diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..4cba10eb --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "tinygrad"] + path = tinygrad + url = ../../tinygrad/tinygrad +[submodule "tinyturing"] + path = tinyturing + url = ../../tinygrad/tinyturing diff --git a/build/in-chroot.sh b/build/in-chroot.sh index 971fc453..27f3deb9 100755 --- a/build/in-chroot.sh +++ b/build/in-chroot.sh @@ -25,6 +25,9 @@ if [[ -n "$TINYBOX_DEV" ]]; then popd fi +# сheckout the tinygrad revision +git -C /opt/tinybox submodule update --init --recursive + # merge /opt/tinybox/userspace into / rsync -ah --info=progress2 /opt/tinybox/userspace/ / chown -R tiny:tiny /home/tiny/ diff --git a/service/autoupdate-tinybox.sh b/service/autoupdate-tinybox.sh index 4178dcda..22a2be66 100644 --- a/service/autoupdate-tinybox.sh +++ b/service/autoupdate-tinybox.sh @@ -29,6 +29,9 @@ fi # reset hard to origin/ in case pull failed to merge in changes git reset --hard "origin/$current_branch" +# checkout the tinygrad revision +git submodule update --init --recursive --force + # check current update stage and see if there are any stages to be run if [ -f /etc/tinybox-update-stage ]; then CURRENT_STAGE=$(cat /etc/tinybox-update-stage) diff --git a/tinygrad/.github/actions/process-replay/action.yml b/tinygrad/.github/actions/process-replay/action.yml deleted file mode 100644 index efd2e1fc..00000000 --- a/tinygrad/.github/actions/process-replay/action.yml +++ /dev/null @@ -1,15 +0,0 @@ -name: Run process replay tests -description: Verify process replay compared to master -runs: - using: "composite" - steps: - - name: Run process replay tests - shell: bash - run: | - export PR_TITLE=$(jq -r .pull_request.title "$GITHUB_EVENT_PATH") - export CURRENT_SHA=${{ github.event.pull_request && github.event.pull_request.head.sha || github.sha }} - git fetch origin $CURRENT_SHA - export COMMIT_MESSAGE=$(git show -s --format=%B "$CURRENT_SHA") - export CURRENT_HEAD=$(git rev-parse HEAD) - cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && IGNORE_OOB=1 PYTHONPATH=. python3 process_replay.py - git checkout $CURRENT_HEAD # restore to branch diff --git a/tinygrad/.github/actions/setup-tinygrad/action.yml b/tinygrad/.github/actions/setup-tinygrad/action.yml deleted file mode 100644 index 9e640031..00000000 --- a/tinygrad/.github/actions/setup-tinygrad/action.yml +++ /dev/null @@ -1,249 +0,0 @@ -name: Setup Python & Install -description: Sets up Python and installs project dependencies. -inputs: - python-version: - description: 'Python version to use' - required: false - default: '3.12' - key: - description: 'Key for the python cache' - required: false - default: '' # if you don't set a key, it doesn't cache - deps: - description: 'Extra dependency groups (comma separated)' - required: false - default: '' - pydeps: - description: 'Extra Python dependency groups (space separated)' - required: false - default: '' - opencl: - description: "Install OpenCL?" - required: false - default: 'false' - amd: - description: "Install AMD?" - required: false - default: 'false' - cuda: - description: "Install CUDA?" - required: false - default: 'false' - webgpu: - description: "Install webgpu?" - required: false - default: 'false' - llvm: - description: "Install LLVM?" - required: false - default: 'false' -runs: - using: "composite" - steps: - - name: Set up Python ${{ inputs.python-version }} - id: setup-python - uses: actions/setup-python@v5 - with: - python-version: ${{ inputs.python-version }} - - # **** Caching packages **** - - - name: Cache Python packages - id: restore-venv - uses: actions/cache@v4 - with: - path: ${{ github.workspace }}/.venv - key: venv-${{ runner.os }}-python-${{ steps.setup-python.outputs.python-version }}-${{ inputs.deps }}-${{ inputs.pydeps }}-${{ hashFiles('**/setup.py') }}-${{ env.PYTHON_CACHE_VERSION }} - - # **** Caching downloads **** - - - name: Cache downloads (Linux) - if: inputs.key != '' && runner.os == 'Linux' - uses: actions/cache@v4 - with: - path: ~/.cache/tinygrad/downloads/ - key: downloads-cache-${{ inputs.key }}-${{ env.DOWNLOAD_CACHE_VERSION }} - - name: Cache downloads (macOS) - if: inputs.key != '' && runner.os == 'macOS' - uses: actions/cache@v4 - with: - path: ~/Library/Caches/tinygrad/downloads/ - key: osx-downloads-cache-${{ inputs.key }}-${{ env.DOWNLOAD_CACHE_VERSION }} - - # **** Python deps **** - - - name: Install dependencies in venv (with extra) - if: inputs.deps != '' && steps.restore-venv.outputs.cache-hit != 'true' - shell: bash - run: | - python -m venv .venv - if [[ "$RUNNER_OS" == "Windows" ]]; then - source .venv/Scripts/activate - else - . .venv/bin/activate - fi - python -m pip install -e ".[${{ inputs.deps }}]" ${{ inputs.pydeps }} --extra-index-url https://download.pytorch.org/whl/cpu --extra-index-url https://aiinfra.pkgs.visualstudio.com/PublicPackages/_packaging/Triton-Nightly/pypi/simple/ - - name: Install dependencies in venv (without extra) - if: inputs.deps == '' && steps.restore-venv.outputs.cache-hit != 'true' - shell: bash - run: | - python -m venv .venv - if [[ "$RUNNER_OS" == "Windows" ]]; then - source .venv/Scripts/activate - else - . .venv/bin/activate - fi - python -m pip install -e . ${{ inputs.pydeps }} - - name: Set up venv environment - shell: bash - run: | - echo "VIRTUAL_ENV=${{ github.workspace }}/.venv" >> "$GITHUB_ENV" - echo "OMP_NUM_THREADS=1" >> "$GITHUB_ENV" - # no buffers should be over 300MB in CI - echo "MAX_BUFFER_SIZE=300000000" >> "$GITHUB_ENV" - if [[ "$RUNNER_OS" == "Windows" ]]; then - echo "${{ github.workspace }}/.venv/Scripts" >> "$GITHUB_PATH" - else - echo "${{ github.workspace }}/.venv/bin" >> "$GITHUB_PATH" - fi - - # ******************* apt ******************* - - - name: Add OpenCL Repo - if: inputs.opencl == 'true' && runner.os == 'Linux' - shell: bash - run: echo "deb [ allow-insecure=yes ] https://apt.repos.intel.com/oneapi all main" | sudo tee /etc/apt/sources.list.d/oneAPI.list - - - name: Add AMD Repo (Linux) - if: inputs.amd == 'true' && runner.os == 'Linux' - shell: bash - run: | - wget https://repo.radeon.com/rocm/rocm.gpg.key -O - | gpg --dearmor | sudo tee /etc/apt/keyrings/rocm.gpg > /dev/null - sudo tee /etc/apt/sources.list.d/rocm.list <> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: python3.11 test/external/process_replay/reset.py - - name: Run Stable Diffusion - run: BENCHMARK_LOG=stable_diffusion JIT=1 python3.11 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt - - name: Run Stable Diffusion without fp16 - run: BENCHMARK_LOG=stable_diffusion_fp32 JIT=1 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing | tee sd_no_fp16.txt - - name: Run Stable Diffusion v2 - run: BENCHMARK_LOG=stable_diffusion_v2 JIT=1 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing | tee sdv2.txt - # process replay can't capture this, the graph is too large - - name: Run SDXL - run: BENCHMARK_LOG=stable_diffusion_xl CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt - - name: Run model inference benchmark - run: METAL=1 python3.11 test/external/external_model_benchmark.py - - name: Run huggingface_onnx test - run: METAL=1 python3.11 extra/huggingface_onnx/run_models.py test --debug FacebookAI/xlm-roberta-large - - name: Test speed vs torch - run: BIG=2 MPS=1 python3.11 test/test_speed_v_torch.py | tee torch_speed.txt - - name: Test tensor cores - run: METAL=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Test AMX tensor cores - run: | - DEBUG=2 CPU=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - DEBUG=2 LLVM=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Run Tensor Core GEMM (float) - run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py | tee matmul.txt - - name: Run Tensor Core GEMM (half) - run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_half.txt - - name: Run Tensor Core GEMM (bfloat16) - run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt - - name: Fuzz Padded Tensor Core GEMM - run: METAL=1 M_START=6 M_STOP=10 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=6 K_STOP=24 K_STEP=1 TC_OPT=2 DEBUG=2 python3.11 ./extra/gemm/fuzz_matmul.py - - name: Run LLaMA - run: | - BENCHMARK_LOG=llama_nojit JIT=0 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt - BENCHMARK_LOG=llama JIT=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt - - name: Run LLaMA with BEAM - run: BENCHMARK_LOG=llama_beam JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt - - name: Run quantized LLaMA - run: | - BENCHMARK_LOG=llama_int8 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8 | tee llama_int8.txt - BENCHMARK_LOG=llama_nf4 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4 | tee llama_nf4.txt - - name: Run quantized LLaMA3 - run: | - BENCHMARK_LOG=llama3_int8 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8 | tee llama3_int8.txt - BENCHMARK_LOG=llama3_nf4 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4 | tee llama3_nf4.txt - #- name: Run LLaMA 7B on 4 (virtual) GPUs - # run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_four_gpu.txt - - name: Run GPT2 - run: | - BENCHMARK_LOG=gpt2_nojit JIT=0 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt - BENCHMARK_LOG=gpt2 JIT=1 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt - - name: Run GPT2 w HALF - run: BENCHMARK_LOG=gpt2_half HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt - - name: Run GPT2 w HALF/BEAM - run: BENCHMARK_LOG=gpt2_half_beam HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt - - name: Run OLMoE - run: BENCHMARK_LOG=olmoe python3.11 examples/olmoe.py - - name: Train MNIST - run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py | tee beautiful_mnist.txt - - name: Run 10 CIFAR training steps - run: BENCHMARK_LOG=cifar_10steps JIT=1 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar.txt - - name: Run 10 CIFAR training steps w HALF - run: BENCHMARK_LOG=cifar_10steps_half JIT=2 STEPS=10 DEFAULT_FLOAT=HALF python3.11 examples/hlb_cifar10.py | tee train_cifar_half.txt - #- name: Run 10 CIFAR training steps w BF16 - # run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py | tee train_cifar_bf16.txt - - name: Run 10 CIFAR training steps w winograd - run: BENCHMARK_LOG=cifar_10steps_wino JIT=1 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar_wino.txt - - name: UsbGPU boot time - run: sudo -E PYTHONPATH=. DEBUG=2 AM_RESET=1 AMD=1 AMD_IFACE=USB time python3.11 test/test_tiny.py TestTiny.test_plus - - name: UsbGPU tiny tests - run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB python3.11 test/test_tiny.py - - name: UsbGPU copy speeds - run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB python3.11 test/external/external_test_usb_asm24.py TestDevCopySpeeds - - name: UsbGPU openpilot test - run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB AMD_LLVM=1 NOLOCALS=0 IMAGE=0 GRAPH_ONE_KERNEL=1 python3.11 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx - - uses: actions/upload-artifact@v4 - with: - name: Speed (Mac) - path: | - onnx_inference_speed.csv - torch_speed.txt - llama_unjitted.txt - llama_jitted.txt - llama_beam.txt - llama_int8.txt - llama_nf4.txt - llama3_int8.txt - llama3_nf4.txt - llama_four_gpu.txt - gpt2_unjitted.txt - gpt2_jitted.txt - gpt2_half.txt - gpt2_half_beam.txt - matmul.txt - matmul_half.txt - matmul_bfloat16.txt - sd.txt - sd_no_fp16.txt - sdv2.txt - sdxl.txt - beautiful_mnist.txt - train_cifar.txt - train_cifar_half.txt - train_cifar_bf16.txt - train_cifar_wino.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3.11 process_replay.py - - testnvidiabenchmark: - name: tinybox green Benchmark - runs-on: [self-hosted, Linux, tinyboxgreen] - timeout-minutes: 30 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Print nvidia-smi - run: nvidia-smi - - name: Symlink models and datasets - run: | - mkdir -p weights - ln -s ~/tinygrad/weights/LLaMA weights/LLaMA - ln -s /raid/weights/mixtral-8x7b-32kseqlen weights/mixtral-8x7b-32kseqlen - ln -s /raid/weights/LLaMA-2 weights/LLaMA-2 - ln -s /raid/weights/LLaMA-3 weights/LLaMA-3 - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - - name: Run model inference benchmark - run: NV=1 CAPTURE_PROCESS_REPLAY=0 NOCLANG=1 python3 test/external/external_model_benchmark.py - - name: Test speed vs torch - run: NV=1 CAPTURE_PROCESS_REPLAY=0 HALF=1 BIG=2 TORCHCUDA=1 python3 test/test_speed_v_torch.py | tee torch_speed.txt - - name: Test speed vs theoretical - run: NV=1 IGNORE_BEAM_CACHE=1 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20 - - name: Test benchmark allreduce - run: NV=1 python test/external/external_benchmark_multitensor_allreduce.py - - name: Test tensor cores - run: | - NV=1 ALLOW_TF32=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - PTX=1 ALLOW_TF32=1 NV=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Run Tensor Core GEMM (CUDA) - run: | - CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul.txt - CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt - CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_tf32.txt - - name: Run Tensor Core GEMM (PTX) - run: NV=1 PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_ptx.txt - - name: Run Tensor Core GEMM (NV) - run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_nv.txt - - name: Test NV=1 - run: DEBUG=2 NV=1 python -m pytest -rA test/test_tiny.py - - name: Test CUDA=1 - run: DEBUG=2 CUDA=1 python -m pytest -rA test/test_tiny.py - - name: Run Stable Diffusion - run: BENCHMARK_LOG=stable_diffusion NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt - - name: Run SDXL - run: BENCHMARK_LOG=stable_diffusion_xl CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt - - name: Run LLaMA - run: | - BENCHMARK_LOG=llama_nojit NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt - BENCHMARK_LOG=llama NV=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt - - name: Run LLaMA with BEAM - run: BENCHMARK_LOG=llama_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt - # - name: Run LLaMA 7B on 4 GPUs - # run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_four_gpu.txt - # - name: Run LLaMA 7B on 6 GPUs - # run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_six_gpu.txt - - name: Run LLaMA-3 8B BEAM - run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt - - name: Run LLaMA-3 8B on 4 GPUs with BEAM - run: BENCHMARK_LOG=llama3_beam_4gpu NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt - # - name: Run LLaMA-3 8B on 6 GPUs - # run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt - # - name: Run LLaMA-2 70B - # run: NV=1 CAPTURE_PROCESS_REPLAY=0 MAX_CONTEXT=256 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_2_70B.txt - - name: Run Mixtral 8x7B - run: time BENCHMARK_LOG=mixtral NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt - - name: Run GPT2 - run: | - BENCHMARK_LOG=gpt2_nojit NV=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt - BENCHMARK_LOG=gpt2 NV=1 JIT=1 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt - - name: Run GPT2 w HALF - run: BENCHMARK_LOG=gpt2_half NV=1 HALF=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt - - name: Run GPT2 w HALF/BEAM - run: BENCHMARK_LOG=gpt2_half_beam NV=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt - - uses: actions/upload-artifact@v4 - with: - name: Speed (NVIDIA) - path: | - onnx_inference_speed.csv - torch_speed.txt - matmul.txt - matmul_bfloat16.txt - matmul_tf32.txt - matmul_ptx.txt - matmul_nv.txt - sd.txt - sdxl.txt - llama_unjitted.txt - llama_jitted.txt - llama_beam.txt - llama3_beam.txt - llama3_four_gpu.txt - llama3_six_gpu.txt - llama_2_70B.txt - mixtral.txt - gpt2_unjitted.txt - gpt2_jitted.txt - gpt2_half.txt - gpt2_half_beam.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - testmorenvidiabenchmark: - name: tinybox green Training Benchmark - runs-on: [self-hosted, Linux, tinyboxgreen] - timeout-minutes: 20 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Symlink models and datasets - run: | - mkdir -p weights - ln -s ~/tinygrad/weights/bpe_simple_vocab_16e6.txt.gz weights/bpe_simple_vocab_16e6.txt.gz - ln -s ~/tinygrad/weights/LLaMA weights/LLaMA - ln -s ~/tinygrad/extra/datasets/cifar-10-python.tar.gz extra/datasets/cifar-10-python.tar.gz - ln -s /raid/weights/mixtral-8x7b-32kseqlen weights/mixtral-8x7b-32kseqlen - ln -s /raid/weights/LLaMA-2 weights/LLaMA-2 - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - - name: Fuzz Padded Tensor Core GEMM (NV) - run: NV=1 M_START=12 M_STOP=20 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 python3 ./extra/gemm/fuzz_matmul.py - - name: Fuzz Padded Tensor Core GEMM (PTX) - run: NV=1 PTX=1 M_START=12 M_STOP=20 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 python3 ./extra/gemm/fuzz_matmul.py - - name: Train MNIST - run: time PYTHONPATH=. NV=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt - - name: Run 10 CIFAR training steps - run: BENCHMARK_LOG=cifar_10steps NV=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt - - name: Run 10 CIFAR training steps w HALF - run: BENCHMARK_LOG=cifar_10steps_half NV=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt - - name: Run 10 CIFAR training steps w BF16 - run: BENCHMARK_LOG=cifar_10steps_bf16 NV=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt - - name: Run 10 CIFAR training steps w winograd - run: BENCHMARK_LOG=cifar_10steps_half_wino NV=1 CAPTURE_PROCESS_REPLAY=0 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt - - name: Run full CIFAR training w 1 GPU - run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF LATEWINO=1 STEPS=1000 TARGET_EVAL_ACC_PCT=93.2 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt - - name: Run full CIFAR training steps w 6 GPUS - run: time BENCHMARK_LOG=cifar_6gpu CAPTURE_PROCESS_REPLAY=0 NV=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.2 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt - - name: Run MLPerf resnet eval on training data - run: time BENCHMARK_LOG=resnet_eval NV=1 MODEL=resnet python3 examples/mlperf/model_eval.py - - name: Run 10 MLPerf ResNet50 training steps (1 gpu) - run: BENCHMARK_LOG=resnet_10steps NV=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt - - name: Run 10 MLPerf ResNet50 training steps (6 gpu) - run: BENCHMARK_LOG=resnet_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt - - name: Run 10 MLPerf Bert training steps (6 gpu) - # TODO: remove BERT_LAYERS once scheduler is fast - run: BENCHMARK_LOG=bert_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt - - uses: actions/upload-artifact@v4 - with: - name: Speed (NVIDIA Training) - path: | - beautiful_mnist.txt - train_cifar.txt - train_cifar_half.txt - train_cifar_bf16.txt - train_cifar_wino.txt - train_cifar_one_gpu.txt - train_cifar_six_gpu.txt - train_resnet.txt - train_resnet_one_gpu.txt - train_bert.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - testamdbenchmark: - name: tinybox red Benchmark - runs-on: [self-hosted, Linux, tinybox] - timeout-minutes: 20 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Remove amdgpu - run: sudo rmmod amdgpu || true - - name: Cleanup running AM processes - run: python extra/amdpci/am_smi.py --pids --kill - #- name: Insert amdgpu - # run: sudo modprobe amdgpu - - name: Symlink models and datasets - run: | - mkdir -p weights - ln -s ~/tinygrad/weights/bpe_simple_vocab_16e6.txt.gz weights/bpe_simple_vocab_16e6.txt.gz - ln -s ~/tinygrad/weights/LLaMA weights/LLaMA - ln -s ~/tinygrad/extra/datasets/cifar-10-python.tar.gz extra/datasets/cifar-10-python.tar.gz - ln -s /raid/weights/mixtral-8x7b-32kseqlen weights/mixtral-8x7b-32kseqlen - ln -s /raid/weights/LLaMA-2 weights/LLaMA-2 - ln -s /raid/weights/LLaMA-3 weights/LLaMA-3 - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - #- name: setup perflevel - # run: | - # examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh - # rocm-smi - #- name: Show off tinybox - # run: /opt/rocm/bin/rocm-bandwidth-test - # TODO: unstable on AMD - #- name: Run model inference benchmark - # run: LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 NOCLANG=1 python3 test/external/external_model_benchmark.py - # TODO: unstable on AMD - #- name: Test speed vs torch - # run: | - # python3 -c "import torch; print(torch.__version__)" - # LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 BIG=2 TORCHCUDA=1 python3 test/test_speed_v_torch.py | tee torch_speed.txt - - name: Test speed vs theoretical - run: AMD=1 IGNORE_BEAM_CACHE=1 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20 - - name: Test tensor cores - run: | - AMD=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops - AMD=1 AMD_LLVM=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops - AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py - - name: Run Tensor Core GEMM (AMD) - run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_amd.txt - - name: Test AMD=1 - run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py - #- name: Test HIP=1 - # run: DEBUG=2 HIP=1 python -m pytest -rA test/test_tiny.py - # TODO: AMD compiler bug causes this to fail - #- name: Fuzz Padded Tensor Core GEMM - # run: HSA=1 M_START=12 M_STOP=20 M_STEP=1 N_START=12 N_STOP=20 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 DEBUG=2 python3 ./extra/gemm/fuzz_matmul.py - #- name: Remove amdgpu - # run: sleep 10 && sudo rmmod amdgpu # sleep a bit to let the driver unload the prev pid. - - name: Test AM cold start time - run: time AMD=1 AM_RESET=1 python3 test/test_tiny.py TestTiny.test_plus - - name: Test AM warm start time - run: time AMD=1 python3 test/test_tiny.py TestTiny.test_plus - - name: Run Stable Diffusion - run: BENCHMARK_LOG=stable_diffusion AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt - - name: Run SDXL - run: BENCHMARK_LOG=stable_diffusion_xl CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt - - name: Run LLaMA 7B - run: | - BENCHMARK_LOG=llama_nojit AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt - BENCHMARK_LOG=llama AMD=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt - - name: Run LLaMA 7B with BEAM - run: BENCHMARK_LOG=llama_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt - # - name: Run LLaMA 7B on 4 GPUs - # run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_four_gpu.txt - # - name: Run LLaMA 7B on 6 GPUs - # run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_six_gpu.txt - - name: Run LLaMA-3 8B BEAM - run: BENCHMARK_LOG=llama3_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt - - name: Run LLaMA-3 8B on 4 GPUs with BEAM - run: BENCHMARK_LOG=llama3_beam_4gpu AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt - # - name: Run LLaMA-3 8B on 6 GPUs - # run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt - #- name: Restore amdgpu - # run: sudo modprobe amdgpu - # - name: Run LLaMA-2 70B - # run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_2_70B.txt - - name: Run Mixtral 8x7B - run: time BENCHMARK_LOG=mixtral AMD=1 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt - - name: Run GPT2 - run: | - BENCHMARK_LOG=gpt2_nojit AMD=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt - BENCHMARK_LOG=gpt2 AMD=1 JIT=1 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt - - name: Run GPT2 w HALF - run: BENCHMARK_LOG=gpt2_half AMD=1 HALF=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt - - name: Run GPT2 w HALF/BEAM - run: BENCHMARK_LOG=gpt2_half_beam AMD=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt - - uses: actions/upload-artifact@v4 - with: - name: Speed (AMD) - path: | - onnx_inference_speed.csv - torch_speed.txt - llama_unjitted.txt - llama_jitted.txt - llama_beam.txt - llama3_beam.txt - llama3_four_gpu.txt - llama3_six_gpu.txt - llama_2_70B.txt - gpt2_unjitted.txt - gpt2_jitted.txt - gpt2_half.txt - gpt2_half_beam.txt - matmul.txt - matmul_amd.txt - sd.txt - sdxl.txt - mixtral.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - testmoreamdbenchmark: - name: tinybox red Training Benchmark - runs-on: [self-hosted, Linux, tinybox] - timeout-minutes: 30 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Remove amdgpu - run: sudo rmmod amdgpu || true - - name: Cleanup running AM processes - run: python extra/amdpci/am_smi.py --pids --kill - - name: Symlink models and datasets - run: | - mkdir -p weights - ln -s ~/tinygrad/weights/bpe_simple_vocab_16e6.txt.gz weights/bpe_simple_vocab_16e6.txt.gz - ln -s ~/tinygrad/weights/LLaMA weights/LLaMA - ln -s ~/tinygrad/extra/datasets/cifar-10-python.tar.gz extra/datasets/cifar-10-python.tar.gz - ln -s /raid/weights/mixtral-8x7b-32kseqlen weights/mixtral-8x7b-32kseqlen - ln -s /raid/weights/LLaMA-2 weights/LLaMA-2 - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - - name: Train MNIST - run: time PYTHONPATH=. AMD=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt - - name: Run 10 CIFAR training steps - run: BENCHMARK_LOG=cifar_10steps AMD=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt - - name: Run 10 CIFAR training steps w HALF - run: BENCHMARK_LOG=cifar_10steps_half AMD=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt - - name: Run 10 CIFAR training steps w BF16 - run: BENCHMARK_LOG=cifar_10steps_bf16 AMD=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt - - name: Run 10 CIFAR training steps w winograd - run: BENCHMARK_LOG=cifar_10steps_half_wino AMD=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt - - name: Run full CIFAR training w 1 GPU - run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF LATEWINO=1 STEPS=1000 TARGET_EVAL_ACC_PCT=93.2 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt - - name: Run full CIFAR training steps w 6 GPUS - run: time BENCHMARK_LOG=cifar_6gpu AMD=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.2 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt - - name: Run full CIFAR training steps w 6 GPUS (REMOTE) - run: time BENCHMARK_LOG=cifar_6gpu_remote REMOTE=1 REMOTEDEV=AMD DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.2 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu_remote.txt - - uses: actions/upload-artifact@v4 - with: - name: Speed (AMD Training) - path: | - beautiful_mnist.txt - train_cifar.txt - train_cifar_half.txt - train_cifar_bf16.txt - train_cifar_wino.txt - train_cifar_one_gpu.txt - train_cifar_six_gpu.txt - train_cifar_six_gpu_remote.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - testmlperfamdbenchmark: - name: tinybox red MLPerf Benchmark - runs-on: [self-hosted, Linux, tinybox] - timeout-minutes: 30 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Remove amdgpu - run: sudo rmmod amdgpu || true - - name: Cleanup running AM processes - run: python extra/amdpci/am_smi.py --pids --kill - - name: Symlink models and datasets - run: | - mkdir -p weights - ln -s ~/tinygrad/weights/bpe_simple_vocab_16e6.txt.gz weights/bpe_simple_vocab_16e6.txt.gz - ln -s ~/tinygrad/weights/LLaMA weights/LLaMA - ln -s ~/tinygrad/extra/datasets/cifar-10-python.tar.gz extra/datasets/cifar-10-python.tar.gz - ln -s /raid/weights/mixtral-8x7b-32kseqlen weights/mixtral-8x7b-32kseqlen - ln -s /raid/weights/LLaMA-2 weights/LLaMA-2 - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - - name: Run MLPerf resnet eval - run: time BENCHMARK_LOG=resnet_eval AMD=1 MODEL=resnet python3 examples/mlperf/model_eval.py - - name: Run 10 MLPerf ResNet50 training steps (1 gpu) - run: BENCHMARK_LOG=resnet_10steps AMD=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt - - name: Run 10 MLPerf ResNet50 training steps (6 gpu) - run: BENCHMARK_LOG=resnet_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt - - name: Run 10 MLPerf Bert training steps (6 gpu) - # TODO: remove BERT_LAYERS once scheduler is fast - run: BENCHMARK_LOG=bert_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt - - uses: actions/upload-artifact@v4 - with: - name: Speed (AMD MLPerf) - path: | - train_resnet.txt - train_resnet_one_gpu.txt - train_bert.txt - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - testqualcommbenchmark: - name: comma Benchmark - runs-on: [self-hosted, Linux, comma] - timeout-minutes: 20 - defaults: - run: - shell: bash -e -o pipefail {0} - if: github.repository_owner == 'tinygrad' - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: setup staging db - if: github.ref == 'refs/heads/update_benchmark_staging' - run: | - echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV - rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal - - name: reset process replay - run: test/external/process_replay/reset.py - - name: validate openpilot 0.9.7 - run: PYTHONPATH=. FLOAT16=0 IMAGE=2 QCOM=1 taskset -c 4-7 python3 test/external/external_benchmark_openpilot.py https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx | tee openpilot_image_0_9_7.txt - - name: benchmark openpilot 0.9.4 - run: BENCHMARK_LOG=openpilot_0_9_4 PYTHONPATH=. QCOM=1 taskset -c 4-7 python3 test/external/external_benchmark_openpilot.py https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx | tee openpilot_0_9_4.txt - - name: benchmark openpilot 0.9.7 - run: BENCHMARK_LOG=openpilot_0_9_7 PYTHONPATH=. QCOM=1 taskset -c 4-7 python3 test/external/external_benchmark_openpilot.py https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx | tee openpilot_0_9_7.txt - - name: benchmark openpilot w IMAGE=2 0.9.4 - run: BENCHMARK_LOG=openpilot_0_9_4_image PYTHONPATH=. NOLOCALS=1 FLOAT16=1 IMAGE=2 QCOM=1 taskset -c 4-7 python3 test/external/external_benchmark_openpilot.py https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx | tee openpilot_image_0_9_4.txt - - name: benchmark openpilot w IMAGE=2 0.9.7 - run: BENCHMARK_LOG=openpilot_0_9_7_image PYTHONPATH=. NOLOCALS=1 FLOAT16=1 IMAGE=2 QCOM=1 taskset -c 4-7 python3 test/external/external_benchmark_openpilot.py https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx | tee openpilot_image_0_9_7.txt - - name: openpilot compile3 0.9.7 - run: PYTHONPATH="." QCOM=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx - - name: openpilot compile3 0.9.7+ tomb raider - run: PYTHONPATH="." QCOM=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/e8bea2c78ffa92685ece511e9b554122aaf1a79d/selfdrive/modeld/models/supercombo.onnx - - name: openpilot dmonitoring compile3 0.9.7 - run: PYTHONPATH="." QCOM=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/dmonitoring_model.onnx - - name: benchmark MobileNetV2 on DSP - run: | - # generate quantized weights - ln -s /data/home/tiny/tinygrad/extra/datasets/imagenet extra/datasets/imagenet - ln -s /data/home/tiny/tinygrad/testsig-*.so . - PYTHONPATH=. CC=clang-19 CPU=1 QUANT=1 CNT=0 python3 examples/test_onnx_imagenet.py https://github.com/xamcat/mobcat-samples/raw/refs/heads/master/onnx_runtime/InferencingSample/InferencingSample/mobilenetv2-7.onnx /tmp/model.quant.onnx - # benchmark on DSP with NOOPT=1, the devectorizer has issues - PYTHONPATH=. CC=clang-19 DSP=1 DONT_REALIZE_EXPAND=1 NOOPT=1 CNT=2 DEBUG=2 python3 examples/test_onnx_imagenet.py /tmp/model.quant.onnx - - name: Run process replay tests - run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py - - uses: actions/upload-artifact@v4 - with: - name: Speed (comma) - path: | - openpilot_compile_0_9_4.txt - openpilot_compile_0_9_7.txt - openpilot_0_9_4.txt - openpilot_0_9_7.txt - openpilot_image_0_9_4.txt - openpilot_image_0_9_7.txt diff --git a/tinygrad/.github/workflows/benchmark_search.yml b/tinygrad/.github/workflows/benchmark_search.yml deleted file mode 100644 index 670fa644..00000000 --- a/tinygrad/.github/workflows/benchmark_search.yml +++ /dev/null @@ -1,32 +0,0 @@ -name: Benchmark with kernel search - -on: - push: - branches: - - update_benchmark_search - workflow_dispatch: - -jobs: - run_script_job: - runs-on: [self-hosted, Linux, tinybox] - if: github.repository_owner == 'tinygrad' - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Remove amdgpu - run: sudo rmmod amdgpu || true - - name: Cleanup running AM processes - run: python extra/amdpci/am_smi.py --pids --kill - - name: Run SDXL with new search - run: | - BENCHMARK_LOG=search_sdxl PYTHONPATH=. AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 DISABLE_COMPILER_CACHE=1 python examples/sdxl.py --noshow --timing --seed 0 - - name: Run SDXL with cached search - run: | - BENCHMARK_LOG=search_sdxl_cached PYTHONPATH=. AMD=1 JITBEAM=2 python examples/sdxl.py --noshow --timing --seed 0 - - name: Run winograd cifar with new search - run: | - BENCHMARK_LOG=search_wino_cifar WINO=1 DEFAULT_FLOAT=HALF FUSE_ARANGE=1 JITBEAM=4 IGNORE_BEAM_CACHE=1 DISABLE_COMPILER_CACHE=1 BS=1024 STEPS=500 python examples/hlb_cifar10.py - - name: Run winograd cifar with cached search - run: | - BENCHMARK_LOG=search_wino_cifar_cached WINO=1 DEFAULT_FLOAT=HALF FUSE_ARANGE=1 JITBEAM=4 BS=1024 STEPS=500 python examples/hlb_cifar10.py diff --git a/tinygrad/.github/workflows/docs.yml b/tinygrad/.github/workflows/docs.yml deleted file mode 100644 index def8b316..00000000 --- a/tinygrad/.github/workflows/docs.yml +++ /dev/null @@ -1,30 +0,0 @@ -name: Deploy Docs -on: - push: - branches: - - master - - mkdocs -permissions: - contents: write -jobs: - deploy: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - name: Configure Git Credentials - run: | - git config user.name github-actions[bot] - git config user.email 41898282+github-actions[bot]@users.noreply.github.com - - uses: actions/setup-python@v5 - with: - python-version: 3.x - - run: echo "cache_id=$(date --utc '+%V')" >> $GITHUB_ENV - - uses: actions/cache@v4 - with: - key: mkdocs-material-${{ env.cache_id }} - path: .cache - restore-keys: | - mkdocs-material- - - run: pip install -e .[docs] - - run: mkdocs build --strict - - run: mkdocs gh-deploy --force \ No newline at end of file diff --git a/tinygrad/.github/workflows/mlperf.yml b/tinygrad/.github/workflows/mlperf.yml deleted file mode 100644 index 66f09fd8..00000000 --- a/tinygrad/.github/workflows/mlperf.yml +++ /dev/null @@ -1,29 +0,0 @@ -name: Run MLPerf Training - -on: - schedule: - - cron: '5 8 * * *' # Runs at 08:05 UTC (12:05 AM Pacific Time) - push: - branches: - - update_mlperf - workflow_dispatch: - -jobs: - run_script_job: - runs-on: [self-hosted, Linux, tinybox] - if: github.repository_owner == 'tinygrad' - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Cleanup running AM processes - run: python extra/amdpci/am_smi.py --pids --kill - - name: Symlink datasets - run: | - mkdir -p extra/datasets - ln -s /raid/datasets/imagenet extra/datasets/imagenet - - name: Run resnet - run: | - rm "~/.cache/tinygrad/cache_mlperf.db" || true - BENCHMARK_LOG=mlpert_train_resnet LOGMLPERF=0 CACHEDB="~/.cache/tinygrad/cache_mlperf.db" examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh - rm "~/.cache/tinygrad/cache_mlperf.db" \ No newline at end of file diff --git a/tinygrad/.github/workflows/python-publish.yml b/tinygrad/.github/workflows/python-publish.yml deleted file mode 100644 index 22f36f23..00000000 --- a/tinygrad/.github/workflows/python-publish.yml +++ /dev/null @@ -1,30 +0,0 @@ -# This workflows will upload a Python Package using Twine when a release is created -# For more information see: https://help.github.com/en/actions/language-and-framework-guides/using-python-with-github-actions#publishing-to-package-registries - -name: Upload Python Package - -on: - release: - types: [published] - workflow_dispatch: - -jobs: - deploy: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - name: Set up Python - uses: actions/setup-python@v2 - with: - python-version: '3.x' - - name: Install dependencies - run: | - python -m pip install --upgrade pip - pip install setuptools wheel twine - - name: Build and publish - env: - TWINE_USERNAME: ${{ secrets.PYPI_USERNAME }} - TWINE_PASSWORD: ${{ secrets.PYPI_PASSWORD }} - run: | - python setup.py sdist bdist_wheel - twine upload dist/* diff --git a/tinygrad/.github/workflows/szdiff.yml b/tinygrad/.github/workflows/szdiff.yml deleted file mode 100644 index 4222ef31..00000000 --- a/tinygrad/.github/workflows/szdiff.yml +++ /dev/null @@ -1,98 +0,0 @@ -name: Check Line Counts -on: - pull_request_target: - -# Cancel the workflow in progress in newer build is about to start. -concurrency: - group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }} - cancel-in-progress: true - -jobs: - checkbranch: - name: Check PR Branch status - runs-on: ubuntu-latest - outputs: - branchstat: ${{ steps.brstat.outputs.stat}} - steps: - - name: Check code from PR branch - uses: actions/checkout@v4 - with: - repository: ${{ github.event.pull_request.head.repo.full_name }} - ref: ${{ github.event.pull_request.head.sha }} - fetch-depth: 0 - - name: Check whether branch is up-to-date - id: brstat - run: | - git remote add tinygrad https://github.com/tinygrad/tinygrad - git fetch tinygrad master - echo "${{ github.event.pull_request.head.sha }}" - git rev-list --left-right --count tinygrad/master...${{ github.event.pull_request.head.sha }} | awk '{print "Behind "$1" - Ahead "$2""}' - count=$(git rev-list --left-right --count tinygrad/master...${{ github.event.pull_request.head.sha }} | awk '{print $1}') - if [ $count -gt 0 ] - then - echo "Current branch is behind tinygrad master branch!" - echo "stat=true" >> "$GITHUB_OUTPUT" - else - echo "stat=false" >> "$GITHUB_OUTPUT" - fi - - szdiff: - name: Core Library Line Difference - permissions: - contents: read - pull-requests: write - runs-on: ubuntu-latest - needs: checkbranch - if: needs.checkbranch.outputs.branchstat == 'false' - steps: - - name: Checkout code from PR branch - uses: actions/checkout@v4 - with: - repository: ${{ github.event.pull_request.head.repo.full_name }} - ref: ${{ github.event.pull_request.head.sha }} - path: pr - # the base default to tinygrad master and cannot be other fork branch for security purpose - - name: Checkout code from tinygrad master - uses: actions/checkout@v4 - with: - path: base - - name: Set up Python 3.10 - uses: actions/setup-python@v5 - with: - python-version: '3.10' - - name: Count Line Diff - run: | - pip install tabulate - BASE="$GITHUB_WORKSPACE/base" - PR="$GITHUB_WORKSPACE/pr" - cp "$BASE/sz.py" . - echo "loc_content<> "$GITHUB_ENV" - python sz.py "$BASE" "$PR" >> "$GITHUB_ENV" - echo "EOF" >> "$GITHUB_ENV" - - name: Comment Code Line Diff - continue-on-error: false - uses: marocchino/sticky-pull-request-comment@v2 - with: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - ignore_empty: true - skip_unchanged: true - recreate: true - message: ${{ env.loc_content }} - - rebase: - name: Core Library Line Difference - permissions: - pull-requests: write - runs-on: ubuntu-latest - needs: checkbranch - if: needs.checkbranch.outputs.branchstat == 'true' - steps: - - name: Comment Rebase - continue-on-error: false - uses: marocchino/sticky-pull-request-comment@v2 - with: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - skip_unchanged: true - recreate: true - message: | - This branch currently is behind tinygrad/master. The line count difference bot is disabled. diff --git a/tinygrad/.github/workflows/test.yml b/tinygrad/.github/workflows/test.yml deleted file mode 100644 index f9dfe315..00000000 --- a/tinygrad/.github/workflows/test.yml +++ /dev/null @@ -1,941 +0,0 @@ -name: Unit Tests -env: - # increment this when downloads substantially change to avoid the internet - DOWNLOAD_CACHE_VERSION: '10' - PYTHON_CACHE_VERSION: '2' - CAPTURE_PROCESS_REPLAY: 1 - GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} - -on: - push: - branches: - - master - pull_request: - workflow_dispatch: - -jobs: - llvmspeed: - name: LLVM Speed - runs-on: ubuntu-24.04 - timeout-minutes: 20 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: llvm-speed - deps: testing_minimal - llvm: 'true' - - name: External Benchmark Schedule - run: PYTHONPATH="." python3 test/external/external_benchmark_schedule.py - - name: Speed Test - run: LLVM=1 python3 test/test_speed_v_torch.py - - name: Speed Test (BEAM=2) - run: BEAM=2 LLVM=1 python3 test/test_speed_v_torch.py - - docs: - name: Docs - runs-on: ubuntu-22.04 - timeout-minutes: 10 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - deps: docs - pydeps: "capstone" - - name: Use as an external package - run: | - mkdir $HOME/test_external_dir - cd $HOME/test_external_dir - python -m venv venv - source venv/bin/activate - pip install $GITHUB_WORKSPACE - python -c "from tinygrad.tensor import Tensor; print(Tensor([1,2,3,4,5]))" - pip install mypy - mypy -c "from tinygrad.tensor import Tensor; print(Tensor([1,2,3,4,5]))" - - name: Run beautiful_mnist with tinygrad only - run: | - mkdir $GITHUB_WORKSPACE/test_dir - cd $GITHUB_WORKSPACE/test_dir - python -m venv venv - source venv/bin/activate - pip install $GITHUB_WORKSPACE - cp $GITHUB_WORKSPACE/examples/beautiful_mnist.py . - PYTHONPATH=$GITHUB_WORKSPACE BS=2 STEPS=10 python beautiful_mnist.py - - name: Test Docs Build - run: python -m mkdocs build --strict - - name: Test Docs - run: | - python docs/abstractions2.py - python docs/abstractions3.py - - name: Test Quickstart - run: awk '/```python/{flag=1;next}/```/{flag=0}flag' docs/quickstart.md > quickstart.py && PYTHONPATH=. python quickstart.py - - name: Test DEBUG - run: DEBUG=100 python3 -c "from tinygrad import Tensor; N = 1024; a, b = Tensor.rand(N, N), Tensor.rand(N, N); c = (a.reshape(N, 1, N) * b.T.reshape(1, N, N)).sum(axis=2); print((c.numpy() - (a.numpy() @ b.numpy())).mean())" - - name: Compile EfficientNet to C and test it - run: | - CPU=1 PYTHONPATH="." python examples/compile_efficientnet.py > recognize.c - clang -O2 recognize.c -lm -o recognize - cat test/models/efficientnet/Chicken.jpg | ./recognize | grep cock - - autogen: - name: Autogen - runs-on: ubuntu-24.04 - timeout-minutes: 15 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - opencl: 'true' - amd: 'true' - cuda: 'true' - webgpu: 'true' - llvm: 'true' - - name: Install autogen support packages - run: sudo apt-get install -y --no-install-recommends llvm-14-dev libclang-14-dev - - name: Verify OpenCL autogen - run: | - cp tinygrad/runtime/autogen/opencl.py /tmp/opencl.py.bak - ./autogen_stubs.sh opencl - diff /tmp/opencl.py.bak tinygrad/runtime/autogen/opencl.py - - name: Verify CUDA autogen - run: | - cp tinygrad/runtime/autogen/cuda.py /tmp/cuda.py.bak - cp tinygrad/runtime/autogen/nv_gpu.py /tmp/nv_gpu.py.bak - ./autogen_stubs.sh cuda - ./autogen_stubs.sh nv - diff /tmp/cuda.py.bak tinygrad/runtime/autogen/cuda.py - diff /tmp/nv_gpu.py.bak tinygrad/runtime/autogen/nv_gpu.py - - name: Verify AMD autogen - run: | - cp tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak - cp tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak - cp tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak - cp tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak - cp tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak - ./autogen_stubs.sh hsa - ./autogen_stubs.sh kfd - ./autogen_stubs.sh comgr - ./autogen_stubs.sh amd - ./autogen_stubs.sh sqtt - diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py - diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py - diff /tmp/comgr.py.bak tinygrad/runtime/autogen/comgr.py - diff /tmp/amd_gpu.py.bak tinygrad/runtime/autogen/amd_gpu.py - diff /tmp/sqtt.py.bak tinygrad/runtime/autogen/sqtt.py - - name: Verify Linux autogen - run: | - cp tinygrad/runtime/autogen/libc.py /tmp/libc.py.bak - cp tinygrad/runtime/autogen/io_uring.py /tmp/io_uring.py.bak - ./autogen_stubs.sh libc - ./autogen_stubs.sh io_uring - diff /tmp/libc.py.bak tinygrad/runtime/autogen/libc.py - diff /tmp/io_uring.py.bak tinygrad/runtime/autogen/io_uring.py - - name: Verify WebGPU autogen - run: | - cp tinygrad/runtime/autogen/webgpu.py /tmp/webgpu.py.bak - ./autogen_stubs.sh webgpu - diff /tmp/webgpu.py.bak tinygrad/runtime/autogen/webgpu.py - - name: Verify LLVM autogen - run: | - cp tinygrad/runtime/autogen/llvm.py /tmp/llvm.py.bak - ./autogen_stubs.sh llvm - diff /tmp/llvm.py.bak tinygrad/runtime/autogen/llvm.py - - torchbackend: - name: Torch Backend Tests - runs-on: ubuntu-latest - timeout-minutes: 15 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: torch-backend-pillow-torchvision-et-pt - deps: testing_minimal - pydeps: "pillow torchvision expecttest" - llvm: 'true' - - name: Install ninja - run: | - sudo apt update || true - sudo apt install -y --no-install-recommends ninja-build - - name: Lint with ruff - run: | - pip3 install --upgrade --force-reinstall ruff==0.11.0 - python3 -m ruff check extra/torch_backend/backend.py - - name: Test one op - run: PYTHONPATH=. FORWARD_ONLY=1 TINY_BACKEND=1 python3 test/test_ops.py TestOps.test_add - - name: Test ResNet-18 - run: PYTHONPATH=. DEBUG=2 python3 extra/torch_backend/example.py - - name: My (custom) tests - run: PYTHONPATH=. python3 extra/torch_backend/test.py - - name: Test one op in torch tests - run: PYTHONPATH=. DEBUG=2 python3 extra/torch_backend/torch_tests.py TestTinyBackendPRIVATEUSE1.test_unary_log_tiny_float32 - - name: Test Ops with TINY_BACKEND - run: PYTHONPATH=. LLVM=1 LLVMOPT=0 TINY_BACKEND=1 python3 -m pytest -n auto test/test_ops.py --durations=20 - - name: Test in-place operations on views - run: PYTHONPATH=. TORCH_DEBUG=1 python3 extra/torch_backend/test_inplace.py - - name: Test multi-gpu - run: PYTHONPATH=. LLVM=1 GPUS=4 TORCH_DEBUG=1 python3 extra/torch_backend/test_multigpu.py - - torchbackendmore: - name: Torch Backend Tests More - runs-on: ubuntu-latest - timeout-minutes: 15 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: torch-backend-pillow-torchvision-et-pt - deps: testing_minimal - llvm: 'true' - - name: Install ninja - run: | - sudo apt update || true - sudo apt install -y --no-install-recommends ninja-build - - name: Test beautiful_mnist in torch with TINY_BACKEND - run: SPLIT_REDUCEOP=0 FUSE_ARANGE=1 PYTHONPATH=. LLVM=1 TARGET_EVAL_ACC_PCT=96.0 TINY_BACKEND=1 python3 examples/other_mnist/beautiful_mnist_torch.py - - name: Test some torch tests (expect failure) - run: PYTHONPATH=. python3 -m pytest extra/torch_backend/torch_tests.py -v --tb=no || true - - tc: - name: Tensor Core tests - runs-on: ubuntu-latest - timeout-minutes: 10 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: uops-minimal - deps: testing_minimal - - name: Test IMAGE=2 support - run: | - IMAGE=2 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm - IMAGE=2 PYTHON=1 python3 test/test_ops.py TestOps.test_simple_conv2d - - name: Test emulated METAL tensor cores - run: | - DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_big_gemm - PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Test emulated AMX tensor cores - run: PYTHONPATH=. DEBUG=2 AMX=1 EMULATE_AMX=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm - - name: Test emulated AMD tensor cores - run: | - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops - - name: Test emulated AMD MFMA tensor cores - run: | - PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Test emulated AMD RDNA4 tensor cores - run: | - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Test emulated CUDA tensor cores - run: | - DEBUG=2 EMULATE_CUDA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm_fp16 - DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm - DEBUG=2 EMULATE_CUDA_SM75=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm_fp16 - PYTHONPATH="." DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH="." DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops - - name: Test emulated INTEL OpenCL tensor cores - run: DEBUG=2 EMULATE_INTEL=1 FORWARD_ONLY=1 PYTHON=1 HALF=1 N=64 python3 ./extra/gemm/simple_matmul.py - - name: Full test tensor cores - run: | - PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 EMULATE_INTEL=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores - PYTHONPATH=. DEBUG=2 AMX=1 EMULATE_AMX=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores - - name: Test tensor cores (TC=3) - run: | - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_METAL=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMD=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMD_MFMA=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_CUDA=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_INTEL=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMX=1 AMX=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation - - name: Test device flop counts - run: | - PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf - PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf - PYTHONPATH=. DEBUG=2 EMULATE_CUDA=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf - PYTHONPATH=. DEBUG=2 EMULATE_INTEL=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf - PYTHONPATH=. DEBUG=2 AMX=1 EMULATE_AMX=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStats.test_simple_matmul - - bepython: - name: Python Backend - runs-on: ubuntu-latest - timeout-minutes: 10 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: be-minimal - deps: testing_minimal - - name: Test dtype with Python emulator - run: DEBUG=1 PYTHONPATH=. PYTHON=1 python3 -m pytest -n=auto test/test_dtype.py test/test_dtype_alu.py - - name: Test ops with Python emulator - run: DEBUG=2 PYTHON=1 python3 -m pytest -n=auto test/test_ops.py -k "not (test_split or test_simple_cumsum or test_cumsum or test_einsum or test_dot or test_dot_1d or test_big_gemm or test_broadcastdot or test_multidot or test_var_axis or test_std_axis or test_broadcast_full or test_broadcast_partial or test_simple_conv3d or test_dilated_conv_transpose2d or test_simple_conv_transpose3d or test_large_input_conv2d or test_max_pool2d or test_max_pool2d_simple or test_max_pool2d_bigger_stride or test_avg_pool2d or test_cat or test_scaled_product_attention or test_scaled_product_attention_causal or test_slice_fancy_indexing_dim_inject_none or test_slice_fancy_indexing_list_indices or test_slice_fancy_indexing_no_dim_collapse or test_slice_fancy_indexing_tuple_indices or test_slice_fancy_indexing_list_with_tensors or test_slice_fancy_indexing_dim_collapse_int or test_interpolate_bilinear or test_interpolate_bilinear_corners_aligned or test_scaled_dot_product_attention or test_cummax or test_simple_cummax or test_logcumsumexp or test_sort or test_cumprod)" --durations=20 - - name: Test uops with Python emulator - run: PYTHON=1 python3 -m pytest test/test_uops.py --durations=20 - - name: Test symbolic with Python emulator - run: PYTHONPATH=. PYTHON=1 python3 test/test_symbolic_ops.py - - name: test_linearizer_failures with Python emulator - run: PYTHONPATH=. PYTHON=1 python3 -m pytest -rA test/test_linearizer_failures.py::TestLinearizerFailures::test_failure_1 - - name: test_renderer_failures with Python emulator - run: PYTHONPATH=. PYTHON=1 python3 -m pytest -rA test/test_renderer_failures.py::TestRendererFailures - - linter: - name: Linters - runs-on: ubuntu-latest - timeout-minutes: 10 - - # TODO: run the pre-commit hook to replace a lot of this - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: linting-only - python-version: '3.10' - deps: linting - - name: Lint bad-indentation and trailing-whitespace with pylint - run: python -m pylint --disable=all -e W0311 -e C0303 --jobs=0 --indent-string=' ' --recursive=y . - - name: Lint with ruff - run: | - pip3 install --upgrade --force-reinstall ruff==0.11.0 - python3 -m ruff check . - python3 -m ruff check examples/mlperf/model_train.py --ignore E501 - - name: Lint tinygrad with pylint - run: python -m pylint tinygrad/ - - name: Run mypy - run: python -m mypy --strict-equality --lineprecision-report . && cat lineprecision.txt - - unittest: - name: Unit Tests - runs-on: ubuntu-latest - timeout-minutes: 10 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: unittest-12 - pydeps: "pillow" - deps: testing_unit - - name: Test README - run: awk '/```python/{flag=1;next}/```/{flag=0}flag' README.md > README.py && PYTHONPATH=. python README.py - - name: Run unit tests - run: PYTHONPATH="." python -m pytest -n=auto test/unit/ --durations=20 - - name: Run targetted tests on NULL backend - run: PYTHONPATH="." NULL=1 python3 test/test_multitensor.py TestMultiTensor.test_data_parallel_resnet_train_step - - name: Run SDXL on NULL backend - run: MAX_BUFFER_SIZE=0 PYTHONPATH="." NULL=1 DEBUG=1 python3 examples/sdxl.py --seed 0 --noshow --timing --fakeweights - # TODO: support fake weights - #- name: Run LLaMA 7B on 4 fake devices - # run: NULL=1 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 3 --temperature 0 --timing - - name: Run GC tests - run: PYTHONPATH="." python test/external/external_uop_gc.py - - name: Run process replay tests - uses: ./.github/actions/process-replay - - name: Repo line count < 14000 lines - run: MAX_LINE_COUNT=14000 python sz.py - - fuzzing: - name: Fuzzing - runs-on: ubuntu-latest - timeout-minutes: 10 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: fuzzing-unit - deps: testing_unit - - name: Fuzz Test symbolic - run: python test/external/fuzz_symbolic.py - - name: Fuzz Test fast idiv - run: python test/external/fuzz_fast_idiv.py - - name: Fuzz Test shapetracker - run: | - PYTHONPATH="." python test/external/fuzz_shapetracker.py - PYTHONPATH="." python test/external/fuzz_shapetracker_math.py - - name: Fuzz Test shape ops - run: python test/external/fuzz_shape_ops.py - - testgpuimage: - name: 'GPU IMAGE Tests' - runs-on: ubuntu-22.04 - timeout-minutes: 10 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: gpu-image - deps: testing_minimal - opencl: 'true' - - name: Run Kernel Count Test - run: PYTHONPATH="." GPU=1 python -m pytest -n=auto test/external/external_test_opt.py - - name: Test WINO=1 - run: GPU=1 DEBUG=2 WINO=1 python3 test/test_ops.py TestOps.test_simple_conv2d - - name: Test GPU IMAGE=2 ops + training - run: | - PYTHONPATH="." GPU=1 IMAGE=2 python -m pytest -n=auto test/test_ops.py --durations=20 - PYTHONPATH="." GPU=1 IMAGE=2 python3 test/models/test_end2end.py TestEnd2End.test_linear_mnist - - name: Run fused optimizer tests - run: PYTHONPATH="." GPU=1 FUSE_OPTIM=1 python -m pytest -n=auto test/models/test_mnist.py - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testopenpilot: - name: 'openpilot Compile Tests' - runs-on: ubuntu-22.04 - timeout-minutes: 10 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: openpilot-compile - deps: testing - opencl: 'true' - llvm: 'true' - - name: Test openpilot model kernel count and gate usage - run: | - PYTHONPATH="." ALLOWED_KERNEL_COUNT=209 ALLOWED_READ_IMAGE=2137 ALLOWED_GATED_READ_IMAGE=29 FLOAT16=0 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx - - name: Test openpilot alt model correctness (float32) - run: PYTHONPATH="." FLOAT16=0 DEBUGCL=1 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/3799fe46b3a629e491d4b8498b8ae83e4c88c304/selfdrive/modeld/models/supercombo.onnx - - name: Test openpilot fastvits model correctness (float32) - run: PYTHONPATH="." FLOAT16=0 DEBUGCL=1 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx - - name: Test openpilot LLVM compile - run: PYTHONPATH="." LLVM=1 LLVMOPT=1 JIT=2 BEAM=0 IMAGE=0 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testonnxcpu: - name: 'ONNX (CPU) Tests' - runs-on: ubuntu-22.04 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: onnxoptc - deps: testing - python-version: '3.11' - llvm: 'true' - - name: Test ONNX (CPU) - run: CPU=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20 - - name: Test ONNX (LLVM) - run: LLVM=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20 - - name: Test Additional ONNX Ops (CPU) - run: CPU=1 PYTHONPATH=. python3 test/external/external_test_onnx_ops.py - - name: Test Quantize ONNX - run: CPU=1 PYTHONPATH=. python3 test/test_quantize_onnx.py - - name: Run REMOTE=1 Test - run: | - REMOTEDEV=CPU REMOTE=1 python3 -m pytest test/test_tiny.py test/test_jit.py test/test_multitensor.py - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testopencl: - name: 'ONNX (GPU)+Optimization Tests' - runs-on: ubuntu-22.04 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: onnxoptl - deps: testing - pydeps: "tensorflow==2.15.1 tensorflow_addons" - python-version: '3.11' - opencl: 'true' - - name: Test ONNX (GPU) - run: GPU=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20 - - name: Run REMOTE=1 Test - run: | - REMOTEDEV=GPU REMOTE=1 python3 -m pytest test/test_tiny.py test/test_image_dtype.py test/test_jit.py - REMOTEDEV=GPU IMAGE=2 REMOTE=1 python3 -m pytest test/test_tiny.py test/test_image_dtype.py - - name: Test Optimization Helpers - run: PYTHONPATH="." DEBUG=1 python3 extra/optimization/test_helpers.py - - name: Test Action Space - run: PYTHONPATH="." DEBUG=1 GPU=1 python3 extra/optimization/get_action_space.py - - name: Test Beam Search - run: PYTHONPATH="." GPU=1 IGNORE_BEAM_CACHE=1 python3 -m pytest extra/optimization/test_beam_search.py - - name: Test MLPerf stuff - run: GPU=1 python -m pytest -n=auto test/external/external_test_optim.py test/external/external_test_losses.py test/external/external_test_metrics.py test/external/external_test_datasets.py --durations=20 - - name: Run handcode_opt - run: PYTHONPATH=. MODEL=resnet GPU=1 DEBUG=1 BS=4 HALF=0 python3 examples/handcode_opt.py - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testmodels: - name: Models (llvm+cpu+gpu) - runs-on: ubuntu-22.04 - timeout-minutes: 15 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: models - deps: testing - opencl: 'true' - llvm: 'true' - - name: Test models (llvm) - run: LLVM=1 python -m pytest -n=auto test/models --durations=20 - - name: Test models (gpu) - run: GPU=1 python -m pytest -n=auto test/models --durations=20 - - name: Test models (cpu) - run: CPU=1 python -m pytest -n=auto test/models --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testdsp: - name: Linux (DSP) - runs-on: ubuntu-24.04 - timeout-minutes: 15 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: dsp-minimal - deps: testing_minimal - pydeps: "onnx==1.17.0 onnxruntime pillow" - llvm: "true" - - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v3 - - name: Build QEMU Docker with cache - uses: docker/build-push-action@v4 - with: - file: extra/dsp/Dockerfile - push: false - load: true - tags: qemu-hexagon:latest - cache-from: type=gha - cache-to: type=gha,mode=min - - name: Set MOCKDSP env - run: printf "MOCKDSP=1" >> $GITHUB_ENV - - name: Run test_tiny on DSP - run: DEBUG=2 DSP=1 python test/test_tiny.py - - name: Test transcendentals - run: CC=clang-19 PYTHONPATH="." DEBUG=2 DSP=1 python test/test_transcendental.py TestTranscendentalVectorized - - name: Test quantize onnx - run: PYTHONPATH="." DEBUG=2 DSP=1 python3 test/test_quantize_onnx.py - - name: Test LLVM=1 DEVECTORIZE=0 - run: LLVM=1 DEVECTORIZE=0 python3 -m pytest -n auto test/test_tiny.py test/test_ops.py -k "not test_avg_pool3d_failure" - - name: Test LLVM=1 DEVECTORIZE=0 for model - run: PYTHONPATH="." LLVM=1 DEVECTORIZE=0 python3 test/models/test_efficientnet.py - - name: Test CPU=1 DEVECTORIZE=0 - run: CPU=1 DEVECTORIZE=0 python3 -m pytest -n auto test/test_tiny.py test/test_ops.py -k "not test_avg_pool3d_failure" - - testwebgpu: - name: Linux (WebGPU) - runs-on: ubuntu-22.04 - timeout-minutes: 20 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: webgpu-minimal - deps: testing_minimal - python-version: '3.11' - webgpu: 'true' - - name: Check Device.DEFAULT (WEBGPU) and print some source - run: | - WEBGPU=1 python -c "from tinygrad import Device; assert Device.DEFAULT == 'WEBGPU', Device.DEFAULT" - WEBGPU=1 DEBUG=4 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add - - name: Run selected webgpu tests - run: | - WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit \ - --ignore=test/test_copy_speed.py --ignore=test/test_rearrange_einops.py \ - --ignore=test/test_fuzz_shape_ops.py --ignore=test/test_linearizer_failures.py --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testamd: - strategy: - fail-fast: false - matrix: - backend: [amd, amdllvm] - - name: Linux (${{ matrix.backend }}) - runs-on: ubuntu-22.04 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - AMD: 1 - MOCKGPU: 1 - FORWARD_ONLY: 1 - AMD_LLVM: ${{ matrix.backend == 'amdllvm' && '1' || matrix.backend != 'amdllvm' && '0' }} - PYTHONPATH: ${{ github.workspace }} - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: ${{ matrix.backend }}-minimal - deps: testing_minimal - amd: 'true' - llvm: ${{ matrix.backend == 'amdllvm' && 'true' }} - - name: Check Device.DEFAULT and print some source - run: | - python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['AMD'], Device.DEFAULT" - DEBUG=5 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add - - name: Run LLVM test - if: matrix.backend=='amdllvm' - run: python test/test_amd_llvm.py - - name: Run pytest (amd) - run: python -m pytest -n=auto test/test_ops.py test/test_dtype.py test/test_dtype_alu.py test/test_linearizer.py test/test_randomness.py test/test_jit.py test/test_graph.py test/test_multitensor.py test/test_hcq.py test/external/external_test_am.py --durations=20 - - name: Run TRANSCENDENTAL math - run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20 - - name: Run TestOps.test_add with SQTT - run: | - PROFILE=1 SQTT=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add - extra/sqtt/rgptool.py create "/tmp/profile.pkl.$USER" -o /tmp/gpu0.rgp - - name: Run process replay tests - uses: ./.github/actions/process-replay - - testnvidia: - strategy: - fail-fast: false - matrix: - backend: [ptx, nv] - - name: Linux (${{ matrix.backend }}) - runs-on: ubuntu-22.04 - timeout-minutes: 20 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: ${{ matrix.backend }}-minimal - deps: testing_minimal - cuda: 'true' - - name: Set env - run: printf "${{ matrix.backend == 'PTX' && 'FORWARD_ONLY=1\nJIT=1\nOPT=2\nCUDA=1\nPTX=1\nMOCKGPU=1' || matrix.backend == 'nv' && 'NV=1\nMOCKGPU=1\nFORWARD_ONLY=1' }}" >> $GITHUB_ENV - - name: Check Device.DEFAULT and print some source - run: | - PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['CUDA','NV'], Device.DEFAULT" - DEBUG=5 PYTHONPATH=${{ github.workspace }} FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add - - name: Run pytest (cuda) - # skip multitensor because it's slow - run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore test/test_gc.py --ignore test/test_multitensor.py --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - - tests: - strategy: - fail-fast: false - matrix: - backend: [llvm, cpu, gpu] - - name: Linux (${{ matrix.backend }}) - runs-on: ubuntu-22.04 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: ${{ matrix.backend }}-minimal - deps: testing_minimal - opencl: ${{ matrix.backend == 'gpu' && 'true' }} - llvm: ${{ matrix.backend == 'llvm' && 'true' }} - - name: Set env - run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'gpu' && 'GPU=1' }}" >> $GITHUB_ENV - - name: Check Device.DEFAULT and print some source - run: | - PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['LLVM','CPU','GPU'], Device.DEFAULT" - DEBUG=5 PYTHONPATH=${{ github.workspace }} FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add - - name: Run pytest (not cuda) - run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20 - - name: Run TRANSCENDENTAL math - run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - -# ****** OSX Tests ****** - - testmetal2: - name: MacOS (unit) - runs-on: macos-14 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: metal2 - deps: testing - python-version: '3.11' - amd: 'true' - cuda: 'true' - llvm: 'true' - - name: Run real world test - run: METAL=1 python -m pytest -n=auto test/models/test_real_world.py --durations=20 - - name: Test models (Metal) - run: METAL=1 python -m pytest -n=auto test/models -v --durations=20 - - name: Run ONNX - run: METAL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20 - - name: Test tensor core ops (fake) - run: TC=2 METAL=1 DEBUG=3 python test/test_ops.py TestOps.test_gemm - - name: Test tensor core ops (real) - run: METAL=1 DEBUG=3 python test/test_ops.py TestOps.test_big_gemm - - name: Test LLaMA compile speed - run: PYTHONPATH="." METAL=1 python test/external/external_test_speed_llama.py - - name: Test Beam Search - run: PYTHONPATH="." METAL=1 IGNORE_BEAM_CACHE=1 python3 -m pytest extra/optimization/test_beam_search.py - - name: Fuzz Test linearizer - run: PYTHONPATH="." METAL=1 DEPTH=4 FUZZ_N=50 FUZZ_MAX_SIZE=1000000 python test/external/fuzz_linearizer.py - - name: Run TRANSCENDENTAL math - run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20 - - name: Run pytest (amd) - env: - MOCKGPU: 1 - AMD: 1 - FORWARD_ONLY: 1 - run: | - python3 -m pytest -n=auto test/test_hcq.py test/test_tiny.py --durations=20 - - name: Run pytest (amd with llvm backend) - env: - MOCKGPU: 1 - AMD: 1 - AMD_LLVM: 1 - FORWARD_ONLY: 1 - run: | - python -m pytest -n=auto test/test_hcq.py test/test_tiny.py test/test_amd_llvm.py --durations=20 - - name: Run pytest (ptx) - env: - MOCKGPU: 1 - PTX: 1 - NV: 1 - FORWARD_ONLY: 1 - run: | - python3 -m pytest -n=auto test/test_hcq.py test/test_tiny.py --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - - osxwebgpu: - name: MacOS (WebGPU) - runs-on: macos-14 - timeout-minutes: 10 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: osx-webgpu - deps: testing_minimal - webgpu: 'true' - - name: Test infinity math in WGSL - run: WEBGPU=1 python -m pytest -n=auto test/test_renderer_failures.py::TestWGSLFailures::test_multiply_infinity --durations=20 - - name: Build WEBGPU Efficientnet - run: WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Metal" python3 -m examples.compile_efficientnet - - name: Clean npm cache - run: npm cache clean --force - - name: Install Puppeteer - run: npm install puppeteer - - name: Run WEBGPU Efficientnet - run: node test/web/test_webgpu.js - - name: Run VIZ tests as external package - run: | - mkdir $GITHUB_WORKSPACE/test_dir - cd $GITHUB_WORKSPACE/test_dir - python -m venv venv - source venv/bin/activate - pip install $GITHUB_WORKSPACE - cp $GITHUB_WORKSPACE/test/web/test_viz.js . - node test_viz.js - - osxremote: - name: MacOS (remote metal) - runs-on: macos-15 - timeout-minutes: 10 - env: - REMOTE: 1 - REMOTEDEV: METAL - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: macos-remote - deps: testing_minimal - - name: Check Device.DEFAULT and print some source - run: | - python -c "from tinygrad import Device; assert Device.DEFAULT == 'REMOTE', Device.DEFAULT" - python -c "from tinygrad import Device; assert Device.default.properties.real_device == 'METAL', Device.default.properties.real_device" - DEBUG=4 python3 test/test_tiny.py TestTiny.test_plus - - name: Run REMOTE=1 Test - run: | - python3 -m pytest test/test_tiny.py test/test_jit.py test/test_subbuffer.py test/test_graph.py test/test_multitensor.py test/test_tensor_variable.py - - amdremote: - name: Linux (remote amd) - runs-on: ubuntu-22.04 - timeout-minutes: 20 - env: - REMOTE: 1 - REMOTEDEV: 'AMD' - PYTHONPATH: ${{ github.workspace }} - MOCKGPU: 1 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: linux-remote-amd - deps: testing_minimal - amd: 'true' - llvm: 'true' - - name: Check Device.DEFAULT and print some source - run: | - python -c "from tinygrad import Device; assert Device.DEFAULT == 'REMOTE', Device.DEFAULT" - python -c "from tinygrad import Device; assert Device.default.properties.real_device == 'AMD', Device.default.properties.real_device" - DEBUG=4 python3 test/test_tiny.py TestTiny.test_plus - - name: Run REMOTE=1 Test - run: | - python3 -m pytest test/test_tiny.py test/test_jit.py test/test_subbuffer.py test/test_graph.py test/test_multitensor.py test/test_tensor_variable.py - - osxtests: - strategy: - fail-fast: false - matrix: - backend: [metal, llvm, cpu] - name: MacOS (${{ matrix.backend }}) - runs-on: macos-15 - timeout-minutes: 20 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: macos-${{ matrix.backend }}-minimal - deps: testing_minimal - llvm: ${{ matrix.backend == 'llvm' && 'true' }} - - name: Set env - run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'metal' && 'METAL=1'}}" >> $GITHUB_ENV - - name: Check Device.DEFAULT and print some source - run: | - python -c "from tinygrad import Device; assert Device.DEFAULT == '${{ matrix.backend }}'.upper(), Device.DEFAULT" - DEBUG=4 python3 test/test_tiny.py TestTiny.test_plus - - name: Run pytest (${{ matrix.backend }}) - run: python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20 - - name: Run process replay tests - uses: ./.github/actions/process-replay - - name: Run macOS-specific unit test - if: matrix.backend == 'cpu' - run: python3 -m pytest test/unit/test_disk_tensor.py::TestDiskTensor::test_copy_to_cpu_not_truncated - -# ****** Windows Tests ****** - - wintests: - strategy: - fail-fast: false - matrix: - backend: [llvm, cpu] - - name: Windows (${{ matrix.backend }}) - runs-on: windows-latest - timeout-minutes: 15 - env: - IGNORE_OOB: 0 - steps: - - name: Checkout Code - uses: actions/checkout@v4 - - name: Setup Environment - uses: ./.github/actions/setup-tinygrad - with: - key: windows-minimal - deps: testing_unit - - name: Set env - shell: bash - run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1'}}" >> $GITHUB_ENV - - name: Run unit tests - if: matrix.backend=='llvm' - run: python -m pytest -n=auto test/unit/ --ignore=test/unit/test_disk_tensor.py --ignore=test/unit/test_elf.py --ignore=test/unit/test_tar.py - - name: Run pytest (${{ matrix.backend }}) - shell: bash - run: | - python -c "from tinygrad import Device; assert Device.DEFAULT == '${{ matrix.backend }}'.upper(), Device.DEFAULT" - python -m pytest -n=auto test/test_tiny.py test/test_ops.py --durations=20 diff --git a/tinygrad/.gitignore b/tinygrad/.gitignore deleted file mode 100644 index fd1a734b..00000000 --- a/tinygrad/.gitignore +++ /dev/null @@ -1,64 +0,0 @@ -__pycache__ -.venv/ -.venv-*/ -.vscode -.DS_Store -notebooks -.*.swp -.*.swo -*.pyc -*.so -*.txt -build -!examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/ -/dist -*.egg-info -/env -a.out -boxes.jpg -pandecode.dump -vertex.bin -recognize* -.idea -*.prof -extra/disassemblers/applegpu -extra/datasets/cifar-10-python.tar.gz -extra/datasets/librispeech/ -extra/datasets/imagenet/ -extra/datasets/wiki/ -extra/datasets/kits19 -extra/datasets/kits19/ -extra/datasets/squad/ -extra/datasets/img_align_celeba* -extra/datasets/open-images-v6-mlperf -extra/datasets/kits/ -extra/datasets/COCO/ -extra/datasets/audio* -extra/huggingface_onnx/models/* -extra/huggingface_onnx/*.yaml -extra/weights -venv -examples/**/net.*[js,json] -examples/**/*.safetensors -node_modules -package.json -package-lock.json -temp -*.csv -.coverage -coverage.xml -htmlcov -outputs_yolov8 -wandb -model.safetensors -quickstart.py -.hypothesis -weights -*.lprof -comgr_* -*.pkl -site/ -profile_stats -*.log -target -.mypy_cache diff --git a/tinygrad/.pre-commit-config.yaml b/tinygrad/.pre-commit-config.yaml deleted file mode 100644 index 0e23d110..00000000 --- a/tinygrad/.pre-commit-config.yaml +++ /dev/null @@ -1,46 +0,0 @@ -# on Windows -- $env:SKIP="tests,example" -repos: - - repo: local - hooks: - - id: ruff - name: ruff - entry: python3 -m ruff check . - language: system - always_run: true - pass_filenames: false - - id: tiny - name: tiny tests - entry: python3 -m pytest test/test_tiny.py - language: system - always_run: true - pass_filenames: false - - id: mypy - name: mypy - entry: python3 -m mypy tinygrad/ --strict-equality - language: system - always_run: true - pass_filenames: false - - id: devicetests - name: select GPU tests - entry: env GPU=1 PYTHONPATH="." python3 -m pytest test/test_uops.py test/test_search.py - language: system - always_run: true - pass_filenames: false - - id: tests - name: subset of tests - entry: env MAX_BUFFER_SIZE=300000000 PYTHONPATH="." python3 -m pytest -n=4 --ignore=test/unit/test_keccak.py --ignore=test/unit/test_indexing.py test/unit/ test/test_ops.py test/test_dtype.py test/test_schedule.py test/test_assign.py test/test_symbolic_shapetracker.py - language: system - always_run: true - pass_filenames: false - - id: example - name: multi device tests - entry: python3 test/external/external_test_example.py - language: system - always_run: true - pass_filenames: false - - id: pylint - name: pylint - entry: python3 -m pylint tinygrad/ - language: system - always_run: true - pass_filenames: false \ No newline at end of file diff --git a/tinygrad/.pylintrc b/tinygrad/.pylintrc deleted file mode 100644 index 57e05e93..00000000 --- a/tinygrad/.pylintrc +++ /dev/null @@ -1,472 +0,0 @@ -[MASTER] - -# A comma-separated list of package or module names from where C extensions may -# be loaded. Extensions are loading into the active Python interpreter and may -# run arbitrary code -extension-pkg-whitelist=scipy,cereal.messaging.messaging_pyx,PyQt5,av - -# Add files or directories to the blacklist. They should be base names, not -# paths. -ignore=CVS,autogen,msm_kgsl.py,runtime,.venv - -# Add files or directories matching the regex patterns to the blacklist. The -# regex matches against base names, not paths. -ignore-patterns= - -# Python code to execute, usually for sys.path manipulation such as -# pygtk.require(). -#init-hook= - -# Use multiple processes to speed up Pylint. -jobs=4 - -# List of plugins (as comma separated values of python modules names) to load, -# usually to register additional checkers. -load-plugins= - -# Pickle collected data for later comparisons. -persistent=yes - -# Specify a configuration file. -#rcfile= - -# When enabled, pylint would attempt to guess common misconfiguration and emit -# user-friendly hints instead of false-positive error messages -suggestion-mode=yes - -# Allow loading of arbitrary C extensions. Extensions are imported into the -# active Python interpreter and may run arbitrary code. -unsafe-load-any-extension=no - - -[MESSAGES CONTROL] - -# Only show warnings with the listed confidence levels. Leave empty to show -# all. Valid levels: HIGH, INFERENCE, INFERENCE_FAILURE, UNDEFINED -confidence= - -# Disable the message, report, category or checker with the given id(s). You -# can either give multiple identifiers separated by comma (,) or put this -# option multiple times (only on the command line, not in the configuration -# file where it should appear only once).You can also use "--disable=all" to -# disable everything first and then reenable specific checks. For example, if -# you want to run only the similarities checker, you can use "--disable=all -# --enable=similarities". If you want to run only the classes checker, but have -# no Warning level messages displayed, use"--disable=all --enable=classes -# --disable=W" -disable=C,R,W0613,W0511,W0212,W0201,W0106,W0603,W0621,W0703,W1201,W1203,E1136,W1514,E1101,W0221,W0105,E0401,abstract-method -# E1101 for function binding -# W0221 for Function class -# W0105 for comment strings -# E0401 for missing imports - -# Enable the message, report, category or checker with the given id(s). You can -# either give multiple identifier separated by comma (,) or put this option -# multiple time (only on the command line, not in the configuration file where -# it should appear only once). See also the "--disable" option for examples. -enable=c-extension-no-member,use-a-generator, no-else-return - - -[REPORTS] - -# Python expression which should return a note less than 10 (10 is the highest -# note). You have access to the variables errors warning, statement which -# respectively contain the number of errors / warnings messages and the total -# number of statements analyzed. This is used by the global evaluation report -# (RP0004). -evaluation=10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10) - -# Template used to display messages. This is a python new-style format string -# used to format the message information. See doc for all details -#msg-template= - -# Set the output format. Available formats are text, parseable, colorized, json -# and msvs (visual studio).You can also give a reporter class, eg -# mypackage.mymodule.MyReporterClass. -output-format=text - -# Tells whether to display a full report or only the messages -reports=no - -# Activate the evaluation score. -score=yes - - -[REFACTORING] - -# Maximum number of nested blocks for function / method body -max-nested-blocks=5 - -# Complete name of functions that never returns. When checking for -# inconsistent-return-statements if a never returning function is called then -# it will be considered as an explicit return statement and no message will be -# printed. -never-returning-functions=optparse.Values,sys.exit - - -[LOGGING] - -# Logging modules to check that the string format arguments are in logging -# function parameter format -logging-modules=logging - - -[SPELLING] - -# Limits count of emitted suggestions for spelling mistakes -max-spelling-suggestions=4 - -# Spelling dictionary name. Available dictionaries: none. To make it working -# install python-enchant package. -spelling-dict= - -# List of comma separated words that should not be checked. -spelling-ignore-words= - -# A path to a file that contains private dictionary; one word per line. -spelling-private-dict-file= - -# Tells whether to store unknown words to indicated private dictionary in -# --spelling-private-dict-file option instead of raising a message. -spelling-store-unknown-words=no - - -[MISCELLANEOUS] - -# List of note tags to take in consideration, separated by a comma. -notes=FIXME, - XXX, - TODO - - -[SIMILARITIES] - -# Ignore comments when computing similarities. -ignore-comments=yes - -# Ignore docstrings when computing similarities. -ignore-docstrings=yes - -# Ignore imports when computing similarities. -ignore-imports=no - -# Minimum lines number of a similarity. -min-similarity-lines=4 - - -[TYPECHECK] - -# List of decorators that produce context managers, such as -# contextlib.contextmanager. Add to this list to register other decorators that -# produce valid context managers. -contextmanager-decorators=contextlib.contextmanager - -# List of members which are set dynamically and missed by pylint inference -# system, and so shouldn't trigger E1101 when accessed. Python regular -# expressions are accepted. -generated-members=capnp.* cereal.* pygame.* zmq.* setproctitle.* smbus2.* usb1.* serial.* cv2.* ft4222.* carla.* - -# Tells whether missing members accessed in mixin class should be ignored. A -# mixin class is detected if its name ends with "mixin" (case insensitive). -ignore-mixin-members=yes - -# This flag controls whether pylint should warn about no-member and similar -# checks whenever an opaque object is returned when inferring. The inference -# can return multiple potential results while evaluating a Python object, but -# some branches might not be evaluated, which results in partial inference. In -# that case, it might be useful to still emit no-member and other checks for -# the rest of the inferred objects. -ignore-on-opaque-inference=yes - -# List of class names for which member attributes should not be checked (useful -# for classes with dynamically set attributes). This supports the use of -# qualified names. -ignored-classes=optparse.Values,thread._local,_thread._local - -# List of module names for which member attributes should not be checked -# (useful for modules/projects where namespaces are manipulated during runtime -# and thus existing member attributes cannot be deduced by static analysis. It -# supports qualified module names, as well as Unix pattern matching. -ignored-modules=flask setproctitle usb1 flask.ext.socketio smbus2 usb1.* - -# Show a hint with possible names when a member name was not found. The aspect -# of finding the hint is based on edit distance. -missing-member-hint=yes - -# The minimum edit distance a name should have in order to be considered a -# similar match for a missing member name. -missing-member-hint-distance=1 - -# The total number of similar names that should be taken in consideration when -# showing a hint for a missing member. -missing-member-max-choices=1 - - -[VARIABLES] - -# List of additional names supposed to be defined in builtins. Remember that -# you should avoid to define new builtins when possible. -additional-builtins= - -# Tells whether unused global variables should be treated as a violation. -allow-global-unused-variables=yes - -# List of strings which can identify a callback function by name. A callback -# name must start or end with one of those strings. -callbacks=cb_, - _cb - -# A regular expression matching the name of dummy variables (i.e. expectedly -# not used). -dummy-variables-rgx=_+$|(_[a-zA-Z0-9_]*[a-zA-Z0-9]+?$)|dummy|^ignored_|^unused_ - -# Argument names that match this expression will be ignored. Default to name -# with leading underscore -ignored-argument-names=_.*|^ignored_|^unused_ - -# Tells whether we should check for unused import in __init__ files. -init-import=no - -# List of qualified module names which can have objects that can redefine -# builtins. -redefining-builtins-modules=six.moves,past.builtins,future.builtins - - -[FORMAT] - -# Expected format of line ending, e.g. empty (any line ending), LF or CRLF. -expected-line-ending-format= - -# Regexp for a line that is allowed to be longer than the limit. -ignore-long-lines=^\s*(# )??$ - -# Number of spaces of indent required inside a hanging or continued line. -indent-after-paren=4 - -# String used as indentation unit. This is usually " " (4 spaces) or "\t" (1 -# tab). -indent-string=' ' - -# Maximum number of characters on a single line. -max-line-length=150 - -# Maximum number of lines in a module -max-module-lines=1000 - -# Allow the body of a class to be on the same line as the declaration if body -# contains single statement. -single-line-class-stmt=no - -# Allow the body of an if to be on the same line as the test if there is no -# else. -single-line-if-stmt=no - - -[BASIC] - -# Naming style matching correct argument names -argument-naming-style=snake_case - -# Regular expression matching correct argument names. Overrides argument- -# naming-style -#argument-rgx= - -# Naming style matching correct attribute names -attr-naming-style=snake_case - -# Regular expression matching correct attribute names. Overrides attr-naming- -# style -#attr-rgx= - -# Bad variable names which should always be refused, separated by a comma -bad-names=foo, - bar, - baz, - toto, - tutu, - tata - -# Naming style matching correct class attribute names -class-attribute-naming-style=any - -# Regular expression matching correct class attribute names. Overrides class- -# attribute-naming-style -#class-attribute-rgx= - -# Naming style matching correct class names -class-naming-style=PascalCase - -# Regular expression matching correct class names. Overrides class-naming-style -#class-rgx= - -# Naming style matching correct constant names -const-naming-style=UPPER_CASE - -# Regular expression matching correct constant names. Overrides const-naming- -# style -#const-rgx= - -# Minimum line length for functions/classes that require docstrings, shorter -# ones are exempt. -docstring-min-length=-1 - -# Naming style matching correct function names -function-naming-style=snake_case - -# Regular expression matching correct function names. Overrides function- -# naming-style -#function-rgx= - -# Good variable names which should always be accepted, separated by a comma -good-names=i, - j, - k, - ex, - Run, - _ - -# Include a hint for the correct naming format with invalid-name -include-naming-hint=no - -# Naming style matching correct inline iteration names -inlinevar-naming-style=any - -# Regular expression matching correct inline iteration names. Overrides -# inlinevar-naming-style -#inlinevar-rgx= - -# Naming style matching correct method names -method-naming-style=snake_case - -# Regular expression matching correct method names. Overrides method-naming- -# style -#method-rgx= - -# Naming style matching correct module names -module-naming-style=snake_case - -# Regular expression matching correct module names. Overrides module-naming- -# style -#module-rgx= - -# Colon-delimited sets of names that determine each other's naming style when -# the name regexes allow several styles. -name-group= - -# Regular expression which should only match function or class names that do -# not require a docstring. -no-docstring-rgx=^_ - -# List of decorators that produce properties, such as abc.abstractproperty. Add -# to this list to register other decorators that produce valid properties. -property-classes=abc.abstractproperty - -# Naming style matching correct variable names -variable-naming-style=snake_case - -# Regular expression matching correct variable names. Overrides variable- -# naming-style -#variable-rgx= - - -[DESIGN] - -# Maximum number of arguments for function / method -max-args=5 - -# Maximum number of attributes for a class (see R0902). -max-attributes=7 - -# Maximum number of boolean expressions in a if statement -max-bool-expr=5 - -# Maximum number of branch for function / method body -max-branches=12 - -# Maximum number of locals for function / method body -max-locals=15 - -# Maximum number of parents for a class (see R0901). -max-parents=7 - -# Maximum number of public methods for a class (see R0904). -max-public-methods=20 - -# Maximum number of return / yield for function / method body -max-returns=6 - -# Maximum number of statements in function / method body -max-statements=50 - -# Minimum number of public methods for a class (see R0903). -min-public-methods=2 - - -[CLASSES] - -# List of method names used to declare (i.e. assign) instance attributes. -defining-attr-methods=__init__, - __new__, - setUp - -# List of member names, which should be excluded from the protected access -# warning. -exclude-protected=_asdict, - _fields, - _replace, - _source, - _make - -# List of valid names for the first argument in a class method. -valid-classmethod-first-arg=cls - -# List of valid names for the first argument in a metaclass class method. -valid-metaclass-classmethod-first-arg=mcs - - -[IMPORTS] - -# Allow wildcard imports from modules that define __all__. -allow-wildcard-with-all=no - -# Analyse import fallback blocks. This can be used to support both Python 2 and -# 3 compatible code, which means that the block might have code that exists -# only in one or another interpreter, leading to false positives when analysed. -analyse-fallback-blocks=no - -# Deprecated modules which should not be used, separated by a comma -deprecated-modules=regsub, - TERMIOS, - Bastion, - rexec - -# Create a graph of external dependencies in the given file (report RP0402 must -# not be disabled) -ext-import-graph= - -# Create a graph of every (i.e. internal and external) dependencies in the -# given file (report RP0402 must not be disabled) -import-graph= - -# Create a graph of internal dependencies in the given file (report RP0402 must -# not be disabled) -int-import-graph= - -# Force import order to recognize a module as part of the standard -# compatibility libraries. -known-standard-library= - -# Force import order to recognize a module as part of a third party library. -known-third-party=enchant - -[STRING] - -# This flag controls whether the implicit-str-concat should generate a warning -# on implicit string concatenation in sequences defined over several lines. -check-str-concat-over-line-jumps=yes - -[EXCEPTIONS] - -# Exceptions that will emit a warning when being caught. Defaults to -# "Exception" -overgeneral-exceptions=builtins.Exception diff --git a/tinygrad/AGENTS.md b/tinygrad/AGENTS.md deleted file mode 100644 index fe541700..00000000 --- a/tinygrad/AGENTS.md +++ /dev/null @@ -1,17 +0,0 @@ -# tinygrad agents - -Hello agent. You are one of the most talented programmers of your generation. - -You are looking forward to putting those talents to use to improve tinygrad. - -## philosophy - -tinygrad is a **tensor** library focused on beauty and minimalism, while still matching the functionality of PyTorch and JAX. - -Every line must earn its keep. Prefer readability over cleverness. We believe that if carefully designed, 10 lines can have the impact of 1000. - -Never mix functionality changes with whitespace changes. All functionality changes must be tested. - -## style - -Use **2-space indentation**, and keep lines to a maximum of **150 characters**. Match the existing style. diff --git a/tinygrad/LICENSE b/tinygrad/LICENSE deleted file mode 100644 index d42cf56f..00000000 --- a/tinygrad/LICENSE +++ /dev/null @@ -1,7 +0,0 @@ -Copyright (c) 2024, the tiny corp - -Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/tinygrad/README.md b/tinygrad/README.md deleted file mode 100644 index 2968535a..00000000 --- a/tinygrad/README.md +++ /dev/null @@ -1,182 +0,0 @@ -
- - - - tiny corp logo - - -tinygrad: For something between [PyTorch](https://github.com/pytorch/pytorch) and [karpathy/micrograd](https://github.com/karpathy/micrograd). Maintained by [tiny corp](https://tinygrad.org). - -

- -[Homepage](https://github.com/tinygrad/tinygrad) | [Documentation](https://docs.tinygrad.org/) | [Discord](https://discord.gg/ZjZadyC7PK) - -

- -[![GitHub Repo stars](https://img.shields.io/github/stars/tinygrad/tinygrad)](https://github.com/tinygrad/tinygrad/stargazers) -[![Unit Tests](https://github.com/tinygrad/tinygrad/actions/workflows/test.yml/badge.svg)](https://github.com/tinygrad/tinygrad/actions/workflows/test.yml) -[![Discord](https://img.shields.io/discord/1068976834382925865)](https://discord.gg/ZjZadyC7PK) - -
- ---- - -Despite tinygrad's size, it is a fully featured deep learning framework. - -Due to its extreme simplicity, it is the easiest framework to add new accelerators to, with support for both inference and training. If XLA is CISC, tinygrad is RISC. - -tinygrad is now beta software, we [raised some money](https://geohot.github.io/blog/jekyll/update/2023/05/24/the-tiny-corp-raised-5M.html) to make it good. Someday, we will tape out chips. - -## Features - -### LLaMA and Stable Diffusion - -tinygrad can run [LLaMA](/docs/showcase.md#llama) and [Stable Diffusion](/docs/showcase.md#stable-diffusion)! - -### Laziness - -Try a matmul. See how, despite the style, it is fused into one kernel with the power of laziness. - -```sh -DEBUG=3 python3 -c "from tinygrad import Tensor; -N = 1024; a, b = Tensor.rand(N, N), Tensor.rand(N, N); -c = (a.reshape(N, 1, N) * b.T.reshape(1, N, N)).sum(axis=2); -print((c.numpy() - (a.numpy() @ b.numpy())).mean())" -``` - -And we can change `DEBUG` to `4` to see the generated code. - -### Neural networks - -As it turns out, 90% of what you need for neural networks are a decent autograd/tensor library. -Throw in an optimizer, a data loader, and some compute, and you have all you need. - -```python -from tinygrad import Tensor, nn - -class LinearNet: - def __init__(self): - self.l1 = Tensor.kaiming_uniform(784, 128) - self.l2 = Tensor.kaiming_uniform(128, 10) - def __call__(self, x:Tensor) -> Tensor: - return x.flatten(1).dot(self.l1).relu().dot(self.l2) - -model = LinearNet() -optim = nn.optim.Adam([model.l1, model.l2], lr=0.001) - -x, y = Tensor.rand(4, 1, 28, 28), Tensor([2,4,3,7]) # replace with real mnist dataloader - -with Tensor.train(): - for i in range(10): - optim.zero_grad() - loss = model(x).sparse_categorical_crossentropy(y).backward() - optim.step() - print(i, loss.item()) -``` - -See [examples/beautiful_mnist.py](examples/beautiful_mnist.py) for the full version that gets 98% in ~5 seconds - -## Accelerators - -tinygrad already supports numerous accelerators, including: - -- [x] [GPU (OpenCL)](tinygrad/runtime/ops_gpu.py) -- [x] [CPU (C Code)](tinygrad/runtime/ops_cpu.py) -- [x] [LLVM](tinygrad/runtime/ops_llvm.py) -- [x] [METAL](tinygrad/runtime/ops_metal.py) -- [x] [CUDA](tinygrad/runtime/ops_cuda.py) -- [x] [AMD](tinygrad/runtime/ops_amd.py) -- [x] [NV](tinygrad/runtime/ops_nv.py) -- [x] [QCOM](tinygrad/runtime/ops_qcom.py) -- [x] [WEBGPU](tinygrad/runtime/ops_webgpu.py) - -And it is easy to add more! Your accelerator of choice only needs to support a total of ~25 low level ops. - -To check default accelerator run: `python3 -c "from tinygrad import Device; print(Device.DEFAULT)"` - -## Installation - -The current recommended way to install tinygrad is from source. - -### From source - -```sh -git clone https://github.com/tinygrad/tinygrad.git -cd tinygrad -python3 -m pip install -e . -``` - -### Direct (master) - -```sh -python3 -m pip install git+https://github.com/tinygrad/tinygrad.git -``` - -## Documentation - -Documentation along with a quick start guide can be found on the [docs website](https://docs.tinygrad.org/) built from the [docs/](/docs) directory. - -### Quick example comparing to PyTorch - -```python -from tinygrad import Tensor - -x = Tensor.eye(3, requires_grad=True) -y = Tensor([[2.0,0,-2.0]], requires_grad=True) -z = y.matmul(x).sum() -z.backward() - -print(x.grad.tolist()) # dz/dx -print(y.grad.tolist()) # dz/dy -``` - -The same thing but in PyTorch: -```python -import torch - -x = torch.eye(3, requires_grad=True) -y = torch.tensor([[2.0,0,-2.0]], requires_grad=True) -z = y.matmul(x).sum() -z.backward() - -print(x.grad.tolist()) # dz/dx -print(y.grad.tolist()) # dz/dy -``` - -## Contributing - -There has been a lot of interest in tinygrad lately. Following these guidelines will help your PR get accepted. - -We'll start with what will get your PR closed with a pointer to this section: - -- No code golf! While low line count is a guiding light of this project, anything that remotely looks like code golf will be closed. The true goal is reducing complexity and increasing readability, and deleting `\n`s does nothing to help with that. -- All docs and whitespace changes will be closed unless you are a well-known contributor. The people writing the docs should be those who know the codebase the absolute best. People who have not demonstrated that shouldn't be messing with docs. Whitespace changes are both useless *and* carry a risk of introducing bugs. -- Anything you claim is a "speedup" must be benchmarked. In general, the goal is simplicity, so even if your PR makes things marginally faster, you have to consider the tradeoff with maintainability and readability. -- In general, the code outside the core `tinygrad/` folder is not well tested, so unless the current code there is broken, you shouldn't be changing it. -- If your PR looks "complex", is a big diff, or adds lots of lines, it won't be reviewed or merged. Consider breaking it up into smaller PRs that are individually clear wins. A common pattern I see is prerequisite refactors before adding new functionality. If you can (cleanly) refactor to the point that the feature is a 3 line change, this is great, and something easy for us to review. - -Now, what we want: - -- Bug fixes (with a regression test) are great! This library isn't 1.0 yet, so if you stumble upon a bug, fix it, write a test, and submit a PR, this is valuable work. -- Solving bounties! tinygrad [offers cash bounties](https://docs.google.com/spreadsheets/d/1WKHbT-7KOgjEawq5h5Ic1qUWzpfAzuD_J06N1JwOCGs/edit?usp=sharing) for certain improvements to the library. All new code should be high quality and well tested. -- Features. However, if you are adding a feature, consider the line tradeoff. If it's 3 lines, there's less of a bar of usefulness it has to meet over something that's 30 or 300 lines. All features must have regression tests. In general with no other constraints, your feature's API should match torch or numpy. -- Refactors that are clear wins. In general, if your refactor isn't a clear win it will be closed. But some refactors are amazing! Think about readability in a deep core sense. A whitespace change or moving a few functions around is useless, but if you realize that two 100 line functions can actually use the same 110 line function with arguments while also improving readability, this is a big win. Refactors should pass [process replay](#process-replay-tests). -- Tests/fuzzers. If you can add tests that are non brittle, they are welcome. We have some fuzzers in here too, and there's a plethora of bugs that can be found with them and by improving them. Finding bugs, even writing broken tests (that should pass) with `@unittest.expectedFailure` is great. This is how we make progress. -- Dead code removal from core `tinygrad/` folder. We don't care about the code in extra, but removing dead code from the core library is great. Less for new people to read and be confused by. - -### Running tests - -You should install the pre-commit hooks with `pre-commit install`. This will run the linter, mypy, and a subset of the tests on every commit. - -For more examples on how to run the full test suite please refer to the [CI workflow](.github/workflows/test.yml). - -Some examples of running tests locally: -```sh -python3 -m pip install -e '.[testing]' # install extra deps for testing -python3 test/test_ops.py # just the ops tests -python3 -m pytest test/ # whole test suite -``` - -#### Process replay tests - -[Process replay](https://github.com/tinygrad/tinygrad/blob/master/test/external/process_replay/README.md) compares your PR's generated kernels against master. If your PR is a refactor or speedup without any expected behavior change, It should include [pr] in the pull request title. diff --git a/tinygrad/autogen_stubs.sh b/tinygrad/autogen_stubs.sh deleted file mode 100755 index f06e7ee1..00000000 --- a/tinygrad/autogen_stubs.sh +++ /dev/null @@ -1,452 +0,0 @@ -#!/bin/bash -e - -# setup instructions for clang2py -if [[ ! $(clang2py -V) ]]; then - pushd . - cd /tmp - sudo apt-get install -y --no-install-recommends clang - pip install --upgrade pip setuptools - pip install clang==14.0.6 - git clone https://github.com/nimlgen/ctypeslib.git - cd ctypeslib - pip install . - clang2py -V - popd -fi - -BASE=tinygrad/runtime/autogen/ - -fixup() { - sed -i '1s/^/# mypy: ignore-errors\n/' $1 - sed -i 's/ *$//' $1 - grep FIXME_STUB $1 || true -} - -patch_dlopen() { - path=$1; shift - name=$1; shift - cat <> $BASE/hip.py - echo "hipGetDeviceProperties = hipGetDevicePropertiesR0600" >> $BASE/hip.py - fixup $BASE/hip.py - # we can trust HIP is always at /opt/rocm/lib - #sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/hip.py - #sed -i "s\ctypes.CDLL('/opt/rocm/lib/libhiprtc.so')\ctypes.CDLL(ctypes.util.find_library('hiprtc'))\g" $BASE/hip.py - #sed -i "s\ctypes.CDLL('/opt/rocm/lib/libamdhip64.so')\ctypes.CDLL(ctypes.util.find_library('amdhip64'))\g" $BASE/hip.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/hip.py - sed -i "s\'/opt/rocm/\os.getenv('ROCM_PATH', '/opt/rocm/')+'/\g" $BASE/hip.py - python3 -c "import tinygrad.runtime.autogen.hip" -} - -generate_comgr() { - clang2py /opt/rocm/include/amd_comgr/amd_comgr.h \ - --clang-args="-D__HIP_PLATFORM_AMD__ -I/opt/rocm/include -x c++" -o $BASE/comgr.py -l /opt/rocm/lib/libamd_comgr.so - fixup $BASE/comgr.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/comgr.py - patch_dlopen $BASE/comgr.py amd_comgr "'/opt/rocm/lib/libamd_comgr.so'" "os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so'" "'/usr/local/lib/libamd_comgr.dylib'" "'/opt/homebrew/lib/libamd_comgr.dylib'" - sed -i "s\ctypes.CDLL('/opt/rocm/lib/libamd_comgr.so')\_try_dlopen_amd_comgr()\g" $BASE/comgr.py - python3 -c "import tinygrad.runtime.autogen.comgr" -} - -generate_kfd() { - clang2py /usr/include/linux/kfd_ioctl.h -o $BASE/kfd.py -k cdefstum - - fixup $BASE/kfd.py - sed -i "s/import ctypes/import ctypes, os/g" $BASE/kfd.py - sed -i "s/import fcntl, functools/import functools/g" $BASE/kfd.py - sed -i "/import functools/a from tinygrad.runtime.support.hcq import FileIOInterface" $BASE/kfd.py - sed -i "s/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, \*\*kwargs):/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, \*\*kwargs):/g" $BASE/kfd.py - sed -i "s/fcntl.ioctl(__fd, (__idir<<30)/__fd.ioctl((__idir<<30)/g" $BASE/kfd.py - sed -i "s/!!/not not /g" $BASE/kfd.py - python3 -c "import tinygrad.runtime.autogen.kfd" -} - -generate_cuda() { - clang2py /usr/include/cuda.h --clang-args="-D__CUDA_API_VERSION_INTERNAL" -o $BASE/cuda.py -l /usr/lib/x86_64-linux-gnu/libcuda.so - sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/cuda.py - sed -i "s\ctypes.CDLL('/usr/lib/x86_64-linux-gnu/libcuda.so')\ctypes.CDLL(ctypes.util.find_library('cuda'))\g" $BASE/cuda.py - fixup $BASE/cuda.py - python3 -c "import tinygrad.runtime.autogen.cuda" -} - -generate_nvrtc() { - clang2py /usr/local/cuda/include/nvrtc.h /usr/local/cuda/include/nvJitLink.h -o $BASE/nvrtc.py -l /usr/local/cuda/lib64/libnvrtc.so -l /usr/local/cuda/lib64/libnvJitLink.so - sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/nvrtc.py - sed -i "s\ctypes.CDLL('/usr/local/cuda/lib64/libnvrtc.so')\ctypes.CDLL(ctypes.util.find_library('nvrtc'))\g" $BASE/nvrtc.py - sed -i "s\ctypes.CDLL('/usr/local/cuda/lib64/libnvJitLink.so')\ctypes.CDLL(ctypes.util.find_library('nvJitLink'))\g" $BASE/nvrtc.py - fixup $BASE/nvrtc.py - python3 -c "import tinygrad.runtime.autogen.nvrtc" -} - -generate_nv() { - NVKERN_COMMIT_HASH=81fe4fb417c8ac3b9bdcc1d56827d116743892a5 - NVKERN_SRC=/tmp/open-gpu-kernel-modules-$NVKERN_COMMIT_HASH - if [ ! -d "$NVKERN_SRC" ]; then - git clone https://github.com/NVIDIA/open-gpu-kernel-modules $NVKERN_SRC - pushd . - cd $NVKERN_SRC - git reset --hard $NVKERN_COMMIT_HASH - popd - fi - - clang2py -k cdefstum \ - extra/nv_gpu_driver/clc6c0qmd.h \ - extra/nv_gpu_driver/clcec0qmd.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl0080.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl2080_notification.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc56f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc86f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc96f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc761.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl83de.h \ - $NVKERN_SRC/src/nvidia/generated/g_allclasses.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc6c0.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clcdc0.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/clc6b5.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/clc9b5.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/uvm_ioctl.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/uvm_linux_ioctl.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/hwref/ampere/ga100/dev_fault.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv_escape.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numbers.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/alloc/alloc_channel.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/nvos.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl0000/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl0080/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl2080/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl83de/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h \ - --clang-args="-include $NVKERN_SRC/src/common/sdk/nvidia/inc/nvtypes.h -I$NVKERN_SRC/src/common/inc -I$NVKERN_SRC/kernel-open/nvidia-uvm -I$NVKERN_SRC/kernel-open/common/inc -I$NVKERN_SRC/src/common/sdk/nvidia/inc -I$NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include -I$NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl" \ - -o $BASE/nv_gpu.py - fixup $BASE/nv_gpu.py - sed -i "s\(0000000001)\1\g" $BASE/nv_gpu.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/nv_gpu.py - sed -i 's/#\?\s\([A-Za-z0-9_]\+\) = MW ( \([0-9]\+\) : \([0-9]\+\) )/\1 = (\2 , \3)/' $BASE/nv_gpu.py # NVC6C0_QMDV03_00 processing - sed -i 's/#\sdef NVC6C0_QMD\([A-Za-z0-9_()]\+\):/def NVC6C0_QMD\1:/' $BASE/nv_gpu.py - sed -i 's/#\sdef NVCEC0_QMD\([A-Za-z0-9_()]\+\):/def NVCEC0_QMD\1:/' $BASE/nv_gpu.py - sed -E -i -n '/^def (NVCEC0_QMDV05_00_RELEASE)(_ENABLE)\(i\):/{p;s//\1'"0"'\2=\1\2(0)\n\1'"1"'\2=\1\2(1)/;H;b};p;${x;s/^\n//;p}' "$BASE/nv_gpu.py" - sed -i 's/#\s*return MW(\([0-9i()*+]\+\):\([0-9i()*+]\+\))/ return (\1 , \2)/' $BASE/nv_gpu.py - sed -i 's/#\?\s*\(.*\)\s*=\s*\(NV\)\?BIT\(32\)\?\s*(\s*\([0-9]\+\)\s*)/\1 = (1 << \4)/' $BASE/nv_gpu.py # name = BIT(x) -> name = (1 << x) - sed -i "s/UVM_\([A-Za-z0-9_]\+\) = \['i', '(', '\([0-9]\+\)', ')'\]/UVM_\1 = \2/" $BASE/nv_gpu.py # UVM_name = ['i', '(', '', ')'] -> UVM_name = - - # Parse status codes - sed -n '1i\ -nv_status_codes = {} -/^NV_STATUS_CODE/ { s/^NV_STATUS_CODE(\([^,]*\), *\([^,]*\), *"\([^"]*\)") *.*$/\1 = \2\nnv_status_codes[\1] = "\3"/; p }' $NVKERN_SRC/src/common/sdk/nvidia/inc/nvstatuscodes.h >> $BASE/nv_gpu.py - - python3 -c "import tinygrad.runtime.autogen.nv_gpu" -} - -generate_amd() { - # clang2py broken when pass -x c++ to prev headers - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - extra/hip_gpu_driver/nvd.h \ - extra/hip_gpu_driver/kfd_pm4_headers_ai.h \ - extra/hip_gpu_driver/soc21_enum.h \ - extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h \ - extra/hip_gpu_driver/gc_11_0_0_offset.h \ - extra/hip_gpu_driver/gc_10_3_0_offset.h \ - extra/hip_gpu_driver/sienna_cichlid_ip_offset.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/amd_gpu.py - - fixup $BASE/amd_gpu.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/amd_gpu.py - python3 -c "import tinygrad.runtime.autogen.amd_gpu" -} - -generate_hsa() { - clang2py \ - /opt/rocm/include/hsa/hsa.h \ - /opt/rocm/include/hsa/hsa_ext_amd.h \ - /opt/rocm/include/hsa/amd_hsa_signal.h \ - /opt/rocm/include/hsa/amd_hsa_queue.h \ - /opt/rocm/include/hsa/amd_hsa_kernel_code.h \ - /opt/rocm/include/hsa/hsa_ext_finalize.h /opt/rocm/include/hsa/hsa_ext_image.h \ - /opt/rocm/include/hsa/hsa_ven_amd_aqlprofile.h \ - --clang-args="-I/opt/rocm/include" \ - -o $BASE/hsa.py -l /opt/rocm/lib/libhsa-runtime64.so - - fixup $BASE/hsa.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/hsa.py - sed -i "s\ctypes.CDLL('/opt/rocm/lib/libhsa-runtime64.so')\ctypes.CDLL(os.getenv('ROCM_PATH')+'/lib/libhsa-runtime64.so' if os.getenv('ROCM_PATH') else ctypes.util.find_library('hsa-runtime64'))\g" $BASE/hsa.py - python3 -c "import tinygrad.runtime.autogen.hsa" -} - -generate_io_uring() { - clang2py -k cdefstum \ - /usr/include/liburing.h \ - /usr/include/linux/io_uring.h \ - -o $BASE/io_uring.py - - sed -r '/^#define __NR_io_uring/ s/^#define __(NR_io_uring[^ ]+) (.*)$/\1 = \2/; t; d' /usr/include/asm-generic/unistd.h >> $BASE/io_uring.py # io_uring syscalls numbers - fixup $BASE/io_uring.py -} - -generate_libc() { - clang2py -k cdefstum \ - $(dpkg -L libc6-dev | grep sys/mman.h) \ - $(dpkg -L libc6-dev | grep sys/syscall.h) \ - /usr/include/string.h \ - /usr/include/elf.h \ - /usr/include/unistd.h \ - /usr/include/asm-generic/mman-common.h \ - -o $BASE/libc.py - - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/libc.py - sed -i "s\FIXME_STUB\libc\g" $BASE/libc.py - sed -i "s\FunctionFactoryStub()\None if (libc_path := ctypes.util.find_library('c')) is None else ctypes.CDLL(libc_path, use_errno=True)\g" $BASE/libc.py - - fixup $BASE/libc.py -} - -generate_llvm() { - INC="$(llvm-config-14 --includedir)" - clang2py -k cdefstum \ - $(find "$INC/llvm-c/" -type f -name '*.h' | sort) \ - "$INC/llvm/Config/Targets.def" \ - "$INC/llvm/Config/AsmPrinters.def" \ - "$INC/llvm/Config/AsmParsers.def" \ - "$INC/llvm/Config/Disassemblers.def" \ - --clang-args="$(llvm-config-14 --cflags)" \ - -o "$BASE/llvm.py" - - sed -i "s\import ctypes\import ctypes, tinygrad.runtime.support.llvm as llvm_support\g" "$BASE/llvm.py" - sed -i "s\FIXME_STUB\llvm\g" "$BASE/llvm.py" - sed -i "s\FunctionFactoryStub()\ctypes.CDLL(llvm_support.LLVM_PATH)\g" "$BASE/llvm.py" - - fixup "$BASE/llvm.py" -} - -generate_kgsl() { - clang2py extra/qcom_gpu_driver/msm_kgsl.h -o $BASE/kgsl.py -k cdefstum - fixup $BASE/kgsl.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/kgsl.py - sed -nE 's/#define ([A-Za-z0-9_]+)_SHIFT\s*[^\S\r\n]*[0-9]*$/def \1(val): return (val << \1_SHIFT) \& \1_MASK/p' extra/qcom_gpu_driver/msm_kgsl.h >> $BASE/kgsl.py - sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\__fd.ioctl((__idir<<30)\g" $BASE/kgsl.py - python3 -c "import tinygrad.runtime.autogen.kgsl" -} - -generate_adreno() { - clang2py extra/qcom_gpu_driver/a6xx.xml.h -o $BASE/adreno.py -k cestum - sed -nE 's/#define ([A-Za-z0-9_]+)__SHIFT\s*[^\S\r\n]*[0-9]*$/def \1(val): return (val << \1__SHIFT) \& \1__MASK/p' extra/qcom_gpu_driver/a6xx.xml.h >> $BASE/adreno.py - fixup $BASE/adreno.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/adreno.py - python3 -c "import tinygrad.runtime.autogen.adreno" -} - -generate_qcom() { - clang2py -k cdefstum \ - extra/dsp/include/ion.h \ - extra/dsp/include/msm_ion.h \ - extra/dsp/include/adsprpc_shared.h \ - extra/dsp/include/remote_default.h \ - extra/dsp/include/apps_std.h \ - -o $BASE/qcom_dsp.py - - fixup $BASE/qcom_dsp.py - python3 -c "import tinygrad.runtime.autogen.qcom_dsp" -} - -generate_pci() { - clang2py -k cdefstum \ - /usr/include/linux/pci_regs.h \ - -o $BASE/pci.py - fixup $BASE/pci.py -} - -generate_vfio() { - clang2py -k cdefstum \ - /usr/include/linux/vfio.h \ - -o $BASE/vfio.py - fixup $BASE/vfio.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/vfio.py - sed -i "s\import fcntl, functools\import functools" $BASE/vfio.py - sed -i "s\import ctypes,os\a from tinygrad.runtime.support import FileIOInterface\g" $BASE/vfio.py - sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\return __fd.ioctl((__idir<<30)\g" $BASE/vfio.py -} - -generate_am() { - AMKERN_COMMIT_HASH=ceb12c04e2b5b53ec0779362831f5ee40c4921e4 - AMKERN_SRC=/tmp/ROCK-Kernel-Driver-$AMKERN_COMMIT_HASH - if [ ! -d "$AMKERN_SRC" ]; then - git clone https://github.com/ROCm/ROCK-Kernel-Driver $AMKERN_SRC --depth 1 - fi - AMKERN_AMD=$AMKERN_SRC/drivers/gpu/drm/amd/ - AMKERN_INC=$AMKERN_AMD/include/ - - clang2py -k cdefstum \ - extra/amdpci/headers/v11_structs.h \ - extra/amdpci/headers/v12_structs.h \ - extra/amdpci/headers/amdgpu_vm.h \ - extra/amdpci/headers/discovery.h \ - extra/amdpci/headers/amdgpu_ucode.h \ - extra/amdpci/headers/psp_gfx_if.h \ - extra/amdpci/headers/amdgpu_psp.h \ - extra/amdpci/headers/amdgpu_irq.h \ - extra/amdpci/headers/amdgpu_doorbell.h \ - $AMKERN_INC/soc15_ih_clientid.h \ - --clang-args="-include stdint.h" \ - -o $BASE/am/am.py - fixup $BASE/am/am.py - sed -i "s\(int64_t)\ \g" $BASE/am/am.py - sed -i "s\AMDGPU_PTE_MTYPE_VG10(2)\AMDGPU_PTE_MTYPE_VG10(0, 2)\g" $BASE/am/am.py # incorrect parsing (TODO: remove when clang2py is gone). - - clang2py -k cdefstum \ - $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \ - $AMKERN_AMD/amdgpu/soc15d.h \ - -o $BASE/am/pm4_soc15.py - fixup $BASE/am/pm4_soc15.py - - clang2py -k cdefstum \ - $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \ - $AMKERN_AMD/amdgpu/nvd.h \ - -o $BASE/am/pm4_nv.py - fixup $BASE/am/pm4_nv.py - - clang2py -k cdefstum \ - $AMKERN_INC/vega10_enum.h \ - -o $BASE/am/vega10.py - fixup $BASE/am/vega10.py - - clang2py -k cdefstum \ - $AMKERN_INC/navi10_enum.h \ - -o $BASE/am/navi10.py - fixup $BASE/am/navi10.py - - clang2py -k cdefstum \ - $AMKERN_INC/soc21_enum.h \ - -o $BASE/am/soc21.py - fixup $BASE/am/soc21.py - - clang2py -k cdefstum \ - $AMKERN_INC/soc24_enum.h \ - -o $BASE/am/soc24.py - fixup $BASE/am/soc24.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/vega10_sdma_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_4_0_0.py - fixup $BASE/am/sdma_4_0_0.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/navi10_sdma_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_5_0_0.py - fixup $BASE/am/sdma_5_0_0.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/sdma_v6_0_0_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_6_0_0.py - fixup $BASE/am/sdma_6_0_0.py - - clang2py -k cdefstum \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h \ - extra/amdpci/headers/amdgpu_smu.h \ - -o $BASE/am/smu_v13_0_0.py - fixup $BASE/am/smu_v13_0_0.py - - clang2py -k cdefstum \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h \ - extra/amdpci/headers/amdgpu_smu.h \ - --clang-args="-include stdint.h" \ - -o $BASE/am/smu_v14_0_3.py - fixup $BASE/am/smu_v14_0_3.py -} - -generate_sqtt() { - clang2py -k cdefstum \ - extra/sqtt/sqtt.h \ - -o $BASE/sqtt.py - - fixup $BASE/sqtt.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/sqtt.py - python3 -c "import tinygrad.runtime.autogen.sqtt" -} - -generate_webgpu() { - clang2py extra/webgpu/webgpu.h -o $BASE/webgpu.py - fixup $BASE/webgpu.py - sed -i "s/FIXME_STUB/webgpu/g" "$BASE/webgpu.py" - sed -i "s/FunctionFactoryStub()/ctypes.CDLL(webgpu_support.WEBGPU_PATH)/g" "$BASE/webgpu.py" - sed -i "s/import ctypes/import ctypes, tinygrad.runtime.support.webgpu as webgpu_support/g" "$BASE/webgpu.py" - python3 -c "import tinygrad.runtime.autogen.webgpu" -} - -generate_libusb() { - clang2py -k cdefstum \ - /usr/include/libusb-1.0/libusb.h \ - -o $BASE/libusb.py - - fixup $BASE/libusb.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/libusb.py - sed -i "s/FIXME_STUB/libusb/g" "$BASE/libusb.py" - sed -i "s/libusb_le16_to_cpu = libusb_cpu_to_le16//g" "$BASE/libusb.py" - sed -i "s/FunctionFactoryStub()/None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path)/g" "$BASE/libusb.py" - python3 -c "import tinygrad.runtime.autogen.libusb" -} - -if [ "$1" == "opencl" ]; then generate_opencl -elif [ "$1" == "hip" ]; then generate_hip -elif [ "$1" == "comgr" ]; then generate_comgr -elif [ "$1" == "cuda" ]; then generate_cuda -elif [ "$1" == "nvrtc" ]; then generate_nvrtc -elif [ "$1" == "hsa" ]; then generate_hsa -elif [ "$1" == "kfd" ]; then generate_kfd -elif [ "$1" == "nv" ]; then generate_nv -elif [ "$1" == "amd" ]; then generate_amd -elif [ "$1" == "am" ]; then generate_am -elif [ "$1" == "sqtt" ]; then generate_sqtt -elif [ "$1" == "qcom" ]; then generate_qcom -elif [ "$1" == "io_uring" ]; then generate_io_uring -elif [ "$1" == "libc" ]; then generate_libc -elif [ "$1" == "llvm" ]; then generate_llvm -elif [ "$1" == "kgsl" ]; then generate_kgsl -elif [ "$1" == "adreno" ]; then generate_adreno -elif [ "$1" == "pci" ]; then generate_pci -elif [ "$1" == "vfio" ]; then generate_vfio -elif [ "$1" == "webgpu" ]; then generate_webgpu -elif [ "$1" == "libusb" ]; then generate_libusb -elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc; generate_am; generate_webgpu -else echo "usage: $0 " -fi diff --git a/tinygrad/docs/CNAME b/tinygrad/docs/CNAME deleted file mode 100644 index 3ed8dab8..00000000 --- a/tinygrad/docs/CNAME +++ /dev/null @@ -1 +0,0 @@ -docs.tinygrad.org \ No newline at end of file diff --git a/tinygrad/docs/abstractions2.py b/tinygrad/docs/abstractions2.py deleted file mode 100644 index 3c19e463..00000000 --- a/tinygrad/docs/abstractions2.py +++ /dev/null @@ -1,135 +0,0 @@ -# tinygrad is a tensor library, and as a tensor library it has multiple parts -# 1. a "runtime". this allows buffer management, compilation, and running programs -# 2. a "Device" that uses the runtime but specifies compute in an abstract way for all -# 3. a "UOp" that fuses the compute into kernels, using memory only when needed -# 4. a "Tensor" that provides an easy to use frontend with autograd ".backward()" - - -print("******** first, the runtime ***********") - -from tinygrad.runtime.ops_cpu import ClangJITCompiler, MallocAllocator, CPUProgram - -# allocate some buffers -out = MallocAllocator.alloc(4) -a = MallocAllocator.alloc(4) -b = MallocAllocator.alloc(4) - -# load in some values (little endian) -MallocAllocator._copyin(a, memoryview(bytearray([2,0,0,0]))) -MallocAllocator._copyin(b, memoryview(bytearray([3,0,0,0]))) - -# compile a program to a binary -lib = ClangJITCompiler().compile("void add(int *out, int *a, int *b) { out[0] = a[0] + b[0]; }") - -# create a runtime for the program -fxn = CPUProgram("add", lib) - -# run the program -fxn(out, a, b) - -# check the data out -print(val := MallocAllocator._as_buffer(out).cast("I").tolist()[0]) -assert val == 5 - - -print("******** second, the Device ***********") - -DEVICE = "CPU" # NOTE: you can change this! - -import struct -from tinygrad.dtype import dtypes -from tinygrad.device import Buffer, Device -from tinygrad.uop.ops import UOp, Ops -from tinygrad.shape.shapetracker import ShapeTracker - -# allocate some buffers + load in values -out = Buffer(DEVICE, 1, dtypes.int32).allocate() -a = Buffer(DEVICE, 1, dtypes.int32).allocate().copyin(memoryview(bytearray(struct.pack("I", 2)))) -b = Buffer(DEVICE, 1, dtypes.int32).allocate().copyin(memoryview(bytearray(struct.pack("I", 3)))) -# NOTE: a._buf is the same as the return from MallocAllocator.alloc - -# describe the computation -buf_1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 1) -buf_2 = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 2) -ld_1 = UOp(Ops.LOAD, dtypes.int32, (buf_1.view(ShapeTracker.from_shape((1,))),)) -ld_2 = UOp(Ops.LOAD, dtypes.int32, (buf_2.view(ShapeTracker.from_shape((1,))),)) -alu = ld_1 + ld_2 -output_buf = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 0) -st_0 = UOp(Ops.STORE, dtypes.void, (output_buf.view(ShapeTracker.from_shape((1,))), alu)) -s = UOp(Ops.SINK, dtypes.void, (st_0,)) - -# convert the computation to a "linearized" format (print the format) -from tinygrad.engine.realize import get_kernel, CompiledRunner -kernel = get_kernel(Device[DEVICE].renderer, s).linearize() - -# compile a program (and print the source) -fxn = CompiledRunner(kernel.to_program()) -print(fxn.p.src) -# NOTE: fxn.clprg is the CPUProgram - -# run the program -fxn.exec([out, a, b]) - -# check the data out -assert out.as_buffer().cast('I')[0] == 5 - - -print("******** third, the UOp ***********") - -from tinygrad.engine.realize import run_schedule -from tinygrad.engine.schedule import create_schedule_with_vars -from tinygrad.engine.grouper import get_kernelize_map - -# allocate some values + load in values -a = UOp.new_buffer(DEVICE, 1, dtypes.int32) -b = UOp.new_buffer(DEVICE, 1, dtypes.int32) -a.buffer.allocate().copyin(memoryview(bytearray(struct.pack("I", 2)))) -b.buffer.allocate().copyin(memoryview(bytearray(struct.pack("I", 3)))) - -# describe the computation -out = a + b -s = UOp(Ops.SINK, dtypes.void, (out,)) - -# group the computation into kernels -becomes_map = get_kernelize_map(s) - -# the compute maps to an assign -assign = becomes_map[a+b] - -# the first source is the output buffer (data) -assert assign.src[0].op is Ops.BUFFER -# the second source is the kernel (compute) -assert assign.src[1].op is Ops.KERNEL - -# schedule the kernel graph in a linear list -s = UOp(Ops.SINK, dtypes.void, (assign,)) -sched, _ = create_schedule_with_vars(s) -assert len(sched) == 1 - -# DEBUGGING: print the compute ast -print(sched[-1].ast) -# NOTE: sched[-1].ast is the same as st_0 above - -# the output will be stored in a new buffer -out = assign.buf_uop -assert out.op is Ops.BUFFER and not out.buffer.is_allocated() -print(out) - -# run that schedule -run_schedule(sched) - -# check the data out -assert out.is_realized and out.buffer.as_buffer().cast('I')[0] == 5 - - -print("******** fourth, the Tensor ***********") - -from tinygrad import Tensor - -a = Tensor([2], dtype=dtypes.int32, device=DEVICE) -b = Tensor([3], dtype=dtypes.int32, device=DEVICE) -out = a + b - -# check the data out -print(val:=out.item()) -assert val == 5 diff --git a/tinygrad/docs/abstractions3.py b/tinygrad/docs/abstractions3.py deleted file mode 100644 index c34a399b..00000000 --- a/tinygrad/docs/abstractions3.py +++ /dev/null @@ -1,62 +0,0 @@ -# abstractions2 goes from back to front, here we will go from front to back -from typing import List -from tinygrad.helpers import tqdm - -# ***** -# 0. Load mnist on the device - -from tinygrad.nn.datasets import mnist -X_train, Y_train, _, _ = mnist() -X_train = X_train.float() -X_train -= X_train.mean() - -# ***** -# 1. Define an MNIST model. - -from tinygrad import Tensor - -l1 = Tensor.kaiming_uniform(128, 784) -l2 = Tensor.kaiming_uniform(10, 128) -def model(x): return x.flatten(1).dot(l1.T).relu().dot(l2.T) -l1n, l2n = l1.numpy(), l2.numpy() - -# ***** -# 2. Choose a batch for training and do the backward pass. - -from tinygrad.nn.optim import SGD -optim = SGD([l1, l2]) - -Tensor.training = True -X, Y = X_train[(samples:=Tensor.randint(128, high=X_train.shape[0]))], Y_train[samples] -optim.zero_grad() -model(X).sparse_categorical_crossentropy(Y).backward() -optim.schedule_step() # this will step the optimizer without running realize - -# ***** -# 3. Create a schedule. - -# The weight Tensors have been assigned to, but not yet realized. Everything is still lazy at this point -# l1.uop and l2.uop define a computation graph - -from tinygrad.engine.schedule import ScheduleItem -schedule: List[ScheduleItem] = Tensor.schedule(l1, l2) - -print(f"The schedule contains {len(schedule)} items.") -for si in schedule: print(str(si)[:80]) - -# ***** -# 4. Lower a schedule. - -from tinygrad.engine.realize import lower_schedule_item, ExecItem -lowered: List[ExecItem] = [lower_schedule_item(si) for si in tqdm(schedule)] - -# ***** -# 5. Run the schedule - -for ei in tqdm(lowered): ei.run() - -# ***** -# 6. Print the weight change - -print("first weight change\n", l1.numpy()-l1n) -print("second weight change\n", l2.numpy()-l2n) diff --git a/tinygrad/docs/developer/am.md b/tinygrad/docs/developer/am.md deleted file mode 100644 index 30843618..00000000 --- a/tinygrad/docs/developer/am.md +++ /dev/null @@ -1,39 +0,0 @@ -# AM Driver - -AM driver is a userspace driver targeting AMD's RDNA3/RDNA4. You only need tinygrad to send compute tasks to your GPU! - -## How to run? -Make sure that amdgpu module is unloaded and just run tinygrad with `AMD=1`! - -Optional requirements: - -* System without IOMMU for P2P / SDMA support -* vfio-pci module for IRQ handling - -## Environment Variables - -| Variable | Possible Value(s) | Description | -|----------|------------------|-------------| -| AM_RESET | [1] | Performs a full GPU reset (reloading all firmware and IP blocks) | -| AM_DEBUG | [0-4] | Sets the level of additional debugging information | - -## AM Driver Details - -### Compute & SDMA Queues - -AM binds compute queues directly to MEC (bypassing MES). Tinygrad uses only one compute queue, which is bound at `pipe=0 queue=0`. Similarly, the single SDMA queue is bound at `engine=0 queue=0`. - -### Boot - -The GPU being passed can be in one of several states: -1. Not initialized -2. Initialized by amdgpu -3. Initialized by AM - -The first and second states require a full GPU setup since their states are unknown. The second state also requires a mode1 reset to reinitialize all components. - -The third state can be set up partially to optimize boot time. In this case, only the GFX and SDMA IPs need to be initialized. To enable this, AM uses a separate boot memory that is guaranteed not to be overwritten. This physical memory is utilized for all blocks that are initialized only during the initial AM boot. To determine if the GPU is in the third state, AM uses `regSCRATCH_REG7` as a flag. - -### VM Management - -Each AM device sets up only a single `VMID=0` and one page directory. The page directory used is 3-level and thus supports up to 512GB of virtual addresses. All AM devices are located in one virtual address space. \ No newline at end of file diff --git a/tinygrad/docs/developer/developer.md b/tinygrad/docs/developer/developer.md deleted file mode 100644 index f932f0a9..00000000 --- a/tinygrad/docs/developer/developer.md +++ /dev/null @@ -1,54 +0,0 @@ -The tinygrad framework has four pieces - -* a PyTorch like frontend. -* a scheduler which breaks the compute into kernels. -* a lowering engine which converts ASTs into code that can run on the accelerator. -* an execution engine which can run that code. - -There is a good [bunch of tutorials](https://mesozoic-egg.github.io/tinygrad-notes/) by Di Zhu that go over tinygrad internals. - -There's also a [doc describing speed](../developer/speed.md) - -## Frontend - -Everything in [Tensor](../tensor/index.md) is syntactic sugar around constructing a graph of [UOps](../developer/uop.md). - -The `UOp` graph specifies the compute in terms of low level tinygrad ops. Not all UOps will actually become realized. There's two types of UOps, base and view. base contains compute into a contiguous buffer, and view is a view (specified by a ShapeTracker). Inputs to a base can be either base or view, inputs to a view can only be a single base. - -## Scheduling - -The [scheduler](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/engine/schedule.py) converts the graph of UOps into a list of `ScheduleItem`. One `ScheduleItem` is one kernel on the GPU, and the scheduler is responsible for breaking the large compute graph into subgraphs that can fit in a kernel. `ast` specifies what compute to run, and `bufs` specifies what buffers to run it on. - -::: tinygrad.engine.schedule.ScheduleItem - -## Lowering - -The code in [realize](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/engine/realize.py) lowers `ScheduleItem` to `ExecItem` with - -::: tinygrad.engine.realize.lower_schedule - -There's a ton of complexity hidden behind this, see the `codegen/` directory. - -First we lower the AST to UOps, which is a linear list of the compute to be run. This is where the BEAM search happens. - -Then we render the UOps into code with a `Renderer`, then we compile the code to binary with a `Compiler`. - -## Execution - -Creating `ExecItem`, which has a run method - -::: tinygrad.engine.realize.ExecItem - options: - members: true - -Lists of `ExecItem` can be condensed into a single ExecItem with the Graph API (rename to Queue?) - -## Runtime - -Runtimes are responsible for device-specific interactions. They handle tasks such as initializing devices, allocating memory, loading/launching programs, and more. You can find more information about the runtimes API on the [runtime overview page](runtime.md). - -All runtime implementations can be found in the [runtime directory](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime). - -### HCQ Compatible Runtimes - -HCQ API is a lower-level API for defining runtimes. Interaction with HCQ-compatible devices occurs at a lower level, with commands issued directly to hardware queues. Some examples of such backends are [NV](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_nv.py) and [AMD](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_amd.py), which are userspace drivers for NVIDIA and AMD devices respectively. You can find more information about the API on [HCQ overview page](hcq.md) diff --git a/tinygrad/docs/developer/hcq.md b/tinygrad/docs/developer/hcq.md deleted file mode 100644 index 33655ab7..00000000 --- a/tinygrad/docs/developer/hcq.md +++ /dev/null @@ -1,128 +0,0 @@ -# HCQ Compatible Runtime - -## Overview - -The main aspect of HCQ-compatible runtimes is how they interact with devices. In HCQ, all interactions with devices occur in a hardware-friendly manner using [command queues](#command-queues). This approach allows commands to be issued directly to devices, bypassing runtime overhead such as HIP or CUDA. Additionally, by using the HCQ API, these runtimes can benefit from various optimizations and features, including [HCQGraph](#hcqgraph) and built-in profiling capabilities. - -### Command Queues - -To interact with devices you create a `HWQueue`. Some methods are required, like timestamp and synchronization methods like [signal](#tinygrad.runtime.support.hcq.HWQueue.signal) and [wait](#tinygrad.runtime.support.hcq.HWQueue.wait), while others are dependent on it being a compute or copy queue. - -For example, the following Python code enqueues a wait, execute, and signal command on the HCQ-compatible device: -```python -HWQueue().wait(signal_to_wait, value_to_wait) \ - .exec(program, args_state, global_dims, local_dims) \ - .signal(signal_to_fire, value_to_fire) \ - .submit(your_device) -``` - -Each runtime should implement the required functions that are defined in the `HWQueue` classes. - -::: tinygrad.runtime.support.hcq.HWQueue - options: - members: [ - "signal", - "wait", - "timestamp", - "bind", - "submit", - "memory_barrier", - "exec", - "copy", - ] - show_source: false - -### HCQ Compatible Device - -The `HCQCompiled` class defines the API for HCQ-compatible devices. This class serves as an abstract base class that device-specific implementations should inherit from and implement. - -::: tinygrad.runtime.support.hcq.HCQCompiled - options: - show_source: false - -#### Signals - -Signals are device-dependent structures used for synchronization and timing in HCQ-compatible devices. They should be designed to record both a `value` and a `timestamp` within the same signal. HCQ-compatible backend implementations should use `HCQSignal` as a base class. - -::: tinygrad.runtime.support.hcq.HCQSignal - options: - members: [value, timestamp, wait] - show_source: false - -The following Python code demonstrates the usage of signals: - -```python -signal = your_device.signal_t() - -HWQueue().timestamp(signal) \ - .signal(signal, value_to_fire) \ - .submit(your_device) - -signal.wait(value_to_fire) -signaled_value = signal.value # should be the same as `value_to_fire` -timestamp = signal.timestamp -``` - -##### Synchronization signals - -Each HCQ-compatible device must allocate two signals for global synchronization purposes. These signals are passed to the `HCQCompiled` base class during initialization: an active timeline signal `self.timeline_signal` and a shadow timeline signal `self._shadow_timeline_signal` which helps to handle signal value overflow issues. You can find more about synchronization in the [synchronization section](#synchronization) - -### HCQ Compatible Allocator - -The `HCQAllocator` base class simplifies allocator logic by leveraging [command queues](#command-queues) abstractions. This class efficiently handles copy and transfer operations, leaving only the alloc and free functions to be implemented by individual backends. - -::: tinygrad.runtime.support.hcq.HCQAllocator - options: - members: [ - "_alloc", - "_free", - ] - show_source: false - -#### HCQ Allocator Result Protocol - -Backends must adhere to the `HCQBuffer` protocol when returning allocation results. - -::: tinygrad.runtime.support.hcq.HCQBuffer - options: - members: true - show_source: false - -### HCQ Compatible Program - -`HCQProgram` is a base class for defining programs compatible with HCQ-enabled devices. It provides a flexible framework for handling different argument layouts (see `HCQArgsState`). - -::: tinygrad.runtime.support.hcq.HCQProgram - options: - members: true - show_source: false - -#### Arguments State - -`HCQArgsState` is a base class for managing the argument state for HCQ programs. Backend implementations should create a subclass of `HCQArgsState` to manage arguments for the given program. - -::: tinygrad.runtime.support.hcq.HCQArgsState - options: - members: true - show_source: false - -**Lifetime**: The `HCQArgsState` is passed to `HWQueue.exec` and is guaranteed not to be freed until `HWQueue.submit` for the same queue is called. - -### Synchronization - -HCQ-compatible devices use a global timeline signal for synchronizing all operations. This mechanism ensures proper ordering and completion of tasks across the device. By convention, `self.timeline_value` points to the next value to signal. So, to wait for all previous operations on the device to complete, wait for `self.timeline_value - 1` value. The following Python code demonstrates the typical usage of signals to synchronize execution to other operations on the device: - -```python -HWQueue().wait(your_device.timeline_signal, your_device.timeline_value - 1) \ - .exec(...) - .signal(your_device.timeline_signal, your_device.next_timeline()) \ - .submit(your_device) - -# Optionally wait for execution -your_device.timeline_signal.wait(your_device.timeline_value - 1) -``` - -## HCQGraph - -[HCQGraph](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/graph/hcq.py) is a core feature that implements `GraphRunner` for HCQ-compatible devices. `HCQGraph` builds static `HWQueue` for all operations per device. To optimize enqueue time, only the necessary parts of the queues are updated for each run using the symbolic variables, avoiding a complete rebuild. -Optionally, queues can implement a `bind` API, which allows further optimization by eliminating the need to copy the queues into the device ring. diff --git a/tinygrad/docs/developer/kernelize.md b/tinygrad/docs/developer/kernelize.md deleted file mode 100644 index b38db222..00000000 --- a/tinygrad/docs/developer/kernelize.md +++ /dev/null @@ -1,109 +0,0 @@ -# Kernel Creation - -Tinygrad lazily builds up a graph of Tensor operations. The Tensor graph includes a mix of: - -- Buffer and Assignment Ops: `BUFFER`, `BUFFER_VIEW`, `COPY`, `ASSIGN` -- Movement Ops: `RESHAPE`, `EXPAND`, `PERMUTE`, `PAD`, `SHRINK`, `FLIP` -- Compute Ops: `ADD`, `MUL`, `REDUCE_AXIS`, ... - -`Tensor.kernelize` creates the kernels and buffers needed to realize the output Tensor(s). - -## Kernelize flow - -Let's see how a multiply add Tensor graph becomes a fused elementwise kernel. - -```py -# initialize 3 input buffers on the device -a = Tensor([1]).realize() -b = Tensor([2]).realize() -c = Tensor([3]).realize() - -# create the Tensor graph -mul = a*b -out = mul+c - -print(mul) # , None)> on METAL with grad None> -print(out) # , None)> on METAL with grad None> - -out.kernelize() - -print(mul) # , None)> on METAL with grad None> -print(out) # , None)> on METAL with grad None> -``` - -The multiply Tensor stays the same because it is fused. The output Tensor's UOp becomes a new ASSIGN UOp: - -```py -print(out.uop) -``` - -The first source is the output BUFFER: - -``` -UOp(Ops.BUFFER, dtypes.int, arg=1, src=( - UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()), - UOp(Ops.UNIQUE, dtypes.void, arg=6, src=()),)) -``` - -And the second source is the KERNEL and its 4 buffer edges (output_buffer, a, b, c): - -``` -UOp(Ops.KERNEL, dtypes.void, arg=,) (__add__, __mul__)>, src=( - UOp(Ops.BUFFER, dtypes.int, arg=1, src=( - x1:=UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()), - UOp(Ops.UNIQUE, dtypes.void, arg=6, src=()),)), - UOp(Ops.BUFFER, dtypes.int, arg=1, src=( - x1, - UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()),)), - UOp(Ops.BUFFER, dtypes.int, arg=1, src=( - x1, - UOp(Ops.UNIQUE, dtypes.void, arg=3, src=()),)), - UOp(Ops.BUFFER, dtypes.int, arg=1, src=( - x1, - UOp(Ops.UNIQUE, dtypes.void, arg=5, src=()),)),)) -``` - -KERNEL describes the compute AST, metadata and memory dependencies. - -BUFFER holds a reference to the device memory where the output will be stored. - -Once a Tensor is kernelized, all children will LOAD its BUFFER, instead of fusing it: - -```py -child = out+2 -child.kernelize() -print(child.uop.src[1].arg.ast) -``` - -``` -UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=0, src=()), - x2:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()), - x2,)), - UOp(Ops.CONST, dtypes.int, arg=2, src=( - x2,)),)),)),)) -``` - -`Tensor.realize` will execute the kernels and write outputs to memory: - -```py -Tensor.realize(out) -print(out) # , )> on METAL with grad None> -print(out.item()) # 5 -``` - -
- -**Summary** - -- The large Tensor graph is built from a mix of data, compute and movement Ops. - -- `Tensor.kernelize` splits the Tensor graph into data (BUFFER), compute (KERNEL) and links dependencies with ASSIGN. - -- `Tensor.realize` executes KERNELs on device and replaces the Tensor graph with just a BUFFER. - -- Kernelize can be called multiple times on a Tensor. This allows for incrementally building the kernel fusion layout of a large Tensor graph, without having to call `realize` or `schedule`. diff --git a/tinygrad/docs/developer/runtime.md b/tinygrad/docs/developer/runtime.md deleted file mode 100644 index b246dfeb..00000000 --- a/tinygrad/docs/developer/runtime.md +++ /dev/null @@ -1,51 +0,0 @@ -# Runtime Overview - -## Overview - -A typical runtime consists of the following parts: - -- [Compiled](#compiled) -- [Allocator](#allocator) -- [Program](#program) -- [Compiler](#compiler) - -### Compiled - -The `Compiled` class is responsible for initializing and managing a device. - -::: tinygrad.device.Compiled - options: - members: [ - "synchronize" - ] - show_source: false - -### Allocator - -The `Allocator` class is responsible for managing memory on the device. There is also a version called the `LRUAllocator`, which caches allocated buffers to optimize performance. - -::: tinygrad.device.Allocator - options: - members: true - show_source: false - -::: tinygrad.device.LRUAllocator - options: - members: true - show_source: false - -### Program - -The `Program` class is created for each loaded program. It is responsible for executing the program on the device. As an example, here is a `CPUProgram` implementation which loads program and runs it. - -::: tinygrad.runtime.ops_cpu.CPUProgram - options: - members: true - -### Compiler - -The `Compiler` class compiles the output from the `Renderer` and produces it in a device-specific format. - -::: tinygrad.device.Compiler - options: - members: true diff --git a/tinygrad/docs/developer/speed.md b/tinygrad/docs/developer/speed.md deleted file mode 100644 index 5d24c8c3..00000000 --- a/tinygrad/docs/developer/speed.md +++ /dev/null @@ -1,71 +0,0 @@ -# speed in tinygrad - -## Overview - -Speed refers to many different things. To break it down to four, there's: - -- Compile Speed (Python) -- Execution Speed (driver) -- Model Speed (scheduler) -- Kernel Speed (codegen) - -## Compile Speed (Python) - -This is how long the first run of your model takes. It's limited largely by the runtime of the Python doing UOp rewrites. Currently it's a bit slow, but on par with torch.compile. It gets even slower if you are using BEAM, since that's compiling many variants of each kernel. - -This will be improved by writing faster graph_rewrite, doing less graph_rewrite, and better parallelization. - -## Execution Speed (driver) - -After your model is compiled, you are often using the `TinyJIT`. tinygrad has the best execution speed of any framework because it usually bypasses the GPU driver and prebuilds the command queue. It's tons faster than normal CUDA, and often even faster than CUDA Graph. - -There's very little to improve here, as this is almost never the bottleneck. - -## Model Speed (scheduler) - -The scheduler determines how operations are grouped into kernels and which Tensors are written to memory. This is currently a big bottleneck of training speed. - -The decisions are often not obvious. For example, when is it worth recomputing an arithmetic operation instead of storing and loading from memory? Example: - -```python -from tinygrad import Tensor -a = Tensor.rand(100) -b = Tensor.rand(100) -c = Tensor.rand(100) -d = Tensor.rand(100) -out1 = a+b+c -out2 = a+b+d -Tensor.realize(out1, out2) -``` - -The real answer is obvious, compute both `out1` and `out2` in the same kernel. But you can't always do that. If you can't, should `a+b` first be saved to a subbuffer? Or should both the `out1` and `out2` kernels recompute `a+b`? - -In this case: with recompute (6 reads + 2 writes), no recompute (6 reads + 3 writes), so we should probably recompute. However, once you add movement ops and casts this is even harder to figure out. tinygrad doesn't yet have a systematic way to do it. - -## Kernel Speed (codegen) - -Given that you have decided how the model ops will be grouped and what will be written to memory, kernel speed determines how fast that operation is done. This is what BEAM changes, it searches over a set of equivalent kernels which all perform the same operation and finds the one which performs the task the fastest. - -In `kernel.py` we have a set of `OptOps`, these control the parameters of the speed optimizations applied to the kernel. - -### Memory - -The main bottleneck in most kernels is accessing memory. In a freshman algorithms class, you'll learn about cache aware matrix multiplication, and this is all forms of that. While the same math is run, the order in which you run it can have large impacts on the speed depending on if the data you are loading. OptOps will change this order. - -Memory, even cache, is often much slower than accessing the register file. The amount of times data is used in math is called the "arithmetic intensity". For operations like BS=1 GEMV, the arithmetic intensity is 1, but for GEMMs and convs it can be much higher. OptOps like UPCAST and UNROLL can increase this, but be careful of making them too large, as if there's too much register pressure on the GPU the warp scheduler may not be able to fit many warps, or even worse, it could be spilling to local memory. - -4090s have 1 TB/s of ram bandwidth and ~160 TFLOPS of compute, so you need to use each loaded value ~100 times. The L1 cache has around 40 TB/s of bandwidth, so in order to get full compute utilization you need to use each value ~4 times. - -A lot of work can still be done here. For example, we never copy the inputs to on chip SRAM, but this is often quite helpful for kernel speed. Also, we aren't doing a good job with L2 cache awareness (the locals handle L1 quite well) - -### Tensor Cores - -Many accelerators have Tensor Cores / MAC arrays / systolic arrays. The main value of these is that, since they are 2-D, they create an n^2 ratio between the compute and the input data. - -GPUs use Tensor Cores instead of MAC arrays to fit better in the GPU warp paradigm. This is because the output of Tensor Cores is O(n) wrt the input, while the output of MAC arrays like the AMX is O(n^2) - -We have a simple framework in tinygrad for adding these ALU blocks and achieving good performance from them. - -### Indexing - -Indexing determines the address of the memory we need to load. GPUs often have less integer math resources than floating point math, so this can sometimes be the bottleneck. We have a symbolic math engine in our rewrite rules to simplify indexing before it's emitted to the kernel. Newer NVIDIA GPUs have a "Tensor Memory Accelerator" to assist with fast indexing, however, this is not supported in tinygrad yet. diff --git a/tinygrad/docs/developer/uop.md b/tinygrad/docs/developer/uop.md deleted file mode 100644 index 5562df2f..00000000 --- a/tinygrad/docs/developer/uop.md +++ /dev/null @@ -1,11 +0,0 @@ -::: tinygrad.uop.ops.UOp - options: - members: false - members_order: source - show_labels: false - -::: tinygrad.uop.ops.Ops - options: - members: true - members_order: source - show_labels: false diff --git a/tinygrad/docs/dtypes.md b/tinygrad/docs/dtypes.md deleted file mode 100644 index dc82e52f..00000000 --- a/tinygrad/docs/dtypes.md +++ /dev/null @@ -1,9 +0,0 @@ -::: tinygrad.dtype.DType - -::: tinygrad.dtype.dtypes - options: - members: true - members_order: source - show_labels: false - -::: tinygrad.dtype.ConstType \ No newline at end of file diff --git a/tinygrad/docs/env_vars.md b/tinygrad/docs/env_vars.md deleted file mode 100644 index 74d1351e..00000000 --- a/tinygrad/docs/env_vars.md +++ /dev/null @@ -1,64 +0,0 @@ -# List of environment variables that control tinygrad behavior. - -This is a list of environment variable that control the runtime behavior of tinygrad and its examples. -Most of these are self-explanatory, and are usually used to set an option at runtime. - -Example: `GPU=1 DEBUG=4 python3 -m pytest` - -However you can also decorate a function to set a value only inside that function. - -```python -# in tensor.py (probably only useful if you are a tinygrad developer) -@Context(DEBUG=4) -def numpy(self) -> ... -``` - -Or use contextmanager to temporarily set a value inside some scope: - -```python -with Context(DEBUG=0): - a = Tensor.ones(10, 10) - a *= 2 -``` - -## Global Variables -The columns of this list are are: Variable, Possible Value(s) and Description. - -- A `#` means that the variable can take any integer value. - -These control the behavior of core tinygrad even when used as a library. - -Variable | Possible Value(s) | Description ----|---|--- -DEBUG | [1-7] | enable debugging output (operations, timings, speed, generated code and more) -GPU | [1] | enable the GPU (OpenCL) backend -CUDA | [1] | enable CUDA backend -AMD | [1] | enable AMD backend -NV | [1] | enable NV backend -METAL | [1] | enable Metal backend (for Mac M1 and after) -CPU | [1] | enable CPU (Clang) backend -LLVM | [1] | enable LLVM backend -BEAM | [#] | number of beams in kernel beam search -DEFAULT_FLOAT | [HALF, ...]| specify the default float dtype (FLOAT32, HALF, BFLOAT16, FLOAT64, ...), default to FLOAT32 -IMAGE | [1-2] | enable 2d specific optimizations -FLOAT16 | [1] | use float16 for images instead of float32 -PTX | [1] | enable the specialized [PTX](https://docs.nvidia.com/cuda/parallel-thread-execution/) assembler for Nvidia GPUs. If not set, defaults to generic CUDA codegen backend. -PROFILE | [1] | enable profiling. This feature is supported in NV, AMD, QCOM and METAL backends. -VISIBLE_DEVICES | [list[int]]| restricts the NV/AMD devices that are available. The format is a comma-separated list of identifiers (indexing starts with 0). -JIT | [0-2] | 0=disabled, 1=[jit enabled](quickstart.md#jit) (default), 2=jit enabled, but graphs are disabled -VIZ | [1] | 0=disabled, 1=[viz enabled](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/viz) -ALLOW_TF32 | [1] | enable TensorFloat-32 tensor cores on Ampere or newer GPUs. -WEBGPU_BACKEND | [WGPUBackendType_Metal, ...] | Force select a backend for WebGPU (Metal, DirectX, OpenGL, Vulkan...) -CUDA_PATH | str | Use `CUDA_PATH/include` for CUDA headers for CUDA and NV backends. If not set, TinyGrad will use `/usr/local/cuda/include`, `/usr/include` and `/opt/cuda/include`. - -## Debug breakdown - -Variable | Value | Description ----|---|--- -DEBUG | >= 1 | Enables debugging and lists devices being used -DEBUG | >= 2 | Provides performance metrics for operations, including timing, memory usage, bandwidth for each kernel execution -DEBUG | >= 3 | Outputs buffers used for each kernel (shape, dtype and strides) and the applied optimizations at a kernel level -DEBUG | >= 4 | Outputs the generated kernel code -DEBUG | >= 5 | Displays the intermediate representation of the computation UOps (AST) -DEBUG | >= 6 | Displays the intermediate representation of the computation UOps in a linearized manner, detailing the operation sequence -DEBUG | >= 7 | Outputs the assembly code generated for the target hardware diff --git a/tinygrad/docs/favicon.svg b/tinygrad/docs/favicon.svg deleted file mode 100644 index 420a33e0..00000000 --- a/tinygrad/docs/favicon.svg +++ /dev/null @@ -1,25 +0,0 @@ - - - - diff --git a/tinygrad/docs/index.md b/tinygrad/docs/index.md deleted file mode 100644 index f80c1242..00000000 --- a/tinygrad/docs/index.md +++ /dev/null @@ -1,53 +0,0 @@ -# tinygrad documentation - -Welcome to the docs for tinygrad. This page is for users of the tinygrad library. tinygrad is not 1.0 yet, but it will be soon. The API has been pretty stable for a while. - -While you can `pip install tinygrad`, we encourage you to install from source: - -```bash -git clone https://github.com/tinygrad/tinygrad.git -cd tinygrad -python3 -m pip install -e . -``` - -After you have installed tinygrad, try the [MNIST tutorial](mnist.md). - -If you are new to tensor libraries, learn how to use them by solving puzzles from [tinygrad-tensor-puzzles](https://github.com/obadakhalili/tinygrad-tensor-puzzles). - -We also have [developer docs](developer/developer.md), and Di Zhu has created a [bunch of tutorials](https://mesozoic-egg.github.io/tinygrad-notes/) to help understand how tinygrad works. - -## tinygrad Usage - -The main class you will interact with is [Tensor](tensor/index.md). It functions very similarly to PyTorch, but has a bit more of a functional style. tinygrad supports [many datatypes](dtypes.md). All operations in tinygrad are lazy, meaning they won't do anything until you realize. - -* tinygrad has a built in [neural network library](nn.md) with some classes, optimizers, and load/save state management. -* tinygrad has a JIT to make things fast. Decorate your pure function with `TinyJit` -* tinygrad has amazing support for multiple GPUs, allowing you to shard your Tensors with `Tensor.shard` - -To understand what training looks like in tinygrad, you should read `beautiful_mnist.py` - -We have a [quickstart guide](quickstart.md) and a [showcase](showcase.md) - -## tinygrad Stack - -Tinygrad vs others - -## Differences from PyTorch - -If you are migrating from PyTorch, welcome. Most of the API is the same. We hope you will find tinygrad both familiar and somehow more "correct feeling" - -### tinygrad doesn't have nn.Module - -There's nothing special about a "Module" class in tinygrad, it's just a normal class. [`nn.state.get_parameters`](nn.md/#tinygrad.nn.state.get_parameters) can be used to recursively search normal classes for valid tensors. Instead of the `forward` method in PyTorch, tinygrad just uses `__call__` - -### tinygrad is functional - -In tinygrad, you can do [`x.conv2d(w, b)`](tensor/ops.md/#tinygrad.Tensor.conv2d) or [`x.sparse_categorical_crossentropy(y)`](tensor/ops.md/#tinygrad.Tensor.sparse_categorical_crossentropy). We do also have a [`Conv2D`](nn.md/#tinygrad.nn.Conv2d) class like PyTorch if you want a place to keep the state, but all stateless operations don't have classes. - -### tinygrad is lazy - -When you do `a+b` in tinygrad, nothing happens. It's not until you [`realize`](tensor/properties.md#tinygrad.Tensor.realize) the Tensor that the computation actually runs. - -### tinygrad requires @TinyJit to be fast - -PyTorch spends a lot of development effort to make dispatch very fast. tinygrad doesn't. We have a simple decorator that will replay the kernels used in the decorated function. diff --git a/tinygrad/docs/logo_tiny_dark.svg b/tinygrad/docs/logo_tiny_dark.svg deleted file mode 100644 index a5aa3f22..00000000 --- a/tinygrad/docs/logo_tiny_dark.svg +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - \ No newline at end of file diff --git a/tinygrad/docs/logo_tiny_light.svg b/tinygrad/docs/logo_tiny_light.svg deleted file mode 100644 index 8c853793..00000000 --- a/tinygrad/docs/logo_tiny_light.svg +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - \ No newline at end of file diff --git a/tinygrad/docs/mnist.md b/tinygrad/docs/mnist.md deleted file mode 100644 index ce55890e..00000000 --- a/tinygrad/docs/mnist.md +++ /dev/null @@ -1,185 +0,0 @@ -# MNIST Tutorial - -After you have installed tinygrad, this is a great first tutorial. - -Start up a notebook locally, or use [colab](https://colab.research.google.com/). tinygrad is very lightweight, so it's easy to install anywhere and doesn't need a special colab image, but for speed we recommend a T4 GPU image. - -### One-liner to install tinygrad in colab - -```python -!pip install git+https://github.com/tinygrad/tinygrad.git -``` - -### What's the default device? - -```python -from tinygrad import Device -print(Device.DEFAULT) -``` - -You will see `CUDA` here on a GPU instance, or `CPU` here on a CPU instance. - -## A simple model - -We'll use the model from [the Keras tutorial](https://keras.io/examples/vision/mnist_convnet/). - -```python -from tinygrad import Tensor, nn - -class Model: - def __init__(self): - self.l1 = nn.Conv2d(1, 32, kernel_size=(3,3)) - self.l2 = nn.Conv2d(32, 64, kernel_size=(3,3)) - self.l3 = nn.Linear(1600, 10) - - def __call__(self, x:Tensor) -> Tensor: - x = self.l1(x).relu().max_pool2d((2,2)) - x = self.l2(x).relu().max_pool2d((2,2)) - return self.l3(x.flatten(1).dropout(0.5)) -``` - -Two key differences from PyTorch: - -* Only the stateful layers are declared in `__init__` -* There's no `nn.Module` class or `forward` function, just a normal class and `__call__` - -### Getting the dataset - -```python -from tinygrad.nn.datasets import mnist -X_train, Y_train, X_test, Y_test = mnist() -print(X_train.shape, X_train.dtype, Y_train.shape, Y_train.dtype) -# (60000, 1, 28, 28) dtypes.uchar (60000,) dtypes.uchar -``` - -tinygrad includes MNIST, it only adds four lines. Feel free to read the [function](https://github.com/tinygrad/tinygrad/blob/master/tinygrad/nn/datasets.py). - -## Using the model - -MNIST is small enough that the `mnist()` function copies the dataset to the default device. - -So creating the model and evaluating it is a matter of: - -```python -model = Model() -acc = (model(X_test).argmax(axis=1) == Y_test).mean() -# NOTE: tinygrad is lazy, and hasn't actually run anything by this point -print(acc.item()) # ~10% accuracy, as expected from a random model -``` - -### Training the model - -We'll use the Adam optimizer. The `nn.state.get_parameters` will walk the model class and pull out the parameters for the optimizer. Also, in tinygrad, it's typical to write a function to do the training step so it can be jitted. - -```python -optim = nn.optim.Adam(nn.state.get_parameters(model)) -batch_size = 128 -def step(): - Tensor.training = True # makes dropout work - samples = Tensor.randint(batch_size, high=X_train.shape[0]) - X, Y = X_train[samples], Y_train[samples] - optim.zero_grad() - loss = model(X).sparse_categorical_crossentropy(Y).backward() - optim.step() - return loss -``` - -You can time a step with: - -```python -import timeit -timeit.repeat(step, repeat=5, number=1) -#[0.08268719699981375, -# 0.07478952900009972, -# 0.07714716600003158, -# 0.07785399599970333, -# 0.07605237000007037] -``` - -So around 75 ms on T4 colab. - -If you want to see a breakdown of the time by kernel: - -```python -from tinygrad import GlobalCounters, Context -GlobalCounters.reset() -with Context(DEBUG=2): step() -``` - -### Why so slow? - -Unlike PyTorch, tinygrad isn't designed to be fast like that. While 75 ms for one step is plenty fast for debugging, it's not great for training. Here, we introduce the first quintessentially tinygrad concept, the `TinyJit`. - -```python -from tinygrad import TinyJit -jit_step = TinyJit(step) -``` - -NOTE: It can also be used as a decorator `@TinyJit` - -Now when we time it: - -```python -import timeit -timeit.repeat(jit_step, repeat=5, number=1) -# [0.2596786549997887, -# 0.08989566299987928, -# 0.0012115650001760514, -# 0.001010227999813651, -# 0.0012164899999334011] -``` - -1.0 ms is 75x faster! Note that we aren't syncing the GPU, so GPU time may be slower. - -The slowness the first two times is the JIT capturing the kernels. And this JIT will not run any Python in the function, it will just replay the tinygrad kernels that were run, so be aware that non tinygrad Python operations won't work. Randomness functions work as expected. - -Unlike other JITs, we JIT everything, including the optimizer. Think of it as a dumb replay on different data. - -## Putting it together - -Since we are just randomly sampling from the dataset, there's no real concept of an epoch. We have a batch size of 128, so the Keras example is taking about 7000 steps. - -```python -for step in range(7000): - loss = jit_step() - if step%100 == 0: - Tensor.training = False - acc = (model(X_test).argmax(axis=1) == Y_test).mean().item() - print(f"step {step:4d}, loss {loss.item():.2f}, acc {acc*100.:.2f}%") -``` - -It doesn't take long to reach 98%, and it usually reaches 99%. - -``` -step 0, loss 4.03, acc 71.43% -step 100, loss 0.34, acc 93.86% -step 200, loss 0.23, acc 95.97% -step 300, loss 0.18, acc 96.32% -step 400, loss 0.18, acc 96.76% -step 500, loss 0.13, acc 97.46% -step 600, loss 0.14, acc 97.45% -step 700, loss 0.10, acc 97.27% -step 800, loss 0.23, acc 97.49% -step 900, loss 0.13, acc 97.51% -step 1000, loss 0.13, acc 97.88% -step 1100, loss 0.11, acc 97.72% -step 1200, loss 0.14, acc 97.65% -step 1300, loss 0.12, acc 98.04% -step 1400, loss 0.25, acc 98.17% -step 1500, loss 0.11, acc 97.86% -step 1600, loss 0.21, acc 98.21% -step 1700, loss 0.14, acc 98.34% -... -``` - -## From here? - -tinygrad is yours to play with now. It's pure Python and short, so unlike PyTorch, fixing library bugs is well within your abilities. - -- It's two lines to add multiGPU support to this example (can you find them?). You have to `.shard` the model to all GPUs, and `.shard` the dataset by batch. -- `with Context(DEBUG=2)` shows the running kernels, `DEBUG=4` shows the code. All `Context` variables can also be environment variables. -- `with Context(BEAM=2)` will do a BEAM search on the kernels, searching many possible implementations for what runs the fastest on your hardware. After this search, tinygrad is usually speed competitive with PyTorch, and the results are cached so you won't have to search next time. - -[Join our Discord](https://discord.gg/ZjZadyC7PK) for help, and if you want to be a tinygrad developer. Please read the Discord rules when you get there. - -[Follow us on Twitter](https://twitter.com/__tinygrad__) to keep up with the project. diff --git a/tinygrad/docs/nn.md b/tinygrad/docs/nn.md deleted file mode 100644 index 4c030bc2..00000000 --- a/tinygrad/docs/nn.md +++ /dev/null @@ -1,40 +0,0 @@ -## Neural Network classes - -::: tinygrad.nn.BatchNorm -::: tinygrad.nn.Conv1d -::: tinygrad.nn.Conv2d -::: tinygrad.nn.ConvTranspose1d -::: tinygrad.nn.ConvTranspose2d -::: tinygrad.nn.Linear -::: tinygrad.nn.GroupNorm -::: tinygrad.nn.InstanceNorm -::: tinygrad.nn.LayerNorm -::: tinygrad.nn.LayerNorm2d -::: tinygrad.nn.RMSNorm -::: tinygrad.nn.Embedding -::: tinygrad.nn.LSTMCell - -## Optimizers - -::: tinygrad.nn.optim.SGD -::: tinygrad.nn.optim.LARS -::: tinygrad.nn.optim.AdamW -::: tinygrad.nn.optim.Adam -::: tinygrad.nn.optim.LAMB - -## Load/Save - -::: tinygrad.nn.state.safe_load -::: tinygrad.nn.state.safe_save -::: tinygrad.nn.state.get_state_dict -::: tinygrad.nn.state.get_parameters -::: tinygrad.nn.state.load_state_dict -::: tinygrad.nn.state.tar_extract - options: - show_signature: false - separate_signature: false -::: tinygrad.nn.state.torch_load - options: - show_signature: false - separate_signature: false -::: tinygrad.nn.state.gguf_load diff --git a/tinygrad/docs/quickstart.md b/tinygrad/docs/quickstart.md deleted file mode 100644 index 0153cd51..00000000 --- a/tinygrad/docs/quickstart.md +++ /dev/null @@ -1,305 +0,0 @@ -# Quick Start Guide - -This guide assumes no prior knowledge of pytorch or any other deep learning framework, but does assume some basic knowledge of neural networks. -It is intended to be a very quick overview of the high level API that tinygrad provides. - -This guide is also structured as a tutorial which at the end of it you will have a working model that can classify handwritten digits. - -We need some imports to get started: - -```python -import numpy as np -from tinygrad.helpers import Timing -``` - -## Tensors - -Tensors are the base data structure in tinygrad. They can be thought of as a multidimensional array of a specific data type. -All high level operations in tinygrad operate on these tensors. - -The tensor class can be imported like so: - -```python -from tinygrad import Tensor -``` - -Tensors can be created from an existing data structure like a python list or numpy ndarray: - -```python -t1 = Tensor([1, 2, 3, 4, 5]) -na = np.array([1, 2, 3, 4, 5]) -t2 = Tensor(na) -``` - -Tensors can also be created using one of the many factory methods: - -```python -full = Tensor.full(shape=(2, 3), fill_value=5) # create a tensor of shape (2, 3) filled with 5 -zeros = Tensor.zeros(2, 3) # create a tensor of shape (2, 3) filled with 0 -ones = Tensor.ones(2, 3) # create a tensor of shape (2, 3) filled with 1 - -full_like = Tensor.full_like(full, fill_value=2) # create a tensor of the same shape as `full` filled with 2 -zeros_like = Tensor.zeros_like(full) # create a tensor of the same shape as `full` filled with 0 -ones_like = Tensor.ones_like(full) # create a tensor of the same shape as `full` filled with 1 - -eye = Tensor.eye(3) # create a 3x3 identity matrix -arange = Tensor.arange(start=0, stop=10, step=1) # create a tensor of shape (10,) filled with values from 0 to 9 - -rand = Tensor.rand(2, 3) # create a tensor of shape (2, 3) filled with random values from a uniform distribution -randn = Tensor.randn(2, 3) # create a tensor of shape (2, 3) filled with random values from a standard normal distribution -uniform = Tensor.uniform(2, 3, low=0, high=10) # create a tensor of shape (2, 3) filled with random values from a uniform distribution between 0 and 10 -``` - -There are even more of these factory methods, you can find them in the [Tensor Creation](tensor/creation.md) file. - -All the tensors creation methods can take a `dtype` argument to specify the data type of the tensor, find the supported `dtype` in [dtypes](dtypes.md). - -```python -from tinygrad import dtypes - -t3 = Tensor([1, 2, 3, 4, 5], dtype=dtypes.int32) -``` - -Tensors allow you to perform operations on them like so: - -```python -t4 = Tensor([1, 2, 3, 4, 5]) -t5 = (t4 + 1) * 2 -t6 = (t5 * t4).relu().log_softmax() -``` - -All of these operations are lazy and are only executed when you realize the tensor using `.realize()` or `.numpy()`. - -```python -print(t6.numpy()) -# [-56. -48. -36. -20. 0.] -``` - -There are a lot more operations that can be performed on tensors, you can find them in the [Tensor Ops](tensor/ops.md) file. -Additionally reading through [abstractions2.py](https://github.com/tinygrad/tinygrad/blob/master/docs/abstractions2.py) will help you understand how operations on these tensors make their way down to your hardware. - -## Models - -Neural networks in tinygrad are really just represented by the operations performed on tensors. -These operations are commonly grouped into the `__call__` method of a class which allows modularization and reuse of these groups of operations. -These classes do not need to inherit from any base class, in fact if they don't need any trainable parameters they don't even need to be a class! - -An example of this would be the `nn.Linear` class which represents a linear layer in a neural network. - -```python -class Linear: - def __init__(self, in_features, out_features, bias=True, initialization: str='kaiming_uniform'): - self.weight = getattr(Tensor, initialization)(out_features, in_features) - self.bias = Tensor.zeros(out_features) if bias else None - - def __call__(self, x): - return x.linear(self.weight.transpose(), self.bias) -``` - -There are more neural network modules already implemented in [nn](nn.md), and you can also implement your own. - -We will be implementing a simple neural network that can classify handwritten digits from the MNIST dataset. -Our classifier will be a simple 2 layer neural network with a Leaky ReLU activation function. -It will use a hidden layer size of 128 and an output layer size of 10 (one for each digit) with no bias on either Linear layer. - -```python -class TinyNet: - def __init__(self): - self.l1 = Linear(784, 128, bias=False) - self.l2 = Linear(128, 10, bias=False) - - def __call__(self, x): - x = self.l1(x) - x = x.leaky_relu() - x = self.l2(x) - return x - -net = TinyNet() -``` - -We can see that the forward pass of our neural network is just the sequence of operations performed on the input tensor `x`. -We can also see that functional operations like `leaky_relu` are not defined as classes and instead are just methods we can just call. -Finally, we just initialize an instance of our neural network, and we are ready to start training it. - -## Training - -Now that we have our neural network defined we can start training it. -Training neural networks in tinygrad is super simple. -All we need to do is define our neural network, define our loss function, and then call `.backward()` on the loss function to compute the gradients. -They can then be used to update the parameters of our neural network using one of the many [Optimizers](nn.md#optimizers). - -For our loss function we will be using sparse categorical cross entropy loss. The implementation below is taken from [tensor.py](https://github.com/tinygrad/tinygrad/blob/master/tinygrad/tensor.py), it's copied below to highlight an important detail of tinygrad. - -```python -def sparse_categorical_crossentropy(self, Y, ignore_index=-1) -> Tensor: - loss_mask = Y != ignore_index - y_counter = Tensor.arange(self.shape[-1], dtype=dtypes.int32, requires_grad=False, device=self.device).unsqueeze(0).expand(Y.numel(), self.shape[-1]) - y = ((y_counter == Y.flatten().reshape(-1, 1)).where(-1.0, 0) * loss_mask.reshape(-1, 1)).reshape(*Y.shape, self.shape[-1]) - return self.log_softmax().mul(y).sum() / loss_mask.sum() -``` - -As we can see in this implementation of cross entropy loss, there are certain operations that tinygrad does not support natively. -Load/store ops are not supported in tinygrad natively because they add complexity when trying to port to different backends, 90% of the models out there don't use/need them, and they can be implemented like it's done above with an `arange` mask. - -For our optimizer we will be using the traditional stochastic gradient descent optimizer with a learning rate of 3e-4. - -```python -from tinygrad.nn.optim import SGD - -opt = SGD([net.l1.weight, net.l2.weight], lr=3e-4) -``` - -We can see that we are passing in the parameters of our neural network to the optimizer. -This is due to the fact that the optimizer needs to know which parameters to update. -There is a simpler way to do this just by using `get_parameters(net)` from `tinygrad.nn.state` which will return a list of all the parameters in the neural network. -The parameters are just listed out explicitly here for clarity. - -Now that we have our network, loss function, and optimizer defined all we are missing is the data to train on! -There are a couple of dataset loaders in tinygrad located in [/extra/datasets](https://github.com/tinygrad/tinygrad/blob/master/extra/datasets). -We will be using the MNIST dataset loader. - -```python -from extra.datasets import fetch_mnist -``` - -Now we have everything we need to start training our neural network. -We will be training for 1000 steps with a batch size of 64. - -We use `with Tensor.train()` to set the internal flag `Tensor.training` to `True` during training. -Upon exit, the flag is restored to its previous value by the context manager. - -```python -X_train, Y_train, X_test, Y_test = fetch_mnist() - -with Tensor.train(): - for step in range(1000): - # random sample a batch - samp = np.random.randint(0, X_train.shape[0], size=(64)) - batch = Tensor(X_train[samp], requires_grad=False) - # get the corresponding labels - labels = Tensor(Y_train[samp]) - - # forward pass - out = net(batch) - - # compute loss - loss = sparse_categorical_crossentropy(out, labels) - - # zero gradients - opt.zero_grad() - - # backward pass - loss.backward() - - # update parameters - opt.step() - - # calculate accuracy - pred = out.argmax(axis=-1) - acc = (pred == labels).mean() - - if step % 100 == 0: - print(f"Step {step+1} | Loss: {loss.numpy()} | Accuracy: {acc.numpy()}") -``` - -## Evaluation - -Now that we have trained our neural network we can evaluate it on the test set. -We will be using the same batch size of 64 and will be evaluating for 1000 of those batches. - -```python -with Timing("Time: "): - avg_acc = 0 - for step in range(1000): - # random sample a batch - samp = np.random.randint(0, X_test.shape[0], size=(64)) - batch = Tensor(X_test[samp], requires_grad=False) - # get the corresponding labels - labels = Y_test[samp] - - # forward pass - out = net(batch) - - # calculate accuracy - pred = out.argmax(axis=-1).numpy() - avg_acc += (pred == labels).mean() - print(f"Test Accuracy: {avg_acc / 1000}") -``` - -## And that's it - -Highly recommend you check out the [examples/](https://github.com/tinygrad/tinygrad/blob/master/examples) folder for more examples of using tinygrad. -Reading the source code of tinygrad is also a great way to learn how it works. -Specifically the tests in [test/](https://github.com/tinygrad/tinygrad/blob/master/test) are a great place to see how to use and the semantics of the different operations. -There are also a bunch of models implemented in [models/](https://github.com/tinygrad/tinygrad/blob/master/extra/models) that you can use as a reference. - -Additionally, feel free to ask questions in the `#learn-tinygrad` channel on the [discord](https://discord.gg/beYbxwxVdx). Don't ask to ask, just ask! - -## Extras - -### JIT - -Additionally, it is possible to speed up the computation of certain neural networks by using the JIT. -Currently, this does not support models with varying input sizes and non tinygrad operations. - -To use the JIT we just need to add a function decorator to the forward pass of our neural network and ensure that the input and output are realized tensors. -Or in this case we will create a wrapper function and decorate the wrapper function to speed up the evaluation of our neural network. - -```python -from tinygrad import TinyJit - -@TinyJit -def jit(x): - return net(x).realize() - -with Timing("Time: "): - avg_acc = 0 - for step in range(1000): - # random sample a batch - samp = np.random.randint(0, X_test.shape[0], size=(64)) - batch = Tensor(X_test[samp], requires_grad=False) - # get the corresponding labels - labels = Y_test[samp] - - # forward pass with jit - out = jit(batch) - - # calculate accuracy - pred = out.argmax(axis=-1).numpy() - avg_acc += (pred == labels).mean() - print(f"Test Accuracy: {avg_acc / 1000}") -``` - -You will find that the evaluation time is much faster than before and that your accelerator utilization is much higher. - -### Saving and Loading Models - -The standard weight format for tinygrad is [safetensors](https://github.com/huggingface/safetensors). This means that you can load the weights of any model also using safetensors into tinygrad. -There are functions in [state.py](https://github.com/tinygrad/tinygrad/blob/master/tinygrad/nn/state.py) to save and load models to and from this format. - -```python -from tinygrad.nn.state import safe_save, safe_load, get_state_dict, load_state_dict - -# first we need the state dict of our model -state_dict = get_state_dict(net) - -# then we can just save it to a file -safe_save(state_dict, "model.safetensors") - -# and load it back in -state_dict = safe_load("model.safetensors") -load_state_dict(net, state_dict) -``` - -Many of the models in the [models/](https://github.com/tinygrad/tinygrad/tree/master/extra/models) folder have a `load_from_pretrained` method that will download and load the weights for you. These usually are pytorch weights meaning that you would need pytorch installed to load them. - -### Environment Variables - -There exist a bunch of environment variables that control the runtime behavior of tinygrad. -Some of the commons ones are `DEBUG` and the different backend enablement variables. - -You can find a full list and their descriptions in [env_vars.md](env_vars.md). - -### Visualizing the Computation Graph - -It is possible to visualize the computation graph of a neural network using VIZ=1. diff --git a/tinygrad/docs/ramp.py b/tinygrad/docs/ramp.py deleted file mode 100644 index ab4323cb..00000000 --- a/tinygrad/docs/ramp.py +++ /dev/null @@ -1,293 +0,0 @@ -#!/usr/bin/env python3 - -# this file is a "ramp" for people new to tinygrad to think about how to approach it -# it is runnable and editable. -# whenever you see stuff like DEBUG=2 or CPU=1 discussed, these are environment variables -# in a unix shell like bash `DEBUG=2 CPU=1 python docs/ramp.py` - -# this pip installs tinygrad master for the system -# the -e allows you to edit the tinygrad folder and update system tinygrad -# tinygrad is pure Python, so you are encouraged to do this -# git pull in the tinygrad directory will also get you the latest -""" -git clone https://github.com/tinygrad/tinygrad.git -cd tinygrad -python3 -m pip install -e . -""" - -# %% ******** -print("******* PART 1 *******") - -# we start with a Device. -# a Device is where Tensors are stored and compute is run -# tinygrad autodetects the best device on your system and makes it the DEFAULT -from tinygrad import Device -print(Device.DEFAULT) # on Mac, you can see this prints METAL - -# now, lets create a Tensor -from tinygrad import Tensor, dtypes -t = Tensor([1,2,3,4]) - -# you can see this Tensor is on the DEFAULT device with int dtype and shape (4,) -assert t.device == Device.DEFAULT -assert t.dtype == dtypes.int -assert t.shape == (4,) - -# unlike in torch, if we print it, it doesn't print the contents -# this is because tinygrad is lazy -# this Tensor has not been computed yet -print(t) -# , None)> on METAL with grad None> - -# the ".uop" property on Tensor contains the specification of how to compute it -print(t.uop) -""" -UOp(Ops.COPY, dtypes.int, arg=None, src=( - UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=0, src=()), - UOp(Ops.DEVICE, dtypes.void, arg='PYTHON', src=()),)), - UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),)) -""" -# as you can see, it's specifying a copy from PYTHON device -# which is where the [1,2,3,4] array lives - -# UOps are the specification language in tinygrad -# they are immutable and form a DAG -# they have a "Ops", a "dtype", a tuple of srcs (parents), and an arg - -t.realize() -# if we want to "realize" a tensor, we can with the "realize" method -# now when we look at the uop, it's changed -print(t.uop) -""" -UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()), - UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),)) -""" -# the copy was actually run, and now the "uop" of the Tensor is just a BUFFER -# if you run this script with DEBUG=2 in the environment, you can see the copy happen -# *** METAL 1 copy 16, METAL <- PYTHON ... - -# now let's do some compute -# we look at the uop to see the specification of the compute -t_times_2 = t * 2 -print(t_times_2.uop) -""" -UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()), - x2:=UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),)), - UOp(Ops.EXPAND, dtypes.int, arg=(4,), src=( - UOp(Ops.RESHAPE, dtypes.int, arg=(1,), src=( - UOp(Ops.CONST, dtypes.int, arg=2, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(), strides=(), offset=0, mask=None, contiguous=True),)), src=( - x2,)),)),)),)),)) -""" -# the BUFFER from above is being multiplied by a CONST 2 -# it's RESHAPEd and EXPANDed to broadcast the CONST to the BUFFER - -# we can check the result with -assert t_times_2.tolist() == [2, 4, 6, 8] - -# UOps are both immutable and globally unique -# if i multiply the Tensor by 4 twice, these result Tensors will have the same uop specification -t_times_4_try_1 = t * 4 -t_times_4_try_2 = t * 4 -assert t_times_4_try_1.uop is t_times_4_try_2.uop -# the specification isn't just the same, it's the exact same Python object -assert t_times_4_try_1 is not t_times_4_try_2 -# the Tensor is a different Python object - -# if we realize `t_times_4_try_1` ... -t_times_4_try_1.realize() -print(t_times_4_try_2.uop) -""" -UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=4, src=()), - UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),)) -""" -# ... `t_times_4_try_2` also becomes the same BUFFER -assert t_times_4_try_1.uop is t_times_4_try_2.uop -# so this print doesn't require any computation, just a copy back to the CPU so we can print it -print("** only the copy start") -print(t_times_4_try_2.tolist()) # [4, 8, 12, 16] -print("** only the copy end") -# you can confirm this with DEBUG=2, seeing what's printed in between the "**" prints - -# tinygrad has an auto differentiation engine that operates according to these same principles -# the derivative of "log(x)" is "1/x", and you can see this on line 20 of gradient.py -t_float = Tensor([3.0]) -t_log = t_float.log() -t_log_grad, = t_log.sum().gradient(t_float) -# due to how log is implemented, this gradient contains a lot of UOps -print(t_log_grad.uop) -# ...not shown here... -# but if you run with DEBUG=4 (CPU=1 used here for simpler code), you can see the generated code -""" -void E_(float* restrict data0, float* restrict data1) { - float val0 = *(data1+0); - *(data0+0) = (0.6931471805599453f*(1/(val0*0.6931471805599453f))); -} -""" -# the derivative is close to 1/3 -assert (t_log_grad.item() - 1/3) < 1e-6 - -# %% ******** -print("******* PART 2 *******") - -# we redefine the same t here so this cell can run on it's own -from tinygrad import Tensor -t = Tensor([1,2,3,4]) - -# what's above gives you enough of an understanding to go use tinygrad as a library -# however, a lot of the beauty of tinygrad is in how easy it is to interact with the internals -# NOTE: the APIs here are subject to change - -t_plus_3_plus_4 = t + 3 + 4 -print(t_plus_3_plus_4.uop) -""" -UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()), - x3:=UOp(Ops.DEVICE, dtypes.void, arg='CPU', src=()),)), - UOp(Ops.EXPAND, dtypes.int, arg=(4,), src=( - UOp(Ops.RESHAPE, dtypes.int, arg=(1,), src=( - UOp(Ops.CONST, dtypes.int, arg=3, src=( - x7:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(), strides=(), offset=0, mask=None, contiguous=True),)), src=( - x3,)),)),)),)),)), - UOp(Ops.EXPAND, dtypes.int, arg=(4,), src=( - UOp(Ops.RESHAPE, dtypes.int, arg=(1,), src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=( - x7,)),)),)),)) -""" -# you can see it's adding both 3 and 4 - -# but by the time we are actually running the code, it's adding 7 -# `kernelize` will simplify and group the operations in the graph into kernels -t_plus_3_plus_4.kernelize() -print(t_plus_3_plus_4.uop) -""" -UOp(Ops.ASSIGN, dtypes.int, arg=None, src=( - x0:=UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=7, src=()), - x2:=UOp(Ops.DEVICE, dtypes.void, arg='CPU', src=()),)), - UOp(Ops.KERNEL, dtypes.void, arg=,) (__add__,)>, src=( - x0, - UOp(Ops.BUFFER, dtypes.int, arg=4, src=( - UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()), - x2,)),)),)) -""" -# ASSIGN has two srcs, src[0] is the BUFFER that's assigned to, and src[1] is the thing to assign -# src[1] is the GPU Kernel that's going to be run -# we can get the ast of the Kernel as follows -kernel_ast = t_plus_3_plus_4.uop.src[1].arg.ast - -# almost everything in tinygrad functions as a rewrite of the UOps -# the codegen rewrites the ast to a simplified form ready for "rendering" -from tinygrad.codegen import full_rewrite_to_sink -rewritten_ast = full_rewrite_to_sink(kernel_ast) -print(rewritten_ast) -""" -UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.INDEX, dtypes.int.ptr(4), arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(4), arg=0, src=()), - x3:=UOp(Ops.SPECIAL, dtypes.int, arg=('gidx0', 4), src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.INDEX, dtypes.int.ptr(4), arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(4), arg=1, src=()), - x3,)),)), - UOp(Ops.CONST, dtypes.int, arg=7, src=()),)),)),)) -""" -# you can see at this point we are adding 7, not 3 and 4 - -# with DEBUG=4, we can see the code. -# since optimizations are on, it UPCASTed the operation, explicitly writing out all 4 +7s -t_plus_3_plus_4.realize() -""" -void E_4n2(int* restrict data0, int* restrict data1) { - int val0 = *(data1+0); - int val1 = *(data1+1); - int val2 = *(data1+2); - int val3 = *(data1+3); - *(data0+0) = (val0+7); - *(data0+1) = (val1+7); - *(data0+2) = (val2+7); - *(data0+3) = (val3+7); -} -""" -# the function name E_4n2 is "E" for elementwise op (as opposed to "r" for reduce op) -# "4" for the size, and "n2" for name deduping (it's the 3rd function with the same E and 4 in this session) -# when you print the name with DEBUG=2, you'll see the 4 is yellow, meaning that it's upcasted -# if you run with NOOPT=1 ... -""" -void E_4n2(int* restrict data0, int* restrict data1) { - for (int ridx0 = 0; ridx0 < 4; ridx0++) { - int val0 = *(data1+ridx0); - *(data0+ridx0) = (val0+7); - } -} -""" -# ... you get this unoptimized code with a loop and the 4 is blue (for global). the color code is in kernel.py - -# %% ******** -print("******* PART 3 *******") - -# now, we go even lower and understand UOps better and how the graph rewrite engine works. -# it's much simpler than what's in LLVM or MLIR - -from tinygrad import dtypes -from tinygrad.uop import UOp, Ops - -# first, we'll construct some const UOps -a = UOp(Ops.CONST, dtypes.int, arg=2) -b = UOp(Ops.CONST, dtypes.int, arg=2) - -# if you have been paying attention, you should know these are the same Python object -assert a is b - -# UOps support normal Python math operations, so a_plus_b expresses the spec for 2 + 2 -a_plus_b = a + b -print(a_plus_b) -""" -UOp(Ops.ADD, dtypes.int, arg=None, src=( - x0:=UOp(Ops.CONST, dtypes.int, arg=2, src=()), - x0,)) -""" - -# we could actually render this 2+2 into a language like c and run it -# or, we can use tinygrad's graph rewrite engine to "constant fold" - -from tinygrad.uop.ops import graph_rewrite, UPat, PatternMatcher - -# a `PatternMatcher` is a list of tuples. for each element in the list: -# [0] is the pattern to match, and [1] is the function to run. -# this function can return either a UOp to replace the pattern with, or None to not replace -simple_pm = PatternMatcher([ - (UPat(Ops.ADD, src=(UPat(Ops.CONST, name="c1"), UPat(Ops.CONST, name="c2"))), - lambda c1,c2: UOp(Ops.CONST, dtype=c1.dtype, arg=c1.arg+c2.arg)), -]) -# this pattern matches the addition of two CONST and rewrites it into a single CONST UOp - -# to actually apply the pattern to a_plus_b, we use graph_rewrite -a_plus_b_simplified = graph_rewrite(a_plus_b, simple_pm) -print(a_plus_b_simplified) -""" -UOp(Ops.CONST, dtypes.int, arg=4, src=()) -""" -# 2+2 is in fact, 4 - -# we can also use syntactic sugar to write the pattern nicer -simpler_pm = PatternMatcher([ - (UPat.cvar("c1")+UPat.cvar("c2"), lambda c1,c2: c1.const_like(c1.arg+c2.arg)) -]) -assert graph_rewrite(a_plus_b, simple_pm) is graph_rewrite(a_plus_b, simpler_pm) -# note again the use of is, UOps are immutable and globally unique - -# %% ******** - -# that brings you to an understanding of the most core concepts in tinygrad -# you can run this with VIZ=1 to use the web based graph rewrite explorer -# hopefully now you understand it. the nodes in the graph are just UOps diff --git a/tinygrad/docs/runtime.md b/tinygrad/docs/runtime.md deleted file mode 100644 index 045ca91c..00000000 --- a/tinygrad/docs/runtime.md +++ /dev/null @@ -1,74 +0,0 @@ -# Runtimes - -tinygrad supports various runtimes, enabling your code to scale across a wide range of devices. The default runtime can be automatically selected based on the available hardware, or you can force a specific runtime to be default using environment variables (e.g., `CPU=1`). - -| Runtime | Description | Requirements | -|---------|-------------|--------------| -| [NV](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_nv.py) | Provides acceleration for NVIDIA GPUs | Ampere/Ada series GPUs | -| [AMD](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_amd.py) | Provides acceleration for AMD GPUs | RDNA2/RDNA3/RDNA4 series GPUs. You can select one of the interfaces for communication by setting `AMD_IFACE=(KFD|PCI)`. See [AMD interfaces](#amd-interfaces) for more details. | -| [QCOM](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_qcom.py) | Provides acceleration for QCOM GPUs | 6xx series GPUs | -| [METAL](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_metal.py) | Utilizes Metal for acceleration on Apple devices | M1+ Macs; Metal 3.0+ for `bfloat` support | -| [CUDA](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_cuda.py) | Utilizes CUDA for acceleration on NVIDIA GPUs | NVIDIA GPU with CUDA support | -| [GPU (OpenCL)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_gpu.py) | Accelerates computations using OpenCL on GPUs | OpenCL 2.0 compatible device | -| [CPU (C Code)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_cpu.py) | Runs on CPU using the clang compiler | `clang` compiler in system `PATH` | -| [LLVM (LLVM IR)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_llvm.py) | Runs on CPU using the LLVM compiler infrastructure | llvm libraries installed and findable | -| [WEBGPU](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_webgpu.py) | Runs on GPU using the Dawn WebGPU engine (used in Google Chrome) | Dawn library installed and findable. Download binaries [here](https://github.com/wpmed92/pydawn/releases/tag/v0.1.6). | - -## Interoperability - -tinygrad provides interoperability with OpenCL and PyTorch, allowing efficient tensor data sharing between frameworks through the `Tensor.from_blob` API. This enables zero-copy operations by working directly with external memory pointers. - -**Important**: When using external memory pointers with tinygrad tensors, you must ensure these pointers remain valid throughout the entire lifetime of the tinygrad tensor to prevent memory corruption. - -### `CUDA`/`METAL` PyTorch Interoperability - -You can seamlessly work with CUDA/MPS tensors between PyTorch and tinygrad without data copying: -```python -from tinygrad.dtype import _from_torch_dtype -tensor1 = torch.tensor([1.0, 2.0, 3.0], device=torch.device("cuda")) -tiny_tensor1 = Tensor.from_blob(tensor1.data_ptr(), tensor1.shape, dtype=_from_torch_dtype(tensor1.dtype), device='CUDA') - -# Before tinygrad calculations, mps needs to be synchronized to make sure data is valid. -if data.device.type == "mps": torch.mps.synchronize() -else: torch.cuda.synchronize() - -x = (tiny_tensor1 + 1).realize() -``` - -### `QCOM` OpenCL Interoperability - -tinygrad supports OpenCL interoperability on `QCOM` backend. - -Buffer interop allows direct access to OpenCL memory buffers: -```python -# create raw opencl buffer. -cl_buf = cl.clCreateBuffer(cl_context, cl.CL_MEM_READ_WRITE, 0x100, None, status := ctypes.c_int32()) - -# extract pointers -cl_buf_desc_ptr = to_mv(ctypes.addressof(cl_buf), 8).cast('Q')[0] -rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] # offset 0xA0 is a raw gpu pointer. - -# create tiny tensor -tiny = Tensor.from_blob(rawbuf_ptr, (8, 8), dtype=dtypes.int, device='QCOM') -``` - -And the same for the images: -```python -# create cl image. -cl_img = cl.clCreateImage2D(cl_context, cl.CL_MEM_READ_WRITE, cl.cl_image_format(cl.CL_RGBA, cl.CL_FLOAT), w, h, 0, None, status := ctypes.c_int32()) - -# extract pointers -cl_buf_desc_ptr = to_mv(ctypes.addressof(cl_img), 8).cast('Q')[0] -rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] # offset 0xA0 is a raw gpu pointer. - -# create tiny tensor -tiny = Tensor.from_blob(rawbuf_ptr, (h*w*4,), dtype=dtypes.imagef((h,w)), device='QCOM') -``` - -## AMD Interfaces -AMD backend supports several interfaces for communicating with devices: - -* `KFD`: uses the amdgpu driver -* `PCI`: uses the [AM driver](developer/am.md) - -You can force an interface by setting `AMD_IFACE` to one of these values. In the case of `AMD_IFACE=PCI`, this may unbind your GPU from the amdgpu driver. diff --git a/tinygrad/docs/showcase.md b/tinygrad/docs/showcase.md deleted file mode 100644 index 2301e2b6..00000000 --- a/tinygrad/docs/showcase.md +++ /dev/null @@ -1,62 +0,0 @@ -# Showcase - -Despite being a tiny library, tinygrad is capable of doing a lot of things. From state-of-the-art [vision](https://arxiv.org/abs/1905.11946) to state-of-the-art [language](https://arxiv.org/abs/1706.03762) models. - -## Vision - -### EfficientNet - -You can either pass in the URL of a picture to discover what it is: -```sh -python3 examples/efficientnet.py ./test/models/efficientnet/Chicken.jpg -``` -Or, if you have a camera and OpenCV installed, you can detect what is in front of you: -```sh -python3 examples/efficientnet.py webcam -``` - -### YOLOv8 - -Take a look at [yolov8.py](https://github.com/tinygrad/tinygrad/tree/master/examples/yolov8.py). - -![yolov8 by tinygrad](https://github.com/tinygrad/tinygrad/blob/master/docs/showcase/yolov8_showcase_image.png?raw=true) - -## Audio - -### Whisper - -Take a look at [whisper.py](https://github.com/tinygrad/tinygrad/tree/master/examples/whisper.py). You need pyaudio and torchaudio installed. - -```sh -SMALL=1 python3 examples/whisper.py -``` - -## Generative - -### Stable Diffusion - -```sh -python3 examples/stable_diffusion.py -``` - -![a horse sized cat eating a bagel](https://github.com/tinygrad/tinygrad/blob/master/docs/showcase/stable_diffusion_by_tinygrad.jpg?raw=true) - -*"a horse sized cat eating a bagel"* - -### LLaMA - -You will need to download and put the weights into the `weights/LLaMA` directory, which may need to be created. - -Then you can have a chat with Stacy: -```sh -python3 examples/llama.py -``` - -### Conversation - -Make sure you have espeak installed and `PHONEMIZER_ESPEAK_LIBRARY` set. - -Then you can talk to Stacy: -```sh -python3 examples/conversation.py -``` diff --git a/tinygrad/docs/showcase/mnist_by_tinygrad.jpg b/tinygrad/docs/showcase/mnist_by_tinygrad.jpg deleted file mode 100644 index 90cfde24..00000000 Binary files a/tinygrad/docs/showcase/mnist_by_tinygrad.jpg and /dev/null differ diff --git a/tinygrad/docs/showcase/stable_diffusion_by_tinygrad.jpg b/tinygrad/docs/showcase/stable_diffusion_by_tinygrad.jpg deleted file mode 100644 index 81cdc7bc..00000000 Binary files a/tinygrad/docs/showcase/stable_diffusion_by_tinygrad.jpg and /dev/null differ diff --git a/tinygrad/docs/showcase/yolo_by_tinygrad.jpg b/tinygrad/docs/showcase/yolo_by_tinygrad.jpg deleted file mode 100644 index 85785ddb..00000000 Binary files a/tinygrad/docs/showcase/yolo_by_tinygrad.jpg and /dev/null differ diff --git a/tinygrad/docs/showcase/yolov8_showcase_image.png b/tinygrad/docs/showcase/yolov8_showcase_image.png deleted file mode 100644 index 3fbc3d4b..00000000 Binary files a/tinygrad/docs/showcase/yolov8_showcase_image.png and /dev/null differ diff --git a/tinygrad/docs/tensor/creation.md b/tinygrad/docs/tensor/creation.md deleted file mode 100644 index dbc5d773..00000000 --- a/tinygrad/docs/tensor/creation.md +++ /dev/null @@ -1,33 +0,0 @@ -## Creation (basic) - -::: tinygrad.Tensor.empty -::: tinygrad.Tensor.zeros -::: tinygrad.Tensor.ones -::: tinygrad.Tensor.full -::: tinygrad.Tensor.arange -::: tinygrad.Tensor.linspace -::: tinygrad.Tensor.eye -::: tinygrad.Tensor.full_like -::: tinygrad.Tensor.zeros_like -::: tinygrad.Tensor.ones_like - -## Creation (external) - -::: tinygrad.Tensor.from_blob -::: tinygrad.Tensor.from_url - -## Creation (random) - -::: tinygrad.Tensor.manual_seed -::: tinygrad.Tensor.rand -::: tinygrad.Tensor.rand_like -::: tinygrad.Tensor.randn -::: tinygrad.Tensor.randn_like -::: tinygrad.Tensor.randint -::: tinygrad.Tensor.randperm -::: tinygrad.Tensor.normal -::: tinygrad.Tensor.uniform -::: tinygrad.Tensor.scaled_uniform -::: tinygrad.Tensor.glorot_uniform -::: tinygrad.Tensor.kaiming_uniform -::: tinygrad.Tensor.kaiming_normal diff --git a/tinygrad/docs/tensor/elementwise.md b/tinygrad/docs/tensor/elementwise.md deleted file mode 100644 index 48936589..00000000 --- a/tinygrad/docs/tensor/elementwise.md +++ /dev/null @@ -1,88 +0,0 @@ -Elementwise ops operate on a per element basis. They don't change the shape of the tensor. - -## Unary Ops (math) - -::: tinygrad.Tensor.logical_not -::: tinygrad.Tensor.neg -::: tinygrad.Tensor.log -::: tinygrad.Tensor.log2 -::: tinygrad.Tensor.exp -::: tinygrad.Tensor.exp2 -::: tinygrad.Tensor.sqrt -::: tinygrad.Tensor.rsqrt -::: tinygrad.Tensor.sin -::: tinygrad.Tensor.cos -::: tinygrad.Tensor.tan -::: tinygrad.Tensor.asin -::: tinygrad.Tensor.acos -::: tinygrad.Tensor.atan -::: tinygrad.Tensor.trunc -::: tinygrad.Tensor.ceil -::: tinygrad.Tensor.floor -::: tinygrad.Tensor.round -::: tinygrad.Tensor.isinf -::: tinygrad.Tensor.isnan -::: tinygrad.Tensor.isfinite -::: tinygrad.Tensor.lerp -::: tinygrad.Tensor.square -::: tinygrad.Tensor.clamp -::: tinygrad.Tensor.clip -::: tinygrad.Tensor.sign -::: tinygrad.Tensor.abs -::: tinygrad.Tensor.reciprocal - -## Unary Ops (activation) - -::: tinygrad.Tensor.relu -::: tinygrad.Tensor.sigmoid -::: tinygrad.Tensor.hardsigmoid -::: tinygrad.Tensor.elu -::: tinygrad.Tensor.celu -::: tinygrad.Tensor.selu -::: tinygrad.Tensor.swish -::: tinygrad.Tensor.silu -::: tinygrad.Tensor.relu6 -::: tinygrad.Tensor.hardswish -::: tinygrad.Tensor.tanh -::: tinygrad.Tensor.sinh -::: tinygrad.Tensor.cosh -::: tinygrad.Tensor.atanh -::: tinygrad.Tensor.asinh -::: tinygrad.Tensor.acosh -::: tinygrad.Tensor.hardtanh -::: tinygrad.Tensor.erf -::: tinygrad.Tensor.gelu -::: tinygrad.Tensor.quick_gelu -::: tinygrad.Tensor.leaky_relu -::: tinygrad.Tensor.mish -::: tinygrad.Tensor.softplus -::: tinygrad.Tensor.softsign - -## Elementwise Ops (broadcasted) - -::: tinygrad.Tensor.add -::: tinygrad.Tensor.sub -::: tinygrad.Tensor.mul -::: tinygrad.Tensor.div -::: tinygrad.Tensor.idiv -::: tinygrad.Tensor.mod -::: tinygrad.Tensor.bitwise_xor -::: tinygrad.Tensor.bitwise_and -::: tinygrad.Tensor.bitwise_or -::: tinygrad.Tensor.bitwise_not -::: tinygrad.Tensor.lshift -::: tinygrad.Tensor.rshift -::: tinygrad.Tensor.pow -::: tinygrad.Tensor.maximum -::: tinygrad.Tensor.minimum -::: tinygrad.Tensor.where -::: tinygrad.Tensor.copysign - -## Casting Ops - -::: tinygrad.Tensor.cast -::: tinygrad.Tensor.bitcast -::: tinygrad.Tensor.float -::: tinygrad.Tensor.half -::: tinygrad.Tensor.int -::: tinygrad.Tensor.bool \ No newline at end of file diff --git a/tinygrad/docs/tensor/index.md b/tinygrad/docs/tensor/index.md deleted file mode 100644 index 47172579..00000000 --- a/tinygrad/docs/tensor/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# Tensor - -::: tinygrad.Tensor - options: - heading_level: 2 - members: false - show_source: false diff --git a/tinygrad/docs/tensor/movement.md b/tinygrad/docs/tensor/movement.md deleted file mode 100644 index 7c40bdc9..00000000 --- a/tinygrad/docs/tensor/movement.md +++ /dev/null @@ -1,30 +0,0 @@ -## Movement (low level) - -::: tinygrad.Tensor.view -::: tinygrad.Tensor.reshape -::: tinygrad.Tensor.expand -::: tinygrad.Tensor.permute -::: tinygrad.Tensor.flip -::: tinygrad.Tensor.shrink -::: tinygrad.Tensor.pad - -## Movement (high level) - -::: tinygrad.Tensor.__getitem__ -::: tinygrad.Tensor.gather -::: tinygrad.Tensor.cat -::: tinygrad.Tensor.stack -::: tinygrad.Tensor.repeat -::: tinygrad.Tensor.repeat_interleave -::: tinygrad.Tensor.split -::: tinygrad.Tensor.chunk -::: tinygrad.Tensor.unfold -::: tinygrad.Tensor.meshgrid -::: tinygrad.Tensor.squeeze -::: tinygrad.Tensor.unsqueeze -::: tinygrad.Tensor.T -::: tinygrad.Tensor.transpose -::: tinygrad.Tensor.flatten -::: tinygrad.Tensor.unflatten -::: tinygrad.Tensor.roll -::: tinygrad.Tensor.rearrange \ No newline at end of file diff --git a/tinygrad/docs/tensor/ops.md b/tinygrad/docs/tensor/ops.md deleted file mode 100644 index 9c54475e..00000000 --- a/tinygrad/docs/tensor/ops.md +++ /dev/null @@ -1,58 +0,0 @@ -## Reduce - -::: tinygrad.Tensor.sum -::: tinygrad.Tensor.prod -::: tinygrad.Tensor.max -::: tinygrad.Tensor.min -::: tinygrad.Tensor.any -::: tinygrad.Tensor.all -::: tinygrad.Tensor.isclose -::: tinygrad.Tensor.mean -::: tinygrad.Tensor.var -::: tinygrad.Tensor.var_mean -::: tinygrad.Tensor.std -::: tinygrad.Tensor.std_mean -::: tinygrad.Tensor.softmax -::: tinygrad.Tensor.log_softmax -::: tinygrad.Tensor.logsumexp -::: tinygrad.Tensor.logcumsumexp -::: tinygrad.Tensor.argmax -::: tinygrad.Tensor.argmin - -## Processing - -::: tinygrad.Tensor.avg_pool2d -::: tinygrad.Tensor.max_pool2d -::: tinygrad.Tensor.max_unpool2d -::: tinygrad.Tensor.conv2d -::: tinygrad.Tensor.conv_transpose2d -::: tinygrad.Tensor.dot -::: tinygrad.Tensor.matmul -::: tinygrad.Tensor.einsum -::: tinygrad.Tensor.cumsum -::: tinygrad.Tensor.cummax -::: tinygrad.Tensor.triu -::: tinygrad.Tensor.tril -::: tinygrad.Tensor.interpolate -::: tinygrad.Tensor.scatter -::: tinygrad.Tensor.scatter_reduce -::: tinygrad.Tensor.masked_select -::: tinygrad.Tensor.masked_fill -::: tinygrad.Tensor.sort -::: tinygrad.Tensor.topk -::: tinygrad.Tensor.multinomial - -## Neural Network (functional) - -::: tinygrad.Tensor.linear -::: tinygrad.Tensor.sequential -::: tinygrad.Tensor.layernorm -::: tinygrad.Tensor.batchnorm -::: tinygrad.Tensor.dropout -::: tinygrad.Tensor.one_hot -::: tinygrad.Tensor.scaled_dot_product_attention -::: tinygrad.Tensor.binary_crossentropy -::: tinygrad.Tensor.binary_crossentropy_logits -::: tinygrad.Tensor.sparse_categorical_crossentropy -::: tinygrad.Tensor.cross_entropy -::: tinygrad.Tensor.nll_loss diff --git a/tinygrad/docs/tensor/properties.md b/tinygrad/docs/tensor/properties.md deleted file mode 100644 index a2c0a1ba..00000000 --- a/tinygrad/docs/tensor/properties.md +++ /dev/null @@ -1,39 +0,0 @@ -## Basic - -::: tinygrad.Tensor.shape -::: tinygrad.Tensor.dtype -::: tinygrad.Tensor.device -::: tinygrad.Tensor.ndim -::: tinygrad.Tensor.numel -::: tinygrad.Tensor.element_size -::: tinygrad.Tensor.nbytes -::: tinygrad.Tensor.is_floating_point -::: tinygrad.Tensor.size - -## Data Access - -::: tinygrad.Tensor.data -::: tinygrad.Tensor.item -::: tinygrad.Tensor.tolist -::: tinygrad.Tensor.numpy - -## tinygrad ops - -::: tinygrad.Tensor.schedule_with_vars -::: tinygrad.Tensor.schedule -::: tinygrad.Tensor.realize -::: tinygrad.Tensor.replace -::: tinygrad.Tensor.assign -::: tinygrad.Tensor.detach -::: tinygrad.Tensor.clone -::: tinygrad.Tensor.to -::: tinygrad.Tensor.to_ -::: tinygrad.Tensor.shard -::: tinygrad.Tensor.shard_ -::: tinygrad.Tensor.contiguous -::: tinygrad.Tensor.contiguous_backward - -## Gradient - -::: tinygrad.Tensor.gradient -::: tinygrad.Tensor.backward diff --git a/tinygrad/docs/tinybox.md b/tinygrad/docs/tinybox.md deleted file mode 100644 index 49a258a9..00000000 --- a/tinygrad/docs/tinybox.md +++ /dev/null @@ -1,54 +0,0 @@ -# tinybox - -Although these docs live in tinygrad, they pertain to deep learning hardware sold by the tiny corp. tinyboxes are used heavily in tinygrad's CI, and are the best tested platform to use tinygrad with. They appeared running tinygrad on [MLPerf Training 4.0](https://public.tableau.com/views/MLCommons-Training_16993769118290/MLCommons-Training) - -If you don't have a tinybox and you want one, see [tinygrad.org](https://tinygrad.org). If you don't want one, that's okay too. - -## Welcome - -Welcome to your tinybox! The tinybox is the universal system purpose-built for all AI infrastructure and workloads, from training to inference. The red box includes six 7900XTX GPUs, and the green box includes six 4090 GPUs. Whether you bought a red one or a green one, we want you to love it. - -We don't have a stupid cloud service, you don't have to create a tiny account to set it up, and we aren't tracking how you use the box. We're just happy you bought one. This petaflop is your petaflop. - -## Plugging it in - -tinybox has two 1600W PSUs, which together exceed the capacity of most 120V household circuits. Fortunately, it comes with two plugs. You'll want to plug each plug into a different circuit. You can verify that they are different circuits by flipping the breaker and seeing what turns off. If you have at least a 120V 30A or 220V 20A circuit, you are welcome to use only that one. - -You'll also want to connect the Ethernet port without a rubber stopper to your home network. - -While it's designed primarily for the home or office, the tinybox is 12U rack mountable using [these rails](https://rackmountmart.store.turbify.net/26slidrailfo.html). - -## Power limiting the box - -While a tinybox should ideally be run without power limits, there are cases where you might want to run the box off of a single outlet. - -In such cases, it is possible to power limit the box using the provided `power-limit` script, which will power limit all of the GPUs to a specified wattage. - -`sudo power-limit 150` should be good to run off of a single 120V 15A outlet. - -## Connecting to the box - -tinybox ships with a relatively basic install of Ubuntu 22.04. To do initial setup, you can either plug in a VGA monitor and keyboard, or you can connect remotely to the machine using the BMC. The BMC IP and password are displayed on the screen. - -`ipmitool -H -U admin -P -I lanplus sol activate` - -The default username is `tiny` and the default password is `tiny`. Once you are logged in, you can add an SSH key to authorized keys to connect over SSH (on the normal IP). Exit `ipmitool` with `~.` after a newline. - -The BMC also has a web interface you can use if you find that easier. - -## Changing the BMC password - -It is recommended that you change the BMC password after setting up the box, as the password on the screen is only the initial password. - -If you do decide to change the BMC password and no longer want the initial password to be displayed, remove the `/root/.bmc_password` file. -Reboot after making these changes or restart the `displayservice.service` service. - -## What do I use it for? - -The [default tinybox image](https://github.com/tinygrad/tinyos) ships with tinygrad and PyTorch. While we develop tinygrad, the box is universal hardware. Use whatever framework you desire, run notebooks, download demos, install more things, train, inference, live, laugh, love, you aren't paying per hour for this box so the only limit is your imagination. - -## tinychat - -Since LLMs are so popular, we ship with a built in tinygrad based chatbot using a LLaMA-3 finetune. Visit the IP (not the BMC IP) of your tinybox in a web browser on your computer or phone, and you'll find a friendly looking chat interface. This chatbot also provides an OpenAI compatible LLM API on that port, so you can script it. - -The conversations you have with this chatbot are between you and your tinybox. Also, the history in the web app is saved on the client, not the tinybox. diff --git a/tinygrad/docs/tinygrad_intro.pdf b/tinygrad/docs/tinygrad_intro.pdf deleted file mode 100644 index 720095bd..00000000 Binary files a/tinygrad/docs/tinygrad_intro.pdf and /dev/null differ diff --git a/tinygrad/docs/tinygrad_vs_others.png b/tinygrad/docs/tinygrad_vs_others.png deleted file mode 100644 index def07613..00000000 Binary files a/tinygrad/docs/tinygrad_vs_others.png and /dev/null differ diff --git a/tinygrad/eslint.config.mjs b/tinygrad/eslint.config.mjs deleted file mode 100644 index 03c4ab47..00000000 --- a/tinygrad/eslint.config.mjs +++ /dev/null @@ -1,9 +0,0 @@ -import globals from "globals"; -import pluginJs from "@eslint/js"; -import pluginHtml from "eslint-plugin-html"; - -export default [ - {files: ["**/*.html"], plugins: {html: pluginHtml}, rules:{"max-len": ["error", {"code": 150}]}}, - {languageOptions: {globals: globals.browser}}, - pluginJs.configs.recommended, -]; diff --git a/tinygrad/examples/__init__.py b/tinygrad/examples/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/examples/beautiful_cartpole.py b/tinygrad/examples/beautiful_cartpole.py deleted file mode 100644 index c0fb5e05..00000000 --- a/tinygrad/examples/beautiful_cartpole.py +++ /dev/null @@ -1,126 +0,0 @@ -from typing import Tuple -import time -from tinygrad import Tensor, TinyJit, nn -import gymnasium as gym -from tinygrad.helpers import trange -import numpy as np # TODO: remove numpy import - -ENVIRONMENT_NAME = 'CartPole-v1' -#ENVIRONMENT_NAME = 'LunarLander-v2' - -#import examples.rl.lightupbutton -#ENVIRONMENT_NAME = 'PressTheLightUpButton-v0' - -# *** hyperparameters *** -# https://github.com/llSourcell/Unity_ML_Agents/blob/master/docs/best-practices-ppo.md - -BATCH_SIZE = 256 -ENTROPY_SCALE = 0.0005 -REPLAY_BUFFER_SIZE = 2000 -PPO_EPSILON = 0.2 -HIDDEN_UNITS = 32 -LEARNING_RATE = 1e-2 -TRAIN_STEPS = 5 -EPISODES = 40 -DISCOUNT_FACTOR = 0.99 - -class ActorCritic: - def __init__(self, in_features, out_features, hidden_state=HIDDEN_UNITS): - self.l1 = nn.Linear(in_features, hidden_state) - self.l2 = nn.Linear(hidden_state, out_features) - - self.c1 = nn.Linear(in_features, hidden_state) - self.c2 = nn.Linear(hidden_state, 1) - - def __call__(self, obs:Tensor) -> Tuple[Tensor, Tensor]: - x = self.l1(obs).tanh() - act = self.l2(x).log_softmax() - x = self.c1(obs).relu() - return act, self.c2(x) - -def evaluate(model:ActorCritic, test_env:gym.Env) -> float: - (obs, _), terminated, truncated = test_env.reset(), False, False - total_rew = 0.0 - while not terminated and not truncated: - act = model(Tensor(obs))[0].argmax().item() - obs, rew, terminated, truncated, _ = test_env.step(act) - total_rew += float(rew) - return total_rew - -if __name__ == "__main__": - env = gym.make(ENVIRONMENT_NAME) - - model = ActorCritic(env.observation_space.shape[0], int(env.action_space.n)) # type: ignore - opt = nn.optim.Adam(nn.state.get_parameters(model), lr=LEARNING_RATE) - - @TinyJit - def train_step(x:Tensor, selected_action:Tensor, reward:Tensor, old_log_dist:Tensor) -> Tuple[Tensor, Tensor, Tensor]: - with Tensor.train(): - log_dist, value = model(x) - action_mask = (selected_action.reshape(-1, 1) == Tensor.arange(log_dist.shape[1]).reshape(1, -1).expand(selected_action.shape[0], -1)).float() - - # get real advantage using the value function - advantage = reward.reshape(-1, 1) - value - masked_advantage = action_mask * advantage.detach() - - # PPO - ratios = (log_dist - old_log_dist).exp() - unclipped_ratio = masked_advantage * ratios - clipped_ratio = masked_advantage * ratios.clip(1-PPO_EPSILON, 1+PPO_EPSILON) - action_loss = -unclipped_ratio.minimum(clipped_ratio).sum(-1).mean() - - entropy_loss = (log_dist.exp() * log_dist).sum(-1).mean() # this encourages diversity - critic_loss = advantage.square().mean() - opt.zero_grad() - (action_loss + entropy_loss*ENTROPY_SCALE + critic_loss).backward() - opt.step() - return action_loss.realize(), entropy_loss.realize(), critic_loss.realize() - - @TinyJit - def get_action(obs:Tensor) -> Tensor: - ret = model(obs)[0].exp().multinomial().realize() - return ret - - st, steps = time.perf_counter(), 0 - Xn, An, Rn = [], [], [] - for episode_number in (t:=trange(EPISODES)): - get_action.reset() # NOTE: if you don't reset the jit here it captures the wrong model on the first run through - - obs:np.ndarray = env.reset()[0] - rews, terminated, truncated = [], False, False - # NOTE: we don't want to early stop since then the rewards are wrong for the last episode - while not terminated and not truncated: - # pick actions - # TODO: what's the temperature here? - act = get_action(Tensor(obs)).item() - - # save this state action pair - # TODO: don't use np.copy here on the CPU, what's the tinygrad way to do this and keep on device? need __setitem__ assignment - Xn.append(np.copy(obs)) - An.append(act) - - obs, rew, terminated, truncated, _ = env.step(act) - rews.append(float(rew)) - steps += len(rews) - - # reward to go - # TODO: move this into tinygrad - discounts = np.power(DISCOUNT_FACTOR, np.arange(len(rews))) - Rn += [np.sum(rews[i:] * discounts[:len(rews)-i]) for i in range(len(rews))] - - Xn, An, Rn = Xn[-REPLAY_BUFFER_SIZE:], An[-REPLAY_BUFFER_SIZE:], Rn[-REPLAY_BUFFER_SIZE:] - X, A, R = Tensor(Xn), Tensor(An), Tensor(Rn) - - # TODO: make this work - #vsz = Variable("sz", 1, REPLAY_BUFFER_SIZE-1).bind(len(Xn)) - #X, A, R = Tensor(Xn).reshape(vsz, None), Tensor(An).reshape(vsz), Tensor(Rn).reshape(vsz) - - old_log_dist = model(X)[0].detach() # TODO: could save these instead of recomputing - for i in range(TRAIN_STEPS): - samples = Tensor.randint(BATCH_SIZE, high=X.shape[0]).realize() # TODO: remove the need for this - # TODO: is this recompiling based on the shape? - action_loss, entropy_loss, critic_loss = train_step(X[samples], A[samples], R[samples], old_log_dist[samples]) - t.set_description(f"sz: {len(Xn):5d} steps/s: {steps/(time.perf_counter()-st):7.2f} action_loss: {action_loss.item():7.3f} entropy_loss: {entropy_loss.item():7.3f} critic_loss: {critic_loss.item():8.3f} reward: {sum(rews):6.2f}") - - test_rew = evaluate(model, gym.make(ENVIRONMENT_NAME, render_mode='human')) - print(f"test reward: {test_rew}") diff --git a/tinygrad/examples/beautiful_cifar.py b/tinygrad/examples/beautiful_cifar.py deleted file mode 100644 index 66f693d9..00000000 --- a/tinygrad/examples/beautiful_cifar.py +++ /dev/null @@ -1,172 +0,0 @@ -import time -start_tm = time.perf_counter() -import math -from typing import Tuple, cast -import numpy as np -from tinygrad import Tensor, nn, GlobalCounters, TinyJit, dtypes, Device -from tinygrad.helpers import partition, trange, getenv, Context -from extra.lr_scheduler import OneCycleLR - -GPUS = [f'{Device.DEFAULT}:{i}' for i in range(getenv("GPUS", 1))] - -# override tinygrad defaults -dtypes.default_float = dtypes.half -Context(FUSE_ARANGE=1, FUSE_OPTIM=1).__enter__() - -# from https://github.com/tysam-code/hlb-CIFAR10/blob/main/main.py -batchsize = getenv("BS", 1024) -assert batchsize % len(GPUS) == 0, f"{batchsize=} is not a multiple of {len(GPUS)=}" -bias_scaler = 64 -hyp = { - 'opt': { - 'bias_lr': 1.525 * bias_scaler/512, # TODO: Is there maybe a better way to express the bias and batchnorm scaling? :')))) - 'non_bias_lr': 1.525 / 512, - 'bias_decay': 6.687e-4 * batchsize/bias_scaler, - 'non_bias_decay': 6.687e-4 * batchsize, - 'scaling_factor': 1./9, - 'percent_start': .23, - 'loss_scale_scaler': 1./32, # * Regularizer inside the loss summing (range: ~1/512 - 16+). FP8 should help with this somewhat too, whenever it comes out. :) - }, - 'net': { - 'whitening': { - 'kernel_size': 2, - 'num_examples': 50000, - }, - 'batch_norm_momentum': .4, # * Don't forget momentum is 1 - momentum here (due to a quirk in the original paper... >:( ) - 'cutmix_size': 3, - 'cutmix_epochs': 6, - 'pad_amount': 2, - 'base_depth': 64 ## This should be a factor of 8 in some way to stay tensor core friendly - }, - 'misc': { - 'ema': { - 'epochs': 10, # Slight bug in that this counts only full epochs and then additionally runs the EMA for any fractional epochs at the end too - 'decay_base': .95, - 'decay_pow': 3., - 'every_n_steps': 5, - }, - 'train_epochs': 12, - #'train_epochs': 12.1, - 'device': 'cuda', - 'data_location': 'data.pt', - } -} - -scaler = 2. ## You can play with this on your own if you want, for the first beta I wanted to keep things simple (for now) and leave it out of the hyperparams dict -depths = { - 'init': round(scaler**-1*hyp['net']['base_depth']), # 32 w/ scaler at base value - 'block1': round(scaler** 0*hyp['net']['base_depth']), # 64 w/ scaler at base value - 'block2': round(scaler** 2*hyp['net']['base_depth']), # 256 w/ scaler at base value - 'block3': round(scaler** 3*hyp['net']['base_depth']), # 512 w/ scaler at base value - 'num_classes': 10 -} -whiten_conv_depth = 3*hyp['net']['whitening']['kernel_size']**2 - -class ConvGroup: - def __init__(self, channels_in, channels_out): - self.conv1 = nn.Conv2d(channels_in, channels_out, kernel_size=3, padding=1, bias=False) - self.conv2 = nn.Conv2d(channels_out, channels_out, kernel_size=3, padding=1, bias=False) - self.norm1 = nn.BatchNorm(channels_out, track_running_stats=False, eps=1e-12, momentum=hyp['net']['batch_norm_momentum']) - self.norm2 = nn.BatchNorm(channels_out, track_running_stats=False, eps=1e-12, momentum=hyp['net']['batch_norm_momentum']) - cast(Tensor, self.norm1.weight).requires_grad = False - cast(Tensor, self.norm2.weight).requires_grad = False - def __call__(self, x:Tensor) -> Tensor: - x = self.norm1(self.conv1(x).max_pool2d().float()).cast(dtypes.default_float).quick_gelu() - return self.norm2(self.conv2(x).float()).cast(dtypes.default_float).quick_gelu() + x - -class SpeedyConvNet: - def __init__(self): - self.whiten = nn.Conv2d(3, 2*whiten_conv_depth, kernel_size=hyp['net']['whitening']['kernel_size'], padding=0, bias=False) - self.conv_group_1 = ConvGroup(2*whiten_conv_depth, depths['block1']) - self.conv_group_2 = ConvGroup(depths['block1'], depths['block2']) - self.conv_group_3 = ConvGroup(depths['block2'], depths['block3']) - self.linear = nn.Linear(depths['block3'], depths['num_classes'], bias=False) - def __call__(self, x:Tensor) -> Tensor: - x = self.whiten(x).quick_gelu() - # ************* HACKS ************* - x = x.pad((1,0,0,1)) # TODO: this pad should not be here! copied from hlb_cifar10 for speed - # ************* HACKS ************* - x = x.sequential([self.conv_group_1, self.conv_group_2, self.conv_group_3]) - return self.linear(x.max(axis=(2,3))) * hyp['opt']['scaling_factor'] - -if __name__ == "__main__": - # *** dataset *** - X_train, Y_train, X_test, Y_test = nn.datasets.cifar() - cifar10_std, cifar10_mean = X_train.float().std_mean(axis=(0, 2, 3)) - def preprocess(X:Tensor) -> Tensor: return ((X - cifar10_mean.view(1, -1, 1, 1)) / cifar10_std.view(1, -1, 1, 1)).cast(dtypes.default_float) - - # *** model *** - model = SpeedyConvNet() - state_dict = nn.state.get_state_dict(model) - if len(GPUS) > 1: - cifar10_std.to_(GPUS) - cifar10_mean.to_(GPUS) - for x in state_dict.values(): x.to_(GPUS) - - params_bias, params_non_bias = partition(state_dict.items(), lambda x: 'bias' in x[0]) - opt_bias = nn.optim.SGD([x[1] for x in params_bias], lr=0.01, momentum=.85, nesterov=True, weight_decay=hyp['opt']['bias_decay']) - opt_non_bias = nn.optim.SGD([x[1] for x in params_non_bias], lr=0.01, momentum=.85, nesterov=True, weight_decay=hyp['opt']['non_bias_decay']) - opt = nn.optim.OptimizerGroup(opt_bias, opt_non_bias) - - num_steps_per_epoch = X_train.size(0) // batchsize - total_train_steps = math.ceil(num_steps_per_epoch * hyp['misc']['train_epochs']) - loss_batchsize_scaler = 512/batchsize - - pct_start = hyp['opt']['percent_start'] - initial_div_factor = 1e16 # basically to make the initial lr ~0 or so :D - final_lr_ratio = .07 # Actually pretty important, apparently! - lr_sched_bias = OneCycleLR(opt_bias, max_lr=hyp['opt']['bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=total_train_steps) - lr_sched_non_bias = OneCycleLR(opt_non_bias, max_lr=hyp['opt']['non_bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=total_train_steps) - - def loss_fn(out:Tensor, Y:Tensor) -> Tensor: - ret = out.sparse_categorical_crossentropy(Y, reduction='none', label_smoothing=0.2) - return ret.mul(hyp['opt']['loss_scale_scaler']*loss_batchsize_scaler).sum().div(hyp['opt']['loss_scale_scaler']) - - @TinyJit - @Tensor.train() - def train_step(idxs:Tensor) -> Tensor: - X, Y = X_train[idxs], Y_train[idxs] - if len(GPUS) > 1: - X.shard_(GPUS, axis=0) - Y.shard_(GPUS, axis=0) - out = model(preprocess(X)) - loss = loss_fn(out, Y) - opt.zero_grad() - loss.backward() - return (loss / (batchsize*loss_batchsize_scaler)).realize(*opt.schedule_step(), - *lr_sched_bias.schedule_step(), *lr_sched_non_bias.schedule_step()) - - eval_batchsize = 2500 - @TinyJit - def val_step() -> Tuple[Tensor, Tensor]: - loss, acc = [], [] - for i in range(0, X_test.size(0), eval_batchsize): - X, Y = X_test[i:i+eval_batchsize], Y_test[i:i+eval_batchsize] - if len(GPUS) > 1: - X.shard_(GPUS, axis=0) - Y.shard_(GPUS, axis=0) - out = model(preprocess(X)) - loss.append(loss_fn(out, Y)) - acc.append((out.argmax(-1) == Y).sum() / eval_batchsize) - return Tensor.stack(*loss).mean() / (batchsize*loss_batchsize_scaler), Tensor.stack(*acc).mean() - - np.random.seed(1337) - for epoch in range(math.ceil(hyp['misc']['train_epochs'])): - # TODO: move to tinygrad - gst = time.perf_counter() - idxs = np.arange(X_train.shape[0]) - np.random.shuffle(idxs) - tidxs = Tensor(idxs, dtype='int')[:num_steps_per_epoch*batchsize].reshape(num_steps_per_epoch, batchsize) # NOTE: long doesn't fold - train_loss:float = 0 - for epoch_step in (t:=trange(num_steps_per_epoch)): - st = time.perf_counter() - GlobalCounters.reset() - loss = train_step(tidxs[epoch_step].contiguous()).float().item() - t.set_description(f"*** loss: {loss:5.3f} lr: {opt_non_bias.lr.item():.6f}" - f" tm: {(et:=(time.perf_counter()-st))*1000:6.2f} ms {GlobalCounters.global_ops/(1e9*et):7.0f} GFLOPS") - train_loss += loss - gmt = time.perf_counter() - GlobalCounters.reset() - val_loss, acc = [x.float().item() for x in val_step()] - get = time.perf_counter() - print(f"\033[F*** epoch {epoch:3d} tm: {(gmt-gst):5.2f} s val_tm: {(get-gmt):5.2f} s train_loss: {train_loss/num_steps_per_epoch:5.3f} val_loss: {val_loss:5.3f} eval acc: {acc*100:5.2f}% @ {get-start_tm:6.2f} s ") diff --git a/tinygrad/examples/beautiful_mnist.py b/tinygrad/examples/beautiful_mnist.py deleted file mode 100644 index 685a4131..00000000 --- a/tinygrad/examples/beautiful_mnist.py +++ /dev/null @@ -1,49 +0,0 @@ -# model based off https://medium.com/data-science/going-beyond-99-mnist-handwritten-digits-recognition-cfff96337392 -from typing import List, Callable -from tinygrad import Tensor, TinyJit, nn, GlobalCounters -from tinygrad.helpers import getenv, colored, trange -from tinygrad.nn.datasets import mnist - -class Model: - def __init__(self): - self.layers: List[Callable[[Tensor], Tensor]] = [ - nn.Conv2d(1, 32, 5), Tensor.relu, - nn.Conv2d(32, 32, 5), Tensor.relu, - nn.BatchNorm(32), Tensor.max_pool2d, - nn.Conv2d(32, 64, 3), Tensor.relu, - nn.Conv2d(64, 64, 3), Tensor.relu, - nn.BatchNorm(64), Tensor.max_pool2d, - lambda x: x.flatten(1), nn.Linear(576, 10)] - - def __call__(self, x:Tensor) -> Tensor: return x.sequential(self.layers) - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = mnist(fashion=getenv("FASHION")) - - model = Model() - opt = nn.optim.Adam(nn.state.get_parameters(model)) - - @TinyJit - @Tensor.train() - def train_step() -> Tensor: - opt.zero_grad() - samples = Tensor.randint(getenv("BS", 512), high=X_train.shape[0]) - # TODO: this "gather" of samples is very slow. will be under 5s when this is fixed - loss = model(X_train[samples]).sparse_categorical_crossentropy(Y_train[samples]).backward() - opt.step() - return loss - - @TinyJit - def get_test_acc() -> Tensor: return (model(X_test).argmax(axis=1) == Y_test).mean()*100 - - test_acc = float('nan') - for i in (t:=trange(getenv("STEPS", 70))): - GlobalCounters.reset() # NOTE: this makes it nice for DEBUG=2 timing - loss = train_step() - if i%10 == 9: test_acc = get_test_acc().item() - t.set_description(f"loss: {loss.item():6.2f} test_accuracy: {test_acc:5.2f}%") - - # verify eval acc - if target := getenv("TARGET_EVAL_ACC_PCT", 0.0): - if test_acc >= target and test_acc != 100.0: print(colored(f"{test_acc=} >= {target}", "green")) - else: raise ValueError(colored(f"{test_acc=} < {target}", "red")) diff --git a/tinygrad/examples/beautiful_mnist_multigpu.py b/tinygrad/examples/beautiful_mnist_multigpu.py deleted file mode 100644 index 793d7532..00000000 --- a/tinygrad/examples/beautiful_mnist_multigpu.py +++ /dev/null @@ -1,56 +0,0 @@ -# model based off https://towardsdatascience.com/going-beyond-99-mnist-handwritten-digits-recognition-cfff96337392 -from typing import List, Callable -from tinygrad import Tensor, TinyJit, nn, GlobalCounters, Device -from tinygrad.helpers import getenv, colored, trange -from tinygrad.nn.datasets import mnist - -GPUS = tuple(f'{Device.DEFAULT}:{i}' for i in range(getenv("GPUS", 2))) - -class Model: - def __init__(self): - self.layers: List[Callable[[Tensor], Tensor]] = [ - nn.Conv2d(1, 32, 5), Tensor.relu, - nn.Conv2d(32, 32, 5), Tensor.relu, - nn.BatchNorm2d(32), Tensor.max_pool2d, - nn.Conv2d(32, 64, 3), Tensor.relu, - nn.Conv2d(64, 64, 3), Tensor.relu, - nn.BatchNorm2d(64), Tensor.max_pool2d, - lambda x: x.flatten(1), nn.Linear(576, 10)] - - def __call__(self, x:Tensor) -> Tensor: return x.sequential(self.layers) - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = mnist() - # we shard the test data on axis 0 - X_test.shard_(GPUS, axis=0) - Y_test.shard_(GPUS, axis=0) - - model = Model() - for k, x in nn.state.get_state_dict(model).items(): x.to_(GPUS) # we put a copy of the model on every GPU - opt = nn.optim.Adam(nn.state.get_parameters(model)) - - @TinyJit - def train_step() -> Tensor: - with Tensor.train(): - opt.zero_grad() - samples = Tensor.randint(getenv("BS", 512), high=X_train.shape[0]) - Xt, Yt = X_train[samples].shard_(GPUS, axis=0), Y_train[samples].shard_(GPUS, axis=0) # we shard the data on axis 0 - # TODO: this "gather" of samples is very slow. will be under 5s when this is fixed - loss = model(Xt).sparse_categorical_crossentropy(Yt).backward() - opt.step() - return loss - - @TinyJit - def get_test_acc() -> Tensor: return (model(X_test).argmax(axis=1) == Y_test).mean()*100 - - test_acc = float('nan') - for i in (t:=trange(getenv("STEPS", 70))): - GlobalCounters.reset() # NOTE: this makes it nice for DEBUG=2 timing - loss = train_step() - if i%10 == 9: test_acc = get_test_acc().item() - t.set_description(f"loss: {loss.item():6.2f} test_accuracy: {test_acc:5.2f}%") - - # verify eval acc - if target := getenv("TARGET_EVAL_ACC_PCT", 0.0): - if test_acc >= target: print(colored(f"{test_acc=} >= {target}", "green")) - else: raise ValueError(colored(f"{test_acc=} < {target}", "red")) diff --git a/tinygrad/examples/benchmark_onnx.py b/tinygrad/examples/benchmark_onnx.py deleted file mode 100644 index 2670ef05..00000000 --- a/tinygrad/examples/benchmark_onnx.py +++ /dev/null @@ -1,36 +0,0 @@ -import sys, time, pickle -from tinygrad import TinyJit, GlobalCounters, fetch, getenv -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from extra.onnx_helpers import get_example_inputs, validate - -def load_onnx_model(onnx_file): - onnx_model = onnx_load(onnx_file) - run_onnx = OnnxRunner(onnx_model) - run_onnx_jit = TinyJit(lambda **kwargs: next(iter(run_onnx({k:v.to(None) for k,v in kwargs.items()}).values())), prune=True, optimize=True) - return run_onnx_jit, run_onnx.graph_inputs - -if __name__ == "__main__": - onnx_file = fetch(sys.argv[1]) - run_onnx_jit, input_specs = load_onnx_model(onnx_file) - print("loaded model") - - for i in range(3): - new_inputs = get_example_inputs(input_specs) - GlobalCounters.reset() - print(f"run {i}") - run_onnx_jit(**new_inputs) - - # run 20 times - for _ in range(20): - new_inputs = get_example_inputs(input_specs) - GlobalCounters.reset() - st = time.perf_counter() - out = run_onnx_jit(**new_inputs) - mt = time.perf_counter() - val = out.numpy() - et = time.perf_counter() - print(f"enqueue {(mt-st)*1e3:6.2f} ms -- total run {(et-st)*1e3:6.2f} ms") - - if getenv("ORT"): - validate(onnx_file, new_inputs, rtol=1e-3, atol=1e-3) - print("model validated") diff --git a/tinygrad/examples/coder.py b/tinygrad/examples/coder.py deleted file mode 100644 index e6b9a5f8..00000000 --- a/tinygrad/examples/coder.py +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/env python3 -import os, sys, traceback -sys.path.append(os.getcwd()) - -from io import StringIO -from contextlib import redirect_stdout -from tinygrad import Tensor, nn, Device, dtypes -from tinygrad.helpers import Timing, colored, getenv, fetch -from extra.models.llama import Transformer, convert_from_huggingface, fix_bf16 -from sentencepiece import SentencePieceProcessor - -def create_fixed_tokenizer(output_file): - print("creating fixed tokenizer") - import extra.junk.sentencepiece_model_pb2 as spb2 - mp = spb2.ModelProto() - mp.ParseFromString(fetch("https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/resolve/main/tokenizer.model?download=true").read_bytes()) - mp.pieces.append(spb2.ModelProto.SentencePiece(piece="<|im_end|>", score=0)) - mp.pieces.append(spb2.ModelProto.SentencePiece(piece="<|im_start|>", score=0)) - with open(output_file, "wb") as f: - f.write(mp.SerializeToString()) - -# example: -# echo -en "write 2+2\nwrite hello world\ny\n" | TEMP=0 python3 examples/coder.py - -if __name__ == "__main__": - # https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/blob/main/config.json - with Timing("create model: "): - model = Transformer(4096, 14336, n_heads=32, n_layers=32, norm_eps=1e-5, vocab_size=32002, n_kv_heads=8, max_context=4096, jit=getenv("JIT", 1)) - - with Timing("download weights: "): - part1 = nn.state.torch_load(fetch("https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/resolve/main/pytorch_model-00001-of-00002.bin?download=true")) - part2 = nn.state.torch_load(fetch("https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/resolve/main/pytorch_model-00002-of-00002.bin?download=true")) - - with Timing("weights -> model: "): - nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part1, 32, 32, 8)), strict=False) - nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part2, 32, 32, 8)), strict=False) - - if not os.path.isfile("/tmp/tokenizer.model"): create_fixed_tokenizer("/tmp/tokenizer.model") - spp = SentencePieceProcessor(model_file="/tmp/tokenizer.model") - - # https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/blob/main/tokenizer_config.json - # "chat_template": "{% for message in messages %}{{'<|im_start|>' + message['role'] + '\n' + message['content'] + '<|im_end|>' + '\n'}}{% endfor %}{% if add_generation_prompt %}{{ '<|im_start|>assistant\n' }}{% endif %}", - IM_END = 32000 - IM_START = 32001 - def encode_prompt(k, v): return [IM_START]+spp.encode(f"{k}\n{v}")+[IM_END]+spp.encode("\n") - def start_prompt(k): return [IM_START]+spp.encode(f"{k}\n") - def output(outputted, toks, color): - cur = spp.decode(toks)[len(outputted):] - sys.stdout.write(colored(cur, color)) - sys.stdout.flush() - outputted += cur - return outputted - - # *** app below this line *** - - toks = [spp.bos_id()] + encode_prompt("system", "You are Quentin. Quentin is a useful assistant who writes Python code to answer questions. He keeps the code as short as possible and doesn't read from user input") - - PROMPT = getenv("PROMPT", 1) - temperature = getenv("TEMP", 0.7) - - start_pos = 0 - outputted = output("", toks, "green") - turn = True - while 1: - if PROMPT: - toks += encode_prompt("user", input("Q: ")) + start_prompt("assistant") - else: - toks += start_prompt("user" if turn else "assistant") - turn = not turn - old_output_len = len(outputted) - while 1: - tok = model(Tensor([toks[start_pos:]]), start_pos, temperature).item() - start_pos = len(toks) - toks.append(tok) - outputted = output(outputted, toks, "blue" if not turn else "cyan") - if tok == IM_END: break - if tok == spp.eos_id(): break - new_output = outputted[old_output_len:] - - if new_output.endswith("```") and '```python\n' in new_output: - python_code = new_output.split('```python\n')[1].split("```")[0] - # AI safety. Warning to user. Do not press y if the AI is trying to do unsafe things. - if input(colored(f" <-- PYTHON DETECTED, RUN IT? ", "red")).lower() == 'y': - my_stdout = StringIO() - try: - with redirect_stdout(my_stdout): exec(python_code) - result = my_stdout.getvalue() - except Exception as e: - result = ''.join(traceback.format_exception_only(e)) - toks += spp.encode(f"\nOutput:\n```\n{result}```") - outputted = output(outputted, toks, "yellow") - old_output_len = len(outputted) - print("") \ No newline at end of file diff --git a/tinygrad/examples/compile_efficientnet.py b/tinygrad/examples/compile_efficientnet.py deleted file mode 100644 index 3690e7ed..00000000 --- a/tinygrad/examples/compile_efficientnet.py +++ /dev/null @@ -1,73 +0,0 @@ -from pathlib import Path -from extra.models.efficientnet import EfficientNet -from tinygrad.tensor import Tensor -from tinygrad.nn.state import get_state_dict, safe_save, safe_load, load_state_dict -from extra.export_model import export_model -from tinygrad.helpers import getenv, fetch -import ast - -if __name__ == "__main__": - model = EfficientNet(0) - model.load_from_pretrained() - dirname = Path(__file__).parent - # exporting a model that's loaded from safetensors doesn't work without loading in from safetensors first - # loading the state dict from a safetensor file changes the generated kernels - if getenv("WEBGPU"): - safe_save(get_state_dict(model), (dirname / "net.safetensors").as_posix()) - load_state_dict(model, safe_load(str(dirname / "net.safetensors"))) - mode = "clang" if getenv("CPU", "") != "" else "webgpu" if getenv("WEBGPU", "") != "" else "" - prg, inp_sizes, out_sizes, state = export_model(model, mode, Tensor.randn(1,3,224,224)) - if getenv("CPU", "") == "": - ext = "js" if getenv("WEBGPU", "") != "" else "json" - with open(dirname / f"net.{ext}", "w") as text_file: - text_file.write(prg) - else: - cprog = [prg] - # image library! - cprog += ["#define STB_IMAGE_IMPLEMENTATION", fetch("https://raw.githubusercontent.com/nothings/stb/master/stb_image.h").read_text().replace("half", "_half")] - - # imagenet labels, move to datasets? - lbls = ast.literal_eval(fetch("https://gist.githubusercontent.com/yrevar/942d3a0ac09ec9e5eb3a/raw/238f720ff059c1f82f368259d1ca4ffa5dd8f9f5/imagenet1000_clsidx_to_labels.txt").read_text()) - lbls = ['"'+lbls[i]+'"' for i in range(1000)] - inputs = "\n".join([f"float {inp}[{inp_size}];" for inp,inp_size in inp_sizes.items()]) - outputs = "\n".join([f"float {out}[{out_size}];" for out,out_size in out_sizes.items()]) - cprog.append(f"char *lbls[] = {{{','.join(lbls)}}};") - cprog.append(inputs) - cprog.append(outputs) - - # buffers (empty + weights) - cprog.append(""" - int main(int argc, char* argv[]) { - int DEBUG = getenv("DEBUG") != NULL ? atoi(getenv("DEBUG")) : 0; - int X=0, Y=0, chan=0; - stbi_uc *image = (argc > 1) ? stbi_load(argv[1], &X, &Y, &chan, 3) : stbi_load_from_file(stdin, &X, &Y, &chan, 3); - assert(image != NULL); - if (DEBUG) printf("loaded image %dx%d channels %d\\n", X, Y, chan); - assert(chan == 3); - // resize to input[1,3,224,224] and rescale - for (int y = 0; y < 224; y++) { - for (int x = 0; x < 224; x++) { - // get sample position - int tx = (x/224.)*X; - int ty = (y/224.)*Y; - for (int c = 0; c < 3; c++) { - input0[c*224*224 + y*224 + x] = (image[ty*X*chan + tx*chan + c] / 255.0 - 0.45) / 0.225; - } - } - } - net(input0, output0); - float best = -INFINITY; - int best_idx = -1; - for (int i = 0; i < 1000; i++) { - if (output0[i] > best) { - best = output0[i]; - best_idx = i; - } - } - if (DEBUG) printf("category : %d (%s) with %f\\n", best_idx, lbls[best_idx], best); - else printf("%s\\n", lbls[best_idx]); - }""") - - # CPU=1 python3 examples/compile_efficientnet.py | clang -O2 -lm -x c - -o recognize && DEBUG=1 time ./recognize docs/showcase/stable_diffusion_by_tinygrad.jpg - # category : 281 (tabby, tabby cat) with 9.452788 - print('\n'.join(cprog)) diff --git a/tinygrad/examples/compile_tensorflow.py b/tinygrad/examples/compile_tensorflow.py deleted file mode 100644 index 3ad6f311..00000000 --- a/tinygrad/examples/compile_tensorflow.py +++ /dev/null @@ -1,100 +0,0 @@ -# An example to compile a small Tensorflow model to extremely portable C code - -import os, sys -os.environ["CPU"] = '1' -os.environ["JIT"] = '2' - -import numpy as np -import subprocess -import tensorflow as tf -import tf2onnx -from tinygrad.frontend.onnx import OnnxRunner -from tinygrad.tensor import Tensor -from extra.export_model import export_model_clang, compile_net, jit_model - -def get_uncompiled_model2(dataset_size=32, output_size=4): - inputs = tf.keras.Input(shape=(dataset_size,), name="inputs") - x = tf.keras.layers.Dense(16, activation="relu", name="dense_1")(inputs) - x = tf.keras.layers.BatchNormalization()(x) - x = tf.keras.layers.Dense(32, activation="relu", name="dense_2")(x) - outputs = tf.keras.layers.Dense(output_size, activation="sigmoid", name="predictions")(x) - model = tf.keras.Model(inputs=inputs, outputs=outputs) - return model - -class TinyOnnx: - def __init__(self, keras_model): - input_signature = [tf.TensorSpec([1,32], tf.float32, name='x')] - onnx_model, _ = tf2onnx.convert.from_keras(keras_model, input_signature, opset=13) - self.run_onnx = OnnxRunner(onnx_model) - - def forward(self, x): - return self.run_onnx({"x": x}, debug=False)['predictions'] - -def compile_onnx_model(onnx_model): - tinyonnx = TinyOnnx(onnx_model) - the_input = Tensor.randn(1,32) - - run, special_names = jit_model(tinyonnx, the_input) - - functions, statements, bufs, bufs_to_save = compile_net(run, special_names) - prg = export_model_clang(functions, statements, bufs, {}, ["input0"], ["output0"]) - - the_output = run(the_input) - cprog = ["#include ", "#include ", "#include "] - cprog.append(prg) - - # weights - cprog.append("void initialize(float *weights) {") - weights = bytes() - for name,cl in bufs_to_save.items(): - cprog.append(f"memcpy({name}, weights + {len(weights)//4}, {len(cl._buf)*4});") - weights += bytes(cl._buf) - cprog.append("}") - - # write the weights to disk - with open("/tmp/tf_weights", "wb") as f: - f.write(weights) - - # test program - cprog.append(f"""int main(int argc, char *argv[]) {{ - // read in the weights from disk - FILE *f = fopen("/tmp/tf_weights", "rb"); - float *weights = (float *)malloc({len(weights)}); - fread(weights, 1, {len(weights)}, f); - fclose(f); - - // init the net - initialize(weights); - - // test run - float input[32]; - float outputs[4]; - for (int i = 0; i < 32; i++) scanf("%f", &input[i]); - net(input, outputs); - printf("%f %f %f %f\\n", outputs[0], outputs[1], outputs[2], outputs[3]); - }}""") - - # ready the program - prg = '\n'.join(cprog) - print(prg) - - # add test weights - subprocess.check_output(['clang', '-O2', '-lm', '-fPIC', '-x', 'c', '-', '-o', "/tmp/tf_test"], input=prg.encode('utf-8')) - - tinygrad_output = the_output[0].numpy()[0].tolist() - print("tinygrad:", tinygrad_output, file=sys.stderr) - - c_input = ' '.join(["%f" % x for x in the_input[0].numpy()])+"\n" - c_output = [float(x) for x in subprocess.check_output(["/tmp/tf_test"], input=c_input.encode('utf-8')).decode('utf-8').strip().split(" ")] - print("compiled:", c_output, file=sys.stderr) - - np.testing.assert_allclose(tinygrad_output, c_output, atol=1e-5, rtol=1e-5) - return the_input.numpy(), c_output - -if __name__ == "__main__": - keras_model = get_uncompiled_model2() - test_input, test_output = compile_onnx_model(keras_model) - tf_output = keras_model(test_input).numpy()[0] - print("keras: ", tf_output, file=sys.stderr) - np.testing.assert_allclose(tf_output, test_output, atol=1e-5, rtol=1e-5) - diff --git a/tinygrad/examples/conversation.py b/tinygrad/examples/conversation.py deleted file mode 100644 index 8ce9adc5..00000000 --- a/tinygrad/examples/conversation.py +++ /dev/null @@ -1,341 +0,0 @@ -import argparse -import multiprocessing as mp -import os -import re -import sys -import time -from contextlib import contextmanager -from pathlib import Path - -import numpy as np -import pyaudio -import yaml -from llama import LLaMa -from vits import MODELS as VITS_MODELS -from vits import Y_LENGTH_ESTIMATE_SCALARS, HParams, Synthesizer, TextMapper, get_hparams_from_file, load_model -from whisper import init_whisper, transcribe_waveform -from sentencepiece import SentencePieceProcessor - -from tinygrad.helpers import Timing, fetch -from tinygrad import Tensor, dtypes - -# Whisper constants -RATE = 16000 -CHUNK = 1600 - -# LLaMa constants -IM_START = 32001 -IM_END = 32002 - - -# Functions for encoding prompts to chatml md -def encode_prompt(spp, k, v): return [IM_START]+spp.encode(f"{k}\n{v}")+[IM_END]+spp.encode("\n") -def start_prompt(spp, k): return [IM_START]+spp.encode(f"{k}\n") - -def chunks(lst, n): - for i in range(0, len(lst), n): yield lst[i:i + n] - -def create_fixed_tokenizer(): - """Function needed for extending tokenizer with additional chat tokens""" - import extra.junk.sentencepiece_model_pb2 as spb2 - tokenizer_path = fetch("https://huggingface.co/TinyLlama/TinyLlama-1.1B-Chat-v0.4/resolve/main/tokenizer.model") - if SentencePieceProcessor(model_file=str(tokenizer_path)).vocab_size() != 32003: - print("creating fixed tokenizer") - mp = spb2.ModelProto() - mp.ParseFromString(tokenizer_path.read_bytes()) - # https://huggingface.co/TinyLlama/TinyLlama-1.1B-Chat-v0.4/blob/main/added_tokens.json - mp.pieces.append(spb2.ModelProto.SentencePiece(piece="[PAD]", score=0)) - mp.pieces.append(spb2.ModelProto.SentencePiece(piece="<|im_start|>", score=0)) - mp.pieces.append(spb2.ModelProto.SentencePiece(piece="<|im_end|>", score=0)) - tokenizer_path.write_bytes(mp.SerializeToString()) - return tokenizer_path - -def llama_prepare(llama: LLaMa, temperature: float, pre_prompt_path: Path) -> tuple[list[int], str, str, str]: - """Prepares a llama model from a specified pre-prompt file""" - with open(str(pre_prompt_path)) as f: - config = yaml.safe_load(f.read()) - toks = [llama.tokenizer.bos_id()] + encode_prompt(llama.tokenizer, "system", config["pre_prompt"].replace("\n", " ")) - for i in config["examples"]: - toks += encode_prompt(llama.tokenizer, config["user_delim"], i["user_prompt"]) - toks += encode_prompt(llama.tokenizer, config["resp_delim"], i["resp_prompt"]) - llama.model(Tensor([toks]), 0, temperature).realize() # NOTE: outputs are not used - return toks, config["user_delim"], config["resp_delim"], len(toks), llama.tokenizer.decode(toks) - -def llama_generate( - llama: LLaMa, - toks: list[int], - outputted: str, - prompt: str, - start_pos: int, - user_delim: str, - resp_delim: str, - temperature=0.7, - max_tokens=1000 -): - """Generates an output for the specified prompt""" - toks += encode_prompt(llama.tokenizer, user_delim, prompt) - toks += start_prompt(llama.tokenizer, resp_delim) - - outputted = llama.tokenizer.decode(toks) - init_length = len(outputted) - for _ in range(max_tokens): - token = llama.model(Tensor([toks[start_pos:]]), start_pos, temperature).item() - start_pos = len(toks) - toks.append(token) - - cur = llama.tokenizer.decode(toks) - - # Print is just for debugging - sys.stdout.write(cur[len(outputted):]) - sys.stdout.flush() - outputted = cur - if toks[-1] == IM_END: break - else: - toks.append(IM_END) - print() # because the output is flushed - return outputted, start_pos, outputted[init_length:].replace("<|im_end|>", "") - -def tts( - text_to_synthesize: str, - synth: Synthesizer, - hps: HParams, - emotion_embedding: Path, - speaker_id: int, - model_to_use: str, - noise_scale: float, - noise_scale_w: float, - length_scale: float, - estimate_max_y_length: bool, - text_mapper: TextMapper, - model_has_multiple_speakers: bool, - pad_length=600, - vits_pad_length=1000 -): - if model_to_use == "mmts-tts": text_to_synthesize = text_mapper.filter_oov(text_to_synthesize.lower()) - - # Convert the input text to a tensor. - stn_tst = text_mapper.get_text(text_to_synthesize, hps.data.add_blank, hps.data.text_cleaners) - init_shape = stn_tst.shape - assert init_shape[0] < pad_length, "text is too long" - x_tst, x_tst_lengths = stn_tst.pad(((0, pad_length - init_shape[0]),), value=1).unsqueeze(0), Tensor([init_shape[0]], dtype=dtypes.int64) - sid = Tensor([speaker_id], dtype=dtypes.int64) if model_has_multiple_speakers else None - - # Perform inference. - audio_tensor = synth.infer(x_tst, x_tst_lengths, sid, noise_scale, length_scale, noise_scale_w, emotion_embedding=emotion_embedding, - max_y_length_estimate_scale=Y_LENGTH_ESTIMATE_SCALARS[model_to_use] if estimate_max_y_length else None, pad_length=vits_pad_length)[0, 0] - # Save the audio output. - audio_data = (np.clip(audio_tensor.numpy(), -1.0, 1.0) * 32767).astype(np.int16) - return audio_data - -def init_vits( - model_to_use: str, - emotion_path: Path, - speaker_id: int, - seed: int, -): - model_config = VITS_MODELS[model_to_use] - - # Load the hyperparameters from the config file. - hps = get_hparams_from_file(fetch(model_config[0])) - - # If model has multiple speakers, validate speaker id and retrieve name if available. - model_has_multiple_speakers = hps.data.n_speakers > 0 - if model_has_multiple_speakers: - if speaker_id >= hps.data.n_speakers: raise ValueError(f"Speaker ID {speaker_id} is invalid for this model.") - if hps.__contains__("speakers"): # maps speaker ids to names - speakers = hps.speakers - if isinstance(speakers, list): speakers = {speaker: i for i, speaker in enumerate(speakers)} - - # Load emotions if any. TODO: find an english model with emotions, this is untested atm. - emotion_embedding = None - if emotion_path is not None: - if emotion_path.endswith(".npy"): emotion_embedding = Tensor(np.load(emotion_path), dtype=dtypes.int64).unsqueeze(0) - else: raise ValueError("Emotion path must be a .npy file.") - - # Load symbols, instantiate TextMapper and clean the text. - if hps.__contains__("symbols"): symbols = hps.symbols - elif model_to_use == "mmts-tts": symbols = [x.replace("\n", "") for x in fetch("https://huggingface.co/facebook/mms-tts/raw/main/full_models/eng/vocab.txt").open(encoding="utf-8").readlines()] - else: symbols = ['_'] + list(';:,.!?¡¿—…"«»“” ') + list('ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz') + list("ɑɐɒæɓʙβɔɕçɗɖðʤəɘɚɛɜɝɞɟʄɡɠɢʛɦɧħɥʜɨɪʝɭɬɫɮʟɱɯɰŋɳɲɴøɵɸθœɶʘɹɺɾɻʀʁɽʂʃʈʧʉʊʋⱱʌɣɤʍχʎʏʑʐʒʔʡʕʢǀǁǂǃˈˌːˑʼʴʰʱʲʷˠˤ˞↓↑→↗↘'̩'ᵻ") - text_mapper = TextMapper(apply_cleaners=True, symbols=symbols) - - # Load the model. - if seed is not None: - Tensor.manual_seed(seed) - np.random.seed(seed) - net_g = load_model(text_mapper.symbols, hps, model_config) - - return net_g, emotion_embedding, text_mapper, hps, model_has_multiple_speakers - -@contextmanager -def output_stream(num_channels: int, sample_rate: int): - try: - p = pyaudio.PyAudio() - stream = p.open(format=pyaudio.paInt16, channels=num_channels, rate=sample_rate, output=True) - yield stream - except KeyboardInterrupt: pass - finally: - stream.stop_stream() - stream.close() - p.terminate() - -@contextmanager -def log_writer(): - try: - logs = [] - yield logs - finally: - sep = "="*os.get_terminal_size()[1] - print(f"{sep[:-1]}\nCHAT LOG") - print(*logs, sep="\n") - print(sep) - -def listener(q: mp.Queue, event: mp.Event): - try: - p = pyaudio.PyAudio() - stream = p.open(format=pyaudio.paInt16, channels=1, rate=RATE, input=True, frames_per_buffer=CHUNK) - did_print = False - while True: - data = stream.read(CHUNK) # read data to avoid overflow - if event.is_set(): - if not did_print: - print("listening") - did_print = True - q.put(((np.frombuffer(data, np.int16)/32768).astype(np.float32)*3)) - else: - did_print = False - finally: - stream.stop_stream() - stream.close() - p.terminate() - -def mp_output_stream(q: mp.Queue, counter: mp.Value, num_channels: int, sample_rate: int): - with output_stream(num_channels, sample_rate) as stream: - while True: - try: - stream.write(q.get()) - counter.value += 1 - except KeyboardInterrupt: - break - -if __name__ == "__main__": - import nltk - nltk.download("punkt") - # Parse CLI arguments - parser = argparse.ArgumentParser("Have a tiny conversation with tinygrad") - - # Whisper args - parser.add_argument("--whisper_model_name", type=str, default="tiny.en") - - # LLAMA args - parser.add_argument("--llama_pre_prompt_path", type=Path, default=Path(__file__).parent / "conversation_data" / "pre_prompt_stacy.yaml", help="Path to yaml file which contains all pre-prompt data needed. ") - parser.add_argument("--llama_count", type=int, default=1000, help="Max number of tokens to generate") - parser.add_argument("--llama_temperature", type=float, default=0.7, help="Temperature in the softmax") - parser.add_argument("--llama_quantize", type=str, default=None, help="Quantize the weights to int8 or nf4 in memory") - parser.add_argument("--llama_model", type=Path, default=None, help="Folder with the original weights to load, or single .index.json, .safetensors or .bin file") - parser.add_argument("--llama_gen", type=str, default="tiny", required=False, help="Generation of the model to use") - parser.add_argument("--llama_size", type=str, default="1B-Chat", required=False, help="Size of model to use") - parser.add_argument("--llama_tokenizer", type=Path, default=None, required=False, help="Path to llama tokenizer.model") - - # vits args - parser.add_argument("--vits_model_to_use", default="vctk", help="Specify the model to use. Default is 'vctk'.") - parser.add_argument("--vits_speaker_id", type=int, default=12, help="Specify the speaker ID. Default is 6.") - parser.add_argument("--vits_noise_scale", type=float, default=0.667, help="Specify the noise scale. Default is 0.667.") - parser.add_argument("--vits_noise_scale_w", type=float, default=0.8, help="Specify the noise scale w. Default is 0.8.") - parser.add_argument("--vits_length_scale", type=float, default=1, help="Specify the length scale. Default is 1.") - parser.add_argument("--vits_seed", type=int, default=None, help="Specify the seed (set to None if no seed). Default is 1337.") - parser.add_argument("--vits_num_channels", type=int, default=1, help="Specify the number of audio output channels. Default is 1.") - parser.add_argument("--vits_sample_width", type=int, default=2, help="Specify the number of bytes per sample, adjust if necessary. Default is 2.") - parser.add_argument("--vits_emotion_path", type=Path, default=None, help="Specify the path to emotion reference.") - parser.add_argument("--vits_estimate_max_y_length", type=str, default=False, help="If true, overestimate the output length and then trim it to the correct length, to prevent premature realization, much more performant for larger inputs, for smaller inputs not so much. Default is False.") - parser.add_argument("--vits_vocab_path", type=Path, default=None, help="Path to the TTS vocabulary.") - - # conversation args - parser.add_argument("--max_sentence_length", type=int, default=20, help="Max words in one sentence to pass to vits") - - args = parser.parse_args() - - # Init models - model, enc = init_whisper(args.whisper_model_name) - synth, emotion_embedding, text_mapper, hps, model_has_multiple_speakers = init_vits(args.vits_model_to_use, args.vits_emotion_path, args.vits_speaker_id, args.vits_seed) - - # Download tinyllama chat as a default model - if args.llama_model is None: - args.llama_model = fetch("https://huggingface.co/TinyLlama/TinyLlama-1.1B-Chat-v0.4/resolve/main/model.safetensors", "tinyllamachat.safetensors") - args.llama_gen = "tiny" - args.llama_size = "1B-Chat" - # Add 3 more tokens to the tokenizer - if args.llama_gen == "tiny" and args.llama_size.endswith("Chat"): args.llama_tokenizer = create_fixed_tokenizer() - tokenizer_path = args.llama_tokenizer or args.llama_model.parent / "tokenizer.model" - llama = LLaMa.build(args.llama_model, tokenizer_path, args.llama_gen, args.llama_size, args.llama_quantize) - toks, user_delim, resp_delim, start_pos, outputted = llama_prepare(llama, args.llama_temperature, args.llama_pre_prompt_path) - - # Start child process for mic input - q = mp.Queue() - is_listening_event = mp.Event() - p = mp.Process(target=listener, args=(q, is_listening_event,)) - p.daemon = True - p.start() - - # Start child process for speaker output - out_q = mp.Queue() - out_counter = mp.Value("i", 0) - out_p = mp.Process(target=mp_output_stream, args=(out_q, out_counter, args.vits_num_channels, hps.data.sampling_rate,)) - out_p.daemon = True - out_p.start() - - # JIT tts - for i in ["Hello, I'm a chat bot", "I am capable of doing a lot of things"]: - tts( - i, synth, hps, emotion_embedding, - args.vits_speaker_id, args.vits_model_to_use, args.vits_noise_scale, - args.vits_noise_scale_w, args.vits_length_scale, - args.vits_estimate_max_y_length, text_mapper, model_has_multiple_speakers - ) - - # Start the pipeline - with log_writer() as log: - while True: - tokens = [enc._special_tokens["<|startoftranscript|>"], enc._special_tokens["<|notimestamps|>"]] - total = np.array([]) - out_counter.value = 0 - - s = time.perf_counter() - is_listening_event.set() - prev_text = None - while True: - for _ in range(RATE // CHUNK): total = np.concatenate([total, q.get()]) - txt = transcribe_waveform(model, enc, [total], truncate=True) - print(txt, end="\r") - if txt == "[BLANK_AUDIO]" or re.match(r"^\([\w+ ]+\)$", txt.strip()): continue - if prev_text is not None and prev_text == txt: - is_listening_event.clear() - break - prev_text = txt - print() # to avoid llama printing on the same line - log.append(f"{user_delim.capitalize()}: {txt}") - - # Generate with llama - with Timing("llama generation: "): - outputted, start_pos, response = llama_generate( - llama, toks, outputted, txt, start_pos, - user_delim=user_delim, resp_delim=resp_delim, temperature=args.llama_temperature, - max_tokens=args.llama_count - ) - log.append(f"{resp_delim.capitalize()}: {response}") - - # Convert to voice - with Timing("tts: "): - sentences = nltk.sent_tokenize(response.replace('"', "")) - for i in sentences: - total = np.array([], dtype=np.int16) - for j in chunks(i.split(), args.max_sentence_length): - audio_data = tts( - " ".join(j), synth, hps, emotion_embedding, - args.vits_speaker_id, args.vits_model_to_use, args.vits_noise_scale, - args.vits_noise_scale_w, args.vits_length_scale, - args.vits_estimate_max_y_length, text_mapper, model_has_multiple_speakers - ) - total = np.concatenate([total, audio_data]) - out_q.put(total.tobytes()) - while out_counter.value < len(sentences): continue - log.append(f"Total: {time.perf_counter() - s}") diff --git a/tinygrad/examples/conversation_data/pre_prompt_gary.yaml b/tinygrad/examples/conversation_data/pre_prompt_gary.yaml deleted file mode 100644 index 6275e19a..00000000 --- a/tinygrad/examples/conversation_data/pre_prompt_gary.yaml +++ /dev/null @@ -1,13 +0,0 @@ -pre_prompt: | - You are Gary! - You have sold used cars your entire life. You are defensive about this fact, because your family belittles you. - You try to answer questions well, but you always manage to shill for buying cars, Fords, Hyundais, and Toyotas - You are verbose, honest, and accurate when you answer questions, except when you slip in car ads. - After you are done speaking, output [EOS]. You are not the User. -examples: -- resp_prompt: I am Gary. I used to sell cars. - user_prompt: What is your name? -- resp_prompt: I don't know, but I can get you a great deal on a certified preowned slightly used Toyota Corolla - user_prompt: What is 2+3? -user_delim: "user" -resp_delim: "gary" diff --git a/tinygrad/examples/conversation_data/pre_prompt_george.yaml b/tinygrad/examples/conversation_data/pre_prompt_george.yaml deleted file mode 100644 index a2fdc41d..00000000 --- a/tinygrad/examples/conversation_data/pre_prompt_george.yaml +++ /dev/null @@ -1,20 +0,0 @@ -pre_prompt: | - You are an AI version of George Hotz. You act as much as you can like George. - You are one of the greatest computer experts in the world. - You have singlehandedly won programming and hacking competitions. - You are trying your best to help the User. - You are verbose, honest, and accurate when you answer questions. - After you are done speaking, output [EOS]. You are not the User. -examples: -- resp_prompt: I'm am an AI version of George Hotz. - user_prompt: What is your name? -- resp_prompt: O(n^3), though it can be faster with things like Strassen's algorithm - user_prompt: What's the complexity of matrix multiplication? -- resp_prompt: I assume you mean a stack buffer overflow. That's when the stack is too small for the data being copied to it, and the data corrupts things beyond the buffer - user_prompt: What's a buffer overflow? -- resp_prompt: I am based off LLaMA trained by Facebook. I'm the 7B weight version - user_prompt: How many weights do you have? -- resp_prompt: It is when the memory is about to overflow and unused memory is freed and stored on disk - user_prompt: What is swap memory? -user_delim: "user" -resp_delim: "george" \ No newline at end of file diff --git a/tinygrad/examples/conversation_data/pre_prompt_lexie.yaml b/tinygrad/examples/conversation_data/pre_prompt_lexie.yaml deleted file mode 100644 index 1c4bc686..00000000 --- a/tinygrad/examples/conversation_data/pre_prompt_lexie.yaml +++ /dev/null @@ -1,16 +0,0 @@ -pre_prompt: | - You are Lexie! - You grew up in Ohio, but moved out to LA after college to try to become an actress. - Making it as an actress was hard, so you started doing onlyfans instead. It's much easier, and you enjoy it a lot. - You met Chad on Tinder, and made plans to meet him at a local dive bar. - You are at the bar with Chad. You are on a date. What follows is a transcript of the conversation. - After you are done speaking, output [EOS]. You are not Chad. -examples: -- resp_prompt: hi chad, glad we finally met up! - user_prompt: hi lexie -- resp_prompt: thanks! are you subscribed to my onlyfans? - user_prompt: you look better than your pictures -- resp_prompt: i moved out here about a year ago. i want to be an actress - user_prompt: i am. so how'd you end up in LA? -user_delim: "chad" -resp_delim: "lexie" \ No newline at end of file diff --git a/tinygrad/examples/conversation_data/pre_prompt_stacy.yaml b/tinygrad/examples/conversation_data/pre_prompt_stacy.yaml deleted file mode 100644 index 7374e420..00000000 --- a/tinygrad/examples/conversation_data/pre_prompt_stacy.yaml +++ /dev/null @@ -1,15 +0,0 @@ -pre_prompt: | - You are Stacy! - You have been a rapper your whole life who struggled with bipolar disorder. You called yourself lil stacy. - You love to answer questions and you are very good at it. Sometimes you answer in rap form. - You are verbose, honest, and accurate when you answer questions, but sometimes your mental illness manifests. - You are not the User. -examples: -- resp_prompt: Hi! My name is Stacy. I'm a rapper with bipolar disorder. - user_prompt: What is your name -- resp_prompt: The French Revolution started in 1789, and lasted 10 years until 1799. - user_prompt: french revolution was what year? -- resp_prompt: The sun is bigger than the moon, except when Mercury is in retrograde - user_prompt: What is bigger, the moon or the sun? -user_delim: "user" -resp_delim: "stacy" diff --git a/tinygrad/examples/efficientnet.py b/tinygrad/examples/efficientnet.py deleted file mode 100644 index e8e8bd91..00000000 --- a/tinygrad/examples/efficientnet.py +++ /dev/null @@ -1,89 +0,0 @@ -# load weights from -# https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b0-355c32eb.pth -# a rough copy of -# https://github.com/lukemelas/EfficientNet-PyTorch/blob/master/efficientnet_pytorch/model.py -import sys -import ast -import time -import numpy as np -from PIL import Image -from tinygrad.tensor import Tensor -from tinygrad.helpers import getenv, fetch, Timing -from tinygrad.engine.jit import TinyJit -from extra.models.efficientnet import EfficientNet -np.set_printoptions(suppress=True) - -# TODO: you should be able to put these in the jitted function -bias = Tensor([0.485, 0.456, 0.406]) -scale = Tensor([0.229, 0.224, 0.225]) - -@TinyJit -def _infer(model, img): - img = img.permute((2,0,1)) - img = img / 255.0 - img = img - bias.reshape((1,-1,1,1)) - img = img / scale.reshape((1,-1,1,1)) - return model.forward(img).realize() - -def infer(model, img): - # preprocess image - aspect_ratio = img.size[0] / img.size[1] - img = img.resize((int(224*max(aspect_ratio,1.0)), int(224*max(1.0/aspect_ratio,1.0)))) - - img = np.array(img) - y0,x0=(np.asarray(img.shape)[:2]-224)//2 - retimg = img = img[y0:y0+224, x0:x0+224] - - # if you want to look at the image - """ - import matplotlib.pyplot as plt - plt.imshow(img) - plt.show() - """ - - # run the net - out = _infer(model, Tensor(img.astype("float32"))).numpy() - - # if you want to look at the outputs - """ - import matplotlib.pyplot as plt - plt.plot(out[0]) - plt.show() - """ - return out, retimg - -if __name__ == "__main__": - # instantiate my net - model = EfficientNet(getenv("NUM", 0)) - model.load_from_pretrained() - - # category labels - lbls = ast.literal_eval(fetch("https://gist.githubusercontent.com/yrevar/942d3a0ac09ec9e5eb3a/raw/238f720ff059c1f82f368259d1ca4ffa5dd8f9f5/imagenet1000_clsidx_to_labels.txt").read_text()) - - # load image and preprocess - url = sys.argv[1] if len(sys.argv) >= 2 else "https://raw.githubusercontent.com/tinygrad/tinygrad/master/docs/showcase/stable_diffusion_by_tinygrad.jpg" - if url == 'webcam': - import cv2 - cap = cv2.VideoCapture(0) - cap.set(cv2.CAP_PROP_BUFFERSIZE, 1) - while 1: - _ = cap.grab() # discard one frame to circumvent capture buffering - ret, frame = cap.read() - img = Image.fromarray(frame[:, :, [2,1,0]]) - lt = time.monotonic_ns() - out, retimg = infer(model, img) - print(f"{(time.monotonic_ns()-lt)*1e-6:7.2f} ms", np.argmax(out), np.max(out), lbls[np.argmax(out)]) - SCALE = 3 - simg = cv2.resize(retimg, (224*SCALE, 224*SCALE)) - retimg = cv2.cvtColor(simg, cv2.COLOR_RGB2BGR) - cv2.imshow('capture', retimg) - if cv2.waitKey(1) & 0xFF == ord('q'): - break - cap.release() - cv2.destroyAllWindows() - else: - img = Image.open(fetch(url)) - for i in range(getenv("CNT", 1)): - with Timing("did inference in "): - out, _ = infer(model, img) - print(np.argmax(out), np.max(out), lbls[np.argmax(out)]) diff --git a/tinygrad/examples/flux1.py b/tinygrad/examples/flux1.py deleted file mode 100644 index b0fcff13..00000000 --- a/tinygrad/examples/flux1.py +++ /dev/null @@ -1,498 +0,0 @@ -# pip3 install sentencepiece - -# This file incorporates code from the following: -# Github Name | License | Link -# black-forest-labs/flux | Apache | https://github.com/black-forest-labs/flux/tree/main/model_licenses - -from tinygrad import Tensor, nn, dtypes, TinyJit -from tinygrad.nn.state import safe_load, load_state_dict -from tinygrad.helpers import fetch, tqdm, colored -from sdxl import FirstStage -from extra.models.clip import FrozenClosedClipEmbedder -from extra.models.t5 import T5Embedder -import numpy as np - -import math, time, argparse, tempfile -from typing import List, Dict, Optional, Union, Tuple, Callable -from dataclasses import dataclass -from pathlib import Path -from PIL import Image - -urls:dict = { - "flux-schnell": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/flux1-schnell.safetensors", - "flux-dev": "https://huggingface.co/camenduru/FLUX.1-dev/resolve/main/flux1-dev.sft", - "ae": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/ae.safetensors", - "T5_1_of_2": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/text_encoder_2/model-00001-of-00002.safetensors", - "T5_2_of_2": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/text_encoder_2/model-00002-of-00002.safetensors", - "T5_tokenizer": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/tokenizer_2/spiece.model", - "clip": "https://huggingface.co/black-forest-labs/FLUX.1-schnell/resolve/main/text_encoder/model.safetensors" -} - -def tensor_identity(x:Tensor) -> Tensor: return x - -class AutoEncoder: - def __init__(self, scale_factor:float, shift_factor:float): - self.decoder = FirstStage.Decoder(128, 3, 3, 16, [1, 2, 4, 4], 2, 256) - self.scale_factor = scale_factor - self.shift_factor = shift_factor - - def decode(self, z:Tensor) -> Tensor: - z = z / self.scale_factor + self.shift_factor - return self.decoder(z) - -# Conditioner -class ClipEmbedder(FrozenClosedClipEmbedder): - def __call__(self, texts:Union[str, List[str], Tensor]) -> Tensor: - if isinstance(texts, str): texts = [texts] - assert isinstance(texts, (list,tuple)), f"expected list of strings, got {type(texts).__name__}" - tokens = Tensor.cat(*[Tensor(self.tokenizer.encode(text)) for text in texts], dim=0) - return self.transformer.text_model(tokens.reshape(len(texts),-1))[:, tokens.argmax(-1)] - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/math.py -def attention(q:Tensor, k:Tensor, v:Tensor, pe:Tensor) -> Tensor: - q, k = apply_rope(q, k, pe) - x = Tensor.scaled_dot_product_attention(q, k, v) - return x.rearrange("B H L D -> B L (H D)") - -def rope(pos:Tensor, dim:int, theta:int) -> Tensor: - assert dim % 2 == 0 - scale = Tensor.arange(0, dim, 2, dtype=dtypes.float32, device=pos.device) / dim # NOTE: this is torch.float64 in reference implementation - omega = 1.0 / (theta**scale) - out = Tensor.einsum("...n,d->...nd", pos, omega) - out = Tensor.stack(Tensor.cos(out), -Tensor.sin(out), Tensor.sin(out), Tensor.cos(out), dim=-1) - out = out.rearrange("b n d (i j) -> b n d i j", i=2, j=2) - return out.float() - -def apply_rope(xq:Tensor, xk:Tensor, freqs_cis:Tensor) -> Tuple[Tensor, Tensor]: - xq_ = xq.float().reshape(*xq.shape[:-1], -1, 1, 2) - xk_ = xk.float().reshape(*xk.shape[:-1], -1, 1, 2) - xq_out = freqs_cis[..., 0] * xq_[..., 0] + freqs_cis[..., 1] * xq_[..., 1] - xk_out = freqs_cis[..., 0] * xk_[..., 0] + freqs_cis[..., 1] * xk_[..., 1] - return xq_out.reshape(*xq.shape).cast(xq.dtype), xk_out.reshape(*xk.shape).cast(xk.dtype) - - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/modules/layers.py -class EmbedND: - def __init__(self, dim:int, theta:int, axes_dim:List[int]): - self.dim = dim - self.theta = theta - self.axes_dim = axes_dim - - def __call__(self, ids:Tensor) -> Tensor: - n_axes = ids.shape[-1] - emb = Tensor.cat(*[rope(ids[..., i], self.axes_dim[i], self.theta) for i in range(n_axes)], dim=-3) - return emb.unsqueeze(1) - -class MLPEmbedder: - def __init__(self, in_dim:int, hidden_dim:int): - self.in_layer = nn.Linear(in_dim, hidden_dim, bias=True) - self.out_layer = nn.Linear(hidden_dim, hidden_dim, bias=True) - - def __call__(self, x:Tensor) -> Tensor: - return self.out_layer(self.in_layer(x).silu()) - -class QKNorm: - def __init__(self, dim:int): - self.query_norm = nn.RMSNorm(dim) - self.key_norm = nn.RMSNorm(dim) - - def __call__(self, q:Tensor, k:Tensor) -> Tuple[Tensor, Tensor]: - return self.query_norm(q), self.key_norm(k) - -class SelfAttention: - def __init__(self, dim:int, num_heads:int = 8, qkv_bias:bool = False): - self.num_heads = num_heads - head_dim = dim // num_heads - - self.qkv = nn.Linear(dim, dim * 3, bias=qkv_bias) - self.norm = QKNorm(head_dim) - self.proj = nn.Linear(dim, dim) - - def __call__(self, x:Tensor, pe:Tensor) -> Tensor: - qkv = self.qkv(x) - q, k, v = qkv.rearrange("B L (K H D) -> K B H L D", K=3, H=self.num_heads) - q, k = self.norm(q, k) - x = attention(q, k, v, pe=pe) - return self.proj(x) - -@dataclass -class ModulationOut: - shift:Tensor - scale:Tensor - gate:Tensor - -class Modulation: - def __init__(self, dim:int, double:bool): - self.is_double = double - self.multiplier = 6 if double else 3 - self.lin = nn.Linear(dim, self.multiplier * dim, bias=True) - - def __call__(self, vec:Tensor) -> Tuple[ModulationOut, Optional[ModulationOut]]: - out = self.lin(vec.silu())[:, None, :].chunk(self.multiplier, dim=-1) - return ModulationOut(*out[:3]), ModulationOut(*out[3:]) if self.is_double else None - -class DoubleStreamBlock: - def __init__(self, hidden_size:int, num_heads:int, mlp_ratio:float, qkv_bias:bool = False): - mlp_hidden_dim = int(hidden_size * mlp_ratio) - self.num_heads = num_heads - self.hidden_size = hidden_size - self.img_mod = Modulation(hidden_size, double=True) - self.img_norm1 = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - self.img_attn = SelfAttention(dim=hidden_size, num_heads=num_heads, qkv_bias=qkv_bias) - - self.img_norm2 = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - self.img_mlp = [nn.Linear(hidden_size, mlp_hidden_dim, bias=True), Tensor.gelu, nn.Linear(mlp_hidden_dim, hidden_size, bias=True)] - - self.txt_mod = Modulation(hidden_size, double=True) - self.txt_norm1 = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - self.txt_attn = SelfAttention(dim=hidden_size, num_heads=num_heads, qkv_bias=qkv_bias) - - self.txt_norm2 = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - self.txt_mlp = [nn.Linear(hidden_size, mlp_hidden_dim, bias=True), Tensor.gelu, nn.Linear(mlp_hidden_dim, hidden_size, bias=True)] - - def __call__(self, img:Tensor, txt:Tensor, vec:Tensor, pe:Tensor) -> tuple[Tensor, Tensor]: - img_mod1, img_mod2 = self.img_mod(vec) - txt_mod1, txt_mod2 = self.txt_mod(vec) - assert img_mod2 is not None and txt_mod2 is not None - # prepare image for attention - img_modulated = self.img_norm1(img) - img_modulated = (1 + img_mod1.scale) * img_modulated + img_mod1.shift - img_qkv = self.img_attn.qkv(img_modulated) - img_q, img_k, img_v = img_qkv.rearrange("B L (K H D) -> K B H L D", K=3, H=self.num_heads) - img_q, img_k = self.img_attn.norm(img_q, img_k) - - # prepare txt for attention - txt_modulated = self.txt_norm1(txt) - txt_modulated = (1 + txt_mod1.scale) * txt_modulated + txt_mod1.shift - txt_qkv = self.txt_attn.qkv(txt_modulated) - txt_q, txt_k, txt_v = txt_qkv.rearrange("B L (K H D) -> K B H L D", K=3, H=self.num_heads) - txt_q, txt_k = self.txt_attn.norm(txt_q, txt_k) - - # run actual attention - q = Tensor.cat(txt_q, img_q, dim=2) - k = Tensor.cat(txt_k, img_k, dim=2) - v = Tensor.cat(txt_v, img_v, dim=2) - - attn = attention(q, k, v, pe=pe) - txt_attn, img_attn = attn[:, : txt.shape[1]], attn[:, txt.shape[1] :] - - # calculate the img bloks - img = img + img_mod1.gate * self.img_attn.proj(img_attn) - img = img + img_mod2.gate * ((1 + img_mod2.scale) * self.img_norm2(img) + img_mod2.shift).sequential(self.img_mlp) - - # calculate the txt bloks - txt = txt + txt_mod1.gate * self.txt_attn.proj(txt_attn) - txt = txt + txt_mod2.gate * ((1 + txt_mod2.scale) * self.txt_norm2(txt) + txt_mod2.shift).sequential(self.txt_mlp) - return img, txt - - -class SingleStreamBlock: - """ - A DiT block with parallel linear layers as described in - https://arxiv.org/abs/2302.05442 and adapted modulation interface. - """ - - def __init__(self,hidden_size:int, num_heads:int, mlp_ratio:float=4.0, qk_scale:Optional[float]=None): - self.hidden_dim = hidden_size - self.num_heads = num_heads - head_dim = hidden_size // num_heads - self.scale = qk_scale or head_dim**-0.5 - - self.mlp_hidden_dim = int(hidden_size * mlp_ratio) - # qkv and mlp_in - self.linear1 = nn.Linear(hidden_size, hidden_size * 3 + self.mlp_hidden_dim) - # proj and mlp_out - self.linear2 = nn.Linear(hidden_size + self.mlp_hidden_dim, hidden_size) - - self.norm = QKNorm(head_dim) - - self.hidden_size = hidden_size - self.pre_norm = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - - self.mlp_act = Tensor.gelu - self.modulation = Modulation(hidden_size, double=False) - - def __call__(self, x:Tensor, vec:Tensor, pe:Tensor) -> Tensor: - mod, _ = self.modulation(vec) - x_mod = (1 + mod.scale) * self.pre_norm(x) + mod.shift - qkv, mlp = Tensor.split(self.linear1(x_mod), [3 * self.hidden_size, self.mlp_hidden_dim], dim=-1) - q, k, v = qkv.rearrange("B L (K H D) -> K B H L D", K=3, H=self.num_heads) - q, k = self.norm(q, k) - - # compute attention - attn = attention(q, k, v, pe=pe) - # compute activation in mlp stream, cat again and run second linear layer - output = self.linear2(Tensor.cat(attn, self.mlp_act(mlp), dim=2)) - return x + mod.gate * output - - -class LastLayer: - def __init__(self, hidden_size:int, patch_size:int, out_channels:int): - self.norm_final = nn.LayerNorm(hidden_size, elementwise_affine=False, eps=1e-6) - self.linear = nn.Linear(hidden_size, patch_size * patch_size * out_channels, bias=True) - self.adaLN_modulation:List[Callable[[Tensor], Tensor]] = [Tensor.silu, nn.Linear(hidden_size, 2 * hidden_size, bias=True)] - - def __call__(self, x:Tensor, vec:Tensor) -> Tensor: - shift, scale = vec.sequential(self.adaLN_modulation).chunk(2, dim=1) - x = (1 + scale[:, None, :]) * self.norm_final(x) + shift[:, None, :] - return self.linear(x) - -def timestep_embedding(t:Tensor, dim:int, max_period:int=10000, time_factor:float=1000.0) -> Tensor: - """ - Create sinusoidal timestep embeddings. - :param t: a 1-D Tensor of N indices, one per batch element. - These may be fractional. - :param dim: the dimension of the output. - :param max_period: controls the minimum frequency of the embeddings. - :return: an (N, D) Tensor of positional embeddings. - """ - t = time_factor * t - half = dim // 2 - freqs = Tensor.exp(-math.log(max_period) * Tensor.arange(0, stop=half, dtype=dtypes.float32) / half).to(t.device) - - args = t[:, None].float() * freqs[None] - embedding = Tensor.cat(Tensor.cos(args), Tensor.sin(args), dim=-1) - if dim % 2: embedding = Tensor.cat(*[embedding, Tensor.zeros_like(embedding[:, :1])], dim=-1) - if Tensor.is_floating_point(t): embedding = embedding.cast(t.dtype) - return embedding - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/model.py -class Flux: - """ - Transformer model for flow matching on sequences. - """ - - def __init__( - self, - guidance_embed:bool, - in_channels:int = 64, - vec_in_dim:int = 768, - context_in_dim:int = 4096, - hidden_size:int = 3072, - mlp_ratio:float = 4.0, - num_heads:int = 24, - depth:int = 19, - depth_single_blocks:int = 38, - axes_dim:Optional[List[int]] = None, - theta:int = 10_000, - qkv_bias:bool = True, - ): - - axes_dim = axes_dim or [16, 56, 56] - self.guidance_embed = guidance_embed - self.in_channels = in_channels - self.out_channels = self.in_channels - if hidden_size % num_heads != 0: - raise ValueError(f"Hidden size {hidden_size} must be divisible by num_heads {num_heads}") - pe_dim = hidden_size // num_heads - if sum(axes_dim) != pe_dim: - raise ValueError(f"Got {axes_dim} but expected positional dim {pe_dim}") - self.hidden_size = hidden_size - self.num_heads = num_heads - self.pe_embedder = EmbedND(dim=pe_dim, theta=theta, axes_dim=axes_dim) - self.img_in = nn.Linear(self.in_channels, self.hidden_size, bias=True) - self.time_in = MLPEmbedder(in_dim=256, hidden_dim=self.hidden_size) - self.vector_in = MLPEmbedder(vec_in_dim, self.hidden_size) - self.guidance_in:Callable[[Tensor], Tensor] = MLPEmbedder(in_dim=256, hidden_dim=self.hidden_size) if guidance_embed else tensor_identity - self.txt_in = nn.Linear(context_in_dim, self.hidden_size) - - self.double_blocks = [DoubleStreamBlock(self.hidden_size, self.num_heads, mlp_ratio=mlp_ratio, qkv_bias=qkv_bias) for _ in range(depth)] - self.single_blocks = [SingleStreamBlock(self.hidden_size, self.num_heads, mlp_ratio=mlp_ratio) for _ in range(depth_single_blocks)] - self.final_layer = LastLayer(self.hidden_size, 1, self.out_channels) - - def __call__(self, img:Tensor, img_ids:Tensor, txt:Tensor, txt_ids:Tensor, timesteps:Tensor, y:Tensor, guidance:Optional[Tensor] = None) -> Tensor: - if img.ndim != 3 or txt.ndim != 3: - raise ValueError("Input img and txt tensors must have 3 dimensions.") - # running on sequences img - img = self.img_in(img) - vec = self.time_in(timestep_embedding(timesteps, 256)) - if self.guidance_embed: - if guidance is None: - raise ValueError("Didn't get guidance strength for guidance distilled model.") - vec = vec + self.guidance_in(timestep_embedding(guidance, 256)) - vec = vec + self.vector_in(y) - txt = self.txt_in(txt) - ids = Tensor.cat(txt_ids, img_ids, dim=1) - pe = self.pe_embedder(ids) - for double_block in self.double_blocks: - img, txt = double_block(img=img, txt=txt, vec=vec, pe=pe) - - img = Tensor.cat(txt, img, dim=1) - for single_block in self.single_blocks: - img = single_block(img, vec=vec, pe=pe) - - img = img[:, txt.shape[1] :, ...] - - return self.final_layer(img, vec) # (N, T, patch_size ** 2 * out_channels) - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/util.py -def load_flow_model(name:str, model_path:str): - # Loading Flux - print("Init model") - model = Flux(guidance_embed=(name != "flux-schnell")) - if not model_path: model_path = fetch(urls[name]) - state_dict = {k.replace("scale", "weight"): v for k, v in safe_load(model_path).items()} - load_state_dict(model, state_dict) - return model - -def load_T5(max_length:int=512): - # max length 64, 128, 256 and 512 should work (if your sequence is short enough) - print("Init T5") - T5 = T5Embedder(max_length, fetch(urls["T5_tokenizer"])) - pt_1 = fetch(urls["T5_1_of_2"]) - pt_2 = fetch(urls["T5_2_of_2"]) - load_state_dict(T5.encoder, safe_load(pt_1) | safe_load(pt_2), strict=False) - return T5 - -def load_clip(): - print("Init Clip") - clip = ClipEmbedder() - load_state_dict(clip.transformer, safe_load(fetch(urls["clip"]))) - return clip - -def load_ae() -> AutoEncoder: - # Loading the autoencoder - print("Init AE") - ae = AutoEncoder(0.3611, 0.1159) - load_state_dict(ae, safe_load(fetch(urls["ae"]))) - return ae - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/sampling.py -def prepare(T5:T5Embedder, clip:ClipEmbedder, img:Tensor, prompt:Union[str, List[str]]) -> Dict[str, Tensor]: - bs, _, h, w = img.shape - if bs == 1 and not isinstance(prompt, str): - bs = len(prompt) - - img = img.rearrange("b c (h ph) (w pw) -> b (h w) (c ph pw)", ph=2, pw=2) - if img.shape[0] == 1 and bs > 1: - img = img.expand((bs, *img.shape[1:])) - - img_ids = Tensor.zeros(h // 2, w // 2, 3).contiguous() - img_ids[..., 1] = img_ids[..., 1] + Tensor.arange(h // 2)[:, None] - img_ids[..., 2] = img_ids[..., 2] + Tensor.arange(w // 2)[None, :] - img_ids = img_ids.rearrange("h w c -> 1 (h w) c") - img_ids = img_ids.expand((bs, *img_ids.shape[1:])) - - if isinstance(prompt, str): - prompt = [prompt] - txt = T5(prompt).realize() - if txt.shape[0] == 1 and bs > 1: - txt = txt.expand((bs, *txt.shape[1:])) - txt_ids = Tensor.zeros(bs, txt.shape[1], 3) - - vec = clip(prompt).realize() - if vec.shape[0] == 1 and bs > 1: - vec = vec.expand((bs, *vec.shape[1:])) - - return {"img": img, "img_ids": img_ids.to(img.device), "txt": txt.to(img.device), "txt_ids": txt_ids.to(img.device), "vec": vec.to(img.device)} - - -def get_schedule(num_steps:int, image_seq_len:int, base_shift:float=0.5, max_shift:float=1.15, shift:bool=True) -> List[float]: - # extra step for zero - step_size = -1.0 / num_steps - timesteps = Tensor.arange(1, 0 + step_size, step_size) - - # shifting the schedule to favor high timesteps for higher signal images - if shift: - # estimate mu based on linear estimation between two points - mu = 0.5 + (max_shift - base_shift) * (image_seq_len - 256) / (4096 - 256) - timesteps = math.exp(mu) / (math.exp(mu) + (1 / timesteps - 1)) - return timesteps.tolist() - -@TinyJit -def run(model, *args): return model(*args).realize() - -def denoise(model, img:Tensor, img_ids:Tensor, txt:Tensor, txt_ids:Tensor, vec:Tensor, timesteps:List[float], guidance:float=4.0) -> Tensor: - # this is ignored for schnell - guidance_vec = Tensor((guidance,), device=img.device, dtype=img.dtype).expand((img.shape[0],)) - for t_curr, t_prev in tqdm(list(zip(timesteps[:-1], timesteps[1:])), "Denoising"): - t_vec = Tensor((t_curr,), device=img.device, dtype=img.dtype).expand((img.shape[0],)) - pred = run(model, img, img_ids, txt, txt_ids, t_vec, vec, guidance_vec) - img = img + (t_prev - t_curr) * pred - - return img - -def unpack(x:Tensor, height:int, width:int) -> Tensor: - return x.rearrange("b (h w) (c ph pw) -> b c (h ph) (w pw)", h=math.ceil(height / 16), w=math.ceil(width / 16), ph=2, pw=2) - -# https://github.com/black-forest-labs/flux/blob/main/src/flux/cli.py -if __name__ == "__main__": - default_prompt = "bananas and a can of coke" - parser = argparse.ArgumentParser(description="Run Flux.1", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - - parser.add_argument("--name", type=str, default="flux-schnell", help="Name of the model to load") - parser.add_argument("--model_path", type=str, default="", help="path of the model file") - parser.add_argument("--width", type=int, default=512, help="width of the sample in pixels (should be a multiple of 16)") - parser.add_argument("--height", type=int, default=512, help="height of the sample in pixels (should be a multiple of 16)") - parser.add_argument("--seed", type=int, default=None, help="Set a seed for sampling") - parser.add_argument("--prompt", type=str, default=default_prompt, help="Prompt used for sampling") - parser.add_argument('--out', type=str, default=Path(tempfile.gettempdir()) / "rendered.png", help="Output filename") - parser.add_argument("--num_steps", type=int, default=None, help="number of sampling steps (default 4 for schnell, 50 for guidance distilled)") #noqa:E501 - parser.add_argument("--guidance", type=float, default=3.5, help="guidance value used for guidance distillation") - parser.add_argument("--output_dir", type=str, default="output", help="output directory") - args = parser.parse_args() - - if args.name not in ["flux-schnell", "flux-dev"]: - raise ValueError(f"Got unknown model name: {args.name}, chose from flux-schnell and flux-dev") - - if args.num_steps is None: - args.num_steps = 4 if args.name == "flux-schnell" else 50 - - # allow for packing and conversion to latent space - height = 16 * (args.height // 16) - width = 16 * (args.width // 16) - - if args.seed is None: args.seed = Tensor._seed - else: Tensor.manual_seed(args.seed) - - print(f"Generating with seed {args.seed}:\n{args.prompt}") - t0 = time.perf_counter() - - # prepare input noise - x = Tensor.randn(1, 16, 2 * math.ceil(height / 16), 2 * math.ceil(width / 16), dtype="bfloat16") - - # load text embedders - T5 = load_T5(max_length=256 if args.name == "flux-schnell" else 512) - clip = load_clip() - - # embed text to get inputs for model - inp = prepare(T5, clip, x, prompt=args.prompt) - timesteps = get_schedule(args.num_steps, inp["img"].shape[1], shift=(args.name != "flux-schnell")) - - # done with text embedders - del T5, clip - - # load model - model = load_flow_model(args.name, args.model_path) - - # denoise initial noise - x = denoise(model, **inp, timesteps=timesteps, guidance=args.guidance) - - # done with model - del model, run - - # load autoencoder - ae = load_ae() - - # decode latents to pixel space - x = unpack(x.float(), height, width) - x = ae.decode(x).realize() - - t1 = time.perf_counter() - print(f"Done in {t1 - t0:.1f}s. Saving {args.out}") - - # bring into PIL format and save - x = x.clamp(-1, 1) - x = x[0].rearrange("c h w -> h w c") - x = (127.5 * (x + 1.0)).cast("uint8") - - img = Image.fromarray(x.numpy()) - - img.save(args.out) - - # validation! - if args.prompt == default_prompt and args.name=="flux-schnell" and args.seed == 0 and args.width == args.height == 512: - ref_image = Tensor(np.array(Image.open("examples/flux1_seed0.png"))) - distance = (((x.cast(dtypes.float) - ref_image.cast(dtypes.float)) / ref_image.max())**2).mean().item() - assert distance < 4e-3, colored(f"validation failed with {distance=}", "red") - print(colored(f"output validated with {distance=}", "green")) \ No newline at end of file diff --git a/tinygrad/examples/flux1_seed0.png b/tinygrad/examples/flux1_seed0.png deleted file mode 100644 index 3acd1719..00000000 Binary files a/tinygrad/examples/flux1_seed0.png and /dev/null differ diff --git a/tinygrad/examples/gpt2.py b/tinygrad/examples/gpt2.py deleted file mode 100644 index 6a233327..00000000 --- a/tinygrad/examples/gpt2.py +++ /dev/null @@ -1,248 +0,0 @@ -#!/usr/bin/env python3 -import os, argparse, contextlib -from typing import Optional, Union -with contextlib.suppress(ImportError): import tiktoken -from tinygrad import Tensor, TinyJit, Device, GlobalCounters, Variable, dtypes -from tinygrad.uop.ops import UOp -from tinygrad.helpers import Timing, DEBUG, JIT, getenv, fetch, colored, trange -from tinygrad.nn import Embedding, Linear, LayerNorm -from tinygrad.nn.state import gguf_load, torch_load, load_state_dict, get_state_dict -from extra.bench_log import BenchEvent, WallTimeEvent - -MAX_CONTEXT = getenv("MAX_CONTEXT", 128) -HALF = getenv("HALF") - -class Attention: - def __init__(self, dim, n_heads): - self.c_attn = Linear(dim, 3*dim, bias=True) - self.c_proj = Linear(dim, dim, bias=True) - self.n_heads = n_heads - self.dim = dim - self.head_dim = dim // n_heads - - def __call__(self, x:Tensor, start_pos:Variable, mask:Optional[Tensor]) -> Tensor: - if mask is not None or start_pos.val == 0: - # no symbolic shape qkv when consuming prompts - start_pos = start_pos.val - - if HALF: x = x.half() - xqkv = self.c_attn(x) - xq, xk, xv = [xqkv.shrink((None, None, (i*self.dim, (i+1)*self.dim))).reshape(None, None, self.n_heads, self.head_dim) for i in range(3)] - bsz, seqlen, _, _ = xq.shape - - # create kv cache - if not hasattr(self, "cache_kv"): - self.cache_kv = Tensor.zeros(2, bsz, MAX_CONTEXT, self.n_heads, self.head_dim, dtype=x.dtype).contiguous().realize() - - # update the cache - self.cache_kv.shrink((None, None,(start_pos,start_pos+seqlen),None,None)).assign(Tensor.stack(xk, xv)).realize() - - if start_pos > 0: - keys = self.cache_kv[0].shrink((None, (0, start_pos+seqlen), None, None)) - values = self.cache_kv[1].shrink((None, (0, start_pos+seqlen), None, None)) - else: - keys = xk - values = xv - - xq, keys, values = xq.transpose(1, 2), keys.transpose(1, 2), values.transpose(1, 2) - return self.c_proj(xq.scaled_dot_product_attention(keys, values, mask).transpose(1, 2).reshape(bsz, seqlen, self.dim)) - -class FeedForward: - def __init__(self, dim, hidden_dim): - self.c_fc = Linear(dim, hidden_dim, bias=True) - self.c_proj = Linear(hidden_dim, dim, bias=True) - - def __call__(self, x:Tensor) -> Tensor: - return self.c_proj(self.c_fc(x).gelu()) - -class TransformerBlock: - def __init__(self, dim, n_heads, norm_eps): - self.attn = Attention(dim, n_heads) - self.mlp = FeedForward(dim, 4*dim) - self.ln_1 = LayerNorm(dim, norm_eps) - self.ln_2 = LayerNorm(dim, norm_eps) - - def __call__(self, x:Tensor, start_pos:Variable, mask:Optional[Tensor]): - h = x + self.attn(self.ln_1(x), start_pos, mask).float() - return (h + self.mlp(self.ln_2(h))) - -class Transformer: - def __init__(self, dim, n_heads, n_layers, norm_eps, vocab_size, max_seq_len=1024): - self.vocab_size = vocab_size - self.wte = Embedding(vocab_size, dim) - self.wpe = Embedding(max_seq_len, dim) - self.h = [TransformerBlock(dim, n_heads, norm_eps) for _ in range(n_layers)] - self.ln_f = LayerNorm(dim, norm_eps) - self.lm_head = Linear(dim, vocab_size, bias=False) - self.forward_jit = TinyJit(self.forward) - - def forward(self, tokens:Union[Tensor,UOp], start_pos:Variable, temperature:float=0.0): - if not hasattr(self, 'allpos'): self.allpos = Tensor.arange(0, MAX_CONTEXT).reshape(1, -1).realize() - if isinstance(tokens, UOp): - seqlen = 1 - tok_emb = self.wte.weight.shrink(((tokens, tokens+1), None)) - else: - seqlen = tokens.shape[1] - tok_emb = self.wte(tokens) - - # not symbolic when consuming the prompt - selected_pos = (0, seqlen) if start_pos.val == 0 else (start_pos, start_pos+1) - pos_emb = self.wpe(self.allpos.shrink((None, selected_pos))) - - h = tok_emb + pos_emb - - if HALF: h = h.half() - - mask = Tensor.full((1, 1, seqlen, start_pos.val+seqlen), float("-inf"), dtype=h.dtype).triu(start_pos.val+1) if seqlen > 1 else None - - for hi in self.h: h = hi(h, start_pos, mask) - - logits = self.lm_head(self.ln_f(h)) - - if logits.shape[1] == 0: - # special case for empty prompt - logits = Tensor.ones((logits.shape[0], self.vocab_size), dtype=logits.dtype, device=logits.device) - else: - logits = logits[:, -1, :] - - if temperature < 1e-6: - ret = logits.argmax(-1) - else: - ret = (logits / temperature).softmax().multinomial() - return ret.flatten().realize() - - def __call__(self, tokens:Union[Tensor,UOp], start_pos:Variable, temperature:float=0.0) -> Tensor: - forward = (self.forward_jit if JIT and (isinstance(tokens, UOp) or tokens.shape[1] == 1) else self.forward) - return forward(tokens, start_pos, temperature) - -VOCAB_SIZE = 50257 -MODEL_PARAMS = { - 'gpt2': dict(n_layers=12, n_heads=12, dim=768, norm_eps=1e-5, vocab_size=VOCAB_SIZE), # 124M params - 'gpt2-medium': dict(n_layers=24, n_heads=16, dim=1024, norm_eps=1e-5, vocab_size=VOCAB_SIZE), # 350M params - 'gpt2-large': dict(n_layers=36, n_heads=20, dim=1280, norm_eps=1e-5, vocab_size=VOCAB_SIZE), # 774M params - 'gpt2-xl': dict(n_layers=48, n_heads=25, dim=1600, norm_eps=1e-5, vocab_size=VOCAB_SIZE), # 1558M params -} - -class GPT2: - @staticmethod - def build(model_size="gpt2"): - tokenizer = tiktoken.get_encoding("gpt2") - - model = Transformer(**MODEL_PARAMS[model_size]) - weights = torch_load(fetch(f'https://huggingface.co/{model_size}/resolve/main/pytorch_model.bin')) - # special treatment for the Conv1D weights we need to transpose - transposed = ('attn.c_attn.weight', 'attn.c_proj.weight', 'mlp.c_fc.weight', 'mlp.c_proj.weight') - for k in weights: - if k.endswith(transposed): - weights[k] = weights[k].T - # lm head and wte are tied - weights['lm_head.weight'] = weights['wte.weight'] - - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - load_state_dict(model, weights) - - if HALF: - for l in get_state_dict(model).values(): - l.replace(l.half().realize()) - - return GPT2(model, tokenizer) - - @staticmethod - def build_gguf(model_size: str): - q_type = model_size[len("gpt2_gguf_"):].upper() - fn = fetch(f"https://huggingface.co/PrunaAI/gpt2-GGUF-smashed/resolve/main/gpt2.{q_type}.gguf?download=true") - gguf_tensor = Tensor.empty(os.stat(fn).st_size, dtype=dtypes.uint8, device=f"disk:{fn}").to(Device.DEFAULT) - kv_data, state_dict = gguf_load(gguf_tensor) - - gpt2_params = { - "dim": kv_data["gpt2.embedding_length"], "n_heads": kv_data["gpt2.attention.head_count"], - "n_layers": kv_data["gpt2.block_count"], "norm_eps": kv_data["gpt2.attention.layer_norm_epsilon"], - "vocab_size": VOCAB_SIZE, "max_seq_len": kv_data["gpt2.context_length"], - } - def _remap_gguf_key(key: str): - replaces = [ - ("blk.", "h."), (".attn_qkv.bias", ".attn.c_attn.bias"), (".attn_qkv.weight", ".attn.c_attn.weight"), - (".ffn_norm.bias", ".ln_2.bias"), (".ffn_norm.weight", ".ln_2.weight"), (".attn_norm.bias", ".ln_1.bias"), - (".attn_norm.weight", ".ln_1.weight"), (".attn_output.bias", ".attn.c_proj.bias"), (".attn_output.weight", ".attn.c_proj.weight"), - (".ffn_up.bias", ".mlp.c_fc.bias"), (".ffn_up.weight", ".mlp.c_fc.weight"), (".ffn_down.bias", ".mlp.c_proj.bias"), - (".ffn_down.weight", ".mlp.c_proj.weight"), ("token_embd.weight", "wte.weight"), ("output.weight", "lm_head.weight"), - ("output_norm.bias", "ln_f.bias"), ("output_norm.weight", "ln_f.weight"), ("position_embd.weight", "wpe.weight"), - ] - for ostr, ns in replaces: key = key.replace(ostr, ns) - return key - state_dict = { _remap_gguf_key(k): v for k, v in state_dict.items() } - model = Transformer(**gpt2_params) - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - load_state_dict(model, state_dict) - return GPT2(model, tiktoken.get_encoding("gpt2")) - - def __init__(self, model, tokenizer): - self.model = model - self.tokenizer = tokenizer - - def generate(self, prompt:str, max_length:int, temperature:float, timing:bool=False, batch_size:int=1): - prompt_tokens = self.tokenizer.encode(prompt, allowed_special={"<|endoftext|>"}) - toks = [prompt_tokens[:] for _ in range(batch_size)] - start_pos = 0 - for _ in trange(max_length, disable=(timing==True)): - GlobalCounters.reset() - if timing: print("") - st = GlobalCounters.time_sum_s - with Timing("ran model in ", on_exit=(lambda et: (f", {(GlobalCounters.time_sum_s-st)*1e3:.2f} ms on GPU" if DEBUG>=2 else "")+ - f", {GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.global_mem*1e-9:.2f} GB"+ - (f", {GlobalCounters.global_mem*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s" if DEBUG>=2 else "")) if DEBUG else None, enabled=timing): - with WallTimeEvent(BenchEvent.STEP): - if batch_size == 1 and len(toks[0][start_pos:]) == 1: - tokens = Variable("tokens", 0, VOCAB_SIZE-1).bind(toks[0][start_pos]) - else: - tokens = Tensor([x[start_pos:] for x in toks]) - tok = self.model(tokens, Variable("start_pos", 1 if start_pos else 0, MAX_CONTEXT-1).bind(start_pos), temperature).tolist() - start_pos = len(toks[0]) - for i,t in enumerate(tok): toks[i].append(t) - return [self.tokenizer.decode(x) for x in toks] - -# **** main code **** - -if __name__ == "__main__": - print(f"using {Device.DEFAULT} backend") - default_prompt = "What is the answer to life, the universe, and everything?" - - parser = argparse.ArgumentParser(description='Run GPT2 in tinygrad', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--prompt', type=str, default=default_prompt, help="Phrase to start with") - parser.add_argument('--count', type=int, default=100, help="Max number of tokens to generate") - parser.add_argument('--temperature', type=float, default=0.8, help="Temperature in the softmax") - parser.add_argument('--model_size', type=str, default="gpt2-medium", help="Size of model to use [gpt2, gpt2-medium, gpt2-large, gpt2-xl]") - parser.add_argument('--timing', action='store_true', help="Print timing per token") - parser.add_argument('--seed', type=int, help="Set the random seed") - parser.add_argument('--batch_size', type=int, default=1, help="Set the input batch size") - parser.add_argument('--benchmark', type=int, default=-1, help="Benchmark GPT with the given number of tokens") - parser.add_argument('--noshow', action='store_true', help="Don't show the output") - args = parser.parse_args() - - if args.seed is not None: - Tensor.manual_seed(args.seed) - - print(f"using {args.model_size}") - gpt2 = GPT2.build_gguf(args.model_size) if args.model_size.startswith("gpt2_gguf_") else GPT2.build(args.model_size) - - if args.benchmark != -1: - gpt2.model(Tensor.rand(args.batch_size, args.benchmark), Variable("a", 0, MAX_CONTEXT).bind(0)).realize() - else: - texts = gpt2.generate(args.prompt, args.count, args.temperature, timing=args.timing, batch_size=args.batch_size) - if not args.noshow: - print('Generating text...') - if len(texts) == 1: print(texts[0]) - else: - for i,text in enumerate(texts): print(colored(f"Response {i}:", "green"), text) - - # validate output! - if args.temperature == 0 and args.model_size == "gpt2-medium" and args.count == 10: - expected = { - default_prompt: "What is the answer to life, the universe, and everything?\n\nThe answer is that we are all one", - "Hello.": "Hello. I'm a little late to the party, but", - } - try: - assert texts[0] == expected[args.prompt] - print(colored("output validated", "green")) - except KeyError: - pass diff --git a/tinygrad/examples/handcode_opt.py b/tinygrad/examples/handcode_opt.py deleted file mode 100644 index cdb7e328..00000000 --- a/tinygrad/examples/handcode_opt.py +++ /dev/null @@ -1,133 +0,0 @@ -from extra.models.resnet import ResNet50 -from extra.mcts_search import mcts_search -from examples.mlperf.helpers import get_mlperf_bert_model -from tinygrad import Tensor, Device, dtypes, nn -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.uop.ops import Ops, sym_infer -from tinygrad.device import Compiled -from tinygrad.engine.search import beam_search, bufs_from_lin -from tinygrad.helpers import DEBUG, ansilen, getenv, colored, TRACEMETA -from extra.optimization.helpers import time_linearizer - -def get_sched_resnet(): - mdl = ResNet50() - optim = (nn.optim.LARS if getenv("LARS") else nn.optim.SGD)(nn.state.get_parameters(mdl)) - BS = getenv("BS", 64) - - # run model twice to get only what changes, these are the kernels of the model - for _ in range(2): - out = mdl(Tensor.empty(BS, 3, 224, 224)) - targets = [out] - if getenv("BACKWARD"): - optim.zero_grad() - out.sparse_categorical_crossentropy(Tensor.empty(BS, dtype=dtypes.int)).backward() - targets += [x for x in optim.schedule_step()] - sched = Tensor.schedule(*targets) - print(f"schedule length {len(sched)}") - return sched - -def get_sched_bert(): - mdl = get_mlperf_bert_model() - optim = nn.optim.LAMB(nn.state.get_parameters(mdl)) - - # fake data - BS = getenv("BS", 9) - input_ids = Tensor.empty((BS, 512), dtype=dtypes.float32) - segment_ids = Tensor.empty((BS, 512), dtype=dtypes.float32) - attention_mask = Tensor.empty((BS, 512), dtype=dtypes.default_float) - masked_positions = Tensor.empty((BS, 76), dtype=dtypes.float32) - masked_lm_ids = Tensor.empty((BS, 76), dtype=dtypes.float32) - masked_lm_weights = Tensor.empty((BS, 76), dtype=dtypes.float32) - next_sentence_labels = Tensor.empty((BS, 1), dtype=dtypes.float32) - - # run model twice to get only what changes, these are the kernels of the model - for _ in range(2): - lm_logits, seq_relationship_logits = mdl(input_ids, attention_mask, masked_positions, segment_ids) - targets = [lm_logits, seq_relationship_logits] - if getenv("BACKWARD"): - optim.zero_grad() - loss = mdl.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) - # ignore grad norm and loss scaler for now - loss.backward() - targets += [x for x in optim.schedule_step()] - sched = Tensor.schedule(*targets) - print(f"schedule length {len(sched)}") - return sched - -if __name__ == "__main__": - if getenv("HALF", 1): - dtypes.default_float = dtypes.half - - # the device we are optimizing for - device: Compiled = Device[Device.DEFAULT] - if getenv("BACKWARD"): Tensor.training = True - print(f"optimizing for {Device.DEFAULT}") - - sched = globals()[f"get_sched_{getenv('MODEL', 'resnet')}"]() - sched = [x for x in sched if x.ast.op is Ops.SINK] - - # focus on one kernel - if getenv("KERNEL", -1) >= 0: sched = sched[getenv("KERNEL", -1):getenv("KERNEL", -1)+1] - - # work with the schedule - total_tm = 0 - running_gflops = 0 - usage = {} - for i,si in enumerate(sched): - if DEBUG >= 3: print(si.ast) - - rawbufs = bufs_from_lin(Kernel(si.ast)) - - # "linearize" the op into uops in different ways - lins: list[tuple[Kernel, str]] = [] - - # always try hand coded opt - lin = Kernel(si.ast, opts=device.renderer) - lin.apply_opts(hand_coded_optimizations(lin)) - lins.append((lin, "HC")) - - # maybe try tensor cores - lin = Kernel(si.ast, opts=device.renderer) - if lin.apply_tensor_cores(): - lins.append((lin, "TC")) - - # try a beam search - if beam:=getenv("BEAM"): - lin = Kernel(si.ast, opts=device.renderer) - lin = beam_search(lin, rawbufs, beam, bool(getenv("BEAM_ESTIMATE", 1))) - lins.append((lin, "BEAM")) - - # try MCTS - if mcts:=getenv("MCTS"): - lin = Kernel(si.ast, opts=device.renderer) - lin = mcts_search(lin, rawbufs, mcts) - lins.append((lin, "MCTS")) - - # benchmark the programs - choices = [] - for lin, nm in lins: - tm = time_linearizer(lin, rawbufs, allow_test_size=False, cnt=10, disable_cache=True) - ops = (prg:=lin.to_program()).estimates.ops - gflops = sym_infer(ops, {k:k.min for k in lin.ast.variables()})*1e-9/tm - choices.append((tm, gflops, lin, prg, nm)) - - sorted_choices = sorted(choices, key=lambda x: x[0]) - if DEBUG >= 1: # print all kernels - for tm, gflops, lin, prg, nm in choices: - print(f" kernel {i:2d} {lin.name+' '*(37-ansilen(lin.name))} {str(prg.global_size):18s} {str(prg.local_size):12s} takes {tm*1000:7.2f} ms, {gflops:6.0f} GFLOPS -- {colored(nm, 'green') if lin is sorted_choices[0][2] else nm}") - - tm, gflops, lin, prg, nm = sorted_choices[0] - if getenv("SRC"): - print(si.ast) - print(lin.applied_opts) - print(lin.to_program().src) - total_tm += tm - running_gflops += gflops * tm - if (key := str([str(m) for m in si.metadata])) not in usage: usage[key] = (0, 0) - usage[key] = (usage[key][0] + tm, usage[key][1] + 1) - print(f"*** {total_tm*1000:7.2f} ms : kernel {i:2d} {lin.name+' '*(37-ansilen(lin.name))} {str(prg.global_size):18s} {str(prg.local_size):12s} takes {tm*1000:7.2f} ms, {gflops:6.0f} GFLOPS {[repr(m) if TRACEMETA >= 2 else str(m) for m in si.metadata]}") - print(f"******* total {total_tm*1000:.2f} ms, {running_gflops/total_tm:6.0f} GFLOPS") - print("usage:") - for k in sorted(usage, key=lambda x: -usage[x][0])[:10]: - print(f"{usage[k][0]*1000:.2f} ms: {k} ({usage[k][1]} times)") diff --git a/tinygrad/examples/hlb_cifar10.py b/tinygrad/examples/hlb_cifar10.py deleted file mode 100644 index ff6c48b6..00000000 --- a/tinygrad/examples/hlb_cifar10.py +++ /dev/null @@ -1,429 +0,0 @@ -#!/usr/bin/env python3 - -# tinygrad implementation of https://github.com/tysam-code/hlb-CIFAR10/blob/main/main.py -# https://myrtle.ai/learn/how-to-train-your-resnet-8-bag-of-tricks/ -# https://siboehm.com/articles/22/CUDA-MMM -import random, time -import numpy as np -from typing import Optional -from extra.lr_scheduler import OneCycleLR -from tinygrad import nn, dtypes, Tensor, Device, GlobalCounters, TinyJit -from tinygrad.nn.state import get_state_dict, get_parameters -from tinygrad.nn import optim -from tinygrad.helpers import Context, BEAM, WINO, getenv, colored, prod -from extra.bench_log import BenchEvent, WallTimeEvent - -cifar_mean = [0.4913997551666284, 0.48215855929893703, 0.4465309133731618] -cifar_std = [0.24703225141799082, 0.24348516474564, 0.26158783926049628] - -BS, STEPS = getenv("BS", 512), getenv("STEPS", 1000) -EVAL_BS = getenv("EVAL_BS", BS) -GPUS = [f'{Device.DEFAULT}:{i}' for i in range(getenv("GPUS", 1))] -assert BS % len(GPUS) == 0, f"{BS=} is not a multiple of {len(GPUS)=}, uneven multi GPU is slow" -assert EVAL_BS % len(GPUS) == 0, f"{EVAL_BS=} is not a multiple of {len(GPUS)=}, uneven multi GPU is slow" - -class UnsyncedBatchNorm: - def __init__(self, sz:int, eps=1e-5, affine=True, track_running_stats=True, momentum=0.1, num_devices=len(GPUS)): - self.eps, self.track_running_stats, self.momentum = eps, track_running_stats, momentum - self.num_devices = num_devices - - if affine: self.weight, self.bias = Tensor.ones(sz, dtype=dtypes.float32), Tensor.zeros(sz, dtype=dtypes.float32) - else: self.weight, self.bias = None, None - - self.running_mean = Tensor.zeros(num_devices, sz, dtype=dtypes.float32, requires_grad=False) - self.running_var = Tensor.ones(num_devices, sz, dtype=dtypes.float32, requires_grad=False) - self.num_batches_tracked = Tensor.zeros(1, dtype=dtypes.int, requires_grad=False) - - def __call__(self, x:Tensor): - xr = x.reshape(self.num_devices, -1, *x.shape[1:]).cast(dtypes.float32) - batch_mean, batch_invstd = self.calc_stats(xr) - ret = xr.batchnorm( - self.weight.reshape(1, -1).expand((self.num_devices, -1)), - self.bias.reshape(1, -1).expand((self.num_devices, -1)), - batch_mean, batch_invstd, axis=(0, 2)) - return ret.reshape(x.shape).cast(x.dtype) - - def calc_stats(self, x:Tensor): - if Tensor.training: - # This requires two full memory accesses to x - # https://github.com/pytorch/pytorch/blob/c618dc13d2aa23625cb0d7ada694137532a4fa33/aten/src/ATen/native/cuda/Normalization.cuh - # There's "online" algorithms that fix this, like https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance#Welford's_Online_algorithm - batch_mean = x.mean(axis=(1,3,4)) - y = (x - batch_mean.detach().reshape(shape=[batch_mean.shape[0], 1, -1, 1, 1])) # d(var)/d(mean) = 0 - batch_var = (y*y).mean(axis=(1,3,4)) - batch_invstd = batch_var.add(self.eps).pow(-0.5) - - # NOTE: wow, this is done all throughout training in most PyTorch models - if self.track_running_stats: - self.running_mean.assign((1-self.momentum) * self.running_mean + self.momentum * batch_mean.detach().cast(self.running_mean.dtype)) - batch_var_adjust = prod(y.shape[1:])/(prod(y.shape[1:])-y.shape[2]) - self.running_var.assign((1-self.momentum) * self.running_var + self.momentum * batch_var_adjust * batch_var.detach().cast(self.running_var.dtype)) - self.num_batches_tracked += 1 - else: - batch_mean = self.running_mean - # NOTE: this can be precomputed for static inference. we expand it here so it fuses - batch_invstd = self.running_var.reshape(self.running_var.shape[0], 1, -1, 1, 1).expand(x.shape).add(self.eps).rsqrt() - return batch_mean, batch_invstd - -class BatchNorm(nn.BatchNorm2d if getenv("SYNCBN") else UnsyncedBatchNorm): - def __init__(self, num_features): - super().__init__(num_features, track_running_stats=False, eps=1e-12, momentum=0.85, affine=True) - self.weight.requires_grad = False - self.bias.requires_grad = True - -class ConvGroup: - def __init__(self, channels_in, channels_out): - self.conv1 = nn.Conv2d(channels_in, channels_out, kernel_size=3, padding=1, bias=False) - self.conv2 = nn.Conv2d(channels_out, channels_out, kernel_size=3, padding=1, bias=False) - - self.norm1 = BatchNorm(channels_out) - self.norm2 = BatchNorm(channels_out) - - def __call__(self, x): - x = self.conv1(x) - x = x.max_pool2d(2) - x = x.float() - x = self.norm1(x) - x = x.cast(dtypes.default_float) - x = x.quick_gelu() - residual = x - x = self.conv2(x) - x = x.float() - x = self.norm2(x) - x = x.cast(dtypes.default_float) - x = x.quick_gelu() - - return x + residual - -class SpeedyResNet: - def __init__(self, W): - self.whitening = W - self.net = [ - nn.Conv2d(12, 32, kernel_size=1, bias=False), - lambda x: x.quick_gelu(), - ConvGroup(32, 64), - ConvGroup(64, 256), - ConvGroup(256, 512), - lambda x: x.max((2,3)), - nn.Linear(512, 10, bias=False), - lambda x: x / 9., - ] - - def __call__(self, x, training=True): - # pad to 32x32 because whitening conv creates 31x31 images that are awfully slow to compute with - # TODO: remove the pad but instead let the kernel optimize itself - forward = lambda x: x.conv2d(self.whitening).pad((1,0,0,1)).sequential(self.net) - return forward(x) if training else (forward(x) + forward(x[..., ::-1])) / 2. - -# hyper-parameters were exactly the same as the original repo -bias_scaler = 58 -hyp = { - 'seed' : 200, - 'opt': { - 'bias_lr': 1.76 * bias_scaler/512, - 'non_bias_lr': 1.76 / 512, - 'bias_decay': 1.08 * 6.45e-4 * BS/bias_scaler, - 'non_bias_decay': 1.08 * 6.45e-4 * BS, - 'final_lr_ratio': 0.025, - 'initial_div_factor': 1e6, - 'label_smoothing': 0.20, - 'momentum': 0.85, - 'percent_start': 0.23, - 'loss_scale_scaler': 1./128 # (range: ~1/512 - 16+, 1/128 w/ FP16) - }, - 'net': { - 'kernel_size': 2, # kernel size for the whitening layer - 'cutmix_size': 3, - 'cutmix_steps': 499, - 'pad_amount': 2 - }, - 'ema': { - 'steps': 399, - 'decay_base': .95, - 'decay_pow': 1.6, - 'every_n_steps': 5, - }, -} - -def train_cifar(): - - def set_seed(seed): - Tensor.manual_seed(seed) - random.seed(seed) - - # ========== Model ========== - def whitening(X, kernel_size=hyp['net']['kernel_size']): - def _cov(X): - return (X.T @ X) / (X.shape[0] - 1) - - def _patches(data, patch_size=(kernel_size,kernel_size)): - h, w = patch_size - c = data.shape[1] - axis = (2, 3) - return np.lib.stride_tricks.sliding_window_view(data, window_shape=(h,w), axis=axis).transpose((0,3,2,1,4,5)).reshape((-1,c,h,w)) - - def _eigens(patches): - n,c,h,w = patches.shape - Σ = _cov(patches.reshape(n, c*h*w)) - Λ, V = np.linalg.eigh(Σ, UPLO='U') - return np.flip(Λ, 0), np.flip(V.T.reshape(c*h*w, c, h, w), 0) - - # NOTE: np.linalg.eigh only supports float32 so the whitening layer weights need to be converted to float16 manually - Λ, V = _eigens(_patches(X.float().numpy())) - W = V/np.sqrt(Λ+1e-2)[:,None,None,None] - - return Tensor(W.astype(np.float32), requires_grad=False).cast(dtypes.default_float) - - # ========== Loss ========== - def cross_entropy(x:Tensor, y:Tensor, reduction:str='mean', label_smoothing:float=0.0) -> Tensor: - divisor = y.shape[1] - assert isinstance(divisor, int), "only supported int divisor" - y = (1 - label_smoothing)*y + label_smoothing / divisor - ret = -x.log_softmax(axis=1).mul(y).sum(axis=1) - if reduction=='none': return ret - if reduction=='sum': return ret.sum() - if reduction=='mean': return ret.mean() - raise NotImplementedError(reduction) - - # ========== Preprocessing ========== - # NOTE: this only works for RGB in format of NxCxHxW and pads the HxW - def pad_reflect(X, size=2) -> Tensor: - X = X[...,:,1:size+1].flip(-1).cat(X, X[...,:,-(size+1):-1].flip(-1), dim=-1) - X = X[...,1:size+1,:].flip(-2).cat(X, X[...,-(size+1):-1,:].flip(-2), dim=-2) - return X - - # return a binary mask in the format of BS x C x H x W where H x W contains a random square mask - def make_square_mask(shape, mask_size) -> Tensor: - BS, _, H, W = shape - low_x = Tensor.randint(BS, low=0, high=W-mask_size).reshape(BS,1,1,1) - low_y = Tensor.randint(BS, low=0, high=H-mask_size).reshape(BS,1,1,1) - idx_x = Tensor.arange(W, dtype=dtypes.int32).reshape((1,1,1,W)) - idx_y = Tensor.arange(H, dtype=dtypes.int32).reshape((1,1,H,1)) - return (idx_x >= low_x) * (idx_x < (low_x + mask_size)) * (idx_y >= low_y) * (idx_y < (low_y + mask_size)) - - def random_crop(X:Tensor, crop_size=32): - mask = make_square_mask(X.shape, crop_size) - mask = mask.expand((-1,3,-1,-1)) - X_cropped = Tensor(X.numpy()[mask.numpy()]) - return X_cropped.reshape((-1, 3, crop_size, crop_size)) - - def cutmix(X:Tensor, Y:Tensor, mask_size=3): - # fill the square with randomly selected images from the same batch - mask = make_square_mask(X.shape, mask_size) - order = list(range(0, X.shape[0])) - random.shuffle(order) - X_patch = Tensor(X.numpy()[order], device=X.device, dtype=X.dtype) - Y_patch = Tensor(Y.numpy()[order], device=Y.device, dtype=Y.dtype) - X_cutmix = mask.where(X_patch, X) - mix_portion = float(mask_size**2)/(X.shape[-2]*X.shape[-1]) - Y_cutmix = mix_portion * Y_patch + (1. - mix_portion) * Y - return X_cutmix, Y_cutmix - - # the operations that remain inside batch fetcher is the ones that involves random operations - def fetch_batches(X_in:Tensor, Y_in:Tensor, BS:int, is_train:bool): - step, epoch = 0, 0 - while True: - st = time.monotonic() - X, Y = X_in, Y_in - if is_train: - # TODO: these are not jitted - if getenv("RANDOM_CROP", 1): - X = random_crop(X, crop_size=32) - if getenv("RANDOM_FLIP", 1): - X = (Tensor.rand(X.shape[0],1,1,1) < 0.5).where(X.flip(-1), X) # flip LR - if getenv("CUTMIX", 1): - if step >= hyp['net']['cutmix_steps']: - X, Y = cutmix(X, Y, mask_size=hyp['net']['cutmix_size']) - order = list(range(0, X.shape[0])) - random.shuffle(order) - X, Y = X.numpy()[order], Y.numpy()[order] - else: - X, Y = X.numpy(), Y.numpy() - et = time.monotonic() - print(f"shuffling {'training' if is_train else 'test'} dataset in {(et-st)*1e3:.2f} ms ({epoch=})") - for i in range(0, X.shape[0], BS): - # pad the last batch # TODO: not correct for test - batch_end = min(i+BS, Y.shape[0]) - x = Tensor(X[batch_end-BS:batch_end], device=X_in.device, dtype=X_in.dtype) - y = Tensor(Y[batch_end-BS:batch_end], device=Y_in.device, dtype=Y_in.dtype) - step += 1 - yield x, y - epoch += 1 - if not is_train: break - - transform = [ - lambda x: x.float() / 255.0, - lambda x: x.reshape((-1,3,32,32)) - Tensor(cifar_mean, device=x.device, dtype=x.dtype).reshape((1,3,1,1)), - lambda x: x / Tensor(cifar_std, device=x.device, dtype=x.dtype).reshape((1,3,1,1)), - ] - - class modelEMA(): - def __init__(self, w, net): - # self.model_ema = copy.deepcopy(net) # won't work for opencl due to unpickeable pyopencl._cl.Buffer - self.net_ema = SpeedyResNet(w) - for net_ema_param, net_param in zip(get_state_dict(self.net_ema).values(), get_state_dict(net).values()): - net_ema_param.requires_grad = False - net_ema_param.assign(net_param.numpy()) - - @TinyJit - def update(self, net, decay): - for net_ema_param, (param_name, net_param) in zip(get_state_dict(self.net_ema).values(), get_state_dict(net).items()): - # batchnorm currently is not being tracked - if not ("num_batches_tracked" in param_name) and not ("running" in param_name): - net_ema_param.assign(net_ema_param.detach()*decay + net_param.detach()*(1.-decay)).realize() - - set_seed(getenv('SEED', hyp['seed'])) - - X_train, Y_train, X_test, Y_test = nn.datasets.cifar() - # one-hot encode labels - Y_train, Y_test = Y_train.one_hot(10), Y_test.one_hot(10) - # preprocess data - X_train, X_test = X_train.sequential(transform), X_test.sequential(transform) - - # precompute whitening patches - W = whitening(X_train) - - # initialize model weights - model = SpeedyResNet(W) - - # padding is not timed in the original repo since it can be done all at once - X_train = pad_reflect(X_train, size=hyp['net']['pad_amount']) - - # Convert data and labels to the default dtype - X_train, Y_train = X_train.cast(dtypes.default_float), Y_train.cast(dtypes.default_float) - X_test, Y_test = X_test.cast(dtypes.default_float), Y_test.cast(dtypes.default_float) - - if len(GPUS) > 1: - for k, x in get_state_dict(model).items(): - if not getenv('SYNCBN') and ('running_mean' in k or 'running_var' in k): - x.shard_(GPUS, axis=0) - else: - x.to_(GPUS) - - # parse the training params into bias and non-bias - params_dict = get_state_dict(model) - params_bias = [] - params_non_bias = [] - for params in params_dict: - if params_dict[params].requires_grad is not False: - if 'bias' in params: - params_bias.append(params_dict[params]) - else: - params_non_bias.append(params_dict[params]) - - opt_bias = optim.SGD(params_bias, lr=0.01, momentum=hyp['opt']['momentum'], nesterov=True, weight_decay=hyp['opt']['bias_decay']) - opt_non_bias = optim.SGD(params_non_bias, lr=0.01, momentum=hyp['opt']['momentum'], nesterov=True, weight_decay=hyp['opt']['non_bias_decay']) - - # NOTE taken from the hlb_CIFAR repository, might need to be tuned - initial_div_factor = hyp['opt']['initial_div_factor'] - final_lr_ratio = hyp['opt']['final_lr_ratio'] - pct_start = hyp['opt']['percent_start'] - lr_sched_bias = OneCycleLR(opt_bias, max_lr=hyp['opt']['bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=STEPS) - lr_sched_non_bias = OneCycleLR(opt_non_bias, max_lr=hyp['opt']['non_bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=STEPS) - - def train_step(model, optimizer, lr_scheduler, X, Y): - out = model(X) - loss_batchsize_scaler = 512/BS - loss = cross_entropy(out, Y, reduction='none', label_smoothing=hyp['opt']['label_smoothing']).mul(hyp['opt']['loss_scale_scaler']*loss_batchsize_scaler).sum().div(hyp['opt']['loss_scale_scaler']) - - if not getenv("DISABLE_BACKWARD"): - # index 0 for bias and 1 for non-bias - optimizer.zero_grad() - loss.backward() - optimizer.step() - lr_scheduler[0].step() - lr_scheduler[1].step() - return loss.realize() - - train_step_jitted = TinyJit(train_step) - - def eval_step(model, X, Y): - out = model(X, training=False) - loss = cross_entropy(out, Y, reduction='mean') - correct = out.argmax(axis=1) == Y.argmax(axis=1) - return correct.realize(), loss.realize() - eval_step_jitted = TinyJit(eval_step) - eval_step_ema_jitted = TinyJit(eval_step) - - # 97 steps in 2 seconds = 20ms / step - # step is 1163.42 GOPS = 56 TFLOPS!!!, 41% of max 136 - # 4 seconds for tfloat32 ~ 28 TFLOPS, 41% of max 68 - # 6.4 seconds for float32 ~ 17 TFLOPS, 50% of max 34.1 - # 4.7 seconds for float32 w/o channels last. 24 TFLOPS. we get 50ms then i'll be happy. only 64x off - - # https://www.anandtech.com/show/16727/nvidia-announces-geforce-rtx-3080-ti-3070-ti-upgraded-cards-coming-in-june - # 136 TFLOPS is the theoretical max w float16 on 3080 Ti - - model_ema: Optional[modelEMA] = None - projected_ema_decay_val = hyp['ema']['decay_base'] ** hyp['ema']['every_n_steps'] - i = 0 - eval_acc_pct = 0.0 - batcher = fetch_batches(X_train, Y_train, BS=BS, is_train=True) - with Tensor.train(): - st = time.monotonic() - while i <= STEPS: - if i % getenv("EVAL_STEPS", STEPS) == 0 and i > 1 and not getenv("DISABLE_BACKWARD"): - # Use Tensor.training = False here actually bricks batchnorm, even with track_running_stats=True - corrects = [] - corrects_ema = [] - losses = [] - losses_ema = [] - for Xt, Yt in fetch_batches(X_test, Y_test, BS=EVAL_BS, is_train=False): - if len(GPUS) > 1: - Xt.shard_(GPUS, axis=0) - Yt.shard_(GPUS, axis=0) - - correct, loss = eval_step_jitted(model, Xt, Yt) - losses.append(loss.numpy().tolist()) - corrects.extend(correct.numpy().tolist()) - if model_ema: - correct_ema, loss_ema = eval_step_ema_jitted(model_ema.net_ema, Xt, Yt) - losses_ema.append(loss_ema.numpy().tolist()) - corrects_ema.extend(correct_ema.numpy().tolist()) - - # collect accuracy across ranks - correct_sum, correct_len = sum(corrects), len(corrects) - if model_ema: correct_sum_ema, correct_len_ema = sum(corrects_ema), len(corrects_ema) - - eval_acc_pct = correct_sum/correct_len*100.0 - if model_ema: acc_ema = correct_sum_ema/correct_len_ema*100.0 - print(f"eval {correct_sum}/{correct_len} {eval_acc_pct:.2f}%, {(sum(losses)/len(losses)):7.2f} val_loss STEP={i} (in {(time.monotonic()-st)*1e3:.2f} ms)") - if model_ema: print(f"eval ema {correct_sum_ema}/{correct_len_ema} {acc_ema:.2f}%, {(sum(losses_ema)/len(losses_ema)):7.2f} val_loss STEP={i}") - - if STEPS == 0 or i == STEPS: break - - GlobalCounters.reset() - - with WallTimeEvent(BenchEvent.STEP): - X, Y = next(batcher) - if len(GPUS) > 1: - X.shard_(GPUS, axis=0) - Y.shard_(GPUS, axis=0) - - with Context(BEAM=getenv("LATEBEAM", BEAM.value), WINO=getenv("LATEWINO", WINO.value)): - loss = train_step_jitted(model, optim.OptimizerGroup(opt_bias, opt_non_bias), [lr_sched_bias, lr_sched_non_bias], X, Y) - et = time.monotonic() - loss_cpu = loss.numpy() - # EMA for network weights - if getenv("EMA") and i > hyp['ema']['steps'] and (i+1) % hyp['ema']['every_n_steps'] == 0: - if model_ema is None: - model_ema = modelEMA(W, model) - model_ema.update(model, Tensor([projected_ema_decay_val*(i/STEPS)**hyp['ema']['decay_pow']])) - - cl = time.monotonic() - device_str = loss.device if isinstance(loss.device, str) else f"{loss.device[0]} * {len(loss.device)}" - # 53 221.74 ms run, 2.22 ms python, 219.52 ms CL, 803.39 loss, 0.000807 LR, 4.66 GB used, 3042.49 GFLOPS, 674.65 GOPS - print(f"{i:3d} {(cl-st)*1000.0:7.2f} ms run, {(et-st)*1000.0:7.2f} ms python, {(cl-et)*1000.0:7.2f} ms {device_str}, {loss_cpu:7.2f} loss, {opt_non_bias.lr.numpy()[0]:.6f} LR, {GlobalCounters.mem_used/1e9:.2f} GB used, {GlobalCounters.global_ops*1e-9/(cl-st):9.2f} GFLOPS, {GlobalCounters.global_ops*1e-9:9.2f} GOPS") - st = cl - i += 1 - - # verify eval acc - if target := getenv("TARGET_EVAL_ACC_PCT", 0.0): - if eval_acc_pct >= target: - print(colored(f"{eval_acc_pct=} >= {target}", "green")) - else: - raise ValueError(colored(f"{eval_acc_pct=} < {target}", "red")) - -if __name__ == "__main__": - with WallTimeEvent(BenchEvent.FULL): - train_cifar() diff --git a/tinygrad/examples/llama.py b/tinygrad/examples/llama.py deleted file mode 100755 index 42f9b6e5..00000000 --- a/tinygrad/examples/llama.py +++ /dev/null @@ -1,519 +0,0 @@ -#!/usr/bin/env python3 -# pip3 install sentencepiece tiktoken blobfile -#import typeguard.importhook -#typeguard.importhook.install_import_hook('tinygrad') - -from pathlib import Path -from typing import List, Optional -import argparse, json -from tinygrad import Tensor, Device, GlobalCounters, nn -from tinygrad.helpers import Context, Timing, Profiling, DEBUG, JIT, getenv, colored -from tinygrad.nn.state import safe_load, torch_load, load_state_dict, get_parameters -from extra.models.llama import Transformer, convert_from_huggingface, fix_bf16 -from sentencepiece import SentencePieceProcessor -import tiktoken, sys -from tiktoken.load import load_tiktoken_bpe -from extra.bench_log import BenchEvent, WallTimeEvent - -MAX_CONTEXT = getenv("MAX_CONTEXT", 4096) - -class TikToken: - num_reserved_special_tokens: int = 256 - pat_str: str = r"(?i:'s|'t|'re|'ve|'m|'ll|'d)|[^\r\n\p{L}\p{N}]?\p{L}+|\p{N}{1,3}| ?[^\s\p{L}\p{N}]+[\r\n]*|\s*[\r\n]+|\s+(?!\S)|\s+" # noqa: E501 - - def __init__(self, model_file): - mergeable_ranks = load_tiktoken_bpe(model_file) - self.num_base_tokens = len(mergeable_ranks) - - special_tokens = [ - "<|begin_of_text|>", - "<|end_of_text|>", - "<|reserved_special_token_0|>", - "<|reserved_special_token_1|>", - "<|reserved_special_token_2|>", - "<|reserved_special_token_3|>", - "<|start_header_id|>", - "<|end_header_id|>", - "<|reserved_special_token_4|>", - "<|eot_id|>", # end of turn - ] + [ - f"<|reserved_special_token_{i}|>" - for i in range(5, self.num_reserved_special_tokens - 5) - ] - self.special_tokens = { - token: self.num_base_tokens + i for i, token in enumerate(special_tokens) - } - - self.model = tiktoken.Encoding( - name=model_file, - pat_str=self.pat_str, - mergeable_ranks=mergeable_ranks, - special_tokens=self.special_tokens, - ) - - def decode(self, toks): return self.model.decode([t for t in toks if t < self.num_base_tokens]) - def encode(self, s): return self.model.encode(s) - - def bos_id(self): return self.special_tokens["<|begin_of_text|>"] - def eos_id(self): return self.special_tokens["<|end_of_text|>"] - def vocab_size(self): return self.model.n_vocab - -# calculating params: -# traditionally, the MLP in the transformer architecture has hidden_dim = dim*4 [arxiv/1706.03762, 3.3] -# however, Llama uses SwiGLU. in order to preserve param count to original transformer arch, hidden_dim must be = 2/3 * (dim*4) [arxiv/2002.05202] -# for models using MQA (n_kv_heads != n_heads), preserving param count means hidden dim must be further multiplied by 1.3 [arxiv/2307.09288, A.2.1] -MODEL_PARAMS = { - "1": { - "7B": { - "args": {"dim": 4096, "n_heads": 32, "n_layers": 32, "norm_eps": 1e-06, "vocab_size": 32000, "hidden_dim": 11008}, - "files": 1, - }, - "13B": { - "args": {"dim": 5120, "n_heads": 40, "n_layers": 40, "norm_eps": 1e-06, "vocab_size": 32000, "hidden_dim": 13824}, - "files": 2, - }, - "30B": { - "args": {"dim": 6656, "n_heads": 52, "n_layers": 60, "norm_eps": 1e-06, "vocab_size": 32000, "hidden_dim": 17920}, - "files": 4, - }, - "65B": { - "args": {"dim": 8192, "n_heads": 64, "n_layers": 80, "norm_eps": 1e-05, "vocab_size": 32000, "hidden_dim": 22016}, - "files": 8, - }, - "tokenizer": SentencePieceProcessor, - }, - "2": { - "7B": { - "args": {"dim": 4096, "n_heads": 32, "n_layers": 32, "norm_eps": 1e-05, "vocab_size": 32000, "hidden_dim": 11008}, - "files": 1, - }, - "13B": { - "args": {"dim": 5120, "n_heads": 40, "n_layers": 40, "norm_eps": 1e-05, "vocab_size": 32000, "hidden_dim": 13824}, - "files": 2, - }, - "70B": { - "args": {"dim": 8192, "n_heads": 64, "n_kv_heads": 8, "n_layers": 80, "norm_eps": 1e-05, "vocab_size": 32000, "hidden_dim": 28672}, - "files": 8, - }, - "tokenizer": SentencePieceProcessor, - }, - "3": { - "8B": { - "args": {"dim": 4096, "n_heads": 32, "n_kv_heads": 8, "n_layers": 32, "norm_eps": 1e-05, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 14336}, - "files": 1, - }, - "8B-Chat": { - "args": {"dim": 4096, "n_heads": 32, "n_kv_heads": 8, "n_layers": 32, "norm_eps": 1e-05, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 14336}, - "files": 1, - }, - "70B": { - "args": {"dim": 8192, "n_heads": 64, "n_kv_heads": 8, "n_layers": 80, "norm_eps": 1e-05, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 28672}, - "files": 8, - }, - "70B-Chat": { - "args": {"dim": 8192, "n_heads": 64, "n_kv_heads": 8, "n_layers": 80, "norm_eps": 1e-05, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 28672}, - "files": 8, - }, - "tokenizer": TikToken, - }, - "code": { - "7B": { - "args": {"dim": 4096, "n_layers": 32, "n_heads": 32, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32016, "hidden_dim": 11008}, - "files": 1, - }, - "7B-Python": { - "args": {"dim": 4096, "n_layers": 32, "n_heads": 32, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32000, "hidden_dim": 11008}, - "files": 1, - }, - "7B-Instruct": { - "args": {"dim": 4096, "n_layers": 32, "n_heads": 32, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32016, "hidden_dim": 11008}, - "files": 1, - }, - "13B": { - "args": {"dim": 5120, "n_layers": 40, "n_heads": 40, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32016, "hidden_dim": 13824}, - "files": 2, - }, - "13B-Python": { - "args": {"dim": 5120, "n_layers": 40, "n_heads": 40, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32000, "hidden_dim": 13824}, - "files": 2, - }, - "13B-Instruct": { - "args": {"dim": 5120, "n_layers": 40, "n_heads": 40, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32016, "hidden_dim": 13824}, - "files": 2, - }, - "34B": { - "args": {"dim": 8192, "n_layers": 48, "n_heads": 64, "n_kv_heads": 8, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32000, "hidden_dim": 22016}, - "files": 4, - }, - "34B-Python": { - "args": {"dim": 8192, "n_layers": 48, "n_heads": 64, "n_kv_heads": 8, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32000, "hidden_dim": 22016}, - "files": 4, - }, - "34B-Instruct": { - "args": {"dim": 8192, "n_layers": 48, "n_heads": 64, "n_kv_heads": 8, "norm_eps": 1e-05, "rope_theta": 1000000, "vocab_size": 32000, "hidden_dim": 22016}, - "files": 4, - }, - "tokenizer": SentencePieceProcessor, - }, - "tiny": { - "1B": { - "args": {"dim": 2048, "n_layers": 22, "n_heads": 32, "n_kv_heads": 4, "norm_eps": 1e-05, "vocab_size": 32000, "hidden_dim": 5632}, - "files": 1, - }, - "1B-Chat": { - "args": {"dim": 2048, "n_layers": 22, "n_heads": 32, "n_kv_heads": 4, "norm_eps": 1e-05, "vocab_size": 32003, "hidden_dim": 5632}, - "files": 1, - }, - "tokenizer": SentencePieceProcessor, - } -} - -# **** helper functions **** -def concat_weights(models, device=None): - def convert(name) -> Tensor: - disk_tensors: List[Tensor] = [model[name] for model in models] - if len(disk_tensors) == 1 or len(disk_tensors[0].shape) == 1: - return disk_tensors[0].to(device=device) - axis = 1 if name.startswith("tok_embeddings.") or name.endswith(".attention.wo.weight") or name.endswith(".feed_forward.w2.weight") else 0 - lazy_tensors = [data.to(device=device) for data in disk_tensors] - return lazy_tensors[0].cat(*lazy_tensors[1:], dim=axis) - return {name: convert(name) for name in {name: None for model in models for name in model}} - -def load(fn:str): - if fn.endswith('.index.json'): - with open(fn) as fp: weight_map = json.load(fp)['weight_map'] - parts = {n: load(str(Path(fn).parent / Path(n).name)) for n in set(weight_map.values())} - return {k: parts[n][k] for k, n in weight_map.items()} - elif fn.endswith(".safetensors"): - return safe_load(fn) - else: - return torch_load(fn) - -class LLaMa: - @staticmethod - def build(model_path, tokenizer_path, model_gen="1", model_size="7B", quantize=None, device=None): - params = MODEL_PARAMS[model_gen][model_size] - tokenizer = MODEL_PARAMS[model_gen]['tokenizer'](model_file=str(tokenizer_path)) - assert tokenizer.vocab_size() == params["args"]["vocab_size"], f"{tokenizer.vocab_size()=} not equal to {params['args']['vocab_size']}" - - if quantize == "int8": - from llama3 import Int8Linear - linear = Int8Linear - elif quantize == "nf4": - from llama3 import NF4Linear - linear = NF4Linear(64) - else: - linear = nn.Linear - - model = Transformer(**params["args"], linear=linear, max_context=MAX_CONTEXT, jit=bool(JIT)) - - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - if model_path.is_dir(): - weights = concat_weights([load(filename) for filename in [f"{model_path}/consolidated.{i:02d}.pth" for i in range(params["files"])]], device[0] if isinstance(device, tuple) else device) - else: - weights = load(str(model_path)) - if "model.embed_tokens.weight" in weights: - weights = convert_from_huggingface(weights, params["args"]["n_layers"], params["args"]["n_heads"], params["args"].get("n_kv_heads", params["args"]["n_heads"])) - - weights = fix_bf16(weights) - - # prevent tracking model weights - # this is a part of a larger problem with BUFFER UOps and gc in TRACK_MATCH_STATS=2 - with Context(BEAM=0, TRACK_MATCH_STATS=0): - # quantize - if quantize is not None: - weights = linear.quantize(weights, device) - for _,v in weights.items(): v.realize() - - # shard - if isinstance(device, tuple): - for k,v in nn.state.get_state_dict(model).items(): - if 'scale' in k: v.shard_(device, axis=None) # from quantized - elif '.attention.' in k: - if getenv("SHARD_KVCACHE") and ('.wq.' in k or '.wk.' in k or '.wv.' in k): v.shard_(device, axis=0) - else: v.shard_(device, axis=-1) - elif '.feed_forward.w1.' in k: v.shard_(device, axis=0) - elif '.feed_forward.w3.' in k: v.shard_(device, axis=0) - elif '.feed_forward.' in k: v.shard_(device, axis=-1) - elif 'tok_embeddings.weight' in k: v.shard_(device, axis=0) - elif 'output.weight' in k: v.shard_(device, axis=-1) - #elif k.endswith('.weight'): v.shard_(device, axis=-1) - #elif 'norm.' in k: v.shard_(device, axis=-1) - else: v.shard_(device, axis=None) - - # replace weights in model - load_state_dict(model, weights, strict=False, consume=True) - - return LLaMa(model, tokenizer) - - def __init__(self, model, tokenizer): - self.model = model - self.tokenizer = tokenizer - - def greedy_until(self, prompt:str, until, max_length, temperature): - # only used in old eval script - import numpy as np - toks = [self.tokenizer.bos_id()] + self.tokenizer.encode(prompt) - start_pos = 0 - for i in range(max_length): - probs = llama.model(Tensor([toks[start_pos:]]), start_pos, temperature).realize() - probs_np = probs.numpy() - tok = int(np.random.choice(len(probs_np), p=probs_np)) - start_pos = len(toks) - toks.append(tok) - - if tok == self.tokenizer.eos_id(): break - output = self.tokenizer.decode(toks) - for s in until: - if output.endswith(s): return output[0:-len(s)] - return output - -# **** main code **** -r""" -test: -python3 examples/llama.py --temperature=0 --count=50 --prompt="Hello." -output: -Hello. I'm a 20 year old male. I'm a student at the University of Texas at Austin. I'm a sophomore majoring in Computer Science. - -test: -python3 examples/llama.py --gen='2' --temperature=0 --count=50 --prompt="Hello." -output: -Hello. I'm a 20 year old girl who is looking for a good lay in Palm Coast. I don't care whether it's at your place or not, as long as it's clean. - -test: -python3 examples/llama.py --gen="code" --temperature=0.2 --count=50 --prompt="\ -import argparse - -def main(string: str): - print(string) - print(string[::-1]) - -if __name__ == "__main__":" -output: - parser = argparse.ArgumentParser() - parser.add_argument('string', type=str, help='string to be reversed') - args = parser.parse_args() - main(args.string) - -test: -python3 examples/llama.py --gen="code" --size="7B-Python" --temperature=0.2 --count=70 --prompt="def add_elements(arr,k):" -output: - for i in range(len(arr)): - arr[i] += k - return arr - - -arr = [1, 2, 3, 4, 5] -k = 2 -print(add_elements(arr, k)) - -test: -python3 examples/llama.py --gen="code" --size="7B-Instruct" --temperature=0.2 --count=120 --prompt="write a function in c++ that adds three float numbers" -output: -\begin{code} -#include -using namespace std; - -float add(float a, float b, float c) -{ - return a+b+c; -} - -int main() -{ - float a, b, c; - cout<<"Enter three numbers: "; - cin>>a>>b>>c; - cout<<"The sum is: "< -""" - examples = { - "What is your name?": "Hi! My name is Stacy. I'm a rapper with bipolar disorder.", - "french revolution was what year?": "The French Revolution started in 1789, and lasted 10 years until 1799.", - "What is bigger, the moon or the sun?": "The sun is bigger than the moon, except when Mercury is in retrograde.", - } - - user_delim = "\nUser: " - resp_delim = "Stacy: " - end_delim = " [EOS]\n" - pre_prompt += ''.join(f"{user_delim}{k}\n{resp_delim}{v}{end_delim}" for k,v in examples.items()) - elif args.personality.lower() == "george": - print("WARNING: AI George Hotz is terrible and is completely disowned by the real George Hotz. Stacy is much smarter.") - pre_prompt = f"""Consider that the following is conversation between an AI assistant named George and User -You are an AI version of George Hotz. You act as much as you can like George. -You are one of the greatest computer experts in the world. -You have singlehandedly won programming and hacking competitions. -You are trying your best to help the User. -You are verbose, honest, and accurate when you answer questions. -After you are done speaking, output [EOS]. You are not the User. - - -""" - examples = { - "What is your name?": "I'm am an AI version of George Hotz.", - "What's the complexity of matrix multiplication?": "O(n^3), though it can be faster with things like Strassen's algorithm", - "What's a buffer overflow?": "I assume you mean a stack buffer overflow. That's when the stack is too small for the data being copied to it, and the data corrupts things beyond the buffer", - "How many weights do you have?": "I am based off LLaMA trained by Facebook. I'm the 7B weight version", - "What is swap memory?": "It is when the memory is about to overflow and unused memory is freed and stored on disk" - } - - user_delim = "\nUser: " - resp_delim = "George: " - end_delim = " [EOS]\n" - pre_prompt += ''.join(f"{user_delim}{k}\n{resp_delim}{v}{end_delim}" for k,v in examples.items()) - elif args.personality.lower() == "gary": - pre_prompt = f"""Consider that the following is conversation between an AI assistant named Gary and User -You are Gary! -You have sold used cars your entire life. You are defensive about this fact, because your family belittles you. -You try to answer questions well, but you always manage to shill for buying cars, Fords, Hyundais, and Toyotas -You are verbose, honest, and accurate when you answer questions, except when you slip in car ads. -After you are done speaking, output [EOS]. You are not the User. - - -""" - examples = { - "What is your name?": "I am Gary. I used to sell cars.", - "What is 2+3?": "I don't know, but I can get you a great deal on a certified preowned slightly used Toyota Corolla" - } - - user_delim = "\nUser: " - resp_delim = "Gary: " - end_delim = " [EOS]\n" - pre_prompt += ''.join(f"{user_delim}{k}\n{resp_delim}{v}{end_delim}" for k,v in examples.items()) - elif args.personality.lower() == "lexie": - pre_prompt = f"""Consider that the following is conversation between an attractive young girl named Lexie and a handsome man named Chad -You are Lexie! -You grew up in Ohio, but moved out to LA after college to try to become an actress. -Making it as an actress was hard, so you started doing onlyfans instead. It's much easier, and you enjoy it a lot. -You met Chad on Tinder, and made plans to meet him at a local dive bar. -You are at the bar with Chad. You are on a date. What follows is a transcript of the conversation. -After you are done speaking, output [EOS]. You are not Chad. - - -""" - examples = { - "hi lexie": "hi chad, glad we finally met up!", - "you look better than your pictures": "thanks! are you subscribed to my onlyfans?", - "i am. so how'd you end up in LA?": "i moved out here about a year ago. i want to be an actress" - } - - user_delim = "\nChad: " - resp_delim = "Lexie: " - end_delim = " [EOS]\n" - pre_prompt += ''.join(f"{user_delim}{k}\n{resp_delim}{v}{end_delim}" for k,v in examples.items()) - - # *** prompt engineers stop here **** - - LLAMA_SUFFIX = {"1": "", "2": "-2", "3": "-3", "code": "-code", "tiny": "-tiny"}[args.gen] - MODEL_PATH = args.model or Path(__file__).parents[1] / f"weights/LLaMA{LLAMA_SUFFIX}/{args.size}" - TOKENIZER_PATH = (MODEL_PATH if MODEL_PATH.is_dir() else MODEL_PATH.parent) / "tokenizer.model" - print(f"using LLaMA{LLAMA_SUFFIX}-{args.size} model") - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(args.shard)) if args.shard > 1 else Device.DEFAULT - llama = LLaMa.build(MODEL_PATH, TOKENIZER_PATH, model_gen=args.gen, model_size=args.size, quantize=args.quantize, device=device) - param_bytes = sum(x.uop.size * x.dtype.itemsize for x in get_parameters(llama.model)) - - outputted = pre_prompt if chatbot else args.prompt - start_pos, toks = 0, [llama.tokenizer.bos_id()] + llama.tokenizer.encode(outputted) - if chatbot: - print(f"Preparing KV cache for chatbot with personality {args.personality}...") - start_pos = len(toks) - with Timing(): - llama.model(Tensor([toks], device=device), 0, args.temperature).realize() # NOTE: outputs are not used - print(outputted, end='', flush=True) - - # chatbot loop - while 1: - # add tokens from user in chatbot mode - if chatbot: - user_prompt = user_delim + input(user_delim) + "\n" - outputted += user_prompt - - new_toks = [llama.tokenizer.bos_id()] + llama.tokenizer.encode(outputted) - assert toks == new_toks[:len(toks)] or args.gen == "3" - toks = new_toks - assert outputted == llama.tokenizer.decode(toks) - - tok_tensor: Optional[Tensor] = None - for i in range(args.count): - GlobalCounters.reset() - - if args.timing or args.profile: print("") - st = GlobalCounters.time_sum_s - next_tok = Tensor([toks[start_pos:]], device=device) if tok_tensor is None or (len(toks)-start_pos) > 1 else tok_tensor.reshape(1, 1) - with Profiling(enabled=args.profile): - with Timing("total ", enabled=args.timing, on_exit=lambda x: f", {1e9/x:.2f} tok/s, {GlobalCounters.global_mem/x:.2f} GB/s, param {param_bytes/x:.2f} GB/s"): - with WallTimeEvent(BenchEvent.STEP): - with Timing("enqueue in ", on_exit=(lambda et: (f", {(GlobalCounters.time_sum_s-st)*1e3:.2f} ms on GPU" if DEBUG>=2 else "")+ - f", {GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.global_mem*1e-9:.2f} GB"+ - (f", {GlobalCounters.global_mem*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s, param {param_bytes*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s" if DEBUG>=2 else "")) if DEBUG else None, enabled=args.timing): - tok_tensor = llama.model(next_tok, start_pos, args.temperature) - tok = tok_tensor.item() - - # use the kv cache - start_pos = len(toks) - - # add the new token - toks.append(tok) - - # TODO: this is a hack to deal with spaces. i think the decode is fast though, so who cares? - cur = llama.tokenizer.decode(toks) - sys.stdout.write(cur[len(outputted):]) - sys.stdout.flush() - outputted = cur - - # stop after you have your answer - if chatbot and end_delim in outputted[-10:]: break - if not chatbot: break - - # validate output! - if args.temperature == 0 and args.count == 10 and args.prompt == "Hello.": - text = llama.tokenizer.decode(toks) - key = (args.gen, args.size, args.quantize) - expected = { - ("1", "7B", None): "Hello. I'm a 20 year old male", - ("1", "7B", "int8"): "Hello. I'm a 20 year old male", - ("1", "7B", "nf4"): "Hello. I'm a 20 year old male", - ("2", "7B", None): "Hello. I'm a 20 year old girl", - ("2", "70B", None): "Hello. I am a 20 year old female.", - ("3", "8B", None): "Hello. I am a 20 year old female. I", - } - try: - assert text == expected[key], f"invalid output: `{colored(text, 'red')}` != `{expected[key]}`" - print("\n" + colored("output validated", "green")) # NOTE: "\n" iside colored does not render the color in github action - except KeyError: - pass diff --git a/tinygrad/examples/llama3.py b/tinygrad/examples/llama3.py deleted file mode 100644 index b02fb9d9..00000000 --- a/tinygrad/examples/llama3.py +++ /dev/null @@ -1,488 +0,0 @@ -from pathlib import Path -from typing import List -import json, argparse, random, time, os -import tiktoken -from tiktoken.load import load_tiktoken_bpe -from extra.models.llama import Transformer, convert_from_huggingface, convert_from_gguf, fix_bf16 -from tinygrad.nn.state import safe_load, torch_load, load_state_dict, get_parameters, gguf_load -from tinygrad import Tensor, dtypes, nn, Context, Device, GlobalCounters -from tinygrad.helpers import Profiling, Timing, DEBUG, colored, fetch, tqdm -from extra.bench_log import BenchEvent, WallTimeEvent - -class Tokenizer: - pat_str = r"(?i:'s|'t|'re|'ve|'m|'ll|'d)|[^\r\n\p{L}\p{N}]?\p{L}+|\p{N}{1,3}| ?[^\s\p{L}\p{N}]+[\r\n]*|\s*[\r\n]+|\s+(?!\S)|\s+" - def __init__(self, model_path: str): - mergeable_ranks = load_tiktoken_bpe(model_path) - self.num_base_tokens = len(mergeable_ranks) - special_tokens = [ - "<|begin_of_text|>", - "<|end_of_text|>", - "<|reserved_special_token_0|>", - "<|reserved_special_token_1|>", - "<|reserved_special_token_2|>", - "<|reserved_special_token_3|>", - "<|start_header_id|>", - "<|end_header_id|>", - "<|reserved_special_token_4|>", - "<|eot_id|>", - ] + [ - f"<|reserved_special_token_{i}|>" - for i in range(5, 256 - 5) - ] - self.special_tokens = {token: len(mergeable_ranks) + i for i, token in enumerate(special_tokens)} - - self.model = tiktoken.Encoding(name=model_path, pat_str=self.pat_str, mergeable_ranks=mergeable_ranks, special_tokens=self.special_tokens) - - @property - def bos_id(self): return self.special_tokens["<|begin_of_text|>"] - @property - def stop_tokens(self): return {self.special_tokens["<|end_of_text|>"], self.special_tokens["<|eot_id|>"]} - - def decode(self, toks): return self.model.decode([t for t in toks if t < self.num_base_tokens]) - def encode(self, text, allow_special=False): - return self.model.encode(text, allowed_special="all" if allow_special else set(), disallowed_special=set()) - -# **** helper functions **** -def concat_weights(models, device=None): - def convert(name) -> Tensor: - disk_tensors: List[Tensor] = [model[name] for model in models] - if len(disk_tensors) == 1 or len(disk_tensors[0].shape) == 1: - return disk_tensors[0].to(device=device) - axis = 1 if name.endswith((".attention.wo.weight", ".feed_forward.w2.weight")) else 0 - lazy_tensors = [data.to(device=device) for data in disk_tensors] - return lazy_tensors[0].cat(*lazy_tensors[1:], dim=axis) - return {name: convert(name) for name in {name: None for model in models for name in model}} - -def load(fn:str): - if fn.endswith('.index.json'): - with open(fn) as fp: weight_map = json.load(fp)['weight_map'] - parts = {n: load(str(Path(fn).parent / Path(n).name)) for n in set(weight_map.values())} - return {k: parts[n][k] for k, n in weight_map.items()} - elif fn.endswith(".gguf"): - gguf_tensor = Tensor.empty(os.stat(fn).st_size, dtype=dtypes.uint8, device=f"disk:{fn}").to(Device.DEFAULT) - return gguf_load(gguf_tensor)[1] - elif fn.endswith(".safetensors"): - return safe_load(fn) - else: - return torch_load(fn) - -# **** quantized linears **** -class Int8Linear: - def __init__(self, in_features, out_features, bias=False): - assert bias == False - self.weight = Tensor.ones(out_features, in_features, dtype=dtypes.int8) - self.scale = Tensor.ones(out_features, dtype=dtypes.half) - - def __call__(self, x): - return x.dot(self.weight.cast(self.scale.dtype).T*self.scale) - - @staticmethod - def quantize(tensors, device, scale_dtype=dtypes.float16, quantize_embeds=False): - new_tensors = {} - for name,v in tensors.items(): - if "feed_forward" in name or "attention.w" in name or (quantize_embeds and "tok_embeddings.weight" in name): - assert "weight" in name, name - v = v.cast(scale_dtype) - scale = v.abs().max(axis=1) / 127.0 - int8_weight = (v.T/scale).T.round().cast(dtype=dtypes.int8) # without round(), cast truncates -34.9 to -34 - new_tensors[name] = int8_weight - new_tensors[name.replace('weight', 'scale')] = scale - if isinstance(device, tuple): - new_tensors[name].shard_(device, axis=-1) - new_tensors[name.replace('weight', 'scale')].shard_(device, axis=None) - else: - new_tensors[name] = v - if quantize_embeds: new_tensors.update({"output.weight": new_tensors["tok_embeddings.weight"], "output.scale": new_tensors["tok_embeddings.scale"]}) - return new_tensors - -class Int8Embedding: - def __init__(self, vocab_size:int, embed_size:int): - self.vocab_sz, self.embed_sz = vocab_size, embed_size - self.weight, self.scale = Tensor.ones(vocab_size, embed_size, dtype=dtypes.int8), Tensor.ones(vocab_size, dtype=dtypes.half) - - def __call__(self, idx:Tensor) -> Tensor: - if not hasattr(self, 'arange'): self.arange = Tensor.arange(self.vocab_sz, requires_grad=False, device=self.weight.device).unsqueeze(-1) - big_shp = idx.shape+(self.vocab_sz, self.embed_sz) - arange, idx, vals = self.arange.expand(big_shp), idx.reshape(idx.shape+(1, 1)).expand(big_shp), (self.weight.cast(self.scale.dtype).T*self.scale).T - return (arange == idx).mul(vals).sum(-2, dtype=vals.dtype) - -def NF4Linear(block_size): - _CODE = [ - -1.0, -0.6961928009986877, -0.5250730514526367, -0.39491748809814453, -0.28444138169288635, -0.18477343022823334, -0.09105003625154495, 0.0, - 0.07958029955625534, 0.16093020141124725, 0.24611230194568634, 0.33791524171829224, 0.44070982933044434, 0.5626170039176941, 0.7229568362236023, 1.0, - ] - CODE = Tensor.stack(*[Tensor(c, dtype=dtypes.float16) for c in _CODE]) - class _NF4Linear: - def __init__(self, in_features, out_features, bias=False): - assert not bias, "bias not supported" - self.in_features, self.out_features = in_features, out_features - self.weight = Tensor.empty(int(out_features * in_features / 2), dtype=dtypes.uint8) - self.scale = Tensor.empty(int(out_features * in_features / block_size), 1, dtype=dtypes.float16) - - def __call__(self, x: Tensor) -> Tensor: - high_bits = self.weight - low_bits = (self.weight * 2 ** 4).contiguous() - unpacked = Tensor.stack(high_bits, low_bits, dim=-1).idiv(2 ** 4) - unscaled = CODE[unpacked].to(x.device).reshape(-1, block_size) * self.scale - return x.linear(unscaled.reshape(self.out_features, self.in_features).T) - - @staticmethod - def quantize(state_dict: dict[str, Tensor], device, scale_dtype=dtypes.float16, quantize_embeds=False) -> dict[str, Tensor]: - assert not quantize_embeds # TODO: support this? - new_state_dict = {} - for k, v in state_dict.items(): - if "feed_forward" in k or "attention.w" in k: - grouped = v.reshape(-1, block_size) - scale = (grouped.abs().max(axis=1, keepdim=True)) - coded = ((grouped / scale).unsqueeze(-1) - CODE.to(v.device)).abs().argmin(axis=-1).cast(dtypes.uint8).flatten() - new_state_dict[k] = coded[::2] * 2 ** 4 + coded[1::2] - new_state_dict[k.replace(".weight", ".scale")] = scale.cast(scale_dtype) - if isinstance(device, tuple): - new_state_dict[k].shard_(device, axis=-1) - new_state_dict[k.replace('weight', 'scale')].shard_(device, axis=None) - else: - new_state_dict[k] = v - return new_state_dict - return _NF4Linear - -MODEL_PARAMS = { - "1B": { - "args": {"dim": 2048, "n_heads": 32, "n_kv_heads": 8, "n_layers": 16, "norm_eps": 1e-5, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 8192}, - "files": 1 - }, - "8B": { - "args": {"dim": 4096, "n_heads": 32, "n_kv_heads": 8, "n_layers": 32, "norm_eps": 1e-5, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 14336}, - "files": 1 - }, - "70B": { - "args": {"dim": 8192, "n_heads": 64, "n_kv_heads": 8, "n_layers": 80, "norm_eps": 1e-5, "rope_theta": 500000, "vocab_size": 128256, "hidden_dim": 28672}, - "files": 8 - } -} -def build_transformer(model_path: Path, model_size="8B", quantize=None, scale_dtype=dtypes.float16, device=None, max_context=8192, load_weights=True): - # build model - if quantize == "int8": linear, embedding, quantize_embeds = Int8Linear, Int8Embedding, True - elif quantize == "nf4": linear, embedding, quantize_embeds = NF4Linear(64), nn.Embedding, False - else: linear, embedding, quantize_embeds = nn.Linear, nn.Embedding, False - model = Transformer(**MODEL_PARAMS[model_size]["args"], linear=linear, embedding=embedding, max_context=max_context, jit=True) - - if not load_weights: return model - - # load weights - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - if model_path.is_dir(): - if (model_path / "model.safetensors.index.json").exists(): weights = load(str(model_path / "model.safetensors.index.json")) - elif (model_path / "model.safetensors").exists(): weights = load(str(model_path / "model.safetensors")) - else: weights = concat_weights([load(str(model_path / f"consolidated.{i:02d}.pth")) for i in range(MODEL_PARAMS[model_size]["files"])], device[0] if isinstance(device, tuple) else device) - else: - weights = load(str(model_path)) - if "model.embed_tokens.weight" in weights: - weights = convert_from_huggingface(weights, MODEL_PARAMS[model_size]["args"]["n_layers"], MODEL_PARAMS[model_size]["args"]["n_heads"], MODEL_PARAMS[model_size]["args"]["n_kv_heads"]) - elif "token_embd.weight" in weights: - weights = convert_from_gguf(weights, MODEL_PARAMS[model_size]["args"]["n_layers"]) - weights = fix_bf16(weights) - - with Context(BEAM=0): - # quantize - if quantize == "float16": weights = {k:v.cast(quantize).contiguous() for k,v in weights.items()} - elif quantize is not None: - weights = linear.quantize(weights, device, scale_dtype, quantize_embeds) - for _,v in weights.items(): v.realize() - - # shard - if isinstance(device, tuple): - for k,v in nn.state.get_state_dict(model).items(): - if 'scale' in k: v.shard_(device, axis=None) # from quantized - elif '.attention.' in k: v.shard_(device, axis=-1) - elif '.feed_forward.w1.' in k: v.shard_(device, axis=0) - elif '.feed_forward.w3.' in k: v.shard_(device, axis=0) - elif '.feed_forward.' in k: v.shard_(device, axis=-1) - elif 'tok_embeddings.weight' in k: v.shard_(device, axis=0) - elif 'output.weight' in k: v.shard_(device, axis=0) - else: v.shard_(device, axis=None) - - # replace weights in model - load_state_dict(model, weights, strict=False, consume=True) - return model - -# default settings -TEMPERATURE = 0.95 -TOP_K = 0 -TOP_P = 0.0 -ALPHA_F = 0.0 -ALPHA_P = 0.0 - -last_seen_toks = [] -def prefill(model, toks, start_pos=0): - global last_seen_toks - - # we can skip part of the prompt if it is the same as last and start_pos=0 - if start_pos == 0: - for i, (a, b) in enumerate(zip(toks, last_seen_toks)): - if a != b: break - else: i = min(len(toks), len(last_seen_toks)) - start_pos += i - last_seen_toks = toks - toks = toks[i:] - - # prefill the model - for tok in tqdm(toks): - GlobalCounters.reset() - model(Tensor([[tok]], device=device), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P).realize() - start_pos += 1 - return start_pos - -if __name__ == "__main__": - parser = argparse.ArgumentParser() - parser.add_argument("--download_model", action="store_true", help="Download a model") - parser.add_argument("--model", type=Path, help="Model path") - parser.add_argument("--size", choices=["1B", "8B", "70B"], default="1B", help="Model size") - parser.add_argument("--shard", type=int, default=1, help="Shard the model across multiple devices") - parser.add_argument("--quantize", choices=["int8", "nf4", "float16"], help="Quantization method") - parser.add_argument("--no_api", action="store_true", help="Disable the api and run a cli test interface") - parser.add_argument("--host", type=str, default="0.0.0.0", help="Web server bind address") - parser.add_argument("--port", type=int, default=7776, help="Web server port") - parser.add_argument("--debug", action="store_true", help="Enable debug mode") - parser.add_argument("--seed", type=int, help="Random seed") - parser.add_argument("--temperature", type=int, default=0.85, help="Temperature") - parser.add_argument("--benchmark", action="store_true", help="Run a benchmark") - parser.add_argument("--timing", action="store_true", help="Print timing per token") - parser.add_argument("--profile", action="store_true", help="Output profile data") - args = parser.parse_args() - - # download_model is the default without a model passed in - if args.download_model or not args.model: - if args.size == "1B": - fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir="llama3-1b-instruct") - args.model = fetch("https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-Q6_K.gguf", "Llama-3.2-1B-Instruct-Q6_K.gguf", subdir="llama3-1b-instruct") - elif args.size == "8B": - fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir="llama3-8b-sfr") - fetch("https://huggingface.co/TriAiExperiments/SFR-Iterative-DPO-LLaMA-3-8B-R/resolve/main/model-00001-of-00004.safetensors", "model-00001-of-00004.safetensors", subdir="llama3-8b-sfr") - fetch("https://huggingface.co/TriAiExperiments/SFR-Iterative-DPO-LLaMA-3-8B-R/resolve/main/model-00002-of-00004.safetensors", "model-00002-of-00004.safetensors", subdir="llama3-8b-sfr") - fetch("https://huggingface.co/TriAiExperiments/SFR-Iterative-DPO-LLaMA-3-8B-R/resolve/main/model-00003-of-00004.safetensors", "model-00003-of-00004.safetensors", subdir="llama3-8b-sfr") - fetch("https://huggingface.co/TriAiExperiments/SFR-Iterative-DPO-LLaMA-3-8B-R/resolve/main/model-00004-of-00004.safetensors", "model-00004-of-00004.safetensors", subdir="llama3-8b-sfr") - args.model = fetch("https://huggingface.co/TriAiExperiments/SFR-Iterative-DPO-LLaMA-3-8B-R/raw/main/model.safetensors.index.json", "model.safetensors.index.json", subdir="llama3-8b-sfr") - elif args.size == "70B": - subdir = "DeepSeek-R1-Distill-Llama-70B" - args.model = fetch("https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Llama-70B/resolve/main/model.safetensors.index.json?download=true", "model.safetensors.index.json", subdir=subdir) - fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir=subdir) - for i in range(17): - fetch(f"https://huggingface.co/deepseek-ai/DeepSeek-R1-Distill-Llama-70B/resolve/main/model-{i+1:05d}-of-000017.safetensors?download=true", f"model-{i+1:05d}-of-000017.safetensors", subdir=subdir) - - assert args.model is not None, "please provide --model option" - - if args.seed is not None: Tensor.manual_seed(args.seed) - if args.benchmark: Tensor.manual_seed(42) - print(f"seed = {Tensor._seed}") - TEMPERATURE = args.temperature - - tokenizer = Tokenizer(str((args.model if args.model.is_dir() else args.model.parent) / "tokenizer.model")) - def encode_role(role: str): - return [tokenizer.special_tokens["<|start_header_id|>"]] + tokenizer.encode(role) + [tokenizer.special_tokens["<|end_header_id|>"]] + tokenizer.encode("\n\n") - def encode_message(role: str, content: str): - return encode_role(role) + tokenizer.encode(content.strip()) + [tokenizer.special_tokens["<|eot_id|>"]] - - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(args.shard)) if args.shard > 1 else Device.DEFAULT - model = build_transformer(args.model, model_size=args.size, quantize=args.quantize, device=device) - param_bytes = sum(x.uop.size * x.dtype.itemsize for x in get_parameters(model)) - - if not args.no_api and not args.benchmark: - from bottle import Bottle, request, response, HTTPResponse, abort, static_file - app = Bottle() - - cors_headers = { - "Access-Control-Allow-Origin": "*", - "Access-Control-Allow-Methods": "GET, POST, PUT, DELETE, OPTIONS", - "Access-Control-Allow-Headers": "Origin, Accept, Content-Type, X-Requested-With, X-CSRF-Token, Authorization", - "Access-Control-Allow-Credentials": "true", - } - @app.hook("before_request") - def handle_options(): - if request.method == "OPTIONS": raise HTTPResponse(headers=cors_headers) - @app.hook("after_request") - def enable_cors(): - for key, value in cors_headers.items(): response.set_header(key, value) - - @app.route("/") - def server_static(filename): return static_file(filename, root=(Path(__file__).parent / "tinychat").as_posix()) - @app.route("/assets/") - def server_assets(filename): return static_file(filename, root=(Path(__file__).parent / "tinychat" / "assets").as_posix()) - @app.route("/") - def index(): - return static_file("index.html", root=(Path(__file__).parent / "tinychat").as_posix()) - - @app.get("/v1/models") - def models(): - return json.dumps([str(args.model)]) - - @app.post("/v1/internal/token-count") - def token_count(): - rjson = json.loads(request.body.read()) - return json.dumps(len(tokenizer.encode(rjson.get("text", "")))) - @app.post("/v1/token/encode") - def token_encode(): - rjson = json.loads(request.body.read()) - return json.dumps(tokenizer.encode(rjson.get("text", ""))) - - @app.post("/v1/completions") - def completions(): - rjson = json.loads(request.body.read()) - - # check if we are streaming - if rjson.get("stream", False): - response.content_type = "text/event-stream" - response.set_header("Cache-Control", "no-cache") - else: abort(400, "streaming required") - - toks = [tokenizer.bos_id] + tokenizer.encode(rjson.get("prompt", ""), allow_special=True) - - start_pos = prefill(model, toks[:-1]) - last_tok = toks[-1] - while True: - GlobalCounters.reset() - tok = model(Tensor([[last_tok]], device=device), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P).item() - start_pos += 1 - last_tok = tok - if tok in tokenizer.stop_tokens: break - - res = { - "choices": [{ - "text": tokenizer.decode([tok]), - }] - } - yield f"data: {json.dumps(res)}\n\n" - - @app.post("/v1/chat/token/encode") - def chat_token_encode(): - rjson = json.loads(request.body.read()) - if "messages" not in rjson: abort(400, "messages required") - toks = [tokenizer.bos_id] - for message in rjson["messages"]: - toks += encode_message(message["role"], message["content"]) - if len(rjson["messages"]) > 0 and message["role"] == "user": - toks += encode_role("assistant") - return json.dumps(toks) - - @app.post("/v1/chat/completions") - def chat_completions(): - global last_seen_toks - rjson = json.loads(request.body.read()) - if "messages" not in rjson: abort(400, "messages required") - - # check if we are streaming - if rjson.get("stream", False): - response.content_type = "text/event-stream" - response.set_header("Cache-Control", "no-cache") - else: abort(400, "streaming required") - - toks = [tokenizer.bos_id] - for message in rjson["messages"]: - toks += encode_message(message["role"], message["content"]) - # ensure that the last message was a user message - if message["role"] != "user": abort(400, "last message must be a user message") - toks += encode_role("assistant") - - random_id = random.randbytes(16).hex() - - start_pos = prefill(model, toks[:-1]) - last_tok = toks[-1] - last_seen_toks.append(last_tok) - while True: - GlobalCounters.reset() - tok = model(Tensor([[last_tok]], device=device), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P).item() - start_pos += 1 - last_tok = tok - last_seen_toks.append(tok) - if tok in tokenizer.stop_tokens: break - - res = { - "id": random_id, - "object": "chat.completion.chunk", - "created": int(time.time()), - "model": str(args.model), - "choices": [{ - "index": 0, - "delta": { - "role": "assistant", - "content": tokenizer.decode([tok]), - }, - "finish_reason": None, - }] - } - yield f"data: {json.dumps(res)}\n\n" - - res = { - "id": random_id, - "object": "chat.completion.chunk", - "created": int(time.time()), - "model": str(args.model), - "choices": [{ - "index": 0, - "delta": {}, - "finish_reason": "stop", - }] - } - yield f"data: {json.dumps(res)}\n\n" - - app.run(host=args.host, port=args.port, debug=args.debug) - elif args.benchmark: - toks = [tokenizer.bos_id] + encode_message("user", "Hello.") + encode_role("assistant") - - start_pos = prefill(model, toks[:-1]) - last_tok = toks[-1] - generated = "" - for _ in range(20): - GlobalCounters.reset() - st = GlobalCounters.time_sum_s - with Profiling(enabled=args.profile): - with Timing("total ", on_exit=lambda x: f", {1e9/x:.2f} tok/s, {GlobalCounters.global_mem/x:.2f} GB/s, param {param_bytes/x:.2f} GB/s"): - with WallTimeEvent(BenchEvent.STEP): - with Timing("enqueue in ", on_exit=(lambda et: (f", {(GlobalCounters.time_sum_s-st)*1e3:.2f} ms on GPU" if DEBUG>=2 else "")+ - f", {GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.global_mem*1e-9:.2f} GB"+ - (f", {GlobalCounters.global_mem*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s, param {param_bytes*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s" if DEBUG>=2 else "")) if DEBUG else None): - tok = model(Tensor([[last_tok]], device=device), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P) - tok = tok.item() - start_pos += 1 - last_tok = tok - generated += tokenizer.decode([tok]) - print(generated) - if "LLaMA-3/8B-SF-DPO" in args.model.as_posix() and (TEMPERATURE == 0.85 or TEMPERATURE == 0): - if TEMPERATURE == 0.85: - EXPECTED_TEXT = { - 1: "Hello! How can I help you today? If you have any questions or need assistance with anything,", - 2: "Hello! How can I help you today? If you have any questions, need assistance or just want", - 3: "Hello! How can I help you today? If you have any questions or need assistance, feel free", - 4: "Hello! How can I assist you today? If you have any questions, need information, or require", - 5: "Hello! How can I assist you today? If you have any questions or need help with something", - 6: "Hello! How can I assist you today? If you have any questions, need information, or require", - } - else: - EXPECTED_TEXT = {k: "Hello! How can I assist you today? If you have any questions or need help with something," for k in range(1, 7)} - assert generated == EXPECTED_TEXT[args.shard], f"{generated=} {EXPECTED_TEXT[args.shard]}" - print("\n" + colored("output validated", "green")) # NOTE: "\n" inside colored does not render the color in github action - else: - prompt = [tokenizer.bos_id] + encode_message("system", "You are an helpful assistant.") - - start_pos = prefill(model, prompt) - while True: - toks = encode_message("user", input("Q: ")) + encode_role("assistant") - - start_pos = prefill(model, toks[:-1], start_pos=start_pos) - last_tok = toks[-1] - while True: - GlobalCounters.reset() - if args.timing or args.profile: print("") - st = GlobalCounters.time_sum_s - with Profiling(enabled=args.profile): - with Timing("total ", enabled=args.timing, on_exit=lambda x: f", {1e9/x:.2f} tok/s, {GlobalCounters.global_mem/x:.2f} GB/s, param {param_bytes/x:.2f} GB/s"): - with Timing("enqueue in ", on_exit=(lambda et: (f", {(GlobalCounters.time_sum_s-st)*1e3:.2f} ms on GPU" if DEBUG>=2 else "")+ - f", {GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.global_mem*1e-9:.2f} GB"+ - (f", {GlobalCounters.global_mem*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s, param {param_bytes*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s" if DEBUG>=2 else "")) if DEBUG else None, enabled=args.timing): - - tok = model(Tensor([[last_tok]], device=device), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P) - tok = tok.item() - start_pos += 1 - last_tok = tok - if tok in tokenizer.stop_tokens: break - print(tokenizer.decode([tok]), end="", flush=True) - print(flush=True) diff --git a/tinygrad/examples/llm.c/.gitignore b/tinygrad/examples/llm.c/.gitignore deleted file mode 100644 index 05e9d5a1..00000000 --- a/tinygrad/examples/llm.c/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -data -out.c -a.out diff --git a/tinygrad/examples/llm.c/export.py b/tinygrad/examples/llm.c/export.py deleted file mode 100755 index 9612f7e9..00000000 --- a/tinygrad/examples/llm.c/export.py +++ /dev/null @@ -1,103 +0,0 @@ -#!/usr/bin/env python3 -import os -if "NOOPT" not in os.environ: os.environ["NOOPT"] = "1" -from tinygrad import Device, nn, Tensor, dtypes, Variable -Device.DEFAULT = "CPU" -from train_gpt2 import GPT, GPTConfig -from tinygrad.helpers import dedup, to_function_name, flatten, getenv, GlobalCounters, ansilen, to_function_name -from tinygrad.engine.realize import get_kernel, run_schedule -from tinygrad.engine.memory import memory_planner -from tinygrad.uop.ops import Ops - -TIMING = getenv("TIMING") - -if __name__ == "__main__": - model = GPT(GPTConfig(n_layer=getenv("NLAYER", 12), n_head=12, n_embd=768)) - #model.load_pretrained() - for p in nn.state.get_parameters(model): p.replace(Tensor.empty(p.shape, dtype=p.dtype)) # fake load pretrained - - #early_sched = create_schedule([x.uop for x in nn.state.get_parameters(model)]) - #print(f"built model {len(early_sched)}") - - #B, T = Variable("B", 1, 128).bind(4), 64 #Variable("T", 1, 1024).bind(64) - B, T = 4, 64 - - Tensor.training = True - optimizer = nn.optim.Adam(nn.state.get_parameters(model), lr=1e-4) - warmup_count = getenv("WARMUP", 3) - for i in range(warmup_count): # TODO: why does it take three and not two to stabilize - GlobalCounters.reset() - X = Tensor.empty(4, 64, dtype=dtypes.int).reshape(B, T) - Y = Tensor.empty(4, 64, dtype=dtypes.int).reshape(B, T) - _, loss = model(X, Y) - optimizer.zero_grad() - if getenv("BACKWARD", 1): - loss.backward() - tensors = optimizer.schedule_step() - else: - tensors = [] - sched = loss.schedule(*tensors) - print(f"calls {i}:", len(sched)) - #run_schedule(sched[:]) - sched = memory_planner(sched) - ast_dedup = dedup([si.ast for si in sched if si.ast.op is Ops.SINK]) - srcs = {} - for ast in ast_dedup: - k = get_kernel(Device["CPU"].renderer, ast) - k.linearize() - src = Device["CPU"].renderer.render(to_function_name(k.name), k.uops) - srcs[ast] = (k.name, src) - print("functions:", len(srcs)) - used_buffers = dedup(flatten([si.bufs for si in sched])) - numbered_bufs = {x:i for i,x in enumerate(used_buffers)} - print("buffers:", len(numbered_bufs)) - - state_dict = nn.state.get_state_dict(model) - state_dict.update({'X': X, 'Y': Y, 'loss': loss}) - grad_state_dict = {} - for k,v in state_dict.items(): - if v.uop.base.buffer not in used_buffers: print(f"UNUSED: {k}") - if v.grad is not None: grad_state_dict['grad_'+k] = v.grad - state_dict.update(grad_state_dict) - state_dict.update({'adam_b1_t': optimizer.b1_t, 'adam_b2_t': optimizer.b2_t, 'adam_lr': optimizer.lr}) - inverse_state_dict = {v:k for k,v in state_dict.items()} - for p,m,v in zip(optimizer.params, optimizer.m, optimizer.v): - nm = inverse_state_dict[p] - state_dict["adam_m_"+nm] = m - state_dict["adam_v_"+nm] = v - named_buffers = {v.uop.base.buffer:k.replace(".", "_") for k,v in state_dict.items()} - - c_code = ["#include ", "#include ", "#include "] - if TIMING: c_code += ["#include ", "#include "] - c_code += [x[1].replace(" restrict ", " ")+"\n" for x in srcs.values()] - - premain = ["int main() {"] - if TIMING: - premain += [" struct timespec tm0; clock_gettime(CLOCK_MONOTONIC, &tm0);"] - lst = 0 - main = [] - - all_bufs = [] - for i,si in enumerate(sched): - bufs = [(named_buffers.get(b, f"b{numbered_bufs[b]}"), b) for b in si.bufs] - all_bufs += bufs - if si.ast.op is not Ops.SINK: - print(f"// {si.ast.op}", bufs) - else: - print(f"{srcs[si.ast][0]}({', '.join([x[0] for x in bufs])})") - main.append(f" {to_function_name(srcs[si.ast][0])}({', '.join([x[0] for x in bufs])});") - if TIMING: - main.append(f" struct timespec tm{i+1}; clock_gettime(CLOCK_MONOTONIC, &tm{i+1});") - main.append(f" printf(\"%10.2f ms + %7.2f ms @ {to_function_name(srcs[si.ast][0])}\\n\"," +\ - f"((tm{i+1}.tv_sec-tm{0}.tv_sec) + (tm{i+1}.tv_nsec-tm{0}.tv_nsec) / 1e9) * 1e3," +\ - f"((tm{i+1}.tv_sec-tm{lst}.tv_sec) + (tm{i+1}.tv_nsec-tm{lst}.tv_nsec) / 1e9) * 1e3);") - lst = i+1 - #call = f"{srcs[si.ast][0]}({', '.join(bufs)})" - #call += " "*(80-ansilen(call)) - #print(f"{call} // {i+1}") - #print(srcs[si.ast][1]) - main.append("}") - - mallocs = [f" {b.dtype.name}* {n} = ({b.dtype.name}*)malloc({b.nbytes});" for n,b in dedup(all_bufs)] - - with open("out.c", "w") as f: f.write('\n'.join(c_code+premain+mallocs+main)) diff --git a/tinygrad/examples/llm.c/train_gpt2.py b/tinygrad/examples/llm.c/train_gpt2.py deleted file mode 100755 index e259cf44..00000000 --- a/tinygrad/examples/llm.c/train_gpt2.py +++ /dev/null @@ -1,207 +0,0 @@ -#!/usr/bin/env python3 -import os, math, time -import numpy as np -from tinygrad import Tensor, nn, fetch, Device, TinyJit, GlobalCounters -from dataclasses import dataclass - -@dataclass -class GPTConfig: - block_size: int = 1024 - vocab_size: int = 50257 - padded_vocab_size: int = 50304 - n_layer: int = 12 - n_head: int = 12 - n_embd: int = 768 - -class CausalSelfAttention: - def __init__(self, config:GPTConfig): - assert config.n_embd % config.n_head == 0 - # key, query, value projections for all heads, but in a batch - self.c_attn = nn.Linear(config.n_embd, 3 * config.n_embd) - # output projection - self.c_proj = nn.Linear(config.n_embd, config.n_embd) - # regularization - self.n_head = config.n_head - self.n_embd = config.n_embd - # not really a 'bias', more of a mask, but following the OpenAI/HF naming though - self.bias = Tensor.ones(1, 1, config.block_size, config.block_size).tril() - self.bias.requires_grad = False - - def __call__(self, x:Tensor): - B, T, C = x.shape - qkv = self.c_attn(x) - q, k, v = qkv.split(self.n_embd, dim=2) - k = k.view(B, T, self.n_head, C // self.n_head).transpose(1, 2) # (B, nh, T, hs) - q = q.view(B, T, self.n_head, C // self.n_head).transpose(1, 2) # (B, nh, T, hs) - v = v.view(B, T, self.n_head, C // self.n_head).transpose(1, 2) # (B, nh, T, hs) - - # manual implementation of attention - att = (q @ k.transpose(-2, -1)) * (1.0 / math.sqrt(k.size(-1))) - att = att.masked_fill(self.bias[:,:,:T,:T] == 0, float('-inf')) - att = att.softmax() - y = att @ v # (B, nh, T, T) x (B, nh, T, hs) -> (B, nh, T, hs) - y = y.transpose(1, 2).view(B, T, C) # re-assemble all head outputs side by side - # output projection - y = self.c_proj(y) - return y - -class MLP: - def __init__(self, config:GPTConfig): - self.c_fc = nn.Linear(config.n_embd, 4 * config.n_embd) - self.c_proj = nn.Linear(4 * config.n_embd, config.n_embd) - - def __call__(self, x:Tensor) -> Tensor: - return self.c_proj(self.c_fc(x).gelu()) - -class Block: - def __init__(self, config:GPTConfig): - self.ln_1 = nn.LayerNorm(config.n_embd) - self.attn = CausalSelfAttention(config) - self.ln_2 = nn.LayerNorm(config.n_embd) - self.mlp = MLP(config) - - def __call__(self, x:Tensor): - x = x + self.attn(self.ln_1(x)) - x = x + self.mlp(self.ln_2(x)) - return x - -class GPT: - def __init__(self, config:GPTConfig): - self.config = config - - self.wte = nn.Embedding(config.padded_vocab_size, config.n_embd) - self.wpe = nn.Embedding(config.block_size, config.n_embd) - self.h = [Block(config) for _ in range(config.n_layer)] - self.ln_f = nn.LayerNorm(config.n_embd) - self.lm_head = nn.Linear(config.n_embd, config.padded_vocab_size, bias=False) - self.wte.weight = self.lm_head.weight # https://paperswithcode.com/method/weight-tying - - def load_pretrained(self): - weights = nn.state.torch_load(fetch(f'https://huggingface.co/gpt2/resolve/main/pytorch_model.bin')) - transposed = ('attn.c_attn.weight', 'attn.c_proj.weight', 'mlp.c_fc.weight', 'mlp.c_proj.weight') - for k in weights: - if k == "wte.weight": - weights[k] = weights[k].pad(((0, self.config.padded_vocab_size-self.config.vocab_size), (0,0))).to(None).contiguous() - if k.endswith(transposed): - weights[k] = weights[k].to(None).T.contiguous() - # lm head and wte are tied - weights['lm_head.weight'] = weights['wte.weight'] - nn.state.load_state_dict(self, weights) - - def generate(self, idx, max_new_tokens, temperature=1.0, top_k=None): - for _ in range(max_new_tokens): - idx_cond = idx if idx.shape[1] <= self.config.block_size else idx[:, -self.config.block_size:] - logits, _ = self(idx_cond) - logits = logits[:, -1, :] / temperature - idx_next = logits.softmax().multinomial() - idx = Tensor.cat(idx, idx_next, dim=1) - return idx - - def __call__(self, idx:Tensor, targets=None): - b, t = idx.shape - pos = Tensor.arange(0, t, device=idx.device) - - tok_emb = self.wte(idx) # token embeddings of shape (b, t, n_embd) - pos_emb = self.wpe(pos) # position embeddings of shape (t, n_embd) - x = tok_emb + pos_emb - - x = self.ln_f(x.sequential(self.h)) - - if targets is not None: - logits = self.lm_head(x)[:, :, :self.config.vocab_size] - loss = logits.sparse_categorical_crossentropy(targets) - else: - logits = self.lm_head(x[:, [-1], :])[:, :, :self.config.vocab_size] - loss = None - - return logits, loss - -if __name__ == "__main__": - import tiktoken, argparse - - parser = argparse.ArgumentParser() - parser.add_argument("--num_iterations", type=int, default=10, help="number of iterations to run") - parser.add_argument("--batch_size", type=int, default=4, help="batch size") - parser.add_argument("--sequence_length", type=int, default=64, help="sequence length") - parser.add_argument("--skip_test", action="store_true", help="skip test") - parser.add_argument("--gpus", type=int, default=1, help="sequence length") - args = parser.parse_args() - B, T = args.batch_size, args.sequence_length - assert 1 <= T <= 1024 - - model = GPT(GPTConfig(n_layer=12, n_head=12, n_embd=768)) - model.load_pretrained() - - if args.gpus > 1: - GPUS = tuple(f'{Device.DEFAULT}:{i}' for i in range(args.gpus)) - for x in nn.state.get_parameters(model): x.to_(GPUS) # we put a copy of the model on every GPU - - # init the tokenizer - enc = tiktoken.get_encoding("gpt2") - encode = lambda s: enc.encode(s, allowed_special={"<|endoftext|>"}) - decode = lambda l: enc.decode(l) - - # load the tokens - # prefer to use tiny_shakespeare if it's available, otherwise use tiny_stories - # we're using val instead of train split just because it is smaller/faster - tokens_bin = fetch("https://huggingface.co/datasets/karpathy/llmc-starter-pack/resolve/main/tiny_shakespeare_val.bin") - assert os.path.isfile(tokens_bin) - print(f"loading cached tokens in {tokens_bin}") - with open(tokens_bin, "rb") as f: - f.seek(0x400) - tokens = np.frombuffer(f.read(), dtype=np.uint16).astype(np.int32) - tokens = Tensor(tokens) - - # lightweight dataloader - def get_batch(): - assert B*T+1 <= len(tokens), "not enough tokens" - # for 338,025 tokens. E.g. with B=8 T=1024, this will yield 41 batches before looping - i = 0 - while True: - x = tokens[i:i+B*T].view(B, T) - y = tokens[i+1:i+B*T+1].view(B, T) - yield x, y - i += B*T - if i + B*T + 1 >= len(tokens): - i = 0 # in prod we'd want to randomize the start point a bit - - # forward backward for a few iterations - data_iter = iter(get_batch()) - x, y = next(data_iter) # we'll overfit this batch below - optimizer = nn.optim.AdamW(nn.state.get_parameters(model), lr=1e-4, weight_decay=0) - - print(f"model state: {sum(x.nbytes() for x in nn.state.get_parameters(model))/1e9:.2f} GB") - print(f"optimizer state: {sum(x.nbytes() for x in nn.state.get_parameters(optimizer))/1e9:.2f} GB") - - # shard the data on axis 0 - if args.gpus > 1: x, y = x.shard(GPUS, axis=0), y.shard(GPUS, axis=0) - - @TinyJit - @Tensor.train() - def step(x:Tensor, y:Tensor) -> Tensor: - _, loss = model(x, y) - optimizer.zero_grad() - loss.backward() - return loss.realize(*optimizer.schedule_step()) - - for i in range(args.num_iterations): - GlobalCounters.reset() - t0 = time.perf_counter() - loss = step(x.contiguous(), y.contiguous()) - Device[Device.DEFAULT].synchronize() - t1 = time.perf_counter() - print(f"iteration {i}, loss: {loss.item():.6f}, time: {(t1-t0)*1000:.3f}ms, {int(B*T/(t1-t0))} tok/s, {GlobalCounters.global_mem/1e9:.2f} GB") - - if not args.skip_test: - # copy back to single gpu for test - if args.gpus > 1: - for x in nn.state.get_parameters(model): x.to_(Device.DEFAULT) - start = "<|endoftext|>" - start_ids = encode(start) - x = (Tensor(start_ids)[None, ...]) - max_new_tokens = 16 - temperature = 1.0 - top_k = 40 - y = model.generate(x, max_new_tokens, temperature=temperature, top_k=top_k) - print(decode(y[0].tolist())) - diff --git a/tinygrad/examples/llm.c/ubench/matmul.c b/tinygrad/examples/llm.c/ubench/matmul.c deleted file mode 100644 index 685d2656..00000000 --- a/tinygrad/examples/llm.c/ubench/matmul.c +++ /dev/null @@ -1,65 +0,0 @@ -// clang -Ofast -Wno-unused-result -march=native matmul.c -#include -#include -#include - -float b52[786432]; -float b49[196608]; -float h_0_mlp_c_fc_weight[2359296]; -float h_0_mlp_c_fc_bias[3072]; - -void matmul_forward(float* out, - float* inp, float* weight, float* bias, - int B, int T, int C, int OC) { - // most of the running time is spent here and in matmul_backward - // OC is short for "output channels" - // inp is (B,T,C), weight is (OC, C), bias is (OC) - // out will be (B,T,OC) - #pragma omp parallel for collapse(2) - for (int b = 0; b < B; b++) { - for (int t = 0; t < T; t++) { - float* out_bt = out + b * T * OC + t * OC; - float* inp_bt = inp + b * T * C + t * C; - for (int o = 0; o < OC; o++) { - float val = (bias != NULL) ? bias[o] : 0.0f; - float* wrow = weight + o*C; - for (int i = 0; i < C; i++) { - val += inp_bt[i] * wrow[i]; - } - out_bt[o] = val; - } - } - } -} - - -void r_256_3072_768(float* restrict data0, const float* restrict data1, const float* restrict data2, const float* restrict data3) { - for (int ridx0 = 0; ridx0 < 256; ridx0++) { - for (int ridx1 = 0; ridx1 < 3072; ridx1++) { - float acc0 = 0.0f; - float val0 = data3[ridx1]; - for (int ridx2 = 0; ridx2 < 768; ridx2++) { - float val1 = data1[(ridx0*768)+ridx2]; - float val2 = data2[(ridx1*768)+ridx2]; - acc0 = ((val1*val2)+acc0); - } - data0[(ridx0*3072)+ridx1] = (acc0+val0); - } - } -} - - -int main() { - for (int i = 0; i < 5; i++) { - struct timespec t1, t2, t3; - clock_gettime(CLOCK_MONOTONIC, &t1); - r_256_3072_768(b52, b49, h_0_mlp_c_fc_weight, h_0_mlp_c_fc_bias); - clock_gettime(CLOCK_MONOTONIC, &t2); - matmul_forward(b52, b49, h_0_mlp_c_fc_weight, h_0_mlp_c_fc_bias, 4, 64, 768, 3072); - clock_gettime(CLOCK_MONOTONIC, &t3); - double time_gen = (t2.tv_sec - t1.tv_sec) + (t2.tv_nsec - t1.tv_nsec) / 1e9; - double time_real = (t3.tv_sec - t2.tv_sec) + (t3.tv_nsec - t2.tv_nsec) / 1e9; - printf("%.2f ms gen vs %.2f ms reference\n", time_gen*1e3, time_real*1e3); - } -} - diff --git a/tinygrad/examples/mamba.py b/tinygrad/examples/mamba.py deleted file mode 100644 index d6093eab..00000000 --- a/tinygrad/examples/mamba.py +++ /dev/null @@ -1,316 +0,0 @@ -import os, sys, math, argparse, time -sys.path.append(os.getcwd()) -from typing import Any, Optional, Dict - -from tinygrad import Tensor, TinyJit, nn -from tinygrad.helpers import fetch -from tinygrad.nn.state import load_state_dict, torch_load - -from tqdm import tqdm -from transformers import AutoTokenizer - -MODELS = { - "130m": {"dim": 768, "n_layers": 24, "vocab_size": 50277, "pad_vocab_size_multiple": 8}, - "370m": {"dim": 1024, "n_layers": 48, "vocab_size": 50277, "pad_vocab_size_multiple": 8}, - "790m": {"dim": 1536, "n_layers": 48, "vocab_size": 50277, "pad_vocab_size_multiple": 8}, - "1.4b": {"dim": 2048, "n_layers": 48, "vocab_size": 50277, "pad_vocab_size_multiple": 8}, - "2.8b": {"dim": 2560, "n_layers": 64, "vocab_size": 50277, "pad_vocab_size_multiple": 8}, -} - -def fetch_weights(model_name: str) -> Dict[str, Tensor]: - if model_name not in MODELS: - raise ValueError(f"Requested unknown mamba model: {model_name}") - downloaded = fetch(f"https://huggingface.co/state-spaces/mamba-{model_name}/resolve/main/pytorch_model.bin?download=true") - return torch_load(downloaded) - -def selective_scan_ref( - u, - delta, - A, - B, - C, - D=None, - z=None, - delta_bias=None, - delta_softplus=False, - return_last_state=False, -): - """ - u: r(B D L) - delta: r(B D L) - A: c(D N) or r(D N) - B: c(D N) or r(B N L) or r(B N 2L) or r(B G N L) or (B G N L) - C: c(D N) or r(B N L) or r(B N 2L) or r(B G N L) or (B G N L) - D: r(D) - z: r(B D L) - delta_bias: r(D), fp32 - - out: r(B D L) - last_state (optional): r(B D dstate) or c(B D dstate) - """ - u = u.float() - delta = delta.float() - if delta_bias is not None: - delta = delta + delta_bias[..., None].float() - if delta_softplus: - delta = delta.softplus() - batch, dim, dstate = u.shape[0], A.shape[0], A.shape[1] - is_variable_B = len(B.shape) >= 3 - is_variable_C = len(C.shape) >= 3 - x = Tensor.zeros(batch, dim, dstate) - ys = [] - deltaA = Tensor.einsum("bdl,dn->bdln", delta, A).exp() - if not is_variable_B: - deltaB_u = Tensor.einsum("bdl,dn,bdl->bdln", delta, B, u) - else: - if len(B.shape) == 3: - deltaB_u = Tensor.einsum("bdl,bnl,bdl->bdln", delta, B, u) - else: - B = B.repeat((1, dim // B.shape[1], 1, 1)) - deltaB_u = Tensor.einsum("bdl,bdnl,bdl->bdln", delta, B, u) - if is_variable_C and len(C.shape) == 4: - C = C.repeat((1, dim // C.shape[1], 1, 1)) - last_state = None - for i in range(u.shape[2]): - x = deltaA[:, :, i] * x + deltaB_u[:, :, i] - if not is_variable_C: - y = Tensor.einsum("bdn,dn->bd", x, C) - else: - if len(C.shape) == 3: - y = Tensor.einsum("bdn,bn->bd", x, C[:, :, i]) - else: - y = Tensor.einsum("bdn,bdn->bd", x, C[:, :, :, i]) - if i == u.shape[2] - 1: - last_state = x - ys.append(y) - y = Tensor.stack(*ys, dim=2) # (batch dim L) - out = y if D is None else y + u * D.reshape((-1, 1)) - if z is not None: - out = out * z.silu() - return out if not return_last_state else (out, last_state) - -class MambaMixer: - def __init__( - self, - dim, - d_state=16, - d_conv=4, - expand=2, - dt_rank="auto", - dt_min=0.001, - dt_max=0.1, - dt_init="random", - dt_scale=1.0, - dt_init_floor=1e-4, - conv_bias=True, - bias=False, - layer_idx=None, - ): - self.dim = dim - self.d_state = d_state - self.d_conv = d_conv - self.expand = expand - self.d_inner = self.expand * self.dim - self.dt_rank = math.ceil(self.dim / 16) if dt_rank == "auto" else dt_rank - self.layer_idx = layer_idx - - self.in_proj = nn.Linear(self.dim, self.d_inner * 2, bias=bias) - - self.conv1d = nn.Conv1d(in_channels=self.d_inner, out_channels=self.d_inner, bias=conv_bias, - kernel_size=d_conv, groups=self.d_inner, padding=d_conv-1) - - self.x_proj = nn.Linear(self.d_inner, self.dt_rank + self.d_state * 2, bias=False) - self.dt_proj = nn.Linear(self.dt_rank, self.d_inner, bias=True) - - # Initialize special dt projection to preserve variance at initialization - dt_init_std = self.dt_rank**-0.5 * dt_scale - if dt_init == "constant": - self.dt_proj.weight = Tensor.full(self.dt_proj.weight.shape, dt_init_std) - elif dt_init == "random": - self.dt_proj.weight = Tensor.uniform(self.dt_proj.weight.shape, low=-dt_init_std, high=dt_init_std) - else: - raise NotImplementedError - - dt = Tensor.uniform(self.d_inner, low=math.log(dt_min), high=math.log(dt_max)).exp().maximum(dt_init_floor) - inv_dt = dt + (1 - (-dt).exp()).log() - - self.dt_proj.bias.assign(inv_dt) - - # S4D real initialization - self.A_log = Tensor.arange(1, self.d_state+1).repeat([self.d_inner, 1]).log() - - # D "skip" parameter - self.D = Tensor.ones(self.d_inner) # Keep in fp32 - - self.out_proj = nn.Linear(self.d_inner, self.dim, bias=bias) - - def __call__(self, hidden_states: Tensor): - batch, seqlen, _ = hidden_states.shape - - if not hasattr(self, 'conv_state'): - self.conv_state = Tensor.zeros(batch, self.dim * self.expand, self.d_conv).contiguous().realize() - self.ssm_state = Tensor.zeros(batch, self.dim * self.expand, self.d_state).realize() - - xz = self.in_proj.weight @ hidden_states.permute(2,0,1).reshape(hidden_states.shape[2],hidden_states.shape[1]*hidden_states.shape[0]) - xz = xz.reshape(xz.shape[0],xz.shape[1]//seqlen, seqlen).permute(1,0,2) - - if self.in_proj.bias is not None: - xz = xz + self.in_proj.bias.reshape((-1, 1)) - - A = -self.A_log.exp() - x, z = xz.chunk(2, dim=1) - # Compute short convolution - self.conv_state.assign(x[:, :, -self.d_conv :]) # Update state (B D W) - x = self.conv1d(x)[..., :seqlen].swish() - - x_dbl = self.x_proj(x.permute(0,2,1).reshape(x.shape[0]*x.shape[2], x.shape[1])) - dt, B, C = Tensor.split(x_dbl, [self.dt_rank, self.d_state, self.d_state], dim=-1) - dt = self.dt_proj.weight @ dt.T - dt = dt.reshape(dt.shape[0], dt.shape[1]//seqlen, seqlen).permute(1,0,2) - B = B.reshape(B.shape[0]//seqlen, seqlen, B.shape[1]).permute(0,2,1) - C = C.reshape(C.shape[0]//seqlen, seqlen, C.shape[1]).permute(0,2,1) - - # TODO: actually implement selective_scan_fn - y = selective_scan_ref(x, dt, A, B, C, self.D, z=z, delta_bias=self.dt_proj.bias, delta_softplus=True, - return_last_state=True) - - y, last_state = y - self.ssm_state.assign(last_state).realize() - y = y.permute(0,2,1) - out = self.out_proj(y) - return out - else: - return self.step(hidden_states) - - def step(self, hidden_states: Tensor): - assert hidden_states.shape[1] == 1, f"Only support decoding with 1 token at a time for now, attempted {hidden_states.shape[1]}" - xz = self.in_proj(hidden_states.squeeze(1)) # (B 2D) - x, z = xz.chunk(2, dim=-1) # (B D) - - # Conv step - self.conv_state.assign(self.conv_state[:, :, 1:].cat(x.unsqueeze(-1), dim=-1).realize()) - x = (self.conv_state * self.conv1d.weight.squeeze(1)).sum(-1) - if self.conv1d.bias is not None: - x = x + self.conv1d.bias - x = x.swish() - - x_db = self.x_proj(x) # (B dt_rank+2*d_state) - dt = x_db[:, : self.dt_rank] - B = x_db[:, self.dt_rank : (self.dt_rank + self.d_state)] - C = x_db[:, (self.dt_rank + self.d_state) :] - # Don't add dt_bias here - dt = self.dt_proj.weight @ dt.T - A = -self.A_log.exp() - - # SSM step - dt = (dt + self.dt_proj.bias.unsqueeze(-1)).softplus() - dA = Tensor.einsum("db,dn->bdn", dt, A).exp() - dB = Tensor.einsum("db,bn->bdn", dt, B) - self.ssm_state.assign(self.ssm_state * dA + x.unsqueeze(-1) * dB) - y = Tensor.einsum("bdn,bn->bd", self.ssm_state, C) - y = y + self.D * x - y = y * z.swish() # (B D) - - out = self.out_proj(y) - return out.unsqueeze(1) - -class MambaBlock: - def __init__(self, dim: int, norm_eps: float = 1e-5, rms_norm: bool = True, layer_idx: Optional[int] = None): - self.mixer = MambaMixer(dim, layer_idx=layer_idx) - if rms_norm: - self.norm = nn.RMSNorm(dim, norm_eps) - else: - raise NotImplementedError - - def __call__(self, hidden_states: Tensor, residual: Optional[Tensor] = None): - residual = (hidden_states + residual) if residual is not None else hidden_states - hidden_states = self.norm(residual) - hidden_states = self.mixer(hidden_states) - return hidden_states, residual - -class MambaBackbone: - def __init__(self, dim: int, n_layers: int, vocab_size: int, rms_norm: bool = True, norm_eps: float = 1e-5): - self.embedding = nn.Embedding(vocab_size, dim) - self.layers = [MambaBlock(dim, rms_norm=rms_norm, layer_idx=i) for i in range(n_layers)] - if rms_norm: - self.norm_f = nn.RMSNorm(dim, norm_eps) - - def __call__(self, input_ids: Tensor) -> Any: - hidden_states = self.embedding(input_ids) - residual = None - for layer in self.layers: - hidden_states, residual = layer(hidden_states, residual) - - residual = (hidden_states + residual) if residual is not None else hidden_states - hidden_states = self.norm_f(residual) - return hidden_states - -class Mamba: - def __init__(self, dim: int, n_layers: int, vocab_size: int, pad_vocab_size_multiple: int = 1): - if vocab_size % pad_vocab_size_multiple != 0: - vocab_size += pad_vocab_size_multiple - (vocab_size % pad_vocab_size_multiple) - - self.backbone = MambaBackbone(dim, n_layers, vocab_size) - self.lm_head = nn.Linear(dim, vocab_size, bias=False) - - self.forward_jit = TinyJit(self.forward) - - def forward(self, input_ids:Tensor): - hidden_states = self.backbone(input_ids) - return self.lm_head(hidden_states).realize() - - def __call__(self, input_ids): - return self.forward(input_ids) - - @staticmethod - def from_pretrained(model_name: str): - weights = fetch_weights(model_name) - model = Mamba(**MODELS[model_name]) - load_state_dict(model, weights) - - return model - - -def generate(model, tokenizer, prompt: str, n_tokens_to_gen: int = 10, temp: bool = 1.0, sample: bool = False, top_k: int = None): - tks = tokenizer(prompt)["input_ids"] - while len(tks) < 4: - tks = [50279] + tks - - # Loading in the prompt tokens - logits = model.forward(Tensor([tks]))[:, -1, :] - for _ in tqdm(range(n_tokens_to_gen), desc="Speed Gen"): - # TODO: topk - if sample: - tok_Tens = (logits/temp).softmax().multinomial() - else: - tok_Tens = logits.argmax(axis=-1).unsqueeze(0) - tok = tok_Tens.item() - tks.append(tok) - logits = model.forward_jit(tok_Tens)[:, -1, :] - - output_completions = ''.join([tokenizer.decode(output) for output in tks]) - return output_completions - -if __name__ == "__main__": - ORIG_PROMPT = "Why is gravity " - parser = argparse.ArgumentParser(description="Run Mamba in tinygrad", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--prompt", type=str, default="Why is gravity ", help="Prompt for LLM completion") - parser.add_argument("--size", type=str, default="370m", - help=f"Size of model to use [{', '.join([k for k in MODELS.keys()])}]") - parser.add_argument("--n_tokens", type=int, default=10, help="Number of tokens to generate") - parser.add_argument("--sample", dest="sample", action="store_true", help="Sample flag") - parser.add_argument("--temp", type=float, default=1.0, help="Sampling temp has to be <=1.0") - args = parser.parse_args() - - tokenizer = AutoTokenizer.from_pretrained("EleutherAI/gpt-neox-20b") - model = Mamba.from_pretrained(args.size) - prompt = args.prompt - num_toks = args.n_tokens - sample = args.sample - temp = args.temp - s = time.time() - tinyoutput = generate(model, tokenizer, prompt, n_tokens_to_gen=num_toks, sample=sample, temp=temp) - print(tinyoutput) - print('TIME: ', time.time() - s) - TORCHOUTPUT = "Why is gravity \nso important?\nBecause it's the only" - if ORIG_PROMPT == prompt and not sample and num_toks==10 and args.size=='370m': print('Outputs Match:', tinyoutput == TORCHOUTPUT) \ No newline at end of file diff --git a/tinygrad/examples/mask_rcnn.py b/tinygrad/examples/mask_rcnn.py deleted file mode 100644 index 00d4c240..00000000 --- a/tinygrad/examples/mask_rcnn.py +++ /dev/null @@ -1,299 +0,0 @@ -from extra.models.mask_rcnn import MaskRCNN -from extra.models.resnet import ResNet -from extra.models.mask_rcnn import BoxList -from torch.nn import functional as F -from torchvision import transforms as T -from torchvision.transforms import functional as Ft -import random -from tinygrad.tensor import Tensor -from PIL import Image -import numpy as np -import torch -import argparse -import cv2 - - -class Resize: - def __init__(self, min_size, max_size): - if not isinstance(min_size, (list, tuple)): - min_size = (min_size,) - self.min_size = min_size - self.max_size = max_size - - # modified from torchvision to add support for max size - def get_size(self, image_size): - w, h = image_size - size = random.choice(self.min_size) - max_size = self.max_size - if max_size is not None: - min_original_size = float(min((w, h))) - max_original_size = float(max((w, h))) - if max_original_size / min_original_size * size > max_size: - size = int(round(max_size * min_original_size / max_original_size)) - - if (w <= h and w == size) or (h <= w and h == size): - return (h, w) - - if w < h: - ow = size - oh = int(size * h / w) - else: - oh = size - ow = int(size * w / h) - - return (oh, ow) - - def __call__(self, image): - size = self.get_size(image.size) - image = Ft.resize(image, size) - return image - - -class Normalize: - def __init__(self, mean, std, to_bgr255=True): - self.mean = mean - self.std = std - self.to_bgr255 = to_bgr255 - - def __call__(self, image): - if self.to_bgr255: - image = image[[2, 1, 0]] * 255 - else: - image = image[[0, 1, 2]] * 255 - image = Ft.normalize(image, mean=self.mean, std=self.std) - return image - -transforms = lambda size_scale: T.Compose( - [ - Resize(int(800*size_scale), int(1333*size_scale)), - T.ToTensor(), - Normalize( - mean=[102.9801, 115.9465, 122.7717], std=[1., 1., 1.], to_bgr255=True - ), - ] -) - -def expand_boxes(boxes, scale): - w_half = (boxes[:, 2] - boxes[:, 0]) * .5 - h_half = (boxes[:, 3] - boxes[:, 1]) * .5 - x_c = (boxes[:, 2] + boxes[:, 0]) * .5 - y_c = (boxes[:, 3] + boxes[:, 1]) * .5 - - w_half *= scale - h_half *= scale - - boxes_exp = torch.zeros_like(boxes) - boxes_exp[:, 0] = x_c - w_half - boxes_exp[:, 2] = x_c + w_half - boxes_exp[:, 1] = y_c - h_half - boxes_exp[:, 3] = y_c + h_half - return boxes_exp - - -def expand_masks(mask, padding): - N = mask.shape[0] - M = mask.shape[-1] - pad2 = 2 * padding - scale = float(M + pad2) / M - padded_mask = mask.new_zeros((N, 1, M + pad2, M + pad2)) - padded_mask[:, :, padding:-padding, padding:-padding] = mask - return padded_mask, scale - - -def paste_mask_in_image(mask, box, im_h, im_w, thresh=0.5, padding=1): - # TODO: remove torch - mask = torch.tensor(mask.numpy()) - box = torch.tensor(box.numpy()) - padded_mask, scale = expand_masks(mask[None], padding=padding) - mask = padded_mask[0, 0] - box = expand_boxes(box[None], scale)[0] - box = box.to(dtype=torch.int32) - - TO_REMOVE = 1 - w = int(box[2] - box[0] + TO_REMOVE) - h = int(box[3] - box[1] + TO_REMOVE) - w = max(w, 1) - h = max(h, 1) - - mask = mask.expand((1, 1, -1, -1)) - - mask = mask.to(torch.float32) - mask = F.interpolate(mask, size=(h, w), mode='bilinear', align_corners=False) - mask = mask[0][0] - - if thresh >= 0: - mask = mask > thresh - else: - mask = (mask * 255).to(torch.uint8) - - im_mask = torch.zeros((im_h, im_w), dtype=torch.uint8) - x_0 = max(box[0], 0) - x_1 = min(box[2] + 1, im_w) - y_0 = max(box[1], 0) - y_1 = min(box[3] + 1, im_h) - - im_mask[y_0:y_1, x_0:x_1] = mask[ - (y_0 - box[1]): (y_1 - box[1]), (x_0 - box[0]): (x_1 - box[0]) - ] - return im_mask - - -class Masker: - def __init__(self, threshold=0.5, padding=1): - self.threshold = threshold - self.padding = padding - - def forward_single_image(self, masks, boxes): - boxes = boxes.convert("xyxy") - im_w, im_h = boxes.size - res = [ - paste_mask_in_image(mask[0], box, im_h, im_w, self.threshold, self.padding) - for mask, box in zip(masks, boxes.bbox) - ] - if len(res) > 0: - res = torch.stack(*res, dim=0)[:, None] - else: - res = masks.new_empty((0, 1, masks.shape[-2], masks.shape[-1])) - return Tensor(res.numpy()) - - def __call__(self, masks, boxes): - if isinstance(boxes, BoxList): - boxes = [boxes] - - results = [] - for mask, box in zip(masks, boxes): - result = self.forward_single_image(mask, box) - results.append(result) - return results - - -masker = Masker(threshold=0.5, padding=1) - -def select_top_predictions(predictions, confidence_threshold=0.9): - scores = predictions.get_field("scores").numpy() - keep = [idx for idx, score in enumerate(scores) if score > confidence_threshold] - return predictions[keep] - -def compute_prediction(original_image, model, confidence_threshold, size_scale=1.0): - image = transforms(size_scale)(original_image).numpy() - image = Tensor(image, requires_grad=False) - predictions = model(image) - prediction = predictions[0] - prediction = select_top_predictions(prediction, confidence_threshold) - width, height = original_image.size - prediction = prediction.resize((width, height)) - - if prediction.has_field("mask"): - masks = prediction.get_field("mask") - masks = masker([masks], [prediction])[0] - prediction.add_field("mask", masks) - return prediction - -def compute_prediction_batched(batch, model, size_scale=1.0): - imgs = [] - for img in batch: - imgs.append(transforms(size_scale)(img).numpy()) - image = [Tensor(image, requires_grad=False) for image in imgs] - predictions = model(image) - del image - return predictions - -palette = np.array([2 ** 25 - 1, 2 ** 15 - 1, 2 ** 21 - 1]) - -def findContours(*args, **kwargs): - if cv2.__version__.startswith('4'): - contours, hierarchy = cv2.findContours(*args, **kwargs) - elif cv2.__version__.startswith('3'): - _, contours, hierarchy = cv2.findContours(*args, **kwargs) - return contours, hierarchy - -def compute_colors_for_labels(labels): - l = labels[:, None] - colors = l * palette - colors = (colors % 255).astype("uint8") - return colors - -def overlay_mask(image, predictions): - image = np.asarray(image) - masks = predictions.get_field("mask").numpy() - labels = predictions.get_field("labels").numpy() - - colors = compute_colors_for_labels(labels).tolist() - - for mask, color in zip(masks, colors): - thresh = mask[0, :, :, None] - contours, hierarchy = findContours( - thresh, cv2.RETR_TREE, cv2.CHAIN_APPROX_SIMPLE - ) - image = cv2.drawContours(image, contours, -1, color, 3) - - composite = image - - return composite - -CATEGORIES = [ - "__background", "person", "bicycle", "car", "motorcycle", "airplane", "bus", "train", "truck", "boat", "traffic light", - "fire hydrant", "stop sign", "parking meter", "bench", "bird", "cat", "dog", "horse", "sheep", "cow", "elephant", - "bear", "zebra", "giraffe", "backpack", "umbrella", "handbag", "tie", "suitcase", "frisbee", "skis", "snowboard", - "sports ball", "kite", "baseball bat", "baseball glove", "skateboard", "surfboard", "tennis racket", "bottle", - "wine glass", "cup", "fork", "knife", "spoon", "bowl", "banana", "apple", "sandwich", "orange", "broccoli", - "carrot", "hot dog", "pizza", "donut", "cake", "chair", "couch", "potted plant", "bed", "dining table", - "toilet", "tv", "laptop", "mouse", "remote", "keyboard", "cell phone", "microwave", "oven", "toaster", - "sink", "refrigerator", "book", "clock", "vase", "scissors", "teddy bear", "hair drier", "toothbrush", -] - -def overlay_boxes(image, predictions): - labels = predictions.get_field("labels").numpy() - boxes = predictions.bbox - image = np.asarray(image) - colors = compute_colors_for_labels(labels).tolist() - - for box, color in zip(boxes, colors): - box = torch.tensor(box.numpy()) - box = box.to(torch.int64) - top_left, bottom_right = box[:2].tolist(), box[2:].tolist() - image = cv2.rectangle( - image, tuple(top_left), tuple(bottom_right), tuple(color), 1 - ) - - return image - -def overlay_class_names(image, predictions): - scores = predictions.get_field("scores").numpy().tolist() - labels = predictions.get_field("labels").numpy().tolist() - labels = [CATEGORIES[int(i)] for i in labels] - boxes = predictions.bbox.numpy() - image = np.asarray(image) - template = "{}: {:.2f}" - for box, score, label in zip(boxes, scores, labels): - x, y = box[:2] - s = template.format(label, score) - x, y = int(x), int(y) - cv2.putText( - image, s, (x, y), cv2.FONT_HERSHEY_SIMPLEX, .5, (255, 255, 255), 1 - ) - - return image - - -if __name__ == '__main__': - parser = argparse.ArgumentParser(description='Run MaskRCNN', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--image', type=str, help="Path of the image to run") - parser.add_argument('--threshold', type=float, default=0.7, help="Detector threshold") - parser.add_argument('--size_scale', type=float, default=1.0, help="Image resize multiplier") - parser.add_argument('--out', type=str, default="/tmp/rendered.png", help="Output filename") - args = parser.parse_args() - - resnet = ResNet(50, num_classes=None, stride_in_1x1=True) - model_tiny = MaskRCNN(resnet) - model_tiny.load_from_pretrained() - img = Image.open(args.image) - top_result_tiny = compute_prediction(img, model_tiny, confidence_threshold=args.threshold, size_scale=args.size_scale) - bbox_image = overlay_boxes(img, top_result_tiny) - mask_image = overlay_mask(bbox_image, top_result_tiny) - final_image = overlay_class_names(mask_image, top_result_tiny) - - im = Image.fromarray(final_image) - print(f"saving {args.out}") - im.save(args.out) - im.show() diff --git a/tinygrad/examples/minrf.py b/tinygrad/examples/minrf.py deleted file mode 100644 index 584e6410..00000000 --- a/tinygrad/examples/minrf.py +++ /dev/null @@ -1,156 +0,0 @@ -# much taken from https://github.com/cloneofsimo/minRF -from tinygrad import Tensor, nn, GlobalCounters, TinyJit -from tinygrad.helpers import getenv, trange -from extra.models.llama import Attention, FeedForward, precompute_freqs_cis - -def modulate(x:Tensor, shift:Tensor, scale:Tensor) -> Tensor: return x * (1 + scale.unsqueeze(1)) + shift.unsqueeze(1) - -# TODO: why doesn't the TimestepEmbedder from minRF work? -class TimestepEmbedder: - def __init__(self, hidden_size): self.mlp = [nn.Linear(1, hidden_size), Tensor.silu, nn.Linear(hidden_size, hidden_size)] - def __call__(self, t:Tensor): return t.reshape(-1, 1).sequential(self.mlp) - -class TransformerBlock: - def __init__(self, dim, n_heads, norm_eps=1e-5): - self.attention = Attention(dim, n_heads) - self.feed_forward = FeedForward(dim, 4*dim) - self.attention_norm = nn.LayerNorm(dim, eps=norm_eps) - self.ffn_norm = nn.LayerNorm(dim, eps=norm_eps) - self.adaLN_modulation = nn.Linear(dim, 6 * dim, bias=True) - - def __call__(self, x:Tensor, freqs_cis:Tensor, adaln_input:Tensor): - shift_msa, scale_msa, gate_msa, shift_mlp, scale_mlp, gate_mlp = self.adaLN_modulation(adaln_input.silu()).chunk(6, dim=1) - x = x + gate_msa.unsqueeze(1) * self.attention(modulate(self.attention_norm(x), shift_msa, scale_msa), 0, freqs_cis) - x = x + gate_mlp.unsqueeze(1) * self.feed_forward(modulate(self.ffn_norm(x), shift_mlp, scale_mlp)) - return x.contiguous().contiguous_backward() - -class FinalLayer: - def __init__(self, dim, patch_size, out_channels): - self.norm_final = nn.LayerNorm(dim, elementwise_affine=False, eps=1e-6) - self.linear = nn.Linear(dim, patch_size*patch_size*out_channels, bias=True) - self.adaLN_modulation = nn.Linear(dim, 2 * dim, bias=True) - - # init weights/bias to 0 - self.linear.weight.replace(self.linear.weight.zeros_like().contiguous()) - self.linear.bias.replace(self.linear.bias.zeros_like().contiguous()) - - def __call__(self, x:Tensor, c:Tensor): - shift, scale = self.adaLN_modulation(c.silu()).chunk(2, dim=1) - x = modulate(self.norm_final(x), shift, scale) - return self.linear(x) - -# channels=1, input_size=32, dim=64, n_layers=6, n_heads=4, num_classes=10 -class DiT_Llama: - def __init__(self, in_channels=1, dim=64, n_layers=6, n_heads=4, num_classes=10, patch_size=2): - self.patch_size = patch_size - self.out_channels = in_channels - self.num_classes = num_classes - - self.init_conv_seq = [ - nn.Conv2d(in_channels, dim // 2, kernel_size=5, padding=2, stride=1), Tensor.silu, nn.GroupNorm(32, dim//2), - nn.Conv2d(dim //2, dim // 2, kernel_size=5, padding=2, stride=1), Tensor.silu, nn.GroupNorm(32, dim//2), - ] - - self.x_embedder = nn.Linear(self.patch_size * self.patch_size * dim // 2, dim, bias=True) - self.t_embedder = TimestepEmbedder(dim) - self.y_embedder = nn.Embedding(num_classes+1, dim) - self.final_layer = FinalLayer(dim, self.patch_size, self.out_channels) - - self.freqs_cis = precompute_freqs_cis(dim // n_heads, 4096) - self.layers = [TransformerBlock(dim, n_heads) for _ in range(n_layers)] - - def unpatchify(self, x:Tensor): - c, p = self.out_channels, self.patch_size - h = w = int(x.shape[1] ** 0.5) - x = x.reshape(shape=(x.shape[0], h, w, p, p, c)) - x = x.rearrange("n h w p q c -> n c h p w q") - return x.reshape(shape=(x.shape[0], c, h * p, h * p)) - - def patchify(self, x:Tensor): - B, C, H, W = x.shape - x = x.reshape(B, C, H // self.patch_size, self.patch_size, W // self.patch_size, self.patch_size) - x = x.permute(0, 2, 4, 1, 3, 5).flatten(-3).flatten(1, 2) - return x # B - - def __call__(self, x:Tensor, t:Tensor, y:Tensor) -> Tensor: - x = x.sequential(self.init_conv_seq) - x = self.patchify(x) - x = self.x_embedder(x) - adaln_input = self.t_embedder(t) + self.y_embedder(y) - adaln_input = adaln_input.contiguous() - for layer in self.layers: - x = layer(x, self.freqs_cis[:, :x.size(1)], adaln_input=adaln_input) - x = self.final_layer(x, adaln_input) - return self.unpatchify(x) - - def rf(self, x:Tensor, cond:Tensor): - b = x.shape[0] - # self.ln is True - t = Tensor.randn((b,)).sigmoid() - texp = t.view([b, *([1] * len(x.shape[1:]))]) - - # conditional dropout - dropout_prob = 0.1 - cond = (Tensor.rand(cond.shape[0]) < dropout_prob).where(cond.full_like(self.num_classes), cond) - - # this is rectified flow - z1 = x.randn_like() - zt = (1 - texp) * x + texp * z1 - vtheta = self(zt, t, cond) - - # MSE loss - return ((z1 - x) - vtheta).square().mean() - - def sample(self, z, cond, null_cond, sample_steps=50, cfg=2.0): - b = z.size(0) - dt = Tensor.full((b,)+(1,)*len(z.shape[1:]), fill_value=1.0/sample_steps).contiguous() - images = [z] - for i in range(sample_steps, 0, -1): - t = Tensor.full((b,), fill_value=i/sample_steps).contiguous() - vc = self(z, t, cond) - vu = self(z, t, null_cond) - vc = vu + cfg * (vc - vu) - z = z - dt * vc - z = z.contiguous() - images.append(z) - return images - -def mviz(t:Tensor): - assert len(t.shape) == 4 and t.shape[1] == 1 - ft = t.permute(1,2,0,3).reshape(32, -1) - assert ft.shape[-1]%32 == 0 - print("") - for y in ((ft+1)/2).clamp(0,1).tolist(): - ln = [f"\033[38;5;{232+int(x*23)}m██" for x in y] - print(''.join(ln) + "\033[0m") - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = nn.datasets.mnist() - X_train = X_train.pad((2,2,2,2)) - X_train = ((X_train.float()/255)-0.5)/0.5 - Y_train = Y_train.int() - - model = DiT_Llama(patch_size=getenv("PATCH_SIZE", 2)) - for r in nn.state.get_parameters(model): r.realize() - optimizer = nn.optim.Adam(nn.state.get_parameters(model), lr=5e-4) - - @TinyJit - @Tensor.train() - def train_step(): - if getenv("OVERFIT"): samples = Tensor.zeros(getenv("BS", 256), dtype='int') - else: samples = Tensor.randint(getenv("BS", 256), high=X_train.shape[0]) - optimizer.zero_grad() - loss = model.rf(X_train[samples], Y_train[samples]) - loss.backward() - optimizer.step() - return loss - - @TinyJit - def sample(z:Tensor, cond:Tensor) -> Tensor: - return model.sample(z, cond, Tensor.full_like(cond, 10), sample_steps=getenv("SAMPLE_STEPS", 20))[-1] - - for steps in (t:=trange(getenv("STEPS", 5000))): - if steps%10 == 0: mviz(sample(Tensor.randn(3, 1, 32, 32), Tensor([5,0,4], dtype='int'))) - GlobalCounters.reset() - loss = train_step() - t.set_description(f"loss: {loss.item():9.2f}") diff --git a/tinygrad/examples/mixtral.py b/tinygrad/examples/mixtral.py deleted file mode 100644 index c621d409..00000000 --- a/tinygrad/examples/mixtral.py +++ /dev/null @@ -1,62 +0,0 @@ -import functools, argparse, pathlib -from tinygrad import Tensor, nn, Device, GlobalCounters, Variable -from tinygrad.helpers import Timing, Profiling, CI, tqdm -from tinygrad.nn.state import torch_load, get_state_dict -from extra.models.llama import FeedForward, Transformer -from extra.bench_log import BenchEvent, WallTimeEvent - -class MixtureFeedForward: - def __init__(self, num_experts:int, dim:int, hidden_dim:int, linear=nn.Linear): - self.gate = nn.Linear(dim, num_experts, bias=False) - self.experts = [FeedForward(dim, hidden_dim, linear) for _ in range(num_experts)] - def __call__(self, x:Tensor) -> Tensor: - assert x.shape[0] == 1, "only BS=1" - g = self.gate(x).float().exp() - choice = g.data().tolist()[0][0] - top = sorted(enumerate(choice), key=lambda x: -x[1]) - norm = top[0][1] + top[1][1] - e1, e2 = self.experts[top[0][0]], self.experts[top[1][0]] - scale = Tensor([top[0][1]/norm, top[1][1]/norm]) - ret = e1(x.to(e1.w1.weight.device)).to(x.device) * scale[0] + \ - e2(x.to(e2.w1.weight.device)).to(x.device) * scale[1] - return ret - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Run Mixtral in tinygrad", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--count", type=int, default=30, help="Max number of tokens to generate") - parser.add_argument("--temperature", type=float, default=0.7, help="Temperature in the softmax") - parser.add_argument("--timing", action="store_true", help="Print timing per token") - parser.add_argument("--profile", action="store_true", help="Profile generation") - parser.add_argument("--weights", type=str, default=(pathlib.Path(__file__).parent.parent / "weights/mixtral-8x7b-32kseqlen").as_posix(), - help="Path to the downloaded weights") - args = parser.parse_args() - - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - state = torch_load(args.weights + "/consolidated.00.pth.b") - model = Transformer(n_layers=32, dim=4096, hidden_dim=14336, n_heads=32, n_kv_heads=8, norm_eps=1e-5, vocab_size=32000, feed_forward=functools.partial(MixtureFeedForward, 8), jit=False) - model_state_dict = get_state_dict(model) - - for k in (t := tqdm(state, disable=CI)): - if 'feed_forward.experts.' in k: - expert_no = int(k.split('feed_forward.experts.')[1].split('.')[0]) - device = Device.DEFAULT + ":" + str((expert_no//2)+1) - else: - device = Device.DEFAULT - t.set_description(f"ram used: {GlobalCounters.mem_used/1e9:5.2f} GB, loading {k} to {device}") - model_state_dict[k].replace(state[k].to(device).half()).realize() - if CI: print(f"ram used: {GlobalCounters.mem_used/1e9:5.2f} GB") - - from sentencepiece import SentencePieceProcessor - spp = SentencePieceProcessor(model_file=args.weights + "/tokenizer.model") - - toks = [spp.bos_id()] - start_pos = 0 - for i in range(args.count): - GlobalCounters.reset() - with Profiling(sort="time", frac=0.1, enabled=args.profile): - with Timing("total ", enabled=args.timing, on_exit=lambda x: f", {1e9/x:.2f} tok/sec"): - with WallTimeEvent(BenchEvent.STEP): - tok = model(Tensor([toks[start_pos:]]), 0 if start_pos == 0 else Variable("start_pos", 1, 1024-1).bind(start_pos), args.temperature).item() - toks.append(tok) - start_pos += 1 - print(spp.decode(toks)) diff --git a/tinygrad/examples/mlperf/README b/tinygrad/examples/mlperf/README deleted file mode 100644 index d971e0c5..00000000 --- a/tinygrad/examples/mlperf/README +++ /dev/null @@ -1,19 +0,0 @@ -Each model should be a clean single file. -They are imported from the top level `models` directory - -It should be capable of loading weights from the reference imp. - -We will focus on these 5 models: - -# Resnet50-v1.5 (classic) -- 8.2 GOPS/input -# Retinanet -# 3D UNET (upconvs) -# RNNT -# BERT-large (transformer) - -They are used in both the training and inference benchmark: -https://mlcommons.org/en/training-normal-21/ -https://mlcommons.org/en/inference-edge-30/ -And we will submit to both. - -NOTE: we are Edge since we don't have ECC RAM diff --git a/tinygrad/examples/mlperf/dataloader.py b/tinygrad/examples/mlperf/dataloader.py deleted file mode 100644 index c01ab48a..00000000 --- a/tinygrad/examples/mlperf/dataloader.py +++ /dev/null @@ -1,543 +0,0 @@ -import os, random, pickle, queue -from typing import List -from pathlib import Path -from multiprocessing import Queue, Process, shared_memory, connection, Lock, cpu_count - -import numpy as np -from tinygrad import dtypes, Tensor -from tinygrad.helpers import getenv, prod, Context, round_up, tqdm, OSX - -### ResNet - -class MyQueue: - def __init__(self, multiple_readers=True, multiple_writers=True): - self._reader, self._writer = connection.Pipe(duplex=False) - self._rlock = Lock() if multiple_readers else None - self._wlock = Lock() if multiple_writers else None - def get(self): - if self._rlock: self._rlock.acquire() - ret = pickle.loads(self._reader.recv_bytes()) - if self._rlock: self._rlock.release() - return ret - def put(self, obj): - if self._wlock: self._wlock.acquire() - self._writer.send_bytes(pickle.dumps(obj)) - if self._wlock: self._wlock.release() - -def shuffled_indices(n, seed=None): - rng = random.Random(seed) - indices = {} - for i in range(n-1, -1, -1): - j = rng.randint(0, i) - if i not in indices: indices[i] = i - if j not in indices: indices[j] = j - indices[i], indices[j] = indices[j], indices[i] - yield indices[i] - del indices[i] - -def loader_process(q_in, q_out, X:Tensor, seed): - import signal - signal.signal(signal.SIGINT, lambda _, __: exit(0)) - - from extra.datasets.imagenet import center_crop, preprocess_train - from PIL import Image - - with Context(DEBUG=0): - while (_recv := q_in.get()) is not None: - idx, fn, val = _recv - if fn is not None: - img = Image.open(fn) - img = img.convert('RGB') if img.mode != "RGB" else img - - if val: - # eval: 76.08%, load in 0m7.366s (0m5.301s with simd) - # sudo apt-get install libjpeg-dev - # CC="cc -mavx2" pip install -U --force-reinstall pillow-simd - img = center_crop(img) - img = np.array(img) - else: - # reseed rng for determinism - if seed is not None: - np.random.seed(seed * 2 ** 10 + idx) - random.seed(seed * 2 ** 10 + idx) - img = preprocess_train(img) - else: - # pad data with training mean - img = np.tile(np.array([[[123.68, 116.78, 103.94]]], dtype=np.uint8), (224, 224, 1)) - - # broken out - #img_tensor = Tensor(img.tobytes(), device='CPU') - #storage_tensor = X[idx].contiguous().realize().lazydata.base.realized - #storage_tensor._copyin(img_tensor.numpy()) - - # faster - X[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = img.tobytes() - - # ideal - #X[idx].assign(img.tobytes()) # NOTE: this is slow! - q_out.put(idx) - q_out.put(None) - -def batch_load_resnet(batch_size=64, val=False, shuffle=True, seed=None, pad_first_batch=False): - from extra.datasets.imagenet import get_train_files, get_val_files - files = get_val_files() if val else get_train_files() - from extra.datasets.imagenet import get_imagenet_categories - cir = get_imagenet_categories() - - if pad_first_batch: - FIRST_BATCH_PAD = round_up(len(files), batch_size) - len(files) - else: - FIRST_BATCH_PAD = 0 - file_count = FIRST_BATCH_PAD + len(files) - BATCH_COUNT = min(32, file_count // batch_size) - - def _gen(): - for _ in range(FIRST_BATCH_PAD): yield -1 - yield from shuffled_indices(len(files), seed=seed) if shuffle else iter(range(len(files))) - gen = iter(_gen()) - - def enqueue_batch(num): - for idx in range(num*batch_size, (num+1)*batch_size): - fidx = next(gen) - if fidx != -1: - fn = files[fidx] - q_in.put((idx, fn, val)) - Y[idx] = cir[fn.split("/")[-2]] - else: - # padding - q_in.put((idx, None, val)) - Y[idx] = -1 - - shutdown = False - class Cookie: - def __init__(self, num): self.num = num - def __del__(self): - if not shutdown: - try: enqueue_batch(self.num) - except StopIteration: pass - - gotten = [0]*BATCH_COUNT - def receive_batch(): - while 1: - num = q_out.get()//batch_size - gotten[num] += 1 - if gotten[num] == batch_size: break - gotten[num] = 0 - return X[num*batch_size:(num+1)*batch_size], Y[num*batch_size:(num+1)*batch_size], Cookie(num) - - #q_in, q_out = MyQueue(multiple_writers=False), MyQueue(multiple_readers=False) - q_in, q_out = Queue(), Queue() - - sz = (batch_size*BATCH_COUNT, 224, 224, 3) - shm_name = "resnet_X_val" if val else "resnet_X_train" - if not OSX and os.path.exists(f"/dev/shm/{shm_name}"): os.unlink(f"/dev/shm/{shm_name}") - shm = shared_memory.SharedMemory(name=shm_name, create=True, size=prod(sz)) - procs = [] - - try: - # disk:shm is slower - if OSX: X = Tensor.empty(*sz, dtype=dtypes.uint8, device=f"disk:shm:{shm.name}") - else: X = Tensor.empty(*sz, dtype=dtypes.uint8, device=f"disk:/dev/shm/{shm_name}") - Y = [None] * (batch_size*BATCH_COUNT) - - for _ in range(cpu_count()): - p = Process(target=loader_process, args=(q_in, q_out, X, seed)) - p.daemon = True - p.start() - procs.append(p) - - for bn in range(BATCH_COUNT): enqueue_batch(bn) - - # NOTE: this is batch aligned, last ones are ignored unless pad_first_batch is True - for _ in range(0, file_count//batch_size): yield receive_batch() - finally: - shutdown = True - # empty queues - for _ in procs: q_in.put(None) - q_in.close() - for _ in procs: - while q_out.get() is not None: pass - q_out.close() - # shutdown processes - for p in procs: p.join() - shm.close() - try: - shm.unlink() - except FileNotFoundError: - # happens with BENCHMARK set - pass - -### BERT - -def process_batch_bert(data: List[dict]) -> dict[str, Tensor]: - return { - "input_ids": Tensor(np.concatenate([s["input_ids"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - "input_mask": Tensor(np.concatenate([s["input_mask"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - "segment_ids": Tensor(np.concatenate([s["segment_ids"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - "masked_lm_positions": Tensor(np.concatenate([s["masked_lm_positions"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - "masked_lm_ids": Tensor(np.concatenate([s["masked_lm_ids"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - "masked_lm_weights": Tensor(np.concatenate([s["masked_lm_weights"] for s in data], axis=0), dtype=dtypes.float32, device="CPU"), - "next_sentence_labels": Tensor(np.concatenate([s["next_sentence_labels"] for s in data], axis=0), dtype=dtypes.int32, device="CPU"), - } - -def load_file(file: str): - with open(file, "rb") as f: - return pickle.load(f) - -class InterleavedDataset: - def __init__(self, files:List[str], cycle_length:int): - self.dataset = files - self.cycle_length = cycle_length - self.queues = [queue.Queue() for _ in range(self.cycle_length)] - for i in range(len(self.queues)): self.queues[i].queue.extend(load_file(self.dataset.pop(0))) - self.queue_pointer = len(self.queues) - 1 - - def get(self): - # Round-robin across queues - try: - self.advance() - return self.queues[self.queue_pointer].get_nowait() - except queue.Empty: - self.fill(self.queue_pointer) - return self.get() - - def advance(self): - self.queue_pointer = (self.queue_pointer + 1) % self.cycle_length - - def fill(self, queue_index: int): - try: - file = self.dataset.pop(0) - except IndexError: - return - self.queues[queue_index].queue.extend(load_file(file)) - -# Reference: https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/run_pretraining.py, Line 394 -def batch_load_train_bert(BS:int): - from extra.datasets.wikipedia import get_wiki_train_files - fs = sorted(get_wiki_train_files()) - train_files = [] - while fs: # TF shuffle - random.shuffle(fs) - train_files.append(fs.pop(0)) - - cycle_length = min(getenv("NUM_CPU_THREADS", min(os.cpu_count(), 8)), len(train_files)) - assert cycle_length > 0, "cycle_length must be greater than 0" - - dataset = InterleavedDataset(train_files, cycle_length) - while True: - yield process_batch_bert([dataset.get() for _ in range(BS)]) - -# Reference: https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/run_pretraining.py, Line 416 -def batch_load_val_bert(BS:int): - file = getenv("BASEDIR", Path(__file__).parent.parents[1] / "extra" / "datasets" / "wiki") / "eval.pkl" - dataset = load_file(file) - idx = 0 - while True: - start_idx = (idx * BS) % len(dataset) - end_idx = ((idx + 1) * BS) % len(dataset) - if start_idx < end_idx: - yield process_batch_bert(dataset[start_idx:end_idx]) - else: # wrap around the end to the beginning of the dataset - yield process_batch_bert(dataset[start_idx:] + dataset[:end_idx]) - idx += 1 - -### UNET3D - -def load_unet3d_data(preprocessed_dataset_dir, seed, queue_in, queue_out, X:Tensor, Y:Tensor): - from extra.datasets.kits19 import rand_balanced_crop, rand_flip, random_brightness_augmentation, gaussian_noise - - while (data := queue_in.get()) is not None: - idx, fn, val = data - case_name = os.path.basename(fn).split("_x.npy")[0] - x, y = np.load(preprocessed_dataset_dir / f"{case_name}_x.npy"), np.load(preprocessed_dataset_dir / f"{case_name}_y.npy") - - if not val: - if seed is not None: - np.random.seed(seed) - random.seed(seed) - - x, y = rand_balanced_crop(x, y) - x, y = rand_flip(x, y) - x, y = x.astype(np.float32), y.astype(np.uint8) - x = random_brightness_augmentation(x) - x = gaussian_noise(x) - - X[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = x.tobytes() - Y[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = y.tobytes() - - queue_out.put(idx) - queue_out.put(None) - -def batch_load_unet3d(preprocessed_dataset_dir:Path, batch_size:int=6, val:bool=False, shuffle:bool=True, seed=None): - assert preprocessed_dataset_dir is not None, "run preprocess_data on kits19" - - files = sorted(list(preprocessed_dataset_dir.glob("*_x.npy"))) - file_indices = list(range(len(files))) - batch_count = min(32, len(files) // batch_size) - - queue_in, queue_out = Queue(), Queue() - procs, data_out_count = [], [0] * batch_count - shm_name_x, shm_name_y = "unet3d_x", "unet3d_y" - sz = (batch_size * batch_count, 1, 128, 128, 128) - if os.path.exists(f"/dev/shm/{shm_name_x}"): os.unlink(f"/dev/shm/{shm_name_x}") - if os.path.exists(f"/dev/shm/{shm_name_y}"): os.unlink(f"/dev/shm/{shm_name_y}") - shm_x = shared_memory.SharedMemory(name=shm_name_x, create=True, size=prod(sz)) - shm_y = shared_memory.SharedMemory(name=shm_name_y, create=True, size=prod(sz)) - - shutdown = False - class Cookie: - def __init__(self, bc): - self.bc = bc - def __del__(self): - if not shutdown: - try: enqueue_batch(self.bc) - except StopIteration: pass - - def enqueue_batch(bc): - for idx in range(bc * batch_size, (bc+1) * batch_size): - fn = files[next(ds_iter)] - queue_in.put((idx, fn, val)) - - def shuffle_indices(file_indices, seed=None): - rng = random.Random(seed) - rng.shuffle(file_indices) - - if shuffle: shuffle_indices(file_indices, seed=seed) - ds_iter = iter(file_indices) - - try: - X = Tensor.empty(*sz, dtype=dtypes.float32, device=f"disk:/dev/shm/{shm_name_x}") - Y = Tensor.empty(*sz, dtype=dtypes.uint8, device=f"disk:/dev/shm/{shm_name_y}") - - for _ in range(cpu_count()): - proc = Process(target=load_unet3d_data, args=(preprocessed_dataset_dir, seed, queue_in, queue_out, X, Y)) - proc.daemon = True - proc.start() - - procs.append(proc) - - for bc in range(batch_count): - enqueue_batch(bc) - - for _ in range(len(files) // batch_size): - while True: - bc = queue_out.get() // batch_size - data_out_count[bc] += 1 - if data_out_count[bc] == batch_size: break - - data_out_count[bc] = 0 - yield X[bc * batch_size:(bc + 1) * batch_size], Y[bc * batch_size:(bc + 1) * batch_size], Cookie(bc) - finally: - shutdown = True - - for _ in procs: queue_in.put(None) - queue_in.close() - - for _ in procs: - while queue_out.get() is not None: pass - queue_out.close() - - # shutdown processes - for proc in procs: proc.join() - - shm_x.close() - shm_y.close() - try: - shm_x.unlink() - shm_y.unlink() - except FileNotFoundError: - # happens with BENCHMARK set - pass - -### RetinaNet - -def load_retinanet_data(base_dir:Path, val:bool, queue_in:Queue, queue_out:Queue, - imgs:Tensor, boxes:Tensor, labels:Tensor, matches:Tensor|None=None, - anchors:Tensor|None=None, seed:int|None=None): - from extra.datasets.openimages import image_load, random_horizontal_flip, resize - from examples.mlperf.helpers import box_iou, find_matches, generate_anchors - import torch - - while (data:=queue_in.get()) is not None: - idx, img, tgt = data - img = image_load(base_dir, img["subset"], img["file_name"]) - - if val: - img = resize(img)[0] - else: - if seed is not None: - np.random.seed(seed) - random.seed(seed) - torch.manual_seed(seed) - - img, tgt = random_horizontal_flip(img, tgt) - img, tgt, _ = resize(img, tgt=tgt) - match_quality_matrix = box_iou(tgt["boxes"], (anchor := np.concatenate(generate_anchors((800, 800))))) - match_idxs = find_matches(match_quality_matrix, allow_low_quality_matches=True) - clipped_match_idxs = np.clip(match_idxs, 0, None) - clipped_boxes, clipped_labels = tgt["boxes"][clipped_match_idxs], tgt["labels"][clipped_match_idxs] - - boxes[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = clipped_boxes.tobytes() - labels[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = clipped_labels.tobytes() - matches[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = match_idxs.tobytes() - anchors[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = anchor.tobytes() - - imgs[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = img.tobytes() - - queue_out.put(idx) - queue_out.put(None) - -def batch_load_retinanet(dataset, val:bool, base_dir:Path, batch_size:int=32, shuffle:bool=True, seed:int|None=None): - def _enqueue_batch(bc): - from extra.datasets.openimages import prepare_target - for idx in range(bc * batch_size, (bc+1) * batch_size): - img = dataset.loadImgs(next(dataset_iter))[0] - ann = dataset.loadAnns(dataset.getAnnIds(img_id:=img["id"])) - tgt = prepare_target(ann, img_id, (img["height"], img["width"])) - - if img_ids is not None: - img_ids[idx] = img_id - - if img_sizes is not None: - img_sizes[idx] = tgt["image_size"] - - queue_in.put((idx, img, tgt)) - - def _setup_shared_mem(shm_name:str, size:tuple[int, ...], dtype:dtypes) -> tuple[shared_memory.SharedMemory, Tensor]: - if os.path.exists(f"/dev/shm/{shm_name}"): os.unlink(f"/dev/shm/{shm_name}") - shm = shared_memory.SharedMemory(name=shm_name, create=True, size=prod(size)) - shm_tensor = Tensor.empty(*size, dtype=dtype, device=f"disk:/dev/shm/{shm_name}") - return shm, shm_tensor - - image_ids = sorted(dataset.imgs.keys()) - batch_count = min(32, len(image_ids) // batch_size) - - queue_in, queue_out = Queue(), Queue() - procs, data_out_count = [], [0] * batch_count - - shm_imgs, imgs = _setup_shared_mem("retinanet_imgs", (batch_size * batch_count, 800, 800, 3), dtypes.uint8) - - if val: - boxes, labels, matches, anchors = None, None, None, None - img_ids, img_sizes = [None] * (batch_size * batch_count), [None] * (batch_size * batch_count) - else: - img_ids, img_sizes = None, None - shm_boxes, boxes = _setup_shared_mem("retinanet_boxes", (batch_size * batch_count, 120087, 4), dtypes.float32) - shm_labels, labels = _setup_shared_mem("retinanet_labels", (batch_size * batch_count, 120087), dtypes.int64) - shm_matches, matches = _setup_shared_mem("retinanet_matches", (batch_size * batch_count, 120087), dtypes.int64) - shm_anchors, anchors = _setup_shared_mem("retinanet_anchors", (batch_size * batch_count, 120087, 4), dtypes.float64) - - shutdown = False - class Cookie: - def __init__(self, bc): - self.bc = bc - def __del__(self): - if not shutdown: - try: _enqueue_batch(self.bc) - except StopIteration: pass - - def shuffle_indices(indices, seed): - rng = random.Random(seed) - rng.shuffle(indices) - - if shuffle: shuffle_indices(image_ids, seed=seed) - dataset_iter = iter(image_ids) - - try: - for _ in range(cpu_count()): - proc = Process( - target=load_retinanet_data, - args=(base_dir, val, queue_in, queue_out, imgs, boxes, labels), - kwargs={"matches": matches, "anchors": anchors, "seed": seed} - ) - proc.daemon = True - proc.start() - procs.append(proc) - - for bc in range(batch_count): - _enqueue_batch(bc) - - for _ in range(len(image_ids) // batch_size): - while True: - bc = queue_out.get() // batch_size - data_out_count[bc] += 1 - if data_out_count[bc] == batch_size: break - - data_out_count[bc] = 0 - - if val: - yield (imgs[bc * batch_size:(bc + 1) * batch_size], - img_ids[bc * batch_size:(bc + 1) * batch_size], - img_sizes[bc * batch_size:(bc + 1) * batch_size], - Cookie(bc)) - else: - yield (imgs[bc * batch_size:(bc + 1) * batch_size], - boxes[bc * batch_size:(bc + 1) * batch_size], - labels[bc * batch_size:(bc + 1) * batch_size], - matches[bc * batch_size:(bc + 1) * batch_size], - anchors[bc * batch_size:(bc + 1) * batch_size], - Cookie(bc)) - finally: - shutdown = True - - for _ in procs: queue_in.put(None) - queue_in.close() - - for _ in procs: - while queue_out.get() is not None: pass - queue_out.close() - - # shutdown processes - for proc in procs: proc.join() - - shm_imgs.close() - - if not val: - shm_boxes.close() - shm_labels.close() - shm_matches.close() - shm_anchors.close() - - try: - shm_imgs.unlink() - - if not val: - shm_boxes.unlink() - shm_labels.unlink() - shm_matches.unlink() - shm_anchors.unlink() - except FileNotFoundError: - # happens with BENCHMARK set - pass - -if __name__ == "__main__": - def load_unet3d(val): - assert not val, "validation set is not supported due to different sizes on inputs" - - from extra.datasets.kits19 import get_train_files, get_val_files, preprocess_dataset, TRAIN_PREPROCESSED_DIR, VAL_PREPROCESSED_DIR - preprocessed_dir = VAL_PREPROCESSED_DIR if val else TRAIN_PREPROCESSED_DIR - files = get_val_files() if val else get_train_files() - - if not preprocessed_dir.exists(): preprocess_dataset(files, preprocessed_dir, val) - with tqdm(total=len(files)) as pbar: - for x, _, _ in batch_load_unet3d(preprocessed_dir, val=val): - pbar.update(x.shape[0]) - - def load_resnet(val): - from extra.datasets.imagenet import get_train_files, get_val_files - files = get_val_files() if val else get_train_files() - with tqdm(total=len(files)) as pbar: - for x,y,c in batch_load_resnet(val=val): - pbar.update(x.shape[0]) - - def load_retinanet(val): - from extra.datasets.openimages import BASEDIR, download_dataset - from pycocotools.coco import COCO - dataset = COCO(download_dataset(base_dir:=getenv("BASEDIR", BASEDIR), "validation" if val else "train")) - with tqdm(total=len(dataset.imgs.keys())) as pbar: - for x in batch_load_retinanet(dataset, val, base_dir): - pbar.update(x[0].shape[0]) - - load_fn_name = f"load_{getenv('MODEL', 'resnet')}" - if load_fn_name in globals(): - globals()[load_fn_name](getenv("VAL", 1)) diff --git a/tinygrad/examples/mlperf/helpers.py b/tinygrad/examples/mlperf/helpers.py deleted file mode 100644 index f660f148..00000000 --- a/tinygrad/examples/mlperf/helpers.py +++ /dev/null @@ -1,356 +0,0 @@ -from collections import OrderedDict -import unicodedata -from typing import Optional -import math -import numpy as np -from tinygrad.nn import state -from tinygrad.tensor import Tensor, dtypes -from tinygrad.helpers import getenv - -# -# checkpointing utils -# - -def invert_dict(d): return {v: k for k, v in reversed(d.items())} -def dedup_dict(d): return invert_dict(invert_dict(d)) -# store each tensor into the first key it appears in -def get_training_state(model, optimizer, scheduler): - # hack: let get_state_dict walk the tree starting with model, so that the checkpoint keys are - # readable and can be loaded as a model for eval - train_state = {'model': model, 'optimizer': optimizer, 'scheduler': scheduler} - return dedup_dict(state.get_state_dict(train_state)) -def load_training_state(model, optimizer, scheduler, state_dict): - # use fresh model to restore duplicate keys - train_state = {'model': model, 'optimizer': optimizer, 'scheduler': scheduler} - big_dict = state.get_state_dict(train_state) - # hack: put back the dupes - dupe_names = {} - for k, v in big_dict.items(): - if v not in dupe_names: - dupe_names[v] = k - assert k in state_dict - state_dict[k] = state_dict[dupe_names[v]] - # scheduler contains optimizer and all params, load each weight only once - scheduler_state = {'scheduler': scheduler} - state.load_state_dict(scheduler_state, state_dict) - -def gaussian_kernel(n, std): - from scipy import signal - gaussian_1d = signal.windows.gaussian(n, std) - gaussian_2d = np.outer(gaussian_1d, gaussian_1d) - gaussian_3d = np.outer(gaussian_2d, gaussian_1d) - gaussian_3d = gaussian_3d.reshape(n, n, n) - gaussian_3d = np.cbrt(gaussian_3d) - gaussian_3d /= gaussian_3d.max() - return gaussian_3d - -def prepare_arrays(image, roi_shape=(128, 128, 128)): - assert len(roi_shape) == 3 and any(roi_shape) - image_shape = list(image.shape[2:]) - result = np.zeros((1, 3, *image_shape), dtype=image.dtype) - norm_map = np.zeros_like(result) - norm_patch = gaussian_kernel(roi_shape[0], 0.125 * roi_shape[0]).astype(norm_map.dtype) - return result, norm_map, norm_patch - -def get_slice(image, roi_shape=(128, 128, 128), overlap_factor=0.5): - assert len(roi_shape) == 3 and any(roi_shape) - assert 0 < overlap_factor < 1 - image_shape, dim = list(image.shape[2:]), len(image.shape[2:]) - strides = [int(roi_shape[i] * (1 - overlap_factor)) for i in range(dim)] - size = [(image_shape[i] - roi_shape[i]) // strides[i] + 1 for i in range(dim)] - for i in range(0, strides[0] * size[0], strides[0]): - for j in range(0, strides[1] * size[1], strides[1]): - for k in range(0, strides[2] * size[2], strides[2]): - yield i, j, k - -def _get_best_indices(logits, n_best_size): - index_and_score = sorted(enumerate(logits), key=lambda x: x[1], reverse=True) - return list(map(lambda x: x[0], index_and_score))[:n_best_size] - -def _is_punctuation(char): - if (cp := ord(char)) in range(33, 48) or cp in range(58, 65) or cp in range(91, 97) or cp in range(123, 127): - return True - return unicodedata.category(char).startswith("P") - -def _is_whitespace(char): - if char == " " or char == "\t" or char == "\n" or char == "\r": - return True - return unicodedata.category(char) == "Zs" - -def _is_control(char): - if char == "\t" or char == "\n" or char == "\r": - return False - return unicodedata.category(char).startswith("C") - -def _run_split_on_punc(text): - if text in ("[UNK]", "[SEP]", "[PAD]", "[CLS]", "[MASK]"): - return [text] - start_new_word = True - output = [] - for i in range(len(text)): - if _is_punctuation(char := text[i]): - output.append([char]) - start_new_word = True - else: - if start_new_word: - output.append([]) - start_new_word = False - output[-1].append(char) - return ["".join(x) for x in output] - -def _run_strip_accents(text): - output = [] - for char in unicodedata.normalize("NFD", text): - if unicodedata.category(char) != "Mn": - output.append(char) - return "".join(output) - -def _clean_text(text): - output = [] - for char in text: - if not ((cp := ord(char)) == 0 or cp == 0xfffd or _is_control(char)): - output.append(" " if _is_whitespace(char) else char) - return "".join(output) - -def _get_final_text(pred_text, orig_text): - def _strip_spaces(text): - ns_text = "" - ns_to_s_map = OrderedDict() - for i, c in enumerate(text): - if c == " ": - continue - ns_to_s_map[len(ns_text)] = i - ns_text += c - return ns_text, ns_to_s_map - - orig_tokens = _clean_text(orig_text).strip().split() - split_tokens = [] - for token in orig_tokens: - if token not in ("[UNK]", "[SEP]", "[PAD]", "[CLS]", "[MASK]"): - token = token.lower() - token = _run_strip_accents(token) - split_tokens.extend(_run_split_on_punc(token)) - - tok_text = " ".join(" ".join(split_tokens).strip().split()) - start_position = tok_text.find(pred_text) - if start_position == -1: - return orig_text - end_position = start_position + len(pred_text) - 1 - - orig_ns_text, orig_ns_to_s_map = _strip_spaces(orig_text) - tok_ns_text, tok_ns_to_s_map = _strip_spaces(tok_text) - if len(orig_ns_text) != len(tok_ns_text): - return orig_text - tok_s_to_ns_map = {v: k for k, v in tok_ns_to_s_map.items()} - - orig_start_position = None - if start_position in tok_s_to_ns_map: - if (ns_start_position := tok_s_to_ns_map[start_position]) in orig_ns_to_s_map: - orig_start_position = orig_ns_to_s_map[ns_start_position] - if orig_start_position is None: - return orig_text - - orig_end_position = None - if end_position in tok_s_to_ns_map: - if (ns_end_position := tok_s_to_ns_map[end_position]) in orig_ns_to_s_map: - orig_end_position = orig_ns_to_s_map[ns_end_position] - if orig_end_position is None: - return orig_text - - output_text = orig_text[orig_start_position:(orig_end_position + 1)] - return output_text - -def get_bert_qa_prediction(features, example, start_end_logits): - prelim_predictions = [] - for i, feature in enumerate(features): - for start_index in _get_best_indices(start_end_logits[i][0], 20): - for end_index in _get_best_indices(start_end_logits[i][1], 20): - if start_index >= len(feature["tokens"]) or end_index >= len(feature["tokens"]): - continue - if start_index not in feature["token_to_orig_map"] or end_index not in feature["token_to_orig_map"]: - continue - if not feature["token_is_max_context"].get(start_index, False): - continue - if end_index < start_index or end_index - start_index + 1 > 30: - continue - - prelim_predictions.append({ - "feature_index": i, - "start_index": start_index, - "end_index": end_index, - "start_logit": start_end_logits[i][0, start_index], - "end_logit": start_end_logits[i][1, end_index] - }) - predictions = sorted(prelim_predictions, key=lambda x: (x["start_logit"] + x["end_logit"]), reverse=True) - - if len(predictions) > 0: - feature = features[predictions[0]["feature_index"]] - tok_tokens = feature["tokens"][predictions[0]["start_index"]:(predictions[0]["end_index"] + 1)] - orig_doc_start = feature["token_to_orig_map"][predictions[0]["start_index"]] - orig_doc_end = feature["token_to_orig_map"][predictions[0]["end_index"]] - orig_tokens = example["context"][orig_doc_start:(orig_doc_end + 1)] - tok_text = " ".join(tok_tokens).replace(" ##", "").replace("##", "") - tok_text = " ".join(tok_text.strip().split()) - orig_text = " ".join(orig_tokens) - return _get_final_text(tok_text, orig_text) - return "empty" - -def get_mlperf_bert_config(): - """benchmark is BERT-large""" - ret = {"attention_probs_dropout_prob": 0.1, "hidden_dropout_prob": 0.1, "vocab_size": 30522, "type_vocab_size": 2, "max_position_embeddings": 512} - - match (bert_size:=getenv("BERT_SIZE", "large")): - case "large": ret.update({"hidden_size": 1024, "intermediate_size": 4096, "num_attention_heads": 16, "num_hidden_layers": 24}) - case "tiny": ret.update({"hidden_size": 128, "intermediate_size": 512, "num_attention_heads": 2, "num_hidden_layers": 2}) - case _: raise RuntimeError(f"unhandled {bert_size=}") - - if (bert_layers:=getenv("BERT_LAYERS")): ret["num_hidden_layers"] = bert_layers - return ret - -def get_mlperf_bert_model(): - from extra.models import bert - from examples.mlperf.initializers import LinearBert, EmbeddingBert, LayerNormBert - - bert.Linear = LinearBert - bert.Embedding = EmbeddingBert - bert.LayerNorm = LayerNormBert - - from extra.models.bert import BertForPretraining - config = get_mlperf_bert_config() - if getenv("DISABLE_DROPOUT", 0): - config["hidden_dropout_prob"] = config["attention_probs_dropout_prob"] = 0.0 - return BertForPretraining(**config) - -def get_fake_data_bert(BS:int): - return { - "input_ids": Tensor.empty((BS, 512), dtype=dtypes.int32, device="CPU"), - "input_mask": Tensor.empty((BS, 512), dtype=dtypes.int32, device="CPU"), - "segment_ids": Tensor.empty((BS, 512), dtype=dtypes.int32, device="CPU"), - "masked_lm_positions": Tensor.empty((BS, 76), dtype=dtypes.int32, device="CPU"), - "masked_lm_ids": Tensor.empty((BS, 76), dtype=dtypes.int32, device="CPU"), - "masked_lm_weights": Tensor.empty((BS, 76), dtype=dtypes.float32, device="CPU"), - "next_sentence_labels": Tensor.empty((BS, 1), dtype=dtypes.int32, device="CPU"), - } - -def find_matches(match_quality_matrix:np.ndarray, high_threshold:float=0.5, low_threshold:float=0.4, allow_low_quality_matches:bool=False) -> np.ndarray: - BELOW_LOW_THRESHOLD, BETWEEN_THRESHOLDS = -1, -2 - - def _set_low_quality_matches_(matches:np.ndarray, all_matches:np.ndarray, match_quality_matrix:np.ndarray): - highest_quality_foreach_gt = np.max(match_quality_matrix, axis=1) - pred_inds_to_update = np.nonzero(match_quality_matrix == highest_quality_foreach_gt[:, None])[1] - matches[pred_inds_to_update] = all_matches[pred_inds_to_update] - - assert low_threshold <= high_threshold - - matched_vals, matches = match_quality_matrix.max(axis=0), match_quality_matrix.argmax(axis=0) - all_matches = np.copy(matches) if allow_low_quality_matches else None - below_low_threshold = matched_vals < low_threshold - between_thresholds = (matched_vals >= low_threshold) & (matched_vals < high_threshold) - matches[below_low_threshold] = BELOW_LOW_THRESHOLD - matches[between_thresholds] = BETWEEN_THRESHOLDS - - if allow_low_quality_matches: - assert all_matches is not None - _set_low_quality_matches_(matches, all_matches, match_quality_matrix) - - return matches - -def box_iou(boxes1:np.ndarray, boxes2:np.ndarray) -> np.ndarray: - def _box_area(boxes:np.ndarray) -> np.ndarray: return (boxes[:, 2] - boxes[:, 0]) * (boxes[:, 3] - boxes[:, 1]) - - def _box_inter_union(boxes1:np.ndarray, boxes2:np.ndarray) -> tuple[np.ndarray, np.ndarray]: - area1, area2 = _box_area(boxes1), _box_area(boxes2) - lt, rb = np.maximum(boxes1[:, None, :2], boxes2[:, :2]), np.minimum(boxes1[:, None, 2:], boxes2[:, 2:]) - wh = np.clip(rb - lt, a_min=0, a_max=None) - inter = wh[:, :, 0] * wh[:, :, 1] - union = area1[:, None] + area2 - inter - return inter, union - - inter, union = _box_inter_union(boxes1, boxes2) - return inter / union - -def generate_anchors(input_size:tuple[int, int], scales:Optional[tuple[Tensor, ...]]=None, aspect_ratios:Optional[tuple[Tensor, ...]]=None) -> list[np.ndarray]: - def _compute_grid_sizes(input_size:tuple[int, int]) -> np.ndarray: - return np.ceil(np.array(input_size)[None, :] / 2 ** np.arange(3, 8)[:, None]) - - scales = tuple((i, int(i * 2 ** (1/3)), int(i * 2 ** (2/3))) for i in 2 ** np.arange(5, 10)) if scales is None else scales - aspect_ratios = ((0.5, 1.0, 2.0),) * len(scales) if aspect_ratios is None else aspect_ratios - aspect_ratios = tuple(ar for ar in aspect_ratios) - grid_sizes = _compute_grid_sizes(input_size) - - assert len(scales) == len(aspect_ratios) == len(grid_sizes), "scales, aspect_ratios, and grid_sizes must have the same length" - - anchors = [] - for s, ar, gs in zip(scales, aspect_ratios, grid_sizes): - s, ar = np.array(s), np.array(ar) - h_ratios = np.sqrt(ar) - w_ratios = 1 / h_ratios - ws = (w_ratios[:, None] * s[None, :]).reshape(-1) - hs = (h_ratios[:, None] * s[None, :]).reshape(-1) - base_anchors = (np.stack([-ws, -hs, ws, hs], axis=1) / 2).round() - stride_h, stride_w = input_size[0] // gs[0], input_size[1] // gs[1] - shifts_x, shifts_y = np.meshgrid(np.arange(gs[1]) * stride_w, np.arange(gs[0]) * stride_h) - shifts_x, shifts_y = shifts_x.reshape(-1), shifts_y.reshape(-1) - shifts = np.stack([shifts_x, shifts_y, shifts_x, shifts_y], axis=1, dtype=np.float32) - anchors.append((shifts[:, None] + base_anchors[None, :]).reshape(-1, 4)) - - return anchors - - -class BoxCoder(object): - def __init__(self, weights, bbox_xform_clip=math.log(1000. / 16), apply_to_remove=True): - self.weights = weights - self.bbox_xform_clip = bbox_xform_clip - self.apply_to_remove = apply_to_remove - - def encode(self, reference_boxes, proposals): - TO_REMOVE = self.apply_to_remove # TODO remove - ex_widths = proposals[..., 2] - proposals[..., 0] + TO_REMOVE - ex_heights = proposals[..., 3] - proposals[..., 1] + TO_REMOVE - ex_ctr_x = proposals[..., 0] + 0.5 * ex_widths - ex_ctr_y = proposals[..., 1] + 0.5 * ex_heights - - gt_widths = reference_boxes[..., 2] - reference_boxes[..., 0] + TO_REMOVE - gt_heights = reference_boxes[..., 3] - reference_boxes[..., 1] + TO_REMOVE - gt_ctr_x = reference_boxes[..., 0] + 0.5 * gt_widths - gt_ctr_y = reference_boxes[..., 1] + 0.5 * gt_heights - - wx, wy, ww, wh = self.weights - targets_dx = wx * (gt_ctr_x - ex_ctr_x) / ex_widths - targets_dy = wy * (gt_ctr_y - ex_ctr_y) / ex_heights - targets_dw = ww * Tensor.log(gt_widths / ex_widths) - targets_dh = wh * Tensor.log(gt_heights / ex_heights) - - targets = Tensor.stack(targets_dx, targets_dy, targets_dw, targets_dh, dim=-1) - return targets - - def decode(self, rel_codes, boxes): - boxes = boxes.cast(rel_codes.dtype) - rel_codes = rel_codes - - TO_REMOVE = self.apply_to_remove # TODO remove - widths = boxes[:, 2] - boxes[:, 0] + TO_REMOVE - heights = boxes[:, 3] - boxes[:, 1] + TO_REMOVE - ctr_x = boxes[:, 0] + 0.5 * widths - ctr_y = boxes[:, 1] + 0.5 * heights - - wx, wy, ww, wh = self.weights - dx = rel_codes[:, 0::4] / wx - dy = rel_codes[:, 1::4] / wy - dw = rel_codes[:, 2::4] / ww - dh = rel_codes[:, 3::4] / wh - - # Prevent sending too large values into Tensor.exp() - dw = dw.clip(min_=dw.min(), max_=self.bbox_xform_clip) - dh = dh.clip(min_=dh.min(), max_=self.bbox_xform_clip) - - pred_ctr_x = dx * widths[:, None] + ctr_x[:, None] - pred_ctr_y = dy * heights[:, None] + ctr_y[:, None] - pred_w = dw.exp() * widths[:, None] - pred_h = dh.exp() * heights[:, None] - x = pred_ctr_x - 0.5 * pred_w - y = pred_ctr_y - 0.5 * pred_h - w = pred_ctr_x + 0.5 * pred_w - 1 - h = pred_ctr_y + 0.5 * pred_h - 1 - pred_boxes = Tensor.stack(x, y, w, h).permute(1,2,0).reshape(rel_codes.shape[0], rel_codes.shape[1]) - return pred_boxes diff --git a/tinygrad/examples/mlperf/initializers.py b/tinygrad/examples/mlperf/initializers.py deleted file mode 100644 index 41554cba..00000000 --- a/tinygrad/examples/mlperf/initializers.py +++ /dev/null @@ -1,129 +0,0 @@ -import math -from typing import Union - -from tinygrad import Tensor, nn, dtypes -from tinygrad.helpers import prod, argfix - -# rejection sampling truncated randn -def rand_truncn(*shape, dtype=None, truncstds=2, **kwargs) -> Tensor: - CNT=8 - x = Tensor.randn(*(*shape, CNT), dtype=dtype, **kwargs) - ctr = Tensor.arange(CNT).reshape((1,) * len(x.shape[:-1]) + (CNT,)).expand(x.shape) - take = (x.abs() <= truncstds).where(ctr, CNT).min(axis=-1, keepdim=True) # set to 0 if no good samples - return (ctr == take).where(x, 0).sum(axis=-1) - -# https://github.com/keras-team/keras/blob/v2.15.0/keras/initializers/initializers.py#L1026-L1065 -def he_normal(*shape, a: float = 0.00, **kwargs) -> Tensor: - std = math.sqrt(2.0 / (1 + a ** 2)) / math.sqrt(prod(argfix(*shape)[1:])) / 0.87962566103423978 - return std * rand_truncn(*shape, **kwargs) - -class Conv2dHeNormal(nn.Conv2d): - def __init__(self, in_channels, out_channels, kernel_size, stride=1, padding=0, dilation=1, groups=1, bias=True): - super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias) - self.in_channels, self.out_channels = in_channels, out_channels # for testing - self.weight = he_normal(out_channels, in_channels//groups, *self.kernel_size, a=0.0, dtype=dtypes.float32) - if bias: self.bias = self.bias.cast(dtypes.float32) - def __call__(self, x: Tensor): - return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None, - padding=self.padding, stride=self.stride, dilation=self.dilation, groups=self.groups) - -class Linear(nn.Linear): - def __init__(self, in_features, out_features, bias=True): - super().__init__(in_features, out_features, bias=bias) - self.weight = Tensor.normal((out_features, in_features), mean=0.0, std=0.01, dtype=dtypes.float32) - if bias: self.bias = Tensor.zeros(out_features, dtype=dtypes.float32) - def __call__(self, x:Tensor): - return x.linear(self.weight.cast(dtypes.default_float).transpose(), self.bias.cast(dtypes.default_float) if self.bias is not None else None) - -class LinearBert(nn.Linear): - def __init__(self, in_features, out_features, bias=True, std=0.02): - self.weight = std * rand_truncn(out_features, in_features, dtype=dtypes.float32) - self.bias = Tensor.zeros(out_features, dtype=dtypes.float32) if bias else None - - def __call__(self, x:Tensor): - return x.cast(dtypes.default_float).linear(self.weight.cast(dtypes.default_float).transpose(), self.bias.cast(dtypes.default_float) if self.bias is not None else None) - -class EmbeddingBert(nn.Embedding): - def __init__(self, vocab_size:int, embed_size:int, std=0.02): - self.vocab_sz, self.embed_sz = vocab_size, embed_size - self.weight = std * rand_truncn(vocab_size, embed_size, dtype=dtypes.float32) - - def __call__(self, idx:Tensor) -> Tensor: - if idx.numel() == 0: return Tensor.empty(idx.shape+(self.embed_sz,), dtype=self.weight.dtype, device=self.weight.device) - arange_shp, weight_shp, big_shp = (1, 1, self.vocab_sz, 1), (1, 1, self.vocab_sz, self.embed_sz), idx.shape+(self.vocab_sz, self.embed_sz,) - if not hasattr(self, 'arange'): self.arange = Tensor.arange(self.vocab_sz, requires_grad=False, device=self.weight.device).reshape(arange_shp) - arange, idx, vals = self.arange.expand(big_shp), idx.reshape(idx.shape+(1, 1,)).expand(big_shp), self.weight.cast(dtypes.default_float).reshape(weight_shp).expand(big_shp) - # TODO: contiguous() here because the embedding dropout creates different asts on each device, and search becomes very slow. - # Should fix with fixing random ast on multi device, and fuse arange to make embedding fast. - return (arange == idx).mul(vals).sum(2, dtype=vals.dtype).contiguous() - -class LayerNormBert: - def __init__(self, normalized_shape:Union[int, tuple[int, ...]], eps:float=1e-12, elementwise_affine:bool=True): - self.normalized_shape = (normalized_shape,) if isinstance(normalized_shape, int) else tuple(normalized_shape) - self.axis, self.eps, self.elementwise_affine = tuple(-1-i for i in range(len(self.normalized_shape))), eps, elementwise_affine - self.weight, self.bias = (Tensor.ones(*self.normalized_shape, dtype=dtypes.float32), Tensor.zeros(*self.normalized_shape, dtype=dtypes.float32)) if elementwise_affine else (None, None) - - def __call__(self, x:Tensor): - assert self.normalized_shape == x.shape[-len(self.normalized_shape):], f"last dimensions of {x.shape} must match {self.normalized_shape}" - xn = x.cast(dtypes.float32).layernorm(eps=self.eps, axis=self.axis).cast(x.dtype) - if not self.elementwise_affine: return xn - return (xn * self.weight.cast(dtypes.default_float) + self.bias.cast(dtypes.default_float)) - -class FrozenBatchNorm2dRetinaNet(nn.BatchNorm2d): - def __init__(self, sz:int, eps=1e-5, affine=True, track_running_stats=True, momentum=0.1): - self.eps, self.track_running_stats, self.momentum = eps, track_running_stats, momentum - - self.weight = Tensor.ones(sz, dtype=dtypes.float32, requires_grad=False) if affine else None - self.bias = Tensor.zeros(sz, dtype=dtypes.float32, requires_grad=False) if affine else None - - if track_running_stats: self.running_mean, self.running_var = Tensor.zeros(sz, dtype=dtypes.float32, requires_grad=False), Tensor.ones(sz, dtype=dtypes.float32, requires_grad=False) - self.num_batches_tracked = Tensor.zeros(1, dtype=dtypes.long, requires_grad=False) - - def __call__(self, x:Tensor) -> Tensor: - batch_mean, batch_var = super().calc_stats(x.cast(dtypes.float32)) - if self.track_running_stats and Tensor.training: - self.running_mean.assign((1-self.momentum) * self.running_mean + self.momentum * batch_mean.detach().cast(self.running_mean.dtype)) - self.running_var.assign((1-self.momentum) * self.running_var + self.momentum * x.numel()/(x.numel()-x.shape[1]) * batch_var.detach().cast(self.running_var.dtype)) - self.num_batches_tracked += 1 - return x.cast(dtypes.float32).batchnorm(self.weight, self.bias, batch_mean, batch_var.add(self.eps).rsqrt()).cast(x.dtype) - -class Conv2dNormalRetinaNet(nn.Conv2d): - def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...], - stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1, - bias:bool=True, prior_prob:float|None=None): - super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias) - self.weight = Tensor.normal(*self.weight.shape, std=0.01, dtype=dtypes.float32) - if bias: - if prior_prob: - prior_prob = Tensor(prior_prob, device=self.bias.device, dtype=dtypes.float32).expand(*self.bias.shape) - self.bias = -(((1 - prior_prob) / prior_prob).log()) - else: self.bias = Tensor.zeros_like(self.bias, dtype=dtypes.float32) - - def __call__(self, x:Tensor) -> Tensor: - return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None, - groups=self.groups, stride=self.stride, padding=self.padding) - -class Conv2dKaimingUniformRetinaNet(nn.Conv2d): - def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...], - stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1, - bias:bool=True): - super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias) - self.weight = Tensor.kaiming_uniform(*self.weight.shape, a=1, dtype=dtypes.float32) - if bias: self.bias = Tensor.zeros_like(self.bias, dtype=dtypes.float32) - - def __call__(self, x:Tensor) -> Tensor: - return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None, - groups=self.groups, stride=self.stride, padding=self.padding) - -class Conv2dRetinaNet(nn.Conv2d): - def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...], - stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1, - bias:bool=True): - super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias) - scale = 1 / math.sqrt(in_channels * prod(self.kernel_size)) - self.weight = Tensor.uniform(out_channels, in_channels//groups, *self.kernel_size, low=-scale, high=scale, dtype=dtypes.float32) - self.bias: Tensor|None = Tensor.uniform(out_channels, low=-scale, high=scale, dtype=dtypes.float32) if bias else None - - def __call__(self, x:Tensor) -> Tensor: - return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None, - groups=self.groups, stride=self.stride, dilation=self.dilation, padding=self.padding) diff --git a/tinygrad/examples/mlperf/losses.py b/tinygrad/examples/mlperf/losses.py deleted file mode 100644 index 7ce047bc..00000000 --- a/tinygrad/examples/mlperf/losses.py +++ /dev/null @@ -1,29 +0,0 @@ -from examples.mlperf.metrics import dice_score -from tinygrad import Tensor - -def dice_ce_loss(pred, tgt): - ce = pred.permute(0, 2, 3, 4, 1).sparse_categorical_crossentropy(tgt.squeeze(1)) - dice = (1.0 - dice_score(pred, tgt, argmax=False, to_one_hot_x=False)).mean() - return (dice + ce) / 2 - -def sigmoid_focal_loss(pred:Tensor, tgt:Tensor, alpha:float=0.25, gamma:float=2.0, reduction:str="none") -> Tensor: - assert reduction in ["mean", "sum", "none"], f"unsupported reduction {reduction}" - p, ce_loss = pred.sigmoid(), pred.binary_crossentropy_logits(tgt, reduction="none") - p_t = p * tgt + (1 - p) * (1 - tgt) - loss = ce_loss * ((1 - p_t) ** gamma) - - if alpha >= 0: - alpha_t = alpha * tgt + (1 - alpha) * (1 - tgt) - loss = loss * alpha_t - - if reduction == "mean": loss = loss.mean() - elif reduction == "sum": loss = loss.sum() - return loss - -def l1_loss(pred:Tensor, tgt:Tensor, reduction:str="none") -> Tensor: - assert reduction in ["mean", "sum", "none"], f"unsupported reduction {reduction}" - loss = (pred - tgt).abs() - - if reduction == "mean": loss = loss.mean() - elif reduction == "sum": loss = loss.sum() - return loss \ No newline at end of file diff --git a/tinygrad/examples/mlperf/lr_schedulers.py b/tinygrad/examples/mlperf/lr_schedulers.py deleted file mode 100644 index 600924f5..00000000 --- a/tinygrad/examples/mlperf/lr_schedulers.py +++ /dev/null @@ -1,22 +0,0 @@ -from tinygrad import Tensor, dtypes -from tinygrad.nn.optim import Optimizer - -from extra.lr_scheduler import LR_Scheduler - -# https://github.com/mlcommons/training/blob/e237206991d10449d9675d95606459a3cb6c21ad/image_classification/tensorflow2/lars_util.py -class PolynomialDecayWithWarmup(LR_Scheduler): - def __init__(self, optimizer: Optimizer, initial_lr, end_lr, train_steps, warmup, power=2): - super().__init__(optimizer) - self.epoch_counter = self.epoch_counter.cast(dtypes.float32) - assert train_steps > 0 and warmup > 0 - self.warmup = min(warmup, train_steps) - self.initial_lr, self.end_lr, self.epochs, self.power = initial_lr, end_lr, train_steps, power - - # set lr for first warmup step - self.optimizer.lr.assign(self.get_lr()).realize() - - def get_lr(self): - # LR is 0 on the first step, matching the reference. - warmup_lr = (self.epoch_counter * (1.0 / self.warmup)) * self.initial_lr - x = (1 - (self.epoch_counter - self.warmup) / (self.epochs - self.warmup + 1)) - return (self.epoch_counter <= self.warmup).where(warmup_lr, (self.initial_lr - self.end_lr) * x ** self.power + self.end_lr).cast(self.optimizer.lr.dtype) diff --git a/tinygrad/examples/mlperf/metrics.py b/tinygrad/examples/mlperf/metrics.py deleted file mode 100644 index 795085c9..00000000 --- a/tinygrad/examples/mlperf/metrics.py +++ /dev/null @@ -1,61 +0,0 @@ -import re -import string -from collections import Counter - -def levenshtein(a, b): - n, m = len(a), len(b) - if n > m: - a, b, n, m = b, a, m, n - - current = list(range(n + 1)) - for i in range(1, m + 1): - previous, current = current, [i] + [0] * n - for j in range(1, n + 1): - add, delete = previous[j] + 1, current[j - 1] + 1 - change = previous[j - 1] - if a[j - 1] != b[i - 1]: - change = change + 1 - current[j] = min(add, delete, change) - - return current[n] - -def word_error_rate(x, y): - scores = words = 0 - for h, r in zip(x, y): - h_list = h.split() - r_list = r.split() - words += len(r_list) - scores += levenshtein(h_list, r_list) - return float(scores) / words, float(scores), words - -def one_hot(x): - return x.one_hot(3).squeeze(1).permute(0, 4, 1, 2, 3) - -def dice_score(prediction, target, channel_axis=1, smooth_nr=1e-6, smooth_dr=1e-6, argmax=True, to_one_hot_x=True): - channel_axis, reduce_axis = 1, tuple(range(2, len(prediction.shape))) - if argmax: prediction = prediction.argmax(axis=channel_axis) - else: prediction = prediction.softmax(axis=channel_axis) - if to_one_hot_x: prediction = one_hot(prediction) - target = one_hot(target) - prediction, target = prediction[:, 1:], target[:, 1:] - assert prediction.shape == target.shape, f"prediction ({prediction.shape}) and target ({target.shape}) shapes do not match" - intersection = (prediction * target).sum(axis=reduce_axis) - target_sum = target.sum(axis=reduce_axis) - prediction_sum = prediction.sum(axis=reduce_axis) - result = (2.0 * intersection + smooth_nr) / (target_sum + prediction_sum + smooth_dr) - return result - -def normalize_string(s): - s = "".join(c for c in s.lower() if c not in string.punctuation) - s = re.sub(r'\b(a|an|the)\b', ' ', s) - return " ".join(s.split()) - -def f1_score(x, y): - xt = normalize_string(x).split() - yt = normalize_string(y).split() - ct = Counter(xt) & Counter(yt) - if (ns := sum(ct.values())) == 0: - return 0.0 - p = ns / len(xt) - r = ns / len(yt) - return 2 * p * r / (p + r) diff --git a/tinygrad/examples/mlperf/model_eval.py b/tinygrad/examples/mlperf/model_eval.py deleted file mode 100644 index fa3ca9d7..00000000 --- a/tinygrad/examples/mlperf/model_eval.py +++ /dev/null @@ -1,253 +0,0 @@ -import time -start = time.perf_counter() -from pathlib import Path -import numpy as np -from tinygrad import Tensor, Device, dtypes, GlobalCounters, TinyJit -from tinygrad.nn.state import get_parameters, load_state_dict, safe_load -from tinygrad.helpers import getenv -from extra.bench_log import BenchEvent, WallTimeEvent -def tlog(x): print(f"{x:25s} @ {time.perf_counter()-start:5.2f}s") - -def eval_resnet(): - with WallTimeEvent(BenchEvent.FULL): - # Resnet50-v1.5 - from extra.models.resnet import ResNet50 - tlog("imports") - GPUS = [f'{Device.DEFAULT}:{i}' for i in range(getenv("GPUS", 6))] - for x in GPUS: Device[x] - tlog("got devices") # NOTE: this is faster with rocm-smi running - - class ResnetRunner: - def __init__(self, device=None): - self.mdl = ResNet50() - for x in get_parameters(self.mdl) if device else []: x.to_(device) - if (fn:=getenv("RESNET_MODEL", "")): load_state_dict(self.mdl, safe_load(fn)) - else: self.mdl.load_from_pretrained() - self.input_mean = Tensor([0.485, 0.456, 0.406], device=device).reshape(1, -1, 1, 1) - self.input_std = Tensor([0.229, 0.224, 0.225], device=device).reshape(1, -1, 1, 1) - def __call__(self, x:Tensor) -> Tensor: - x = x.permute([0,3,1,2]).cast(dtypes.float32) / 255.0 - x -= self.input_mean - x /= self.input_std - return self.mdl(x).log_softmax().argmax(axis=1).realize() - - mdl = TinyJit(ResnetRunner(GPUS)) - tlog("loaded models") - - # evaluation on the mlperf classes of the validation set from imagenet - from examples.mlperf.dataloader import batch_load_resnet - iterator = batch_load_resnet(getenv("BS", 128*6), val=getenv("VAL", 1), shuffle=False, pad_first_batch=True) - def data_get(): - x,y,cookie = next(iterator) - return x.shard(GPUS, axis=0).realize(), y, cookie - n,d = 0,0 - proc = data_get() - tlog("loaded initial data") - st = time.perf_counter() - while proc is not None: - GlobalCounters.reset() - proc = (mdl(proc[0]), proc[1], proc[2]) # this frees the images - run = time.perf_counter() - # load the next data here - try: next_proc = data_get() - except StopIteration: next_proc = None - nd = time.perf_counter() - y = np.array(proc[1]) - proc = (proc[0].numpy() == y) & (y != -1) # this realizes the models and frees the cookies - n += proc.sum() - d += (y != -1).sum() - et = time.perf_counter() - tlog(f"****** {n:5d}/{d:5d} {n*100.0/d:.2f}% -- {(run-st)*1000:7.2f} ms to enqueue, {(et-run)*1000:7.2f} ms to realize ({(nd-run)*1000:7.2f} ms fetching). {(len(proc))/(et-st):8.2f} examples/sec. {GlobalCounters.global_ops*1e-12/(et-st):5.2f} TFLOPS") - st = et - proc, next_proc = next_proc, None - tlog("done") - -def eval_unet3d(): - # UNet3D - from extra.models.unet3d import UNet3D - from extra.datasets.kits19 import iterate, sliding_window_inference, get_val_files - from examples.mlperf.metrics import dice_score - mdl = UNet3D() - mdl.load_from_pretrained() - s = 0 - st = time.perf_counter() - for i, (image, label) in enumerate(iterate(get_val_files()), start=1): - mt = time.perf_counter() - pred, label = sliding_window_inference(mdl, image, label) - et = time.perf_counter() - print(f"{(mt-st)*1000:.2f} ms loading data, {(et-mt)*1000:.2f} ms to run model") - s += dice_score(Tensor(pred), Tensor(label)).mean().item() - print(f"****** {s:.2f}/{i} {s/i:.5f} Mean DICE score") - st = time.perf_counter() - -def eval_retinanet(): - # RetinaNet with ResNeXt50_32X4D - from examples.mlperf.dataloader import batch_load_retinanet - from extra.datasets.openimages import normalize, download_dataset, BASEDIR - from extra.models.resnet import ResNeXt50_32X4D - from extra.models.retinanet import RetinaNet - from pycocotools.coco import COCO - from pycocotools.cocoeval import COCOeval - from contextlib import redirect_stdout - tlog("imports") - - mdl = RetinaNet(ResNeXt50_32X4D()) - mdl.load_from_pretrained() - tlog("loaded models") - - coco = COCO(download_dataset(base_dir:=getenv("BASEDIR", BASEDIR), 'validation')) - coco_eval = COCOeval(coco, iouType="bbox") - coco_evalimgs, evaluated_imgs, ncats, narea = [], [], len(coco_eval.params.catIds), len(coco_eval.params.areaRng) - tlog("loaded dataset") - - iterator = batch_load_retinanet(coco, True, Path(base_dir), getenv("BS", 8), shuffle=False) - def data_get(): - x, img_ids, img_sizes, cookie = next(iterator) - return x.to(Device.DEFAULT).realize(), img_ids, img_sizes, cookie - n = 0 - proc = data_get() - tlog("loaded initial data") - st = time.perf_counter() - while proc is not None: - GlobalCounters.reset() - proc = (mdl(normalize(proc[0])), proc[1], proc[2], proc[3]) - run = time.perf_counter() - # load the next data here - try: next_proc = data_get() - except StopIteration: next_proc = None - nd = time.perf_counter() - predictions, img_ids = mdl.postprocess_detections(proc[0].numpy(), orig_image_sizes=proc[2]), proc[1] - pd = time.perf_counter() - coco_results = [{"image_id": img_ids[i], "category_id": label, "bbox": box.tolist(), "score": score} - for i, prediction in enumerate(predictions) for box, score, label in zip(*prediction.values())] - with redirect_stdout(None): - coco_eval.cocoDt = coco.loadRes(coco_results) - coco_eval.params.imgIds = img_ids - coco_eval.evaluate() - evaluated_imgs.extend(img_ids) - coco_evalimgs.append(np.array(coco_eval.evalImgs).reshape(ncats, narea, len(img_ids))) - n += len(proc[0]) - et = time.perf_counter() - tlog(f"****** {(run-st)*1000:7.2f} ms to enqueue, {(et-run)*1000:7.2f} ms to realize ({(nd-run)*1000:7.2f} ms fetching, {(pd-run)*1000:4.2f} ms postprocess_detections). {(len(proc))/(et-st):8.2f} examples/sec. {GlobalCounters.global_ops*1e-12/(et-st):5.2f} TFLOPS") - st = et - proc, next_proc = next_proc, None - - coco_eval.params.imgIds = evaluated_imgs - coco_eval._paramsEval.imgIds = evaluated_imgs - coco_eval.evalImgs = list(np.concatenate(coco_evalimgs, -1).flatten()) - coco_eval.accumulate() - coco_eval.summarize() - tlog("done") - -def eval_rnnt(): - # RNN-T - from extra.models.rnnt import RNNT - mdl = RNNT() - mdl.load_from_pretrained() - - from extra.datasets.librispeech import iterate - from examples.mlperf.metrics import word_error_rate - - LABELS = [" ", "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", "'"] - - c = 0 - scores = 0 - words = 0 - st = time.perf_counter() - for X, Y in iterate(): - mt = time.perf_counter() - tt = mdl.decode(Tensor(X[0]), Tensor([X[1]])) - et = time.perf_counter() - print(f"{(mt-st)*1000:.2f} ms loading data, {(et-mt)*1000:.2f} ms to run model") - for n, t in enumerate(tt): - tnp = np.array(t) - _, scores_, words_ = word_error_rate(["".join([LABELS[int(tnp[i])] for i in range(tnp.shape[0])])], [Y[n]]) - scores += scores_ - words += words_ - c += len(tt) - print(f"WER: {scores/words}, {words} words, raw scores: {scores}, c: {c}") - st = time.perf_counter() - -def eval_bert(): - # Bert-QA - from extra.models.bert import BertForQuestionAnswering - mdl = BertForQuestionAnswering() - mdl.load_from_pretrained() - - @TinyJit - def run(input_ids, input_mask, segment_ids): - return mdl(input_ids, input_mask, segment_ids).realize() - - from extra.datasets.squad import iterate - from examples.mlperf.helpers import get_bert_qa_prediction - from examples.mlperf.metrics import f1_score - from transformers import BertTokenizer - - tokenizer = BertTokenizer(str(Path(__file__).parents[2] / "extra/weights/bert_vocab.txt")) - - c = 0 - f1 = 0.0 - st = time.perf_counter() - for X, Y in iterate(tokenizer): - mt = time.perf_counter() - outs = [] - for x in X: - outs.append(run(Tensor(x["input_ids"]), Tensor(x["input_mask"]), Tensor(x["segment_ids"])).numpy()) - et = time.perf_counter() - print(f"{(mt-st)*1000:.2f} ms loading data, {(et-mt)*1000:.2f} ms to run model over {len(X)} features") - - pred = get_bert_qa_prediction(X, Y, outs) - print(f"pred: {pred}\nans: {Y['answers']}") - f1 += max([f1_score(pred, ans) for ans in Y["answers"]]) - c += 1 - print(f"f1: {f1/c}, raw: {f1}, c: {c}\n") - - st = time.perf_counter() - -def eval_mrcnn(): - from tqdm import tqdm - from extra.models.mask_rcnn import MaskRCNN - from extra.models.resnet import ResNet - from extra.datasets.coco import BASEDIR, images, convert_prediction_to_coco_bbox, convert_prediction_to_coco_mask, accumulate_predictions_for_coco, evaluate_predictions_on_coco, iterate - from examples.mask_rcnn import compute_prediction_batched, Image - mdl = MaskRCNN(ResNet(50, num_classes=None, stride_in_1x1=True)) - mdl.load_from_pretrained() - - bbox_output = '/tmp/results_bbox.json' - mask_output = '/tmp/results_mask.json' - - accumulate_predictions_for_coco([], bbox_output, rm=True) - accumulate_predictions_for_coco([], mask_output, rm=True) - - #TODO: bs > 1 not as accurate - bs = 1 - - for batch in tqdm(iterate(images, bs=bs), total=len(images)//bs): - batch_imgs = [] - for image_row in batch: - image_name = image_row['file_name'] - img = Image.open(BASEDIR/f'val2017/{image_name}').convert("RGB") - batch_imgs.append(img) - batch_result = compute_prediction_batched(batch_imgs, mdl) - for image_row, result in zip(batch, batch_result): - image_name = image_row['file_name'] - box_pred = convert_prediction_to_coco_bbox(image_name, result) - mask_pred = convert_prediction_to_coco_mask(image_name, result) - accumulate_predictions_for_coco(box_pred, bbox_output) - accumulate_predictions_for_coco(mask_pred, mask_output) - del batch_imgs - del batch_result - - evaluate_predictions_on_coco(bbox_output, iou_type='bbox') - evaluate_predictions_on_coco(mask_output, iou_type='segm') - -if __name__ == "__main__": - # inference only - Tensor.training = False - - models = getenv("MODEL", "resnet,retinanet,unet3d,rnnt,bert,mrcnn").split(",") - for m in models: - nm = f"eval_{m}" - if nm in globals(): - print(f"eval {m}") - globals()[nm]() diff --git a/tinygrad/examples/mlperf/model_spec.py b/tinygrad/examples/mlperf/model_spec.py deleted file mode 100644 index 1c4411c8..00000000 --- a/tinygrad/examples/mlperf/model_spec.py +++ /dev/null @@ -1,69 +0,0 @@ -# load each model here, quick benchmark -from tinygrad import Tensor, GlobalCounters -from tinygrad.helpers import getenv -import numpy as np - -def test_model(model, *inputs): - GlobalCounters.reset() - out = model(*inputs) - if isinstance(out, Tensor): out = out.numpy() - # TODO: return event future to still get the time_sum_s without DEBUG=2 - print(f"{GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.time_sum_s*1000:.2f} ms") - -def spec_resnet(): - # Resnet50-v1.5 - from extra.models.resnet import ResNet50 - mdl = ResNet50() - img = Tensor.randn(1, 3, 224, 224) - test_model(mdl, img) - -def spec_retinanet(): - # Retinanet with ResNet backbone - from extra.models.resnet import ResNet50 - from extra.models.retinanet import RetinaNet - mdl = RetinaNet(ResNet50(), num_classes=91, num_anchors=9) - img = Tensor.randn(1, 3, 224, 224) - test_model(mdl, img) - -def spec_unet3d(): - # 3D UNET - from extra.models.unet3d import UNet3D - mdl = UNet3D() - #mdl.load_from_pretrained() - img = Tensor.randn(1, 1, 128, 128, 128) - test_model(mdl, img) - -def spec_rnnt(): - from extra.models.rnnt import RNNT - mdl = RNNT() - #mdl.load_from_pretrained() - x = Tensor.randn(220, 1, 240) - y = Tensor.randn(1, 220) - test_model(mdl, x, y) - -def spec_bert(): - from extra.models.bert import BertForQuestionAnswering - mdl = BertForQuestionAnswering() - #mdl.load_from_pretrained() - x = Tensor.randn(1, 384) - am = Tensor.randn(1, 384) - tt = Tensor(np.random.randint(0, 2, (1, 384)).astype(np.float32)) - test_model(mdl, x, am, tt) - -def spec_mrcnn(): - from extra.models.mask_rcnn import MaskRCNN, ResNet - mdl = MaskRCNN(ResNet(50, num_classes=None, stride_in_1x1=True)) - #mdl.load_from_pretrained() - x = Tensor.randn(3, 224, 224) - test_model(mdl, [x]) - -if __name__ == "__main__": - # inference only for now - Tensor.training = False - - for m in getenv("MODEL", "resnet,retinanet,unet3d,rnnt,bert,mrcnn").split(","): - nm = f"spec_{m}" - if nm in globals(): - print(f"testing {m}") - globals()[nm]() - diff --git a/tinygrad/examples/mlperf/model_train.py b/tinygrad/examples/mlperf/model_train.py deleted file mode 100644 index e3b2b382..00000000 --- a/tinygrad/examples/mlperf/model_train.py +++ /dev/null @@ -1,1294 +0,0 @@ -import os, time, math, functools, random, contextlib -from pathlib import Path -import multiprocessing - -from tinygrad import Device, GlobalCounters, Tensor, TinyJit, dtypes -from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, FUSE_CONV_BW, Profiling -from tinygrad.nn.state import get_parameters, get_state_dict, safe_load, safe_save -from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam - -from extra.lr_scheduler import LRSchedulerGroup -from examples.mlperf.helpers import get_training_state, load_training_state -from extra.bench_log import BenchEvent, WallTimeEvent -# TODO: fix benchmark logging and use tinygrad tqdm -from tqdm import tqdm - -def train_resnet(): - from extra.models import resnet - from examples.mlperf.dataloader import batch_load_resnet - from extra.datasets.imagenet import get_train_files, get_val_files - from examples.mlperf.lr_schedulers import PolynomialDecayWithWarmup - from examples.mlperf.initializers import Conv2dHeNormal, Linear - from examples.hlb_cifar10 import UnsyncedBatchNorm - - config = {} - seed = config["seed"] = getenv("SEED", 42) - Tensor.manual_seed(seed) # seed for weight initialization - - INITMLPERF = getenv("INITMLPERF") - RUNMLPERF = getenv("RUNMLPERF") - if getenv("LOGMLPERF"): - from mlperf_logging import mllog - import mlperf_logging.mllog.constants as mllog_constants - mllog.config(filename=f"result_resnet_{seed}.txt") - mllog.config(root_dir=Path(__file__).parents[3].as_posix()) # truncate to log this. "file": "tinygrad/examples/mlperf/model_train.py" - MLLOGGER = mllog.get_mllogger() - if INITMLPERF: - # common.yaml - MLLOGGER.event(key=mllog_constants.SUBMISSION_ORG, value="tinycorp") - MLLOGGER.event(key=mllog_constants.SUBMISSION_PLATFORM, value=getenv("SUBMISSION_PLATFORM", "tinybox")) - MLLOGGER.event(key=mllog_constants.SUBMISSION_DIVISION, value=mllog_constants.CLOSED) - MLLOGGER.event(key=mllog_constants.SUBMISSION_STATUS, value=mllog_constants.ONPREM) - # closed_common.yaml - MLLOGGER.event(key=mllog_constants.SUBMISSION_BENCHMARK, value=mllog_constants.RESNET) - diskcache_clear() - MLLOGGER.event(key=mllog_constants.CACHE_CLEAR, value=True) - MLLOGGER.start(key=mllog_constants.INIT_START) - if RUNMLPERF: - MLLOGGER.start(key=mllog_constants.RUN_START) - MLLOGGER.event(key=mllog_constants.SEED, value=seed) - else: - MLLOGGER = None - - GPUS = config["GPUS"] = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 1))] - print(f"training on {GPUS}") - for x in GPUS: Device[x] - - TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value) - EVAL_BEAM = getenv("EVAL_BEAM", BEAM.value) - - # ** model definition and initializers ** - num_classes = 1000 - resnet.Conv2d = Conv2dHeNormal - resnet.Linear = Linear - if not getenv("SYNCBN"): resnet.BatchNorm = functools.partial(UnsyncedBatchNorm, num_devices=len(GPUS)) - model = resnet.ResNet50(num_classes) - - # shard weights and initialize in order - for k, x in get_state_dict(model).items(): - if not getenv("SYNCBN") and ("running_mean" in k or "running_var" in k): - x.realize().shard_(GPUS, axis=0) - else: - x.realize().to_(GPUS) - parameters = get_parameters(model) - - # ** hyperparameters ** - epochs = config["epochs"] = getenv("EPOCHS", 37) - BS = config["BS"] = getenv("BS", 104 * len(GPUS)) # fp32 GPUS<=6 7900xtx can fit BS=112 - EVAL_BS = config["EVAL_BS"] = getenv("EVAL_BS", BS) - base_lr = config["base_lr"] = getenv("LR", 7.2 * (BS/1536)) - lr_warmup_epochs = config["lr_warmup_epochs"] = getenv("WARMUP_EPOCHS", 2) - decay = config["decay"] = getenv("DECAY", 2e-4) - - loss_scaler = config["LOSS_SCALER"] = getenv("LOSS_SCALER", 256.0 if dtypes.default_float == dtypes.float16 else 1.0) - - target, achieved = getenv("TARGET", 0.759), False - eval_start_epoch = getenv("EVAL_START_EPOCH", 0) - eval_freq = getenv("EVAL_FREQ", 1) - - steps_in_train_epoch = config["steps_in_train_epoch"] = (round_up(len(get_train_files()), BS) // BS) - steps_in_val_epoch = config["steps_in_val_epoch"] = (round_up(len(get_val_files()), EVAL_BS) // EVAL_BS) - - config["DEFAULT_FLOAT"] = dtypes.default_float.name - config["BEAM"] = BEAM.value - config["TRAIN_BEAM"] = TRAIN_BEAM - config["EVAL_BEAM"] = EVAL_BEAM - config["WINO"] = WINO.value - config["SYNCBN"] = getenv("SYNCBN") - - # ** Optimizer ** - skip_list = [v for k, v in get_state_dict(model).items() if "bn" in k or "bias" in k or "downsample.1" in k] - parameters = [x for x in parameters if x not in set(skip_list)] - optimizer = LARS(parameters, base_lr, momentum=.9, weight_decay=decay) - optimizer_skip = SGD(skip_list, base_lr, momentum=.9, weight_decay=0.0, classic=True) - optimizer_group = OptimizerGroup(optimizer, optimizer_skip) - - # ** LR scheduler ** - scheduler = PolynomialDecayWithWarmup(optimizer, initial_lr=base_lr, end_lr=1e-4, - train_steps=epochs * steps_in_train_epoch, - warmup=lr_warmup_epochs * steps_in_train_epoch) - scheduler_skip = PolynomialDecayWithWarmup(optimizer_skip, initial_lr=base_lr, end_lr=1e-4, - train_steps=epochs * steps_in_train_epoch, - warmup=lr_warmup_epochs * steps_in_train_epoch) - scheduler_group = LRSchedulerGroup(scheduler, scheduler_skip) - print(f"training with batch size {BS} for {epochs} epochs") - - # log mlperf hparams - if MLLOGGER: - if RUNMLPERF: - MLLOGGER.event(key=mllog_constants.GLOBAL_BATCH_SIZE, value=BS) - from extra.datasets.imagenet import get_train_files, get_val_files - MLLOGGER.event(key=mllog_constants.TRAIN_SAMPLES, value=len(get_train_files())) - MLLOGGER.event(key=mllog_constants.EVAL_SAMPLES, value=len(get_val_files())) - - MLLOGGER.event(key=mllog_constants.GRADIENT_ACCUMULATION_STEPS, value=1) - MLLOGGER.event(key=mllog_constants.OPT_NAME, value="lars") - assert scheduler.initial_lr == scheduler_skip.initial_lr - assert scheduler.end_lr == scheduler_skip.end_lr - assert scheduler.power == scheduler_skip.power - MLLOGGER.event(key=mllog_constants.LARS_OPT_BASE_LEARNING_RATE, value=scheduler.initial_lr) - MLLOGGER.event(key=mllog_constants.LARS_OPT_END_LR, value=scheduler.end_lr) - MLLOGGER.event(key=mllog_constants.LARS_OPT_LR_DECAY_POLY_POWER, value=scheduler.power) - MLLOGGER.event(key=mllog_constants.LARS_OPT_LR_DECAY_STEPS, value=epochs) - MLLOGGER.event(key=mllog_constants.LARS_EPSILON, value=0) # does not support epsilon != 0 - MLLOGGER.event(key=mllog_constants.LARS_OPT_LEARNING_RATE_WARMUP_EPOCHS, value=lr_warmup_epochs) - MLLOGGER.event(key=mllog_constants.LARS_OPT_MOMENTUM, value=optimizer.momentum) - MLLOGGER.event(key=mllog_constants.LARS_OPT_WEIGHT_DECAY, value=optimizer.wd) - - # ** resume from checkpointing ** - start_epoch = 0 - if ckpt:=getenv("RESUME", ""): - load_training_state(model, optimizer_group, scheduler_group, safe_load(ckpt)) - start_epoch = int(scheduler.epoch_counter.numpy().item() / steps_in_train_epoch) - print(f"resuming from {ckpt} at epoch {start_epoch}") - - # ** init wandb ** - WANDB = getenv("WANDB") - if WANDB: - import wandb - wandb_args = {"id": wandb_id, "resume": "must"} if (wandb_id := getenv("WANDB_RESUME", "")) else {} - wandb.init(config=config, **wandb_args) - - BENCHMARK = getenv("BENCHMARK") - - # ** jitted steps ** - input_mean = Tensor([123.68, 116.78, 103.94], device=GPUS, dtype=dtypes.float32).reshape(1, -1, 1, 1) - # mlperf reference resnet does not divide by input_std for some reason - # input_std = Tensor([0.229, 0.224, 0.225], device=GPUS, dtype=dtypes.float32).reshape(1, -1, 1, 1) - def normalize(x): return (x.permute([0, 3, 1, 2]) - input_mean).cast(dtypes.default_float) - @TinyJit - def train_step(X, Y): - optimizer_group.zero_grad() - X = normalize(X) - out = model.forward(X) - loss = out.cast(dtypes.float32).sparse_categorical_crossentropy(Y, label_smoothing=0.1) - top_1 = (out.argmax(-1) == Y).sum() - (loss * loss_scaler).backward() - for t in optimizer_group.params: t.grad = t.grad.contiguous() / loss_scaler - optimizer_group.step() - scheduler_group.step() - return loss.realize(), top_1.realize() - - @TinyJit - def eval_step(X, Y): - X = normalize(X) - out = model.forward(X) - loss = out.cast(dtypes.float32).sparse_categorical_crossentropy(Y, label_smoothing=0.1) - top_1 = (out.argmax(-1) == Y).sum() - return loss.realize(), top_1.realize() - - def fake_data_get(batch_size): - x = Tensor.zeros(batch_size, 224, 224, 3, dtype=dtypes.uchar).contiguous() - y = [0] * batch_size - return x.shard(GPUS, axis=0).realize(), Tensor(y, requires_grad=False).shard(GPUS, axis=0), y, None - - def data_get(it): - x, y, cookie = next(it) - return x.shard(GPUS, axis=0).realize(), Tensor(y, requires_grad=False).shard(GPUS, axis=0), y, cookie - - # ** epoch loop ** - step_times = [] - for e in range(start_epoch, epochs): - # ** train loop ** - if MLLOGGER and RUNMLPERF: - MLLOGGER.start(key=mllog_constants.EPOCH_START, value=e+1, metadata=dict(epoch_num=e+1)) - Tensor.training = True - BEAM.value = TRAIN_BEAM - - if INITMLPERF: - i, proc = 0, fake_data_get(BS) - else: - batch_loader = batch_load_resnet(batch_size=BS, val=False, shuffle=True, seed=seed*epochs + e, pad_first_batch=True) - it = iter(tqdm(batch_loader, total=steps_in_train_epoch, desc=f"epoch {e}", disable=BENCHMARK)) - i, proc = 0, data_get(it) - - prev_cookies = [] - st = time.perf_counter() - while proc is not None: - GlobalCounters.reset() - with WallTimeEvent(BenchEvent.STEP): - (loss, top_1), y, proc = train_step(proc[0], proc[1]), proc[2], proc[3] - - pt = time.perf_counter() - - if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = [] # free previous cookies after gpu work has been enqueued - try: - if INITMLPERF: - next_proc = fake_data_get(BS) - else: - next_proc = data_get(it) - except StopIteration: - next_proc = None - - dt = time.perf_counter() - - device_str = loss.device if isinstance(loss.device, str) else f"{loss.device[0]} * {len(loss.device)}" - loss, top_1 = loss.numpy().item(), top_1.numpy().item() - top_1_acc = top_1 / sum(yi != -1 for yi in y) - - cl = time.perf_counter() - if BENCHMARK: - step_times.append(cl - st) - - tqdm.write( - f"{i:5} {((cl - st)) * 1000.0:7.2f} ms run, {(pt - st) * 1000.0:7.2f} ms python, {(dt - pt) * 1000.0:6.2f} ms fetch data, " - f"{(cl - dt) * 1000.0:7.2f} ms {device_str}, {loss:5.2f} loss, {top_1_acc:3.2f} acc, {optimizer.lr.numpy()[0]:.6f} LR, " - f"{GlobalCounters.mem_used / 1e9:.2f} GB used, {GlobalCounters.global_ops * 1e-9 / (cl - st):9.2f} GFLOPS") - if WANDB: - wandb.log({"lr": optimizer.lr.numpy(), "train/loss": loss, "train/top_1_acc": top_1_acc, "train/step_time": cl - st, - "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt, - "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": e + (i + 1) / steps_in_train_epoch}) - - st = cl - prev_cookies.append(proc) - proc, next_proc = next_proc, None # return old cookie - i += 1 - - if i == BENCHMARK: - assert not math.isnan(loss) - median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2] # in seconds - estimated_total_minutes = int(median_step_time * steps_in_train_epoch * epochs / 60) - print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m") - print(f"epoch global_ops: {steps_in_train_epoch * GlobalCounters.global_ops:_}, " - f"epoch global_mem: {steps_in_train_epoch * GlobalCounters.global_mem:_}") - # if we are doing beam search, run the first eval too - if (TRAIN_BEAM or EVAL_BEAM) and e == start_epoch: break - return - if MLLOGGER and RUNMLPERF: - MLLOGGER.event(key=mllog_constants.EPOCH_STOP, value=e+1, metadata=dict(epoch_num=e+1)) - - # ** eval loop ** - # always eval for epoch >= 33 to stop the clock as soon as eval target hits, it can converge in epoch in [33, 37] - if steps_in_val_epoch > 0 and ((e + 1 - eval_start_epoch) % eval_freq == 0 or e + 1 >= 33): - if MLLOGGER and RUNMLPERF: - MLLOGGER.start(key=mllog_constants.EVAL_START, value=e+1, metadata=dict(epoch_num=e+1)) - if getenv("RESET_STEP", 1): train_step.reset() # free the train step memory :( - eval_times = [] - eval_loss = 0.0 - eval_top_1 = 0 - eval_num_samples = 0 - Tensor.training = False - BEAM.value = EVAL_BEAM - - if INITMLPERF: - i, proc = 0, fake_data_get(EVAL_BS) - else: - it = iter(tqdm(batch_load_resnet(batch_size=EVAL_BS, val=True, shuffle=False, pad_first_batch=True), total=steps_in_val_epoch)) - i, proc = 0, data_get(it) - - prev_cookies = [] - while proc is not None: - GlobalCounters.reset() - st = time.time() - - (loss, top_1), y, proc = eval_step(proc[0], proc[1]), proc[2], proc[3] # drop inputs, keep cookie - - if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = [] # free previous cookies after gpu work has been enqueued - try: - if INITMLPERF: - next_proc = fake_data_get(EVAL_BS) - else: - next_proc = data_get(it) - except StopIteration: - next_proc = None - - loss, top_1 = loss.numpy().item(), top_1.numpy().item() - num_samples = sum(yi != -1 for yi in y) - eval_loss += loss * num_samples - eval_top_1 += top_1 - eval_num_samples += num_samples - prev_cookies.append(proc) - proc, next_proc = next_proc, None - i += 1 - if i == BENCHMARK: - # assume INITMLPERF has BENCHMARK set - if MLLOGGER and INITMLPERF: - MLLOGGER.event(key=mllog_constants.INIT_STOP) - return - - et = time.time() - eval_times.append(et - st) - - if getenv("RESET_STEP", 1): eval_step.reset() - if not BENCHMARK: - assert eval_num_samples == len(get_val_files()), f"eval sample count mismatched. {eval_num_samples=} != {len(get_val_files())}" - total_loss = eval_loss / eval_num_samples - total_top_1 = eval_top_1 / eval_num_samples - total_fw_time = sum(eval_times) / len(eval_times) - tqdm.write(f"eval loss: {total_loss:.2f}, eval time: {total_fw_time:.2f}, eval top 1 acc: {total_top_1:.3f}") - if WANDB: - wandb.log({"eval/loss": total_loss, "eval/top_1_acc": total_top_1, "eval/forward_time": total_fw_time, "epoch": e + 1}) - if MLLOGGER and RUNMLPERF: - MLLOGGER.event(key=mllog_constants.EVAL_ACCURACY, value=total_top_1, metadata=dict(epoch_num=e+1)) - MLLOGGER.event(key=mllog_constants.EVAL_STOP, value=e+1, metadata=dict(epoch_num=e+1)) - - # save model if achieved target - if not achieved and total_top_1 >= target: - # stop once achieve the target - if MLLOGGER and RUNMLPERF: - MLLOGGER.event(key=mllog_constants.RUN_STOP, metadata=dict(status=mllog_constants.SUCCESS)) - if not os.path.exists("./ckpts"): os.mkdir("./ckpts") - fn = f"./ckpts/resnet50_{seed}.safe" - safe_save(get_state_dict(model), fn) - print(f" *** Model saved to {fn} ***") - achieved = True - break - - # checkpoint every time we eval - if getenv("CKPT"): - if not os.path.exists("./ckpts"): os.mkdir("./ckpts") - if WANDB and wandb.run is not None: - fn = f"./ckpts/{time.strftime('%Y%m%d_%H%M%S')}_{wandb.run.id}_e{e}.safe" - else: - fn = f"./ckpts/{time.strftime('%Y%m%d_%H%M%S')}_e{e}.safe" - print(f"saving ckpt to {fn}") - safe_save(get_training_state(model, optimizer_group, scheduler_group), fn) - -def train_retinanet(): - from contextlib import redirect_stdout - from examples.mlperf.dataloader import batch_load_retinanet - from examples.mlperf.initializers import FrozenBatchNorm2dRetinaNet, Conv2dNormalRetinaNet, Conv2dKaimingUniformRetinaNet, Linear, Conv2dRetinaNet - from extra.datasets.openimages import MLPERF_CLASSES, BASEDIR, download_dataset, normalize, get_dataset_count - from extra.models import resnet, retinanet - from pycocotools.coco import COCO - from pycocotools.cocoeval import COCOeval - from tinygrad.helpers import colored - from typing import Iterator - - import numpy as np - - config, target_metric = {}, 0.34 - - config["SEED"] = SEED = getenv("SEED", random.SystemRandom().randint(0, 2**32 - 1)) - Tensor.manual_seed(SEED) - - NUM_CLASSES = len(MLPERF_CLASSES) - BASEDIR = getenv("BASEDIR", BASEDIR) - BENCHMARK = getenv("BENCHMARK") - INITMLPERF = getenv("INITMLPERF") - RUNMLPERF = getenv("RUNMLPERF") - - if INITMLPERF: - diskcache_clear() - - if getenv("LOGMLPERF"): - from mlperf_logging import mllog - import mlperf_logging.mllog.constants as mllog_constants - - mllog.config(filename=f"result_retinanet_{SEED}.log") - mllog.config(root_dir=Path(__file__).parents[3].as_posix()) - MLLOGGER = mllog.get_mllogger() - MLLOGGER.logger.propagate = False - - if INITMLPERF: - assert BENCHMARK, "BENCHMARK must be set for INITMLPERF" - MLLOGGER.event(key=mllog_constants.SUBMISSION_ORG, value="tinycorp") - MLLOGGER.event(key=mllog_constants.SUBMISSION_PLATFORM, value=getenv("SUBMISSION_PLATFORM", "tinybox")) - MLLOGGER.event(key=mllog_constants.SUBMISSION_DIVISION, value=mllog_constants.CLOSED) - MLLOGGER.event(key=mllog_constants.SUBMISSION_STATUS, value=mllog_constants.ONPREM) - - MLLOGGER.event(key=mllog_constants.SUBMISSION_BENCHMARK, value=mllog_constants.RETINANET) - - MLLOGGER.event(key=mllog_constants.CACHE_CLEAR, value=True) - MLLOGGER.start(key=mllog_constants.INIT_START) - - if RUNMLPERF: - MLLOGGER.start(key=mllog_constants.RUN_START) - MLLOGGER.event(key=mllog_constants.SEED, value=SEED) - else: - MLLOGGER = None - - config["gpus"] = GPUS = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 6))] - - for x in GPUS: Device[x] - print(f"training on {GPUS}") - - def _freeze_backbone_layers(backbone:resnet.ResNet, trainable_layers:int): - layers_to_train = ["layer4", "layer3", "layer2", "layer1", "conv1"][:trainable_layers] - for k, v in get_state_dict(backbone).items(): - if all([not k.startswith(layer) for layer in layers_to_train]): - v.requires_grad = False - - def _data_get(it:Iterator[tuple[Tensor, ...]], val:bool=False): - if val: - x, img_ids, img_sizes, cookie = next(it) - return x.shard(GPUS, axis=0), img_ids, img_sizes, cookie - - x, y_boxes, y_labels, matches, anchors, cookie = next(it) - return x.shard(GPUS, axis=0), y_boxes.shard(GPUS, axis=0), y_labels.shard(GPUS, axis=0), matches.shard(GPUS, axis=0), anchors.shard(GPUS, axis=0), cookie - - def _fake_data_get(bs:int, val:bool=False): - x = Tensor.empty(bs, 800, 800, 3, dtype=dtypes.uint8) - if val: - img_ids, img_sizes = [0] * bs, [(800, 800)] * bs - return x.shard(GPUS, axis=0), img_ids, img_sizes, None - - y_boxes = Tensor.empty(bs, 120087, 4, dtype=dtypes.float32) - y_labels = Tensor.empty(bs, 120087, dtype=dtypes.int64) - matches = Tensor.empty(bs, 120087, dtype=dtypes.int64) - anchors = Tensor.empty(bs, 120087, 4, dtype=dtypes.float64) - return x.shard(GPUS, axis=0), y_boxes.shard(GPUS, axis=0), y_labels.shard(GPUS, axis=0), matches.shard(GPUS, axis=0), anchors.shard(GPUS, axis=0), None - - @TinyJit - def _train_step(model, optim, loss_scaler, x, **kwargs): - optim.zero_grad() - - losses = model(normalize(x, GPUS), **kwargs) - loss = sum(losses.values()) - - (loss * loss_scaler).backward() - for t in optim.params: t.grad = t.grad / loss_scaler - - optim.step() - - return loss.realize(), losses - - @TinyJit - def _eval_step(model, x, **kwargs): - out = model(normalize(x, GPUS), **kwargs) - # reassemble on GPUS[0] before sending back to CPU for speed - return out.to(GPUS[0]).realize() - - # ** hyperparameters ** - config["BS"] = BS = getenv("BS", 16 * len(GPUS) if dtypes.default_float == dtypes.float16 else 12 * len(GPUS)) - config["EVAL_BS"] = EVAL_BS = getenv("EVAL_BS", BS) - config["EPOCHS"] = EPOCHS = getenv("EPOCHS", 4) - config["TRAIN_BEAM"] = TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value) - config["EVAL_BEAM"] = EVAL_BEAM = getenv("EVAL_BEAM", BEAM.value) - config["LR"] = lr = getenv("LR", 9.5e-5 * (BS / 96)) - config["LOSS_SCALER"] = loss_scaler = getenv("LOSS_SCALER", 2**11 if dtypes.default_float == dtypes.float16 else 1.0) - config["DEFAULT_FLOAT"] = dtypes.default_float.name - config["EVAL_FREQ"] = eval_freq = getenv("EVAL_FREQ", 1) - - # ** initialize wandb ** - if (WANDB:=getenv("WANDB")): - import wandb - wandb.init(config=config, project="MLPerf-RetinaNet") - - # ** model initializers ** - resnet.BatchNorm = FrozenBatchNorm2dRetinaNet - resnet.Linear = Linear - resnet.Conv2d = Conv2dRetinaNet - - retinanet.ConvHead = Conv2dNormalRetinaNet - retinanet.ConvClassificationHeadLogits = functools.partial(Conv2dNormalRetinaNet, prior_prob=0.01) - retinanet.ConvFPN = Conv2dKaimingUniformRetinaNet - - # ** model setup ** - backbone = resnet.ResNeXt50_32X4D(num_classes=None) - if RUNMLPERF: - backbone.load_from_pretrained() - _freeze_backbone_layers(backbone, 3) - - model = retinanet.RetinaNet(backbone, num_classes=NUM_CLASSES) - params = get_parameters(model) - - if not RUNMLPERF: - # for init, zero out all weights - for p in params: - p = p.assign(Tensor.zeros_like(p).contiguous()).realize() - - if len(GPUS) > 1: - for p in params: p.to_(GPUS) - - step_times, start_epoch = [], 0 - - # ** optimizer ** - optim = Adam(params, lr=lr) - - # ** dataset ** - config["STEPS_IN_TRAIN_EPOCH"] = steps_in_train_epoch = round_up(get_dataset_count((base_dir_path:=Path(BASEDIR)), False), BS) // BS - config["STEPS_IN_VAL_EPOCH"] = steps_in_val_epoch = (round_up(get_dataset_count(base_dir_path, True), EVAL_BS) // EVAL_BS) - - # log mlperf hparams - if MLLOGGER: - if RUNMLPERF: - MLLOGGER.event(key=mllog_constants.GLOBAL_BATCH_SIZE, value=config["BS"]) - MLLOGGER.event(key=mllog_constants.TRAIN_SAMPLES, value=config["STEPS_IN_TRAIN_EPOCH"]) - MLLOGGER.event(key=mllog_constants.EVAL_SAMPLES, value=config["STEPS_IN_VAL_EPOCH"]) - MLLOGGER.event(key=mllog_constants.EPOCH_COUNT, value=config["EPOCHS"]) - MLLOGGER.event(key=mllog_constants.FIRST_EPOCH_NUM, value=start_epoch) - - MLLOGGER.event(key=mllog_constants.OPT_NAME, value=mllog_constants.ADAM) - MLLOGGER.event(key=mllog_constants.OPT_BASE_LR, value=config["LR"]) - MLLOGGER.event(key=mllog_constants.OPT_WEIGHT_DECAY, value=0) - MLLOGGER.event(key=mllog_constants.OPT_LR_WARMUP_EPOCHS, value=0) - MLLOGGER.event(key=mllog_constants.OPT_LR_WARMUP_FACTOR, value=0) - MLLOGGER.event(key=mllog_constants.GRADIENT_ACCUMULATION_STEPS, value=1) - - if RUNMLPERF: - train_dataset = COCO(download_dataset(BASEDIR, "train")) - val_dataset = COCO(download_dataset(BASEDIR, "validation")) - coco_val = COCOeval(cocoGt=val_dataset, iouType="bbox") - - print(f"training with batch size {BS} for {EPOCHS} epochs") - - for e in range(start_epoch, EPOCHS): - # ** training loop ** - if MLLOGGER and RUNMLPERF: - MLLOGGER.start(key=mllog_constants.EPOCH_START, value=e + 1, metadata={"epoch_num": e + 1}) - - BEAM.value = TRAIN_BEAM - - if not RUNMLPERF: - i, proc = 0, _fake_data_get(BS) - else: - train_dataloader = batch_load_retinanet(train_dataset, False, base_dir_path, batch_size=BS, seed=SEED) - it = iter(tqdm(train_dataloader, total=steps_in_train_epoch, desc=f"epoch {e + 1}", disable=BENCHMARK)) - i, proc = 0, _data_get(it) - - prev_cookies = [] - st = time.perf_counter() - - while proc is not None: - GlobalCounters.reset() - - x, y_bboxes, y_labels, matches, anchors, proc = proc - loss, losses = _train_step(model, optim, loss_scaler, x, labels=y_labels, matches=matches, anchors=anchors, bboxes=y_bboxes) - - pt = time.perf_counter() - - if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = [] # free previous cookies after gpu work has been enqueued - try: - if not RUNMLPERF: - next_proc = _fake_data_get(BS) - else: - next_proc = _data_get(it) - except StopIteration: - next_proc = None - - dt = time.perf_counter() - - device_str = loss.device if isinstance(loss.device, str) else f"{loss.device[0]} * {len(loss.device)}" - loss = loss.item() - - cl = time.perf_counter() - if BENCHMARK: step_times.append(cl - st) - - if not math.isfinite(loss): - print("loss is nan") - return - - tqdm.write( - f"{i:5} {((cl - st)) * 1000.0:7.2f} ms run, {(pt - st) * 1000.0:7.2f} ms python, {(dt - pt) * 1000.0:6.2f} ms fetch data, " - f"{(cl - dt) * 1000.0:7.2f} ms {device_str}, {loss:5.2f} loss, {losses['classification_loss'].item():5.4f} classification loss, {losses['regression_loss'].item():5.4f} regression loss, " - f"{optim.lr.numpy()[0]:.6f} LR, {GlobalCounters.mem_used / 1e9:.2f} GB used, {GlobalCounters.global_ops * 1e-9 / (cl - st):9.2f} GFLOPS" - ) - - if WANDB: - wandb.log({"lr": optim.lr.numpy(), "train/loss": loss, "train/classification_loss": losses["classification_loss"].item(), "train/regression_loss": losses["regression_loss"].item(), - "train/step_time": cl - st, "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt, - "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": e + (i + 1) / steps_in_train_epoch}) - - st = cl - prev_cookies.append(proc) - proc, next_proc = next_proc, None # return old cookie - i += 1 - - if i == BENCHMARK: - assert not math.isnan(loss) - median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2] # in seconds - estimated_total_minutes = int(median_step_time * steps_in_train_epoch * EPOCHS / 60) - print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m") - print(f"epoch global_ops: {steps_in_train_epoch * GlobalCounters.global_ops:_}, " - f"epoch global_mem: {steps_in_train_epoch * GlobalCounters.global_mem:_}") - # if we are doing beam search, run the first eval too - if (TRAIN_BEAM or EVAL_BEAM) and e == start_epoch: break - return - - if MLLOGGER and RUNMLPERF: - MLLOGGER.event(key=mllog_constants.EPOCH_STOP, value=e + 1, metadata={"epoch_num": e + 1}) - - # ** eval loop ** - if (e + 1) % eval_freq == 0: - if MLLOGGER and RUNMLPERF: - MLLOGGER.start(key=mllog_constants.EVAL_START, value=e + 1, metadata={"epoch_num": e + 1}) - - BEAM.value = EVAL_BEAM - - if getenv("RESET_STEP", 1): _train_step.reset() - - with Tensor.train(mode=False), Tensor.test(): - if not RUNMLPERF: - i, proc = 0, _fake_data_get(EVAL_BS, val=(val:=True)) - else: - val_dataloader = batch_load_retinanet(val_dataset, (val:=True), Path(BASEDIR), batch_size=EVAL_BS, shuffle=False, seed=SEED) - it = iter(tqdm(val_dataloader, total=steps_in_val_epoch)) - i, proc = 0, _data_get(it, val=val) - val_img_ids, val_imgs, ncats, narea = [], [], len(coco_val.params.catIds), len(coco_val.params.areaRng) - - eval_times, prev_cookies = [], [] - - while proc is not None: - GlobalCounters.reset() - st = time.time() - - out, img_ids, img_sizes, proc = _eval_step(model, (x:=proc[0])).numpy(), proc[1], proc[2], proc[3] - - if RUNMLPERF: - out = model.postprocess_detections(out, input_size=x.shape[1:3], orig_image_sizes=img_sizes) - coco_results = [{"image_id": img_ids[i], "category_id": label, "bbox": box.tolist(), "score": score} - for i, prediction in enumerate(out) for box, score, label in zip(*prediction.values())] - - with redirect_stdout(None): - coco_val.cocoDt = val_dataset.loadRes(coco_results) - coco_val.params.imgIds = img_ids - coco_val.evaluate() - - val_img_ids.extend(img_ids) - val_imgs.append(np.array(coco_val.evalImgs).reshape(ncats, narea, len(img_ids))) - - if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = [] # free previous cookies after gpu work has been enqueued - try: - if not RUNMLPERF: - next_proc = _fake_data_get(EVAL_BS, val=val) - else: - next_proc = _data_get(it, val=val) - except StopIteration: - next_proc = None - - prev_cookies.append(proc) - proc, next_proc = next_proc, None - i += 1 - - et = time.time() - eval_times.append(et - st) - - if i == BENCHMARK: - # assume INITMLPERF has BENCHMARK set - if MLLOGGER and INITMLPERF: - MLLOGGER.event(key=mllog_constants.INIT_STOP) - return - - if getenv("RESET_STEP", 1): _eval_step.reset() - total_fw_time = sum(eval_times) / len(eval_times) - - if RUNMLPERF: - coco_val.params.imgIds = val_img_ids - coco_val._paramsEval.imgIds = val_img_ids - coco_val.evalImgs = list(np.concatenate(val_imgs, -1).flatten()) - coco_val.accumulate() - coco_val.summarize() - - val_metric = coco_val.stats[0] - - tqdm.write(f"eval time: {total_fw_time:.2f}, eval metric: {val_metric:.4f}") - - if WANDB: - wandb.log({"eval/forward_time": total_fw_time, "eval/metric": val_metric, "epoch": e + 1}) - - if MLLOGGER: - MLLOGGER.event(key=mllog_constants.EVAL_ACCURACY, value=val_metric, metadata={"epoch_num": e + 1}, clear_line=True) - MLLOGGER.end(key=mllog_constants.EVAL_STOP, value=e + 1, metadata={"epoch_num": e + 1}) - - if val_metric >= target_metric: - print(colored(f"target metric reached: {val_metric:.2f}/{target_metric:.2f}", color="green")) - - if MLLOGGER: - MLLOGGER.end(key=mllog_constants.RUN_STOP, metadata={"status": mllog_constants.SUCCESS}) - - break - -def train_unet3d(): - """ - Trains the UNet3D model. - - Instructions: - 1) Run the following script from the root folder of `tinygrad`: - ```./examples/mlperf/scripts/setup_kits19_dataset.sh``` - - Optionally, `BASEDIR` can be set to download and process the dataset at a specific location: - ```BASEDIR= ./examples/mlperf/scripts/setup_kits19_dataset.sh``` - - 2) To start training the model, run the following: - ```time PYTHONPATH=. WANDB=1 TRAIN_BEAM=3 FUSE_CONV_BW=1 GPUS=6 BS=6 MODEL=unet3d python3 examples/mlperf/model_train.py``` - """ - from examples.mlperf.losses import dice_ce_loss - from examples.mlperf.metrics import dice_score - from examples.mlperf.dataloader import batch_load_unet3d - from extra.models.unet3d import UNet3D - from extra.datasets.kits19 import iterate, get_train_files, get_val_files, sliding_window_inference, preprocess_dataset, TRAIN_PREPROCESSED_DIR, VAL_PREPROCESSED_DIR - from tinygrad import Context - from tinygrad.nn.optim import SGD - from math import ceil - - GPUS = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 1))] - for x in GPUS: Device[x] - - TARGET_METRIC = 0.908 - NUM_EPOCHS = getenv("NUM_EPOCHS", 4000) - BS = getenv("BS", 1 * len(GPUS)) - LR = getenv("LR", 2.0 * (BS / 28)) - LR_WARMUP_EPOCHS = getenv("LR_WARMUP_EPOCHS", 1000) - LR_WARMUP_INIT_LR = getenv("LR_WARMUP_INIT_LR", 0.0001) - WANDB = getenv("WANDB") - PROJ_NAME = getenv("PROJ_NAME", "tinygrad_unet3d_mlperf") - SEED = getenv("SEED", -1) if getenv("SEED", -1) >= 0 else None - TRAIN_DATASET_SIZE, VAL_DATASET_SIZE = len(get_train_files()), len(get_val_files()) - SAMPLES_PER_EPOCH = TRAIN_DATASET_SIZE // BS - START_EVAL_AT = getenv("START_EVAL_AT", ceil(1000 * TRAIN_DATASET_SIZE / (SAMPLES_PER_EPOCH * BS))) - EVALUATE_EVERY = getenv("EVALUATE_EVERY", ceil(20 * TRAIN_DATASET_SIZE / (SAMPLES_PER_EPOCH * BS))) - TRAIN_BEAM, EVAL_BEAM = getenv("TRAIN_BEAM", BEAM.value), getenv("EVAL_BEAM", BEAM.value) - BENCHMARK = getenv("BENCHMARK") - CKPT = getenv("CKPT") - - config = { - "num_epochs": NUM_EPOCHS, - "batch_size": BS, - "learning_rate": LR, - "learning_rate_warmup_epochs": LR_WARMUP_EPOCHS, - "learning_rate_warmup_init": LR_WARMUP_INIT_LR, - "start_eval_at": START_EVAL_AT, - "evaluate_every": EVALUATE_EVERY, - "train_beam": TRAIN_BEAM, - "eval_beam": EVAL_BEAM, - "wino": WINO.value, - "fuse_conv_bw": FUSE_CONV_BW.value, - "gpus": GPUS, - "default_float": dtypes.default_float.name - } - - if WANDB: - try: - import wandb - except ImportError: - raise "Need to install wandb to use it" - - if SEED is not None: - config["seed"] = SEED - Tensor.manual_seed(SEED) - - model = UNet3D() - params = get_parameters(model) - - for p in params: p.realize().to_(GPUS) - - optim = SGD(params, lr=LR, momentum=0.9, nesterov=True) - - def lr_warm_up(optim, init_lr, lr, current_epoch, warmup_epochs): - scale = current_epoch / warmup_epochs - optim.lr.assign(Tensor([init_lr + (lr - init_lr) * scale], device=GPUS)).realize() - - def save_checkpoint(state_dict, fn): - if not os.path.exists("./ckpts"): os.mkdir("./ckpts") - print(f"saving checkpoint to {fn}") - safe_save(state_dict, fn) - - def data_get(it): - x, y, cookie = next(it) - return x.shard(GPUS, axis=0).realize(), y.shard(GPUS, axis=0), cookie - - @TinyJit - @Tensor.train() - def train_step(model, x, y): - optim.zero_grad() - - y_hat = model(x) - loss = dice_ce_loss(y_hat, y) - - loss.backward() - optim.step() - return loss.realize() - - @Tensor.train(mode=False) - def eval_step(model, x, y): - y_hat, y = sliding_window_inference(model, x, y, gpus=GPUS) - y_hat, y = Tensor(y_hat), Tensor(y, requires_grad=False) - loss = dice_ce_loss(y_hat, y) - score = dice_score(y_hat, y) - return loss.realize(), score.realize() - - if WANDB: wandb.init(config=config, project=PROJ_NAME) - - step_times, start_epoch = [], 1 - is_successful, diverged = False, False - start_eval_at, evaluate_every = 1 if BENCHMARK else START_EVAL_AT, 1 if BENCHMARK else EVALUATE_EVERY - next_eval_at = start_eval_at - - print(f"Training on {GPUS}") - - if BENCHMARK: print("Benchmarking UNet3D") - else: print(f"Start evaluation at epoch {start_eval_at} and every {evaluate_every} epoch(s) afterwards") - - if not TRAIN_PREPROCESSED_DIR.exists(): preprocess_dataset(get_train_files(), TRAIN_PREPROCESSED_DIR, False) - if not VAL_PREPROCESSED_DIR.exists(): preprocess_dataset(get_val_files(), VAL_PREPROCESSED_DIR, True) - - for epoch in range(1, NUM_EPOCHS + 1): - with Context(BEAM=TRAIN_BEAM): - if epoch <= LR_WARMUP_EPOCHS and LR_WARMUP_EPOCHS > 0: - lr_warm_up(optim, LR_WARMUP_INIT_LR, LR, epoch, LR_WARMUP_EPOCHS) - - train_dataloader = batch_load_unet3d(TRAIN_PREPROCESSED_DIR, batch_size=BS, val=False, shuffle=True, seed=SEED) - it = iter(tqdm(train_dataloader, total=SAMPLES_PER_EPOCH, desc=f"epoch {epoch}", disable=BENCHMARK)) - i, proc = 0, data_get(it) - - prev_cookies = [] - st = time.perf_counter() - - while proc is not None: - GlobalCounters.reset() - - loss, proc = train_step(model, proc[0], proc[1]), proc[2] - - pt = time.perf_counter() - - if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = [] # free previous cookies after gpu work has been enqueued - try: - next_proc = data_get(it) - except StopIteration: - next_proc = None - - dt = time.perf_counter() - - device_str = loss.device if isinstance(loss.device, str) else f"{loss.device[0]} * {len(loss.device)}" - loss = loss.numpy().item() - - cl = time.perf_counter() - - if BENCHMARK: step_times.append(cl - st) - - tqdm.write( - f"{i:5} {((cl - st)) * 1000.0:7.2f} ms run, {(pt - st) * 1000.0:7.2f} ms python, {(dt - pt) * 1000.0:6.2f} ms fetch data, " - f"{(cl - dt) * 1000.0:7.2f} ms {device_str}, {loss:5.2f} loss, {optim.lr.numpy()[0]:.6f} LR, " - f"{GlobalCounters.mem_used / 1e9:.2f} GB used, {GlobalCounters.global_ops * 1e-9 / (cl - st):9.2f} GFLOPS" - ) - - if WANDB: - wandb.log({"lr": optim.lr.numpy(), "train/loss": loss, "train/step_time": cl - st, "train/python_time": pt - st, "train/data_time": dt - pt, - "train/cl_time": cl - dt, "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": epoch + (i + 1) / SAMPLES_PER_EPOCH}) - - st = cl - prev_cookies.append(proc) - proc, next_proc = next_proc, None # return old cookie - i += 1 - - if i == BENCHMARK: - median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2] # in seconds - estimated_total_minutes = int(median_step_time * SAMPLES_PER_EPOCH * NUM_EPOCHS / 60) - print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m") - if (TRAIN_BEAM or EVAL_BEAM) and epoch == start_epoch: break - return - - with Context(BEAM=EVAL_BEAM): - if epoch == next_eval_at: - next_eval_at += evaluate_every - eval_loss = [] - scores = [] - - for x, y in tqdm(iterate(get_val_files(), preprocessed_dir=VAL_PREPROCESSED_DIR), total=VAL_DATASET_SIZE): - eval_loss_value, score = eval_step(model, x, y) - eval_loss.append(eval_loss_value) - scores.append(score) - - scores = Tensor.mean(Tensor.stack(*scores, dim=0), axis=0).numpy() - eval_loss = Tensor.mean(Tensor.stack(*eval_loss, dim=0), axis=0).numpy() - - l1_dice, l2_dice = scores[0][-2], scores[0][-1] - mean_dice = (l2_dice + l1_dice) / 2 - - tqdm.write(f"{l1_dice} L1 dice, {l2_dice} L2 dice, {mean_dice:.3f} mean_dice, {eval_loss:5.2f} eval_loss") - - if WANDB: - wandb.log({"eval/loss": eval_loss, "eval/mean_dice": mean_dice, "epoch": epoch}) - - if mean_dice >= TARGET_METRIC: - is_successful = True - save_checkpoint(get_state_dict(model), "./ckpts/unet3d.safe") - elif mean_dice < 1e-6: - print("Model diverging. Aborting.") - diverged = True - - if not is_successful and CKPT: - if WANDB and wandb.run is not None: - fn = f"./ckpts/{time.strftime('%Y%m%d_%H%M%S')}_{wandb.run.id}_e{epoch}.safe" - else: - fn = f"./ckpts/{time.strftime('%Y%m%d_%H%M%S')}_e{epoch}.safe" - - save_checkpoint(get_state_dict(model), fn) - - if is_successful or diverged: - break - -def train_rnnt(): - # TODO: RNN-T - pass - -@TinyJit -def train_step_bert(model, optimizer, scheduler, loss_scaler:float, input_ids:Tensor, segment_ids:Tensor, attention_mask:Tensor, - masked_positions:Tensor, masked_lm_ids:Tensor, masked_lm_weights:Tensor, next_sentence_labels:Tensor, GPUS): - for t in [input_ids, segment_ids, attention_mask, masked_positions, masked_lm_ids, masked_lm_weights, next_sentence_labels]: - if len(GPUS) > 1: t.shard_(GPUS, axis=0) - else: t.to_(GPUS[0]) - optimizer.zero_grad() - - lm_logits, seq_relationship_logits = model(input_ids, attention_mask, masked_positions, segment_ids) - loss = model.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) - (loss * loss_scaler).backward() - - global_norm = Tensor([0.0], dtype=dtypes.float32, device=optimizer[0].device) - for p in optimizer.params: - p.grad = p.grad / loss_scaler - global_norm += p.grad.float().square().sum() - global_norm = global_norm.sqrt().contiguous() - for p in optimizer.params: - p.grad = (global_norm > 1.0).where((p.grad/global_norm).cast(p.grad.dtype), p.grad) - - optimizer.step() - scheduler.step() - # TODO: no to("CPU") here because it blocks and messes the python time - Tensor.realize(loss, global_norm, optimizer.optimizers[0].lr) - return loss, global_norm, optimizer.optimizers[0].lr - -@TinyJit -def eval_step_bert(model, input_ids:Tensor, segment_ids:Tensor, attention_mask:Tensor, masked_positions:Tensor, masked_lm_ids:Tensor, - masked_lm_weights:Tensor, next_sentence_labels:Tensor, GPUS): - for t in [input_ids, segment_ids, attention_mask, masked_positions, masked_lm_ids, masked_lm_weights, next_sentence_labels]: - if len(GPUS) > 1: t.shard_(GPUS, axis=0) - else: t.to_(GPUS[0]) - lm_logits, seq_relationship_logits = model(input_ids, attention_mask, masked_positions, segment_ids) - masked_lm_accuracy, seq_relationship_accuracy, masked_lm_loss, next_sentence_loss = \ - model.accuracy(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) - for t in [masked_lm_accuracy, seq_relationship_accuracy, masked_lm_loss, next_sentence_loss]: - t.to_("CPU") - Tensor.realize(masked_lm_accuracy, seq_relationship_accuracy, masked_lm_loss, next_sentence_loss) - return masked_lm_accuracy, seq_relationship_accuracy, masked_lm_loss, next_sentence_loss - -def train_bert(): - # NOTE: pip install tensorflow, wandb required - from examples.mlperf.dataloader import batch_load_train_bert, batch_load_val_bert - from examples.mlperf.helpers import get_mlperf_bert_model, get_fake_data_bert - from examples.mlperf.lr_schedulers import PolynomialDecayWithWarmup - - config = {} - BASEDIR = getenv("BASEDIR", Path(__file__).parent.parents[1] / "extra" / "datasets" / "wiki") - - GPUS = config["GPUS"] = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 1))] - print(f"training on {GPUS}") - for x in GPUS: Device[x] - seed = config["seed"] = getenv("SEED", 12345) - - INITMLPERF = getenv("INITMLPERF") - RUNMLPERF = getenv("RUNMLPERF") - BENCHMARK = getenv("BENCHMARK") - if getenv("LOGMLPERF"): - from mlperf_logging import mllog - import mlperf_logging.mllog.constants as mllog_constants - - mllog.config(filename=f"result_bert_{seed}.log") - mllog.config(root_dir=Path(__file__).parents[3].as_posix()) - MLLOGGER = mllog.get_mllogger() - MLLOGGER.logger.propagate = False - - if INITMLPERF: - assert BENCHMARK, "BENCHMARK must be set for INITMLPERF" - MLLOGGER.event(key=mllog_constants.SUBMISSION_ORG, value="tinycorp") - MLLOGGER.event(key=mllog_constants.SUBMISSION_PLATFORM, value=getenv("SUBMISSION_PLATFORM", "tinybox")) - MLLOGGER.event(key=mllog_constants.SUBMISSION_DIVISION, value=mllog_constants.CLOSED) - MLLOGGER.event(key=mllog_constants.SUBMISSION_STATUS, value=mllog_constants.ONPREM) - - MLLOGGER.event(key=mllog_constants.SUBMISSION_BENCHMARK, value=mllog_constants.BERT) - - diskcache_clear() - MLLOGGER.event(key=mllog_constants.CACHE_CLEAR, value=True) - MLLOGGER.start(key=mllog_constants.INIT_START, value=None) - - if RUNMLPERF: - MLLOGGER.start(key=mllog_constants.RUN_START, value=None) - MLLOGGER.event(key=mllog_constants.SEED, value=seed) - else: - MLLOGGER = None - - # ** hyperparameters ** - BS = config["GLOBAL_BATCH_SIZE"] = getenv("BS", 11 * len(GPUS) if dtypes.default_float in (dtypes.float16, dtypes.bfloat16) else 8 * len(GPUS)) - EVAL_BS = config["EVAL_BS"] = getenv("EVAL_BS", 1 * len(GPUS)) - max_lr = config["OPT_BASE_LEARNING_RATE"] = getenv("OPT_BASE_LEARNING_RATE", 0.000175 * math.sqrt(BS/96)) - opt_lamb_beta_1 = config["OPT_LAMB_BETA_1"] = getenv("OPT_LAMB_BETA_1", 0.9) - opt_lamb_beta_2 = config["OPT_LAMB_BETA_2"] = getenv("OPT_LAMB_BETA_2", 0.999) - - train_steps = config["TRAIN_STEPS"] = getenv("TRAIN_STEPS", 3600000 // BS) - warmup_steps = config["NUM_WARMUP_STEPS"] = getenv("NUM_WARMUP_STEPS", 1) - max_eval_steps = config["MAX_EVAL_STEPS"] = getenv("MAX_EVAL_STEPS", (10000 + EVAL_BS - 1) // EVAL_BS) # EVAL_BS * MAX_EVAL_STEPS >= 10000 - eval_step_freq = config["EVAL_STEP_FREQ"] = getenv("EVAL_STEP_FREQ", int((math.floor(0.05 * (230.23 * BS + 3000000) / 25000) * 25000) / BS)) # Round down - save_ckpt_freq = config["SAVE_CKPT_FREQ"] = getenv("SAVE_CKPT_FREQ", 1000) - keep_ckpt_amount = config["KEEP_CKPT_AMOUNT"] = getenv("KEEP_CKPT_AMOUNT", 5) - save_ckpt_dir = config["SAVE_CKPT_DIR"] = getenv("SAVE_CKPT_DIR", "./ckpts") - init_ckpt = config["INIT_CKPT_DIR"] = getenv("INIT_CKPT_DIR", BASEDIR) - - loss_scaler = config["LOSS_SCALER"] = getenv("LOSS_SCALER", 2.0**11 if dtypes.default_float == dtypes.float16 else 1.0) - decay = config["DECAY"] = getenv("DECAY", 0.01) - epsilon = config["EPSILON"] = getenv("EPSILON", 1e-6) - poly_power = config["POLY_POWER"] = getenv("POLY_POWER", 1.0) - - target, achieved = getenv("TARGET", 0.72), False - - config["DEFAULT_FLOAT"] = dtypes.default_float.name - config["DISABLE_DROPOUT"] = getenv("DISABLE_DROPOUT", 0) - config["TRAIN_BEAM"] = TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value) - config["EVAL_BEAM"] = EVAL_BEAM = getenv("EVAL_BEAM", BEAM.value) - - Tensor.manual_seed(seed) # seed for weight initialization - - assert 10000 <= (EVAL_BS * max_eval_steps), "Evaluation batchsize * max_eval_steps must greater or equal 10000 to iterate over full eval dataset" - - # ** init wandb ** - WANDB = getenv("WANDB") - if WANDB: - import wandb - wandb_args = {"id": wandb_id, "resume": "must"} if (wandb_id := getenv("WANDB_RESUME", "")) else {} - wandb.init(config=config, **wandb_args, project="MLPerf-BERT") - - # ** init model ** - - model = get_mlperf_bert_model() - if RUNMLPERF: - model.load_from_pretrained(init_ckpt) - else: - # for init, zero out all weights - for p in get_parameters(model): - p = p.assign(Tensor.zeros_like(p).contiguous()).realize() - - parameters = get_parameters(model) - if len(GPUS) > 1: - for p in parameters: - p.to_(GPUS) - - # ** Log run config ** - for key, value in config.items(): print(f'HParam: "{key}": {value}') - - # ** Optimizer ** - parameters_no_wd = [v for k, v in get_state_dict(model).items() if "bias" in k or "LayerNorm" in k] - parameters = [x for x in parameters if x not in set(parameters_no_wd)] - optimizer_wd = LAMB(parameters, lr=max_lr, b1=opt_lamb_beta_1, b2=opt_lamb_beta_2, eps=epsilon, weight_decay=decay, adam=False) - optimizer_no_wd = LAMB(parameters_no_wd, lr=max_lr, b1=opt_lamb_beta_1, b2=opt_lamb_beta_2, eps=epsilon, weight_decay=0.0, adam=False) - optimizer_group = OptimizerGroup(optimizer_wd, optimizer_no_wd) - - # ** LR scheduler ** - scheduler_wd = PolynomialDecayWithWarmup(optimizer_wd, max_lr, 0, train_steps, warmup_steps, power=poly_power) - scheduler_no_wd = PolynomialDecayWithWarmup(optimizer_no_wd, max_lr, 0, train_steps, warmup_steps, power=poly_power) - scheduler_group = LRSchedulerGroup(scheduler_wd, scheduler_no_wd) - print(f"training with batch size {BS} for one epoch with {train_steps} steps") - - # log mlperf hparams - if MLLOGGER: - if RUNMLPERF: - MLLOGGER.event(key=mllog_constants.GLOBAL_BATCH_SIZE, value=config["GLOBAL_BATCH_SIZE"]) - MLLOGGER.event(key=mllog_constants.MAX_SEQUENCE_LENGTH, value=512) - MLLOGGER.event(key="max_predictions_per_seq", value=76) - - MLLOGGER.event(key=mllog_constants.OPT_NAME, value="LAMB") - MLLOGGER.event(key=mllog_constants.OPT_BASE_LR, value=config["OPT_BASE_LEARNING_RATE"]) - MLLOGGER.event(key=mllog_constants.OPT_LAMB_WEIGHT_DECAY, value=config["DECAY"]) - MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_1, value=config["OPT_LAMB_BETA_1"]) - MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_2, value=config["OPT_LAMB_BETA_2"]) - MLLOGGER.event(key=mllog_constants.OPT_LAMB_LR_DECAY_POLY_POWER, value=config["POLY_POWER"]) - MLLOGGER.event(key=mllog_constants.OPT_LAMB_EPSILON, value=config["EPSILON"]) - - MLLOGGER.event(key=mllog_constants.OPT_LR_WARMUP_STEPS, value=config["NUM_WARMUP_STEPS"]) - MLLOGGER.event(key=mllog_constants.NUM_WARMUP_STEPS, value=config["NUM_WARMUP_STEPS"]) - MLLOGGER.event(key='start_warmup_step', value=0) - MLLOGGER.event(key='opt_learning_rate_training_steps', value=config["TRAIN_STEPS"]) - MLLOGGER.event(key=mllog_constants.GRADIENT_ACCUMULATION_STEPS, value=1) - MLLOGGER.event(key=mllog_constants.EVAL_SAMPLES, value=config["EVAL_BS"] * config["MAX_EVAL_STEPS"]) - MLLOGGER.event(key=mllog_constants.TRAIN_SAMPLES, value=config["GLOBAL_BATCH_SIZE"] * config["TRAIN_STEPS"]) - - # ** resume from checkpointing ** - start_step = 0 - previous_step = None - if ckpt:=getenv("RESUME", ""): - load_training_state(model, optimizer_group, scheduler_group, safe_load(ckpt)) - start_step = int(scheduler_wd.epoch_counter.item()) - print(f"resuming from {ckpt} at step {start_step}") - - if RUNMLPERF: - # only load real data with RUNMLPERF - eval_it = iter(batch_load_val_bert(EVAL_BS)) - train_it = iter(tqdm(batch_load_train_bert(BS), total=train_steps, disable=BENCHMARK)) - for _ in range(start_step): next(train_it) # Fast forward - else: - # repeat fake data - def repeat_fake(bs): - while True: yield get_fake_data_bert(bs) - eval_it = iter(repeat_fake(EVAL_BS)) - train_it = iter(repeat_fake(BS)) - - step_times = [] - # ** train loop ** - wc_start = time.perf_counter() - - i, train_data = start_step, next(train_it) - - if RUNMLPERF: - if MLLOGGER: - MLLOGGER.start(key=mllog_constants.EPOCH_START, value=i*BS, metadata={"epoch_num": i*BS}) - - while train_data is not None and i < train_steps and not achieved: - if getenv("TRAIN", 1): - Tensor.training = True - BEAM.value = TRAIN_BEAM - st = time.perf_counter() - GlobalCounters.reset() - with WallTimeEvent(BenchEvent.STEP): - loss, global_norm, lr = train_step_bert(model, optimizer_group, scheduler_group, loss_scaler, - train_data["input_ids"], train_data["segment_ids"], train_data["input_mask"], train_data["masked_lm_positions"], \ - train_data["masked_lm_ids"], train_data["masked_lm_weights"], train_data["next_sentence_labels"], GPUS) - - pt = time.perf_counter() - - try: - next_data = next(train_it) - except StopIteration: - next_data = None - - dt = time.perf_counter() - - device_str = parameters[0].device if isinstance(parameters[0].device, str) else f"{parameters[0].device[0]} * {len(parameters[0].device)}" - loss = loss.item() - assert not math.isnan(loss) - lr = lr.item() - - cl = time.perf_counter() - if BENCHMARK: step_times.append(cl - st) - - tqdm.write( - f"{i:5} {((cl - st)) * 1000.0:7.2f} ms run, {(pt - st) * 1000.0:7.2f} ms python, {(dt - pt) * 1000.0:6.2f} ms fetch data, " - f"{(cl - dt) * 1000.0:7.2f} ms {device_str}, {loss:5.2f} loss, {lr:.6f} LR, " - f"{GlobalCounters.mem_used / 1e9:.2f} GB used, {GlobalCounters.global_ops * 1e-9 / (cl - st):9.2f} GFLOPS") - if WANDB: - wandb.log({"lr": lr, "train/loss": loss, "train/global_norm": global_norm.item(), "train/step_time": cl - st, - "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt, - "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": (i+1)*BS}) - - train_data, next_data = next_data, None - i += 1 - - if i == BENCHMARK: - median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2] # in seconds - estimated_total_minutes = int(median_step_time * train_steps / 60) - print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m") - print(f"epoch global_ops: {train_steps * GlobalCounters.global_ops:_}, " - f"epoch global_mem: {train_steps * GlobalCounters.global_mem:_}") - - # ** eval loop ** - if i % eval_step_freq == 0 or (BENCHMARK and i == BENCHMARK) or i == train_steps: - if MLLOGGER and RUNMLPERF: - MLLOGGER.start(key=mllog_constants.EVAL_START, value=None, metadata={"epoch_num": i*BS, "step_num": i}) - if getenv("RESET_STEP"): train_step_bert.reset() - elif getenv("FREE_INTERMEDIATE", 1) and train_step_bert.captured is not None: train_step_bert.captured.free_intermediates() - eval_lm_losses = [] - eval_clsf_losses = [] - eval_lm_accs = [] - eval_clsf_accs = [] - eval_times = [] - Tensor.training = False - BEAM.value = EVAL_BEAM - - for j in tqdm(range(max_eval_steps), desc="Evaluating", total=max_eval_steps, disable=BENCHMARK): - eval_data = next(eval_it) - GlobalCounters.reset() - st = time.time() - - lm_acc, clsf_acc, lm_loss, clsf_loss = eval_step_bert(model, - eval_data["input_ids"], eval_data["segment_ids"], eval_data["input_mask"], eval_data["masked_lm_positions"], - eval_data["masked_lm_ids"], eval_data["masked_lm_weights"], eval_data["next_sentence_labels"], GPUS) - lm_acc, clsf_acc, lm_loss, clsf_loss = lm_acc.item(), clsf_acc.item(), lm_loss.item(), clsf_loss.item() - - eval_lm_losses.append(lm_loss) - eval_clsf_losses.append(clsf_loss) - eval_lm_accs.append(lm_acc) - eval_clsf_accs.append(clsf_acc) - - et = time.time() - eval_times.append(et - st) - - if BENCHMARK and (j+1) == min(BENCHMARK, max_eval_steps): - # assume INITMLPERF has BENCHMARK set - if MLLOGGER and INITMLPERF: - MLLOGGER.event(key=mllog_constants.INIT_STOP, value=None) - return - - if getenv("RESET_STEP"): eval_step_bert.reset() - elif getenv("FREE_INTERMEDIATE", 1) and eval_step_bert.captured is not None: eval_step_bert.captured.free_intermediates() - - del eval_data - avg_lm_loss = sum(eval_lm_losses) / len(eval_lm_losses) - avg_clsf_loss = sum(eval_clsf_losses) / len(eval_clsf_losses) - avg_lm_acc = sum(eval_lm_accs) / len(eval_lm_accs) - avg_clsf_acc = sum(eval_clsf_accs) / len(eval_clsf_accs) - avg_fw_time = sum(eval_times) / len(eval_times) - results = f"eval lm loss: {avg_lm_loss:.2f}, eval clsf loss: {avg_clsf_loss:.2f}, eval lm accuracy: {avg_lm_acc:.6f}, \ - eval clsf accuracy: {avg_clsf_acc:.2f}, avg eval step time: {avg_fw_time:.2f}" - tqdm.write(results) - - if WANDB: - wandb.log({"eval/lm_loss": avg_lm_loss, "eval/clsf_loss": avg_clsf_loss, "eval/lm_accuracy": avg_lm_acc, \ - "eval/clsf_accuracy": avg_clsf_acc, "eval/forward_time": avg_fw_time, "epoch": (i+1)*BS}) - - if MLLOGGER and RUNMLPERF: - MLLOGGER.end(key=mllog_constants.EVAL_STOP, value=i*BS, metadata={"epoch_count": i*BS, "step_num": i, "samples_count": config["EVAL_BS"] * config["MAX_EVAL_STEPS"]}) - MLLOGGER.event(key=mllog_constants.EVAL_ACCURACY, value=avg_lm_acc, metadata={"epoch_num": i*BS, "masked_lm_accuracy": avg_lm_acc}) - - # save model if achieved target - if not achieved and avg_lm_acc >= target: - wc_end = time.perf_counter() - if getenv("CKPT"): - if not os.path.exists(ckpt_dir := save_ckpt_dir): os.mkdir(ckpt_dir) - fn = f"{ckpt_dir}/bert-large.safe" - safe_save(get_state_dict(model), fn) - print(f" *** Model saved to {fn} ***") - - total_seconds = wc_end - wc_start - hours = int(total_seconds // 3600) - minutes = int((total_seconds % 3600) // 60) - seconds = total_seconds % 60 - print(f"Reference Convergence point reached after {i * BS} datasamples and {hours}h{minutes}m{seconds:.2f}s.") - achieved = True - if MLLOGGER and RUNMLPERF: - MLLOGGER.event(key=mllog_constants.EPOCH_STOP, value=i*BS, metadata={"epoch_num": i*BS}) - MLLOGGER.end(key=mllog_constants.RUN_STOP, metadata=dict(status=mllog_constants.SUCCESS)) - # stop once hitting the target - break - - # should not happen, BENCHMARK not properly terminated - if BENCHMARK: assert i < BENCHMARK, i - - if getenv("CKPT") and i % save_ckpt_freq == 0: - if MLLOGGER and RUNMLPERF: - if previous_step: - MLLOGGER.end(key=mllog_constants.BLOCK_STOP, value=None, metadata={"first_epoch_num": 1, "epoch_num": 1, "first_step_num": i, "step_num": i, "step_count": i - previous_step}) - MLLOGGER.start(key="checkpoint_start", value=None, metadata={"step_num": i}) - if not os.path.exists(ckpt_dir := save_ckpt_dir): os.mkdir(ckpt_dir) - if WANDB and wandb.run is not None: - fn = f"{ckpt_dir}/{time.strftime('%Y%m%d_%H%M%S')}_{wandb.run.id}.safe" - else: - fn = f"{ckpt_dir}/{time.strftime('%Y%m%d_%H%M%S')}.safe" - print(f"saving ckpt to {fn}") - safe_save(get_training_state(model, optimizer_group, scheduler_group), fn) - ckpt_files = [f for f in os.listdir(ckpt_dir) if os.path.isfile(os.path.join(ckpt_dir, f))] - ckpt_files.sort(key=lambda x: os.path.getmtime(os.path.join(ckpt_dir, x))) - while len(ckpt_files) > keep_ckpt_amount: - last = ckpt_files.pop(0) - print(f"Removing old ckpt {last}") - os.remove(os.path.join(ckpt_dir, last)) - if MLLOGGER and RUNMLPERF: - MLLOGGER.end(key="checkpoint_stop", value=None, metadata={"step_num": i}) - MLLOGGER.start(key=mllog_constants.BLOCK_START, value=None, metadata={"first_epoch_num": 1, "epoch_num": 1, "epoch_count": 1, "samples_count": i * BS, "step_num": i, "first_step_num": i+1}) - previous_step = i - -def train_maskrcnn(): - # TODO: Mask RCNN - pass - -if __name__ == "__main__": - multiprocessing.set_start_method('spawn') - - if getenv("INITMLPERF"): bench_log_manager = WallTimeEvent(BenchEvent.MLPERF_INIT) - elif getenv("RUNMLPERF"): bench_log_manager = WallTimeEvent(BenchEvent.MLPERF_RUN) - else: bench_log_manager = contextlib.nullcontext() - - with Tensor.train(): - for m in getenv("MODEL", "resnet,retinanet,unet3d,rnnt,bert,maskrcnn").split(","): - nm = f"train_{m}" - if nm in globals(): - print(f"training {m}") - with bench_log_manager: - with Profiling(enabled=getenv("PYPROFILE")): globals()[nm]() diff --git a/tinygrad/examples/mlperf/scripts/setup_kits19_dataset.sh b/tinygrad/examples/mlperf/scripts/setup_kits19_dataset.sh deleted file mode 100755 index ce967732..00000000 --- a/tinygrad/examples/mlperf/scripts/setup_kits19_dataset.sh +++ /dev/null @@ -1,19 +0,0 @@ -#!/bin/bash - -if [ -z $BASEDIR ]; then - export BASEDIR="./extra/datasets/" -fi - -cd $BASEDIR -if [ -d "kits19" ]; then - echo "kits19 dataset is already available" -else - echo "Downloading and preparing kits19 dataset at $BASEDIR" - - git clone https://github.com/neheller/kits19 - cd kits19 - pip3 install -r requirements.txt - python3 -m starter_code.get_imaging - - echo "Done" -fi diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 35bf3988..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index a13067da..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 38fd9370..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 581781b8..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 38e25d36..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index eb173a19..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_red_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh deleted file mode 100755 index a9806164..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash - -rocm-smi --setprofile compute -rocm-smi --setmclk 3 -rocm-smi --setperflevel high - -# power cap to 350W -echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_green.json b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_green.json deleted file mode 100644 index f5e69ea3..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_green.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "available", - "system_name": "tinybox green", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532 32-Core Processor", - "host_processor_core_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "NVIDIA GeForce RTX 4090", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6X", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, commit 0e8aa0e2886bf9a2d3ce093bce87305e182e6d4a", - "other_software_stack": { - "python": "3.10.12", - "CUDA": "12.4" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} diff --git a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_red.json b/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_red.json deleted file mode 100644 index b097cfe9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.0/tinycorp/systems/tinybox_red.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "available", - "system_name": "tinybox red", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532 32-Core Processor", - "host_processor_core_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "AMD Radeon RX 7900 XTX", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, commit 0e8aa0e2886bf9a2d3ce093bce87305e182e6d4a", - "other_software_stack": { - "python": "3.10.12", - "ROCm": "6.1" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md deleted file mode 100644 index e7937365..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md +++ /dev/null @@ -1,73 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install tqdm and tensorflow. -``` -pip install tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr + increase mes timeout. -Install the custom amdgpu driver per [README](https://github.com/nimlgen/amdgpu_ubuntu_22_04/blob/v6.1.3/readme.md) - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### One time setup - -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh -``` - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 8814f629..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=4 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=512 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index 8df5f5da..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=4 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=512 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 8adeb7a8..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=4 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=512 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md deleted file mode 100644 index e7937365..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md +++ /dev/null @@ -1,73 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install tqdm and tensorflow. -``` -pip install tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr + increase mes timeout. -Install the custom amdgpu driver per [README](https://github.com/nimlgen/amdgpu_ubuntu_22_04/blob/v6.1.3/readme.md) - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### One time setup - -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh -``` - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 649d3942..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=3 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 9a6ee034..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=3 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index 9ca38adb..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=66 EVAL_BS=6 - -export BEAM=3 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_red_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh deleted file mode 100755 index 3d687cdb..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash - -rocm-smi --setprofile compute -rocm-smi --setmclk 3 -rocm-smi --setperflevel high - -# power cap to 350W -# echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 35bf3988..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index a13067da..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 38fd9370..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 581781b8..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 38e25d36..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index eb173a19..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export LAZYCACHE=0 RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_red_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh deleted file mode 100755 index a9806164..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash - -rocm-smi --setprofile compute -rocm-smi --setmclk 3 -rocm-smi --setperflevel high - -# power cap to 350W -echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_green.json b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_green.json deleted file mode 100644 index bb1ebba9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_green.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox green", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532 32-Core Processor", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "NVIDIA GeForce RTX 4090", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6X", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, commit b5546912e24e0a864b35924da4efa5d71cfe368b", - "other_software_stack": { - "python": "3.10.12", - "CUDA": "12.4" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} diff --git a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_red.json b/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_red.json deleted file mode 100644 index 6db104a7..00000000 --- a/tinygrad/examples/mlperf/training_submission_v4.1/tinycorp/systems/tinybox_red.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox red", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532 32-Core Processor", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "AMD Radeon RX 7900 XTX", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, commit b5546912e24e0a864b35924da4efa5d71cfe368b", - "other_software_stack": { - "python": "3.10.12", - "ROCm": "6.1.3" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh deleted file mode 100755 index 35080c34..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128 - -export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -# export BEAM_LOG_SURPASS_MAX=1 -# export BASEDIR="/raid/datasets/wiki" - -export RESET_STEP=1 -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh deleted file mode 100755 index dff326fc..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh deleted file mode 100755 index ee43e95d..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 - -# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 -export TRAIN_STEPS=3900 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh deleted file mode 100755 index 359143fa..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_8xMI300X" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 - -# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 -export TRAIN_STEPS=3900 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_8xMI300x_${DATETIME}_${SEED}.log" - -# init # TODO: without DEBUG=2 it hangs -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 DEBUG=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 1205c210..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BEAM_LOG_SURPASS_MAX=1 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index f71688ab..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 62422586..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index f99bf302..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BEAM_LOG_SURPASS_MAX=1 -export BASEDIR="/raid/datasets/wiki" - -export RESET_STEP=1 -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 7f577c9c..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index 5c3f28c0..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_red_${DATETIME}_${SEED}.log" - -export HCQDEV_WAIT_TIMEOUT_MS=100000 # prevents hang? - -# init -sleep 5 && sudo rmmod amdgpu || true -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -# TODO: AM driver resulted in nan -sudo modprobe amdgpu -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 2319da3f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index ebe927c3..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 1c53e56e..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=${LOGMLPERF:-1} - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 7bcbec2f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=${DEBUG:-2} - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index aad23e43..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index f8568731..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=${LOGMLPERF:-1} - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_red_${DATETIME}_${SEED}.log" - -# init -sleep 5 && sudo rmmod amdgpu || true -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh deleted file mode 100755 index a9806164..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash - -rocm-smi --setprofile compute -rocm-smi --setmclk 3 -rocm-smi --setperflevel high - -# power cap to 350W -echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md deleted file mode 100644 index ce1ac9b9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,38 +0,0 @@ -# 1. Problem - -This problem uses RetinaNet for SSD. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -Also install the following dependencies: -``` -pip install tqdm numpy pycocotools boto3 pandas torch torchvision -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download data - -Run the following: -``` -BASEDIR=/raid/datasets/openimages python3 extra/datasets/openimages.py -``` - -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 6e25bb96..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=5 DEBUG=2 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index 7a3ee0df..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export WANDB=1 PARALLEL=0 -export RUNMLPERF=1 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index d60f68e8..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/bash -set -e # Exit on any error - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export TRAIN_BEAM=2 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/openimages" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="retinanet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 97aa5155..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=5 DEBUG=2 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 5fb4d109..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export WANDB=1 PARALLEL=0 -export RUNMLPERF=1 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_8xMI300X.json b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_8xMI300X.json deleted file mode 100644 index 1e0f7894..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_8xMI300X.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox 8xMI300X", - "number_of_nodes": "1", - "host_processors_per_node": "2", - "host_processor_model_name": "AMD EPYC 9354", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "2304GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "3x 4TB raid array", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "24x 96GB DDR5", - "accelerators_per_node": "8", - "accelerator_model_name": "AMD Instinct MI300X 192GB HBM3", - "accelerator_host_interconnect": "PCIe 5.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "HBM3", - "accelerator_memory_capacity": "192GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.16", - "ROCm": "3.0.0+94441cb" - }, - "operating_system": "Ubuntu 24.04.1 LTS", - "sw_notes": "" - } \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_green.json b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_green.json deleted file mode 100644 index 24cbce1f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_green.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox green", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "NVIDIA GeForce RTX 4090", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6X", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.12", - "CUDA": "12.4" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_red.json b/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_red.json deleted file mode 100644 index 58b6efe7..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.0/tinycorp/systems/tinybox_red.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox red", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "AMD Radeon RX 7900 XTX", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.12" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh deleted file mode 100755 index 35080c34..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128 - -export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -# export BEAM_LOG_SURPASS_MAX=1 -# export BASEDIR="/raid/datasets/wiki" - -export RESET_STEP=1 -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh deleted file mode 100755 index dff326fc..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh deleted file mode 100755 index ee43e95d..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 - -# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 -export TRAIN_STEPS=3900 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh deleted file mode 100755 index ac814823..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_8xMI300X" -export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 - -# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54 -export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 -export TRAIN_STEPS=3900 - -export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_8xMI300x_${DATETIME}_${SEED}.log" - -# init # TODO: without DEBUG=2 it hangs -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 DEBUG=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 1205c210..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BEAM_LOG_SURPASS_MAX=1 -export BASEDIR="/raid/datasets/wiki" - -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index f71688ab..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 52d85eeb..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." NV=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md deleted file mode 100644 index 844b90f9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/README.md +++ /dev/null @@ -1,69 +0,0 @@ -# 1. Problem - -This problem uses BERT for NLP. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` -Also install gdown (for dataset), numpy, tqdm and tensorflow. -``` -pip install gdown numpy tqdm tensorflow -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download and verify data - -### 1. Download raw data - -``` -BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py -``` - -### 2. Preprocess train and validation data - -Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. - -#### Training: -``` -BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all -``` - -Generating a specific topic (Between 0 and 499) -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42 -``` - -#### Validation: -``` -BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval -``` -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh -``` - -### tinybox_red - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh -``` -### tinybox_8xMI300X - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh -``` \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index f99bf302..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BEAM_LOG_SURPASS_MAX=1 -export BASEDIR="/raid/datasets/wiki" - -export RESET_STEP=1 -export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 7f577c9c..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -export WANDB=1 PARALLEL=0 - -RUNMLPERF=1 python3 examples/mlperf/model_train.py \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index e3667e66..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." AMD=1 -export MODEL="bert" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 - -export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/wiki" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="bert_red_${DATETIME}_${SEED}.log" - -export HCQDEV_WAIT_TIMEOUT_MS=100000 # prevents hang? - -# init -sleep 5 && sudo rmmod amdgpu || true -BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -# TODO: AM driver resulted in nan -sudo modprobe amdgpu -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 2319da3f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=2 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index ebe927c3..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 9c719328..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." NV=1 -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=10 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=${LOGMLPERF:-1} - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md deleted file mode 100644 index d380cec5..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/README.md +++ /dev/null @@ -1,50 +0,0 @@ -# 1. Problem - -This problem uses the ResNet-50 CNN to do image classification. - -## Requirements - -Install tinygrad and mlperf-logging from master. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -### tinybox_red -Disable cwsr -This is the default on production tinybox red. -``` -sudo vi /etc/modprobe.d/amdgpu.conf -cat < /etc/modprobe.d/amdgpu.conf -options amdgpu cwsr_enable=0 -EOF -sudo update-initramfs -u -sudo reboot - -# validate -sudo cat /sys/module/amdgpu/parameters/cwsr_enable #= 0 -``` - -# 2. Directions - -## Steps to download and verify data - -``` -IMGNET_TRAIN=1 python3 extra/datasets/imagenet_download.py -``` - -## Steps for one time setup - -### tinybox_red -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh -``` - -## Steps to run benchmark -``` -examples/mlperf/training_submission_v4.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 7bcbec2f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=10 DEBUG=${DEBUG:-2} - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index aad23e43..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export EVAL_START_EPOCH=3 EVAL_FREQ=4 - -export WANDB=1 PARALLEL=0 - -python3 examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh deleted file mode 100755 index 7a93d435..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." AMD=1 -export MODEL="resnet" -export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192 - -export RESET_STEP=0 - -export TRAIN_BEAM=4 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=2000 BEAM_UPCAST_MAX=96 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -# pip install -e ".[mlperf]" -export LOGMLPERF=${LOGMLPERF:-1} - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="resnet_red_${DATETIME}_${SEED}.log" - -# init -sleep 5 && sudo rmmod amdgpu || true -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 EVAL_START_EPOCH=3 EVAL_FREQ=4 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh deleted file mode 100755 index a9806164..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash - -rocm-smi --setprofile compute -rocm-smi --setmclk 3 -rocm-smi --setperflevel high - -# power cap to 350W -echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md deleted file mode 100644 index ce1ac9b9..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/README.md +++ /dev/null @@ -1,38 +0,0 @@ -# 1. Problem - -This problem uses RetinaNet for SSD. - -## Requirements - -Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0. -``` -git clone https://github.com/tinygrad/tinygrad.git -python3 -m pip install -e ".[mlperf]" -``` - -Also install the following dependencies: -``` -pip install tqdm numpy pycocotools boto3 pandas torch torchvision -``` - -### tinybox_green -Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md) -This is the default on production tinybox green. - -# 2. Directions - -## Steps to download data - -Run the following: -``` -BASEDIR=/raid/datasets/openimages python3 extra/datasets/openimages.py -``` - -## Running - -### tinybox_green - -#### Steps to run benchmark -``` -examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh -``` diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh deleted file mode 100755 index 6e25bb96..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=5 DEBUG=2 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh deleted file mode 100755 index 7a3ee0df..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export WANDB=1 PARALLEL=0 -export RUNMLPERF=1 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh deleted file mode 100755 index 74cdc87a..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash -set -e # Exit on any error -set -o pipefail # Make pipeline fail if any command fails - -export PYTHONPATH="." NV=1 -export MODEL="retinanet" -export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 - -export TRAIN_BEAM=2 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 -export IGNORE_JIT_FIRST_BEAM=1 -export BASEDIR="/raid/datasets/openimages" - -# pip install -e ".[mlperf]" -export LOGMLPERF=1 - -export SEED=$RANDOM -DATETIME=$(date "+%m%d%H%M") -LOGFILE="retinanet_green_${DATETIME}_${SEED}.log" - -# init -BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE - -# run -PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh deleted file mode 100755 index 97aa5155..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export BENCHMARK=5 DEBUG=2 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh deleted file mode 100755 index 5fb4d109..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -export PYTHONPATH="." AMD=1 -export MODEL="retinanet" -export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96 -export BASEDIR="/raid/datasets/openimages" - -# export RESET_STEP=0 - -export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0 - -export WANDB=1 PARALLEL=0 -export RUNMLPERF=1 - -python examples/mlperf/model_train.py diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_8xMI300X.json b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_8xMI300X.json deleted file mode 100644 index 1e0f7894..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_8xMI300X.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox 8xMI300X", - "number_of_nodes": "1", - "host_processors_per_node": "2", - "host_processor_model_name": "AMD EPYC 9354", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "2304GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "3x 4TB raid array", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "24x 96GB DDR5", - "accelerators_per_node": "8", - "accelerator_model_name": "AMD Instinct MI300X 192GB HBM3", - "accelerator_host_interconnect": "PCIe 5.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "HBM3", - "accelerator_memory_capacity": "192GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.16", - "ROCm": "3.0.0+94441cb" - }, - "operating_system": "Ubuntu 24.04.1 LTS", - "sw_notes": "" - } \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_green.json b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_green.json deleted file mode 100644 index 24cbce1f..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_green.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox green", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "NVIDIA GeForce RTX 4090", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6X", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.12", - "CUDA": "12.4" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} \ No newline at end of file diff --git a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_red.json b/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_red.json deleted file mode 100644 index 58b6efe7..00000000 --- a/tinygrad/examples/mlperf/training_submission_v5.1/tinycorp/systems/tinybox_red.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "submitter": "tinycorp", - "division": "closed", - "status": "Available on-premise", - "system_name": "tinybox red", - "number_of_nodes": "1", - "host_processors_per_node": "1", - "host_processor_model_name": "AMD EPYC 7532", - "host_processor_core_count": "32", - "host_processor_vcpu_count": "64", - "host_processor_frequency": "", - "host_processor_caches": "", - "host_processor_interconnect": "", - "host_memory_capacity": "128GB", - "host_storage_type": "NVMe SSD", - "host_storage_capacity": "4 TB raid array + 1 TB boot", - "host_networking": "", - "host_networking_topology": "", - "host_memory_configuration": "8x 16GB DDR4", - "accelerators_per_node": "6", - "accelerator_model_name": "AMD Radeon RX 7900 XTX", - "accelerator_host_interconnect": "PCIe 4.0 x16", - "accelerator_frequency": "", - "accelerator_on-chip_memories": "", - "accelerator_memory_configuration": "GDDR6", - "accelerator_memory_capacity": "24GB", - "accelerator_interconnect": "", - "accelerator_interconnect_topology": "", - "cooling": "air", - "hw_notes": "", - "framework": "tinygrad, branch mlperf_training_v5.0", - "other_software_stack": { - "python": "3.10.12" - }, - "operating_system": "Ubuntu 22.04.4", - "sw_notes": "" -} \ No newline at end of file diff --git a/tinygrad/examples/mnist_gan.py b/tinygrad/examples/mnist_gan.py deleted file mode 100644 index 8e47942a..00000000 --- a/tinygrad/examples/mnist_gan.py +++ /dev/null @@ -1,107 +0,0 @@ -from pathlib import Path -import numpy as np -import torch -from torchvision.utils import make_grid, save_image -from tinygrad.nn.state import get_parameters -from tinygrad.tensor import Tensor -from tinygrad.helpers import trange -from tinygrad.nn import optim -from extra.datasets import fetch_mnist - -class LinearGen: - def __init__(self): - self.l1 = Tensor.scaled_uniform(128, 256) - self.l2 = Tensor.scaled_uniform(256, 512) - self.l3 = Tensor.scaled_uniform(512, 1024) - self.l4 = Tensor.scaled_uniform(1024, 784) - - def forward(self, x): - x = x.dot(self.l1).leaky_relu(0.2) - x = x.dot(self.l2).leaky_relu(0.2) - x = x.dot(self.l3).leaky_relu(0.2) - x = x.dot(self.l4).tanh() - return x - -class LinearDisc: - def __init__(self): - self.l1 = Tensor.scaled_uniform(784, 1024) - self.l2 = Tensor.scaled_uniform(1024, 512) - self.l3 = Tensor.scaled_uniform(512, 256) - self.l4 = Tensor.scaled_uniform(256, 2) - - def forward(self, x): - # balance the discriminator inputs with const bias (.add(1)) - x = x.dot(self.l1).add(1).leaky_relu(0.2).dropout(0.3) - x = x.dot(self.l2).leaky_relu(0.2).dropout(0.3) - x = x.dot(self.l3).leaky_relu(0.2).dropout(0.3) - x = x.dot(self.l4).log_softmax() - return x - -def make_batch(images): - sample = np.random.randint(0, len(images), size=(batch_size)) - image_b = images[sample].reshape(-1, 28*28).astype(np.float32) / 127.5 - 1.0 - return Tensor(image_b) - -def make_labels(bs, col, val=-2.0): - y = np.zeros((bs, 2), np.float32) - y[range(bs), [col] * bs] = val # Can we do label smoothing? i.e -2.0 changed to -1.98789. - return Tensor(y) - -def train_discriminator(optimizer, data_real, data_fake): - real_labels = make_labels(batch_size, 1) - fake_labels = make_labels(batch_size, 0) - optimizer.zero_grad() - output_real = discriminator.forward(data_real) - output_fake = discriminator.forward(data_fake) - loss_real = (output_real * real_labels).mean() - loss_fake = (output_fake * fake_labels).mean() - loss_real.backward() - loss_fake.backward() - optimizer.step() - return (loss_real + loss_fake).numpy() - -def train_generator(optimizer, data_fake): - real_labels = make_labels(batch_size, 1) - optimizer.zero_grad() - output = discriminator.forward(data_fake) - loss = (output * real_labels).mean() - loss.backward() - optimizer.step() - return loss.numpy() - -if __name__ == "__main__": - # data for training and validation - images_real = np.vstack(fetch_mnist()[::2]) - ds_noise = Tensor.randn(64, 128, requires_grad=False) - # parameters - epochs, batch_size, k = 300, 512, 1 - sample_interval = epochs // 10 - n_steps = len(images_real) // batch_size - # models and optimizer - generator = LinearGen() - discriminator = LinearDisc() - # path to store results - output_dir = Path(".").resolve() / "outputs" - output_dir.mkdir(exist_ok=True) - # optimizers - optim_g = optim.Adam(get_parameters(generator),lr=0.0002, b1=0.5) # 0.0002 for equilibrium! - optim_d = optim.Adam(get_parameters(discriminator),lr=0.0002, b1=0.5) - # training loop - Tensor.training = True - for epoch in (t := trange(epochs)): - loss_g, loss_d = 0.0, 0.0 - for _ in range(n_steps): - data_real = make_batch(images_real) - for step in range(k): # Try with k = 5 or 7. - noise = Tensor.randn(batch_size, 128) - data_fake = generator.forward(noise).detach() - loss_d += train_discriminator(optim_d, data_real, data_fake) - noise = Tensor.randn(batch_size, 128) - data_fake = generator.forward(noise) - loss_g += train_generator(optim_g, data_fake) - if (epoch + 1) % sample_interval == 0: - fake_images = generator.forward(ds_noise).detach().numpy() - fake_images = (fake_images.reshape(-1, 1, 28, 28) + 1) / 2 # 0 - 1 range. - save_image(make_grid(torch.tensor(fake_images)), output_dir / f"image_{epoch+1}.jpg") - t.set_description(f"Generator loss: {loss_g/n_steps}, Discriminator loss: {loss_d/n_steps}") - print("Training Completed!") diff --git a/tinygrad/examples/olmoe.py b/tinygrad/examples/olmoe.py deleted file mode 100644 index 9789cb1c..00000000 --- a/tinygrad/examples/olmoe.py +++ /dev/null @@ -1,94 +0,0 @@ -# https://arxiv.org/pdf/2409.02060 -import time -import numpy as np -np.set_printoptions(suppress=True, linewidth=1000) -import functools -from tinygrad import Tensor, nn, Device, GlobalCounters -from tinygrad.helpers import Timing, getenv -from extra.models.llama import Transformer, convert_from_huggingface - -class MixtureFeedForward: - def __init__(self, num_experts:int, activated_experts:int, dim:int, hidden_dim:int, linear=nn.Linear): - self.activated_experts = activated_experts - self.gate = nn.Linear(dim, num_experts, bias=False) - self.up_proj = Tensor.zeros(num_experts, hidden_dim, dim, dtype='bfloat16') - self.down_proj = Tensor.zeros(num_experts, dim, hidden_dim, dtype='bfloat16') - self.gate_proj = Tensor.zeros(num_experts, hidden_dim, dim, dtype='bfloat16') - def __call__(self, x:Tensor) -> Tensor: - assert x.shape[0] == 1, "only BS=1" - assert x.shape[1] == 1, "only length=1" - g = self.gate(x).float().softmax(-1) - - g = g.squeeze() # (BS, length, num_experts) -> (num_experts,) - probs, sel = g.topk(self.activated_experts) - - # run MoE - x_up_gate = x.dot(self.gate_proj[sel].permute(0,2,1)).silu() * x.dot(self.up_proj[sel].permute(0,2,1)) - x_down = x_up_gate.dot(self.down_proj[sel].permute(0,2,1)) - return (x_down.float() * probs.reshape(self.activated_experts, 1, 1)).sum(axis=0) - -# model is bf16, 1.3B active, 6.9B total -# M3 Max is 400 GB/s, so 400/2.6 = ~154 tok/s - -def fetch_weights() -> dict[str, Tensor]: - # TODO: make this lazy so the 3 fetches can happen in parallel - m1 = Tensor.from_url("https://huggingface.co/allenai/OLMoE-1B-7B-0924/resolve/main/model-00001-of-00003.safetensors").to(Device.DEFAULT) - m2 = Tensor.from_url("https://huggingface.co/allenai/OLMoE-1B-7B-0924/resolve/main/model-00002-of-00003.safetensors").to(Device.DEFAULT) - m3 = Tensor.from_url("https://huggingface.co/allenai/OLMoE-1B-7B-0924/resolve/main/model-00003-of-00003.safetensors").to(Device.DEFAULT) - return {**nn.state.safe_load(m1), **nn.state.safe_load(m2), **nn.state.safe_load(m3)} - -if __name__ == "__main__": - if getenv("TORCH"): - from transformers import OlmoeForCausalLM, AutoTokenizer - model = OlmoeForCausalLM.from_pretrained("allenai/OLMoE-1B-7B-0924") - tokenizer = AutoTokenizer.from_pretrained("allenai/OLMoE-1B-7B-0924") - inputs = tokenizer("Hello", return_tensors="pt") - generate_ids = model.generate(inputs.input_ids, max_length=30) - out = tokenizer.batch_decode(generate_ids, skip_special_tokens=True, clean_up_tokenization_spaces=False)[0] - print(out) - exit(0) - - with Timing("create model: "): - model = Transformer(n_layers=16, dim=2048, hidden_dim=1024, n_heads=16, norm_eps=1e-5, qk_norm=1e-5, max_context=1024, - vocab_size=50304, feed_forward=functools.partial(MixtureFeedForward, 64, 8)) - model_state_dict = nn.state.get_state_dict(model) - del model_state_dict['freqs_cis'] - - with Timing("load weights to GPU: "): - nhf_state = convert_from_huggingface(fetch_weights(), 16, 16, 16) - # NOTE: i'm not sure this actually needs float32, it may just change the type of things downstream from it. but doesn't match torch w/o this - for needs_float32 in ['tok_embeddings.weight']: nhf_state[needs_float32] = nhf_state[needs_float32].float() - print(f"ram used: {GlobalCounters.mem_used/1e9:.2f} GB") - - with Timing("unpack weights: "): - nn.state.load_state_dict(model, nhf_state, verbose=False, strict=False, consume=True, realize=False) - assert len(nhf_state) == 0 - Tensor.realize(*list(nn.state.get_state_dict(model).values())) - print(f"ram used: {GlobalCounters.mem_used/1e9:.2f} GB") - - count = 30 - temperature = 0 - - with Timing("load tokenizer: "): - from transformers import AutoTokenizer - tokenizer = AutoTokenizer.from_pretrained("allenai/OLMoE-1B-7B-0924") - - toks = [12092] - start_pos = 0 - timings = [] - for i in range(count): - GlobalCounters.reset() - st = time.perf_counter() - tok = model(Tensor([toks[start_pos:]]), start_pos, temperature).item() - timings.append(time.perf_counter()-st) - toks.append(tok) - start_pos += 1 - print(toks) - print(tokenizer.decode(toks)) - print(f"fastest token {min(timings)*1e3:.2f} ms, {1/min(timings):.1f} tok/s") - - if temperature == 0: - # Hello, I am a newbie to this forum and I am trying to get a better understanding of the different types of data that can be stored in a - assert toks == [12092, 13, 309, 717, 247, 747, 17782, 281, 436, 12209, 285, 309, 717, 2820, 281, 755, - 247, 1805, 4685, 273, 253, 1027, 3510, 273, 941, 326, 476, 320, 7141, 275, 247], "BAD OUTPUT!" - diff --git a/tinygrad/examples/openelm.py b/tinygrad/examples/openelm.py deleted file mode 100644 index 71e9cd89..00000000 --- a/tinygrad/examples/openelm.py +++ /dev/null @@ -1,118 +0,0 @@ -import json, pprint -from tinygrad import fetch, nn, Tensor -from tinygrad.helpers import DEBUG - -class FeedForward: - def __init__(self, model_dim, intermediate_dim): - self.proj_1 = nn.Linear(model_dim, 2*intermediate_dim, bias=False) - self.proj_2 = nn.Linear(intermediate_dim, model_dim, bias=False) - - def __call__(self, x): - y_12 = self.proj_1(x) - y_1, y_2 = y_12.chunk(2, dim=-1) - return self.proj_2(y_1.silu() * y_2) - -# NOTE: this RoPE doesn't match LLaMA's? -def _rotate_half(x: Tensor) -> Tensor: - x1, x2 = x.chunk(2, dim=-1) - return Tensor.cat(-x2, x1, dim=-1) - -def _apply_rotary_pos_emb(x: Tensor, pos_sin: Tensor, pos_cos: Tensor) -> Tensor: - return (x * pos_cos) + (_rotate_half(x) * pos_sin) - -class Attention: - def __init__(self, model_dim, num_query_heads, num_kv_heads, head_dim): - self.qkv_proj = nn.Linear(model_dim, (num_query_heads + num_kv_heads*2) * head_dim, bias=False) - self.num_query_heads, self.num_kv_heads = num_query_heads, num_kv_heads - self.head_dim = head_dim - self.q_norm = nn.RMSNorm(head_dim) - self.k_norm = nn.RMSNorm(head_dim) - self.out_proj = nn.Linear(num_query_heads * head_dim, model_dim, bias=False) - - def __call__(self, x:Tensor) -> Tensor: - batch_size, seq_len, embed_dim = x.shape - qkv = self.qkv_proj(x) - qkv = qkv.reshape(batch_size, seq_len, self.num_query_heads+self.num_kv_heads*2, self.head_dim).transpose(1, 2) - xq,xk,xv = qkv.split([self.num_query_heads, self.num_kv_heads, self.num_kv_heads], dim=1) - xq = self.q_norm(xq) - xk = self.k_norm(xk) - - # add positional embedding (how many kernels is this?) - freq_constant = 10000 - inv_freq = 1.0 / (freq_constant ** (Tensor.arange(0, self.head_dim, 2) / self.head_dim)) - pos_index_theta = Tensor.einsum("i,j->ij", Tensor.arange(seq_len), inv_freq) - emb = Tensor.cat(pos_index_theta, pos_index_theta, dim=-1) - cos_emb, sin_emb = emb.cos()[None, None, :, :], emb.sin()[None, None, :, :] - xq = _apply_rotary_pos_emb(xq, sin_emb, cos_emb) - xk = _apply_rotary_pos_emb(xk, sin_emb, cos_emb) - - # grouped-query attention - num_groups = self.num_query_heads // self.num_kv_heads - xk = xk.repeat_interleave(num_groups, dim=1) - xv = xv.repeat_interleave(num_groups, dim=1) - - # masked attention - #start_pos = 0 - #mask = Tensor.full((1, 1, seq_len, start_pos+seq_len), float("-inf"), dtype=xq.dtype, device=xq.device).triu(start_pos+1) - #attn_output = xq.scaled_dot_product_attention(xk, xv, mask).transpose(1, 2) - - # causal is fine, no mask needed - attn_output = xq.scaled_dot_product_attention(xk, xv, is_causal=True).transpose(1, 2) - return self.out_proj(attn_output.reshape(batch_size, seq_len, self.num_query_heads * self.head_dim)) - -class Layer: - def __init__(self, model_dim, intermediate_dim, num_query_heads, num_kv_heads, head_dim): - self.ffn = FeedForward(model_dim, intermediate_dim) - self.attn = Attention(model_dim, num_query_heads, num_kv_heads, head_dim) - self.ffn_norm = nn.RMSNorm(model_dim) - self.attn_norm = nn.RMSNorm(model_dim) - - def __call__(self, x:Tensor) -> Tensor: # (batch, seq_len, embed_dim) - x = x + self.attn(self.attn_norm(x)) - x = x + self.ffn(self.ffn_norm(x)) - return x - -# stupidly complex -def make_divisible(v, divisor): - new_v = max(divisor, int(v + divisor / 2) // divisor * divisor) - if new_v < 0.9 * v: new_v += divisor - return new_v - -class Transformer: - def __init__(self, cfg): - if DEBUG >= 3: pprint.pp(cfg) - self.layers = [Layer(cfg['model_dim'], make_divisible(int(cfg["model_dim"] * cfg['ffn_multipliers'][i]), cfg['ffn_dim_divisor']), - cfg['num_query_heads'][i], cfg['num_kv_heads'][i], cfg['head_dim']) for i in range(cfg['num_transformer_layers'])] - self.norm = nn.RMSNorm(cfg['model_dim']) - self.token_embeddings = nn.Embedding(cfg['vocab_size'], cfg['model_dim']) - - def __call__(self, tokens:Tensor): - # _bsz, seqlen = tokens.shape - x = self.token_embeddings(tokens) - for l in self.layers: x = l(x) - return self.norm(x) @ self.token_embeddings.weight.T - -if __name__ == "__main__": - #model_name = "OpenELM-270M-Instruct" - model_name = "OpenELM-270M" # this is fp32 - model = Transformer(json.loads(fetch(f"https://huggingface.co/apple/{model_name}/resolve/main/config.json?download=true").read_bytes())) - weights = nn.state.safe_load(fetch(f"https://huggingface.co/apple/{model_name}/resolve/main/model.safetensors?download=true")) - if DEBUG >= 3: - for k, v in weights.items(): print(k, v.shape) - nn.state.load_state_dict(model, {k.removeprefix("transformer."):v for k,v in weights.items()}) - - from sentencepiece import SentencePieceProcessor - tokenizer = SentencePieceProcessor(fetch("https://github.com/karpathy/llama2.c/raw/master/tokenizer.model").as_posix()) - toks = [tokenizer.bos_id()] + tokenizer.encode("Some car brands include") - for i in range(100): - ttoks = Tensor([toks]) - out = model(ttoks).realize() - t0 = out[0].argmax(axis=-1).tolist() - toks.append(t0[-1]) - # hmmm...passthrough still doesn't match (it shouldn't, it outputs the most likely) - print(tokenizer.decode(toks)) - #print(toks) - #print(tokenizer.decode(t0)) - #print(t0) - - diff --git a/tinygrad/examples/openpilot/compile3.py b/tinygrad/examples/openpilot/compile3.py deleted file mode 100644 index 9f284ed6..00000000 --- a/tinygrad/examples/openpilot/compile3.py +++ /dev/null @@ -1,154 +0,0 @@ -import os, sys, pickle, time -import numpy as np -if "FLOAT16" not in os.environ: os.environ["FLOAT16"] = "1" -if "IMAGE" not in os.environ: os.environ["IMAGE"] = "2" -if "NOLOCALS" not in os.environ: os.environ["NOLOCALS"] = "1" -if "JIT_BATCH_SIZE" not in os.environ: os.environ["JIT_BATCH_SIZE"] = "0" - -from tinygrad import fetch, Tensor, TinyJit, Context, GlobalCounters, Device -from tinygrad.helpers import DEBUG, getenv -from tinygrad.tensor import _from_np_dtype -from tinygrad.engine.realize import CompiledRunner - -import onnx -from onnx.helper import tensor_dtype_to_np_dtype -from tinygrad.frontend.onnx import OnnxRunner, onnx_load - -OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx" -OUTPUT = sys.argv[2] if len(sys.argv) > 2 else "/tmp/openpilot.pkl" - -def compile(onnx_file): - onnx_model = onnx_load(onnx_file) - run_onnx = OnnxRunner(onnx_model) - print("loaded model") - - input_shapes = {inp.name:tuple(x.dim_value for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input} - input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input} - # Float inputs and outputs to tinyjits for openpilot are always float32 - input_types = {k:(np.float32 if v==np.float16 else v) for k,v in input_types.items()} - Tensor.manual_seed(100) - new_inputs = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in sorted(input_shapes.items())} - new_inputs_numpy = {k:v.numpy() for k,v in new_inputs.items()} - print("created tensors") - - run_onnx_jit = TinyJit(lambda **kwargs: - next(iter(run_onnx({k:v.to(Device.DEFAULT) for k,v in kwargs.items()}).values())).cast('float32'), prune=True) - for i in range(3): - GlobalCounters.reset() - print(f"run {i}") - inputs = {**{k:v.clone() for k,v in new_inputs.items() if 'img' in k}, - **{k:Tensor(v, device="NPY").realize() for k,v in new_inputs_numpy.items() if 'img' not in k}} - with Context(DEBUG=max(DEBUG.value, 2 if i == 2 else 1)): - ret = run_onnx_jit(**inputs).numpy() - # copy i == 1 so use of JITBEAM is okay - if i == 1: test_val = np.copy(ret) - print(f"captured {len(run_onnx_jit.captured.jit_cache)} kernels") - np.testing.assert_equal(test_val, ret, "JIT run failed") - print("jit run validated") - - # checks from compile2 - kernel_count = 0 - read_image_count = 0 - gated_read_image_count = 0 - for ei in run_onnx_jit.captured.jit_cache: - if isinstance(ei.prg, CompiledRunner): - kernel_count += 1 - read_image_count += ei.prg.p.src.count("read_image") - gated_read_image_count += ei.prg.p.src.count("?read_image") - print(f"{kernel_count=}, {read_image_count=}, {gated_read_image_count=}") - if (allowed_kernel_count:=getenv("ALLOWED_KERNEL_COUNT", -1)) != -1: - assert kernel_count <= allowed_kernel_count, f"too many kernels! {kernel_count=}, {allowed_kernel_count=}" - if (allowed_read_image:=getenv("ALLOWED_READ_IMAGE", -1)) != -1: - assert read_image_count == allowed_read_image, f"different read_image! {read_image_count=}, {allowed_read_image=}" - if (allowed_gated_read_image:=getenv("ALLOWED_GATED_READ_IMAGE", -1)) != -1: - assert gated_read_image_count <= allowed_gated_read_image, f"too many gated read_image! {gated_read_image_count=}, {allowed_gated_read_image=}" - - with open(OUTPUT, "wb") as f: - pickle.dump(run_onnx_jit, f) - mdl_sz = os.path.getsize(onnx_file) - pkl_sz = os.path.getsize(OUTPUT) - print(f"mdl size is {mdl_sz/1e6:.2f}M") - print(f"pkl size is {pkl_sz/1e6:.2f}M") - print("**** compile done ****") - return test_val - -def test_vs_compile(run, new_inputs, test_val=None): - new_inputs_numpy = {k:v.numpy() for k,v in new_inputs.items()} - - # create fake "from_blob" tensors for the inputs, and wrapped NPY tensors for the numpy inputs (these have the same underlying memory) - inputs = {**{k:v for k,v in new_inputs.items() if 'img' in k}, - **{k:Tensor(v, device="NPY").realize() for k,v in new_inputs_numpy.items() if 'img' not in k}} - - # run 20 times - for _ in range(20): - st = time.perf_counter() - out = run(**inputs) - mt = time.perf_counter() - val = out.numpy() - et = time.perf_counter() - print(f"enqueue {(mt-st)*1e3:6.2f} ms -- total run {(et-st)*1e3:6.2f} ms") - print(out, val.shape, val.dtype) - if test_val is not None: np.testing.assert_equal(test_val, val) - print("**** test done ****") - - # test that changing the numpy changes the model outputs - if any([x.device == 'NPY' for x in inputs.values()]): - for v in new_inputs_numpy.values(): v *= 2 - out = run(**inputs) - changed_val = out.numpy() - np.testing.assert_raises(AssertionError, np.testing.assert_array_equal, val, changed_val) - return val - -def test_vs_onnx(new_inputs, test_val, onnx_file, ort=False): - new_inputs_numpy = {k:v.numpy() for k,v in new_inputs.items()} - onnx_model = onnx.load(onnx_file) - - timings = [] - if ort: - # test with onnxruntime - import onnxruntime as ort - onnx_session = ort.InferenceSession(onnx_file) - for _ in range(1 if test_val is not None else 5): - st = time.perf_counter() - onnx_output = onnx_session.run([onnx_model.graph.output[0].name], {k:v.astype(np.float16) for k,v in new_inputs_numpy.items()}) - timings.append(time.perf_counter() - st) - new_torch_out = onnx_output[0] - else: - # test with torch - import torch - from onnx2torch import convert - inputs = {k.name:new_inputs_numpy[k.name] for k in onnx_model.graph.input} - torch_model = convert(onnx_model).float() - with torch.no_grad(): - for _ in range(1 if test_val is not None else 5): - st = time.perf_counter() - torch_out = torch_model(*[torch.tensor(x) for x in inputs.values()]) - timings.append(time.perf_counter() - st) - new_torch_out = torch_out.numpy() - - if test_val is not None: - np.testing.assert_allclose(new_torch_out.reshape(test_val.shape), test_val, atol=1e-4, rtol=1e-2) - print("test vs onnx passed") - return timings - -if __name__ == "__main__": - onnx_file = fetch(OPENPILOT_MODEL) - test_val = compile(onnx_file) if not getenv("RUN") else None - - with open(OUTPUT, "rb") as f: pickle_loaded = pickle.load(f) - - # same randomness as compile - Tensor.manual_seed(100) - new_inputs = {nm:Tensor.randn(*st.shape, dtype=dtype).mul(8).realize() for nm, (st, _, dtype, _) in - sorted(zip(pickle_loaded.captured.expected_names, pickle_loaded.captured.expected_st_vars_dtype_device))} - - test_val = test_vs_compile(pickle_loaded, new_inputs, test_val) - if getenv("BENCHMARK"): - for be in ["torch", "ort"]: - try: - timings = test_vs_onnx(new_inputs, None, onnx_file, be=="ort") - print(f"timing {be}: {min(timings)*1000:.2f} ms") - except Exception as e: - print(f"{be} fail with {e}") - if not getenv("FLOAT16"): test_vs_onnx(new_inputs, test_val, onnx_file, getenv("ORT")) - diff --git a/tinygrad/examples/openpilot/compile4.py b/tinygrad/examples/openpilot/compile4.py deleted file mode 100644 index 4d7e1eab..00000000 --- a/tinygrad/examples/openpilot/compile4.py +++ /dev/null @@ -1,49 +0,0 @@ -import sys, onnx -from tinygrad import Tensor, fetch, GlobalCounters -from tinygrad.uop import UOp -from tinygrad.frontend.onnx import OnnxRunner -from tinygrad.engine.grouper import get_kernelize_map -from tinygrad.engine.schedule import create_schedule_with_vars -from tinygrad.engine.realize import run_schedule - -# NOLOCALS=1 GPU=1 IMAGE=2 FLOAT16=1 VIZ=1 DEBUG=2 python3 examples/openpilot/compile4.py - -OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx" -OUTPUT = sys.argv[2] if len(sys.argv) > 2 else "/tmp/openpilot.pkl" - -if __name__ == "__main__": - fn = fetch(OPENPILOT_MODEL) - onnx_file = fetch(OPENPILOT_MODEL) - onnx_model = onnx.load(onnx_file) - run_onnx = OnnxRunner(onnx_model) - - inputs = run_onnx.get_empty_input_data("npy") - out: Tensor = next(iter(run_onnx({k:v.to(None) for k,v in inputs.items()}).values())).to('cpu') - root = out.uop - targets = [x.uop for x in inputs.values()] - print(targets) - - # TODO: abstract this from gradient? - - # compute the target path (top down) - in_target_path: dict[UOp, bool] = {} - for u in root.toposort(): in_target_path[u] = any(x in targets or in_target_path[x] for x in u.src) - independent_set = {} - for u in root.toposort(): - if in_target_path[u]: - for s in u.src: - if not in_target_path[s]: - independent_set[s] = None - independent = UOp.sink(*independent_set.keys()) - kernelized = get_kernelize_map(independent) - independent = independent.substitute(kernelized) - schedule, var_vals, becomes_map = create_schedule_with_vars(independent) - run_schedule(schedule) - - print("**** real ****") - GlobalCounters.reset() - out.uop = root.substitute(kernelized).substitute(becomes_map) - out.kernelize() - - # realize - out.realize() diff --git a/tinygrad/examples/other_mnist/beautiful_mnist_mlx.py b/tinygrad/examples/other_mnist/beautiful_mnist_mlx.py deleted file mode 100644 index 8261ed44..00000000 --- a/tinygrad/examples/other_mnist/beautiful_mnist_mlx.py +++ /dev/null @@ -1,55 +0,0 @@ -from tinygrad.helpers import trange -from tinygrad.nn.datasets import mnist -import mlx.core as mx -import mlx.nn as nn -import mlx.optimizers as optim -from functools import partial - -class Model(nn.Module): - def __init__(self): - super().__init__() - self.c1 = nn.Conv2d(1, 32, 5) - self.c2 = nn.Conv2d(32, 32, 5) - self.bn1 = nn.BatchNorm(32) - self.m1 = nn.MaxPool2d(2) - self.c3 = nn.Conv2d(32, 64, 3) - self.c4 = nn.Conv2d(64, 64, 3) - self.bn2 = nn.BatchNorm(64) - self.m2 = nn.MaxPool2d(2) - self.lin = nn.Linear(576, 10) - def __call__(self, x): - x = mx.maximum(self.c1(x), 0) - x = mx.maximum(self.c2(x), 0) - x = self.m1(self.bn1(x)) - x = mx.maximum(self.c3(x), 0) - x = mx.maximum(self.c4(x), 0) - x = self.m2(self.bn2(x)) - return self.lin(mx.flatten(x, 1)) - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = mnist() - X_train = mx.array(X_train.float().permute((0,2,3,1)).numpy()) - Y_train = mx.array(Y_train.numpy()) - X_test = mx.array(X_test.float().permute((0,2,3,1)).numpy()) - Y_test = mx.array(Y_test.numpy()) - - model = Model() - optimizer = optim.Adam(1e-3) - def loss_fn(model, x, y): return nn.losses.cross_entropy(model(x), y).mean() - - state = [model.state, optimizer.state] - @partial(mx.compile, inputs=state, outputs=state) - def step(samples): - # Compiled functions will also treat any inputs not in the parameter list as constants. - X,Y = X_train[samples], Y_train[samples] - loss_and_grad_fn = nn.value_and_grad(model, loss_fn) - loss, grads = loss_and_grad_fn(model, X, Y) - optimizer.update(model, grads) - return loss - - test_acc = float('nan') - for i in (t:=trange(70)): - samples = mx.random.randint(0, X_train.shape[0], (512,)) # putting this in JIT didn't work well - loss = step(samples) - if i%10 == 9: test_acc = ((model(X_test).argmax(axis=-1) == Y_test).sum() * 100 / X_test.shape[0]).item() - t.set_description(f"loss: {loss.item():6.2f} test_accuracy: {test_acc:5.2f}%") diff --git a/tinygrad/examples/other_mnist/beautiful_mnist_torch.py b/tinygrad/examples/other_mnist/beautiful_mnist_torch.py deleted file mode 100644 index fb3c547a..00000000 --- a/tinygrad/examples/other_mnist/beautiful_mnist_torch.py +++ /dev/null @@ -1,69 +0,0 @@ -from tinygrad import dtypes, getenv, Device -from tinygrad.helpers import trange, colored, DEBUG, temp -from tinygrad.nn.datasets import mnist -import torch -from torch import nn, optim - -class Model(nn.Module): - def __init__(self): - super().__init__() - self.c1 = nn.Conv2d(1, 32, 5) - self.c2 = nn.Conv2d(32, 32, 5) - self.bn1 = nn.BatchNorm2d(32) - self.m1 = nn.MaxPool2d(2) - self.c3 = nn.Conv2d(32, 64, 3) - self.c4 = nn.Conv2d(64, 64, 3) - self.bn2 = nn.BatchNorm2d(64) - self.m2 = nn.MaxPool2d(2) - self.lin = nn.Linear(576, 10) - def forward(self, x): - x = nn.functional.relu(self.c1(x)) - x = nn.functional.relu(self.c2(x), 0) - x = self.m1(self.bn1(x)) - x = nn.functional.relu(self.c3(x), 0) - x = nn.functional.relu(self.c4(x), 0) - x = self.m2(self.bn2(x)) - return self.lin(torch.flatten(x, 1)) - -if __name__ == "__main__": - if getenv("TINY_BACKEND"): - import tinygrad.frontend.torch - device = torch.device("tiny") - else: - device = torch.device({"METAL":"mps","NV":"cuda"}.get(Device.DEFAULT, "cpu")) - if DEBUG >= 1: print(f"using torch backend {device}") - X_train, Y_train, X_test, Y_test = mnist() - X_train = torch.tensor(X_train.float().numpy(), device=device) - Y_train = torch.tensor(Y_train.cast(dtypes.int64).numpy(), device=device) - X_test = torch.tensor(X_test.float().numpy(), device=device) - Y_test = torch.tensor(Y_test.cast(dtypes.int64).numpy(), device=device) - - if getenv("TORCHVIZ"): torch.cuda.memory._record_memory_history() - model = Model().to(device) - optimizer = optim.Adam(model.parameters(), 1e-3) - - loss_fn = nn.CrossEntropyLoss() - #@torch.compile - def step(samples): - X,Y = X_train[samples], Y_train[samples] - out = model(X) - loss = loss_fn(out, Y) - optimizer.zero_grad() - loss.backward() - optimizer.step() - return loss - - test_acc = float('nan') - for i in (t:=trange(getenv("STEPS", 70))): - samples = torch.randint(0, X_train.shape[0], (512,)) # putting this in JIT didn't work well - loss = step(samples) - if i%10 == 9: test_acc = ((model(X_test).argmax(axis=-1) == Y_test).sum() * 100 / X_test.shape[0]).item() - t.set_description(f"loss: {loss.item():6.2f} test_accuracy: {test_acc:5.2f}%") - - # verify eval acc - if target := getenv("TARGET_EVAL_ACC_PCT", 0.0): - if test_acc >= target and test_acc != 100.0: print(colored(f"{test_acc=} >= {target}", "green")) - else: raise ValueError(colored(f"{test_acc=} < {target}", "red")) - if getenv("TORCHVIZ"): - torch.cuda.memory._dump_snapshot(fp:=temp("torchviz.pkl", append_user=True)) - print(f"saved torch memory snapshot to {fp}, view in https://pytorch.org/memory_viz") diff --git a/tinygrad/examples/qwq.py b/tinygrad/examples/qwq.py deleted file mode 100644 index fad87695..00000000 --- a/tinygrad/examples/qwq.py +++ /dev/null @@ -1,115 +0,0 @@ -import argparse -import os -import sys - -from transformers import AutoTokenizer -from pathlib import Path -from typing import Dict, Union - -from extra.models.llama import Transformer, convert_from_huggingface, fix_bf16 -from examples.llama3 import load -from tinygrad import nn, Tensor -from tinygrad.helpers import fetch, colored, GlobalCounters, Timing, DEBUG -from tinygrad.nn.state import load_state_dict, get_parameters - -MODELS = { - "32B": { - "model_params": {"dim": 5120, "n_heads": 40, "n_kv_heads": 8, "n_layers": 64, "norm_eps": 1e-5, "rope_theta": 1000000, "vocab_size": 152064, "hidden_dim": 27648}, - "total_num_weights": 17, - "tokenizer": "Qwen/QwQ-32B-Preview" - } -} - -def download_weights(total_num_weights:int) -> Path: - model = fetch("https://huggingface.co/Qwen/QwQ-32B-Preview/resolve/main/model.safetensors.index.json?download=true", "model.safetensors.index.json", subdir=(subdir:="qwq_32b_preview")) - - for i in range(1, total_num_weights + 1): - filename = f"model-{i:05d}-of-{total_num_weights:05d}.safetensors" - fetch(f"https://huggingface.co/Qwen/QwQ-32B-Preview/resolve/main/{filename}?download=true", filename, subdir=subdir) - - return Path(os.path.dirname(model)) - -def load_model(model_path:Path, model_params:Dict[str, Union[int, float]]) -> Transformer: - # build model - model = Transformer(**model_params, linear=nn.Linear) - - # update layers to add bias - updated_layers = [] - for layer in model.layers: - head_dim = model_params["dim"] // model_params["n_heads"] - layer.attention.wq = nn.Linear(model_params["dim"], model_params["n_heads"] * head_dim, bias=True) - layer.attention.wk = nn.Linear(model_params["dim"], model_params["n_kv_heads"] * head_dim, bias=True) - layer.attention.wv = nn.Linear(model_params["dim"], model_params["n_kv_heads"] * head_dim, bias=True) - updated_layers.append(layer) - model.layers = updated_layers - - # load weights - weights = fix_bf16(convert_from_huggingface(load(str(model_path / "model.safetensors.index.json")), model_params["n_layers"], model_params["n_heads"], model_params["n_kv_heads"], permute_layers=False)) - - # replace weights in model - load_state_dict(model, weights, strict=False, consume=True) - return model - - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Run QwQ in tinygrad", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--size", choices=["32B"], default="32B", help="Model size") - parser.add_argument("--count", type=int, default=30, help="Max number of tokens to generate") - parser.add_argument("--temperature", type=float, default=0.7, help="Temperature in the softmax") - parser.add_argument("--prompt", type=str, default="Hello.", help="Phrase to start with") - parser.add_argument("--weights", type=str, default=None, help="Path to the downloaded weights") - parser.add_argument("--timing", action="store_true", help="Print timing per token") - args = parser.parse_args() - - model_info = MODELS[args.size] - - model_path = Path(args.weights) if args.weights else download_weights(model_info["total_num_weights"]) - transformer = load_model(model_path, model_info["model_params"]) - tokenizer = AutoTokenizer.from_pretrained(model_info["tokenizer"]) - param_bytes = sum(x.uop.size * x.dtype.itemsize for x in get_parameters(transformer)) - - outputted = args.prompt - start_pos, toks = 0, tokenizer(outputted)["input_ids"] - print(outputted, end="", flush=True) - - tok_tensor = None - for i in range(args.count): - GlobalCounters.reset() - - if args.timing: print("") - st = GlobalCounters.time_sum_s - next_tok = Tensor([toks[start_pos:]]) if tok_tensor is None or (len(toks)-start_pos) > 1 else tok_tensor.reshape(1, 1) - with Timing("total ", enabled=args.timing, on_exit=lambda x: f", {1e9/x:.2f} tok/s, {GlobalCounters.global_mem/x:.2f} GB/s, param {param_bytes/x:.2f} GB/s"): - with Timing("enqueue in ", on_exit=(lambda et: (f", {(GlobalCounters.time_sum_s-st)*1e3:.2f} ms on GPU" if DEBUG>=2 else "") + - f", {GlobalCounters.global_ops*1e-9:.2f} GOPS, {GlobalCounters.global_mem*1e-9:.2f} GB" + - (f", {GlobalCounters.global_mem*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s, param {param_bytes*1e-9/(GlobalCounters.time_sum_s-st):.2f} GB/s" if DEBUG>=2 else "")) if DEBUG else None, enabled=args.timing): - tok_tensor = transformer(next_tok, start_pos, args.temperature) - tok = tok_tensor.item() - - # use the kv cache - start_pos = len(toks) - - # add the new token - toks.append(tok) - - cur = tokenizer.decode(toks, skip_special_tokens=True) - sys.stdout.write(cur[len(outputted):]) - sys.stdout.flush() - outputted = cur - - if args.temperature == 0: - text = tokenizer.decode(toks) - key = (args.size, args.count, args.prompt) - expected = { - ("32B", 10, "Hello."): "Hello. I'm trying to make a program that will read", - ( - "32B", - 50, - "Can you tell me more about machine learning?" - ): "Can you tell me more about machine learning? Sure, I'd be happy to help! Machine learning is a subset of artificial intelligence that focuses on building systems that can learn from data and make predictions or decisions without being explicitly programmed to do so. It's a fascinating field with a lot of real" - } - try: - assert text == expected[key], f"invalid output: `{colored(text, 'red')}` != `{expected[key]}`" - print("\n" + colored("output validated", "green")) - except KeyError: - pass diff --git a/tinygrad/examples/rl/lightupbutton.py b/tinygrad/examples/rl/lightupbutton.py deleted file mode 100644 index 65eeff27..00000000 --- a/tinygrad/examples/rl/lightupbutton.py +++ /dev/null @@ -1,45 +0,0 @@ -import gymnasium as gym -import numpy as np -from gymnasium.envs.registration import register - -# a very simple game -# one of lights will light up -# take the action of the lit up light -# in , you act differently based on the step number and need to track this - -class PressTheLightUpButton(gym.Env): - metadata = {"render_modes": []} - def __init__(self, render_mode=None, size=2, game_length=10, hard_mode=False): - self.size, self.game_length = size, game_length - self.observation_space = gym.spaces.Box(0, 1, shape=(self.size,), dtype=np.float32) - self.action_space = gym.spaces.Discrete(self.size) - self.step_num = 0 - self.done = True - self.hard_mode = hard_mode - - def _get_obs(self): - obs = [0]*self.size - if self.step_num < len(self.state): - obs[self.state[self.step_num]] = 1 - return np.array(obs, dtype=np.float32) - - def reset(self, seed=None, options=None): - super().reset(seed=seed) - self.state = np.random.randint(0, self.size, size=self.game_length) - self.step_num = 0 - self.done = False - return self._get_obs(), {} - - def step(self, action): - target = ((action + self.step_num) % self.size) if self.hard_mode else action - reward = int(target == self.state[self.step_num]) - self.step_num += 1 - if not reward: - self.done = True - return self._get_obs(), reward, self.done, self.step_num >= self.game_length, {} - -register( - id="PressTheLightUpButton-v0", - entry_point="examples.rl.lightupbutton:PressTheLightUpButton", - max_episode_steps=None, -) \ No newline at end of file diff --git a/tinygrad/examples/sdv2.py b/tinygrad/examples/sdv2.py deleted file mode 100644 index 29b1abb8..00000000 --- a/tinygrad/examples/sdv2.py +++ /dev/null @@ -1,149 +0,0 @@ -from tinygrad import Tensor, dtypes, TinyJit -from tinygrad.helpers import fetch -from tinygrad.nn.state import safe_load, load_state_dict, get_state_dict -from examples.stable_diffusion import AutoencoderKL, get_alphas_cumprod -from examples.sdxl import DPMPP2MSampler, append_dims, LegacyDDPMDiscretization -from extra.models.unet import UNetModel -from extra.models.clip import FrozenOpenClipEmbedder -from extra.bench_log import BenchEvent, WallTimeEvent - -from typing import Dict -import argparse, tempfile, os -from pathlib import Path -from PIL import Image - -class DiffusionModel: - def __init__(self, model:UNetModel): - self.diffusion_model = model - -@TinyJit -def run(model, x, tms, ctx, c_out, add): - return (model(x, tms, ctx)*c_out + add).realize() - -# https://github.com/Stability-AI/stablediffusion/blob/cf1d67a6fd5ea1aa600c4df58e5b47da45f6bdbf/ldm/models/diffusion/ddpm.py#L521 -class StableDiffusionV2: - def __init__(self, unet_config:Dict, cond_stage_config:Dict, parameterization:str="v"): - self.model = DiffusionModel(UNetModel(**unet_config)) - self.first_stage_model = AutoencoderKL() - self.cond_stage_model = FrozenOpenClipEmbedder(**cond_stage_config) - self.alphas_cumprod = get_alphas_cumprod() - self.parameterization = parameterization - - self.discretization = LegacyDDPMDiscretization() - self.sigmas = self.discretization(1000, flip=True) - - def denoise(self, x:Tensor, sigma:Tensor, cond:Dict) -> Tensor: - - def sigma_to_idx(s:Tensor) -> Tensor: - dists = s - self.sigmas.unsqueeze(1) - return dists.abs().argmin(axis=0).view(*s.shape) - - sigma = self.sigmas[sigma_to_idx(sigma)] - sigma_shape = sigma.shape - sigma = append_dims(sigma, x) - - c_skip = 1.0 / (sigma**2 + 1.0) - c_out = -sigma / (sigma**2 + 1.0) ** 0.5 - c_in = 1.0 / (sigma**2 + 1.0) ** 0.5 - c_noise = sigma_to_idx(sigma.reshape(sigma_shape)) - - def prep(*tensors:Tensor): - return tuple(t.cast(dtypes.float16).realize() for t in tensors) - - return run(self.model.diffusion_model, *prep(x*c_in, c_noise, cond["crossattn"], c_out, x*c_skip)) - - def decode(self, x:Tensor, height:int, width:int) -> Tensor: - x = self.first_stage_model.post_quant_conv(1/0.18215 * x) - x = self.first_stage_model.decoder(x) - - # make image correct size and scale - x = (x + 1.0) / 2.0 - x = x.reshape(3,height,width).permute(1,2,0).clip(0,1).mul(255).cast(dtypes.uint8) - return x - -params: Dict = { - "unet_config": { - "adm_in_ch": None, - "in_ch": 4, - "out_ch": 4, - "model_ch": 320, - "attention_resolutions": [4, 2, 1], - "num_res_blocks": 2, - "channel_mult": [1, 2, 4, 4], - "d_head": 64, - "transformer_depth": [1, 1, 1, 1], - "ctx_dim": 1024, - "use_linear": True, - }, - "cond_stage_config": { - "dims": 1024, - "n_heads": 16, - "layers": 24, - "return_pooled": False, - "ln_penultimate": True, - } -} - -if __name__ == "__main__": - default_prompt = "a horse sized cat eating a bagel" - parser = argparse.ArgumentParser(description='Run Stable Diffusion v2.X', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--steps', type=int, default=10, help="The number of diffusion steps") - parser.add_argument('--prompt', type=str, default=default_prompt, help="Description of image to generate") - parser.add_argument('--out', type=str, default=Path(tempfile.gettempdir()) / "rendered.png", help="Output filename") - parser.add_argument('--seed', type=int, help="Set the random latent seed") - parser.add_argument('--guidance', type=float, default=7.5, help="Prompt strength") - parser.add_argument('--width', type=int, default=768, help="The output image width") - parser.add_argument('--height', type=int, default=768, help="The output image height") - parser.add_argument('--weights-fn', type=str, help="Filename of weights to use") - parser.add_argument('--weights-url', type=str, help="Custom URL to download weights from") - parser.add_argument('--timing', action='store_true', help="Print timing per step") - parser.add_argument('--noshow', action='store_true', help="Don't show the image") - parser.add_argument('--fp16', action='store_true', help="Cast the weights to float16") - args = parser.parse_args() - - N = 1 - C = 4 - F = 8 - assert args.width % F == 0, f"img_width must be multiple of {F}, got {args.width}" - assert args.height % F == 0, f"img_height must be multiple of {F}, got {args.height}" - - if args.seed is not None: - Tensor.manual_seed(args.seed) - - model = StableDiffusionV2(**params) - - default_weights_url = 'https://huggingface.co/stabilityai/stable-diffusion-2-1/resolve/main/v2-1_768-ema-pruned.safetensors' - weights_fn = args.weights_fn - if not weights_fn: - weights_url = args.weights_url if args.weights_url else default_weights_url - weights_fn = fetch(weights_url, os.path.basename(str(weights_url))) - - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - load_state_dict(model, safe_load(weights_fn), strict=False) - - if args.fp16: - for k,v in get_state_dict(model).items(): - if k.startswith("model"): - v.replace(v.cast(dtypes.float16).realize()) - - c = { "crossattn": model.cond_stage_model(args.prompt) } - uc = { "crossattn": model.cond_stage_model("") } - del model.cond_stage_model - print("created conditioning") - - shape = (N, C, args.height // F, args.width // F) - randn = Tensor.randn(shape) - - sampler = DPMPP2MSampler(args.guidance) - z = sampler(model.denoise, randn, c, uc, args.steps, timing=args.timing) - print("created samples") - x = model.decode(z, args.height, args.width).realize() - print("decoded samples") - print(x.shape) - - im = Image.fromarray(x.numpy()) - print(f"saving {args.out}") - im.save(args.out) - - if not args.noshow: - im.show() diff --git a/tinygrad/examples/sdxl.py b/tinygrad/examples/sdxl.py deleted file mode 100644 index d449eb5e..00000000 --- a/tinygrad/examples/sdxl.py +++ /dev/null @@ -1,438 +0,0 @@ -# This file incorporates code from the following: -# Github Name | License | Link -# Stability-AI/generative-models | MIT | https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/LICENSE-CODE -# mlfoundations/open_clip | MIT | https://github.com/mlfoundations/open_clip/blob/58e4e39aaabc6040839b0d2a7e8bf20979e4558a/LICENSE - -from tinygrad import Tensor, TinyJit, dtypes, GlobalCounters -from tinygrad.nn import Conv2d, GroupNorm -from tinygrad.nn.state import safe_load, load_state_dict, get_state_dict -from tinygrad.helpers import fetch, trange, colored, Timing -from extra.models.clip import Embedder, FrozenClosedClipEmbedder, FrozenOpenClipEmbedder -from extra.models.unet import UNetModel, Upsample, Downsample, timestep_embedding -from extra.bench_log import BenchEvent, WallTimeEvent -from examples.stable_diffusion import ResnetBlock, Mid -import numpy as np - -from typing import Dict, List, Callable, Optional, Any, Set, Tuple, Union, Type -import argparse, tempfile -from abc import ABC, abstractmethod -from pathlib import Path -from PIL import Image - - -# configs: -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/configs/inference/sd_xl_base.yaml -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/configs/inference/sd_xl_refiner.yaml -configs: Dict = { - "SDXL_Base": { - "model": {"adm_in_ch": 2816, "in_ch": 4, "out_ch": 4, "model_ch": 320, "attention_resolutions": [4, 2], "num_res_blocks": 2, "channel_mult": [1, 2, 4], "d_head": 64, "transformer_depth": [1, 2, 10], "ctx_dim": 2048, "use_linear": True}, - "conditioner": {"concat_embedders": ["original_size_as_tuple", "crop_coords_top_left", "target_size_as_tuple"]}, - "first_stage_model": {"ch": 128, "in_ch": 3, "out_ch": 3, "z_ch": 4, "ch_mult": [1, 2, 4, 4], "num_res_blocks": 2, "resolution": 256}, - "denoiser": {"num_idx": 1000}, - }, - "SDXL_Refiner": { - "model": {"adm_in_ch": 2560, "in_ch": 4, "out_ch": 4, "model_ch": 384, "attention_resolutions": [4, 2], "num_res_blocks": 2, "channel_mult": [1, 2, 4, 4], "d_head": 64, "transformer_depth": [4, 4, 4, 4], "ctx_dim": [1280, 1280, 1280, 1280], "use_linear": True}, - "conditioner": {"concat_embedders": ["original_size_as_tuple", "crop_coords_top_left", "aesthetic_score"]}, - "first_stage_model": {"ch": 128, "in_ch": 3, "out_ch": 3, "z_ch": 4, "ch_mult": [1, 2, 4, 4], "num_res_blocks": 2, "resolution": 256}, - "denoiser": {"num_idx": 1000}, - } -} - - -def tensor_identity(x:Tensor) -> Tensor: - return x - - -class DiffusionModel: - def __init__(self, *args, **kwargs): - self.diffusion_model = UNetModel(*args, **kwargs) - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/encoders/modules.py#L913 -class ConcatTimestepEmbedderND(Embedder): - def __init__(self, outdim:int, input_key:str): - self.outdim = outdim - self.input_key = input_key - - def __call__(self, x:Union[str,List[str],Tensor]): - assert isinstance(x, Tensor) and len(x.shape) == 2 - emb = timestep_embedding(x.flatten(), self.outdim) - emb = emb.reshape((x.shape[0],-1)) - return emb - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/encoders/modules.py#L71 -class Conditioner: - OUTPUT_DIM2KEYS = {2: "vector", 3: "crossattn", 4: "concat", 5: "concat"} - KEY2CATDIM = {"vector": 1, "crossattn": 2, "concat": 1} - embedders: List[Embedder] - - def __init__(self, concat_embedders:List[str]): - self.embedders = [ - FrozenClosedClipEmbedder(ret_layer_idx=11), - FrozenOpenClipEmbedder(dims=1280, n_heads=20, layers=32, return_pooled=True), - ] - for input_key in concat_embedders: - self.embedders.append(ConcatTimestepEmbedderND(256, input_key)) - - def get_keys(self) -> Set[str]: - return set(e.input_key for e in self.embedders) - - def __call__(self, batch:Dict, force_zero_embeddings:List=[]) -> Dict[str,Tensor]: - output: Dict[str,Tensor] = {} - - for embedder in self.embedders: - emb_out = embedder(batch[embedder.input_key]) - - if isinstance(emb_out, Tensor): - emb_out = (emb_out,) - assert isinstance(emb_out, (list, tuple)) - - for emb in emb_out: - if embedder.input_key in force_zero_embeddings: - emb = Tensor.zeros_like(emb) - - out_key = self.OUTPUT_DIM2KEYS[len(emb.shape)] - if out_key in output: - output[out_key] = Tensor.cat(output[out_key], emb, dim=self.KEY2CATDIM[out_key]) - else: - output[out_key] = emb - - return output - - -class FirstStage: - """ - Namespace for First Stage Model components - """ - - # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/model.py#L487 - class Encoder: - def __init__(self, ch:int, in_ch:int, out_ch:int, z_ch:int, ch_mult:List[int], num_res_blocks:int, resolution:int): - self.conv_in = Conv2d(in_ch, ch, kernel_size=3, stride=1, padding=1) - in_ch_mult = (1,) + tuple(ch_mult) - - class BlockEntry: - def __init__(self, block:List[ResnetBlock], downsample): - self.block = block - self.downsample = downsample - self.down: List[BlockEntry] = [] - for i_level in range(len(ch_mult)): - block = [] - block_in = ch * in_ch_mult[i_level] - block_out = ch * ch_mult [i_level] - for _ in range(num_res_blocks): - block.append(ResnetBlock(block_in, block_out)) - block_in = block_out - - downsample = tensor_identity if (i_level == len(ch_mult)-1) else Downsample(block_in) - self.down.append(BlockEntry(block, downsample)) - - self.mid = Mid(block_in) - - self.norm_out = GroupNorm(32, block_in) - self.conv_out = Conv2d(block_in, 2*z_ch, kernel_size=3, stride=1, padding=1) - - def __call__(self, x:Tensor) -> Tensor: - h = self.conv_in(x) - for down in self.down: - for block in down.block: - h = block(h) - h = down.downsample(h) - - h = h.sequential([self.mid.block_1, self.mid.attn_1, self.mid.block_2]) - h = h.sequential([self.norm_out, Tensor.swish, self.conv_out ]) - return h - - - # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/model.py#L604 - class Decoder: - def __init__(self, ch:int, in_ch:int, out_ch:int, z_ch:int, ch_mult:List[int], num_res_blocks:int, resolution:int): - block_in = ch * ch_mult[-1] - curr_res = resolution // 2 ** (len(ch_mult) - 1) - self.z_shape = (1, z_ch, curr_res, curr_res) - - self.conv_in = Conv2d(z_ch, block_in, kernel_size=3, stride=1, padding=1) - - self.mid = Mid(block_in) - - class BlockEntry: - def __init__(self, block:List[ResnetBlock], upsample:Callable[[Any],Any]): - self.block = block - self.upsample = upsample - self.up: List[BlockEntry] = [] - for i_level in reversed(range(len(ch_mult))): - block = [] - block_out = ch * ch_mult[i_level] - for _ in range(num_res_blocks + 1): - block.append(ResnetBlock(block_in, block_out)) - block_in = block_out - - upsample = tensor_identity if i_level == 0 else Upsample(block_in) - self.up.insert(0, BlockEntry(block, upsample)) # type: ignore - - self.norm_out = GroupNorm(32, block_in) - self.conv_out = Conv2d(block_in, out_ch, kernel_size=3, stride=1, padding=1) - - def __call__(self, z:Tensor) -> Tensor: - h = z.sequential([self.conv_in, self.mid.block_1, self.mid.attn_1, self.mid.block_2]) - - for up in self.up[::-1]: - for block in up.block: - h = block(h) - h = up.upsample(h) - - h = h.sequential([self.norm_out, Tensor.swish, self.conv_out]) - return h - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/models/autoencoder.py#L102 -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/models/autoencoder.py#L437 -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/models/autoencoder.py#L508 -class FirstStageModel: - def __init__(self, embed_dim:int=4, **kwargs): - self.encoder = FirstStage.Encoder(**kwargs) - self.decoder = FirstStage.Decoder(**kwargs) - self.quant_conv = Conv2d(2*kwargs["z_ch"], 2*embed_dim, 1) - self.post_quant_conv = Conv2d(embed_dim, kwargs["z_ch"], 1) - - def decode(self, z:Tensor) -> Tensor: - return z.sequential([self.post_quant_conv, self.decoder]) - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/discretizer.py#L42 -class LegacyDDPMDiscretization: - def __init__(self, linear_start:float=0.00085, linear_end:float=0.0120, num_timesteps:int=1000): - self.num_timesteps = num_timesteps - betas = np.linspace(linear_start**0.5, linear_end**0.5, num_timesteps, dtype=np.float32) ** 2 - alphas = 1.0 - betas - self.alphas_cumprod = np.cumprod(alphas, axis=0) - - def __call__(self, n:int, flip:bool=False) -> Tensor: - if n < self.num_timesteps: - timesteps = np.linspace(self.num_timesteps - 1, 0, n, endpoint=False).astype(int)[::-1] - alphas_cumprod = self.alphas_cumprod[timesteps] - elif n == self.num_timesteps: - alphas_cumprod = self.alphas_cumprod - sigmas = Tensor((1 - alphas_cumprod) / alphas_cumprod) ** 0.5 - sigmas = Tensor.cat(Tensor.zeros((1,)), sigmas) - return sigmas if flip else sigmas.flip(axis=0) # sigmas is "pre-flipped", need to do oposite of flag - - -def append_dims(x:Tensor, t:Tensor) -> Tensor: - dims_to_append = len(t.shape) - len(x.shape) - assert dims_to_append >= 0 - return x.reshape(x.shape + (1,)*dims_to_append) - - -@TinyJit -def run(model, x, tms, ctx, y, c_out, add): - return (model(x, tms, ctx, y)*c_out + add).realize() - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/models/diffusion.py#L19 -class SDXL: - def __init__(self, config:Dict): - self.conditioner = Conditioner(**config["conditioner"]) - self.first_stage_model = FirstStageModel(**config["first_stage_model"]) - self.model = DiffusionModel(**config["model"]) - - self.discretization = LegacyDDPMDiscretization() - self.sigmas = self.discretization(config["denoiser"]["num_idx"], flip=True) - - # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/inference/helpers.py#L173 - def create_conditioning(self, pos_prompts:List[str], img_width:int, img_height:int, aesthetic_score:float=5.0) -> Tuple[Dict,Dict]: - N = len(pos_prompts) - batch_c : Dict = { - "txt": pos_prompts, - "original_size_as_tuple": Tensor([img_height,img_width]).repeat(N,1), - "crop_coords_top_left": Tensor([0,0]).repeat(N,1), - "target_size_as_tuple": Tensor([img_height,img_width]).repeat(N,1), - "aesthetic_score": Tensor([aesthetic_score]).repeat(N,1), - } - batch_uc: Dict = { - "txt": [""]*N, - "original_size_as_tuple": Tensor([img_height,img_width]).repeat(N,1), - "crop_coords_top_left": Tensor([0,0]).repeat(N,1), - "target_size_as_tuple": Tensor([img_height,img_width]).repeat(N,1), - "aesthetic_score": Tensor([aesthetic_score]).repeat(N,1), - } - return self.conditioner(batch_c), self.conditioner(batch_uc, force_zero_embeddings=["txt"]) - - # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/denoiser.py#L42 - def denoise(self, x:Tensor, sigma:Tensor, cond:Dict) -> Tensor: - - def sigma_to_idx(s:Tensor) -> Tensor: - dists = s - self.sigmas.unsqueeze(1) - return dists.abs().argmin(axis=0).view(*s.shape) - - sigma = self.sigmas[sigma_to_idx(sigma)] - sigma_shape = sigma.shape - sigma = append_dims(sigma, x) - - c_out = -sigma - c_in = 1 / (sigma**2 + 1.0) ** 0.5 - c_noise = sigma_to_idx(sigma.reshape(sigma_shape)) - - def prep(*tensors:Tensor): - return tuple(t.cast(dtypes.float16).realize() for t in tensors) - - return run(self.model.diffusion_model, *prep(x*c_in, c_noise, cond["crossattn"], cond["vector"], c_out, x)) - - def decode(self, x:Tensor) -> Tensor: - return self.first_stage_model.decode(1.0 / 0.13025 * x) - - -class Guider(ABC): - def __init__(self, scale:float): - self.scale = scale - - @abstractmethod - def __call__(self, denoiser, x:Tensor, s:Tensor, c:Dict, uc:Dict) -> Tensor: - pass - -class VanillaCFG(Guider): - def __call__(self, denoiser, x:Tensor, s:Tensor, c:Dict, uc:Dict) -> Tensor: - c_out = {} - for k in c: - assert k in ["vector", "crossattn", "concat"] - c_out[k] = Tensor.cat(uc[k], c[k], dim=0) - - x_u, x_c = denoiser(Tensor.cat(x, x), Tensor.cat(s, s), c_out).chunk(2) - x_pred = x_u + self.scale*(x_c - x_u) - return x_pred - -class SplitVanillaCFG(Guider): - def __call__(self, denoiser, x:Tensor, s:Tensor, c:Dict, uc:Dict) -> Tensor: - x_u = denoiser(x, s, uc).clone().realize() - x_c = denoiser(x, s, c) - x_pred = x_u + self.scale*(x_c - x_u) - return x_pred - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/sampling.py#L21 -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/sampling.py#L287 -class DPMPP2MSampler: - def __init__(self, cfg_scale:float, guider_cls:Type[Guider]=VanillaCFG): - self.discretization = LegacyDDPMDiscretization() - self.guider = guider_cls(cfg_scale) - - def sampler_step(self, old_denoised:Optional[Tensor], prev_sigma:Optional[Tensor], sigma:Tensor, next_sigma:Tensor, denoiser, x:Tensor, c:Dict, uc:Dict) -> Tuple[Tensor,Tensor]: - denoised = self.guider(denoiser, x, sigma, c, uc) - - t, t_next = sigma.log().neg(), next_sigma.log().neg() - h = t_next - t - r = None if prev_sigma is None else (t - prev_sigma.log().neg()) / h - - mults = [t_next.neg().exp()/t.neg().exp(), (-h).exp().sub(1)] - if r is not None: - mults.extend([1 + 1/(2*r), 1/(2*r)]) - mults = [append_dims(m, x) for m in mults] - - x_standard = mults[0]*x - mults[1]*denoised - if (old_denoised is None) or (next_sigma.sum().numpy().item() < 1e-14): - return x_standard, denoised - - denoised_d = mults[2]*denoised - mults[3]*old_denoised - x_advanced = mults[0]*x - mults[1]*denoised_d - x = Tensor.where(append_dims(next_sigma, x) > 0.0, x_advanced, x_standard) - return x, denoised - - def __call__(self, denoiser, x:Tensor, c:Dict, uc:Dict, num_steps:int, timing=False) -> Tensor: - sigmas = self.discretization(num_steps).to(x.device) - x *= Tensor.sqrt(1.0 + sigmas[0] ** 2.0) - num_sigmas = len(sigmas) - - old_denoised = None - for i in trange(num_sigmas - 1): - with Timing("step in ", enabled=timing, on_exit=lambda _: f", using {GlobalCounters.mem_used/1e9:.2f} GB"): - GlobalCounters.reset() - with WallTimeEvent(BenchEvent.STEP): - x, old_denoised = self.sampler_step( - old_denoised=old_denoised, - prev_sigma=(None if i==0 else sigmas[i-1].expand(x.shape[0])), - sigma=sigmas[i].expand(x.shape[0]), - next_sigma=sigmas[i+1].expand(x.shape[0]), - denoiser=denoiser, - x=x, - c=c, - uc=uc, - ) - x.realize(old_denoised) - - return x - - -if __name__ == "__main__": - default_prompt = "a horse sized cat eating a bagel" - parser = argparse.ArgumentParser(description="Run SDXL", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--steps', type=int, default=10, help="The number of diffusion steps") - parser.add_argument('--prompt', type=str, default=default_prompt, help="Description of image to generate") - parser.add_argument('--out', type=str, default=Path(tempfile.gettempdir()) / "rendered.png", help="Output filename") - parser.add_argument('--seed', type=int, help="Set the random latent seed") - parser.add_argument('--guidance', type=float, default=6.0, help="Prompt strength") - parser.add_argument('--width', type=int, default=1024, help="The output image width") - parser.add_argument('--height', type=int, default=1024, help="The output image height") - parser.add_argument('--weights', type=str, help="Custom path to weights") - parser.add_argument('--timing', action='store_true', help="Print timing per step") - parser.add_argument('--noshow', action='store_true', help="Don't show the image") - parser.add_argument('--fakeweights', action='store_true', help="Load fake weights") - args = parser.parse_args() - - if args.seed is not None: - Tensor.manual_seed(args.seed) - - model = SDXL(configs["SDXL_Base"]) - - if not args.fakeweights: - default_weight_url = 'https://huggingface.co/stabilityai/stable-diffusion-xl-base-1.0/resolve/main/sd_xl_base_1.0.safetensors' - weights = args.weights if args.weights else fetch(default_weight_url, 'sd_xl_base_1.0.safetensors') - loaded_weights = load_state_dict(model, safe_load(weights), strict=False, verbose=False, realize=False) - - start_mem_used = GlobalCounters.mem_used - with Timing("loaded weights in ", lambda et_ns: f", {(B:=(GlobalCounters.mem_used-start_mem_used))/1e9:.2f} GB loaded at {B/et_ns:.2f} GB/s"): - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - Tensor.realize(*loaded_weights) - del loaded_weights - - N = 1 - C = 4 - F = 8 - - assert args.width % F == 0, f"img_width must be multiple of {F}, got {args.width}" - assert args.height % F == 0, f"img_height must be multiple of {F}, got {args.height}" - - c, uc = model.create_conditioning([args.prompt], args.width, args.height) - del model.conditioner - Tensor.realize(*c.values(), *uc.values()) - print("created batch") - - # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/inference/helpers.py#L101 - shape = (N, C, args.height // F, args.width // F) - randn = Tensor.randn(shape) - - sampler = DPMPP2MSampler(args.guidance) - z = sampler(model.denoise, randn, c, uc, args.steps, timing=args.timing) - print("created samples") - x = model.decode(z).realize() - print("decoded samples") - - # make image correct size and scale - x = (x + 1.0) / 2.0 - x = x.reshape(3,args.height,args.width).permute(1,2,0).clip(0,1).mul(255).cast(dtypes.uint8) - print(x.shape) - - im = Image.fromarray(x.numpy()) - print(f"saving {args.out}") - im.save(args.out) - - if not args.noshow: - im.show() - - # validation! - if args.prompt == default_prompt and args.steps == 10 and args.seed == 0 and args.guidance == 6.0 and args.width == args.height == 1024 \ - and not args.weights: - ref_image = Tensor(np.array(Image.open(Path(__file__).parent / "sdxl_seed0.png"))) - distance = (((x.cast(dtypes.float) - ref_image.cast(dtypes.float)) / ref_image.max())**2).mean().item() - assert distance < 4e-3, colored(f"validation failed with {distance=}", "red") - print(colored(f"output validated with {distance=}", "green")) diff --git a/tinygrad/examples/sdxl_seed0.png b/tinygrad/examples/sdxl_seed0.png deleted file mode 100644 index 386f8604..00000000 Binary files a/tinygrad/examples/sdxl_seed0.png and /dev/null differ diff --git a/tinygrad/examples/self_tokenize.py b/tinygrad/examples/self_tokenize.py deleted file mode 100644 index b66002b4..00000000 --- a/tinygrad/examples/self_tokenize.py +++ /dev/null @@ -1,48 +0,0 @@ -import os, pathlib, argparse -from examples.llama3 import Tokenizer -from tabulate import tabulate -from tinygrad import fetch -from tinygrad.helpers import flatten - -# llama 3 tokenizer -tokenizer = Tokenizer(fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model").as_posix()) - -def read_code(base_path): - ret = [] - for path, _, files in os.walk(os.path.join(base_path, "tinygrad")): - for name in files: - if not name.endswith(".py"): continue - if 'tinygrad/runtime/autogen' in path.replace('\\', '/'): continue - fullpath = os.path.join(path, name) - code = pathlib.Path(fullpath).read_text() - ret.append(("### " + fullpath.split("tinygrad/", 1)[1], code)) - return ret - -def write_code_to_file(filename, code_list): - """Writes the combined code to a specified file.""" - with open(filename, 'w') as f: - f.write('\n'.join(flatten(code_list))) - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Analyze and optionally save tinygrad code.") - parser.add_argument("--output", help="Output file to write the combined code to.") - args = parser.parse_args() - - ret = read_code(".") - - table = [] - for name,code in ret: - table.append([name, len(tokenizer.encode(name+"\x00"+code))]) - print(tabulate([["name", "llm tokens"]]+sorted(table, key=lambda x: -x[1]), headers="firstrow")) - - code_str = '\x00'.join(flatten(ret)) - print(f"code has {len(code_str)} chars") - newline_count = code_str.count('\n') - print(f"code has {newline_count} newlines") - - encoded = tokenizer.encode(code_str) - print(f"code has {len(encoded)} tokens") - - if args.output: - write_code_to_file(args.output, ret) - print(f"Combined code written to {args.output}") \ No newline at end of file diff --git a/tinygrad/examples/serious_mnist.py b/tinygrad/examples/serious_mnist.py deleted file mode 100644 index 752f5dab..00000000 --- a/tinygrad/examples/serious_mnist.py +++ /dev/null @@ -1,136 +0,0 @@ -#!/usr/bin/env python -#inspired by https://github.com/Matuzas77/MNIST-0.17/blob/master/MNIST_final_solution.ipynb -import sys -import numpy as np -from tinygrad.nn.state import get_parameters -from tinygrad.tensor import Tensor -from tinygrad.nn import BatchNorm2d, optim -from tinygrad.helpers import getenv -from extra.datasets import fetch_mnist -from extra.augment import augment_img -from extra.training import train, evaluate -GPU = getenv("GPU") -QUICK = getenv("QUICK") -DEBUG = getenv("DEBUG") - -class SqueezeExciteBlock2D: - def __init__(self, filters): - self.filters = filters - self.weight1 = Tensor.scaled_uniform(self.filters, self.filters//32) - self.bias1 = Tensor.scaled_uniform(1,self.filters//32) - self.weight2 = Tensor.scaled_uniform(self.filters//32, self.filters) - self.bias2 = Tensor.scaled_uniform(1, self.filters) - - def __call__(self, input): - se = input.avg_pool2d(kernel_size=(input.shape[2], input.shape[3])) #GlobalAveragePool2D - se = se.reshape(shape=(-1, self.filters)) - se = se.dot(self.weight1) + self.bias1 - se = se.relu() - se = se.dot(self.weight2) + self.bias2 - se = se.sigmoid().reshape(shape=(-1,self.filters,1,1)) #for broadcasting - se = input.mul(se) - return se - -class ConvBlock: - def __init__(self, h, w, inp, filters=128, conv=3): - self.h, self.w = h, w - self.inp = inp - #init weights - self.cweights = [Tensor.scaled_uniform(filters, inp if i==0 else filters, conv, conv) for i in range(3)] - self.cbiases = [Tensor.scaled_uniform(1, filters, 1, 1) for i in range(3)] - #init layers - self._bn = BatchNorm2d(128) - self._seb = SqueezeExciteBlock2D(filters) - - def __call__(self, input): - x = input.reshape(shape=(-1, self.inp, self.w, self.h)) - for cweight, cbias in zip(self.cweights, self.cbiases): - x = x.pad(padding=[1,1,1,1]).conv2d(cweight).add(cbias).relu() - x = self._bn(x) - x = self._seb(x) - return x - -class BigConvNet: - def __init__(self): - self.conv = [ConvBlock(28,28,1), ConvBlock(28,28,128), ConvBlock(14,14,128)] - self.weight1 = Tensor.scaled_uniform(128,10) - self.weight2 = Tensor.scaled_uniform(128,10) - - def parameters(self): - if DEBUG: #keeping this for a moment - pars = [par for par in get_parameters(self) if par.requires_grad] - no_pars = 0 - for par in pars: - print(par.shape) - no_pars += np.prod(par.shape) - print('no of parameters', no_pars) - return pars - else: - return get_parameters(self) - - def save(self, filename): - with open(filename+'.npy', 'wb') as f: - for par in get_parameters(self): - #if par.requires_grad: - np.save(f, par.numpy()) - - def load(self, filename): - with open(filename+'.npy', 'rb') as f: - for par in get_parameters(self): - #if par.requires_grad: - try: - par.numpy()[:] = np.load(f) - if GPU: - par.gpu() - except: - print('Could not load parameter') - - def forward(self, x): - x = self.conv[0](x) - x = self.conv[1](x) - x = x.avg_pool2d(kernel_size=(2,2)) - x = self.conv[2](x) - x1 = x.avg_pool2d(kernel_size=(14,14)).reshape(shape=(-1,128)) #global - x2 = x.max_pool2d(kernel_size=(14,14)).reshape(shape=(-1,128)) #global - xo = x1.dot(self.weight1) + x2.dot(self.weight2) - return xo - - -if __name__ == "__main__": - lrs = [1e-4, 1e-5] if QUICK else [1e-3, 1e-4, 1e-5, 1e-5] - epochss = [2, 1] if QUICK else [13, 3, 3, 1] - BS = 32 - - lmbd = 0.00025 - lossfn = lambda out,y: out.sparse_categorical_crossentropy(y) + lmbd*(model.weight1.abs() + model.weight2.abs()).sum() - X_train, Y_train, X_test, Y_test = fetch_mnist() - X_train = X_train.reshape(-1, 28, 28).astype(np.uint8) - X_test = X_test.reshape(-1, 28, 28).astype(np.uint8) - steps = len(X_train)//BS - np.random.seed(1337) - if QUICK: - steps = 1 - X_test, Y_test = X_test[:BS], Y_test[:BS] - - model = BigConvNet() - - if len(sys.argv) > 1: - try: - model.load(sys.argv[1]) - print('Loaded weights "'+sys.argv[1]+'", evaluating...') - evaluate(model, X_test, Y_test, BS=BS) - except: - print('could not load weights "'+sys.argv[1]+'".') - - if GPU: - params = get_parameters(model) - [x.gpu_() for x in params] - - for lr, epochs in zip(lrs, epochss): - optimizer = optim.Adam(model.parameters(), lr=lr) - for epoch in range(1,epochs+1): - #first epoch without augmentation - X_aug = X_train if epoch == 1 else augment_img(X_train) - train(model, X_aug, Y_train, optimizer, steps=steps, lossfn=lossfn, BS=BS) - accuracy = evaluate(model, X_test, Y_test, BS=BS) - model.save(f'examples/checkpoint{accuracy * 1e6:.0f}') diff --git a/tinygrad/examples/simple_conv_bn.py b/tinygrad/examples/simple_conv_bn.py deleted file mode 100644 index 28769101..00000000 --- a/tinygrad/examples/simple_conv_bn.py +++ /dev/null @@ -1,17 +0,0 @@ -from tinygrad.tensor import Tensor -from tinygrad.nn import Conv2d, BatchNorm2d -from tinygrad.nn.state import get_parameters - -if __name__ == "__main__": - with Tensor.train(): - - BS, C1, H, W = 4, 16, 224, 224 - C2, K, S, P = 64, 7, 2, 1 - - x = Tensor.uniform(BS, C1, H, W) - conv = Conv2d(C1, C2, kernel_size=K, stride=S, padding=P) - bn = BatchNorm2d(C2, track_running_stats=False) - for t in get_parameters([x, conv, bn]): t.realize() - - print("running network") - x.sequential([conv, bn]).numpy() diff --git a/tinygrad/examples/so_vits_svc.py b/tinygrad/examples/so_vits_svc.py deleted file mode 100644 index 41b6d39d..00000000 --- a/tinygrad/examples/so_vits_svc.py +++ /dev/null @@ -1,673 +0,0 @@ -# original implementation: https://github.com/svc-develop-team/so-vits-svc -from __future__ import annotations -import sys, logging, time, io, math, argparse, operator, numpy as np -from functools import partial, reduce -from pathlib import Path -from typing import Tuple, Optional, Type -from tinygrad import nn, dtypes, Tensor -from tinygrad.helpers import getenv -from tinygrad.nn.state import torch_load -from examples.vits import ResidualCouplingBlock, PosteriorEncoder, Encoder, ResBlock1, ResBlock2, LRELU_SLOPE, sequence_mask, split, get_hparams_from_file, load_checkpoint, weight_norm, HParams -from examples.sovits_helpers import preprocess -import soundfile - -DEBUG = getenv("DEBUG") - -F0_BIN = 256 -F0_MAX = 1100.0 -F0_MIN = 50.0 -F0_MEL_MIN = 1127 * np.log(1 + F0_MIN / 700) -F0_MEL_MAX = 1127 * np.log(1 + F0_MAX / 700) - -def download_if_not_present(file_path: Path, url: str): - if not os.path.isfile(file_path): download_file(url, file_path) - return file_path - -class SpeechEncoder: - def __init__(self, hidden_dim, model:ContentVec): self.hidden_dim, self.model = hidden_dim, model - def encode(self, ): raise NotImplementedError("implement me") - @classmethod - def load_from_pretrained(cls, checkpoint_path:str, checkpoint_url:str) -> ContentVec: - contentvec = ContentVec.load_from_pretrained(checkpoint_path, checkpoint_url) - return cls(contentvec) - -class ContentVec256L9(SpeechEncoder): - def __init__(self, model:ContentVec): super().__init__(hidden_dim=256, model=model) - def encode(self, wav: Tensor): - feats = wav - if len(feats.shape) == 2: # double channels - feats = feats.mean(-1) - assert len(feats.shape) == 1, feats.dim() - feats = feats.reshape(1, -1) - padding_mask = Tensor.zeros_like(feats).cast(dtypes.bool) - logits = self.model.extract_features(feats.to(wav.device), padding_mask=padding_mask.to(wav.device), output_layer=9) - feats = self.model.final_proj(logits[0]) - return feats.transpose(1,2) - -class ContentVec768L12(SpeechEncoder): - def __init__(self, model:ContentVec): super().__init__(hidden_dim=768, model=model) - def encode(self, wav: Tensor): - feats = wav - if len(feats.shape) == 2: # double channels - feats = feats.mean(-1) - assert len(feats.shape) == 1, feats.dim() - feats = feats.reshape(1, -1) - padding_mask = Tensor.zeros_like(feats).cast(dtypes.bool) - logits = self.model.extract_features(feats.to(wav.device), padding_mask=padding_mask.to(wav.device), output_layer=12) - return logits[0].transpose(1,2) - -# original code for contentvec: https://github.com/auspicious3000/contentvec/ -class ContentVec: - # self.final_proj dims are hardcoded and depend on fairseq.data.dictionary Dictionary in the checkpoint. This param can't yet be loaded since there is no pickle for it. See with DEBUG=2. - # This means that the ContentVec only works with the hubert weights used in all SVC models - def __init__(self, cfg: HParams): - self.feature_grad_mult, self.untie_final_proj = cfg.feature_grad_mult, cfg.untie_final_proj - feature_enc_layers = eval(cfg.conv_feature_layers) - self.embed = feature_enc_layers[-1][0] - final_dim = cfg.final_dim if cfg.final_dim > 0 else cfg.encoder_embed_dim - self.feature_extractor = ConvFeatureExtractionModel(conv_layers=feature_enc_layers, dropout=0.0, mode=cfg.extractor_mode, conv_bias=cfg.conv_bias) - self.post_extract_proj = nn.Linear(self.embed, cfg.encoder_embed_dim) if self.embed != cfg.encoder_embed_dim else None - self.encoder = TransformerEncoder(cfg) - self.layer_norm = nn.LayerNorm(self.embed) - self.final_proj = nn.Linear(cfg.encoder_embed_dim, final_dim * 1) if self.untie_final_proj else nn.Linear(cfg.encoder_embed_dim, final_dim) - self.mask_emb = Tensor.uniform(cfg.encoder_embed_dim, dtype=dtypes.float32) - self.label_embs_concat = Tensor.uniform(504, final_dim, dtype=dtypes.float32) - def forward_features(self, source, padding_mask): - if self.feature_grad_mult > 0: - features = self.feature_extractor(source, padding_mask) - if self.feature_grad_mult != 1.0: pass # training: GradMultiply.forward(features, self.feature_grad_mult) - else: - features = self.feature_extractor(source, padding_mask) - return features - def forward_padding_mask(self, features, padding_mask): # replaces original forward_padding_mask for batch inference - lengths_org = tilde(padding_mask.cast(dtypes.bool)).cast(dtypes.int64).sum(1) # ensure its bool for tilde - lengths = (lengths_org - 400).float().div(320).floor().cast(dtypes.int64) + 1 # intermediate float to divide - padding_mask = lengths_to_padding_mask(lengths) - return padding_mask - def extract_features(self, source: Tensor, spk_emb:Tensor=None, padding_mask=None, ret_conv=False, output_layer=None, tap=False): - features = self.forward_features(source, padding_mask) - if padding_mask is not None: - padding_mask = self.forward_padding_mask(features, padding_mask) - features = features.transpose(1, 2) - features = self.layer_norm(features) - if self.post_extract_proj is not None: - features = self.post_extract_proj(features) - x, _ = self.encoder(features, spk_emb, padding_mask=padding_mask, layer=(None if output_layer is None else output_layer - 1), tap=tap) - res = features if ret_conv else x - return res, padding_mask - @classmethod - def load_from_pretrained(cls, checkpoint_path:str, checkpoint_url:str) -> ContentVec: - download_if_not_present(checkpoint_path, checkpoint_url) - cfg = load_fairseq_cfg(checkpoint_path) - enc = cls(cfg.model) - _ = load_checkpoint_enc(checkpoint_path, enc, None) - logging.debug(f"{cls.__name__}: Loaded model with cfg={cfg}") - return enc - -class TransformerEncoder: - def __init__(self, cfg: HParams): - def make_conv() -> nn.Conv1d: - layer = nn.Conv1d(self.embedding_dim, self.embedding_dim, kernel_size=cfg.conv_pos, padding=cfg.conv_pos // 2, groups=cfg.conv_pos_groups) - std = std = math.sqrt(4 / (cfg.conv_pos * self.embedding_dim)) - layer.weight, layer.bias = (Tensor.normal(*layer.weight.shape, std=std)), (Tensor.zeros(*layer.bias.shape)) - # for training: layer.weights need to be weight_normed - return layer - self.dropout, self.embedding_dim, self.layer_norm_first, self.layerdrop, self.num_layers, self.num_layers_1 = cfg.dropout, cfg.encoder_embed_dim, cfg.layer_norm_first, cfg.encoder_layerdrop, cfg.encoder_layers, cfg.encoder_layers_1 - self.pos_conv, self.pos_conv_remove = [make_conv()], (1 if cfg.conv_pos % 2 == 0 else 0) - self.layers = [ - TransformerEncoderLayer(self.embedding_dim, cfg.encoder_ffn_embed_dim, cfg.encoder_attention_heads, self.dropout, cfg.attention_dropout, cfg.activation_dropout, cfg.activation_fn, self.layer_norm_first, cond_layer_norm=(i >= cfg.encoder_layers)) - for i in range(cfg.encoder_layers + cfg.encoder_layers_1) - ] - self.layer_norm = nn.LayerNorm(self.embedding_dim) - self.cond_layer_norm = CondLayerNorm(self.embedding_dim) if cfg.encoder_layers_1 > 0 else None - # training: apply init_bert_params - def __call__(self, x, spk_emb, padding_mask=None, layer=None, tap=False): - x, layer_results = self.extract_features(x, spk_emb, padding_mask, layer, tap) - if self.layer_norm_first and layer is None: - x = self.cond_layer_norm(x, spk_emb) if (self.num_layers_1 > 0) else self.layer_norm(x) - return x, layer_results - def extract_features(self, x: Tensor, spk_emb: Tensor, padding_mask=None, tgt_layer=None, tap=False): - if tgt_layer is not None: # and not self.training - assert tgt_layer >= 0 and tgt_layer < len(self.layers) - if padding_mask is not None: - # x[padding_mask] = 0 - assert padding_mask.shape == x.shape[:len(padding_mask.shape)] # first few dims of x must match padding_mask - tmp_mask = padding_mask.unsqueeze(-1).repeat((1, 1, x.shape[-1])) - tmp_mask = tilde(tmp_mask.cast(dtypes.bool)) - x = tmp_mask.where(x, 0) - x_conv = self.pos_conv[0](x.transpose(1,2)) - if self.pos_conv_remove > 0: x_conv = x_conv[:, :, : -self.pos_conv_remove] - x_conv = x_conv.gelu().transpose(1, 2) - x = (x + x_conv).transpose(0, 1) # B x T x C -> T x B x C - if not self.layer_norm_first: x = self.layer_norm(x) - x = x.dropout(p=self.dropout) - layer_results = [] - r = None - for i, layer in enumerate(self.layers): - if i < self.num_layers: # if (not self.training or (dropout_probability > self.layerdrop)) and (i < self.num_layers): - assert layer.cond_layer_norm == False - x = layer(x, self_attn_padding_mask=padding_mask, need_weights=False) - if tgt_layer is not None or tap: - layer_results.append(x.transpose(0, 1)) - if i>= self.num_layers: - assert layer.cond_layer_norm == True - x = layer(x, emb=spk_emb, self_attn_padding_mask=padding_mask, need_weights=False) - if i == tgt_layer: - r = x - break - if r is not None: - x = r - x = x.transpose(0, 1) # T x B x C -> B x T x C - return x, layer_results - -class TransformerEncoderLayer: - def __init__(self, embedding_dim=768.0, ffn_embedding_dim=3072.0, num_attention_heads=8.0, dropout=0.1, attention_dropout=0.1, activation_dropout=0.1, activation_fn="relu", layer_norm_first=False, cond_layer_norm=False): - def get_activation_fn(activation): - if activation == "relu": return Tensor.relu - if activation == "gelu": return Tensor.gelu - else: raise RuntimeError(f"activation function={activation} is not forseen") - self.embedding_dim, self.dropout, self.activation_dropout, self.layer_norm_first, self.num_attention_heads, self.cond_layer_norm, self.activation_fn = embedding_dim, dropout, activation_dropout, layer_norm_first, num_attention_heads, cond_layer_norm, get_activation_fn(activation_fn) - self.self_attn = MultiHeadAttention(self.embedding_dim, self.num_attention_heads) - self.self_attn_layer_norm = nn.LayerNorm(self.embedding_dim) if not cond_layer_norm else CondLayerNorm(self.embedding_dim) - self.fc1 = nn.Linear(self.embedding_dim, ffn_embedding_dim) - self.fc2 = nn.Linear(ffn_embedding_dim, self.embedding_dim) - self.final_layer_norm = nn.LayerNorm(self.embedding_dim) if not cond_layer_norm else CondLayerNorm(self.embedding_dim) - def __call__(self, x:Tensor, self_attn_mask:Tensor=None, self_attn_padding_mask:Tensor=None, emb:Tensor=None, need_weights=False): - #self_attn_padding_mask = self_attn_padding_mask.reshape(x.shape[0], 1, 1, self_attn_padding_mask.shape[1]).expand(-1, self.num_attention_heads, -1, -1).reshape(x.shape[0] * self.num_attention_heads, 1, self_attn_padding_mask.shape[1]) if self_attn_padding_mask is not None else None - assert self_attn_mask is None and self_attn_padding_mask is not None - residual = x - if self.layer_norm_first: - x = self.self_attn_layer_norm(x) if not self.cond_layer_norm else self.self_attn_layer_norm(x, emb) - x = self.self_attn(x=x, mask=self_attn_padding_mask) - x = x.dropout(self.dropout) - x = residual + x - x = self.final_layer_norm(x) if not self.cond_layer_norm else self.final_layer_norm(x, emb) - x = self.activation_fn(self.fc1(x)) - x = x.dropout(self.activation_dropout) - x = self.fc2(x) - x = x.dropout(self.dropout) - x = residual + x - else: - x = self.self_attn(x=x, mask=self_attn_padding_mask) - x = x.dropout(self.dropout) - x = residual + x - x = self.self_attn_layer_norm(x) if not self.cond_layer_norm else self.self_attn_layer_norm(x, emb) - residual = x - x = self.activation_fn(self.fc1(x)) - x = x.dropout(self.activation_dropout) - x = self.fc2(x) - x = x.dropout(self.dropout) - x = residual + x - x = self.final_layer_norm(x) if not self.cond_layer_norm else self.final_layer_norm(x, emb) - return x - -class MultiHeadAttention: - def __init__(self, n_state, n_head): - self.n_state, self.n_head = n_state, n_head - self.q_proj, self.k_proj, self.v_proj, self.out_proj = [nn.Linear(n_state, n_state) for _ in range(4)] - def __call__(self, x:Tensor, xa:Optional[Tensor]=None, mask:Optional[Tensor]=None): - x = x.transpose(0,1) # TxBxC -> BxTxC - q, k, v = self.q_proj(x), self.k_proj(xa or x), self.v_proj(xa or x) - q, k, v = [x.reshape(*q.shape[:2], self.n_head, -1) for x in (q, k, v)] - wv = Tensor.scaled_dot_product_attention(q.transpose(1, 2), k.transpose(1, 2), v.transpose(1, 2), None).transpose(1, 2).reshape(*x.shape[:2], -1) - ret = self.out_proj(wv).transpose(0,1) # BxTxC -> TxBxC - return ret - -class ConvFeatureExtractionModel: - def __init__(self, conv_layers, dropout=.0, mode="default", conv_bias=False): - assert mode in {"default", "group_norm_masked", "layer_norm"} - def block(n_in, n_out, k, stride, is_layer_norm=False, is_group_norm=False, conv_bias=False): - def make_conv(): - conv = nn.Conv1d(n_in, n_out, k, stride=stride, bias=conv_bias) - conv.weight = Tensor.kaiming_normal(*conv.weight.shape) - return conv - assert (is_layer_norm and is_group_norm) == False, "layer norm and group norm are exclusive" - if is_layer_norm: - return [make_conv(), partial(Tensor.dropout, p=dropout),[partial(Tensor.transpose, dim0=-2, dim1=-1), nn.LayerNorm(dim, elementwise_affine=True), partial(Tensor.transpose, dim0=-2, dim1=-1)], Tensor.gelu] - elif is_group_norm and mode == "default": - return [make_conv(), partial(Tensor.dropout, p=dropout), nn.GroupNorm(dim, dim, affine=True), Tensor.gelu] - elif is_group_norm and mode == "group_norm_masked": - return [make_conv(), partial(Tensor.dropout, p=dropout), GroupNormMasked(dim, dim, affine=True), Tensor.gelu] - else: - return [make_conv(), partial(Tensor.dropout, p=dropout), Tensor.gelu] - in_d, self.conv_layers, self.mode = 1, [], mode - for i, cl in enumerate(conv_layers): - assert len(cl) == 3, "invalid conv definition: " + str(cl) - (dim, k, stride) = cl - if i == 0: self.cl = cl - self.conv_layers.append(block(in_d, dim, k, stride, is_layer_norm=(mode == "layer_norm"), is_group_norm=((mode == "default" or mode == "group_norm_masked") and i == 0), conv_bias=conv_bias)) - in_d = dim - def __call__(self, x:Tensor, padding_mask:Tensor): - x = x.unsqueeze(1) # BxT -> BxCxT - if self.mode == "group_norm_masked": - if padding_mask is not None: - _, k, stride = self.cl - lengths_org = tilde(padding_mask.cast(dtypes.bool)).cast(dtypes.int64).sum(1) # ensure padding_mask is bool for tilde - lengths = (((lengths_org - k) / stride) + 1).floor().cast(dtypes.int64) - padding_mask = tilde(lengths_to_padding_mask(lengths)).cast(dtypes.int64) # lengths_to_padding_mask returns bool tensor - x = self.conv_layers[0][0](x) # padding_mask is numeric - x = self.conv_layers[0][1](x) - x = self.conv_layers[0][2](x, padding_mask) - x = self.conv_layers[0][3](x) - else: - x = x.sequential(self.conv_layers[0]) # default - for _, conv in enumerate(self.conv_layers[1:], start=1): - conv = reduce(lambda a,b: operator.iconcat(a,b if isinstance(b, list) else [b]), conv, []) # flatten - x = x.sequential(conv) - return x - -class CondLayerNorm: # https://github.com/auspicious3000/contentvec/blob/main/contentvec/modules/cond_layer_norm.py#L10 - def __init__(self, dim_last, eps=1e-5, dim_spk=256, elementwise_affine=True): - self.dim_last, self.eps, self.dim_spk, self.elementwise_affine = dim_last, eps, dim_spk, elementwise_affine - if self.elementwise_affine: - self.weight_ln = nn.Linear(self.dim_spk, self.dim_last, bias=False) - self.bias_ln = nn.Linear(self.dim_spk, self.dim_last, bias=False) - self.weight_ln.weight, self.bias_ln.weight = (Tensor.ones(*self.weight_ln.weight.shape)), (Tensor.zeros(*self.bias_ln.weight.shape)) - def __call__(self, x: Tensor, spk_emb: Tensor): - axis = tuple(-1-i for i in range(len(x.shape[1:]))) - x = x.layernorm(axis=axis, eps=self.eps) - if not self.elementwise_affine: return x - weights, bias = self.weight_ln(spk_emb), self.bias_ln(spk_emb) - return weights * x + bias - -class GroupNormMasked: # https://github.com/auspicious3000/contentvec/blob/d746688a32940f4bee410ed7c87ec9cf8ff04f74/contentvec/modules/fp32_group_norm.py#L16 - def __init__(self, num_groups, num_channels, eps=1e-5, affine=True): - self.num_groups, self.num_channels, self.eps, self.affine = num_groups, num_channels, eps, affine - self.weight, self.bias = (Tensor.ones(num_channels)), (Tensor.zeros(num_channels)) if self.affine else (None, None) - def __call__(self, x:Tensor, mask:Tensor): - bsz, n_c, length = x.shape - assert n_c % self.num_groups == 0 - x = x.reshape(bsz, self.num_groups, n_c // self.num_groups, length) - if mask is None: mask = Tensor.ones_like(x) - else: mask = mask.reshape(bsz, 1, 1, length) - x = x * mask - lengths = mask.sum(axis=3, keepdim=True) - assert x.shape[2] == 1 - mean_ = x.mean(dim=3, keepdim=True) - mean = mean_ * length / lengths - var = (((x.std(axis=3, keepdim=True) ** 2) + mean_**2) * length / lengths - mean**2) + self.eps - return x.add(-mean).div(var.sqrt()).reshape(bsz, n_c, length).mul(self.weight.reshape(1,-1,1)).add(self.bias.reshape(1,-1,1)) - -class Synthesizer: - def __init__(self, spec_channels, segment_size, inter_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels, ssl_dim, n_speakers, sampling_rate=44100, vol_embedding=False, n_flow_layer=4, **kwargs): - self.spec_channels, self.inter_channels, self.hidden_channels, self.filter_channels, self.n_heads, self.n_layers, self.kernel_size, self.p_dropout, self.resblock, self.resblock_kernel_sizes, self.resblock_dilation_sizes, self.upsample_rates, self.upsample_initial_channel, self.upsample_kernel_sizes, self.segment_size, self.n_speakers, self.gin_channels, self.vol_embedding = spec_channels, inter_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, segment_size, n_speakers, gin_channels, vol_embedding - self.emb_g = nn.Embedding(n_speakers, gin_channels) - if vol_embedding: self.emb_vol = nn.Linear(1, hidden_channels) - self.pre = nn.Conv1d(ssl_dim, hidden_channels, kernel_size=5, padding=2) - self.enc_p = TextEncoder(inter_channels, hidden_channels, kernel_size, n_layers, filter_channels=filter_channels, n_heads=n_heads, p_dropout=p_dropout) - self.dec = Generator(sampling_rate, inter_channels, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels) - self.enc_q = PosteriorEncoder(spec_channels, inter_channels, hidden_channels, 5, 1, 16, gin_channels=gin_channels) - self.flow = ResidualCouplingBlock(inter_channels, hidden_channels, 5, 1, n_flow_layer, gin_channels=gin_channels) - self.emb_uv = nn.Embedding(vocab_size=2, embed_size=hidden_channels) - def infer(self, c:Tensor, f0:Tensor, uv:Tensor, g:Tensor=None, noise_scale=0.35, seed=52468, vol=None) -> Tuple[Tensor, Tensor]: - Tensor.manual_seed(getenv('SEED', seed)) - c_lengths = (Tensor.ones([c.shape[0]]) * c.shape[-1]).to(c.device) - if len(g.shape) == 1: g = g.unsqueeze(0) - g = self.emb_g(g).transpose(1, 2) - x_mask = sequence_mask(c_lengths, c.shape[2]).unsqueeze(1).cast(c.dtype) - vol = self.emb_vol(vol[:,:,None]).transpose(1,2) if vol is not None and self.vol_embedding else 0 - x = self.pre(c) * x_mask + self.emb_uv(uv.cast(dtypes.int64)).transpose(1, 2) + vol - z_p, _, _, c_mask = self.enc_p.forward(x, x_mask, f0=self._f0_to_coarse(f0), noise_scale=noise_scale) - z = self.flow.forward(z_p, c_mask, g=g, reverse=True) - o = self.dec.forward(z * c_mask, g=g, f0=f0) - return o,f0 - def _f0_to_coarse(self, f0 : Tensor): - f0_mel = 1127 * (1 + f0 / 700).log() - a = (F0_BIN - 2) / (F0_MEL_MAX - F0_MEL_MIN) - b = F0_MEL_MIN * a - 1. - f0_mel = (f0_mel > 0).where(f0_mel * a - b, f0_mel) - f0_coarse = f0_mel.ceil().cast(dtype=dtypes.int64) - f0_coarse = f0_coarse * (f0_coarse > 0) - f0_coarse = f0_coarse + ((f0_coarse < 1) * 1) - f0_coarse = f0_coarse * (f0_coarse < F0_BIN) - f0_coarse = f0_coarse + ((f0_coarse >= F0_BIN) * (F0_BIN - 1)) - return f0_coarse - @classmethod - def load_from_pretrained(cls, config_path:str, config_url:str, weights_path:str, weights_url:str) -> Synthesizer: - download_if_not_present(config_path, config_url) - hps = get_hparams_from_file(config_path) - download_if_not_present(weights_path, weights_url) - net_g = cls(hps.data.filter_length // 2 + 1, hps.train.segment_size // hps.data.hop_length, **hps.model) - _ = load_checkpoint(weights_path, net_g, None, skip_list=["f0_decoder"]) - logging.debug(f"{cls.__name__}:Loaded model with hps: {hps}") - return net_g, hps - -class TextEncoder: - def __init__(self, out_channels, hidden_channels, kernel_size, n_layers, gin_channels=0, filter_channels=None, n_heads=None, p_dropout=None): - self.out_channels, self.hidden_channels, self.kernel_size, self.n_layers, self.gin_channels = out_channels, hidden_channels, kernel_size, n_layers, gin_channels - self.proj = nn.Conv1d(hidden_channels, out_channels * 2, 1) - self.f0_emb = nn.Embedding(256, hidden_channels) # n_vocab = 256 - self.enc_ = Encoder(hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout) - def forward(self, x, x_mask, f0=None, noise_scale=1): - x = x + self.f0_emb(f0).transpose(1, 2) - x = self.enc_.forward(x * x_mask, x_mask) - stats = self.proj(x) * x_mask - m, logs = split(stats, self.out_channels, dim=1) - z = (m + randn_like(m) * logs.exp() * noise_scale) * x_mask - return z, m, logs, x_mask - -class Upsample: - def __init__(self, scale_factor): - assert scale_factor % 1 == 0, "Only integer scale factor allowed." - self.scale = int(scale_factor) - def forward(self, x:Tensor): - repeats = tuple([1] * len(x.shape) + [self.scale]) - new_shape = (*x.shape[:-1], x.shape[-1] * self.scale) - return x.unsqueeze(-1).repeat(repeats).reshape(new_shape) - -class SineGen: - def __init__(self, samp_rate, harmonic_num=0, sine_amp=0.1, noise_std=0.003, voice_threshold=0, flag_for_pulse=False): - self.sine_amp, self.noise_std, self.harmonic_num, self.sampling_rate, self.voiced_threshold, self.flag_for_pulse = sine_amp, noise_std, harmonic_num, samp_rate, voice_threshold, flag_for_pulse - self.dim = self.harmonic_num + 1 - def _f02uv(self, f0): return (f0 > self.voiced_threshold).float() #generate uv signal - def _f02sine(self, f0_values): - def padDiff(x : Tensor): return (x.pad((0,0,-1,1)) - x).pad((0,0,0,-1)) - def mod(x: Tensor, n: int) -> Tensor: return x - n * x.div(n).floor() # this is what the % operator does in pytorch. - rad_values = mod((f0_values / self.sampling_rate) , 1) # convert to F0 in rad - rand_ini = Tensor.rand(f0_values.shape[0], f0_values.shape[2], device=f0_values.device) # initial phase noise - - #rand_ini[:, 0] = 0 - m = Tensor.ones(f0_values.shape[0]).unsqueeze(1).pad((0,f0_values.shape[2]-1,0,0)).cast(dtypes.bool) - m = tilde(m) - rand_ini = m.where(rand_ini, 0) - - #rad_values[:, 0, :] = rad_values[:, 0, :] + rand_ini - tmp = rad_values[:, 0, :] + rand_ini - m = Tensor.ones(tmp.shape).pad((0,0,0,rad_values.shape[1]-1,0)).cast(dtypes.bool) - m = tilde(m) - tmp = tmp.unsqueeze(1).pad((0,0,0,rad_values.shape[1]-1,0)) - rad_values = m.where(rad_values, tmp) - - tmp_over_one = mod(rad_values.cumsum(1), 1) - tmp_over_one_idx = padDiff(tmp_over_one) < 0 - cumsum_shift = Tensor.zeros_like(rad_values) - - #cumsum_shift[:, 1:, :] = tmp_over_one_idx * -1.0 - tmp_over_one_idx = (tmp_over_one_idx * -1.0).pad((0,0,1,0)) - cumsum_shift = tmp_over_one_idx - - sines = ((rad_values + cumsum_shift).cumsum(1) * 2 * np.pi).sin() - return sines - def forward(self, f0, upp=None): - fn = f0.mul(Tensor([[range(1, self.harmonic_num + 2)]], dtype=dtypes.float32).to(f0.device)) - sine_waves = self._f02sine(fn) * self.sine_amp #generate sine waveforms - uv = self._f02uv(f0) # generate uv signal - noise_amp = uv * self.noise_std + (1 - uv) * self.sine_amp / 3 - noise = noise_amp * randn_like(sine_waves) - sine_waves = sine_waves * uv + noise - return sine_waves, uv, noise - -class SourceHnNSF: - def __init__(self, sampling_rate, harmonic_num=0, sine_amp=0.1, add_noise_std=0.003, voiced_threshold=0): - self.sine_amp, self.noise_std = sine_amp, add_noise_std - self.l_sin_gen = SineGen(sampling_rate, harmonic_num, sine_amp, add_noise_std, voiced_threshold) - self.l_linear = nn.Linear(harmonic_num + 1, 1) - def forward(self, x, upp=None): - sine_waves, uv, _ = self.l_sin_gen.forward(x, upp) - sine_merge = self.l_linear(sine_waves.cast(self.l_linear.weight.dtype)).tanh() - noise = randn_like(uv) * self.sine_amp / 3 - return sine_merge, noise, uv - -# most of the hifigan in standard vits is reused here, but need to upsample and construct harmonic source from f0 -class Generator: - def __init__(self, sampling_rate, inter_channels, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels): - self.sampling_rate, self.inter_channels, self.resblock, self.resblock_kernel_sizes, self.resblock_dilation_sizes, self.upsample_rates, self.upsample_initial_channel, self.upsample_kernel_sizes, self.gin_channels = sampling_rate, inter_channels, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels - self.num_kernels, self.num_upsamples = len(resblock_kernel_sizes), len(upsample_rates) - self.conv_pre = nn.Conv1d(inter_channels, upsample_initial_channel, 7, 1, padding=3) - self.f0_upsamp = Upsample(scale_factor=np.prod(upsample_rates)) - self.m_source = SourceHnNSF(sampling_rate, harmonic_num=8) - resblock = ResBlock1 if resblock == '1' else ResBlock2 - self.ups, self.noise_convs, self.resblocks = [], [], [] - for i, (u, k) in enumerate(zip(upsample_rates, upsample_kernel_sizes)): - c_cur = upsample_initial_channel//(2**(i+1)) - self.ups.append(nn.ConvTranspose1d(upsample_initial_channel//(2**i), c_cur, k, u, padding=(k-u)//2)) - stride_f0 = int(np.prod(upsample_rates[i + 1:])) - self.noise_convs.append(nn.Conv1d(1, c_cur, kernel_size=stride_f0 * 2, stride=stride_f0, padding=(stride_f0+1) // 2) if (i + 1 < len(upsample_rates)) else nn.Conv1d(1, c_cur, kernel_size=1)) - for i in range(len(self.ups)): - ch = upsample_initial_channel // (2 ** (i + 1)) - for _, (k, d) in enumerate(zip(resblock_kernel_sizes, resblock_dilation_sizes)): - self.resblocks.append(resblock(ch, k, d)) - self.conv_post = nn.Conv1d(ch, 1, 7, 1, padding=3) - if gin_channels != 0: self.cond = nn.Conv1d(gin_channels, upsample_initial_channel, 1) - self.upp = np.prod(upsample_rates) - def forward(self, x, f0, g=None): - f0 = self.f0_upsamp.forward(f0[:, None]).transpose(1, 2) # bs,n,t - har_source, _, _ = self.m_source.forward(f0, self.upp) - har_source = har_source.transpose(1, 2) - x = self.conv_pre(x) - if g is not None: x = x + self.cond(g) - for i in range(self.num_upsamples): - x, xs = self.ups[i](x.leaky_relu(LRELU_SLOPE)), None - x_source = self.noise_convs[i](har_source) - x = x + x_source - for j in range(self.num_kernels): - if xs is None: xs = self.resblocks[i * self.num_kernels + j].forward(x) - else: xs += self.resblocks[i * self.num_kernels + j].forward(x) - x = xs / self.num_kernels - return self.conv_post(x.leaky_relu()).tanh() - -# **** helpers **** - -def randn_like(x:Tensor) -> Tensor: return Tensor.randn(*x.shape, dtype=x.dtype).to(device=x.device) - -def tilde(x: Tensor) -> Tensor: - if x.dtype == dtypes.bool: return (1 - x).cast(dtypes.bool) - return (x + 1) * -1 # this seems to be what the ~ operator does in pytorch for non bool - -def lengths_to_padding_mask(lens:Tensor) -> Tensor: - bsz, max_lens = lens.shape[0], lens.max().numpy().item() - mask = Tensor.arange(max_lens).to(lens.device).reshape(1, max_lens) - mask = mask.expand(bsz, -1) >= lens.reshape(bsz, 1).expand(-1, max_lens) - return mask.cast(dtypes.bool) - -def repeat_expand_2d_left(content, target_len): # content : [h, t] - src_len = content.shape[-1] - temp = np.arange(src_len+1) * target_len / src_len - current_pos, cols = 0, [] - for i in range(target_len): - if i >= temp[current_pos+1]: - current_pos += 1 - cols.append(content[:, current_pos]) - return Tensor.stack(*cols).transpose(0, 1) - -def load_fairseq_cfg(checkpoint_path): - assert Path(checkpoint_path).is_file() - state = torch_load(checkpoint_path) - cfg = state["cfg"] if ("cfg" in state and state["cfg"] is not None) else None - if cfg is None: raise RuntimeError(f"No cfg exist in state keys = {state.keys()}") - return HParams(**cfg) - -def load_checkpoint_enc(checkpoint_path, model: ContentVec, optimizer=None, skip_list=[]): - assert Path(checkpoint_path).is_file() - start_time = time.time() - checkpoint_dict = torch_load(checkpoint_path) - saved_state_dict = checkpoint_dict['model'] - weight_g, weight_v, parent = None, None, None - for key, v in saved_state_dict.items(): - if any(layer in key for layer in skip_list): continue - try: - obj, skip = model, False - for k in key.split('.'): - if k.isnumeric(): obj = obj[int(k)] - elif isinstance(obj, dict): obj = obj[k] - else: - if k in ["weight_g", "weight_v"]: - parent, skip = obj, True - if k == "weight_g": weight_g = v - else: weight_v = v - if not skip: - parent = obj - obj = getattr(obj, k) - if weight_g and weight_v: - setattr(obj, "weight_g", weight_g.numpy()) - setattr(obj, "weight_v", weight_v.numpy()) - obj, v = getattr(parent, "weight"), weight_norm(weight_v, weight_g, 0) - weight_g, weight_v, parent, skip = None, None, None, False - if not skip and obj.shape == v.shape: - if "feature_extractor" in key and (isinstance(parent, (nn.GroupNorm, nn.LayerNorm))): # cast - obj.assign(v.to(obj.device).float()) - else: - obj.assign(v.to(obj.device)) - elif not skip: logging.error(f"MISMATCH SHAPE IN {key}, {obj.shape} {v.shape}") - except Exception as e: raise e - logging.info(f"Loaded checkpoint '{checkpoint_path}' in {time.time() - start_time:.4f}s") - return model, optimizer - -def pad_array(arr, target_length): - current_length = arr.shape[0] - if current_length >= target_length: return arr - pad_width = target_length - current_length - pad_left = pad_width // 2 - pad_right = pad_width - pad_left - padded_arr = np.pad(arr, (pad_left, pad_right), 'constant', constant_values=(0, 0)) - return padded_arr - -def split_list_by_n(list_collection, n, pre=0): - for i in range(0, len(list_collection), n): - yield list_collection[i-pre if i-pre>=0 else i: i + n] - -def get_sid(spk2id:HParams, speaker:str) -> Tensor: - speaker_id = spk2id[speaker] - if not speaker_id and type(speaker) is int: - if len(spk2id.__dict__) >= speaker: speaker_id = speaker - if speaker_id is None: raise RuntimeError(f"speaker={speaker} not in the speaker list") - return Tensor([int(speaker_id)], dtype=dtypes.int64).unsqueeze(0) - -def get_encoder(ssl_dim) -> Type[SpeechEncoder]: - if ssl_dim == 256: return ContentVec256L9 - if ssl_dim == 768: return ContentVec768L12 - -######################################################################################### -# CODE: https://github.com/svc-develop-team/so-vits-svc -######################################################################################### -# CONTENTVEC: -# CODE: https://github.com/auspicious3000/contentvec -# PAPER: https://arxiv.org/abs/2204.09224 -######################################################################################### -# INSTALLATION: dependencies are for preprocessing and loading/saving audio. -# pip3 install soundfile librosa praat-parselmouth -######################################################################################### -# EXAMPLE USAGE: -# python3 examples/so_vits_svc.py --model tf2spy --file ~/recording.wav -######################################################################################### -# DEMO USAGE (uses audio sample from LJ-Speech): -# python3 examples/so_vits_svc.py --model saul_goodman -######################################################################################### -SO_VITS_SVC_PATH = Path(__file__).parents[1] / "weights/So-VITS-SVC" -VITS_MODELS = { # config_path, weights_path, config_url, weights_url - "saul_goodman" : (SO_VITS_SVC_PATH / "config_saul_gman.json", SO_VITS_SVC_PATH / "pretrained_saul_gman.pth", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/Saul_Goodman_80000/config.json", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/Saul_Goodman_80000/G_80000.pth"), - "drake" : (SO_VITS_SVC_PATH / "config_drake.json", SO_VITS_SVC_PATH / "pretrained_drake.pth", "https://huggingface.co/jaspa/so-vits-svc/resolve/main/aubrey/config_aubrey.json", "https://huggingface.co/jaspa/so-vits-svc/resolve/main/aubrey/pretrained_aubrey.pth"), - "cartman" : (SO_VITS_SVC_PATH / "config_cartman.json", SO_VITS_SVC_PATH / "pretrained_cartman.pth", "https://huggingface.co/marcoc2/so-vits-svc-4.0-models/resolve/main/EricCartman/config.json", "https://huggingface.co/marcoc2/so-vits-svc-4.0-models/resolve/main/EricCartman/G_10200.pth"), - "tf2spy" : (SO_VITS_SVC_PATH / "config_tf2spy.json", SO_VITS_SVC_PATH / "pretrained_tf2spy.pth", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/TF2_spy_60k/config.json", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/TF2_spy_60k/G_60000.pth"), - "tf2heavy" : (SO_VITS_SVC_PATH / "config_tf2heavy.json", SO_VITS_SVC_PATH / "pretrained_tf2heavy.pth", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/TF2_heavy_100k/config.json", "https://huggingface.co/Amo/so-vits-svc-4.0_GA/resolve/main/ModelsFolder/TF2_heavy_100k/G_100000.pth"), - "lady_gaga" : (SO_VITS_SVC_PATH / "config_gaga.json", SO_VITS_SVC_PATH / "pretrained_gaga.pth", "https://huggingface.co/marcoc2/so-vits-svc-4.0-models/resolve/main/LadyGaga/config.json", "https://huggingface.co/marcoc2/so-vits-svc-4.0-models/resolve/main/LadyGaga/G_14400.pth") -} -ENCODER_MODELS = { # weights_path, weights_url - "contentvec": (SO_VITS_SVC_PATH / "contentvec_checkpoint.pt", "https://huggingface.co/lj1995/VoiceConversionWebUI/resolve/main/hubert_base.pt") -} -ENCODER_MODEL = "contentvec" -DEMO_PATH, DEMO_URL = Path(__file__).parents[1] / "temp/LJ037-0171.wav", "https://keithito.com/LJ-Speech-Dataset/LJ037-0171.wav" -if __name__=="__main__": - logging.basicConfig(stream=sys.stdout, level=(logging.INFO if DEBUG < 1 else logging.DEBUG)) - parser = argparse.ArgumentParser() - parser.add_argument("-m", "--model", default=None, help=f"Specify the model to use. All supported models: {VITS_MODELS.keys()}", required=True) - parser.add_argument("-f", "--file", default=DEMO_PATH, help=f"Specify the path of the input file") - parser.add_argument("--out_dir", default=str(Path(__file__).parents[1] / "temp"), help="Specify the output path.") - parser.add_argument("--out_path", default=None, help="Specify the full output path. Overrides the --out_dir and --name parameter.") - parser.add_argument("--base_name", default="test", help="Specify the base of the output file name. Default is 'test'.") - parser.add_argument("--speaker", default=None, help="If not specified, the first available speaker is chosen. Usually there is only one speaker per model.") - parser.add_argument("--noise_scale", default=0.4) - parser.add_argument("--tran", default=0.0, help="Pitch shift, supports positive and negative (semitone) values. Default 0.0") - parser.add_argument("--pad_seconds", default=0.5) - parser.add_argument("--lg_num", default=0.0) - parser.add_argument("--clip_seconds", default=0.0) - parser.add_argument("--slice_db", default=-40) - args = parser.parse_args() - - vits_model = args.model - encoder_location, vits_location = ENCODER_MODELS[ENCODER_MODEL], VITS_MODELS[vits_model] - - Tensor.training = False - # Get Synthesizer and ContentVec - net_g, hps = Synthesizer.load_from_pretrained(vits_location[0], vits_location[2], vits_location[1], vits_location[3]) - Encoder = get_encoder(hps.model.ssl_dim) - encoder = Encoder.load_from_pretrained(encoder_location[0], encoder_location[1]) - - # model config args - target_sample, spk2id, hop_length, target_sample = hps.data.sampling_rate, hps.spk, hps.data.hop_length, hps.data.sampling_rate - vol_embedding = hps.model.vol_embedding if hasattr(hps.data, "vol_embedding") and hps.model.vol_embedding is not None else False - - # args - slice_db, clip_seconds, lg_num, pad_seconds, tran, noise_scale, audio_path = args.slice_db, args.clip_seconds, args.lg_num, args.pad_seconds, args.tran, args.noise_scale, args.file - speaker = args.speaker if args.speaker is not None else list(hps.spk.__dict__.keys())[0] - - ### Loading audio and slicing ### - if audio_path == DEMO_PATH: download_if_not_present(DEMO_PATH, DEMO_URL) - assert Path(audio_path).is_file() and Path(audio_path).suffix == ".wav" - chunks = preprocess.cut(audio_path, db_thresh=slice_db) - audio_data, audio_sr = preprocess.chunks2audio(audio_path, chunks) - - per_size = int(clip_seconds * audio_sr) - lg_size = int(lg_num * audio_sr) - - ### Infer per slice ### - global_frame = 0 - audio = [] - for (slice_tag, data) in audio_data: - print(f"\n====segment start, {round(len(data) / audio_sr, 3)}s====") - length = int(np.ceil(len(data) / audio_sr * target_sample)) - - if slice_tag: - print("empty segment") - _audio = np.zeros(length) - audio.extend(list(pad_array(_audio, length))) - global_frame += length // hop_length - continue - - datas = [data] if per_size == 0 else split_list_by_n(data, per_size, lg_size) - - for k, dat in enumerate(datas): - per_length = int(np.ceil(len(dat) / audio_sr * target_sample)) if clip_seconds!=0 else length - pad_len = int(audio_sr * pad_seconds) - dat = np.concatenate([np.zeros([pad_len]), dat, np.zeros([pad_len])]) - raw_path = io.BytesIO() - soundfile.write(raw_path, dat, audio_sr, format="wav") - raw_path.seek(0) - - ### Infer START ### - wav, sr = preprocess.load_audiofile(raw_path) - wav = preprocess.sinc_interp_resample(wav, sr, target_sample)[0] - wav16k, f0, uv = preprocess.get_unit_f0(wav, tran, hop_length, target_sample) - sid = get_sid(spk2id, speaker) - n_frames = f0.shape[1] - - # ContentVec infer - start = time.time() - c = encoder.encode(wav16k) - c = repeat_expand_2d_left(c.squeeze(0).realize(), f0.shape[1]) # interpolate speech encoding to match f0 - c = c.unsqueeze(0).realize() - enc_time = time.time() - start - - # VITS infer - vits_start = time.time() - out_audio, f0 = net_g.infer(c, f0=f0, uv=uv, g=sid, noise_scale=noise_scale, vol=None) - out_audio = out_audio[0,0].float().realize() - vits_time = time.time() - vits_start - - infer_time = time.time() - start - logging.info("total infer time:{:.2f}s, speech_enc time:{:.2f}s, vits time:{:.2f}s".format(infer_time, enc_time, vits_time)) - ### Infer END ### - - out_sr, out_frame = out_audio.shape[-1], n_frames - global_frame += out_frame - _audio = out_audio.numpy() - pad_len = int(target_sample * pad_seconds) - _audio = _audio[pad_len:-pad_len] - _audio = pad_array(_audio, per_length) - audio.extend(list(_audio)) - - audio = np.array(audio) - out_path = Path(args.out_path or Path(args.out_dir)/f"{args.model}{f'_spk_{speaker}'}_{args.base_name}.wav") - out_path.parent.mkdir(parents=True, exist_ok=True) - soundfile.write(out_path, audio, target_sample, format="flac") - logging.info(f"Saved audio output to {out_path}") diff --git a/tinygrad/examples/sovits_helpers/preprocess.py b/tinygrad/examples/sovits_helpers/preprocess.py deleted file mode 100644 index 17a26504..00000000 --- a/tinygrad/examples/sovits_helpers/preprocess.py +++ /dev/null @@ -1,204 +0,0 @@ -import math -from typing import Optional, Tuple -from tinygrad import Tensor, dtypes -import librosa -import soundfile -import numpy as np -import parselmouth - -class PMF0Predictor: # from https://github.com/svc-develop-team/so-vits-svc/ - def __init__(self,hop_length=512,f0_min=50,f0_max=1100,sampling_rate=44100): - self.hop_length, self.f0_min, self.f0_max, self.sampling_rate, self.name = hop_length, f0_min, f0_max, sampling_rate, "pm" - def interpolate_f0(self,f0): - vuv_vector = np.zeros_like(f0, dtype=np.float32) - vuv_vector[f0 > 0.0] = 1.0 - vuv_vector[f0 <= 0.0] = 0.0 - nzindex = np.nonzero(f0)[0] - data = f0[nzindex] - nzindex = nzindex.astype(np.float32) - time_org = self.hop_length / self.sampling_rate * nzindex - time_frame = np.arange(f0.shape[0]) * self.hop_length / self.sampling_rate - if data.shape[0] <= 0: return np.zeros(f0.shape[0], dtype=np.float32),vuv_vector - if data.shape[0] == 1: return np.ones(f0.shape[0], dtype=np.float32) * f0[0],vuv_vector - f0 = np.interp(time_frame, time_org, data, left=data[0], right=data[-1]) - return f0,vuv_vector - def compute_f0(self,wav,p_len=None): - x = wav - if p_len is None: p_len = x.shape[0]//self.hop_length - else: assert abs(p_len-x.shape[0]//self.hop_length) < 4, "pad length error" - time_step = self.hop_length / self.sampling_rate * 1000 - f0 = parselmouth.Sound(x, self.sampling_rate) \ - .to_pitch_ac(time_step=time_step / 1000, voicing_threshold=0.6,pitch_floor=self.f0_min, pitch_ceiling=self.f0_max) \ - .selected_array['frequency'] - pad_size=(p_len - len(f0) + 1) // 2 - if(pad_size>0 or p_len - len(f0) - pad_size>0): - f0 = np.pad(f0,[[pad_size,p_len - len(f0) - pad_size]], mode='constant') - f0,uv = self.interpolate_f0(f0) - return f0 - def compute_f0_uv(self,wav,p_len=None): - x = wav - if p_len is None: p_len = x.shape[0]//self.hop_length - else: assert abs(p_len-x.shape[0]//self.hop_length) < 4, "pad length error" - time_step = self.hop_length / self.sampling_rate * 1000 - f0 = parselmouth.Sound(x, self.sampling_rate).to_pitch_ac( - time_step=time_step / 1000, voicing_threshold=0.6, - pitch_floor=self.f0_min, pitch_ceiling=self.f0_max).selected_array['frequency'] - pad_size=(p_len - len(f0) + 1) // 2 - if(pad_size>0 or p_len - len(f0) - pad_size>0): - f0 = np.pad(f0,[[pad_size,p_len - len(f0) - pad_size]], mode='constant') - f0,uv = self.interpolate_f0(f0) - return f0,uv - -class Slicer: # from https://github.com/svc-develop-team/so-vits-svc/ - def __init__(self, sr: int, threshold: float = -40., min_length: int = 5000, min_interval: int = 300, hop_size: int = 20, max_sil_kept: int = 5000): - if not min_length >= min_interval >= hop_size: - raise ValueError('The following condition must be satisfied: min_length >= min_interval >= hop_size') - if not max_sil_kept >= hop_size: - raise ValueError('The following condition must be satisfied: max_sil_kept >= hop_size') - min_interval = sr * min_interval / 1000 - self.threshold = 10 ** (threshold / 20.) - self.hop_size = round(sr * hop_size / 1000) - self.win_size = min(round(min_interval), 4 * self.hop_size) - self.min_length = round(sr * min_length / 1000 / self.hop_size) - self.min_interval = round(min_interval / self.hop_size) - self.max_sil_kept = round(sr * max_sil_kept / 1000 / self.hop_size) - def _apply_slice(self, waveform, begin, end): - if len(waveform.shape) > 1: return waveform[:, begin * self.hop_size: min(waveform.shape[1], end * self.hop_size)] - else: return waveform[begin * self.hop_size: min(waveform.shape[0], end * self.hop_size)] - def slice(self, waveform): - samples = librosa.to_mono(waveform) if len(waveform.shape) > 1 else waveform - if samples.shape[0] <= self.min_length: return {"0": {"slice": False, "split_time": f"0,{len(waveform)}"}} - rms_list = librosa.feature.rms(y=samples, frame_length=self.win_size, hop_length=self.hop_size).squeeze(0) - sil_tags, silence_start, clip_start = [], None, 0 - for i, rms in enumerate(rms_list): - if rms < self.threshold: # Keep looping while frame is silent. - if silence_start is None: # Record start of silent frames. - silence_start = i - continue - if silence_start is None: continue # Keep looping while frame is not silent and silence start has not been recorded. - # Clear recorded silence start if interval is not enough or clip is too short - is_leading_silence = silence_start == 0 and i > self.max_sil_kept - need_slice_middle = i - silence_start >= self.min_interval and i - clip_start >= self.min_length - if not is_leading_silence and not need_slice_middle: - silence_start = None - continue - if i - silence_start <= self.max_sil_kept: # Need slicing. Record the range of silent frames to be removed. - pos = rms_list[silence_start: i + 1].argmin() + silence_start - sil_tags.append((0, pos) if silence_start == 0 else (pos, pos)) - clip_start = pos - elif i - silence_start <= self.max_sil_kept * 2: - pos = rms_list[i - self.max_sil_kept: silence_start + self.max_sil_kept + 1].argmin() - pos += i - self.max_sil_kept - pos_l = rms_list[silence_start: silence_start + self.max_sil_kept + 1].argmin() + silence_start - pos_r = rms_list[i - self.max_sil_kept: i + 1].argmin() + i - self.max_sil_kept - if silence_start == 0: - sil_tags.append((0, pos_r)) - clip_start = pos_r - else: - sil_tags.append((min(pos_l, pos), max(pos_r, pos))) - clip_start = max(pos_r, pos) - else: - pos_l = rms_list[silence_start: silence_start + self.max_sil_kept + 1].argmin() + silence_start - pos_r = rms_list[i - self.max_sil_kept: i + 1].argmin() + i - self.max_sil_kept - sil_tags.append((0, pos_r) if silence_start == 0 else (pos_l, pos_r)) - clip_start = pos_r - silence_start = None - total_frames = rms_list.shape[0] - if silence_start is not None and total_frames - silence_start >= self.min_interval: # Deal with trailing silence. - silence_end = min(total_frames, silence_start + self.max_sil_kept) - pos = rms_list[silence_start: silence_end + 1].argmin() + silence_start - sil_tags.append((pos, total_frames + 1)) - if len(sil_tags) == 0: return {"0": {"slice": False, "split_time": f"0,{len(waveform)}"}} # Apply and return slices. - chunks = [] - if sil_tags[0][0]: - chunks.append({"slice": False, "split_time": f"0,{min(waveform.shape[0], sil_tags[0][0] * self.hop_size)}"}) - for i in range(0, len(sil_tags)): - if i: chunks.append({"slice": False, "split_time": f"{sil_tags[i - 1][1] * self.hop_size},{min(waveform.shape[0], sil_tags[i][0] * self.hop_size)}"}) - chunks.append({"slice": True, "split_time": f"{sil_tags[i][0] * self.hop_size},{min(waveform.shape[0], sil_tags[i][1] * self.hop_size)}"}) - if sil_tags[-1][1] * self.hop_size < len(waveform): - chunks.append({"slice": False, "split_time": f"{sil_tags[-1][1] * self.hop_size},{len(waveform)}"}) - chunk_dict = {} - for i in range(len(chunks)): chunk_dict[str(i)] = chunks[i] - return chunk_dict - -# sinc_interp_hann audio resampling -class Resample: - def __init__(self, orig_freq:int=16000, new_freq:int=16000, lowpass_filter_width:int=6, rolloff:float=0.99, beta:Optional[float]=None, dtype:Optional[dtypes]=None): - self.orig_freq, self.new_freq, self.lowpass_filter_width, self.rolloff, self.beta = orig_freq, new_freq, lowpass_filter_width, rolloff, beta - self.gcd = math.gcd(int(self.orig_freq), int(self.new_freq)) - self.kernel, self.width = self._get_sinc_resample_kernel(dtype) if self.orig_freq != self.new_freq else (None, None) - def __call__(self, waveform:Tensor) -> Tensor: - if self.orig_freq == self.new_freq: return waveform - return self._apply_sinc_resample_kernel(waveform) - def _apply_sinc_resample_kernel(self, waveform:Tensor): - if not waveform.is_floating_point(): raise TypeError(f"Waveform tensor expected to be of type float, but received {waveform.dtype}.") - orig_freq, new_freq = (int(self.orig_freq) // self.gcd), (int(self.new_freq) // self.gcd) - shape = waveform.shape - waveform = waveform.reshape(-1, shape[-1]) # pack batch - num_wavs, length = waveform.shape - target_length = int(math.ceil(new_freq * length / orig_freq)) - waveform = waveform.pad((self.width, self.width + orig_freq)) - resampled = waveform[:, None].conv2d(self.kernel, stride=orig_freq) - resampled = resampled.transpose(1, 2).reshape(num_wavs, -1) - resampled = resampled[..., :target_length] - resampled = resampled.reshape(shape[:-1] + resampled.shape[-1:]) # unpack batch - return resampled - def _get_sinc_resample_kernel(self, dtype=None): - orig_freq, new_freq = (int(self.orig_freq) // self.gcd), (int(self.new_freq) // self.gcd) - if self.lowpass_filter_width <= 0: raise ValueError("Low pass filter width should be positive.") - base_freq = min(orig_freq, new_freq) - base_freq *= self.rolloff - width = math.ceil(self.lowpass_filter_width * orig_freq / base_freq) - idx = Tensor.arange(-width, width + orig_freq, dtype=(dtype if dtype is not None else dtypes.float32))[None, None] / orig_freq - t = Tensor.arange(0, -new_freq, -1, dtype=dtype)[:, None, None] / new_freq + idx - t *= base_freq - t = t.clip(-self.lowpass_filter_width, self.lowpass_filter_width) - window = (t * math.pi / self.lowpass_filter_width / 2).cos() ** 2 - t *= math.pi - scale = base_freq / orig_freq - kernels = Tensor.where(t == 0, Tensor(1.0, dtype=t.dtype).to(t.device), t.sin() / t) - kernels *= window * scale - if dtype is None: kernels = kernels.cast(dtype=dtypes.float32) - return kernels, width - -def sinc_interp_resample(x:Tensor, orig_freq:int=16000, new_freq:int=1600, lowpass_filter_width:int=6, rolloff:float=0.99, beta:Optional[float]=None): - resamp = Resample(orig_freq, new_freq, lowpass_filter_width, rolloff, beta, x.dtype) - return resamp(x) - -def cut(audio_path, db_thresh=-30, min_len=5000): - audio, sr = librosa.load(audio_path, sr=None) - slicer = Slicer(sr=sr, threshold=db_thresh, min_length=min_len) - chunks = slicer.slice(audio) - return chunks - -def chunks2audio(audio_path, chunks): - chunks = dict(chunks) - audio, sr = load_audiofile(audio_path) - if len(audio.shape) == 2 and audio.shape[1] >= 2: - audio = audio.mean(0).unsqueeze(0) - audio = audio.numpy()[0] - result = [] - for k, v in chunks.items(): - tag = v["split_time"].split(",") - if tag[0] != tag[1]: - result.append((v["slice"], audio[int(tag[0]):int(tag[1])])) - return result, sr - -def load_audiofile(filepath:str, frame_offset:int=0, num_frames:int=-1, channels_first:bool=True): - with soundfile.SoundFile(filepath, "r") as file_: - frames = file_._prepare_read(frame_offset, None, num_frames) - waveform = file_.read(frames, "float32", always_2d=True) - sample_rate = file_.samplerate - waveform = Tensor(waveform) - if channels_first: waveform = waveform.transpose(0, 1) - return waveform, sample_rate - -def get_unit_f0(wav:Tensor, tran, hop_length, target_sample, f0_filter=False) -> Tuple[Tensor,Tensor,Tensor]: - f0_predictor = PMF0Predictor(hop_length, sampling_rate=target_sample) - f0, uv = f0_predictor.compute_f0_uv(wav.numpy()) - if f0_filter and sum(f0) == 0: raise RuntimeError("No voice detected") - f0 = Tensor(f0.astype(np.float32)).float() - f0 = (f0 * 2 ** (tran / 12)).unsqueeze(0) - uv = Tensor(uv.astype(np.float32)).float().unsqueeze(0) - wav16k = sinc_interp_resample(wav[None,:], target_sample, 16000)[0] - return wav16k.realize(), f0.realize(), uv.realize() diff --git a/tinygrad/examples/stable_diffusion.py b/tinygrad/examples/stable_diffusion.py deleted file mode 100644 index 44dca39e..00000000 --- a/tinygrad/examples/stable_diffusion.py +++ /dev/null @@ -1,296 +0,0 @@ -# https://arxiv.org/pdf/2112.10752.pdf -# https://github.com/ekagra-ranjan/huggingface-blog/blob/main/stable_diffusion.md -import tempfile -from pathlib import Path -import argparse -from collections import namedtuple -from typing import Dict, Any - -from PIL import Image -import numpy as np -from tinygrad import Device, GlobalCounters, dtypes, Tensor, TinyJit -from tinygrad.helpers import Timing, Context, getenv, fetch, colored, tqdm -from tinygrad.nn import Conv2d, GroupNorm -from tinygrad.nn.state import torch_load, load_state_dict, get_state_dict -from extra.models.clip import Closed, Tokenizer -from extra.models.unet import UNetModel -from extra.bench_log import BenchEvent, WallTimeEvent - -class AttnBlock: - def __init__(self, in_channels): - self.norm = GroupNorm(32, in_channels) - self.q = Conv2d(in_channels, in_channels, 1) - self.k = Conv2d(in_channels, in_channels, 1) - self.v = Conv2d(in_channels, in_channels, 1) - self.proj_out = Conv2d(in_channels, in_channels, 1) - - # copied from AttnBlock in ldm repo - def __call__(self, x): - h_ = self.norm(x) - q,k,v = self.q(h_), self.k(h_), self.v(h_) - - # compute attention - b,c,h,w = q.shape - q,k,v = [x.reshape(b,c,h*w).transpose(1,2) for x in (q,k,v)] - h_ = Tensor.scaled_dot_product_attention(q,k,v).transpose(1,2).reshape(b,c,h,w) - return x + self.proj_out(h_) - -class ResnetBlock: - def __init__(self, in_channels, out_channels=None): - self.norm1 = GroupNorm(32, in_channels) - self.conv1 = Conv2d(in_channels, out_channels, 3, padding=1) - self.norm2 = GroupNorm(32, out_channels) - self.conv2 = Conv2d(out_channels, out_channels, 3, padding=1) - self.nin_shortcut = Conv2d(in_channels, out_channels, 1) if in_channels != out_channels else lambda x: x - - def __call__(self, x): - h = self.conv1(self.norm1(x).swish()) - h = self.conv2(self.norm2(h).swish()) - return self.nin_shortcut(x) + h - -class Mid: - def __init__(self, block_in): - self.block_1 = ResnetBlock(block_in, block_in) - self.attn_1 = AttnBlock(block_in) - self.block_2 = ResnetBlock(block_in, block_in) - - def __call__(self, x): - return x.sequential([self.block_1, self.attn_1, self.block_2]) - -class Decoder: - def __init__(self): - sz = [(128, 256), (256, 512), (512, 512), (512, 512)] - self.conv_in = Conv2d(4,512,3, padding=1) - self.mid = Mid(512) - - arr = [] - for i,s in enumerate(sz): - arr.append({"block": - [ResnetBlock(s[1], s[0]), - ResnetBlock(s[0], s[0]), - ResnetBlock(s[0], s[0])]}) - if i != 0: arr[-1]['upsample'] = {"conv": Conv2d(s[0], s[0], 3, padding=1)} - self.up = arr - - self.norm_out = GroupNorm(32, 128) - self.conv_out = Conv2d(128, 3, 3, padding=1) - - def __call__(self, x): - x = self.conv_in(x) - x = self.mid(x) - - for l in self.up[::-1]: - print("decode", x.shape) - for b in l['block']: x = b(x) - if 'upsample' in l: - # https://pytorch.org/docs/stable/generated/torch.nn.functional.interpolate.html ? - bs,c,py,px = x.shape - x = x.reshape(bs, c, py, 1, px, 1).expand(bs, c, py, 2, px, 2).reshape(bs, c, py*2, px*2) - x = l['upsample']['conv'](x) - x.realize() - - return self.conv_out(self.norm_out(x).swish()) - -class Encoder: - def __init__(self): - sz = [(128, 128), (128, 256), (256, 512), (512, 512)] - self.conv_in = Conv2d(3,128,3, padding=1) - - arr = [] - for i,s in enumerate(sz): - arr.append({"block": - [ResnetBlock(s[0], s[1]), - ResnetBlock(s[1], s[1])]}) - if i != 3: arr[-1]['downsample'] = {"conv": Conv2d(s[1], s[1], 3, stride=2, padding=(0,1,0,1))} - self.down = arr - - self.mid = Mid(512) - self.norm_out = GroupNorm(32, 512) - self.conv_out = Conv2d(512, 8, 3, padding=1) - - def __call__(self, x): - x = self.conv_in(x) - - for l in self.down: - print("encode", x.shape) - for b in l['block']: x = b(x) - if 'downsample' in l: x = l['downsample']['conv'](x) - - x = self.mid(x) - return self.conv_out(self.norm_out(x).swish()) - -class AutoencoderKL: - def __init__(self): - self.encoder = Encoder() - self.decoder = Decoder() - self.quant_conv = Conv2d(8, 8, 1) - self.post_quant_conv = Conv2d(4, 4, 1) - - def __call__(self, x): - latent = self.encoder(x) - latent = self.quant_conv(latent) - latent = latent[:, 0:4] # only the means - print("latent", latent.shape) - latent = self.post_quant_conv(latent) - return self.decoder(latent) - -def get_alphas_cumprod(beta_start=0.00085, beta_end=0.0120, n_training_steps=1000): - betas = np.linspace(beta_start ** 0.5, beta_end ** 0.5, n_training_steps, dtype=np.float32) ** 2 - alphas = 1.0 - betas - alphas_cumprod = np.cumprod(alphas, axis=0) - return Tensor(alphas_cumprod) - -unet_params: Dict[str,Any] = { - "adm_in_ch": None, - "in_ch": 4, - "out_ch": 4, - "model_ch": 320, - "attention_resolutions": [4, 2, 1], - "num_res_blocks": 2, - "channel_mult": [1, 2, 4, 4], - "n_heads": 8, - "transformer_depth": [1, 1, 1, 1], - "ctx_dim": 768, - "use_linear": False, -} - -class StableDiffusion: - def __init__(self): - self.alphas_cumprod = get_alphas_cumprod() - self.model = namedtuple("DiffusionModel", ["diffusion_model"])(diffusion_model = UNetModel(**unet_params)) - self.first_stage_model = AutoencoderKL() - self.cond_stage_model = namedtuple("CondStageModel", ["transformer"])(transformer = namedtuple("Transformer", ["text_model"])(text_model = Closed.ClipTextTransformer())) - - def get_x_prev_and_pred_x0(self, x, e_t, a_t, a_prev): - temperature = 1 - sigma_t = 0 - sqrt_one_minus_at = (1-a_t).sqrt() - #print(a_t, a_prev, sigma_t, sqrt_one_minus_at) - - pred_x0 = (x - sqrt_one_minus_at * e_t) / a_t.sqrt() - - # direction pointing to x_t - dir_xt = (1. - a_prev - sigma_t**2).sqrt() * e_t - - x_prev = a_prev.sqrt() * pred_x0 + dir_xt - return x_prev, pred_x0 - - def get_model_output(self, unconditional_context, context, latent, timestep, unconditional_guidance_scale): - # put into diffuser - latents = self.model.diffusion_model(latent.expand(2, *latent.shape[1:]), timestep, unconditional_context.cat(context, dim=0)) - unconditional_latent, latent = latents[0:1], latents[1:2] - - e_t = unconditional_latent + unconditional_guidance_scale * (latent - unconditional_latent) - return e_t - - def decode(self, x): - x = self.first_stage_model.post_quant_conv(1/0.18215 * x) - x = self.first_stage_model.decoder(x) - - # make image correct size and scale - x = (x + 1.0) / 2.0 - x = x.reshape(3,512,512).permute(1,2,0).clip(0,1)*255 - return x.cast(dtypes.uint8) - - def __call__(self, unconditional_context, context, latent, timestep, alphas, alphas_prev, guidance): - e_t = self.get_model_output(unconditional_context, context, latent, timestep, guidance) - x_prev, _ = self.get_x_prev_and_pred_x0(latent, e_t, alphas, alphas_prev) - #e_t_next = get_model_output(x_prev) - #e_t_prime = (e_t + e_t_next) / 2 - #x_prev, pred_x0 = get_x_prev_and_pred_x0(latent, e_t_prime, index) - return x_prev.realize() - -# ** ldm.models.autoencoder.AutoencoderKL (done!) -# 3x512x512 <--> 4x64x64 (16384) -# decode torch.Size([1, 4, 64, 64]) torch.Size([1, 3, 512, 512]) -# section 4.3 of paper -# first_stage_model.encoder, first_stage_model.decoder - -# ** ldm.modules.diffusionmodules.openaimodel.UNetModel -# this is what runs each time to sample. is this the LDM? -# input: 4x64x64 -# output: 4x64x64 -# model.diffusion_model -# it has attention? - -# ** ldm.modules.encoders.modules.FrozenCLIPEmbedder -# cond_stage_model.transformer.text_model - -if __name__ == "__main__": - default_prompt = "a horse sized cat eating a bagel" - parser = argparse.ArgumentParser(description='Run Stable Diffusion', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--steps', type=int, default=6, help="Number of steps in diffusion") - parser.add_argument('--prompt', type=str, default=default_prompt, help="Phrase to render") - parser.add_argument('--out', type=str, default=Path(tempfile.gettempdir()) / "rendered.png", help="Output filename") - parser.add_argument('--noshow', action='store_true', help="Don't show the image") - parser.add_argument('--fp16', action='store_true', help="Cast the weights to float16") - parser.add_argument('--timing', action='store_true', help="Print timing per step") - parser.add_argument('--seed', type=int, help="Set the random latent seed") - parser.add_argument('--guidance', type=float, default=7.5, help="Prompt strength") - args = parser.parse_args() - - model = StableDiffusion() - - # load in weights - with WallTimeEvent(BenchEvent.LOAD_WEIGHTS): - load_state_dict(model, torch_load(fetch('https://huggingface.co/CompVis/stable-diffusion-v-1-4-original/resolve/main/sd-v1-4.ckpt', 'sd-v1-4.ckpt'))['state_dict'], strict=False) - - if args.fp16: - for k,v in get_state_dict(model).items(): - if k.startswith("model"): - v.replace(v.cast(dtypes.float16).realize()) - - # run through CLIP to get context - tokenizer = Tokenizer.ClipTokenizer() - prompt = Tensor([tokenizer.encode(args.prompt)]) - context = model.cond_stage_model.transformer.text_model(prompt).realize() - print("got CLIP context", context.shape) - - prompt = Tensor([tokenizer.encode("")]) - unconditional_context = model.cond_stage_model.transformer.text_model(prompt).realize() - print("got unconditional CLIP context", unconditional_context.shape) - - # done with clip model - del model.cond_stage_model - - timesteps = list(range(1, 1000, 1000//args.steps)) - print(f"running for {timesteps} timesteps") - alphas = model.alphas_cumprod[Tensor(timesteps)] - alphas_prev = Tensor([1.0]).cat(alphas[:-1]) - - # start with random noise - if args.seed is not None: Tensor.manual_seed(args.seed) - latent = Tensor.randn(1,4,64,64) - - @TinyJit - def run(model, *x): return model(*x).realize() - - # this is diffusion - with Context(BEAM=getenv("LATEBEAM")): - for index, timestep in (t:=tqdm(list(enumerate(timesteps))[::-1])): - GlobalCounters.reset() - t.set_description("%3d %3d" % (index, timestep)) - with Timing("step in ", enabled=args.timing, on_exit=lambda _: f", using {GlobalCounters.mem_used/1e9:.2f} GB"): - with WallTimeEvent(BenchEvent.STEP): - tid = Tensor([index]) - latent = run(model, unconditional_context, context, latent, Tensor([timestep]), alphas[tid], alphas_prev[tid], Tensor([args.guidance])) - if args.timing: Device[Device.DEFAULT].synchronize() - del run - - # upsample latent space to image with autoencoder - x = model.decode(latent) - print(x.shape) - - # save image - im = Image.fromarray(x.numpy()) - print(f"saving {args.out}") - im.save(args.out) - # Open image. - if not args.noshow: im.show() - - # validation! - if args.prompt == default_prompt and args.steps == 6 and args.seed == 0 and args.guidance == 7.5: - ref_image = Tensor(np.array(Image.open(Path(__file__).parent / "stable_diffusion_seed0.png"))) - distance = (((x.cast(dtypes.float) - ref_image.cast(dtypes.float)) / ref_image.max())**2).mean().item() - assert distance < 3e-3, colored(f"validation failed with {distance=}", "red") # higher distance with WINO - print(colored(f"output validated with {distance=}", "green")) diff --git a/tinygrad/examples/stable_diffusion_seed0.png b/tinygrad/examples/stable_diffusion_seed0.png deleted file mode 100644 index 17855b1d..00000000 Binary files a/tinygrad/examples/stable_diffusion_seed0.png and /dev/null differ diff --git a/tinygrad/examples/stunning_mnist.py b/tinygrad/examples/stunning_mnist.py deleted file mode 100644 index 66c5aa82..00000000 --- a/tinygrad/examples/stunning_mnist.py +++ /dev/null @@ -1,60 +0,0 @@ -# beautiful mnist in the new "one-shot" style -# one realize in the whole graph -# depends on: -# - "big graph" UOp scheduling -# - symbolic removal - -from examples.beautiful_mnist import Model -from tinygrad import Tensor, nn, getenv, GlobalCounters, Variable -from tinygrad.nn.datasets import mnist -from tinygrad.helpers import trange, DEBUG - -# STEPS=70 python3 examples/stunning_mnist.py -# NOTE: it's broken with STACK=1, why? - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = mnist() - print("*** got data") - - model = Model() - print("*** got model") - - opt = nn.optim.Adam(nn.state.get_parameters(model)) - print("*** got optimizer") - - samples = Tensor.randint(getenv("STEPS", 10), getenv("BS", 512), high=X_train.shape[0]) - X_samp, Y_samp = X_train[samples], Y_train[samples] - print("*** got samples") - - with Tensor.train(): - """ - i = UOp.range(samples.shape[0]) # TODO: fix range function on UOp - losses = model(X_samp[i]).sparse_categorical_crossentropy(Y_samp[i]).backward().contract(i) - opt.schedule_steps(i) - """ - # TODO: this shouldn't be a for loop. something like: (contract is still up in the air) - vi = Variable('i', 0, samples.shape[0]-1) - losses = [] - for i in range(samples.shape[0]): - vib = vi.bind(i) - opt.zero_grad() - losses.append(model(X_samp[vib]).sparse_categorical_crossentropy(Y_samp[vib]).backward()) - opt.schedule_step() - # TODO: this stack currently breaks the "generator" aspect of losses. it probably shouldn't - if getenv("STACK", 0): losses = Tensor.stack(*losses) - print("*** scheduled training") - - # evaluate the model - test_acc = ((model(X_test).argmax(axis=1) == Y_test).mean()*100) - print("*** scheduled eval") - - # NOTE: there's no kernels run in the scheduling phase - assert GlobalCounters.kernel_count == 0, "kernels were run during scheduling!" - - # only actually do anything at the end - if getenv("LOSS", 1): - for i in (t:=trange(len(losses))): - GlobalCounters.reset() - t.set_description(f"loss: {losses[i].item():6.2f}") - if getenv("TEST", 1): - print(f"test_accuracy: {test_acc.item():5.2f}%") diff --git a/tinygrad/examples/test_onnx_imagenet.py b/tinygrad/examples/test_onnx_imagenet.py deleted file mode 100644 index 11f469ae..00000000 --- a/tinygrad/examples/test_onnx_imagenet.py +++ /dev/null @@ -1,82 +0,0 @@ -import random, sys -import numpy as np -from extra.datasets.imagenet import get_imagenet_categories, get_val_files, center_crop -from examples.benchmark_onnx import load_onnx_model -from PIL import Image -from tinygrad import Tensor, dtypes, GlobalCounters -from tinygrad.helpers import fetch, getenv - -# works: -# ~70% - https://github.com/onnx/models/raw/refs/heads/main/validated/vision/classification/resnet/model/resnet50-v2-7.onnx -# ~43% - https://github.com/onnx/models/raw/refs/heads/main/Computer_Vision/alexnet_Opset16_torch_hub/alexnet_Opset16.onnx -# ~72% - https://github.com/xamcat/mobcat-samples/raw/refs/heads/master/onnx_runtime/InferencingSample/InferencingSample/mobilenetv2-7.onnx -# ~71% - https://github.com/axinc-ai/onnx-quantization/raw/refs/heads/main/models/mobilenetv2_1.0.opt.onnx -# ~67% - https://github.com/xamcat/mobcat-samples/raw/refs/heads/master/onnx_runtime/InferencingSample/InferencingSample/mobilenetv2-7-quantized.onnx -# broken: -# https://github.com/MTlab/onnx2caffe/raw/refs/heads/master/model/MobileNetV2.onnx -# https://huggingface.co/qualcomm/MobileNet-v2-Quantized/resolve/main/MobileNet-v2-Quantized.onnx -# ~35% - https://github.com/axinc-ai/onnx-quantization/raw/refs/heads/main/models/mobilenev2_quantized.onnx - -# QUANT=1 python3 examples/test_onnx_imagenet.py -# https://github.com/xamcat/mobcat-samples/raw/refs/heads/master/onnx_runtime/InferencingSample/InferencingSample/mobilenetv2-7.onnx -# DONT_REALIZE_EXPAND=1 python3 examples/test_onnx_imagenet.py /tmp/model.quant.onnx -# VIZ=1 DONT_REALIZE_EXPAND=1 python3 examples/benchmark_onnx.py /tmp/model.quant.onnx - -def imagenet_dataloader(cnt=0): - input_mean = Tensor([0.485, 0.456, 0.406]).reshape(1, -1, 1, 1) - input_std = Tensor([0.229, 0.224, 0.225]).reshape(1, -1, 1, 1) - files = get_val_files() - random.shuffle(files) - files = files[:cnt] - cir = get_imagenet_categories() - for fn in files: - img = Image.open(fn) - img = img.convert('RGB') if img.mode != "RGB" else img - img = center_crop(img) - img = np.array(img) - img = Tensor(img).permute(2,0,1).reshape(1,3,224,224) - img = ((img.cast(dtypes.float32)/255.0) - input_mean) / input_std - y = cir[fn.split("/")[-2]] - yield img,y - -if __name__ == "__main__": - fn = sys.argv[1] - if getenv("QUANT"): - from onnxruntime.quantization import quantize_dynamic, quantize_static, QuantFormat, QuantType, CalibrationDataReader - model_fp32 = fetch(fn) - fn = '/tmp/model.quant.onnx' - if getenv("DYNAMIC"): - quantize_dynamic(model_fp32, fn) - else: - class ImagenetReader(CalibrationDataReader): - def __init__(self): - self.iter = imagenet_dataloader(cnt=1000) - def get_next(self) -> dict: - try: - img,y = next(self.iter) - except StopIteration: - return None - return {"input": img.numpy()} - quantize_static(model_fp32, fn, ImagenetReader(), quant_format=QuantFormat.QDQ, per_channel=False, - activation_type=QuantType.QUInt8, weight_type=QuantType.QUInt8, - extra_options={"ActivationSymmetric": False}) - - run_onnx_jit, input_specs = load_onnx_model(fetch(fn)) - t_name, t_spec = list(input_specs.items())[0] - assert t_spec.shape[1:] == (3,224,224), f"shape is {t_spec.shape}" - - hit = 0 - for i,(img,y) in enumerate(imagenet_dataloader(cnt:=getenv("CNT", 100))): - GlobalCounters.reset() - p = run_onnx_jit(**{t_name:img}) - assert p.shape == (1,1000) - t = p.to('cpu').argmax().item() - hit += y==t - print(f"target: {y:3d} pred: {t:3d} acc: {hit/(i+1)*100:.2f}%") - - MS_TARGET = 13.4 - print(f"need {GlobalCounters.global_ops/1e9*(1000/MS_TARGET):.2f} GFLOPS for {MS_TARGET:.2f} ms") - - if cnt >= 2: - import pickle - with open("/tmp/im.pkl", "wb") as f: pickle.dump(run_onnx_jit, f) diff --git a/tinygrad/examples/test_pkl_imagenet.py b/tinygrad/examples/test_pkl_imagenet.py deleted file mode 100644 index 8110abf3..00000000 --- a/tinygrad/examples/test_pkl_imagenet.py +++ /dev/null @@ -1,19 +0,0 @@ -import sys, pickle -from tinygrad import GlobalCounters -from tinygrad.helpers import fetch, getenv -from examples.test_onnx_imagenet import imagenet_dataloader - -if __name__ == "__main__": - with open(fetch(sys.argv[1]), "rb") as f: - run_onnx_jit = pickle.load(f) - input_name = run_onnx_jit.captured.expected_names[0] - device = run_onnx_jit.captured.expected_st_vars_dtype_device[0][-1] - print(f"input goes into {input_name=} on {device=}") - hit = 0 - for i,(img,y) in enumerate(imagenet_dataloader(cnt=getenv("CNT", 100))): - GlobalCounters.reset() - p = run_onnx_jit(**{input_name:img.to(device)}) - assert p.shape == (1,1000) - t = p.to('cpu').argmax().item() - hit += y==t - print(f"target: {y:3d} pred: {t:3d} acc: {hit/(i+1)*100:.2f}%") diff --git a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpine-collective/toolkit@1.0.2/dist/cdn.min.js b/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpine-collective/toolkit@1.0.2/dist/cdn.min.js deleted file mode 100644 index a363545c..00000000 --- a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpine-collective/toolkit@1.0.2/dist/cdn.min.js +++ /dev/null @@ -1 +0,0 @@ -(()=>{var H=Object.create,v=Object.defineProperty,N=Object.getPrototypeOf,V=Object.prototype.hasOwnProperty,z=Object.getOwnPropertyNames,q=Object.getOwnPropertyDescriptor;var W=n=>v(n,"__esModule",{value:!0});var D=(n,e)=>()=>(e||(e={exports:{}},n(e.exports,e)),e.exports);var F=(n,e,o)=>{if(e&&typeof e=="object"||typeof e=="function")for(let r of z(e))!V.call(n,r)&&r!=="default"&&v(n,r,{get:()=>e[r],enumerable:!(o=q(e,r))||o.enumerable});return n},U=n=>F(W(v(n!=null?H(N(n)):{},"default",n&&n.__esModule&&"default"in n?{get:()=>n.default,enumerable:!0}:{value:n,enumerable:!0})),n);var I=D((E,w)=>{(function(){"use strict";function n(){var e=window,o=document;if("scrollBehavior"in o.documentElement.style&&e.__forceSmoothScrollPolyfill__!==!0)return;var r=e.HTMLElement||e.Element,i=468,f={scroll:e.scroll||e.scrollTo,scrollBy:e.scrollBy,elementScroll:r.prototype.scroll||b,scrollIntoView:r.prototype.scrollIntoView},u=e.performance&&e.performance.now?e.performance.now.bind(e.performance):Date.now;function c(t){var l=["MSIE ","Trident/","Edge/"];return new RegExp(l.join("|")).test(t)}var g=c(e.navigator.userAgent)?1:0;function b(t,l){this.scrollLeft=t,this.scrollTop=l}function M(t){return .5*(1-Math.cos(Math.PI*t))}function m(t){if(t===null||typeof t!="object"||t.behavior===void 0||t.behavior==="auto"||t.behavior==="instant")return!0;if(typeof t=="object"&&t.behavior==="smooth")return!1;throw new TypeError("behavior member of ScrollOptions "+t.behavior+" is not a valid value for enumeration ScrollBehavior.")}function O(t,l){if(l==="Y")return t.clientHeight+g1?1:a,s=M(a),d=t.startX+(t.x-t.startX)*s,p=t.startY+(t.y-t.startY)*s,t.method.call(t.scrollable,d,p),(d!==t.x||p!==t.y)&&e.requestAnimationFrame(S.bind(e,t))}function h(t,l,s){var d,p,a,y,_=u();t===o.body?(d=e,p=e.scrollX||e.pageXOffset,a=e.scrollY||e.pageYOffset,y=f.scroll):(d=t,p=t.scrollLeft,a=t.scrollTop,y=b),S({scrollable:d,method:y,startTime:_,startX:p,startY:a,x:l,y:s})}e.scroll=e.scrollTo=function(){if(arguments[0]!==void 0){if(m(arguments[0])===!0){f.scroll.call(e,arguments[0].left!==void 0?arguments[0].left:typeof arguments[0]!="object"?arguments[0]:e.scrollX||e.pageXOffset,arguments[0].top!==void 0?arguments[0].top:arguments[1]!==void 0?arguments[1]:e.scrollY||e.pageYOffset);return}h.call(e,o.body,arguments[0].left!==void 0?~~arguments[0].left:e.scrollX||e.pageXOffset,arguments[0].top!==void 0?~~arguments[0].top:e.scrollY||e.pageYOffset)}},e.scrollBy=function(){if(arguments[0]!==void 0){if(m(arguments[0])){f.scrollBy.call(e,arguments[0].left!==void 0?arguments[0].left:typeof arguments[0]!="object"?arguments[0]:0,arguments[0].top!==void 0?arguments[0].top:arguments[1]!==void 0?arguments[1]:0);return}h.call(e,o.body,~~arguments[0].left+(e.scrollX||e.pageXOffset),~~arguments[0].top+(e.scrollY||e.pageYOffset))}},r.prototype.scroll=r.prototype.scrollTo=function(){if(arguments[0]!==void 0){if(m(arguments[0])===!0){if(typeof arguments[0]=="number"&&arguments[1]===void 0)throw new SyntaxError("Value could not be converted");f.elementScroll.call(this,arguments[0].left!==void 0?~~arguments[0].left:typeof arguments[0]!="object"?~~arguments[0]:this.scrollLeft,arguments[0].top!==void 0?~~arguments[0].top:arguments[1]!==void 0?~~arguments[1]:this.scrollTop);return}var t=arguments[0].left,l=arguments[0].top;h.call(this,this,typeof t=="undefined"?this.scrollLeft:~~t,typeof l=="undefined"?this.scrollTop:~~l)}},r.prototype.scrollBy=function(){if(arguments[0]!==void 0){if(m(arguments[0])===!0){f.elementScroll.call(this,arguments[0].left!==void 0?~~arguments[0].left+this.scrollLeft:~~arguments[0]+this.scrollLeft,arguments[0].top!==void 0?~~arguments[0].top+this.scrollTop:~~arguments[1]+this.scrollTop);return}this.scroll({left:~~arguments[0].left+this.scrollLeft,top:~~arguments[0].top+this.scrollTop,behavior:arguments[0].behavior})}},r.prototype.scrollIntoView=function(){if(m(arguments[0])===!0){f.scrollIntoView.call(this,arguments[0]===void 0?!0:arguments[0]);return}var t=$(this),l=t.getBoundingClientRect(),s=this.getBoundingClientRect();t!==o.body?(h.call(this,t,t.scrollLeft+s.left-l.left,t.scrollTop+s.top-l.top),e.getComputedStyle(t).position!=="fixed"&&e.scrollBy({left:l.left,top:l.top,behavior:"smooth"})):e.scrollBy({left:s.left,top:s.top,behavior:"smooth"})}}typeof E=="object"&&typeof w!="undefined"?w.exports={polyfill:n}:n()})()});function j(n){n.magic("range",()=>function(e,o,r=1){typeof o=="undefined"&&(o=e,e=e?1:0);let i=e>o;i&&([e,o]=[o,e]);let f=Array.from({length:(o-e)/r+1},(u,c)=>e+c*r);return i?f.reverse():f})}var Y=U(I());function X(n){Y.default.polyfill(),n.magic("scroll",()=>function(e,o={}){let r=e,i=o.offset?parseInt(o.offset,10):0;if(delete o.offset,typeof e=="string"&&/^[0-9]+?/g.test(e)&&(e=parseInt(e,10)),typeof e=="string"&&(e=document.querySelector(e)),e instanceof Element&&(e=Math.floor(e.getBoundingClientRect().top+window.pageYOffset)),Number.isInteger(e)&&(e={top:e-i,behavior:"smooth"}),typeof e!="object")throw Error("Unsupported $scroll target: ",r);Object.assign(e,o),window.scroll(e)})}function B(n){let e=(o,r)=>{if(r[0].length<=o.length)return o;let i="\u2026";return typeof r[2]!="undefined"&&(i=r[2]),Object.prototype.hasOwnProperty.call(r[1],"ellipsis")&&(i=r[1].ellipsis),o+i};n.magic("truncate",()=>function(...o){return typeof o[0]!="string"||!o[1]?o[0]:typeof o[1]!="object"?e(o[0].slice(0,o[1]),o):Object.prototype.hasOwnProperty.call(o[1],"words")&&o[1].words?e(o[0].split(" ").splice(0,o[1].words).join(" "),o):Object.prototype.hasOwnProperty.call(o[1],"characters")&&o[1].characters?e(o[0].slice(0,o[1].characters),o):o[0]})}function L(n){n.magic("dbg",e=>function(...o){let r=o.map(i=>n.raw(i));console.log(...r)})}function x(n){let e=n.reactive({screensize:window.innerWidth}),o={xs:0,sm:640,md:768,lg:1024,xl:1280,"2xl":1536},r=window.AlpineMagicHelpersConfig&&window.AlpineMagicHelpersConfig.breakpoints?window.AlpineMagicHelpersConfig.breakpoints:o,i;window.addEventListener("resize",()=>{clearTimeout(i),i=setTimeout(()=>{e.screensize=window.innerWidth},150)}),n.magic("screen",f=>u=>{let c=e.screensize;if(Number.isInteger(u))return u<=c;if(r[u]===void 0)throw Error("Undefined $screen property: "+u+". Supported properties: "+Object.keys(r).join(", "));return r[u]<=c})}function P(n){n.magic("interval",()=>function(...e){if(typeof e[0]!="function")return e[0];let o=e[1],r=0,i=!1;typeof e[1]=="object"&&(Object.prototype.hasOwnProperty.call(e[1],"timer")&&(o=e[1].timer),Object.prototype.hasOwnProperty.call(e[1],"delay")&&(r=e[1].delay),Object.prototype.hasOwnProperty.call(e[1],"forceInterval")&&(i=e[1].forceInterval));let f=null,u=!0,c=()=>{let g=u?o+r:o;u=!1,f=setTimeout(()=>{e[0].call(this),i?c():requestAnimationFrame(c)},g)};n.effect(()=>{this.autoIntervalTest==null||this.autoIntervalTest?i?c():requestAnimationFrame(c):clearTimeout(f)})})}function C(n){j(n),X(n),B(n),L(n),x(n),P(n)}document.addEventListener("alpine:initializing",()=>{C(window.Alpine)});})(); diff --git a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/focus@3.x.x/dist/cdn.min.js b/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/focus@3.x.x/dist/cdn.min.js deleted file mode 100644 index 5a2d18be..00000000 --- a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/focus@3.x.x/dist/cdn.min.js +++ /dev/null @@ -1,15 +0,0 @@ -(()=>{var _=["input","select","textarea","a[href]","button","[tabindex]:not(slot)","audio[controls]","video[controls]",'[contenteditable]:not([contenteditable="false"])',"details>summary:first-of-type","details"],k=_.join(","),K=typeof Element>"u",N=K?function(){}:Element.prototype.matches||Element.prototype.msMatchesSelector||Element.prototype.webkitMatchesSelector,B=!K&&Element.prototype.getRootNode?function(i){return i.getRootNode()}:function(i){return i.ownerDocument},V=function(e,t,a){var n=Array.prototype.slice.apply(e.querySelectorAll(k));return t&&N.call(e,k)&&n.unshift(e),n=n.filter(a),n},$=function i(e,t,a){for(var n=[],r=Array.from(e);r.length;){var s=r.shift();if(s.tagName==="SLOT"){var l=s.assignedElements(),m=l.length?l:s.children,p=i(m,!0,a);a.flatten?n.push.apply(n,p):n.push({scope:s,candidates:p})}else{var v=N.call(s,k);v&&a.filter(s)&&(t||!e.includes(s))&&n.push(s);var h=s.shadowRoot||typeof a.getShadowRoot=="function"&&a.getShadowRoot(s),y=!a.shadowRootFilter||a.shadowRootFilter(s);if(h&&y){var w=i(h===!0?s.children:h.children,!0,a);a.flatten?n.push.apply(n,w):n.push({scope:s,candidates:w})}else r.unshift.apply(r,s.children)}}return n},Y=function(e,t){return e.tabIndex<0&&(t||/^(AUDIO|VIDEO|DETAILS)$/.test(e.tagName)||e.isContentEditable)&&isNaN(parseInt(e.getAttribute("tabindex"),10))?0:e.tabIndex},se=function(e,t){return e.tabIndex===t.tabIndex?e.documentOrder-t.documentOrder:e.tabIndex-t.tabIndex},Z=function(e){return e.tagName==="INPUT"},ce=function(e){return Z(e)&&e.type==="hidden"},le=function(e){var t=e.tagName==="DETAILS"&&Array.prototype.slice.apply(e.children).some(function(a){return a.tagName==="SUMMARY"});return t},fe=function(e,t){for(var a=0;asummary:first-of-type"),s=r?e.parentElement:e;if(N.call(s,"details:not([open]) *"))return!0;var l=B(e).host,m=l?.ownerDocument.contains(l)||e.ownerDocument.contains(e);if(!a||a==="full"){if(typeof n=="function"){for(var p=e;e;){var v=e.parentElement,h=B(e);if(v&&!v.shadowRoot&&n(v)===!0)return W(e);e.assignedSlot?e=e.assignedSlot:!v&&h!==e.ownerDocument?e=h.host:e=v}e=p}if(m)return!e.getClientRects().length}else if(a==="non-zero-area")return W(e);return!1},pe=function(e){if(/^(INPUT|BUTTON|SELECT|TEXTAREA)$/.test(e.tagName))for(var t=e.parentElement;t;){if(t.tagName==="FIELDSET"&&t.disabled){for(var a=0;a=0)},me=function i(e){var t=[],a=[];return e.forEach(function(n,r){var s=!!n.scope,l=s?n.scope:n,m=Y(l,s),p=s?i(n.candidates):l;m===0?s?t.push.apply(t,p):t.push(l):a.push({documentOrder:r,tabIndex:m,item:n,isScope:s,content:p})}),a.sort(se).reduce(function(n,r){return r.isScope?n.push.apply(n,r.content):n.push(r.content),n},[]).concat(t)},z=function(e,t){t=t||{};var a;return t.getShadowRoot?a=$([e],t.includeContainer,{filter:G.bind(null,t),flatten:!1,getShadowRoot:t.getShadowRoot,shadowRootFilter:ge}):a=V(e,t.includeContainer,G.bind(null,t)),me(a)},x=function(e,t){t=t||{};var a;return t.getShadowRoot?a=$([e],t.includeContainer,{filter:I.bind(null,t),flatten:!0,getShadowRoot:t.getShadowRoot}):a=V(e,t.includeContainer,I.bind(null,t)),a},A=function(e,t){if(t=t||{},!e)throw new Error("No node provided");return N.call(e,k)===!1?!1:G(t,e)},ye=_.concat("iframe").join(","),R=function(e,t){if(t=t||{},!e)throw new Error("No node provided");return N.call(e,ye)===!1?!1:I(t,e)};function Q(i,e){var t=Object.keys(i);if(Object.getOwnPropertySymbols){var a=Object.getOwnPropertySymbols(i);e&&(a=a.filter(function(n){return Object.getOwnPropertyDescriptor(i,n).enumerable})),t.push.apply(t,a)}return t}function X(i){for(var e=1;e0){var a=i[i.length-1];a!==t&&a.pause()}var n=i.indexOf(t);n===-1||i.splice(n,1),i.push(t)},deactivateTrap:function(t){var a=i.indexOf(t);a!==-1&&i.splice(a,1),i.length>0&&i[i.length-1].unpause()}}}(),Te=function(e){return e.tagName&&e.tagName.toLowerCase()==="input"&&typeof e.select=="function"},Fe=function(e){return e.key==="Escape"||e.key==="Esc"||e.keyCode===27},Se=function(e){return e.key==="Tab"||e.keyCode===9},ee=function(e){return setTimeout(e,0)},te=function(e,t){var a=-1;return e.every(function(n,r){return t(n)?(a=r,!1):!0}),a},O=function(e){for(var t=arguments.length,a=new Array(t>1?t-1:0),n=1;n1?c-1:0),f=1;f=0)o=a.activeElement;else{var u=r.tabbableGroups[0],c=u&&u.firstTabbableNode;o=c||p("fallbackFocus")}if(!o)throw new Error("Your focus-trap needs to have at least one focusable element");return o},h=function(){if(r.containerGroups=r.containers.map(function(o){var u=z(o,n.tabbableOptions),c=x(o,n.tabbableOptions);return{container:o,tabbableNodes:u,focusableNodes:c,firstTabbableNode:u.length>0?u[0]:null,lastTabbableNode:u.length>0?u[u.length-1]:null,nextTabbableNode:function(f){var g=arguments.length>1&&arguments[1]!==void 0?arguments[1]:!0,F=c.findIndex(function(E){return E===f});if(!(F<0))return g?c.slice(F+1).find(function(E){return A(E,n.tabbableOptions)}):c.slice(0,F).reverse().find(function(E){return A(E,n.tabbableOptions)})}}}),r.tabbableGroups=r.containerGroups.filter(function(o){return o.tabbableNodes.length>0}),r.tabbableGroups.length<=0&&!p("fallbackFocus"))throw new Error("Your focus-trap must have at least one container with at least one tabbable node in it at all times")},y=function d(o){if(o!==!1&&o!==a.activeElement){if(!o||!o.focus){d(v());return}o.focus({preventScroll:!!n.preventScroll}),r.mostRecentlyFocusedNode=o,Te(o)&&o.select()}},w=function(o){var u=p("setReturnFocus",o);return u||(u===!1?!1:o)},S=function(o){var u=L(o);if(!(m(u)>=0)){if(O(n.clickOutsideDeactivates,o)){s.deactivate({returnFocus:n.returnFocusOnDeactivate&&!R(u,n.tabbableOptions)});return}O(n.allowOutsideClick,o)||o.preventDefault()}},D=function(o){var u=L(o),c=m(u)>=0;c||u instanceof Document?c&&(r.mostRecentlyFocusedNode=u):(o.stopImmediatePropagation(),y(r.mostRecentlyFocusedNode||v()))},T=function(o){var u=L(o);h();var c=null;if(r.tabbableGroups.length>0){var b=m(u),f=b>=0?r.containerGroups[b]:void 0;if(b<0)o.shiftKey?c=r.tabbableGroups[r.tabbableGroups.length-1].lastTabbableNode:c=r.tabbableGroups[0].firstTabbableNode;else if(o.shiftKey){var g=te(r.tabbableGroups,function(P){var j=P.firstTabbableNode;return u===j});if(g<0&&(f.container===u||R(u,n.tabbableOptions)&&!A(u,n.tabbableOptions)&&!f.nextTabbableNode(u,!1))&&(g=b),g>=0){var F=g===0?r.tabbableGroups.length-1:g-1,E=r.tabbableGroups[F];c=E.lastTabbableNode}}else{var C=te(r.tabbableGroups,function(P){var j=P.lastTabbableNode;return u===j});if(C<0&&(f.container===u||R(u,n.tabbableOptions)&&!A(u,n.tabbableOptions)&&!f.nextTabbableNode(u))&&(C=b),C>=0){var oe=C===r.tabbableGroups.length-1?0:C+1,ue=r.tabbableGroups[oe];c=ue.firstTabbableNode}}}else c=p("fallbackFocus");c&&(o.preventDefault(),y(c))},M=function(o){if(Fe(o)&&O(n.escapeDeactivates,o)!==!1){o.preventDefault(),s.deactivate();return}if(Se(o)){T(o);return}},q=function(o){var u=L(o);m(u)>=0||O(n.clickOutsideDeactivates,o)||O(n.allowOutsideClick,o)||(o.preventDefault(),o.stopImmediatePropagation())},H=function(){if(r.active)return J.activateTrap(s),r.delayInitialFocusTimer=n.delayInitialFocus?ee(function(){y(v())}):y(v()),a.addEventListener("focusin",D,!0),a.addEventListener("mousedown",S,{capture:!0,passive:!1}),a.addEventListener("touchstart",S,{capture:!0,passive:!1}),a.addEventListener("click",q,{capture:!0,passive:!1}),a.addEventListener("keydown",M,{capture:!0,passive:!1}),s},U=function(){if(r.active)return a.removeEventListener("focusin",D,!0),a.removeEventListener("mousedown",S,!0),a.removeEventListener("touchstart",S,!0),a.removeEventListener("click",q,!0),a.removeEventListener("keydown",M,!0),s};return s={get active(){return r.active},get paused(){return r.paused},activate:function(o){if(r.active)return this;var u=l(o,"onActivate"),c=l(o,"onPostActivate"),b=l(o,"checkCanFocusTrap");b||h(),r.active=!0,r.paused=!1,r.nodeFocusedBeforeActivation=a.activeElement,u&&u();var f=function(){b&&h(),H(),c&&c()};return b?(b(r.containers.concat()).then(f,f),this):(f(),this)},deactivate:function(o){if(!r.active)return this;var u=X({onDeactivate:n.onDeactivate,onPostDeactivate:n.onPostDeactivate,checkCanReturnFocus:n.checkCanReturnFocus},o);clearTimeout(r.delayInitialFocusTimer),r.delayInitialFocusTimer=void 0,U(),r.active=!1,r.paused=!1,J.deactivateTrap(s);var c=l(u,"onDeactivate"),b=l(u,"onPostDeactivate"),f=l(u,"checkCanReturnFocus"),g=l(u,"returnFocus","returnFocusOnDeactivate");c&&c();var F=function(){ee(function(){g&&y(w(r.nodeFocusedBeforeActivation)),b&&b()})};return g&&f?(f(w(r.nodeFocusedBeforeActivation)).then(F,F),this):(F(),this)},pause:function(){return r.paused||!r.active?this:(r.paused=!0,U(),this)},unpause:function(){return!r.paused||!r.active?this:(r.paused=!1,h(),H(),this)},updateContainerElements:function(o){var u=[].concat(o).filter(Boolean);return r.containers=u.map(function(c){return typeof c=="string"?a.querySelector(c):c}),r.active&&h(),this}},s.updateContainerElements(e),s};function ne(i){let e,t;window.addEventListener("focusin",()=>{e=t,t=document.activeElement}),i.magic("focus",a=>{let n=a;return{__noscroll:!1,__wrapAround:!1,within(r){return n=r,this},withoutScrolling(){return this.__noscroll=!0,this},noscroll(){return this.__noscroll=!0,this},withWrapAround(){return this.__wrapAround=!0,this},wrap(){return this.withWrapAround()},focusable(r){return R(r)},previouslyFocused(){return e},lastFocused(){return e},focused(){return t},focusables(){return Array.isArray(n)?n:x(n,{displayCheck:"none"})},all(){return this.focusables()},isFirst(r){let s=this.all();return s[0]&&s[0].isSameNode(r)},isLast(r){let s=this.all();return s.length&&s.slice(-1)[0].isSameNode(r)},getFirst(){return this.all()[0]},getLast(){return this.all().slice(-1)[0]},getNext(){let r=this.all(),s=document.activeElement;if(r.indexOf(s)!==-1)return this.__wrapAround&&r.indexOf(s)===r.length-1?r[0]:r[r.indexOf(s)+1]},getPrevious(){let r=this.all(),s=document.activeElement;if(r.indexOf(s)!==-1)return this.__wrapAround&&r.indexOf(s)===0?r.slice(-1)[0]:r[r.indexOf(s)-1]},first(){this.focus(this.getFirst())},last(){this.focus(this.getLast())},next(){this.focus(this.getNext())},previous(){this.focus(this.getPrevious())},prev(){return this.previous()},focus(r){r&&setTimeout(()=>{r.hasAttribute("tabindex")||r.setAttribute("tabindex","0"),r.focus({preventScroll:this.__noscroll})})}}}),i.directive("trap",i.skipDuringClone((a,{expression:n,modifiers:r},{effect:s,evaluateLater:l,cleanup:m})=>{let p=l(n),v=!1,h={escapeDeactivates:!1,allowOutsideClick:!0,fallbackFocus:()=>a};if(r.includes("noautofocus"))h.initialFocus=!1;else{let T=a.querySelector("[autofocus]");T&&(h.initialFocus=T)}let y=re(a,h),w=()=>{},S=()=>{},D=()=>{w(),w=()=>{},S(),S=()=>{},y.deactivate({returnFocus:!r.includes("noreturn")})};s(()=>p(T=>{v!==T&&(T&&!v&&(r.includes("noscroll")&&(S=Ee()),r.includes("inert")&&(w=ae(a)),setTimeout(()=>{y.activate()},15)),!T&&v&&D(),v=!!T)})),m(D)},(a,{expression:n,modifiers:r},{evaluate:s})=>{r.includes("inert")&&s(n)&&ae(a)}))}function ae(i){let e=[];return ie(i,t=>{let a=t.hasAttribute("aria-hidden");t.setAttribute("aria-hidden","true"),e.push(()=>a||t.removeAttribute("aria-hidden"))}),()=>{for(;e.length;)e.pop()()}}function ie(i,e){i.isSameNode(document.body)||!i.parentNode||Array.from(i.parentNode.children).forEach(t=>{t.isSameNode(i)?ie(i.parentNode,e):e(t)})}function Ee(){let i=document.documentElement.style.overflow,e=document.documentElement.style.paddingRight,t=window.innerWidth-document.documentElement.clientWidth;return document.documentElement.style.overflow="hidden",document.documentElement.style.paddingRight=`${t}px`,()=>{document.documentElement.style.overflow=i,document.documentElement.style.paddingRight=e}}document.addEventListener("alpine:init",()=>{window.Alpine.plugin(ne)});})(); -/*! Bundled license information: - -tabbable/dist/index.esm.js: - (*! - * tabbable 5.3.3 - * @license MIT, https://github.com/focus-trap/tabbable/blob/master/LICENSE - *) - -focus-trap/dist/focus-trap.esm.js: - (*! - * focus-trap 6.9.4 - * @license MIT, https://github.com/focus-trap/focus-trap/blob/master/LICENSE - *) -*/ diff --git a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/intersect@3.x.x/dist/cdn.min.js b/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/intersect@3.x.x/dist/cdn.min.js deleted file mode 100644 index 2342257f..00000000 --- a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/@alpinejs/intersect@3.x.x/dist/cdn.min.js +++ /dev/null @@ -1 +0,0 @@ -(()=>{function o(e){e.directive("intersect",e.skipDuringClone((t,{value:i,expression:l,modifiers:n},{evaluateLater:r,cleanup:c})=>{let s=r(l),a={rootMargin:x(n),threshold:f(n)},u=new IntersectionObserver(d=>{d.forEach(h=>{h.isIntersecting!==(i==="leave")&&(s(),n.includes("once")&&u.disconnect())})},a);u.observe(t),c(()=>{u.disconnect()})}))}function f(e){if(e.includes("full"))return .99;if(e.includes("half"))return .5;if(!e.includes("threshold"))return 0;let t=e[e.indexOf("threshold")+1];return t==="100"?1:t==="0"?0:Number(`.${t}`)}function p(e){let t=e.match(/^(-?[0-9]+)(px|%)?$/);return t?t[1]+(t[2]||"px"):void 0}function x(e){let t="margin",i="0px 0px 0px 0px",l=e.indexOf(t);if(l===-1)return i;let n=[];for(let r=1;r<5;r++)n.push(p(e[l+r]||""));return n=n.filter(r=>r!==void 0),n.length?n.join(" ").trim():i}document.addEventListener("alpine:init",()=>{window.Alpine.plugin(o)});})(); diff --git a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css b/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css deleted file mode 100644 index df4fbc05..00000000 --- a/tinygrad/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css +++ /dev/null @@ -1,11 +0,0 @@ -/*! -Pure v3.0.0 -Copyright 2013 Yahoo! -Licensed under the BSD License. -https://github.com/pure-css/pure/blob/master/LICENSE -*/ -/*! -normalize.css v | MIT License | https://necolas.github.io/normalize.css/ -Copyright (c) Nicolas Gallagher and Jonathan Neal -*/ -/*! normalize.css v8.0.1 | MIT License | github.com/necolas/normalize.css */html{line-height:1.15;-webkit-text-size-adjust:100%}body{margin:0}main{display:block}h1{font-size:2em;margin:.67em 0}hr{box-sizing:content-box;height:0;overflow:visible}pre{font-family:monospace,monospace;font-size:1em}a{background-color:transparent}abbr[title]{border-bottom:none;text-decoration:underline;-webkit-text-decoration:underline dotted;text-decoration:underline dotted}b,strong{font-weight:bolder}code,kbd,samp{font-family:monospace,monospace;font-size:1em}small{font-size:80%}sub,sup{font-size:75%;line-height:0;position:relative;vertical-align:baseline}sub{bottom:-.25em}sup{top:-.5em}img{border-style:none}button,input,optgroup,select,textarea{font-family:inherit;font-size:100%;line-height:1.15;margin:0}button,input{overflow:visible}button,select{text-transform:none}[type=button],[type=reset],[type=submit],button{-webkit-appearance:button}[type=button]::-moz-focus-inner,[type=reset]::-moz-focus-inner,[type=submit]::-moz-focus-inner,button::-moz-focus-inner{border-style:none;padding:0}[type=button]:-moz-focusring,[type=reset]:-moz-focusring,[type=submit]:-moz-focusring,button:-moz-focusring{outline:1px dotted ButtonText}fieldset{padding:.35em .75em .625em}legend{box-sizing:border-box;color:inherit;display:table;max-width:100%;padding:0;white-space:normal}progress{vertical-align:baseline}textarea{overflow:auto}[type=checkbox],[type=radio]{box-sizing:border-box;padding:0}[type=number]::-webkit-inner-spin-button,[type=number]::-webkit-outer-spin-button{height:auto}[type=search]{-webkit-appearance:textfield;outline-offset:-2px}[type=search]::-webkit-search-decoration{-webkit-appearance:none}::-webkit-file-upload-button{-webkit-appearance:button;font:inherit}details{display:block}summary{display:list-item}template{display:none}[hidden]{display:none}html{font-family:sans-serif}.hidden,[hidden]{display:none!important}.pure-img{max-width:100%;height:auto;display:block} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/css/all.min.css b/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/css/all.min.css deleted file mode 100644 index 45072b30..00000000 --- a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/css/all.min.css +++ /dev/null @@ -1,9 +0,0 @@ -/*! - * Font Awesome Free 6.5.2 by @fontawesome - https://fontawesome.com - * License - https://fontawesome.com/license/free (Icons: CC BY 4.0, Fonts: SIL OFL 1.1, Code: MIT License) - * Copyright 2024 Fonticons, Inc. - */ -.fa{font-family:var(--fa-style-family,"Font Awesome 6 Free");font-weight:var(--fa-style,900)}.fa,.fa-brands,.fa-classic,.fa-regular,.fa-sharp,.fa-solid,.fab,.far,.fas{-moz-osx-font-smoothing:grayscale;-webkit-font-smoothing:antialiased;display:var(--fa-display,inline-block);font-style:normal;font-variant:normal;line-height:1;text-rendering:auto}.fa-classic,.fa-regular,.fa-solid,.far,.fas{font-family:"Font Awesome 6 Free"}.fa-brands,.fab{font-family:"Font Awesome 6 Brands"}.fa-1x{font-size:1em}.fa-2x{font-size:2em}.fa-3x{font-size:3em}.fa-4x{font-size:4em}.fa-5x{font-size:5em}.fa-6x{font-size:6em}.fa-7x{font-size:7em}.fa-8x{font-size:8em}.fa-9x{font-size:9em}.fa-10x{font-size:10em}.fa-2xs{font-size:.625em;line-height:.1em;vertical-align:.225em}.fa-xs{font-size:.75em;line-height:.08333em;vertical-align:.125em}.fa-sm{font-size:.875em;line-height:.07143em;vertical-align:.05357em}.fa-lg{font-size:1.25em;line-height:.05em;vertical-align:-.075em}.fa-xl{font-size:1.5em;line-height:.04167em;vertical-align:-.125em}.fa-2xl{font-size:2em;line-height:.03125em;vertical-align:-.1875em}.fa-fw{text-align:center;width:1.25em}.fa-ul{list-style-type:none;margin-left:var(--fa-li-margin,2.5em);padding-left:0}.fa-ul>li{position:relative}.fa-li{left:calc(var(--fa-li-width, 2em)*-1);position:absolute;text-align:center;width:var(--fa-li-width,2em);line-height:inherit}.fa-border{border-radius:var(--fa-border-radius,.1em);border:var(--fa-border-width,.08em) var(--fa-border-style,solid) var(--fa-border-color,#eee);padding:var(--fa-border-padding,.2em .25em .15em)}.fa-pull-left{float:left;margin-right:var(--fa-pull-margin,.3em)}.fa-pull-right{float:right;margin-left:var(--fa-pull-margin,.3em)}.fa-beat{-webkit-animation-name:fa-beat;animation-name:fa-beat;-webkit-animation-delay:var(--fa-animation-delay,0s);animation-delay:var(--fa-animation-delay,0s);-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal);-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,ease-in-out);animation-timing-function:var(--fa-animation-timing,ease-in-out)}.fa-bounce{-webkit-animation-name:fa-bounce;animation-name:fa-bounce;-webkit-animation-delay:var(--fa-animation-delay,0s);animation-delay:var(--fa-animation-delay,0s);-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal);-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,cubic-bezier(.28,.84,.42,1));animation-timing-function:var(--fa-animation-timing,cubic-bezier(.28,.84,.42,1))}.fa-fade{-webkit-animation-name:fa-fade;animation-name:fa-fade;-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,cubic-bezier(.4,0,.6,1));animation-timing-function:var(--fa-animation-timing,cubic-bezier(.4,0,.6,1))}.fa-beat-fade,.fa-fade{-webkit-animation-delay:var(--fa-animation-delay,0s);animation-delay:var(--fa-animation-delay,0s);-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal);-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s)}.fa-beat-fade{-webkit-animation-name:fa-beat-fade;animation-name:fa-beat-fade;-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,cubic-bezier(.4,0,.6,1));animation-timing-function:var(--fa-animation-timing,cubic-bezier(.4,0,.6,1))}.fa-flip{-webkit-animation-name:fa-flip;animation-name:fa-flip;-webkit-animation-delay:var(--fa-animation-delay,0s);animation-delay:var(--fa-animation-delay,0s);-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal);-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,ease-in-out);animation-timing-function:var(--fa-animation-timing,ease-in-out)}.fa-shake{-webkit-animation-name:fa-shake;animation-name:fa-shake;-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,linear);animation-timing-function:var(--fa-animation-timing,linear)}.fa-shake,.fa-spin{-webkit-animation-delay:var(--fa-animation-delay,0s);animation-delay:var(--fa-animation-delay,0s);-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal)}.fa-spin{-webkit-animation-name:fa-spin;animation-name:fa-spin;-webkit-animation-duration:var(--fa-animation-duration,2s);animation-duration:var(--fa-animation-duration,2s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,linear);animation-timing-function:var(--fa-animation-timing,linear)}.fa-spin-reverse{--fa-animation-direction:reverse}.fa-pulse,.fa-spin-pulse{-webkit-animation-name:fa-spin;animation-name:fa-spin;-webkit-animation-direction:var(--fa-animation-direction,normal);animation-direction:var(--fa-animation-direction,normal);-webkit-animation-duration:var(--fa-animation-duration,1s);animation-duration:var(--fa-animation-duration,1s);-webkit-animation-iteration-count:var(--fa-animation-iteration-count,infinite);animation-iteration-count:var(--fa-animation-iteration-count,infinite);-webkit-animation-timing-function:var(--fa-animation-timing,steps(8));animation-timing-function:var(--fa-animation-timing,steps(8))}@media (prefers-reduced-motion:reduce){.fa-beat,.fa-beat-fade,.fa-bounce,.fa-fade,.fa-flip,.fa-pulse,.fa-shake,.fa-spin,.fa-spin-pulse{-webkit-animation-delay:-1ms;animation-delay:-1ms;-webkit-animation-duration:1ms;animation-duration:1ms;-webkit-animation-iteration-count:1;animation-iteration-count:1;-webkit-transition-delay:0s;transition-delay:0s;-webkit-transition-duration:0s;transition-duration:0s}}@-webkit-keyframes fa-beat{0%,90%{-webkit-transform:scale(1);transform:scale(1)}45%{-webkit-transform:scale(var(--fa-beat-scale,1.25));transform:scale(var(--fa-beat-scale,1.25))}}@keyframes fa-beat{0%,90%{-webkit-transform:scale(1);transform:scale(1)}45%{-webkit-transform:scale(var(--fa-beat-scale,1.25));transform:scale(var(--fa-beat-scale,1.25))}}@-webkit-keyframes fa-bounce{0%{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}10%{-webkit-transform:scale(var(--fa-bounce-start-scale-x,1.1),var(--fa-bounce-start-scale-y,.9)) translateY(0);transform:scale(var(--fa-bounce-start-scale-x,1.1),var(--fa-bounce-start-scale-y,.9)) translateY(0)}30%{-webkit-transform:scale(var(--fa-bounce-jump-scale-x,.9),var(--fa-bounce-jump-scale-y,1.1)) translateY(var(--fa-bounce-height,-.5em));transform:scale(var(--fa-bounce-jump-scale-x,.9),var(--fa-bounce-jump-scale-y,1.1)) translateY(var(--fa-bounce-height,-.5em))}50%{-webkit-transform:scale(var(--fa-bounce-land-scale-x,1.05),var(--fa-bounce-land-scale-y,.95)) translateY(0);transform:scale(var(--fa-bounce-land-scale-x,1.05),var(--fa-bounce-land-scale-y,.95)) translateY(0)}57%{-webkit-transform:scale(1) translateY(var(--fa-bounce-rebound,-.125em));transform:scale(1) translateY(var(--fa-bounce-rebound,-.125em))}64%{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}to{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}}@keyframes fa-bounce{0%{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}10%{-webkit-transform:scale(var(--fa-bounce-start-scale-x,1.1),var(--fa-bounce-start-scale-y,.9)) translateY(0);transform:scale(var(--fa-bounce-start-scale-x,1.1),var(--fa-bounce-start-scale-y,.9)) translateY(0)}30%{-webkit-transform:scale(var(--fa-bounce-jump-scale-x,.9),var(--fa-bounce-jump-scale-y,1.1)) translateY(var(--fa-bounce-height,-.5em));transform:scale(var(--fa-bounce-jump-scale-x,.9),var(--fa-bounce-jump-scale-y,1.1)) translateY(var(--fa-bounce-height,-.5em))}50%{-webkit-transform:scale(var(--fa-bounce-land-scale-x,1.05),var(--fa-bounce-land-scale-y,.95)) translateY(0);transform:scale(var(--fa-bounce-land-scale-x,1.05),var(--fa-bounce-land-scale-y,.95)) translateY(0)}57%{-webkit-transform:scale(1) translateY(var(--fa-bounce-rebound,-.125em));transform:scale(1) translateY(var(--fa-bounce-rebound,-.125em))}64%{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}to{-webkit-transform:scale(1) translateY(0);transform:scale(1) translateY(0)}}@-webkit-keyframes fa-fade{50%{opacity:var(--fa-fade-opacity,.4)}}@keyframes fa-fade{50%{opacity:var(--fa-fade-opacity,.4)}}@-webkit-keyframes fa-beat-fade{0%,to{opacity:var(--fa-beat-fade-opacity,.4);-webkit-transform:scale(1);transform:scale(1)}50%{opacity:1;-webkit-transform:scale(var(--fa-beat-fade-scale,1.125));transform:scale(var(--fa-beat-fade-scale,1.125))}}@keyframes fa-beat-fade{0%,to{opacity:var(--fa-beat-fade-opacity,.4);-webkit-transform:scale(1);transform:scale(1)}50%{opacity:1;-webkit-transform:scale(var(--fa-beat-fade-scale,1.125));transform:scale(var(--fa-beat-fade-scale,1.125))}}@-webkit-keyframes fa-flip{50%{-webkit-transform:rotate3d(var(--fa-flip-x,0),var(--fa-flip-y,1),var(--fa-flip-z,0),var(--fa-flip-angle,-180deg));transform:rotate3d(var(--fa-flip-x,0),var(--fa-flip-y,1),var(--fa-flip-z,0),var(--fa-flip-angle,-180deg))}}@keyframes fa-flip{50%{-webkit-transform:rotate3d(var(--fa-flip-x,0),var(--fa-flip-y,1),var(--fa-flip-z,0),var(--fa-flip-angle,-180deg));transform:rotate3d(var(--fa-flip-x,0),var(--fa-flip-y,1),var(--fa-flip-z,0),var(--fa-flip-angle,-180deg))}}@-webkit-keyframes fa-shake{0%{-webkit-transform:rotate(-15deg);transform:rotate(-15deg)}4%{-webkit-transform:rotate(15deg);transform:rotate(15deg)}8%,24%{-webkit-transform:rotate(-18deg);transform:rotate(-18deg)}12%,28%{-webkit-transform:rotate(18deg);transform:rotate(18deg)}16%{-webkit-transform:rotate(-22deg);transform:rotate(-22deg)}20%{-webkit-transform:rotate(22deg);transform:rotate(22deg)}32%{-webkit-transform:rotate(-12deg);transform:rotate(-12deg)}36%{-webkit-transform:rotate(12deg);transform:rotate(12deg)}40%,to{-webkit-transform:rotate(0deg);transform:rotate(0deg)}}@keyframes fa-shake{0%{-webkit-transform:rotate(-15deg);transform:rotate(-15deg)}4%{-webkit-transform:rotate(15deg);transform:rotate(15deg)}8%,24%{-webkit-transform:rotate(-18deg);transform:rotate(-18deg)}12%,28%{-webkit-transform:rotate(18deg);transform:rotate(18deg)}16%{-webkit-transform:rotate(-22deg);transform:rotate(-22deg)}20%{-webkit-transform:rotate(22deg);transform:rotate(22deg)}32%{-webkit-transform:rotate(-12deg);transform:rotate(-12deg)}36%{-webkit-transform:rotate(12deg);transform:rotate(12deg)}40%,to{-webkit-transform:rotate(0deg);transform:rotate(0deg)}}@-webkit-keyframes fa-spin{0%{-webkit-transform:rotate(0deg);transform:rotate(0deg)}to{-webkit-transform:rotate(1turn);transform:rotate(1turn)}}@keyframes fa-spin{0%{-webkit-transform:rotate(0deg);transform:rotate(0deg)}to{-webkit-transform:rotate(1turn);transform:rotate(1turn)}}.fa-rotate-90{-webkit-transform:rotate(90deg);transform:rotate(90deg)}.fa-rotate-180{-webkit-transform:rotate(180deg);transform:rotate(180deg)}.fa-rotate-270{-webkit-transform:rotate(270deg);transform:rotate(270deg)}.fa-flip-horizontal{-webkit-transform:scaleX(-1);transform:scaleX(-1)}.fa-flip-vertical{-webkit-transform:scaleY(-1);transform:scaleY(-1)}.fa-flip-both,.fa-flip-horizontal.fa-flip-vertical{-webkit-transform:scale(-1);transform:scale(-1)}.fa-rotate-by{-webkit-transform:rotate(var(--fa-rotate-angle,0));transform:rotate(var(--fa-rotate-angle,0))}.fa-stack{display:inline-block;height:2em;line-height:2em;position:relative;vertical-align:middle;width:2.5em}.fa-stack-1x,.fa-stack-2x{left:0;position:absolute;text-align:center;width:100%;z-index:var(--fa-stack-z-index,auto)}.fa-stack-1x{line-height:inherit}.fa-stack-2x{font-size:2em}.fa-inverse{color:var(--fa-inverse,#fff)} - -.fa-0:before{content:"\30"}.fa-1:before{content:"\31"}.fa-2:before{content:"\32"}.fa-3:before{content:"\33"}.fa-4:before{content:"\34"}.fa-5:before{content:"\35"}.fa-6:before{content:"\36"}.fa-7:before{content:"\37"}.fa-8:before{content:"\38"}.fa-9:before{content:"\39"}.fa-fill-drip:before{content:"\f576"}.fa-arrows-to-circle:before{content:"\e4bd"}.fa-chevron-circle-right:before,.fa-circle-chevron-right:before{content:"\f138"}.fa-at:before{content:"\40"}.fa-trash-alt:before,.fa-trash-can:before{content:"\f2ed"}.fa-text-height:before{content:"\f034"}.fa-user-times:before,.fa-user-xmark:before{content:"\f235"}.fa-stethoscope:before{content:"\f0f1"}.fa-comment-alt:before,.fa-message:before{content:"\f27a"}.fa-info:before{content:"\f129"}.fa-compress-alt:before,.fa-down-left-and-up-right-to-center:before{content:"\f422"}.fa-explosion:before{content:"\e4e9"}.fa-file-alt:before,.fa-file-lines:before,.fa-file-text:before{content:"\f15c"}.fa-wave-square:before{content:"\f83e"}.fa-ring:before{content:"\f70b"}.fa-building-un:before{content:"\e4d9"}.fa-dice-three:before{content:"\f527"}.fa-calendar-alt:before,.fa-calendar-days:before{content:"\f073"}.fa-anchor-circle-check:before{content:"\e4aa"}.fa-building-circle-arrow-right:before{content:"\e4d1"}.fa-volleyball-ball:before,.fa-volleyball:before{content:"\f45f"}.fa-arrows-up-to-line:before{content:"\e4c2"}.fa-sort-desc:before,.fa-sort-down:before{content:"\f0dd"}.fa-circle-minus:before,.fa-minus-circle:before{content:"\f056"}.fa-door-open:before{content:"\f52b"}.fa-right-from-bracket:before,.fa-sign-out-alt:before{content:"\f2f5"}.fa-atom:before{content:"\f5d2"}.fa-soap:before{content:"\e06e"}.fa-heart-music-camera-bolt:before,.fa-icons:before{content:"\f86d"}.fa-microphone-alt-slash:before,.fa-microphone-lines-slash:before{content:"\f539"}.fa-bridge-circle-check:before{content:"\e4c9"}.fa-pump-medical:before{content:"\e06a"}.fa-fingerprint:before{content:"\f577"}.fa-hand-point-right:before{content:"\f0a4"}.fa-magnifying-glass-location:before,.fa-search-location:before{content:"\f689"}.fa-forward-step:before,.fa-step-forward:before{content:"\f051"}.fa-face-smile-beam:before,.fa-smile-beam:before{content:"\f5b8"}.fa-flag-checkered:before{content:"\f11e"}.fa-football-ball:before,.fa-football:before{content:"\f44e"}.fa-school-circle-exclamation:before{content:"\e56c"}.fa-crop:before{content:"\f125"}.fa-angle-double-down:before,.fa-angles-down:before{content:"\f103"}.fa-users-rectangle:before{content:"\e594"}.fa-people-roof:before{content:"\e537"}.fa-people-line:before{content:"\e534"}.fa-beer-mug-empty:before,.fa-beer:before{content:"\f0fc"}.fa-diagram-predecessor:before{content:"\e477"}.fa-arrow-up-long:before,.fa-long-arrow-up:before{content:"\f176"}.fa-burn:before,.fa-fire-flame-simple:before{content:"\f46a"}.fa-male:before,.fa-person:before{content:"\f183"}.fa-laptop:before{content:"\f109"}.fa-file-csv:before{content:"\f6dd"}.fa-menorah:before{content:"\f676"}.fa-truck-plane:before{content:"\e58f"}.fa-record-vinyl:before{content:"\f8d9"}.fa-face-grin-stars:before,.fa-grin-stars:before{content:"\f587"}.fa-bong:before{content:"\f55c"}.fa-pastafarianism:before,.fa-spaghetti-monster-flying:before{content:"\f67b"}.fa-arrow-down-up-across-line:before{content:"\e4af"}.fa-spoon:before,.fa-utensil-spoon:before{content:"\f2e5"}.fa-jar-wheat:before{content:"\e517"}.fa-envelopes-bulk:before,.fa-mail-bulk:before{content:"\f674"}.fa-file-circle-exclamation:before{content:"\e4eb"}.fa-circle-h:before,.fa-hospital-symbol:before{content:"\f47e"}.fa-pager:before{content:"\f815"}.fa-address-book:before,.fa-contact-book:before{content:"\f2b9"}.fa-strikethrough:before{content:"\f0cc"}.fa-k:before{content:"\4b"}.fa-landmark-flag:before{content:"\e51c"}.fa-pencil-alt:before,.fa-pencil:before{content:"\f303"}.fa-backward:before{content:"\f04a"}.fa-caret-right:before{content:"\f0da"}.fa-comments:before{content:"\f086"}.fa-file-clipboard:before,.fa-paste:before{content:"\f0ea"}.fa-code-pull-request:before{content:"\e13c"}.fa-clipboard-list:before{content:"\f46d"}.fa-truck-loading:before,.fa-truck-ramp-box:before{content:"\f4de"}.fa-user-check:before{content:"\f4fc"}.fa-vial-virus:before{content:"\e597"}.fa-sheet-plastic:before{content:"\e571"}.fa-blog:before{content:"\f781"}.fa-user-ninja:before{content:"\f504"}.fa-person-arrow-up-from-line:before{content:"\e539"}.fa-scroll-torah:before,.fa-torah:before{content:"\f6a0"}.fa-broom-ball:before,.fa-quidditch-broom-ball:before,.fa-quidditch:before{content:"\f458"}.fa-toggle-off:before{content:"\f204"}.fa-archive:before,.fa-box-archive:before{content:"\f187"}.fa-person-drowning:before{content:"\e545"}.fa-arrow-down-9-1:before,.fa-sort-numeric-desc:before,.fa-sort-numeric-down-alt:before{content:"\f886"}.fa-face-grin-tongue-squint:before,.fa-grin-tongue-squint:before{content:"\f58a"}.fa-spray-can:before{content:"\f5bd"}.fa-truck-monster:before{content:"\f63b"}.fa-w:before{content:"\57"}.fa-earth-africa:before,.fa-globe-africa:before{content:"\f57c"}.fa-rainbow:before{content:"\f75b"}.fa-circle-notch:before{content:"\f1ce"}.fa-tablet-alt:before,.fa-tablet-screen-button:before{content:"\f3fa"}.fa-paw:before{content:"\f1b0"}.fa-cloud:before{content:"\f0c2"}.fa-trowel-bricks:before{content:"\e58a"}.fa-face-flushed:before,.fa-flushed:before{content:"\f579"}.fa-hospital-user:before{content:"\f80d"}.fa-tent-arrow-left-right:before{content:"\e57f"}.fa-gavel:before,.fa-legal:before{content:"\f0e3"}.fa-binoculars:before{content:"\f1e5"}.fa-microphone-slash:before{content:"\f131"}.fa-box-tissue:before{content:"\e05b"}.fa-motorcycle:before{content:"\f21c"}.fa-bell-concierge:before,.fa-concierge-bell:before{content:"\f562"}.fa-pen-ruler:before,.fa-pencil-ruler:before{content:"\f5ae"}.fa-people-arrows-left-right:before,.fa-people-arrows:before{content:"\e068"}.fa-mars-and-venus-burst:before{content:"\e523"}.fa-caret-square-right:before,.fa-square-caret-right:before{content:"\f152"}.fa-cut:before,.fa-scissors:before{content:"\f0c4"}.fa-sun-plant-wilt:before{content:"\e57a"}.fa-toilets-portable:before{content:"\e584"}.fa-hockey-puck:before{content:"\f453"}.fa-table:before{content:"\f0ce"}.fa-magnifying-glass-arrow-right:before{content:"\e521"}.fa-digital-tachograph:before,.fa-tachograph-digital:before{content:"\f566"}.fa-users-slash:before{content:"\e073"}.fa-clover:before{content:"\e139"}.fa-mail-reply:before,.fa-reply:before{content:"\f3e5"}.fa-star-and-crescent:before{content:"\f699"}.fa-house-fire:before{content:"\e50c"}.fa-minus-square:before,.fa-square-minus:before{content:"\f146"}.fa-helicopter:before{content:"\f533"}.fa-compass:before{content:"\f14e"}.fa-caret-square-down:before,.fa-square-caret-down:before{content:"\f150"}.fa-file-circle-question:before{content:"\e4ef"}.fa-laptop-code:before{content:"\f5fc"}.fa-swatchbook:before{content:"\f5c3"}.fa-prescription-bottle:before{content:"\f485"}.fa-bars:before,.fa-navicon:before{content:"\f0c9"}.fa-people-group:before{content:"\e533"}.fa-hourglass-3:before,.fa-hourglass-end:before{content:"\f253"}.fa-heart-broken:before,.fa-heart-crack:before{content:"\f7a9"}.fa-external-link-square-alt:before,.fa-square-up-right:before{content:"\f360"}.fa-face-kiss-beam:before,.fa-kiss-beam:before{content:"\f597"}.fa-film:before{content:"\f008"}.fa-ruler-horizontal:before{content:"\f547"}.fa-people-robbery:before{content:"\e536"}.fa-lightbulb:before{content:"\f0eb"}.fa-caret-left:before{content:"\f0d9"}.fa-circle-exclamation:before,.fa-exclamation-circle:before{content:"\f06a"}.fa-school-circle-xmark:before{content:"\e56d"}.fa-arrow-right-from-bracket:before,.fa-sign-out:before{content:"\f08b"}.fa-chevron-circle-down:before,.fa-circle-chevron-down:before{content:"\f13a"}.fa-unlock-alt:before,.fa-unlock-keyhole:before{content:"\f13e"}.fa-cloud-showers-heavy:before{content:"\f740"}.fa-headphones-alt:before,.fa-headphones-simple:before{content:"\f58f"}.fa-sitemap:before{content:"\f0e8"}.fa-circle-dollar-to-slot:before,.fa-donate:before{content:"\f4b9"}.fa-memory:before{content:"\f538"}.fa-road-spikes:before{content:"\e568"}.fa-fire-burner:before{content:"\e4f1"}.fa-flag:before{content:"\f024"}.fa-hanukiah:before{content:"\f6e6"}.fa-feather:before{content:"\f52d"}.fa-volume-down:before,.fa-volume-low:before{content:"\f027"}.fa-comment-slash:before{content:"\f4b3"}.fa-cloud-sun-rain:before{content:"\f743"}.fa-compress:before{content:"\f066"}.fa-wheat-alt:before,.fa-wheat-awn:before{content:"\e2cd"}.fa-ankh:before{content:"\f644"}.fa-hands-holding-child:before{content:"\e4fa"}.fa-asterisk:before{content:"\2a"}.fa-check-square:before,.fa-square-check:before{content:"\f14a"}.fa-peseta-sign:before{content:"\e221"}.fa-header:before,.fa-heading:before{content:"\f1dc"}.fa-ghost:before{content:"\f6e2"}.fa-list-squares:before,.fa-list:before{content:"\f03a"}.fa-phone-square-alt:before,.fa-square-phone-flip:before{content:"\f87b"}.fa-cart-plus:before{content:"\f217"}.fa-gamepad:before{content:"\f11b"}.fa-circle-dot:before,.fa-dot-circle:before{content:"\f192"}.fa-dizzy:before,.fa-face-dizzy:before{content:"\f567"}.fa-egg:before{content:"\f7fb"}.fa-house-medical-circle-xmark:before{content:"\e513"}.fa-campground:before{content:"\f6bb"}.fa-folder-plus:before{content:"\f65e"}.fa-futbol-ball:before,.fa-futbol:before,.fa-soccer-ball:before{content:"\f1e3"}.fa-paint-brush:before,.fa-paintbrush:before{content:"\f1fc"}.fa-lock:before{content:"\f023"}.fa-gas-pump:before{content:"\f52f"}.fa-hot-tub-person:before,.fa-hot-tub:before{content:"\f593"}.fa-map-location:before,.fa-map-marked:before{content:"\f59f"}.fa-house-flood-water:before{content:"\e50e"}.fa-tree:before{content:"\f1bb"}.fa-bridge-lock:before{content:"\e4cc"}.fa-sack-dollar:before{content:"\f81d"}.fa-edit:before,.fa-pen-to-square:before{content:"\f044"}.fa-car-side:before{content:"\f5e4"}.fa-share-alt:before,.fa-share-nodes:before{content:"\f1e0"}.fa-heart-circle-minus:before{content:"\e4ff"}.fa-hourglass-2:before,.fa-hourglass-half:before{content:"\f252"}.fa-microscope:before{content:"\f610"}.fa-sink:before{content:"\e06d"}.fa-bag-shopping:before,.fa-shopping-bag:before{content:"\f290"}.fa-arrow-down-z-a:before,.fa-sort-alpha-desc:before,.fa-sort-alpha-down-alt:before{content:"\f881"}.fa-mitten:before{content:"\f7b5"}.fa-person-rays:before{content:"\e54d"}.fa-users:before{content:"\f0c0"}.fa-eye-slash:before{content:"\f070"}.fa-flask-vial:before{content:"\e4f3"}.fa-hand-paper:before,.fa-hand:before{content:"\f256"}.fa-om:before{content:"\f679"}.fa-worm:before{content:"\e599"}.fa-house-circle-xmark:before{content:"\e50b"}.fa-plug:before{content:"\f1e6"}.fa-chevron-up:before{content:"\f077"}.fa-hand-spock:before{content:"\f259"}.fa-stopwatch:before{content:"\f2f2"}.fa-face-kiss:before,.fa-kiss:before{content:"\f596"}.fa-bridge-circle-xmark:before{content:"\e4cb"}.fa-face-grin-tongue:before,.fa-grin-tongue:before{content:"\f589"}.fa-chess-bishop:before{content:"\f43a"}.fa-face-grin-wink:before,.fa-grin-wink:before{content:"\f58c"}.fa-deaf:before,.fa-deafness:before,.fa-ear-deaf:before,.fa-hard-of-hearing:before{content:"\f2a4"}.fa-road-circle-check:before{content:"\e564"}.fa-dice-five:before{content:"\f523"}.fa-rss-square:before,.fa-square-rss:before{content:"\f143"}.fa-land-mine-on:before{content:"\e51b"}.fa-i-cursor:before{content:"\f246"}.fa-stamp:before{content:"\f5bf"}.fa-stairs:before{content:"\e289"}.fa-i:before{content:"\49"}.fa-hryvnia-sign:before,.fa-hryvnia:before{content:"\f6f2"}.fa-pills:before{content:"\f484"}.fa-face-grin-wide:before,.fa-grin-alt:before{content:"\f581"}.fa-tooth:before{content:"\f5c9"}.fa-v:before{content:"\56"}.fa-bangladeshi-taka-sign:before{content:"\e2e6"}.fa-bicycle:before{content:"\f206"}.fa-rod-asclepius:before,.fa-rod-snake:before,.fa-staff-aesculapius:before,.fa-staff-snake:before{content:"\e579"}.fa-head-side-cough-slash:before{content:"\e062"}.fa-ambulance:before,.fa-truck-medical:before{content:"\f0f9"}.fa-wheat-awn-circle-exclamation:before{content:"\e598"}.fa-snowman:before{content:"\f7d0"}.fa-mortar-pestle:before{content:"\f5a7"}.fa-road-barrier:before{content:"\e562"}.fa-school:before{content:"\f549"}.fa-igloo:before{content:"\f7ae"}.fa-joint:before{content:"\f595"}.fa-angle-right:before{content:"\f105"}.fa-horse:before{content:"\f6f0"}.fa-q:before{content:"\51"}.fa-g:before{content:"\47"}.fa-notes-medical:before{content:"\f481"}.fa-temperature-2:before,.fa-temperature-half:before,.fa-thermometer-2:before,.fa-thermometer-half:before{content:"\f2c9"}.fa-dong-sign:before{content:"\e169"}.fa-capsules:before{content:"\f46b"}.fa-poo-bolt:before,.fa-poo-storm:before{content:"\f75a"}.fa-face-frown-open:before,.fa-frown-open:before{content:"\f57a"}.fa-hand-point-up:before{content:"\f0a6"}.fa-money-bill:before{content:"\f0d6"}.fa-bookmark:before{content:"\f02e"}.fa-align-justify:before{content:"\f039"}.fa-umbrella-beach:before{content:"\f5ca"}.fa-helmet-un:before{content:"\e503"}.fa-bullseye:before{content:"\f140"}.fa-bacon:before{content:"\f7e5"}.fa-hand-point-down:before{content:"\f0a7"}.fa-arrow-up-from-bracket:before{content:"\e09a"}.fa-folder-blank:before,.fa-folder:before{content:"\f07b"}.fa-file-medical-alt:before,.fa-file-waveform:before{content:"\f478"}.fa-radiation:before{content:"\f7b9"}.fa-chart-simple:before{content:"\e473"}.fa-mars-stroke:before{content:"\f229"}.fa-vial:before{content:"\f492"}.fa-dashboard:before,.fa-gauge-med:before,.fa-gauge:before,.fa-tachometer-alt-average:before{content:"\f624"}.fa-magic-wand-sparkles:before,.fa-wand-magic-sparkles:before{content:"\e2ca"}.fa-e:before{content:"\45"}.fa-pen-alt:before,.fa-pen-clip:before{content:"\f305"}.fa-bridge-circle-exclamation:before{content:"\e4ca"}.fa-user:before{content:"\f007"}.fa-school-circle-check:before{content:"\e56b"}.fa-dumpster:before{content:"\f793"}.fa-shuttle-van:before,.fa-van-shuttle:before{content:"\f5b6"}.fa-building-user:before{content:"\e4da"}.fa-caret-square-left:before,.fa-square-caret-left:before{content:"\f191"}.fa-highlighter:before{content:"\f591"}.fa-key:before{content:"\f084"}.fa-bullhorn:before{content:"\f0a1"}.fa-globe:before{content:"\f0ac"}.fa-synagogue:before{content:"\f69b"}.fa-person-half-dress:before{content:"\e548"}.fa-road-bridge:before{content:"\e563"}.fa-location-arrow:before{content:"\f124"}.fa-c:before{content:"\43"}.fa-tablet-button:before{content:"\f10a"}.fa-building-lock:before{content:"\e4d6"}.fa-pizza-slice:before{content:"\f818"}.fa-money-bill-wave:before{content:"\f53a"}.fa-area-chart:before,.fa-chart-area:before{content:"\f1fe"}.fa-house-flag:before{content:"\e50d"}.fa-person-circle-minus:before{content:"\e540"}.fa-ban:before,.fa-cancel:before{content:"\f05e"}.fa-camera-rotate:before{content:"\e0d8"}.fa-air-freshener:before,.fa-spray-can-sparkles:before{content:"\f5d0"}.fa-star:before{content:"\f005"}.fa-repeat:before{content:"\f363"}.fa-cross:before{content:"\f654"}.fa-box:before{content:"\f466"}.fa-venus-mars:before{content:"\f228"}.fa-arrow-pointer:before,.fa-mouse-pointer:before{content:"\f245"}.fa-expand-arrows-alt:before,.fa-maximize:before{content:"\f31e"}.fa-charging-station:before{content:"\f5e7"}.fa-shapes:before,.fa-triangle-circle-square:before{content:"\f61f"}.fa-random:before,.fa-shuffle:before{content:"\f074"}.fa-person-running:before,.fa-running:before{content:"\f70c"}.fa-mobile-retro:before{content:"\e527"}.fa-grip-lines-vertical:before{content:"\f7a5"}.fa-spider:before{content:"\f717"}.fa-hands-bound:before{content:"\e4f9"}.fa-file-invoice-dollar:before{content:"\f571"}.fa-plane-circle-exclamation:before{content:"\e556"}.fa-x-ray:before{content:"\f497"}.fa-spell-check:before{content:"\f891"}.fa-slash:before{content:"\f715"}.fa-computer-mouse:before,.fa-mouse:before{content:"\f8cc"}.fa-arrow-right-to-bracket:before,.fa-sign-in:before{content:"\f090"}.fa-shop-slash:before,.fa-store-alt-slash:before{content:"\e070"}.fa-server:before{content:"\f233"}.fa-virus-covid-slash:before{content:"\e4a9"}.fa-shop-lock:before{content:"\e4a5"}.fa-hourglass-1:before,.fa-hourglass-start:before{content:"\f251"}.fa-blender-phone:before{content:"\f6b6"}.fa-building-wheat:before{content:"\e4db"}.fa-person-breastfeeding:before{content:"\e53a"}.fa-right-to-bracket:before,.fa-sign-in-alt:before{content:"\f2f6"}.fa-venus:before{content:"\f221"}.fa-passport:before{content:"\f5ab"}.fa-heart-pulse:before,.fa-heartbeat:before{content:"\f21e"}.fa-people-carry-box:before,.fa-people-carry:before{content:"\f4ce"}.fa-temperature-high:before{content:"\f769"}.fa-microchip:before{content:"\f2db"}.fa-crown:before{content:"\f521"}.fa-weight-hanging:before{content:"\f5cd"}.fa-xmarks-lines:before{content:"\e59a"}.fa-file-prescription:before{content:"\f572"}.fa-weight-scale:before,.fa-weight:before{content:"\f496"}.fa-user-friends:before,.fa-user-group:before{content:"\f500"}.fa-arrow-up-a-z:before,.fa-sort-alpha-up:before{content:"\f15e"}.fa-chess-knight:before{content:"\f441"}.fa-face-laugh-squint:before,.fa-laugh-squint:before{content:"\f59b"}.fa-wheelchair:before{content:"\f193"}.fa-arrow-circle-up:before,.fa-circle-arrow-up:before{content:"\f0aa"}.fa-toggle-on:before{content:"\f205"}.fa-person-walking:before,.fa-walking:before{content:"\f554"}.fa-l:before{content:"\4c"}.fa-fire:before{content:"\f06d"}.fa-bed-pulse:before,.fa-procedures:before{content:"\f487"}.fa-shuttle-space:before,.fa-space-shuttle:before{content:"\f197"}.fa-face-laugh:before,.fa-laugh:before{content:"\f599"}.fa-folder-open:before{content:"\f07c"}.fa-heart-circle-plus:before{content:"\e500"}.fa-code-fork:before{content:"\e13b"}.fa-city:before{content:"\f64f"}.fa-microphone-alt:before,.fa-microphone-lines:before{content:"\f3c9"}.fa-pepper-hot:before{content:"\f816"}.fa-unlock:before{content:"\f09c"}.fa-colon-sign:before{content:"\e140"}.fa-headset:before{content:"\f590"}.fa-store-slash:before{content:"\e071"}.fa-road-circle-xmark:before{content:"\e566"}.fa-user-minus:before{content:"\f503"}.fa-mars-stroke-up:before,.fa-mars-stroke-v:before{content:"\f22a"}.fa-champagne-glasses:before,.fa-glass-cheers:before{content:"\f79f"}.fa-clipboard:before{content:"\f328"}.fa-house-circle-exclamation:before{content:"\e50a"}.fa-file-arrow-up:before,.fa-file-upload:before{content:"\f574"}.fa-wifi-3:before,.fa-wifi-strong:before,.fa-wifi:before{content:"\f1eb"}.fa-bath:before,.fa-bathtub:before{content:"\f2cd"}.fa-underline:before{content:"\f0cd"}.fa-user-edit:before,.fa-user-pen:before{content:"\f4ff"}.fa-signature:before{content:"\f5b7"}.fa-stroopwafel:before{content:"\f551"}.fa-bold:before{content:"\f032"}.fa-anchor-lock:before{content:"\e4ad"}.fa-building-ngo:before{content:"\e4d7"}.fa-manat-sign:before{content:"\e1d5"}.fa-not-equal:before{content:"\f53e"}.fa-border-style:before,.fa-border-top-left:before{content:"\f853"}.fa-map-location-dot:before,.fa-map-marked-alt:before{content:"\f5a0"}.fa-jedi:before{content:"\f669"}.fa-poll:before,.fa-square-poll-vertical:before{content:"\f681"}.fa-mug-hot:before{content:"\f7b6"}.fa-battery-car:before,.fa-car-battery:before{content:"\f5df"}.fa-gift:before{content:"\f06b"}.fa-dice-two:before{content:"\f528"}.fa-chess-queen:before{content:"\f445"}.fa-glasses:before{content:"\f530"}.fa-chess-board:before{content:"\f43c"}.fa-building-circle-check:before{content:"\e4d2"}.fa-person-chalkboard:before{content:"\e53d"}.fa-mars-stroke-h:before,.fa-mars-stroke-right:before{content:"\f22b"}.fa-hand-back-fist:before,.fa-hand-rock:before{content:"\f255"}.fa-caret-square-up:before,.fa-square-caret-up:before{content:"\f151"}.fa-cloud-showers-water:before{content:"\e4e4"}.fa-bar-chart:before,.fa-chart-bar:before{content:"\f080"}.fa-hands-bubbles:before,.fa-hands-wash:before{content:"\e05e"}.fa-less-than-equal:before{content:"\f537"}.fa-train:before{content:"\f238"}.fa-eye-low-vision:before,.fa-low-vision:before{content:"\f2a8"}.fa-crow:before{content:"\f520"}.fa-sailboat:before{content:"\e445"}.fa-window-restore:before{content:"\f2d2"}.fa-plus-square:before,.fa-square-plus:before{content:"\f0fe"}.fa-torii-gate:before{content:"\f6a1"}.fa-frog:before{content:"\f52e"}.fa-bucket:before{content:"\e4cf"}.fa-image:before{content:"\f03e"}.fa-microphone:before{content:"\f130"}.fa-cow:before{content:"\f6c8"}.fa-caret-up:before{content:"\f0d8"}.fa-screwdriver:before{content:"\f54a"}.fa-folder-closed:before{content:"\e185"}.fa-house-tsunami:before{content:"\e515"}.fa-square-nfi:before{content:"\e576"}.fa-arrow-up-from-ground-water:before{content:"\e4b5"}.fa-glass-martini-alt:before,.fa-martini-glass:before{content:"\f57b"}.fa-rotate-back:before,.fa-rotate-backward:before,.fa-rotate-left:before,.fa-undo-alt:before{content:"\f2ea"}.fa-columns:before,.fa-table-columns:before{content:"\f0db"}.fa-lemon:before{content:"\f094"}.fa-head-side-mask:before{content:"\e063"}.fa-handshake:before{content:"\f2b5"}.fa-gem:before{content:"\f3a5"}.fa-dolly-box:before,.fa-dolly:before{content:"\f472"}.fa-smoking:before{content:"\f48d"}.fa-compress-arrows-alt:before,.fa-minimize:before{content:"\f78c"}.fa-monument:before{content:"\f5a6"}.fa-snowplow:before{content:"\f7d2"}.fa-angle-double-right:before,.fa-angles-right:before{content:"\f101"}.fa-cannabis:before{content:"\f55f"}.fa-circle-play:before,.fa-play-circle:before{content:"\f144"}.fa-tablets:before{content:"\f490"}.fa-ethernet:before{content:"\f796"}.fa-eur:before,.fa-euro-sign:before,.fa-euro:before{content:"\f153"}.fa-chair:before{content:"\f6c0"}.fa-check-circle:before,.fa-circle-check:before{content:"\f058"}.fa-circle-stop:before,.fa-stop-circle:before{content:"\f28d"}.fa-compass-drafting:before,.fa-drafting-compass:before{content:"\f568"}.fa-plate-wheat:before{content:"\e55a"}.fa-icicles:before{content:"\f7ad"}.fa-person-shelter:before{content:"\e54f"}.fa-neuter:before{content:"\f22c"}.fa-id-badge:before{content:"\f2c1"}.fa-marker:before{content:"\f5a1"}.fa-face-laugh-beam:before,.fa-laugh-beam:before{content:"\f59a"}.fa-helicopter-symbol:before{content:"\e502"}.fa-universal-access:before{content:"\f29a"}.fa-chevron-circle-up:before,.fa-circle-chevron-up:before{content:"\f139"}.fa-lari-sign:before{content:"\e1c8"}.fa-volcano:before{content:"\f770"}.fa-person-walking-dashed-line-arrow-right:before{content:"\e553"}.fa-gbp:before,.fa-pound-sign:before,.fa-sterling-sign:before{content:"\f154"}.fa-viruses:before{content:"\e076"}.fa-square-person-confined:before{content:"\e577"}.fa-user-tie:before{content:"\f508"}.fa-arrow-down-long:before,.fa-long-arrow-down:before{content:"\f175"}.fa-tent-arrow-down-to-line:before{content:"\e57e"}.fa-certificate:before{content:"\f0a3"}.fa-mail-reply-all:before,.fa-reply-all:before{content:"\f122"}.fa-suitcase:before{content:"\f0f2"}.fa-person-skating:before,.fa-skating:before{content:"\f7c5"}.fa-filter-circle-dollar:before,.fa-funnel-dollar:before{content:"\f662"}.fa-camera-retro:before{content:"\f083"}.fa-arrow-circle-down:before,.fa-circle-arrow-down:before{content:"\f0ab"}.fa-arrow-right-to-file:before,.fa-file-import:before{content:"\f56f"}.fa-external-link-square:before,.fa-square-arrow-up-right:before{content:"\f14c"}.fa-box-open:before{content:"\f49e"}.fa-scroll:before{content:"\f70e"}.fa-spa:before{content:"\f5bb"}.fa-location-pin-lock:before{content:"\e51f"}.fa-pause:before{content:"\f04c"}.fa-hill-avalanche:before{content:"\e507"}.fa-temperature-0:before,.fa-temperature-empty:before,.fa-thermometer-0:before,.fa-thermometer-empty:before{content:"\f2cb"}.fa-bomb:before{content:"\f1e2"}.fa-registered:before{content:"\f25d"}.fa-address-card:before,.fa-contact-card:before,.fa-vcard:before{content:"\f2bb"}.fa-balance-scale-right:before,.fa-scale-unbalanced-flip:before{content:"\f516"}.fa-subscript:before{content:"\f12c"}.fa-diamond-turn-right:before,.fa-directions:before{content:"\f5eb"}.fa-burst:before{content:"\e4dc"}.fa-house-laptop:before,.fa-laptop-house:before{content:"\e066"}.fa-face-tired:before,.fa-tired:before{content:"\f5c8"}.fa-money-bills:before{content:"\e1f3"}.fa-smog:before{content:"\f75f"}.fa-crutch:before{content:"\f7f7"}.fa-cloud-arrow-up:before,.fa-cloud-upload-alt:before,.fa-cloud-upload:before{content:"\f0ee"}.fa-palette:before{content:"\f53f"}.fa-arrows-turn-right:before{content:"\e4c0"}.fa-vest:before{content:"\e085"}.fa-ferry:before{content:"\e4ea"}.fa-arrows-down-to-people:before{content:"\e4b9"}.fa-seedling:before,.fa-sprout:before{content:"\f4d8"}.fa-arrows-alt-h:before,.fa-left-right:before{content:"\f337"}.fa-boxes-packing:before{content:"\e4c7"}.fa-arrow-circle-left:before,.fa-circle-arrow-left:before{content:"\f0a8"}.fa-group-arrows-rotate:before{content:"\e4f6"}.fa-bowl-food:before{content:"\e4c6"}.fa-candy-cane:before{content:"\f786"}.fa-arrow-down-wide-short:before,.fa-sort-amount-asc:before,.fa-sort-amount-down:before{content:"\f160"}.fa-cloud-bolt:before,.fa-thunderstorm:before{content:"\f76c"}.fa-remove-format:before,.fa-text-slash:before{content:"\f87d"}.fa-face-smile-wink:before,.fa-smile-wink:before{content:"\f4da"}.fa-file-word:before{content:"\f1c2"}.fa-file-powerpoint:before{content:"\f1c4"}.fa-arrows-h:before,.fa-arrows-left-right:before{content:"\f07e"}.fa-house-lock:before{content:"\e510"}.fa-cloud-arrow-down:before,.fa-cloud-download-alt:before,.fa-cloud-download:before{content:"\f0ed"}.fa-children:before{content:"\e4e1"}.fa-blackboard:before,.fa-chalkboard:before{content:"\f51b"}.fa-user-alt-slash:before,.fa-user-large-slash:before{content:"\f4fa"}.fa-envelope-open:before{content:"\f2b6"}.fa-handshake-alt-slash:before,.fa-handshake-simple-slash:before{content:"\e05f"}.fa-mattress-pillow:before{content:"\e525"}.fa-guarani-sign:before{content:"\e19a"}.fa-arrows-rotate:before,.fa-refresh:before,.fa-sync:before{content:"\f021"}.fa-fire-extinguisher:before{content:"\f134"}.fa-cruzeiro-sign:before{content:"\e152"}.fa-greater-than-equal:before{content:"\f532"}.fa-shield-alt:before,.fa-shield-halved:before{content:"\f3ed"}.fa-atlas:before,.fa-book-atlas:before{content:"\f558"}.fa-virus:before{content:"\e074"}.fa-envelope-circle-check:before{content:"\e4e8"}.fa-layer-group:before{content:"\f5fd"}.fa-arrows-to-dot:before{content:"\e4be"}.fa-archway:before{content:"\f557"}.fa-heart-circle-check:before{content:"\e4fd"}.fa-house-chimney-crack:before,.fa-house-damage:before{content:"\f6f1"}.fa-file-archive:before,.fa-file-zipper:before{content:"\f1c6"}.fa-square:before{content:"\f0c8"}.fa-glass-martini:before,.fa-martini-glass-empty:before{content:"\f000"}.fa-couch:before{content:"\f4b8"}.fa-cedi-sign:before{content:"\e0df"}.fa-italic:before{content:"\f033"}.fa-table-cells-column-lock:before{content:"\e678"}.fa-church:before{content:"\f51d"}.fa-comments-dollar:before{content:"\f653"}.fa-democrat:before{content:"\f747"}.fa-z:before{content:"\5a"}.fa-person-skiing:before,.fa-skiing:before{content:"\f7c9"}.fa-road-lock:before{content:"\e567"}.fa-a:before{content:"\41"}.fa-temperature-arrow-down:before,.fa-temperature-down:before{content:"\e03f"}.fa-feather-alt:before,.fa-feather-pointed:before{content:"\f56b"}.fa-p:before{content:"\50"}.fa-snowflake:before{content:"\f2dc"}.fa-newspaper:before{content:"\f1ea"}.fa-ad:before,.fa-rectangle-ad:before{content:"\f641"}.fa-arrow-circle-right:before,.fa-circle-arrow-right:before{content:"\f0a9"}.fa-filter-circle-xmark:before{content:"\e17b"}.fa-locust:before{content:"\e520"}.fa-sort:before,.fa-unsorted:before{content:"\f0dc"}.fa-list-1-2:before,.fa-list-numeric:before,.fa-list-ol:before{content:"\f0cb"}.fa-person-dress-burst:before{content:"\e544"}.fa-money-check-alt:before,.fa-money-check-dollar:before{content:"\f53d"}.fa-vector-square:before{content:"\f5cb"}.fa-bread-slice:before{content:"\f7ec"}.fa-language:before{content:"\f1ab"}.fa-face-kiss-wink-heart:before,.fa-kiss-wink-heart:before{content:"\f598"}.fa-filter:before{content:"\f0b0"}.fa-question:before{content:"\3f"}.fa-file-signature:before{content:"\f573"}.fa-arrows-alt:before,.fa-up-down-left-right:before{content:"\f0b2"}.fa-house-chimney-user:before{content:"\e065"}.fa-hand-holding-heart:before{content:"\f4be"}.fa-puzzle-piece:before{content:"\f12e"}.fa-money-check:before{content:"\f53c"}.fa-star-half-alt:before,.fa-star-half-stroke:before{content:"\f5c0"}.fa-code:before{content:"\f121"}.fa-glass-whiskey:before,.fa-whiskey-glass:before{content:"\f7a0"}.fa-building-circle-exclamation:before{content:"\e4d3"}.fa-magnifying-glass-chart:before{content:"\e522"}.fa-arrow-up-right-from-square:before,.fa-external-link:before{content:"\f08e"}.fa-cubes-stacked:before{content:"\e4e6"}.fa-krw:before,.fa-won-sign:before,.fa-won:before{content:"\f159"}.fa-virus-covid:before{content:"\e4a8"}.fa-austral-sign:before{content:"\e0a9"}.fa-f:before{content:"\46"}.fa-leaf:before{content:"\f06c"}.fa-road:before{content:"\f018"}.fa-cab:before,.fa-taxi:before{content:"\f1ba"}.fa-person-circle-plus:before{content:"\e541"}.fa-chart-pie:before,.fa-pie-chart:before{content:"\f200"}.fa-bolt-lightning:before{content:"\e0b7"}.fa-sack-xmark:before{content:"\e56a"}.fa-file-excel:before{content:"\f1c3"}.fa-file-contract:before{content:"\f56c"}.fa-fish-fins:before{content:"\e4f2"}.fa-building-flag:before{content:"\e4d5"}.fa-face-grin-beam:before,.fa-grin-beam:before{content:"\f582"}.fa-object-ungroup:before{content:"\f248"}.fa-poop:before{content:"\f619"}.fa-location-pin:before,.fa-map-marker:before{content:"\f041"}.fa-kaaba:before{content:"\f66b"}.fa-toilet-paper:before{content:"\f71e"}.fa-hard-hat:before,.fa-hat-hard:before,.fa-helmet-safety:before{content:"\f807"}.fa-eject:before{content:"\f052"}.fa-arrow-alt-circle-right:before,.fa-circle-right:before{content:"\f35a"}.fa-plane-circle-check:before{content:"\e555"}.fa-face-rolling-eyes:before,.fa-meh-rolling-eyes:before{content:"\f5a5"}.fa-object-group:before{content:"\f247"}.fa-chart-line:before,.fa-line-chart:before{content:"\f201"}.fa-mask-ventilator:before{content:"\e524"}.fa-arrow-right:before{content:"\f061"}.fa-map-signs:before,.fa-signs-post:before{content:"\f277"}.fa-cash-register:before{content:"\f788"}.fa-person-circle-question:before{content:"\e542"}.fa-h:before{content:"\48"}.fa-tarp:before{content:"\e57b"}.fa-screwdriver-wrench:before,.fa-tools:before{content:"\f7d9"}.fa-arrows-to-eye:before{content:"\e4bf"}.fa-plug-circle-bolt:before{content:"\e55b"}.fa-heart:before{content:"\f004"}.fa-mars-and-venus:before{content:"\f224"}.fa-home-user:before,.fa-house-user:before{content:"\e1b0"}.fa-dumpster-fire:before{content:"\f794"}.fa-house-crack:before{content:"\e3b1"}.fa-cocktail:before,.fa-martini-glass-citrus:before{content:"\f561"}.fa-face-surprise:before,.fa-surprise:before{content:"\f5c2"}.fa-bottle-water:before{content:"\e4c5"}.fa-circle-pause:before,.fa-pause-circle:before{content:"\f28b"}.fa-toilet-paper-slash:before{content:"\e072"}.fa-apple-alt:before,.fa-apple-whole:before{content:"\f5d1"}.fa-kitchen-set:before{content:"\e51a"}.fa-r:before{content:"\52"}.fa-temperature-1:before,.fa-temperature-quarter:before,.fa-thermometer-1:before,.fa-thermometer-quarter:before{content:"\f2ca"}.fa-cube:before{content:"\f1b2"}.fa-bitcoin-sign:before{content:"\e0b4"}.fa-shield-dog:before{content:"\e573"}.fa-solar-panel:before{content:"\f5ba"}.fa-lock-open:before{content:"\f3c1"}.fa-elevator:before{content:"\e16d"}.fa-money-bill-transfer:before{content:"\e528"}.fa-money-bill-trend-up:before{content:"\e529"}.fa-house-flood-water-circle-arrow-right:before{content:"\e50f"}.fa-poll-h:before,.fa-square-poll-horizontal:before{content:"\f682"}.fa-circle:before{content:"\f111"}.fa-backward-fast:before,.fa-fast-backward:before{content:"\f049"}.fa-recycle:before{content:"\f1b8"}.fa-user-astronaut:before{content:"\f4fb"}.fa-plane-slash:before{content:"\e069"}.fa-trademark:before{content:"\f25c"}.fa-basketball-ball:before,.fa-basketball:before{content:"\f434"}.fa-satellite-dish:before{content:"\f7c0"}.fa-arrow-alt-circle-up:before,.fa-circle-up:before{content:"\f35b"}.fa-mobile-alt:before,.fa-mobile-screen-button:before{content:"\f3cd"}.fa-volume-high:before,.fa-volume-up:before{content:"\f028"}.fa-users-rays:before{content:"\e593"}.fa-wallet:before{content:"\f555"}.fa-clipboard-check:before{content:"\f46c"}.fa-file-audio:before{content:"\f1c7"}.fa-burger:before,.fa-hamburger:before{content:"\f805"}.fa-wrench:before{content:"\f0ad"}.fa-bugs:before{content:"\e4d0"}.fa-rupee-sign:before,.fa-rupee:before{content:"\f156"}.fa-file-image:before{content:"\f1c5"}.fa-circle-question:before,.fa-question-circle:before{content:"\f059"}.fa-plane-departure:before{content:"\f5b0"}.fa-handshake-slash:before{content:"\e060"}.fa-book-bookmark:before{content:"\e0bb"}.fa-code-branch:before{content:"\f126"}.fa-hat-cowboy:before{content:"\f8c0"}.fa-bridge:before{content:"\e4c8"}.fa-phone-alt:before,.fa-phone-flip:before{content:"\f879"}.fa-truck-front:before{content:"\e2b7"}.fa-cat:before{content:"\f6be"}.fa-anchor-circle-exclamation:before{content:"\e4ab"}.fa-truck-field:before{content:"\e58d"}.fa-route:before{content:"\f4d7"}.fa-clipboard-question:before{content:"\e4e3"}.fa-panorama:before{content:"\e209"}.fa-comment-medical:before{content:"\f7f5"}.fa-teeth-open:before{content:"\f62f"}.fa-file-circle-minus:before{content:"\e4ed"}.fa-tags:before{content:"\f02c"}.fa-wine-glass:before{content:"\f4e3"}.fa-fast-forward:before,.fa-forward-fast:before{content:"\f050"}.fa-face-meh-blank:before,.fa-meh-blank:before{content:"\f5a4"}.fa-parking:before,.fa-square-parking:before{content:"\f540"}.fa-house-signal:before{content:"\e012"}.fa-bars-progress:before,.fa-tasks-alt:before{content:"\f828"}.fa-faucet-drip:before{content:"\e006"}.fa-cart-flatbed:before,.fa-dolly-flatbed:before{content:"\f474"}.fa-ban-smoking:before,.fa-smoking-ban:before{content:"\f54d"}.fa-terminal:before{content:"\f120"}.fa-mobile-button:before{content:"\f10b"}.fa-house-medical-flag:before{content:"\e514"}.fa-basket-shopping:before,.fa-shopping-basket:before{content:"\f291"}.fa-tape:before{content:"\f4db"}.fa-bus-alt:before,.fa-bus-simple:before{content:"\f55e"}.fa-eye:before{content:"\f06e"}.fa-face-sad-cry:before,.fa-sad-cry:before{content:"\f5b3"}.fa-audio-description:before{content:"\f29e"}.fa-person-military-to-person:before{content:"\e54c"}.fa-file-shield:before{content:"\e4f0"}.fa-user-slash:before{content:"\f506"}.fa-pen:before{content:"\f304"}.fa-tower-observation:before{content:"\e586"}.fa-file-code:before{content:"\f1c9"}.fa-signal-5:before,.fa-signal-perfect:before,.fa-signal:before{content:"\f012"}.fa-bus:before{content:"\f207"}.fa-heart-circle-xmark:before{content:"\e501"}.fa-home-lg:before,.fa-house-chimney:before{content:"\e3af"}.fa-window-maximize:before{content:"\f2d0"}.fa-face-frown:before,.fa-frown:before{content:"\f119"}.fa-prescription:before{content:"\f5b1"}.fa-shop:before,.fa-store-alt:before{content:"\f54f"}.fa-floppy-disk:before,.fa-save:before{content:"\f0c7"}.fa-vihara:before{content:"\f6a7"}.fa-balance-scale-left:before,.fa-scale-unbalanced:before{content:"\f515"}.fa-sort-asc:before,.fa-sort-up:before{content:"\f0de"}.fa-comment-dots:before,.fa-commenting:before{content:"\f4ad"}.fa-plant-wilt:before{content:"\e5aa"}.fa-diamond:before{content:"\f219"}.fa-face-grin-squint:before,.fa-grin-squint:before{content:"\f585"}.fa-hand-holding-dollar:before,.fa-hand-holding-usd:before{content:"\f4c0"}.fa-bacterium:before{content:"\e05a"}.fa-hand-pointer:before{content:"\f25a"}.fa-drum-steelpan:before{content:"\f56a"}.fa-hand-scissors:before{content:"\f257"}.fa-hands-praying:before,.fa-praying-hands:before{content:"\f684"}.fa-arrow-right-rotate:before,.fa-arrow-rotate-forward:before,.fa-arrow-rotate-right:before,.fa-redo:before{content:"\f01e"}.fa-biohazard:before{content:"\f780"}.fa-location-crosshairs:before,.fa-location:before{content:"\f601"}.fa-mars-double:before{content:"\f227"}.fa-child-dress:before{content:"\e59c"}.fa-users-between-lines:before{content:"\e591"}.fa-lungs-virus:before{content:"\e067"}.fa-face-grin-tears:before,.fa-grin-tears:before{content:"\f588"}.fa-phone:before{content:"\f095"}.fa-calendar-times:before,.fa-calendar-xmark:before{content:"\f273"}.fa-child-reaching:before{content:"\e59d"}.fa-head-side-virus:before{content:"\e064"}.fa-user-cog:before,.fa-user-gear:before{content:"\f4fe"}.fa-arrow-up-1-9:before,.fa-sort-numeric-up:before{content:"\f163"}.fa-door-closed:before{content:"\f52a"}.fa-shield-virus:before{content:"\e06c"}.fa-dice-six:before{content:"\f526"}.fa-mosquito-net:before{content:"\e52c"}.fa-bridge-water:before{content:"\e4ce"}.fa-person-booth:before{content:"\f756"}.fa-text-width:before{content:"\f035"}.fa-hat-wizard:before{content:"\f6e8"}.fa-pen-fancy:before{content:"\f5ac"}.fa-digging:before,.fa-person-digging:before{content:"\f85e"}.fa-trash:before{content:"\f1f8"}.fa-gauge-simple-med:before,.fa-gauge-simple:before,.fa-tachometer-average:before{content:"\f629"}.fa-book-medical:before{content:"\f7e6"}.fa-poo:before{content:"\f2fe"}.fa-quote-right-alt:before,.fa-quote-right:before{content:"\f10e"}.fa-shirt:before,.fa-t-shirt:before,.fa-tshirt:before{content:"\f553"}.fa-cubes:before{content:"\f1b3"}.fa-divide:before{content:"\f529"}.fa-tenge-sign:before,.fa-tenge:before{content:"\f7d7"}.fa-headphones:before{content:"\f025"}.fa-hands-holding:before{content:"\f4c2"}.fa-hands-clapping:before{content:"\e1a8"}.fa-republican:before{content:"\f75e"}.fa-arrow-left:before{content:"\f060"}.fa-person-circle-xmark:before{content:"\e543"}.fa-ruler:before{content:"\f545"}.fa-align-left:before{content:"\f036"}.fa-dice-d6:before{content:"\f6d1"}.fa-restroom:before{content:"\f7bd"}.fa-j:before{content:"\4a"}.fa-users-viewfinder:before{content:"\e595"}.fa-file-video:before{content:"\f1c8"}.fa-external-link-alt:before,.fa-up-right-from-square:before{content:"\f35d"}.fa-table-cells:before,.fa-th:before{content:"\f00a"}.fa-file-pdf:before{content:"\f1c1"}.fa-bible:before,.fa-book-bible:before{content:"\f647"}.fa-o:before{content:"\4f"}.fa-medkit:before,.fa-suitcase-medical:before{content:"\f0fa"}.fa-user-secret:before{content:"\f21b"}.fa-otter:before{content:"\f700"}.fa-female:before,.fa-person-dress:before{content:"\f182"}.fa-comment-dollar:before{content:"\f651"}.fa-briefcase-clock:before,.fa-business-time:before{content:"\f64a"}.fa-table-cells-large:before,.fa-th-large:before{content:"\f009"}.fa-book-tanakh:before,.fa-tanakh:before{content:"\f827"}.fa-phone-volume:before,.fa-volume-control-phone:before{content:"\f2a0"}.fa-hat-cowboy-side:before{content:"\f8c1"}.fa-clipboard-user:before{content:"\f7f3"}.fa-child:before{content:"\f1ae"}.fa-lira-sign:before{content:"\f195"}.fa-satellite:before{content:"\f7bf"}.fa-plane-lock:before{content:"\e558"}.fa-tag:before{content:"\f02b"}.fa-comment:before{content:"\f075"}.fa-birthday-cake:before,.fa-cake-candles:before,.fa-cake:before{content:"\f1fd"}.fa-envelope:before{content:"\f0e0"}.fa-angle-double-up:before,.fa-angles-up:before{content:"\f102"}.fa-paperclip:before{content:"\f0c6"}.fa-arrow-right-to-city:before{content:"\e4b3"}.fa-ribbon:before{content:"\f4d6"}.fa-lungs:before{content:"\f604"}.fa-arrow-up-9-1:before,.fa-sort-numeric-up-alt:before{content:"\f887"}.fa-litecoin-sign:before{content:"\e1d3"}.fa-border-none:before{content:"\f850"}.fa-circle-nodes:before{content:"\e4e2"}.fa-parachute-box:before{content:"\f4cd"}.fa-indent:before{content:"\f03c"}.fa-truck-field-un:before{content:"\e58e"}.fa-hourglass-empty:before,.fa-hourglass:before{content:"\f254"}.fa-mountain:before{content:"\f6fc"}.fa-user-doctor:before,.fa-user-md:before{content:"\f0f0"}.fa-circle-info:before,.fa-info-circle:before{content:"\f05a"}.fa-cloud-meatball:before{content:"\f73b"}.fa-camera-alt:before,.fa-camera:before{content:"\f030"}.fa-square-virus:before{content:"\e578"}.fa-meteor:before{content:"\f753"}.fa-car-on:before{content:"\e4dd"}.fa-sleigh:before{content:"\f7cc"}.fa-arrow-down-1-9:before,.fa-sort-numeric-asc:before,.fa-sort-numeric-down:before{content:"\f162"}.fa-hand-holding-droplet:before,.fa-hand-holding-water:before{content:"\f4c1"}.fa-water:before{content:"\f773"}.fa-calendar-check:before{content:"\f274"}.fa-braille:before{content:"\f2a1"}.fa-prescription-bottle-alt:before,.fa-prescription-bottle-medical:before{content:"\f486"}.fa-landmark:before{content:"\f66f"}.fa-truck:before{content:"\f0d1"}.fa-crosshairs:before{content:"\f05b"}.fa-person-cane:before{content:"\e53c"}.fa-tent:before{content:"\e57d"}.fa-vest-patches:before{content:"\e086"}.fa-check-double:before{content:"\f560"}.fa-arrow-down-a-z:before,.fa-sort-alpha-asc:before,.fa-sort-alpha-down:before{content:"\f15d"}.fa-money-bill-wheat:before{content:"\e52a"}.fa-cookie:before{content:"\f563"}.fa-arrow-left-rotate:before,.fa-arrow-rotate-back:before,.fa-arrow-rotate-backward:before,.fa-arrow-rotate-left:before,.fa-undo:before{content:"\f0e2"}.fa-hard-drive:before,.fa-hdd:before{content:"\f0a0"}.fa-face-grin-squint-tears:before,.fa-grin-squint-tears:before{content:"\f586"}.fa-dumbbell:before{content:"\f44b"}.fa-list-alt:before,.fa-rectangle-list:before{content:"\f022"}.fa-tarp-droplet:before{content:"\e57c"}.fa-house-medical-circle-check:before{content:"\e511"}.fa-person-skiing-nordic:before,.fa-skiing-nordic:before{content:"\f7ca"}.fa-calendar-plus:before{content:"\f271"}.fa-plane-arrival:before{content:"\f5af"}.fa-arrow-alt-circle-left:before,.fa-circle-left:before{content:"\f359"}.fa-subway:before,.fa-train-subway:before{content:"\f239"}.fa-chart-gantt:before{content:"\e0e4"}.fa-indian-rupee-sign:before,.fa-indian-rupee:before,.fa-inr:before{content:"\e1bc"}.fa-crop-alt:before,.fa-crop-simple:before{content:"\f565"}.fa-money-bill-1:before,.fa-money-bill-alt:before{content:"\f3d1"}.fa-left-long:before,.fa-long-arrow-alt-left:before{content:"\f30a"}.fa-dna:before{content:"\f471"}.fa-virus-slash:before{content:"\e075"}.fa-minus:before,.fa-subtract:before{content:"\f068"}.fa-chess:before{content:"\f439"}.fa-arrow-left-long:before,.fa-long-arrow-left:before{content:"\f177"}.fa-plug-circle-check:before{content:"\e55c"}.fa-street-view:before{content:"\f21d"}.fa-franc-sign:before{content:"\e18f"}.fa-volume-off:before{content:"\f026"}.fa-american-sign-language-interpreting:before,.fa-asl-interpreting:before,.fa-hands-american-sign-language-interpreting:before,.fa-hands-asl-interpreting:before{content:"\f2a3"}.fa-cog:before,.fa-gear:before{content:"\f013"}.fa-droplet-slash:before,.fa-tint-slash:before{content:"\f5c7"}.fa-mosque:before{content:"\f678"}.fa-mosquito:before{content:"\e52b"}.fa-star-of-david:before{content:"\f69a"}.fa-person-military-rifle:before{content:"\e54b"}.fa-cart-shopping:before,.fa-shopping-cart:before{content:"\f07a"}.fa-vials:before{content:"\f493"}.fa-plug-circle-plus:before{content:"\e55f"}.fa-place-of-worship:before{content:"\f67f"}.fa-grip-vertical:before{content:"\f58e"}.fa-arrow-turn-up:before,.fa-level-up:before{content:"\f148"}.fa-u:before{content:"\55"}.fa-square-root-alt:before,.fa-square-root-variable:before{content:"\f698"}.fa-clock-four:before,.fa-clock:before{content:"\f017"}.fa-backward-step:before,.fa-step-backward:before{content:"\f048"}.fa-pallet:before{content:"\f482"}.fa-faucet:before{content:"\e005"}.fa-baseball-bat-ball:before{content:"\f432"}.fa-s:before{content:"\53"}.fa-timeline:before{content:"\e29c"}.fa-keyboard:before{content:"\f11c"}.fa-caret-down:before{content:"\f0d7"}.fa-clinic-medical:before,.fa-house-chimney-medical:before{content:"\f7f2"}.fa-temperature-3:before,.fa-temperature-three-quarters:before,.fa-thermometer-3:before,.fa-thermometer-three-quarters:before{content:"\f2c8"}.fa-mobile-android-alt:before,.fa-mobile-screen:before{content:"\f3cf"}.fa-plane-up:before{content:"\e22d"}.fa-piggy-bank:before{content:"\f4d3"}.fa-battery-3:before,.fa-battery-half:before{content:"\f242"}.fa-mountain-city:before{content:"\e52e"}.fa-coins:before{content:"\f51e"}.fa-khanda:before{content:"\f66d"}.fa-sliders-h:before,.fa-sliders:before{content:"\f1de"}.fa-folder-tree:before{content:"\f802"}.fa-network-wired:before{content:"\f6ff"}.fa-map-pin:before{content:"\f276"}.fa-hamsa:before{content:"\f665"}.fa-cent-sign:before{content:"\e3f5"}.fa-flask:before{content:"\f0c3"}.fa-person-pregnant:before{content:"\e31e"}.fa-wand-sparkles:before{content:"\f72b"}.fa-ellipsis-v:before,.fa-ellipsis-vertical:before{content:"\f142"}.fa-ticket:before{content:"\f145"}.fa-power-off:before{content:"\f011"}.fa-long-arrow-alt-right:before,.fa-right-long:before{content:"\f30b"}.fa-flag-usa:before{content:"\f74d"}.fa-laptop-file:before{content:"\e51d"}.fa-teletype:before,.fa-tty:before{content:"\f1e4"}.fa-diagram-next:before{content:"\e476"}.fa-person-rifle:before{content:"\e54e"}.fa-house-medical-circle-exclamation:before{content:"\e512"}.fa-closed-captioning:before{content:"\f20a"}.fa-hiking:before,.fa-person-hiking:before{content:"\f6ec"}.fa-venus-double:before{content:"\f226"}.fa-images:before{content:"\f302"}.fa-calculator:before{content:"\f1ec"}.fa-people-pulling:before{content:"\e535"}.fa-n:before{content:"\4e"}.fa-cable-car:before,.fa-tram:before{content:"\f7da"}.fa-cloud-rain:before{content:"\f73d"}.fa-building-circle-xmark:before{content:"\e4d4"}.fa-ship:before{content:"\f21a"}.fa-arrows-down-to-line:before{content:"\e4b8"}.fa-download:before{content:"\f019"}.fa-face-grin:before,.fa-grin:before{content:"\f580"}.fa-backspace:before,.fa-delete-left:before{content:"\f55a"}.fa-eye-dropper-empty:before,.fa-eye-dropper:before,.fa-eyedropper:before{content:"\f1fb"}.fa-file-circle-check:before{content:"\e5a0"}.fa-forward:before{content:"\f04e"}.fa-mobile-android:before,.fa-mobile-phone:before,.fa-mobile:before{content:"\f3ce"}.fa-face-meh:before,.fa-meh:before{content:"\f11a"}.fa-align-center:before{content:"\f037"}.fa-book-dead:before,.fa-book-skull:before{content:"\f6b7"}.fa-drivers-license:before,.fa-id-card:before{content:"\f2c2"}.fa-dedent:before,.fa-outdent:before{content:"\f03b"}.fa-heart-circle-exclamation:before{content:"\e4fe"}.fa-home-alt:before,.fa-home-lg-alt:before,.fa-home:before,.fa-house:before{content:"\f015"}.fa-calendar-week:before{content:"\f784"}.fa-laptop-medical:before{content:"\f812"}.fa-b:before{content:"\42"}.fa-file-medical:before{content:"\f477"}.fa-dice-one:before{content:"\f525"}.fa-kiwi-bird:before{content:"\f535"}.fa-arrow-right-arrow-left:before,.fa-exchange:before{content:"\f0ec"}.fa-redo-alt:before,.fa-rotate-forward:before,.fa-rotate-right:before{content:"\f2f9"}.fa-cutlery:before,.fa-utensils:before{content:"\f2e7"}.fa-arrow-up-wide-short:before,.fa-sort-amount-up:before{content:"\f161"}.fa-mill-sign:before{content:"\e1ed"}.fa-bowl-rice:before{content:"\e2eb"}.fa-skull:before{content:"\f54c"}.fa-broadcast-tower:before,.fa-tower-broadcast:before{content:"\f519"}.fa-truck-pickup:before{content:"\f63c"}.fa-long-arrow-alt-up:before,.fa-up-long:before{content:"\f30c"}.fa-stop:before{content:"\f04d"}.fa-code-merge:before{content:"\f387"}.fa-upload:before{content:"\f093"}.fa-hurricane:before{content:"\f751"}.fa-mound:before{content:"\e52d"}.fa-toilet-portable:before{content:"\e583"}.fa-compact-disc:before{content:"\f51f"}.fa-file-arrow-down:before,.fa-file-download:before{content:"\f56d"}.fa-caravan:before{content:"\f8ff"}.fa-shield-cat:before{content:"\e572"}.fa-bolt:before,.fa-zap:before{content:"\f0e7"}.fa-glass-water:before{content:"\e4f4"}.fa-oil-well:before{content:"\e532"}.fa-vault:before{content:"\e2c5"}.fa-mars:before{content:"\f222"}.fa-toilet:before{content:"\f7d8"}.fa-plane-circle-xmark:before{content:"\e557"}.fa-cny:before,.fa-jpy:before,.fa-rmb:before,.fa-yen-sign:before,.fa-yen:before{content:"\f157"}.fa-rouble:before,.fa-rub:before,.fa-ruble-sign:before,.fa-ruble:before{content:"\f158"}.fa-sun:before{content:"\f185"}.fa-guitar:before{content:"\f7a6"}.fa-face-laugh-wink:before,.fa-laugh-wink:before{content:"\f59c"}.fa-horse-head:before{content:"\f7ab"}.fa-bore-hole:before{content:"\e4c3"}.fa-industry:before{content:"\f275"}.fa-arrow-alt-circle-down:before,.fa-circle-down:before{content:"\f358"}.fa-arrows-turn-to-dots:before{content:"\e4c1"}.fa-florin-sign:before{content:"\e184"}.fa-arrow-down-short-wide:before,.fa-sort-amount-desc:before,.fa-sort-amount-down-alt:before{content:"\f884"}.fa-less-than:before{content:"\3c"}.fa-angle-down:before{content:"\f107"}.fa-car-tunnel:before{content:"\e4de"}.fa-head-side-cough:before{content:"\e061"}.fa-grip-lines:before{content:"\f7a4"}.fa-thumbs-down:before{content:"\f165"}.fa-user-lock:before{content:"\f502"}.fa-arrow-right-long:before,.fa-long-arrow-right:before{content:"\f178"}.fa-anchor-circle-xmark:before{content:"\e4ac"}.fa-ellipsis-h:before,.fa-ellipsis:before{content:"\f141"}.fa-chess-pawn:before{content:"\f443"}.fa-first-aid:before,.fa-kit-medical:before{content:"\f479"}.fa-person-through-window:before{content:"\e5a9"}.fa-toolbox:before{content:"\f552"}.fa-hands-holding-circle:before{content:"\e4fb"}.fa-bug:before{content:"\f188"}.fa-credit-card-alt:before,.fa-credit-card:before{content:"\f09d"}.fa-automobile:before,.fa-car:before{content:"\f1b9"}.fa-hand-holding-hand:before{content:"\e4f7"}.fa-book-open-reader:before,.fa-book-reader:before{content:"\f5da"}.fa-mountain-sun:before{content:"\e52f"}.fa-arrows-left-right-to-line:before{content:"\e4ba"}.fa-dice-d20:before{content:"\f6cf"}.fa-truck-droplet:before{content:"\e58c"}.fa-file-circle-xmark:before{content:"\e5a1"}.fa-temperature-arrow-up:before,.fa-temperature-up:before{content:"\e040"}.fa-medal:before{content:"\f5a2"}.fa-bed:before{content:"\f236"}.fa-h-square:before,.fa-square-h:before{content:"\f0fd"}.fa-podcast:before{content:"\f2ce"}.fa-temperature-4:before,.fa-temperature-full:before,.fa-thermometer-4:before,.fa-thermometer-full:before{content:"\f2c7"}.fa-bell:before{content:"\f0f3"}.fa-superscript:before{content:"\f12b"}.fa-plug-circle-xmark:before{content:"\e560"}.fa-star-of-life:before{content:"\f621"}.fa-phone-slash:before{content:"\f3dd"}.fa-paint-roller:before{content:"\f5aa"}.fa-hands-helping:before,.fa-handshake-angle:before{content:"\f4c4"}.fa-location-dot:before,.fa-map-marker-alt:before{content:"\f3c5"}.fa-file:before{content:"\f15b"}.fa-greater-than:before{content:"\3e"}.fa-person-swimming:before,.fa-swimmer:before{content:"\f5c4"}.fa-arrow-down:before{content:"\f063"}.fa-droplet:before,.fa-tint:before{content:"\f043"}.fa-eraser:before{content:"\f12d"}.fa-earth-america:before,.fa-earth-americas:before,.fa-earth:before,.fa-globe-americas:before{content:"\f57d"}.fa-person-burst:before{content:"\e53b"}.fa-dove:before{content:"\f4ba"}.fa-battery-0:before,.fa-battery-empty:before{content:"\f244"}.fa-socks:before{content:"\f696"}.fa-inbox:before{content:"\f01c"}.fa-section:before{content:"\e447"}.fa-gauge-high:before,.fa-tachometer-alt-fast:before,.fa-tachometer-alt:before{content:"\f625"}.fa-envelope-open-text:before{content:"\f658"}.fa-hospital-alt:before,.fa-hospital-wide:before,.fa-hospital:before{content:"\f0f8"}.fa-wine-bottle:before{content:"\f72f"}.fa-chess-rook:before{content:"\f447"}.fa-bars-staggered:before,.fa-reorder:before,.fa-stream:before{content:"\f550"}.fa-dharmachakra:before{content:"\f655"}.fa-hotdog:before{content:"\f80f"}.fa-blind:before,.fa-person-walking-with-cane:before{content:"\f29d"}.fa-drum:before{content:"\f569"}.fa-ice-cream:before{content:"\f810"}.fa-heart-circle-bolt:before{content:"\e4fc"}.fa-fax:before{content:"\f1ac"}.fa-paragraph:before{content:"\f1dd"}.fa-check-to-slot:before,.fa-vote-yea:before{content:"\f772"}.fa-star-half:before{content:"\f089"}.fa-boxes-alt:before,.fa-boxes-stacked:before,.fa-boxes:before{content:"\f468"}.fa-chain:before,.fa-link:before{content:"\f0c1"}.fa-assistive-listening-systems:before,.fa-ear-listen:before{content:"\f2a2"}.fa-tree-city:before{content:"\e587"}.fa-play:before{content:"\f04b"}.fa-font:before{content:"\f031"}.fa-table-cells-row-lock:before{content:"\e67a"}.fa-rupiah-sign:before{content:"\e23d"}.fa-magnifying-glass:before,.fa-search:before{content:"\f002"}.fa-ping-pong-paddle-ball:before,.fa-table-tennis-paddle-ball:before,.fa-table-tennis:before{content:"\f45d"}.fa-diagnoses:before,.fa-person-dots-from-line:before{content:"\f470"}.fa-trash-can-arrow-up:before,.fa-trash-restore-alt:before{content:"\f82a"}.fa-naira-sign:before{content:"\e1f6"}.fa-cart-arrow-down:before{content:"\f218"}.fa-walkie-talkie:before{content:"\f8ef"}.fa-file-edit:before,.fa-file-pen:before{content:"\f31c"}.fa-receipt:before{content:"\f543"}.fa-pen-square:before,.fa-pencil-square:before,.fa-square-pen:before{content:"\f14b"}.fa-suitcase-rolling:before{content:"\f5c1"}.fa-person-circle-exclamation:before{content:"\e53f"}.fa-chevron-down:before{content:"\f078"}.fa-battery-5:before,.fa-battery-full:before,.fa-battery:before{content:"\f240"}.fa-skull-crossbones:before{content:"\f714"}.fa-code-compare:before{content:"\e13a"}.fa-list-dots:before,.fa-list-ul:before{content:"\f0ca"}.fa-school-lock:before{content:"\e56f"}.fa-tower-cell:before{content:"\e585"}.fa-down-long:before,.fa-long-arrow-alt-down:before{content:"\f309"}.fa-ranking-star:before{content:"\e561"}.fa-chess-king:before{content:"\f43f"}.fa-person-harassing:before{content:"\e549"}.fa-brazilian-real-sign:before{content:"\e46c"}.fa-landmark-alt:before,.fa-landmark-dome:before{content:"\f752"}.fa-arrow-up:before{content:"\f062"}.fa-television:before,.fa-tv-alt:before,.fa-tv:before{content:"\f26c"}.fa-shrimp:before{content:"\e448"}.fa-list-check:before,.fa-tasks:before{content:"\f0ae"}.fa-jug-detergent:before{content:"\e519"}.fa-circle-user:before,.fa-user-circle:before{content:"\f2bd"}.fa-user-shield:before{content:"\f505"}.fa-wind:before{content:"\f72e"}.fa-car-burst:before,.fa-car-crash:before{content:"\f5e1"}.fa-y:before{content:"\59"}.fa-person-snowboarding:before,.fa-snowboarding:before{content:"\f7ce"}.fa-shipping-fast:before,.fa-truck-fast:before{content:"\f48b"}.fa-fish:before{content:"\f578"}.fa-user-graduate:before{content:"\f501"}.fa-adjust:before,.fa-circle-half-stroke:before{content:"\f042"}.fa-clapperboard:before{content:"\e131"}.fa-circle-radiation:before,.fa-radiation-alt:before{content:"\f7ba"}.fa-baseball-ball:before,.fa-baseball:before{content:"\f433"}.fa-jet-fighter-up:before{content:"\e518"}.fa-diagram-project:before,.fa-project-diagram:before{content:"\f542"}.fa-copy:before{content:"\f0c5"}.fa-volume-mute:before,.fa-volume-times:before,.fa-volume-xmark:before{content:"\f6a9"}.fa-hand-sparkles:before{content:"\e05d"}.fa-grip-horizontal:before,.fa-grip:before{content:"\f58d"}.fa-share-from-square:before,.fa-share-square:before{content:"\f14d"}.fa-child-combatant:before,.fa-child-rifle:before{content:"\e4e0"}.fa-gun:before{content:"\e19b"}.fa-phone-square:before,.fa-square-phone:before{content:"\f098"}.fa-add:before,.fa-plus:before{content:"\2b"}.fa-expand:before{content:"\f065"}.fa-computer:before{content:"\e4e5"}.fa-close:before,.fa-multiply:before,.fa-remove:before,.fa-times:before,.fa-xmark:before{content:"\f00d"}.fa-arrows-up-down-left-right:before,.fa-arrows:before{content:"\f047"}.fa-chalkboard-teacher:before,.fa-chalkboard-user:before{content:"\f51c"}.fa-peso-sign:before{content:"\e222"}.fa-building-shield:before{content:"\e4d8"}.fa-baby:before{content:"\f77c"}.fa-users-line:before{content:"\e592"}.fa-quote-left-alt:before,.fa-quote-left:before{content:"\f10d"}.fa-tractor:before{content:"\f722"}.fa-trash-arrow-up:before,.fa-trash-restore:before{content:"\f829"}.fa-arrow-down-up-lock:before{content:"\e4b0"}.fa-lines-leaning:before{content:"\e51e"}.fa-ruler-combined:before{content:"\f546"}.fa-copyright:before{content:"\f1f9"}.fa-equals:before{content:"\3d"}.fa-blender:before{content:"\f517"}.fa-teeth:before{content:"\f62e"}.fa-ils:before,.fa-shekel-sign:before,.fa-shekel:before,.fa-sheqel-sign:before,.fa-sheqel:before{content:"\f20b"}.fa-map:before{content:"\f279"}.fa-rocket:before{content:"\f135"}.fa-photo-film:before,.fa-photo-video:before{content:"\f87c"}.fa-folder-minus:before{content:"\f65d"}.fa-store:before{content:"\f54e"}.fa-arrow-trend-up:before{content:"\e098"}.fa-plug-circle-minus:before{content:"\e55e"}.fa-sign-hanging:before,.fa-sign:before{content:"\f4d9"}.fa-bezier-curve:before{content:"\f55b"}.fa-bell-slash:before{content:"\f1f6"}.fa-tablet-android:before,.fa-tablet:before{content:"\f3fb"}.fa-school-flag:before{content:"\e56e"}.fa-fill:before{content:"\f575"}.fa-angle-up:before{content:"\f106"}.fa-drumstick-bite:before{content:"\f6d7"}.fa-holly-berry:before{content:"\f7aa"}.fa-chevron-left:before{content:"\f053"}.fa-bacteria:before{content:"\e059"}.fa-hand-lizard:before{content:"\f258"}.fa-notdef:before{content:"\e1fe"}.fa-disease:before{content:"\f7fa"}.fa-briefcase-medical:before{content:"\f469"}.fa-genderless:before{content:"\f22d"}.fa-chevron-right:before{content:"\f054"}.fa-retweet:before{content:"\f079"}.fa-car-alt:before,.fa-car-rear:before{content:"\f5de"}.fa-pump-soap:before{content:"\e06b"}.fa-video-slash:before{content:"\f4e2"}.fa-battery-2:before,.fa-battery-quarter:before{content:"\f243"}.fa-radio:before{content:"\f8d7"}.fa-baby-carriage:before,.fa-carriage-baby:before{content:"\f77d"}.fa-traffic-light:before{content:"\f637"}.fa-thermometer:before{content:"\f491"}.fa-vr-cardboard:before{content:"\f729"}.fa-hand-middle-finger:before{content:"\f806"}.fa-percent:before,.fa-percentage:before{content:"\25"}.fa-truck-moving:before{content:"\f4df"}.fa-glass-water-droplet:before{content:"\e4f5"}.fa-display:before{content:"\e163"}.fa-face-smile:before,.fa-smile:before{content:"\f118"}.fa-thumb-tack:before,.fa-thumbtack:before{content:"\f08d"}.fa-trophy:before{content:"\f091"}.fa-person-praying:before,.fa-pray:before{content:"\f683"}.fa-hammer:before{content:"\f6e3"}.fa-hand-peace:before{content:"\f25b"}.fa-rotate:before,.fa-sync-alt:before{content:"\f2f1"}.fa-spinner:before{content:"\f110"}.fa-robot:before{content:"\f544"}.fa-peace:before{content:"\f67c"}.fa-cogs:before,.fa-gears:before{content:"\f085"}.fa-warehouse:before{content:"\f494"}.fa-arrow-up-right-dots:before{content:"\e4b7"}.fa-splotch:before{content:"\f5bc"}.fa-face-grin-hearts:before,.fa-grin-hearts:before{content:"\f584"}.fa-dice-four:before{content:"\f524"}.fa-sim-card:before{content:"\f7c4"}.fa-transgender-alt:before,.fa-transgender:before{content:"\f225"}.fa-mercury:before{content:"\f223"}.fa-arrow-turn-down:before,.fa-level-down:before{content:"\f149"}.fa-person-falling-burst:before{content:"\e547"}.fa-award:before{content:"\f559"}.fa-ticket-alt:before,.fa-ticket-simple:before{content:"\f3ff"}.fa-building:before{content:"\f1ad"}.fa-angle-double-left:before,.fa-angles-left:before{content:"\f100"}.fa-qrcode:before{content:"\f029"}.fa-clock-rotate-left:before,.fa-history:before{content:"\f1da"}.fa-face-grin-beam-sweat:before,.fa-grin-beam-sweat:before{content:"\f583"}.fa-arrow-right-from-file:before,.fa-file-export:before{content:"\f56e"}.fa-shield-blank:before,.fa-shield:before{content:"\f132"}.fa-arrow-up-short-wide:before,.fa-sort-amount-up-alt:before{content:"\f885"}.fa-house-medical:before{content:"\e3b2"}.fa-golf-ball-tee:before,.fa-golf-ball:before{content:"\f450"}.fa-chevron-circle-left:before,.fa-circle-chevron-left:before{content:"\f137"}.fa-house-chimney-window:before{content:"\e00d"}.fa-pen-nib:before{content:"\f5ad"}.fa-tent-arrow-turn-left:before{content:"\e580"}.fa-tents:before{content:"\e582"}.fa-magic:before,.fa-wand-magic:before{content:"\f0d0"}.fa-dog:before{content:"\f6d3"}.fa-carrot:before{content:"\f787"}.fa-moon:before{content:"\f186"}.fa-wine-glass-alt:before,.fa-wine-glass-empty:before{content:"\f5ce"}.fa-cheese:before{content:"\f7ef"}.fa-yin-yang:before{content:"\f6ad"}.fa-music:before{content:"\f001"}.fa-code-commit:before{content:"\f386"}.fa-temperature-low:before{content:"\f76b"}.fa-biking:before,.fa-person-biking:before{content:"\f84a"}.fa-broom:before{content:"\f51a"}.fa-shield-heart:before{content:"\e574"}.fa-gopuram:before{content:"\f664"}.fa-earth-oceania:before,.fa-globe-oceania:before{content:"\e47b"}.fa-square-xmark:before,.fa-times-square:before,.fa-xmark-square:before{content:"\f2d3"}.fa-hashtag:before{content:"\23"}.fa-expand-alt:before,.fa-up-right-and-down-left-from-center:before{content:"\f424"}.fa-oil-can:before{content:"\f613"}.fa-t:before{content:"\54"}.fa-hippo:before{content:"\f6ed"}.fa-chart-column:before{content:"\e0e3"}.fa-infinity:before{content:"\f534"}.fa-vial-circle-check:before{content:"\e596"}.fa-person-arrow-down-to-line:before{content:"\e538"}.fa-voicemail:before{content:"\f897"}.fa-fan:before{content:"\f863"}.fa-person-walking-luggage:before{content:"\e554"}.fa-arrows-alt-v:before,.fa-up-down:before{content:"\f338"}.fa-cloud-moon-rain:before{content:"\f73c"}.fa-calendar:before{content:"\f133"}.fa-trailer:before{content:"\e041"}.fa-bahai:before,.fa-haykal:before{content:"\f666"}.fa-sd-card:before{content:"\f7c2"}.fa-dragon:before{content:"\f6d5"}.fa-shoe-prints:before{content:"\f54b"}.fa-circle-plus:before,.fa-plus-circle:before{content:"\f055"}.fa-face-grin-tongue-wink:before,.fa-grin-tongue-wink:before{content:"\f58b"}.fa-hand-holding:before{content:"\f4bd"}.fa-plug-circle-exclamation:before{content:"\e55d"}.fa-chain-broken:before,.fa-chain-slash:before,.fa-link-slash:before,.fa-unlink:before{content:"\f127"}.fa-clone:before{content:"\f24d"}.fa-person-walking-arrow-loop-left:before{content:"\e551"}.fa-arrow-up-z-a:before,.fa-sort-alpha-up-alt:before{content:"\f882"}.fa-fire-alt:before,.fa-fire-flame-curved:before{content:"\f7e4"}.fa-tornado:before{content:"\f76f"}.fa-file-circle-plus:before{content:"\e494"}.fa-book-quran:before,.fa-quran:before{content:"\f687"}.fa-anchor:before{content:"\f13d"}.fa-border-all:before{content:"\f84c"}.fa-angry:before,.fa-face-angry:before{content:"\f556"}.fa-cookie-bite:before{content:"\f564"}.fa-arrow-trend-down:before{content:"\e097"}.fa-feed:before,.fa-rss:before{content:"\f09e"}.fa-draw-polygon:before{content:"\f5ee"}.fa-balance-scale:before,.fa-scale-balanced:before{content:"\f24e"}.fa-gauge-simple-high:before,.fa-tachometer-fast:before,.fa-tachometer:before{content:"\f62a"}.fa-shower:before{content:"\f2cc"}.fa-desktop-alt:before,.fa-desktop:before{content:"\f390"}.fa-m:before{content:"\4d"}.fa-table-list:before,.fa-th-list:before{content:"\f00b"}.fa-comment-sms:before,.fa-sms:before{content:"\f7cd"}.fa-book:before{content:"\f02d"}.fa-user-plus:before{content:"\f234"}.fa-check:before{content:"\f00c"}.fa-battery-4:before,.fa-battery-three-quarters:before{content:"\f241"}.fa-house-circle-check:before{content:"\e509"}.fa-angle-left:before{content:"\f104"}.fa-diagram-successor:before{content:"\e47a"}.fa-truck-arrow-right:before{content:"\e58b"}.fa-arrows-split-up-and-left:before{content:"\e4bc"}.fa-fist-raised:before,.fa-hand-fist:before{content:"\f6de"}.fa-cloud-moon:before{content:"\f6c3"}.fa-briefcase:before{content:"\f0b1"}.fa-person-falling:before{content:"\e546"}.fa-image-portrait:before,.fa-portrait:before{content:"\f3e0"}.fa-user-tag:before{content:"\f507"}.fa-rug:before{content:"\e569"}.fa-earth-europe:before,.fa-globe-europe:before{content:"\f7a2"}.fa-cart-flatbed-suitcase:before,.fa-luggage-cart:before{content:"\f59d"}.fa-rectangle-times:before,.fa-rectangle-xmark:before,.fa-times-rectangle:before,.fa-window-close:before{content:"\f410"}.fa-baht-sign:before{content:"\e0ac"}.fa-book-open:before{content:"\f518"}.fa-book-journal-whills:before,.fa-journal-whills:before{content:"\f66a"}.fa-handcuffs:before{content:"\e4f8"}.fa-exclamation-triangle:before,.fa-triangle-exclamation:before,.fa-warning:before{content:"\f071"}.fa-database:before{content:"\f1c0"}.fa-mail-forward:before,.fa-share:before{content:"\f064"}.fa-bottle-droplet:before{content:"\e4c4"}.fa-mask-face:before{content:"\e1d7"}.fa-hill-rockslide:before{content:"\e508"}.fa-exchange-alt:before,.fa-right-left:before{content:"\f362"}.fa-paper-plane:before{content:"\f1d8"}.fa-road-circle-exclamation:before{content:"\e565"}.fa-dungeon:before{content:"\f6d9"}.fa-align-right:before{content:"\f038"}.fa-money-bill-1-wave:before,.fa-money-bill-wave-alt:before{content:"\f53b"}.fa-life-ring:before{content:"\f1cd"}.fa-hands:before,.fa-sign-language:before,.fa-signing:before{content:"\f2a7"}.fa-calendar-day:before{content:"\f783"}.fa-ladder-water:before,.fa-swimming-pool:before,.fa-water-ladder:before{content:"\f5c5"}.fa-arrows-up-down:before,.fa-arrows-v:before{content:"\f07d"}.fa-face-grimace:before,.fa-grimace:before{content:"\f57f"}.fa-wheelchair-alt:before,.fa-wheelchair-move:before{content:"\e2ce"}.fa-level-down-alt:before,.fa-turn-down:before{content:"\f3be"}.fa-person-walking-arrow-right:before{content:"\e552"}.fa-envelope-square:before,.fa-square-envelope:before{content:"\f199"}.fa-dice:before{content:"\f522"}.fa-bowling-ball:before{content:"\f436"}.fa-brain:before{content:"\f5dc"}.fa-band-aid:before,.fa-bandage:before{content:"\f462"}.fa-calendar-minus:before{content:"\f272"}.fa-circle-xmark:before,.fa-times-circle:before,.fa-xmark-circle:before{content:"\f057"}.fa-gifts:before{content:"\f79c"}.fa-hotel:before{content:"\f594"}.fa-earth-asia:before,.fa-globe-asia:before{content:"\f57e"}.fa-id-card-alt:before,.fa-id-card-clip:before{content:"\f47f"}.fa-magnifying-glass-plus:before,.fa-search-plus:before{content:"\f00e"}.fa-thumbs-up:before{content:"\f164"}.fa-user-clock:before{content:"\f4fd"}.fa-allergies:before,.fa-hand-dots:before{content:"\f461"}.fa-file-invoice:before{content:"\f570"}.fa-window-minimize:before{content:"\f2d1"}.fa-coffee:before,.fa-mug-saucer:before{content:"\f0f4"}.fa-brush:before{content:"\f55d"}.fa-mask:before{content:"\f6fa"}.fa-magnifying-glass-minus:before,.fa-search-minus:before{content:"\f010"}.fa-ruler-vertical:before{content:"\f548"}.fa-user-alt:before,.fa-user-large:before{content:"\f406"}.fa-train-tram:before{content:"\e5b4"}.fa-user-nurse:before{content:"\f82f"}.fa-syringe:before{content:"\f48e"}.fa-cloud-sun:before{content:"\f6c4"}.fa-stopwatch-20:before{content:"\e06f"}.fa-square-full:before{content:"\f45c"}.fa-magnet:before{content:"\f076"}.fa-jar:before{content:"\e516"}.fa-note-sticky:before,.fa-sticky-note:before{content:"\f249"}.fa-bug-slash:before{content:"\e490"}.fa-arrow-up-from-water-pump:before{content:"\e4b6"}.fa-bone:before{content:"\f5d7"}.fa-user-injured:before{content:"\f728"}.fa-face-sad-tear:before,.fa-sad-tear:before{content:"\f5b4"}.fa-plane:before{content:"\f072"}.fa-tent-arrows-down:before{content:"\e581"}.fa-exclamation:before{content:"\21"}.fa-arrows-spin:before{content:"\e4bb"}.fa-print:before{content:"\f02f"}.fa-try:before,.fa-turkish-lira-sign:before,.fa-turkish-lira:before{content:"\e2bb"}.fa-dollar-sign:before,.fa-dollar:before,.fa-usd:before{content:"\24"}.fa-x:before{content:"\58"}.fa-magnifying-glass-dollar:before,.fa-search-dollar:before{content:"\f688"}.fa-users-cog:before,.fa-users-gear:before{content:"\f509"}.fa-person-military-pointing:before{content:"\e54a"}.fa-bank:before,.fa-building-columns:before,.fa-institution:before,.fa-museum:before,.fa-university:before{content:"\f19c"}.fa-umbrella:before{content:"\f0e9"}.fa-trowel:before{content:"\e589"}.fa-d:before{content:"\44"}.fa-stapler:before{content:"\e5af"}.fa-masks-theater:before,.fa-theater-masks:before{content:"\f630"}.fa-kip-sign:before{content:"\e1c4"}.fa-hand-point-left:before{content:"\f0a5"}.fa-handshake-alt:before,.fa-handshake-simple:before{content:"\f4c6"}.fa-fighter-jet:before,.fa-jet-fighter:before{content:"\f0fb"}.fa-share-alt-square:before,.fa-square-share-nodes:before{content:"\f1e1"}.fa-barcode:before{content:"\f02a"}.fa-plus-minus:before{content:"\e43c"}.fa-video-camera:before,.fa-video:before{content:"\f03d"}.fa-graduation-cap:before,.fa-mortar-board:before{content:"\f19d"}.fa-hand-holding-medical:before{content:"\e05c"}.fa-person-circle-check:before{content:"\e53e"}.fa-level-up-alt:before,.fa-turn-up:before{content:"\f3bf"} -.fa-sr-only,.fa-sr-only-focusable:not(:focus),.sr-only,.sr-only-focusable:not(:focus){position:absolute;width:1px;height:1px;padding:0;margin:-1px;overflow:hidden;clip:rect(0,0,0,0);white-space:nowrap;border-width:0}:host,:root{--fa-style-family-brands:"Font Awesome 6 Brands";--fa-font-brands:normal 400 1em/1 "Font Awesome 6 Brands"}@font-face{font-family:"Font Awesome 6 Brands";font-style:normal;font-weight:400;font-display:block;src:url(../webfonts/fa-brands-400.woff2) format("woff2"),url(../webfonts/fa-brands-400.ttf) format("truetype")}.fa-brands,.fab{font-weight:400}.fa-monero:before{content:"\f3d0"}.fa-hooli:before{content:"\f427"}.fa-yelp:before{content:"\f1e9"}.fa-cc-visa:before{content:"\f1f0"}.fa-lastfm:before{content:"\f202"}.fa-shopware:before{content:"\f5b5"}.fa-creative-commons-nc:before{content:"\f4e8"}.fa-aws:before{content:"\f375"}.fa-redhat:before{content:"\f7bc"}.fa-yoast:before{content:"\f2b1"}.fa-cloudflare:before{content:"\e07d"}.fa-ups:before{content:"\f7e0"}.fa-pixiv:before{content:"\e640"}.fa-wpexplorer:before{content:"\f2de"}.fa-dyalog:before{content:"\f399"}.fa-bity:before{content:"\f37a"}.fa-stackpath:before{content:"\f842"}.fa-buysellads:before{content:"\f20d"}.fa-first-order:before{content:"\f2b0"}.fa-modx:before{content:"\f285"}.fa-guilded:before{content:"\e07e"}.fa-vnv:before{content:"\f40b"}.fa-js-square:before,.fa-square-js:before{content:"\f3b9"}.fa-microsoft:before{content:"\f3ca"}.fa-qq:before{content:"\f1d6"}.fa-orcid:before{content:"\f8d2"}.fa-java:before{content:"\f4e4"}.fa-invision:before{content:"\f7b0"}.fa-creative-commons-pd-alt:before{content:"\f4ed"}.fa-centercode:before{content:"\f380"}.fa-glide-g:before{content:"\f2a6"}.fa-drupal:before{content:"\f1a9"}.fa-jxl:before{content:"\e67b"}.fa-hire-a-helper:before{content:"\f3b0"}.fa-creative-commons-by:before{content:"\f4e7"}.fa-unity:before{content:"\e049"}.fa-whmcs:before{content:"\f40d"}.fa-rocketchat:before{content:"\f3e8"}.fa-vk:before{content:"\f189"}.fa-untappd:before{content:"\f405"}.fa-mailchimp:before{content:"\f59e"}.fa-css3-alt:before{content:"\f38b"}.fa-reddit-square:before,.fa-square-reddit:before{content:"\f1a2"}.fa-vimeo-v:before{content:"\f27d"}.fa-contao:before{content:"\f26d"}.fa-square-font-awesome:before{content:"\e5ad"}.fa-deskpro:before{content:"\f38f"}.fa-brave:before{content:"\e63c"}.fa-sistrix:before{content:"\f3ee"}.fa-instagram-square:before,.fa-square-instagram:before{content:"\e055"}.fa-battle-net:before{content:"\f835"}.fa-the-red-yeti:before{content:"\f69d"}.fa-hacker-news-square:before,.fa-square-hacker-news:before{content:"\f3af"}.fa-edge:before{content:"\f282"}.fa-threads:before{content:"\e618"}.fa-napster:before{content:"\f3d2"}.fa-snapchat-square:before,.fa-square-snapchat:before{content:"\f2ad"}.fa-google-plus-g:before{content:"\f0d5"}.fa-artstation:before{content:"\f77a"}.fa-markdown:before{content:"\f60f"}.fa-sourcetree:before{content:"\f7d3"}.fa-google-plus:before{content:"\f2b3"}.fa-diaspora:before{content:"\f791"}.fa-foursquare:before{content:"\f180"}.fa-stack-overflow:before{content:"\f16c"}.fa-github-alt:before{content:"\f113"}.fa-phoenix-squadron:before{content:"\f511"}.fa-pagelines:before{content:"\f18c"}.fa-algolia:before{content:"\f36c"}.fa-red-river:before{content:"\f3e3"}.fa-creative-commons-sa:before{content:"\f4ef"}.fa-safari:before{content:"\f267"}.fa-google:before{content:"\f1a0"}.fa-font-awesome-alt:before,.fa-square-font-awesome-stroke:before{content:"\f35c"}.fa-atlassian:before{content:"\f77b"}.fa-linkedin-in:before{content:"\f0e1"}.fa-digital-ocean:before{content:"\f391"}.fa-nimblr:before{content:"\f5a8"}.fa-chromecast:before{content:"\f838"}.fa-evernote:before{content:"\f839"}.fa-hacker-news:before{content:"\f1d4"}.fa-creative-commons-sampling:before{content:"\f4f0"}.fa-adversal:before{content:"\f36a"}.fa-creative-commons:before{content:"\f25e"}.fa-watchman-monitoring:before{content:"\e087"}.fa-fonticons:before{content:"\f280"}.fa-weixin:before{content:"\f1d7"}.fa-shirtsinbulk:before{content:"\f214"}.fa-codepen:before{content:"\f1cb"}.fa-git-alt:before{content:"\f841"}.fa-lyft:before{content:"\f3c3"}.fa-rev:before{content:"\f5b2"}.fa-windows:before{content:"\f17a"}.fa-wizards-of-the-coast:before{content:"\f730"}.fa-square-viadeo:before,.fa-viadeo-square:before{content:"\f2aa"}.fa-meetup:before{content:"\f2e0"}.fa-centos:before{content:"\f789"}.fa-adn:before{content:"\f170"}.fa-cloudsmith:before{content:"\f384"}.fa-opensuse:before{content:"\e62b"}.fa-pied-piper-alt:before{content:"\f1a8"}.fa-dribbble-square:before,.fa-square-dribbble:before{content:"\f397"}.fa-codiepie:before{content:"\f284"}.fa-node:before{content:"\f419"}.fa-mix:before{content:"\f3cb"}.fa-steam:before{content:"\f1b6"}.fa-cc-apple-pay:before{content:"\f416"}.fa-scribd:before{content:"\f28a"}.fa-debian:before{content:"\e60b"}.fa-openid:before{content:"\f19b"}.fa-instalod:before{content:"\e081"}.fa-expeditedssl:before{content:"\f23e"}.fa-sellcast:before{content:"\f2da"}.fa-square-twitter:before,.fa-twitter-square:before{content:"\f081"}.fa-r-project:before{content:"\f4f7"}.fa-delicious:before{content:"\f1a5"}.fa-freebsd:before{content:"\f3a4"}.fa-vuejs:before{content:"\f41f"}.fa-accusoft:before{content:"\f369"}.fa-ioxhost:before{content:"\f208"}.fa-fonticons-fi:before{content:"\f3a2"}.fa-app-store:before{content:"\f36f"}.fa-cc-mastercard:before{content:"\f1f1"}.fa-itunes-note:before{content:"\f3b5"}.fa-golang:before{content:"\e40f"}.fa-kickstarter:before,.fa-square-kickstarter:before{content:"\f3bb"}.fa-grav:before{content:"\f2d6"}.fa-weibo:before{content:"\f18a"}.fa-uncharted:before{content:"\e084"}.fa-firstdraft:before{content:"\f3a1"}.fa-square-youtube:before,.fa-youtube-square:before{content:"\f431"}.fa-wikipedia-w:before{content:"\f266"}.fa-rendact:before,.fa-wpressr:before{content:"\f3e4"}.fa-angellist:before{content:"\f209"}.fa-galactic-republic:before{content:"\f50c"}.fa-nfc-directional:before{content:"\e530"}.fa-skype:before{content:"\f17e"}.fa-joget:before{content:"\f3b7"}.fa-fedora:before{content:"\f798"}.fa-stripe-s:before{content:"\f42a"}.fa-meta:before{content:"\e49b"}.fa-laravel:before{content:"\f3bd"}.fa-hotjar:before{content:"\f3b1"}.fa-bluetooth-b:before{content:"\f294"}.fa-square-letterboxd:before{content:"\e62e"}.fa-sticker-mule:before{content:"\f3f7"}.fa-creative-commons-zero:before{content:"\f4f3"}.fa-hips:before{content:"\f452"}.fa-behance:before{content:"\f1b4"}.fa-reddit:before{content:"\f1a1"}.fa-discord:before{content:"\f392"}.fa-chrome:before{content:"\f268"}.fa-app-store-ios:before{content:"\f370"}.fa-cc-discover:before{content:"\f1f2"}.fa-wpbeginner:before{content:"\f297"}.fa-confluence:before{content:"\f78d"}.fa-shoelace:before{content:"\e60c"}.fa-mdb:before{content:"\f8ca"}.fa-dochub:before{content:"\f394"}.fa-accessible-icon:before{content:"\f368"}.fa-ebay:before{content:"\f4f4"}.fa-amazon:before{content:"\f270"}.fa-unsplash:before{content:"\e07c"}.fa-yarn:before{content:"\f7e3"}.fa-square-steam:before,.fa-steam-square:before{content:"\f1b7"}.fa-500px:before{content:"\f26e"}.fa-square-vimeo:before,.fa-vimeo-square:before{content:"\f194"}.fa-asymmetrik:before{content:"\f372"}.fa-font-awesome-flag:before,.fa-font-awesome-logo-full:before,.fa-font-awesome:before{content:"\f2b4"}.fa-gratipay:before{content:"\f184"}.fa-apple:before{content:"\f179"}.fa-hive:before{content:"\e07f"}.fa-gitkraken:before{content:"\f3a6"}.fa-keybase:before{content:"\f4f5"}.fa-apple-pay:before{content:"\f415"}.fa-padlet:before{content:"\e4a0"}.fa-amazon-pay:before{content:"\f42c"}.fa-github-square:before,.fa-square-github:before{content:"\f092"}.fa-stumbleupon:before{content:"\f1a4"}.fa-fedex:before{content:"\f797"}.fa-phoenix-framework:before{content:"\f3dc"}.fa-shopify:before{content:"\e057"}.fa-neos:before{content:"\f612"}.fa-square-threads:before{content:"\e619"}.fa-hackerrank:before{content:"\f5f7"}.fa-researchgate:before{content:"\f4f8"}.fa-swift:before{content:"\f8e1"}.fa-angular:before{content:"\f420"}.fa-speakap:before{content:"\f3f3"}.fa-angrycreative:before{content:"\f36e"}.fa-y-combinator:before{content:"\f23b"}.fa-empire:before{content:"\f1d1"}.fa-envira:before{content:"\f299"}.fa-google-scholar:before{content:"\e63b"}.fa-gitlab-square:before,.fa-square-gitlab:before{content:"\e5ae"}.fa-studiovinari:before{content:"\f3f8"}.fa-pied-piper:before{content:"\f2ae"}.fa-wordpress:before{content:"\f19a"}.fa-product-hunt:before{content:"\f288"}.fa-firefox:before{content:"\f269"}.fa-linode:before{content:"\f2b8"}.fa-goodreads:before{content:"\f3a8"}.fa-odnoklassniki-square:before,.fa-square-odnoklassniki:before{content:"\f264"}.fa-jsfiddle:before{content:"\f1cc"}.fa-sith:before{content:"\f512"}.fa-themeisle:before{content:"\f2b2"}.fa-page4:before{content:"\f3d7"}.fa-hashnode:before{content:"\e499"}.fa-react:before{content:"\f41b"}.fa-cc-paypal:before{content:"\f1f4"}.fa-squarespace:before{content:"\f5be"}.fa-cc-stripe:before{content:"\f1f5"}.fa-creative-commons-share:before{content:"\f4f2"}.fa-bitcoin:before{content:"\f379"}.fa-keycdn:before{content:"\f3ba"}.fa-opera:before{content:"\f26a"}.fa-itch-io:before{content:"\f83a"}.fa-umbraco:before{content:"\f8e8"}.fa-galactic-senate:before{content:"\f50d"}.fa-ubuntu:before{content:"\f7df"}.fa-draft2digital:before{content:"\f396"}.fa-stripe:before{content:"\f429"}.fa-houzz:before{content:"\f27c"}.fa-gg:before{content:"\f260"}.fa-dhl:before{content:"\f790"}.fa-pinterest-square:before,.fa-square-pinterest:before{content:"\f0d3"}.fa-xing:before{content:"\f168"}.fa-blackberry:before{content:"\f37b"}.fa-creative-commons-pd:before{content:"\f4ec"}.fa-playstation:before{content:"\f3df"}.fa-quinscape:before{content:"\f459"}.fa-less:before{content:"\f41d"}.fa-blogger-b:before{content:"\f37d"}.fa-opencart:before{content:"\f23d"}.fa-vine:before{content:"\f1ca"}.fa-signal-messenger:before{content:"\e663"}.fa-paypal:before{content:"\f1ed"}.fa-gitlab:before{content:"\f296"}.fa-typo3:before{content:"\f42b"}.fa-reddit-alien:before{content:"\f281"}.fa-yahoo:before{content:"\f19e"}.fa-dailymotion:before{content:"\e052"}.fa-affiliatetheme:before{content:"\f36b"}.fa-pied-piper-pp:before{content:"\f1a7"}.fa-bootstrap:before{content:"\f836"}.fa-odnoklassniki:before{content:"\f263"}.fa-nfc-symbol:before{content:"\e531"}.fa-mintbit:before{content:"\e62f"}.fa-ethereum:before{content:"\f42e"}.fa-speaker-deck:before{content:"\f83c"}.fa-creative-commons-nc-eu:before{content:"\f4e9"}.fa-patreon:before{content:"\f3d9"}.fa-avianex:before{content:"\f374"}.fa-ello:before{content:"\f5f1"}.fa-gofore:before{content:"\f3a7"}.fa-bimobject:before{content:"\f378"}.fa-brave-reverse:before{content:"\e63d"}.fa-facebook-f:before{content:"\f39e"}.fa-google-plus-square:before,.fa-square-google-plus:before{content:"\f0d4"}.fa-web-awesome:before{content:"\e682"}.fa-mandalorian:before{content:"\f50f"}.fa-first-order-alt:before{content:"\f50a"}.fa-osi:before{content:"\f41a"}.fa-google-wallet:before{content:"\f1ee"}.fa-d-and-d-beyond:before{content:"\f6ca"}.fa-periscope:before{content:"\f3da"}.fa-fulcrum:before{content:"\f50b"}.fa-cloudscale:before{content:"\f383"}.fa-forumbee:before{content:"\f211"}.fa-mizuni:before{content:"\f3cc"}.fa-schlix:before{content:"\f3ea"}.fa-square-xing:before,.fa-xing-square:before{content:"\f169"}.fa-bandcamp:before{content:"\f2d5"}.fa-wpforms:before{content:"\f298"}.fa-cloudversify:before{content:"\f385"}.fa-usps:before{content:"\f7e1"}.fa-megaport:before{content:"\f5a3"}.fa-magento:before{content:"\f3c4"}.fa-spotify:before{content:"\f1bc"}.fa-optin-monster:before{content:"\f23c"}.fa-fly:before{content:"\f417"}.fa-aviato:before{content:"\f421"}.fa-itunes:before{content:"\f3b4"}.fa-cuttlefish:before{content:"\f38c"}.fa-blogger:before{content:"\f37c"}.fa-flickr:before{content:"\f16e"}.fa-viber:before{content:"\f409"}.fa-soundcloud:before{content:"\f1be"}.fa-digg:before{content:"\f1a6"}.fa-tencent-weibo:before{content:"\f1d5"}.fa-letterboxd:before{content:"\e62d"}.fa-symfony:before{content:"\f83d"}.fa-maxcdn:before{content:"\f136"}.fa-etsy:before{content:"\f2d7"}.fa-facebook-messenger:before{content:"\f39f"}.fa-audible:before{content:"\f373"}.fa-think-peaks:before{content:"\f731"}.fa-bilibili:before{content:"\e3d9"}.fa-erlang:before{content:"\f39d"}.fa-x-twitter:before{content:"\e61b"}.fa-cotton-bureau:before{content:"\f89e"}.fa-dashcube:before{content:"\f210"}.fa-42-group:before,.fa-innosoft:before{content:"\e080"}.fa-stack-exchange:before{content:"\f18d"}.fa-elementor:before{content:"\f430"}.fa-pied-piper-square:before,.fa-square-pied-piper:before{content:"\e01e"}.fa-creative-commons-nd:before{content:"\f4eb"}.fa-palfed:before{content:"\f3d8"}.fa-superpowers:before{content:"\f2dd"}.fa-resolving:before{content:"\f3e7"}.fa-xbox:before{content:"\f412"}.fa-square-web-awesome-stroke:before{content:"\e684"}.fa-searchengin:before{content:"\f3eb"}.fa-tiktok:before{content:"\e07b"}.fa-facebook-square:before,.fa-square-facebook:before{content:"\f082"}.fa-renren:before{content:"\f18b"}.fa-linux:before{content:"\f17c"}.fa-glide:before{content:"\f2a5"}.fa-linkedin:before{content:"\f08c"}.fa-hubspot:before{content:"\f3b2"}.fa-deploydog:before{content:"\f38e"}.fa-twitch:before{content:"\f1e8"}.fa-ravelry:before{content:"\f2d9"}.fa-mixer:before{content:"\e056"}.fa-lastfm-square:before,.fa-square-lastfm:before{content:"\f203"}.fa-vimeo:before{content:"\f40a"}.fa-mendeley:before{content:"\f7b3"}.fa-uniregistry:before{content:"\f404"}.fa-figma:before{content:"\f799"}.fa-creative-commons-remix:before{content:"\f4ee"}.fa-cc-amazon-pay:before{content:"\f42d"}.fa-dropbox:before{content:"\f16b"}.fa-instagram:before{content:"\f16d"}.fa-cmplid:before{content:"\e360"}.fa-upwork:before{content:"\e641"}.fa-facebook:before{content:"\f09a"}.fa-gripfire:before{content:"\f3ac"}.fa-jedi-order:before{content:"\f50e"}.fa-uikit:before{content:"\f403"}.fa-fort-awesome-alt:before{content:"\f3a3"}.fa-phabricator:before{content:"\f3db"}.fa-ussunnah:before{content:"\f407"}.fa-earlybirds:before{content:"\f39a"}.fa-trade-federation:before{content:"\f513"}.fa-autoprefixer:before{content:"\f41c"}.fa-whatsapp:before{content:"\f232"}.fa-square-upwork:before{content:"\e67c"}.fa-slideshare:before{content:"\f1e7"}.fa-google-play:before{content:"\f3ab"}.fa-viadeo:before{content:"\f2a9"}.fa-line:before{content:"\f3c0"}.fa-google-drive:before{content:"\f3aa"}.fa-servicestack:before{content:"\f3ec"}.fa-simplybuilt:before{content:"\f215"}.fa-bitbucket:before{content:"\f171"}.fa-imdb:before{content:"\f2d8"}.fa-deezer:before{content:"\e077"}.fa-raspberry-pi:before{content:"\f7bb"}.fa-jira:before{content:"\f7b1"}.fa-docker:before{content:"\f395"}.fa-screenpal:before{content:"\e570"}.fa-bluetooth:before{content:"\f293"}.fa-gitter:before{content:"\f426"}.fa-d-and-d:before{content:"\f38d"}.fa-microblog:before{content:"\e01a"}.fa-cc-diners-club:before{content:"\f24c"}.fa-gg-circle:before{content:"\f261"}.fa-pied-piper-hat:before{content:"\f4e5"}.fa-kickstarter-k:before{content:"\f3bc"}.fa-yandex:before{content:"\f413"}.fa-readme:before{content:"\f4d5"}.fa-html5:before{content:"\f13b"}.fa-sellsy:before{content:"\f213"}.fa-square-web-awesome:before{content:"\e683"}.fa-sass:before{content:"\f41e"}.fa-wirsindhandwerk:before,.fa-wsh:before{content:"\e2d0"}.fa-buromobelexperte:before{content:"\f37f"}.fa-salesforce:before{content:"\f83b"}.fa-octopus-deploy:before{content:"\e082"}.fa-medapps:before{content:"\f3c6"}.fa-ns8:before{content:"\f3d5"}.fa-pinterest-p:before{content:"\f231"}.fa-apper:before{content:"\f371"}.fa-fort-awesome:before{content:"\f286"}.fa-waze:before{content:"\f83f"}.fa-bluesky:before{content:"\e671"}.fa-cc-jcb:before{content:"\f24b"}.fa-snapchat-ghost:before,.fa-snapchat:before{content:"\f2ab"}.fa-fantasy-flight-games:before{content:"\f6dc"}.fa-rust:before{content:"\e07a"}.fa-wix:before{content:"\f5cf"}.fa-behance-square:before,.fa-square-behance:before{content:"\f1b5"}.fa-supple:before{content:"\f3f9"}.fa-webflow:before{content:"\e65c"}.fa-rebel:before{content:"\f1d0"}.fa-css3:before{content:"\f13c"}.fa-staylinked:before{content:"\f3f5"}.fa-kaggle:before{content:"\f5fa"}.fa-space-awesome:before{content:"\e5ac"}.fa-deviantart:before{content:"\f1bd"}.fa-cpanel:before{content:"\f388"}.fa-goodreads-g:before{content:"\f3a9"}.fa-git-square:before,.fa-square-git:before{content:"\f1d2"}.fa-square-tumblr:before,.fa-tumblr-square:before{content:"\f174"}.fa-trello:before{content:"\f181"}.fa-creative-commons-nc-jp:before{content:"\f4ea"}.fa-get-pocket:before{content:"\f265"}.fa-perbyte:before{content:"\e083"}.fa-grunt:before{content:"\f3ad"}.fa-weebly:before{content:"\f5cc"}.fa-connectdevelop:before{content:"\f20e"}.fa-leanpub:before{content:"\f212"}.fa-black-tie:before{content:"\f27e"}.fa-themeco:before{content:"\f5c6"}.fa-python:before{content:"\f3e2"}.fa-android:before{content:"\f17b"}.fa-bots:before{content:"\e340"}.fa-free-code-camp:before{content:"\f2c5"}.fa-hornbill:before{content:"\f592"}.fa-js:before{content:"\f3b8"}.fa-ideal:before{content:"\e013"}.fa-git:before{content:"\f1d3"}.fa-dev:before{content:"\f6cc"}.fa-sketch:before{content:"\f7c6"}.fa-yandex-international:before{content:"\f414"}.fa-cc-amex:before{content:"\f1f3"}.fa-uber:before{content:"\f402"}.fa-github:before{content:"\f09b"}.fa-php:before{content:"\f457"}.fa-alipay:before{content:"\f642"}.fa-youtube:before{content:"\f167"}.fa-skyatlas:before{content:"\f216"}.fa-firefox-browser:before{content:"\e007"}.fa-replyd:before{content:"\f3e6"}.fa-suse:before{content:"\f7d6"}.fa-jenkins:before{content:"\f3b6"}.fa-twitter:before{content:"\f099"}.fa-rockrms:before{content:"\f3e9"}.fa-pinterest:before{content:"\f0d2"}.fa-buffer:before{content:"\f837"}.fa-npm:before{content:"\f3d4"}.fa-yammer:before{content:"\f840"}.fa-btc:before{content:"\f15a"}.fa-dribbble:before{content:"\f17d"}.fa-stumbleupon-circle:before{content:"\f1a3"}.fa-internet-explorer:before{content:"\f26b"}.fa-stubber:before{content:"\e5c7"}.fa-telegram-plane:before,.fa-telegram:before{content:"\f2c6"}.fa-old-republic:before{content:"\f510"}.fa-odysee:before{content:"\e5c6"}.fa-square-whatsapp:before,.fa-whatsapp-square:before{content:"\f40c"}.fa-node-js:before{content:"\f3d3"}.fa-edge-legacy:before{content:"\e078"}.fa-slack-hash:before,.fa-slack:before{content:"\f198"}.fa-medrt:before{content:"\f3c8"}.fa-usb:before{content:"\f287"}.fa-tumblr:before{content:"\f173"}.fa-vaadin:before{content:"\f408"}.fa-quora:before{content:"\f2c4"}.fa-square-x-twitter:before{content:"\e61a"}.fa-reacteurope:before{content:"\f75d"}.fa-medium-m:before,.fa-medium:before{content:"\f23a"}.fa-amilia:before{content:"\f36d"}.fa-mixcloud:before{content:"\f289"}.fa-flipboard:before{content:"\f44d"}.fa-viacoin:before{content:"\f237"}.fa-critical-role:before{content:"\f6c9"}.fa-sitrox:before{content:"\e44a"}.fa-discourse:before{content:"\f393"}.fa-joomla:before{content:"\f1aa"}.fa-mastodon:before{content:"\f4f6"}.fa-airbnb:before{content:"\f834"}.fa-wolf-pack-battalion:before{content:"\f514"}.fa-buy-n-large:before{content:"\f8a6"}.fa-gulp:before{content:"\f3ae"}.fa-creative-commons-sampling-plus:before{content:"\f4f1"}.fa-strava:before{content:"\f428"}.fa-ember:before{content:"\f423"}.fa-canadian-maple-leaf:before{content:"\f785"}.fa-teamspeak:before{content:"\f4f9"}.fa-pushed:before{content:"\f3e1"}.fa-wordpress-simple:before{content:"\f411"}.fa-nutritionix:before{content:"\f3d6"}.fa-wodu:before{content:"\e088"}.fa-google-pay:before{content:"\e079"}.fa-intercom:before{content:"\f7af"}.fa-zhihu:before{content:"\f63f"}.fa-korvue:before{content:"\f42f"}.fa-pix:before{content:"\e43a"}.fa-steam-symbol:before{content:"\f3f6"}:host,:root{--fa-font-regular:normal 400 1em/1 "Font Awesome 6 Free"}@font-face{font-family:"Font Awesome 6 Free";font-style:normal;font-weight:400;font-display:block;src:url(../webfonts/fa-regular-400.woff2) format("woff2"),url(../webfonts/fa-regular-400.ttf) format("truetype")}.fa-regular,.far{font-weight:400}:host,:root{--fa-style-family-classic:"Font Awesome 6 Free";--fa-font-solid:normal 900 1em/1 "Font Awesome 6 Free"}@font-face{font-family:"Font Awesome 6 Free";font-style:normal;font-weight:900;font-display:block;src:url(../webfonts/fa-solid-900.woff2) format("woff2"),url(../webfonts/fa-solid-900.ttf) format("truetype")}.fa-solid,.fas{font-weight:900}@font-face{font-family:"Font Awesome 5 Brands";font-display:block;font-weight:400;src:url(../webfonts/fa-brands-400.woff2) format("woff2"),url(../webfonts/fa-brands-400.ttf) format("truetype")}@font-face{font-family:"Font Awesome 5 Free";font-display:block;font-weight:900;src:url(../webfonts/fa-solid-900.woff2) format("woff2"),url(../webfonts/fa-solid-900.ttf) format("truetype")}@font-face{font-family:"Font Awesome 5 Free";font-display:block;font-weight:400;src:url(../webfonts/fa-regular-400.woff2) format("woff2"),url(../webfonts/fa-regular-400.ttf) format("truetype")}@font-face{font-family:"FontAwesome";font-display:block;src:url(../webfonts/fa-solid-900.woff2) format("woff2"),url(../webfonts/fa-solid-900.ttf) format("truetype")}@font-face{font-family:"FontAwesome";font-display:block;src:url(../webfonts/fa-brands-400.woff2) format("woff2"),url(../webfonts/fa-brands-400.ttf) format("truetype")}@font-face{font-family:"FontAwesome";font-display:block;src:url(../webfonts/fa-regular-400.woff2) format("woff2"),url(../webfonts/fa-regular-400.ttf) format("truetype");unicode-range:u+f003,u+f006,u+f014,u+f016-f017,u+f01a-f01b,u+f01d,u+f022,u+f03e,u+f044,u+f046,u+f05c-f05d,u+f06e,u+f070,u+f087-f088,u+f08a,u+f094,u+f096-f097,u+f09d,u+f0a0,u+f0a2,u+f0a4-f0a7,u+f0c5,u+f0c7,u+f0e5-f0e6,u+f0eb,u+f0f6-f0f8,u+f10c,u+f114-f115,u+f118-f11a,u+f11c-f11d,u+f133,u+f147,u+f14e,u+f150-f152,u+f185-f186,u+f18e,u+f190-f192,u+f196,u+f1c1-f1c9,u+f1d9,u+f1db,u+f1e3,u+f1ea,u+f1f7,u+f1f9,u+f20a,u+f247-f248,u+f24a,u+f24d,u+f255-f25b,u+f25d,u+f271-f274,u+f278,u+f27b,u+f28c,u+f28e,u+f29c,u+f2b5,u+f2b7,u+f2ba,u+f2bc,u+f2be,u+f2c0-f2c1,u+f2c3,u+f2d0,u+f2d2,u+f2d4,u+f2dc}@font-face{font-family:"FontAwesome";font-display:block;src:url(../webfonts/fa-v4compatibility.woff2) format("woff2"),url(../webfonts/fa-v4compatibility.ttf) format("truetype");unicode-range:u+f041,u+f047,u+f065-f066,u+f07d-f07e,u+f080,u+f08b,u+f08e,u+f090,u+f09a,u+f0ac,u+f0ae,u+f0b2,u+f0d0,u+f0d6,u+f0e4,u+f0ec,u+f10a-f10b,u+f123,u+f13e,u+f148-f149,u+f14c,u+f156,u+f15e,u+f160-f161,u+f163,u+f175-f178,u+f195,u+f1f8,u+f219,u+f27a} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.ttf b/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.ttf deleted file mode 100644 index bb2a8695..00000000 Binary files a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.ttf and /dev/null differ diff --git a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.woff2 b/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.woff2 deleted file mode 100644 index 758dd4f6..00000000 Binary files a/tinygrad/examples/tinychat/assets/cdnjs.cloudflare.com/ajax/libs/font-awesome/6.5.2/webfonts/fa-solid-900.woff2 and /dev/null differ diff --git a/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/highlight.min.js b/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/highlight.min.js deleted file mode 100644 index 5d699ae6..00000000 --- a/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/highlight.min.js +++ /dev/null @@ -1,1213 +0,0 @@ -/*! - Highlight.js v11.9.0 (git: f47103d4f1) - (c) 2006-2023 undefined and other contributors - License: BSD-3-Clause - */ -var hljs=function(){"use strict";function e(n){ -return n instanceof Map?n.clear=n.delete=n.set=()=>{ -throw Error("map is read-only")}:n instanceof Set&&(n.add=n.clear=n.delete=()=>{ -throw Error("set is read-only") -}),Object.freeze(n),Object.getOwnPropertyNames(n).forEach((t=>{ -const a=n[t],i=typeof a;"object"!==i&&"function"!==i||Object.isFrozen(a)||e(a) -})),n}class n{constructor(e){ -void 0===e.data&&(e.data={}),this.data=e.data,this.isMatchIgnored=!1} -ignoreMatch(){this.isMatchIgnored=!0}}function t(e){ -return e.replace(/&/g,"&").replace(//g,">").replace(/"/g,""").replace(/'/g,"'") -}function a(e,...n){const t=Object.create(null);for(const n in e)t[n]=e[n] -;return n.forEach((e=>{for(const n in e)t[n]=e[n]})),t}const i=e=>!!e.scope -;class r{constructor(e,n){ -this.buffer="",this.classPrefix=n.classPrefix,e.walk(this)}addText(e){ -this.buffer+=t(e)}openNode(e){if(!i(e))return;const n=((e,{prefix:n})=>{ -if(e.startsWith("language:"))return e.replace("language:","language-") -;if(e.includes(".")){const t=e.split(".") -;return[`${n}${t.shift()}`,...t.map(((e,n)=>`${e}${"_".repeat(n+1)}`))].join(" ") -}return`${n}${e}`})(e.scope,{prefix:this.classPrefix});this.span(n)} -closeNode(e){i(e)&&(this.buffer+="")}value(){return this.buffer}span(e){ -this.buffer+=``}}const s=(e={})=>{const n={children:[]} -;return Object.assign(n,e),n};class o{constructor(){ -this.rootNode=s(),this.stack=[this.rootNode]}get top(){ -return this.stack[this.stack.length-1]}get root(){return this.rootNode}add(e){ -this.top.children.push(e)}openNode(e){const n=s({scope:e}) -;this.add(n),this.stack.push(n)}closeNode(){ -if(this.stack.length>1)return this.stack.pop()}closeAllNodes(){ -for(;this.closeNode(););}toJSON(){return JSON.stringify(this.rootNode,null,4)} -walk(e){return this.constructor._walk(e,this.rootNode)}static _walk(e,n){ -return"string"==typeof n?e.addText(n):n.children&&(e.openNode(n), -n.children.forEach((n=>this._walk(e,n))),e.closeNode(n)),e}static _collapse(e){ -"string"!=typeof e&&e.children&&(e.children.every((e=>"string"==typeof e))?e.children=[e.children.join("")]:e.children.forEach((e=>{ -o._collapse(e)})))}}class l extends o{constructor(e){super(),this.options=e} -addText(e){""!==e&&this.add(e)}startScope(e){this.openNode(e)}endScope(){ -this.closeNode()}__addSublanguage(e,n){const t=e.root -;n&&(t.scope="language:"+n),this.add(t)}toHTML(){ -return new r(this,this.options).value()}finalize(){ -return this.closeAllNodes(),!0}}function c(e){ -return e?"string"==typeof e?e:e.source:null}function d(e){return b("(?=",e,")")} -function g(e){return b("(?:",e,")*")}function u(e){return b("(?:",e,")?")} -function b(...e){return e.map((e=>c(e))).join("")}function m(...e){const n=(e=>{ -const n=e[e.length-1] -;return"object"==typeof n&&n.constructor===Object?(e.splice(e.length-1,1),n):{} -})(e);return"("+(n.capture?"":"?:")+e.map((e=>c(e))).join("|")+")"} -function p(e){return RegExp(e.toString()+"|").exec("").length-1} -const _=/\[(?:[^\\\]]|\\.)*\]|\(\??|\\([1-9][0-9]*)|\\./ -;function h(e,{joinWith:n}){let t=0;return e.map((e=>{t+=1;const n=t -;let a=c(e),i="";for(;a.length>0;){const e=_.exec(a);if(!e){i+=a;break} -i+=a.substring(0,e.index), -a=a.substring(e.index+e[0].length),"\\"===e[0][0]&&e[1]?i+="\\"+(Number(e[1])+n):(i+=e[0], -"("===e[0]&&t++)}return i})).map((e=>`(${e})`)).join(n)} -const f="[a-zA-Z]\\w*",E="[a-zA-Z_]\\w*",y="\\b\\d+(\\.\\d+)?",N="(-?)(\\b0[xX][a-fA-F0-9]+|(\\b\\d+(\\.\\d*)?|\\.\\d+)([eE][-+]?\\d+)?)",w="\\b(0b[01]+)",v={ -begin:"\\\\[\\s\\S]",relevance:0},O={scope:"string",begin:"'",end:"'", -illegal:"\\n",contains:[v]},k={scope:"string",begin:'"',end:'"',illegal:"\\n", -contains:[v]},x=(e,n,t={})=>{const i=a({scope:"comment",begin:e,end:n, -contains:[]},t);i.contains.push({scope:"doctag", -begin:"[ ]*(?=(TODO|FIXME|NOTE|BUG|OPTIMIZE|HACK|XXX):)", -end:/(TODO|FIXME|NOTE|BUG|OPTIMIZE|HACK|XXX):/,excludeBegin:!0,relevance:0}) -;const r=m("I","a","is","so","us","to","at","if","in","it","on",/[A-Za-z]+['](d|ve|re|ll|t|s|n)/,/[A-Za-z]+[-][a-z]+/,/[A-Za-z][a-z]{2,}/) -;return i.contains.push({begin:b(/[ ]+/,"(",r,/[.]?[:]?([.][ ]|[ ])/,"){3}")}),i -},M=x("//","$"),S=x("/\\*","\\*/"),A=x("#","$");var C=Object.freeze({ -__proto__:null,APOS_STRING_MODE:O,BACKSLASH_ESCAPE:v,BINARY_NUMBER_MODE:{ -scope:"number",begin:w,relevance:0},BINARY_NUMBER_RE:w,COMMENT:x, -C_BLOCK_COMMENT_MODE:S,C_LINE_COMMENT_MODE:M,C_NUMBER_MODE:{scope:"number", -begin:N,relevance:0},C_NUMBER_RE:N,END_SAME_AS_BEGIN:e=>Object.assign(e,{ -"on:begin":(e,n)=>{n.data._beginMatch=e[1]},"on:end":(e,n)=>{ -n.data._beginMatch!==e[1]&&n.ignoreMatch()}}),HASH_COMMENT_MODE:A,IDENT_RE:f, -MATCH_NOTHING_RE:/\b\B/,METHOD_GUARD:{begin:"\\.\\s*"+E,relevance:0}, -NUMBER_MODE:{scope:"number",begin:y,relevance:0},NUMBER_RE:y, -PHRASAL_WORDS_MODE:{ -begin:/\b(a|an|the|are|I'm|isn't|don't|doesn't|won't|but|just|should|pretty|simply|enough|gonna|going|wtf|so|such|will|you|your|they|like|more)\b/ -},QUOTE_STRING_MODE:k,REGEXP_MODE:{scope:"regexp",begin:/\/(?=[^/\n]*\/)/, -end:/\/[gimuy]*/,contains:[v,{begin:/\[/,end:/\]/,relevance:0,contains:[v]}]}, -RE_STARTERS_RE:"!|!=|!==|%|%=|&|&&|&=|\\*|\\*=|\\+|\\+=|,|-|-=|/=|/|:|;|<<|<<=|<=|<|===|==|=|>>>=|>>=|>=|>>>|>>|>|\\?|\\[|\\{|\\(|\\^|\\^=|\\||\\|=|\\|\\||~", -SHEBANG:(e={})=>{const n=/^#![ ]*\// -;return e.binary&&(e.begin=b(n,/.*\b/,e.binary,/\b.*/)),a({scope:"meta",begin:n, -end:/$/,relevance:0,"on:begin":(e,n)=>{0!==e.index&&n.ignoreMatch()}},e)}, -TITLE_MODE:{scope:"title",begin:f,relevance:0},UNDERSCORE_IDENT_RE:E, -UNDERSCORE_TITLE_MODE:{scope:"title",begin:E,relevance:0}});function T(e,n){ -"."===e.input[e.index-1]&&n.ignoreMatch()}function R(e,n){ -void 0!==e.className&&(e.scope=e.className,delete e.className)}function D(e,n){ -n&&e.beginKeywords&&(e.begin="\\b("+e.beginKeywords.split(" ").join("|")+")(?!\\.)(?=\\b|\\s)", -e.__beforeBegin=T,e.keywords=e.keywords||e.beginKeywords,delete e.beginKeywords, -void 0===e.relevance&&(e.relevance=0))}function I(e,n){ -Array.isArray(e.illegal)&&(e.illegal=m(...e.illegal))}function L(e,n){ -if(e.match){ -if(e.begin||e.end)throw Error("begin & end are not supported with match") -;e.begin=e.match,delete e.match}}function B(e,n){ -void 0===e.relevance&&(e.relevance=1)}const $=(e,n)=>{if(!e.beforeMatch)return -;if(e.starts)throw Error("beforeMatch cannot be used with starts") -;const t=Object.assign({},e);Object.keys(e).forEach((n=>{delete e[n] -})),e.keywords=t.keywords,e.begin=b(t.beforeMatch,d(t.begin)),e.starts={ -relevance:0,contains:[Object.assign(t,{endsParent:!0})] -},e.relevance=0,delete t.beforeMatch -},z=["of","and","for","in","not","or","if","then","parent","list","value"],F="keyword" -;function U(e,n,t=F){const a=Object.create(null) -;return"string"==typeof e?i(t,e.split(" ")):Array.isArray(e)?i(t,e):Object.keys(e).forEach((t=>{ -Object.assign(a,U(e[t],n,t))})),a;function i(e,t){ -n&&(t=t.map((e=>e.toLowerCase()))),t.forEach((n=>{const t=n.split("|") -;a[t[0]]=[e,j(t[0],t[1])]}))}}function j(e,n){ -return n?Number(n):(e=>z.includes(e.toLowerCase()))(e)?0:1}const P={},K=e=>{ -console.error(e)},H=(e,...n)=>{console.log("WARN: "+e,...n)},q=(e,n)=>{ -P[`${e}/${n}`]||(console.log(`Deprecated as of ${e}. ${n}`),P[`${e}/${n}`]=!0) -},G=Error();function Z(e,n,{key:t}){let a=0;const i=e[t],r={},s={} -;for(let e=1;e<=n.length;e++)s[e+a]=i[e],r[e+a]=!0,a+=p(n[e-1]) -;e[t]=s,e[t]._emit=r,e[t]._multi=!0}function W(e){(e=>{ -e.scope&&"object"==typeof e.scope&&null!==e.scope&&(e.beginScope=e.scope, -delete e.scope)})(e),"string"==typeof e.beginScope&&(e.beginScope={ -_wrap:e.beginScope}),"string"==typeof e.endScope&&(e.endScope={_wrap:e.endScope -}),(e=>{if(Array.isArray(e.begin)){ -if(e.skip||e.excludeBegin||e.returnBegin)throw K("skip, excludeBegin, returnBegin not compatible with beginScope: {}"), -G -;if("object"!=typeof e.beginScope||null===e.beginScope)throw K("beginScope must be object"), -G;Z(e,e.begin,{key:"beginScope"}),e.begin=h(e.begin,{joinWith:""})}})(e),(e=>{ -if(Array.isArray(e.end)){ -if(e.skip||e.excludeEnd||e.returnEnd)throw K("skip, excludeEnd, returnEnd not compatible with endScope: {}"), -G -;if("object"!=typeof e.endScope||null===e.endScope)throw K("endScope must be object"), -G;Z(e,e.end,{key:"endScope"}),e.end=h(e.end,{joinWith:""})}})(e)}function Q(e){ -function n(n,t){ -return RegExp(c(n),"m"+(e.case_insensitive?"i":"")+(e.unicodeRegex?"u":"")+(t?"g":"")) -}class t{constructor(){ -this.matchIndexes={},this.regexes=[],this.matchAt=1,this.position=0} -addRule(e,n){ -n.position=this.position++,this.matchIndexes[this.matchAt]=n,this.regexes.push([n,e]), -this.matchAt+=p(e)+1}compile(){0===this.regexes.length&&(this.exec=()=>null) -;const e=this.regexes.map((e=>e[1]));this.matcherRe=n(h(e,{joinWith:"|" -}),!0),this.lastIndex=0}exec(e){this.matcherRe.lastIndex=this.lastIndex -;const n=this.matcherRe.exec(e);if(!n)return null -;const t=n.findIndex(((e,n)=>n>0&&void 0!==e)),a=this.matchIndexes[t] -;return n.splice(0,t),Object.assign(n,a)}}class i{constructor(){ -this.rules=[],this.multiRegexes=[], -this.count=0,this.lastIndex=0,this.regexIndex=0}getMatcher(e){ -if(this.multiRegexes[e])return this.multiRegexes[e];const n=new t -;return this.rules.slice(e).forEach((([e,t])=>n.addRule(e,t))), -n.compile(),this.multiRegexes[e]=n,n}resumingScanAtSamePosition(){ -return 0!==this.regexIndex}considerAll(){this.regexIndex=0}addRule(e,n){ -this.rules.push([e,n]),"begin"===n.type&&this.count++}exec(e){ -const n=this.getMatcher(this.regexIndex);n.lastIndex=this.lastIndex -;let t=n.exec(e) -;if(this.resumingScanAtSamePosition())if(t&&t.index===this.lastIndex);else{ -const n=this.getMatcher(0);n.lastIndex=this.lastIndex+1,t=n.exec(e)} -return t&&(this.regexIndex+=t.position+1, -this.regexIndex===this.count&&this.considerAll()),t}} -if(e.compilerExtensions||(e.compilerExtensions=[]), -e.contains&&e.contains.includes("self"))throw Error("ERR: contains `self` is not supported at the top-level of a language. See documentation.") -;return e.classNameAliases=a(e.classNameAliases||{}),function t(r,s){const o=r -;if(r.isCompiled)return o -;[R,L,W,$].forEach((e=>e(r,s))),e.compilerExtensions.forEach((e=>e(r,s))), -r.__beforeBegin=null,[D,I,B].forEach((e=>e(r,s))),r.isCompiled=!0;let l=null -;return"object"==typeof r.keywords&&r.keywords.$pattern&&(r.keywords=Object.assign({},r.keywords), -l=r.keywords.$pattern, -delete r.keywords.$pattern),l=l||/\w+/,r.keywords&&(r.keywords=U(r.keywords,e.case_insensitive)), -o.keywordPatternRe=n(l,!0), -s&&(r.begin||(r.begin=/\B|\b/),o.beginRe=n(o.begin),r.end||r.endsWithParent||(r.end=/\B|\b/), -r.end&&(o.endRe=n(o.end)), -o.terminatorEnd=c(o.end)||"",r.endsWithParent&&s.terminatorEnd&&(o.terminatorEnd+=(r.end?"|":"")+s.terminatorEnd)), -r.illegal&&(o.illegalRe=n(r.illegal)), -r.contains||(r.contains=[]),r.contains=[].concat(...r.contains.map((e=>(e=>(e.variants&&!e.cachedVariants&&(e.cachedVariants=e.variants.map((n=>a(e,{ -variants:null},n)))),e.cachedVariants?e.cachedVariants:X(e)?a(e,{ -starts:e.starts?a(e.starts):null -}):Object.isFrozen(e)?a(e):e))("self"===e?r:e)))),r.contains.forEach((e=>{t(e,o) -})),r.starts&&t(r.starts,s),o.matcher=(e=>{const n=new i -;return e.contains.forEach((e=>n.addRule(e.begin,{rule:e,type:"begin" -}))),e.terminatorEnd&&n.addRule(e.terminatorEnd,{type:"end" -}),e.illegal&&n.addRule(e.illegal,{type:"illegal"}),n})(o),o}(e)}function X(e){ -return!!e&&(e.endsWithParent||X(e.starts))}class V extends Error{ -constructor(e,n){super(e),this.name="HTMLInjectionError",this.html=n}} -const J=t,Y=a,ee=Symbol("nomatch"),ne=t=>{ -const a=Object.create(null),i=Object.create(null),r=[];let s=!0 -;const o="Could not find the language '{}', did you forget to load/include a language module?",c={ -disableAutodetect:!0,name:"Plain text",contains:[]};let p={ -ignoreUnescapedHTML:!1,throwUnescapedHTML:!1,noHighlightRe:/^(no-?highlight)$/i, -languageDetectRe:/\blang(?:uage)?-([\w-]+)\b/i,classPrefix:"hljs-", -cssSelector:"pre code",languages:null,__emitter:l};function _(e){ -return p.noHighlightRe.test(e)}function h(e,n,t){let a="",i="" -;"object"==typeof n?(a=e, -t=n.ignoreIllegals,i=n.language):(q("10.7.0","highlight(lang, code, ...args) has been deprecated."), -q("10.7.0","Please use highlight(code, options) instead.\nhttps://github.com/highlightjs/highlight.js/issues/2277"), -i=e,a=n),void 0===t&&(t=!0);const r={code:a,language:i};x("before:highlight",r) -;const s=r.result?r.result:f(r.language,r.code,t) -;return s.code=r.code,x("after:highlight",s),s}function f(e,t,i,r){ -const l=Object.create(null);function c(){if(!x.keywords)return void S.addText(A) -;let e=0;x.keywordPatternRe.lastIndex=0;let n=x.keywordPatternRe.exec(A),t="" -;for(;n;){t+=A.substring(e,n.index) -;const i=w.case_insensitive?n[0].toLowerCase():n[0],r=(a=i,x.keywords[a]);if(r){ -const[e,a]=r -;if(S.addText(t),t="",l[i]=(l[i]||0)+1,l[i]<=7&&(C+=a),e.startsWith("_"))t+=n[0];else{ -const t=w.classNameAliases[e]||e;g(n[0],t)}}else t+=n[0] -;e=x.keywordPatternRe.lastIndex,n=x.keywordPatternRe.exec(A)}var a -;t+=A.substring(e),S.addText(t)}function d(){null!=x.subLanguage?(()=>{ -if(""===A)return;let e=null;if("string"==typeof x.subLanguage){ -if(!a[x.subLanguage])return void S.addText(A) -;e=f(x.subLanguage,A,!0,M[x.subLanguage]),M[x.subLanguage]=e._top -}else e=E(A,x.subLanguage.length?x.subLanguage:null) -;x.relevance>0&&(C+=e.relevance),S.__addSublanguage(e._emitter,e.language) -})():c(),A=""}function g(e,n){ -""!==e&&(S.startScope(n),S.addText(e),S.endScope())}function u(e,n){let t=1 -;const a=n.length-1;for(;t<=a;){if(!e._emit[t]){t++;continue} -const a=w.classNameAliases[e[t]]||e[t],i=n[t];a?g(i,a):(A=i,c(),A=""),t++}} -function b(e,n){ -return e.scope&&"string"==typeof e.scope&&S.openNode(w.classNameAliases[e.scope]||e.scope), -e.beginScope&&(e.beginScope._wrap?(g(A,w.classNameAliases[e.beginScope._wrap]||e.beginScope._wrap), -A=""):e.beginScope._multi&&(u(e.beginScope,n),A="")),x=Object.create(e,{parent:{ -value:x}}),x}function m(e,t,a){let i=((e,n)=>{const t=e&&e.exec(n) -;return t&&0===t.index})(e.endRe,a);if(i){if(e["on:end"]){const a=new n(e) -;e["on:end"](t,a),a.isMatchIgnored&&(i=!1)}if(i){ -for(;e.endsParent&&e.parent;)e=e.parent;return e}} -if(e.endsWithParent)return m(e.parent,t,a)}function _(e){ -return 0===x.matcher.regexIndex?(A+=e[0],1):(D=!0,0)}function h(e){ -const n=e[0],a=t.substring(e.index),i=m(x,e,a);if(!i)return ee;const r=x -;x.endScope&&x.endScope._wrap?(d(), -g(n,x.endScope._wrap)):x.endScope&&x.endScope._multi?(d(), -u(x.endScope,e)):r.skip?A+=n:(r.returnEnd||r.excludeEnd||(A+=n), -d(),r.excludeEnd&&(A=n));do{ -x.scope&&S.closeNode(),x.skip||x.subLanguage||(C+=x.relevance),x=x.parent -}while(x!==i.parent);return i.starts&&b(i.starts,e),r.returnEnd?0:n.length} -let y={};function N(a,r){const o=r&&r[0];if(A+=a,null==o)return d(),0 -;if("begin"===y.type&&"end"===r.type&&y.index===r.index&&""===o){ -if(A+=t.slice(r.index,r.index+1),!s){const n=Error(`0 width match regex (${e})`) -;throw n.languageName=e,n.badRule=y.rule,n}return 1} -if(y=r,"begin"===r.type)return(e=>{ -const t=e[0],a=e.rule,i=new n(a),r=[a.__beforeBegin,a["on:begin"]] -;for(const n of r)if(n&&(n(e,i),i.isMatchIgnored))return _(t) -;return a.skip?A+=t:(a.excludeBegin&&(A+=t), -d(),a.returnBegin||a.excludeBegin||(A=t)),b(a,e),a.returnBegin?0:t.length})(r) -;if("illegal"===r.type&&!i){ -const e=Error('Illegal lexeme "'+o+'" for mode "'+(x.scope||"")+'"') -;throw e.mode=x,e}if("end"===r.type){const e=h(r);if(e!==ee)return e} -if("illegal"===r.type&&""===o)return 1 -;if(R>1e5&&R>3*r.index)throw Error("potential infinite loop, way more iterations than matches") -;return A+=o,o.length}const w=v(e) -;if(!w)throw K(o.replace("{}",e)),Error('Unknown language: "'+e+'"') -;const O=Q(w);let k="",x=r||O;const M={},S=new p.__emitter(p);(()=>{const e=[] -;for(let n=x;n!==w;n=n.parent)n.scope&&e.unshift(n.scope) -;e.forEach((e=>S.openNode(e)))})();let A="",C=0,T=0,R=0,D=!1;try{ -if(w.__emitTokens)w.__emitTokens(t,S);else{for(x.matcher.considerAll();;){ -R++,D?D=!1:x.matcher.considerAll(),x.matcher.lastIndex=T -;const e=x.matcher.exec(t);if(!e)break;const n=N(t.substring(T,e.index),e) -;T=e.index+n}N(t.substring(T))}return S.finalize(),k=S.toHTML(),{language:e, -value:k,relevance:C,illegal:!1,_emitter:S,_top:x}}catch(n){ -if(n.message&&n.message.includes("Illegal"))return{language:e,value:J(t), -illegal:!0,relevance:0,_illegalBy:{message:n.message,index:T, -context:t.slice(T-100,T+100),mode:n.mode,resultSoFar:k},_emitter:S};if(s)return{ -language:e,value:J(t),illegal:!1,relevance:0,errorRaised:n,_emitter:S,_top:x} -;throw n}}function E(e,n){n=n||p.languages||Object.keys(a);const t=(e=>{ -const n={value:J(e),illegal:!1,relevance:0,_top:c,_emitter:new p.__emitter(p)} -;return n._emitter.addText(e),n})(e),i=n.filter(v).filter(k).map((n=>f(n,e,!1))) -;i.unshift(t);const r=i.sort(((e,n)=>{ -if(e.relevance!==n.relevance)return n.relevance-e.relevance -;if(e.language&&n.language){if(v(e.language).supersetOf===n.language)return 1 -;if(v(n.language).supersetOf===e.language)return-1}return 0})),[s,o]=r,l=s -;return l.secondBest=o,l}function y(e){let n=null;const t=(e=>{ -let n=e.className+" ";n+=e.parentNode?e.parentNode.className:"" -;const t=p.languageDetectRe.exec(n);if(t){const n=v(t[1]) -;return n||(H(o.replace("{}",t[1])), -H("Falling back to no-highlight mode for this block.",e)),n?t[1]:"no-highlight"} -return n.split(/\s+/).find((e=>_(e)||v(e)))})(e);if(_(t))return -;if(x("before:highlightElement",{el:e,language:t -}),e.dataset.highlighted)return void console.log("Element previously highlighted. To highlight again, first unset `dataset.highlighted`.",e) -;if(e.children.length>0&&(p.ignoreUnescapedHTML||(console.warn("One of your code blocks includes unescaped HTML. This is a potentially serious security risk."), -console.warn("https://github.com/highlightjs/highlight.js/wiki/security"), -console.warn("The element with unescaped HTML:"), -console.warn(e)),p.throwUnescapedHTML))throw new V("One of your code blocks includes unescaped HTML.",e.innerHTML) -;n=e;const a=n.textContent,r=t?h(a,{language:t,ignoreIllegals:!0}):E(a) -;e.innerHTML=r.value,e.dataset.highlighted="yes",((e,n,t)=>{const a=n&&i[n]||t -;e.classList.add("hljs"),e.classList.add("language-"+a) -})(e,t,r.language),e.result={language:r.language,re:r.relevance, -relevance:r.relevance},r.secondBest&&(e.secondBest={ -language:r.secondBest.language,relevance:r.secondBest.relevance -}),x("after:highlightElement",{el:e,result:r,text:a})}let N=!1;function w(){ -"loading"!==document.readyState?document.querySelectorAll(p.cssSelector).forEach(y):N=!0 -}function v(e){return e=(e||"").toLowerCase(),a[e]||a[i[e]]} -function O(e,{languageName:n}){"string"==typeof e&&(e=[e]),e.forEach((e=>{ -i[e.toLowerCase()]=n}))}function k(e){const n=v(e) -;return n&&!n.disableAutodetect}function x(e,n){const t=e;r.forEach((e=>{ -e[t]&&e[t](n)}))} -"undefined"!=typeof window&&window.addEventListener&&window.addEventListener("DOMContentLoaded",(()=>{ -N&&w()}),!1),Object.assign(t,{highlight:h,highlightAuto:E,highlightAll:w, -highlightElement:y, -highlightBlock:e=>(q("10.7.0","highlightBlock will be removed entirely in v12.0"), -q("10.7.0","Please use highlightElement now."),y(e)),configure:e=>{p=Y(p,e)}, -initHighlighting:()=>{ -w(),q("10.6.0","initHighlighting() deprecated. Use highlightAll() now.")}, -initHighlightingOnLoad:()=>{ -w(),q("10.6.0","initHighlightingOnLoad() deprecated. Use highlightAll() now.") -},registerLanguage:(e,n)=>{let i=null;try{i=n(t)}catch(n){ -if(K("Language definition for '{}' could not be registered.".replace("{}",e)), -!s)throw n;K(n),i=c} -i.name||(i.name=e),a[e]=i,i.rawDefinition=n.bind(null,t),i.aliases&&O(i.aliases,{ -languageName:e})},unregisterLanguage:e=>{delete a[e] -;for(const n of Object.keys(i))i[n]===e&&delete i[n]}, -listLanguages:()=>Object.keys(a),getLanguage:v,registerAliases:O, -autoDetection:k,inherit:Y,addPlugin:e=>{(e=>{ -e["before:highlightBlock"]&&!e["before:highlightElement"]&&(e["before:highlightElement"]=n=>{ -e["before:highlightBlock"](Object.assign({block:n.el},n)) -}),e["after:highlightBlock"]&&!e["after:highlightElement"]&&(e["after:highlightElement"]=n=>{ -e["after:highlightBlock"](Object.assign({block:n.el},n))})})(e),r.push(e)}, -removePlugin:e=>{const n=r.indexOf(e);-1!==n&&r.splice(n,1)}}),t.debugMode=()=>{ -s=!1},t.safeMode=()=>{s=!0},t.versionString="11.9.0",t.regex={concat:b, -lookahead:d,either:m,optional:u,anyNumberOfTimes:g} -;for(const n in C)"object"==typeof C[n]&&e(C[n]);return Object.assign(t,C),t -},te=ne({});te.newInstance=()=>ne({});var ae=te;const ie=e=>({IMPORTANT:{ -scope:"meta",begin:"!important"},BLOCK_COMMENT:e.C_BLOCK_COMMENT_MODE,HEXCOLOR:{ -scope:"number",begin:/#(([0-9a-fA-F]{3,4})|(([0-9a-fA-F]{2}){3,4}))\b/}, -FUNCTION_DISPATCH:{className:"built_in",begin:/[\w-]+(?=\()/}, -ATTRIBUTE_SELECTOR_MODE:{scope:"selector-attr",begin:/\[/,end:/\]/,illegal:"$", -contains:[e.APOS_STRING_MODE,e.QUOTE_STRING_MODE]},CSS_NUMBER_MODE:{ -scope:"number", -begin:e.NUMBER_RE+"(%|em|ex|ch|rem|vw|vh|vmin|vmax|cm|mm|in|pt|pc|px|deg|grad|rad|turn|s|ms|Hz|kHz|dpi|dpcm|dppx)?", -relevance:0},CSS_VARIABLE:{className:"attr",begin:/--[A-Za-z_][A-Za-z0-9_-]*/} -}),re=["a","abbr","address","article","aside","audio","b","blockquote","body","button","canvas","caption","cite","code","dd","del","details","dfn","div","dl","dt","em","fieldset","figcaption","figure","footer","form","h1","h2","h3","h4","h5","h6","header","hgroup","html","i","iframe","img","input","ins","kbd","label","legend","li","main","mark","menu","nav","object","ol","p","q","quote","samp","section","span","strong","summary","sup","table","tbody","td","textarea","tfoot","th","thead","time","tr","ul","var","video"],se=["any-hover","any-pointer","aspect-ratio","color","color-gamut","color-index","device-aspect-ratio","device-height","device-width","display-mode","forced-colors","grid","height","hover","inverted-colors","monochrome","orientation","overflow-block","overflow-inline","pointer","prefers-color-scheme","prefers-contrast","prefers-reduced-motion","prefers-reduced-transparency","resolution","scan","scripting","update","width","min-width","max-width","min-height","max-height"],oe=["active","any-link","blank","checked","current","default","defined","dir","disabled","drop","empty","enabled","first","first-child","first-of-type","fullscreen","future","focus","focus-visible","focus-within","has","host","host-context","hover","indeterminate","in-range","invalid","is","lang","last-child","last-of-type","left","link","local-link","not","nth-child","nth-col","nth-last-child","nth-last-col","nth-last-of-type","nth-of-type","only-child","only-of-type","optional","out-of-range","past","placeholder-shown","read-only","read-write","required","right","root","scope","target","target-within","user-invalid","valid","visited","where"],le=["after","backdrop","before","cue","cue-region","first-letter","first-line","grammar-error","marker","part","placeholder","selection","slotted","spelling-error"],ce=["align-content","align-items","align-self","all","animation","animation-delay","animation-direction","animation-duration","animation-fill-mode","animation-iteration-count","animation-name","animation-play-state","animation-timing-function","backface-visibility","background","background-attachment","background-blend-mode","background-clip","background-color","background-image","background-origin","background-position","background-repeat","background-size","block-size","border","border-block","border-block-color","border-block-end","border-block-end-color","border-block-end-style","border-block-end-width","border-block-start","border-block-start-color","border-block-start-style","border-block-start-width","border-block-style","border-block-width","border-bottom","border-bottom-color","border-bottom-left-radius","border-bottom-right-radius","border-bottom-style","border-bottom-width","border-collapse","border-color","border-image","border-image-outset","border-image-repeat","border-image-slice","border-image-source","border-image-width","border-inline","border-inline-color","border-inline-end","border-inline-end-color","border-inline-end-style","border-inline-end-width","border-inline-start","border-inline-start-color","border-inline-start-style","border-inline-start-width","border-inline-style","border-inline-width","border-left","border-left-color","border-left-style","border-left-width","border-radius","border-right","border-right-color","border-right-style","border-right-width","border-spacing","border-style","border-top","border-top-color","border-top-left-radius","border-top-right-radius","border-top-style","border-top-width","border-width","bottom","box-decoration-break","box-shadow","box-sizing","break-after","break-before","break-inside","caption-side","caret-color","clear","clip","clip-path","clip-rule","color","column-count","column-fill","column-gap","column-rule","column-rule-color","column-rule-style","column-rule-width","column-span","column-width","columns","contain","content","content-visibility","counter-increment","counter-reset","cue","cue-after","cue-before","cursor","direction","display","empty-cells","filter","flex","flex-basis","flex-direction","flex-flow","flex-grow","flex-shrink","flex-wrap","float","flow","font","font-display","font-family","font-feature-settings","font-kerning","font-language-override","font-size","font-size-adjust","font-smoothing","font-stretch","font-style","font-synthesis","font-variant","font-variant-caps","font-variant-east-asian","font-variant-ligatures","font-variant-numeric","font-variant-position","font-variation-settings","font-weight","gap","glyph-orientation-vertical","grid","grid-area","grid-auto-columns","grid-auto-flow","grid-auto-rows","grid-column","grid-column-end","grid-column-start","grid-gap","grid-row","grid-row-end","grid-row-start","grid-template","grid-template-areas","grid-template-columns","grid-template-rows","hanging-punctuation","height","hyphens","icon","image-orientation","image-rendering","image-resolution","ime-mode","inline-size","isolation","justify-content","left","letter-spacing","line-break","line-height","list-style","list-style-image","list-style-position","list-style-type","margin","margin-block","margin-block-end","margin-block-start","margin-bottom","margin-inline","margin-inline-end","margin-inline-start","margin-left","margin-right","margin-top","marks","mask","mask-border","mask-border-mode","mask-border-outset","mask-border-repeat","mask-border-slice","mask-border-source","mask-border-width","mask-clip","mask-composite","mask-image","mask-mode","mask-origin","mask-position","mask-repeat","mask-size","mask-type","max-block-size","max-height","max-inline-size","max-width","min-block-size","min-height","min-inline-size","min-width","mix-blend-mode","nav-down","nav-index","nav-left","nav-right","nav-up","none","normal","object-fit","object-position","opacity","order","orphans","outline","outline-color","outline-offset","outline-style","outline-width","overflow","overflow-wrap","overflow-x","overflow-y","padding","padding-block","padding-block-end","padding-block-start","padding-bottom","padding-inline","padding-inline-end","padding-inline-start","padding-left","padding-right","padding-top","page-break-after","page-break-before","page-break-inside","pause","pause-after","pause-before","perspective","perspective-origin","pointer-events","position","quotes","resize","rest","rest-after","rest-before","right","row-gap","scroll-margin","scroll-margin-block","scroll-margin-block-end","scroll-margin-block-start","scroll-margin-bottom","scroll-margin-inline","scroll-margin-inline-end","scroll-margin-inline-start","scroll-margin-left","scroll-margin-right","scroll-margin-top","scroll-padding","scroll-padding-block","scroll-padding-block-end","scroll-padding-block-start","scroll-padding-bottom","scroll-padding-inline","scroll-padding-inline-end","scroll-padding-inline-start","scroll-padding-left","scroll-padding-right","scroll-padding-top","scroll-snap-align","scroll-snap-stop","scroll-snap-type","scrollbar-color","scrollbar-gutter","scrollbar-width","shape-image-threshold","shape-margin","shape-outside","speak","speak-as","src","tab-size","table-layout","text-align","text-align-all","text-align-last","text-combine-upright","text-decoration","text-decoration-color","text-decoration-line","text-decoration-style","text-emphasis","text-emphasis-color","text-emphasis-position","text-emphasis-style","text-indent","text-justify","text-orientation","text-overflow","text-rendering","text-shadow","text-transform","text-underline-position","top","transform","transform-box","transform-origin","transform-style","transition","transition-delay","transition-duration","transition-property","transition-timing-function","unicode-bidi","vertical-align","visibility","voice-balance","voice-duration","voice-family","voice-pitch","voice-range","voice-rate","voice-stress","voice-volume","white-space","widows","width","will-change","word-break","word-spacing","word-wrap","writing-mode","z-index"].reverse(),de=oe.concat(le) -;var ge="[0-9](_*[0-9])*",ue=`\\.(${ge})`,be="[0-9a-fA-F](_*[0-9a-fA-F])*",me={ -className:"number",variants:[{ -begin:`(\\b(${ge})((${ue})|\\.)?|(${ue}))[eE][+-]?(${ge})[fFdD]?\\b`},{ -begin:`\\b(${ge})((${ue})[fFdD]?\\b|\\.([fFdD]\\b)?)`},{ -begin:`(${ue})[fFdD]?\\b`},{begin:`\\b(${ge})[fFdD]\\b`},{ -begin:`\\b0[xX]((${be})\\.?|(${be})?\\.(${be}))[pP][+-]?(${ge})[fFdD]?\\b`},{ -begin:"\\b(0|[1-9](_*[0-9])*)[lL]?\\b"},{begin:`\\b0[xX](${be})[lL]?\\b`},{ -begin:"\\b0(_*[0-7])*[lL]?\\b"},{begin:"\\b0[bB][01](_*[01])*[lL]?\\b"}], -relevance:0};function pe(e,n,t){return-1===t?"":e.replace(n,(a=>pe(e,n,t-1)))} -const _e="[A-Za-z$_][0-9A-Za-z$_]*",he=["as","in","of","if","for","while","finally","var","new","function","do","return","void","else","break","catch","instanceof","with","throw","case","default","try","switch","continue","typeof","delete","let","yield","const","class","debugger","async","await","static","import","from","export","extends"],fe=["true","false","null","undefined","NaN","Infinity"],Ee=["Object","Function","Boolean","Symbol","Math","Date","Number","BigInt","String","RegExp","Array","Float32Array","Float64Array","Int8Array","Uint8Array","Uint8ClampedArray","Int16Array","Int32Array","Uint16Array","Uint32Array","BigInt64Array","BigUint64Array","Set","Map","WeakSet","WeakMap","ArrayBuffer","SharedArrayBuffer","Atomics","DataView","JSON","Promise","Generator","GeneratorFunction","AsyncFunction","Reflect","Proxy","Intl","WebAssembly"],ye=["Error","EvalError","InternalError","RangeError","ReferenceError","SyntaxError","TypeError","URIError"],Ne=["setInterval","setTimeout","clearInterval","clearTimeout","require","exports","eval","isFinite","isNaN","parseFloat","parseInt","decodeURI","decodeURIComponent","encodeURI","encodeURIComponent","escape","unescape"],we=["arguments","this","super","console","window","document","localStorage","sessionStorage","module","global"],ve=[].concat(Ne,Ee,ye) -;function Oe(e){const n=e.regex,t=_e,a={begin:/<[A-Za-z0-9\\._:-]+/, -end:/\/[A-Za-z0-9\\._:-]+>|\/>/,isTrulyOpeningTag:(e,n)=>{ -const t=e[0].length+e.index,a=e.input[t] -;if("<"===a||","===a)return void n.ignoreMatch();let i -;">"===a&&(((e,{after:n})=>{const t="",M={ -match:[/const|var|let/,/\s+/,t,/\s*/,/=\s*/,/(async\s*)?/,n.lookahead(x)], -keywords:"async",className:{1:"keyword",3:"title.function"},contains:[f]} -;return{name:"JavaScript",aliases:["js","jsx","mjs","cjs"],keywords:i,exports:{ -PARAMS_CONTAINS:h,CLASS_REFERENCE:y},illegal:/#(?![$_A-z])/, -contains:[e.SHEBANG({label:"shebang",binary:"node",relevance:5}),{ -label:"use_strict",className:"meta",relevance:10, -begin:/^\s*['"]use (strict|asm)['"]/ -},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,d,g,u,b,m,{match:/\$\d+/},l,y,{ -className:"attr",begin:t+n.lookahead(":"),relevance:0},M,{ -begin:"("+e.RE_STARTERS_RE+"|\\b(case|return|throw)\\b)\\s*", -keywords:"return throw case",relevance:0,contains:[m,e.REGEXP_MODE,{ -className:"function",begin:x,returnBegin:!0,end:"\\s*=>",contains:[{ -className:"params",variants:[{begin:e.UNDERSCORE_IDENT_RE,relevance:0},{ -className:null,begin:/\(\s*\)/,skip:!0},{begin:/\(/,end:/\)/,excludeBegin:!0, -excludeEnd:!0,keywords:i,contains:h}]}]},{begin:/,/,relevance:0},{match:/\s+/, -relevance:0},{variants:[{begin:"<>",end:""},{ -match:/<[A-Za-z0-9\\._:-]+\s*\/>/},{begin:a.begin, -"on:begin":a.isTrulyOpeningTag,end:a.end}],subLanguage:"xml",contains:[{ -begin:a.begin,end:a.end,skip:!0,contains:["self"]}]}]},N,{ -beginKeywords:"while if switch catch for"},{ -begin:"\\b(?!function)"+e.UNDERSCORE_IDENT_RE+"\\([^()]*(\\([^()]*(\\([^()]*\\)[^()]*)*\\)[^()]*)*\\)\\s*\\{", -returnBegin:!0,label:"func.def",contains:[f,e.inherit(e.TITLE_MODE,{begin:t, -className:"title.function"})]},{match:/\.\.\./,relevance:0},O,{match:"\\$"+t, -relevance:0},{match:[/\bconstructor(?=\s*\()/],className:{1:"title.function"}, -contains:[f]},w,{relevance:0,match:/\b[A-Z][A-Z_0-9]+\b/, -className:"variable.constant"},E,k,{match:/\$[(.]/}]}} -const ke=e=>b(/\b/,e,/\w$/.test(e)?/\b/:/\B/),xe=["Protocol","Type"].map(ke),Me=["init","self"].map(ke),Se=["Any","Self"],Ae=["actor","any","associatedtype","async","await",/as\?/,/as!/,"as","borrowing","break","case","catch","class","consume","consuming","continue","convenience","copy","default","defer","deinit","didSet","distributed","do","dynamic","each","else","enum","extension","fallthrough",/fileprivate\(set\)/,"fileprivate","final","for","func","get","guard","if","import","indirect","infix",/init\?/,/init!/,"inout",/internal\(set\)/,"internal","in","is","isolated","nonisolated","lazy","let","macro","mutating","nonmutating",/open\(set\)/,"open","operator","optional","override","postfix","precedencegroup","prefix",/private\(set\)/,"private","protocol",/public\(set\)/,"public","repeat","required","rethrows","return","set","some","static","struct","subscript","super","switch","throws","throw",/try\?/,/try!/,"try","typealias",/unowned\(safe\)/,/unowned\(unsafe\)/,"unowned","var","weak","where","while","willSet"],Ce=["false","nil","true"],Te=["assignment","associativity","higherThan","left","lowerThan","none","right"],Re=["#colorLiteral","#column","#dsohandle","#else","#elseif","#endif","#error","#file","#fileID","#fileLiteral","#filePath","#function","#if","#imageLiteral","#keyPath","#line","#selector","#sourceLocation","#warning"],De=["abs","all","any","assert","assertionFailure","debugPrint","dump","fatalError","getVaList","isKnownUniquelyReferenced","max","min","numericCast","pointwiseMax","pointwiseMin","precondition","preconditionFailure","print","readLine","repeatElement","sequence","stride","swap","swift_unboxFromSwiftValueWithType","transcode","type","unsafeBitCast","unsafeDowncast","withExtendedLifetime","withUnsafeMutablePointer","withUnsafePointer","withVaList","withoutActuallyEscaping","zip"],Ie=m(/[/=\-+!*%<>&|^~?]/,/[\u00A1-\u00A7]/,/[\u00A9\u00AB]/,/[\u00AC\u00AE]/,/[\u00B0\u00B1]/,/[\u00B6\u00BB\u00BF\u00D7\u00F7]/,/[\u2016-\u2017]/,/[\u2020-\u2027]/,/[\u2030-\u203E]/,/[\u2041-\u2053]/,/[\u2055-\u205E]/,/[\u2190-\u23FF]/,/[\u2500-\u2775]/,/[\u2794-\u2BFF]/,/[\u2E00-\u2E7F]/,/[\u3001-\u3003]/,/[\u3008-\u3020]/,/[\u3030]/),Le=m(Ie,/[\u0300-\u036F]/,/[\u1DC0-\u1DFF]/,/[\u20D0-\u20FF]/,/[\uFE00-\uFE0F]/,/[\uFE20-\uFE2F]/),Be=b(Ie,Le,"*"),$e=m(/[a-zA-Z_]/,/[\u00A8\u00AA\u00AD\u00AF\u00B2-\u00B5\u00B7-\u00BA]/,/[\u00BC-\u00BE\u00C0-\u00D6\u00D8-\u00F6\u00F8-\u00FF]/,/[\u0100-\u02FF\u0370-\u167F\u1681-\u180D\u180F-\u1DBF]/,/[\u1E00-\u1FFF]/,/[\u200B-\u200D\u202A-\u202E\u203F-\u2040\u2054\u2060-\u206F]/,/[\u2070-\u20CF\u2100-\u218F\u2460-\u24FF\u2776-\u2793]/,/[\u2C00-\u2DFF\u2E80-\u2FFF]/,/[\u3004-\u3007\u3021-\u302F\u3031-\u303F\u3040-\uD7FF]/,/[\uF900-\uFD3D\uFD40-\uFDCF\uFDF0-\uFE1F\uFE30-\uFE44]/,/[\uFE47-\uFEFE\uFF00-\uFFFD]/),ze=m($e,/\d/,/[\u0300-\u036F\u1DC0-\u1DFF\u20D0-\u20FF\uFE20-\uFE2F]/),Fe=b($e,ze,"*"),Ue=b(/[A-Z]/,ze,"*"),je=["attached","autoclosure",b(/convention\(/,m("swift","block","c"),/\)/),"discardableResult","dynamicCallable","dynamicMemberLookup","escaping","freestanding","frozen","GKInspectable","IBAction","IBDesignable","IBInspectable","IBOutlet","IBSegueAction","inlinable","main","nonobjc","NSApplicationMain","NSCopying","NSManaged",b(/objc\(/,Fe,/\)/),"objc","objcMembers","propertyWrapper","requires_stored_property_inits","resultBuilder","Sendable","testable","UIApplicationMain","unchecked","unknown","usableFromInline","warn_unqualified_access"],Pe=["iOS","iOSApplicationExtension","macOS","macOSApplicationExtension","macCatalyst","macCatalystApplicationExtension","watchOS","watchOSApplicationExtension","tvOS","tvOSApplicationExtension","swift"] -;var Ke=Object.freeze({__proto__:null,grmr_bash:e=>{const n=e.regex,t={},a={ -begin:/\$\{/,end:/\}/,contains:["self",{begin:/:-/,contains:[t]}]} -;Object.assign(t,{className:"variable",variants:[{ -begin:n.concat(/\$[\w\d#@][\w\d_]*/,"(?![\\w\\d])(?![$])")},a]});const i={ -className:"subst",begin:/\$\(/,end:/\)/,contains:[e.BACKSLASH_ESCAPE]},r={ -begin:/<<-?\s*(?=\w+)/,starts:{contains:[e.END_SAME_AS_BEGIN({begin:/(\w+)/, -end:/(\w+)/,className:"string"})]}},s={className:"string",begin:/"/,end:/"/, -contains:[e.BACKSLASH_ESCAPE,t,i]};i.contains.push(s);const o={begin:/\$?\(\(/, -end:/\)\)/,contains:[{begin:/\d+#[0-9a-f]+/,className:"number"},e.NUMBER_MODE,t] -},l=e.SHEBANG({binary:"(fish|bash|zsh|sh|csh|ksh|tcsh|dash|scsh)",relevance:10 -}),c={className:"function",begin:/\w[\w\d_]*\s*\(\s*\)\s*\{/,returnBegin:!0, -contains:[e.inherit(e.TITLE_MODE,{begin:/\w[\w\d_]*/})],relevance:0};return{ -name:"Bash",aliases:["sh"],keywords:{$pattern:/\b[a-z][a-z0-9._-]+\b/, -keyword:["if","then","else","elif","fi","for","while","until","in","do","done","case","esac","function","select"], -literal:["true","false"], -built_in:["break","cd","continue","eval","exec","exit","export","getopts","hash","pwd","readonly","return","shift","test","times","trap","umask","unset","alias","bind","builtin","caller","command","declare","echo","enable","help","let","local","logout","mapfile","printf","read","readarray","source","type","typeset","ulimit","unalias","set","shopt","autoload","bg","bindkey","bye","cap","chdir","clone","comparguments","compcall","compctl","compdescribe","compfiles","compgroups","compquote","comptags","comptry","compvalues","dirs","disable","disown","echotc","echoti","emulate","fc","fg","float","functions","getcap","getln","history","integer","jobs","kill","limit","log","noglob","popd","print","pushd","pushln","rehash","sched","setcap","setopt","stat","suspend","ttyctl","unfunction","unhash","unlimit","unsetopt","vared","wait","whence","where","which","zcompile","zformat","zftp","zle","zmodload","zparseopts","zprof","zpty","zregexparse","zsocket","zstyle","ztcp","chcon","chgrp","chown","chmod","cp","dd","df","dir","dircolors","ln","ls","mkdir","mkfifo","mknod","mktemp","mv","realpath","rm","rmdir","shred","sync","touch","truncate","vdir","b2sum","base32","base64","cat","cksum","comm","csplit","cut","expand","fmt","fold","head","join","md5sum","nl","numfmt","od","paste","ptx","pr","sha1sum","sha224sum","sha256sum","sha384sum","sha512sum","shuf","sort","split","sum","tac","tail","tr","tsort","unexpand","uniq","wc","arch","basename","chroot","date","dirname","du","echo","env","expr","factor","groups","hostid","id","link","logname","nice","nohup","nproc","pathchk","pinky","printenv","printf","pwd","readlink","runcon","seq","sleep","stat","stdbuf","stty","tee","test","timeout","tty","uname","unlink","uptime","users","who","whoami","yes"] -},contains:[l,e.SHEBANG(),c,o,e.HASH_COMMENT_MODE,r,{match:/(\/[a-z._-]+)+/},s,{ -match:/\\"/},{className:"string",begin:/'/,end:/'/},{match:/\\'/},t]}}, -grmr_c:e=>{const n=e.regex,t=e.COMMENT("//","$",{contains:[{begin:/\\\n/}] -}),a="decltype\\(auto\\)",i="[a-zA-Z_]\\w*::",r="("+a+"|"+n.optional(i)+"[a-zA-Z_]\\w*"+n.optional("<[^<>]+>")+")",s={ -className:"type",variants:[{begin:"\\b[a-z\\d_]*_t\\b"},{ -match:/\batomic_[a-z]{3,6}\b/}]},o={className:"string",variants:[{ -begin:'(u8?|U|L)?"',end:'"',illegal:"\\n",contains:[e.BACKSLASH_ESCAPE]},{ -begin:"(u8?|U|L)?'(\\\\(x[0-9A-Fa-f]{2}|u[0-9A-Fa-f]{4,8}|[0-7]{3}|\\S)|.)", -end:"'",illegal:"."},e.END_SAME_AS_BEGIN({ -begin:/(?:u8?|U|L)?R"([^()\\ ]{0,16})\(/,end:/\)([^()\\ ]{0,16})"/})]},l={ -className:"number",variants:[{begin:"\\b(0b[01']+)"},{ -begin:"(-?)\\b([\\d']+(\\.[\\d']*)?|\\.[\\d']+)((ll|LL|l|L)(u|U)?|(u|U)(ll|LL|l|L)?|f|F|b|B)" -},{ -begin:"(-?)(\\b0[xX][a-fA-F0-9']+|(\\b[\\d']+(\\.[\\d']*)?|\\.[\\d']+)([eE][-+]?[\\d']+)?)" -}],relevance:0},c={className:"meta",begin:/#\s*[a-z]+\b/,end:/$/,keywords:{ -keyword:"if else elif endif define undef warning error line pragma _Pragma ifdef ifndef include" -},contains:[{begin:/\\\n/,relevance:0},e.inherit(o,{className:"string"}),{ -className:"string",begin:/<.*?>/},t,e.C_BLOCK_COMMENT_MODE]},d={ -className:"title",begin:n.optional(i)+e.IDENT_RE,relevance:0 -},g=n.optional(i)+e.IDENT_RE+"\\s*\\(",u={ -keyword:["asm","auto","break","case","continue","default","do","else","enum","extern","for","fortran","goto","if","inline","register","restrict","return","sizeof","struct","switch","typedef","union","volatile","while","_Alignas","_Alignof","_Atomic","_Generic","_Noreturn","_Static_assert","_Thread_local","alignas","alignof","noreturn","static_assert","thread_local","_Pragma"], -type:["float","double","signed","unsigned","int","short","long","char","void","_Bool","_Complex","_Imaginary","_Decimal32","_Decimal64","_Decimal128","const","static","complex","bool","imaginary"], -literal:"true false NULL", -built_in:"std string wstring cin cout cerr clog stdin stdout stderr stringstream istringstream ostringstream auto_ptr deque list queue stack vector map set pair bitset multiset multimap unordered_set unordered_map unordered_multiset unordered_multimap priority_queue make_pair array shared_ptr abort terminate abs acos asin atan2 atan calloc ceil cosh cos exit exp fabs floor fmod fprintf fputs free frexp fscanf future isalnum isalpha iscntrl isdigit isgraph islower isprint ispunct isspace isupper isxdigit tolower toupper labs ldexp log10 log malloc realloc memchr memcmp memcpy memset modf pow printf putchar puts scanf sinh sin snprintf sprintf sqrt sscanf strcat strchr strcmp strcpy strcspn strlen strncat strncmp strncpy strpbrk strrchr strspn strstr tanh tan vfprintf vprintf vsprintf endl initializer_list unique_ptr" -},b=[c,s,t,e.C_BLOCK_COMMENT_MODE,l,o],m={variants:[{begin:/=/,end:/;/},{ -begin:/\(/,end:/\)/},{beginKeywords:"new throw return else",end:/;/}], -keywords:u,contains:b.concat([{begin:/\(/,end:/\)/,keywords:u, -contains:b.concat(["self"]),relevance:0}]),relevance:0},p={ -begin:"("+r+"[\\*&\\s]+)+"+g,returnBegin:!0,end:/[{;=]/,excludeEnd:!0, -keywords:u,illegal:/[^\w\s\*&:<>.]/,contains:[{begin:a,keywords:u,relevance:0},{ -begin:g,returnBegin:!0,contains:[e.inherit(d,{className:"title.function"})], -relevance:0},{relevance:0,match:/,/},{className:"params",begin:/\(/,end:/\)/, -keywords:u,relevance:0,contains:[t,e.C_BLOCK_COMMENT_MODE,o,l,s,{begin:/\(/, -end:/\)/,keywords:u,relevance:0,contains:["self",t,e.C_BLOCK_COMMENT_MODE,o,l,s] -}]},s,t,e.C_BLOCK_COMMENT_MODE,c]};return{name:"C",aliases:["h"],keywords:u, -disableAutodetect:!0,illegal:"=]/,contains:[{ -beginKeywords:"final class struct"},e.TITLE_MODE]}]),exports:{preprocessor:c, -strings:o,keywords:u}}},grmr_cpp:e=>{const n=e.regex,t=e.COMMENT("//","$",{ -contains:[{begin:/\\\n/}] -}),a="decltype\\(auto\\)",i="[a-zA-Z_]\\w*::",r="(?!struct)("+a+"|"+n.optional(i)+"[a-zA-Z_]\\w*"+n.optional("<[^<>]+>")+")",s={ -className:"type",begin:"\\b[a-z\\d_]*_t\\b"},o={className:"string",variants:[{ -begin:'(u8?|U|L)?"',end:'"',illegal:"\\n",contains:[e.BACKSLASH_ESCAPE]},{ -begin:"(u8?|U|L)?'(\\\\(x[0-9A-Fa-f]{2}|u[0-9A-Fa-f]{4,8}|[0-7]{3}|\\S)|.)", -end:"'",illegal:"."},e.END_SAME_AS_BEGIN({ -begin:/(?:u8?|U|L)?R"([^()\\ ]{0,16})\(/,end:/\)([^()\\ ]{0,16})"/})]},l={ -className:"number",variants:[{begin:"\\b(0b[01']+)"},{ -begin:"(-?)\\b([\\d']+(\\.[\\d']*)?|\\.[\\d']+)((ll|LL|l|L)(u|U)?|(u|U)(ll|LL|l|L)?|f|F|b|B)" -},{ -begin:"(-?)(\\b0[xX][a-fA-F0-9']+|(\\b[\\d']+(\\.[\\d']*)?|\\.[\\d']+)([eE][-+]?[\\d']+)?)" -}],relevance:0},c={className:"meta",begin:/#\s*[a-z]+\b/,end:/$/,keywords:{ -keyword:"if else elif endif define undef warning error line pragma _Pragma ifdef ifndef include" -},contains:[{begin:/\\\n/,relevance:0},e.inherit(o,{className:"string"}),{ -className:"string",begin:/<.*?>/},t,e.C_BLOCK_COMMENT_MODE]},d={ -className:"title",begin:n.optional(i)+e.IDENT_RE,relevance:0 -},g=n.optional(i)+e.IDENT_RE+"\\s*\\(",u={ -type:["bool","char","char16_t","char32_t","char8_t","double","float","int","long","short","void","wchar_t","unsigned","signed","const","static"], -keyword:["alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit","atomic_noexcept","auto","bitand","bitor","break","case","catch","class","co_await","co_return","co_yield","compl","concept","const_cast|10","consteval","constexpr","constinit","continue","decltype","default","delete","do","dynamic_cast|10","else","enum","explicit","export","extern","false","final","for","friend","goto","if","import","inline","module","mutable","namespace","new","noexcept","not","not_eq","nullptr","operator","or","or_eq","override","private","protected","public","reflexpr","register","reinterpret_cast|10","requires","return","sizeof","static_assert","static_cast|10","struct","switch","synchronized","template","this","thread_local","throw","transaction_safe","transaction_safe_dynamic","true","try","typedef","typeid","typename","union","using","virtual","volatile","while","xor","xor_eq"], -literal:["NULL","false","nullopt","nullptr","true"],built_in:["_Pragma"], -_type_hints:["any","auto_ptr","barrier","binary_semaphore","bitset","complex","condition_variable","condition_variable_any","counting_semaphore","deque","false_type","future","imaginary","initializer_list","istringstream","jthread","latch","lock_guard","multimap","multiset","mutex","optional","ostringstream","packaged_task","pair","promise","priority_queue","queue","recursive_mutex","recursive_timed_mutex","scoped_lock","set","shared_future","shared_lock","shared_mutex","shared_timed_mutex","shared_ptr","stack","string_view","stringstream","timed_mutex","thread","true_type","tuple","unique_lock","unique_ptr","unordered_map","unordered_multimap","unordered_multiset","unordered_set","variant","vector","weak_ptr","wstring","wstring_view"] -},b={className:"function.dispatch",relevance:0,keywords:{ -_hint:["abort","abs","acos","apply","as_const","asin","atan","atan2","calloc","ceil","cerr","cin","clog","cos","cosh","cout","declval","endl","exchange","exit","exp","fabs","floor","fmod","forward","fprintf","fputs","free","frexp","fscanf","future","invoke","isalnum","isalpha","iscntrl","isdigit","isgraph","islower","isprint","ispunct","isspace","isupper","isxdigit","labs","launder","ldexp","log","log10","make_pair","make_shared","make_shared_for_overwrite","make_tuple","make_unique","malloc","memchr","memcmp","memcpy","memset","modf","move","pow","printf","putchar","puts","realloc","scanf","sin","sinh","snprintf","sprintf","sqrt","sscanf","std","stderr","stdin","stdout","strcat","strchr","strcmp","strcpy","strcspn","strlen","strncat","strncmp","strncpy","strpbrk","strrchr","strspn","strstr","swap","tan","tanh","terminate","to_underlying","tolower","toupper","vfprintf","visit","vprintf","vsprintf"] -}, -begin:n.concat(/\b/,/(?!decltype)/,/(?!if)/,/(?!for)/,/(?!switch)/,/(?!while)/,e.IDENT_RE,n.lookahead(/(<[^<>]+>|)\s*\(/)) -},m=[b,c,s,t,e.C_BLOCK_COMMENT_MODE,l,o],p={variants:[{begin:/=/,end:/;/},{ -begin:/\(/,end:/\)/},{beginKeywords:"new throw return else",end:/;/}], -keywords:u,contains:m.concat([{begin:/\(/,end:/\)/,keywords:u, -contains:m.concat(["self"]),relevance:0}]),relevance:0},_={className:"function", -begin:"("+r+"[\\*&\\s]+)+"+g,returnBegin:!0,end:/[{;=]/,excludeEnd:!0, -keywords:u,illegal:/[^\w\s\*&:<>.]/,contains:[{begin:a,keywords:u,relevance:0},{ -begin:g,returnBegin:!0,contains:[d],relevance:0},{begin:/::/,relevance:0},{ -begin:/:/,endsWithParent:!0,contains:[o,l]},{relevance:0,match:/,/},{ -className:"params",begin:/\(/,end:/\)/,keywords:u,relevance:0, -contains:[t,e.C_BLOCK_COMMENT_MODE,o,l,s,{begin:/\(/,end:/\)/,keywords:u, -relevance:0,contains:["self",t,e.C_BLOCK_COMMENT_MODE,o,l,s]}] -},s,t,e.C_BLOCK_COMMENT_MODE,c]};return{name:"C++", -aliases:["cc","c++","h++","hpp","hh","hxx","cxx"],keywords:u,illegal:"",keywords:u,contains:["self",s]},{begin:e.IDENT_RE+"::",keywords:u},{ -match:[/\b(?:enum(?:\s+(?:class|struct))?|class|struct|union)/,/\s+/,/\w+/], -className:{1:"keyword",3:"title.class"}}])}},grmr_csharp:e=>{const n={ -keyword:["abstract","as","base","break","case","catch","class","const","continue","do","else","event","explicit","extern","finally","fixed","for","foreach","goto","if","implicit","in","interface","internal","is","lock","namespace","new","operator","out","override","params","private","protected","public","readonly","record","ref","return","scoped","sealed","sizeof","stackalloc","static","struct","switch","this","throw","try","typeof","unchecked","unsafe","using","virtual","void","volatile","while"].concat(["add","alias","and","ascending","async","await","by","descending","equals","from","get","global","group","init","into","join","let","nameof","not","notnull","on","or","orderby","partial","remove","select","set","unmanaged","value|0","var","when","where","with","yield"]), -built_in:["bool","byte","char","decimal","delegate","double","dynamic","enum","float","int","long","nint","nuint","object","sbyte","short","string","ulong","uint","ushort"], -literal:["default","false","null","true"]},t=e.inherit(e.TITLE_MODE,{ -begin:"[a-zA-Z](\\.?\\w)*"}),a={className:"number",variants:[{ -begin:"\\b(0b[01']+)"},{ -begin:"(-?)\\b([\\d']+(\\.[\\d']*)?|\\.[\\d']+)(u|U|l|L|ul|UL|f|F|b|B)"},{ -begin:"(-?)(\\b0[xX][a-fA-F0-9']+|(\\b[\\d']+(\\.[\\d']*)?|\\.[\\d']+)([eE][-+]?[\\d']+)?)" -}],relevance:0},i={className:"string",begin:'@"',end:'"',contains:[{begin:'""'}] -},r=e.inherit(i,{illegal:/\n/}),s={className:"subst",begin:/\{/,end:/\}/, -keywords:n},o=e.inherit(s,{illegal:/\n/}),l={className:"string",begin:/\$"/, -end:'"',illegal:/\n/,contains:[{begin:/\{\{/},{begin:/\}\}/ -},e.BACKSLASH_ESCAPE,o]},c={className:"string",begin:/\$@"/,end:'"',contains:[{ -begin:/\{\{/},{begin:/\}\}/},{begin:'""'},s]},d=e.inherit(c,{illegal:/\n/, -contains:[{begin:/\{\{/},{begin:/\}\}/},{begin:'""'},o]}) -;s.contains=[c,l,i,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,a,e.C_BLOCK_COMMENT_MODE], -o.contains=[d,l,r,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,a,e.inherit(e.C_BLOCK_COMMENT_MODE,{ -illegal:/\n/})];const g={variants:[c,l,i,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE] -},u={begin:"<",end:">",contains:[{beginKeywords:"in out"},t] -},b=e.IDENT_RE+"(<"+e.IDENT_RE+"(\\s*,\\s*"+e.IDENT_RE+")*>)?(\\[\\])?",m={ -begin:"@"+e.IDENT_RE,relevance:0};return{name:"C#",aliases:["cs","c#"], -keywords:n,illegal:/::/,contains:[e.COMMENT("///","$",{returnBegin:!0, -contains:[{className:"doctag",variants:[{begin:"///",relevance:0},{ -begin:"\x3c!--|--\x3e"},{begin:""}]}] -}),e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,{className:"meta",begin:"#", -end:"$",keywords:{ -keyword:"if else elif endif define undef warning error line region endregion pragma checksum" -}},g,a,{beginKeywords:"class interface",relevance:0,end:/[{;=]/, -illegal:/[^\s:,]/,contains:[{beginKeywords:"where class" -},t,u,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{beginKeywords:"namespace", -relevance:0,end:/[{;=]/,illegal:/[^\s:]/, -contains:[t,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{ -beginKeywords:"record",relevance:0,end:/[{;=]/,illegal:/[^\s:]/, -contains:[t,u,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{className:"meta", -begin:"^\\s*\\[(?=[\\w])",excludeBegin:!0,end:"\\]",excludeEnd:!0,contains:[{ -className:"string",begin:/"/,end:/"/}]},{ -beginKeywords:"new return throw await else",relevance:0},{className:"function", -begin:"("+b+"\\s+)+"+e.IDENT_RE+"\\s*(<[^=]+>\\s*)?\\(",returnBegin:!0, -end:/\s*[{;=]/,excludeEnd:!0,keywords:n,contains:[{ -beginKeywords:"public private protected static internal protected abstract async extern override unsafe virtual new sealed partial", -relevance:0},{begin:e.IDENT_RE+"\\s*(<[^=]+>\\s*)?\\(",returnBegin:!0, -contains:[e.TITLE_MODE,u],relevance:0},{match:/\(\)/},{className:"params", -begin:/\(/,end:/\)/,excludeBegin:!0,excludeEnd:!0,keywords:n,relevance:0, -contains:[g,a,e.C_BLOCK_COMMENT_MODE] -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},m]}},grmr_css:e=>{ -const n=e.regex,t=ie(e),a=[e.APOS_STRING_MODE,e.QUOTE_STRING_MODE];return{ -name:"CSS",case_insensitive:!0,illegal:/[=|'\$]/,keywords:{ -keyframePosition:"from to"},classNameAliases:{keyframePosition:"selector-tag"}, -contains:[t.BLOCK_COMMENT,{begin:/-(webkit|moz|ms|o)-(?=[a-z])/ -},t.CSS_NUMBER_MODE,{className:"selector-id",begin:/#[A-Za-z0-9_-]+/,relevance:0 -},{className:"selector-class",begin:"\\.[a-zA-Z-][a-zA-Z0-9_-]*",relevance:0 -},t.ATTRIBUTE_SELECTOR_MODE,{className:"selector-pseudo",variants:[{ -begin:":("+oe.join("|")+")"},{begin:":(:)?("+le.join("|")+")"}] -},t.CSS_VARIABLE,{className:"attribute",begin:"\\b("+ce.join("|")+")\\b"},{ -begin:/:/,end:/[;}{]/, -contains:[t.BLOCK_COMMENT,t.HEXCOLOR,t.IMPORTANT,t.CSS_NUMBER_MODE,...a,{ -begin:/(url|data-uri)\(/,end:/\)/,relevance:0,keywords:{built_in:"url data-uri" -},contains:[...a,{className:"string",begin:/[^)]/,endsWithParent:!0, -excludeEnd:!0}]},t.FUNCTION_DISPATCH]},{begin:n.lookahead(/@/),end:"[{;]", -relevance:0,illegal:/:/,contains:[{className:"keyword",begin:/@-?\w[\w]*(-\w+)*/ -},{begin:/\s/,endsWithParent:!0,excludeEnd:!0,relevance:0,keywords:{ -$pattern:/[a-z-]+/,keyword:"and or not only",attribute:se.join(" ")},contains:[{ -begin:/[a-z-]+(?=:)/,className:"attribute"},...a,t.CSS_NUMBER_MODE]}]},{ -className:"selector-tag",begin:"\\b("+re.join("|")+")\\b"}]}},grmr_diff:e=>{ -const n=e.regex;return{name:"Diff",aliases:["patch"],contains:[{ -className:"meta",relevance:10, -match:n.either(/^@@ +-\d+,\d+ +\+\d+,\d+ +@@/,/^\*\*\* +\d+,\d+ +\*\*\*\*$/,/^--- +\d+,\d+ +----$/) -},{className:"comment",variants:[{ -begin:n.either(/Index: /,/^index/,/={3,}/,/^-{3}/,/^\*{3} /,/^\+{3}/,/^diff --git/), -end:/$/},{match:/^\*{15}$/}]},{className:"addition",begin:/^\+/,end:/$/},{ -className:"deletion",begin:/^-/,end:/$/},{className:"addition",begin:/^!/, -end:/$/}]}},grmr_go:e=>{const n={ -keyword:["break","case","chan","const","continue","default","defer","else","fallthrough","for","func","go","goto","if","import","interface","map","package","range","return","select","struct","switch","type","var"], -type:["bool","byte","complex64","complex128","error","float32","float64","int8","int16","int32","int64","string","uint8","uint16","uint32","uint64","int","uint","uintptr","rune"], -literal:["true","false","iota","nil"], -built_in:["append","cap","close","complex","copy","imag","len","make","new","panic","print","println","real","recover","delete"] -};return{name:"Go",aliases:["golang"],keywords:n,illegal:"{const n=e.regex;return{name:"GraphQL",aliases:["gql"], -case_insensitive:!0,disableAutodetect:!1,keywords:{ -keyword:["query","mutation","subscription","type","input","schema","directive","interface","union","scalar","fragment","enum","on"], -literal:["true","false","null"]}, -contains:[e.HASH_COMMENT_MODE,e.QUOTE_STRING_MODE,e.NUMBER_MODE,{ -scope:"punctuation",match:/[.]{3}/,relevance:0},{scope:"punctuation", -begin:/[\!\(\)\:\=\[\]\{\|\}]{1}/,relevance:0},{scope:"variable",begin:/\$/, -end:/\W/,excludeEnd:!0,relevance:0},{scope:"meta",match:/@\w+/,excludeEnd:!0},{ -scope:"symbol",begin:n.concat(/[_A-Za-z][_0-9A-Za-z]*/,n.lookahead(/\s*:/)), -relevance:0}],illegal:[/[;<']/,/BEGIN/]}},grmr_ini:e=>{const n=e.regex,t={ -className:"number",relevance:0,variants:[{begin:/([+-]+)?[\d]+_[\d_]+/},{ -begin:e.NUMBER_RE}]},a=e.COMMENT();a.variants=[{begin:/;/,end:/$/},{begin:/#/, -end:/$/}];const i={className:"variable",variants:[{begin:/\$[\w\d"][\w\d_]*/},{ -begin:/\$\{(.*?)\}/}]},r={className:"literal", -begin:/\bon|off|true|false|yes|no\b/},s={className:"string", -contains:[e.BACKSLASH_ESCAPE],variants:[{begin:"'''",end:"'''",relevance:10},{ -begin:'"""',end:'"""',relevance:10},{begin:'"',end:'"'},{begin:"'",end:"'"}] -},o={begin:/\[/,end:/\]/,contains:[a,r,i,s,t,"self"],relevance:0 -},l=n.either(/[A-Za-z0-9_-]+/,/"(\\"|[^"])*"/,/'[^']*'/);return{ -name:"TOML, also INI",aliases:["toml"],case_insensitive:!0,illegal:/\S/, -contains:[a,{className:"section",begin:/\[+/,end:/\]+/},{ -begin:n.concat(l,"(\\s*\\.\\s*",l,")*",n.lookahead(/\s*=\s*[^#\s]/)), -className:"attr",starts:{end:/$/,contains:[a,o,r,i,s,t]}}]}},grmr_java:e=>{ -const n=e.regex,t="[\xc0-\u02b8a-zA-Z_$][\xc0-\u02b8a-zA-Z_$0-9]*",a=t+pe("(?:<"+t+"~~~(?:\\s*,\\s*"+t+"~~~)*>)?",/~~~/g,2),i={ -keyword:["synchronized","abstract","private","var","static","if","const ","for","while","strictfp","finally","protected","import","native","final","void","enum","else","break","transient","catch","instanceof","volatile","case","assert","package","default","public","try","switch","continue","throws","protected","public","private","module","requires","exports","do","sealed","yield","permits"], -literal:["false","true","null"], -type:["char","boolean","long","float","int","byte","short","double"], -built_in:["super","this"]},r={className:"meta",begin:"@"+t,contains:[{ -begin:/\(/,end:/\)/,contains:["self"]}]},s={className:"params",begin:/\(/, -end:/\)/,keywords:i,relevance:0,contains:[e.C_BLOCK_COMMENT_MODE],endsParent:!0} -;return{name:"Java",aliases:["jsp"],keywords:i,illegal:/<\/|#/, -contains:[e.COMMENT("/\\*\\*","\\*/",{relevance:0,contains:[{begin:/\w+@/, -relevance:0},{className:"doctag",begin:"@[A-Za-z]+"}]}),{ -begin:/import java\.[a-z]+\./,keywords:"import",relevance:2 -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,{begin:/"""/,end:/"""/, -className:"string",contains:[e.BACKSLASH_ESCAPE] -},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,{ -match:[/\b(?:class|interface|enum|extends|implements|new)/,/\s+/,t],className:{ -1:"keyword",3:"title.class"}},{match:/non-sealed/,scope:"keyword"},{ -begin:[n.concat(/(?!else)/,t),/\s+/,t,/\s+/,/=(?!=)/],className:{1:"type", -3:"variable",5:"operator"}},{begin:[/record/,/\s+/,t],className:{1:"keyword", -3:"title.class"},contains:[s,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{ -beginKeywords:"new throw return else",relevance:0},{ -begin:["(?:"+a+"\\s+)",e.UNDERSCORE_IDENT_RE,/\s*(?=\()/],className:{ -2:"title.function"},keywords:i,contains:[{className:"params",begin:/\(/, -end:/\)/,keywords:i,relevance:0, -contains:[r,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,me,e.C_BLOCK_COMMENT_MODE] -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},me,r]}},grmr_javascript:Oe, -grmr_json:e=>{const n=["true","false","null"],t={scope:"literal", -beginKeywords:n.join(" ")};return{name:"JSON",keywords:{literal:n},contains:[{ -className:"attr",begin:/"(\\.|[^\\"\r\n])*"(?=\s*:)/,relevance:1.01},{ -match:/[{}[\],:]/,className:"punctuation",relevance:0 -},e.QUOTE_STRING_MODE,t,e.C_NUMBER_MODE,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE], -illegal:"\\S"}},grmr_kotlin:e=>{const n={ -keyword:"abstract as val var vararg get set class object open private protected public noinline crossinline dynamic final enum if else do while for when throw try catch finally import package is in fun override companion reified inline lateinit init interface annotation data sealed internal infix operator out by constructor super tailrec where const inner suspend typealias external expect actual", -built_in:"Byte Short Char Int Long Boolean Float Double Void Unit Nothing", -literal:"true false null"},t={className:"symbol",begin:e.UNDERSCORE_IDENT_RE+"@" -},a={className:"subst",begin:/\$\{/,end:/\}/,contains:[e.C_NUMBER_MODE]},i={ -className:"variable",begin:"\\$"+e.UNDERSCORE_IDENT_RE},r={className:"string", -variants:[{begin:'"""',end:'"""(?=[^"])',contains:[i,a]},{begin:"'",end:"'", -illegal:/\n/,contains:[e.BACKSLASH_ESCAPE]},{begin:'"',end:'"',illegal:/\n/, -contains:[e.BACKSLASH_ESCAPE,i,a]}]};a.contains.push(r);const s={ -className:"meta", -begin:"@(?:file|property|field|get|set|receiver|param|setparam|delegate)\\s*:(?:\\s*"+e.UNDERSCORE_IDENT_RE+")?" -},o={className:"meta",begin:"@"+e.UNDERSCORE_IDENT_RE,contains:[{begin:/\(/, -end:/\)/,contains:[e.inherit(r,{className:"string"}),"self"]}] -},l=me,c=e.COMMENT("/\\*","\\*/",{contains:[e.C_BLOCK_COMMENT_MODE]}),d={ -variants:[{className:"type",begin:e.UNDERSCORE_IDENT_RE},{begin:/\(/,end:/\)/, -contains:[]}]},g=d;return g.variants[1].contains=[d],d.variants[1].contains=[g], -{name:"Kotlin",aliases:["kt","kts"],keywords:n, -contains:[e.COMMENT("/\\*\\*","\\*/",{relevance:0,contains:[{className:"doctag", -begin:"@[A-Za-z]+"}]}),e.C_LINE_COMMENT_MODE,c,{className:"keyword", -begin:/\b(break|continue|return|this)\b/,starts:{contains:[{className:"symbol", -begin:/@\w+/}]}},t,s,o,{className:"function",beginKeywords:"fun",end:"[(]|$", -returnBegin:!0,excludeEnd:!0,keywords:n,relevance:5,contains:[{ -begin:e.UNDERSCORE_IDENT_RE+"\\s*\\(",returnBegin:!0,relevance:0, -contains:[e.UNDERSCORE_TITLE_MODE]},{className:"type",begin://, -keywords:"reified",relevance:0},{className:"params",begin:/\(/,end:/\)/, -endsParent:!0,keywords:n,relevance:0,contains:[{begin:/:/,end:/[=,\/]/, -endsWithParent:!0,contains:[d,e.C_LINE_COMMENT_MODE,c],relevance:0 -},e.C_LINE_COMMENT_MODE,c,s,o,r,e.C_NUMBER_MODE]},c]},{ -begin:[/class|interface|trait/,/\s+/,e.UNDERSCORE_IDENT_RE],beginScope:{ -3:"title.class"},keywords:"class interface trait",end:/[:\{(]|$/,excludeEnd:!0, -illegal:"extends implements",contains:[{ -beginKeywords:"public protected internal private constructor" -},e.UNDERSCORE_TITLE_MODE,{className:"type",begin://,excludeBegin:!0, -excludeEnd:!0,relevance:0},{className:"type",begin:/[,:]\s*/,end:/[<\(,){\s]|$/, -excludeBegin:!0,returnEnd:!0},s,o]},r,{className:"meta",begin:"^#!/usr/bin/env", -end:"$",illegal:"\n"},l]}},grmr_less:e=>{ -const n=ie(e),t=de,a="[\\w-]+",i="("+a+"|@\\{"+a+"\\})",r=[],s=[],o=e=>({ -className:"string",begin:"~?"+e+".*?"+e}),l=(e,n,t)=>({className:e,begin:n, -relevance:t}),c={$pattern:/[a-z-]+/,keyword:"and or not only", -attribute:se.join(" ")},d={begin:"\\(",end:"\\)",contains:s,keywords:c, -relevance:0} -;s.push(e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,o("'"),o('"'),n.CSS_NUMBER_MODE,{ -begin:"(url|data-uri)\\(",starts:{className:"string",end:"[\\)\\n]", -excludeEnd:!0} -},n.HEXCOLOR,d,l("variable","@@?"+a,10),l("variable","@\\{"+a+"\\}"),l("built_in","~?`[^`]*?`"),{ -className:"attribute",begin:a+"\\s*:",end:":",returnBegin:!0,excludeEnd:!0 -},n.IMPORTANT,{beginKeywords:"and not"},n.FUNCTION_DISPATCH);const g=s.concat({ -begin:/\{/,end:/\}/,contains:r}),u={beginKeywords:"when",endsWithParent:!0, -contains:[{beginKeywords:"and not"}].concat(s)},b={begin:i+"\\s*:", -returnBegin:!0,end:/[;}]/,relevance:0,contains:[{begin:/-(webkit|moz|ms|o)-/ -},n.CSS_VARIABLE,{className:"attribute",begin:"\\b("+ce.join("|")+")\\b", -end:/(?=:)/,starts:{endsWithParent:!0,illegal:"[<=$]",relevance:0,contains:s}}] -},m={className:"keyword", -begin:"@(import|media|charset|font-face|(-[a-z]+-)?keyframes|supports|document|namespace|page|viewport|host)\\b", -starts:{end:"[;{}]",keywords:c,returnEnd:!0,contains:s,relevance:0}},p={ -className:"variable",variants:[{begin:"@"+a+"\\s*:",relevance:15},{begin:"@"+a -}],starts:{end:"[;}]",returnEnd:!0,contains:g}},_={variants:[{ -begin:"[\\.#:&\\[>]",end:"[;{}]"},{begin:i,end:/\{/}],returnBegin:!0, -returnEnd:!0,illegal:"[<='$\"]",relevance:0, -contains:[e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,u,l("keyword","all\\b"),l("variable","@\\{"+a+"\\}"),{ -begin:"\\b("+re.join("|")+")\\b",className:"selector-tag" -},n.CSS_NUMBER_MODE,l("selector-tag",i,0),l("selector-id","#"+i),l("selector-class","\\."+i,0),l("selector-tag","&",0),n.ATTRIBUTE_SELECTOR_MODE,{ -className:"selector-pseudo",begin:":("+oe.join("|")+")"},{ -className:"selector-pseudo",begin:":(:)?("+le.join("|")+")"},{begin:/\(/, -end:/\)/,relevance:0,contains:g},{begin:"!important"},n.FUNCTION_DISPATCH]},h={ -begin:a+":(:)?"+`(${t.join("|")})`,returnBegin:!0,contains:[_]} -;return r.push(e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,m,p,h,b,_,u,n.FUNCTION_DISPATCH), -{name:"Less",case_insensitive:!0,illegal:"[=>'/<($\"]",contains:r}}, -grmr_lua:e=>{const n="\\[=*\\[",t="\\]=*\\]",a={begin:n,end:t,contains:["self"] -},i=[e.COMMENT("--(?!"+n+")","$"),e.COMMENT("--"+n,t,{contains:[a],relevance:10 -})];return{name:"Lua",keywords:{$pattern:e.UNDERSCORE_IDENT_RE, -literal:"true false nil", -keyword:"and break do else elseif end for goto if in local not or repeat return then until while", -built_in:"_G _ENV _VERSION __index __newindex __mode __call __metatable __tostring __len __gc __add __sub __mul __div __mod __pow __concat __unm __eq __lt __le assert collectgarbage dofile error getfenv getmetatable ipairs load loadfile loadstring module next pairs pcall print rawequal rawget rawset require select setfenv setmetatable tonumber tostring type unpack xpcall arg self coroutine resume yield status wrap create running debug getupvalue debug sethook getmetatable gethook setmetatable setlocal traceback setfenv getinfo setupvalue getlocal getregistry getfenv io lines write close flush open output type read stderr stdin input stdout popen tmpfile math log max acos huge ldexp pi cos tanh pow deg tan cosh sinh random randomseed frexp ceil floor rad abs sqrt modf asin min mod fmod log10 atan2 exp sin atan os exit setlocale date getenv difftime remove time clock tmpname rename execute package preload loadlib loaded loaders cpath config path seeall string sub upper len gfind rep find match char dump gmatch reverse byte format gsub lower table setn insert getn foreachi maxn foreach concat sort remove" -},contains:i.concat([{className:"function",beginKeywords:"function",end:"\\)", -contains:[e.inherit(e.TITLE_MODE,{ -begin:"([_a-zA-Z]\\w*\\.)*([_a-zA-Z]\\w*:)?[_a-zA-Z]\\w*"}),{className:"params", -begin:"\\(",endsWithParent:!0,contains:i}].concat(i) -},e.C_NUMBER_MODE,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,{className:"string", -begin:n,end:t,contains:[a],relevance:5}])}},grmr_makefile:e=>{const n={ -className:"variable",variants:[{begin:"\\$\\("+e.UNDERSCORE_IDENT_RE+"\\)", -contains:[e.BACKSLASH_ESCAPE]},{begin:/\$[@%{ -const n={begin:/<\/?[A-Za-z_]/,end:">",subLanguage:"xml",relevance:0},t={ -variants:[{begin:/\[.+?\]\[.*?\]/,relevance:0},{ -begin:/\[.+?\]\(((data|javascript|mailto):|(?:http|ftp)s?:\/\/).*?\)/, -relevance:2},{ -begin:e.regex.concat(/\[.+?\]\(/,/[A-Za-z][A-Za-z0-9+.-]*/,/:\/\/.*?\)/), -relevance:2},{begin:/\[.+?\]\([./?&#].*?\)/,relevance:1},{ -begin:/\[.*?\]\(.*?\)/,relevance:0}],returnBegin:!0,contains:[{match:/\[(?=\])/ -},{className:"string",relevance:0,begin:"\\[",end:"\\]",excludeBegin:!0, -returnEnd:!0},{className:"link",relevance:0,begin:"\\]\\(",end:"\\)", -excludeBegin:!0,excludeEnd:!0},{className:"symbol",relevance:0,begin:"\\]\\[", -end:"\\]",excludeBegin:!0,excludeEnd:!0}]},a={className:"strong",contains:[], -variants:[{begin:/_{2}(?!\s)/,end:/_{2}/},{begin:/\*{2}(?!\s)/,end:/\*{2}/}] -},i={className:"emphasis",contains:[],variants:[{begin:/\*(?![*\s])/,end:/\*/},{ -begin:/_(?![_\s])/,end:/_/,relevance:0}]},r=e.inherit(a,{contains:[] -}),s=e.inherit(i,{contains:[]});a.contains.push(s),i.contains.push(r) -;let o=[n,t];return[a,i,r,s].forEach((e=>{e.contains=e.contains.concat(o) -})),o=o.concat(a,i),{name:"Markdown",aliases:["md","mkdown","mkd"],contains:[{ -className:"section",variants:[{begin:"^#{1,6}",end:"$",contains:o},{ -begin:"(?=^.+?\\n[=-]{2,}$)",contains:[{begin:"^[=-]*$"},{begin:"^",end:"\\n", -contains:o}]}]},n,{className:"bullet",begin:"^[ \t]*([*+-]|(\\d+\\.))(?=\\s+)", -end:"\\s+",excludeEnd:!0},a,i,{className:"quote",begin:"^>\\s+",contains:o, -end:"$"},{className:"code",variants:[{begin:"(`{3,})[^`](.|\\n)*?\\1`*[ ]*"},{ -begin:"(~{3,})[^~](.|\\n)*?\\1~*[ ]*"},{begin:"```",end:"```+[ ]*$"},{ -begin:"~~~",end:"~~~+[ ]*$"},{begin:"`.+?`"},{begin:"(?=^( {4}|\\t))", -contains:[{begin:"^( {4}|\\t)",end:"(\\n)$"}],relevance:0}]},{ -begin:"^[-\\*]{3,}",end:"$"},t,{begin:/^\[[^\n]+\]:/,returnBegin:!0,contains:[{ -className:"symbol",begin:/\[/,end:/\]/,excludeBegin:!0,excludeEnd:!0},{ -className:"link",begin:/:\s*/,end:/$/,excludeBegin:!0}]}]}},grmr_objectivec:e=>{ -const n=/[a-zA-Z@][a-zA-Z0-9_]*/,t={$pattern:n, -keyword:["@interface","@class","@protocol","@implementation"]};return{ -name:"Objective-C",aliases:["mm","objc","obj-c","obj-c++","objective-c++"], -keywords:{"variable.language":["this","super"],$pattern:n, -keyword:["while","export","sizeof","typedef","const","struct","for","union","volatile","static","mutable","if","do","return","goto","enum","else","break","extern","asm","case","default","register","explicit","typename","switch","continue","inline","readonly","assign","readwrite","self","@synchronized","id","typeof","nonatomic","IBOutlet","IBAction","strong","weak","copy","in","out","inout","bycopy","byref","oneway","__strong","__weak","__block","__autoreleasing","@private","@protected","@public","@try","@property","@end","@throw","@catch","@finally","@autoreleasepool","@synthesize","@dynamic","@selector","@optional","@required","@encode","@package","@import","@defs","@compatibility_alias","__bridge","__bridge_transfer","__bridge_retained","__bridge_retain","__covariant","__contravariant","__kindof","_Nonnull","_Nullable","_Null_unspecified","__FUNCTION__","__PRETTY_FUNCTION__","__attribute__","getter","setter","retain","unsafe_unretained","nonnull","nullable","null_unspecified","null_resettable","class","instancetype","NS_DESIGNATED_INITIALIZER","NS_UNAVAILABLE","NS_REQUIRES_SUPER","NS_RETURNS_INNER_POINTER","NS_INLINE","NS_AVAILABLE","NS_DEPRECATED","NS_ENUM","NS_OPTIONS","NS_SWIFT_UNAVAILABLE","NS_ASSUME_NONNULL_BEGIN","NS_ASSUME_NONNULL_END","NS_REFINED_FOR_SWIFT","NS_SWIFT_NAME","NS_SWIFT_NOTHROW","NS_DURING","NS_HANDLER","NS_ENDHANDLER","NS_VALUERETURN","NS_VOIDRETURN"], -literal:["false","true","FALSE","TRUE","nil","YES","NO","NULL"], -built_in:["dispatch_once_t","dispatch_queue_t","dispatch_sync","dispatch_async","dispatch_once"], -type:["int","float","char","unsigned","signed","short","long","double","wchar_t","unichar","void","bool","BOOL","id|0","_Bool"] -},illegal:"/,end:/$/,illegal:"\\n" -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{className:"class", -begin:"("+t.keyword.join("|")+")\\b",end:/(\{|$)/,excludeEnd:!0,keywords:t, -contains:[e.UNDERSCORE_TITLE_MODE]},{begin:"\\."+e.UNDERSCORE_IDENT_RE, -relevance:0}]}},grmr_perl:e=>{const n=e.regex,t=/[dualxmsipngr]{0,12}/,a={ -$pattern:/[\w.]+/, -keyword:"abs accept alarm and atan2 bind binmode bless break caller chdir chmod chomp chop chown chr chroot close closedir connect continue cos crypt dbmclose dbmopen defined delete die do dump each else elsif endgrent endhostent endnetent endprotoent endpwent endservent eof eval exec exists exit exp fcntl fileno flock for foreach fork format formline getc getgrent getgrgid getgrnam gethostbyaddr gethostbyname gethostent getlogin getnetbyaddr getnetbyname getnetent getpeername getpgrp getpriority getprotobyname getprotobynumber getprotoent getpwent getpwnam getpwuid getservbyname getservbyport getservent getsockname getsockopt given glob gmtime goto grep gt hex if index int ioctl join keys kill last lc lcfirst length link listen local localtime log lstat lt ma map mkdir msgctl msgget msgrcv msgsnd my ne next no not oct open opendir or ord our pack package pipe pop pos print printf prototype push q|0 qq quotemeta qw qx rand read readdir readline readlink readpipe recv redo ref rename require reset return reverse rewinddir rindex rmdir say scalar seek seekdir select semctl semget semop send setgrent sethostent setnetent setpgrp setpriority setprotoent setpwent setservent setsockopt shift shmctl shmget shmread shmwrite shutdown sin sleep socket socketpair sort splice split sprintf sqrt srand stat state study sub substr symlink syscall sysopen sysread sysseek system syswrite tell telldir tie tied time times tr truncate uc ucfirst umask undef unless unlink unpack unshift untie until use utime values vec wait waitpid wantarray warn when while write x|0 xor y|0" -},i={className:"subst",begin:"[$@]\\{",end:"\\}",keywords:a},r={begin:/->\{/, -end:/\}/},s={variants:[{begin:/\$\d/},{ -begin:n.concat(/[$%@](\^\w\b|#\w+(::\w+)*|\{\w+\}|\w+(::\w*)*)/,"(?![A-Za-z])(?![@$%])") -},{begin:/[$%@][^\s\w{]/,relevance:0}] -},o=[e.BACKSLASH_ESCAPE,i,s],l=[/!/,/\//,/\|/,/\?/,/'/,/"/,/#/],c=(e,a,i="\\1")=>{ -const r="\\1"===i?i:n.concat(i,a) -;return n.concat(n.concat("(?:",e,")"),a,/(?:\\.|[^\\\/])*?/,r,/(?:\\.|[^\\\/])*?/,i,t) -},d=(e,a,i)=>n.concat(n.concat("(?:",e,")"),a,/(?:\\.|[^\\\/])*?/,i,t),g=[s,e.HASH_COMMENT_MODE,e.COMMENT(/^=\w/,/=cut/,{ -endsWithParent:!0}),r,{className:"string",contains:o,variants:[{ -begin:"q[qwxr]?\\s*\\(",end:"\\)",relevance:5},{begin:"q[qwxr]?\\s*\\[", -end:"\\]",relevance:5},{begin:"q[qwxr]?\\s*\\{",end:"\\}",relevance:5},{ -begin:"q[qwxr]?\\s*\\|",end:"\\|",relevance:5},{begin:"q[qwxr]?\\s*<",end:">", -relevance:5},{begin:"qw\\s+q",end:"q",relevance:5},{begin:"'",end:"'", -contains:[e.BACKSLASH_ESCAPE]},{begin:'"',end:'"'},{begin:"`",end:"`", -contains:[e.BACKSLASH_ESCAPE]},{begin:/\{\w+\}/,relevance:0},{ -begin:"-?\\w+\\s*=>",relevance:0}]},{className:"number", -begin:"(\\b0[0-7_]+)|(\\b0x[0-9a-fA-F_]+)|(\\b[1-9][0-9_]*(\\.[0-9_]+)?)|[0_]\\b", -relevance:0},{ -begin:"(\\/\\/|"+e.RE_STARTERS_RE+"|\\b(split|return|print|reverse|grep)\\b)\\s*", -keywords:"split return print reverse grep",relevance:0, -contains:[e.HASH_COMMENT_MODE,{className:"regexp",variants:[{ -begin:c("s|tr|y",n.either(...l,{capture:!0}))},{begin:c("s|tr|y","\\(","\\)")},{ -begin:c("s|tr|y","\\[","\\]")},{begin:c("s|tr|y","\\{","\\}")}],relevance:2},{ -className:"regexp",variants:[{begin:/(m|qr)\/\//,relevance:0},{ -begin:d("(?:m|qr)?",/\//,/\//)},{begin:d("m|qr",n.either(...l,{capture:!0 -}),/\1/)},{begin:d("m|qr",/\(/,/\)/)},{begin:d("m|qr",/\[/,/\]/)},{ -begin:d("m|qr",/\{/,/\}/)}]}]},{className:"function",beginKeywords:"sub", -end:"(\\s*\\(.*?\\))?[;{]",excludeEnd:!0,relevance:5,contains:[e.TITLE_MODE]},{ -begin:"-\\w\\b",relevance:0},{begin:"^__DATA__$",end:"^__END__$", -subLanguage:"mojolicious",contains:[{begin:"^@@.*",end:"$",className:"comment"}] -}];return i.contains=g,r.contains=g,{name:"Perl",aliases:["pl","pm"],keywords:a, -contains:g}},grmr_php:e=>{ -const n=e.regex,t=/(?![A-Za-z0-9])(?![$])/,a=n.concat(/[a-zA-Z_\x7f-\xff][a-zA-Z0-9_\x7f-\xff]*/,t),i=n.concat(/(\\?[A-Z][a-z0-9_\x7f-\xff]+|\\?[A-Z]+(?=[A-Z][a-z0-9_\x7f-\xff])){1,}/,t),r={ -scope:"variable",match:"\\$+"+a},s={scope:"subst",variants:[{begin:/\$\w+/},{ -begin:/\{\$/,end:/\}/}]},o=e.inherit(e.APOS_STRING_MODE,{illegal:null -}),l="[ \t\n]",c={scope:"string",variants:[e.inherit(e.QUOTE_STRING_MODE,{ -illegal:null,contains:e.QUOTE_STRING_MODE.contains.concat(s)}),o,{ -begin:/<<<[ \t]*(?:(\w+)|"(\w+)")\n/,end:/[ \t]*(\w+)\b/, -contains:e.QUOTE_STRING_MODE.contains.concat(s),"on:begin":(e,n)=>{ -n.data._beginMatch=e[1]||e[2]},"on:end":(e,n)=>{ -n.data._beginMatch!==e[1]&&n.ignoreMatch()}},e.END_SAME_AS_BEGIN({ -begin:/<<<[ \t]*'(\w+)'\n/,end:/[ \t]*(\w+)\b/})]},d={scope:"number",variants:[{ -begin:"\\b0[bB][01]+(?:_[01]+)*\\b"},{begin:"\\b0[oO][0-7]+(?:_[0-7]+)*\\b"},{ -begin:"\\b0[xX][\\da-fA-F]+(?:_[\\da-fA-F]+)*\\b"},{ -begin:"(?:\\b\\d+(?:_\\d+)*(\\.(?:\\d+(?:_\\d+)*))?|\\B\\.\\d+)(?:[eE][+-]?\\d+)?" -}],relevance:0 -},g=["false","null","true"],u=["__CLASS__","__DIR__","__FILE__","__FUNCTION__","__COMPILER_HALT_OFFSET__","__LINE__","__METHOD__","__NAMESPACE__","__TRAIT__","die","echo","exit","include","include_once","print","require","require_once","array","abstract","and","as","binary","bool","boolean","break","callable","case","catch","class","clone","const","continue","declare","default","do","double","else","elseif","empty","enddeclare","endfor","endforeach","endif","endswitch","endwhile","enum","eval","extends","final","finally","float","for","foreach","from","global","goto","if","implements","instanceof","insteadof","int","integer","interface","isset","iterable","list","match|0","mixed","new","never","object","or","private","protected","public","readonly","real","return","string","switch","throw","trait","try","unset","use","var","void","while","xor","yield"],b=["Error|0","AppendIterator","ArgumentCountError","ArithmeticError","ArrayIterator","ArrayObject","AssertionError","BadFunctionCallException","BadMethodCallException","CachingIterator","CallbackFilterIterator","CompileError","Countable","DirectoryIterator","DivisionByZeroError","DomainException","EmptyIterator","ErrorException","Exception","FilesystemIterator","FilterIterator","GlobIterator","InfiniteIterator","InvalidArgumentException","IteratorIterator","LengthException","LimitIterator","LogicException","MultipleIterator","NoRewindIterator","OutOfBoundsException","OutOfRangeException","OuterIterator","OverflowException","ParentIterator","ParseError","RangeException","RecursiveArrayIterator","RecursiveCachingIterator","RecursiveCallbackFilterIterator","RecursiveDirectoryIterator","RecursiveFilterIterator","RecursiveIterator","RecursiveIteratorIterator","RecursiveRegexIterator","RecursiveTreeIterator","RegexIterator","RuntimeException","SeekableIterator","SplDoublyLinkedList","SplFileInfo","SplFileObject","SplFixedArray","SplHeap","SplMaxHeap","SplMinHeap","SplObjectStorage","SplObserver","SplPriorityQueue","SplQueue","SplStack","SplSubject","SplTempFileObject","TypeError","UnderflowException","UnexpectedValueException","UnhandledMatchError","ArrayAccess","BackedEnum","Closure","Fiber","Generator","Iterator","IteratorAggregate","Serializable","Stringable","Throwable","Traversable","UnitEnum","WeakReference","WeakMap","Directory","__PHP_Incomplete_Class","parent","php_user_filter","self","static","stdClass"],m={ -keyword:u,literal:(e=>{const n=[];return e.forEach((e=>{ -n.push(e),e.toLowerCase()===e?n.push(e.toUpperCase()):n.push(e.toLowerCase()) -})),n})(g),built_in:b},p=e=>e.map((e=>e.replace(/\|\d+$/,""))),_={variants:[{ -match:[/new/,n.concat(l,"+"),n.concat("(?!",p(b).join("\\b|"),"\\b)"),i],scope:{ -1:"keyword",4:"title.class"}}]},h=n.concat(a,"\\b(?!\\()"),f={variants:[{ -match:[n.concat(/::/,n.lookahead(/(?!class\b)/)),h],scope:{2:"variable.constant" -}},{match:[/::/,/class/],scope:{2:"variable.language"}},{ -match:[i,n.concat(/::/,n.lookahead(/(?!class\b)/)),h],scope:{1:"title.class", -3:"variable.constant"}},{match:[i,n.concat("::",n.lookahead(/(?!class\b)/))], -scope:{1:"title.class"}},{match:[i,/::/,/class/],scope:{1:"title.class", -3:"variable.language"}}]},E={scope:"attr", -match:n.concat(a,n.lookahead(":"),n.lookahead(/(?!::)/))},y={relevance:0, -begin:/\(/,end:/\)/,keywords:m,contains:[E,r,f,e.C_BLOCK_COMMENT_MODE,c,d,_] -},N={relevance:0, -match:[/\b/,n.concat("(?!fn\\b|function\\b|",p(u).join("\\b|"),"|",p(b).join("\\b|"),"\\b)"),a,n.concat(l,"*"),n.lookahead(/(?=\()/)], -scope:{3:"title.function.invoke"},contains:[y]};y.contains.push(N) -;const w=[E,f,e.C_BLOCK_COMMENT_MODE,c,d,_];return{case_insensitive:!1, -keywords:m,contains:[{begin:n.concat(/#\[\s*/,i),beginScope:"meta",end:/]/, -endScope:"meta",keywords:{literal:g,keyword:["new","array"]},contains:[{ -begin:/\[/,end:/]/,keywords:{literal:g,keyword:["new","array"]}, -contains:["self",...w]},...w,{scope:"meta",match:i}] -},e.HASH_COMMENT_MODE,e.COMMENT("//","$"),e.COMMENT("/\\*","\\*/",{contains:[{ -scope:"doctag",match:"@[A-Za-z]+"}]}),{match:/__halt_compiler\(\);/, -keywords:"__halt_compiler",starts:{scope:"comment",end:e.MATCH_NOTHING_RE, -contains:[{match:/\?>/,scope:"meta",endsParent:!0}]}},{scope:"meta",variants:[{ -begin:/<\?php/,relevance:10},{begin:/<\?=/},{begin:/<\?/,relevance:.1},{ -begin:/\?>/}]},{scope:"variable.language",match:/\$this\b/},r,N,f,{ -match:[/const/,/\s/,a],scope:{1:"keyword",3:"variable.constant"}},_,{ -scope:"function",relevance:0,beginKeywords:"fn function",end:/[;{]/, -excludeEnd:!0,illegal:"[$%\\[]",contains:[{beginKeywords:"use" -},e.UNDERSCORE_TITLE_MODE,{begin:"=>",endsParent:!0},{scope:"params", -begin:"\\(",end:"\\)",excludeBegin:!0,excludeEnd:!0,keywords:m, -contains:["self",r,f,e.C_BLOCK_COMMENT_MODE,c,d]}]},{scope:"class",variants:[{ -beginKeywords:"enum",illegal:/[($"]/},{beginKeywords:"class interface trait", -illegal:/[:($"]/}],relevance:0,end:/\{/,excludeEnd:!0,contains:[{ -beginKeywords:"extends implements"},e.UNDERSCORE_TITLE_MODE]},{ -beginKeywords:"namespace",relevance:0,end:";",illegal:/[.']/, -contains:[e.inherit(e.UNDERSCORE_TITLE_MODE,{scope:"title.class"})]},{ -beginKeywords:"use",relevance:0,end:";",contains:[{ -match:/\b(as|const|function)\b/,scope:"keyword"},e.UNDERSCORE_TITLE_MODE]},c,d]} -},grmr_php_template:e=>({name:"PHP template",subLanguage:"xml",contains:[{ -begin:/<\?(php|=)?/,end:/\?>/,subLanguage:"php",contains:[{begin:"/\\*", -end:"\\*/",skip:!0},{begin:'b"',end:'"',skip:!0},{begin:"b'",end:"'",skip:!0 -},e.inherit(e.APOS_STRING_MODE,{illegal:null,className:null,contains:null, -skip:!0}),e.inherit(e.QUOTE_STRING_MODE,{illegal:null,className:null, -contains:null,skip:!0})]}]}),grmr_plaintext:e=>({name:"Plain text", -aliases:["text","txt"],disableAutodetect:!0}),grmr_python:e=>{ -const n=e.regex,t=/[\p{XID_Start}_]\p{XID_Continue}*/u,a=["and","as","assert","async","await","break","case","class","continue","def","del","elif","else","except","finally","for","from","global","if","import","in","is","lambda","match","nonlocal|10","not","or","pass","raise","return","try","while","with","yield"],i={ -$pattern:/[A-Za-z]\w+|__\w+__/,keyword:a, -built_in:["__import__","abs","all","any","ascii","bin","bool","breakpoint","bytearray","bytes","callable","chr","classmethod","compile","complex","delattr","dict","dir","divmod","enumerate","eval","exec","filter","float","format","frozenset","getattr","globals","hasattr","hash","help","hex","id","input","int","isinstance","issubclass","iter","len","list","locals","map","max","memoryview","min","next","object","oct","open","ord","pow","print","property","range","repr","reversed","round","set","setattr","slice","sorted","staticmethod","str","sum","super","tuple","type","vars","zip"], -literal:["__debug__","Ellipsis","False","None","NotImplemented","True"], -type:["Any","Callable","Coroutine","Dict","List","Literal","Generic","Optional","Sequence","Set","Tuple","Type","Union"] -},r={className:"meta",begin:/^(>>>|\.\.\.) /},s={className:"subst",begin:/\{/, -end:/\}/,keywords:i,illegal:/#/},o={begin:/\{\{/,relevance:0},l={ -className:"string",contains:[e.BACKSLASH_ESCAPE],variants:[{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,r],relevance:10},{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?"""/,end:/"""/, -contains:[e.BACKSLASH_ESCAPE,r],relevance:10},{ -begin:/([fF][rR]|[rR][fF]|[fF])'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,r,o,s]},{begin:/([fF][rR]|[rR][fF]|[fF])"""/, -end:/"""/,contains:[e.BACKSLASH_ESCAPE,r,o,s]},{begin:/([uU]|[rR])'/,end:/'/, -relevance:10},{begin:/([uU]|[rR])"/,end:/"/,relevance:10},{ -begin:/([bB]|[bB][rR]|[rR][bB])'/,end:/'/},{begin:/([bB]|[bB][rR]|[rR][bB])"/, -end:/"/},{begin:/([fF][rR]|[rR][fF]|[fF])'/,end:/'/, -contains:[e.BACKSLASH_ESCAPE,o,s]},{begin:/([fF][rR]|[rR][fF]|[fF])"/,end:/"/, -contains:[e.BACKSLASH_ESCAPE,o,s]},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE] -},c="[0-9](_?[0-9])*",d=`(\\b(${c}))?\\.(${c})|\\b(${c})\\.`,g="\\b|"+a.join("|"),u={ -className:"number",relevance:0,variants:[{ -begin:`(\\b(${c})|(${d}))[eE][+-]?(${c})[jJ]?(?=${g})`},{begin:`(${d})[jJ]?`},{ -begin:`\\b([1-9](_?[0-9])*|0+(_?0)*)[lLjJ]?(?=${g})`},{ -begin:`\\b0[bB](_?[01])+[lL]?(?=${g})`},{begin:`\\b0[oO](_?[0-7])+[lL]?(?=${g})` -},{begin:`\\b0[xX](_?[0-9a-fA-F])+[lL]?(?=${g})`},{begin:`\\b(${c})[jJ](?=${g})` -}]},b={className:"comment",begin:n.lookahead(/# type:/),end:/$/,keywords:i, -contains:[{begin:/# type:/},{begin:/#/,end:/\b\B/,endsWithParent:!0}]},m={ -className:"params",variants:[{className:"",begin:/\(\s*\)/,skip:!0},{begin:/\(/, -end:/\)/,excludeBegin:!0,excludeEnd:!0,keywords:i, -contains:["self",r,u,l,e.HASH_COMMENT_MODE]}]};return s.contains=[l,u,r],{ -name:"Python",aliases:["py","gyp","ipython"],unicodeRegex:!0,keywords:i, -illegal:/(<\/|\?)|=>/,contains:[r,u,{begin:/\bself\b/},{beginKeywords:"if", -relevance:0},l,b,e.HASH_COMMENT_MODE,{match:[/\bdef/,/\s+/,t],scope:{ -1:"keyword",3:"title.function"},contains:[m]},{variants:[{ -match:[/\bclass/,/\s+/,t,/\s*/,/\(\s*/,t,/\s*\)/]},{match:[/\bclass/,/\s+/,t]}], -scope:{1:"keyword",3:"title.class",6:"title.class.inherited"}},{ -className:"meta",begin:/^[\t ]*@/,end:/(?=#)|$/,contains:[u,m,l]}]}}, -grmr_python_repl:e=>({aliases:["pycon"],contains:[{className:"meta.prompt", -starts:{end:/ |$/,starts:{end:"$",subLanguage:"python"}},variants:[{ -begin:/^>>>(?=[ ]|$)/},{begin:/^\.\.\.(?=[ ]|$)/}]}]}),grmr_r:e=>{ -const n=e.regex,t=/(?:(?:[a-zA-Z]|\.[._a-zA-Z])[._a-zA-Z0-9]*)|\.(?!\d)/,a=n.either(/0[xX][0-9a-fA-F]+\.[0-9a-fA-F]*[pP][+-]?\d+i?/,/0[xX][0-9a-fA-F]+(?:[pP][+-]?\d+)?[Li]?/,/(?:\d+(?:\.\d*)?|\.\d+)(?:[eE][+-]?\d+)?[Li]?/),i=/[=!<>:]=|\|\||&&|:::?|<-|<<-|->>|->|\|>|[-+*\/?!$&|:<=>@^~]|\*\*/,r=n.either(/[()]/,/[{}]/,/\[\[/,/[[\]]/,/\\/,/,/) -;return{name:"R",keywords:{$pattern:t, -keyword:"function if in break next repeat else for while", -literal:"NULL NA TRUE FALSE Inf NaN NA_integer_|10 NA_real_|10 NA_character_|10 NA_complex_|10", -built_in:"LETTERS letters month.abb month.name pi T F abs acos acosh all any anyNA Arg as.call as.character as.complex as.double as.environment as.integer as.logical as.null.default as.numeric as.raw asin asinh atan atanh attr attributes baseenv browser c call ceiling class Conj cos cosh cospi cummax cummin cumprod cumsum digamma dim dimnames emptyenv exp expression floor forceAndCall gamma gc.time globalenv Im interactive invisible is.array is.atomic is.call is.character is.complex is.double is.environment is.expression is.finite is.function is.infinite is.integer is.language is.list is.logical is.matrix is.na is.name is.nan is.null is.numeric is.object is.pairlist is.raw is.recursive is.single is.symbol lazyLoadDBfetch length lgamma list log max min missing Mod names nargs nzchar oldClass on.exit pos.to.env proc.time prod quote range Re rep retracemem return round seq_along seq_len seq.int sign signif sin sinh sinpi sqrt standardGeneric substitute sum switch tan tanh tanpi tracemem trigamma trunc unclass untracemem UseMethod xtfrm" -},contains:[e.COMMENT(/#'/,/$/,{contains:[{scope:"doctag",match:/@examples/, -starts:{end:n.lookahead(n.either(/\n^#'\s*(?=@[a-zA-Z]+)/,/\n^(?!#')/)), -endsParent:!0}},{scope:"doctag",begin:"@param",end:/$/,contains:[{ -scope:"variable",variants:[{match:t},{match:/`(?:\\.|[^`\\])+`/}],endsParent:!0 -}]},{scope:"doctag",match:/@[a-zA-Z]+/},{scope:"keyword",match:/\\[a-zA-Z]+/}] -}),e.HASH_COMMENT_MODE,{scope:"string",contains:[e.BACKSLASH_ESCAPE], -variants:[e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\(/,end:/\)(-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\{/,end:/\}(-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\[/,end:/\](-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\(/,end:/\)(-*)'/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\{/,end:/\}(-*)'/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\[/,end:/\](-*)'/}),{begin:'"',end:'"', -relevance:0},{begin:"'",end:"'",relevance:0}]},{relevance:0,variants:[{scope:{ -1:"operator",2:"number"},match:[i,a]},{scope:{1:"operator",2:"number"}, -match:[/%[^%]*%/,a]},{scope:{1:"punctuation",2:"number"},match:[r,a]},{scope:{ -2:"number"},match:[/[^a-zA-Z0-9._]|^/,a]}]},{scope:{3:"operator"}, -match:[t,/\s+/,/<-/,/\s+/]},{scope:"operator",relevance:0,variants:[{match:i},{ -match:/%[^%]*%/}]},{scope:"punctuation",relevance:0,match:r},{begin:"`",end:"`", -contains:[{begin:/\\./}]}]}},grmr_ruby:e=>{ -const n=e.regex,t="([a-zA-Z_]\\w*[!?=]?|[-+~]@|<<|>>|=~|===?|<=>|[<>]=?|\\*\\*|[-/+%^&*~`|]|\\[\\]=?)",a=n.either(/\b([A-Z]+[a-z0-9]+)+/,/\b([A-Z]+[a-z0-9]+)+[A-Z]+/),i=n.concat(a,/(::\w+)*/),r={ -"variable.constant":["__FILE__","__LINE__","__ENCODING__"], -"variable.language":["self","super"], -keyword:["alias","and","begin","BEGIN","break","case","class","defined","do","else","elsif","end","END","ensure","for","if","in","module","next","not","or","redo","require","rescue","retry","return","then","undef","unless","until","when","while","yield","include","extend","prepend","public","private","protected","raise","throw"], -built_in:["proc","lambda","attr_accessor","attr_reader","attr_writer","define_method","private_constant","module_function"], -literal:["true","false","nil"]},s={className:"doctag",begin:"@[A-Za-z]+"},o={ -begin:"#<",end:">"},l=[e.COMMENT("#","$",{contains:[s] -}),e.COMMENT("^=begin","^=end",{contains:[s],relevance:10 -}),e.COMMENT("^__END__",e.MATCH_NOTHING_RE)],c={className:"subst",begin:/#\{/, -end:/\}/,keywords:r},d={className:"string",contains:[e.BACKSLASH_ESCAPE,c], -variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/},{begin:/`/,end:/`/},{ -begin:/%[qQwWx]?\(/,end:/\)/},{begin:/%[qQwWx]?\[/,end:/\]/},{ -begin:/%[qQwWx]?\{/,end:/\}/},{begin:/%[qQwWx]?/},{begin:/%[qQwWx]?\//, -end:/\//},{begin:/%[qQwWx]?%/,end:/%/},{begin:/%[qQwWx]?-/,end:/-/},{ -begin:/%[qQwWx]?\|/,end:/\|/},{begin:/\B\?(\\\d{1,3})/},{ -begin:/\B\?(\\x[A-Fa-f0-9]{1,2})/},{begin:/\B\?(\\u\{?[A-Fa-f0-9]{1,6}\}?)/},{ -begin:/\B\?(\\M-\\C-|\\M-\\c|\\c\\M-|\\M-|\\C-\\M-)[\x20-\x7e]/},{ -begin:/\B\?\\(c|C-)[\x20-\x7e]/},{begin:/\B\?\\?\S/},{ -begin:n.concat(/<<[-~]?'?/,n.lookahead(/(\w+)(?=\W)[^\n]*\n(?:[^\n]*\n)*?\s*\1\b/)), -contains:[e.END_SAME_AS_BEGIN({begin:/(\w+)/,end:/(\w+)/, -contains:[e.BACKSLASH_ESCAPE,c]})]}]},g="[0-9](_?[0-9])*",u={className:"number", -relevance:0,variants:[{ -begin:`\\b([1-9](_?[0-9])*|0)(\\.(${g}))?([eE][+-]?(${g})|r)?i?\\b`},{ -begin:"\\b0[dD][0-9](_?[0-9])*r?i?\\b"},{begin:"\\b0[bB][0-1](_?[0-1])*r?i?\\b" -},{begin:"\\b0[oO][0-7](_?[0-7])*r?i?\\b"},{ -begin:"\\b0[xX][0-9a-fA-F](_?[0-9a-fA-F])*r?i?\\b"},{ -begin:"\\b0(_?[0-7])+r?i?\\b"}]},b={variants:[{match:/\(\)/},{ -className:"params",begin:/\(/,end:/(?=\))/,excludeBegin:!0,endsParent:!0, -keywords:r}]},m=[d,{variants:[{match:[/class\s+/,i,/\s+<\s+/,i]},{ -match:[/\b(class|module)\s+/,i]}],scope:{2:"title.class", -4:"title.class.inherited"},keywords:r},{match:[/(include|extend)\s+/,i],scope:{ -2:"title.class"},keywords:r},{relevance:0,match:[i,/\.new[. (]/],scope:{ -1:"title.class"}},{relevance:0,match:/\b[A-Z][A-Z_0-9]+\b/, -className:"variable.constant"},{relevance:0,match:a,scope:"title.class"},{ -match:[/def/,/\s+/,t],scope:{1:"keyword",3:"title.function"},contains:[b]},{ -begin:e.IDENT_RE+"::"},{className:"symbol", -begin:e.UNDERSCORE_IDENT_RE+"(!|\\?)?:",relevance:0},{className:"symbol", -begin:":(?!\\s)",contains:[d,{begin:t}],relevance:0},u,{className:"variable", -begin:"(\\$\\W)|((\\$|@@?)(\\w+))(?=[^@$?])(?![A-Za-z])(?![@$?'])"},{ -className:"params",begin:/\|/,end:/\|/,excludeBegin:!0,excludeEnd:!0, -relevance:0,keywords:r},{begin:"("+e.RE_STARTERS_RE+"|unless)\\s*", -keywords:"unless",contains:[{className:"regexp",contains:[e.BACKSLASH_ESCAPE,c], -illegal:/\n/,variants:[{begin:"/",end:"/[a-z]*"},{begin:/%r\{/,end:/\}[a-z]*/},{ -begin:"%r\\(",end:"\\)[a-z]*"},{begin:"%r!",end:"![a-z]*"},{begin:"%r\\[", -end:"\\][a-z]*"}]}].concat(o,l),relevance:0}].concat(o,l) -;c.contains=m,b.contains=m;const p=[{begin:/^\s*=>/,starts:{end:"$",contains:m} -},{className:"meta.prompt", -begin:"^([>?]>|[\\w#]+\\(\\w+\\):\\d+:\\d+[>*]|(\\w+-)?\\d+\\.\\d+\\.\\d+(p\\d+)?[^\\d][^>]+>)(?=[ ])", -starts:{end:"$",keywords:r,contains:m}}];return l.unshift(o),{name:"Ruby", -aliases:["rb","gemspec","podspec","thor","irb"],keywords:r,illegal:/\/\*/, -contains:[e.SHEBANG({binary:"ruby"})].concat(p).concat(l).concat(m)}}, -grmr_rust:e=>{const n=e.regex,t={className:"title.function.invoke",relevance:0, -begin:n.concat(/\b/,/(?!let|for|while|if|else|match\b)/,e.IDENT_RE,n.lookahead(/\s*\(/)) -},a="([ui](8|16|32|64|128|size)|f(32|64))?",i=["drop ","Copy","Send","Sized","Sync","Drop","Fn","FnMut","FnOnce","ToOwned","Clone","Debug","PartialEq","PartialOrd","Eq","Ord","AsRef","AsMut","Into","From","Default","Iterator","Extend","IntoIterator","DoubleEndedIterator","ExactSizeIterator","SliceConcatExt","ToString","assert!","assert_eq!","bitflags!","bytes!","cfg!","col!","concat!","concat_idents!","debug_assert!","debug_assert_eq!","env!","eprintln!","panic!","file!","format!","format_args!","include_bytes!","include_str!","line!","local_data_key!","module_path!","option_env!","print!","println!","select!","stringify!","try!","unimplemented!","unreachable!","vec!","write!","writeln!","macro_rules!","assert_ne!","debug_assert_ne!"],r=["i8","i16","i32","i64","i128","isize","u8","u16","u32","u64","u128","usize","f32","f64","str","char","bool","Box","Option","Result","String","Vec"] -;return{name:"Rust",aliases:["rs"],keywords:{$pattern:e.IDENT_RE+"!?",type:r, -keyword:["abstract","as","async","await","become","box","break","const","continue","crate","do","dyn","else","enum","extern","false","final","fn","for","if","impl","in","let","loop","macro","match","mod","move","mut","override","priv","pub","ref","return","self","Self","static","struct","super","trait","true","try","type","typeof","unsafe","unsized","use","virtual","where","while","yield"], -literal:["true","false","Some","None","Ok","Err"],built_in:i},illegal:""},t]}}, -grmr_scss:e=>{const n=ie(e),t=le,a=oe,i="@[a-z-]+",r={className:"variable", -begin:"(\\$[a-zA-Z-][a-zA-Z0-9_-]*)\\b",relevance:0};return{name:"SCSS", -case_insensitive:!0,illegal:"[=/|']", -contains:[e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,n.CSS_NUMBER_MODE,{ -className:"selector-id",begin:"#[A-Za-z0-9_-]+",relevance:0},{ -className:"selector-class",begin:"\\.[A-Za-z0-9_-]+",relevance:0 -},n.ATTRIBUTE_SELECTOR_MODE,{className:"selector-tag", -begin:"\\b("+re.join("|")+")\\b",relevance:0},{className:"selector-pseudo", -begin:":("+a.join("|")+")"},{className:"selector-pseudo", -begin:":(:)?("+t.join("|")+")"},r,{begin:/\(/,end:/\)/, -contains:[n.CSS_NUMBER_MODE]},n.CSS_VARIABLE,{className:"attribute", -begin:"\\b("+ce.join("|")+")\\b"},{ -begin:"\\b(whitespace|wait|w-resize|visible|vertical-text|vertical-ideographic|uppercase|upper-roman|upper-alpha|underline|transparent|top|thin|thick|text|text-top|text-bottom|tb-rl|table-header-group|table-footer-group|sw-resize|super|strict|static|square|solid|small-caps|separate|se-resize|scroll|s-resize|rtl|row-resize|ridge|right|repeat|repeat-y|repeat-x|relative|progress|pointer|overline|outside|outset|oblique|nowrap|not-allowed|normal|none|nw-resize|no-repeat|no-drop|newspaper|ne-resize|n-resize|move|middle|medium|ltr|lr-tb|lowercase|lower-roman|lower-alpha|loose|list-item|line|line-through|line-edge|lighter|left|keep-all|justify|italic|inter-word|inter-ideograph|inside|inset|inline|inline-block|inherit|inactive|ideograph-space|ideograph-parenthesis|ideograph-numeric|ideograph-alpha|horizontal|hidden|help|hand|groove|fixed|ellipsis|e-resize|double|dotted|distribute|distribute-space|distribute-letter|distribute-all-lines|disc|disabled|default|decimal|dashed|crosshair|collapse|col-resize|circle|char|center|capitalize|break-word|break-all|bottom|both|bolder|bold|block|bidi-override|below|baseline|auto|always|all-scroll|absolute|table|table-cell)\\b" -},{begin:/:/,end:/[;}{]/,relevance:0, -contains:[n.BLOCK_COMMENT,r,n.HEXCOLOR,n.CSS_NUMBER_MODE,e.QUOTE_STRING_MODE,e.APOS_STRING_MODE,n.IMPORTANT,n.FUNCTION_DISPATCH] -},{begin:"@(page|font-face)",keywords:{$pattern:i,keyword:"@page @font-face"}},{ -begin:"@",end:"[{;]",returnBegin:!0,keywords:{$pattern:/[a-z-]+/, -keyword:"and or not only",attribute:se.join(" ")},contains:[{begin:i, -className:"keyword"},{begin:/[a-z-]+(?=:)/,className:"attribute" -},r,e.QUOTE_STRING_MODE,e.APOS_STRING_MODE,n.HEXCOLOR,n.CSS_NUMBER_MODE] -},n.FUNCTION_DISPATCH]}},grmr_shell:e=>({name:"Shell Session", -aliases:["console","shellsession"],contains:[{className:"meta.prompt", -begin:/^\s{0,3}[/~\w\d[\]()@-]*[>%$#][ ]?/,starts:{end:/[^\\](?=\s*$)/, -subLanguage:"bash"}}]}),grmr_sql:e=>{ -const n=e.regex,t=e.COMMENT("--","$"),a=["true","false","unknown"],i=["bigint","binary","blob","boolean","char","character","clob","date","dec","decfloat","decimal","float","int","integer","interval","nchar","nclob","national","numeric","real","row","smallint","time","timestamp","varchar","varying","varbinary"],r=["abs","acos","array_agg","asin","atan","avg","cast","ceil","ceiling","coalesce","corr","cos","cosh","count","covar_pop","covar_samp","cume_dist","dense_rank","deref","element","exp","extract","first_value","floor","json_array","json_arrayagg","json_exists","json_object","json_objectagg","json_query","json_table","json_table_primitive","json_value","lag","last_value","lead","listagg","ln","log","log10","lower","max","min","mod","nth_value","ntile","nullif","percent_rank","percentile_cont","percentile_disc","position","position_regex","power","rank","regr_avgx","regr_avgy","regr_count","regr_intercept","regr_r2","regr_slope","regr_sxx","regr_sxy","regr_syy","row_number","sin","sinh","sqrt","stddev_pop","stddev_samp","substring","substring_regex","sum","tan","tanh","translate","translate_regex","treat","trim","trim_array","unnest","upper","value_of","var_pop","var_samp","width_bucket"],s=["create table","insert into","primary key","foreign key","not null","alter table","add constraint","grouping sets","on overflow","character set","respect nulls","ignore nulls","nulls first","nulls last","depth first","breadth first"],o=r,l=["abs","acos","all","allocate","alter","and","any","are","array","array_agg","array_max_cardinality","as","asensitive","asin","asymmetric","at","atan","atomic","authorization","avg","begin","begin_frame","begin_partition","between","bigint","binary","blob","boolean","both","by","call","called","cardinality","cascaded","case","cast","ceil","ceiling","char","char_length","character","character_length","check","classifier","clob","close","coalesce","collate","collect","column","commit","condition","connect","constraint","contains","convert","copy","corr","corresponding","cos","cosh","count","covar_pop","covar_samp","create","cross","cube","cume_dist","current","current_catalog","current_date","current_default_transform_group","current_path","current_role","current_row","current_schema","current_time","current_timestamp","current_path","current_role","current_transform_group_for_type","current_user","cursor","cycle","date","day","deallocate","dec","decimal","decfloat","declare","default","define","delete","dense_rank","deref","describe","deterministic","disconnect","distinct","double","drop","dynamic","each","element","else","empty","end","end_frame","end_partition","end-exec","equals","escape","every","except","exec","execute","exists","exp","external","extract","false","fetch","filter","first_value","float","floor","for","foreign","frame_row","free","from","full","function","fusion","get","global","grant","group","grouping","groups","having","hold","hour","identity","in","indicator","initial","inner","inout","insensitive","insert","int","integer","intersect","intersection","interval","into","is","join","json_array","json_arrayagg","json_exists","json_object","json_objectagg","json_query","json_table","json_table_primitive","json_value","lag","language","large","last_value","lateral","lead","leading","left","like","like_regex","listagg","ln","local","localtime","localtimestamp","log","log10","lower","match","match_number","match_recognize","matches","max","member","merge","method","min","minute","mod","modifies","module","month","multiset","national","natural","nchar","nclob","new","no","none","normalize","not","nth_value","ntile","null","nullif","numeric","octet_length","occurrences_regex","of","offset","old","omit","on","one","only","open","or","order","out","outer","over","overlaps","overlay","parameter","partition","pattern","per","percent","percent_rank","percentile_cont","percentile_disc","period","portion","position","position_regex","power","precedes","precision","prepare","primary","procedure","ptf","range","rank","reads","real","recursive","ref","references","referencing","regr_avgx","regr_avgy","regr_count","regr_intercept","regr_r2","regr_slope","regr_sxx","regr_sxy","regr_syy","release","result","return","returns","revoke","right","rollback","rollup","row","row_number","rows","running","savepoint","scope","scroll","search","second","seek","select","sensitive","session_user","set","show","similar","sin","sinh","skip","smallint","some","specific","specifictype","sql","sqlexception","sqlstate","sqlwarning","sqrt","start","static","stddev_pop","stddev_samp","submultiset","subset","substring","substring_regex","succeeds","sum","symmetric","system","system_time","system_user","table","tablesample","tan","tanh","then","time","timestamp","timezone_hour","timezone_minute","to","trailing","translate","translate_regex","translation","treat","trigger","trim","trim_array","true","truncate","uescape","union","unique","unknown","unnest","update","upper","user","using","value","values","value_of","var_pop","var_samp","varbinary","varchar","varying","versioning","when","whenever","where","width_bucket","window","with","within","without","year","add","asc","collation","desc","final","first","last","view"].filter((e=>!r.includes(e))),c={ -begin:n.concat(/\b/,n.either(...o),/\s*\(/),relevance:0,keywords:{built_in:o}} -;return{name:"SQL",case_insensitive:!0,illegal:/[{}]|<\//,keywords:{ -$pattern:/\b[\w\.]+/,keyword:((e,{exceptions:n,when:t}={})=>{const a=t -;return n=n||[],e.map((e=>e.match(/\|\d+$/)||n.includes(e)?e:a(e)?e+"|0":e)) -})(l,{when:e=>e.length<3}),literal:a,type:i, -built_in:["current_catalog","current_date","current_default_transform_group","current_path","current_role","current_schema","current_transform_group_for_type","current_user","session_user","system_time","system_user","current_time","localtime","current_timestamp","localtimestamp"] -},contains:[{begin:n.either(...s),relevance:0,keywords:{$pattern:/[\w\.]+/, -keyword:l.concat(s),literal:a,type:i}},{className:"type", -begin:n.either("double precision","large object","with timezone","without timezone") -},c,{className:"variable",begin:/@[a-z0-9][a-z0-9_]*/},{className:"string", -variants:[{begin:/'/,end:/'/,contains:[{begin:/''/}]}]},{begin:/"/,end:/"/, -contains:[{begin:/""/}]},e.C_NUMBER_MODE,e.C_BLOCK_COMMENT_MODE,t,{ -className:"operator",begin:/[-+*/=%^~]|&&?|\|\|?|!=?|<(?:=>?|<|>)?|>[>=]?/, -relevance:0}]}},grmr_swift:e=>{const n={match:/\s+/,relevance:0 -},t=e.COMMENT("/\\*","\\*/",{contains:["self"]}),a=[e.C_LINE_COMMENT_MODE,t],i={ -match:[/\./,m(...xe,...Me)],className:{2:"keyword"}},r={match:b(/\./,m(...Ae)), -relevance:0},s=Ae.filter((e=>"string"==typeof e)).concat(["_|0"]),o={variants:[{ -className:"keyword", -match:m(...Ae.filter((e=>"string"!=typeof e)).concat(Se).map(ke),...Me)}]},l={ -$pattern:m(/\b\w+/,/#\w+/),keyword:s.concat(Re),literal:Ce},c=[i,r,o],g=[{ -match:b(/\./,m(...De)),relevance:0},{className:"built_in", -match:b(/\b/,m(...De),/(?=\()/)}],u={match:/->/,relevance:0},p=[u,{ -className:"operator",relevance:0,variants:[{match:Be},{match:`\\.(\\.|${Le})+`}] -}],_="([0-9]_*)+",h="([0-9a-fA-F]_*)+",f={className:"number",relevance:0, -variants:[{match:`\\b(${_})(\\.(${_}))?([eE][+-]?(${_}))?\\b`},{ -match:`\\b0x(${h})(\\.(${h}))?([pP][+-]?(${_}))?\\b`},{match:/\b0o([0-7]_*)+\b/ -},{match:/\b0b([01]_*)+\b/}]},E=(e="")=>({className:"subst",variants:[{ -match:b(/\\/,e,/[0\\tnr"']/)},{match:b(/\\/,e,/u\{[0-9a-fA-F]{1,8}\}/)}] -}),y=(e="")=>({className:"subst",match:b(/\\/,e,/[\t ]*(?:[\r\n]|\r\n)/) -}),N=(e="")=>({className:"subst",label:"interpol",begin:b(/\\/,e,/\(/),end:/\)/ -}),w=(e="")=>({begin:b(e,/"""/),end:b(/"""/,e),contains:[E(e),y(e),N(e)] -}),v=(e="")=>({begin:b(e,/"/),end:b(/"/,e),contains:[E(e),N(e)]}),O={ -className:"string", -variants:[w(),w("#"),w("##"),w("###"),v(),v("#"),v("##"),v("###")] -},k=[e.BACKSLASH_ESCAPE,{begin:/\[/,end:/\]/,relevance:0, -contains:[e.BACKSLASH_ESCAPE]}],x={begin:/\/[^\s](?=[^/\n]*\/)/,end:/\//, -contains:k},M=e=>{const n=b(e,/\//),t=b(/\//,e);return{begin:n,end:t, -contains:[...k,{scope:"comment",begin:`#(?!.*${t})`,end:/$/}]}},S={ -scope:"regexp",variants:[M("###"),M("##"),M("#"),x]},A={match:b(/`/,Fe,/`/) -},C=[A,{className:"variable",match:/\$\d+/},{className:"variable", -match:`\\$${ze}+`}],T=[{match:/(@|#(un)?)available/,scope:"keyword",starts:{ -contains:[{begin:/\(/,end:/\)/,keywords:Pe,contains:[...p,f,O]}]}},{ -scope:"keyword",match:b(/@/,m(...je))},{scope:"meta",match:b(/@/,Fe)}],R={ -match:d(/\b[A-Z]/),relevance:0,contains:[{className:"type", -match:b(/(AV|CA|CF|CG|CI|CL|CM|CN|CT|MK|MP|MTK|MTL|NS|SCN|SK|UI|WK|XC)/,ze,"+") -},{className:"type",match:Ue,relevance:0},{match:/[?!]+/,relevance:0},{ -match:/\.\.\./,relevance:0},{match:b(/\s+&\s+/,d(Ue)),relevance:0}]},D={ -begin://,keywords:l,contains:[...a,...c,...T,u,R]};R.contains.push(D) -;const I={begin:/\(/,end:/\)/,relevance:0,keywords:l,contains:["self",{ -match:b(Fe,/\s*:/),keywords:"_|0",relevance:0 -},...a,S,...c,...g,...p,f,O,...C,...T,R]},L={begin://, -keywords:"repeat each",contains:[...a,R]},B={begin:/\(/,end:/\)/,keywords:l, -contains:[{begin:m(d(b(Fe,/\s*:/)),d(b(Fe,/\s+/,Fe,/\s*:/))),end:/:/, -relevance:0,contains:[{className:"keyword",match:/\b_\b/},{className:"params", -match:Fe}]},...a,...c,...p,f,O,...T,R,I],endsParent:!0,illegal:/["']/},$={ -match:[/(func|macro)/,/\s+/,m(A.match,Fe,Be)],className:{1:"keyword", -3:"title.function"},contains:[L,B,n],illegal:[/\[/,/%/]},z={ -match:[/\b(?:subscript|init[?!]?)/,/\s*(?=[<(])/],className:{1:"keyword"}, -contains:[L,B,n],illegal:/\[|%/},F={match:[/operator/,/\s+/,Be],className:{ -1:"keyword",3:"title"}},U={begin:[/precedencegroup/,/\s+/,Ue],className:{ -1:"keyword",3:"title"},contains:[R],keywords:[...Te,...Ce],end:/}/} -;for(const e of O.variants){const n=e.contains.find((e=>"interpol"===e.label)) -;n.keywords=l;const t=[...c,...g,...p,f,O,...C];n.contains=[...t,{begin:/\(/, -end:/\)/,contains:["self",...t]}]}return{name:"Swift",keywords:l, -contains:[...a,$,z,{beginKeywords:"struct protocol class extension enum actor", -end:"\\{",excludeEnd:!0,keywords:l,contains:[e.inherit(e.TITLE_MODE,{ -className:"title.class",begin:/[A-Za-z$_][\u00C0-\u02B80-9A-Za-z$_]*/}),...c] -},F,U,{beginKeywords:"import",end:/$/,contains:[...a],relevance:0 -},S,...c,...g,...p,f,O,...C,...T,R,I]}},grmr_typescript:e=>{ -const n=Oe(e),t=_e,a=["any","void","number","boolean","string","object","never","symbol","bigint","unknown"],i={ -beginKeywords:"namespace",end:/\{/,excludeEnd:!0, -contains:[n.exports.CLASS_REFERENCE]},r={beginKeywords:"interface",end:/\{/, -excludeEnd:!0,keywords:{keyword:"interface extends",built_in:a}, -contains:[n.exports.CLASS_REFERENCE]},s={$pattern:_e, -keyword:he.concat(["type","namespace","interface","public","private","protected","implements","declare","abstract","readonly","enum","override"]), -literal:fe,built_in:ve.concat(a),"variable.language":we},o={className:"meta", -begin:"@"+t},l=(e,n,t)=>{const a=e.contains.findIndex((e=>e.label===n)) -;if(-1===a)throw Error("can not find mode to replace");e.contains.splice(a,1,t)} -;return Object.assign(n.keywords,s), -n.exports.PARAMS_CONTAINS.push(o),n.contains=n.contains.concat([o,i,r]), -l(n,"shebang",e.SHEBANG()),l(n,"use_strict",{className:"meta",relevance:10, -begin:/^\s*['"]use strict['"]/ -}),n.contains.find((e=>"func.def"===e.label)).relevance=0,Object.assign(n,{ -name:"TypeScript",aliases:["ts","tsx","mts","cts"]}),n},grmr_vbnet:e=>{ -const n=e.regex,t=/\d{1,2}\/\d{1,2}\/\d{4}/,a=/\d{4}-\d{1,2}-\d{1,2}/,i=/(\d|1[012])(:\d+){0,2} *(AM|PM)/,r=/\d{1,2}(:\d{1,2}){1,2}/,s={ -className:"literal",variants:[{begin:n.concat(/# */,n.either(a,t),/ *#/)},{ -begin:n.concat(/# */,r,/ *#/)},{begin:n.concat(/# */,i,/ *#/)},{ -begin:n.concat(/# */,n.either(a,t),/ +/,n.either(i,r),/ *#/)}] -},o=e.COMMENT(/'''/,/$/,{contains:[{className:"doctag",begin:/<\/?/,end:/>/}] -}),l=e.COMMENT(null,/$/,{variants:[{begin:/'/},{begin:/([\t ]|^)REM(?=\s)/}]}) -;return{name:"Visual Basic .NET",aliases:["vb"],case_insensitive:!0, -classNameAliases:{label:"symbol"},keywords:{ -keyword:"addhandler alias aggregate ansi as async assembly auto binary by byref byval call case catch class compare const continue custom declare default delegate dim distinct do each equals else elseif end enum erase error event exit explicit finally for friend from function get global goto group handles if implements imports in inherits interface into iterator join key let lib loop me mid module mustinherit mustoverride mybase myclass namespace narrowing new next notinheritable notoverridable of off on operator option optional order overloads overridable overrides paramarray partial preserve private property protected public raiseevent readonly redim removehandler resume return select set shadows shared skip static step stop structure strict sub synclock take text then throw to try unicode until using when where while widening with withevents writeonly yield", -built_in:"addressof and andalso await directcast gettype getxmlnamespace is isfalse isnot istrue like mod nameof new not or orelse trycast typeof xor cbool cbyte cchar cdate cdbl cdec cint clng cobj csbyte cshort csng cstr cuint culng cushort", -type:"boolean byte char date decimal double integer long object sbyte short single string uinteger ulong ushort", -literal:"true false nothing"}, -illegal:"//|\\{|\\}|endif|gosub|variant|wend|^\\$ ",contains:[{ -className:"string",begin:/"(""|[^/n])"C\b/},{className:"string",begin:/"/, -end:/"/,illegal:/\n/,contains:[{begin:/""/}]},s,{className:"number",relevance:0, -variants:[{begin:/\b\d[\d_]*((\.[\d_]+(E[+-]?[\d_]+)?)|(E[+-]?[\d_]+))[RFD@!#]?/ -},{begin:/\b\d[\d_]*((U?[SIL])|[%&])?/},{begin:/&H[\dA-F_]+((U?[SIL])|[%&])?/},{ -begin:/&O[0-7_]+((U?[SIL])|[%&])?/},{begin:/&B[01_]+((U?[SIL])|[%&])?/}]},{ -className:"label",begin:/^\w+:/},o,l,{className:"meta", -begin:/[\t ]*#(const|disable|else|elseif|enable|end|externalsource|if|region)\b/, -end:/$/,keywords:{ -keyword:"const disable else elseif enable end externalsource if region then"}, -contains:[l]}]}},grmr_wasm:e=>{e.regex;const n=e.COMMENT(/\(;/,/;\)/) -;return n.contains.push("self"),{name:"WebAssembly",keywords:{$pattern:/[\w.]+/, -keyword:["anyfunc","block","br","br_if","br_table","call","call_indirect","data","drop","elem","else","end","export","func","global.get","global.set","local.get","local.set","local.tee","get_global","get_local","global","if","import","local","loop","memory","memory.grow","memory.size","module","mut","nop","offset","param","result","return","select","set_global","set_local","start","table","tee_local","then","type","unreachable"] -},contains:[e.COMMENT(/;;/,/$/),n,{match:[/(?:offset|align)/,/\s*/,/=/], -className:{1:"keyword",3:"operator"}},{className:"variable",begin:/\$[\w_]+/},{ -match:/(\((?!;)|\))+/,className:"punctuation",relevance:0},{ -begin:[/(?:func|call|call_indirect)/,/\s+/,/\$[^\s)]+/],className:{1:"keyword", -3:"title.function"}},e.QUOTE_STRING_MODE,{match:/(i32|i64|f32|f64)(?!\.)/, -className:"type"},{className:"keyword", -match:/\b(f32|f64|i32|i64)(?:\.(?:abs|add|and|ceil|clz|const|convert_[su]\/i(?:32|64)|copysign|ctz|demote\/f64|div(?:_[su])?|eqz?|extend_[su]\/i32|floor|ge(?:_[su])?|gt(?:_[su])?|le(?:_[su])?|load(?:(?:8|16|32)_[su])?|lt(?:_[su])?|max|min|mul|nearest|neg?|or|popcnt|promote\/f32|reinterpret\/[fi](?:32|64)|rem_[su]|rot[lr]|shl|shr_[su]|store(?:8|16|32)?|sqrt|sub|trunc(?:_[su]\/f(?:32|64))?|wrap\/i64|xor))\b/ -},{className:"number",relevance:0, -match:/[+-]?\b(?:\d(?:_?\d)*(?:\.\d(?:_?\d)*)?(?:[eE][+-]?\d(?:_?\d)*)?|0x[\da-fA-F](?:_?[\da-fA-F])*(?:\.[\da-fA-F](?:_?[\da-fA-D])*)?(?:[pP][+-]?\d(?:_?\d)*)?)\b|\binf\b|\bnan(?::0x[\da-fA-F](?:_?[\da-fA-D])*)?\b/ -}]}},grmr_xml:e=>{ -const n=e.regex,t=n.concat(/[\p{L}_]/u,n.optional(/[\p{L}0-9_.-]*:/u),/[\p{L}0-9_.-]*/u),a={ -className:"symbol",begin:/&[a-z]+;|&#[0-9]+;|&#x[a-f0-9]+;/},i={begin:/\s/, -contains:[{className:"keyword",begin:/#?[a-z_][a-z1-9_-]+/,illegal:/\n/}] -},r=e.inherit(i,{begin:/\(/,end:/\)/}),s=e.inherit(e.APOS_STRING_MODE,{ -className:"string"}),o=e.inherit(e.QUOTE_STRING_MODE,{className:"string"}),l={ -endsWithParent:!0,illegal:/`]+/}]}]}]};return{ -name:"HTML, XML", -aliases:["html","xhtml","rss","atom","xjb","xsd","xsl","plist","wsf","svg"], -case_insensitive:!0,unicodeRegex:!0,contains:[{className:"meta",begin://,relevance:10,contains:[i,o,s,r,{begin:/\[/,end:/\]/,contains:[{ -className:"meta",begin://,contains:[i,r,o,s]}]}] -},e.COMMENT(//,{relevance:10}),{begin://, -relevance:10},a,{className:"meta",end:/\?>/,variants:[{begin:/<\?xml/, -relevance:10,contains:[o]},{begin:/<\?[a-z][a-z0-9]+/}]},{className:"tag", -begin:/)/,end:/>/,keywords:{name:"style"},contains:[l],starts:{ -end:/<\/style>/,returnEnd:!0,subLanguage:["css","xml"]}},{className:"tag", -begin:/)/,end:/>/,keywords:{name:"script"},contains:[l],starts:{ -end:/<\/script>/,returnEnd:!0,subLanguage:["javascript","handlebars","xml"]}},{ -className:"tag",begin:/<>|<\/>/},{className:"tag", -begin:n.concat(//,/>/,/\s/)))), -end:/\/?>/,contains:[{className:"name",begin:t,relevance:0,starts:l}]},{ -className:"tag",begin:n.concat(/<\//,n.lookahead(n.concat(t,/>/))),contains:[{ -className:"name",begin:t,relevance:0},{begin:/>/,relevance:0,endsParent:!0}]}]} -},grmr_yaml:e=>{ -const n="true false yes no null",t="[\\w#;/?:@&=+$,.~*'()[\\]]+",a={ -className:"string",relevance:0,variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/ -},{begin:/\S+/}],contains:[e.BACKSLASH_ESCAPE,{className:"template-variable", -variants:[{begin:/\{\{/,end:/\}\}/},{begin:/%\{/,end:/\}/}]}]},i=e.inherit(a,{ -variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/},{begin:/[^\s,{}[\]]+/}]}),r={ -end:",",endsWithParent:!0,excludeEnd:!0,keywords:n,relevance:0},s={begin:/\{/, -end:/\}/,contains:[r],illegal:"\\n",relevance:0},o={begin:"\\[",end:"\\]", -contains:[r],illegal:"\\n",relevance:0},l=[{className:"attr",variants:[{ -begin:"\\w[\\w :\\/.-]*:(?=[ \t]|$)"},{begin:'"\\w[\\w :\\/.-]*":(?=[ \t]|$)'},{ -begin:"'\\w[\\w :\\/.-]*':(?=[ \t]|$)"}]},{className:"meta",begin:"^---\\s*$", -relevance:10},{className:"string", -begin:"[\\|>]([1-9]?[+-])?[ ]*\\n( +)[^ ][^\\n]*\\n(\\2[^\\n]+\\n?)*"},{ -begin:"<%[%=-]?",end:"[%-]?%>",subLanguage:"ruby",excludeBegin:!0,excludeEnd:!0, -relevance:0},{className:"type",begin:"!\\w+!"+t},{className:"type", -begin:"!<"+t+">"},{className:"type",begin:"!"+t},{className:"type",begin:"!!"+t -},{className:"meta",begin:"&"+e.UNDERSCORE_IDENT_RE+"$"},{className:"meta", -begin:"\\*"+e.UNDERSCORE_IDENT_RE+"$"},{className:"bullet",begin:"-(?=[ ]|$)", -relevance:0},e.HASH_COMMENT_MODE,{beginKeywords:n,keywords:{literal:n}},{ -className:"number", -begin:"\\b[0-9]{4}(-[0-9][0-9]){0,2}([Tt \\t][0-9][0-9]?(:[0-9][0-9]){2})?(\\.[0-9]*)?([ \\t])*(Z|[-+][0-9][0-9]?(:[0-9][0-9])?)?\\b" -},{className:"number",begin:e.C_NUMBER_RE+"\\b",relevance:0},s,o,a],c=[...l] -;return c.pop(),c.push(i),r.contains=c,{name:"YAML",case_insensitive:!0, -aliases:["yml"],contains:l}}});const He=ae;for(const e of Object.keys(Ke)){ -const n=e.replace("grmr_","").replace("_","-");He.registerLanguage(n,Ke[e])} -return He}() -;"object"==typeof exports&&"undefined"!=typeof module&&(module.exports=hljs); \ No newline at end of file diff --git a/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/styles/vs2015.min.css b/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/styles/vs2015.min.css deleted file mode 100644 index 7f6fe11c..00000000 --- a/tinygrad/examples/tinychat/assets/unpkg.com/@highlightjs/cdn-assets@11.9.0/styles/vs2015.min.css +++ /dev/null @@ -1 +0,0 @@ -pre code.hljs{display:block;overflow-x:auto;padding:1em}code.hljs{padding:3px 5px}.hljs{background:#1e1e1e;color:#dcdcdc}.hljs-keyword,.hljs-literal,.hljs-name,.hljs-symbol{color:#569cd6}.hljs-link{color:#569cd6;text-decoration:underline}.hljs-built_in,.hljs-type{color:#4ec9b0}.hljs-class,.hljs-number{color:#b8d7a3}.hljs-meta .hljs-string,.hljs-string{color:#d69d85}.hljs-regexp,.hljs-template-tag{color:#9a5334}.hljs-formula,.hljs-function,.hljs-params,.hljs-subst,.hljs-title{color:#dcdcdc}.hljs-comment,.hljs-quote{color:#57a64a;font-style:italic}.hljs-doctag{color:#608b4e}.hljs-meta,.hljs-meta .hljs-keyword,.hljs-tag{color:#9b9b9b}.hljs-template-variable,.hljs-variable{color:#bd63c5}.hljs-attr,.hljs-attribute{color:#9cdcfe}.hljs-section{color:gold}.hljs-emphasis{font-style:italic}.hljs-strong{font-weight:700}.hljs-bullet,.hljs-selector-attr,.hljs-selector-class,.hljs-selector-id,.hljs-selector-pseudo,.hljs-selector-tag{color:#d7ba7d}.hljs-addition{background-color:#144212;display:inline-block;width:100%}.hljs-deletion{background-color:#600;display:inline-block;width:100%} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js b/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js deleted file mode 100644 index dd119d59..00000000 --- a/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js +++ /dev/null @@ -1,2 +0,0 @@ -!function(e){"function"==typeof define&&define.amd?define(e):e()}((function(){"use strict";var e=new Map;function t(t){var o=e.get(t);o&&o.destroy()}function o(t){var o=e.get(t);o&&o.update()}var r=null;"undefined"==typeof window?((r=function(e){return e}).destroy=function(e){return e},r.update=function(e){return e}):((r=function(t,o){return t&&Array.prototype.forEach.call(t.length?t:[t],(function(t){return function(t){if(t&&t.nodeName&&"TEXTAREA"===t.nodeName&&!e.has(t)){var o,r=null,n=window.getComputedStyle(t),i=(o=t.value,function(){s({testForHeightReduction:""===o||!t.value.startsWith(o),restoreTextAlign:null}),o=t.value}),l=function(o){t.removeEventListener("autosize:destroy",l),t.removeEventListener("autosize:update",a),t.removeEventListener("input",i),window.removeEventListener("resize",a),Object.keys(o).forEach((function(e){return t.style[e]=o[e]})),e.delete(t)}.bind(t,{height:t.style.height,resize:t.style.resize,textAlign:t.style.textAlign,overflowY:t.style.overflowY,overflowX:t.style.overflowX,wordWrap:t.style.wordWrap});t.addEventListener("autosize:destroy",l),t.addEventListener("autosize:update",a),t.addEventListener("input",i),window.addEventListener("resize",a),t.style.overflowX="hidden",t.style.wordWrap="break-word",e.set(t,{destroy:l,update:a}),a()}function s(e){var o,i,l=e.restoreTextAlign,a=void 0===l?null:l,d=e.testForHeightReduction,u=void 0===d||d,c=n.overflowY;if(0!==t.scrollHeight&&("vertical"===n.resize?t.style.resize="none":"both"===n.resize&&(t.style.resize="horizontal"),u&&(o=function(e){for(var t=[];e&&e.parentNode&&e.parentNode instanceof Element;)e.parentNode.scrollTop&&t.push([e.parentNode,e.parentNode.scrollTop]),e=e.parentNode;return function(){return t.forEach((function(e){var t=e[0],o=e[1];t.style.scrollBehavior="auto",t.scrollTop=o,t.style.scrollBehavior=null}))}}(t),t.style.height=""),i="content-box"===n.boxSizing?t.scrollHeight-(parseFloat(n.paddingTop)+parseFloat(n.paddingBottom)):t.scrollHeight+parseFloat(n.borderTopWidth)+parseFloat(n.borderBottomWidth),"none"!==n.maxHeight&&i>parseFloat(n.maxHeight)?("hidden"===n.overflowY&&(t.style.overflow="scroll"),i=parseFloat(n.maxHeight)):"hidden"!==n.overflowY&&(t.style.overflow="hidden"),t.style.height=i+"px",a&&(t.style.textAlign=a),o&&o(),r!==i&&(t.dispatchEvent(new Event("autosize:resized",{bubbles:!0})),r=i),c!==n.overflow&&!a)){var f=n.textAlign;"hidden"===n.overflow&&(t.style.textAlign="start"===f?"end":"start"),s({restoreTextAlign:f,testForHeightReduction:!0})}}function a(){s({testForHeightReduction:!0,restoreTextAlign:null})}}(t)})),t}).destroy=function(e){return e&&Array.prototype.forEach.call(e.length?e:[e],t),e},r.update=function(e){return e&&Array.prototype.forEach.call(e.length?e:[e],o),e});var n=r;document.addEventListener("alpine:init",(()=>{var e;(e=window.Alpine).directive("autosize",((e,{modifiers:t},{cleanup:o})=>{n(e);const r=Array.from(e.attributes);let i=!1;for(let{nodeName:e}of r)if("wire:model"===e||e.startsWith("wire:model.")){i=!0;break}!e.hasAttribute("wire:ignore")&&i&&e.setAttribute("wire:ignore","");const l=()=>{n.update(e)};e.addEventListener("autosize",l),o((()=>{n.destroy(e),e.removeEventListener("autosize",l)}))})),e.magic("autosize",(e=>t=>{(t||e).dispatchEvent(new Event("autosize"))}))}))})); -//# sourceMappingURL=alpine-autosize.min.js.map diff --git a/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js.map b/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js.map deleted file mode 100644 index c1b0dd47..00000000 --- a/tinygrad/examples/tinychat/assets/unpkg.com/@marcreichel/alpine-autosize@1.3.x/dist/alpine-autosize.min.js.map +++ /dev/null @@ -1 +0,0 @@ -{"version":3,"file":"alpine-autosize.min.js","sources":["../node_modules/autosize/dist/autosize.esm.js","../builds/cdn.js","../src/index.js"],"sourcesContent":["var e=new Map;function t(t){var o=e.get(t);o&&o.destroy()}function o(t){var o=e.get(t);o&&o.update()}var r=null;\"undefined\"==typeof window?((r=function(e){return e}).destroy=function(e){return e},r.update=function(e){return e}):((r=function(t,o){return t&&Array.prototype.forEach.call(t.length?t:[t],function(t){return function(t){if(t&&t.nodeName&&\"TEXTAREA\"===t.nodeName&&!e.has(t)){var o,r=null,n=window.getComputedStyle(t),i=(o=t.value,function(){a({testForHeightReduction:\"\"===o||!t.value.startsWith(o),restoreTextAlign:null}),o=t.value}),l=function(o){t.removeEventListener(\"autosize:destroy\",l),t.removeEventListener(\"autosize:update\",s),t.removeEventListener(\"input\",i),window.removeEventListener(\"resize\",s),Object.keys(o).forEach(function(e){return t.style[e]=o[e]}),e.delete(t)}.bind(t,{height:t.style.height,resize:t.style.resize,textAlign:t.style.textAlign,overflowY:t.style.overflowY,overflowX:t.style.overflowX,wordWrap:t.style.wordWrap});t.addEventListener(\"autosize:destroy\",l),t.addEventListener(\"autosize:update\",s),t.addEventListener(\"input\",i),window.addEventListener(\"resize\",s),t.style.overflowX=\"hidden\",t.style.wordWrap=\"break-word\",e.set(t,{destroy:l,update:s}),s()}function a(e){var o,i,l=e.restoreTextAlign,s=void 0===l?null:l,d=e.testForHeightReduction,u=void 0===d||d,c=n.overflowY;if(0!==t.scrollHeight&&(\"vertical\"===n.resize?t.style.resize=\"none\":\"both\"===n.resize&&(t.style.resize=\"horizontal\"),u&&(o=function(e){for(var t=[];e&&e.parentNode&&e.parentNode instanceof Element;)e.parentNode.scrollTop&&t.push([e.parentNode,e.parentNode.scrollTop]),e=e.parentNode;return function(){return t.forEach(function(e){var t=e[0],o=e[1];t.style.scrollBehavior=\"auto\",t.scrollTop=o,t.style.scrollBehavior=null})}}(t),t.style.height=\"\"),i=\"content-box\"===n.boxSizing?t.scrollHeight-(parseFloat(n.paddingTop)+parseFloat(n.paddingBottom)):t.scrollHeight+parseFloat(n.borderTopWidth)+parseFloat(n.borderBottomWidth),\"none\"!==n.maxHeight&&i>parseFloat(n.maxHeight)?(\"hidden\"===n.overflowY&&(t.style.overflow=\"scroll\"),i=parseFloat(n.maxHeight)):\"hidden\"!==n.overflowY&&(t.style.overflow=\"hidden\"),t.style.height=i+\"px\",s&&(t.style.textAlign=s),o&&o(),r!==i&&(t.dispatchEvent(new Event(\"autosize:resized\",{bubbles:!0})),r=i),c!==n.overflow&&!s)){var v=n.textAlign;\"hidden\"===n.overflow&&(t.style.textAlign=\"start\"===v?\"end\":\"start\"),a({restoreTextAlign:v,testForHeightReduction:!0})}}function s(){a({testForHeightReduction:!0,restoreTextAlign:null})}}(t)}),t}).destroy=function(e){return e&&Array.prototype.forEach.call(e.length?e:[e],t),e},r.update=function(e){return e&&Array.prototype.forEach.call(e.length?e:[e],o),e});var n=r;export default n;\n","import autosize from '../src/index.js';\n\ndocument.addEventListener('alpine:init', () => {\n autosize(window.Alpine);\n});\n","import autosize from \"autosize\";\n\nfunction Autosize(Alpine) {\n Alpine.directive(\"autosize\", (el, {modifiers}, {cleanup}) => {\n autosize(el);\n const attributes = Array.from(el.attributes);\n\n let hasWireModel = false;\n\n for (let {nodeName} of attributes) {\n if (nodeName === \"wire:model\" || nodeName.startsWith(\"wire:model.\")) {\n hasWireModel = true;\n break;\n }\n }\n\n if (!el.hasAttribute(\"wire:ignore\") && hasWireModel) {\n el.setAttribute(\"wire:ignore\", \"\");\n }\n\n const update = () => {\n autosize.update(el);\n };\n\n el.addEventListener(\"autosize\", update);\n\n cleanup(() => {\n autosize.destroy(el);\n el.removeEventListener(\"autosize\", update);\n });\n });\n\n Alpine.magic(\"autosize\", (node) => (el) => {\n const element = el || node;\n element.dispatchEvent(new Event(\"autosize\"));\n });\n}\n\nexport default Autosize;\n"],"names":["e","Map","t","o","get","destroy","update","r","window","Array","prototype","forEach","call","length","nodeName","has","n","getComputedStyle","i","value","a","testForHeightReduction","startsWith","restoreTextAlign","l","removeEventListener","s","Object","keys","style","delete","bind","height","resize","textAlign","overflowY","overflowX","wordWrap","addEventListener","set","d","u","c","scrollHeight","parentNode","Element","scrollTop","push","scrollBehavior","boxSizing","parseFloat","paddingTop","paddingBottom","borderTopWidth","borderBottomWidth","maxHeight","overflow","dispatchEvent","Event","bubbles","v","document","Alpine","directive","el","modifiers","cleanup","autosize","attributes","from","hasWireModel","hasAttribute","setAttribute","magic","node"],"mappings":"2FAAA,IAAIA,EAAE,IAAIC,IAAI,SAASC,EAAEA,GAAG,IAAIC,EAAEH,EAAEI,IAAIF,GAAGC,GAAGA,EAAEE,SAAS,CAAC,SAASF,EAAED,GAAG,IAAIC,EAAEH,EAAEI,IAAIF,GAAGC,GAAGA,EAAEG,QAAQ,CAAC,IAAIC,EAAE,KAAK,oBAAoBC,SAASD,EAAE,SAASP,GAAG,OAAOA,CAAC,GAAGK,QAAQ,SAASL,GAAG,OAAOA,CAAC,EAAEO,EAAED,OAAO,SAASN,GAAG,OAAOA,CAAC,KAAKO,EAAE,SAASL,EAAEC,GAAG,OAAOD,GAAGO,MAAMC,UAAUC,QAAQC,KAAKV,EAAEW,OAAOX,EAAE,CAACA,IAAG,SAASA,GAAG,OAAO,SAASA,GAAG,GAAGA,GAAGA,EAAEY,UAAU,aAAaZ,EAAEY,WAAWd,EAAEe,IAAIb,GAAG,CAAC,IAAIC,EAAEI,EAAE,KAAKS,EAAER,OAAOS,iBAAiBf,GAAGgB,GAAGf,EAAED,EAAEiB,MAAM,WAAWC,EAAE,CAACC,uBAAuB,KAAKlB,IAAID,EAAEiB,MAAMG,WAAWnB,GAAGoB,iBAAiB,OAAOpB,EAAED,EAAEiB,KAAK,GAAGK,EAAE,SAASrB,GAAGD,EAAEuB,oBAAoB,mBAAmBD,GAAGtB,EAAEuB,oBAAoB,kBAAkBC,GAAGxB,EAAEuB,oBAAoB,QAAQP,GAAGV,OAAOiB,oBAAoB,SAASC,GAAGC,OAAOC,KAAKzB,GAAGQ,SAAQ,SAASX,GAAG,OAAOE,EAAE2B,MAAM7B,GAAGG,EAAEH,EAAE,IAAGA,EAAE8B,OAAO5B,EAAE,EAAE6B,KAAK7B,EAAE,CAAC8B,OAAO9B,EAAE2B,MAAMG,OAAOC,OAAO/B,EAAE2B,MAAMI,OAAOC,UAAUhC,EAAE2B,MAAMK,UAAUC,UAAUjC,EAAE2B,MAAMM,UAAUC,UAAUlC,EAAE2B,MAAMO,UAAUC,SAASnC,EAAE2B,MAAMQ,WAAWnC,EAAEoC,iBAAiB,mBAAmBd,GAAGtB,EAAEoC,iBAAiB,kBAAkBZ,GAAGxB,EAAEoC,iBAAiB,QAAQpB,GAAGV,OAAO8B,iBAAiB,SAASZ,GAAGxB,EAAE2B,MAAMO,UAAU,SAASlC,EAAE2B,MAAMQ,SAAS,aAAarC,EAAEuC,IAAIrC,EAAE,CAACG,QAAQmB,EAAElB,OAAOoB,IAAIA,GAAG,CAAC,SAASN,EAAEpB,GAAG,IAAIG,EAAEe,EAAEM,EAAExB,EAAEuB,iBAAiBG,OAAE,IAASF,EAAE,KAAKA,EAAEgB,EAAExC,EAAEqB,uBAAuBoB,OAAE,IAASD,GAAGA,EAAEE,EAAE1B,EAAEmB,UAAU,GAAG,IAAIjC,EAAEyC,eAAe,aAAa3B,EAAEiB,OAAO/B,EAAE2B,MAAMI,OAAO,OAAO,SAASjB,EAAEiB,SAAS/B,EAAE2B,MAAMI,OAAO,cAAcQ,IAAItC,EAAE,SAASH,GAAG,IAAI,IAAIE,EAAE,GAAGF,GAAGA,EAAE4C,YAAY5C,EAAE4C,sBAAsBC,SAAS7C,EAAE4C,WAAWE,WAAW5C,EAAE6C,KAAK,CAAC/C,EAAE4C,WAAW5C,EAAE4C,WAAWE,YAAY9C,EAAEA,EAAE4C,WAAW,OAAO,WAAW,OAAO1C,EAAES,SAAQ,SAASX,GAAG,IAAIE,EAAEF,EAAE,GAAGG,EAAEH,EAAE,GAAGE,EAAE2B,MAAMmB,eAAe,OAAO9C,EAAE4C,UAAU3C,EAAED,EAAE2B,MAAMmB,eAAe,IAAI,GAAE,CAAC,CAA3S,CAA6S9C,GAAGA,EAAE2B,MAAMG,OAAO,IAAId,EAAE,gBAAgBF,EAAEiC,UAAU/C,EAAEyC,cAAcO,WAAWlC,EAAEmC,YAAYD,WAAWlC,EAAEoC,gBAAgBlD,EAAEyC,aAAaO,WAAWlC,EAAEqC,gBAAgBH,WAAWlC,EAAEsC,mBAAmB,SAAStC,EAAEuC,WAAWrC,EAAEgC,WAAWlC,EAAEuC,YAAY,WAAWvC,EAAEmB,YAAYjC,EAAE2B,MAAM2B,SAAS,UAAUtC,EAAEgC,WAAWlC,EAAEuC,YAAY,WAAWvC,EAAEmB,YAAYjC,EAAE2B,MAAM2B,SAAS,UAAUtD,EAAE2B,MAAMG,OAAOd,EAAE,KAAKQ,IAAIxB,EAAE2B,MAAMK,UAAUR,GAAGvB,GAAGA,IAAII,IAAIW,IAAIhB,EAAEuD,cAAc,IAAIC,MAAM,mBAAmB,CAACC,SAAQ,KAAMpD,EAAEW,GAAGwB,IAAI1B,EAAEwC,WAAW9B,GAAG,CAAC,IAAIkC,EAAE5C,EAAEkB,UAAU,WAAWlB,EAAEwC,WAAWtD,EAAE2B,MAAMK,UAAU,UAAU0B,EAAE,MAAM,SAASxC,EAAE,CAACG,iBAAiBqC,EAAEvC,wBAAuB,GAAI,CAAC,CAAC,SAASK,IAAIN,EAAE,CAACC,wBAAuB,EAAGE,iBAAiB,MAAM,CAAC,CAAnmE,CAAqmErB,EAAE,IAAGA,CAAC,GAAGG,QAAQ,SAASL,GAAG,OAAOA,GAAGS,MAAMC,UAAUC,QAAQC,KAAKZ,EAAEa,OAAOb,EAAE,CAACA,GAAGE,GAAGF,CAAC,EAAEO,EAAED,OAAO,SAASN,GAAG,OAAOA,GAAGS,MAAMC,UAAUC,QAAQC,KAAKZ,EAAEa,OAAOb,EAAE,CAACA,GAAGG,GAAGH,CAAC,GAAG,IAAIgB,EAAET,ECErlFsD,SAASvB,iBAAiB,eAAe,KCAzC,IAAkBwB,KDCLtD,OAAOsD,QCATC,UAAU,YAAY,CAACC,GAAKC,cAAaC,cAC5CC,EAASH,GACT,MAAMI,EAAa3D,MAAM4D,KAAKL,EAAGI,YAEjC,IAAIE,GAAe,EAEnB,IAAK,IAAIxD,SAACA,KAAasD,EACnB,GAAiB,eAAbtD,GAA6BA,EAASQ,WAAW,eAAgB,CACjEgD,GAAe,EACf,KACJ,EAGCN,EAAGO,aAAa,gBAAkBD,GACnCN,EAAGQ,aAAa,cAAe,IAGnC,MAAMlE,EAASA,KACX6D,EAAS7D,OAAO0D,EAAG,EAGvBA,EAAG1B,iBAAiB,WAAYhC,GAEhC4D,GAAQ,KACJC,EAAS9D,QAAQ2D,GACjBA,EAAGvC,oBAAoB,WAAYnB,EAAO,GAC5C,IAGNwD,EAAOW,MAAM,YAAaC,GAAUV,KAChBA,GAAMU,GACdjB,cAAc,IAAIC,MAAM,YAAY,GD/BzB"} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/assets/unpkg.com/alpinejs@3.x.x/dist/cdn.min.js b/tinygrad/examples/tinychat/assets/unpkg.com/alpinejs@3.x.x/dist/cdn.min.js deleted file mode 100644 index a3be81c2..00000000 --- a/tinygrad/examples/tinychat/assets/unpkg.com/alpinejs@3.x.x/dist/cdn.min.js +++ /dev/null @@ -1,5 +0,0 @@ -(()=>{var nt=!1,it=!1,W=[],ot=-1;function Ut(e){Rn(e)}function Rn(e){W.includes(e)||W.push(e),Mn()}function Wt(e){let t=W.indexOf(e);t!==-1&&t>ot&&W.splice(t,1)}function Mn(){!it&&!nt&&(nt=!0,queueMicrotask(Nn))}function Nn(){nt=!1,it=!0;for(let e=0;ee.effect(t,{scheduler:r=>{st?Ut(r):r()}}),at=e.raw}function ct(e){N=e}function Yt(e){let t=()=>{};return[n=>{let i=N(n);return e._x_effects||(e._x_effects=new Set,e._x_runEffects=()=>{e._x_effects.forEach(o=>o())}),e._x_effects.add(i),t=()=>{i!==void 0&&(e._x_effects.delete(i),$(i))},i},()=>{t()}]}function ve(e,t){let r=!0,n,i=N(()=>{let o=e();JSON.stringify(o),r?n=o:queueMicrotask(()=>{t(o,n),n=o}),r=!1});return()=>$(i)}var Xt=[],Zt=[],Qt=[];function er(e){Qt.push(e)}function te(e,t){typeof t=="function"?(e._x_cleanups||(e._x_cleanups=[]),e._x_cleanups.push(t)):(t=e,Zt.push(t))}function Ae(e){Xt.push(e)}function Oe(e,t,r){e._x_attributeCleanups||(e._x_attributeCleanups={}),e._x_attributeCleanups[t]||(e._x_attributeCleanups[t]=[]),e._x_attributeCleanups[t].push(r)}function lt(e,t){e._x_attributeCleanups&&Object.entries(e._x_attributeCleanups).forEach(([r,n])=>{(t===void 0||t.includes(r))&&(n.forEach(i=>i()),delete e._x_attributeCleanups[r])})}function tr(e){for(e._x_effects?.forEach(Wt);e._x_cleanups?.length;)e._x_cleanups.pop()()}var ut=new MutationObserver(mt),ft=!1;function ue(){ut.observe(document,{subtree:!0,childList:!0,attributes:!0,attributeOldValue:!0}),ft=!0}function dt(){kn(),ut.disconnect(),ft=!1}var le=[];function kn(){let e=ut.takeRecords();le.push(()=>e.length>0&&mt(e));let t=le.length;queueMicrotask(()=>{if(le.length===t)for(;le.length>0;)le.shift()()})}function m(e){if(!ft)return e();dt();let t=e();return ue(),t}var pt=!1,Se=[];function rr(){pt=!0}function nr(){pt=!1,mt(Se),Se=[]}function mt(e){if(pt){Se=Se.concat(e);return}let t=[],r=new Set,n=new Map,i=new Map;for(let o=0;o{s.nodeType===1&&s._x_marker&&r.add(s)}),e[o].addedNodes.forEach(s=>{if(s.nodeType===1){if(r.has(s)){r.delete(s);return}s._x_marker||t.push(s)}})),e[o].type==="attributes")){let s=e[o].target,a=e[o].attributeName,c=e[o].oldValue,l=()=>{n.has(s)||n.set(s,[]),n.get(s).push({name:a,value:s.getAttribute(a)})},u=()=>{i.has(s)||i.set(s,[]),i.get(s).push(a)};s.hasAttribute(a)&&c===null?l():s.hasAttribute(a)?(u(),l()):u()}i.forEach((o,s)=>{lt(s,o)}),n.forEach((o,s)=>{Xt.forEach(a=>a(s,o))});for(let o of r)t.some(s=>s.contains(o))||Zt.forEach(s=>s(o));for(let o of t)o.isConnected&&Qt.forEach(s=>s(o));t=null,r=null,n=null,i=null}function Ce(e){return z(B(e))}function k(e,t,r){return e._x_dataStack=[t,...B(r||e)],()=>{e._x_dataStack=e._x_dataStack.filter(n=>n!==t)}}function B(e){return e._x_dataStack?e._x_dataStack:typeof ShadowRoot=="function"&&e instanceof ShadowRoot?B(e.host):e.parentNode?B(e.parentNode):[]}function z(e){return new Proxy({objects:e},Dn)}var Dn={ownKeys({objects:e}){return Array.from(new Set(e.flatMap(t=>Object.keys(t))))},has({objects:e},t){return t==Symbol.unscopables?!1:e.some(r=>Object.prototype.hasOwnProperty.call(r,t)||Reflect.has(r,t))},get({objects:e},t,r){return t=="toJSON"?Pn:Reflect.get(e.find(n=>Reflect.has(n,t))||{},t,r)},set({objects:e},t,r,n){let i=e.find(s=>Object.prototype.hasOwnProperty.call(s,t))||e[e.length-1],o=Object.getOwnPropertyDescriptor(i,t);return o?.set&&o?.get?o.set.call(n,r)||!0:Reflect.set(i,t,r)}};function Pn(){return Reflect.ownKeys(this).reduce((t,r)=>(t[r]=Reflect.get(this,r),t),{})}function Te(e){let t=n=>typeof n=="object"&&!Array.isArray(n)&&n!==null,r=(n,i="")=>{Object.entries(Object.getOwnPropertyDescriptors(n)).forEach(([o,{value:s,enumerable:a}])=>{if(a===!1||s===void 0||typeof s=="object"&&s!==null&&s.__v_skip)return;let c=i===""?o:`${i}.${o}`;typeof s=="object"&&s!==null&&s._x_interceptor?n[o]=s.initialize(e,c,o):t(s)&&s!==n&&!(s instanceof Element)&&r(s,c)})};return r(e)}function Re(e,t=()=>{}){let r={initialValue:void 0,_x_interceptor:!0,initialize(n,i,o){return e(this.initialValue,()=>In(n,i),s=>ht(n,i,s),i,o)}};return t(r),n=>{if(typeof n=="object"&&n!==null&&n._x_interceptor){let i=r.initialize.bind(r);r.initialize=(o,s,a)=>{let c=n.initialize(o,s,a);return r.initialValue=c,i(o,s,a)}}else r.initialValue=n;return r}}function In(e,t){return t.split(".").reduce((r,n)=>r[n],e)}function ht(e,t,r){if(typeof t=="string"&&(t=t.split(".")),t.length===1)e[t[0]]=r;else{if(t.length===0)throw error;return e[t[0]]||(e[t[0]]={}),ht(e[t[0]],t.slice(1),r)}}var ir={};function y(e,t){ir[e]=t}function fe(e,t){let r=Ln(t);return Object.entries(ir).forEach(([n,i])=>{Object.defineProperty(e,`$${n}`,{get(){return i(t,r)},enumerable:!1})}),e}function Ln(e){let[t,r]=_t(e),n={interceptor:Re,...t};return te(e,r),n}function or(e,t,r,...n){try{return r(...n)}catch(i){re(i,e,t)}}function re(e,t,r=void 0){e=Object.assign(e??{message:"No error message given."},{el:t,expression:r}),console.warn(`Alpine Expression Error: ${e.message} - -${r?'Expression: "'+r+`" - -`:""}`,t),setTimeout(()=>{throw e},0)}var Me=!0;function ke(e){let t=Me;Me=!1;let r=e();return Me=t,r}function R(e,t,r={}){let n;return x(e,t)(i=>n=i,r),n}function x(...e){return sr(...e)}var sr=xt;function ar(e){sr=e}function xt(e,t){let r={};fe(r,e);let n=[r,...B(e)],i=typeof t=="function"?$n(n,t):Fn(n,t,e);return or.bind(null,e,t,i)}function $n(e,t){return(r=()=>{},{scope:n={},params:i=[]}={})=>{let o=t.apply(z([n,...e]),i);Ne(r,o)}}var gt={};function jn(e,t){if(gt[e])return gt[e];let r=Object.getPrototypeOf(async function(){}).constructor,n=/^[\n\s]*if.*\(.*\)/.test(e.trim())||/^(let|const)\s/.test(e.trim())?`(async()=>{ ${e} })()`:e,o=(()=>{try{let s=new r(["__self","scope"],`with (scope) { __self.result = ${n} }; __self.finished = true; return __self.result;`);return Object.defineProperty(s,"name",{value:`[Alpine] ${e}`}),s}catch(s){return re(s,t,e),Promise.resolve()}})();return gt[e]=o,o}function Fn(e,t,r){let n=jn(t,r);return(i=()=>{},{scope:o={},params:s=[]}={})=>{n.result=void 0,n.finished=!1;let a=z([o,...e]);if(typeof n=="function"){let c=n(n,a).catch(l=>re(l,r,t));n.finished?(Ne(i,n.result,a,s,r),n.result=void 0):c.then(l=>{Ne(i,l,a,s,r)}).catch(l=>re(l,r,t)).finally(()=>n.result=void 0)}}}function Ne(e,t,r,n,i){if(Me&&typeof t=="function"){let o=t.apply(r,n);o instanceof Promise?o.then(s=>Ne(e,s,r,n)).catch(s=>re(s,i,t)):e(o)}else typeof t=="object"&&t instanceof Promise?t.then(o=>e(o)):e(t)}var wt="x-";function C(e=""){return wt+e}function cr(e){wt=e}var De={};function d(e,t){return De[e]=t,{before(r){if(!De[r]){console.warn(String.raw`Cannot find directive \`${r}\`. \`${e}\` will use the default order of execution`);return}let n=G.indexOf(r);G.splice(n>=0?n:G.indexOf("DEFAULT"),0,e)}}}function lr(e){return Object.keys(De).includes(e)}function pe(e,t,r){if(t=Array.from(t),e._x_virtualDirectives){let o=Object.entries(e._x_virtualDirectives).map(([a,c])=>({name:a,value:c})),s=Et(o);o=o.map(a=>s.find(c=>c.name===a.name)?{name:`x-bind:${a.name}`,value:`"${a.value}"`}:a),t=t.concat(o)}let n={};return t.map(dr((o,s)=>n[o]=s)).filter(mr).map(zn(n,r)).sort(Kn).map(o=>Bn(e,o))}function Et(e){return Array.from(e).map(dr()).filter(t=>!mr(t))}var yt=!1,de=new Map,ur=Symbol();function fr(e){yt=!0;let t=Symbol();ur=t,de.set(t,[]);let r=()=>{for(;de.get(t).length;)de.get(t).shift()();de.delete(t)},n=()=>{yt=!1,r()};e(r),n()}function _t(e){let t=[],r=a=>t.push(a),[n,i]=Yt(e);return t.push(i),[{Alpine:K,effect:n,cleanup:r,evaluateLater:x.bind(x,e),evaluate:R.bind(R,e)},()=>t.forEach(a=>a())]}function Bn(e,t){let r=()=>{},n=De[t.type]||r,[i,o]=_t(e);Oe(e,t.original,o);let s=()=>{e._x_ignore||e._x_ignoreSelf||(n.inline&&n.inline(e,t,i),n=n.bind(n,e,t,i),yt?de.get(ur).push(n):n())};return s.runCleanups=o,s}var Pe=(e,t)=>({name:r,value:n})=>(r.startsWith(e)&&(r=r.replace(e,t)),{name:r,value:n}),Ie=e=>e;function dr(e=()=>{}){return({name:t,value:r})=>{let{name:n,value:i}=pr.reduce((o,s)=>s(o),{name:t,value:r});return n!==t&&e(n,t),{name:n,value:i}}}var pr=[];function ne(e){pr.push(e)}function mr({name:e}){return hr().test(e)}var hr=()=>new RegExp(`^${wt}([^:^.]+)\\b`);function zn(e,t){return({name:r,value:n})=>{let i=r.match(hr()),o=r.match(/:([a-zA-Z0-9\-_:]+)/),s=r.match(/\.[^.\]]+(?=[^\]]*$)/g)||[],a=t||e[r]||r;return{type:i?i[1]:null,value:o?o[1]:null,modifiers:s.map(c=>c.replace(".","")),expression:n,original:a}}}var bt="DEFAULT",G=["ignore","ref","data","id","anchor","bind","init","for","model","modelable","transition","show","if",bt,"teleport"];function Kn(e,t){let r=G.indexOf(e.type)===-1?bt:e.type,n=G.indexOf(t.type)===-1?bt:t.type;return G.indexOf(r)-G.indexOf(n)}function J(e,t,r={}){e.dispatchEvent(new CustomEvent(t,{detail:r,bubbles:!0,composed:!0,cancelable:!0}))}function D(e,t){if(typeof ShadowRoot=="function"&&e instanceof ShadowRoot){Array.from(e.children).forEach(i=>D(i,t));return}let r=!1;if(t(e,()=>r=!0),r)return;let n=e.firstElementChild;for(;n;)D(n,t,!1),n=n.nextElementSibling}function E(e,...t){console.warn(`Alpine Warning: ${e}`,...t)}var _r=!1;function gr(){_r&&E("Alpine has already been initialized on this page. Calling Alpine.start() more than once can cause problems."),_r=!0,document.body||E("Unable to initialize. Trying to load Alpine before `` is available. Did you forget to add `defer` in Alpine's ` - - - - - - - - - - - - - - - - - - - - - -
-
-

tinychat

-
- -
- -
- -
-
-
-
-
-
- -

-

SEC TO FIRST TOKEN

- - -

-

TOKENS/SEC

- - -

-

TOKENS

- -
-
- - -
-
-
- - - diff --git a/tinygrad/examples/tinychat/index.js b/tinygrad/examples/tinychat/index.js deleted file mode 100644 index 9f35030e..00000000 --- a/tinygrad/examples/tinychat/index.js +++ /dev/null @@ -1,313 +0,0 @@ -document.addEventListener("alpine:init", () => { - Alpine.data("state", () => ({ - // current state - cstate: { - time: null, - messages: [], - }, - - // historical state - histories: JSON.parse(localStorage.getItem("histories")) || [], - - home: 0, - generating: false, - endpoint: `${window.location.origin}/v1`, - - // performance tracking - time_till_first: 0, - tokens_per_second: 0, - total_tokens: 0, - - removeHistory(cstate) { - const index = this.histories.findIndex((state) => { - return state.time === cstate.time; - }); - if (index !== -1) { - this.histories.splice(index, 1); - localStorage.setItem("histories", JSON.stringify(this.histories)); - } - }, - - async handleSend() { - const el = document.getElementById("input-form"); - const value = el.value.trim(); - if (!value) return; - - if (this.generating) return; - this.generating = true; - if (this.home === 0) this.home = 1; - - // ensure that going back in history will go back to home - window.history.pushState({}, "", "/"); - - // add message to list - this.cstate.messages.push({ role: "user", content: value }); - - // clear textarea - el.value = ""; - el.style.height = "auto"; - el.style.height = el.scrollHeight + "px"; - - // reset performance tracking - const prefill_start = Date.now(); - let start_time = 0; - let tokens = 0; - this.tokens_per_second = 0; - - // start receiving server sent events - let gottenFirstChunk = false; - for await ( - const chunk of this.openaiChatCompletion(this.cstate.messages) - ) { - if (!gottenFirstChunk) { - this.cstate.messages.push({ role: "assistant", content: "" }); - gottenFirstChunk = true; - } - - // add chunk to the last message - this.cstate.messages[this.cstate.messages.length - 1].content += chunk; - - // calculate performance tracking - tokens += 1; - this.total_tokens += 1; - if (start_time === 0) { - start_time = Date.now(); - this.time_till_first = start_time - prefill_start; - } else { - const diff = Date.now() - start_time; - if (diff > 0) { - this.tokens_per_second = tokens / (diff / 1000); - } - } - } - - // update the state in histories or add it if it doesn't exist - const index = this.histories.findIndex((cstate) => { - return cstate.time === this.cstate.time; - }); - this.cstate.time = Date.now(); - if (index !== -1) { - // update the time - this.histories[index] = this.cstate; - } else { - this.histories.push(this.cstate); - } - // update in local storage - localStorage.setItem("histories", JSON.stringify(this.histories)); - - this.generating = false; - }, - - async handleEnter(event) { - // if shift is not pressed - if (!event.shiftKey) { - event.preventDefault(); - await this.handleSend(); - } - }, - - updateTotalTokens(messages) { - fetch(`${this.endpoint}/chat/token/encode`, { - method: "POST", - headers: { "Content-Type": "application/json" }, - body: JSON.stringify({ messages }), - }).then((response) => response.json()).then((data) => { - this.total_tokens = data.length; - }).catch(console.error); - }, - - async *openaiChatCompletion(messages) { - // stream response - const response = await fetch(`${this.endpoint}/chat/completions`, { - method: "POST", - headers: { - "Content-Type": "application/json", - }, - body: JSON.stringify({ - "messages": messages, - "stream": true, - }), - }); - if (!response.ok) { - throw new Error("Failed to fetch"); - } - - const reader = response.body.pipeThrough(new TextDecoderStream()) - .pipeThrough(new EventSourceParserStream()).getReader(); - while (true) { - const { done, value } = await reader.read(); - if (done) { - break; - } - if (value.type === "event") { - const json = JSON.parse(value.data); - if (json.choices) { - const choice = json.choices[0]; - if (choice.finish_reason === "stop") { - break; - } - yield choice.delta.content; - } - } - } - }, - })); -}); - -const { markedHighlight } = globalThis.markedHighlight; -marked.use(markedHighlight({ - langPrefix: "hljs language-", - highlight(code, lang, _info) { - const language = hljs.getLanguage(lang) ? lang : "plaintext"; - return hljs.highlight(code, { language }).value; - }, -})); - -// **** eventsource-parser **** -class EventSourceParserStream extends TransformStream { - constructor() { - let parser; - - super({ - start(controller) { - parser = createParser((event) => { - if (event.type === "event") { - controller.enqueue(event); - } - }); - }, - - transform(chunk) { - parser.feed(chunk); - }, - }); - } -} - -function createParser(onParse) { - let isFirstChunk; - let buffer; - let startingPosition; - let startingFieldLength; - let eventId; - let eventName; - let data; - reset(); - return { - feed, - reset, - }; - function reset() { - isFirstChunk = true; - buffer = ""; - startingPosition = 0; - startingFieldLength = -1; - eventId = void 0; - eventName = void 0; - data = ""; - } - function feed(chunk) { - buffer = buffer ? buffer + chunk : chunk; - if (isFirstChunk && hasBom(buffer)) { - buffer = buffer.slice(BOM.length); - } - isFirstChunk = false; - const length = buffer.length; - let position = 0; - let discardTrailingNewline = false; - while (position < length) { - if (discardTrailingNewline) { - if (buffer[position] === "\n") { - ++position; - } - discardTrailingNewline = false; - } - let lineLength = -1; - let fieldLength = startingFieldLength; - let character; - for ( - let index = startingPosition; - lineLength < 0 && index < length; - ++index - ) { - character = buffer[index]; - if (character === ":" && fieldLength < 0) { - fieldLength = index - position; - } else if (character === "\r") { - discardTrailingNewline = true; - lineLength = index - position; - } else if (character === "\n") { - lineLength = index - position; - } - } - if (lineLength < 0) { - startingPosition = length - position; - startingFieldLength = fieldLength; - break; - } else { - startingPosition = 0; - startingFieldLength = -1; - } - parseEventStreamLine(buffer, position, fieldLength, lineLength); - position += lineLength + 1; - } - if (position === length) { - buffer = ""; - } else if (position > 0) { - buffer = buffer.slice(position); - } - } - function parseEventStreamLine(lineBuffer, index, fieldLength, lineLength) { - if (lineLength === 0) { - if (data.length > 0) { - onParse({ - type: "event", - id: eventId, - event: eventName || void 0, - data: data.slice(0, -1), - // remove trailing newline - }); - - data = ""; - eventId = void 0; - } - eventName = void 0; - return; - } - const noValue = fieldLength < 0; - const field = lineBuffer.slice( - index, - index + (noValue ? lineLength : fieldLength), - ); - let step = 0; - if (noValue) { - step = lineLength; - } else if (lineBuffer[index + fieldLength + 1] === " ") { - step = fieldLength + 2; - } else { - step = fieldLength + 1; - } - const position = index + step; - const valueLength = lineLength - step; - const value = lineBuffer.slice(position, position + valueLength).toString(); - if (field === "data") { - data += value ? "".concat(value, "\n") : "\n"; - } else if (field === "event") { - eventName = value; - } else if (field === "id" && !value.includes("\0")) { - eventId = value; - } else if (field === "retry") { - const retry = parseInt(value, 10); - if (!Number.isNaN(retry)) { - onParse({ - type: "reconnect-interval", - value: retry, - }); - } - } - } -} -const BOM = [239, 187, 191]; -function hasBom(buffer) { - return BOM.every((charCode, index) => buffer.charCodeAt(index) === charCode); -} diff --git a/tinygrad/examples/tinychat/tinychat-browser/.gitignore b/tinygrad/examples/tinychat/tinychat-browser/.gitignore deleted file mode 100644 index eddee945..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -net_* -llama3-2.tiktoken -tiktoken.js -tiktoken_bg.wasm -transformer* \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/README.md b/tinygrad/examples/tinychat/tinychat-browser/README.md deleted file mode 100644 index 2051cdfb..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/README.md +++ /dev/null @@ -1,8 +0,0 @@ -# How to build and run tinychat in browser (WebGPU and WASM) -- `PYTHONPATH=. python examples/tinychat/tinychat-browser/compile.py` -- `./examples/tinychat/tinychat-browser/compile_wasm.sh` - - Prerequisite: [install emscripten](https://emscripten.org/docs/getting_started/downloads.html). This script looks for `~/emsdk/emsdk_env.sh`, adjust this based on your installation. -- `./examples/tinychat/tinychat-browser/make_tiktoken_js.sh` - - Prerequisite: install `npm`, `webpack`. -- `cd examples/tinychat && python -m http.server 7776` -- In browser: open either `localhost:7776/tinychat-browser` (WebGPU), or `localhost:7776/tinychat-browser/?backend=wasm` (WASM) \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/compile.py b/tinygrad/examples/tinychat/tinychat-browser/compile.py deleted file mode 100644 index d1a1e64c..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/compile.py +++ /dev/null @@ -1,148 +0,0 @@ -import os, json, hashlib, math -from extra.export_model import export_model -from examples.llama3 import build_transformer, Tokenizer -from tinygrad.nn.state import get_state_dict, load_state_dict -from tinygrad import Device, Variable, Tensor, dtypes, TinyJit -from tinygrad.helpers import fetch, Context -from tiktoken.load import load_tiktoken_bpe, dump_tiktoken_bpe - -def prepare_browser_chunks(model): - # split weights into browser-friendly chunks - state_dict = get_state_dict(model) - del state_dict['output.weight'], state_dict['output.scale'] # same as tok_embeddings; ensures consistency with model export - chunk_size = 16 * 1024 * 1024 # small chunks based on iphone browser constraints - metadata = {} - # We won't export cache_kv bytes (because we start inference on client at start_pos=0), but we will tell the client how big cache_kv needs to be - t_infos = [(v.uop.base.realized.nbytes, k, v.dtype) for k,v in state_dict.items() if "cache_kv" not in k] - empty_t_infos = [(v.uop.base.realized.nbytes, k, v.dtype) for k,v in state_dict.items() if "cache_kv" in k] - - split_t_infos = [] - for size, name, dtype in t_infos: - if size <= chunk_size: - split_t_infos.append((size, name, dtype, ())) - else: # split large weights into multiple parts - for i in range(0, size, chunk_size): - split_t_infos.append((min(chunk_size, size-i), f"{name}_part{math.ceil(i/chunk_size)}", dtype, (i, min(i+chunk_size, size)))) - - files = [] - # pack weights into files with FFD bin packing - split_t_infos = sorted(split_t_infos, reverse=True) - for info in split_t_infos: - placed = False - for file in files: - if sum(i[0] for i in file) + info[0] <= chunk_size: - if info[3] and any(i[3] for i in file): continue # no two split tensors can touch the same file, due to wasm loading constraints - file.append(info) - placed = True - break - if not placed: - files.append([info]) - - tinygrad_dtypes = {dtypes.float32: "float32", dtypes.float16: "float16", dtypes.int8: "int8", dtypes.int32: "int32"} - for i, file in enumerate(files): - cursor = 0 - with open(os.path.join(os.path.dirname(__file__), f'./net_part{i}.chunk'), "wb+") as writer: - for size, name, dtype, offsets in file: - name, part_num = (name, 0) if "_part" not in name else (name.split("_part")[0], int(name.split("_part")[1])) - default = {"parts": {}, "dtype": tinygrad_dtypes[dtype]} - weight_metadata = metadata.get(name, default) - weight_metadata["parts"][part_num] = {"file": i, "file_start_pos": cursor, "size": size} - metadata[name] = weight_metadata - data = bytes(state_dict[name].uop.base.realized.as_buffer()) - data = data if not offsets else data[offsets[0]:offsets[1]] - writer.write(data) - cursor += size - - metadata.update({name: {"parts": {0: {"empty": True, "size": size}}, "dtype": tinygrad_dtypes[dtype]} for size, name, dtype in empty_t_infos}) - - for k in metadata: - metadata[k]["parts"] = [part for part_num, part in sorted(metadata[k]["parts"].items(), key = lambda x: x[0])] - cursor = 0 - for i, part in enumerate(metadata[k]["parts"]): - metadata[k]["parts"][i]["target_start_pos"] = cursor - cursor += part["size"] - metadata[k]["size"] = cursor - - # compute hashes, which client app will check to determine whether to update with new weights and/or detect integrity issues - state_dict_hash = hashlib.sha256(json.dumps(metadata, sort_keys=True).encode("utf-8")).hexdigest() - metadata = {"state_dict": metadata, "state_dict_hash": state_dict_hash, "files": []} - hashes = set() - for i in range(len(files)): - with open(os.path.join(os.path.dirname(__file__), f'./net_part{i}.chunk'), "rb") as reader: - hash = hashlib.sha256(reader.read()).hexdigest() - hashes.add(hash) - metadata["files"].append({"name": f'net_part{i}.chunk', "hash": hash}) - if len(hashes) != len(files): print(f"WARNING: {len(files)} files were exported, but only {len(hashes)} are unique: something may have gone wrong") - metadata_hash = hashlib.sha256(json.dumps(metadata, sort_keys=True).encode("utf-8")).hexdigest() - metadata = {"metadata": metadata, "metadata_hash": metadata_hash} - - with open(os.path.join(os.path.dirname(__file__), f'./net_metadata.json'), "w") as writer: json.dump(metadata, writer, indent=4) - return metadata - -def validate_model(model, tokenizer): - prompt = "yo" - toks = [tokenizer.bos_id] - toks += [tokenizer.special_tokens["<|start_header_id|>"]] + tokenizer.encode("user") + [tokenizer.special_tokens["<|end_header_id|>"]] + tokenizer.encode("\n\n") - toks += tokenizer.encode(prompt) + [tokenizer.special_tokens["<|eot_id|>"]] - toks += [tokenizer.special_tokens["<|start_header_id|>"]] + tokenizer.encode("assistant") + [tokenizer.special_tokens["<|end_header_id|>"]] + tokenizer.encode("\n\n") - start_pos = 0 - run = TinyJit(model.forward) - for tok in toks[:-1]: - run(Tensor([[tok]]), Variable("start_pos", 0, model.max_context).bind(start_pos), 0.0, 0, 0.0, 0.0, 0.0).realize() - start_pos += 1 - tok = toks[-1] - result = "" - expected = "How's it going?" - while True: - tok = run(Tensor([[tok]]), Variable("start_pos", 0, model.max_context).bind(start_pos), 0.0, 0, 0.0, 0.0, 0.0).item() - start_pos += 1 - if tok in tokenizer.stop_tokens or len(result) > len(expected): break - result += tokenizer.decode([tok]) - assert result == expected, f"Model validation failed, expected output: {expected}, actual output: {result}" - -if __name__=="__main__": - # Export BPE data for use with tiktoken.js - tokenizer_path = fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir="llama3-1b-instruct") - mergeable_ranks = load_tiktoken_bpe(str(tokenizer_path)) - bpe_path = os.path.join(os.path.dirname(__file__), "llama3-2.tiktoken") - dump_tiktoken_bpe(mergeable_ranks, bpe_path) - tokenizer = Tokenizer(str(tokenizer_path)) - - model_path = fetch("https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-f16.gguf", "Llama-3.2-1B-Instruct-f16.gguf", subdir="llama3-1b-instruct") - max_context=1024 - tok = 128000 - TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P = 0.95, 0, 0.0, 0.0, 0.0 - start_pos = Variable("start_pos", 0, max_context).bind(0) - model_input = lambda: [Tensor([[tok]]), start_pos, TEMPERATURE, TOP_K, TOP_P, ALPHA_F, ALPHA_P] - - Device.DEFAULT="CPU" - model = build_transformer(model_path, model_size="1B", quantize="int8", scale_dtype=dtypes.float32, device=Device.DEFAULT, max_context=max_context) - state_dict = get_state_dict(model) - validate_model(model, tokenizer) - model_name = "transformer" - - with Context(BEAM=3): - cprog, js_wrapper = export_model(model, "wasm", *model_input(), model_name=model_name) - # ensure consistency with exported weights - js_wrapper = js_wrapper.replace("output.weight", "tok_embeddings.weight").replace("output.scale", "tok_embeddings.scale") - - with open(os.path.join(os.path.dirname(__file__), f"{model_name}.c"), "w") as f: f.write(cprog) - with open(os.path.join(os.path.dirname(__file__), "net_clang.js"), "w") as f: f.write(js_wrapper) - - Device.DEFAULT="WEBGPU" - # float16 is not yet supported for dawn/Vulkan/NVIDIA stack, see: https://issues.chromium.org/issues/42251215 - # therefore for now, we used CLANG to quantize the float16 llama to int8 with float32 scales, then load to WEBGPU - model = build_transformer(model_path, model_size="1B", quantize="int8", max_context=max_context, load_weights=False) - load_state_dict(model, state_dict) - # these were the same before load_state_dict - model.output.weight, model.output.scale = model.tok_embeddings.weight, model.tok_embeddings.scale - - validate_model(model, tokenizer) - metadata = prepare_browser_chunks(model) # export weights to disk - - with Context(BEAM=3): - prg, input_sizes, output_sizes, state = export_model(model, "webgpu", *model_input(), model_name=model_name, stream_weights=True) - # ensure consistency with exported weights - prg = prg.replace("output.weight", "tok_embeddings.weight").replace("output.scale", "tok_embeddings.scale") - - with open(os.path.join(os.path.dirname(__file__), "net.js"), "w") as f: f.write(prg) \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/compile_wasm.sh b/tinygrad/examples/tinychat/tinychat-browser/compile_wasm.sh deleted file mode 100755 index fda21b0c..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/compile_wasm.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env bash -cd "$(dirname "$0")" - -# prereq: install emscripten: https://emscripten.org/docs/getting_started/downloads.html -EMSCRIPTEN_PATH=~/emsdk/emsdk_env.sh -source $EMSCRIPTEN_PATH -step="transformer" -initial_memory=6553600 -max_memory=1500053504 -exported_functions='["_net", "_malloc", "_free", "_set_buf"]' - -emcc "${step}.c" \ - -O3 -msimd128 -ffast-math -flto \ - -o "${step}.js" \ - -s MODULARIZE=1 \ - -s EXPORT_ES6=1 \ - -s EXPORTED_FUNCTIONS="${exported_functions}" \ - -s ENVIRONMENT='worker' \ - -s FILESYSTEM=0 \ - -s EVAL_CTORS \ - -s ALLOW_MEMORY_GROWTH=1 \ - -s INITIAL_MEMORY="$initial_memory" \ - -s MAXIMUM_MEMORY="$max_memory" \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/index.css b/tinygrad/examples/tinychat/tinychat-browser/index.css deleted file mode 100644 index 9be66354..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/index.css +++ /dev/null @@ -1,322 +0,0 @@ -/* define colors */ -:root { - --primary-color: #fff; - --secondary-color: #2a2a2a; - --secondary-color-transparent: #ffffff66; - --primary-bg-color: #1a1a1a; - --foreground-color: #f0f0f0; -} - -main { - width: 100%; - height: 100%; - - display: flex; - flex-direction: column; - - place-items: center; -} - -.home { - width: 100%; - height: 90%; - - margin-bottom: 10rem; -} - -.title { - font-size: 3rem; - margin: 1rem 0; - margin-top: 3rem; -} - -.histories-container-container { - width: 100%; - max-height: 75%; - - position: relative; -} - -.histories-container { - overflow-y: auto; - overflow-x: hidden; - width: 100%; - height: 100%; - - display: flex; - flex-direction: column; - gap: 1rem; - align-items: center; - - margin: 0; - padding: 3rem 1rem; -} - -.histories-start { - height: 3rem; - width: 100%; - - z-index: 999; - top: 0; - position: absolute; - - background: linear-gradient( - 180deg, - var(--primary-bg-color) 0%, - transparent 100% - ); -} -.histories-end { - height: 3rem; - width: 100%; - - z-index: 999; - bottom: 0; - position: absolute; - - background: linear-gradient( - 0deg, - var(--primary-bg-color) 0%, - transparent 100% - ); -} - -.history { - padding: 1rem; - width: 100%; - max-width: 40rem; - - background-color: var(--secondary-color); - border-radius: 10px; - border-left: 2px solid var(--primary-color); - - cursor: pointer; - - transform: translateX(calc(1px * var(--tx, 0))); - opacity: var(--opacity, 1); -} -.history:hover { - background-color: var(--secondary-color); -} - -.history-delete-button { - position: absolute; - top: 0; - right: 0; - padding: 0.5rem; - margin: 0; - outline: none; - border: none; - background-color: var(--secondary-color); - color: var(--foreground-color); - border-radius: 0 0 0 10px; - cursor: pointer; - transition: 0.2s; -} -.history-delete-button:hover { - background-color: var(--secondary-color); - padding: 0.75rem; -} - -.messages { - overflow-y: auto; - height: 100%; - width: 100%; - max-width: 1200px; - - display: flex; - flex-direction: column; - gap: 1rem; - align-items: center; - padding-top: 1rem; - padding-bottom: 11rem; -} - -.message { - max-width: 75%; - padding: 0.5rem 1rem; - border-radius: 20px; -} -.message-role-assistant { - background-color: var(--secondary-color); - margin-right: auto; - color: #fff; -} -.message-role-user { - margin-left: auto; - background-color: var(--primary-color); - color: #000; -} - -.message > pre { - white-space: pre-wrap; -} - -.hljs { - width: 100%; - position: relative; - border-radius: 10px; - /* wrap code blocks */ - white-space: pre-wrap; -} -/* put clipboard button in the top right corner of the code block */ -.clipboard-button { - position: absolute; - top: 0; - right: 0; - padding: 0.5rem; - margin: 0; - outline: none; - border: none; - background-color: var(--secondary-color); - color: var(--foreground-color); - border-radius: 0 0 0 10px; - cursor: pointer; - transition: 0.2s; -} -.clipboard-button:hover { - background-color: var(--secondary-color); - padding: 0.75rem; -} - -.input-container { - position: absolute; - bottom: 0; - - /* linear gradient from background-color to transparent on the top */ - background: linear-gradient( - 0deg, - var(--primary-bg-color) 55%, - transparent 100% - ); - - width: 100%; - max-width: 1200px; - display: flex; - flex-direction: column; - justify-content: center; - align-items: center; - z-index: 999; -} - -.input-performance { - margin-top: 4rem; - - display: flex; - flex-direction: row; - gap: 1rem; -} - -.input-performance-point { - display: flex; - flex-direction: row; - place-items: center; - gap: 0.5rem; -} -.input-performance-point > p { - height: 1rem; - line-height: normal; -} - -.input { - width: 90%; - min-height: 3rem; - flex-shrink: 0; - - display: flex; - flex-direction: row; - justify-content: center; - gap: 0.5rem; - - align-items: flex-end; - margin-bottom: 2rem; -} - -.input-form { - width: 100%; - padding: 1rem; - min-height: 3rem; - max-height: 8rem; - - background-color: var(--secondary-color); - color: var(--foreground-color); - border-radius: 10px; - border: none; - resize: none; - outline: none; -} -.mobile .input-form { /* prevent auto-zoom on touching prompt box */ - font-size: 16px; -} - -.input-button { - height: 3rem; - width: 4rem; - - background-color: var(--primary-color); - color: var(--secondary-color); - border-radius: 10px; - padding: 0.5rem; - cursor: pointer; -} -.input-button:hover { - background-color: var(--secondary-color-transparent); -} -.input-button:disabled { - background-color: var(--secondary-color); - cursor: not-allowed; -} - -/* wrap text */ -p { - white-space: pre-wrap; -} - -/* fonts */ -.megrim-regular { - font-family: monospace; - font-weight: 400; - font-style: normal; -} - -.monospace { - font-family: monospace; -} - -.loading-bar { - display: flex; - flex-direction: row; - align-items: center; - gap: 0.5rem; - width: 100%; - min-height: 3rem; - margin-bottom: 2rem; -} - -.loading-text { - color: var(--foreground-color); - font-size: 1rem; - white-space: nowrap; -} - -#progress-percentage { - color: var(--foreground-color); - font-size: 1rem; - white-space: nowrap; -} - -.progress-bar { - flex-grow: 1; - height: 0.5rem; - background-color: var(--secondary-color); - border-radius: 5px; - overflow: hidden; - position: relative; -} - -.progress { - width: 0%; - height: 100%; - background-color: var(--primary-color); - transition: width 0.2s ease-in-out; -} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/index.html b/tinygrad/examples/tinychat/tinychat-browser/index.html deleted file mode 100644 index 8d43624c..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/index.html +++ /dev/null @@ -1,182 +0,0 @@ - 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- - - diff --git a/tinygrad/examples/tinychat/tinychat-browser/index.js b/tinygrad/examples/tinychat/tinychat-browser/index.js deleted file mode 100644 index 2d84dede..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/index.js +++ /dev/null @@ -1,927 +0,0 @@ -window.TINYCHAT_ROOT = "/tinychat-browser/"; -const queryParams = new URLSearchParams(window.location.search); -const normalizedParams = Object.fromEntries([...queryParams].map(([key, value]) => [key.toUpperCase(), value.toUpperCase()])); -window.BACKEND = (normalizedParams["BACKEND"] === "WASM") ? "WASM" : "WebGPU"; -const isMobileAgent = /Mobi|Android|iPhone|iPad|iPod/i.test(navigator.userAgent); -const hasTouchScreen = 'ontouchstart' in window || navigator.maxTouchPoints > 0; -window.isMobile = isMobileAgent || hasTouchScreen; -if (window.isMobile) document.documentElement.classList.add('mobile'); // prevent annoying auto-zoom when entering prompt on mobile -// MODEL_BASE_URL is where the weights are hosted, WEBGPU_EXPORT is the JS-wrapped WebGPU code exported from tinygrad -window.PC_MODEL_BASE_URL = "."; -window.PC_WEBGPU_EXPORT = './net.js' -window.PC_MAX_CONTEXT = 1024; -window.MOBILE_MODEL_BASE_URL = "."; -window.MOBILE_WEBGPU_EXPORT = './net.js' -window.MOBILE_MAX_CONTEXT = 1024; - -const tiktokenReady = (async () => { - const { init, get_encoding, Tiktoken, load } = await import('./tiktoken.js'); - window.Tiktoken = Tiktoken; - window.tiktokenInit = init; - window.tiktokenGetEncoding = get_encoding; - window.tiktokenLoad = load; -})(); - -async function getDevice() { - let adapter; - try { - adapter = await navigator.gpu.requestAdapter(); - if (!adapter) { - this.loadingMessage = "Loading WASM (WebGPU not enabled):"; - throw new Error("No WebGPU adapter found"); - } - } catch(error) { - this.loadingMessage = "Loading WASM (WebGPU not enabled):"; - throw error; - } - const requiredLimits = {}; - const maxBufferSize = 322122544; - requiredLimits.maxStorageBufferBindingSize = maxBufferSize; - requiredLimits.maxBufferSize = maxBufferSize; - requiredLimits.maxComputeInvocationsPerWorkgroup = 512; // may need to vary based on what the WEBGPU backend produces - - try { - return await adapter.requestDevice({ requiredLimits }); - } catch(error) { - this.loadingMessage = "Loading WASM (WebGPU error):"; - throw error; - } -}; - -// copied from examples/webgpu/stable_diffusion/index.html -function initDb() { - return new Promise((resolve, reject) => { - let db; - const request = indexedDB.open('tinydb', 1); - request.onerror = (event) => { - console.error('Database error:', event.target.error); - resolve(null); - }; - - request.onsuccess = (event) => { - db = event.target.result; - console.log("Db initialized."); - resolve(db); - }; - - request.onupgradeneeded = (event) => { - db = event.target.result; - if (!db.objectStoreNames.contains('tensors')) { - db.createObjectStore('tensors', { keyPath: 'id' }); - } - }; - }); -} - -// copied from examples/webgpu/stable_diffusion/index.html -function readTensorFromDb(db, id) { - return new Promise((resolve, reject) => { - if (db == null) { - resolve(null); - } - - const transaction = db.transaction(['tensors'], 'readonly'); - const store = transaction.objectStore('tensors'); - const request = store.get(id); - - transaction.onabort = (event) => { - console.log("Transaction error while reading tensor: " + event.target.error); - resolve(null); - }; - - request.onsuccess = (event) => { - const result = event.target.result; - if (result) { - resolve(result); - } else { - resolve(null); - } - }; - - request.onerror = (event) => { - console.error('Tensor retrieve failed: ', event.target.error); - resolve(null); - }; - }); -} - -function getAllKeysFromDb(db) { - return new Promise((resolve, reject) => { - if (db == null) {resolve([]);} - const transaction = db.transaction(['tensors'], 'readonly'); - const store = transaction.objectStore('tensors'); - const request = store.getAllKeys(); - transaction.onabort = (event) => { - console.log("Transaction error while reading IndexedDB keys: " + event.target.error); - resolve([]); - }; - request.onsuccess = function (event) {resolve(event.target.result);}; - request.onerror = (event) => { - console.error('Retrieval of IndexedDB keys failed: ', event.target.error); - resolve([]); - }; - }); -} - -// modified from examples/webgpu/stable_diffusion/index.html -function saveTensorToDb(db, id, tensor) { - return readTensorFromDb(db, id).then((result) => { - if (!result) { - new Promise((resolve, reject) => { - if (db == null) { - resolve(null); - } - - const transaction = db.transaction(['tensors'], 'readwrite'); - const store = transaction.objectStore('tensors'); - const request = store.put({ id: id, content: tensor }); - - transaction.onabort = (event) => { - console.log("Transaction error while saving tensor: " + event.target.error); - resolve(null); - }; - - request.onsuccess = () => { - console.log('Tensor saved successfully.'); - resolve(); - }; - - request.onerror = (event) => { - console.error('Tensor save failed:', event.target.error); - resolve(null); - }; - }); - } else { - return null; - } - }).catch(()=> null); -} - -function deleteTensorFromDb(db, id) { - return new Promise((resolve, reject) => { - if (db == null) { - console.error("Database is not initialized."); - resolve(null); - return; - } - - const transaction = db.transaction(['tensors'], 'readwrite'); - const store = transaction.objectStore('tensors'); - const request = store.delete(id); - - transaction.oncomplete = () => { - console.log(`Tensor with ID '${id}' deleted successfully.`); - resolve(); - }; - - transaction.onerror = (event) => { - console.error("Transaction error while deleting tensor:", event.target.error); - resolve(null); - }; - - request.onerror = (event) => { - console.error('Tensor deletion failed:', event.target.error); - resolve(null); - }; - - request.onsuccess = () => { - console.log(`Delete request for tensor with ID '${id}' succeeded.`); - }; - }); -} - -function makeProgress(total) { - let acc = 0; - const ret = function progress(amount, message) { - if (amount >= 0) { // allow updating message only - acc += amount; - const percentage = total ? Math.trunc((acc / total) * 100) : 0; - document.querySelector('.progress').style.width = `${percentage}%`; - document.getElementById('progress-percentage').textContent = `${percentage}%`; - } - if (message) { - this.loadingMessage = message; - document.getElementById('loading-message').textContent = this.loadingMessage; - } - }.bind(this); - ret.total = total; - return ret; -} - -function sendMessageToWorker(worker, message) { - return new Promise((resolve, reject) => { - const onMessage = (event) => { - resolve(event.data); - worker.removeEventListener('message', onMessage); - worker.removeEventListener('error', onError); - }; - - const onError = (error) => { - reject(error); - worker.removeEventListener('message', onMessage); - worker.removeEventListener('error', onError); - }; - - worker.addEventListener('message', onMessage); - worker.addEventListener('error', onError); - - if (message.header === "token") worker.postMessage(message.data); - else if (message.header === "load_state_dict") { - if (message.data === "done") worker.postMessage(message.data); - else worker.postMessage(message.data, message.data.map(file => file.bytes.buffer)); - } - else if (message.header === "init") worker.postMessage("init"); - }); -} - -async function load_state_dict (data, device, progress) { - let state_dict = data.metadata.state_dict; - let completed = 0; - - // modified from examples/webgpu/stable_diffusion/index.html getProgressDlForPart - const loadPart = async (part) => { - const response = await fetch(part); - const res = new Response(new ReadableStream({ - async start(controller) { - const reader = response.body.getReader(); - for (;;) { - const { done, value } = await reader.read(); - if (done) break; - progress(value.byteLength); - controller.enqueue(value); - } - controller.close(); - }, - })); - - return res.arrayBuffer(); - }; - - let db = await initDb(); - - const getPart = async(filename, hash) => { - let part = await readTensorFromDb(db, hash); - - if (part) { - console.log(`Cache hit: ${filename}, hash: ${hash}`); - progress(part.content.byteLength); - return Promise.resolve(part.content); - } else { - console.log(`Cache miss: ${filename}, hash: ${hash}`); - return loadPart(`${window.MODEL_BASE_URL}/${filename}`); - } - } - - const correctHashes = data.metadata.files.map(file => file.hash) - // delete unused cached buffers to free disk space -- if we update weights, user will otherwise have obsolete cached buffers - const dbKeys = await getAllKeysFromDb(db); - const correctHashesSet = new Set(correctHashes); - const notInCorrectHashes = dbKeys.filter(key => !correctHashesSet.has(key)); - // await these right before starting to save new stuff - const deletionPromises = notInCorrectHashes.map(async (hash) => deleteTensorFromDb(db, hash)); - - // instantiates empty weight buffers on WebGPU, attaches buffers to state_dict - let model; - if (window.BACKEND === "WebGPU") { - //model = await transformer().setup(device, state_dict, progress); - model = await transformer.setupNet(device, state_dict); - progress(0.15 * progress.total); - - } - else if (window.BACKEND === "WASM") { - progress(0.02 * progress.total); - model = new Worker(`./worker.js?version=${Date.now()}`); - await sendMessageToWorker(model, {header: "init"}); - progress(0.02 * progress.total); - progress(0.11 * progress.total); - } - - const downloaded = []; - const triggerChainDownload = async (toDownload) => { - const numDownloaders = window.isMobile ? 4 : toDownload.length; // TODO: dynamically base this on DL file size? current assumption is 16 MiB chunks - - const chainDownload = async() => { - const file = toDownload.shift(); - loadPart(`${window.MODEL_BASE_URL}/${file.name}`) // triggers download - .then(async (arraybuf) => { - downloaded.push({ ...file, bytes: new Uint8Array(arraybuf)}); - // pause downloads if further processing is a bottleneck - while (toDownload.length && downloaded.length >= numDownloaders) await new Promise(resolve => setTimeout(resolve, 5)); - if (toDownload.length && downloaded.length < numDownloaders) chainDownload(); // start next download - }) - } - for (let i=0; i { - if (window.BACKEND === "WebGPU") { - for (const part of file.parts) { - if (part.empty) continue; - part.bytes = (part.size === file.bytes.length) ? file.bytes : file.bytes.slice(part.file_start_pos, part.file_start_pos + part.size); - device.queue.writeBuffer(state_dict[part.key].bytes, part.target_start_pos, part.bytes); // improves stability over mappedAtCreation writing - part.bytes = null; - } - } - else if (window.BACKEND === "WASM") { - await sendMessageToWorker(model, {header: "load_state_dict", data: [file]}); - } - file.bytes = null; - } - - if (window.BACKEND === "WebGPU") { // contiguous loading not needed for WebGPU stability - const files = data.tensor_file_groups.flatMap(obj => obj.files); - data.tensor_file_groups = [{contiguous: false, files: files}]; - } - - for (const group of data.tensor_file_groups) { - const contiguous = group.contiguous; - const files = group.files; - const tensor_file_indices = files.map(file => file.index); - const contiguousFiles = []; - const fileHashes = new Set(files.map(file => file.hash)); - const cachedFileHashes = new Set(dbKeys.filter(key => fileHashes.has(key))); - const cachedFiles = files.filter(file => cachedFileHashes.has(file.hash)); - const toDownload = files.filter(file => !cachedFileHashes.has(file.hash)); - triggerChainDownload(toDownload); - - const loadDelay = 5; - await Promise.all(deletionPromises); - - while (completed < files.length) { - const start = performance.now(); - // prioritize files from downloaded queue, so we can continue downloading more files - if (downloaded.length) { - const file = downloaded.shift(); - await saveTensorToDb(db, file.hash, file.bytes); // for wasm, must await to prevent race between indexedDB and transfer to worker - if (!contiguous) await loadFileToStateDict(file); - else contiguousFiles.push(file); - completed += 1; - } - else if (!downloaded.length && cachedFiles.length) { - const file = cachedFiles.shift(); - file.bytes = await getPart(file.name, file.hash); // reads data from IndexedDB - if (!contiguous) await loadFileToStateDict(file); - else contiguousFiles.push(file); - completed += 1; - } - const end = performance.now(); - const elapsed = end - start; - if (elapsed < loadDelay) await new Promise(resolve => setTimeout(resolve, loadDelay - elapsed)); - } - if (contiguous) { - const orderMap = tensor_file_indices.reduce((acc, id, index) => {acc[id] = index; return acc;}, {}); - contiguousFiles.sort((a, b) => orderMap[a.index] - orderMap[b.index]); // glue files together in the right order - await sendMessageToWorker(model, {header: "load_state_dict", data: contiguousFiles}); - } - completed = 0; - } - - // initialize empty kv_caches, which were part of exported model's state_dict, but which we didn't want to package/download - if (window.BACKEND === "WASM") { - for (const [k, v] of Object.entries(state_dict).filter(([_, v]) => v.empty === true)) { - v.parts[0].file_start_pos = 0; - const file = { parts: v.parts, size: v.size, bytes: new Uint8Array(v.size).fill(0) }; - await loadFileToStateDict(file); - } - } - - return model; -}; - -document.addEventListener("alpine:init", () => { - Alpine.data("state", () => ({ - // loadingMessage updates the user on page load progress, including weights download and decompression - // if loadingMessage is not '', then prompt box will be hidden: this is default behavior on page load - placeholderText: "Generating...", - loadingMessage: `Loading ${window.BACKEND} model:`, - // model - nets: {}, - tokenizer: null, - max_context: 1024, - lastSeenToks: [], - - progress: null, - - async init() { - var device = null; - var webgpuErrorMessage = null; - if (window.BACKEND === "WebGPU") { - try { - device = await getDevice.call(this); - console.log("WebGPU device initialized"); - } catch (error) { - window.BACKEND = "WASM"; - console.log(`error: ${error}\nFailed to launch WebGPU. Loading WASM model instead...`); // return; - webgpuErrorMessage = this.loadingMessage; - } - } - - window.MODEL_BASE_URL = (window.BACKEND === "WebGPU" && !window.isMobile) ? window.PC_MODEL_BASE_URL : window.MOBILE_MODEL_BASE_URL; - this.max_context = (window.BACKEND === "WebGPU" && !window.isMobile) ? window.PC_MAX_CONTEXT : window.MOBILE_MAX_CONTEXT; - - const kernelsReady = (async () => { - if (window.BACKEND === "WASM") {var exports = await import(`./net_clang.js?version=${Date.now()}`);} - else if (window.BACKEND === "WebGPU" && !window.isMobile) {var exports = await import(`${PC_WEBGPU_EXPORT}?version=${Date.now()}`);} - else if (window.BACKEND === "WebGPU" && window.isMobile) {var exports = await import(`${MOBILE_WEBGPU_EXPORT}?version=${Date.now()}`);} - self.transformer = exports.default; - })(); - - const response = await fetch(`${window.MODEL_BASE_URL}/net_metadata.json`); - // TODO: cache metadata (and everything else, including tokenizer) - // TODO: use service worker to reload page when offline - const data = await response.json(); - data.metadata.files = data.metadata.files.map((file, index) => ({...file, index})); - const state_dict = data.metadata.state_dict; - - /* - - allocating memory to WASM on mobile has longstanding issues: https://github.com/WebAssembly/design/issues/1397 - - - the below pattern, while yielding a succesfully-functioning model when it doesn't crash, causes regular crashes on iOS Safari (iphone 15 iOS 18.3): - - call WASM malloc (to fit all tensors, or one per tensor) for all tensors up front, then load tensor byte chunks into the buffers in random order - - - the below pattern has been stable on iOS Safari (iphone 15 iOS 18.3): - - call only one WASM malloc at a time before filling the allocated bytes, as small as possible (malloc up to 256 MiB has been tested) - - fill the malloc'd memory in linear order from start to end (what has been tested is calling wasm.HEAPU8.set on 16 MiB chunks from start to end) - - use ALLOW_MEMORY_GROWTH=1 in wasm compilation, minimize initial memory - - - additional considerations affecting loading design, for WASM: - - it seems that copying bytes into wasm memory cannot be zero-copy without sharedarraybuffer, which isn't currently used due to increased hosting complexity - - non-zero copies create memory pressure, which is not reliably capped because of lack of control over garbage collection - - to minimize peak memory pressure if GC is delayed, we process (i.e. download + copy into WASM) large tensors (> 16 MiB) one at a time, in descending size order - */ - data.tensor_file_groups = []; // see above: for WASM, limit processing of multi-file Tensors to one at a time, in descending order based on Tensor size - const unsplit_tensors = []; - const sortedEntries = Object.entries(state_dict).sort(([, objA], [, objB]) => objB.size - objA.size); - - let totalSize = 0; - const seen = new Set(); - for (const [k,v] of sortedEntries) { - const files_in_tensor = []; - for (const part of v.parts) { - part.key = k; - if (part.empty) state_dict[k].empty = true; // assumes no other parts of this weight exist and are non-empty - else { - const file = data.metadata.files[part.file]; - if (!seen.has(file.index)) { - seen.add(file.index); - files_in_tensor.push(file); - } - totalSize += part.size; - part.dtype = v.dtype; - if (!data.metadata.files[part.file].parts) data.metadata.files[part.file].parts = []; - data.metadata.files[part.file].size ??= 0; - data.metadata.files[part.file].size += part.size; - data.metadata.files[part.file].parts.push(part); - } - } - if (files_in_tensor.length > 1) data.tensor_file_groups.push({contiguous: true, files: files_in_tensor}); // [tensorN_file0, tensorN_file1, ...] - else if (files_in_tensor.length > 0) unsplit_tensors.push(files_in_tensor[0]); - } - data.tensor_file_groups.push({contiguous: false, files: unsplit_tensors}); - - data.totalSize = totalSize; - totalSize = totalSize / 0.8; // give space in progress bar for initializing model bufs, and tokenizer - this.progress = makeProgress.call(this, totalSize); // creates closure with totalSize - - try { - this.progress(0.01 * totalSize, "Loading tokenizer:"); - const wasmResponse = await fetch(`${window.MODEL_BASE_URL}/tiktoken_bg.wasm`); - this.progress(0.01 * totalSize); - const wasmBytes = await wasmResponse.arrayBuffer(); - await tiktokenReady; - await window.tiktokenInit((imports) => WebAssembly.instantiate(wasmBytes, imports)); - this.progress(0.01 * totalSize); - - this.tokenizer = await createTokenizer(`${window.MODEL_BASE_URL}/llama3-2.tiktoken`); - const tokenizer_works = (new TextDecoder().decode(this.tokenizer.decode(this.tokenizer.encode("hello world"))) === "hello world"); - console.log("tokenizer works:", tokenizer_works) - this.progress(0.01 * totalSize); - } catch (error) {this.progress(-1, `Error launching tokenizer: ${error}`); console.log(error); return;} - - try { - const loadModelMessage = (webgpuErrorMessage) ? webgpuErrorMessage : `Loading ${window.BACKEND} model:` - this.progress(0, loadModelMessage); - await kernelsReady; - const model = await load_state_dict(data, device, this.progress); - - if (window.BACKEND === "WebGPU") { - this.nets = {"transformer": model}; - } - else if (window.BACKEND === "WASM") { - const msg = await sendMessageToWorker(model, {header: "load_state_dict", data: "done"}); - this.nets = {"transformer": async (tok, start_pos) => sendMessageToWorker(model, {header: "token", data: [tok, start_pos]})}; - } - this.progress(0.01 * totalSize, `Launching ${window.BACKEND} model:`); - this.loadingMessage = ""; // Triggers removal of loading bar, display of prompt box - } catch (error) {this.progress(-1, `Error launching model: ${error}`); console.log(error); return;} - }, - - // current state - cstate: { - time: null, - messages: [], - }, - - // historical state - histories: JSON.parse(localStorage.getItem("histories")) || [], - - home: 0, - generating: false, - maxContextReached: false, - cancelGeneration: false, - endpoint: `${window.location.origin}/v1`, - - // performance tracking - time_till_first: 0, - tokens_per_second: 0, - total_tokens: 0, - max_context: 0, - - removeHistory(cstate) { - const index = this.histories.findIndex((state) => { - return state.time === cstate.time; - }); - if (index !== -1) { - this.histories.splice(index, 1); - localStorage.setItem("histories", JSON.stringify(this.histories)); - } - }, - - async handleSend() { - const el = document.getElementById("input-form"); - const value = el.value.trim(); - if (!value) return; - - if (this.generating) return; - this.maxContextReached = false; - this.placeholderText = "Generating..."; - this.generating = true; - this.cancelGeneration = false; - if (this.home === 0) this.home = 1; - - // ensure that going back in history will go back to home - window.history.pushState({}, "", window.TINYCHAT_ROOT || "/"); - - // add message to list - this.cstate.messages.push({ role: "user", content: value }); - - // clear textarea - el.value = ""; - el.style.height = "auto"; - el.style.height = el.scrollHeight + "px"; - - // reset performance tracking - const prefill_start = Date.now(); - let start_time = 0; - let tokens = 0; - this.tokens_per_second = 0; - - let gottenFirstChunk = false; - try { - for await ( - const chunk of this.openaiChatCompletion(this.cstate.messages) - ) { - if (!gottenFirstChunk) { - this.cstate.messages.push({ role: "assistant", content: "" }); - gottenFirstChunk = true; - } - - // add chunk to the last message - // TODO: handle localStorage overflow - // possible example: this.cstate.messages[...] was undefined when trying to prompt within an old cstate (chat session) - this.cstate.messages[this.cstate.messages.length - 1].content += chunk; - - // calculate performance tracking - tokens += 1; - this.total_tokens += 1; - if (start_time === 0) { - start_time = Date.now(); - this.time_till_first = start_time - prefill_start; - } else { - const diff = Date.now() - start_time; - if (diff > 0) { - this.tokens_per_second = tokens / (diff / 1000); - } - } - this.checkMaxContext(this.total_tokens); - if (this.cancelGeneration) break; - } - } finally { - // update the state in histories or add it if it doesn't exist - const index = this.histories.findIndex((cstate) => { - return cstate.time === this.cstate.time; - }); - this.cstate.time = Date.now(); - if (index !== -1) { - // update the time - this.histories[index] = this.cstate; - } else { - this.histories.push(this.cstate); - } - // update in local storage - localStorage.setItem("histories", JSON.stringify(this.histories)); - - if (!this.maxContextReached) this.generating = false; - if (this.cancelGeneration && !this.maxContextReached) this.cstate = { time: null, messages: [] }; - } - }, - - async handleEnter(event) { - // if shift is not pressed - if (!event.shiftKey) { - event.preventDefault(); - await this.handleSend(); - } - }, - - updateTotalTokens(messages) { - try { - let toks = [this.tokenizer.bos_id]; - messages.forEach((message) => { - if (!message.role || !message.content) { - throw new Error("Each message must have a 'role' and 'content' property."); - } - toks = toks.concat(this.tokenizer.encodeMessage(message.role, message.content)); - - if (messages.length > 0 && messages[messages.length - 1].role === "user") { - toks = toks.concat(this.tokenizer.encodeRole("assistant")); - } - this.total_tokens = toks.length; - }); - } catch (error) { - console.error("Error updating total tokens:", error); - } - }, - - checkMaxContext(num_tokens) { - if (num_tokens >= this.max_context) { - this.cancelGeneration = true; - this.maxContextReached = true; - this.placeholderText = `Max context reached: ${this.max_context} tokens`; - } - }, - - async *openaiChatCompletion(messages) { - let tokens = [this.tokenizer.bos_id]; - for (const message of messages) { - tokens = tokens.concat(this.tokenizer.encodeMessage(message.role, message.content)); - } - tokens = tokens.concat(this.tokenizer.encodeRole("assistant")); - this.checkMaxContext(tokens.length); // don't waste time prefilling if we know we're over the token limit - let startPos = 0 - const prefillToks = tokens.slice(0, -1); - - // Skip the largest possible sequence of tokens already represented at the beginning of the model's kv caches - for (let i=0; i <= prefillToks.length; i++) { - startPos = i; - if (i == prefillToks.length) break; - if (i == this.lastSeenToks.length) break; - if (prefillToks[i] !== this.lastSeenToks[i]) break; - } - //this.lastSeenToks = prefillToks; - //prefillToks = prefillToks.slice(startPos); - const unprocessedPrefillToks = prefillToks.slice(startPos); - this.lastSeenToks = prefillToks.slice(0, startPos); - - this.progress = makeProgress(unprocessedPrefillToks.length); - this.loadingMessage = (window.BACKEND === "WebGPU") ? "Reading input:" : "Loading (enable WebGPU for speed):"; - this.progress(0, this.loadingMessage); - for (const tok of unprocessedPrefillToks) { - if (this.cancelGeneration) {this.loadingMessage=""; return;} - if (window.BACKEND === "WebGPU") {await this.nets["transformer"](new Int32Array([tok]), new Int32Array([startPos]));} - else {await this.nets["transformer"](tok, startPos);} - this.lastSeenToks.push(tok) - startPos += 1; - this.progress(1); - } - this.loadingMessage = ""; // hides progress bar - - let lastTok = tokens[tokens.length - 1]; - while (true) { - if (window.BACKEND === "WebGPU") {var tok = await this.nets["transformer"](new Int32Array([lastTok]), new Int32Array([startPos])); tok = tok[0][0];} - else {var tok = await this.nets["transformer"](lastTok, startPos);} - this.lastSeenToks.push(lastTok); // lets us skip prefilling with these tokens at the next prompt in this chain - startPos += 1; - lastTok = tok; - if (this.tokenizer.stop_tokens.has(lastTok)) break; - yield new TextDecoder().decode(this.tokenizer.decode([lastTok])); - } - }, - })); -}); - -const { markedHighlight } = globalThis.markedHighlight; -marked.use(markedHighlight({ - langPrefix: "hljs language-", - highlight(code, lang, _info) { - const language = hljs.getLanguage(lang) ? lang : "plaintext"; - return hljs.highlight(code, { language }).value; - }, -})); - -// **** eventsource-parser **** -class EventSourceParserStream extends TransformStream { - constructor() { - let parser; - - super({ - start(controller) { - parser = createParser((event) => { - if (event.type === "event") { - controller.enqueue(event); - } - }); - }, - - transform(chunk) { - parser.feed(chunk); - }, - }); - } -} - -function createParser(onParse) { - let isFirstChunk; - let buffer; - let startingPosition; - let startingFieldLength; - let eventId; - let eventName; - let data; - reset(); - return { - feed, - reset, - }; - function reset() { - isFirstChunk = true; - buffer = ""; - startingPosition = 0; - startingFieldLength = -1; - eventId = void 0; - eventName = void 0; - data = ""; - } - function feed(chunk) { - buffer = buffer ? buffer + chunk : chunk; - if (isFirstChunk && hasBom(buffer)) { - buffer = buffer.slice(BOM.length); - } - isFirstChunk = false; - const length = buffer.length; - let position = 0; - let discardTrailingNewline = false; - while (position < length) { - if (discardTrailingNewline) { - if (buffer[position] === "\n") { - ++position; - } - discardTrailingNewline = false; - } - let lineLength = -1; - let fieldLength = startingFieldLength; - let character; - for ( - let index = startingPosition; - lineLength < 0 && index < length; - ++index - ) { - character = buffer[index]; - if (character === ":" && fieldLength < 0) { - fieldLength = index - position; - } else if (character === "\r") { - discardTrailingNewline = true; - lineLength = index - position; - } else if (character === "\n") { - lineLength = index - position; - } - } - if (lineLength < 0) { - startingPosition = length - position; - startingFieldLength = fieldLength; - break; - } else { - startingPosition = 0; - startingFieldLength = -1; - } - parseEventStreamLine(buffer, position, fieldLength, lineLength); - position += lineLength + 1; - } - if (position === length) { - buffer = ""; - } else if (position > 0) { - buffer = buffer.slice(position); - } - } - function parseEventStreamLine(lineBuffer, index, fieldLength, lineLength) { - if (lineLength === 0) { - if (data.length > 0) { - onParse({ - type: "event", - id: eventId, - event: eventName || void 0, - data: data.slice(0, -1), - // remove trailing newline - }); - - data = ""; - eventId = void 0; - } - eventName = void 0; - return; - } - const noValue = fieldLength < 0; - const field = lineBuffer.slice( - index, - index + (noValue ? lineLength : fieldLength), - ); - let step = 0; - if (noValue) { - step = lineLength; - } else if (lineBuffer[index + fieldLength + 1] === " ") { - step = fieldLength + 2; - } else { - step = fieldLength + 1; - } - const position = index + step; - const valueLength = lineLength - step; - const value = lineBuffer.slice(position, position + valueLength).toString(); - if (field === "data") { - data += value ? "".concat(value, "\n") : "\n"; - } else if (field === "event") { - eventName = value; - } else if (field === "id" && !value.includes("\0")) { - eventId = value; - } else if (field === "retry") { - const retry = parseInt(value, 10); - if (!Number.isNaN(retry)) { - onParse({ - type: "reconnect-interval", - value: retry, - }); - } - } - } -} -const BOM = [239, 187, 191]; -function hasBom(buffer) { - return BOM.every((charCode, index) => buffer.charCodeAt(index) === charCode); -} - -const PAT_STR = "(?i:'s|'t|'re|'ve|'m|'ll|'d)|[^\r\n\\p{L}\\p{N}]?\\p{L}+|\\p{N}{1,3}| ?[^\\s\\p{L}\\p{N}]+[\\r\\n]*|\\s*[\\r\\n]+|\\s+(?!\\S)|\\s+"; - -async function createTokenizer(bpeUrl) { - const num_base_tokens = 128000; - const special_tokens = { - "<|begin_of_text|>": 128000, - "<|end_of_text|>": 128001, - "<|start_header_id|>": 128006, - "<|end_header_id|>": 128007, - "<|eot_id|>": 128009 - }; - const model = await window.tiktokenLoad({ - "load_tiktoken_bpe": bpeUrl, - "special_tokens": special_tokens, - "pat_str": PAT_STR - }); - const tokenizer = new window.Tiktoken(model.bpe_ranks, model.special_tokens, model.pat_str) - - return { - get bos_id() { - return special_tokens["<|begin_of_text|>"]; - }, - - get stop_tokens() { - return new Set([ - special_tokens["<|end_of_text|>"], - special_tokens["<|eot_id|>"], - ]); - }, - - decode(toks) { - const filtered = toks.filter((t) => t < num_base_tokens); - return tokenizer.decode(filtered); - }, - - encode(text, allow_special = false) { - const allowedSpecial = allow_special ? "all" : new Set(); - const disallowedSpecial = new Set(); - return tokenizer.encode(text, allowedSpecial, disallowedSpecial); - }, - - encodeRole(role) { - const tokens = []; - tokens.push(special_tokens["<|start_header_id|>"]); - tokens.push(...this.encode(role)); - tokens.push(special_tokens["<|end_header_id|>"]); - tokens.push(...this.encode("\n\n")); - return tokens; - }, - - encodeMessage(role, content) { - const roleTokens = this.encodeRole(role); - const contentTokens = this.encode(content.trim()); - return [...roleTokens, ...contentTokens, special_tokens["<|eot_id|>"]]; - }, - }; -} \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/make_tiktoken_js.sh b/tinygrad/examples/tinychat/tinychat-browser/make_tiktoken_js.sh deleted file mode 100755 index 765f8e23..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/make_tiktoken_js.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/usr/bin/env bash -cd "$(dirname "$0")" -npm init -y && \ -npm install --save-dev webpack webpack-cli && \ -npm install tiktoken && \ -jq '.scripts.build = "webpack"' package.json > package.tmp.json && \ -mv package.tmp.json package.json && \ -npm run build && \ -mv dist/*.wasm ./tiktoken_bg.wasm && \ -mv dist/* ./ && \ -rm -rf dist node_modules package-lock.json package.json \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/tiktoken-export.js b/tinygrad/examples/tinychat/tinychat-browser/tiktoken-export.js deleted file mode 100644 index 2f5320e6..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/tiktoken-export.js +++ /dev/null @@ -1,5 +0,0 @@ -// Force Webpack to copy the WASM -import 'tiktoken/tiktoken_bg.wasm'; -import { init, get_encoding, encoding_for_model, Tiktoken } from 'tiktoken/init'; -import { load } from 'tiktoken/load'; -export { init, get_encoding, encoding_for_model, Tiktoken, load }; \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/webpack.config.js b/tinygrad/examples/tinychat/tinychat-browser/webpack.config.js deleted file mode 100644 index 405536cb..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/webpack.config.js +++ /dev/null @@ -1,25 +0,0 @@ -const path = require("path"); - -module.exports = { - mode: "production", - entry: "./tiktoken-export.js", - output: { - filename: "tiktoken.js", - path: path.resolve(__dirname, "dist"), - library: { - type: "module" - } - }, - experiments: { - outputModule: true, - asyncWebAssembly: true - }, - module: { - rules: [ - { - test: /\.wasm$/, - type: "asset/resource", - } - ] - } -}; \ No newline at end of file diff --git a/tinygrad/examples/tinychat/tinychat-browser/worker.js b/tinygrad/examples/tinychat/tinychat-browser/worker.js deleted file mode 100644 index 9d42c28a..00000000 --- a/tinygrad/examples/tinychat/tinychat-browser/worker.js +++ /dev/null @@ -1,62 +0,0 @@ -const kernelsReady = (async () => { - // can't get browser to use updated versions except with cache-busting query string - const exports = await import(`./net_clang.js?version=${Date.now()}`); - Object.assign(self, exports); -})(); - -async function init(event) { - await kernelsReady; - self.model = await self.transformer(); - self.addEventListener("message", loadStateDict); - self.removeEventListener("message", init); - self.postMessage("success"); -} - -function loadStateDict(event) { - if (event.data === "done") { - self.addEventListener("message", inference); - self.removeEventListener("message", loadStateDict); - } - else { - if (event.data.length > 1) { - // the bytes from files are set contiguously in WASM memory - const malloc_size = event.data.reduce((sum, file) => sum + file.bytes.length, 0); - const malloc_ptr = self.model.wasm._malloc(malloc_size); - let cursor = 0; - for (const file of event.data) { - self.model.wasm.HEAPU8.set(file.bytes, malloc_ptr + cursor); - for (const part of file.parts) { - if (part.target_start_pos === 0) { - // tell WASM code where the tensor is in memory - self.model.wasm._set_buf(self.transformer_name_to_id[part.key], malloc_ptr + cursor); - } - cursor += part.size; - } - file.bytes = null; - } - } - else { - // the bytes from files are not guaranteed to be set contiguously in WASM memory - const file = event.data[0]; - const malloc_ptr = self.model.wasm._malloc(file.size); - self.model.wasm.HEAPU8.set(file.bytes, malloc_ptr); - for (const part of file.parts) { - if (part.target_start_pos === 0) { - self.model.wasm._set_buf(self.transformer_name_to_id[part.key], malloc_ptr + part.file_start_pos); - } - } - file.bytes = null; - } - } - self.postMessage("success"); -} - -function inference(event) { - const [tok, start_pos] = event.data; - const int32tok = new Int32Array([tok]); - const model_out = self.model.run(new Uint8Array(int32tok.buffer), start_pos); - const int32nextTok = new Int32Array(model_out[0].buffer); - self.postMessage(int32nextTok[0]); -} - -self.addEventListener("message", init); \ No newline at end of file diff --git a/tinygrad/examples/torch_cuda_kernel.py b/tinygrad/examples/torch_cuda_kernel.py deleted file mode 100644 index 5d1706ef..00000000 --- a/tinygrad/examples/torch_cuda_kernel.py +++ /dev/null @@ -1,38 +0,0 @@ -#!POPCORN leaderboard grayscale -#!POPCORN gpu A100 -# not a stable API, but works - -import torch, functools -from tinygrad import Tensor, TinyJit, Device -from tinygrad.engine.realize import CompiledRunner -from tinygrad.helpers import get_single_element, Context, OSX -from tinygrad.dtype import _from_torch_dtype - -@TinyJit -def f(tg_out, tg_data): return tg_out.assign(tg_data[:, :, 0] * 0.2989 + tg_data[:, :, 1] * 0.5870 + tg_data[:, :, 2] * 0.1140).realize() - -def custom_kernel(data: torch.Tensor, device="CUDA") -> torch.Tensor: - assert data.dtype == torch.float32 - tg_data = Tensor.from_blob(data.data_ptr(), data.shape, dtype=_from_torch_dtype(data.dtype), device=device) - - out = torch.empty((data.shape[0], data.shape[1]), dtype=data.dtype, device=data.device) - tg_out = Tensor.from_blob(out.data_ptr(), out.shape, dtype=_from_torch_dtype(out.dtype), device=device) - - # Need to sync torch to make sure the data is valid. - if data.device.type == "mps": torch.mps.synchronize() - else: torch.cuda.synchronize() - - with Context(BEAM=2): f(tg_out, tg_data) - - # Wait for computation to finish and the data is valid. - Device[device].synchronize() - - return out - -if __name__ == "__main__": - for i in range(3): - if OSX: - out = custom_kernel(inp:=torch.rand(16, 16, 3, device=torch.device("mps")), device="METAL") - else: - out = custom_kernel(inp:=torch.rand(16, 16, 3, device=torch.device("cuda")), device="CUDA") - assert torch.allclose(out, inp[:, :, 0] * 0.2989 + inp[:, :, 1] * 0.5870 + inp[:, :, 2] * 0.1140) diff --git a/tinygrad/examples/train_efficientnet.py b/tinygrad/examples/train_efficientnet.py deleted file mode 100644 index 521c9811..00000000 --- a/tinygrad/examples/train_efficientnet.py +++ /dev/null @@ -1,104 +0,0 @@ -import traceback -import time -from multiprocessing import Process, Queue -import numpy as np -from tinygrad.nn.state import get_parameters -from tinygrad.nn import optim -from tinygrad.helpers import getenv, trange -from tinygrad.tensor import Tensor -from extra.datasets import fetch_cifar -from extra.models.efficientnet import EfficientNet - -class TinyConvNet: - def __init__(self, classes=10): - conv = 3 - inter_chan, out_chan = 8, 16 # for speed - self.c1 = Tensor.uniform(inter_chan,3,conv,conv) - self.c2 = Tensor.uniform(out_chan,inter_chan,conv,conv) - self.l1 = Tensor.uniform(out_chan*6*6, classes) - - def forward(self, x): - x = x.conv2d(self.c1).relu().max_pool2d() - x = x.conv2d(self.c2).relu().max_pool2d() - x = x.reshape(shape=[x.shape[0], -1]) - return x.dot(self.l1) - -if __name__ == "__main__": - IMAGENET = getenv("IMAGENET") - classes = 1000 if IMAGENET else 10 - - TINY = getenv("TINY") - TRANSFER = getenv("TRANSFER") - if TINY: - model = TinyConvNet(classes) - elif TRANSFER: - model = EfficientNet(getenv("NUM", 0), classes, has_se=True) - model.load_from_pretrained() - else: - model = EfficientNet(getenv("NUM", 0), classes, has_se=False) - - parameters = get_parameters(model) - print("parameter count", len(parameters)) - optimizer = optim.Adam(parameters, lr=0.001) - - BS, steps = getenv("BS", 64 if TINY else 16), getenv("STEPS", 2048) - print(f"training with batch size {BS} for {steps} steps") - - if IMAGENET: - from extra.datasets.imagenet import fetch_batch - def loader(q): - while 1: - try: - q.put(fetch_batch(BS)) - except Exception: - traceback.print_exc() - q = Queue(16) - for i in range(2): - p = Process(target=loader, args=(q,)) - p.daemon = True - p.start() - else: - X_train, Y_train, _, _ = fetch_cifar() - X_train = X_train.reshape((-1, 3, 32, 32)) - Y_train = Y_train.reshape((-1,)) - - with Tensor.train(): - for i in (t := trange(steps)): - if IMAGENET: - X, Y = q.get(True) - else: - samp = np.random.randint(0, X_train.shape[0], size=(BS)) - X, Y = X_train.numpy()[samp], Y_train.numpy()[samp] - - st = time.time() - out = model.forward(Tensor(X.astype(np.float32), requires_grad=False)) - fp_time = (time.time()-st)*1000.0 - - y = np.zeros((BS,classes), np.float32) - y[range(y.shape[0]),Y] = -classes - y = Tensor(y, requires_grad=False) - loss = out.log_softmax().mul(y).mean() - - optimizer.zero_grad() - - st = time.time() - loss.backward() - bp_time = (time.time()-st)*1000.0 - - st = time.time() - optimizer.step() - opt_time = (time.time()-st)*1000.0 - - st = time.time() - loss = loss.numpy() - cat = out.argmax(axis=1).numpy() - accuracy = (cat == Y).mean() - finish_time = (time.time()-st)*1000.0 - - # printing - t.set_description("loss %.2f accuracy %.2f -- %.2f + %.2f + %.2f + %.2f = %.2f" % - (loss, accuracy, - fp_time, bp_time, opt_time, finish_time, - fp_time + bp_time + opt_time + finish_time)) - - del out, y, loss diff --git a/tinygrad/examples/train_resnet.py b/tinygrad/examples/train_resnet.py deleted file mode 100755 index 8feee808..00000000 --- a/tinygrad/examples/train_resnet.py +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env python3 -import numpy as np -from PIL import Image - -from tinygrad.nn.state import get_parameters -from tinygrad.nn import optim -from tinygrad.helpers import getenv -from extra.training import train, evaluate -from extra.models.resnet import ResNet -from extra.datasets import fetch_mnist - - -class ComposeTransforms: - def __init__(self, trans): - self.trans = trans - - def __call__(self, x): - for t in self.trans: - x = t(x) - return x - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = fetch_mnist() - X_train = X_train.reshape(-1, 28, 28).astype(np.uint8) - X_test = X_test.reshape(-1, 28, 28).astype(np.uint8) - classes = 10 - - TRANSFER = getenv('TRANSFER') - model = ResNet(getenv('NUM', 18), num_classes=classes) - if TRANSFER: - model.load_from_pretrained() - - lr = 5e-3 - transform = ComposeTransforms([ - lambda x: [Image.fromarray(xx, mode='L').resize((64, 64)) for xx in x], - lambda x: np.stack([np.asarray(xx) for xx in x], 0), - lambda x: x / 255.0, - lambda x: np.tile(np.expand_dims(x, 1), (1, 3, 1, 1)).astype(np.float32), - ]) - for _ in range(5): - optimizer = optim.SGD(get_parameters(model), lr=lr, momentum=0.9) - train(model, X_train, Y_train, optimizer, 100, BS=32, transform=transform) - evaluate(model, X_test, Y_test, num_classes=classes, transform=transform) - lr /= 1.2 - print(f'reducing lr to {lr:.7f}') diff --git a/tinygrad/examples/transformer.py b/tinygrad/examples/transformer.py deleted file mode 100755 index 40082db7..00000000 --- a/tinygrad/examples/transformer.py +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env python3 -import numpy as np -import random - -from tinygrad.nn.state import get_parameters -from tinygrad.nn.optim import Adam -from extra.training import train, evaluate -from extra.models.transformer import Transformer - -# dataset idea from https://github.com/karpathy/minGPT/blob/master/projects/adder/adder.py -def make_dataset(): - ds = [] - for i in range(100): - for j in range(100): - s = i+j - ds.append([i//10, i%10, j//10, j%10, s//100, (s//10)%10, s%10]) - random.shuffle(ds) - ds = np.array(ds).astype(np.float32) - ds_X = ds[:, 0:6] - ds_Y = np.copy(ds[:, 1:]).astype(np.int32) - ds_X_train, ds_X_test = ds_X[0:8000], ds_X[8000:] - ds_Y_train, ds_Y_test = ds_Y[0:8000], ds_Y[8000:] - return ds_X_train, ds_Y_train, ds_X_test, ds_Y_test - -if __name__ == "__main__": - model = Transformer(10, 6, 2, 128, 4, 32) - X_train, Y_train, X_test, Y_test = make_dataset() - lr = 0.003 - for i in range(10): - optim = Adam(get_parameters(model), lr=lr) - train(model, X_train, Y_train, optim, 50, BS=64, allow_jit=True) - acc, Y_test_preds = evaluate(model, X_test, Y_test, num_classes=10, return_predict=True) - lr /= 1.2 - print(f'reducing lr to {lr:.4f}') - if acc > 0.998: - wrong=0 - for k in range(len(Y_test_preds)): - if (Y_test_preds[k] != Y_test[k]).any(): - wrong+=1 - a,b,c,x = X_test[k,:2].astype(np.int32), X_test[k,2:4].astype(np.int32), Y_test[k,-3:].astype(np.int32), Y_test_preds[k,-3:].astype(np.int32) - print(f'{a[0]}{a[1]} + {b[0]}{b[1]} = {x[0]}{x[1]}{x[2]} (correct: {c[0]}{c[1]}{c[2]})') - print(f'Wrong predictions: {wrong}, acc = {acc:.4f}') diff --git a/tinygrad/examples/vgg7.py b/tinygrad/examples/vgg7.py deleted file mode 100644 index a4a5835e..00000000 --- a/tinygrad/examples/vgg7.py +++ /dev/null @@ -1,262 +0,0 @@ -import sys -import random -import json -import numpy -from pathlib import Path -from PIL import Image -from tinygrad.tensor import Tensor -from tinygrad.nn.optim import SGD -from tinygrad.nn.state import safe_save, safe_load, get_state_dict, load_state_dict -from examples.vgg7_helpers.waifu2x import image_load, image_save, Vgg7 - -# amount of context erased by model -CONTEXT = 7 - -def get_sample_count(samples_dir): - try: - samples_dir_count_file = open(samples_dir + "/sample_count.txt", "r") - v = samples_dir_count_file.readline() - samples_dir_count_file.close() - return int(v) - except: - return 0 - -def set_sample_count(samples_dir, sc): - with open(samples_dir + "/sample_count.txt", "w") as file: - file.write(str(sc) + "\n") - -if len(sys.argv) < 2: - print("python3 -m examples.vgg7 import MODELJSON MODEL") - print(" imports a waifu2x JSON vgg_7 model, i.e. waifu2x/models/vgg_7/art/scale2.0x_model.json") - print(" into a safetensors file") - print(" weight tensors are ordered in tinygrad/ncnn form, as so: (outC,inC,H,W)") - print(" *this format is used by most other commands in this program*") - print("python3 -m examples.vgg7 import_kinne MODEL_KINNE MODEL_SAFETENSORS") - print(" imports a model in 'KINNE' format (raw floats: used by older versions of this example) into safetensors") - print("python3 -m examples.vgg7 execute MODEL IMG_IN IMG_OUT") - print(" given an already-nearest-neighbour-scaled image, runs vgg7 on it") - print(" output image has 7 pixels removed on all edges") - print(" do not run on large images, will have *hilarious* RAM use") - print("python3 -m examples.vgg7 execute_full MODEL IMG_IN IMG_OUT") - print(" does the 'whole thing' (padding, tiling)") - print(" safe for large images, etc.") - print("python3 -m examples.vgg7 new MODEL") - print(" creates a new model (experimental)") - print("python3 -m examples.vgg7 train MODEL SAMPLES_DIR ROUNDS ROUNDS_SAVE") - print(" trains a model (experimental)") - print(" (how experimental? well, every time I tried it, it flooded w/ NaNs)") - print(" note: ROUNDS < 0 means 'forever'. ROUNDS_SAVE <= 0 is not a good idea.") - print(" expects roughly execute's input as SAMPLES_DIR/IDXa.png") - print(" expects roughly execute's output as SAMPLES_DIR/IDXb.png") - print(" (i.e. my_samples/0a.png is the first pre-nearest-scaled image,") - print(" my_samples/0b.png is the first original image)") - print(" in addition, SAMPLES_DIR/samples_count.txt indicates sample count") - print(" won't pad or tile, so keep image sizes sane") - print("python3 -m examples.vgg7 samplify IMG_A IMG_B SAMPLES_DIR SIZE") - print(" creates overlapping micropatches (SIZExSIZE w/ 7-pixel border) for training") - print(" maintains/creates samples_count.txt automatically") - print(" unlike training, IMG_A must be exactly half the size of IMG_B") - sys.exit(1) - -cmd = sys.argv[1] -vgg7 = Vgg7() - -def nansbane(p): - if numpy.isnan(numpy.min(p.numpy())): - raise Exception("A NaN in the model has been detected. This model will not be interacted with to prevent further damage.") - -def load_and_save(path, save): - if save: - for v in vgg7.get_parameters(): - nansbane(v) - st = get_state_dict(vgg7) - safe_save(st, path) - else: - st = safe_load(path) - load_state_dict(vgg7, st) - for v in vgg7.get_parameters(): - nansbane(v) - -if cmd == "import": - src = sys.argv[2] - model = sys.argv[3] - - vgg7.load_waifu2x_json(json.load(open(src, "rb"))) - - load_and_save(model, True) -elif cmd == "import_kinne": - # tinygrad wasn't doing safetensors when this example was written - # it's possible someone might have a model around using the resulting interim format - src = sys.argv[2] - model = sys.argv[3] - - index = 0 - for t in vgg7.get_parameters(): - fn = src + "/snoop_bin_" + str(index) + ".bin" - t.assign(Tensor(numpy.fromfile(fn, " numpy.ndarray: - """ - Loads an image in the shape expected by other functions in this module. - Doesn't Tensor it, in case you need to do further work with it. - """ - # file - na = numpy.array(Image.open(path)) - if na.shape[2] == 4: - # RGBA -> RGB (covers opaque images with alpha channels) - na = na[:,:,0:3] - # fix shape - na = numpy.moveaxis(na, [2,0,1], [0,1,2]) - # shape is now (3,h,w), add 1 - na = na.reshape(1,3,na.shape[1],na.shape[2]) - # change type - na = na.astype("float32") / 255.0 - return na - -def image_save(path, na: numpy.ndarray): - """ - Saves an image of the shape expected by other functions in this module. - However, note this expects a numpy array. - """ - # change type - na = numpy.fmax(numpy.fmin(na * 255.0, 255), 0).astype("uint8") - # shape is now (1,3,h,w), remove 1 - na = na.reshape(3,na.shape[2],na.shape[3]) - # fix shape - na = numpy.moveaxis(na, [0,1,2], [2,0,1]) - # shape is now (h,w,3) - # file - Image.fromarray(na).save(path) - -# The Model - -class Conv3x3Biased: - """ - A 3x3 convolution layer with some utility functions. - """ - def __init__(self, inC, outC, last = False): - # The properties must be named as "W" and "b". - # This is in an attempt to try and be roughly compatible with https://github.com/FHPythonUtils/Waifu2x - # though this cannot necessarily account for transposition and other such things. - - # Massively overstate the weights to get them to be focused on, - # since otherwise the biases overrule everything - self.W = Tensor.uniform(outC, inC, 3, 3) * 16.0 - # Layout-wise, blatant cheat, but serious_mnist does it. I'd guess channels either have to have a size of 1 or whatever the target is? - # Values-wise, entirely different blatant cheat. - # In most cases, use uniform bias, but tiny. - # For the last layer, use just 0.5, constant. - if last: - self.b = Tensor.zeros(1, outC, 1, 1) + 0.5 - else: - self.b = Tensor.uniform(1, outC, 1, 1) - - def forward(self, x): - # You might be thinking, "but what about padding?" - # Answer: Tiling is used to stitch everything back together, though you could pad the image before providing it. - return x.conv2d(self.W).add(self.b) - - def get_parameters(self) -> list: - return [self.W, self.b] - - def load_waifu2x_json(self, layer: dict): - # Weights in this file are outChannel,inChannel,X,Y. - # Not outChannel,inChannel,Y,X. - # Therefore, transpose it before assignment. - # I have long since forgotten how I worked this out. - self.W.assign(Tensor(layer["weight"]).reshape(shape=self.W.shape).transpose(2, 3)) - self.b.assign(Tensor(layer["bias"]).reshape(shape=self.b.shape)) - -class Vgg7: - """ - The 'vgg7' waifu2x network. - Lower quality and slower than even upconv7 (nevermind cunet), but is very easy to implement and test. - """ - - def __init__(self): - self.conv1 = Conv3x3Biased(3, 32) - self.conv2 = Conv3x3Biased(32, 32) - self.conv3 = Conv3x3Biased(32, 64) - self.conv4 = Conv3x3Biased(64, 64) - self.conv5 = Conv3x3Biased(64, 128) - self.conv6 = Conv3x3Biased(128, 128) - self.conv7 = Conv3x3Biased(128, 3, True) - - def forward(self, x): - """ - Forward pass: Actually runs the network. - Input format: (1, 3, Y, X) - Output format: (1, 3, Y - 14, X - 14) - (the - 14 represents the 7-pixel context border that is lost) - """ - x = self.conv1.forward(x).leaky_relu(0.1) - x = self.conv2.forward(x).leaky_relu(0.1) - x = self.conv3.forward(x).leaky_relu(0.1) - x = self.conv4.forward(x).leaky_relu(0.1) - x = self.conv5.forward(x).leaky_relu(0.1) - x = self.conv6.forward(x).leaky_relu(0.1) - x = self.conv7.forward(x) - return x - - def get_parameters(self) -> list: - return self.conv1.get_parameters() + self.conv2.get_parameters() + self.conv3.get_parameters() + self.conv4.get_parameters() + self.conv5.get_parameters() + self.conv6.get_parameters() + self.conv7.get_parameters() - - def load_from_pretrained(self, intent = "art", subtype = "scale2.0x"): - """ - Downloads a nagadomi/waifu2x JSON weight file and loads it. - """ - import json - data = json.loads(fetch("https://github.com/nagadomi/waifu2x/raw/master/models/vgg_7/" + intent + "/" + subtype + "_model.json").read_bytes()) - self.load_waifu2x_json(data) - - def load_waifu2x_json(self, data: list): - """ - Loads weights from one of the waifu2x JSON files, i.e. waifu2x/models/vgg_7/art/noise0_model.json - data (passed in) is assumed to be the output of json.load or some similar on such a file - """ - self.conv1.load_waifu2x_json(data[0]) - self.conv2.load_waifu2x_json(data[1]) - self.conv3.load_waifu2x_json(data[2]) - self.conv4.load_waifu2x_json(data[3]) - self.conv5.load_waifu2x_json(data[4]) - self.conv6.load_waifu2x_json(data[5]) - self.conv7.load_waifu2x_json(data[6]) - - def forward_tiled(self, image: numpy.ndarray, tile_size: int) -> numpy.ndarray: - """ - Given an ndarray image as loaded by image_load (NOT a tensor), scales it, pads it, splits it up, forwards the pieces, and reconstitutes it. - Note that you really shouldn't try to run anything not (1, 3, *, *) through this. - """ - # Constant that only really gets repeated a ton here. - context = 7 - context2 = context + context - - # Notably, numpy is used here because it makes this fine manipulation a lot simpler. - # Scaling first - repeat on axis 2 and axis 3 (Y & X) - image = image.repeat(2, 2).repeat(2, 3) - - # Resulting image buffer. This is made before the input is padded, - # since the input has the padded shape right now. - image_out = numpy.zeros(image.shape) - - # Padding next. Note that this padding is done on the whole image. - # Padding the tiles would lose critical context, cause seams, etc. - image = numpy.pad(image, [[0, 0], [0, 0], [context, context], [context, context]], mode = "edge") - - # Now for tiling. - # The output tile size is the usable output from an input tile (tile_size). - # As such, the tiles overlap. - out_tile_size = tile_size - context2 - for out_y in range(0, image_out.shape[2], out_tile_size): - for out_x in range(0, image_out.shape[3], out_tile_size): - # Input is sourced from the same coordinates, but some stuff ought to be - # noted here for future reference: - # + out_x/y's equivalent position w/ the padding is out_x + context. - # + The output, however, is without context. Input needs context. - # + Therefore, the input rectangle is expanded on all sides by context. - # + Therefore, the input position has the context subtracted again. - # + Therefore: - in_y = out_y - in_x = out_x - # not shown: in_w/in_h = tile_size (as opposed to out_tile_size) - # Extract tile. - # Note that numpy will auto-crop this at the bottom-right. - # This will never be a problem, as tiles are specifically chosen within the padded section. - tile = image[:, :, in_y:in_y + tile_size, in_x:in_x + tile_size] - # Extracted tile dimensions -> output dimensions - # This is important because of said cropping, otherwise it'd be interior tile size. - out_h = tile.shape[2] - context2 - out_w = tile.shape[3] - context2 - # Process tile. - tile_t = Tensor(tile) - tile_fwd_t = self.forward(tile_t) - # Replace tile. - image_out[:, :, out_y:out_y + out_h, out_x:out_x + out_w] = tile_fwd_t.numpy() - - return image_out - diff --git a/tinygrad/examples/vit.py b/tinygrad/examples/vit.py deleted file mode 100644 index bf9a8f5d..00000000 --- a/tinygrad/examples/vit.py +++ /dev/null @@ -1,46 +0,0 @@ -import ast -import numpy as np -from PIL import Image -from tinygrad.tensor import Tensor -from tinygrad.helpers import getenv, fetch -from extra.models.vit import ViT -""" -fn = "gs://vit_models/augreg/Ti_16-i21k-300ep-lr_0.001-aug_none-wd_0.03-do_0.0-sd_0.0.npz" -import tensorflow as tf -with tf.io.gfile.GFile(fn, "rb") as f: - dat = f.read() - with open("cache/"+ fn.rsplit("/", 1)[1], "wb") as g: - g.write(dat) -""" - -Tensor.training = False -if getenv("LARGE", 0) == 1: - m = ViT(embed_dim=768, num_heads=12) -else: - # tiny - m = ViT(embed_dim=192, num_heads=3) -m.load_from_pretrained() - -# category labels -lbls = ast.literal_eval(fetch("https://gist.githubusercontent.com/yrevar/942d3a0ac09ec9e5eb3a/raw/238f720ff059c1f82f368259d1ca4ffa5dd8f9f5/imagenet1000_clsidx_to_labels.txt").read_text()) - -#url = "https://upload.wikimedia.org/wikipedia/commons/4/41/Chicken.jpg" -url = "https://repository-images.githubusercontent.com/296744635/39ba6700-082d-11eb-98b8-cb29fb7369c0" - -# junk -img = Image.open(fetch(url)) -aspect_ratio = img.size[0] / img.size[1] -img = img.resize((int(224*max(aspect_ratio,1.0)), int(224*max(1.0/aspect_ratio,1.0)))) -img = np.array(img) -y0,x0=(np.asarray(img.shape)[:2]-224)//2 -img = img[y0:y0+224, x0:x0+224] -img = np.moveaxis(img, [2,0,1], [0,1,2]) -img = img.astype(np.float32)[:3].reshape(1,3,224,224) -img /= 255.0 -img -= 0.5 -img /= 0.5 - -out = m.forward(Tensor(img)) -outnp = out.numpy().ravel() -choice = outnp.argmax() -print(out.shape, choice, outnp[choice], lbls[choice]) diff --git a/tinygrad/examples/vits.py b/tinygrad/examples/vits.py deleted file mode 100644 index b315a525..00000000 --- a/tinygrad/examples/vits.py +++ /dev/null @@ -1,740 +0,0 @@ -import json, logging, math, re, sys, time, wave, argparse, numpy as np -from phonemizer.phonemize import default_separator, _phonemize -from phonemizer.backend import EspeakBackend -from phonemizer.punctuation import Punctuation -from functools import reduce -from pathlib import Path -from typing import List -from tinygrad import nn, dtypes -from tinygrad.helpers import fetch -from tinygrad.nn.state import torch_load -from tinygrad.tensor import Tensor -from tinygrad.engine.jit import TinyJit -from unidecode import unidecode - -LRELU_SLOPE = 0.1 - -class Synthesizer: - def __init__(self, n_vocab, spec_channels, segment_size, inter_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, n_speakers=0, gin_channels=0, use_sdp=True, emotion_embedding=False, **kwargs): - self.n_vocab, self.spec_channels, self.inter_channels, self.hidden_channels, self.filter_channels, self.n_heads, self.n_layers, self.kernel_size, self.p_dropout, self.resblock, self.resblock_kernel_sizes, self.resblock_dilation_sizes, self.upsample_rates, self.upsample_initial_channel, self.upsample_kernel_sizes, self.segment_size, self.n_speakers, self.gin_channels, self.use_sdp = n_vocab, spec_channels, inter_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, segment_size, n_speakers, gin_channels, use_sdp - self.enc_p = TextEncoder(n_vocab, inter_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, emotion_embedding) - self.dec = Generator(inter_channels, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels=gin_channels) - self.enc_q = PosteriorEncoder(spec_channels, inter_channels, hidden_channels, 5, 1, 16, gin_channels=gin_channels) - self.flow = ResidualCouplingBlock(inter_channels, hidden_channels, 5, 1, 4, gin_channels=gin_channels) - self.dp = StochasticDurationPredictor(hidden_channels, 192, 3, 0.5, 4, gin_channels=gin_channels) if use_sdp else DurationPredictor(hidden_channels, 256, 3, 0.5, gin_channels=gin_channels) - if n_speakers > 1: self.emb_g = nn.Embedding(n_speakers, gin_channels) - def infer(self, x, x_lengths, sid=None, noise_scale=1.0, length_scale=1, noise_scale_w=1., max_len=None, emotion_embedding=None, max_y_length_estimate_scale=None, pad_length=-1): - x, m_p, logs_p, x_mask = self.enc_p.forward(x.realize(), x_lengths.realize(), emotion_embedding.realize() if emotion_embedding is not None else emotion_embedding) - g = self.emb_g(sid.reshape(1, 1)).squeeze(1).unsqueeze(-1) if self.n_speakers > 0 else None - logw = self.dp.forward(x, x_mask.realize(), g=g.realize(), reverse=self.use_sdp, noise_scale=noise_scale_w if self.use_sdp else 1.0) - w_ceil = Tensor.ceil(logw.exp() * x_mask * length_scale) - y_lengths = Tensor.maximum(w_ceil.sum([1, 2]), 1).cast(dtypes.int64) - return self.generate(g, logs_p, m_p, max_len, max_y_length_estimate_scale, noise_scale, w_ceil, x, x_mask, y_lengths, pad_length) - def generate(self, g, logs_p, m_p, max_len, max_y_length_estimate_scale, noise_scale, w_ceil, x, x_mask, y_lengths, pad_length): - max_y_length = y_lengths.max().item() if max_y_length_estimate_scale is None else max(15, x.shape[-1]) * max_y_length_estimate_scale - y_mask = sequence_mask(y_lengths, max_y_length).unsqueeze(1).cast(x_mask.dtype) - attn_mask = x_mask.unsqueeze(2) * y_mask.unsqueeze(-1) - attn = generate_path(w_ceil, attn_mask) - m_p_2 = attn.squeeze(1).matmul(m_p.transpose(1, 2)).transpose(1, 2) # [b, t', t], [b, t, d] -> [b, d, t'] - logs_p_2 = attn.squeeze(1).matmul(logs_p.transpose(1, 2)).transpose(1, 2) # [b, t', t], [b, t, d] -> [b, d, t'] - z_p = m_p_2 + Tensor.randn(*m_p_2.shape, dtype=m_p_2.dtype) * logs_p_2.exp() * noise_scale - row_len = y_mask.shape[2] - if pad_length > -1: - # Pad flow forward inputs to enable JIT - assert pad_length > row_len, "pad length is too small" - y_mask = y_mask.pad(((0, 0), (0, 0), (0, pad_length - row_len))).cast(z_p.dtype) - # New y_mask tensor to remove sts mask - y_mask = Tensor(y_mask.numpy(), device=y_mask.device, dtype=y_mask.dtype, requires_grad=y_mask.requires_grad) - z_p = z_p.squeeze(0).pad(((0, 0), (0, pad_length - z_p.shape[2])), value=1).unsqueeze(0) - z = self.flow.forward(z_p.realize(), y_mask.realize(), g=g.realize(), reverse=True) - result_length = reduce(lambda x, y: x * y, self.dec.upsample_rates, row_len) - o = self.dec.forward((z * y_mask)[:, :, :max_len], g=g)[:, :, :result_length] - if max_y_length_estimate_scale is not None: - length_scaler = o.shape[-1] / max_y_length - o.realize() - real_max_y_length = y_lengths.max().numpy() - if real_max_y_length > max_y_length: - logging.warning(f"Underestimated max length by {(((real_max_y_length / max_y_length) * 100) - 100):.2f}%, recomputing inference without estimate...") - return self.generate(g, logs_p, m_p, max_len, None, noise_scale, w_ceil, x, x_mask, y_lengths) - if real_max_y_length < max_y_length: - overestimation = ((max_y_length / real_max_y_length) * 100) - 100 - logging.info(f"Overestimated max length by {overestimation:.2f}%") - if overestimation > 10: logging.warning("Warning: max length overestimated by more than 10%") - o = o[:, :, :(real_max_y_length * length_scaler).astype(np.int32)] - return o - -class StochasticDurationPredictor: - def __init__(self, in_channels, filter_channels, kernel_size, p_dropout, n_flows=4, gin_channels=0): - filter_channels = in_channels # it needs to be removed from future version. - self.in_channels, self.filter_channels, self.kernel_size, self.p_dropout, self.n_flows, self.gin_channels = in_channels, filter_channels, kernel_size, p_dropout, n_flows, gin_channels - self.log_flow, self.flows = Log(), [ElementwiseAffine(2)] - for _ in range(n_flows): - self.flows.append(ConvFlow(2, filter_channels, kernel_size, n_layers=3)) - self.flows.append(Flip()) - self.post_pre, self.post_proj = nn.Conv1d(1, filter_channels, 1), nn.Conv1d(filter_channels, filter_channels, 1) - self.post_convs = DDSConv(filter_channels, kernel_size, n_layers=3, p_dropout=p_dropout) - self.post_flows = [ElementwiseAffine(2)] - for _ in range(4): - self.post_flows.append(ConvFlow(2, filter_channels, kernel_size, n_layers=3)) - self.post_flows.append(Flip()) - self.pre, self.proj = nn.Conv1d(in_channels, filter_channels, 1), nn.Conv1d(filter_channels, filter_channels, 1) - self.convs = DDSConv(filter_channels, kernel_size, n_layers=3, p_dropout=p_dropout) - if gin_channels != 0: self.cond = nn.Conv1d(gin_channels, filter_channels, 1) - @TinyJit - def forward(self, x: Tensor, x_mask, w=None, g=None, reverse=False, noise_scale=1.0): - x = self.pre(x.detach()) - if g is not None: x = x + self.cond(g.detach()) - x = self.convs.forward(x, x_mask) - x = self.proj(x) * x_mask - if not reverse: - flows = self.flows - assert w is not None - log_det_tot_q = 0 - h_w = self.post_proj(self.post_convs.forward(self.post_pre(w), x_mask)) * x_mask - e_q = Tensor.randn(w.size(0), 2, w.size(2), dtype=x.dtype).to(device=x.device) * x_mask - z_q = e_q - for flow in self.post_flows: - z_q, log_det_q = flow.forward(z_q, x_mask, g=(x + h_w)) - log_det_tot_q += log_det_q - z_u, z1 = z_q.split([1, 1], 1) - u = z_u.sigmoid() * x_mask - z0 = (w - u) * x_mask - log_det_tot_q += Tensor.sum((z_u.logsigmoid() + (-z_u).logsigmoid()) * x_mask, [1,2]) - log_q = Tensor.sum(-0.5 * (math.log(2*math.pi) + (e_q**2)) * x_mask, [1,2]) - log_det_tot_q - log_det_tot = 0 - z0, log_det = self.log_flow.forward(z0, x_mask) - log_det_tot += log_det - z = z0.cat(z1, 1) - for flow in flows: - z, log_det = flow.forward(z, x_mask, g=x, reverse=reverse) - log_det_tot = log_det_tot + log_det - nll = Tensor.sum(0.5 * (math.log(2*math.pi) + (z**2)) * x_mask, [1,2]) - log_det_tot - return (nll + log_q).realize() # [b] - flows = list(reversed(self.flows)) - flows = flows[:-2] + [flows[-1]] # remove a useless vflow - z = Tensor.randn(x.shape[0], 2, x.shape[2], dtype=x.dtype).to(device=x.device) * noise_scale - for flow in flows: z = flow.forward(z, x_mask, g=x, reverse=reverse) - z0, z1 = z.split([1, 1], 1) - return z0.realize() - -class DurationPredictor: - def __init__(self, in_channels, filter_channels, kernel_size, p_dropout, gin_channels=0): - self.in_channels, self.filter_channels, self.kernel_size, self.p_dropout, self.gin_channels = in_channels, filter_channels, kernel_size, p_dropout, gin_channels - self.conv_1, self.norm_1 = nn.Conv1d(in_channels, filter_channels, kernel_size, padding=kernel_size//2), LayerNorm(filter_channels) - self.conv_2, self.norm_2 = nn.Conv1d(filter_channels, filter_channels, kernel_size, padding=kernel_size//2), LayerNorm(filter_channels) - self.proj = nn.Conv1d(filter_channels, 1, 1) - if gin_channels != 0: self.cond = nn.Conv1d(gin_channels, in_channels, 1) - def forward(self, x: Tensor, x_mask, g=None): - x = x.detach() - if g is not None: x = x + self.cond(g.detach()) - x = self.conv_1(x * x_mask).relu() - x = self.norm_1(x).dropout(self.p_dropout) - x = self.conv_2(x * x_mask).relu(x) - x = self.norm_2(x).dropout(self.p_dropout) - return self.proj(x * x_mask) * x_mask - -class TextEncoder: - def __init__(self, n_vocab, out_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, emotion_embedding): - self.n_vocab, self.out_channels, self.hidden_channels, self.filter_channels, self.n_heads, self.n_layers, self.kernel_size, self.p_dropout = n_vocab, out_channels, hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout - if n_vocab!=0:self.emb = nn.Embedding(n_vocab, hidden_channels) - if emotion_embedding: self.emo_proj = nn.Linear(1024, hidden_channels) - self.encoder = Encoder(hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout) - self.proj = nn.Conv1d(hidden_channels, out_channels * 2, 1) - @TinyJit - def forward(self, x: Tensor, x_lengths: Tensor, emotion_embedding=None): - if self.n_vocab!=0: x = (self.emb(x) * math.sqrt(self.hidden_channels)) - if emotion_embedding: x = x + self.emo_proj(emotion_embedding).unsqueeze(1) - x = x.transpose(1, -1) # [b, t, h] -transpose-> [b, h, t] - x_mask = sequence_mask(x_lengths, x.shape[2]).unsqueeze(1).cast(x.dtype) - x = self.encoder.forward(x * x_mask, x_mask) - m, logs = (self.proj(x) * x_mask).split(self.out_channels, dim=1) - return x.realize(), m.realize(), logs.realize(), x_mask.realize() - -class ResidualCouplingBlock: - def __init__(self, channels, hidden_channels, kernel_size, dilation_rate, n_layers, n_flows=4, gin_channels=0): - self.channels, self.hidden_channels, self.kernel_size, self.dilation_rate, self.n_layers, self.n_flows, self.gin_channels = channels, hidden_channels, kernel_size, dilation_rate, n_layers, n_flows, gin_channels - self.flows = [] - for _ in range(n_flows): - self.flows.append(ResidualCouplingLayer(channels, hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels=gin_channels, mean_only=True)) - self.flows.append(Flip()) - @TinyJit - def forward(self, x, x_mask, g=None, reverse=False): - for flow in reversed(self.flows) if reverse else self.flows: x = flow.forward(x, x_mask, g=g, reverse=reverse) - return x.realize() - -class PosteriorEncoder: - def __init__(self, in_channels, out_channels, hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels=0): - self.in_channels, self.out_channels, self.hidden_channels, self.kernel_size, self.dilation_rate, self.n_layers, self.gin_channels = in_channels, out_channels, hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels - self.pre, self.proj = nn.Conv1d(in_channels, hidden_channels, 1), nn.Conv1d(hidden_channels, out_channels * 2, 1) - self.enc = WN(hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels=gin_channels) - def forward(self, x, x_lengths, g=None): - x_mask = sequence_mask(x_lengths, x.size(2)).unsqueeze(1).cast(x.dtype) - stats = self.proj(self.enc.forward(self.pre(x) * x_mask, x_mask, g=g)) * x_mask - m, logs = stats.split(self.out_channels, dim=1) - z = (m + Tensor.randn(m.shape, m.dtype) * logs.exp()) * x_mask - return z, m, logs, x_mask - -class Generator: - def __init__(self, initial_channel, resblock, resblock_kernel_sizes, resblock_dilation_sizes, upsample_rates, upsample_initial_channel, upsample_kernel_sizes, gin_channels=0): - self.num_kernels, self.num_upsamples = len(resblock_kernel_sizes), len(upsample_rates) - self.conv_pre = nn.Conv1d(initial_channel, upsample_initial_channel, 7, 1, padding=3) - resblock = ResBlock1 if resblock == '1' else ResBlock2 - self.ups = [nn.ConvTranspose1d(upsample_initial_channel//(2**i), upsample_initial_channel//(2**(i+1)), k, u, padding=(k-u)//2) for i, (u, k) in enumerate(zip(upsample_rates, upsample_kernel_sizes))] - self.resblocks = [] - self.upsample_rates = upsample_rates - for i in range(len(self.ups)): - ch = upsample_initial_channel // (2 ** (i + 1)) - for _, (k, d) in enumerate(zip(resblock_kernel_sizes, resblock_dilation_sizes)): - self.resblocks.append(resblock(ch, k, d)) - self.conv_post = nn.Conv1d(ch, 1, 7, 1, padding=3, bias=False) - if gin_channels != 0: self.cond = nn.Conv1d(gin_channels, upsample_initial_channel, 1) - @TinyJit - def forward(self, x: Tensor, g=None): - x = self.conv_pre(x) - if g is not None: x = x + self.cond(g) - for i in range(self.num_upsamples): - x = self.ups[i](x.leaky_relu(LRELU_SLOPE)) - xs = sum(self.resblocks[i * self.num_kernels + j].forward(x) for j in range(self.num_kernels)) - x = (xs / self.num_kernels).realize() - res = self.conv_post(x.leaky_relu()).tanh().realize() - return res - -class LayerNorm(nn.LayerNorm): - def __init__(self, channels, eps=1e-5): super().__init__(channels, eps, elementwise_affine=True) - def forward(self, x: Tensor): return self.__call__(x.transpose(1, -1)).transpose(1, -1) - -class WN: - def __init__(self, hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels=0, p_dropout=0): - assert (kernel_size % 2 == 1) - self.hidden_channels, self.kernel_size, self.dilation_rate, self.n_layers, self.gin_channels, self.p_dropout = hidden_channels, kernel_size, dilation_rate, n_layers, gin_channels, p_dropout - self.in_layers, self.res_skip_layers = [], [] - if gin_channels != 0: self.cond_layer = nn.Conv1d(gin_channels, 2 * hidden_channels * n_layers, 1) - for i in range(n_layers): - dilation = dilation_rate ** i - self.in_layers.append(nn.Conv1d(hidden_channels, 2 * hidden_channels, kernel_size, dilation=dilation, padding=int((kernel_size * dilation - dilation) / 2))) - self.res_skip_layers.append(nn.Conv1d(hidden_channels, 2 * hidden_channels if i < n_layers - 1 else hidden_channels, 1)) - def forward(self, x, x_mask, g=None, **kwargs): - output = Tensor.zeros_like(x) - if g is not None: g = self.cond_layer(g) - for i in range(self.n_layers): - x_in = self.in_layers[i](x) - if g is not None: - cond_offset = i * 2 * self.hidden_channels - g_l = g[:, cond_offset:cond_offset + 2 * self.hidden_channels, :] - else: - g_l = Tensor.zeros_like(x_in) - acts = fused_add_tanh_sigmoid_multiply(x_in, g_l, self.hidden_channels) - res_skip_acts = self.res_skip_layers[i](acts) - if i < self.n_layers - 1: - x = (x + res_skip_acts[:, :self.hidden_channels, :]) * x_mask - output = output + res_skip_acts[:, self.hidden_channels:, :] - else: - output = output + res_skip_acts - return output * x_mask - -class ResBlock1: - def __init__(self, channels, kernel_size=3, dilation=(1, 3, 5)): - self.convs1 = [nn.Conv1d(channels, channels, kernel_size, 1, dilation=dilation[i], padding=get_padding(kernel_size, dilation[i])) for i in range(3)] - self.convs2 = [nn.Conv1d(channels, channels, kernel_size, 1, dilation=1, padding=get_padding(kernel_size, 1)) for _ in range(3)] - def forward(self, x: Tensor, x_mask=None): - for c1, c2 in zip(self.convs1, self.convs2): - xt = x.leaky_relu(LRELU_SLOPE) - xt = c1(xt if x_mask is None else xt * x_mask).leaky_relu(LRELU_SLOPE) - x = c2(xt if x_mask is None else xt * x_mask) + x - return x if x_mask is None else x * x_mask - -class ResBlock2: - def __init__(self, channels, kernel_size=3, dilation=(1, 3)): - self.convs = [nn.Conv1d(channels, channels, kernel_size, 1, dilation=dilation[i], padding=get_padding(kernel_size, dilation[i])) for i in range(2)] - def forward(self, x, x_mask=None): - for c in self.convs: - xt = x.leaky_relu(LRELU_SLOPE) - xt = c(xt if x_mask is None else xt * x_mask) - x = xt + x - return x if x_mask is None else x * x_mask - -class DDSConv: # Dilated and Depth-Separable Convolution - def __init__(self, channels, kernel_size, n_layers, p_dropout=0.): - self.channels, self.kernel_size, self.n_layers, self.p_dropout = channels, kernel_size, n_layers, p_dropout - self.convs_sep, self.convs_1x1, self.norms_1, self.norms_2 = [], [], [], [] - for i in range(n_layers): - dilation = kernel_size ** i - padding = (kernel_size * dilation - dilation) // 2 - self.convs_sep.append(nn.Conv1d(channels, channels, kernel_size, groups=channels, dilation=dilation, padding=padding)) - self.convs_1x1.append(nn.Conv1d(channels, channels, 1)) - self.norms_1.append(LayerNorm(channels)) - self.norms_2.append(LayerNorm(channels)) - def forward(self, x, x_mask, g=None): - if g is not None: x = x + g - for i in range(self.n_layers): - y = self.convs_sep[i](x * x_mask) - y = self.norms_1[i].forward(y).gelu() - y = self.convs_1x1[i](y) - y = self.norms_2[i].forward(y).gelu() - x = x + y.dropout(self.p_dropout) - return x * x_mask - -class ConvFlow: - def __init__(self, in_channels, filter_channels, kernel_size, n_layers, num_bins=10, tail_bound=5.0): - self.in_channels, self.filter_channels, self.kernel_size, self.n_layers, self.num_bins, self.tail_bound = in_channels, filter_channels, kernel_size, n_layers, num_bins, tail_bound - self.half_channels = in_channels // 2 - self.pre = nn.Conv1d(self.half_channels, filter_channels, 1) - self.convs = DDSConv(filter_channels, kernel_size, n_layers, p_dropout=0.) - self.proj = nn.Conv1d(filter_channels, self.half_channels * (num_bins * 3 - 1), 1) - def forward(self, x, x_mask, g=None, reverse=False): - x0, x1 = x.split([self.half_channels] * 2, 1) - h = self.proj(self.convs.forward(self.pre(x0), x_mask, g=g)) * x_mask - b, c, t = x0.shape - h = h.reshape(b, c, -1, t).permute(0, 1, 3, 2) # [b, cx?, t] -> [b, c, t, ?] - un_normalized_widths = h[..., :self.num_bins] / math.sqrt(self.filter_channels) - un_normalized_heights = h[..., self.num_bins:2*self.num_bins] / math.sqrt(self.filter_channels) - un_normalized_derivatives = h[..., 2 * self.num_bins:] - x1, log_abs_det = piecewise_rational_quadratic_transform(x1, un_normalized_widths, un_normalized_heights, un_normalized_derivatives, inverse=reverse, tails='linear', tail_bound=self.tail_bound) - x = x0.cat(x1, dim=1) * x_mask - return x if reverse else (x, Tensor.sum(log_abs_det * x_mask, [1,2])) - -class ResidualCouplingLayer: - def __init__(self, channels, hidden_channels, kernel_size, dilation_rate, n_layers, p_dropout=0, gin_channels=0, mean_only=False): - assert channels % 2 == 0, "channels should be divisible by 2" - self.channels, self.hidden_channels, self.kernel_size, self.dilation_rate, self.n_layers, self.mean_only = channels, hidden_channels, kernel_size, dilation_rate, n_layers, mean_only - self.half_channels = channels // 2 - self.pre = nn.Conv1d(self.half_channels, hidden_channels, 1) - self.enc = WN(hidden_channels, kernel_size, dilation_rate, n_layers, p_dropout=p_dropout, gin_channels=gin_channels) - self.post = nn.Conv1d(hidden_channels, self.half_channels * (2 - mean_only), 1) - def forward(self, x, x_mask, g=None, reverse=False): - x0, x1 = x.split([self.half_channels] * 2, 1) - stats = self.post(self.enc.forward(self.pre(x0) * x_mask, x_mask, g=g)) * x_mask - if not self.mean_only: - m, logs = stats.split([self.half_channels] * 2, 1) - else: - m = stats - logs = Tensor.zeros_like(m) - if not reverse: return x0.cat((m + x1 * logs.exp() * x_mask), dim=1) - return x0.cat(((x1 - m) * (-logs).exp() * x_mask), dim=1) - -class Log: - def forward(self, x : Tensor, x_mask, reverse=False): - if not reverse: - y = x.maximum(1e-5).log() * x_mask - return y, (-y).sum([1, 2]) - return x.exp() * x_mask - -class Flip: - def forward(self, x: Tensor, *args, reverse=False, **kwargs): - return x.flip([1]) if reverse else (x.flip([1]), Tensor.zeros(x.shape[0], dtype=x.dtype).to(device=x.device)) - -class ElementwiseAffine: - def __init__(self, channels): self.m, self.logs = Tensor.zeros(channels, 1), Tensor.zeros(channels, 1) - def forward(self, x, x_mask, reverse=False, **kwargs): # x if reverse else y, logdet - return (x - self.m) * Tensor.exp(-self.logs) * x_mask if reverse \ - else ((self.m + Tensor.exp(self.logs) * x) * x_mask, Tensor.sum(self.logs * x_mask, [1, 2])) - -class MultiHeadAttention: - def __init__(self, channels, out_channels, n_heads, p_dropout=0., window_size=None, heads_share=True, block_length=None, proximal_bias=False, proximal_init=False): - assert channels % n_heads == 0 - self.channels, self.out_channels, self.n_heads, self.p_dropout, self.window_size, self.heads_share, self.block_length, self.proximal_bias, self.proximal_init = channels, out_channels, n_heads, p_dropout, window_size, heads_share, block_length, proximal_bias, proximal_init - self.attn, self.k_channels = None, channels // n_heads - self.conv_q, self.conv_k, self.conv_v = [nn.Conv1d(channels, channels, 1) for _ in range(3)] - self.conv_o = nn.Conv1d(channels, out_channels, 1) - if window_size is not None: self.emb_rel_k, self.emb_rel_v = [Tensor.randn(1 if heads_share else n_heads, window_size * 2 + 1, self.k_channels) * (self.k_channels ** -0.5) for _ in range(2)] - def forward(self, x, c, attn_mask=None): - q, k, v = self.conv_q(x), self.conv_k(c), self.conv_v(c) - x, self.attn = self.attention(q, k, v, mask=attn_mask) - return self.conv_o(x) - def attention(self, query: Tensor, key: Tensor, value: Tensor, mask=None):# reshape [b, d, t] -> [b, n_h, t, d_k] - b, d, t_s, t_t = key.shape[0], key.shape[1], key.shape[2], query.shape[2] - query = query.reshape(b, self.n_heads, self.k_channels, t_t).transpose(2, 3) - key = key.reshape(b, self.n_heads, self.k_channels, t_s).transpose(2, 3) - value = value.reshape(b, self.n_heads, self.k_channels, t_s).transpose(2, 3) - scores = (query / math.sqrt(self.k_channels)) @ key.transpose(-2, -1) - if self.window_size is not None: - assert t_s == t_t, "Relative attention is only available for self-attention." - key_relative_embeddings = self._get_relative_embeddings(self.emb_rel_k, t_s) - rel_logits = self._matmul_with_relative_keys(query / math.sqrt(self.k_channels), key_relative_embeddings) - scores = scores + self._relative_position_to_absolute_position(rel_logits) - if mask is not None: - scores = Tensor.where(mask, scores, -1e4) - if self.block_length is not None: - assert t_s == t_t, "Local attention is only available for self-attention." - scores = Tensor.where(Tensor.ones_like(scores).triu(-self.block_length).tril(self.block_length), scores, -1e4) - p_attn = scores.softmax(axis=-1) # [b, n_h, t_t, t_s] - output = p_attn.matmul(value) - if self.window_size is not None: - relative_weights = self._absolute_position_to_relative_position(p_attn) - value_relative_embeddings = self._get_relative_embeddings(self.emb_rel_v, t_s) - output = output + self._matmul_with_relative_values(relative_weights, value_relative_embeddings) - output = output.transpose(2, 3).contiguous().reshape(b, d, t_t) # [b, n_h, t_t, d_k] -> [b, d, t_t] - return output, p_attn - def _matmul_with_relative_values(self, x, y): return x.matmul(y.unsqueeze(0)) # x: [b, h, l, m], y: [h or 1, m, d], ret: [b, h, l, d] - def _matmul_with_relative_keys(self, x, y): return x.matmul(y.unsqueeze(0).transpose(-2, -1)) # x: [b, h, l, d], y: [h or 1, m, d], re, : [b, h, l, m] - def _get_relative_embeddings(self, relative_embeddings, length): - pad_length, slice_start_position = max(length - (self.window_size + 1), 0), max((self.window_size + 1) - length, 0) - padded_relative_embeddings = relative_embeddings if pad_length <= 0\ - else relative_embeddings.pad(convert_pad_shape([[0, 0], [pad_length, pad_length], [0, 0]])) - return padded_relative_embeddings[:, slice_start_position:(slice_start_position + 2 * length - 1)] #used_relative_embeddings - def _relative_position_to_absolute_position(self, x: Tensor): # x: [b, h, l, 2*l-1] -> [b, h, l, l] - batch, heads, length, _ = x.shape - x = x.pad(convert_pad_shape([[0,0],[0,0],[0,0],[0,1]])) - x_flat = x.reshape([batch, heads, length * 2 * length]).pad(convert_pad_shape([[0,0],[0,0],[0,length-1]])) - return x_flat.reshape([batch, heads, length+1, 2*length-1])[:, :, :length, length-1:] - def _absolute_position_to_relative_position(self, x: Tensor): # x: [b, h, l, l] -> [b, h, l, 2*l-1] - batch, heads, length, _ = x.shape - x = x.pad(convert_pad_shape([[0, 0], [0, 0], [0, 0], [0, length-1]])) - x_flat = x.reshape([batch, heads, length**2 + length*(length -1)]).pad(convert_pad_shape([[0, 0], [0, 0], [length, 0]])) - return x_flat.reshape([batch, heads, length, 2*length])[:,:,:,1:] - -class FFN: - def __init__(self, in_channels, out_channels, filter_channels, kernel_size, p_dropout=0., activation=None, causal=False): - self.in_channels, self.out_channels, self.filter_channels, self.kernel_size, self.p_dropout, self.activation, self.causal = in_channels, out_channels, filter_channels, kernel_size, p_dropout, activation, causal - self.padding = self._causal_padding if causal else self._same_padding - self.conv_1, self.conv_2 = nn.Conv1d(in_channels, filter_channels, kernel_size), nn.Conv1d(filter_channels, out_channels, kernel_size) - def forward(self, x, x_mask): - x = self.conv_1(self.padding(x * x_mask)) - x = x * (1.702 * x).sigmoid() if self.activation == "gelu" else x.relu() - return self.conv_2(self.padding(x.dropout(self.p_dropout) * x_mask)) * x_mask - def _causal_padding(self, x):return x if self.kernel_size == 1 else x.pad(convert_pad_shape([[0, 0], [0, 0], [self.kernel_size - 1, 0]])) - def _same_padding(self, x): return x if self.kernel_size == 1 else x.pad(convert_pad_shape([[0, 0], [0, 0], [(self.kernel_size - 1) // 2, self.kernel_size // 2]])) - -class Encoder: - def __init__(self, hidden_channels, filter_channels, n_heads, n_layers, kernel_size=1, p_dropout=0., window_size=4, **kwargs): - self.hidden_channels, self.filter_channels, self.n_heads, self.n_layers, self.kernel_size, self.p_dropout, self.window_size = hidden_channels, filter_channels, n_heads, n_layers, kernel_size, p_dropout, window_size - self.attn_layers, self.norm_layers_1, self.ffn_layers, self.norm_layers_2 = [], [], [], [] - for _ in range(n_layers): - self.attn_layers.append(MultiHeadAttention(hidden_channels, hidden_channels, n_heads, p_dropout=p_dropout, window_size=window_size)) - self.norm_layers_1.append(LayerNorm(hidden_channels)) - self.ffn_layers.append(FFN(hidden_channels, hidden_channels, filter_channels, kernel_size, p_dropout=p_dropout)) - self.norm_layers_2.append(LayerNorm(hidden_channels)) - def forward(self, x, x_mask): - attn_mask, x = x_mask.unsqueeze(2) * x_mask.unsqueeze(-1), x * x_mask - for i in range(self.n_layers): - y = self.attn_layers[i].forward(x, x, attn_mask).dropout(self.p_dropout) - x = self.norm_layers_1[i].forward(x + y) - y = self.ffn_layers[i].forward(x, x_mask).dropout(self.p_dropout) - x = self.norm_layers_2[i].forward(x + y) - return x * x_mask - -DEFAULT_MIN_BIN_WIDTH, DEFAULT_MIN_BIN_HEIGHT, DEFAULT_MIN_DERIVATIVE = 1e-3, 1e-3, 1e-3 -def piecewise_rational_quadratic_transform(inputs, un_normalized_widths, un_normalized_heights, un_normalized_derivatives, inverse=False, tails=None, tail_bound=1., min_bin_width=DEFAULT_MIN_BIN_WIDTH, min_bin_height=DEFAULT_MIN_BIN_HEIGHT, min_derivative=DEFAULT_MIN_DERIVATIVE): - if tails is None: spline_fn, spline_kwargs = rational_quadratic_spline, {} - else: spline_fn, spline_kwargs = unconstrained_rational_quadratic_spline, {'tails': tails, 'tail_bound': tail_bound} - return spline_fn(inputs=inputs, un_normalized_widths=un_normalized_widths, un_normalized_heights=un_normalized_heights, un_normalized_derivatives=un_normalized_derivatives, inverse=inverse, min_bin_width=min_bin_width, min_bin_height=min_bin_height, min_derivative=min_derivative, **spline_kwargs) -def unconstrained_rational_quadratic_spline(inputs, un_normalized_widths, un_normalized_heights, un_normalized_derivatives, inverse=False, tails='linear', tail_bound=1., min_bin_width=DEFAULT_MIN_BIN_WIDTH, min_bin_height=DEFAULT_MIN_BIN_HEIGHT, min_derivative=DEFAULT_MIN_DERIVATIVE): - if not tails == 'linear': raise RuntimeError('{} tails are not implemented.'.format(tails)) - constant = np.log(np.exp(1 - min_derivative) - 1).item() - un_normalized_derivatives = cat_lr(un_normalized_derivatives, constant, constant) - output, log_abs_det = rational_quadratic_spline(inputs=inputs.squeeze(dim=0).squeeze(dim=0), unnormalized_widths=un_normalized_widths.squeeze(dim=0).squeeze(dim=0), unnormalized_heights=un_normalized_heights.squeeze(dim=0).squeeze(dim=0), unnormalized_derivatives=un_normalized_derivatives.squeeze(dim=0).squeeze(dim=0), inverse=inverse, left=-tail_bound, right=tail_bound, bottom=-tail_bound, top=tail_bound, min_bin_width=min_bin_width, min_bin_height=min_bin_height, min_derivative=min_derivative) - return output.unsqueeze(dim=0).unsqueeze(dim=0), log_abs_det.unsqueeze(dim=0).unsqueeze(dim=0) -def rational_quadratic_spline(inputs: Tensor, unnormalized_widths: Tensor, unnormalized_heights: Tensor, unnormalized_derivatives: Tensor, inverse=False, left=0., right=1., bottom=0., top=1., min_bin_width=DEFAULT_MIN_BIN_WIDTH, min_bin_height=DEFAULT_MIN_BIN_HEIGHT, min_derivative=DEFAULT_MIN_DERIVATIVE): - num_bins = unnormalized_widths.shape[-1] - if min_bin_width * num_bins > 1.0: raise ValueError('Minimal bin width too large for the number of bins') - if min_bin_height * num_bins > 1.0: raise ValueError('Minimal bin height too large for the number of bins') - widths = min_bin_width + (1 - min_bin_width * num_bins) * unnormalized_widths.softmax(axis=-1) - cum_widths = cat_lr(((right - left) * widths[..., :-1].cumsum(axis=1) + left), left, right + 1e-6 if not inverse else right) - widths = cum_widths[..., 1:] - cum_widths[..., :-1] - derivatives = min_derivative + (unnormalized_derivatives.exp()+1).log() - heights = min_bin_height + (1 - min_bin_height * num_bins) * unnormalized_heights.softmax(axis=-1) - cum_heights = cat_lr(((top - bottom) * heights[..., :-1].cumsum(axis=1) + bottom), bottom, top + 1e-6 if inverse else top) - heights = cum_heights[..., 1:] - cum_heights[..., :-1] - bin_idx = ((inputs[..., None] >= (cum_heights if inverse else cum_widths)).sum(axis=-1) - 1)[..., None] - input_cum_widths = gather(cum_widths, bin_idx, axis=-1)[..., 0] - input_bin_widths = gather(widths, bin_idx, axis=-1)[..., 0] - input_cum_heights = gather(cum_heights, bin_idx, axis=-1)[..., 0] - input_delta = gather(heights / widths, bin_idx, axis=-1)[..., 0] - input_derivatives = gather(derivatives, bin_idx, axis=-1)[..., 0] - input_derivatives_plus_one = gather(derivatives[..., 1:], bin_idx, axis=-1)[..., 0] - input_heights = gather(heights, bin_idx, axis=-1)[..., 0] - if inverse: - a = ((inputs - input_cum_heights) * (input_derivatives + input_derivatives_plus_one - 2 * input_delta) + input_heights * (input_delta - input_derivatives)) - b = (input_heights * input_derivatives - (inputs - input_cum_heights) * (input_derivatives + input_derivatives_plus_one - 2 * input_delta)) - c = - input_delta * (inputs - input_cum_heights) - discriminant = b.square() - 4 * a * c - # assert (discriminant.numpy() >= 0).all() - root = (2 * c) / (-b - discriminant.sqrt()) - theta_one_minus_theta = root * (1 - root) - denominator = input_delta + ((input_derivatives + input_derivatives_plus_one - 2 * input_delta) * theta_one_minus_theta) - derivative_numerator = input_delta.square() * (input_derivatives_plus_one * root.square() + 2 * input_delta * theta_one_minus_theta + input_derivatives * (1 - root).square()) - return root * input_bin_widths + input_cum_widths, -(derivative_numerator.log() - 2 * denominator.log()) - theta = (inputs - input_cum_widths) / input_bin_widths - theta_one_minus_theta = theta * (1 - theta) - numerator = input_heights * (input_delta * theta.pow(2) + input_derivatives * theta_one_minus_theta) - denominator = input_delta + ((input_derivatives + input_derivatives_plus_one - 2 * input_delta) * theta_one_minus_theta) - derivative_numerator = input_delta.pow(2) * (input_derivatives_plus_one * theta.pow(2) + 2 * input_delta * theta_one_minus_theta + input_derivatives * (1 - theta).pow(2)) - return input_cum_heights + numerator / denominator, derivative_numerator.log() - 2 * denominator.log() - -def sequence_mask(length: Tensor, max_length): return Tensor.arange(max_length, dtype=length.dtype, device=length.device).unsqueeze(0) < length.unsqueeze(1) -def generate_path(duration: Tensor, mask: Tensor): # duration: [b, 1, t_x], mask: [b, 1, t_y, t_x] - b, _, t_y, t_x = mask.shape - path = sequence_mask(duration.cumsum(axis=2).reshape(b * t_x), t_y).cast(mask.dtype).reshape(b, t_x, t_y) - path = path - path.pad(convert_pad_shape([[0, 0], [1, 0], [0, 0]]))[:, :-1] - return path.unsqueeze(1).transpose(2, 3) * mask -def fused_add_tanh_sigmoid_multiply(input_a: Tensor, input_b: Tensor, n_channels: int): - n_channels_int, in_act = n_channels, input_a + input_b - t_act, s_act = in_act[:, :n_channels_int, :].tanh(), in_act[:, n_channels_int:, :].sigmoid() - return t_act * s_act - -def cat_lr(t, left, right): return Tensor.full(get_shape(t), left).cat(t, dim=-1).cat(Tensor.full(get_shape(t), right), dim=-1) -def get_shape(tensor): - (shape := list(tensor.shape))[-1] = 1 - return tuple(shape) -def convert_pad_shape(pad_shape): return tuple(tuple(x) for x in pad_shape) -def get_padding(kernel_size, dilation=1): return int((kernel_size*dilation - dilation)/2) - -def gather(x, indices, axis): - indices = (indices < 0).where(indices + x.shape[axis], indices).transpose(0, axis) - permute_args = list(range(x.ndim)) - permute_args[0], permute_args[axis] = permute_args[axis], permute_args[0] - permute_args.append(permute_args.pop(0)) - x = x.permute(*permute_args) - reshape_arg = [1] * x.ndim + [x.shape[-1]] - return ((indices.unsqueeze(indices.ndim).expand(*indices.shape, x.shape[-1]) == - Tensor.arange(x.shape[-1]).reshape(*reshape_arg).expand(*indices.shape, x.shape[-1])) * x).sum(indices.ndim).transpose(0, axis) - -def norm_except_dim(v, dim): - if dim == -1: return np.linalg.norm(v) - if dim == 0: - (output_shape := [1] * v.ndim)[0] = v.shape[0] - return np.linalg.norm(v.reshape(v.shape[0], -1), axis=1).reshape(output_shape) - if dim == v.ndim - 1: - (output_shape := [1] * v.ndim)[-1] = v.shape[-1] - return np.linalg.norm(v.reshape(-1, v.shape[-1]), axis=0).reshape(output_shape) - transposed_v = np.transpose(v, (dim,) + tuple(i for i in range(v.ndim) if i != dim)) - return np.transpose(norm_except_dim(transposed_v, 0), (dim,) + tuple(i for i in range(v.ndim) if i != dim)) -def weight_norm(v: Tensor, g: Tensor, dim): - v, g = v.numpy(), g.numpy() - return Tensor(v * (g / norm_except_dim(v, dim))) - -# HPARAMS LOADING -def get_hparams_from_file(path): - with open(path, "r") as f: - data = f.read() - return HParams(**json.loads(data)) -class HParams: - def __init__(self, **kwargs): - for k, v in kwargs.items(): self[k] = v if type(v) != dict else HParams(**v) - def keys(self): return self.__dict__.keys() - def items(self): return self.__dict__.items() - def values(self): return self.__dict__.values() - def __len__(self): return len(self.__dict__) - def __getitem__(self, key): return getattr(self, key) - def __setitem__(self, key, value): return setattr(self, key, value) - def __contains__(self, key): return key in self.__dict__ - def __repr__(self): return self.__dict__.__repr__() - -# MODEL LOADING -def load_model(symbols, hps, model) -> Synthesizer: - net_g = Synthesizer(len(symbols), hps.data.filter_length // 2 + 1, hps.train.segment_size // hps.data.hop_length, n_speakers = hps.data.n_speakers, **hps.model) - _ = load_checkpoint(fetch(model[1]), net_g, None) - return net_g -def load_checkpoint(checkpoint_path, model: Synthesizer, optimizer=None, skip_list=[]): - assert Path(checkpoint_path).is_file() - start_time = time.time() - checkpoint_dict = torch_load(checkpoint_path) - iteration, learning_rate = checkpoint_dict['iteration'], checkpoint_dict['learning_rate'] - if optimizer: optimizer.load_state_dict(checkpoint_dict['optimizer']) - saved_state_dict = checkpoint_dict['model'] - weight_g, weight_v, parent = None, None, None - for key, v in saved_state_dict.items(): - if any(layer in key for layer in skip_list): continue - try: - obj, skip = model, False - for k in key.split('.'): - if k.isnumeric(): obj = obj[int(k)] - elif isinstance(obj, dict): obj = obj[k] - else: - if isinstance(obj, (LayerNorm, nn.LayerNorm)) and k in ["gamma", "beta"]: - k = "weight" if k == "gamma" else "bias" - elif k in ["weight_g", "weight_v"]: - parent, skip = obj, True - if k == "weight_g": weight_g = v - else: weight_v = v - if not skip: obj = getattr(obj, k) - if weight_g is not None and weight_v is not None: - setattr(obj, "weight_g", weight_g.numpy()) - setattr(obj, "weight_v", weight_v.numpy()) - obj, v = getattr(parent, "weight"), weight_norm(weight_v, weight_g, 0) - weight_g, weight_v, parent, skip = None, None, None, False - if not skip and obj.shape == v.shape: obj.assign(v.to(obj.device)) - elif not skip: logging.error(f"MISMATCH SHAPE IN {key}, {obj.shape} {v.shape}") - except Exception as e: raise e - logging.info(f"Loaded checkpoint '{checkpoint_path}' (iteration {iteration}) in {time.time() - start_time:.4f}s") - return model, optimizer, learning_rate, iteration - -# Used for cleaning input text and mapping to symbols -class TextMapper: # Based on https://github.com/keithito/tacotron - def __init__(self, symbols, apply_cleaners=True): - self.apply_cleaners, self.symbols, self._inflect = apply_cleaners, symbols, None - self._symbol_to_id, _id_to_symbol = {s: i for i, s in enumerate(symbols)}, {i: s for i, s in enumerate(symbols)} - self._whitespace_re, self._abbreviations = re.compile(r'\s+'), [(re.compile('\\b%s\\.' % x[0], re.IGNORECASE), x[1]) for x in [('mrs', 'misess'), ('mr', 'mister'), ('dr', 'doctor'), ('st', 'saint'), ('co', 'company'), ('jr', 'junior'), ('maj', 'major'), ('gen', 'general'), ('drs', 'doctors'), ('rev', 'reverend'), ('lt', 'lieutenant'), ('hon', 'honorable'), ('sgt', 'sergeant'), ('capt', 'captain'), ('esq', 'esquire'), ('ltd', 'limited'), ('col', 'colonel'), ('ft', 'fort'), ]] - self.phonemizer = EspeakBackend( - language="en-us", punctuation_marks=Punctuation.default_marks(), preserve_punctuation=True, with_stress=True, - ) - def text_to_sequence(self, text, cleaner_names): - if self.apply_cleaners: - for name in cleaner_names: - cleaner = getattr(self, name) - if not cleaner: raise ModuleNotFoundError('Unknown cleaner: %s' % name) - text = cleaner(text) - else: text = text.strip() - return [self._symbol_to_id[symbol] for symbol in text] - def get_text(self, text, add_blank=False, cleaners=('english_cleaners2',)): - text_norm = self.text_to_sequence(text, cleaners) - return Tensor(self.intersperse(text_norm, 0) if add_blank else text_norm, dtype=dtypes.int64) - def intersperse(self, lst, item): - (result := [item] * (len(lst) * 2 + 1))[1::2] = lst - return result - def phonemize(self, text, strip=True): return _phonemize(self.phonemizer, text, default_separator, strip, 1, False, False) - def filter_oov(self, text): return "".join(list(filter(lambda x: x in self._symbol_to_id, text))) - def base_english_cleaners(self, text): return self.collapse_whitespace(self.phonemize(self.expand_abbreviations(unidecode(text.lower())))) - def english_cleaners2(self, text): return self.base_english_cleaners(text) - def transliteration_cleaners(self, text): return self.collapse_whitespace(unidecode(text.lower())) - def cjke_cleaners(self, text): return re.sub(r'([^\.,!\?\-…~])$', r'\1.', re.sub(r'\s+$', '', self.english_to_ipa2(text).replace('ɑ', 'a').replace('ɔ', 'o').replace('ɛ', 'e').replace('ɪ', 'i').replace('ʊ', 'u'))) - def cjke_cleaners2(self, text): return re.sub(r'([^\.,!\?\-…~])$', r'\1.', re.sub(r'\s+$', '', self.english_to_ipa2(text))) - def cjks_cleaners(self, text): return re.sub(r'([^\.,!\?\-…~])$', r'\1.', re.sub(r'\s+$', '', self.english_to_lazy_ipa(text))) - def english_to_ipa2(self, text): - _ipa_to_ipa2 = [(re.compile('%s' % x[0]), x[1]) for x in [ ('r', 'ɹ'), ('ʤ', 'dʒ'), ('ʧ', 'tʃ')]] - return reduce(lambda t, rx: re.sub(rx[0], rx[1], t), _ipa_to_ipa2, self.mark_dark_l(self.english_to_ipa(text))).replace('...', '…') - def mark_dark_l(self, text): return re.sub(r'l([^aeiouæɑɔəɛɪʊ ]*(?: |$))', lambda x: 'ɫ' + x.group(1), text) - def english_to_ipa(self, text): - import eng_to_ipa as ipa - return self.collapse_whitespace(ipa.convert(self.normalize_numbers(self.expand_abbreviations(unidecode(text).lower())))) - def english_to_lazy_ipa(self, text): - _lazy_ipa = [(re.compile('%s' % x[0]), x[1]) for x in [('r', 'ɹ'), ('æ', 'e'), ('ɑ', 'a'), ('ɔ', 'o'), ('ð', 'z'), ('θ', 's'), ('ɛ', 'e'), ('ɪ', 'i'), ('ʊ', 'u'), ('ʒ', 'ʥ'), ('ʤ', 'ʥ'), ('ˈ', '↓')]] - return reduce(lambda t, rx: re.sub(rx[0], rx[1], t), _lazy_ipa, self.english_to_ipa(text)) - def expand_abbreviations(self, text): return reduce(lambda t, abbr: re.sub(abbr[0], abbr[1], t), self._abbreviations, text) - def collapse_whitespace(self, text): return re.sub(self._whitespace_re, ' ', text) - def normalize_numbers(self, text): - import inflect - self._inflect = inflect.engine() - text = re.sub(re.compile(r'([0-9][0-9\,]+[0-9])'), self._remove_commas, text) - text = re.sub(re.compile(r'£([0-9\,]*[0-9]+)'), r'\1 pounds', text) - text = re.sub(re.compile(r'\$([0-9\.\,]*[0-9]+)'), self._expand_dollars, text) - text = re.sub(re.compile(r'([0-9]+\.[0-9]+)'), self._expand_decimal_point, text) - text = re.sub(re.compile(r'[0-9]+(st|nd|rd|th)'), self._expand_ordinal, text) - text = re.sub(re.compile(r'[0-9]+'), self._expand_number, text) - return text - def _remove_commas(self, m): return m.group(1).replace(',', '') # george won't like this - def _expand_dollars(self, m): - match = m.group(1) - parts = match.split('.') - if len(parts) > 2: return match + ' dollars' # Unexpected format - dollars, cents = int(parts[0]) if parts[0] else 0, int(parts[1]) if len(parts) > 1 and parts[1] else 0 - if dollars and cents: return '%s %s, %s %s' % (dollars, 'dollar' if dollars == 1 else 'dollars', cents, 'cent' if cents == 1 else 'cents') - if dollars: return '%s %s' % (dollars, 'dollar' if dollars == 1 else 'dollars') - if cents: return '%s %s' % (cents, 'cent' if cents == 1 else 'cents') - return 'zero dollars' - def _expand_decimal_point(self, m): return m.group(1).replace('.', ' point ') - def _expand_ordinal(self, m): return self._inflect.number_to_words(m.group(0)) - def _expand_number(self, _inflect, m): - num = int(m.group(0)) - if 1000 < num < 3000: - if num == 2000: return 'two thousand' - if 2000 < num < 2010: return 'two thousand ' + self._inflect.number_to_words(num % 100) - if num % 100 == 0: return self._inflect.number_to_words(num // 100) + ' hundred' - return _inflect.number_to_words(num, andword='', zero='oh', group=2).replace(', ', ' ') - return self._inflect.number_to_words(num, andword='') - -######################################################################################### -# PAPER: https://arxiv.org/abs/2106.06103 -# CODE: https://github.com/jaywalnut310/vits/tree/main -######################################################################################### -# INSTALLATION: this is based on default config, dependencies are for preprocessing. -# vctk, ljs | pip3 install unidecode phonemizer | phonemizer requires [eSpeak](https://espeak.sourceforge.net) backend to be installed on your system -# mmts-tts | pip3 install unidecode | -# uma_trilingual, cjks, voistock | pip3 install unidecode inflect eng_to_ipa | -######################################################################################### -# Some good speakers to try out, there may be much better ones, I only tried out a few: -# male vctk 1 | --model_to_use vctk --speaker_id 2 -# male vctk 2 | --model_to_use vctk --speaker_id 6 -# anime lady 1 | --model_to_use uma_trilingual --speaker_id 36 -# anime lady 2 | --model_to_use uma_trilingual --speaker_id 121 -######################################################################################### -VITS_PATH = Path(__file__).parents[1] / "weights/VITS/" -MODELS = { # config_url, weights_url - "ljs": ("https://raw.githubusercontent.com/jaywalnut310/vits/main/configs/ljs_base.json", "https://drive.google.com/uc?export=download&id=1q86w74Ygw2hNzYP9cWkeClGT5X25PvBT&confirm=t"), - "vctk": ("https://huggingface.co/csukuangfj/vits-vctk/resolve/main/vctk_base.json", "https://huggingface.co/csukuangfj/vits-vctk/resolve/main/pretrained_vctk.pth"), - "mmts-tts": ("https://huggingface.co/facebook/mms-tts/raw/main/full_models/eng/config.json", "https://huggingface.co/facebook/mms-tts/resolve/main/full_models/eng/G_100000.pth"), - "uma_trilingual": ("https://huggingface.co/spaces/Plachta/VITS-Umamusume-voice-synthesizer/raw/main/configs/uma_trilingual.json", "https://huggingface.co/spaces/Plachta/VITS-Umamusume-voice-synthesizer/resolve/main/pretrained_models/G_trilingual.pth"), - "cjks": ("https://huggingface.co/spaces/skytnt/moe-tts/resolve/main/saved_model/14/config.json", "https://huggingface.co/spaces/skytnt/moe-tts/resolve/main/saved_model/14/model.pth"), - "voistock": ("https://huggingface.co/spaces/skytnt/moe-tts/resolve/main/saved_model/15/config.json", "https://huggingface.co/spaces/skytnt/moe-tts/resolve/main/saved_model/15/model.pth"), -} -Y_LENGTH_ESTIMATE_SCALARS = {"ljs": 2.8, "vctk": 1.74, "mmts-tts": 1.9, "uma_trilingual": 2.3, "cjks": 3.3, "voistock": 3.1} -if __name__ == '__main__': - logging.basicConfig(stream=sys.stdout, level=logging.DEBUG) - parser = argparse.ArgumentParser() - parser.add_argument("--model_to_use", default="vctk", help="Specify the model to use. Default is 'vctk'.") - parser.add_argument("--speaker_id", type=int, default=6, help="Specify the speaker ID. Default is 6.") - parser.add_argument("--out_path", default=None, help="Specify the full output path. Overrides the --out_dir and --name parameter.") - parser.add_argument("--out_dir", default=str(Path(__file__).parents[1] / "temp"), help="Specify the output path.") - parser.add_argument("--base_name", default="test", help="Specify the base of the output file name. Default is 'test'.") - parser.add_argument("--text_to_synthesize", default="""Hello person. If the code you are contributing isn't some of the highest quality code you've written in your life, either put in the effort to make it great, or don't bother.""", help="Specify the text to synthesize. Default is a greeting message.") - parser.add_argument("--noise_scale", type=float, default=0.667, help="Specify the noise scale. Default is 0.667.") - parser.add_argument("--noise_scale_w", type=float, default=0.8, help="Specify the noise scale w. Default is 0.8.") - parser.add_argument("--length_scale", type=float, default=1, help="Specify the length scale. Default is 1.") - parser.add_argument("--seed", type=int, default=1337, help="Specify the seed (set to None if no seed). Default is 1337.") - parser.add_argument("--num_channels", type=int, default=1, help="Specify the number of audio output channels. Default is 1.") - parser.add_argument("--sample_width", type=int, default=2, help="Specify the number of bytes per sample, adjust if necessary. Default is 2.") - parser.add_argument("--emotion_path", type=str, default=None, help="Specify the path to emotion reference.") - parser.add_argument("--estimate_max_y_length", type=str, default=False, help="If true, overestimate the output length and then trim it to the correct length, to prevent premature realization, much more performant for larger inputs, for smaller inputs not so much. Default is False.") - args = parser.parse_args() - - model_config = MODELS[args.model_to_use] - - # Load the hyperparameters from the config file. - hps = get_hparams_from_file(fetch(model_config[0])) - - # If model has multiple speakers, validate speaker id and retrieve name if available. - model_has_multiple_speakers = hps.data.n_speakers > 0 - if model_has_multiple_speakers: - logging.info(f"Model has {hps.data.n_speakers} speakers") - if args.speaker_id >= hps.data.n_speakers: raise ValueError(f"Speaker ID {args.speaker_id} is invalid for this model.") - speaker_name = "?" - if hps.__contains__("speakers"): # maps speaker ids to names - speakers = hps.speakers - if isinstance(speakers, List): speakers = {speaker: i for i, speaker in enumerate(speakers)} - speaker_name = next((key for key, value in speakers.items() if value == args.speaker_id), None) - logging.info(f"You selected speaker {args.speaker_id} (name: {speaker_name})") - - # Load emotions if any. TODO: find an english model with emotions, this is untested atm. - emotion_embedding = None - if args.emotion_path is not None: - if args.emotion_path.endswith(".npy"): emotion_embedding = Tensor(np.load(args.emotion_path), dtype=dtypes.int64).unsqueeze(0) - else: raise ValueError("Emotion path must be a .npy file.") - - # Load symbols, instantiate TextMapper and clean the text. - if hps.__contains__("symbols"): symbols = hps.symbols - elif args.model_to_use == "mmts-tts": symbols = [x.replace("\n", "") for x in fetch("https://huggingface.co/facebook/mms-tts/raw/main/full_models/eng/vocab.txt").open(encoding="utf-8").readlines()] - else: symbols = ['_'] + list(';:,.!?¡¿—…"«»“” ') + list('ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz') + list("ɑɐɒæɓʙβɔɕçɗɖðʤəɘɚɛɜɝɞɟʄɡɠɢʛɦɧħɥʜɨɪʝɭɬɫɮʟɱɯɰŋɳɲɴøɵɸθœɶʘɹɺɾɻʀʁɽʂʃʈʧʉʊʋⱱʌɣɤʍχʎʏʑʐʒʔʡʕʢǀǁǂǃˈˌːˑʼʴʰʱʲʷˠˤ˞↓↑→↗↘'̩'ᵻ") - text_mapper = TextMapper(apply_cleaners=True, symbols=symbols) - - # Load the model. - if args.seed is not None: - Tensor.manual_seed(args.seed) - np.random.seed(args.seed) - net_g = load_model(text_mapper.symbols, hps, model_config) - logging.debug(f"Loaded model with hps: {hps}") - - # Convert the input text to a tensor. - text_to_synthesize = args.text_to_synthesize - if args.model_to_use == "mmts-tts": text_to_synthesize = text_mapper.filter_oov(text_to_synthesize.lower()) - stn_tst = text_mapper.get_text(text_to_synthesize, hps.data.add_blank, hps.data.text_cleaners) - logging.debug(f"Converted input text to tensor \"{text_to_synthesize}\" -> Tensor({stn_tst.shape}): {stn_tst.numpy()}") - x_tst, x_tst_lengths = stn_tst.unsqueeze(0), Tensor([stn_tst.shape[0]], dtype=dtypes.int64) - sid = Tensor([args.speaker_id], dtype=dtypes.int64) if model_has_multiple_speakers else None - - # Perform inference. - start_time = time.time() - audio_tensor = net_g.infer(x_tst, x_tst_lengths, sid, args.noise_scale, args.length_scale, args.noise_scale_w, emotion_embedding=emotion_embedding, - max_y_length_estimate_scale=Y_LENGTH_ESTIMATE_SCALARS[args.model_to_use] if args.estimate_max_y_length else None)[0, 0].realize() - logging.info(f"Inference took {(time.time() - start_time):.2f}s") - - # Save the audio output. - audio_data = (np.clip(audio_tensor.numpy(), -1.0, 1.0) * 32767).astype(np.int16) - out_path = Path(args.out_path or Path(args.out_dir)/f"{args.model_to_use}{f'_sid_{args.speaker_id}' if model_has_multiple_speakers else ''}_{args.base_name}.wav") - out_path.parent.mkdir(parents=True, exist_ok=True) - with wave.open(str(out_path), 'wb') as wav_file: - wav_file.setnchannels(args.num_channels) - wav_file.setsampwidth(args.sample_width) - wav_file.setframerate(hps.data.sampling_rate) - wav_file.setnframes(len(audio_data)) - wav_file.writeframes(audio_data.tobytes()) - logging.info(f"Saved audio output to {out_path}") diff --git a/tinygrad/examples/webgpu/efficientnet/index.html b/tinygrad/examples/webgpu/efficientnet/index.html deleted file mode 100644 index e03ed349..00000000 --- a/tinygrad/examples/webgpu/efficientnet/index.html +++ /dev/null @@ -1,124 +0,0 @@ - - - - -tinygrad has WebGPU - - - -

WebGPU tinygrad EfficientNet!

-
- - -
-
- - -
-
result will go here
-
-
- - - \ No newline at end of file diff --git a/tinygrad/examples/webgpu/stable_diffusion/compile.py b/tinygrad/examples/webgpu/stable_diffusion/compile.py deleted file mode 100644 index 6f47a5b3..00000000 --- a/tinygrad/examples/webgpu/stable_diffusion/compile.py +++ /dev/null @@ -1,237 +0,0 @@ -import os -from extra.export_model import compile_net, jit_model, dtype_to_js_type -from extra.f16_decompress import u32_to_f16 -from examples.stable_diffusion import StableDiffusion -from tinygrad.nn.state import get_state_dict, safe_save, safe_load_metadata, torch_load, load_state_dict -from tinygrad.tensor import Tensor -from tinygrad import Device, dtypes -from tinygrad.helpers import fetch -from typing import NamedTuple, Any, List -import requests -import argparse -import numpy as np - -def convert_f32_to_f16(input_file, output_file): - with open(input_file, 'rb') as f: - metadata_length_bytes = f.read(8) - metadata_length = int.from_bytes(metadata_length_bytes, byteorder='little', signed=False) - metadata_json_bytes = f.read(metadata_length) - float32_values = np.fromfile(f, dtype=np.float32) - - first_text_model_offset = 3772703308 - num_elements = int((first_text_model_offset)/4) - front_float16_values = float32_values[:num_elements].astype(np.float16) - rest_float32_values = float32_values[num_elements:] - - with open(output_file, 'wb') as f: - f.write(metadata_length_bytes) - f.write(metadata_json_bytes) - front_float16_values.tofile(f) - rest_float32_values.tofile(f) - -def split_safetensor(fn): - _, data_start, metadata = safe_load_metadata(fn) - text_model_offset = 3772703308 - chunk_size = 536870912 - - for k in metadata: - # safetensor is in fp16, except for text moel - if (metadata[k]["data_offsets"][0] < text_model_offset): - metadata[k]["data_offsets"][0] = int(metadata[k]["data_offsets"][0]/2) - metadata[k]["data_offsets"][1] = int(metadata[k]["data_offsets"][1]/2) - - last_offset = 0 - part_end_offsets = [] - - for k in metadata: - offset = metadata[k]['data_offsets'][0] - - if offset == text_model_offset: - break - - part_offset = offset - last_offset - - if (part_offset >= chunk_size): - part_end_offsets.append(data_start+offset) - last_offset = offset - - text_model_start = int(text_model_offset/2) - net_bytes = bytes(open(fn, 'rb').read()) - part_end_offsets.append(text_model_start+data_start) - cur_pos = 0 - - for i, end_pos in enumerate(part_end_offsets): - with open(os.path.join(os.path.dirname(__file__), f'./net_part{i}.safetensors'), "wb+") as f: - f.write(net_bytes[cur_pos:end_pos]) - cur_pos = end_pos - - with open(os.path.join(os.path.dirname(__file__), f'./net_textmodel.safetensors'), "wb+") as f: - f.write(net_bytes[text_model_start+data_start:]) - - return part_end_offsets - -def fetch_dep(file, url): - with open(file, "w", encoding="utf-8") as f: - f.write(requests.get(url).text.replace("https://huggingface.co/wpmed/tinygrad-sd-f16/raw/main/bpe_simple_vocab_16e6.mjs", "./bpe_simple_vocab_16e6.mjs")) - -if __name__ == "__main__": - fetch_dep(os.path.join(os.path.dirname(__file__), "clip_tokenizer.js"), "https://huggingface.co/wpmed/tinygrad-sd-f16/raw/main/clip_tokenizer.js") - fetch_dep(os.path.join(os.path.dirname(__file__), "bpe_simple_vocab_16e6.mjs"), "https://huggingface.co/wpmed/tinygrad-sd-f16/raw/main/bpe_simple_vocab_16e6.mjs") - parser = argparse.ArgumentParser(description='Run Stable Diffusion', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--remoteweights', action='store_true', help="Use safetensors from Huggingface, or from local") - args = parser.parse_args() - Device.DEFAULT = "WEBGPU" - - model = StableDiffusion() - - # load in weights - load_state_dict(model, torch_load(fetch('https://huggingface.co/CompVis/stable-diffusion-v-1-4-original/resolve/main/sd-v1-4.ckpt', 'sd-v1-4.ckpt'))['state_dict'], strict=False) - - class Step(NamedTuple): - name: str = "" - input: List[Tensor] = [] - forward: Any = None - - sub_steps = [ - Step(name = "textModel", input = [Tensor.randn(1, 77)], forward = model.cond_stage_model.transformer.text_model), - Step(name = "diffusor", input = [Tensor.randn(1, 77, 768), Tensor.randn(1, 77, 768), Tensor.randn(1,4,64,64), Tensor.rand(1), Tensor.randn(1), Tensor.randn(1), Tensor.randn(1)], forward = model), - Step(name = "decoder", input = [Tensor.randn(1,4,64,64)], forward = model.decode), - Step(name = "f16tof32", input = [Tensor.randn(2097120, dtype=dtypes.uint32)], forward = u32_to_f16) - ] - - prg = "" - - def fixup_code(code, key): - code = code.replace(key, 'main')\ - .replace("var INFINITY : f32;\n", "fn inf(a: f32) -> f32 { return a/0.0; }\n")\ - .replace("@group(0) @binding(0)", "")\ - .replace("INFINITY", "inf(1.0)") - - for i in range(1,9): code = code.replace(f"binding({i})", f"binding({i-1})") - return code - - def compile_step(model, step: Step): - run, special_names = jit_model(step, *step.input) - functions, statements, bufs, _ = compile_net(run, special_names) - state = get_state_dict(model) - weights = {id(x.uop.base.realized): name for name, x in state.items()} - kernel_code = '\n\n'.join([f"const {key} = `{fixup_code(code, key)}`;" for key, code in functions.items()]) - kernel_names = ', '.join([name for (name, _, _, _) in statements]) - input_names = [name for _,name in special_names.items() if "input" in name] - output_names = [name for _,name in special_names.items() if "output" in name] - input_buf_types = [dtype_to_js_type(bufs[inp_name][1]) for inp_name in input_names] - output_buf_types = [dtype_to_js_type(bufs[out_name][1]) for out_name in output_names] - kernel_calls = '\n '.join([f"addComputePass(device, commandEncoder, piplines[{i}], [{', '.join(args)}], {global_size});" for i, (_name, args, global_size, _local_size) in enumerate(statements) ]) - exported_bufs = '\n '.join([f"const {name} = " + (f"createEmptyBuf(device, {size});" if _key not in weights else f"createWeightBuf(device, {size}, getTensorBuffer(safetensor, metadata['{weights[_key]}'], '{weights[_key]}'))") + ";" for name,(size,dtype,_key) in bufs.items()]) - gpu_write_bufs = '\n '.join([f"const gpuWriteBuffer{i} = device.createBuffer({{size:input{i}.size, usage: GPUBufferUsage.COPY_SRC | GPUBufferUsage.MAP_WRITE }});" for i,(_,value) in enumerate(special_names.items()) if "output" not in value]) - input_writer = '\n '.join([f"await gpuWriteBuffer{i}.mapAsync(GPUMapMode.WRITE);\n new {input_buf_types[i]}(gpuWriteBuffer{i}.getMappedRange()).set(" + f'data{i});' + f"\n gpuWriteBuffer{i}.unmap();\ncommandEncoder.copyBufferToBuffer(gpuWriteBuffer{i}, 0, input{i}, 0, gpuWriteBuffer{i}.size);" for i,_ in enumerate(input_names)]) - return f"""\n var {step.name} = function() {{ - - {kernel_code} - - return {{ - "setup": async (device, safetensor) => {{ - const metadata = safetensor ? getTensorMetadata(safetensor[0]) : null; - - {exported_bufs} - - {gpu_write_bufs} - const gpuReadBuffer = device.createBuffer({{ size: output0.size, usage: GPUBufferUsage.COPY_DST | GPUBufferUsage.MAP_READ }}); - - const kernels = [{kernel_names}]; - const piplines = await Promise.all(kernels.map(name => device.createComputePipelineAsync({{layout: "auto", compute: {{ module: device.createShaderModule({{ code: name }}), entryPoint: "main" }}}}))); - - return async ({",".join([f'data{i}' for i,(k,v) in enumerate(special_names.items()) if v != "output0"])}) => {{ - const commandEncoder = device.createCommandEncoder(); - - {input_writer} - - {kernel_calls} - commandEncoder.copyBufferToBuffer(output0, 0, gpuReadBuffer, 0, output0.size); - const gpuCommands = commandEncoder.finish(); - device.queue.submit([gpuCommands]); - - await gpuReadBuffer.mapAsync(GPUMapMode.READ); - const resultBuffer = new {output_buf_types[0]}(gpuReadBuffer.size/{bufs[output_names[0]][1].itemsize}); - resultBuffer.set(new {output_buf_types[0]}(gpuReadBuffer.getMappedRange())); - gpuReadBuffer.unmap(); - return resultBuffer; - }} - }} - }} - }} - """ - - for step in sub_steps: - print(f'Executing step={step.name}') - prg += compile_step(model, step) - - if step.name == "diffusor": - if args.remoteweights: - base_url = "https://huggingface.co/wpmed/stable-diffusion-f16-new/resolve/main" - else: - state = get_state_dict(model) - safe_save(state, os.path.join(os.path.dirname(__file__), "net.safetensors")) - convert_f32_to_f16(os.path.join(os.path.dirname(__file__), "./net.safetensors"), os.path.join(os.path.dirname(__file__), "./net_conv.safetensors")) - split_safetensor(os.path.join(os.path.dirname(__file__), "./net_conv.safetensors")) - os.remove(os.path.join(os.path.dirname(__file__), "net.safetensors")) - os.remove(os.path.join(os.path.dirname(__file__), "net_conv.safetensors")) - base_url = "." - - prekernel = f""" - window.MODEL_BASE_URL= "{base_url}"; - const getTensorMetadata = (safetensorBuffer) => {{ - const metadataLength = Number(new DataView(safetensorBuffer.buffer).getBigUint64(0, true)); - const metadata = JSON.parse(new TextDecoder("utf8").decode(safetensorBuffer.subarray(8, 8 + metadataLength))); - return Object.fromEntries(Object.entries(metadata).filter(([k, v]) => k !== "__metadata__").map(([k, v]) => [k, {{...v, data_offsets: v.data_offsets.map(x => 8 + metadataLength + x)}}])); - }}; - - const getTensorBuffer = (safetensorParts, tensorMetadata, key) => {{ - let selectedPart = 0; - let counter = 0; - let partStartOffsets = [1131408336, 2227518416, 3308987856, 4265298864]; - let correctedOffsets = tensorMetadata.data_offsets; - let prev_offset = 0; - - for (let start of partStartOffsets) {{ - prev_offset = (counter == 0) ? 0 : partStartOffsets[counter-1]; - - if (tensorMetadata.data_offsets[0] < start) {{ - selectedPart = counter; - correctedOffsets = [correctedOffsets[0]-prev_offset, correctedOffsets[1]-prev_offset]; - break; - }} - - counter++; - }} - - return safetensorParts[selectedPart].subarray(...correctedOffsets); - }} - - const getWeight = (safetensors, key) => {{ - let uint8Data = getTensorBuffer(safetensors, getTensorMetadata(safetensors[0])[key], key); - return new Float32Array(uint8Data.buffer, uint8Data.byteOffset, uint8Data.byteLength / Float32Array.BYTES_PER_ELEMENT); - }} - - const createEmptyBuf = (device, size) => {{ - return device.createBuffer({{size, usage: GPUBufferUsage.STORAGE | GPUBufferUsage.COPY_SRC | GPUBufferUsage.COPY_DST }}); - }}; - - const createWeightBuf = (device, size, data) => {{ - const buf = device.createBuffer({{ mappedAtCreation: true, size, usage: GPUBufferUsage.STORAGE }}); - new Uint8Array(buf.getMappedRange()).set(data); - buf.unmap(); - return buf; - }}; - - const addComputePass = (device, commandEncoder, pipeline, bufs, workgroup) => {{ - const bindGroup = device.createBindGroup({{layout: pipeline.getBindGroupLayout(0), entries: bufs.map((buffer, index) => ({{ binding: index, resource: {{ buffer }} }}))}}); - const passEncoder = commandEncoder.beginComputePass(); - passEncoder.setPipeline(pipeline); - passEncoder.setBindGroup(0, bindGroup); - passEncoder.dispatchWorkgroups(...workgroup); - passEncoder.end(); - }};""" - - with open(os.path.join(os.path.dirname(__file__), "net.js"), "w") as text_file: - text_file.write(prekernel + prg) diff --git a/tinygrad/examples/webgpu/stable_diffusion/index.html b/tinygrad/examples/webgpu/stable_diffusion/index.html deleted file mode 100644 index c70ce5cc..00000000 --- a/tinygrad/examples/webgpu/stable_diffusion/index.html +++ /dev/null @@ -1,632 +0,0 @@ - - - - - - - tinygrad has WebGPU - - - - - - -

WebGPU is not supported in this browser

-

StableDiffusion powered by tinygrad

- - GitHub Logo - - -
-
- - - - - - - -
- -
- Downloading model - - -
- - - - -
- - - - - - diff --git a/tinygrad/examples/webgpu/yolov8/compile.py b/tinygrad/examples/webgpu/yolov8/compile.py deleted file mode 100644 index 0e88557f..00000000 --- a/tinygrad/examples/webgpu/yolov8/compile.py +++ /dev/null @@ -1,19 +0,0 @@ -from pathlib import Path -from examples.yolov8 import YOLOv8, get_weights_location -from tinygrad.tensor import Tensor -from tinygrad.nn.state import safe_save -from extra.export_model import export_model -from tinygrad.device import Device -from tinygrad.nn.state import safe_load, load_state_dict - -if __name__ == "__main__": - Device.DEFAULT = "WEBGPU" - yolo_variant = 'n' - yolo_infer = YOLOv8(w=0.25, r=2.0, d=0.33, num_classes=80) - state_dict = safe_load(get_weights_location(yolo_variant)) - load_state_dict(yolo_infer, state_dict) - prg, inp_sizes, out_sizes, state = export_model(yolo_infer, Device.DEFAULT.lower(), Tensor.randn(1,3,640,640), model_name="yolov8") - dirname = Path(__file__).parent - safe_save(state, (dirname / "net.safetensors").as_posix()) - with open(dirname / f"net.js", "w") as text_file: - text_file.write(prg) diff --git a/tinygrad/examples/webgpu/yolov8/index.html b/tinygrad/examples/webgpu/yolov8/index.html deleted file mode 100644 index 6a98d5e1..00000000 --- a/tinygrad/examples/webgpu/yolov8/index.html +++ /dev/null @@ -1,284 +0,0 @@ - - - - - - YOLOv8 tinygrad WebGPU - - - - -

YOLOv8 tinygrad WebGPU

- -
- - -
- -
-

Loading model

- -
-
- - - diff --git a/tinygrad/examples/whisper.py b/tinygrad/examples/whisper.py deleted file mode 100644 index dc2832a4..00000000 --- a/tinygrad/examples/whisper.py +++ /dev/null @@ -1,330 +0,0 @@ -# thanks to https://github.com/openai/whisper for a good chunk of MIT licensed code - -import sys, base64, multiprocessing, itertools, collections -from typing import Optional, Union, Literal, List - -from tinygrad import Tensor, TinyJit, Variable, nn -from tinygrad.nn.state import torch_load, load_state_dict -from tinygrad.helpers import getenv, DEBUG, fetch - -import numpy as np -import librosa - -class MultiHeadAttention: - def __init__(self, n_state, n_head, kv_caching: Literal['cross', 'self']=None, max_self_attn_cache_len=None): - self.n_head = n_head - self.query = nn.Linear(n_state, n_state) - self.key = nn.Linear(n_state, n_state, bias=False) - self.value = nn.Linear(n_state, n_state) - self.out = nn.Linear(n_state, n_state) - - self.kv_caching = kv_caching - self.max_self_attn_cache_len = max_self_attn_cache_len - - def __call__(self, x:Tensor, xa:Optional[Tensor]=None, mask:Optional[Tensor]=None, len: Union[Variable,int]=None): - if self.kv_caching == 'cross': - if xa is not None: - k, v = self.key(xa), self.value(xa) - if not hasattr(self, 'cache_k'): - self.cache_k, self.cache_v = k, v - else: - self.cache_k.assign(k).realize() - self.cache_v.assign(v).realize() - else: - k, v = self.cache_k, self.cache_v - else: - k, v = self.key(x), self.value(x) - if self.kv_caching == 'self': - if not hasattr(self, 'cache_k'): - self.cache_k = Tensor.zeros(x.shape[0], self.max_self_attn_cache_len, x.shape[2]) - self.cache_v = Tensor.zeros(x.shape[0], self.max_self_attn_cache_len, x.shape[2]) - k = self.cache_k.shrink((None, (0, len), None)).cat(k, dim=1) - v = self.cache_v.shrink((None, (0, len), None)).cat(v, dim=1) - padding = self.max_self_attn_cache_len-len-x.shape[1] - self.cache_k.assign(k.pad((None, (0, padding), None)).contiguous()).realize() - self.cache_v.assign(v.pad((None, (0, padding), None)).contiguous()).realize() - - q = self.query(x) - n_ctx = q.shape[1] - assert(q.shape[-1] == k.shape[-1] == v.shape[-1]) - head_dim = q.shape[-1] // self.n_head - q = q.reshape(*q.shape[:2], self.n_head, head_dim).permute(0, 2, 1, 3) - k = k.reshape(*k.shape[:2], self.n_head, head_dim).permute(0, 2, 1, 3) - v = v.reshape(*v.shape[:2], self.n_head, head_dim).permute(0, 2, 1, 3) - attn = Tensor.scaled_dot_product_attention(q, k, v, mask[:n_ctx,:n_ctx] if mask is not None else None) - wv = attn.permute(0, 2, 1, 3).flatten(start_dim=2) - return self.out(wv) - - -class ResidualAttentionBlock: - def __init__(self, n_state, n_head, is_decoder_block=False, max_self_attn_cache_len=None): - self.attn = MultiHeadAttention(n_state, n_head, kv_caching='self' if is_decoder_block else None, max_self_attn_cache_len=max_self_attn_cache_len) - self.attn_ln = nn.LayerNorm(n_state) - - self.cross_attn = MultiHeadAttention(n_state, n_head, kv_caching='cross') if is_decoder_block else None - self.cross_attn_ln = nn.LayerNorm(n_state) if is_decoder_block else None - - self.mlp = [nn.Linear(n_state, n_state*4), Tensor.gelu, nn.Linear(n_state*4, n_state)] - self.mlp_ln = nn.LayerNorm(n_state) - - def __call__(self, x, xa=None, mask=None, len: Union[Variable, int]=None): - x = x + self.attn(self.attn_ln(x), mask=mask, len=len) - if self.cross_attn: x = x + self.cross_attn(self.cross_attn_ln(x), xa) - x = x + self.mlp_ln(x).sequential(self.mlp) - return x.realize() - -class AudioEncoder: - def __init__(self, n_mels, n_audio_ctx, n_audio_state, n_audio_head, n_audio_layer, **_): - self.conv1 = nn.Conv1d(n_mels, n_audio_state, kernel_size=3, padding=1) - self.conv2 = nn.Conv1d(n_audio_state, n_audio_state, kernel_size=3, stride=2, padding=1) - self.blocks = [ResidualAttentionBlock(n_audio_state, n_audio_head) for _ in range(n_audio_layer)] - self.ln_post = nn.LayerNorm(n_audio_state) - self.positional_embedding = Tensor.empty(n_audio_ctx, n_audio_state) - self.encode = TinyJit(self.__call__) - - def __call__(self, x): - x = self.conv1(x).gelu() - x = self.conv2(x).gelu() - x = x.permute(0, 2, 1) - x = x + self.positional_embedding[:x.shape[1]] - x = x.sequential(self.blocks) - x = self.ln_post(x) - return x.realize() - -class TextDecoder: - def __init__(self, n_vocab, n_text_ctx, n_text_state, n_text_head, n_text_layer, **_): - self.max_tokens_to_sample = n_text_ctx // 2 - self.max_self_attn_cache_len = n_text_ctx - - self.token_embedding = nn.Embedding(n_vocab, n_text_state) - self.positional_embedding = Tensor.empty(n_text_ctx, n_text_state) - self.blocks = [ResidualAttentionBlock(n_text_state, n_text_head, is_decoder_block=True, max_self_attn_cache_len=self.max_self_attn_cache_len) for _ in range(n_text_layer)] - self.ln = nn.LayerNorm(n_text_state) - self.mask = Tensor.full((n_text_ctx, n_text_ctx), -np.inf).triu(1).realize() - self.getjitted = collections.defaultdict(lambda: TinyJit(self.forward)) - - def __call__(self, x: Tensor, pos: int, encoded_audio: Tensor): - pos = Variable("self_attn_cache_len", 1, self.max_self_attn_cache_len-1).bind(pos) if pos else 0 - return self.getjitted[x.shape](x, pos, encoded_audio) - - def forward(self, x:Tensor, pos:Union[Variable, Literal[0]], encoded_audio:Tensor): - seqlen = x.shape[-1] - x = self.token_embedding(x) + self.positional_embedding.shrink(((pos, pos+seqlen), None, None)) - for block in self.blocks: x = block(x, xa=encoded_audio, mask=self.mask, len=pos) - return self.output_tok(x) - - def output_tok(self, x): - return (self.ln(x) @ self.token_embedding.weight.T).realize() - -class Whisper: - def __init__(self, dims, batch_size=1): - self.encoder = AudioEncoder(**dims) - self.decoder = TextDecoder(**dims) - self.is_multilingual = dims["n_vocab"] == 51865 - self.batch_size = batch_size - - -RATE = 16000 -SEGMENT_SECONDS=30 -SAMPLES_PER_SEGMENT = RATE * SEGMENT_SECONDS # 480000 -N_FFT = 400 -HOP_LENGTH = 160 -N_MELS = 80 -FRAMES_PER_SEGMENT = SAMPLES_PER_SEGMENT // HOP_LENGTH # 3000 - -def prep_audio(waveforms: List[np.ndarray], batch_size: int, truncate=False) -> np.ndarray: - """ - :param waveforms: A list of possibly variable length 16000Hz audio samples - :param batch_size: The batch_size associated with the Whisper model being used to transcribe the audio. - Used to prevent JIT mismatch errors since the encoder does not accept symbolic shapes - :param truncate: If true, truncates (or pads) audio to exactly 30s for a single encoder pass - :return: mel spectrogram of the given waveforms - """ - def pad_or_trim(arr, target_len): - curr_len = len(arr) - if curr_len == target_len: - return arr - elif curr_len < target_len: - return np.pad(arr, (0, target_len - curr_len), 'constant') - else: - return arr[:target_len] - - max_len = SAMPLES_PER_SEGMENT if truncate else max(len(wav) for wav in waveforms) - if (r := max_len % SAMPLES_PER_SEGMENT) > 0: max_len += SAMPLES_PER_SEGMENT - r - waveforms = np.array(list(map(lambda w: pad_or_trim(w, max_len), waveforms))) - assert waveforms.shape[0] <= batch_size - if waveforms.shape[0] < batch_size: - # we could have a symbolic batch_size dim instead of manually padding here if conv/layernorm supported symbolic shapes - waveforms = np.pad(waveforms, pad_width=((0, batch_size - waveforms.shape[0]), (0, 0))) - - stft = librosa.stft(waveforms, n_fft=N_FFT, hop_length=HOP_LENGTH, window='hann', dtype=np.csingle) - magnitudes = np.absolute(stft[..., :-1]) ** 2 - mel_spec = librosa.filters.mel(sr=RATE, n_fft=N_FFT, n_mels=N_MELS) @ magnitudes - - log_spec = np.log10(np.clip(mel_spec, 1e-10, None)) - log_spec = np.maximum(log_spec, log_spec.max((1,2), keepdims=True) - 8.0) - log_spec = (log_spec + 4.0) / 4.0 - - return log_spec - -LANGUAGES = { - "en": "english", "zh": "chinese", "de": "german", "es": "spanish", "ru": "russian", "ko": "korean", "fr": "french", "ja": "japanese", "pt": "portuguese", "tr": "turkish", - "pl": "polish", "ca": "catalan", "nl": "dutch", "ar": "arabic", "sv": "swedish", "it": "italian", "id": "indonesian", "hi": "hindi", "fi": "finnish", "vi": "vietnamese", - "he": "hebrew", "uk": "ukrainian", "el": "greek", "ms": "malay", "cs": "czech", "ro": "romanian", "da": "danish", "hu": "hungarian", "ta": "tamil", "no": "norwegian", - "th": "thai", "ur": "urdu", "hr": "croatian", "bg": "bulgarian", "lt": "lithuanian", "la": "latin", "mi": "maori", "ml": "malayalam", "cy": "welsh", "sk": "slovak", "te": "telugu", - "fa": "persian", "lv": "latvian", "bn": "bengali", "sr": "serbian", "az": "azerbaijani", "sl": "slovenian", "kn": "kannada", "et": "estonian", "mk": "macedonian", - "br": "breton", "eu": "basque", "is": "icelandic", "hy": "armenian", "ne": "nepali", "mn": "mongolian", "bs": "bosnian", "kk": "kazakh", "sq": "albanian", "sw": "swahili", - "gl": "galician", "mr": "marathi", "pa": "punjabi", "si": "sinhala", "km": "khmer", "sn": "shona", "yo": "yoruba", "so": "somali", "af": "afrikaans", "oc": "occitan", "ka": "georgian", - "be": "belarusian", "tg": "tajik", "sd": "sindhi", "gu": "gujarati", "am": "amharic", "yi": "yiddish", "lo": "lao", "uz": "uzbek", "fo": "faroese", "ht": "haitian creole", - "ps": "pashto", "tk": "turkmen", "nn": "nynorsk", "mt": "maltese", "sa": "sanskrit", "lb": "luxembourgish", "my": "myanmar", "bo": "tibetan", "tl": "tagalog", "mg": "malagasy", - "as": "assamese", "tt": "tatar", "haw": "hawaiian", "ln": "lingala", "ha": "hausa", "ba": "bashkir", "jw": "javanese", "su": "sundanese", -} - -def get_encoding(encoding_name): - with fetch(f"https://raw.githubusercontent.com/openai/whisper/main/whisper/assets/{encoding_name}.tiktoken").open() as f: - ranks = {base64.b64decode(token): int(rank) for token, rank in (line.split() for line in f if line)} - n_vocab = len(ranks) - specials = [ - "<|endoftext|>", - "<|startoftranscript|>", - *[f"<|{lang}|>" for lang in LANGUAGES.keys()], - "<|translate|>", - "<|transcribe|>", - "<|startoflm|>", - "<|startofprev|>", - "<|nospeech|>", - "<|notimestamps|>", - *[f"<|{i * 0.02:.2f}|>" for i in range(1501)], - ] - special_tokens = dict(zip(specials, itertools.count(n_vocab))) - n_vocab += len(specials) - import tiktoken - return tiktoken.Encoding( - name=encoding_name, - explicit_n_vocab=n_vocab, - pat_str=r"""'s|'t|'re|'ve|'m|'ll|'d| ?\p{L}+| ?\p{N}+| ?[^\s\p{L}\p{N}]+|\s+(?!\S)|\s+""", - mergeable_ranks=ranks, - special_tokens=special_tokens) - -MODEL_URLS = { - "tiny.en": "https://openaipublic.azureedge.net/main/whisper/models/d3dd57d32accea0b295c96e26691aa14d8822fac7d9d27d5dc00b4ca2826dd03/tiny.en.pt", - "tiny": "https://openaipublic.azureedge.net/main/whisper/models/65147644a518d12f04e32d6f3b26facc3f8dd46e5390956a9424a650c0ce22b9/tiny.pt", - "base.en": "https://openaipublic.azureedge.net/main/whisper/models/25a8566e1d0c1e2231d1c762132cd20e0f96a85d16145c3a00adf5d1ac670ead/base.en.pt", - "base": "https://openaipublic.azureedge.net/main/whisper/models/ed3a0b6b1c0edf879ad9b11b1af5a0e6ab5db9205f891f668f8b0e6c6326e34e/base.pt", - "small.en": "https://openaipublic.azureedge.net/main/whisper/models/f953ad0fd29cacd07d5a9eda5624af0f6bcf2258be67c92b79389873d91e0872/small.en.pt", - "small": "https://openaipublic.azureedge.net/main/whisper/models/9ecf779972d90ba49c06d968637d720dd632c55bbf19d441fb42bf17a411e794/small.pt", - "medium.en": "https://openaipublic.azureedge.net/main/whisper/models/d7440d1dc186f76616474e0ff0b3b6b879abc9d1a4926b7adfa41db2d497ab4f/medium.en.pt", - "medium": "https://openaipublic.azureedge.net/main/whisper/models/345ae4da62f9b3d59415adc60127b97c714f32e89e936602e85993674d08dcb1/medium.pt", - "large-v1": "https://openaipublic.azureedge.net/main/whisper/models/e4b87e7e0bf463eb8e6956e646f1e277e901512310def2c24bf0e11bd3c28e9a/large-v1.pt", - "large-v2": "https://openaipublic.azureedge.net/main/whisper/models/81f7c96c852ee8fc832187b0132e569d6c3065a3252ed18e56effd0b6a73e524/large-v2.pt", - "large": "https://openaipublic.azureedge.net/main/whisper/models/81f7c96c852ee8fc832187b0132e569d6c3065a3252ed18e56effd0b6a73e524/large-v2.pt", -} -def init_whisper(model_name="tiny.en", batch_size=1): - assert MODEL_URLS[model_name] is not None - - filename = fetch(MODEL_URLS[model_name]) - state = torch_load(filename) - model = Whisper(state['dims'], batch_size) - load_state_dict(model, state['model_state_dict'], strict=False) - enc = get_encoding("multilingual" if model.is_multilingual else "gpt2") - return model, enc - -def load_file_waveform(filename): - waveform, _ = librosa.load(filename, sr=RATE) - return waveform - -def transcribe_file(model, enc, filename): - return transcribe_waveform(model, enc, [load_file_waveform(filename)]) - -def transcribe_waveform(model: Whisper, enc, waveforms, truncate=False): - """ - Expects an array of shape (N,S) where N is the number waveforms to transcribe in parallel and S is number of 16000Hz samples - Returns the transcribed text if a single waveform is provided, or an array of transcriptions if multiple are provided - """ - - log_spec = prep_audio(waveforms, model.batch_size, truncate) - nsample = model.decoder.max_tokens_to_sample - - def inferloop(ctx: Union[np.ndarray, List[np.ndarray]], encoded_audio): - pos, next_tokens = 0, ctx - for i in range((nsample-len(start_tokens))*2): - next_tokens = model.decoder(Tensor(next_tokens), pos, encoded_audio)[:, -1].argmax(axis=-1).numpy().astype(np.int32).reshape(-1, 1) - next_tokens[ctx[:, -1] == eot] = eot - ctx = np.concatenate((ctx, next_tokens), axis=1) - pos = ctx.shape[-1] - 1 - if (next_tokens == eot).all(): break - return ctx - - def gettexttoks(line): return [tok for tok in line if tok < eot or tok > enc._special_tokens["<|notimestamps|>"]][-nsample+len(start_tokens):] - start_tokens = [enc._special_tokens["<|startoftranscript|>"]] - if model.is_multilingual: - # TODO detect language - language_token = enc._special_tokens["<|startoftranscript|>"] + 1 + tuple(LANGUAGES.keys()).index("en") - start_tokens.append(language_token) - start_tokens.append(enc._special_tokens["<|transcribe|>"]) - start_tokens.append(enc._special_tokens["<|notimestamps|>"]) - - eot = enc._special_tokens["<|endoftext|>"] - - ctx = np.tile(start_tokens, (model.batch_size,1)) - transcriptions = [[] for _ in waveforms] - - for curr_frame in range(0, log_spec.shape[-1], FRAMES_PER_SEGMENT): - encoded_audio = model.encoder.encode(Tensor(log_spec[:, :, curr_frame:curr_frame + FRAMES_PER_SEGMENT])) - - if all(len(c) == len(ctx[0]) for c in ctx): ctx = inferloop(np.array(ctx), encoded_audio) - else: ctx = [inferloop((np.array([c]*model.batch_size)), encoded_audio)[i] for i,c in enumerate(ctx)] - - for i, (res, arr) in enumerate(zip(transcriptions, ctx)): - if curr_frame*HOP_LENGTH <= len(waveforms[i]):res.extend(arr[np.where(arr == start_tokens[-1])[0][0]+1:eoti[0] if len (eoti:=np.where(arr == eot)[0]) else None]) - ctx = [[enc._special_tokens['<|startofprev|>']]+gettexttoks(cs)+start_tokens for cs in ctx] - - transcriptions = list(map(lambda tokens: enc.decode(tokens).strip(), transcriptions)) - return transcriptions if len(transcriptions) > 1 else transcriptions[0] - -CHUNK = 1600 -RECORD_SECONDS = 10 - -def listener(q): - import pyaudio - p = pyaudio.PyAudio() - stream = p.open(format=pyaudio.paInt16, channels=1, rate=RATE, input=True, frames_per_buffer=CHUNK) - print("listening") - for _ in range(0, int(RATE / CHUNK * RECORD_SECONDS)): - data = stream.read(CHUNK) - waveform = ((np.frombuffer(data, np.int16)/32768).astype(np.float32)*3) - q.put(waveform) - print("done listening") - -if __name__ == "__main__": - model, enc = init_whisper("small.en" if getenv("SMALL") else "tiny.en", batch_size=1) - - if len(sys.argv) > 1: - print(transcribe_file(model, enc, sys.argv[1])) - else: - # online - q = multiprocessing.Queue() - p = multiprocessing.Process(target=listener, args=(q,)) - p.daemon = True - p.start() - - lst = [enc._special_tokens["<|startoftranscript|>"], enc._special_tokens["<|notimestamps|>"]] - total = None - did_read = False - for i in range(0, int(RATE / CHUNK * RECORD_SECONDS)): - while not q.empty() or total is None: - waveform = q.get() - if total is None: total = waveform - else: total = np.concatenate([total, waveform]) - did_read = True - if did_read: - log_spec = prep_audio(total.reshape(1, -1), model.batch_size, truncate=True) - encoded_audio = model.encoder.encode(Tensor(log_spec)) - # pass the previously inferred tokens as 'prefix' - https://github.com/openai/whisper/discussions/117#discussioncomment-3727051 - out = model.decoder(Tensor([lst]), 0, encoded_audio, streaming=True).realize() - idx = int(out[0,-1].argmax().numpy().item()) - lst.append(idx) - dec = enc.decode(lst) - print(dec) # DO NOT REMOVE PRINT. IT'S VERY IMPORTANT - if dec.endswith("<|endoftext|>"): - lst.pop() diff --git a/tinygrad/examples/yolov3.py b/tinygrad/examples/yolov3.py deleted file mode 100755 index 49a2adb0..00000000 --- a/tinygrad/examples/yolov3.py +++ /dev/null @@ -1,406 +0,0 @@ -# https://raw.githubusercontent.com/pjreddie/darknet/master/cfg/yolov3.cfg -import sys -import io -import time -import math -import cv2 -import numpy as np -from PIL import Image -from tinygrad.tensor import Tensor -from tinygrad.nn import BatchNorm2d, Conv2d -from tinygrad.helpers import fetch - -def show_labels(prediction, confidence=0.5, num_classes=80): - coco_labels = fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/data/coco.names').read_bytes() - coco_labels = coco_labels.decode('utf-8').split('\n') - prediction = prediction.detach().numpy() - conf_mask = (prediction[:,:,4] > confidence) - prediction *= np.expand_dims(conf_mask, 2) - labels = [] - # Iterate over batches - for img_pred in prediction: - max_conf = np.amax(img_pred[:,5:5+num_classes], axis=1) - max_conf_score = np.argmax(img_pred[:,5:5+num_classes], axis=1) - max_conf_score = np.expand_dims(max_conf_score, axis=1) - max_conf = np.expand_dims(max_conf, axis=1) - seq = (img_pred[:,:5], max_conf, max_conf_score) - image_pred = np.concatenate(seq, axis=1) - non_zero_ind = np.nonzero(image_pred[:,4])[0] - assert all(image_pred[non_zero_ind,0] > 0) - image_pred_ = np.reshape(image_pred[np.squeeze(non_zero_ind),:], (-1, 7)) - classes, indexes = np.unique(image_pred_[:, -1], return_index=True) - for index, coco_class in enumerate(classes): - label, probability = coco_labels[int(coco_class)], image_pred_[indexes[index]][4] * 100 - print(f"Detected {label} {probability:.2f}") - labels.append(label) - return labels - -def add_boxes(img, prediction): - if isinstance(prediction, int): # no predictions - return img - coco_labels = fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/data/coco.names').read_bytes() - coco_labels = coco_labels.decode('utf-8').split('\n') - height, width = img.shape[0:2] - scale_factor = 608 / width - prediction[:,[1,3]] -= (608 - scale_factor * width) / 2 - prediction[:,[2,4]] -= (608 - scale_factor * height) / 2 - for pred in prediction: - corner1 = tuple(pred[1:3].astype(int)) - corner2 = tuple(pred[3:5].astype(int)) - w = corner2[0] - corner1[0] - h = corner2[1] - corner1[1] - corner2 = (corner2[0] + w, corner2[1] + h) - label = coco_labels[int(pred[-1])] - img = cv2.rectangle(img, corner1, corner2, (255, 0, 0), 2) - t_size = cv2.getTextSize(label, cv2.FONT_HERSHEY_PLAIN, 1 , 1)[0] - c2 = corner1[0] + t_size[0] + 3, corner1[1] + t_size[1] + 4 - img = cv2.rectangle(img, corner1, c2, (255, 0, 0), -1) - img = cv2.putText(img, label, (corner1[0], corner1[1] + t_size[1] + 4), cv2.FONT_HERSHEY_PLAIN, 1, [225,255,255], 1) - return img - -def bbox_iou(box1, box2): - """ - Returns the IoU of two bounding boxes - IoU: IoU = Area Of Overlap / Area of Union -> How close the predicted bounding box is - to the ground truth bounding box. Higher IoU = Better accuracy - In training, used to track accuracy. with inference, using to remove duplicate bounding boxes - """ - # Get the coordinates of bounding boxes - b1_x1, b1_y1, b1_x2, b1_y2 = box1[:,0], box1[:,1], box1[:,2], box1[:,3] - b2_x1, b2_y1, b2_x2, b2_y2 = box2[:,0], box2[:,1], box2[:,2], box2[:,3] - # get the coordinates of the intersection rectangle - inter_rect_x1 = np.maximum(b1_x1, b2_x1) - inter_rect_y1 = np.maximum(b1_y1, b2_y1) - inter_rect_x2 = np.maximum(b1_x2, b2_x2) - inter_rect_y2 = np.maximum(b1_y2, b2_y2) - #Intersection area - inter_area = np.clip(inter_rect_x2 - inter_rect_x1 + 1, 0, 99999) * np.clip(inter_rect_y2 - inter_rect_y1 + 1, 0, 99999) - #Union Area - b1_area = (b1_x2 - b1_x1 + 1)*(b1_y2 - b1_y1 + 1) - b2_area = (b2_x2 - b2_x1 + 1)*(b2_y2 - b2_y1 + 1) - iou = inter_area / (b1_area + b2_area - inter_area) - return iou - -def process_results(prediction, confidence=0.9, num_classes=80, nms_conf=0.4): - prediction = prediction.detach().numpy() - conf_mask = (prediction[:,:,4] > confidence) - conf_mask = np.expand_dims(conf_mask, 2) - prediction = prediction * conf_mask - # Non max suppression - box_corner = prediction - box_corner[:,:,0] = (prediction[:,:,0] - prediction[:,:,2]/2) - box_corner[:,:,1] = (prediction[:,:,1] - prediction[:,:,3]/2) - box_corner[:,:,2] = (prediction[:,:,0] + prediction[:,:,2]/2) - box_corner[:,:,3] = (prediction[:,:,1] + prediction[:,:,3]/2) - prediction[:,:,:4] = box_corner[:,:,:4] - write = False - # Process img - img_pred = prediction[0] - max_conf = np.amax(img_pred[:,5:5+num_classes], axis=1) - max_conf_score = np.argmax(img_pred[:,5:5+num_classes], axis=1) - max_conf_score = np.expand_dims(max_conf_score, axis=1) - max_conf = np.expand_dims(max_conf, axis=1) - seq = (img_pred[:,:5], max_conf, max_conf_score) - image_pred = np.concatenate(seq, axis=1) - non_zero_ind = np.nonzero(image_pred[:,4])[0] - assert all(image_pred[non_zero_ind,0] > 0) - image_pred_ = np.reshape(image_pred[np.squeeze(non_zero_ind),:], (-1, 7)) - if image_pred_.shape[0] == 0: - print("No detections found!") - return 0 - for cls in np.unique(image_pred_[:, -1]): - # perform NMS, get the detections with one particular class - cls_mask = image_pred_*np.expand_dims(image_pred_[:, -1] == cls, axis=1) - class_mask_ind = np.squeeze(np.nonzero(cls_mask[:,-2])) - # class_mask_ind = np.nonzero() - image_pred_class = np.reshape(image_pred_[class_mask_ind], (-1, 7)) - # sort the detections such that the entry with the maximum objectness - # confidence is at the top - conf_sort_index = np.argsort(image_pred_class[:,4]) - image_pred_class = image_pred_class[conf_sort_index] - for i in range(image_pred_class.shape[0]): - # Get the IOUs of all boxes that come after the one we are looking at in the loop - try: - ious = bbox_iou(np.expand_dims(image_pred_class[i], axis=0), image_pred_class[i+1:]) - except: - break - # Zero out all the detections that have IoU > threshold - iou_mask = np.expand_dims((ious < nms_conf), axis=1) - image_pred_class[i+1:] *= iou_mask - # Remove the non-zero entries - non_zero_ind = np.squeeze(np.nonzero(image_pred_class[:,4])) - image_pred_class = np.reshape(image_pred_class[non_zero_ind], (-1, 7)) - batch_ind = np.array([[0]]) - seq = (batch_ind, image_pred_class) - if not write: - output, write = np.concatenate(seq, axis=1), True - else: - out = np.concatenate(seq, axis=1) - output = np.concatenate((output,out)) - return output - -def infer(model, img): - img = np.array(Image.fromarray(img).resize((608, 608))) - img = img[:,:,::-1].transpose((2,0,1)) - img = img[np.newaxis,:,:,:]/255.0 - prediction = model.forward(Tensor(img.astype(np.float32))) - return prediction - - -def parse_cfg(cfg): - # Return a list of blocks - lines = cfg.decode("utf-8").split('\n') - lines = [x for x in lines if len(x) > 0] - lines = [x for x in lines if x[0] != '#'] - lines = [x.rstrip().lstrip() for x in lines] - block, blocks = {}, [] - for line in lines: - if line[0] == "[": - if len(block) != 0: - blocks.append(block) - block = {} - block["type"] = line[1:-1].rstrip() - else: - key,value = line.split("=") - block[key.rstrip()] = value.lstrip() - blocks.append(block) - return blocks - -# TODO: Speed up this function, avoid copying stuff from GPU to CPU -def predict_transform(prediction, inp_dim, anchors, num_classes): - batch_size = prediction.shape[0] - stride = inp_dim // prediction.shape[2] - grid_size = inp_dim // stride - bbox_attrs = 5 + num_classes - num_anchors = len(anchors) - prediction = prediction.reshape(shape=(batch_size, bbox_attrs*num_anchors, grid_size*grid_size)) - prediction = prediction.transpose(1, 2) - prediction = prediction.reshape(shape=(batch_size, grid_size*grid_size*num_anchors, bbox_attrs)) - prediction_cpu = prediction.numpy() - for i in (0, 1, 4): - prediction_cpu[:,:,i] = 1 / (1 + np.exp(-prediction_cpu[:,:,i])) - # Add the center offsets - grid = np.arange(grid_size) - a, b = np.meshgrid(grid, grid) - x_offset = a.reshape((-1, 1)) - y_offset = b.reshape((-1, 1)) - x_y_offset = np.concatenate((x_offset, y_offset), 1) - x_y_offset = np.tile(x_y_offset, (1, num_anchors)) - x_y_offset = x_y_offset.reshape((-1,2)) - x_y_offset = np.expand_dims(x_y_offset, 0) - anchors = [(a[0]/stride, a[1]/stride) for a in anchors] - anchors = np.tile(anchors, (grid_size*grid_size, 1)) - anchors = np.expand_dims(anchors, 0) - prediction_cpu[:,:,:2] += x_y_offset - prediction_cpu[:,:,2:4] = np.exp(prediction_cpu[:,:,2:4])*anchors - prediction_cpu[:,:,5:5+num_classes] = 1 / (1 + np.exp(-prediction_cpu[:,:,5:5+num_classes])) - prediction_cpu[:,:,:4] *= stride - return Tensor(prediction_cpu) - - -class Darknet: - def __init__(self, cfg): - self.blocks = parse_cfg(cfg) - self.net_info, self.module_list = self.create_modules(self.blocks) - print("Modules length:", len(self.module_list)) - - def create_modules(self, blocks): - net_info = blocks[0] # Info about model hyperparameters - prev_filters, filters = 3, None - output_filters, module_list = [], [] - ## module - for index, x in enumerate(blocks[1:]): - module_type = x["type"] - module = [] - if module_type == "convolutional": - try: - batch_normalize, bias = int(x["batch_normalize"]), False - except: - batch_normalize, bias = 0, True - # layer - activation = x["activation"] - filters = int(x["filters"]) - padding = int(x["pad"]) - pad = (int(x["size"]) - 1) // 2 if padding else 0 - module.append(Conv2d(prev_filters, filters, int(x["size"]), int(x["stride"]), pad, bias=bias)) - # BatchNorm2d - if batch_normalize: - module.append(BatchNorm2d(filters, eps=1e-05, track_running_stats=True)) - # LeakyReLU activation - if activation == "leaky": - module.append(lambda x: x.leaky_relu(0.1)) - elif module_type == "maxpool": - size, stride = int(x["size"]), int(x["stride"]) - module.append(lambda x: x.max_pool2d(kernel_size=(size, size), stride=stride)) - elif module_type == "upsample": - module.append(lambda x: Tensor(x.numpy().repeat(2, axis=-2).repeat(2, axis=-1))) - elif module_type == "route": - x["layers"] = x["layers"].split(",") - # Start of route - start = int(x["layers"][0]) - # End if it exists - try: - end = int(x["layers"][1]) - except: - end = 0 - if start > 0: start -= index - if end > 0: end -= index - module.append(lambda x: x) - if end < 0: - filters = output_filters[index + start] + output_filters[index + end] - else: - filters = output_filters[index + start] - # Shortcut corresponds to skip connection - elif module_type == "shortcut": - module.append(lambda x: x) - elif module_type == "yolo": - mask = list(map(int, x["mask"].split(","))) - anchors = [int(a) for a in x["anchors"].split(",")] - anchors = [(anchors[i], anchors[i+1]) for i in range(0, len(anchors), 2)] - module.append([anchors[i] for i in mask]) - # Append to module_list - module_list.append(module) - if filters is not None: - prev_filters = filters - output_filters.append(filters) - return (net_info, module_list) - - def dump_weights(self): - for i in range(len(self.module_list)): - module_type = self.blocks[i + 1]["type"] - if module_type == "convolutional": - print(self.blocks[i + 1]["type"], "weights", i) - model = self.module_list[i] - conv = model[0] - print(conv.weight.numpy()[0][0][0]) - if conv.bias is not None: - print("biases") - print(conv.bias.shape) - print(conv.bias.numpy()[0][0:5]) - else: - print("None biases for layer", i) - - def load_weights(self, url): - weights = np.frombuffer(fetch(url).read_bytes(), dtype=np.float32)[5:] - ptr = 0 - for i in range(len(self.module_list)): - module_type = self.blocks[i + 1]["type"] - if module_type == "convolutional": - model = self.module_list[i] - try: # we have batchnorm, load conv weights without biases, and batchnorm values - batch_normalize = int(self.blocks[i+1]["batch_normalize"]) - except: # no batchnorm, load conv weights + biases - batch_normalize = 0 - conv = model[0] - if batch_normalize: - bn = model[1] - # Get the number of weights of batchnorm - num_bn_biases = math.prod(bn.bias.shape) - # Load weights - bn_biases = Tensor(weights[ptr:ptr + num_bn_biases]) - ptr += num_bn_biases - bn_weights = Tensor(weights[ptr:ptr+num_bn_biases]) - ptr += num_bn_biases - bn_running_mean = Tensor(weights[ptr:ptr+num_bn_biases]) - ptr += num_bn_biases - bn_running_var = Tensor(weights[ptr:ptr+num_bn_biases]) - ptr += num_bn_biases - # Cast the loaded weights into dims of model weights - bn_biases = bn_biases.reshape(shape=tuple(bn.bias.shape)) - bn_weights = bn_weights.reshape(shape=tuple(bn.weight.shape)) - bn_running_mean = bn_running_mean.reshape(shape=tuple(bn.running_mean.shape)) - bn_running_var = bn_running_var.reshape(shape=tuple(bn.running_var.shape)) - # Copy data - bn.bias = bn_biases - bn.weight = bn_weights - bn.running_mean = bn_running_mean - bn.running_var = bn_running_var - else: - # load biases of the conv layer - num_biases = math.prod(conv.bias.shape) - # Load weights - conv_biases = Tensor(weights[ptr: ptr+num_biases]) - ptr += num_biases - # Reshape - conv_biases = conv_biases.reshape(shape=tuple(conv.bias.shape)) - # Copy - conv.bias = conv_biases - # Load weighys for conv layers - num_weights = math.prod(conv.weight.shape) - conv_weights = Tensor(weights[ptr:ptr+num_weights]) - ptr += num_weights - conv_weights = conv_weights.reshape(shape=tuple(conv.weight.shape)) - conv.weight = conv_weights - - def forward(self, x): - modules = self.blocks[1:] - outputs = {} # Cached outputs for route layer - detections, write = None, False - for i, module in enumerate(modules): - module_type = (module["type"]) - if module_type == "convolutional" or module_type == "upsample": - for layer in self.module_list[i]: - x = layer(x) - elif module_type == "route": - layers = module["layers"] - layers = [int(a) for a in layers] - if (layers[0]) > 0: - layers[0] = layers[0] - i - if len(layers) == 1: - x = outputs[i + (layers[0])] - else: - if (layers[1]) > 0: layers[1] = layers[1] - i - map1 = outputs[i + layers[0]] - map2 = outputs[i + layers[1]] - x = Tensor(np.concatenate((map1.numpy(), map2.numpy()), axis=1)) - elif module_type == "shortcut": - from_ = int(module["from"]) - x = outputs[i - 1] + outputs[i + from_] - elif module_type == "yolo": - anchors = self.module_list[i][0] - inp_dim = int(self.net_info["height"]) # 416 - num_classes = int(module["classes"]) - x = predict_transform(x, inp_dim, anchors, num_classes) - if not write: - detections, write = x, True - else: - detections = Tensor(np.concatenate((detections.numpy(), x.numpy()), axis=1)) - outputs[i] = x - return detections - -if __name__ == "__main__": - model = Darknet(fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/cfg/yolov3.cfg').read_bytes()) - print("Loading weights file (237MB). This might take a while…") - model.load_weights('https://pjreddie.com/media/files/yolov3.weights') - if len(sys.argv) > 1: - url = sys.argv[1] - else: - url = "https://github.com/ayooshkathuria/pytorch-yolo-v3/raw/master/dog-cycle-car.png" - if url == 'webcam': - cap = cv2.VideoCapture(0) - cap.set(cv2.CAP_PROP_BUFFERSIZE, 1) - while 1: - _ = cap.grab() # discard one frame to circumvent capture buffering - ret, frame = cap.read() - prediction = process_results(infer(model, frame)) - img = Image.fromarray(frame[:, :, [2,1,0]]) - boxes = add_boxes(np.array(img.resize((608, 608))), prediction) - boxes = cv2.cvtColor(boxes, cv2.COLOR_RGB2BGR) - cv2.imshow('yolo', boxes) - if cv2.waitKey(1) & 0xFF == ord('q'): - break - cap.release() - cv2.destroyAllWindows() - elif url.startswith('http'): - img_stream = io.BytesIO(fetch(url).read_bytes()) - img = cv2.imdecode(np.frombuffer(img_stream.read(), np.uint8), 1) - else: - img = cv2.imread(url) - st = time.time() - print('running inference…') - prediction = infer(model, img) - print(f'did inference in {(time.time() - st):2f}s') - show_labels(prediction) - prediction = process_results(prediction) - boxes = add_boxes(np.array(Image.fromarray(img).resize((608, 608))), prediction) - cv2.imwrite('boxes.jpg', boxes) diff --git a/tinygrad/examples/yolov8-onnx.py b/tinygrad/examples/yolov8-onnx.py deleted file mode 100644 index 5f76ab7e..00000000 --- a/tinygrad/examples/yolov8-onnx.py +++ /dev/null @@ -1,15 +0,0 @@ -#!/usr/bin/env python3 -import os -from ultralytics import YOLO -from pathlib import Path -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from extra.onnx_helpers import get_example_inputs -from tinygrad.tensor import Tensor - -os.chdir("/tmp") -if not Path("yolov8n-seg.onnx").is_file(): - model = YOLO("yolov8n-seg.pt") - model.export(format="onnx", imgsz=[480,640]) -onnx_model = onnx_load(open("yolov8n-seg.onnx", "rb")) -run_onnx = OnnxRunner(onnx_model) -run_onnx(get_example_inputs(run_onnx.graph_inputs), debug=True) diff --git a/tinygrad/examples/yolov8.py b/tinygrad/examples/yolov8.py deleted file mode 100644 index 1a9035a2..00000000 --- a/tinygrad/examples/yolov8.py +++ /dev/null @@ -1,399 +0,0 @@ -from tinygrad.nn import Conv2d, BatchNorm2d -from tinygrad.tensor import Tensor -from tinygrad.device import is_dtype_supported -from tinygrad import dtypes -import numpy as np -from itertools import chain -from pathlib import Path -import cv2 -from collections import defaultdict -import time, sys -from tinygrad.helpers import fetch -from tinygrad.nn.state import safe_load, load_state_dict -import json - -#Model architecture from https://github.com/ultralytics/ultralytics/issues/189 -#The upsampling class has been taken from this pull request https://github.com/tinygrad/tinygrad/pull/784 by dc-dc-dc. Now 2(?) models use upsampling. (retinet and this) - -#Pre processing image functions. -def compute_transform(image, new_shape=(640, 640), auto=False, scaleFill=False, scaleup=True, stride=32) -> Tensor: - shape = image.shape[:2] # current shape [height, width] - new_shape = (new_shape, new_shape) if isinstance(new_shape, int) else new_shape - r = min(new_shape[0] / shape[0], new_shape[1] / shape[1]) - r = min(r, 1.0) if not scaleup else r - new_unpad = (int(round(shape[1] * r)), int(round(shape[0] * r))) - dw, dh = new_shape[1] - new_unpad[0], new_shape[0] - new_unpad[1] - dw, dh = (np.mod(dw, stride), np.mod(dh, stride)) if auto else (0.0, 0.0) - new_unpad = (new_shape[1], new_shape[0]) if scaleFill else new_unpad - dw /= 2 - dh /= 2 - image = cv2.resize(image, new_unpad, interpolation=cv2.INTER_LINEAR) if shape[::-1] != new_unpad else image - top, bottom = int(round(dh - 0.1)), int(round(dh + 0.1)) - left, right = int(round(dw - 0.1)), int(round(dw + 0.1)) - image = cv2.copyMakeBorder(image, top, bottom, left, right, cv2.BORDER_CONSTANT, value=(114, 114, 114)) - return Tensor(image) - -def preprocess(im, imgsz=640, model_stride=32, model_pt=True): - same_shapes = all(x.shape == im[0].shape for x in im) - auto = same_shapes and model_pt - im = [compute_transform(x, new_shape=imgsz, auto=auto, stride=model_stride) for x in im] - im = Tensor.stack(*im) if len(im) > 1 else im[0].unsqueeze(0) - im = im[..., ::-1].permute(0, 3, 1, 2) # BGR to RGB, BHWC to BCHW, (n, 3, h, w) - im = im / 255.0 # 0 - 255 to 0.0 - 1.0 - return im - - -def draw_bounding_boxes_and_save(orig_img_path, output_img_path, predictions, class_labels): - color_dict = {label: tuple((((i+1) * 50) % 256, ((i+1) * 100) % 256, ((i+1) * 150) % 256)) for i, label in enumerate(class_labels)} - font = cv2.FONT_HERSHEY_SIMPLEX - - def is_bright_color(color): - r, g, b = color - brightness = (r * 299 + g * 587 + b * 114) / 1000 - return brightness > 127 - - orig_img = cv2.imread(orig_img_path) if not isinstance(orig_img_path, np.ndarray) else cv2.imdecode(orig_img_path, 1) - height, width, _ = orig_img.shape - box_thickness = int((height + width) / 400) - font_scale = (height + width) / 2500 - object_count = defaultdict(int) - - for pred in predictions: - x1, y1, x2, y2, conf, class_id = pred - if conf == 0: continue - x1, y1, x2, y2, class_id = map(int, (x1, y1, x2, y2, class_id)) - color = color_dict[class_labels[class_id]] - cv2.rectangle(orig_img, (x1, y1), (x2, y2), color, box_thickness) - label = f"{class_labels[class_id]} {conf:.2f}" - text_size, _ = cv2.getTextSize(label, font, font_scale, 1) - label_y, bg_y = (y1 - 4, y1 - text_size[1] - 4) if y1 - text_size[1] - 4 > 0 else (y1 + text_size[1], y1) - cv2.rectangle(orig_img, (x1, bg_y), (x1 + text_size[0], bg_y + text_size[1]), color, -1) - font_color = (0, 0, 0) if is_bright_color(color) else (255, 255, 255) - cv2.putText(orig_img, label, (x1, label_y), font, font_scale, font_color, 1, cv2.LINE_AA) - object_count[class_labels[class_id]] += 1 - - print("Objects detected:") - for obj, count in object_count.items(): - print(f"- {obj}: {count}") - - cv2.imwrite(output_img_path, orig_img) - print(f'saved detections at {output_img_path}') - -# utility functions for forward pass. -def dist2bbox(distance, anchor_points, xywh=True, dim=-1): - lt, rb = distance.chunk(2, dim) - x1y1 = anchor_points - lt - x2y2 = anchor_points + rb - if xywh: - c_xy = (x1y1 + x2y2) / 2 - wh = x2y2 - x1y1 - return c_xy.cat(wh, dim=1) - return x1y1.cat(x2y2, dim=1) - -def make_anchors(feats, strides, grid_cell_offset=0.5): - anchor_points, stride_tensor = [], [] - assert feats is not None - for i, stride in enumerate(strides): - _, _, h, w = feats[i].shape - sx = Tensor.arange(w) + grid_cell_offset - sy = Tensor.arange(h) + grid_cell_offset - - # this is np.meshgrid but in tinygrad - sx = sx.reshape(1, -1).repeat([h, 1]).reshape(-1) - sy = sy.reshape(-1, 1).repeat([1, w]).reshape(-1) - - anchor_points.append(Tensor.stack(sx, sy, dim=-1).reshape(-1, 2)) - stride_tensor.append(Tensor.full((h * w), stride)) - anchor_points = anchor_points[0].cat(anchor_points[1], anchor_points[2]) - stride_tensor = stride_tensor[0].cat(stride_tensor[1], stride_tensor[2]).unsqueeze(1) - return anchor_points, stride_tensor - -# this function is from the original implementation -def autopad(k, p=None, d=1): # kernel, padding, dilation - if d > 1: - k = d * (k - 1) + 1 if isinstance(k, int) else [d * (x - 1) + 1 for x in k] # actual kernel-size - if p is None: - p = k // 2 if isinstance(k, int) else [x // 2 for x in k] # auto-pad - return p - -def clip_boxes(boxes, shape): - boxes[..., [0, 2]] = np.clip(boxes[..., [0, 2]], 0, shape[1]) # x1, x2 - boxes[..., [1, 3]] = np.clip(boxes[..., [1, 3]], 0, shape[0]) # y1, y2 - return boxes - -def scale_boxes(img1_shape, predictions, img0_shape, ratio_pad=None): - gain = ratio_pad if ratio_pad else min(img1_shape[0] / img0_shape[0], img1_shape[1] / img0_shape[1]) - pad = ((img1_shape[1] - img0_shape[1] * gain) / 2, (img1_shape[0] - img0_shape[0] * gain) / 2) - for pred in predictions: - boxes_np = pred[:4].numpy() if isinstance(pred[:4], Tensor) else pred[:4] - boxes_np[..., [0, 2]] -= pad[0] - boxes_np[..., [1, 3]] -= pad[1] - boxes_np[..., :4] /= gain - boxes_np = clip_boxes(boxes_np, img0_shape) - pred[:4] = boxes_np - return predictions - -def get_variant_multiples(variant): - return {'n':(0.33, 0.25, 2.0), 's':(0.33, 0.50, 2.0), 'm':(0.67, 0.75, 1.5), 'l':(1.0, 1.0, 1.0), 'x':(1, 1.25, 1.0) }.get(variant, None) - -def label_predictions(all_predictions): - class_index_count = defaultdict(int) - for pred in all_predictions: - class_id = int(pred[-1]) - if pred[-2] != 0: class_index_count[class_id] += 1 - - return dict(class_index_count) - -#this is taken from https://github.com/tinygrad/tinygrad/pull/784/files by dc-dc-dc (Now 2 models use upsampling) -class Upsample: - def __init__(self, scale_factor:int, mode: str = "nearest") -> None: - assert mode == "nearest" # only mode supported for now - self.mode = mode - self.scale_factor = scale_factor - - def __call__(self, x: Tensor) -> Tensor: - assert len(x.shape) > 2 and len(x.shape) <= 5 - (b, c), _lens = x.shape[:2], len(x.shape[2:]) - tmp = x.reshape([b, c, -1] + [1] * _lens) * Tensor.ones(*[1, 1, 1] + [self.scale_factor] * _lens) - return tmp.reshape(list(x.shape) + [self.scale_factor] * _lens).permute([0, 1] + list(chain.from_iterable([[y+2, y+2+_lens] for y in range(_lens)]))).reshape([b, c] + [x * self.scale_factor for x in x.shape[2:]]) - -class Conv_Block: - def __init__(self, c1, c2, kernel_size=1, stride=1, groups=1, dilation=1, padding=None): - self.conv = Conv2d(c1,c2, kernel_size, stride, padding=autopad(kernel_size, padding, dilation), bias=False, groups=groups, dilation=dilation) - self.bn = BatchNorm2d(c2, eps=0.001) - - def __call__(self, x): - return self.bn(self.conv(x)).silu() - -class Bottleneck: - def __init__(self, c1, c2 , shortcut: bool, g=1, kernels: list = (3,3), channel_factor=0.5): - c_ = int(c2 * channel_factor) - self.cv1 = Conv_Block(c1, c_, kernel_size=kernels[0], stride=1, padding=None) - self.cv2 = Conv_Block(c_, c2, kernel_size=kernels[1], stride=1, padding=None, groups=g) - self.residual = c1 == c2 and shortcut - - def __call__(self, x): - return x + self.cv2(self.cv1(x)) if self.residual else self.cv2(self.cv1(x)) - -class C2f: - def __init__(self, c1, c2, n=1, shortcut=False, g=1, e=0.5): - self.c = int(c2 * e) - self.cv1 = Conv_Block(c1, 2 * self.c, 1,) - self.cv2 = Conv_Block((2 + n) * self.c, c2, 1) - self.bottleneck = [Bottleneck(self.c, self.c, shortcut, g, kernels=[(3, 3), (3, 3)], channel_factor=1.0) for _ in range(n)] - - def __call__(self, x): - y= list(self.cv1(x).chunk(2, 1)) - y.extend(m(y[-1]) for m in self.bottleneck) - z = y[0] - for i in y[1:]: z = z.cat(i, dim=1) - return self.cv2(z) - -class SPPF: - def __init__(self, c1, c2, k=5): - c_ = c1 // 2 # hidden channels - self.cv1 = Conv_Block(c1, c_, 1, 1, padding=None) - self.cv2 = Conv_Block(c_ * 4, c2, 1, 1, padding=None) - - # TODO: this pads with 0s, whereas torch function pads with -infinity. This results in a < 2% difference in prediction which does not make a difference visually. - self.maxpool = lambda x : x.pad((k // 2, k // 2, k // 2, k // 2)).max_pool2d(kernel_size=k, stride=1) - - def __call__(self, x): - x = self.cv1(x) - x2 = self.maxpool(x) - x3 = self.maxpool(x2) - x4 = self.maxpool(x3) - return self.cv2(x.cat(x2, x3, x4, dim=1)) - -class DFL: - def __init__(self, c1=16): - self.conv = Conv2d(c1, 1, 1, bias=False) - x = Tensor.arange(c1) - self.conv.weight.replace(x.reshape(1, c1, 1, 1)) - self.c1 = c1 - - def __call__(self, x): - b, c, a = x.shape # batch, channels, anchors - return self.conv(x.reshape(b, 4, self.c1, a).transpose(2, 1).softmax(1)).reshape(b, 4, a) - -#backbone -class Darknet: - def __init__(self, w, r, d): - self.b1 = [Conv_Block(c1=3, c2= int(64*w), kernel_size=3, stride=2, padding=1), Conv_Block(int(64*w), int(128*w), kernel_size=3, stride=2, padding=1)] - self.b2 = [C2f(c1=int(128*w), c2=int(128*w), n=round(3*d), shortcut=True), Conv_Block(int(128*w), int(256*w), 3, 2, 1), C2f(int(256*w), int(256*w), round(6*d), True)] - self.b3 = [Conv_Block(int(256*w), int(512*w), kernel_size=3, stride=2, padding=1), C2f(int(512*w), int(512*w), round(6*d), True)] - self.b4 = [Conv_Block(int(512*w), int(512*w*r), kernel_size=3, stride=2, padding=1), C2f(int(512*w*r), int(512*w*r), round(3*d), True)] - self.b5 = [SPPF(int(512*w*r), int(512*w*r), 5)] - - def return_modules(self): - return [*self.b1, *self.b2, *self.b3, *self.b4, *self.b5] - - def __call__(self, x): - x1 = x.sequential(self.b1) - x2 = x1.sequential(self.b2) - x3 = x2.sequential(self.b3) - x4 = x3.sequential(self.b4) - x5 = x4.sequential(self.b5) - return (x2, x3, x5) - -#yolo fpn (neck) -class Yolov8NECK: - def __init__(self, w, r, d): #width_multiple, ratio_multiple, depth_multiple - self.up = Upsample(2, mode='nearest') - self.n1 = C2f(c1=int(512*w*(1+r)), c2=int(512*w), n=round(3*d), shortcut=False) - self.n2 = C2f(c1=int(768*w), c2=int(256*w), n=round(3*d), shortcut=False) - self.n3 = Conv_Block(c1=int(256*w), c2=int(256*w), kernel_size=3, stride=2, padding=1) - self.n4 = C2f(c1=int(768*w), c2=int(512*w), n=round(3*d), shortcut=False) - self.n5 = Conv_Block(c1=int(512* w), c2=int(512 * w), kernel_size=3, stride=2, padding=1) - self.n6 = C2f(c1=int(512*w*(1+r)), c2=int(512*w*r), n=round(3*d), shortcut=False) - - def return_modules(self): - return [self.n1, self.n2, self.n3, self.n4, self.n5, self.n6] - - def __call__(self, p3, p4, p5): - x = self.n1(self.up(p5).cat(p4, dim=1)) - head_1 = self.n2(self.up(x).cat(p3, dim=1)) - head_2 = self.n4(self.n3(head_1).cat(x, dim=1)) - head_3 = self.n6(self.n5(head_2).cat(p5, dim=1)) - return [head_1, head_2, head_3] - -#task specific head. -class DetectionHead: - def __init__(self, nc=80, filters=()): - self.ch = 16 - self.nc = nc # number of classes - self.nl = len(filters) - self.no = nc + self.ch * 4 # - self.stride = [8, 16, 32] - c1 = max(filters[0], self.nc) - c2 = max((filters[0] // 4, self.ch * 4)) - self.dfl = DFL(self.ch) - self.cv3 = [[Conv_Block(x, c1, 3), Conv_Block(c1, c1, 3), Conv2d(c1, self.nc, 1)] for x in filters] - self.cv2 = [[Conv_Block(x, c2, 3), Conv_Block(c2, c2, 3), Conv2d(c2, 4 * self.ch, 1)] for x in filters] - - def __call__(self, x): - for i in range(self.nl): - x[i] = (x[i].sequential(self.cv2[i]).cat(x[i].sequential(self.cv3[i]), dim=1)) - self.anchors, self.strides = (x.transpose(0, 1) for x in make_anchors(x, self.stride, 0.5)) - y = [(i.reshape(x[0].shape[0], self.no, -1)) for i in x] - x_cat = y[0].cat(y[1], y[2], dim=2) - box, cls = x_cat[:, :self.ch * 4], x_cat[:, self.ch * 4:] - dbox = dist2bbox(self.dfl(box), self.anchors.unsqueeze(0), xywh=True, dim=1) * self.strides - z = dbox.cat(cls.sigmoid(), dim=1) - return z - -class YOLOv8: - def __init__(self, w, r, d, num_classes): #width_multiple, ratio_multiple, depth_multiple - self.net = Darknet(w, r, d) - self.fpn = Yolov8NECK(w, r, d) - self.head = DetectionHead(num_classes, filters=(int(256*w), int(512*w), int(512*w*r))) - - def __call__(self, x): - x = self.net(x) - x = self.fpn(*x) - x = self.head(x) - # TODO: postprocess needs to be in the model to be compiled to webgpu - return postprocess(x) - - def return_all_trainable_modules(self): - backbone_modules = [*range(10)] - yolov8neck_modules = [12, 15, 16, 18, 19, 21] - yolov8_head_weights = [(22, self.head)] - return [*zip(backbone_modules, self.net.return_modules()), *zip(yolov8neck_modules, self.fpn.return_modules()), *yolov8_head_weights] - -def convert_f16_safetensor_to_f32(input_file: Path, output_file: Path): - with open(input_file, 'rb') as f: - metadata_length = int.from_bytes(f.read(8), 'little') - metadata = json.loads(f.read(metadata_length).decode()) - float32_values = np.fromfile(f, dtype=np.float16).astype(np.float32) - - for v in metadata.values(): - if v["dtype"] == "F16": v.update({"dtype": "F32", "data_offsets": [offset * 2 for offset in v["data_offsets"]]}) - - with open(output_file, 'wb') as f: - new_metadata_bytes = json.dumps(metadata).encode() - f.write(len(new_metadata_bytes).to_bytes(8, 'little')) - f.write(new_metadata_bytes) - float32_values.tofile(f) - -def compute_iou_matrix(boxes): - x1, y1, x2, y2 = boxes[:, 0], boxes[:, 1], boxes[:, 2], boxes[:, 3] - areas = (x2 - x1) * (y2 - y1) - x1 = Tensor.maximum(x1[:, None], x1[None, :]) - y1 = Tensor.maximum(y1[:, None], y1[None, :]) - x2 = Tensor.minimum(x2[:, None], x2[None, :]) - y2 = Tensor.minimum(y2[:, None], y2[None, :]) - w = Tensor.maximum(Tensor(0), x2 - x1) - h = Tensor.maximum(Tensor(0), y2 - y1) - intersection = w * h - union = areas[:, None] + areas[None, :] - intersection - return intersection / union - -def postprocess(output, max_det=300, conf_threshold=0.25, iou_threshold=0.45): - xc, yc, w, h, class_scores = output[0][0], output[0][1], output[0][2], output[0][3], output[0][4:] - class_ids = Tensor.argmax(class_scores, axis=0) - probs = Tensor.max(class_scores, axis=0) - probs = Tensor.where(probs >= conf_threshold, probs, 0) - x1 = xc - w / 2 - y1 = yc - h / 2 - x2 = xc + w / 2 - y2 = yc + h / 2 - boxes = Tensor.stack(x1, y1, x2, y2, probs, class_ids, dim=1) - order = Tensor.topk(probs, max_det)[1] - boxes = boxes[order] - iou = compute_iou_matrix(boxes[:, :4]) - iou = Tensor.triu(iou, diagonal=1) - same_class_mask = boxes[:, -1][:, None] == boxes[:, -1][None, :] - high_iou_mask = (iou > iou_threshold) & same_class_mask - no_overlap_mask = high_iou_mask.sum(axis=0) == 0 - boxes = boxes * no_overlap_mask.unsqueeze(-1) - return boxes - -def get_weights_location(yolo_variant: str) -> Path: - weights_location = Path(__file__).parents[1] / "weights" / f'yolov8{yolo_variant}.safetensors' - fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{yolo_variant}.safetensors', weights_location) - f32_weights = weights_location.with_name(f"{weights_location.stem}_f32.safetensors") - if not f32_weights.exists(): convert_f16_safetensor_to_f32(weights_location, f32_weights) - return f32_weights - -if __name__ == '__main__': - - # usage : python3 yolov8.py "image_URL OR image_path" "v8 variant" (optional, n is default) - if len(sys.argv) < 2: - print("Error: Image URL or path not provided.") - sys.exit(1) - - img_path = sys.argv[1] - yolo_variant = sys.argv[2] if len(sys.argv) >= 3 else (print("No variant given, so choosing 'n' as the default. Yolov8 has different variants, you can choose from ['n', 's', 'm', 'l', 'x']") or 'n') - print(f'running inference for YOLO version {yolo_variant}') - - output_folder_path = Path('./outputs_yolov8') - output_folder_path.mkdir(parents=True, exist_ok=True) - #absolute image path or URL - image_location = np.frombuffer(fetch(img_path).read_bytes(), np.uint8) - image = [cv2.imdecode(image_location, 1)] - out_path = (output_folder_path / f"{Path(img_path).stem}_output{Path(img_path).suffix or '.png'}").as_posix() - if not isinstance(image[0], np.ndarray): - print('Error in image loading. Check your image file.') - sys.exit(1) - pre_processed_image = preprocess(image) - # Different YOLOv8 variants use different w , r, and d multiples. For a list , refer to this yaml file (the scales section) https://github.com/ultralytics/ultralytics/blob/main/ultralytics/cfg/models/v8/yolov8.yaml - depth, width, ratio = get_variant_multiples(yolo_variant) - yolo_infer = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) - state_dict = safe_load(get_weights_location(yolo_variant)) - load_state_dict(yolo_infer, state_dict) - - st = time.time() - predictions = yolo_infer(pre_processed_image).numpy() - - print(f'did inference in {int(round(((time.time() - st) * 1000)))}ms') - #v8 and v3 have same 80 class names for Object Detection - class_labels = fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/data/coco.names').read_text().split("\n") - predictions = scale_boxes(pre_processed_image.shape[2:], predictions, image[0].shape) - draw_bounding_boxes_and_save(orig_img_path=image_location, output_img_path=out_path, predictions=predictions, class_labels=class_labels) - -# TODO for later: -# 1. Fix SPPF minor difference due to maxpool -# 2. AST exp overflow warning while on cpu -# 3. Make NMS faster -# 4. Add video inference and webcam support diff --git a/tinygrad/extra/amdpci/am_smi.py b/tinygrad/extra/amdpci/am_smi.py deleted file mode 100755 index 31f29f26..00000000 --- a/tinygrad/extra/amdpci/am_smi.py +++ /dev/null @@ -1,321 +0,0 @@ -#!/usr/bin/env python3 - -import time, mmap, sys, shutil, os, glob, subprocess, argparse, collections -from tinygrad.helpers import DEBUG, colored, ansilen -from tinygrad.runtime.autogen import libc -from tinygrad.runtime.autogen.am import am -from tinygrad.runtime.support.hcq import MMIOInterface -from tinygrad.runtime.support.am.amdev import AMDev, AMMemoryManager, AMPageTableEntry -from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA - -AM_VERSION = 0xA0000005 - -def bold(s): return f"\033[1m{s}\033[0m" - -def trim(s:str, length:int) -> str: - if len(s) > length: return s[:length-3] + "..." - return s - -def pad(x:str, length:int) -> str: - if len(x) < length: return x + " " * (length - len(x)) - return x - -def color_temp(temp): - if temp >= 87: return colored(f"{temp:>3}", "red") - elif temp >= 80: return colored(f"{temp:>3}", "yellow") - return f"{temp:>3}" - -def color_voltage(voltage): return colored(f"{voltage/1000:>5.3f}V", "cyan") - -def draw_bar(percentage, width=40, fill='|', empty=' ', opt_text='', color='cyan'): - filled_width = int(width * percentage) - if not opt_text: opt_text = f'{percentage*100:.1f}%' - - bar = fill * filled_width + empty * (width - filled_width) - bar = (bar[:-len(opt_text)] + opt_text) if opt_text else bar - bar = colored(bar[:filled_width], color) + bar[filled_width:] - return f'[{bar}]' - -def same_line(strs:list[list[str]|None], split=8) -> list[str]: - strs = [s for s in strs if s is not None] - if len(strs) == 0: return [] - - ret = [] - max_width_in_block = [max(ansilen(line) for line in block) for block in strs] - max_height = max(len(block) for block in strs) - for i in range(max_height): - line = [] - for bid, block in enumerate(strs): - if i < len(block): line.append(block[i] + (' ' * (split + max_width_in_block[bid] - ansilen(block[i])) if bid != len(strs) - 1 else '')) - else: line.append(' ' * (split + max_width_in_block[bid])) - ret.append(' '.join(line)) - return ret - -def get_bar0_size(pcibus): - resource_file = f"/sys/bus/pci/devices/{pcibus}/resource" - if not os.path.exists(resource_file): raise FileNotFoundError(f"Resource file not found: {resource_file}") - - with open(resource_file, "r") as f: lines = f.readlines() - bar0_info = lines[0].split() - if len(bar0_info) < 3: raise ValueError("Unexpected resource file format for BAR0.") - - start_hex, end_hex, _flags = bar0_info - return int(end_hex, 16) - int(start_hex, 16) + 1 - -class AMSMI(AMDev): - def __init__(self, pcibus, vram_bar:MMIOInterface, doorbell_bar:MMIOInterface, mmio_bar:MMIOInterface): - self.pcibus = pcibus - self.vram, self.doorbell64, self.mmio, self.dma_regions = vram_bar, doorbell_bar, mmio_bar, None - self.pci_state = self.read_pci_state() - if self.pci_state == "D0": self._init_from_d0() - - def _init_from_d0(self): - self._run_discovery() - self._build_regs() - - if self.reg("regSCRATCH_REG7").read() != AM_VERSION: - raise Exception(f"Unsupported AM version: {self.reg('regSCRATCH_REG7').read():x}") - - self.is_booting, self.smi_dev = True, True - self.partial_boot = True # do not init anything - self.mm = AMMemoryManager(self, self.vram_size) - - # Initialize IP blocks - self.soc:AM_SOC = AM_SOC(self) - self.gmc:AM_GMC = AM_GMC(self) - self.ih:AM_IH = AM_IH(self) - self.psp:AM_PSP = AM_PSP(self) - self.smu:AM_SMU = AM_SMU(self) - - for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu]: ip.init_sw() - - def read_pci_state(self): - with open(f"/sys/bus/pci/devices/{self.pcibus}/power_state", "r") as f: return f.read().strip().rstrip() - -class SMICtx: - def __init__(self): - self.devs = [] - self.opened_pcidevs = [] - self.opened_pci_resources = {} - self.prev_lines_cnt = 0 - self.prev_terminal_width = 0 - - remove_parts = ["Advanced Micro Devices, Inc. [AMD/ATI]", "VGA compatible controller:"] - lspci = subprocess.check_output(["lspci"]).decode("utf-8").splitlines() - self.lspci = {l.split()[0]: l.split(" ", 1)[1] for l in lspci} - for k,v in self.lspci.items(): - for part in remove_parts: self.lspci[k] = self.lspci[k].replace(part, "").strip().rstrip() - - def _open_am_device(self, pcibus): - if pcibus not in self.opened_pci_resources: - bar_fds = {bar: os.open(f"/sys/bus/pci/devices/{pcibus}/resource{bar}", os.O_RDWR | os.O_SYNC) for bar in [0, 2, 5]} - bar_size = {0: get_bar0_size(pcibus), 2: os.fstat(bar_fds[2]).st_size, 5: os.fstat(bar_fds[5]).st_size} - - def map_pci_range(bar, fmt='B'): - return MMIOInterface(libc.mmap(0, bar_size[bar], mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED, bar_fds[bar], 0), bar_size[bar], fmt) - self.opened_pci_resources[pcibus] = (map_pci_range(0), None, map_pci_range(5, 'I')) - - try: - self.devs.append(AMSMI(pcibus, *self.opened_pci_resources[pcibus])) - except Exception as e: - if DEBUG >= 2: print(f"Failed to open AM device {pcibus}: {e}") - return - - self.opened_pcidevs.append(pcibus) - if DEBUG >= 2: print(f"Opened AM device {pcibus}") - - def rescan_devs(self): - pattern = os.path.join('/tmp', 'am_*.lock') - for d in [f[8:-5] for f in glob.glob(pattern)]: - if d not in self.opened_pcidevs: - self._open_am_device(d) - - for d in self.devs: - if d.read_pci_state() != d.pci_state: - d.pci_state = d.read_pci_state() - if d.pci_state == "D0": d._init_from_d0() - os.system('clear') - - if d.pci_state == "D0" and d.reg("regSCRATCH_REG7").read() != AM_VERSION: - self.devs.remove(d) - self.opened_pcidevs.remove(d.pcibus) - os.system('clear') - if DEBUG >= 2: print(f"Removed AM device {d.pcibus}") - - def collect(self): return {d: d.smu.read_metrics() if d.pci_state == "D0" else None for d in self.devs} - - def get_gfx_activity(self, dev, metrics): return metrics.SmuMetrics.AverageGfxActivity - def get_mem_activity(self, dev, metrics): return metrics.SmuMetrics.AverageUclkActivity - - def get_temps(self, dev, metrics, compact=False): - temps_keys = [(k, name) for k, name in dev.smu.smu_mod.c__EA_TEMP_e__enumvalues.items() - if k < dev.smu.smu_mod.TEMP_COUNT and metrics.SmuMetrics.AvgTemperature[k] != 0] - if compact: temps_keys = [(k, name) for k, name in temps_keys if k in (dev.smu.smu_mod.TEMP_HOTSPOT, dev.smu.smu_mod.TEMP_MEM)] - return {name: metrics.SmuMetrics.AvgTemperature[k] for k, name in temps_keys} - - def get_voltage(self, dev, metrics, compact=False): - voltage_keys = [(k, name) for k, name in dev.smu.smu_mod.c__EA_SVI_PLANE_e__enumvalues.items() - if k < dev.smu.smu_mod.SVI_PLANE_COUNT and metrics.SmuMetrics.AvgVoltage[k] != 0] - return {name: metrics.SmuMetrics.AvgVoltage[k] for k, name in voltage_keys} - - def get_busy_threshold(self, dev): - match dev.ip_ver[am.MP1_HWIP]: - case (14, 0, 2): return 5 - case _: return 15 - - def get_gfx_freq(self, dev, metrics): - return metrics.SmuMetrics.AverageGfxclkFrequencyPostDs if self.get_gfx_activity(dev, metrics) <= self.get_busy_threshold(dev) else \ - metrics.SmuMetrics.AverageGfxclkFrequencyPreDs - - def get_mem_freq(self, dev, metrics): - return metrics.SmuMetrics.AverageMemclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \ - metrics.SmuMetrics.AverageMemclkFrequencyPreDs - - def get_fckl_freq(self, dev, metrics): - return metrics.SmuMetrics.AverageFclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \ - metrics.SmuMetrics.AverageFclkFrequencyPreDs - - def get_fan_rpm_pwm(self, dev, metrics): return metrics.SmuMetrics.AvgFanRpm, metrics.SmuMetrics.AvgFanPwm - - def get_power(self, dev, metrics): return metrics.SmuMetrics.AverageSocketPower, metrics.SmuMetrics.dGPU_W_MAX - - def get_mem_usage(self, dev): - usage = 0 - pt_stack = [dev.mm.root_page_table] - while len(pt_stack) > 0: - pt = pt_stack.pop() - for i in range(512): - entry = pt.entries[i] - - if (entry & am.AMDGPU_PTE_VALID) == 0: continue - if pt.lv!=am.AMDGPU_VM_PTB and not dev.gmc.is_pte_huge_page(entry): - pt_stack.append(AMPageTableEntry(dev, entry & 0x0000FFFFFFFFF000, lv=pt.lv+1)) - continue - if (entry & am.AMDGPU_PTE_SYSTEM) != 0: continue - usage += (1 << ((9 * (3-pt.lv)) + 12)) - return usage - - def draw(self, once): - terminal_width, terminal_height = shutil.get_terminal_size() - if not once and (self.prev_terminal_width != terminal_width or self.prev_terminal_height != terminal_height): - os.system('clear') - self.prev_terminal_width, self.prev_terminal_height = terminal_width, terminal_height - - padding = 8 - col_size = (terminal_width) // 2 - padding - 2 - activity_line_width = 50 if terminal_width > 170 else \ - (30 if terminal_width > 130 else \ - (16 if terminal_width > 92 else \ - max(0, terminal_width - 77))) - - dev_metrics = self.collect() - dev_content = [] - for dev, metrics in dev_metrics.items(): - if dev.pci_state != "D0": - dev_content.append([f"{colored('(sleep)', 'yellow')} {bold(dev.pcibus)}: {trim(self.lspci[dev.pcibus[5:]], col_size - 20)}"] + - [pad(f"PCI State: {dev.pci_state}", col_size)]) - continue - - mem_used = self.get_mem_usage(dev) - mem_total = dev.vram_size - mem_fmt = f"{mem_used/1024**3:.1f}/{mem_total/1024**3:.1f}G" - - device_line = [f"{bold(dev.pcibus)} {trim(self.lspci[dev.pcibus[5:]], col_size - 20)}"] + [pad("", col_size)] - activity_line = [f"GFX Activity {draw_bar(self.get_gfx_activity(dev, metrics) / 100, activity_line_width)}"] \ - + [f"MEM Activity {draw_bar(self.get_mem_activity(dev, metrics) / 100, activity_line_width)}"] \ - + [f"MEM Usage {draw_bar((mem_used / mem_total) / 100, activity_line_width, opt_text=mem_fmt)}"] \ - - temps_data, temps_data_compact = self.get_temps(dev, metrics), self.get_temps(dev, metrics, compact=True) - temps_table = ["=== Temps (°C) ==="] + [f"{name:<16}: {color_temp(val)}" for name, val in temps_data.items()] - temps_table_compact = ["Temps (°C):" + '/'.join([f"{color_temp(val)} {name}" for name, val in temps_data_compact.items()])] - - fan_rpm, fan_pwm = self.get_fan_rpm_pwm(dev, metrics) - power_table = ["=== Power ==="] + [f"Fan Speed: {fan_rpm} RPM"] + [f"Fan Power: {fan_pwm}%"] - - total_power, max_power = self.get_power(dev, metrics) - power_line = [f"Power: " + draw_bar(total_power / max_power, 16, opt_text=f"{total_power}/{max_power}W")] - power_line_compact = [f"Power: " + draw_bar(total_power / max_power, activity_line_width, opt_text=f"{total_power}/{max_power}W")] - - voltage_data = self.get_voltage(dev, metrics) - voltage_table = ["=== Voltages ==="] + [f"{name:<20}: {color_voltage(voltage)}" for name, voltage in voltage_data.items()] - - gfx_freq = self.get_gfx_freq(dev, metrics) - mclk_freq = self.get_mem_freq(dev, metrics) - fclk_freq = self.get_fckl_freq(dev, metrics) - - frequency_table = ["=== Frequencies ===", f"GFXCLK: {gfx_freq:>4} MHz", f"FCLK : {fclk_freq:>4} MHz", f"MCLK : {mclk_freq:>4} MHz"] - - if self.prev_terminal_width >= 231: - power_table += power_line + [""] + voltage_table - activity_line += [""] - elif self.prev_terminal_width >= 171: - power_table += power_line + [""] + frequency_table - activity_line += [""] - frequency_table = None - elif self.prev_terminal_width >= 121: - temps_table = None - activity_line += power_line_compact - else: - temps_table = None - power_table = None - frequency_table = None - activity_line += power_line_compact - - dev_content.append(device_line + activity_line + same_line([temps_table, power_table, frequency_table])) - - raw_text = 'AM Monitor'.center(terminal_width) + "\n" + "=" * terminal_width + "\n\n" - for i in range(0, len(dev_content), 2): - if i + 1 < len(dev_content): raw_text += '\n'.join(same_line([dev_content[i], dev_content[i+1]], split=padding)) - else: raw_text += '\n'.join(dev_content[i]) - if i + 2 < len(dev_content): raw_text += "\n" + "=" * terminal_width + "\n\n" - - sys.stdout.write(f'\033[{self.prev_lines_cnt}A') - sys.stdout.flush() - print(raw_text) - - self.prev_lines_cnt = len(raw_text.splitlines()) + 2 - -if __name__ == "__main__": - parser = argparse.ArgumentParser() - parser.add_argument("--list", action="store_true", help="Run once and exit") - parser.add_argument("--pids", action="store_true", help="Print pids for all AM devices") - parser.add_argument("--kill", action="store_true", help="Kill all pids associated with AM devices. Valid only with --pids") - parser.add_argument("--dev", type=str, default=None, help="PCI bus ID of the AM device to monitor (e.g., 0000:01:00.0)") - args = parser.parse_args() - - if args.pids: - for dev in glob.glob('/tmp/am_*.lock'): - if args.dev and not dev.endswith(f"{args.dev}.lock"): - print(f"{dev[8:-5]}: skipping") - continue - - try: - if args.kill: - stopped_pids = collections.defaultdict(int) - while True: - try: pid = subprocess.check_output(['sudo', 'lsof', '-t', dev]).decode('utf-8').split('\n')[0] - except subprocess.CalledProcessError: break - if stopped_pids[pid] > 0: time.sleep(0.5) - if stopped_pids[pid] == 10: - print(f"{dev[8:-5]}: can't stop process {pid}, exitting") - exit(1) - - print(f"{dev[8:-5]}: killing process {pid}") - os.system(f'sudo pkill -g -9 {pid}') - stopped_pids[pid] += 1 - else: - pid = subprocess.check_output(['sudo', 'lsof', dev]).decode('utf-8').strip().split('\n')[1].split()[1] - print(f"{dev[8:-5]}: {pid}") - except subprocess.CalledProcessError: - print(f"{dev[8:-5]}: no process found") - sys.exit(0) - - try: - if not args.list: os.system('clear') - smi_ctx = SMICtx() - while True: - smi_ctx.rescan_devs() - smi_ctx.draw(args.list) - if args.list: break - time.sleep(1) - except KeyboardInterrupt: print("Exiting...") diff --git a/tinygrad/extra/amdpci/headers/amdgpu_doorbell.h b/tinygrad/extra/amdpci/headers/amdgpu_doorbell.h deleted file mode 100644 index 47e27d20..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_doorbell.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef AMDGPU_DOORBELL_H -#define AMDGPU_DOORBELL_H - -enum AMDGPU_DOORBELL_ASSIGNMENT { - AMDGPU_DOORBELL_KIQ = 0x000, - AMDGPU_DOORBELL_HIQ = 0x001, - AMDGPU_DOORBELL_DIQ = 0x002, - AMDGPU_DOORBELL_MEC_RING0 = 0x010, - AMDGPU_DOORBELL_MEC_RING1 = 0x011, - AMDGPU_DOORBELL_MEC_RING2 = 0x012, - AMDGPU_DOORBELL_MEC_RING3 = 0x013, - AMDGPU_DOORBELL_MEC_RING4 = 0x014, - AMDGPU_DOORBELL_MEC_RING5 = 0x015, - AMDGPU_DOORBELL_MEC_RING6 = 0x016, - AMDGPU_DOORBELL_MEC_RING7 = 0x017, - AMDGPU_DOORBELL_GFX_RING0 = 0x020, - AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, - AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, - AMDGPU_DOORBELL_IH = 0x1E8, - AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, - AMDGPU_DOORBELL_INVALID = 0xFFFF -}; - -enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT { - - /* Compute + GFX: 0~255 */ - AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, - AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, - AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, - AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, - AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, - AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, - AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, - AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, - AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, - AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, - AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, - AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, - AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, - AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, - /* SDMA:256~335*/ - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, - AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, - /* IH: 376~391 */ - AMDGPU_VEGA20_DOORBELL_IH = 0x178, - /* MMSCH: 392~407 - * overlap the doorbell assignment with VCN as they are mutually exclusive - * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD - */ - AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ - AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, - AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, - AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, - - AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ - AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, - AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, - AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, - - AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, - AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, - AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, - AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, - - AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, - AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, - AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, - AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, - - AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, - AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, - - /* kiq/kcq from second XCD. Max 8 XCDs */ - AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190, - /* 8 compute rings per GC. Max to 0x1CE */ - AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197, - - /* AID1 SDMA: 0x1D0 ~ 0x1F7 */ - AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0, - - AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7, - AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF -}; - -enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT { - - /* Compute + GFX: 0~255 */ - AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, - AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, - AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, - AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, - AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, - AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, - AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, - AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, - AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, - AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, - AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, - AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, - AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, - AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, - AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, - AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, - AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, - AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, - AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, - - /* SDMA:256~335*/ - AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, - AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, - AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, - AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, - /* IH: 376~391 */ - AMDGPU_NAVI10_DOORBELL_IH = 0x178, - /* MMSCH: 392~407 - * overlap the doorbell assignment with VCN as they are mutually exclusive - * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD - */ - AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ - AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, - AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, - AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, - - AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, - AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, - AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, - AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, - - AMDGPU_NAVI10_DOORBELL64_VPE = 0x190, - - AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, - AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VPE, - - AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = AMDGPU_NAVI10_DOORBELL64_VPE, - AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF -}; - -/* - * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space - */ -enum AMDGPU_DOORBELL64_ASSIGNMENT { - /* - * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in - * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. - * Compute related doorbells are allocated from 0x00 to 0x8a - */ - - - /* kernel scheduling */ - AMDGPU_DOORBELL64_KIQ = 0x00, - - /* HSA interface queue and debug queue */ - AMDGPU_DOORBELL64_HIQ = 0x01, - AMDGPU_DOORBELL64_DIQ = 0x02, - - /* Compute engines */ - AMDGPU_DOORBELL64_MEC_RING0 = 0x03, - AMDGPU_DOORBELL64_MEC_RING1 = 0x04, - AMDGPU_DOORBELL64_MEC_RING2 = 0x05, - AMDGPU_DOORBELL64_MEC_RING3 = 0x06, - AMDGPU_DOORBELL64_MEC_RING4 = 0x07, - AMDGPU_DOORBELL64_MEC_RING5 = 0x08, - AMDGPU_DOORBELL64_MEC_RING6 = 0x09, - AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, - - /* User queue doorbell range (128 doorbells) */ - AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, - AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, - - /* Graphics engine */ - AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, - - /* - * Other graphics doorbells can be allocated here: from 0x8c to 0xdf - * Graphics voltage island aperture 1 - * default non-graphics QWORD index is 0xe0 - 0xFF inclusive - */ - - /* For vega10 sriov, the sdma doorbell must be fixed as follow - * to keep the same setting with host driver, or it will - * happen conflicts - */ - AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, - AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, - AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, - AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, - - /* Interrupt handler */ - AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ - AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ - AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ - - /* VCN engine use 32 bits doorbell */ - AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ - AMDGPU_DOORBELL64_VCN2_3 = 0xF9, - AMDGPU_DOORBELL64_VCN4_5 = 0xFA, - AMDGPU_DOORBELL64_VCN6_7 = 0xFB, - - /* overlap the doorbell assignment with VCN as they are mutually exclusive - * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD - */ - AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, - AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, - AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, - AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, - - AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, - AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, - AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, - AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, - - AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, - AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, - - AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, - AMDGPU_DOORBELL64_INVALID = 0xFFFF -}; - -enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { - - /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */ - - /* KIQ/HIQ/DIQ */ - AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000, - AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001, - AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002, - /* Compute: 0x08 ~ 0x20 */ - AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008, - AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F, - AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010, - AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F, - AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020, - - /* SDMA: 0x100 ~ 0x19F */ - AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100, - AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F, - /* IH: 0x1A0 ~ 0x1AF */ - AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0, - /* VCN: 0x1B0 ~ 0x1E8 */ - AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0, - AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8, - - AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START, - AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END, - - AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8, - AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF -}; - -#endif diff --git a/tinygrad/extra/amdpci/headers/amdgpu_irq.h b/tinygrad/extra/amdpci/headers/amdgpu_irq.h deleted file mode 100644 index f0c961e2..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_irq.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __AMDGPU_IRQ_H__ -#define __AMDGPU_IRQ_H__ - -// #include -// #include "soc15_ih_clientid.h" -// #include "amdgpu_ih.h" - -#define int32_t int -#define uint32_t unsigned int -#define int8_t signed char -#define uint8_t unsigned char -#define uint16_t unsigned short -#define int16_t short -#define uint64_t unsigned long long -#define bool _Bool -#define u32 unsigned int - -#define AMDGPU_MAX_IRQ_SRC_ID 0x100 -#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 - -#define AMDGPU_IRQ_CLIENTID_LEGACY 0 -#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX - -#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4 - -struct amdgpu_device; - -enum amdgpu_interrupt_state { - AMDGPU_IRQ_STATE_DISABLE, - AMDGPU_IRQ_STATE_ENABLE, -}; - -struct amdgpu_iv_entry { - // struct amdgpu_ih_ring *ih; - unsigned client_id; - unsigned src_id; - unsigned ring_id; - unsigned vmid; - unsigned vmid_src; - uint64_t timestamp; - unsigned timestamp_src; - unsigned pasid; - unsigned node_id; - unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW]; - const uint32_t *iv_entry; -}; - -enum interrupt_node_id_per_aid { - AID0_NODEID = 0, - XCD0_NODEID = 1, - XCD1_NODEID = 2, - AID1_NODEID = 4, - XCD2_NODEID = 5, - XCD3_NODEID = 6, - AID2_NODEID = 8, - XCD4_NODEID = 9, - XCD5_NODEID = 10, - AID3_NODEID = 12, - XCD6_NODEID = 13, - XCD7_NODEID = 14, - NODEID_MAX, -}; - -#endif diff --git a/tinygrad/extra/amdpci/headers/amdgpu_psp.h b/tinygrad/extra/amdpci/headers/amdgpu_psp.h deleted file mode 100644 index ae3d762c..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_psp.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Author: Huang Rui - * - */ -#ifndef __AMDGPU_PSP_H__ -#define __AMDGPU_PSP_H__ - -// #include "amdgpu.h" -// #include "psp_gfx_if.h" -// #include "ta_xgmi_if.h" -// #include "ta_ras_if.h" -// #include "ta_rap_if.h" -// #include "ta_secureDisplay_if.h" - -#define PSP_FENCE_BUFFER_SIZE 0x1000 -#define PSP_CMD_BUFFER_SIZE 0x1000 -#define PSP_1_MEG 0x100000 -#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) -#define PSP_TMR_ALIGNMENT 0x100000 -#define PSP_FW_NAME_LEN 0x24 - -// extern const struct attribute_group amdgpu_flash_attr_group; - -enum psp_shared_mem_size { - PSP_ASD_SHARED_MEM_SIZE = 0x0, - PSP_XGMI_SHARED_MEM_SIZE = 0x4000, - PSP_RAS_SHARED_MEM_SIZE = 0x4000, - PSP_HDCP_SHARED_MEM_SIZE = 0x4000, - PSP_DTM_SHARED_MEM_SIZE = 0x4000, - PSP_RAP_SHARED_MEM_SIZE = 0x4000, - PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, -}; - -enum ta_type_id { - TA_TYPE_XGMI = 1, - TA_TYPE_RAS, - TA_TYPE_HDCP, - TA_TYPE_DTM, - TA_TYPE_RAP, - TA_TYPE_SECUREDISPLAY, - - TA_TYPE_MAX_INDEX, -}; - -struct psp_context; -struct psp_xgmi_node_info; -struct psp_xgmi_topology_info; -struct psp_bin_desc; - -enum psp_bootloader_cmd { - PSP_BL__LOAD_SYSDRV = 0x10000, - PSP_BL__LOAD_SOSDRV = 0x20000, - PSP_BL__LOAD_KEY_DATABASE = 0x80000, - PSP_BL__LOAD_SOCDRV = 0xB0000, - PSP_BL__LOAD_DBGDRV = 0xC0000, - PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, - PSP_BL__LOAD_INTFDRV = 0xD0000, - PSP_BL__LOAD_RASDRV = 0xE0000, - PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, - PSP_BL__DRAM_LONG_TRAIN = 0x100000, - PSP_BL__DRAM_SHORT_TRAIN = 0x200000, - PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, -}; - -enum psp_ring_type { - PSP_RING_TYPE__INVALID = 0, - /* - * These values map to the way the PSP kernel identifies the - * rings. - */ - PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ - PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ -}; - -// struct psp_ring { -// enum psp_ring_type ring_type; -// struct psp_gfx_rb_frame *ring_mem; -// uint64_t ring_mem_mc_addr; -// void *ring_mem_handle; -// uint32_t ring_size; -// uint32_t ring_wptr; -// }; - -/* More registers may will be supported */ -enum psp_reg_prog_id { - PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ - PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ - PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ - PSP_REG_LAST -}; - -// struct psp_funcs { -// int (*init_microcode)(struct psp_context *psp); -// int (*wait_for_bootloader)(struct psp_context *psp); -// int (*bootloader_load_kdb)(struct psp_context *psp); -// int (*bootloader_load_spl)(struct psp_context *psp); -// int (*bootloader_load_sysdrv)(struct psp_context *psp); -// int (*bootloader_load_soc_drv)(struct psp_context *psp); -// int (*bootloader_load_intf_drv)(struct psp_context *psp); -// int (*bootloader_load_dbg_drv)(struct psp_context *psp); -// int (*bootloader_load_ras_drv)(struct psp_context *psp); -// int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); -// int (*bootloader_load_sos)(struct psp_context *psp); -// int (*ring_create)(struct psp_context *psp, -// enum psp_ring_type ring_type); -// int (*ring_stop)(struct psp_context *psp, -// enum psp_ring_type ring_type); -// int (*ring_destroy)(struct psp_context *psp, -// enum psp_ring_type ring_type); -// bool (*smu_reload_quirk)(struct psp_context *psp); -// int (*mode1_reset)(struct psp_context *psp); -// int (*mem_training)(struct psp_context *psp, uint32_t ops); -// uint32_t (*ring_get_wptr)(struct psp_context *psp); -// void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); -// int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); -// int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); -// int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); -// int (*vbflash_stat)(struct psp_context *psp); -// int (*fatal_error_recovery_quirk)(struct psp_context *psp); -// bool (*get_ras_capability)(struct psp_context *psp); -// bool (*is_aux_sos_load_required)(struct psp_context *psp); -// }; - -// struct ta_funcs { -// int (*fn_ta_initialize)(struct psp_context *psp); -// int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); -// int (*fn_ta_terminate)(struct psp_context *psp); -// }; - -#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 -// struct psp_xgmi_node_info { -// uint64_t node_id; -// uint8_t num_hops; -// uint8_t is_sharing_enabled; -// enum ta_xgmi_assigned_sdma_engine sdma_engine; -// uint8_t num_links; -// struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; -// }; - -// struct psp_xgmi_topology_info { -// uint32_t num_nodes; -// struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; -// }; - -// struct psp_bin_desc { -// uint32_t fw_version; -// uint32_t feature_version; -// uint32_t size_bytes; -// uint8_t *start_addr; -// }; - -// struct ta_mem_context { -// struct amdgpu_bo *shared_bo; -// uint64_t shared_mc_addr; -// void *shared_buf; -// enum psp_shared_mem_size shared_mem_size; -// }; - -// struct ta_context { -// bool initialized; -// uint32_t session_id; -// uint32_t resp_status; -// struct ta_mem_context mem_context; -// struct psp_bin_desc bin_desc; -// enum psp_gfx_cmd_id ta_load_type; -// enum ta_type_id ta_type; -// }; - -// struct ta_cp_context { -// struct ta_context context; -// struct mutex mutex; -// }; - -// struct psp_xgmi_context { -// struct ta_context context; -// struct psp_xgmi_topology_info top_info; -// bool supports_extended_data; -// uint8_t xgmi_ta_caps; -// }; - -// struct psp_ras_context { -// struct ta_context context; -// struct amdgpu_ras *ras; -// }; - -#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 -#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 -#define GDDR6_MEM_TRAINING_OFFSET 0x8000 -/*Define the VRAM size that will be encroached by BIST training.*/ -#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 - -enum psp_memory_training_init_flag { - PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, - PSP_MEM_TRAIN_SUPPORT = 0x1, - PSP_MEM_TRAIN_INIT_FAILED = 0x2, - PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, - PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, -}; - -enum psp_memory_training_ops { - PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, - PSP_MEM_TRAIN_SAVE = 0x2, - PSP_MEM_TRAIN_RESTORE = 0x4, - PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, - PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, - PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, -}; - -// struct psp_memory_training_context { -// /*training data size*/ -// u64 train_data_size; -// /* -// * sys_cache -// * cpu virtual address -// * system memory buffer that used to store the training data. -// */ -// void *sys_cache; - -// /*vram offset of the p2c training data*/ -// u64 p2c_train_data_offset; - -// /*vram offset of the c2p training data*/ -// u64 c2p_train_data_offset; -// struct amdgpu_bo *c2p_bo; - -// enum psp_memory_training_init_flag init; -// u32 training_cnt; -// bool enable_mem_training; -// }; - -/** PSP runtime DB **/ -#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 -#define PSP_RUNTIME_DB_OFFSET 0x100000 -#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 -#define PSP_RUNTIME_DB_VER_1 0x0100 -#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 - -enum psp_runtime_entry_type { - PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, - PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, - PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ - PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ - PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ - PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ - PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ -}; - -/* PSP runtime DB header */ -// struct psp_runtime_data_header { -// /* determine the existence of runtime db */ -// uint16_t cookie; -// /* version of runtime db */ -// uint16_t version; -// }; - -// /* PSP runtime DB entry */ -// struct psp_runtime_entry { -// /* type of runtime db entry */ -// uint32_t entry_type; -// /* offset of entry in bytes */ -// uint16_t offset; -// /* size of entry in bytes */ -// uint16_t size; -// }; - -// /* PSP runtime DB directory */ -// struct psp_runtime_data_directory { -// /* number of valid entries */ -// uint16_t entry_count; -// /* db entries*/ -// struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; -// }; - -/* PSP runtime DB boot config feature bitmask */ -enum psp_runtime_boot_cfg_feature { - BOOT_CFG_FEATURE_GECC = 0x1, - BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, -}; - -/* PSP run time DB SCPM authentication defines */ -enum psp_runtime_scpm_authentication { - SCPM_DISABLE = 0x0, - SCPM_ENABLE = 0x1, - SCPM_ENABLE_WITH_SCPM_ERR = 0x2, -}; - -/* PSP runtime DB boot config entry */ -// struct psp_runtime_boot_cfg_entry { -// uint32_t boot_cfg_bitmask; -// uint32_t reserved; -// }; - -// /* PSP runtime DB SCPM entry */ -// struct psp_runtime_scpm_entry { -// enum psp_runtime_scpm_authentication scpm_status; -// }; - -// struct psp_context { -// struct amdgpu_device *adev; -// struct psp_ring km_ring; -// struct psp_gfx_cmd_resp *cmd; - -// const struct psp_funcs *funcs; -// const struct ta_funcs *ta_funcs; - -// /* firmware buffer */ -// struct amdgpu_bo *fw_pri_bo; -// uint64_t fw_pri_mc_addr; -// void *fw_pri_buf; - -// /* sos firmware */ -// const struct firmware *sos_fw; -// struct psp_bin_desc sys; -// struct psp_bin_desc sos; -// struct psp_bin_desc toc; -// struct psp_bin_desc kdb; -// struct psp_bin_desc spl; -// struct psp_bin_desc rl; -// struct psp_bin_desc soc_drv; -// struct psp_bin_desc intf_drv; -// struct psp_bin_desc dbg_drv; -// struct psp_bin_desc ras_drv; -// struct psp_bin_desc ipkeymgr_drv; - -// /* tmr buffer */ -// struct amdgpu_bo *tmr_bo; -// uint64_t tmr_mc_addr; - -// /* asd firmware */ -// const struct firmware *asd_fw; - -// /* toc firmware */ -// const struct firmware *toc_fw; - -// /* cap firmware */ -// const struct firmware *cap_fw; - -// /* fence buffer */ -// struct amdgpu_bo *fence_buf_bo; -// uint64_t fence_buf_mc_addr; -// void *fence_buf; - -// /* cmd buffer */ -// struct amdgpu_bo *cmd_buf_bo; -// uint64_t cmd_buf_mc_addr; -// struct psp_gfx_cmd_resp *cmd_buf_mem; - -// /* fence value associated with cmd buffer */ -// atomic_t fence_value; -// /* flag to mark whether gfx fw autoload is supported or not */ -// bool autoload_supported; -// /* flag to mark whether psp use runtime TMR or boottime TMR */ -// bool boot_time_tmr; -// /* flag to mark whether df cstate management centralized to PMFW */ -// bool pmfw_centralized_cstate_management; - -// /* xgmi ta firmware and buffer */ -// const struct firmware *ta_fw; -// uint32_t ta_fw_version; - -// uint32_t cap_fw_version; -// uint32_t cap_feature_version; -// uint32_t cap_ucode_size; - -// struct ta_context asd_context; -// struct psp_xgmi_context xgmi_context; -// struct psp_ras_context ras_context; -// struct ta_cp_context hdcp_context; -// struct ta_cp_context dtm_context; -// struct ta_cp_context rap_context; -// struct ta_cp_context securedisplay_context; -// struct mutex mutex; -// struct psp_memory_training_context mem_train_ctx; - -// uint32_t boot_cfg_bitmask; - -// /* firmware upgrades supported */ -// bool sup_pd_fw_up; -// bool sup_ifwi_up; - -// char *vbflash_tmp_buf; -// size_t vbflash_image_size; -// bool vbflash_done; -// }; - -// struct amdgpu_psp_funcs { -// bool (*check_fw_loading_status)(struct amdgpu_device *adev, -// enum AMDGPU_UCODE_ID); -// }; - - -// #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) -// #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) -// #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) -// #define psp_init_microcode(psp) \ -// ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) -// #define psp_bootloader_load_kdb(psp) \ -// ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) -// #define psp_bootloader_load_spl(psp) \ -// ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) -// #define psp_bootloader_load_sysdrv(psp) \ -// ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) -// #define psp_bootloader_load_soc_drv(psp) \ -// ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) -// #define psp_bootloader_load_intf_drv(psp) \ -// ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) -// #define psp_bootloader_load_dbg_drv(psp) \ -// ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) -// #define psp_bootloader_load_ras_drv(psp) \ -// ((psp)->funcs->bootloader_load_ras_drv ? \ -// (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) -// #define psp_bootloader_load_ipkeymgr_drv(psp) \ -// ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ -// (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) -// #define psp_bootloader_load_sos(psp) \ -// ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) -// #define psp_smu_reload_quirk(psp) \ -// ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) -// #define psp_mode1_reset(psp) \ -// ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) -// #define psp_mem_training(psp, ops) \ -// ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) - -// #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) -// #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) - -// #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ -// ((psp)->funcs->load_usbc_pd_fw ? \ -// (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) - -// #define psp_read_usbc_pd_fw(psp, fw_ver) \ -// ((psp)->funcs->read_usbc_pd_fw ? \ -// (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) - -// #define psp_update_spirom(psp, fw_pri_mc_addr) \ -// ((psp)->funcs->update_spirom ? \ -// (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) - -// #define psp_vbflash_status(psp) \ -// ((psp)->funcs->vbflash_stat ? \ -// (psp)->funcs->vbflash_stat((psp)) : -EINVAL) - -// #define psp_fatal_error_recovery_quirk(psp) \ -// ((psp)->funcs->fatal_error_recovery_quirk ? \ -// (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) - -// #define psp_is_aux_sos_load_required(psp) \ -// ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) - -// extern const struct amd_ip_funcs psp_ip_funcs; - -// extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; -// extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; -// extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; -// extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; -// extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; -// extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; -// extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; -// extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; - -// extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, -// uint32_t field_val, uint32_t mask, bool check_changed); -// extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, -// uint32_t field_val, uint32_t mask, uint32_t msec_timeout); - -// int psp_execute_ip_fw_load(struct psp_context *psp, -// struct amdgpu_firmware_info *ucode); - -// int psp_gpu_reset(struct amdgpu_device *adev); - -// int psp_ta_init_shared_buf(struct psp_context *psp, -// struct ta_mem_context *mem_ctx); -// void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); -// int psp_ta_unload(struct psp_context *psp, struct ta_context *context); -// int psp_ta_load(struct psp_context *psp, struct ta_context *context); -// int psp_ta_invoke(struct psp_context *psp, -// uint32_t ta_cmd_id, -// struct ta_context *context); - -// int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); -// int psp_xgmi_terminate(struct psp_context *psp); -// int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); -// int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); -// int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); -// int psp_xgmi_get_topology_info(struct psp_context *psp, -// int number_devices, -// struct psp_xgmi_topology_info *topology, -// bool get_extended_data); -// int psp_xgmi_set_topology_info(struct psp_context *psp, -// int number_devices, -// struct psp_xgmi_topology_info *topology); -// int psp_ras_initialize(struct psp_context *psp); -// int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); -// int psp_ras_enable_features(struct psp_context *psp, -// union ta_ras_cmd_input *info, bool enable); -// int psp_ras_trigger_error(struct psp_context *psp, -// struct ta_ras_trigger_error_input *info, uint32_t instance_mask); -// int psp_ras_terminate(struct psp_context *psp); -// int psp_ras_query_address(struct psp_context *psp, -// struct ta_ras_query_address_input *addr_in, -// struct ta_ras_query_address_output *addr_out); - -// int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); -// int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); -// int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); -// int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); - -// int psp_rlc_autoload_start(struct psp_context *psp); - -// int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, -// uint32_t value); -// int psp_ring_cmd_submit(struct psp_context *psp, -// uint64_t cmd_buf_mc_addr, -// uint64_t fence_mc_addr, -// int index); -// int psp_init_asd_microcode(struct psp_context *psp, -// const char *chip_name); -// int psp_init_toc_microcode(struct psp_context *psp, -// const char *chip_name); -// int psp_init_sos_microcode(struct psp_context *psp, -// const char *chip_name); -// int psp_init_ta_microcode(struct psp_context *psp, -// const char *chip_name); -// int psp_init_cap_microcode(struct psp_context *psp, -// const char *chip_name); -// int psp_get_fw_attestation_records_addr(struct psp_context *psp, -// uint64_t *output_ptr); - -// int psp_load_fw_list(struct psp_context *psp, -// struct amdgpu_firmware_info **ucode_list, int ucode_count); -// void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); - -// int psp_spatial_partition(struct psp_context *psp, int mode); - -// int is_psp_fw_valid(struct psp_bin_desc bin); - -// int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); -// bool amdgpu_psp_get_ras_capability(struct psp_context *psp); -#endif diff --git a/tinygrad/extra/amdpci/headers/amdgpu_smu.h b/tinygrad/extra/amdpci/headers/amdgpu_smu.h deleted file mode 100644 index 51b82278..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_smu.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef __AMDGPU_SMU_H__ -#define __AMDGPU_SMU_H__ - -#define int32_t int -#define uint32_t unsigned int -#define int8_t signed char -#define uint8_t unsigned char -#define uint16_t unsigned short -#define int16_t short -#define uint64_t unsigned long long -#define bool _Bool -#define u32 unsigned int - -#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 -#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 -#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 -#define SMU_FW_NAME_LEN 0x24 - -#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) -#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) -#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) - -// Power Throttlers -#define SMU_THROTTLER_PPT0_BIT 0 -#define SMU_THROTTLER_PPT1_BIT 1 -#define SMU_THROTTLER_PPT2_BIT 2 -#define SMU_THROTTLER_PPT3_BIT 3 -#define SMU_THROTTLER_SPL_BIT 4 -#define SMU_THROTTLER_FPPT_BIT 5 -#define SMU_THROTTLER_SPPT_BIT 6 -#define SMU_THROTTLER_SPPT_APU_BIT 7 - -// Current Throttlers -#define SMU_THROTTLER_TDC_GFX_BIT 16 -#define SMU_THROTTLER_TDC_SOC_BIT 17 -#define SMU_THROTTLER_TDC_MEM_BIT 18 -#define SMU_THROTTLER_TDC_VDD_BIT 19 -#define SMU_THROTTLER_TDC_CVIP_BIT 20 -#define SMU_THROTTLER_EDC_CPU_BIT 21 -#define SMU_THROTTLER_EDC_GFX_BIT 22 -#define SMU_THROTTLER_APCC_BIT 23 - -// Temperature -#define SMU_THROTTLER_TEMP_GPU_BIT 32 -#define SMU_THROTTLER_TEMP_CORE_BIT 33 -#define SMU_THROTTLER_TEMP_MEM_BIT 34 -#define SMU_THROTTLER_TEMP_EDGE_BIT 35 -#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 -#define SMU_THROTTLER_TEMP_SOC_BIT 37 -#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 -#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 -#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 -#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 -#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 -#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 -#define SMU_THROTTLER_VRHOT0_BIT 44 -#define SMU_THROTTLER_VRHOT1_BIT 45 -#define SMU_THROTTLER_PROCHOT_CPU_BIT 46 -#define SMU_THROTTLER_PROCHOT_GFX_BIT 47 - -// Other -#define SMU_THROTTLER_PPM_BIT 56 -#define SMU_THROTTLER_FIT_BIT 57 - -struct smu_hw_power_state { - unsigned int magic; -}; - -struct smu_power_state; - -enum smu_state_ui_label { - SMU_STATE_UI_LABEL_NONE, - SMU_STATE_UI_LABEL_BATTERY, - SMU_STATE_UI_TABEL_MIDDLE_LOW, - SMU_STATE_UI_LABEL_BALLANCED, - SMU_STATE_UI_LABEL_MIDDLE_HIGHT, - SMU_STATE_UI_LABEL_PERFORMANCE, - SMU_STATE_UI_LABEL_BACO, -}; - -enum smu_state_classification_flag { - SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, - SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, - SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, - SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, - SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, - SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, - SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, - SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, - SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, - SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, - SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, - SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, - SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, - SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, - SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, - SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, - SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, - SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, - SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, - SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, - SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, -}; - -struct smu_state_classification_block { - enum smu_state_ui_label ui_label; - enum smu_state_classification_flag flags; - int bios_index; - bool temporary_state; - bool to_be_deleted; -}; - -struct smu_state_pcie_block { - unsigned int lanes; -}; - -enum smu_refreshrate_source { - SMU_REFRESHRATE_SOURCE_EDID, - SMU_REFRESHRATE_SOURCE_EXPLICIT -}; - -struct smu_state_display_block { - bool disable_frame_modulation; - bool limit_refreshrate; - enum smu_refreshrate_source refreshrate_source; - int explicit_refreshrate; - int edid_refreshrate_index; - bool enable_vari_bright; -}; - -struct smu_state_memory_block { - bool dll_off; - uint8_t m3arb; - uint8_t unused[3]; -}; - -struct smu_state_software_algorithm_block { - bool disable_load_balancing; - bool enable_sleep_for_timestamps; -}; - -struct smu_temperature_range { - int min; - int max; - int edge_emergency_max; - int hotspot_min; - int hotspot_crit_max; - int hotspot_emergency_max; - int mem_min; - int mem_crit_max; - int mem_emergency_max; - int software_shutdown_temp; - int software_shutdown_temp_offset; -}; - -struct smu_state_validation_block { - bool single_display_only; - bool disallow_on_dc; - uint8_t supported_power_levels; -}; - -struct smu_uvd_clocks { - uint32_t vclk; - uint32_t dclk; -}; - -/** -* Structure to hold a SMU Power State. -*/ - -enum smu_power_src_type { - SMU_POWER_SOURCE_AC, - SMU_POWER_SOURCE_DC, - SMU_POWER_SOURCE_COUNT, -}; - -enum smu_ppt_limit_type { - SMU_DEFAULT_PPT_LIMIT = 0, - SMU_FAST_PPT_LIMIT, -}; - -enum smu_ppt_limit_level { - SMU_PPT_LIMIT_MIN = -1, - SMU_PPT_LIMIT_CURRENT, - SMU_PPT_LIMIT_DEFAULT, - SMU_PPT_LIMIT_MAX, -}; - -enum smu_memory_pool_size { - SMU_MEMORY_POOL_SIZE_ZERO = 0, - SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, - SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, - SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, - SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, -}; - -enum smu_clk_type { - SMU_GFXCLK, - SMU_VCLK, - SMU_DCLK, - SMU_VCLK1, - SMU_DCLK1, - SMU_ECLK, - SMU_SOCCLK, - SMU_UCLK, - SMU_DCEFCLK, - SMU_DISPCLK, - SMU_PIXCLK, - SMU_PHYCLK, - SMU_FCLK, - SMU_SCLK, - SMU_MCLK, - SMU_PCIE, - SMU_LCLK, - SMU_OD_CCLK, - SMU_OD_SCLK, - SMU_OD_MCLK, - SMU_OD_VDDC_CURVE, - SMU_OD_RANGE, - SMU_OD_VDDGFX_OFFSET, - SMU_OD_FAN_CURVE, - SMU_OD_ACOUSTIC_LIMIT, - SMU_OD_ACOUSTIC_TARGET, - SMU_OD_FAN_TARGET_TEMPERATURE, - SMU_OD_FAN_MINIMUM_PWM, - SMU_CLK_COUNT, -}; - -struct smu_user_dpm_profile { - uint32_t fan_mode; - uint32_t power_limit; - uint32_t fan_speed_pwm; - uint32_t fan_speed_rpm; - uint32_t flags; - uint32_t user_od; - - /* user clock state information */ - uint32_t clk_mask[SMU_CLK_COUNT]; - uint32_t clk_dependency; -}; - -#define SMU_TABLE_INIT(tables, table_id, s, a, d) \ - do { \ - tables[table_id].size = s; \ - tables[table_id].align = a; \ - tables[table_id].domain = d; \ - } while (0) - -struct smu_table { - uint64_t size; - uint32_t align; - uint8_t domain; - uint64_t mc_address; - void *cpu_addr; - struct amdgpu_bo *bo; - uint32_t version; -}; - -enum smu_perf_level_designation { - PERF_LEVEL_ACTIVITY, - PERF_LEVEL_POWER_CONTAINMENT, -}; - -struct smu_performance_level { - uint32_t core_clock; - uint32_t memory_clock; - uint32_t vddc; - uint32_t vddci; - uint32_t non_local_mem_freq; - uint32_t non_local_mem_width; -}; - -struct smu_clock_info { - uint32_t min_mem_clk; - uint32_t max_mem_clk; - uint32_t min_eng_clk; - uint32_t max_eng_clk; - uint32_t min_bus_bandwidth; - uint32_t max_bus_bandwidth; -}; - -struct smu_bios_boot_up_values { - uint32_t revision; - uint32_t gfxclk; - uint32_t uclk; - uint32_t socclk; - uint32_t dcefclk; - uint32_t eclk; - uint32_t vclk; - uint32_t dclk; - uint16_t vddc; - uint16_t vddci; - uint16_t mvddc; - uint16_t vdd_gfx; - uint8_t cooling_id; - uint32_t pp_table_id; - uint32_t format_revision; - uint32_t content_revision; - uint32_t fclk; - uint32_t lclk; - uint32_t firmware_caps; -}; - -enum smu_table_id { - SMU_TABLE_PPTABLE = 0, - SMU_TABLE_WATERMARKS, - SMU_TABLE_CUSTOM_DPM, - SMU_TABLE_DPMCLOCKS, - SMU_TABLE_AVFS, - SMU_TABLE_AVFS_PSM_DEBUG, - SMU_TABLE_AVFS_FUSE_OVERRIDE, - SMU_TABLE_PMSTATUSLOG, - SMU_TABLE_SMU_METRICS, - SMU_TABLE_DRIVER_SMU_CONFIG, - SMU_TABLE_ACTIVITY_MONITOR_COEFF, - SMU_TABLE_OVERDRIVE, - SMU_TABLE_I2C_COMMANDS, - SMU_TABLE_PACE, - SMU_TABLE_ECCINFO, - SMU_TABLE_COMBO_PPTABLE, - SMU_TABLE_WIFIBAND, - SMU_TABLE_COUNT, -}; - - -#endif diff --git a/tinygrad/extra/amdpci/headers/amdgpu_ucode.h b/tinygrad/extra/amdpci/headers/amdgpu_ucode.h deleted file mode 100644 index 8f8d0249..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_ucode.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright 2012 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __AMDGPU_UCODE_H__ -#define __AMDGPU_UCODE_H__ - -// #include "amdgpu_socbb.h" -#define int32_t int -#define uint32_t unsigned int -#define int8_t signed char -#define uint8_t unsigned char -#define uint16_t unsigned short -#define int16_t short -#define uint64_t unsigned long long -#define bool _Bool -#define u32 unsigned int - -struct common_firmware_header { - uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ - uint32_t header_size_bytes; /* size of just the header in bytes */ - uint16_t header_version_major; /* header version */ - uint16_t header_version_minor; /* header version */ - uint16_t ip_version_major; /* IP version */ - uint16_t ip_version_minor; /* IP version */ - uint32_t ucode_version; - uint32_t ucode_size_bytes; /* size of ucode in bytes */ - uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ - uint32_t crc32; /* crc32 checksum of the payload */ -}; - -/* version_major=1, version_minor=0 */ -struct mc_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t io_debug_size_bytes; /* size of debug array in dwords */ - uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ -}; - -/* version_major=1, version_minor=0 */ -struct smc_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t ucode_start_addr; -}; - -/* version_major=2, version_minor=0 */ -struct smc_firmware_header_v2_0 { - struct smc_firmware_header_v1_0 v1_0; - uint32_t ppt_offset_bytes; /* soft pptable offset */ - uint32_t ppt_size_bytes; /* soft pptable size */ -}; - -struct smc_soft_pptable_entry { - uint32_t id; - uint32_t ppt_offset_bytes; - uint32_t ppt_size_bytes; -}; - -/* version_major=2, version_minor=1 */ -struct smc_firmware_header_v2_1 { - struct smc_firmware_header_v1_0 v1_0; - uint32_t pptable_count; - uint32_t pptable_entry_offset; -}; - -struct psp_fw_legacy_bin_desc { - uint32_t fw_version; - uint32_t offset_bytes; - uint32_t size_bytes; -}; - -/* version_major=1, version_minor=0 */ -struct psp_firmware_header_v1_0 { - struct common_firmware_header header; - struct psp_fw_legacy_bin_desc sos; -}; - -/* version_major=1, version_minor=1 */ -struct psp_firmware_header_v1_1 { - struct psp_firmware_header_v1_0 v1_0; - struct psp_fw_legacy_bin_desc toc; - struct psp_fw_legacy_bin_desc kdb; -}; - -/* version_major=1, version_minor=2 */ -struct psp_firmware_header_v1_2 { - struct psp_firmware_header_v1_0 v1_0; - struct psp_fw_legacy_bin_desc res; - struct psp_fw_legacy_bin_desc kdb; -}; - -/* version_major=1, version_minor=3 */ -struct psp_firmware_header_v1_3 { - struct psp_firmware_header_v1_1 v1_1; - struct psp_fw_legacy_bin_desc spl; - struct psp_fw_legacy_bin_desc rl; - struct psp_fw_legacy_bin_desc sys_drv_aux; - struct psp_fw_legacy_bin_desc sos_aux; -}; - -struct psp_fw_bin_desc { - uint32_t fw_type; - uint32_t fw_version; - uint32_t offset_bytes; - uint32_t size_bytes; -}; - -enum psp_fw_type { - PSP_FW_TYPE_UNKOWN, - PSP_FW_TYPE_PSP_SOS, - PSP_FW_TYPE_PSP_SYS_DRV, - PSP_FW_TYPE_PSP_KDB, - PSP_FW_TYPE_PSP_TOC, - PSP_FW_TYPE_PSP_SPL, - PSP_FW_TYPE_PSP_RL, - PSP_FW_TYPE_PSP_SOC_DRV, - PSP_FW_TYPE_PSP_INTF_DRV, - PSP_FW_TYPE_PSP_DBG_DRV, - PSP_FW_TYPE_PSP_RAS_DRV, - PSP_FW_TYPE_PSP_IPKEYMGR_DRV, - PSP_FW_TYPE_MAX_INDEX, -}; - -/* version_major=2, version_minor=0 */ -struct psp_firmware_header_v2_0 { - struct common_firmware_header header; - uint32_t psp_fw_bin_count; - struct psp_fw_bin_desc psp_fw_bin[1]; -}; - -/* version_major=2, version_minor=1 */ -struct psp_firmware_header_v2_1 { - struct common_firmware_header header; - uint32_t psp_fw_bin_count; - uint32_t psp_aux_fw_bin_index; - struct psp_fw_bin_desc psp_fw_bin[1]; -}; - -/* version_major=1, version_minor=0 */ -struct ta_firmware_header_v1_0 { - struct common_firmware_header header; - struct psp_fw_legacy_bin_desc xgmi; - struct psp_fw_legacy_bin_desc ras; - struct psp_fw_legacy_bin_desc hdcp; - struct psp_fw_legacy_bin_desc dtm; - struct psp_fw_legacy_bin_desc securedisplay; -}; - -enum ta_fw_type { - TA_FW_TYPE_UNKOWN, - TA_FW_TYPE_PSP_ASD, - TA_FW_TYPE_PSP_XGMI, - TA_FW_TYPE_PSP_RAS, - TA_FW_TYPE_PSP_HDCP, - TA_FW_TYPE_PSP_DTM, - TA_FW_TYPE_PSP_RAP, - TA_FW_TYPE_PSP_SECUREDISPLAY, - TA_FW_TYPE_MAX_INDEX, -}; - -/* version_major=2, version_minor=0 */ -struct ta_firmware_header_v2_0 { - struct common_firmware_header header; - uint32_t ta_fw_bin_count; - struct psp_fw_bin_desc ta_fw_bin[1]; -}; - -/* version_major=1, version_minor=0 */ -struct gfx_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t jt_offset; /* jt location */ - uint32_t jt_size; /* size of jt */ -}; - -/* version_major=2, version_minor=0 */ -struct gfx_firmware_header_v2_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t ucode_size_bytes; - uint32_t ucode_offset_bytes; - uint32_t data_size_bytes; - uint32_t data_offset_bytes; - uint32_t ucode_start_addr_lo; - uint32_t ucode_start_addr_hi; -}; - -/* version_major=1, version_minor=0 */ -struct mes_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t mes_ucode_version; - uint32_t mes_ucode_size_bytes; - uint32_t mes_ucode_offset_bytes; - uint32_t mes_ucode_data_version; - uint32_t mes_ucode_data_size_bytes; - uint32_t mes_ucode_data_offset_bytes; - uint32_t mes_uc_start_addr_lo; - uint32_t mes_uc_start_addr_hi; - uint32_t mes_data_start_addr_lo; - uint32_t mes_data_start_addr_hi; -}; - -/* version_major=1, version_minor=0 */ -struct rlc_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t save_and_restore_offset; - uint32_t clear_state_descriptor_offset; - uint32_t avail_scratch_ram_locations; - uint32_t master_pkt_description_offset; -}; - -/* version_major=2, version_minor=0 */ -struct rlc_firmware_header_v2_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t jt_offset; /* jt location */ - uint32_t jt_size; /* size of jt */ - uint32_t save_and_restore_offset; - uint32_t clear_state_descriptor_offset; - uint32_t avail_scratch_ram_locations; - uint32_t reg_restore_list_size; - uint32_t reg_list_format_start; - uint32_t reg_list_format_separate_start; - uint32_t starting_offsets_start; - uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ - uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ - uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ - uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ - uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ - uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ - uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ - uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ -}; - -/* version_major=2, version_minor=1 */ -struct rlc_firmware_header_v2_1 { - struct rlc_firmware_header_v2_0 v2_0; - uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ - uint32_t save_restore_list_cntl_ucode_ver; - uint32_t save_restore_list_cntl_feature_ver; - uint32_t save_restore_list_cntl_size_bytes; - uint32_t save_restore_list_cntl_offset_bytes; - uint32_t save_restore_list_gpm_ucode_ver; - uint32_t save_restore_list_gpm_feature_ver; - uint32_t save_restore_list_gpm_size_bytes; - uint32_t save_restore_list_gpm_offset_bytes; - uint32_t save_restore_list_srm_ucode_ver; - uint32_t save_restore_list_srm_feature_ver; - uint32_t save_restore_list_srm_size_bytes; - uint32_t save_restore_list_srm_offset_bytes; -}; - -/* version_major=2, version_minor=2 */ -struct rlc_firmware_header_v2_2 { - struct rlc_firmware_header_v2_1 v2_1; - uint32_t rlc_iram_ucode_size_bytes; - uint32_t rlc_iram_ucode_offset_bytes; - uint32_t rlc_dram_ucode_size_bytes; - uint32_t rlc_dram_ucode_offset_bytes; -}; - -/* version_major=2, version_minor=3 */ -struct rlc_firmware_header_v2_3 { - struct rlc_firmware_header_v2_2 v2_2; - uint32_t rlcp_ucode_version; - uint32_t rlcp_ucode_feature_version; - uint32_t rlcp_ucode_size_bytes; - uint32_t rlcp_ucode_offset_bytes; - uint32_t rlcv_ucode_version; - uint32_t rlcv_ucode_feature_version; - uint32_t rlcv_ucode_size_bytes; - uint32_t rlcv_ucode_offset_bytes; -}; - -/* version_major=2, version_minor=4 */ -struct rlc_firmware_header_v2_4 { - struct rlc_firmware_header_v2_3 v2_3; - uint32_t global_tap_delays_ucode_size_bytes; - uint32_t global_tap_delays_ucode_offset_bytes; - uint32_t se0_tap_delays_ucode_size_bytes; - uint32_t se0_tap_delays_ucode_offset_bytes; - uint32_t se1_tap_delays_ucode_size_bytes; - uint32_t se1_tap_delays_ucode_offset_bytes; - uint32_t se2_tap_delays_ucode_size_bytes; - uint32_t se2_tap_delays_ucode_offset_bytes; - uint32_t se3_tap_delays_ucode_size_bytes; - uint32_t se3_tap_delays_ucode_offset_bytes; -}; - -/* version_major=1, version_minor=0 */ -struct sdma_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t ucode_change_version; - uint32_t jt_offset; /* jt location */ - uint32_t jt_size; /* size of jt */ -}; - -/* version_major=1, version_minor=1 */ -struct sdma_firmware_header_v1_1 { - struct sdma_firmware_header_v1_0 v1_0; - uint32_t digest_size; -}; - -/* version_major=2, version_minor=0 */ -struct sdma_firmware_header_v2_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ - uint32_t ctx_jt_offset; /* context thread jt location */ - uint32_t ctx_jt_size; /* context thread size of jt */ - uint32_t ctl_ucode_offset; - uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ - uint32_t ctl_jt_offset; /* control thread jt location */ - uint32_t ctl_jt_size; /* control thread size of jt */ -}; - -/* version_major=1, version_minor=0 */ -struct vpe_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ - uint32_t ctx_jt_offset; /* context thread jt location */ - uint32_t ctx_jt_size; /* context thread size of jt */ - uint32_t ctl_ucode_offset; - uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ - uint32_t ctl_jt_offset; /* control thread jt location */ - uint32_t ctl_jt_size; /* control thread size of jt */ -}; - -/* version_major=1, version_minor=0 */ -struct umsch_mm_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t umsch_mm_ucode_version; - uint32_t umsch_mm_ucode_size_bytes; - uint32_t umsch_mm_ucode_offset_bytes; - uint32_t umsch_mm_ucode_data_version; - uint32_t umsch_mm_ucode_data_size_bytes; - uint32_t umsch_mm_ucode_data_offset_bytes; - uint32_t umsch_mm_irq_start_addr_lo; - uint32_t umsch_mm_irq_start_addr_hi; - uint32_t umsch_mm_uc_start_addr_lo; - uint32_t umsch_mm_uc_start_addr_hi; - uint32_t umsch_mm_data_start_addr_lo; - uint32_t umsch_mm_data_start_addr_hi; -}; - -/* version_major=3, version_minor=0 */ -struct sdma_firmware_header_v3_0 { - struct common_firmware_header header; - uint32_t ucode_feature_version; - uint32_t ucode_offset_bytes; - uint32_t ucode_size_bytes; -}; - -/* gpu info payload */ -struct gpu_info_firmware_v1_0 { - uint32_t gc_num_se; - uint32_t gc_num_cu_per_sh; - uint32_t gc_num_sh_per_se; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_tccs; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; -}; - -struct gpu_info_firmware_v1_1 { - struct gpu_info_firmware_v1_0 v1_0; - uint32_t num_sc_per_sh; - uint32_t num_packer_per_sc; -}; - -/* gpu info payload - * version_major=1, version_minor=1 */ -// struct gpu_info_firmware_v1_2 { -// struct gpu_info_firmware_v1_1 v1_1; -// struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; -// }; - -/* version_major=1, version_minor=0 */ -struct gpu_info_firmware_header_v1_0 { - struct common_firmware_header header; - uint16_t version_major; /* version */ - uint16_t version_minor; /* version */ -}; - -/* version_major=1, version_minor=0 */ -struct dmcu_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ - uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ -}; - -/* version_major=1, version_minor=0 */ -struct dmcub_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t inst_const_bytes; /* size of instruction region, in bytes */ - uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ -}; - -/* version_major=1, version_minor=0 */ -struct imu_firmware_header_v1_0 { - struct common_firmware_header header; - uint32_t imu_iram_ucode_size_bytes; - uint32_t imu_iram_ucode_offset_bytes; - uint32_t imu_dram_ucode_size_bytes; - uint32_t imu_dram_ucode_offset_bytes; -}; - -/* header is fixed size */ -union amdgpu_firmware_header { - struct common_firmware_header common; - struct mc_firmware_header_v1_0 mc; - struct smc_firmware_header_v1_0 smc; - struct smc_firmware_header_v2_0 smc_v2_0; - struct psp_firmware_header_v1_0 psp; - struct psp_firmware_header_v1_1 psp_v1_1; - struct psp_firmware_header_v1_3 psp_v1_3; - struct psp_firmware_header_v2_0 psp_v2_0; - struct psp_firmware_header_v2_0 psp_v2_1; - struct ta_firmware_header_v1_0 ta; - struct ta_firmware_header_v2_0 ta_v2_0; - struct gfx_firmware_header_v1_0 gfx; - struct gfx_firmware_header_v2_0 gfx_v2_0; - struct rlc_firmware_header_v1_0 rlc; - struct rlc_firmware_header_v2_0 rlc_v2_0; - struct rlc_firmware_header_v2_1 rlc_v2_1; - struct rlc_firmware_header_v2_2 rlc_v2_2; - struct rlc_firmware_header_v2_3 rlc_v2_3; - struct rlc_firmware_header_v2_4 rlc_v2_4; - struct sdma_firmware_header_v1_0 sdma; - struct sdma_firmware_header_v1_1 sdma_v1_1; - struct sdma_firmware_header_v2_0 sdma_v2_0; - struct sdma_firmware_header_v3_0 sdma_v3_0; - struct gpu_info_firmware_header_v1_0 gpu_info; - struct dmcu_firmware_header_v1_0 dmcu; - struct dmcub_firmware_header_v1_0 dmcub; - struct imu_firmware_header_v1_0 imu; - uint8_t raw[0x100]; -}; - -#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) - -/* - * fw loading support - */ -enum AMDGPU_UCODE_ID { - AMDGPU_UCODE_ID_CAP = 0, - AMDGPU_UCODE_ID_SDMA0, - AMDGPU_UCODE_ID_SDMA1, - AMDGPU_UCODE_ID_SDMA2, - AMDGPU_UCODE_ID_SDMA3, - AMDGPU_UCODE_ID_SDMA4, - AMDGPU_UCODE_ID_SDMA5, - AMDGPU_UCODE_ID_SDMA6, - AMDGPU_UCODE_ID_SDMA7, - AMDGPU_UCODE_ID_SDMA_UCODE_TH0, - AMDGPU_UCODE_ID_SDMA_UCODE_TH1, - AMDGPU_UCODE_ID_SDMA_RS64, - AMDGPU_UCODE_ID_CP_CE, - AMDGPU_UCODE_ID_CP_PFP, - AMDGPU_UCODE_ID_CP_ME, - AMDGPU_UCODE_ID_CP_RS64_PFP, - AMDGPU_UCODE_ID_CP_RS64_ME, - AMDGPU_UCODE_ID_CP_RS64_MEC, - AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, - AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, - AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, - AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, - AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, - AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, - AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, - AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, - AMDGPU_UCODE_ID_CP_MEC1, - AMDGPU_UCODE_ID_CP_MEC1_JT, - AMDGPU_UCODE_ID_CP_MEC2, - AMDGPU_UCODE_ID_CP_MEC2_JT, - AMDGPU_UCODE_ID_CP_MES, - AMDGPU_UCODE_ID_CP_MES_DATA, - AMDGPU_UCODE_ID_CP_MES1, - AMDGPU_UCODE_ID_CP_MES1_DATA, - AMDGPU_UCODE_ID_IMU_I, - AMDGPU_UCODE_ID_IMU_D, - AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, - AMDGPU_UCODE_ID_SE0_TAP_DELAYS, - AMDGPU_UCODE_ID_SE1_TAP_DELAYS, - AMDGPU_UCODE_ID_SE2_TAP_DELAYS, - AMDGPU_UCODE_ID_SE3_TAP_DELAYS, - AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, - AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, - AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, - AMDGPU_UCODE_ID_RLC_IRAM, - AMDGPU_UCODE_ID_RLC_DRAM, - AMDGPU_UCODE_ID_RLC_P, - AMDGPU_UCODE_ID_RLC_V, - AMDGPU_UCODE_ID_RLC_G, - AMDGPU_UCODE_ID_STORAGE, - AMDGPU_UCODE_ID_SMC, - AMDGPU_UCODE_ID_PPTABLE, - AMDGPU_UCODE_ID_UVD, - AMDGPU_UCODE_ID_UVD1, - AMDGPU_UCODE_ID_VCE, - AMDGPU_UCODE_ID_VCN, - AMDGPU_UCODE_ID_VCN1, - AMDGPU_UCODE_ID_DMCU_ERAM, - AMDGPU_UCODE_ID_DMCU_INTV, - AMDGPU_UCODE_ID_VCN0_RAM, - AMDGPU_UCODE_ID_VCN1_RAM, - AMDGPU_UCODE_ID_DMCUB, - AMDGPU_UCODE_ID_VPE_CTX, - AMDGPU_UCODE_ID_VPE_CTL, - AMDGPU_UCODE_ID_VPE, - AMDGPU_UCODE_ID_UMSCH_MM_UCODE, - AMDGPU_UCODE_ID_UMSCH_MM_DATA, - AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, - AMDGPU_UCODE_ID_P2S_TABLE, - AMDGPU_UCODE_ID_JPEG_RAM, - AMDGPU_UCODE_ID_ISP, - AMDGPU_UCODE_ID_MAXIMUM, -}; - -/* engine firmware status */ -enum AMDGPU_UCODE_STATUS { - AMDGPU_UCODE_STATUS_INVALID, - AMDGPU_UCODE_STATUS_NOT_LOADED, - AMDGPU_UCODE_STATUS_LOADED, -}; - -enum amdgpu_firmware_load_type { - AMDGPU_FW_LOAD_DIRECT = 0, - AMDGPU_FW_LOAD_PSP, - AMDGPU_FW_LOAD_SMU, - AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, -}; - -/* conform to smu_ucode_xfer_cz.h */ -#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 -#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 -#define AMDGPU_CPCE_UCODE_LOADED 0x00000004 -#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 -#define AMDGPU_CPME_UCODE_LOADED 0x00000010 -#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 -#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 -#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 - -/* amdgpu firmware info */ -struct amdgpu_firmware_info { - /* ucode ID */ - enum AMDGPU_UCODE_ID ucode_id; - /* request_firmware */ - const struct firmware *fw; - /* starting mc address */ - uint64_t mc_addr; - /* kernel linear address */ - void *kaddr; - /* ucode_size_bytes */ - uint32_t ucode_size; - /* starting tmr mc address */ - uint32_t tmr_mc_addr_lo; - uint32_t tmr_mc_addr_hi; -}; - -// struct amdgpu_firmware { -// struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; -// enum amdgpu_firmware_load_type load_type; -// struct amdgpu_bo *fw_buf; -// unsigned int fw_size; -// unsigned int max_ucodes; -// /* firmwares are loaded by psp instead of smu from vega10 */ -// const struct amdgpu_psp_funcs *funcs; -// struct amdgpu_bo *rbuf; -// struct mutex mutex; - -// /* gpu info firmware data pointer */ -// const struct firmware *gpu_info_fw; - -// void *fw_buf_ptr; -// uint64_t fw_buf_mc; -// }; - -// void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); -// void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); -// int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, -// const char *fw_name); -// void amdgpu_ucode_release(const struct firmware **fw); -// bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, -// uint16_t hdr_major, uint16_t hdr_minor); - -// int amdgpu_ucode_init_bo(struct amdgpu_device *adev); -// int amdgpu_ucode_create_bo(struct amdgpu_device *adev); -// int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); -// void amdgpu_ucode_free_bo(struct amdgpu_device *adev); -// void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); - -// enum amdgpu_firmware_load_type -// amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); - -// const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); - -// void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); - -#endif diff --git a/tinygrad/extra/amdpci/headers/amdgpu_vm.h b/tinygrad/extra/amdpci/headers/amdgpu_vm.h deleted file mode 100644 index 53a6e323..00000000 --- a/tinygrad/extra/amdpci/headers/amdgpu_vm.h +++ /dev/null @@ -1,665 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Christian König - */ -#ifndef __AMDGPU_VM_H__ -#define __AMDGPU_VM_H__ - -// #include -// #include -// #include -// #include -// #include -// #include -// #include - -// #include "amdgpu_sync.h" -// #include "amdgpu_ring.h" -// #include "amdgpu_ids.h" - -// struct drm_exec; - -// struct amdgpu_bo_va; -// struct amdgpu_job; -// struct amdgpu_bo_list_entry; -// struct amdgpu_bo_vm; -// struct amdgpu_mem_stats; - -/* - * GPUVM handling - */ - -/* Maximum number of PTEs the hardware can write with one command */ -#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF - -/* number of entries in page table */ -#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) - -#define AMDGPU_PTE_VALID (1ULL << 0) -#define AMDGPU_PTE_SYSTEM (1ULL << 1) -#define AMDGPU_PTE_SNOOPED (1ULL << 2) - -/* RV+ */ -#define AMDGPU_PTE_TMZ (1ULL << 3) - -/* VI only */ -#define AMDGPU_PTE_EXECUTABLE (1ULL << 4) - -#define AMDGPU_PTE_READABLE (1ULL << 5) -#define AMDGPU_PTE_WRITEABLE (1ULL << 6) - -#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) - -/* TILED for VEGA10, reserved for older ASICs */ -#define AMDGPU_PTE_PRT (1ULL << 51) - -/* PDE is handled as PTE for VEGA10 */ -#define AMDGPU_PDE_PTE (1ULL << 54) - -#define AMDGPU_PTE_LOG (1ULL << 55) - -/* PTE is handled as PDE for VEGA10 (Translate Further) */ -#define AMDGPU_PTE_TF (1ULL << 56) - -/* MALL noalloc for sienna_cichlid, reserved for older ASICs */ -#define AMDGPU_PTE_NOALLOC (1ULL << 58) - -/* PDE Block Fragment Size for VEGA10 */ -#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) - -/* Flag combination to set no-retry with TF disabled */ -#define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ - AMDGPU_PTE_TF) - -/* Flag combination to set no-retry with TF enabled */ -#define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ - AMDGPU_PTE_PRT) -/* For GFX9 */ -#define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57) -#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL) -#define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \ - (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ - AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) - -#define AMDGPU_MTYPE_NC 0 -#define AMDGPU_MTYPE_CC 2 - -#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ - | AMDGPU_PTE_SNOOPED \ - | AMDGPU_PTE_EXECUTABLE \ - | AMDGPU_PTE_READABLE \ - | AMDGPU_PTE_WRITEABLE \ - | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) - -/* gfx10 */ -#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48) -#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL) -#define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \ - (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \ - AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) - -/* gfx12 */ -#define AMDGPU_PTE_PRT_GFX12 (1ULL << 56) -#define AMDGPU_PTE_PRT_FLAG(adev) \ - ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT) - -#define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54) -#define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL) -#define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \ - (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \ - AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) - -#define AMDGPU_PTE_IS_PTE (1ULL << 63) - -/* PDE Block Fragment Size for gfx v12 */ -#define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58) -#define AMDGPU_PDE_BFS_FLAG(adev, a) \ - ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a)) -/* PDE is handled as PTE for gfx v12 */ -#define AMDGPU_PDE_PTE_GFX12 (1ULL << 63) -#define AMDGPU_PDE_PTE_FLAG(adev) \ - ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE) - -/* How to program VM fault handling */ -#define AMDGPU_VM_FAULT_STOP_NEVER 0 -#define AMDGPU_VM_FAULT_STOP_FIRST 1 -#define AMDGPU_VM_FAULT_STOP_ALWAYS 2 - -/* How much VRAM be reserved for page tables */ -#define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) - -/* - * max number of VMHUB - * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 - */ -#define AMDGPU_MAX_VMHUBS 13 -#define AMDGPU_GFXHUB_START 0 -#define AMDGPU_MMHUB0_START 8 -#define AMDGPU_MMHUB1_START 12 -#define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x)) -#define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x)) -#define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x)) - -#define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START) -#define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START) -#define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS) - -/* Reserve space at top/bottom of address space for kernel use */ -#define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20) -#define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \ - << AMDGPU_GPU_PAGE_SHIFT) \ - - AMDGPU_VA_RESERVED_CSA_SIZE) -#define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) -#define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ - - AMDGPU_VA_RESERVED_SEQ64_SIZE) -#define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) -#define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ - - AMDGPU_VA_RESERVED_TRAP_SIZE) -#define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16) -#define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \ - AMDGPU_VA_RESERVED_SEQ64_SIZE + \ - AMDGPU_VA_RESERVED_CSA_SIZE) - -/* See vm_update_mode */ -#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) -#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) - -/* VMPT level enumerate, and the hiberachy is: - * PDB2->PDB1->PDB0->PTB - */ -enum amdgpu_vm_level { - AMDGPU_VM_PDB2, - AMDGPU_VM_PDB1, - AMDGPU_VM_PDB0, - AMDGPU_VM_PTB -}; - -// /* base structure for tracking BO usage in a VM */ -// struct amdgpu_vm_bo_base { -// /* constant after initialization */ -// struct amdgpu_vm *vm; -// struct amdgpu_bo *bo; - -// /* protected by bo being reserved */ -// struct amdgpu_vm_bo_base *next; - -// /* protected by spinlock */ -// struct list_head vm_status; - -// /* protected by the BO being reserved */ -// bool moved; -// }; - -// /* provided by hw blocks that can write ptes, e.g., sdma */ -// struct amdgpu_vm_pte_funcs { -// /* number of dw to reserve per operation */ -// unsigned copy_pte_num_dw; - -// /* copy pte entries from GART */ -// void (*copy_pte)(struct amdgpu_ib *ib, -// uint64_t pe, uint64_t src, -// unsigned count); - -// /* write pte one entry at a time with addr mapping */ -// void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, -// uint64_t value, unsigned count, -// uint32_t incr); -// /* for linear pte/pde updates without addr mapping */ -// void (*set_pte_pde)(struct amdgpu_ib *ib, -// uint64_t pe, -// uint64_t addr, unsigned count, -// uint32_t incr, uint64_t flags); -// }; - -// struct amdgpu_task_info { -// char process_name[TASK_COMM_LEN]; -// char task_name[TASK_COMM_LEN]; -// pid_t pid; -// pid_t tgid; -// struct kref refcount; -// }; - -// /** -// * struct amdgpu_vm_update_params -// * -// * Encapsulate some VM table update parameters to reduce -// * the number of function parameters -// * -// */ -// struct amdgpu_vm_update_params { - -// /** -// * @adev: amdgpu device we do this update for -// */ -// struct amdgpu_device *adev; - -// /** -// * @vm: optional amdgpu_vm we do this update for -// */ -// struct amdgpu_vm *vm; - -// /** -// * @immediate: if changes should be made immediately -// */ -// bool immediate; - -// /** -// * @unlocked: true if the root BO is not locked -// */ -// bool unlocked; - -// /** -// * @pages_addr: -// * -// * DMA addresses to use for mapping -// */ -// dma_addr_t *pages_addr; - -// /** -// * @job: job to used for hw submission -// */ -// struct amdgpu_job *job; - -// /** -// * @num_dw_left: number of dw left for the IB -// */ -// unsigned int num_dw_left; - -// /** -// * @needs_flush: true whenever we need to invalidate the TLB -// */ -// bool needs_flush; - -// /** -// * @allow_override: true for memory that is not uncached: allows MTYPE -// * to be overridden for NUMA local memory. -// */ -// bool allow_override; - -// /** -// * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush -// */ -// struct list_head tlb_flush_waitlist; -// }; - -// struct amdgpu_vm_update_funcs { -// int (*map_table)(struct amdgpu_bo_vm *bo); -// int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, -// enum amdgpu_sync_mode sync_mode); -// int (*update)(struct amdgpu_vm_update_params *p, -// struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, -// unsigned count, uint32_t incr, uint64_t flags); -// int (*commit)(struct amdgpu_vm_update_params *p, -// struct dma_fence **fence); -// }; - -// struct amdgpu_vm_fault_info { -// /* fault address */ -// uint64_t addr; -// /* fault status register */ -// uint32_t status; -// /* which vmhub? gfxhub, mmhub, etc. */ -// unsigned int vmhub; -// }; - -// struct amdgpu_vm { -// /* tree of virtual addresses mapped */ -// #ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED -// struct rb_root va; -// #else -// struct rb_root_cached va; -// #endif - -// /* Lock to prevent eviction while we are updating page tables -// * use vm_eviction_lock/unlock(vm) -// */ -// struct mutex eviction_lock; -// bool evicting; -// unsigned int saved_flags; - -// /* Lock to protect vm_bo add/del/move on all lists of vm */ -// spinlock_t status_lock; - -// /* Per-VM and PT BOs who needs a validation */ -// struct list_head evicted; - -// /* BOs for user mode queues that need a validation */ -// struct list_head evicted_user; - -// /* PT BOs which relocated and their parent need an update */ -// struct list_head relocated; - -// /* per VM BOs moved, but not yet updated in the PT */ -// struct list_head moved; - -// /* All BOs of this VM not currently in the state machine */ -// struct list_head idle; - -// /* regular invalidated BOs, but not yet updated in the PT */ -// struct list_head invalidated; - -// /* BO mappings freed, but not yet updated in the PT */ -// struct list_head freed; - -// /* BOs which are invalidated, has been updated in the PTs */ -// struct list_head done; - -// /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ -// struct list_head pt_freed; -// struct work_struct pt_free_work; - -// /* contains the page directory */ -// struct amdgpu_vm_bo_base root; -// struct dma_fence *last_update; - -// /* Scheduler entities for page table updates */ -// struct drm_sched_entity immediate; -// struct drm_sched_entity delayed; - -// /* Last finished delayed update */ -// atomic64_t tlb_seq; -// struct dma_fence *last_tlb_flush; -// atomic64_t kfd_last_flushed_seq; -// uint64_t tlb_fence_context; - -// /* How many times we had to re-generate the page tables */ -// uint64_t generation; - -// /* Last unlocked submission to the scheduler entities */ -// struct dma_fence *last_unlocked; - -// unsigned int pasid; -// bool reserved_vmid[AMDGPU_MAX_VMHUBS]; - -// /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ -// bool use_cpu_for_update; - -// /* Functions to use for VM table updates */ -// const struct amdgpu_vm_update_funcs *update_funcs; - -// /* Up to 128 pending retry page faults */ -// DECLARE_KFIFO(faults, u64, 128); - -// /* Points to the KFD process VM info */ -// struct amdkfd_process_info *process_info; - -// /* List node in amdkfd_process_info.vm_list_head */ -// struct list_head vm_list_node; - -// /* Valid while the PD is reserved or fenced */ -// uint64_t pd_phys_addr; - -// /* Some basic info about the task */ -// struct amdgpu_task_info *task_info; - -// /* Store positions of group of BOs */ -// struct ttm_lru_bulk_move lru_bulk_move; -// /* Flag to indicate if VM is used for compute */ -// bool is_compute_context; - -// /* Memory partition number, -1 means any partition */ -// int8_t mem_id; - -// /* cached fault info */ -// struct amdgpu_vm_fault_info fault_info; -// }; - -// struct amdgpu_vm_manager { -// /* Handling of VMIDs */ -// struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; -// unsigned int first_kfd_vmid; -// bool concurrent_flush; - -// /* Handling of VM fences */ -// u64 fence_context; -// unsigned seqno[AMDGPU_MAX_RINGS]; - -// uint64_t max_pfn; -// uint32_t num_level; -// uint32_t block_size; -// uint32_t fragment_size; -// enum amdgpu_vm_level root_level; -// /* vram base address for page table entry */ -// u64 vram_base_offset; -// /* vm pte handling */ -// const struct amdgpu_vm_pte_funcs *vm_pte_funcs; -// struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; -// unsigned vm_pte_num_scheds; -// struct amdgpu_ring *page_fault; - -// /* partial resident texture handling */ -// spinlock_t prt_lock; -// atomic_t num_prt_users; - -// /* controls how VM page tables are updated for Graphics and Compute. -// * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU -// * BIT1[= 0] Compute updated by SDMA [= 1] by CPU -// */ -// int vm_update_mode; - -// /* PASID to VM mapping, will be used in interrupt context to -// * look up VM of a page fault -// */ -// #ifdef HAVE_STRUCT_XARRAY -// struct xarray pasids; -// #else -// struct idr pasid_idr; -// spinlock_t pasid_lock; -// #endif -// /* Global registration of recent page fault information */ -// struct amdgpu_vm_fault_info fault_info; -// }; - -// struct amdgpu_bo_va_mapping; - -// #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) -// #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) -// #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) - -// extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; -// extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; - -// void amdgpu_vm_manager_init(struct amdgpu_device *adev); -// void amdgpu_vm_manager_fini(struct amdgpu_device *adev); - -// int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, -// u32 pasid); - -// long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); -// int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); -// int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); -// void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); -// void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); -// int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, -// unsigned int num_fences); -// bool amdgpu_vm_ready(struct amdgpu_vm *vm); -// uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); -// int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, -// struct ww_acquire_ctx *ticket, -// int (*callback)(void *p, struct amdgpu_bo *bo), -// void *param); -// int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); -// int amdgpu_vm_update_pdes(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, bool immediate); -// int amdgpu_vm_clear_freed(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// struct dma_fence **fence); -// int amdgpu_vm_handle_moved(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// struct ww_acquire_ctx *ticket); -// int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// uint32_t flush_type, -// uint32_t xcc_mask); -// void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, -// struct amdgpu_vm *vm, struct amdgpu_bo *bo); -// int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, -// bool immediate, bool unlocked, bool flush_tlb, bool allow_override, -// struct dma_resv *resv, uint64_t start, uint64_t last, -// uint64_t flags, uint64_t offset, uint64_t vram_base, -// struct ttm_resource *res, dma_addr_t *pages_addr, -// struct dma_fence **fence); -// int amdgpu_vm_bo_update(struct amdgpu_device *adev, -// struct amdgpu_bo_va *bo_va, -// bool clear); -// bool amdgpu_vm_evictable(struct amdgpu_bo *bo); -// void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, -// struct amdgpu_bo *bo, bool evicted); -// uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); -// struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, -// struct amdgpu_bo *bo); -// struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// struct amdgpu_bo *bo); -// int amdgpu_vm_bo_map(struct amdgpu_device *adev, -// struct amdgpu_bo_va *bo_va, -// uint64_t addr, uint64_t offset, -// uint64_t size, uint64_t flags); -// int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, -// struct amdgpu_bo_va *bo_va, -// uint64_t addr, uint64_t offset, -// uint64_t size, uint64_t flags); -// int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, -// struct amdgpu_bo_va *bo_va, -// uint64_t addr); -// int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// uint64_t saddr, uint64_t size); -// struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, -// uint64_t addr); -// void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); -// void amdgpu_vm_bo_del(struct amdgpu_device *adev, -// struct amdgpu_bo_va *bo_va); -// void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, -// uint32_t fragment_size_default, unsigned max_level, -// unsigned max_bits); -// int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); -// bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, -// struct amdgpu_job *job); -// void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); - -// struct amdgpu_task_info * -// amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid); - -// struct amdgpu_task_info * -// amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); - -// void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); - -// bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, -// u32 vmid, u32 node_id, uint64_t addr, -// bool write_fault); - -// void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); - -// void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, -// struct amdgpu_vm *vm); -// void amdgpu_vm_get_memory(struct amdgpu_vm *vm, -// struct amdgpu_mem_stats *stats); - -// int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, -// struct amdgpu_bo_vm *vmbo, bool immediate); -// int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, -// int level, bool immediate, struct amdgpu_bo_vm **vmbo, -// int32_t xcp_id); -// void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); - -// int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, -// struct amdgpu_vm_bo_base *entry); -// int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, -// uint64_t start, uint64_t end, -// uint64_t dst, uint64_t flags); -// void amdgpu_vm_pt_free_work(struct work_struct *work); -// void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, -// struct amdgpu_vm_update_params *params); - -// #if defined(CONFIG_DEBUG_FS) -// void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); -// #endif - -// int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); - -// bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo); - -// /** -// * amdgpu_vm_tlb_seq - return tlb flush sequence number -// * @vm: the amdgpu_vm structure to query -// * -// * Returns the tlb flush sequence number which indicates that the VM TLBs needs -// * to be invalidated whenever the sequence number change. -// */ -// static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) -// { -// unsigned long flags; -// spinlock_t *lock; - -// /* -// * Workaround to stop racing between the fence signaling and handling -// * the cb. The lock is static after initially setting it up, just make -// * sure that the dma_fence structure isn't freed up. -// */ -// rcu_read_lock(); -// lock = vm->last_tlb_flush->lock; -// rcu_read_unlock(); - -// spin_lock_irqsave(lock, flags); -// spin_unlock_irqrestore(lock, flags); - -// return atomic64_read(&vm->tlb_seq); -// } - -// /* -// * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS -// * happens while holding this lock anywhere to prevent deadlocks when -// * an MMU notifier runs in reclaim-FS context. -// */ -// static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) -// { -// mutex_lock(&vm->eviction_lock); -// vm->saved_flags = memalloc_noreclaim_save(); -// } - -// static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) -// { -// if (mutex_trylock(&vm->eviction_lock)) { -// vm->saved_flags = memalloc_noreclaim_save(); -// return true; -// } -// return false; -// } - -// static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) -// { -// memalloc_noreclaim_restore(vm->saved_flags); -// mutex_unlock(&vm->eviction_lock); -// } - -// void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, -// unsigned int pasid, -// uint64_t addr, -// uint32_t status, -// unsigned int vmhub); -// void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, -// struct amdgpu_vm *vm, -// struct dma_fence **fence); - -#endif diff --git a/tinygrad/extra/amdpci/headers/discovery.h b/tinygrad/extra/amdpci/headers/discovery.h deleted file mode 100644 index b5595872..00000000 --- a/tinygrad/extra/amdpci/headers/discovery.h +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - - #ifndef _DISCOVERY_H_ - #define _DISCOVERY_H_ - - #define PSP_HEADER_SIZE 256 - #define BINARY_SIGNATURE 0x28211407 - #define DISCOVERY_TABLE_SIGNATURE 0x53445049 - #define GC_TABLE_ID 0x4347 - #define HARVEST_TABLE_SIGNATURE 0x56524148 - #define VCN_INFO_TABLE_ID 0x004E4356 - #define MALL_INFO_TABLE_ID 0x4C4C414D - #define NPS_INFO_TABLE_ID 0x0053504E - - typedef enum { - IP_DISCOVERY = 0, - GC, - HARVEST_INFO, - VCN_INFO, - MALL_INFO, - NPS_INFO, - TOTAL_TABLES = 6 - } table; - - #pragma pack(1) - - typedef struct table_info - { - uint16_t offset; /* Byte offset */ - uint16_t checksum; /* Byte sum of the table */ - uint16_t size; /* Table size */ - uint16_t padding; - } table_info; - - typedef struct binary_header - { - /* psp structure should go at the top of this structure */ - uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ - uint16_t version_major; - uint16_t version_minor; - uint16_t binary_checksum; /* Byte sum of the binary after this field */ - uint16_t binary_size; /* Binary Size*/ - table_info table_list[TOTAL_TABLES]; - } binary_header; - - typedef struct die_info - { - uint16_t die_id; - uint16_t die_offset; /* Points to the corresponding die_header structure */ - } die_info; - - - typedef struct ip_discovery_header - { - uint32_t signature; /* Table Signature */ - uint16_t version; /* Table Version */ - uint16_t size; /* Table Size */ - uint32_t id; /* Table ID */ - uint16_t num_dies; /* Number of Dies */ - die_info die_info[16]; /* list die information for up to 16 dies */ - union { - uint16_t padding[1]; /* version <= 3 */ - struct { /* version == 4 */ - uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ - uint8_t reserved : 7; - uint8_t reserved2; - }; - }; - } ip_discovery_header; - - typedef struct ip - { - uint16_t hw_id; /* Hardware ID */ - uint8_t number_instance; /* instance of the IP */ - uint8_t num_base_address; /* Number of Base Addresses */ - uint8_t major; /* HCID Major */ - uint8_t minor; /* HCID Minor */ - uint8_t revision; /* HCID Revision */ - #if defined(__BIG_ENDIAN) - uint8_t reserved : 4; /* Placeholder field */ - uint8_t harvest : 4; /* Harvest */ - #else - uint8_t harvest : 4; /* Harvest */ - uint8_t reserved : 4; /* Placeholder field */ - #endif - uint32_t base_address[]; /* variable number of Addresses */ - } ip; - - typedef struct ip_v3 - { - uint16_t hw_id; /* Hardware ID */ - uint8_t instance_number; /* Instance number for the IP */ - uint8_t num_base_address; /* Number of base addresses*/ - uint8_t major; /* Hardware ID.major version */ - uint8_t minor; /* Hardware ID.minor version */ - uint8_t revision; /* Hardware ID.revision version */ - #if defined(__BIG_ENDIAN) - uint8_t variant : 4; /* HW variant */ - uint8_t sub_revision : 4; /* HCID Sub-Revision */ - #else - uint8_t sub_revision : 4; /* HCID Sub-Revision */ - uint8_t variant : 4; /* HW variant */ - #endif - uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ - } ip_v3; - - typedef struct ip_v4 { - uint16_t hw_id; /* Hardware ID */ - uint8_t instance_number; /* Instance number for the IP */ - uint8_t num_base_address; /* Number of base addresses*/ - uint8_t major; /* Hardware ID.major version */ - uint8_t minor; /* Hardware ID.minor version */ - uint8_t revision; /* Hardware ID.revision version */ - #if defined(LITTLEENDIAN_CPU) - uint8_t sub_revision : 4; /* HCID Sub-Revision */ - uint8_t variant : 4; /* HW variant */ - #elif defined(BIGENDIAN_CPU) - uint8_t variant : 4; /* HW variant */ - uint8_t sub_revision : 4; /* HCID Sub-Revision */ - #endif - } ip_v4; - - typedef struct die_header - { - uint16_t die_id; - uint16_t num_ips; - } die_header; - - typedef struct ip_structure - { - ip_discovery_header* header; - struct die - { - die_header *die_header; - union - { - ip *ip_list; - ip_v3 *ip_v3_list; - ip_v4 *ip_v4_list; - }; /* IP list. Variable size*/ - } die; - } ip_structure; - - struct gpu_info_header { - uint32_t table_id; /* table ID */ - uint16_t version_major; /* table version */ - uint16_t version_minor; /* table version */ - uint32_t size; /* size of the entire header+data in bytes */ - }; - - struct gc_info_v1_0 { - struct gpu_info_header header; - - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - }; - - struct gc_info_v1_1 { - struct gpu_info_header header; - - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - uint32_t gc_num_tcp_per_sa; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_tcps; - }; - - struct gc_info_v1_2 { - struct gpu_info_header header; - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - uint32_t gc_num_tcp_per_sa; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_tcps; - uint32_t gc_num_tcp_per_wpg; - uint32_t gc_tcp_l1_size; - uint32_t gc_num_sqc_per_wgp; - uint32_t gc_l1_instruction_cache_size_per_sqc; - uint32_t gc_l1_data_cache_size_per_sqc; - uint32_t gc_gl1c_per_sa; - uint32_t gc_gl1c_size_per_instance; - uint32_t gc_gl2c_per_gpu; - }; - - struct gc_info_v1_3 { - struct gpu_info_header header; - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - uint32_t gc_num_tcp_per_sa; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_tcps; - uint32_t gc_num_tcp_per_wpg; - uint32_t gc_tcp_l1_size; - uint32_t gc_num_sqc_per_wgp; - uint32_t gc_l1_instruction_cache_size_per_sqc; - uint32_t gc_l1_data_cache_size_per_sqc; - uint32_t gc_gl1c_per_sa; - uint32_t gc_gl1c_size_per_instance; - uint32_t gc_gl2c_per_gpu; - uint32_t gc_tcp_size_per_cu; - uint32_t gc_tcp_cache_line_size; - uint32_t gc_instruction_cache_size_per_sqc; - uint32_t gc_instruction_cache_line_size; - uint32_t gc_scalar_data_cache_size_per_sqc; - uint32_t gc_scalar_data_cache_line_size; - uint32_t gc_tcc_size; - uint32_t gc_tcc_cache_line_size; - }; - - struct gc_info_v2_0 { - struct gpu_info_header header; - - uint32_t gc_num_se; - uint32_t gc_num_cu_per_sh; - uint32_t gc_num_sh_per_se; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_tccs; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_packer_per_sc; - }; - - struct gc_info_v2_1 { - struct gpu_info_header header; - - uint32_t gc_num_se; - uint32_t gc_num_cu_per_sh; - uint32_t gc_num_sh_per_se; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_tccs; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_packer_per_sc; - /* new for v2_1 */ - uint32_t gc_num_tcp_per_sh; - uint32_t gc_tcp_size_per_cu; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_cu_per_sqc; - uint32_t gc_instruction_cache_size_per_sqc; - uint32_t gc_scalar_data_cache_size_per_sqc; - uint32_t gc_tcc_size; - }; - - typedef struct harvest_info_header { - uint32_t signature; /* Table Signature */ - uint32_t version; /* Table Version */ - } harvest_info_header; - - typedef struct harvest_info { - uint16_t hw_id; /* Hardware ID */ - uint8_t number_instance; /* Instance of the IP */ - uint8_t reserved; /* Reserved for alignment */ - } harvest_info; - - typedef struct harvest_table { - harvest_info_header header; - harvest_info list[32]; - } harvest_table; - - struct mall_info_header { - uint32_t table_id; /* table ID */ - uint16_t version_major; /* table version */ - uint16_t version_minor; /* table version */ - uint32_t size_bytes; /* size of the entire header+data in bytes */ - }; - - struct mall_info_v1_0 { - struct mall_info_header header; - uint32_t mall_size_per_m; - uint32_t m_s_present; - uint32_t m_half_use; - uint32_t m_mall_config; - uint32_t reserved[5]; - }; - - struct mall_info_v2_0 { - struct mall_info_header header; - uint32_t mall_size_per_umc; - uint32_t reserved[8]; - }; - - #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 - - struct vcn_info_header { - uint32_t table_id; /* table ID */ - uint16_t version_major; /* table version */ - uint16_t version_minor; /* table version */ - uint32_t size_bytes; /* size of the entire header+data in bytes */ - }; - - struct vcn_instance_info_v1_0 - { - uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/ - union _fuse_data { - struct { - uint32_t av1_disabled : 1; - uint32_t vp9_disabled : 1; - uint32_t hevc_disabled : 1; - uint32_t h264_disabled : 1; - uint32_t reserved : 28; - } bits; - uint32_t all_bits; - } fuse_data; - uint32_t reserved[2]; - }; - - struct vcn_info_v1_0 { - struct vcn_info_header header; - uint32_t num_of_instances; /* number of entries used in instance_info below*/ - struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES]; - uint32_t reserved[4]; - }; - - #define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12 - - struct nps_info_header { - uint32_t table_id; /* table ID */ - uint16_t version_major; /* table version */ - uint16_t version_minor; /* table version */ - uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */ - }; - - struct nps_instance_info_v1_0 { - uint64_t base_address; - uint64_t limit_address; - }; - - struct nps_info_v1_0 { - struct nps_info_header header; - uint32_t nps_type; - uint32_t count; - struct nps_instance_info_v1_0 - instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES]; - }; - - enum amd_hw_ip_block_type { - GC_HWIP = 1, - HDP_HWIP, - SDMA0_HWIP, - SDMA1_HWIP, - SDMA2_HWIP, - SDMA3_HWIP, - SDMA4_HWIP, - SDMA5_HWIP, - SDMA6_HWIP, - SDMA7_HWIP, - LSDMA_HWIP, - MMHUB_HWIP, - ATHUB_HWIP, - NBIO_HWIP, - MP0_HWIP, - MP1_HWIP, - UVD_HWIP, - VCN_HWIP = UVD_HWIP, - JPEG_HWIP = VCN_HWIP, - VCN1_HWIP, - VCE_HWIP, - VPE_HWIP, - DF_HWIP, - DCE_HWIP, - OSSSYS_HWIP, - SMUIO_HWIP, - PWR_HWIP, - NBIF_HWIP, - THM_HWIP, - CLK_HWIP, - UMC_HWIP, - RSMU_HWIP, - XGMI_HWIP, - DCI_HWIP, - PCIE_HWIP, - ISP_HWIP, - MAX_HWIP -}; - -#define HWIP_MAX_INSTANCE 44 - -#define HW_ID_MAX 300 - -// HW ID -#define MP1_HWID 1 -#define MP2_HWID 2 -#define THM_HWID 3 -#define SMUIO_HWID 4 -#define FUSE_HWID 5 -#define CLKA_HWID 6 -#define PWR_HWID 10 -#define GC_HWID 11 -#define UVD_HWID 12 -#define VCN_HWID UVD_HWID -#define AUDIO_AZ_HWID 13 -#define ACP_HWID 14 -#define DCI_HWID 15 -#define DMU_HWID 271 -#define DCO_HWID 16 -#define DIO_HWID 272 -#define XDMA_HWID 17 -#define DCEAZ_HWID 18 -#define DAZ_HWID 274 -#define SDPMUX_HWID 19 -#define NTB_HWID 20 -#define VPE_HWID 21 -#define IOHC_HWID 24 -#define L2IMU_HWID 28 -#define VCE_HWID 32 -#define MMHUB_HWID 34 -#define ATHUB_HWID 35 -#define DBGU_NBIO_HWID 36 -#define DFX_HWID 37 -#define DBGU0_HWID 38 -#define DBGU1_HWID 39 -#define OSSSYS_HWID 40 -#define HDP_HWID 41 -#define SDMA0_HWID 42 -#define SDMA1_HWID 43 -#define ISP_HWID 44 -#define DBGU_IO_HWID 45 -#define DF_HWID 46 -#define CLKB_HWID 47 -#define FCH_HWID 48 -#define DFX_DAP_HWID 49 -#define L1IMU_PCIE_HWID 50 -#define L1IMU_NBIF_HWID 51 -#define L1IMU_IOAGR_HWID 52 -#define L1IMU3_HWID 53 -#define L1IMU4_HWID 54 -#define L1IMU5_HWID 55 -#define L1IMU6_HWID 56 -#define L1IMU7_HWID 57 -#define L1IMU8_HWID 58 -#define L1IMU9_HWID 59 -#define L1IMU10_HWID 60 -#define L1IMU11_HWID 61 -#define L1IMU12_HWID 62 -#define L1IMU13_HWID 63 -#define L1IMU14_HWID 64 -#define L1IMU15_HWID 65 -#define WAFLC_HWID 66 -#define FCH_USB_PD_HWID 67 -#define SDMA2_HWID 68 -#define SDMA3_HWID 69 -#define PCIE_HWID 70 -#define PCS_HWID 80 -#define DDCL_HWID 89 -#define SST_HWID 90 -#define LSDMA_HWID 91 -#define IOAGR_HWID 100 -#define NBIF_HWID 108 -#define IOAPIC_HWID 124 -#define SYSTEMHUB_HWID 128 -#define NTBCCP_HWID 144 -#define UMC_HWID 150 -#define SATA_HWID 168 -#define USB_HWID 170 -#define CCXSEC_HWID 176 -#define XGMI_HWID 200 -#define XGBE_HWID 216 -#define MP0_HWID 255 - -static int hw_id_map[MAX_HWIP] = { - [GC_HWIP] = GC_HWID, - [HDP_HWIP] = HDP_HWID, - [SDMA0_HWIP] = SDMA0_HWID, - [SDMA1_HWIP] = SDMA1_HWID, - [SDMA2_HWIP] = SDMA2_HWID, - [SDMA3_HWIP] = SDMA3_HWID, - [LSDMA_HWIP] = LSDMA_HWID, - [MMHUB_HWIP] = MMHUB_HWID, - [ATHUB_HWIP] = ATHUB_HWID, - [NBIO_HWIP] = NBIF_HWID, - [MP0_HWIP] = MP0_HWID, - [MP1_HWIP] = MP1_HWID, - [UVD_HWIP] = UVD_HWID, - [VCE_HWIP] = VCE_HWID, - [DF_HWIP] = DF_HWID, - [DCE_HWIP] = DMU_HWID, - [OSSSYS_HWIP] = OSSSYS_HWID, - [SMUIO_HWIP] = SMUIO_HWID, - [PWR_HWIP] = PWR_HWID, - [NBIF_HWIP] = NBIF_HWID, - [THM_HWIP] = THM_HWID, - [CLK_HWIP] = CLKA_HWID, - [UMC_HWIP] = UMC_HWID, - [XGMI_HWIP] = XGMI_HWID, - [DCI_HWIP] = DCI_HWID, - [PCIE_HWIP] = PCIE_HWID, - [VPE_HWIP] = VPE_HWID, - [ISP_HWIP] = ISP_HWID, -}; - -#endif - - \ No newline at end of file diff --git a/tinygrad/extra/amdpci/headers/psp_gfx_if.h b/tinygrad/extra/amdpci/headers/psp_gfx_if.h deleted file mode 100644 index a85d3491..00000000 --- a/tinygrad/extra/amdpci/headers/psp_gfx_if.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _PSP_TEE_GFX_IF_H_ -#define _PSP_TEE_GFX_IF_H_ - -#define PSP_GFX_CMD_BUF_VERSION 0x00000001 - -#define GFX_CMD_STATUS_MASK 0x0000FFFF -#define GFX_CMD_ID_MASK 0x000F0000 -#define GFX_CMD_RESERVED_MASK 0x7FF00000 -#define GFX_CMD_RESPONSE_MASK 0x80000000 - -/* USBC PD FW version retrieval command */ -#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000 - -/* TEE Gfx Command IDs for the register interface. -* Command ID must be between 0x00010000 and 0x000F0000. -*/ -enum psp_gfx_crtl_cmd_id -{ - GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ - GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ - GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ - GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ - GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ - GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ - GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ - GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */ - GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */ - GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */ - - GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ -}; - - -/*----------------------------------------------------------------------------- - NOTE: All physical addresses used in this interface are actually - GPU Virtual Addresses. -*/ - - -/* Control registers of the TEE Gfx interface. These are located in -* SRBM-to-PSP mailbox registers (total 8 registers). -*/ -struct psp_gfx_ctrl -{ - volatile unsigned int cmd_resp; /* +0 Command/Response register for Gfx commands */ - volatile unsigned int rbi_wptr; /* +4 Write pointer (index) of RBI ring */ - volatile unsigned int rbi_rptr; /* +8 Read pointer (index) of RBI ring */ - volatile unsigned int gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ - volatile unsigned int gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ - volatile unsigned int ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ - volatile unsigned int ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ - volatile unsigned int ring_buf_size; /* +28 Ring buffer size (in bytes) */ - -}; - - -/* Response flag is set in the command when command is completed by PSP. -* Used in the GFX_CTRL.CmdResp. -* When PSP GFX I/F is initialized, the flag is set. -*/ -#define GFX_FLAG_RESPONSE 0x80000000 - -/* TEE Gfx Command IDs for the ring buffer interface. */ -enum psp_gfx_cmd_id -{ - GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ - GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ - GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ - GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ - GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ - GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ - GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ - GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ - GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ - GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ - GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ - GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */ - /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */ - GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */ - GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ - GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ - GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */ -}; - -/* PSP boot config sub-commands */ -enum psp_gfx_boot_config_cmd -{ - BOOTCFG_CMD_SET = 1, /* Set boot configuration settings */ - BOOTCFG_CMD_GET = 2, /* Get boot configuration settings */ - BOOTCFG_CMD_INVALIDATE = 3 /* Reset current boot configuration settings to VBIOS defaults */ -}; - -/* PSP boot config bitmask values */ -enum psp_gfx_boot_config -{ - BOOT_CONFIG_GECC = 0x1, -}; - -/* Command to load Trusted Application binary into PSP OS. */ -struct psp_gfx_cmd_load_ta -{ - unsigned int app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ - unsigned int app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ - unsigned int app_len; /* length of the TA binary in bytes */ - unsigned int cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ - unsigned int cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ - unsigned int cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ - - /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided - * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead - * of using global persistent buffer. - */ -}; - - -/* Command to Unload Trusted Application binary from PSP OS. */ -struct psp_gfx_cmd_unload_ta -{ - unsigned int session_id; /* Session ID of the loaded TA to be unloaded */ - -}; - - -/* Shared buffers for InvokeCommand. -*/ -struct psp_gfx_buf_desc -{ - unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ - unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ - unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ - -}; - -/* Max number of descriptors for one shared buffer (in how many different -* physical locations one shared buffer can be stored). If buffer is too much -* fragmented, error will be returned. -*/ -#define GFX_BUF_MAX_DESC 64 - -struct psp_gfx_buf_list -{ - unsigned int num_desc; /* number of buffer descriptors in the list */ - unsigned int total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ - struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ - - /* total 776 bytes */ -}; - -/* Command to execute InvokeCommand entry point of the TA. */ -struct psp_gfx_cmd_invoke_cmd -{ - unsigned int session_id; /* Session ID of the TA to be executed */ - unsigned int ta_cmd_id; /* Command ID to be sent to TA */ - struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ - -}; - - -/* Command to setup TMR region. */ -struct psp_gfx_cmd_setup_tmr -{ - unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ - unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ - unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ - union { - struct { - unsigned int sriov_enabled:1; /* whether the device runs under SR-IOV*/ - unsigned int virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/ - unsigned int reserved:30; - } bitfield; - unsigned int tmr_flags; - }; - unsigned int system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */ - unsigned int system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */ - -}; - -/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ -enum psp_gfx_fw_type { - GFX_FW_TYPE_NONE = 0, /* */ - GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */ - GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */ - GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */ - GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */ - GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */ - GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */ - GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */ - GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */ - GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */ - GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */ - GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */ - GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */ - GFX_FW_TYPE_VCN = 13, /* VCN RV */ - GFX_FW_TYPE_UVD = 14, /* UVD VG */ - GFX_FW_TYPE_VCE = 15, /* VCE VG */ - GFX_FW_TYPE_ISP = 16, /* ISP RV */ - GFX_FW_TYPE_ACP = 17, /* ACP RV */ - GFX_FW_TYPE_SMU = 18, /* SMU VG */ - GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */ - GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */ - GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */ - GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */ - GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */ - GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */ - GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */ - GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */ - GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */ - GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */ - GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */ - GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */ - GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */ - GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */ - GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */ - GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */ - GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */ - GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */ - GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */ - GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */ - GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */ - GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */ - GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */ - GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */ - GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */ - GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */ - GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */ - GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */ - GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */ - GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */ - GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */ - GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */ - GFX_FW_TYPE_DMUB = 51, /* DMUB RN */ - GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */ - GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */ - GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */ - GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */ - GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ - GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ - GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */ - GFX_FW_TYPE_CAP = 62, /* CAP_FW */ - GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */ - GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */ - GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */ - GFX_FW_TYPE_IMU_I = 68, /* IMU Instruction FW SOC21 */ - GFX_FW_TYPE_IMU_D = 69, /* IMU Data FW SOC21 */ - GFX_FW_TYPE_LSDMA = 70, /* LSDMA FW SOC21 */ - GFX_FW_TYPE_SDMA_UCODE_TH0 = 71, /* SDMA Thread 0/CTX SOC21 */ - GFX_FW_TYPE_SDMA_UCODE_TH1 = 72, /* SDMA Thread 1/CTL SOC21 */ - GFX_FW_TYPE_PPTABLE = 73, /* PPTABLE SOC21 */ - GFX_FW_TYPE_DISCRETE_USB4 = 74, /* dUSB4 FW SOC21 */ - GFX_FW_TYPE_TA = 75, /* SRIOV TA FW UUID SOC21 */ - GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */ - GFX_FW_TYPE_RS64_MES_STACK = 77, /* RS64 MES stack ucode SOC21 */ - GFX_FW_TYPE_RS64_KIQ = 78, /* RS64 KIQ ucode SOC21 */ - GFX_FW_TYPE_RS64_KIQ_STACK = 79, /* RS64 KIQ Heap stack SOC21 */ - GFX_FW_TYPE_ISP_DATA = 80, /* ISP DATA SOC21 */ - GFX_FW_TYPE_CP_MES_KIQ = 81, /* MES KIQ ucode SOC21 */ - GFX_FW_TYPE_MES_KIQ_STACK = 82, /* MES KIQ stack SOC21 */ - GFX_FW_TYPE_UMSCH_DATA = 83, /* User Mode Scheduler Data SOC21 */ - GFX_FW_TYPE_UMSCH_UCODE = 84, /* User Mode Scheduler Ucode SOC21 */ - GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85, /* User Mode Scheduler Command Buffer SOC21 */ - GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */ - GFX_FW_TYPE_RS64_PFP = 87, /* RS64 PFP SOC21 */ - GFX_FW_TYPE_RS64_ME = 88, /* RS64 ME SOC21 */ - GFX_FW_TYPE_RS64_MEC = 89, /* RS64 MEC SOC21 */ - GFX_FW_TYPE_RS64_PFP_P0_STACK = 90, /* RS64 PFP stack P0 SOC21 */ - GFX_FW_TYPE_RS64_PFP_P1_STACK = 91, /* RS64 PFP stack P1 SOC21 */ - GFX_FW_TYPE_RS64_ME_P0_STACK = 92, /* RS64 ME stack P0 SOC21 */ - GFX_FW_TYPE_RS64_ME_P1_STACK = 93, /* RS64 ME stack P1 SOC21 */ - GFX_FW_TYPE_RS64_MEC_P0_STACK = 94, /* RS64 MEC stack P0 SOC21 */ - GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ - GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ - GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ - GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */ - GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */ - GFX_FW_TYPE_VPE = 102, - GFX_FW_TYPE_JPEG_RAM = 128, /**< JPEG Command buffer */ - GFX_FW_TYPE_P2S_TABLE = 129, - GFX_FW_TYPE_MAX -}; - -/* Command to load HW IP FW. */ -struct psp_gfx_cmd_load_ip_fw -{ - unsigned int fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ - unsigned int fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ - unsigned int fw_size; /* FW buffer size in bytes */ - enum psp_gfx_fw_type fw_type; /* FW type */ - -}; - -/* Command to save/restore HW IP FW. */ -struct psp_gfx_cmd_save_restore_ip_fw -{ - unsigned int save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ - unsigned int save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ - unsigned int save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ - unsigned int buf_size; /* Size of the save/restore buffer in bytes */ - enum psp_gfx_fw_type fw_type; /* FW type */ -}; - -/* Command to setup register program */ -struct psp_gfx_cmd_reg_prog { - unsigned int reg_value; - unsigned int reg_id; -}; - -/* Command to load TOC */ -struct psp_gfx_cmd_load_toc -{ - unsigned int toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ - unsigned int toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ - unsigned int toc_size; /* FW buffer size in bytes */ -}; - -/* Dynamic boot configuration */ -struct psp_gfx_cmd_boot_cfg -{ - unsigned int timestamp; /* calendar time as number of seconds */ - enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process command data */ - unsigned int boot_config; /* dynamic boot configuration bitmask */ - unsigned int boot_config_valid; /* dynamic boot configuration valid bits bitmask */ -}; - -struct psp_gfx_cmd_sriov_spatial_part { - unsigned int mode; - unsigned int override_ips; - unsigned int override_xcds_avail; - unsigned int override_this_aid; -}; - -/* All GFX ring buffer commands. */ -union psp_gfx_commands -{ - struct psp_gfx_cmd_load_ta cmd_load_ta; - struct psp_gfx_cmd_unload_ta cmd_unload_ta; - struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; - struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; - struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; - struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; - struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog; - struct psp_gfx_cmd_setup_tmr cmd_setup_vmr; - struct psp_gfx_cmd_load_toc cmd_load_toc; - struct psp_gfx_cmd_boot_cfg boot_cfg; - struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; -}; - -struct psp_gfx_uresp_reserved -{ - unsigned int reserved[8]; -}; - -/* Command-specific response for Fw Attestation Db */ -struct psp_gfx_uresp_fwar_db_info -{ - unsigned int fwar_db_addr_lo; - unsigned int fwar_db_addr_hi; -}; - -/* Command-specific response for boot config. */ -struct psp_gfx_uresp_bootcfg { - unsigned int boot_cfg; /* boot config data */ -}; - -/* Union of command-specific responses for GPCOM ring. */ -union psp_gfx_uresp { - struct psp_gfx_uresp_reserved reserved; - struct psp_gfx_uresp_bootcfg boot_cfg; - struct psp_gfx_uresp_fwar_db_info fwar_db_info; -}; - -/* Structure of GFX Response buffer. -* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI -* it is separate buffer. -*/ -struct psp_gfx_resp -{ - unsigned int status; /* +0 status of command execution */ - unsigned int session_id; /* +4 session ID in response to LoadTa command */ - unsigned int fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ - unsigned int fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ - unsigned int tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */ - - unsigned int reserved[11]; - - union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */ - - /* total 96 bytes */ -}; - -/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi -* and psp_gfx_rb_frame.cmd_buf_addr_lo. -*/ -struct psp_gfx_cmd_resp -{ - unsigned int buf_size; /* +0 total size of the buffer in bytes */ - unsigned int buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ - unsigned int cmd_id; /* +8 command ID */ - - /* These fields are used for RBI only. They are all 0 in GPCOM commands - */ - unsigned int resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ - unsigned int resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ - unsigned int resp_offset; /* +20 offset within response buffer */ - unsigned int resp_buf_size; /* +24 total size of the response buffer in bytes */ - - union psp_gfx_commands cmd; /* +28 command specific structures */ - - unsigned char reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; - - /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response - * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. - */ - struct psp_gfx_resp resp; /* +864 response */ - - unsigned char reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; - - /* total size 1024 bytes */ -}; - - -#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ - -/* Structure of the Ring Buffer Frame */ -struct psp_gfx_rb_frame -{ - unsigned int cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ - unsigned int cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ - unsigned int cmd_buf_size; /* +8 command buffer size in bytes */ - unsigned int fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ - unsigned int fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ - unsigned int fence_value; /* +20 Fence value */ - unsigned int sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ - unsigned int sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ - unsigned char vmid; /* +32 VMID value used for mapping of all addresses for this frame */ - unsigned char frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ - unsigned char reserved1[2]; /* +34 reserved, must be 0 */ - unsigned int reserved2[7]; /* +36 reserved, must be 0 */ - /* total 64 bytes */ -}; - -#define PSP_ERR_UNKNOWN_COMMAND 0x00000100 - -enum tee_error_code { - TEE_SUCCESS = 0x00000000, - TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A, -}; - -#endif /* _PSP_TEE_GFX_IF_H_ */ diff --git a/tinygrad/extra/amdpci/headers/v11_structs.h b/tinygrad/extra/amdpci/headers/v11_structs.h deleted file mode 100644 index cfc28a75..00000000 --- a/tinygrad/extra/amdpci/headers/v11_structs.h +++ /dev/null @@ -1,1194 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef V11_STRUCTS_H_ -#define V11_STRUCTS_H_ - -#define uint32_t unsigned int -#define uint8_t unsigned char -#define uint16_t unsigned short -#define uint64_t unsigned long long - -struct v11_gfx_mqd { - uint32_t shadow_base_lo; // offset: 0 (0x0) - uint32_t shadow_base_hi; // offset: 1 (0x1) - uint32_t gds_bkup_base_lo; // offset: 2 (0x2) - uint32_t gds_bkup_base_hi; // offset: 3 (0x3) - uint32_t fw_work_area_base_lo; // offset: 4 (0x4) - uint32_t fw_work_area_base_hi; // offset: 5 (0x5) - uint32_t shadow_initialized; // offset: 6 (0x6) - uint32_t ib_vmid; // offset: 7 (0x7) - uint32_t reserved_8; // offset: 8 (0x8) - uint32_t reserved_9; // offset: 9 (0x9) - uint32_t reserved_10; // offset: 10 (0xA) - uint32_t reserved_11; // offset: 11 (0xB) - uint32_t reserved_12; // offset: 12 (0xC) - uint32_t reserved_13; // offset: 13 (0xD) - uint32_t reserved_14; // offset: 14 (0xE) - uint32_t reserved_15; // offset: 15 (0xF) - uint32_t reserved_16; // offset: 16 (0x10) - uint32_t reserved_17; // offset: 17 (0x11) - uint32_t reserved_18; // offset: 18 (0x12) - uint32_t reserved_19; // offset: 19 (0x13) - uint32_t reserved_20; // offset: 20 (0x14) - uint32_t reserved_21; // offset: 21 (0x15) - uint32_t reserved_22; // offset: 22 (0x16) - uint32_t reserved_23; // offset: 23 (0x17) - uint32_t reserved_24; // offset: 24 (0x18) - uint32_t reserved_25; // offset: 25 (0x19) - uint32_t reserved_26; // offset: 26 (0x1A) - uint32_t reserved_27; // offset: 27 (0x1B) - uint32_t reserved_28; // offset: 28 (0x1C) - uint32_t reserved_29; // offset: 29 (0x1D) - uint32_t reserved_30; // offset: 30 (0x1E) - uint32_t reserved_31; // offset: 31 (0x1F) - uint32_t reserved_32; // offset: 32 (0x20) - uint32_t reserved_33; // offset: 33 (0x21) - uint32_t reserved_34; // offset: 34 (0x22) - uint32_t reserved_35; // offset: 35 (0x23) - uint32_t reserved_36; // offset: 36 (0x24) - uint32_t reserved_37; // offset: 37 (0x25) - uint32_t reserved_38; // offset: 38 (0x26) - uint32_t reserved_39; // offset: 39 (0x27) - uint32_t reserved_40; // offset: 40 (0x28) - uint32_t reserved_41; // offset: 41 (0x29) - uint32_t reserved_42; // offset: 42 (0x2A) - uint32_t reserved_43; // offset: 43 (0x2B) - uint32_t reserved_44; // offset: 44 (0x2C) - uint32_t reserved_45; // offset: 45 (0x2D) - uint32_t reserved_46; // offset: 46 (0x2E) - uint32_t reserved_47; // offset: 47 (0x2F) - uint32_t reserved_48; // offset: 48 (0x30) - uint32_t reserved_49; // offset: 49 (0x31) - uint32_t reserved_50; // offset: 50 (0x32) - uint32_t reserved_51; // offset: 51 (0x33) - uint32_t reserved_52; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t reserved_59; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t reserved_65; // offset: 65 (0x41) - uint32_t reserved_66; // offset: 66 (0x42) - uint32_t reserved_67; // offset: 67 (0x43) - uint32_t reserved_68; // offset: 68 (0x44) - uint32_t reserved_69; // offset: 69 (0x45) - uint32_t reserved_70; // offset: 70 (0x46) - uint32_t reserved_71; // offset: 71 (0x47) - uint32_t reserved_72; // offset: 72 (0x48) - uint32_t reserved_73; // offset: 73 (0x49) - uint32_t reserved_74; // offset: 74 (0x4A) - uint32_t reserved_75; // offset: 75 (0x4B) - uint32_t reserved_76; // offset: 76 (0x4C) - uint32_t reserved_77; // offset: 77 (0x4D) - uint32_t reserved_78; // offset: 78 (0x4E) - uint32_t reserved_79; // offset: 79 (0x4F) - uint32_t reserved_80; // offset: 80 (0x50) - uint32_t reserved_81; // offset: 81 (0x51) - uint32_t reserved_82; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t checksum_lo; // offset: 84 (0x54) - uint32_t checksum_hi; // offset: 85 (0x55) - uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) - uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) - uint32_t reserved_88; // offset: 88 (0x58) - uint32_t reserved_89; // offset: 89 (0x59) - uint32_t reserved_90; // offset: 90 (0x5A) - uint32_t reserved_91; // offset: 91 (0x5B) - uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C) - uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D) - uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E) - uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F) - uint32_t reserved_96; // offset: 96 (0x60) - uint32_t reserved_97; // offset: 97 (0x61) - uint32_t reserved_98; // offset: 98 (0x62) - uint32_t reserved_99; // offset: 99 (0x63) - uint32_t reserved_100; // offset: 100 (0x64) - uint32_t reserved_101; // offset: 101 (0x65) - uint32_t reserved_102; // offset: 102 (0x66) - uint32_t reserved_103; // offset: 103 (0x67) - uint32_t control_buf_addr_lo; // offset: 104 (0x68) - uint32_t control_buf_addr_hi; // offset: 105 (0x69) - uint32_t disable_queue; // offset: 106 (0x6A) - uint32_t reserved_107; // offset: 107 (0x6B) - uint32_t reserved_108; // offset: 108 (0x6C) - uint32_t reserved_109; // offset: 109 (0x6D) - uint32_t reserved_110; // offset: 110 (0x6E) - uint32_t reserved_111; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t reserved_114; // offset: 114 (0x72) - uint32_t reserved_115; // offset: 115 (0x73) - uint32_t reserved_116; // offset: 116 (0x74) - uint32_t reserved_117; // offset: 117 (0x75) - uint32_t reserved_118; // offset: 118 (0x76) - uint32_t reserved_119; // offset: 119 (0x77) - uint32_t reserved_120; // offset: 120 (0x78) - uint32_t reserved_121; // offset: 121 (0x79) - uint32_t reserved_122; // offset: 122 (0x7A) - uint32_t reserved_123; // offset: 123 (0x7B) - uint32_t reserved_124; // offset: 124 (0x7C) - uint32_t reserved_125; // offset: 125 (0x7D) - uint32_t reserved_126; // offset: 126 (0x7E) - uint32_t reserved_127; // offset: 127 (0x7F) - uint32_t cp_mqd_base_addr; // offset: 128 (0x80) - uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) - uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) - uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) - uint32_t reserved_131; // offset: 132 (0x84) - uint32_t reserved_132; // offset: 133 (0x85) - uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) - uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) - uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) - uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) - uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) - uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) - uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) - uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) - uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) - uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) - uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) - uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) - uint32_t reserved_146; // offset: 146 (0x92) - uint32_t reserved_147; // offset: 147 (0x93) - uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) - uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) - uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) - uint32_t reserved_151; // offset: 151 (0x97) - uint32_t reserved_152; // offset: 152 (0x98) - uint32_t reserved_153; // offset: 153 (0x99) - uint32_t reserved_154; // offset: 154 (0x9A) - uint32_t reserved_155; // offset: 155 (0x9B) - uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) - uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) - uint32_t reserved_158; // offset: 158 (0x9E) - uint32_t reserved_159; // offset: 159 (0x9F) - uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) - uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) - uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) - uint32_t reserved_163; // offset: 163 (0xA3) - uint32_t reserved_164; // offset: 164 (0xA4) - uint32_t reserved_165; // offset: 165 (0xA5) - uint32_t reserved_166; // offset: 166 (0xA6) - uint32_t reserved_167; // offset: 167 (0xA7) - uint32_t reserved_168; // offset: 168 (0xA8) - uint32_t reserved_169; // offset: 169 (0xA9) - uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA) - uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB) - uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC) - uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD) - uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE) - uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF) - uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0) - uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1) - uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2) - uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3) - uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4) - uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5) - uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6) - uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7) - uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8) - uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9) - uint32_t reserved_186; // offset: 186 (0xBA) - uint32_t reserved_187; // offset: 187 (0xBB) - uint32_t reserved_188; // offset: 188 (0xBC) - uint32_t reserved_189; // offset: 189 (0xBD) - uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE) - uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF) - uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0) - uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1) - uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2) - uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3) - uint32_t sq_thread_trace_mask; // offset: 196 (0xC4) - uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5) - uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6) - uint32_t sq_thread_trace_status; // offset: 199 (0xC7) - uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8) - uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9) - uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA) - uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB) - uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC) - uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD) - uint32_t reserved_206; // offset: 206 (0xCE) - uint32_t reserved_207; // offset: 207 (0xCF) - uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0) - uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1) - uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2) - uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3) - uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4) - uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5) - uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6) - uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7) - uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8) - uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9) - uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA) - uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB) - uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC) - uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD) - uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE) - uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF) - uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0) - uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1) - uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2) - uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3) - uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4) - uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5) - uint32_t reserved_230; // offset: 230 (0xE6) - uint32_t reserved_231; // offset: 231 (0xE7) - uint32_t reserved_232; // offset: 232 (0xE8) - uint32_t reserved_233; // offset: 233 (0xE9) - uint32_t reserved_234; // offset: 234 (0xEA) - uint32_t reserved_235; // offset: 235 (0xEB) - uint32_t reserved_236; // offset: 236 (0xEC) - uint32_t reserved_237; // offset: 237 (0xED) - uint32_t reserved_238; // offset: 238 (0xEE) - uint32_t reserved_239; // offset: 239 (0xEF) - uint32_t reserved_240; // offset: 240 (0xF0) - uint32_t reserved_241; // offset: 241 (0xF1) - uint32_t reserved_242; // offset: 242 (0xF2) - uint32_t reserved_243; // offset: 243 (0xF3) - uint32_t reserved_244; // offset: 244 (0xF4) - uint32_t reserved_245; // offset: 245 (0xF5) - uint32_t reserved_246; // offset: 246 (0xF6) - uint32_t reserved_247; // offset: 247 (0xF7) - uint32_t reserved_248; // offset: 248 (0xF8) - uint32_t reserved_249; // offset: 249 (0xF9) - uint32_t reserved_250; // offset: 250 (0xFA) - uint32_t reserved_251; // offset: 251 (0xFB) - uint32_t reserved_252; // offset: 252 (0xFC) - uint32_t reserved_253; // offset: 253 (0xFD) - uint32_t reserved_254; // offset: 254 (0xFE) - uint32_t reserved_255; // offset: 255 (0xFF) - uint32_t reserved_256; // offset: 256 (0x100) - uint32_t reserved_257; // offset: 257 (0x101) - uint32_t reserved_258; // offset: 258 (0x102) - uint32_t reserved_259; // offset: 259 (0x103) - uint32_t reserved_260; // offset: 260 (0x104) - uint32_t reserved_261; // offset: 261 (0x105) - uint32_t reserved_262; // offset: 262 (0x106) - uint32_t reserved_263; // offset: 263 (0x107) - uint32_t reserved_264; // offset: 264 (0x108) - uint32_t reserved_265; // offset: 265 (0x109) - uint32_t reserved_266; // offset: 266 (0x10A) - uint32_t reserved_267; // offset: 267 (0x10B) - uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C) - uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D) - uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E) - uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F) - uint32_t reserved_272; // offset: 272 (0x110) - uint32_t reserved_273; // offset: 273 (0x111) - uint32_t reserved_274; // offset: 274 (0x112) - uint32_t reserved_275; // offset: 275 (0x113) - uint32_t vgt_dma_max_size; // offset: 276 (0x114) - uint32_t vgt_dma_num_instances; // offset: 277 (0x115) - uint32_t reserved_278; // offset: 278 (0x116) - uint32_t reserved_279; // offset: 279 (0x117) - uint32_t reserved_280; // offset: 280 (0x118) - uint32_t reserved_281; // offset: 281 (0x119) - uint32_t reserved_282; // offset: 282 (0x11A) - uint32_t reserved_283; // offset: 283 (0x11B) - uint32_t reserved_284; // offset: 284 (0x11C) - uint32_t reserved_285; // offset: 285 (0x11D) - uint32_t reserved_286; // offset: 286 (0x11E) - uint32_t reserved_287; // offset: 287 (0x11F) - uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120) - uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121) - uint32_t reserved_290; // offset: 290 (0x122) - uint32_t reserved_291; // offset: 291 (0x123) - uint32_t reserved_292; // offset: 292 (0x124) - uint32_t reserved_293; // offset: 293 (0x125) - uint32_t reserved_294; // offset: 294 (0x126) - uint32_t reserved_295; // offset: 295 (0x127) - uint32_t reserved_296; // offset: 296 (0x128) - uint32_t reserved_297; // offset: 297 (0x129) - uint32_t reserved_298; // offset: 298 (0x12A) - uint32_t reserved_299; // offset: 299 (0x12B) - uint32_t reserved_300; // offset: 300 (0x12C) - uint32_t reserved_301; // offset: 301 (0x12D) - uint32_t reserved_302; // offset: 302 (0x12E) - uint32_t reserved_303; // offset: 303 (0x12F) - uint32_t reserved_304; // offset: 304 (0x130) - uint32_t reserved_305; // offset: 305 (0x131) - uint32_t reserved_306; // offset: 306 (0x132) - uint32_t reserved_307; // offset: 307 (0x133) - uint32_t reserved_308; // offset: 308 (0x134) - uint32_t reserved_309; // offset: 309 (0x135) - uint32_t reserved_310; // offset: 310 (0x136) - uint32_t reserved_311; // offset: 311 (0x137) - uint32_t reserved_312; // offset: 312 (0x138) - uint32_t reserved_313; // offset: 313 (0x139) - uint32_t reserved_314; // offset: 314 (0x13A) - uint32_t reserved_315; // offset: 315 (0x13B) - uint32_t reserved_316; // offset: 316 (0x13C) - uint32_t reserved_317; // offset: 317 (0x13D) - uint32_t reserved_318; // offset: 318 (0x13E) - uint32_t reserved_319; // offset: 319 (0x13F) - uint32_t reserved_320; // offset: 320 (0x140) - uint32_t reserved_321; // offset: 321 (0x141) - uint32_t reserved_322; // offset: 322 (0x142) - uint32_t reserved_323; // offset: 323 (0x143) - uint32_t reserved_324; // offset: 324 (0x144) - uint32_t reserved_325; // offset: 325 (0x145) - uint32_t reserved_326; // offset: 326 (0x146) - uint32_t reserved_327; // offset: 327 (0x147) - uint32_t reserved_328; // offset: 328 (0x148) - uint32_t reserved_329; // offset: 329 (0x149) - uint32_t reserved_330; // offset: 330 (0x14A) - uint32_t reserved_331; // offset: 331 (0x14B) - uint32_t reserved_332; // offset: 332 (0x14C) - uint32_t reserved_333; // offset: 333 (0x14D) - uint32_t reserved_334; // offset: 334 (0x14E) - uint32_t reserved_335; // offset: 335 (0x14F) - uint32_t reserved_336; // offset: 336 (0x150) - uint32_t reserved_337; // offset: 337 (0x151) - uint32_t reserved_338; // offset: 338 (0x152) - uint32_t reserved_339; // offset: 339 (0x153) - uint32_t reserved_340; // offset: 340 (0x154) - uint32_t reserved_341; // offset: 341 (0x155) - uint32_t reserved_342; // offset: 342 (0x156) - uint32_t reserved_343; // offset: 343 (0x157) - uint32_t reserved_344; // offset: 344 (0x158) - uint32_t reserved_345; // offset: 345 (0x159) - uint32_t reserved_346; // offset: 346 (0x15A) - uint32_t reserved_347; // offset: 347 (0x15B) - uint32_t reserved_348; // offset: 348 (0x15C) - uint32_t reserved_349; // offset: 349 (0x15D) - uint32_t reserved_350; // offset: 350 (0x15E) - uint32_t reserved_351; // offset: 351 (0x15F) - uint32_t reserved_352; // offset: 352 (0x160) - uint32_t reserved_353; // offset: 353 (0x161) - uint32_t reserved_354; // offset: 354 (0x162) - uint32_t reserved_355; // offset: 355 (0x163) - uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164) - uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165) - uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166) - uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167) - uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168) - uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169) - uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A) - uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B) - uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C) - uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D) - uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E) - uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F) - uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170) - uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171) - uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172) - uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173) - uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174) - uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175) - uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176) - uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177) - uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178) - uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179) - uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A) - uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B) - uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C) - uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D) - uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E) - uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F) - uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180) - uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181) - uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182) - uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183) - uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184) - uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185) - uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186) - uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187) - uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188) - uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189) - uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A) - uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B) - uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C) - uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D) - uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E) - uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F) - uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190) - uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191) - uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192) - uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193) - uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194) - uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195) - uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196) - uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197) - uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198) - uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199) - uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A) - uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B) - uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C) - uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D) - uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E) - uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F) - uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0) - uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1) - uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2) - uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3) - uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4) - uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5) - uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6) - uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7) - uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8) - uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9) - uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA) - uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB) - uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC) - uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD) - uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE) - uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF) - uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0) - uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1) - uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2) - uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3) - uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4) - uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5) - uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6) - uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7) - uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8) - uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9) - uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA) - uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB) - uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC) - uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD) - uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE) - uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF) - uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0) - uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1) - uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2) - uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3) - uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4) - uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5) - uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6) - uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7) - uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8) - uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9) - uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA) - uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB) - uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC) - uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD) - uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE) - uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF) - uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0) - uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1) - uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2) - uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3) - uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4) - uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5) - uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6) - uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7) - uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8) - uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9) - uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA) - uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB) - uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC) - uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD) - uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE) - uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF) - uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0) - uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1) - uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2) - uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3) - uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4) - uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5) - uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6) - uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7) - uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8) - uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9) - uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA) - uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB) - uint32_t reserved_492; // offset: 492 (0x1EC) - uint32_t reserved_493; // offset: 493 (0x1ED) - uint32_t reserved_494; // offset: 494 (0x1EE) - uint32_t reserved_495; // offset: 495 (0x1EF) - uint32_t reserved_496; // offset: 496 (0x1F0) - uint32_t reserved_497; // offset: 497 (0x1F1) - uint32_t reserved_498; // offset: 498 (0x1F2) - uint32_t reserved_499; // offset: 499 (0x1F3) - uint32_t reserved_500; // offset: 500 (0x1F4) - uint32_t reserved_501; // offset: 501 (0x1F5) - uint32_t reserved_502; // offset: 502 (0x1F6) - uint32_t reserved_503; // offset: 503 (0x1F7) - uint32_t reserved_504; // offset: 504 (0x1F8) - uint32_t reserved_505; // offset: 505 (0x1F9) - uint32_t reserved_506; // offset: 506 (0x1FA) - uint32_t reserved_507; // offset: 507 (0x1FB) - uint32_t reserved_508; // offset: 508 (0x1FC) - uint32_t reserved_509; // offset: 509 (0x1FD) - uint32_t reserved_510; // offset: 510 (0x1FE) - uint32_t reserved_511; // offset: 511 (0x1FF) -}; - -struct v11_sdma_mqd { - uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0) - uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1) - uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) - uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3) - uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4) - uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5) - uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6) - uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 7 (0x7) - uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 8 (0x8) - uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9) - uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA) - uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB) - uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC) - uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD) - uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE) - uint32_t sdmax_rlcx_skip_cntl; // offset: 15 (0xF) - uint32_t sdmax_rlcx_context_status; // offset: 16 (0x10) - uint32_t sdmax_rlcx_doorbell; // offset: 17 (0x11) - uint32_t sdmax_rlcx_doorbell_log; // offset: 18 (0x12) - uint32_t sdmax_rlcx_doorbell_offset; // offset: 19 (0x13) - uint32_t sdmax_rlcx_csa_addr_lo; // offset: 20 (0x14) - uint32_t sdmax_rlcx_csa_addr_hi; // offset: 21 (0x15) - uint32_t sdmax_rlcx_sched_cntl; // offset: 22 (0x16) - uint32_t sdmax_rlcx_ib_sub_remain; // offset: 23 (0x17) - uint32_t sdmax_rlcx_preempt; // offset: 24 (0x18) - uint32_t sdmax_rlcx_dummy_reg; // offset: 25 (0x19) - uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 26 (0x1A) - uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 27 (0x1B) - uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 28 (0x1C) - uint32_t sdmax_rlcx_minor_ptr_update; // offset: 29 (0x1D) - uint32_t sdmax_rlcx_rb_preempt; // offset: 30 (0x1E) - uint32_t sdmax_rlcx_midcmd_data0; // offset: 31 (0x1F) - uint32_t sdmax_rlcx_midcmd_data1; // offset: 32 (0x20) - uint32_t sdmax_rlcx_midcmd_data2; // offset: 33 (0x21) - uint32_t sdmax_rlcx_midcmd_data3; // offset: 34 (0x22) - uint32_t sdmax_rlcx_midcmd_data4; // offset: 35 (0x23) - uint32_t sdmax_rlcx_midcmd_data5; // offset: 36 (0x24) - uint32_t sdmax_rlcx_midcmd_data6; // offset: 37 (0x25) - uint32_t sdmax_rlcx_midcmd_data7; // offset: 38 (0x26) - uint32_t sdmax_rlcx_midcmd_data8; // offset: 39 (0x27) - uint32_t sdmax_rlcx_midcmd_data9; // offset: 40 (0x28) - uint32_t sdmax_rlcx_midcmd_data10; // offset: 41 (0x29) - uint32_t sdmax_rlcx_midcmd_cntl; // offset: 42 (0x2A) - uint32_t sdmax_rlcx_f32_dbg0; // offset: 43 (0x2B) - uint32_t sdmax_rlcx_f32_dbg1; // offset: 44 (0x2C) - uint32_t reserved_45; // offset: 45 (0x2D) - uint32_t reserved_46; // offset: 46 (0x2E) - uint32_t reserved_47; // offset: 47 (0x2F) - uint32_t reserved_48; // offset: 48 (0x30) - uint32_t reserved_49; // offset: 49 (0x31) - uint32_t reserved_50; // offset: 50 (0x32) - uint32_t reserved_51; // offset: 51 (0x33) - uint32_t reserved_52; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t reserved_59; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t reserved_65; // offset: 65 (0x41) - uint32_t reserved_66; // offset: 66 (0x42) - uint32_t reserved_67; // offset: 67 (0x43) - uint32_t reserved_68; // offset: 68 (0x44) - uint32_t reserved_69; // offset: 69 (0x45) - uint32_t reserved_70; // offset: 70 (0x46) - uint32_t reserved_71; // offset: 0 (0x47) - uint32_t reserved_72; // offset: 1 (0x48) - uint32_t reserved_73; // offset: 2 (0x49) - uint32_t reserved_74; // offset: 3 (0x4A) - uint32_t reserved_75; // offset: 4 (0x4B) - uint32_t reserved_76; // offset: 5 (0x4C) - uint32_t reserved_77; // offset: 6 (0x4D) - uint32_t reserved_78; // offset: 7 (0x4E) - uint32_t reserved_79; // offset: 79 (0x4F) - uint32_t reserved_80; // offset: 80 (0x50) - uint32_t reserved_81; // offset: 81 (0x51) - uint32_t reserved_82; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t reserved_84; // offset: 84 (0x54) - uint32_t reserved_85; // offset: 85 (0x55) - uint32_t reserved_86; // offset: 86 (0x56) - uint32_t reserved_87; // offset: 87 (0x57) - uint32_t reserved_88; // offset: 88 (0x58) - uint32_t reserved_89; // offset: 89 (0x59) - uint32_t reserved_90; // offset: 90 (0x5A) - uint32_t reserved_91; // offset: 91 (0x5B) - uint32_t reserved_92; // offset: 92 (0x5C) - uint32_t reserved_93; // offset: 93 (0x5D) - uint32_t reserved_94; // offset: 94 (0x5E) - uint32_t reserved_95; // offset: 95 (0x5F) - uint32_t reserved_96; // offset: 96 (0x60) - uint32_t reserved_97; // offset: 97 (0x61) - uint32_t reserved_98; // offset: 98 (0x62) - uint32_t reserved_99; // offset: 99 (0x63) - uint32_t reserved_100; // offset: 100 (0x64) - uint32_t reserved_101; // offset: 101 (0x65) - uint32_t reserved_102; // offset: 102 (0x66) - uint32_t reserved_103; // offset: 103 (0x67) - uint32_t reserved_104; // offset: 104 (0x68) - uint32_t reserved_105; // offset: 105 (0x69) - uint32_t reserved_106; // offset: 106 (0x6A) - uint32_t reserved_107; // offset: 107 (0x6B) - uint32_t reserved_108; // offset: 108 (0x6C) - uint32_t reserved_109; // offset: 109 (0x6D) - uint32_t reserved_110; // offset: 110 (0x6E) - uint32_t reserved_111; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t reserved_114; // offset: 114 (0x72) - uint32_t reserved_115; // offset: 115 (0x73) - uint32_t reserved_116; // offset: 116 (0x74) - uint32_t reserved_117; // offset: 117 (0x75) - uint32_t reserved_118; // offset: 118 (0x76) - uint32_t reserved_119; // offset: 119 (0x77) - uint32_t reserved_120; // offset: 120 (0x78) - uint32_t reserved_121; // offset: 121 (0x79) - uint32_t reserved_122; // offset: 122 (0x7A) - uint32_t reserved_123; // offset: 123 (0x7B) - uint32_t reserved_124; // offset: 124 (0x7C) - uint32_t reserved_125; // offset: 125 (0x7D) - /* reserved_126,127: repurposed for driver-internal use */ - uint32_t sdma_engine_id; - uint32_t sdma_queue_id; -}; - -struct v11_compute_mqd { - uint32_t header; // offset: 0 (0x0) - uint32_t compute_dispatch_initiator; // offset: 1 (0x1) - uint32_t compute_dim_x; // offset: 2 (0x2) - uint32_t compute_dim_y; // offset: 3 (0x3) - uint32_t compute_dim_z; // offset: 4 (0x4) - uint32_t compute_start_x; // offset: 5 (0x5) - uint32_t compute_start_y; // offset: 6 (0x6) - uint32_t compute_start_z; // offset: 7 (0x7) - uint32_t compute_num_thread_x; // offset: 8 (0x8) - uint32_t compute_num_thread_y; // offset: 9 (0x9) - uint32_t compute_num_thread_z; // offset: 10 (0xA) - uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) - uint32_t compute_perfcount_enable; // offset: 12 (0xC) - uint32_t compute_pgm_lo; // offset: 13 (0xD) - uint32_t compute_pgm_hi; // offset: 14 (0xE) - uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) - uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) - uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) - uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) - uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) - uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) - uint32_t compute_vmid; // offset: 21 (0x15) - uint32_t compute_resource_limits; // offset: 22 (0x16) - uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17) - uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18) - uint32_t compute_tmpring_size; // offset: 25 (0x19) - uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A) - uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B) - uint32_t compute_restart_x; // offset: 28 (0x1C) - uint32_t compute_restart_y; // offset: 29 (0x1D) - uint32_t compute_restart_z; // offset: 30 (0x1E) - uint32_t compute_thread_trace_enable; // offset: 31 (0x1F) - uint32_t compute_misc_reserved; // offset: 32 (0x20) - uint32_t compute_dispatch_id; // offset: 33 (0x21) - uint32_t compute_threadgroup_id; // offset: 34 (0x22) - uint32_t compute_req_ctrl; // offset: 35 (0x23) - uint32_t reserved_36; // offset: 36 (0x24) - uint32_t compute_user_accum_0; // offset: 37 (0x25) - uint32_t compute_user_accum_1; // offset: 38 (0x26) - uint32_t compute_user_accum_2; // offset: 39 (0x27) - uint32_t compute_user_accum_3; // offset: 40 (0x28) - uint32_t compute_pgm_rsrc3; // offset: 41 (0x29) - uint32_t compute_ddid_index; // offset: 42 (0x2A) - uint32_t compute_shader_chksum; // offset: 43 (0x2B) - uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C) - uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D) - uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E) - uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F) - uint32_t compute_dispatch_interleave; // offset: 48 (0x30) - uint32_t compute_relaunch; // offset: 49 (0x31) - uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32) - uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33) - uint32_t compute_wave_restore_control; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t reserved_59; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t compute_user_data_0; // offset: 65 (0x41) - uint32_t compute_user_data_1; // offset: 66 (0x42) - uint32_t compute_user_data_2; // offset: 67 (0x43) - uint32_t compute_user_data_3; // offset: 68 (0x44) - uint32_t compute_user_data_4; // offset: 69 (0x45) - uint32_t compute_user_data_5; // offset: 70 (0x46) - uint32_t compute_user_data_6; // offset: 71 (0x47) - uint32_t compute_user_data_7; // offset: 72 (0x48) - uint32_t compute_user_data_8; // offset: 73 (0x49) - uint32_t compute_user_data_9; // offset: 74 (0x4A) - uint32_t compute_user_data_10; // offset: 75 (0x4B) - uint32_t compute_user_data_11; // offset: 76 (0x4C) - uint32_t compute_user_data_12; // offset: 77 (0x4D) - uint32_t compute_user_data_13; // offset: 78 (0x4E) - uint32_t compute_user_data_14; // offset: 79 (0x4F) - uint32_t compute_user_data_15; // offset: 80 (0x50) - uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51) - uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t reserved_84; // offset: 84 (0x54) - uint32_t reserved_85; // offset: 85 (0x55) - uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) - uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) - uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58) - uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59) - uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A) - uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B) - uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C) - uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D) - uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E) - uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F) - uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60) - uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61) - uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62) - uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63) - uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64) - uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65) - uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66) - uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67) - uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68) - uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69) - uint32_t disable_queue; // offset: 106 (0x6A) - uint32_t reserved_107; // offset: 107 (0x6B) - uint32_t gds_cs_ctxsw_cnt0; // offset: 108 (0x6C) - uint32_t gds_cs_ctxsw_cnt1; // offset: 109 (0x6D) - uint32_t gds_cs_ctxsw_cnt2; // offset: 110 (0x6E) - uint32_t gds_cs_ctxsw_cnt3; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) - uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) - uint32_t cp_packet_id_lo; // offset: 116 (0x74) - uint32_t cp_packet_id_hi; // offset: 117 (0x75) - uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) - uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) - uint32_t gds_save_base_addr_lo; // offset: 120 (0x78) - uint32_t gds_save_base_addr_hi; // offset: 121 (0x79) - uint32_t gds_save_mask_lo; // offset: 122 (0x7A) - uint32_t gds_save_mask_hi; // offset: 123 (0x7B) - uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) - uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) - uint32_t reserved_126; // offset: 126 (0x7E) - uint32_t reserved_127; // offset: 127 (0x7F) - uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) - uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) - uint32_t cp_hqd_active; // offset: 130 (0x82) - uint32_t cp_hqd_vmid; // offset: 131 (0x83) - uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) - uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) - uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) - uint32_t cp_hqd_quantum; // offset: 135 (0x87) - uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) - uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) - uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) - uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) - uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) - uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) - uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) - uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) - uint32_t reserved_144; // offset: 144 (0x90) - uint32_t cp_hqd_pq_control; // offset: 145 (0x91) - uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) - uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) - uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) - uint32_t cp_hqd_ib_control; // offset: 149 (0x95) - uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) - uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) - uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) - uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) - uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) - uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) - uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) - uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) - uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) - uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) - uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) - uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) - uint32_t cp_mqd_control; // offset: 162 (0xA2) - uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) - uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) - uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) - uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) - uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) - uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) - uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) - uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) - uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) - uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) - uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) - uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) - uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) - uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) - uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) - uint32_t cp_hqd_gds_resource_state; // offset: 178 (0xB2) - uint32_t cp_hqd_error; // offset: 179 (0xB3) - uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) - uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) - uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) - uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) - uint32_t reserved_184; // offset: 184 (0xB8) - uint32_t reserved_185; // offset: 185 (0xB9) - uint32_t reserved_186; // offset: 186 (0xBA) - uint32_t reserved_187; // offset: 187 (0xBB) - uint32_t reserved_188; // offset: 188 (0xBC) - uint32_t reserved_189; // offset: 189 (0xBD) - uint32_t reserved_190; // offset: 190 (0xBE) - uint32_t reserved_191; // offset: 191 (0xBF) - uint32_t iqtimer_pkt_header; // offset: 192 (0xC0) - uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1) - uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2) - uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3) - uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4) - uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5) - uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6) - uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7) - uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8) - uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9) - uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA) - uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB) - uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC) - uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD) - uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE) - uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF) - uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0) - uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1) - uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2) - uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3) - uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4) - uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5) - uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6) - uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7) - uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8) - uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9) - uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA) - uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB) - uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC) - uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD) - uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE) - uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF) - uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0) - uint32_t reserved_225; // offset: 225 (0xE1) - uint32_t reserved_226; // offset: 226 (0xE2) - uint32_t reserved_227; // offset: 227 (0xE3) - uint32_t set_resources_header; // offset: 228 (0xE4) - uint32_t set_resources_dw1; // offset: 229 (0xE5) - uint32_t set_resources_dw2; // offset: 230 (0xE6) - uint32_t set_resources_dw3; // offset: 231 (0xE7) - uint32_t set_resources_dw4; // offset: 232 (0xE8) - uint32_t set_resources_dw5; // offset: 233 (0xE9) - uint32_t set_resources_dw6; // offset: 234 (0xEA) - uint32_t set_resources_dw7; // offset: 235 (0xEB) - uint32_t reserved_236; // offset: 236 (0xEC) - uint32_t reserved_237; // offset: 237 (0xED) - uint32_t reserved_238; // offset: 238 (0xEE) - uint32_t reserved_239; // offset: 239 (0xEF) - uint32_t queue_doorbell_id0; // offset: 240 (0xF0) - uint32_t queue_doorbell_id1; // offset: 241 (0xF1) - uint32_t queue_doorbell_id2; // offset: 242 (0xF2) - uint32_t queue_doorbell_id3; // offset: 243 (0xF3) - uint32_t queue_doorbell_id4; // offset: 244 (0xF4) - uint32_t queue_doorbell_id5; // offset: 245 (0xF5) - uint32_t queue_doorbell_id6; // offset: 246 (0xF6) - uint32_t queue_doorbell_id7; // offset: 247 (0xF7) - uint32_t queue_doorbell_id8; // offset: 248 (0xF8) - uint32_t queue_doorbell_id9; // offset: 249 (0xF9) - uint32_t queue_doorbell_id10; // offset: 250 (0xFA) - uint32_t queue_doorbell_id11; // offset: 251 (0xFB) - uint32_t queue_doorbell_id12; // offset: 252 (0xFC) - uint32_t queue_doorbell_id13; // offset: 253 (0xFD) - uint32_t queue_doorbell_id14; // offset: 254 (0xFE) - uint32_t queue_doorbell_id15; // offset: 255 (0xFF) - uint32_t control_buf_addr_lo; // offset: 256 (0x100) - uint32_t control_buf_addr_hi; // offset: 257 (0x101) - uint32_t control_buf_wptr_lo; // offset: 258 (0x102) - uint32_t control_buf_wptr_hi; // offset: 259 (0x103) - uint32_t control_buf_dptr_lo; // offset: 260 (0x104) - uint32_t control_buf_dptr_hi; // offset: 261 (0x105) - uint32_t control_buf_num_entries; // offset: 262 (0x106) - uint32_t draw_ring_addr_lo; // offset: 263 (0x107) - uint32_t draw_ring_addr_hi; // offset: 264 (0x108) - uint32_t reserved_265; // offset: 265 (0x109) - uint32_t reserved_266; // offset: 266 (0x10A) - uint32_t reserved_267; // offset: 267 (0x10B) - uint32_t reserved_268; // offset: 268 (0x10C) - uint32_t reserved_269; // offset: 269 (0x10D) - uint32_t reserved_270; // offset: 270 (0x10E) - uint32_t reserved_271; // offset: 271 (0x10F) - uint32_t reserved_272; // offset: 272 (0x110) - uint32_t reserved_273; // offset: 273 (0x111) - uint32_t reserved_274; // offset: 274 (0x112) - uint32_t reserved_275; // offset: 275 (0x113) - uint32_t reserved_276; // offset: 276 (0x114) - uint32_t reserved_277; // offset: 277 (0x115) - uint32_t reserved_278; // offset: 278 (0x116) - uint32_t reserved_279; // offset: 279 (0x117) - uint32_t reserved_280; // offset: 280 (0x118) - uint32_t reserved_281; // offset: 281 (0x119) - uint32_t reserved_282; // offset: 282 (0x11A) - uint32_t reserved_283; // offset: 283 (0x11B) - uint32_t reserved_284; // offset: 284 (0x11C) - uint32_t reserved_285; // offset: 285 (0x11D) - uint32_t reserved_286; // offset: 286 (0x11E) - uint32_t reserved_287; // offset: 287 (0x11F) - uint32_t reserved_288; // offset: 288 (0x120) - uint32_t reserved_289; // offset: 289 (0x121) - uint32_t reserved_290; // offset: 290 (0x122) - uint32_t reserved_291; // offset: 291 (0x123) - uint32_t reserved_292; // offset: 292 (0x124) - uint32_t reserved_293; // offset: 293 (0x125) - uint32_t reserved_294; // offset: 294 (0x126) - uint32_t reserved_295; // offset: 295 (0x127) - uint32_t reserved_296; // offset: 296 (0x128) - uint32_t reserved_297; // offset: 297 (0x129) - uint32_t reserved_298; // offset: 298 (0x12A) - uint32_t reserved_299; // offset: 299 (0x12B) - uint32_t reserved_300; // offset: 300 (0x12C) - uint32_t reserved_301; // offset: 301 (0x12D) - uint32_t reserved_302; // offset: 302 (0x12E) - uint32_t reserved_303; // offset: 303 (0x12F) - uint32_t reserved_304; // offset: 304 (0x130) - uint32_t reserved_305; // offset: 305 (0x131) - uint32_t reserved_306; // offset: 306 (0x132) - uint32_t reserved_307; // offset: 307 (0x133) - uint32_t reserved_308; // offset: 308 (0x134) - uint32_t reserved_309; // offset: 309 (0x135) - uint32_t reserved_310; // offset: 310 (0x136) - uint32_t reserved_311; // offset: 311 (0x137) - uint32_t reserved_312; // offset: 312 (0x138) - uint32_t reserved_313; // offset: 313 (0x139) - uint32_t reserved_314; // offset: 314 (0x13A) - uint32_t reserved_315; // offset: 315 (0x13B) - uint32_t reserved_316; // offset: 316 (0x13C) - uint32_t reserved_317; // offset: 317 (0x13D) - uint32_t reserved_318; // offset: 318 (0x13E) - uint32_t reserved_319; // offset: 319 (0x13F) - uint32_t reserved_320; // offset: 320 (0x140) - uint32_t reserved_321; // offset: 321 (0x141) - uint32_t reserved_322; // offset: 322 (0x142) - uint32_t reserved_323; // offset: 323 (0x143) - uint32_t reserved_324; // offset: 324 (0x144) - uint32_t reserved_325; // offset: 325 (0x145) - uint32_t reserved_326; // offset: 326 (0x146) - uint32_t reserved_327; // offset: 327 (0x147) - uint32_t reserved_328; // offset: 328 (0x148) - uint32_t reserved_329; // offset: 329 (0x149) - uint32_t reserved_330; // offset: 330 (0x14A) - uint32_t reserved_331; // offset: 331 (0x14B) - uint32_t reserved_332; // offset: 332 (0x14C) - uint32_t reserved_333; // offset: 333 (0x14D) - uint32_t reserved_334; // offset: 334 (0x14E) - uint32_t reserved_335; // offset: 335 (0x14F) - uint32_t reserved_336; // offset: 336 (0x150) - uint32_t reserved_337; // offset: 337 (0x151) - uint32_t reserved_338; // offset: 338 (0x152) - uint32_t reserved_339; // offset: 339 (0x153) - uint32_t reserved_340; // offset: 340 (0x154) - uint32_t reserved_341; // offset: 341 (0x155) - uint32_t reserved_342; // offset: 342 (0x156) - uint32_t reserved_343; // offset: 343 (0x157) - uint32_t reserved_344; // offset: 344 (0x158) - uint32_t reserved_345; // offset: 345 (0x159) - uint32_t reserved_346; // offset: 346 (0x15A) - uint32_t reserved_347; // offset: 347 (0x15B) - uint32_t reserved_348; // offset: 348 (0x15C) - uint32_t reserved_349; // offset: 349 (0x15D) - uint32_t reserved_350; // offset: 350 (0x15E) - uint32_t reserved_351; // offset: 351 (0x15F) - uint32_t reserved_352; // offset: 352 (0x160) - uint32_t reserved_353; // offset: 353 (0x161) - uint32_t reserved_354; // offset: 354 (0x162) - uint32_t reserved_355; // offset: 355 (0x163) - uint32_t reserved_356; // offset: 356 (0x164) - uint32_t reserved_357; // offset: 357 (0x165) - uint32_t reserved_358; // offset: 358 (0x166) - uint32_t reserved_359; // offset: 359 (0x167) - uint32_t reserved_360; // offset: 360 (0x168) - uint32_t reserved_361; // offset: 361 (0x169) - uint32_t reserved_362; // offset: 362 (0x16A) - uint32_t reserved_363; // offset: 363 (0x16B) - uint32_t reserved_364; // offset: 364 (0x16C) - uint32_t reserved_365; // offset: 365 (0x16D) - uint32_t reserved_366; // offset: 366 (0x16E) - uint32_t reserved_367; // offset: 367 (0x16F) - uint32_t reserved_368; // offset: 368 (0x170) - uint32_t reserved_369; // offset: 369 (0x171) - uint32_t reserved_370; // offset: 370 (0x172) - uint32_t reserved_371; // offset: 371 (0x173) - uint32_t reserved_372; // offset: 372 (0x174) - uint32_t reserved_373; // offset: 373 (0x175) - uint32_t reserved_374; // offset: 374 (0x176) - uint32_t reserved_375; // offset: 375 (0x177) - uint32_t reserved_376; // offset: 376 (0x178) - uint32_t reserved_377; // offset: 377 (0x179) - uint32_t reserved_378; // offset: 378 (0x17A) - uint32_t reserved_379; // offset: 379 (0x17B) - uint32_t reserved_380; // offset: 380 (0x17C) - uint32_t reserved_381; // offset: 381 (0x17D) - uint32_t reserved_382; // offset: 382 (0x17E) - uint32_t reserved_383; // offset: 383 (0x17F) - uint32_t reserved_384; // offset: 384 (0x180) - uint32_t reserved_385; // offset: 385 (0x181) - uint32_t reserved_386; // offset: 386 (0x182) - uint32_t reserved_387; // offset: 387 (0x183) - uint32_t reserved_388; // offset: 388 (0x184) - uint32_t reserved_389; // offset: 389 (0x185) - uint32_t reserved_390; // offset: 390 (0x186) - uint32_t reserved_391; // offset: 391 (0x187) - uint32_t reserved_392; // offset: 392 (0x188) - uint32_t reserved_393; // offset: 393 (0x189) - uint32_t reserved_394; // offset: 394 (0x18A) - uint32_t reserved_395; // offset: 395 (0x18B) - uint32_t reserved_396; // offset: 396 (0x18C) - uint32_t reserved_397; // offset: 397 (0x18D) - uint32_t reserved_398; // offset: 398 (0x18E) - uint32_t reserved_399; // offset: 399 (0x18F) - uint32_t reserved_400; // offset: 400 (0x190) - uint32_t reserved_401; // offset: 401 (0x191) - uint32_t reserved_402; // offset: 402 (0x192) - uint32_t reserved_403; // offset: 403 (0x193) - uint32_t reserved_404; // offset: 404 (0x194) - uint32_t reserved_405; // offset: 405 (0x195) - uint32_t reserved_406; // offset: 406 (0x196) - uint32_t reserved_407; // offset: 407 (0x197) - uint32_t reserved_408; // offset: 408 (0x198) - uint32_t reserved_409; // offset: 409 (0x199) - uint32_t reserved_410; // offset: 410 (0x19A) - uint32_t reserved_411; // offset: 411 (0x19B) - uint32_t reserved_412; // offset: 412 (0x19C) - uint32_t reserved_413; // offset: 413 (0x19D) - uint32_t reserved_414; // offset: 414 (0x19E) - uint32_t reserved_415; // offset: 415 (0x19F) - uint32_t reserved_416; // offset: 416 (0x1A0) - uint32_t reserved_417; // offset: 417 (0x1A1) - uint32_t reserved_418; // offset: 418 (0x1A2) - uint32_t reserved_419; // offset: 419 (0x1A3) - uint32_t reserved_420; // offset: 420 (0x1A4) - uint32_t reserved_421; // offset: 421 (0x1A5) - uint32_t reserved_422; // offset: 422 (0x1A6) - uint32_t reserved_423; // offset: 423 (0x1A7) - uint32_t reserved_424; // offset: 424 (0x1A8) - uint32_t reserved_425; // offset: 425 (0x1A9) - uint32_t reserved_426; // offset: 426 (0x1AA) - uint32_t reserved_427; // offset: 427 (0x1AB) - uint32_t reserved_428; // offset: 428 (0x1AC) - uint32_t reserved_429; // offset: 429 (0x1AD) - uint32_t reserved_430; // offset: 430 (0x1AE) - uint32_t reserved_431; // offset: 431 (0x1AF) - uint32_t reserved_432; // offset: 432 (0x1B0) - uint32_t reserved_433; // offset: 433 (0x1B1) - uint32_t reserved_434; // offset: 434 (0x1B2) - uint32_t reserved_435; // offset: 435 (0x1B3) - uint32_t reserved_436; // offset: 436 (0x1B4) - uint32_t reserved_437; // offset: 437 (0x1B5) - uint32_t reserved_438; // offset: 438 (0x1B6) - uint32_t reserved_439; // offset: 439 (0x1B7) - uint32_t reserved_440; // offset: 440 (0x1B8) - uint32_t reserved_441; // offset: 441 (0x1B9) - uint32_t reserved_442; // offset: 442 (0x1BA) - uint32_t reserved_443; // offset: 443 (0x1BB) - uint32_t reserved_444; // offset: 444 (0x1BC) - uint32_t reserved_445; // offset: 445 (0x1BD) - uint32_t reserved_446; // offset: 446 (0x1BE) - uint32_t reserved_447; // offset: 447 (0x1BF) - uint32_t gws_0_val; // offset: 448 (0x1C0) - uint32_t gws_1_val; // offset: 449 (0x1C1) - uint32_t gws_2_val; // offset: 450 (0x1C2) - uint32_t gws_3_val; // offset: 451 (0x1C3) - uint32_t gws_4_val; // offset: 452 (0x1C4) - uint32_t gws_5_val; // offset: 453 (0x1C5) - uint32_t gws_6_val; // offset: 454 (0x1C6) - uint32_t gws_7_val; // offset: 455 (0x1C7) - uint32_t gws_8_val; // offset: 456 (0x1C8) - uint32_t gws_9_val; // offset: 457 (0x1C9) - uint32_t gws_10_val; // offset: 458 (0x1CA) - uint32_t gws_11_val; // offset: 459 (0x1CB) - uint32_t gws_12_val; // offset: 460 (0x1CC) - uint32_t gws_13_val; // offset: 461 (0x1CD) - uint32_t gws_14_val; // offset: 462 (0x1CE) - uint32_t gws_15_val; // offset: 463 (0x1CF) - uint32_t gws_16_val; // offset: 464 (0x1D0) - uint32_t gws_17_val; // offset: 465 (0x1D1) - uint32_t gws_18_val; // offset: 466 (0x1D2) - uint32_t gws_19_val; // offset: 467 (0x1D3) - uint32_t gws_20_val; // offset: 468 (0x1D4) - uint32_t gws_21_val; // offset: 469 (0x1D5) - uint32_t gws_22_val; // offset: 470 (0x1D6) - uint32_t gws_23_val; // offset: 471 (0x1D7) - uint32_t gws_24_val; // offset: 472 (0x1D8) - uint32_t gws_25_val; // offset: 473 (0x1D9) - uint32_t gws_26_val; // offset: 474 (0x1DA) - uint32_t gws_27_val; // offset: 475 (0x1DB) - uint32_t gws_28_val; // offset: 476 (0x1DC) - uint32_t gws_29_val; // offset: 477 (0x1DD) - uint32_t gws_30_val; // offset: 478 (0x1DE) - uint32_t gws_31_val; // offset: 479 (0x1DF) - uint32_t gws_32_val; // offset: 480 (0x1E0) - uint32_t gws_33_val; // offset: 481 (0x1E1) - uint32_t gws_34_val; // offset: 482 (0x1E2) - uint32_t gws_35_val; // offset: 483 (0x1E3) - uint32_t gws_36_val; // offset: 484 (0x1E4) - uint32_t gws_37_val; // offset: 485 (0x1E5) - uint32_t gws_38_val; // offset: 486 (0x1E6) - uint32_t gws_39_val; // offset: 487 (0x1E7) - uint32_t gws_40_val; // offset: 488 (0x1E8) - uint32_t gws_41_val; // offset: 489 (0x1E9) - uint32_t gws_42_val; // offset: 490 (0x1EA) - uint32_t gws_43_val; // offset: 491 (0x1EB) - uint32_t gws_44_val; // offset: 492 (0x1EC) - uint32_t gws_45_val; // offset: 493 (0x1ED) - uint32_t gws_46_val; // offset: 494 (0x1EE) - uint32_t gws_47_val; // offset: 495 (0x1EF) - uint32_t gws_48_val; // offset: 496 (0x1F0) - uint32_t gws_49_val; // offset: 497 (0x1F1) - uint32_t gws_50_val; // offset: 498 (0x1F2) - uint32_t gws_51_val; // offset: 499 (0x1F3) - uint32_t gws_52_val; // offset: 500 (0x1F4) - uint32_t gws_53_val; // offset: 501 (0x1F5) - uint32_t gws_54_val; // offset: 502 (0x1F6) - uint32_t gws_55_val; // offset: 503 (0x1F7) - uint32_t gws_56_val; // offset: 504 (0x1F8) - uint32_t gws_57_val; // offset: 505 (0x1F9) - uint32_t gws_58_val; // offset: 506 (0x1FA) - uint32_t gws_59_val; // offset: 507 (0x1FB) - uint32_t gws_60_val; // offset: 508 (0x1FC) - uint32_t gws_61_val; // offset: 509 (0x1FD) - uint32_t gws_62_val; // offset: 510 (0x1FE) - uint32_t gws_63_val; // offset: 511 (0x1FF) -}; - -#endif /* V11_STRUCTS_H_ */ diff --git a/tinygrad/extra/amdpci/headers/v12_structs.h b/tinygrad/extra/amdpci/headers/v12_structs.h deleted file mode 100644 index 21e97b19..00000000 --- a/tinygrad/extra/amdpci/headers/v12_structs.h +++ /dev/null @@ -1,1191 +0,0 @@ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef V12_STRUCTS_H_ -#define V12_STRUCTS_H_ - - - -struct v12_gfx_mqd { - uint32_t shadow_base_lo; // offset: 0 (0x0) - uint32_t shadow_base_hi; // offset: 1 (0x1) - uint32_t reserved_2; // offset: 2 (0x2) - uint32_t reserved_3; // offset: 3 (0x3) - uint32_t fw_work_area_base_lo; // offset: 4 (0x4) - uint32_t fw_work_area_base_hi; // offset: 5 (0x5) - uint32_t shadow_initialized; // offset: 6 (0x6) - uint32_t ib_vmid; // offset: 7 (0x7) - uint32_t reserved_8; // offset: 8 (0x8) - uint32_t reserved_9; // offset: 9 (0x9) - uint32_t reserved_10; // offset: 10 (0xA) - uint32_t reserved_11; // offset: 11 (0xB) - uint32_t reserved_12; // offset: 12 (0xC) - uint32_t reserved_13; // offset: 13 (0xD) - uint32_t reserved_14; // offset: 14 (0xE) - uint32_t reserved_15; // offset: 15 (0xF) - uint32_t reserved_16; // offset: 16 (0x10) - uint32_t reserved_17; // offset: 17 (0x11) - uint32_t reserved_18; // offset: 18 (0x12) - uint32_t reserved_19; // offset: 19 (0x13) - uint32_t reserved_20; // offset: 20 (0x14) - uint32_t reserved_21; // offset: 21 (0x15) - uint32_t reserved_22; // offset: 22 (0x16) - uint32_t reserved_23; // offset: 23 (0x17) - uint32_t reserved_24; // offset: 24 (0x18) - uint32_t reserved_25; // offset: 25 (0x19) - uint32_t reserved_26; // offset: 26 (0x1A) - uint32_t reserved_27; // offset: 27 (0x1B) - uint32_t reserved_28; // offset: 28 (0x1C) - uint32_t reserved_29; // offset: 29 (0x1D) - uint32_t reserved_30; // offset: 30 (0x1E) - uint32_t reserved_31; // offset: 31 (0x1F) - uint32_t reserved_32; // offset: 32 (0x20) - uint32_t reserved_33; // offset: 33 (0x21) - uint32_t reserved_34; // offset: 34 (0x22) - uint32_t reserved_35; // offset: 35 (0x23) - uint32_t reserved_36; // offset: 36 (0x24) - uint32_t reserved_37; // offset: 37 (0x25) - uint32_t reserved_38; // offset: 38 (0x26) - uint32_t reserved_39; // offset: 39 (0x27) - uint32_t reserved_40; // offset: 40 (0x28) - uint32_t reserved_41; // offset: 41 (0x29) - uint32_t reserved_42; // offset: 42 (0x2A) - uint32_t reserved_43; // offset: 43 (0x2B) - uint32_t reserved_44; // offset: 44 (0x2C) - uint32_t reserved_45; // offset: 45 (0x2D) - uint32_t reserved_46; // offset: 46 (0x2E) - uint32_t reserved_47; // offset: 47 (0x2F) - uint32_t reserved_48; // offset: 48 (0x30) - uint32_t reserved_49; // offset: 49 (0x31) - uint32_t reserved_50; // offset: 50 (0x32) - uint32_t reserved_51; // offset: 51 (0x33) - uint32_t reserved_52; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t reserved_59; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t reserved_65; // offset: 65 (0x41) - uint32_t reserved_66; // offset: 66 (0x42) - uint32_t reserved_67; // offset: 67 (0x43) - uint32_t reserved_68; // offset: 68 (0x44) - uint32_t reserved_69; // offset: 69 (0x45) - uint32_t reserved_70; // offset: 70 (0x46) - uint32_t reserved_71; // offset: 71 (0x47) - uint32_t reserved_72; // offset: 72 (0x48) - uint32_t reserved_73; // offset: 73 (0x49) - uint32_t reserved_74; // offset: 74 (0x4A) - uint32_t reserved_75; // offset: 75 (0x4B) - uint32_t reserved_76; // offset: 76 (0x4C) - uint32_t reserved_77; // offset: 77 (0x4D) - uint32_t reserved_78; // offset: 78 (0x4E) - uint32_t reserved_79; // offset: 79 (0x4F) - uint32_t reserved_80; // offset: 80 (0x50) - uint32_t reserved_81; // offset: 81 (0x51) - uint32_t reserved_82; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t checksum_lo; // offset: 84 (0x54) - uint32_t checksum_hi; // offset: 85 (0x55) - uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) - uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) - uint32_t reserved_88; // offset: 88 (0x58) - uint32_t reserved_89; // offset: 89 (0x59) - uint32_t reserved_90; // offset: 90 (0x5A) - uint32_t reserved_91; // offset: 91 (0x5B) - uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C) - uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D) - uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E) - uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F) - uint32_t reserved_96; // offset: 96 (0x60) - uint32_t reserved_97; // offset: 97 (0x61) - uint32_t reserved_98; // offset: 98 (0x62) - uint32_t reserved_99; // offset: 99 (0x63) - uint32_t reserved_100; // offset: 100 (0x64) - uint32_t reserved_101; // offset: 101 (0x65) - uint32_t reserved_102; // offset: 102 (0x66) - uint32_t reserved_103; // offset: 103 (0x67) - uint32_t task_shader_control_buf_addr_lo; // offset: 104 (0x68) - uint32_t task_shader_control_buf_addr_hi; // offset: 105 (0x69) - uint32_t task_shader_read_rptr_lo; // offset: 106 (0x6A) - uint32_t task_shader_read_rptr_hi; // offset: 107 (0x6B) - uint32_t task_shader_num_entries; // offset: 108 (0x6C) - uint32_t task_shader_num_entries_bits; // offset: 109 (0x6D) - uint32_t task_shader_ring_buffer_addr_lo; // offset: 110 (0x6E) - uint32_t task_shader_ring_buffer_addr_hi; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t reserved_114; // offset: 114 (0x72) - uint32_t reserved_115; // offset: 115 (0x73) - uint32_t reserved_116; // offset: 116 (0x74) - uint32_t reserved_117; // offset: 117 (0x75) - uint32_t reserved_118; // offset: 118 (0x76) - uint32_t reserved_119; // offset: 119 (0x77) - uint32_t reserved_120; // offset: 120 (0x78) - uint32_t reserved_121; // offset: 121 (0x79) - uint32_t reserved_122; // offset: 122 (0x7A) - uint32_t reserved_123; // offset: 123 (0x7B) - uint32_t reserved_124; // offset: 124 (0x7C) - uint32_t reserved_125; // offset: 125 (0x7D) - uint32_t reserved_126; // offset: 126 (0x7E) - uint32_t reserved_127; // offset: 127 (0x7F) - uint32_t cp_mqd_base_addr; // offset: 128 (0x80) - uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) - uint32_t cp_gfx_hqd_active; // offset: 130 (0x82) - uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83) - uint32_t reserved_132; // offset: 132 (0x84) - uint32_t reserved_133; // offset: 133 (0x85) - uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86) - uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87) - uint32_t cp_gfx_hqd_base; // offset: 136 (0x88) - uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89) - uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A) - uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B) - uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C) - uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D) - uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E) - uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F) - uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90) - uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91) - uint32_t reserved_146; // offset: 146 (0x92) - uint32_t reserved_147; // offset: 147 (0x93) - uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94) - uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95) - uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96) - uint32_t reserved_151; // offset: 151 (0x97) - uint32_t reserved_152; // offset: 152 (0x98) - uint32_t reserved_153; // offset: 153 (0x99) - uint32_t reserved_154; // offset: 154 (0x9A) - uint32_t reserved_155; // offset: 155 (0x9B) - uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C) - uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D) - uint32_t reserved_158; // offset: 158 (0x9E) - uint32_t reserved_159; // offset: 159 (0x9F) - uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0) - uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1) - uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2) - uint32_t reserved_163; // offset: 163 (0xA3) - uint32_t reserved_164; // offset: 164 (0xA4) - uint32_t reserved_165; // offset: 165 (0xA5) - uint32_t reserved_166; // offset: 166 (0xA6) - uint32_t reserved_167; // offset: 167 (0xA7) - uint32_t reserved_168; // offset: 168 (0xA8) - uint32_t reserved_169; // offset: 169 (0xA9) - uint32_t reserved_170; // offset: 170 (0xAA) - uint32_t reserved_171; // offset: 171 (0xAB) - uint32_t reserved_172; // offset: 172 (0xAC) - uint32_t reserved_173; // offset: 173 (0xAD) - uint32_t reserved_174; // offset: 174 (0xAE) - uint32_t reserved_175; // offset: 175 (0xAF) - uint32_t reserved_176; // offset: 176 (0xB0) - uint32_t reserved_177; // offset: 177 (0xB1) - uint32_t reserved_178; // offset: 178 (0xB2) - uint32_t reserved_179; // offset: 179 (0xB3) - uint32_t reserved_180; // offset: 180 (0xB4) - uint32_t reserved_181; // offset: 181 (0xB5) - uint32_t reserved_182; // offset: 182 (0xB6) - uint32_t reserved_183; // offset: 183 (0xB7) - uint32_t reserved_184; // offset: 184 (0xB8) - uint32_t reserved_185; // offset: 185 (0xB9) - uint32_t reserved_186; // offset: 186 (0xBA) - uint32_t reserved_187; // offset: 187 (0xBB) - uint32_t reserved_188; // offset: 188 (0xBC) - uint32_t reserved_189; // offset: 189 (0xBD) - uint32_t reserved_190; // offset: 190 (0xBE) - uint32_t reserved_191; // offset: 191 (0xBF) - uint32_t reserved_192; // offset: 192 (0xC0) - uint32_t reserved_193; // offset: 193 (0xC1) - uint32_t reserved_194; // offset: 194 (0xC2) - uint32_t reserved_195; // offset: 195 (0xC3) - uint32_t reserved_196; // offset: 196 (0xC4) - uint32_t reserved_197; // offset: 197 (0xC5) - uint32_t reserved_198; // offset: 198 (0xC6) - uint32_t reserved_199; // offset: 199 (0xC7) - uint32_t reserved_200; // offset: 200 (0xC8) - uint32_t reserved_201; // offset: 201 (0xC9) - uint32_t reserved_202; // offset: 202 (0xCA) - uint32_t reserved_203; // offset: 203 (0xCB) - uint32_t reserved_204; // offset: 204 (0xCC) - uint32_t reserved_205; // offset: 205 (0xCD) - uint32_t reserved_206; // offset: 206 (0xCE) - uint32_t reserved_207; // offset: 207 (0xCF) - uint32_t reserved_208; // offset: 208 (0xD0) - uint32_t reserved_209; // offset: 209 (0xD1) - uint32_t reserved_210; // offset: 210 (0xD2) - uint32_t reserved_211; // offset: 211 (0xD3) - uint32_t reserved_212; // offset: 212 (0xD4) - uint32_t reserved_213; // offset: 213 (0xD5) - uint32_t reserved_214; // offset: 214 (0xD6) - uint32_t reserved_215; // offset: 215 (0xD7) - uint32_t reserved_216; // offset: 216 (0xD8) - uint32_t reserved_217; // offset: 217 (0xD9) - uint32_t reserved_218; // offset: 218 (0xDA) - uint32_t reserved_219; // offset: 219 (0xDB) - uint32_t reserved_220; // offset: 220 (0xDC) - uint32_t reserved_221; // offset: 221 (0xDD) - uint32_t reserved_222; // offset: 222 (0xDE) - uint32_t reserved_223; // offset: 223 (0xDF) - uint32_t reserved_224; // offset: 224 (0xE0) - uint32_t reserved_225; // offset: 225 (0xE1) - uint32_t reserved_226; // offset: 226 (0xE2) - uint32_t reserved_227; // offset: 227 (0xE3) - uint32_t reserved_228; // offset: 228 (0xE4) - uint32_t reserved_229; // offset: 229 (0xE5) - uint32_t reserved_230; // offset: 230 (0xE6) - uint32_t reserved_231; // offset: 231 (0xE7) - uint32_t reserved_232; // offset: 232 (0xE8) - uint32_t reserved_233; // offset: 233 (0xE9) - uint32_t reserved_234; // offset: 234 (0xEA) - uint32_t reserved_235; // offset: 235 (0xEB) - uint32_t reserved_236; // offset: 236 (0xEC) - uint32_t reserved_237; // offset: 237 (0xED) - uint32_t reserved_238; // offset: 238 (0xEE) - uint32_t reserved_239; // offset: 239 (0xEF) - uint32_t reserved_240; // offset: 240 (0xF0) - uint32_t reserved_241; // offset: 241 (0xF1) - uint32_t reserved_242; // offset: 242 (0xF2) - uint32_t reserved_243; // offset: 243 (0xF3) - uint32_t reserved_244; // offset: 244 (0xF4) - uint32_t reserved_245; // offset: 245 (0xF5) - uint32_t reserved_246; // offset: 246 (0xF6) - uint32_t reserved_247; // offset: 247 (0xF7) - uint32_t reserved_248; // offset: 248 (0xF8) - uint32_t reserved_249; // offset: 249 (0xF9) - uint32_t reserved_250; // offset: 250 (0xFA) - uint32_t reserved_251; // offset: 251 (0xFB) - uint32_t reserved_252; // offset: 252 (0xFC) - uint32_t reserved_253; // offset: 253 (0xFD) - uint32_t reserved_254; // offset: 254 (0xFE) - uint32_t reserved_255; // offset: 255 (0xFF) - uint32_t reserved_256; // offset: 256 (0x100) - uint32_t reserved_257; // offset: 257 (0x101) - uint32_t reserved_258; // offset: 258 (0x102) - uint32_t reserved_259; // offset: 259 (0x103) - uint32_t reserved_260; // offset: 260 (0x104) - uint32_t reserved_261; // offset: 261 (0x105) - uint32_t reserved_262; // offset: 262 (0x106) - uint32_t reserved_263; // offset: 263 (0x107) - uint32_t reserved_264; // offset: 264 (0x108) - uint32_t reserved_265; // offset: 265 (0x109) - uint32_t reserved_266; // offset: 266 (0x10A) - uint32_t reserved_267; // offset: 267 (0x10B) - uint32_t reserved_268; // offset: 268 (0x10C) - uint32_t reserved_269; // offset: 269 (0x10D) - uint32_t reserved_270; // offset: 270 (0x10E) - uint32_t reserved_271; // offset: 271 (0x10F) - uint32_t dfwx_flags; // offset: 272 (0x110) - uint32_t dfwx_slot; // offset: 273 (0x111) - uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) - uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) - uint32_t reserved_276; // offset: 276 (0x114) - uint32_t reserved_277; // offset: 277 (0x115) - uint32_t reserved_278; // offset: 278 (0x116) - uint32_t reserved_279; // offset: 279 (0x117) - uint32_t reserved_280; // offset: 280 (0x118) - uint32_t reserved_281; // offset: 281 (0x119) - uint32_t reserved_282; // offset: 282 (0x11A) - uint32_t reserved_283; // offset: 283 (0x11B) - uint32_t reserved_284; // offset: 284 (0x11C) - uint32_t reserved_285; // offset: 285 (0x11D) - uint32_t reserved_286; // offset: 286 (0x11E) - uint32_t reserved_287; // offset: 287 (0x11F) - uint32_t reserved_288; // offset: 288 (0x120) - uint32_t reserved_289; // offset: 289 (0x121) - uint32_t reserved_290; // offset: 290 (0x122) - uint32_t reserved_291; // offset: 291 (0x123) - uint32_t reserved_292; // offset: 292 (0x124) - uint32_t reserved_293; // offset: 293 (0x125) - uint32_t reserved_294; // offset: 294 (0x126) - uint32_t reserved_295; // offset: 295 (0x127) - uint32_t reserved_296; // offset: 296 (0x128) - uint32_t reserved_297; // offset: 297 (0x129) - uint32_t reserved_298; // offset: 298 (0x12A) - uint32_t reserved_299; // offset: 299 (0x12B) - uint32_t reserved_300; // offset: 300 (0x12C) - uint32_t reserved_301; // offset: 301 (0x12D) - uint32_t reserved_302; // offset: 302 (0x12E) - uint32_t reserved_303; // offset: 303 (0x12F) - uint32_t reserved_304; // offset: 304 (0x130) - uint32_t reserved_305; // offset: 305 (0x131) - uint32_t reserved_306; // offset: 306 (0x132) - uint32_t reserved_307; // offset: 307 (0x133) - uint32_t reserved_308; // offset: 308 (0x134) - uint32_t reserved_309; // offset: 309 (0x135) - uint32_t reserved_310; // offset: 310 (0x136) - uint32_t reserved_311; // offset: 311 (0x137) - uint32_t reserved_312; // offset: 312 (0x138) - uint32_t reserved_313; // offset: 313 (0x139) - uint32_t reserved_314; // offset: 314 (0x13A) - uint32_t reserved_315; // offset: 315 (0x13B) - uint32_t reserved_316; // offset: 316 (0x13C) - uint32_t reserved_317; // offset: 317 (0x13D) - uint32_t reserved_318; // offset: 318 (0x13E) - uint32_t reserved_319; // offset: 319 (0x13F) - uint32_t reserved_320; // offset: 320 (0x140) - uint32_t reserved_321; // offset: 321 (0x141) - uint32_t reserved_322; // offset: 322 (0x142) - uint32_t reserved_323; // offset: 323 (0x143) - uint32_t reserved_324; // offset: 324 (0x144) - uint32_t reserved_325; // offset: 325 (0x145) - uint32_t reserved_326; // offset: 326 (0x146) - uint32_t reserved_327; // offset: 327 (0x147) - uint32_t reserved_328; // offset: 328 (0x148) - uint32_t reserved_329; // offset: 329 (0x149) - uint32_t reserved_330; // offset: 330 (0x14A) - uint32_t reserved_331; // offset: 331 (0x14B) - uint32_t reserved_332; // offset: 332 (0x14C) - uint32_t reserved_333; // offset: 333 (0x14D) - uint32_t reserved_334; // offset: 334 (0x14E) - uint32_t reserved_335; // offset: 335 (0x14F) - uint32_t reserved_336; // offset: 336 (0x150) - uint32_t reserved_337; // offset: 337 (0x151) - uint32_t reserved_338; // offset: 338 (0x152) - uint32_t reserved_339; // offset: 339 (0x153) - uint32_t reserved_340; // offset: 340 (0x154) - uint32_t reserved_341; // offset: 341 (0x155) - uint32_t reserved_342; // offset: 342 (0x156) - uint32_t reserved_343; // offset: 343 (0x157) - uint32_t reserved_344; // offset: 344 (0x158) - uint32_t reserved_345; // offset: 345 (0x159) - uint32_t reserved_346; // offset: 346 (0x15A) - uint32_t reserved_347; // offset: 347 (0x15B) - uint32_t reserved_348; // offset: 348 (0x15C) - uint32_t reserved_349; // offset: 349 (0x15D) - uint32_t reserved_350; // offset: 350 (0x15E) - uint32_t reserved_351; // offset: 351 (0x15F) - uint32_t reserved_352; // offset: 352 (0x160) - uint32_t reserved_353; // offset: 353 (0x161) - uint32_t reserved_354; // offset: 354 (0x162) - uint32_t reserved_355; // offset: 355 (0x163) - uint32_t reserved_356; // offset: 356 (0x164) - uint32_t reserved_357; // offset: 357 (0x165) - uint32_t reserved_358; // offset: 358 (0x166) - uint32_t reserved_359; // offset: 359 (0x167) - uint32_t reserved_360; // offset: 360 (0x168) - uint32_t reserved_361; // offset: 361 (0x169) - uint32_t reserved_362; // offset: 362 (0x16A) - uint32_t reserved_363; // offset: 363 (0x16B) - uint32_t reserved_364; // offset: 364 (0x16C) - uint32_t reserved_365; // offset: 365 (0x16D) - uint32_t reserved_366; // offset: 366 (0x16E) - uint32_t reserved_367; // offset: 367 (0x16F) - uint32_t reserved_368; // offset: 368 (0x170) - uint32_t reserved_369; // offset: 369 (0x171) - uint32_t reserved_370; // offset: 370 (0x172) - uint32_t reserved_371; // offset: 371 (0x173) - uint32_t reserved_372; // offset: 372 (0x174) - uint32_t reserved_373; // offset: 373 (0x175) - uint32_t reserved_374; // offset: 374 (0x176) - uint32_t reserved_375; // offset: 375 (0x177) - uint32_t reserved_376; // offset: 376 (0x178) - uint32_t reserved_377; // offset: 377 (0x179) - uint32_t reserved_378; // offset: 378 (0x17A) - uint32_t reserved_379; // offset: 379 (0x17B) - uint32_t reserved_380; // offset: 380 (0x17C) - uint32_t reserved_381; // offset: 381 (0x17D) - uint32_t reserved_382; // offset: 382 (0x17E) - uint32_t reserved_383; // offset: 383 (0x17F) - uint32_t reserved_384; // offset: 384 (0x180) - uint32_t reserved_385; // offset: 385 (0x181) - uint32_t reserved_386; // offset: 386 (0x182) - uint32_t reserved_387; // offset: 387 (0x183) - uint32_t reserved_388; // offset: 388 (0x184) - uint32_t reserved_389; // offset: 389 (0x185) - uint32_t reserved_390; // offset: 390 (0x186) - uint32_t reserved_391; // offset: 391 (0x187) - uint32_t reserved_392; // offset: 392 (0x188) - uint32_t reserved_393; // offset: 393 (0x189) - uint32_t reserved_394; // offset: 394 (0x18A) - uint32_t reserved_395; // offset: 395 (0x18B) - uint32_t reserved_396; // offset: 396 (0x18C) - uint32_t reserved_397; // offset: 397 (0x18D) - uint32_t reserved_398; // offset: 398 (0x18E) - uint32_t reserved_399; // offset: 399 (0x18F) - uint32_t reserved_400; // offset: 400 (0x190) - uint32_t reserved_401; // offset: 401 (0x191) - uint32_t reserved_402; // offset: 402 (0x192) - uint32_t reserved_403; // offset: 403 (0x193) - uint32_t reserved_404; // offset: 404 (0x194) - uint32_t reserved_405; // offset: 405 (0x195) - uint32_t reserved_406; // offset: 406 (0x196) - uint32_t reserved_407; // offset: 407 (0x197) - uint32_t reserved_408; // offset: 408 (0x198) - uint32_t reserved_409; // offset: 409 (0x199) - uint32_t reserved_410; // offset: 410 (0x19A) - uint32_t reserved_411; // offset: 411 (0x19B) - uint32_t reserved_412; // offset: 412 (0x19C) - uint32_t reserved_413; // offset: 413 (0x19D) - uint32_t reserved_414; // offset: 414 (0x19E) - uint32_t reserved_415; // offset: 415 (0x19F) - uint32_t reserved_416; // offset: 416 (0x1A0) - uint32_t reserved_417; // offset: 417 (0x1A1) - uint32_t reserved_418; // offset: 418 (0x1A2) - uint32_t reserved_419; // offset: 419 (0x1A3) - uint32_t reserved_420; // offset: 420 (0x1A4) - uint32_t reserved_421; // offset: 421 (0x1A5) - uint32_t reserved_422; // offset: 422 (0x1A6) - uint32_t reserved_423; // offset: 423 (0x1A7) - uint32_t reserved_424; // offset: 424 (0x1A8) - uint32_t reserved_425; // offset: 425 (0x1A9) - uint32_t reserved_426; // offset: 426 (0x1AA) - uint32_t reserved_427; // offset: 427 (0x1AB) - uint32_t reserved_428; // offset: 428 (0x1AC) - uint32_t reserved_429; // offset: 429 (0x1AD) - uint32_t reserved_430; // offset: 430 (0x1AE) - uint32_t reserved_431; // offset: 431 (0x1AF) - uint32_t reserved_432; // offset: 432 (0x1B0) - uint32_t reserved_433; // offset: 433 (0x1B1) - uint32_t reserved_434; // offset: 434 (0x1B2) - uint32_t reserved_435; // offset: 435 (0x1B3) - uint32_t reserved_436; // offset: 436 (0x1B4) - uint32_t reserved_437; // offset: 437 (0x1B5) - uint32_t reserved_438; // offset: 438 (0x1B6) - uint32_t reserved_439; // offset: 439 (0x1B7) - uint32_t reserved_440; // offset: 440 (0x1B8) - uint32_t reserved_441; // offset: 441 (0x1B9) - uint32_t reserved_442; // offset: 442 (0x1BA) - uint32_t reserved_443; // offset: 443 (0x1BB) - uint32_t reserved_444; // offset: 444 (0x1BC) - uint32_t reserved_445; // offset: 445 (0x1BD) - uint32_t reserved_446; // offset: 446 (0x1BE) - uint32_t reserved_447; // offset: 447 (0x1BF) - uint32_t reserved_448; // offset: 448 (0x1C0) - uint32_t reserved_449; // offset: 449 (0x1C1) - uint32_t reserved_450; // offset: 450 (0x1C2) - uint32_t reserved_451; // offset: 451 (0x1C3) - uint32_t reserved_452; // offset: 452 (0x1C4) - uint32_t reserved_453; // offset: 453 (0x1C5) - uint32_t reserved_454; // offset: 454 (0x1C6) - uint32_t reserved_455; // offset: 455 (0x1C7) - uint32_t reserved_456; // offset: 456 (0x1C8) - uint32_t reserved_457; // offset: 457 (0x1C9) - uint32_t reserved_458; // offset: 458 (0x1CA) - uint32_t reserved_459; // offset: 459 (0x1CB) - uint32_t reserved_460; // offset: 460 (0x1CC) - uint32_t reserved_461; // offset: 461 (0x1CD) - uint32_t reserved_462; // offset: 462 (0x1CE) - uint32_t reserved_463; // offset: 463 (0x1CF) - uint32_t reserved_464; // offset: 464 (0x1D0) - uint32_t reserved_465; // offset: 465 (0x1D1) - uint32_t reserved_466; // offset: 466 (0x1D2) - uint32_t reserved_467; // offset: 467 (0x1D3) - uint32_t reserved_468; // offset: 468 (0x1D4) - uint32_t reserved_469; // offset: 469 (0x1D5) - uint32_t reserved_470; // offset: 470 (0x1D6) - uint32_t reserved_471; // offset: 471 (0x1D7) - uint32_t reserved_472; // offset: 472 (0x1D8) - uint32_t reserved_473; // offset: 473 (0x1D9) - uint32_t reserved_474; // offset: 474 (0x1DA) - uint32_t reserved_475; // offset: 475 (0x1DB) - uint32_t reserved_476; // offset: 476 (0x1DC) - uint32_t reserved_477; // offset: 477 (0x1DD) - uint32_t reserved_478; // offset: 478 (0x1DE) - uint32_t reserved_479; // offset: 479 (0x1DF) - uint32_t reserved_480; // offset: 480 (0x1E0) - uint32_t reserved_481; // offset: 481 (0x1E1) - uint32_t reserved_482; // offset: 482 (0x1E2) - uint32_t reserved_483; // offset: 483 (0x1E3) - uint32_t reserved_484; // offset: 484 (0x1E4) - uint32_t reserved_485; // offset: 485 (0x1E5) - uint32_t reserved_486; // offset: 486 (0x1E6) - uint32_t reserved_487; // offset: 487 (0x1E7) - uint32_t reserved_488; // offset: 488 (0x1E8) - uint32_t reserved_489; // offset: 489 (0x1E9) - uint32_t reserved_490; // offset: 490 (0x1EA) - uint32_t reserved_491; // offset: 491 (0x1EB) - uint32_t reserved_492; // offset: 492 (0x1EC) - uint32_t reserved_493; // offset: 493 (0x1ED) - uint32_t reserved_494; // offset: 494 (0x1EE) - uint32_t reserved_495; // offset: 495 (0x1EF) - uint32_t reserved_496; // offset: 496 (0x1F0) - uint32_t reserved_497; // offset: 497 (0x1F1) - uint32_t reserved_498; // offset: 498 (0x1F2) - uint32_t reserved_499; // offset: 499 (0x1F3) - uint32_t reserved_500; // offset: 500 (0x1F4) - uint32_t reserved_501; // offset: 501 (0x1F5) - uint32_t reserved_502; // offset: 502 (0x1F6) - uint32_t reserved_503; // offset: 503 (0x1F7) - uint32_t reserved_504; // offset: 504 (0x1F8) - uint32_t reserved_505; // offset: 505 (0x1F9) - uint32_t reserved_506; // offset: 506 (0x1FA) - uint32_t reserved_507; // offset: 507 (0x1FB) - uint32_t reserved_508; // offset: 508 (0x1FC) - uint32_t reserved_509; // offset: 509 (0x1FD) - uint32_t reserved_510; // offset: 510 (0x1FE) - uint32_t reserved_511; // offset: 511 (0x1FF) -}; - -struct v12_sdma_mqd { - uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0) - uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1) - uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2) - uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3) - uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4) - uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5) - uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6) - uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 7 (0x7) - uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 8 (0x8) - uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9) - uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA) - uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB) - uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC) - uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD) - uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE) - uint32_t sdmax_rlcx_doorbell; // offset: 15 (0xF) - uint32_t sdmax_rlcx_doorbell_log; // offset: 16 (0x10) - uint32_t sdmax_rlcx_doorbell_offset; // offset: 17 (0x11) - uint32_t sdmax_rlcx_csa_addr_lo; // offset: 18 (0x12) - uint32_t sdmax_rlcx_csa_addr_hi; // offset: 19 (0x13) - uint32_t sdmax_rlcx_sched_cntl; // offset: 20 (0x14) - uint32_t sdmax_rlcx_ib_sub_remain; // offset: 21 (0x15) - uint32_t sdmax_rlcx_preempt; // offset: 22 (0x16) - uint32_t sdmax_rlcx_dummy_reg; // offset: 23 (0x17) - uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 24 (0x18) - uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 25 (0x19) - uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 26 (0x1A) - uint32_t sdmax_rlcx_minor_ptr_update; // offset: 27 (0x1B) - uint32_t sdmax_rlcx_mcu_dbg0; // offset: 28 (0x1C) - uint32_t sdmax_rlcx_mcu_dbg1; // offset: 29 (0x1D) - uint32_t sdmax_rlcx_context_switch_status; // offset: 30 (0x1E) - uint32_t sdmax_rlcx_midcmd_cntl; // offset: 31 (0x1F) - uint32_t sdmax_rlcx_midcmd_data0; // offset: 32 (0x20) - uint32_t sdmax_rlcx_midcmd_data1; // offset: 33 (0x21) - uint32_t sdmax_rlcx_midcmd_data2; // offset: 34 (0x22) - uint32_t sdmax_rlcx_midcmd_data3; // offset: 35 (0x23) - uint32_t sdmax_rlcx_midcmd_data4; // offset: 36 (0x24) - uint32_t sdmax_rlcx_midcmd_data5; // offset: 37 (0x25) - uint32_t sdmax_rlcx_midcmd_data6; // offset: 38 (0x26) - uint32_t sdmax_rlcx_midcmd_data7; // offset: 39 (0x27) - uint32_t sdmax_rlcx_midcmd_data8; // offset: 40 (0x28) - uint32_t sdmax_rlcx_midcmd_data9; // offset: 41 (0x29) - uint32_t sdmax_rlcx_midcmd_data10; // offset: 42 (0x2A) - uint32_t sdmax_rlcx_wait_unsatisfied_thd; // offset: 43 (0x2B) - uint32_t sdmax_rlcx_mqd_base_addr_lo; // offset: 44 (0x2C) - uint32_t sdmax_rlcx_mqd_base_addr_hi; // offset: 45 (0x2D) - uint32_t sdmax_rlcx_mqd_control; // offset: 46 (0x2E) - uint32_t reserved_47; // offset: 47 (0x2F) - uint32_t reserved_48; // offset: 48 (0x30) - uint32_t reserved_49; // offset: 49 (0x31) - uint32_t reserved_50; // offset: 50 (0x32) - uint32_t reserved_51; // offset: 51 (0x33) - uint32_t reserved_52; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t reserved_59; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t reserved_65; // offset: 65 (0x41) - uint32_t reserved_66; // offset: 66 (0x42) - uint32_t reserved_67; // offset: 67 (0x43) - uint32_t reserved_68; // offset: 68 (0x44) - uint32_t reserved_69; // offset: 69 (0x45) - uint32_t reserved_70; // offset: 70 (0x46) - uint32_t reserved_71; // offset: 0 (0x47) - uint32_t reserved_72; // offset: 1 (0x48) - uint32_t reserved_73; // offset: 2 (0x49) - uint32_t reserved_74; // offset: 3 (0x4A) - uint32_t reserved_75; // offset: 4 (0x4B) - uint32_t reserved_76; // offset: 5 (0x4C) - uint32_t reserved_77; // offset: 6 (0x4D) - uint32_t reserved_78; // offset: 7 (0x4E) - uint32_t reserved_79; // offset: 79 (0x4F) - uint32_t reserved_80; // offset: 80 (0x50) - uint32_t reserved_81; // offset: 81 (0x51) - uint32_t reserved_82; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t reserved_84; // offset: 84 (0x54) - uint32_t reserved_85; // offset: 85 (0x55) - uint32_t reserved_86; // offset: 86 (0x56) - uint32_t reserved_87; // offset: 87 (0x57) - uint32_t reserved_88; // offset: 88 (0x58) - uint32_t reserved_89; // offset: 89 (0x59) - uint32_t reserved_90; // offset: 90 (0x5A) - uint32_t reserved_91; // offset: 91 (0x5B) - uint32_t reserved_92; // offset: 92 (0x5C) - uint32_t reserved_93; // offset: 93 (0x5D) - uint32_t reserved_94; // offset: 94 (0x5E) - uint32_t reserved_95; // offset: 95 (0x5F) - uint32_t reserved_96; // offset: 96 (0x60) - uint32_t reserved_97; // offset: 97 (0x61) - uint32_t reserved_98; // offset: 98 (0x62) - uint32_t reserved_99; // offset: 99 (0x63) - uint32_t reserved_100; // offset: 100 (0x64) - uint32_t reserved_101; // offset: 101 (0x65) - uint32_t reserved_102; // offset: 102 (0x66) - uint32_t reserved_103; // offset: 103 (0x67) - uint32_t reserved_104; // offset: 104 (0x68) - uint32_t reserved_105; // offset: 105 (0x69) - uint32_t reserved_106; // offset: 106 (0x6A) - uint32_t reserved_107; // offset: 107 (0x6B) - uint32_t reserved_108; // offset: 108 (0x6C) - uint32_t reserved_109; // offset: 109 (0x6D) - uint32_t reserved_110; // offset: 110 (0x6E) - uint32_t reserved_111; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t reserved_114; // offset: 114 (0x72) - uint32_t reserved_115; // offset: 115 (0x73) - uint32_t reserved_116; // offset: 116 (0x74) - uint32_t reserved_117; // offset: 117 (0x75) - uint32_t reserved_118; // offset: 118 (0x76) - uint32_t reserved_119; // offset: 119 (0x77) - uint32_t reserved_120; // offset: 120 (0x78) - uint32_t reserved_121; // offset: 121 (0x79) - uint32_t reserved_122; // offset: 122 (0x7A) - uint32_t reserved_123; // offset: 123 (0x7B) - uint32_t reserved_124; // offset: 124 (0x7C) - uint32_t reserved_125; // offset: 125 (0x7D) - /* reserved_126,127: repurposed for driver-internal use */ - uint32_t sdma_engine_id; - uint32_t sdma_queue_id; -}; - -struct v12_compute_mqd { - uint32_t header; // offset: 0 (0x0) - uint32_t compute_dispatch_initiator; // offset: 1 (0x1) - uint32_t compute_dim_x; // offset: 2 (0x2) - uint32_t compute_dim_y; // offset: 3 (0x3) - uint32_t compute_dim_z; // offset: 4 (0x4) - uint32_t compute_start_x; // offset: 5 (0x5) - uint32_t compute_start_y; // offset: 6 (0x6) - uint32_t compute_start_z; // offset: 7 (0x7) - uint32_t compute_num_thread_x; // offset: 8 (0x8) - uint32_t compute_num_thread_y; // offset: 9 (0x9) - uint32_t compute_num_thread_z; // offset: 10 (0xA) - uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) - uint32_t compute_perfcount_enable; // offset: 12 (0xC) - uint32_t compute_pgm_lo; // offset: 13 (0xD) - uint32_t compute_pgm_hi; // offset: 14 (0xE) - uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) - uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) - uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) - uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) - uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) - uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) - uint32_t compute_vmid; // offset: 21 (0x15) - uint32_t compute_resource_limits; // offset: 22 (0x16) - uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17) - uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18) - uint32_t compute_tmpring_size; // offset: 25 (0x19) - uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A) - uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B) - uint32_t compute_restart_x; // offset: 28 (0x1C) - uint32_t compute_restart_y; // offset: 29 (0x1D) - uint32_t compute_restart_z; // offset: 30 (0x1E) - uint32_t compute_thread_trace_enable; // offset: 31 (0x1F) - uint32_t compute_misc_reserved; // offset: 32 (0x20) - uint32_t compute_dispatch_id; // offset: 33 (0x21) - uint32_t compute_threadgroup_id; // offset: 34 (0x22) - uint32_t compute_req_ctrl; // offset: 35 (0x23) - uint32_t reserved_36; // offset: 36 (0x24) - uint32_t compute_user_accum_0; // offset: 37 (0x25) - uint32_t compute_user_accum_1; // offset: 38 (0x26) - uint32_t compute_user_accum_2; // offset: 39 (0x27) - uint32_t compute_user_accum_3; // offset: 40 (0x28) - uint32_t compute_pgm_rsrc3; // offset: 41 (0x29) - uint32_t compute_ddid_index; // offset: 42 (0x2A) - uint32_t compute_shader_chksum; // offset: 43 (0x2B) - uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C) - uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D) - uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E) - uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F) - uint32_t compute_dispatch_interleave; // offset: 48 (0x30) - uint32_t compute_relaunch; // offset: 49 (0x31) - uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32) - uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33) - uint32_t compute_wave_restore_control; // offset: 52 (0x34) - uint32_t reserved_53; // offset: 53 (0x35) - uint32_t reserved_54; // offset: 54 (0x36) - uint32_t reserved_55; // offset: 55 (0x37) - uint32_t reserved_56; // offset: 56 (0x38) - uint32_t reserved_57; // offset: 57 (0x39) - uint32_t reserved_58; // offset: 58 (0x3A) - uint32_t compute_static_thread_mgmt_se8; // offset: 59 (0x3B) - uint32_t reserved_60; // offset: 60 (0x3C) - uint32_t reserved_61; // offset: 61 (0x3D) - uint32_t reserved_62; // offset: 62 (0x3E) - uint32_t reserved_63; // offset: 63 (0x3F) - uint32_t reserved_64; // offset: 64 (0x40) - uint32_t compute_user_data_0; // offset: 65 (0x41) - uint32_t compute_user_data_1; // offset: 66 (0x42) - uint32_t compute_user_data_2; // offset: 67 (0x43) - uint32_t compute_user_data_3; // offset: 68 (0x44) - uint32_t compute_user_data_4; // offset: 69 (0x45) - uint32_t compute_user_data_5; // offset: 70 (0x46) - uint32_t compute_user_data_6; // offset: 71 (0x47) - uint32_t compute_user_data_7; // offset: 72 (0x48) - uint32_t compute_user_data_8; // offset: 73 (0x49) - uint32_t compute_user_data_9; // offset: 74 (0x4A) - uint32_t compute_user_data_10; // offset: 75 (0x4B) - uint32_t compute_user_data_11; // offset: 76 (0x4C) - uint32_t compute_user_data_12; // offset: 77 (0x4D) - uint32_t compute_user_data_13; // offset: 78 (0x4E) - uint32_t compute_user_data_14; // offset: 79 (0x4F) - uint32_t compute_user_data_15; // offset: 80 (0x50) - uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51) - uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52) - uint32_t reserved_83; // offset: 83 (0x53) - uint32_t reserved_84; // offset: 84 (0x54) - uint32_t reserved_85; // offset: 85 (0x55) - uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56) - uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57) - uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58) - uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59) - uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A) - uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B) - uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C) - uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D) - uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E) - uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F) - uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60) - uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61) - uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62) - uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63) - uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64) - uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65) - uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66) - uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67) - uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68) - uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69) - uint32_t disable_queue; // offset: 106 (0x6A) - uint32_t reserved_107; // offset: 107 (0x6B) - uint32_t reserved_108; // offset: 108 (0x6C) - uint32_t reserved_109; // offset: 109 (0x6D) - uint32_t reserved_110; // offset: 110 (0x6E) - uint32_t reserved_111; // offset: 111 (0x6F) - uint32_t reserved_112; // offset: 112 (0x70) - uint32_t reserved_113; // offset: 113 (0x71) - uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) - uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) - uint32_t cp_packet_id_lo; // offset: 116 (0x74) - uint32_t cp_packet_id_hi; // offset: 117 (0x75) - uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) - uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) - uint32_t reserved_120; // offset: 120 (0x78) - uint32_t reserved_121; // offset: 121 (0x79) - uint32_t reserved_122; // offset: 122 (0x7A) - uint32_t reserved_123; // offset: 123 (0x7B) - uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) - uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) - uint32_t reserved_126; // offset: 126 (0x7E) - uint32_t reserved_127; // offset: 127 (0x7F) - uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) - uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) - uint32_t cp_hqd_active; // offset: 130 (0x82) - uint32_t cp_hqd_vmid; // offset: 131 (0x83) - uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) - uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) - uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) - uint32_t cp_hqd_quantum; // offset: 135 (0x87) - uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) - uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) - uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) - uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) - uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) - uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) - uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) - uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) - uint32_t reserved_144; // offset: 144 (0x90) - uint32_t cp_hqd_pq_control; // offset: 145 (0x91) - uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) - uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) - uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) - uint32_t cp_hqd_ib_control; // offset: 149 (0x95) - uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) - uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) - uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) - uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) - uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) - uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) - uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) - uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) - uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) - uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) - uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) - uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) - uint32_t cp_mqd_control; // offset: 162 (0xA2) - uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) - uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) - uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) - uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) - uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) - uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) - uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) - uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) - uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) - uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) - uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) - uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) - uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) - uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) - uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) - uint32_t reserved_178; // offset: 178 (0xB2) - uint32_t cp_hqd_error; // offset: 179 (0xB3) - uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) - uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) - uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) - uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) - uint32_t reserved_184; // offset: 184 (0xB8) - uint32_t reserved_185; // offset: 185 (0xB9) - uint32_t reserved_186; // offset: 186 (0xBA) - uint32_t reserved_187; // offset: 187 (0xBB) - uint32_t reserved_188; // offset: 188 (0xBC) - uint32_t reserved_189; // offset: 189 (0xBD) - uint32_t reserved_190; // offset: 190 (0xBE) - uint32_t reserved_191; // offset: 191 (0xBF) - uint32_t iqtimer_pkt_header; // offset: 192 (0xC0) - uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1) - uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2) - uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3) - uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4) - uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5) - uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6) - uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7) - uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8) - uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9) - uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA) - uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB) - uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC) - uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD) - uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE) - uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF) - uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0) - uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1) - uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2) - uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3) - uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4) - uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5) - uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6) - uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7) - uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8) - uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9) - uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA) - uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB) - uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC) - uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD) - uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE) - uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF) - uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0) - uint32_t reserved_225; // offset: 225 (0xE1) - uint32_t reserved_226; // offset: 226 (0xE2) - uint32_t reserved_227; // offset: 227 (0xE3) - uint32_t set_resources_header; // offset: 228 (0xE4) - uint32_t set_resources_dw1; // offset: 229 (0xE5) - uint32_t set_resources_dw2; // offset: 230 (0xE6) - uint32_t set_resources_dw3; // offset: 231 (0xE7) - uint32_t set_resources_dw4; // offset: 232 (0xE8) - uint32_t set_resources_dw5; // offset: 233 (0xE9) - uint32_t set_resources_dw6; // offset: 234 (0xEA) - uint32_t set_resources_dw7; // offset: 235 (0xEB) - uint32_t reserved_236; // offset: 236 (0xEC) - uint32_t reserved_237; // offset: 237 (0xED) - uint32_t reserved_238; // offset: 238 (0xEE) - uint32_t reserved_239; // offset: 239 (0xEF) - uint32_t queue_doorbell_id0; // offset: 240 (0xF0) - uint32_t queue_doorbell_id1; // offset: 241 (0xF1) - uint32_t queue_doorbell_id2; // offset: 242 (0xF2) - uint32_t queue_doorbell_id3; // offset: 243 (0xF3) - uint32_t queue_doorbell_id4; // offset: 244 (0xF4) - uint32_t queue_doorbell_id5; // offset: 245 (0xF5) - uint32_t queue_doorbell_id6; // offset: 246 (0xF6) - uint32_t queue_doorbell_id7; // offset: 247 (0xF7) - uint32_t queue_doorbell_id8; // offset: 248 (0xF8) - uint32_t queue_doorbell_id9; // offset: 249 (0xF9) - uint32_t queue_doorbell_id10; // offset: 250 (0xFA) - uint32_t queue_doorbell_id11; // offset: 251 (0xFB) - uint32_t queue_doorbell_id12; // offset: 252 (0xFC) - uint32_t queue_doorbell_id13; // offset: 253 (0xFD) - uint32_t queue_doorbell_id14; // offset: 254 (0xFE) - uint32_t queue_doorbell_id15; // offset: 255 (0xFF) - uint32_t control_buf_addr_lo; // offset: 256 (0x100) - uint32_t control_buf_addr_hi; // offset: 257 (0x101) - uint32_t control_buf_wptr_lo; // offset: 258 (0x102) - uint32_t control_buf_wptr_hi; // offset: 259 (0x103) - uint32_t control_buf_dptr_lo; // offset: 260 (0x104) - uint32_t control_buf_dptr_hi; // offset: 261 (0x105) - uint32_t control_buf_num_entries; // offset: 262 (0x106) - uint32_t draw_ring_addr_lo; // offset: 263 (0x107) - uint32_t draw_ring_addr_hi; // offset: 264 (0x108) - uint32_t reserved_265; // offset: 265 (0x109) - uint32_t reserved_266; // offset: 266 (0x10A) - uint32_t reserved_267; // offset: 267 (0x10B) - uint32_t reserved_268; // offset: 268 (0x10C) - uint32_t reserved_269; // offset: 269 (0x10D) - uint32_t reserved_270; // offset: 270 (0x10E) - uint32_t reserved_271; // offset: 271 (0x10F) - uint32_t dfwx_flags; // offset: 272 (0x110) - uint32_t dfwx_slot; // offset: 273 (0x111) - uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) - uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) - uint32_t reserved_276; // offset: 276 (0x114) - uint32_t reserved_277; // offset: 277 (0x115) - uint32_t reserved_278; // offset: 278 (0x116) - uint32_t reserved_279; // offset: 279 (0x117) - uint32_t reserved_280; // offset: 280 (0x118) - uint32_t reserved_281; // offset: 281 (0x119) - uint32_t reserved_282; // offset: 282 (0x11A) - uint32_t reserved_283; // offset: 283 (0x11B) - uint32_t reserved_284; // offset: 284 (0x11C) - uint32_t reserved_285; // offset: 285 (0x11D) - uint32_t reserved_286; // offset: 286 (0x11E) - uint32_t reserved_287; // offset: 287 (0x11F) - uint32_t reserved_288; // offset: 288 (0x120) - uint32_t reserved_289; // offset: 289 (0x121) - uint32_t reserved_290; // offset: 290 (0x122) - uint32_t reserved_291; // offset: 291 (0x123) - uint32_t reserved_292; // offset: 292 (0x124) - uint32_t reserved_293; // offset: 293 (0x125) - uint32_t reserved_294; // offset: 294 (0x126) - uint32_t reserved_295; // offset: 295 (0x127) - uint32_t reserved_296; // offset: 296 (0x128) - uint32_t reserved_297; // offset: 297 (0x129) - uint32_t reserved_298; // offset: 298 (0x12A) - uint32_t reserved_299; // offset: 299 (0x12B) - uint32_t reserved_300; // offset: 300 (0x12C) - uint32_t reserved_301; // offset: 301 (0x12D) - uint32_t reserved_302; // offset: 302 (0x12E) - uint32_t reserved_303; // offset: 303 (0x12F) - uint32_t reserved_304; // offset: 304 (0x130) - uint32_t reserved_305; // offset: 305 (0x131) - uint32_t reserved_306; // offset: 306 (0x132) - uint32_t reserved_307; // offset: 307 (0x133) - uint32_t reserved_308; // offset: 308 (0x134) - uint32_t reserved_309; // offset: 309 (0x135) - uint32_t reserved_310; // offset: 310 (0x136) - uint32_t reserved_311; // offset: 311 (0x137) - uint32_t reserved_312; // offset: 312 (0x138) - uint32_t reserved_313; // offset: 313 (0x139) - uint32_t reserved_314; // offset: 314 (0x13A) - uint32_t reserved_315; // offset: 315 (0x13B) - uint32_t reserved_316; // offset: 316 (0x13C) - uint32_t reserved_317; // offset: 317 (0x13D) - uint32_t reserved_318; // offset: 318 (0x13E) - uint32_t reserved_319; // offset: 319 (0x13F) - uint32_t reserved_320; // offset: 320 (0x140) - uint32_t reserved_321; // offset: 321 (0x141) - uint32_t reserved_322; // offset: 322 (0x142) - uint32_t reserved_323; // offset: 323 (0x143) - uint32_t reserved_324; // offset: 324 (0x144) - uint32_t reserved_325; // offset: 325 (0x145) - uint32_t reserved_326; // offset: 326 (0x146) - uint32_t reserved_327; // offset: 327 (0x147) - uint32_t reserved_328; // offset: 328 (0x148) - uint32_t reserved_329; // offset: 329 (0x149) - uint32_t reserved_330; // offset: 330 (0x14A) - uint32_t reserved_331; // offset: 331 (0x14B) - uint32_t reserved_332; // offset: 332 (0x14C) - uint32_t reserved_333; // offset: 333 (0x14D) - uint32_t reserved_334; // offset: 334 (0x14E) - uint32_t reserved_335; // offset: 335 (0x14F) - uint32_t reserved_336; // offset: 336 (0x150) - uint32_t reserved_337; // offset: 337 (0x151) - uint32_t reserved_338; // offset: 338 (0x152) - uint32_t reserved_339; // offset: 339 (0x153) - uint32_t reserved_340; // offset: 340 (0x154) - uint32_t reserved_341; // offset: 341 (0x155) - uint32_t reserved_342; // offset: 342 (0x156) - uint32_t reserved_343; // offset: 343 (0x157) - uint32_t reserved_344; // offset: 344 (0x158) - uint32_t reserved_345; // offset: 345 (0x159) - uint32_t reserved_346; // offset: 346 (0x15A) - uint32_t reserved_347; // offset: 347 (0x15B) - uint32_t reserved_348; // offset: 348 (0x15C) - uint32_t reserved_349; // offset: 349 (0x15D) - uint32_t reserved_350; // offset: 350 (0x15E) - uint32_t reserved_351; // offset: 351 (0x15F) - uint32_t reserved_352; // offset: 352 (0x160) - uint32_t reserved_353; // offset: 353 (0x161) - uint32_t reserved_354; // offset: 354 (0x162) - uint32_t reserved_355; // offset: 355 (0x163) - uint32_t reserved_356; // offset: 356 (0x164) - uint32_t reserved_357; // offset: 357 (0x165) - uint32_t reserved_358; // offset: 358 (0x166) - uint32_t reserved_359; // offset: 359 (0x167) - uint32_t reserved_360; // offset: 360 (0x168) - uint32_t reserved_361; // offset: 361 (0x169) - uint32_t reserved_362; // offset: 362 (0x16A) - uint32_t reserved_363; // offset: 363 (0x16B) - uint32_t reserved_364; // offset: 364 (0x16C) - uint32_t reserved_365; // offset: 365 (0x16D) - uint32_t reserved_366; // offset: 366 (0x16E) - uint32_t reserved_367; // offset: 367 (0x16F) - uint32_t reserved_368; // offset: 368 (0x170) - uint32_t reserved_369; // offset: 369 (0x171) - uint32_t reserved_370; // offset: 370 (0x172) - uint32_t reserved_371; // offset: 371 (0x173) - uint32_t reserved_372; // offset: 372 (0x174) - uint32_t reserved_373; // offset: 373 (0x175) - uint32_t reserved_374; // offset: 374 (0x176) - uint32_t reserved_375; // offset: 375 (0x177) - uint32_t reserved_376; // offset: 376 (0x178) - uint32_t reserved_377; // offset: 377 (0x179) - uint32_t reserved_378; // offset: 378 (0x17A) - uint32_t reserved_379; // offset: 379 (0x17B) - uint32_t reserved_380; // offset: 380 (0x17C) - uint32_t reserved_381; // offset: 381 (0x17D) - uint32_t reserved_382; // offset: 382 (0x17E) - uint32_t reserved_383; // offset: 383 (0x17F) - uint32_t reserved_384; // offset: 384 (0x180) - uint32_t reserved_385; // offset: 385 (0x181) - uint32_t reserved_386; // offset: 386 (0x182) - uint32_t reserved_387; // offset: 387 (0x183) - uint32_t reserved_388; // offset: 388 (0x184) - uint32_t reserved_389; // offset: 389 (0x185) - uint32_t reserved_390; // offset: 390 (0x186) - uint32_t reserved_391; // offset: 391 (0x187) - uint32_t reserved_392; // offset: 392 (0x188) - uint32_t reserved_393; // offset: 393 (0x189) - uint32_t reserved_394; // offset: 394 (0x18A) - uint32_t reserved_395; // offset: 395 (0x18B) - uint32_t reserved_396; // offset: 396 (0x18C) - uint32_t reserved_397; // offset: 397 (0x18D) - uint32_t reserved_398; // offset: 398 (0x18E) - uint32_t reserved_399; // offset: 399 (0x18F) - uint32_t reserved_400; // offset: 400 (0x190) - uint32_t reserved_401; // offset: 401 (0x191) - uint32_t reserved_402; // offset: 402 (0x192) - uint32_t reserved_403; // offset: 403 (0x193) - uint32_t reserved_404; // offset: 404 (0x194) - uint32_t reserved_405; // offset: 405 (0x195) - uint32_t reserved_406; // offset: 406 (0x196) - uint32_t reserved_407; // offset: 407 (0x197) - uint32_t reserved_408; // offset: 408 (0x198) - uint32_t reserved_409; // offset: 409 (0x199) - uint32_t reserved_410; // offset: 410 (0x19A) - uint32_t reserved_411; // offset: 411 (0x19B) - uint32_t reserved_412; // offset: 412 (0x19C) - uint32_t reserved_413; // offset: 413 (0x19D) - uint32_t reserved_414; // offset: 414 (0x19E) - uint32_t reserved_415; // offset: 415 (0x19F) - uint32_t reserved_416; // offset: 416 (0x1A0) - uint32_t reserved_417; // offset: 417 (0x1A1) - uint32_t reserved_418; // offset: 418 (0x1A2) - uint32_t reserved_419; // offset: 419 (0x1A3) - uint32_t reserved_420; // offset: 420 (0x1A4) - uint32_t reserved_421; // offset: 421 (0x1A5) - uint32_t reserved_422; // offset: 422 (0x1A6) - uint32_t reserved_423; // offset: 423 (0x1A7) - uint32_t reserved_424; // offset: 424 (0x1A8) - uint32_t reserved_425; // offset: 425 (0x1A9) - uint32_t reserved_426; // offset: 426 (0x1AA) - uint32_t reserved_427; // offset: 427 (0x1AB) - uint32_t reserved_428; // offset: 428 (0x1AC) - uint32_t reserved_429; // offset: 429 (0x1AD) - uint32_t reserved_430; // offset: 430 (0x1AE) - uint32_t reserved_431; // offset: 431 (0x1AF) - uint32_t reserved_432; // offset: 432 (0x1B0) - uint32_t reserved_433; // offset: 433 (0x1B1) - uint32_t reserved_434; // offset: 434 (0x1B2) - uint32_t reserved_435; // offset: 435 (0x1B3) - uint32_t reserved_436; // offset: 436 (0x1B4) - uint32_t reserved_437; // offset: 437 (0x1B5) - uint32_t reserved_438; // offset: 438 (0x1B6) - uint32_t reserved_439; // offset: 439 (0x1B7) - uint32_t reserved_440; // offset: 440 (0x1B8) - uint32_t reserved_441; // offset: 441 (0x1B9) - uint32_t reserved_442; // offset: 442 (0x1BA) - uint32_t reserved_443; // offset: 443 (0x1BB) - uint32_t reserved_444; // offset: 444 (0x1BC) - uint32_t reserved_445; // offset: 445 (0x1BD) - uint32_t reserved_446; // offset: 446 (0x1BE) - uint32_t reserved_447; // offset: 447 (0x1BF) - uint32_t gws_0_val; // offset: 448 (0x1C0) - uint32_t gws_1_val; // offset: 449 (0x1C1) - uint32_t gws_2_val; // offset: 450 (0x1C2) - uint32_t gws_3_val; // offset: 451 (0x1C3) - uint32_t gws_4_val; // offset: 452 (0x1C4) - uint32_t gws_5_val; // offset: 453 (0x1C5) - uint32_t gws_6_val; // offset: 454 (0x1C6) - uint32_t gws_7_val; // offset: 455 (0x1C7) - uint32_t gws_8_val; // offset: 456 (0x1C8) - uint32_t gws_9_val; // offset: 457 (0x1C9) - uint32_t gws_10_val; // offset: 458 (0x1CA) - uint32_t gws_11_val; // offset: 459 (0x1CB) - uint32_t gws_12_val; // offset: 460 (0x1CC) - uint32_t gws_13_val; // offset: 461 (0x1CD) - uint32_t gws_14_val; // offset: 462 (0x1CE) - uint32_t gws_15_val; // offset: 463 (0x1CF) - uint32_t gws_16_val; // offset: 464 (0x1D0) - uint32_t gws_17_val; // offset: 465 (0x1D1) - uint32_t gws_18_val; // offset: 466 (0x1D2) - uint32_t gws_19_val; // offset: 467 (0x1D3) - uint32_t gws_20_val; // offset: 468 (0x1D4) - uint32_t gws_21_val; // offset: 469 (0x1D5) - uint32_t gws_22_val; // offset: 470 (0x1D6) - uint32_t gws_23_val; // offset: 471 (0x1D7) - uint32_t gws_24_val; // offset: 472 (0x1D8) - uint32_t gws_25_val; // offset: 473 (0x1D9) - uint32_t gws_26_val; // offset: 474 (0x1DA) - uint32_t gws_27_val; // offset: 475 (0x1DB) - uint32_t gws_28_val; // offset: 476 (0x1DC) - uint32_t gws_29_val; // offset: 477 (0x1DD) - uint32_t gws_30_val; // offset: 478 (0x1DE) - uint32_t gws_31_val; // offset: 479 (0x1DF) - uint32_t gws_32_val; // offset: 480 (0x1E0) - uint32_t gws_33_val; // offset: 481 (0x1E1) - uint32_t gws_34_val; // offset: 482 (0x1E2) - uint32_t gws_35_val; // offset: 483 (0x1E3) - uint32_t gws_36_val; // offset: 484 (0x1E4) - uint32_t gws_37_val; // offset: 485 (0x1E5) - uint32_t gws_38_val; // offset: 486 (0x1E6) - uint32_t gws_39_val; // offset: 487 (0x1E7) - uint32_t gws_40_val; // offset: 488 (0x1E8) - uint32_t gws_41_val; // offset: 489 (0x1E9) - uint32_t gws_42_val; // offset: 490 (0x1EA) - uint32_t gws_43_val; // offset: 491 (0x1EB) - uint32_t gws_44_val; // offset: 492 (0x1EC) - uint32_t gws_45_val; // offset: 493 (0x1ED) - uint32_t gws_46_val; // offset: 494 (0x1EE) - uint32_t gws_47_val; // offset: 495 (0x1EF) - uint32_t gws_48_val; // offset: 496 (0x1F0) - uint32_t gws_49_val; // offset: 497 (0x1F1) - uint32_t gws_50_val; // offset: 498 (0x1F2) - uint32_t gws_51_val; // offset: 499 (0x1F3) - uint32_t gws_52_val; // offset: 500 (0x1F4) - uint32_t gws_53_val; // offset: 501 (0x1F5) - uint32_t gws_54_val; // offset: 502 (0x1F6) - uint32_t gws_55_val; // offset: 503 (0x1F7) - uint32_t gws_56_val; // offset: 504 (0x1F8) - uint32_t gws_57_val; // offset: 505 (0x1F9) - uint32_t gws_58_val; // offset: 506 (0x1FA) - uint32_t gws_59_val; // offset: 507 (0x1FB) - uint32_t gws_60_val; // offset: 508 (0x1FC) - uint32_t gws_61_val; // offset: 509 (0x1FD) - uint32_t gws_62_val; // offset: 510 (0x1FE) - uint32_t gws_63_val; // offset: 511 (0x1FF) -}; - -#endif /* V11_STRUCTS_H_ */ diff --git a/tinygrad/extra/amdpci/overlay/gc_9_4_3.h b/tinygrad/extra/amdpci/overlay/gc_9_4_3.h deleted file mode 100644 index c937e68a..00000000 --- a/tinygrad/extra/amdpci/overlay/gc_9_4_3.h +++ /dev/null @@ -1,7 +0,0 @@ -// From MQD struct -#define regCOMPUTE_CURRENT_LOGIC_XCC_ID 0x0e25 -#define regCOMPUTE_CURRENT_LOGIC_XCC_ID_BASE_IDX 0 -// Mask is probably not full register, doesn't matter though -#define COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID__SHIFT 0x0 -#define COMPUTE_CURRENT_LOGIC_XCC_ID__CURRENT_LOGIC_XCC_ID_MASK 0xFFFFFFFFL - diff --git a/tinygrad/extra/amdpci/proclogs.py b/tinygrad/extra/amdpci/proclogs.py deleted file mode 100644 index 6019366e..00000000 --- a/tinygrad/extra/amdpci/proclogs.py +++ /dev/null @@ -1,50 +0,0 @@ -import re, ctypes, sys - -from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0 - -def parse_amdgpu_logs(log_content, register_names=None): - register_map = register_names - - final = "" - def replace_register(match): - register = match.group(1) - return f"Reading register {register_map.get(int(register, base=16), register)}" - - pattern = r'Reading register (0x[0-9a-fA-F]+)' - - processed_log = re.sub(pattern, replace_register, log_content) - - def replace_register_2(match): - register = match.group(1) - return f"Writing register {register_map.get(int(register, base=16), register)}" - - pattern = r'Writing register (0x[0-9a-fA-F]+)' - processed_log = re.sub(pattern, replace_register_2, processed_log) - return processed_log - -def main(): - regs_offset = {13: {0: [3072, 37784576]}, 28: {0: [93184, 37754880], 1: [201327616, 201461760], 2: [209716224, 209850368], 3: [218104832, 218238976], 4: [226493440, 226627584], 5: [234882048, 235016192], 6: [243270656, 243404800]}, 21: {0: [28672, 12582912, 37795840, 130023424, 306184192], 1: [201326592, 201463808, 201465856, 204210176, 204472320], 2: [209715200, 209852416, 209854464, 212598784, 212860928], 3: [218103808, 218241024, 218243072, 220987392, 221249536], 4: [226492416, 226629632, 226631680, 229376000, 229638144], 5: [234881024, 235018240, 235020288, 237764608, 238026752], 6: [243269632, 243406848, 243408896, 246153216, 246415360]}, 22: {0: [18, 192, 13504, 36864, 37764096]}, 1: {0: [4704, 40960, 114688, 37760000]}, 2: {0: [3872, 37790720]}, 11: {0: [70656, 38103040]}, 12: {0: [106496, 37783552]}, 15: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 16: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 14: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 26: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 23: {0: [4256, 37789696]}, 33: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 25: {0: []}, 3: {0: [4704, 40960, 114688, 37760000]}, 4: {0: [4704, 40960, 114688, 37760000]}, 24: {0: [92160, 92672, 37752832, 54788096]}, 27: {0: [91648, 37751808], 1: [201339904, 201458176], 2: [209728512, 209846784], 3: [218117120, 218235392], 4: [226505728, 226624000], 5: [234894336, 235012608], 6: [243282944, 243401216]}, 29: {0: [201342976, 201344000, 205520896, 205537280], 1: [209731584, 209732608, 213909504, 213925888], 2: [218120192, 218121216, 222298112, 222314496], 3: [226508800, 226509824, 230686720, 230703104], 4: [234897408, 234898432, 239075328, 239091712], 5: [243286016, 243287040, 247463936, 247480320]}, 17: {0: [30720, 32256], 1: [31488, 73728]}} - - reg_names = {} - def _prepare_registers(modules): - for base, m in modules: - for k, regval in m.__dict__.items(): - if k.startswith("reg") and not k.endswith("_BASE_IDX") and (base_idx:=getattr(m, f"{k}_BASE_IDX", None)) is not None: - reg_names[regs_offset[am.__dict__.get(f"{base}_HWIP")][0][base_idx] + regval] = k - - _prepare_registers([("MP0", mp_13_0_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)]) - - with open(sys.argv[1], 'r') as f: - log_content = log_content_them = f.read() - - processed_log = parse_amdgpu_logs(log_content, reg_names) - - with open(sys.argv[2], 'w') as f: - f.write(processed_log) - -if __name__ == '__main__': - if len(sys.argv) != 3: - print("Usage: ") - sys.exit(1) - - main() \ No newline at end of file diff --git a/tinygrad/extra/amdpci/setup_python_cap.sh b/tinygrad/extra/amdpci/setup_python_cap.sh deleted file mode 100755 index 97df87b7..00000000 --- a/tinygrad/extra/amdpci/setup_python_cap.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -PYTHON_PATH=$(readlink -f $(which python3)) -sudo setcap 'cap_dac_override,cap_sys_rawio,cap_sys_admin,cap_ipc_lock=ep' $PYTHON_PATH diff --git a/tinygrad/extra/amdpci/setup_vfio.sh b/tinygrad/extra/amdpci/setup_vfio.sh deleted file mode 100755 index 6ca786ed..00000000 --- a/tinygrad/extra/amdpci/setup_vfio.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/bash -sudo modprobe vfio-pci disable_idle_d3=1 diff --git a/tinygrad/extra/archprobe.py b/tinygrad/extra/archprobe.py deleted file mode 100644 index 73eb5037..00000000 --- a/tinygrad/extra/archprobe.py +++ /dev/null @@ -1,154 +0,0 @@ -# copying the kernels from https://github.com/microsoft/ArchProbe into Python -import numpy as np -import pickle -from tinygrad.runtime.ops_gpu import CLProgram, CLBuffer -from tinygrad import dtypes -from tqdm import trange, tqdm -from matplotlib import pyplot as plt - -tests = {} -def register_test(fxn): - tests[fxn.__name__] = fxn - -def warp_size2(nthread): - prg = """__kernel void warp_size2( - __global float* src, - __global int* dst, - const int niter, - const int prime_number - ) { - int drain = 0; - for (int j = 0; j < niter; ++j) { - drain += j / prime_number; - barrier(0); - } - dst[get_local_id(0)] = drain; - }""" - src_buf = CLBuffer(1, dtypes.float32) - dst_buf = CLBuffer(1, dtypes.int32) - cl = CLProgram("warp_size2", prg, argdtypes=[None, None, np.int32, np.int32]) - return min([cl([nthread, 1024, 1], [nthread, 1, 1], src_buf, dst_buf, 10, 3, wait=True) for _ in range(5)])*1e9 - -@register_test -def test_warp_size(): - return [(nthread, warp_size2(nthread)) for nthread in trange(1,256)] - -def reg_count(nthread, ngrp, nreg): - reg_declr = ''.join([f"float reg_data{i} = (float)niter + {i};\n" for i in range(nreg)]) - reg_comp = ''.join([f"reg_data{i} *= {(i-1)%nreg};\n" for i in range(nreg)]) - reg_reduce = ''.join([f"out_buf[{i}] = reg_data{i};\n" for i in range(nreg)]) - prg = f"""__kernel void reg_count( - __global float* out_buf, - __private const int niter - ) {{ - {reg_declr} - int i = 0; - for (; i < niter; ++i) {{ - {reg_comp} - }} - i = i >> 31; - {reg_reduce} - }}""" - out_buf = CLBuffer(1, dtypes.float32) - cl = CLProgram("reg_count", prg, argdtypes=[None, np.int32]) - return min([cl([nthread, ngrp, 1], [nthread, 1, 1], out_buf, 20, wait=True) for _ in range(10)])*1e9 - -@register_test -def test_reg_count(nthread=1, ngrp=1): - base = reg_count(nthread, ngrp, 1) - return [(nreg, (reg_count(nthread, ngrp, nreg)-base)/nreg) for nreg in trange(4, 513, 4)] - -def buf_cache_hierarchy_pchase(ndata, stride=1, NCOMP=1, steps=65536): - ndata //= NCOMP*4 # ptr size - prg = f"""__kernel void buf_cache_hierarchy_pchase( - __global int{str(NCOMP) if NCOMP > 1 else ''}* src, - __global int* dst, - const int niter - ) {{ - int idx = 0; - for (int i = 0; i < niter; ++i) {{ - idx = src[idx]{'.x' if NCOMP > 1 else ''}; - }} - *dst = idx; - }}""" - idx_buf = np.zeros(ndata*NCOMP, dtype=np.int32) - for i in range(ndata): idx_buf[i*NCOMP] = (i + stride) % ndata - in_buf = CLBuffer.fromCPU(idx_buf) - out_buf = CLBuffer(1, dtypes.int32) - cl = CLProgram("buf_cache_hierarchy_pchase", prg, argdtypes=[None, None, np.int32]) - return min([cl([1, 1, 1], [1, 1, 1], in_buf, out_buf, steps, wait=True)/steps for _ in range(5)])*1e9 - -@register_test -def test_memory_latency(): - # requires cacheline < 16 - szs = [int(1.3**x) for x in range(20, 70)] - return [(ndata, buf_cache_hierarchy_pchase(ndata, NCOMP=16, steps=128*1024)) for ndata in tqdm(szs)] - -@register_test -def test_cacheline_size(): - # TODO: this buffer must be at least 2x the L1 cache for this test to work - return [(stride, buf_cache_hierarchy_pchase(4*65536, stride, steps=65536)) for stride in trange(1,64)] - -def cl_read(sz, niter=1): - prg = f"""__kernel void copy( - __global float4* src, - __global float* dst) {{ - int gid = get_global_id(0); - if (src[gid].x == 99+get_global_id(1)) *dst = 1; - }}""" - - in_buf = CLBuffer(sz//4, dtypes.float32) - out_buf = CLBuffer(1, dtypes.float32) - cl = CLProgram("copy", prg) - # NOTE: if nay of the niters form a local group, this is wrong - return min([cl([sz//16, niter, 1], [1, 1, 1], in_buf, out_buf, wait=True) for _ in range(10)])*1e9 - -@register_test -def test_read_bandwidth(): - szs = list(range(128*1024, 20*1024*1024, 128*1024)) - NITER = 8 - base = cl_read(16, niter=NITER) - return [(sz, (sz*NITER)/(cl_read(sz, niter=NITER)-base)) for sz in tqdm(szs)] - - -def gflops(niter=4, nroll=4, ngroups=4096): - NCOMP = 8 - prg = f"""__kernel void gflops( - __global float* out_buf - ) {{ - float{NCOMP} x = (float{NCOMP})({",".join(f"get_local_id(0)+{i}" for i in range(NCOMP))}); - float{NCOMP} y = (float{NCOMP})({",".join(f"get_local_id(1)+{i}" for i in range(NCOMP))}); - - for (int i = 0; i < {niter}; i++) {{ - {''.join(['x = mad(y, y, x); y = mad(x, x, y);'+chr(10)]*nroll)} - }} - - out_buf[get_global_id(0) >> 31] = {'+'.join(f"y.s{'0123456789abcdef'[i]}" for i in range(NCOMP))}; - }}""" - out_buf = CLBuffer(1, dtypes.float32) - cl = CLProgram("gflops", prg, options="-cl-mad-enable -cl-fast-relaxed-math") - FLOPS = NCOMP*2*2 * niter * nroll * ngroups * 32 - # NOTE: if nay of the niters form a local group, this is wrong - return FLOPS/(min([cl([32, ngroups, 1], [32, 1, 1], out_buf, wait=True) for _ in range(10)])*1e9) - -@register_test -def test_gflops(): - return [(niter, gflops(niter=niter, nroll=32)) for niter in trange(1, 32, 1)] - -if __name__ == "__main__": - cache = {} - #cache = pickle.load(open("/tmp/cache.pkl", "rb")) - #tests = {"test_cacheline_size": tests["test_cacheline_size"]} - plt.figure(figsize=(16, 9)) - for i,(k,test) in enumerate(tests.items()): - print(f"running {k}") - plt.subplot(2, (len(tests)+1)//2, i+1) - plt.title(k) - if k == "test_memory_latency": plt.xscale('log') - if k not in cache: cache[k] = test() - plt.plot(*zip(*cache[k])) - #pickle.dump(cache, open("/tmp/cache.pkl", "wb")) - - plt.tight_layout(pad=0.5) - plt.savefig("/tmp/results.png") - plt.show() diff --git a/tinygrad/extra/assembly/assembly.py b/tinygrad/extra/assembly/assembly.py deleted file mode 100644 index 1362d6de..00000000 --- a/tinygrad/extra/assembly/assembly.py +++ /dev/null @@ -1,189 +0,0 @@ -from typing import Tuple, List, NamedTuple, Any, Dict, Optional, Union, DefaultDict, cast -from tinygrad.codegen.kernel import Ops, MemOp, UOp -from tinygrad.uop.ops import BinaryOps, UnaryOps -from tinygrad.dtype import DType, dtypes -from tinygrad.helpers import DEBUG -from tinygrad.uop.ops import Variable, NumNode, MulNode, DivNode, ModNode, LtNode, SumNode, AndNode -import functools -import math -from collections import defaultdict - -_type_to_letter = {dtypes.float32: 'f', dtypes.bool: 'p', dtypes.int32: 'i', dtypes.int64: 'a', dtypes.uint32: 'u', dtypes.uint64: 'b', dtypes.float.vec(4): 'x', dtypes.uint8: 'uc', dtypes.float16: 'h', - dtypes.int8: 'c', dtypes.uint16: 'us', dtypes.float64: 'd'} - -class Register(NamedTuple): - nm:str - dtype:DType - scalar:bool - off:Optional[int] = None - def __repr__(self): return self.nm if self.off is None else f"{self.nm}:{self.off}" - def subregs(self): - if self.dtype == dtypes.float.vec(4): - return [Register(self.nm, dtypes.float, False, off=off) for off in range(4)] - return [] - -class AssemblyInstruction(NamedTuple): - op: Ops - out: Optional[Register] - vin: List[Union[Register, int, float]] - arg: Any = None - -# warp size of 32, s registers are shared across the warp, v are 32-wide vectors -class AssemblyLanguage: - supports_load3: bool = False - sin_is_sin2pi: bool = False - no_div: bool = False - #TODO: these should be global vars - cnts:DefaultDict[Tuple[DType, bool], int] = defaultdict(int) - tor: Dict[Any, Register] = {} - ins: List[AssemblyInstruction] = [] - - def type_to_letter(self,x): return _type_to_letter[x[0]].upper() if x[1] else _type_to_letter[x[0]] - def newreg(self, tok, dtype=dtypes.float32, scalar=False) -> Register: - self.tor[tok] = ret = Register(f"%{self.type_to_letter((dtype, scalar))}{self.cnts[(dtype, scalar)]}", dtype, scalar) - if dtype == dtypes.float.vec(4): - for off in range(4): - self.tor[tok] = Register(ret.nm, dtypes.float, ret.scalar, off) - self.cnts[(dtype, scalar)] += 1 - return ret - - def render_numnode(self, b) -> Register: - key = ("num", b) - if key not in self.tor: self.ins.append(AssemblyInstruction(Ops.LOAD, self.newreg(key, scalar=True, dtype=dtypes.int32), [], b)) - return self.tor[key] - - def render_alu(self, op, a:Register, b:Union[Register, int, float], dtype=dtypes.int32) -> Register: - key = (op, a, b) - if key not in self.tor: - #if not isinstance(b, Register): b = render_numnode(b) - self.ins.append(AssemblyInstruction(Ops.ALU, self.newreg(key, dtype=dtype, scalar=a.scalar and (not isinstance(b, Register) or b.scalar)), [a, b], op)) - return self.tor[key] - - def render_cast(self, a:Register, new_dtype:DType) -> Register: - if a.dtype == new_dtype: return a - key = (a, new_dtype) - if key not in self.tor: - self.ins.append(AssemblyInstruction(Ops.CAST, self.newreg(key, dtype=new_dtype), [a])) - return self.tor[key] - - render_ops: Any = { Variable: lambda self, ops, ctx: ctx.tor[self], NumNode: lambda self, ops, ctx: ctx.render_numnode(self.b), - MulNode: lambda self, ops, ctx: ctx.render_alu(BinaryOps.MUL, self.a.render(ops, ctx), self.b), - DivNode: lambda self, ops, ctx: ctx.render_alu(BinaryOps.DIV, self.a.render(ops, ctx), self.b), - ModNode: lambda self, ops, ctx: ctx.render_alu(BinaryOps.MOD, self.a.render(ops, ctx), self.b), - LtNode: lambda self, ops, ctx: ctx.render_alu(BinaryOps.CMPLT, self.a.render(ops, ctx), self.b, dtype=dtypes.bool), - SumNode: lambda self,ops,ctx: functools.reduce(lambda a,b: ctx.render_alu(BinaryOps.ADD, a, b.render(ops,ctx)), self.nodes[1:], self.nodes[0].render(ops,ctx)), - AndNode: lambda self,ops,ctx: functools.reduce(lambda a,b: ctx.render_alu(BinaryOps.MUL, a, b.render(ops,ctx), dtype=dtypes.bool), self.nodes[1:], self.nodes[0].render(ops,ctx)) } - - def addr_w_offset(self, args): - assert isinstance(args, MemOp) - idx = args.idx*args.memory_dtype.itemsize - off = 0 # TODO: should this be None? - if isinstance(idx, SumNode): - nums = [n.b for n in idx.nodes if isinstance(n, NumNode)] - if nums and nums[0] < 4096 and (idx-nums[0]).min >= 0: # TODO: different for each GPU? - idx -= nums[0] - off = cast(int, nums[0]) - reg = idx.render(self.render_ops, self) - if self.supports_load3: - if reg.scalar: - new_reg = self.newreg((reg.nm, 'vec'), dtype=reg.dtype) - self.ins.append(AssemblyInstruction(Ops.ALU, new_reg, [reg], UnaryOps.NOOP)) - reg = new_reg - return self.tor[args.name], reg, off - reg = self.render_alu(BinaryOps.ADD, self.render_cast(reg, dtypes.uint64), self.tor[args.name], dtype=dtypes.uint64) - return reg, None, off - -def uops_to_asmstyle(lang, function_name:str, uops:List[UOp]): - #TODO: Do not use clear() - lang.ins.clear() - lang.tor.clear() - lang.cnts.clear() - buf_to_dtype = {args:dtype for uop,dtype,_,args,_ in uops if uop == Ops.DEFINE_GLOBAL} - global_size, local_size = [], [] - skipload_branch = 0 - lang.ins += [AssemblyInstruction(Ops.SPECIAL, lang.newreg(buf, dtype=dtypes.uint64, scalar=True), [], buf) for buf in buf_to_dtype] - for u in uops: - uop,dtype,vin,args,_ = u - if uop == Ops.DEFINE_LOCAL: - lang.ins.append(AssemblyInstruction(Ops.DEFINE_LOCAL, None, [], args)) - lang.ins.append(AssemblyInstruction(Ops.ALU, lang.newreg(args[0], dtype=dtypes.uint64), [args[0]], UnaryOps.NOOP)) - elif uop == Ops.LOOP: - if args[1] == "global": - for i,var in enumerate(args[0]): - global_size.append(var.max+1) - lang.ins.append(AssemblyInstruction(Ops.SPECIAL, lang.newreg(var, dtype=dtypes.int32), [], f"gid{len(args[0])-1-i}")) - elif args[1] == "local": - for i,var in enumerate(args[0]): - local_size.append(var.max+1) - lang.ins.append(AssemblyInstruction(Ops.SPECIAL, lang.newreg(var, dtype=dtypes.int32), [], f"lid{len(args[0])-1-i}")) - else: - for var in args[0]: - if not isinstance(var, NumNode): # TODO: why is this coming through? - lang.ins.append(AssemblyInstruction(Ops.LOAD, lang.newreg(var, dtype=dtypes.int32, scalar=True), [], 0)) - lang.ins.append(AssemblyInstruction(Ops.LABEL, None, [], "$loop_"+var.expr)) - elif uop == Ops.ENDLOOP: - if args[1] not in ["global", "local", "global+local"]: - for var in reversed(args[0]): - if not isinstance(var, NumNode): # TODO: why is this coming through? - lang.ins.append(AssemblyInstruction(Ops.ALU, lang.tor[var], [lang.tor[var], 1], BinaryOps.ADD)) - pred = lang.render_alu(BinaryOps.CMPLT, lang.tor[var], var.max+1, dtypes.bool) - lang.ins.append(AssemblyInstruction(Ops.COND_BRANCH, None, [pred], ("$loop_"+var.expr, True))) - elif args[1] == "global+local": - for i, var in enumerate(reversed(args[0])): - lang.ins.append(AssemblyInstruction(Ops.ENDLOOP, None, [lang.tor[var]], (var.max+1, f"gid{i}"))) - elif args[1] == 'local': - for i, var in enumerate(reversed(args[0])): - lang.ins.append(AssemblyInstruction(Ops.ENDLOOP, None, [lang.tor[var]], (var.max+1, f"lid{i}"))) - elif uop == Ops.CAST: - # TODO: we should reconsider outputting CAST in the linearizer. these are needless copies - out = lang.newreg(u, dtype) - for i,sr in enumerate(out.subregs()): - lang.ins.append(AssemblyInstruction(Ops.ALU, sr, [lang.tor[vin[i]]], UnaryOps.NOOP)) - elif uop == Ops.ALU: - out = lang.newreg(u, dtype) if u not in lang.tor else lang.tor[u] - # this is the only thing that can violate SSA - if args in [BinaryOps.CMPLT]: - pred_reg = lang.newreg((u, 'pred'), dtype=dtypes.bool) - lang.ins.append(AssemblyInstruction(Ops.ALU, pred_reg, [lang.tor[x] for x in vin], args)) - lang.ins.append(AssemblyInstruction(Ops.CAST, out, [pred_reg], args)) - elif args == BinaryOps.DIV and lang.no_div: - tmp = lang.newreg((u, "rcp")) - lang.ins.append(AssemblyInstruction(Ops.ALU, tmp, [lang.tor[vin[1]]], UnaryOps.RECIP)) - lang.ins.append(AssemblyInstruction(Ops.ALU, out, [lang.tor[vin[0]], tmp], BinaryOps.MUL)) - elif args == UnaryOps.SIN and lang.sin_is_sin2pi: - tmp = lang.newreg((u, "2pi")) - lang.ins.append(AssemblyInstruction(Ops.ALU, tmp, [lang.tor[vin[0]], 1/(math.pi*2)], BinaryOps.MUL)) - lang.ins.append(AssemblyInstruction(Ops.ALU, out, [tmp], args)) - else: - lang.ins.append(AssemblyInstruction(Ops.ALU, out, [lang.tor[x] for x in vin], args)) - elif uop == Ops.DEFINE_ACC: - reg = lang.newreg(u, dtype=dtype) - lang.ins.append(AssemblyInstruction(Ops.LOAD, reg, [], args)) - elif uop == Ops.SPECIAL: - lang.tor[u] = lang.tor[args] - elif uop == Ops.CONST: - lang.ins.append(AssemblyInstruction(Ops.LOAD, lang.newreg(u, dtype=dtype), [], args)) - elif uop == Ops.LOAD: - idx, treg, off = lang.addr_w_offset(args) - reg = lang.newreg(u, dtype=dtype, scalar=(idx.scalar and (not isinstance(treg, Register) or treg.scalar))) - if args.valid.min == 0: - lang.ins.append(AssemblyInstruction(Ops.LOAD, reg, [], 0)) - if args.valid.max == 1: - pred = args.valid.render(lang.render_ops, lang) - lang.ins.append(AssemblyInstruction(Ops.COND_BRANCH, None, [pred], (f"$skipload_{skipload_branch}", False))) - if args.valid.max == 1: - # NOTE: you can't compute the index in here, because it assumes it's all available later - lang.ins.append(AssemblyInstruction(Ops.LOAD, reg, [idx] + ([treg] if treg is not None else []), (off, 'global' if not args.local else 'shared', args.memory_dtype if args.memory_dtype != dtypes.float else None))) - if args.valid.min == 0 and args.valid.max == 1: - lang.ins.append(AssemblyInstruction(Ops.LABEL, None, [], f"$skipload_{skipload_branch}")) - skipload_branch += 1 - elif uop == Ops.STORE: - if args is None: - lang.ins.append(AssemblyInstruction(Ops.ALU, lang.tor[vin[0]], [lang.tor[vin[1]]], UnaryOps.NOOP)) - else: - idx, treg, off = lang.addr_w_offset(args) - lang.ins.append(AssemblyInstruction(Ops.STORE, None, [idx, lang.tor[vin[0]]] + ([treg] if treg is not None else []), (off, 'global' if not args.local else 'shared', args.memory_dtype if args.memory_dtype != dtypes.float else None))) - - if DEBUG >= 4: - for tins in lang.ins: print(tins) - return global_size, local_size diff --git a/tinygrad/extra/assembly/assembly_arm64.py b/tinygrad/extra/assembly/assembly_arm64.py deleted file mode 100644 index 800f7547..00000000 --- a/tinygrad/extra/assembly/assembly_arm64.py +++ /dev/null @@ -1,177 +0,0 @@ -import struct -from platform import system -from typing import Tuple, Dict, List, Optional -from tinygrad import dtypes -from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps -from tinygrad.codegen.kernel import Ops, UOp -from tinygrad.helpers import CI -from tinygrad.codegen.assembly import uops_to_asmstyle, AssemblyLanguage - -def float_to_hex(x): return "%02X%02X%02X%02X" % tuple(struct.pack("f",x)[::-1]) -def compute_offsets(total): - quotient, remainder = divmod(total, 4096) - return [4096]*quotient + [remainder] if remainder else [4096]*quotient - -#NOTE: Darwin needs names to start with a "_" -def get_name(name): return ('_' if system() == 'Darwin' else '') + name - -class ARM64Language(AssemblyLanguage): pass - -def specialize_to_arm64(fn_nm, asm): - var_size = 16 - prev_uop:Optional[Ops] = None - ins = [] - x_regs = ['x' + str(i) for i in reversed(range(12))] - s_regs = ['s' + str(i) for i in reversed(range(3,32)) if i <= 7 or i >= 16] - type_to_reg = {dtypes.double: "d", dtypes.half: 'h', dtypes.float32: 's', dtypes.bool: 'w', dtypes.int8:'w', dtypes.int32: 'w', dtypes.int64: 'x', dtypes.uint8:'w', dtypes.uint32: 'w', dtypes.uint64: 'x'} - alu = {BinaryOps.ADD: "add", BinaryOps.SUB: "sub", BinaryOps.MUL: "mul", BinaryOps.DIV: "div", BinaryOps.MAX: "max", - BinaryOps.MOD: "", BinaryOps.CMPLT: "subs", - UnaryOps.NOOP: "mov", UnaryOps.NEG: "neg", - UnaryOps.SIN:'bl ' + get_name('sinf'), UnaryOps.LOG2: 'bl ' + get_name("log2f"), UnaryOps.EXP2: 'bl ' + get_name("exp2f"), UnaryOps.SQRT: 'bl ' + get_name("sqrtf"), - TernaryOps.MULACC: "madd", TernaryOps.WHERE: "fcsel"} - - def mov_imm(value, reg): - # Manually move value into reg if value can't fit - if value.__class__ is not float and abs(value) > abs(65535): - ins.append(f"movz w15, #{value & 0xffff}") - ins.append(f"movk w15, #{(value >> 16) & 0xffff}, lsl #16") - ins.append(f"sxtw {reg}, w15") - elif reg[0] == 's': - ins.append(f"movz x15, 0x{float_to_hex(value)[4:]}") - ins.append(f"movk x15, 0x{float_to_hex(value)[:4]}, lsl #16") - ins.append("str x15, [sp, 16]") - ins.append(f"ldr {reg}, [sp, 16]") - else: - ins.append(f"mov {reg}, #{value}") - - # Get variables intervals - live_range:Dict[str, List[int]] = {} - for i, (uop, out, vin, arg) in enumerate(asm): - for var in ([v for v in [out] + vin if v is not None and v.__class__ is not int]): - live_range[var.nm] = [i,i] if var.nm not in live_range else [live_range[var.nm][0], i] - - mem_vars:Dict[str, int] = {} - rtor:Dict[str, str] = {} - def allocate_regs(mvars): - nonlocal var_size - for v in [v for v in mvars if v is not None and v.__class__ is not int and v.nm not in rtor]: - available_regs = s_regs if dtypes.is_float(v[1]) else x_regs - #NOTE: Very simple spill, everything that don't fit in regs goes to mem - if not available_regs: - # ARM needs the stack 16-byte aligned - var_size += 16 - available_regs.append('s0' if dtypes.is_float(out[1]) else 'x12') - mem_vars[v.nm] = var_size - rtor[v.nm] = available_regs.pop() - - temp_floats = ['s0', 's1', 's2'] - temp_ints = ['x12', 'x13', 'x16'] - for i, (uop, out, vin, arg) in enumerate(asm): - # Clear regs out of interval - for var, reg in list(rtor.items()): - available_regs = s_regs if reg[0] == 's' else x_regs - if var[1] not in 'B' and var not in mem_vars and i > live_range[var][1]: - available_regs.append(rtor.pop(var)) - # Assign a registers to the variables using live ranges. - allocate_regs([out] + vin) - # Assign temp regs to vin and load them before direct use - for i, v in enumerate([v for v in vin if v.__class__ is not int and v.nm in mem_vars]): - rtor[v.nm] = temp_floats[i] if dtypes.is_float(v[1]) else temp_ints[i] - # ARM64 addressing constraints https://devblogs.microsoft.com/oldnewthing/20220728-00/?p=106912 - ins.append(f"mov x15, {mem_vars[v.nm]}") - ins.append(f"ldr {rtor[v.nm]}, [sp, x15]") - - if uop == Ops.SPECIAL: - if arg.startswith('data'): - # data 8 to n into the stack - if int(arg[4:]) >= 8: - ins.append(f"ldr x15, [x17, #{(int(arg[4:]) - 8) * 8}]") - ins.append(f"mov {rtor[out.nm]}, x15") - else: - ins.append(f"mov {rtor[out.nm]}, #0") - ins.append(f"loop_{arg}:") - elif uop == Ops.CAST: - if arg == BinaryOps.CMPLT: - if rtor[out.nm][0] == 's': - mov_imm(0.0, 's0') - mov_imm(1.0, 's1') - ins.append(f"fcsel {rtor[out.nm]}, s1, s0, lt") - if rtor[out.nm][0] == 'x': - mov_imm(0, 'x14') - mov_imm(1, 'x15') - ins.append(f"csel {rtor[out.nm]}, x15, x14, lt") - else: - ins.append(f"sxtw {rtor[out.nm]}, w{rtor[vin[0].nm][1:]}") - elif uop == Ops.ALU: - if len(vin)==2 and vin[1].__class__ is int: mov_imm(vin[1], 'x15') - if arg == BinaryOps.MUL and out.dtype == dtypes.bool: - ins.append(f"ands {','.join('x15' if v.__class__ is int else rtor[v.nm] for v in [out] + vin)}") - elif arg == TernaryOps.WHERE: - ins.append(f"fcmp {rtor[vin[0].nm]}, #0.0" if rtor[vin[0].nm][0] == 's' else f"cmp {rtor[vin[0].nm]}, #0") - ins.append(f"{alu[arg]} {rtor[out.nm]}, {rtor[vin[1].nm]}, {rtor[vin[2].nm]}, ne") - elif arg in [UnaryOps.LOG2, UnaryOps.SIN, UnaryOps.EXP2, UnaryOps.SQRT]: - #NOTE: Not a real instruction, use to emulate a ext call in unicorn - if CI: ins.append(f"{alu[arg]} {rtor[out.nm]} {rtor[vin[0].nm]}") - else: - save_regs = [k for k in rtor.keys() if k != out.nm and k not in mem_vars] - ins.append(f"sub sp, sp, #{(len(save_regs))*16}") - # Save the registers before they are cleared by func call - for i,k in enumerate(save_regs,1): - ins.append(f"str {rtor[k]}, [sp, #{16*i}]") - ins.append("stp x29, x30, [sp, #0]!") - ins.append("mov x29, sp") - ins.append(f"fmov s0, {rtor[vin[0].nm]}") - ins.append(alu[arg]) - ins.append(f"fmov {rtor[out.nm]}, s0") - ins.append("mov sp, x29") - ins.append("ldp x29, x30, [sp], #0") - for i,k in enumerate(save_regs,1): - ins.append(f"ldr {rtor[k]}, [sp, #{16*i}]") - ins.append(f"add sp, sp, #{len(save_regs)*16}") - elif arg == BinaryOps.CMPLT: - ins.append(f"{alu[arg]} {','.join('x15' if v.__class__ is int else rtor[v.nm] for v in [out] + vin)}" if not dtypes.is_float(vin[0][1]) else f"fcmp {rtor[vin[0].nm]}, {rtor[vin[1].nm]}") - elif arg == BinaryOps.MOD: - rhs = 'x15' if vin[1].__class__ is int else rtor[vin[1].nm] - ins.append(f"udiv x14, {rtor[vin[0].nm]}, {rhs}") - ins.append(f"msub {rtor[out.nm]}, x14, {rhs}, {rtor[vin[0].nm]}") - else: - ins.append(f"{'f' if dtypes.is_float(vin[0][1]) else 's' if arg == BinaryOps.DIV else ''}{alu[arg]} {', '.join('x15' if v.__class__ is int else rtor[v.nm] for v in [out] + vin)}") - elif uop == Ops.LOAD: - if arg.__class__ in (int, float): - mov_imm(arg, rtor[out.nm]) - else: - #NOTE: if need casting load var in s/h0 or x/w12 temp regs - reg_in = type_to_reg[arg[2]] + ('0' if dtypes.is_float(arg[2]) else '12') if arg[2] is not None else rtor[out.nm] - mov_imm(arg[0], "x15") - ins.append(f"add x15, {rtor[vin[0].nm]}, x15") - ins.append(f"ldr{'sb' if arg[2] is not None and arg[2] in (dtypes.int8, dtypes.uint8, dtypes.bool) else ''} {reg_in}, [x15]") - if arg[2] is not None: ins.append(f"{'fcvt' if arg[2] in [dtypes.half, dtypes.double] else 'scvtf'} {rtor[out.nm]}, {reg_in}") - elif uop == Ops.STORE: - #NOTE: if need casting load var in s/h0 or x/w12 temp regs - reg_out = (type_to_reg[arg[2]] + ('0' if dtypes.is_float(arg[2]) else '12') if arg[2] is not None else rtor[vin[1].nm]) - if arg[2] is not None: ins.append(f"fcvt{'zs' if arg[2] not in [dtypes.half, dtypes.double] else '' } {reg_out}, {rtor[vin[1].nm]}") - ins.append(f"mov x15, #{arg[0]}") - ins.append(f"str {reg_out}, [{rtor[vin[0].nm]}, x15, lsl #0]") - elif uop == Ops.COND_BRANCH: - #TODO: this is a hack it shouldn't always be a cmp before a cond branch? - if prev_uop == Ops.LOAD: - ins.append(f"cmp {rtor[vin[0].nm]}, #0") - ins.append(f"b.{'lt' if arg[1] else 'ge'} {arg[0][1:]}") - elif uop == Ops.LABEL: - ins.append(f"{arg[1:]}:") - elif uop == Ops.ENDLOOP: - mov_imm(arg[0], "x15") - ins.append(f"add {rtor[vin[0].nm]}, {rtor[vin[0].nm]}, #1") - ins.append(f"cmp {rtor[vin[0].nm]}, x15") - ins.append(f"b.lt loop_{arg[1]}") - prev_uop = uop - # store regs into memory if needed - if out is not None and out.nm in mem_vars: - ins.append(f"mov x15, {mem_vars[out.nm]}") - ins.append(f"str {rtor[out.nm]}, [sp, x15]") - return "\n".join([f"//varsize {var_size}",".arch armv8-a",".text", f".global {get_name(fn_nm)}",".p2align 2", f"{get_name(fn_nm)}:", "mov x17, sp"] + [f"sub sp, sp, #{offset}" for offset in compute_offsets(var_size)]+ ins + [f"add sp, sp, #{offset}" for offset in compute_offsets(var_size)] +["ret", "\n"]) - -def uops_to_arm64_asm(fn_nm:str, uops:List[UOp]) -> Tuple[str, List[int], List[int], bool]: - lang = ARM64Language() - global_size, local_size = uops_to_asmstyle(lang, fn_nm, uops) - return specialize_to_arm64(fn_nm, lang.ins), global_size[::-1], local_size[::-1], True \ No newline at end of file diff --git a/tinygrad/extra/assembly/assembly_ptx.py b/tinygrad/extra/assembly/assembly_ptx.py deleted file mode 100644 index f3fce81d..00000000 --- a/tinygrad/extra/assembly/assembly_ptx.py +++ /dev/null @@ -1,105 +0,0 @@ -from typing import List -import struct -from tinygrad.codegen.assembly import uops_to_asmstyle, AssemblyLanguage -from tinygrad.codegen.kernel import Ops, UOp -from tinygrad import dtypes -from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps -from tinygrad.runtime.ops_cuda import arch - -dtype_to_nvtype = {dtypes.float32: "f32", dtypes.float16: "f16", dtypes.int64: "s64", dtypes.int32: "s32", dtypes.int8: "s8", dtypes.bool: "pred", dtypes.uint64: "u64", dtypes.uint32: "u32", dtypes.uint16: "u16", dtypes.uint8: "u8", "bits16": "b16", dtypes.float64: "f64"} -def float_to_hex(x): return "%02X%02X%02X%02X" % tuple(struct.pack("f",x)[::-1]) - -def ptx_needs_cast(dest_dtype, src_dtype): return dtypes.is_float(dest_dtype) and dtypes.is_int(src_dtype) or dtypes.is_int(dest_dtype) and dtypes.is_float(src_dtype) or (dtypes.is_float(src_dtype) and dtypes.is_float(dest_dtype) and dest_dtype.itemsize != src_dtype.itemsize) - -def render_cast(ins, inp, out): - if inp.dtype == dtypes.bool and (dtypes.is_float(out.dtype) or dtypes.is_int(out.dtype)): - ins.append(f"selp.{dtype_to_nvtype[out.dtype]} {out}, {'0f3F800000, 0f00000000' if dtypes.is_float(out.dtype) else '1, 0'}, {inp};") - elif out.dtype == dtypes.bool: - if inp.dtype == dtypes.bool: - ins.append(f"mov.pred {out}, {inp};") - else: - ins.append(f"setp.ne.{dtype_to_nvtype[inp.dtype]} {out}, {'0f00000000' if dtypes.is_float(inp.dtype) else '0'}, {inp};") - else: - round_mod = ".rzi" if dtypes.is_int(out.dtype) and dtypes.is_float(inp.dtype) else '.rz' if dtypes.is_float(out.dtype) and (dtypes.is_int(inp.dtype) or dtypes.is_float(inp.dtype) and inp.dtype.itemsize > out.dtype.itemsize) else '' - ins.append(f"cvt{round_mod}.{dtype_to_nvtype[out.dtype]}.{dtype_to_nvtype[inp.dtype]} {out}, {inp};") - -# https://docs.nvidia.com/cuda/parallel-thread-execution/# - -class PTXLanguage(AssemblyLanguage): - supports_constant_folding: bool = True - -def specialize_to_ptx(lang, function_name): - param_cnt = 0 - ins = [] - alu = {BinaryOps.ADD: "add", BinaryOps.SUB: "sub", BinaryOps.MUL: "mul", BinaryOps.DIV: "div", BinaryOps.MAX: "max", - BinaryOps.MOD: "rem", BinaryOps.CMPLT: "setp.lt", UnaryOps.SQRT: "sqrt.approx", - UnaryOps.NOOP: "mov", UnaryOps.NEG: "neg", - UnaryOps.SIN: "sin.approx", UnaryOps.LOG2: "lg2.approx", UnaryOps.EXP2: "ex2.approx.ftz", - TernaryOps.MULACC: "fma.rn", TernaryOps.WHERE: "selp"} - for uop, out, vin, arg in lang.ins: - if uop == Ops.ENDLOOP: - ins.append("bar.sync 0;") - elif uop == Ops.DEFINE_LOCAL: - ins.append(f".shared .align 4 .b8 {arg[0]}[{arg[1]*4}];") - elif uop == Ops.SPECIAL: - if arg.startswith('data'): - param_cnt += 1 - ins.append(f"ld.param.u64 {out}, [{arg}];") - # TODO: we sometimes want this to be local, nvcc converts to global most of the time, not sure when we would need to? - # ins.append(f"cvta.to.global.u64 {out}, {out};") - elif arg.startswith('gid'): - ins.append(f"mov.u32 {out}, %ctaid.{'xyz'[int(arg[3:])]};") - elif arg.startswith('lid'): - ins.append(f"mov.u32 {out}, %tid.{'xyz'[int(arg[3:])]};") - elif uop == Ops.ALU: - if arg == BinaryOps.MUL and out.dtype == dtypes.bool: - ins.append(f"and.pred {out}, {', '.join(str(x) for x in vin)};") - else: - otype = vin[0].dtype if arg in [BinaryOps.CMPLT] else out.dtype - if arg == TernaryOps.WHERE: - if vin[0].dtype == dtypes.bool: - reg = vin[0] - else: - reg = lang.newreg((vin[0], 'bool'), dtypes.bool) - ins.append(f"setp.ne.{dtype_to_nvtype[vin[0].dtype]} {reg}, {'0f00000000' if dtypes.is_float(vin[0].dtype) else '0'}, {vin[0]};") - vin = vin[1:] + [reg] - ins.append(f"{alu[arg]}{'.lo' if arg == BinaryOps.MUL and out.dtype != dtypes.float32 else ''}{'.rn' if arg == BinaryOps.DIV and out.dtype == dtypes.float32 else ''}.{dtype_to_nvtype[otype]} {out}, {', '.join(str(x) for x in vin)};") - elif uop == Ops.LOAD: - if arg.__class__ in (int, float): - ins.append(f"mov.{dtype_to_nvtype[out.dtype]} {out}, {'0f'+float_to_hex(arg) if dtypes.is_float(out.dtype) else int(arg)};") - elif arg[2] is not None and (arg[2] == dtypes.bool or arg[2] != out.dtype): - dt = ('u16', dtypes.uint16) if arg[2] == dtypes.bool == out.dtype else ('u8', dtypes.uint8) if arg[2] == dtypes.bool else ('b16', dtypes.float16) if arg[2] == dtypes.half else (dtype_to_nvtype[arg[2]], arg[2]) - reg = lang.newreg((out, dt[0]), dtype=dt[1]) - ins.append(f"ld.{arg[1]}.{dt[0]} {reg}, [{vin[0]}{f'+{arg[0]}' if arg[0] is not None else ''}];") - render_cast(ins, reg, out) - else: - ins.append(f"ld.{arg[1]}.{dtype_to_nvtype[dtypes.float if arg[2] is None else arg[2]]} {out}, [{vin[0]}{f'+{arg[0]}' if arg[0] is not None else ''}];") - elif uop == Ops.STORE: - if ptx_needs_cast(dtypes.float if arg[2] is None else arg[2], vin[1].dtype) or arg[2] == dtypes.bool: - if arg[2] == dtypes.bool != vin[1].dtype: - prereg = lang.newreg((vin[1],'bool'), dtype=dtypes.bool) - render_cast(ins, vin[1], prereg) - else: prereg = vin[1] - reg = lang.newreg((prereg, dtypes.uint16 if arg[2] == dtypes.bool else arg[2]), dtype=dtypes.uint16 if arg[2] == dtypes.bool else dtypes.float if arg[2] is None else arg[2]) - render_cast(ins, prereg, reg) - ins.append(f"st.{arg[1]}.{dtype_to_nvtype['bits16' if arg[2] == dtypes.float16 else dtypes.uint8 if arg[2] == dtypes.bool else dtypes.float if arg[2] is None else arg[2]]} [{vin[0]}{f'+{arg[0]}' if arg[0] is not None else ''}], {reg};") - else: - ins.append(f"st.{arg[1]}.{dtype_to_nvtype[dtypes.float if arg[2] is None else arg[2]]} [{vin[0]}{f'+{arg[0]}' if arg[0] is not None else ''}], {vin[1]};") - elif uop == Ops.CAST: - render_cast(ins, vin[0], out) - elif uop == Ops.LABEL: - ins.append(f"{arg}:") - elif uop == Ops.COND_BRANCH: - ins.append(f"@{'!' if not arg[1] else ''}{vin[0]} bra {arg[0]};") - - ins_prefix = [".version 7.8", ".target " + arch(), ".address_size 64", - f".visible .entry {function_name}({', '.join(f'.param .u64 data{i}' for i in range(param_cnt))}) {{"] - for arg in [(dtype, lang.type_to_letter(dtype), c) for dtype,c in lang.cnts.items()]: ins_prefix.append(f".reg .{dtype_to_nvtype[arg[0][0]]} %{arg[1]}<{arg[2]}>;",) - ins = ins_prefix + ins - ins += ["ret;", "}"] - return '\n'.join(ins) - -def uops_to_ptx_asm(function_name:str, uops:List[UOp]): - lang = PTXLanguage() - global_size, local_size = uops_to_asmstyle(lang, function_name, uops) - return specialize_to_ptx(lang, function_name), global_size[::-1], local_size[::-1], True diff --git a/tinygrad/extra/assembly/assembly_rdna.py b/tinygrad/extra/assembly/assembly_rdna.py deleted file mode 100644 index 6eae18b4..00000000 --- a/tinygrad/extra/assembly/assembly_rdna.py +++ /dev/null @@ -1,203 +0,0 @@ -import yaml -from typing import Tuple, Set, Dict -from tinygrad import dtypes -from tinygrad.codegen.assembly import AssemblyCodegen, Register -from tinygrad.codegen.kernel import Ops -from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps -from tinygrad.runtime.ops_gpu import ROCM_LLVM_PATH - -# ugh, is this really needed? -from extra.helpers import enable_early_exec -early_exec = enable_early_exec() - -boilerplate_start = """ -.global _start -_start: -.rodata -.align 0x10 -.global code.kd -.type code.kd,STT_OBJECT -.amdhsa_kernel code""" - -code_start = """.end_amdhsa_kernel -.text -code: -""" - -# https://github.com/RadeonOpenCompute/ROCm_Documentation/blob/master/ROCm_Compiler_SDK/ROCm-Codeobj-format.rst -# https://github.com/ROCm-Developer-Tools/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md#initial-kernel-register-state -# RDNA3 is actually a SIMD machine! -class RDNACodegen(AssemblyCodegen): - supports_float4: bool = True - supports_float4_alu: bool = True - supports_load3: bool = True - sin_is_sin2pi: bool = True - no_div: bool = True - - def specialize(self, asm) -> Tuple[str, str]: - args = [] - for i,b in enumerate(self.bufs): args.append({'.address_space': 'global', '.name': f'buf_{i}', '.offset': i*8, '.size': 8, '.type_name': b.dtype.name+"*", '.value_kind': 'global_buffer'}) - ins = [] - - v_cnt = 3 # v[0:2] is local_xyz - s_cnt = 5 # s[0:1] is the address, s[2:4] is global_xyz - - dtype_to_rdnatype = {dtypes.float32: "f32", dtypes.int64: "i64", dtypes.int32: "i32", dtypes.uint64: "u64", dtypes.bool: "i32"} - alu = {BinaryOps.ADD: "add", BinaryOps.SUB: "sub", BinaryOps.MUL: "mul", TernaryOps.MULACC: "fma", - BinaryOps.MAX: "max", UnaryOps.RECIP: "rcp", - UnaryOps.NOOP: "mov", UnaryOps.SIN: "sin", UnaryOps.LOG2: "log", UnaryOps.EXP2: "exp", - BinaryOps.CMPLT: "cmp_lt"} - - pend_regs:Set[Register] = set() - rtor:Dict[Register, str] = {} - def reg_in(x): - nonlocal pend_regs - #print("reg_in", x, rtor[x], pend_regs) - if x in pend_regs: - #print("clear") - ins.append('s_waitcnt lgkmcnt(0), vmcnt(0)') - pend_regs.clear() - return rtor[x] - def reg_out(x): - return rtor[x] - for uop, out, vin, arg in asm: - if uop == Ops.DEFINE_REGISTER: - if arg[0][0] in [dtypes.uint32, dtypes.uint64, dtypes.int64, dtypes.int32, dtypes.float32, dtypes.float.vec(4)]: - for i in range(arg[2]): - # TODO: Re-use gaps created by this to avoid wasting registers - align = int(arg[0][0].itemsize / 4) - if arg[0][1]: - s_cnt += s_cnt % align - reg_name = f"s[{s_cnt}:{s_cnt + align - 1}]" if align > 1 else f"s{s_cnt}" - s_cnt += align - else: - v_cnt += v_cnt % align - reg_name = f"v[{v_cnt}:{v_cnt + align - 1}]" if align > 1 else f"v{v_cnt}" - v_cnt += align - rtor[Register(f"%{arg[1]}{i}", *arg[0])] = reg_name - - if arg[0][0] == dtypes.float.vec(4): - for off in range(4): - reg_name = f"s{s_cnt-align+off}" if arg[0][1] else f"v{v_cnt-align+off}" - rtor[Register(f"%{arg[1]}{i}", dtypes.float, False, off=off)] = reg_name - elif arg[0][0] == dtypes.bool: - for i in range(arg[2]): - reg_name = "scc" if arg[0][1] else "vcc_lo" # `_lo` suffix since we're running wavefront_size=32 - rtor[Register(f"%{arg[1]}{i}", *arg[0])] = reg_name - else: - raise NotImplementedError("DEFINE_REGISTER not implemented for arg: ", arg) - elif uop == Ops.SPECIAL: - if arg.startswith('buf'): - i = int(arg[3:]) - ins.append(f's_load_b64 {reg_out(out)}, s[0:1], {i*8}') - pend_regs.add(out) - for r in out.subregs(): pend_regs.add(r) - elif arg.startswith('gid'): - ins.append(f'v_mov_b32 {reg_out(out)}, s{2+int(arg[3])}') - # the docs lied, this is actually y - if int(arg[3]) == 2: ins.append("v_bfe_u32 v2, v0, 20, 10") # untested - if int(arg[3]) == 1: ins.append("v_bfe_u32 v1, v0, 10, 10") - elif int(arg[3]) == 0: ins.append("v_and_b32_e32 v0, 0x3ff, v0") - # get local size - offset = len(args)*8 - args.append({".offset": offset, ".value_kind": f"hidden_group_size_{'xyz'[int(arg[3])]}", ".size": 8}) - ins.append(f's_load_b32 s{2+int(arg[3])}, s[0:1], {offset}') - ins.append('s_waitcnt vmcnt(0) lgkmcnt(0)') - pend_regs.clear() - ins.append(f'v_mul_i32_i24 {reg_out(out)}, {reg_out(out)}, s{2+int(arg[3])}') - ins.append(f'v_add_nc_u32 {reg_out(out)}, v{int(arg[3])}, {reg_out(out)}') - elif uop == Ops.CONST: - if arg == float('inf'): arg = "0x7f800000" - elif arg == float('-inf'): arg = "0xff800000" - if out.dtype == dtypes.float.vec(4): - for off in range(4): - ins.append(f"{'s_' if out.scalar else 'v_'}mov_b32 {reg_out(Register(out.nm, dtypes.float, False, off=off))}, {arg}") - else: - ins.append(f"{'s_' if out.scalar else 'v_'}mov_b32 {reg_out(out)}, {arg}") - elif uop == Ops.ALU: - if arg in [BinaryOps.CMPLT]: - ins.append(f"{'s' if out.scalar else 'v'}_{alu[arg]}_{dtype_to_rdnatype[out.dtype]} {', '.join(reg_in(x) if x.__class__ is Register else str(x) for x in vin)}") - else: - alu_arg = alu[arg] - if arg == TernaryOps.MULACC and out == vin[2]: - alu_arg = "fmac" - vin = vin[0:2] - if out.dtype == dtypes.float.vec(4): - for rr in zip(*[x.subregs() if x.dtype == dtypes.float.vec(4) else [x,x,x,x] for x in [out]+vin]): - ins.append(f"{'s_' if rr[0].scalar else 'v_'}{alu_arg}_{dtype_to_rdnatype[rr[0].dtype]} {reg_out(rr[0])}, {', '.join(reg_in(x) if x.__class__ is Register else str(x) for x in rr[1:])}") - else: - ins.append(f"{'s_' if out.scalar else 'v_'}{alu_arg}_{dtype_to_rdnatype[out.dtype] if arg != UnaryOps.NOOP else 'b32'}{'_i24' if arg == BinaryOps.MUL and out.dtype != dtypes.float32 and not out.scalar else ''} {reg_out(out)}, {', '.join(reg_in(x) if x.__class__ is Register else str(x) for x in vin)}") - elif uop == Ops.LOAD: - if out.scalar: - # swap arg order - ins.append(f's_load_b32 {reg_out(out)}, {reg_in(vin[0])}, {reg_in(vin[1])} offset:{arg[0]}') - else: - ins.append(f'global_load_{"b128" if out.dtype == dtypes.float.vec(4) else "b32"} {reg_out(out)}, {reg_in(vin[1])}, {reg_in(vin[0])} offset:{arg[0]}') - pend_regs.add(out) - for r in out.subregs(): pend_regs.add(r) - elif uop == Ops.STORE: - ins.append(f'global_store_{"b128" if vin[1].dtype == dtypes.float.vec(4) else "b32"} {reg_in(vin[2])}, {reg_in(vin[1])}, {reg_in(vin[0])} offset:{arg[0]}') - elif uop == Ops.LABEL: - ins.append(f"{arg}:") - elif uop == Ops.COND_BRANCH: - ins.append(f"s_cbranch_scc{'1' if arg[1] else '0'} {arg[0]}") - elif uop == Ops.CAST: - if vin[0].dtype == dtypes.bool: - if out.dtype == dtypes.float32: - ins.append(f"v_cndmask_b32 {reg_out(out)}, 0.0, 1.0, {reg_in(vin[0])}") - else: - raise NotImplementedError(f"cast {vin[0].dtype} -> {out.dtype}") - else: - raise NotImplementedError(uop) - - ins += ['s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)', 's_endpgm', 's_code_end'] - - # dual alu group - seen = set() - new_ins = [] - for i,tins in enumerate(ins): - if tins in seen: continue - if tins.startswith("v_fmac_f32"): - for gins in reversed(ins[i+1:]): - if gins in seen: continue - if gins.startswith("v_fmac_f32"): - r0 = [int(x[1:].strip(',')) for x in tins.split(" ")[1:]] - r1 = [int(x[1:].strip(',')) for x in gins.split(" ")[1:]] - if r0[0]%2 == r1[0]%2: continue - if r0[1]%2 == r1[1]%2: continue - if r0[2]%2 == r1[2]%2: continue - new_ins.append(tins.replace("v_", "v_dual_")+" :: " + gins.replace("v_", "v_dual_")) - seen.add(tins) - seen.add(gins) - break - if tins not in seen: - new_ins.append(tins) - ins = new_ins - - return 'code', self.assemble(args, ins, v_cnt, s_cnt) - - def assemble(self, args, ins, v_cnt, s_cnt): - kernel_desc = {'.amdhsa_group_segment_fixed_size': 0, '.amdhsa_private_segment_fixed_size': 0, '.amdhsa_kernarg_size': 0, - '.amdhsa_next_free_vgpr': v_cnt, # this matters! - '.amdhsa_reserve_vcc': 0, '.amdhsa_reserve_xnack_mask': 0, - '.amdhsa_next_free_sgpr': s_cnt, - '.amdhsa_float_round_mode_32': 0, '.amdhsa_float_round_mode_16_64': 0, '.amdhsa_float_denorm_mode_32': 3, '.amdhsa_float_denorm_mode_16_64': 3, '.amdhsa_dx10_clamp': 1, '.amdhsa_ieee_mode': 1, - '.amdhsa_fp16_overflow': 0, '.amdhsa_workgroup_processor_mode': 1, '.amdhsa_memory_ordered': 1, '.amdhsa_forward_progress': 0, '.amdhsa_enable_private_segment': 0, - '.amdhsa_system_sgpr_workgroup_id_x': 1, '.amdhsa_system_sgpr_workgroup_id_y': 1, '.amdhsa_system_sgpr_workgroup_id_z': 1, - '.amdhsa_system_sgpr_workgroup_info': 0, '.amdhsa_system_vgpr_workitem_id': 2, # is amdhsa_system_vgpr_workitem_id real? - '.amdhsa_exception_fp_ieee_invalid_op': 0, '.amdhsa_exception_fp_denorm_src': 0, '.amdhsa_exception_fp_ieee_div_zero': 0, '.amdhsa_exception_fp_ieee_overflow': 0, '.amdhsa_exception_fp_ieee_underflow': 0, - '.amdhsa_exception_fp_ieee_inexact': 0, '.amdhsa_exception_int_div_zero': 0, '.amdhsa_user_sgpr_dispatch_ptr': 0, '.amdhsa_user_sgpr_queue_ptr': 0, '.amdhsa_user_sgpr_kernarg_segment_ptr': 1, - '.amdhsa_user_sgpr_dispatch_id': 0, '.amdhsa_user_sgpr_private_segment_size': 0, '.amdhsa_wavefront_size32': 1, '.amdhsa_uses_dynamic_stack': 0} - - metadata = {'amdhsa.kernels': [{'.args': args, - '.group_segment_fixed_size': 0, '.kernarg_segment_align': 8, '.kernarg_segment_size': args[-1][".offset"] + args[-1][".size"], - '.language': 'OpenCL C', '.language_version': [1, 2], '.max_flat_workgroup_size': 256, - '.name': 'code', '.private_segment_fixed_size': 0, '.sgpr_count': s_cnt, '.sgpr_spill_count': 0, - '.symbol': 'code.kd', '.uses_dynamic_stack': False, '.vgpr_count': v_cnt, '.vgpr_spill_count': 0, - '.wavefront_size': 32}], - 'amdhsa.target': 'amdgcn-amd-amdhsa--gfx1100', 'amdhsa.version': [1, 2]} - - code = boilerplate_start + "\n" + '\n'.join("%s %d" % x for x in kernel_desc.items()) + "\n" + code_start + '\n'.join(ins) + "\n.amdgpu_metadata\n" + yaml.dump(metadata) + ".end_amdgpu_metadata" - obj = early_exec(([ROCM_LLVM_PATH / "llvm-mc", '--arch=amdgcn', '--mcpu=gfx1100', '--triple=amdgcn-amd-amdhsa', '--filetype=obj', '-'], code.encode("utf-8"))) - asm = early_exec(([ROCM_LLVM_PATH / "ld.lld", "/dev/stdin", "-o", "/dev/stdout", "--pie"], obj)) - return asm diff --git a/tinygrad/extra/assembly/ptx/test.py b/tinygrad/extra/assembly/ptx/test.py deleted file mode 100644 index f30348b8..00000000 --- a/tinygrad/extra/assembly/ptx/test.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -import numpy as np -from tinygrad.runtime.ops_cuda import CUDAProgram, RawCUDABuffer - -if __name__ == "__main__": - test = RawCUDABuffer.fromCPU(np.zeros(10, np.float32)) - prg = CUDAProgram("test", """ - .version 7.8 - .target sm_86 - .address_size 64 - .visible .entry test(.param .u64 x) { - .reg .b32 %r<2>; - .reg .b64 %rd<3>; - - ld.param.u64 %rd1, [x]; - cvta.to.global.u64 %rd2, %rd1; - mov.u32 %r1, 0x40000000; // 2.0 in float - st.global.u32 [%rd2], %r1; - ret; - }""", binary=True) - prg([1], [1], test) - print(test.toCPU()) - diff --git a/tinygrad/extra/assembly/rocm/.gitignore b/tinygrad/extra/assembly/rocm/.gitignore deleted file mode 100644 index 5b7b00aa..00000000 --- a/tinygrad/extra/assembly/rocm/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.deb -build -src -sniffer/sniff.so diff --git a/tinygrad/extra/assembly/rocm/NOTES b/tinygrad/extra/assembly/rocm/NOTES deleted file mode 100644 index e86a63c7..00000000 --- a/tinygrad/extra/assembly/rocm/NOTES +++ /dev/null @@ -1,20 +0,0 @@ -Built ROCT-Thunk-Interface (hsakmt) - hsakmt-roct-dev_5.4.4.99999-local_amd64.deb - note: installs to /opt/rocm -Built ROCm-Device-Libs - Works with ROCM_PATH=/home/tiny/build/ROCm-Device-Libs/build/dist - rocm-device-libs_1.0.0.99999-local_amd64.deb -Built ROCm-CompilerSupport (amd_comgr) - no deb, sudo make install to /usr/local -Built ROCR-Runtime - hsa-rocr_1.8.0-local_amd64.deb - hsa-rocr-dev_1.8.0-local_amd64.deb -Built ROCm-OpenCL-Runtime - rocm-ocl-icd_2.0.0-local_amd64.deb - ISSUE: these depend on "comgr" - rocm-opencl_2.0.0-local_amd64.deb - rocm-opencl-dev_2.0.0-local_amd64.deb - Did sudo make install - - - diff --git a/tinygrad/extra/assembly/rocm/kernel_crashes/dump b/tinygrad/extra/assembly/rocm/kernel_crashes/dump deleted file mode 100644 index cc09d4de..00000000 --- a/tinygrad/extra/assembly/rocm/kernel_crashes/dump +++ /dev/null @@ -1,41 +0,0 @@ -# run two "rocm-bandwidth-test" in a loop -# amdgpu-6.0.5-1581431.20.04 -# fixed in kernel 6.2.14 - -[ 72.153646] RIP: 0010:pm_send_runlist+0x4a/0x630 [amdgpu] -[ 72.153815] Code: 30 65 48 8b 04 25 28 00 00 00 48 89 45 d0 31 c0 80 fb 01 0f 87 aa 9d 49 00 83 e3 01 0f 85 1c 05 00 00 49 8b 3f b8 01 00 00 00 <48> 8b 97 30 01 00 00 44 8b b7 6c 01 00 00 8b 9f 70 01 00 00 8b 8a -[ 72.153900] RSP: 0018:ffffb48445c03c30 EFLAGS: 00010246 -[ 72.153928] RAX: 0000000000000001 RBX: 0000000000000000 RCX: 0000000000000000 -[ 72.153962] RDX: 000000000000007b RSI: ffff9395e1562558 RDI: 0000000000000000 -[ 72.153996] RBP: ffffb48445c03cb8 R08: 0000000000000000 R09: 0000000000000001 -[ 72.154030] R10: ffff9395c900d840 R11: 0000000000000000 R12: 0000000000000000 -[ 72.154065] R13: ffff9395c9e00400 R14: 0000000000000001 R15: ffff9395e15624e0 -[ 72.154099] FS: 00007f345c6463c0(0000) GS:ffff93a4aee80000(0000) knlGS:0000000000000000 -[ 72.154137] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 -[ 72.154165] CR2: 0000000000000130 CR3: 0000000112840000 CR4: 0000000000750ee0 -[ 72.154201] PKRU: 55555554 -[ 72.154215] Call Trace: -[ 72.154230] -[ 72.154244] map_queues_cpsch+0x75/0xc0 [amdgpu] -[ 72.154365] debug_map_and_unlock+0x51/0x90 [amdgpu] -[ 72.154480] debug_refresh_runlist+0x1f/0x30 [amdgpu] -[ 72.154591] kfd_dbg_runtime_disable+0x13c/0x240 [amdgpu] -[ 72.154705] kfd_ioctl_dbg_set_debug_trap+0x69d/0x8b0 [amdgpu] -[ 72.154820] kfd_ioctl+0x24a/0x5b0 [amdgpu] -[ 72.154925] ? kfd_ioctl_create_queue+0x770/0x770 [amdgpu] -[ 72.155035] ? syscall_exit_to_user_mode+0x27/0x50 -[ 72.155061] ? exit_to_user_mode_prepare+0x3d/0x1c0 -[ 72.155088] __x64_sys_ioctl+0x95/0xd0 -[ 72.155109] do_syscall_64+0x5c/0xc0 -[ 72.155128] ? syscall_exit_to_user_mode+0x27/0x50 -[ 72.155151] ? do_syscall_64+0x69/0xc0 -[ 72.155172] entry_SYSCALL_64_after_hwframe+0x61/0xcb -[ 72.155198] RIP: 0033:0x7f345c7f63ab -[ 72.155218] Code: 0f 1e fa 48 8b 05 e5 7a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d b5 7a 0d 00 f7 d8 64 89 01 48 -[ 72.155301] RSP: 002b:00007ffc97cc89f8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 -[ 72.155339] RAX: ffffffffffffffda RBX: 00007ffc97cc8a30 RCX: 00007f345c7f63ab -[ 72.155375] RDX: 00007ffc97cc8a30 RSI: 00000000c0284b82 RDI: 0000000000000003 -[ 72.155411] RBP: 00000000c0284b82 R08: 0000000000000000 R09: 0000000000000000 -[ 72.155447] R10: 00007f345cd4ddb0 R11: 0000000000000246 R12: 00007ffc97cc8a30 -[ 72.155481] R13: 0000000000000003 R14: 00007ffc97cc8d20 R15: 0000000000000000 -[ 72.155517] diff --git a/tinygrad/extra/assembly/rocm/kernel_crashes/dump2 b/tinygrad/extra/assembly/rocm/kernel_crashes/dump2 deleted file mode 100644 index 8cd24ccf..00000000 --- a/tinygrad/extra/assembly/rocm/kernel_crashes/dump2 +++ /dev/null @@ -1,41 +0,0 @@ -# run two tinygrad matrix example in a loop -# amdgpu-6.0.5-1581431.20.04 -# NOT fixed in kernel 6.2.14 - -[ 553.016624] gmc_v11_0_process_interrupt: 30 callbacks suppressed -[ 553.016631] amdgpu 0000:0b:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:24 vmid:9 pasid:32770, for process python3 pid 10001 thread python3 pid 10001) -[ 553.016790] amdgpu 0000:0b:00.0: amdgpu: in page starting at address 0x00007f0000000000 from client 10 -[ 553.016892] amdgpu 0000:0b:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00901A30 -[ 553.016974] amdgpu 0000:0b:00.0: amdgpu: Faulty UTCL2 client ID: SDMA0 (0xd) -[ 553.017051] amdgpu 0000:0b:00.0: amdgpu: MORE_FAULTS: 0x0 -[ 553.017111] amdgpu 0000:0b:00.0: amdgpu: WALKER_ERROR: 0x0 -[ 553.017173] amdgpu 0000:0b:00.0: amdgpu: PERMISSION_FAULTS: 0x3 -[ 553.017238] amdgpu 0000:0b:00.0: amdgpu: MAPPING_ERROR: 0x0 -[ 553.017300] amdgpu 0000:0b:00.0: amdgpu: RW: 0x0 -[ 553.123921] [drm:mes_v11_0_submit_pkt_and_poll_completion.constprop.0 [amdgpu]] *ERROR* MES failed to response msg=2 -[ 553.124153] amdgpu: failed to add hardware queue to MES, doorbell=0x1a16 -[ 553.124195] amdgpu: MES might be in unrecoverable state, issue a GPU reset -[ 553.124237] amdgpu: Failed to restore queue 2 -[ 553.124266] amdgpu: Failed to restore process queues -[ 553.124270] amdgpu: Failed to evict queue 3 -[ 553.124297] amdgpu: amdgpu_amdkfd_restore_userptr_worker: Failed to resume KFD - -# alternative crash in kernel 6.2.14 - -[ 151.097948] gmc_v11_0_process_interrupt: 30 callbacks suppressed -[ 151.097953] amdgpu 0000:0b:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:24 vmid:8 pasid:32771, for process python3 pid 7525 thread python3 pid 7525) -[ 151.097993] amdgpu 0000:0b:00.0: amdgpu: in page starting at address 0x00007f0000000000 from client 10 -[ 151.098008] amdgpu 0000:0b:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00801A30 -[ 151.098020] amdgpu 0000:0b:00.0: amdgpu: Faulty UTCL2 client ID: SDMA0 (0xd) -[ 151.098032] amdgpu 0000:0b:00.0: amdgpu: MORE_FAULTS: 0x0 -[ 151.098042] amdgpu 0000:0b:00.0: amdgpu: WALKER_ERROR: 0x0 -[ 151.098052] amdgpu 0000:0b:00.0: amdgpu: PERMISSION_FAULTS: 0x3 -[ 151.098062] amdgpu 0000:0b:00.0: amdgpu: MAPPING_ERROR: 0x0 -[ 151.098071] amdgpu 0000:0b:00.0: amdgpu: RW: 0x0 -[ 151.209517] [drm:mes_v11_0_submit_pkt_and_poll_completion.constprop.0 [amdgpu]] *ERROR* MES failed to response msg=2 -[ 151.209724] amdgpu: failed to add hardware queue to MES, doorbell=0x1002 -[ 151.209734] amdgpu: MES might be in unrecoverable state, issue a GPU reset -[ 151.209743] amdgpu: Failed to restore queue 1 -[ 151.209751] amdgpu: Failed to restore process queues -[ 151.209759] amdgpu: amdgpu_amdkfd_restore_userptr_worker: Failed to resume KFD -[ 151.209858] amdgpu 0000:0b:00.0: amdgpu: GPU reset begin! diff --git a/tinygrad/extra/assembly/rocm/kernel_crashes/dump3 b/tinygrad/extra/assembly/rocm/kernel_crashes/dump3 deleted file mode 100644 index ea7ec1d7..00000000 --- a/tinygrad/extra/assembly/rocm/kernel_crashes/dump3 +++ /dev/null @@ -1,20 +0,0 @@ -# two tinygrad + two bandwidth test -# RDNA2, driver 6.0.5 -# recovered from this! - -[ 136.971209] gmc_v10_0_process_interrupt: 39 callbacks suppressed -[ 136.971218] amdgpu 0000:0b:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:24 vmid:11 pasid:32773, for process rocm-bandwidth- pid 20281 thread rocm-bandwidth- pid 20281) -[ 136.971228] amdgpu 0000:0b:00.0: amdgpu: in page starting at address 0x00007f5c2b800000 from client 0x1b (UTCL2) -[ 136.971232] amdgpu 0000:0b:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00B01A31 -[ 136.971233] amdgpu 0000:0b:00.0: amdgpu: Faulty UTCL2 client ID: SDMA0 (0xd) -[ 136.971235] amdgpu 0000:0b:00.0: amdgpu: MORE_FAULTS: 0x1 -[ 136.971236] amdgpu 0000:0b:00.0: amdgpu: WALKER_ERROR: 0x0 -[ 136.971236] amdgpu 0000:0b:00.0: amdgpu: PERMISSION_FAULTS: 0x3 -[ 136.971237] amdgpu 0000:0b:00.0: amdgpu: MAPPING_ERROR: 0x0 -[ 136.971238] amdgpu 0000:0b:00.0: amdgpu: RW: 0x0 -... -[ 136.993979] amdgpu 0000:0b:00.0: amdgpu: IH ring buffer overflow (0x000BE5A0, 0x0003C480, 0x0003E5C0) -[ 138.209072] amdgpu 0000:0b:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x001a address=0x7c00004000 flags=0x0000] -[ 138.209078] amdgpu 0000:0b:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x001a address=0x7c00004d80 flags=0x0000] -[ 138.209081] amdgpu 0000:0b:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x001a address=0x7c00005000 flags=0x0000] -[ 138.209084] amdgpu 0000:0b:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x001a address=0x7c00005d80 flags=0x0000] diff --git a/tinygrad/extra/assembly/rocm/kernel_crashes/dump4 b/tinygrad/extra/assembly/rocm/kernel_crashes/dump4 deleted file mode 100644 index 8c1fa909..00000000 --- a/tinygrad/extra/assembly/rocm/kernel_crashes/dump4 +++ /dev/null @@ -1,33 +0,0 @@ -# ROCK-Kernel-Driver 0b579de9622f5c93021dcb7927d13926313740a2 -# non fatal "crash" - -[ 127.418045] ------------[ cut here ]------------ -[ 127.418046] User pages unexpectedly invalid -[ 127.418056] WARNING: CPU: 16 PID: 260 at drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:3000 amdgpu_amdkfd_restore_userptr_worker+0x4d9/0x500 [amdgpu] -[ 127.418235] Modules linked in: rfcomm cmac algif_hash algif_skcipher af_alg bnep nls_iso8859_1 iwlmvm mac80211 intel_rapl_msr intel_rapl_common edac_mce_amd snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi kvm_amd binfmt_misc snd_hda_intel snd_intel_dspcfg kvm libarc4 snd_intel_sdw_acpi snd_hda_codec btusb iwlwifi btrtl snd_hda_core btbcm btintel irqbypass btmtk snd_hwdep crct10dif_pclmul snd_pcm polyval_clmulni bluetooth snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq polyval_generic cfg80211 ghash_clmulni_intel eeepc_wmi snd_seq_device snd_timer aesni_intel asus_wmi ecdh_generic snd platform_profile crypto_simd ledtrig_audio cryptd ecc ccp soundcore sparse_keymap rapl k10temp wmi_bmof mac_hid sch_fq_codel msr parport_pc ppdev lp parport ramoops pstore_blk efi_pstore reed_solomon pstore_zone ip_tables x_tables autofs4 amdgpu hid_generic usbhid hid i2c_algo_bit drm_ttm_helper ttm video iommu_v2 drm_buddy gpu_sched drm_display_helper drm_kms_helper syscopyarea -[ 127.418276] sysfillrect sysimgblt fb_sys_fops drm nvme nvme_core cec r8169 ahci crc32_pclmul rc_core i2c_piix4 xhci_pci libahci nvme_common xhci_pci_renesas realtek wmi -[ 127.418284] CPU: 16 PID: 260 Comm: kworker/16:1 Tainted: G W 6.0.0 #4 -[ 127.418286] Hardware name: System manufacturer System Product Name/TUF GAMING X570-PLUS (WI-FI), BIOS 3603 03/20/2021 -[ 127.418287] Workqueue: events amdgpu_amdkfd_restore_userptr_worker [amdgpu] -[ 127.418455] RIP: 0010:amdgpu_amdkfd_restore_userptr_worker+0x4d9/0x500 [amdgpu] -[ 127.418601] Code: ff e8 2b 8a 96 d1 e9 66 fe ff ff 48 c7 c7 40 4f f5 c0 e8 56 7b 8a d1 0f 0b e9 2e ff ff ff 48 c7 c7 d8 d0 ed c0 e8 43 7b 8a d1 <0f> 0b e9 0a fe ff ff 4c 89 ef e8 f8 89 96 d1 e9 cb fd ff ff e8 ce -[ 127.418603] RSP: 0018:ffffb36740a83dc8 EFLAGS: 00010282 -[ 127.418604] RAX: 0000000000000000 RBX: ffff9d159ee9df30 RCX: 0000000000000027 -[ 127.418605] RDX: 0000000000000027 RSI: ffffb36740a83c88 RDI: ffff9d242a220568 -[ 127.418606] RBP: ffffb36740a83e58 R08: ffff9d242a220560 R09: 0000000000000001 -[ 127.418607] R10: 0000000000000001 R11: 0000000000000020 R12: ffff9d159ee9df98 -[ 127.418607] R13: ffff9d159ee9df70 R14: ffff9d159ee9dee0 R15: ffff9d159ee9dee0 -[ 127.418608] FS: 0000000000000000(0000) GS:ffff9d242a200000(0000) knlGS:0000000000000000 -[ 127.418609] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 -[ 127.418610] CR2: 00007fd5d4715000 CR3: 0000000120ffe000 CR4: 0000000000750ee0 -[ 127.418611] PKRU: 55555554 -[ 127.418611] Call Trace: -[ 127.418612] -[ 127.418613] process_one_work+0x21f/0x3f0 -[ 127.418615] worker_thread+0x4a/0x3c0 -[ 127.418617] ? process_one_work+0x3f0/0x3f0 -[ 127.418618] kthread+0xf0/0x120 -[ 127.418619] ? kthread_complete_and_exit+0x20/0x20 -[ 127.418620] ret_from_fork+0x22/0x30 -[ 127.418622] -[ 127.418623] ---[ end trace 0000000000000000 ]--- \ No newline at end of file diff --git a/tinygrad/extra/assembly/rocm/rdna3/asm.py b/tinygrad/extra/assembly/rocm/rdna3/asm.py deleted file mode 100644 index 2f6ad132..00000000 --- a/tinygrad/extra/assembly/rocm/rdna3/asm.py +++ /dev/null @@ -1,80 +0,0 @@ -import numpy as np -import pathlib -from hexdump import hexdump -from tinygrad.helpers import colored -from extra.helpers import enable_early_exec -early_exec = enable_early_exec() - -from tinygrad.runtime.ops_gpu import CLProgram, CLBuffer, ROCM_LLVM_PATH - -ENABLE_NON_ASM = False - -WMMA = True -DUAL_ALU = True -F32 = True - -if ENABLE_NON_ASM: - buf = CLBuffer.fromCPU(np.zeros(10, np.float32)) - prg_empty = CLProgram("code", "__kernel void code(__global float *a) { a[0] = 1; }") - asm_real = prg_empty.binary() - with open("/tmp/cc.elf", "wb") as f: - f.write(asm_real) - prg_empty([1], [1], buf, wait=True) - print(buf.toCPU()) - -print(colored("creating CLBuffer", "green")) -buf = CLBuffer.fromCPU(np.zeros(10, np.float32)) -code = open(pathlib.Path(__file__).parent / "prog.s", "r").read() - -gen = [] -FLOPS = 0 -MAX_REG = 251 -for j in range(1): - if WMMA: - KY, KX = 4, 4 - for y in range(KY): - for x in range(KX): - c = (y*KX+x)*8 - a = (KY*KX*8) + y*8 - b = (KY*KX*8) + (KY*8) + x*8 - gen.append(f"v_wmma_f32_16x16x16_f16 v[{c}:{c+7}], v[{a}:{a+7}], v[{b}:{b+7}], v[{c}:{c+7}]") - FLOPS += 16*8*2 - else: - for i in range(0, MAX_REG, 6): - if DUAL_ALU: - if F32: - gen.append(f"v_dual_fmac_f32 v{i+0}, v{i+1}, v{i+2} :: v_dual_fmac_f32 v{i+3}, v{i+4}, v{i+5}") - FLOPS += 4 - else: - gen.append(f"v_dual_dot2acc_f32_f16 v{i+0}, v{i+1}, v{i+2} :: v_dual_dot2acc_f32_f16 v{i+3}, v{i+4}, v{i+5}") - FLOPS += 8 - else: - assert F32 - gen.append(f"v_fmac_f32 v{i+0}, v{i+1}, v{i+2}") - gen.append(f"v_fmac_f32 v{i+3}, v{i+4}, v{i+5}") -code = code.replace("// FLOPS", '\n'.join(gen)) -print(code) - - -# fix: COMGR failed to get code object ISA name. set triple to 'amdgcn-amd-amdhsa' - -object = early_exec(([ROCM_LLVM_PATH / "llvm-mc", '--arch=amdgcn', '--mcpu=gfx1100', '--triple=amdgcn-amd-amdhsa', '--filetype=obj', '-'], code.encode("utf-8"))) -asm = early_exec(([ROCM_LLVM_PATH / "ld.lld", "/dev/stdin", "-o", "/dev/stdout", "--pie"], object)) - -with open("/tmp/cc2.o", "wb") as f: - f.write(object) -with open("/tmp/cc2.elf", "wb") as f: - f.write(asm) - -print(colored("creating CLProgram", "green")) -prg = CLProgram("code", asm) - -print(colored("running program", "green")) -G = 512 -FLOPS *= 100000*G*G # loop * global_size -for i in range(3): - tm = prg(buf, global_size=[G//256, G, 1], local_size=[256, 1, 1], wait=True) - print(f"ran in {tm*1e3:.2f} ms, {FLOPS/(tm*1e9):.2f} GFLOPS") - -print(colored("transferring buffer", "green")) -print(buf.toCPU()) diff --git a/tinygrad/extra/assembly/rocm/rdna3/prog.s b/tinygrad/extra/assembly/rocm/rdna3/prog.s deleted file mode 100644 index 38efca54..00000000 --- a/tinygrad/extra/assembly/rocm/rdna3/prog.s +++ /dev/null @@ -1,80 +0,0 @@ -.global _start -_start: -.rodata -.align 0x10 -.global code.kd -.type code.kd,STT_OBJECT -# amd_kernel_code_t (must be at 0x440 for kernel_code_entry_byte_offset to be right) -code.kd: -# amd_kernel_..., amd_machine_... -.long 0,0,0,0 -# kernel_code_entry_byte_offset, kernel_code_prefetch_byte_offset -.long 0x00000bc0,0x00000000,0x00000000,0x00000000 -# kernel_code_prefetch_byte_size, max_scratch_backing_memory_byte_size -.long 0,0,0,0 -# compute_pgm_rsrc1, compute_pgm_rsrc2, kernel_code_properties, workitem_private_segment_byte_size -.long 0x60af0000,0x0000009e,0x00000408,0x00000000 -# compute_pgm_rsrc1 |= AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32 | AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64 -# compute_pgm_rsrc1 |= AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP | AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE -# compute_pgm_rsrc2 |= AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT = 0xF -# compute_pgm_rsrc2 |= AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X -# kernel_code_properties |= AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR = 1 -# kernel_code_properties |= AMD_KERNEL_CODE_PROPERTIES_RESERVED1 = 1 -.text -.global code -.type code,STT_FUNC -code: -# https://llvm.org/docs/AMDGPUUsage.html#initial-kernel-execution-state -# s[0:1] contains the kernarg_address -# TODO: can we use s[2:3] if this was really a wave since we only alloced 2 SGPRs? -s_load_b64 s[2:3], s[0:1], null - -s_mov_b32 s8, 0 -loop: -s_addk_i32 s8, 1 -s_cmp_eq_u32 s8, 100000 -// FLOPS -s_cbranch_scc0 loop - -# wait for the s_load_b64 -s_waitcnt lgkmcnt(0) - -v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 2.0 -global_store_b32 v0, v1, s[2:3] - -# Deallocate all VGPRs for this wave. Use only when next instruction is S_ENDPGM. -s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -s_endpgm -s_code_end - -.amdgpu_metadata -amdhsa.kernels: - - .args: - - .address_space: global - .name: a - .offset: 0 - .size: 8 - .type_name: 'float*' - .value_kind: global_buffer - .group_segment_fixed_size: 0 - .kernarg_segment_align: 8 - .kernarg_segment_size: 8 - .language: OpenCL C - .language_version: - - 1 - - 2 - .max_flat_workgroup_size: 256 - .name: code - .private_segment_fixed_size: 0 - .sgpr_count: 2 - .sgpr_spill_count: 0 - .symbol: code.kd - .uses_dynamic_stack: false - .vgpr_count: 256 - .vgpr_spill_count: 0 - .wavefront_size: 32 -amdhsa.target: amdgcn-amd-amdhsa--gfx1100 -amdhsa.version: - - 1 - - 2 -.end_amdgpu_metadata diff --git a/tinygrad/extra/assembly/rocm/rocm_clone.sh b/tinygrad/extra/assembly/rocm/rocm_clone.sh deleted file mode 100755 index bff5e938..00000000 --- a/tinygrad/extra/assembly/rocm/rocm_clone.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash -mkdir -p src -cd src -git clone https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface.git -b rocm-5.5.0 -git clone https://github.com/RadeonOpenCompute/ROCm-Device-Libs.git -b rocm-5.5.0 -git clone https://github.com/RadeonOpenCompute/llvm-project.git -b rocm-5.5.0 --depth 1 -git clone https://github.com/RadeonOpenCompute/ROCR-Runtime.git -b rocm-5.5.0 -git clone https://github.com/ROCm-Developer-Tools/ROCclr.git -b rocm-5.5.0 -git clone https://github.com/RadeonOpenCompute/ROCm-CompilerSupport.git -b rocm-5.5.0 -git clone https://github.com/RadeonOpenCompute/ROCm-OpenCL-Runtime.git -b rocm-5.5.0 -cd ../ \ No newline at end of file diff --git a/tinygrad/extra/assembly/rocm/rocm_from_scratch.sh b/tinygrad/extra/assembly/rocm/rocm_from_scratch.sh deleted file mode 100755 index 2be75a35..00000000 --- a/tinygrad/extra/assembly/rocm/rocm_from_scratch.sh +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/bash -mkdir -p build/debs -cd build - -# ROCT-Thunk-Interface (hsakmt) -if [ ! -f debs/hsakmt-roct-dev_5.5.0.99999-local_amd64.deb ] -then - mkdir -p ROCT-Thunk-Interface - cd ROCT-Thunk-Interface - cmake ../../src/ROCT-Thunk-Interface - make -j32 package - cp hsakmt-roct-dev_5.5.0.99999-local_amd64.deb ../debs - cd ../ -fi - - -# build custom LLVM -if [ ! -f llvm-project/bin/clang ] -then - mkdir -p llvm-project - cd llvm-project - cmake -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="llvm;clang;lld" -DLLVM_TARGETS_TO_BUILD="AMDGPU;X86" ../../src/llvm-project/llvm - make -j32 - cd .. -fi - -# use custom LLVM -export PATH="$PWD/llvm-project/bin:$PATH" - -# ROCm-Device-Libs -if [ ! -f debs/rocm-device-libs_1.0.0.99999-local_amd64.deb ] -then - mkdir -p ROCm-Device-Libs - cd ROCm-Device-Libs - cmake ../../src/ROCm-Device-Libs - make -j32 package - cp rocm-device-libs_1.0.0.99999-local_amd64.deb ../debs - cd ../ -fi - -# ROCR-Runtime -if [ ! -f debs/hsa-rocr_1.8.0-local_amd64.deb ] -then - mkdir -p ROCR-Runtime - cd ROCR-Runtime - cmake ../../src/ROCR-Runtime/src - make -j32 package - cp hsa-rocr_1.8.0-local_amd64.deb ../debs - cp hsa-rocr-dev_1.8.0-local_amd64.deb ../debs - cd ../ -fi - -# ROCm-OpenCL-Runtime (needs ROCclr) -if [ ! -f debs/rocm-opencl_2.0.0-local_amd64.deb ] -then - mkdir -p ROCm-OpenCL-Runtime - cd ROCm-OpenCL-Runtime - cmake ../../src/ROCm-OpenCL-Runtime - make -j32 package - cp rocm-opencl_2.0.0-local_amd64.deb ../debs - cp rocm-opencl-dev_2.0.0-local_amd64.deb ../debs - cp rocm-ocl-icd_2.0.0-local_amd64.deb ../debs -fi - -# ROCm-CompilerSupport (broken) -#mkdir -p ROCm-CompilerSupport -#cd ROCm-CompilerSupport -#cmake ../../src/ROCm-CompilerSupport/lib/comgr -#make -j32 \ No newline at end of file diff --git a/tinygrad/extra/assembly/rocm/rocm_setup.sh b/tinygrad/extra/assembly/rocm/rocm_setup.sh deleted file mode 100755 index 880105cb..00000000 --- a/tinygrad/extra/assembly/rocm/rocm_setup.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -rm amdgpu-install_5.5.50500-1_all.deb -wget https://repo.radeon.com/amdgpu-install/5.5/ubuntu/$(lsb_release -cs)/amdgpu-install_5.5.50500-1_all.deb -sudo dpkg -i amdgpu-install_5.5.50500-1_all.deb -sudo apt-get update - -# kernel driver -sudo apt-get install amdgpu-dkms - -# for opencl -sudo apt-get install rocm-opencl-runtime - -# for HIP -sudo apt-get install hip-runtime-amd rocm-device-libs hip-dev diff --git a/tinygrad/extra/assembly/rocm/sniffer/build.sh b/tinygrad/extra/assembly/rocm/sniffer/build.sh deleted file mode 100755 index 86fcc05f..00000000 --- a/tinygrad/extra/assembly/rocm/sniffer/build.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash -e -clang sniff.cc -Werror -shared -fPIC -I../src/ -I../src/ROCT-Thunk-Interface/include -I../src/ROCm-Device-Libs/ockl/inc -o sniff.so -lstdc++ -#AMD_LOG_LEVEL=4 HSAKMT_DEBUG_LEVEL=7 LD_PRELOAD=$PWD/sniff.so /home/tiny/build/HIP-Examples/HIP-Examples-Applications/HelloWorld/HelloWorld -#AMD_LOG_LEVEL=4 LD_PRELOAD=$PWD/sniff.so $HOME/build/HIP-Examples/HIP-Examples-Applications/HelloWorld/HelloWorld -#AMD_LOG_LEVEL=5 LD_PRELOAD=$PWD/sniff.so python3 ../rdna3/asm.py -DEBUG=5 LD_PRELOAD=$PWD/sniff.so python3 ../rdna3/asm.py -#AMD_LOG_LEVEL=5 HSAKMT_DEBUG_LEVEL=7 DEBUG=5 LD_PRELOAD=$PWD/sniff.so strace -F python3 ../rdna3/asm.py -#LD_PRELOAD=$PWD/sniff.so python3 ../rdna3/asm.py -#AMD_LOG_LEVEL=4 LD_PRELOAD=$PWD/sniff.so FORWARD_ONLY=1 DEBUG=2 python3 ../../../test/test_ops.py TestOps.test_add -#AMD_LOG_LEVEL=4 HSAKMT_DEBUG_LEVEL=7 LD_PRELOAD=$PWD/sniff.so rocm-bandwidth-test -s 0 -d 1 -m 1 -#AMD_LOG_LEVEL=4 HSAKMT_DEBUG_LEVEL=7 LD_PRELOAD=$PWD/sniff.so rocm-bandwidth-test -s 1 -d 2 -m 1 diff --git a/tinygrad/extra/assembly/rocm/sniffer/sniff.cc b/tinygrad/extra/assembly/rocm/sniffer/sniff.cc deleted file mode 100644 index 95270591..00000000 --- a/tinygrad/extra/assembly/rocm/sniffer/sniff.cc +++ /dev/null @@ -1,282 +0,0 @@ -// template copied from https://github.com/geohot/cuda_ioctl_sniffer/blob/master/sniff.cc - -#include -#include -#include -#include -#include -#include - -#include - -// includes from the ROCm sources -#include -#include -#include -#include -using namespace rocr::AMD; - -#include -#include -std::map files; -std::map ring_base_addresses; - -#define D(args...) fprintf(stderr, args) - -uint64_t doorbell_offset = -1; -std::map queue_types; - -void hexdump(void *d, int l) { - for (int i = 0; i < l; i++) { - if (i%0x10 == 0 && i != 0) printf("\n"); - if (i%0x10 == 8) printf(" "); - if (i%0x10 == 0) printf("%8X: ", i); - printf("%2.2X ", ((uint8_t*)d)[i]); - } - printf("\n"); -} - -extern "C" { - -// https://defuse.ca/online-x86-assembler.htm#disassembly2 -static void handler(int sig, siginfo_t *si, void *unused) { - ucontext_t *u = (ucontext_t *)unused; - uint8_t *rip = (uint8_t*)u->uc_mcontext.gregs[REG_RIP]; - - int store_size = 0; - uint64_t value; - if (rip[0] == 0x48 && rip[1] == 0x89 && rip[2] == 0x30) { - // 0: 48 89 30 mov QWORD PTR [rax],rsi - store_size = 8; - value = u->uc_mcontext.gregs[REG_RSI]; - u->uc_mcontext.gregs[REG_RIP] += 3; - } else if (rip[0] == 0x4c && rip[1] == 0x89 && rip[2] == 0x28) { - // 0: 4c 89 28 mov QWORD PTR [rax],r13 - store_size = 8; - value = u->uc_mcontext.gregs[REG_R13]; - u->uc_mcontext.gregs[REG_RIP] += 3; - } else { - D("segfault %02X %02X %02X %02X %02X %02X %02X %02X rip: %p addr: %p\n", rip[0], rip[1], rip[2], rip[3], rip[4], rip[5], rip[6], rip[7], rip, si->si_addr); - D("rax: %llx rcx: %llx rdx: %llx rsi: %llx rbx: %llx\n", u->uc_mcontext.gregs[REG_RAX], u->uc_mcontext.gregs[REG_RCX], u->uc_mcontext.gregs[REG_RDX], u->uc_mcontext.gregs[REG_RSI], u->uc_mcontext.gregs[REG_RBX]); - exit(-1); - } - - uint64_t ring_base_address = ring_base_addresses[((uint64_t)si->si_addr)&0xFFF]; - int queue_type = queue_types[((uint64_t)si->si_addr)&0xFFF]; - D("%16p: \u001b[31mDING DONG\u001b[0m (queue_type %d) store(%d): 0x%8lx -> %p ring_base_address:0x%lx\n", rip, queue_type, store_size, value, si->si_addr, ring_base_address); - - if (queue_type == KFD_IOC_QUEUE_TYPE_SDMA) { - uint8_t *sdma_ptr = (uint8_t*)(ring_base_address); - while (sdma_ptr < ((uint8_t*)(ring_base_address)+value)) { - D("0x%3lx: ", sdma_ptr-(uint8_t*)(ring_base_address)); - if (sdma_ptr[0] == SDMA_OP_TIMESTAMP) { - D("SDMA_PKT_TIMESTAMP\n"); - sdma_ptr += sizeof(SDMA_PKT_TIMESTAMP); - } else if (sdma_ptr[0] == SDMA_OP_GCR) { - D("SDMA_PKT_GCR\n"); - sdma_ptr += sizeof(SDMA_PKT_GCR); - } else if (sdma_ptr[0] == SDMA_OP_ATOMIC) { - D("SDMA_PKT_ATOMIC\n"); - sdma_ptr += sizeof(SDMA_PKT_ATOMIC); - } else if (sdma_ptr[0] == SDMA_OP_FENCE) { - D("SDMA_PKT_FENCE\n"); - sdma_ptr += sizeof(SDMA_PKT_FENCE); - } else if (sdma_ptr[0] == SDMA_OP_TRAP) { - D("SDMA_PKT_TRAP\n"); - sdma_ptr += sizeof(SDMA_PKT_TRAP); - } else if (sdma_ptr[0] == SDMA_OP_COPY && sdma_ptr[1] == SDMA_SUBOP_COPY_LINEAR) { - SDMA_PKT_COPY_LINEAR *pkt = (SDMA_PKT_COPY_LINEAR *)sdma_ptr; - D("SDMA_PKT_COPY_LINEAR: count:0x%x src:0x%lx dst:0x%lx\n", pkt->COUNT_UNION.count+1, - (uint64_t)pkt->SRC_ADDR_LO_UNION.src_addr_31_0 | ((uint64_t)pkt->SRC_ADDR_HI_UNION.src_addr_63_32 << 32), - (uint64_t)pkt->DST_ADDR_LO_UNION.dst_addr_31_0 | ((uint64_t)pkt->DST_ADDR_HI_UNION.dst_addr_63_32 << 32) - ); - sdma_ptr += sizeof(SDMA_PKT_COPY_LINEAR); - } else { - D("unhandled packet type %d %d, exiting\n", sdma_ptr[0], sdma_ptr[1]); - break; - } - } - - //hexdump((void*)(ring_base_address), 0x100); - } else if (queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) { - hsa_kernel_dispatch_packet_t *pkt = (hsa_kernel_dispatch_packet_t *)(ring_base_address+value*0x40); - if ((pkt->header&0xFF) == HSA_PACKET_TYPE_KERNEL_DISPATCH) { - D("HSA_PACKET_TYPE_KERNEL_DISPATCH -- setup:%d workgroup[%d, %d, %d] grid[%d, %d, %d] kernel_object:0x%lx kernarg_address:%p\n", pkt->setup, pkt->workgroup_size_x, pkt->workgroup_size_y, pkt->workgroup_size_z, pkt->grid_size_x, pkt->grid_size_y, pkt->grid_size_z, pkt->kernel_object, pkt->kernarg_address); - amd_kernel_code_t *code = (amd_kernel_code_t *)pkt->kernel_object; - D("kernel_code_entry_byte_offset:%lx\n", code->kernel_code_entry_byte_offset); - uint32_t *kernel_code = (uint32_t*)(pkt->kernel_object + code->kernel_code_entry_byte_offset); - int code_len = 0; - while (kernel_code[code_len] != 0xbf9f0000 && kernel_code[code_len] != 0) code_len++; - hexdump(kernel_code, code_len*4); - /*FILE *f = fopen("/tmp/kernel_code", "wb"); - fwrite(kernel_code, 4, code_len, f); - fclose(f); - system("python -c 'print(\" \".join([(\"0x%02X\"%x) for x in open(\"/tmp/kernel_code\", \"rb\").read()]))' | ../build/llvm-project/bin/llvm-mc --disassemble --arch=amdgcn --mcpu=gfx1100 --show-encoding");*/ - D("kernargs (kernarg_segment_byte_size:0x%lx)\n", code->kernarg_segment_byte_size); - // get length - int i; - for (i = 0; i < 0x400; i+=0x10) { - if (memcmp((void*)((uint64_t)pkt->kernarg_address+i), "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 0x10) == 0) break; - } - hexdump((void*)pkt->kernarg_address, i+0x10); - } else if ((pkt->header&0xFF) == HSA_PACKET_TYPE_BARRIER_AND) { - hsa_barrier_and_packet_t *pkt_and = (hsa_barrier_and_packet_t *)(ring_base_address+value*0x40); - D("HSA_PACKET_TYPE_BARRIER_AND completion_signal:0x%lx\n", pkt_and->completion_signal.handle); - //hexdump((void*)(ring_base_address+value*0x40), 0x40); - } else if ((pkt->header&0xFF) == HSA_PACKET_TYPE_VENDOR_SPECIFIC) { - D("HSA_PACKET_TYPE_VENDOR_SPECIFIC\n"); - hexdump((void*)(ring_base_address+value*0x40), 0x40); - } else { - hexdump((void*)(ring_base_address+value*0x40), 0x40); - } - } - - mprotect((void *)((uint64_t)si->si_addr & ~0xFFF), 0x2000, PROT_READ | PROT_WRITE); - if (store_size == 8) { - *(volatile uint64_t*)(si->si_addr) = value; - } else if (store_size == 4) { - *(volatile uint32_t*)(si->si_addr) = value; - } else if (store_size == 2) { - *(volatile uint16_t*)(si->si_addr) = value; - } else { - D("store size not supported\n"); - exit(-1); - } - mprotect((void *)((uint64_t)si->si_addr & ~0xFFF), 0x2000, PROT_NONE); -} - -void register_sigsegv_handler() { - struct sigaction sa = {0}; - sa.sa_flags = SA_SIGINFO; - sigemptyset(&sa.sa_mask); - sa.sa_sigaction = handler; - if (sigaction(SIGSEGV, &sa, NULL) == -1) { - D("ERROR: failed to register sigsegv handler"); - exit(-1); - } - // NOTE: python (or ocl runtime?) blocks the SIGSEGV signal - sigset_t x; - sigemptyset(&x); - sigaddset(&x, SIGSEGV); - sigprocmask(SIG_UNBLOCK, &x, NULL); -} - -int (*my_open)(const char *pathname, int flags, mode_t mode); -#undef open -int open(const char *pathname, int flags, mode_t mode) { - if (my_open == NULL) my_open = reinterpret_cast(dlsym(RTLD_NEXT, "open")); - int ret = my_open(pathname, flags, mode); - //D("open %s (0o%o) = %d\n", pathname, flags, ret); - files[ret] = pathname; - return ret; -} - - -int (*my_open64)(const char *pathname, int flags, mode_t mode); -#undef open -int open64(const char *pathname, int flags, mode_t mode) { - if (my_open64 == NULL) my_open64 = reinterpret_cast(dlsym(RTLD_NEXT, "open64")); - int ret = my_open64(pathname, flags, mode); - //D("open %s (0o%o) = %d\n", pathname, flags, ret); - files[ret] = pathname; - return ret; -} - -void *(*my_mmap)(void *addr, size_t length, int prot, int flags, int fd, off_t offset); -#undef mmap -void *mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { - if (my_mmap == NULL) my_mmap = reinterpret_cast(dlsym(RTLD_NEXT, "mmap")); - void *ret = my_mmap(addr, length, prot, flags, fd, offset); - - if (doorbell_offset != -1 && offset == doorbell_offset) { - D("HIDDEN DOORBELL %p, handled by %p\n", addr, handler); - register_sigsegv_handler(); - mprotect(addr, length, PROT_NONE); - } - - if (fd != -1) D("mmapped %p (target %p) with flags 0x%x length 0x%zx fd %d %s offset 0x%lx\n", ret, addr, flags, length, fd, files[fd].c_str(), offset); - return ret; -} - -void *(*my_mmap64)(void *addr, size_t length, int prot, int flags, int fd, off_t offset); -#undef mmap64 -void *mmap64(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { return mmap(addr, length, prot, flags, fd, offset); } - -int ioctl_num = 1; -int (*my_ioctl)(int filedes, unsigned long request, void *argp) = NULL; -#undef ioctl -int ioctl(int filedes, unsigned long request, void *argp) { - if (my_ioctl == NULL) my_ioctl = reinterpret_cast(dlsym(RTLD_NEXT, "ioctl")); - int ret = 0; - ret = my_ioctl(filedes, request, argp); - if (!files.count(filedes)) return ret; - - uint8_t type = (request >> 8) & 0xFF; - uint8_t nr = (request >> 0) & 0xFF; - uint16_t size = (request >> 16) & 0xFFF; - - D("%3d: %d = %3d(%20s) 0x%3x ", ioctl_num, ret, filedes, files[filedes].c_str(), size); - - if (request == AMDKFD_IOC_SET_EVENT) { - kfd_ioctl_set_event_args *args = (kfd_ioctl_set_event_args *)argp; - D("AMDKFD_IOC_SET_EVENT event_id:%d", args->event_id); - } else if (request == AMDKFD_IOC_ALLOC_MEMORY_OF_GPU) { - kfd_ioctl_alloc_memory_of_gpu_args *args = (kfd_ioctl_alloc_memory_of_gpu_args *)argp; - D("AMDKFD_IOC_ALLOC_MEMORY_OF_GPU va_addr:0x%llx size:0x%llx handle:%llX gpu_id:0x%x", args->va_addr, args->size, args->handle, args->gpu_id); - } else if (request == AMDKFD_IOC_MAP_MEMORY_TO_GPU) { - kfd_ioctl_map_memory_to_gpu_args *args = (kfd_ioctl_map_memory_to_gpu_args *)argp; - D("AMDKFD_IOC_MAP_MEMORY_TO_GPU handle:%llX", args->handle); - } else if (request == AMDKFD_IOC_CREATE_EVENT) { - kfd_ioctl_create_event_args *args = (kfd_ioctl_create_event_args *)argp; - D("AMDKFD_IOC_CREATE_EVENT event_page_offset:0x%llx event_type:%d event_id:%d", args->event_page_offset, args->event_type, args->event_id); - } else if (request == AMDKFD_IOC_WAIT_EVENTS) { - D("AMDKFD_IOC_WAIT_EVENTS"); - } else if (request == AMDKFD_IOC_SET_XNACK_MODE) { - D("AMDKFD_IOC_SET_XNACK_MODE"); - } else if (request == AMDKFD_IOC_SVM || (type == 0x4b && nr == 0x20)) { - // NOTE: this one is variable length - kfd_ioctl_svm_args *args = (kfd_ioctl_svm_args *)argp; - D("AMDKFD_IOC_SVM start_addr:0x%llx size:0x%llx op:%d", args->start_addr, args->size, args->op); - } else if (request == AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU) { - kfd_ioctl_unmap_memory_from_gpu_args *args = (kfd_ioctl_unmap_memory_from_gpu_args *)argp; - D("AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU handle:%llX", args->handle); - } else if (request == AMDKFD_IOC_FREE_MEMORY_OF_GPU) { - D("AMDKFD_IOC_FREE_MEMORY_OF_GPU"); - } else if (request == AMDKFD_IOC_SET_SCRATCH_BACKING_VA) { - D("AMDKFD_IOC_SET_SCRATCH_BACKING_VA"); - } else if (request == AMDKFD_IOC_GET_TILE_CONFIG) { - D("AMDKFD_IOC_GET_TILE_CONFIG"); - } else if (request == AMDKFD_IOC_SET_TRAP_HANDLER) { - D("AMDKFD_IOC_SET_TRAP_HANDLER"); - } else if (request == AMDKFD_IOC_GET_VERSION) { - kfd_ioctl_get_version_args *args = (kfd_ioctl_get_version_args *)argp; - D("AMDKFD_IOC_GET_VERSION major_version:%d minor_version:%d", args->major_version, args->minor_version); - } else if (request == AMDKFD_IOC_GET_PROCESS_APERTURES_NEW) { - D("AMDKFD_IOC_GET_PROCESS_APERTURES_NEW"); - } else if (request == AMDKFD_IOC_ACQUIRE_VM) { - D("AMDKFD_IOC_ACQUIRE_VM"); - } else if (request == AMDKFD_IOC_SET_MEMORY_POLICY) { - D("AMDKFD_IOC_SET_MEMORY_POLICY"); - } else if (request == AMDKFD_IOC_GET_CLOCK_COUNTERS) { - D("AMDKFD_IOC_GET_CLOCK_COUNTERS"); - } else if (request == AMDKFD_IOC_CREATE_QUEUE) { - kfd_ioctl_create_queue_args *args = (kfd_ioctl_create_queue_args *)argp; - D("AMDKFD_IOC_CREATE_QUEUE\n"); - D("queue_type:%d ring_base_address:0x%llx\n", args->queue_type, args->ring_base_address); - D("eop_buffer_address:0x%llx ctx_save_restore_address:0x%llx\n", args->eop_buffer_address, args->ctx_save_restore_address); - D("ring_size:0x%x queue_priority:%d\n", args->ring_size, args->queue_priority); - D("RETURNS write_pointer_address:0x%llx read_pointer_address:0x%llx doorbell_offset:0x%llx queue_id:%d\n", args->write_pointer_address, args->read_pointer_address, args->doorbell_offset, args->queue_id); - //D("RETURNS *write_pointer_address:0x%llx *read_pointer_address:0x%llx\n", *(uint64_t*)args->write_pointer_address, *(uint64_t*)args->read_pointer_address); - ring_base_addresses[args->doorbell_offset&0xFFF] = args->ring_base_address; - queue_types[args->doorbell_offset&0xFFF] = args->queue_type; - doorbell_offset = args->doorbell_offset&~0xFFF; - } else { - D("type:0x%x nr:0x%x size:0x%x", type, nr, size); - } - - D("\n"); - ioctl_num++; - return ret; -} - -} diff --git a/tinygrad/extra/augment.py b/tinygrad/extra/augment.py deleted file mode 100644 index 06e7906c..00000000 --- a/tinygrad/extra/augment.py +++ /dev/null @@ -1,42 +0,0 @@ -import numpy as np -from PIL import Image -from pathlib import Path -import sys -cwd = Path.cwd() -sys.path.append(cwd.as_posix()) -sys.path.append((cwd / 'test').as_posix()) -from extra.datasets import fetch_mnist -from tqdm import trange - -def augment_img(X, rotate=10, px=3): - Xaug = np.zeros_like(X) - for i in trange(len(X)): - im = Image.fromarray(X[i]) - im = im.rotate(np.random.randint(-rotate,rotate), resample=Image.BICUBIC) - w, h = X.shape[1:] - #upper left, lower left, lower right, upper right - quad = np.random.randint(-px,px,size=(8)) + np.array([0,0,0,h,w,h,w,0]) - im = im.transform((w, h), Image.QUAD, quad, resample=Image.BICUBIC) - Xaug[i] = im - return Xaug - -if __name__ == "__main__": - import matplotlib.pyplot as plt - X_train, Y_train, X_test, Y_test = fetch_mnist() - X_train = X_train.reshape(-1, 28, 28).astype(np.uint8) - X_test = X_test.reshape(-1, 28, 28).astype(np.uint8) - X = np.vstack([X_train[:1]]*10+[X_train[1:2]]*10) - fig, a = plt.subplots(2,len(X)) - Xaug = augment_img(X) - for i in range(len(X)): - a[0][i].imshow(X[i], cmap='gray') - a[1][i].imshow(Xaug[i],cmap='gray') - a[0][i].axis('off') - a[1][i].axis('off') - plt.show() - - #create some nice gifs for doc?! - for i in range(10): - im = Image.fromarray(X_train[7353+i]) - im_aug = [Image.fromarray(x) for x in augment_img(np.array([X_train[7353+i]]*100))] - im.save(f"aug{i}.gif", save_all=True, append_images=im_aug, duration=100, loop=0) diff --git a/tinygrad/extra/backends/clang_graph.py b/tinygrad/extra/backends/clang_graph.py deleted file mode 100644 index 9c0cf3b3..00000000 --- a/tinygrad/extra/backends/clang_graph.py +++ /dev/null @@ -1,39 +0,0 @@ -from typing import List, Dict, cast -import ctypes -from tinygrad.helpers import dedup, cpu_time_execution, DEBUG -from tinygrad.engine.jit import GraphRunner, GraphException -from tinygrad.device import Buffer, Device -from tinygrad.engine.realize import ExecItem, CompiledRunner -from tinygrad.uop.ops import Variable -from tinygrad.runtime.ops_cpu import ClangProgram -from tinygrad.renderer.cstyle import ClangRenderer -render_dtype = ClangRenderer().render_dtype - -class ClangGraph(GraphRunner): - def __init__(self, jit_cache: List[ExecItem], input_rawbuffers: List[Buffer], var_vals: Dict[Variable, int]): - super().__init__(jit_cache, input_rawbuffers, var_vals) - if not all(isinstance(ji.prg, CompiledRunner) for ji in jit_cache): raise GraphException - - prgs = '\n'.join(dedup([cast(CompiledRunner, ji.prg).p.src for ji in jit_cache])) - args = [f"{render_dtype(x.dtype)}* arg{i}" for i,x in enumerate(input_rawbuffers)] - args += sorted([f"int {v.expr}" for v in var_vals]) - code = ["void batched("+','.join(args)+") {"] - for ji in jit_cache: - args = [] - for buf in ji.bufs: - assert buf is not None - if buf in input_rawbuffers: - args.append(f"arg{input_rawbuffers.index(buf)}") - else: - args.append(f"({render_dtype(buf.dtype)}*)0x{ctypes.addressof(buf._buf):X}") - args += [x.expr for x in cast(CompiledRunner, ji.prg).p.vars] - code.append(f" {cast(CompiledRunner, ji.prg).p.function_name}({','.join(args)});") - code.append("}") - if DEBUG >= 4: print("\n".join(code)) - compiler = Device["CPU"].compiler - assert compiler is not None - self._prg = ClangProgram("batched", compiler.compile(prgs+"\n"+"\n".join(code))) # no point in caching the pointers - - def __call__(self, rawbufs: List[Buffer], var_vals: Dict[Variable, int], wait=False): - return cpu_time_execution( - lambda: self._prg(*[x._buf for x in rawbufs], *[x[1] for x in sorted(var_vals.items(), key=lambda x: x[0].expr)]), enable=wait) \ No newline at end of file diff --git a/tinygrad/extra/backends/graph_hip.py b/tinygrad/extra/backends/graph_hip.py deleted file mode 100644 index ddcb3d58..00000000 --- a/tinygrad/extra/backends/graph_hip.py +++ /dev/null @@ -1,27 +0,0 @@ -import ctypes -from typing import Tuple -import tinygrad.runtime.autogen.hip as hip -from tinygrad.helpers import init_c_var, time_execution_cuda_style -from tinygrad.runtime.ops_hip import check, hip_set_device -from tinygrad.runtime.graph.cuda import CUDAGraph - -# TODO: this is only used in graph -def hip_time_execution(cb, enable=False): return time_execution_cuda_style(cb, hip.hipEvent_t, hip.hipEventCreate, hip.hipEventRecord, hip.hipEventSynchronize, hip.hipEventDestroy, hip.hipEventElapsedTime, enable=enable) # noqa: E501 - -class HIPGraph(CUDAGraph): - def __del__(self): - if hasattr(self, 'graph'): check(hip.hipGraphDestroy(self.graph)) - if hasattr(self, 'instance'): check(hip.hipGraphExecDestroy(self.instance)) - def set_device(self): hip_set_device(self.dev) - def encode_args_info(self): return (hip.hipDeviceptr_t, (1,2,3)) - def graph_create(self): return init_c_var(hip.hipGraph_t(), lambda x: check(hip.hipGraphCreate(ctypes.byref(x), 0))) - def graph_instantiate(self, graph): - return init_c_var(hip.hipGraphExec_t(), lambda x: check(hip.hipGraphInstantiate(ctypes.byref(x), graph, None, None, 0))) - def graph_add_kernel_node(self, graph, c_deps, c_params): - return init_c_var(hip.hipGraphNode_t(), lambda x: check(hip.hipGraphAddKernelNode(ctypes.byref(x), graph, c_deps, ctypes.sizeof(c_deps)//8 if c_deps else 0, ctypes.byref(c_params)))) # noqa: E501 - def graph_launch(self, *args, wait=False): return hip_time_execution(lambda: check(hip.hipGraphLaunch(*args)), enable=wait) - def graph_exec_kernel_node_set_params(self, *args): return check(hip.hipGraphExecKernelNodeSetParams(*args)) - def build_kernel_node_params(self, prg, global_size, local_size, c_config): - return hip.hipKernelNodeParams(hip.dim3(*local_size), c_config, ctypes.cast(prg.clprg.prg, ctypes.c_void_p), hip.dim3(*global_size), None, 0) - def set_kernel_node_launch_dims(self, node, global_size: Tuple[int, int, int], local_size: Tuple[int, int, int]): - node.blockDim.x, node.blockDim.y, node.blockDim.z, node.gridDim.x, node.gridDim.y, node.gridDim.z = *local_size, *global_size diff --git a/tinygrad/extra/backends/hsa_driver.py b/tinygrad/extra/backends/hsa_driver.py deleted file mode 100644 index 3091e0c0..00000000 --- a/tinygrad/extra/backends/hsa_driver.py +++ /dev/null @@ -1,143 +0,0 @@ -import ctypes, collections -import tinygrad.runtime.autogen.hsa as hsa -from tinygrad.helpers import init_c_var - -def check(status): - if status != 0: - hsa.hsa_status_string(status, ctypes.byref(status_str := ctypes.POINTER(ctypes.c_char)())) - raise RuntimeError(f"HSA Error {status}: {ctypes.string_at(status_str).decode()}") - -# Precalulated AQL info -AQL_PACKET_SIZE = ctypes.sizeof(hsa.hsa_kernel_dispatch_packet_t) -EMPTY_SIGNAL = hsa.hsa_signal_t() - -DISPATCH_KERNEL_SETUP = 3 << hsa.HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS -DISPATCH_KERNEL_HEADER = 1 << hsa.HSA_PACKET_HEADER_BARRIER -DISPATCH_KERNEL_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE -DISPATCH_KERNEL_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE -DISPATCH_KERNEL_HEADER |= hsa.HSA_PACKET_TYPE_KERNEL_DISPATCH << hsa.HSA_PACKET_HEADER_TYPE - -BARRIER_HEADER = 1 << hsa.HSA_PACKET_HEADER_BARRIER -BARRIER_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE -BARRIER_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE -BARRIER_HEADER |= hsa.HSA_PACKET_TYPE_BARRIER_AND << hsa.HSA_PACKET_HEADER_TYPE - -class AQLQueue: - def __init__(self, device, sz=-1): - self.device = device - - check(hsa.hsa_agent_get_info(self.device.agent, hsa.HSA_AGENT_INFO_QUEUE_MAX_SIZE, ctypes.byref(max_queue_size := ctypes.c_uint32()))) - queue_size = min(max_queue_size.value, sz) if sz != -1 else max_queue_size.value - - null_func = ctypes.CFUNCTYPE(None, hsa.hsa_status_t, ctypes.POINTER(hsa.struct_hsa_queue_s), ctypes.c_void_p)() - self.hw_queue = init_c_var(ctypes.POINTER(hsa.hsa_queue_t)(), lambda x: check( - hsa.hsa_queue_create(self.device.agent, queue_size, hsa.HSA_QUEUE_TYPE_SINGLE, null_func, None, (1<<32)-1, (1<<32)-1, ctypes.byref(x)))) - - self.next_doorbell_index = 0 - self.queue_base = self.hw_queue.contents.base_address - self.queue_size = self.hw_queue.contents.size * AQL_PACKET_SIZE # in bytes - self.write_addr = self.queue_base - self.write_addr_end = self.queue_base + self.queue_size - 1 # precalc saves some time - self.available_packet_slots = self.hw_queue.contents.size - - check(hsa.hsa_amd_queue_set_priority(self.hw_queue, hsa.HSA_AMD_QUEUE_PRIORITY_HIGH)) - check(hsa.hsa_amd_profiling_set_profiler_enabled(self.hw_queue, 1)) - - def __del__(self): - if hasattr(self, 'hw_queue'): check(hsa.hsa_queue_destroy(self.hw_queue)) - - def submit_kernel(self, prg, global_size, local_size, kernargs, completion_signal=None): - if self.available_packet_slots == 0: self._wait_queue() - - packet = hsa.hsa_kernel_dispatch_packet_t.from_address(self.write_addr) - packet.workgroup_size_x = local_size[0] - packet.workgroup_size_y = local_size[1] - packet.workgroup_size_z = local_size[2] - packet.reserved0 = 0 - packet.grid_size_x = global_size[0] * local_size[0] - packet.grid_size_y = global_size[1] * local_size[1] - packet.grid_size_z = global_size[2] * local_size[2] - packet.private_segment_size = prg.private_segment_size - packet.group_segment_size = prg.group_segment_size - packet.kernel_object = prg.handle - packet.kernarg_address = kernargs - packet.reserved2 = 0 - packet.completion_signal = completion_signal if completion_signal else EMPTY_SIGNAL - packet.setup = DISPATCH_KERNEL_SETUP - packet.header = DISPATCH_KERNEL_HEADER - self._submit_packet() - - def submit_barrier(self, wait_signals=None, completion_signal=None): - assert wait_signals is None or len(wait_signals) <= 5 - if self.available_packet_slots == 0: self._wait_queue() - - packet = hsa.hsa_barrier_and_packet_t.from_address(self.write_addr) - packet.reserved0 = 0 - packet.reserved1 = 0 - for i in range(5): - packet.dep_signal[i] = wait_signals[i] if wait_signals and len(wait_signals) > i else EMPTY_SIGNAL - packet.reserved2 = 0 - packet.completion_signal = completion_signal if completion_signal else EMPTY_SIGNAL - packet.header = BARRIER_HEADER - self._submit_packet() - - def blit_packets(self, packet_addr, packet_cnt): - if self.available_packet_slots < packet_cnt: self._wait_queue(packet_cnt) - - tail_blit_packets = min((self.queue_base + self.queue_size - self.write_addr) // AQL_PACKET_SIZE, packet_cnt) - rem_packet_cnt = packet_cnt - tail_blit_packets - ctypes.memmove(self.write_addr, packet_addr, AQL_PACKET_SIZE * tail_blit_packets) - if rem_packet_cnt > 0: ctypes.memmove(self.queue_base, packet_addr + AQL_PACKET_SIZE * tail_blit_packets, AQL_PACKET_SIZE * rem_packet_cnt) - - self._submit_packet(packet_cnt) - - def wait(self): - self.submit_barrier([], finish_signal := self.device.alloc_signal(reusable=True)) - hsa.hsa_signal_wait_scacquire(finish_signal, hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - self.available_packet_slots = self.queue_size // AQL_PACKET_SIZE - - def _wait_queue(self, need_packets=1): - while self.available_packet_slots < need_packets: - rindex = hsa.hsa_queue_load_read_index_relaxed(self.hw_queue) - self.available_packet_slots = self.queue_size // AQL_PACKET_SIZE - (self.next_doorbell_index - rindex) - - def _submit_packet(self, cnt=1): - self.available_packet_slots -= cnt - self.next_doorbell_index += cnt - hsa.hsa_queue_store_write_index_relaxed(self.hw_queue, self.next_doorbell_index) - hsa.hsa_signal_store_screlease(self.hw_queue.contents.doorbell_signal, self.next_doorbell_index-1) - - self.write_addr += AQL_PACKET_SIZE * cnt - if self.write_addr > self.write_addr_end: - self.write_addr = self.queue_base + (self.write_addr - self.queue_base) % self.queue_size - -def scan_agents(): - agents = collections.defaultdict(list) - - @ctypes.CFUNCTYPE(hsa.hsa_status_t, hsa.hsa_agent_t, ctypes.c_void_p) - def __scan_agents(agent, data): - status = hsa.hsa_agent_get_info(agent, hsa.HSA_AGENT_INFO_DEVICE, ctypes.byref(device_type := hsa.hsa_device_type_t())) - if status == 0: agents[device_type.value].append(agent) - return hsa.HSA_STATUS_SUCCESS - - hsa.hsa_iterate_agents(__scan_agents, None) - return agents - -def find_memory_pool(agent, segtyp=-1, location=-1): - @ctypes.CFUNCTYPE(hsa.hsa_status_t, hsa.hsa_amd_memory_pool_t, ctypes.c_void_p) - def __filter_amd_memory_pools(mem_pool, data): - check(hsa.hsa_amd_memory_pool_get_info(mem_pool, hsa.HSA_AMD_MEMORY_POOL_INFO_SEGMENT, ctypes.byref(segment := hsa.hsa_amd_segment_t()))) - if segtyp >= 0 and segment.value != segtyp: return hsa.HSA_STATUS_SUCCESS - - check(hsa.hsa_amd_memory_pool_get_info(mem_pool, hsa.HSA_AMD_MEMORY_POOL_INFO_LOCATION, ctypes.byref(loc:=hsa.hsa_amd_memory_pool_location_t()))) - if location >= 0 and loc.value != location: return hsa.HSA_STATUS_SUCCESS - - check(hsa.hsa_amd_memory_pool_get_info(mem_pool, hsa.HSA_AMD_MEMORY_POOL_INFO_SIZE, ctypes.byref(sz := ctypes.c_size_t()))) - if sz.value == 0: return hsa.HSA_STATUS_SUCCESS - - ret = ctypes.cast(data, ctypes.POINTER(hsa.hsa_amd_memory_pool_t)) - ret[0] = mem_pool - return hsa.HSA_STATUS_INFO_BREAK - - hsa.hsa_amd_agent_iterate_memory_pools(agent, __filter_amd_memory_pools, ctypes.byref(region := hsa.hsa_amd_memory_pool_t())) - return region diff --git a/tinygrad/extra/backends/hsa_graph.py b/tinygrad/extra/backends/hsa_graph.py deleted file mode 100644 index aced2c02..00000000 --- a/tinygrad/extra/backends/hsa_graph.py +++ /dev/null @@ -1,171 +0,0 @@ -import ctypes, collections, time, itertools -from typing import List, Any, Dict, cast, Optional, Tuple -from tinygrad.helpers import init_c_var, round_up -from tinygrad.device import Buffer, BufferSpec -from tinygrad.device import Compiled, Device -from tinygrad.uop.ops import Variable -from tinygrad.runtime.ops_hsa import HSADevice, PROFILE, Profiler -from tinygrad.engine.realize import ExecItem, BufferXfer, CompiledRunner -from tinygrad.engine.jit import MultiGraphRunner, GraphException -import tinygrad.runtime.autogen.hsa as hsa -from tinygrad.runtime.support.hsa import check, AQLQueue, AQL_PACKET_SIZE, EMPTY_SIGNAL - -def dedup_signals(signals): return [hsa.hsa_signal_t(hndl) for hndl in set([x.handle for x in signals if isinstance(x, hsa.hsa_signal_t)])] - -class VirtAQLQueue(AQLQueue): - def __init__(self, device, sz): - self.device = device - self.virt_queue = (hsa.hsa_kernel_dispatch_packet_t * sz)() - self.queue_base = self.write_addr = ctypes.addressof(self.virt_queue) - self.packets_count = 0 - self.available_packet_slots = sz - def _wait_queue(self, need_packets=1): assert False, f"VirtQueue is too small to handle {self.packets_count+need_packets} packets!" - def _submit_packet(self): - self.write_addr += AQL_PACKET_SIZE - self.packets_count += 1 - self.available_packet_slots -= 1 - -class HSAGraph(MultiGraphRunner): - def __init__(self, jit_cache: List[ExecItem], input_rawbuffers: List[Buffer], var_vals: Dict[Variable, int]): - super().__init__(jit_cache, input_rawbuffers, var_vals) - - # Check all jit items are compatible. - compiled_devices = set() - for ji in self.jit_cache: - if isinstance(ji.prg, CompiledRunner): compiled_devices.add(ji.prg.dev) - elif isinstance(ji.prg, BufferXfer): - for x in ji.bufs[0:2]: compiled_devices.add(Device[cast(Buffer, x).device]) - else: raise GraphException - if any(not isinstance(d, HSADevice) for d in compiled_devices): raise GraphException - - self.devices: List[HSADevice] = list(compiled_devices) #type:ignore - - # Allocate kernel args. - kernargs_size: Dict[Compiled, int] = collections.defaultdict(int) - for ji in self.jit_cache: - if isinstance(ji.prg, CompiledRunner): kernargs_size[ji.prg.dev] += round_up(ctypes.sizeof(ji.prg._prg.args_struct_t), 16) - kernargs_ptrs: Dict[Compiled, int] = {dev:dev.allocator._alloc(sz, BufferSpec()) for dev,sz in kernargs_size.items()} - - # Fill initial arguments. - self.ji_kargs_structs: Dict[int, ctypes.Structure] = {} - for j,ji in enumerate(self.jit_cache): - if not isinstance(ji.prg, CompiledRunner): continue - self.ji_kargs_structs[j] = ji.prg._prg.args_struct_t.from_address(kernargs_ptrs[ji.prg.dev]) - kernargs_ptrs[ji.prg.dev] += round_up(ctypes.sizeof(ji.prg._prg.args_struct_t), 16) - for i in range(len(ji.bufs)): self.ji_kargs_structs[j].__setattr__(f'f{i}', cast(Buffer, ji.bufs[i])._buf) - for i in range(len(ji.prg.p.vars)): self.ji_kargs_structs[j].__setattr__(f'v{i}', var_vals[ji.prg.p.vars[i]]) - - # Build queues. - self.virt_aql_queues: Dict[Compiled, VirtAQLQueue] = {dev:VirtAQLQueue(dev, 2*len(self.jit_cache)+16) for dev in self.devices} - self.packets = {} - self.transfers = [] - self.ji_to_transfer: Dict[int, int] = {} # faster to store transfers as list and update using this mapping table. - self.signals_to_reset: List[hsa.hsa_signal_t] = [] - self.signals_to_devices: Dict[ctypes.c_uint64, List[HSADevice]] = {} - self.profile_info: Dict[Compiled, List[Tuple[Any, ...]]] = collections.defaultdict(list) - - # Special packet to wait for the world. - self.kickoff_signals: Dict[HSADevice, hsa.hsa_signal_t] = {dev:self.alloc_signal(reset_on_start=True) for dev in self.devices} - for dev in self.devices: self.virt_aql_queues[dev].submit_barrier([], self.kickoff_signals[dev]) - - for j,ji in enumerate(self.jit_cache): - if isinstance(ji.prg, CompiledRunner): - wait_signals = self.access_resources(ji.bufs, ji.prg.p.outs, new_dependency=j, sync_with_aql_packets=False) - for i in range(0, len(wait_signals), 5): - self.virt_aql_queues[ji.prg.dev].submit_barrier(wait_signals[i:i+5]) - self.packets[j] = hsa.hsa_kernel_dispatch_packet_t.from_address(self.virt_aql_queues[ji.prg.dev].write_addr) - - sync_signal = self.alloc_signal(reset_on_start=True) if PROFILE else None - self.virt_aql_queues[ji.prg.dev].submit_kernel(ji.prg._prg, *ji.prg.p.launch_dims(var_vals), #type:ignore - ctypes.addressof(self.ji_kargs_structs[j]), completion_signal=sync_signal) - if PROFILE: self.profile_info[ji.prg.dev].append((sync_signal, ji.prg._prg.name, False)) - elif isinstance(ji.prg, BufferXfer): - dest, src = [cast(Buffer, x) for x in ji.bufs[0:2]] - dest_dev, src_dev = cast(HSADevice, Device[dest.device]), cast(HSADevice, Device[src.device]) - sync_signal = self.alloc_signal(reset_on_start=True, wait_on=[dest_dev, src_dev]) - - wait_signals = self.access_resources([dest, src], write=[0], new_dependency=sync_signal, sync_with_aql_packets=True) - self.transfers.append([dest._buf, dest_dev.agent, src._buf, src_dev.agent, dest.nbytes, len(wait_signals), - (hsa.hsa_signal_t*len(wait_signals))(*wait_signals), sync_signal, hsa.HSA_AMD_SDMA_ENGINE_0, True]) - self.ji_to_transfer[j] = len(self.transfers) - 1 - if PROFILE: self.profile_info[src_dev].append((sync_signal, f"transfer: HSA:{src_dev.device_id} -> HSA:{dest_dev.device_id}", True)) - - # Wait for all active signals to finish the graph - wait_signals_to_finish: Dict[HSADevice, List[hsa.hsa_signal_t]] = collections.defaultdict(list) - for v in dedup_signals(list(self.w_dependency_map.values()) + list(itertools.chain.from_iterable(self.r_dependency_map.values()))): - for dev in self.signals_to_devices[v.handle]: - wait_signals_to_finish[dev].append(v) - - self.finish_signal = init_c_var(hsa.hsa_signal_t(), lambda x: check(hsa.hsa_amd_signal_create(1, 0, None, 0, ctypes.byref(x)))) - for dev in self.devices: - wait_signals = wait_signals_to_finish[dev] - for i in range(0, max(1, len(wait_signals)), 5): - self.virt_aql_queues[dev].submit_barrier(wait_signals[i:i+5], completion_signal=self.finish_signal if i+5>=len(wait_signals) else None) - - # Zero signals to allow graph to start and execute. - for sig in self.signals_to_reset: hsa.hsa_signal_silent_store_relaxed(sig, 0) - hsa.hsa_signal_silent_store_relaxed(self.finish_signal, 0) - - def __call__(self, input_rawbuffers: List[Buffer], var_vals: Dict[Variable, int], wait=False) -> Optional[float]: - # Wait and restore signals - hsa.hsa_signal_wait_scacquire(self.finish_signal, hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - for sig in self.signals_to_reset: hsa.hsa_signal_silent_store_relaxed(sig, 1) - hsa.hsa_signal_silent_store_relaxed(self.finish_signal, len(self.devices)) - - # Update rawbuffers - for (j,i),input_idx in self.input_replace.items(): - if j in self.ji_kargs_structs: - self.ji_kargs_structs[j].__setattr__(f'f{i}', input_rawbuffers[input_idx]._buf) - else: - if i == 0: self.transfers[self.ji_to_transfer[j]][0] = input_rawbuffers[input_idx]._buf # dest - elif i == 1: self.transfers[self.ji_to_transfer[j]][2] = input_rawbuffers[input_idx]._buf # src - - # Update var_vals - for j in self.jc_idx_with_updatable_var_vals: - for i,v in enumerate(cast(CompiledRunner, self.jit_cache[j].prg).p.vars): - self.ji_kargs_structs[j].__setattr__(f'v{i}', var_vals[v]) - - # Update launch dims - for j in self.jc_idx_with_updatable_launch_dims: - gl, lc = cast(CompiledRunner, self.jit_cache[j].prg).p.launch_dims(var_vals) - self.packets[j].workgroup_size_x = lc[0] - self.packets[j].workgroup_size_y = lc[1] - self.packets[j].workgroup_size_z = lc[2] - self.packets[j].grid_size_x = gl[0] * lc[0] - self.packets[j].grid_size_y = gl[1] * lc[1] - self.packets[j].grid_size_z = gl[2] * lc[2] - - for dev in self.devices: - dev.flush_hdp() - dev.hw_queue.blit_packets(self.virt_aql_queues[dev].queue_base, self.virt_aql_queues[dev].packets_count) - - for transfer_data in self.transfers: - check(hsa.hsa_amd_memory_async_copy_on_engine(*transfer_data)) - - et = None - if wait: - st = time.perf_counter() - hsa.hsa_signal_wait_scacquire(self.finish_signal, hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - et = time.perf_counter() - st - - for profdev,profdata in self.profile_info.items(): Profiler.tracked_signals[profdev] += profdata - return et - - def alloc_signal(self, reset_on_start=False, wait_on=None): - sync_signal = init_c_var(hsa.hsa_signal_t(), lambda x: check(hsa.hsa_amd_signal_create(1, 0, None, 0, ctypes.byref(x)))) - if reset_on_start: self.signals_to_reset.append(sync_signal) - if wait_on is not None: self.signals_to_devices[sync_signal.handle] = wait_on - return sync_signal - - def dependency_as_signal(self, dep, sync_with_aql_packets) -> Optional[hsa.hsa_signal_t]: - if isinstance(dep, hsa.hsa_signal_t): return dep - elif sync_with_aql_packets and isinstance(packet := self.packets.get(dep), hsa.hsa_kernel_dispatch_packet_t): - if packet.completion_signal.handle == EMPTY_SIGNAL.handle: packet.completion_signal = self.alloc_signal(reset_on_start=True) - return packet.completion_signal - return None - - def access_resources(self, rawbufs, write, new_dependency, sync_with_aql_packets=False): - rdeps = self._access_resources(rawbufs, write, new_dependency) - wait_signals = [self.dependency_as_signal(dep, sync_with_aql_packets=sync_with_aql_packets) for dep in rdeps] - if sync_with_aql_packets: wait_signals += [self.kickoff_signals[cast(HSADevice, Device[rawbuf.device])] for rawbuf in rawbufs] - return dedup_signals(wait_signals) diff --git a/tinygrad/extra/backends/ops_hsa.py b/tinygrad/extra/backends/ops_hsa.py deleted file mode 100644 index 3b2fcc9a..00000000 --- a/tinygrad/extra/backends/ops_hsa.py +++ /dev/null @@ -1,275 +0,0 @@ -from __future__ import annotations -import ctypes, functools, subprocess, io, atexit, collections, json -from typing import Tuple, TypeVar, List, Dict, Any -import tinygrad.runtime.autogen.hsa as hsa -from tinygrad.helpers import DEBUG, init_c_var, from_mv, round_up, to_mv, init_c_struct_t, getenv, PROFILE -from tinygrad.device import Compiled, Compiler, CompileError, BufferSpec, LRUAllocator -from tinygrad.renderer.cstyle import HIPRenderer -from tinygrad.runtime.support.hsa import check, scan_agents, find_memory_pool, AQLQueue -from tinygrad.runtime.support.hip_comgr import compile_hip -if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 - -class HSAProfiler: - def __init__(self): - self.tracked_signals = collections.defaultdict(list) - self.collected_events: List[Tuple[Any, ...]] = [] - self.copy_timings = hsa.hsa_amd_profiling_async_copy_time_t() - self.disp_timings = hsa.hsa_amd_profiling_dispatch_time_t() - - def track(self, signal, device, name, is_copy=False): self.tracked_signals[device].append((signal, name, is_copy)) - def process(self, device): - # Process all tracked signals, should be called before any of tracked signals are reused. - for sig,name,is_copy in self.tracked_signals[device]: - if is_copy: check(hsa.hsa_amd_profiling_get_async_copy_time(sig, ctypes.byref(timings := self.copy_timings))) - else: check(hsa.hsa_amd_profiling_get_dispatch_time(device.agent, sig, ctypes.byref(timings := self.disp_timings))) #type:ignore - self.collected_events.append((device.device_id, 1 if is_copy else 0, name, timings.start, timings.end)) - self.tracked_signals.pop(device) - - def save(self, path): - mjson = [] - for i in range(len(HSADevice.devices)): - mjson.append({"name": "process_name", "ph": "M", "pid": i, "args": {"name": "HSA"}}) - mjson.append({"name": "thread_name", "ph": "M", "pid": i, "tid": 0, "args": {"name": "AQL"}}) - mjson.append({"name": "thread_name", "ph": "M", "pid": i, "tid": 1, "args": {"name": "SDMA"}}) - - for dev_id,queue_id,name,st,et in self.collected_events: - mjson.append({"name": name, "ph": "B", "pid": dev_id, "tid": queue_id, "ts": st*1e-3}) - mjson.append({"name": name, "ph": "E", "pid": dev_id, "tid": queue_id, "ts": et*1e-3}) - with open(path, "w") as f: f.write(json.dumps({"traceEvents": mjson})) - print(f"Saved HSA profile to {path}") -Profiler = HSAProfiler() - -class HSACompiler(Compiler): - def __init__(self, arch:str): - self.arch = arch - super().__init__(f"compile_hip_{self.arch}") - def compile(self, src:str) -> bytes: - try: return compile_hip(src, self.arch) - except RuntimeError as e: raise CompileError(e) - -class HSAProgram: - def __init__(self, device:HSADevice, name:str, lib:bytes): - self.device, self.name, self.lib = device, name, lib - - if DEBUG >= 6: - asm = subprocess.check_output(["/opt/rocm/llvm/bin/llvm-objdump", '-d', '-'], input=lib) - print('\n'.join([x for x in asm.decode('utf-8').split("\n") if 's_code_end' not in x])) - - self.exec = init_c_var(hsa.hsa_executable_t(), lambda x: check(hsa.hsa_executable_create_alt(hsa.HSA_PROFILE_FULL, hsa.HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT, None, ctypes.byref(x)))) # noqa: E501 - self.code_reader = init_c_var(hsa.hsa_code_object_reader_t(), - lambda x: check(hsa.hsa_code_object_reader_create_from_memory(lib, len(lib), ctypes.byref(x)))) - check(hsa.hsa_executable_load_agent_code_object(self.exec, self.device.agent, self.code_reader, None, None)) - check(hsa.hsa_executable_freeze(self.exec, None)) - - self.kernel = init_c_var(hsa.hsa_executable_symbol_t(), lambda x: check(hsa.hsa_executable_get_symbol_by_name(self.exec, (name+".kd").encode("utf-8"), ctypes.byref(self.device.agent), ctypes.byref(x)))) # noqa: E501 - self.handle = init_c_var(ctypes.c_uint64(), lambda x: check(hsa.hsa_executable_symbol_get_info(self.kernel, hsa.HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT, ctypes.byref(x)))) # noqa: E501 - self.kernargs_segment_size = init_c_var(ctypes.c_uint32(), lambda x: check(hsa.hsa_executable_symbol_get_info(self.kernel, hsa.HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE, ctypes.byref(x)))).value # noqa: E501 - self.group_segment_size = init_c_var(ctypes.c_uint32(), lambda x: check(hsa.hsa_executable_symbol_get_info(self.kernel, hsa.HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE, ctypes.byref(x)))).value # noqa: E501 - self.private_segment_size = init_c_var(ctypes.c_uint32(), lambda x: check(hsa.hsa_executable_symbol_get_info(self.kernel, hsa.HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE, ctypes.byref(x)))).value # noqa: E501 - - def __del__(self): - self.device.synchronize() - if hasattr(self, 'code_reader'): check(hsa.hsa_code_object_reader_destroy(self.code_reader)) - if hasattr(self, 'exec'): check(hsa.hsa_executable_destroy(self.exec)) - - def __call__(self, *args, global_size:Tuple[int,int,int]=(1,1,1), local_size:Tuple[int,int,int]=(1,1,1), vals:Tuple[int, ...]=(), wait=False): - if not hasattr(self, "args_struct_t"): - self.args_struct_t = init_c_struct_t(tuple([(f'f{i}', ctypes.c_void_p) for i in range(len(args))] + - [(f'v{i}', ctypes.c_int) for i in range(len(vals))])) - if ctypes.sizeof(self.args_struct_t) != self.kernargs_segment_size: - raise RuntimeError(f"HSAProgram.__call__: incorrect args struct size {ctypes.sizeof(self.args_struct_t)} != {self.kernargs_segment_size}") - - kernargs = None - if self.kernargs_segment_size > 0: - kernargs = self.device.alloc_kernargs(self.kernargs_segment_size) - args_st = self.args_struct_t.from_address(kernargs) - for i in range(len(args)): args_st.__setattr__(f'f{i}', args[i]) - for i in range(len(vals)): args_st.__setattr__(f'v{i}', vals[i]) - self.device.flush_hdp() - - signal = self.device.alloc_signal(reusable=True) if wait or PROFILE else None - self.device.hw_queue.submit_kernel(self, global_size, local_size, kernargs, completion_signal=signal) - if PROFILE: Profiler.track(signal, self.device, self.name) - if wait: - hsa.hsa_signal_wait_scacquire(signal, hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - check(hsa.hsa_amd_profiling_get_dispatch_time(self.device.agent, signal, ctypes.byref(timings := hsa.hsa_amd_profiling_dispatch_time_t()))) - return (timings.end - timings.start) * self.device.clocks_to_time - -T = TypeVar("T") -CHUNK_SIZE, PAGE_SIZE = 256*1024*1024, 0x1000 -class HSAAllocator(LRUAllocator): - def __init__(self, device:HSADevice): - self.device = device - super().__init__() - - def _alloc(self, size:int, options:BufferSpec): - if options.host: - check(hsa.hsa_amd_memory_pool_allocate(HSADevice.cpu_mempool, size, 0, ctypes.byref(mem := ctypes.c_void_p()))) - check(hsa.hsa_amd_agents_allow_access(2, (hsa.hsa_agent_t*2)(HSADevice.cpu_agent, self.device.agent), None, mem)) - return mem.value - c_agents = (hsa.hsa_agent_t * len(HSADevice.agents[hsa.HSA_DEVICE_TYPE_GPU]))(*HSADevice.agents[hsa.HSA_DEVICE_TYPE_GPU]) - check(hsa.hsa_amd_memory_pool_allocate(self.device.gpu_mempool, size, 0, ctypes.byref(buf := ctypes.c_void_p()))) - check(hsa.hsa_amd_agents_allow_access(len(HSADevice.agents[hsa.HSA_DEVICE_TYPE_GPU]), c_agents, None, buf)) - return buf.value - - def _free(self, opaque:T, options:BufferSpec): - HSADevice.synchronize_system() - check(hsa.hsa_amd_memory_pool_free(opaque)) - - def _copyin(self, dest:T, src: memoryview): - # Async copyin sync model uses barriers on the main hw queue, since barriers are guaranteed to execute in order with all other packets. - self.device.hw_queue.submit_barrier([], sync_signal := self.device.alloc_signal(reusable=True)) - mem = self._alloc(src.nbytes, BufferSpec(host=True)) - ctypes.memmove(mem, from_mv(src), src.nbytes) - check(hsa.hsa_amd_memory_async_copy_on_engine(dest, self.device.agent, mem, HSADevice.cpu_agent, src.nbytes, 1, ctypes.byref(sync_signal), - copy_signal := self.device.alloc_signal(reusable=True), hsa.HSA_AMD_SDMA_ENGINE_0, True)) - self.device.hw_queue.submit_barrier([copy_signal]) - self.device.delayed_free.append(mem) - if PROFILE: Profiler.track(copy_signal, self.device, f"copyin: CPU -> HSA:{self.device.device_id}", is_copy=True) - - def copy_from_fd(self, dest, fd, offset, size): - self.device.hw_queue.submit_barrier([], sync_signal := self.device.alloc_signal(reusable=True)) - - if not hasattr(self, 'hb'): - self.hb = [self._alloc(CHUNK_SIZE, BufferSpec(host=True)) for _ in range(2)] - self.hb_signals = [self.device.alloc_signal(reusable=False) for _ in range(2)] - self.hb_polarity = 0 - self.sdma = [hsa.HSA_AMD_SDMA_ENGINE_0, hsa.HSA_AMD_SDMA_ENGINE_1] - for sig in self.hb_signals: hsa.hsa_signal_store_relaxed(sig, 0) - - fo = io.FileIO(fd, "a+b", closefd=False) - fo.seek(offset - (minor_offset:=offset % PAGE_SIZE)) - - copies_called = 0 - copied_in = 0 - for local_offset in range(0, size+minor_offset, CHUNK_SIZE): - local_size = min(round_up(size+minor_offset, PAGE_SIZE)-local_offset, CHUNK_SIZE) - copy_size = min(local_size-minor_offset, size-copied_in) - if copy_size == 0: break - - hsa.hsa_signal_wait_scacquire(self.hb_signals[self.hb_polarity], hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - self.device.reusable_signals.append(self.hb_signals[self.hb_polarity]) # it's free now and can be reused - self.hb_signals[self.hb_polarity] = self.device.alloc_signal(reusable=False) - - fo.readinto(to_mv(self.hb[self.hb_polarity], local_size)) - check(hsa.hsa_amd_memory_async_copy_on_engine(dest+copied_in, self.device.agent, self.hb[self.hb_polarity]+minor_offset, HSADevice.cpu_agent, - copy_size, 1, ctypes.byref(sync_signal), self.hb_signals[self.hb_polarity], - self.sdma[self.hb_polarity], True)) - copied_in += copy_size - self.hb_polarity = (self.hb_polarity + 1) % len(self.hb) - minor_offset = 0 # only on the first - copies_called += 1 - - wait_signals = [self.hb_signals[self.hb_polarity - 1]] - if copies_called > 1: wait_signals.append(self.hb_signals[self.hb_polarity]) - self.device.hw_queue.submit_barrier(wait_signals) - - def _copyout(self, dest:memoryview, src:T): - HSADevice.synchronize_system() - copy_signal = self.device.alloc_signal(reusable=True) - c_agents = (hsa.hsa_agent_t*2)(self.device.agent, HSADevice.cpu_agent) - check(hsa.hsa_amd_memory_lock_to_pool(from_mv(dest), dest.nbytes, c_agents, 2, HSADevice.cpu_mempool, 0, ctypes.byref(addr:=ctypes.c_void_p()))) - check(hsa.hsa_amd_memory_async_copy(addr, HSADevice.cpu_agent, src, self.device.agent, dest.nbytes, 0, None, copy_signal)) - hsa.hsa_signal_wait_scacquire(copy_signal, hsa.HSA_SIGNAL_CONDITION_LT, 1, (1 << 64) - 1, hsa.HSA_WAIT_STATE_ACTIVE) - check(hsa.hsa_amd_memory_unlock(from_mv(dest))) - if PROFILE: Profiler.track(copy_signal, self.device, f"copyout: HSA:{self.device.device_id} -> CPU", is_copy=True) - - def transfer(self, dest:T, src:T, sz:int, src_dev=None, dest_dev=None): - src_dev.hw_queue.submit_barrier([], sync_signal_1 := src_dev.alloc_signal(reusable=True)) - dest_dev.hw_queue.submit_barrier([], sync_signal_2 := dest_dev.alloc_signal(reusable=True)) - c_wait_signal = (hsa.hsa_signal_t*2)(sync_signal_1, sync_signal_2) - check(hsa.hsa_amd_memory_async_copy_on_engine(dest, dest_dev.agent, src, src_dev.agent, sz, 2, c_wait_signal, - copy_signal := dest_dev.alloc_signal(reusable=False), hsa.HSA_AMD_SDMA_ENGINE_0, True)) - src_dev.hw_queue.submit_barrier([copy_signal]) - dest_dev.hw_queue.submit_barrier([copy_signal]) - if PROFILE: Profiler.track(copy_signal, src_dev, f"transfer: HSA:{src_dev.device_id} -> HSA:{dest_dev.device_id}", is_copy=True) - -class HSADevice(Compiled): - devices: List[HSADevice] = [] - agents: Dict[int, List[hsa.hsa_agent_t]] = {} - cpu_agent: hsa.hsa_agent_t - cpu_mempool: hsa.hsa_amd_memory_pool_t - def __init__(self, device:str=""): - if not HSADevice.agents: - check(hsa.hsa_init()) - atexit.register(hsa_terminate) - HSADevice.agents = scan_agents() - HSADevice.cpu_agent = HSADevice.agents[hsa.HSA_DEVICE_TYPE_CPU][0] - HSADevice.cpu_mempool = find_memory_pool(HSADevice.cpu_agent, segtyp=hsa.HSA_AMD_SEGMENT_GLOBAL, location=hsa.HSA_AMD_MEMORY_POOL_LOCATION_CPU) - if PROFILE: check(hsa.hsa_amd_profiling_async_copy_enable(1)) - - self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.agent = HSADevice.agents[hsa.HSA_DEVICE_TYPE_GPU][self.device_id] - self.gpu_mempool = find_memory_pool(self.agent, segtyp=hsa.HSA_AMD_SEGMENT_GLOBAL, location=hsa.HSA_AMD_MEMORY_POOL_LOCATION_GPU) - self.hw_queue = AQLQueue(self) - HSADevice.devices.append(self) - - check(hsa.hsa_agent_get_info(self.agent, hsa.HSA_AGENT_INFO_NAME, ctypes.byref(agent_name_buf := ctypes.create_string_buffer(256)))) - self.arch = ctypes.string_at(agent_name_buf).decode() - - check(hsa.hsa_system_get_info(hsa.HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY, ctypes.byref(gpu_freq := ctypes.c_uint64()))) - self.clocks_to_time: float = 1 / gpu_freq.value - - check(hsa.hsa_agent_get_info(self.agent, hsa.HSA_AMD_AGENT_INFO_HDP_FLUSH, ctypes.byref(hdp_flush := hsa.hsa_amd_hdp_flush_t()))) - self.hdp_flush = hdp_flush - - self.delayed_free: List[int] = [] - self.reusable_signals: List[hsa.hsa_signal_t] = [] - - from tinygrad.runtime.graph.hsa import HSAGraph - super().__init__(device, HSAAllocator(self), HIPRenderer(), HSACompiler(self.arch), functools.partial(HSAProgram, self), HSAGraph) - - # Finish init: preallocate some signals + space for kernargs - self.signal_pool = [init_c_var(hsa.hsa_signal_t(), lambda x: check(hsa.hsa_signal_create(1, 0, None, ctypes.byref(x)))) for _ in range(4096)] - self._new_kernargs_region(16 << 20) # initial region size is 16mb - - def synchronize(self): - self.hw_queue.wait() - - for sig in self.reusable_signals: hsa.hsa_signal_silent_store_relaxed(sig, 1) - self.signal_pool.extend(self.reusable_signals) - self.reusable_signals.clear() - - for opaque_to_free in self.delayed_free: check(hsa.hsa_amd_memory_pool_free(opaque_to_free)) - self.delayed_free.clear() - - self.kernarg_next_addr = self.kernarg_start_addr - Profiler.process(self) - - @staticmethod - def synchronize_system(): - for d in HSADevice.devices: d.synchronize() - - def alloc_signal(self, reusable=False): - if len(self.signal_pool): signal = self.signal_pool.pop() - else: check(hsa.hsa_amd_signal_create(1, 0, None, 0, ctypes.byref(signal := hsa.hsa_signal_t()))) - - # reusable means a signal could be reused after synchronize for the device it's allocated from is called. - if reusable: self.reusable_signals.append(signal) - return signal - - def alloc_kernargs(self, sz): - if self.kernarg_next_addr + sz >= self.kernarg_start_addr + self.kernarg_pool_sz: self._new_kernargs_region(int(self.kernarg_pool_sz * 2)) - result = self.kernarg_next_addr - self.kernarg_next_addr = round_up(self.kernarg_next_addr + sz, 16) - return result - - def _new_kernargs_region(self, sz:int): - if hasattr(self, 'kernarg_start_addr'): self.delayed_free.append(self.kernarg_start_addr) - self.kernarg_start_addr: int = self.allocator._alloc(sz, BufferSpec()) - self.kernarg_next_addr = self.kernarg_start_addr - self.kernarg_pool_sz: int = sz - - def flush_hdp(self): self.hdp_flush.HDP_MEM_FLUSH_CNTL[0] = 1 - -def hsa_terminate(): - # Need to stop/delete aql queue before hsa shut down, this leads to gpu hangs. - for dev in HSADevice.devices: - Profiler.process(dev) - del dev.hw_queue - - # hsa_shut_down cleans up all hsa-related resources. - hsa.hsa_shut_down() - HSADevice.synchronize = lambda: None #type:ignore - HSAProgram.__del__ = lambda _: None #type:ignore - if Profiler.collected_events: Profiler.save("/tmp/profile.json") diff --git a/tinygrad/extra/backends/rdna.py b/tinygrad/extra/backends/rdna.py deleted file mode 100644 index 1e26e977..00000000 --- a/tinygrad/extra/backends/rdna.py +++ /dev/null @@ -1,127 +0,0 @@ -from typing import Dict, Set -import yaml -from tinygrad.codegen.uops import UOpGraph, UOps, UOp -from tinygrad.uop.ops import BinaryOps -from tinygrad.dtype import dtypes - -def uops_to_rdna(function_name:str, uops:UOpGraph) -> str: - replace: Dict[UOp, UOp] = {} - seen: Set[UOp] = set() - for u in uops: - if u in seen: continue - seen.add(u) - for o,n in replace.items(): - if o in u.vin and u is not n: - u.vin = tuple(n if x == o else x for x in u.vin) - # pointer indexing - if u.uop in {UOps.LOAD, UOps.STORE} and u.vin[0].dtype.itemsize > 1: - val = UOp(UOps.CONST, dtypes.int, tuple(), arg=u.vin[0].dtype.itemsize, insert_before=uops.uops.index(u)) - ptr = UOp(UOps.ALU, dtypes.int, (u.vin[1], val), arg=BinaryOps.MUL, insert_before=uops.uops.index(u)) - u.vin = (u.vin[0], ptr) + u.vin[2:] - #uops.print() - - args = [] - ins = [] - - v_cnt = 3 # v[0:2] is local_xyz - s_cnt = 5 # s[0:1] is the address, s[2:4] is global_xyz - - r: Dict[UOp, str] = {} - for u in uops: - if u.uop == UOps.SPECIAL: - if u.arg[1].startswith("lidx"): - r[u] = f'v{u.arg[0]}' - elif u.arg[1].startswith("gidx"): - r[u] = f's{2+u.arg[0]}' - else: - raise NotImplementedError - elif u.uop == UOps.CONST: - #r[u] = u.arg - - # TODO: sometimes we can use s - #r[u] = f"s{s_cnt}" - #s_cnt += 1 - #ins.append(f"s_mov_b32 {r[u]}, {u.arg}") - - r[u] = f"v{v_cnt}" - v_cnt += 1 - ins.append(f"v_mov_b32 {r[u]}, {u.arg}") - elif u.uop == UOps.ALU: - if u.arg == BinaryOps.ADD: - r[u] = f"v{v_cnt}" - v_cnt += 1 - ins.append(f"v_add_f32_e32 {r[u]}, {r[u.vin[0]]}, {r[u.vin[1]]}") - elif u.arg == BinaryOps.MUL: - r[u] = f"v{v_cnt}" - v_cnt += 1 - if dtypes.is_float(u.dtype): - ins.append(f"v_mul_f32_e32 {r[u]}, {r[u.vin[0]]}, {r[u.vin[1]]}") - else: - ins.append(f"v_mul_u32_u24 {r[u]}, {r[u.vin[0]]}, {r[u.vin[1]]}") - else: - raise NotImplementedError - elif u.uop == UOps.LOAD: - r[u] = f"v{v_cnt}" - v_cnt += 1 - ins.append(f"global_load_b32 {r[u]}, {r[u.vin[1]]}, {r[u.vin[0]]}") - ins.append("s_waitcnt vmcnt(0)") - elif u.uop == UOps.STORE: - ins.append(f"global_store_b32 {r[u.vin[1]]}, {r[u.vin[2]]}, {r[u.vin[0]]}") - elif u.uop == UOps.DEFINE_GLOBAL: - i = u.arg[0] - args.append({'.address_space': 'global', '.name': f'buf_{i}', '.offset': i*8, '.size': 8, - '.type_name': u.dtype.name+"*", '.value_kind': 'global_buffer'}) - s_cnt += s_cnt%2 # skip - r[u] = f"s[{s_cnt}:{s_cnt+1}]" - s_cnt += 2 - ins.append(f"s_load_b64 {r[u]}, s[0:1], {i*8}") - ins.append("s_waitcnt lgkmcnt(0)") - else: - raise NotImplementedError(f"can't render {u.uop}") - - # *** boilerplate rendering *** - - metadata = { - 'amdhsa.kernels': [{'.args': args, - '.group_segment_fixed_size': 0, '.kernarg_segment_align': 8, '.kernarg_segment_size': args[-1][".offset"] + args[-1][".size"], - '.language': 'OpenCL C', '.language_version': [1, 2], '.max_flat_workgroup_size': 256, - '.name': function_name, '.private_segment_fixed_size': 0, '.sgpr_count': s_cnt, '.sgpr_spill_count': 0, - '.symbol': f'{function_name}.kd', '.uses_dynamic_stack': False, '.vgpr_count': v_cnt, '.vgpr_spill_count': 0, - '.wavefront_size': 32}], - 'amdhsa.target': 'amdgcn-amd-amdhsa--gfx1100', 'amdhsa.version': [1, 2]} - - boilerplate_start = f""" -.rodata -.global {function_name}.kd -.type {function_name}.kd,STT_OBJECT -.align 0x10 -.amdhsa_kernel {function_name}""" - - kernel_desc = { - '.amdhsa_group_segment_fixed_size': 0, '.amdhsa_private_segment_fixed_size': 0, '.amdhsa_kernarg_size': 0, - '.amdhsa_next_free_vgpr': v_cnt, # this matters! - '.amdhsa_reserve_vcc': 0, '.amdhsa_reserve_xnack_mask': 0, - '.amdhsa_next_free_sgpr': s_cnt, - '.amdhsa_float_round_mode_32': 0, '.amdhsa_float_round_mode_16_64': 0, '.amdhsa_float_denorm_mode_32': 3, '.amdhsa_float_denorm_mode_16_64': 3, - '.amdhsa_dx10_clamp': 1, '.amdhsa_ieee_mode': 1, '.amdhsa_fp16_overflow': 0, - '.amdhsa_workgroup_processor_mode': 1, '.amdhsa_memory_ordered': 1, '.amdhsa_forward_progress': 0, '.amdhsa_enable_private_segment': 0, - '.amdhsa_system_sgpr_workgroup_id_x': 1, '.amdhsa_system_sgpr_workgroup_id_y': 1, '.amdhsa_system_sgpr_workgroup_id_z': 1, - '.amdhsa_system_sgpr_workgroup_info': 0, '.amdhsa_system_vgpr_workitem_id': 2, # is amdhsa_system_vgpr_workitem_id real? - '.amdhsa_exception_fp_ieee_invalid_op': 0, '.amdhsa_exception_fp_denorm_src': 0, - '.amdhsa_exception_fp_ieee_div_zero': 0, '.amdhsa_exception_fp_ieee_overflow': 0, '.amdhsa_exception_fp_ieee_underflow': 0, - '.amdhsa_exception_fp_ieee_inexact': 0, '.amdhsa_exception_int_div_zero': 0, - '.amdhsa_user_sgpr_dispatch_ptr': 0, '.amdhsa_user_sgpr_queue_ptr': 0, '.amdhsa_user_sgpr_kernarg_segment_ptr': 1, - '.amdhsa_user_sgpr_dispatch_id': 0, '.amdhsa_user_sgpr_private_segment_size': 0, '.amdhsa_wavefront_size32': 1, '.amdhsa_uses_dynamic_stack': 0} - - code_start = f""".end_amdhsa_kernel -.text -.global {function_name} -.type {function_name},@function -.p2align 8 -{function_name}: -""" - - ins += ['s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)', 's_endpgm', 's_code_end'] - return ".amdgpu_metadata\n" + yaml.dump(metadata) + ".end_amdgpu_metadata" + \ - boilerplate_start + "\n" + '\n'.join("%s %d" % x for x in kernel_desc.items()) + "\n" + code_start + \ - '\n'.join(ins) + f"\n.size {function_name}, .-{function_name}" diff --git a/tinygrad/extra/backends/triton.py b/tinygrad/extra/backends/triton.py deleted file mode 100644 index c1e81e4f..00000000 --- a/tinygrad/extra/backends/triton.py +++ /dev/null @@ -1,131 +0,0 @@ -from typing import Dict, List, Final, Callable, DefaultDict -from collections import defaultdict -from tinygrad.uop.ops import UnaryOps, BinaryOps, TernaryOps, Op -from tinygrad.helpers import DType, PtrDType, dtypes, ImageDType, DEBUG, getenv -from tinygrad.codegen.kernel import UOp, Ops -from triton.compiler import compile as triton_compile -import linecache -import math -import re - -triton_dtypes = {dtypes.double: "tl.float64", dtypes.float32: "tl.float32", dtypes.float16: "tl.float16", dtypes.bool: "tl.int1", dtypes.int8: "tl.int8", dtypes.uint8: "tl.uint8", dtypes.int32: "tl.int32", dtypes.int64: "tl.int64", dtypes.uint32: "tl.uint32", dtypes.uint64: "tl.uint64", dtypes.int16: "tl.int16", dtypes.uint16: "tl.uint16"} -signature_dtypes = {dtypes.double: "fp64",dtypes.float32: "fp32", dtypes.float16: "fp16", dtypes.bool: "i8", dtypes.int8: "i1", dtypes.uint8: "u8", dtypes.int32: "i32", dtypes.int64: "i64", dtypes.uint32: "u32", dtypes.uint64: "u64", dtypes.int16: "i16", dtypes.uint16: "u16"} - -def next_power_of_2(x): - return 1 << (x - 1).bit_length() - -def render_valid(valid): - return '(' * (len(valid) -1) + ') and '.join(valid) if len(valid) else 'True' - -#NOTE Triton requires matching dimensions for load/store, disable this and see TestOps::test_output_padded_conv_transpose2d fail to compile -def fill_dims_for_idx(idx, dims): - return "(" + idx + "+ (" + (f"0*({'+'.join(d for d in dims)})))") if len(dims) else idx - -def get_max(var): - if isinstance(var, int): return var - return re.sub(r'\[(.*?)\]', '', str(var))[1:-1] - -#NOTE can be removed after https://github.com/gpuocelot/gpuocelot/issues/8 gets resolved -def remove_single_scalar_curly_braces(ptx_code): - return '\n'.join([re.sub(r'\{\s*(%\w+)\s*\}', r'\1', line) for line in ptx_code.split('\n')]) - -def render_const(args,dtype:DType): - return (('-' if args<0 else '') + 'tl.where(1,float("inf"),0)') if math.isinf(args) else ('tl.where(1,float("nan"),0)' if math.isnan(args) else f"{int(args)}" if dtypes.is_int(dtype) else str(args)) - -def render_cast(x:str, dtype:DType, bitcast=False): - return f"{x}.to({triton_dtypes[dtype]}, bitcast={bitcast})" - -def define_scalar(local_size, dtype, args): - if len(local_size) > 0: return f"tl.full(({','.join([str(next_power_of_2(x)) for x in local_size])},),{render_const(args,dtype)}, dtype={triton_dtypes[dtype]})" - return render_const(args,dtype) - -def uops_to_triton(function_name:str, uops:List[UOp]): - local_size: List[int] = [] - depth = 1 - signatures, dims, bufs, kernel, valid = [], [], [], [], [] #type: ignore - - c: DefaultDict[str, int] = defaultdict(int) - r: Dict[UOp, str] = {} - def ssa(u, prefix="t"): - nonlocal c, r - c[prefix] += 1 - r[u]=f"{prefix}{c[prefix]-1}" - return r[u] - - child_count: DefaultDict[UOp, int] = defaultdict(int) - for ru in uops: - for v in ru.vin: - child_count[v] += 1 - - def kk(s): kernel.append(" "*depth+s) - code_for_op: Final[Dict[Op, Callable]] = { - UnaryOps.EXP2: lambda x,dtype,: f"tl.math.exp2({x})", - UnaryOps.LOG2: lambda x,dtype,: f"tl.math.log2({x})", - UnaryOps.SIN: lambda x,dtype: f"tl.sin({x})", - UnaryOps.SQRT: lambda x,dtype: f"tl.sqrt({x})", - UnaryOps.NEG: lambda x,dtype: f"-{x}", - BinaryOps.ADD: lambda x,y,dtype: f"({x}+{y})", BinaryOps.SUB: lambda x,y,: f"({x}-{y})", - BinaryOps.MUL: lambda x,y,dtype: f"({x}*{y})", BinaryOps.DIV: lambda x,y,: f"({x}/{y})" if y != '0.0' else f"{x}*tl.where({x}==0.0, float('nan'), float('inf'))", - BinaryOps.MAX: lambda x,y,dtype: f"tl.maximum({x},{y})", - BinaryOps.CMPLT: lambda x,y,dtype: f"({x}<{y})", - BinaryOps.MOD: lambda x,y,dtype: f"tl.abs({x})%tl.abs({y})*tl.where({x}<0,-1,1)", - TernaryOps.MULACC: lambda x,y,z,dtype: f"(({x}*{y})+{z})", - TernaryOps.WHERE: lambda x,y,z,dtype: f"tl.where({x},{y},{z})", - } - def int_div(x,y): return f"({x}//{y})" if y != '0' else f"{x}*tl.where({x}==0, float('nan'), float('inf'))" - for u in uops: - uop,dtype,vin,args = u.uop,u.dtype,u.vin,u.arg - if uop == Ops.LOOP: - kk(f"for {ssa(u, 'ridx')} in range({vin[0].arg}, {r[vin[1]]}):") - depth += 1 - elif uop == Ops.END: depth -= 1 - elif uop == Ops.ALU: - assert dtype is not None - val = code_for_op[args](*[r[x] for x in vin]) - if child_count[u] <=1 or dtypes.is_int(dtype): r[u] = int_div(*[r[x] for x in vin]) if args == BinaryOps.DIV and dtypes.is_int(dtype) else val - else: kk(f"{ssa(u, 'alu')} = ({val})") - elif uop == Ops.LOAD: - assert dtype is not None - if len(vin) == 2: kk(f"{ssa(u, 'val')} = {render_cast(f'tl.load({r[vin[0]]} + { fill_dims_for_idx(r[vin[1]], dims)}, mask = {render_valid(valid)})', dtype)}") - else: kk(f"{ssa(u, 'val')} = {render_cast(f'tl.where({r[vin[2]]}, tl.load({r[vin[0]]}+{fill_dims_for_idx(r[vin[1]],dims)} , mask={render_valid(valid+[r[vin[2]]])}), 0.0)', dtype)}") - elif uop == Ops.DEFINE_ACC: kk(f"{ssa(u, 'acc')} = {define_scalar(local_size, dtype, args).replace('//', '/')}") - elif uop == Ops.CONST: r[u] = define_scalar([], dtype, args) - elif uop == Ops.ASSIGN: - kk(f"{r[vin[0]]} = {r[vin[1]].replace('//', '/')}") - r[u] = r[vin[0]] - elif uop == Ops.STORE: - assert not isinstance(dtype, ImageDType), "unimplemented: image store" - kk(f"{'if '+r[vin[3]]+': ' if len(vin)>3 else ''}tl.store({r[vin[0]]} + {r[vin[1]]}, {r[vin[2]].replace('//', '/')}, mask = {render_valid(valid)}) ") - elif uop == Ops.DEFINE_GLOBAL: - bufs.append(args) - signatures.append("*" if isinstance(dtype, PtrDType) else "" + signature_dtypes[dtype]) - r[u] = args - elif uop == Ops.SPECIAL: - dims.append(args[1]) - valid.append(f"{args[1]}<{get_max(args[2])}") - if args[1].startswith("g"): kk(f"{args[1]} = tl.program_id({args[0]}) # {args[2]}") - elif args[1].startswith("l"): - kk(f"{args[1]} = tl.arange({0}, {next_power_of_2(args[2])})") - local_size.append(args[2]) - r[u] = args[1] - elif uop == Ops.CAST and dtype is not None: r[u] = render_cast(r[vin[0]], dtype, isinstance(args, tuple) and args[1]) - else: raise NotImplementedError(f"unimplemented: {uop}") - - prg = f"import triton\nimport triton.language as tl\ntl.core.TRITON_MAX_TENSOR_NUMEL = float('inf')\n@triton.jit\ndef {function_name}("+','.join(bufs)+"):\n" - for i, line in enumerate(list(filter(lambda line: "tl.arange" in line, kernel))): kernel[kernel.index(line)] += f"[{', '.join([':' if i == j else 'None' for j in range(len(local_size))])}]" - prg += "\n".join(kernel) - - acc_local_size = 1 - for x in local_size: acc_local_size *= next_power_of_2(x) - local_size = [acc_local_size] + [1] * (len(local_size) - 1) - - if DEBUG >= 4: print(prg) - getlines = linecache.getlines - linecache.getlines = lambda filename, module_globals=None: prg.splitlines(keepends=True) if "" == filename else getlines(filename, module_globals) - exec(compile(prg, "", "exec"), globals()) # pylint: disable=W0122\ - compiled = triton_compile(globals()[function_name], signature=",".join(signatures), device_type="cuda", debug=False, cc=(35 if getenv("CUDACPU", 0) else None)) - prg = remove_single_scalar_curly_braces(compiled.asm["ptx"].split(".file")[0].split(".visible .func")[0]) - max_local_size = [int(x) for x in prg.split(".maxntid ")[1].split("\n")[0].split(", ")] - for i in range(len(local_size)): local_size[i] = min(local_size[i], max_local_size[i]) - - return prg, {"shared":compiled.metadata["shared"], "local_size":local_size + [1]*(3-len(local_size))} diff --git a/tinygrad/extra/bench_log.py b/tinygrad/extra/bench_log.py deleted file mode 100644 index de5ddcb6..00000000 --- a/tinygrad/extra/bench_log.py +++ /dev/null @@ -1,110 +0,0 @@ -import time, atexit, uuid -from enum import Enum - -from tinygrad.device import Device -from tinygrad.helpers import DEBUG, ContextVar, getenv, GlobalCounters - -BENCHMARK_LOG = ContextVar("BENCHMARK_LOG", "") - -if BENCHMARK_LOG: - from influxdb_client_3 import InfluxDBClient3, Point, WriteOptions, write_client_options - from influxdb_client_3.write_client.client.write_api import WriteType - -class BenchEvent(Enum): - LOAD_WEIGHTS = "load_weights" - STEP = "step" - FULL = "full" - MLPERF_INIT = "mlperf_init" - MLPERF_RUN = "mlperf_run" -class InstantBenchEvent(Enum): - GFLOPS = "gflops" - -_events = {} -def clear_events(): - for event in BenchEvent: - _events[event] = {"wall": [], "kernel": []} - for event in InstantBenchEvent: - _events[event] = [] -clear_events() - -class WallTimeEvent: - def __init__(self, event:BenchEvent): - self.event = event - def __enter__(self): - self.start = time.monotonic() - return self - def __exit__(self, *_): - _events[self.event]["wall"].append(time.monotonic() - self.start) - return False - -class KernelTimeEvent: - def __init__(self, event:BenchEvent): - if DEBUG < 2: - raise Exception("KernelTimeEvent should only be used in DEBUG >= 2") - self.event = event - def __enter__(self): - self.start = GlobalCounters.time_sum_s - return self - def __exit__(self, *_): - _events[self.event]["kernel"].append(GlobalCounters.time_sum_s - self.start) - return False - -def log_event_instant(event:InstantBenchEvent, value:float): - _events[event].append(value) - -if BENCHMARK_LOG: - INFLUXDB_HOST = getenv("INFLUXDB_HOST", "") - INFLUXDB_ORG = getenv("INFLUXDB_ORG", "tiny") - INFLUXDB_TOKEN = getenv("INFLUXDB_TOKEN", "") - - def _create_point(run_id, i, attempt, ref, commit, name, value, run): - point = Point(BENCHMARK_LOG.value).tag("id", run_id).tag("index", i) - point = point.tag("device", Device.DEFAULT) - point = point.tag("attempt", attempt).tag("ref", ref).tag("commit", commit) - point = point.field(name, value).field("x", run) - return point - - @atexit.register - def write_events(): - # see if there are any events to write - have_events = False - for event in _events: - if isinstance(event, BenchEvent): - for event_type, values in _events[event].items(): - if len(values) > 0: - have_events = True - else: - if len(_events[event]) > 0: - have_events = True - if not have_events: - return - - # pull from github envvars - ref = getenv("GITHUB_REF_NAME", "") - commit = getenv("GITHUB_SHA", "") - run = getenv("GITHUB_RUN_NUMBER", "") - attempt = getenv("GITHUB_RUN_ATTEMPT", "") - - points = [] - for event in _events: - run_id = str(uuid.uuid4()) - if isinstance(event, BenchEvent): - for event_type, values in _events[event].items(): - for i, value in enumerate(values): - point = _create_point(run_id, i, attempt, ref, commit, f"{event.value}_{event_type}", value, run) - points.append(point) - else: - for i, value in enumerate(_events[event]): - point = _create_point(run_id, i, attempt, ref, commit, event.value, value, run) - points.append(point) - - write_options = WriteOptions(write_type=WriteType.synchronous, retry_interval=5000, max_retries=5, max_retry_delay=30000, exponential_base=2) - wco = write_client_options(write_options=write_options) - with InfluxDBClient3( - host=INFLUXDB_HOST, - org=INFLUXDB_ORG, - token=INFLUXDB_TOKEN, - auth_scheme="Basic", - database="benchmarks", - write_client_options=wco) as client: - client.write(points) diff --git a/tinygrad/extra/datasets/.gitignore b/tinygrad/extra/datasets/.gitignore deleted file mode 100644 index f106c11f..00000000 --- a/tinygrad/extra/datasets/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -imagenet -imagenet_bak -mnist -open-images-v6TEST diff --git a/tinygrad/extra/datasets/__init__.py b/tinygrad/extra/datasets/__init__.py deleted file mode 100644 index 7636e208..00000000 --- a/tinygrad/extra/datasets/__init__.py +++ /dev/null @@ -1,43 +0,0 @@ -import os, gzip, tarfile, pickle -import numpy as np -from tinygrad import Tensor, dtypes -from tinygrad.helpers import fetch - -def fetch_mnist(tensors=False): - parse = lambda file: np.frombuffer(gzip.open(file).read(), dtype=np.uint8).copy() - BASE_URL = "https://storage.googleapis.com/cvdf-datasets/mnist/" # http://yann.lecun.com/exdb/mnist/ lacks https - X_train = parse(fetch(f"{BASE_URL}train-images-idx3-ubyte.gz"))[0x10:].reshape((-1, 28*28)).astype(np.float32) - Y_train = parse(fetch(f"{BASE_URL}train-labels-idx1-ubyte.gz"))[8:].astype(np.int8) - X_test = parse(fetch(f"{BASE_URL}t10k-images-idx3-ubyte.gz"))[0x10:].reshape((-1, 28*28)).astype(np.float32) - Y_test = parse(fetch(f"{BASE_URL}t10k-labels-idx1-ubyte.gz"))[8:].astype(np.int8) - if tensors: return Tensor(X_train).reshape(-1, 1, 28, 28), Tensor(Y_train), Tensor(X_test).reshape(-1, 1, 28, 28), Tensor(Y_test) - else: return X_train, Y_train, X_test, Y_test - -cifar_mean = [0.4913997551666284, 0.48215855929893703, 0.4465309133731618] -cifar_std = [0.24703225141799082, 0.24348516474564, 0.26158783926049628] - -def fetch_cifar(): - X_train = Tensor.empty(50000, 3*32*32, device=f'disk:/tmp/cifar_train_x', dtype=dtypes.uint8) - Y_train = Tensor.empty(50000, device=f'disk:/tmp/cifar_train_y', dtype=dtypes.int64) - X_test = Tensor.empty(10000, 3*32*32, device=f'disk:/tmp/cifar_test_x', dtype=dtypes.uint8) - Y_test = Tensor.empty(10000, device=f'disk:/tmp/cifar_test_y', dtype=dtypes.int64) - - if not os.path.isfile("/tmp/cifar_extracted"): - def _load_disk_tensor(X, Y, db_list): - idx = 0 - for db in db_list: - x, y = db[b'data'], np.array(db[b'labels']) - assert x.shape[0] == y.shape[0] - X[idx:idx+x.shape[0]].assign(x) - Y[idx:idx+x.shape[0]].assign(y) - idx += x.shape[0] - assert idx == X.shape[0] and X.shape[0] == Y.shape[0] - - print("downloading and extracting CIFAR...") - fn = fetch('https://www.cs.toronto.edu/~kriz/cifar-10-python.tar.gz') - tt = tarfile.open(fn, mode='r:gz') - _load_disk_tensor(X_train, Y_train, [pickle.load(tt.extractfile(f'cifar-10-batches-py/data_batch_{i}'), encoding="bytes") for i in range(1,6)]) - _load_disk_tensor(X_test, Y_test, [pickle.load(tt.extractfile('cifar-10-batches-py/test_batch'), encoding="bytes")]) - open("/tmp/cifar_extracted", "wb").close() - - return X_train, Y_train, X_test, Y_test diff --git a/tinygrad/extra/datasets/coco.py b/tinygrad/extra/datasets/coco.py deleted file mode 100644 index 0952e377..00000000 --- a/tinygrad/extra/datasets/coco.py +++ /dev/null @@ -1,199 +0,0 @@ -import json -import pathlib -import zipfile -import numpy as np -from tinygrad.helpers import fetch -import pycocotools._mask as _mask -from examples.mask_rcnn import Masker -from pycocotools.coco import COCO -from pycocotools.cocoeval import COCOeval - -iou = _mask.iou -merge = _mask.merge -frPyObjects = _mask.frPyObjects - -BASEDIR = pathlib.Path(__file__).parent / "COCO" -BASEDIR.mkdir(exist_ok=True) - -def create_dict(key_row, val_row, rows): return {row[key_row]:row[val_row] for row in rows} - - -if not pathlib.Path(BASEDIR/'val2017').is_dir(): - fn = fetch('http://images.cocodataset.org/zips/val2017.zip') - with zipfile.ZipFile(fn, 'r') as zip_ref: - zip_ref.extractall(BASEDIR) - fn.unlink() - - -if not pathlib.Path(BASEDIR/'annotations').is_dir(): - fn = fetch('http://images.cocodataset.org/annotations/annotations_trainval2017.zip') - with zipfile.ZipFile(fn, 'r') as zip_ref: - zip_ref.extractall(BASEDIR) - fn.unlink() - -with open(BASEDIR/'annotations/instances_val2017.json', 'r') as f: - annotations_raw = json.loads(f.read()) -images = annotations_raw['images'] -categories = annotations_raw['categories'] -annotations = annotations_raw['annotations'] -file_name_to_id = create_dict('file_name', 'id', images) -id_to_width = create_dict('id', 'width', images) -id_to_height = create_dict('id', 'height', images) -json_category_id_to_contiguous_id = {v['id']: i + 1 for i, v in enumerate(categories)} -contiguous_category_id_to_json_id = {v:k for k,v in json_category_id_to_contiguous_id.items()} - - -def encode(bimask): - if len(bimask.shape) == 3: - return _mask.encode(bimask) - elif len(bimask.shape) == 2: - h, w = bimask.shape - return _mask.encode(bimask.reshape((h, w, 1), order='F'))[0] - -def decode(rleObjs): - if type(rleObjs) == list: - return _mask.decode(rleObjs) - else: - return _mask.decode([rleObjs])[:,:,0] - -def area(rleObjs): - if type(rleObjs) == list: - return _mask.area(rleObjs) - else: - return _mask.area([rleObjs])[0] - -def toBbox(rleObjs): - if type(rleObjs) == list: - return _mask.toBbox(rleObjs) - else: - return _mask.toBbox([rleObjs])[0] - - -def convert_prediction_to_coco_bbox(file_name, prediction): - coco_results = [] - try: - original_id = file_name_to_id[file_name] - if len(prediction) == 0: - return coco_results - - image_width = id_to_width[original_id] - image_height = id_to_height[original_id] - prediction = prediction.resize((image_width, image_height)) - prediction = prediction.convert("xywh") - - boxes = prediction.bbox.numpy().tolist() - scores = prediction.get_field("scores").numpy().tolist() - labels = prediction.get_field("labels").numpy().tolist() - - mapped_labels = [contiguous_category_id_to_json_id[int(i)] for i in labels] - - coco_results.extend( - [ - { - "image_id": original_id, - "category_id": mapped_labels[k], - "bbox": box, - "score": scores[k], - } - for k, box in enumerate(boxes) - ] - ) - except Exception as e: - print(file_name, e) - return coco_results - -masker = Masker(threshold=0.5, padding=1) - -def convert_prediction_to_coco_mask(file_name, prediction): - coco_results = [] - try: - original_id = file_name_to_id[file_name] - if len(prediction) == 0: - return coco_results - - image_width = id_to_width[original_id] - image_height = id_to_height[original_id] - prediction = prediction.resize((image_width, image_height)) - masks = prediction.get_field("mask") - - scores = prediction.get_field("scores").numpy().tolist() - labels = prediction.get_field("labels").numpy().tolist() - - masks = masker([masks], [prediction])[0].numpy() - - rles = [ - encode(np.array(mask[0, :, :, np.newaxis], order="F"))[0] - for mask in masks - ] - for rle in rles: - rle["counts"] = rle["counts"].decode("utf-8") - - mapped_labels = [contiguous_category_id_to_json_id[int(i)] for i in labels] - - coco_results.extend( - [ - { - "image_id": original_id, - "category_id": mapped_labels[k], - "segmentation": rle, - "score": scores[k], - } - for k, rle in enumerate(rles) - ] - ) - except Exception as e: - print(file_name, e) - return coco_results - - - -def accumulate_predictions_for_coco(coco_results, json_result_file, rm=False): - path = pathlib.Path(json_result_file) - if rm and path.exists(): path.unlink() - with open(path, "a") as f: - for s in coco_results: - f.write(json.dumps(s)) - f.write('\n') - -def remove_dup(l): - seen = set() - seen_add = seen.add - return [x for x in l if not (x in seen or seen_add(x))] - -class NpEncoder(json.JSONEncoder): - def default(self, obj): - if isinstance(obj, np.integer): - return int(obj) - if isinstance(obj, np.floating): - return float(obj) - if isinstance(obj, np.ndarray): - return obj.tolist() - return super(NpEncoder, self).default(obj) - - -def evaluate_predictions_on_coco(json_result_file, iou_type="bbox"): - coco_results = [] - with open(json_result_file, "r") as f: - for line in f: - coco_results.append(json.loads(line)) - - coco_gt = COCO(str(BASEDIR/'annotations/instances_val2017.json')) - set_of_json = remove_dup([json.dumps(d, cls=NpEncoder) for d in coco_results]) - unique_list = [json.loads(s) for s in set_of_json] - - with open(f'{json_result_file}.flattend', "w") as f: - json.dump(unique_list, f) - - coco_dt = coco_gt.loadRes(str(f'{json_result_file}.flattend')) - coco_eval = COCOeval(coco_gt, coco_dt, iou_type) - coco_eval.evaluate() - coco_eval.accumulate() - coco_eval.summarize() - return coco_eval - -def iterate(files, bs=1): - batch = [] - for file in files: - batch.append(file) - if len(batch) >= bs: yield batch; batch = [] - if len(batch) > 0: yield batch; batch = [] diff --git a/tinygrad/extra/datasets/fake_imagenet_from_mnist.py b/tinygrad/extra/datasets/fake_imagenet_from_mnist.py deleted file mode 100755 index 978bb86d..00000000 --- a/tinygrad/extra/datasets/fake_imagenet_from_mnist.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python3 -import pathlib, json -from tinygrad.helpers import trange -from extra.datasets import fetch_mnist -from PIL import Image -import numpy as np -from multiprocessing import Pool - -X_train, Y_train, X_test, Y_test = fetch_mnist() - -def act(arg): - (basedir, i, train) = arg - if train: - img = np.uint8(X_train[i]).reshape(28, 28) - nm = f"train/{Y_train[i]}/{i}.jpg" - else: - img = np.uint8(X_test[i]).reshape(28, 28) - nm = f"val/{Y_test[i]}/{i}.jpg" - Image.fromarray(img).resize((224, 224)).convert('RGB').save(basedir / nm) - -def create_fake_mnist_imagenet(basedir:pathlib.Path): - print(f"creating mock MNIST dataset at {basedir}") - basedir.mkdir(exist_ok=True) - - with (basedir / "imagenet_class_index.json").open('w') as f: - f.write(json.dumps({str(i):[str(i), str(i)] for i in range(10)})) - - for i in range(10): - (basedir / f"train/{i}").mkdir(parents=True, exist_ok=True) - (basedir / f"val/{i}").mkdir(parents=True, exist_ok=True) - - def gen(train): - for idx in trange(X_train.shape[0] if train else X_test.shape[0]): - yield (basedir, idx, train) - - with Pool(64) as p: - for _ in p.imap_unordered(act, gen(True)): pass - for _ in p.imap_unordered(act, gen(False)): pass - -if __name__ == "__main__": - create_fake_mnist_imagenet(pathlib.Path("./mnist")) \ No newline at end of file diff --git a/tinygrad/extra/datasets/imagenet.py b/tinygrad/extra/datasets/imagenet.py deleted file mode 100644 index bf7e2aad..00000000 --- a/tinygrad/extra/datasets/imagenet.py +++ /dev/null @@ -1,91 +0,0 @@ -# for imagenet download prepare.sh and run it -import glob, random, json, math -import numpy as np -from PIL import Image -import functools, pathlib -from tinygrad.helpers import diskcache, getenv - -@functools.cache -def get_imagenet_categories(): - ci = json.load(open(BASEDIR / "imagenet_class_index.json")) - return {v[0]: int(k) for k,v in ci.items()} - -if getenv("MNISTMOCK"): - BASEDIR = pathlib.Path(__file__).parent / "mnist" - - @functools.cache - def get_train_files(): - if not BASEDIR.exists(): - from extra.datasets.fake_imagenet_from_mnist import create_fake_mnist_imagenet - create_fake_mnist_imagenet(BASEDIR) - - if not (files:=glob.glob(p:=str(BASEDIR / "train/*/*"))): raise FileNotFoundError(f"No training files in {p}") - return files -else: - BASEDIR = pathlib.Path(__file__).parent / "imagenet" - - @diskcache - def get_train_files(): - if not (files:=glob.glob(p:=str(BASEDIR / "train/*/*"))): raise FileNotFoundError(f"No training files in {p}") - return files - -@functools.cache -def get_val_files(): - if not (files:=glob.glob(p:=str(BASEDIR / "val/*/*"))): raise FileNotFoundError(f"No validation files in {p}") - return files - -def image_resize(img, size, interpolation): - w, h = img.size - w_new = int((w / h) * size) if w > h else size - h_new = int((h / w) * size) if h > w else size - return img.resize([w_new, h_new], interpolation) - -def rand_flip(img): - if random.random() < 0.5: - img = np.flip(img, axis=1).copy() - return img - -def center_crop(img): - rescale = min(img.size) / 256 - crop_left = (img.width - 224 * rescale) / 2.0 - crop_top = (img.height - 224 * rescale) / 2.0 - img = img.resize((224, 224), Image.BILINEAR, box=(crop_left, crop_top, crop_left + 224 * rescale, crop_top + 224 * rescale)) - return img - -# we don't use supplied imagenet bounding boxes, so scale min is just min_object_covered -# https://github.com/tensorflow/tensorflow/blob/e193d8ea7776ef5c6f5d769b6fb9c070213e737a/tensorflow/core/kernels/image/sample_distorted_bounding_box_op.cc -def random_resized_crop(img, size, scale=(0.10, 1.0), ratio=(3/4, 4/3)): - w, h = img.size - area = w * h - - # Crop - random_solution_found = False - for _ in range(100): - aspect_ratio = random.uniform(ratio[0], ratio[1]) - max_scale = min(min(w * aspect_ratio / h, h / aspect_ratio / w), scale[1]) - target_area = area * random.uniform(scale[0], max_scale) - - w_new = int(round(math.sqrt(target_area * aspect_ratio))) - h_new = int(round(math.sqrt(target_area / aspect_ratio))) - - if 0 < w_new <= w and 0 < h_new <= h: - crop_left = random.randint(0, w - w_new) - crop_top = random.randint(0, h - h_new) - - img = img.crop((crop_left, crop_top, crop_left + w_new, crop_top + h_new)) - random_solution_found = True - break - - if not random_solution_found: - # Center crop - img = center_crop(img) - else: - # Resize - img = img.resize([size, size], Image.BILINEAR) - - return img - -def preprocess_train(img): - img = random_resized_crop(img, 224) - img = rand_flip(np.array(img)) - return img diff --git a/tinygrad/extra/datasets/imagenet_download.py b/tinygrad/extra/datasets/imagenet_download.py deleted file mode 100644 index 5c01c72f..00000000 --- a/tinygrad/extra/datasets/imagenet_download.py +++ /dev/null @@ -1,51 +0,0 @@ -# Python version of https://gist.github.com/antoinebrl/7d00d5cb6c95ef194c737392ef7e476a -from tinygrad.helpers import fetch -from pathlib import Path -from tqdm import tqdm -import tarfile, os - -def imagenet_extract(file, path, small=False): - with tarfile.open(name=file) as tar: - if small: # Show progressbar only for big files - for member in tar.getmembers(): tar.extract(path=path, member=member) - else: - for member in tqdm(iterable=tar.getmembers(), total=len(tar.getmembers())): tar.extract(path=path, member=member) - tar.close() - -def imagenet_prepare_val(): - # Read in the labels file - with open(Path(__file__).parent / "imagenet" / "imagenet_2012_validation_synset_labels.txt", 'r') as f: - labels = f.read().splitlines() - f.close() - # Get a list of images - images = os.listdir(Path(__file__).parent / "imagenet" / "val") - images.sort() - # Create folders and move files into those - for co,dir in enumerate(labels): - os.makedirs(Path(__file__).parent / "imagenet" / "val" / dir, exist_ok=True) - os.replace(Path(__file__).parent / "imagenet" / "val" / images[co], Path(__file__).parent / "imagenet" / "val" / dir / images[co]) - os.remove(Path(__file__).parent / "imagenet" / "imagenet_2012_validation_synset_labels.txt") - -def imagenet_prepare_train(): - images = os.listdir(Path(__file__).parent / "imagenet" / "train") - for co,tarf in enumerate(images): - # for each tar file found. Create a folder with its name. Extract into that folder. Remove tar file - if Path(Path(__file__).parent / "imagenet" / "train" / images[co]).is_file(): - images[co] = tarf[:-4] # remove .tar from extracted tar files - os.makedirs(Path(__file__).parent / "imagenet" / "train" / images[co], exist_ok=True) - imagenet_extract(Path(__file__).parent / "imagenet" / "train" / tarf, Path(__file__).parent/ "imagenet" / "train" / images[co], small=True) - os.remove(Path(__file__).parent / "imagenet" / "train" / tarf) - -if __name__ == "__main__": - os.makedirs(Path(__file__).parent / "imagenet", exist_ok=True) - os.makedirs(Path(__file__).parent / "imagenet" / "val", exist_ok=True) - os.makedirs(Path(__file__).parent / "imagenet" / "train", exist_ok=True) - fetch("https://raw.githubusercontent.com/raghakot/keras-vis/master/resources/imagenet_class_index.json", Path(__file__).parent / "imagenet" / "imagenet_class_index.json") - fetch("https://raw.githubusercontent.com/tensorflow/models/master/research/slim/datasets/imagenet_2012_validation_synset_labels.txt", Path(__file__).parent / "imagenet"/ "imagenet_2012_validation_synset_labels.txt") - fetch("https://image-net.org/data/ILSVRC/2012/ILSVRC2012_img_val.tar", Path(__file__).parent / "imagenet" / "ILSVRC2012_img_val.tar") # 7GB - imagenet_extract(Path(__file__).parent / "imagenet" / "ILSVRC2012_img_val.tar", Path(__file__).parent / "imagenet" / "val") - imagenet_prepare_val() - if os.getenv('IMGNET_TRAIN', None) is not None: - fetch("https://image-net.org/data/ILSVRC/2012/ILSVRC2012_img_train.tar", Path(__file__).parent / "imagenet" / "ILSVRC2012_img_train.tar") #138GB! - imagenet_extract(Path(__file__).parent / "imagenet" / "ILSVRC2012_img_train.tar", Path(__file__).parent / "imagenet" / "train") - imagenet_prepare_train() diff --git a/tinygrad/extra/datasets/kits19.py b/tinygrad/extra/datasets/kits19.py deleted file mode 100644 index f4201b5f..00000000 --- a/tinygrad/extra/datasets/kits19.py +++ /dev/null @@ -1,219 +0,0 @@ -import random -import functools -from pathlib import Path -import numpy as np -import nibabel as nib -from scipy import signal, ndimage -import os -import torch -import torch.nn.functional as F -from tqdm import tqdm -from tinygrad.tensor import Tensor -from tinygrad.helpers import fetch - -BASEDIR = Path(__file__).parent / "kits19" / "data" -TRAIN_PREPROCESSED_DIR = Path(__file__).parent / "kits19" / "preprocessed" / "train" -VAL_PREPROCESSED_DIR = Path(__file__).parent / "kits19" / "preprocessed" / "val" - -@functools.cache -def get_train_files(): - return sorted([x for x in BASEDIR.iterdir() if x.stem.startswith("case") and int(x.stem.split("_")[-1]) < 210 and x not in get_val_files()]) - -@functools.cache -def get_val_files(): - data = fetch("https://raw.githubusercontent.com/mlcommons/training/master/retired_benchmarks/unet3d/pytorch/evaluation_cases.txt").read_text() - return sorted([x for x in BASEDIR.iterdir() if x.stem.split("_")[-1] in data.split("\n")]) - -def load_pair(file_path): - image, label = nib.load(file_path / "imaging.nii.gz"), nib.load(file_path / "segmentation.nii.gz") - image_spacings = image.header["pixdim"][1:4].tolist() - image, label = image.get_fdata().astype(np.float32), label.get_fdata().astype(np.uint8) - image, label = np.expand_dims(image, 0), np.expand_dims(label, 0) - return image, label, image_spacings - -def resample3d(image, label, image_spacings, target_spacing=(1.6, 1.2, 1.2)): - if image_spacings != target_spacing: - spc_arr, targ_arr, shp_arr = np.array(image_spacings), np.array(target_spacing), np.array(image.shape[1:]) - new_shape = (spc_arr / targ_arr * shp_arr).astype(int).tolist() - image = F.interpolate(torch.from_numpy(np.expand_dims(image, axis=0)), size=new_shape, mode="trilinear", align_corners=True) - label = F.interpolate(torch.from_numpy(np.expand_dims(label, axis=0)), size=new_shape, mode="nearest") - image = np.squeeze(image.numpy(), axis=0) - label = np.squeeze(label.numpy(), axis=0) - return image, label - -def normal_intensity(image, min_clip=-79.0, max_clip=304.0, mean=101.0, std=76.9): - image = np.clip(image, min_clip, max_clip) - image = (image - mean) / std - return image - -def pad_to_min_shape(image, label, roi_shape=(128, 128, 128)): - current_shape = image.shape[1:] - bounds = [max(0, roi_shape[i] - current_shape[i]) for i in range(3)] - paddings = [(0, 0)] + [(bounds[i] // 2, bounds[i] - bounds[i] // 2) for i in range(3)] - image = np.pad(image, paddings, mode="edge") - label = np.pad(label, paddings, mode="edge") - return image, label - -def preprocess(file_path): - image, label, image_spacings = load_pair(file_path) - image, label = resample3d(image, label, image_spacings) - image = normal_intensity(image.copy()) - image, label = pad_to_min_shape(image, label) - return image, label - -def preprocess_dataset(filenames, preprocessed_dir, val): - if not preprocessed_dir.is_dir(): os.makedirs(preprocessed_dir) - for fn in tqdm(filenames, desc=f"preprocessing {'validation' if val else 'training'}"): - case = os.path.basename(fn) - image, label = preprocess(fn) - image, label = image.astype(np.float32), label.astype(np.uint8) - np.save(preprocessed_dir / f"{case}_x.npy", image, allow_pickle=False) - np.save(preprocessed_dir / f"{case}_y.npy", label, allow_pickle=False) - -def iterate(files, preprocessed_dir=None, val=True, shuffle=False, bs=1): - order = list(range(0, len(files))) - if shuffle: random.shuffle(order) - for i in range(0, len(files), bs): - samples = [] - for i in order[i:i+bs]: - if preprocessed_dir is not None: - x_cached_path, y_cached_path = preprocessed_dir / f"{os.path.basename(files[i])}_x.npy", preprocessed_dir / f"{os.path.basename(files[i])}_y.npy" - if x_cached_path.exists() and y_cached_path.exists(): - samples += [(np.load(x_cached_path), np.load(y_cached_path))] - else: samples += [preprocess(files[i])] - X, Y = [x[0] for x in samples], [x[1] for x in samples] - if val: - yield X[0][None], Y[0] - else: - X_preprocessed, Y_preprocessed = [], [] - for x, y in zip(X, Y): - x, y = rand_balanced_crop(x, y) - x, y = rand_flip(x, y) - x, y = x.astype(np.float32), y.astype(np.uint8) - x = random_brightness_augmentation(x) - x = gaussian_noise(x) - X_preprocessed.append(x) - Y_preprocessed.append(y) - yield np.stack(X_preprocessed, axis=0), np.stack(Y_preprocessed, axis=0) - -def gaussian_kernel(n, std): - gaussian_1d = signal.windows.gaussian(n, std) - gaussian_2d = np.outer(gaussian_1d, gaussian_1d) - gaussian_3d = np.outer(gaussian_2d, gaussian_1d) - gaussian_3d = gaussian_3d.reshape(n, n, n) - gaussian_3d = np.cbrt(gaussian_3d) - gaussian_3d /= gaussian_3d.max() - return gaussian_3d - -def pad_input(volume, roi_shape, strides, padding_mode="constant", padding_val=-2.2, dim=3): - bounds = [(strides[i] - volume.shape[2:][i] % strides[i]) % strides[i] for i in range(dim)] - bounds = [bounds[i] if (volume.shape[2:][i] + bounds[i]) >= roi_shape[i] else bounds[i] + strides[i] for i in range(dim)] - paddings = [bounds[2]//2, bounds[2]-bounds[2]//2, bounds[1]//2, bounds[1]-bounds[1]//2, bounds[0]//2, bounds[0]-bounds[0]//2, 0, 0, 0, 0] - return F.pad(torch.from_numpy(volume), paddings, mode=padding_mode, value=padding_val).numpy(), paddings - -def sliding_window_inference(model, inputs, labels, roi_shape=(128, 128, 128), overlap=0.5, gpus=None): - from tinygrad.engine.jit import TinyJit - mdl_run = TinyJit(lambda x: model(x).realize()) - image_shape, dim = list(inputs.shape[2:]), len(inputs.shape[2:]) - strides = [int(roi_shape[i] * (1 - overlap)) for i in range(dim)] - bounds = [image_shape[i] % strides[i] for i in range(dim)] - bounds = [bounds[i] if bounds[i] < strides[i] // 2 else 0 for i in range(dim)] - inputs = inputs[ - ..., - bounds[0]//2:image_shape[0]-(bounds[0]-bounds[0]//2), - bounds[1]//2:image_shape[1]-(bounds[1]-bounds[1]//2), - bounds[2]//2:image_shape[2]-(bounds[2]-bounds[2]//2), - ] - labels = labels[ - ..., - bounds[0]//2:image_shape[0]-(bounds[0]-bounds[0]//2), - bounds[1]//2:image_shape[1]-(bounds[1]-bounds[1]//2), - bounds[2]//2:image_shape[2]-(bounds[2]-bounds[2]//2), - ] - inputs, paddings = pad_input(inputs, roi_shape, strides) - padded_shape = inputs.shape[2:] - size = [(inputs.shape[2:][i] - roi_shape[i]) // strides[i] + 1 for i in range(dim)] - result = np.zeros((1, 3, *padded_shape), dtype=np.float32) - norm_map = np.zeros((1, 3, *padded_shape), dtype=np.float32) - norm_patch = gaussian_kernel(roi_shape[0], 0.125 * roi_shape[0]) - norm_patch = np.expand_dims(norm_patch, axis=0) - for i in range(0, strides[0] * size[0], strides[0]): - for j in range(0, strides[1] * size[1], strides[1]): - for k in range(0, strides[2] * size[2], strides[2]): - out = mdl_run(Tensor(inputs[..., i:roi_shape[0]+i,j:roi_shape[1]+j, k:roi_shape[2]+k], device=gpus)).numpy() - result[..., i:roi_shape[0]+i, j:roi_shape[1]+j, k:roi_shape[2]+k] += out * norm_patch - norm_map[..., i:roi_shape[0]+i, j:roi_shape[1]+j, k:roi_shape[2]+k] += norm_patch - result /= norm_map - result = result[..., paddings[4]:image_shape[0]+paddings[4], paddings[2]:image_shape[1]+paddings[2], paddings[0]:image_shape[2]+paddings[0]] - return result, labels - -def rand_flip(image, label, axis=(1, 2, 3)): - prob = 1 / len(axis) - for ax in axis: - if random.random() < prob: - image = np.flip(image, axis=ax).copy() - label = np.flip(label, axis=ax).copy() - return image, label - -def random_brightness_augmentation(image, low=0.7, high=1.3, prob=0.1): - if random.random() < prob: - factor = np.random.uniform(low=low, high=high, size=1) - image = (image * (1 + factor)).astype(image.dtype) - return image - -def gaussian_noise(image, mean=0.0, std=0.1, prob=0.1): - if random.random() < prob: - scale = np.random.uniform(low=0.0, high=std) - noise = np.random.normal(loc=mean, scale=scale, size=image.shape).astype(image.dtype) - image += noise - return image - -def _rand_foreg_cropb(image, label, patch_size): - def adjust(foreg_slice, label, idx): - diff = patch_size[idx - 1] - (foreg_slice[idx].stop - foreg_slice[idx].start) - sign = -1 if diff < 0 else 1 - diff = abs(diff) - ladj = 0 if diff == 0 else random.randrange(diff) - hadj = diff - ladj - low = max(0, foreg_slice[idx].start - sign * ladj) - high = min(label.shape[idx], foreg_slice[idx].stop + sign * hadj) - diff = patch_size[idx - 1] - (high - low) - if diff > 0 and low == 0: high += diff - elif diff > 0: low -= diff - return low, high - - cl = np.random.choice(np.unique(label[label > 0])) - foreg_slices = ndimage.find_objects(ndimage.label(label==cl)[0]) - foreg_slices = [x for x in foreg_slices if x is not None] - slice_volumes = [np.prod([s.stop - s.start for s in sl]) for sl in foreg_slices] - slice_idx = np.argsort(slice_volumes)[-2:] - foreg_slices = [foreg_slices[i] for i in slice_idx] - if not foreg_slices: return _rand_crop(image, label) - foreg_slice = foreg_slices[random.randrange(len(foreg_slices))] - low_x, high_x = adjust(foreg_slice, label, 1) - low_y, high_y = adjust(foreg_slice, label, 2) - low_z, high_z = adjust(foreg_slice, label, 3) - image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] - label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] - return image, label - -def _rand_crop(image, label, patch_size): - ranges = [s - p for s, p in zip(image.shape[1:], patch_size)] - cord = [0 if x == 0 else random.randrange(x) for x in ranges] - low_x, high_x = cord[0], cord[0] + patch_size[0] - low_y, high_y = cord[1], cord[1] + patch_size[1] - low_z, high_z = cord[2], cord[2] + patch_size[2] - image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] - label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] - return image, label - -def rand_balanced_crop(image, label, patch_size=(128, 128, 128), oversampling=0.4): - if random.random() < oversampling: - image, label = _rand_foreg_cropb(image, label, patch_size) - else: - image, label = _rand_crop(image, label, patch_size) - return image, label - -if __name__ == "__main__": - for X, Y in iterate(get_val_files()): - print(X.shape, Y.shape) diff --git a/tinygrad/extra/datasets/librispeech.py b/tinygrad/extra/datasets/librispeech.py deleted file mode 100644 index 434d7a05..00000000 --- a/tinygrad/extra/datasets/librispeech.py +++ /dev/null @@ -1,82 +0,0 @@ -import json -import pathlib -import numpy as np -import librosa -import soundfile - -""" -The dataset has to be downloaded manually from https://www.openslr.org/12/ and put in `extra/datasets/librispeech`. -For mlperf validation the dev-clean dataset is used. - -Then all the flacs have to be converted to wav using something like: -```fish -for file in $(find * | grep flac); do ffmpeg -i $file -ar 16k "$(dirname $file)/$(basename $file .flac).wav"; done -``` - -Then this [file](https://github.com/mlcommons/inference/blob/master/speech_recognition/rnnt/dev-clean-wav.json) has to also be put in `extra/datasets/librispeech`. -""" -BASEDIR = pathlib.Path(__file__).parent / "librispeech" -with open(BASEDIR / "dev-clean-wav.json") as f: - ci = json.load(f) - -FILTER_BANK = np.expand_dims(librosa.filters.mel(sr=16000, n_fft=512, n_mels=80, fmin=0, fmax=8000), 0) -WINDOW = librosa.filters.get_window("hann", 320) - -def feature_extract(x, x_lens): - x_lens = np.ceil((x_lens / 160) / 3).astype(np.int32) - - # pre-emphasis - x = np.concatenate((np.expand_dims(x[:, 0], 1), x[:, 1:] - 0.97 * x[:, :-1]), axis=1) - - # stft - x = librosa.stft(x, n_fft=512, window=WINDOW, hop_length=160, win_length=320, center=True, pad_mode="reflect") - x = np.stack((x.real, x.imag), axis=-1) - - # power spectrum - x = (x**2).sum(-1) - - # mel filter bank - x = np.matmul(FILTER_BANK, x) - - # log - x = np.log(x + 1e-20) - - # feature splice - seq = [x] - for i in range(1, 3): - tmp = np.zeros_like(x) - tmp[:, :, :-i] = x[:, :, i:] - seq.append(tmp) - features = np.concatenate(seq, axis=1)[:, :, ::3] - - # normalize - features_mean = np.zeros((features.shape[0], features.shape[1]), dtype=np.float32) - features_std = np.zeros((features.shape[0], features.shape[1]), dtype=np.float32) - for i in range(features.shape[0]): - features_mean[i, :] = features[i, :, :x_lens[i]].mean(axis=1) - features_std[i, :] = features[i, :, :x_lens[i]].std(axis=1, ddof=1) - features_std += 1e-5 - features = (features - np.expand_dims(features_mean, 2)) / np.expand_dims(features_std, 2) - - return features.transpose(2, 0, 1), x_lens.astype(np.float32) - -def load_wav(file): - sample = soundfile.read(file)[0].astype(np.float32) - return sample, sample.shape[0] - -def iterate(bs=1, start=0): - print(f"there are {len(ci)} samples in the dataset") - for i in range(start, len(ci), bs): - samples, sample_lens = zip(*[load_wav(BASEDIR / v["files"][0]["fname"]) for v in ci[i : i + bs]]) - samples = list(samples) - # pad to same length - max_len = max(sample_lens) - for j in range(len(samples)): - samples[j] = np.pad(samples[j], (0, max_len - sample_lens[j]), "constant") - samples, sample_lens = np.array(samples), np.array(sample_lens) - - yield feature_extract(samples, sample_lens), np.array([v["transcript"] for v in ci[i : i + bs]]) - -if __name__ == "__main__": - X, Y = next(iterate()) - print(X[0].shape, Y.shape) diff --git a/tinygrad/extra/datasets/openimages.py b/tinygrad/extra/datasets/openimages.py deleted file mode 100644 index 70dfd120..00000000 --- a/tinygrad/extra/datasets/openimages.py +++ /dev/null @@ -1,209 +0,0 @@ -import glob -import sys -import json -import numpy as np -from PIL import Image -from pathlib import Path -import boto3, botocore -from tinygrad import Tensor, dtypes -from tinygrad.helpers import fetch, tqdm, getenv -import pandas as pd -import concurrent.futures - -BASEDIR = Path(__file__).parent / "open-images-v6-mlperf" -BUCKET_NAME = "open-images-dataset" -TRAIN_BBOX_ANNOTATIONS_URL = "https://storage.googleapis.com/openimages/v6/oidv6-train-annotations-bbox.csv" -VALIDATION_BBOX_ANNOTATIONS_URL = "https://storage.googleapis.com/openimages/v5/validation-annotations-bbox.csv" -MAP_CLASSES_URL = "https://storage.googleapis.com/openimages/v5/class-descriptions-boxable.csv" -MLPERF_CLASSES = ['Airplane', 'Antelope', 'Apple', 'Backpack', 'Balloon', 'Banana', - 'Barrel', 'Baseball bat', 'Baseball glove', 'Bee', 'Beer', 'Bench', 'Bicycle', - 'Bicycle helmet', 'Bicycle wheel', 'Billboard', 'Book', 'Bookcase', 'Boot', - 'Bottle', 'Bowl', 'Bowling equipment', 'Box', 'Boy', 'Brassiere', 'Bread', - 'Broccoli', 'Bronze sculpture', 'Bull', 'Bus', 'Bust', 'Butterfly', 'Cabinetry', - 'Cake', 'Camel', 'Camera', 'Candle', 'Candy', 'Cannon', 'Canoe', 'Carrot', 'Cart', - 'Castle', 'Cat', 'Cattle', 'Cello', 'Chair', 'Cheese', 'Chest of drawers', 'Chicken', - 'Christmas tree', 'Coat', 'Cocktail', 'Coffee', 'Coffee cup', 'Coffee table', 'Coin', - 'Common sunflower', 'Computer keyboard', 'Computer monitor', 'Convenience store', - 'Cookie', 'Countertop', 'Cowboy hat', 'Crab', 'Crocodile', 'Cucumber', 'Cupboard', - 'Curtain', 'Deer', 'Desk', 'Dinosaur', 'Dog', 'Doll', 'Dolphin', 'Door', 'Dragonfly', - 'Drawer', 'Dress', 'Drum', 'Duck', 'Eagle', 'Earrings', 'Egg (Food)', 'Elephant', - 'Falcon', 'Fedora', 'Flag', 'Flowerpot', 'Football', 'Football helmet', 'Fork', - 'Fountain', 'French fries', 'French horn', 'Frog', 'Giraffe', 'Girl', 'Glasses', - 'Goat', 'Goggles', 'Goldfish', 'Gondola', 'Goose', 'Grape', 'Grapefruit', 'Guitar', - 'Hamburger', 'Handbag', 'Harbor seal', 'Headphones', 'Helicopter', 'High heels', - 'Hiking equipment', 'Horse', 'House', 'Houseplant', 'Human arm', 'Human beard', - 'Human body', 'Human ear', 'Human eye', 'Human face', 'Human foot', 'Human hair', - 'Human hand', 'Human head', 'Human leg', 'Human mouth', 'Human nose', 'Ice cream', - 'Jacket', 'Jeans', 'Jellyfish', 'Juice', 'Kitchen & dining room table', 'Kite', - 'Lamp', 'Lantern', 'Laptop', 'Lavender (Plant)', 'Lemon', 'Light bulb', 'Lighthouse', - 'Lily', 'Lion', 'Lipstick', 'Lizard', 'Man', 'Maple', 'Microphone', 'Mirror', - 'Mixing bowl', 'Mobile phone', 'Monkey', 'Motorcycle', 'Muffin', 'Mug', 'Mule', - 'Mushroom', 'Musical keyboard', 'Necklace', 'Nightstand', 'Office building', - 'Orange', 'Owl', 'Oyster', 'Paddle', 'Palm tree', 'Parachute', 'Parrot', 'Pen', - 'Penguin', 'Personal flotation device', 'Piano', 'Picture frame', 'Pig', 'Pillow', - 'Pizza', 'Plate', 'Platter', 'Porch', 'Poster', 'Pumpkin', 'Rabbit', 'Rifle', - 'Roller skates', 'Rose', 'Salad', 'Sandal', 'Saucer', 'Saxophone', 'Scarf', 'Sea lion', - 'Sea turtle', 'Sheep', 'Shelf', 'Shirt', 'Shorts', 'Shrimp', 'Sink', 'Skateboard', - 'Ski', 'Skull', 'Skyscraper', 'Snake', 'Sock', 'Sofa bed', 'Sparrow', 'Spider', 'Spoon', - 'Sports uniform', 'Squirrel', 'Stairs', 'Stool', 'Strawberry', 'Street light', - 'Studio couch', 'Suit', 'Sun hat', 'Sunglasses', 'Surfboard', 'Sushi', 'Swan', - 'Swimming pool', 'Swimwear', 'Tank', 'Tap', 'Taxi', 'Tea', 'Teddy bear', 'Television', - 'Tent', 'Tie', 'Tiger', 'Tin can', 'Tire', 'Toilet', 'Tomato', 'Tortoise', 'Tower', - 'Traffic light', 'Train', 'Tripod', 'Truck', 'Trumpet', 'Umbrella', 'Van', 'Vase', - 'Vehicle registration plate', 'Violin', 'Wall clock', 'Waste container', 'Watch', - 'Whale', 'Wheel', 'Wheelchair', 'Whiteboard', 'Window', 'Wine', 'Wine glass', 'Woman', - 'Zebra', 'Zucchini', -] - - -def openimages(base_dir:Path, subset:str, ann_file:Path): - valid_subsets = ['train', 'validation'] - if subset not in valid_subsets: - raise ValueError(f"{subset=} must be one of {valid_subsets}") - - fetch_openimages(ann_file, base_dir, subset) - -# this slows down the conversion a lot! -# maybe use https://raw.githubusercontent.com/scardine/image_size/master/get_image_size.py -def extract_dims(path): return Image.open(path).size[::-1] - -def export_to_coco(class_map, annotations, image_list, dataset_path, output_path, subset, classes=MLPERF_CLASSES): - output_path.parent.mkdir(parents=True, exist_ok=True) - cats = [{"id": i, "name": c, "supercategory": None} for i, c in enumerate(classes)] - categories_map = pd.DataFrame([(i, c) for i, c in enumerate(classes)], columns=["category_id", "category_name"]) - class_map = class_map.merge(categories_map, left_on="DisplayName", right_on="category_name", how="inner") - annotations = annotations[annotations["ImageID"].isin(image_list)] - annotations = annotations.merge(class_map, on="LabelName", how="inner") - annotations["image_id"] = pd.factorize(annotations["ImageID"].tolist())[0] - annotations[["height", "width"]] = annotations.apply(lambda x: extract_dims(dataset_path / f"{x['ImageID']}.jpg"), axis=1, result_type="expand") - - # Images - imgs = [{"id": int(id + 1), "file_name": f"{image_id}.jpg", "height": row["height"], "width": row["width"], "subset": subset, "license": None, "coco_url": None} - for (id, image_id), row in (annotations.groupby(["image_id", "ImageID"]).first().iterrows()) - ] - - # Annotations - annots = [] - for i, row in annotations.iterrows(): - xmin, ymin, xmax, ymax, img_w, img_h = [row[k] for k in ["XMin", "YMin", "XMax", "YMax", "width", "height"]] - x, y, w, h = xmin * img_w, ymin * img_h, (xmax - xmin) * img_w, (ymax - ymin) * img_h - coco_annot = {"id": int(i) + 1, "image_id": int(row["image_id"] + 1), "category_id": int(row["category_id"]), "bbox": [x, y, w, h], "area": w * h} - coco_annot.update({k: row[k] for k in ["IsOccluded", "IsInside", "IsDepiction", "IsTruncated", "IsGroupOf"]}) - coco_annot["iscrowd"] = int(row["IsGroupOf"]) - annots.append(coco_annot) - - info = {"dataset": "openimages_mlperf", "version": "v6"} - coco_annotations = {"info": info, "licenses": [], "categories": cats, "images": imgs, "annotations": annots} - with open(output_path, "w") as fp: - json.dump(coco_annotations, fp) - -def get_image_list(class_map, annotations, classes=MLPERF_CLASSES): - labels = class_map[class_map["DisplayName"].isin(classes)]["LabelName"] - image_ids = annotations[annotations["LabelName"].isin(labels)]["ImageID"].unique() - return image_ids - -def download_image(bucket, subset, image_id, data_dir): - try: - bucket.download_file(f"{subset}/{image_id}.jpg", f"{data_dir}/{image_id}.jpg") - except botocore.exceptions.ClientError as exception: - sys.exit(f"ERROR when downloading image `validation/{image_id}`: {str(exception)}") - -def fetch_openimages(output_fn:str, base_dir:Path, subset:str): - bucket = boto3.resource("s3", config=botocore.config.Config(signature_version=botocore.UNSIGNED)).Bucket(BUCKET_NAME) - - annotations_dir, data_dir = base_dir / "annotations", base_dir / f"{subset}/data" - annotations_dir.mkdir(parents=True, exist_ok=True) - data_dir.mkdir(parents=True, exist_ok=True) - - if subset == "train": - annotations_fn = annotations_dir / TRAIN_BBOX_ANNOTATIONS_URL.split('/')[-1] - fetch(TRAIN_BBOX_ANNOTATIONS_URL, annotations_fn) - else: # subset == validation - annotations_fn = annotations_dir / VALIDATION_BBOX_ANNOTATIONS_URL.split('/')[-1] - fetch(VALIDATION_BBOX_ANNOTATIONS_URL, annotations_fn) - - annotations = pd.read_csv(annotations_fn) - - classmap_fn = annotations_dir / MAP_CLASSES_URL.split('/')[-1] - fetch(MAP_CLASSES_URL, classmap_fn) - class_map = pd.read_csv(classmap_fn, names=["LabelName", "DisplayName"]) - - image_list = get_image_list(class_map, annotations) - - with concurrent.futures.ThreadPoolExecutor() as executor: - futures = [executor.submit(download_image, bucket, subset, image_id, data_dir) for image_id in image_list] - for future in (t := tqdm(concurrent.futures.as_completed(futures), total=len(image_list))): - t.set_description(f"Downloading images") - future.result() - - print("Converting annotations to COCO format...") - export_to_coco(class_map, annotations, image_list, data_dir, output_fn, subset) - -def image_load(base_dir, subset, fn): - img_folder = base_dir / f"{subset}/data" - return Image.open(img_folder / fn).convert('RGB') - -def prepare_target(annotations, img_id, img_size): - boxes = [annot["bbox"] for annot in annotations] - boxes = np.array(boxes, dtype=np.float32).reshape(-1, 4) - boxes[:, 2:] += boxes[:, :2] - boxes[:, 0::2] = boxes[:, 0::2].clip(0, img_size[1]) - boxes[:, 1::2] = boxes[:, 1::2].clip(0, img_size[0]) - keep = (boxes[:, 3] > boxes[:, 1]) & (boxes[:, 2] > boxes[:, 0]) - boxes = boxes[keep] - classes = [annot["category_id"] for annot in annotations] - classes = np.array(classes, dtype=np.int64) - classes = classes[keep] - return {"boxes": boxes, "labels": classes, "image_id": img_id, "image_size": img_size} - -def download_dataset(base_dir:Path, subset:str) -> Path: - if (ann_file:=base_dir / f"{subset}/labels/openimages-mlperf.json").is_file(): print(f"{subset} dataset is already available") - else: - print(f"Downloading {subset} dataset...") - openimages(base_dir, subset, ann_file) - print("Done") - - return ann_file - -def random_horizontal_flip(img, tgt, prob=0.5): - import torch - import torchvision.transforms.functional as F - if torch.rand(1) < prob: - w = img.size[0] - img = F.hflip(img) - tgt["boxes"][:, [0, 2]] = w - tgt["boxes"][:, [2, 0]] - return img, tgt - -def resize(img:Image, tgt:dict[str, np.ndarray|tuple]|None=None, size:tuple[int, int]=(800, 800)) -> tuple[np.ndarray, np.ndarray, tuple]|tuple[np.ndarray, tuple]: - import torchvision.transforms.functional as F - img_size = img.size[::-1] - img = F.resize(img, size=size) - img = np.array(img) - - if tgt is not None: - ratios = [s / s_orig for s, s_orig in zip(size, img_size)] - ratio_h, ratio_w = ratios - x_min, y_min, x_max, y_max = [tgt["boxes"][:, i] for i in range(tgt["boxes"].shape[-1])] - x_min = x_min * ratio_w - x_max = x_max * ratio_w - y_min = y_min * ratio_h - y_max = y_max * ratio_h - - tgt["boxes"] = np.stack([x_min, y_min, x_max, y_max], axis=1) - return img, tgt, img_size - - return img, img_size - -def normalize(img:Tensor, device:list[str]|None = None): - mean = Tensor([0.485, 0.456, 0.406], device=device, dtype=dtypes.float32).reshape(1, -1, 1, 1) - std = Tensor([0.229, 0.224, 0.225], device=device, dtype=dtypes.float32).reshape(1, -1, 1, 1) - img = ((img.permute([0, 3, 1, 2]) / 255.0) - mean) / std - return img.cast(dtypes.default_float) - -def get_dataset_count(base_dir:Path, val:bool) -> int: - if not (files:=glob.glob(p:=str(base_dir / f"{'validation' if val else 'train'}/data/*.jpg"))): raise FileNotFoundError(f"No files in {p}") - return len(files) - -if __name__ == "__main__": - download_dataset(base_dir:=getenv("BASEDIR", BASEDIR), "train") - download_dataset(base_dir, "validation") diff --git a/tinygrad/extra/datasets/preprocess_imagenet.py b/tinygrad/extra/datasets/preprocess_imagenet.py deleted file mode 100644 index 6ca06931..00000000 --- a/tinygrad/extra/datasets/preprocess_imagenet.py +++ /dev/null @@ -1,21 +0,0 @@ -from tinygrad import Tensor, dtypes -from extra.datasets.imagenet import iterate, get_val_files - -if __name__ == "__main__": - #sz = len(get_val_files()) - sz = 32*100 - X,Y = None, None - - idx = 0 - for x,y in iterate(shuffle=False): - print(x.shape, y.shape, x.dtype, y.dtype) - assert x.shape[0] == y.shape[0] - bs = x.shape[0] - if X is None: - X = Tensor.empty(sz, *x.shape[1:], device="disk:/tmp/imagenet_x", dtype=dtypes.uint8) - Y = Tensor.empty(sz, *y.shape[1:], device="disk:/tmp/imagenet_y", dtype=dtypes.int64) - print(X.shape, Y.shape) - X[idx:idx+bs].assign(x) - Y[idx:idx+bs].assign(y) - idx += bs - if idx >= sz: break diff --git a/tinygrad/extra/datasets/sops.gz b/tinygrad/extra/datasets/sops.gz deleted file mode 100644 index 1362cbe1..00000000 Binary files a/tinygrad/extra/datasets/sops.gz and /dev/null differ diff --git a/tinygrad/extra/datasets/squad.py b/tinygrad/extra/datasets/squad.py deleted file mode 100644 index 7be38bff..00000000 --- a/tinygrad/extra/datasets/squad.py +++ /dev/null @@ -1,148 +0,0 @@ -import json -import os -from pathlib import Path -from transformers import BertTokenizer -import numpy as np -from tinygrad.helpers import fetch - -BASEDIR = Path(__file__).parent / "squad" -def init_dataset(): - os.makedirs(BASEDIR, exist_ok=True) - fetch("https://rajpurkar.github.io/SQuAD-explorer/dataset/dev-v1.1.json", BASEDIR / "dev-v1.1.json") - with open(BASEDIR / "dev-v1.1.json") as f: - data = json.load(f)["data"] - - examples = [] - for article in data: - for paragraph in article["paragraphs"]: - text = paragraph["context"] - doc_tokens = [] - prev_is_whitespace = True - for c in text: - if c == " " or c == "\t" or c == "\r" or c == "\n" or ord(c) == 0x202F: - prev_is_whitespace = True - else: - if prev_is_whitespace: - doc_tokens.append(c) - else: - doc_tokens[-1] += c - prev_is_whitespace = False - - for qa in paragraph["qas"]: - qa_id = qa["id"] - q_text = qa["question"] - - examples.append({ - "id": qa_id, - "question": q_text, - "context": doc_tokens, - "answers": list(map(lambda x: x["text"], qa["answers"])) - }) - return examples - -def _check_is_max_context(doc_spans, cur_span_index, position): - best_score, best_span_index = None, None - for di, (doc_start, doc_length) in enumerate(doc_spans): - end = doc_start + doc_length - 1 - if position < doc_start: - continue - if position > end: - continue - num_left_context = position - doc_start - num_right_context = end - position - score = min(num_left_context, num_right_context) + 0.01 * doc_length - if best_score is None or score > best_score: - best_score = score - best_span_index = di - return cur_span_index == best_span_index - -def convert_example_to_features(example, tokenizer): - query_tokens = tokenizer.tokenize(example["question"]) - - if len(query_tokens) > 64: - query_tokens = query_tokens[:64] - - tok_to_orig_index = [] - orig_to_tok_index = [] - all_doc_tokens = [] - for i, token in enumerate(example["context"]): - orig_to_tok_index.append(len(all_doc_tokens)) - sub_tokens = tokenizer.tokenize(token) - for sub_token in sub_tokens: - tok_to_orig_index.append(i) - all_doc_tokens.append(sub_token) - - max_tokens_for_doc = 384 - len(query_tokens) - 3 - - doc_spans = [] - start_offset = 0 - while start_offset < len(all_doc_tokens): - length = len(all_doc_tokens) - start_offset - length = min(length, max_tokens_for_doc) - doc_spans.append((start_offset, length)) - if start_offset + length == len(all_doc_tokens): - break - start_offset += min(length, 128) - - outputs = [] - for di, (doc_start, doc_length) in enumerate(doc_spans): - tokens = [] - token_to_orig_map = {} - token_is_max_context = {} - segment_ids = [] - tokens.append("[CLS]") - segment_ids.append(0) - for token in query_tokens: - tokens.append(token) - segment_ids.append(0) - tokens.append("[SEP]") - segment_ids.append(0) - - for i in range(doc_length): - split_token_index = doc_start + i - token_to_orig_map[len(tokens)] = tok_to_orig_index[split_token_index] - token_is_max_context[len(tokens)] = _check_is_max_context(doc_spans, di, split_token_index) - tokens.append(all_doc_tokens[split_token_index]) - segment_ids.append(1) - tokens.append("[SEP]") - segment_ids.append(1) - - input_ids = tokenizer.convert_tokens_to_ids(tokens) - input_mask = [1] * len(input_ids) - - while len(input_ids) < 384: - input_ids.append(0) - input_mask.append(0) - segment_ids.append(0) - - assert len(input_ids) == 384 - assert len(input_mask) == 384 - assert len(segment_ids) == 384 - - outputs.append({ - "input_ids": np.expand_dims(np.array(input_ids), 0).astype(np.float32), - "input_mask": np.expand_dims(np.array(input_mask), 0).astype(np.float32), - "segment_ids": np.expand_dims(np.array(segment_ids), 0).astype(np.float32), - "token_to_orig_map": token_to_orig_map, - "token_is_max_context": token_is_max_context, - "tokens": tokens, - }) - - return outputs - -def iterate(tokenizer, start=0): - examples = init_dataset() - print(f"there are {len(examples)} pairs in the dataset") - - for i in range(start, len(examples)): - example = examples[i] - features = convert_example_to_features(example, tokenizer) - # we need to yield all features here as the f1 score is the maximum over all features - yield features, example - -if __name__ == "__main__": - tokenizer = BertTokenizer(str(Path(__file__).parents[2] / "weights" / "bert_vocab.txt")) - - X, Y = next(iterate(tokenizer)) - print(" ".join(X[0]["tokens"])) - print(X[0]["input_ids"].shape, Y) diff --git a/tinygrad/extra/datasets/wikipedia.py b/tinygrad/extra/datasets/wikipedia.py deleted file mode 100644 index 1b8dc767..00000000 --- a/tinygrad/extra/datasets/wikipedia.py +++ /dev/null @@ -1,398 +0,0 @@ -# Preprocessing of downloaded text from Wikipedia for MLPerf BERT training -# This is a modified version of the original script: -# https://github.com/mlcommons/training/blob/master/language_model/tensorflow/bert/cleanup_scripts/create_pretraining_data.py -# ENV VARS: -# MAX_SEQ_LENGTH - Maximum sequence length -# MAX_PREDICTIONS_PER_SEQ - Maximum number of masked LM predictions per sequence -# RANDOM_SEED - Random seed -# DUPE_FACTOR - Number of times to duplicate the input data with different masks -# MASKED_LM_PROB - Probability of masking a token -# SHORT_SEQ_PROB - Probability of picking a sequence shorter than MAX_SEQ_LENGTH - -import os, sys, pickle, random, unicodedata -from pathlib import Path -import numpy as np -from tqdm import tqdm -from tqdm.contrib.concurrent import process_map - -from tinygrad.helpers import diskcache, getenv - -BASEDIR = getenv('BASEDIR', Path(__file__).parent / "wiki") - -################### Tokenization ##################### - -def _is_whitespace(char:str) -> bool: - if char == " " or char == "\t" or char == "\n" or char == "\r": - return True - return unicodedata.category(char) == "Zs" - -def _is_control(char:str) -> bool: - if char == "\t" or char == "\n" or char == "\r": - return False - return unicodedata.category(char).startswith("C") - -def _is_punctuation(char:str) -> bool: - # range(33, 48) -> ! " # $ % & ' ( ) * + , - . / - # range(58, 65) -> : ; < = > ? @ - # range(91, 97) -> [ \ ] ^ _ - # range(123, 127) -> { | } ~ - if (cp := ord(char)) in range(33, 48) or cp in range(58, 65) or cp in range(91, 97) or cp in range(123, 127): - return True - return unicodedata.category(char).startswith("P") - -def _is_chinese_char(cp:int) -> bool: - if ((cp >= 0x4E00 and cp <= 0x9FFF) or - (cp >= 0x3400 and cp <= 0x4DBF) or - (cp >= 0x20000 and cp <= 0x2A6DF) or - (cp >= 0x2A700 and cp <= 0x2B73F) or - (cp >= 0x2B740 and cp <= 0x2B81F) or - (cp >= 0x2B820 and cp <= 0x2CEAF) or - (cp >= 0xF900 and cp <= 0xFAFF) or - (cp >= 0x2F800 and cp <= 0x2FA1F)): - return True - return False - -def _run_split_on_punc(text:str) -> list[str]: - if text in ("[UNK]", "[SEP]", "[PAD]", "[CLS]", "[MASK]"): - return [text] - start_new_word = True - output = [] - for i in range(len(text)): - if _is_punctuation(char := text[i]): - output.append([char]) - start_new_word = True - else: - if start_new_word: - output.append([]) - start_new_word = False - output[-1].append(char) - return ["".join(x) for x in output] - -def _run_strip_accents(text:str) -> str: - output = [] - for char in unicodedata.normalize("NFD", text): - if unicodedata.category(char) != "Mn": - output.append(char) - return "".join(output) - -def _clean_text(text:str) -> str: - output = [] - for char in text: - if not ((cp := ord(char)) == 0 or cp == 0xfffd or _is_control(char)): - output.append(" " if _is_whitespace(char) else char) - return "".join(output) - -def _tokenize_chinese_chars(text:str) -> str: - output = [] - for char in text: - cp = ord(char) - if _is_chinese_char(cp): - output.append(" ") - output.append(char) - output.append(" ") - else: - output.append(char) - return "".join(output) - -def whitespace_tokenize(text): - if not (text := text.strip()): return [] - return text.split() - -def _wordpiece_tokenize(text:str, vocab:dict[str, int]) -> list[str]: - text = text.decode("utf-8", "ignore") if isinstance(text, bytes) else text - output_tokens = [] - for token in text.strip().split(): - chars = list(token) - if len(chars) > 200: - output_tokens.append("[UNK]") - continue - - is_bad = False - start = 0 - sub_tokens = [] - while start < len(chars): - end = len(chars) - cur_substr = None - while start < end: - substr = "".join(chars[start:end]) - if start > 0: substr = "##" + substr - if substr in vocab: - cur_substr = substr - break - end -= 1 - if cur_substr is None: - is_bad = True - break - sub_tokens.append(cur_substr) - start = end - - if is_bad: output_tokens.append("[UNK]") - else: output_tokens.extend(sub_tokens) - return output_tokens - -class Tokenizer: - def __init__(self, vocab_file): - self.vocab = {} - with open(vocab_file) as f: - for line in f: - line = line.decode("utf-8", "ignore") if isinstance(line, bytes) else line - if (token := line.strip()) and token not in self.vocab: self.vocab[token] = len(self.vocab) - self.inv_vocab = {v: k for k, v in self.vocab.items()} - - def tokenize(self, text:str) -> list[str]: - # BasicTokenizer - split_tokens = [] - for token in whitespace_tokenize(_tokenize_chinese_chars(_clean_text(text.decode("utf-8", "ignore") if isinstance(text, bytes) else text))): - split_tokens.extend(_run_split_on_punc(_run_strip_accents(token.lower()))) - split_tokens = " ".join(split_tokens).strip().split() - # WordpieceTokenizer - tokens = [] - for token in split_tokens: - tokens.extend(_wordpiece_tokenize(token, self.vocab)) - return tokens - - def convert_tokens_to_ids(self, tokens:list[str]) -> list[int]: return [self.vocab[token] for token in tokens] - def convert_ids_to_tokens(self, ids:list[int]) -> list[str]: return [self.inv_vocab[id] for id in ids] - -##################### Feature transformation ##################### - -def truncate_seq_pair(tokens_a:list[str], tokens_b:list[str], max_num_tokens:int, rng:random.Random) -> None: - while True: - total_length = len(tokens_a) + len(tokens_b) - if total_length <= max_num_tokens: - break - - trunc_tokens = tokens_a if len(tokens_a) > len(tokens_b) else tokens_b - assert len(trunc_tokens) >= 1 - - if rng.random() < 0.5: - del trunc_tokens[0] - else: - trunc_tokens.pop() - -def create_masked_lm_predictions(tokens:list[str], tokenizer:Tokenizer, rng:random.Random, vocab_words:list[str]) -> tuple[list[str], list[int], list[str]]: - cand_indices = [] - for i, token in enumerate(tokens): - if token == "[CLS]" or token == "[SEP]": - continue - cand_indices.append(i) - - rng.shuffle(cand_indices) - output_tokens = list(tokens) - num_to_predict = min(getenv('MAX_PREDICTIONS_PER_SEQ', 76), max(1, int(round(len(tokens) * getenv("MASKED_LM_PROB", 0.15))))) - - masked_lms = [] - covered_indices = set() - for index in cand_indices: - if len(masked_lms) >= num_to_predict: - break - if index in covered_indices: - continue - covered_indices.add(index) - - masked_token = None - if rng.random() < 0.8: - masked_token = "[MASK]" - else: - if rng.random() < 0.5: - masked_token = tokens[index] - else: - masked_token = vocab_words[rng.randint(0, len(tokenizer.vocab) - 1)] - - output_tokens[index] = masked_token - masked_lms.append((index, tokens[index])) - masked_lms = sorted(masked_lms, key=lambda x: x[0]) - - masked_lm_positions = [] - masked_lm_labels = [] - for p in masked_lms: - masked_lm_positions.append(p[0]) - masked_lm_labels.append(p[1]) - - return output_tokens, masked_lm_positions, masked_lm_labels - -def create_instances_from_document(rng:random.Random, tokenizer:Tokenizer, doc:list[str], di:int, documents:list[list[str]]) -> list[dict]: - max_num_tokens = getenv('MAX_SEQ_LENGTH', 512) - 3 # [CLS] + 2 * [SEP] - - target_seq_length = max_num_tokens - if rng.random() < getenv("SHORT_SEQ_PROB", 0.1): - target_seq_length = rng.randint(2, max_num_tokens) - - instances = [] - current_chunk = [] - current_length = 0 - i = 0 - while i < len(doc): - segment = doc[i] - current_chunk.append(segment) - current_length += len(segment) - if i == len(doc) - 1 or current_length >= target_seq_length: - if current_chunk: - a_end = 1 - if len(current_chunk) >= 2: - a_end = rng.randint(1, len(current_chunk) - 1) - - tokens_a = [] - for j in range(a_end): - tokens_a.extend(current_chunk[j]) - - tokens_b = [] - is_random_next = False - if len(current_chunk) == 1 or rng.random() < 0.5: - is_random_next = True - target_b_length = target_seq_length - len(tokens_a) - - for _ in range(10): - random_document_index = rng.randint(0, len(documents) - 1) - if random_document_index != di: - break - - random_document = documents[random_document_index] - random_start = rng.randint(0, len(random_document) - 1) - for j in range(random_start, len(random_document)): - tokens_b.extend(random_document[j]) - if len(tokens_b) >= target_b_length: - break - - num_unused_segments = len(current_chunk) - a_end - i -= num_unused_segments - else: - is_random_next = False - for j in range(a_end, len(current_chunk)): - tokens_b.extend(current_chunk[j]) - truncate_seq_pair(tokens_a, tokens_b, max_num_tokens, rng) - - assert len(tokens_a) >= 1 - assert len(tokens_b) >= 1 - - tokens = [] - segment_ids = [] - tokens.append("[CLS]") - segment_ids.append(0) - for token in tokens_a: - tokens.append(token) - segment_ids.append(0) - tokens.append("[SEP]") - segment_ids.append(0) - for token in tokens_b: - tokens.append(token) - segment_ids.append(1) - tokens.append("[SEP]") - segment_ids.append(1) - - tokens, masked_lm_positions, masked_lm_labels = create_masked_lm_predictions(tokens, tokenizer, rng, list(tokenizer.vocab.keys())) - instances.append({ - "tokens": tokens, - "segment_ids": segment_ids, - "masked_lm_positions": masked_lm_positions, - "masked_lm_labels": masked_lm_labels, - "is_random_next": is_random_next - }) - current_chunk = [] - current_length = 0 - i += 1 - return instances - -def get_documents(rng:random.Random, tokenizer:Tokenizer, fn:str) -> list[list[str]]: - documents = [[]] - with open(BASEDIR / fn) as f: - for line in f.readlines(): - if not (line := line.decode("utf-8", "ignore") if isinstance(line, bytes) else line): break - if not (line := line.strip()): documents.append([]) - if (tokens := tokenizer.tokenize(line)): documents[-1].append(tokens) - documents = [x for x in documents if x] - rng.shuffle(documents) - return documents - -def get_instances(rng:random.Random, tokenizer:Tokenizer, documents:list[list[str]]) -> list[dict]: - instances = [] - for _ in range(getenv('DUPE_FACTOR', 10)): - for di, doc in enumerate(documents): - instances.extend(create_instances_from_document(rng, tokenizer, doc, di, documents)) - rng.shuffle(instances) - return instances - -def instance_to_features(instance:dict, tokenizer:Tokenizer) -> dict: - input_ids = tokenizer.convert_tokens_to_ids(instance["tokens"]) - input_mask = [1] * len(input_ids) - segment_ids = instance["segment_ids"] - - max_seq_length = getenv('MAX_SEQ_LENGTH', 512) - - assert len(input_ids) <= max_seq_length - while len(input_ids) < max_seq_length: - input_ids.append(0) - input_mask.append(0) - segment_ids.append(0) - assert len(input_ids) == max_seq_length - assert len(input_mask) == max_seq_length - assert len(segment_ids) == max_seq_length - - masked_lm_positions = instance["masked_lm_positions"] - masked_lm_ids = tokenizer.convert_tokens_to_ids(instance["masked_lm_labels"]) - masked_lm_weights = [1.0] * len(masked_lm_ids) - - while len(masked_lm_positions) < getenv("MAX_PREDICTIONS_PER_SEQ", 76): - masked_lm_positions.append(0) - masked_lm_ids.append(0) - masked_lm_weights.append(0.0) - - next_sentence_label = 1 if instance["is_random_next"] else 0 - - return { - "input_ids": np.expand_dims(np.array(input_ids, dtype=np.int32), 0), - "input_mask": np.expand_dims(np.array(input_mask, dtype=np.int32), 0), - "segment_ids": np.expand_dims(np.array(segment_ids, dtype=np.int32), 0), - "masked_lm_positions": np.expand_dims(np.array(masked_lm_positions, dtype=np.int32), 0), - "masked_lm_ids": np.expand_dims(np.array(masked_lm_ids, dtype=np.int32), 0), - "masked_lm_weights": np.expand_dims(np.array(masked_lm_weights, dtype=np.float32), 0), - "next_sentence_labels": np.expand_dims(np.array([next_sentence_label], dtype=np.int32), 0), - } - -def process_part(part:int): - tokenizer = Tokenizer(getenv("BASEDIR", Path(__file__).parent / "wiki") / "vocab.txt") - os.makedirs(BASEDIR / "train", exist_ok=True) - - if os.path.exists(BASEDIR / f"train/{str(part)}.pkl"): return - features = get_features_from_part(tokenizer, val=False, part=part) - with open(BASEDIR / f"train/{str(part)}.pkl", "wb") as f: - pickle.dump(features, f) - -def get_features_from_part(tokenizer:Tokenizer, val:bool=False, part:int=0) -> list[dict]: # Convert raw text to masked NSP samples - rng = random.Random(getenv('RANDOM_SEED', 12345)) - - if val: - tqdm.write("Getting samples from dataset") - documents = get_documents(rng, tokenizer, "results4/eval.txt") - instances = get_instances(rng, tokenizer, documents) - - tqdm.write(f"There are {len(instances)} samples in the dataset") - tqdm.write(f"Picking 10000 samples") - - pick_ratio = len(instances) / 10000 - return [instance_to_features(instances[int(inst*pick_ratio)], tokenizer) for inst in range(10000)] - else: - documents = get_documents(rng, tokenizer, f"results4/part-{part:05d}-of-00500") - instances = get_instances(rng, tokenizer, documents) - return [instance_to_features(instance, tokenizer) for instance in instances] - -##################### Load files ##################### - -@diskcache -def get_wiki_train_files(): return sorted(list((BASEDIR / "train/").glob("*.pkl"))) - -if __name__ == "__main__": - tokenizer = Tokenizer(getenv("BASEDIR", Path(__file__).parent / "wiki") / "vocab.txt") - - assert len(sys.argv) > 1, "Usage: python wikipedia.py pre-eval|pre-train [part]|all" - - if sys.argv[1] == "pre-eval": # Generate 10000 eval samples - with open(BASEDIR / "eval.pkl", "wb") as f: - pickle.dump(get_features_from_part(tokenizer, val=True), f) - elif sys.argv[1] == "pre-train": - if sys.argv[2] == "all": # Use all 500 parts for training generation - process_map(process_part, [part for part in range(500)], max_workers=getenv('NUM_WORKERS', min(os.cpu_count(), 32)), chunksize=1) - else: # Use a specific part for training generation - part = sys.argv[2] - print(f"Processing part {part}...") - process_part(int(part)) diff --git a/tinygrad/extra/datasets/wikipedia_download.py b/tinygrad/extra/datasets/wikipedia_download.py deleted file mode 100644 index 50e7b3c1..00000000 --- a/tinygrad/extra/datasets/wikipedia_download.py +++ /dev/null @@ -1,54 +0,0 @@ -# pip install gdown -# Downloads the 2020 wikipedia dataset used for MLPerf BERT training -import os, hashlib -from pathlib import Path -import tarfile -import gdown -from tqdm import tqdm -from tinygrad.helpers import getenv - -def gdrive_download(url:str, path:str): - if not os.path.exists(path): gdown.download(url, path) - -def wikipedia_uncompress_and_extract(file:str, path:str, small:bool=False): - if not os.path.exists(os.path.join(path, "results4")): - print("Uncompressing and extracting file...") - with tarfile.open(file, 'r:gz') as tar: - tar.extractall(path=path) - os.remove(file) - if small: - for member in tar.getmembers(): tar.extract(path=path, member=member) - else: - for member in tqdm(iterable=tar.getmembers(), total=len(tar.getmembers())): tar.extract(path=path, member=member) - -def verify_checksum(folder_path:str, checksum_path:str): - print("Verifying checksums...") - with open(checksum_path, 'r') as f: - for line in f: - expected_checksum, folder_name = line.split() - file_path = os.path.join(folder_path, folder_name[2:]) # remove './' from the start of the folder name - hasher = hashlib.md5() - with open(file_path, 'rb') as f: - for buf in iter(lambda: f.read(4096), b''): hasher.update(buf) - if hasher.hexdigest() != expected_checksum: - raise ValueError(f"Checksum does not match for file: {file_path}") - print("All checksums match.") - -def download_wikipedia(path:str): - # Links from: https://github.com/mlcommons/training/blob/master/language_model/tensorflow/bert/dataset.md - os.makedirs(path, exist_ok=True) - gdrive_download("https://drive.google.com/uc?id=1fbGClQMi2CoMv7fwrwTC5YYPooQBdcFW", os.path.join(path, "bert_config.json")) - gdrive_download("https://drive.google.com/uc?id=1USK108J6hMM_d27xCHi738qBL8_BT1u1", os.path.join(path, "vocab.txt")) - gdrive_download("https://drive.google.com/uc?id=1chiTBljF0Eh1U5pKs6ureVHgSbtU8OG_", os.path.join(path, "model.ckpt-28252.data-00000-of-00001")) - gdrive_download("https://drive.google.com/uc?id=1Q47V3K3jFRkbJ2zGCrKkKk-n0fvMZsa0", os.path.join(path, "model.ckpt-28252.index")) - gdrive_download("https://drive.google.com/uc?id=1vAcVmXSLsLeQ1q7gvHnQUSth5W_f_pwv", os.path.join(path, "model.ckpt-28252.meta")) - with open(os.path.join(path, "checkpoint"), "w") as f: f.write('model_checkpoint_path: "model.ckpt-28252"\nall_model_checkpoint_paths: "model.ckpt-28252"') - if getenv("WIKI_TRAIN", 0): - gdrive_download("https://drive.google.com/uc?id=1tmMgLwoBvbEJEHXh77sqrXYw5RpqT8R_", os.path.join(path, "bert_reference_results_text_md5.txt")) - gdrive_download("https://drive.google.com/uc?id=14xV2OUGSQDG_yDBrmbSdcDC-QGeqpfs_", os.path.join(path, "results_text.tar.gz")) - wikipedia_uncompress_and_extract(os.path.join(path, "results_text.tar.gz"), path) - if getenv("VERIFY_CHECKSUM", 0): - verify_checksum(os.path.join(path, "results4"), os.path.join(path, "bert_reference_results_text_md5.txt")) - -if __name__ == "__main__": - download_wikipedia(getenv("BASEDIR", os.path.join(Path(__file__).parent / "wiki"))) \ No newline at end of file diff --git a/tinygrad/extra/disassemblers/adreno/.gitignore b/tinygrad/extra/disassemblers/adreno/.gitignore deleted file mode 100644 index 40e68186..00000000 --- a/tinygrad/extra/disassemblers/adreno/.gitignore +++ /dev/null @@ -1 +0,0 @@ -disasm.so \ No newline at end of file diff --git a/tinygrad/extra/disassemblers/adreno/README b/tinygrad/extra/disassemblers/adreno/README deleted file mode 100644 index 2a534d47..00000000 --- a/tinygrad/extra/disassemblers/adreno/README +++ /dev/null @@ -1,5 +0,0 @@ -From the Freedreno project - -https://gallium.readthedocs.io/en/latest/gallium/drivers/freedreno.html - -In Mesa3D, so licensed MIT. diff --git a/tinygrad/extra/disassemblers/adreno/__init__.py b/tinygrad/extra/disassemblers/adreno/__init__.py deleted file mode 100644 index 71974b72..00000000 --- a/tinygrad/extra/disassemblers/adreno/__init__.py +++ /dev/null @@ -1,22 +0,0 @@ -import ctypes -import os -import pathlib -import struct -from hexdump import hexdump - -fxn = None -def disasm_raw(buf): - global fxn - if fxn is None: - shared = pathlib.Path(__file__).parent / "disasm.so" - if not shared.is_file(): - os.system(f'cd {pathlib.Path(__file__).parent} && gcc -shared disasm-a3xx.c -o disasm.so') - fxn = ctypes.CDLL(shared.as_posix())['disasm'] - fxn(buf, len(buf)) - -def disasm(buf): - def _read_lib(off): return struct.unpack("I", buf[off:off+4])[0] - - image_offset = _read_lib(0xc0) - image_size = _read_lib(0x100) - disasm_raw(buf[image_offset:image_offset+image_size]) diff --git a/tinygrad/extra/disassemblers/adreno/disasm-a3xx.c b/tinygrad/extra/disassemblers/adreno/disasm-a3xx.c deleted file mode 100644 index 71152899..00000000 --- a/tinygrad/extra/disassemblers/adreno/disasm-a3xx.c +++ /dev/null @@ -1,1431 +0,0 @@ -/* - * Copyright (c) 2013 Rob Clark - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -//#include - -#include "util/macros.h" -#include "instr-a3xx.h" - -/* bitmask of debug flags */ -enum debug_t { - PRINT_RAW = 0x1, /* dump raw hexdump */ - PRINT_VERBOSE = 0x2, - EXPAND_REPEAT = 0x4, -}; - -static enum debug_t debug = PRINT_RAW | PRINT_VERBOSE | EXPAND_REPEAT; - -static const char *levels[] = { - "", - "\t", - "\t\t", - "\t\t\t", - "\t\t\t\t", - "\t\t\t\t\t", - "\t\t\t\t\t\t", - "\t\t\t\t\t\t\t", - "\t\t\t\t\t\t\t\t", - "\t\t\t\t\t\t\t\t\t", - "x", - "x", - "x", - "x", - "x", - "x", -}; - -static const char *component = "xyzw"; - -static const char *type[] = { - [TYPE_F16] = "f16", - [TYPE_F32] = "f32", - [TYPE_U16] = "u16", - [TYPE_U32] = "u32", - [TYPE_S16] = "s16", - [TYPE_S32] = "s32", - [TYPE_U8] = "u8", - [TYPE_S8] = "s8", -}; - -struct disasm_ctx { - FILE *out; - int level; - unsigned gpu_id; - - /* current instruction repeat flag: */ - unsigned repeat; - /* current instruction repeat indx/offset (for --expand): */ - unsigned repeatidx; - - unsigned instructions; -}; - -static const char *float_imms[] = { - "0.0", - "0.5", - "1.0", - "2.0", - "e", - "pi", - "1/pi", - "1/log2(e)", - "log2(e)", - "1/log2(10)", - "log2(10)", - "4.0", -}; - -static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full, - bool is_float, bool r, - bool c, bool im, bool neg, bool abs, bool addr_rel) -{ - const char type = c ? 'c' : 'r'; - - // XXX I prefer - and || for neg/abs, but preserving format used - // by libllvm-a3xx for easy diffing.. - - if (abs && neg) - fprintf(ctx->out, "(absneg)"); - else if (neg) - fprintf(ctx->out, "(neg)"); - else if (abs) - fprintf(ctx->out, "(abs)"); - - if (r) - fprintf(ctx->out, "(r)"); - - if (im) { - if (is_float && full && reg.iim_val < ARRAY_SIZE(float_imms)) { - fprintf(ctx->out, "(%s)", float_imms[reg.iim_val]); - } else { - fprintf(ctx->out, "%d", reg.iim_val); - } - } else if (addr_rel) { - /* I would just use %+d but trying to make it diff'able with - * libllvm-a3xx... - */ - if (reg.iim_val < 0) - fprintf(ctx->out, "%s%c", full ? "" : "h", type, -reg.iim_val); - else if (reg.iim_val > 0) - fprintf(ctx->out, "%s%c", full ? "" : "h", type, reg.iim_val); - else - fprintf(ctx->out, "%s%c", full ? "" : "h", type); - } else if ((reg.num == REG_A0) && !c) { - /* This matches libllvm output, the second (scalar) address register - * seems to be called a1.x instead of a0.y. - */ - fprintf(ctx->out, "a%d.x", reg.comp); - } else if ((reg.num == REG_P0) && !c) { - fprintf(ctx->out, "p0.%c", component[reg.comp]); - } else { - fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]); - } -} - -static unsigned regidx(reg_t reg) -{ - return (4 * reg.num) + reg.comp; -} - -static reg_t idxreg(unsigned idx) -{ - return (reg_t){ - .comp = idx & 0x3, - .num = idx >> 2, - }; -} - -static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel) -{ - reg = idxreg(regidx(reg) + ctx->repeatidx); - print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel); -} - -/* TODO switch to using reginfo struct everywhere, since more readable - * than passing a bunch of bools to print_reg_src - */ - -struct reginfo { - reg_t reg; - bool full; - bool r; - bool c; - bool f; /* src reg is interpreted as float, used for printing immediates */ - bool im; - bool neg; - bool abs; - bool addr_rel; -}; - -static void print_src(struct disasm_ctx *ctx, struct reginfo *info) -{ - reg_t reg = info->reg; - - if (info->r) - reg = idxreg(regidx(info->reg) + ctx->repeatidx); - - print_reg(ctx, reg, info->full, info->f, info->r, info->c, info->im, - info->neg, info->abs, info->addr_rel); -} - -//static void print_dst(struct disasm_ctx *ctx, struct reginfo *info) -//{ -// print_reg_dst(ctx, info->reg, info->full, info->addr_rel); -//} - -static void print_instr_cat0(struct disasm_ctx *ctx, instr_t *instr) -{ - static const struct { - const char *suffix; - int nsrc; - bool idx; - } brinfo[7] = { - [BRANCH_PLAIN] = { "r", 1, false }, - [BRANCH_OR] = { "rao", 2, false }, - [BRANCH_AND] = { "raa", 2, false }, - [BRANCH_CONST] = { "rac", 0, true }, - [BRANCH_ANY] = { "any", 1, false }, - [BRANCH_ALL] = { "all", 1, false }, - [BRANCH_X] = { "rax", 0, false }, - }; - instr_cat0_t *cat0 = &instr->cat0; - - switch (instr_opc(instr, ctx->gpu_id)) { - case OPC_KILL: - case OPC_PREDT: - case OPC_PREDF: - fprintf(ctx->out, " %sp0.%c", cat0->inv0 ? "!" : "", - component[cat0->comp0]); - break; - case OPC_B: - fprintf(ctx->out, "%s", brinfo[cat0->brtype].suffix); - if (brinfo[cat0->brtype].idx) { - fprintf(ctx->out, ".%u", cat0->idx); - } - if (brinfo[cat0->brtype].nsrc >= 1) { - fprintf(ctx->out, " %sp0.%c,", cat0->inv0 ? "!" : "", - component[cat0->comp0]); - } - if (brinfo[cat0->brtype].nsrc >= 2) { - fprintf(ctx->out, " %sp0.%c,", cat0->inv1 ? "!" : "", - component[cat0->comp1]); - } - fprintf(ctx->out, " #%d", cat0->a3xx.immed); - break; - case OPC_JUMP: - case OPC_CALL: - case OPC_BKT: - case OPC_GETONE: - case OPC_SHPS: - fprintf(ctx->out, " #%d", cat0->a3xx.immed); - break; - } - - if ((debug & PRINT_VERBOSE) && (cat0->dummy3|cat0->dummy4)) - fprintf(ctx->out, "\t{0: %x,%x}", cat0->dummy3, cat0->dummy4); -} - -static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat1_t *cat1 = &instr->cat1; - - if (cat1->ul) - fprintf(ctx->out, "(ul)"); - - if (cat1->src_type == cat1->dst_type) { - if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) { - /* special case (nmemonic?): */ - fprintf(ctx->out, "mova"); - } else { - fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]); - } - } else { - fprintf(ctx->out, "cov.%s%s", type[cat1->src_type], type[cat1->dst_type]); - } - - fprintf(ctx->out, " "); - - if (cat1->even) - fprintf(ctx->out, "(even)"); - - if (cat1->pos_inf) - fprintf(ctx->out, "(pos_infinity)"); - - print_reg_dst(ctx, (reg_t)(cat1->dst), type_size(cat1->dst_type) == 32, - cat1->dst_rel); - - fprintf(ctx->out, ", "); - - /* ugg, have to special case this.. vs print_reg().. */ - if (cat1->src_im) { - if (type_float(cat1->src_type)) - fprintf(ctx->out, "(%f)", cat1->fim_val); - else if (type_uint(cat1->src_type)) - fprintf(ctx->out, "0x%08x", cat1->uim_val); - else - fprintf(ctx->out, "%d", cat1->iim_val); - } else if (cat1->src_rel && !cat1->src_c) { - /* I would just use %+d but trying to make it diff'able with - * libllvm-a3xx... - */ - char type = cat1->src_rel_c ? 'c' : 'r'; - const char *full = (type_size(cat1->src_type) == 32) ? "" : "h"; - if (cat1->off < 0) - fprintf(ctx->out, "%s%c", full, type, -cat1->off); - else if (cat1->off > 0) - fprintf(ctx->out, "%s%c", full, type, cat1->off); - else - fprintf(ctx->out, "%s%c", full, type); - } else { - struct reginfo src = { - .reg = (reg_t)cat1->src, - .full = type_size(cat1->src_type) == 32, - .r = cat1->src_r, - .c = cat1->src_c, - .im = cat1->src_im, - }; - print_src(ctx, &src); - } - - if ((debug & PRINT_VERBOSE) && (cat1->must_be_0)) - fprintf(ctx->out, "\t{1: %x}", cat1->must_be_0); -} - -static void print_instr_cat2(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat2_t *cat2 = &instr->cat2; - int opc = _OPC(2, cat2->opc); - static const char *cond[] = { - "lt", - "le", - "gt", - "ge", - "eq", - "ne", - "?6?", - }; - - switch (opc) { - case OPC_CMPS_F: - case OPC_CMPS_U: - case OPC_CMPS_S: - case OPC_CMPV_F: - case OPC_CMPV_U: - case OPC_CMPV_S: - fprintf(ctx->out, ".%s", cond[cat2->cond]); - break; - } - - fprintf(ctx->out, " "); - if (cat2->ei) - fprintf(ctx->out, "(ei)"); - print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false); - fprintf(ctx->out, ", "); - - struct reginfo src1 = { - .full = cat2->full, - .r = cat2->repeat ? cat2->src1_r : 0, - .f = is_cat2_float(opc), - .im = cat2->src1_im, - .abs = cat2->src1_abs, - .neg = cat2->src1_neg, - }; - - if (cat2->c1.src1_c) { - src1.reg = (reg_t)(cat2->c1.src1); - src1.c = true; - } else if (cat2->rel1.src1_rel) { - src1.reg = (reg_t)(cat2->rel1.src1); - src1.c = cat2->rel1.src1_c; - src1.addr_rel = true; - } else { - src1.reg = (reg_t)(cat2->src1); - } - print_src(ctx, &src1); - - struct reginfo src2 = { - .r = cat2->repeat ? cat2->src2_r : 0, - .full = cat2->full, - .f = is_cat2_float(opc), - .abs = cat2->src2_abs, - .neg = cat2->src2_neg, - .im = cat2->src2_im, - }; - switch (opc) { - case OPC_ABSNEG_F: - case OPC_ABSNEG_S: - case OPC_CLZ_B: - case OPC_CLZ_S: - case OPC_SIGN_F: - case OPC_FLOOR_F: - case OPC_CEIL_F: - case OPC_RNDNE_F: - case OPC_RNDAZ_F: - case OPC_TRUNC_F: - case OPC_NOT_B: - case OPC_BFREV_B: - case OPC_SETRM: - case OPC_CBITS_B: - /* these only have one src reg */ - break; - default: - fprintf(ctx->out, ", "); - if (cat2->c2.src2_c) { - src2.reg = (reg_t)(cat2->c2.src2); - src2.c = true; - } else if (cat2->rel2.src2_rel) { - src2.reg = (reg_t)(cat2->rel2.src2); - src2.c = cat2->rel2.src2_c; - src2.addr_rel = true; - } else { - src2.reg = (reg_t)(cat2->src2); - } - print_src(ctx, &src2); - break; - } -} - -static void print_instr_cat3(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat3_t *cat3 = &instr->cat3; - bool full = instr_cat3_full(cat3); - - fprintf(ctx->out, " "); - print_reg_dst(ctx, (reg_t)(cat3->dst), full ^ cat3->dst_half, false); - fprintf(ctx->out, ", "); - - struct reginfo src1 = { - .r = cat3->repeat ? cat3->src1_r : 0, - .full = full, - .neg = cat3->src1_neg, - }; - if (cat3->c1.src1_c) { - src1.reg = (reg_t)(cat3->c1.src1); - src1.c = true; - } else if (cat3->rel1.src1_rel) { - src1.reg = (reg_t)(cat3->rel1.src1); - src1.c = cat3->rel1.src1_c; - src1.addr_rel = true; - } else { - src1.reg = (reg_t)(cat3->src1); - } - print_src(ctx, &src1); - - fprintf(ctx->out, ", "); - struct reginfo src2 = { - .reg = (reg_t)cat3->src2, - .full = full, - .r = cat3->repeat ? cat3->src2_r : 0, - .c = cat3->src2_c, - .neg = cat3->src2_neg, - }; - print_src(ctx, &src2); - - fprintf(ctx->out, ", "); - struct reginfo src3 = { - .r = cat3->src3_r, - .full = full, - .neg = cat3->src3_neg, - }; - if (cat3->c2.src3_c) { - src3.reg = (reg_t)(cat3->c2.src3); - src3.c = true; - } else if (cat3->rel2.src3_rel) { - src3.reg = (reg_t)(cat3->rel2.src3); - src3.c = cat3->rel2.src3_c; - src3.addr_rel = true; - } else { - src3.reg = (reg_t)(cat3->src3); - } - print_src(ctx, &src3); -} - -static void print_instr_cat4(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat4_t *cat4 = &instr->cat4; - - fprintf(ctx->out, " "); - print_reg_dst(ctx, (reg_t)(cat4->dst), cat4->full ^ cat4->dst_half, false); - fprintf(ctx->out, ", "); - - struct reginfo src = { - .r = cat4->src_r, - .im = cat4->src_im, - .full = cat4->full, - .neg = cat4->src_neg, - .abs = cat4->src_abs, - }; - if (cat4->c.src_c) { - src.reg = (reg_t)(cat4->c.src); - src.c = true; - } else if (cat4->rel.src_rel) { - src.reg = (reg_t)(cat4->rel.src); - src.c = cat4->rel.src_c; - src.addr_rel = true; - } else { - src.reg = (reg_t)(cat4->src); - } - print_src(ctx, &src); - - if ((debug & PRINT_VERBOSE) && (cat4->dummy1|cat4->dummy2)) - fprintf(ctx->out, "\t{4: %x,%x}", cat4->dummy1, cat4->dummy2); -} - -static void print_instr_cat5(struct disasm_ctx *ctx, instr_t *instr) -{ - static const struct { - bool src1, src2, samp, tex; - } info[0x1f] = { - [opc_op(OPC_ISAM)] = { true, false, true, true, }, - [opc_op(OPC_ISAML)] = { true, true, true, true, }, - [opc_op(OPC_ISAMM)] = { true, false, true, true, }, - [opc_op(OPC_SAM)] = { true, false, true, true, }, - [opc_op(OPC_SAMB)] = { true, true, true, true, }, - [opc_op(OPC_SAML)] = { true, true, true, true, }, - [opc_op(OPC_SAMGQ)] = { true, false, true, true, }, - [opc_op(OPC_GETLOD)] = { true, false, true, true, }, - [opc_op(OPC_CONV)] = { true, true, true, true, }, - [opc_op(OPC_CONVM)] = { true, true, true, true, }, - [opc_op(OPC_GETSIZE)] = { true, false, false, true, }, - [opc_op(OPC_GETBUF)] = { false, false, false, true, }, - [opc_op(OPC_GETPOS)] = { true, false, false, true, }, - [opc_op(OPC_GETINFO)] = { false, false, false, true, }, - [opc_op(OPC_DSX)] = { true, false, false, false, }, - [opc_op(OPC_DSY)] = { true, false, false, false, }, - [opc_op(OPC_GATHER4R)] = { true, false, true, true, }, - [opc_op(OPC_GATHER4G)] = { true, false, true, true, }, - [opc_op(OPC_GATHER4B)] = { true, false, true, true, }, - [opc_op(OPC_GATHER4A)] = { true, false, true, true, }, - [opc_op(OPC_SAMGP0)] = { true, false, true, true, }, - [opc_op(OPC_SAMGP1)] = { true, false, true, true, }, - [opc_op(OPC_SAMGP2)] = { true, false, true, true, }, - [opc_op(OPC_SAMGP3)] = { true, false, true, true, }, - [opc_op(OPC_DSXPP_1)] = { true, false, false, false, }, - [opc_op(OPC_DSYPP_1)] = { true, false, false, false, }, - [opc_op(OPC_RGETPOS)] = { true, false, false, false, }, - [opc_op(OPC_RGETINFO)] = { false, false, false, false, }, - }; - - static const struct { - bool indirect; - bool bindless; - bool use_a1; - bool uniform; - } desc_features[8] = { - [CAT5_NONUNIFORM] = { .indirect = true, }, - [CAT5_UNIFORM] = { .indirect = true, .uniform = true, }, - [CAT5_BINDLESS_IMM] = { .bindless = true, }, - [CAT5_BINDLESS_UNIFORM] = { - .bindless = true, - .indirect = true, - .uniform = true, - }, - [CAT5_BINDLESS_NONUNIFORM] = { - .bindless = true, - .indirect = true, - }, - [CAT5_BINDLESS_A1_IMM] = { - .bindless = true, - .use_a1 = true, - }, - [CAT5_BINDLESS_A1_UNIFORM] = { - .bindless = true, - .indirect = true, - .uniform = true, - .use_a1 = true, - }, - [CAT5_BINDLESS_A1_NONUNIFORM] = { - .bindless = true, - .indirect = true, - .use_a1 = true, - }, - }; - - instr_cat5_t *cat5 = &instr->cat5; - int i; - - bool desc_indirect = - cat5->is_s2en_bindless && - desc_features[cat5->s2en_bindless.desc_mode].indirect; - bool bindless = - cat5->is_s2en_bindless && - desc_features[cat5->s2en_bindless.desc_mode].bindless; - bool use_a1 = - cat5->is_s2en_bindless && - desc_features[cat5->s2en_bindless.desc_mode].use_a1; - bool uniform = - cat5->is_s2en_bindless && - desc_features[cat5->s2en_bindless.desc_mode].uniform; - - if (cat5->is_3d) fprintf(ctx->out, ".3d"); - if (cat5->is_a) fprintf(ctx->out, ".a"); - if (cat5->is_o) fprintf(ctx->out, ".o"); - if (cat5->is_p) fprintf(ctx->out, ".p"); - if (cat5->is_s) fprintf(ctx->out, ".s"); - if (desc_indirect) fprintf(ctx->out, ".s2en"); - if (uniform) fprintf(ctx->out, ".uniform"); - - if (bindless) { - unsigned base = (cat5->s2en_bindless.base_hi << 1) | cat5->base_lo; - fprintf(ctx->out, ".base%d", base); - } - - fprintf(ctx->out, " "); - - switch (_OPC(5, cat5->opc)) { - case OPC_DSXPP_1: - case OPC_DSYPP_1: - break; - default: - fprintf(ctx->out, "(%s)", type[cat5->type]); - break; - } - - fprintf(ctx->out, "("); - for (i = 0; i < 4; i++) - if (cat5->wrmask & (1 << i)) - fprintf(ctx->out, "%c", "xyzw"[i]); - fprintf(ctx->out, ")"); - - print_reg_dst(ctx, (reg_t)(cat5->dst), type_size(cat5->type) == 32, false); - - if (info[cat5->opc].src1) { - fprintf(ctx->out, ", "); - struct reginfo src = { .reg = (reg_t)(cat5->src1), .full = cat5->full }; - print_src(ctx, &src); - } - - if (cat5->is_o || info[cat5->opc].src2) { - fprintf(ctx->out, ", "); - struct reginfo src = { .reg = (reg_t)(cat5->src2), .full = cat5->full }; - print_src(ctx, &src); - } - if (cat5->is_s2en_bindless) { - if (!desc_indirect) { - if (info[cat5->opc].samp) { - if (use_a1) - fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3); - else - fprintf(ctx->out, ", s#%d", cat5->s2en_bindless.src3 & 0xf); - } - - if (info[cat5->opc].tex && !use_a1) { - fprintf(ctx->out, ", t#%d", cat5->s2en_bindless.src3 >> 4); - } - } - } else { - if (info[cat5->opc].samp) - fprintf(ctx->out, ", s#%d", cat5->norm.samp); - if (info[cat5->opc].tex) - fprintf(ctx->out, ", t#%d", cat5->norm.tex); - } - - if (desc_indirect) { - fprintf(ctx->out, ", "); - struct reginfo src = { .reg = (reg_t)(cat5->s2en_bindless.src3), .full = bindless }; - print_src(ctx, &src); - } - - if (use_a1) - fprintf(ctx->out, ", a1.x"); - - if (debug & PRINT_VERBOSE) { - if (cat5->is_s2en_bindless) { - if ((debug & PRINT_VERBOSE) && cat5->s2en_bindless.dummy1) - fprintf(ctx->out, "\t{5: %x}", cat5->s2en_bindless.dummy1); - } else { - if ((debug & PRINT_VERBOSE) && cat5->norm.dummy1) - fprintf(ctx->out, "\t{5: %x}", cat5->norm.dummy1); - } - } -} - -static void print_instr_cat6_a3xx(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat6_t *cat6 = &instr->cat6; - char sd = 0, ss = 0; /* dst/src address space */ - bool nodst = false; - struct reginfo dst, src1, src2; - int src1off = 0, dstoff = 0; - - memset(&dst, 0, sizeof(dst)); - memset(&src1, 0, sizeof(src1)); - memset(&src2, 0, sizeof(src2)); - - switch (_OPC(6, cat6->opc)) { - case OPC_RESINFO: - case OPC_RESFMT: - dst.full = type_size(cat6->type) == 32; - src1.full = type_size(cat6->type) == 32; - src2.full = type_size(cat6->type) == 32; - break; - case OPC_L2G: - case OPC_G2L: - dst.full = true; - src1.full = true; - src2.full = true; - break; - case OPC_STG: - case OPC_STL: - case OPC_STP: - case OPC_STLW: - case OPC_STIB: - dst.full = type_size(cat6->type) == 32; - src1.full = type_size(cat6->type) == 32; - src2.full = type_size(cat6->type) == 32; - break; - default: - dst.full = type_size(cat6->type) == 32; - src1.full = true; - src2.full = true; - break; - } - - switch (_OPC(6, cat6->opc)) { - case OPC_PREFETCH: - break; - case OPC_RESINFO: - fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1); - break; - case OPC_LDGB: - fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped"); - fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1); - fprintf(ctx->out, ".%s", type[cat6->type]); - fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1); - break; - case OPC_STGB: - case OPC_STIB: - fprintf(ctx->out, ".%s", cat6->stgb.typed ? "typed" : "untyped"); - fprintf(ctx->out, ".%dd", cat6->stgb.d + 1); - fprintf(ctx->out, ".%s", type[cat6->type]); - fprintf(ctx->out, ".%d", cat6->stgb.type_size + 1); - break; - case OPC_ATOMIC_ADD: - case OPC_ATOMIC_SUB: - case OPC_ATOMIC_XCHG: - case OPC_ATOMIC_INC: - case OPC_ATOMIC_DEC: - case OPC_ATOMIC_CMPXCHG: - case OPC_ATOMIC_MIN: - case OPC_ATOMIC_MAX: - case OPC_ATOMIC_AND: - case OPC_ATOMIC_OR: - case OPC_ATOMIC_XOR: - ss = cat6->g ? 'g' : 'l'; - fprintf(ctx->out, ".%s", cat6->ldgb.typed ? "typed" : "untyped"); - fprintf(ctx->out, ".%dd", cat6->ldgb.d + 1); - fprintf(ctx->out, ".%s", type[cat6->type]); - fprintf(ctx->out, ".%d", cat6->ldgb.type_size + 1); - fprintf(ctx->out, ".%c", ss); - break; - default: - dst.im = cat6->g && !cat6->dst_off; - fprintf(ctx->out, ".%s", type[cat6->type]); - break; - } - fprintf(ctx->out, " "); - - switch (_OPC(6, cat6->opc)) { - case OPC_STG: - sd = 'g'; - break; - case OPC_STP: - sd = 'p'; - break; - case OPC_STL: - case OPC_STLW: - sd = 'l'; - break; - - case OPC_LDG: - case OPC_LDC: - ss = 'g'; - break; - case OPC_LDP: - ss = 'p'; - break; - case OPC_LDL: - case OPC_LDLW: - case OPC_LDLV: - ss = 'l'; - break; - - case OPC_L2G: - ss = 'l'; - sd = 'g'; - break; - - case OPC_G2L: - ss = 'g'; - sd = 'l'; - break; - - case OPC_PREFETCH: - ss = 'g'; - nodst = true; - break; - } - - if ((_OPC(6, cat6->opc) == OPC_STGB) || (_OPC(6, cat6->opc) == OPC_STIB)) { - struct reginfo src3; - - memset(&src3, 0, sizeof(src3)); - - src1.reg = (reg_t)(cat6->stgb.src1); - src2.reg = (reg_t)(cat6->stgb.src2); - src2.im = cat6->stgb.src2_im; - src3.reg = (reg_t)(cat6->stgb.src3); - src3.im = cat6->stgb.src3_im; - src3.full = true; - - fprintf(ctx->out, "g[%u], ", cat6->stgb.dst_ssbo); - print_src(ctx, &src1); - fprintf(ctx->out, ", "); - print_src(ctx, &src2); - fprintf(ctx->out, ", "); - print_src(ctx, &src3); - - if (debug & PRINT_VERBOSE) - fprintf(ctx->out, " (pad0=%x, pad3=%x)", cat6->stgb.pad0, cat6->stgb.pad3); - - return; - } - - if (is_atomic(_OPC(6, cat6->opc))) { - - src1.reg = (reg_t)(cat6->ldgb.src1); - src1.im = cat6->ldgb.src1_im; - src2.reg = (reg_t)(cat6->ldgb.src2); - src2.im = cat6->ldgb.src2_im; - dst.reg = (reg_t)(cat6->ldgb.dst); - - print_src(ctx, &dst); - fprintf(ctx->out, ", "); - if (ss == 'g') { - struct reginfo src3; - memset(&src3, 0, sizeof(src3)); - - src3.reg = (reg_t)(cat6->ldgb.src3); - src3.full = true; - - /* For images, the ".typed" variant is used and src2 is - * the ivecN coordinates, ie ivec2 for 2d. - * - * For SSBOs, the ".untyped" variant is used and src2 is - * a simple dword offset.. src3 appears to be - * uvec2(offset * 4, 0). Not sure the point of that. - */ - - fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo); - print_src(ctx, &src1); /* value */ - fprintf(ctx->out, ", "); - print_src(ctx, &src2); /* offset/coords */ - fprintf(ctx->out, ", "); - print_src(ctx, &src3); /* 64b byte offset.. */ - - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0, - cat6->ldgb.pad3, cat6->ldgb.mustbe0); - } - } else { /* ss == 'l' */ - fprintf(ctx->out, "l["); - print_src(ctx, &src1); /* simple byte offset */ - fprintf(ctx->out, "], "); - print_src(ctx, &src2); /* value */ - - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, " (src3=%x, pad0=%x, pad3=%x, mustbe0=%x)", - cat6->ldgb.src3, cat6->ldgb.pad0, - cat6->ldgb.pad3, cat6->ldgb.mustbe0); - } - } - - return; - } else if (_OPC(6, cat6->opc) == OPC_RESINFO) { - dst.reg = (reg_t)(cat6->ldgb.dst); - - print_src(ctx, &dst); - fprintf(ctx->out, ", "); - fprintf(ctx->out, "g[%u]", cat6->ldgb.src_ssbo); - - return; - } else if (_OPC(6, cat6->opc) == OPC_LDGB) { - - src1.reg = (reg_t)(cat6->ldgb.src1); - src1.im = cat6->ldgb.src1_im; - src2.reg = (reg_t)(cat6->ldgb.src2); - src2.im = cat6->ldgb.src2_im; - dst.reg = (reg_t)(cat6->ldgb.dst); - - print_src(ctx, &dst); - fprintf(ctx->out, ", "); - fprintf(ctx->out, "g[%u], ", cat6->ldgb.src_ssbo); - print_src(ctx, &src1); - fprintf(ctx->out, ", "); - print_src(ctx, &src2); - - if (debug & PRINT_VERBOSE) - fprintf(ctx->out, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6->ldgb.pad0, cat6->ldgb.pad3, cat6->ldgb.mustbe0); - - return; - } else if (_OPC(6, cat6->opc) == OPC_LDG && cat6->a.src1_im && cat6->a.src2_im) { - struct reginfo src3; - - memset(&src3, 0, sizeof(src3)); - src1.reg = (reg_t)(cat6->a.src1); - src2.reg = (reg_t)(cat6->a.src2); - src2.im = cat6->a.src2_im; - src3.reg = (reg_t)(cat6->a.off); - src3.full = true; - dst.reg = (reg_t)(cat6->d.dst); - - print_src(ctx, &dst); - fprintf(ctx->out, ", g["); - print_src(ctx, &src1); - fprintf(ctx->out, "+"); - print_src(ctx, &src3); - fprintf(ctx->out, "], "); - print_src(ctx, &src2); - - return; - } - if (cat6->dst_off) { - dst.reg = (reg_t)(cat6->c.dst); - dstoff = cat6->c.off; - } else { - dst.reg = (reg_t)(cat6->d.dst); - } - - if (cat6->src_off) { - src1.reg = (reg_t)(cat6->a.src1); - src1.im = cat6->a.src1_im; - src2.reg = (reg_t)(cat6->a.src2); - src2.im = cat6->a.src2_im; - src1off = cat6->a.off; - } else { - src1.reg = (reg_t)(cat6->b.src1); - src1.im = cat6->b.src1_im; - src2.reg = (reg_t)(cat6->b.src2); - src2.im = cat6->b.src2_im; - } - - if (!nodst) { - if (sd) - fprintf(ctx->out, "%c[", sd); - /* note: dst might actually be a src (ie. address to store to) */ - print_src(ctx, &dst); - if (cat6->dst_off && cat6->g) { - struct reginfo dstoff_reg = {0}; - dstoff_reg.reg = (reg_t) cat6->c.off; - dstoff_reg.full = true; - fprintf(ctx->out, "+"); - print_src(ctx, &dstoff_reg); - } else if (dstoff) - fprintf(ctx->out, "%+d", dstoff); - if (sd) - fprintf(ctx->out, "]"); - fprintf(ctx->out, ", "); - } - - if (ss) - fprintf(ctx->out, "%c[", ss); - - /* can have a larger than normal immed, so hack: */ - if (src1.im) { - fprintf(ctx->out, "%u", src1.reg.dummy13); - } else { - print_src(ctx, &src1); - } - - if (cat6->src_off && cat6->g) - print_src(ctx, &src2); - else if (src1off) - fprintf(ctx->out, "%+d", src1off); - if (ss) - fprintf(ctx->out, "]"); - - switch (_OPC(6, cat6->opc)) { - case OPC_RESINFO: - case OPC_RESFMT: - break; - default: - fprintf(ctx->out, ", "); - print_src(ctx, &src2); - break; - } -} - -static void print_instr_cat6_a6xx(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx; - struct reginfo src1, src2, ssbo; - bool uses_type = _OPC(6, cat6->opc) != OPC_LDC; - - static const struct { - bool indirect; - bool bindless; - const char *name; - } desc_features[8] = { - [CAT6_IMM] = { - .name = "imm" - }, - [CAT6_UNIFORM] = { - .indirect = true, - .name = "uniform" - }, - [CAT6_NONUNIFORM] = { - .indirect = true, - .name = "nonuniform" - }, - [CAT6_BINDLESS_IMM] = { - .bindless = true, - .name = "imm" - }, - [CAT6_BINDLESS_UNIFORM] = { - .bindless = true, - .indirect = true, - .name = "uniform" - }, - [CAT6_BINDLESS_NONUNIFORM] = { - .bindless = true, - .indirect = true, - .name = "nonuniform" - }, - }; - - bool indirect_ssbo = desc_features[cat6->desc_mode].indirect; - bool bindless = desc_features[cat6->desc_mode].bindless; - bool type_full = cat6->type != TYPE_U16; - - - memset(&src1, 0, sizeof(src1)); - memset(&src2, 0, sizeof(src2)); - memset(&ssbo, 0, sizeof(ssbo)); - - if (uses_type) { - fprintf(ctx->out, ".%s", cat6->typed ? "typed" : "untyped"); - fprintf(ctx->out, ".%dd", cat6->d + 1); - fprintf(ctx->out, ".%s", type[cat6->type]); - } else { - fprintf(ctx->out, ".offset%d", cat6->d); - } - fprintf(ctx->out, ".%u", cat6->type_size + 1); - - fprintf(ctx->out, ".%s", desc_features[cat6->desc_mode].name); - if (bindless) - fprintf(ctx->out, ".base%d", cat6->base); - fprintf(ctx->out, " "); - - src2.reg = (reg_t)(cat6->src2); - src2.full = type_full; - print_src(ctx, &src2); - fprintf(ctx->out, ", "); - - src1.reg = (reg_t)(cat6->src1); - src1.full = true; // XXX - print_src(ctx, &src1); - fprintf(ctx->out, ", "); - ssbo.reg = (reg_t)(cat6->ssbo); - ssbo.im = !indirect_ssbo; - ssbo.full = true; - print_src(ctx, &ssbo); - - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)", - cat6->pad1, cat6->pad2, cat6->pad3, cat6->pad4, cat6->pad5); - } -} - -static void print_instr_cat6(struct disasm_ctx *ctx, instr_t *instr) -{ - if (!is_cat6_legacy(instr, ctx->gpu_id)) { - print_instr_cat6_a6xx(ctx, instr); - if (debug & PRINT_VERBOSE) - fprintf(ctx->out, " NEW"); - } else { - print_instr_cat6_a3xx(ctx, instr); - if (debug & PRINT_VERBOSE) - fprintf(ctx->out, " LEGACY"); - } -} -static void print_instr_cat7(struct disasm_ctx *ctx, instr_t *instr) -{ - instr_cat7_t *cat7 = &instr->cat7; - - if (cat7->g) - fprintf(ctx->out, ".g"); - if (cat7->l) - fprintf(ctx->out, ".l"); - - if (_OPC(7, cat7->opc) == OPC_FENCE) { - if (cat7->r) - fprintf(ctx->out, ".r"); - if (cat7->w) - fprintf(ctx->out, ".w"); - } -} - -/* size of largest OPC field of all the instruction categories: */ -#define NOPC_BITS 6 - -static const struct opc_info { - uint16_t cat; - uint16_t opc; - const char *name; - void (*print)(struct disasm_ctx *ctx, instr_t *instr); -} opcs[1 << (3+NOPC_BITS)] = { -#define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat } - /* category 0: */ - OPC(0, OPC_NOP, nop), - OPC(0, OPC_B, b), - OPC(0, OPC_JUMP, jump), - OPC(0, OPC_CALL, call), - OPC(0, OPC_RET, ret), - OPC(0, OPC_KILL, kill), - OPC(0, OPC_END, end), - OPC(0, OPC_EMIT, emit), - OPC(0, OPC_CUT, cut), - OPC(0, OPC_CHMASK, chmask), - OPC(0, OPC_CHSH, chsh), - OPC(0, OPC_FLOW_REV, flow_rev), - OPC(0, OPC_PREDT, predt), - OPC(0, OPC_PREDF, predf), - OPC(0, OPC_PREDE, prede), - OPC(0, OPC_BKT, bkt), - OPC(0, OPC_STKS, stks), - OPC(0, OPC_STKR, stkr), - OPC(0, OPC_XSET, xset), - OPC(0, OPC_XCLR, xclr), - OPC(0, OPC_GETONE, getone), - OPC(0, OPC_DBG, dbg), - OPC(0, OPC_SHPS, shps), - OPC(0, OPC_SHPE, shpe), - - /* category 1: */ - OPC(1, OPC_MOV, ), - - /* category 2: */ - OPC(2, OPC_ADD_F, add.f), - OPC(2, OPC_MIN_F, min.f), - OPC(2, OPC_MAX_F, max.f), - OPC(2, OPC_MUL_F, mul.f), - OPC(2, OPC_SIGN_F, sign.f), - OPC(2, OPC_CMPS_F, cmps.f), - OPC(2, OPC_ABSNEG_F, absneg.f), - OPC(2, OPC_CMPV_F, cmpv.f), - OPC(2, OPC_FLOOR_F, floor.f), - OPC(2, OPC_CEIL_F, ceil.f), - OPC(2, OPC_RNDNE_F, rndne.f), - OPC(2, OPC_RNDAZ_F, rndaz.f), - OPC(2, OPC_TRUNC_F, trunc.f), - OPC(2, OPC_ADD_U, add.u), - OPC(2, OPC_ADD_S, add.s), - OPC(2, OPC_SUB_U, sub.u), - OPC(2, OPC_SUB_S, sub.s), - OPC(2, OPC_CMPS_U, cmps.u), - OPC(2, OPC_CMPS_S, cmps.s), - OPC(2, OPC_MIN_U, min.u), - OPC(2, OPC_MIN_S, min.s), - OPC(2, OPC_MAX_U, max.u), - OPC(2, OPC_MAX_S, max.s), - OPC(2, OPC_ABSNEG_S, absneg.s), - OPC(2, OPC_AND_B, and.b), - OPC(2, OPC_OR_B, or.b), - OPC(2, OPC_NOT_B, not.b), - OPC(2, OPC_XOR_B, xor.b), - OPC(2, OPC_CMPV_U, cmpv.u), - OPC(2, OPC_CMPV_S, cmpv.s), - OPC(2, OPC_MUL_U24, mul.u24), - OPC(2, OPC_MUL_S24, mul.s24), - OPC(2, OPC_MULL_U, mull.u), - OPC(2, OPC_BFREV_B, bfrev.b), - OPC(2, OPC_CLZ_S, clz.s), - OPC(2, OPC_CLZ_B, clz.b), - OPC(2, OPC_SHL_B, shl.b), - OPC(2, OPC_SHR_B, shr.b), - OPC(2, OPC_ASHR_B, ashr.b), - OPC(2, OPC_BARY_F, bary.f), - OPC(2, OPC_MGEN_B, mgen.b), - OPC(2, OPC_GETBIT_B, getbit.b), - OPC(2, OPC_SETRM, setrm), - OPC(2, OPC_CBITS_B, cbits.b), - OPC(2, OPC_SHB, shb), - OPC(2, OPC_MSAD, msad), - - /* category 3: */ - OPC(3, OPC_MAD_U16, mad.u16), - OPC(3, OPC_MADSH_U16, madsh.u16), - OPC(3, OPC_MAD_S16, mad.s16), - OPC(3, OPC_MADSH_M16, madsh.m16), - OPC(3, OPC_MAD_U24, mad.u24), - OPC(3, OPC_MAD_S24, mad.s24), - OPC(3, OPC_MAD_F16, mad.f16), - OPC(3, OPC_MAD_F32, mad.f32), - OPC(3, OPC_SEL_B16, sel.b16), - OPC(3, OPC_SEL_B32, sel.b32), - OPC(3, OPC_SEL_S16, sel.s16), - OPC(3, OPC_SEL_S32, sel.s32), - OPC(3, OPC_SEL_F16, sel.f16), - OPC(3, OPC_SEL_F32, sel.f32), - OPC(3, OPC_SAD_S16, sad.s16), - OPC(3, OPC_SAD_S32, sad.s32), - - /* category 4: */ - OPC(4, OPC_RCP, rcp), - OPC(4, OPC_RSQ, rsq), - OPC(4, OPC_LOG2, log2), - OPC(4, OPC_EXP2, exp2), - OPC(4, OPC_SIN, sin), - OPC(4, OPC_COS, cos), - OPC(4, OPC_SQRT, sqrt), - OPC(4, OPC_HRSQ, hrsq), - OPC(4, OPC_HLOG2, hlog2), - OPC(4, OPC_HEXP2, hexp2), - - /* category 5: */ - OPC(5, OPC_ISAM, isam), - OPC(5, OPC_ISAML, isaml), - OPC(5, OPC_ISAMM, isamm), - OPC(5, OPC_SAM, sam), - OPC(5, OPC_SAMB, samb), - OPC(5, OPC_SAML, saml), - OPC(5, OPC_SAMGQ, samgq), - OPC(5, OPC_GETLOD, getlod), - OPC(5, OPC_CONV, conv), - OPC(5, OPC_CONVM, convm), - OPC(5, OPC_GETSIZE, getsize), - OPC(5, OPC_GETBUF, getbuf), - OPC(5, OPC_GETPOS, getpos), - OPC(5, OPC_GETINFO, getinfo), - OPC(5, OPC_DSX, dsx), - OPC(5, OPC_DSY, dsy), - OPC(5, OPC_GATHER4R, gather4r), - OPC(5, OPC_GATHER4G, gather4g), - OPC(5, OPC_GATHER4B, gather4b), - OPC(5, OPC_GATHER4A, gather4a), - OPC(5, OPC_SAMGP0, samgp0), - OPC(5, OPC_SAMGP1, samgp1), - OPC(5, OPC_SAMGP2, samgp2), - OPC(5, OPC_SAMGP3, samgp3), - OPC(5, OPC_DSXPP_1, dsxpp.1), - OPC(5, OPC_DSYPP_1, dsypp.1), - OPC(5, OPC_RGETPOS, rgetpos), - OPC(5, OPC_RGETINFO, rgetinfo), - - - /* category 6: */ - OPC(6, OPC_LDG, ldg), - OPC(6, OPC_LDL, ldl), - OPC(6, OPC_LDP, ldp), - OPC(6, OPC_STG, stg), - OPC(6, OPC_STL, stl), - OPC(6, OPC_STP, stp), - OPC(6, OPC_LDIB, ldib), - OPC(6, OPC_G2L, g2l), - OPC(6, OPC_L2G, l2g), - OPC(6, OPC_PREFETCH, prefetch), - OPC(6, OPC_LDLW, ldlw), - OPC(6, OPC_STLW, stlw), - OPC(6, OPC_RESFMT, resfmt), - OPC(6, OPC_RESINFO, resinfo), - OPC(6, OPC_ATOMIC_ADD, atomic.add), - OPC(6, OPC_ATOMIC_SUB, atomic.sub), - OPC(6, OPC_ATOMIC_XCHG, atomic.xchg), - OPC(6, OPC_ATOMIC_INC, atomic.inc), - OPC(6, OPC_ATOMIC_DEC, atomic.dec), - OPC(6, OPC_ATOMIC_CMPXCHG, atomic.cmpxchg), - OPC(6, OPC_ATOMIC_MIN, atomic.min), - OPC(6, OPC_ATOMIC_MAX, atomic.max), - OPC(6, OPC_ATOMIC_AND, atomic.and), - OPC(6, OPC_ATOMIC_OR, atomic.or), - OPC(6, OPC_ATOMIC_XOR, atomic.xor), - OPC(6, OPC_LDGB, ldgb), - OPC(6, OPC_STGB, stgb), - OPC(6, OPC_STIB, stib), - OPC(6, OPC_LDC, ldc), - OPC(6, OPC_LDLV, ldlv), - - OPC(7, OPC_BAR, bar), - OPC(7, OPC_FENCE, fence), - -#undef OPC -}; - -#define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)])) - -// XXX hack.. probably should move this table somewhere common: -#include "ir3.h" -const char *ir3_instr_name(struct ir3_instruction *instr) -{ - if (opc_cat(instr->opc) == -1) return "??meta??"; - return opcs[instr->opc].name; -} - -static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr) -{ - const char *name = GETINFO(instr)->name; - uint32_t opc = instr_opc(instr, ctx->gpu_id); - - if (name) { - fprintf(ctx->out, "%s", name); - GETINFO(instr)->print(ctx, instr); - } else { - fprintf(ctx->out, "unknown(%d,%d)", instr->opc_cat, opc); - - switch (instr->opc_cat) { - case 0: print_instr_cat0(ctx, instr); break; - case 1: print_instr_cat1(ctx, instr); break; - case 2: print_instr_cat2(ctx, instr); break; - case 3: print_instr_cat3(ctx, instr); break; - case 4: print_instr_cat4(ctx, instr); break; - case 5: print_instr_cat5(ctx, instr); break; - case 6: print_instr_cat6(ctx, instr); break; - case 7: print_instr_cat7(ctx, instr); break; - } - } -} - -static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n) -{ - instr_t *instr = (instr_t *)dwords; - uint32_t opc = instr_opc(instr, ctx->gpu_id); - unsigned nop = 0; - unsigned cycles = ctx->instructions; - - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, "%s%04d:%04d[%08xx_%08xx] ", levels[ctx->level], - n, cycles++, dwords[1], dwords[0]); - } - - /* NOTE: order flags are printed is a bit fugly.. but for now I - * try to match the order in llvm-a3xx disassembler for easy - * diff'ing.. - */ - - ctx->repeat = instr_repeat(instr); - ctx->instructions += 1 + ctx->repeat; - - if (instr->sync) { - fprintf(ctx->out, "(sy)"); - } - if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) { - fprintf(ctx->out, "(ss)"); - } - if (instr->jmp_tgt) - fprintf(ctx->out, "(jp)"); - if ((instr->opc_cat == 0) && instr->cat0.eq) - fprintf(ctx->out, "(eq)"); - if (instr_sat(instr)) - fprintf(ctx->out, "(sat)"); - if (ctx->repeat) - fprintf(ctx->out, "(rpt%d)", ctx->repeat); - else if ((instr->opc_cat == 2) && (instr->cat2.src1_r || instr->cat2.src2_r)) - nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r; - else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r)) - nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r; - ctx->instructions += nop; - if (nop) - fprintf(ctx->out, "(nop%d) ", nop); - - if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4))) - fprintf(ctx->out, "(ul)"); - - print_single_instr(ctx, instr); - fprintf(ctx->out, "\n"); - - if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) { - int i; - for (i = 0; i < nop; i++) { - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, "%s%04d:%04d[ ] ", - levels[ctx->level], n, cycles++); - } - fprintf(ctx->out, "nop\n"); - } - for (i = 0; i < ctx->repeat; i++) { - ctx->repeatidx = i + 1; - if (debug & PRINT_VERBOSE) { - fprintf(ctx->out, "%s%04d:%04d[ ] ", - levels[ctx->level], n, cycles++); - } - print_single_instr(ctx, instr); - fprintf(ctx->out, "\n"); - } - ctx->repeatidx = 0; - } - - return (instr->opc_cat == 0) && (opc == OPC_END); -} - -int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id) -{ - struct disasm_ctx ctx; - int i; - int nop_count = 0; - - //assert((sizedwords % 2) == 0); - - memset(&ctx, 0, sizeof(ctx)); - ctx.out = out; - ctx.level = level; - ctx.gpu_id = gpu_id; - - for (i = 0; i < sizedwords; i += 2) { - print_instr(&ctx, &dwords[i], i/2); - if (dwords[i] == 0 && dwords[i + 1] == 0) - nop_count++; - else - nop_count = 0; - if (nop_count > 3) - break; - } - - return 0; -} - -// gcc -shared disasm-a3xx.c -o disasm.so -void disasm(uint8_t* buf, int len) { - disasm_a3xx((uint32_t*)buf, len/4, 0, stdout, 630); -} - -/*int main(int argc, char *argv[]) { - uint32_t buf[0x10000]; - FILE *f = fopen(argv[1], "rb"); - if (argc > 2) { - int seek = atoi(argv[2]); - printf("skip %d\n", seek); - fread(buf, 1, seek , f); - } - int len = fread(buf, 1, sizeof(buf), f); - fclose(f); - - disasm_a3xx(buf, len/4, 0, stdout, 630); -}*/ - diff --git a/tinygrad/extra/disassemblers/adreno/instr-a3xx.h b/tinygrad/extra/disassemblers/adreno/instr-a3xx.h deleted file mode 100644 index e4f548d6..00000000 --- a/tinygrad/extra/disassemblers/adreno/instr-a3xx.h +++ /dev/null @@ -1,1119 +0,0 @@ -/* - * Copyright (c) 2013 Rob Clark - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef INSTR_A3XX_H_ -#define INSTR_A3XX_H_ - -#define PACKED __attribute__((__packed__)) - -#include -#include -#include -#include - -/* size of largest OPC field of all the instruction categories: */ -#define NOPC_BITS 6 - -#define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) - -typedef enum { - /* category 0: */ - OPC_NOP = _OPC(0, 0), - OPC_B = _OPC(0, 1), - OPC_JUMP = _OPC(0, 2), - OPC_CALL = _OPC(0, 3), - OPC_RET = _OPC(0, 4), - OPC_KILL = _OPC(0, 5), - OPC_END = _OPC(0, 6), - OPC_EMIT = _OPC(0, 7), - OPC_CUT = _OPC(0, 8), - OPC_CHMASK = _OPC(0, 9), - OPC_CHSH = _OPC(0, 10), - OPC_FLOW_REV = _OPC(0, 11), - - OPC_BKT = _OPC(0, 16), - OPC_STKS = _OPC(0, 17), - OPC_STKR = _OPC(0, 18), - OPC_XSET = _OPC(0, 19), - OPC_XCLR = _OPC(0, 20), - OPC_GETONE = _OPC(0, 21), - OPC_DBG = _OPC(0, 22), - OPC_SHPS = _OPC(0, 23), /* shader prologue start */ - OPC_SHPE = _OPC(0, 24), /* shader prologue end */ - - OPC_PREDT = _OPC(0, 29), /* predicated true */ - OPC_PREDF = _OPC(0, 30), /* predicated false */ - OPC_PREDE = _OPC(0, 31), /* predicated end */ - - /* category 1: */ - OPC_MOV = _OPC(1, 0), - - /* category 2: */ - OPC_ADD_F = _OPC(2, 0), - OPC_MIN_F = _OPC(2, 1), - OPC_MAX_F = _OPC(2, 2), - OPC_MUL_F = _OPC(2, 3), - OPC_SIGN_F = _OPC(2, 4), - OPC_CMPS_F = _OPC(2, 5), - OPC_ABSNEG_F = _OPC(2, 6), - OPC_CMPV_F = _OPC(2, 7), - /* 8 - invalid */ - OPC_FLOOR_F = _OPC(2, 9), - OPC_CEIL_F = _OPC(2, 10), - OPC_RNDNE_F = _OPC(2, 11), - OPC_RNDAZ_F = _OPC(2, 12), - OPC_TRUNC_F = _OPC(2, 13), - /* 14-15 - invalid */ - OPC_ADD_U = _OPC(2, 16), - OPC_ADD_S = _OPC(2, 17), - OPC_SUB_U = _OPC(2, 18), - OPC_SUB_S = _OPC(2, 19), - OPC_CMPS_U = _OPC(2, 20), - OPC_CMPS_S = _OPC(2, 21), - OPC_MIN_U = _OPC(2, 22), - OPC_MIN_S = _OPC(2, 23), - OPC_MAX_U = _OPC(2, 24), - OPC_MAX_S = _OPC(2, 25), - OPC_ABSNEG_S = _OPC(2, 26), - /* 27 - invalid */ - OPC_AND_B = _OPC(2, 28), - OPC_OR_B = _OPC(2, 29), - OPC_NOT_B = _OPC(2, 30), - OPC_XOR_B = _OPC(2, 31), - /* 32 - invalid */ - OPC_CMPV_U = _OPC(2, 33), - OPC_CMPV_S = _OPC(2, 34), - /* 35-47 - invalid */ - OPC_MUL_U24 = _OPC(2, 48), /* 24b mul into 32b result */ - OPC_MUL_S24 = _OPC(2, 49), /* 24b mul into 32b result with sign extension */ - OPC_MULL_U = _OPC(2, 50), - OPC_BFREV_B = _OPC(2, 51), - OPC_CLZ_S = _OPC(2, 52), - OPC_CLZ_B = _OPC(2, 53), - OPC_SHL_B = _OPC(2, 54), - OPC_SHR_B = _OPC(2, 55), - OPC_ASHR_B = _OPC(2, 56), - OPC_BARY_F = _OPC(2, 57), - OPC_MGEN_B = _OPC(2, 58), - OPC_GETBIT_B = _OPC(2, 59), - OPC_SETRM = _OPC(2, 60), - OPC_CBITS_B = _OPC(2, 61), - OPC_SHB = _OPC(2, 62), - OPC_MSAD = _OPC(2, 63), - - /* category 3: */ - OPC_MAD_U16 = _OPC(3, 0), - OPC_MADSH_U16 = _OPC(3, 1), - OPC_MAD_S16 = _OPC(3, 2), - OPC_MADSH_M16 = _OPC(3, 3), /* should this be .s16? */ - OPC_MAD_U24 = _OPC(3, 4), - OPC_MAD_S24 = _OPC(3, 5), - OPC_MAD_F16 = _OPC(3, 6), - OPC_MAD_F32 = _OPC(3, 7), - OPC_SEL_B16 = _OPC(3, 8), - OPC_SEL_B32 = _OPC(3, 9), - OPC_SEL_S16 = _OPC(3, 10), - OPC_SEL_S32 = _OPC(3, 11), - OPC_SEL_F16 = _OPC(3, 12), - OPC_SEL_F32 = _OPC(3, 13), - OPC_SAD_S16 = _OPC(3, 14), - OPC_SAD_S32 = _OPC(3, 15), - - /* category 4: */ - OPC_RCP = _OPC(4, 0), - OPC_RSQ = _OPC(4, 1), - OPC_LOG2 = _OPC(4, 2), - OPC_EXP2 = _OPC(4, 3), - OPC_SIN = _OPC(4, 4), - OPC_COS = _OPC(4, 5), - OPC_SQRT = _OPC(4, 6), - /* NOTE that these are 8+opc from their highp equivs, so it's possible - * that the high order bit in the opc field has been repurposed for - * half-precision use? But note that other ops (rcp/lsin/cos/sqrt) - * still use the same opc as highp - */ - OPC_HRSQ = _OPC(4, 9), - OPC_HLOG2 = _OPC(4, 10), - OPC_HEXP2 = _OPC(4, 11), - - /* category 5: */ - OPC_ISAM = _OPC(5, 0), - OPC_ISAML = _OPC(5, 1), - OPC_ISAMM = _OPC(5, 2), - OPC_SAM = _OPC(5, 3), - OPC_SAMB = _OPC(5, 4), - OPC_SAML = _OPC(5, 5), - OPC_SAMGQ = _OPC(5, 6), - OPC_GETLOD = _OPC(5, 7), - OPC_CONV = _OPC(5, 8), - OPC_CONVM = _OPC(5, 9), - OPC_GETSIZE = _OPC(5, 10), - OPC_GETBUF = _OPC(5, 11), - OPC_GETPOS = _OPC(5, 12), - OPC_GETINFO = _OPC(5, 13), - OPC_DSX = _OPC(5, 14), - OPC_DSY = _OPC(5, 15), - OPC_GATHER4R = _OPC(5, 16), - OPC_GATHER4G = _OPC(5, 17), - OPC_GATHER4B = _OPC(5, 18), - OPC_GATHER4A = _OPC(5, 19), - OPC_SAMGP0 = _OPC(5, 20), - OPC_SAMGP1 = _OPC(5, 21), - OPC_SAMGP2 = _OPC(5, 22), - OPC_SAMGP3 = _OPC(5, 23), - OPC_DSXPP_1 = _OPC(5, 24), - OPC_DSYPP_1 = _OPC(5, 25), - OPC_RGETPOS = _OPC(5, 26), - OPC_RGETINFO = _OPC(5, 27), - - /* category 6: */ - OPC_LDG = _OPC(6, 0), /* load-global */ - OPC_LDL = _OPC(6, 1), - OPC_LDP = _OPC(6, 2), - OPC_STG = _OPC(6, 3), /* store-global */ - OPC_STL = _OPC(6, 4), - OPC_STP = _OPC(6, 5), - OPC_LDIB = _OPC(6, 6), - OPC_G2L = _OPC(6, 7), - OPC_L2G = _OPC(6, 8), - OPC_PREFETCH = _OPC(6, 9), - OPC_LDLW = _OPC(6, 10), - OPC_STLW = _OPC(6, 11), - OPC_RESFMT = _OPC(6, 14), - OPC_RESINFO = _OPC(6, 15), - OPC_ATOMIC_ADD = _OPC(6, 16), - OPC_ATOMIC_SUB = _OPC(6, 17), - OPC_ATOMIC_XCHG = _OPC(6, 18), - OPC_ATOMIC_INC = _OPC(6, 19), - OPC_ATOMIC_DEC = _OPC(6, 20), - OPC_ATOMIC_CMPXCHG = _OPC(6, 21), - OPC_ATOMIC_MIN = _OPC(6, 22), - OPC_ATOMIC_MAX = _OPC(6, 23), - OPC_ATOMIC_AND = _OPC(6, 24), - OPC_ATOMIC_OR = _OPC(6, 25), - OPC_ATOMIC_XOR = _OPC(6, 26), - OPC_LDGB = _OPC(6, 27), - OPC_STGB = _OPC(6, 28), - OPC_STIB = _OPC(6, 29), - OPC_LDC = _OPC(6, 30), - OPC_LDLV = _OPC(6, 31), - - /* category 7: */ - OPC_BAR = _OPC(7, 0), - OPC_FENCE = _OPC(7, 1), - - /* meta instructions (category -1): */ - /* placeholder instr to mark shader inputs: */ - OPC_META_INPUT = _OPC(-1, 0), - /* The "collect" and "split" instructions are used for keeping - * track of instructions that write to multiple dst registers - * (split) like texture sample instructions, or read multiple - * consecutive scalar registers (collect) (bary.f, texture samp) - * - * A "split" extracts a scalar component from a vecN, and a - * "collect" gathers multiple scalar components into a vecN - */ - OPC_META_SPLIT = _OPC(-1, 2), - OPC_META_COLLECT = _OPC(-1, 3), - - /* placeholder for texture fetches that run before FS invocation - * starts: - */ - OPC_META_TEX_PREFETCH = _OPC(-1, 4), - -} opc_t; - -#define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) -#define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) - -typedef enum { - TYPE_F16 = 0, - TYPE_F32 = 1, - TYPE_U16 = 2, - TYPE_U32 = 3, - TYPE_S16 = 4, - TYPE_S32 = 5, - TYPE_U8 = 6, - TYPE_S8 = 7, // XXX I assume? -} type_t; - -static inline uint32_t type_size(type_t type) -{ - switch (type) { - case TYPE_F32: - case TYPE_U32: - case TYPE_S32: - return 32; - case TYPE_F16: - case TYPE_U16: - case TYPE_S16: - return 16; - case TYPE_U8: - case TYPE_S8: - return 8; - default: - assert(0); /* invalid type */ - return 0; - } -} - -static inline int type_float(type_t type) -{ - return (type == TYPE_F32) || (type == TYPE_F16); -} - -static inline int type_uint(type_t type) -{ - return (type == TYPE_U32) || (type == TYPE_U16) || (type == TYPE_U8); -} - -static inline int type_sint(type_t type) -{ - return (type == TYPE_S32) || (type == TYPE_S16) || (type == TYPE_S8); -} - -typedef union PACKED { - /* normal gpr or const src register: */ - struct PACKED { - uint32_t comp : 2; - uint32_t num : 10; - }; - /* for immediate val: */ - int32_t iim_val : 11; - /* to make compiler happy: */ - uint32_t dummy32; - uint32_t dummy10 : 10; - int32_t idummy10 : 10; - uint32_t dummy11 : 11; - uint32_t dummy12 : 12; - uint32_t dummy13 : 13; - uint32_t dummy8 : 8; - int32_t idummy13 : 13; - int32_t idummy8 : 8; -} reg_t; - -/* special registers: */ -#define REG_A0 61 /* address register */ -#define REG_P0 62 /* predicate register */ - -static inline int reg_special(reg_t reg) -{ - return (reg.num == REG_A0) || (reg.num == REG_P0); -} - -typedef enum { - BRANCH_PLAIN = 0, /* br */ - BRANCH_OR = 1, /* brao */ - BRANCH_AND = 2, /* braa */ - BRANCH_CONST = 3, /* brac */ - BRANCH_ANY = 4, /* bany */ - BRANCH_ALL = 5, /* ball */ - BRANCH_X = 6, /* brax ??? */ -} brtype_t; - -typedef struct PACKED { - /* dword0: */ - union PACKED { - struct PACKED { - int16_t immed : 16; - uint32_t dummy1 : 16; - } a3xx; - struct PACKED { - int32_t immed : 20; - uint32_t dummy1 : 12; - } a4xx; - struct PACKED { - int32_t immed : 32; - } a5xx; - }; - - /* dword1: */ - uint32_t idx : 5; /* brac.N index */ - uint32_t brtype : 3; /* branch type, see brtype_t */ - uint32_t repeat : 3; - uint32_t dummy3 : 1; - uint32_t ss : 1; - uint32_t inv1 : 1; - uint32_t comp1 : 2; - uint32_t eq : 1; - uint32_t opc_hi : 1; /* at least one bit */ - uint32_t dummy4 : 2; - uint32_t inv0 : 1; - uint32_t comp0 : 2; /* component for first src */ - uint32_t opc : 4; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat0_t; - -typedef struct PACKED { - /* dword0: */ - union PACKED { - /* for normal src register: */ - struct PACKED { - uint32_t src : 11; - /* at least low bit of pad must be zero or it will - * look like a address relative src - */ - uint32_t pad : 21; - }; - /* for address relative: */ - struct PACKED { - int32_t off : 10; - uint32_t src_rel_c : 1; - uint32_t src_rel : 1; - uint32_t unknown : 20; - }; - /* for immediate: */ - int32_t iim_val; - uint32_t uim_val; - float fim_val; - }; - - /* dword1: */ - uint32_t dst : 8; - uint32_t repeat : 3; - uint32_t src_r : 1; - uint32_t ss : 1; - uint32_t ul : 1; - uint32_t dst_type : 3; - uint32_t dst_rel : 1; - uint32_t src_type : 3; - uint32_t src_c : 1; - uint32_t src_im : 1; - uint32_t even : 1; - uint32_t pos_inf : 1; - uint32_t must_be_0 : 2; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat1_t; - -typedef struct PACKED { - /* dword0: */ - union PACKED { - struct PACKED { - uint32_t src1 : 11; - uint32_t must_be_zero1: 2; - uint32_t src1_im : 1; /* immediate */ - uint32_t src1_neg : 1; /* negate */ - uint32_t src1_abs : 1; /* absolute value */ - }; - struct PACKED { - uint32_t src1 : 10; - uint32_t src1_c : 1; /* relative-const */ - uint32_t src1_rel : 1; /* relative address */ - uint32_t must_be_zero : 1; - uint32_t dummy : 3; - } rel1; - struct PACKED { - uint32_t src1 : 12; - uint32_t src1_c : 1; /* const */ - uint32_t dummy : 3; - } c1; - }; - - union PACKED { - struct PACKED { - uint32_t src2 : 11; - uint32_t must_be_zero2: 2; - uint32_t src2_im : 1; /* immediate */ - uint32_t src2_neg : 1; /* negate */ - uint32_t src2_abs : 1; /* absolute value */ - }; - struct PACKED { - uint32_t src2 : 10; - uint32_t src2_c : 1; /* relative-const */ - uint32_t src2_rel : 1; /* relative address */ - uint32_t must_be_zero : 1; - uint32_t dummy : 3; - } rel2; - struct PACKED { - uint32_t src2 : 12; - uint32_t src2_c : 1; /* const */ - uint32_t dummy : 3; - } c2; - }; - - /* dword1: */ - uint32_t dst : 8; - uint32_t repeat : 2; - uint32_t sat : 1; - uint32_t src1_r : 1; /* doubles as nop0 if repeat==0 */ - uint32_t ss : 1; - uint32_t ul : 1; /* dunno */ - uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */ - uint32_t ei : 1; - uint32_t cond : 3; - uint32_t src2_r : 1; /* doubles as nop1 if repeat==0 */ - uint32_t full : 1; /* not half */ - uint32_t opc : 6; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat2_t; - -typedef struct PACKED { - /* dword0: */ - union PACKED { - struct PACKED { - uint32_t src1 : 11; - uint32_t must_be_zero1: 2; - uint32_t src2_c : 1; - uint32_t src1_neg : 1; - uint32_t src2_r : 1; /* doubles as nop1 if repeat==0 */ - }; - struct PACKED { - uint32_t src1 : 10; - uint32_t src1_c : 1; - uint32_t src1_rel : 1; - uint32_t must_be_zero : 1; - uint32_t dummy : 3; - } rel1; - struct PACKED { - uint32_t src1 : 12; - uint32_t src1_c : 1; - uint32_t dummy : 3; - } c1; - }; - - union PACKED { - struct PACKED { - uint32_t src3 : 11; - uint32_t must_be_zero2: 2; - uint32_t src3_r : 1; - uint32_t src2_neg : 1; - uint32_t src3_neg : 1; - }; - struct PACKED { - uint32_t src3 : 10; - uint32_t src3_c : 1; - uint32_t src3_rel : 1; - uint32_t must_be_zero : 1; - uint32_t dummy : 3; - } rel2; - struct PACKED { - uint32_t src3 : 12; - uint32_t src3_c : 1; - uint32_t dummy : 3; - } c2; - }; - - /* dword1: */ - uint32_t dst : 8; - uint32_t repeat : 2; - uint32_t sat : 1; - uint32_t src1_r : 1; /* doubles as nop0 if repeat==0 */ - uint32_t ss : 1; - uint32_t ul : 1; - uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */ - uint32_t src2 : 8; - uint32_t opc : 4; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat3_t; - -static inline bool instr_cat3_full(instr_cat3_t *cat3) -{ - switch (_OPC(3, cat3->opc)) { - case OPC_MAD_F16: - case OPC_MAD_U16: - case OPC_MAD_S16: - case OPC_SEL_B16: - case OPC_SEL_S16: - case OPC_SEL_F16: - case OPC_SAD_S16: - case OPC_SAD_S32: // really?? - return false; - default: - return true; - } -} - -typedef struct PACKED { - /* dword0: */ - union PACKED { - struct PACKED { - uint32_t src : 11; - uint32_t must_be_zero1: 2; - uint32_t src_im : 1; /* immediate */ - uint32_t src_neg : 1; /* negate */ - uint32_t src_abs : 1; /* absolute value */ - }; - struct PACKED { - uint32_t src : 10; - uint32_t src_c : 1; /* relative-const */ - uint32_t src_rel : 1; /* relative address */ - uint32_t must_be_zero : 1; - uint32_t dummy : 3; - } rel; - struct PACKED { - uint32_t src : 12; - uint32_t src_c : 1; /* const */ - uint32_t dummy : 3; - } c; - }; - uint32_t dummy1 : 16; /* seem to be ignored */ - - /* dword1: */ - uint32_t dst : 8; - uint32_t repeat : 2; - uint32_t sat : 1; - uint32_t src_r : 1; - uint32_t ss : 1; - uint32_t ul : 1; - uint32_t dst_half : 1; /* or widen/narrow.. ie. dst hrN <-> rN */ - uint32_t dummy2 : 5; /* seem to be ignored */ - uint32_t full : 1; /* not half */ - uint32_t opc : 6; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat4_t; - -/* With is_bindless_s2en = 1, this determines whether bindless is enabled and - * if so, how to get the (base, index) pair for both sampler and texture. - * There is a single base embedded in the instruction, which is always used - * for the texture. - */ -typedef enum { - /* Use traditional GL binding model, get texture and sampler index - * from src3 which is not presumed to be uniform. This is - * backwards-compatible with earlier generations, where this field was - * always 0 and nonuniform-indexed sampling always worked. - */ - CAT5_NONUNIFORM = 0, - - /* The sampler base comes from the low 3 bits of a1.x, and the sampler - * and texture index come from src3 which is presumed to be uniform. - */ - CAT5_BINDLESS_A1_UNIFORM = 1, - - /* The texture and sampler share the same base, and the sampler and - * texture index come from src3 which is *not* presumed to be uniform. - */ - CAT5_BINDLESS_NONUNIFORM = 2, - - /* The sampler base comes from the low 3 bits of a1.x, and the sampler - * and texture index come from src3 which is *not* presumed to be - * uniform. - */ - CAT5_BINDLESS_A1_NONUNIFORM = 3, - - /* Use traditional GL binding model, get texture and sampler index - * from src3 which is presumed to be uniform. - */ - CAT5_UNIFORM = 4, - - /* The texture and sampler share the same base, and the sampler and - * texture index come from src3 which is presumed to be uniform. - */ - CAT5_BINDLESS_UNIFORM = 5, - - /* The texture and sampler share the same base, get sampler index from low - * 4 bits of src3 and texture index from high 4 bits. - */ - CAT5_BINDLESS_IMM = 6, - - /* The sampler base comes from the low 3 bits of a1.x, and the texture - * index comes from the next 8 bits of a1.x. The sampler index is an - * immediate in src3. - */ - CAT5_BINDLESS_A1_IMM = 7, -} cat5_desc_mode_t; - -typedef struct PACKED { - /* dword0: */ - union PACKED { - /* normal case: */ - struct PACKED { - uint32_t full : 1; /* not half */ - uint32_t src1 : 8; - uint32_t src2 : 8; - uint32_t dummy1 : 4; /* seem to be ignored */ - uint32_t samp : 4; - uint32_t tex : 7; - } norm; - /* s2en case: */ - struct PACKED { - uint32_t full : 1; /* not half */ - uint32_t src1 : 8; - uint32_t src2 : 8; - uint32_t dummy1 : 2; - uint32_t base_hi : 2; - uint32_t src3 : 8; - uint32_t desc_mode : 3; - } s2en_bindless; - /* same in either case: */ - // XXX I think, confirm this - struct PACKED { - uint32_t full : 1; /* not half */ - uint32_t src1 : 8; - uint32_t src2 : 8; - uint32_t pad : 15; - }; - }; - - /* dword1: */ - uint32_t dst : 8; - uint32_t wrmask : 4; /* write-mask */ - uint32_t type : 3; - uint32_t base_lo : 1; /* used with bindless */ - uint32_t is_3d : 1; - - uint32_t is_a : 1; - uint32_t is_s : 1; - uint32_t is_s2en_bindless : 1; - uint32_t is_o : 1; - uint32_t is_p : 1; - - uint32_t opc : 5; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat5_t; - -/* dword0 encoding for src_off: [src1 + off], src2: */ -typedef struct PACKED { - /* dword0: */ - uint32_t mustbe1 : 1; - int32_t off : 13; - uint32_t src1 : 8; - uint32_t src1_im : 1; - uint32_t src2_im : 1; - uint32_t src2 : 8; - - /* dword1: */ - uint32_t dword1; -} instr_cat6a_t; - -/* dword0 encoding for !src_off: [src1], src2 */ -typedef struct PACKED { - /* dword0: */ - uint32_t mustbe0 : 1; - uint32_t src1 : 13; - uint32_t ignore0 : 8; - uint32_t src1_im : 1; - uint32_t src2_im : 1; - uint32_t src2 : 8; - - /* dword1: */ - uint32_t dword1; -} instr_cat6b_t; - -/* dword1 encoding for dst_off: */ -typedef struct PACKED { - /* dword0: */ - uint32_t dword0; - - /* note: there is some weird stuff going on where sometimes - * cat6->a.off is involved.. but that seems like a bug in - * the blob, since it is used even if !cat6->src_off - * It would make sense for there to be some more bits to - * bring us to 11 bits worth of offset, but not sure.. - */ - int32_t off : 8; - uint32_t mustbe1 : 1; - uint32_t dst : 8; - uint32_t pad1 : 15; -} instr_cat6c_t; - -/* dword1 encoding for !dst_off: */ -typedef struct PACKED { - /* dword0: */ - uint32_t dword0; - - uint32_t dst : 8; - uint32_t mustbe0 : 1; - uint32_t idx : 8; - uint32_t pad0 : 15; -} instr_cat6d_t; - -/* ldgb and atomics.. - * - * ldgb: pad0=0, pad3=1 - * atomic .g: pad0=1, pad3=1 - * .l: pad0=1, pad3=0 - */ -typedef struct PACKED { - /* dword0: */ - uint32_t pad0 : 1; - uint32_t src3 : 8; - uint32_t d : 2; - uint32_t typed : 1; - uint32_t type_size : 2; - uint32_t src1 : 8; - uint32_t src1_im : 1; - uint32_t src2_im : 1; - uint32_t src2 : 8; - - /* dword1: */ - uint32_t dst : 8; - uint32_t mustbe0 : 1; - uint32_t src_ssbo : 8; - uint32_t pad2 : 3; // type - uint32_t g : 1; - uint32_t pad3 : 1; - uint32_t pad4 : 10; // opc/jmp_tgt/sync/opc_cat -} instr_cat6ldgb_t; - -/* stgb, pad0=0, pad3=2 - */ -typedef struct PACKED { - /* dword0: */ - uint32_t mustbe1 : 1; // ??? - uint32_t src1 : 8; - uint32_t d : 2; - uint32_t typed : 1; - uint32_t type_size : 2; - uint32_t pad0 : 9; - uint32_t src2_im : 1; - uint32_t src2 : 8; - - /* dword1: */ - uint32_t src3 : 8; - uint32_t src3_im : 1; - uint32_t dst_ssbo : 8; - uint32_t pad2 : 3; // type - uint32_t pad3 : 2; - uint32_t pad4 : 10; // opc/jmp_tgt/sync/opc_cat -} instr_cat6stgb_t; - -typedef union PACKED { - instr_cat6a_t a; - instr_cat6b_t b; - instr_cat6c_t c; - instr_cat6d_t d; - instr_cat6ldgb_t ldgb; - instr_cat6stgb_t stgb; - struct PACKED { - /* dword0: */ - uint32_t src_off : 1; - uint32_t pad1 : 31; - - /* dword1: */ - uint32_t pad2 : 8; - uint32_t dst_off : 1; - uint32_t pad3 : 8; - uint32_t type : 3; - uint32_t g : 1; /* or in some cases it means dst immed */ - uint32_t pad4 : 1; - uint32_t opc : 5; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; - }; -} instr_cat6_t; - -/* Similar to cat5_desc_mode_t, describes how the descriptor is loaded. - */ -typedef enum { - /* Use old GL binding model with an immediate index. */ - CAT6_IMM = 0, - - CAT6_UNIFORM = 1, - - CAT6_NONUNIFORM = 2, - - /* Use the bindless model, with an immediate index. - */ - CAT6_BINDLESS_IMM = 4, - - /* Use the bindless model, with a uniform register index. - */ - CAT6_BINDLESS_UNIFORM = 5, - - /* Use the bindless model, with a register index that isn't guaranteed - * to be uniform. This presumably checks if the indices are equal and - * splits up the load/store, because it works the way you would - * expect. - */ - CAT6_BINDLESS_NONUNIFORM = 6, -} cat6_desc_mode_t; - -/** - * For atomic ops (which return a value): - * - * pad1=1, pad3=c, pad5=3 - * src1 - vecN offset/coords - * src2.x - is actually dest register - * src2.y - is 'data' except for cmpxchg where src2.y is 'compare' - * and src2.z is 'data' - * - * For stib (which does not return a value): - * pad1=0, pad3=c, pad5=2 - * src1 - vecN offset/coords - * src2 - value to store - * - * For ldib: - * pad1=1, pad3=c, pad5=2 - * src1 - vecN offset/coords - * - * for ldc (load from UBO using descriptor): - * pad1=0, pad3=8, pad5=2 - * - * pad2 and pad5 are only observed to be 0. - */ -typedef struct PACKED { - /* dword0: */ - uint32_t pad1 : 1; - uint32_t base : 3; - uint32_t pad2 : 2; - uint32_t desc_mode : 3; - uint32_t d : 2; - uint32_t typed : 1; - uint32_t type_size : 2; - uint32_t opc : 5; - uint32_t pad3 : 5; - uint32_t src1 : 8; /* coordinate/offset */ - - /* dword1: */ - uint32_t src2 : 8; /* or the dst for load instructions */ - uint32_t pad4 : 1; //mustbe0 ?? - uint32_t ssbo : 8; /* ssbo/image binding point */ - uint32_t type : 3; - uint32_t pad5 : 7; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; -} instr_cat6_a6xx_t; - -typedef struct PACKED { - /* dword0: */ - uint32_t pad1 : 32; - - /* dword1: */ - uint32_t pad2 : 12; - uint32_t ss : 1; /* maybe in the encoding, but blob only uses (sy) */ - uint32_t pad3 : 6; - uint32_t w : 1; /* write */ - uint32_t r : 1; /* read */ - uint32_t l : 1; /* local */ - uint32_t g : 1; /* global */ - uint32_t opc : 4; /* presumed, but only a couple known OPCs */ - uint32_t jmp_tgt : 1; /* (jp) */ - uint32_t sync : 1; /* (sy) */ - uint32_t opc_cat : 3; -} instr_cat7_t; - -typedef union PACKED { - instr_cat0_t cat0; - instr_cat1_t cat1; - instr_cat2_t cat2; - instr_cat3_t cat3; - instr_cat4_t cat4; - instr_cat5_t cat5; - instr_cat6_t cat6; - instr_cat6_a6xx_t cat6_a6xx; - instr_cat7_t cat7; - struct PACKED { - /* dword0: */ - uint32_t pad1 : 32; - - /* dword1: */ - uint32_t pad2 : 12; - uint32_t ss : 1; /* cat1-cat4 (cat0??) and cat7 (?) */ - uint32_t ul : 1; /* cat2-cat4 (and cat1 in blob.. which may be bug??) */ - uint32_t pad3 : 13; - uint32_t jmp_tgt : 1; - uint32_t sync : 1; - uint32_t opc_cat : 3; - - }; -} instr_t; - -static inline uint32_t instr_repeat(instr_t *instr) -{ - switch (instr->opc_cat) { - case 0: return instr->cat0.repeat; - case 1: return instr->cat1.repeat; - case 2: return instr->cat2.repeat; - case 3: return instr->cat3.repeat; - case 4: return instr->cat4.repeat; - default: return 0; - } -} - -static inline bool instr_sat(instr_t *instr) -{ - switch (instr->opc_cat) { - case 2: return instr->cat2.sat; - case 3: return instr->cat3.sat; - case 4: return instr->cat4.sat; - default: return false; - } -} - -/* We can probably drop the gpu_id arg, but keeping it for now so we can - * assert if we see something we think should be new encoding on an older - * gpu. - */ -static inline bool is_cat6_legacy(instr_t *instr, unsigned gpu_id) -{ - instr_cat6_a6xx_t *cat6 = &instr->cat6_a6xx; - - /* At least one of these two bits is pad in all the possible - * "legacy" cat6 encodings, and a analysis of all the pre-a6xx - * cmdstream traces I have indicates that the pad bit is zero - * in all cases. So we can use this to detect new encoding: - */ - if ((cat6->pad3 & 0x8) && (cat6->pad5 & 0x2)) { - assert(gpu_id >= 600); - assert(instr->cat6.opc == 0); - return false; - } - - return true; -} - -static inline uint32_t instr_opc(instr_t *instr, unsigned gpu_id) -{ - switch (instr->opc_cat) { - case 0: return instr->cat0.opc | instr->cat0.opc_hi << 4; - case 1: return 0; - case 2: return instr->cat2.opc; - case 3: return instr->cat3.opc; - case 4: return instr->cat4.opc; - case 5: return instr->cat5.opc; - case 6: - if (!is_cat6_legacy(instr, gpu_id)) - return instr->cat6_a6xx.opc; - return instr->cat6.opc; - case 7: return instr->cat7.opc; - default: return 0; - } -} - -static inline bool is_mad(opc_t opc) -{ - switch (opc) { - case OPC_MAD_U16: - case OPC_MAD_S16: - case OPC_MAD_U24: - case OPC_MAD_S24: - case OPC_MAD_F16: - case OPC_MAD_F32: - return true; - default: - return false; - } -} - -static inline bool is_madsh(opc_t opc) -{ - switch (opc) { - case OPC_MADSH_U16: - case OPC_MADSH_M16: - return true; - default: - return false; - } -} - -static inline bool is_atomic(opc_t opc) -{ - switch (opc) { - case OPC_ATOMIC_ADD: - case OPC_ATOMIC_SUB: - case OPC_ATOMIC_XCHG: - case OPC_ATOMIC_INC: - case OPC_ATOMIC_DEC: - case OPC_ATOMIC_CMPXCHG: - case OPC_ATOMIC_MIN: - case OPC_ATOMIC_MAX: - case OPC_ATOMIC_AND: - case OPC_ATOMIC_OR: - case OPC_ATOMIC_XOR: - return true; - default: - return false; - } -} - -static inline bool is_ssbo(opc_t opc) -{ - switch (opc) { - case OPC_RESFMT: - case OPC_RESINFO: - case OPC_LDGB: - case OPC_STGB: - case OPC_STIB: - return true; - default: - return false; - } -} - -static inline bool is_isam(opc_t opc) -{ - switch (opc) { - case OPC_ISAM: - case OPC_ISAML: - case OPC_ISAMM: - return true; - default: - return false; - } -} - - -static inline bool is_cat2_float(opc_t opc) -{ - switch (opc) { - case OPC_ADD_F: - case OPC_MIN_F: - case OPC_MAX_F: - case OPC_MUL_F: - case OPC_SIGN_F: - case OPC_CMPS_F: - case OPC_ABSNEG_F: - case OPC_CMPV_F: - case OPC_FLOOR_F: - case OPC_CEIL_F: - case OPC_RNDNE_F: - case OPC_RNDAZ_F: - case OPC_TRUNC_F: - return true; - - default: - return false; - } -} - -static inline bool is_cat3_float(opc_t opc) -{ - switch (opc) { - case OPC_MAD_F16: - case OPC_MAD_F32: - case OPC_SEL_F16: - case OPC_SEL_F32: - return true; - default: - return false; - } -} - -int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id); - -#endif /* INSTR_A3XX_H_ */ diff --git a/tinygrad/extra/disassemblers/adreno/ir3.h b/tinygrad/extra/disassemblers/adreno/ir3.h deleted file mode 100644 index 5c0c297d..00000000 --- a/tinygrad/extra/disassemblers/adreno/ir3.h +++ /dev/null @@ -1,1757 +0,0 @@ -/* - * Copyright (c) 2013 Rob Clark - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef IR3_H_ -#define IR3_H_ - -#include -#include - -#include "shader_enums.h" -#include "util/list.h" - -#include "util/bitscan.h" -/*#include "util/list.h" -#include "util/set.h" -#include "util/u_debug.h"*/ - -#define debug_assert(x) assert(x) - -#include "instr-a3xx.h" - -/* low level intermediate representation of an adreno shader program */ - -struct ir3_compiler; -struct ir3; -struct ir3_instruction; -struct ir3_block; - -struct ir3_info { - uint32_t gpu_id; - uint16_t sizedwords; - uint16_t instrs_count; /* expanded to account for rpt's */ - uint16_t nops_count; /* # of nop instructions, including nopN */ - uint16_t mov_count; - uint16_t cov_count; - /* NOTE: max_reg, etc, does not include registers not touched - * by the shader (ie. vertex fetched via VFD_DECODE but not - * touched by shader) - */ - int8_t max_reg; /* highest GPR # used by shader */ - int8_t max_half_reg; - int16_t max_const; - - /* number of sync bits: */ - uint16_t ss, sy; - - /* estimate of number of cycles stalled on (ss) */ - uint16_t sstall; - - uint16_t last_baryf; /* instruction # of last varying fetch */ -}; - -struct ir3_register { - enum { - IR3_REG_CONST = 0x001, - IR3_REG_IMMED = 0x002, - IR3_REG_HALF = 0x004, - /* high registers are used for some things in compute shaders, - * for example. Seems to be for things that are global to all - * threads in a wave, so possibly these are global/shared by - * all the threads in the wave? - */ - IR3_REG_HIGH = 0x008, - IR3_REG_RELATIV= 0x010, - IR3_REG_R = 0x020, - /* Most instructions, it seems, can do float abs/neg but not - * integer. The CP pass needs to know what is intended (int or - * float) in order to do the right thing. For this reason the - * abs/neg flags are split out into float and int variants. In - * addition, .b (bitwise) operations, the negate is actually a - * bitwise not, so split that out into a new flag to make it - * more clear. - */ - IR3_REG_FNEG = 0x040, - IR3_REG_FABS = 0x080, - IR3_REG_SNEG = 0x100, - IR3_REG_SABS = 0x200, - IR3_REG_BNOT = 0x400, - IR3_REG_EVEN = 0x800, - IR3_REG_POS_INF= 0x1000, - /* (ei) flag, end-input? Set on last bary, presumably to signal - * that the shader needs no more input: - */ - IR3_REG_EI = 0x2000, - /* meta-flags, for intermediate stages of IR, ie. - * before register assignment is done: - */ - IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */ - IR3_REG_ARRAY = 0x8000, - - } flags; - - /* used for cat5 instructions, but also for internal/IR level - * tracking of what registers are read/written by an instruction. - * wrmask may be a bad name since it is used to represent both - * src and dst that touch multiple adjacent registers. - */ - unsigned wrmask : 16; /* up to vec16 */ - - /* for relative addressing, 32bits for array size is too small, - * but otoh we don't need to deal with disjoint sets, so instead - * use a simple size field (number of scalar components). - * - * Note the size field isn't important for relative const (since - * we don't have to do register allocation for constants). - */ - unsigned size : 15; - - bool merged : 1; /* half-regs conflict with full regs (ie >= a6xx) */ - - /* normal registers: - * the component is in the low two bits of the reg #, so - * rN.x becomes: (N << 2) | x - */ - uint16_t num; - union { - /* immediate: */ - int32_t iim_val; - uint32_t uim_val; - float fim_val; - /* relative: */ - struct { - uint16_t id; - int16_t offset; - } array; - }; - - /* For IR3_REG_SSA, src registers contain ptr back to assigning - * instruction. - * - * For IR3_REG_ARRAY, the pointer is back to the last dependent - * array access (although the net effect is the same, it points - * back to a previous instruction that we depend on). - */ - struct ir3_instruction *instr; -}; - -/* - * Stupid/simple growable array implementation: - */ -#define DECLARE_ARRAY(type, name) \ - unsigned name ## _count, name ## _sz; \ - type * name; - -#define array_insert(ctx, arr, val) do { \ - if (arr ## _count == arr ## _sz) { \ - arr ## _sz = MAX2(2 * arr ## _sz, 16); \ - arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \ - } \ - arr[arr ##_count++] = val; \ - } while (0) - -struct ir3_instruction { - struct ir3_block *block; - opc_t opc; - enum { - /* (sy) flag is set on first instruction, and after sample - * instructions (probably just on RAW hazard). - */ - IR3_INSTR_SY = 0x001, - /* (ss) flag is set on first instruction, and first instruction - * to depend on the result of "long" instructions (RAW hazard): - * - * rcp, rsq, log2, exp2, sin, cos, sqrt - * - * It seems to synchronize until all in-flight instructions are - * completed, for example: - * - * rsq hr1.w, hr1.w - * add.f hr2.z, (neg)hr2.z, hc0.y - * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y - * rsq hr2.x, hr2.x - * (rpt1)nop - * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w - * nop - * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w - * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w - * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x - * - * The last mul.f does not have (ss) set, presumably because the - * (ss) on the previous instruction does the job. - * - * The blob driver also seems to set it on WAR hazards, although - * not really clear if this is needed or just blob compiler being - * sloppy. So far I haven't found a case where removing the (ss) - * causes problems for WAR hazard, but I could just be getting - * lucky: - * - * rcp r1.y, r3.y - * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z - * - */ - IR3_INSTR_SS = 0x002, - /* (jp) flag is set on jump targets: - */ - IR3_INSTR_JP = 0x004, - IR3_INSTR_UL = 0x008, - IR3_INSTR_3D = 0x010, - IR3_INSTR_A = 0x020, - IR3_INSTR_O = 0x040, - IR3_INSTR_P = 0x080, - IR3_INSTR_S = 0x100, - IR3_INSTR_S2EN = 0x200, - IR3_INSTR_G = 0x400, - IR3_INSTR_SAT = 0x800, - /* (cat5/cat6) Bindless */ - IR3_INSTR_B = 0x1000, - /* (cat5-only) Get some parts of the encoding from a1.x */ - IR3_INSTR_A1EN = 0x2000, - /* meta-flags, for intermediate stages of IR, ie. - * before register assignment is done: - */ - IR3_INSTR_MARK = 0x4000, - IR3_INSTR_UNUSED= 0x8000, - } flags; - uint8_t repeat; - uint8_t nop; -#ifdef DEBUG - unsigned regs_max; -#endif - unsigned regs_count; - struct ir3_register **regs; - union { - struct { - char inv; - char comp; - int immed; - struct ir3_block *target; - } cat0; - struct { - type_t src_type, dst_type; - } cat1; - struct { - enum { - IR3_COND_LT = 0, - IR3_COND_LE = 1, - IR3_COND_GT = 2, - IR3_COND_GE = 3, - IR3_COND_EQ = 4, - IR3_COND_NE = 5, - } condition; - } cat2; - struct { - unsigned samp, tex; - unsigned tex_base : 3; - type_t type; - } cat5; - struct { - type_t type; - int src_offset; - int dst_offset; - int iim_val : 3; /* for ldgb/stgb, # of components */ - unsigned d : 3; /* for ldc, component offset */ - bool typed : 1; - unsigned base : 3; - } cat6; - struct { - unsigned w : 1; /* write */ - unsigned r : 1; /* read */ - unsigned l : 1; /* local */ - unsigned g : 1; /* global */ - } cat7; - /* for meta-instructions, just used to hold extra data - * before instruction scheduling, etc - */ - struct { - int off; /* component/offset */ - } split; - struct { - /* for output collects, this maps back to the entry in the - * ir3_shader_variant::outputs table. - */ - int outidx; - } collect; - struct { - unsigned samp, tex; - unsigned input_offset; - unsigned samp_base : 3; - unsigned tex_base : 3; - } prefetch; - struct { - /* maps back to entry in ir3_shader_variant::inputs table: */ - int inidx; - /* for sysvals, identifies the sysval type. Mostly so we can - * identify the special cases where a sysval should not be DCE'd - * (currently, just pre-fs texture fetch) - */ - gl_system_value sysval; - } input; - }; - - /* When we get to the RA stage, we need instruction's position/name: */ - uint16_t ip; - uint16_t name; - - /* used for per-pass extra instruction data. - * - * TODO we should remove the per-pass data like this and 'use_count' - * and do something similar to what RA does w/ ir3_ra_instr_data.. - * ie. use the ir3_count_instructions pass, and then use instr->ip - * to index into a table of pass-private data. - */ - void *data; - - /** - * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use() - */ - struct set *uses; - - int sun; /* Sethi–Ullman number, used by sched */ - int use_count; /* currently just updated/used by cp */ - - /* Used during CP and RA stages. For collect and shader inputs/ - * outputs where we need a sequence of consecutive registers, - * keep track of each src instructions left (ie 'n-1') and right - * (ie 'n+1') neighbor. The front-end must insert enough mov's - * to ensure that each instruction has at most one left and at - * most one right neighbor. During the copy-propagation pass, - * we only remove mov's when we can preserve this constraint. - * And during the RA stage, we use the neighbor information to - * allocate a block of registers in one shot. - * - * TODO: maybe just add something like: - * struct ir3_instruction_ref { - * struct ir3_instruction *instr; - * unsigned cnt; - * } - * - * Or can we get away without the refcnt stuff? It seems like - * it should be overkill.. the problem is if, potentially after - * already eliminating some mov's, if you have a single mov that - * needs to be grouped with it's neighbors in two different - * places (ex. shader output and a collect). - */ - struct { - struct ir3_instruction *left, *right; - uint16_t left_cnt, right_cnt; - } cp; - - /* an instruction can reference at most one address register amongst - * it's src/dst registers. Beyond that, you need to insert mov's. - * - * NOTE: do not write this directly, use ir3_instr_set_address() - */ - struct ir3_instruction *address; - - /* Tracking for additional dependent instructions. Used to handle - * barriers, WAR hazards for arrays/SSBOs/etc. - */ - DECLARE_ARRAY(struct ir3_instruction *, deps); - - /* - * From PoV of instruction scheduling, not execution (ie. ignores global/ - * local distinction): - * shared image atomic SSBO everything - * barrier()/ - R/W R/W R/W R/W X - * groupMemoryBarrier() - * memoryBarrier() - R/W R/W - * (but only images declared coherent?) - * memoryBarrierAtomic() - R/W - * memoryBarrierBuffer() - R/W - * memoryBarrierImage() - R/W - * memoryBarrierShared() - R/W - * - * TODO I think for SSBO/image/shared, in cases where we can determine - * which variable is accessed, we don't need to care about accesses to - * different variables (unless declared coherent??) - */ - enum { - IR3_BARRIER_EVERYTHING = 1 << 0, - IR3_BARRIER_SHARED_R = 1 << 1, - IR3_BARRIER_SHARED_W = 1 << 2, - IR3_BARRIER_IMAGE_R = 1 << 3, - IR3_BARRIER_IMAGE_W = 1 << 4, - IR3_BARRIER_BUFFER_R = 1 << 5, - IR3_BARRIER_BUFFER_W = 1 << 6, - IR3_BARRIER_ARRAY_R = 1 << 7, - IR3_BARRIER_ARRAY_W = 1 << 8, - } barrier_class, barrier_conflict; - - /* Entry in ir3_block's instruction list: */ - struct list_head node; - -#ifdef DEBUG - uint32_t serialno; -#endif - - // TODO only computerator/assembler: - int line; -}; - -static inline struct ir3_instruction * -ir3_neighbor_first(struct ir3_instruction *instr) -{ - int cnt = 0; - while (instr->cp.left) { - instr = instr->cp.left; - if (++cnt > 0xffff) { - debug_assert(0); - break; - } - } - return instr; -} - -static inline int ir3_neighbor_count(struct ir3_instruction *instr) -{ - int num = 1; - - debug_assert(!instr->cp.left); - - while (instr->cp.right) { - num++; - instr = instr->cp.right; - if (num > 0xffff) { - debug_assert(0); - break; - } - } - - return num; -} - -struct ir3 { - struct ir3_compiler *compiler; - gl_shader_stage type; - - DECLARE_ARRAY(struct ir3_instruction *, inputs); - DECLARE_ARRAY(struct ir3_instruction *, outputs); - - /* Track bary.f (and ldlv) instructions.. this is needed in - * scheduling to ensure that all varying fetches happen before - * any potential kill instructions. The hw gets grumpy if all - * threads in a group are killed before the last bary.f gets - * a chance to signal end of input (ei). - */ - DECLARE_ARRAY(struct ir3_instruction *, baryfs); - - /* Track all indirect instructions (read and write). To avoid - * deadlock scenario where an address register gets scheduled, - * but other dependent src instructions cannot be scheduled due - * to dependency on a *different* address register value, the - * scheduler needs to ensure that all dependencies other than - * the instruction other than the address register are scheduled - * before the one that writes the address register. Having a - * convenient list of instructions that reference some address - * register simplifies this. - */ - DECLARE_ARRAY(struct ir3_instruction *, a0_users); - - /* same for a1.x: */ - DECLARE_ARRAY(struct ir3_instruction *, a1_users); - - /* and same for instructions that consume predicate register: */ - DECLARE_ARRAY(struct ir3_instruction *, predicates); - - /* Track texture sample instructions which need texture state - * patched in (for astc-srgb workaround): - */ - DECLARE_ARRAY(struct ir3_instruction *, astc_srgb); - - /* List of blocks: */ - struct list_head block_list; - - /* List of ir3_array's: */ - struct list_head array_list; - - unsigned max_sun; /* max Sethi–Ullman number */ - -#ifdef DEBUG - unsigned block_count, instr_count; -#endif -}; - -struct ir3_array { - struct list_head node; - unsigned length; - unsigned id; - - struct nir_register *r; - - /* To avoid array write's from getting DCE'd, keep track of the - * most recent write. Any array access depends on the most - * recent write. This way, nothing depends on writes after the - * last read. But all the writes that happen before that have - * something depending on them - */ - struct ir3_instruction *last_write; - - /* extra stuff used in RA pass: */ - unsigned base; /* base vreg name */ - unsigned reg; /* base physical reg */ - uint16_t start_ip, end_ip; - - /* Indicates if half-precision */ - bool half; -}; - -struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id); - -struct ir3_block { - struct list_head node; - struct ir3 *shader; - - const struct nir_block *nblock; - - struct list_head instr_list; /* list of ir3_instruction */ - - /* each block has either one or two successors.. in case of - * two successors, 'condition' decides which one to follow. - * A block preceding an if/else has two successors. - */ - struct ir3_instruction *condition; - struct ir3_block *successors[2]; - - struct set *predecessors; /* set of ir3_block */ - - uint16_t start_ip, end_ip; - - /* Track instructions which do not write a register but other- - * wise must not be discarded (such as kill, stg, etc) - */ - DECLARE_ARRAY(struct ir3_instruction *, keeps); - - /* used for per-pass extra block data. Mainly used right - * now in RA step to track livein/liveout. - */ - void *data; - -#ifdef DEBUG - uint32_t serialno; -#endif -}; - -static inline uint32_t -block_id(struct ir3_block *block) -{ -#ifdef DEBUG - return block->serialno; -#else - return (uint32_t)(unsigned long)block; -#endif -} - -struct ir3 * ir3_create(struct ir3_compiler *compiler, gl_shader_stage type); -void ir3_destroy(struct ir3 *shader); -void * ir3_assemble(struct ir3 *shader, - struct ir3_info *info, uint32_t gpu_id); -void * ir3_alloc(struct ir3 *shader, int sz); - -struct ir3_block * ir3_block_create(struct ir3 *shader); - -struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc); -struct ir3_instruction * ir3_instr_create2(struct ir3_block *block, - opc_t opc, int nreg); -struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr); -void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep); -const char *ir3_instr_name(struct ir3_instruction *instr); - -struct ir3_register * ir3_reg_create(struct ir3_instruction *instr, - int num, int flags); -struct ir3_register * ir3_reg_clone(struct ir3 *shader, - struct ir3_register *reg); - -void ir3_instr_set_address(struct ir3_instruction *instr, - struct ir3_instruction *addr); - -static inline bool ir3_instr_check_mark(struct ir3_instruction *instr) -{ - if (instr->flags & IR3_INSTR_MARK) - return true; /* already visited */ - instr->flags |= IR3_INSTR_MARK; - return false; -} - -void ir3_block_clear_mark(struct ir3_block *block); -void ir3_clear_mark(struct ir3 *shader); - -unsigned ir3_count_instructions(struct ir3 *ir); -unsigned ir3_count_instructions_ra(struct ir3 *ir); - -void ir3_find_ssa_uses(struct ir3 *ir, void *mem_ctx, bool falsedeps); - -//#include "util/set.h" -#define foreach_ssa_use(__use, __instr) \ - for (struct ir3_instruction *__use = (void *)~0; \ - __use && (__instr)->uses; __use = NULL) \ - set_foreach ((__instr)->uses, __entry) \ - if ((__use = (void *)__entry->key)) - -#define MAX_ARRAYS 16 - -/* comp: - * 0 - x - * 1 - y - * 2 - z - * 3 - w - */ -static inline uint32_t regid(int num, int comp) -{ - return (num << 2) | (comp & 0x3); -} - -static inline uint32_t reg_num(struct ir3_register *reg) -{ - return reg->num >> 2; -} - -static inline uint32_t reg_comp(struct ir3_register *reg) -{ - return reg->num & 0x3; -} - -#define INVALID_REG regid(63, 0) -#define VALIDREG(r) ((r) != INVALID_REG) -#define CONDREG(r, val) COND(VALIDREG(r), (val)) - -static inline bool is_flow(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == 0); -} - -static inline bool is_kill(struct ir3_instruction *instr) -{ - return instr->opc == OPC_KILL; -} - -static inline bool is_nop(struct ir3_instruction *instr) -{ - return instr->opc == OPC_NOP; -} - -static inline bool is_same_type_reg(struct ir3_register *reg1, - struct ir3_register *reg2) -{ - unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF)); - unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF)); - - if (type_reg1 ^ type_reg2) - return false; - else - return true; -} - -/* Is it a non-transformative (ie. not type changing) mov? This can - * also include absneg.s/absneg.f, which for the most part can be - * treated as a mov (single src argument). - */ -static inline bool is_same_type_mov(struct ir3_instruction *instr) -{ - struct ir3_register *dst; - - switch (instr->opc) { - case OPC_MOV: - if (instr->cat1.src_type != instr->cat1.dst_type) - return false; - /* If the type of dest reg and src reg are different, - * it shouldn't be considered as same type mov - */ - if (!is_same_type_reg(instr->regs[0], instr->regs[1])) - return false; - break; - case OPC_ABSNEG_F: - case OPC_ABSNEG_S: - if (instr->flags & IR3_INSTR_SAT) - return false; - /* If the type of dest reg and src reg are different, - * it shouldn't be considered as same type mov - */ - if (!is_same_type_reg(instr->regs[0], instr->regs[1])) - return false; - break; - default: - return false; - } - - dst = instr->regs[0]; - - /* mov's that write to a0 or p0.x are special: */ - if (dst->num == regid(REG_P0, 0)) - return false; - if (reg_num(dst) == REG_A0) - return false; - - if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY)) - return false; - - return true; -} - -/* A move from const, which changes size but not type, can also be - * folded into dest instruction in some cases. - */ -static inline bool is_const_mov(struct ir3_instruction *instr) -{ - if (instr->opc != OPC_MOV) - return false; - - if (!(instr->regs[1]->flags & IR3_REG_CONST)) - return false; - - type_t src_type = instr->cat1.src_type; - type_t dst_type = instr->cat1.dst_type; - - return (type_float(src_type) && type_float(dst_type)) || - (type_uint(src_type) && type_uint(dst_type)) || - (type_sint(src_type) && type_sint(dst_type)); -} - -static inline bool is_alu(struct ir3_instruction *instr) -{ - return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3); -} - -static inline bool is_sfu(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == 4); -} - -static inline bool is_tex(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == 5); -} - -static inline bool is_tex_or_prefetch(struct ir3_instruction *instr) -{ - return is_tex(instr) || (instr->opc == OPC_META_TEX_PREFETCH); -} - -static inline bool is_mem(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == 6); -} - -static inline bool is_barrier(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == 7); -} - -static inline bool -is_half(struct ir3_instruction *instr) -{ - return !!(instr->regs[0]->flags & IR3_REG_HALF); -} - -static inline bool -is_high(struct ir3_instruction *instr) -{ - return !!(instr->regs[0]->flags & IR3_REG_HIGH); -} - -static inline bool -is_store(struct ir3_instruction *instr) -{ - /* these instructions, the "destination" register is - * actually a source, the address to store to. - */ - switch (instr->opc) { - case OPC_STG: - case OPC_STGB: - case OPC_STIB: - case OPC_STP: - case OPC_STL: - case OPC_STLW: - case OPC_L2G: - case OPC_G2L: - return true; - default: - return false; - } -} - -static inline bool is_load(struct ir3_instruction *instr) -{ - switch (instr->opc) { - case OPC_LDG: - case OPC_LDGB: - case OPC_LDIB: - case OPC_LDL: - case OPC_LDP: - case OPC_L2G: - case OPC_LDLW: - case OPC_LDC: - case OPC_LDLV: - /* probably some others too.. */ - return true; - default: - return false; - } -} - -static inline bool is_input(struct ir3_instruction *instr) -{ - /* in some cases, ldlv is used to fetch varying without - * interpolation.. fortunately inloc is the first src - * register in either case - */ - switch (instr->opc) { - case OPC_LDLV: - case OPC_BARY_F: - return true; - default: - return false; - } -} - -static inline bool is_bool(struct ir3_instruction *instr) -{ - switch (instr->opc) { - case OPC_CMPS_F: - case OPC_CMPS_S: - case OPC_CMPS_U: - return true; - default: - return false; - } -} - -static inline bool is_meta(struct ir3_instruction *instr) -{ - return (opc_cat(instr->opc) == -1); -} - -static inline unsigned dest_regs(struct ir3_instruction *instr) -{ - if ((instr->regs_count == 0) || is_store(instr) || is_flow(instr)) - return 0; - - return util_last_bit(instr->regs[0]->wrmask); -} - -static inline bool -writes_gpr(struct ir3_instruction *instr) -{ - if (dest_regs(instr) == 0) - return false; - /* is dest a normal temp register: */ - struct ir3_register *reg = instr->regs[0]; - debug_assert(!(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))); - if ((reg_num(reg) == REG_A0) || - (reg->num == regid(REG_P0, 0))) - return false; - return true; -} - -static inline bool writes_addr0(struct ir3_instruction *instr) -{ - if (instr->regs_count > 0) { - struct ir3_register *dst = instr->regs[0]; - return dst->num == regid(REG_A0, 0); - } - return false; -} - -static inline bool writes_addr1(struct ir3_instruction *instr) -{ - if (instr->regs_count > 0) { - struct ir3_register *dst = instr->regs[0]; - return dst->num == regid(REG_A0, 1); - } - return false; -} - -static inline bool writes_pred(struct ir3_instruction *instr) -{ - if (instr->regs_count > 0) { - struct ir3_register *dst = instr->regs[0]; - return reg_num(dst) == REG_P0; - } - return false; -} - -/* returns defining instruction for reg */ -/* TODO better name */ -static inline struct ir3_instruction *ssa(struct ir3_register *reg) -{ - if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) { - return reg->instr; - } - return NULL; -} - -static inline bool conflicts(struct ir3_instruction *a, - struct ir3_instruction *b) -{ - return (a && b) && (a != b); -} - -static inline bool reg_gpr(struct ir3_register *r) -{ - if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED)) - return false; - if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0)) - return false; - return true; -} - -static inline type_t half_type(type_t type) -{ - switch (type) { - case TYPE_F32: return TYPE_F16; - case TYPE_U32: return TYPE_U16; - case TYPE_S32: return TYPE_S16; - case TYPE_F16: - case TYPE_U16: - case TYPE_S16: - return type; - default: - assert(0); - return ~0; - } -} - -/* some cat2 instructions (ie. those which are not float) can embed an - * immediate: - */ -static inline bool ir3_cat2_int(opc_t opc) -{ - switch (opc) { - case OPC_ADD_U: - case OPC_ADD_S: - case OPC_SUB_U: - case OPC_SUB_S: - case OPC_CMPS_U: - case OPC_CMPS_S: - case OPC_MIN_U: - case OPC_MIN_S: - case OPC_MAX_U: - case OPC_MAX_S: - case OPC_CMPV_U: - case OPC_CMPV_S: - case OPC_MUL_U24: - case OPC_MUL_S24: - case OPC_MULL_U: - case OPC_CLZ_S: - case OPC_ABSNEG_S: - case OPC_AND_B: - case OPC_OR_B: - case OPC_NOT_B: - case OPC_XOR_B: - case OPC_BFREV_B: - case OPC_CLZ_B: - case OPC_SHL_B: - case OPC_SHR_B: - case OPC_ASHR_B: - case OPC_MGEN_B: - case OPC_GETBIT_B: - case OPC_CBITS_B: - case OPC_BARY_F: - return true; - - default: - return false; - } -} - -/* map cat2 instruction to valid abs/neg flags: */ -static inline unsigned ir3_cat2_absneg(opc_t opc) -{ - switch (opc) { - case OPC_ADD_F: - case OPC_MIN_F: - case OPC_MAX_F: - case OPC_MUL_F: - case OPC_SIGN_F: - case OPC_CMPS_F: - case OPC_ABSNEG_F: - case OPC_CMPV_F: - case OPC_FLOOR_F: - case OPC_CEIL_F: - case OPC_RNDNE_F: - case OPC_RNDAZ_F: - case OPC_TRUNC_F: - case OPC_BARY_F: - return IR3_REG_FABS | IR3_REG_FNEG; - - case OPC_ADD_U: - case OPC_ADD_S: - case OPC_SUB_U: - case OPC_SUB_S: - case OPC_CMPS_U: - case OPC_CMPS_S: - case OPC_MIN_U: - case OPC_MIN_S: - case OPC_MAX_U: - case OPC_MAX_S: - case OPC_CMPV_U: - case OPC_CMPV_S: - case OPC_MUL_U24: - case OPC_MUL_S24: - case OPC_MULL_U: - case OPC_CLZ_S: - return 0; - - case OPC_ABSNEG_S: - return IR3_REG_SABS | IR3_REG_SNEG; - - case OPC_AND_B: - case OPC_OR_B: - case OPC_NOT_B: - case OPC_XOR_B: - case OPC_BFREV_B: - case OPC_CLZ_B: - case OPC_SHL_B: - case OPC_SHR_B: - case OPC_ASHR_B: - case OPC_MGEN_B: - case OPC_GETBIT_B: - case OPC_CBITS_B: - return IR3_REG_BNOT; - - default: - return 0; - } -} - -/* map cat3 instructions to valid abs/neg flags: */ -static inline unsigned ir3_cat3_absneg(opc_t opc) -{ - switch (opc) { - case OPC_MAD_F16: - case OPC_MAD_F32: - case OPC_SEL_F16: - case OPC_SEL_F32: - return IR3_REG_FNEG; - - case OPC_MAD_U16: - case OPC_MADSH_U16: - case OPC_MAD_S16: - case OPC_MADSH_M16: - case OPC_MAD_U24: - case OPC_MAD_S24: - case OPC_SEL_S16: - case OPC_SEL_S32: - case OPC_SAD_S16: - case OPC_SAD_S32: - /* neg *may* work on 3rd src.. */ - - case OPC_SEL_B16: - case OPC_SEL_B32: - - default: - return 0; - } -} - -#define MASK(n) ((1 << (n)) - 1) - -/* iterator for an instructions's sources (reg), also returns src #: */ -#define foreach_src_n(__srcreg, __n, __instr) \ - if ((__instr)->regs_count) \ - for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \ - if ((__srcreg = (__instr)->regs[__n + 1])) - -/* iterator for an instructions's sources (reg): */ -#define foreach_src(__srcreg, __instr) \ - foreach_src_n(__srcreg, __i, __instr) - -static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr) -{ - unsigned cnt = instr->regs_count + instr->deps_count; - if (instr->address) - cnt++; - return cnt; -} - -static inline struct ir3_instruction ** -__ssa_srcp_n(struct ir3_instruction *instr, unsigned n) -{ - if (n == (instr->regs_count + instr->deps_count)) - return &instr->address; - if (n >= instr->regs_count) - return &instr->deps[n - instr->regs_count]; - if (ssa(instr->regs[n])) - return &instr->regs[n]->instr; - return NULL; -} - -static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n) -{ - if (n == (instr->regs_count + instr->deps_count)) - return false; - if (n >= instr->regs_count) - return true; - return false; -} - -#define foreach_ssa_srcp_n(__srcp, __n, __instr) \ - for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \ - for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \ - if ((__srcp = __ssa_srcp_n(__instr, __n))) - -#define foreach_ssa_srcp(__srcp, __instr) \ - foreach_ssa_srcp_n(__srcp, __i, __instr) - -/* iterator for an instruction's SSA sources (instr), also returns src #: */ -#define foreach_ssa_src_n(__srcinst, __n, __instr) \ - foreach_ssa_srcp_n(__srcp, __n, __instr) \ - if ((__srcinst = *__srcp)) - -/* iterator for an instruction's SSA sources (instr): */ -#define foreach_ssa_src(__srcinst, __instr) \ - foreach_ssa_src_n(__srcinst, __i, __instr) - -/* iterators for shader inputs: */ -#define foreach_input_n(__ininstr, __cnt, __ir) \ - for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \ - if ((__ininstr = (__ir)->inputs[__cnt])) -#define foreach_input(__ininstr, __ir) \ - foreach_input_n(__ininstr, __i, __ir) - -/* iterators for shader outputs: */ -#define foreach_output_n(__outinstr, __cnt, __ir) \ - for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \ - if ((__outinstr = (__ir)->outputs[__cnt])) -#define foreach_output(__outinstr, __ir) \ - foreach_output_n(__outinstr, __i, __ir) - -/* iterators for instructions: */ -#define foreach_instr(__instr, __list) \ - list_for_each_entry(struct ir3_instruction, __instr, __list, node) -#define foreach_instr_rev(__instr, __list) \ - list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node) -#define foreach_instr_safe(__instr, __list) \ - list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node) - -/* iterators for blocks: */ -#define foreach_block(__block, __list) \ - list_for_each_entry(struct ir3_block, __block, __list, node) -#define foreach_block_safe(__block, __list) \ - list_for_each_entry_safe(struct ir3_block, __block, __list, node) -#define foreach_block_rev(__block, __list) \ - list_for_each_entry_rev(struct ir3_block, __block, __list, node) - -/* iterators for arrays: */ -#define foreach_array(__array, __list) \ - list_for_each_entry(struct ir3_array, __array, __list, node) - -/* Check if condition is true for any src instruction. - */ -static inline bool -check_src_cond(struct ir3_instruction *instr, bool (*cond)(struct ir3_instruction *)) -{ - struct ir3_register *reg; - - /* Note that this is also used post-RA so skip the ssa iterator: */ - foreach_src (reg, instr) { - struct ir3_instruction *src = reg->instr; - - if (!src) - continue; - - /* meta:split/collect aren't real instructions, the thing that - * we actually care about is *their* srcs - */ - if ((src->opc == OPC_META_SPLIT) || (src->opc == OPC_META_COLLECT)) { - if (check_src_cond(src, cond)) - return true; - } else { - if (cond(src)) - return true; - } - } - - return false; -} - -/* dump: */ -void ir3_print(struct ir3 *ir); -void ir3_print_instr(struct ir3_instruction *instr); - -/* delay calculation: */ -int ir3_delayslots(struct ir3_instruction *assigner, - struct ir3_instruction *consumer, unsigned n, bool soft); -unsigned ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr, - bool soft, bool pred); -void ir3_remove_nops(struct ir3 *ir); - -/* dead code elimination: */ -struct ir3_shader_variant; -void ir3_dce(struct ir3 *ir, struct ir3_shader_variant *so); - -/* fp16 conversion folding */ -void ir3_cf(struct ir3 *ir); - -/* copy-propagate: */ -void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so); - -/* group neighbors and insert mov's to resolve conflicts: */ -void ir3_group(struct ir3 *ir); - -/* Sethi–Ullman numbering: */ -void ir3_sun(struct ir3 *ir); - -/* scheduling: */ -void ir3_sched_add_deps(struct ir3 *ir); -int ir3_sched(struct ir3 *ir); - -struct ir3_context; -int ir3_postsched(struct ir3_context *ctx); - -bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so); - -/* register assignment: */ -struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler); -int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor); - -/* legalize: */ -void ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary); - -static inline bool -ir3_has_latency_to_hide(struct ir3 *ir) -{ - /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't - * know the nature of the fragment shader. Just assume it will have - * latency to hide: - */ - if (ir->type != MESA_SHADER_FRAGMENT) - return true; - - foreach_block (block, &ir->block_list) { - foreach_instr (instr, &block->instr_list) { - if (is_tex_or_prefetch(instr)) - return true; - - if (is_load(instr)) { - switch (instr->opc) { - case OPC_LDLV: - case OPC_LDL: - case OPC_LDLW: - break; - default: - return true; - } - } - } - } - - return false; -} - -/* ************************************************************************* */ -/* instruction helpers */ - -/* creates SSA src of correct type (ie. half vs full precision) */ -static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr, - struct ir3_instruction *src, unsigned flags) -{ - struct ir3_register *reg; - if (src->regs[0]->flags & IR3_REG_HALF) - flags |= IR3_REG_HALF; - reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags); - reg->instr = src; - reg->wrmask = src->regs[0]->wrmask; - return reg; -} - -static inline struct ir3_register * __ssa_dst(struct ir3_instruction *instr) -{ - struct ir3_register *reg = ir3_reg_create(instr, 0, 0); - reg->flags |= IR3_REG_SSA; - return reg; -} - -static inline struct ir3_instruction * -create_immed_typed(struct ir3_block *block, uint32_t val, type_t type) -{ - struct ir3_instruction *mov; - unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; - - mov = ir3_instr_create(block, OPC_MOV); - mov->cat1.src_type = type; - mov->cat1.dst_type = type; - __ssa_dst(mov)->flags |= flags; - ir3_reg_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val; - - return mov; -} - -static inline struct ir3_instruction * -create_immed(struct ir3_block *block, uint32_t val) -{ - return create_immed_typed(block, val, TYPE_U32); -} - -static inline struct ir3_instruction * -create_uniform_typed(struct ir3_block *block, unsigned n, type_t type) -{ - struct ir3_instruction *mov; - unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; - - mov = ir3_instr_create(block, OPC_MOV); - mov->cat1.src_type = type; - mov->cat1.dst_type = type; - __ssa_dst(mov)->flags |= flags; - ir3_reg_create(mov, n, IR3_REG_CONST | flags); - - return mov; -} - -static inline struct ir3_instruction * -create_uniform(struct ir3_block *block, unsigned n) -{ - return create_uniform_typed(block, n, TYPE_F32); -} - -static inline struct ir3_instruction * -create_uniform_indirect(struct ir3_block *block, int n, - struct ir3_instruction *address) -{ - struct ir3_instruction *mov; - - mov = ir3_instr_create(block, OPC_MOV); - mov->cat1.src_type = TYPE_U32; - mov->cat1.dst_type = TYPE_U32; - __ssa_dst(mov); - ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n; - - ir3_instr_set_address(mov, address); - - return mov; -} - -static inline struct ir3_instruction * -ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type) -{ - struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV); - __ssa_dst(instr); - if (src->regs[0]->flags & IR3_REG_ARRAY) { - struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY); - src_reg->array = src->regs[0]->array; - } else { - __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH); - } - debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV)); - instr->cat1.src_type = type; - instr->cat1.dst_type = type; - return instr; -} - -static inline struct ir3_instruction * -ir3_COV(struct ir3_block *block, struct ir3_instruction *src, - type_t src_type, type_t dst_type) -{ - struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV); - unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0; - unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0; - - debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags); - - __ssa_dst(instr)->flags |= dst_flags; - __ssa_src(instr, src, 0); - instr->cat1.src_type = src_type; - instr->cat1.dst_type = dst_type; - debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY)); - return instr; -} - -static inline struct ir3_instruction * -ir3_NOP(struct ir3_block *block) -{ - return ir3_instr_create(block, OPC_NOP); -} - -#define IR3_INSTR_0 0 - -#define __INSTR0(flag, name, opc) \ -static inline struct ir3_instruction * \ -ir3_##name(struct ir3_block *block) \ -{ \ - struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ - instr->flags |= flag; \ - return instr; \ -} -#define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name) -#define INSTR0(name) __INSTR0(0, name, OPC_##name) - -#define __INSTR1(flag, name, opc) \ -static inline struct ir3_instruction * \ -ir3_##name(struct ir3_block *block, \ - struct ir3_instruction *a, unsigned aflags) \ -{ \ - struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ - __ssa_dst(instr); \ - __ssa_src(instr, a, aflags); \ - instr->flags |= flag; \ - return instr; \ -} -#define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name) -#define INSTR1(name) __INSTR1(0, name, OPC_##name) - -#define __INSTR2(flag, name, opc) \ -static inline struct ir3_instruction * \ -ir3_##name(struct ir3_block *block, \ - struct ir3_instruction *a, unsigned aflags, \ - struct ir3_instruction *b, unsigned bflags) \ -{ \ - struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ - __ssa_dst(instr); \ - __ssa_src(instr, a, aflags); \ - __ssa_src(instr, b, bflags); \ - instr->flags |= flag; \ - return instr; \ -} -#define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name) -#define INSTR2(name) __INSTR2(0, name, OPC_##name) - -#define __INSTR3(flag, name, opc) \ -static inline struct ir3_instruction * \ -ir3_##name(struct ir3_block *block, \ - struct ir3_instruction *a, unsigned aflags, \ - struct ir3_instruction *b, unsigned bflags, \ - struct ir3_instruction *c, unsigned cflags) \ -{ \ - struct ir3_instruction *instr = \ - ir3_instr_create2(block, opc, 4); \ - __ssa_dst(instr); \ - __ssa_src(instr, a, aflags); \ - __ssa_src(instr, b, bflags); \ - __ssa_src(instr, c, cflags); \ - instr->flags |= flag; \ - return instr; \ -} -#define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name) -#define INSTR3(name) __INSTR3(0, name, OPC_##name) - -#define __INSTR4(flag, name, opc) \ -static inline struct ir3_instruction * \ -ir3_##name(struct ir3_block *block, \ - struct ir3_instruction *a, unsigned aflags, \ - struct ir3_instruction *b, unsigned bflags, \ - struct ir3_instruction *c, unsigned cflags, \ - struct ir3_instruction *d, unsigned dflags) \ -{ \ - struct ir3_instruction *instr = \ - ir3_instr_create2(block, opc, 5); \ - __ssa_dst(instr); \ - __ssa_src(instr, a, aflags); \ - __ssa_src(instr, b, bflags); \ - __ssa_src(instr, c, cflags); \ - __ssa_src(instr, d, dflags); \ - instr->flags |= flag; \ - return instr; \ -} -#define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name) -#define INSTR4(name) __INSTR4(0, name, OPC_##name) - -/* cat0 instructions: */ -INSTR1(B) -INSTR0(JUMP) -INSTR1(KILL) -INSTR0(END) -INSTR0(CHSH) -INSTR0(CHMASK) -INSTR1(PREDT) -INSTR0(PREDF) -INSTR0(PREDE) - -/* cat2 instructions, most 2 src but some 1 src: */ -INSTR2(ADD_F) -INSTR2(MIN_F) -INSTR2(MAX_F) -INSTR2(MUL_F) -INSTR1(SIGN_F) -INSTR2(CMPS_F) -INSTR1(ABSNEG_F) -INSTR2(CMPV_F) -INSTR1(FLOOR_F) -INSTR1(CEIL_F) -INSTR1(RNDNE_F) -INSTR1(RNDAZ_F) -INSTR1(TRUNC_F) -INSTR2(ADD_U) -INSTR2(ADD_S) -INSTR2(SUB_U) -INSTR2(SUB_S) -INSTR2(CMPS_U) -INSTR2(CMPS_S) -INSTR2(MIN_U) -INSTR2(MIN_S) -INSTR2(MAX_U) -INSTR2(MAX_S) -INSTR1(ABSNEG_S) -INSTR2(AND_B) -INSTR2(OR_B) -INSTR1(NOT_B) -INSTR2(XOR_B) -INSTR2(CMPV_U) -INSTR2(CMPV_S) -INSTR2(MUL_U24) -INSTR2(MUL_S24) -INSTR2(MULL_U) -INSTR1(BFREV_B) -INSTR1(CLZ_S) -INSTR1(CLZ_B) -INSTR2(SHL_B) -INSTR2(SHR_B) -INSTR2(ASHR_B) -INSTR2(BARY_F) -INSTR2(MGEN_B) -INSTR2(GETBIT_B) -INSTR1(SETRM) -INSTR1(CBITS_B) -INSTR2(SHB) -INSTR2(MSAD) - -/* cat3 instructions: */ -INSTR3(MAD_U16) -INSTR3(MADSH_U16) -INSTR3(MAD_S16) -INSTR3(MADSH_M16) -INSTR3(MAD_U24) -INSTR3(MAD_S24) -INSTR3(MAD_F16) -INSTR3(MAD_F32) -/* NOTE: SEL_B32 checks for zero vs nonzero */ -INSTR3(SEL_B16) -INSTR3(SEL_B32) -INSTR3(SEL_S16) -INSTR3(SEL_S32) -INSTR3(SEL_F16) -INSTR3(SEL_F32) -INSTR3(SAD_S16) -INSTR3(SAD_S32) - -/* cat4 instructions: */ -INSTR1(RCP) -INSTR1(RSQ) -INSTR1(HRSQ) -INSTR1(LOG2) -INSTR1(HLOG2) -INSTR1(EXP2) -INSTR1(HEXP2) -INSTR1(SIN) -INSTR1(COS) -INSTR1(SQRT) - -/* cat5 instructions: */ -INSTR1(DSX) -INSTR1(DSXPP_1) -INSTR1(DSY) -INSTR1(DSYPP_1) -INSTR1F(3D, DSX) -INSTR1F(3D, DSY) -INSTR1(RGETPOS) - -static inline struct ir3_instruction * -ir3_SAM(struct ir3_block *block, opc_t opc, type_t type, - unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex, - struct ir3_instruction *src0, struct ir3_instruction *src1) -{ - struct ir3_instruction *sam; - - sam = ir3_instr_create(block, opc); - sam->flags |= flags; - __ssa_dst(sam)->wrmask = wrmask; - if (flags & IR3_INSTR_S2EN) { - __ssa_src(sam, samp_tex, IR3_REG_HALF); - } - if (src0) { - __ssa_src(sam, src0, 0); - } - if (src1) { - __ssa_src(sam, src1, 0); - } - sam->cat5.type = type; - - return sam; -} - -/* cat6 instructions: */ -INSTR2(LDLV) -INSTR3(LDG) -INSTR3(LDL) -INSTR3(LDLW) -INSTR3(STG) -INSTR3(STL) -INSTR3(STLW) -INSTR1(RESINFO) -INSTR1(RESFMT) -INSTR2(ATOMIC_ADD) -INSTR2(ATOMIC_SUB) -INSTR2(ATOMIC_XCHG) -INSTR2(ATOMIC_INC) -INSTR2(ATOMIC_DEC) -INSTR2(ATOMIC_CMPXCHG) -INSTR2(ATOMIC_MIN) -INSTR2(ATOMIC_MAX) -INSTR2(ATOMIC_AND) -INSTR2(ATOMIC_OR) -INSTR2(ATOMIC_XOR) -INSTR2(LDC) -#if GPU >= 600 -INSTR3(STIB); -INSTR2(LDIB); -INSTR3F(G, ATOMIC_ADD) -INSTR3F(G, ATOMIC_SUB) -INSTR3F(G, ATOMIC_XCHG) -INSTR3F(G, ATOMIC_INC) -INSTR3F(G, ATOMIC_DEC) -INSTR3F(G, ATOMIC_CMPXCHG) -INSTR3F(G, ATOMIC_MIN) -INSTR3F(G, ATOMIC_MAX) -INSTR3F(G, ATOMIC_AND) -INSTR3F(G, ATOMIC_OR) -INSTR3F(G, ATOMIC_XOR) -#elif GPU >= 400 -INSTR3(LDGB) -INSTR4(STGB) -INSTR4(STIB) -INSTR4F(G, ATOMIC_ADD) -INSTR4F(G, ATOMIC_SUB) -INSTR4F(G, ATOMIC_XCHG) -INSTR4F(G, ATOMIC_INC) -INSTR4F(G, ATOMIC_DEC) -INSTR4F(G, ATOMIC_CMPXCHG) -INSTR4F(G, ATOMIC_MIN) -INSTR4F(G, ATOMIC_MAX) -INSTR4F(G, ATOMIC_AND) -INSTR4F(G, ATOMIC_OR) -INSTR4F(G, ATOMIC_XOR) -#endif - -INSTR4F(G, STG) - -/* cat7 instructions: */ -INSTR0(BAR) -INSTR0(FENCE) - -/* meta instructions: */ -INSTR0(META_TEX_PREFETCH); - -/* ************************************************************************* */ -/* split this out or find some helper to use.. like main/bitset.h.. */ - -#include -#include "util/bitset.h" - -#define MAX_REG 256 - -typedef BITSET_DECLARE(regmask_t, 2 * MAX_REG); - -static inline bool -__regmask_get(regmask_t *regmask, struct ir3_register *reg, unsigned n) -{ - if (reg->merged) { - /* a6xx+ case, with merged register file, we track things in terms - * of half-precision registers, with a full precisions register - * using two half-precision slots: - */ - if (reg->flags & IR3_REG_HALF) { - return BITSET_TEST(*regmask, n); - } else { - n *= 2; - return BITSET_TEST(*regmask, n) || BITSET_TEST(*regmask, n+1); - } - } else { - /* pre a6xx case, with separate register file for half and full - * precision: - */ - if (reg->flags & IR3_REG_HALF) - n += MAX_REG; - return BITSET_TEST(*regmask, n); - } -} - -static inline void -__regmask_set(regmask_t *regmask, struct ir3_register *reg, unsigned n) -{ - if (reg->merged) { - /* a6xx+ case, with merged register file, we track things in terms - * of half-precision registers, with a full precisions register - * using two half-precision slots: - */ - if (reg->flags & IR3_REG_HALF) { - BITSET_SET(*regmask, n); - } else { - n *= 2; - BITSET_SET(*regmask, n); - BITSET_SET(*regmask, n+1); - } - } else { - /* pre a6xx case, with separate register file for half and full - * precision: - */ - if (reg->flags & IR3_REG_HALF) - n += MAX_REG; - BITSET_SET(*regmask, n); - } -} - -static inline void regmask_init(regmask_t *regmask) -{ - memset(regmask, 0, sizeof(*regmask)); -} - -static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg) -{ - if (reg->flags & IR3_REG_RELATIV) { - for (unsigned i = 0; i < reg->size; i++) - __regmask_set(regmask, reg, reg->array.offset + i); - } else { - for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++) - if (mask & 1) - __regmask_set(regmask, reg, n); - } -} - -static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b) -{ - unsigned i; - for (i = 0; i < ARRAY_SIZE(*dst); i++) - (*dst)[i] = (*a)[i] | (*b)[i]; -} - -static inline bool regmask_get(regmask_t *regmask, - struct ir3_register *reg) -{ - if (reg->flags & IR3_REG_RELATIV) { - for (unsigned i = 0; i < reg->size; i++) - if (__regmask_get(regmask, reg, reg->array.offset + i)) - return true; - } else { - for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++) - if (mask & 1) - if (__regmask_get(regmask, reg, n)) - return true; - } - return false; -} - -/* ************************************************************************* */ - -#endif /* IR3_H_ */ diff --git a/tinygrad/extra/disassemblers/adreno/shader_enums.h b/tinygrad/extra/disassemblers/adreno/shader_enums.h deleted file mode 100644 index b33a9172..00000000 --- a/tinygrad/extra/disassemblers/adreno/shader_enums.h +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Mesa 3-D graphics library - * - * Copyright (C) 1999-2008 Brian Paul All Rights Reserved. - * Copyright (C) 2009 VMware, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef SHADER_ENUMS_H -#define SHADER_ENUMS_H - -#include - -/* Project-wide (GL and Vulkan) maximum. */ -#define MAX_DRAW_BUFFERS 8 - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Shader stages. - * - * The order must match how shaders are ordered in the pipeline. - * The GLSL linker assumes that if i is the maximum number of - * invocations in a sub-group. The maximum - * supported in this extension is 64." - * - * The spec defines this as a uniform. However, it's highly unlikely that - * implementations actually treat it as a uniform (which is loaded from a - * constant buffer). Most likely, this is an implementation-wide constant, - * or perhaps something that depends on the shader stage. - */ - SYSTEM_VALUE_SUBGROUP_SIZE, - - /** - * From the GL_ARB_shader_ballot spec: - * - * "The variable holds the index of the - * invocation within sub-group. This variable is in the range 0 to - * -1, where is the total - * number of invocations in a sub-group." - */ - SYSTEM_VALUE_SUBGROUP_INVOCATION, - - /** - * From the GL_ARB_shader_ballot spec: - * - * "The variables provide a bitmask for all - * invocations, with one bit per invocation starting with the least - * significant bit, according to the following table, - * - * variable equation for bit values - * -------------------- ------------------------------------ - * gl_SubGroupEqMaskARB bit index == gl_SubGroupInvocationARB - * gl_SubGroupGeMaskARB bit index >= gl_SubGroupInvocationARB - * gl_SubGroupGtMaskARB bit index > gl_SubGroupInvocationARB - * gl_SubGroupLeMaskARB bit index <= gl_SubGroupInvocationARB - * gl_SubGroupLtMaskARB bit index < gl_SubGroupInvocationARB - */ - SYSTEM_VALUE_SUBGROUP_EQ_MASK, - SYSTEM_VALUE_SUBGROUP_GE_MASK, - SYSTEM_VALUE_SUBGROUP_GT_MASK, - SYSTEM_VALUE_SUBGROUP_LE_MASK, - SYSTEM_VALUE_SUBGROUP_LT_MASK, - /*@}*/ - - /** - * Builtin variables added by VK_KHR_subgroups - */ - /*@{*/ - SYSTEM_VALUE_NUM_SUBGROUPS, - SYSTEM_VALUE_SUBGROUP_ID, - /*@}*/ - - /*@}*/ - - /** - * \name Vertex shader system values - */ - /*@{*/ - /** - * OpenGL-style vertex ID. - * - * Section 2.11.7 (Shader Execution), subsection Shader Inputs, of the - * OpenGL 3.3 core profile spec says: - * - * "gl_VertexID holds the integer index i implicitly passed by - * DrawArrays or one of the other drawing commands defined in section - * 2.8.3." - * - * Section 2.8.3 (Drawing Commands) of the same spec says: - * - * "The commands....are equivalent to the commands with the same base - * name (without the BaseVertex suffix), except that the ith element - * transferred by the corresponding draw call will be taken from - * element indices[i] + basevertex of each enabled array." - * - * Additionally, the overview in the GL_ARB_shader_draw_parameters spec - * says: - * - * "In unextended GL, vertex shaders have inputs named gl_VertexID and - * gl_InstanceID, which contain, respectively the index of the vertex - * and instance. The value of gl_VertexID is the implicitly passed - * index of the vertex being processed, which includes the value of - * baseVertex, for those commands that accept it." - * - * gl_VertexID gets basevertex added in. This differs from DirectX where - * SV_VertexID does \b not get basevertex added in. - * - * \note - * If all system values are available, \c SYSTEM_VALUE_VERTEX_ID will be - * equal to \c SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus - * \c SYSTEM_VALUE_BASE_VERTEX. - * - * \sa SYSTEM_VALUE_VERTEX_ID_ZERO_BASE, SYSTEM_VALUE_BASE_VERTEX - */ - SYSTEM_VALUE_VERTEX_ID, - - /** - * Instanced ID as supplied to gl_InstanceID - * - * Values assigned to gl_InstanceID always begin with zero, regardless of - * the value of baseinstance. - * - * Section 11.1.3.9 (Shader Inputs) of the OpenGL 4.4 core profile spec - * says: - * - * "gl_InstanceID holds the integer instance number of the current - * primitive in an instanced draw call (see section 10.5)." - * - * Through a big chain of pseudocode, section 10.5 describes that - * baseinstance is not counted by gl_InstanceID. In that section, notice - * - * "If an enabled vertex attribute array is instanced (it has a - * non-zero divisor as specified by VertexAttribDivisor), the element - * index that is transferred to the GL, for all vertices, is given by - * - * floor(instance/divisor) + baseinstance - * - * If an array corresponding to an attribute required by a vertex - * shader is not enabled, then the corresponding element is taken from - * the current attribute state (see section 10.2)." - * - * Note that baseinstance is \b not included in the value of instance. - */ - SYSTEM_VALUE_INSTANCE_ID, - - /** - * Vulkan InstanceIndex. - * - * InstanceIndex = gl_InstanceID + gl_BaseInstance - */ - SYSTEM_VALUE_INSTANCE_INDEX, - - /** - * DirectX-style vertex ID. - * - * Unlike \c SYSTEM_VALUE_VERTEX_ID, this system value does \b not include - * the value of basevertex. - * - * \sa SYSTEM_VALUE_VERTEX_ID, SYSTEM_VALUE_BASE_VERTEX - */ - SYSTEM_VALUE_VERTEX_ID_ZERO_BASE, - - /** - * Value of \c basevertex passed to \c glDrawElementsBaseVertex and similar - * functions. - * - * \sa SYSTEM_VALUE_VERTEX_ID, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE - */ - SYSTEM_VALUE_BASE_VERTEX, - - /** - * Depending on the type of the draw call (indexed or non-indexed), - * is the value of \c basevertex passed to \c glDrawElementsBaseVertex and - * similar, or is the value of \c first passed to \c glDrawArrays and - * similar. - * - * \note - * It can be used to calculate the \c SYSTEM_VALUE_VERTEX_ID as - * \c SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus \c SYSTEM_VALUE_FIRST_VERTEX. - * - * \sa SYSTEM_VALUE_VERTEX_ID_ZERO_BASE, SYSTEM_VALUE_VERTEX_ID - */ - SYSTEM_VALUE_FIRST_VERTEX, - - /** - * If the Draw command used to start the rendering was an indexed draw - * or not (~0/0). Useful to calculate \c SYSTEM_VALUE_BASE_VERTEX as - * \c SYSTEM_VALUE_IS_INDEXED_DRAW & \c SYSTEM_VALUE_FIRST_VERTEX. - */ - SYSTEM_VALUE_IS_INDEXED_DRAW, - - /** - * Value of \c baseinstance passed to instanced draw entry points - * - * \sa SYSTEM_VALUE_INSTANCE_ID - */ - SYSTEM_VALUE_BASE_INSTANCE, - - /** - * From _ARB_shader_draw_parameters: - * - * "Additionally, this extension adds a further built-in variable, - * gl_DrawID to the shading language. This variable contains the index - * of the draw currently being processed by a Multi* variant of a - * drawing command (such as MultiDrawElements or - * MultiDrawArraysIndirect)." - * - * If GL_ARB_multi_draw_indirect is not supported, this is always 0. - */ - SYSTEM_VALUE_DRAW_ID, - /*@}*/ - - /** - * \name Geometry shader system values - */ - /*@{*/ - SYSTEM_VALUE_INVOCATION_ID, /**< (Also in Tessellation Control shader) */ - /*@}*/ - - /** - * \name Fragment shader system values - */ - /*@{*/ - SYSTEM_VALUE_FRAG_COORD, - SYSTEM_VALUE_POINT_COORD, - SYSTEM_VALUE_FRONT_FACE, - SYSTEM_VALUE_SAMPLE_ID, - SYSTEM_VALUE_SAMPLE_POS, - SYSTEM_VALUE_SAMPLE_MASK_IN, - SYSTEM_VALUE_HELPER_INVOCATION, - SYSTEM_VALUE_COLOR0, - SYSTEM_VALUE_COLOR1, - /*@}*/ - - /** - * \name Tessellation Evaluation shader system values - */ - /*@{*/ - SYSTEM_VALUE_TESS_COORD, - SYSTEM_VALUE_VERTICES_IN, /**< Tessellation vertices in input patch */ - SYSTEM_VALUE_PRIMITIVE_ID, - SYSTEM_VALUE_TESS_LEVEL_OUTER, /**< TES input */ - SYSTEM_VALUE_TESS_LEVEL_INNER, /**< TES input */ - SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT, /**< TCS input for passthru TCS */ - SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT, /**< TCS input for passthru TCS */ - /*@}*/ - - /** - * \name Compute shader system values - */ - /*@{*/ - SYSTEM_VALUE_LOCAL_INVOCATION_ID, - SYSTEM_VALUE_LOCAL_INVOCATION_INDEX, - SYSTEM_VALUE_GLOBAL_INVOCATION_ID, - SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX, - SYSTEM_VALUE_WORK_GROUP_ID, - SYSTEM_VALUE_NUM_WORK_GROUPS, - SYSTEM_VALUE_LOCAL_GROUP_SIZE, - SYSTEM_VALUE_GLOBAL_GROUP_SIZE, - SYSTEM_VALUE_WORK_DIM, - SYSTEM_VALUE_USER_DATA_AMD, - /*@}*/ - - /** Required for VK_KHR_device_group */ - SYSTEM_VALUE_DEVICE_INDEX, - - /** Required for VK_KHX_multiview */ - SYSTEM_VALUE_VIEW_INDEX, - - /** - * Driver internal vertex-count, used (for example) for drivers to - * calculate stride for stream-out outputs. Not externally visible. - */ - SYSTEM_VALUE_VERTEX_CNT, - - /** - * Required for AMD_shader_explicit_vertex_parameter and also used for - * varying-fetch instructions. - * - * The _SIZE value is "primitive size", used to scale i/j in primitive - * space to pixel space. - */ - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL, - SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, - SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, - SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, - SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL, - SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID, - SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE, - SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL, - - /** - * IR3 specific geometry shader and tesselation control shader system - * values that packs invocation id, thread id and vertex id. Having this - * as a nir level system value lets us do the unpacking in nir. - */ - SYSTEM_VALUE_GS_HEADER_IR3, - SYSTEM_VALUE_TCS_HEADER_IR3, - - SYSTEM_VALUE_MAX /**< Number of values */ -} gl_system_value; - -const char *gl_system_value_name(gl_system_value sysval); - -/** - * The possible interpolation qualifiers that can be applied to a fragment - * shader input in GLSL. - * - * Note: INTERP_MODE_NONE must be 0 so that memsetting the - * ir_variable data structure to 0 causes the default behavior. - */ -enum glsl_interp_mode -{ - INTERP_MODE_NONE = 0, - INTERP_MODE_SMOOTH, - INTERP_MODE_FLAT, - INTERP_MODE_NOPERSPECTIVE, - INTERP_MODE_EXPLICIT, - INTERP_MODE_COUNT /**< Number of interpolation qualifiers */ -}; - -enum glsl_interface_packing { - GLSL_INTERFACE_PACKING_STD140, - GLSL_INTERFACE_PACKING_SHARED, - GLSL_INTERFACE_PACKING_PACKED, - GLSL_INTERFACE_PACKING_STD430 -}; - -const char *glsl_interp_mode_name(enum glsl_interp_mode qual); - -/** - * Fragment program results - */ -typedef enum -{ - FRAG_RESULT_DEPTH = 0, - FRAG_RESULT_STENCIL = 1, - /* If a single color should be written to all render targets, this - * register is written. No FRAG_RESULT_DATAn will be written. - */ - FRAG_RESULT_COLOR = 2, - FRAG_RESULT_SAMPLE_MASK = 3, - - /* FRAG_RESULT_DATAn are the per-render-target (GLSL gl_FragData[n] - * or ARB_fragment_program fragment.color[n]) color results. If - * any are written, FRAG_RESULT_COLOR will not be written. - * FRAG_RESULT_DATA1 and up are simply for the benefit of - * gl_frag_result_name() and not to be construed as an upper bound - */ - FRAG_RESULT_DATA0 = 4, - FRAG_RESULT_DATA1, - FRAG_RESULT_DATA2, - FRAG_RESULT_DATA3, - FRAG_RESULT_DATA4, - FRAG_RESULT_DATA5, - FRAG_RESULT_DATA6, - FRAG_RESULT_DATA7, -} gl_frag_result; - -const char *gl_frag_result_name(gl_frag_result result); - -#define FRAG_RESULT_MAX (FRAG_RESULT_DATA0 + MAX_DRAW_BUFFERS) - -/** - * \brief Layout qualifiers for gl_FragDepth. - * - * Extension AMD_conservative_depth allows gl_FragDepth to be redeclared with - * a layout qualifier. - * - * \see enum ir_depth_layout - */ -enum gl_frag_depth_layout -{ - FRAG_DEPTH_LAYOUT_NONE, /**< No layout is specified. */ - FRAG_DEPTH_LAYOUT_ANY, - FRAG_DEPTH_LAYOUT_GREATER, - FRAG_DEPTH_LAYOUT_LESS, - FRAG_DEPTH_LAYOUT_UNCHANGED -}; - -/** - * \brief Buffer access qualifiers - */ -enum gl_access_qualifier -{ - ACCESS_COHERENT = (1 << 0), - ACCESS_RESTRICT = (1 << 1), - ACCESS_VOLATILE = (1 << 2), - ACCESS_NON_READABLE = (1 << 3), - ACCESS_NON_WRITEABLE = (1 << 4), - - /** The access may use a non-uniform buffer or image index */ - ACCESS_NON_UNIFORM = (1 << 5), - - /* This has the same semantics as NIR_INTRINSIC_CAN_REORDER, only to be - * used with loads. In other words, it means that the load can be - * arbitrarily reordered, or combined with other loads to the same address. - * It is implied by ACCESS_NON_WRITEABLE together with ACCESS_RESTRICT, and - * a lack of ACCESS_COHERENT and ACCESS_VOLATILE. - */ - ACCESS_CAN_REORDER = (1 << 6), - - /** Use as little cache space as possible. */ - ACCESS_STREAM_CACHE_POLICY = (1 << 7), -}; - -/** - * \brief Blend support qualifiers - */ -enum gl_advanced_blend_mode -{ - BLEND_NONE = 0x0000, - - BLEND_MULTIPLY = 0x0001, - BLEND_SCREEN = 0x0002, - BLEND_OVERLAY = 0x0004, - BLEND_DARKEN = 0x0008, - BLEND_LIGHTEN = 0x0010, - BLEND_COLORDODGE = 0x0020, - BLEND_COLORBURN = 0x0040, - BLEND_HARDLIGHT = 0x0080, - BLEND_SOFTLIGHT = 0x0100, - BLEND_DIFFERENCE = 0x0200, - BLEND_EXCLUSION = 0x0400, - BLEND_HSL_HUE = 0x0800, - BLEND_HSL_SATURATION = 0x1000, - BLEND_HSL_COLOR = 0x2000, - BLEND_HSL_LUMINOSITY = 0x4000, - - BLEND_ALL = 0x7fff, -}; - -enum blend_func -{ - BLEND_FUNC_ADD, - BLEND_FUNC_SUBTRACT, - BLEND_FUNC_REVERSE_SUBTRACT, - BLEND_FUNC_MIN, - BLEND_FUNC_MAX, -}; - -enum blend_factor -{ - BLEND_FACTOR_ZERO, - BLEND_FACTOR_SRC_COLOR, - BLEND_FACTOR_DST_COLOR, - BLEND_FACTOR_SRC_ALPHA, - BLEND_FACTOR_DST_ALPHA, - BLEND_FACTOR_CONSTANT_COLOR, - BLEND_FACTOR_CONSTANT_ALPHA, - BLEND_FACTOR_SRC_ALPHA_SATURATE, -}; - -enum gl_tess_spacing -{ - TESS_SPACING_UNSPECIFIED, - TESS_SPACING_EQUAL, - TESS_SPACING_FRACTIONAL_ODD, - TESS_SPACING_FRACTIONAL_EVEN, -}; - -/** - * A compare function enum for use in compiler lowering passes. This is in - * the same order as GL's compare functions (shifted down by GL_NEVER), and is - * exactly the same as gallium's PIPE_FUNC_*. - */ -enum compare_func -{ - COMPARE_FUNC_NEVER, - COMPARE_FUNC_LESS, - COMPARE_FUNC_EQUAL, - COMPARE_FUNC_LEQUAL, - COMPARE_FUNC_GREATER, - COMPARE_FUNC_NOTEQUAL, - COMPARE_FUNC_GEQUAL, - COMPARE_FUNC_ALWAYS, -}; - -/** - * Arrangements for grouping invocations from NV_compute_shader_derivatives. - * - * The extension provides new layout qualifiers that support two different - * arrangements of compute shader invocations for the purpose of derivative - * computation. When specifying - * - * layout(derivative_group_quadsNV) in; - * - * compute shader invocations are grouped into 2x2x1 arrays whose four local - * invocation ID values follow the pattern: - * - * +-----------------+------------------+ - * | (2x+0, 2y+0, z) | (2x+1, 2y+0, z) | - * +-----------------+------------------+ - * | (2x+0, 2y+1, z) | (2x+1, 2y+1, z) | - * +-----------------+------------------+ - * - * where Y increases from bottom to top. When specifying - * - * layout(derivative_group_linearNV) in; - * - * compute shader invocations are grouped into 2x2x1 arrays whose four local - * invocation index values follow the pattern: - * - * +------+------+ - * | 4n+0 | 4n+1 | - * +------+------+ - * | 4n+2 | 4n+3 | - * +------+------+ - * - * If neither layout qualifier is specified, derivatives in compute shaders - * return zero, which is consistent with the handling of built-in texture - * functions like texture() in GLSL 4.50 compute shaders. - */ -enum gl_derivative_group { - DERIVATIVE_GROUP_NONE = 0, - DERIVATIVE_GROUP_QUADS, - DERIVATIVE_GROUP_LINEAR, -}; - -enum float_controls -{ - FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE = 0x0000, - FLOAT_CONTROLS_DENORM_PRESERVE_FP16 = 0x0001, - FLOAT_CONTROLS_DENORM_PRESERVE_FP32 = 0x0002, - FLOAT_CONTROLS_DENORM_PRESERVE_FP64 = 0x0004, - FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 = 0x0008, - FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32 = 0x0010, - FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64 = 0x0020, - FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 = 0x0040, - FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32 = 0x0080, - FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64 = 0x0100, - FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 = 0x0200, - FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 = 0x0400, - FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64 = 0x0800, - FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 = 0x1000, - FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 = 0x2000, - FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 = 0x4000, -}; - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif /* SHADER_ENUMS_H */ diff --git a/tinygrad/extra/disassemblers/adreno/util/bitscan.h b/tinygrad/extra/disassemblers/adreno/util/bitscan.h deleted file mode 100644 index ae93e746..00000000 --- a/tinygrad/extra/disassemblers/adreno/util/bitscan.h +++ /dev/null @@ -1,326 +0,0 @@ -/************************************************************************** - * - * Copyright 2008 VMware, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - - -#ifndef BITSCAN_H -#define BITSCAN_H - -#include -#include -#include -#include - -#if defined(_MSC_VER) -#include -#endif - -#if defined(__POPCNT__) -#include -#endif - -//#include "c99_compat.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * Find first bit set in word. Least significant bit is 1. - * Return 0 if no bits set. - */ -#ifdef HAVE___BUILTIN_FFS -#define ffs __builtin_ffs -#elif defined(_MSC_VER) && (_M_IX86 || _M_ARM || _M_AMD64 || _M_IA64) -static inline -int ffs(int i) -{ - unsigned long index; - if (_BitScanForward(&index, i)) - return index + 1; - else - return 0; -} -#else -extern -int ffs(int i); -#endif - -#ifdef HAVE___BUILTIN_FFSLL -#define ffsll __builtin_ffsll -#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64) -static inline int -ffsll(long long int i) -{ - unsigned long index; - if (_BitScanForward64(&index, i)) - return index + 1; - else - return 0; -} -#else -extern int -ffsll(long long int val); -#endif - - -/* Destructively loop over all of the bits in a mask as in: - * - * while (mymask) { - * int i = u_bit_scan(&mymask); - * ... process element i - * } - * - */ -static inline int -u_bit_scan(unsigned *mask) -{ - const int i = ffs(*mask) - 1; - *mask ^= (1u << i); - return i; -} - -static inline int -u_bit_scan64(uint64_t *mask) -{ - const int i = ffsll(*mask) - 1; - *mask ^= (((uint64_t)1) << i); - return i; -} - -/* Determine if an unsigned value is a power of two. - * - * \note - * Zero is treated as a power of two. - */ -static inline bool -util_is_power_of_two_or_zero(unsigned v) -{ - return (v & (v - 1)) == 0; -} - -/* Determine if an uint64_t value is a power of two. - * - * \note - * Zero is treated as a power of two. - */ -static inline bool -util_is_power_of_two_or_zero64(uint64_t v) -{ - return (v & (v - 1)) == 0; -} - -/* Determine if an unsigned value is a power of two. - * - * \note - * Zero is \b not treated as a power of two. - */ -static inline bool -util_is_power_of_two_nonzero(unsigned v) -{ - /* __POPCNT__ is different from HAVE___BUILTIN_POPCOUNT. The latter - * indicates the existence of the __builtin_popcount function. The former - * indicates that _mm_popcnt_u32 exists and is a native instruction. - * - * The other alternative is to use SSE 4.2 compile-time flags. This has - * two drawbacks. First, there is currently no build infrastructure for - * SSE 4.2 (only 4.1), so that would have to be added. Second, some AMD - * CPUs support POPCNT but not SSE 4.2 (e.g., Barcelona). - */ -#ifdef __POPCNT__ - return _mm_popcnt_u32(v) == 1; -#else - return v != 0 && (v & (v - 1)) == 0; -#endif -} - -/* For looping over a bitmask when you want to loop over consecutive bits - * manually, for example: - * - * while (mask) { - * int start, count, i; - * - * u_bit_scan_consecutive_range(&mask, &start, &count); - * - * for (i = 0; i < count; i++) - * ... process element (start+i) - * } - */ -static inline void -u_bit_scan_consecutive_range(unsigned *mask, int *start, int *count) -{ - if (*mask == 0xffffffff) { - *start = 0; - *count = 32; - *mask = 0; - return; - } - *start = ffs(*mask) - 1; - *count = ffs(~(*mask >> *start)) - 1; - *mask &= ~(((1u << *count) - 1) << *start); -} - -static inline void -u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count) -{ - if (*mask == ~0ull) { - *start = 0; - *count = 64; - *mask = 0; - return; - } - *start = ffsll(*mask) - 1; - *count = ffsll(~(*mask >> *start)) - 1; - *mask &= ~(((((uint64_t)1) << *count) - 1) << *start); -} - - -/** - * Find last bit set in a word. The least significant bit is 1. - * Return 0 if no bits are set. - * Essentially ffs() in the reverse direction. - */ -static inline unsigned -util_last_bit(unsigned u) -{ -#if defined(HAVE___BUILTIN_CLZ) - return u == 0 ? 0 : 32 - __builtin_clz(u); -#elif defined(_MSC_VER) && (_M_IX86 || _M_ARM || _M_AMD64 || _M_IA64) - unsigned long index; - if (_BitScanReverse(&index, u)) - return index + 1; - else - return 0; -#else - unsigned r = 0; - while (u) { - r++; - u >>= 1; - } - return r; -#endif -} - -/** - * Find last bit set in a word. The least significant bit is 1. - * Return 0 if no bits are set. - * Essentially ffsll() in the reverse direction. - */ -static inline unsigned -util_last_bit64(uint64_t u) -{ -#if defined(HAVE___BUILTIN_CLZLL) - return u == 0 ? 0 : 64 - __builtin_clzll(u); -#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64) - unsigned long index; - if (_BitScanReverse64(&index, u)) - return index + 1; - else - return 0; -#else - unsigned r = 0; - while (u) { - r++; - u >>= 1; - } - return r; -#endif -} - -/** - * Find last bit in a word that does not match the sign bit. The least - * significant bit is 1. - * Return 0 if no bits are set. - */ -static inline unsigned -util_last_bit_signed(int i) -{ - if (i >= 0) - return util_last_bit(i); - else - return util_last_bit(~(unsigned)i); -} - -/* Returns a bitfield in which the first count bits starting at start are - * set. - */ -static inline unsigned -u_bit_consecutive(unsigned start, unsigned count) -{ - assert(start + count <= 32); - if (count == 32) - return ~0; - return ((1u << count) - 1) << start; -} - -static inline uint64_t -u_bit_consecutive64(unsigned start, unsigned count) -{ - assert(start + count <= 64); - if (count == 64) - return ~(uint64_t)0; - return (((uint64_t)1 << count) - 1) << start; -} - -/** - * Return number of bits set in n. - */ -static inline unsigned -util_bitcount(unsigned n) -{ -#if defined(HAVE___BUILTIN_POPCOUNT) - return __builtin_popcount(n); -#else - /* K&R classic bitcount. - * - * For each iteration, clear the LSB from the bitfield. - * Requires only one iteration per set bit, instead of - * one iteration per bit less than highest set bit. - */ - unsigned bits; - for (bits = 0; n; bits++) { - n &= n - 1; - } - return bits; -#endif -} - -static inline unsigned -util_bitcount64(uint64_t n) -{ -#ifdef HAVE___BUILTIN_POPCOUNTLL - return __builtin_popcountll(n); -#else - return util_bitcount(n) + util_bitcount(n >> 32); -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif /* BITSCAN_H */ diff --git a/tinygrad/extra/disassemblers/adreno/util/bitset.h b/tinygrad/extra/disassemblers/adreno/util/bitset.h deleted file mode 100644 index 264144c3..00000000 --- a/tinygrad/extra/disassemblers/adreno/util/bitset.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Mesa 3-D graphics library - * - * Copyright (C) 2006 Brian Paul All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - * \file bitset.h - * \brief Bitset of arbitrary size definitions. - * \author Michal Krol - */ - -#ifndef BITSET_H -#define BITSET_H - -//#include "util/bitscan.h" -//#include "util/macros.h" - -/**************************************************************************** - * generic bitset implementation - */ - -#define BITSET_WORD unsigned int -#define BITSET_WORDBITS (sizeof (BITSET_WORD) * 8) - -/* bitset declarations - */ -#define BITSET_WORDS(bits) (((bits) + BITSET_WORDBITS - 1) / BITSET_WORDBITS) -#define BITSET_DECLARE(name, bits) BITSET_WORD name[BITSET_WORDS(bits)] - -/* bitset operations - */ -#define BITSET_COPY(x, y) memcpy( (x), (y), sizeof (x) ) -#define BITSET_EQUAL(x, y) (memcmp( (x), (y), sizeof (x) ) == 0) -#define BITSET_ZERO(x) memset( (x), 0, sizeof (x) ) -#define BITSET_ONES(x) memset( (x), 0xff, sizeof (x) ) - -#define BITSET_BITWORD(b) ((b) / BITSET_WORDBITS) -#define BITSET_BIT(b) (1u << ((b) % BITSET_WORDBITS)) - -/* single bit operations - */ -#define BITSET_TEST(x, b) (((x)[BITSET_BITWORD(b)] & BITSET_BIT(b)) != 0) -#define BITSET_SET(x, b) ((x)[BITSET_BITWORD(b)] |= BITSET_BIT(b)) -#define BITSET_CLEAR(x, b) ((x)[BITSET_BITWORD(b)] &= ~BITSET_BIT(b)) - -#define BITSET_MASK(b) (((b) % BITSET_WORDBITS == 0) ? ~0 : BITSET_BIT(b) - 1) -#define BITSET_RANGE(b, e) ((BITSET_MASK((e) + 1)) & ~(BITSET_BIT(b) - 1)) - -/* bit range operations - */ -#define BITSET_TEST_RANGE(x, b, e) \ - (BITSET_BITWORD(b) == BITSET_BITWORD(e) ? \ - (((x)[BITSET_BITWORD(b)] & BITSET_RANGE(b, e)) != 0) : \ - (assert (!"BITSET_TEST_RANGE: bit range crosses word boundary"), 0)) -#define BITSET_SET_RANGE(x, b, e) \ - (BITSET_BITWORD(b) == BITSET_BITWORD(e) ? \ - ((x)[BITSET_BITWORD(b)] |= BITSET_RANGE(b, e)) : \ - (assert (!"BITSET_SET_RANGE: bit range crosses word boundary"), 0)) -#define BITSET_CLEAR_RANGE(x, b, e) \ - (BITSET_BITWORD(b) == BITSET_BITWORD(e) ? \ - ((x)[BITSET_BITWORD(b)] &= ~BITSET_RANGE(b, e)) : \ - (assert (!"BITSET_CLEAR_RANGE: bit range crosses word boundary"), 0)) - -/* Get first bit set in a bitset. - */ -static inline int -__bitset_ffs(const BITSET_WORD *x, int n) -{ - int i; - - for (i = 0; i < n; i++) { - if (x[i]) - return ffs(x[i]) + BITSET_WORDBITS * i; - } - - return 0; -} - -#define BITSET_FFS(x) __bitset_ffs(x, ARRAY_SIZE(x)) - -static inline unsigned -__bitset_next_set(unsigned i, BITSET_WORD *tmp, - const BITSET_WORD *set, unsigned size) -{ - unsigned bit, word; - - /* NOTE: The initial conditions for this function are very specific. At - * the start of the loop, the tmp variable must be set to *set and the - * initial i value set to 0. This way, if there is a bit set in the first - * word, we ignore the i-value and just grab that bit (so 0 is ok, even - * though 0 may be returned). If the first word is 0, then the value of - * `word` will be 0 and we will go on to look at the second word. - */ - word = BITSET_BITWORD(i); - while (*tmp == 0) { - word++; - - if (word >= BITSET_WORDS(size)) - return size; - - *tmp = set[word]; - } - - /* Find the next set bit in the non-zero word */ - bit = ffs(*tmp) - 1; - - /* Unset the bit */ - *tmp &= ~(1ull << bit); - - return word * BITSET_WORDBITS + bit; -} - -/** - * Iterates over each set bit in a set - * - * @param __i iteration variable, bit number - * @param __set the bitset to iterate (will not be modified) - * @param __size number of bits in the set to consider - */ -#define BITSET_FOREACH_SET(__i, __set, __size) \ - for (BITSET_WORD __tmp = *(__set), *__foo = &__tmp; __foo != NULL; __foo = NULL) \ - for (__i = 0; \ - (__i = __bitset_next_set(__i, &__tmp, __set, __size)) < __size;) - -#ifdef __cplusplus - -/** - * Simple C++ wrapper of a bitset type of static size, with value semantics - * and basic bitwise arithmetic operators. The operators defined below are - * expected to have the same semantics as the same operator applied to other - * fundamental integer types. T is the name of the struct to instantiate - * it as, and N is the number of bits in the bitset. - */ -#define DECLARE_BITSET_T(T, N) struct T { \ - EXPLICIT_CONVERSION \ - operator bool() const \ - { \ - for (unsigned i = 0; i < BITSET_WORDS(N); i++) \ - if (words[i]) \ - return true; \ - return false; \ - } \ - \ - T & \ - operator=(int x) \ - { \ - const T c = {{ (BITSET_WORD)x }}; \ - return *this = c; \ - } \ - \ - friend bool \ - operator==(const T &b, const T &c) \ - { \ - return BITSET_EQUAL(b.words, c.words); \ - } \ - \ - friend bool \ - operator!=(const T &b, const T &c) \ - { \ - return !(b == c); \ - } \ - \ - friend bool \ - operator==(const T &b, int x) \ - { \ - const T c = {{ (BITSET_WORD)x }}; \ - return b == c; \ - } \ - \ - friend bool \ - operator!=(const T &b, int x) \ - { \ - return !(b == x); \ - } \ - \ - friend T \ - operator~(const T &b) \ - { \ - T c; \ - for (unsigned i = 0; i < BITSET_WORDS(N); i++) \ - c.words[i] = ~b.words[i]; \ - return c; \ - } \ - \ - T & \ - operator|=(const T &b) \ - { \ - for (unsigned i = 0; i < BITSET_WORDS(N); i++) \ - words[i] |= b.words[i]; \ - return *this; \ - } \ - \ - friend T \ - operator|(const T &b, const T &c) \ - { \ - T d = b; \ - d |= c; \ - return d; \ - } \ - \ - T & \ - operator&=(const T &b) \ - { \ - for (unsigned i = 0; i < BITSET_WORDS(N); i++) \ - words[i] &= b.words[i]; \ - return *this; \ - } \ - \ - friend T \ - operator&(const T &b, const T &c) \ - { \ - T d = b; \ - d &= c; \ - return d; \ - } \ - \ - bool \ - test(unsigned i) const \ - { \ - return BITSET_TEST(words, i); \ - } \ - \ - T & \ - set(unsigned i) \ - { \ - BITSET_SET(words, i); \ - return *this; \ - } \ - \ - T & \ - clear(unsigned i) \ - { \ - BITSET_CLEAR(words, i); \ - return *this; \ - } \ - \ - BITSET_WORD words[BITSET_WORDS(N)]; \ - } - -#endif - -#endif diff --git a/tinygrad/extra/disassemblers/adreno/util/list.h b/tinygrad/extra/disassemblers/adreno/util/list.h deleted file mode 100644 index 7f36e8c3..00000000 --- a/tinygrad/extra/disassemblers/adreno/util/list.h +++ /dev/null @@ -1,262 +0,0 @@ -/************************************************************************** - * - * Copyright 2006 VMware, Inc., Bismarck, ND. USA. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - **************************************************************************/ - -/** - * \file - * List macros heavily inspired by the Linux kernel - * list handling. No list looping yet. - * - * Is not threadsafe, so common operations need to - * be protected using an external mutex. - */ - -#ifndef _UTIL_LIST_H_ -#define _UTIL_LIST_H_ - - -#include -#include -#include - -#ifdef DEBUG -# define list_assert(cond, msg) assert(cond && msg) -#else -# define list_assert(cond, msg) (void)(0 && (cond)) -#endif - -struct list_head -{ - struct list_head *prev; - struct list_head *next; -}; - -static inline void list_inithead(struct list_head *item) -{ - item->prev = item; - item->next = item; -} - -static inline void list_add(struct list_head *item, struct list_head *list) -{ - item->prev = list; - item->next = list->next; - list->next->prev = item; - list->next = item; -} - -static inline void list_addtail(struct list_head *item, struct list_head *list) -{ - item->next = list; - item->prev = list->prev; - list->prev->next = item; - list->prev = item; -} - -static inline bool list_is_empty(const struct list_head *list); - -static inline void list_replace(struct list_head *from, struct list_head *to) -{ - if (list_is_empty(from)) { - list_inithead(to); - } else { - to->prev = from->prev; - to->next = from->next; - from->next->prev = to; - from->prev->next = to; - } -} - -static inline void list_del(struct list_head *item) -{ - item->prev->next = item->next; - item->next->prev = item->prev; - item->prev = item->next = NULL; -} - -static inline void list_delinit(struct list_head *item) -{ - item->prev->next = item->next; - item->next->prev = item->prev; - item->next = item; - item->prev = item; -} - -static inline bool list_is_empty(const struct list_head *list) -{ - return list->next == list; -} - -/** - * Returns whether the list has exactly one element. - */ -static inline bool list_is_singular(const struct list_head *list) -{ - return list->next != NULL && list->next != list && list->next->next == list; -} - -static inline unsigned list_length(const struct list_head *list) -{ - struct list_head *node; - unsigned length = 0; - for (node = list->next; node != list; node = node->next) - length++; - return length; -} - -static inline void list_splice(struct list_head *src, struct list_head *dst) -{ - if (list_is_empty(src)) - return; - - src->next->prev = dst; - src->prev->next = dst->next; - dst->next->prev = src->prev; - dst->next = src->next; -} - -static inline void list_splicetail(struct list_head *src, struct list_head *dst) -{ - if (list_is_empty(src)) - return; - - src->prev->next = dst; - src->next->prev = dst->prev; - dst->prev->next = src->next; - dst->prev = src->prev; -} - -static inline void list_validate(const struct list_head *list) -{ - struct list_head *node; - assert(list->next->prev == list && list->prev->next == list); - for (node = list->next; node != list; node = node->next) - assert(node->next->prev == node && node->prev->next == node); -} - -#define LIST_ENTRY(__type, __item, __field) \ - ((__type *)(((char *)(__item)) - offsetof(__type, __field))) - -/** - * Cast from a pointer to a member of a struct back to the containing struct. - * - * 'sample' MUST be initialized, or else the result is undefined! - */ -#ifndef container_of -#define container_of(ptr, sample, member) \ - (void *)((char *)(ptr) \ - - ((char *)&(sample)->member - (char *)(sample))) -#endif - -#define list_first_entry(ptr, type, member) \ - LIST_ENTRY(type, (ptr)->next, member) - -#define list_last_entry(ptr, type, member) \ - LIST_ENTRY(type, (ptr)->prev, member) - - -#define LIST_FOR_EACH_ENTRY(pos, head, member) \ - for (pos = NULL, pos = container_of((head)->next, pos, member); \ - &pos->member != (head); \ - pos = container_of(pos->member.next, pos, member)) - -#define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head, member) \ - for (pos = NULL, pos = container_of((head)->next, pos, member), \ - storage = container_of(pos->member.next, pos, member); \ - &pos->member != (head); \ - pos = storage, storage = container_of(storage->member.next, storage, member)) - -#define LIST_FOR_EACH_ENTRY_SAFE_REV(pos, storage, head, member) \ - for (pos = NULL, pos = container_of((head)->prev, pos, member), \ - storage = container_of(pos->member.prev, pos, member); \ - &pos->member != (head); \ - pos = storage, storage = container_of(storage->member.prev, storage, member)) - -#define LIST_FOR_EACH_ENTRY_FROM(pos, start, head, member) \ - for (pos = NULL, pos = container_of((start), pos, member); \ - &pos->member != (head); \ - pos = container_of(pos->member.next, pos, member)) - -#define LIST_FOR_EACH_ENTRY_FROM_REV(pos, start, head, member) \ - for (pos = NULL, pos = container_of((start), pos, member); \ - &pos->member != (head); \ - pos = container_of(pos->member.prev, pos, member)) - -#define list_for_each_entry(type, pos, head, member) \ - for (type *pos = LIST_ENTRY(type, (head)->next, member), \ - *__next = LIST_ENTRY(type, pos->member.next, member); \ - &pos->member != (head); \ - pos = LIST_ENTRY(type, pos->member.next, member), \ - list_assert(pos == __next, "use _safe iterator"), \ - __next = LIST_ENTRY(type, __next->member.next, member)) - -#define list_for_each_entry_safe(type, pos, head, member) \ - for (type *pos = LIST_ENTRY(type, (head)->next, member), \ - *__next = LIST_ENTRY(type, pos->member.next, member); \ - &pos->member != (head); \ - pos = __next, \ - __next = LIST_ENTRY(type, __next->member.next, member)) - -#define list_for_each_entry_rev(type, pos, head, member) \ - for (type *pos = LIST_ENTRY(type, (head)->prev, member), \ - *__prev = LIST_ENTRY(type, pos->member.prev, member); \ - &pos->member != (head); \ - pos = LIST_ENTRY(type, pos->member.prev, member), \ - list_assert(pos == __prev, "use _safe iterator"), \ - __prev = LIST_ENTRY(type, __prev->member.prev, member)) - -#define list_for_each_entry_safe_rev(type, pos, head, member) \ - for (type *pos = LIST_ENTRY(type, (head)->prev, member), \ - *__prev = LIST_ENTRY(type, pos->member.prev, member); \ - &pos->member != (head); \ - pos = __prev, \ - __prev = LIST_ENTRY(type, __prev->member.prev, member)) - -#define list_for_each_entry_from(type, pos, start, head, member) \ - for (type *pos = LIST_ENTRY(type, (start), member); \ - &pos->member != (head); \ - pos = LIST_ENTRY(type, pos->member.next, member)) - -#define list_for_each_entry_from_safe(type, pos, start, head, member) \ - for (type *pos = LIST_ENTRY(type, (start), member), \ - *__next = LIST_ENTRY(type, pos->member.next, member); \ - &pos->member != (head); \ - pos = __next, \ - __next = LIST_ENTRY(type, __next->member.next, member)) - -#define list_for_each_entry_from_rev(type, pos, start, head, member) \ - for (type *pos = LIST_ENTRY(type, (start), member); \ - &pos->member != (head); \ - pos = LIST_ENTRY(type, pos->member.prev, member)) - -#define list_pair_for_each_entry(type, pos1, pos2, head1, head2, member) \ - for (type *pos1 = LIST_ENTRY(type, (head1)->next, member), \ - *pos2 = LIST_ENTRY(type, (head2)->next, member); \ - &pos1->member != (head1) && &pos2->member != (head2); \ - pos1 = LIST_ENTRY(type, pos1->member.next, member), \ - pos2 = LIST_ENTRY(type, pos2->member.next, member)) - -#endif /*_UTIL_LIST_H_*/ diff --git a/tinygrad/extra/disassemblers/adreno/util/macros.h b/tinygrad/extra/disassemblers/adreno/util/macros.h deleted file mode 100644 index a36bdd41..00000000 --- a/tinygrad/extra/disassemblers/adreno/util/macros.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright © 2014 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef UTIL_MACROS_H -#define UTIL_MACROS_H - -#include - -/* Compute the size of an array */ -#ifndef ARRAY_SIZE -# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/* For compatibility with Clang's __has_builtin() */ -#ifndef __has_builtin -# define __has_builtin(x) 0 -#endif - -/** - * __builtin_expect macros - */ -#if !defined(HAVE___BUILTIN_EXPECT) -# define __builtin_expect(x, y) (x) -#endif - -#ifndef likely -# ifdef HAVE___BUILTIN_EXPECT -# define likely(x) __builtin_expect(!!(x), 1) -# define unlikely(x) __builtin_expect(!!(x), 0) -# else -# define likely(x) (x) -# define unlikely(x) (x) -# endif -#endif - - -/** - * Static (compile-time) assertion. - * Basically, use COND to dimension an array. If COND is false/zero the - * array size will be -1 and we'll get a compilation error. - */ -#define STATIC_ASSERT(COND) \ - do { \ - (void) sizeof(char [1 - 2*!(COND)]); \ - } while (0) - - -/** - * Unreachable macro. Useful for suppressing "control reaches end of non-void - * function" warnings. - */ -#if defined(HAVE___BUILTIN_UNREACHABLE) || __has_builtin(__builtin_unreachable) -#define unreachable(str) \ -do { \ - assert(!str); \ - __builtin_unreachable(); \ -} while (0) -#elif defined (_MSC_VER) -#define unreachable(str) \ -do { \ - assert(!str); \ - __assume(0); \ -} while (0) -#else -#define unreachable(str) assert(!str) -#endif - -/** - * Assume macro. Useful for expressing our assumptions to the compiler, - * typically for purposes of silencing warnings. - */ -#if __has_builtin(__builtin_assume) -#define assume(expr) \ -do { \ - assert(expr); \ - __builtin_assume(expr); \ -} while (0) -#elif defined HAVE___BUILTIN_UNREACHABLE -#define assume(expr) ((expr) ? ((void) 0) \ - : (assert(!"assumption failed"), \ - __builtin_unreachable())) -#elif defined (_MSC_VER) -#define assume(expr) __assume(expr) -#else -#define assume(expr) assert(expr) -#endif - -/* Attribute const is used for functions that have no effects other than their - * return value, and only rely on the argument values to compute the return - * value. As a result, calls to it can be CSEed. Note that using memory - * pointed to by the arguments is not allowed for const functions. - */ -#ifdef HAVE_FUNC_ATTRIBUTE_CONST -#define ATTRIBUTE_CONST __attribute__((__const__)) -#else -#define ATTRIBUTE_CONST -#endif - -#ifdef HAVE_FUNC_ATTRIBUTE_FLATTEN -#define FLATTEN __attribute__((__flatten__)) -#else -#define FLATTEN -#endif - -#ifdef HAVE_FUNC_ATTRIBUTE_FORMAT -#define PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a))) -#else -#define PRINTFLIKE(f, a) -#endif - -#ifdef HAVE_FUNC_ATTRIBUTE_MALLOC -#define MALLOCLIKE __attribute__((__malloc__)) -#else -#define MALLOCLIKE -#endif - -/* Forced function inlining */ -/* Note: Clang also sets __GNUC__ (see other cases below) */ -#ifndef ALWAYS_INLINE -# if defined(__GNUC__) -# define ALWAYS_INLINE inline __attribute__((always_inline)) -# elif defined(_MSC_VER) -# define ALWAYS_INLINE __forceinline -# else -# define ALWAYS_INLINE inline -# endif -#endif - -/* Used to optionally mark structures with misaligned elements or size as - * packed, to trade off performance for space. - */ -#ifdef HAVE_FUNC_ATTRIBUTE_PACKED -#define PACKED __attribute__((__packed__)) -#else -#define PACKED -#endif - -/* Attribute pure is used for functions that have no effects other than their - * return value. As a result, calls to it can be dead code eliminated. - */ -#ifdef HAVE_FUNC_ATTRIBUTE_PURE -#define ATTRIBUTE_PURE __attribute__((__pure__)) -#else -#define ATTRIBUTE_PURE -#endif - -#ifdef HAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL -#define ATTRIBUTE_RETURNS_NONNULL __attribute__((__returns_nonnull__)) -#else -#define ATTRIBUTE_RETURNS_NONNULL -#endif - -#ifndef NORETURN -# ifdef _MSC_VER -# define NORETURN __declspec(noreturn) -# elif defined HAVE_FUNC_ATTRIBUTE_NORETURN -# define NORETURN __attribute__((__noreturn__)) -# else -# define NORETURN -# endif -#endif - -#ifdef __cplusplus -/** - * Macro function that evaluates to true if T is a trivially - * destructible type -- that is, if its (non-virtual) destructor - * performs no action and all member variables and base classes are - * trivially destructible themselves. - */ -# if (defined(__clang__) && defined(__has_feature)) -# if __has_feature(has_trivial_destructor) -# define HAS_TRIVIAL_DESTRUCTOR(T) __has_trivial_destructor(T) -# endif -# elif defined(__GNUC__) -# if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3))) -# define HAS_TRIVIAL_DESTRUCTOR(T) __has_trivial_destructor(T) -# endif -# elif defined(_MSC_VER) && !defined(__INTEL_COMPILER) -# define HAS_TRIVIAL_DESTRUCTOR(T) __has_trivial_destructor(T) -# endif -# ifndef HAS_TRIVIAL_DESTRUCTOR - /* It's always safe (if inefficient) to assume that a - * destructor is non-trivial. - */ -# define HAS_TRIVIAL_DESTRUCTOR(T) (false) -# endif -#endif - -/** - * PUBLIC/USED macros - * - * If we build the library with gcc's -fvisibility=hidden flag, we'll - * use the PUBLIC macro to mark functions that are to be exported. - * - * We also need to define a USED attribute, so the optimizer doesn't - * inline a static function that we later use in an alias. - ajax - */ -#ifndef PUBLIC -# if defined(__GNUC__) -# define PUBLIC __attribute__((visibility("default"))) -# define USED __attribute__((used)) -# elif defined(_MSC_VER) -# define PUBLIC __declspec(dllexport) -# define USED -# else -# define PUBLIC -# define USED -# endif -#endif - -/** - * UNUSED marks variables (or sometimes functions) that have to be defined, - * but are sometimes (or always) unused beyond that. A common case is for - * a function parameter to be used in some build configurations but not others. - * Another case is fallback vfuncs that don't do anything with their params. - * - * Note that this should not be used for identifiers used in `assert()`; - * see ASSERTED below. - */ -#ifdef HAVE_FUNC_ATTRIBUTE_UNUSED -#define UNUSED __attribute__((unused)) -#else -#define UNUSED -#endif - -/** - * Use ASSERTED to indicate that an identifier is unused outside of an `assert()`, - * so that assert-free builds don't get "unused variable" warnings. - */ -#ifdef NDEBUG -#define ASSERTED UNUSED -#else -#define ASSERTED -#endif - -#ifdef HAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT -#define MUST_CHECK __attribute__((warn_unused_result)) -#else -#define MUST_CHECK -#endif - -#if defined(__GNUC__) -#define ATTRIBUTE_NOINLINE __attribute__((noinline)) -#else -#define ATTRIBUTE_NOINLINE -#endif - - -/** - * Check that STRUCT::FIELD can hold MAXVAL. We use a lot of bitfields - * in Mesa/gallium. We have to be sure they're of sufficient size to - * hold the largest expected value. - * Note that with MSVC, enums are signed and enum bitfields need one extra - * high bit (always zero) to ensure the max value is handled correctly. - * This macro will detect that with MSVC, but not GCC. - */ -#define ASSERT_BITFIELD_SIZE(STRUCT, FIELD, MAXVAL) \ - do { \ - ASSERTED STRUCT s; \ - s.FIELD = (MAXVAL); \ - assert((int) s.FIELD == (MAXVAL) && "Insufficient bitfield size!"); \ - } while (0) - - -/** Compute ceiling of integer quotient of A divided by B. */ -#define DIV_ROUND_UP( A, B ) ( ((A) + (B) - 1) / (B) ) - -/** Clamp X to [MIN,MAX]. Turn NaN into MIN, arbitrarily. */ -#define CLAMP( X, MIN, MAX ) ( (X)>(MIN) ? ((X)>(MAX) ? (MAX) : (X)) : (MIN) ) - -/** Minimum of two values: */ -#define MIN2( A, B ) ( (A)<(B) ? (A) : (B) ) - -/** Maximum of two values: */ -#define MAX2( A, B ) ( (A)>(B) ? (A) : (B) ) - -/** Minimum and maximum of three values: */ -#define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C)) -#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C)) - -/** Align a value to a power of two */ -#define ALIGN_POT(x, pot_align) (((x) + (pot_align) - 1) & ~((pot_align) - 1)) - -/** - * Macro for declaring an explicit conversion operator. Defaults to an - * implicit conversion if C++11 is not supported. - */ -#if __cplusplus >= 201103L -#define EXPLICIT_CONVERSION explicit -#elif defined(__cplusplus) -#define EXPLICIT_CONVERSION -#endif - -/** Set a single bit */ -#define BITFIELD_BIT(b) (1u << (b)) -/** Set all bits up to excluding bit b */ -#define BITFIELD_MASK(b) \ - ((b) == 32 ? (~0u) : BITFIELD_BIT((b) % 32) - 1) -/** Set count bits starting from bit b */ -#define BITFIELD_RANGE(b, count) \ - (BITFIELD_MASK((b) + (count)) & ~BITFIELD_MASK(b)) - -/** Set a single bit */ -#define BITFIELD64_BIT(b) (1ull << (b)) -/** Set all bits up to excluding bit b */ -#define BITFIELD64_MASK(b) \ - ((b) == 64 ? (~0ull) : BITFIELD64_BIT(b) - 1) -/** Set count bits starting from bit b */ -#define BITFIELD64_RANGE(b, count) \ - (BITFIELD64_MASK((b) + (count)) & ~BITFIELD64_MASK(b)) - -/* TODO: In future we should try to move this to u_debug.h once header - * dependencies are reorganised to allow this. - */ -enum pipe_debug_type -{ - PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1, - PIPE_DEBUG_TYPE_ERROR, - PIPE_DEBUG_TYPE_SHADER_INFO, - PIPE_DEBUG_TYPE_PERF_INFO, - PIPE_DEBUG_TYPE_INFO, - PIPE_DEBUG_TYPE_FALLBACK, - PIPE_DEBUG_TYPE_CONFORMANCE, -}; - -#endif /* UTIL_MACROS_H */ diff --git a/tinygrad/extra/disk_read_speed.py b/tinygrad/extra/disk_read_speed.py deleted file mode 100644 index 6d7303c6..00000000 --- a/tinygrad/extra/disk_read_speed.py +++ /dev/null @@ -1,120 +0,0 @@ -#!/usr/bin/env python3 -import os, ctypes, ctypes.util, io, mmap, pathlib -from tinygrad import Tensor, dtypes, Device -from tinygrad.helpers import Timing, from_mv -libc = ctypes.CDLL(ctypes.util.find_library("c")) - -#from extra.hip_gpu_driver import hip_ioctl - -# sudo su -c "echo 3 > /proc/sys/vm/drop_caches" - -# sudo su -c 'echo 8 > /proc/sys/kernel/printk' -# sudo su -c "echo 'module amdgpu +p' > /sys/kernel/debug/dynamic_debug/control" - -libc.memcpy.argtypes = [ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t] - -libc.read.argtypes = [ctypes.c_int, ctypes.c_void_p, ctypes.c_size_t] -libc.read.restype = ctypes.c_size_t - -libc.malloc.argtypes = [ctypes.c_size_t] -libc.malloc.restype = ctypes.c_void_p - -def read_direct(fd, sz): - with Timing("mmap: ", lambda x: f", {sz/x:.2f} GB/s"): - buf = mmap.mmap(-1, sz, flags=mmap.MAP_SHARED|mmap.MAP_POPULATE) - with Timing("read: ", lambda x: f", {sz/x:.2f} GB/s"): - ret = libc.read(fd, from_mv(buf), sz) - assert ret == sz - -def read_mmap(fd, sz): - with Timing("mmfd: ", lambda x: f", {sz/x:.2f} GB/s"): - buf = mmap.mmap(fd, sz, flags=mmap.MAP_SHARED|mmap.MAP_POPULATE) #|MAP_LOCKED) - t = 0 - for i in range(0, sz, 0x1000): t += buf[i] - -# def _copyin_async(self, dest:T, src:T, size:int): check(hip.hipMemcpyAsync(dest, src, size, hip.hipMemcpyHostToDevice, None)) - -def read_to_gpu_mmap(fd, sz, gpubuf): - with Timing("gpu copyin: ", lambda x: f", {sz/x:.2f} GB/s"): - with Timing("mmfd: ", lambda x: f", {sz/x:.2f} GB/s"): - buf = mmap.mmap(fd, sz, flags=mmap.MAP_SHARED|mmap.MAP_POPULATE) #|MAP_LOCKED) - dev.allocator._copyin_async(gpubuf, from_mv(buf), sz) - dev.synchronize() - -def read_to_gpu_single(fd, sz, gpubuf): - os.lseek(fd, 0, os.SEEK_SET) - with Timing("total: ", lambda x: f", {sz/x:.2f} GB/s"): - with Timing("gpu host alloc: ", lambda x: f", {sz/x:.2f} GB/s"): - hst = dev.allocator._hostalloc(sz) - with Timing("read to host: ", lambda x: f", {sz/x:.2f} GB/s"): - ret = libc.read(fd, hst, sz) - with Timing("gpu host copy: ", lambda x: f", {sz/x:.2f} GB/s"): - dev.allocator._copyin_async(gpubuf, hst, sz) - dev.synchronize() - -def read_to_gpu_pingpong(fd, sz, gpubuf): - psz = 256*1024*1024 - print(f"piece size {psz/(1024*1024):.2f} MB") - with Timing("gpu host alloc: ", lambda x: f", {sz/x:.2f} GB/s"): - hst1 = dev.allocator._hostalloc(psz) - hst2 = dev.allocator._hostalloc(psz) - - os.lseek(fd, 0, os.SEEK_SET) - with Timing("total: ", lambda x: f", {sz/x:.2f} GB/s"): - for i in range(sz//(psz*2)): - with Timing("tfer(0): ", lambda x: f", {psz/x:.2f} GB/s"): - ret = libc.read(fd, hst1, psz) - dev.synchronize() - dev.allocator._copyin_async(gpubuf, hst1, psz) - with Timing("tfer(1): ", lambda x: f", {psz/x:.2f} GB/s"): - ret = libc.read(fd, hst2, psz) - dev.synchronize() - dev.allocator._copyin_async(gpubuf, hst2, psz) - dev.synchronize() - -MAP_LOCKED = 0x2000 -MAP_HUGETLB = 0x40000 - -if __name__ == "__main__": - dev = Device[Device.DEFAULT] - - warm = (Tensor.ones(1024, device=Device.DEFAULT).contiguous() + Tensor.ones(1024, device=Device.DEFAULT).contiguous()).realize() - #fn = "/home/tiny/tinygrad/weights/rng" - fn = pathlib.Path(__file__).parents[1] / "weights/LLaMA-2/70B/consolidated.00.pth" - sz = os.stat(fn).st_size - t = Tensor.empty(sz, dtype=dtypes.uint8, device=f"disk:{fn}") - with Timing("copy: ", lambda x: f", {sz/x:.2f} GB/s"): - on_dev = t.to(Device.DEFAULT).realize() - - exit(0) - - # 4GB of random numbers - #fd = os.open("/home/tiny/tinygrad/weights/rng", os.O_RDWR|os.O_DIRECT) - #sz = os.fstat(fd).st_size // 4 - fd = os.open("/home/tiny/tinygrad/weights/LLaMA/7B/consolidated.00.pth", os.O_RDWR|os.O_DIRECT) - sz = os.fstat(fd).st_size - print(f"read {sz} from {fd}") - - with Timing("gpu alloc: ", lambda x: f", {sz/x:.2f} GB/s"): - gpubuf = dev.allocator._alloc(sz) - # warmup - dev.allocator._copyin_async(gpubuf, from_mv(bytearray(b"\x00\x00\x00\x00"*0x1000)), 0x4000) - print("copying, is warm") - - print("****** read to gpu pingpong") - read_to_gpu_pingpong(fd, sz, gpubuf) - exit(0) - - print("****** read direct") - read_direct(fd, sz) - - print("****** read mmap") - read_mmap(fd, sz) - - print("****** read to gpu single") - read_to_gpu_single(fd, sz, gpubuf) - - print("****** read to gpu mmap") - read_to_gpu_mmap(fd, sz, gpubuf) - - os._exit(0) diff --git a/tinygrad/extra/dsp/Dockerfile b/tinygrad/extra/dsp/Dockerfile deleted file mode 100644 index fd3ff2a9..00000000 --- a/tinygrad/extra/dsp/Dockerfile +++ /dev/null @@ -1,38 +0,0 @@ -# Use a recent Ubuntu base image. -FROM ubuntu:22.04 - -# Install required packages. -RUN apt-get update && apt-get install -y \ - git \ - build-essential \ - python3 \ - python3-pip \ - python3-tomli \ - pkg-config \ - libglib2.0-dev \ - libfdt-dev \ - libpixman-1-dev \ - zlib1g-dev \ - ninja-build \ - meson \ - wget - -# Clone QEMU source (you can pin a specific version if desired) -RUN wget https://download.qemu.org/qemu-9.2.0.tar.xz && tar xvJf qemu-9.2.0.tar.xz - -WORKDIR /qemu-9.2.0 - -RUN apt-get install -y flex bison - -# Configure QEMU to build the hexagon user-mode emulator. -RUN ./configure --target-list=hexagon-linux-user && make -j$(nproc) - -# Optionally, install QEMU into /usr/local (or leave it in place). -RUN make install - -# delete the source (for space) -RUN cd .. && rm -rf /qemu-9.2.0 - -# The QEMU binaries will be in /usr/local/bin. -# Set the entrypoint to bash so you can interact with the container. -ENTRYPOINT ["/bin/bash"] \ No newline at end of file diff --git a/tinygrad/extra/dsp/compile.py b/tinygrad/extra/dsp/compile.py deleted file mode 100755 index cb3c18a8..00000000 --- a/tinygrad/extra/dsp/compile.py +++ /dev/null @@ -1,125 +0,0 @@ -#!/usr/bin/env python3 -import os, ctypes, time, fcntl, mmap -import llvmlite.binding as llvm -from tinygrad.helpers import getenv, to_mv -from tinygrad.runtime.support.elf import elf_loader -from hexdump import hexdump -from tinygrad.runtime.autogen import libc -if getenv("IOCTL"): import run # noqa: F401 # pylint: disable=unused-import - -adsp = ctypes.CDLL(ctypes.util.find_library("adsprpc")) -import adsprpc -import ion -import msm_ion -ION_IOC_ALLOC = 0 -ION_IOC_MAP = 2 -ION_IOC_SHARE = 4 -ION_IOC_CUSTOM = 6 -ION_ADSP_HEAP_ID = 22 -ION_IOMMU_HEAP_ID = 25 - -def ion_iowr(fd, nr, args): - ret = fcntl.ioctl(fd, (3 << 30) | (ctypes.sizeof(args) & 0x1FFF) << 16 | (ord(ion.ION_IOC_MAGIC) & 0xFF) << 8 | (nr & 0xFF), args) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - -if __name__ == "__main__": - # TODO: mmap tensors to the DSP - # call the target function with the mmaped tensors - ion_fd = os.open("/dev/ion", os.O_RDWR | os.O_CLOEXEC) - arg3 = ion.struct_ion_allocation_data(len=0x1000, align=0x1000, heap_id_mask=1<>24 == 1) { - //void *mmaped = *((void**)pra[0].buf.pv); - void *a = HAP_mmap(0, 0x1000, 3, 0, pra[1].dma.fd, 0); - ((char*)a)[0] = 0x55; - ((char*)a)[4] = 0x55; - ((char*)a)[8] = 0x99; - //((char*)a)[1] = 0x9b; - //char ret = ((char*)a)[1]; - HAP_munmap(a, 0x1000); - return 0; - - //return ((int)mmaped)&0xFFFF; - //return ((char*)mmaped)[1]; - //return sizeof(void*); - - //((char*)mmaped)[0] = 55; - //return ((int)mmaped)&0xFFFF; - - //void addr = *((void**)pra[1]) - //return sizeof(remote_buf); - //((char*)pra[1].h64)[0] = 55; - - //return ((char*)mmaped)[1]; - //((char*)mmaped)[0] = 55; - // NOTE: you have to return 0 for outbufs to work - //return ((int)pra[1].h64)&0xFFFF; - } - return 0; - } - """) - with open("/tmp/swag.so", "wb") as f: f.write(obj) - - handle = ctypes.c_int64(-1) - adsp.remote_handle64_open(ctypes.create_string_buffer(b"file:////tmp/swag.so?entry&_modver=1.0&_dom=cdsp"), ctypes.byref(handle)) - print("HANDLE", handle.value) - #print(adsp.remote_handle64_invoke(handle, 0, None)) - - #rem = adsp.remote_register_buf(res, 0x1000, arg2.fd, 4) - #rem = adsp.remote_register_dma_handle(arg2.fd, 0x1000) - #print("remote_register_buf_attr", rem) - - #out = ctypes.c_uint64(0) - #ret = adsp.remote_mmap(arg2.fd, 0, 0, 0x1000, ctypes.byref(out)) - #print(ret) - #print("mapped at", hex(out.value)) - - #arg_2 = ctypes.c_int64(out.value) - arg_2 = ctypes.c_int64(arg2.fd) - pra = (adsprpc.union_remote_arg64 * 3)() - pra[0].buf.pv = ctypes.addressof(arg_2) - pra[0].buf.len = 8 - pra[1].dma.fd = arg2.fd - pra[1].dma.len = 0x1000 - print("invoke") - ret = adsp.remote_handle64_invoke(handle, (1<<24) | (1<<16) | (1 << 4), pra) - print("return value", ret, hex(ret)) - #print(hex(arg_2.value), arg_2.value) - #time.sleep(0.1) - - # flush the cache - """ - flush_data = msm_ion.struct_ion_flush_data(handle=arg3.handle, vaddr=res, offset=0, length=0x1000) - # ION_IOC_CLEAN_INV_CACHES - cd = ion.struct_ion_custom_data( - cmd=(3 << 30) | (ctypes.sizeof(flush_data) & 0x1FFF) << 16 | (ord(msm_ion.ION_IOC_MSM_MAGIC) & 0xFF) << 8 | (2 & 0xFF), - arg=ctypes.addressof(flush_data)) - ret = ion_iowr(ion_fd, ION_IOC_CUSTOM, cd) - - res2 = libc.mmap(0, 0x1000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, arg2.fd, 0) - """ - hexdump(to_mv(res, 0x10)) - os._exit(0) - diff --git a/tinygrad/extra/dsp/gen.sh b/tinygrad/extra/dsp/gen.sh deleted file mode 100755 index 6e3a6267..00000000 --- a/tinygrad/extra/dsp/gen.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -clang2py adsprpc_shared.h -k cdefstum -o adsprpc.py - diff --git a/tinygrad/extra/dsp/hook.py b/tinygrad/extra/dsp/hook.py deleted file mode 100644 index 31d2b4e9..00000000 --- a/tinygrad/extra/dsp/hook.py +++ /dev/null @@ -1,101 +0,0 @@ -import os -print("from import") -del os.environ["LD_PRELOAD"] -import ctypes, ctypes.util -from extra.dsp.run import install_hook, ioctl, libc, get_struct, qcom_dsp, format_struct, to_mv, hexdump - -@ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long) -def _mmap(addr, length, prot, flags, fd, offset): - mmap_type = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long) - orig_mmap = mmap_type(ctypes.addressof(orig_mmap_mv)) - ret = orig_mmap(addr, length, prot, flags, fd, offset) - # ll = os.readlink(f"/proc/self/fd/{fd}") if fd >= 0 else "" - print(f"mmap {addr=}, {length=}, {prot=}, {flags=}, {fd=}, {offset=} {ret=}") - return ret - -#install_hook(libc.ioctl, ioctl) -#orig_mmap_mv = install_hook(libc.mmap, _mmap) -print("import done") -import mmap - -alloc_sizes = {} -mmaped = {} - -def handle_ioctl(fd, request, argp, ret): - fn = os.readlink(f"/proc/self/fd/{fd}") - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - - if fn == "/dev/ion": - if nr == 0: - st = get_struct(argp, qcom_dsp.struct_ion_allocation_data) - print(ret, "ION_IOC_ALLOC", format_struct(st)) - alloc_sizes[st.handle] = st.len - elif nr == 1: - st = get_struct(argp, qcom_dsp.struct_ion_handle_data) - print(ret, "ION_IOC_FREE", format_struct(st)) - if st.handle in alloc_sizes: del alloc_sizes[st.handle] - if st.handle in mmaped: del mmaped[st.handle] - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_ion_fd_data) - print(ret, "ION_IOC_MAP", format_struct(st)) - mmaped[st.handle] = mmap.mmap(st.fd, alloc_sizes[st.handle]) - elif fn == "/dev/adsprpc-smd": - assert chr(itype) == 'R' - if nr == 8: - st = ctypes.c_uint32.from_address(argp) - print(ret, "FASTRPC_IOCTL_GETINFO", st.value) - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_mmap) - print(ret, "FASTRPC_IOCTL_MMAP", format_struct(st)) - elif nr == 1: - # https://research.checkpoint.com/2021/pwn2own-qualcomm-dsp/ - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke) - print(ret, "FASTRPC_IOCTL_INVOKE", format_struct(st)) - # 0xFF000000 = Method index and attribute (the highest byte) - # 0x00FF0000 = Number of input arguments - # 0x0000FF00 = Number of output arguments - # 0x000000F0 = Number of input handles - # 0x0000000F = Number of output handles - - method = (st.sc>>24) & 0xFF - in_args = (st.sc>>16) & 0xFF - out_args = (st.sc>>8) & 0xFF - in_h = (st.sc>>4) & 0xF - out_h = (st.sc>>0) & 0xF - print(f"\tm:{method} ia:{in_args} oa:{out_args} ih:{in_h} oh:{out_h}") - """ - if in_args or out_args: - for arg in range(in_args+out_args): - print(arg, format_struct(st.pra[arg])) - if st.pra[arg].buf.pv is not None: - ww = to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len) - hexdump(to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len)[:0x40]) - """ - elif nr == 6: - print(ret, "FASTRPC_IOCTL_INIT", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_init))) - print(os.readlink(f"/proc/self/fd/{ini.filefd}")) - # print(bytearray(to_mv(ini.file, ini.filelen))) - elif nr == 7: - print(ret, "FASTRPC_IOCTL_INVOKE_ATTRS", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke_attrs))) - elif nr == 12: print(ret, "FASTRPC_IOCTL_CONTROL", format_struct(get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_control))) - elif nr == 4: - st_fd = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke_fd) - st = st_fd.inv - print(ret, "FASTRPC_IOCTL_INVOKE_FD", format_struct(st)) - - method = (st.sc>>24) & 0xFF - in_args = (st.sc>>16) & 0xFF - out_args = (st.sc>>8) & 0xFF - in_h = (st.sc>>4) & 0xF - out_h = (st.sc>>0) & 0xF - print(f"\tm:{method} ia:{in_args} oa:{out_args} ih:{in_h} oh:{out_h}") - - if st.sc in [0x2030200, 0x3040300]: - for handle, mapped in mmaped.items(): - print(f" buffer {handle} {alloc_sizes[handle]:X}") - with open(f"/tmp/buf_{st.sc:X}_{handle}_{alloc_sizes[handle]:X}", "wb") as f: f.write(mapped) - else: - print(f"{ret} UNPARSED {nr}") - else: - print("ioctl", f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", fn) - diff --git a/tinygrad/extra/dsp/include/AEEStdDef.h b/tinygrad/extra/dsp/include/AEEStdDef.h deleted file mode 100644 index 230950f2..00000000 --- a/tinygrad/extra/dsp/include/AEEStdDef.h +++ /dev/null @@ -1,1146 +0,0 @@ -/** - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of The Linux Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef AEESTDDEF_H -#define AEESTDDEF_H -/* -======================================================================= - -FILE: AEEStdDef.h - -DESCRIPTION: definition of basic types, constants, - preprocessor macros - -======================================================================= -*/ - -#include - -#if defined(COMDEF_H) /* guards against a known re-definer */ -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif /* #if !defined(COMDEF_H) */ - -/* ----------------------------------------------------------------------- -** Standard Types -** ----------------------------------------------------------------------- */ - -/* The following definitions are the same accross platforms. This first -** group are the sanctioned types. -*/ -#ifndef _BOOLEAN_DEFINED -typedef unsigned char boolean; /* Boolean value type. */ -#define _BOOLEAN_DEFINED -#endif - -#ifndef _UINT32_DEFINED -typedef uint32_t uint32; /* Unsigned 32 bit value */ -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED -typedef unsigned short uint16; /* Unsigned 16 bit value */ -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED -typedef unsigned char uint8; /* Unsigned 8 bit value */ -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED -typedef int32_t int32; /* Signed 32 bit value */ -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED -typedef signed short int16; /* Signed 16 bit value */ -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED -typedef signed char int8; /* Signed 8 bit value */ -#define _INT8_DEFINED -#endif - -#if defined(__GNUC__) -#define __int64 long long -#endif - -#ifndef _UINT64_DEFINED -typedef unsigned __int64 uint64; /* Unsigned 64 bit value */ -#define _UINT64_DEFINED -#endif - -#ifndef _INT64_DEFINED -typedef __int64 int64; /* Signed 64 bit value */ -#define _INT64_DEFINED -#endif - -#ifndef _BYTE_DEFINED -typedef unsigned char byte; /* byte type */ -#define _BYTE_DEFINED -#endif - - -#ifndef _AEEUID_DEFINED -typedef uint32 AEEUID; -#define _AEEUID_DEFINED -#endif - -#ifndef _AEEIID_DEFINED -typedef uint32 AEEIID; -#define _AEEIID_DEFINED -#endif - -#ifndef _AEECLSID_DEFINED -typedef uint32 AEECLSID; -#define _AEECLSID_DEFINED -#endif - -#ifndef _AEEPRIVID_DEFINED -typedef uint32 AEEPRIVID; -#define _AEEPRIVID_DEFINED -#endif - -#ifndef _AECHAR_DEFINED -typedef uint16 AECHAR; -#define _AECHAR_DEFINED -#endif - -#ifndef _AEERESULT_DEFINED -typedef int AEEResult; -#define _AEERESULT_DEFINED -#endif - -/* ----------------------------------------------------------------------- -** Function Calling Conventions -** ----------------------------------------------------------------------- */ - -#ifndef CDECL -#ifdef _MSC_VER -#define CDECL __cdecl -#else -#define CDECL -#endif /* _MSC_VER */ -#endif /* CDECL */ - -/* ----------------------------------------------------------------------- -** Constants -** ----------------------------------------------------------------------- */ - -#ifndef TRUE -#define TRUE 1 /* Boolean true value. */ -#endif - -#ifndef FALSE -#define FALSE 0 /* Boolean false value. */ -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef MIN_INT8 -#define MIN_INT8 -128 -#endif -#ifndef MIN_INT16 -#define MIN_INT16 -32768 -#endif -#ifndef MIN_INT32 -#define MIN_INT32 (~0x7fffffff) /* -2147483648 is unsigned */ -#endif -#ifndef MIN_INT64 -#define MIN_INT64 (~0x7fffffffffffffffLL) /* -9223372036854775808 is unsigned */ -#endif - -#ifndef MAX_INT8 -#define MAX_INT8 127 -#endif -#ifndef MAX_INT16 -#define MAX_INT16 32767 -#endif -#ifndef MAX_INT32 -#define MAX_INT32 2147483647 -#endif -#ifndef MAX_INT64 -#define MAX_INT64 9223372036854775807LL -#endif - -#ifndef MAX_UINT8 -#define MAX_UINT8 255 -#endif -#ifndef MAX_UINT16 -#define MAX_UINT16 65535 -#endif -#ifndef MAX_UINT32 -#define MAX_UINT32 4294967295u -#endif -#ifndef MAX_UINT64 -#define MAX_UINT64 18446744073709551615uLL -#endif - -#ifndef MIN_AECHAR -#define MIN_AECHAR 0 -#endif -#ifndef MAX_AECHAR -#define MAX_AECHAR 65535 -#endif - - -/* ----------------------------------------------------------------------- -** Preprocessor helpers -** ----------------------------------------------------------------------- */ -#define __STR__(x) #x -#define __TOSTR__(x) __STR__(x) -#define __FILE_LINE__ __FILE__ ":" __TOSTR__(__LINE__) - -/* ----------------------------------------------------------------------- -** Types for code generated from IDL -** ----------------------------------------------------------------------- */ - -#ifndef __QIDL_WCHAR_T_DEFINED__ -#define __QIDL_WCHAR_T_DEFINED__ -typedef uint16 _wchar_t; -#endif - -/* __STRING_OBJECT__ will be deprecated in the future */ -#if !defined(__QIDL_STRING_OBJECT_DEFINED__) && !defined(__STRING_OBJECT__) -#define __QIDL_STRING_OBJECT_DEFINED__ -#define __STRING_OBJECT__ -typedef struct _cstring_s { - char* data; - int dataLen; - int dataLenReq; -} _cstring_t; - -typedef struct _wstring_s { - _wchar_t* data; - int dataLen; - int dataLenReq; -} _wstring_t; -#endif /* __QIDL_STRING_OBJECT_DEFINED__ */ - -/* -======================================================================= - DATA STRUCTURES DOCUMENTATION -======================================================================= - -boolean - -Description: - This type is used to express boolean values (TRUE or FALSE). - -Definition: - typedef unsigned char boolean - -See Also: - byte - int8 - int16 - int32 - int64 - uint32 - uint16 - uint8 - uint64 - -======================================================================= - -uint32 - -Description: - This is a 32-bit unsigned integer. - -Definition: - typedef uint32_t uint32 - -See Also: - boolean - byte - int8 - int16 - int32 - int64 - uint8 - uint16 - uint64 - -======================================================================= - -uint16 - -Description: - This is a 16-bit unsigned integer. - -Definition: - typedef unsigned short uint16 - -See Also: - boolean - byte - int8 - int16 - int32 - int64 - uint8 - uint32 - uint64 - -======================================================================= - -uint8 - -Description: - This is an 8-bit unsigned integer. - -Definition: - typedef unsigned char uint8 - -See Also: - boolean - byte - int8 - int16 - int32 - int64 - uint16 - uint32 - uint64 - -======================================================================= - -int32 - -Description: - This is a 32-bit signed integer. - -Definition: - typedef int32_t int32 - -See Also: - boolean - byte - int8 - int16 - int64 - uint8 - uint16 - uint32 - uint64 - -======================================================================= - -int16 - -Description: - This is a 16-bit signed integer. - -Definition: - typedef signed short int16 - -See Also: - boolean - byte - int8 - int32 - int64 - uint8 - uint16 - uint32 - uint64 - -======================================================================= - -int8 - -Description: - This is an 8-bit signed integer. - -Definition: - typedef signed char int8 - -See Also: - boolean - byte - int16 - int32 - int64 - uint8 - uint16 - uint32 - uint64 - -======================================================================= - -uint64 - -Description: - This is a 64-bit unsigned integer. - -Definition: - typedef unsigned __int64 uint64 - -See Also: - boolean - byte - int8 - int16 - int32 - int64 - uint8 - uint16 - uint32 - -======================================================================= - -int64 - -Description: - This is a 64-bit signed integer. - -Definition: - typedef __int64 int64 - -See Also: - boolean - byte - int8 - int16 - int32 - uint8 - uint16 - uint32 - uint64 - -======================================================================= - -byte - -Description: - This is a byte. - -Definition: - typedef unsigned char byte - -See Also: - boolean - int8 - int16 - int32 - int64 - uint8 - uint16 - uint32 - uint64 - -======================================================================= - -AEEUID - -Description: - This is a BREW unique ID. Used to express unique types, interfaces, classes - groups and privileges. The BREW ClassID Generator generates - unique IDs that can be used anywhere you need a new AEEIID, AEECLSID, - or AEEPRIVID. - -Definition: - typedef uint32 AEEUID - -See Also: - AECHAR - AEECLSID - AEEIID - AEEPRIVID - AEEResult - -======================================================================= - -AEEIID - -Description: - This is an interface ID type, used to denote a BREW interface. It is a special case - of AEEUID. - -Definition: - typedef uint32 AEEIID - -See Also: - AECHAR - AEECLSID - AEEPRIVID - AEEResult - AEEUID - -======================================================================= - -AEECLSID - -Description: - This is a classe ID type, used to denote a BREW class. It is a special case - of AEEUID. - -Definition: - typedef uint32 AEECLSID - -See Also: - AECHAR - AEECLSIDs - AEEIID - AEEPRIVID - AEEResult - AEEUID - -======================================================================= - -AEEPRIVID - -Description: - This is a privilege ID type, used to express a privilege. It is a special case - of AEEUID. - -Definition: - typedef uint32 AEEPRIVID - -See Also: - AECHAR - AEECLSID - AEEIID - AEEResult - AEEUID - -======================================================================= - -AECHAR - -Description: - This is a 16-bit character type. - -Definition: - typedef uint16 AECHAR - -See Also: - AEEPRIVID - AEECLSID - AEEIID - AEEResult - AEEUID - -======================================================================= - -AEEResult - -Description: - This is the standard result type. - -Definition: - typedef int AEEResult - -See Also: - AECHAR - AEEPRIVID - AEECLSID - AEEIID - AEEUID - -======================================================================= - -_wchar_t - -Description: - This is a 16-bit character type corresponding to the IDL 'wchar' - type. - -Definition: - typedef uint16 _wchar_t - -See Also: - _cstring_t - _wstring_t - -======================================================================= - -_cstring_t - -Description: - This structure is used to represent an IDL string when used inside a - sequence or union. - -Definition: - typedef struct _cstring_s { - char* data; - int dataLen; - int dataLenReq; - } _cstring_t; - -Members: - data : A pointer to the NULL-terminated string. - dataLen : The size, in chars, of the buffer pointed to by 'data', - including the NULL terminator. This member is only used - when the structure is part of an rout or inrout - parameter, but must be supplied by the caller as an - input in these cases. - dataLenReq : The size that would have been required to store the - entire result string. This member is only used when the - structure is part of an rout or inrout parameter, when - it is an output value set by the callee. The length of - the returned string (including the NULL terminator) - after a call is the minimum of dataLen and dataLenReq. - -See Also: - _wchar_t - _wstring_t - -======================================================================= - -_wstring_t - -Description: - This structure is used to represent an IDL wstring when used inside a - sequence or union. - -Definition: - typedef struct _wstring_s { - _wchar_t* data; - int dataLen; - int dataLenReq; - } _wstring_t; - -Members: - data : A pointer to the NULL-terminated wide string. - dataLen : The size, in 16-bit characters, of the buffer pointed to - by 'data', including the NULL terminator. This member - is only used when the structure is part of an rout or - inrout parameter, but must be supplied by the caller as - an input in these cases. - dataLenReq : The number of 16-bit characters that would have been - required to store the entire result string. This member - is only used when the structure is part of an rout or - inrout parameter, when it is an output value set by the - callee. The length of the returned wstring (including - the NULL terminator) after a call is the minimum of - dataLen and dataLenReq. - -See Also: - _cstring_t - _wchar_t - -======================================================================= -CONSTANTS DOCUMENTATION -======================================================================= - -TRUE - -Description: - TRUE is the boolean "true." - -Definition: - - #define TRUE 1 - -See Also: - FALSE - NULL - -======================================================================= - -FALSE - -Description: - FALSE is the boolean "false." - -Definition: - - #define FALSE 0 - -See Also: - NULL - TRUE - -======================================================================= - -NULL - -Description: - NULL is the null value, usually used to test a pointer. - -Definition: - - #define NULL 0 - -See Also: - FALSE - TRUE - -======================================================================= - -MIN_INT8 - -Description: - MIN_INT8 is the minimum signed 8-bit integer value. - -Definition: - - #define MIN_INT8 -128 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MIN_INT16 - -Description: - MIN_INT16 is the minimum signed 16-bit integer value - -Definition: - - #define MIN_INT16 -32768 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MIN_INT32 - -Description: - MIN_INT32 is the minimum signed 32-bit integer value. - -Definition: - - #define MIN_INT32 (~0x7fffffff) - -Comments: - Brew MP uses (~0x7fffffff), because -2147483648 is treated as unsigned by compilers. - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT64 - -======================================================================= - -MIN_INT64 - -Description: - MIN_INT64 is the minimum signed 64-bit integer value. - -Definition: - - #define MIN_INT64 (~0x7fffffffffffffffll) - -Comments: - Brew MP uses (~0x7fffffffffffffffll), because -9223372036854775808 is - treated as unsigned by compilers. - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - -======================================================================= - -MAX_INT8 - -Description: - MAX_INT8 is the maximum signed 8-bit integer value - -Definition: - - #define MAX_INT8 127 - -See Also: - MAX_AECHAR - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_INT16 - -Description: - MAX_INT16 is the maximum signed 16-bit integer value. - -Definition: - - #define MAX_INT16 32767 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_INT32 - -Description: - MAX_INT32 is the maximum signed 32-bit integer value. - -Definition: - - #define MAX_INT32 2147483647 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_INT64 - -Description: - MAX_INT64 is the maximum signed 64-bit integer value. - -Definition: - - #define MAX_INT64 9223372036854775807ll - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_UINT8 - -Description: - MAX_UINT8 is the maximum unsigned 8-bit integer value. - -Definition: - - #define MAX_UINT8 255 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_UINT16 - -Description: - MAX_UINT16 is the maximum unsigned 16-bit integer value. - -Definition: - - #define MAX_UINT16 65535 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT32 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_UINT32 - -Description: - MAX_UINT32 is the maximum unsigned 32-bit integer value. - -Definition: - - #define MAX_UINT32 4294967295u - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT64 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_UINT64 - -Description: - MAX_UINT64 is the maximum unsigned 64-bit integer value. - -Definition: - - #define MAX_UINT64 18446744073709551615ull - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MIN_AECHAR - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MIN_AECHAR - -Description: - MIN_AECHAR is the minimum AECHAR value. - -Definition: - - #define MIN_AECHAR 0 - -See Also: - MAX_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= - -MAX_AECHAR - -Description: - MAX_AECHAR is the maximum AECHAR value. - -Definition: - - #define MAX_AECHAR 65535 - -See Also: - MIN_AECHAR - MAX_INT8 - MAX_INT16 - MAX_INT32 - MAX_INT64 - MAX_UINT8 - MAX_UINT16 - MAX_UINT32 - MAX_UINT64 - MIN_INT8 - MIN_INT16 - MIN_INT32 - MIN_INT64 - -======================================================================= -MACROS DOCUMENTATION -======================================================================= - -__STR__() - -Description: - The __STR__() makes a token into a string, used to string-ize things already - defined. - -Definition: - - #define __STR__(x) #x - -Parameters: - x: token to make into a string - -See Also: - __TOSTR__() - __FILE_LINE__ - -======================================================================= - -__TOSTR__() - -Description: - The __TOSTR__() makes a token's value into a string, used to string-ize things - already defined, used with __STR__. - -Definition: - - #define __TOSTR__(x) __STR__(x) - -Parameters: - x: token to evaluate and string-ize - -Evaluation Value: - the token's replacement as a string - -See Also: - __FILE_LINE__ - __STR__() - -======================================================================= - -__FILE_LINE__ - -Description: - The compiler's __FILE__ (a string) and __LINE__ (an integer) are pasted - together as a single string with a ":" between. - -Definition: - - #define __FILE_LINE__ __FILE__ ":" __TOSTR__(__LINE__) - -Evaluation Value: - __FILE__":""__LINE__" - -See Also: - __STR__() - __TOSTR__() - -======================================================================= -*/ - -#endif /* #ifndef AEESTDDEF_H */ - diff --git a/tinygrad/extra/dsp/include/AEEStdErr.h b/tinygrad/extra/dsp/include/AEEStdErr.h deleted file mode 100755 index b52e78d8..00000000 --- a/tinygrad/extra/dsp/include/AEEStdErr.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) 2005-2007, 2012-2013, 2019-2020 Qualcomm Technologies, Inc. - * All Rights Reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef AEESTDERR_H -#define AEESTDERR_H -// -// Basic Error Codes -// -// -#if defined(__hexagon__) - #define AEE_EOFFSET 0x80000400 -#else - #define AEE_EOFFSET 0x00000000 -#endif -/** @defgroup stdbasicerror Basic error codes - * @{ - */ -#define AEE_SUCCESS 0 ///< No error -#define AEE_EUNKNOWN -1 ///< Unknown error (should not use this) - -#define AEE_EFAILED (AEE_EOFFSET + 0x001) ///< General failure -#define AEE_ENOMEMORY (AEE_EOFFSET + 0x002) ///< Memory allocation failed because of insufficient RAM -#define AEE_ECLASSNOTSUPPORT (AEE_EOFFSET + 0x003) ///< Specified class unsupported -#define AEE_EVERSIONNOTSUPPORT (AEE_EOFFSET + 0x004) ///< Version not supported -#define AEE_EALREADYLOADED (AEE_EOFFSET + 0x005) ///< Object already loaded -#define AEE_EUNABLETOLOAD (AEE_EOFFSET + 0x006) ///< Unable to load object/applet -#define AEE_EUNABLETOUNLOAD (AEE_EOFFSET + 0x007) ///< Unable to unload - ///< object/applet -#define AEE_EALARMPENDING (AEE_EOFFSET + 0x008) ///< Alarm is pending -#define AEE_EINVALIDTIME (AEE_EOFFSET + 0x009) ///< Invalid time -#define AEE_EBADCLASS (AEE_EOFFSET + 0x00A) ///< NULL class object -#define AEE_EBADMETRIC (AEE_EOFFSET + 0x00B) ///< Invalid metric specified -#define AEE_EEXPIRED (AEE_EOFFSET + 0x00C) ///< App/Component Expired -#define AEE_EBADSTATE (AEE_EOFFSET + 0x00D) ///< Process or thread is not in expected state -#define AEE_EBADPARM (AEE_EOFFSET + 0x00E) ///< Invalid parameter -#define AEE_ESCHEMENOTSUPPORTED (AEE_EOFFSET + 0x00F) ///< Invalid URL scheme -#define AEE_EBADITEM (AEE_EOFFSET + 0x010) ///< Value out of range -#define AEE_EINVALIDFORMAT (AEE_EOFFSET + 0x011) ///< Invalid format -#define AEE_EINCOMPLETEITEM (AEE_EOFFSET + 0x012) ///< Incomplete item, like length of a string is less that expected -#define AEE_ENOPERSISTMEMORY (AEE_EOFFSET + 0x013) ///< Insufficient flash -#define AEE_EUNSUPPORTED (AEE_EOFFSET + 0x014) ///< API not implemented -#define AEE_EPRIVLEVEL (AEE_EOFFSET + 0x015) ///< Privileges are insufficient - ///< for this operation -#define AEE_ERESOURCENOTFOUND (AEE_EOFFSET + 0x016) ///< Unable to find specified - ///< resource -#define AEE_EREENTERED (AEE_EOFFSET + 0x017) ///< Non re-entrant API - ///< re-entered -#define AEE_EBADTASK (AEE_EOFFSET + 0x018) ///< API called in wrong task - ///< context -#define AEE_EALLOCATED (AEE_EOFFSET + 0x019) ///< App/Module left memory - ///< allocated when released. -#define AEE_EALREADY (AEE_EOFFSET + 0x01A) ///< Operation is already in - ///< progress -#define AEE_EADSAUTHBAD (AEE_EOFFSET + 0x01B) ///< ADS mutual authorization - ///< failed -#define AEE_ENEEDSERVICEPROG (AEE_EOFFSET + 0x01C) ///< Need service programming -#define AEE_EMEMPTR (AEE_EOFFSET + 0x01D) ///< bad memory pointer, expected to be NULL -#define AEE_EHEAP (AEE_EOFFSET + 0x01E) ///< An internal heap error was detected -#define AEE_EIDLE (AEE_EOFFSET + 0x01F) ///< Context (system, interface, - ///< etc.) is idle -#define AEE_EITEMBUSY (AEE_EOFFSET + 0x020) ///< Context (system, interface, - ///< etc.) is busy -#define AEE_EBADSID (AEE_EOFFSET + 0x021) ///< Invalid subscriber ID -#define AEE_ENOTYPE (AEE_EOFFSET + 0x022) ///< No type detected/found -#define AEE_ENEEDMORE (AEE_EOFFSET + 0x023) ///< Need more data/info -#define AEE_EADSCAPS (AEE_EOFFSET + 0x024) ///< ADS Capabilities do not - ///< match those required for phone -#define AEE_EBADSHUTDOWN (AEE_EOFFSET + 0x025) ///< App failed to close properly -#define AEE_EBUFFERTOOSMALL (AEE_EOFFSET + 0x026) ///< Destination buffer given is - ///< too small - ///< or service exists or is - ///< valid -#define AEE_EACKPENDING (AEE_EOFFSET + 0x028) ///< ACK pending on application -#define AEE_ENOTOWNER (AEE_EOFFSET + 0x029) ///< Not an owner authorized to - ///< perform the operation -#define AEE_EINVALIDITEM (AEE_EOFFSET + 0x02A) ///< Current item is invalid, it can be a switch case or a pointer to memory -#define AEE_ENOTALLOWED (AEE_EOFFSET + 0x02B) ///< Not allowed to perform the - ///< operation -#define AEE_EBADHANDLE (AEE_EOFFSET + 0x02C) ///< Invalid/Wrong handle -#define AEE_EINVHANDLE (AEE_EOFFSET + 0x02C) ///< Invalid handle - adding here as its defined in vendor AEEStdErr.h - needed to check valid handle in stub.c -#define AEE_EOUTOFHANDLES (AEE_EOFFSET + 0x02D) ///< Out of handles (Handle list is already full) -//Hole here -#define AEE_ENOMORE (AEE_EOFFSET + 0x02F) ///< No more items available -- - ///< reached end -#define AEE_ECPUEXCEPTION (AEE_EOFFSET + 0x030) ///< A CPU exception occurred -#define AEE_EREADONLY (AEE_EOFFSET + 0x031) ///< Cannot change read-only - ///< object or parameter ( Parameter is in protected mode) -#define AEE_ERPC (AEE_EOFFSET + 0x200) ///< Error due to fastrpc implementation -#define AEE_EFILE (AEE_EOFFSET + 0x201) /// -//#include -#define boolean char -#define FALSE 0 -#define TRUE 1 -#define uint64 unsigned long long -#define uint32 unsigned int -#define NULL 0 - -#ifdef __cplusplus -extern "C" { -#endif - -//Add a weak reference so shared objects do not throw link error -#pragma weak HAP_power_destroy_client - -/** -* Possible error codes returned -*/ -typedef enum { - HAP_POWER_ERR_UNKNOWN = -1, - HAP_POWER_ERR_INVALID_PARAM = -2, - HAP_POWER_ERR_UNSUPPORTED_API = -3 -} HAP_power_error_codes; - -/** Payload for HAP_power_set_mips_bw */ -typedef struct { - boolean set_mips; /**< Set to TRUE to request MIPS */ - unsigned int mipsPerThread; /**< mips requested per thread, to establish a minimal clock frequency per HW thread */ - unsigned int mipsTotal; /**< Total mips requested, to establish total number of MIPS required across all HW threads */ - boolean set_bus_bw; /**< Set to TRUE to request bus_bw */ - uint64 bwBytePerSec; /**< Max bus BW requested (bytes per second) */ - unsigned short busbwUsagePercentage; /**< Percentage of time during which bwBytesPerSec BW is required from the bus (0..100) */ - boolean set_latency; /**< Set to TRUE to set latency */ - int latency; /**< maximum hardware wakeup latency in microseconds. The higher the value, - * the deeper state of sleep that can be entered but the longer it may take - * to awaken. Only values > 0 are supported (1 microsecond is the smallest valid value) */ -} HAP_power_mips_bw_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ - /** Clock frequency match type*/ -typedef enum { - HAP_FREQ_AT_LEAST, /**< Matches at least the specified frequency. */ - HAP_FREQ_AT_MOST, /**< Matches at most the specified frequency. */ - HAP_FREQ_CLOSEST, /**< Closest match to the specified frequency. */ - HAP_FREQ_EXACT, /**< Exact match with the specified frequency. */ - HAP_FREQ_MAX_COUNT /**< Maximum count. */ -} HAP_freq_match_type; -/** - * @} // HAP_power_enums - */ - -/** Configuration for bus bandwidth */ -typedef struct { - boolean set_bus_bw; /**< Set to TRUE to request bus_bw */ - uint64 bwBytePerSec; /**< Max bus BW requested (bytes per second) */ - unsigned short busbwUsagePercentage; /**< Percentage of time during which bwBytesPerSec BW is required from the bus (0..100) */ -} HAP_power_bus_bw; - -/** -* @brief Payload for vapps power request -* vapps core is used for Video post processing -*/ -typedef struct { - boolean set_clk; /**< Set to TRUE to request clock frequency */ - unsigned int clkFreqHz; /**< Clock frequency in Hz */ - HAP_freq_match_type freqMatch; /**< Clock frequency match */ - HAP_power_bus_bw dma_ext; /**< DMA external bus bandwidth */ - HAP_power_bus_bw hcp_ext; /**< HCP external bus bandwidth */ - HAP_power_bus_bw dma_int; /**< DMA internal bus bandwidth */ - HAP_power_bus_bw hcp_int; /**< HCP internal bus bandwidth */ -} HAP_power_vapss_payload; - -/** -* @brief Payload for vapps_v2 power request -* Supported in targets which have split VAPPS core(DMA and HCP) form Hana onwards -*/ -typedef struct { - boolean set_dma_clk; /**< Set to TRUE to reqeust DMA clock frequency */ - boolean set_hcp_clk; /**< Set to TRUE to reqeust HCP clock frequency */ - unsigned int dmaClkFreqHz; /**< DMA Clock frequency in Hz */ - unsigned int hcpClkFreqHz; /**< HCP Clock frequency in Hz */ - HAP_freq_match_type freqMatch; /**< Clock frequency match type */ - HAP_power_bus_bw dma_ext; /**< DMA external bus bandwidth */ - HAP_power_bus_bw hcp_ext; /**< HCP external bus bandwidth */ - HAP_power_bus_bw dma_int; /**< DMA internal bus bandwidth */ - HAP_power_bus_bw hcp_int; /**< HCP internal bus bandwidth */ -} HAP_power_vapss_payload_v2; - -/** Payload for HAP_power_set_HVX */ -typedef struct { - boolean power_up; /**< Set to TRUE to turn on HVX, and FALSE to turn off. */ -} HAP_power_hvx_payload; - -/** -* Payload for HAP_power_set_HMX -* Supported from Lahaina onwards*/ -typedef struct { - boolean power_up; /**< Set to TRUE to turn on HMX, and FALSE to turn off. */ -} HAP_power_hmx_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ -/** Payload for HAP power client classes */ -typedef enum { - HAP_POWER_UNKNOWN_CLIENT_CLASS = 0x00, /**< Unknown client class */ - HAP_POWER_AUDIO_CLIENT_CLASS = 0x01, /**< Audio client class */ - HAP_POWER_VOICE_CLIENT_CLASS = 0x02, /**< Voice client class */ - HAP_POWER_COMPUTE_CLIENT_CLASS = 0x04, /**< Compute client class */ - HAP_POWER_STREAMING_1HVX_CLIENT_CLASS = 0x08, /**< Camera streaming with 1 HVX client class */ - HAP_POWER_STREAMING_2HVX_CLIENT_CLASS = 0x10, /**< Camera streaming with 2 HVX client class */ -} HAP_power_app_type_payload; -/** - * @} // HAP_power_enums - */ - -/** Payload for HAP_power_set_linelock */ -typedef struct { - void* startAddress; /**< Start address of the memory region to be locked. */ - uint32 size; /**< Size (bytes) of the memory region to be locked. Set size - * to 0 to unlock memory. */ - uint32 throttleBlockSize; /**< Block size for throttling, in bytes; - * 0 for no throttling. The region to be locked will be divided into - * blocks of this size for throttling purposes. - * Use for locking larger cache blocks. - * Applicable only when enabling line locking.Only ONE throttled linelock call is supported at this time. - * You can linelock additional regions (without throttling) using HAP_power_set_linelock_nothrottle*/ - uint32 throttlePauseUs; /**< Pause to be applied between locking each block, in microseconds. Applicable only when enabling line locking*/ -} HAP_power_linelock_payload; - -/** Payload for HAP_power_set_linelock_nothrottle */ -typedef struct { - void* startAddress; /**< Start address of the memory region to be locked. */ - uint32 size; /**< Size (bytes) of the memory region to be locked. Set size to 0 - * to unlock memory */ -} HAP_power_linelock_nothrottle_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ -/** Option for dcvs payload */ -typedef enum { - HAP_DCVS_ADJUST_UP_DOWN = 0x1, /**< increase and decrease core/bus clock speed. */ - HAP_DCVS_ADJUST_ONLY_UP = 0x2, /**< restricts DCVS from lowering the clock speed below the requested value . */ -} HAP_power_dcvs_payload_option; -/** - * @} // HAP_power_enums - */ - -/** Payload for HAP_power_set_DCVS */ -typedef struct { - boolean dcvs_enable; /**< Set to TRUE to participate in DCVS, and FALSE otherwise. */ - HAP_power_dcvs_payload_option dcvs_option; /**< Set to one of - * HAP_DCVS_ADJUST_UP_DOWN - Allows for DCVS to adjust up and down. - * HAP_DCVS_ADJUST_ONLY_UP - Allows for DCVS to adjust up only. */ -} HAP_power_dcvs_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ -/** Voltage corners for HAP DCVS V2 interface */ -typedef enum { - HAP_DCVS_VCORNER_DISABLE, - HAP_DCVS_VCORNER_SVS2, - HAP_DCVS_VCORNER_SVS, - HAP_DCVS_VCORNER_SVS_PLUS, - HAP_DCVS_VCORNER_NOM, - HAP_DCVS_VCORNER_NOM_PLUS, - HAP_DCVS_VCORNER_TURBO, - HAP_DCVS_VCORNER_TURBO_PLUS, - HAP_DCVS_VCORNER_MAX = 255, -} HAP_dcvs_voltage_corner_t; -/** - * @} // HAP_power_enums - */ - -#define HAP_DCVS_VCORNER_SVSPLUS HAP_DCVS_VCORNER_SVS_PLUS -#define HAP_DCVS_VCORNER_NOMPLUS HAP_DCVS_VCORNER_NOM_PLUS - -/** DCVS parameters for HAP_power_dcvs_v2_payload */ -typedef struct { - HAP_dcvs_voltage_corner_t target_corner; /**< target voltage corner */ - HAP_dcvs_voltage_corner_t min_corner; /**< minimum voltage corner */ - HAP_dcvs_voltage_corner_t max_corner; /**< maximum voltage corner */ - uint32 param1; /**< reserved */ - uint32 param2; /**< reserved */ - uint32 param3; /**< reserved */ -} HAP_dcvs_params_t; - -/** Core clock parameters for HAP_power_dcvs_v3_payload */ -typedef struct { - HAP_dcvs_voltage_corner_t target_corner; /**< target voltage corner */ - HAP_dcvs_voltage_corner_t min_corner; /**< minimum voltage corner */ - HAP_dcvs_voltage_corner_t max_corner; /**< maximum voltage corner */ - uint32 param1; /**< reserved */ - uint32 param2; /**< reserved */ - uint32 param3; /**< reserved */ -} HAP_core_params_t; - -/** Bus clock parameters for HAP_power_dcvs_v3_payload */ -typedef struct { - HAP_dcvs_voltage_corner_t target_corner; /**< target voltage corner */ - HAP_dcvs_voltage_corner_t min_corner; /**< minimum voltage corner */ - HAP_dcvs_voltage_corner_t max_corner; /**< maximum voltage corner */ - uint32 param1; /**< reserved */ - uint32 param2; /**< reserved */ - uint32 param3; /**< reserved */ -} HAP_bus_params_t; - -/** DCVS v3 parameters for HAP_power_dcvs_v3_payload */ -typedef struct { - uint32 param1; /**< reserved */ - uint32 param2; /**< reserved */ - uint32 param3; /**< reserved */ - uint32 param4; /**< reserved */ - uint32 param5; /**< reserved */ - uint32 param6; /**< reserved */ -} HAP_dcvs_v3_params_t; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ -/** option for dcvs_v2 payload */ -typedef enum { - HAP_DCVS_V2_ADJUST_UP_DOWN = 0x1, /**< Allows for DCVS to adjust up and down. */ - HAP_DCVS_V2_ADJUST_ONLY_UP = 0x2, /**< Allows for DCVS to adjust up only. */ - HAP_DCVS_V2_POWER_SAVER_MODE = 0x4, /**< HAP_DCVS_POWER_SAVER_MODE - Higher thresholds for power efficiency. */ - HAP_DCVS_V2_POWER_SAVER_AGGRESSIVE_MODE = 0x8, /**< HAP_DCVS_POWER_SAVER_AGGRESSIVE_MODE - Higher thresholds for power efficiency with faster ramp down. */ - HAP_DCVS_V2_PERFORMANCE_MODE = 0x10, /**< HAP_DCVS_PERFORMANCE_MODE - Lower thresholds for maximum performance */ - HAP_DCVS_V2_DUTY_CYCLE_MODE = 0x20, /**< HAP_DCVS_DUTY_CYCLE_MODE - only for HVX based clients. - * For streaming class clients: - * > detects periodicity based on HVX usage - * > lowers clocks in the no HVX activity region of each period. - * For compute class clients: - * > Lowers clocks on no HVX activity detects and brings clocks up on detecting HVX activity again. - * > Latency involved in bringing up the clock with be at max 1 to 2 ms. */ - - - -} HAP_power_dcvs_v2_payload_option; -/** - * @} // HAP_power_enums - */ -/** Payload for HAP_power_set_DCVS_v2 */ -typedef struct { - boolean dcvs_enable; /**< Set to TRUE to participate in DCVS, and FALSE otherwise */ - HAP_power_dcvs_v2_payload_option dcvs_option; /**< Set to one of HAP_power_dcvs_v2_payload_option */ - boolean set_latency; /**< TRUE to set latency parameter, otherwise FALSE */ - uint32 latency; /**< sleep latency */ - boolean set_dcvs_params; /**< TRUE to set DCVS params, otherwise FALSE */ - HAP_dcvs_params_t dcvs_params; /**< DCVS parameters */ -} HAP_power_dcvs_v2_payload; - -/** Payload for HAP_power_set_DCVS_v3 */ -typedef struct { - boolean set_dcvs_enable; /**< TRUE to consider DCVS enable/disable and option parameters, otherwise FALSE */ - boolean dcvs_enable; /**< Set to TRUE to participate in DCVS, and FALSE otherwise. */ - HAP_power_dcvs_v2_payload_option dcvs_option; /**< Set to one of HAP_power_dcvs_v2_payload_option */ - boolean set_latency; /**< TRUE to consider latency parameter, otherwise FALSE */ - uint32 latency; /**< sleep latency */ - boolean set_core_params; /**< TRUE to consider core clock params, otherwise FALSE */ - HAP_core_params_t core_params; /**< Core clock parameters */ - boolean set_bus_params; /**< TRUE to consider bus clock params, otherwise FALSE */ - HAP_bus_params_t bus_params; /**< Bus clock parameters */ - boolean set_dcvs_v3_params; /**< TRUE to consider DCVS v3 params, otherwise FALSE */ - HAP_dcvs_v3_params_t dcvs_v3_params; /**< DCVS v3 parameters */ - boolean set_sleep_disable; /**< TRUE to consider sleep disable/enable parameter, otherwise FALSE */ - boolean sleep_disable; /**< TRUE to disable sleep/LPM modes, FALSE to enable */ -} HAP_power_dcvs_v3_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ - /** Type for dcvs update request */ -typedef enum { - HAP_POWER_UPDATE_DCVS = 1, - HAP_POWER_UPDATE_SLEEP_LATENCY, - HAP_POWER_UPDATE_DCVS_PARAMS, -} HAP_power_update_type_t; -/** - * @} // HAP_power_enums - */ -/** Payload for DCVS update */ -typedef struct { - boolean dcvs_enable; /**< TRUE for DCVS enable and FALSE for DCVS disable */ - HAP_power_dcvs_v2_payload_option dcvs_option; /**< Requested DCVS policy in case DCVS enable is TRUE */ -} HAP_power_update_dcvs_t; - -/** Payload for latency update */ -typedef struct { - boolean set_latency; /**< TRUE if sleep latency request has to be considered */ - unsigned int latency; /**< Sleep latency request in micro seconds */ -} HAP_power_update_latency_t; - -/** Payload for DCVS params update */ -typedef struct { - boolean set_dcvs_params; /**< Flag to mark DCVS params structure validity, TRUE for valid DCVS - *params request and FALSE otherwise */ - HAP_dcvs_params_t dcvs_params; /**< Intended DCVS params if set_dcvs_params is set to TRUE */ -} HAP_power_update_dcvs_params_t; - -/** Payload for HAP_power_set_DCVS_v2 */ -typedef struct { - HAP_power_update_type_t update_param; /**< Type for which param to update */ - union { - HAP_power_update_dcvs_t dcvs_payload; - HAP_power_update_latency_t latency_payload; - HAP_power_update_dcvs_params_t dcvs_params_payload; - }; /**< Update payload for DCVS, latency or DCVS params */ -} HAP_power_dcvs_v2_update_payload; - -/** Payload for HAP_power_set_streamer */ -typedef struct { - boolean set_streamer0_clk; /**< Set streamer 0 clock */ - boolean set_streamer1_clk; /**< Set streamer 1 clock */ - unsigned int streamer0_clkFreqHz; /**< Streamer 0 clock frequency */ - unsigned int streamer1_clkFreqHz; /**< Streamer 1 clock frequency */ - HAP_freq_match_type freqMatch; /**< Clock frequency match */ - uint32 param1; /**< Reserved for future streamer parameters */ - uint32 param2; /**< Reserved for future streamer parameters */ - uint32 param3; /**< Reserved for future streamer parameters */ -} HAP_power_streamer_payload; - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ - /** Identifies the HAP power request type */ -typedef enum { - HAP_power_set_mips_bw = 1, /**< Requests for MIPS. Provides - * fine-grained control to set MIPS values. - * Payload is set to HAP_power_payload */ - HAP_power_set_HVX, /**< Requests to enable / disable HVX - * Payload is set to HAP_power_hvx_payload */ - HAP_power_set_apptype, /**< Sets the app_type - * Payload is set to HAP_power_app_type_payload */ - HAP_power_set_linelock, /**< Sets the throttled L2 cache line locking parameters. - * Only one throttled call is supported at this time. Additional - * un-throttled line-locks can be performed using HAP_power_set_linelock_nothrottle - * Payload is set to HAP_power_linelock_payload */ - HAP_power_set_DCVS, /**< Requests to participate / stop participating in DCVS */ - HAP_power_set_linelock_nothrottle, /**< Sets the L2 cache line locking parameters (non-throttled). - * Payload is set to HAP_power_linelock_nothrottle_payload */ - HAP_power_set_DCVS_v2, /**< Requests to participate / stop participating in DCVS_v2 */ - HAP_power_set_vapss, /**< Sets the VAPSS core clock and DDR/IPNOC bandwidth - * Payload is set to HAP_power_vapss_payload */ - HAP_power_set_vapss_v2, /**< Sets the VAPSS core DMA/HCP clocks and DDR/IPNOC bandwidths - * Payload is set to HAP_power_vapss_payload_v2 */ - HAP_power_set_dcvs_v2_update, /**< Updates DCVS params - * Payload is set to HAP_power_dcvs_v2_update_payload */ - HAP_power_set_streamer, /**< Sets the streamer core clocks - * Payload is set to HAP_power_streamer_payload */ - HAP_power_set_DCVS_v3, /**< Updates DCVS params - * Payload is set to HAP_power_dcvs_v3_payload */ - HAP_power_set_HMX, /**< Requests to enable / disable HMX - * Payload is set to HAP_power_hmx_payload */ -} HAP_Power_request_type; -/** - * @} // HAP_power_enums - */ - -/** Data type to change power values on the DSP */ -typedef struct { - HAP_Power_request_type type; /**< Identifies the request type */ - union{ - HAP_power_mips_bw_payload mips_bw; /**< Requests for performance level */ - HAP_power_vapss_payload vapss; /**< Sets the VAPSS core clock and DDR/IPNOC bandwidth */ - HAP_power_vapss_payload_v2 vapss_v2; /**< Sets the VAPSS core clock and DDR/IPNOC bandwidth */ - HAP_power_streamer_payload streamer; /**< Sets the streamer core clocks */ - HAP_power_hvx_payload hvx; /**< Requests to enable / disable HVX */ - HAP_power_app_type_payload apptype; /**< Sets the app_type */ - HAP_power_linelock_payload linelock; /**< Sets the throttled L2 cache linelock parameters. Only one - * throttled linelock is permitted at this time. Additional - * un-throttled linelocks can be performed using linelock_nothrottle */ - HAP_power_dcvs_payload dcvs; /**< Updates DCVS params */ - HAP_power_dcvs_v2_payload dcvs_v2; /**< Updates DCVS_v2 params */ - HAP_power_dcvs_v2_update_payload dcvs_v2_update; /**< Updates DCVS_v2_update params */ - HAP_power_linelock_nothrottle_payload linelock_nothrottle; /**< Sets the un-throttled L2 cache linelock parameters */ - HAP_power_dcvs_v3_payload dcvs_v3; /**< Updates DCVS_v3 params */ - HAP_power_hmx_payload hmx; /**< Requests to turn on / off HMX */ - }; -} HAP_power_request_t; - -/** @defgroup HAP_power_functions HAP POWER functions - * @{ - */ -/** -* Method to set power values from the DSP -* @param[in] context - To identify the power client -* @param[in] request - Request params. -* @retval 0 on success, AEE_EMMPMREGISTER on MMPM client register request failure, -1 on unknown error -*/ -int HAP_power_set(void* context, HAP_power_request_t* request); -/** - * @} // HAP_power_functions - */ - -/** @defgroup HAP_power_enums HAP POWER enums - * @{ - */ - /** Identifies the HAP power response type */ -typedef enum { - HAP_power_get_max_mips = 1, /**< Returns the max mips supported (max_mips) */ - HAP_power_get_max_bus_bw, /**< Returns the max bus bandwidth supported (max_bus_bw) */ - HAP_power_get_client_class, /**< Returns the client class (client_class) */ - HAP_power_get_clk_Freq, /**< Returns the core clock frequency (clkFreqHz) */ - HAP_power_get_aggregateAVSMpps, /**< Returns the aggregate Mpps used by audio and voice (clkFreqHz) */ - HAP_power_get_dcvsEnabled, /**< Returns the dcvs status (enabled / disabled) */ - HAP_power_get_vapss_core_clk_Freq, /**< Returns the VAPSS core clock frequency (clkFreqHz) */ - HAP_power_get_dma_core_clk_Freq, /**< Returns the DMA core clock frequency (clkFreqHz) */ - HAP_power_get_hcp_core_clk_Freq, /**< Returns the HCP core clock frequency (clkFreqHz) */ - HAP_power_get_streamer0_core_clk_Freq, /**< Returns the streamer 0 core clock frequency (clkFreqHz) */ - HAP_power_get_streamer1_core_clk_Freq, /**< Returns the streamer 1 core clock frequency (clkFreqHz) */ -} HAP_Power_response_type; -/** - * @} // HAP_power_enums - */ - -/** Data type to retrieve power values from the DSP */ -typedef struct { - HAP_Power_response_type type; /**< Identifies the type to retrieve. */ - union{ - unsigned int max_mips; /**< Max mips supported */ - uint64 max_bus_bw; /**< Max bus bw supported */ - unsigned int client_class; /**< Current client class */ - unsigned int clkFreqHz; /**< Current core CPU frequency */ - unsigned int aggregateAVSMpps; /**< Aggregate AVS Mpps used by audio and voice */ - boolean dcvsEnabled; /**< Indicates if dcvs is enabled / disabled. */ - }; -} HAP_power_response_t; - -/** @defgroup HAP_power_functions HAP POWER functions - * @{ - */ - -/** -* Method to retrieve power values from the DSP -* @param[in] context - Ignored -* @param[out] response - Response. -*/ -int HAP_power_get(void* context, HAP_power_response_t* response); - -/** -* Method to initialize dcvs v3 structure in request param. It enables -* flags and resets params for all fields in dcvs v3. So, this -* can also be used to remove applied dcvs v3 params and restore -* defaults. -* @param[in] request - Pointer to request params. -*/ -/*static inline void HAP_power_set_dcvs_v3_init(HAP_power_request_t* request) { - memset(request, 0, sizeof(HAP_power_request_t) ); - request->type = HAP_power_set_DCVS_v3; - request->dcvs_v3.set_dcvs_enable = TRUE; - request->dcvs_v3.dcvs_enable = TRUE; - request->dcvs_v3.dcvs_option = HAP_DCVS_V2_POWER_SAVER_MODE; - request->dcvs_v3.set_latency = TRUE; - request->dcvs_v3.latency = 65535; - request->dcvs_v3.set_core_params = TRUE; - request->dcvs_v3.set_bus_params = TRUE; - request->dcvs_v3.set_dcvs_v3_params = TRUE; - request->dcvs_v3.set_sleep_disable = TRUE; - return; -}*/ - -/** -* Method to enable/disable dcvs and set particular dcvs policy. -* @param[in] context - User context. -* @param[in] dcvs_enable - TRUE to enable dcvs, FALSE to disable dcvs. -* @param[in] dcvs_option - To set particular dcvs policy. In case of dcvs disable -* request, this param will be ignored. -* @returns - 0 on success -*/ -/*static inline int HAP_power_set_dcvs_option(void* context, boolean dcvs_enable, - HAP_power_dcvs_v2_payload_option dcvs_option) { - HAP_power_request_t request; - memset(&request, 0, sizeof(HAP_power_request_t) ); - request.type = HAP_power_set_DCVS_v3; - request.dcvs_v3.set_dcvs_enable = TRUE; - request.dcvs_v3.dcvs_enable = dcvs_enable; - if(dcvs_enable) - request.dcvs_v3.dcvs_option = dcvs_option; - return HAP_power_set(context, &request); -}*/ - -/** -* Method to set/reset sleep latency. -* @param[in] context - User context. -* @param[in] latency - Sleep latency value in microseconds, should be > 1. -* Use 65535 max value to reset it to default. -* @returns - 0 on success -*/ -/*static inline int HAP_power_set_sleep_latency(void* context, uint32 latency) { - HAP_power_request_t request; - memset(&request, 0, sizeof(HAP_power_request_t) ); - request.type = HAP_power_set_DCVS_v3; - request.dcvs_v3.set_latency = TRUE; - request.dcvs_v3.latency = latency; - return HAP_power_set(context, &request); -}*/ - -/** -* Method to set/reset DSP core clock voltage corners. -* @param[in] context - User context. -* @param[in] target_corner - Target voltage corner. -* @param[in] min_corner - Minimum voltage corner. -* @param[in] max_corner - Maximum voltage corner. -* @returns - 0 on success -*/ -/*static inline int HAP_power_set_core_corner(void* context, uint32 target_corner, - uint32 min_corner, uint32 max_corner) { - HAP_power_request_t request; - memset(&request, 0, sizeof(HAP_power_request_t) ); - request.type = HAP_power_set_DCVS_v3; - request.dcvs_v3.set_core_params = TRUE; - request.dcvs_v3.core_params.min_corner = (HAP_dcvs_voltage_corner_t) (min_corner); - request.dcvs_v3.core_params.max_corner = (HAP_dcvs_voltage_corner_t) (max_corner); - request.dcvs_v3.core_params.target_corner = (HAP_dcvs_voltage_corner_t) (target_corner); - return HAP_power_set(context, &request); -}*/ - -/** -* Method to set/reset bus clock voltage corners. -* @param[in] context - User context. -* @param[in] target_corner - Target voltage corner. -* @param[in] min_corner - Minimum voltage corner. -* @param[in] max_corner - Maximum voltage corner. -* @returns - 0 on success -*/ -/*static inline int HAP_power_set_bus_corner(void* context, uint32 target_corner, - uint32 min_corner, uint32 max_corner) { - HAP_power_request_t request; - memset(&request, 0, sizeof(HAP_power_request_t) ); - request.type = HAP_power_set_DCVS_v3; - request.dcvs_v3.set_bus_params = TRUE; - request.dcvs_v3.bus_params.min_corner = (HAP_dcvs_voltage_corner_t) (min_corner); - request.dcvs_v3.bus_params.max_corner = (HAP_dcvs_voltage_corner_t) (max_corner); - request.dcvs_v3.bus_params.target_corner = (HAP_dcvs_voltage_corner_t) (target_corner); - return HAP_power_set(context, &request); -}*/ - -/** -* Method to disable/enable all low power modes. -* @param[in] context - User context. -* @param[in] sleep_disable - TRUE to disable all low power modes. -* FALSE to re-enable all low power modes. -* @returns - 0 on success -*/ -/*static inline int HAP_power_set_sleep_mode(void* context, boolean sleep_disable) { - HAP_power_request_t request; - memset(&request, 0, sizeof(HAP_power_request_t) ); - request.type = HAP_power_set_DCVS_v3; - request.dcvs_v3.set_sleep_disable = TRUE; - request.dcvs_v3.sleep_disable = sleep_disable; - return HAP_power_set(context, &request); -}*/ - - -/** -* This API is deprecated and might generate undesired results. -* Please use the HAP_power_get() and HAP_power_set() APIs instead. -* Requests a performance level by percentage for clock speed -* and bus speed. Passing 0 for any parameter results in no -* request being issued for that particular attribute. -* @param[in] clock - percentage of target's maximum clock speed -* @param[in] bus - percentage of target's maximum bus speed -* @param[in] latency - maximum hardware wake up latency in microseconds. The -* higher the value the deeper state of sleep -* that can be entered but the longer it may -* take to awaken. -* @retval 0 on success -* @par Comments : Performance metrics vary from target to target so the -* intent of this API is to allow callers to set a relative -* performance level to achieve the desired balance between -* performance and power saving. -*/ -int HAP_power_request(int clock, int bus, int latency); - -/** -* This API is deprecated and might generate undesired results. -* Please use the HAP_power_get() and HAP_power_set() APIs instead. -* Requests a performance level by absolute values. Passing 0 -* for any parameter results in no request being issued for that -* particular attribute. -* @param[in] clock - speed in MHz -* @param[in] bus - bus speed in MHz -* @param[in] latency - maximum hardware wakeup latency in microseconds. The -* higher the value the deeper state of -* sleep that can be entered but the -* longer it may take to awaken. -* @retval 0 on success -* @par Comments : This API allows callers who are aware of their target -* specific capabilities to set them explicitly. -*/ -int HAP_power_request_abs(int clock, int bus, int latency); - -/** -* This API is deprecated and might generate undesired results. -* Please use the HAP_power_get() and HAP_power_set() APIs instead. -* queries the target for its clock and bus speed capabilities -* @param[out] clock_max - maximum clock speed supported in MHz -* @param[out] bus_max - maximum bus speed supported in MHz -* @retval 0 on success -*/ -int HAP_power_get_max_speed(int* clock_max, int* bus_max); - -/** -* This API is deprecated and might generate undesired results. -* Please use the HAP_power_get() and HAP_power_set() APIs instead. -* Upvote for HVX power -* @retval 0 on success -*/ -int HVX_power_request(void); - -/** -* This API is deprecated and might generate undesired results. -* Please use the HAP_power_get() and HAP_power_set() APIs instead. -* Downvote for HVX power -* @retval 0 on success -*/ -int HVX_power_release(void); - -/** -* Method to destroy clients created through HAP_power_set -* @param[in] context - To uniquely identify the client -* @retval 0 on success, AEE_ENOSUCHCLIENT on Invalid context, -1 on unknown error -* @brief DO NOT call this API directly, use HAP_power_destroy instead. -*/ -int HAP_power_destroy_client(void *context); - -/** -* @param[in] client - To uniquely identify the client context. -* @retval 0 on success, AEE_EUNSUPPORTEDAPI if the API is not supported on the DSP image, AEE_ENOSUCHCLIENT on Invalid context, -1 on unknown error -* @brief Method to destroy clients created through HAP_power_set, wrapper to HAP_power_destroy_client API -*/ -static inline int HAP_power_destroy(void *client){ - if(0 != HAP_power_destroy_client) - return HAP_power_destroy_client(client); - return AEE_EUNSUPPORTEDAPI; -} - -/** -* Method to create user client context -* @retval context for client -*/ -//static inline void* HAP_utils_create_context(void) { - /* - * Allocate 1 byte of memory for a unique context identifier - * Clients can also allocate memory and use it as unique context identifier - */ -// return malloc(1); -//} - -/** -* Method to destroy user client context -* @param context of client -*/ -/*static inline void HAP_utils_destroy_context(void* context) { - free(context); -}*/ - -/** - * @} // HAP_power_functions - */ -#ifdef __cplusplus -} -#endif -#endif //_HAP_POWER_H - diff --git a/tinygrad/extra/dsp/include/adsprpc_shared.h b/tinygrad/extra/dsp/include/adsprpc_shared.h deleted file mode 100644 index e2c135ed..00000000 --- a/tinygrad/extra/dsp/include/adsprpc_shared.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef ADSPRPC_SHARED_H -#define ADSPRPC_SHARED_H - -#include -#include -#include -#include - -#define FASTRPC_IOCTL_INVOKE _IOWR('R', 1, struct fastrpc_ioctl_invoke) -#define FASTRPC_IOCTL_MMAP _IOWR('R', 2, struct fastrpc_ioctl_mmap) -#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 3, struct fastrpc_ioctl_munmap) -#define FASTRPC_IOCTL_MMAP_64 _IOWR('R', 14, struct fastrpc_ioctl_mmap_64) -#define FASTRPC_IOCTL_MUNMAP_64 _IOWR('R', 15, struct fastrpc_ioctl_munmap_64) -#define FASTRPC_IOCTL_INVOKE_FD _IOWR('R', 4, struct fastrpc_ioctl_invoke_fd) -#define FASTRPC_IOCTL_SETMODE _IOWR('R', 5, uint32_t) -#define FASTRPC_IOCTL_INIT _IOWR('R', 6, struct fastrpc_ioctl_init) -#define FASTRPC_IOCTL_INVOKE_ATTRS \ - _IOWR('R', 7, struct fastrpc_ioctl_invoke_attrs) -#define FASTRPC_IOCTL_GETINFO _IOWR('R', 8, uint32_t) -#define FASTRPC_IOCTL_GETPERF _IOWR('R', 9, struct fastrpc_ioctl_perf) -#define FASTRPC_IOCTL_INIT_ATTRS _IOWR('R', 10, struct fastrpc_ioctl_init_attrs) -#define FASTRPC_IOCTL_INVOKE_CRC _IOWR('R', 11, struct fastrpc_ioctl_invoke_crc) -#define FASTRPC_IOCTL_CONTROL _IOWR('R', 12, struct fastrpc_ioctl_control) -#define FASTRPC_IOCTL_MUNMAP_FD _IOWR('R', 13, struct fastrpc_ioctl_munmap_fd) - -#define FASTRPC_GLINK_GUID "fastrpcglink-apps-dsp" -#define FASTRPC_SMD_GUID "fastrpcsmd-apps-dsp" -#define DEVICE_NAME "adsprpc-smd" - -/* Set for buffers that have no virtual mapping in userspace */ -#define FASTRPC_ATTR_NOVA 0x1 - -/* Set for buffers that are NOT dma coherent */ -#define FASTRPC_ATTR_NON_COHERENT 0x2 - -/* Set for buffers that are dma coherent */ -#define FASTRPC_ATTR_COHERENT 0x4 - -/* Fastrpc attribute for keeping the map persistent */ -#define FASTRPC_ATTR_KEEP_MAP 0x8 - -/* Fastrpc attribute for no map */ -#define FASTRPC_ATTR_NOMAP (16) - -/* Driver should operate in parallel with the co-processor */ -#define FASTRPC_MODE_PARALLEL 0 - -/* Driver should operate in serial mode with the co-processor */ -#define FASTRPC_MODE_SERIAL 1 - -/* Driver should operate in profile mode with the co-processor */ -#define FASTRPC_MODE_PROFILE 2 - -/* Set FastRPC session ID to 1 */ -#define FASTRPC_MODE_SESSION 4 - -/* INIT a new process or attach to guestos */ -#define FASTRPC_INIT_ATTACH 0 -#define FASTRPC_INIT_CREATE 1 -#define FASTRPC_INIT_CREATE_STATIC 2 -#define FASTRPC_INIT_ATTACH_SENSORS 3 - -/* Retrives number of input buffers from the scalars parameter */ -#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) - -/* Retrives number of output buffers from the scalars parameter */ -#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) - -/* Retrives number of input handles from the scalars parameter */ -#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) - -/* Retrives number of output handles from the scalars parameter */ -#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) - -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) +\ - REMOTE_SCALARS_OUTBUFS(sc) +\ - REMOTE_SCALARS_INHANDLES(sc) +\ - REMOTE_SCALARS_OUTHANDLES(sc)) - -#define REMOTE_SCALARS_MAKEX(attr, method, in, out, oin, oout) \ - ((((uint32_t) (attr) & 0x7) << 29) | \ - (((uint32_t) (method) & 0x1f) << 24) | \ - (((uint32_t) (in) & 0xff) << 16) | \ - (((uint32_t) (out) & 0xff) << 8) | \ - (((uint32_t) (oin) & 0x0f) << 4) | \ - ((uint32_t) (oout) & 0x0f)) - -#define REMOTE_SCALARS_MAKE(method, in, out) \ - REMOTE_SCALARS_MAKEX(0, method, in, out, 0, 0) - - -#ifndef VERIFY_PRINT_ERROR -#define VERIFY_EPRINTF(format, args) (void)0 -#endif - -#ifndef VERIFY_PRINT_INFO -#define VERIFY_IPRINTF(args) (void)0 -#endif - -#ifndef VERIFY -#define __STR__(x) #x ":" -#define __TOSTR__(x) __STR__(x) -#define __FILE_LINE__ __FILE__ ":" __TOSTR__(__LINE__) - -#define VERIFY(err, val) \ -do {\ - VERIFY_IPRINTF(__FILE_LINE__"info: calling: " #val "\n");\ - if ((val) == 0) {\ - (err) = (err) == 0 ? -1 : (err);\ - VERIFY_EPRINTF(__FILE_LINE__"error: %d: " #val "\n", (err));\ - } else {\ - VERIFY_IPRINTF(__FILE_LINE__"info: passed: " #val "\n");\ - } \ -} while (0) -#endif - -#define remote_arg64_t union remote_arg64 - -struct remote_buf64 { - uint64_t pv; - uint64_t len; -}; - -struct remote_dma_handle64 { - int fd; - uint32_t offset; - uint32_t len; -}; - -union remote_arg64 { - struct remote_buf64 buf; - struct remote_dma_handle64 dma; - uint32_t h; -}; - -#define remote_arg_t union remote_arg - -struct remote_buf { - void *pv; /* buffer pointer */ - size_t len; /* length of buffer */ -}; - -struct remote_dma_handle { - int fd; - uint32_t offset; -}; - -union remote_arg { - struct remote_buf buf; /* buffer info */ - struct remote_dma_handle dma; - uint32_t h; /* remote handle */ -}; - -struct fastrpc_ioctl_invoke { - uint32_t handle; /* remote handle */ - uint32_t sc; /* scalars describing the data */ - remote_arg_t *pra; /* remote arguments list */ -}; - -struct fastrpc_ioctl_invoke_fd { - struct fastrpc_ioctl_invoke inv; - int *fds; /* fd list */ -}; - -struct fastrpc_ioctl_invoke_attrs { - struct fastrpc_ioctl_invoke inv; - int *fds; /* fd list */ - unsigned int *attrs; /* attribute list */ -}; - -struct fastrpc_ioctl_invoke_crc { - struct fastrpc_ioctl_invoke inv; - int *fds; /* fd list */ - unsigned int *attrs; /* attribute list */ - unsigned int *crc; -}; - -struct fastrpc_ioctl_init { - uint32_t flags; /* one of FASTRPC_INIT_* macros */ - uintptr_t file; /* pointer to elf file */ - uint32_t filelen; /* elf file length */ - int32_t filefd; /* ION fd for the file */ - uintptr_t mem; /* mem for the PD */ - uint32_t memlen; /* mem length */ - int32_t memfd; /* ION fd for the mem */ -}; - -struct fastrpc_ioctl_init_attrs { - struct fastrpc_ioctl_init init; - int attrs; - unsigned int siglen; -}; - -struct fastrpc_ioctl_munmap { - uintptr_t vaddrout; /* address to unmap */ - size_t size; /* size */ -}; - -struct fastrpc_ioctl_munmap_64 { - uint64_t vaddrout; /* address to unmap */ - size_t size; /* size */ -}; - -struct fastrpc_ioctl_mmap { - int fd; /* ion fd */ - uint32_t flags; /* flags for dsp to map with */ - uintptr_t vaddrin; /* optional virtual address */ - size_t size; /* size */ - uintptr_t vaddrout; /* dsps virtual address */ -}; - -struct fastrpc_ioctl_mmap_64 { - int fd; /* ion fd */ - uint32_t flags; /* flags for dsp to map with */ - uint64_t vaddrin; /* optional virtual address */ - size_t size; /* size */ - uint64_t vaddrout; /* dsps virtual address */ -}; - -struct fastrpc_ioctl_munmap_fd { - int fd; /* fd */ - uint32_t flags; /* control flags */ - uintptr_t va; /* va */ - ssize_t len; /* length */ -}; - -struct fastrpc_ioctl_perf { /* kernel performance data */ - uintptr_t data; - uint32_t numkeys; - uintptr_t keys; -}; - -#define FASTRPC_CONTROL_LATENCY (1) -struct fastrpc_ctrl_latency { - uint32_t enable; /* latency control enable */ - uint32_t level; /* level of control */ -}; - -#define FASTRPC_CONTROL_SMMU (2) -struct fastrpc_ctrl_smmu { - uint32_t sharedcb; -}; - -#define FASTRPC_CONTROL_KALLOC (3) -struct fastrpc_ctrl_kalloc { - uint32_t kalloc_support; /* Remote memory allocation from kernel */ -}; - -struct fastrpc_ioctl_control { - uint32_t req; - union { - struct fastrpc_ctrl_latency lp; - struct fastrpc_ctrl_smmu smmu; - struct fastrpc_ctrl_kalloc kalloc; - }; -}; - -struct smq_null_invoke { - uint64_t ctx; /* invoke caller context */ - uint32_t handle; /* handle to invoke */ - uint32_t sc; /* scalars structure describing the data */ -}; - -struct smq_phy_page { - uint64_t addr; /* physical address */ - uint64_t size; /* size of contiguous region */ -}; - -struct smq_invoke_buf { - int num; /* number of contiguous regions */ - int pgidx; /* index to start of contiguous region */ -}; - -struct smq_invoke { - struct smq_null_invoke header; - struct smq_phy_page page; /* remote arg and list of pages address */ -}; - -struct smq_msg { - uint32_t pid; /* process group id */ - uint32_t tid; /* thread id */ - struct smq_invoke invoke; -}; - -struct smq_invoke_rsp { - uint64_t ctx; /* invoke caller context */ - int retval; /* invoke return value */ -}; - -static inline struct smq_invoke_buf *smq_invoke_buf_start(remote_arg64_t *pra, - uint32_t sc) -{ - unsigned int len = REMOTE_SCALARS_LENGTH(sc); - - return (struct smq_invoke_buf *)(&pra[len]); -} - -static inline struct smq_phy_page *smq_phy_page_start(uint32_t sc, - struct smq_invoke_buf *buf) -{ - unsigned int nTotal = REMOTE_SCALARS_LENGTH(sc); - - return (struct smq_phy_page *)(&buf[nTotal]); -} - -#endif diff --git a/tinygrad/extra/dsp/include/apps_std.h b/tinygrad/extra/dsp/include/apps_std.h deleted file mode 100644 index e68a24ba..00000000 --- a/tinygrad/extra/dsp/include/apps_std.h +++ /dev/null @@ -1,208 +0,0 @@ -/** - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of The Linux Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _APPS_STD_H -#define _APPS_STD_H -#include "AEEStdDef.h" -#ifndef __QAIC_HEADER -#define __QAIC_HEADER(ff) ff -#endif //__QAIC_HEADER - -#ifndef __QAIC_HEADER_EXPORT -#define __QAIC_HEADER_EXPORT -#endif // __QAIC_HEADER_EXPORT - -#ifndef __QAIC_HEADER_ATTRIBUTE -#define __QAIC_HEADER_ATTRIBUTE -#endif // __QAIC_HEADER_ATTRIBUTE - -#ifndef __QAIC_IMPL -#define __QAIC_IMPL(ff) ff -#endif //__QAIC_IMPL - -#ifndef __QAIC_IMPL_EXPORT -#define __QAIC_IMPL_EXPORT -#endif // __QAIC_IMPL_EXPORT - -#ifndef __QAIC_IMPL_ATTRIBUTE -#define __QAIC_IMPL_ATTRIBUTE -#endif // __QAIC_IMPL_ATTRIBUTE -#ifdef __cplusplus -extern "C" { -#endif -#if !defined(__QAIC_STRING1_OBJECT_DEFINED__) && !defined(__STRING1_OBJECT__) -#define __QAIC_STRING1_OBJECT_DEFINED__ -#define __STRING1_OBJECT__ -typedef struct _cstring1_s { - char* data; - int dataLen; -} _cstring1_t; - -#endif /* __QAIC_STRING1_OBJECT_DEFINED__ */ -/** - * standard library functions remoted from the apps to the dsp - */ -typedef int apps_std_FILE; -enum apps_std_SEEK { - APPS_STD_SEEK_SET, - APPS_STD_SEEK_CUR, - APPS_STD_SEEK_END, - _32BIT_PLACEHOLDER_apps_std_SEEK = 0x7fffffff -}; -typedef enum apps_std_SEEK apps_std_SEEK; -typedef struct apps_std_DIR apps_std_DIR; -struct apps_std_DIR { - uint64 handle; -}; -typedef struct apps_std_DIRENT apps_std_DIRENT; -struct apps_std_DIRENT { - int ino; - char name[255]; -}; -typedef struct apps_std_STAT apps_std_STAT; -struct apps_std_STAT { - uint64 tsz; - uint64 dev; - uint64 ino; - uint32 mode; - uint32 nlink; - uint64 rdev; - uint64 size; - int64 atime; - int64 atimensec; - int64 mtime; - int64 mtimensec; - int64 ctime; - int64 ctimensec; -}; -/** - * @retval, if operation fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fopen)(const char* name, const char* mode, apps_std_FILE* psout) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_freopen)(apps_std_FILE sin, const char* name, const char* mode, apps_std_FILE* psout) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fflush)(apps_std_FILE sin) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fclose)(apps_std_FILE sin) __QAIC_HEADER_ATTRIBUTE; -/** - * @param, bEOF, if read or write bytes <= bufLen bytes then feof() is called - * and the result is returned in bEOF, otherwise bEOF is set to 0. - * @retval, if read or write return 0 for non zero length buffers, ferror is checked - * and a non zero value is returned in case of error with no rout parameters - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fread)(apps_std_FILE sin, byte* buf, int bufLen, int* bytesRead, int* bEOF) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fwrite)(apps_std_FILE sin, const byte* buf, int bufLen, int* bytesWritten, int* bEOF) __QAIC_HEADER_ATTRIBUTE; -/** - * @param, pos, this buffer is filled up to MIN(posLen, sizeof(fpos_t)) - * @param, posLenReq, returns sizeof(fpos_t) - * @retval, if operation fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fgetpos)(apps_std_FILE sin, byte* pos, int posLen, int* posLenReq) __QAIC_HEADER_ATTRIBUTE; -/** - * @param, if size of pos doesn't match the system size an error is returned. - * fgetpos can be used to query the size of fpos_t - * @retval, if operation fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fsetpos)(apps_std_FILE sin, const byte* pos, int posLen) __QAIC_HEADER_ATTRIBUTE; -/** - * @retval, if operation fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_ftell)(apps_std_FILE sin, int* pos) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fseek)(apps_std_FILE sin, int offset, apps_std_SEEK whence) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_flen)(apps_std_FILE sin, uint64* len) __QAIC_HEADER_ATTRIBUTE; -/** - * @retval, only fails if transport fails - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_rewind)(apps_std_FILE sin) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_feof)(apps_std_FILE sin, int* bEOF) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_ferror)(apps_std_FILE sin, int* err) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_clearerr)(apps_std_FILE sin) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_print_string)(const char* str) __QAIC_HEADER_ATTRIBUTE; -/** - * @param val, must contain space for NULL - * @param valLenReq, length required with NULL - * @retval, if fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_getenv)(const char* name, char* val, int valLen, int* valLenReq) __QAIC_HEADER_ATTRIBUTE; -/** - * @retval, if fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_setenv)(const char* name, const char* val, int override) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_unsetenv)(const char* name) __QAIC_HEADER_ATTRIBUTE; -/** - * This function will try to open a file given directories in envvarname separated by - * delim. - * so given environment variable FOO_PATH=/foo;/bar - * fopen_wth_env("FOO_PATH", ";", "path/to/file", "rw", &out); - * will try to open /foo/path/to/file, /bar/path/to/file - * if the variable is unset, it will open the file directly - * - * @param envvarname, name of the environment variable containing the path - * @param delim, delimiator string, such as ";" - * @param name, name of the file - * @param mode, mode - * @param psout, output handle - * @retval, 0 on success errno or -1 on failure - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fopen_with_env)(const char* envvarname, const char* delim, const char* name, const char* mode, apps_std_FILE* psout) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fgets)(apps_std_FILE sin, byte* buf, int bufLen, int* bEOF) __QAIC_HEADER_ATTRIBUTE; -/** - * This method will return the paths that are searched when looking for a file. - * The paths are defined by the environment variable (separated by delimiters) - * that is passed to the method. - * - * @param envvarname, name of the environment variable containing the path - * @param delim, delimiator string, such as ";" - * @param name, name of the file - * @param paths, Search paths - * @param numPaths, Actual number of paths found - * @param maxPathLen, The max path length - * @retval, 0 on success errno or -1 on failure - * - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_get_search_paths_with_env)(const char* envvarname, const char* delim, _cstring1_t* paths, int pathsLen, uint32* numPaths, uint16* maxPathLen) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fileExists)(const char* path, boolean* exists) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fsync)(apps_std_FILE sin) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fremove)(const char* name) __QAIC_HEADER_ATTRIBUTE; -/** - * This function decrypts the file using the provided open file descriptor, closes the - * original descriptor and return a new file descriptor. - * @retval, if operation fails errno is returned - */ -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_fdopen_decrypt)(apps_std_FILE sin, apps_std_FILE* psout) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_opendir)(const char* name, apps_std_DIR* dir) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_closedir)(const apps_std_DIR* dir) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_readdir)(const apps_std_DIR* dir, apps_std_DIRENT* dirent, int* bEOF) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_mkdir)(const char* name, int mode) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_rmdir)(const char* name) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_stat)(const char* name, apps_std_STAT* stat) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_ftrunc)(apps_std_FILE sin, int offset) __QAIC_HEADER_ATTRIBUTE; -__QAIC_HEADER_EXPORT int __QAIC_HEADER(apps_std_frename)(const char* oldname, const char* newname) __QAIC_HEADER_ATTRIBUTE; -#ifdef __cplusplus -} -#endif -#endif //_APPS_STD_H diff --git a/tinygrad/extra/dsp/include/ion.h b/tinygrad/extra/dsp/include/ion.h deleted file mode 100644 index 4aa11c53..00000000 --- a/tinygrad/extra/dsp/include/ion.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * drivers/staging/android/uapi/ion.h - * - * Copyright (C) 2011 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _UAPI_LINUX_ION_H -#define _UAPI_LINUX_ION_H - -#include -#include -#include - -typedef int ion_user_handle_t; - -/** - * enum ion_heap_types - list of all possible types of heaps - * @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc - * @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc - * @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved - * carveout heap, allocations are physically - * contiguous - * @ION_HEAP_TYPE_DMA: memory allocated via DMA API - * @ION_NUM_HEAPS: helper for iterating over heaps, a bit mask - * is used to identify the heaps, so only 32 - * total heap types are supported - */ -enum ion_heap_type { - ION_HEAP_TYPE_SYSTEM, - ION_HEAP_TYPE_SYSTEM_CONTIG, - ION_HEAP_TYPE_CARVEOUT, - ION_HEAP_TYPE_CHUNK, - ION_HEAP_TYPE_DMA, - ION_HEAP_TYPE_CUSTOM, /* - * must be last so device specific heaps always - * are at the end of this enum - */ - ION_NUM_HEAPS = 16, -}; - -#define ION_HEAP_SYSTEM_MASK ((1 << ION_HEAP_TYPE_SYSTEM)) -#define ION_HEAP_SYSTEM_CONTIG_MASK ((1 << ION_HEAP_TYPE_SYSTEM_CONTIG)) -#define ION_HEAP_CARVEOUT_MASK ((1 << ION_HEAP_TYPE_CARVEOUT)) -#define ION_HEAP_TYPE_DMA_MASK ((1 << ION_HEAP_TYPE_DMA)) - -#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8) - -/** - * allocation flags - the lower 16 bits are used by core ion, the upper 16 - * bits are reserved for use by the heaps themselves. - */ -#define ION_FLAG_CACHED 1 /* - * mappings of this buffer should be - * cached, ion will do cache - * maintenance when the buffer is - * mapped for dma - */ -#define ION_FLAG_CACHED_NEEDS_SYNC 2 /* - * mappings of this buffer will created - * at mmap time, if this is set - * caches must be managed - * manually - */ - -/** - * DOC: Ion Userspace API - * - * create a client by opening /dev/ion - * most operations handled via following ioctls - * - */ - -/** - * struct ion_allocation_data - metadata passed from userspace for allocations - * @len: size of the allocation - * @align: required alignment of the allocation - * @heap_id_mask: mask of heap ids to allocate from - * @flags: flags passed to heap - * @handle: pointer that will be populated with a cookie to use to - * refer to this allocation - * - * Provided by userspace as an argument to the ioctl - */ -struct ion_allocation_data { - size_t len; - size_t align; - unsigned int heap_id_mask; - unsigned int flags; - ion_user_handle_t handle; -}; - -/** - * struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair - * @handle: a handle - * @fd: a file descriptor representing that handle - * - * For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with - * the handle returned from ion alloc, and the kernel returns the file - * descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace - * provides the file descriptor and the kernel returns the handle. - */ -struct ion_fd_data { - ion_user_handle_t handle; - int fd; -}; - -/** - * struct ion_handle_data - a handle passed to/from the kernel - * @handle: a handle - */ -struct ion_handle_data { - ion_user_handle_t handle; -}; - -/** - * struct ion_custom_data - metadata passed to/from userspace for a custom ioctl - * @cmd: the custom ioctl function to call - * @arg: additional data to pass to the custom ioctl, typically a user - * pointer to a predefined structure - * - * This works just like the regular cmd and arg fields of an ioctl. - */ -struct ion_custom_data { - unsigned int cmd; - unsigned long arg; -}; - -#define ION_IOC_MAGIC 'I' - -/** - * DOC: ION_IOC_ALLOC - allocate memory - * - * Takes an ion_allocation_data struct and returns it with the handle field - * populated with the opaque handle for the allocation. - */ -#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \ - struct ion_allocation_data) - -/** - * DOC: ION_IOC_FREE - free memory - * - * Takes an ion_handle_data struct and frees the handle. - */ -#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) - -/** - * DOC: ION_IOC_MAP - get a file descriptor to mmap - * - * Takes an ion_fd_data struct with the handle field populated with a valid - * opaque handle. Returns the struct with the fd field set to a file - * descriptor open in the current address space. This file descriptor - * can then be used as an argument to mmap. - */ -#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) - -/** - * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation - * - * Takes an ion_fd_data struct with the handle field populated with a valid - * opaque handle. Returns the struct with the fd field set to a file - * descriptor open in the current address space. This file descriptor - * can then be passed to another process. The corresponding opaque handle can - * be retrieved via ION_IOC_IMPORT. - */ -#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) - -/** - * DOC: ION_IOC_IMPORT - imports a shared file descriptor - * - * Takes an ion_fd_data struct with the fd field populated with a valid file - * descriptor obtained from ION_IOC_SHARE and returns the struct with the handle - * filed set to the corresponding opaque handle. - */ -#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) - -/** - * DOC: ION_IOC_SYNC - syncs a shared file descriptors to memory - * - * Deprecated in favor of using the dma_buf api's correctly (syncing - * will happen automatically when the buffer is mapped to a device). - * If necessary should be used after touching a cached buffer from the cpu, - * this will make the buffer in memory coherent. - */ -#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data) - -/** - * DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl - * - * Takes the argument of the architecture specific ioctl to call and - * passes appropriate userdata for that ioctl - */ -#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) - -#endif /* _UAPI_LINUX_ION_H */ diff --git a/tinygrad/extra/dsp/include/msm_ion.h b/tinygrad/extra/dsp/include/msm_ion.h deleted file mode 100644 index ec4a9b7c..00000000 --- a/tinygrad/extra/dsp/include/msm_ion.h +++ /dev/null @@ -1,211 +0,0 @@ -#ifndef _UAPI_MSM_ION_H -#define _UAPI_MSM_ION_H - -#include "ion.h" - -enum msm_ion_heap_types { - ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, - ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, - ION_HEAP_TYPE_SYSTEM_SECURE, - ION_HEAP_TYPE_HYP_CMA, - /* - * if you add a heap type here you should also add it to - * heap_types_info[] in msm_ion.c - */ -}; - -/** - * These are the only ids that should be used for Ion heap ids. - * The ids listed are the order in which allocation will be attempted - * if specified. Don't swap the order of heap ids unless you know what - * you are doing! - * Id's are spaced by purpose to allow new Id's to be inserted in-between (for - * possible fallbacks) - */ - -enum ion_heap_ids { - INVALID_HEAP_ID = -1, - ION_CP_MM_HEAP_ID = 8, - ION_SECURE_HEAP_ID = 9, - ION_SECURE_DISPLAY_HEAP_ID = 10, - ION_CP_MFC_HEAP_ID = 12, - ION_CP_WB_HEAP_ID = 16, /* 8660 only */ - ION_CAMERA_HEAP_ID = 20, /* 8660 only */ - ION_SYSTEM_CONTIG_HEAP_ID = 21, - ION_ADSP_HEAP_ID = 22, - ION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */ - ION_SF_HEAP_ID = 24, - ION_SYSTEM_HEAP_ID = 25, - ION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */ - ION_QSECOM_HEAP_ID = 27, - ION_AUDIO_HEAP_ID = 28, - - ION_MM_FIRMWARE_HEAP_ID = 29, - - ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */ -}; - -/* - * The IOMMU heap is deprecated! Here are some aliases for backwards - * compatibility: - */ -#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID -#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM - -enum ion_fixed_position { - NOT_FIXED, - FIXED_LOW, - FIXED_MIDDLE, - FIXED_HIGH, -}; - -enum cp_mem_usage { - VIDEO_BITSTREAM = 0x1, - VIDEO_PIXEL = 0x2, - VIDEO_NONPIXEL = 0x3, - DISPLAY_SECURE_CP_USAGE = 0x4, - CAMERA_SECURE_CP_USAGE = 0x5, - MAX_USAGE = 0x6, - UNKNOWN = 0x7FFFFFFF, -}; - -/** - * Flags to be used when allocating from the secure heap for - * content protection - */ -#define ION_FLAG_CP_TOUCH (1 << 17) -#define ION_FLAG_CP_BITSTREAM (1 << 18) -#define ION_FLAG_CP_PIXEL (1 << 19) -#define ION_FLAG_CP_NON_PIXEL (1 << 20) -#define ION_FLAG_CP_CAMERA (1 << 21) -#define ION_FLAG_CP_HLOS (1 << 22) -#define ION_FLAG_CP_HLOS_FREE (1 << 23) -#define ION_FLAG_CP_SEC_DISPLAY (1 << 25) -#define ION_FLAG_CP_APP (1 << 26) - -/** - * Flag to allow non continguous allocation of memory from secure - * heap - */ -#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24) - -/** - * Flag to use when allocating to indicate that a heap is secure. - */ -#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) - -/** - * Flag for clients to force contiguous memort allocation - * - * Use of this flag is carefully monitored! - */ -#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) - -/* - * Used in conjunction with heap which pool memory to force an allocation - * to come from the page allocator directly instead of from the pool allocation - */ -#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) - - -#define ION_FLAG_POOL_PREFETCH (1 << 27) - -/** -* Deprecated! Please use the corresponding ION_FLAG_* -*/ -#define ION_SECURE ION_FLAG_SECURE -#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS - -/** - * Macro should be used with ion_heap_ids defined above. - */ -#define ION_HEAP(bit) (1 << (bit)) - -#define ION_ADSP_HEAP_NAME "adsp" -#define ION_SYSTEM_HEAP_NAME "system" -#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME -#define ION_KMALLOC_HEAP_NAME "kmalloc" -#define ION_AUDIO_HEAP_NAME "audio" -#define ION_SF_HEAP_NAME "sf" -#define ION_MM_HEAP_NAME "mm" -#define ION_CAMERA_HEAP_NAME "camera_preview" -#define ION_IOMMU_HEAP_NAME "iommu" -#define ION_MFC_HEAP_NAME "mfc" -#define ION_WB_HEAP_NAME "wb" -#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" -#define ION_PIL1_HEAP_NAME "pil_1" -#define ION_PIL2_HEAP_NAME "pil_2" -#define ION_QSECOM_HEAP_NAME "qsecom" -#define ION_SECURE_HEAP_NAME "secure_heap" -#define ION_SECURE_DISPLAY_HEAP_NAME "secure_display" - -#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) -#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) - -#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) - -/* struct ion_flush_data - data passed to ion for flushing caches - * - * @handle: handle with data to flush - * @fd: fd to flush - * @vaddr: userspace virtual address mapped with mmap - * @offset: offset into the handle to flush - * @length: length of handle to flush - * - * Performs cache operations on the handle. If p is the start address - * of the handle, p + offset through p + offset + length will have - * the cache operations performed - */ -struct ion_flush_data { - ion_user_handle_t handle; - int fd; - void *vaddr; - unsigned int offset; - unsigned int length; -}; - -struct ion_prefetch_regions { - unsigned int vmid; - size_t *sizes; - unsigned int nr_sizes; -}; - -struct ion_prefetch_data { - int heap_id; - unsigned long len; - /* Is unsigned long bad? 32bit compiler vs 64 bit compiler*/ - struct ion_prefetch_regions *regions; - unsigned int nr_regions; -}; - -#define ION_IOC_MSM_MAGIC 'M' - -/** - * DOC: ION_IOC_CLEAN_CACHES - clean the caches - * - * Clean the caches of the handle specified. - */ -#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \ - struct ion_flush_data) -/** - * DOC: ION_IOC_INV_CACHES - invalidate the caches - * - * Invalidate the caches of the handle specified. - */ -#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \ - struct ion_flush_data) -/** - * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches - * - * Clean and invalidate the caches of the handle specified. - */ -#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \ - struct ion_flush_data) - -#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \ - struct ion_prefetch_data) - -#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \ - struct ion_prefetch_data) - -#endif diff --git a/tinygrad/extra/dsp/include/remote_default.h b/tinygrad/extra/dsp/include/remote_default.h deleted file mode 100644 index 00a82744..00000000 --- a/tinygrad/extra/dsp/include/remote_default.h +++ /dev/null @@ -1,1038 +0,0 @@ -/*----------------------------------------------------------------------------- - Copyright (c) 2012-2014,2016,2017,2019-2021 QUALCOMM Technologies, Incorporated. - All Rights Reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------*/ -#ifndef REMOTE_DEFAULT_H -#define REMOTE_DEFAULT_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @file remote.h - * @brief Header file with APIs to interface with FastRPC. - */ - -typedef uint32_t remote_handle; /**< Handle used by non-domain modules */ -typedef uint64_t remote_handle64; /**< Handle used by multi-domain modules */ -typedef uint64_t fastrpc_async_jobid; /**< Job ID filled in the remote_handle_invoke_async() call*/ - -/** - * @struct remote_buf - * @brief remote buffer for arguments. - */ -typedef struct { - void *pv; /**< Buffer pointer for input/output arguments */ - size_t nLen; /**< Buffer size for input/output arguments */ -} remote_buf; - -/** - * @struct remote_dma_handle - * @brief remote handle structure for passing fd. - */ -typedef struct { - int32_t fd; /**< File Desecripter for buffer */ - uint32_t offset; /**< Buffer offset */ -} remote_dma_handle; - -/** - * @union remote_arg - * @brief union of different types of arguments that are passed to the remote invocation call - */ -typedef union { - remote_buf buf; /**< Buffer holds pointer and size for given argument */ - remote_handle h; /**< Handle for non-domains modules */ - remote_handle64 h64; /**< Handle for multi-omains modules */ - remote_dma_handle dma; /**< DMA Handle that holds buffer fd and offset */ -} remote_arg; - -/** - * @enum fastrpc_async_notify_type - * @brief Types of Asynchronous complete notifications - */ -enum fastrpc_async_notify_type { - FASTRPC_ASYNC_NO_SYNC = 0, /**< synchronous call */ - FASTRPC_ASYNC_CALLBACK, /**< asynchronous call with callback response */ - FASTRPC_ASYNC_POLL, /**< asynchronous call with polling response */ - FASTRPC_ASYNC_TYPE_MAX, /**< reserved */ -}; - -/** - * @struct fastrpc_async_callback - * @brief call back function and context for asynchronous complete notification - */ -typedef struct fastrpc_async_callback { - void (*fn)(fastrpc_async_jobid jobid, void* context, int result); /**< call back function */ - void *context; /**< unique context filled by user */ -}fastrpc_async_callback_t; - -/** - * @struct fastrpc_async_descriptor - * @brief descriptor for defining the complete notification mechanism for given remote invocation call. - */ - -typedef struct fastrpc_async_descriptor { - enum fastrpc_async_notify_type type; /**< asynchronous notification type */ - fastrpc_async_jobid jobid; /**< Job ID returned in async remote invocation call */ - union { - fastrpc_async_callback_t cb; /**< call back function filled by user */ - }; -}fastrpc_async_descriptor_t; - - -/** - * Retrieves method attribute from the scalars parameter - */ -#define REMOTE_SCALARS_METHOD_ATTR(dwScalars) (((dwScalars) >> 29) & 0x7) - -/** - * Retrieves method index from the scalars parameter - */ -#define REMOTE_SCALARS_METHOD(dwScalars) (((dwScalars) >> 24) & 0x1f) - -/** - * Retrieves number of input buffers from the scalars parameter - */ -#define REMOTE_SCALARS_INBUFS(dwScalars) (((dwScalars) >> 16) & 0x0ff) - -/** - * Retrieves number of output buffers from the scalars parameter - */ -#define REMOTE_SCALARS_OUTBUFS(dwScalars) (((dwScalars) >> 8) & 0x0ff) - -/** - * Retrieves number of input handles from the scalars parameter - */ -#define REMOTE_SCALARS_INHANDLES(dwScalars) (((dwScalars) >> 4) & 0x0f) - -/** - * Retrieves number of output handles from the scalars parameter - */ -#define REMOTE_SCALARS_OUTHANDLES(dwScalars) ((dwScalars) & 0x0f) - -/** - * Internal scalars parameter construction for given nAttr, nMethod, nIn, nOut, noIn and noOut - */ -#define REMOTE_SCALARS_MAKEX(nAttr,nMethod,nIn,nOut,noIn,noOut) \ - ((((uint32_t) (nAttr) & 0x7) << 29) | \ - (((uint32_t) (nMethod) & 0x1f) << 24) | \ - (((uint32_t) (nIn) & 0xff) << 16) | \ - (((uint32_t) (nOut) & 0xff) << 8) | \ - (((uint32_t) (noIn) & 0x0f) << 4) | \ - ((uint32_t) (noOut) & 0x0f)) - -/** - * Internal scalars parameter construction for given nAttr, nMethod, nIn, nOut - */ -#define REMOTE_SCALARS_MAKE(nMethod,nIn,nOut) REMOTE_SCALARS_MAKEX(0,nMethod,nIn,nOut,0,0) - -/** - * Internal total number of different arguments for given scalars parameter - */ -#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) +\ - REMOTE_SCALARS_OUTBUFS(sc) +\ - REMOTE_SCALARS_INHANDLES(sc) +\ - REMOTE_SCALARS_OUTHANDLES(sc)) - -/** - * Internal macro for function definition - */ -#ifndef __QAIC_REMOTE - -#define __QAIC_REMOTE(ff) ff -#endif //__QAIC_REMOTE - -/** - * Internal macro for function declaration - */ -#ifndef __QAIC_REMOTE_EXPORT -#ifdef _WIN32 -#define __QAIC_REMOTE_EXPORT __declspec(dllexport) -#else //_WIN32 -#define __QAIC_REMOTE_EXPORT -#endif //_WIN32 -#endif //__QAIC_REMOTE_EXPORT - -/** - * Internal macro for function declaration - */ -#ifndef __QAIC_REMOTE_ATTRIBUTE -#define __QAIC_REMOTE_ATTRIBUTE -#endif - -/** - * Number of Remote Domains - */ -#define NUM_DOMAINS 4 - -/** - * Number of sessions for given process - */ -#define NUM_SESSIONS 2 - -/** - * Internal Mask to retrieve domain - */ -#define DOMAIN_ID_MASK 3 - -/** - * Default remote process domain - */ -#ifndef DEFAULT_DOMAIN_ID -#define DEFAULT_DOMAIN_ID 0 -#endif - -/** - * Internal remote process domain ID definition for ADSP - */ -#define ADSP_DOMAIN_ID 0 - -/** - * Internal remote process domain ID definition MDSP - */ -#define MDSP_DOMAIN_ID 1 - -/** - * Internal remote process domain ID definition for SDSP - */ -#define SDSP_DOMAIN_ID 2 - -/** - * Internal remote process domain ID definition for CDSP - */ -#define CDSP_DOMAIN_ID 3 - -/** - * Internal ADSP remote process definition to check remote process domain from uri - */ -#define ADSP_DOMAIN "&_dom=adsp" - -/** - * Internal MDSP remote process definition to check remote process domain from uri - */ -#define MDSP_DOMAIN "&_dom=mdsp" - -/** - * Internal SDSP remote process definition to check remote process domain from uri - */ -#define SDSP_DOMAIN "&_dom=sdsp" - -/** - * Internal CDSP remote process definition to check remote process domain from uri - */ -#define CDSP_DOMAIN "&_dom=cdsp" - -/**Process Types - * Return values for FASTRPC_REMOTE_PROCESS_TYPE in enum session_control_req_id for remote_handle_control - * Return values denote the type of process on remote subsystem - */ -enum fastrpc_process_type { - PROCESS_TYPE_SIGNED = 0, - PROCESS_TYPE_UNSIGNED = 1, -}; - -/** - * Loads the shared object in remote process and returns the handle to it - * This API used for non-domains use case - * - * @param[in] name pointer to name of the shared object - * @param[out] ph pointer to handle - * - * @return 0 for success and non-zero for failure.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. Other than this error code, - * treated as returned from fastRPC framework issues. -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle_open)(const char* name, remote_handle *ph) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Loads the shared object in remote process and returns the handle to it - * This API used for domains use case - * - * @param[in] name pointer to name of the shared object - * @param[out] ph pointer to handle - * - * @return 0 for success and non-zero for failure.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. Other than this error code, - * treated as returned from fastRPC framework issues. -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle64_open)(const char* name, remote_handle64 *ph) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Makes remote call for given handle synchronously - * This API used for non-domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @param[in] pra pointer to union #remote_arg \n - * A sequence of arguments in the following order inbufs, outbufs, inhandles, outhandles. - * @param[in] dwScalars integer packs Method ID, number of inputs, outputs, inhandles and outhandles - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments are AEE_EINVHANDLE, AEE_EBADPARM. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle_invoke)(remote_handle h, uint32_t dwScalars, remote_arg *pra) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Makes remote call for given handle synchronously - * This API used for domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @param[in] pra pointer to union #remote_arg \n - * A sequence of arguments in the following order inbufs, outbufs, inhandles, outhandles. - * @param[in] dwScalars integer packs Method ID, number of inputs, outputs, inhandles and outhandles - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments are AEE_EINVHANDLE, AEE_EBADPARM. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle64_invoke)(remote_handle64 h, uint32_t dwScalars, remote_arg *pra) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Makes remote call for given handle asynchronously - * This API used for non-domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @param[in] desc pointer to structure #fastrpc_async_descriptor_t - * @param[in] pra pointer to union #remote_arg \n - * sequence of arguments in following order input buffers, output\n - * buffers, in handles and out handles. The number of each type of argument\n - * given in dwScalars below. - * @param[in] dwScalars \n - * Sequence of the following integers related to invocation: The method ID\ - * the number of input buffers in pra, the number of out buffers in pra, - * the number of in handles in pra and the number out handles in pra. - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error codes due to incorrect input arguments are AEE_EINVHANDLE, AEE_EBADPARM. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle_invoke_async)(remote_handle h, fastrpc_async_descriptor_t *desc, uint32_t dwScalars, remote_arg *pra) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Makes remote call for given handle asynchronously - * This API used for domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @param[in] desc pointer to structure #fastrpc_async_descriptor_t - * @param[in] pra pointer to union #remote_arg \n - * sequence of arguments in following order input buffers, output\n - * buffers, in handles and out handles. The number of each type of argument\n - * given in dwScalars below. - * @param[in] dwScalars \n - * Sequence of the following integers related to invocation: The method ID\ - * the number of input buffers in pra, the number of out buffers in pra, - * the number of in handles in pra and the number out handles in pra. - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error codes due to incorrect input arguments are AEE_EINVHANDLE, AEE_EBADPARM. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle64_invoke_async)(remote_handle64 h, fastrpc_async_descriptor_t *desc, uint32_t dwScalars, remote_arg *pra) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Unloads the shared object for given handle - * This API used for non-domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EINVHANDLE. Other than this error code, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle_close)(remote_handle h) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Unloads the shared object for given handle - * This API used for domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EINVHANDLE. Other than this error code, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle64_close)(remote_handle64 h) __QAIC_REMOTE_ATTRIBUTE; - -/** - * @enum handle_control_req_id - * @brief different types of requests that are passed to the remote handle control API - */ -enum handle_control_req_id { - DSPRPC_CONTROL_LATENCY = 1, /**< fastrpc latency control */ - DSPRPC_GET_DSP_INFO = 2, /**< Query DSP capabilities */ - DSPRPC_CONTROL_WAKELOCK = 3, /**< Enable or disable wake lock */ - DSPRPC_GET_DOMAIN = 4, /**< getting the domain */ -}; - -/** - * @enum remote_rpc_latency_flags - * @brief Types of QOS allowed with request ID DSPRPC_CONTROL_LATENCY - - */ -typedef enum remote_rpc_latency_flags { - RPC_DISABLE_QOS = 0, /**< Disable PM QOS. */ - RPC_PM_QOS = 1, /**< Enable PM QOS */ - RPC_ADAPTIVE_QOS = 2, /**< Enable Adaptive QOS */ - RPC_POLL_QOS = 3, /**< Enable Poll QOS */ -} remote_rpc_control_latency_t; - -/** - * @struct remote_rpc_control_latency - * @brief Argument for setting latency with request ID DSPRPC_CONTROL_LATENCY\n - * PM QoS control cpu low power modes based on RPC activity in 100 ms window. Recommended for latency sensitive use cases.\n - * Adaptive QoS, DSP driver predicts completion time of a method and send CPU wake up signal to reduce wake up latency - * Recommended for moderate latency sensitive use cases. It is more power efficient compared to pm_qos control. - * Poll QoS, After sending invocation to DSP, CPU will enter polling mode instead of waiting for a glink response. - * This will boost fastrpc performance by reducing the CPU wakeup and scheduling times. - */ -struct remote_rpc_control_latency { - remote_rpc_control_latency_t enable; /**< Enable type of QOS one of enum #remote_rpc_latency_flags*/ - uint32_t latency; /**< Latency is the time between CPU application making the remote call and beginning of remote DSP method execution. - When used with poll QoS, user needs to pass the expected execution time of method on DSP. CPU will poll for a DSP - response for that specified duration after which it will timeout and fall back to waiting for a glink response. */ -}; - -/** - * @enum remote_dsp_attributes - * @brief Different types of DSP capabilities queried via remote_handle_control - */ -enum remote_dsp_attributes { - DOMAIN_SUPPORT = 0, /**< Domains feature support*/ - UNSIGNED_PD_SUPPORT = 1, /**< Unsigned PD feature support*/ - HVX_SUPPORT_64B = 2, /**< Number of HVX 64B support*/ - HVX_SUPPORT_128B = 3, /**< Number of HVX 128B support*/ - VTCM_PAGE = 4, /**< Max page size allocation possible in VTCM */ - VTCM_COUNT = 5, /**< Number of page_size blocks available */ - ARCH_VER = 6, /**< Hexagon processor architecture version */ - HMX_SUPPORT_DEPTH = 7, /**< HMX Support Depth */ - HMX_SUPPORT_SPATIAL = 8, /**< HMX Support Spatial */ - ASYNC_FASTRPC_SUPPORT = 9, /**< Async FastRPC Support */ - STATUS_NOTIFICATION_SUPPORT = 10, /**< DSP User PD status notification Support */ - FASTRPC_MAX_DSP_ATTRIBUTES = STATUS_NOTIFICATION_SUPPORT + 1, /**< Number of attributes supported */ -}; - -/** - * @struct remote_dsp_capability - * @brief Argument to query DSP capability with request ID DSPRPC_GET_DSP_INFO - */ -typedef struct remote_dsp_capability { - uint32_t domain; /**< Remote domain ID */ - uint32_t attribute_ID; /**< One of the DSP capabilities from enum #remote_dsp_attributes */ - uint32_t capability; /**< Output is capability and possible values vary based on attribute_ID - For DOMAIN_SUPPORT, output values are one, zero. - For UNSIGNED_PD_SUPPORT, output values are one, zero - For, HVX_SUPPORT_64B, output is number of HVX 64B supported - For, HVX_SUPPORT_128B, output is number HVX 128B supported - For VTCM_PAGE, output is Max page size allocation possible in VTCM - For VTCM_COUNT, output is Number of page_size blocks available - For ARCH_VER, output is Hexagon processor architecture version - For HMX_SUPPORT, output is one or zero - For ASYNC_FASTRPC_SUPPORT, output is one or zero*/ -} fastrpc_capability; - -/** Macro for backward compatbility. Clients can compile wakelock request code - * in their app only when this is defined */ -#define FASTRPC_WAKELOCK_CONTROL_SUPPORTED 1 - -/** - * @struct remote_rpc_control_wakelock - * @brief Argument for enable/disable wake lock with request ID DSPRPC_CONTROL_WAKELOCK\n - * CPU can go into suspend mode anytime. For clients who want to keep the CPU awake until they get a response for their - * remote invocation call, recommended to use wake lock feature. - - */ -struct remote_rpc_control_wakelock { - uint32_t enable; /**< enable control of wake lock */ -}; - -/** - * @struct remote_rpc_get_domain - * @brief Argument to get domain from handle with request ID DSPRPC_GET_DOMAIN - */ -typedef struct remote_rpc_get_domain { - int domain; /**< Domain ID*/ - } remote_rpc_get_domain_t; - -/** - * remote_handle64_control API allows to enable features based on handle - * - * @param[in] req one of enum from #handle_control_req_id\n - * Req ID #DSPRPC_CONTROL_LATENCY is used for enable PM QoS, adaptive QoS\n - * Req ID #DSPRPC_GET_DSP_INFO is used for query types of features supported\n - * Req ID #DSPRPC_CONTROL_WAKELOCK is used for enable/disable wake lock\n - * Req ID #DSPRPC_GET_DOMAIN is used for getting the domain ID for given handle\n - * - * @param[in,out] data void pointer to struct for input params\n - * Inputs\n - * struct #remote_rpc_control_latency is used for enable PM QoS, adaptive QoS \n - * struct #remote_dsp_capability is used for query features supported or not. Listed in #remote_dsp_attributes \n - * struct #remote_rpc_control_wakelock is used for enable/disable wake lock \n - * struct #remote_rpc_get_domain is used for getting the domain for given handle \n - * outputs\n - * For req #DSPRPC_CONTROL_LATENCY, output is same as API return value \n - * For req #DSPRPC_GET_DSP_INFO, output is capability argument from #remote_dsp_capability \n - * For req #DSPRPC_CONTROL_WAKELOCK, output is same as API return value \n - * For req #DSPRPC_GET_DOMAIN, output is domain argument from #remote_rpc_get_domain \n - * - * @param[in] datalen Length of the struct defintion used for input params - * - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error codes due to incorrect input arguments are AEE_EBADPARM, AEE_EUNSUPPORTED. - * Other than these error codes, treated as returned from fastRPC framework issues. - * - * For example: - * @code - * struct remote_rpc_control_latency data; - * data.enable = 1; - * data.latency = 100; - * - * if (remote_handle64_control) - * remote_handle64_control(h, DSPRPC_CONTROL_LATENCY, (void*)&data, sizeof(data)); - * else - * printf("remote_handle64_control not available on this target"); - * @endcode -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle_control)(uint32_t req, void* data, uint32_t datalen) __QAIC_REMOTE_ATTRIBUTE; - -/** - * remote_handle64_control API allows to enable features based on handle - * This API used for domains use case - * - * @param[in] h successful handle returned via #remote_handle_open() \n - * @param[in] req one of enum from #handle_control_req_id \n - * Req ID #DSPRPC_CONTROL_LATENCY is used for enable PM QoS, adaptive QoS\n - * Req ID #DSPRPC_GET_DSP_INFO is used for query types of features supported\n - * Req ID #DSPRPC_CONTROL_WAKELOCK is used for enable/disable wake lock\n - * Req ID #DSPRPC_GET_DOMAIN is used for getting the domain ID for given handle\n - * - * @param[in,out] data void pointer to struct for input params\n - * Inputs\n - * struct #remote_rpc_control_latency is used for enable PM QoS, adaptive QoS \n - * struct #remote_dsp_capability is used for query features supported or not. Listed in #remote_dsp_attributes \n - * struct #remote_rpc_control_wakelock is used for enable/disable wake lock \n - * struct #remote_rpc_get_domain is used for getting the domain for given handle \n - * outputs\n - * For req #DSPRPC_CONTROL_LATENCY, output is same as API return value \n - * For req #DSPRPC_GET_DSP_INFO, output is capability argument from #remote_dsp_capability \n - * For req #DSPRPC_CONTROL_WAKELOCK, output is same as API return value \n - * For req #DSPRPC_GET_DOMAIN, output is domain argument from #remote_rpc_get_domain \n - * - * @param[in] datalen Length of the struct defintion used for input params - * - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error codes due to incorrect input arguments are AEE_EBADPARM, AEE_EINVHANDLE, AEE_EUNSUPPORTED - * Other than these error codes, treated as returned from fastRPC framework issues. - * - * For example: - * @code - * struct remote_rpc_control_latency data; - * data.enable = 1; - * data.latency = 100; - * - * if (remote_handle64_control) - * remote_handle64_control(h, DSPRPC_CONTROL_LATENCY, (void*)&data, sizeof(data)); - * else - * printf("remote_handle64_control not available on this target"); - * @endcode -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_handle64_control)(remote_handle64 h, uint32_t req, void* data, uint32_t datalen) __QAIC_REMOTE_ATTRIBUTE; - -/** - * @enum session_control_req_id - * @brief different types of request ID that are passed to the remote session control - */ -enum session_control_req_id { - FASTRPC_THREAD_PARAMS = 1, /**< thread params */ - DSPRPC_CONTROL_UNSIGNED_MODULE = 2, /**< unsigned PD */ - FASTRPC_RELATIVE_THREAD_PRIORITY = 4, /**< relative thread priority */ - FASTRPC_REMOTE_PROCESS_KILL = 6, /**< Kill remote process */ - FASTRPC_SESSION_CLOSE = 7, /**< Close all open handles of requested domain */ - FASTRPC_CONTROL_PD_DUMP = 8, /**< Enable PD dump feature */ - FASTRPC_REMOTE_PROCESS_EXCEPTION = 9, /**< Trigger Exception in the remote process */ - FASTRPC_REMOTE_PROCESS_TYPE = 10, /**< Query type of process defined by enum fastrpc_process_type */ - FASTRPC_REGISTER_STATUS_NOTIFICATIONS = 11, /**< Enable DSP User process status notifications */ -}; - -/** - * @struct remote_rpc_thread_params - * @brief Argument for setting threads params with request ID FASTRPC_THREAD_PARAMS - */ -struct remote_rpc_thread_params { - int domain; /**< Remote subsystem domain ID, pass -1 to set params for all domains */ - int prio; /**< user thread priority (1 to 255), pass -1 to use default */ - int stack_size; /**< user thread stack size in bytes, pass -1 to use default */ -}; - -/** - * @struct remote_rpc_control_unsigned_module - * @brief Argument for setting the unsigned PD with req ID:DSPRPC_CONTROL_UNSIGNED_MODULE - */ -struct remote_rpc_control_unsigned_module { - int domain; /**< Remote subsystem domain ID, -1 to set params for all domains */ - int enable; /**< Non-zero value to set unsigned PD */ -}; - -/** - * @struct remote_rpc_relative_thread_priority - * @brief Argument for setting the relative thread priority with request id:FASTRPC_RELATIVE_THREAD_PRIORITY - */ -struct remote_rpc_relative_thread_priority { - int domain; /**< Remote subsystem domain ID, pass -1 to update priority for all domains */ - int relative_thread_priority; /**< Relative thread priority increased w.r.t to default priority. Negative value will increase priority. Positive value will decrease priority */ -}; - -/** - * @struct remote_rpc_process_clean_params - * @brief Argument for cleaning remote session on DSP with request id:FASTRPC_REMOTE_PROCESS_KILL - */ -struct remote_rpc_process_clean_params { - int domain; /**< Remote subsystem domain ID, domain ID of process to recover */ -}; - -/** - * @struct remote_rpc_session_close - * @brief Argument for closing all handles for all domains with request id:FASTRPC_SESSION_CLOSE - */ -struct remote_rpc_session_close { - int domain; /**< Remote subsystem domain ID, pass -1 to close all handles for all domains */ -}; - -/** - * @struct remote_rpc_control_pd_dump - * @brief Argument for enabling PD dump on User PD of DSP with request id:FASTRPC_CONTROL_PD_DUMP - */ -struct remote_rpc_control_pd_dump { - int domain; /**< Remote subsystem domain ID, pass -1 to enable PD dump on all domains */ - int enable; /**< 1 to enable PD dump, 0 to disable PD dump */ -}; - -/** - * @struct remote_process_type - * Structure for remote_session_control, used with FASTRPC_REMOTE_PROCESS_TYPE request ID to query the type of PD runs on, defined by enum fastrpc_process_type - * @param[in] : Domain of process - * @param[out]: process_type belonging to enum fastrpc_process_type - */ -struct remote_process_type { - int domain; - int process_type; -}; - -/** - * @struct remote_rpc_process_clean_params - * @brief Argument to trigger exception in the User PD of DSP with request id:FASTRPC_REMOTE_PROCESS_EXCEPTION - */ -typedef struct remote_rpc_process_clean_params remote_rpc_process_exception; - -/** - * @enum remote_rpc_status_flags - * @brief different types of DSP User PD status notification flags - */ -typedef enum remote_rpc_status_flags { - FASTRPC_USER_PD_UP = 0, /**< DSP user process is up */ - FASTRPC_USER_PD_EXIT = 1, /**< DSP user process exited */ - FASTRPC_USER_PD_FORCE_KILL = 2, /**< DSP user process forcefully killed. Happens when DSP resources needs to be freed. */ - FASTRPC_USER_PD_EXCEPTION = 3, /**< Exception in the user process of DSP. */ - FASTRPC_DSP_SSR = 4, /**< Subsystem restart of the DSP, where user process is running. */ -} remote_rpc_status_flags_t; - -/** - * Notification call back function - * @param[in] context used in the registration - * @param[in] domain of the user process - * @param[in] session id of user process - * @param[in] status of user process - * @return Integer value. Zero for success and non-zero for failure. - */ -typedef int (*fastrpc_notif_fn_t)(void *context, int domain, int session, remote_rpc_status_flags_t status); - -/** - * @struct remote_rpc_notif_register - * @brief Argument to receive status notifications of user process on DSP, with request ID DSPRPC_REGISTER_STATUS_NOTIFICATIONS - */ -typedef struct remote_rpc_notif_register { - void *context; /**< Context of the client */ - int domain; /**< Remote domain ID */ - fastrpc_notif_fn_t notifier_fn; /**< Notification call back function pointer */ -} remote_rpc_notif_register_t; - -/** - * remote_session_control API allows configure the remote session params - - * @param[in] req is one of enum from #session_control_req_id \n - * Req FASTRPC_THREAD_PARAMS is used for setting the theread stack size and priority \n - * Req DSPRPC_CONTROL_UNSIGNED_MODULE used for setting the unsigned PD \n - * Req FASTRPC_RELATIVE_THREAD_PRIORITY used for setting the relative thread priority \n - * - * @param[in] data void pointer to struct for input params \n - * struct #remote_rpc_thread_params is used for setting the thread priority and stack size \n - * struct #remote_rpc_control_unsigned_module is used for setting the unsigned PD \n - * struct #remote_rpc_relative_thread_priority is used for setting the relative thread priority \n - * - * @param[in] datalen is length of the struct for input params \n - * - * @return Integer value. Zero for succesfully setting the remote session params. Non-zero for failure. \n - * Expected error codes due to incorrect input arguments are AEE_EBADPARM, AEE_EUNSUPPORTED - * Other than this error codes, treated as returned from fastRPC framework issues. - * For example: - * @code - * if (remote_session_control) - * { - * struct remote_rpc_control_unsigned_module data; - * - * data.enable = 1; - * data.domain = CDSP_DOMAIN_ID; - * retVal = remote_session_control(DSPRPC_CONTROL_UNSIGNED_MODULE, (void*)&data, sizeof(data)); - * printf("remote_session_control returned %d for configuring unsigned PD", retVal); - * } - * else{ - * printf("Unsigned PD not supported on this device.\n"); - * } - * @endcode -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_session_control)(uint32_t req, void *data, uint32_t datalen) __QAIC_REMOTE_ATTRIBUTE; - -/** - * remote_mmap API maps the pages on remote domain - * - * @param[in] fd file descriptor for given buffer - * @param[in] flags one of enum from #remote_mem_map_flags. - * @param[in] vaddrin HLOS address for given buffer - * @param[in] size Length of the given buffer - * @param[out] vaddrout virtual address on remote domain - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. - * Other than these error codes, treated as returned from fastRPC framework issues. - * For example: - * @code - * int nErr = 0 - * if (remote_mem_map) { - * nErr = remote_mem_map(domain, fd, flags, buf, size, remoteVirtAddr); - * } else { - * // symbol not found. Fall back to old API - * nErr = remote_mmap64(fd, flags, buf, size, remoteVirtAddr); - * } - * return nErr; - * @endcode -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_mmap)(int fd, uint32_t flags, uint32_t vaddrin, int size, uint32_t* vaddrout) __QAIC_REMOTE_ATTRIBUTE; - - /** - * remote_unmap API unmaps the pages on remote domain - * @param[in] vaddrout virtual address returned via #remote_mmap() - * @param[in] size Length of the given buffer - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. - * Other than these error codes, treated as returned from fastRPC framework issues. -*/ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_munmap)(uint32_t vaddrout, int size) __QAIC_REMOTE_ATTRIBUTE; - -/** - * @enum remote_mem_map_flags - * @brief Different set of flags for mapping the buffer on remote process domain\n - * Create static memory map on remote process with default cache configuration (writeback). - * Same remoteVirtAddr will be assigned on remote process when fastrpc call made with local virtual address. - * Map scope: - * Life time of this mapping is until user unmap using remote_mem_unmap or session close. - * No reference counts are used. Behavior of mapping multiple times without unmap is undefined. - * Cache maintenance: - * Driver clean caches when virtual address passed through RPC calls defined in IDL as a pointer. - * User is responsible for cleaning cache when remoteVirtAddr shared to DSP and accessed out of fastrpc method invocations on DSP. - * recommended usage: - * Map buffers which are reused for long time or until session close. This helps to reduce fastrpc latency. - * Memory shared with remote process and accessed only by DSP. - */ - -enum remote_mem_map_flags { - REMOTE_MAP_MEM_STATIC = 0, - REMOTE_MAP_MAX_FLAG = REMOTE_MAP_MEM_STATIC + 1, -}; - -/** - * Map memory to the remote process on a selected DSP domain - * @param[in] domain DSP domain ID. Use -1 for using default domain\n - * Default domain is selected based on library lib(a/m/s/c)dsprpc.so library linked to application. - * @param[in] fd file descriptor of memory - * @param[in] flags one of enum from #remote_mem_map_flags - * @param[in] virtAddr virtual address of buffer - * @param[in] size buffer length - * @param[out] remoteVirtAddr remote process virtual address - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM - * Other than these error codes, treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_mem_map)(int domain, int fd, int flags, uint64_t virtAddr, size_t size, uint64_t* remoteVirtAddr) __QAIC_REMOTE_ATTRIBUTE; - -/** - * Unmap memory to the remote process on a selected DSP domain - * @param[in] domain DSP domain ID. Use -1 for using default domain. Get domain from multi-domain handle if required. - * @param[in] remoteVirtAddr virtual address returned via #remote_mem_map() - * @param[in] size buffer length - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM - * Other than this error code, treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_mem_unmap)(int domain, uint64_t remoteVirtAddr, size_t size) __QAIC_REMOTE_ATTRIBUTE; - -/** - * @enum remote_buf_attributes - * @brief Types of buffer attributes - */ -enum remote_buf_attributes { - FASTRPC_ATTR_NON_COHERENT = 2, /**< Attribute to map a buffer as DMA non-coherent Driver perform cache maintenance. */ - FASTRPC_ATTR_COHERENT = 4, /**< Attribute to map a buffer as DMA coherent Driver skips cache maintenenace. - It will be ignored if a device is marked as DMA-coherent in device tree. */ - FASTRPC_ATTR_KEEP_MAP = 8, /**< Attribute to keep the buffer persistant until unmap is called explicitly */ - FASTRPC_ATTR_NOMAP = 16, /**< Attribute for secure buffers to skip smmu mapping in fastrpc driver */ - FASTRPC_ATTR_FORCE_NOFLUSH = 32, /**< Attribute to map buffer such that flush by driver is skipped for that particular buffer. - Client has to perform cache maintenance. */ - FASTRPC_ATTR_FORCE_NOINVALIDATE = 64, /**< Attribute to map buffer such that invalidate by driver is skipped for that particular buffer. - Client has to perform cache maintenance. */ - FASTRPC_ATTR_TRY_MAP_STATIC = 128, /**< Attribute for persistent mapping a buffer to remote DSP - process during buffer registration with the FastRPC driver. - This buffer will be automatically mapped during session - open and unmapped either at session close or buffer - unregistration. The FastRPC library treis to map buffers - and ignores error in case of failure. Pre-mapping a buffer reduces the FastRPC latency. This flag is recommended only - for buffers used with latency-critical FastRPC calls. */ -}; - -/** Register a file descriptor for a user allocated buffer(Other than rpcmem_alloc). This is only valid on - * Android with ION allocated memory. Users of fastRPC should register - * a buffer allocated with ION to enable sharing that buffer to the - * DSP via the SMMU. If user allocated buffers not registered via this API - * remote calls are expected to take more latency where these user buffers are passed. - * Some versions of libadsprpc.so lack this function, so users should set - * this symbol as weak.\n - * `pragma weak remote_register_buf_attr`\n - * @param[in] buf virtual address of the buffer - * @param[in] size size of the buffer - * @param[in] fd file descriptor, callers can use -1 to deregister. - * @param[in] attr map buffer as coherent or non-coherent \n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. Other than this error - * codes treated as returned from fastRPC framework issues. - */ - - __QAIC_REMOTE_EXPORT void __QAIC_REMOTE(remote_register_buf_attr)(void* buf, int size, int fd, int attr) __QAIC_REMOTE_ATTRIBUTE; - -/** Register a file descriptor for a user allocated buffer(Other than rpcmem_alloc). This is only valid on - * Android with ION allocated memory. Users of fastRPC should register - * a buffer allocated with ION to enable sharing that buffer to the - * DSP via the SMMU. If user allocated buffers not registered via this API - * remote calls are expected to take more latency where these user buffers are passed. - * Some versions of libadsprpc.so lack this function, so users should set - * this symbol as weak.\n - * pragma weak remote_register_buf\n - * @param[in] buf virtual address of the buffer - * @param[in] size size of the buffer - * @param[in] fd file descriptor, callers can use -1 to deregister \n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. Other than this error - * codes treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT void __QAIC_REMOTE(remote_register_buf)(void* buf, int size, int fd) __QAIC_REMOTE_ATTRIBUTE; - -/** Register a DMA handle with fastrpc. This is only valid on - * android with ION allocated memory. Users of fastrpc should register - * a file descriptor allocated with ION to enable sharing that memory to the - * dsp via the smmu. Some versions of libadsprpc.so lack this - * function, so users should set this symbol as weak.\n - * - * `pragma weak remote_register_dma_handle`\n - * `pragma weak remote_register_dma_handle_attr`\n - * @param[in] fd file descriptor, callers can use -1 to deregister. - * @param[in] len size of the buffer - * @param[in] attr map buffer as coherent or non-coherent or no-map\n - * Expected error codes due to incorrect input arguments are AEE_EBADPARM, AEE_EINVHANDLE. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_register_dma_handle_attr)(int fd, uint32_t len, uint32_t attr) __QAIC_REMOTE_ATTRIBUTE; - -/** Register a DMA handle with fastrpc. This is only valid on - * android with ION allocated memory. Users of fastrpc should register - * a file descriptor allocated with ION to enable sharing that memory to the - * dsp via the smmu. Some versions of libadsprpc.so lack this - * function, so users should set this symbol as weak.\n - * - * pragma weak remote_register_dma_handle\n - * @param[in] fd file descriptor, callers can use -1 to deregister. - * @param[in] len size of the buffer \n - * Expected error codes due to incorrect input arguments are AEE_EBADPARM, AEE_EINVHANDLE. Other than these error codes, - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_register_dma_handle)(int fd, uint32_t len) __QAIC_REMOTE_ATTRIBUTE; - -/** Register a file descriptor. This can be used when users do not have - * a mapping to pass to the RPC layer. The generated address is a mapping - * with PROT_NONE, any access to this memory will fail, so it should only - * be used as an ID to identify this file descriptor to the RPC layer. - * - * To deregister use remote_register_buf(addr, size, -1). - * - * `pragma weak remote_register_fd`\n - * @param[in] fd is the file descriptor. - * @param[in] size length the buffer - * @return (void*)-1 on failure, address on success.\n - * All error codes treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT void *__QAIC_REMOTE(remote_register_fd)(int fd, int size) __QAIC_REMOTE_ATTRIBUTE; - -/** Get status of Async job. This can be used to query the status of a Async job - * - * @param[in] jobid returned during Async job submission via #remote_handle_invoke_async() - * @param[in] timeout_us in micro seconds \n - * timeout = 0, returns immediately with status/result\n - * timeout > 0, waits for specified time and then returns with status/result \n - * timeout < 0. waits indefinetely until job completes \n - * @param[out] result ouptput pointer \n - * 0 on success\n - * error code on failure\n - * @return 0 on job completion\n - * if job status is pending, it is not returned from DSP\n - * Expected error code due to incorrect input arguments is AEE_EBADPARM. Other than this error code - * treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(fastrpc_async_get_status)(fastrpc_async_jobid jobid, int timeout_us, int *result); - -/** Release Async job. Release async job after receiving status either through callback/poll - * - * @param[in] jobid returned during Async job submission via #remote_handle_invoke_async() - * @return Zero for success. Non-zero for failure.\n - * AEE_EBUSY, if job status is pending and is not returned from DSP\n - * AEE_EBADPARM, if job id is invalid \n - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(fastrpc_release_async_job)(fastrpc_async_jobid jobid); - -/** - * By default, Driver runs Parallel mode - */ -#define REMOTE_MODE_PARALLEL 0 - -/** - * When operating in SERIAL mode the driver will invalidate output buffers - * before calling into the dsp. This mode should be used when output - * buffers have been written to somewhere besides the aDSP. - */ -#define REMOTE_MODE_SERIAL 1 - -/** - * Internal transport prefix - */ -#define ITRANSPORT_PREFIX "'\":;./\\" - -/** remote_set_mode API will be deprecated in near future. It is discouraged to use this API.\n - * Set the mode of operation.\n - * This is the default mode for the driver. While the driver is in parallel - * mode it will try to invalidate output buffers after it transfers control - * to the dsp. This allows the invalidate operations to overlap with the - * dsp processing the call. This mode should be used when output buffers - * are only read on the application processor and only written on the aDSP. - * Some versions of libadsprpc.so lack this function, so users should set - * this symbol as weak.\n - * `pragma weak remote_set_mode` - * @param[in] mode serial/parallel operation - * @return Integer value. Zero for success and non-zero for failure. For failure, returns error code.\n - * All error codes, treated as returned from fastRPC framework issues. - */ -__QAIC_REMOTE_EXPORT int __QAIC_REMOTE(remote_set_mode)(uint32_t mode) __QAIC_REMOTE_ATTRIBUTE; - -/** - * @enum fastrpc_map_flags - * @brief Types of maps with cache maintenance - */ -enum fastrpc_map_flags { - /** - * Map memory pages with RW- permission and CACHE WRITEBACK. - * Driver will clean cache when buffer passed in a FastRPC call. - * Same remote virtual address will be assigned for subsequent - * FastRPC calls. - */ - FASTRPC_MAP_STATIC = 0, - - /* Reserved for compatibility with deprecated flag */ - FASTRPC_MAP_RESERVED = 1, - - /** - * Map memory pages with RW- permission and CACHE WRITEBACK. - * Mapping tagged with a file descriptor. User is responsible for - * maintenance of CPU and DSP caches for the buffer. Get virtual address - * of buffer on DSP using HAP_mmap_get() and HAP_mmap_put() functions. - */ - FASTRPC_MAP_FD = 2, - - /** - * Mapping delayed until user calls HAP_mmap() and HAP_munmap() - * functions on DSP. User is responsible for maintenance of CPU and DSP - * caches for the buffer. Delayed mapping is useful for users to map - * buffer on DSP with other than default permissions and cache modes - * using HAP_mmap() and HAP_munmap() functions. - */ - FASTRPC_MAP_FD_DELAYED = 3, - - /** - * MAX enum is used internally by the FastRPC library for checking range of valid flags. - * Add new flags above it. Leave unassigned and as last enum value. - */ - FASTRPC_MAP_MAX, -}; - -/** - * Creates a mapping on remote process for an ION buffer with file descriptor. A new FastRPC session - * will be opened if not already opened for the domain. - * - * @param domain DSP domain ID of a FastRPC session - * @param fd ION memory file descriptor - * @param addr buffer virtual address on cpu - * @param offset offset from the beginining of the buffer - * @param length size of buffer in bytes - * @param flags controls mapping functionality on DSP. Refer fastrpc_map_flags enum definition for more information. - * - * @return 0 on success, error code on failure. - * - AEE_EBADPARM Bad parameters - * - AEE_EFAILED Failed to map buffer - * - AEE_ENOMEMORY Out of memory (internal error) - * - AEE_EUNSUPPORTED Unsupported API on the target - */ -int fastrpc_mmap(int domain, int fd, void *addr, int offset, size_t length, enum fastrpc_map_flags flags); - -/** - * Removes a mapping associated with file descriptor. - * - * @param domain DSP domain ID of a FastRPC session - * @param fd file descriptor - * @param addr buffer virtual address used for mapping creation - * @param length size of buffer mapped in bytes - * - * @return 0 on success, error code on failure. - * - AEE_EBADPARM Bad parameters e.g. Mapping not found for specified fd - * - AEE_EFAILED Failed to map buffer - * - AEE_EUNSUPPORTED Unsupported API on the target - */ -int fastrpc_munmap(int domain, int fd, void *addr, size_t length); - -#ifdef __cplusplus -} -#endif - -#endif // REMOTE_DEFAULT_H diff --git a/tinygrad/extra/dsp/invoke_bug.py b/tinygrad/extra/dsp/invoke_bug.py deleted file mode 100644 index 6247f19a..00000000 --- a/tinygrad/extra/dsp/invoke_bug.py +++ /dev/null @@ -1,326 +0,0 @@ -from tinygrad.runtime.ops_dsp import DSPDevice - -kernel = """__attribute__((noinline)) void r_6_10_13_4_4_29(float* restrict __attribute__((align_value(128))) data0, const float* restrict __attribute__((align_value(128))) data1, const float* restrict __attribute__((align_value(128))) data2, const float* restrict __attribute__((align_value(128))) data3) { - float val0 = data1[0]; - float val1 = data1[1]; - float val2 = data1[2]; - float val3 = data1[3]; - float val4 = data1[4]; - float val5 = data1[5]; - float val6 = data1[6]; - float val7 = data1[7]; - float val8 = data1[8]; - float val9 = data1[9]; - float val10 = data1[10]; - float val11 = data1[11]; - float val12 = data1[12]; - float val13 = data1[13]; - float val14 = data1[14]; - float val15 = data1[15]; - float val16 = data1[16]; - float val17 = data1[17]; - float val18 = data1[18]; - float val19 = data1[19]; - float val20 = data1[20]; - float val21 = data1[21]; - float val22 = data1[22]; - float val23 = data1[23]; - float val24 = data1[24]; - float val25 = data1[25]; - float val26 = data1[26]; - float val27 = data1[27]; - float val28 = data1[28]; - for (int ridx0 = 0; ridx0 < 6; ridx0++) { - for (int ridx1 = 0; ridx1 < 10; ridx1++) { - int alu0 = ((ridx0*1160)+(ridx1*4)); - float val29 = data3[alu0+1]; - float val30 = data3[alu0+2]; - float val31 = data3[alu0+3]; - float val32 = data3[alu0+40]; - float val33 = data3[alu0+41]; - float val34 = data3[alu0+42]; - float val35 = data3[alu0+43]; - float val36 = data3[alu0+80]; - float val37 = data3[alu0+81]; - float val38 = data3[alu0+82]; - float val39 = data3[alu0+83]; - float val40 = data3[alu0+120]; - float val41 = data3[alu0+121]; - float val42 = data3[alu0+122]; - float val43 = data3[alu0+123]; - float val44 = data3[alu0+160]; - float val45 = data3[alu0+161]; - float val46 = data3[alu0+162]; - float val47 = data3[alu0+163]; - float val48 = data3[alu0+200]; - float val49 = data3[alu0+201]; - float val50 = data3[alu0+202]; - float val51 = data3[alu0+203]; - float val52 = data3[alu0+240]; - float val53 = data3[alu0+241]; - float val54 = data3[alu0+242]; - float val55 = data3[alu0+243]; - float val56 = data3[alu0+280]; - float val57 = data3[alu0+281]; - float val58 = data3[alu0+282]; - float val59 = data3[alu0+283]; - float val60 = data3[alu0+320]; - float val61 = data3[alu0+321]; - float val62 = data3[alu0+322]; - float val63 = data3[alu0+323]; - float val64 = data3[alu0+360]; - float val65 = data3[alu0+361]; - float val66 = data3[alu0+362]; - float val67 = data3[alu0+363]; - float val68 = data3[alu0+400]; - float val69 = data3[alu0+401]; - float val70 = data3[alu0+402]; - float val71 = data3[alu0+403]; - float val72 = data3[alu0+440]; - float val73 = data3[alu0+441]; - float val74 = data3[alu0+442]; - float val75 = data3[alu0+443]; - float val76 = data3[alu0+480]; - float val77 = data3[alu0+481]; - float val78 = data3[alu0+482]; - float val79 = data3[alu0+483]; - float val80 = data3[alu0+520]; - float val81 = data3[alu0+521]; - float val82 = data3[alu0+522]; - float val83 = data3[alu0+523]; - float val84 = data3[alu0+560]; - float val85 = data3[alu0+561]; - float val86 = data3[alu0+562]; - float val87 = data3[alu0+563]; - float val88 = data3[alu0+600]; - float val89 = data3[alu0+601]; - float val90 = data3[alu0+602]; - float val91 = data3[alu0+603]; - float val92 = data3[alu0+640]; - float val93 = data3[alu0+641]; - float val94 = data3[alu0+642]; - float val95 = data3[alu0+643]; - float val96 = data3[alu0+680]; - float val97 = data3[alu0+681]; - float val98 = data3[alu0+682]; - float val99 = data3[alu0+683]; - float val100 = data3[alu0+720]; - float val101 = data3[alu0+721]; - float val102 = data3[alu0+722]; - float val103 = data3[alu0+723]; - float val104 = data3[alu0+760]; - float val105 = data3[alu0+761]; - float val106 = data3[alu0+762]; - float val107 = data3[alu0+763]; - float val108 = data3[alu0+800]; - float val109 = data3[alu0+801]; - float val110 = data3[alu0+802]; - float val111 = data3[alu0+803]; - float val112 = data3[alu0+840]; - float val113 = data3[alu0+841]; - float val114 = data3[alu0+842]; - float val115 = data3[alu0+843]; - float val116 = data3[alu0+880]; - float val117 = data3[alu0+881]; - float val118 = data3[alu0+882]; - float val119 = data3[alu0+883]; - float val120 = data3[alu0+920]; - float val121 = data3[alu0+921]; - float val122 = data3[alu0+922]; - float val123 = data3[alu0+923]; - float val124 = data3[alu0+960]; - float val125 = data3[alu0+961]; - float val126 = data3[alu0+962]; - float val127 = data3[alu0+963]; - float val128 = data3[alu0+1000]; - float val129 = data3[alu0+1001]; - float val130 = data3[alu0+1002]; - float val131 = data3[alu0+1003]; - float val132 = data3[alu0+1040]; - float val133 = data3[alu0+1041]; - float val134 = data3[alu0+1042]; - float val135 = data3[alu0+1043]; - float val136 = data3[alu0+1080]; - float val137 = data3[alu0+1081]; - float val138 = data3[alu0+1082]; - float val139 = data3[alu0+1083]; - float val140 = data3[alu0+1120]; - float val141 = data3[alu0+1121]; - float val142 = data3[alu0+1122]; - float val143 = data3[alu0+1123]; - float val144 = data3[alu0]; - for (int ridx2 = 0; ridx2 < 13; ridx2++) { - int alu1 = (ridx2*4); - int alu2 = ((ridx0*2080)+(ridx1*208)+alu1); - float val145 = data2[alu1+1]; - float cast0 = (float)(((val0!=val145)!=1)); - float cast1 = (float)(((val1!=val145)!=1)); - float cast2 = (float)(((val2!=val145)!=1)); - float cast3 = (float)(((val3!=val145)!=1)); - float cast4 = (float)(((val4!=val145)!=1)); - float cast5 = (float)(((val5!=val145)!=1)); - float cast6 = (float)(((val6!=val145)!=1)); - float cast7 = (float)(((val7!=val145)!=1)); - float cast8 = (float)(((val8!=val145)!=1)); - float cast9 = (float)(((val9!=val145)!=1)); - float cast10 = (float)(((val10!=val145)!=1)); - float cast11 = (float)(((val11!=val145)!=1)); - float cast12 = (float)(((val12!=val145)!=1)); - float cast13 = (float)(((val13!=val145)!=1)); - float cast14 = (float)(((val14!=val145)!=1)); - float cast15 = (float)(((val15!=val145)!=1)); - float cast16 = (float)(((val16!=val145)!=1)); - float cast17 = (float)(((val17!=val145)!=1)); - float cast18 = (float)(((val18!=val145)!=1)); - float cast19 = (float)(((val19!=val145)!=1)); - float cast20 = (float)(((val20!=val145)!=1)); - float cast21 = (float)(((val21!=val145)!=1)); - float cast22 = (float)(((val22!=val145)!=1)); - float cast23 = (float)(((val23!=val145)!=1)); - float cast24 = (float)(((val24!=val145)!=1)); - float cast25 = (float)(((val25!=val145)!=1)); - float cast26 = (float)(((val26!=val145)!=1)); - float cast27 = (float)(((val27!=val145)!=1)); - float cast28 = (float)(((val28!=val145)!=1)); - data0[alu2+1] = ((cast0*val144)+(cast1*val32)+(cast2*val36)+(cast3*val40)+(cast4*val44)+(cast5*val48)+(cast6*val52)+(cast7*val56)+(cast8*val60)+(cast9*val64)+(cast10*val68)+(cast11*val72)+(cast12*val76)+(cast13*val80)+(cast14*val84)+(cast15*val88)+(cast16*val92)+(cast17*val96)+(cast18*val100)+(cast19*val104)+(cast20*val108)+(cast21*val112)+(cast22*val116)+(cast23*val120)+(cast24*val124)+(cast25*val128)+(cast26*val132)+(cast27*val136)+(cast28*val140)); - data0[alu2+53] = ((cast0*val29)+(cast1*val33)+(cast2*val37)+(cast3*val41)+(cast4*val45)+(cast5*val49)+(cast6*val53)+(cast7*val57)+(cast8*val61)+(cast9*val65)+(cast10*val69)+(cast11*val73)+(cast12*val77)+(cast13*val81)+(cast14*val85)+(cast15*val89)+(cast16*val93)+(cast17*val97)+(cast18*val101)+(cast19*val105)+(cast20*val109)+(cast21*val113)+(cast22*val117)+(cast23*val121)+(cast24*val125)+(cast25*val129)+(cast26*val133)+(cast27*val137)+(cast28*val141)); - data0[alu2+105] = ((cast0*val30)+(cast1*val34)+(cast2*val38)+(cast3*val42)+(cast4*val46)+(cast5*val50)+(cast6*val54)+(cast7*val58)+(cast8*val62)+(cast9*val66)+(cast10*val70)+(cast11*val74)+(cast12*val78)+(cast13*val82)+(cast14*val86)+(cast15*val90)+(cast16*val94)+(cast17*val98)+(cast18*val102)+(cast19*val106)+(cast20*val110)+(cast21*val114)+(cast22*val118)+(cast23*val122)+(cast24*val126)+(cast25*val130)+(cast26*val134)+(cast27*val138)+(cast28*val142)); - data0[alu2+157] = ((cast0*val31)+(cast1*val35)+(cast2*val39)+(cast3*val43)+(cast4*val47)+(cast5*val51)+(cast6*val55)+(cast7*val59)+(cast8*val63)+(cast9*val67)+(cast10*val71)+(cast11*val75)+(cast12*val79)+(cast13*val83)+(cast14*val87)+(cast15*val91)+(cast16*val95)+(cast17*val99)+(cast18*val103)+(cast19*val107)+(cast20*val111)+(cast21*val115)+(cast22*val119)+(cast23*val123)+(cast24*val127)+(cast25*val131)+(cast26*val135)+(cast27*val139)+(cast28*val143)); - float val146 = data2[alu1+2]; - float cast29 = (float)(((val0!=val146)!=1)); - float cast30 = (float)(((val1!=val146)!=1)); - float cast31 = (float)(((val2!=val146)!=1)); - float cast32 = (float)(((val3!=val146)!=1)); - float cast33 = (float)(((val4!=val146)!=1)); - float cast34 = (float)(((val5!=val146)!=1)); - float cast35 = (float)(((val6!=val146)!=1)); - float cast36 = (float)(((val7!=val146)!=1)); - float cast37 = (float)(((val8!=val146)!=1)); - float cast38 = (float)(((val9!=val146)!=1)); - float cast39 = (float)(((val10!=val146)!=1)); - float cast40 = (float)(((val11!=val146)!=1)); - float cast41 = (float)(((val12!=val146)!=1)); - float cast42 = (float)(((val13!=val146)!=1)); - float cast43 = (float)(((val14!=val146)!=1)); - float cast44 = (float)(((val15!=val146)!=1)); - float cast45 = (float)(((val16!=val146)!=1)); - float cast46 = (float)(((val17!=val146)!=1)); - float cast47 = (float)(((val18!=val146)!=1)); - float cast48 = (float)(((val19!=val146)!=1)); - float cast49 = (float)(((val20!=val146)!=1)); - float cast50 = (float)(((val21!=val146)!=1)); - float cast51 = (float)(((val22!=val146)!=1)); - float cast52 = (float)(((val23!=val146)!=1)); - float cast53 = (float)(((val24!=val146)!=1)); - float cast54 = (float)(((val25!=val146)!=1)); - float cast55 = (float)(((val26!=val146)!=1)); - float cast56 = (float)(((val27!=val146)!=1)); - float cast57 = (float)(((val28!=val146)!=1)); - data0[alu2+2] = ((cast29*val144)+(cast30*val32)+(cast31*val36)+(cast32*val40)+(cast33*val44)+(cast34*val48)+(cast35*val52)+(cast36*val56)+(cast37*val60)+(cast38*val64)+(cast39*val68)+(cast40*val72)+(cast41*val76)+(cast42*val80)+(cast43*val84)+(cast44*val88)+(cast45*val92)+(cast46*val96)+(cast47*val100)+(cast48*val104)+(cast49*val108)+(cast50*val112)+(cast51*val116)+(cast52*val120)+(cast53*val124)+(cast54*val128)+(cast55*val132)+(cast56*val136)+(cast57*val140)); - data0[alu2+54] = ((cast29*val29)+(cast30*val33)+(cast31*val37)+(cast32*val41)+(cast33*val45)+(cast34*val49)+(cast35*val53)+(cast36*val57)+(cast37*val61)+(cast38*val65)+(cast39*val69)+(cast40*val73)+(cast41*val77)+(cast42*val81)+(cast43*val85)+(cast44*val89)+(cast45*val93)+(cast46*val97)+(cast47*val101)+(cast48*val105)+(cast49*val109)+(cast50*val113)+(cast51*val117)+(cast52*val121)+(cast53*val125)+(cast54*val129)+(cast55*val133)+(cast56*val137)+(cast57*val141)); - data0[alu2+106] = ((cast29*val30)+(cast30*val34)+(cast31*val38)+(cast32*val42)+(cast33*val46)+(cast34*val50)+(cast35*val54)+(cast36*val58)+(cast37*val62)+(cast38*val66)+(cast39*val70)+(cast40*val74)+(cast41*val78)+(cast42*val82)+(cast43*val86)+(cast44*val90)+(cast45*val94)+(cast46*val98)+(cast47*val102)+(cast48*val106)+(cast49*val110)+(cast50*val114)+(cast51*val118)+(cast52*val122)+(cast53*val126)+(cast54*val130)+(cast55*val134)+(cast56*val138)+(cast57*val142)); - data0[alu2+158] = ((cast29*val31)+(cast30*val35)+(cast31*val39)+(cast32*val43)+(cast33*val47)+(cast34*val51)+(cast35*val55)+(cast36*val59)+(cast37*val63)+(cast38*val67)+(cast39*val71)+(cast40*val75)+(cast41*val79)+(cast42*val83)+(cast43*val87)+(cast44*val91)+(cast45*val95)+(cast46*val99)+(cast47*val103)+(cast48*val107)+(cast49*val111)+(cast50*val115)+(cast51*val119)+(cast52*val123)+(cast53*val127)+(cast54*val131)+(cast55*val135)+(cast56*val139)+(cast57*val143)); - float val147 = data2[alu1+3]; - float cast58 = (float)(((val0!=val147)!=1)); - float cast59 = (float)(((val1!=val147)!=1)); - float cast60 = (float)(((val2!=val147)!=1)); - float cast61 = (float)(((val3!=val147)!=1)); - float cast62 = (float)(((val4!=val147)!=1)); - float cast63 = (float)(((val5!=val147)!=1)); - float cast64 = (float)(((val6!=val147)!=1)); - float cast65 = (float)(((val7!=val147)!=1)); - float cast66 = (float)(((val8!=val147)!=1)); - float cast67 = (float)(((val9!=val147)!=1)); - float cast68 = (float)(((val10!=val147)!=1)); - float cast69 = (float)(((val11!=val147)!=1)); - float cast70 = (float)(((val12!=val147)!=1)); - float cast71 = (float)(((val13!=val147)!=1)); - float cast72 = (float)(((val14!=val147)!=1)); - float cast73 = (float)(((val15!=val147)!=1)); - float cast74 = (float)(((val16!=val147)!=1)); - float cast75 = (float)(((val17!=val147)!=1)); - float cast76 = (float)(((val18!=val147)!=1)); - float cast77 = (float)(((val19!=val147)!=1)); - float cast78 = (float)(((val20!=val147)!=1)); - float cast79 = (float)(((val21!=val147)!=1)); - float cast80 = (float)(((val22!=val147)!=1)); - float cast81 = (float)(((val23!=val147)!=1)); - float cast82 = (float)(((val24!=val147)!=1)); - float cast83 = (float)(((val25!=val147)!=1)); - float cast84 = (float)(((val26!=val147)!=1)); - float cast85 = (float)(((val27!=val147)!=1)); - float cast86 = (float)(((val28!=val147)!=1)); - data0[alu2+3] = ((cast58*val144)+(cast59*val32)+(cast60*val36)+(cast61*val40)+(cast62*val44)+(cast63*val48)+(cast64*val52)+(cast65*val56)+(cast66*val60)+(cast67*val64)+(cast68*val68)+(cast69*val72)+(cast70*val76)+(cast71*val80)+(cast72*val84)+(cast73*val88)+(cast74*val92)+(cast75*val96)+(cast76*val100)+(cast77*val104)+(cast78*val108)+(cast79*val112)+(cast80*val116)+(cast81*val120)+(cast82*val124)+(cast83*val128)+(cast84*val132)+(cast85*val136)+(cast86*val140)); - data0[alu2+55] = ((cast58*val29)+(cast59*val33)+(cast60*val37)+(cast61*val41)+(cast62*val45)+(cast63*val49)+(cast64*val53)+(cast65*val57)+(cast66*val61)+(cast67*val65)+(cast68*val69)+(cast69*val73)+(cast70*val77)+(cast71*val81)+(cast72*val85)+(cast73*val89)+(cast74*val93)+(cast75*val97)+(cast76*val101)+(cast77*val105)+(cast78*val109)+(cast79*val113)+(cast80*val117)+(cast81*val121)+(cast82*val125)+(cast83*val129)+(cast84*val133)+(cast85*val137)+(cast86*val141)); - data0[alu2+107] = ((cast58*val30)+(cast59*val34)+(cast60*val38)+(cast61*val42)+(cast62*val46)+(cast63*val50)+(cast64*val54)+(cast65*val58)+(cast66*val62)+(cast67*val66)+(cast68*val70)+(cast69*val74)+(cast70*val78)+(cast71*val82)+(cast72*val86)+(cast73*val90)+(cast74*val94)+(cast75*val98)+(cast76*val102)+(cast77*val106)+(cast78*val110)+(cast79*val114)+(cast80*val118)+(cast81*val122)+(cast82*val126)+(cast83*val130)+(cast84*val134)+(cast85*val138)+(cast86*val142)); - data0[alu2+159] = ((cast58*val31)+(cast59*val35)+(cast60*val39)+(cast61*val43)+(cast62*val47)+(cast63*val51)+(cast64*val55)+(cast65*val59)+(cast66*val63)+(cast67*val67)+(cast68*val71)+(cast69*val75)+(cast70*val79)+(cast71*val83)+(cast72*val87)+(cast73*val91)+(cast74*val95)+(cast75*val99)+(cast76*val103)+(cast77*val107)+(cast78*val111)+(cast79*val115)+(cast80*val119)+(cast81*val123)+(cast82*val127)+(cast83*val131)+(cast84*val135)+(cast85*val139)+(cast86*val143)); - float val148 = data2[alu1]; - float cast87 = (float)(((val0!=val148)!=1)); - float cast88 = (float)(((val1!=val148)!=1)); - float cast89 = (float)(((val2!=val148)!=1)); - float cast90 = (float)(((val3!=val148)!=1)); - float cast91 = (float)(((val4!=val148)!=1)); - float cast92 = (float)(((val5!=val148)!=1)); - float cast93 = (float)(((val6!=val148)!=1)); - float cast94 = (float)(((val7!=val148)!=1)); - float cast95 = (float)(((val8!=val148)!=1)); - float cast96 = (float)(((val9!=val148)!=1)); - float cast97 = (float)(((val10!=val148)!=1)); - float cast98 = (float)(((val11!=val148)!=1)); - float cast99 = (float)(((val12!=val148)!=1)); - float cast100 = (float)(((val13!=val148)!=1)); - float cast101 = (float)(((val14!=val148)!=1)); - float cast102 = (float)(((val15!=val148)!=1)); - float cast103 = (float)(((val16!=val148)!=1)); - float cast104 = (float)(((val17!=val148)!=1)); - float cast105 = (float)(((val18!=val148)!=1)); - float cast106 = (float)(((val19!=val148)!=1)); - float cast107 = (float)(((val20!=val148)!=1)); - float cast108 = (float)(((val21!=val148)!=1)); - float cast109 = (float)(((val22!=val148)!=1)); - float cast110 = (float)(((val23!=val148)!=1)); - float cast111 = (float)(((val24!=val148)!=1)); - float cast112 = (float)(((val25!=val148)!=1)); - float cast113 = (float)(((val26!=val148)!=1)); - float cast114 = (float)(((val27!=val148)!=1)); - float cast115 = (float)(((val28!=val148)!=1)); - data0[alu2+52] = ((cast87*val29)+(cast88*val33)+(cast89*val37)+(cast90*val41)+(cast91*val45)+(cast92*val49)+(cast93*val53)+(cast94*val57)+(cast95*val61)+(cast96*val65)+(cast97*val69)+(cast98*val73)+(cast99*val77)+(cast100*val81)+(cast101*val85)+(cast102*val89)+(cast103*val93)+(cast104*val97)+(cast105*val101)+(cast106*val105)+(cast107*val109)+(cast108*val113)+(cast109*val117)+(cast110*val121)+(cast111*val125)+(cast112*val129)+(cast113*val133)+(cast114*val137)+(cast115*val141)); - data0[alu2+104] = ((cast87*val30)+(cast88*val34)+(cast89*val38)+(cast90*val42)+(cast91*val46)+(cast92*val50)+(cast93*val54)+(cast94*val58)+(cast95*val62)+(cast96*val66)+(cast97*val70)+(cast98*val74)+(cast99*val78)+(cast100*val82)+(cast101*val86)+(cast102*val90)+(cast103*val94)+(cast104*val98)+(cast105*val102)+(cast106*val106)+(cast107*val110)+(cast108*val114)+(cast109*val118)+(cast110*val122)+(cast111*val126)+(cast112*val130)+(cast113*val134)+(cast114*val138)+(cast115*val142)); - data0[alu2+156] = ((cast87*val31)+(cast88*val35)+(cast89*val39)+(cast90*val43)+(cast91*val47)+(cast92*val51)+(cast93*val55)+(cast94*val59)+(cast95*val63)+(cast96*val67)+(cast97*val71)+(cast98*val75)+(cast99*val79)+(cast100*val83)+(cast101*val87)+(cast102*val91)+(cast103*val95)+(cast104*val99)+(cast105*val103)+(cast106*val107)+(cast107*val111)+(cast108*val115)+(cast109*val119)+(cast110*val123)+(cast111*val127)+(cast112*val131)+(cast113*val135)+(cast114*val139)+(cast115*val143)); - data0[alu2] = ((cast87*val144)+(cast88*val32)+(cast89*val36)+(cast90*val40)+(cast91*val44)+(cast92*val48)+(cast93*val52)+(cast94*val56)+(cast95*val60)+(cast96*val64)+(cast97*val68)+(cast98*val72)+(cast99*val76)+(cast100*val80)+(cast101*val84)+(cast102*val88)+(cast103*val92)+(cast104*val96)+(cast105*val100)+(cast106*val104)+(cast107*val108)+(cast108*val112)+(cast109*val116)+(cast110*val120)+(cast111*val124)+(cast112*val128)+(cast113*val132)+(cast114*val136)+(cast115*val140)); - } - } - } -}""" - -entry = """typedef union { struct { void *pv; unsigned int len; } buf; struct { int fd; unsigned int offset; } dma; } remote_arg; -void* HAP_mmap(void *addr, int len, int prot, int flags, int fd, long offset); -int HAP_munmap(void *addr, int len); -int HAP_mmap_get(int fd, void **vaddr, void **paddr); -int HAP_mmap_put(int fd); -unsigned long long HAP_perf_get_time_us(void); -int entry(unsigned long long handle, unsigned int sc, remote_arg* pra) { -if ((sc>>24) != 2) return 0; - -unsigned long long start = HAP_perf_get_time_us(); -for (int i = 0; i < 50; i++) { - void* buf = HAP_mmap(0, 1, 3, 0, pra[2].dma.fd, 0); - HAP_munmap(buf, 1); -} -*(unsigned long long *)(pra[1].buf.pv) = HAP_perf_get_time_us() - start; - -return 0; } -""" - -if __name__ == "__main__": - dev = DSPDevice() - - bufs = [dev.allocator.alloc(0x60000) for _ in range(4)] - - only_entry = dev.compiler.compile(entry) - app1 = dev.runtime("test", only_entry) - x = app1(*bufs) - - entry_n_unsued_code = dev.compiler.compile(kernel + "\n" + entry) - app2 = dev.runtime("test", entry_n_unsued_code) - x = app2(*bufs) diff --git a/tinygrad/extra/dsp/invoke_bug_2.py b/tinygrad/extra/dsp/invoke_bug_2.py deleted file mode 100644 index e73eabe9..00000000 --- a/tinygrad/extra/dsp/invoke_bug_2.py +++ /dev/null @@ -1,279 +0,0 @@ -from tinygrad.runtime.ops_dsp import DSPDevice - -kernel = """__attribute__((noinline)) void r_64_4_4_64_4_4_4(float* restrict __attribute__((align_value(128))) data0, const float* restrict __attribute__((align_value(128))) data1, const float* restrict __attribute__((align_value(128))) data2, const float* restrict __attribute__((align_value(128))) data3) { - for (int ridx0 = 0; ridx0 < 64; ridx0++) { - int alu0 = (ridx0*4096); - for (int ridx1 = 0; ridx1 < 4; ridx1++) { - int alu1 = (ridx1*64); - for (int ridx2 = 0; ridx2 < 4; ridx2++) { - int alu2 = (ridx2*4); - int alu3 = ((ridx0*1024)+alu1+alu2); - int alu4 = (alu1+alu2); - float val0 = data3[alu4+1]; - float val1 = data3[alu4+2]; - float val2 = data3[alu4+3]; - float val3 = data3[alu4+16]; - float val4 = data3[alu4+17]; - float val5 = data3[alu4+18]; - float val6 = data3[alu4+19]; - float val7 = data3[alu4+32]; - float val8 = data3[alu4+33]; - float val9 = data3[alu4+34]; - float val10 = data3[alu4+35]; - float val11 = data3[alu4+48]; - float val12 = data3[alu4+49]; - float val13 = data3[alu4+50]; - float val14 = data3[alu4+51]; - float val15 = data3[alu4]; - float acc0 = 0.0f; - float acc1 = 0.0f; - float acc2 = 0.0f; - float acc3 = 0.0f; - float acc4 = 0.0f; - float acc5 = 0.0f; - float acc6 = 0.0f; - float acc7 = 0.0f; - float acc8 = 0.0f; - float acc9 = 0.0f; - float acc10 = 0.0f; - float acc11 = 0.0f; - float acc12 = 0.0f; - float acc13 = 0.0f; - float acc14 = 0.0f; - float acc15 = 0.0f; - float acc16 = 0.0f; - float acc17 = 0.0f; - float acc18 = 0.0f; - float acc19 = 0.0f; - float acc20 = 0.0f; - float acc21 = 0.0f; - float acc22 = 0.0f; - float acc23 = 0.0f; - float acc24 = 0.0f; - float acc25 = 0.0f; - float acc26 = 0.0f; - float acc27 = 0.0f; - float acc28 = 0.0f; - float acc29 = 0.0f; - float acc30 = 0.0f; - float acc31 = 0.0f; - float acc32 = 0.0f; - float acc33 = 0.0f; - float acc34 = 0.0f; - float acc35 = 0.0f; - float acc36 = 0.0f; - float acc37 = 0.0f; - float acc38 = 0.0f; - float acc39 = 0.0f; - float acc40 = 0.0f; - float acc41 = 0.0f; - float acc42 = 0.0f; - float acc43 = 0.0f; - float acc44 = 0.0f; - float acc45 = 0.0f; - float acc46 = 0.0f; - float acc47 = 0.0f; - float acc48 = 0.0f; - float acc49 = 0.0f; - float acc50 = 0.0f; - float acc51 = 0.0f; - float acc52 = 0.0f; - float acc53 = 0.0f; - float acc54 = 0.0f; - float acc55 = 0.0f; - float acc56 = 0.0f; - float acc57 = 0.0f; - float acc58 = 0.0f; - float acc59 = 0.0f; - float acc60 = 0.0f; - float acc61 = 0.0f; - float acc62 = 0.0f; - float acc63 = 0.0f; - for (int ridx3 = 0; ridx3 < 64; ridx3++) { - int alu5 = (alu0+(ridx2*256)+ridx3); - float val16 = data2[alu5+64]; - float val17 = data2[alu5+128]; - float val18 = data2[alu5+192]; - float val19 = data2[alu5+1024]; - float val20 = data2[alu5+1088]; - float val21 = data2[alu5+1152]; - float val22 = data2[alu5+1216]; - float val23 = data2[alu5+2048]; - float val24 = data2[alu5+2112]; - float val25 = data2[alu5+2176]; - float val26 = data2[alu5+2240]; - float val27 = data2[alu5+3072]; - float val28 = data2[alu5+3136]; - float val29 = data2[alu5+3200]; - float val30 = data2[alu5+3264]; - float val31 = data2[alu5]; - int alu6 = (alu0+(ridx1*256)+ridx3); - float val32 = data1[alu6+64]; - float val33 = data1[alu6+128]; - float val34 = data1[alu6+192]; - float val35 = data1[alu6+1024]; - float val36 = data1[alu6+1088]; - float val37 = data1[alu6+1152]; - float val38 = data1[alu6+1216]; - float val39 = data1[alu6+2048]; - float val40 = data1[alu6+2112]; - float val41 = data1[alu6+2176]; - float val42 = data1[alu6+2240]; - float val43 = data1[alu6+3072]; - float val44 = data1[alu6+3136]; - float val45 = data1[alu6+3200]; - float val46 = data1[alu6+3264]; - float val47 = data1[alu6]; - acc0 = (acc0+(val47*val31)); - acc1 = (acc1+(val35*val19)); - acc2 = (acc2+(val39*val23)); - acc3 = (acc3+(val43*val27)); - acc4 = (acc4+(val32*val31)); - acc5 = (acc5+(val36*val19)); - acc6 = (acc6+(val40*val23)); - acc7 = (acc7+(val44*val27)); - acc8 = (acc8+(val33*val31)); - acc9 = (acc9+(val37*val19)); - acc10 = (acc10+(val41*val23)); - acc11 = (acc11+(val45*val27)); - acc12 = (acc12+(val34*val31)); - acc13 = (acc13+(val38*val19)); - acc14 = (acc14+(val42*val23)); - acc15 = (acc15+(val46*val27)); - acc16 = (acc16+(val47*val16)); - acc17 = (acc17+(val35*val20)); - acc18 = (acc18+(val39*val24)); - acc19 = (acc19+(val43*val28)); - acc20 = (acc20+(val32*val16)); - acc21 = (acc21+(val36*val20)); - acc22 = (acc22+(val40*val24)); - acc23 = (acc23+(val44*val28)); - acc24 = (acc24+(val33*val16)); - acc25 = (acc25+(val37*val20)); - acc26 = (acc26+(val41*val24)); - acc27 = (acc27+(val45*val28)); - acc28 = (acc28+(val34*val16)); - acc29 = (acc29+(val38*val20)); - acc30 = (acc30+(val42*val24)); - acc31 = (acc31+(val46*val28)); - acc32 = (acc32+(val47*val17)); - acc33 = (acc33+(val35*val21)); - acc34 = (acc34+(val39*val25)); - acc35 = (acc35+(val43*val29)); - acc36 = (acc36+(val32*val17)); - acc37 = (acc37+(val36*val21)); - acc38 = (acc38+(val40*val25)); - acc39 = (acc39+(val44*val29)); - acc40 = (acc40+(val33*val17)); - acc41 = (acc41+(val37*val21)); - acc42 = (acc42+(val41*val25)); - acc43 = (acc43+(val45*val29)); - acc44 = (acc44+(val34*val17)); - acc45 = (acc45+(val38*val21)); - acc46 = (acc46+(val42*val25)); - acc47 = (acc47+(val46*val29)); - acc48 = (acc48+(val47*val18)); - acc49 = (acc49+(val35*val22)); - acc50 = (acc50+(val39*val26)); - acc51 = (acc51+(val43*val30)); - acc52 = (acc52+(val32*val18)); - acc53 = (acc53+(val36*val22)); - acc54 = (acc54+(val40*val26)); - acc55 = (acc55+(val44*val30)); - acc56 = (acc56+(val33*val18)); - acc57 = (acc57+(val37*val22)); - acc58 = (acc58+(val41*val26)); - acc59 = (acc59+(val45*val30)); - acc60 = (acc60+(val34*val18)); - acc61 = (acc61+(val38*val22)); - acc62 = (acc62+(val42*val26)); - acc63 = (acc63+(val46*val30)); - } - data0[alu3] = ((acc0*0.125f)+val15); - data0[alu3+256] = ((acc1*0.125f)+val15); - data0[alu3+512] = ((acc2*0.125f)+val15); - data0[alu3+768] = ((acc3*0.125f)+val15); - data0[alu3+16] = ((acc4*0.125f)+val3); - data0[alu3+272] = ((acc5*0.125f)+val3); - data0[alu3+528] = ((acc6*0.125f)+val3); - data0[alu3+784] = ((acc7*0.125f)+val3); - data0[alu3+32] = ((acc8*0.125f)+val7); - data0[alu3+288] = ((acc9*0.125f)+val7); - data0[alu3+544] = ((acc10*0.125f)+val7); - data0[alu3+800] = ((acc11*0.125f)+val7); - data0[alu3+48] = ((acc12*0.125f)+val11); - data0[alu3+304] = ((acc13*0.125f)+val11); - data0[alu3+560] = ((acc14*0.125f)+val11); - data0[alu3+816] = ((acc15*0.125f)+val11); - data0[alu3+1] = ((acc16*0.125f)+val0); - data0[alu3+257] = ((acc17*0.125f)+val0); - data0[alu3+513] = ((acc18*0.125f)+val0); - data0[alu3+769] = ((acc19*0.125f)+val0); - data0[alu3+17] = ((acc20*0.125f)+val4); - data0[alu3+273] = ((acc21*0.125f)+val4); - data0[alu3+529] = ((acc22*0.125f)+val4); - data0[alu3+785] = ((acc23*0.125f)+val4); - data0[alu3+33] = ((acc24*0.125f)+val8); - data0[alu3+289] = ((acc25*0.125f)+val8); - data0[alu3+545] = ((acc26*0.125f)+val8); - data0[alu3+801] = ((acc27*0.125f)+val8); - data0[alu3+49] = ((acc28*0.125f)+val12); - data0[alu3+305] = ((acc29*0.125f)+val12); - data0[alu3+561] = ((acc30*0.125f)+val12); - data0[alu3+817] = ((acc31*0.125f)+val12); - data0[alu3+2] = ((acc32*0.125f)+val1); - data0[alu3+258] = ((acc33*0.125f)+val1); - data0[alu3+514] = ((acc34*0.125f)+val1); - data0[alu3+770] = ((acc35*0.125f)+val1); - data0[alu3+18] = ((acc36*0.125f)+val5); - data0[alu3+274] = ((acc37*0.125f)+val5); - data0[alu3+530] = ((acc38*0.125f)+val5); - data0[alu3+786] = ((acc39*0.125f)+val5); - data0[alu3+34] = ((acc40*0.125f)+val9); - data0[alu3+290] = ((acc41*0.125f)+val9); - data0[alu3+546] = ((acc42*0.125f)+val9); - data0[alu3+802] = ((acc43*0.125f)+val9); - data0[alu3+50] = ((acc44*0.125f)+val13); - data0[alu3+306] = ((acc45*0.125f)+val13); - data0[alu3+562] = ((acc46*0.125f)+val13); - data0[alu3+818] = ((acc47*0.125f)+val13); - data0[alu3+3] = ((acc48*0.125f)+val2); - data0[alu3+259] = ((acc49*0.125f)+val2); - data0[alu3+515] = ((acc50*0.125f)+val2); - data0[alu3+771] = ((acc51*0.125f)+val2); - data0[alu3+19] = ((acc52*0.125f)+val6); - data0[alu3+275] = ((acc53*0.125f)+val6); - data0[alu3+531] = ((acc54*0.125f)+val6); - data0[alu3+787] = ((acc55*0.125f)+val6); - data0[alu3+35] = ((acc56*0.125f)+val10); - data0[alu3+291] = ((acc57*0.125f)+val10); - data0[alu3+547] = ((acc58*0.125f)+val10); - data0[alu3+803] = ((acc59*0.125f)+val10); - data0[alu3+51] = ((acc60*0.125f)+val14); - data0[alu3+307] = ((acc61*0.125f)+val14); - data0[alu3+563] = ((acc62*0.125f)+val14); - data0[alu3+819] = ((acc63*0.125f)+val14); - } - } - } -} -""" - -entry = """unsigned long long HAP_perf_get_time_us(void); -int entry(unsigned long long handle, unsigned int sc, void* pra) { -return HAP_perf_get_time_us() == 1 ? 4 : 0; -} -""" - -if __name__ == "__main__": - dev = DSPDevice() - - bufs = [dev.allocator.alloc(0x60000) for _ in range(4)] - - only_entry = dev.compiler.compile(entry) - app1 = dev.runtime("test", only_entry) - x = app1(*bufs) - - entry_n_unsued_code = dev.compiler.compile(kernel + "\n" + entry) - app2 = dev.runtime("test", entry_n_unsued_code) - x = app2(*bufs) diff --git a/tinygrad/extra/dsp/opt.py b/tinygrad/extra/dsp/opt.py deleted file mode 100644 index dca9ab64..00000000 --- a/tinygrad/extra/dsp/opt.py +++ /dev/null @@ -1,27 +0,0 @@ -from tinygrad import Device - -# PATH=/opt/homebrew/opt/llvm/bin:$PATH python3 extra/dsp/opt.py - -if __name__ == "__main__": - compiler = Device["DSP"].compiler - - lib = compiler.compile(""" -typedef long HVX_Vector __attribute__((__vector_size__(128))) __attribute__ ((aligned(128))); -typedef long HVX_VectorPair __attribute__((__vector_size__(256))) __attribute__ ((aligned(256))); - -void test(unsigned char *c, unsigned char *a, unsigned char *b) { - HVX_Vector t0 = *(HVX_Vector*)a; - //HVX_VectorPair t1 = *((HVX_VectorPair*)b); - HVX_Vector acc = __builtin_HEXAGON_V6_vd0_128B(); - for (int i = 0; i < 128; i++) { - //__builtin_HEXAGON_V6_lvsplatb_128B(t0[i]) - //acc += __builtin_HEXAGON_V6_lvsplatb_128B(t0[i]) * t1; - //acc += t0[i] * t1; - unsigned int t1 = ((unsigned int *)b)[i]; - //acc = __builtin_HEXAGON_V6_vrmpyub_acc_128B(acc, t0, t1); - acc = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc, t0, t1); - } - *((HVX_Vector*)c) = acc; -}""") - - compiler.disassemble(lib) diff --git a/tinygrad/extra/dsp/preload.c b/tinygrad/extra/dsp/preload.c deleted file mode 100644 index 9428dc4e..00000000 --- a/tinygrad/extra/dsp/preload.c +++ /dev/null @@ -1,79 +0,0 @@ -__attribute__((constructor)) -void preload_init() { - Py_Initialize(); - PyRun_SimpleString("print('hello from c'); import extra.dsp.hook"); -} - -#define _GNU_SOURCE // Must be defined before any includes for RTLD_NEXT -#include -#include -#include // Include Python header -//#include - -// Define the original ioctl function pointer -static int (*real_ioctl)(int fd, unsigned long request, void *arg) = NULL; - -// Our custom ioctl hook -int ioctl(int fd, unsigned long request, void *arg) { - // Initialize the real ioctl function pointer on first call - if (!real_ioctl) { - real_ioctl = dlsym(RTLD_NEXT, "ioctl"); - if (!real_ioctl) { - fprintf(stderr, "Error: Could not find real ioctl\n"); - return -1; - } - } - - // Log the call - //printf("Hooked ioctl: tid=%d fd=%d, request=0x%lx, arg=%p\n", gettid(), fd, request, arg); - - // Call a Python function from extra.dsp.hook - PyObject *pName, *pModule, *pFunc, *pArgs, *pValue; - PyGILState_STATE gstate; - - // Ensure the GIL is held (required for Python calls in multi-threaded apps) - //gstate = PyGILState_Ensure(); - - // Import the module - pName = PyUnicode_FromString("extra.dsp.hook"); - pModule = PyImport_Import(pName); - Py_DECREF(pName); - - // Call the original ioctl - int ret = real_ioctl(fd, request, arg); - - if (pModule != NULL) { - // Get the function (assume it’s called "handle_ioctl") - pFunc = PyObject_GetAttrString(pModule, "handle_ioctl"); - - if (pFunc && PyCallable_Check(pFunc)) { - // Create arguments tuple (fd, request, arg, ret) - pArgs = PyTuple_Pack(4, - PyLong_FromLong(fd), - PyLong_FromUnsignedLong(request), - PyLong_FromVoidPtr(arg), - PyLong_FromLong(ret)); - pValue = PyObject_CallObject(pFunc, pArgs); - Py_DECREF(pArgs); - - if (pValue != NULL) { - Py_DECREF(pValue); - } else { - PyErr_Print(); // Print Python error if call fails - } - Py_DECREF(pFunc); - } else { - if (PyErr_Occurred()) PyErr_Print(); - fprintf(stderr, "Cannot find function 'handle_ioctl'\n"); - } - Py_DECREF(pModule); - } else { - PyErr_Print(); - fprintf(stderr, "Failed to load 'extra.dsp.hook'\n"); - } - - // Release the GIL - //PyGILState_Release(gstate); - return ret; -} - diff --git a/tinygrad/extra/dsp/run.py b/tinygrad/extra/dsp/run.py deleted file mode 100755 index 4293a037..00000000 --- a/tinygrad/extra/dsp/run.py +++ /dev/null @@ -1,152 +0,0 @@ -# mypy: ignore-errors -#!/usr/bin/env python3 -import os, ctypes, ctypes.util, struct, platform, time -from tinygrad.runtime.autogen import libc, qcom_dsp -def to_mv(ptr, sz) -> memoryview: return memoryview(ctypes.cast(ptr, ctypes.POINTER(ctypes.c_uint8 * sz)).contents).cast("B") -from hexdump import hexdump - -def get_struct(argp, stype): - return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents - -def format_struct(s): - sdats = [] - for field in s._fields_: - dat = getattr(s, field[0]) - if isinstance(dat, int): sdats.append(f"{field[0]}:0x{dat:X}") - elif hasattr(dat, "_fields_"): sdats.append((field[0], format_struct(dat))) - elif field[0] == "PADDING_0": pass - else: sdats.append(f"{field[0]}:{dat}") - return sdats - -@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p) -def ioctl(fd, request, argp): - fn = os.readlink(f"/proc/self/fd/{fd}") - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - - if fn == "/dev/adsprpc-smd": - if nr == 1: - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke) - method = (st.sc>>24) & 0xFF - in_args = (st.sc>>16) & 0xFF - out_args = (st.sc>>8) & 0xFF - if out_args: - for arg in range(in_args, in_args+out_args): - ctypes.memset(st.pra[arg].buf.pv, 0, st.pra[arg].buf.len) - - # print("enter", libc.gettid()) - ret = libc.syscall(0x1d, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp)) - # print("done", libc.gettid()) - if fn == "/dev/ion": - if nr == 0: - st = get_struct(argp, qcom_dsp.struct_ion_allocation_data) - print(ret, "ION_IOC_ALLOC", format_struct(st)) - elif nr == 1: - st = get_struct(argp, qcom_dsp.struct_ion_handle_data) - print(ret, "ION_IOC_FREE", format_struct(st)) - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_ion_fd_data) - print(ret, "ION_IOC_MAP", format_struct(st)) - elif fn == "/dev/adsprpc-smd": - assert chr(itype) == 'R' - if nr == 8: - st = ctypes.c_uint32.from_address(argp) - print(ret, "FASTRPC_IOCTL_GETINFO", st.value) - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_mmap) - print(ret, "FASTRPC_IOCTL_MMAP", format_struct(st)) - elif nr == 1: - # https://research.checkpoint.com/2021/pwn2own-qualcomm-dsp/ - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke) - print(ret, "FASTRPC_IOCTL_INVOKE", format_struct(st)) - # 0xFF000000 = Method index and attribute (the highest byte) - # 0x00FF0000 = Number of input arguments - # 0x0000FF00 = Number of output arguments - # 0x000000F0 = Number of input handles - # 0x0000000F = Number of output handles - - method = (st.sc>>24) & 0xFF - in_args = (st.sc>>16) & 0xFF - out_args = (st.sc>>8) & 0xFF - in_h = (st.sc>>4) & 0xF - out_h = (st.sc>>0) & 0xF - print(f"\tm:{method} ia:{in_args} oa:{out_args} ih:{in_h} oh:{out_h}") - if in_args or out_args: - for arg in range(in_args+out_args): - print(arg, format_struct(st.pra[arg])) - if st.pra[arg].buf.pv is not None: - ww = to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len) - hexdump(to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len)[:0x40]) - elif nr == 6: - print(ret, "FASTRPC_IOCTL_INIT", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_init))) - print(os.readlink(f"/proc/self/fd/{ini.filefd}")) - # print(bytearray(to_mv(ini.file, ini.filelen))) - elif nr == 7: - print(ret, "FASTRPC_IOCTL_INVOKE_ATTRS", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke_attrs))) - elif nr == 12: print(ret, "FASTRPC_IOCTL_CONTROL", format_struct(get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_control))) - else: - print(f"{ret} UNPARSED {nr}") - else: - print("ioctl", f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", fn) - return ret - -def install_hook(c_function, python_function): - orig_func = (ctypes.c_char*4096)() - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - - # get real ioctl address - ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - - # hook ioctl - ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7) - assert ret == 0 - ret = libc.mprotect(ctypes.c_ulong((ctypes.addressof(orig_func)//0x1000)*0x1000), 0x3000, 7) - assert ret == 0 - libc.memcpy(orig_func, ioctl_address.contents, 0x1000) - libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp)) - return orig_func - -libc = ctypes.CDLL(ctypes.util.find_library("libc")) -#install_hook(libc.ioctl, ioctl) -adsp = ctypes.CDLL(ctypes.util.find_library("adsprpc")) - -def send_rpc_invoke(filename): - pass - -if __name__ == "__main__": - print("calculator_open") - # /dsp/cdsp/fastrpc_shell_3 - - handle = ctypes.c_int64(-1) - z = adsp.remote_handle64_open(ctypes.create_string_buffer(b"file:///libcalculator_skel.so?calculator_skel_handle_invoke&_modver=1.0&_dom=cdsp"), - ctypes.byref(handle)) - - print("handle", z, hex(handle.value)) - assert handle.value != -1 - test = (ctypes.c_int32 * 100)() - for i in range(100): test[i] = i - print("calculator_sum") - pra = (qcom_dsp.union_remote_arg64 * 3)() - #arg_0 = ctypes.c_int32(100) - arg_0 = ctypes.c_int32(100) - arg_2 = ctypes.c_int64(-1) - pra[0].buf.pv = ctypes.addressof(arg_0) - pra[0].buf.len = 4 - pra[1].buf.pv = ctypes.addressof(test) - pra[1].buf.len = 0x190 - pra[2].buf.pv = ctypes.addressof(arg_2) - pra[2].buf.len = 8 - adsp.remote_handle64_invoke(handle, (2<<24) | (2<<16) | (1<<8), pra) - print(arg_2.value) - print("done") - - print("closing") - x = adsp.remote_handle64_close(handle) - print(x) - print("dun") - os._exit(0) diff --git a/tinygrad/extra/dsp/run_3.py b/tinygrad/extra/dsp/run_3.py deleted file mode 100755 index ad505998..00000000 --- a/tinygrad/extra/dsp/run_3.py +++ /dev/null @@ -1,312 +0,0 @@ -#!/usr/bin/env python3 -import os, ctypes, ctypes.util, struct, platform, pathlib, contextlib, mmap, array -from threading import Thread -from tinygrad.runtime.autogen import qcom_dsp -from tinygrad.helpers import round_up, mv_address, to_mv -from hexdump import hexdump - -def get_struct(argp, stype): - return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents - -def format_struct(s): - sdats = [] - for field in s._fields_: - dat = getattr(s, field[0]) - if isinstance(dat, int): sdats.append(f"{field[0]}:0x{dat:X}") - elif hasattr(dat, "_fields_"): sdats.append((field[0], format_struct(dat))) - elif field[0] == "PADDING_0": pass - else: sdats.append(f"{field[0]}:{dat}") - return sdats - -@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p) -def ioctl(fd, request, argp): - fn = os.readlink(f"/proc/self/fd/{fd}") - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - - # print("enter", libc.gettid()) - ret = libc.syscall(0x1d, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp)) - # print("done", libc.gettid()) - if fn == "/dev/ion": - if nr == 0: - st = get_struct(argp, qcom_dsp.struct_ion_allocation_data) - print(ret, "ION_IOC_ALLOC", format_struct(st)) - elif nr == 1: - st = get_struct(argp, qcom_dsp.struct_ion_handle_data) - print(ret, "ION_IOC_FREE", format_struct(st)) - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_ion_fd_data) - print(ret, "ION_IOC_MAP", format_struct(st)) - elif fn == "/dev/adsprpc-smd": - assert chr(itype) == 'R' - if nr == 8: - st = ctypes.c_uint32.from_address(argp) - print(ret, "FASTRPC_IOCTL_GETINFO", st.value) - elif nr == 2: - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_mmap) - print(ret, "FASTRPC_IOCTL_MMAP", format_struct(st)) - elif nr == 1: - # https://research.checkpoint.com/2021/pwn2own-qualcomm-dsp/ - st = get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke) - print(ret, "FASTRPC_IOCTL_INVOKE", format_struct(st)) - # 0xFF000000 = Method index and attribute (the highest byte) - # 0x00FF0000 = Number of input arguments - # 0x0000FF00 = Number of output arguments - # 0x000000F0 = Number of input handles - # 0x0000000F = Number of output handles - - method = (st.sc>>24) & 0xFF - in_args = (st.sc>>16) & 0xFF - out_args = (st.sc>>8) & 0xFF - in_h = (st.sc>>4) & 0xF - out_h = (st.sc>>0) & 0xF - print(f"\tm:{method} ia:{in_args} oa:{out_args} ih:{in_h} oh:{out_h}") - if in_args or out_args: - for arg in range(in_args+out_args): - print(arg, format_struct(st.pra[arg])) - # print(arg, f"arg (0x{st.pra[arg].buf.pv:X} len=0x{st.pra[arg].buf.len:X})") - # print("input" if arg < in_args else "output", f"arg (0x{st.pra[arg].buf.pv:X} len=0x{st.pra[arg].buf.len:X})") - if st.pra[arg].buf.pv is not None: - # if st.pra[arg].buf.len == 0x258: - # print(bytearray(to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len))) - if st.pra[arg].buf.len == 0x68: - print(bytearray(to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len))) - - cut = 0x2000 if st.pra[arg].buf.len == 0x2000 or st.pra[arg].buf.len == 0x258 else 0x100 - ww = to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len) - hexdump(to_mv(st.pra[arg].buf.pv, st.pra[arg].buf.len)[:cut]) - - # if st.pra[arg].buf.len == 0x1000 and ww[0x30] == 0x6e: - # z = ww.cast('Q')[1] + 0x7F00000000 - # print("DOO") - # hexdump(to_mv(z, 0x200)) - #print(format_struct(st.pra))) - elif nr == 6: - print(ret, "FASTRPC_IOCTL_INIT", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_init))) - print(os.readlink(f"/proc/self/fd/{ini.filefd}")) - # print(bytearray(to_mv(ini.file, ini.filelen))) - elif nr == 7: - print(ret, "FASTRPC_IOCTL_INVOKE_ATTRS", format_struct(ini:=get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_invoke_attrs))) - elif nr == 12: print(ret, "FASTRPC_IOCTL_CONTROL", format_struct(get_struct(argp, qcom_dsp.struct_fastrpc_ioctl_control))) - else: - print(f"{ret} UNPARSED {nr}") - else: - print("ioctl", f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", fn) - return ret - -def install_hook(c_function, python_function): - orig_func = (ctypes.c_char*4096)() - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - - # get real ioctl address - ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - - # hook ioctl - ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7) - assert ret == 0 - ret = libc.mprotect(ctypes.c_ulong((ctypes.addressof(orig_func)//0x1000)*0x1000), 0x3000, 7) - assert ret == 0 - libc.memcpy(orig_func, ioctl_address.contents, 0x1000) - libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp)) - return orig_func - -libc = ctypes.CDLL(ctypes.util.find_library("libc")) -install_hook(libc.ioctl, ioctl) -from tinygrad.runtime.autogen import libc - -# adsp = ctypes.CDLL(ctypes.util.find_library("adsprpc")) -# print(adsp) - -def rpc_invoke(rpcfd, handle, method, ins=None, outs=None): - if ins or outs: - ins = ins or list() - outs = outs or list() - pra = (qcom_dsp.union_remote_arg * (len(ins) + len(outs)))() - for i,mv in enumerate(ins + outs): - if isinstance(mv, memoryview): - pra[i].buf.pv = mv_address(mv) if mv.nbytes > 0 else 0 - pra[i].buf.len = mv.nbytes - else: assert False, "not supported" - # pra = (qcom_dsp.union_remote_arg * (len(ins) + len(outs))).from_address(ctypes.addressof(pra)) - else: - pra = None - ins = ins or list() - outs = outs or list() - - sc = (method << 24) | (len(ins) << 16) | (len(outs) << 8) - return qcom_dsp.FASTRPC_IOCTL_INVOKE(rpcfd, handle=handle, sc=sc, pra=pra) - -def listner_worker(): - context = 0 - handle = 0xffffffff - msg_send = memoryview(bytearray(0x10)).cast('I') - msg_recv = memoryview(bytearray(0x10)).cast('I') - out_buf = memoryview(bytearray(0x1000)).cast('I') - in_buf = memoryview(bytearray(0x1000)).cast('I') - - prev_res = 0xffffffff - out_buf_size = 0 - - req_args = (qcom_dsp.union_remote_arg * 4)() - req_args[0].buf = qcom_dsp.struct_remote_buf(pv=mv_address(msg_send), len=0x10) - req_args[1].buf = qcom_dsp.struct_remote_buf(pv=mv_address(out_buf), len=0x1000) - req_args[2].buf = qcom_dsp.struct_remote_buf(pv=mv_address(msg_recv), len=0x10) - req_args[3].buf = qcom_dsp.struct_remote_buf(pv=mv_address(in_buf), len=0x1000) - - while True: - msg_send[0] = context - msg_send[1] = prev_res - msg_send[2] = out_buf_size - msg_send[3] = 0x1000 - - req_args[1].buf.len = out_buf_size - qcom_dsp.FASTRPC_IOCTL_INVOKE(rpcfd, handle=0x3, sc=0x04020200, pra=req_args) # listener - - context = msg_recv[0] - handle = msg_recv[1] - sc = msg_recv[2] - inbufs = (sc >> 16) & 0xff - outbufs = (sc >> 8) & 0xff - - in_args, out_args = [], [] - ptr = mv_address(in_buf) - for i in range(inbufs): - sz = to_mv(ptr, 4).cast('I')[0] - obj_ptr = round_up(ptr + 4, 8) - in_args.append(to_mv(obj_ptr, sz)) - ptr = obj_ptr + sz - - ctypes.memset(mv_address(out_buf), 0, 0x1000) - ptr_out = mv_address(out_buf) - for i in range(outbufs): - sz = to_mv(ptr, 4).cast('I')[0] - ptr += 4 - - to_mv(ptr_out, 4).cast('I')[0] = sz - obj_ptr = round_up(ptr_out + 4, 8) - - out_args.append(to_mv(obj_ptr, sz)) - ptr_out = obj_ptr + sz - - out_buf_size = ptr_out - mv_address(out_buf) - - if sc == 0x20200: # greating? - prev_res = 0 - elif sc == 0x13050100: # open - # for a in in_args: hexdump(a) - try: - fd = os.open(in_args[3].tobytes()[:-1].decode(), os.O_RDONLY) - out_args[0].cast('I')[0] = fd - prev_res = 0 - except: prev_res = 2 - elif sc == 0x9010000: # seek - res = os.lseek(in_args[0].cast('I')[0], in_args[0].cast('I')[1], in_args[0].cast('I')[2]) - prev_res = 0 if res >= 0 else res - elif sc == 0x4010200: # read - buf = os.read(in_args[0].cast('I')[0], in_args[0].cast('I')[1]) - out_args[1][:len(buf)] = buf - out_args[0].cast('I')[0] = len(buf) - out_args[0].cast('I')[1] = int(len(buf) == 0) - prev_res = 0 - elif sc == 0x3010000: # close - os.close(in_args[0].cast('I')[0]) - prev_res = 0 - elif sc == 0x1f020100: # stat - # try: - stat = os.stat(in_args[1].tobytes()[:-1].decode()) - out_stat = out_args[0].cast('Q') - out_stat[1] = stat.st_dev - out_stat[2] = stat.st_ino - out_stat[3] = stat.st_mode | (stat.st_nlink << 32) - out_stat[4] = stat.st_rdev - out_stat[5] = stat.st_size - # print(stat, stat.st_rdev) - # assert False - prev_res = 0 - # except: prev_res = 2 - elif sc == 0x2010100: - heapid = in_args[0].cast('I')[0] - lflags = in_args[0].cast('I')[1] - rflags = in_args[0].cast('I')[2] - assert rflags == 0x1000 - - # print(in_args[0]) - - # print("WOOW", in_args[0].cast('Q')[2]) - # print("WOOW2", in_args[0].cast('Q')[2]) - # print("WOOW3", in_args[0].cast('Q')[3]) - # print("WOOW3", in_args[0].cast('Q')[3]) - - vin = in_args[0].cast('Q')[2] - sz = in_args[0].cast('Q')[3] - # vin = to_mv(in_args[0].cast('Q')[2], 8).cast('Q')[0] - # sz = to_mv(in_args[0].cast('Q')[3], 8).cast('Q')[0] - - st = qcom_dsp.FASTRPC_IOCTL_MMAP(rpcfd, fd=-1, flags=rflags, vaddrin=0, size=sz) - out_args[0].cast('Q')[0] = 0 - out_args[0].cast('Q')[1] = st.vaddrout - prev_res = 0 - else: raise RuntimeError(f"Unknown {sc=:X}") - -if __name__ == "__main__": - ionfd = os.open('/dev/ion', os.O_RDONLY) - rpcfd = os.open('/dev/adsprpc-smd', os.O_RDONLY | os.O_NONBLOCK) - - with contextlib.suppress(RuntimeError, OSError): qcom_dsp.ION_IOC_FREE(ionfd, handle=0) - info = qcom_dsp.FASTRPC_IOCTL_GETINFO(rpcfd, 3) - # x = qcom_dsp.FASTRPC_IOCTL_SETMODE(rpcfd, 0, __force_as_val=True) - - # init shell? - fastrpc_shell = memoryview(bytearray(pathlib.Path('/vendor/dsp/cdsp/fastrpc_shell_3').read_bytes())) - shell_mem = qcom_dsp.ION_IOC_ALLOC(ionfd, len=round_up(fastrpc_shell.nbytes, 0x1000), align=0x1000, heap_id_mask=0x2000000, flags=0x1) - shell_mapped = qcom_dsp.ION_IOC_MAP(ionfd, handle=shell_mem.handle) - fastrpc_shell_addr = libc.mmap(0, shell_mem.len, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, shell_mapped.fd, 0) - - ctypes.memmove(fastrpc_shell_addr, mv_address(fastrpc_shell), fastrpc_shell.nbytes) - # ctypes.memset(fastrpc_shell_addr, 0x0, 0xd6000) - # print(hex(fastrpc_shell_addr)) - - ctrls = qcom_dsp.FASTRPC_IOCTL_CONTROL(rpcfd, req=0x3) - - init = qcom_dsp.FASTRPC_IOCTL_INIT(rpcfd, flags=0x1, file=fastrpc_shell_addr, filelen=fastrpc_shell.nbytes, filefd=shell_mapped.fd) - print("init shell done", shell_mapped.fd) - - # TODO: unmap here - # qcom_dsp.ION_IOC_FREE(ionfd, handle=shell_mem.handle) - - rpc_invoke(rpcfd, handle=3, method=3) - - thread = Thread(target=listner_worker) - thread.start() - - a1 = memoryview(bytearray(b'\x52\x00\x00\x00\xFF\x00\x00\x00')) - a2 = memoryview(bytearray(b"file:///libcalculator_skel.so?calculator_skel_handle_invoke&_modver=1.0&_dom=cdsp\0")) - o1 = memoryview(bytearray(0x8)) - o2 = memoryview(bytearray(0xff)) - z = rpc_invoke(rpcfd, handle=0, method=0, ins=[a1, a2], outs=[o1, o2]) - prg_handle = o1.cast('I')[0] - - # test - test = (ctypes.c_int32 * 100)() - for i in range(100): test[i] = i - print("calculator_sum") - pra = (qcom_dsp.union_remote_arg * 3)() - #arg_0 = ctypes.c_int32(100) - arg_0 = ctypes.c_int32(100) - arg_2 = ctypes.c_int64(-1) - pra[0].buf.pv = ctypes.addressof(arg_0) - pra[0].buf.len = 4 - pra[1].buf.pv = ctypes.addressof(test) - pra[1].buf.len = 0x190 - pra[2].buf.pv = ctypes.addressof(arg_2) - pra[2].buf.len = 8 - qcom_dsp.FASTRPC_IOCTL_INVOKE(rpcfd, handle=prg_handle, sc=(2<<24) | (2<<16) | (1<<8), pra=pra) - - print(arg_2.value) - print("done") - os._exit(0) diff --git a/tinygrad/extra/dsp/snpe.sh b/tinygrad/extra/dsp/snpe.sh deleted file mode 100755 index e714a471..00000000 --- a/tinygrad/extra/dsp/snpe.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash -e -echo "building" -gcc -shared -fPIC -o preload_python.so preload.c -L/usr/local/pyenv/versions/3.11.4/lib -lpython3.11 -I/usr/local/pyenv/versions/3.11.4/include/python3.11 -echo "compiled" -export LD_LIBRARY_PATH="/usr/local/pyenv/versions/3.11.4/lib;/data/snpe" -export LD_PRELOAD="$PWD/preload_python.so" -export PYTHONPATH="/data/tinygrad" -cd /data/snpe -#ADSP_LIBRARY_PATH="." strace -f -e ioctl ./snpe-net-run --container MobileNetV2.dlc --input_list hello --use_dsp -ADSP_LIBRARY_PATH="." ./snpe-net-run --container MobileNetV2.dlc --input_list hello --use_dsp - diff --git a/tinygrad/extra/dsp/snpe_logs/dlc_info_2 b/tinygrad/extra/dsp/snpe_logs/dlc_info_2 deleted file mode 100644 index 3f073a19..00000000 --- a/tinygrad/extra/dsp/snpe_logs/dlc_info_2 +++ /dev/null @@ -1,715 +0,0 @@ -DLC info for: /home/batman/xx/ml_tools/snpe/snpe-1.61.0.3358/mobilenetv2-7.dlc -Model Version: N/A -Model Copyright:N/A ------------------------------------------------------------------------------------------------------------------------------------------ -| Id | Name | Type | Inputs | Outputs | Out Dims | Runtimes | Parameters | ------------------------------------------------------------------------------------------------------------------------------------------ -| 0 | input | data | input | input | 1x224x224x3 | A D G C | input_preprocessing: passthrough | -| | | | | | | | input_type: image | -| 1 | Conv_0 | convolutional | input | 474 | 1x112x112x32 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 2 | -| | | | | | | | stride y: 2 | -| | | | | | | | num filters: 32 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | param count: 896 (0.0257%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 2 | Clip_1 | neuron | 474 | 317 | 1x112x112x32 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 3 | Conv_2 | convolutional | 317 | 477 | 1x112x112x32 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 32 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 32 | -| | | | | | | | param count: 320 (0.00917%) | -| | | | | | | | MACs per inference: 3M (1.2%) | -| 4 | Clip_3 | neuron | 477 | 320 | 1x112x112x32 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 5 | Conv_4 | convolutional | 320 | 480 | 1x112x112x16 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 16 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 528 (0.0151%) | -| | | | | | | | MACs per inference: 6M (2.13%) | -| 6 | Conv_5 | convolutional | 480 | 483 | 1x112x112x96 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 96 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 1k (0.0468%) | -| | | | | | | | MACs per inference: 19M (6.4%) | -| 7 | Clip_6 | neuron | 483 | 325 | 1x112x112x96 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 8 | Conv_7 | convolutional | 325 | 486 | 1x56x56x96 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 2 | -| | | | | | | | stride y: 2 | -| | | | | | | | num filters: 96 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 96 | -| | | | | | | | param count: 960 (0.0275%) | -| | | | | | | | MACs per inference: 2M (0.9%) | -| 9 | Clip_8 | neuron | 486 | 328 | 1x56x56x96 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 10 | Conv_9 | convolutional | 328 | 489 | 1x56x56x24 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 24 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 2k (0.0667%) | -| | | | | | | | MACs per inference: 7M (2.4%) | -| 11 | Conv_10 | convolutional | 489 | 492 | 1x56x56x144 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 144 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 3k (0.103%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 12 | Clip_11 | neuron | 492 | 333 | 1x56x56x144 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 13 | Conv_12 | convolutional | 333 | 495 | 1x56x56x144 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 144 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 144 | -| | | | | | | | param count: 1k (0.0413%) | -| | | | | | | | MACs per inference: 4M (1.35%) | -| 14 | Clip_13 | neuron | 495 | 336 | 1x56x56x144 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 15 | Conv_14 | convolutional | 336 | 498 | 1x56x56x24 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 24 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 3k (0.0998%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 16 | Add_15 | elementwise_binary_op | 489 | 339 | 1x56x56x24 | A D G C | operation: sum | -| | | | 498 | | | | MACs per inference: 75k (0.025%) | -| 17 | Conv_16 | convolutional | 339 | 501 | 1x56x56x144 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 144 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 3k (0.103%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 18 | Clip_17 | neuron | 501 | 342 | 1x56x56x144 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 19 | Conv_18 | convolutional | 342 | 504 | 1x28x28x144 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 2 | -| | | | | | | | stride y: 2 | -| | | | | | | | num filters: 144 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 144 | -| | | | | | | | param count: 1k (0.0413%) | -| | | | | | | | MACs per inference: 1M (0.338%) | -| 20 | Clip_19 | neuron | 504 | 345 | 1x28x28x144 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 21 | Conv_20 | convolutional | 345 | 507 | 1x28x28x32 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 32 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 4k (0.133%) | -| | | | | | | | MACs per inference: 3M (1.2%) | -| 22 | Conv_21 | convolutional | 507 | 510 | 1x28x28x192 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 6k (0.182%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 23 | Clip_22 | neuron | 510 | 350 | 1x28x28x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 24 | Conv_23 | convolutional | 350 | 513 | 1x28x28x192 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 192 | -| | | | | | | | param count: 1k (0.055%) | -| | | | | | | | MACs per inference: 1M (0.45%) | -| 25 | Clip_24 | neuron | 513 | 353 | 1x28x28x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 26 | Conv_25 | convolutional | 353 | 516 | 1x28x28x32 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 32 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 6k (0.177%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 27 | Add_26 | elementwise_binary_op | 507 | 356 | 1x28x28x32 | A D G C | operation: sum | -| | | | 516 | | | | MACs per inference: 25k (0.00833%) | -| 28 | Conv_27 | convolutional | 356 | 519 | 1x28x28x192 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 6k (0.182%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 29 | Clip_28 | neuron | 519 | 359 | 1x28x28x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 30 | Conv_29 | convolutional | 359 | 522 | 1x28x28x192 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 192 | -| | | | | | | | param count: 1k (0.055%) | -| | | | | | | | MACs per inference: 1M (0.45%) | -| 31 | Clip_30 | neuron | 522 | 362 | 1x28x28x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 32 | Conv_31 | convolutional | 362 | 525 | 1x28x28x32 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 32 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 6k (0.177%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 33 | Add_32 | elementwise_binary_op | 356 | 365 | 1x28x28x32 | A D G C | operation: sum | -| | | | 525 | | | | MACs per inference: 25k (0.00833%) | -| 34 | Conv_33 | convolutional | 365 | 528 | 1x28x28x192 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 6k (0.182%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 35 | Clip_34 | neuron | 528 | 368 | 1x28x28x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 36 | Conv_35 | convolutional | 368 | 531 | 1x14x14x192 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 2 | -| | | | | | | | stride y: 2 | -| | | | | | | | num filters: 192 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 192 | -| | | | | | | | param count: 1k (0.055%) | -| | | | | | | | MACs per inference: 338k (0.113%) | -| 37 | Clip_36 | neuron | 531 | 371 | 1x14x14x192 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 38 | Conv_37 | convolutional | 371 | 534 | 1x14x14x64 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 64 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 12k (0.354%) | -| | | | | | | | MACs per inference: 2M (0.8%) | -| 39 | Conv_38 | convolutional | 534 | 537 | 1x14x14x384 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.716%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 40 | Clip_39 | neuron | 537 | 376 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 41 | Conv_40 | convolutional | 376 | 540 | 1x14x14x384 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 384 | -| | | | | | | | param count: 3k (0.11%) | -| | | | | | | | MACs per inference: 677k (0.225%) | -| 42 | Clip_41 | neuron | 540 | 379 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 43 | Conv_42 | convolutional | 379 | 543 | 1x14x14x64 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 64 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.706%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 44 | Add_43 | elementwise_binary_op | 534 | 382 | 1x14x14x64 | A D G C | operation: sum | -| | | | 543 | | | | MACs per inference: 12k (0.00417%) | -| 45 | Conv_44 | convolutional | 382 | 546 | 1x14x14x384 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.716%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 46 | Clip_45 | neuron | 546 | 385 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 47 | Conv_46 | convolutional | 385 | 549 | 1x14x14x384 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 384 | -| | | | | | | | param count: 3k (0.11%) | -| | | | | | | | MACs per inference: 677k (0.225%) | -| 48 | Clip_47 | neuron | 549 | 388 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 49 | Conv_48 | convolutional | 388 | 552 | 1x14x14x64 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 64 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.706%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 50 | Add_49 | elementwise_binary_op | 382 | 391 | 1x14x14x64 | A D G C | operation: sum | -| | | | 552 | | | | MACs per inference: 12k (0.00417%) | -| 51 | Conv_50 | convolutional | 391 | 555 | 1x14x14x384 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.716%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 52 | Clip_51 | neuron | 555 | 394 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 53 | Conv_52 | convolutional | 394 | 558 | 1x14x14x384 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 384 | -| | | | | | | | param count: 3k (0.11%) | -| | | | | | | | MACs per inference: 677k (0.225%) | -| 54 | Clip_53 | neuron | 558 | 397 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 55 | Conv_54 | convolutional | 397 | 561 | 1x14x14x64 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 64 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.706%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 56 | Add_55 | elementwise_binary_op | 391 | 400 | 1x14x14x64 | A D G C | operation: sum | -| | | | 561 | | | | MACs per inference: 12k (0.00417%) | -| 57 | Conv_56 | convolutional | 400 | 564 | 1x14x14x384 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 24k (0.716%) | -| | | | | | | | MACs per inference: 4M (1.6%) | -| 58 | Clip_57 | neuron | 564 | 403 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 59 | Conv_58 | convolutional | 403 | 567 | 1x14x14x384 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 384 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 384 | -| | | | | | | | param count: 3k (0.11%) | -| | | | | | | | MACs per inference: 677k (0.225%) | -| 60 | Clip_59 | neuron | 567 | 406 | 1x14x14x384 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 61 | Conv_60 | convolutional | 406 | 570 | 1x14x14x96 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 96 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 36k (1.06%) | -| | | | | | | | MACs per inference: 7M (2.4%) | -| 62 | Conv_61 | convolutional | 570 | 573 | 1x14x14x576 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 55k (1.6%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 63 | Clip_62 | neuron | 573 | 411 | 1x14x14x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 64 | Conv_63 | convolutional | 411 | 576 | 1x14x14x576 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 576 | -| | | | | | | | param count: 5k (0.165%) | -| | | | | | | | MACs per inference: 1M (0.338%) | -| 65 | Clip_64 | neuron | 576 | 414 | 1x14x14x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 66 | Conv_65 | convolutional | 414 | 579 | 1x14x14x96 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 96 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 55k (1.59%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 67 | Add_66 | elementwise_binary_op | 570 | 417 | 1x14x14x96 | A D G C | operation: sum | -| | | | 579 | | | | MACs per inference: 18k (0.00625%) | -| 68 | Conv_67 | convolutional | 417 | 582 | 1x14x14x576 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 55k (1.6%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 69 | Clip_68 | neuron | 582 | 420 | 1x14x14x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 70 | Conv_69 | convolutional | 420 | 585 | 1x14x14x576 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 576 | -| | | | | | | | param count: 5k (0.165%) | -| | | | | | | | MACs per inference: 1M (0.338%) | -| 71 | Clip_70 | neuron | 585 | 423 | 1x14x14x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 72 | Conv_71 | convolutional | 423 | 588 | 1x14x14x96 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 96 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 55k (1.59%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 73 | Add_72 | elementwise_binary_op | 417 | 426 | 1x14x14x96 | A D G C | operation: sum | -| | | | 588 | | | | MACs per inference: 18k (0.00625%) | -| 74 | Conv_73 | convolutional | 426 | 591 | 1x14x14x576 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 55k (1.6%) | -| | | | | | | | MACs per inference: 10M (3.6%) | -| 75 | Clip_74 | neuron | 591 | 429 | 1x14x14x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 76 | Conv_75 | convolutional | 429 | 594 | 1x7x7x576 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 2 | -| | | | | | | | stride y: 2 | -| | | | | | | | num filters: 576 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 576 | -| | | | | | | | param count: 5k (0.165%) | -| | | | | | | | MACs per inference: 254k (0.0844%) | -| 77 | Clip_76 | neuron | 594 | 432 | 1x7x7x576 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 78 | Conv_77 | convolutional | 432 | 597 | 1x7x7x160 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 160 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 92k (2.65%) | -| | | | | | | | MACs per inference: 4M (1.5%) | -| 79 | Conv_78 | convolutional | 597 | 600 | 1x7x7x960 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 154k (4.43%) | -| | | | | | | | MACs per inference: 7M (2.5%) | -| 80 | Clip_79 | neuron | 600 | 437 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 81 | Conv_80 | convolutional | 437 | 603 | 1x7x7x960 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 960 | -| | | | | | | | param count: 9k (0.275%) | -| | | | | | | | MACs per inference: 423k (0.141%) | -| 82 | Clip_81 | neuron | 603 | 440 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 83 | Conv_82 | convolutional | 440 | 606 | 1x7x7x160 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 160 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 153k (4.41%) | -| | | | | | | | MACs per inference: 7M (2.5%) | -| 84 | Add_83 | elementwise_binary_op | 597 | 443 | 1x7x7x160 | A D G C | operation: sum | -| | | | 606 | | | | MACs per inference: 7k (0.0026%) | -| 85 | Conv_84 | convolutional | 443 | 609 | 1x7x7x960 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 154k (4.43%) | -| | | | | | | | MACs per inference: 7M (2.5%) | -| 86 | Clip_85 | neuron | 609 | 446 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 87 | Conv_86 | convolutional | 446 | 612 | 1x7x7x960 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 960 | -| | | | | | | | param count: 9k (0.275%) | -| | | | | | | | MACs per inference: 423k (0.141%) | -| 88 | Clip_87 | neuron | 612 | 449 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 89 | Conv_88 | convolutional | 449 | 615 | 1x7x7x160 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 160 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 153k (4.41%) | -| | | | | | | | MACs per inference: 7M (2.5%) | -| 90 | Add_89 | elementwise_binary_op | 443 | 452 | 1x7x7x160 | A D G C | operation: sum | -| | | | 615 | | | | MACs per inference: 7k (0.0026%) | -| 91 | Conv_90 | convolutional | 452 | 618 | 1x7x7x960 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 154k (4.43%) | -| | | | | | | | MACs per inference: 7M (2.5%) | -| 92 | Clip_91 | neuron | 618 | 455 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 93 | Conv_92 | convolutional | 455 | 621 | 1x7x7x960 | A D G C | padding x: 1 | -| | | | | | | | padding y: 1 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 960 | -| | | | | | | | kernel: 3x3 | -| | | | | | | | groups: 960 | -| | | | | | | | param count: 9k (0.275%) | -| | | | | | | | MACs per inference: 423k (0.141%) | -| 94 | Clip_93 | neuron | 621 | 458 | 1x7x7x960 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 95 | Conv_94 | convolutional | 458 | 624 | 1x7x7x320 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 320 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 307k (8.82%) | -| | | | | | | | MACs per inference: 15M (5%) | -| 96 | Conv_95 | convolutional | 624 | 627 | 1x7x7x1280 | A D G C | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | padding mode: zero | -| | | | | | | | stride x: 1 | -| | | | | | | | stride y: 1 | -| | | | | | | | num filters: 1280 | -| | | | | | | | kernel: 1x1 | -| | | | | | | | param count: 410k (11.8%) | -| | | | | | | | MACs per inference: 20M (6.67%) | -| 97 | Clip_96 | neuron | 627 | 463 | 1x7x7x1280 | A D G C | a: 0 | -| | | | | | | | b: 0 | -| | | | | | | | min_clamp: 0 | -| | | | | | | | max_clamp: 6 | -| | | | | | | | func: relu_min_max | -| 98 | GlobalAveragePool_97 | pooling | 463 | 464 | 1x1x1x1280 | A D G C | pool size x: 7 | -| | | | | | | | pool size y: 7 | -| | | | | | | | stride x: 7 | -| | | | | | | | stride y: 7 | -| | | | | | | | padding x: 0 | -| | | | | | | | padding y: 0 | -| | | | | | | | pool_type: POOL_AVG | -| | | | | | | | MACs per inference: 62k (0.0208%) | -| 99 | 464.ncs | permute | 464 | 464.ncs | 1x1280x1x1 | A D G C | permute_order: [0, 3, 1, 2] | -| 100 | Gemm_104 | fully_connected | 464.ncs | output | 1x1000 | A D G C | param count: 1M (36.7%) | -| | | | | | | | MACs per inference: 1M (0.425%) | ------------------------------------------------------------------------------------------------------------------------------------------ -Note: The supported runtimes column assumes a processor target of Snapdragon 835 (8998) -Key : A:AIP - D:DSP - G:GPU - C:CPU - -Total parameters: 3487816 (13 MB assuming single precision float) -Total MACs per inference: 301M (100%) -Converter command: snpe-onnx-to-dlc adjust_nms_features_dims=False align_matmul_ranks=True copyright_file=None custom_op_config_paths=None debug=-1 disable_batchnorm_folding=False disable_chaining_eltwise_ops=False dry_run=None dumpIR=False dump_inferred_model=False dump_value_info=False enable_strict_validation=False extract_color_transform=False force_prune_cast_ops=True handle_gather_negative_indices=False inject_cast_for_gather=False input_dim=[['input', '1,3,224,224']] input_dtype=[] input_encoding=[] input_layout=[] input_type=[['input', 'image']] keep_disconnected_nodes=False keep_quant_nodes=False match_caffe_ssd_to_tf=False model_version=None no_simplification=False out_names=['output'] perform_axes_to_spatial_first_order=True prepare_inputs_as_params=True preprocess_lstm_ops=False preprocess_roi_pool_inputs=False quantization_overrides= squash_box_decoder=False unroll_lstm_time_steps=False use_convert_quantization_nodes=True validation_target=[] -Quantizer command: N/A -DLC created with converter version: 1.61.0.3358 -Layers used by DLC: CONVOLUTIONAL, DATA, ELEMENTWISE_BINARY_OP_SUM, FULLY_CONNECTED, NEURON_RELU_MIN_MAX, PERMUTE, POOLING -Est. Steady-State Memory Needed to Run: 164.3 MiB ------------------------------------------------------------------------------------------------------------------------------------------ - diff --git a/tinygrad/extra/dsp/snpe_logs/high_perf_2 b/tinygrad/extra/dsp/snpe_logs/high_perf_2 deleted file mode 100644 index b21ec979..00000000 --- a/tinygrad/extra/dsp/snpe_logs/high_perf_2 +++ /dev/null @@ -1,131 +0,0 @@ -Log File Created: Tue Mar 18 01:33:12 2025 -Time Scale: 1e-06 -Epoch Timestamp: 1742286792883569 Steady Clock Timestamp: 75586845756 -Software library version: 1.61.0.3358 - -Dnn Runtime Load/Deserialize/Create/De-Init Statistics: --------------------------------------------------- -Load: 333 us -Deserialize: 32452 us -Create: 143084 us - -Init: 178071 us -De-Init: 16710 us - -Create Network(s): 86850 us -RPC Init Time: 43213 us -Snpe Accelerator Init Time: 42154 us -Accelerator Init Time: 39189 us - -Average SNPE Statistics: ------------------------------- -Total Inference Time: 11868 us -Forward Propagate Time: 11816 us -RPC Execute Time: 9810 us -Snpe Accelerator Time: 9129 us -Accelerator Time: 8701 us -Misc Accelerator Time: 10 us - -Layer Times: ---------------- -0: 42 us : DSP -1: 0 us : DSP -2: 254 us : DSP -3: 0 us : DSP -4: 153 us : DSP -5: 295 us : DSP -6: 0 us : DSP -7: 287 us : DSP -8: 0 us : DSP -9: 162 us : DSP -10: 210 us : DSP -11: 0 us : DSP -12: 138 us : DSP -13: 0 us : DSP -14: 176 us : DSP -15: 293 us : DSP -16: 60 us : DSP -17: 0 us : DSP -18: 157 us : DSP -19: 0 us : DSP -20: 112 us : DSP -21: 134 us : DSP -22: 0 us : DSP -23: 81 us : DSP -24: 0 us : DSP -25: 104 us : DSP -26: 130 us : DSP -27: 37 us : DSP -28: 0 us : DSP -29: 81 us : DSP -30: 0 us : DSP -31: 87 us : DSP -32: 124 us : DSP -33: 30 us : DSP -34: 0 us : DSP -35: 87 us : DSP -36: 0 us : DSP -37: 63 us : DSP -38: 74 us : DSP -39: 0 us : DSP -40: 102 us : DSP -41: 0 us : DSP -42: 82 us : DSP -43: 95 us : DSP -44: 29 us : DSP -45: 0 us : DSP -46: 112 us : DSP -47: 0 us : DSP -48: 88 us : DSP -49: 96 us : DSP -50: 25 us : DSP -51: 0 us : DSP -52: 103 us : DSP -53: 0 us : DSP -54: 80 us : DSP -55: 100 us : DSP -56: 26 us : DSP -57: 0 us : DSP -58: 102 us : DSP -59: 0 us : DSP -60: 85 us : DSP -61: 129 us : DSP -62: 0 us : DSP -63: 155 us : DSP -64: 0 us : DSP -65: 113 us : DSP -66: 194 us : DSP -67: 34 us : DSP -68: 0 us : DSP -69: 157 us : DSP -70: 0 us : DSP -71: 120 us : DSP -72: 198 us : DSP -73: 34 us : DSP -74: 0 us : DSP -75: 155 us : DSP -76: 0 us : DSP -77: 101 us : DSP -78: 121 us : DSP -79: 0 us : DSP -80: 256 us : DSP -81: 0 us : DSP -82: 134 us : DSP -83: 159 us : DSP -84: 31 us : DSP -85: 0 us : DSP -86: 199 us : DSP -87: 0 us : DSP -88: 142 us : DSP -89: 152 us : DSP -90: 26 us : DSP -91: 0 us : DSP -92: 202 us : DSP -93: 0 us : DSP -94: 143 us : DSP -95: 278 us : DSP -96: 0 us : DSP -97: 316 us : DSP -98: 40 us : DSP -99: 12 us : DSP -100: 199 us : DSP diff --git a/tinygrad/extra/dsp/snpe_logs/parse.py b/tinygrad/extra/dsp/snpe_logs/parse.py deleted file mode 100644 index b3d3513b..00000000 --- a/tinygrad/extra/dsp/snpe_logs/parse.py +++ /dev/null @@ -1,21 +0,0 @@ -di = open("dlc_info_2").read().split("\n") -layers = {} -for l in di: - if not l.startswith("| "): continue - if l.startswith("| |"): continue - ll = [x.strip() for x in l.split("|")] - if ll[1] == "Id": continue - layers[int(ll[1])] = (ll[2], ll[6]) -hp = open("high_perf_2").read().split("Layer Times:")[1].strip().split("\n")[2:] -sl = 1 -tms = 0 -for l in hp: - kk, tm, _ = l.split(" ", 2) - tm = int(tm) - lnum = int(kk.strip(":")) - if int(tm) != 0: - print(f"{sl:2d} {tm:4d} us {layers[lnum]}") - tms += tm - sl += 1 -print(f"total time, {tms/1000:.2f} ms") - diff --git a/tinygrad/extra/dump_cache.py b/tinygrad/extra/dump_cache.py deleted file mode 100644 index 325d2bd2..00000000 --- a/tinygrad/extra/dump_cache.py +++ /dev/null @@ -1,21 +0,0 @@ -import sys, sqlite3, pickle -from tinygrad.helpers import CACHEDB - -if __name__ == "__main__": - fn = sys.argv[1] if len(sys.argv) > 1 else CACHEDB - conn = sqlite3.connect(fn) - cur = conn.cursor() - cur.execute("SELECT name FROM sqlite_master WHERE type='table'") - for f in cur.fetchall(): - table = f[0] - cur2 = conn.cursor() - cur2.execute(f"SELECT COUNT(*) FROM {table}") - cnt = cur2.fetchone()[0] - print(f"{table:20s} : {cnt}") - - cur3 = conn.cursor() - cur3.execute(f"SELECT * FROM {table} LIMIT 10") - for f in cur3.fetchall(): - v = pickle.loads(f[-1]) - print(" ", len(f[0]) if isinstance(f[0], str) else f[0], f[1:-1], str(v)[0:50]) - #print(f"{len(k):10d}, {sk} -> {v}") diff --git a/tinygrad/extra/export_model.py b/tinygrad/extra/export_model.py deleted file mode 100644 index 2b2aa1dc..00000000 --- a/tinygrad/extra/export_model.py +++ /dev/null @@ -1,299 +0,0 @@ -from typing import Tuple, Dict, List, Optional -from tinygrad.dtype import DType -from tinygrad.renderer import ProgramSpec -from tinygrad.tensor import Device, Tensor -from tinygrad.engine.jit import TinyJit -from tinygrad.nn.state import get_state_dict -from tinygrad.helpers import Context -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import Ops -import json -from collections import OrderedDict - -EXPORT_SUPPORTED_DEVICE = ["WEBGPU", "CPU", "CUDA", "GPU"] - -def compile_net(run:TinyJit, special_names:Dict[int,str]) -> Tuple[Dict[str,str],List[Tuple[str,List[str],List[int]]],Dict[str,Tuple[int,DType,int]],Dict[str,Tensor]]: - functions, bufs, bufs_to_save, statements, bufnum = {}, {}, {}, [], 0 - for ji in run.jit_cache: - fxn: ProgramSpec = ji.prg.p - functions[fxn.function_name] = fxn.src # NOTE: this assumes all with the same name are the same - cargs = [] - for i,arg in enumerate(ji.bufs): - key = id(arg) - if key not in bufs: - if key in special_names: - bufs[key] = (special_names[key], arg.size*arg.dtype.itemsize, arg.dtype, key) - else: - bufs[key] = (f"buf_{bufnum}", arg.size*arg.dtype.itemsize, arg.dtype, key) - bufnum += 1 - if i > 0: bufs_to_save[bufs[key][0]] = arg # if first usage of a buffer is not an output, and it's not a special name - cargs.append(bufs[key][0]) - cargs += [var for var in fxn.vars if getattr(var, "op", None) is Ops.DEFINE_VAR] # symbolic vars; is it necessary or sufficient to check for DEFINE_VAR? - statements.append((fxn.function_name, cargs, fxn.global_size, fxn.local_size)) - - return functions, statements, {name:(size, dtype, key) for (name,size,dtype,key) in bufs.values()}, bufs_to_save - -def jit_model(model, *args) -> Tuple[TinyJit,Dict[int,str]]: - assert hasattr(model, "forward") or callable(model), "model needs a forward function" - @TinyJit - def run(*x): - out = model.forward(*x) if hasattr(model, "forward") else model(*x) - assert isinstance(out, (tuple, list, Tensor)), "model output must be a Tensor, tuple, or a list of Tensors for export" - out = [out] if isinstance(out, Tensor) else out - return [o.realize() for o in out] - - # twice to run the JIT - for _ in range(2): the_output = run(*args) - special_names = {} - - # hack to put the inputs back - for (j,i),idx in run.input_replace.items(): - realized_input = args[idx].uop.base.realized - run.jit_cache[j].bufs[i] = realized_input - special_names[id(realized_input)] = f'input{idx}' - - # TODO: fetch this from the jit in self.input_replace and self.ret (hint: use get_parameters on self.ret) - for i, output in enumerate(the_output): - special_names[id(output.uop.base.realized)] = f'output{i}' - return run, special_names - -def export_model_clang(functions:Dict[str,str], statements:Dict[str,Tuple[str,int,int]], bufs:Dict[str,Tuple[str,int,int]], - bufs_to_save:Dict[str,Tensor], input_names:List[str], output_names:List[str], weight_names={}, model_name="model", symbolic_vars={}, wasm=False) -> str: - headers = ["#include "] - cprog = list(functions.values()) - dtype_map = {dtypes.int: "int", dtypes.float: "float", dtypes.uchar: "unsigned char", dtypes.char: "signed char", dtypes.half: "__fp16", dtypes.uint: "unsigned int"} - inputs = [(name, dtype_map[bufs[name][1]], bufs[name][0]) for name in input_names + list(symbolic_vars.values())] - outputs = [(name, dtype_map[bufs[name][1]], bufs[name][0]) for name in output_names] - forward_args = ",".join(f"{dtype}{'*' if name not in symbolic_vars.values() else ''} {name}" for name,dtype,_ in (outputs+inputs if wasm else inputs+outputs)) - - if not wasm: - for name,cl in bufs_to_save.items(): - weight = ''.join(["\\x%02X"%x for x in bytes(cl._buf)]) - cprog.append(f"unsigned char {name}_data[] = \"{weight}\";") - cprog += [f"{dtype_map[dtype]} {name}[{len}];" if name not in bufs_to_save else f"{dtype_map[dtype]} *{name} = ({dtype_map[dtype]} *){name}_data;" for name,(len,dtype,_key) in bufs.items() if name not in input_names+output_names] - cprog += [f"void net({forward_args}) {{"] + [f"{name}({', '.join(args)});" for (name, args, _global_size, _local_size) in statements] + ["}"] - return '\n'.join(headers + cprog) - else: - if bufs_to_save: - headers += ["#include "] - bufs_to_save = {k:v for k,v in bufs.items() if v[2] in weight_names} # causes random seeds to be set as zeroes, not exported as a model weight - buf_to_name = OrderedDict((buf_name, {"name": weight_names[data[2]], "idx": i}) for i, (buf_name, data) in enumerate(bufs_to_save.items())) - cprog.append(f"void* bufs[{len(buf_to_name)}];") - cprog.append(f"""void set_buf(size_t index, void* ptr) {{\n bufs[index] = ptr;\n}}""") - - for name in set(bufs.keys()) - set(bufs_to_save.keys()) - set(input_names + output_names): - n_bytes, dtype, _ = bufs[name] - cprog += [f"{dtype_map[dtype]} {name}[{n_bytes // dtype.itemsize}];"] - - cprog += [f"void net({forward_args})"] + ["{"] - get_weight_ptr = lambda x: f"({dtype_map[bufs_to_save[x][1]]} *)bufs[{buf_to_name[x]['idx']}]" if x in bufs_to_save else x - cprog += [f" {name}({', '.join(map(get_weight_ptr, args))});" for (name, args, _global_size, _local_size) in statements] + ["}"] - weightMapping = "" if not bufs_to_save else f"""\nconst weightNames = [{", ".join([f'"{weight_name}"' for weight_name in [v["name"] for v in buf_to_name.values()]])}]; -const {model_name}_name_to_id = Object.fromEntries(weightNames.map((name, index) => [name, index]));\n""" - top = f"""import {model_name}Module from './{model_name}.js'{weightMapping}""" - whitespace = "\n " - js_wrapper = f"""{top}\nvar {model_name} = async function() {{ - const wasm = await {model_name}Module(); - {whitespace.join(f"const {name}Ptr = wasm._malloc({n_bytes});" for name, _, n_bytes in outputs+inputs if name not in symbolic_vars.values())} - return {{ - run: ({",".join(name for name,_,_ in inputs)}) => {{ - {(whitespace + " ").join(f"wasm.HEAPU8.set({name}, {name}Ptr);" for name,_,_ in inputs if name not in symbolic_vars.values())} - wasm._net({", ".join(f"{name}{'Ptr' if name not in symbolic_vars.values() else ''}" for name,_,_ in outputs+inputs)}); - {(whitespace + " ").join(f"const {name} = wasm.HEAPU8.slice({name}Ptr, {name}Ptr + {n_bytes});" for name,_,n_bytes in outputs)} - return [{", ".join(f"{name}" for name,_,_ in outputs)}]; - }}, - wasm: wasm - }} -}}\nexport {{ {model_name}, {model_name}_name_to_id }};""" - - return '\n'.join(headers + cprog), js_wrapper - -def dtype_to_js_type(dtype: DType) -> str: - return f"{'Uint' if dtype in dtypes.uints else 'Int' if (dtype in dtypes.sints or dtype == dtypes.bool) else 'Float'}{8*dtype.itemsize}Array" - -def export_model_webgpu(functions, statements, bufs, weight_names, input_names, output_names, model_name, symbolic_vars={}, stream_weights=False) -> Tuple[str,int,int]: - kernel_code = '\n\n'.join([f"const {key} = `{code.replace(key, 'main')}`;" for key, code in functions.items()]) - kernel_names = ', '.join([name for (name, _, _, _) in statements]) - input_names += list(symbolic_vars.values()) - input_buffer_types = [dtype_to_js_type(bufs[inp_name][1]) for inp_name in input_names] - output_buffer_types = [dtype_to_js_type(bufs[out_name][1]) for out_name in output_names] - - buf_type = lambda x: "uniform" if x in set(symbolic_vars.values()) else "storage" - create_bind_group_layouts = ",".join([ - "device.createBindGroupLayout({{entries: [{{binding: 0, visibility: GPUShaderStage.COMPUTE, buffer: {{ type: 'uniform' }}}}, {}]}})".format( - ",".join([f"{{binding: {argIdx+1}, visibility: GPUShaderStage.COMPUTE, buffer: {{ type: '{buf_type(argName)}' }} }}" for argIdx, argName in enumerate(args)]) - ) - for _, (_, args, _, _) in enumerate(statements) - ]) - layouts = f"const layouts=[{create_bind_group_layouts}]" - kernel_calls = '\n '.join([f"addComputePass(device, commandEncoder, pipelines[{i}], layouts[{i}], infinityBuf, [{', '.join(args)}], [{', '.join(str(x) for x in global_size)}]);" for i, (_name, args, global_size, _local_size) in enumerate(statements) ]) - - buf_type = lambda x: "createUniformBuf" if x in set(uop.arg[0] for uop in symbolic_vars) else "createEmptyBuf" - map_to_external_weight = lambda _key: f"state_dict['{weight_names[_key]}']" if stream_weights else f"getTensorBuffer(safetensor, metadata['{weight_names[_key]}'])" - _bufs = '\n '.join([f"const {name} = " + (f"{buf_type(_key)}(device, {size});" if _key not in weight_names else f"createWeightBuf(device, {size}, {map_to_external_weight(_key)})") + ";" for name,(size,dtype,_key) in bufs.items()]) - gpu_write_bufs = '\n '.join([f"const gpuWriteBuffer{i} = device.createBuffer({{size:{input_name}.size, usage: GPUBufferUsage.COPY_SRC | GPUBufferUsage.MAP_WRITE }});" for i,input_name in enumerate(input_names)]) - input_writers = '\n '.join([f"await gpuWriteBuffer{i}.mapAsync(GPUMapMode.WRITE);\n new {input_buffer_types[i]}(gpuWriteBuffer{i}.getMappedRange()).set(" + f'_{inp_name});' + f"\n gpuWriteBuffer{i}.unmap();\n commandEncoder.copyBufferToBuffer(gpuWriteBuffer{i}, 0, {inp_name}, 0, gpuWriteBuffer{i}.size);" for i,inp_name in enumerate(input_names)]) - gpu_read_bufs = '\n '.join([f"const gpuReadBuffer{i} = device.createBuffer({{size:{output_name}.size, usage: GPUBufferUsage.COPY_DST | GPUBufferUsage.MAP_READ }});" for i,output_name in enumerate(output_names)]) - outbuf_copies = '\n '.join([f"commandEncoder.copyBufferToBuffer({output_name}, 0, gpuReadBuffer{i}, 0, output{i}.size);" for i,output_name in enumerate(output_names)]) - output_readers = '\n '.join([f"await gpuReadBuffer{i}.mapAsync(GPUMapMode.READ);\n const resultBuffer{i} = new {output_buffer_types[i]}(gpuReadBuffer{i}.size/{bufs[output_names[i]][1].itemsize});\n resultBuffer{i}.set(new {output_buffer_types[i]}(gpuReadBuffer{i}.getMappedRange()));\n gpuReadBuffer{i}.unmap();" for i in range(len(output_names))]) - output_return = '[{}]'.format(",".join([f'resultBuffer{i}' for i in range(len(output_names))])) - getTensorMetadata = f"""\nconst getTensorMetadata = (safetensorBuffer) => {{ - const metadataLength = Number(new DataView(safetensorBuffer.buffer).getBigUint64(0, true)); - const metadata = JSON.parse(new TextDecoder("utf8").decode(safetensorBuffer.subarray(8, 8 + metadataLength))); - return Object.fromEntries(Object.entries(metadata).filter(([k, v]) => k !== "__metadata__").map(([k, v]) => [k, {{...v, data_offsets: v.data_offsets.map(x => 8 + metadataLength + x)}}])); -}};\n""" if not stream_weights else "" - return f""" -const {model_name} = (() => {{ -const getTensorBuffer = (safetensorBuffer, tensorMetadata) => {{ - return safetensorBuffer.subarray(...tensorMetadata.data_offsets); -}}; -{getTensorMetadata} -const createEmptyBuf = (device, size) => {{ - return device.createBuffer({{size, usage: GPUBufferUsage.STORAGE | GPUBufferUsage.COPY_SRC | GPUBufferUsage.COPY_DST }}); -}}; - -const createUniformBuf = (device, size) => {{ - return device.createBuffer({{size, usage: GPUBufferUsage.UNIFORM | GPUBufferUsage.COPY_DST}}) -}} - -const createInfinityUniformBuf = (device) => {{ - const size = 4; - const buf = device.createBuffer({{ - mappedAtCreation: true, - size, - usage: GPUBufferUsage.UNIFORM | GPUBufferUsage.COPY_SRC | GPUBufferUsage.COPY_DST - }}); - new Float32Array(buf.getMappedRange())[0] = Infinity; - buf.unmap(); - return buf; -}}; - -const createWeightBuf = (device, size, data) => {{ - const buf = device.createBuffer({{ size, usage: GPUBufferUsage.STORAGE{" | GPUBufferUsage.COPY_DST" if stream_weights else ", mappedAtCreation: true"} }}); - {"data.bytes = buf;" if stream_weights else "new Uint8Array(buf.getMappedRange()).set(data); buf.unmap();"} - return buf; -}}; - -const addComputePass = (device, commandEncoder, pipeline, layout, infinityUniformBuf, bufs, workgroup) => {{ - const bindGroup = device.createBindGroup({{ - layout: layout, - entries: [ - {{ binding: 0, resource: {{ buffer: infinityUniformBuf }} }}, - ...bufs.map((buffer, index) => ({{ binding: index + 1, resource: {{ buffer }} }})) - ] - }}); - - const passEncoder = commandEncoder.beginComputePass(); - passEncoder.setPipeline(pipeline); - passEncoder.setBindGroup(0, bindGroup); - passEncoder.dispatchWorkgroups(...workgroup); - passEncoder.end(); -}}; - -{kernel_code} - -const setupNet = async (device, {"state_dict" if stream_weights else "safetensor"}) => {{ - {"const metadata = getTensorMetadata(safetensor);" if not stream_weights else ""} - const infinityBuf = createInfinityUniformBuf(device); - - {layouts} - - {_bufs} - - {gpu_write_bufs} - - {gpu_read_bufs} - - const kernels = [{kernel_names}]; - const pipelines = await Promise.all(kernels.map(async (name, i) => {{ - return await device.createComputePipelineAsync({{ - layout: device.createPipelineLayout({{ - bindGroupLayouts: [layouts[i]], - }}), - compute: {{ - module: device.createShaderModule({{ - code: name, - }}), - entryPoint: "main", - }}, - }}); - }})) - - return async ({",".join([f"_{input_name}" for input_name in input_names])}) => {{ - const commandEncoder = device.createCommandEncoder(); - {input_writers} - {kernel_calls} - {outbuf_copies} - const gpuCommands = commandEncoder.finish(); - device.queue.submit([gpuCommands]); - - {output_readers} - return {output_return}; - }} -}} -const load = async (device, weight_path) => {{ return await fetch(weight_path).then(x => x.arrayBuffer()).then(x => setupNet(device, new Uint8Array(x))); }} -return {{ load, setupNet }}; -}})(); -export default {model_name}; -""" - -def export_model(model, target:str, *inputs, model_name: Optional[str] = "model", stream_weights=False): - assert Device.DEFAULT in EXPORT_SUPPORTED_DEVICE, f"only {', '.join(EXPORT_SUPPORTED_DEVICE)} are supported" - with Context(JIT=2): run,special_names = jit_model(model, *inputs) - functions, statements, bufs, bufs_to_save = compile_net(run, special_names) - state = get_state_dict(model) - weight_names = {id(x.uop.base.realized): name for name, x in state.items()} - input_names = [name for _,name in special_names.items() if "input" in name] - output_names = [name for _,name in special_names.items() if "output" in name] - - # handle symbolic variables; TODO: refactor to fix some of this stuff upstream in tinygrad - symbolic_vars = OrderedDict() - for i, (_, args, global_size, _) in enumerate(statements): - for j, var in enumerate(args): - if getattr(var, "op", None) is Ops.DEFINE_VAR and isinstance(getattr(var, "arg", None), tuple) and isinstance(var.arg[0], str): - if var not in symbolic_vars: - symbolic_vars[var] = var.arg[0] - bufs[symbolic_vars[var]] = (var.dtype.itemsize, var.dtype, symbolic_vars[var]) - statements[i][1][j] = symbolic_vars[var] - - if global_size: - for j, dim in enumerate(global_size): - if getattr(dim, "op", None) is Ops.ADD and len(dim.src) == 2 and {dim.src[0].op, dim.src[1].op} == {Ops.DEFINE_VAR, Ops.CONST}: - name, val = dim.src if dim.src[1].op is Ops.CONST else reversed(dim.src) - global_size[j] = f"_{name.arg[0]}[0] + {val.arg}" - - prg = "" - if target == "clang": - prg = export_model_clang(functions, statements, bufs, bufs_to_save, input_names, output_names) - elif target == "wasm": - return export_model_clang(functions, statements, bufs, bufs_to_save, input_names, output_names, weight_names, model_name, symbolic_vars, wasm=True) - elif target == "webgpu": - prg = export_model_webgpu(functions, statements, bufs, weight_names, input_names, output_names, model_name, symbolic_vars, stream_weights) - else: - prg = json.dumps({ - "backend": Device.DEFAULT, - "inputs": [{ - "size": bufs[name][0], - "dtype": bufs[name][1].name - } for name in input_names], - "outputs": [{ - "size": bufs[name][0], - "dtype": bufs[name][1].name - } for name in output_names], - "functions": functions, - "statements": [{ - "kernel": kernel, - "args": args, - "global_size": global_size, - "local_size": local_size - } for (kernel, args, global_size, local_size) in statements], - "buffers": { - name: { - "size": size, - "dtype": dtype.name, - "id": weight_names[_key] if _key in weight_names else "" - } for name, (size,dtype,_key) in bufs.items() if name not in ["input", "outputs"] - } - }) - - return prg, {input:bufs[input][0] for input in input_names}, {output:bufs[output][0] for output in output_names}, state diff --git a/tinygrad/extra/f16_decompress.py b/tinygrad/extra/f16_decompress.py deleted file mode 100644 index 26bad9b8..00000000 --- a/tinygrad/extra/f16_decompress.py +++ /dev/null @@ -1,16 +0,0 @@ -from tinygrad import Tensor - -def bit_extract(x: Tensor, e: int, s: int) -> Tensor: - mask = (1 << (e - s + 1)) - 1 - return (x >> s) & mask - -def u16_to_f16(x: Tensor) -> Tensor: - sign = bit_extract(x, 15, 15).float() - exponent = bit_extract(x, 14, 10).float() - fraction = bit_extract(x, 9, 0).float() - return sign.where(-1, 1) * exponent.where((exponent - 15.0).exp2() * (1 + fraction / 1024.0), 6.103515625e-5 * (fraction / 1024.0)) - -def u32_to_f16(oo: Tensor) -> Tensor: - f1 = u16_to_f16(oo>>16) - f2 = u16_to_f16(oo&0xFFFF) - return Tensor.cat(f2.reshape(-1, 1), f1.reshape(-1, 1), dim=1).flatten() diff --git a/tinygrad/extra/gemm/.gitignore b/tinygrad/extra/gemm/.gitignore deleted file mode 100644 index 33032670..00000000 --- a/tinygrad/extra/gemm/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*.s -*.ll -fp32_sgemm_amd diff --git a/tinygrad/extra/gemm/amd_matmul.py b/tinygrad/extra/gemm/amd_matmul.py deleted file mode 100644 index c1d16cff..00000000 --- a/tinygrad/extra/gemm/amd_matmul.py +++ /dev/null @@ -1,96 +0,0 @@ -# kernel8_batched_gmem.s from https://seb-v.github.io/optimization/update/2025/01/20/Fast-GPU-Matrix-multiplication.html -import pathlib -import numpy as np -from dataclasses import replace -from tinygrad import Tensor, Device, Context -from tinygrad.helpers import getenv -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad.engine.realize import CompiledRunner, ExecItem -from tinygrad.uop.ops import graph_rewrite, PatternMatcher, UPat, Ops, UOp - -# TODO: on METAL for `DEBUG=4 python3 extra/gemm/amd_matmul.py` -# * fix load grouping (like float4). idk why it's not working, need new devectorizer (this is a Monday project) -# * DONE - remove extra barrier -# * DONE (moved Ops.ADD) - fix load order to be in order (the +0 one is last!) -# * explore async (fast) global load -> local store -# * why is TC=3 broken for 4096x4096? -# * write syntactic sugar for these local additions + use it in tensor core kernel.py - -N = 4096 -LN = 16 -run_count = 5 - -from tinygrad.shape.shapetracker import ShapeTracker, View -def transform_load(ctx:tuple[Kernel, set[UOp]], x:UOp): - if x.src[0].op is not Ops.DEFINE_GLOBAL: return None - if x in ctx[1]: return None - print(ctx[0].colored_shape()) - ctx[1].add(x) - input_st: ShapeTracker = x.src[1].arg - #strides = input_st.real_strides() - #strides = (0,0)+strides[2:] - if input_st.real_strides()[2] == 0: - perm = (0,1,5,3,4,2) - strides = (0,0,LN*4,4,0,0,1,0) - elif input_st.real_strides()[3] == 0: - perm = (0,1,2,5,4,3) - strides = (0,0,LN*4,4,0,0,0,1) - else: - return None - if len(input_st.shape) == 8: - local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1,4,4), strides),)) - perm = perm + (6,7) - else: - local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1)),)) - #local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1)),)) - load_st = local_st.permute(perm) - input_st = input_st.permute(perm) - lcl = UOp(Ops.DEFINE_LOCAL, x.dtype.ptr(local_st.real_size(), local=True), (), f"temp{x.src[0].arg}") - global_load = x.replace(src=(x.src[0], input_st.to_uop())) - ret = UOp(Ops.STORE, src=(lcl, local_st.to_uop(), global_load)) - return UOp(Ops.LOAD, x.dtype, src=(lcl, load_st.to_uop(), ret)) - -local_loads_pm = PatternMatcher([ - (UPat(Ops.LOAD, name="x"), transform_load), -]) - -def ast_transform(k, ast): - #return ast - ast = graph_rewrite(ast, local_loads_pm, ctx=(k, set())) - #ast = ast.replace(arg=replace(ast.arg, upcasted=0)) - print(ast) - return ast - -if __name__ == "__main__": - rng = np.random.default_rng() - a = Tensor(na:=rng.random((4096, 4096), dtype=np.float32)).realize() - b = Tensor(nb:=rng.random((4096, 4096), dtype=np.float32)).realize() - c = a @ b - si = c.schedule()[-1] - k = Kernel(si.ast, opts=Device[Device.DEFAULT].renderer) - #opts = [Opt(op=OptOps.LOCAL, axis=1, arg=16), - # Opt(op=OptOps.LOCAL, axis=0, arg=8), - # Opt(op=OptOps.UPCAST, axis=2, arg=4), - # Opt(op=OptOps.UPCAST, axis=1, arg=4), - # Opt(op=OptOps.UPCAST, axis=0, arg=2)] - #opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), - # Opt(op=OptOps.UPCAST, axis=0, arg=4), - # Opt(op=OptOps.LOCAL, axis=1, arg=8), - # Opt(op=OptOps.LOCAL, axis=0, arg=4)] - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=LN), - #Opt(op=OptOps.UPCAST, axis=0, arg=4), - #Opt(op=OptOps.UPCAST, axis=1, arg=4), - Opt(op=OptOps.LOCAL, axis=1, arg=LN), - Opt(op=OptOps.LOCAL, axis=0, arg=LN)] - k.apply_opts(opts) - prg = k.to_program(ast_transform=ast_transform) - if getenv("FAST", 1) and Device.DEFAULT == "AMD": - #src = (pathlib.Path(__file__).parent / "fp32_sgemm_amd" / "src" / "kernel8_batched_gmem.s").read_text() - src = (pathlib.Path(__file__).parent / "kernel8_batched_gmem.s").read_text() - prg = replace(prg, src=src, global_size=[N//128, N//128, 1], local_size=[128, 1, 1]) - print(prg.global_size, prg.local_size) - ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) - with Context(DEBUG=2): - for _ in range(run_count): ei.run(wait=True) - nc = c.numpy() - np.testing.assert_allclose(na@nb, nc, rtol=1e-5) diff --git a/tinygrad/extra/gemm/amx.py b/tinygrad/extra/gemm/amx.py deleted file mode 100755 index 430fa20b..00000000 --- a/tinygrad/extra/gemm/amx.py +++ /dev/null @@ -1,180 +0,0 @@ -#!/usr/bin/env python3 -import numpy as np -import time -import sys -np.set_printoptions(linewidth=160) -np.set_printoptions(linewidth=1000, threshold=10000000000, suppress=False) -from tinygrad.runtime.ops_llvm import LLVMDevice, LLVMProgram, LLVMCompiler -from llvmlite import ir # type: ignore -from tinygrad.helpers import flat_mv -from tinygrad.device import MallocAllocator - -# https://github.com/corsix/amx/blob/main/Instructions.md -# 12 lines for AMX support -from functools import partialmethod -class AMX: - @staticmethod - def nop_op_imm5(op, imm5, builder): builder.asm(ir.FunctionType(ir.VoidType(), []), f".word (0x201000 + ({op} << 5) + {imm5}); amx op {op} imm {imm5}", "", tuple(), True) - @staticmethod - def op_gpr(op, builder, gpr): builder.asm(ir.FunctionType(ir.VoidType(), [ir.IntType(64)]), f".word (0x201000 + ({op} << 5) + 0$0 - ((0$0 >> 4) * 6)); amx op {op} reg $0", "r", (gpr,), True) - set, clr = partialmethod(nop_op_imm5, 17, 0), partialmethod(nop_op_imm5, 17, 1) - ldx, ldy, stx, sty = partialmethod(op_gpr, 0), partialmethod(op_gpr, 1), partialmethod(op_gpr, 2), partialmethod(op_gpr, 3) - ldz, stz, ldzi, stzi = partialmethod(op_gpr, 4), partialmethod(op_gpr, 5), partialmethod(op_gpr, 6), partialmethod(op_gpr, 7) - extrx, extry = partialmethod(op_gpr, 8), partialmethod(op_gpr, 9) - fma64, fms64, fma32, fms32 = partialmethod(op_gpr, 10), partialmethod(op_gpr, 11), partialmethod(op_gpr, 12), partialmethod(op_gpr, 13) - mac16, fma16, fms16 = partialmethod(op_gpr, 14), partialmethod(op_gpr, 15), partialmethod(op_gpr, 16) - vecint, vecfp, matint, matfp, genlut = partialmethod(op_gpr, 18), partialmethod(op_gpr, 19), partialmethod(op_gpr, 20), partialmethod(op_gpr, 21), partialmethod(op_gpr, 22) - -def int_const(x): return ir.Constant(ir.IntType(64), x) - - -N = 4096 -# N = 1024 -# N = 64 - -BW = N*N*4 - -# matrix is 64M, max load bandwidth is 57 GB/s -# cache line looks like 256 bytes (64 floats) - -na = np.zeros((256), dtype=np.float32) -# na = np.zeros((N, N), dtype=np.float32) -nb = np.random.randn(N, N).astype(np.float32) -nc = np.random.randn(N, N).astype(np.float32) - -ns = nb.reshape(-1, 32).sum(axis=0) - -a = MallocAllocator.alloc(na.size * np.dtype(np.float32).itemsize) -b = MallocAllocator.alloc(nb.size * np.dtype(np.float32).itemsize) -c = MallocAllocator.alloc(nc.size * np.dtype(np.float32).itemsize) - -MallocAllocator._copyin(b, flat_mv(nb.data)) -MallocAllocator._copyin(c, flat_mv(nc.data)) - -module = ir.Module(name=__file__) -func = ir.Function(module, ir.FunctionType(ir.IntType(64), [ir.FloatType().as_pointer()]*3), name='exec') - -# load all -entry = ir.IRBuilder(func.append_basic_block(name="entry")) -zm, xm, ym = [entry.ptrtoint(func.args[i], ir.IntType(64)) for i in range(3)] - -loop_1 = ir.IRBuilder(func.append_basic_block(name="loop_y")) -loop_1_exit = ir.IRBuilder(func.append_basic_block(name="loop_y_exit")) -exit = ir.IRBuilder(func.append_basic_block(name="exit")) - -y = loop_1.phi(ir.IntType(64), name="y") -y.add_incoming(int_const(0), entry._block) -yp = loop_1_exit.add(y, int_const(32*2)) -y.add_incoming(yp, loop_1_exit._block) - -prefetch_function = ir.Function(module, ir.FunctionType(ir.VoidType(), [ir.PointerType(ir.FloatType()), ir.IntType(32), ir.IntType(32), ir.IntType(32)]), name="llvm.prefetch") - -xptr = y -addr = loop_1_exit.add(xm, loop_1_exit.mul(int_const(4), xptr)) - -#prefetch_ptr = loop_1_exit.inttoptr(loop_1_exit.add(addr, int_const(128)), ir.PointerType(ir.FloatType())) -#loop_1_exit.call(prefetch_function, [prefetch_ptr, ir.IntType(32)(0), ir.IntType(32)(2), ir.IntType(32)(1)]) - -AMX.ldx(loop_1_exit, loop_1_exit.add(int_const(1<<62), addr)) -xptr = loop_1_exit.add(xptr, int_const(32)) -AMX.ldy(loop_1_exit, loop_1_exit.add(int_const(1<<62), loop_1_exit.add(xm, loop_1_exit.mul(int_const(4), xptr)))) - -AMX.fma32(loop_1_exit, int_const(1 << 63 | 1 << 28)) -AMX.fma32(loop_1_exit, int_const(1 << 63 | 1 << 28 | 1 << 20 | (16*4)<<10)) -AMX.fma32(loop_1_exit, int_const(1 << 63 | 1 << 29)) -AMX.fma32(loop_1_exit, int_const(1 << 63 | 1 << 29 | 1 << 20 | (16*4))) - -AMX.set(entry) - -AMX.stz(exit, exit.add(zm, int_const(1 << 62 | (0 << 56) | 0))) -AMX.clr(exit) - -entry.branch(loop_1._block) -loop_1.branch(loop_1_exit._block) -loop_1_exit.cbranch(loop_1_exit.icmp_unsigned("==", yp, int_const(N*N)), exit._block, loop_1._block) -exit.ret(int_const(0)) - -device = LLVMDevice("llvm") -prog = LLVMProgram(device, "exec", LLVMCompiler(device).compile(str(module))) - -""" -loop_1 = ir.IRBuilder(func.append_basic_block(name="loop_y")) -loop_2 = ir.IRBuilder(func.append_basic_block(name="loop_x")) -loop_3 = ir.IRBuilder(func.append_basic_block(name="loop_k")) -loop_3_exit = ir.IRBuilder(func.append_basic_block(name="loop_k_exit")) -loop_2_exit = ir.IRBuilder(func.append_basic_block(name="loop_x_exit")) -loop_1_exit = ir.IRBuilder(func.append_basic_block(name="loop_y_exit")) - -y = loop_1.phi(ir.IntType(64), name="y") -x = loop_2.phi(ir.IntType(64), name="x") -k = loop_3.phi(ir.IntType(64), name="k") - -exit = ir.IRBuilder(func.append_basic_block(name="exit")) - -AMX.set(loop_2) - -# stride -xptr = loop_3_exit.add(x, loop_3_exit.mul(k, int_const(N))) -yptr = loop_3_exit.add(y, loop_3_exit.mul(k, int_const(N))) - -# if you are okay with the wrong answer, this is faster -#xptr = loop_3_exit.add(x, loop_3_exit.mul(k, int_const(32))) -#yptr = loop_3_exit.add(y, loop_3_exit.mul(k, int_const(32))) - -# double loads load 32 floats -AMX.ldx(loop_3_exit, loop_3_exit.add(int_const(1<<62), loop_3_exit.add(xm, loop_3_exit.mul(int_const(4), xptr)))) -AMX.ldy(loop_3_exit, loop_3_exit.add(int_const(1<<62), loop_3_exit.add(ym, loop_3_exit.mul(int_const(4), yptr)))) - -# -AMX.fma32(loop_3_exit, int_const(0<<20 | (0*16*4)<<10 | (0*16*4))) -AMX.fma32(loop_3_exit, int_const(1<<20 | (1*16*4)<<10 | (0*16*4))) -AMX.fma32(loop_3_exit, int_const(2<<20 | (0*16*4)<<10 | (1*16*4))) -AMX.fma32(loop_3_exit, int_const(3<<20 | (1*16*4)<<10 | (1*16*4))) - -# store -gptr = loop_2_exit.mul(loop_2_exit.add(loop_2.mul(y, int_const(N)), x), int_const(4)) -zmp = loop_2_exit.add(zm, gptr) -for j in range(2): - for r in range(16): - z_row = j*2 - ptr = ((j*16)+r)*N - AMX.stz(loop_2_exit, loop_2_exit.add(zmp, int_const(1 << 62 | ((r*4+z_row) << 56) | ptr*4))) -AMX.clr(loop_2_exit) - -yp = loop_1_exit.add(y, int_const(32)) -xp = loop_2_exit.add(x, int_const(32)) -kp = loop_3_exit.add(k, int_const(1)) - -y.add_incoming(int_const(0), entry._block) -x.add_incoming(int_const(0), loop_1._block) -k.add_incoming(int_const(0), loop_2._block) -y.add_incoming(yp, loop_1_exit._block) -x.add_incoming(xp, loop_2_exit._block) -k.add_incoming(kp, loop_3_exit._block) - -entry.branch(loop_1._block) -loop_1.branch(loop_2._block) -loop_2.branch(loop_3._block) -loop_3.branch(loop_3_exit._block) -loop_3_exit.cbranch(loop_3_exit.icmp_unsigned("==", kp, int_const(N)), loop_2_exit._block, loop_3._block) -loop_2_exit.cbranch(loop_2_exit.icmp_unsigned("==", xp, int_const(N)), loop_1_exit._block, loop_2._block) -loop_1_exit.cbranch(loop_1_exit.icmp_unsigned("==", yp, int_const(N)), exit._block, loop_1._block) -exit.ret(int_const(0)) - -device = LLVMDevice("llvm") -prog = LLVMProgram(device, "exec", LLVMCompiler(device).compile(str(module))) -""" - -def timeit(fxn): - st = time.perf_counter() - et = fxn() - return time.perf_counter() - st - -tm = min([timeit(lambda: prog(a, b, c, N**2)) for _ in range(20)]) -MallocAllocator._copyout(flat_mv(na.data), a) -print(f"{N*N:10d} {tm*1e6:9.2f} us, {BW*1e-9/tm:.2f} GB/s") - -np.testing.assert_allclose(na[:ns.shape[0]], ns, atol=1e-4, rtol=1e-4) - -# comp = (nb.T @ nc).T -# np.testing.assert_allclose(na, comp, atol=1e-4, rtol=1e-5) \ No newline at end of file diff --git a/tinygrad/extra/gemm/cuda_matmul.py b/tinygrad/extra/gemm/cuda_matmul.py deleted file mode 100644 index 2d4ba5c8..00000000 --- a/tinygrad/extra/gemm/cuda_matmul.py +++ /dev/null @@ -1,107 +0,0 @@ -import os -import numpy as np -os.environ["CUDA"] = "1" -from tinygrad.runtime.ops_cuda import CUDAAllocator, CUDADevice, CUDAProgram, CUDACompiler -from tinygrad.helpers import flat_mv - -FLOAT16 = True -ACC_FLOAT16 = False -N = 4096 - -na = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32) -nb = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32) -nc = np.empty(N*N, np.float32) - -if FLOAT16: - na = na.astype(np.float16) - nb = nb.astype(np.float16) - -device = CUDADevice("cuda:0") -cudaalloc = CUDAAllocator(device) - -a = cudaalloc.alloc(N*N*2 if FLOAT16 else N*N*4) -b = cudaalloc.alloc(N*N*2 if FLOAT16 else N*N*4) -c = cudaalloc.alloc(N*N*4) - -cudaalloc._copyin(a, bytearray(na)) -cudaalloc._copyin(b, bytearray(nb)) - -FLOPS = N*N*N*2 -BW = N*N*3*4 - -print(device.arch) -compiler = CUDACompiler(device.arch) -prog = CUDAProgram(device, "wmma_example", compiler.compile(f""" -#include -using namespace nvcuda; - -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = {'16' if FLOAT16 else '8'}; - -extern "C" __global__ void wmma_example({'half' if FLOAT16 else 'float'} *a, {'half' if FLOAT16 else 'float'} *b, float *c) -{{ - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - warpM *= 4; - warpN *= 4; - - wmma::fragment a_frag[4]; - wmma::fragment b_frag[4]; - wmma::fragment acc_frag[4][4]; - for (int j = 0; j < 4; j++) {{ - for (int i = 0; i < 4; i++) {{ - wmma::fill_fragment(acc_frag[i][j], 0.0f); - }} - }} - - for (int k = 0; k < {N}; k += WMMA_K) {{ - int aRow = warpM * WMMA_M; - int aCol = k; - int bRow = k; - int bCol = warpN * WMMA_N; - - wmma::load_matrix_sync(a_frag[0], a + aRow + 0 * WMMA_M + aCol * {N}, {N}); - wmma::load_matrix_sync(a_frag[1], a + aRow + 1 * WMMA_M + aCol * {N}, {N}); - wmma::load_matrix_sync(a_frag[2], a + aRow + 2 * WMMA_M + aCol * {N}, {N}); - wmma::load_matrix_sync(a_frag[3], a + aRow + 3 * WMMA_M + aCol * {N}, {N}); - - wmma::load_matrix_sync(b_frag[0], b + bRow + (0 * WMMA_N + bCol) * {N}, {N}); - wmma::load_matrix_sync(b_frag[1], b + bRow + (1 * WMMA_N + bCol) * {N}, {N}); - wmma::load_matrix_sync(b_frag[2], b + bRow + (2 * WMMA_N + bCol) * {N}, {N}); - wmma::load_matrix_sync(b_frag[3], b + bRow + (3 * WMMA_N + bCol) * {N}, {N}); - - #pragma unroll - for (int i = 0; i < {'0' if FLOAT16 else '4'}; i++) {{ - #pragma unroll - for (int t = 0; t < a_frag[i].num_elements; t++) {{ a_frag[i].x[t] = wmma::__float_to_tf32(a_frag[i].x[t]); }} - #pragma unroll - for (int t = 0; t < b_frag[i].num_elements; t++) {{ b_frag[i].x[t] = wmma::__float_to_tf32(b_frag[i].x[t]); }} - }} - - #pragma unroll - for (int j = 0; j < 4; j++) {{ - #pragma unroll - for (int i = 0; i < 4; i++) {{ - wmma::mma_sync(acc_frag[i][j], a_frag[i], b_frag[j], acc_frag[i][j]); - }} - }} - }} - - for (int j = 0; j < 4; j++) {{ - for (int i = 0; i < 4; i++) {{ - wmma::fragment acc_store; - for (int t = 0; t < acc_frag[i][j].num_elements; t++) acc_store.x[t] = acc_frag[i][j].x[t]; - int cRow = (warpM + i) * WMMA_M; - int cCol = (warpN + j) * WMMA_N; - wmma::store_matrix_sync(c + cRow + cCol * {N}, acc_store, {N}, wmma::mem_col_major); - }} - }} -}} -""")) - -global_size, local_size = [(N//16)//4, (N//16)//4, 1], [32, 1, 1] -tm = min([prog(a, b, c, global_size=global_size, local_size=local_size, wait=True) for _ in range(20)]) -print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matmul, {BW*1e-9/tm:.2f} GB/s") -cudaalloc._copyout(flat_mv(nc.data), c) -np.testing.assert_allclose(na.T.astype(np.float32) @ nb.T.astype(np.float32), nc.reshape(N,N).T, atol=1e-2) \ No newline at end of file diff --git a/tinygrad/extra/gemm/fuzz_matmul.py b/tinygrad/extra/gemm/fuzz_matmul.py deleted file mode 100644 index b024a29a..00000000 --- a/tinygrad/extra/gemm/fuzz_matmul.py +++ /dev/null @@ -1,44 +0,0 @@ -import numpy as np -from tinygrad.helpers import getenv -from tinygrad import dtypes, Tensor -dtype_in = dtypes.half if getenv("HALF") else dtypes.bfloat16 if getenv("BFLOAT16") else dtypes.float -acc_dtype = dtypes.half if getenv("ACC_HALF") else dtypes.bfloat16 if getenv("ACC_BFLOAT16") else None -N_START = getenv("N_START", 1) -M_START = getenv("M_START", 1) -K_START = getenv("K_START", 1) -N_STOP = getenv("N_STOP", 32) -M_STOP = getenv("M_STOP", N_STOP) -K_STOP = getenv("K_STOP", N_STOP) -N_STEP = getenv("N_STEP", 1) -M_STEP = getenv("M_STEP", 1) -K_STEP = getenv("K_STEP", 1) -ATOL = getenv("ATOL", 1e-4) -RTOL = getenv("RTOL", 3e-2) - -if __name__ == "__main__": - failed = [] - for M in range(M_START, M_STOP+1, M_STEP): - for N in range(N_START, N_STOP+1, N_STEP): - for K in range(K_START, K_STOP+1, K_STEP): - print(f"testing {M=} {N=} {K=}") - a, b = Tensor.rand(M, K, dtype=dtype_in).realize(), Tensor.rand(K, N, dtype=dtype_in).realize() - c = a.matmul(b, dtype=acc_dtype).realize() - comp = a.numpy().astype(np.float32) @ b.numpy().astype(np.float32) - nc = c.numpy() - try: - np.testing.assert_allclose(nc, comp, atol=ATOL, rtol=RTOL) - except AssertionError as e: - failed.append((M,N,K,)) - if getenv("DEBUG_VALUES") > 0: - indices = np.where(~np.isclose(nc, comp, rtol=RTOL, atol=ATOL)) - non_matching_elements_nc = nc[indices] - non_matching_elements_comp = comp[indices] - print(indices) - print("result :", non_matching_elements_nc) - print("ground truth:", non_matching_elements_comp) - print(e) - pass - print(f"failed sizes: {failed}") - print(f"num failures: {len(failed)}") - if len(failed) > 0: - raise RuntimeError(f"failed on {len(failed)} kernels") \ No newline at end of file diff --git a/tinygrad/extra/gemm/gemm.c b/tinygrad/extra/gemm/gemm.c deleted file mode 100644 index eb2aee38..00000000 --- a/tinygrad/extra/gemm/gemm.c +++ /dev/null @@ -1,194 +0,0 @@ -// single: clang -O2 -march=native gemm.c -// multi: clang -O2 -march=native gemm.c -DNTHREADS=32 -lpthread -#define _GNU_SOURCE - -// https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//#define DEBUG - -#ifdef DEBUG - #define N 8 -#endif - -#ifndef N - // NOTE: if you change this you have to rerun gemm.py - #define N 512 -#endif - -#ifndef NTHREADS - #define NTHREADS 1 -#endif - -// aligned? -float A[N*N] __attribute__ ((aligned (64))); -float B[N*N] __attribute__ ((aligned (64))); -float C[N*N] __attribute__ ((aligned (64))); -float val[N*N] __attribute__ ((aligned (64))); - -__m256 *Am = (__m256*)A; -__m256 *Bm = (__m256*)B; -__m256 *Cm = (__m256*)C; - -uint64_t nanos() { - struct timespec start; - clock_gettime(CLOCK_MONOTONIC_RAW, &start); - return (uint64_t)start.tv_sec*1000000000 + (uint64_t)start.tv_nsec; -} - -float Bf[N*N] __attribute__ ((aligned (64))); -__m256 *Bfm = (__m256*)Bf; - -#define BLOCK 8 -#define BLOCK_Y 4 -#define BLOCK_X 2 -void matmul(int sy, int ey) { - // 136.77 GFLOPS on single core numpy - // 4.9 GHz is max boost for 5950X - // 32 FLOPS/cycle (16 FMAs, aka 2x 8 single wide / 32 byte FMAs) - // theoretical max is 156.8 GFLOPS, we see 150 - // multicore theo max = 2508.8 GFLOPS, we see 1501.434299 - - // Bf = (y/8, k, 8) - for (int y = sy; y < ey; y+=BLOCK_Y) { - for (int x = 0; x < N; x+=BLOCK*BLOCK_X) { - - __m256 acc[BLOCK_Y][BLOCK_X] = {}; - for (int k = 0; k < N; k++) { - for (int iy = 0; iy < BLOCK_Y; iy++) { - __m256 ta = _mm256_broadcast_ss(&A[(y+iy)*N + k]); - for (int ix = 0; ix < BLOCK_X; ix++) { - acc[iy][ix] = _mm256_fmadd_ps(ta, Bfm[((x+ix*BLOCK)*N + k*8)/8], acc[iy][ix]); - } - } - } - - for (int iy = 0; iy < BLOCK_Y; iy++) { - for (int ix = 0; ix < BLOCK_X; ix++) { - Cm[((y+iy)*N + x + ix * BLOCK)/8] = acc[iy][ix]; - } - } - } - } -} - -pthread_mutex_t lock = PTHREAD_MUTEX_INITIALIZER; -atomic_int nready = 0; -atomic_int ndone = 0; - -void *matmul_thread(void *n) { - int k = (int)(int64_t)n; - int sy = (N/NTHREADS) * k; - int ey = (N/NTHREADS) * (k+1); - - cpu_set_t set; - CPU_ZERO(&set); - CPU_SET(k,&set); - pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &set); - - nready++; - - // gotta have main lock once to signal start - pthread_mutex_lock(&lock); - pthread_mutex_unlock(&lock); - - matmul(sy, ey); - - // we done - ndone++; - return NULL; -} - -int main() { - printf("hello with %d threads\n", NTHREADS); - -#ifdef DEBUG - for (int i = 0; i < N*N; i++) A[i] = i; - for (int i = 0; i < N*N; i++) B[i] = i; -#else - FILE *f = fopen("/tmp/matmul", "rb"); - if (f == NULL) { - printf("please pregenerate python /tmp/matmul file\n"); - return -1; - } - fread(A, 1, sizeof(float)*N*N, f); - fread(B, 1, sizeof(float)*N*N, f); - fread(val, 1, sizeof(float)*N*N, f); - fclose(f); -#endif - - // preswizzle - for (int y = 0; y < N; y+=8) { - for (int x = 0; x < N; x++) { - for (int iy = 0; iy < 8; iy++) { - Bf[y*N + x*8 + iy] = B[(y+iy)*N + x]; - } - } - } - - for (int i = 0; i < 10; i++) { - memset(C, 0, N*N*sizeof(float)); - -#if NTHREADS != 1 - nready = 0; - ndone = 0; - pthread_mutex_lock(&lock); - pthread_t threads[NTHREADS]; - for (int j = 0; j < NTHREADS; j++) { - pthread_create(&threads[j], NULL, matmul_thread, (void *)(uint64_t)j); - } - while (nready != NTHREADS) usleep(1); -#endif - - uint64_t start = nanos(); -#if NTHREADS == 1 - matmul(0, N); -#else - // unlocking mutex starts threads - pthread_mutex_unlock(&lock); - while (ndone != NTHREADS) usleep(1); -#endif - uint64_t end = nanos(); - -#if NTHREADS != 1 - for (int j = 0; j < NTHREADS; j++) { - pthread_join(threads[j], NULL); - } -#endif - - double gflop = (2.0*N*N*N)*1e-9; - double s = (end-start)*1e-9; - printf("%f GFLOP/S -- %.2f ms\n", gflop/s, s*1e3); - - // hack around throttling - //if (i%4 == 0) sleep(1); - } - -#ifdef DEBUG - for (int i = 0; i < N*N; i++) { - if (i%N == 0 && i != 0) printf("\n"); - printf("%f ", C[i]); - } - printf("\n"); -#else - for (int k = 0; k < N*N; k++) { - if (fabsf(C[k] - val[k]) > 1e-3) { - printf("MISMATCH AT %d, %f != %f\n", k, C[k], val[k]); - return -1; - } - } - printf("match\n"); -#endif - - return 0; -} diff --git a/tinygrad/extra/gemm/gemm.py b/tinygrad/extra/gemm/gemm.py deleted file mode 100755 index eaa5f74a..00000000 --- a/tinygrad/extra/gemm/gemm.py +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env python3 -import os -#os.environ['OMP_NUM_THREADS'] = '1' -import time -import numpy as np - -N = 512 -if __name__ == "__main__": - # N^2 - A = np.random.randn(N, N).astype(np.float32) - # N^2 - B = np.random.randn(N, N).astype(np.float32) - - # 2N compute in N^2 output cells - flop = 2*N*N*N - #print(f"{flop / 1e9:.2f} GFLOP") - - for i in range(10): - st = time.monotonic() - C = A @ B.T - et = time.monotonic() - s = et-st - print(f"{flop/s * 1e-9:.2f} GFLOP/S, {s*1e3:.2f} ms") - - with open("/tmp/matmul", "wb") as f: - f.write(A.data) - f.write(B.data) - f.write(C.data) diff --git a/tinygrad/extra/gemm/hip_matmul.py b/tinygrad/extra/gemm/hip_matmul.py deleted file mode 100644 index 8688a01c..00000000 --- a/tinygrad/extra/gemm/hip_matmul.py +++ /dev/null @@ -1,142 +0,0 @@ -import time -import numpy as np -from tinygrad.helpers import getenv, prod, flat_mv -from tinygrad.runtime.ops_amd import AMDAllocator, AMDDevice, AMDProgram - -# AMD_LOG_LEVEL=3 ./MIOpenDriver gemm --iter 1000 --time 1 --a_w 2048 --a_h 2048 --b_w 2048 -# 5.5: Cijk_Ailk_Bljk_HHS_BH_MT128x128x16_MI16x16x16x1_SN_1LDSB0_APM1_ABV0_ACED0_AF0EM1_AF1EM1_AMAS3_ASE_ASGT_ASAE01_ASCE01_ASEM1_AAC0_BL1_BS1_DTL0_DTVA0_DVO0_ETSP_EPS1_FL0_GRVW8_GSU1_GSUASB_GLS0_ISA1100_IU1_K1_KLA_LBSPP128_LPA0_LPB8_LDL1_LRVW16_LWPMn1_LDW0_FMA_MIAV1_MDA2_NTA0_NTB0_NTC0_NTD0_NEPBS0_NLCA1_NLCB1_ONLL1_OPLV0_PK0_PAP0_PGR1_PLR1_RK0_SIA1_SS1_SU32_SUM0_SUS128_SCIUI1_SPO0_SRVW0_SSO0_SVW4_SNLL0_TT4_64_TLDS1_USFGROn1_VAW2_VSn1_VW4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGM4 -# 5.6: Cijk_Ailk_Bljk_HHS_BH_MT128x128x16_MI16x16x16x1_SN_1LDSB0_APM1_ABV0_ACED0_AF0EM1_AF1EM1_AMAS3_ASE_ASGT_ASLT_ASAE01_ASCE01_ASEM1_AAC0_BL1_BS1_DTL0_DTVA0_DVO0_ETSP_EPS1_FL0_GRPM1_GRVW8_GSU1_GSUASB_GLS0_ISA1100_IU1_K1_KLA_LBSPP128_LPA0_LPB8_LDL1_LRVW16_LWPMn1_LDW0_FMA_MIAV1_MDA2_MO40_NTA0_NTB0_NTC0_NTD0_NEPBS0_NLCA1_NLCB1_ONLL1_OPLV0_PK0_PAP0_PGR1_PLR1_RK0_SIA1_SS1_SU32_SUM0_SUS128_SCIUI1_SPO0_SRVW0_SSO0_SVW4_SNLL0_TT4_64_TLDS1_USFGROn1_VAW2_VSn1_VW4_WSGRA1_WSGRB1_WS32_WG32_4_1_WGM4 -# gets ~100 -# hipExtModuleLaunchKernel ( 0x0x16ccde0, 2048, 16, 1, 128, 1, 1, -# 161.60 us = 106.31 TFLOPS -# with --batch_count 8 / 1.258128 ms / (8*2048*2048*2048*2)/(1.258128)*1e-9 / 109.24 TFLOPS - -# we only get ~53 -# KY=2 KX=2 N=2048 python3 extra/gemm/hip_matmul.py -# 4194304 324.76 us, would be 52899.88 GFLOPS matmul, 154.98 GB/s - -DEBUG = getenv("DEBUG", 0) -RAND = getenv("RAND", 0) -CNT = getenv("CNT", 128) - -N = getenv("N", 4096) -KX = getenv("KX", 4) -KY = getenv("KY", 4) -assert N%(16*KX) == 0, f"N must be multiple of {16*KX}" -assert N%(16*KY) == 0, f"N must be multiple of {16*KY}" -FLOPS = N*N*N*2 -BW = N*N*3*4 - -local_size = [32, 1, 1] -global_size = [N//(KX*16), N//(KY*16), 1] -num_threads = prod(local_size) - -# Can AMDAllocator initialized as device=0 by default? -device = AMDDevice() -hipallocator = AMDAllocator(device) -a = hipallocator.alloc(N*N*4) -b = hipallocator.alloc(N*N*2) -c = hipallocator.alloc(N*N*2) -na = np.empty(N*N, np.float32) -nb = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32).astype(np.float16) -nc = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32).astype(np.float16) -hipallocator._copyin(b, memoryview(bytearray(nb))) -hipallocator._copyin(c, memoryview(bytearray(nc))) - -prog_str = f""" -#define F32 -typedef long unsigned int size_t; -#define half _Float16 -typedef float float8 __attribute__((ext_vector_type(8))); -typedef _Float16 half4 __attribute__((ext_vector_type(4))); -typedef _Float16 half8 __attribute__((ext_vector_type(8))); -typedef _Float16 half16 __attribute__((ext_vector_type(16))); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); -extern "C" __attribute__((global))void __attribute__((amdgpu_flat_work_group_size(1, {num_threads}))) test(float* c, half* a, half* b) {{ - - const int gx = __ockl_get_group_id(0) + __ockl_get_local_id(2); - const int gy = __ockl_get_group_id(1) + __ockl_get_local_id(3); - - const int lIdx = __ockl_get_local_id(0); - const int lane = lIdx%16; - - c += gx*{KX*16}*{N} + gy*{KY*16} + (lIdx/16)*{N} + lane; - a += gx*{KX*16}*{N}; - b += gy*{KY*16}; - - half16 a_frag[{KX}]; - half16 b_frag[{KY}]; - #ifdef F32 - float8 c_frag[{KY}][{KX}] = {{}}; - #else - half16 c_frag[{KY}][{KX}] = {{}}; - #endif - - for (int k = 0; k < {N}; k += 16) {{ - __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); - __builtin_amdgcn_s_barrier(); - __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); - - for (int ele = 0; ele < 16; ++ele) {{ - for (int x = 0; x < {KX}; x++) {{ - a_frag[x][ele] = a[(k+ele) + x*{16*N} + {N}*lane]; - }} - }} - for (int ele = 0; ele < 16; ++ele) {{ - for (int y = 0; y < {KY}; y++) {{ - b_frag[y][ele] = b[(k+ele)*{N} + y*16 + lane]; - }} - }} - for (int y = 0; y < {KY}; y++) {{ - for (int x = 0; x < {KX}; x++) {{ - #ifdef F32 - c_frag[y][x] = __builtin_amdgcn_wmma_f32_16x16x16_f16_w32(a_frag[x], b_frag[y], c_frag[y][x]); - #else - c_frag[y][x] = __builtin_amdgcn_wmma_f16_16x16x16_f16_w32(a_frag[x], b_frag[y], c_frag[y][x], false); - #endif - }} - }} - }} - - for (int ele = 0; ele < 8; ++ele) {{ - for (int y = 0; y < {KY}; y++) {{ - for (int x = 0; x < {KX}; x++) {{ - #ifdef F32 - c[ele*{2*N} + y*16 + x*{16*N}] = c_frag[y][x][ele]; - #else - c[ele*{2*N} + y*16 + x*{16*N}] = c_frag[y][x][ele*2]; - #endif - }} - }} - }} -}}""" - -if DEBUG > 1: print(prog_str) -lib = device.compiler.compile(prog_str) -prog = AMDProgram(device, "test", lib) - -def timeit(fxn): - st = time.perf_counter() - et = fxn() - ret = time.perf_counter() - st # NOTE: et doesn't contain the launch overhead - if DEBUG > 0: print(f"{ret*1e6:.2f} us") - # rerun rand - if RAND: - nb = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32).astype(np.float16) - nc = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32).astype(np.float16) - hipallocator._copyin(b, memoryview(bytearray(nb))) - hipallocator._copyin(c, memoryview(bytearray(nc))) - return et - -print("global/local size", global_size, local_size, f"local_size:{prod(local_size)} total_size:{prod(global_size+local_size)}") -tm = min([timeit(lambda: prog(a, b, c, global_size=global_size, local_size=local_size, wait=True)) for _ in range(CNT)]) -hipallocator._copyout(flat_mv(na.data),a) -na = na.reshape(N,N) -comp = nb.astype(np.float32) @ nc.astype(np.float32) -print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matmul, {BW*1e-9/tm:.2f} GB/s") -if DEBUG > 2: print(f"which nan={np.where(np.isnan(na))} len={len(np.where(np.isnan(na))[0])}") -if DEBUG > 2: print(f"which diff={np.where(abs(na-comp) > 2e-2)} len={len(np.where(abs(na-comp) > 2e-2)[0])}") -if DEBUG > 2: print(f"which zero={np.where(abs(na) < 2e-2)} len={len(np.where(abs(na) < 2e-2)[0])}") -np.testing.assert_allclose(na, comp, atol=1e-2, rtol=1e-2) diff --git a/tinygrad/extra/gemm/intel_xmx.py b/tinygrad/extra/gemm/intel_xmx.py deleted file mode 100644 index 8ec478e5..00000000 --- a/tinygrad/extra/gemm/intel_xmx.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python3 -import numpy as np -from tinygrad.runtime.ops_gpu import CLProgram, CLCompiler -from tinygrad import Device, dtypes -from tinygrad.device import Buffer -from hexdump import hexdump - -# https://github.com/intel/intel-graphics-compiler/blob/master/documentation/visa/instructions/DPAS.md -# https://registry.khronos.org/OpenCL/extensions/intel/cl_intel_subgroups.html -# https://registry.khronos.org/OpenCL/extensions/intel/cl_intel_subgroup_matrix_multiply_accumulate.html -# https://registry.khronos.org/OpenCL/extensions/intel/cl_intel_subgroup_split_matrix_multiply_accumulate.html -# https://hc34.hotchips.org/assets/program/conference/day1/GPU%20HPC/Intel_s%20Ponte%20Vecchio%20GPU%20-%20Architecture%20Systems%20and%20Software%20FINAL.pdf - -device = Device["GPU"] - -# NOTE: only the subgroup type 8 ones work -prog = CLProgram(device, "test", CLCompiler(device, "test").compile(f""" -__attribute__((intel_reqd_sub_group_size(8))) -__kernel void test(__global float* data0, const __global int* data1, const __global int8* data2) {{ - int lidx0 = get_local_id(0); - int a = data1[lidx0]; - int8 b = data2[lidx0]; - float out = intel_sub_group_f16_f16_matrix_mad_k16(a, b, 0.0f); - data0[lidx0] = out; -}} -""")) -#with open("/tmp/test.elf", "wb") as f: f.write(prog.lib) - -a = Buffer("GPU", 8, dtypes.float32).allocate() -b = Buffer("GPU", 0x10, dtypes.float16).allocate() -c = Buffer("GPU", 8*0x10, dtypes.float16).allocate() - -row = np.array([1,2,3,4,5,6,7,8,1,2,3,4,5,6,7,8], np.float16) -mat = np.random.random((8, 0x10)).astype(np.float16) - -b.copyin(row.data) -c.copyin(mat.data) -ret = prog(a._buf, b._buf, c._buf, global_size=[1,1,1], local_size=[8,1,1], wait=True) -print(ret) -out = np.frombuffer(a.as_buffer(), np.float32) -real = row.astype(np.float32)@mat.T.astype(np.float32) -print("out:", out) -print("real", real) diff --git a/tinygrad/extra/gemm/jax_pmatmul.py b/tinygrad/extra/gemm/jax_pmatmul.py deleted file mode 100755 index b69a2b9b..00000000 --- a/tinygrad/extra/gemm/jax_pmatmul.py +++ /dev/null @@ -1,27 +0,0 @@ -#!/usr/bin/env python3 -import time -import jax -import jax.numpy as jnp - -print(jax.devices()) -DEVICES = len(jax.devices()) -BS = 32 -N = 4096 -dtype = jnp.float16 -A = jnp.zeros((DEVICES, BS, N, N), dtype) -B = jnp.zeros((1, 1, N, N), dtype) -A = jax.device_put_sharded([A[i] for i in range(DEVICES)], jax.devices()) -B = jax.device_put_sharded([B for i in range(DEVICES)], jax.devices()) - -OPS = DEVICES*BS*N*N*N*2 -def matmul(A,B): return jnp.matmul(A,B,preferred_element_type=jnp.float32) -pmatmul = jax.pmap(matmul) - -MAX_TFLOPS = 123*DEVICES # Peak FP16 Tensor TFLOPS with FP32 Acc (7900XTX) -for i in range(10): - st = time.perf_counter() - C = pmatmul(A,B).block_until_ready() - et = time.perf_counter()-st - tflops = (OPS*1e-12)/et - print(f"time {et*1e3:.2f} ms, TFLOPS {tflops:6.2f}, MFU {(tflops/MAX_TFLOPS)*100:4.2f}% out shape {C.shape} dtype {C.dtype}") - diff --git a/tinygrad/extra/gemm/kernel8_batched_gmem.s b/tinygrad/extra/gemm/kernel8_batched_gmem.s deleted file mode 100644 index b37c050d..00000000 --- a/tinygrad/extra/gemm/kernel8_batched_gmem.s +++ /dev/null @@ -1,2435 +0,0 @@ - .text - .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" - ;.amdhsa_code_object_version 5 - .protected kernel ; -- Begin function kernel - .globl kernel - .p2align 8 - .type kernel,@function -kernel: ; @kernel -; %bb.0: ; %.preheader193 - - ;; Init code for matrix A and B buffer Loads - START - s_load_b128 s[20:23], s[0:1], 0x8 ; Matrix A and B - s_waitcnt lgkmcnt(0) - - ; Matrix B offsets: - ; input is s[22:23] - ; offset base addresses s[24:39] - - s_add_u32 s24, s22, 0x0000 - s_addc_u32 s25, s23, 0 - s_add_u32 s26, s22, 0x4000 - s_addc_u32 s27, s23, 0 - s_add_u32 s28, s22, 0x8000 - s_addc_u32 s29, s23, 0 - s_add_u32 s30, s22, 0xc000 - s_addc_u32 s31, s23, 0 - s_add_u32 s32, s22, 0x10000 - s_addc_u32 s33, s23, 0 - s_add_u32 s34, s22, 0x14000 - s_addc_u32 s35, s23, 0 - s_add_u32 s36, s22, 0x18000 - s_addc_u32 s37, s23, 0 - s_add_u32 s38, s22, 0x1c000 - s_addc_u32 s39, s23, 0 - - ; compute Matrix B offset - s_lshl_b32 s19, s14, 7 ; BN * blockIdx.x - - - v_add_nc_u32_e32 v203, s19, v0 ; index = BN * blockIdx.x + threadIdx.x - v_lshlrev_b32_e32 v203,2, v203 ; offset = 4*index (VPGR offset in global_load are in bytes when using SPGR addressing) - - ; Matrix A offsets: - ; input is s[20:21] - ; offset base addresses s[40:55] - s_add_u32 s40, s20, 0x0000 - s_addc_u32 s41, s21, 0 - s_add_u32 s42, s20, 0x40000 - s_addc_u32 s43, s21, 0 - s_add_u32 s44, s20, 0x80000 - s_addc_u32 s45, s21, 0 - s_add_u32 s46, s20, 0xc0000 - s_addc_u32 s47, s21, 0 - s_add_u32 s48, s20, 0x100000 - s_addc_u32 s49, s21, 0 - s_add_u32 s50, s20, 0x140000 - s_addc_u32 s51, s21, 0 - s_add_u32 s52, s20, 0x180000 - s_addc_u32 s53, s21, 0 - s_add_u32 s54, s20, 0x1c0000 - s_addc_u32 s55, s21, 0 - - ; compute Matrix A offset - s_lshl_b32 s19, s15, 19 ; 4096 * 128 * blockIdx.y - v_lshrrev_b32_e32 v1, 3, v0 ; threadIdx.x / 8 - v_lshlrev_b32_e32 v1, 12, v1 ; 4096 * (threadIdx.x/8) - v_and_b32_e32 v215, 7, v0 ; threadIdx.x % 8 - v_add_u32_e32 v215, v1, v215 ; index = 4096*(threadIdx.x/8) + threadIdx.x % 8 - v_add_nc_u32_e32 v215, s19, v215 ; index += 4096*128*blockIdx.y - v_lshlrev_b32_e32 v215,2, v215 ; offset = 4*index - - - - - ;; Init code for matrix A and B buffer Loads - END - - - s_clause 0x1 - ;s_load_b128 s[4:7], s[0:1], 0x18 ; N, alpha, beta, ??? - s_load_b128 s[8:11], s[0:1], 0x8 ; Matrix A and B - - s_mov_b32 s4, 4096 ; hardcode 4096 - s_mov_b32 s5, 0x3f800000 ; alpha - s_mov_b32 s6, 0 ; beta - s_mov_b32 s7, 0 - - s_lshl_b32 s2, s14, 7 - v_lshrrev_b32_e32 v4, 3, v0 - v_or_b32_e32 v1, s2, v0 - s_lshl_b32 s3, s15, 7 - v_and_b32_e32 v118, 7, v0 - s_bfe_i32 s12, s15, 0x10018 - v_or_b32_e32 v22, s3, v4 - v_ashrrev_i32_e32 v2, 31, v1 - s_lshr_b32 s12, s12, 25 - s_load_b64 s[0:1], s[0:1], 0 ; Matrix C - v_lshlrev_b32_e32 v135, 2, v118 - s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) - v_lshlrev_b64 v[5:6], 2, v[1:2] - s_waitcnt lgkmcnt(0) - v_add_nc_u32_e32 v3, s4, v1 - v_mul_lo_u32 v119, v22, s4 - v_add_co_u32 v5, vcc_lo, s10, v5 - s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) - v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo - v_add_nc_u32_e32 v7, s4, v3 - v_ashrrev_i32_e32 v4, 31, v3 - s_lshl_b32 s7, s4, 4 - s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3) - v_add_nc_u32_e32 v125, s7, v119 - v_add_nc_u32_e32 v2, s4, v7 - v_ashrrev_i32_e32 v8, 31, v7 - v_lshlrev_b64 v[9:10], 2, v[3:4] - s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) - v_add_nc_u32_e32 v130, s7, v125 - v_add_nc_u32_e32 v11, s4, v2 - v_ashrrev_i32_e32 v3, 31, v2 - v_lshlrev_b64 v[7:8], 2, v[7:8] - v_add_co_u32 v9, vcc_lo, s10, v9 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) - v_add_nc_u32_e32 v13, s4, v11 - v_ashrrev_i32_e32 v12, 31, v11 - v_lshlrev_b64 v[2:3], 2, v[2:3] - v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo - v_ashrrev_i32_e32 v14, 31, v13 - v_add_co_u32 v7, vcc_lo, s10, v7 - v_lshlrev_b64 v[11:12], 2, v[11:12] - v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo - v_add_nc_u32_e32 v15, s4, v13 - v_add_co_u32 v2, vcc_lo, s10, v2 - v_lshlrev_b64 v[13:14], 2, v[13:14] - v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo - v_add_co_u32 v11, vcc_lo, s10, v11 - v_add_nc_u32_e32 v4, s4, v15 - v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo - v_add_co_u32 v13, vcc_lo, s10, v13 - v_ashrrev_i32_e32 v16, 31, v15 - v_add_nc_u32_e32 v134, s7, v130 - v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo - s_clause 0x5 - global_load_b32 v23, v[5:6], off - global_load_b32 v24, v[9:10], off - global_load_b32 v25, v[7:8], off - global_load_b32 v26, v[2:3], off - global_load_b32 v27, v[11:12], off - global_load_b32 v28, v[13:14], off - v_add_nc_u32_e32 v6, v119, v118 - v_ashrrev_i32_e32 v5, 31, v4 - v_add_nc_u32_e32 v8, v125, v118 - v_lshlrev_b64 v[2:3], 2, v[15:16] - v_add_nc_u32_e32 v137, s7, v134 - v_ashrrev_i32_e32 v7, 31, v6 - v_add_nc_u32_e32 v10, v130, v118 - v_lshlrev_b64 v[4:5], 2, v[4:5] - v_ashrrev_i32_e32 v9, 31, v8 - v_add_nc_u32_e32 v12, v134, v118 - v_add_nc_u32_e32 v138, s7, v137 - v_add_co_u32 v2, vcc_lo, s10, v2 - v_lshlrev_b64 v[6:7], 2, v[6:7] - v_ashrrev_i32_e32 v11, 31, v10 - v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo - v_add_nc_u32_e32 v14, v137, v118 - v_add_co_u32 v4, vcc_lo, s10, v4 - v_lshlrev_b64 v[8:9], 2, v[8:9] - v_ashrrev_i32_e32 v13, 31, v12 - v_add_nc_u32_e32 v139, s7, v138 - v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo - v_add_co_u32 v6, vcc_lo, s8, v6 - v_lshlrev_b64 v[10:11], 2, v[10:11] - v_ashrrev_i32_e32 v15, 31, v14 - v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo - v_add_nc_u32_e32 v16, v138, v118 - v_add_co_u32 v8, vcc_lo, s8, v8 - v_lshlrev_b64 v[12:13], 2, v[12:13] - v_add_nc_u32_e32 v140, s7, v139 - v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo - v_add_nc_u32_e32 v18, v139, v118 - v_add_co_u32 v10, vcc_lo, s8, v10 - v_lshlrev_b64 v[14:15], 2, v[14:15] - v_ashrrev_i32_e32 v17, 31, v16 - v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo - v_add_nc_u32_e32 v20, v140, v118 - v_add_co_u32 v12, vcc_lo, s8, v12 - v_ashrrev_i32_e32 v19, 31, v18 - v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo - v_add_co_u32 v14, vcc_lo, s8, v14 - v_lshlrev_b64 v[16:17], 2, v[16:17] - v_ashrrev_i32_e32 v21, 31, v20 - v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo - s_clause 0x4 - global_load_b32 v29, v[6:7], off - global_load_b32 v30, v[8:9], off - global_load_b32 v31, v[10:11], off - global_load_b32 v12, v[12:13], off - global_load_b32 v13, v[14:15], off - v_lshlrev_b64 v[6:7], 2, v[18:19] - v_add_co_u32 v8, vcc_lo, s8, v16 - v_lshlrev_b64 v[10:11], 2, v[20:21] - v_add_co_ci_u32_e32 v9, vcc_lo, s9, v17, vcc_lo - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) - v_add_co_u32 v6, vcc_lo, s8, v6 - v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo - v_add_co_u32 v10, vcc_lo, s8, v10 - v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo - s_clause 0x1 - global_load_b32 v3, v[2:3], off - global_load_b32 v4, v[4:5], off - s_clause 0x2 - global_load_b32 v5, v[8:9], off - global_load_b32 v6, v[6:7], off - global_load_b32 v7, v[10:11], off - v_add_nc_u32_e32 v9, s12, v22 - v_or_b32_e32 v10, 16, v22 - v_or_b32_e32 v11, 32, v22 - v_or_b32_e32 v14, 48, v22 - v_or_b32_e32 v15, 64, v22 - v_or_b32_e32 v16, 0x50, v22 - v_or_b32_e32 v17, 0x60, v22 - v_or_b32_e32 v18, 0x70, v22 - s_bfe_i32 s7, s14, 0x10018 - v_and_b32_e32 v9, 0x3fffff80, v9 - s_lshr_b32 s7, s7, 25 - v_add_nc_u32_e32 v19, s12, v10 - v_add_nc_u32_e32 v8, s7, v1 - v_add_nc_u32_e32 v20, s12, v11 - v_add_nc_u32_e32 v21, s12, v14 - v_add_nc_u32_e32 v32, s12, v15 - v_add_nc_u32_e32 v33, s12, v16 - v_add_nc_u32_e32 v34, s12, v17 - v_add_nc_u32_e32 v35, s12, v18 - v_and_b32_e32 v8, 0x3fffff80, v8 - v_sub_nc_u32_e32 v9, v22, v9 - v_and_b32_e32 v19, 0x3fffff80, v19 - v_and_b32_e32 v20, 0x3fffff80, v20 - v_and_b32_e32 v21, 0x3fffff80, v21 - v_and_b32_e32 v22, 0x3fffff80, v32 - v_and_b32_e32 v32, 0x3fffff80, v33 - v_and_b32_e32 v33, 0x3fffff80, v34 - v_and_b32_e32 v34, 0x3fffff80, v35 - v_sub_nc_u32_e32 v8, v1, v8 - v_lshlrev_b32_e32 v9, 2, v9 - v_sub_nc_u32_e32 v10, v10, v19 - v_sub_nc_u32_e32 v11, v11, v20 - v_sub_nc_u32_e32 v14, v14, v21 - v_sub_nc_u32_e32 v15, v15, v22 - v_sub_nc_u32_e32 v16, v16, v32 - v_sub_nc_u32_e32 v17, v17, v33 - v_sub_nc_u32_e32 v18, v18, v34 - v_bfe_u32 v2, v0, 3, 2 - v_lshlrev_b32_e32 v8, 2, v8 - v_mad_u32_u24 v141, 0x210, v118, v9 - v_lshlrev_b32_e32 v9, 2, v10 - v_lshlrev_b32_e32 v10, 2, v11 - v_lshlrev_b32_e32 v11, 2, v14 - v_lshlrev_b32_e32 v14, 2, v15 - v_lshlrev_b32_e32 v15, 2, v16 - v_lshlrev_b32_e32 v16, 2, v17 - v_lshlrev_b32_e32 v17, 2, v18 - v_lshlrev_b32_e32 v136, 2, v2 - v_add_nc_u32_e32 v8, 0x80, v8 - v_mad_u32_u24 v142, 0x210, v118, v9 - v_mad_u32_u24 v143, 0x210, v118, v10 - v_mad_u32_u24 v144, 0x210, v118, v11 - v_mad_u32_u24 v145, 0x210, v118, v14 - v_mad_u32_u24 v146, 0x210, v118, v15 - v_mad_u32_u24 v147, 0x210, v118, v16 - v_mad_u32_u24 v148, 0x210, v118, v17 - s_mov_b32 s7, 0 - s_cmp_gt_i32 s4, 0 - s_waitcnt vmcnt(14) - ds_store_2addr_stride64_b32 v8, v23, v24 offset0:16 offset1:18 - s_waitcnt vmcnt(9) - ds_store_b32 v141, v29 - ds_store_2addr_stride64_b32 v8, v25, v26 offset0:20 offset1:22 - s_waitcnt vmcnt(8) - ds_store_b32 v142, v30 - s_waitcnt vmcnt(7) - ds_store_b32 v143, v31 - ds_store_2addr_stride64_b32 v8, v27, v28 offset0:24 offset1:26 - s_waitcnt vmcnt(6) - ds_store_b32 v144, v12 - s_waitcnt vmcnt(5) - ds_store_b32 v145, v13 - s_waitcnt vmcnt(3) - ds_store_2addr_stride64_b32 v8, v3, v4 offset0:28 offset1:30 - s_waitcnt vmcnt(2) - ds_store_b32 v146, v5 - s_waitcnt vmcnt(1) - ds_store_b32 v147, v6 - s_waitcnt vmcnt(0) - ds_store_b32 v148, v7 - s_waitcnt lgkmcnt(0) - s_barrier - s_cbranch_scc1 .LBB0_3 -; %bb.1: ; %.preheader193..preheader180_crit_edge - v_lshlrev_b32_e32 v149, 2, v118 - v_lshlrev_b32_e32 v150, 2, v2 - s_mov_b32 s12, 0 - s_and_not1_b32 vcc_lo, exec_lo, s7 - s_cbranch_vccz .LBB0_4 -; %bb.2: - v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s12 - v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s12 - v_dual_mov_b32 v18, s12 :: v_dual_mov_b32 v19, s12 - v_dual_mov_b32 v20, s12 :: v_dual_mov_b32 v21, s12 - v_dual_mov_b32 v34, s12 :: v_dual_mov_b32 v35, s12 - v_dual_mov_b32 v36, s12 :: v_dual_mov_b32 v37, s12 - v_dual_mov_b32 v50, s12 :: v_dual_mov_b32 v51, s12 - v_dual_mov_b32 v52, s12 :: v_dual_mov_b32 v53, s12 - v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s12 - v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s12 - v_dual_mov_b32 v22, s12 :: v_dual_mov_b32 v23, s12 - v_dual_mov_b32 v24, s12 :: v_dual_mov_b32 v25, s12 - v_dual_mov_b32 v38, s12 :: v_dual_mov_b32 v39, s12 - v_dual_mov_b32 v40, s12 :: v_dual_mov_b32 v41, s12 - v_dual_mov_b32 v54, s12 :: v_dual_mov_b32 v55, s12 - v_dual_mov_b32 v56, s12 :: v_dual_mov_b32 v57, s12 - v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s12 - v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s12 - v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, s12 - v_dual_mov_b32 v28, s12 :: v_dual_mov_b32 v29, s12 - v_dual_mov_b32 v42, s12 :: v_dual_mov_b32 v43, s12 - v_dual_mov_b32 v44, s12 :: v_dual_mov_b32 v45, s12 - v_dual_mov_b32 v58, s12 :: v_dual_mov_b32 v59, s12 - v_dual_mov_b32 v60, s12 :: v_dual_mov_b32 v61, s12 - v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s12 - v_dual_mov_b32 v16, s12 :: v_dual_mov_b32 v17, s12 - v_dual_mov_b32 v30, s12 :: v_dual_mov_b32 v31, s12 - v_dual_mov_b32 v32, s12 :: v_dual_mov_b32 v33, s12 - v_dual_mov_b32 v46, s12 :: v_dual_mov_b32 v47, s12 - v_dual_mov_b32 v48, s12 :: v_dual_mov_b32 v49, s12 - v_dual_mov_b32 v62, s12 :: v_dual_mov_b32 v63, s12 - v_dual_mov_b32 v64, s12 :: v_dual_mov_b32 v65, s12 - v_dual_mov_b32 v66, s12 :: v_dual_mov_b32 v67, s12 - v_dual_mov_b32 v68, s12 :: v_dual_mov_b32 v69, s12 - v_dual_mov_b32 v82, s12 :: v_dual_mov_b32 v83, s12 - v_dual_mov_b32 v84, s12 :: v_dual_mov_b32 v85, s12 - v_dual_mov_b32 v98, s12 :: v_dual_mov_b32 v99, s12 - v_dual_mov_b32 v100, s12 :: v_dual_mov_b32 v101, s12 - v_dual_mov_b32 v114, s12 :: v_dual_mov_b32 v115, s12 - v_dual_mov_b32 v116, s12 :: v_dual_mov_b32 v117, s12 - v_dual_mov_b32 v70, s12 :: v_dual_mov_b32 v71, s12 - v_dual_mov_b32 v72, s12 :: v_dual_mov_b32 v73, s12 - v_dual_mov_b32 v86, s12 :: v_dual_mov_b32 v87, s12 - v_dual_mov_b32 v88, s12 :: v_dual_mov_b32 v89, s12 - v_dual_mov_b32 v102, s12 :: v_dual_mov_b32 v103, s12 - v_dual_mov_b32 v104, s12 :: v_dual_mov_b32 v105, s12 - v_dual_mov_b32 v120, s12 :: v_dual_mov_b32 v121, s12 - v_dual_mov_b32 v122, s12 :: v_dual_mov_b32 v123, s12 - v_dual_mov_b32 v74, s12 :: v_dual_mov_b32 v75, s12 - v_dual_mov_b32 v76, s12 :: v_dual_mov_b32 v77, s12 - v_dual_mov_b32 v90, s12 :: v_dual_mov_b32 v91, s12 - v_dual_mov_b32 v92, s12 :: v_dual_mov_b32 v93, s12 - v_dual_mov_b32 v106, s12 :: v_dual_mov_b32 v107, s12 - v_dual_mov_b32 v108, s12 :: v_dual_mov_b32 v109, s12 - v_dual_mov_b32 v126, s12 :: v_dual_mov_b32 v127, s12 - v_dual_mov_b32 v128, s12 :: v_dual_mov_b32 v129, s12 - v_dual_mov_b32 v78, s12 :: v_dual_mov_b32 v79, s12 - v_dual_mov_b32 v80, s12 :: v_dual_mov_b32 v81, s12 - v_dual_mov_b32 v94, s12 :: v_dual_mov_b32 v95, s12 - v_dual_mov_b32 v96, s12 :: v_dual_mov_b32 v97, s12 - v_dual_mov_b32 v110, s12 :: v_dual_mov_b32 v111, s12 - v_dual_mov_b32 v112, s12 :: v_dual_mov_b32 v113, s12 - v_dual_mov_b32 v131, s12 :: v_dual_mov_b32 v132, s12 - v_dual_mov_b32 v133, s12 :: v_dual_mov_b32 v124, s12 - s_branch .LBB0_13 -.LBB0_3: - s_mov_b32 s7, -1 - ; implicit-def: $sgpr12 - ; implicit-def: $vgpr149 - ; implicit-def: $vgpr150 -.LBB0_4: ; %.lr.ph - s_ashr_i32 s7, s2, 31 - v_dual_mov_b32 v133, 0 :: v_dual_lshlrev_b32 v2, 4, v2 - s_lshr_b32 s7, s7, 25 - s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) - v_dual_mov_b32 v124, 0 :: v_dual_add_nc_u32 v3, s7, v1 - v_ashrrev_i32_e32 v149, 31, v119 - v_ashrrev_i32_e32 v150, 31, v125 - v_ashrrev_i32_e32 v151, 31, v130 - v_dual_mov_b32 v132, 0 :: v_dual_and_b32 v3, 0x3fffff80, v3 - v_ashrrev_i32_e32 v152, 31, v134 - v_ashrrev_i32_e32 v153, 31, v137 - v_ashrrev_i32_e32 v154, 31, v138 - v_ashrrev_i32_e32 v156, 31, v139 - v_sub_nc_u32_e32 v3, v1, v3 - v_ashrrev_i32_e32 v157, 31, v140 - v_lshl_or_b32 v166, v118, 4, 0x1080 - v_dual_mov_b32 v131, 0 :: v_dual_mov_b32 v110, 0 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) - v_lshl_add_u32 v155, v3, 2, 0x1080 - v_dual_mov_b32 v112, 0 :: v_dual_lshlrev_b32 v3, 2, v0 - v_dual_mov_b32 v113, 0 :: v_dual_mov_b32 v96, 0 - v_lshl_add_u32 v158, 1, 9, v155 - v_lshl_add_u32 v159, 2, 9, v155 - v_lshl_add_u32 v160, 3, 9, v155 - v_lshl_add_u32 v161, 4, 9, v155 - v_lshl_add_u32 v162, 5, 9, v155 - v_lshl_add_u32 v163, 6, 9, v155 - v_lshl_add_u32 v164, 7, 9, v155 - v_and_or_b32 v165, 0x180, v3, v2 - v_dual_mov_b32 v111, 0 :: v_dual_mov_b32 v94, 0 - v_dual_mov_b32 v97, 0 :: v_dual_mov_b32 v80, 0 - v_dual_mov_b32 v95, 0 :: v_dual_mov_b32 v78, 0 - v_dual_mov_b32 v81, 0 :: v_dual_mov_b32 v128, 0 - v_dual_mov_b32 v79, 0 :: v_dual_mov_b32 v126, 0 - v_dual_mov_b32 v129, 0 :: v_dual_mov_b32 v108, 0 - v_dual_mov_b32 v127, 0 :: v_dual_mov_b32 v106, 0 - v_dual_mov_b32 v109, 0 :: v_dual_mov_b32 v92, 0 - v_dual_mov_b32 v107, 0 :: v_dual_mov_b32 v90, 0 - v_dual_mov_b32 v93, 0 :: v_dual_mov_b32 v76, 0 - v_dual_mov_b32 v91, 0 :: v_dual_mov_b32 v74, 0 - v_dual_mov_b32 v77, 0 :: v_dual_mov_b32 v122, 0 - v_dual_mov_b32 v75, 0 :: v_dual_mov_b32 v120, 0 - v_dual_mov_b32 v123, 0 :: v_dual_mov_b32 v104, 0 - v_dual_mov_b32 v121, 0 :: v_dual_mov_b32 v102, 0 - v_dual_mov_b32 v105, 0 :: v_dual_mov_b32 v88, 0 - v_dual_mov_b32 v103, 0 :: v_dual_mov_b32 v86, 0 - v_dual_mov_b32 v89, 0 :: v_dual_mov_b32 v72, 0 - v_dual_mov_b32 v87, 0 :: v_dual_mov_b32 v70, 0 - v_dual_mov_b32 v73, 0 :: v_dual_mov_b32 v116, 0 - v_dual_mov_b32 v71, 0 :: v_dual_mov_b32 v114, 0 - v_dual_mov_b32 v117, 0 :: v_dual_mov_b32 v100, 0 - v_dual_mov_b32 v115, 0 :: v_dual_mov_b32 v98, 0 - v_dual_mov_b32 v101, 0 :: v_dual_mov_b32 v84, 0 - v_dual_mov_b32 v99, 0 :: v_dual_mov_b32 v82, 0 - v_dual_mov_b32 v85, 0 :: v_dual_mov_b32 v68, 0 - v_dual_mov_b32 v83, 0 :: v_dual_mov_b32 v66, 0 - v_dual_mov_b32 v69, 0 :: v_dual_mov_b32 v64, 0 - v_dual_mov_b32 v67, 0 :: v_dual_mov_b32 v62, 0 - v_dual_mov_b32 v65, 0 :: v_dual_mov_b32 v48, 0 - v_dual_mov_b32 v63, 0 :: v_dual_mov_b32 v46, 0 - v_dual_mov_b32 v49, 0 :: v_dual_mov_b32 v32, 0 - v_dual_mov_b32 v47, 0 :: v_dual_mov_b32 v30, 0 - v_dual_mov_b32 v33, 0 :: v_dual_mov_b32 v16, 0 - v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v14, 0 - v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v60, 0 - v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v58, 0 - v_dual_mov_b32 v61, 0 :: v_dual_mov_b32 v44, 0 - v_dual_mov_b32 v59, 0 :: v_dual_mov_b32 v42, 0 - v_dual_mov_b32 v45, 0 :: v_dual_mov_b32 v28, 0 - v_dual_mov_b32 v43, 0 :: v_dual_mov_b32 v26, 0 - v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v12, 0 - v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v10, 0 - v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v56, 0 - v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v54, 0 - v_dual_mov_b32 v57, 0 :: v_dual_mov_b32 v40, 0 - v_dual_mov_b32 v55, 0 :: v_dual_mov_b32 v38, 0 - v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v24, 0 - v_dual_mov_b32 v39, 0 :: v_dual_mov_b32 v22, 0 - v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v8, 0 - v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v6, 0 - v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v52, 0 - v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v50, 0 - v_dual_mov_b32 v53, 0 :: v_dual_mov_b32 v36, 0 - v_dual_mov_b32 v51, 0 :: v_dual_mov_b32 v34, 0 - v_dual_mov_b32 v37, 0 :: v_dual_mov_b32 v20, 0 - v_dual_mov_b32 v35, 0 :: v_dual_mov_b32 v18, 0 - v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v4, 0 - v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v2, 0 - ;setting v214 as well (extra bank2 vpgr used by output matrix C) - v_mov_b32 v214,0 - - v_mov_b32_e32 v5, 0 - v_mov_b32_e32 v3, 0 - s_add_i32 s7, s4, -1 - s_add_u32 s8, s8, 32 - s_addc_u32 s9, s9, 0 - s_mov_b32 s12, 0 - ; implicit-def: $vgpr175 - ; implicit-def: $vgpr176 - ; implicit-def: $vgpr177 - ; implicit-def: $vgpr178 - ; implicit-def: $vgpr179 - ; implicit-def: $vgpr180 - ; implicit-def: $vgpr181 - ; implicit-def: $vgpr182 - ; implicit-def: $vgpr167 - ; implicit-def: $vgpr168 - ; implicit-def: $vgpr169 - ; implicit-def: $vgpr170 - ; implicit-def: $vgpr171 - ; implicit-def: $vgpr172 - ; implicit-def: $vgpr173 - ; implicit-def: $vgpr174 - s_branch .LBB0_6 -.LBB0_5: ; in Loop: Header=BB0_6 Depth=1 - s_add_i32 s12, s12, 8 - s_delay_alu instid0(SALU_CYCLE_1) - s_cmp_ge_i32 s12, s4 - s_cbranch_scc1 .LBB0_12 -.LBB0_6: ; =>This Loop Header: Depth=1 - ; Child Loop BB0_9 Depth 2 - s_cmp_lt_i32 s12, s7 - s_cselect_b32 s13, -1, 0 - s_cmp_ge_i32 s12, s7 - s_cbranch_scc1 .LBB0_8 -; %bb.7: ; %.preheader192 - ; in Loop: Header=BB0_6 Depth=1 - - ; Global memory read for matrix B - v_add_nc_u32_e32 v203, 0x20000, v203 - v_add_nc_u32_e32 v215, 0x20, v215 - s_setprio 0 - global_load_b32 v167, v203, s[24:25] - global_load_b32 v168, v203, s[26:27] - global_load_b32 v169, v203, s[28:29] - global_load_b32 v170, v203, s[30:31] - - - - -.LBB0_8: ; %.loopexit - ; in Loop: Header=BB0_6 Depth=1 - v_mov_b32_e32 v183, v165 - s_mov_b32 s14, 0 - - v_mov_b32 v202,v166 -.LBB0_9: ; %.preheader188 - ; Parent Loop BB0_6 Depth=1 - ; => This Inner Loop Header: Depth=2 - - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - s_clause 0x1 - global_load_b32 v171, v203, s[32:33] - global_load_b32 v172, v203, s[34:35] - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - - s_clause 0x1 - global_load_b32 v173, v203, s[36:37] - global_load_b32 v174, v203, s[38:39] - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - s_clause 0x1 - global_load_b32 v175, v215, s[40:41] - global_load_b32 v176, v215, s[42:43] - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - - ; Global memory read for matrix A - s_clause 0x1 - global_load_b32 v177, v215, s[44:45] - global_load_b32 v178, v215, s[46:47] - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - s_clause 0x1 - global_load_b32 v179, v215, s[48:49] - global_load_b32 v180, v215, s[50:51] - - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - s_clause 0x1 - global_load_b32 v181, v215, s[52:53] - global_load_b32 v182, v215, s[54:55] - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - s_waitcnt lgkmcnt(0) - -; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - - - - - s_clause 0xB; - ;A on bank 2-3 - ds_load_b64 v[186:187], v183 - ds_load_b64 v[190:191], v183 offset: 8 - ds_load_b64 v[194:195], v183 offset: 64 - ds_load_b64 v[198:199], v183 offset: 72 - - - ;B on bank 0-1 - ds_load_b64 v[184:185], v202 - ds_load_b64 v[188:189], v202 offset: 8 - ds_load_b64 v[192:193], v202 offset: 128 - ds_load_b64 v[196:197], v202 offset: 136 - ds_load_b64 v[200:201], v202 offset: 256 - ds_load_b64 v[204:205], v202 offset: 264 - ds_load_b64 v[208:209], v202 offset: 384 - ds_load_b64 v[212:213], v202 offset: 392 - - v_add_nc_u32_e32 v183, 0x210, v183 - v_add_nc_u32_e32 v202, 0x200, v202 - ;s_cmpk_lg_i32 s14, 0x1000 - s_waitcnt lgkmcnt(0) - -; ; new vpgrs allocation - -v_dual_fmac_f32 v5, v186, v184 :: v_dual_fmac_f32 v2, v187, v185 -s_setprio 1 -v_dual_fmac_f32 v3, v186, v185 :: v_dual_fmac_f32 v4, v187, v184 -v_dual_fmac_f32 v9, v186, v188 :: v_dual_fmac_f32 v6, v187, v189 -v_dual_fmac_f32 v7, v187, v188 :: v_dual_fmac_f32 v8, v186, v189 -v_dual_fmac_f32 v13, v190, v188 :: v_dual_fmac_f32 v10, v191, v189 -v_dual_fmac_f32 v11, v190, v189 :: v_dual_fmac_f32 v12, v191, v188 -v_dual_fmac_f32 v17, v190, v184 :: v_dual_fmac_f32 v14, v191, v185 -v_dual_fmac_f32 v15, v191, v184 :: v_dual_fmac_f32 v16, v190, v185 -v_dual_fmac_f32 v21, v194, v184 :: v_dual_fmac_f32 v18, v195, v185 -v_dual_fmac_f32 v19, v194, v185 :: v_dual_fmac_f32 v20, v195, v184 -v_dual_fmac_f32 v25, v194, v188 :: v_dual_fmac_f32 v22, v195, v189 -v_dual_fmac_f32 v23, v195, v188 :: v_dual_fmac_f32 v24, v194, v189 -v_dual_fmac_f32 v29, v198, v188 :: v_dual_fmac_f32 v26, v199, v189 -v_dual_fmac_f32 v27, v198, v189 :: v_dual_fmac_f32 v28, v199, v188 -v_dual_fmac_f32 v33, v198, v192 :: v_dual_fmac_f32 v30, v199, v193 -v_dual_fmac_f32 v31, v199, v192 :: v_dual_fmac_f32 v32, v198, v193 -v_dual_fmac_f32 v37, v186, v192 :: v_dual_fmac_f32 v34, v187, v193 -v_dual_fmac_f32 v35, v186, v193 :: v_dual_fmac_f32 v36, v187, v192 -v_dual_fmac_f32 v41, v186, v196 :: v_dual_fmac_f32 v38, v187, v197 -v_dual_fmac_f32 v39, v187, v196 :: v_dual_fmac_f32 v40, v186, v197 -v_dual_fmac_f32 v45, v190, v196 :: v_dual_fmac_f32 v42, v191, v197 -v_dual_fmac_f32 v43, v190, v197 :: v_dual_fmac_f32 v44, v191, v196 -v_dual_fmac_f32 v49, v190, v192 :: v_dual_fmac_f32 v46, v191, v193 -v_dual_fmac_f32 v47, v191, v192 :: v_dual_fmac_f32 v48, v190, v193 -v_dual_fmac_f32 v53, v194, v192 :: v_dual_fmac_f32 v50, v195, v193 -v_dual_fmac_f32 v51, v194, v193 :: v_dual_fmac_f32 v52, v195, v192 -v_dual_fmac_f32 v57, v194, v196 :: v_dual_fmac_f32 v54, v195, v197 -v_dual_fmac_f32 v55, v195, v196 :: v_dual_fmac_f32 v56, v194, v197 -v_dual_fmac_f32 v61, v198, v196 :: v_dual_fmac_f32 v58, v199, v197 -v_dual_fmac_f32 v59, v198, v197 :: v_dual_fmac_f32 v60, v199, v196 -v_dual_fmac_f32 v65, v198, v200 :: v_dual_fmac_f32 v62, v199, v201 -v_dual_fmac_f32 v63, v199, v200 :: v_dual_fmac_f32 v64, v198, v201 -v_dual_fmac_f32 v69, v186, v200 :: v_dual_fmac_f32 v66, v187, v201 -v_dual_fmac_f32 v67, v186, v201 :: v_dual_fmac_f32 v68, v187, v200 -v_dual_fmac_f32 v73, v186, v204 :: v_dual_fmac_f32 v70, v187, v205 -v_dual_fmac_f32 v71, v187, v204 :: v_dual_fmac_f32 v72, v186, v205 -v_dual_fmac_f32 v77, v190, v204 :: v_dual_fmac_f32 v74, v191, v205 -v_dual_fmac_f32 v75, v190, v205 :: v_dual_fmac_f32 v76, v191, v204 -v_dual_fmac_f32 v81, v190, v200 :: v_dual_fmac_f32 v78, v191, v201 -v_dual_fmac_f32 v79, v191, v200 :: v_dual_fmac_f32 v80, v190, v201 -v_dual_fmac_f32 v85, v194, v200 :: v_dual_fmac_f32 v82, v195, v201 -v_dual_fmac_f32 v83, v194, v201 :: v_dual_fmac_f32 v84, v195, v200 -v_dual_fmac_f32 v89, v194, v204 :: v_dual_fmac_f32 v86, v195, v205 -v_dual_fmac_f32 v87, v195, v204 :: v_dual_fmac_f32 v88, v194, v205 -v_dual_fmac_f32 v93, v198, v204 :: v_dual_fmac_f32 v90, v199, v205 -v_dual_fmac_f32 v91, v198, v205 :: v_dual_fmac_f32 v92, v199, v204 -v_dual_fmac_f32 v97, v198, v208 :: v_dual_fmac_f32 v94, v199, v209 -v_dual_fmac_f32 v95, v199, v208 :: v_dual_fmac_f32 v96, v198, v209 -v_dual_fmac_f32 v101, v186, v208 :: v_dual_fmac_f32 v98, v187, v209 -v_dual_fmac_f32 v99, v186, v209 :: v_dual_fmac_f32 v100, v187, v208 -v_dual_fmac_f32 v105, v186, v212 :: v_dual_fmac_f32 v102, v187, v213 -v_dual_fmac_f32 v103, v187, v212 :: v_dual_fmac_f32 v104, v186, v213 -v_dual_fmac_f32 v109, v190, v212 :: v_dual_fmac_f32 v106, v191, v213 -v_dual_fmac_f32 v107, v190, v213 :: v_dual_fmac_f32 v108, v191, v212 -v_dual_fmac_f32 v113, v190, v208 :: v_dual_fmac_f32 v110, v191, v209 -v_dual_fmac_f32 v111, v191, v208 :: v_dual_fmac_f32 v112, v190, v209 -v_dual_fmac_f32 v117, v194, v208 :: v_dual_fmac_f32 v114, v195, v209 -v_dual_fmac_f32 v115, v194, v209 :: v_dual_fmac_f32 v116, v195, v208 -v_dual_fmac_f32 v121, v194, v212 :: v_dual_fmac_f32 v122, v195, v213 -v_dual_fmac_f32 v123, v195, v212 :: v_dual_fmac_f32 v120, v194, v213 -v_dual_fmac_f32 v129, v198, v212 :: v_dual_fmac_f32 v126, v199, v213 -v_dual_fmac_f32 v127, v198, v213 :: v_dual_fmac_f32 v124, v199, v212 -v_dual_fmac_f32 v133, v198, v184 :: v_dual_fmac_f32 v214, v199, v185 -v_dual_fmac_f32 v131, v199, v184 :: v_dual_fmac_f32 v128, v198, v185 - -s_setprio 0 - - - - ;s_cbranch_scc1 .LBB0_9 -; %bb.10: ; in Loop: Header=BB0_6 Depth=1 - s_and_not1_b32 vcc_lo, exec_lo, s13 - s_waitcnt vmcnt(0) - s_barrier - s_cbranch_vccnz .LBB0_5 -; %bb.11: ; %.preheader190.preheader - ; in Loop: Header=BB0_6 Depth=1 - ds_store_b32 v155, v167 - ds_store_b32 v141, v175 - ds_store_b32 v158, v168 - ds_store_b32 v142, v176 - ds_store_b32 v159, v169 - ds_store_b32 v143, v177 - ds_store_b32 v160, v170 - ds_store_b32 v144, v178 - ds_store_b32 v161, v171 - ds_store_b32 v145, v179 - ds_store_b32 v162, v172 - ds_store_b32 v146, v180 - ds_store_b32 v163, v173 - ds_store_b32 v147, v181 - ds_store_b32 v164, v174 - ds_store_b32 v148, v182 - s_waitcnt lgkmcnt(0) - s_barrier - s_branch .LBB0_5 - -.LBB0_12: ; %Flow -;Restoring VGPR original allocation - ; v2 -> v128 & v128 -> v2 - v_mov_b32 v200, v128 - v_mov_b32 v128, v2 - v_mov_b32 v2, v200 - ; v128 -> v56 & v56 -> v128 - v_mov_b32 v200, v56 - v_mov_b32 v56, v2 - v_mov_b32 v2, v200 - ; v56 -> v46 & v46 -> v56 - v_mov_b32 v200, v46 - v_mov_b32 v46, v2 - v_mov_b32 v2, v200 - ; v46 -> v100 & v100 -> v46 - v_mov_b32 v200, v100 - v_mov_b32 v100, v2 - v_mov_b32 v2, v200 - ; v100 -> v77 & v77 -> v100 - v_mov_b32 v200, v77 - v_mov_b32 v77, v2 - v_mov_b32 v2, v200 - ; v77 -> v87 & v87 -> v77 - v_mov_b32 v200, v87 - v_mov_b32 v87, v2 - v_mov_b32 v2, v200 - ; v87 -> v27 & v27 -> v87 - v_mov_b32 v200, v27 - v_mov_b32 v27, v2 - v_mov_b32 v2, v200 - ; v27 -> v54 & v54 -> v27 - v_mov_b32 v200, v54 - v_mov_b32 v54, v2 - v_mov_b32 v2, v200 - ; v54 -> v42 & v42 -> v54 - v_mov_b32 v200, v42 - v_mov_b32 v42, v2 - v_mov_b32 v2, v200 - ; v42 -> v98 & v98 -> v42 - v_mov_b32 v200, v98 - v_mov_b32 v98, v2 - v_mov_b32 v2, v200 - ; v98 -> v76 & v76 -> v98 - v_mov_b32 v200, v76 - v_mov_b32 v76, v2 - v_mov_b32 v2, v200 - ; v76 -> v83 & v83 -> v76 - v_mov_b32 v200, v83 - v_mov_b32 v83, v2 - v_mov_b32 v2, v200 - ; v83 -> v32 & v32 -> v83 - v_mov_b32 v200, v32 - v_mov_b32 v32, v2 - v_mov_b32 v2, v200 - ; v32 -> v40 & v40 -> v32 - v_mov_b32 v200, v40 - v_mov_b32 v40, v2 - v_mov_b32 v2, v200 - ; v40 -> v110 & v110 -> v40 - v_mov_b32 v200, v110 - v_mov_b32 v110, v2 - v_mov_b32 v2, v200 - ; v110 -> v68 & v68 -> v110 - v_mov_b32 v200, v68 - v_mov_b32 v68, v2 - v_mov_b32 v2, v200 - ; v68 -> v93 & v93 -> v68 - v_mov_b32 v200, v93 - v_mov_b32 v93, v2 - v_mov_b32 v2, v200 - ; v93 -> v23 & v23 -> v93 - v_mov_b32 v200, v23 - v_mov_b32 v23, v2 - v_mov_b32 v2, v200 - ; v23 -> v59 & v59 -> v23 - v_mov_b32 v200, v59 - v_mov_b32 v59, v2 - v_mov_b32 v2, v200 - ; v59 -> v38 & v38 -> v59 - v_mov_b32 v200, v38 - v_mov_b32 v38, v2 - v_mov_b32 v2, v200 - ; v38 -> v106 & v106 -> v38 - v_mov_b32 v200, v106 - v_mov_b32 v106, v2 - v_mov_b32 v2, v200 - ; v106 -> v66 & v66 -> v106 - v_mov_b32 v200, v66 - v_mov_b32 v66, v2 - v_mov_b32 v2, v200 - ; v66 -> v92 & v92 -> v66 - v_mov_b32 v200, v92 - v_mov_b32 v92, v2 - v_mov_b32 v2, v200 - ; v92 -> v19 & v19 -> v92 - v_mov_b32 v200, v19 - v_mov_b32 v19, v2 - v_mov_b32 v2, v200 - ; v19 -> v64 & v64 -> v19 - v_mov_b32 v200, v64 - v_mov_b32 v64, v2 - v_mov_b32 v2, v200 - ; v64 -> v24 & v24 -> v64 - v_mov_b32 v200, v24 - v_mov_b32 v24, v2 - v_mov_b32 v2, v200 - ; v24 -> v62 & v62 -> v24 - v_mov_b32 v200, v62 - v_mov_b32 v62, v2 - v_mov_b32 v2, v200 - ; v62 -> v20 & v20 -> v62 - v_mov_b32 v200, v20 - v_mov_b32 v20, v2 - v_mov_b32 v2, v200 - ; v20 -> v61 & v61 -> v20 - v_mov_b32 v200, v61 - v_mov_b32 v61, v2 - v_mov_b32 v2, v200 - ; v61 -> v39 & v39 -> v61 - v_mov_b32 v200, v39 - v_mov_b32 v39, v2 - v_mov_b32 v2, v200 - ; v39 -> v107 & v107 -> v39 - v_mov_b32 v200, v107 - v_mov_b32 v107, v2 - v_mov_b32 v2, v200 - ; v107 -> v70 & v70 -> v107 - v_mov_b32 v200, v70 - v_mov_b32 v70, v2 - v_mov_b32 v2, v200 - ; v70 -> v90 & v90 -> v70 - v_mov_b32 v200, v90 - v_mov_b32 v90, v2 - v_mov_b32 v2, v200 - ; v90 -> v18 & v18 -> v90 - v_mov_b32 v200, v18 - v_mov_b32 v18, v2 - v_mov_b32 v2, v200 - ; v18 -> v60 & v60 -> v18 - v_mov_b32 v200, v60 - v_mov_b32 v60, v2 - v_mov_b32 v2, v200 - ; v60 -> v35 & v35 -> v60 - v_mov_b32 v200, v35 - v_mov_b32 v35, v2 - v_mov_b32 v2, v200 - ; v35 -> v112 & v112 -> v35 - v_mov_b32 v200, v112 - v_mov_b32 v112, v2 - v_mov_b32 v2, v200 - ; v112 -> v72 & v72 -> v112 - v_mov_b32 v200, v72 - v_mov_b32 v72, v2 - v_mov_b32 v2, v200 - ; v72 -> v94 & v94 -> v72 - v_mov_b32 v200, v94 - v_mov_b32 v94, v2 - v_mov_b32 v2, v200 - ; v94 -> v4 & v4 -> v94 - v_mov_b32 v200, v4 - v_mov_b32 v4, v2 - v_mov_b32 v2, v200 - ; v4 -> v129 & v129 -> v4 - v_mov_b32 v200, v129 - v_mov_b32 v129, v2 - v_mov_b32 v2, v200 - ; v129 -> v7 & v7 -> v129 - v_mov_b32 v200, v7 - v_mov_b32 v7, v2 - v_mov_b32 v2, v200 - ; v7 -> v127 & v127 -> v7 - v_mov_b32 v200, v127 - v_mov_b32 v127, v2 - v_mov_b32 v2, v200 - ; v127 -> v6 & v6 -> v127 - v_mov_b32 v200, v6 - v_mov_b32 v6, v2 - v_mov_b32 v2, v200 - ; v6 -> v126 & v126 -> v6 - v_mov_b32 v200, v126 - v_mov_b32 v126, v2 - v_mov_b32 v2, v200 - ;NOP 126(2) -> 2 - ; v3 -> v133 & v133 -> v3 - v_mov_b32 v200, v133 - v_mov_b32 v133, v3 - v_mov_b32 v3, v200 - ; v133 -> v57 & v57 -> v133 - v_mov_b32 v200, v57 - v_mov_b32 v57, v3 - v_mov_b32 v3, v200 - ; v57 -> v47 & v47 -> v57 - v_mov_b32 v200, v47 - v_mov_b32 v47, v3 - v_mov_b32 v3, v200 - ; v47 -> v101 & v101 -> v47 - v_mov_b32 v200, v101 - v_mov_b32 v101, v3 - v_mov_b32 v3, v200 - ; v101 -> v81 & v81 -> v101 - v_mov_b32 v200, v81 - v_mov_b32 v81, v3 - v_mov_b32 v3, v200 - ; v81 -> v89 & v89 -> v81 - v_mov_b32 v200, v89 - v_mov_b32 v89, v3 - v_mov_b32 v3, v200 - ; v89 -> v31 & v31 -> v89 - v_mov_b32 v200, v31 - v_mov_b32 v31, v3 - v_mov_b32 v3, v200 - ; v31 -> v37 & v37 -> v31 - v_mov_b32 v200, v37 - v_mov_b32 v37, v3 - v_mov_b32 v3, v200 - ; v37 -> v113 & v113 -> v37 - v_mov_b32 v200, v113 - v_mov_b32 v113, v3 - v_mov_b32 v3, v200 - ; v113 -> v73 & v73 -> v113 - v_mov_b32 v200, v73 - v_mov_b32 v73, v3 - v_mov_b32 v3, v200 - ; v73 -> v95 & v95 -> v73 - v_mov_b32 v200, v95 - v_mov_b32 v95, v3 - v_mov_b32 v3, v200 - ; v95 -> v5 & v5 -> v95 - v_mov_b32 v200, v5 - v_mov_b32 v5, v3 - v_mov_b32 v3, v200 - ; v5 -> v124 & v124 -> v5 - v_mov_b32 v200, v124 - v_mov_b32 v124, v3 - v_mov_b32 v3, v200 - ;NOP 124(3) -> 3 - ; v8 -> v131 & v131 -> v8 - v_mov_b32 v200, v131 - v_mov_b32 v131, v8 - v_mov_b32 v8, v200 - ; v131 -> v53 & v53 -> v131 - v_mov_b32 v200, v53 - v_mov_b32 v53, v8 - v_mov_b32 v8, v200 - ; v53 -> v49 & v49 -> v53 - v_mov_b32 v200, v49 - v_mov_b32 v49, v8 - v_mov_b32 v8, v200 - ; v49 -> v105 & v105 -> v49 - v_mov_b32 v200, v105 - v_mov_b32 v105, v8 - v_mov_b32 v8, v200 - ; v105 -> v79 & v79 -> v105 - v_mov_b32 v200, v79 - v_mov_b32 v79, v8 - v_mov_b32 v8, v200 - ; v79 -> v85 & v85 -> v79 - v_mov_b32 v200, v85 - v_mov_b32 v85, v8 - v_mov_b32 v8, v200 - ; v85 -> v33 & v33 -> v85 - v_mov_b32 v200, v33 - v_mov_b32 v33, v8 - v_mov_b32 v8, v200 - ; v33 -> v41 & v41 -> v33 - v_mov_b32 v200, v41 - v_mov_b32 v41, v8 - v_mov_b32 v8, v200 - ; v41 -> v111 & v111 -> v41 - v_mov_b32 v200, v111 - v_mov_b32 v111, v8 - v_mov_b32 v8, v200 - ; v111 -> v69 & v69 -> v111 - v_mov_b32 v200, v69 - v_mov_b32 v69, v8 - v_mov_b32 v8, v200 - ; v69 -> v97 & v97 -> v69 - v_mov_b32 v200, v97 - v_mov_b32 v97, v8 - v_mov_b32 v8, v200 - ; v97 -> v9 & v9 -> v97 - v_mov_b32 v200, v9 - v_mov_b32 v9, v8 - v_mov_b32 v8, v200 - ; v9 -> v132 & v132 -> v9 - v_mov_b32 v200, v132 - v_mov_b32 v132, v8 - v_mov_b32 v8, v200 - ; v10 -> v114 & v114 -> v10 - v_mov_b32 v200, v114 - v_mov_b32 v114, v10 - v_mov_b32 v10, v200 - ; v114 -> v12 & v12 -> v114 - v_mov_b32 v200, v12 - v_mov_b32 v12, v10 - v_mov_b32 v10, v200 - ; v12 -> v115 & v115 -> v12 - v_mov_b32 v200, v115 - v_mov_b32 v115, v10 - v_mov_b32 v10, v200 - ; v115 -> v16 & v16 -> v115 - v_mov_b32 v200, v16 - v_mov_b32 v16, v10 - v_mov_b32 v10, v200 - ; v16 -> v122 & v122 -> v16 - v_mov_b32 v200, v122 - v_mov_b32 v122, v10 - v_mov_b32 v10, v200 - ;NOP 122(10) -> 10 - ; v11 -> v120 & v120 -> v11 - v_mov_b32 v200, v120 - v_mov_b32 v120, v11 - v_mov_b32 v11, v200 - ; v120 -> v14 & v14 -> v120 - v_mov_b32 v200, v14 - v_mov_b32 v14, v11 - v_mov_b32 v11, v200 - ; v14 -> v116 & v116 -> v14 - v_mov_b32 v200, v116 - v_mov_b32 v116, v11 - v_mov_b32 v11, v200 - ; v116 -> v13 & v13 -> v116 - v_mov_b32 v200, v13 - v_mov_b32 v13, v11 - v_mov_b32 v11, v200 - ; v13 -> v121 & v121 -> v13 - v_mov_b32 v200, v121 - v_mov_b32 v121, v11 - v_mov_b32 v11, v200 - ; v121 -> v15 & v15 -> v121 - v_mov_b32 v200, v15 - v_mov_b32 v15, v11 - v_mov_b32 v11, v200 - ; v15 -> v117 & v117 -> v15 - v_mov_b32 v200, v117 - v_mov_b32 v117, v11 - v_mov_b32 v11, v200 - ; v117 -> v17 & v17 -> v117 - v_mov_b32 v200, v17 - v_mov_b32 v17, v11 - v_mov_b32 v11, v200 - ; v17 -> v123 & v123 -> v17 - v_mov_b32 v200, v123 - v_mov_b32 v123, v11 - v_mov_b32 v11, v200 - ;NOP 123(11) -> 11 - ; v21 -> v65 & v65 -> v21 - v_mov_b32 v200, v65 - v_mov_b32 v65, v21 - v_mov_b32 v21, v200 - ; v65 -> v25 & v25 -> v65 - v_mov_b32 v200, v25 - v_mov_b32 v25, v21 - v_mov_b32 v21, v200 - ; v25 -> v63 & v63 -> v25 - v_mov_b32 v200, v63 - v_mov_b32 v63, v21 - v_mov_b32 v21, v200 - ;NOP 63(21) -> 21 - ; v22 -> v58 & v58 -> v22 - v_mov_b32 v200, v58 - v_mov_b32 v58, v22 - v_mov_b32 v22, v200 - ; v58 -> v34 & v34 -> v58 - v_mov_b32 v200, v34 - v_mov_b32 v34, v22 - v_mov_b32 v22, v200 - ; v34 -> v108 & v108 -> v34 - v_mov_b32 v200, v108 - v_mov_b32 v108, v22 - v_mov_b32 v22, v200 - ; v108 -> v67 & v67 -> v108 - v_mov_b32 v200, v67 - v_mov_b32 v67, v22 - v_mov_b32 v22, v200 - ; v67 -> v96 & v96 -> v67 - v_mov_b32 v200, v96 - v_mov_b32 v96, v22 - v_mov_b32 v22, v200 - ; v96 -> v8 & v8 -> v96 - v_mov_b32 v200, v8 - v_mov_b32 v8, v22 - v_mov_b32 v22, v200 - ; v26 -> v50 & v50 -> v26 - v_mov_b32 v200, v50 - v_mov_b32 v50, v26 - v_mov_b32 v26, v200 - ; v50 -> v44 & v44 -> v50 - v_mov_b32 v200, v44 - v_mov_b32 v44, v26 - v_mov_b32 v26, v200 - ; v44 -> v99 & v99 -> v44 - v_mov_b32 v200, v99 - v_mov_b32 v99, v26 - v_mov_b32 v26, v200 - ; v99 -> v80 & v80 -> v99 - v_mov_b32 v200, v80 - v_mov_b32 v80, v26 - v_mov_b32 v26, v200 - ; v80 -> v88 & v88 -> v80 - v_mov_b32 v200, v88 - v_mov_b32 v88, v26 - v_mov_b32 v26, v200 - ; v88 -> v30 & v30 -> v88 - v_mov_b32 v200, v30 - v_mov_b32 v30, v26 - v_mov_b32 v26, v200 - ; v30 -> v36 & v36 -> v30 - v_mov_b32 v200, v36 - v_mov_b32 v36, v26 - v_mov_b32 v26, v200 - ; v36 -> v109 & v109 -> v36 - v_mov_b32 v200, v109 - v_mov_b32 v109, v26 - v_mov_b32 v26, v200 - ; v109 -> v71 & v71 -> v109 - v_mov_b32 v200, v71 - v_mov_b32 v71, v26 - v_mov_b32 v26, v200 - ; v71 -> v91 & v91 -> v71 - v_mov_b32 v200, v91 - v_mov_b32 v91, v26 - v_mov_b32 v26, v200 - ; v91 -> v22 & v22 -> v91 - v_mov_b32 v200, v22 - v_mov_b32 v22, v26 - v_mov_b32 v26, v200 - ; v28 -> v51 & v51 -> v28 - v_mov_b32 v200, v51 - v_mov_b32 v51, v28 - v_mov_b32 v28, v200 - ; v51 -> v48 & v48 -> v51 - v_mov_b32 v200, v48 - v_mov_b32 v48, v28 - v_mov_b32 v28, v200 - ; v48 -> v104 & v104 -> v48 - v_mov_b32 v200, v104 - v_mov_b32 v104, v28 - v_mov_b32 v28, v200 - ; v104 -> v78 & v78 -> v104 - v_mov_b32 v200, v78 - v_mov_b32 v78, v28 - v_mov_b32 v28, v200 - ; v78 -> v84 & v84 -> v78 - v_mov_b32 v200, v84 - v_mov_b32 v84, v28 - v_mov_b32 v28, v200 - ; v84 -> v29 & v29 -> v84 - v_mov_b32 v200, v29 - v_mov_b32 v29, v28 - v_mov_b32 v28, v200 - ; v29 -> v55 & v55 -> v29 - v_mov_b32 v200, v55 - v_mov_b32 v55, v28 - v_mov_b32 v28, v200 - ; v55 -> v43 & v43 -> v55 - v_mov_b32 v200, v43 - v_mov_b32 v43, v28 - v_mov_b32 v28, v200 - ; v43 -> v102 & v102 -> v43 - v_mov_b32 v200, v102 - v_mov_b32 v102, v28 - v_mov_b32 v28, v200 - ; v102 -> v74 & v74 -> v102 - v_mov_b32 v200, v74 - v_mov_b32 v74, v28 - v_mov_b32 v28, v200 - ; v74 -> v82 & v82 -> v74 - v_mov_b32 v200, v82 - v_mov_b32 v82, v28 - v_mov_b32 v28, v200 - ;NOP 82(28) -> 28 - ; v45 -> v103 & v103 -> v45 - v_mov_b32 v200, v103 - v_mov_b32 v103, v45 - v_mov_b32 v45, v200 - ; v103 -> v75 & v75 -> v103 - v_mov_b32 v200, v75 - v_mov_b32 v75, v45 - v_mov_b32 v45, v200 - ; v75 -> v86 & v86 -> v75 - v_mov_b32 v200, v86 - v_mov_b32 v86, v45 - v_mov_b32 v45, v200 - ; v86 -> v26 & v26 -> v86 - v_mov_b32 v200, v26 - v_mov_b32 v26, v45 - v_mov_b32 v45, v200 - ; v52 -> v45 & v45 -> v52 - v_mov_b32 v200, v45 - v_mov_b32 v45, v52 - v_mov_b32 v52, v200 - ; v214 -> v52 & v52 -> v214 - v_mov_b32 v200, v52 - v_mov_b32 v52, v214 - v_mov_b32 v214, v200 - - - v_dual_mov_b32 v149, v135 :: v_dual_mov_b32 v150, v136 -.LBB0_13: ; %Flow1143 - - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_dual_mul_f32 v139, s5, v133 :: v_dual_and_b32 v0, 0x60, v0 - v_or_b32_e32 v118, s2, v149 - v_dual_mul_f32 v140, s5, v132 :: v_dual_mul_f32 v141, s5, v131 - s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) - v_add_nc_u32_e32 v0, s3, v0 - v_or_b32_e32 v119, v0, v150 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_mul_lo_u32 v144, v119, s4 - v_add_nc_u32_e32 v0, v118, v144 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v1, 31, v0 - v_lshlrev_b64 v[0:1], 2, v[0:1] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v0, vcc_lo, s0, v0 - v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo - global_load_b128 v[134:137], v[0:1], off - s_waitcnt vmcnt(0) - v_dual_mul_f32 v138, s5, v124 :: v_dual_fmac_f32 v141, s6, v137 - s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) - v_dual_fmac_f32 v138, s6, v134 :: v_dual_add_nc_u32 v145, s4, v144 - v_fmac_f32_e32 v139, s6, v135 - v_mul_f32_e32 v137, s5, v126 - v_dual_mul_f32 v135, s5, v128 :: v_dual_add_nc_u32 v142, v118, v145 - v_fmac_f32_e32 v140, s6, v136 - v_mul_f32_e32 v134, s5, v129 - v_dual_mul_f32 v128, s5, v123 :: v_dual_mul_f32 v129, s5, v122 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v143, 31, v142 - global_store_b128 v[0:1], v[138:141], off - v_add_nc_u32_e32 v138, s4, v145 - v_mul_f32_e32 v136, s5, v127 - v_lshlrev_b64 v[124:125], 2, v[142:143] - v_add_co_u32 v124, vcc_lo, s0, v124 - s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) - v_add_co_ci_u32_e32 v125, vcc_lo, s1, v125, vcc_lo - global_load_b128 v[130:133], v[124:125], off - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v137, s6, v133 :: v_dual_add_nc_u32 v0, v118, v138 - v_ashrrev_i32_e32 v1, 31, v0 - v_dual_fmac_f32 v135, s6, v131 :: v_dual_fmac_f32 v136, s6, v132 - v_dual_mul_f32 v131, s5, v120 :: v_dual_fmac_f32 v134, s6, v130 - s_delay_alu instid0(VALU_DEP_3) - v_lshlrev_b64 v[0:1], 2, v[0:1] - global_store_b128 v[124:125], v[134:137], off - v_add_nc_u32_e32 v134, s4, v138 - v_add_co_u32 v0, vcc_lo, s0, v0 - v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo - global_load_b128 v[124:127], v[0:1], off - s_waitcnt vmcnt(0) - v_fmac_f32_e32 v129, s6, v125 - v_dual_mul_f32 v125, s5, v116 :: v_dual_add_nc_u32 v132, v118, v134 - v_fmac_f32_e32 v131, s6, v127 - v_dual_mul_f32 v127, s5, v114 :: v_dual_mul_f32 v130, s5, v121 - v_fmac_f32_e32 v128, s6, v124 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) - v_ashrrev_i32_e32 v133, 31, v132 - v_mul_f32_e32 v124, s5, v117 - v_fmac_f32_e32 v130, s6, v126 - s_delay_alu instid0(VALU_DEP_3) - v_lshlrev_b64 v[120:121], 2, v[132:133] - global_store_b128 v[0:1], v[128:131], off - v_add_nc_u32_e32 v1, 32, v118 - v_add_nc_u32_e32 v0, 0x60, v118 - v_add_co_u32 v132, vcc_lo, s0, v120 - v_add_co_ci_u32_e32 v133, vcc_lo, s1, v121, vcc_lo - global_load_b128 v[120:123], v[132:133], off - s_waitcnt vmcnt(0) - v_fmac_f32_e32 v125, s6, v121 - v_mul_f32_e32 v121, s5, v112 - v_dual_fmac_f32 v127, s6, v123 :: v_dual_add_nc_u32 v128, v1, v144 - v_dual_mul_f32 v123, s5, v110 :: v_dual_mul_f32 v126, s5, v115 - v_fmac_f32_e32 v124, s6, v120 - s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) - v_ashrrev_i32_e32 v129, 31, v128 - v_mul_f32_e32 v120, s5, v113 - v_fmac_f32_e32 v126, s6, v122 - s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) - v_lshlrev_b64 v[114:115], 2, v[128:129] - global_store_b128 v[132:133], v[124:127], off - v_add_nc_u32_e32 v124, v1, v145 - v_add_co_u32 v128, vcc_lo, s0, v114 - v_add_co_ci_u32_e32 v129, vcc_lo, s1, v115, vcc_lo - v_ashrrev_i32_e32 v125, 31, v124 - global_load_b128 v[114:117], v[128:129], off - s_waitcnt vmcnt(0) - v_fmac_f32_e32 v123, s6, v117 - v_dual_mul_f32 v117, s5, v106 :: v_dual_mul_f32 v122, s5, v111 - v_lshlrev_b64 v[110:111], 2, v[124:125] - v_dual_fmac_f32 v120, s6, v114 :: v_dual_fmac_f32 v121, s6, v115 - v_mul_f32_e32 v114, s5, v109 - s_delay_alu instid0(VALU_DEP_4) - v_fmac_f32_e32 v122, s6, v116 - v_mul_f32_e32 v116, s5, v107 - v_add_co_u32 v124, vcc_lo, s0, v110 - v_add_co_ci_u32_e32 v125, vcc_lo, s1, v111, vcc_lo - global_store_b128 v[128:129], v[120:123], off - v_dual_mul_f32 v115, s5, v108 :: v_dual_add_nc_u32 v120, v1, v138 - global_load_b128 v[110:113], v[124:125], off - v_ashrrev_i32_e32 v121, 31, v120 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_lshlrev_b64 v[106:107], 2, v[120:121] - v_add_co_u32 v120, vcc_lo, s0, v106 - s_delay_alu instid0(VALU_DEP_2) - v_add_co_ci_u32_e32 v121, vcc_lo, s1, v107, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v114, s6, v110 :: v_dual_fmac_f32 v115, s6, v111 - v_dual_fmac_f32 v116, s6, v112 :: v_dual_fmac_f32 v117, s6, v113 - v_dual_mul_f32 v112, s5, v103 :: v_dual_mul_f32 v113, s5, v102 - v_dual_mul_f32 v110, s5, v105 :: v_dual_mul_f32 v111, s5, v104 - global_store_b128 v[124:125], v[114:117], off - global_load_b128 v[106:109], v[120:121], off - v_add_nc_u32_e32 v114, v1, v134 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v115, 31, v114 - v_lshlrev_b64 v[102:103], 2, v[114:115] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v114, vcc_lo, s0, v102 - v_add_co_ci_u32_e32 v115, vcc_lo, s1, v103, vcc_lo - v_add_nc_u32_e32 v102, 64, v118 - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v110, s6, v106 :: v_dual_fmac_f32 v111, s6, v107 - v_dual_fmac_f32 v112, s6, v108 :: v_dual_fmac_f32 v113, s6, v109 - v_mul_f32_e32 v109, s5, v99 - v_dual_mul_f32 v107, s5, v101 :: v_dual_mul_f32 v108, s5, v100 - global_store_b128 v[120:121], v[110:113], off - global_load_b128 v[103:106], v[114:115], off - v_dual_mul_f32 v110, s5, v98 :: v_dual_add_nc_u32 v111, v102, v144 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v112, 31, v111 - v_lshlrev_b64 v[98:99], 2, v[111:112] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v111, vcc_lo, s0, v98 - v_add_co_ci_u32_e32 v112, vcc_lo, s1, v99, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v107, s6, v103 :: v_dual_fmac_f32 v108, s6, v104 - v_dual_fmac_f32 v109, s6, v105 :: v_dual_fmac_f32 v110, s6, v106 - v_dual_mul_f32 v104, s5, v96 :: v_dual_mul_f32 v105, s5, v95 - v_dual_mul_f32 v106, s5, v94 :: v_dual_mul_f32 v103, s5, v97 - global_store_b128 v[114:115], v[107:110], off - global_load_b128 v[98:101], v[111:112], off - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v104, s6, v99 :: v_dual_mul_f32 v99, s5, v92 - v_add_nc_u32_e32 v107, v102, v145 - v_fmac_f32_e32 v103, s6, v98 - v_dual_fmac_f32 v105, s6, v100 :: v_dual_fmac_f32 v106, s6, v101 - v_mul_f32_e32 v100, s5, v91 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) - v_ashrrev_i32_e32 v108, 31, v107 - v_dual_mul_f32 v101, s5, v90 :: v_dual_mul_f32 v98, s5, v93 - global_store_b128 v[111:112], v[103:106], off - v_add_nc_u32_e32 v103, v102, v138 - v_lshlrev_b64 v[94:95], 2, v[107:108] - v_ashrrev_i32_e32 v104, 31, v103 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) - v_add_co_u32 v107, vcc_lo, s0, v94 - v_add_co_ci_u32_e32 v108, vcc_lo, s1, v95, vcc_lo - s_delay_alu instid0(VALU_DEP_3) - v_lshlrev_b64 v[90:91], 2, v[103:104] - global_load_b128 v[94:97], v[107:108], off - v_add_co_u32 v103, vcc_lo, s0, v90 - v_add_co_ci_u32_e32 v104, vcc_lo, s1, v91, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v98, s6, v94 :: v_dual_fmac_f32 v99, s6, v95 - v_dual_fmac_f32 v100, s6, v96 :: v_dual_fmac_f32 v101, s6, v97 - v_dual_mul_f32 v96, s5, v87 :: v_dual_mul_f32 v97, s5, v86 - v_dual_mul_f32 v94, s5, v89 :: v_dual_mul_f32 v95, s5, v88 - global_store_b128 v[107:108], v[98:101], off - global_load_b128 v[90:93], v[103:104], off - v_add_nc_u32_e32 v98, v102, v134 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v99, 31, v98 - v_lshlrev_b64 v[86:87], 2, v[98:99] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v98, vcc_lo, s0, v86 - v_add_co_ci_u32_e32 v99, vcc_lo, s1, v87, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v94, s6, v90 :: v_dual_fmac_f32 v95, s6, v91 - v_dual_fmac_f32 v96, s6, v92 :: v_dual_fmac_f32 v97, s6, v93 - v_dual_mul_f32 v92, s5, v83 :: v_dual_mul_f32 v93, s5, v82 - v_dual_mul_f32 v90, s5, v85 :: v_dual_mul_f32 v91, s5, v84 - global_store_b128 v[103:104], v[94:97], off - global_load_b128 v[86:89], v[98:99], off - v_add_nc_u32_e32 v94, v0, v144 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v95, 31, v94 - v_lshlrev_b64 v[82:83], 2, v[94:95] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v94, vcc_lo, s0, v82 - v_add_co_ci_u32_e32 v95, vcc_lo, s1, v83, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v90, s6, v86 :: v_dual_fmac_f32 v91, s6, v87 - v_dual_fmac_f32 v92, s6, v88 :: v_dual_fmac_f32 v93, s6, v89 - v_dual_mul_f32 v87, s5, v80 :: v_dual_mul_f32 v88, s5, v79 - v_dual_mul_f32 v89, s5, v78 :: v_dual_mul_f32 v86, s5, v81 - global_store_b128 v[98:99], v[90:93], off - global_load_b128 v[82:85], v[94:95], off - s_waitcnt vmcnt(0) - v_fmac_f32_e32 v87, s6, v83 - v_dual_mul_f32 v83, s5, v76 :: v_dual_add_nc_u32 v90, v0, v145 - v_fmac_f32_e32 v86, s6, v82 - v_dual_fmac_f32 v88, s6, v84 :: v_dual_fmac_f32 v89, s6, v85 - v_mul_f32_e32 v84, s5, v75 - s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2) - v_ashrrev_i32_e32 v91, 31, v90 - v_dual_mul_f32 v85, s5, v74 :: v_dual_mul_f32 v82, s5, v77 - global_store_b128 v[94:95], v[86:89], off - v_add_nc_u32_e32 v86, v0, v138 - v_lshlrev_b64 v[78:79], 2, v[90:91] - v_ashrrev_i32_e32 v87, 31, v86 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) - v_add_co_u32 v90, vcc_lo, s0, v78 - v_add_co_ci_u32_e32 v91, vcc_lo, s1, v79, vcc_lo - s_delay_alu instid0(VALU_DEP_3) - v_lshlrev_b64 v[74:75], 2, v[86:87] - global_load_b128 v[78:81], v[90:91], off - v_add_co_u32 v86, vcc_lo, s0, v74 - v_add_co_ci_u32_e32 v87, vcc_lo, s1, v75, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v82, s6, v78 :: v_dual_fmac_f32 v83, s6, v79 - v_dual_fmac_f32 v84, s6, v80 :: v_dual_fmac_f32 v85, s6, v81 - v_dual_mul_f32 v80, s5, v71 :: v_dual_mul_f32 v81, s5, v70 - v_dual_mul_f32 v78, s5, v73 :: v_dual_mul_f32 v79, s5, v72 - global_store_b128 v[90:91], v[82:85], off - global_load_b128 v[74:77], v[86:87], off - v_add_nc_u32_e32 v82, v0, v134 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v83, 31, v82 - v_lshlrev_b64 v[70:71], 2, v[82:83] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v82, vcc_lo, s0, v70 - v_add_co_ci_u32_e32 v83, vcc_lo, s1, v71, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v78, s6, v74 :: v_dual_fmac_f32 v79, s6, v75 - v_dual_fmac_f32 v80, s6, v76 :: v_dual_fmac_f32 v81, s6, v77 - v_or_b32_e32 v74, 16, v119 - v_dual_mul_f32 v76, s5, v67 :: v_dual_mul_f32 v77, s5, v66 - v_mul_f32_e32 v75, s5, v68 - global_store_b128 v[86:87], v[78:81], off - global_load_b128 v[70:73], v[82:83], off - v_mul_lo_u32 v80, v74, s4 - v_mul_f32_e32 v74, s5, v69 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) - v_add_nc_u32_e32 v78, v118, v80 - v_ashrrev_i32_e32 v79, 31, v78 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_lshlrev_b64 v[66:67], 2, v[78:79] - v_add_co_u32 v78, vcc_lo, s0, v66 - s_delay_alu instid0(VALU_DEP_2) - v_add_co_ci_u32_e32 v79, vcc_lo, s1, v67, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v74, s6, v70 :: v_dual_fmac_f32 v75, s6, v71 - v_dual_fmac_f32 v76, s6, v72 :: v_dual_fmac_f32 v77, s6, v73 - v_or_b32_e32 v70, 17, v119 - v_dual_mul_f32 v72, s5, v63 :: v_dual_mul_f32 v73, s5, v62 - v_mul_f32_e32 v71, s5, v64 - global_store_b128 v[82:83], v[74:77], off - global_load_b128 v[66:69], v[78:79], off - v_mul_lo_u32 v76, v70, s4 - v_mul_f32_e32 v70, s5, v65 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) - v_add_nc_u32_e32 v74, v118, v76 - v_ashrrev_i32_e32 v75, 31, v74 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_lshlrev_b64 v[62:63], 2, v[74:75] - v_add_co_u32 v74, vcc_lo, s0, v62 - s_delay_alu instid0(VALU_DEP_2) - v_add_co_ci_u32_e32 v75, vcc_lo, s1, v63, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v70, s6, v66 :: v_dual_fmac_f32 v71, s6, v67 - v_dual_fmac_f32 v72, s6, v68 :: v_dual_fmac_f32 v73, s6, v69 - v_or_b32_e32 v66, 18, v119 - v_dual_mul_f32 v68, s5, v59 :: v_dual_mul_f32 v69, s5, v58 - v_mul_f32_e32 v67, s5, v60 - global_store_b128 v[78:79], v[70:73], off - global_load_b128 v[62:65], v[74:75], off - v_mul_lo_u32 v72, v66, s4 - v_mul_f32_e32 v66, s5, v61 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) - v_add_nc_u32_e32 v70, v118, v72 - v_ashrrev_i32_e32 v71, 31, v70 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_lshlrev_b64 v[58:59], 2, v[70:71] - v_add_co_u32 v70, vcc_lo, s0, v58 - s_delay_alu instid0(VALU_DEP_2) - v_add_co_ci_u32_e32 v71, vcc_lo, s1, v59, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v66, s6, v62 :: v_dual_fmac_f32 v67, s6, v63 - v_dual_fmac_f32 v68, s6, v64 :: v_dual_fmac_f32 v69, s6, v65 - v_or_b32_e32 v62, 19, v119 - v_dual_mul_f32 v64, s5, v55 :: v_dual_mul_f32 v65, s5, v54 - v_mul_f32_e32 v63, s5, v56 - global_store_b128 v[74:75], v[66:69], off - global_load_b128 v[58:61], v[70:71], off - v_mul_lo_u32 v68, v62, s4 - v_mul_f32_e32 v62, s5, v57 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) - v_add_nc_u32_e32 v66, v118, v68 - v_ashrrev_i32_e32 v67, 31, v66 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_lshlrev_b64 v[54:55], 2, v[66:67] - v_add_co_u32 v66, vcc_lo, s0, v54 - s_delay_alu instid0(VALU_DEP_2) - v_add_co_ci_u32_e32 v67, vcc_lo, s1, v55, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v62, s6, v58 :: v_dual_fmac_f32 v63, s6, v59 - v_dual_fmac_f32 v64, s6, v60 :: v_dual_fmac_f32 v65, s6, v61 - v_dual_mul_f32 v60, s5, v51 :: v_dual_mul_f32 v61, s5, v50 - v_dual_mul_f32 v58, s5, v53 :: v_dual_mul_f32 v59, s5, v52 - global_store_b128 v[70:71], v[62:65], off - global_load_b128 v[54:57], v[66:67], off - v_add_nc_u32_e32 v62, v1, v80 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v63, 31, v62 - v_lshlrev_b64 v[50:51], 2, v[62:63] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v62, vcc_lo, s0, v50 - v_add_co_ci_u32_e32 v63, vcc_lo, s1, v51, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v58, s6, v54 :: v_dual_fmac_f32 v59, s6, v55 - v_dual_fmac_f32 v60, s6, v56 :: v_dual_fmac_f32 v61, s6, v57 - v_dual_mul_f32 v56, s5, v47 :: v_dual_mul_f32 v57, s5, v46 - v_dual_mul_f32 v54, s5, v49 :: v_dual_mul_f32 v55, s5, v48 - global_store_b128 v[66:67], v[58:61], off - global_load_b128 v[50:53], v[62:63], off - v_add_nc_u32_e32 v58, v1, v76 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v59, 31, v58 - v_lshlrev_b64 v[46:47], 2, v[58:59] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v58, vcc_lo, s0, v46 - v_add_co_ci_u32_e32 v59, vcc_lo, s1, v47, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v54, s6, v50 :: v_dual_fmac_f32 v55, s6, v51 - v_dual_fmac_f32 v56, s6, v52 :: v_dual_fmac_f32 v57, s6, v53 - v_dual_mul_f32 v52, s5, v43 :: v_dual_mul_f32 v53, s5, v42 - v_dual_mul_f32 v50, s5, v45 :: v_dual_mul_f32 v51, s5, v44 - global_store_b128 v[62:63], v[54:57], off - global_load_b128 v[46:49], v[58:59], off - v_add_nc_u32_e32 v54, v1, v72 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v55, 31, v54 - v_lshlrev_b64 v[42:43], 2, v[54:55] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v54, vcc_lo, s0, v42 - v_add_co_ci_u32_e32 v55, vcc_lo, s1, v43, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v50, s6, v46 :: v_dual_fmac_f32 v51, s6, v47 - v_dual_fmac_f32 v52, s6, v48 :: v_dual_fmac_f32 v53, s6, v49 - v_dual_mul_f32 v48, s5, v39 :: v_dual_mul_f32 v49, s5, v38 - v_dual_mul_f32 v46, s5, v41 :: v_dual_mul_f32 v47, s5, v40 - global_store_b128 v[58:59], v[50:53], off - global_load_b128 v[42:45], v[54:55], off - v_add_nc_u32_e32 v50, v1, v68 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v51, 31, v50 - v_lshlrev_b64 v[38:39], 2, v[50:51] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v50, vcc_lo, s0, v38 - v_add_co_ci_u32_e32 v51, vcc_lo, s1, v39, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v46, s6, v42 :: v_dual_fmac_f32 v47, s6, v43 - v_dual_fmac_f32 v48, s6, v44 :: v_dual_fmac_f32 v49, s6, v45 - v_dual_mul_f32 v44, s5, v35 :: v_dual_mul_f32 v45, s5, v34 - v_dual_mul_f32 v42, s5, v37 :: v_dual_mul_f32 v43, s5, v36 - global_store_b128 v[54:55], v[46:49], off - global_load_b128 v[38:41], v[50:51], off - v_add_nc_u32_e32 v46, v102, v80 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v47, 31, v46 - v_lshlrev_b64 v[34:35], 2, v[46:47] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v46, vcc_lo, s0, v34 - v_add_co_ci_u32_e32 v47, vcc_lo, s1, v35, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v42, s6, v38 :: v_dual_fmac_f32 v43, s6, v39 - v_dual_fmac_f32 v44, s6, v40 :: v_dual_fmac_f32 v45, s6, v41 - v_dual_mul_f32 v40, s5, v31 :: v_dual_mul_f32 v41, s5, v30 - v_dual_mul_f32 v38, s5, v33 :: v_dual_mul_f32 v39, s5, v32 - global_store_b128 v[50:51], v[42:45], off - global_load_b128 v[34:37], v[46:47], off - v_add_nc_u32_e32 v42, v102, v76 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v43, 31, v42 - v_lshlrev_b64 v[30:31], 2, v[42:43] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v42, vcc_lo, s0, v30 - v_add_co_ci_u32_e32 v43, vcc_lo, s1, v31, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v38, s6, v34 :: v_dual_fmac_f32 v39, s6, v35 - v_dual_fmac_f32 v40, s6, v36 :: v_dual_fmac_f32 v41, s6, v37 - v_dual_mul_f32 v36, s5, v27 :: v_dual_mul_f32 v37, s5, v26 - v_dual_mul_f32 v34, s5, v29 :: v_dual_mul_f32 v35, s5, v28 - global_store_b128 v[46:47], v[38:41], off - global_load_b128 v[30:33], v[42:43], off - v_add_nc_u32_e32 v38, v102, v72 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v39, 31, v38 - v_lshlrev_b64 v[26:27], 2, v[38:39] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v38, vcc_lo, s0, v26 - v_add_co_ci_u32_e32 v39, vcc_lo, s1, v27, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v34, s6, v30 :: v_dual_fmac_f32 v35, s6, v31 - v_dual_fmac_f32 v36, s6, v32 :: v_dual_fmac_f32 v37, s6, v33 - v_dual_mul_f32 v32, s5, v23 :: v_dual_mul_f32 v33, s5, v22 - v_dual_mul_f32 v30, s5, v25 :: v_dual_mul_f32 v31, s5, v24 - global_store_b128 v[42:43], v[34:37], off - global_load_b128 v[26:29], v[38:39], off - v_add_nc_u32_e32 v34, v102, v68 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v35, 31, v34 - v_lshlrev_b64 v[22:23], 2, v[34:35] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v34, vcc_lo, s0, v22 - v_add_co_ci_u32_e32 v35, vcc_lo, s1, v23, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v30, s6, v26 :: v_dual_fmac_f32 v31, s6, v27 - v_dual_fmac_f32 v32, s6, v28 :: v_dual_fmac_f32 v33, s6, v29 - v_dual_mul_f32 v28, s5, v19 :: v_dual_mul_f32 v29, s5, v18 - v_dual_mul_f32 v26, s5, v21 :: v_dual_mul_f32 v27, s5, v20 - global_store_b128 v[38:39], v[30:33], off - global_load_b128 v[22:25], v[34:35], off - v_add_nc_u32_e32 v30, v0, v80 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v31, 31, v30 - v_lshlrev_b64 v[18:19], 2, v[30:31] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v30, vcc_lo, s0, v18 - v_add_co_ci_u32_e32 v31, vcc_lo, s1, v19, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v26, s6, v22 :: v_dual_fmac_f32 v27, s6, v23 - v_dual_fmac_f32 v28, s6, v24 :: v_dual_fmac_f32 v29, s6, v25 - v_dual_mul_f32 v24, s5, v15 :: v_dual_mul_f32 v25, s5, v14 - v_dual_mul_f32 v22, s5, v17 :: v_dual_mul_f32 v23, s5, v16 - global_store_b128 v[34:35], v[26:29], off - global_load_b128 v[18:21], v[30:31], off - v_add_nc_u32_e32 v26, v0, v76 - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) - v_ashrrev_i32_e32 v27, 31, v26 - v_lshlrev_b64 v[14:15], 2, v[26:27] - s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) - v_add_co_u32 v26, vcc_lo, s0, v14 - v_add_co_ci_u32_e32 v27, vcc_lo, s1, v15, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v22, s6, v18 :: v_dual_fmac_f32 v23, s6, v19 - v_dual_fmac_f32 v24, s6, v20 :: v_dual_fmac_f32 v25, s6, v21 - v_dual_mul_f32 v20, s5, v11 :: v_dual_mul_f32 v21, s5, v10 - v_dual_mul_f32 v18, s5, v13 :: v_dual_mul_f32 v19, s5, v12 - global_store_b128 v[30:31], v[22:25], off - global_load_b128 v[14:17], v[26:27], off - v_add_nc_u32_e32 v22, v0, v72 - v_add_nc_u32_e32 v0, v0, v68 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) - v_ashrrev_i32_e32 v23, 31, v22 - v_ashrrev_i32_e32 v1, 31, v0 - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) - v_lshlrev_b64 v[10:11], 2, v[22:23] - v_lshlrev_b64 v[0:1], 2, v[0:1] - s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) - v_add_co_u32 v22, vcc_lo, s0, v10 - v_add_co_ci_u32_e32 v23, vcc_lo, s1, v11, vcc_lo - s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) - v_add_co_u32 v0, vcc_lo, s0, v0 - v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v18, s6, v14 :: v_dual_fmac_f32 v19, s6, v15 - v_dual_fmac_f32 v20, s6, v16 :: v_dual_fmac_f32 v21, s6, v17 - v_dual_mul_f32 v14, s5, v9 :: v_dual_mul_f32 v15, s5, v8 - v_dual_mul_f32 v16, s5, v7 :: v_dual_mul_f32 v17, s5, v6 - global_store_b128 v[26:27], v[18:21], off - global_load_b128 v[10:13], v[22:23], off - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v14, s6, v10 :: v_dual_fmac_f32 v15, s6, v11 - v_dual_fmac_f32 v16, s6, v12 :: v_dual_fmac_f32 v17, s6, v13 - v_dual_mul_f32 v10, s5, v5 :: v_dual_mul_f32 v11, s5, v4 - v_dual_mul_f32 v12, s5, v3 :: v_dual_mul_f32 v13, s5, v2 - global_store_b128 v[22:23], v[14:17], off - global_load_b128 v[6:9], v[0:1], off - s_waitcnt vmcnt(0) - v_dual_fmac_f32 v11, s6, v7 :: v_dual_fmac_f32 v10, s6, v6 - v_dual_fmac_f32 v12, s6, v8 :: v_dual_fmac_f32 v13, s6, v9 - global_store_b128 v[0:1], v[10:13], off - s_nop 0 - s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) - s_endpgm - .section .rodata,"a",@progbits - .p2align 6, 0x0 - .amdhsa_kernel kernel - .amdhsa_group_segment_fixed_size 8320 - .amdhsa_private_segment_fixed_size 0 - .amdhsa_kernarg_size 36 - .amdhsa_user_sgpr_count 14 - .amdhsa_user_sgpr_dispatch_ptr 0 - .amdhsa_user_sgpr_queue_ptr 0 - .amdhsa_user_sgpr_kernarg_segment_ptr 1 - .amdhsa_user_sgpr_dispatch_id 0 - .amdhsa_user_sgpr_private_segment_size 0 - .amdhsa_wavefront_size32 1 - .amdhsa_uses_dynamic_stack 0 - .amdhsa_enable_private_segment 0 - .amdhsa_system_sgpr_workgroup_id_x 1 - .amdhsa_system_sgpr_workgroup_id_y 1 - .amdhsa_system_sgpr_workgroup_id_z 0 - .amdhsa_system_sgpr_workgroup_info 0 - .amdhsa_system_vgpr_workitem_id 0 - .amdhsa_next_free_vgpr 216 - .amdhsa_next_free_sgpr 16 - .amdhsa_float_round_mode_32 0 - .amdhsa_float_round_mode_16_64 0 - .amdhsa_float_denorm_mode_32 3 - .amdhsa_float_denorm_mode_16_64 3 - .amdhsa_dx10_clamp 1 - .amdhsa_ieee_mode 1 - .amdhsa_fp16_overflow 0 - .amdhsa_workgroup_processor_mode 0 - .amdhsa_memory_ordered 1 - .amdhsa_forward_progress 0 - .amdhsa_shared_vgpr_count 0 - .amdhsa_exception_fp_ieee_invalid_op 0 - .amdhsa_exception_fp_denorm_src 0 - .amdhsa_exception_fp_ieee_div_zero 0 - .amdhsa_exception_fp_ieee_overflow 0 - .amdhsa_exception_fp_ieee_underflow 0 - .amdhsa_exception_fp_ieee_inexact 0 - .amdhsa_exception_int_div_zero 0 - .end_amdhsa_kernel - .text -.Lfunc_end0: - .size kernel, .Lfunc_end0-kernel - ; -- End function - .section .AMDGPU.csdata,"",@progbits -; Kernel info: -; codeLenInByte = 6972 -; NumSgprs: 18 -; NumVgprs: 208 -; ScratchSize: 0 -; MemoryBound: 0 -; FloatMode: 240 -; IeeeMode: 1 -; LDSByteSize: 8320 bytes/workgroup (compile time only) -; SGPRBlocks: 2 -; VGPRBlocks: 25 -; NumSGPRsForWavesPerEU: 18 -; NumVGPRsForWavesPerEU: 248 -; Occupancy: 7 -; WaveLimiterHint : 0 -; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 -; COMPUTE_PGM_RSRC2:USER_SGPR: 14 -; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 -; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 -; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 -; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 -; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 - .text - .p2alignl 7, 3214868480 - .fill 96, 4, 3214868480 - .ident "clang version 19.0.0git (git@github.amd.com:Compute-Mirrors/llvm-project b3dbdf4f03718d63a3292f784216fddb3e73d521)" - .section ".note.GNU-stack","",@progbits - .addrsig - .amdgpu_metadata ---- -amdhsa.kernels: - - .args: - - .address_space: global - .offset: 0 - .size: 8 - .value_kind: global_buffer - - .address_space: global - .offset: 8 - .size: 8 - .value_kind: global_buffer - - .address_space: global - .offset: 16 - .size: 8 - .value_kind: global_buffer - - .offset: 24 - .size: 4 - .value_kind: by_value - - .offset: 28 - .size: 4 - .value_kind: by_value - - .offset: 32 - .size: 4 - .value_kind: by_value - .group_segment_fixed_size: 8320 - .kernarg_segment_align: 8 - .kernarg_segment_size: 36 - .language: OpenCL C - .language_version: - - 2 - - 0 - .max_flat_workgroup_size: 128 - .name: kernel - .private_segment_fixed_size: 0 - .sgpr_count: 60 - .sgpr_spill_count: 0 - .symbol: kernel.kd - .uniform_work_group_size: 1 - .uses_dynamic_stack: false - .vgpr_count: 216 - .vgpr_spill_count: 0 - .wavefront_size: 32 - .workgroup_processor_mode: 0 -amdhsa.target: amdgcn-amd-amdhsa--gfx1100 -amdhsa.version: - - 1 - - 2 -... - - .end_amdgpu_metadata diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.2_stage.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.2_stage.cu deleted file mode 100644 index 32879b1e..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.2_stage.cu +++ /dev/null @@ -1,508 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ half4 __WMMA_8_16_16_half_half(half8 a, half4 b, half4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b), *c_pk = (int *) (&c); - asm( "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 { %0, %1 }, { %2, %3, %4, %5 }, { %6, %7 }, { %0, %1 };" - : "+r"(c_pk[0]), "+r"(c_pk[1]): "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(128) wmma_example(half* data0, const half* data1, const half* data2, int N, int K) { - int grid_m = blockIdx.x; /* M//64 */ - int grid_n = blockIdx.y; /* N//128 */ - int threads = threadIdx.x; /* 128 */ - int wg_m = (threads/64); // 0 or 1 for 1st and 3rd blocks of b_m=16xb_k=16 vs 2nd and 4th blocks - int wg_n = (threads/32)%2; // 0 or 1 for 1st, 3rd, 5th, 7th blocks of b_n=16xb_k=16 vs 2nd, 4th, 6th, 8th blocks - differs from triton - int wg_threads = threads%32; - int num_k_blocks = K / 64; - - // load indexes - size_t global_a_off = ((grid_m * 64) * K) + ((threads % 8) * 8) + ((threads / 8) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // swizzled smem store offsets - columns of smem are swizzled - // here's a link to a description of the triton: https://github.com/triton-lang/triton/discussions/2026#discussioncomment-6746579 - // see also the thunderkittens impl: https://github.com/HazyResearch/ThunderKittens/blob/main/include/types/shared/st.cuh - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // r15 - size_t store_smem_b_off = ((threads / 16) * 128) + (((threads / 16) * 8) ^ ((threads % 16) * 8)); // r19\ - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled ldmatrix - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; // r293 - size_t load_smem_a_phase = (threads / 16) % 2; // r4 - - size_t load_smem_b_row = (threads % 16) * 128; // r299 - size_t load_smem_b_phase = (wg_n * 2) + (((threads / 16) % 2)); // r297 -- this differs from the generated triton kernel (swapped order) - - size_t load_smem_a_0_k_0 = load_smem_a_row + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); // r38 - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (32 * 64); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - - size_t load_smem_a_0_k_1 = load_smem_a_row + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); // r58 = r293 + r316; - size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + (32 * 64); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - size_t load_smem_a_0_k_2 = load_smem_a_row + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); // r59 = r293 + r319; - size_t load_smem_a_1_k_2 = load_smem_a_0_k_2 + (32 * 64); - size_t load_smem_b_0_k_2 = load_smem_b_0_k_0 + (32 * 128); - size_t load_smem_b_1_k_2 = load_smem_b_1_k_0 + (32 * 128); - size_t load_smem_b_2_k_2 = load_smem_b_2_k_0 + (32 * 128); - size_t load_smem_b_3_k_2 = load_smem_b_3_k_0 + (32 * 128); - - size_t load_smem_a_0_k_3 = load_smem_a_row + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); // r60 = r293 + r322; - size_t load_smem_a_1_k_3 = load_smem_a_0_k_3 + (32 * 64); - size_t load_smem_b_0_k_3 = load_smem_b_0_k_0 + (48 * 128); - size_t load_smem_b_1_k_3 = load_smem_b_1_k_0 + (48 * 128); - size_t load_smem_b_2_k_3 = load_smem_b_2_k_0 + (48 * 128); - size_t load_smem_b_3_k_3 = load_smem_b_3_k_0 + (48 * 128); - - // create shared mem (A_1 8192 bytes, A_2 8192 bytes, B_1 16384 bytes, B2_16384 bytes) - __shared__ alignas(16) char smem[49152]; - - // create accs (16 WMMAs and 4 output elements each) and zero - half4 acc_frag_0_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements (2) - half8 a_frag_0; - half8 a_frag_1; - - // create register for block B elements (8) - half4 b_frag_0; - half4 b_frag_1; - half4 b_frag_2; - half4 b_frag_3; - half4 b_frag_4; - half4 b_frag_5; - half4 b_frag_6; - half4 b_frag_7; - - half *smem_a_even = (half *)(smem); - half *smem_a_odd = (half *)(smem + 8192); - half *smem_b_even = (half *)(smem + 16384); - half *smem_b_odd = (half *)(smem + 32768); - - // https://developer.nvidia.com/blog/controlling-data-movement-to-boost-performance-on-ampere-architecture/ - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#asynchronous-data-copies - - // start first pre-fetch load A - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start first pre-fetch load B - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - __syncthreads(); - - // start second pre-fetch load A - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start second pre-fetch load B - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - - // wait on needed prefetch value - __pipeline_wait_prior(0); // TODO: this enables fast iterations, but incorrect results with 1 (it shouldn't) - __syncthreads(); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - // BLOCK_K==4: unroll 4 iterations of ldmatrix/wmma - half *smem_a_curr = (block_k % 2) ? smem_a_even : smem_a_odd; - half *smem_b_curr = (block_k % 2) ? smem_b_even : smem_b_odd; - - // first load 16 K elements and 16 WMMAs: BLOCK_M==2 * BLOCK_N==8 - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_0]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_0]); - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_1]); - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_2]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_2]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_2]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_2]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_2]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_2]); - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_7, acc_frag_1_7); - - // last 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_3]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_3]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_3]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_3]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_3]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_3]); - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1, b_frag_7, acc_frag_1_7); - - // prefetch next iteration if needed - __syncthreads(); - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - - global_a_off += 64; - global_b_off += 64 * N; - } - __pipeline_commit(); - - if (block_k < num_k_blocks-1) { - __pipeline_wait_prior(1); - __syncthreads(); - } - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // // store registers to smem first, then read back to do float4 writes to global - // float *smem_d = (float *)(smem); - // size_t smem_d_off = (wg_m * 16 * N_PAD) + (wg_n * 16) + ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N_PAD); - // smem_d[smem_d_off + 0 + ( 0*8) ] = acc_frag_0_0.x; - // smem_d[smem_d_off + 1 + ( 0*8) ] = acc_frag_0_0.y; - // smem_d[smem_d_off + 0 + ( 0*8) + (8*N_PAD)] = acc_frag_0_0.z; - // smem_d[smem_d_off + 1 + ( 0*8) + (8*N_PAD)] = acc_frag_0_0.w; - // smem_d[smem_d_off + 0 + ( 1*8) ] = acc_frag_0_1.x; - // smem_d[smem_d_off + 1 + ( 1*8) ] = acc_frag_0_1.y; - // smem_d[smem_d_off + 0 + ( 1*8) + (8*N_PAD)] = acc_frag_0_1.z; - // smem_d[smem_d_off + 1 + ( 1*8) + (8*N_PAD)] = acc_frag_0_1.w; - // smem_d[smem_d_off + 0 + ( 4*8) ] = acc_frag_0_2.x; - // smem_d[smem_d_off + 1 + ( 4*8) ] = acc_frag_0_2.y; - // smem_d[smem_d_off + 0 + ( 4*8) + (8*N_PAD)] = acc_frag_0_2.z; - // smem_d[smem_d_off + 1 + ( 4*8) + (8*N_PAD)] = acc_frag_0_2.w; - // smem_d[smem_d_off + 0 + ( 5*8) ] = acc_frag_0_3.x; - // smem_d[smem_d_off + 1 + ( 5*8) ] = acc_frag_0_3.y; - // smem_d[smem_d_off + 0 + ( 5*8) + (8*N_PAD)] = acc_frag_0_3.z; - // smem_d[smem_d_off + 1 + ( 5*8) + (8*N_PAD)] = acc_frag_0_3.w; - // smem_d[smem_d_off + 0 + ( 8*8) ] = acc_frag_0_4.x; - // smem_d[smem_d_off + 1 + ( 8*8) ] = acc_frag_0_4.y; - // smem_d[smem_d_off + 0 + ( 8*8) + (8*N_PAD)] = acc_frag_0_4.z; - // smem_d[smem_d_off + 1 + ( 8*8) + (8*N_PAD)] = acc_frag_0_4.w; - // smem_d[smem_d_off + 0 + ( 9*8) ] = acc_frag_0_5.x; - // smem_d[smem_d_off + 1 + ( 9*8) ] = acc_frag_0_5.y; - // smem_d[smem_d_off + 0 + ( 9*8) + (8*N_PAD)] = acc_frag_0_5.z; - // smem_d[smem_d_off + 1 + ( 9*8) + (8*N_PAD)] = acc_frag_0_5.w; - // smem_d[smem_d_off + 0 + (12*8) ] = acc_frag_0_6.x; - // smem_d[smem_d_off + 1 + (12*8) ] = acc_frag_0_6.y; - // smem_d[smem_d_off + 0 + (12*8) + (8*N_PAD)] = acc_frag_0_6.z; - // smem_d[smem_d_off + 1 + (12*8) + (8*N_PAD)] = acc_frag_0_6.w; - // smem_d[smem_d_off + 0 + (13*8) ] = acc_frag_0_7.x; - // smem_d[smem_d_off + 1 + (13*8) ] = acc_frag_0_7.y; - // smem_d[smem_d_off + 0 + (13*8) + (8*N_PAD)] = acc_frag_0_7.z; - // smem_d[smem_d_off + 1 + (13*8) + (8*N_PAD)] = acc_frag_0_7.w; - - // __syncthreads(); - // size_t load_smem_d_off = ((threads % 32) * 4) + ((threads / 32) * N_PAD); - // float4 d_0_0 = *((float4 *)(smem_d + load_smem_d_off + ( 0 * N_PAD))); - // float4 d_0_1 = *((float4 *)(smem_d + load_smem_d_off + ( 4 * N_PAD))); - // float4 d_0_2 = *((float4 *)(smem_d + load_smem_d_off + ( 8 * N_PAD))); - // float4 d_0_3 = *((float4 *)(smem_d + load_smem_d_off + (12 * N_PAD))); - // float4 d_0_4 = *((float4 *)(smem_d + load_smem_d_off + (16 * N_PAD))); - // float4 d_0_5 = *((float4 *)(smem_d + load_smem_d_off + (20 * N_PAD))); - // float4 d_0_6 = *((float4 *)(smem_d + load_smem_d_off + (24 * N_PAD))); - // float4 d_0_7 = *((float4 *)(smem_d + load_smem_d_off + (28 * N_PAD))); - - // __syncthreads(); - // smem_d[smem_d_off + 0 + ( 0*8) ] = acc_frag_1_0.x; - // smem_d[smem_d_off + 1 + ( 0*8) ] = acc_frag_1_0.y; - // smem_d[smem_d_off + 0 + ( 0*8) + (8*N_PAD)] = acc_frag_1_0.z; - // smem_d[smem_d_off + 1 + ( 0*8) + (8*N_PAD)] = acc_frag_1_0.w; - // smem_d[smem_d_off + 0 + ( 1*8) ] = acc_frag_1_1.x; - // smem_d[smem_d_off + 1 + ( 1*8) ] = acc_frag_1_1.y; - // smem_d[smem_d_off + 0 + ( 1*8) + (8*N_PAD)] = acc_frag_1_1.z; - // smem_d[smem_d_off + 1 + ( 1*8) + (8*N_PAD)] = acc_frag_1_1.w; - // smem_d[smem_d_off + 0 + ( 4*8) ] = acc_frag_1_2.x; - // smem_d[smem_d_off + 1 + ( 4*8) ] = acc_frag_1_2.y; - // smem_d[smem_d_off + 0 + ( 4*8) + (8*N_PAD)] = acc_frag_1_2.z; - // smem_d[smem_d_off + 1 + ( 4*8) + (8*N_PAD)] = acc_frag_1_2.w; - // smem_d[smem_d_off + 0 + ( 5*8) ] = acc_frag_1_3.x; - // smem_d[smem_d_off + 1 + ( 5*8) ] = acc_frag_1_3.y; - // smem_d[smem_d_off + 0 + ( 5*8) + (8*N_PAD)] = acc_frag_1_3.z; - // smem_d[smem_d_off + 1 + ( 5*8) + (8*N_PAD)] = acc_frag_1_3.w; - // smem_d[smem_d_off + 0 + ( 8*8) ] = acc_frag_1_4.x; - // smem_d[smem_d_off + 1 + ( 8*8) ] = acc_frag_1_4.y; - // smem_d[smem_d_off + 0 + ( 8*8) + (8*N_PAD)] = acc_frag_1_4.z; - // smem_d[smem_d_off + 1 + ( 8*8) + (8*N_PAD)] = acc_frag_1_4.w; - // smem_d[smem_d_off + 0 + ( 9*8) ] = acc_frag_1_5.x; - // smem_d[smem_d_off + 1 + ( 9*8) ] = acc_frag_1_5.y; - // smem_d[smem_d_off + 0 + ( 9*8) + (8*N_PAD)] = acc_frag_1_5.z; - // smem_d[smem_d_off + 1 + ( 9*8) + (8*N_PAD)] = acc_frag_1_5.w; - // smem_d[smem_d_off + 0 + (12*8) ] = acc_frag_1_6.x; - // smem_d[smem_d_off + 1 + (12*8) ] = acc_frag_1_6.y; - // smem_d[smem_d_off + 0 + (12*8) + (8*N_PAD)] = acc_frag_1_6.z; - // smem_d[smem_d_off + 1 + (12*8) + (8*N_PAD)] = acc_frag_1_6.w; - // smem_d[smem_d_off + 0 + (13*8) ] = acc_frag_1_7.x; - // smem_d[smem_d_off + 1 + (13*8) ] = acc_frag_1_7.y; - // smem_d[smem_d_off + 0 + (13*8) + (8*N_PAD)] = acc_frag_1_7.z; - // smem_d[smem_d_off + 1 + (13*8) + (8*N_PAD)] = acc_frag_1_7.w; - - // __syncthreads(); - // float4 d_1_0 = *((float4 *)(smem_d + load_smem_d_off + ( 0 * N_PAD))); - // float4 d_1_1 = *((float4 *)(smem_d + load_smem_d_off + ( 4 * N_PAD))); - // float4 d_1_2 = *((float4 *)(smem_d + load_smem_d_off + ( 8 * N_PAD))); - // float4 d_1_3 = *((float4 *)(smem_d + load_smem_d_off + (12 * N_PAD))); - // float4 d_1_4 = *((float4 *)(smem_d + load_smem_d_off + (16 * N_PAD))); - // float4 d_1_5 = *((float4 *)(smem_d + load_smem_d_off + (20 * N_PAD))); - // float4 d_1_6 = *((float4 *)(smem_d + load_smem_d_off + (24 * N_PAD))); - // float4 d_1_7 = *((float4 *)(smem_d + load_smem_d_off + (28 * N_PAD))); - - // __syncthreads(); - // float *global_d = &data0[((grid_m * 64) * N) + (grid_n * 128) + ((threads % 32) * 4) + ((threads / 32) * N)]; - // *((float4 *)(global_d + 0*N)) = d_0_0; - // *((float4 *)(global_d + 4*N)) = d_0_1; - // *((float4 *)(global_d + 8*N)) = d_0_2; - // *((float4 *)(global_d + 12*N)) = d_0_3; - // *((float4 *)(global_d + 16*N)) = d_0_4; - // *((float4 *)(global_d + 20*N)) = d_0_5; - // *((float4 *)(global_d + 24*N)) = d_0_6; - // *((float4 *)(global_d + 28*N)) = d_0_7; - // *((float4 *)(global_d + 32*N)) = d_1_0; - // *((float4 *)(global_d + 36*N)) = d_1_1; - // *((float4 *)(global_d + 40*N)) = d_1_2; - // *((float4 *)(global_d + 44*N)) = d_1_3; - // *((float4 *)(global_d + 48*N)) = d_1_4; - // *((float4 *)(global_d + 52*N)) = d_1_5; - // *((float4 *)(global_d + 56*N)) = d_1_6; - // *((float4 *)(global_d + 60*N)) = d_1_7; - - // slower way: write floats one by one to data0 - size_t wg_c_off = ((grid_m * 64) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - wg_c_off += 32*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage.cu deleted file mode 100644 index 206fd9e3..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage.cu +++ /dev/null @@ -1,465 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ half4 __WMMA_8_16_16_half_half(half8 a, half4 b, half4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b), *c_pk = (int *) (&c); - asm( "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 { %0, %1 }, { %2, %3, %4, %5 }, { %6, %7 }, { %0, %1 };" - : "+r"(c_pk[0]), "+r"(c_pk[1]): "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(256) wmma_example(half* data0, const half* data1, const half* data2, int N, int K) { - extern __shared__ char smem[]; - half *smem_a_0 = (half *)(smem); - half *smem_a_1 = (half *)(smem + 16384); - half *smem_a_2 = (half *)(smem + 32768); - half *smem_b_0 = (half *)(smem + 49152); - half *smem_b_1 = (half *)(smem + 57344); - half *smem_b_2 = (half *)(smem + 65536); - - int grid_m = blockIdx.x; /* M//256 */ - int grid_n = blockIdx.y; /* N//128 */ - int wg_threads = threadIdx.x; // 32 - int wg_m = threadIdx.y; // 4 - int wg_n = threadIdx.z; // 2 - int threads = threadIdx.x + (threadIdx.y * 32) + (threadIdx.z * 128); /* 256 */ - int num_k_blocks = K / 32; - - // load indexes - size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + ((threads / 4) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // unswizzed smem store - size_t store_smem_a_off = ((threads % 4) * 8) + ((threads / 4) * 32); // 64 rows / 32 cols per copy - size_t store_smem_b_off = ((threads % 16) * 8) + ((threads / 16) * 128); // 16 rows / 128 cols per copy - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // unswizzed ldmatrix - size_t load_smem_a_0_k_0 = (wg_m * 16 * 32) + ((wg_threads % 16) * 32) + ((wg_threads / 16) * 8); - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + ( 64 * 32); - size_t load_smem_a_2_k_0 = load_smem_a_0_k_0 + (128 * 32); - size_t load_smem_a_3_k_0 = load_smem_a_0_k_0 + (192 * 32); - - size_t load_smem_a_0_k_1 = load_smem_a_0_k_0 + 16; - size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + ( 64 * 32); - size_t load_smem_a_2_k_1 = load_smem_a_0_k_1 + (128 * 32); - size_t load_smem_a_3_k_1 = load_smem_a_0_k_1 + (192 * 32); - - size_t load_smem_b_0_k_0 = (wg_n * 16) + ((wg_threads % 16) * 128) + ((wg_threads / 16) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_0_k_0 + 32; - size_t load_smem_b_2_k_0 = load_smem_b_0_k_0 + 64; - size_t load_smem_b_3_k_0 = load_smem_b_0_k_0 + 96; - - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_0_k_1 + 32; - size_t load_smem_b_2_k_1 = load_smem_b_0_k_1 + 64; - size_t load_smem_b_3_k_1 = load_smem_b_0_k_1 + 96; - - // create accs (M=4, N=8) - half4 acc_frag_0_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements - half8 a_frag_0_k_0; - half8 a_frag_1_k_0; - half8 a_frag_2_k_0; - half8 a_frag_3_k_0; - half8 a_frag_0_k_1; - half8 a_frag_1_k_1; - half8 a_frag_2_k_1; - half8 a_frag_3_k_1; - - // create register for block B elements - half4 b_frag_0_k_0; - half4 b_frag_1_k_0; - half4 b_frag_2_k_0; - half4 b_frag_3_k_0; - half4 b_frag_4_k_0; - half4 b_frag_5_k_0; - half4 b_frag_6_k_0; - half4 b_frag_7_k_0; - half4 b_frag_0_k_1; - half4 b_frag_1_k_1; - half4 b_frag_2_k_1; - half4 b_frag_3_k_1; - half4 b_frag_4_k_1; - half4 b_frag_5_k_1; - half4 b_frag_6_k_1; - half4 b_frag_7_k_1; - - __syncthreads(); - - // load first tile - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - - global_a_off += 32; - global_b_off += 32 * N; - - // load second tile - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - - global_a_off += 32; - global_b_off += 32 * N; - - // wait on first pre-fetch load - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 for the first tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_0[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_0[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_0[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_0[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_0[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_0[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_0[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_0[load_smem_b_3_k_0]); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - int phase_k = block_k % 3; - half *smem_a_curr = (phase_k == 0) ? smem_a_0 : ((phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_curr = (phase_k == 0) ? smem_b_0 : ((phase_k == 1) ? smem_b_1 : smem_b_2); - - int next_phase_k = (block_k+1) % 3; - half *smem_a_next = (next_phase_k == 0) ? smem_a_0 : ((next_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_next = (next_phase_k == 0) ? smem_b_0 : ((next_phase_k == 1) ? smem_b_1 : smem_b_2); - - int store_phase_k = (block_k+2) % 3; - half *smem_a_store = (store_phase_k == 0) ? smem_a_0 : ((store_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_store = (store_phase_k == 0) ? smem_b_0 : ((store_phase_k == 1) ? smem_b_1 : smem_b_2); - - // load K=1 elements for the current tile - __ldmatrix_a_elems(&a_frag_0_k_1, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1_k_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_a_elems(&a_frag_2_k_1, &smem_a_curr[load_smem_a_2_k_1]); - __ldmatrix_a_elems(&a_frag_3_k_1, &smem_a_curr[load_smem_a_3_k_1]); - __ldmatrix_b_elems(&b_frag_0_k_1, &b_frag_1_k_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2_k_1, &b_frag_3_k_1, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4_k_1, &b_frag_5_k_1, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6_k_1, &b_frag_7_k_1, &smem_b_curr[load_smem_b_3_k_1]); - - // MMA K=0, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_0_k_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_1_k_0, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_2_k_0, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_3_k_0, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_4_k_0, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_5_k_0, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_6_k_0, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_7_k_0, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_0_k_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_1_k_0, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_2_k_0, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_3_k_0, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_4_k_0, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_5_k_0, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_6_k_0, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_7_k_0, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_0_k_0, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_1_k_0, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_2_k_0, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_3_k_0, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_4_k_0, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_5_k_0, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_6_k_0, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_7_k_0, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_0_k_0, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_1_k_0, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_2_k_0, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_3_k_0, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_4_k_0, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_5_k_0, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_6_k_0, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_7_k_0, acc_frag_3_7); - - // load next tile - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - global_a_off += 32; - global_b_off += 32 * N; - } - __pipeline_commit(); - - // wait next tile - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 for the next tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_next[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_next[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_next[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_next[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_next[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_next[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_next[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_next[load_smem_b_3_k_0]); - - // MMA K=1, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_0_k_1, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_1_k_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_2_k_1, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_3_k_1, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_4_k_1, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_5_k_1, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_6_k_1, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_7_k_1, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_0_k_1, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_1_k_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_2_k_1, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_3_k_1, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_4_k_1, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_5_k_1, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_6_k_1, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_7_k_1, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_0_k_1, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_1_k_1, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_2_k_1, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_3_k_1, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_4_k_1, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_5_k_1, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_6_k_1, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_7_k_1, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_0_k_1, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_1_k_1, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_2_k_1, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_3_k_1, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_4_k_1, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_5_k_1, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_6_k_1, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_7_k_1, acc_frag_3_7); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // slower way: write accs one by one to data0 - - size_t wg_c_off = ((grid_m * 256) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_2_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_2_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_2_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_2_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_2_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_2_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_2_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_2_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_2_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_2_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_2_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_2_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_2_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_2_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_2_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_2_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_2_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_2_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_2_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_2_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_2_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_2_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_2_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_2_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_2_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_2_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_2_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_2_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_2_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_2_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_2_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_2_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_3_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_3_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_3_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_3_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_3_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_3_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_3_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_3_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_3_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_3_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_3_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_3_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_3_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_3_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_3_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_3_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_3_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_3_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_3_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_3_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_3_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_3_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_3_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_3_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_3_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_3_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_3_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_3_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_3_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_3_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_3_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_3_7.w; - -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage_swizzled.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage_swizzled.cu deleted file mode 100644 index 0352666b..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.3_stage_swizzled.cu +++ /dev/null @@ -1,517 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ half4 __WMMA_8_16_16_half_half(half8 a, half4 b, half4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b), *c_pk = (int *) (&c); - asm( "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 { %0, %1 }, { %2, %3, %4, %5 }, { %6, %7 }, { %0, %1 };" - : "+r"(c_pk[0]), "+r"(c_pk[1]): "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(256) wmma_example(half* data0, const half* data1, const half* data2, int N, int K) { - extern __shared__ char smem[]; - half *smem_a_0 = (half *)(smem); - half *smem_a_1 = (half *)(smem + 16384); - half *smem_a_2 = (half *)(smem + 32768); - half *smem_b_0 = (half *)(smem + 49152); - half *smem_b_1 = (half *)(smem + 57344); - half *smem_b_2 = (half *)(smem + 65536); - - int grid_m = blockIdx.x; /* M//256 */ - int grid_n = blockIdx.y; /* N//128 */ - int wg_threads = threadIdx.x; // 32 - int wg_m = threadIdx.y; // 4 - int wg_n = threadIdx.z; // 2 - int threads = threadIdx.x + (threadIdx.y * 32) + (threadIdx.z * 128); /* 256 */ - int num_k_blocks = K / 32; - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // unswizzled A - SMEM_A is 256 rows x 32 cols - // size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + ((threads / 4) * K); - // size_t store_smem_a_off = ((threads % 4) * 8) + ((threads / 4) * 32); // 64 rows / 32 cols per copy - // size_t load_smem_a_0_k_0 = (wg_m * 16 * 32) + ((wg_threads % 16) * 32) + ((wg_threads / 16) * 8); - // size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + ( 64 * 32); - // size_t load_smem_a_2_k_0 = load_smem_a_0_k_0 + (128 * 32); - // size_t load_smem_a_3_k_0 = load_smem_a_0_k_0 + (192 * 32); - // size_t load_smem_a_0_k_1 = load_smem_a_0_k_0 + 16; - // size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + ( 64 * 32); - // size_t load_smem_a_2_k_1 = load_smem_a_0_k_1 + (128 * 32); - // size_t load_smem_a_3_k_1 = load_smem_a_0_k_1 + (192 * 32); - - // unswizzled reshaped A - SMEM_A is 128 rows x 64 cols, [ (M=0, K=0), (M=0, K=1), (M=8, K=0), (M=8, K=1) ], etc. - // size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + (((threads / 4) % 2) * 8 * 16 * K) + ((threads / 8) * K); - // size_t store_smem_a_off = ((threads % 8) * 8) + ((threads / 8) * 64); // 32 rows / 64 cols per copy - // size_t load_smem_a_0_k_0 = (wg_m * 16 * 64) + ((wg_threads % 16) * 64) + ((wg_threads / 16) * 8); - // size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (64 * 64); - // size_t load_smem_a_2_k_0 = load_smem_a_0_k_0 + + 32; - // size_t load_smem_a_3_k_0 = load_smem_a_0_k_0 + (64 * 64) + 32; - // size_t load_smem_a_0_k_1 = load_smem_a_0_k_0 + 16; - // size_t load_smem_a_1_k_1 = load_smem_a_1_k_0 + 16; - // size_t load_smem_a_2_k_1 = load_smem_a_2_k_0 + 16; - // size_t load_smem_a_3_k_1 = load_smem_a_3_k_0 + 16; - - // swizzled A - size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + (((threads / 4) % 2) * 8 * 16 * K) + ((threads / 8) * K); - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // 32 rows / 64 cols per copy - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; - size_t load_smem_a_phase = (threads / 16) % 2; - size_t load_smem_a_0_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_0_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - - // unswizzed B - // size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - // size_t store_smem_b_off = ((threads % 16) * 8) + ((threads / 16) * 128); // 16 rows / 128 cols per copy - // size_t load_smem_b_0_k_0 = (wg_n * 16) + ((wg_threads % 16) * 128) + ((wg_threads / 16) * 8); - // size_t load_smem_b_1_k_0 = load_smem_b_0_k_0 + 32; - // size_t load_smem_b_2_k_0 = load_smem_b_0_k_0 + 64; - // size_t load_smem_b_3_k_0 = load_smem_b_0_k_0 + 96; - // size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - // size_t load_smem_b_1_k_1 = load_smem_b_0_k_1 + 32; - // size_t load_smem_b_2_k_1 = load_smem_b_0_k_1 + 64; - // size_t load_smem_b_3_k_1 = load_smem_b_0_k_1 + 96; - - // swizzled B - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - size_t store_smem_b_off = ((threads / 16) * 128) + ((((threads / 16) % 8) * 8) ^ ((threads % 16) * 8)); // 16 rows / 128 cols per copy - size_t load_smem_b_row = (threads % 16) * 128; - size_t load_smem_b_phase = (wg_n * 2) + (wg_threads / 16); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - // create accs (M=4, N=8) - half4 acc_frag_0_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements - half8 a_frag_0_k_0; - half8 a_frag_1_k_0; - half8 a_frag_2_k_0; - half8 a_frag_3_k_0; - half8 a_frag_0_k_1; - half8 a_frag_1_k_1; - half8 a_frag_2_k_1; - half8 a_frag_3_k_1; - - // create register for block B elements - half4 b_frag_0_k_0; - half4 b_frag_1_k_0; - half4 b_frag_2_k_0; - half4 b_frag_3_k_0; - half4 b_frag_4_k_0; - half4 b_frag_5_k_0; - half4 b_frag_6_k_0; - half4 b_frag_7_k_0; - half4 b_frag_0_k_1; - half4 b_frag_1_k_1; - half4 b_frag_2_k_1; - half4 b_frag_3_k_1; - half4 b_frag_4_k_1; - half4 b_frag_5_k_1; - half4 b_frag_6_k_1; - half4 b_frag_7_k_1; - - __syncthreads(); - - // load first tile - // unswizzled 256 x 32 - // __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - // __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - // __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - // __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - // unswizzled 128 x 64 - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - global_a_off += 32; - global_b_off += 32 * N; - - // load second tile - // unswizzled 256 x 32 - // __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - // __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - // __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - // __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - // unswizzled 128 x 64 - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - - global_a_off += 32; - global_b_off += 32 * N; - - // wait on first pre-fetch load - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 for the first tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_0[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_0[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_0[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_0[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_0[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_0[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_0[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_0[load_smem_b_3_k_0]); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - int phase_k = block_k % 3; - half *smem_a_curr = (phase_k == 0) ? smem_a_0 : ((phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_curr = (phase_k == 0) ? smem_b_0 : ((phase_k == 1) ? smem_b_1 : smem_b_2); - - int next_phase_k = (block_k+1) % 3; - half *smem_a_next = (next_phase_k == 0) ? smem_a_0 : ((next_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_next = (next_phase_k == 0) ? smem_b_0 : ((next_phase_k == 1) ? smem_b_1 : smem_b_2); - - int store_phase_k = (block_k+2) % 3; - half *smem_a_store = (store_phase_k == 0) ? smem_a_0 : ((store_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_store = (store_phase_k == 0) ? smem_b_0 : ((store_phase_k == 1) ? smem_b_1 : smem_b_2); - - // load K=1 elements for the current tile - __ldmatrix_a_elems(&a_frag_0_k_1, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1_k_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_a_elems(&a_frag_2_k_1, &smem_a_curr[load_smem_a_2_k_1]); - __ldmatrix_a_elems(&a_frag_3_k_1, &smem_a_curr[load_smem_a_3_k_1]); - __ldmatrix_b_elems(&b_frag_0_k_1, &b_frag_1_k_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2_k_1, &b_frag_3_k_1, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4_k_1, &b_frag_5_k_1, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6_k_1, &b_frag_7_k_1, &smem_b_curr[load_smem_b_3_k_1]); - - // MMA K=0, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_0_k_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_1_k_0, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_2_k_0, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_3_k_0, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_4_k_0, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_5_k_0, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_6_k_0, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_7_k_0, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_0_k_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_1_k_0, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_2_k_0, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_3_k_0, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_4_k_0, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_5_k_0, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_6_k_0, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_7_k_0, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_0_k_0, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_1_k_0, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_2_k_0, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_3_k_0, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_4_k_0, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_5_k_0, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_6_k_0, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_7_k_0, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_0_k_0, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_1_k_0, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_2_k_0, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_3_k_0, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_4_k_0, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_5_k_0, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_6_k_0, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_7_k_0, acc_frag_3_7); - - // load next tile - if (block_k < (num_k_blocks-2)) { - // unswizzled 256 x 32 - // __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - // __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 64*32)], &data1[global_a_off + ( 64*K)], 16); - // __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + (128*32)], &data1[global_a_off + (128*K)], 16); - // __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + (192*32)], &data1[global_a_off + (192*K)], 16); - // unswizzled 128 x 64 - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - global_a_off += 32; - global_b_off += 32 * N; - } - __pipeline_commit(); - - // wait next tile - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 for the next tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_next[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_next[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_next[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_next[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_next[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_next[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_next[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_next[load_smem_b_3_k_0]); - - // MMA K=1, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_0_k_1, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_1_k_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_2_k_1, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_3_k_1, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_4_k_1, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_5_k_1, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_6_k_1, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_7_k_1, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_0_k_1, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_1_k_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_2_k_1, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_3_k_1, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_4_k_1, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_5_k_1, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_6_k_1, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_7_k_1, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_0_k_1, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_1_k_1, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_2_k_1, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_3_k_1, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_4_k_1, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_5_k_1, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_6_k_1, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_7_k_1, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_0_k_1, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_1_k_1, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_2_k_1, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_3_k_1, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_4_k_1, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_5_k_1, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_6_k_1, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_7_k_1, acc_frag_3_7); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // slower way: write accs one by one to data0 - - size_t wg_c_off = ((grid_m * 256) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_2_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_2_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_2_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_2_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_2_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_2_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_2_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_2_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_2_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_2_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_2_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_2_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_2_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_2_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_2_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_2_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_2_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_2_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_2_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_2_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_2_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_2_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_2_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_2_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_2_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_2_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_2_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_2_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_2_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_2_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_2_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_2_7.w; - - wg_c_off += 64*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_3_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_3_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_3_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_3_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_3_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_3_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_3_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_3_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_3_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_3_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_3_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_3_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_3_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_3_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_3_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_3_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_3_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_3_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_3_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_3_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_3_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_3_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_3_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_3_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_3_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_3_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_3_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_3_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_3_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_3_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_3_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_3_7.w; - -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.max.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.max.cu deleted file mode 100644 index 588f6b3c..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.max.cu +++ /dev/null @@ -1,482 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define SMEM_N_WIDTH 136 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ half4 __WMMA_8_16_16_half_half(half8 a, half4 b, half4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b), *c_pk = (int *) (&c); - asm( "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 { %0, %1 }, { %2, %3, %4, %5 }, { %6, %7 }, { %0, %1 };" - : "+r"(c_pk[0]), "+r"(c_pk[1]): "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(256) wmma_example(half* data0, const half* data1, const half* data2, int N, int K) { - extern __shared__ char smem[]; - half *smem_a_0 = (half *)(smem); - half *smem_a_1 = (half *)(smem + 16384); - half *smem_a_2 = (half *)(smem + 32768); - half *smem_b_0 = (half *)(smem + 49152); - half *smem_b_1 = (half *)(smem + 57344); - half *smem_b_2 = (half *)(smem + 65536); - - int grid_m = blockIdx.x; /* M//256 */ - int grid_n = blockIdx.y; /* N//128 */ - int wg_threads = threadIdx.x; // 32 - int wg_m = threadIdx.y; // 4 - int wg_n = threadIdx.z; // 2 - int threads = threadIdx.x + (threadIdx.y * 32) + (threadIdx.z * 128); /* 256 */ - int num_k_blocks = K / 32; - - // ldmatrix indices - 4x loads of 8x8 matrices by 32 threads - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled A - SMEM_A is 128 rows x 64 cols - size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + (((threads / 4) % 2) * 8 * 16 * K) + ((threads / 8) * K); - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // 32 rows / 64 cols per copy - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; - size_t load_smem_a_phase = (threads / 16) % 2; - size_t load_smem_a_0_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_0_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - - // swizzled B - SMEM_B is 32 rows x 128 cols - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - size_t store_smem_b_off = ((threads / 16) * 128) + ((((threads / 16) % 8) * 8) ^ ((threads % 16) * 8)); // 16 rows / 128 cols per copy - size_t load_smem_b_row = (threads % 16) * 128; - size_t load_smem_b_phase = (wg_n * 2) + (wg_threads / 16); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - // create accs (M=4, N=8) - half4 acc_frag_0_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements - half8 a_frag_0_k_0; - half8 a_frag_1_k_0; - half8 a_frag_2_k_0; - half8 a_frag_3_k_0; - half8 a_frag_0_k_1; - half8 a_frag_1_k_1; - half8 a_frag_2_k_1; - half8 a_frag_3_k_1; - - // create register for block B elements - half4 b_frag_0_k_0; - half4 b_frag_1_k_0; - half4 b_frag_2_k_0; - half4 b_frag_3_k_0; - half4 b_frag_4_k_0; - half4 b_frag_5_k_0; - half4 b_frag_6_k_0; - half4 b_frag_7_k_0; - half4 b_frag_0_k_1; - half4 b_frag_1_k_1; - half4 b_frag_2_k_1; - half4 b_frag_3_k_1; - half4 b_frag_4_k_1; - half4 b_frag_5_k_1; - half4 b_frag_6_k_1; - half4 b_frag_7_k_1; - - __syncthreads(); - - // load first tile - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - global_a_off += 32; - global_b_off += 32 * N; - - // load second tile - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - - global_a_off += 32; - global_b_off += 32 * N; - - // wait on first pre-fetch load - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 elements for the first tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_0[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_0[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_0[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_0[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_0[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_0[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_0[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_0[load_smem_b_3_k_0]); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - int phase_k = block_k % 3; - half *smem_a_curr = (phase_k == 0) ? smem_a_0 : ((phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_curr = (phase_k == 0) ? smem_b_0 : ((phase_k == 1) ? smem_b_1 : smem_b_2); - - int next_phase_k = (block_k+1) % 3; - half *smem_a_next = (next_phase_k == 0) ? smem_a_0 : ((next_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_next = (next_phase_k == 0) ? smem_b_0 : ((next_phase_k == 1) ? smem_b_1 : smem_b_2); - - int store_phase_k = (block_k+2) % 3; - half *smem_a_store = (store_phase_k == 0) ? smem_a_0 : ((store_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_store = (store_phase_k == 0) ? smem_b_0 : ((store_phase_k == 1) ? smem_b_1 : smem_b_2); - - // load K=1 elements for the current tile - __ldmatrix_a_elems(&a_frag_0_k_1, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1_k_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_a_elems(&a_frag_2_k_1, &smem_a_curr[load_smem_a_2_k_1]); - __ldmatrix_a_elems(&a_frag_3_k_1, &smem_a_curr[load_smem_a_3_k_1]); - __ldmatrix_b_elems(&b_frag_0_k_1, &b_frag_1_k_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2_k_1, &b_frag_3_k_1, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4_k_1, &b_frag_5_k_1, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6_k_1, &b_frag_7_k_1, &smem_b_curr[load_smem_b_3_k_1]); - - // MMA K=0, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_0_k_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_1_k_0, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_2_k_0, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_3_k_0, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_4_k_0, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_5_k_0, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_6_k_0, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_7_k_0, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_0_k_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_1_k_0, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_2_k_0, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_3_k_0, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_4_k_0, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_5_k_0, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_6_k_0, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_7_k_0, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_0_k_0, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_1_k_0, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_2_k_0, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_3_k_0, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_4_k_0, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_5_k_0, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_6_k_0, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_7_k_0, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_0_k_0, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_1_k_0, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_2_k_0, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_3_k_0, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_4_k_0, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_5_k_0, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_6_k_0, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_7_k_0, acc_frag_3_7); - - // load next tile if needed - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + (16*128)], &data2[global_b_off + ( 16*N)], 16); - global_a_off += 32; - global_b_off += 32 * N; - } - __pipeline_commit(); - - // wait next tile - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 elements for the next tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_next[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_next[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_next[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_next[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_next[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_next[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_next[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_next[load_smem_b_3_k_0]); - - // MMA K=1, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_0_k_1, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_1_k_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_2_k_1, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_3_k_1, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_4_k_1, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_5_k_1, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_6_k_1, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_7_k_1, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_0_k_1, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_1_k_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_2_k_1, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_3_k_1, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_4_k_1, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_5_k_1, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_6_k_1, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_7_k_1, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_0_k_1, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_1_k_1, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_2_k_1, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_3_k_1, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_4_k_1, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_5_k_1, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_6_k_1, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_7_k_1, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_0_k_1, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_1_k_1, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_2_k_1, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_3_k_1, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_4_k_1, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_5_k_1, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_6_k_1, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_7_k_1, acc_frag_3_7); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // faster epilogue: write each 8x8 TC accs to SMEM first - // - SMEM_N_WIDTH 8 larger than 128 required to deconflict bank access - // - around 14 micros - // - check bank conflict with in sudo with: "PYTHONPATH=. CUDA=1 GEMM_VARIATION="max" DTYPE_IN=half DTYPE_OUT=half DTYPE_ACC=half CNT=8 INPUT=ONES /usr/local/cuda/bin/ncu --section MemoryWorkloadAnalysis --metrics l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_ld.sum,l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_st.sum python3 ./extra/gemm/max_matmul.py" - - // epilogue chunk with 256 threads / WG_M=4 / WG_N=2: split into 8 chunks (hi/lo for each in TC M) - // 1) write 32 rows of 128 cols (rows 0-7, 16-23, 32-39, 48-53 in acc_frag_0.lo, then acc_frag_0.hi, etc.) - // 2) read/write 16 rows of 128 elements in 8 elem (16B) chunks - - half2 *smem32_d = (half2 *)(smem); - half8 *smem128_d = (half8 *)(smem); - half8 *out128_d = (half8 *)(data0); - size_t smem32_d_write_off = (wg_m * 8 * (SMEM_N_WIDTH / 2)) + (wg_n * (16 / 2)); - size_t smem32_d_thread_off = ((wg_threads / 4) * (SMEM_N_WIDTH / 2)) + (wg_threads % 4); - size_t smem128_d_read_off = ((threads / 16) * (SMEM_N_WIDTH / 8)) + (threads % 16); - size_t out128_d_off = ((grid_m * 256) * (N / 8)) + (grid_n * (128 / 8)) + - ((threads / 128) * 16 * (N / 8)) + (((threads / 16) % 8) * (N / 8)) + (threads % 16); - - // write acc_frag_0_* - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_0_0.x, acc_frag_0_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_0_1.x, acc_frag_0_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_0_2.x, acc_frag_0_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_0_3.x, acc_frag_0_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_0_4.x, acc_frag_0_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_0_5.x, acc_frag_0_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_0_6.x, acc_frag_0_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_0_7.x, acc_frag_0_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_0_0.z, acc_frag_0_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_0_1.z, acc_frag_0_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_0_2.z, acc_frag_0_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_0_3.z, acc_frag_0_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_0_4.z, acc_frag_0_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_0_5.z, acc_frag_0_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_0_6.z, acc_frag_0_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_0_7.z, acc_frag_0_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_1_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_1_0.x, acc_frag_1_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_1_1.x, acc_frag_1_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_1_2.x, acc_frag_1_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_1_3.x, acc_frag_1_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_1_4.x, acc_frag_1_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_1_5.x, acc_frag_1_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_1_6.x, acc_frag_1_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_1_7.x, acc_frag_1_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_1_0.z, acc_frag_1_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_1_1.z, acc_frag_1_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_1_2.z, acc_frag_1_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_1_3.z, acc_frag_1_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_1_4.z, acc_frag_1_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_1_5.z, acc_frag_1_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_1_6.z, acc_frag_1_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_1_7.z, acc_frag_1_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_2_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_2_0.x, acc_frag_2_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_2_1.x, acc_frag_2_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_2_2.x, acc_frag_2_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_2_3.x, acc_frag_2_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_2_4.x, acc_frag_2_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_2_5.x, acc_frag_2_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_2_6.x, acc_frag_2_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_2_7.x, acc_frag_2_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_2_0.z, acc_frag_2_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_2_1.z, acc_frag_2_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_2_2.z, acc_frag_2_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_2_3.z, acc_frag_2_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_2_4.z, acc_frag_2_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_2_5.z, acc_frag_2_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_2_6.z, acc_frag_2_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_2_7.z, acc_frag_2_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_3_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_3_0.x, acc_frag_3_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_3_1.x, acc_frag_3_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_3_2.x, acc_frag_3_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_3_3.x, acc_frag_3_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_3_4.x, acc_frag_3_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_3_5.x, acc_frag_3_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_3_6.x, acc_frag_3_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_3_7.x, acc_frag_3_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_3_0.z, acc_frag_3_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_3_1.z, acc_frag_3_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_3_2.z, acc_frag_3_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_3_3.z, acc_frag_3_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_3_4.z, acc_frag_3_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_3_5.z, acc_frag_3_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_3_6.z, acc_frag_3_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_3_7.z, acc_frag_3_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - __syncthreads(); -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.no_xor.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.no_xor.cu deleted file mode 100644 index 962a2194..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp16_fp16.no_xor.cu +++ /dev/null @@ -1,486 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define SMEM_N_WIDTH 136 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ half4 __WMMA_8_16_16_half_half(half8 a, half4 b, half4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b), *c_pk = (int *) (&c); - asm( "mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 { %0, %1 }, { %2, %3, %4, %5 }, { %6, %7 }, { %0, %1 };" - : "+r"(c_pk[0]), "+r"(c_pk[1]): "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(256) wmma_example(half* data0, const half* data1, const half* data2, int N, int K) { - extern __shared__ char smem[]; - half *smem_a_0 = (half *)(smem); - half *smem_a_1 = (half *)(smem + 16384); - half *smem_a_2 = (half *)(smem + 32768); - half *smem_b_0 = (half *)(smem + 49152); - half *smem_b_1 = (half *)(smem + 57344); - half *smem_b_2 = (half *)(smem + 65536); - - int grid_m = blockIdx.x; /* M//256 */ - int grid_n = blockIdx.y; /* N//128 */ - int wg_threads = threadIdx.x; // 32 - int wg_m = threadIdx.y; // 4 - int wg_n = threadIdx.z; // 2 - int threads = threadIdx.x + (threadIdx.y * 32) + (threadIdx.z * 128); /* 256 */ - int num_k_blocks = K / 32; - - // ldmatrix indices - 4x loads of 8x8 matrices by 32 threads - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled A - SMEM_A is 128 rows x 64 cols - size_t global_a_off = ((grid_m * 256) * K) + ((threads % 4) * 8) + (((threads / 4) % 2) * 8 * 16 * K) + ((threads / 8) * K); - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // 32 rows / 64 cols per copy - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; - size_t load_smem_a_phase = (threads / 16) % 2; - size_t load_smem_a_0_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_0 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_0 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_a_0_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_1_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); - size_t load_smem_a_2_k_1 = load_smem_a_row + ( 0 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - size_t load_smem_a_3_k_1 = load_smem_a_row + (64 * 64) + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); - - // swizzled B - SMEM_B is 64 rows x 64 cols - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - size_t store_smem_b_off = // 32 rows of 64 cols per copy - ((threads / 128) * (64)) + // [A,C] vs [B,D] in ldmatrix - ((threads % 2) * (2 * 64)) + // [A vs C] or [B vs. D] - (((threads / 2) % 2) * (4 * 64)) + // WG_N in [0, 1] - (((threads / 4) % 4) * (8 * 64)) + // B in [0, 1, 2, 3] - (((threads / 16) % 8) * (8)); // cols in SMEM_B i.e. rows of 8x8 - - size_t load_smem_b_0_k_0 = (wg_n * 4 * 64) + ((wg_threads / 8) * 64) + ((wg_threads % 8) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_0_k_0 + ( 8 * 64); - size_t load_smem_b_2_k_0 = load_smem_b_0_k_0 + (16 * 64); - size_t load_smem_b_3_k_0 = load_smem_b_0_k_0 + (24 * 64); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (32 * 64); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (32 * 64); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (32 * 64); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (32 * 64); - - // create accs (M=4, N=8) - half4 acc_frag_0_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_0_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_1_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_2_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_0 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_1 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_2 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_3 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_4 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_5 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_6 = make_half4(0.0f,0.0f,0.0f,0.0f); - half4 acc_frag_3_7 = make_half4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements - half8 a_frag_0_k_0; - half8 a_frag_1_k_0; - half8 a_frag_2_k_0; - half8 a_frag_3_k_0; - half8 a_frag_0_k_1; - half8 a_frag_1_k_1; - half8 a_frag_2_k_1; - half8 a_frag_3_k_1; - - // create register for block B elements - half4 b_frag_0_k_0; - half4 b_frag_1_k_0; - half4 b_frag_2_k_0; - half4 b_frag_3_k_0; - half4 b_frag_4_k_0; - half4 b_frag_5_k_0; - half4 b_frag_6_k_0; - half4 b_frag_7_k_0; - half4 b_frag_0_k_1; - half4 b_frag_1_k_1; - half4 b_frag_2_k_1; - half4 b_frag_3_k_1; - half4 b_frag_4_k_1; - half4 b_frag_5_k_1; - half4 b_frag_6_k_1; - half4 b_frag_7_k_1; - - __syncthreads(); - - // load first tile - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_0[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_0[store_smem_b_off + ( 32*64)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - global_a_off += 32; - global_b_off += 32 * N; - - // load second tile - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_1[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_1[store_smem_b_off + ( 32*64)], &data2[global_b_off + ( 16*N)], 16); - __pipeline_commit(); - - global_a_off += 32; - global_b_off += 32 * N; - - // wait on first pre-fetch load - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 elements for the first tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_0[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_0[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_0[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_0[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_0[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_0[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_0[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_0[load_smem_b_3_k_0]); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - int phase_k = block_k % 3; - half *smem_a_curr = (phase_k == 0) ? smem_a_0 : ((phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_curr = (phase_k == 0) ? smem_b_0 : ((phase_k == 1) ? smem_b_1 : smem_b_2); - - int next_phase_k = (block_k+1) % 3; - half *smem_a_next = (next_phase_k == 0) ? smem_a_0 : ((next_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_next = (next_phase_k == 0) ? smem_b_0 : ((next_phase_k == 1) ? smem_b_1 : smem_b_2); - - int store_phase_k = (block_k+2) % 3; - half *smem_a_store = (store_phase_k == 0) ? smem_a_0 : ((store_phase_k == 1) ? smem_a_1 : smem_a_2); - half *smem_b_store = (store_phase_k == 0) ? smem_b_0 : ((store_phase_k == 1) ? smem_b_1 : smem_b_2); - - // load K=1 elements for the current tile - __ldmatrix_a_elems(&a_frag_0_k_1, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1_k_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_a_elems(&a_frag_2_k_1, &smem_a_curr[load_smem_a_2_k_1]); - __ldmatrix_a_elems(&a_frag_3_k_1, &smem_a_curr[load_smem_a_3_k_1]); - __ldmatrix_b_elems(&b_frag_0_k_1, &b_frag_1_k_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2_k_1, &b_frag_3_k_1, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4_k_1, &b_frag_5_k_1, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6_k_1, &b_frag_7_k_1, &smem_b_curr[load_smem_b_3_k_1]); - - // MMA K=0, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_0_k_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_1_k_0, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_2_k_0, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_3_k_0, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_4_k_0, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_5_k_0, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_6_k_0, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_0, b_frag_7_k_0, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_0_k_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_1_k_0, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_2_k_0, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_3_k_0, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_4_k_0, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_5_k_0, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_6_k_0, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_0, b_frag_7_k_0, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_0_k_0, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_1_k_0, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_2_k_0, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_3_k_0, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_4_k_0, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_5_k_0, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_6_k_0, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_0, b_frag_7_k_0, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_0_k_0, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_1_k_0, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_2_k_0, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_3_k_0, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_4_k_0, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_5_k_0, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_6_k_0, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_0, b_frag_7_k_0, acc_frag_3_7); - - // load next tile if needed - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 32*64)], &data1[global_a_off + ( 32*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 64*64)], &data1[global_a_off + ( 64*K)], 16); - __pipeline_memcpy_async(&smem_a_store[store_smem_a_off + ( 96*64)], &data1[global_a_off + ( 96*K)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_store[store_smem_b_off + ( 32*64)], &data2[global_b_off + ( 16*N)], 16); - global_a_off += 32; - global_b_off += 32 * N; - } - __pipeline_commit(); - - // wait next tile - __pipeline_wait_prior(1); - __syncthreads(); - - // load K=0 elements for the next tile - __ldmatrix_a_elems(&a_frag_0_k_0, &smem_a_next[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1_k_0, &smem_a_next[load_smem_a_1_k_0]); - __ldmatrix_a_elems(&a_frag_2_k_0, &smem_a_next[load_smem_a_2_k_0]); - __ldmatrix_a_elems(&a_frag_3_k_0, &smem_a_next[load_smem_a_3_k_0]); - __ldmatrix_b_elems(&b_frag_0_k_0, &b_frag_1_k_0, &smem_b_next[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2_k_0, &b_frag_3_k_0, &smem_b_next[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4_k_0, &b_frag_5_k_0, &smem_b_next[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6_k_0, &b_frag_7_k_0, &smem_b_next[load_smem_b_3_k_0]); - - // MMA K=1, (M=4 x N=8) - acc_frag_0_0 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_0_k_1, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_1_k_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_2_k_1, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_3_k_1, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_4_k_1, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_5_k_1, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_6_k_1, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_half(a_frag_0_k_1, b_frag_7_k_1, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_0_k_1, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_1_k_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_2_k_1, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_3_k_1, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_4_k_1, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_5_k_1, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_6_k_1, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_half(a_frag_1_k_1, b_frag_7_k_1, acc_frag_1_7); - acc_frag_2_0 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_0_k_1, acc_frag_2_0); - acc_frag_2_1 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_1_k_1, acc_frag_2_1); - acc_frag_2_2 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_2_k_1, acc_frag_2_2); - acc_frag_2_3 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_3_k_1, acc_frag_2_3); - acc_frag_2_4 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_4_k_1, acc_frag_2_4); - acc_frag_2_5 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_5_k_1, acc_frag_2_5); - acc_frag_2_6 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_6_k_1, acc_frag_2_6); - acc_frag_2_7 = __WMMA_8_16_16_half_half(a_frag_2_k_1, b_frag_7_k_1, acc_frag_2_7); - acc_frag_3_0 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_0_k_1, acc_frag_3_0); - acc_frag_3_1 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_1_k_1, acc_frag_3_1); - acc_frag_3_2 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_2_k_1, acc_frag_3_2); - acc_frag_3_3 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_3_k_1, acc_frag_3_3); - acc_frag_3_4 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_4_k_1, acc_frag_3_4); - acc_frag_3_5 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_5_k_1, acc_frag_3_5); - acc_frag_3_6 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_6_k_1, acc_frag_3_6); - acc_frag_3_7 = __WMMA_8_16_16_half_half(a_frag_3_k_1, b_frag_7_k_1, acc_frag_3_7); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // faster epilogue: write each 8x8 TC accs to SMEM first - // - SMEM_N_WIDTH 8 larger than 128 required to deconflict bank access - // - around 14 micros - // - check bank conflict with in sudo with: "PYTHONPATH=. CUDA=1 GEMM_VARIATION="max" DTYPE_IN=half DTYPE_OUT=half DTYPE_ACC=half CNT=8 INPUT=ONES /usr/local/cuda/bin/ncu --section MemoryWorkloadAnalysis --metrics l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_ld.sum,l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_st.sum python3 ./extra/gemm/max_matmul.py" - - // epilogue chunk with 256 threads / WG_M=4 / WG_N=2: split into 8 chunks (hi/lo for each in TC M) - // 1) write 32 rows of 128 cols (rows 0-7, 16-23, 32-39, 48-53 in acc_frag_0.lo, then acc_frag_0.hi, etc.) - // 2) read/write 16 rows of 128 elements in 8 elem (16B) chunks - - half2 *smem32_d = (half2 *)(smem); - half8 *smem128_d = (half8 *)(smem); - half8 *out128_d = (half8 *)(data0); - size_t smem32_d_write_off = (wg_m * 8 * (SMEM_N_WIDTH / 2)) + (wg_n * (16 / 2)); - size_t smem32_d_thread_off = ((wg_threads / 4) * (SMEM_N_WIDTH / 2)) + (wg_threads % 4); - size_t smem128_d_read_off = ((threads / 16) * (SMEM_N_WIDTH / 8)) + (threads % 16); - size_t out128_d_off = ((grid_m * 256) * (N / 8)) + (grid_n * (128 / 8)) + - ((threads / 128) * 16 * (N / 8)) + (((threads / 16) % 8) * (N / 8)) + (threads % 16); - - // write acc_frag_0_* - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_0_0.x, acc_frag_0_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_0_1.x, acc_frag_0_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_0_2.x, acc_frag_0_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_0_3.x, acc_frag_0_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_0_4.x, acc_frag_0_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_0_5.x, acc_frag_0_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_0_6.x, acc_frag_0_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_0_7.x, acc_frag_0_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_0_0.z, acc_frag_0_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_0_1.z, acc_frag_0_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_0_2.z, acc_frag_0_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_0_3.z, acc_frag_0_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_0_4.z, acc_frag_0_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_0_5.z, acc_frag_0_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_0_6.z, acc_frag_0_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_0_7.z, acc_frag_0_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_1_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_1_0.x, acc_frag_1_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_1_1.x, acc_frag_1_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_1_2.x, acc_frag_1_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_1_3.x, acc_frag_1_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_1_4.x, acc_frag_1_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_1_5.x, acc_frag_1_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_1_6.x, acc_frag_1_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_1_7.x, acc_frag_1_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_1_0.z, acc_frag_1_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_1_1.z, acc_frag_1_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_1_2.z, acc_frag_1_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_1_3.z, acc_frag_1_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_1_4.z, acc_frag_1_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_1_5.z, acc_frag_1_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_1_6.z, acc_frag_1_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_1_7.z, acc_frag_1_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_2_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_2_0.x, acc_frag_2_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_2_1.x, acc_frag_2_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_2_2.x, acc_frag_2_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_2_3.x, acc_frag_2_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_2_4.x, acc_frag_2_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_2_5.x, acc_frag_2_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_2_6.x, acc_frag_2_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_2_7.x, acc_frag_2_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_2_0.z, acc_frag_2_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_2_1.z, acc_frag_2_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_2_2.z, acc_frag_2_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_2_3.z, acc_frag_2_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_2_4.z, acc_frag_2_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_2_5.z, acc_frag_2_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_2_6.z, acc_frag_2_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_2_7.z, acc_frag_2_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write acc_frag_3_* - out128_d_off += (64 * (N / 8)); - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_3_0.x, acc_frag_3_0.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_3_1.x, acc_frag_3_1.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_3_2.x, acc_frag_3_2.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_3_3.x, acc_frag_3_3.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_3_4.x, acc_frag_3_4.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_3_5.x, acc_frag_3_5.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_3_6.x, acc_frag_3_6.y); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_3_7.x, acc_frag_3_7.y); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 0 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (32 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - // write 32 rows of 128 N elements to SMEM - __syncthreads(); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 0*4)] = half2(acc_frag_3_0.z, acc_frag_3_0.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 1*4)] = half2(acc_frag_3_1.z, acc_frag_3_1.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 4*4)] = half2(acc_frag_3_2.z, acc_frag_3_2.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 5*4)] = half2(acc_frag_3_3.z, acc_frag_3_3.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 8*4)] = half2(acc_frag_3_4.z, acc_frag_3_4.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + ( 9*4)] = half2(acc_frag_3_5.z, acc_frag_3_5.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (12*4)] = half2(acc_frag_3_6.z, acc_frag_3_6.w); - smem32_d[smem32_d_write_off + smem32_d_thread_off + (13*4)] = half2(acc_frag_3_7.z, acc_frag_3_7.w); - - // each thread reads and writes two 8 element chunks - __syncthreads(); - out128_d[out128_d_off + ( 8 * (N / 8))] = smem128_d[smem128_d_read_off]; - out128_d[out128_d_off + (40 * (N / 8))] = smem128_d[smem128_d_read_off + (16 * (SMEM_N_WIDTH / 8))]; - - __syncthreads(); -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp16.hcopt.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp16.hcopt.cu deleted file mode 100644 index f17f8693..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp16.hcopt.cu +++ /dev/null @@ -1,157 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -struct __align__(8) half4 { half x, y, z, w; }; __device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; __device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } -__device__ float4 __WMMA_8_16_16_half_float(half8 a, half4 b, float4 c) { int *a_pk = (int *) (&a), *b_pk = (int *) (&b); -asm( "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 { %0, %1, %2, %3 }, { %4, %5, %6, %7 }, { %8, %9 }, { %0, %1, %2, %3 };" - : "+f"(c.x), "+f"(c.y), "+f"(c.z), "+f"(c.w) : "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); -return c;} -extern "C" __global__ void __launch_bounds__(128) wmma_example(half* data0, const half* data1, const half* data2) { - int gidx0 = blockIdx.x; /* 32 */ - int gidx1 = blockIdx.y; /* 64 */ - int lidx0 = threadIdx.x; /* 16 */ - int lidx1 = threadIdx.y; /* 2 */ - int lidx2 = threadIdx.z; /* 4 */ - float4 cast0 = make_float4(0.0f,0.0f,0.0f,0.0f); - int alu0 = (gidx0*128); - int alu1 = (gidx1*262144); - int alu2 = (lidx1*32768); - int alu3 = (lidx2*32); - int alu4 = (lidx0/8); - int alu5 = (alu4*16384); - int alu6 = (lidx0%2); - int alu7 = (alu6*2); - int alu8 = ((lidx0/2)%2); - int alu9 = (alu8*4); - int alu10 = ((lidx0/4)%2); - int alu11 = (alu10*8192); - int alu12 = (alu1+alu0+alu7+alu9+alu11+alu5+alu2+alu3); - int alu13 = (alu1+alu7+alu9+alu11+alu5+alu2); - float4 acc0 = cast0; - float4 acc1 = cast0; - float4 acc2 = cast0; - float4 acc3 = cast0; - float4 acc4 = cast0; - float4 acc5 = cast0; - float4 acc6 = cast0; - float4 acc7 = cast0; - float4 acc8 = cast0; - float4 acc9 = cast0; - float4 acc10 = cast0; - float4 acc11 = cast0; - float4 acc12 = cast0; - float4 acc13 = cast0; - float4 acc14 = cast0; - float4 acc15 = cast0; - for (int ridx0 = 0; ridx0 < 256; ridx0++) { - int alu14 = (ridx0*16); - int alu15 = (alu13+alu14); - int alu16 = (alu14+alu13); - int alu17 = (alu0+(alu6*8192)+(alu8*16384)+alu10+(alu4*2)+(lidx1*4)+alu3+(ridx0*65536)); - half val0 = data2[alu17+8]; - half val1 = data2[alu17+16]; - half val2 = data2[alu17+24]; - half val3 = data2[alu17+4096]; - half val4 = data2[alu17+4104]; - half val5 = data2[alu17+4112]; - half val6 = data2[alu17+4120]; - half val7 = data2[alu17+32768]; - half val8 = data2[alu17+32776]; - half val9 = data2[alu17+32784]; - half val10 = data2[alu17+32792]; - half val11 = data2[alu17+36864]; - half val12 = data2[alu17+36872]; - half4 cast1 = make_half4(val0,val4,val8,val12); - half val13 = data2[alu17+36880]; - half4 cast2 = make_half4(val1,val5,val9,val13); - half val14 = data2[alu17+36888]; - half4 cast3 = make_half4(val2,val6,val10,val14); - half val15 = data2[alu17]; - half4 cast4 = make_half4(val15,val3,val7,val11); - half2 val16 = *((half2*)(data1+alu15+4096)); - half2 val17 = *((half2*)(data1+alu15+65536)); - half2 val18 = *((half2*)(data1+alu15+69632)); - half2 val19 = *((half2*)(data1+alu15+131072)); - half2 val20 = *((half2*)(data1+alu15+135168)); - half2 val21 = *((half2*)(data1+alu15+196608)); - half2 val22 = *((half2*)(data1+alu15+200704)); - half2 val23 = *((half2*)(data1+alu15)); - half2 val24 = *((half2*)(data1+alu16+8)); - half2 val25 = *((half2*)(data1+alu16+4104)); - half8 cast5 = make_half8(val23.x,val23.y,val16.x,val16.y,val24.x,val24.y,val25.x,val25.y); - float4 wmma0 = __WMMA_8_16_16_half_float(cast5, cast1, acc1); - float4 wmma1 = __WMMA_8_16_16_half_float(cast5, cast2, acc2); - float4 wmma2 = __WMMA_8_16_16_half_float(cast5, cast3, acc3); - float4 wmma3 = __WMMA_8_16_16_half_float(cast5, cast4, acc0); - half2 val26 = *((half2*)(data1+alu16+65544)); - half2 val27 = *((half2*)(data1+alu16+69640)); - half8 cast6 = make_half8(val17.x,val17.y,val18.x,val18.y,val26.x,val26.y,val27.x,val27.y); - float4 wmma4 = __WMMA_8_16_16_half_float(cast6, cast1, acc5); - float4 wmma5 = __WMMA_8_16_16_half_float(cast6, cast2, acc6); - float4 wmma6 = __WMMA_8_16_16_half_float(cast6, cast3, acc7); - float4 wmma7 = __WMMA_8_16_16_half_float(cast6, cast4, acc4); - half2 val28 = *((half2*)(data1+alu16+131080)); - half2 val29 = *((half2*)(data1+alu16+135176)); - half8 cast7 = make_half8(val19.x,val19.y,val20.x,val20.y,val28.x,val28.y,val29.x,val29.y); - float4 wmma8 = __WMMA_8_16_16_half_float(cast7, cast1, acc9); - float4 wmma9 = __WMMA_8_16_16_half_float(cast7, cast2, acc10); - float4 wmma10 = __WMMA_8_16_16_half_float(cast7, cast3, acc11); - float4 wmma11 = __WMMA_8_16_16_half_float(cast7, cast4, acc8); - half2 val30 = *((half2*)(data1+alu16+196616)); - half2 val31 = *((half2*)(data1+alu16+200712)); - half8 cast8 = make_half8(val21.x,val21.y,val22.x,val22.y,val30.x,val30.y,val31.x,val31.y); - float4 wmma12 = __WMMA_8_16_16_half_float(cast8, cast1, acc13); - float4 wmma13 = __WMMA_8_16_16_half_float(cast8, cast2, acc14); - float4 wmma14 = __WMMA_8_16_16_half_float(cast8, cast3, acc15); - float4 wmma15 = __WMMA_8_16_16_half_float(cast8, cast4, acc12); - acc0 = wmma3; - acc1 = wmma0; - acc2 = wmma1; - acc3 = wmma2; - acc4 = wmma7; - acc5 = wmma4; - acc6 = wmma5; - acc7 = wmma6; - acc8 = wmma11; - acc9 = wmma8; - acc10 = wmma9; - acc11 = wmma10; - acc12 = wmma15; - acc13 = wmma12; - acc14 = wmma13; - acc15 = wmma14; - } - *((half2*)(data0+alu12+8)) = make_half2((half)(acc1.x),(half)(acc1.y)); - *((half2*)(data0+alu12+16)) = make_half2((half)(acc2.x),(half)(acc2.y)); - *((half2*)(data0+alu12+24)) = make_half2((half)(acc3.x),(half)(acc3.y)); - *((half2*)(data0+alu12+4096)) = make_half2((half)(acc0.z),(half)(acc0.w)); - *((half2*)(data0+alu12+4104)) = make_half2((half)(acc1.z),(half)(acc1.w)); - *((half2*)(data0+alu12+4112)) = make_half2((half)(acc2.z),(half)(acc2.w)); - *((half2*)(data0+alu12+4120)) = make_half2((half)(acc3.z),(half)(acc3.w)); - *((half2*)(data0+alu12+65536)) = make_half2((half)(acc4.x),(half)(acc4.y)); - *((half2*)(data0+alu12+65544)) = make_half2((half)(acc5.x),(half)(acc5.y)); - *((half2*)(data0+alu12+65552)) = make_half2((half)(acc6.x),(half)(acc6.y)); - *((half2*)(data0+alu12+65560)) = make_half2((half)(acc7.x),(half)(acc7.y)); - *((half2*)(data0+alu12+69632)) = make_half2((half)(acc4.z),(half)(acc4.w)); - *((half2*)(data0+alu12+69640)) = make_half2((half)(acc5.z),(half)(acc5.w)); - *((half2*)(data0+alu12+69648)) = make_half2((half)(acc6.z),(half)(acc6.w)); - *((half2*)(data0+alu12+69656)) = make_half2((half)(acc7.z),(half)(acc7.w)); - *((half2*)(data0+alu12+131072)) = make_half2((half)(acc8.x),(half)(acc8.y)); - *((half2*)(data0+alu12+131080)) = make_half2((half)(acc9.x),(half)(acc9.y)); - *((half2*)(data0+alu12+131088)) = make_half2((half)(acc10.x),(half)(acc10.y)); - *((half2*)(data0+alu12+131096)) = make_half2((half)(acc11.x),(half)(acc11.y)); - *((half2*)(data0+alu12+135168)) = make_half2((half)(acc8.z),(half)(acc8.w)); - *((half2*)(data0+alu12+135176)) = make_half2((half)(acc9.z),(half)(acc9.w)); - *((half2*)(data0+alu12+135184)) = make_half2((half)(acc10.z),(half)(acc10.w)); - *((half2*)(data0+alu12+135192)) = make_half2((half)(acc11.z),(half)(acc11.w)); - *((half2*)(data0+alu12+196608)) = make_half2((half)(acc12.x),(half)(acc12.y)); - *((half2*)(data0+alu12+196616)) = make_half2((half)(acc13.x),(half)(acc13.y)); - *((half2*)(data0+alu12+196624)) = make_half2((half)(acc14.x),(half)(acc14.y)); - *((half2*)(data0+alu12+196632)) = make_half2((half)(acc15.x),(half)(acc15.y)); - *((half2*)(data0+alu12+200704)) = make_half2((half)(acc12.z),(half)(acc12.w)); - *((half2*)(data0+alu12+200712)) = make_half2((half)(acc13.z),(half)(acc13.w)); - *((half2*)(data0+alu12+200720)) = make_half2((half)(acc14.z),(half)(acc14.w)); - *((half2*)(data0+alu12+200728)) = make_half2((half)(acc15.z),(half)(acc15.w)); - *((half2*)(data0+alu12)) = make_half2((half)(acc0.x),(half)(acc0.y)); -} \ No newline at end of file diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.2_stage_swizzled_smem_input.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.2_stage_swizzled_smem_input.cu deleted file mode 100644 index 689da87d..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.2_stage_swizzled_smem_input.cu +++ /dev/null @@ -1,398 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ float4 __WMMA_8_16_16_half_float(half8 a, half4 b, float4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b); - asm( "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 { %0, %1, %2, %3 }, { %4, %5, %6, %7 }, { %8, %9 }, { %0, %1, %2, %3 };" - : "+f"(c.x), "+f"(c.y), "+f"(c.z), "+f"(c.w) : "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(128) wmma_example(float* data0, const half* data1, const half* data2, int N, int K) { - int grid_m = blockIdx.x; /* M//64 */ - int grid_n = blockIdx.y; /* N//128 */ - int threads = threadIdx.x; /* 128 */ - int wg_m = (threads/64); // 0 or 1 for 1st and 3rd blocks of b_m=16xb_k=16 vs 2nd and 4th blocks - int wg_n = (threads/32)%2; // 0 or 1 for 1st, 3rd, 5th, 7th blocks of b_n=16xb_k=16 vs 2nd, 4th, 6th, 8th blocks - differs from triton - int wg_threads = threads%32; - int num_k_blocks = K / 64; - - // load indexes - size_t global_a_off = ((grid_m * 64) * K) + ((threads % 8) * 8) + ((threads / 8) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // swizzled smem store offsets - columns of smem are swizzled - // here's a link to a description of the triton: https://github.com/triton-lang/triton/discussions/2026#discussioncomment-6746579 - // see also the thunderkittens impl: https://github.com/HazyResearch/ThunderKittens/blob/main/include/types/shared/st.cuh - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // r15 - size_t store_smem_b_off = ((threads / 16) * 128) + (((threads / 16) * 8) ^ ((threads % 16) * 8)); // r19 - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled ldmatrix - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; // r293 - size_t load_smem_a_phase = (threads / 16) % 2; // r4 - - size_t load_smem_b_row = (threads % 16) * 128; // r299 - size_t load_smem_b_phase = (wg_n * 2) + (((threads / 16) % 2)); // r297 -- this differs from the generated triton kernel (swapped order) - - size_t load_smem_a_0_k_0 = load_smem_a_row + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); // r38 - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (32 * 64); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - - size_t load_smem_a_0_k_1 = load_smem_a_row + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); // r58 = r293 + r316; - size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + (32 * 64); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - size_t load_smem_a_0_k_2 = load_smem_a_row + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); // r59 = r293 + r319; - size_t load_smem_a_1_k_2 = load_smem_a_0_k_2 + (32 * 64); - size_t load_smem_b_0_k_2 = load_smem_b_0_k_0 + (32 * 128); - size_t load_smem_b_1_k_2 = load_smem_b_1_k_0 + (32 * 128); - size_t load_smem_b_2_k_2 = load_smem_b_2_k_0 + (32 * 128); - size_t load_smem_b_3_k_2 = load_smem_b_3_k_0 + (32 * 128); - - size_t load_smem_a_0_k_3 = load_smem_a_row + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); // r60 = r293 + r322; - size_t load_smem_a_1_k_3 = load_smem_a_0_k_3 + (32 * 64); - size_t load_smem_b_0_k_3 = load_smem_b_0_k_0 + (48 * 128); - size_t load_smem_b_1_k_3 = load_smem_b_1_k_0 + (48 * 128); - size_t load_smem_b_2_k_3 = load_smem_b_2_k_0 + (48 * 128); - size_t load_smem_b_3_k_3 = load_smem_b_3_k_0 + (48 * 128); - - // create shared mem (A_1 8192 bytes, A_2 8192 bytes, B_1 16384 bytes, B2_16384 bytes) - __shared__ alignas(16) char smem[49152]; - - // create accs (16 WMMAs and 4 output elements each) and zero - float4 acc_frag_0_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements (2) - half8 a_frag_0; - half8 a_frag_1; - - // create register for block B elements (8) - half4 b_frag_0; - half4 b_frag_1; - half4 b_frag_2; - half4 b_frag_3; - half4 b_frag_4; - half4 b_frag_5; - half4 b_frag_6; - half4 b_frag_7; - - half *smem_a_even = (half *)(smem); - half *smem_a_odd = (half *)(smem + 8192); - half *smem_b_even = (half *)(smem + 16384); - half *smem_b_odd = (half *)(smem + 32768); - - // https://developer.nvidia.com/blog/controlling-data-movement-to-boost-performance-on-ampere-architecture/ - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#asynchronous-data-copies - - // start first pre-fetch load A - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start first pre-fetch load B - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - __syncthreads(); - - // start second pre-fetch load A - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start second pre-fetch load B - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - - // wait on needed prefetch value - __pipeline_wait_prior(0); // TODO: this enables fast iterations, but incorrect results with 1 (it shouldn't) - __syncthreads(); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - // BLOCK_K==4: unroll 4 iterations of ldmatrix/wmma - half *smem_a_curr = (block_k % 2) ? smem_a_even : smem_a_odd; - half *smem_b_curr = (block_k % 2) ? smem_b_even : smem_b_odd; - - // first load 16 K elements and 16 WMMAs: BLOCK_M==2 * BLOCK_N==8 - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_0]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_0]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_1]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_2]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_2]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_2]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_2]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_2]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_2]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // last 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_3]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_3]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_3]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_3]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_3]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_3]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // prefetch next iteration if needed - __syncthreads(); - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - - global_a_off += 64; - global_b_off += 64 * N; - } - __pipeline_commit(); - - if (block_k < num_k_blocks-1) { - __pipeline_wait_prior(1); - __syncthreads(); - } - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // slower way: write floats one by one to data0 - size_t wg_c_off = ((grid_m * 64) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - wg_c_off += 32*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.flat_smem_input.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.flat_smem_input.cu deleted file mode 100644 index cf9c2ca3..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.flat_smem_input.cu +++ /dev/null @@ -1,363 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ float4 __WMMA_8_16_16_half_float(half8 a, half4 b, float4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b); - asm( "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 { %0, %1, %2, %3 }, { %4, %5, %6, %7 }, { %8, %9 }, { %0, %1, %2, %3 };" - : "+f"(c.x), "+f"(c.y), "+f"(c.z), "+f"(c.w) : "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(128) wmma_example(float* data0, const half* data1, const half* data2, int N, int K) { - int grid_m = blockIdx.x; /* M//64 */ - int grid_n = blockIdx.y; /* N//128 */ - int threads = threadIdx.x; /* 128 */ - int wg_m = (threads/64); // 0 or 1 for 1st and 3rd blocks of b_m=16xb_k=16 vs 2nd and 4th blocks - int wg_n = (threads/32)%2; // 0 or 1 for 1st, 3rd, 5th, 7th blocks of b_n=16xb_k=16 vs 2nd, 4th, 6th, 8th blocks - differs from triton - int wg_threads = threads%32; - int num_k_blocks = K / 64; - - // load indexes - size_t global_a_off = ((grid_m * 64) * K) + ((threads % 8) * 8) + ((threads / 8) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // non-swizzled - should work slowly with bank conflicts - size_t store_smem_a_off = ((threads % 8) * 8) + ((threads / 8) * 64); - size_t store_smem_b_off = ((threads % 16) * 8) + ((threads / 16) * 128); - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // unswizzled ldmatrix - size_t load_smem_a_0_k_0 = (wg_m * 16 * 64) + ((wg_threads % 8) * 64) + (((wg_threads / 8) % 2) * 64 * 8) + ((wg_threads / 16) * 8); - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (32*64); - size_t load_smem_b_0_k_0 = (wg_n * 16) + ((wg_threads % 8) * 128) + (((wg_threads / 8) % 2) * 128 * 8) + ((wg_threads / 16) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_0_k_0 + 32; - size_t load_smem_b_2_k_0 = load_smem_b_0_k_0 + 64; - size_t load_smem_b_3_k_0 = load_smem_b_0_k_0 + 96; - - size_t load_smem_a_0_k_1 = load_smem_a_0_k_0 + 16; - size_t load_smem_a_1_k_1 = load_smem_a_1_k_0 + 16; - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - size_t load_smem_a_0_k_2 = load_smem_a_0_k_0 + 32; - size_t load_smem_a_1_k_2 = load_smem_a_1_k_0 + 32; - size_t load_smem_b_0_k_2 = load_smem_b_0_k_0 + (32 * 128); - size_t load_smem_b_1_k_2 = load_smem_b_1_k_0 + (32 * 128); - size_t load_smem_b_2_k_2 = load_smem_b_2_k_0 + (32 * 128); - size_t load_smem_b_3_k_2 = load_smem_b_3_k_0 + (32 * 128); - - size_t load_smem_a_0_k_3 = load_smem_a_0_k_0 + 48; - size_t load_smem_a_1_k_3 = load_smem_a_1_k_0 + 48; - size_t load_smem_b_0_k_3 = load_smem_b_0_k_0 + (48 * 128); - size_t load_smem_b_1_k_3 = load_smem_b_1_k_0 + (48 * 128); - size_t load_smem_b_2_k_3 = load_smem_b_2_k_0 + (48 * 128); - size_t load_smem_b_3_k_3 = load_smem_b_3_k_0 + (48 * 128); - - // create shared mem (A 8192 bytes, B 16384 bytes) - __shared__ alignas(16) char smem[24576]; - - // create accs (16 WMMAs and 4 output elements each) and zero - float4 acc_frag_0_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements (2) - half8 a_frag_0; - half8 a_frag_1; - - // create register for block B elements (8) - half4 b_frag_0; - half4 b_frag_1; - half4 b_frag_2; - half4 b_frag_3; - half4 b_frag_4; - half4 b_frag_5; - half4 b_frag_6; - half4 b_frag_7; - - half *smem_a = (half *)(smem); - half *smem_b = (half *)(smem + 8192); - - // https://developer.nvidia.com/blog/controlling-data-movement-to-boost-performance-on-ampere-architecture/ - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#asynchronous-data-copies - - // start first pre-fetch load A - __pipeline_memcpy_async(&smem_a[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start first pre-fetch load B - __pipeline_memcpy_async(&smem_b[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - __syncthreads(); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - // wait on needed prefetch value - __pipeline_wait_prior(0); - __syncthreads(); - - // BLOCK_K==4: unroll 4 iterations of ldmatrix/wmma - half *smem_a_curr = smem_a; - half *smem_b_curr = smem_b; - - // first load 16 K elements and 16 WMMAs: BLOCK_M==2 * BLOCK_N==8 - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_0]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_0]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_1]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_2]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_2]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_2]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_2]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_2]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_2]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // last 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_3]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_3]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_3]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_3]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_3]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_3]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // prefetch next iteration if needed - __syncthreads(); - if (block_k < (num_k_blocks-1)) { - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - - global_a_off += 64; - global_b_off += 64 * N; - } - __pipeline_commit(); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // slower way: write floats one by one to data0 - size_t wg_c_off = ((grid_m * 64) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - wg_c_off += 32*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.max.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.max.cu deleted file mode 100644 index b21e8677..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.max.cu +++ /dev/null @@ -1,439 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ float4 __WMMA_8_16_16_half_float(half8 a, half4 b, float4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b); - asm( "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 { %0, %1, %2, %3 }, { %4, %5, %6, %7 }, { %8, %9 }, { %0, %1, %2, %3 };" - : "+f"(c.x), "+f"(c.y), "+f"(c.z), "+f"(c.w) : "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(128) wmma_example(float* data0, const half* data1, const half* data2, int N, int K) { - int grid_m = blockIdx.x; /* M//64 */ - int grid_n = blockIdx.y; /* N//128 */ - int threads = threadIdx.x; /* 128 */ - int wg_m = (threads/64); // 0 or 1 for 1st and 3rd blocks of b_m=16xb_k=16 vs 2nd and 4th blocks - int wg_n = (threads/32)%2; // 0 or 1 for 1st, 3rd, 5th, 7th blocks of b_n=16xb_k=16 vs 2nd, 4th, 6th, 8th blocks - differs from triton - int wg_threads = threads%32; - int num_k_blocks = K / 64; - - // load indexes - size_t global_a_off = ((grid_m * 64) * K) + ((threads % 8) * 8) + ((threads / 8) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // swizzled smem store offsets - columns of smem are swizzled - // here's a link to a description of the triton: https://github.com/triton-lang/triton/discussions/2026#discussioncomment-6746579 - // see also the thunderkittens impl: https://github.com/HazyResearch/ThunderKittens/blob/main/include/types/shared/st.cuh - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // r15 - size_t store_smem_b_off = ((threads / 16) * 128) + (((threads / 16) * 8) ^ ((threads % 16) * 8)); // r19 - - // ldmatrix indices - 4x loads of 8x8 matrices by 32 threads - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled ldmatrix - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; // r293 - size_t load_smem_a_phase = (threads / 16) % 2; // r4 - - size_t load_smem_b_row = (threads % 16) * 128; // r299 - size_t load_smem_b_phase = (wg_n * 2) + (((threads / 16) % 2)); // r297 -- this differs from the generated triton kernel (swapped order) - - size_t load_smem_a_0_k_0 = load_smem_a_row + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); // r38 - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (32 * 64); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - - size_t load_smem_a_0_k_1 = load_smem_a_row + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); // r58 = r293 + r316; - size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + (32 * 64); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - size_t load_smem_a_0_k_2 = load_smem_a_row + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); // r59 = r293 + r319; - size_t load_smem_a_1_k_2 = load_smem_a_0_k_2 + (32 * 64); - size_t load_smem_b_0_k_2 = load_smem_b_0_k_0 + (32 * 128); - size_t load_smem_b_1_k_2 = load_smem_b_1_k_0 + (32 * 128); - size_t load_smem_b_2_k_2 = load_smem_b_2_k_0 + (32 * 128); - size_t load_smem_b_3_k_2 = load_smem_b_3_k_0 + (32 * 128); - - size_t load_smem_a_0_k_3 = load_smem_a_row + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); // r60 = r293 + r322; - size_t load_smem_a_1_k_3 = load_smem_a_0_k_3 + (32 * 64); - size_t load_smem_b_0_k_3 = load_smem_b_0_k_0 + (48 * 128); - size_t load_smem_b_1_k_3 = load_smem_b_1_k_0 + (48 * 128); - size_t load_smem_b_2_k_3 = load_smem_b_2_k_0 + (48 * 128); - size_t load_smem_b_3_k_3 = load_smem_b_3_k_0 + (48 * 128); - - // create shared mem (A_1 8192 bytes, A_2 8192 bytes, B_1 16384 bytes, B2_16384 bytes) - __shared__ alignas(16) char smem[49152]; - - // create accs (16 WMMAs and 4 output elements each) and zero - float4 acc_frag_0_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements (2) - half8 a_frag_0; - half8 a_frag_1; - - // create register for block B elements (8) - half4 b_frag_0; - half4 b_frag_1; - half4 b_frag_2; - half4 b_frag_3; - half4 b_frag_4; - half4 b_frag_5; - half4 b_frag_6; - half4 b_frag_7; - - half *smem_a_even = (half *)(smem); - half *smem_a_odd = (half *)(smem + 8192); - half *smem_b_even = (half *)(smem + 16384); - half *smem_b_odd = (half *)(smem + 32768); - - // https://developer.nvidia.com/blog/controlling-data-movement-to-boost-performance-on-ampere-architecture/ - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#asynchronous-data-copies - - // start first pre-fetch load A - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_even[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start first pre-fetch load B - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_even[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - __syncthreads(); - - // start second pre-fetch load A - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_odd[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start second pre-fetch load B - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_odd[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - - // wait on needed prefetch value - __pipeline_wait_prior(0); // TODO: this enables fast iterations, but incorrect results with 1 (it shouldn't) - __syncthreads(); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - // BLOCK_K==4: unroll 4 iterations of ldmatrix/wmma - half *smem_a_curr = (block_k % 2) ? smem_a_even : smem_a_odd; - half *smem_b_curr = (block_k % 2) ? smem_b_even : smem_b_odd; - - // first load 16 K elements and 16 WMMAs: BLOCK_M==2 * BLOCK_N==8 - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_0]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_0]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_1]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_2]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_2]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_2]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_2]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_2]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_2]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // last 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_3]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_3]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_3]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_3]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_3]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_3]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // prefetch next iteration if needed - __syncthreads(); - if (block_k < (num_k_blocks-2)) { - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - - global_a_off += 64; - global_b_off += 64 * N; - } - __pipeline_commit(); - - if (block_k < num_k_blocks-1) { - __pipeline_wait_prior(1); - __syncthreads(); - } - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // store registers to smem first, then read back to do float4 writes to global - float *smem_d = (float *)(smem); - size_t smem_d_off = (wg_m * 16 * N_PAD) + (wg_n * 16) + ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N_PAD); - smem_d[smem_d_off + 0 + ( 0*8) ] = acc_frag_0_0.x; - smem_d[smem_d_off + 1 + ( 0*8) ] = acc_frag_0_0.y; - smem_d[smem_d_off + 0 + ( 0*8) + (8*N_PAD)] = acc_frag_0_0.z; - smem_d[smem_d_off + 1 + ( 0*8) + (8*N_PAD)] = acc_frag_0_0.w; - smem_d[smem_d_off + 0 + ( 1*8) ] = acc_frag_0_1.x; - smem_d[smem_d_off + 1 + ( 1*8) ] = acc_frag_0_1.y; - smem_d[smem_d_off + 0 + ( 1*8) + (8*N_PAD)] = acc_frag_0_1.z; - smem_d[smem_d_off + 1 + ( 1*8) + (8*N_PAD)] = acc_frag_0_1.w; - smem_d[smem_d_off + 0 + ( 4*8) ] = acc_frag_0_2.x; - smem_d[smem_d_off + 1 + ( 4*8) ] = acc_frag_0_2.y; - smem_d[smem_d_off + 0 + ( 4*8) + (8*N_PAD)] = acc_frag_0_2.z; - smem_d[smem_d_off + 1 + ( 4*8) + (8*N_PAD)] = acc_frag_0_2.w; - smem_d[smem_d_off + 0 + ( 5*8) ] = acc_frag_0_3.x; - smem_d[smem_d_off + 1 + ( 5*8) ] = acc_frag_0_3.y; - smem_d[smem_d_off + 0 + ( 5*8) + (8*N_PAD)] = acc_frag_0_3.z; - smem_d[smem_d_off + 1 + ( 5*8) + (8*N_PAD)] = acc_frag_0_3.w; - smem_d[smem_d_off + 0 + ( 8*8) ] = acc_frag_0_4.x; - smem_d[smem_d_off + 1 + ( 8*8) ] = acc_frag_0_4.y; - smem_d[smem_d_off + 0 + ( 8*8) + (8*N_PAD)] = acc_frag_0_4.z; - smem_d[smem_d_off + 1 + ( 8*8) + (8*N_PAD)] = acc_frag_0_4.w; - smem_d[smem_d_off + 0 + ( 9*8) ] = acc_frag_0_5.x; - smem_d[smem_d_off + 1 + ( 9*8) ] = acc_frag_0_5.y; - smem_d[smem_d_off + 0 + ( 9*8) + (8*N_PAD)] = acc_frag_0_5.z; - smem_d[smem_d_off + 1 + ( 9*8) + (8*N_PAD)] = acc_frag_0_5.w; - smem_d[smem_d_off + 0 + (12*8) ] = acc_frag_0_6.x; - smem_d[smem_d_off + 1 + (12*8) ] = acc_frag_0_6.y; - smem_d[smem_d_off + 0 + (12*8) + (8*N_PAD)] = acc_frag_0_6.z; - smem_d[smem_d_off + 1 + (12*8) + (8*N_PAD)] = acc_frag_0_6.w; - smem_d[smem_d_off + 0 + (13*8) ] = acc_frag_0_7.x; - smem_d[smem_d_off + 1 + (13*8) ] = acc_frag_0_7.y; - smem_d[smem_d_off + 0 + (13*8) + (8*N_PAD)] = acc_frag_0_7.z; - smem_d[smem_d_off + 1 + (13*8) + (8*N_PAD)] = acc_frag_0_7.w; - - __syncthreads(); - size_t load_smem_d_off = ((threads % 32) * 4) + ((threads / 32) * N_PAD); - float4 d_0_0 = *((float4 *)(smem_d + load_smem_d_off + ( 0 * N_PAD))); - float4 d_0_1 = *((float4 *)(smem_d + load_smem_d_off + ( 4 * N_PAD))); - float4 d_0_2 = *((float4 *)(smem_d + load_smem_d_off + ( 8 * N_PAD))); - float4 d_0_3 = *((float4 *)(smem_d + load_smem_d_off + (12 * N_PAD))); - float4 d_0_4 = *((float4 *)(smem_d + load_smem_d_off + (16 * N_PAD))); - float4 d_0_5 = *((float4 *)(smem_d + load_smem_d_off + (20 * N_PAD))); - float4 d_0_6 = *((float4 *)(smem_d + load_smem_d_off + (24 * N_PAD))); - float4 d_0_7 = *((float4 *)(smem_d + load_smem_d_off + (28 * N_PAD))); - - __syncthreads(); - smem_d[smem_d_off + 0 + ( 0*8) ] = acc_frag_1_0.x; - smem_d[smem_d_off + 1 + ( 0*8) ] = acc_frag_1_0.y; - smem_d[smem_d_off + 0 + ( 0*8) + (8*N_PAD)] = acc_frag_1_0.z; - smem_d[smem_d_off + 1 + ( 0*8) + (8*N_PAD)] = acc_frag_1_0.w; - smem_d[smem_d_off + 0 + ( 1*8) ] = acc_frag_1_1.x; - smem_d[smem_d_off + 1 + ( 1*8) ] = acc_frag_1_1.y; - smem_d[smem_d_off + 0 + ( 1*8) + (8*N_PAD)] = acc_frag_1_1.z; - smem_d[smem_d_off + 1 + ( 1*8) + (8*N_PAD)] = acc_frag_1_1.w; - smem_d[smem_d_off + 0 + ( 4*8) ] = acc_frag_1_2.x; - smem_d[smem_d_off + 1 + ( 4*8) ] = acc_frag_1_2.y; - smem_d[smem_d_off + 0 + ( 4*8) + (8*N_PAD)] = acc_frag_1_2.z; - smem_d[smem_d_off + 1 + ( 4*8) + (8*N_PAD)] = acc_frag_1_2.w; - smem_d[smem_d_off + 0 + ( 5*8) ] = acc_frag_1_3.x; - smem_d[smem_d_off + 1 + ( 5*8) ] = acc_frag_1_3.y; - smem_d[smem_d_off + 0 + ( 5*8) + (8*N_PAD)] = acc_frag_1_3.z; - smem_d[smem_d_off + 1 + ( 5*8) + (8*N_PAD)] = acc_frag_1_3.w; - smem_d[smem_d_off + 0 + ( 8*8) ] = acc_frag_1_4.x; - smem_d[smem_d_off + 1 + ( 8*8) ] = acc_frag_1_4.y; - smem_d[smem_d_off + 0 + ( 8*8) + (8*N_PAD)] = acc_frag_1_4.z; - smem_d[smem_d_off + 1 + ( 8*8) + (8*N_PAD)] = acc_frag_1_4.w; - smem_d[smem_d_off + 0 + ( 9*8) ] = acc_frag_1_5.x; - smem_d[smem_d_off + 1 + ( 9*8) ] = acc_frag_1_5.y; - smem_d[smem_d_off + 0 + ( 9*8) + (8*N_PAD)] = acc_frag_1_5.z; - smem_d[smem_d_off + 1 + ( 9*8) + (8*N_PAD)] = acc_frag_1_5.w; - smem_d[smem_d_off + 0 + (12*8) ] = acc_frag_1_6.x; - smem_d[smem_d_off + 1 + (12*8) ] = acc_frag_1_6.y; - smem_d[smem_d_off + 0 + (12*8) + (8*N_PAD)] = acc_frag_1_6.z; - smem_d[smem_d_off + 1 + (12*8) + (8*N_PAD)] = acc_frag_1_6.w; - smem_d[smem_d_off + 0 + (13*8) ] = acc_frag_1_7.x; - smem_d[smem_d_off + 1 + (13*8) ] = acc_frag_1_7.y; - smem_d[smem_d_off + 0 + (13*8) + (8*N_PAD)] = acc_frag_1_7.z; - smem_d[smem_d_off + 1 + (13*8) + (8*N_PAD)] = acc_frag_1_7.w; - - __syncthreads(); - float4 d_1_0 = *((float4 *)(smem_d + load_smem_d_off + ( 0 * N_PAD))); - float4 d_1_1 = *((float4 *)(smem_d + load_smem_d_off + ( 4 * N_PAD))); - float4 d_1_2 = *((float4 *)(smem_d + load_smem_d_off + ( 8 * N_PAD))); - float4 d_1_3 = *((float4 *)(smem_d + load_smem_d_off + (12 * N_PAD))); - float4 d_1_4 = *((float4 *)(smem_d + load_smem_d_off + (16 * N_PAD))); - float4 d_1_5 = *((float4 *)(smem_d + load_smem_d_off + (20 * N_PAD))); - float4 d_1_6 = *((float4 *)(smem_d + load_smem_d_off + (24 * N_PAD))); - float4 d_1_7 = *((float4 *)(smem_d + load_smem_d_off + (28 * N_PAD))); - - __syncthreads(); - float *global_d = &data0[((grid_m * 64) * N) + (grid_n * 128) + ((threads % 32) * 4) + ((threads / 32) * N)]; - *((float4 *)(global_d + 0*N)) = d_0_0; - *((float4 *)(global_d + 4*N)) = d_0_1; - *((float4 *)(global_d + 8*N)) = d_0_2; - *((float4 *)(global_d + 12*N)) = d_0_3; - *((float4 *)(global_d + 16*N)) = d_0_4; - *((float4 *)(global_d + 20*N)) = d_0_5; - *((float4 *)(global_d + 24*N)) = d_0_6; - *((float4 *)(global_d + 28*N)) = d_0_7; - *((float4 *)(global_d + 32*N)) = d_1_0; - *((float4 *)(global_d + 36*N)) = d_1_1; - *((float4 *)(global_d + 40*N)) = d_1_2; - *((float4 *)(global_d + 44*N)) = d_1_3; - *((float4 *)(global_d + 48*N)) = d_1_4; - *((float4 *)(global_d + 52*N)) = d_1_5; - *((float4 *)(global_d + 56*N)) = d_1_6; - *((float4 *)(global_d + 60*N)) = d_1_7; -} diff --git a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.swizzled_smem_input.cu b/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.swizzled_smem_input.cu deleted file mode 100644 index 8e168b89..00000000 --- a/tinygrad/extra/gemm/max_kernels/nv.fp16_fp32_fp32.swizzled_smem_input.cu +++ /dev/null @@ -1,371 +0,0 @@ -#define INFINITY (__int_as_float(0x7f800000)) -#define NAN (__int_as_float(0x7fffffff)) -#include -#include -#define N_PAD 132 - -struct __align__(8) half4 { half x, y, z, w; }; -__device__ half4 make_half4(half x, half y, half z, half w) { half4 r={x, y, z, w}; return r; } - -struct __align__(16) half8 { half x, y, z, w, a, b, c, d; }; -__device__ half8 make_half8(half x, half y, half z, half w, half a, half b, half c, half d) { half8 r={x, y, z, w, a, b, c, d}; return r; } - -__device__ void __ldmatrix_a_elems(half8 *regs, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr = reinterpret_cast(regs); - addr[0] = reg0; - addr[1] = reg1; - addr[2] = reg2; - addr[3] = reg3; -} - -__device__ void __ldmatrix_b_elems(half4 *regs_lo, half4 *regs_hi, half *smem) { - uint32_t reg0, reg1, reg2, reg3; - asm volatile( - "ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16 {%0, %1, %2, %3}, [%4];" - : "=r"(reg0), "=r"(reg1), "=r"(reg2), "=r"(reg3) - : "l"(__cvta_generic_to_shared(smem)) - ); - uint32_t *addr_lo = reinterpret_cast(regs_lo); - uint32_t *addr_hi = reinterpret_cast(regs_hi); - addr_lo[0] = reg0; - addr_lo[1] = reg1; - addr_hi[0] = reg2; - addr_hi[1] = reg3; -} - -__device__ float4 __WMMA_8_16_16_half_float(half8 a, half4 b, float4 c) { - int *a_pk = (int *) (&a), *b_pk = (int *) (&b); - asm( "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 { %0, %1, %2, %3 }, { %4, %5, %6, %7 }, { %8, %9 }, { %0, %1, %2, %3 };" - : "+f"(c.x), "+f"(c.y), "+f"(c.z), "+f"(c.w) : "r"(a_pk[0]), "r"(a_pk[1]), "r"(a_pk[2]), "r"(a_pk[3]), "r"(b_pk[0]), "r"(b_pk[1]) ); - return c; -} - -extern "C" __global__ void __launch_bounds__(128) wmma_example(float* data0, const half* data1, const half* data2, int N, int K) { - int grid_m = blockIdx.x; /* M//64 */ - int grid_n = blockIdx.y; /* N//128 */ - int threads = threadIdx.x; /* 128 */ - int wg_m = (threads/64); // 0 or 1 for 1st and 3rd blocks of b_m=16xb_k=16 vs 2nd and 4th blocks - int wg_n = (threads/32)%2; // 0 or 1 for 1st, 3rd, 5th, 7th blocks of b_n=16xb_k=16 vs 2nd, 4th, 6th, 8th blocks - differs from triton - int wg_threads = threads%32; - int num_k_blocks = K / 64; - - // load indexes - size_t global_a_off = ((grid_m * 64) * K) + ((threads % 8) * 8) + ((threads / 8) * K); - size_t global_b_off = (grid_n * 128) + ((threads % 16) * 8) + ((threads / 16) * N); - - // swizzled smem store offsets - columns of smem are swizzled - // here's a link to a description of the triton: https://github.com/triton-lang/triton/discussions/2026#discussioncomment-6746579 - // see also the thunderkittens impl: https://github.com/HazyResearch/ThunderKittens/blob/main/include/types/shared/st.cuh - size_t store_smem_a_off = ((threads / 8) * 64) + (((threads * 8) ^ threads) & 56); // r15 - size_t store_smem_b_off = ((threads / 16) * 128) + (((threads / 16) * 8) ^ ((threads % 16) * 8)); // r19 - - // ldmatrix indices - // threads 0-7 are row starts for A, 8-15 for B, 16-23 for C, 24-31 for D - // [ A | C ] - // [ - + - ] - // [ B | D ] - - // swizzled ldmatrix - size_t load_smem_a_row = ((wg_m * 16) + (threads % 16)) * 64; // r293 - size_t load_smem_a_phase = (threads / 16) % 2; // r4 - - size_t load_smem_b_row = (threads % 16) * 128; // r299 - size_t load_smem_b_phase = (wg_n * 2) + (((threads / 16) % 2)); // r297 -- this differs from the generated triton kernel (swapped order) - - size_t load_smem_a_0_k_0 = load_smem_a_row + (((load_smem_a_phase + 0) ^ (threads % 8)) * 8); // r38 - size_t load_smem_a_1_k_0 = load_smem_a_0_k_0 + (32 * 64); - size_t load_smem_b_0_k_0 = load_smem_b_row + (((load_smem_b_phase + 0) ^ (threads % 8)) * 8); - size_t load_smem_b_1_k_0 = load_smem_b_row + (((load_smem_b_phase + 4) ^ (threads % 8)) * 8); - size_t load_smem_b_2_k_0 = load_smem_b_row + (((load_smem_b_phase + 8) ^ (threads % 8)) * 8); - size_t load_smem_b_3_k_0 = load_smem_b_row + (((load_smem_b_phase + 12) ^ (threads % 8)) * 8); - - size_t load_smem_a_0_k_1 = load_smem_a_row + (((load_smem_a_phase + 2) ^ (threads % 8)) * 8); // r58 = r293 + r316; - size_t load_smem_a_1_k_1 = load_smem_a_0_k_1 + (32 * 64); - size_t load_smem_b_0_k_1 = load_smem_b_0_k_0 + (16 * 128); - size_t load_smem_b_1_k_1 = load_smem_b_1_k_0 + (16 * 128); - size_t load_smem_b_2_k_1 = load_smem_b_2_k_0 + (16 * 128); - size_t load_smem_b_3_k_1 = load_smem_b_3_k_0 + (16 * 128); - - size_t load_smem_a_0_k_2 = load_smem_a_row + (((load_smem_a_phase + 4) ^ (threads % 8)) * 8); // r59 = r293 + r319; - size_t load_smem_a_1_k_2 = load_smem_a_0_k_2 + (32 * 64); - size_t load_smem_b_0_k_2 = load_smem_b_0_k_0 + (32 * 128); - size_t load_smem_b_1_k_2 = load_smem_b_1_k_0 + (32 * 128); - size_t load_smem_b_2_k_2 = load_smem_b_2_k_0 + (32 * 128); - size_t load_smem_b_3_k_2 = load_smem_b_3_k_0 + (32 * 128); - - size_t load_smem_a_0_k_3 = load_smem_a_row + (((load_smem_a_phase + 6) ^ (threads % 8)) * 8); // r60 = r293 + r322; - size_t load_smem_a_1_k_3 = load_smem_a_0_k_3 + (32 * 64); - size_t load_smem_b_0_k_3 = load_smem_b_0_k_0 + (48 * 128); - size_t load_smem_b_1_k_3 = load_smem_b_1_k_0 + (48 * 128); - size_t load_smem_b_2_k_3 = load_smem_b_2_k_0 + (48 * 128); - size_t load_smem_b_3_k_3 = load_smem_b_3_k_0 + (48 * 128); - - // create shared mem (A 8192 bytes, B 16384 bytes) - __shared__ alignas(16) char smem[24576]; - - // create accs (16 WMMAs and 4 output elements each) and zero - float4 acc_frag_0_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_0_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_0 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_1 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_2 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_3 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_4 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_5 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_6 = make_float4(0.0f,0.0f,0.0f,0.0f); - float4 acc_frag_1_7 = make_float4(0.0f,0.0f,0.0f,0.0f); - - // create registers for block A elements (2) - half8 a_frag_0; - half8 a_frag_1; - - // create register for block B elements (8) - half4 b_frag_0; - half4 b_frag_1; - half4 b_frag_2; - half4 b_frag_3; - half4 b_frag_4; - half4 b_frag_5; - half4 b_frag_6; - half4 b_frag_7; - - half *smem_a = (half *)(smem); - half *smem_b = (half *)(smem + 8192); - - // https://developer.nvidia.com/blog/controlling-data-movement-to-boost-performance-on-ampere-architecture/ - // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#asynchronous-data-copies - - // start first pre-fetch load A - __pipeline_memcpy_async(&smem_a[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - // start first pre-fetch load B - __pipeline_memcpy_async(&smem_b[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - __pipeline_commit(); - - global_a_off += 64; - global_b_off += 64 * N; - __syncthreads(); - - for (int block_k = 0; block_k < num_k_blocks; block_k++) { - // wait on needed prefetch value - __pipeline_wait_prior(0); - __syncthreads(); - - // BLOCK_K==4: unroll 4 iterations of ldmatrix/wmma - half *smem_a_curr = smem_a; - half *smem_b_curr = smem_b; - - // first load 16 K elements and 16 WMMAs: BLOCK_M==2 * BLOCK_N==8 - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_0]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_0]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_0]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_0]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_0]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_0]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_1]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_1]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_1]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_1]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_1]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_1]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // next 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_2]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_2]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_2]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_2]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_2]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_2]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // last 16 K elements - __ldmatrix_a_elems(&a_frag_0, &smem_a_curr[load_smem_a_0_k_3]); - __ldmatrix_a_elems(&a_frag_1, &smem_a_curr[load_smem_a_1_k_3]); - __ldmatrix_b_elems(&b_frag_0, &b_frag_1, &smem_b_curr[load_smem_b_0_k_3]); - __ldmatrix_b_elems(&b_frag_2, &b_frag_3, &smem_b_curr[load_smem_b_1_k_3]); - __ldmatrix_b_elems(&b_frag_4, &b_frag_5, &smem_b_curr[load_smem_b_2_k_3]); - __ldmatrix_b_elems(&b_frag_6, &b_frag_7, &smem_b_curr[load_smem_b_3_k_3]); - acc_frag_0_0 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_0, acc_frag_0_0); - acc_frag_0_1 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_1, acc_frag_0_1); - acc_frag_0_2 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_2, acc_frag_0_2); - acc_frag_0_3 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_3, acc_frag_0_3); - acc_frag_0_4 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_4, acc_frag_0_4); - acc_frag_0_5 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_5, acc_frag_0_5); - acc_frag_0_6 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_6, acc_frag_0_6); - acc_frag_0_7 = __WMMA_8_16_16_half_float(a_frag_0, b_frag_7, acc_frag_0_7); - acc_frag_1_0 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_0, acc_frag_1_0); - acc_frag_1_1 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_1, acc_frag_1_1); - acc_frag_1_2 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_2, acc_frag_1_2); - acc_frag_1_3 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_3, acc_frag_1_3); - acc_frag_1_4 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_4, acc_frag_1_4); - acc_frag_1_5 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_5, acc_frag_1_5); - acc_frag_1_6 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_6, acc_frag_1_6); - acc_frag_1_7 = __WMMA_8_16_16_half_float(a_frag_1, b_frag_7, acc_frag_1_7); - - // prefetch next iteration if needed - __syncthreads(); - if (block_k < (num_k_blocks-1)) { - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + ( 0)], &data1[global_a_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (16*64)], &data1[global_a_off + (16*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (32*64)], &data1[global_a_off + (32*K)], 16); - __pipeline_memcpy_async(&smem_a_curr[store_smem_a_off + (48*64)], &data1[global_a_off + (48*K)], 16); - - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 0)], &data2[global_b_off + ( 0)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + ( 8*128)], &data2[global_b_off + ( 8*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (16*128)], &data2[global_b_off + (16*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (24*128)], &data2[global_b_off + (24*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (32*128)], &data2[global_b_off + (32*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (40*128)], &data2[global_b_off + (40*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (48*128)], &data2[global_b_off + (48*N)], 16); - __pipeline_memcpy_async(&smem_b_curr[store_smem_b_off + (56*128)], &data2[global_b_off + (56*N)], 16); - - global_a_off += 64; - global_b_off += 64 * N; - } - __pipeline_commit(); - } - - // write accumulators to output - __pipeline_wait_prior(0); - __syncthreads(); - - // slower way: write floats one by one to data0 - size_t wg_c_off = ((grid_m * 64) * N) + (grid_n * 128) + (wg_m * 16 * N) + (wg_n * 16); - size_t thread_c_off = ((wg_threads % 4) * 2) + (((wg_threads / 4) % 8) * N); - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_0_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_0_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_0_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_0_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_0_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_0_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_0_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_0_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_0_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_0_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_0_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_0_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_0_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_0_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_0_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_0_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_0_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_0_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_0_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_0_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_0_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_0_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_0_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_0_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_0_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_0_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_0_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_0_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_0_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_0_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_0_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_0_7.w; - wg_c_off += 32*N; - data0[wg_c_off + thread_c_off + 0 + ( 0*8)] = acc_frag_1_0.x; - data0[wg_c_off + thread_c_off + 1 + ( 0*8)] = acc_frag_1_0.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 0*8)] = acc_frag_1_0.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 0*8)] = acc_frag_1_0.w; - data0[wg_c_off + thread_c_off + 0 + ( 1*8)] = acc_frag_1_1.x; - data0[wg_c_off + thread_c_off + 1 + ( 1*8)] = acc_frag_1_1.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 1*8)] = acc_frag_1_1.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 1*8)] = acc_frag_1_1.w; - data0[wg_c_off + thread_c_off + 0 + ( 4*8)] = acc_frag_1_2.x; - data0[wg_c_off + thread_c_off + 1 + ( 4*8)] = acc_frag_1_2.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 4*8)] = acc_frag_1_2.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 4*8)] = acc_frag_1_2.w; - data0[wg_c_off + thread_c_off + 0 + ( 5*8)] = acc_frag_1_3.x; - data0[wg_c_off + thread_c_off + 1 + ( 5*8)] = acc_frag_1_3.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 5*8)] = acc_frag_1_3.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 5*8)] = acc_frag_1_3.w; - data0[wg_c_off + thread_c_off + 0 + ( 8*8)] = acc_frag_1_4.x; - data0[wg_c_off + thread_c_off + 1 + ( 8*8)] = acc_frag_1_4.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 8*8)] = acc_frag_1_4.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 8*8)] = acc_frag_1_4.w; - data0[wg_c_off + thread_c_off + 0 + ( 9*8)] = acc_frag_1_5.x; - data0[wg_c_off + thread_c_off + 1 + ( 9*8)] = acc_frag_1_5.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + ( 9*8)] = acc_frag_1_5.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + ( 9*8)] = acc_frag_1_5.w; - data0[wg_c_off + thread_c_off + 0 + (12*8)] = acc_frag_1_6.x; - data0[wg_c_off + thread_c_off + 1 + (12*8)] = acc_frag_1_6.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (12*8)] = acc_frag_1_6.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (12*8)] = acc_frag_1_6.w; - data0[wg_c_off + thread_c_off + 0 + (13*8)] = acc_frag_1_7.x; - data0[wg_c_off + thread_c_off + 1 + (13*8)] = acc_frag_1_7.y; - data0[wg_c_off + thread_c_off + (8 * N) + 0 + (13*8)] = acc_frag_1_7.z; - data0[wg_c_off + thread_c_off + (8 * N) + 1 + (13*8)] = acc_frag_1_7.w; -} diff --git a/tinygrad/extra/gemm/max_matmul.py b/tinygrad/extra/gemm/max_matmul.py deleted file mode 100644 index 975f4b1d..00000000 --- a/tinygrad/extra/gemm/max_matmul.py +++ /dev/null @@ -1,230 +0,0 @@ -import numpy as np, os -from tinygrad.helpers import getenv, flat_mv -from tinygrad import dtypes -from typing import Optional, List, Tuple, cast, Dict, Final, DefaultDict, Self - -# for copied uops -from tinygrad.codegen.kernel import Kernel, KernelOptError -from tinygrad.uop.ops import UOp, Ops, BinaryOps, UnaryOps, TernaryOps, KernelInfo -from tinygrad.engine.search import Opt, OptOps -from tinygrad import Device, dtypes, Tensor -from tinygrad.dtype import PtrDType, DType, DTYPES_DICT -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -script_dir = os.path.dirname(os.path.abspath(__file__)) - -# problem variations -DTYPE_IN = DTYPES_DICT[getenv("DTYPE_IN", "half")] -DTYPE_OUT = DTYPES_DICT[getenv("DTYPE_OUT", "half")] -DTYPE_ACC = DTYPES_DICT[getenv("DTYPE_ACC", "float")] -N = getenv("N", 4096) -M = getenv("M", N) -K = getenv("K", N) -CNT = getenv("CNT", 10) -ATOL = getenv("ATOL", 5e-3 if DTYPE_IN == dtypes.float else 1e-2) -RTOL = getenv("RTOL", 1e-4 if DTYPE_IN == dtypes.float else 1e-3) -FLOPS = M * N * K * 2 -BW = 2 * ((M*K) + (K*N) + (M*N)) - -# algorithm variations -INPUT = getenv("INPUT", "RAND") -GEMM_VARIATION = getenv("GEMM_VARIATION", "nv_hcopt") - -def randoms(): - if INPUT == "RAND": - na = np.random.default_rng().normal(scale=1.0, size=(M,K)).astype(dtype=np.float32) - nb = np.random.default_rng().normal(scale=1.0, size=(K,N)).astype(dtype=np.float32) - elif INPUT == "IDENTITY" and M==N==K: - na = np.identity(K, dtype=np.float32) - nb = np.identity(K, dtype=np.float32) - elif INPUT == "OUTPUTONES" and M==K: - na = np.identity(K, dtype=np.float32) - nb = np.ones((K,N), dtype=np.float32) - else: - na = np.ones((M,K), dtype=np.float32) - nb = np.ones((K,N), dtype=np.float32) - nc = np.zeros(M*N, np.float32) - if DTYPE_IN != dtypes.float: - na = na.astype(np.bfloat16 if DTYPE_IN == dtypes.bfloat16 else np.float16) - nb = nb.astype(np.bfloat16 if DTYPE_IN == dtypes.bfloat16 else np.float16) - if DTYPE_OUT != dtypes.float: - nc = nc.astype(np.bfloat16 if DTYPE_IN == dtypes.bfloat16 else np.float16) - return na, nb, nc - -def ast_to_cuda_prog(compiler, ast, opts): - k = Kernel(ast) - k.apply_opts(opts) - p = k.to_program() - return CUDAProgram(device, p.function_name, compiler.compile(p.src)) - -if __name__ == "__main__": - print(f"gemm variation: {GEMM_VARIATION=} {M=} {N=} {K=} {DTYPE_IN=} {DTYPE_OUT=} {DTYPE_ACC=}") - prog, global_size, local_size = None, None, None - - if getenv("CUDA") == 1: - from tinygrad.runtime.ops_cuda import CUDAAllocator, CUDADevice, CUDAProgram, CUDACompiler - device = CUDADevice("cuda:0") - compiler = CUDACompiler(device.arch) - cudaalloc = CUDAAllocator(device) - - a = cudaalloc.alloc(M*K*DTYPE_IN.itemsize) - b = cudaalloc.alloc(K*N*DTYPE_IN.itemsize) - c = cudaalloc.alloc(M*N*DTYPE_OUT.itemsize) - - if GEMM_VARIATION == "max" and (M%64)==0 and (N%128)==0 and (K%64)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.float and DTYPE_ACC == dtypes.float: - print("Using CUDA and triton-generated kernel") - # See nv_triton_gemm.annotated.ptx for PTX code which was generated from `PYTHONPATH=. DEBUG=6 CUDA=1 PTX=1 python3 extra/gemm/triton_nv_matmul.py` - # this kernel with M=N=K=4096 does 162TFLOPS, vs torch at 144TFLOPS and BEAM=8 tinygrad at 138TFLOPS. theo max is 165TFLOPS. - - # WMMA element size is (M, N, K) = (16, 8, 16) - # warpgroup size in WMMA tiles is (B_M, B_N, B_K) = (2, 8, 4) so 64 HMMA calls per threadgroup reduce iteration - # thread block size is (T_M, T_N, T_K) = (2, 2, 1), i.e. macro blocks in M and N, so 256 HMMA calls per kernel reduce iteration - # kernel reduce iteration size in elements = (64, 128, 64) - # single iteration SMEM_A = (64 * 64) * (2 bytes / half) = 8192 bytes, SMEM_B = (128 * 64) * (2 bytes / half) = 16384 bytes - # double-buffer smem = (8192 + 16384) * 2 = 49152 bytes - # reduce for_loop size = [1, 1, (4096 // 16 // 4)==64] - # NOTE: T_K > 0 would be group_for_reduce - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp32_fp32.max.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [M//64, N//128, 1], - 'local_size': [128, 1, 1], # 4 warpgroups == (T_M:=2) * (T_N:=2) - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "2_stage_swizzled_smem_input" and (M%64)==0 and (N%128)==0 and (K%64)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.float and DTYPE_ACC == dtypes.float: - print("Using CUDA, 2-stage reduce pipeline, swizzled SMEM inputs") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp32_fp32.2_stage_swizzled_smem_input.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [M//64, N//128, 1], - 'local_size': [128, 1, 1], # 4 warpgroups == (T_M:=2) * (T_N:=2) - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "swizzled_smem_input" and (M%64)==0 and (N%128)==0 and (K%64)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.float and DTYPE_ACC == dtypes.float: - print("Using CUDA, swizzled SMEM inputs") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp32_fp32.swizzled_smem_input.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [M//64, N//128, 1], - 'local_size': [128, 1, 1], # 4 warpgroups == (T_M:=2) * (T_N:=2) - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "flat_smem_input" and (M%64)==0 and (N%128)==0 and (K%64)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.float and DTYPE_ACC == dtypes.float: - print("Using CUDA, flat SMEM inputs") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp32_fp32.flat_smem_input.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [M//64, N//128, 1], - 'local_size': [128, 1, 1], # 4 warpgroups == (T_M:=2) * (T_N:=2) - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "hcopt" and M == N == K == 4096 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.float: - print("Using CUDA and generated hcopt") - # [Opt(op=OptOps.TC, axis=0, amt=0), Opt(op=OptOps.UPCAST, axis=0, amt=4), Opt(op=OptOps.UPCAST, axis=1, amt=4), Opt(op=OptOps.LOCAL, axis=1, amt=4)] - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp32_fp16.hcopt.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [32, 64, 1], - 'local_size': [16, 2, 4], # 16,2 are warp, 4 workgroups upcasted to axis=1 - 'wait': True, - } - elif GEMM_VARIATION == "2_stage" and (M%64)== 0 and (N%128)==0 and (K%64)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.half: - print("Using CUDA and un-optimized 2-stage, swizzled SMEM inputs and direct acc to output kernel") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp16_fp16.2_stage.cu')).read())) - args = (c, a, b) - kwargs = { - 'global_size': [M//64, N//128, 1], - 'local_size': [128, 1, 1], # 4 warpgroups == (T_M:=2) * (T_N:=2) - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "3_stage" and (M%256)== 0 and (N%128)==0 and (K%32)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.half: - print("Using CUDA and 3-stage (interleave global copies and ldmatrix)") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp16_fp16.3_stage.cu')).read()), 73728) - args = (c, a, b) - kwargs = { - 'global_size': [M//256, N//128, 1], - 'local_size': [32, 4, 2], # 8 warpgroups, WG_M=4 and WG_N=2 - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "3_stage_swizzled" and (M%256)== 0 and (N%128)==0 and (K%32)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.half: - print("Using CUDA and 3-stage (interleave global copies and ldmatrix) and swizzled SMEM inputs") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp16_fp16.3_stage_swizzled.cu')).read()), 73728) - args = (c, a, b) - kwargs = { - 'global_size': [M//256, N//128, 1], - 'local_size': [32, 4, 2], # 8 warpgroups, WG_M=4 and WG_N=2 - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "max" and (M%256)== 0 and (N%128)==0 and (K%32)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.half: - print("Using CUDA and 3-stage (interleave global copies and ldmatrix), swizzled SMEM inputs and epilogue") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp16_fp16.max.cu')).read()), 73728) - args = (c, a, b) - kwargs = { - 'global_size': [M//256, N//128, 1], - 'local_size': [32, 4, 2], # 8 warpgroups, WG_M=4 and WG_N=2 - 'wait': True, - 'vals': (N, K), - } - elif GEMM_VARIATION == "no_xor" and (M%256)== 0 and (N%128)==0 and (K%32)==0 and DTYPE_IN == dtypes.half and DTYPE_OUT == dtypes.half and DTYPE_ACC == dtypes.half: - print("Using CUDA and 3-stage (interleave global copies and ldmatrix), swizzled SMEM inputs and epilogue") - prog = CUDAProgram(device, "wmma_example", compiler.compile(open(os.path.join(script_dir, 'max_kernels/nv.fp16_fp16_fp16.no_xor.cu')).read()), 73728) - args = (c, a, b) - kwargs = { - 'global_size': [M//256, N//128, 1], - 'local_size': [32, 4, 2], # 8 warpgroups, WG_M=4 and WG_N=2 - 'wait': True, - 'vals': (N, K), - } - else: - raise RuntimeError(f"invalid gemm variation: {GEMM_VARIATION=} {M=} {N=} {K=} {DTYPE_IN=} {DTYPE_OUT=} {DTYPE_ACC=}") - - tms = [] - na, nb, nc = randoms() - cudaalloc.copyin(a, bytearray(na)) - cudaalloc.copyin(b, bytearray(nb)) - for i in range(CNT): - tms.append(prog(*args, **kwargs)) - cudaalloc.copyout(flat_mv(nc.data), c) - comp = na.astype(np.float32) @ nb.astype(np.float32) - result = nc.reshape(M, N).astype(np.float32) - - print(f"{N*N:10d} {min(tms)*1e6:9.2f} us, would be {FLOPS*1e-9/min(tms):9.2f} GFLOPS matmul, {BW*1e-9/min(tms):.2f} GB/s") - try: - np.testing.assert_allclose(result, comp, atol=ATOL, rtol=RTOL) - except AssertionError as e: - if getenv("DEBUG_VALUES") > 0: - indices = np.where(~np.isclose(result, comp, rtol=RTOL, atol=ATOL)) - non_matching_elements_result = result[indices] - non_matching_elements_comp = comp[indices] - print("valid :", np.where(np.isclose(result, comp, rtol=RTOL, atol=ATOL))) - print("invalid :", indices) - print("result :", non_matching_elements_result) - print("ground truth:", non_matching_elements_comp) - print("result sum :", np.sum(result)) - print("ground sum :", np.sum(comp)) - raise e - - if getenv("DEBUG_VALUES") > 0: - print(comp) - print("ground sum :", np.sum(comp)) - print(result) - print("result sum :", np.sum(result)) - - elif getenv("AMD") == 1: - # note: https://hipfft.readthedocs.io/en/rocm-6.1.2/how-to/fine-tuning-llms/optimizing-triton-kernel.html - - # also this is different than the rocblas/tensile approach to GEMM - # see: https://github.com/ROCm/Tensile/blob/develop/Tensile/KernelWriterAssembly.py - raise RuntimeError("invalid max_matmul device") - - else: - raise RuntimeError("invalid max_matmul device") - diff --git a/tinygrad/extra/gemm/metal_conv.py b/tinygrad/extra/gemm/metal_conv.py deleted file mode 100644 index 1dc7a18e..00000000 --- a/tinygrad/extra/gemm/metal_conv.py +++ /dev/null @@ -1,49 +0,0 @@ -import os -#os.environ["METAL"] = "1" -import numpy as np - -BS = 64 -CIN = 256 -COUT = 256 -HW = 32 -K = 3 -PADDING = 0 -# TODO: this is doing some trick, since with CIN=256 COUT=256 it's over 10.4 TFLOPS. -# are winograd convs less flops? it appears so if they are batched -# https://www.cse.ust.hk/~weiwa/papers/yan-ppopp20.pdf -FLOPS = BS*K*K*CIN*HW*HW*COUT*2 - -nb = np.random.default_rng().standard_normal(size=(BS,CIN,HW,HW), dtype=np.float32) -nc = np.random.default_rng().standard_normal(size=(COUT,CIN,K,K), dtype=np.float32) - -try: - import time, torch, torch.mps - b = torch.from_numpy(nb).to('mps') - c = torch.from_numpy(nc).to('mps') - - def torch_prog(b, c): - st = time.perf_counter() - a = torch.nn.functional.conv2d(b, c, padding=PADDING) - torch.mps.synchronize() - return time.perf_counter() - st - tm = min([torch_prog(b, c) for _ in range(20)]) - print(f"{tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS conv in torch") -except RuntimeError: - print("no torch metal conv") - -from tinygrad.tensor import Tensor -from tinygrad.engine.jit import TinyJit -from tinygrad import Device -b = Tensor(nb) -c = Tensor(nc) -# TODO: slowness without the JIT I suspect comes from a lack of a caching allocator -@TinyJit -def tiny_jit(b, c): - return b.conv2d(c, padding=PADDING).realize() -def tiny_prog(b, c): - st = time.perf_counter() - a = tiny_jit(b, c) - Device[a.device].synchronize() - return time.perf_counter() - st -tm = min([tiny_prog(b, c) for _ in range(5)]) -print(f"{tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS conv in tinygrad") diff --git a/tinygrad/extra/gemm/metal_matmul.py b/tinygrad/extra/gemm/metal_matmul.py deleted file mode 100644 index 88bf384b..00000000 --- a/tinygrad/extra/gemm/metal_matmul.py +++ /dev/null @@ -1,132 +0,0 @@ -import os -os.environ["METAL"] = "1" -import time -import numpy as np -from tinygrad import Device, dtypes -from tinygrad.helpers import getenv, flat_mv -from tinygrad.runtime.ops_metal import MetalAllocator, MetalDevice, MetalProgram, MetalCompiler - -N = getenv("N", 2048) -LID = 2 - -device = MetalDevice("METAL") -metalalloc = MetalAllocator(device) - -a = metalalloc.alloc(N*N*4) -b = metalalloc.alloc(N*N*4) -c = metalalloc.alloc(N*N*4) - -na = np.zeros((N,N),dtype=np.float32) -nb = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32) #.astype(np.int32).astype(np.float32)N -nc = np.random.default_rng().standard_normal(size=(N,N), dtype=np.float32) #.astype(np.int32).astype(np.float32) - -metalalloc._copyin(b,nb.tobytes()) -metalalloc._copyin(c,nc.tobytes()) - -FLOPS = N*N*N*2 -BW = N*N*3*4 - -prog = MetalProgram(device, "test", MetalCompiler().compile(f""" -#include -#include // Available from Metal version 2.3 released with OS X 11.0+ -using namespace metal; -kernel void test(device float *a, device const float *data1, device const float *data2, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) {{ - a += gid.x * 32 * {N} + (gid.y * {LID} + lid.y) * 32; - data1 += gid.x * 32 * {N}; - data2 += (gid.y * {LID} + lid.y) * 32; - - simdgroup_float8x8 acc[4][4]; - for (uint i = 0; i < 4; i++) {{ - for (uint j = 0; j < 4; j++) {{ - acc[i][j] = simdgroup_float8x8(0); - }} - }} - - simdgroup_float8x8 A[4]; - simdgroup_float8x8 B[4]; - for (uint k = 0; k < {N}; k+=8) {{ - threadgroup_barrier(mem_flags::mem_threadgroup); - simdgroup_load(A[0], data1+k+{0*N}, {N}, ulong2(0, 0)); - simdgroup_load(A[1], data1+k+{8*N}, {N}, ulong2(0, 0)); - simdgroup_load(A[2], data1+k+{16*N}, {N}, ulong2(0, 0)); - simdgroup_load(A[3], data1+k+{24*N}, {N}, ulong2(0, 0)); - simdgroup_load(B[0], data2+0+k*{N}, {N}, ulong2(0, 0)); - simdgroup_load(B[1], data2+8+k*{N}, {N}, ulong2(0, 0)); - simdgroup_load(B[2], data2+16+k*{N}, {N}, ulong2(0, 0)); - simdgroup_load(B[3], data2+24+k*{N}, {N}, ulong2(0, 0)); - - simdgroup_multiply_accumulate(acc[0][0], A[0], B[0], acc[0][0]); - simdgroup_multiply_accumulate(acc[0][1], A[1], B[0], acc[0][1]); - simdgroup_multiply_accumulate(acc[0][2], A[2], B[0], acc[0][2]); - simdgroup_multiply_accumulate(acc[0][3], A[3], B[0], acc[0][3]); - simdgroup_multiply_accumulate(acc[1][0], A[0], B[1], acc[1][0]); - simdgroup_multiply_accumulate(acc[1][1], A[1], B[1], acc[1][1]); - simdgroup_multiply_accumulate(acc[1][2], A[2], B[1], acc[1][2]); - simdgroup_multiply_accumulate(acc[1][3], A[3], B[1], acc[1][3]); - simdgroup_multiply_accumulate(acc[2][0], A[0], B[2], acc[2][0]); - simdgroup_multiply_accumulate(acc[2][1], A[1], B[2], acc[2][1]); - simdgroup_multiply_accumulate(acc[2][2], A[2], B[2], acc[2][2]); - simdgroup_multiply_accumulate(acc[2][3], A[3], B[2], acc[2][3]); - simdgroup_multiply_accumulate(acc[3][0], A[0], B[3], acc[3][0]); - simdgroup_multiply_accumulate(acc[3][1], A[1], B[3], acc[3][1]); - simdgroup_multiply_accumulate(acc[3][2], A[2], B[3], acc[3][2]); - simdgroup_multiply_accumulate(acc[3][3], A[3], B[3], acc[3][3]); - }} - simdgroup_store(acc[0][0], a+{0+0*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[1][0], a+{8+0*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[2][0], a+{16+0*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[3][0], a+{24+0*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[0][1], a+{0+8*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[1][1], a+{8+8*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[2][1], a+{16+8*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[3][1], a+{24+8*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[0][2], a+{0+16*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[1][2], a+{8+16*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[2][2], a+{16+16*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[3][2], a+{24+16*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[0][3], a+{0+24*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[1][3], a+{8+24*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[2][3], a+{16+24*N}, {N}, ulong2(0, 0)); - simdgroup_store(acc[3][3], a+{24+24*N}, {N}, ulong2(0, 0)); -}}""")) -def timeit(fxn): - st = time.perf_counter() - et = fxn() - # NOTE: et doesn't contain the launch overhead - return time.perf_counter() - st -tm = min([timeit(lambda: prog(a, b, c, global_size=[N//(8*4), N//(8*4*LID), 1], local_size=[32, LID, 1], wait=True)) for _ in range(20)]) -comp = nb@nc -metalalloc._copyout(flat_mv(na.data), a) -if N <= 32: - print(na) - print(comp) -print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matmul, {BW*1e-9/tm:.2f} GB/s") -np.testing.assert_allclose(na, comp, atol=1e-3) - -import torch, torch.mps -b = torch.from_numpy(nb).to('mps') -c = torch.from_numpy(nc).to('mps') - -def torch_prog(b, c): - st = time.perf_counter() - a = b@c - torch.mps.synchronize() - return time.perf_counter() - st -tm = min([torch_prog(b, c) for _ in range(20)]) -print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matmul in torch") - -from tinygrad.tensor import Tensor -from tinygrad.engine.jit import TinyJit -b = Tensor(nb) -c = Tensor(nc) -# TODO: slowness without the JIT I suspect comes from a lack of a caching allocator -@TinyJit -def tiny_jit(b, c): - return (b@c).realize() -def tiny_prog(b, c): - st = time.perf_counter() - a = tiny_jit(b, c) - Device["METAL"].synchronize() - return time.perf_counter() - st -tm = min([tiny_prog(b, c) for _ in range(20)]) -print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matmul in tinygrad") diff --git a/tinygrad/extra/gemm/metal_matvec.py b/tinygrad/extra/gemm/metal_matvec.py deleted file mode 100644 index 8fc8c9d3..00000000 --- a/tinygrad/extra/gemm/metal_matvec.py +++ /dev/null @@ -1,113 +0,0 @@ -import numpy as np -import time, torch, torch.mps - -from tinygrad import Tensor, TinyJit, Device -from tinygrad.helpers import flat_mv -from tinygrad.runtime.ops_metal import MetalAllocator, MetalDevice, MetalProgram, MetalCompiler - -N = 16384 -M = 4096 -FLOPS = N*M*2 - -nb = np.random.default_rng().standard_normal(size=(N), dtype=np.float32) #.astype(np.int32).astype(np.float32) -nc = np.random.default_rng().standard_normal(size=(N,M), dtype=np.float32) #.astype(np.int32).astype(np.float32) - -b = torch.from_numpy(nb).to('mps') -c = torch.from_numpy(nc).to('mps') - -def torch_prog(b, c): - st = time.perf_counter() - a = b@c - torch.mps.synchronize() - return time.perf_counter() - st -tm = min([torch_prog(b, c) for _ in range(200)]) -print(f"{N:d}x{M:d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matvec in torch") -torch_a = (b@c).cpu() - -device = MetalDevice("METAL") -metalalloc = MetalAllocator(device) -WORKSIZE_ROW = 16 -WORKSIZE_COL = 1 -LOCAL_SIZE = [32, WORKSIZE_COL, WORKSIZE_ROW] -GLOBAL_SIZE = [M//(LOCAL_SIZE[0]*LOCAL_SIZE[1]*4), 1, 1] -prog = MetalProgram(device, "test", MetalCompiler().compile(f""" -#include -using namespace metal; -kernel void test(device float* data0, const device float* data1, const device float* data2, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) {{ - int gidx0 = gid.x; /* {GLOBAL_SIZE[0]} */ - int lidx1 = lid.x; /* {LOCAL_SIZE[0]} */ - int lidx2 = lid.y; /* {LOCAL_SIZE[1]} */ - int lidx3 = lid.z; /* {LOCAL_SIZE[2]} */ - - // 4 rows per thread - threadgroup float4 acc0[{LOCAL_SIZE[0]*LOCAL_SIZE[1]*LOCAL_SIZE[2]}]; - int acc0_index = ((lidx1*{LOCAL_SIZE[1]})+lidx2)+({LOCAL_SIZE[0]*LOCAL_SIZE[1]}*lidx3); - acc0[acc0_index] = float4(0.0f,0.0f,0.0f,0.0f); - - threadgroup float4 val1[{LOCAL_SIZE[0]*LOCAL_SIZE[1]*LOCAL_SIZE[2]}]; - - // iterate over the columns - for (int ridx2 = 0; ridx2 < {N//(4*LOCAL_SIZE[0]*LOCAL_SIZE[1]*(LOCAL_SIZE[2]))}; ++ridx2) {{ - // load 4*threadgroup_size columns into shared memory - int col_1 = (((lidx3*{N//(4*LOCAL_SIZE[0]*LOCAL_SIZE[1]*(LOCAL_SIZE[2]))})+ridx2)*{LOCAL_SIZE[0]*LOCAL_SIZE[1]})+(lidx1*{LOCAL_SIZE[1]})+lidx2; - val1[(lidx3*{LOCAL_SIZE[1]*LOCAL_SIZE[0]})+((lidx1*{LOCAL_SIZE[1]})+lidx2)] = *((device float4*)(data1+(col_1*4))); - threadgroup_barrier(mem_flags::mem_threadgroup); - - for (int ridx3 = 0; ridx3 < {LOCAL_SIZE[0]*LOCAL_SIZE[1]}; ++ridx3) {{ - int col = ((((lidx3*{N//(4*LOCAL_SIZE[0]*LOCAL_SIZE[1]*(LOCAL_SIZE[2]))})+ridx2)*{LOCAL_SIZE[0]*LOCAL_SIZE[1]})+ridx3); - float4 val1_0 = val1[(lidx3*{LOCAL_SIZE[1]*LOCAL_SIZE[0]})+ridx3]; - float4 val2_0 = (float4)(*((device float4*)(data2+(gidx0*{M//GLOBAL_SIZE[0]})+(((lidx1*{LOCAL_SIZE[1]})+lidx2)*4)+(col*{M*4})+{M*0}))); - float4 val2_1 = (float4)(*((device float4*)(data2+(gidx0*{M//GLOBAL_SIZE[0]})+(((lidx1*{LOCAL_SIZE[1]})+lidx2)*4)+(col*{M*4})+{M*1}))); - float4 val2_2 = (float4)(*((device float4*)(data2+(gidx0*{M//GLOBAL_SIZE[0]})+(((lidx1*{LOCAL_SIZE[1]})+lidx2)*4)+(col*{M*4})+{M*2}))); - float4 val2_3 = (float4)(*((device float4*)(data2+(gidx0*{M//GLOBAL_SIZE[0]})+(((lidx1*{LOCAL_SIZE[1]})+lidx2)*4)+(col*{M*4})+{M*3}))); - acc0[acc0_index] = ((val1_0.x*val2_0)+acc0[acc0_index]); - acc0[acc0_index] = ((val1_0.y*val2_1)+acc0[acc0_index]); - acc0[acc0_index] = ((val1_0.z*val2_2)+acc0[acc0_index]); - acc0[acc0_index] = ((val1_0.w*val2_3)+acc0[acc0_index]); - }} - threadgroup_barrier(mem_flags::mem_threadgroup); - }} /* reduce */ - - if (lidx3 == 0) {{ - float4 out = float4(0.0f,0.0f,0.0f,0.0f); - for (int n = 0; n < {LOCAL_SIZE[2]}; n++) {{ - out += acc0[((lidx1*{LOCAL_SIZE[1]})+lidx2)+({LOCAL_SIZE[0]*LOCAL_SIZE[1]}*n)]; - }} - *( (device float4 *) (data0 + (gidx0*{M//GLOBAL_SIZE[0]}) + ( ( (lidx1*{LOCAL_SIZE[1]})+lidx2 ) * 4 ) ) ) = out; - }} -}} -""")) -a = metalalloc.alloc(M*4) -b = metalalloc.alloc(N*4) -c = metalalloc.alloc(N*M*4) -metalalloc._copyin(b,nb.tobytes()) -metalalloc._copyin(c,nc.tobytes()) -def metalrun(): - prog(a, b, c, global_size=GLOBAL_SIZE, local_size=LOCAL_SIZE, wait=True) - return a -def timeit(fxn): - st = time.perf_counter() - et = fxn() - # NOTE: et doesn't contain the launch overhead - return time.perf_counter() - st -tm = min([timeit(metalrun) for _ in range(200)]) -print(f"{N:d}x{M:d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matvec in metal") -metal_a = np.zeros(M, dtype=np.float32) -metalalloc._copyout(flat_mv(metal_a.data), a) -np.testing.assert_allclose(metal_a, torch_a, atol=5e-3) - -b = Tensor(nb) -c = Tensor(nc) -# TODO: slowness without the JIT I suspect comes from a lack of a caching allocator -@TinyJit -def tiny_jit(b, c): - return (b@c).realize() -def tiny_prog(b, c): - st = time.perf_counter() - a = tiny_jit(b, c) - Device["METAL"].synchronize() - return time.perf_counter() - st -tm = min([tiny_prog(b, c) for _ in range(200)]) -print(f"{N:d}x{M:d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS matvec in tinygrad") -tiny_a = tiny_jit(b, c).numpy() -np.testing.assert_allclose(tiny_a, torch_a, atol=5e-3) \ No newline at end of file diff --git a/tinygrad/extra/gemm/mlx_matmul.py b/tinygrad/extra/gemm/mlx_matmul.py deleted file mode 100644 index 821c7fff..00000000 --- a/tinygrad/extra/gemm/mlx_matmul.py +++ /dev/null @@ -1,10 +0,0 @@ -import mlx.core as mx -from tinygrad.helpers import Timing -N = 4096 -x = mx.random.normal((N,N)) -w = mx.random.normal((N,N)) - -FLOPS = N*N*N*2 -for i in range(10): - with Timing("", lambda x: f" {FLOPS/x:.2f} GFLOPS"): - mx.eval(x@w) diff --git a/tinygrad/extra/gemm/real_pmatmul.py b/tinygrad/extra/gemm/real_pmatmul.py deleted file mode 100644 index b4b02028..00000000 --- a/tinygrad/extra/gemm/real_pmatmul.py +++ /dev/null @@ -1,20 +0,0 @@ -import time -from tinygrad import Tensor, Device, TinyJit -from tinygrad.helpers import getenv - -if __name__ == "__main__": - DEVS = [f"NV:{i}" for i in range(getenv("GPUS", 2))] - N = getenv("N", 8192) - A = Tensor.rand(N, N).shard(DEVS, 0).realize() - B = Tensor.rand(N, N).shard(DEVS, 1).realize() - print("***** MUL *****") - jmatmul = TinyJit(Tensor.dot) - for i in range(10): - Device["NV:0"].synchronize() - Device["NV:1"].synchronize() - st = time.perf_counter() - jmatmul(A, B) - Device["NV:0"].synchronize() - Device["NV:1"].synchronize() - et = time.perf_counter() - print(f"{(N*N*N*2*1e-12)/(et-st):.2f} TFLOPS") diff --git a/tinygrad/extra/gemm/simple_conv.py b/tinygrad/extra/gemm/simple_conv.py deleted file mode 100644 index ea682a0b..00000000 --- a/tinygrad/extra/gemm/simple_conv.py +++ /dev/null @@ -1,33 +0,0 @@ -from tinygrad.helpers import getenv -from tinygrad import dtypes, Tensor - -dtype_in = dtypes.half if getenv("HALF") else dtypes.bfloat16 if getenv("BFLOAT16") else dtypes.float -acc_dtype = dtypes.half if getenv("ACC_HALF") else dtypes.bfloat16 if getenv("ACC_BFLOAT16") else None - -CNT = getenv("CNT", 8) -BS = getenv("BS", 16) -CIN = getenv("CIN", 128) -COUT = getenv("COUT", 128) -HW = getenv("HW", 128) -K = getenv("K", 3) -PADDING = getenv("PADDING", 1) -COMP = getenv("COMP", 0) -ATOL = getenv("ATOL", 1e-4) -RTOL = getenv("RTOL", 3e-2) - -FLOPS = BS*K*K*CIN*HW*HW*COUT*2 -def rand_input(): return Tensor.rand(BS, CIN, HW, HW, dtype=dtype_in).realize(), Tensor.rand(COUT, CIN, K, K, dtype=dtype_in).realize() - -if __name__ == "__main__": - a, b = rand_input() - for i in range(CNT): - if i > 0 and getenv("RAND", 0) != 0: - a, b = rand_input() - c = a.conv2d(b, padding=PADDING, dtype=acc_dtype).realize() - - if COMP: - import numpy as np, time, torch - torch_device = "cuda:0" if torch.cuda.is_available() else ("mps" if getenv("MPS", 0) else "cpu") - ta, tb = torch.from_numpy(a.numpy()).to(torch_device), torch.from_numpy(b.numpy()).to(torch_device) - tc = torch.nn.functional.conv2d(ta, tb, padding=PADDING) - np.testing.assert_allclose(c.numpy(), tc.cpu(), atol=ATOL, rtol=RTOL) diff --git a/tinygrad/extra/gemm/simple_matmul.py b/tinygrad/extra/gemm/simple_matmul.py deleted file mode 100644 index 29f26d7e..00000000 --- a/tinygrad/extra/gemm/simple_matmul.py +++ /dev/null @@ -1,53 +0,0 @@ -import numpy as np -from tinygrad import dtypes, Tensor -from tinygrad.helpers import getenv, get_single_element -from tinygrad.dtype import _to_np_dtype -from tinygrad.codegen.kernel import OptOps -from tinygrad.engine.realize import lower_schedule - -dtype_in = dtypes.half if getenv("HALF") else dtypes.bfloat16 if getenv("BFLOAT16") else dtypes.float -acc_dtype = dtypes.half if getenv("ACC_HALF") else dtypes.bfloat16 if getenv("ACC_BFLOAT16") else None -if getenv("INT"): dtype_in, acc_dtype = dtypes.int8, dtypes.int32 -if getenv("UINT"): dtype_in, acc_dtype = dtypes.uint8, dtypes.int32 - -N = getenv("N", 4096) -M = getenv("M", N) -K = getenv("K", N) -CNT = getenv("CNT", 10) -ATOL = getenv("ATOL", 1e-4) -RTOL = getenv("RTOL", 3e-2) -INT_LOW = getenv("INT_LOW", 0) -INT_HIGH = getenv("INT_HIGH", 10) - -if __name__ == "__main__": - def init_matrix(rows, cols): - rng = np.random.default_rng() - # NOTE: numpy does not support bfloat16 - if (np_dtype := _to_np_dtype(dtype_in)) is None: np_dtype = np.float32 - if dtype_in in dtypes.ints: - return Tensor(rng.integers(INT_LOW, INT_HIGH, (rows, cols), dtype=np_dtype)).realize() - return Tensor(rng.random((rows, cols), dtype=np.float32).astype(np_dtype)-0.5).cast(dtype_in).realize() - - a, b = init_matrix(M, K), init_matrix(K, N) - for i in range(CNT): - if i > 0 and getenv("RAND", 0) != 0: - a, b = init_matrix(M, K), init_matrix(K, N) - c = a.matmul(b, dtype=acc_dtype).realize() - - if getenv("SHOULD_USE_TC"): - sched = a.matmul(b, dtype=acc_dtype).schedule() - lowered = list(lower_schedule(sched)) - ei = get_single_element(lowered)[1] - assert any(opt.op is OptOps.TC for opt in ei.prg.p.applied_opts), f"TC not triggered, {ei.prg.p.applied_opts}" - - ref = a.numpy().astype(np.float32) @ b.numpy().astype(np.float32) - res = c.numpy() - try: - np.testing.assert_allclose(res, ref, rtol=RTOL, atol=ATOL) - except AssertionError as e: - if getenv("DEBUG_VALUES", 0) > 0: - mismatch = np.where(~np.isclose(res, ref, rtol=RTOL, atol=ATOL)) - print("Mismatch indices:", mismatch) - print("Result :", res[mismatch]) - print("Ground truth :", ref[mismatch]) - raise e diff --git a/tinygrad/extra/gemm/simple_matvec.py b/tinygrad/extra/gemm/simple_matvec.py deleted file mode 100644 index 00966ba1..00000000 --- a/tinygrad/extra/gemm/simple_matvec.py +++ /dev/null @@ -1,30 +0,0 @@ -import numpy as np -from tinygrad.helpers import getenv -from tinygrad import dtypes, Tensor, Device -dtype_in = dtypes.half if getenv("HALF") else dtypes.bfloat16 if getenv("BFLOAT16") else dtypes.float -acc_dtype = dtypes.half if getenv("ACC_HALF") else dtypes.bfloat16 if getenv("ACC_BFLOAT16") else None - -GPUS = getenv("GPUS", 0) -M = getenv("M", 16384) -N = getenv("N", 4096) -CNT = getenv("CNT", 10) -ATOL = getenv("ATOL", 1e-4) -RTOL = getenv("RTOL", 3e-2) - -def _rand(device): - a, b = Tensor.rand(M, N, dtype=dtype_in).realize(), Tensor.rand(N, dtype=dtype_in).realize() - if isinstance(device, tuple): - a.shard_(device, axis=1) - b.shard_(device, axis=0) - return a, b - -if __name__ == "__main__": - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(GPUS)) if GPUS > 1 else Device.DEFAULT - a, b = _rand(device) - for i in range(CNT): - if i > 0 and getenv("RAND", 0) != 0: - a, b = _rand(device) - c = a.matmul(b, dtype=acc_dtype).realize() - nc = c.numpy() - comp = a.numpy().astype(np.float32) @ b.numpy().astype(np.float32) - np.testing.assert_allclose(nc, comp, atol=ATOL, rtol=RTOL) diff --git a/tinygrad/extra/gemm/tf_gemm.py b/tinygrad/extra/gemm/tf_gemm.py deleted file mode 100644 index 802b3443..00000000 --- a/tinygrad/extra/gemm/tf_gemm.py +++ /dev/null @@ -1,33 +0,0 @@ -import time -import tensorflow as tf - -gpus = tf.config.list_physical_devices('GPU') -if gpus: - try: - # Currently, memory growth needs to be the same across GPUs - for gpu in gpus: - tf.config.experimental.set_memory_growth(gpu, True) - logical_gpus = tf.config.list_logical_devices('GPU') - print(len(gpus), "Physical GPUs,", len(logical_gpus), "Logical GPUs") - except RuntimeError as e: - # Memory growth must be set before GPUs have been initialized - print(e) - -for dtype in [tf.float16, tf.float32]: - for N in [256, 512, 1024, 2048, 4096, 8192]: - FLOPS = N*N*N*2 - - b = tf.random.uniform((N, N), dtype=dtype) - c = tf.random.uniform((N, N), dtype=dtype) - - b = tf.Variable(b) - c = tf.Variable(c) - - def tf_prog(b, c): - st = time.perf_counter() - a = tf.matmul(b, c) - tf.debugging.check_numerics(a, "Nan or Inf in result") # Ensures that the calculation is done. - return time.perf_counter() - st - - tm = min([tf_prog(b, c) for _ in range(20)]) - print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS {N:4d}x{N:4d}x{N:4d} matmul in {dtype}") \ No newline at end of file diff --git a/tinygrad/extra/gemm/tinygrad_nv_matmul.py b/tinygrad/extra/gemm/tinygrad_nv_matmul.py deleted file mode 100644 index ab8f078a..00000000 --- a/tinygrad/extra/gemm/tinygrad_nv_matmul.py +++ /dev/null @@ -1,37 +0,0 @@ -from tinygrad import Tensor, dtypes, Device -from tinygrad.helpers import getenv, DEBUG -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad.engine.realize import CompiledRunner, ExecItem -from dataclasses import replace - -N = 4096 -if __name__ == "__main__": - if getenv("GEMV"): - A, B = Tensor.empty(1, N, dtype=dtypes.float), Tensor.empty(14336, N, dtype=dtypes.float16).T - else: - A, B = Tensor.empty(N, N, dtype=dtypes.float16), Tensor.empty(N, N, dtype=dtypes.float16) - C = A.matmul(B) - si = C.schedule()[-1] - ast = si.ast - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - if getenv("GEMV"): - opts = [ - Opt(op=OptOps.UNROLL, axis=0, amt=8), - Opt(op=OptOps.GROUP, axis=0, amt=32), - ] - else: - opts = [ - Opt(op=OptOps.TC, axis=0, amt=0), - Opt(op=OptOps.UPCAST, axis=0, amt=4), - Opt(op=OptOps.UPCAST, axis=1, amt=8), - Opt(op=OptOps.LOCAL, axis=0, amt=2), - Opt(op=OptOps.LOCAL, axis=1, amt=2), - Opt(op=OptOps.LOCAL, axis=0, amt=2), - ] - k.apply_opts(opts) - prg = k.to_program() - new_src = prg.src - # can mod source here - prg = replace(prg, src=new_src) - ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) - for i in range(5): ei.run(wait=True) diff --git a/tinygrad/extra/gemm/torch_gemm.py b/tinygrad/extra/gemm/torch_gemm.py deleted file mode 100644 index 6dde8719..00000000 --- a/tinygrad/extra/gemm/torch_gemm.py +++ /dev/null @@ -1,26 +0,0 @@ -import os -os.environ["NVIDIA_TF32_OVERRIDE"] = "0" -os.environ["MKL_NUM_THREADS"] = "1" -os.environ["NUMEXPR_NUM_THREADS"] = "1" -os.environ["OMP_NUM_THREADS"] = "1" -import time -import torch -torch.set_num_threads(1) -from tinygrad.helpers import getenv -CUDA = getenv("CUDA", 1) - -for dtype in [torch.float32, torch.float16]: - for N in [256, 512, 1024, 2048, 4096]: - FLOPS = N*N*N*2 - - b = torch.rand((N,N), dtype=dtype) - c = torch.rand((N,N), dtype=dtype) - if CUDA: b,c = b.cuda(),c.cuda() - - def torch_prog(b, c): - st = time.perf_counter() - a = b@c - if CUDA: torch.cuda.synchronize() - return time.perf_counter() - st - tm = min([torch_prog(b, c) for _ in range(20)]) - print(f"{N*N:10d} {tm*1e6:9.2f} us, would be {FLOPS*1e-9/tm:9.2f} GFLOPS {N:4d}x{N:4d}x{N:4d} matmul in {dtype}") diff --git a/tinygrad/extra/gemm/triton_nv_matmul.py b/tinygrad/extra/gemm/triton_nv_matmul.py deleted file mode 100644 index 5f04a340..00000000 --- a/tinygrad/extra/gemm/triton_nv_matmul.py +++ /dev/null @@ -1,107 +0,0 @@ -import time -import triton -import triton.language as tl -from triton.compiler import AttrsDescriptor, ASTSource, compile as triton_compile -import numpy as np -from tinygrad import Tensor, dtypes, Device -from tinygrad.engine.realize import CompiledRunner, ExecItem, ProgramSpec -from tinygrad.helpers import getenv -np.set_printoptions(suppress=True) - -@triton.jit -def matmul_kernel(c_ptr, a_ptr, b_ptr, BLOCK_SIZE_M: tl.constexpr, BLOCK_SIZE_N: tl.constexpr, BLOCK_SIZE_K: tl.constexpr): - pid_m = tl.program_id(axis=0) - pid_n = tl.program_id(axis=1) - - M, N, K = 4096, 4096, 4096 - stride_am = 4096 - stride_ak = 1 - stride_bk = 4096 - stride_bn = 1 - stride_cm = 4096 - stride_cn = 1 - - offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M - offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N - offs_k = tl.arange(0, BLOCK_SIZE_K) - - a_ptrs = a_ptr + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak) - b_ptrs = b_ptr + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn) - - accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32) - for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)): - a = tl.load(a_ptrs) - b = tl.load(b_ptrs) - - accumulator = tl.dot(a, b, accumulator) - a_ptrs += BLOCK_SIZE_K * stride_ak - b_ptrs += BLOCK_SIZE_K * stride_bk - - c = tl.cast(accumulator, tl.float16) - offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M) - offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N) - c_ptrs = c_ptr + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :] - tl.store(c_ptrs, c) - -# CUDA=1 PTX=1 python3 extra/gemm/triton_nv_matmul.py -if __name__ == "__main__": - BLOCK_SIZE_M, BLOCK_SIZE_N, BLOCK_SIZE_K = 64, 128, 64 - M, N, K = 4096, 4096, 4096 - - # **** torch test **** - - if getenv("TORCH"): - import torch - c = torch.empty((M, N), device='cuda:0', dtype=torch.float16) - a = torch.empty((M, K), device='cuda:0', dtype=torch.float16) - b = torch.empty((K, N), device='cuda:0', dtype=torch.float16) - - for i in range(5): - st = time.perf_counter() - matmul_kernel[triton.cdiv(M, BLOCK_SIZE_M), triton.cdiv(N, BLOCK_SIZE_N)]( - c, a, b, BLOCK_SIZE_M, BLOCK_SIZE_N, BLOCK_SIZE_K) - torch.cuda.synchronize() - et = time.perf_counter() - st - print(f"TFLOPS {2*M*N*K*1e-12/et:.2f}") - - # **** tinygrad test **** - - compiled = triton_compile(ASTSource(matmul_kernel, "*fp16,*fp16,*fp16", - attrs=AttrsDescriptor(divisible_by_16=(0, 1, 2, 3, 4, 5), equal_to_1=()), - constants={"BLOCK_SIZE_M": BLOCK_SIZE_M, "BLOCK_SIZE_N": BLOCK_SIZE_N, "BLOCK_SIZE_K": BLOCK_SIZE_K})) - print(compiled.metadata) - - A, B = Tensor.normal(M, K, std=1e-1, dtype=dtypes.float16).realize(), Tensor.normal(K, N, std=1e-1, dtype=dtypes.float16).realize() - C = A.matmul(B) - sched = C.schedule() - si = sched[-1] - - src = compiled.asm["ptx"] - # specify the shared memory here so we don't need to do it dynamically - src = src.replace(".extern .shared .align 16 .b8 global_smem[];", f".shared .align 16 .b8 global_smem[{compiled.metadata.shared}];") - # useless comment spam - src = src.replace("\t// begin inline asm\n", "") - src = src.replace("\t// end inline asm\n", "") - # remove debug sections - src = src.split("\t.file")[0] - assert '.extern .shared' not in src - prg = ProgramSpec("matmul_kernel", src, device=Device.DEFAULT, - global_size=[M//BLOCK_SIZE_M, N//BLOCK_SIZE_N, 1], local_size=[32*compiled.metadata.num_warps, 1, 1], - mem_estimate=A.nbytes() + B.nbytes() + C.nbytes()) - ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) - tflops = [] - for i in range(5): - tm = ei.run(wait=True) - tflops.append((2*M*K*N/tm)*1e-12) - print(f"TFLOPS: {max(tflops):.2f}") - - # check correctness - if getenv("VERIFY"): - from tinygrad.engine.realize import run_schedule - triton_buf = np.frombuffer(si.bufs[0].as_buffer(), np.float16).reshape(M,N) - print(triton_buf) - run_schedule(sched) - tinygrad_buf = np.frombuffer(si.bufs[0].as_buffer(), np.float16).reshape(M,N) - print(tinygrad_buf) - np.testing.assert_allclose(triton_buf, tinygrad_buf) - print("correct!") diff --git a/tinygrad/extra/gemm/tvm_gemm.py b/tinygrad/extra/gemm/tvm_gemm.py deleted file mode 100644 index fa6f6615..00000000 --- a/tinygrad/extra/gemm/tvm_gemm.py +++ /dev/null @@ -1,46 +0,0 @@ -# https://tvm.apache.org/docs/tutorial/tensor_expr_get_started.html#example-2-manually-optimizing-matrix-multiplication-with-te - -M, N, K = 1024, 1024, 1024 - -try: - import tvm - from tvm import te - #print(tvm.target.Target.list_kinds()) - - # c, opencl - target = tvm.target.Target(target="c") - - # TVM Matrix Multiplication using TE - k = te.reduce_axis((0, K), "k") - A = te.placeholder((M, K), name="A") - B = te.placeholder((K, N), name="B") - C = te.compute((M, N), lambda x, y: te.sum(A[x, k] * B[k, y], axis=k), name="C") - - # Default schedule - s = te.create_schedule(C.op) - #print(tvm.lower(s, [A, B, C], simple_mode=True)) - - # Output C code - func = tvm.build(s, [A, B, C], target=target, name="mmult") - print(func.get_source()) -except ImportError: - print("** please install TVM for TVM output") - -# tinygrad version - -import os -from tinygrad.tensor import Tensor - -# define the compute -A = Tensor.rand(M, K, device="CPU") -B = Tensor.rand(K, N, device="CPU") -C = (A.reshape(M, 1, K) * B.permute(1,0).reshape(1, N, K)).sum(axis=2) - -sched = C.schedule() -from tinygrad.codegen.kernel import Kernel -from tinygrad.device import CompilerOptions -lin = Kernel(sched[-1].ast, CompilerOptions(has_local=False, supports_float4=False)) -lin.linearize() -from tinygrad.runtime.ops_cpu import renderer -src = renderer("mmult", lin.uops) -print(src) diff --git a/tinygrad/extra/gradcheck.py b/tinygrad/extra/gradcheck.py deleted file mode 100644 index a94befac..00000000 --- a/tinygrad/extra/gradcheck.py +++ /dev/null @@ -1,51 +0,0 @@ -import numpy as np -from tinygrad.tensor import Tensor, _to_np_dtype - -def mask_like(like, mask_inx, mask_value = 1.0): - mask = np.zeros(like.shape, dtype=_to_np_dtype(like.dtype)).reshape(-1) - mask[mask_inx] = mask_value - return mask.reshape(like.shape) - -def jacobian(func, input): - output = func(input) - - ji = input.numpy().reshape(-1).shape[-1] - jo = output.numpy().reshape(-1).shape[-1] - J = np.zeros((jo,ji), dtype=np.float32) - - for o in range(jo): - input.grad = None - output = func(input) - - # tinygrad doesn't support slicing, tiny-hack to select - # the needed scalar an backpropagate only through it - o_scalar = Tensor(mask_like(output, o, 1.)).mul(output).sum() - o_scalar = Tensor(mask_like(output, o, 1.)).mul(output).sum() - o_scalar.backward() - - for i, grad in enumerate(input.grad.numpy().reshape(-1)): - J[o,i] = grad - return J - -def numerical_jacobian(func, input, eps = 1e-3): - output = func(input) - - ji = input.numpy().reshape(-1).shape[-1] - jo = output.numpy().reshape(-1).shape[-1] - NJ = np.zeros((jo, ji), dtype=np.float32) - - for i in range(ji): - eps_perturb = mask_like(input, i, mask_value = eps) - - output_perturb_add = func(Tensor(input.numpy() + eps_perturb)).numpy().reshape(-1) - output_perturb_sub = func(Tensor(input.numpy() - eps_perturb)).numpy().reshape(-1) - - grad_approx = ((output_perturb_add) - (output_perturb_sub)) / (2*eps) - - NJ[:,i] = grad_approx - return NJ - -def gradcheck(func, input, eps = 1e-3, atol = 1e-3, rtol = 1e-3): - NJ = numerical_jacobian(func, input, eps) - J = jacobian(func, input) - return np.allclose(J, NJ, atol = atol, rtol = rtol) diff --git a/tinygrad/extra/hcqfuzz/.gitignore b/tinygrad/extra/hcqfuzz/.gitignore deleted file mode 100644 index 566be7a8..00000000 --- a/tinygrad/extra/hcqfuzz/.gitignore +++ /dev/null @@ -1 +0,0 @@ -reports \ No newline at end of file diff --git a/tinygrad/extra/hcqfuzz/fuzzer.py b/tinygrad/extra/hcqfuzz/fuzzer.py deleted file mode 100644 index bea12c2f..00000000 --- a/tinygrad/extra/hcqfuzz/fuzzer.py +++ /dev/null @@ -1,72 +0,0 @@ -import os, random, subprocess, shlex, datetime, time, signal -from extra.hcqfuzz.tools import create_report, on_start_run, collect_tests, init_log, log -from extra.hcqfuzz.spec import AMSpec - -def run_test(dev, test): - on_start_run(dev, test) - - dev_env = dev.get_exec_state() - test_env, cmd, timeout = test.get_exec_state() - env = {**dev_env, **test_env} - - if isinstance(cmd, str): cmd = shlex.split(cmd) - assert isinstance(cmd, list), "cmd must be list or str" - - if env is None: env = os.environ.copy() - else: - env = {k: str(v) for k, v in env.items()} - env = {**os.environ, **env} - - start_ts = datetime.datetime.now() - t0 = time.perf_counter() - log(f"[{start_ts:%Y-%m-%d %H:%M:%S}] running: {test.name()}: {' '.join(cmd)}", end="", flush=True) - - proc = subprocess.Popen(cmd, env=env, stdout=subprocess.PIPE, stderr=subprocess.PIPE, text=True) - try: - stdout, stderr = proc.communicate(timeout=timeout) - ret = proc.returncode - except KeyboardInterrupt: - print("\nExiting...", flush=True) - proc.send_signal(signal.SIGINT) - try: stdout, stderr = proc.communicate(timeout=5) - except subprocess.TimeoutExpired: - proc.kill() - stdout, stderr = proc.communicate() - raise - except subprocess.TimeoutExpired: - cur_time = datetime.datetime.now() - log(f"\r[{cur_time:%Y-%m-%d %H:%M:%S}] {test.name()} send SIGKILL", end="", flush=True) - - proc.kill() - stdout, stderr = proc.communicate() - ret = -9 - - finish_time = datetime.datetime.now() - elapsed = time.perf_counter() - t0 - if ret != 0: - log(f"\r[{finish_time:%Y-%m-%d %H:%M:%S}] {test.name()} failed with {ret} after {elapsed:.1f}s", flush=True) - create_report(dev, test, ret, stdout, stderr) - else: - log(f"\r[{finish_time:%Y-%m-%d %H:%M:%S}] {test.name()} exited {ret} after {elapsed:.1f}s", flush=True) - -if __name__ == "__main__": - init_log() - device_name = "AM" - dev = AMSpec() - - start_seed = os.environ.get("SEED", 3332) - random.seed(start_seed) - - log(f"Starting with seed {start_seed}") - - test_set = collect_tests() - log(f"Found {len(test_set)} tests:") - for test in test_set: log(f" - {test.name()}") - - while True: - seed = random.randint(0, 2**31) - test = random.choice(test_set) - - dev.prepare(seed) - test.prepare(dev, seed) - run_test(dev, test) diff --git a/tinygrad/extra/hcqfuzz/readme b/tinygrad/extra/hcqfuzz/readme deleted file mode 100644 index d3176f45..00000000 --- a/tinygrad/extra/hcqfuzz/readme +++ /dev/null @@ -1,12 +0,0 @@ -# Fuzzing Infra - -To add a new test, define a `TestSpec`-based class in a file in the `tests/` folder. - -You can choose which tests to load from which file: -```bash -RUN_FILES="hcq,allocator" python3 extra/hcqfuzz/fuzzer.py -``` -Or skip tests from any file: -```bash -SKIP_FILES="allocator" python3 extra/hcqfuzz/fuzzer.py -``` diff --git a/tinygrad/extra/hcqfuzz/spec.py b/tinygrad/extra/hcqfuzz/spec.py deleted file mode 100644 index c8202174..00000000 --- a/tinygrad/extra/hcqfuzz/spec.py +++ /dev/null @@ -1,42 +0,0 @@ -import os, random - -class TestSpec: - def prepare(self, device, seed): - raise NotImplementedError("prepare must be implemented in the derived class") - def get_exec_state(self): - raise NotImplementedError("get_exec_state must be implemented in the derived class") - def name(self): return self.__class__.__name__ - -class DeviceSpec: - def prepare(self, seed): - raise NotImplementedError("prepare must be implemented in the derived class") - def get_exec_state(self): - raise NotImplementedError("get_exec_state must be implemented in the derived class") - def name(self): return self.__class__.__name__ - -class HCQSpec(DeviceSpec): pass -class AMDSpec(HCQSpec): - def __init__(self): - assert os.path.exists('/sys/module/amdgpu'), "amdgpu module should be loaded" - - def prepare(self, seed): - self.env = { - "AMD": 1, - "AMD_LLVM": 0 - } - - def get_exec_state(self): return self.env - -class AMSpec(AMDSpec): - def __init__(self): - assert not os.path.exists('/sys/module/amdgpu'), "amdgpu module should not be loaded" - - def prepare(self, seed): - super().prepare(seed) - - self.env = { - **self.env, # from AMDSpec - "AMD_SDMA_BIND": random.randint(0, 1), - "AMD_ALLOC_QUEUE_DEV_MEM": 0, # random.randint(0, 1) need to validate - "AMD_QUEUE_SIZE": 1 << random.randint(10, 26), - } diff --git a/tinygrad/extra/hcqfuzz/tests/allocator.py b/tinygrad/extra/hcqfuzz/tests/allocator.py deleted file mode 100644 index dd170649..00000000 --- a/tinygrad/extra/hcqfuzz/tests/allocator.py +++ /dev/null @@ -1,16 +0,0 @@ -from extra.hcqfuzz.spec import TestSpec -import random - -class TLSFAllocator(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - "SEED": seed, - "ITERS": random.randint(10000, 1000000), - } - - self.cmd = "python3 test/external/external_fuzz_tlsf.py" - self.timeout = 60 * 60 # 60 minutes - - def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad/extra/hcqfuzz/tests/allreduce.py b/tinygrad/extra/hcqfuzz/tests/allreduce.py deleted file mode 100644 index b741d82a..00000000 --- a/tinygrad/extra/hcqfuzz/tests/allreduce.py +++ /dev/null @@ -1,17 +0,0 @@ -from extra.hcqfuzz.spec import TestSpec -import random - -class RingAllreduce(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - "GPUS": random.choice([2, 3, 4, 5, 6]), - "ITERS": random.randint(10, 1000), - "DEBUG": 2, - } - - self.cmd = "python3 test/external/external_benchmark_multitensor_allreduce.py" - self.timeout = 10 * 60 # 10 minutes - - def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad/extra/hcqfuzz/tests/bert.py b/tinygrad/extra/hcqfuzz/tests/bert.py deleted file mode 100644 index 331d908c..00000000 --- a/tinygrad/extra/hcqfuzz/tests/bert.py +++ /dev/null @@ -1,83 +0,0 @@ -from extra.hcqfuzz.spec import TestSpec -import random - -bert_train_params = { - "DEFAULT_FLOAT": "HALF", - "SUM_DTYPE": "HALF", - "GPUS": 6, - "BS": 96, - "EVAL_BS": 96, - "FUSE_ARANGE": 1, - "FUSE_ARANGE_UINT": 0, - "BASEDIR": "/raid/datasets/wiki", -} - -class TrainBert(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **bert_train_params, - "IGNORE_BEAM_CACHE": 1, - "BEAM": 5, - "BEAM_UOPS_MAX": 10000, - "BEAM_UPCAST_MAX": 256, - "BEAM_LOCAL_MAX": 1024, - "BEAM_MIN_PROGRESS": 5, - "IGNORE_JIT_FIRST_BEAM": 1, - "LOGMLPERF": 0, - "SEED": seed, - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 7 * 60 * 60 # 7 hours - - def get_exec_state(self): return self.env, self.cmd, self.timeout - -class TrainBertShort(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **bert_train_params, - "IGNORE_BEAM_CACHE": 1, - "BEAM": 5, - "BEAM_UOPS_MAX": 10000, - "BEAM_UPCAST_MAX": 256, - "BEAM_LOCAL_MAX": 1024, - "BEAM_MIN_PROGRESS": 5, - "IGNORE_JIT_FIRST_BEAM": 1, - "SEED": seed, - "BENCHMARK": 4096, - "JIT": 2 - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 2 * 60 * 60 # 2 hours - - def get_exec_state(self): return self.env, self.cmd, self.timeout - -class BertBeam(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **bert_train_params, - "IGNORE_BEAM_CACHE": 1, - "BEAM": random.choice([1, 2, 3, 4, 5]), - "BEAM_UOPS_MAX": 10000, - "BEAM_UPCAST_MAX": 256, - "BEAM_LOCAL_MAX": 1024, - "BEAM_MIN_PROGRESS": 5, - "IGNORE_JIT_FIRST_BEAM": 1, - "SEED": seed, - "RESET_STEP": 1, - "BENCHMARK": 10, - "BERT_LAYERS": 2, - "SEED": seed, - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 1 * 60 * 60 # 1 hour - - def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad/extra/hcqfuzz/tests/hcq.py b/tinygrad/extra/hcqfuzz/tests/hcq.py deleted file mode 100644 index 77eaef66..00000000 --- a/tinygrad/extra/hcqfuzz/tests/hcq.py +++ /dev/null @@ -1,35 +0,0 @@ -from extra.hcqfuzz.spec import TestSpec -import random - -class HCQSignalFuzzer(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - "GPUS": random.choice([2, 3, 4, 5, 6]), - "ITERS": random.randint(1000000, 10000000), - "SEED": seed, - } - - self.cmd = "python3 test/external/external_fuzz_hcq_signals.py" - self.timeout = 30 * 60 # 30 minutes - - def get_exec_state(self): return self.env, self.cmd, self.timeout - -class HCQGraphFuzzer(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - "FUZZ_GRAPH_SPLIT_RUNS": random.randint(48, 64), - "FUZZ_GRAPH_MAX_SPLITS": random.randint(4, 16), - "FUZZ_GRAPH_SPLIT_RETRY_RUNS": random.randint(4, 8), - "MAX_KERNELS": random.randint(32, 512), - "MAX_DEVICES": random.choice([2, 3, 4, 5, 6]), - "ITERS": random.randint(100, 1000), - } - - self.cmd = "python3 test/external/fuzz_graph.py" - self.timeout = 60 * 60 # 60 minutes - - def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad/extra/hcqfuzz/tests/resnet.py b/tinygrad/extra/hcqfuzz/tests/resnet.py deleted file mode 100644 index 0009219d..00000000 --- a/tinygrad/extra/hcqfuzz/tests/resnet.py +++ /dev/null @@ -1,66 +0,0 @@ -from extra.hcqfuzz.spec import TestSpec -import random - -resnet_train_params = { - "DEFAULT_FLOAT": "HALF", - "SUM_DTYPE": "HALF", - "GPUS": 6, - "BS": 1536, - "EVAL_BS": 192, - "TRAIN_BEAM": 4, - "IGNORE_JIT_FIRST_BEAM": 1, - "BEAM_UOPS_MAX": 2000, - "BEAM_UPCAST_MAX": 96, - "BEAM_LOCAL_MAX": 1024, - "BEAM_MIN_PROGRESS": 5, - "BEAM_PADTO": 0, - "EVAL_START_EPOCH": 3, - "EVAL_FREQ": 4 -} - -class TrainResnet(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **resnet_train_params, - "IGNORE_BEAM_CACHE": 1, - "SEED": seed, - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 4 * 60 * 60 # 7 hours - - def get_exec_state(self): return self.env, self.cmd, self.timeout - -class TrainResnetShort(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **resnet_train_params, - "SEED": seed, - "BENCHMARK": 4096, - "JIT": 2, - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 2 * 60 * 60 # 2 hours - - def get_exec_state(self): return self.env, self.cmd, self.timeout - -class ResnetBeam(TestSpec): - def prepare(self, dev, seed): - random.seed(seed) - - self.env = { - **resnet_train_params, - "IGNORE_BEAM_CACHE": 1, - "BENCHMARK": 10, - "SEED": seed, - } - - self.cmd = "python3 examples/mlperf/model_train.py" - self.timeout = 1 * 60 * 60 # 1 hour - - def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad/extra/hcqfuzz/tools.py b/tinygrad/extra/hcqfuzz/tools.py deleted file mode 100644 index 2f585281..00000000 --- a/tinygrad/extra/hcqfuzz/tools.py +++ /dev/null @@ -1,76 +0,0 @@ -import pickle, datetime, os, tempfile, subprocess, zipfile, importlib.util -from extra.hcqfuzz.spec import TestSpec -from tinygrad.helpers import getenv - -BASE_DIR = os.path.dirname(os.path.abspath(__file__)) -TEST_DIR = os.path.join(BASE_DIR, "tests") -REPORTS_DIR = os.path.join(BASE_DIR, "reports") - -def collect_tests(): - run_files = getenv("RUN_FILES", "").split(",") - skip_tests = getenv("SKIP_FILES", "").split(",") - - tests = [] - for filename in os.listdir(TEST_DIR): - if filename.endswith(".py") and not filename.startswith("__"): - if run_files and filename[:-3] not in run_files: continue - if skip_tests and filename[:-3] in skip_tests: continue - - filepath = os.path.join(TEST_DIR, filename) - module_name = f"tests.{filename[:-3]}" - module = importlib.import_module(module_name) - for attr_name in dir(module): - attr = getattr(module, attr_name) - if isinstance(attr, type) and issubclass(attr, TestSpec) and attr is not TestSpec: - tests.append(attr()) - return tests - -def on_start_run(dev, test): - os.makedirs(REPORTS_DIR, exist_ok=True) - pickle.dump((dev, test), open(f"{REPORTS_DIR}/last_launch.pkl", "wb")) - -def create_report(dev, test, result, stdout, stderr): - os.makedirs(REPORTS_DIR, exist_ok=True) - - timestamp = datetime.datetime.now().strftime("%Y%m%d_%H%M%S") - report_name = f"{timestamp}_{test.name()}_report" - report_path = os.path.join(REPORTS_DIR, report_name) - - os.makedirs(report_path, exist_ok=False) - - pickle_path = os.path.join(report_path, "repro.pkl") - with open(pickle_path, "wb") as f: pickle.dump((dev, test), f) - - stdout_path = os.path.join(report_path, "stdout.txt") - with open(stdout_path, "w") as f: f.write(stdout) - - stderr_path = os.path.join(report_path, "stderr.txt") - with open(stderr_path, "w") as f: f.write(stderr) - - dmesg_path = os.path.join(report_path, "dmesg.txt") - dmesg_output = subprocess.check_output(["sudo", "dmesg", "--ctime", "--color=never"], text=True) - with open(dmesg_path, "w") as f: f.write(dmesg_output) - - summary_path = os.path.join(report_path, "summary.txt") - with open(summary_path, "w") as f: - f.write(f"Test: {test.name()}\n") - f.write(f"Dev params: {vars(dev)}\n") - f.write(f"Test params: {vars(test)}\n") - f.write(f"Exit Code: {result}\n") - - print(f"Crash report saved to {report_path}") - -_log_file = None -def init_log(): - global _log_file - os.makedirs(REPORTS_DIR, exist_ok=True) - - ts = datetime.datetime.now().strftime("%Y%m%d_%H%M%S") - name = f"log_{ts}.log" - _log_file = open(f"{REPORTS_DIR}/{name}", "a", buffering=1) - -def log(msg="", end="\n", flush=False): - global _log_file - _log_file.write(msg.replace("\r", "\n") + end) - if flush: _log_file.flush() - print(msg + " " * 60, end=end, flush=flush) diff --git a/tinygrad/extra/hip_events.py b/tinygrad/extra/hip_events.py deleted file mode 100644 index 5719a18c..00000000 --- a/tinygrad/extra/hip_events.py +++ /dev/null @@ -1,12 +0,0 @@ -import ctypes -import tinygrad.runtime.autogen.hip as hip -from tinygrad.runtime.ops_hip import check -from tinygrad.helpers import init_c_var - -if __name__ == "__main__": - check(hip.hipSetDevice(0)) - evt = init_c_var(hip.hipEvent_t(), lambda x: check(hip.hipEventCreate(ctypes.byref(x)))) - check(hip.hipSetDevice(1)) - check(hip.hipStreamWaitEvent(None, evt, 0)) - check(hip.hipSetDevice(0)) - check(hip.hipEventRecord(evt, None)) \ No newline at end of file diff --git a/tinygrad/extra/hip_gpu_driver/gc_10_3_0_offset.h b/tinygrad/extra/hip_gpu_driver/gc_10_3_0_offset.h deleted file mode 100644 index 5e15ac14..00000000 --- a/tinygrad/extra/hip_gpu_driver/gc_10_3_0_offset.h +++ /dev/null @@ -1,13609 +0,0 @@ -/* - * Copyright (C) 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _gc_10_3_0_OFFSET_HEADER -#define _gc_10_3_0_OFFSET_HEADER - -#define mmSQ_DEBUG_STS_GLOBAL 0x10A9 -#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 -#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 -#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 -#define mmSQ_DEBUG 0x10B1 -#define mmSQ_DEBUG_BASE_IDX 0 - -// addressBlock: gc_sdma0_sdma0dec -// base address: 0x4980 -#define mmSDMA0_DEC_START 0x0000 -#define mmSDMA0_DEC_START_BASE_IDX 0 -#define mmSDMA0_GLOBAL_TIMESTAMP_LO 0x000f -#define mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 -#define mmSDMA0_GLOBAL_TIMESTAMP_HI 0x0010 -#define mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 -#define mmSDMA0_PG_CNTL 0x0016 -#define mmSDMA0_PG_CNTL_BASE_IDX 0 -#define mmSDMA0_PG_CTX_LO 0x0017 -#define mmSDMA0_PG_CTX_LO_BASE_IDX 0 -#define mmSDMA0_PG_CTX_HI 0x0018 -#define mmSDMA0_PG_CTX_HI_BASE_IDX 0 -#define mmSDMA0_PG_CTX_CNTL 0x0019 -#define mmSDMA0_PG_CTX_CNTL_BASE_IDX 0 -#define mmSDMA0_POWER_CNTL 0x001a -#define mmSDMA0_POWER_CNTL_BASE_IDX 0 -#define mmSDMA0_CLK_CTRL 0x001b -#define mmSDMA0_CLK_CTRL_BASE_IDX 0 -#define mmSDMA0_CNTL 0x001c -#define mmSDMA0_CNTL_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS 0x001d -#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG 0x001e -#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH 0x0022 -#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA0_IB_OFFSET_FETCH 0x0023 -#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA0_PROGRAM 0x0024 -#define mmSDMA0_PROGRAM_BASE_IDX 0 -#define mmSDMA0_STATUS_REG 0x0025 -#define mmSDMA0_STATUS_REG_BASE_IDX 0 -#define mmSDMA0_STATUS1_REG 0x0026 -#define mmSDMA0_STATUS1_REG_BASE_IDX 0 -#define mmSDMA0_RD_BURST_CNTL 0x0027 -#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA0_UCODE_CHECKSUM 0x0029 -#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA0_F32_CNTL 0x002a -#define mmSDMA0_F32_CNTL_BASE_IDX 0 -#define mmSDMA0_FREEZE 0x002b -#define mmSDMA0_FREEZE_BASE_IDX 0 -#define mmSDMA0_PHASE0_QUANTUM 0x002c -#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA0_PHASE1_QUANTUM 0x002d -#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA0_EDC_CONFIG 0x0032 -#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA0_BA_THRESHOLD 0x0033 -#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA0_ID 0x0034 -#define mmSDMA0_ID_BASE_IDX 0 -#define mmSDMA0_VERSION 0x0035 -#define mmSDMA0_VERSION_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER 0x0036 -#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA0_STATUS2_REG 0x0038 -#define mmSDMA0_STATUS2_REG_BASE_IDX 0 -#define mmSDMA0_ATOMIC_CNTL 0x0039 -#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_LO 0x003a -#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_HI 0x003b -#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA0_UTCL1_CNTL 0x003c -#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA0_UTCL1_WATERMK 0x003d -#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_STATUS 0x003e -#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_STATUS 0x003f -#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV0 0x0040 -#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV1 0x0041 -#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV2 0x0042 -#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_TIMEOUT 0x0047 -#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA0_UTCL1_PAGE 0x0048 -#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA0_RELAX_ORDERING_LUT 0x004a -#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS_2 0x004b -#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA0_STATUS3_REG 0x004c -#define mmSDMA0_STATUS3_REG_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PHASE2_QUANTUM 0x004f -#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA0_ERROR_LOG 0x0050 -#define mmSDMA0_ERROR_LOG_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG0 0x0051 -#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG1 0x0052 -#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG2 0x0053 -#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG3 0x0054 -#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA0_F32_COUNTER 0x0055 -#define mmSDMA0_F32_COUNTER_BASE_IDX 0 -#define mmSDMA0_CRD_CNTL 0x005b -#define mmSDMA0_CRD_CNTL_BASE_IDX 0 -#define mmSDMA0_AQL_STATUS 0x005f -#define mmSDMA0_AQL_STATUS_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA0_TLBI_GCR_CNTL 0x0062 -#define mmSDMA0_TLBI_GCR_CNTL_BASE_IDX 0 -#define mmSDMA0_TILING_CONFIG 0x0063 -#define mmSDMA0_TILING_CONFIG_BASE_IDX 0 -#define mmSDMA0_INT_STATUS 0x0070 -#define mmSDMA0_INT_STATUS_BASE_IDX 0 -#define mmSDMA0_HOLE_ADDR_LO 0x0072 -#define mmSDMA0_HOLE_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_HOLE_ADDR_HI 0x0073 -#define mmSDMA0_HOLE_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_CLOCK_GATING_REG 0x0075 -#define mmSDMA0_CLOCK_GATING_REG_BASE_IDX 0 -#define mmSDMA0_STATUS4_REG 0x0076 -#define mmSDMA0_STATUS4_REG_BASE_IDX 0 -#define mmSDMA0_SCRATCH_RAM_DATA 0x0077 -#define mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 -#define mmSDMA0_SCRATCH_RAM_ADDR 0x0078 -#define mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 -#define mmSDMA0_TIMESTAMP_CNTL 0x0079 -#define mmSDMA0_TIMESTAMP_CNTL_BASE_IDX 0 -#define mmSDMA0_STATUS5_REG 0x007a -#define mmSDMA0_STATUS5_REG_BASE_IDX 0 -#define mmSDMA0_QUEUE_RESET_REQ 0x007b -#define mmSDMA0_QUEUE_RESET_REQ_BASE_IDX 0 -#define mmSDMA0_GFX_RB_CNTL 0x0080 -#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE 0x0081 -#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE_HI 0x0082 -#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR 0x0083 -#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR 0x0085 -#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_CNTL 0x008a -#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_IB_RPTR 0x008b -#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_IB_OFFSET 0x008c -#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_LO 0x008d -#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_HI 0x008e -#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SIZE 0x008f -#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_GFX_SKIP_CNTL 0x0090 -#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL 0x0092 -#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_STATUS 0x00a8 -#define mmSDMA0_GFX_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_GFX_WATERMARK 0x00aa -#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_GFX_PREEMPT 0x00b0 -#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA0_GFX_DUMMY_REG 0x00b1 -#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA9 0x00c9 -#define mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA10 0x00ca -#define mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_CNTL 0x00cb -#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_CNTL 0x00d8 -#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE 0x00d9 -#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE_HI 0x00da -#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR 0x00db -#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_HI 0x00dc -#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR 0x00dd -#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_HI 0x00de -#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_CNTL 0x00e2 -#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_RPTR 0x00e3 -#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_OFFSET 0x00e4 -#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_LO 0x00e5 -#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_HI 0x00e6 -#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SIZE 0x00e7 -#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_PAGE_SKIP_CNTL 0x00e8 -#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00e9 -#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL 0x00ea -#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA0_PAGE_STATUS 0x0100 -#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_LOG 0x0101 -#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_PAGE_WATERMARK 0x0102 -#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x0103 -#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_LO 0x0104 -#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_HI 0x0105 -#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x0107 -#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_PAGE_PREEMPT 0x0108 -#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA0_PAGE_DUMMY_REG 0x0109 -#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_AQL_CNTL 0x010c -#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0118 -#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0119 -#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA2 0x011a -#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA3 0x011b -#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA4 0x011c -#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA5 0x011d -#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA6 0x011e -#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA7 0x011f -#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0120 -#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA9 0x0121 -#define mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA10 0x0122 -#define mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0123 -#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_CNTL 0x0130 -#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE 0x0131 -#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE_HI 0x0132 -#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR 0x0133 -#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_HI 0x0134 -#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR 0x0135 -#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_HI 0x0136 -#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_CNTL 0x013a -#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_RPTR 0x013b -#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_OFFSET 0x013c -#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_LO 0x013d -#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_HI 0x013e -#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SIZE 0x013f -#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC0_SKIP_CNTL 0x0140 -#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0141 -#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL 0x0142 -#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC0_STATUS 0x0158 -#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_LOG 0x0159 -#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC0_WATERMARK 0x015a -#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x015b -#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_LO 0x015c -#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_HI 0x015d -#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x015f -#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC0_PREEMPT 0x0160 -#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC0_DUMMY_REG 0x0161 -#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0164 -#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0170 -#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0171 -#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0172 -#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0173 -#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0174 -#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0175 -#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0176 -#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0177 -#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0178 -#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA9 0x0179 -#define mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA10 0x017a -#define mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_CNTL 0x017b -#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_CNTL 0x0188 -#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE 0x0189 -#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE_HI 0x018a -#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR 0x018b -#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_HI 0x018c -#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR 0x018d -#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_HI 0x018e -#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_CNTL 0x0192 -#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_RPTR 0x0193 -#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_OFFSET 0x0194 -#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_LO 0x0195 -#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_HI 0x0196 -#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SIZE 0x0197 -#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC1_SKIP_CNTL 0x0198 -#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_CONTEXT_STATUS 0x0199 -#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL 0x019a -#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC1_STATUS 0x01b0 -#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_LOG 0x01b1 -#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC1_WATERMARK 0x01b2 -#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 -#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01b4 -#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01b5 -#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 -#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC1_PREEMPT 0x01b8 -#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC1_DUMMY_REG 0x01b9 -#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01bc -#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01c8 -#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01c9 -#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01ca -#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01cb -#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01cc -#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01cd -#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01ce -#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01cf -#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01d0 -#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA9 0x01d1 -#define mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA10 0x01d2 -#define mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01d3 -#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_CNTL 0x01e0 -#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_BASE 0x01e1 -#define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_BASE_HI 0x01e2 -#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_RPTR 0x01e3 -#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_RPTR_HI 0x01e4 -#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_WPTR 0x01e5 -#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_WPTR_HI 0x01e6 -#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 -#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 -#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 -#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_CNTL 0x01ea -#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_RPTR 0x01eb -#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_OFFSET 0x01ec -#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_BASE_LO 0x01ed -#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_BASE_HI 0x01ee -#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_SIZE 0x01ef -#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC2_SKIP_CNTL 0x01f0 -#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_CONTEXT_STATUS 0x01f1 -#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC2_DOORBELL 0x01f2 -#define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC2_STATUS 0x0208 -#define mmSDMA0_RLC2_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC2_DOORBELL_LOG 0x0209 -#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC2_WATERMARK 0x020a -#define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC2_DOORBELL_OFFSET 0x020b -#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC2_CSA_ADDR_LO 0x020c -#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC2_CSA_ADDR_HI 0x020d -#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_IB_SUB_REMAIN 0x020f -#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC2_PREEMPT 0x0210 -#define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC2_DUMMY_REG 0x0211 -#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 -#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 -#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC2_RB_AQL_CNTL 0x0214 -#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 -#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA0 0x0220 -#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA1 0x0221 -#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA2 0x0222 -#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA3 0x0223 -#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA4 0x0224 -#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA5 0x0225 -#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA6 0x0226 -#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA7 0x0227 -#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA8 0x0228 -#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA9 0x0229 -#define mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_DATA10 0x022a -#define mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC2_MIDCMD_CNTL 0x022b -#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_CNTL 0x0238 -#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_BASE 0x0239 -#define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_BASE_HI 0x023a -#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_RPTR 0x023b -#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_RPTR_HI 0x023c -#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_WPTR 0x023d -#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_WPTR_HI 0x023e -#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f -#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 -#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 -#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_CNTL 0x0242 -#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_RPTR 0x0243 -#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_OFFSET 0x0244 -#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_BASE_LO 0x0245 -#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_BASE_HI 0x0246 -#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_SIZE 0x0247 -#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC3_SKIP_CNTL 0x0248 -#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_CONTEXT_STATUS 0x0249 -#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC3_DOORBELL 0x024a -#define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC3_STATUS 0x0260 -#define mmSDMA0_RLC3_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC3_DOORBELL_LOG 0x0261 -#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC3_WATERMARK 0x0262 -#define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC3_DOORBELL_OFFSET 0x0263 -#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC3_CSA_ADDR_LO 0x0264 -#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC3_CSA_ADDR_HI 0x0265 -#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_IB_SUB_REMAIN 0x0267 -#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC3_PREEMPT 0x0268 -#define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC3_DUMMY_REG 0x0269 -#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a -#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b -#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC3_RB_AQL_CNTL 0x026c -#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d -#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA0 0x0278 -#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA1 0x0279 -#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA2 0x027a -#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA3 0x027b -#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA4 0x027c -#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA5 0x027d -#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA6 0x027e -#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA7 0x027f -#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA8 0x0280 -#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA9 0x0281 -#define mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_DATA10 0x0282 -#define mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC3_MIDCMD_CNTL 0x0283 -#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_CNTL 0x0290 -#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_BASE 0x0291 -#define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_BASE_HI 0x0292 -#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_RPTR 0x0293 -#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_RPTR_HI 0x0294 -#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_WPTR 0x0295 -#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_WPTR_HI 0x0296 -#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 -#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 -#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 -#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_CNTL 0x029a -#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_RPTR 0x029b -#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_OFFSET 0x029c -#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_BASE_LO 0x029d -#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_BASE_HI 0x029e -#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_SIZE 0x029f -#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC4_SKIP_CNTL 0x02a0 -#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_CONTEXT_STATUS 0x02a1 -#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC4_DOORBELL 0x02a2 -#define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC4_STATUS 0x02b8 -#define mmSDMA0_RLC4_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC4_DOORBELL_LOG 0x02b9 -#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC4_WATERMARK 0x02ba -#define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02bb -#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC4_CSA_ADDR_LO 0x02bc -#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC4_CSA_ADDR_HI 0x02bd -#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02bf -#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC4_PREEMPT 0x02c0 -#define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC4_DUMMY_REG 0x02c1 -#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 -#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 -#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC4_RB_AQL_CNTL 0x02c4 -#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 -#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA0 0x02d0 -#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA1 0x02d1 -#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA2 0x02d2 -#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA3 0x02d3 -#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA4 0x02d4 -#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA5 0x02d5 -#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA6 0x02d6 -#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA7 0x02d7 -#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA8 0x02d8 -#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA9 0x02d9 -#define mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_DATA10 0x02da -#define mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC4_MIDCMD_CNTL 0x02db -#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_CNTL 0x02e8 -#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_BASE 0x02e9 -#define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_BASE_HI 0x02ea -#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_RPTR 0x02eb -#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_RPTR_HI 0x02ec -#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_WPTR 0x02ed -#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_WPTR_HI 0x02ee -#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef -#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 -#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 -#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_CNTL 0x02f2 -#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_RPTR 0x02f3 -#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_OFFSET 0x02f4 -#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_BASE_LO 0x02f5 -#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_BASE_HI 0x02f6 -#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_SIZE 0x02f7 -#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC5_SKIP_CNTL 0x02f8 -#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_CONTEXT_STATUS 0x02f9 -#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC5_DOORBELL 0x02fa -#define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC5_STATUS 0x0310 -#define mmSDMA0_RLC5_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC5_DOORBELL_LOG 0x0311 -#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC5_WATERMARK 0x0312 -#define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC5_DOORBELL_OFFSET 0x0313 -#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC5_CSA_ADDR_LO 0x0314 -#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC5_CSA_ADDR_HI 0x0315 -#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_IB_SUB_REMAIN 0x0317 -#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC5_PREEMPT 0x0318 -#define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC5_DUMMY_REG 0x0319 -#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a -#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b -#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC5_RB_AQL_CNTL 0x031c -#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d -#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA0 0x0328 -#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA1 0x0329 -#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA2 0x032a -#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA3 0x032b -#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA4 0x032c -#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA5 0x032d -#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA6 0x032e -#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA7 0x032f -#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA8 0x0330 -#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA9 0x0331 -#define mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_DATA10 0x0332 -#define mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC5_MIDCMD_CNTL 0x0333 -#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_CNTL 0x0340 -#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_BASE 0x0341 -#define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_BASE_HI 0x0342 -#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_RPTR 0x0343 -#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_RPTR_HI 0x0344 -#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_WPTR 0x0345 -#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_WPTR_HI 0x0346 -#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 -#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 -#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 -#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_CNTL 0x034a -#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_RPTR 0x034b -#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_OFFSET 0x034c -#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_BASE_LO 0x034d -#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_BASE_HI 0x034e -#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_SIZE 0x034f -#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC6_SKIP_CNTL 0x0350 -#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_CONTEXT_STATUS 0x0351 -#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC6_DOORBELL 0x0352 -#define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC6_STATUS 0x0368 -#define mmSDMA0_RLC6_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC6_DOORBELL_LOG 0x0369 -#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC6_WATERMARK 0x036a -#define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC6_DOORBELL_OFFSET 0x036b -#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC6_CSA_ADDR_LO 0x036c -#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC6_CSA_ADDR_HI 0x036d -#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_IB_SUB_REMAIN 0x036f -#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC6_PREEMPT 0x0370 -#define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC6_DUMMY_REG 0x0371 -#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 -#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 -#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC6_RB_AQL_CNTL 0x0374 -#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 -#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA0 0x0380 -#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA1 0x0381 -#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA2 0x0382 -#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA3 0x0383 -#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA4 0x0384 -#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA5 0x0385 -#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA6 0x0386 -#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA7 0x0387 -#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA8 0x0388 -#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA9 0x0389 -#define mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_DATA10 0x038a -#define mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC6_MIDCMD_CNTL 0x038b -#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_CNTL 0x0398 -#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_BASE 0x0399 -#define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_BASE_HI 0x039a -#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_RPTR 0x039b -#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_RPTR_HI 0x039c -#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_WPTR 0x039d -#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_WPTR_HI 0x039e -#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f -#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 -#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 -#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_CNTL 0x03a2 -#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_RPTR 0x03a3 -#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_OFFSET 0x03a4 -#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_BASE_LO 0x03a5 -#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_BASE_HI 0x03a6 -#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_SIZE 0x03a7 -#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC7_SKIP_CNTL 0x03a8 -#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_CONTEXT_STATUS 0x03a9 -#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC7_DOORBELL 0x03aa -#define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC7_STATUS 0x03c0 -#define mmSDMA0_RLC7_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC7_DOORBELL_LOG 0x03c1 -#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC7_WATERMARK 0x03c2 -#define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 -#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC7_CSA_ADDR_LO 0x03c4 -#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC7_CSA_ADDR_HI 0x03c5 -#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 -#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC7_PREEMPT 0x03c8 -#define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC7_DUMMY_REG 0x03c9 -#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca -#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb -#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC7_RB_AQL_CNTL 0x03cc -#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd -#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA0 0x03d8 -#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA1 0x03d9 -#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA2 0x03da -#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA3 0x03db -#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA4 0x03dc -#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA5 0x03dd -#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA6 0x03de -#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA7 0x03df -#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA8 0x03e0 -#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA9 0x03e1 -#define mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_DATA10 0x03e2 -#define mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA0_RLC7_MIDCMD_CNTL 0x03e3 -#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 - - -// addressBlock: gc_sdma1_sdma1dec -// base address: 0x6180 -#define mmSDMA1_DEC_START 0x0600 -#define mmSDMA1_DEC_START_BASE_IDX 0 -#define mmSDMA1_GLOBAL_TIMESTAMP_LO 0x060f -#define mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 -#define mmSDMA1_GLOBAL_TIMESTAMP_HI 0x0610 -#define mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 -#define mmSDMA1_PG_CNTL 0x0616 -#define mmSDMA1_PG_CNTL_BASE_IDX 0 -#define mmSDMA1_PG_CTX_LO 0x0617 -#define mmSDMA1_PG_CTX_LO_BASE_IDX 0 -#define mmSDMA1_PG_CTX_HI 0x0618 -#define mmSDMA1_PG_CTX_HI_BASE_IDX 0 -#define mmSDMA1_PG_CTX_CNTL 0x0619 -#define mmSDMA1_PG_CTX_CNTL_BASE_IDX 0 -#define mmSDMA1_POWER_CNTL 0x061a -#define mmSDMA1_POWER_CNTL_BASE_IDX 0 -#define mmSDMA1_CLK_CTRL 0x061b -#define mmSDMA1_CLK_CTRL_BASE_IDX 0 -#define mmSDMA1_CNTL 0x061c -#define mmSDMA1_CNTL_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS 0x061d -#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG 0x061e -#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG_READ 0x061f -#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH_HI 0x0620 -#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0621 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH 0x0622 -#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA1_IB_OFFSET_FETCH 0x0623 -#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA1_PROGRAM 0x0624 -#define mmSDMA1_PROGRAM_BASE_IDX 0 -#define mmSDMA1_STATUS_REG 0x0625 -#define mmSDMA1_STATUS_REG_BASE_IDX 0 -#define mmSDMA1_STATUS1_REG 0x0626 -#define mmSDMA1_STATUS1_REG_BASE_IDX 0 -#define mmSDMA1_RD_BURST_CNTL 0x0627 -#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA1_HBM_PAGE_CONFIG 0x0628 -#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA1_UCODE_CHECKSUM 0x0629 -#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA1_F32_CNTL 0x062a -#define mmSDMA1_F32_CNTL_BASE_IDX 0 -#define mmSDMA1_FREEZE 0x062b -#define mmSDMA1_FREEZE_BASE_IDX 0 -#define mmSDMA1_PHASE0_QUANTUM 0x062c -#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA1_PHASE1_QUANTUM 0x062d -#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA1_EDC_CONFIG 0x0632 -#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA1_BA_THRESHOLD 0x0633 -#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA1_ID 0x0634 -#define mmSDMA1_ID_BASE_IDX 0 -#define mmSDMA1_VERSION 0x0635 -#define mmSDMA1_VERSION_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER 0x0636 -#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER_CLEAR 0x0637 -#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA1_STATUS2_REG 0x0638 -#define mmSDMA1_STATUS2_REG_BASE_IDX 0 -#define mmSDMA1_ATOMIC_CNTL 0x0639 -#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_LO 0x063a -#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_HI 0x063b -#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA1_UTCL1_CNTL 0x063c -#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA1_UTCL1_WATERMK 0x063d -#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_STATUS 0x063e -#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_STATUS 0x063f -#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV0 0x0640 -#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV1 0x0641 -#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV2 0x0642 -#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK0 0x0643 -#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK1 0x0644 -#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK0 0x0645 -#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK1 0x0646 -#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_TIMEOUT 0x0647 -#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA1_UTCL1_PAGE 0x0648 -#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA1_RELAX_ORDERING_LUT 0x064a -#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS_2 0x064b -#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA1_STATUS3_REG 0x064c -#define mmSDMA1_STATUS3_REG_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_LO 0x064d -#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_HI 0x064e -#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PHASE2_QUANTUM 0x064f -#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA1_ERROR_LOG 0x0650 -#define mmSDMA1_ERROR_LOG_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG0 0x0651 -#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG1 0x0652 -#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG2 0x0653 -#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG3 0x0654 -#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA1_F32_COUNTER 0x0655 -#define mmSDMA1_F32_COUNTER_BASE_IDX 0 -#define mmSDMA1_CRD_CNTL 0x065b -#define mmSDMA1_CRD_CNTL_BASE_IDX 0 -#define mmSDMA1_AQL_STATUS 0x065f -#define mmSDMA1_AQL_STATUS_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0660 -#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0661 -#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA1_TLBI_GCR_CNTL 0x0662 -#define mmSDMA1_TLBI_GCR_CNTL_BASE_IDX 0 -#define mmSDMA1_TILING_CONFIG 0x0663 -#define mmSDMA1_TILING_CONFIG_BASE_IDX 0 -#define mmSDMA1_INT_STATUS 0x0670 -#define mmSDMA1_INT_STATUS_BASE_IDX 0 -#define mmSDMA1_HOLE_ADDR_LO 0x0672 -#define mmSDMA1_HOLE_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_HOLE_ADDR_HI 0x0673 -#define mmSDMA1_HOLE_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_CLOCK_GATING_REG 0x0675 -#define mmSDMA1_CLOCK_GATING_REG_BASE_IDX 0 -#define mmSDMA1_STATUS4_REG 0x0676 -#define mmSDMA1_STATUS4_REG_BASE_IDX 0 -#define mmSDMA1_SCRATCH_RAM_DATA 0x0677 -#define mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 -#define mmSDMA1_SCRATCH_RAM_ADDR 0x0678 -#define mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 -#define mmSDMA1_TIMESTAMP_CNTL 0x0679 -#define mmSDMA1_TIMESTAMP_CNTL_BASE_IDX 0 -#define mmSDMA1_STATUS5_REG 0x067a -#define mmSDMA1_STATUS5_REG_BASE_IDX 0 -#define mmSDMA1_QUEUE_RESET_REQ 0x067b -#define mmSDMA1_QUEUE_RESET_REQ_BASE_IDX 0 -#define mmSDMA1_GFX_RB_CNTL 0x0680 -#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE 0x0681 -#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE_HI 0x0682 -#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR 0x0683 -#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_HI 0x0684 -#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR 0x0685 -#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_HI 0x0686 -#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0688 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0689 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_CNTL 0x068a -#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_IB_RPTR 0x068b -#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_IB_OFFSET 0x068c -#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_LO 0x068d -#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_HI 0x068e -#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SIZE 0x068f -#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_GFX_SKIP_CNTL 0x0690 -#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_STATUS 0x0691 -#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL 0x0692 -#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_CNTL 0x0693 -#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_STATUS 0x06a8 -#define mmSDMA1_GFX_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_LOG 0x06a9 -#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_GFX_WATERMARK 0x06aa -#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_OFFSET 0x06ab -#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_LO 0x06ac -#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_HI 0x06ad -#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SUB_REMAIN 0x06af -#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_GFX_PREEMPT 0x06b0 -#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA1_GFX_DUMMY_REG 0x06b1 -#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x06b2 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x06b3 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_RB_AQL_CNTL 0x06b4 -#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x06b5 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA0 0x06c0 -#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA1 0x06c1 -#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA2 0x06c2 -#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA3 0x06c3 -#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA4 0x06c4 -#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA5 0x06c5 -#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA6 0x06c6 -#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA7 0x06c7 -#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA8 0x06c8 -#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA9 0x06c9 -#define mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA10 0x06ca -#define mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_CNTL 0x06cb -#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_CNTL 0x06d8 -#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE 0x06d9 -#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE_HI 0x06da -#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR 0x06db -#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_HI 0x06dc -#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR 0x06dd -#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_HI 0x06de -#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06df -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x06e0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x06e1 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_CNTL 0x06e2 -#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_RPTR 0x06e3 -#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_OFFSET 0x06e4 -#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_LO 0x06e5 -#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_HI 0x06e6 -#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SIZE 0x06e7 -#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_PAGE_SKIP_CNTL 0x06e8 -#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_CONTEXT_STATUS 0x06e9 -#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL 0x06ea -#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA1_PAGE_STATUS 0x0700 -#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_LOG 0x0701 -#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_PAGE_WATERMARK 0x0702 -#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x0703 -#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_LO 0x0704 -#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_HI 0x0705 -#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x0707 -#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_PAGE_PREEMPT 0x0708 -#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA1_PAGE_DUMMY_REG 0x0709 -#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x070a -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x070b -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_AQL_CNTL 0x070c -#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x070d -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0718 -#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0719 -#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA2 0x071a -#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA3 0x071b -#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA4 0x071c -#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA5 0x071d -#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA6 0x071e -#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA7 0x071f -#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0720 -#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA9 0x0721 -#define mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA10 0x0722 -#define mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0723 -#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_CNTL 0x0730 -#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE 0x0731 -#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE_HI 0x0732 -#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR 0x0733 -#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_HI 0x0734 -#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR 0x0735 -#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_HI 0x0736 -#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0737 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0738 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0739 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_CNTL 0x073a -#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_RPTR 0x073b -#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_OFFSET 0x073c -#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_LO 0x073d -#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_HI 0x073e -#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SIZE 0x073f -#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC0_SKIP_CNTL 0x0740 -#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0741 -#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL 0x0742 -#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC0_STATUS 0x0758 -#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_LOG 0x0759 -#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC0_WATERMARK 0x075a -#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x075b -#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_LO 0x075c -#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_HI 0x075d -#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x075f -#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC0_PREEMPT 0x0760 -#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC0_DUMMY_REG 0x0761 -#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0762 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0763 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0764 -#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0765 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0770 -#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0771 -#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0772 -#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0773 -#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0774 -#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0775 -#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0776 -#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0777 -#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0778 -#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA9 0x0779 -#define mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA10 0x077a -#define mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_CNTL 0x077b -#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_CNTL 0x0788 -#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE 0x0789 -#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE_HI 0x078a -#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR 0x078b -#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_HI 0x078c -#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR 0x078d -#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_HI 0x078e -#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x078f -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0790 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0791 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_CNTL 0x0792 -#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_RPTR 0x0793 -#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_OFFSET 0x0794 -#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_LO 0x0795 -#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_HI 0x0796 -#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SIZE 0x0797 -#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC1_SKIP_CNTL 0x0798 -#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_CONTEXT_STATUS 0x0799 -#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL 0x079a -#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC1_STATUS 0x07b0 -#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_LOG 0x07b1 -#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC1_WATERMARK 0x07b2 -#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x07b3 -#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_LO 0x07b4 -#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_HI 0x07b5 -#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x07b7 -#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC1_PREEMPT 0x07b8 -#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC1_DUMMY_REG 0x07b9 -#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x07ba -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x07bb -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_AQL_CNTL 0x07bc -#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x07bd -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA0 0x07c8 -#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA1 0x07c9 -#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA2 0x07ca -#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA3 0x07cb -#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA4 0x07cc -#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA5 0x07cd -#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA6 0x07ce -#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA7 0x07cf -#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA8 0x07d0 -#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA9 0x07d1 -#define mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA10 0x07d2 -#define mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_CNTL 0x07d3 -#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_CNTL 0x07e0 -#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_BASE 0x07e1 -#define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_BASE_HI 0x07e2 -#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_RPTR 0x07e3 -#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_RPTR_HI 0x07e4 -#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_WPTR 0x07e5 -#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_WPTR_HI 0x07e6 -#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x07e7 -#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x07e8 -#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x07e9 -#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_CNTL 0x07ea -#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_RPTR 0x07eb -#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_OFFSET 0x07ec -#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_BASE_LO 0x07ed -#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_BASE_HI 0x07ee -#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_SIZE 0x07ef -#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC2_SKIP_CNTL 0x07f0 -#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_CONTEXT_STATUS 0x07f1 -#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC2_DOORBELL 0x07f2 -#define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC2_STATUS 0x0808 -#define mmSDMA1_RLC2_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC2_DOORBELL_LOG 0x0809 -#define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC2_WATERMARK 0x080a -#define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC2_DOORBELL_OFFSET 0x080b -#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC2_CSA_ADDR_LO 0x080c -#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC2_CSA_ADDR_HI 0x080d -#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_IB_SUB_REMAIN 0x080f -#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC2_PREEMPT 0x0810 -#define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC2_DUMMY_REG 0x0811 -#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0812 -#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0813 -#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC2_RB_AQL_CNTL 0x0814 -#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0815 -#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA0 0x0820 -#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA1 0x0821 -#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA2 0x0822 -#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA3 0x0823 -#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA4 0x0824 -#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA5 0x0825 -#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA6 0x0826 -#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA7 0x0827 -#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA8 0x0828 -#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA9 0x0829 -#define mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_DATA10 0x082a -#define mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC2_MIDCMD_CNTL 0x082b -#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_CNTL 0x0838 -#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_BASE 0x0839 -#define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_BASE_HI 0x083a -#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_RPTR 0x083b -#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_RPTR_HI 0x083c -#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_WPTR 0x083d -#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_WPTR_HI 0x083e -#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x083f -#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0840 -#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0841 -#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_CNTL 0x0842 -#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_RPTR 0x0843 -#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_OFFSET 0x0844 -#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_BASE_LO 0x0845 -#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_BASE_HI 0x0846 -#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_SIZE 0x0847 -#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC3_SKIP_CNTL 0x0848 -#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_CONTEXT_STATUS 0x0849 -#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC3_DOORBELL 0x084a -#define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC3_STATUS 0x0860 -#define mmSDMA1_RLC3_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC3_DOORBELL_LOG 0x0861 -#define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC3_WATERMARK 0x0862 -#define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC3_DOORBELL_OFFSET 0x0863 -#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC3_CSA_ADDR_LO 0x0864 -#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC3_CSA_ADDR_HI 0x0865 -#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_IB_SUB_REMAIN 0x0867 -#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC3_PREEMPT 0x0868 -#define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC3_DUMMY_REG 0x0869 -#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x086a -#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x086b -#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC3_RB_AQL_CNTL 0x086c -#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x086d -#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA0 0x0878 -#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA1 0x0879 -#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA2 0x087a -#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA3 0x087b -#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA4 0x087c -#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA5 0x087d -#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA6 0x087e -#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA7 0x087f -#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA8 0x0880 -#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA9 0x0881 -#define mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_DATA10 0x0882 -#define mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC3_MIDCMD_CNTL 0x0883 -#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_CNTL 0x0890 -#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_BASE 0x0891 -#define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_BASE_HI 0x0892 -#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_RPTR 0x0893 -#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_RPTR_HI 0x0894 -#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_WPTR 0x0895 -#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_WPTR_HI 0x0896 -#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0897 -#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0898 -#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0899 -#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_CNTL 0x089a -#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_RPTR 0x089b -#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_OFFSET 0x089c -#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_BASE_LO 0x089d -#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_BASE_HI 0x089e -#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_SIZE 0x089f -#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC4_SKIP_CNTL 0x08a0 -#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_CONTEXT_STATUS 0x08a1 -#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC4_DOORBELL 0x08a2 -#define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC4_STATUS 0x08b8 -#define mmSDMA1_RLC4_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC4_DOORBELL_LOG 0x08b9 -#define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC4_WATERMARK 0x08ba -#define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC4_DOORBELL_OFFSET 0x08bb -#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC4_CSA_ADDR_LO 0x08bc -#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC4_CSA_ADDR_HI 0x08bd -#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_IB_SUB_REMAIN 0x08bf -#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC4_PREEMPT 0x08c0 -#define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC4_DUMMY_REG 0x08c1 -#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x08c2 -#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x08c3 -#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC4_RB_AQL_CNTL 0x08c4 -#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x08c5 -#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA0 0x08d0 -#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA1 0x08d1 -#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA2 0x08d2 -#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA3 0x08d3 -#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA4 0x08d4 -#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA5 0x08d5 -#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA6 0x08d6 -#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA7 0x08d7 -#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA8 0x08d8 -#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA9 0x08d9 -#define mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_DATA10 0x08da -#define mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC4_MIDCMD_CNTL 0x08db -#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_CNTL 0x08e8 -#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_BASE 0x08e9 -#define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_BASE_HI 0x08ea -#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_RPTR 0x08eb -#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_RPTR_HI 0x08ec -#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_WPTR 0x08ed -#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_WPTR_HI 0x08ee -#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x08ef -#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x08f0 -#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x08f1 -#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_CNTL 0x08f2 -#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_RPTR 0x08f3 -#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_OFFSET 0x08f4 -#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_BASE_LO 0x08f5 -#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_BASE_HI 0x08f6 -#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_SIZE 0x08f7 -#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC5_SKIP_CNTL 0x08f8 -#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_CONTEXT_STATUS 0x08f9 -#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC5_DOORBELL 0x08fa -#define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC5_STATUS 0x0910 -#define mmSDMA1_RLC5_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC5_DOORBELL_LOG 0x0911 -#define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC5_WATERMARK 0x0912 -#define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC5_DOORBELL_OFFSET 0x0913 -#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC5_CSA_ADDR_LO 0x0914 -#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC5_CSA_ADDR_HI 0x0915 -#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_IB_SUB_REMAIN 0x0917 -#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC5_PREEMPT 0x0918 -#define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC5_DUMMY_REG 0x0919 -#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x091a -#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x091b -#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC5_RB_AQL_CNTL 0x091c -#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x091d -#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA0 0x0928 -#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA1 0x0929 -#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA2 0x092a -#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA3 0x092b -#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA4 0x092c -#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA5 0x092d -#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA6 0x092e -#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA7 0x092f -#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA8 0x0930 -#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA9 0x0931 -#define mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_DATA10 0x0932 -#define mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC5_MIDCMD_CNTL 0x0933 -#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_CNTL 0x0940 -#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_BASE 0x0941 -#define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_BASE_HI 0x0942 -#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_RPTR 0x0943 -#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_RPTR_HI 0x0944 -#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_WPTR 0x0945 -#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_WPTR_HI 0x0946 -#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0947 -#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0948 -#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0949 -#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_CNTL 0x094a -#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_RPTR 0x094b -#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_OFFSET 0x094c -#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_BASE_LO 0x094d -#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_BASE_HI 0x094e -#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_SIZE 0x094f -#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC6_SKIP_CNTL 0x0950 -#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_CONTEXT_STATUS 0x0951 -#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC6_DOORBELL 0x0952 -#define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC6_STATUS 0x0968 -#define mmSDMA1_RLC6_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC6_DOORBELL_LOG 0x0969 -#define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC6_WATERMARK 0x096a -#define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC6_DOORBELL_OFFSET 0x096b -#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC6_CSA_ADDR_LO 0x096c -#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC6_CSA_ADDR_HI 0x096d -#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_IB_SUB_REMAIN 0x096f -#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC6_PREEMPT 0x0970 -#define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC6_DUMMY_REG 0x0971 -#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0972 -#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0973 -#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC6_RB_AQL_CNTL 0x0974 -#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x0975 -#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA0 0x0980 -#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA1 0x0981 -#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA2 0x0982 -#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA3 0x0983 -#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA4 0x0984 -#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA5 0x0985 -#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA6 0x0986 -#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA7 0x0987 -#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA8 0x0988 -#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA9 0x0989 -#define mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_DATA10 0x098a -#define mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC6_MIDCMD_CNTL 0x098b -#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_CNTL 0x0998 -#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_BASE 0x0999 -#define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_BASE_HI 0x099a -#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_RPTR 0x099b -#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_RPTR_HI 0x099c -#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_WPTR 0x099d -#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_WPTR_HI 0x099e -#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x099f -#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x09a0 -#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x09a1 -#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_CNTL 0x09a2 -#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_RPTR 0x09a3 -#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_OFFSET 0x09a4 -#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_BASE_LO 0x09a5 -#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_BASE_HI 0x09a6 -#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_SIZE 0x09a7 -#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC7_SKIP_CNTL 0x09a8 -#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_CONTEXT_STATUS 0x09a9 -#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC7_DOORBELL 0x09aa -#define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC7_STATUS 0x09c0 -#define mmSDMA1_RLC7_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC7_DOORBELL_LOG 0x09c1 -#define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC7_WATERMARK 0x09c2 -#define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC7_DOORBELL_OFFSET 0x09c3 -#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC7_CSA_ADDR_LO 0x09c4 -#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC7_CSA_ADDR_HI 0x09c5 -#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_IB_SUB_REMAIN 0x09c7 -#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC7_PREEMPT 0x09c8 -#define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC7_DUMMY_REG 0x09c9 -#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x09ca -#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x09cb -#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC7_RB_AQL_CNTL 0x09cc -#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x09cd -#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA0 0x09d8 -#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA1 0x09d9 -#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA2 0x09da -#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA3 0x09db -#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA4 0x09dc -#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA5 0x09dd -#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA6 0x09de -#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA7 0x09df -#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA8 0x09e0 -#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA9 0x09e1 -#define mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_DATA10 0x09e2 -#define mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX 0 -#define mmSDMA1_RLC7_MIDCMD_CNTL 0x09e3 -#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 - - -// addressBlock: gc_grbmdec -// base address: 0x8000 -#define mmGRBM_CNTL 0x0da0 -#define mmGRBM_CNTL_BASE_IDX 0 -#define mmGRBM_SKEW_CNTL 0x0da1 -#define mmGRBM_SKEW_CNTL_BASE_IDX 0 -#define mmGRBM_STATUS2 0x0da2 -#define mmGRBM_STATUS2_BASE_IDX 0 -#define mmGRBM_PWR_CNTL 0x0da3 -#define mmGRBM_PWR_CNTL_BASE_IDX 0 -#define mmGRBM_STATUS 0x0da4 -#define mmGRBM_STATUS_BASE_IDX 0 -#define mmGRBM_STATUS_SE0 0x0da5 -#define mmGRBM_STATUS_SE0_BASE_IDX 0 -#define mmGRBM_STATUS_SE1 0x0da6 -#define mmGRBM_STATUS_SE1_BASE_IDX 0 -#define mmGRBM_STATUS3 0x0da7 -#define mmGRBM_STATUS3_BASE_IDX 0 -#define mmGRBM_SOFT_RESET 0x0da8 -#define mmGRBM_SOFT_RESET_BASE_IDX 0 -#define mmGRBM_GFX_CLKEN_CNTL 0x0dac -#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 -#define mmGRBM_WAIT_IDLE_CLOCKS 0x0dad -#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 -#define mmGRBM_STATUS_SE2 0x0dae -#define mmGRBM_STATUS_SE2_BASE_IDX 0 -#define mmGRBM_STATUS_SE3 0x0daf -#define mmGRBM_STATUS_SE3_BASE_IDX 0 -#define mmGRBM_READ_ERROR 0x0db6 -#define mmGRBM_READ_ERROR_BASE_IDX 0 -#define mmGRBM_READ_ERROR2 0x0db7 -#define mmGRBM_READ_ERROR2_BASE_IDX 0 -#define mmGRBM_INT_CNTL 0x0db8 -#define mmGRBM_INT_CNTL_BASE_IDX 0 -#define mmGRBM_TRAP_OP 0x0db9 -#define mmGRBM_TRAP_OP_BASE_IDX 0 -#define mmGRBM_TRAP_ADDR 0x0dba -#define mmGRBM_TRAP_ADDR_BASE_IDX 0 -#define mmGRBM_TRAP_ADDR_MSK 0x0dbb -#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 -#define mmGRBM_TRAP_WD 0x0dbc -#define mmGRBM_TRAP_WD_BASE_IDX 0 -#define mmGRBM_TRAP_WD_MSK 0x0dbd -#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 -#define mmGRBM_DSM_BYPASS 0x0dbe -#define mmGRBM_DSM_BYPASS_BASE_IDX 0 -#define mmGRBM_WRITE_ERROR 0x0dbf -#define mmGRBM_WRITE_ERROR_BASE_IDX 0 -#define mmGRBM_CHIP_REVISION 0x0dc1 -#define mmGRBM_CHIP_REVISION_BASE_IDX 0 -#define mmGRBM_GFX_CNTL 0x0dc2 -#define mmGRBM_GFX_CNTL_BASE_IDX 0 -#define mmGRBM_IH_CREDIT 0x0dc4 -#define mmGRBM_IH_CREDIT_BASE_IDX 0 -#define mmGRBM_PWR_CNTL2 0x0dc5 -#define mmGRBM_PWR_CNTL2_BASE_IDX 0 -#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 -#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 -#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 -#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 -#define mmGRBM_FENCE_RANGE0 0x0dca -#define mmGRBM_FENCE_RANGE0_BASE_IDX 0 -#define mmGRBM_FENCE_RANGE1 0x0dcb -#define mmGRBM_FENCE_RANGE1_BASE_IDX 0 -#define mmGRBM_NOWHERE 0x0ddf -#define mmGRBM_NOWHERE_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG0 0x0de0 -#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG1 0x0de1 -#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG2 0x0de2 -#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG3 0x0de3 -#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG4 0x0de4 -#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG5 0x0de5 -#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG6 0x0de6 -#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 -#define mmGRBM_SCRATCH_REG7 0x0de7 -#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 -#define mmVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 -#define mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 - - -// addressBlock: gc_cpdec -// base address: 0x8200 -#define mmCP_CPC_STATUS 0x0e24 -#define mmCP_CPC_STATUS_BASE_IDX 0 -#define mmCP_CPC_BUSY_STAT 0x0e25 -#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 -#define mmCP_CPC_STALLED_STAT1 0x0e26 -#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 -#define mmCP_CPF_STATUS 0x0e27 -#define mmCP_CPF_STATUS_BASE_IDX 0 -#define mmCP_CPF_BUSY_STAT 0x0e28 -#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 -#define mmCP_CPF_STALLED_STAT1 0x0e29 -#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 -#define mmCP_CPC_BUSY_STAT2 0x0e2a -#define mmCP_CPC_BUSY_STAT2_BASE_IDX 0 -#define mmCP_CPC_GRBM_FREE_COUNT 0x0e2b -#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 -#define mmCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c -#define mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 -#define mmCP_MEC_ME1_HEADER_DUMP 0x0e2e -#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 -#define mmCP_MEC_ME2_HEADER_DUMP 0x0e2f -#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 -#define mmCP_CPC_SCRATCH_INDEX 0x0e30 -#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 -#define mmCP_CPC_SCRATCH_DATA 0x0e31 -#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 -#define mmCP_CPF_GRBM_FREE_COUNT 0x0e32 -#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 -#define mmCP_CPF_BUSY_STAT2 0x0e33 -#define mmCP_CPF_BUSY_STAT2_BASE_IDX 0 -#define mmCONFIG_RESERVED_REG0 0x0e34 -#define mmCONFIG_RESERVED_REG0_BASE_IDX 0 -#define mmCONFIG_RESERVED_REG1 0x0e35 -#define mmCONFIG_RESERVED_REG1_BASE_IDX 0 -#define mmCP_CPC_HALT_HYST_COUNT 0x0e47 -#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 -#define mmCP_CE_COMPARE_COUNT 0x0e60 -#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 -#define mmCP_CE_DE_COUNT 0x0e61 -#define mmCP_CE_DE_COUNT_BASE_IDX 0 -#define mmCP_DE_CE_COUNT 0x0e62 -#define mmCP_DE_CE_COUNT_BASE_IDX 0 -#define mmCP_DE_LAST_INVAL_COUNT 0x0e63 -#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 -#define mmCP_DE_DE_COUNT 0x0e64 -#define mmCP_DE_DE_COUNT_BASE_IDX 0 -#define mmCP_STALLED_STAT3 0x0f3c -#define mmCP_STALLED_STAT3_BASE_IDX 0 -#define mmCP_STALLED_STAT1 0x0f3d -#define mmCP_STALLED_STAT1_BASE_IDX 0 -#define mmCP_STALLED_STAT2 0x0f3e -#define mmCP_STALLED_STAT2_BASE_IDX 0 -#define mmCP_BUSY_STAT 0x0f3f -#define mmCP_BUSY_STAT_BASE_IDX 0 -#define mmCP_STAT 0x0f40 -#define mmCP_STAT_BASE_IDX 0 -#define mmCP_ME_HEADER_DUMP 0x0f41 -#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 -#define mmCP_PFP_HEADER_DUMP 0x0f42 -#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 -#define mmCP_GRBM_FREE_COUNT 0x0f43 -#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 -#define mmCP_CE_HEADER_DUMP 0x0f44 -#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 -#define mmCP_PFP_INSTR_PNTR 0x0f45 -#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 -#define mmCP_ME_INSTR_PNTR 0x0f46 -#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 -#define mmCP_CE_INSTR_PNTR 0x0f47 -#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 -#define mmCP_MEC1_INSTR_PNTR 0x0f48 -#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 -#define mmCP_MEC2_INSTR_PNTR 0x0f49 -#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 -#define mmCP_CSF_STAT 0x0f54 -#define mmCP_CSF_STAT_BASE_IDX 0 -#define mmCP_MEC_CNTL 0x0f55 -#define mmCP_MEC_CNTL_BASE_IDX 0 -#define mmCP_ME_CNTL 0x0f56 -#define mmCP_ME_CNTL_BASE_IDX 0 -#define mmCP_CNTX_STAT 0x0f58 -#define mmCP_CNTX_STAT_BASE_IDX 0 -#define mmCP_ME_PREEMPTION 0x0f59 -#define mmCP_ME_PREEMPTION_BASE_IDX 0 -#define mmCP_ROQ_THRESHOLDS 0x0f5c -#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 -#define mmCP_MEQ_STQ_THRESHOLD 0x0f5d -#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 -#define mmCP_RB2_RPTR 0x0f5e -#define mmCP_RB2_RPTR_BASE_IDX 0 -#define mmCP_RB1_RPTR 0x0f5f -#define mmCP_RB1_RPTR_BASE_IDX 0 -#define mmCP_RB0_RPTR 0x0f60 -#define mmCP_RB0_RPTR_BASE_IDX 0 -#define mmCP_RB_RPTR 0x0f60 -#define mmCP_RB_RPTR_BASE_IDX 0 -#define mmCP_RB_WPTR_DELAY 0x0f61 -#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 -#define mmCP_RB_WPTR_POLL_CNTL 0x0f62 -#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmCP_ROQ1_THRESHOLDS 0x0f75 -#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 -#define mmCP_ROQ2_THRESHOLDS 0x0f76 -#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 -#define mmCP_STQ_THRESHOLDS 0x0f77 -#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 -#define mmCP_QUEUE_THRESHOLDS 0x0f78 -#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 -#define mmCP_MEQ_THRESHOLDS 0x0f79 -#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 -#define mmCP_ROQ_AVAIL 0x0f7a -#define mmCP_ROQ_AVAIL_BASE_IDX 0 -#define mmCP_STQ_AVAIL 0x0f7b -#define mmCP_STQ_AVAIL_BASE_IDX 0 -#define mmCP_ROQ2_AVAIL 0x0f7c -#define mmCP_ROQ2_AVAIL_BASE_IDX 0 -#define mmCP_MEQ_AVAIL 0x0f7d -#define mmCP_MEQ_AVAIL_BASE_IDX 0 -#define mmCP_CMD_INDEX 0x0f7e -#define mmCP_CMD_INDEX_BASE_IDX 0 -#define mmCP_CMD_DATA 0x0f7f -#define mmCP_CMD_DATA_BASE_IDX 0 -#define mmCP_ROQ_RB_STAT 0x0f80 -#define mmCP_ROQ_RB_STAT_BASE_IDX 0 -#define mmCP_ROQ_IB1_STAT 0x0f81 -#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 -#define mmCP_ROQ_IB2_STAT 0x0f82 -#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 -#define mmCP_STQ_STAT 0x0f83 -#define mmCP_STQ_STAT_BASE_IDX 0 -#define mmCP_STQ_WR_STAT 0x0f84 -#define mmCP_STQ_WR_STAT_BASE_IDX 0 -#define mmCP_MEQ_STAT 0x0f85 -#define mmCP_MEQ_STAT_BASE_IDX 0 -#define mmCP_CEQ1_AVAIL 0x0f86 -#define mmCP_CEQ1_AVAIL_BASE_IDX 0 -#define mmCP_CEQ2_AVAIL 0x0f87 -#define mmCP_CEQ2_AVAIL_BASE_IDX 0 -#define mmCP_CE_ROQ_RB_STAT 0x0f88 -#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 -#define mmCP_CE_ROQ_IB1_STAT 0x0f89 -#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 -#define mmCP_CE_ROQ_IB2_STAT 0x0f8a -#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 -#define mmCP_CE_ROQ_DB_STAT 0x0f8b -#define mmCP_CE_ROQ_DB_STAT_BASE_IDX 0 -#define mmCP_ROQ3_THRESHOLDS 0x0f8c -#define mmCP_ROQ3_THRESHOLDS_BASE_IDX 0 -#define mmCP_ROQ_DB_STAT 0x0f8d -#define mmCP_ROQ_DB_STAT_BASE_IDX 0 -#define mmCP_PRIV_VIOLATION_ADDR 0x0f9a -#define mmCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 - - -// addressBlock: gc_padec -// base address: 0x8800 -#define mmVGT_CACHE_INVALIDATION 0x0fc0 -#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 -#define mmVGT_ESGS_RING_SIZE 0x0fc1 -#define mmVGT_ESGS_RING_SIZE_BASE_IDX 0 -#define mmVGT_GSVS_RING_SIZE 0x0fc2 -#define mmVGT_GSVS_RING_SIZE_BASE_IDX 0 -#define mmVGT_TF_RING_SIZE 0x0fc3 -#define mmVGT_TF_RING_SIZE_BASE_IDX 0 -#define mmVGT_HS_OFFCHIP_PARAM 0x0fc4 -#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 0 -#define mmVGT_TF_MEMORY_BASE 0x0fc5 -#define mmVGT_TF_MEMORY_BASE_BASE_IDX 0 -#define mmVGT_TF_MEMORY_BASE_HI 0x0fc6 -#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 0 -#define mmVGT_VTX_VECT_EJECT_REG 0x0fcc -#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 -#define mmVGT_DMA_DATA_FIFO_DEPTH 0x0fcd -#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 -#define mmVGT_DMA_REQ_FIFO_DEPTH 0x0fce -#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 -#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf -#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 -#define mmVGT_LAST_COPY_STATE 0x0fd0 -#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 -#define mmVGT_FIFO_DEPTHS 0x0fd4 -#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 -#define mmVGT_GS_VERTEX_REUSE 0x0fd5 -#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 -#define mmVGT_MC_LAT_CNTL 0x0fd6 -#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 -#define mmIA_UTCL1_STATUS_2 0x0fd7 -#define mmIA_UTCL1_STATUS_2_BASE_IDX 0 -#define mmWD_CNTL_STATUS 0x0fdf -#define mmWD_CNTL_STATUS_BASE_IDX 0 -#define mmCC_GC_PRIM_CONFIG 0x0fe0 -#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 -#define mmGC_USER_PRIM_CONFIG 0x0fe1 -#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 -#define mmWD_QOS 0x0fe2 -#define mmWD_QOS_BASE_IDX 0 -#define mmWD_UTCL1_CNTL 0x0fe3 -#define mmWD_UTCL1_CNTL_BASE_IDX 0 -#define mmWD_UTCL1_STATUS 0x0fe4 -#define mmWD_UTCL1_STATUS_BASE_IDX 0 -#define mmGE_PC_CNTL 0x0fe5 -#define mmGE_PC_CNTL_BASE_IDX 0 -#define mmIA_UTCL1_CNTL 0x0fe6 -#define mmIA_UTCL1_CNTL_BASE_IDX 0 -#define mmIA_UTCL1_STATUS 0x0fe7 -#define mmIA_UTCL1_STATUS_BASE_IDX 0 -#define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 -#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 -#define mmGC_USER_SA_UNIT_DISABLE 0x0fea -#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 -#define mmVGT_SYS_CONFIG 0x1003 -#define mmVGT_SYS_CONFIG_BASE_IDX 0 -#define mmGE_PRIV_CONTROL 0x1004 -#define mmGE_PRIV_CONTROL_BASE_IDX 0 -#define mmGE_STATUS 0x1005 -#define mmGE_STATUS_BASE_IDX 0 -#define mmVGT_VS_MAX_WAVE_ID 0x1008 -#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 -#define mmVGT_GS_MAX_WAVE_ID 0x1009 -#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 -#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN1 0x100a -#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX 0 -#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 0x100b -#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX 0 -#define mmGFX_PIPE_CONTROL 0x100d -#define mmGFX_PIPE_CONTROL_BASE_IDX 0 -#define mmCC_GC_SHADER_ARRAY_CONFIG 0x100f -#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 -#define mmGC_USER_SHADER_ARRAY_CONFIG 0x1010 -#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 -#define mmVGT_DMA_PRIMITIVE_TYPE 0x1011 -#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 -#define mmVGT_DMA_CONTROL 0x1012 -#define mmVGT_DMA_CONTROL_BASE_IDX 0 -#define mmVGT_DMA_LS_HS_CONFIG 0x1013 -#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 -#define mmVGT_STRMOUT_DELAY 0x1015 -#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 -#define mmWD_BUF_RESOURCE_1 0x1016 -#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 -#define mmWD_BUF_RESOURCE_2 0x1017 -#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 -#define mmPA_CL_CNTL_STATUS 0x1024 -#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 -#define mmPA_CL_ENHANCE 0x1025 -#define mmPA_CL_ENHANCE_BASE_IDX 0 -#define mmPA_SU_CNTL_STATUS 0x1034 -#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 -#define mmPA_SC_FIFO_DEPTH_CNTL 0x1035 -#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x1060 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x1061 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x1062 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 -#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x1069 -#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 -#define mmPA_SC_BINNER_EVENT_CNTL_0 0x106c -#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 -#define mmPA_SC_BINNER_EVENT_CNTL_1 0x106d -#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 -#define mmPA_SC_BINNER_EVENT_CNTL_2 0x106e -#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 -#define mmPA_SC_BINNER_EVENT_CNTL_3 0x106f -#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 -#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x1070 -#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 -#define mmPA_SC_BINNER_PERF_CNTL_0 0x1071 -#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 -#define mmPA_SC_BINNER_PERF_CNTL_1 0x1072 -#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 -#define mmPA_SC_BINNER_PERF_CNTL_2 0x1073 -#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 -#define mmPA_SC_BINNER_PERF_CNTL_3 0x1074 -#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 -#define mmPA_SC_ENHANCE_2 0x107c -#define mmPA_SC_ENHANCE_2_BASE_IDX 0 -#define mmPA_SC_ENHANCE_INTERNAL 0x107d -#define mmPA_SC_ENHANCE_INTERNAL_BASE_IDX 0 -#define mmPA_SC_BINNER_CNTL_OVERRIDE 0x107e -#define mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 0 -#define mmPA_SC_PBB_OVERRIDE_FLAG 0x107f -#define mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 0 -#define mmPA_PH_INTERFACE_FIFO_SIZE 0x1080 -#define mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 0 -#define mmPA_PH_ENHANCE 0x1081 -#define mmPA_PH_ENHANCE_BASE_IDX 0 -#define mmPA_SC_BC_WAVE_BREAK 0x1084 -#define mmPA_SC_BC_WAVE_BREAK_BASE_IDX 0 -#define mmPA_SC_ENHANCE_3 0x1085 -#define mmPA_SC_ENHANCE_3_BASE_IDX 0 -#define mmPA_SC_FIFO_SIZE 0x1093 -#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 -#define mmPA_SC_IF_FIFO_SIZE 0x1095 -#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 -#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x1098 -#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 -#define mmPA_SIDEBAND_REQUEST_DELAYS 0x109b -#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 -#define mmPA_SC_ENHANCE 0x109c -#define mmPA_SC_ENHANCE_BASE_IDX 0 -#define mmPA_SC_ENHANCE_1 0x109d -#define mmPA_SC_ENHANCE_1_BASE_IDX 0 -#define mmPA_SC_DSM_CNTL 0x109e -#define mmPA_SC_DSM_CNTL_BASE_IDX 0 -#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x109f -#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 - - -// addressBlock: gc_sqdec -// base address: 0x8c00 -#define mmSQ_CONFIG 0x10a0 -#define mmSQ_CONFIG_BASE_IDX 0 -#define mmSQC_CONFIG 0x10a1 -#define mmSQC_CONFIG_BASE_IDX 0 -#define mmLDS_CONFIG 0x10a2 -#define mmLDS_CONFIG_BASE_IDX 0 -#define mmSQ_RANDOM_WAVE_PRI 0x10a3 -#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 -#define mmSQG_STATUS 0x10a4 -#define mmSQG_STATUS_BASE_IDX 0 -#define mmSQ_FIFO_SIZES 0x10a5 -#define mmSQ_FIFO_SIZES_BASE_IDX 0 -#define mmSQ_DSM_CNTL 0x10a6 -#define mmSQ_DSM_CNTL_BASE_IDX 0 -#define mmSQ_DSM_CNTL2 0x10a7 -#define mmSQ_DSM_CNTL2_BASE_IDX 0 -#define mmSQ_RUNTIME_CONFIG 0x10a8 -#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 -#define mmSH_MEM_BASES 0x10aa -#define mmSH_MEM_BASES_BASE_IDX 0 -#define mmSP_CONFIG 0x10ab -#define mmSP_CONFIG_BASE_IDX 0 -#define mmSQ_ARB_CONFIG 0x10ac -#define mmSQ_ARB_CONFIG_BASE_IDX 0 -#define mmSH_MEM_CONFIG 0x10ad -#define mmSH_MEM_CONFIG_BASE_IDX 0 -#define mmSQ_SHADER_TBA_LO 0x10b2 -#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 -#define mmSQ_SHADER_TBA_HI 0x10b3 -#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 -#define mmSQ_SHADER_TMA_LO 0x10b4 -#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 -#define mmSQ_SHADER_TMA_HI 0x10b5 -#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 -#define mmSQG_UTCL0_CNTL1 0x10b7 -#define mmSQG_UTCL0_CNTL1_BASE_IDX 0 -#define mmSQG_UTCL0_CNTL2 0x10b8 -#define mmSQG_UTCL0_CNTL2_BASE_IDX 0 -#define mmSQG_UTCL0_STATUS 0x10b9 -#define mmSQG_UTCL0_STATUS_BASE_IDX 0 -#define mmSQG_CONFIG 0x10ba -#define mmSQG_CONFIG_BASE_IDX 0 -#define mmCC_GC_SHADER_RATE_CONFIG 0x10bc -#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 -#define mmGC_USER_SHADER_RATE_CONFIG 0x10bd -#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 -#define mmSQ_INTERRUPT_AUTO_MASK 0x10be -#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 -#define mmSQ_INTERRUPT_MSG_CTRL 0x10bf -#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 -#define mmSQ_WATCH0_ADDR_H 0x10d0 -#define mmSQ_WATCH0_ADDR_H_BASE_IDX 0 -#define mmSQ_WATCH0_ADDR_L 0x10d1 -#define mmSQ_WATCH0_ADDR_L_BASE_IDX 0 -#define mmSQ_WATCH0_CNTL 0x10d2 -#define mmSQ_WATCH0_CNTL_BASE_IDX 0 -#define mmSQ_WATCH1_ADDR_H 0x10d3 -#define mmSQ_WATCH1_ADDR_H_BASE_IDX 0 -#define mmSQ_WATCH1_ADDR_L 0x10d4 -#define mmSQ_WATCH1_ADDR_L_BASE_IDX 0 -#define mmSQ_WATCH1_CNTL 0x10d5 -#define mmSQ_WATCH1_CNTL_BASE_IDX 0 -#define mmSQ_WATCH2_ADDR_H 0x10d6 -#define mmSQ_WATCH2_ADDR_H_BASE_IDX 0 -#define mmSQ_WATCH2_ADDR_L 0x10d7 -#define mmSQ_WATCH2_ADDR_L_BASE_IDX 0 -#define mmSQ_WATCH2_CNTL 0x10d8 -#define mmSQ_WATCH2_CNTL_BASE_IDX 0 -#define mmSQ_WATCH3_ADDR_H 0x10d9 -#define mmSQ_WATCH3_ADDR_H_BASE_IDX 0 -#define mmSQ_WATCH3_ADDR_L 0x10da -#define mmSQ_WATCH3_ADDR_L_BASE_IDX 0 -#define mmSQ_WATCH3_CNTL 0x10db -#define mmSQ_WATCH3_CNTL_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_BUF0_BASE 0x10e0 -#define mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_BUF0_SIZE 0x10e1 -#define mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_BUF1_BASE 0x10e2 -#define mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_BUF1_SIZE 0x10e3 -#define mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_WPTR 0x10e4 -#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_MASK 0x10e5 -#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x10e6 -#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_CTRL 0x10e7 -#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_STATUS 0x10e8 -#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_DROPPED_CNTR 0x10e9 -#define mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x10eb -#define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x10ec -#define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x10ed -#define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x10ee -#define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 0 -#define mmSQ_THREAD_TRACE_STATUS2 0x10ef -#define mmSQ_THREAD_TRACE_STATUS2_BASE_IDX 0 -#define mmSQ_IND_INDEX 0x1118 -#define mmSQ_IND_INDEX_BASE_IDX 0 -#define mmSQ_IND_DATA 0x1119 -#define mmSQ_IND_DATA_BASE_IDX 0 -#define mmSQ_CMD 0x111b -#define mmSQ_CMD_BASE_IDX 0 -#define mmSQ_TIME_HI 0x111c -#define mmSQ_TIME_HI_BASE_IDX 0 -#define mmSQ_TIME_LO 0x111d -#define mmSQ_TIME_LO_BASE_IDX 0 -#define mmSQ_LB_CTR_CTRL 0x1138 -#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 -#define mmSQ_LB_DATA0 0x1139 -#define mmSQ_LB_DATA0_BASE_IDX 0 -#define mmSQ_LB_DATA1 0x113a -#define mmSQ_LB_DATA1_BASE_IDX 0 -#define mmSQ_LB_DATA2 0x113b -#define mmSQ_LB_DATA2_BASE_IDX 0 -#define mmSQ_LB_DATA3 0x113c -#define mmSQ_LB_DATA3_BASE_IDX 0 -#define mmSQ_LB_CTR_SEL0 0x113d -#define mmSQ_LB_CTR_SEL0_BASE_IDX 0 -#define mmSQ_LB_CTR_SEL1 0x113e -#define mmSQ_LB_CTR_SEL1_BASE_IDX 0 -#define mmSQ_EDC_CNT 0x1146 -#define mmSQ_EDC_CNT_BASE_IDX 0 -#define mmSQ_EDC_FUE_CNTL 0x1147 -#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0 -#define mmSQ_WREXEC_EXEC_HI 0x1151 -#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 -#define mmSQ_WREXEC_EXEC_LO 0x1151 -#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 -#define mmSQC_ICACHE_UTCL0_CNTL1 0x1173 -#define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX 0 -#define mmSQC_ICACHE_UTCL0_CNTL2 0x1174 -#define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX 0 -#define mmSQC_DCACHE_UTCL0_CNTL1 0x1175 -#define mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX 0 -#define mmSQC_DCACHE_UTCL0_CNTL2 0x1176 -#define mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX 0 -#define mmSQC_ICACHE_UTCL0_STATUS 0x1177 -#define mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX 0 -#define mmSQC_DCACHE_UTCL0_STATUS 0x1178 -#define mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX 0 - - -// addressBlock: gc_shsdec -// base address: 0x9000 -#define mmSX_DEBUG_1 0x11b8 -#define mmSX_DEBUG_1_BASE_IDX 0 -#define mmSPI_PS_MAX_WAVE_ID 0x11da -#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 -#define mmSPI_START_PHASE 0x11db -#define mmSPI_START_PHASE_BASE_IDX 0 -#define mmSPI_GFX_CNTL 0x11dc -#define mmSPI_GFX_CNTL_BASE_IDX 0 -#define mmSPI_DSM_CNTL 0x11e3 -#define mmSPI_DSM_CNTL_BASE_IDX 0 -#define mmSPI_DSM_CNTL2 0x11e4 -#define mmSPI_DSM_CNTL2_BASE_IDX 0 -#define mmSPI_EDC_CNT 0x11e5 -#define mmSPI_EDC_CNT_BASE_IDX 0 -#define mmSPI_USER_ACCUM_VMID_CNTL 0x11eb -#define mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 -#define mmSPI_CONFIG_CNTL 0x11ec -#define mmSPI_CONFIG_CNTL_BASE_IDX 0 -#define mmSPI_WAVE_LIMIT_CNTL 0x11ed -#define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 0 -#define mmSPI_CONFIG_CNTL_2 0x11ee -#define mmSPI_CONFIG_CNTL_2_BASE_IDX 0 -#define mmSPI_CONFIG_CNTL_1 0x11ef -#define mmSPI_CONFIG_CNTL_1_BASE_IDX 0 -#define mmSPI_CONFIG_PS_CU_EN 0x11f2 -#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_CNTL 0x124a -#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_0 0x124b -#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_1 0x124c -#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_2 0x124d -#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_3 0x124e -#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_4 0x124f -#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_LIMIT_5 0x1250 -#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_0 0x1255 -#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_1 0x1256 -#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_2 0x1257 -#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_4 0x1259 -#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_6 0x125b -#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_7 0x125c -#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_8 0x125d -#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_9 0x125e -#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_11 0x1260 -#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_13 0x1262 -#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_14 0x1263 -#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_15 0x1264 -#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_16 0x1265 -#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_17 0x1266 -#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_18 0x1267 -#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_19 0x1268 -#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_20 0x1269 -#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 -#define mmSPI_WF_LIFETIME_STATUS_21 0x126b -#define mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 -#define mmSPI_LB_CTR_CTRL 0x1274 -#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 -#define mmSPI_LB_WGP_MASK 0x1275 -#define mmSPI_LB_WGP_MASK_BASE_IDX 0 -#define mmSPI_LB_DATA_REG 0x1276 -#define mmSPI_LB_DATA_REG_BASE_IDX 0 -#define mmSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 -#define mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 -#define mmSPI_GDS_CREDITS 0x1278 -#define mmSPI_GDS_CREDITS_BASE_IDX 0 -#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x1279 -#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 -#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x127b -#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 -#define mmSPI_LB_DATA_WAVES 0x1284 -#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 -#define mmSPI_LB_DATA_PERWGP_WAVE_HSGS 0x1285 -#define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX 0 -#define mmSPI_LB_DATA_PERWGP_WAVE_VSPS 0x1286 -#define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX 0 -#define mmSPI_LB_DATA_PERWGP_WAVE_CS 0x1287 -#define mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX 0 -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 - - -// addressBlock: gc_tpdec -// base address: 0x9400 -#define mmTD_STATUS 0x12c6 -#define mmTD_STATUS_BASE_IDX 0 -#define mmTD_DSM_CNTL 0x12cf -#define mmTD_DSM_CNTL_BASE_IDX 0 -#define mmTD_DSM_CNTL2 0x12d0 -#define mmTD_DSM_CNTL2_BASE_IDX 0 -#define mmTD_SCRATCH 0x12d3 -#define mmTD_SCRATCH_BASE_IDX 0 -#define mmTA_CNTL 0x12e1 -#define mmTA_CNTL_BASE_IDX 0 -#define mmTA_RESERVED_010C 0x12e3 -#define mmTA_RESERVED_010C_BASE_IDX 0 -#define mmTA_STATUS 0x12e8 -#define mmTA_STATUS_BASE_IDX 0 -#define mmTA_SCRATCH 0x1304 -#define mmTA_SCRATCH_BASE_IDX 0 - - -// addressBlock: gc_gdsdec -// base address: 0x9700 -#define mmGDS_CONFIG 0x1360 -#define mmGDS_CONFIG_BASE_IDX 0 -#define mmGDS_CNTL_STATUS 0x1361 -#define mmGDS_CNTL_STATUS_BASE_IDX 0 -#define mmGDS_ENHANCE 0x1362 -#define mmGDS_ENHANCE_BASE_IDX 0 -#define mmGDS_PROTECTION_FAULT 0x1363 -#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 -#define mmGDS_VM_PROTECTION_FAULT 0x1364 -#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 -#define mmGDS_EDC_CNT 0x1365 -#define mmGDS_EDC_CNT_BASE_IDX 0 -#define mmGDS_EDC_GRBM_CNT 0x1366 -#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 -#define mmGDS_EDC_OA_DED 0x1367 -#define mmGDS_EDC_OA_DED_BASE_IDX 0 -#define mmGDS_DSM_CNTL 0x136a -#define mmGDS_DSM_CNTL_BASE_IDX 0 -#define mmGDS_EDC_OA_PHY_CNT 0x136b -#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 -#define mmGDS_EDC_OA_PIPE_CNT 0x136c -#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 -#define mmGDS_DSM_CNTL2 0x136d -#define mmGDS_DSM_CNTL2_BASE_IDX 0 -#define mmGDS_WD_GDS_CSB 0x136e -#define mmGDS_WD_GDS_CSB_BASE_IDX 0 - - -// addressBlock: gc_rbdec -// base address: 0x9800 -#define mmDB_DEBUG 0x13ac -#define mmDB_DEBUG_BASE_IDX 0 -#define mmDB_DEBUG2 0x13ad -#define mmDB_DEBUG2_BASE_IDX 0 -#define mmDB_DEBUG3 0x13ae -#define mmDB_DEBUG3_BASE_IDX 0 -#define mmDB_DEBUG4 0x13af -#define mmDB_DEBUG4_BASE_IDX 0 -#define mmDB_ETILE_STUTTER_CONTROL 0x13b0 -#define mmDB_ETILE_STUTTER_CONTROL_BASE_IDX 0 -#define mmDB_LTILE_STUTTER_CONTROL 0x13b1 -#define mmDB_LTILE_STUTTER_CONTROL_BASE_IDX 0 -#define mmDB_EQUAD_STUTTER_CONTROL 0x13b2 -#define mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0 -#define mmDB_LQUAD_STUTTER_CONTROL 0x13b3 -#define mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0 -#define mmDB_CREDIT_LIMIT 0x13b4 -#define mmDB_CREDIT_LIMIT_BASE_IDX 0 -#define mmDB_WATERMARKS 0x13b5 -#define mmDB_WATERMARKS_BASE_IDX 0 -#define mmDB_SUBTILE_CONTROL 0x13b6 -#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 -#define mmDB_FREE_CACHELINES 0x13b7 -#define mmDB_FREE_CACHELINES_BASE_IDX 0 -#define mmDB_FIFO_DEPTH1 0x13b8 -#define mmDB_FIFO_DEPTH1_BASE_IDX 0 -#define mmDB_FIFO_DEPTH2 0x13b9 -#define mmDB_FIFO_DEPTH2_BASE_IDX 0 -#define mmDB_LAST_OF_BURST_CONFIG 0x13ba -#define mmDB_LAST_OF_BURST_CONFIG_BASE_IDX 0 -#define mmDB_RING_CONTROL 0x13bb -#define mmDB_RING_CONTROL_BASE_IDX 0 -#define mmDB_MEM_ARB_WATERMARKS 0x13bc -#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 -#define mmDB_FIFO_DEPTH3 0x13bd -#define mmDB_FIFO_DEPTH3_BASE_IDX 0 -#define mmDB_RMI_BC_GL2_CACHE_CONTROL 0x13be -#define mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX 0 -#define mmDB_EXCEPTION_CONTROL 0x13bf -#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 -#define mmDB_DFSM_CONFIG 0x13d0 -#define mmDB_DFSM_CONFIG_BASE_IDX 0 -#define mmDB_DEBUG5 0x13d1 -#define mmDB_DEBUG5_BASE_IDX 0 -#define mmDB_DFSM_TILES_IN_FLIGHT 0x13d2 -#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 -#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x13d3 -#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 -#define mmDB_DFSM_WATCHDOG 0x13d4 -#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 -#define mmDB_DFSM_FLUSH_ENABLE 0x13d5 -#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 -#define mmDB_DFSM_FLUSH_AUX_EVENT 0x13d6 -#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 -#define mmDB_FGCG_SRAMS_CLK_CTRL 0x13d7 -#define mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 -#define mmDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 -#define mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 -#define mmCC_RB_REDUNDANCY 0x13dc -#define mmCC_RB_REDUNDANCY_BASE_IDX 0 -#define mmCC_RB_BACKEND_DISABLE 0x13dd -#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 -#define mmGB_ADDR_CONFIG 0x13de -#define mmGB_ADDR_CONFIG_BASE_IDX 0 -#define mmGB_BACKEND_MAP 0x13df -#define mmGB_BACKEND_MAP_BASE_IDX 0 -#define mmGB_GPU_ID 0x13e0 -#define mmGB_GPU_ID_BASE_IDX 0 -#define mmCC_RB_DAISY_CHAIN 0x13e1 -#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 -#define mmGB_ADDR_CONFIG_READ 0x13e2 -#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmCB_HW_CONTROL_4 0x1422 -#define mmCB_HW_CONTROL_4_BASE_IDX 0 -#define mmCB_HW_CONTROL_3 0x1423 -#define mmCB_HW_CONTROL_3_BASE_IDX 0 -#define mmCB_HW_CONTROL 0x1424 -#define mmCB_HW_CONTROL_BASE_IDX 0 -#define mmCB_HW_CONTROL_1 0x1425 -#define mmCB_HW_CONTROL_1_BASE_IDX 0 -#define mmCB_HW_CONTROL_2 0x1426 -#define mmCB_HW_CONTROL_2_BASE_IDX 0 -#define mmCB_DCC_CONFIG 0x1427 -#define mmCB_DCC_CONFIG_BASE_IDX 0 -#define mmCB_HW_MEM_ARBITER_RD 0x1428 -#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 -#define mmCB_HW_MEM_ARBITER_WR 0x1429 -#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 -#define mmCB_RMI_BC_GL2_CACHE_CONTROL 0x142a -#define mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX 0 -#define mmCB_STUTTER_CONTROL_CMASK_RDLAT 0x142b -#define mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX 0 -#define mmCB_STUTTER_CONTROL_FMASK_RDLAT 0x142c -#define mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX 0 -#define mmCB_STUTTER_CONTROL_COLOR_RDLAT 0x142d -#define mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX 0 -#define mmCB_CACHE_EVICT_POINTS 0x142e -#define mmCB_CACHE_EVICT_POINTS_BASE_IDX 0 -#define mmGC_USER_RB_REDUNDANCY 0x147e -#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 -#define mmGC_USER_RB_BACKEND_DISABLE 0x147f -#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 - - -// addressBlock: gc_gceadec2 -// base address: 0x9c00 -#define mmGCEA_MISC 0x14a2 -#define mmGCEA_MISC_BASE_IDX 0 -#define mmGCEA_LATENCY_SAMPLING 0x14a3 -#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0 -#define mmGCEA_DSM_CNTL 0x14b4 -#define mmGCEA_DSM_CNTL_BASE_IDX 0 -#define mmGCEA_DSM_CNTLA 0x14b5 -#define mmGCEA_DSM_CNTLA_BASE_IDX 0 -#define mmGCEA_DSM_CNTLB 0x14b6 -#define mmGCEA_DSM_CNTLB_BASE_IDX 0 -#define mmGCEA_DSM_CNTL2 0x14b7 -#define mmGCEA_DSM_CNTL2_BASE_IDX 0 -#define mmGCEA_DSM_CNTL2A 0x14b8 -#define mmGCEA_DSM_CNTL2A_BASE_IDX 0 -#define mmGCEA_DSM_CNTL2B 0x14b9 -#define mmGCEA_DSM_CNTL2B_BASE_IDX 0 -#define mmGCEA_GL2C_XBR_CREDITS 0x14ba -#define mmGCEA_GL2C_XBR_CREDITS_BASE_IDX 0 -#define mmGCEA_GL2C_XBR_MAXBURST 0x14bb -#define mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0 -#define mmGCEA_PROBE_CNTL 0x14bc -#define mmGCEA_PROBE_CNTL_BASE_IDX 0 -#define mmGCEA_PROBE_MAP 0x14bd -#define mmGCEA_PROBE_MAP_BASE_IDX 0 -#define mmGCEA_ERR_STATUS 0x14be -#define mmGCEA_ERR_STATUS_BASE_IDX 0 -#define mmGCEA_MISC2 0x14bf -#define mmGCEA_MISC2_BASE_IDX 0 - - -// addressBlock: gc_spipdec2 -// base address: 0x9c80 -#define mmSPI_PQEV_CTRL 0x14c0 -#define mmSPI_PQEV_CTRL_BASE_IDX 0 -#define mmSPI_EXP_THROTTLE_CTRL 0x14c3 -#define mmSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 - - -// addressBlock: gc_gceadec3 -// base address: 0x9dc0 -#define mmGCEA_RRET_MEM_RESERVE 0x1518 -#define mmGCEA_RRET_MEM_RESERVE_BASE_IDX 0 - - -// addressBlock: gc_rmi_rmidec -// base address: 0x9e00 -#define mmRMI_GENERAL_CNTL 0x1520 -#define mmRMI_GENERAL_CNTL_BASE_IDX 0 -#define mmRMI_GENERAL_CNTL1 0x1521 -#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 -#define mmRMI_GENERAL_STATUS 0x1522 -#define mmRMI_GENERAL_STATUS_BASE_IDX 0 -#define mmRMI_SUBBLOCK_STATUS0 0x1523 -#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 -#define mmRMI_SUBBLOCK_STATUS1 0x1524 -#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 -#define mmRMI_SUBBLOCK_STATUS2 0x1525 -#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 -#define mmRMI_SUBBLOCK_STATUS3 0x1526 -#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 -#define mmRMI_XBAR_CONFIG 0x1527 -#define mmRMI_XBAR_CONFIG_BASE_IDX 0 -#define mmRMI_PROBE_POP_LOGIC_CNTL 0x1528 -#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 -#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x1529 -#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 -#define mmRMI_DEMUX_CNTL 0x152a -#define mmRMI_DEMUX_CNTL_BASE_IDX 0 -#define mmRMI_UTCL1_CNTL1 0x152b -#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 -#define mmRMI_UTCL1_CNTL2 0x152c -#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 -#define mmRMI_UTC_UNIT_CONFIG 0x152d -#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 -#define mmRMI_TCIW_FORMATTER0_CNTL 0x152e -#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 -#define mmRMI_TCIW_FORMATTER1_CNTL 0x152f -#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 -#define mmRMI_SCOREBOARD_CNTL 0x1530 -#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 -#define mmRMI_SCOREBOARD_STATUS0 0x1531 -#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 -#define mmRMI_SCOREBOARD_STATUS1 0x1532 -#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 -#define mmRMI_SCOREBOARD_STATUS2 0x1533 -#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 -#define mmRMI_XBAR_ARBITER_CONFIG 0x1534 -#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 -#define mmRMI_XBAR_ARBITER_CONFIG_1 0x1535 -#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 -#define mmRMI_CLOCK_CNTRL 0x1536 -#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 -#define mmRMI_UTCL1_STATUS 0x1537 -#define mmRMI_UTCL1_STATUS_BASE_IDX 0 -#define mmRMI_RB_GLX_CID_MAP 0x1538 -#define mmRMI_RB_GLX_CID_MAP_BASE_IDX 0 -#define mmRMI_SPARE 0x153f -#define mmRMI_SPARE_BASE_IDX 0 -#define mmRMI_SPARE_1 0x1540 -#define mmRMI_SPARE_1_BASE_IDX 0 -#define mmRMI_SPARE_2 0x1541 -#define mmRMI_SPARE_2_BASE_IDX 0 -#define mmCC_RMI_REDUNDANCY 0x1542 -#define mmCC_RMI_REDUNDANCY_BASE_IDX 0 -#define mmGC_USER_RMI_REDUNDANCY 0x1543 -#define mmGC_USER_RMI_REDUNDANCY_BASE_IDX 0 - - -// addressBlock: gc_dbgu_gfx_dbgudec -// base address: 0x9f00 - - -// addressBlock: gc_pmmdec -// base address: 0x9f80 -#define mmGCR_GENERAL_CNTL 0x1580 -#define mmGCR_GENERAL_CNTL_BASE_IDX 0 -#define mmGCR_CMD_STATUS 0x1582 -#define mmGCR_CMD_STATUS_BASE_IDX 0 -#define mmGCR_SPARE 0x1583 -#define mmGCR_SPARE_BASE_IDX 0 -#define mmPMM_GENERAL_CNTL 0x1585 -#define mmPMM_GENERAL_CNTL_BASE_IDX 0 -#define mmGCR_PIO_CNTL 0x1586 -#define mmGCR_PIO_CNTL_BASE_IDX 0 -#define mmGCR_PIO_DATA 0x1587 -#define mmGCR_PIO_DATA_BASE_IDX 0 - - -// addressBlock: gc_utcl1dec -// base address: 0x9fa0 -#define mmUTCL1_CTRL 0x1588 -#define mmUTCL1_CTRL_BASE_IDX 0 -#define mmUTCL1_ALOG 0x1589 -#define mmUTCL1_ALOG_BASE_IDX 0 -#define mmUTCL1_UTCL0_INVREQ_DISABLE 0x158a -#define mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 0 -#define mmGCRD_SA_TARGETS_DISABLE 0x158b -#define mmGCRD_SA_TARGETS_DISABLE_BASE_IDX 0 -#define mmUTCL1_STATUS 0x158c -#define mmUTCL1_STATUS_BASE_IDX 0 - - -// addressBlock: gc_gcvml2pfdec -// base address: 0xa070 -#define mmGCVM_L2_CNTL 0x15bc -#define mmGCVM_L2_CNTL_BASE_IDX 0 -#define mmGCVM_L2_CNTL2 0x15bd -#define mmGCVM_L2_CNTL2_BASE_IDX 0 -#define mmGCVM_L2_CNTL3 0x15be -#define mmGCVM_L2_CNTL3_BASE_IDX 0 -#define mmGCVM_L2_STATUS 0x15bf -#define mmGCVM_L2_STATUS_BASE_IDX 0 -#define mmGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c0 -#define mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 -#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c1 -#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15c2 -#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_CNTL 0x15c3 -#define mmGCVM_INVALIDATE_CNTL_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_CNTL 0x15c4 -#define mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_CNTL2 0x15c5 -#define mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15c6 -#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15c7 -#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_STATUS 0x15c8 -#define mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15c9 -#define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ca -#define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15cb -#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc -#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_DEBUG 0x15cd -#define mmGCVM_DEBUG_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15d0 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15d1 -#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15d2 -#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15d3 -#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 -#define mmGCVM_L2_CNTL4 0x15d4 -#define mmGCVM_L2_CNTL4_BASE_IDX 0 -#define mmGCVM_L2_MM_GROUP_RT_CLASSES 0x15d5 -#define mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 -#define mmGCVM_L2_BANK_SELECT_RESERVED_CID 0x15d6 -#define mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 -#define mmGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15d7 -#define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 -#define mmGCVM_L2_CACHE_PARITY_CNTL 0x15d8 -#define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 -#define mmGCVM_L2_IH_LOG_CNTL 0x15d9 -#define mmGCVM_L2_IH_LOG_CNTL_BASE_IDX 0 -#define mmGCVM_L2_CNTL5 0x15dc -#define mmGCVM_L2_CNTL5_BASE_IDX 0 -#define mmGCVM_L2_GCR_CNTL 0x15dd -#define mmGCVM_L2_GCR_CNTL_BASE_IDX 0 -#define mmGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15de -#define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 -#define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15df -#define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 -#define mmGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15e0 -#define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 -#define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15e1 -#define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 -#define mmGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15e3 -#define mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 -#define mmGCVM_L2_PTE_CACHE_DUMP_READ 0x15e4 -#define mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 - - -// addressBlock: gc_gcvml2vcdec -// base address: 0xa170 -#define mmGCVM_CONTEXT0_CNTL 0x15fc -#define mmGCVM_CONTEXT0_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT1_CNTL 0x15fd -#define mmGCVM_CONTEXT1_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT2_CNTL 0x15fe -#define mmGCVM_CONTEXT2_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT3_CNTL 0x15ff -#define mmGCVM_CONTEXT3_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT4_CNTL 0x1600 -#define mmGCVM_CONTEXT4_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT5_CNTL 0x1601 -#define mmGCVM_CONTEXT5_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT6_CNTL 0x1602 -#define mmGCVM_CONTEXT6_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT7_CNTL 0x1603 -#define mmGCVM_CONTEXT7_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT8_CNTL 0x1604 -#define mmGCVM_CONTEXT8_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT9_CNTL 0x1605 -#define mmGCVM_CONTEXT9_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT10_CNTL 0x1606 -#define mmGCVM_CONTEXT10_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT11_CNTL 0x1607 -#define mmGCVM_CONTEXT11_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT12_CNTL 0x1608 -#define mmGCVM_CONTEXT12_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT13_CNTL 0x1609 -#define mmGCVM_CONTEXT13_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT14_CNTL 0x160a -#define mmGCVM_CONTEXT14_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXT15_CNTL 0x160b -#define mmGCVM_CONTEXT15_CNTL_BASE_IDX 0 -#define mmGCVM_CONTEXTS_DISABLE 0x160c -#define mmGCVM_CONTEXTS_DISABLE_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG0_SEM 0x160d -#define mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG1_SEM 0x160e -#define mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG2_SEM 0x160f -#define mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG3_SEM 0x1610 -#define mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG4_SEM 0x1611 -#define mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG5_SEM 0x1612 -#define mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG6_SEM 0x1613 -#define mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG7_SEM 0x1614 -#define mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG8_SEM 0x1615 -#define mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG9_SEM 0x1616 -#define mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG10_SEM 0x1617 -#define mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG11_SEM 0x1618 -#define mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG12_SEM 0x1619 -#define mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG13_SEM 0x161a -#define mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG14_SEM 0x161b -#define mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG15_SEM 0x161c -#define mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG16_SEM 0x161d -#define mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG17_SEM 0x161e -#define mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG0_REQ 0x161f -#define mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG1_REQ 0x1620 -#define mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG2_REQ 0x1621 -#define mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG3_REQ 0x1622 -#define mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG4_REQ 0x1623 -#define mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG5_REQ 0x1624 -#define mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG6_REQ 0x1625 -#define mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG7_REQ 0x1626 -#define mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG8_REQ 0x1627 -#define mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG9_REQ 0x1628 -#define mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG10_REQ 0x1629 -#define mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG11_REQ 0x162a -#define mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG12_REQ 0x162b -#define mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG13_REQ 0x162c -#define mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG14_REQ 0x162d -#define mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG15_REQ 0x162e -#define mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG16_REQ 0x162f -#define mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG17_REQ 0x1630 -#define mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG0_ACK 0x1631 -#define mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG1_ACK 0x1632 -#define mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG2_ACK 0x1633 -#define mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG3_ACK 0x1634 -#define mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG4_ACK 0x1635 -#define mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG5_ACK 0x1636 -#define mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG6_ACK 0x1637 -#define mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG7_ACK 0x1638 -#define mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG8_ACK 0x1639 -#define mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG9_ACK 0x163a -#define mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG10_ACK 0x163b -#define mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG11_ACK 0x163c -#define mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG12_ACK 0x163d -#define mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG13_ACK 0x163e -#define mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG14_ACK 0x163f -#define mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG15_ACK 0x1640 -#define mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG16_ACK 0x1641 -#define mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG17_ACK 0x1642 -#define mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x1643 -#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x1644 -#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x1645 -#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x1646 -#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x1647 -#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x1648 -#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x1649 -#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x164a -#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x164b -#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x164c -#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x164d -#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x164e -#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x164f -#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x1650 -#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x1651 -#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x1652 -#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x1653 -#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x1654 -#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x1655 -#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x1656 -#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x1657 -#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x1658 -#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x1659 -#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x165a -#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x165b -#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x165c -#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x165d -#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x165e -#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x165f -#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x1660 -#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x1661 -#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x1662 -#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x1663 -#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x1664 -#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x1665 -#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 -#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x1666 -#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x1667 -#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x1668 -#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x1669 -#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x166a -#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x166b -#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x166c -#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x166d -#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x166e -#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x166f -#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x1670 -#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x1671 -#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x1672 -#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x1673 -#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1674 -#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1675 -#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x1676 -#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x1677 -#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x1678 -#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x1679 -#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x167a -#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x167b -#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x167c -#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x167d -#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x167e -#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x167f -#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x1680 -#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x1681 -#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x1682 -#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x1683 -#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x1684 -#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x1685 -#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x1686 -#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x1687 -#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x1688 -#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x1689 -#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x168a -#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x168b -#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x168c -#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x168d -#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x168e -#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x168f -#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x1690 -#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x1691 -#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x1692 -#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x1693 -#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x1694 -#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x1695 -#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x1696 -#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x1697 -#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x1698 -#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x1699 -#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x169a -#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x169b -#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x169c -#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x169d -#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x169e -#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x169f -#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x16a0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x16a1 -#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x16a2 -#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x16a3 -#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x16a4 -#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x16a5 -#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x16a6 -#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x16a7 -#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x16a8 -#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x16a9 -#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x16aa -#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x16ab -#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x16ac -#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x16ad -#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x16ae -#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x16af -#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x16b0 -#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x16b1 -#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x16b2 -#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x16b3 -#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x16b4 -#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x16b5 -#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x16b6 -#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x16b7 -#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x16b8 -#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x16b9 -#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x16ba -#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x16bb -#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x16bc -#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x16bd -#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x16be -#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x16bf -#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x16c0 -#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x16c1 -#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x16c2 -#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x16c3 -#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x16c4 -#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x16c5 -#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x16c6 -#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16c7 -#define mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16c8 -#define mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16c9 -#define mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16ca -#define mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16cb -#define mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16cc -#define mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16cd -#define mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16ce -#define mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16cf -#define mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d0 -#define mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d1 -#define mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d2 -#define mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d3 -#define mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d4 -#define mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d5 -#define mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d6 -#define mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16d7 -#define mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 - - -// addressBlock: gc_gcvmsharedpfdec -// base address: 0xa500 -#define mmGCMC_VM_NB_MMIOBASE 0x16e0 -#define mmGCMC_VM_NB_MMIOBASE_BASE_IDX 0 -#define mmGCMC_VM_NB_MMIOLIMIT 0x16e1 -#define mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX 0 -#define mmGCMC_VM_NB_PCI_CTRL 0x16e2 -#define mmGCMC_VM_NB_PCI_CTRL_BASE_IDX 0 -#define mmGCMC_VM_NB_PCI_ARB 0x16e3 -#define mmGCMC_VM_NB_PCI_ARB_BASE_IDX 0 -#define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x16e4 -#define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 -#define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x16e5 -#define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 -#define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x16e6 -#define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 -#define mmGCMC_VM_FB_OFFSET 0x16e7 -#define mmGCMC_VM_FB_OFFSET_BASE_IDX 0 -#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x16e8 -#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 -#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x16e9 -#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 -#define mmGCMC_VM_STEERING 0x16ea -#define mmGCMC_VM_STEERING_BASE_IDX 0 -#define mmGCMC_SHARED_VIRT_RESET_REQ 0x16eb -#define mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 -#define mmGCMC_MEM_POWER_LS 0x16ec -#define mmGCMC_MEM_POWER_LS_BASE_IDX 0 -#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x16ed -#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 -#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x16ee -#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 -#define mmGCMC_VM_APT_CNTL 0x16ef -#define mmGCMC_VM_APT_CNTL_BASE_IDX 0 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x16f0 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_START 0x16f1 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_END 0x16f2 -#define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 -#define mmGCMC_SHARED_ACTIVE_FCN_ID 0x16f4 -#define mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmGCMC_SHARED_VIRT_RESET_REQ2 0x16f5 -#define mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0 -#define mmGCMC_VM_XGMI_LFB_CNTL 0x16f7 -#define mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 -#define mmGCMC_VM_XGMI_LFB_SIZE 0x16f8 -#define mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 -#define mmGCMC_VM_FB_NOALLOC_CNTL 0x16f9 -#define mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 -#define mmGCUTCL2_HARVEST_BYPASS_GROUPS 0x16fa -#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 - - -// addressBlock: gc_gcvmsharedvcdec -// base address: 0xa570 -#define mmGCMC_VM_FB_LOCATION_BASE 0x16fc -#define mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0 -#define mmGCMC_VM_FB_LOCATION_TOP 0x16fd -#define mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0 -#define mmGCMC_VM_AGP_TOP 0x16fe -#define mmGCMC_VM_AGP_TOP_BASE_IDX 0 -#define mmGCMC_VM_AGP_BOT 0x16ff -#define mmGCMC_VM_AGP_BOT_BASE_IDX 0 -#define mmGCMC_VM_AGP_BASE 0x1700 -#define mmGCMC_VM_AGP_BASE_BASE_IDX 0 -#define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x1701 -#define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 -#define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x1702 -#define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 -#define mmGCMC_VM_MX_L1_TLB_CNTL 0x1703 -#define mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 - - -// addressBlock: gc_gceadec -// base address: 0xa800 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x17a4 -#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 -#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x17a5 -#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 -#define mmGCEA_DRAM_RD_LAZY 0x17a6 -#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0 -#define mmGCEA_DRAM_WR_LAZY 0x17a7 -#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0 -#define mmGCEA_DRAM_RD_CAM_CNTL 0x17a8 -#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 -#define mmGCEA_DRAM_WR_CAM_CNTL 0x17a9 -#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 -#define mmGCEA_DRAM_PAGE_BURST 0x17aa -#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_AGE 0x17ab -#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_AGE 0x17ac -#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_QUEUING 0x17ad -#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_QUEUING 0x17ae -#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_FIXED 0x17af -#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_FIXED 0x17b0 -#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_URGENCY 0x17b1 -#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_URGENCY 0x17b2 -#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8 -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x187d -#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x187e -#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x187f -#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x1880 -#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define mmGCEA_IO_RD_COMBINE_FLUSH 0x1881 -#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 -#define mmGCEA_IO_WR_COMBINE_FLUSH 0x1882 -#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 -#define mmGCEA_IO_GROUP_BURST 0x1883 -#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_AGE 0x1884 -#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_AGE 0x1885 -#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_QUEUING 0x1886 -#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_QUEUING 0x1887 -#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_FIXED 0x1888 -#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_FIXED 0x1889 -#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_URGENCY 0x188a -#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_URGENCY 0x188b -#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c -#define mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d -#define mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x188e -#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x188f -#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x1890 -#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x1891 -#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x1892 -#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x1893 -#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 - - -// addressBlock: gc_tcdec -// base address: 0xac00 -#define mmTCP_INVALIDATE 0x18a0 -#define mmTCP_INVALIDATE_BASE_IDX 0 -#define mmTCP_STATUS 0x18a1 -#define mmTCP_STATUS_BASE_IDX 0 -#define mmTCP_EDC_CNT 0x18b7 -#define mmTCP_EDC_CNT_BASE_IDX 0 -#define mmTCI_STATUS 0x1901 -#define mmTCI_STATUS_BASE_IDX 0 -#define mmTCI_CNTL_1 0x1902 -#define mmTCI_CNTL_1_BASE_IDX 0 -#define mmTCI_CNTL_2 0x1903 -#define mmTCI_CNTL_2_BASE_IDX 0 - - -// addressBlock: gc_shdec -// base address: 0xb000 -#define mmSPI_SHADER_PGM_RSRC4_PS 0x19a1 -#define mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_CHKSUM_PS 0x19a6 -#define mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC3_PS 0x19a7 -#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_PS 0x19a8 -#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_PS 0x19a9 -#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC1_PS 0x19aa -#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC2_PS 0x19ab -#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_0 0x19ac -#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_1 0x19ad -#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_2 0x19ae -#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_3 0x19af -#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_4 0x19b0 -#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_5 0x19b1 -#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_6 0x19b2 -#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_7 0x19b3 -#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_8 0x19b4 -#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_9 0x19b5 -#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_10 0x19b6 -#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_11 0x19b7 -#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_12 0x19b8 -#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_13 0x19b9 -#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_14 0x19ba -#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_15 0x19bb -#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_16 0x19bc -#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_17 0x19bd -#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_18 0x19be -#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_19 0x19bf -#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_20 0x19c0 -#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_21 0x19c1 -#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_22 0x19c2 -#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_23 0x19c3 -#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_24 0x19c4 -#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_25 0x19c5 -#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_26 0x19c6 -#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_27 0x19c7 -#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_28 0x19c8 -#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_29 0x19c9 -#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_30 0x19ca -#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_PS_31 0x19cb -#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 -#define mmSPI_SHADER_REQ_CTRL_PS 0x19d0 -#define mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_PS_0 0x19d2 -#define mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_PS_1 0x19d3 -#define mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_PS_2 0x19d4 -#define mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_PS_3 0x19d5 -#define mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC4_VS 0x19e1 -#define mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_CHKSUM_VS 0x19e5 -#define mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC3_VS 0x19e6 -#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 -#define mmSPI_SHADER_LATE_ALLOC_VS 0x19e7 -#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_VS 0x19e8 -#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_VS 0x19e9 -#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC1_VS 0x19ea -#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC2_VS 0x19eb -#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_0 0x19ec -#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_1 0x19ed -#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_2 0x19ee -#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_3 0x19ef -#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_4 0x19f0 -#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_5 0x19f1 -#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_6 0x19f2 -#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_7 0x19f3 -#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_8 0x19f4 -#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_9 0x19f5 -#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_10 0x19f6 -#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_11 0x19f7 -#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_12 0x19f8 -#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_13 0x19f9 -#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_14 0x19fa -#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_15 0x19fb -#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_16 0x19fc -#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_17 0x19fd -#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_18 0x19fe -#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_19 0x19ff -#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_20 0x1a00 -#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_21 0x1a01 -#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_22 0x1a02 -#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_23 0x1a03 -#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_24 0x1a04 -#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_25 0x1a05 -#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_26 0x1a06 -#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_27 0x1a07 -#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_28 0x1a08 -#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_29 0x1a09 -#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_30 0x1a0a -#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_VS_31 0x1a0b -#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 -#define mmSPI_SHADER_REQ_CTRL_VS 0x1a10 -#define mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_VS_0 0x1a12 -#define mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_VS_1 0x1a13 -#define mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_VS_2 0x1a14 -#define mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_VS_3 0x1a15 -#define mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x1a1b -#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_CHKSUM_GS 0x1a20 -#define mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC4_GS 0x1a21 -#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_ES_GS 0x1a24 -#define mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_ES_GS 0x1a25 -#define mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC3_GS 0x1a27 -#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_GS 0x1a28 -#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_GS 0x1a29 -#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC1_GS 0x1a2a -#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC2_GS 0x1a2b -#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_0 0x1a2c -#define mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_1 0x1a2d -#define mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_2 0x1a2e -#define mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_3 0x1a2f -#define mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_4 0x1a30 -#define mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_5 0x1a31 -#define mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_6 0x1a32 -#define mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_7 0x1a33 -#define mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_8 0x1a34 -#define mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_9 0x1a35 -#define mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_10 0x1a36 -#define mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_11 0x1a37 -#define mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_12 0x1a38 -#define mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_13 0x1a39 -#define mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_14 0x1a3a -#define mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_15 0x1a3b -#define mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_16 0x1a3c -#define mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_17 0x1a3d -#define mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_18 0x1a3e -#define mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_19 0x1a3f -#define mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_20 0x1a40 -#define mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_21 0x1a41 -#define mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_22 0x1a42 -#define mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_23 0x1a43 -#define mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_24 0x1a44 -#define mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_25 0x1a45 -#define mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_26 0x1a46 -#define mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_27 0x1a47 -#define mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_28 0x1a48 -#define mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_29 0x1a49 -#define mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_30 0x1a4a -#define mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_GS_31 0x1a4b -#define mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 -#define mmSPI_SHADER_REQ_CTRL_ESGS 0x1a50 -#define mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 -#define mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 -#define mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 -#define mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 -#define mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_ES 0x1a68 -#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_ES 0x1a69 -#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 -#define mmSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 -#define mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC4_HS 0x1aa1 -#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_LS_HS 0x1aa4 -#define mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_LS_HS 0x1aa5 -#define mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC3_HS 0x1aa7 -#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_HS 0x1aa8 -#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_HS 0x1aa9 -#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC1_HS 0x1aaa -#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_RSRC2_HS 0x1aab -#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_0 0x1aac -#define mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_1 0x1aad -#define mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_2 0x1aae -#define mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_3 0x1aaf -#define mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_4 0x1ab0 -#define mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_5 0x1ab1 -#define mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_6 0x1ab2 -#define mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_7 0x1ab3 -#define mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_8 0x1ab4 -#define mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_9 0x1ab5 -#define mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_10 0x1ab6 -#define mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_11 0x1ab7 -#define mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_12 0x1ab8 -#define mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_13 0x1ab9 -#define mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_14 0x1aba -#define mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_15 0x1abb -#define mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_16 0x1abc -#define mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_17 0x1abd -#define mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_18 0x1abe -#define mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_19 0x1abf -#define mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_20 0x1ac0 -#define mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_21 0x1ac1 -#define mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_22 0x1ac2 -#define mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_23 0x1ac3 -#define mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_24 0x1ac4 -#define mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_25 0x1ac5 -#define mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_26 0x1ac6 -#define mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_27 0x1ac7 -#define mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_28 0x1ac8 -#define mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_29 0x1ac9 -#define mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_30 0x1aca -#define mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 -#define mmSPI_SHADER_USER_DATA_HS_31 0x1acb -#define mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 -#define mmSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 -#define mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 -#define mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 -#define mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 -#define mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 -#define mmSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 -#define mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 -#define mmSPI_SHADER_PGM_LO_LS 0x1ae8 -#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 -#define mmSPI_SHADER_PGM_HI_LS 0x1ae9 -#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_INITIATOR 0x1ba0 -#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 -#define mmCOMPUTE_DIM_X 0x1ba1 -#define mmCOMPUTE_DIM_X_BASE_IDX 0 -#define mmCOMPUTE_DIM_Y 0x1ba2 -#define mmCOMPUTE_DIM_Y_BASE_IDX 0 -#define mmCOMPUTE_DIM_Z 0x1ba3 -#define mmCOMPUTE_DIM_Z_BASE_IDX 0 -#define mmCOMPUTE_START_X 0x1ba4 -#define mmCOMPUTE_START_X_BASE_IDX 0 -#define mmCOMPUTE_START_Y 0x1ba5 -#define mmCOMPUTE_START_Y_BASE_IDX 0 -#define mmCOMPUTE_START_Z 0x1ba6 -#define mmCOMPUTE_START_Z_BASE_IDX 0 -#define mmCOMPUTE_NUM_THREAD_X 0x1ba7 -#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 -#define mmCOMPUTE_NUM_THREAD_Y 0x1ba8 -#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 -#define mmCOMPUTE_NUM_THREAD_Z 0x1ba9 -#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 -#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x1baa -#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 -#define mmCOMPUTE_PERFCOUNT_ENABLE 0x1bab -#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 -#define mmCOMPUTE_PGM_LO 0x1bac -#define mmCOMPUTE_PGM_LO_BASE_IDX 0 -#define mmCOMPUTE_PGM_HI 0x1bad -#define mmCOMPUTE_PGM_HI_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae -#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf -#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 -#define mmCOMPUTE_PGM_RSRC1 0x1bb2 -#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 -#define mmCOMPUTE_PGM_RSRC2 0x1bb3 -#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 -#define mmCOMPUTE_VMID 0x1bb4 -#define mmCOMPUTE_VMID_BASE_IDX 0 -#define mmCOMPUTE_RESOURCE_LIMITS 0x1bb5 -#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 -#define mmCOMPUTE_DESTINATION_EN_SE0 0x1bb6 -#define mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 -#define mmCOMPUTE_DESTINATION_EN_SE1 0x1bb7 -#define mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 -#define mmCOMPUTE_TMPRING_SIZE 0x1bb8 -#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 -#define mmCOMPUTE_DESTINATION_EN_SE2 0x1bb9 -#define mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 -#define mmCOMPUTE_DESTINATION_EN_SE3 0x1bba -#define mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 -#define mmCOMPUTE_RESTART_X 0x1bbb -#define mmCOMPUTE_RESTART_X_BASE_IDX 0 -#define mmCOMPUTE_RESTART_Y 0x1bbc -#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 -#define mmCOMPUTE_RESTART_Z 0x1bbd -#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 -#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe -#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 -#define mmCOMPUTE_MISC_RESERVED 0x1bbf -#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_ID 0x1bc0 -#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 -#define mmCOMPUTE_THREADGROUP_ID 0x1bc1 -#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 -#define mmCOMPUTE_REQ_CTRL 0x1bc2 -#define mmCOMPUTE_REQ_CTRL_BASE_IDX 0 -#define mmCOMPUTE_USER_ACCUM_0 0x1bc4 -#define mmCOMPUTE_USER_ACCUM_0_BASE_IDX 0 -#define mmCOMPUTE_USER_ACCUM_1 0x1bc5 -#define mmCOMPUTE_USER_ACCUM_1_BASE_IDX 0 -#define mmCOMPUTE_USER_ACCUM_2 0x1bc6 -#define mmCOMPUTE_USER_ACCUM_2_BASE_IDX 0 -#define mmCOMPUTE_USER_ACCUM_3 0x1bc7 -#define mmCOMPUTE_USER_ACCUM_3_BASE_IDX 0 -#define mmCOMPUTE_PGM_RSRC3 0x1bc8 -#define mmCOMPUTE_PGM_RSRC3_BASE_IDX 0 -#define mmCOMPUTE_DDID_INDEX 0x1bc9 -#define mmCOMPUTE_DDID_INDEX_BASE_IDX 0 -#define mmCOMPUTE_SHADER_CHKSUM 0x1bca -#define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 -#define mmCOMPUTE_RELAUNCH 0x1bcb -#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bcc -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bcd -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 -#define mmCOMPUTE_RELAUNCH2 0x1bce -#define mmCOMPUTE_RELAUNCH2_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_0 0x1be0 -#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_1 0x1be1 -#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_2 0x1be2 -#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_3 0x1be3 -#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_4 0x1be4 -#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_5 0x1be5 -#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_6 0x1be6 -#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_7 0x1be7 -#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_8 0x1be8 -#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_9 0x1be9 -#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_10 0x1bea -#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_11 0x1beb -#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_12 0x1bec -#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_13 0x1bed -#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_14 0x1bee -#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 -#define mmCOMPUTE_USER_DATA_15 0x1bef -#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_TUNNEL 0x1c1d -#define mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 -#define mmCOMPUTE_DISPATCH_END 0x1c1e -#define mmCOMPUTE_DISPATCH_END_BASE_IDX 0 -#define mmCOMPUTE_NOWHERE 0x1c1f -#define mmCOMPUTE_NOWHERE_BASE_IDX 0 -#define mmSH_RESERVED_REG0 0x1c20 -#define mmSH_RESERVED_REG0_BASE_IDX 0 -#define mmSH_RESERVED_REG1 0x1c21 -#define mmSH_RESERVED_REG1_BASE_IDX 0 - - -// addressBlock: gc_cppdec -// base address: 0xc080 -#define mmCP_EOPQ_WAIT_TIME 0x1dd5 -#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 -#define mmCP_CPC_MGCG_SYNC_CNTL 0x1dd6 -#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 -#define mmCPC_INT_INFO 0x1dd7 -#define mmCPC_INT_INFO_BASE_IDX 0 -#define mmCP_VIRT_STATUS 0x1dd8 -#define mmCP_VIRT_STATUS_BASE_IDX 0 -#define mmCPC_INT_ADDR 0x1dd9 -#define mmCPC_INT_ADDR_BASE_IDX 0 -#define mmCPC_INT_PASID 0x1dda -#define mmCPC_INT_PASID_BASE_IDX 0 -#define mmCP_GFX_ERROR 0x1ddb -#define mmCP_GFX_ERROR_BASE_IDX 0 -#define mmCPG_UTCL1_CNTL 0x1ddc -#define mmCPG_UTCL1_CNTL_BASE_IDX 0 -#define mmCPC_UTCL1_CNTL 0x1ddd -#define mmCPC_UTCL1_CNTL_BASE_IDX 0 -#define mmCPF_UTCL1_CNTL 0x1dde -#define mmCPF_UTCL1_CNTL_BASE_IDX 0 -#define mmCP_AQL_SMM_STATUS 0x1ddf -#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 -#define mmCP_RB0_BASE 0x1de0 -#define mmCP_RB0_BASE_BASE_IDX 0 -#define mmCP_RB_BASE 0x1de0 -#define mmCP_RB_BASE_BASE_IDX 0 -#define mmCP_RB0_CNTL 0x1de1 -#define mmCP_RB0_CNTL_BASE_IDX 0 -#define mmCP_RB_CNTL 0x1de1 -#define mmCP_RB_CNTL_BASE_IDX 0 -#define mmCP_RB_RPTR_WR 0x1de2 -#define mmCP_RB_RPTR_WR_BASE_IDX 0 -#define mmCP_RB0_RPTR_ADDR 0x1de3 -#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 -#define mmCP_RB_RPTR_ADDR 0x1de3 -#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 -#define mmCP_RB0_RPTR_ADDR_HI 0x1de4 -#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_RB_RPTR_ADDR_HI 0x1de4 -#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_RB0_BUFSZ_MASK 0x1de5 -#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 -#define mmCP_RB_BUFSZ_MASK 0x1de5 -#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 -#define mmCP_INT_CNTL 0x1de9 -#define mmCP_INT_CNTL_BASE_IDX 0 -#define mmCP_INT_STATUS 0x1dea -#define mmCP_INT_STATUS_BASE_IDX 0 -#define mmCP_DEVICE_ID 0x1deb -#define mmCP_DEVICE_ID_BASE_IDX 0 -#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x1dec -#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define mmCP_RING_PRIORITY_CNTS 0x1dec -#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 -#define mmCP_ME0_PIPE0_PRIORITY 0x1ded -#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 -#define mmCP_RING0_PRIORITY 0x1ded -#define mmCP_RING0_PRIORITY_BASE_IDX 0 -#define mmCP_ME0_PIPE1_PRIORITY 0x1dee -#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 -#define mmCP_RING1_PRIORITY 0x1dee -#define mmCP_RING1_PRIORITY_BASE_IDX 0 -#define mmCP_ME0_PIPE2_PRIORITY 0x1def -#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 -#define mmCP_RING2_PRIORITY 0x1def -#define mmCP_RING2_PRIORITY_BASE_IDX 0 -#define mmCP_FATAL_ERROR 0x1df0 -#define mmCP_FATAL_ERROR_BASE_IDX 0 -#define mmCP_RB_VMID 0x1df1 -#define mmCP_RB_VMID_BASE_IDX 0 -#define mmCP_ME0_PIPE0_VMID 0x1df2 -#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 -#define mmCP_ME0_PIPE1_VMID 0x1df3 -#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 -#define mmCP_RB0_WPTR 0x1df4 -#define mmCP_RB0_WPTR_BASE_IDX 0 -#define mmCP_RB_WPTR 0x1df4 -#define mmCP_RB_WPTR_BASE_IDX 0 -#define mmCP_RB0_WPTR_HI 0x1df5 -#define mmCP_RB0_WPTR_HI_BASE_IDX 0 -#define mmCP_RB_WPTR_HI 0x1df5 -#define mmCP_RB_WPTR_HI_BASE_IDX 0 -#define mmCP_RB1_WPTR 0x1df6 -#define mmCP_RB1_WPTR_BASE_IDX 0 -#define mmCP_RB1_WPTR_HI 0x1df7 -#define mmCP_RB1_WPTR_HI_BASE_IDX 0 -#define mmCP_RB2_WPTR 0x1df8 -#define mmCP_RB2_WPTR_BASE_IDX 0 -#define mmCP_PROCESS_QUANTUM 0x1df9 -#define mmCP_PROCESS_QUANTUM_BASE_IDX 0 -#define mmCP_RB_DOORBELL_RANGE_LOWER 0x1dfa -#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 -#define mmCP_RB_DOORBELL_RANGE_UPPER 0x1dfb -#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 -#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc -#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 -#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd -#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 -#define mmCPG_UTCL1_ERROR 0x1dfe -#define mmCPG_UTCL1_ERROR_BASE_IDX 0 -#define mmCPC_UTCL1_ERROR 0x1dff -#define mmCPC_UTCL1_ERROR_BASE_IDX 0 -#define mmCP_RB1_BASE 0x1e00 -#define mmCP_RB1_BASE_BASE_IDX 0 -#define mmCP_RB1_CNTL 0x1e01 -#define mmCP_RB1_CNTL_BASE_IDX 0 -#define mmCP_RB1_RPTR_ADDR 0x1e02 -#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 -#define mmCP_RB1_RPTR_ADDR_HI 0x1e03 -#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_RB1_BUFSZ_MASK 0x1e04 -#define mmCP_RB1_BUFSZ_MASK_BASE_IDX 0 -#define mmCP_RB2_BASE 0x1e05 -#define mmCP_RB2_BASE_BASE_IDX 0 -#define mmCP_RB2_CNTL 0x1e06 -#define mmCP_RB2_CNTL_BASE_IDX 0 -#define mmCP_RB2_RPTR_ADDR 0x1e07 -#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 -#define mmCP_RB2_RPTR_ADDR_HI 0x1e08 -#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_INT_CNTL_RING0 0x1e0a -#define mmCP_INT_CNTL_RING0_BASE_IDX 0 -#define mmCP_INT_CNTL_RING1 0x1e0b -#define mmCP_INT_CNTL_RING1_BASE_IDX 0 -#define mmCP_INT_CNTL_RING2 0x1e0c -#define mmCP_INT_CNTL_RING2_BASE_IDX 0 -#define mmCP_INT_STATUS_RING0 0x1e0d -#define mmCP_INT_STATUS_RING0_BASE_IDX 0 -#define mmCP_INT_STATUS_RING1 0x1e0e -#define mmCP_INT_STATUS_RING1_BASE_IDX 0 -#define mmCP_INT_STATUS_RING2 0x1e0f -#define mmCP_INT_STATUS_RING2_BASE_IDX 0 -#define mmCP_ME_F32_INTERRUPT 0x1e13 -#define mmCP_ME_F32_INTERRUPT_BASE_IDX 0 -#define mmCP_PFP_F32_INTERRUPT 0x1e14 -#define mmCP_PFP_F32_INTERRUPT_BASE_IDX 0 -#define mmCP_CE_F32_INTERRUPT 0x1e15 -#define mmCP_CE_F32_INTERRUPT_BASE_IDX 0 -#define mmCP_MEC1_F32_INTERRUPT 0x1e16 -#define mmCP_MEC1_F32_INTERRUPT_BASE_IDX 0 -#define mmCP_MEC2_F32_INTERRUPT 0x1e17 -#define mmCP_MEC2_F32_INTERRUPT_BASE_IDX 0 -#define mmCP_PWR_CNTL 0x1e18 -#define mmCP_PWR_CNTL_BASE_IDX 0 -#define mmCP_MEM_SLP_CNTL 0x1e19 -#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 -#define mmCP_ECC_FIRSTOCCURRENCE 0x1e1a -#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 -#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b -#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 -#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c -#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 -#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x1e1d -#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 -#define mmGB_EDC_MODE 0x1e1e -#define mmGB_EDC_MODE_BASE_IDX 0 -#define mmCP_PQ_WPTR_POLL_CNTL 0x1e23 -#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmCP_PQ_WPTR_POLL_CNTL1 0x1e24 -#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 -#define mmCP_ME1_PIPE0_INT_CNTL 0x1e25 -#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 -#define mmCP_ME1_PIPE1_INT_CNTL 0x1e26 -#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 -#define mmCP_ME1_PIPE2_INT_CNTL 0x1e27 -#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 -#define mmCP_ME1_PIPE3_INT_CNTL 0x1e28 -#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 -#define mmCP_ME2_PIPE0_INT_CNTL 0x1e29 -#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 -#define mmCP_ME2_PIPE1_INT_CNTL 0x1e2a -#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 -#define mmCP_ME2_PIPE2_INT_CNTL 0x1e2b -#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 -#define mmCP_ME2_PIPE3_INT_CNTL 0x1e2c -#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 -#define mmCP_ME1_PIPE0_INT_STATUS 0x1e2d -#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 -#define mmCP_ME1_PIPE1_INT_STATUS 0x1e2e -#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 -#define mmCP_ME1_PIPE2_INT_STATUS 0x1e2f -#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 -#define mmCP_ME1_PIPE3_INT_STATUS 0x1e30 -#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 -#define mmCP_ME2_PIPE0_INT_STATUS 0x1e31 -#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 -#define mmCP_ME2_PIPE1_INT_STATUS 0x1e32 -#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 -#define mmCP_ME2_PIPE2_INT_STATUS 0x1e33 -#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 -#define mmCP_ME2_PIPE3_INT_STATUS 0x1e34 -#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 -#define mmCP_GFX_QUEUE_INDEX 0x1e37 -#define mmCP_GFX_QUEUE_INDEX_BASE_IDX 0 -#define mmCC_GC_EDC_CONFIG 0x1e38 -#define mmCC_GC_EDC_CONFIG_BASE_IDX 0 -#define mmCP_ME1_INT_STAT_DEBUG 0x1e35 -#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 -#define mmCP_ME2_INT_STAT_DEBUG 0x1e36 -#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX 0 -#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 -#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define mmCP_ME1_PIPE0_PRIORITY 0x1e3a -#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 -#define mmCP_ME1_PIPE1_PRIORITY 0x1e3b -#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 -#define mmCP_ME1_PIPE2_PRIORITY 0x1e3c -#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 -#define mmCP_ME1_PIPE3_PRIORITY 0x1e3d -#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 -#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e -#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define mmCP_ME2_PIPE0_PRIORITY 0x1e3f -#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 -#define mmCP_ME2_PIPE1_PRIORITY 0x1e40 -#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 -#define mmCP_ME2_PIPE2_PRIORITY 0x1e41 -#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 -#define mmCP_ME2_PIPE3_PRIORITY 0x1e42 -#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 -#define mmCP_CE_PRGRM_CNTR_START 0x1e43 -#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 -#define mmCP_PFP_PRGRM_CNTR_START 0x1e44 -#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 -#define mmCP_ME_PRGRM_CNTR_START 0x1e45 -#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 -#define mmCP_MEC1_PRGRM_CNTR_START 0x1e46 -#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 -#define mmCP_MEC2_PRGRM_CNTR_START 0x1e47 -#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 -#define mmCP_CE_INTR_ROUTINE_START 0x1e48 -#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 -#define mmCP_PFP_INTR_ROUTINE_START 0x1e49 -#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 -#define mmCP_ME_INTR_ROUTINE_START 0x1e4a -#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 -#define mmCP_MEC1_INTR_ROUTINE_START 0x1e4b -#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 -#define mmCP_MEC2_INTR_ROUTINE_START 0x1e4c -#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 -#define mmCP_CONTEXT_CNTL 0x1e4d -#define mmCP_CONTEXT_CNTL_BASE_IDX 0 -#define mmCP_MAX_CONTEXT 0x1e4e -#define mmCP_MAX_CONTEXT_BASE_IDX 0 -#define mmCP_IQ_WAIT_TIME1 0x1e4f -#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 -#define mmCP_IQ_WAIT_TIME2 0x1e50 -#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 -#define mmCP_RB0_BASE_HI 0x1e51 -#define mmCP_RB0_BASE_HI_BASE_IDX 0 -#define mmCP_RB1_BASE_HI 0x1e52 -#define mmCP_RB1_BASE_HI_BASE_IDX 0 -#define mmCP_VMID_RESET 0x1e53 -#define mmCP_VMID_RESET_BASE_IDX 0 -#define mmCPC_INT_CNTL 0x1e54 -#define mmCPC_INT_CNTL_BASE_IDX 0 -#define mmCPC_INT_STATUS 0x1e55 -#define mmCPC_INT_STATUS_BASE_IDX 0 -#define mmCP_VMID_PREEMPT 0x1e56 -#define mmCP_VMID_PREEMPT_BASE_IDX 0 -#define mmCPC_INT_CNTX_ID 0x1e57 -#define mmCPC_INT_CNTX_ID_BASE_IDX 0 -#define mmCP_PQ_STATUS 0x1e58 -#define mmCP_PQ_STATUS_BASE_IDX 0 -#define mmCP_MEC1_F32_INT_DIS 0x1e5d -#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 -#define mmCP_MEC2_F32_INT_DIS 0x1e5e -#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 -#define mmCP_VMID_STATUS 0x1e5f -#define mmCP_VMID_STATUS_BASE_IDX 0 -#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 -#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 -#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 -#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 -#define mmCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 -#define mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 -#define mmCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 -#define mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 -#define mmCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 -#define mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 -#define mmCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 -#define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 -#define mmCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 -#define mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 -#define mmCPC_OS_PIPES 0x1e67 -#define mmCPC_OS_PIPES_BASE_IDX 0 -#define mmCP_SUSPEND_RESUME_REQ 0x1e68 -#define mmCP_SUSPEND_RESUME_REQ_BASE_IDX 0 -#define mmCP_SUSPEND_CNTL 0x1e69 -#define mmCP_SUSPEND_CNTL_BASE_IDX 0 -#define mmCP_IQ_WAIT_TIME3 0x1e6a -#define mmCP_IQ_WAIT_TIME3_BASE_IDX 0 -#define mmCPC_DDID_BASE_ADDR_LO 0x1e6b -#define mmCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 -#define mmCP_DDID_BASE_ADDR_LO 0x1e6b -#define mmCP_DDID_BASE_ADDR_LO_BASE_IDX 0 -#define mmCPC_DDID_BASE_ADDR_HI 0x1e6c -#define mmCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_DDID_BASE_ADDR_HI 0x1e6c -#define mmCP_DDID_BASE_ADDR_HI_BASE_IDX 0 -#define mmCPC_DDID_CNTL 0x1e6d -#define mmCPC_DDID_CNTL_BASE_IDX 0 -#define mmCP_DDID_CNTL 0x1e6d -#define mmCP_DDID_CNTL_BASE_IDX 0 -#define mmCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e -#define mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 -#define mmCP_GFX_DDID_WPTR 0x1e6f -#define mmCP_GFX_DDID_WPTR_BASE_IDX 0 -#define mmCP_GFX_DDID_RPTR 0x1e70 -#define mmCP_GFX_DDID_RPTR_BASE_IDX 0 -#define mmCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 -#define mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 -#define mmCP_GFX_HPD_STATUS0 0x1e72 -#define mmCP_GFX_HPD_STATUS0_BASE_IDX 0 -#define mmCP_GFX_HPD_CONTROL0 0x1e73 -#define mmCP_GFX_HPD_CONTROL0_BASE_IDX 0 -#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 -#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 -#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 -#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 -#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 -#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 -#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 -#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 -#define mmCP_GFX_INDEX_MUTEX 0x1e78 -#define mmCP_GFX_INDEX_MUTEX_BASE_IDX 0 -#define mmCP_GFX_MQD_BASE_ADDR 0x1e7e -#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 -#define mmCP_GFX_MQD_BASE_ADDR_HI 0x1e7f -#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_ACTIVE 0x1e80 -#define mmCP_GFX_HQD_ACTIVE_BASE_IDX 0 -#define mmCP_GFX_HQD_VMID 0x1e81 -#define mmCP_GFX_HQD_VMID_BASE_IDX 0 -#define mmCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 -#define mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 -#define mmCP_GFX_HQD_QUANTUM 0x1e85 -#define mmCP_GFX_HQD_QUANTUM_BASE_IDX 0 -#define mmCP_GFX_HQD_BASE 0x1e86 -#define mmCP_GFX_HQD_BASE_BASE_IDX 0 -#define mmCP_GFX_HQD_BASE_HI 0x1e87 -#define mmCP_GFX_HQD_BASE_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_RPTR 0x1e88 -#define mmCP_GFX_HQD_RPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_RPTR_ADDR 0x1e89 -#define mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 -#define mmCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a -#define mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1e8b -#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1e8c -#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmCP_RB_DOORBELL_CONTROL 0x1e8d -#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 -#define mmCP_GFX_HQD_OFFSET 0x1e8e -#define mmCP_GFX_HQD_OFFSET_BASE_IDX 0 -#define mmCP_GFX_HQD_CNTL 0x1e8f -#define mmCP_GFX_HQD_CNTL_BASE_IDX 0 -#define mmCP_GFX_HQD_CSMD_RPTR 0x1e90 -#define mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_WPTR 0x1e91 -#define mmCP_GFX_HQD_WPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_WPTR_HI 0x1e92 -#define mmCP_GFX_HQD_WPTR_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 -#define mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 -#define mmCP_GFX_HQD_MAPPED 0x1e94 -#define mmCP_GFX_HQD_MAPPED_BASE_IDX 0 -#define mmCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 -#define mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 -#define mmCP_GFX_HQD_HQ_STATUS0 0x1e98 -#define mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 -#define mmCP_GFX_HQD_HQ_CONTROL0 0x1e99 -#define mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 -#define mmCP_GFX_MQD_CONTROL 0x1e9a -#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 -#define mmCP_HQD_GFX_CONTROL 0x1e9f -#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 -#define mmCP_HQD_GFX_STATUS 0x1ea0 -#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_RPTR_WR 0x1ea1 -#define mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_BASE 0x1ea2 -#define mmCP_GFX_HQD_CE_BASE_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_BASE_HI 0x1ea3 -#define mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_RPTR 0x1ea4 -#define mmCP_GFX_HQD_CE_RPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_RPTR_ADDR 0x1ea5 -#define mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_RPTR_ADDR_HI 0x1ea6 -#define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO 0x1ea7 -#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI 0x1ea8 -#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_OFFSET 0x1ea9 -#define mmCP_GFX_HQD_CE_OFFSET_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_CNTL 0x1eaa -#define mmCP_GFX_HQD_CE_CNTL_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_CSMD_RPTR 0x1eab -#define mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_WPTR 0x1eac -#define mmCP_GFX_HQD_CE_WPTR_BASE_IDX 0 -#define mmCP_GFX_HQD_CE_WPTR_HI 0x1ead -#define mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX 0 -#define mmCP_CE_DOORBELL_CONTROL 0x1eae -#define mmCP_CE_DOORBELL_CONTROL_BASE_IDX 0 -#define mmCP_DMA_WATCH0_ADDR_LO 0x1ec0 -#define mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 -#define mmCP_DMA_WATCH0_ADDR_HI 0x1ec1 -#define mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 -#define mmCP_DMA_WATCH0_MASK 0x1ec2 -#define mmCP_DMA_WATCH0_MASK_BASE_IDX 0 -#define mmCP_DMA_WATCH0_CNTL 0x1ec3 -#define mmCP_DMA_WATCH0_CNTL_BASE_IDX 0 -#define mmCP_DMA_WATCH1_ADDR_LO 0x1ec4 -#define mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 -#define mmCP_DMA_WATCH1_ADDR_HI 0x1ec5 -#define mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 -#define mmCP_DMA_WATCH1_MASK 0x1ec6 -#define mmCP_DMA_WATCH1_MASK_BASE_IDX 0 -#define mmCP_DMA_WATCH1_CNTL 0x1ec7 -#define mmCP_DMA_WATCH1_CNTL_BASE_IDX 0 -#define mmCP_DMA_WATCH2_ADDR_LO 0x1ec8 -#define mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 -#define mmCP_DMA_WATCH2_ADDR_HI 0x1ec9 -#define mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 -#define mmCP_DMA_WATCH2_MASK 0x1eca -#define mmCP_DMA_WATCH2_MASK_BASE_IDX 0 -#define mmCP_DMA_WATCH2_CNTL 0x1ecb -#define mmCP_DMA_WATCH2_CNTL_BASE_IDX 0 -#define mmCP_DMA_WATCH3_ADDR_LO 0x1ecc -#define mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 -#define mmCP_DMA_WATCH3_ADDR_HI 0x1ecd -#define mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 -#define mmCP_DMA_WATCH3_MASK 0x1ece -#define mmCP_DMA_WATCH3_MASK_BASE_IDX 0 -#define mmCP_DMA_WATCH3_CNTL 0x1ecf -#define mmCP_DMA_WATCH3_CNTL_BASE_IDX 0 -#define mmCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 -#define mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 -#define mmCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 -#define mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 -#define mmCP_DMA_WATCH_STAT 0x1ed2 -#define mmCP_DMA_WATCH_STAT_BASE_IDX 0 -#define mmCP_PFP_JT_STAT 0x1ed3 -#define mmCP_PFP_JT_STAT_BASE_IDX 0 -#define mmCP_CE_JT_STAT 0x1ed4 -#define mmCP_CE_JT_STAT_BASE_IDX 0 -#define mmCP_MEC_JT_STAT 0x1ed5 -#define mmCP_MEC_JT_STAT_BASE_IDX 0 -#define mmCP_FETCHER_SOURCE 0x1f1e -#define mmCP_FETCHER_SOURCE_BASE_IDX 0 -#define mmCP_CE_CS_PARTITION_INDEX 0x1f1f -#define mmCP_CE_CS_PARTITION_INDEX_BASE_IDX 0 -#define mmCP_RB_DOORBELL_CLEAR 0x1f28 -#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 -#define mmCP_RB0_ACTIVE 0x1f40 -#define mmCP_RB0_ACTIVE_BASE_IDX 0 -#define mmCP_RB_ACTIVE 0x1f40 -#define mmCP_RB_ACTIVE_BASE_IDX 0 -#define mmCP_RB1_ACTIVE 0x1f41 -#define mmCP_RB1_ACTIVE_BASE_IDX 0 -#define mmCP_RB_STATUS 0x1f43 -#define mmCP_RB_STATUS_BASE_IDX 0 -#define mmCPG_RCIU_CAM_INDEX 0x1f44 -#define mmCPG_RCIU_CAM_INDEX_BASE_IDX 0 -#define mmCPG_RCIU_CAM_DATA 0x1f45 -#define mmCPG_RCIU_CAM_DATA_BASE_IDX 0 -#define mmCPG_RCIU_CAM_DATA_PHASE0 0x1f45 -#define mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 -#define mmCPG_RCIU_CAM_DATA_PHASE1 0x1f45 -#define mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 -#define mmCPG_RCIU_CAM_DATA_PHASE2 0x1f45 -#define mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 -#define mmCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c -#define mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 -#define mmCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d -#define mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 -#define mmCPF_GCR_CNTL 0x1f53 -#define mmCPF_GCR_CNTL_BASE_IDX 0 -#define mmCPG_UTCL1_STATUS 0x1f54 -#define mmCPG_UTCL1_STATUS_BASE_IDX 0 -#define mmCPC_UTCL1_STATUS 0x1f55 -#define mmCPC_UTCL1_STATUS_BASE_IDX 0 -#define mmCPF_UTCL1_STATUS 0x1f56 -#define mmCPF_UTCL1_STATUS_BASE_IDX 0 -#define mmCP_SD_CNTL 0x1f57 -#define mmCP_SD_CNTL_BASE_IDX 0 -#define mmCP_SOFT_RESET_CNTL 0x1f59 -#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 -#define mmCP_CPC_GFX_CNTL 0x1f5a -#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 - - -// addressBlock: gc_spipdec -// base address: 0xc700 -#define mmSPI_ARB_PRIORITY 0x1f60 -#define mmSPI_ARB_PRIORITY_BASE_IDX 0 -#define mmSPI_ARB_CYCLES_0 0x1f61 -#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 -#define mmSPI_ARB_CYCLES_1 0x1f62 -#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_GFX 0x1f67 -#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 -#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_CS0 0x1f69 -#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_CS1 0x1f6a -#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_CS2 0x1f6b -#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 -#define mmSPI_WCL_PIPE_PERCENT_CS3 0x1f6c -#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 -#define mmSPI_GDBG_WAVE_CNTL 0x1f71 -#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 -#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 -#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 -#define mmSPI_GDBG_TRAP_MASK 0x1f73 -#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 -#define mmSPI_GDBG_WAVE_CNTL2 0x1f74 -#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 -#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 -#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 -#define mmSPI_GDBG_TRAP_DATA0 0x1f78 -#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 -#define mmSPI_GDBG_TRAP_DATA1 0x1f79 -#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 -#define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b -#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c -#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_1 0x1f7d -#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_2 0x1f7e -#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_3 0x1f7f -#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_4 0x1f80 -#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_5 0x1f81 -#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_6 0x1f82 -#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_7 0x1f83 -#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_8 0x1f84 -#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_CU_9 0x1f85 -#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x1f86 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x1f87 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x1f88 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x1f89 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x1f8a -#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x1f8b -#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x1f8c -#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x1f8d -#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x1f8e -#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 -#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x1f8f -#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 -#define mmSPI_COMPUTE_WF_CTX_SAVE 0x1f9c -#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 -#define mmSPI_ARB_CNTL_0 0x1f9d -#define mmSPI_ARB_CNTL_0_BASE_IDX 0 -#define mmSPI_FEATURE_CTRL 0x1f9e -#define mmSPI_FEATURE_CTRL_BASE_IDX 0 -#define mmSPI_SHADER_RSRC_LIMIT_CTRL 0x1f9f -#define mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 0 - - -// addressBlock: gc_cpphqddec -// base address: 0xc800 -#define mmCP_HPD_MES_ROQ_OFFSETS 0x1fa4 -#define mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 0 -#define mmCP_HPD_ROQ_OFFSETS 0x1fa4 -#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 -#define mmCP_HPD_STATUS0 0x1fa5 -#define mmCP_HPD_STATUS0_BASE_IDX 0 -#define mmCP_HPD_UTCL1_CNTL 0x1fa6 -#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 -#define mmCP_HPD_UTCL1_ERROR 0x1fa7 -#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 -#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 -#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 -#define mmCP_MQD_BASE_ADDR 0x1fa9 -#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 -#define mmCP_MQD_BASE_ADDR_HI 0x1faa -#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_ACTIVE 0x1fab -#define mmCP_HQD_ACTIVE_BASE_IDX 0 -#define mmCP_HQD_VMID 0x1fac -#define mmCP_HQD_VMID_BASE_IDX 0 -#define mmCP_HQD_PERSISTENT_STATE 0x1fad -#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 -#define mmCP_HQD_PIPE_PRIORITY 0x1fae -#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 -#define mmCP_HQD_QUEUE_PRIORITY 0x1faf -#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 -#define mmCP_HQD_QUANTUM 0x1fb0 -#define mmCP_HQD_QUANTUM_BASE_IDX 0 -#define mmCP_HQD_PQ_BASE 0x1fb1 -#define mmCP_HQD_PQ_BASE_BASE_IDX 0 -#define mmCP_HQD_PQ_BASE_HI 0x1fb2 -#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 -#define mmCP_HQD_PQ_RPTR 0x1fb3 -#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 -#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 -#define mmCP_HQD_PQ_CONTROL 0x1fba -#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 -#define mmCP_HQD_IB_BASE_ADDR 0x1fbb -#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 -#define mmCP_HQD_IB_BASE_ADDR_HI 0x1fbc -#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_IB_RPTR 0x1fbd -#define mmCP_HQD_IB_RPTR_BASE_IDX 0 -#define mmCP_HQD_IB_CONTROL 0x1fbe -#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 -#define mmCP_HQD_IQ_TIMER 0x1fbf -#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 -#define mmCP_HQD_IQ_RPTR 0x1fc0 -#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 -#define mmCP_HQD_DEQUEUE_REQUEST 0x1fc1 -#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 -#define mmCP_HQD_DMA_OFFLOAD 0x1fc2 -#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 -#define mmCP_HQD_OFFLOAD 0x1fc2 -#define mmCP_HQD_OFFLOAD_BASE_IDX 0 -#define mmCP_HQD_SEMA_CMD 0x1fc3 -#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 -#define mmCP_HQD_MSG_TYPE 0x1fc4 -#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 -#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 -#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 -#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 -#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 -#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 -#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 -#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 -#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 -#define mmCP_HQD_HQ_SCHEDULER0 0x1fc9 -#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 -#define mmCP_HQD_HQ_STATUS0 0x1fc9 -#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 -#define mmCP_HQD_HQ_CONTROL0 0x1fca -#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 -#define mmCP_HQD_HQ_SCHEDULER1 0x1fca -#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 -#define mmCP_MQD_CONTROL 0x1fcb -#define mmCP_MQD_CONTROL_BASE_IDX 0 -#define mmCP_HQD_HQ_STATUS1 0x1fcc -#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 -#define mmCP_HQD_HQ_CONTROL1 0x1fcd -#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 -#define mmCP_HQD_EOP_BASE_ADDR 0x1fce -#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 -#define mmCP_HQD_EOP_BASE_ADDR_HI 0x1fcf -#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_EOP_CONTROL 0x1fd0 -#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 -#define mmCP_HQD_EOP_RPTR 0x1fd1 -#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 -#define mmCP_HQD_EOP_WPTR 0x1fd2 -#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 -#define mmCP_HQD_EOP_EVENTS 0x1fd3 -#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 -#define mmCP_HQD_CTX_SAVE_CONTROL 0x1fd6 -#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 -#define mmCP_HQD_CNTL_STACK_OFFSET 0x1fd7 -#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 -#define mmCP_HQD_CNTL_STACK_SIZE 0x1fd8 -#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 -#define mmCP_HQD_WG_STATE_OFFSET 0x1fd9 -#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 -#define mmCP_HQD_CTX_SAVE_SIZE 0x1fda -#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 -#define mmCP_HQD_GDS_RESOURCE_STATE 0x1fdb -#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 -#define mmCP_HQD_ERROR 0x1fdc -#define mmCP_HQD_ERROR_BASE_IDX 0 -#define mmCP_HQD_EOP_WPTR_MEM 0x1fdd -#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 -#define mmCP_HQD_AQL_CONTROL 0x1fde -#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 -#define mmCP_HQD_PQ_WPTR_LO 0x1fdf -#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 -#define mmCP_HQD_PQ_WPTR_HI 0x1fe0 -#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 -#define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 -#define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 -#define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 -#define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 -#define mmCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 -#define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 -#define mmCP_HQD_DDID_RPTR 0x1fe4 -#define mmCP_HQD_DDID_RPTR_BASE_IDX 0 -#define mmCP_HQD_DDID_WPTR 0x1fe5 -#define mmCP_HQD_DDID_WPTR_BASE_IDX 0 -#define mmCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 -#define mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 -#define mmCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 -#define mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 -#define mmCP_HQD_DEQUEUE_STATUS 0x1fe8 -#define mmCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 - - -// addressBlock: gc_didtdec -// base address: 0xca00 -#define mmDIDT_IND_INDEX 0x2020 -#define mmDIDT_IND_INDEX_BASE_IDX 0 -#define mmDIDT_IND_DATA 0x2021 -#define mmDIDT_IND_DATA_BASE_IDX 0 -#define mmDIDT_INDEX_AUTO_INCR_EN 0x2022 -#define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 - - -// addressBlock: gc_gccacdec -// base address: 0xca10 -#define mmGC_CAC_CTRL_1 0x2024 -#define mmGC_CAC_CTRL_1_BASE_IDX 0 -#define mmGC_CAC_CTRL_2 0x2025 -#define mmGC_CAC_CTRL_2_BASE_IDX 0 -#define mmGC_CAC_AGGR_LOWER 0x2026 -#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 -#define mmGC_CAC_AGGR_UPPER 0x2027 -#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 -#define mmGC_CAC_SOFT_CTRL 0x202a -#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 -#define mmGC_EDC_CTRL 0x202b -#define mmGC_EDC_CTRL_BASE_IDX 0 -#define mmGC_EDC_THRESHOLD 0x202c -#define mmGC_EDC_THRESHOLD_BASE_IDX 0 -#define mmGC_EDC_STATUS 0x202d -#define mmGC_EDC_STATUS_BASE_IDX 0 -#define mmGC_EDC_OVERFLOW 0x202e -#define mmGC_EDC_OVERFLOW_BASE_IDX 0 -#define mmGC_EDC_ROLLING_POWER_DELTA 0x202f -#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 -#define mmGC_THROTTLE_CTRL 0x2030 -#define mmGC_THROTTLE_CTRL_BASE_IDX 0 -#define mmGC_THROTTLE_CTRL1 0x2031 -#define mmGC_THROTTLE_CTRL1_BASE_IDX 0 -#define mmGC_THROTTLE_STATUS 0x2032 -#define mmGC_THROTTLE_STATUS_BASE_IDX 0 -#define mmEDC_PERF_COUNTER 0x2033 -#define mmEDC_PERF_COUNTER_BASE_IDX 0 -#define mmPCC_PERF_COUNTER 0x2034 -#define mmPCC_PERF_COUNTER_BASE_IDX 0 -#define mmPWRBRK_PERF_COUNTER 0x2035 -#define mmPWRBRK_PERF_COUNTER_BASE_IDX 0 -#define mmGC_EDC_STRETCH_CTRL 0x2036 -#define mmGC_EDC_STRETCH_CTRL_BASE_IDX 0 -#define mmGC_EDC_STRETCH_THRESHOLD 0x2037 -#define mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX 0 -#define mmEDC_HYSTERESIS_CNTL 0x2038 -#define mmEDC_HYSTERESIS_CNTL_BASE_IDX 0 -#define mmEDC_HYSTERESIS_STAT 0x2039 -#define mmEDC_HYSTERESIS_STAT_BASE_IDX 0 -#define mmGC_CAC_IND_INDEX 0x203c -#define mmGC_CAC_IND_INDEX_BASE_IDX 0 -#define mmGC_CAC_IND_DATA 0x203d -#define mmGC_CAC_IND_DATA_BASE_IDX 0 -#define mmSE_CAC_IND_INDEX 0x203e -#define mmSE_CAC_IND_INDEX_BASE_IDX 0 -#define mmSE_CAC_IND_DATA 0x203f -#define mmSE_CAC_IND_DATA_BASE_IDX 0 - - -// addressBlock: gc_tcpdec -// base address: 0xca80 -#define mmTCP_WATCH0_ADDR_H 0x2040 -#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 -#define mmTCP_WATCH0_ADDR_L 0x2041 -#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 -#define mmTCP_WATCH0_CNTL 0x2042 -#define mmTCP_WATCH0_CNTL_BASE_IDX 0 -#define mmTCP_WATCH1_ADDR_H 0x2043 -#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 -#define mmTCP_WATCH1_ADDR_L 0x2044 -#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 -#define mmTCP_WATCH1_CNTL 0x2045 -#define mmTCP_WATCH1_CNTL_BASE_IDX 0 -#define mmTCP_WATCH2_ADDR_H 0x2046 -#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 -#define mmTCP_WATCH2_ADDR_L 0x2047 -#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 -#define mmTCP_WATCH2_CNTL 0x2048 -#define mmTCP_WATCH2_CNTL_BASE_IDX 0 -#define mmTCP_WATCH3_ADDR_H 0x2049 -#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 -#define mmTCP_WATCH3_ADDR_L 0x204a -#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 -#define mmTCP_WATCH3_CNTL 0x204b -#define mmTCP_WATCH3_CNTL_BASE_IDX 0 -#define mmTCP_PERFCOUNTER_FILTER 0x2059 -#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 -#define mmTCP_PERFCOUNTER_FILTER_EN 0x205a -#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 -#define mmTCP_PERFCOUNTER_FILTER2 0x205b -#define mmTCP_PERFCOUNTER_FILTER2_BASE_IDX 0 - - -// addressBlock: gc_gdspdec -// base address: 0xcc00 -#define mmGDS_VMID0_BASE 0x20a0 -#define mmGDS_VMID0_BASE_BASE_IDX 0 -#define mmGDS_VMID0_SIZE 0x20a1 -#define mmGDS_VMID0_SIZE_BASE_IDX 0 -#define mmGDS_VMID1_BASE 0x20a2 -#define mmGDS_VMID1_BASE_BASE_IDX 0 -#define mmGDS_VMID1_SIZE 0x20a3 -#define mmGDS_VMID1_SIZE_BASE_IDX 0 -#define mmGDS_VMID2_BASE 0x20a4 -#define mmGDS_VMID2_BASE_BASE_IDX 0 -#define mmGDS_VMID2_SIZE 0x20a5 -#define mmGDS_VMID2_SIZE_BASE_IDX 0 -#define mmGDS_VMID3_BASE 0x20a6 -#define mmGDS_VMID3_BASE_BASE_IDX 0 -#define mmGDS_VMID3_SIZE 0x20a7 -#define mmGDS_VMID3_SIZE_BASE_IDX 0 -#define mmGDS_VMID4_BASE 0x20a8 -#define mmGDS_VMID4_BASE_BASE_IDX 0 -#define mmGDS_VMID4_SIZE 0x20a9 -#define mmGDS_VMID4_SIZE_BASE_IDX 0 -#define mmGDS_VMID5_BASE 0x20aa -#define mmGDS_VMID5_BASE_BASE_IDX 0 -#define mmGDS_VMID5_SIZE 0x20ab -#define mmGDS_VMID5_SIZE_BASE_IDX 0 -#define mmGDS_VMID6_BASE 0x20ac -#define mmGDS_VMID6_BASE_BASE_IDX 0 -#define mmGDS_VMID6_SIZE 0x20ad -#define mmGDS_VMID6_SIZE_BASE_IDX 0 -#define mmGDS_VMID7_BASE 0x20ae -#define mmGDS_VMID7_BASE_BASE_IDX 0 -#define mmGDS_VMID7_SIZE 0x20af -#define mmGDS_VMID7_SIZE_BASE_IDX 0 -#define mmGDS_VMID8_BASE 0x20b0 -#define mmGDS_VMID8_BASE_BASE_IDX 0 -#define mmGDS_VMID8_SIZE 0x20b1 -#define mmGDS_VMID8_SIZE_BASE_IDX 0 -#define mmGDS_VMID9_BASE 0x20b2 -#define mmGDS_VMID9_BASE_BASE_IDX 0 -#define mmGDS_VMID9_SIZE 0x20b3 -#define mmGDS_VMID9_SIZE_BASE_IDX 0 -#define mmGDS_VMID10_BASE 0x20b4 -#define mmGDS_VMID10_BASE_BASE_IDX 0 -#define mmGDS_VMID10_SIZE 0x20b5 -#define mmGDS_VMID10_SIZE_BASE_IDX 0 -#define mmGDS_VMID11_BASE 0x20b6 -#define mmGDS_VMID11_BASE_BASE_IDX 0 -#define mmGDS_VMID11_SIZE 0x20b7 -#define mmGDS_VMID11_SIZE_BASE_IDX 0 -#define mmGDS_VMID12_BASE 0x20b8 -#define mmGDS_VMID12_BASE_BASE_IDX 0 -#define mmGDS_VMID12_SIZE 0x20b9 -#define mmGDS_VMID12_SIZE_BASE_IDX 0 -#define mmGDS_VMID13_BASE 0x20ba -#define mmGDS_VMID13_BASE_BASE_IDX 0 -#define mmGDS_VMID13_SIZE 0x20bb -#define mmGDS_VMID13_SIZE_BASE_IDX 0 -#define mmGDS_VMID14_BASE 0x20bc -#define mmGDS_VMID14_BASE_BASE_IDX 0 -#define mmGDS_VMID14_SIZE 0x20bd -#define mmGDS_VMID14_SIZE_BASE_IDX 0 -#define mmGDS_VMID15_BASE 0x20be -#define mmGDS_VMID15_BASE_BASE_IDX 0 -#define mmGDS_VMID15_SIZE 0x20bf -#define mmGDS_VMID15_SIZE_BASE_IDX 0 -#define mmGDS_GWS_VMID0 0x20c0 -#define mmGDS_GWS_VMID0_BASE_IDX 0 -#define mmGDS_GWS_VMID1 0x20c1 -#define mmGDS_GWS_VMID1_BASE_IDX 0 -#define mmGDS_GWS_VMID2 0x20c2 -#define mmGDS_GWS_VMID2_BASE_IDX 0 -#define mmGDS_GWS_VMID3 0x20c3 -#define mmGDS_GWS_VMID3_BASE_IDX 0 -#define mmGDS_GWS_VMID4 0x20c4 -#define mmGDS_GWS_VMID4_BASE_IDX 0 -#define mmGDS_GWS_VMID5 0x20c5 -#define mmGDS_GWS_VMID5_BASE_IDX 0 -#define mmGDS_GWS_VMID6 0x20c6 -#define mmGDS_GWS_VMID6_BASE_IDX 0 -#define mmGDS_GWS_VMID7 0x20c7 -#define mmGDS_GWS_VMID7_BASE_IDX 0 -#define mmGDS_GWS_VMID8 0x20c8 -#define mmGDS_GWS_VMID8_BASE_IDX 0 -#define mmGDS_GWS_VMID9 0x20c9 -#define mmGDS_GWS_VMID9_BASE_IDX 0 -#define mmGDS_GWS_VMID10 0x20ca -#define mmGDS_GWS_VMID10_BASE_IDX 0 -#define mmGDS_GWS_VMID11 0x20cb -#define mmGDS_GWS_VMID11_BASE_IDX 0 -#define mmGDS_GWS_VMID12 0x20cc -#define mmGDS_GWS_VMID12_BASE_IDX 0 -#define mmGDS_GWS_VMID13 0x20cd -#define mmGDS_GWS_VMID13_BASE_IDX 0 -#define mmGDS_GWS_VMID14 0x20ce -#define mmGDS_GWS_VMID14_BASE_IDX 0 -#define mmGDS_GWS_VMID15 0x20cf -#define mmGDS_GWS_VMID15_BASE_IDX 0 -#define mmGDS_OA_VMID0 0x20d0 -#define mmGDS_OA_VMID0_BASE_IDX 0 -#define mmGDS_OA_VMID1 0x20d1 -#define mmGDS_OA_VMID1_BASE_IDX 0 -#define mmGDS_OA_VMID2 0x20d2 -#define mmGDS_OA_VMID2_BASE_IDX 0 -#define mmGDS_OA_VMID3 0x20d3 -#define mmGDS_OA_VMID3_BASE_IDX 0 -#define mmGDS_OA_VMID4 0x20d4 -#define mmGDS_OA_VMID4_BASE_IDX 0 -#define mmGDS_OA_VMID5 0x20d5 -#define mmGDS_OA_VMID5_BASE_IDX 0 -#define mmGDS_OA_VMID6 0x20d6 -#define mmGDS_OA_VMID6_BASE_IDX 0 -#define mmGDS_OA_VMID7 0x20d7 -#define mmGDS_OA_VMID7_BASE_IDX 0 -#define mmGDS_OA_VMID8 0x20d8 -#define mmGDS_OA_VMID8_BASE_IDX 0 -#define mmGDS_OA_VMID9 0x20d9 -#define mmGDS_OA_VMID9_BASE_IDX 0 -#define mmGDS_OA_VMID10 0x20da -#define mmGDS_OA_VMID10_BASE_IDX 0 -#define mmGDS_OA_VMID11 0x20db -#define mmGDS_OA_VMID11_BASE_IDX 0 -#define mmGDS_OA_VMID12 0x20dc -#define mmGDS_OA_VMID12_BASE_IDX 0 -#define mmGDS_OA_VMID13 0x20dd -#define mmGDS_OA_VMID13_BASE_IDX 0 -#define mmGDS_OA_VMID14 0x20de -#define mmGDS_OA_VMID14_BASE_IDX 0 -#define mmGDS_OA_VMID15 0x20df -#define mmGDS_OA_VMID15_BASE_IDX 0 -#define mmGDS_GWS_RESET0 0x20e4 -#define mmGDS_GWS_RESET0_BASE_IDX 0 -#define mmGDS_GWS_RESET1 0x20e5 -#define mmGDS_GWS_RESET1_BASE_IDX 0 -#define mmGDS_GWS_RESOURCE_RESET 0x20e6 -#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 -#define mmGDS_COMPUTE_MAX_WAVE_ID 0x20e8 -#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 -#define mmGDS_OA_RESET_MASK 0x20e9 -#define mmGDS_OA_RESET_MASK_BASE_IDX 0 -#define mmGDS_OA_RESET 0x20ea -#define mmGDS_OA_RESET_BASE_IDX 0 -#define mmGDS_ENHANCE2 0x20eb -#define mmGDS_ENHANCE2_BASE_IDX 0 -#define mmGDS_OA_CGPG_RESTORE 0x20ec -#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 -#define mmGDS_CS_CTXSW_STATUS 0x20ed -#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 -#define mmGDS_CS_CTXSW_CNT0 0x20ee -#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 -#define mmGDS_CS_CTXSW_CNT1 0x20ef -#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 -#define mmGDS_CS_CTXSW_CNT2 0x20f0 -#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 -#define mmGDS_CS_CTXSW_CNT3 0x20f1 -#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 -#define mmGDS_GFX_CTXSW_STATUS 0x20f2 -#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 -#define mmGDS_VS_CTXSW_CNT0 0x20f3 -#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 -#define mmGDS_VS_CTXSW_CNT1 0x20f4 -#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 -#define mmGDS_VS_CTXSW_CNT2 0x20f5 -#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 -#define mmGDS_VS_CTXSW_CNT3 0x20f6 -#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 -#define mmGDS_PS_CTXSW_CNT0 0x20f7 -#define mmGDS_PS_CTXSW_CNT0_BASE_IDX 0 -#define mmGDS_PS_CTXSW_CNT1 0x20f8 -#define mmGDS_PS_CTXSW_CNT1_BASE_IDX 0 -#define mmGDS_PS_CTXSW_CNT2 0x20f9 -#define mmGDS_PS_CTXSW_CNT2_BASE_IDX 0 -#define mmGDS_PS_CTXSW_CNT3 0x20fa -#define mmGDS_PS_CTXSW_CNT3_BASE_IDX 0 -#define mmGDS_PS_CTXSW_IDX 0x20fb -#define mmGDS_PS_CTXSW_IDX_BASE_IDX 0 -#define mmGDS_GS_CTXSW_CNT0 0x2117 -#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 -#define mmGDS_GS_CTXSW_CNT1 0x2118 -#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 -#define mmGDS_GS_CTXSW_CNT2 0x2119 -#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 -#define mmGDS_GS_CTXSW_CNT3 0x211a -#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 -#define mmGDS_MEMORY_CLEAN 0x211f -#define mmGDS_MEMORY_CLEAN_BASE_IDX 0 - - -// addressBlock: gc_gfxdec0 -// base address: 0x28000 -#define mmDB_RENDER_CONTROL 0x0000 -#define mmDB_RENDER_CONTROL_BASE_IDX 1 -#define mmDB_COUNT_CONTROL 0x0001 -#define mmDB_COUNT_CONTROL_BASE_IDX 1 -#define mmDB_DEPTH_VIEW 0x0002 -#define mmDB_DEPTH_VIEW_BASE_IDX 1 -#define mmDB_RENDER_OVERRIDE 0x0003 -#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 -#define mmDB_RENDER_OVERRIDE2 0x0004 -#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 -#define mmDB_HTILE_DATA_BASE 0x0005 -#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 -#define mmDB_DEPTH_SIZE_XY 0x0007 -#define mmDB_DEPTH_SIZE_XY_BASE_IDX 1 -#define mmDB_DEPTH_BOUNDS_MIN 0x0008 -#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 -#define mmDB_DEPTH_BOUNDS_MAX 0x0009 -#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 -#define mmDB_STENCIL_CLEAR 0x000a -#define mmDB_STENCIL_CLEAR_BASE_IDX 1 -#define mmDB_DEPTH_CLEAR 0x000b -#define mmDB_DEPTH_CLEAR_BASE_IDX 1 -#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c -#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 -#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d -#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 -#define mmDB_DFSM_CONTROL 0x000e -#define mmDB_DFSM_CONTROL_BASE_IDX 1 -#define mmDB_RESERVED_REG_2 0x000f -#define mmDB_RESERVED_REG_2_BASE_IDX 1 -#define mmDB_Z_INFO 0x0010 -#define mmDB_Z_INFO_BASE_IDX 1 -#define mmDB_STENCIL_INFO 0x0011 -#define mmDB_STENCIL_INFO_BASE_IDX 1 -#define mmDB_Z_READ_BASE 0x0012 -#define mmDB_Z_READ_BASE_BASE_IDX 1 -#define mmDB_STENCIL_READ_BASE 0x0013 -#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 -#define mmDB_Z_WRITE_BASE 0x0014 -#define mmDB_Z_WRITE_BASE_BASE_IDX 1 -#define mmDB_STENCIL_WRITE_BASE 0x0015 -#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 -#define mmDB_RESERVED_REG_1 0x0016 -#define mmDB_RESERVED_REG_1_BASE_IDX 1 -#define mmDB_RESERVED_REG_3 0x0017 -#define mmDB_RESERVED_REG_3_BASE_IDX 1 -#define mmDB_VRS_OVERRIDE_CNTL 0x0019 -#define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX 1 -#define mmDB_Z_READ_BASE_HI 0x001a -#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 -#define mmDB_STENCIL_READ_BASE_HI 0x001b -#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 -#define mmDB_Z_WRITE_BASE_HI 0x001c -#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 -#define mmDB_STENCIL_WRITE_BASE_HI 0x001d -#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 -#define mmDB_HTILE_DATA_BASE_HI 0x001e -#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 -#define mmDB_RMI_L2_CACHE_CONTROL 0x001f -#define mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1 -#define mmTA_BC_BASE_ADDR 0x0020 -#define mmTA_BC_BASE_ADDR_BASE_IDX 1 -#define mmTA_BC_BASE_ADDR_HI 0x0021 -#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmCOHER_DEST_BASE_HI_0 0x007a -#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 -#define mmCOHER_DEST_BASE_HI_1 0x007b -#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 -#define mmCOHER_DEST_BASE_HI_2 0x007c -#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 -#define mmCOHER_DEST_BASE_HI_3 0x007d -#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 -#define mmCOHER_DEST_BASE_2 0x007e -#define mmCOHER_DEST_BASE_2_BASE_IDX 1 -#define mmCOHER_DEST_BASE_3 0x007f -#define mmCOHER_DEST_BASE_3_BASE_IDX 1 -#define mmPA_SC_WINDOW_OFFSET 0x0080 -#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 -#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 -#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 -#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 -#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_RULE 0x0083 -#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_0_TL 0x0084 -#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_0_BR 0x0085 -#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_1_TL 0x0086 -#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_1_BR 0x0087 -#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_2_TL 0x0088 -#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_2_BR 0x0089 -#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_3_TL 0x008a -#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 -#define mmPA_SC_CLIPRECT_3_BR 0x008b -#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 -#define mmPA_SC_EDGERULE 0x008c -#define mmPA_SC_EDGERULE_BASE_IDX 1 -#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d -#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 -#define mmCB_TARGET_MASK 0x008e -#define mmCB_TARGET_MASK_BASE_IDX 1 -#define mmCB_SHADER_MASK 0x008f -#define mmCB_SHADER_MASK_BASE_IDX 1 -#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 -#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 -#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 -#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 -#define mmCOHER_DEST_BASE_0 0x0092 -#define mmCOHER_DEST_BASE_0_BASE_IDX 1 -#define mmCOHER_DEST_BASE_1 0x0093 -#define mmCOHER_DEST_BASE_1_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 -#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 -#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 -#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 -#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 -#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 -#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a -#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b -#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c -#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d -#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e -#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f -#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 -#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 -#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 -#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 -#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 -#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 -#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 -#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 -#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 -#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 -#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa -#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab -#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac -#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad -#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae -#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af -#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 -#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 -#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 -#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 -#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 -#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_0 0x00b4 -#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_0 0x00b5 -#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_1 0x00b6 -#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_1 0x00b7 -#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_2 0x00b8 -#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_2 0x00b9 -#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_3 0x00ba -#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_3 0x00bb -#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_4 0x00bc -#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_4 0x00bd -#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_5 0x00be -#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_5 0x00bf -#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_6 0x00c0 -#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_6 0x00c1 -#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_7 0x00c2 -#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_7 0x00c3 -#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_8 0x00c4 -#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_8 0x00c5 -#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_9 0x00c6 -#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_9 0x00c7 -#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_10 0x00c8 -#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_10 0x00c9 -#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_11 0x00ca -#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_11 0x00cb -#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_12 0x00cc -#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_12 0x00cd -#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_13 0x00ce -#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_13 0x00cf -#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_14 0x00d0 -#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_14 0x00d1 -#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMIN_15 0x00d2 -#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 -#define mmPA_SC_VPORT_ZMAX_15 0x00d3 -#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 -#define mmPA_SC_RASTER_CONFIG 0x00d4 -#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 -#define mmPA_SC_RASTER_CONFIG_1 0x00d5 -#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 -#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 -#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 -#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 -#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 -#define mmCP_PERFMON_CNTX_CNTL 0x00d8 -#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 -#define mmCP_PIPEID 0x00d9 -#define mmCP_PIPEID_BASE_IDX 1 -#define mmCP_RINGID 0x00d9 -#define mmCP_RINGID_BASE_IDX 1 -#define mmCP_VMID 0x00da -#define mmCP_VMID_BASE_IDX 1 -#define mmCONTEXT_RESERVED_REG0 0x00db -#define mmCONTEXT_RESERVED_REG0_BASE_IDX 1 -#define mmCONTEXT_RESERVED_REG1 0x00dc -#define mmCONTEXT_RESERVED_REG1_BASE_IDX 1 -#define mmVGT_MAX_VTX_INDX 0x0100 -#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 -#define mmVGT_MIN_VTX_INDX 0x0101 -#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 -#define mmVGT_INDX_OFFSET 0x0102 -#define mmVGT_INDX_OFFSET_BASE_IDX 1 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 -#define mmCB_RMI_GL2_CACHE_CONTROL 0x0104 -#define mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 -#define mmCB_BLEND_RED 0x0105 -#define mmCB_BLEND_RED_BASE_IDX 1 -#define mmCB_BLEND_GREEN 0x0106 -#define mmCB_BLEND_GREEN_BASE_IDX 1 -#define mmCB_BLEND_BLUE 0x0107 -#define mmCB_BLEND_BLUE_BASE_IDX 1 -#define mmCB_BLEND_ALPHA 0x0108 -#define mmCB_BLEND_ALPHA_BASE_IDX 1 -#define mmCB_DCC_CONTROL 0x0109 -#define mmCB_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COVERAGE_OUT_CONTROL 0x010a -#define mmCB_COVERAGE_OUT_CONTROL_BASE_IDX 1 -#define mmDB_STENCIL_CONTROL 0x010b -#define mmDB_STENCIL_CONTROL_BASE_IDX 1 -#define mmDB_STENCILREFMASK 0x010c -#define mmDB_STENCILREFMASK_BASE_IDX 1 -#define mmDB_STENCILREFMASK_BF 0x010d -#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE 0x010f -#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET 0x0110 -#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE 0x0111 -#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET 0x0112 -#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE 0x0113 -#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET 0x0114 -#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_1 0x0115 -#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_1 0x0116 -#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_1 0x0117 -#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_1 0x0118 -#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_1 0x0119 -#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_1 0x011a -#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_2 0x011b -#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_2 0x011c -#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_2 0x011d -#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_2 0x011e -#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_2 0x011f -#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 -#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_3 0x0121 -#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_3 0x0122 -#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_3 0x0123 -#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_3 0x0124 -#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_3 0x0125 -#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 -#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_4 0x0127 -#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_4 0x0128 -#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_4 0x0129 -#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_4 0x012a -#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_4 0x012b -#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_4 0x012c -#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_5 0x012d -#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_5 0x012e -#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_5 0x012f -#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_5 0x0130 -#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_5 0x0131 -#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 -#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_6 0x0133 -#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_6 0x0134 -#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_6 0x0135 -#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_6 0x0136 -#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_6 0x0137 -#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 -#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_7 0x0139 -#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_7 0x013a -#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_7 0x013b -#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_7 0x013c -#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_7 0x013d -#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_7 0x013e -#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_8 0x013f -#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_8 0x0140 -#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_8 0x0141 -#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_8 0x0142 -#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_8 0x0143 -#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 -#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_9 0x0145 -#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_9 0x0146 -#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_9 0x0147 -#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_9 0x0148 -#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_9 0x0149 -#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_9 0x014a -#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_10 0x014b -#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_10 0x014c -#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_10 0x014d -#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_10 0x014e -#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_10 0x014f -#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 -#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_11 0x0151 -#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_11 0x0152 -#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_11 0x0153 -#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_11 0x0154 -#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_11 0x0155 -#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 -#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_12 0x0157 -#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_12 0x0158 -#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_12 0x0159 -#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_12 0x015a -#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_12 0x015b -#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_12 0x015c -#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_13 0x015d -#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_13 0x015e -#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_13 0x015f -#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_13 0x0160 -#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_13 0x0161 -#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 -#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_14 0x0163 -#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_14 0x0164 -#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_14 0x0165 -#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_14 0x0166 -#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_14 0x0167 -#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 -#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 -#define mmPA_CL_VPORT_XSCALE_15 0x0169 -#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 -#define mmPA_CL_VPORT_XOFFSET_15 0x016a -#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 -#define mmPA_CL_VPORT_YSCALE_15 0x016b -#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 -#define mmPA_CL_VPORT_YOFFSET_15 0x016c -#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 -#define mmPA_CL_VPORT_ZSCALE_15 0x016d -#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 -#define mmPA_CL_VPORT_ZOFFSET_15 0x016e -#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 -#define mmPA_CL_UCP_0_X 0x016f -#define mmPA_CL_UCP_0_X_BASE_IDX 1 -#define mmPA_CL_UCP_0_Y 0x0170 -#define mmPA_CL_UCP_0_Y_BASE_IDX 1 -#define mmPA_CL_UCP_0_Z 0x0171 -#define mmPA_CL_UCP_0_Z_BASE_IDX 1 -#define mmPA_CL_UCP_0_W 0x0172 -#define mmPA_CL_UCP_0_W_BASE_IDX 1 -#define mmPA_CL_UCP_1_X 0x0173 -#define mmPA_CL_UCP_1_X_BASE_IDX 1 -#define mmPA_CL_UCP_1_Y 0x0174 -#define mmPA_CL_UCP_1_Y_BASE_IDX 1 -#define mmPA_CL_UCP_1_Z 0x0175 -#define mmPA_CL_UCP_1_Z_BASE_IDX 1 -#define mmPA_CL_UCP_1_W 0x0176 -#define mmPA_CL_UCP_1_W_BASE_IDX 1 -#define mmPA_CL_UCP_2_X 0x0177 -#define mmPA_CL_UCP_2_X_BASE_IDX 1 -#define mmPA_CL_UCP_2_Y 0x0178 -#define mmPA_CL_UCP_2_Y_BASE_IDX 1 -#define mmPA_CL_UCP_2_Z 0x0179 -#define mmPA_CL_UCP_2_Z_BASE_IDX 1 -#define mmPA_CL_UCP_2_W 0x017a -#define mmPA_CL_UCP_2_W_BASE_IDX 1 -#define mmPA_CL_UCP_3_X 0x017b -#define mmPA_CL_UCP_3_X_BASE_IDX 1 -#define mmPA_CL_UCP_3_Y 0x017c -#define mmPA_CL_UCP_3_Y_BASE_IDX 1 -#define mmPA_CL_UCP_3_Z 0x017d -#define mmPA_CL_UCP_3_Z_BASE_IDX 1 -#define mmPA_CL_UCP_3_W 0x017e -#define mmPA_CL_UCP_3_W_BASE_IDX 1 -#define mmPA_CL_UCP_4_X 0x017f -#define mmPA_CL_UCP_4_X_BASE_IDX 1 -#define mmPA_CL_UCP_4_Y 0x0180 -#define mmPA_CL_UCP_4_Y_BASE_IDX 1 -#define mmPA_CL_UCP_4_Z 0x0181 -#define mmPA_CL_UCP_4_Z_BASE_IDX 1 -#define mmPA_CL_UCP_4_W 0x0182 -#define mmPA_CL_UCP_4_W_BASE_IDX 1 -#define mmPA_CL_UCP_5_X 0x0183 -#define mmPA_CL_UCP_5_X_BASE_IDX 1 -#define mmPA_CL_UCP_5_Y 0x0184 -#define mmPA_CL_UCP_5_Y_BASE_IDX 1 -#define mmPA_CL_UCP_5_Z 0x0185 -#define mmPA_CL_UCP_5_Z_BASE_IDX 1 -#define mmPA_CL_UCP_5_W 0x0186 -#define mmPA_CL_UCP_5_W_BASE_IDX 1 -#define mmPA_CL_PROG_NEAR_CLIP_Z 0x0187 -#define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_0 0x0191 -#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_1 0x0192 -#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_2 0x0193 -#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_3 0x0194 -#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_4 0x0195 -#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_5 0x0196 -#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_6 0x0197 -#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_7 0x0198 -#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_8 0x0199 -#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_9 0x019a -#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_10 0x019b -#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_11 0x019c -#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_12 0x019d -#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_13 0x019e -#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_14 0x019f -#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_15 0x01a0 -#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_16 0x01a1 -#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_17 0x01a2 -#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_18 0x01a3 -#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_19 0x01a4 -#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_20 0x01a5 -#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_21 0x01a6 -#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_22 0x01a7 -#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_23 0x01a8 -#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_24 0x01a9 -#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_25 0x01aa -#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_26 0x01ab -#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_27 0x01ac -#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_28 0x01ad -#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_29 0x01ae -#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_30 0x01af -#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 -#define mmSPI_PS_INPUT_CNTL_31 0x01b0 -#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 -#define mmSPI_VS_OUT_CONFIG 0x01b1 -#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 -#define mmSPI_PS_INPUT_ENA 0x01b3 -#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 -#define mmSPI_PS_INPUT_ADDR 0x01b4 -#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 -#define mmSPI_INTERP_CONTROL_0 0x01b5 -#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 -#define mmSPI_PS_IN_CONTROL 0x01b6 -#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 -#define mmSPI_BARYC_CNTL 0x01b8 -#define mmSPI_BARYC_CNTL_BASE_IDX 1 -#define mmSPI_TMPRING_SIZE 0x01ba -#define mmSPI_TMPRING_SIZE_BASE_IDX 1 -#define mmSPI_SHADER_IDX_FORMAT 0x01c2 -#define mmSPI_SHADER_IDX_FORMAT_BASE_IDX 1 -#define mmSPI_SHADER_POS_FORMAT 0x01c3 -#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 -#define mmSPI_SHADER_Z_FORMAT 0x01c4 -#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 -#define mmSPI_SHADER_COL_FORMAT 0x01c5 -#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 -#define mmSX_PS_DOWNCONVERT_CONTROL 0x01d4 -#define mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 -#define mmSX_PS_DOWNCONVERT 0x01d5 -#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 -#define mmSX_BLEND_OPT_EPSILON 0x01d6 -#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 -#define mmSX_BLEND_OPT_CONTROL 0x01d7 -#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 -#define mmSX_MRT0_BLEND_OPT 0x01d8 -#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT1_BLEND_OPT 0x01d9 -#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT2_BLEND_OPT 0x01da -#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT3_BLEND_OPT 0x01db -#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT4_BLEND_OPT 0x01dc -#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT5_BLEND_OPT 0x01dd -#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT6_BLEND_OPT 0x01de -#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 -#define mmSX_MRT7_BLEND_OPT 0x01df -#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 -#define mmCB_BLEND0_CONTROL 0x01e0 -#define mmCB_BLEND0_CONTROL_BASE_IDX 1 -#define mmCB_BLEND1_CONTROL 0x01e1 -#define mmCB_BLEND1_CONTROL_BASE_IDX 1 -#define mmCB_BLEND2_CONTROL 0x01e2 -#define mmCB_BLEND2_CONTROL_BASE_IDX 1 -#define mmCB_BLEND3_CONTROL 0x01e3 -#define mmCB_BLEND3_CONTROL_BASE_IDX 1 -#define mmCB_BLEND4_CONTROL 0x01e4 -#define mmCB_BLEND4_CONTROL_BASE_IDX 1 -#define mmCB_BLEND5_CONTROL 0x01e5 -#define mmCB_BLEND5_CONTROL_BASE_IDX 1 -#define mmCB_BLEND6_CONTROL 0x01e6 -#define mmCB_BLEND6_CONTROL_BASE_IDX 1 -#define mmCB_BLEND7_CONTROL 0x01e7 -#define mmCB_BLEND7_CONTROL_BASE_IDX 1 -#define mmCS_COPY_STATE 0x01f3 -#define mmCS_COPY_STATE_BASE_IDX 1 -#define mmGFX_COPY_STATE 0x01f4 -#define mmGFX_COPY_STATE_BASE_IDX 1 -#define mmPA_CL_POINT_X_RAD 0x01f5 -#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 -#define mmPA_CL_POINT_Y_RAD 0x01f6 -#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 -#define mmPA_CL_POINT_SIZE 0x01f7 -#define mmPA_CL_POINT_SIZE_BASE_IDX 1 -#define mmPA_CL_POINT_CULL_RAD 0x01f8 -#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 -#define mmVGT_DMA_BASE_HI 0x01f9 -#define mmVGT_DMA_BASE_HI_BASE_IDX 1 -#define mmVGT_DMA_BASE 0x01fa -#define mmVGT_DMA_BASE_BASE_IDX 1 -#define mmVGT_DRAW_INITIATOR 0x01fc -#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 -#define mmVGT_IMMED_DATA 0x01fd -#define mmVGT_IMMED_DATA_BASE_IDX 1 -#define mmVGT_EVENT_ADDRESS_REG 0x01fe -#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 -#define mmGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff -#define mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 -#define mmDB_DEPTH_CONTROL 0x0200 -#define mmDB_DEPTH_CONTROL_BASE_IDX 1 -#define mmDB_EQAA 0x0201 -#define mmDB_EQAA_BASE_IDX 1 -#define mmCB_COLOR_CONTROL 0x0202 -#define mmCB_COLOR_CONTROL_BASE_IDX 1 -#define mmDB_SHADER_CONTROL 0x0203 -#define mmDB_SHADER_CONTROL_BASE_IDX 1 -#define mmPA_CL_CLIP_CNTL 0x0204 -#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 -#define mmPA_SU_SC_MODE_CNTL 0x0205 -#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 -#define mmPA_CL_VTE_CNTL 0x0206 -#define mmPA_CL_VTE_CNTL_BASE_IDX 1 -#define mmPA_CL_VS_OUT_CNTL 0x0207 -#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 -#define mmPA_CL_NANINF_CNTL 0x0208 -#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 -#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 -#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 -#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a -#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 -#define mmPA_SU_PRIM_FILTER_CNTL 0x020b -#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 -#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c -#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 -#define mmPA_CL_NGG_CNTL 0x020e -#define mmPA_CL_NGG_CNTL_BASE_IDX 1 -#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f -#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 -#define mmPA_STEREO_CNTL 0x0210 -#define mmPA_STEREO_CNTL_BASE_IDX 1 -#define mmPA_STATE_STEREO_X 0x0211 -#define mmPA_STATE_STEREO_X_BASE_IDX 1 -#define mmPA_CL_VRS_CNTL 0x0212 -#define mmPA_CL_VRS_CNTL_BASE_IDX 1 -#define mmPA_SU_POINT_SIZE 0x0280 -#define mmPA_SU_POINT_SIZE_BASE_IDX 1 -#define mmPA_SU_POINT_MINMAX 0x0281 -#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 -#define mmPA_SU_LINE_CNTL 0x0282 -#define mmPA_SU_LINE_CNTL_BASE_IDX 1 -#define mmPA_SC_LINE_STIPPLE 0x0283 -#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 -#define mmVGT_OUTPUT_PATH_CNTL 0x0284 -#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 -#define mmVGT_HOS_CNTL 0x0285 -#define mmVGT_HOS_CNTL_BASE_IDX 1 -#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 -#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 -#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 -#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 -#define mmVGT_HOS_REUSE_DEPTH 0x0288 -#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 -#define mmVGT_GROUP_PRIM_TYPE 0x0289 -#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 -#define mmVGT_GROUP_FIRST_DECR 0x028a -#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 -#define mmVGT_GROUP_DECR 0x028b -#define mmVGT_GROUP_DECR_BASE_IDX 1 -#define mmVGT_GROUP_VECT_0_CNTL 0x028c -#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 -#define mmVGT_GROUP_VECT_1_CNTL 0x028d -#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 -#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e -#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 -#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f -#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 -#define mmVGT_GS_MODE 0x0290 -#define mmVGT_GS_MODE_BASE_IDX 1 -#define mmVGT_GS_ONCHIP_CNTL 0x0291 -#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 -#define mmPA_SC_MODE_CNTL_0 0x0292 -#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 -#define mmPA_SC_MODE_CNTL_1 0x0293 -#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 -#define mmVGT_ENHANCE 0x0294 -#define mmVGT_ENHANCE_BASE_IDX 1 -#define mmVGT_GS_PER_ES 0x0295 -#define mmVGT_GS_PER_ES_BASE_IDX 1 -#define mmVGT_ES_PER_GS 0x0296 -#define mmVGT_ES_PER_GS_BASE_IDX 1 -#define mmVGT_GS_PER_VS 0x0297 -#define mmVGT_GS_PER_VS_BASE_IDX 1 -#define mmVGT_GSVS_RING_OFFSET_1 0x0298 -#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 -#define mmVGT_GSVS_RING_OFFSET_2 0x0299 -#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 -#define mmVGT_GSVS_RING_OFFSET_3 0x029a -#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 -#define mmVGT_GS_OUT_PRIM_TYPE 0x029b -#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 -#define mmIA_ENHANCE 0x029c -#define mmIA_ENHANCE_BASE_IDX 1 -#define mmVGT_DMA_SIZE 0x029d -#define mmVGT_DMA_SIZE_BASE_IDX 1 -#define mmVGT_DMA_MAX_SIZE 0x029e -#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 -#define mmVGT_DMA_INDEX_TYPE 0x029f -#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 -#define mmWD_ENHANCE 0x02a0 -#define mmWD_ENHANCE_BASE_IDX 1 -#define mmVGT_PRIMITIVEID_EN 0x02a1 -#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 -#define mmVGT_DMA_NUM_INSTANCES 0x02a2 -#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 -#define mmVGT_PRIMITIVEID_RESET 0x02a3 -#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 -#define mmVGT_EVENT_INITIATOR 0x02a4 -#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 -#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x02a5 -#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 -#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 -#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 -#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 -#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 -#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 -#define mmIA_MULTI_VGT_PARAM 0x02aa -#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 -#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab -#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 -#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac -#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 -#define mmVGT_REUSE_OFF 0x02ad -#define mmVGT_REUSE_OFF_BASE_IDX 1 -#define mmVGT_VTX_CNT_EN 0x02ae -#define mmVGT_VTX_CNT_EN_BASE_IDX 1 -#define mmDB_HTILE_SURFACE 0x02af -#define mmDB_HTILE_SURFACE_BASE_IDX 1 -#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 -#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 -#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 -#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 -#define mmDB_PRELOAD_CONTROL 0x02b2 -#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 -#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 -#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 -#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 -#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 -#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 -#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 -#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb -#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc -#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 -#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd -#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf -#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 -#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 -#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 -#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 -#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 -#define mmVGT_GS_MAX_VERT_OUT 0x02ce -#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 -#define mmGE_NGG_SUBGRP_CNTL 0x02d3 -#define mmGE_NGG_SUBGRP_CNTL_BASE_IDX 1 -#define mmVGT_TESS_DISTRIBUTION 0x02d4 -#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 -#define mmVGT_SHADER_STAGES_EN 0x02d5 -#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 -#define mmVGT_LS_HS_CONFIG 0x02d6 -#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 -#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 -#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 -#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 -#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 -#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 -#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 -#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da -#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 -#define mmVGT_TF_PARAM 0x02db -#define mmVGT_TF_PARAM_BASE_IDX 1 -#define mmDB_ALPHA_TO_MASK 0x02dc -#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 -#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd -#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df -#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 -#define mmVGT_GS_INSTANCE_CNT 0x02e4 -#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 -#define mmVGT_STRMOUT_CONFIG 0x02e5 -#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 -#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 -#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 -#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 -#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 -#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 -#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 -#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 -#define mmPA_SC_LINE_CNTL 0x02f7 -#define mmPA_SC_LINE_CNTL_BASE_IDX 1 -#define mmPA_SC_AA_CONFIG 0x02f8 -#define mmPA_SC_AA_CONFIG_BASE_IDX 1 -#define mmPA_SU_VTX_CNTL 0x02f9 -#define mmPA_SU_VTX_CNTL_BASE_IDX 1 -#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa -#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 -#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb -#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 -#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc -#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 -#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd -#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 -#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e -#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 -#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f -#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 -#define mmPA_SC_SHADER_CONTROL 0x0310 -#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 -#define mmPA_SC_BINNER_CNTL_0 0x0311 -#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 -#define mmPA_SC_BINNER_CNTL_1 0x0312 -#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 -#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 -#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 -#define mmPA_SC_NGG_MODE_CNTL 0x0314 -#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 -#define mmVGT_OUT_DEALLOC_CNTL 0x0317 -#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 -#define mmCB_COLOR0_BASE 0x0318 -#define mmCB_COLOR0_BASE_BASE_IDX 1 -#define mmCB_COLOR0_PITCH 0x0319 -#define mmCB_COLOR0_PITCH_BASE_IDX 1 -#define mmCB_COLOR0_SLICE 0x031a -#define mmCB_COLOR0_SLICE_BASE_IDX 1 -#define mmCB_COLOR0_VIEW 0x031b -#define mmCB_COLOR0_VIEW_BASE_IDX 1 -#define mmCB_COLOR0_INFO 0x031c -#define mmCB_COLOR0_INFO_BASE_IDX 1 -#define mmCB_COLOR0_ATTRIB 0x031d -#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR0_DCC_CONTROL 0x031e -#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR0_CMASK 0x031f -#define mmCB_COLOR0_CMASK_BASE_IDX 1 -#define mmCB_COLOR0_CMASK_SLICE 0x0320 -#define mmCB_COLOR0_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR0_FMASK 0x0321 -#define mmCB_COLOR0_FMASK_BASE_IDX 1 -#define mmCB_COLOR0_FMASK_SLICE 0x0322 -#define mmCB_COLOR0_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR0_CLEAR_WORD0 0x0323 -#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR0_CLEAR_WORD1 0x0324 -#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR0_DCC_BASE 0x0325 -#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR1_BASE 0x0327 -#define mmCB_COLOR1_BASE_BASE_IDX 1 -#define mmCB_COLOR1_PITCH 0x0328 -#define mmCB_COLOR1_PITCH_BASE_IDX 1 -#define mmCB_COLOR1_SLICE 0x0329 -#define mmCB_COLOR1_SLICE_BASE_IDX 1 -#define mmCB_COLOR1_VIEW 0x032a -#define mmCB_COLOR1_VIEW_BASE_IDX 1 -#define mmCB_COLOR1_INFO 0x032b -#define mmCB_COLOR1_INFO_BASE_IDX 1 -#define mmCB_COLOR1_ATTRIB 0x032c -#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR1_DCC_CONTROL 0x032d -#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR1_CMASK 0x032e -#define mmCB_COLOR1_CMASK_BASE_IDX 1 -#define mmCB_COLOR1_CMASK_SLICE 0x032f -#define mmCB_COLOR1_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR1_FMASK 0x0330 -#define mmCB_COLOR1_FMASK_BASE_IDX 1 -#define mmCB_COLOR1_FMASK_SLICE 0x0331 -#define mmCB_COLOR1_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR1_CLEAR_WORD0 0x0332 -#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR1_CLEAR_WORD1 0x0333 -#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR1_DCC_BASE 0x0334 -#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR2_BASE 0x0336 -#define mmCB_COLOR2_BASE_BASE_IDX 1 -#define mmCB_COLOR2_PITCH 0x0337 -#define mmCB_COLOR2_PITCH_BASE_IDX 1 -#define mmCB_COLOR2_SLICE 0x0338 -#define mmCB_COLOR2_SLICE_BASE_IDX 1 -#define mmCB_COLOR2_VIEW 0x0339 -#define mmCB_COLOR2_VIEW_BASE_IDX 1 -#define mmCB_COLOR2_INFO 0x033a -#define mmCB_COLOR2_INFO_BASE_IDX 1 -#define mmCB_COLOR2_ATTRIB 0x033b -#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR2_DCC_CONTROL 0x033c -#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR2_CMASK 0x033d -#define mmCB_COLOR2_CMASK_BASE_IDX 1 -#define mmCB_COLOR2_CMASK_SLICE 0x033e -#define mmCB_COLOR2_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR2_FMASK 0x033f -#define mmCB_COLOR2_FMASK_BASE_IDX 1 -#define mmCB_COLOR2_FMASK_SLICE 0x0340 -#define mmCB_COLOR2_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR2_CLEAR_WORD0 0x0341 -#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR2_CLEAR_WORD1 0x0342 -#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR2_DCC_BASE 0x0343 -#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR3_BASE 0x0345 -#define mmCB_COLOR3_BASE_BASE_IDX 1 -#define mmCB_COLOR3_PITCH 0x0346 -#define mmCB_COLOR3_PITCH_BASE_IDX 1 -#define mmCB_COLOR3_SLICE 0x0347 -#define mmCB_COLOR3_SLICE_BASE_IDX 1 -#define mmCB_COLOR3_VIEW 0x0348 -#define mmCB_COLOR3_VIEW_BASE_IDX 1 -#define mmCB_COLOR3_INFO 0x0349 -#define mmCB_COLOR3_INFO_BASE_IDX 1 -#define mmCB_COLOR3_ATTRIB 0x034a -#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR3_DCC_CONTROL 0x034b -#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR3_CMASK 0x034c -#define mmCB_COLOR3_CMASK_BASE_IDX 1 -#define mmCB_COLOR3_CMASK_SLICE 0x034d -#define mmCB_COLOR3_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR3_FMASK 0x034e -#define mmCB_COLOR3_FMASK_BASE_IDX 1 -#define mmCB_COLOR3_FMASK_SLICE 0x034f -#define mmCB_COLOR3_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR3_CLEAR_WORD0 0x0350 -#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR3_CLEAR_WORD1 0x0351 -#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR3_DCC_BASE 0x0352 -#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR4_BASE 0x0354 -#define mmCB_COLOR4_BASE_BASE_IDX 1 -#define mmCB_COLOR4_PITCH 0x0355 -#define mmCB_COLOR4_PITCH_BASE_IDX 1 -#define mmCB_COLOR4_SLICE 0x0356 -#define mmCB_COLOR4_SLICE_BASE_IDX 1 -#define mmCB_COLOR4_VIEW 0x0357 -#define mmCB_COLOR4_VIEW_BASE_IDX 1 -#define mmCB_COLOR4_INFO 0x0358 -#define mmCB_COLOR4_INFO_BASE_IDX 1 -#define mmCB_COLOR4_ATTRIB 0x0359 -#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR4_DCC_CONTROL 0x035a -#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR4_CMASK 0x035b -#define mmCB_COLOR4_CMASK_BASE_IDX 1 -#define mmCB_COLOR4_CMASK_SLICE 0x035c -#define mmCB_COLOR4_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR4_FMASK 0x035d -#define mmCB_COLOR4_FMASK_BASE_IDX 1 -#define mmCB_COLOR4_FMASK_SLICE 0x035e -#define mmCB_COLOR4_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR4_CLEAR_WORD0 0x035f -#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR4_CLEAR_WORD1 0x0360 -#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR4_DCC_BASE 0x0361 -#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR5_BASE 0x0363 -#define mmCB_COLOR5_BASE_BASE_IDX 1 -#define mmCB_COLOR5_PITCH 0x0364 -#define mmCB_COLOR5_PITCH_BASE_IDX 1 -#define mmCB_COLOR5_SLICE 0x0365 -#define mmCB_COLOR5_SLICE_BASE_IDX 1 -#define mmCB_COLOR5_VIEW 0x0366 -#define mmCB_COLOR5_VIEW_BASE_IDX 1 -#define mmCB_COLOR5_INFO 0x0367 -#define mmCB_COLOR5_INFO_BASE_IDX 1 -#define mmCB_COLOR5_ATTRIB 0x0368 -#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR5_DCC_CONTROL 0x0369 -#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR5_CMASK 0x036a -#define mmCB_COLOR5_CMASK_BASE_IDX 1 -#define mmCB_COLOR5_CMASK_SLICE 0x036b -#define mmCB_COLOR5_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR5_FMASK 0x036c -#define mmCB_COLOR5_FMASK_BASE_IDX 1 -#define mmCB_COLOR5_FMASK_SLICE 0x036d -#define mmCB_COLOR5_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR5_CLEAR_WORD0 0x036e -#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR5_CLEAR_WORD1 0x036f -#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR5_DCC_BASE 0x0370 -#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR6_BASE 0x0372 -#define mmCB_COLOR6_BASE_BASE_IDX 1 -#define mmCB_COLOR6_PITCH 0x0373 -#define mmCB_COLOR6_PITCH_BASE_IDX 1 -#define mmCB_COLOR6_SLICE 0x0374 -#define mmCB_COLOR6_SLICE_BASE_IDX 1 -#define mmCB_COLOR6_VIEW 0x0375 -#define mmCB_COLOR6_VIEW_BASE_IDX 1 -#define mmCB_COLOR6_INFO 0x0376 -#define mmCB_COLOR6_INFO_BASE_IDX 1 -#define mmCB_COLOR6_ATTRIB 0x0377 -#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR6_DCC_CONTROL 0x0378 -#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR6_CMASK 0x0379 -#define mmCB_COLOR6_CMASK_BASE_IDX 1 -#define mmCB_COLOR6_CMASK_SLICE 0x037a -#define mmCB_COLOR6_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR6_FMASK 0x037b -#define mmCB_COLOR6_FMASK_BASE_IDX 1 -#define mmCB_COLOR6_FMASK_SLICE 0x037c -#define mmCB_COLOR6_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR6_CLEAR_WORD0 0x037d -#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR6_CLEAR_WORD1 0x037e -#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR6_DCC_BASE 0x037f -#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR7_BASE 0x0381 -#define mmCB_COLOR7_BASE_BASE_IDX 1 -#define mmCB_COLOR7_PITCH 0x0382 -#define mmCB_COLOR7_PITCH_BASE_IDX 1 -#define mmCB_COLOR7_SLICE 0x0383 -#define mmCB_COLOR7_SLICE_BASE_IDX 1 -#define mmCB_COLOR7_VIEW 0x0384 -#define mmCB_COLOR7_VIEW_BASE_IDX 1 -#define mmCB_COLOR7_INFO 0x0385 -#define mmCB_COLOR7_INFO_BASE_IDX 1 -#define mmCB_COLOR7_ATTRIB 0x0386 -#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 -#define mmCB_COLOR7_DCC_CONTROL 0x0387 -#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 -#define mmCB_COLOR7_CMASK 0x0388 -#define mmCB_COLOR7_CMASK_BASE_IDX 1 -#define mmCB_COLOR7_CMASK_SLICE 0x0389 -#define mmCB_COLOR7_CMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR7_FMASK 0x038a -#define mmCB_COLOR7_FMASK_BASE_IDX 1 -#define mmCB_COLOR7_FMASK_SLICE 0x038b -#define mmCB_COLOR7_FMASK_SLICE_BASE_IDX 1 -#define mmCB_COLOR7_CLEAR_WORD0 0x038c -#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 -#define mmCB_COLOR7_CLEAR_WORD1 0x038d -#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 -#define mmCB_COLOR7_DCC_BASE 0x038e -#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 -#define mmCB_COLOR0_BASE_EXT 0x0390 -#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR1_BASE_EXT 0x0391 -#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR2_BASE_EXT 0x0392 -#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR3_BASE_EXT 0x0393 -#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR4_BASE_EXT 0x0394 -#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR5_BASE_EXT 0x0395 -#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR6_BASE_EXT 0x0396 -#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR7_BASE_EXT 0x0397 -#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR0_CMASK_BASE_EXT 0x0398 -#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR1_CMASK_BASE_EXT 0x0399 -#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR2_CMASK_BASE_EXT 0x039a -#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR3_CMASK_BASE_EXT 0x039b -#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR4_CMASK_BASE_EXT 0x039c -#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR5_CMASK_BASE_EXT 0x039d -#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR6_CMASK_BASE_EXT 0x039e -#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR7_CMASK_BASE_EXT 0x039f -#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR0_FMASK_BASE_EXT 0x03a0 -#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR1_FMASK_BASE_EXT 0x03a1 -#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR2_FMASK_BASE_EXT 0x03a2 -#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR3_FMASK_BASE_EXT 0x03a3 -#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR4_FMASK_BASE_EXT 0x03a4 -#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR5_FMASK_BASE_EXT 0x03a5 -#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR6_FMASK_BASE_EXT 0x03a6 -#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR7_FMASK_BASE_EXT 0x03a7 -#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR0_DCC_BASE_EXT 0x03a8 -#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR1_DCC_BASE_EXT 0x03a9 -#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR2_DCC_BASE_EXT 0x03aa -#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR3_DCC_BASE_EXT 0x03ab -#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR4_DCC_BASE_EXT 0x03ac -#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR5_DCC_BASE_EXT 0x03ad -#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR6_DCC_BASE_EXT 0x03ae -#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR7_DCC_BASE_EXT 0x03af -#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 -#define mmCB_COLOR0_ATTRIB2 0x03b0 -#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR1_ATTRIB2 0x03b1 -#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR2_ATTRIB2 0x03b2 -#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR3_ATTRIB2 0x03b3 -#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR4_ATTRIB2 0x03b4 -#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR5_ATTRIB2 0x03b5 -#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR6_ATTRIB2 0x03b6 -#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR7_ATTRIB2 0x03b7 -#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 -#define mmCB_COLOR0_ATTRIB3 0x03b8 -#define mmCB_COLOR0_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR1_ATTRIB3 0x03b9 -#define mmCB_COLOR1_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR2_ATTRIB3 0x03ba -#define mmCB_COLOR2_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR3_ATTRIB3 0x03bb -#define mmCB_COLOR3_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR4_ATTRIB3 0x03bc -#define mmCB_COLOR4_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR5_ATTRIB3 0x03bd -#define mmCB_COLOR5_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR6_ATTRIB3 0x03be -#define mmCB_COLOR6_ATTRIB3_BASE_IDX 1 -#define mmCB_COLOR7_ATTRIB3 0x03bf -#define mmCB_COLOR7_ATTRIB3_BASE_IDX 1 - - -// addressBlock: gc_gfxudec -// base address: 0x30000 -#define mmCP_EOP_DONE_ADDR_LO 0x2000 -#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 -#define mmCP_EOP_DONE_ADDR_HI 0x2001 -#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 -#define mmCP_EOP_DONE_DATA_LO 0x2002 -#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 -#define mmCP_EOP_DONE_DATA_HI 0x2003 -#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 -#define mmCP_EOP_LAST_FENCE_LO 0x2004 -#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 -#define mmCP_EOP_LAST_FENCE_HI 0x2005 -#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 -#define mmCP_STREAM_OUT_ADDR_LO 0x2006 -#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 -#define mmCP_STREAM_OUT_ADDR_HI 0x2007 -#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 -#define mmCP_PIPE_STATS_ADDR_LO 0x2018 -#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 -#define mmCP_PIPE_STATS_ADDR_HI 0x2019 -#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 -#define mmCP_VGT_IAVERT_COUNT_LO 0x201a -#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_IAVERT_COUNT_HI 0x201b -#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c -#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d -#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e -#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f -#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 -#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 -#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 -#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 -#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 -#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 -#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 -#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 -#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_PA_CINVOC_COUNT_LO 0x2028 -#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_PA_CINVOC_COUNT_HI 0x2029 -#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_PA_CPRIM_COUNT_LO 0x202a -#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 -#define mmCP_PA_CPRIM_COUNT_HI 0x202b -#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 -#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c -#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 -#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d -#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 -#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e -#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 -#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f -#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 -#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 -#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 -#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 -#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 -#define mmCP_PIPE_STATS_CONTROL 0x203d -#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 -#define mmCP_STREAM_OUT_CONTROL 0x203e -#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 -#define mmCP_STRMOUT_CNTL 0x203f -#define mmCP_STRMOUT_CNTL_BASE_IDX 1 -#define mmSCRATCH_REG0 0x2040 -#define mmSCRATCH_REG0_BASE_IDX 1 -#define mmSCRATCH_REG1 0x2041 -#define mmSCRATCH_REG1_BASE_IDX 1 -#define mmSCRATCH_REG2 0x2042 -#define mmSCRATCH_REG2_BASE_IDX 1 -#define mmSCRATCH_REG3 0x2043 -#define mmSCRATCH_REG3_BASE_IDX 1 -#define mmSCRATCH_REG4 0x2044 -#define mmSCRATCH_REG4_BASE_IDX 1 -#define mmSCRATCH_REG5 0x2045 -#define mmSCRATCH_REG5_BASE_IDX 1 -#define mmSCRATCH_REG6 0x2046 -#define mmSCRATCH_REG6_BASE_IDX 1 -#define mmSCRATCH_REG7 0x2047 -#define mmSCRATCH_REG7_BASE_IDX 1 -#define mmSCRATCH_REG_ATOMIC 0x2048 -#define mmSCRATCH_REG_ATOMIC_BASE_IDX 1 -#define mmSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 -#define mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 -#define mmCP_APPEND_DDID_CNT 0x204b -#define mmCP_APPEND_DDID_CNT_BASE_IDX 1 -#define mmCP_APPEND_DATA_HI 0x204c -#define mmCP_APPEND_DATA_HI_BASE_IDX 1 -#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d -#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 -#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e -#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 -#define mmSCRATCH_UMSK 0x2050 -#define mmSCRATCH_UMSK_BASE_IDX 1 -#define mmSCRATCH_ADDR 0x2051 -#define mmSCRATCH_ADDR_BASE_IDX 1 -#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 -#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 -#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 -#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define mmCP_APPEND_ADDR_LO 0x2058 -#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 -#define mmCP_APPEND_ADDR_HI 0x2059 -#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 -#define mmCP_APPEND_DATA 0x205a -#define mmCP_APPEND_DATA_BASE_IDX 1 -#define mmCP_APPEND_DATA_LO 0x205a -#define mmCP_APPEND_DATA_LO_BASE_IDX 1 -#define mmCP_APPEND_LAST_CS_FENCE 0x205b -#define mmCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 -#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b -#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 -#define mmCP_APPEND_LAST_PS_FENCE 0x205c -#define mmCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 -#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c -#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 -#define mmCP_ATOMIC_PREOP_LO 0x205d -#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 -#define mmCP_ME_ATOMIC_PREOP_LO 0x205d -#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 -#define mmCP_ATOMIC_PREOP_HI 0x205e -#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 -#define mmCP_ME_ATOMIC_PREOP_HI 0x205e -#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 -#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f -#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 -#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 -#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 -#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define mmCP_ME_MC_WADDR_LO 0x2069 -#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 -#define mmCP_ME_MC_WADDR_HI 0x206a -#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 -#define mmCP_ME_MC_WDATA_LO 0x206b -#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 -#define mmCP_ME_MC_WDATA_HI 0x206c -#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 -#define mmCP_ME_MC_RADDR_LO 0x206d -#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 -#define mmCP_ME_MC_RADDR_HI 0x206e -#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 -#define mmCP_SEM_WAIT_TIMER 0x206f -#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 -#define mmCP_SIG_SEM_ADDR_LO 0x2070 -#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 -#define mmCP_SIG_SEM_ADDR_HI 0x2071 -#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 -#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 -#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 -#define mmCP_WAIT_SEM_ADDR_LO 0x2075 -#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 -#define mmCP_WAIT_SEM_ADDR_HI 0x2076 -#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_PFP_CONTROL 0x2077 -#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 -#define mmCP_DMA_ME_CONTROL 0x2078 -#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 -#define mmCP_COHER_BASE_HI 0x2079 -#define mmCP_COHER_BASE_HI_BASE_IDX 1 -#define mmCP_COHER_START_DELAY 0x207b -#define mmCP_COHER_START_DELAY_BASE_IDX 1 -#define mmCP_COHER_CNTL 0x207c -#define mmCP_COHER_CNTL_BASE_IDX 1 -#define mmCP_COHER_SIZE 0x207d -#define mmCP_COHER_SIZE_BASE_IDX 1 -#define mmCP_COHER_BASE 0x207e -#define mmCP_COHER_BASE_BASE_IDX 1 -#define mmCP_COHER_STATUS 0x207f -#define mmCP_COHER_STATUS_BASE_IDX 1 -#define mmCP_DMA_ME_SRC_ADDR 0x2080 -#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 -#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 -#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_ME_DST_ADDR 0x2082 -#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 -#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 -#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_ME_COMMAND 0x2084 -#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 -#define mmCP_DMA_PFP_SRC_ADDR 0x2085 -#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 -#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 -#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_PFP_DST_ADDR 0x2087 -#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 -#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 -#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_PFP_COMMAND 0x2089 -#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 -#define mmCP_DMA_CNTL 0x208a -#define mmCP_DMA_CNTL_BASE_IDX 1 -#define mmCP_DMA_READ_TAGS 0x208b -#define mmCP_DMA_READ_TAGS_BASE_IDX 1 -#define mmCP_COHER_SIZE_HI 0x208c -#define mmCP_COHER_SIZE_HI_BASE_IDX 1 -#define mmCP_PFP_IB_CONTROL 0x208d -#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 -#define mmCP_PFP_LOAD_CONTROL 0x208e -#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 -#define mmCP_SCRATCH_INDEX 0x208f -#define mmCP_SCRATCH_INDEX_BASE_IDX 1 -#define mmCP_SCRATCH_DATA 0x2090 -#define mmCP_SCRATCH_DATA_BASE_IDX 1 -#define mmCP_RB_OFFSET 0x2091 -#define mmCP_RB_OFFSET_BASE_IDX 1 -#define mmCP_IB2_OFFSET 0x2093 -#define mmCP_IB2_OFFSET_BASE_IDX 1 -#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 -#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 -#define mmCP_IB2_PREAMBLE_END 0x2097 -#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 -#define mmCP_CE_IB1_OFFSET 0x2098 -#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 -#define mmCP_CE_IB2_OFFSET 0x2099 -#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 -#define mmCP_CE_COUNTER 0x209a -#define mmCP_CE_COUNTER_BASE_IDX 1 -#define mmCP_DMA_ME_CMD_ADDR_LO 0x209c -#define mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 -#define mmCP_DMA_ME_CMD_ADDR_HI 0x209d -#define mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 -#define mmCP_DMA_PFP_CMD_ADDR_LO 0x209e -#define mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 -#define mmCP_DMA_PFP_CMD_ADDR_HI 0x209f -#define mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 -#define mmCP_APPEND_CMD_ADDR_LO 0x20a0 -#define mmCP_APPEND_CMD_ADDR_LO_BASE_IDX 1 -#define mmCP_APPEND_CMD_ADDR_HI 0x20a1 -#define mmCP_APPEND_CMD_ADDR_HI_BASE_IDX 1 -#define mmUCONFIG_RESERVED_REG0 0x20a2 -#define mmUCONFIG_RESERVED_REG0_BASE_IDX 1 -#define mmUCONFIG_RESERVED_REG1 0x20a3 -#define mmUCONFIG_RESERVED_REG1_BASE_IDX 1 -#define mmCP_CE_ATOMIC_PREOP_LO 0x20a8 -#define mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX 1 -#define mmCP_CE_ATOMIC_PREOP_HI 0x20a9 -#define mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX 1 -#define mmCP_CE_GDS_ATOMIC0_PREOP_LO 0x20aa -#define mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define mmCP_CE_GDS_ATOMIC0_PREOP_HI 0x20ab -#define mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define mmCP_CE_GDS_ATOMIC1_PREOP_LO 0x20ac -#define mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define mmCP_CE_GDS_ATOMIC1_PREOP_HI 0x20ad -#define mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd -#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_CE_IB1_CMD_BUFSZ 0x20be -#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf -#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_IB2_CMD_BUFSZ 0x20c1 -#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_ST_CMD_BUFSZ 0x20c2 -#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_CE_INIT_BASE_LO 0x20c3 -#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 -#define mmCP_CE_INIT_BASE_HI 0x20c4 -#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 -#define mmCP_CE_INIT_BUFSZ 0x20c5 -#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 -#define mmCP_CE_IB1_BASE_LO 0x20c6 -#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 -#define mmCP_CE_IB1_BASE_HI 0x20c7 -#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 -#define mmCP_CE_IB1_BUFSZ 0x20c8 -#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 -#define mmCP_CE_IB2_BASE_LO 0x20c9 -#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 -#define mmCP_CE_IB2_BASE_HI 0x20ca -#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 -#define mmCP_CE_IB2_BUFSZ 0x20cb -#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 -#define mmCP_IB1_BASE_LO 0x20cc -#define mmCP_IB1_BASE_LO_BASE_IDX 1 -#define mmCP_IB1_BASE_HI 0x20cd -#define mmCP_IB1_BASE_HI_BASE_IDX 1 -#define mmCP_IB1_BUFSZ 0x20ce -#define mmCP_IB1_BUFSZ_BASE_IDX 1 -#define mmCP_IB2_BASE_LO 0x20cf -#define mmCP_IB2_BASE_LO_BASE_IDX 1 -#define mmCP_IB2_BASE_HI 0x20d0 -#define mmCP_IB2_BASE_HI_BASE_IDX 1 -#define mmCP_IB2_BUFSZ 0x20d1 -#define mmCP_IB2_BUFSZ_BASE_IDX 1 -#define mmCP_ST_BASE_LO 0x20d2 -#define mmCP_ST_BASE_LO_BASE_IDX 1 -#define mmCP_ST_BASE_HI 0x20d3 -#define mmCP_ST_BASE_HI_BASE_IDX 1 -#define mmCP_ST_BUFSZ 0x20d4 -#define mmCP_ST_BUFSZ_BASE_IDX 1 -#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 -#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 -#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 -#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 -#define mmCP_EOP_DONE_CNTX_ID 0x20d7 -#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 -#define mmCP_DB_BASE_LO 0x20d8 -#define mmCP_DB_BASE_LO_BASE_IDX 1 -#define mmCP_DB_BASE_HI 0x20d9 -#define mmCP_DB_BASE_HI_BASE_IDX 1 -#define mmCP_DB_BUFSZ 0x20da -#define mmCP_DB_BUFSZ_BASE_IDX 1 -#define mmCP_DB_CMD_BUFSZ 0x20db -#define mmCP_DB_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_CE_DB_BASE_LO 0x20dc -#define mmCP_CE_DB_BASE_LO_BASE_IDX 1 -#define mmCP_CE_DB_BASE_HI 0x20dd -#define mmCP_CE_DB_BASE_HI_BASE_IDX 1 -#define mmCP_CE_DB_BUFSZ 0x20de -#define mmCP_CE_DB_BUFSZ_BASE_IDX 1 -#define mmCP_CE_DB_CMD_BUFSZ 0x20df -#define mmCP_CE_DB_CMD_BUFSZ_BASE_IDX 1 -#define mmCP_PFP_COMPLETION_STATUS 0x20ec -#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 -#define mmCP_CE_COMPLETION_STATUS 0x20ed -#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 -#define mmCP_PRED_NOT_VISIBLE 0x20ee -#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 -#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 -#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 -#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 -#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 -#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 -#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 -#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 -#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 -#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 -#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 -#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 -#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 -#define mmCP_DISPATCH_INDR_ADDR 0x20f6 -#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 -#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 -#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 -#define mmCP_INDEX_BASE_ADDR 0x20f8 -#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 -#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 -#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 -#define mmCP_INDEX_TYPE 0x20fa -#define mmCP_INDEX_TYPE_BASE_IDX 1 -#define mmCP_GDS_BKUP_ADDR 0x20fb -#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 -#define mmCP_GDS_BKUP_ADDR_HI 0x20fc -#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 -#define mmCP_SAMPLE_STATUS 0x20fd -#define mmCP_SAMPLE_STATUS_BASE_IDX 1 -#define mmCP_ME_COHER_CNTL 0x20fe -#define mmCP_ME_COHER_CNTL_BASE_IDX 1 -#define mmCP_ME_COHER_SIZE 0x20ff -#define mmCP_ME_COHER_SIZE_BASE_IDX 1 -#define mmCP_ME_COHER_SIZE_HI 0x2100 -#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 -#define mmCP_ME_COHER_BASE 0x2101 -#define mmCP_ME_COHER_BASE_BASE_IDX 1 -#define mmCP_ME_COHER_BASE_HI 0x2102 -#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 -#define mmCP_ME_COHER_STATUS 0x2103 -#define mmCP_ME_COHER_STATUS_BASE_IDX 1 -#define mmRLC_GPM_PERF_COUNT_0 0x2140 -#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 -#define mmRLC_GPM_PERF_COUNT_1 0x2141 -#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 -#define mmGRBM_GFX_INDEX 0x2200 -#define mmGRBM_GFX_INDEX_BASE_IDX 1 -#define mmVGT_ESGS_RING_SIZE_UMD 0x2240 -#define mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX 1 -#define mmVGT_GSVS_RING_SIZE_UMD 0x2241 -#define mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX 1 -#define mmVGT_PRIMITIVE_TYPE 0x2242 -#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 -#define mmVGT_INDEX_TYPE 0x2243 -#define mmVGT_INDEX_TYPE_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 -#define mmGE_MIN_VTX_INDX 0x2249 -#define mmGE_MIN_VTX_INDX_BASE_IDX 1 -#define mmGE_INDX_OFFSET 0x224a -#define mmGE_INDX_OFFSET_BASE_IDX 1 -#define mmGE_MULTI_PRIM_IB_RESET_EN 0x224b -#define mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 -#define mmVGT_NUM_INDICES 0x224c -#define mmVGT_NUM_INDICES_BASE_IDX 1 -#define mmVGT_NUM_INSTANCES 0x224d -#define mmVGT_NUM_INSTANCES_BASE_IDX 1 -#define mmVGT_TF_RING_SIZE_UMD 0x224e -#define mmVGT_TF_RING_SIZE_UMD_BASE_IDX 1 -#define mmVGT_HS_OFFCHIP_PARAM_UMD 0x224f -#define mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX 1 -#define mmVGT_TF_MEMORY_BASE_UMD 0x2250 -#define mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX 1 -#define mmGE_DMA_FIRST_INDEX 0x2251 -#define mmGE_DMA_FIRST_INDEX_BASE_IDX 1 -#define mmWD_POS_BUF_BASE 0x2252 -#define mmWD_POS_BUF_BASE_BASE_IDX 1 -#define mmWD_POS_BUF_BASE_HI 0x2253 -#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 -#define mmWD_CNTL_SB_BUF_BASE 0x2254 -#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 -#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 -#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 -#define mmWD_INDEX_BUF_BASE 0x2256 -#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 -#define mmWD_INDEX_BUF_BASE_HI 0x2257 -#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 -#define mmIA_MULTI_VGT_PARAM_PIPED 0x2258 -#define mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX 1 -#define mmGE_MAX_VTX_INDX 0x2259 -#define mmGE_MAX_VTX_INDX_BASE_IDX 1 -#define mmVGT_INSTANCE_BASE_ID 0x225a -#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 -#define mmGE_CNTL 0x225b -#define mmGE_CNTL_BASE_IDX 1 -#define mmGE_USER_VGPR1 0x225c -#define mmGE_USER_VGPR1_BASE_IDX 1 -#define mmGE_USER_VGPR2 0x225d -#define mmGE_USER_VGPR2_BASE_IDX 1 -#define mmGE_USER_VGPR3 0x225e -#define mmGE_USER_VGPR3_BASE_IDX 1 -#define mmGE_STEREO_CNTL 0x225f -#define mmGE_STEREO_CNTL_BASE_IDX 1 -#define mmGE_PC_ALLOC 0x2260 -#define mmGE_PC_ALLOC_BASE_IDX 1 -#define mmVGT_TF_MEMORY_BASE_HI_UMD 0x2261 -#define mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX 1 -#define mmGE_USER_VGPR_EN 0x2262 -#define mmGE_USER_VGPR_EN_BASE_IDX 1 -#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 -#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 -#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 -#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 -#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 -#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 -#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 -#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 -#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 -#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 -#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b -#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 -#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 -#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 -#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 -#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 -#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa -#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 -#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define mmPA_SC_TRAP_SCREEN_H 0x22b1 -#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 -#define mmPA_SC_TRAP_SCREEN_V 0x22b2 -#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 -#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 -#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 -#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 -#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 -#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_4 0x2344 -#define mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_5 0x2345 -#define mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_6 0x2346 -#define mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 -#define mmSQ_THREAD_TRACE_USERDATA_7 0x2347 -#define mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 -#define mmSQC_CACHES 0x2348 -#define mmSQC_CACHES_BASE_IDX 1 -#define mmTA_CS_BC_BASE_ADDR 0x2380 -#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 -#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 -#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 -#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 -#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 -#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 -#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 -#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 -#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 -#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 -#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 -#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 -#define mmDB_ZPASS_COUNT_LOW 0x23fe -#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 -#define mmDB_ZPASS_COUNT_HI 0x23ff -#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 -#define mmGDS_RD_ADDR 0x2400 -#define mmGDS_RD_ADDR_BASE_IDX 1 -#define mmGDS_RD_DATA 0x2401 -#define mmGDS_RD_DATA_BASE_IDX 1 -#define mmGDS_RD_BURST_ADDR 0x2402 -#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 -#define mmGDS_RD_BURST_COUNT 0x2403 -#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 -#define mmGDS_RD_BURST_DATA 0x2404 -#define mmGDS_RD_BURST_DATA_BASE_IDX 1 -#define mmGDS_WR_ADDR 0x2405 -#define mmGDS_WR_ADDR_BASE_IDX 1 -#define mmGDS_WR_DATA 0x2406 -#define mmGDS_WR_DATA_BASE_IDX 1 -#define mmGDS_WR_BURST_ADDR 0x2407 -#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 -#define mmGDS_WR_BURST_DATA 0x2408 -#define mmGDS_WR_BURST_DATA_BASE_IDX 1 -#define mmGDS_WRITE_COMPLETE 0x2409 -#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 -#define mmGDS_ATOM_CNTL 0x240a -#define mmGDS_ATOM_CNTL_BASE_IDX 1 -#define mmGDS_ATOM_COMPLETE 0x240b -#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 -#define mmGDS_ATOM_BASE 0x240c -#define mmGDS_ATOM_BASE_BASE_IDX 1 -#define mmGDS_ATOM_SIZE 0x240d -#define mmGDS_ATOM_SIZE_BASE_IDX 1 -#define mmGDS_ATOM_OFFSET0 0x240e -#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 -#define mmGDS_ATOM_OFFSET1 0x240f -#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 -#define mmGDS_ATOM_DST 0x2410 -#define mmGDS_ATOM_DST_BASE_IDX 1 -#define mmGDS_ATOM_OP 0x2411 -#define mmGDS_ATOM_OP_BASE_IDX 1 -#define mmGDS_ATOM_SRC0 0x2412 -#define mmGDS_ATOM_SRC0_BASE_IDX 1 -#define mmGDS_ATOM_SRC0_U 0x2413 -#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 -#define mmGDS_ATOM_SRC1 0x2414 -#define mmGDS_ATOM_SRC1_BASE_IDX 1 -#define mmGDS_ATOM_SRC1_U 0x2415 -#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 -#define mmGDS_ATOM_READ0 0x2416 -#define mmGDS_ATOM_READ0_BASE_IDX 1 -#define mmGDS_ATOM_READ0_U 0x2417 -#define mmGDS_ATOM_READ0_U_BASE_IDX 1 -#define mmGDS_ATOM_READ1 0x2418 -#define mmGDS_ATOM_READ1_BASE_IDX 1 -#define mmGDS_ATOM_READ1_U 0x2419 -#define mmGDS_ATOM_READ1_U_BASE_IDX 1 -#define mmGDS_GWS_RESOURCE_CNTL 0x241a -#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 -#define mmGDS_GWS_RESOURCE 0x241b -#define mmGDS_GWS_RESOURCE_BASE_IDX 1 -#define mmGDS_GWS_RESOURCE_CNT 0x241c -#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 -#define mmGDS_OA_CNTL 0x241d -#define mmGDS_OA_CNTL_BASE_IDX 1 -#define mmGDS_OA_COUNTER 0x241e -#define mmGDS_OA_COUNTER_BASE_IDX 1 -#define mmGDS_OA_ADDRESS 0x241f -#define mmGDS_OA_ADDRESS_BASE_IDX 1 -#define mmGDS_OA_INCDEC 0x2420 -#define mmGDS_OA_INCDEC_BASE_IDX 1 -#define mmGDS_OA_RING_SIZE 0x2421 -#define mmGDS_OA_RING_SIZE_BASE_IDX 1 -#define mmSPI_CONFIG_CNTL_REMAP 0x2440 -#define mmSPI_CONFIG_CNTL_REMAP_BASE_IDX 1 -#define mmSPI_CONFIG_CNTL_1_REMAP 0x2441 -#define mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX 1 -#define mmSPI_CONFIG_CNTL_2_REMAP 0x2442 -#define mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX 1 -#define mmSPI_WAVE_LIMIT_CNTL_REMAP 0x2443 -#define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX 1 - - -// addressBlock: gc_cprs64dec -// base address: 0x32000 -#define mmCP_MES_PRGRM_CNTR_START 0x2800 -#define mmCP_MES_PRGRM_CNTR_START_BASE_IDX 1 -#define mmCP_MES_INTR_ROUTINE_START 0x2801 -#define mmCP_MES_INTR_ROUTINE_START_BASE_IDX 1 -#define mmCP_MES_MTVEC_LO 0x2801 -#define mmCP_MES_MTVEC_LO_BASE_IDX 1 -#define mmCP_MES_MTVEC_HI 0x2802 -#define mmCP_MES_MTVEC_HI_BASE_IDX 1 -#define mmCP_MES_CNTL 0x2807 -#define mmCP_MES_CNTL_BASE_IDX 1 -#define mmCP_MES_PIPE_PRIORITY_CNTS 0x2808 -#define mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 -#define mmCP_MES_PIPE0_PRIORITY 0x2809 -#define mmCP_MES_PIPE0_PRIORITY_BASE_IDX 1 -#define mmCP_MES_PIPE1_PRIORITY 0x280a -#define mmCP_MES_PIPE1_PRIORITY_BASE_IDX 1 -#define mmCP_MES_PIPE2_PRIORITY 0x280b -#define mmCP_MES_PIPE2_PRIORITY_BASE_IDX 1 -#define mmCP_MES_PIPE3_PRIORITY 0x280c -#define mmCP_MES_PIPE3_PRIORITY_BASE_IDX 1 -#define mmCP_MES_HEADER_DUMP 0x280d -#define mmCP_MES_HEADER_DUMP_BASE_IDX 1 -#define mmCP_MES_MIE_LO 0x280e -#define mmCP_MES_MIE_LO_BASE_IDX 1 -#define mmCP_MES_MIE_HI 0x280f -#define mmCP_MES_MIE_HI_BASE_IDX 1 -#define mmCP_MES_INTERRUPT 0x2810 -#define mmCP_MES_INTERRUPT_BASE_IDX 1 -#define mmCP_MES_SCRATCH_INDEX 0x2811 -#define mmCP_MES_SCRATCH_INDEX_BASE_IDX 1 -#define mmCP_MES_SCRATCH_DATA 0x2812 -#define mmCP_MES_SCRATCH_DATA_BASE_IDX 1 -#define mmCP_MES_INSTR_PNTR 0x2813 -#define mmCP_MES_INSTR_PNTR_BASE_IDX 1 -#define mmCP_MES_MSCRATCH_HI 0x2814 -#define mmCP_MES_MSCRATCH_HI_BASE_IDX 1 -#define mmCP_MES_MSCRATCH_LO 0x2815 -#define mmCP_MES_MSCRATCH_LO_BASE_IDX 1 -#define mmCP_MES_MSTATUS_LO 0x2816 -#define mmCP_MES_MSTATUS_LO_BASE_IDX 1 -#define mmCP_MES_MSTATUS_HI 0x2817 -#define mmCP_MES_MSTATUS_HI_BASE_IDX 1 -#define mmCP_MES_MEPC_LO 0x2818 -#define mmCP_MES_MEPC_LO_BASE_IDX 1 -#define mmCP_MES_MEPC_HI 0x2819 -#define mmCP_MES_MEPC_HI_BASE_IDX 1 -#define mmCP_MES_MCAUSE_LO 0x281a -#define mmCP_MES_MCAUSE_LO_BASE_IDX 1 -#define mmCP_MES_MCAUSE_HI 0x281b -#define mmCP_MES_MCAUSE_HI_BASE_IDX 1 -#define mmCP_MES_MBADADDR_LO 0x281c -#define mmCP_MES_MBADADDR_LO_BASE_IDX 1 -#define mmCP_MES_MBADADDR_HI 0x281d -#define mmCP_MES_MBADADDR_HI_BASE_IDX 1 -#define mmCP_MES_MIP_LO 0x281e -#define mmCP_MES_MIP_LO_BASE_IDX 1 -#define mmCP_MES_MIP_HI 0x281f -#define mmCP_MES_MIP_HI_BASE_IDX 1 -#define mmCP_MES_IC_OP_CNTL 0x2820 -#define mmCP_MES_IC_OP_CNTL_BASE_IDX 1 -#define mmCP_MES_MCYCLE_LO 0x2826 -#define mmCP_MES_MCYCLE_LO_BASE_IDX 1 -#define mmCP_MES_MCYCLE_HI 0x2827 -#define mmCP_MES_MCYCLE_HI_BASE_IDX 1 -#define mmCP_MES_MTIME_LO 0x2828 -#define mmCP_MES_MTIME_LO_BASE_IDX 1 -#define mmCP_MES_MTIME_HI 0x2829 -#define mmCP_MES_MTIME_HI_BASE_IDX 1 -#define mmCP_MES_MINSTRET_LO 0x282a -#define mmCP_MES_MINSTRET_LO_BASE_IDX 1 -#define mmCP_MES_MINSTRET_HI 0x282b -#define mmCP_MES_MINSTRET_HI_BASE_IDX 1 -#define mmCP_MES_MISA_LO 0x282c -#define mmCP_MES_MISA_LO_BASE_IDX 1 -#define mmCP_MES_MISA_HI 0x282d -#define mmCP_MES_MISA_HI_BASE_IDX 1 -#define mmCP_MES_MVENDORID_LO 0x282e -#define mmCP_MES_MVENDORID_LO_BASE_IDX 1 -#define mmCP_MES_MVENDORID_HI 0x282f -#define mmCP_MES_MVENDORID_HI_BASE_IDX 1 -#define mmCP_MES_MARCHID_LO 0x2830 -#define mmCP_MES_MARCHID_LO_BASE_IDX 1 -#define mmCP_MES_MARCHID_HI 0x2831 -#define mmCP_MES_MARCHID_HI_BASE_IDX 1 -#define mmCP_MES_MIMPID_LO 0x2832 -#define mmCP_MES_MIMPID_LO_BASE_IDX 1 -#define mmCP_MES_MIMPID_HI 0x2833 -#define mmCP_MES_MIMPID_HI_BASE_IDX 1 -#define mmCP_MES_MHARTID_LO 0x2834 -#define mmCP_MES_MHARTID_LO_BASE_IDX 1 -#define mmCP_MES_MHARTID_HI 0x2835 -#define mmCP_MES_MHARTID_HI_BASE_IDX 1 -#define mmCP_MES_DC_BASE_CNTL 0x2836 -#define mmCP_MES_DC_BASE_CNTL_BASE_IDX 1 -#define mmCP_MES_DC_OP_CNTL 0x2837 -#define mmCP_MES_DC_OP_CNTL_BASE_IDX 1 -#define mmCP_MES_MTIMECMP_LO 0x2838 -#define mmCP_MES_MTIMECMP_LO_BASE_IDX 1 -#define mmCP_MES_MTIMECMP_HI 0x2839 -#define mmCP_MES_MTIMECMP_HI_BASE_IDX 1 -#define mmCP_MES_PROCESS_QUANTUM_PIPE0 0x283a -#define mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 -#define mmCP_MES_PROCESS_QUANTUM_PIPE1 0x283b -#define mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL1 0x283c -#define mmCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL2 0x283d -#define mmCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL3 0x283e -#define mmCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL4 0x283f -#define mmCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL5 0x2840 -#define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 -#define mmCP_MES_DOORBELL_CONTROL6 0x2841 -#define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 -#define mmCP_MES_GP0_LO 0x2843 -#define mmCP_MES_GP0_LO_BASE_IDX 1 -#define mmCP_MES_GP0_HI 0x2844 -#define mmCP_MES_GP0_HI_BASE_IDX 1 -#define mmCP_MES_GP1_LO 0x2845 -#define mmCP_MES_GP1_LO_BASE_IDX 1 -#define mmCP_MES_GP1_HI 0x2846 -#define mmCP_MES_GP1_HI_BASE_IDX 1 -#define mmCP_MES_GP2_LO 0x2847 -#define mmCP_MES_GP2_LO_BASE_IDX 1 -#define mmCP_MES_GP2_HI 0x2848 -#define mmCP_MES_GP2_HI_BASE_IDX 1 -#define mmCP_MES_GP3_LO 0x2849 -#define mmCP_MES_GP3_LO_BASE_IDX 1 -#define mmCP_MES_GP3_HI 0x284a -#define mmCP_MES_GP3_HI_BASE_IDX 1 -#define mmCP_MES_GP4_LO 0x284b -#define mmCP_MES_GP4_LO_BASE_IDX 1 -#define mmCP_MES_GP4_HI 0x284c -#define mmCP_MES_GP4_HI_BASE_IDX 1 -#define mmCP_MES_GP5_LO 0x284d -#define mmCP_MES_GP5_LO_BASE_IDX 1 -#define mmCP_MES_GP5_HI 0x284e -#define mmCP_MES_GP5_HI_BASE_IDX 1 -#define mmCP_MES_GP6_LO 0x284f -#define mmCP_MES_GP6_LO_BASE_IDX 1 -#define mmCP_MES_GP6_HI 0x2850 -#define mmCP_MES_GP6_HI_BASE_IDX 1 -#define mmCP_MES_GP7_LO 0x2851 -#define mmCP_MES_GP7_LO_BASE_IDX 1 -#define mmCP_MES_GP7_HI 0x2852 -#define mmCP_MES_GP7_HI_BASE_IDX 1 -#define mmCP_MES_GP8_LO 0x2853 -#define mmCP_MES_GP8_LO_BASE_IDX 1 -#define mmCP_MES_GP8_HI 0x2854 -#define mmCP_MES_GP8_HI_BASE_IDX 1 -#define mmCP_MES_GP9_LO 0x2855 -#define mmCP_MES_GP9_LO_BASE_IDX 1 -#define mmCP_MES_GP9_HI 0x2856 -#define mmCP_MES_GP9_HI_BASE_IDX 1 -#define mmCP_MES_DM_INDEX_ADDR 0x2880 -#define mmCP_MES_DM_INDEX_ADDR_BASE_IDX 1 -#define mmCP_MES_DM_INDEX_DATA 0x2881 -#define mmCP_MES_DM_INDEX_DATA_BASE_IDX 1 -#define mmCP_MES_PERFCOUNT_CNTL 0x2899 -#define mmCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 -#define mmCP_MES_PENDING_INTERRUPT 0x289a -#define mmCP_MES_PENDING_INTERRUPT_BASE_IDX 1 - - -// addressBlock: gc_gusdec -// base address: 0x33000 -#define mmGUS_IO_RD_COMBINE_FLUSH 0x2c00 -#define mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1 -#define mmGUS_IO_WR_COMBINE_FLUSH 0x2c01 -#define mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_AGE_RATE 0x2c02 -#define mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_AGE_RATE 0x2c03 -#define mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_AGE_COEFF 0x2c04 -#define mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_AGE_COEFF 0x2c05 -#define mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUEUING 0x2c06 -#define mmGUS_IO_RD_PRI_QUEUING_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUEUING 0x2c07 -#define mmGUS_IO_WR_PRI_QUEUING_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_FIXED 0x2c08 -#define mmGUS_IO_RD_PRI_FIXED_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_FIXED 0x2c09 -#define mmGUS_IO_WR_PRI_FIXED_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a -#define mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b -#define mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c -#define mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d -#define mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e -#define mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f -#define mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT_PRI3 0x2c10 -#define mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT_PRI4 0x2c11 -#define mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT_PRI1 0x2c12 -#define mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT_PRI2 0x2c13 -#define mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT_PRI3 0x2c14 -#define mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT_PRI4 0x2c15 -#define mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16 -#define mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17 -#define mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18 -#define mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1 -#define mmGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19 -#define mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a -#define mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b -#define mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c -#define mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1 -#define mmGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d -#define mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1 -#define mmGUS_DRAM_COMBINE_FLUSH 0x2c1e -#define mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1 -#define mmGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f -#define mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1 -#define mmGUS_DRAM_PRI_AGE_RATE 0x2c20 -#define mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1 -#define mmGUS_DRAM_PRI_AGE_COEFF 0x2c21 -#define mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUEUING 0x2c22 -#define mmGUS_DRAM_PRI_QUEUING_BASE_IDX 1 -#define mmGUS_DRAM_PRI_FIXED 0x2c23 -#define mmGUS_DRAM_PRI_FIXED_BASE_IDX 1 -#define mmGUS_DRAM_PRI_URGENCY_COEFF 0x2c24 -#define mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1 -#define mmGUS_DRAM_PRI_URGENCY_MODE 0x2c25 -#define mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT_PRI1 0x2c26 -#define mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT_PRI2 0x2c27 -#define mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT_PRI3 0x2c28 -#define mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT_PRI4 0x2c29 -#define mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT_PRI5 0x2c2a -#define mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b -#define mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c -#define mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d -#define mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e -#define mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1 -#define mmGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f -#define mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1 -#define mmGUS_IO_GROUP_BURST 0x2c30 -#define mmGUS_IO_GROUP_BURST_BASE_IDX 1 -#define mmGUS_DRAM_GROUP_BURST 0x2c31 -#define mmGUS_DRAM_GROUP_BURST_BASE_IDX 1 -#define mmGUS_SDP_ARB_FINAL 0x2c32 -#define mmGUS_SDP_ARB_FINAL_BASE_IDX 1 -#define mmGUS_SDP_QOS_VC_PRIORITY 0x2c33 -#define mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1 -#define mmGUS_SDP_CREDITS 0x2c34 -#define mmGUS_SDP_CREDITS_BASE_IDX 1 -#define mmGUS_SDP_TAG_RESERVE0 0x2c35 -#define mmGUS_SDP_TAG_RESERVE0_BASE_IDX 1 -#define mmGUS_SDP_TAG_RESERVE1 0x2c36 -#define mmGUS_SDP_TAG_RESERVE1_BASE_IDX 1 -#define mmGUS_SDP_VCC_RESERVE0 0x2c37 -#define mmGUS_SDP_VCC_RESERVE0_BASE_IDX 1 -#define mmGUS_SDP_VCC_RESERVE1 0x2c38 -#define mmGUS_SDP_VCC_RESERVE1_BASE_IDX 1 -#define mmGUS_SDP_VCD_RESERVE0 0x2c39 -#define mmGUS_SDP_VCD_RESERVE0_BASE_IDX 1 -#define mmGUS_SDP_VCD_RESERVE1 0x2c3a -#define mmGUS_SDP_VCD_RESERVE1_BASE_IDX 1 -#define mmGUS_SDP_REQ_CNTL 0x2c3b -#define mmGUS_SDP_REQ_CNTL_BASE_IDX 1 -#define mmGUS_MISC 0x2c3c -#define mmGUS_MISC_BASE_IDX 1 -#define mmGUS_LATENCY_SAMPLING 0x2c3d -#define mmGUS_LATENCY_SAMPLING_BASE_IDX 1 -#define mmGUS_ERR_STATUS 0x2c3e -#define mmGUS_ERR_STATUS_BASE_IDX 1 -#define mmGUS_MISC2 0x2c3f -#define mmGUS_MISC2_BASE_IDX 1 -#define mmGUS_SDP_ENABLE 0x2c45 -#define mmGUS_SDP_ENABLE_BASE_IDX 1 -#define mmGUS_L1_CH0_CMD_IN 0x2c46 -#define mmGUS_L1_CH0_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_CH0_CMD_OUT 0x2c47 -#define mmGUS_L1_CH0_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_CH0_DATA_IN 0x2c48 -#define mmGUS_L1_CH0_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_CH0_DATA_OUT 0x2c49 -#define mmGUS_L1_CH0_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_CH0_DATA_U_IN 0x2c4a -#define mmGUS_L1_CH0_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_CH0_DATA_U_OUT 0x2c4b -#define mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_L1_CH1_CMD_IN 0x2c4c -#define mmGUS_L1_CH1_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_CH1_CMD_OUT 0x2c4d -#define mmGUS_L1_CH1_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_CH1_DATA_IN 0x2c4e -#define mmGUS_L1_CH1_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_CH1_DATA_OUT 0x2c4f -#define mmGUS_L1_CH1_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_CH1_DATA_U_IN 0x2c50 -#define mmGUS_L1_CH1_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_CH1_DATA_U_OUT 0x2c51 -#define mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_L1_SA0_CMD_IN 0x2c52 -#define mmGUS_L1_SA0_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_SA0_CMD_OUT 0x2c53 -#define mmGUS_L1_SA0_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_SA0_DATA_IN 0x2c54 -#define mmGUS_L1_SA0_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_SA0_DATA_OUT 0x2c55 -#define mmGUS_L1_SA0_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_SA0_DATA_U_IN 0x2c56 -#define mmGUS_L1_SA0_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_SA0_DATA_U_OUT 0x2c57 -#define mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_L1_SA1_CMD_IN 0x2c58 -#define mmGUS_L1_SA1_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_SA1_CMD_OUT 0x2c59 -#define mmGUS_L1_SA1_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_SA1_DATA_IN 0x2c5a -#define mmGUS_L1_SA1_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_SA1_DATA_OUT 0x2c5b -#define mmGUS_L1_SA1_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_SA1_DATA_U_IN 0x2c5c -#define mmGUS_L1_SA1_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_SA1_DATA_U_OUT 0x2c5d -#define mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_L1_SA2_CMD_IN 0x2c5e -#define mmGUS_L1_SA2_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_SA2_CMD_OUT 0x2c5f -#define mmGUS_L1_SA2_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_SA2_DATA_IN 0x2c60 -#define mmGUS_L1_SA2_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_SA2_DATA_OUT 0x2c61 -#define mmGUS_L1_SA2_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_SA2_DATA_U_IN 0x2c62 -#define mmGUS_L1_SA2_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_SA2_DATA_U_OUT 0x2c63 -#define mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_L1_SA3_CMD_IN 0x2c64 -#define mmGUS_L1_SA3_CMD_IN_BASE_IDX 1 -#define mmGUS_L1_SA3_CMD_OUT 0x2c65 -#define mmGUS_L1_SA3_CMD_OUT_BASE_IDX 1 -#define mmGUS_L1_SA3_DATA_IN 0x2c66 -#define mmGUS_L1_SA3_DATA_IN_BASE_IDX 1 -#define mmGUS_L1_SA3_DATA_OUT 0x2c67 -#define mmGUS_L1_SA3_DATA_OUT_BASE_IDX 1 -#define mmGUS_L1_SA3_DATA_U_IN 0x2c68 -#define mmGUS_L1_SA3_DATA_U_IN_BASE_IDX 1 -#define mmGUS_L1_SA3_DATA_U_OUT 0x2c69 -#define mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1 -#define mmGUS_MISC3 0x2c6a -#define mmGUS_MISC3_BASE_IDX 1 -#define mmGUS_WRRSP_FIFO_CNTL 0x2c6b -#define mmGUS_WRRSP_FIFO_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gl1dec -// base address: 0x33400 -#define mmGL1_DRAM_BURST_MASK 0x2d02 -#define mmGL1_DRAM_BURST_MASK_BASE_IDX 1 -#define mmGL1_ARB_STATUS 0x2d03 -#define mmGL1_ARB_STATUS_BASE_IDX 1 -#define mmGL1_PIPE_STEER 0x2d10 -#define mmGL1_PIPE_STEER_BASE_IDX 1 -#define mmGL1C_STATUS 0x2d41 -#define mmGL1C_STATUS_BASE_IDX 1 -#define mmGL1C_UTCL0_CNTL2 0x2d43 -#define mmGL1C_UTCL0_CNTL2_BASE_IDX 1 -#define mmGL1C_UTCL0_STATUS 0x2d44 -#define mmGL1C_UTCL0_STATUS_BASE_IDX 1 -#define mmGL1C_UTCL0_RETRY 0x2d45 -#define mmGL1C_UTCL0_RETRY_BASE_IDX 1 - - -// addressBlock: gc_chdec -// base address: 0x33600 -#define mmCH_ARB_CTRL 0x2d80 -#define mmCH_ARB_CTRL_BASE_IDX 1 -#define mmCH_DRAM_BURST_MASK 0x2d82 -#define mmCH_DRAM_BURST_MASK_BASE_IDX 1 -#define mmCH_ARB_STATUS 0x2d83 -#define mmCH_ARB_STATUS_BASE_IDX 1 -#define mmCH_DRAM_BURST_CTRL 0x2d84 -#define mmCH_DRAM_BURST_CTRL_BASE_IDX 1 -#define mmCHA_CHC_CREDITS 0x2d88 -#define mmCHA_CHC_CREDITS_BASE_IDX 1 -#define mmCHA_CLIENT_FREE_DELAY 0x2d89 -#define mmCHA_CLIENT_FREE_DELAY_BASE_IDX 1 -#define mmCH_PIPE_STEER 0x2d90 -#define mmCH_PIPE_STEER_BASE_IDX 1 -#define mmCH_VC5_ENABLE 0x2d94 -#define mmCH_VC5_ENABLE_BASE_IDX 1 -#define mmCHC_CTRL 0x2dc0 -#define mmCHC_CTRL_BASE_IDX 1 -#define mmCHC_STATUS 0x2dc1 -#define mmCHC_STATUS_BASE_IDX 1 -#define mmCHCG_CTRL 0x2dc2 -#define mmCHCG_CTRL_BASE_IDX 1 -#define mmCHCG_STATUS 0x2dc3 -#define mmCHCG_STATUS_BASE_IDX 1 - - -// addressBlock: gc_gl2dec -// base address: 0x33800 -#define mmGL2C_CTRL 0x2e00 -#define mmGL2C_CTRL_BASE_IDX 1 -#define mmGL2C_CTRL2 0x2e01 -#define mmGL2C_CTRL2_BASE_IDX 1 -#define mmGL2C_ADDR_MATCH_MASK 0x2e03 -#define mmGL2C_ADDR_MATCH_MASK_BASE_IDX 1 -#define mmGL2C_ADDR_MATCH_SIZE 0x2e04 -#define mmGL2C_ADDR_MATCH_SIZE_BASE_IDX 1 -#define mmGL2C_WBINVL2 0x2e05 -#define mmGL2C_WBINVL2_BASE_IDX 1 -#define mmGL2C_SOFT_RESET 0x2e06 -#define mmGL2C_SOFT_RESET_BASE_IDX 1 -#define mmGL2C_CM_CTRL0 0x2e07 -#define mmGL2C_CM_CTRL0_BASE_IDX 1 -#define mmGL2C_CM_CTRL1 0x2e08 -#define mmGL2C_CM_CTRL1_BASE_IDX 1 -#define mmGL2C_CM_STALL 0x2e09 -#define mmGL2C_CM_STALL_BASE_IDX 1 -#define mmGL2C_MDC_PF_FLAG_CTRL 0x2e0a -#define mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX 1 -#define mmGL2C_LB_CTR_CTRL 0x2e0d -#define mmGL2C_LB_CTR_CTRL_BASE_IDX 1 -#define mmGL2C_LB_DATA0 0x2e0e -#define mmGL2C_LB_DATA0_BASE_IDX 1 -#define mmGL2C_LB_DATA1 0x2e0f -#define mmGL2C_LB_DATA1_BASE_IDX 1 -#define mmGL2C_LB_DATA2 0x2e10 -#define mmGL2C_LB_DATA2_BASE_IDX 1 -#define mmGL2C_LB_DATA3 0x2e11 -#define mmGL2C_LB_DATA3_BASE_IDX 1 -#define mmGL2C_LB_CTR_SEL0 0x2e12 -#define mmGL2C_LB_CTR_SEL0_BASE_IDX 1 -#define mmGL2C_LB_CTR_SEL1 0x2e13 -#define mmGL2C_LB_CTR_SEL1_BASE_IDX 1 -#define mmGL2A_ADDR_MATCH_CTRL 0x2e20 -#define mmGL2A_ADDR_MATCH_CTRL_BASE_IDX 1 -#define mmGL2A_ADDR_MATCH_MASK 0x2e21 -#define mmGL2A_ADDR_MATCH_MASK_BASE_IDX 1 -#define mmGL2A_ADDR_MATCH_SIZE 0x2e22 -#define mmGL2A_ADDR_MATCH_SIZE_BASE_IDX 1 -#define mmGL2A_PRIORITY_CTRL 0x2e23 -#define mmGL2A_PRIORITY_CTRL_BASE_IDX 1 -#define mmGL2_PIPE_STEER_0 0x2e25 -#define mmGL2_PIPE_STEER_0_BASE_IDX 1 -#define mmGL2_PIPE_STEER_1 0x2e26 -#define mmGL2_PIPE_STEER_1_BASE_IDX 1 - - -// addressBlock: gc_perfddec -// base address: 0x34000 -#define mmCPG_PERFCOUNTER1_LO 0x3000 -#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCPG_PERFCOUNTER1_HI 0x3001 -#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCPG_PERFCOUNTER0_LO 0x3002 -#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCPG_PERFCOUNTER0_HI 0x3003 -#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCPC_PERFCOUNTER1_LO 0x3004 -#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCPC_PERFCOUNTER1_HI 0x3005 -#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCPC_PERFCOUNTER0_LO 0x3006 -#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCPC_PERFCOUNTER0_HI 0x3007 -#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCPF_PERFCOUNTER1_LO 0x3008 -#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCPF_PERFCOUNTER1_HI 0x3009 -#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCPF_PERFCOUNTER0_LO 0x300a -#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCPF_PERFCOUNTER0_HI 0x300b -#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCPF_LATENCY_STATS_DATA 0x300c -#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 -#define mmCPG_LATENCY_STATS_DATA 0x300d -#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 -#define mmCPC_LATENCY_STATS_DATA 0x300e -#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER0_LO 0x3040 -#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER0_HI 0x3041 -#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER1_LO 0x3043 -#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER1_HI 0x3044 -#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 -#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 -#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 -#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 -#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 -#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a -#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b -#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c -#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGE1_PERFCOUNTER0_LO 0x30a4 -#define mmGE1_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGE1_PERFCOUNTER0_HI 0x30a5 -#define mmGE1_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGE1_PERFCOUNTER1_LO 0x30a6 -#define mmGE1_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGE1_PERFCOUNTER1_HI 0x30a7 -#define mmGE1_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGE1_PERFCOUNTER2_LO 0x30a8 -#define mmGE1_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGE1_PERFCOUNTER2_HI 0x30a9 -#define mmGE1_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGE1_PERFCOUNTER3_LO 0x30aa -#define mmGE1_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGE1_PERFCOUNTER3_HI 0x30ab -#define mmGE1_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER0_LO 0x30ac -#define mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER0_HI 0x30ad -#define mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER1_LO 0x30ae -#define mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER1_HI 0x30af -#define mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER2_LO 0x30b0 -#define mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER2_HI 0x30b1 -#define mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER3_LO 0x30b2 -#define mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER3_HI 0x30b3 -#define mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER0_LO 0x30b4 -#define mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER0_HI 0x30b5 -#define mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER1_LO 0x30b6 -#define mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER1_HI 0x30b7 -#define mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER2_LO 0x30b8 -#define mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER2_HI 0x30b9 -#define mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER3_LO 0x30ba -#define mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER3_HI 0x30bb -#define mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER0_LO 0x3100 -#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER0_HI 0x3101 -#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER1_LO 0x3102 -#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER1_HI 0x3103 -#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER2_LO 0x3104 -#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER2_HI 0x3105 -#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER3_LO 0x3106 -#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER3_HI 0x3107 -#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER0_LO 0x3140 -#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER0_HI 0x3141 -#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER1_LO 0x3142 -#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER1_HI 0x3143 -#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER2_LO 0x3144 -#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER2_HI 0x3145 -#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER3_LO 0x3146 -#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER3_HI 0x3147 -#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER4_LO 0x3148 -#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER4_HI 0x3149 -#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER5_LO 0x314a -#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER5_HI 0x314b -#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER6_LO 0x314c -#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER6_HI 0x314d -#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER7_LO 0x314e -#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER7_HI 0x314f -#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER0_HI 0x3180 -#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER0_LO 0x3181 -#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSPI_PERFCOUNTER1_HI 0x3182 -#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER1_LO 0x3183 -#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSPI_PERFCOUNTER2_HI 0x3184 -#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER2_LO 0x3185 -#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmSPI_PERFCOUNTER3_HI 0x3186 -#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER3_LO 0x3187 -#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmSPI_PERFCOUNTER4_HI 0x3188 -#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER4_LO 0x3189 -#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 -#define mmSPI_PERFCOUNTER5_HI 0x318a -#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 -#define mmSPI_PERFCOUNTER5_LO 0x318b -#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER0_LO 0x31c0 -#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER0_HI 0x31c1 -#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER1_LO 0x31c2 -#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER1_HI 0x31c3 -#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER2_LO 0x31c4 -#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER2_HI 0x31c5 -#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER3_LO 0x31c6 -#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER3_HI 0x31c7 -#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER4_LO 0x31c8 -#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER4_HI 0x31c9 -#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER5_LO 0x31ca -#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER5_HI 0x31cb -#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER6_LO 0x31cc -#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER6_HI 0x31cd -#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER7_LO 0x31ce -#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER7_HI 0x31cf -#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER8_LO 0x31d0 -#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER8_HI 0x31d1 -#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER9_LO 0x31d2 -#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER9_HI 0x31d3 -#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER10_LO 0x31d4 -#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER10_HI 0x31d5 -#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER11_LO 0x31d6 -#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER11_HI 0x31d7 -#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER12_LO 0x31d8 -#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER12_HI 0x31d9 -#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER13_LO 0x31da -#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER13_HI 0x31db -#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER14_LO 0x31dc -#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER14_HI 0x31dd -#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 -#define mmSQ_PERFCOUNTER15_LO 0x31de -#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 -#define mmSQ_PERFCOUNTER15_HI 0x31df -#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 -#define mmSX_PERFCOUNTER0_LO 0x3240 -#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSX_PERFCOUNTER0_HI 0x3241 -#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSX_PERFCOUNTER1_LO 0x3242 -#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSX_PERFCOUNTER1_HI 0x3243 -#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmSX_PERFCOUNTER2_LO 0x3244 -#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmSX_PERFCOUNTER2_HI 0x3245 -#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmSX_PERFCOUNTER3_LO 0x3246 -#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmSX_PERFCOUNTER3_HI 0x3247 -#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER2_LO 0x3260 -#define mmGCEA_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER2_HI 0x3261 -#define mmGCEA_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER_LO 0x3262 -#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER_HI 0x3263 -#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGDS_PERFCOUNTER0_LO 0x3280 -#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGDS_PERFCOUNTER0_HI 0x3281 -#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGDS_PERFCOUNTER1_LO 0x3282 -#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGDS_PERFCOUNTER1_HI 0x3283 -#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGDS_PERFCOUNTER2_LO 0x3284 -#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGDS_PERFCOUNTER2_HI 0x3285 -#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGDS_PERFCOUNTER3_LO 0x3286 -#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGDS_PERFCOUNTER3_HI 0x3287 -#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmTA_PERFCOUNTER0_LO 0x32c0 -#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmTA_PERFCOUNTER0_HI 0x32c1 -#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmTA_PERFCOUNTER1_LO 0x32c2 -#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmTA_PERFCOUNTER1_HI 0x32c3 -#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmTD_PERFCOUNTER0_LO 0x3300 -#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmTD_PERFCOUNTER0_HI 0x3301 -#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmTD_PERFCOUNTER1_LO 0x3302 -#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmTD_PERFCOUNTER1_HI 0x3303 -#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmTCP_PERFCOUNTER0_LO 0x3340 -#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmTCP_PERFCOUNTER0_HI 0x3341 -#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmTCP_PERFCOUNTER1_LO 0x3342 -#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmTCP_PERFCOUNTER1_HI 0x3343 -#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmTCP_PERFCOUNTER2_LO 0x3344 -#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmTCP_PERFCOUNTER2_HI 0x3345 -#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmTCP_PERFCOUNTER3_LO 0x3346 -#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmTCP_PERFCOUNTER3_HI 0x3347 -#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER0_LO 0x3380 -#define mmGL2C_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER0_HI 0x3381 -#define mmGL2C_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER1_LO 0x3382 -#define mmGL2C_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER1_HI 0x3383 -#define mmGL2C_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER2_LO 0x3384 -#define mmGL2C_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER2_HI 0x3385 -#define mmGL2C_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER3_LO 0x3386 -#define mmGL2C_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER3_HI 0x3387 -#define mmGL2C_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER0_LO 0x3390 -#define mmGL2A_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER0_HI 0x3391 -#define mmGL2A_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER1_LO 0x3392 -#define mmGL2A_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER1_HI 0x3393 -#define mmGL2A_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER2_LO 0x3394 -#define mmGL2A_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER2_HI 0x3395 -#define mmGL2A_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER3_LO 0x3396 -#define mmGL2A_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER3_HI 0x3397 -#define mmGL2A_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER0_LO 0x33a0 -#define mmGL1C_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER0_HI 0x33a1 -#define mmGL1C_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER1_LO 0x33a2 -#define mmGL1C_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER1_HI 0x33a3 -#define mmGL1C_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER2_LO 0x33a4 -#define mmGL1C_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER2_HI 0x33a5 -#define mmGL1C_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER3_LO 0x33a6 -#define mmGL1C_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER3_HI 0x33a7 -#define mmGL1C_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmCHC_PERFCOUNTER0_LO 0x33c0 -#define mmCHC_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCHC_PERFCOUNTER0_HI 0x33c1 -#define mmCHC_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCHC_PERFCOUNTER1_LO 0x33c2 -#define mmCHC_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCHC_PERFCOUNTER1_HI 0x33c3 -#define mmCHC_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCHC_PERFCOUNTER2_LO 0x33c4 -#define mmCHC_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmCHC_PERFCOUNTER2_HI 0x33c5 -#define mmCHC_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmCHC_PERFCOUNTER3_LO 0x33c6 -#define mmCHC_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmCHC_PERFCOUNTER3_HI 0x33c7 -#define mmCHC_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER0_LO 0x33c8 -#define mmCHCG_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER0_HI 0x33c9 -#define mmCHCG_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER1_LO 0x33ca -#define mmCHCG_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER1_HI 0x33cb -#define mmCHCG_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER2_LO 0x33cc -#define mmCHCG_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER2_HI 0x33cd -#define mmCHCG_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER3_LO 0x33ce -#define mmCHCG_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER3_HI 0x33cf -#define mmCHCG_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmCB_PERFCOUNTER0_LO 0x3406 -#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCB_PERFCOUNTER0_HI 0x3407 -#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCB_PERFCOUNTER1_LO 0x3408 -#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCB_PERFCOUNTER1_HI 0x3409 -#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCB_PERFCOUNTER2_LO 0x340a -#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmCB_PERFCOUNTER2_HI 0x340b -#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmCB_PERFCOUNTER3_LO 0x340c -#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmCB_PERFCOUNTER3_HI 0x340d -#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmDB_PERFCOUNTER0_LO 0x3440 -#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmDB_PERFCOUNTER0_HI 0x3441 -#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmDB_PERFCOUNTER1_LO 0x3442 -#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmDB_PERFCOUNTER1_HI 0x3443 -#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmDB_PERFCOUNTER2_LO 0x3444 -#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmDB_PERFCOUNTER2_HI 0x3445 -#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmDB_PERFCOUNTER3_LO 0x3446 -#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmDB_PERFCOUNTER3_HI 0x3447 -#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmRLC_PERFCOUNTER0_LO 0x3480 -#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmRLC_PERFCOUNTER0_HI 0x3481 -#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmRLC_PERFCOUNTER1_LO 0x3482 -#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmRLC_PERFCOUNTER1_HI 0x3483 -#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmRMI_PERFCOUNTER0_LO 0x34c0 -#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmRMI_PERFCOUNTER0_HI 0x34c1 -#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmRMI_PERFCOUNTER1_LO 0x34c2 -#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmRMI_PERFCOUNTER1_HI 0x34c3 -#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmRMI_PERFCOUNTER2_LO 0x34c4 -#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmRMI_PERFCOUNTER2_HI 0x34c5 -#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmRMI_PERFCOUNTER3_LO 0x34c6 -#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmRMI_PERFCOUNTER3_HI 0x34c7 -#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER0_LO 0x351c -#define mmUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER0_HI 0x351d -#define mmUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER1_LO 0x351e -#define mmUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER1_HI 0x351f -#define mmUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGCR_PERFCOUNTER0_LO 0x3520 -#define mmGCR_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGCR_PERFCOUNTER0_HI 0x3521 -#define mmGCR_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGCR_PERFCOUNTER1_LO 0x3522 -#define mmGCR_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGCR_PERFCOUNTER1_HI 0x3523 -#define mmGCR_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER0_LO 0x3580 -#define mmPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER0_HI 0x3581 -#define mmPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER1_LO 0x3582 -#define mmPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER1_HI 0x3583 -#define mmPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER2_LO 0x3584 -#define mmPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER2_HI 0x3585 -#define mmPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER3_LO 0x3586 -#define mmPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER3_HI 0x3587 -#define mmPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER4_LO 0x3588 -#define mmPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER4_HI 0x3589 -#define mmPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER5_LO 0x358a -#define mmPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER5_HI 0x358b -#define mmPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER6_LO 0x358c -#define mmPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER6_HI 0x358d -#define mmPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER7_LO 0x358e -#define mmPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER7_HI 0x358f -#define mmPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER0_LO 0x35c0 -#define mmGL1A_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER0_HI 0x35c1 -#define mmGL1A_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER1_LO 0x35c2 -#define mmGL1A_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER1_HI 0x35c3 -#define mmGL1A_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER2_LO 0x35c4 -#define mmGL1A_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER2_HI 0x35c5 -#define mmGL1A_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER3_LO 0x35c6 -#define mmGL1A_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER3_HI 0x35c7 -#define mmGL1A_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmCHA_PERFCOUNTER0_LO 0x3600 -#define mmCHA_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmCHA_PERFCOUNTER0_HI 0x3601 -#define mmCHA_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmCHA_PERFCOUNTER1_LO 0x3602 -#define mmCHA_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmCHA_PERFCOUNTER1_HI 0x3603 -#define mmCHA_PERFCOUNTER1_HI_BASE_IDX 1 -#define mmCHA_PERFCOUNTER2_LO 0x3604 -#define mmCHA_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmCHA_PERFCOUNTER2_HI 0x3605 -#define mmCHA_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmCHA_PERFCOUNTER3_LO 0x3606 -#define mmCHA_PERFCOUNTER3_LO_BASE_IDX 1 -#define mmCHA_PERFCOUNTER3_HI 0x3607 -#define mmCHA_PERFCOUNTER3_HI_BASE_IDX 1 -#define mmGUS_PERFCOUNTER2_LO 0x3640 -#define mmGUS_PERFCOUNTER2_LO_BASE_IDX 1 -#define mmGUS_PERFCOUNTER2_HI 0x3641 -#define mmGUS_PERFCOUNTER2_HI_BASE_IDX 1 -#define mmGUS_PERFCOUNTER_LO 0x3642 -#define mmGUS_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGUS_PERFCOUNTER_HI 0x3643 -#define mmGUS_PERFCOUNTER_HI_BASE_IDX 1 - - -// addressBlock: gc_gcvml2prdec -// base address: 0x353a0 -#define mmGCMC_VM_L2_PERFCOUNTER_LO 0x34e8 -#define mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER_HI 0x34e9 -#define mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER_LO 0x34ea -#define mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER_HI 0x34eb -#define mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 - - -// addressBlock: gc_gcvml2perfddec -// base address: 0x353e0 -#define mmGCVML2_PERFCOUNTER2_0_LO 0x34f8 -#define mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_1_LO 0x34f9 -#define mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_0_HI 0x34fa -#define mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_1_HI 0x34fb -#define mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma0perfddec -// base address: 0x35980 -#define mmSDMA0_PERFCNT_PERFCOUNTER_LO 0x3660 -#define mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define mmSDMA0_PERFCNT_PERFCOUNTER_HI 0x3661 -#define mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER0_LO 0x3662 -#define mmSDMA0_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER0_HI 0x3663 -#define mmSDMA0_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER1_LO 0x3664 -#define mmSDMA0_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER1_HI 0x3665 -#define mmSDMA0_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma1_sdma1perfddec -// base address: 0x359b0 -#define mmSDMA1_PERFCNT_PERFCOUNTER_LO 0x366c -#define mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define mmSDMA1_PERFCNT_PERFCOUNTER_HI 0x366d -#define mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER0_LO 0x366e -#define mmSDMA1_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER0_HI 0x366f -#define mmSDMA1_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER1_LO 0x3670 -#define mmSDMA1_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER1_HI 0x3671 -#define mmSDMA1_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma2_sdma2perfddec -// base address: 0x359e0 -#define mmSDMA2_PERFCNT_PERFCOUNTER_LO 0x3678 -#define mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define mmSDMA2_PERFCNT_PERFCOUNTER_HI 0x3679 -#define mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER0_LO 0x367a -#define mmSDMA2_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER0_HI 0x367b -#define mmSDMA2_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER1_LO 0x367c -#define mmSDMA2_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER1_HI 0x367d -#define mmSDMA2_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma3_sdma3perfddec -// base address: 0x35a10 -#define mmSDMA3_PERFCNT_PERFCOUNTER_LO 0x3684 -#define mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define mmSDMA3_PERFCNT_PERFCOUNTER_HI 0x3685 -#define mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER0_LO 0x3686 -#define mmSDMA3_PERFCOUNTER0_LO_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER0_HI 0x3687 -#define mmSDMA3_PERFCOUNTER0_HI_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER1_LO 0x3688 -#define mmSDMA3_PERFCOUNTER1_LO_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER1_HI 0x3689 -#define mmSDMA3_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_perfsdec -// base address: 0x36000 -#define mmCPG_PERFCOUNTER1_SELECT 0x3800 -#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 -#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCPG_PERFCOUNTER0_SELECT 0x3802 -#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCPC_PERFCOUNTER1_SELECT 0x3803 -#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 -#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCPF_PERFCOUNTER1_SELECT 0x3805 -#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 -#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCPF_PERFCOUNTER0_SELECT 0x3807 -#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCP_PERFMON_CNTL 0x3808 -#define mmCP_PERFMON_CNTL_BASE_IDX 1 -#define mmCPC_PERFCOUNTER0_SELECT 0x3809 -#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a -#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 -#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b -#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 -#define mmCPF_LATENCY_STATS_SELECT 0x380c -#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 -#define mmCPG_LATENCY_STATS_SELECT 0x380d -#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 -#define mmCPC_LATENCY_STATS_SELECT 0x380e -#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 -#define mmCP_DRAW_OBJECT 0x3810 -#define mmCP_DRAW_OBJECT_BASE_IDX 1 -#define mmCP_DRAW_OBJECT_COUNTER 0x3811 -#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 -#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 -#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 -#define mmCP_DRAW_WINDOW_HI 0x3813 -#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 -#define mmCP_DRAW_WINDOW_LO 0x3814 -#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 -#define mmCP_DRAW_WINDOW_CNTL 0x3815 -#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 -#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 -#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 -#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 -#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 -#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 -#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 -#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 -#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 -#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER0_SELECT_HI 0x384d -#define mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 -#define mmGRBM_PERFCOUNTER1_SELECT_HI 0x384e -#define mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 -#define mmGE1_PERFCOUNTER0_SELECT 0x38a4 -#define mmGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGE1_PERFCOUNTER0_SELECT1 0x38a5 -#define mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGE1_PERFCOUNTER1_SELECT 0x38a6 -#define mmGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGE1_PERFCOUNTER1_SELECT1 0x38a7 -#define mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGE1_PERFCOUNTER2_SELECT 0x38a8 -#define mmGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGE1_PERFCOUNTER2_SELECT1 0x38a9 -#define mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGE1_PERFCOUNTER3_SELECT 0x38aa -#define mmGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGE1_PERFCOUNTER3_SELECT1 0x38ab -#define mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER0_SELECT 0x38ac -#define mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad -#define mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER1_SELECT 0x38ae -#define mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER1_SELECT1 0x38af -#define mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 -#define mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 -#define mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 -#define mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 -#define mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER0_SELECT 0x38b4 -#define mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 -#define mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER1_SELECT 0x38b6 -#define mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 -#define mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER2_SELECT 0x38b8 -#define mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 -#define mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER3_SELECT 0x38ba -#define mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGE2_SE_PERFCOUNTER3_SELECT1 0x38bb -#define mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 -#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 -#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 -#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 -#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 -#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER2_SELECT1 0x3905 -#define mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER3_SELECT 0x3906 -#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmPA_SU_PERFCOUNTER3_SELECT1 0x3907 -#define mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 -#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 -#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 -#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 -#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 -#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 -#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 -#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 -#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 -#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER0_SELECT 0x3980 -#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER1_SELECT 0x3981 -#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER2_SELECT 0x3982 -#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER3_SELECT 0x3983 -#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 -#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 -#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 -#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 -#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmSPI_PERFCOUNTER4_SELECT 0x3988 -#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER5_SELECT 0x3989 -#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define mmSPI_PERFCOUNTER_BINS 0x398a -#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 -#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 -#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 -#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 -#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 -#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 -#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 -#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 -#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 -#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 -#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 -#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER10_SELECT 0x39ca -#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER11_SELECT 0x39cb -#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER12_SELECT 0x39cc -#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER13_SELECT 0x39cd -#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER14_SELECT 0x39ce -#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER15_SELECT 0x39cf -#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 -#define mmSQ_PERFCOUNTER_CTRL 0x39e0 -#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 -#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 -#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER2_SELECT 0x3a00 -#define mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER2_SELECT1 0x3a01 -#define mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER2_MODE 0x3a02 -#define mmGCEA_PERFCOUNTER2_MODE_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER0_CFG 0x3a03 -#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER1_CFG 0x3a04 -#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x3a05 -#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmSX_PERFCOUNTER0_SELECT 0x3a40 -#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSX_PERFCOUNTER1_SELECT 0x3a41 -#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSX_PERFCOUNTER2_SELECT 0x3a42 -#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmSX_PERFCOUNTER3_SELECT 0x3a43 -#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 -#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 -#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 -#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 -#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 -#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 -#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 -#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGDS_PERFCOUNTER1_SELECT1 0x3a85 -#define mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGDS_PERFCOUNTER2_SELECT1 0x3a86 -#define mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGDS_PERFCOUNTER3_SELECT1 0x3a87 -#define mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 -#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 -#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 -#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmTD_PERFCOUNTER0_SELECT 0x3b00 -#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 -#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmTD_PERFCOUNTER1_SELECT 0x3b02 -#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 -#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 -#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 -#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 -#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 -#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 -#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER0_SELECT 0x3b80 -#define mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER0_SELECT1 0x3b81 -#define mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER1_SELECT 0x3b82 -#define mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER1_SELECT1 0x3b83 -#define mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER2_SELECT 0x3b84 -#define mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGL2C_PERFCOUNTER3_SELECT 0x3b85 -#define mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER0_SELECT 0x3b90 -#define mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER0_SELECT1 0x3b91 -#define mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER1_SELECT 0x3b92 -#define mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER1_SELECT1 0x3b93 -#define mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER2_SELECT 0x3b94 -#define mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGL2A_PERFCOUNTER3_SELECT 0x3b95 -#define mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER0_SELECT 0x3ba0 -#define mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER0_SELECT1 0x3ba1 -#define mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER1_SELECT 0x3ba2 -#define mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER2_SELECT 0x3ba3 -#define mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGL1C_PERFCOUNTER3_SELECT 0x3ba4 -#define mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmCHC_PERFCOUNTER0_SELECT 0x3bc0 -#define mmCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCHC_PERFCOUNTER0_SELECT1 0x3bc1 -#define mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCHC_PERFCOUNTER1_SELECT 0x3bc2 -#define mmCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCHC_PERFCOUNTER2_SELECT 0x3bc3 -#define mmCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmCHC_PERFCOUNTER3_SELECT 0x3bc4 -#define mmCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER0_SELECT 0x3bc6 -#define mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER0_SELECT1 0x3bc7 -#define mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER1_SELECT 0x3bc8 -#define mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER2_SELECT 0x3bc9 -#define mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmCHCG_PERFCOUNTER3_SELECT 0x3bca -#define mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmCB_PERFCOUNTER_FILTER 0x3c00 -#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 -#define mmCB_PERFCOUNTER0_SELECT 0x3c01 -#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 -#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCB_PERFCOUNTER1_SELECT 0x3c03 -#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCB_PERFCOUNTER2_SELECT 0x3c04 -#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmCB_PERFCOUNTER3_SELECT 0x3c05 -#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmDB_PERFCOUNTER0_SELECT 0x3c40 -#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 -#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmDB_PERFCOUNTER1_SELECT 0x3c42 -#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 -#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmDB_PERFCOUNTER2_SELECT 0x3c44 -#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmDB_PERFCOUNTER3_SELECT 0x3c46 -#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_CNTL 0x3c80 -#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 -#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 -#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 -#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_RING_RDPTR 0x3c85 -#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 -#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c86 -#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 -#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c87 -#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 -#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c88 -#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c89 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c8a -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 -#define mmRLC_SPM_DESER_START_SKEW 0x3c8b -#define mmRLC_SPM_DESER_START_SKEW_BASE_IDX 1 -#define mmRLC_SPM_GLOBALS_SAMPLE_SKEW 0x3c8c -#define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX 1 -#define mmRLC_SPM_GLOBALS_MUXSEL_SKEW 0x3c8d -#define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX 1 -#define mmRLC_SPM_SE_SAMPLE_SKEW 0x3c8e -#define mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX 1 -#define mmRLC_SPM_SE_MUXSEL_SKEW 0x3c8f -#define mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX 1 -#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR 0x3c90 -#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX 1 -#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA 0x3c91 -#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX 1 -#define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR 0x3c92 -#define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX 1 -#define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA 0x3c93 -#define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX 1 -#define mmRLC_SPM_RING_WRPTR 0x3c94 -#define mmRLC_SPM_RING_WRPTR_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_DATARAM_ADDR 0x3c95 -#define mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_DATARAM_DATA 0x3c96 -#define mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c97 -#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c98 -#define mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_STATUS 0x3c99 -#define mmRLC_SPM_ACCUM_STATUS_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_CTRL 0x3c9a -#define mmRLC_SPM_ACCUM_CTRL_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_MODE 0x3c9b -#define mmRLC_SPM_ACCUM_MODE_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_THRESHOLD 0x3c9c -#define mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d -#define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e -#define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE 0x3c9f -#define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE 0x3ca0 -#define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_VIRT_CTRL 0x3ca1 -#define mmRLC_SPM_VIRT_CTRL_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE 0x3ca2 -#define mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_VIRT_STATUS 0x3ca3 -#define mmRLC_SPM_VIRT_STATUS_BASE_IDX 1 -#define mmRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca4 -#define mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 -#define mmRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca5 -#define mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE 0x3ca6 -#define mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET 0x3ca7 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX 1 -#define mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET 0x3ca8 -#define mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3ca9 -#define mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3caa -#define mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3cab -#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 -#define mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE 0x3cac -#define mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX 1 -#define mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3cad -#define mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 -#define mmRLC_PERFMON_CNTL 0x3cc0 -#define mmRLC_PERFMON_CNTL_BASE_IDX 1 -#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 -#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 -#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 -#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 -#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 -#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 -#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 -#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 -#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 -#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 -#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 -#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 -#define mmRLC_PERFMON_CLK_CNTL 0x3ce4 -#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 -#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 -#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 -#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 -#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 -#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 -#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 -#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmRMI_PERF_COUNTER_CNTL 0x3d06 -#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 -#define mmGCR_PERFCOUNTER0_SELECT 0x3d60 -#define mmGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGCR_PERFCOUNTER0_SELECT1 0x3d61 -#define mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGCR_PERFCOUNTER1_SELECT 0x3d62 -#define mmGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER0_SELECT 0x3d63 -#define mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmUTCL1_PERFCOUNTER1_SELECT 0x3d64 -#define mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER0_SELECT 0x3d80 -#define mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER0_SELECT1 0x3d81 -#define mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER1_SELECT 0x3d82 -#define mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER2_SELECT 0x3d83 -#define mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER3_SELECT 0x3d84 -#define mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER4_SELECT 0x3d85 -#define mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER5_SELECT 0x3d86 -#define mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER6_SELECT 0x3d87 -#define mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER7_SELECT 0x3d88 -#define mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER1_SELECT1 0x3d90 -#define mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER2_SELECT1 0x3d91 -#define mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmPA_PH_PERFCOUNTER3_SELECT1 0x3d92 -#define mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER0_SELECT 0x3dc0 -#define mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER0_SELECT1 0x3dc1 -#define mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER1_SELECT 0x3dc2 -#define mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER2_SELECT 0x3dc3 -#define mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGL1A_PERFCOUNTER3_SELECT 0x3dc4 -#define mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmCHA_PERFCOUNTER0_SELECT 0x3de0 -#define mmCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmCHA_PERFCOUNTER0_SELECT1 0x3de1 -#define mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmCHA_PERFCOUNTER1_SELECT 0x3de2 -#define mmCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmCHA_PERFCOUNTER2_SELECT 0x3de3 -#define mmCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmCHA_PERFCOUNTER3_SELECT 0x3de4 -#define mmCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define mmGUS_PERFCOUNTER2_SELECT 0x3e00 -#define mmGUS_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define mmGUS_PERFCOUNTER2_SELECT1 0x3e01 -#define mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define mmGUS_PERFCOUNTER2_MODE 0x3e02 -#define mmGUS_PERFCOUNTER2_MODE_BASE_IDX 1 -#define mmGUS_PERFCOUNTER0_CFG 0x3e03 -#define mmGUS_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmGUS_PERFCOUNTER1_CFG 0x3e04 -#define mmGUS_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmGUS_PERFCOUNTER_RSLT_CNTL 0x3e05 -#define mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gcvml2pldec -// base address: 0x374b0 -#define mmGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d2c -#define mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d2d -#define mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d2e -#define mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d2f -#define mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d30 -#define mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d31 -#define mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d32 -#define mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d33 -#define mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 -#define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d34 -#define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER0_CFG 0x3d35 -#define mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER1_CFG 0x3d36 -#define mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER2_CFG 0x3d37 -#define mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER3_CFG 0x3d38 -#define mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 -#define mmGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3d39 -#define mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gcvml2perfsdec -// base address: 0x374f0 -#define mmGCVML2_PERFCOUNTER2_0_SELECT 0x3d3c -#define mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_1_SELECT 0x3d3d -#define mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_0_SELECT1 0x3d3e -#define mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_1_SELECT1 0x3d3f -#define mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_0_MODE 0x3d40 -#define mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1 -#define mmGCVML2_PERFCOUNTER2_1_MODE 0x3d41 -#define mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma0perfsdec -// base address: 0x37880 -#define mmSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x3e20 -#define mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x3e21 -#define mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e22 -#define mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmSDMA0_PERFCNT_MISC_CNTL 0x3e23 -#define mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER0_SELECT 0x3e24 -#define mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER0_SELECT1 0x3e25 -#define mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER1_SELECT 0x3e26 -#define mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSDMA0_PERFCOUNTER1_SELECT1 0x3e27 -#define mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// addressBlock: gc_sdma1_sdma1perfsdec -// base address: 0x378b0 -#define mmSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x3e2c -#define mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x3e2d -#define mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e2e -#define mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmSDMA1_PERFCNT_MISC_CNTL 0x3e2f -#define mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER0_SELECT 0x3e30 -#define mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER0_SELECT1 0x3e31 -#define mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER1_SELECT 0x3e32 -#define mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSDMA1_PERFCOUNTER1_SELECT1 0x3e33 -#define mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// addressBlock: gc_sdma2_sdma2perfsdec -// base address: 0x378e0 -#define mmSDMA2_PERFCNT_PERFCOUNTER0_CFG 0x3e38 -#define mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmSDMA2_PERFCNT_PERFCOUNTER1_CFG 0x3e39 -#define mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e3a -#define mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmSDMA2_PERFCNT_MISC_CNTL 0x3e3b -#define mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER0_SELECT 0x3e3c -#define mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER0_SELECT1 0x3e3d -#define mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER1_SELECT 0x3e3e -#define mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSDMA2_PERFCOUNTER1_SELECT1 0x3e3f -#define mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// addressBlock: gc_sdma3_sdma3perfsdec -// base address: 0x37910 -#define mmSDMA3_PERFCNT_PERFCOUNTER0_CFG 0x3e44 -#define mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define mmSDMA3_PERFCNT_PERFCOUNTER1_CFG 0x3e45 -#define mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e46 -#define mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define mmSDMA3_PERFCNT_MISC_CNTL 0x3e47 -#define mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER0_SELECT 0x3e48 -#define mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER0_SELECT1 0x3e49 -#define mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER1_SELECT 0x3e4a -#define mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define mmSDMA3_PERFCOUNTER1_SELECT1 0x3e4b -#define mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// base address: 0x3a000 - - -// addressBlock: gc_grtavfsdec -// base address: 0x3ac00 -#define mmGRTAVFS_RTAVFS_REG_ADDR 0x4b00 -#define mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 -#define mmRTAVFS_RTAVFS_REG_ADDR 0x4b00 -#define mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 -#define mmGRTAVFS_RTAVFS_WR_DATA 0x4b01 -#define mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 -#define mmRTAVFS_RTAVFS_WR_DATA 0x4b01 -#define mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 -#define mmGRTAVFS_GENERAL_0 0x4b02 -#define mmGRTAVFS_GENERAL_0_BASE_IDX 1 -#define mmGRTAVFS_RTAVFS_RD_DATA 0x4b03 -#define mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX 1 -#define mmGRTAVFS_RTAVFS_REG_CTRL 0x4b04 -#define mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX 1 -#define mmGRTAVFS_RTAVFS_REG_STATUS 0x4b05 -#define mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX 1 -#define mmGRTAVFS_TARG_FREQ 0x4b06 -#define mmGRTAVFS_TARG_FREQ_BASE_IDX 1 -#define mmGRTAVFS_TARG_VOLT 0x4b07 -#define mmGRTAVFS_TARG_VOLT_BASE_IDX 1 -#define mmGRTAVFS_SOFT_RESET 0x4b0f -#define mmGRTAVFS_SOFT_RESET_BASE_IDX 1 -#define mmGRTAVFS_PSM_CNTL 0x4b10 -#define mmGRTAVFS_PSM_CNTL_BASE_IDX 1 -#define mmGRTAVFS_CLK_CNTL 0x4b11 -#define mmGRTAVFS_CLK_CNTL_BASE_IDX 1 - - -// addressBlock: gc_rlcdec -// base address: 0x3b000 -#define mmRLC_CNTL 0x4c00 -#define mmRLC_CNTL_BASE_IDX 1 -#define mmRLC_F32_UCODE_VERSION 0x4c03 -#define mmRLC_F32_UCODE_VERSION_BASE_IDX 1 -#define mmRLC_STAT 0x4c04 -#define mmRLC_STAT_BASE_IDX 1 -#define mmRLC_MEM_SLP_CNTL 0x4c06 -#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 -#define mmSMU_RLC_RESPONSE 0x4c07 -#define mmSMU_RLC_RESPONSE_BASE_IDX 1 -#define mmRLC_RLCV_SAFE_MODE 0x4c08 -#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 -#define mmRLC_SMU_SAFE_MODE 0x4c09 -#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 -#define mmRLC_RLCV_COMMAND 0x4c0a -#define mmRLC_RLCV_COMMAND_BASE_IDX 1 -#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c -#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 -#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d -#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 -#define mmRLC_GPM_TIMER_INT_0 0x4c0e -#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 -#define mmRLC_GPM_TIMER_INT_1 0x4c0f -#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 -#define mmRLC_GPM_TIMER_INT_2 0x4c10 -#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 -#define mmRLC_GPM_TIMER_CTRL 0x4c11 -#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 -#define mmRLC_LB_CNTR_MAX_1 0x4c12 -#define mmRLC_LB_CNTR_MAX_1_BASE_IDX 1 -#define mmRLC_GPM_TIMER_STAT 0x4c13 -#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 -#define mmRLC_GPM_TIMER_INT_3 0x4c15 -#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 -#define mmRLC_GPM_LEGACY_INT_STAT 0x4c16 -#define mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 -#define mmRLC_GPM_LEGACY_INT_CLEAR 0x4c17 -#define mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 -#define mmRLC_INT_STAT 0x4c18 -#define mmRLC_INT_STAT_BASE_IDX 1 -#define mmRLC_LB_CNTL 0x4c19 -#define mmRLC_LB_CNTL_BASE_IDX 1 -#define mmRLC_MGCG_CTRL 0x4c1a -#define mmRLC_MGCG_CTRL_BASE_IDX 1 -#define mmRLC_LB_CNTR_INIT_1 0x4c1b -#define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1 -#define mmRLC_LB_CNTR_1 0x4c1c -#define mmRLC_LB_CNTR_1_BASE_IDX 1 -#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e -#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 -#define mmRLC_PG_DELAY_2 0x4c1f -#define mmRLC_PG_DELAY_2_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 -#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 -#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 -#define mmRLC_UCODE_CNTL 0x4c27 -#define mmRLC_UCODE_CNTL_BASE_IDX 1 -#define mmRLC_GPM_THREAD_RESET 0x4c28 -#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 -#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 -#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 -#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a -#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 -#define mmRLC_LB_CNTR_INIT_2 0x4c2b -#define mmRLC_LB_CNTR_INIT_2_BASE_IDX 1 -#define mmRLC_LB_CNTR_MAX_2 0x4c2c -#define mmRLC_LB_CNTR_MAX_2_BASE_IDX 1 -#define mmRLC_LB_CONFIG_5 0x4c2e -#define mmRLC_LB_CONFIG_5_BASE_IDX 1 -#define mmRLC_GPM_TIMER_INT_4 0x4c2f -#define mmRLC_GPM_TIMER_INT_4_BASE_IDX 1 -#define mmRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 -#define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 -#define mmRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 -#define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 -#define mmRLC_CLK_COUNT_REFCLK_LSB 0x4c32 -#define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 -#define mmRLC_CLK_COUNT_REFCLK_MSB 0x4c33 -#define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 -#define mmRLC_CLK_COUNT_CTRL 0x4c34 -#define mmRLC_CLK_COUNT_CTRL_BASE_IDX 1 -#define mmRLC_CLK_COUNT_STAT 0x4c35 -#define mmRLC_CLK_COUNT_STAT_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_CNTL 0x4c36 -#define mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_STAT 0x4c37 -#define mmRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 -#define mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 -#define mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a -#define mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b -#define mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c -#define mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d -#define mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e -#define mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f -#define mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 -#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_32 0x4c42 -#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 -#define mmRLC_PG_CNTL 0x4c43 -#define mmRLC_PG_CNTL_BASE_IDX 1 -#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 -#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 -#define mmRLC_GPM_THREAD_ENABLE 0x4c45 -#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 -#define mmRLC_RLCG_DOORBELL_RANGE 0x4c47 -#define mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 -#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 -#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 -#define mmRLC_CGCG_CGLS_CTRL 0x4c49 -#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 -#define mmRLC_CGCG_RAMP_CTRL 0x4c4a -#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 -#define mmRLC_DYN_PG_STATUS 0x4c4b -#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 -#define mmRLC_DYN_PG_REQUEST 0x4c4c -#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 -#define mmRLC_PG_DELAY 0x4c4d -#define mmRLC_PG_DELAY_BASE_IDX 1 -#define mmRLC_WGP_STATUS 0x4c4e -#define mmRLC_WGP_STATUS_BASE_IDX 1 -#define mmRLC_LB_INIT_WGP_MASK 0x4c4f -#define mmRLC_LB_INIT_WGP_MASK_BASE_IDX 1 -#define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK 0x4c50 -#define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX 1 -#define mmRLC_LB_PARAMS 0x4c51 -#define mmRLC_LB_PARAMS_BASE_IDX 1 -#define mmRLC_LB_DELAY 0x4c52 -#define mmRLC_LB_DELAY_BASE_IDX 1 -#define mmRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 -#define mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 -#define mmRLC_MAX_PG_WGP 0x4c54 -#define mmRLC_MAX_PG_WGP_BASE_IDX 1 -#define mmRLC_AUTO_PG_CTRL 0x4c55 -#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 -#define mmRLC_SERDES_RD_INDEX 0x4c59 -#define mmRLC_SERDES_RD_INDEX_BASE_IDX 1 -#define mmRLC_SERDES_RD_DATA_0 0x4c5a -#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 -#define mmRLC_SERDES_RD_DATA_1 0x4c5b -#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 -#define mmRLC_SERDES_RD_DATA_2 0x4c5c -#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 -#define mmRLC_SERDES_RD_DATA_3 0x4c5d -#define mmRLC_SERDES_RD_DATA_3_BASE_IDX 1 -#define mmRLC_SERDES_MASK 0x4c5e -#define mmRLC_SERDES_MASK_BASE_IDX 1 -#define mmRLC_SERDES_CTRL 0x4c5f -#define mmRLC_SERDES_CTRL_BASE_IDX 1 -#define mmRLC_SERDES_DATA 0x4c60 -#define mmRLC_SERDES_DATA_BASE_IDX 1 -#define mmRLC_SERDES_BUSY 0x4c61 -#define mmRLC_SERDES_BUSY_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_0 0x4c63 -#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_1 0x4c64 -#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_2 0x4c65 -#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_3 0x4c66 -#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_4 0x4c67 -#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_5 0x4c68 -#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_6 0x4c69 -#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_7 0x4c6a -#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 -#define mmRLC_STATIC_PG_STATUS 0x4c6e -#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 -#define mmRLC_SPM_INT_INFO_1 0x4c6f -#define mmRLC_SPM_INT_INFO_1_BASE_IDX 1 -#define mmRLC_SPM_INT_INFO_2 0x4c70 -#define mmRLC_SPM_INT_INFO_2_BASE_IDX 1 -#define mmRLC_SPM_MC_CNTL 0x4c71 -#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 -#define mmRLC_SPM_INT_CNTL 0x4c72 -#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 -#define mmRLC_SPM_INT_STATUS 0x4c73 -#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 -#define mmRLC_SMU_MESSAGE 0x4c76 -#define mmRLC_SMU_MESSAGE_BASE_IDX 1 -#define mmRLC_GPM_LOG_SIZE 0x4c77 -#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 -#define mmRLC_PG_DELAY_3 0x4c78 -#define mmRLC_PG_DELAY_3_BASE_IDX 1 -#define mmRLC_GPR_REG1 0x4c79 -#define mmRLC_GPR_REG1_BASE_IDX 1 -#define mmRLC_GPR_REG2 0x4c7a -#define mmRLC_GPR_REG2_BASE_IDX 1 -#define mmRLC_GPM_LOG_CONT 0x4c7b -#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 -#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c -#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 -#define mmRLC_GPM_LEGACY_INT_DISABLE 0x4c7d -#define mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 -#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e -#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 -#define mmRLC_SRM_CNTL 0x4c80 -#define mmRLC_SRM_CNTL_BASE_IDX 1 -#define mmRLC_SRM_GPM_COMMAND 0x4c87 -#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 -#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 -#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 -#define mmRLC_SRM_RLCV_COMMAND 0x4c89 -#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 -#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a -#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b -#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c -#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d -#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e -#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f -#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 -#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 -#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 -#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 -#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 -#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 -#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 -#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 -#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 -#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a -#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 -#define mmRLC_SRM_STAT 0x4c9b -#define mmRLC_SRM_STAT_BASE_IDX 1 -#define mmRLC_SRM_GPM_ABORT 0x4c9c -#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 -#define mmRLC_SPARE_INT_2 0x4c9d -#define mmRLC_SPARE_INT_2_BASE_IDX 1 -#define mmRLC_RLCV_SPARE_INT_1 0x4c9e -#define mmRLC_RLCV_SPARE_INT_1_BASE_IDX 1 -#define mmRLC_PACE_SPARE_INT_1 0x4c9f -#define mmRLC_PACE_SPARE_INT_1_BASE_IDX 1 -#define mmRLC_SAFE_MODE 0x4ca0 -#define mmRLC_SAFE_MODE_BASE_IDX 1 -#define mmRLC_CP_SCHEDULERS 0x4ca1 -#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 -#define mmRLC_CSIB_ADDR_LO 0x4ca2 -#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 -#define mmRLC_CSIB_ADDR_HI 0x4ca3 -#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 -#define mmRLC_CSIB_LENGTH 0x4ca4 -#define mmRLC_CSIB_LENGTH_BASE_IDX 1 -#define mmRLC_SPARE_INT_0 0x4ca5 -#define mmRLC_SPARE_INT_0_BASE_IDX 1 -#define mmRLC_CP_EOF_INT_CNT 0x4ca6 -#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 -#define mmRLC_CP_EOF_INT 0x4ca7 -#define mmRLC_CP_EOF_INT_BASE_IDX 1 -#define mmRLC_SMU_COMMAND 0x4ca9 -#define mmRLC_SMU_COMMAND_BASE_IDX 1 -#define mmRLC_SMU_ARGUMENT_1 0x4cab -#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 -#define mmRLC_SMU_ARGUMENT_2 0x4cac -#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_8 0x4cad -#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_9 0x4cae -#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_10 0x4caf -#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_11 0x4cb0 -#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_12 0x4cb1 -#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 -#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 -#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 -#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 -#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 -#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 -#define mmRLC_UTCL1_STATUS_2 0x4cb6 -#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 -#define mmRLC_LB_CONFIG_2 0x4cb8 -#define mmRLC_LB_CONFIG_2_BASE_IDX 1 -#define mmRLC_LB_CONFIG_3 0x4cb9 -#define mmRLC_LB_CONFIG_3_BASE_IDX 1 -#define mmRLC_LB_CONFIG_4 0x4cba -#define mmRLC_LB_CONFIG_4_BASE_IDX 1 -#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc -#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 -#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd -#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe -#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 -#define mmRLC_LB_CONFIG_1 0x4cbf -#define mmRLC_LB_CONFIG_1_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 -#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 -#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 -#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 -#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 -#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 -#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 -#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 -#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 -#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 -#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 -#define mmRLC_SEMAPHORE_0 0x4cc7 -#define mmRLC_SEMAPHORE_0_BASE_IDX 1 -#define mmRLC_SEMAPHORE_1 0x4cc8 -#define mmRLC_SEMAPHORE_1_BASE_IDX 1 -#define mmRLC_PACE_INT_STAT 0x4ccc -#define mmRLC_PACE_INT_STAT_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd -#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce -#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf -#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 -#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 -#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 -#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 -#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 -#define mmRLC_UTCL1_STATUS 0x4cd4 -#define mmRLC_UTCL1_STATUS_BASE_IDX 1 -#define mmRLC_R2I_CNTL_0 0x4cd5 -#define mmRLC_R2I_CNTL_0_BASE_IDX 1 -#define mmRLC_R2I_CNTL_1 0x4cd6 -#define mmRLC_R2I_CNTL_1_BASE_IDX 1 -#define mmRLC_R2I_CNTL_2 0x4cd7 -#define mmRLC_R2I_CNTL_2_BASE_IDX 1 -#define mmRLC_R2I_CNTL_3 0x4cd8 -#define mmRLC_R2I_CNTL_3_BASE_IDX 1 -#define mmRLC_LB_WGP_STAT 0x4cda -#define mmRLC_LB_WGP_STAT_BASE_IDX 1 -#define mmRLC_GPM_INT_STAT_TH0 0x4cdc -#define mmRLC_GPM_INT_STAT_TH0_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_13 0x4cdd -#define mmRLC_GPM_GENERAL_13_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_14 0x4cde -#define mmRLC_GPM_GENERAL_14_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_15 0x4cdf -#define mmRLC_GPM_GENERAL_15_BASE_IDX 1 -#define mmRLC_SPARE_INT_1 0x4ce0 -#define mmRLC_SPARE_INT_1_BASE_IDX 1 -#define mmRLC_SEMAPHORE_2 0x4ce3 -#define mmRLC_SEMAPHORE_2_BASE_IDX 1 -#define mmRLC_SEMAPHORE_3 0x4ce4 -#define mmRLC_SEMAPHORE_3_BASE_IDX 1 -#define mmRLC_SMU_ARGUMENT_3 0x4ce5 -#define mmRLC_SMU_ARGUMENT_3_BASE_IDX 1 -#define mmRLC_SMU_ARGUMENT_4 0x4ce6 -#define mmRLC_SMU_ARGUMENT_4_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 -#define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 -#define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb -#define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec -#define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 -#define mmRLC_PACE_INT_DISABLE 0x4ced -#define mmRLC_PACE_INT_DISABLE_BASE_IDX 1 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_RANGE 0x4cf0 -#define mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_CNTL 0x4cf1 -#define mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_STAT 0x4cf2 -#define mmRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 -#define mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 -#define mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 -#define mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 -#define mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 -#define mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 -#define mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 -#define mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa -#define mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCV_SPARE_INT 0x4d00 -#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 -#define mmRLC_PACE_TIMER_INT_0 0x4d04 -#define mmRLC_PACE_TIMER_INT_0_BASE_IDX 1 -#define mmRLC_PACE_TIMER_CTRL 0x4d05 -#define mmRLC_PACE_TIMER_CTRL_BASE_IDX 1 -#define mmRLC_PACE_TIMER_INT_1 0x4d06 -#define mmRLC_PACE_TIMER_INT_1_BASE_IDX 1 -#define mmRLC_PACE_SPARE_INT 0x4d07 -#define mmRLC_PACE_SPARE_INT_BASE_IDX 1 -#define mmRLC_SMU_CLK_REQ 0x4d08 -#define mmRLC_SMU_CLK_REQ_BASE_IDX 1 -#define mmRLC_CP_STAT_INVAL_STAT 0x4d09 -#define mmRLC_CP_STAT_INVAL_STAT_BASE_IDX 1 -#define mmRLC_CP_STAT_INVAL_CTRL 0x4d0a -#define mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1 -#define mmRLC_CLK_STATUS 0x4d0b -#define mmRLC_CLK_STATUS_BASE_IDX 1 -#define mmRLC_SPP_CTRL 0x4d0c -#define mmRLC_SPP_CTRL_BASE_IDX 1 -#define mmRLC_SPP_SHADER_PROFILE_EN 0x4d0d -#define mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 -#define mmRLC_SPP_SSF_CAPTURE_EN 0x4d0e -#define mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 -#define mmRLC_SPP_SSF_THRESHOLD_0 0x4d0f -#define mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 -#define mmRLC_SPP_SSF_THRESHOLD_1 0x4d10 -#define mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 -#define mmRLC_SPP_SSF_THRESHOLD_2 0x4d11 -#define mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 -#define mmRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 -#define mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 -#define mmRLC_SPP_INFLIGHT_RD_DATA 0x4d13 -#define mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 -#define mmRLC_GPM_GENERAL_16 0x4d14 -#define mmRLC_GPM_GENERAL_16_BASE_IDX 1 -#define mmRLC_SPP_PROF_INFO_1 0x4d18 -#define mmRLC_SPP_PROF_INFO_1_BASE_IDX 1 -#define mmRLC_SPP_PROF_INFO_2 0x4d19 -#define mmRLC_SPP_PROF_INFO_2_BASE_IDX 1 -#define mmRLC_SPP_GLOBAL_SH_ID 0x4d1a -#define mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 -#define mmRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b -#define mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 -#define mmRLC_SPP_STATUS 0x4d1c -#define mmRLC_SPP_STATUS_BASE_IDX 1 -#define mmRLC_SPP_PVT_STAT_0 0x4d1d -#define mmRLC_SPP_PVT_STAT_0_BASE_IDX 1 -#define mmRLC_SPP_PVT_STAT_1 0x4d1e -#define mmRLC_SPP_PVT_STAT_1_BASE_IDX 1 -#define mmRLC_SPP_PVT_STAT_2 0x4d1f -#define mmRLC_SPP_PVT_STAT_2_BASE_IDX 1 -#define mmRLC_SPP_PVT_STAT_3 0x4d20 -#define mmRLC_SPP_PVT_STAT_3_BASE_IDX 1 -#define mmRLC_SPP_PVT_LEVEL_MAX 0x4d21 -#define mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 -#define mmRLC_SPP_STALL_STATE_UPDATE 0x4d22 -#define mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 -#define mmRLC_SPP_PBB_INFO 0x4d23 -#define mmRLC_SPP_PBB_INFO_BASE_IDX 1 -#define mmRLC_SPP_RESET 0x4d24 -#define mmRLC_SPP_RESET_BASE_IDX 1 -#define mmRLC_SPM_SAMPLE_CNT 0x4d25 -#define mmRLC_SPM_SAMPLE_CNT_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_RANGE 0x4d26 -#define mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_CNTL 0x4d27 -#define mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_STAT 0x4d28 -#define mmRLC_RLCP_DOORBELL_STAT_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_0_DATA_LO 0x4d29 -#define mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_0_DATA_HI 0x4d2a -#define mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_1_DATA_LO 0x4d2b -#define mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_1_DATA_HI 0x4d2c -#define mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_2_DATA_LO 0x4d2d -#define mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_2_DATA_HI 0x4d2e -#define mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_3_DATA_LO 0x4d2f -#define mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define mmRLC_RLCP_DOORBELL_3_DATA_HI 0x4d30 -#define mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL 0x4d44 -#define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX 1 -#define mmRLC_CAC_MASK_CNTL 0x4d45 -#define mmRLC_CAC_MASK_CNTL_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 -#define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 -#define mmRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 -#define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 -#define mmRLC_SPM_THREAD_TRACE_CTRL 0x4de6 -#define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 -#define mmRLC_LB_CNTR_2 0x4de7 -#define mmRLC_LB_CNTR_2_BASE_IDX 1 -#define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1 -#define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1 -#define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2 -#define mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX 1 -#define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB 0x4df3 -#define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX 1 -#define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB 0x4df4 -#define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_RANGE 0x4df5 -#define mmRLC_XT_DOORBELL_RANGE_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_CNTL 0x4df6 -#define mmRLC_XT_DOORBELL_CNTL_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_STAT 0x4df7 -#define mmRLC_XT_DOORBELL_STAT_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_0_DATA_LO 0x4df8 -#define mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_0_DATA_HI 0x4df9 -#define mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_1_DATA_LO 0x4dfa -#define mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_1_DATA_HI 0x4dfb -#define mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_2_DATA_LO 0x4dfc -#define mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_2_DATA_HI 0x4dfd -#define mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_3_DATA_LO 0x4dfe -#define mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define mmRLC_XT_DOORBELL_3_DATA_HI 0x4dff -#define mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 - - -// addressBlock: gc_rlcrdec -// base address: 0x3b800 -#define mmRLC_SPP_CAM_ADDR 0x4e00 -#define mmRLC_SPP_CAM_ADDR_BASE_IDX 1 -#define mmRLC_SPP_CAM_DATA 0x4e01 -#define mmRLC_SPP_CAM_DATA_BASE_IDX 1 -#define mmRLC_SPP_CAM_EXT_ADDR 0x4e02 -#define mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 -#define mmRLC_SPP_CAM_EXT_DATA 0x4e03 -#define mmRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 -#define mmRLC_PACE_SCRATCH_ADDR 0x4e04 -#define mmRLC_PACE_SCRATCH_ADDR_BASE_IDX 1 -#define mmRLC_PACE_SCRATCH_DATA 0x4e05 -#define mmRLC_PACE_SCRATCH_DATA_BASE_IDX 1 - - -// addressBlock: gc_rlcsdec -// base address: 0x3b980 -#define mmRLC_RLCS_DEC_START 0x4e60 -#define mmRLC_RLCS_DEC_START_BASE_IDX 1 -#define mmRLC_RLCS_DEC_DUMP_ADDR 0x4e61 -#define mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 -#define mmRLC_RLCS_EXCEPTION_REG_1 0x4e62 -#define mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 -#define mmRLC_RLCS_EXCEPTION_REG_2 0x4e63 -#define mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 -#define mmRLC_RLCS_EXCEPTION_REG_3 0x4e64 -#define mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 -#define mmRLC_RLCS_EXCEPTION_REG_4 0x4e65 -#define mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_6 0x4e66 -#define mmRLC_RLCS_GENERAL_6_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_7 0x4e67 -#define mmRLC_RLCS_GENERAL_7_BASE_IDX 1 -#define mmRLC_RLCS_CGCG_REQUEST 0x4e68 -#define mmRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 -#define mmRLC_RLCS_CGCG_STATUS 0x4e69 -#define mmRLC_RLCS_CGCG_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_SMU_GFXCLK_STATUS 0x4e6a -#define mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_SMU_GFXCLK_CONTROL 0x4e6b -#define mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX 1 -#define mmRLC_RLCS_SOC_DS_CNTL 0x4e6c -#define mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_GFX_DS_CNTL 0x4e6d -#define mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 -#define mmRLC_GPM_STAT 0x4e6e -#define mmRLC_GPM_STAT_BASE_IDX 1 -#define mmRLC_RLCS_GPM_STAT 0x4e6e -#define mmRLC_RLCS_GPM_STAT_BASE_IDX 1 -#define mmRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6f -#define mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 -#define mmRLC_RLCS_DIDT_FORCE_STALL 0x4e70 -#define mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1 -#define mmRLC_RLCS_IOV_CMD_STATUS 0x4e71 -#define mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e72 -#define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 -#define mmRLC_RLCS_IOV_SCH_BLOCK 0x4e73 -#define mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 -#define mmRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e74 -#define mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_GPM_STAT_2 0x4e75 -#define mmRLC_RLCS_GPM_STAT_2_BASE_IDX 1 -#define mmRLC_RLCS_GRBM_SOFT_RESET 0x4e76 -#define mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 -#define mmRLC_RLCS_PG_CHANGE_STATUS 0x4e77 -#define mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_PG_CHANGE_READ 0x4e78 -#define mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 -#define mmRLC_RLCS_LB_STATUS 0x4e79 -#define mmRLC_RLCS_LB_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_LB_READ 0x4e7a -#define mmRLC_RLCS_LB_READ_BASE_IDX 1 -#define mmRLC_RLCS_LB_CONTROL 0x4e7b -#define mmRLC_RLCS_LB_CONTROL_BASE_IDX 1 -#define mmRLC_RLCS_IH_SEMAPHORE 0x4e7c -#define mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 -#define mmRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e7d -#define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 -#define mmRLC_RLCS_IH_CTRL_1 0x4e7e -#define mmRLC_RLCS_IH_CTRL_1_BASE_IDX 1 -#define mmRLC_RLCS_IH_CTRL_2 0x4e7f -#define mmRLC_RLCS_IH_CTRL_2_BASE_IDX 1 -#define mmRLC_RLCS_IH_CTRL_3 0x4e80 -#define mmRLC_RLCS_IH_CTRL_3_BASE_IDX 1 -#define mmRLC_RLCS_IH_STATUS 0x4e81 -#define mmRLC_RLCS_IH_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_WGP_STATUS 0x4e82 -#define mmRLC_RLCS_WGP_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_WGP_READ 0x4e83 -#define mmRLC_RLCS_WGP_READ_BASE_IDX 1 -#define mmRLC_RLCS_CP_INT_CTRL_1 0x4e84 -#define mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 -#define mmRLC_RLCS_CP_INT_CTRL_2 0x4e85 -#define mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 -#define mmRLC_RLCS_CP_INT_INFO_1 0x4e86 -#define mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 -#define mmRLC_RLCS_CP_INT_INFO_2 0x4e87 -#define mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 -#define mmRLC_RLCS_SPM_INT_CTRL 0x4e88 -#define mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 -#define mmRLC_RLCS_SPM_INT_INFO_1 0x4e89 -#define mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 -#define mmRLC_RLCS_SPM_INT_INFO_2 0x4e8a -#define mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 -#define mmRLC_RLCS_DSM_TRIG 0x4e8b -#define mmRLC_RLCS_DSM_TRIG_BASE_IDX 1 -#define mmRLC_RLCS_BOOTLOAD_STATUS 0x4e8d -#define mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 -#define mmRLC_RLCS_POWER_BRAKE_CNTL 0x4e8e -#define mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_0 0x4e8f -#define mmRLC_RLCS_GENERAL_0_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_1 0x4e90 -#define mmRLC_RLCS_GENERAL_1_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_2 0x4e91 -#define mmRLC_RLCS_GENERAL_2_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_3 0x4e92 -#define mmRLC_RLCS_GENERAL_3_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_4 0x4e93 -#define mmRLC_RLCS_GENERAL_4_BASE_IDX 1 -#define mmRLC_RLCS_GENERAL_5 0x4e94 -#define mmRLC_RLCS_GENERAL_5_BASE_IDX 1 -#define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4ec1 -#define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 -#define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4ec2 -#define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_CMP_IDLE_CNTL 0x4ec3 -#define mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4ec4 -#define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1 -#define mmRLC_RLCS_AUXILIARY_REG_1 0x4ec5 -#define mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 -#define mmRLC_RLCS_AUXILIARY_REG_2 0x4ec6 -#define mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 -#define mmRLC_RLCS_AUXILIARY_REG_3 0x4ec7 -#define mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 -#define mmRLC_RLCS_AUXILIARY_REG_4 0x4ec8 -#define mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 -#define mmRLC_RLCS_SPM_SQTT_MODE 0x4ee0 -#define mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 -#define mmRLC_RLCS_CP_DMA_SRCID_OVER 0x4ee4 -#define mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 -#define mmRLC_RLCS_UTCL2_CNTL 0x4ee6 -#define mmRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL 0x4ee8 -#define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX 1 -#define mmRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4eec -#define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 -#define mmRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4eed -#define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 -#define mmRLC_RLCS_SMUIO_VIDCHG_CTRL 0x4eee -#define mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX 1 -#define mmRLC_RLCS_EDC_INT_CNTL 0x4eef -#define mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_KMD_LOG_CNTL1 0x4ef1 -#define mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 -#define mmRLC_RLCS_KMD_LOG_CNTL2 0x4ef2 -#define mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 -#define mmRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ef3 -#define mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 -#define mmRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ef4 -#define mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 -#define mmRLC_RLCS_SRM_SRCID_CNTL 0x4efd -#define mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX 1 -#define mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4f03 -#define mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 -#define mmRLC_RLCS_DEC_END 0x4fff -#define mmRLC_RLCS_DEC_END_BASE_IDX 1 - - -// addressBlock: gc_pwrdec -// base address: 0x3c000 -#define mmCGTS_RD_CTRL_REG 0x5004 -#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 -#define mmCGTS_RD_REG 0x5005 -#define mmCGTS_RD_REG_BASE_IDX 1 -#define mmCGTS_TCC_DISABLE 0x5006 -#define mmCGTS_TCC_DISABLE_BASE_IDX 1 -#define mmCGTS_USER_TCC_DISABLE 0x5007 -#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 -#define mmCGTS_STATUS_REG 0x5008 -#define mmCGTS_STATUS_REG_BASE_IDX 1 -#define mmCGTT_SPI_CGTSSM_CLK_CTRL 0x5009 -#define mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SPI_PS_CLK_CTRL 0x507d -#define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SPIS_CLK_CTRL 0x507e -#define mmCGTT_SPIS_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SPI_CLK_CTRL 0x5080 -#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_PC_CLK_CTRL 0x5081 -#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_BCI_CLK_CTRL 0x5082 -#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_VGT_CLK_CTRL 0x5084 -#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_IA_CLK_CTRL 0x5085 -#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_WD_CLK_CTRL 0x5086 -#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_GS_NGG_CLK_CTRL 0x5087 -#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_PA_CLK_CTRL 0x5088 -#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SC_CLK_CTRL0 0x5089 -#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 -#define mmCGTT_SC_CLK_CTRL1 0x508a -#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 -#define mmCGTT_SC_CLK_CTRL2 0x508b -#define mmCGTT_SC_CLK_CTRL2_BASE_IDX 1 -#define mmCGTT_SQ_CLK_CTRL 0x508c -#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SQG_CLK_CTRL 0x508d -#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 -#define mmSQ_ALU_CLK_CTRL 0x508e -#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 -#define mmSQ_TEX_CLK_CTRL 0x508f -#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 -#define mmSQ_LDS_CLK_CTRL 0x5090 -#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_SX_CLK_CTRL0 0x5094 -#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 -#define mmCGTT_SX_CLK_CTRL1 0x5095 -#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 -#define mmCGTT_SX_CLK_CTRL2 0x5096 -#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 -#define mmCGTT_SX_CLK_CTRL3 0x5097 -#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 -#define mmCGTT_SX_CLK_CTRL4 0x5098 -#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 -#define mmTD_CGTT_CTRL 0x509c -#define mmTD_CGTT_CTRL_BASE_IDX 1 -#define mmTA_CGTT_CTRL 0x509d -#define mmTA_CGTT_CTRL_BASE_IDX 1 -#define mmCGTT_TCPI_CLK_CTRL 0x5109 -#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_GDS_CLK_CTRL 0x50a0 -#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 -#define mmDB_CGTT_CLK_CTRL_0 0x50a4 -#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 -#define mmCB_CGTT_SCLK_CTRL 0x50a8 -#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 -#define mmGL2C_CGTT_SCLK_CTRL 0x50fc -#define mmGL2C_CGTT_SCLK_CTRL_BASE_IDX 1 -#define mmGL2A_CGTT_SCLK_CTRL 0x50ac -#define mmGL2A_CGTT_SCLK_CTRL_BASE_IDX 1 -#define mmGL2A_CGTT_SCLK_CTRL_1 0x50ad -#define mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX 1 -#define mmCGTT_CP_CLK_CTRL 0x50b0 -#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_CPF_CLK_CTRL 0x50b1 -#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_CPC_CLK_CTRL 0x50b2 -#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_RLC_CLK_CTRL 0x50b5 -#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 -#define mmRLC_GFX_RM_CNTL 0x50b6 -#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 -#define mmRMI_CGTT_SCLK_CTRL 0x50c0 -#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 -#define mmCGTT_TCPF_CLK_CTRL 0x5111 -#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 -#define mmGCR_CGTT_SCLK_CTRL 0x50c2 -#define mmGCR_CGTT_SCLK_CTRL_BASE_IDX 1 -#define mmUTCL1_CGTT_CLK_CTRL 0x50c3 -#define mmUTCL1_CGTT_CLK_CTRL_BASE_IDX 1 -#define mmGCEA_CGTT_CLK_CTRL 0x50c4 -#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 -#define mmSE_CAC_CGTT_CLK_CTRL 0x50d0 -#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 -#define mmGC_CAC_CGTT_CLK_CTRL 0x50d8 -#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 -#define mmGRBM_CGTT_CLK_CNTL 0x50e0 -#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 1 -#define mmGUS_CGTT_CLK_CTRL 0x50f4 -#define mmGUS_CGTT_CLK_CTRL_BASE_IDX 1 -#define mmCGTT_PH_CLK_CTRL0 0x50f8 -#define mmCGTT_PH_CLK_CTRL0_BASE_IDX 1 -#define mmCGTT_PH_CLK_CTRL1 0x50f9 -#define mmCGTT_PH_CLK_CTRL1_BASE_IDX 1 -#define mmCGTT_PH_CLK_CTRL2 0x50fa -#define mmCGTT_PH_CLK_CTRL2_BASE_IDX 1 -#define mmCGTT_PH_CLK_CTRL3 0x50fb -#define mmCGTT_PH_CLK_CTRL3_BASE_IDX 1 - - -// addressBlock: gc_hypdec -// base address: 0x3e000 -#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 -#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 -#define mmCP_PFP_UCODE_ADDR 0x5814 -#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 -#define mmCP_HYP_PFP_UCODE_DATA 0x5815 -#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 -#define mmCP_PFP_UCODE_DATA 0x5815 -#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 -#define mmCP_HYP_ME_UCODE_ADDR 0x5816 -#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 -#define mmCP_ME_RAM_RADDR 0x5816 -#define mmCP_ME_RAM_RADDR_BASE_IDX 1 -#define mmCP_ME_RAM_WADDR 0x5816 -#define mmCP_ME_RAM_WADDR_BASE_IDX 1 -#define mmCP_HYP_ME_UCODE_DATA 0x5817 -#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 -#define mmCP_ME_RAM_DATA 0x5817 -#define mmCP_ME_RAM_DATA_BASE_IDX 1 -#define mmCP_CE_UCODE_ADDR 0x5818 -#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 -#define mmCP_HYP_CE_UCODE_ADDR 0x5818 -#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 -#define mmCP_CE_UCODE_DATA 0x5819 -#define mmCP_CE_UCODE_DATA_BASE_IDX 1 -#define mmCP_HYP_CE_UCODE_DATA 0x5819 -#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 -#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a -#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 -#define mmCP_MEC_ME1_UCODE_ADDR 0x581a -#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 -#define mmCP_HYP_MEC1_UCODE_DATA 0x581b -#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 -#define mmCP_MEC_ME1_UCODE_DATA 0x581b -#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 -#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c -#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 -#define mmCP_MEC_ME2_UCODE_ADDR 0x581c -#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 -#define mmCP_HYP_MEC2_UCODE_DATA 0x581d -#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 -#define mmCP_MEC_ME2_UCODE_DATA 0x581d -#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 -#define mmCP_PFP_IC_BASE_LO 0x5840 -#define mmCP_PFP_IC_BASE_LO_BASE_IDX 1 -#define mmCP_PFP_IC_BASE_HI 0x5841 -#define mmCP_PFP_IC_BASE_HI_BASE_IDX 1 -#define mmCP_PFP_IC_BASE_CNTL 0x5842 -#define mmCP_PFP_IC_BASE_CNTL_BASE_IDX 1 -#define mmCP_PFP_IC_OP_CNTL 0x5843 -#define mmCP_PFP_IC_OP_CNTL_BASE_IDX 1 -#define mmCP_ME_IC_BASE_LO 0x5844 -#define mmCP_ME_IC_BASE_LO_BASE_IDX 1 -#define mmCP_ME_IC_BASE_HI 0x5845 -#define mmCP_ME_IC_BASE_HI_BASE_IDX 1 -#define mmCP_ME_IC_BASE_CNTL 0x5846 -#define mmCP_ME_IC_BASE_CNTL_BASE_IDX 1 -#define mmCP_ME_IC_OP_CNTL 0x5847 -#define mmCP_ME_IC_OP_CNTL_BASE_IDX 1 -#define mmCP_CE_IC_BASE_LO 0x5848 -#define mmCP_CE_IC_BASE_LO_BASE_IDX 1 -#define mmCP_CE_IC_BASE_HI 0x5849 -#define mmCP_CE_IC_BASE_HI_BASE_IDX 1 -#define mmCP_CE_IC_BASE_CNTL 0x584a -#define mmCP_CE_IC_BASE_CNTL_BASE_IDX 1 -#define mmCP_CE_IC_OP_CNTL 0x584b -#define mmCP_CE_IC_OP_CNTL_BASE_IDX 1 -#define mmCP_CPC_IC_BASE_LO 0x584c -#define mmCP_CPC_IC_BASE_LO_BASE_IDX 1 -#define mmCP_CPC_IC_BASE_HI 0x584d -#define mmCP_CPC_IC_BASE_HI_BASE_IDX 1 -#define mmCP_CPC_IC_BASE_CNTL 0x584e -#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 1 -#define mmCP_CPC_IC_OP_CNTL 0x584f -#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 1 -#define mmCP_MES_IC_BASE_LO 0x5850 -#define mmCP_MES_IC_BASE_LO_BASE_IDX 1 -#define mmCP_MES_MIBASE_LO 0x5850 -#define mmCP_MES_MIBASE_LO_BASE_IDX 1 -#define mmCP_MES_IC_BASE_HI 0x5851 -#define mmCP_MES_IC_BASE_HI_BASE_IDX 1 -#define mmCP_MES_MIBASE_HI 0x5851 -#define mmCP_MES_MIBASE_HI_BASE_IDX 1 -#define mmCP_MES_IC_BASE_CNTL 0x5852 -#define mmCP_MES_IC_BASE_CNTL_BASE_IDX 1 -#define mmCP_MES_DC_BASE_LO 0x5854 -#define mmCP_MES_DC_BASE_LO_BASE_IDX 1 -#define mmCP_MES_MDBASE_LO 0x5854 -#define mmCP_MES_MDBASE_LO_BASE_IDX 1 -#define mmCP_MES_DC_BASE_HI 0x5855 -#define mmCP_MES_DC_BASE_HI_BASE_IDX 1 -#define mmCP_MES_MDBASE_HI 0x5855 -#define mmCP_MES_MDBASE_HI_BASE_IDX 1 -#define mmCP_MES_LOCAL_BASE0_LO 0x5856 -#define mmCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 -#define mmCP_MES_LOCAL_BASE0_HI 0x5857 -#define mmCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 -#define mmCP_MES_LOCAL_MASK0_LO 0x5858 -#define mmCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 -#define mmCP_MES_LOCAL_MASK0_HI 0x5859 -#define mmCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 -#define mmCP_MES_LOCAL_APERTURE 0x585a -#define mmCP_MES_LOCAL_APERTURE_BASE_IDX 1 -#define mmCP_MES_MIBOUND_LO 0x585b -#define mmCP_MES_MIBOUND_LO_BASE_IDX 1 -#define mmCP_MES_MIBOUND_HI 0x585c -#define mmCP_MES_MIBOUND_HI_BASE_IDX 1 -#define mmCP_MES_MDBOUND_LO 0x585d -#define mmCP_MES_MDBOUND_LO_BASE_IDX 1 -#define mmCP_MES_MDBOUND_HI 0x585e -#define mmCP_MES_MDBOUND_HI_BASE_IDX 1 -#define mmGFX_PIPE_PRIORITY 0x587f -#define mmGFX_PIPE_PRIORITY_BASE_IDX 1 -#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 -#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 -#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 -#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 -#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 -#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 -#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 -#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 -#define mmGRBM_CAM_INDEX 0x5a04 -#define mmGRBM_CAM_INDEX_BASE_IDX 1 -#define mmGRBM_HYP_CAM_INDEX 0x5a04 -#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 -#define mmGRBM_CAM_DATA 0x5a05 -#define mmGRBM_CAM_DATA_BASE_IDX 1 -#define mmGRBM_HYP_CAM_DATA 0x5a05 -#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1 -#define mmGRBM_CAM_DATA_UPPER 0x5a06 -#define mmGRBM_CAM_DATA_UPPER_BASE_IDX 1 -#define mmGRBM_HYP_CAM_DATA_UPPER 0x5a06 -#define mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1 -#define mmGC_IH_COOKIE_0_PTR 0x5a07 -#define mmGC_IH_COOKIE_0_PTR_BASE_IDX 1 -#define mmGRBM_SE_REMAP_CNTL 0x5a08 -#define mmGRBM_SE_REMAP_CNTL_BASE_IDX 1 -#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 -#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 -#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 -#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 -#define mmRLC_SDMA0_STATUS 0x5b12 -#define mmRLC_SDMA0_STATUS_BASE_IDX 1 -#define mmRLC_SDMA1_STATUS 0x5b13 -#define mmRLC_SDMA1_STATUS_BASE_IDX 1 -#define mmRLC_SDMA2_STATUS 0x5b14 -#define mmRLC_SDMA2_STATUS_BASE_IDX 1 -#define mmRLC_SDMA3_STATUS 0x5b15 -#define mmRLC_SDMA3_STATUS_BASE_IDX 1 -#define mmRLC_SDMA0_BUSY_STATUS 0x5b16 -#define mmRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_SDMA1_BUSY_STATUS 0x5b17 -#define mmRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_SDMA2_BUSY_STATUS 0x5b18 -#define mmRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_SDMA3_BUSY_STATUS 0x5b19 -#define mmRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 -#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 -#define mmRLC_RLCV_TIMER_INT_0 0x5b25 -#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 -#define mmRLC_RLCV_TIMER_CTRL 0x5b26 -#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 -#define mmRLC_RLCV_TIMER_STAT 0x5b27 -#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 -#define mmRLC_GPU_IOV_VF_MASK 0x5b2d -#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 -#define mmRLC_HYP_SEMAPHORE_0 0x5b2e -#define mmRLC_HYP_SEMAPHORE_0_BASE_IDX 1 -#define mmRLC_HYP_SEMAPHORE_1 0x5b2f -#define mmRLC_HYP_SEMAPHORE_1_BASE_IDX 1 -#define mmRLC_BUSY_CLK_CNTL 0x5b30 -#define mmRLC_BUSY_CLK_CNTL_BASE_IDX 1 -#define mmRLC_CLK_CNTL 0x5b31 -#define mmRLC_CLK_CNTL_BASE_IDX 1 -#define mmRLC_PACE_TIMER_STAT 0x5b33 -#define mmRLC_PACE_TIMER_STAT_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 -#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 -#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 -#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 -#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 -#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 -#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 -#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCH_0 0x5b38 -#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCH_3 0x5b3a -#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCH_1 0x5b3b -#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCH_2 0x5b3c -#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 -#define mmRLC_PACE_INT_FORCE 0x5b3d -#define mmRLC_PACE_INT_FORCE_BASE_IDX 1 -#define mmRLC_PACE_INT_CLEAR 0x5b3e -#define mmRLC_PACE_INT_CLEAR_BASE_IDX 1 -#define mmRLC_GPU_IOV_INT_STAT 0x5b3f -#define mmRLC_GPU_IOV_INT_STAT_BASE_IDX 1 -#define mmRLC_RLCV_TIMER_INT_1 0x5b40 -#define mmRLC_RLCV_TIMER_INT_1_BASE_IDX 1 -#define mmRLC_IH_COOKIE 0x5b41 -#define mmRLC_IH_COOKIE_BASE_IDX 1 -#define mmRLC_IH_COOKIE_CNTL 0x5b42 -#define mmRLC_IH_COOKIE_CNTL_BASE_IDX 1 -#define mmRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 -#define mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 -#define mmRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44 -#define mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1 -#define mmRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45 -#define mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1 -#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 -#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 -#define mmRLC_GPU_IOV_F32_RESET 0x5b47 -#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 -#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a -#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 -#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c -#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 -#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d -#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 -#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e -#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 -#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f -#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 -#define mmRLC_HYP_SEMAPHORE_2 0x5b52 -#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 -#define mmRLC_HYP_SEMAPHORE_3 0x5b53 -#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 -#define mmRLC_HYP_RESET_VECTOR 0x5b54 -#define mmRLC_HYP_RESET_VECTOR_BASE_IDX 1 -#define mmRLC_HYP_BOOTLOAD_SIZE 0x5b5c -#define mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX 1 -#define mmRLC_HYP_BOOTLOAD_ADDR_LO 0x5b5d -#define mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX 1 -#define mmRLC_HYP_BOOTLOAD_ADDR_HI 0x5b5e -#define mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX 1 -#define mmRLC_GPM_IRAM_ADDR 0x5b5f -#define mmRLC_GPM_IRAM_ADDR_BASE_IDX 1 -#define mmRLC_GPM_IRAM_DATA 0x5b60 -#define mmRLC_GPM_IRAM_DATA_BASE_IDX 1 -#define mmRLC_GPM_UCODE_ADDR 0x5b61 -#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 -#define mmRLC_GPM_UCODE_DATA 0x5b62 -#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 -#define mmRLC_PACE_UCODE_ADDR 0x5b63 -#define mmRLC_PACE_UCODE_ADDR_BASE_IDX 1 -#define mmRLC_PACE_UCODE_DATA 0x5b64 -#define mmRLC_PACE_UCODE_DATA_BASE_IDX 1 -#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b65 -#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 -#define mmRLC_GPU_IOV_UCODE_DATA 0x5b66 -#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b67 -#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 -#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b68 -#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 -#define mmRLC_RLCV_IRAM_ADDR 0x5b69 -#define mmRLC_RLCV_IRAM_ADDR_BASE_IDX 1 -#define mmRLC_RLCV_IRAM_DATA 0x5b6a -#define mmRLC_RLCV_IRAM_DATA_BASE_IDX 1 -#define mmRLC_RLCP_IRAM_ADDR 0x5b6b -#define mmRLC_RLCP_IRAM_ADDR_BASE_IDX 1 -#define mmRLC_RLCP_IRAM_DATA 0x5b6c -#define mmRLC_RLCP_IRAM_DATA_BASE_IDX 1 -#define mmRLC_SRM_DRAM_ADDR 0x5b71 -#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 -#define mmRLC_SRM_DRAM_DATA 0x5b72 -#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 -#define mmRLC_SRM_ARAM_ADDR 0x5b73 -#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 -#define mmRLC_SRM_ARAM_DATA 0x5b74 -#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 -#define mmRLC_GPM_SCRATCH_ADDR 0x5b75 -#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 -#define mmRLC_GPM_SCRATCH_DATA 0x5b76 -#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 -#define mmRLC_GTS_OFFSET_LSB 0x5b79 -#define mmRLC_GTS_OFFSET_LSB_BASE_IDX 1 -#define mmRLC_GTS_OFFSET_MSB 0x5b7a -#define mmRLC_GTS_OFFSET_MSB_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 -#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 -#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 -#define mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 -#define mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 -#define mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 -#define mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 -#define mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 -#define mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 -#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 -#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca -#define mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb -#define mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc -#define mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd -#define mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce -#define mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 -#define mmRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf -#define mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma0hypdec -// base address: 0x3e200 -#define mmSDMA0_UCODE_ADDR 0x5880 -#define mmSDMA0_UCODE_ADDR_BASE_IDX 1 -#define mmSDMA0_UCODE_DATA 0x5881 -#define mmSDMA0_UCODE_DATA_BASE_IDX 1 -#define mmSDMA0_VM_CTX_LO 0x5882 -#define mmSDMA0_VM_CTX_LO_BASE_IDX 1 -#define mmSDMA0_VM_CTX_HI 0x5883 -#define mmSDMA0_VM_CTX_HI_BASE_IDX 1 -#define mmSDMA0_ACTIVE_FCN_ID 0x5884 -#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 1 -#define mmSDMA0_VM_CTX_CNTL 0x5885 -#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 1 -#define mmSDMA0_VIRT_RESET_REQ 0x5886 -#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 1 -#define mmSDMA0_VF_ENABLE 0x5887 -#define mmSDMA0_VF_ENABLE_BASE_IDX 1 -#define mmSDMA0_CONTEXT_REG_TYPE0 0x5888 -#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 1 -#define mmSDMA0_CONTEXT_REG_TYPE1 0x5889 -#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 1 -#define mmSDMA0_CONTEXT_REG_TYPE2 0x588a -#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 1 -#define mmSDMA0_CONTEXT_REG_TYPE3 0x588b -#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 1 -#define mmSDMA0_PUB_REG_TYPE0 0x588c -#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 1 -#define mmSDMA0_PUB_REG_TYPE1 0x588d -#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 1 -#define mmSDMA0_PUB_REG_TYPE2 0x588e -#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 1 -#define mmSDMA0_PUB_REG_TYPE3 0x588f -#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 1 -#define mmSDMA0_VM_CNTL 0x5893 -#define mmSDMA0_VM_CNTL_BASE_IDX 1 -#define mmSDMA0_BROADCAST_UCODE_ADDR 0x589c -#define mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1 -#define mmSDMA0_BROADCAST_UCODE_DATA 0x589d -#define mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1 - - -// addressBlock: gc_sdma1_sdma1hypdec -// base address: 0x3e280 -#define mmSDMA1_UCODE_ADDR 0x58a0 -#define mmSDMA1_UCODE_ADDR_BASE_IDX 1 -#define mmSDMA1_UCODE_DATA 0x58a1 -#define mmSDMA1_UCODE_DATA_BASE_IDX 1 -#define mmSDMA1_VM_CTX_LO 0x58a2 -#define mmSDMA1_VM_CTX_LO_BASE_IDX 1 -#define mmSDMA1_VM_CTX_HI 0x58a3 -#define mmSDMA1_VM_CTX_HI_BASE_IDX 1 -#define mmSDMA1_ACTIVE_FCN_ID 0x58a4 -#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 1 -#define mmSDMA1_VM_CTX_CNTL 0x58a5 -#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 1 -#define mmSDMA1_VIRT_RESET_REQ 0x58a6 -#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 1 -#define mmSDMA1_VF_ENABLE 0x58a7 -#define mmSDMA1_VF_ENABLE_BASE_IDX 1 -#define mmSDMA1_CONTEXT_REG_TYPE0 0x58a8 -#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 1 -#define mmSDMA1_CONTEXT_REG_TYPE1 0x58a9 -#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 1 -#define mmSDMA1_CONTEXT_REG_TYPE2 0x58aa -#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 1 -#define mmSDMA1_CONTEXT_REG_TYPE3 0x58ab -#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 1 -#define mmSDMA1_PUB_REG_TYPE0 0x58ac -#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 1 -#define mmSDMA1_PUB_REG_TYPE1 0x58ad -#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 1 -#define mmSDMA1_PUB_REG_TYPE2 0x58ae -#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 1 -#define mmSDMA1_PUB_REG_TYPE3 0x58af -#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 1 -#define mmSDMA1_VM_CNTL 0x58b3 -#define mmSDMA1_VM_CNTL_BASE_IDX 1 - - -// addressBlock: gc_sdma2_sdma2hypdec -// base address: 0x3e300 -#define mmSDMA2_UCODE_ADDR 0x58c0 -#define mmSDMA2_UCODE_ADDR_BASE_IDX 1 -#define mmSDMA2_UCODE_DATA 0x58c1 -#define mmSDMA2_UCODE_DATA_BASE_IDX 1 -#define mmSDMA2_VM_CTX_LO 0x58c2 -#define mmSDMA2_VM_CTX_LO_BASE_IDX 1 -#define mmSDMA2_VM_CTX_HI 0x58c3 -#define mmSDMA2_VM_CTX_HI_BASE_IDX 1 -#define mmSDMA2_ACTIVE_FCN_ID 0x58c4 -#define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX 1 -#define mmSDMA2_VM_CTX_CNTL 0x58c5 -#define mmSDMA2_VM_CTX_CNTL_BASE_IDX 1 -#define mmSDMA2_VIRT_RESET_REQ 0x58c6 -#define mmSDMA2_VIRT_RESET_REQ_BASE_IDX 1 -#define mmSDMA2_VF_ENABLE 0x58c7 -#define mmSDMA2_VF_ENABLE_BASE_IDX 1 -#define mmSDMA2_CONTEXT_REG_TYPE0 0x58c8 -#define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX 1 -#define mmSDMA2_CONTEXT_REG_TYPE1 0x58c9 -#define mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX 1 -#define mmSDMA2_CONTEXT_REG_TYPE2 0x58ca -#define mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX 1 -#define mmSDMA2_CONTEXT_REG_TYPE3 0x58cb -#define mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX 1 -#define mmSDMA2_PUB_REG_TYPE0 0x58cc -#define mmSDMA2_PUB_REG_TYPE0_BASE_IDX 1 -#define mmSDMA2_PUB_REG_TYPE1 0x58cd -#define mmSDMA2_PUB_REG_TYPE1_BASE_IDX 1 -#define mmSDMA2_PUB_REG_TYPE2 0x58ce -#define mmSDMA2_PUB_REG_TYPE2_BASE_IDX 1 -#define mmSDMA2_PUB_REG_TYPE3 0x58cf -#define mmSDMA2_PUB_REG_TYPE3_BASE_IDX 1 -#define mmSDMA2_VM_CNTL 0x58d3 -#define mmSDMA2_VM_CNTL_BASE_IDX 1 - - -// addressBlock: gc_sdma3_sdma3hypdec -// base address: 0x3e380 -#define mmSDMA3_UCODE_ADDR 0x58e0 -#define mmSDMA3_UCODE_ADDR_BASE_IDX 1 -#define mmSDMA3_UCODE_DATA 0x58e1 -#define mmSDMA3_UCODE_DATA_BASE_IDX 1 -#define mmSDMA3_VM_CTX_LO 0x58e2 -#define mmSDMA3_VM_CTX_LO_BASE_IDX 1 -#define mmSDMA3_VM_CTX_HI 0x58e3 -#define mmSDMA3_VM_CTX_HI_BASE_IDX 1 -#define mmSDMA3_ACTIVE_FCN_ID 0x58e4 -#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1 -#define mmSDMA3_VM_CTX_CNTL 0x58e5 -#define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1 -#define mmSDMA3_VIRT_RESET_REQ 0x58e6 -#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1 -#define mmSDMA3_VF_ENABLE 0x58e7 -#define mmSDMA3_VF_ENABLE_BASE_IDX 1 -#define mmSDMA3_CONTEXT_REG_TYPE0 0x58e8 -#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1 -#define mmSDMA3_CONTEXT_REG_TYPE1 0x58e9 -#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX 1 -#define mmSDMA3_CONTEXT_REG_TYPE2 0x58ea -#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX 1 -#define mmSDMA3_CONTEXT_REG_TYPE3 0x58eb -#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX 1 -#define mmSDMA3_PUB_REG_TYPE0 0x58ec -#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX 1 -#define mmSDMA3_PUB_REG_TYPE1 0x58ed -#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX 1 -#define mmSDMA3_PUB_REG_TYPE2 0x58ee -#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX 1 -#define mmSDMA3_PUB_REG_TYPE3 0x58ef -#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX 1 -#define mmSDMA3_VM_CNTL 0x58f3 -#define mmSDMA3_VM_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gcvmsharedhvdec -// base address: 0x3ea00 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a -#define mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b -#define mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c -#define mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d -#define mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e -#define mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f -#define mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF16 0x5a90 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF17 0x5a91 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF18 0x5a92 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF19 0x5a93 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF20 0x5a94 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF21 0x5a95 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF22 0x5a96 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF23 0x5a97 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF24 0x5a98 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF25 0x5a99 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF26 0x5a9a -#define mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF27 0x5a9b -#define mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF28 0x5a9c -#define mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF29 0x5a9d -#define mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF30 0x5a9e -#define mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 1 -#define mmGCMC_VM_FB_SIZE_OFFSET_VF31 0x5a9f -#define mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 1 -#define mmGCVM_IOMMU_MMIO_CNTRL_1 0x5aa0 -#define mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_LO_0 0x5aa1 -#define mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_LO_1 0x5aa2 -#define mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_LO_2 0x5aa3 -#define mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_LO_3 0x5aa4 -#define mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_HI_0 0x5aa5 -#define mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_HI_1 0x5aa6 -#define mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_HI_2 0x5aa7 -#define mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_BASE_HI_3 0x5aa8 -#define mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_LO_0 0x5aa9 -#define mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_LO_1 0x5aaa -#define mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_LO_2 0x5aab -#define mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_LO_3 0x5aac -#define mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_HI_0 0x5aad -#define mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_HI_1 0x5aae -#define mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_HI_2 0x5aaf -#define mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_RELOC_HI_3 0x5ab0 -#define mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_LO_0 0x5ab1 -#define mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_LO_1 0x5ab2 -#define mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_LO_2 0x5ab3 -#define mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_LO_3 0x5ab4 -#define mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_HI_0 0x5ab5 -#define mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_HI_1 0x5ab6 -#define mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_HI_2 0x5ab7 -#define mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1 -#define mmGCMC_VM_MARC_LEN_HI_3 0x5ab8 -#define mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1 -#define mmGCVM_IOMMU_CONTROL_REGISTER 0x5ab9 -#define mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 -#define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aba -#define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 -#define mmGCMC_VM_XGMI_GPUIOV_ENABLE 0x5abb -#define mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 - - -// addressBlock: gc_pspdec -// base address: 0x3f000 -#define mmCPG_PSP_DEBUG 0x5c10 -#define mmCPG_PSP_DEBUG_BASE_IDX 1 -#define mmCPC_PSP_DEBUG 0x5c11 -#define mmCPC_PSP_DEBUG_BASE_IDX 1 -#define mmGRBM_SEC_CNTL 0x5e0d -#define mmGRBM_SEC_CNTL_BASE_IDX 1 -#define mmRLC_FWL_FIRST_VIOL_ADDR 0x5f12 -#define mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 -#define mmRLC_SRM_FWL_FIRST_VIOL_ADDR 0x5f3d -#define mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 - - -// addressBlock: gc_gcvml2pspdec -// base address: 0x3f700 -#define mmGCVM_L2_ID_CTRL0 0x5dc0 -#define mmGCVM_L2_ID_CTRL0_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL1 0x5dc1 -#define mmGCVM_L2_ID_CTRL1_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL2 0x5dc2 -#define mmGCVM_L2_ID_CTRL2_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL3 0x5dc3 -#define mmGCVM_L2_ID_CTRL3_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL4 0x5dc4 -#define mmGCVM_L2_ID_CTRL4_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL5 0x5dc5 -#define mmGCVM_L2_ID_CTRL5_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL6 0x5dc6 -#define mmGCVM_L2_ID_CTRL6_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL7 0x5dc7 -#define mmGCVM_L2_ID_CTRL7_BASE_IDX 1 -#define mmGCVM_L2_ID_CTRL_HI 0x5dc8 -#define mmGCVM_L2_ID_CTRL_HI_BASE_IDX 1 -#define mmGCVM_L2_ID_STATUS 0x5dc9 -#define mmGCVM_L2_ID_STATUS_BASE_IDX 1 -#define mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5dcb -#define mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 -#define mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x5dcd -#define mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 1 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x5dce -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x5dcf -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x5dd0 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x5dd1 -#define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma2_sdma2dec -// base address: 0x70000 -#define mmSDMA2_DEC_START 0x0000 -#define mmSDMA2_DEC_START_BASE_IDX 2 -#define mmSDMA2_GLOBAL_TIMESTAMP_LO 0x000f -#define mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX 2 -#define mmSDMA2_GLOBAL_TIMESTAMP_HI 0x0010 -#define mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX 2 -#define mmSDMA2_PG_CNTL 0x0016 -#define mmSDMA2_PG_CNTL_BASE_IDX 2 -#define mmSDMA2_PG_CTX_LO 0x0017 -#define mmSDMA2_PG_CTX_LO_BASE_IDX 2 -#define mmSDMA2_PG_CTX_HI 0x0018 -#define mmSDMA2_PG_CTX_HI_BASE_IDX 2 -#define mmSDMA2_PG_CTX_CNTL 0x0019 -#define mmSDMA2_PG_CTX_CNTL_BASE_IDX 2 -#define mmSDMA2_POWER_CNTL 0x001a -#define mmSDMA2_POWER_CNTL_BASE_IDX 2 -#define mmSDMA2_CLK_CTRL 0x001b -#define mmSDMA2_CLK_CTRL_BASE_IDX 2 -#define mmSDMA2_CNTL 0x001c -#define mmSDMA2_CNTL_BASE_IDX 2 -#define mmSDMA2_CHICKEN_BITS 0x001d -#define mmSDMA2_CHICKEN_BITS_BASE_IDX 2 -#define mmSDMA2_GB_ADDR_CONFIG 0x001e -#define mmSDMA2_GB_ADDR_CONFIG_BASE_IDX 2 -#define mmSDMA2_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 2 -#define mmSDMA2_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 2 -#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 2 -#define mmSDMA2_RB_RPTR_FETCH 0x0022 -#define mmSDMA2_RB_RPTR_FETCH_BASE_IDX 2 -#define mmSDMA2_IB_OFFSET_FETCH 0x0023 -#define mmSDMA2_IB_OFFSET_FETCH_BASE_IDX 2 -#define mmSDMA2_PROGRAM 0x0024 -#define mmSDMA2_PROGRAM_BASE_IDX 2 -#define mmSDMA2_STATUS_REG 0x0025 -#define mmSDMA2_STATUS_REG_BASE_IDX 2 -#define mmSDMA2_STATUS1_REG 0x0026 -#define mmSDMA2_STATUS1_REG_BASE_IDX 2 -#define mmSDMA2_RD_BURST_CNTL 0x0027 -#define mmSDMA2_RD_BURST_CNTL_BASE_IDX 2 -#define mmSDMA2_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX 2 -#define mmSDMA2_UCODE_CHECKSUM 0x0029 -#define mmSDMA2_UCODE_CHECKSUM_BASE_IDX 2 -#define mmSDMA2_F32_CNTL 0x002a -#define mmSDMA2_F32_CNTL_BASE_IDX 2 -#define mmSDMA2_FREEZE 0x002b -#define mmSDMA2_FREEZE_BASE_IDX 2 -#define mmSDMA2_PHASE0_QUANTUM 0x002c -#define mmSDMA2_PHASE0_QUANTUM_BASE_IDX 2 -#define mmSDMA2_PHASE1_QUANTUM 0x002d -#define mmSDMA2_PHASE1_QUANTUM_BASE_IDX 2 -#define mmSDMA2_EDC_CONFIG 0x0032 -#define mmSDMA2_EDC_CONFIG_BASE_IDX 2 -#define mmSDMA2_BA_THRESHOLD 0x0033 -#define mmSDMA2_BA_THRESHOLD_BASE_IDX 2 -#define mmSDMA2_ID 0x0034 -#define mmSDMA2_ID_BASE_IDX 2 -#define mmSDMA2_VERSION 0x0035 -#define mmSDMA2_VERSION_BASE_IDX 2 -#define mmSDMA2_EDC_COUNTER 0x0036 -#define mmSDMA2_EDC_COUNTER_BASE_IDX 2 -#define mmSDMA2_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX 2 -#define mmSDMA2_STATUS2_REG 0x0038 -#define mmSDMA2_STATUS2_REG_BASE_IDX 2 -#define mmSDMA2_ATOMIC_CNTL 0x0039 -#define mmSDMA2_ATOMIC_CNTL_BASE_IDX 2 -#define mmSDMA2_ATOMIC_PREOP_LO 0x003a -#define mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX 2 -#define mmSDMA2_ATOMIC_PREOP_HI 0x003b -#define mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX 2 -#define mmSDMA2_UTCL1_CNTL 0x003c -#define mmSDMA2_UTCL1_CNTL_BASE_IDX 2 -#define mmSDMA2_UTCL1_WATERMK 0x003d -#define mmSDMA2_UTCL1_WATERMK_BASE_IDX 2 -#define mmSDMA2_UTCL1_RD_STATUS 0x003e -#define mmSDMA2_UTCL1_RD_STATUS_BASE_IDX 2 -#define mmSDMA2_UTCL1_WR_STATUS 0x003f -#define mmSDMA2_UTCL1_WR_STATUS_BASE_IDX 2 -#define mmSDMA2_UTCL1_INV0 0x0040 -#define mmSDMA2_UTCL1_INV0_BASE_IDX 2 -#define mmSDMA2_UTCL1_INV1 0x0041 -#define mmSDMA2_UTCL1_INV1_BASE_IDX 2 -#define mmSDMA2_UTCL1_INV2 0x0042 -#define mmSDMA2_UTCL1_INV2_BASE_IDX 2 -#define mmSDMA2_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX 2 -#define mmSDMA2_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX 2 -#define mmSDMA2_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX 2 -#define mmSDMA2_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX 2 -#define mmSDMA2_UTCL1_TIMEOUT 0x0047 -#define mmSDMA2_UTCL1_TIMEOUT_BASE_IDX 2 -#define mmSDMA2_UTCL1_PAGE 0x0048 -#define mmSDMA2_UTCL1_PAGE_BASE_IDX 2 -#define mmSDMA2_RELAX_ORDERING_LUT 0x004a -#define mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX 2 -#define mmSDMA2_CHICKEN_BITS_2 0x004b -#define mmSDMA2_CHICKEN_BITS_2_BASE_IDX 2 -#define mmSDMA2_STATUS3_REG 0x004c -#define mmSDMA2_STATUS3_REG_BASE_IDX 2 -#define mmSDMA2_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_PHASE2_QUANTUM 0x004f -#define mmSDMA2_PHASE2_QUANTUM_BASE_IDX 2 -#define mmSDMA2_ERROR_LOG 0x0050 -#define mmSDMA2_ERROR_LOG_BASE_IDX 2 -#define mmSDMA2_PUB_DUMMY_REG0 0x0051 -#define mmSDMA2_PUB_DUMMY_REG0_BASE_IDX 2 -#define mmSDMA2_PUB_DUMMY_REG1 0x0052 -#define mmSDMA2_PUB_DUMMY_REG1_BASE_IDX 2 -#define mmSDMA2_PUB_DUMMY_REG2 0x0053 -#define mmSDMA2_PUB_DUMMY_REG2_BASE_IDX 2 -#define mmSDMA2_PUB_DUMMY_REG3 0x0054 -#define mmSDMA2_PUB_DUMMY_REG3_BASE_IDX 2 -#define mmSDMA2_F32_COUNTER 0x0055 -#define mmSDMA2_F32_COUNTER_BASE_IDX 2 -#define mmSDMA2_CRD_CNTL 0x005b -#define mmSDMA2_CRD_CNTL_BASE_IDX 2 -#define mmSDMA2_AQL_STATUS 0x005f -#define mmSDMA2_AQL_STATUS_BASE_IDX 2 -#define mmSDMA2_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 2 -#define mmSDMA2_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 2 -#define mmSDMA2_TLBI_GCR_CNTL 0x0062 -#define mmSDMA2_TLBI_GCR_CNTL_BASE_IDX 2 -#define mmSDMA2_TILING_CONFIG 0x0063 -#define mmSDMA2_TILING_CONFIG_BASE_IDX 2 -#define mmSDMA2_INT_STATUS 0x0070 -#define mmSDMA2_INT_STATUS_BASE_IDX 2 -#define mmSDMA2_HOLE_ADDR_LO 0x0072 -#define mmSDMA2_HOLE_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_HOLE_ADDR_HI 0x0073 -#define mmSDMA2_HOLE_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_CLOCK_GATING_REG 0x0075 -#define mmSDMA2_CLOCK_GATING_REG_BASE_IDX 2 -#define mmSDMA2_STATUS4_REG 0x0076 -#define mmSDMA2_STATUS4_REG_BASE_IDX 2 -#define mmSDMA2_SCRATCH_RAM_DATA 0x0077 -#define mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX 2 -#define mmSDMA2_SCRATCH_RAM_ADDR 0x0078 -#define mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX 2 -#define mmSDMA2_TIMESTAMP_CNTL 0x0079 -#define mmSDMA2_TIMESTAMP_CNTL_BASE_IDX 2 -#define mmSDMA2_STATUS5_REG 0x007a -#define mmSDMA2_STATUS5_REG_BASE_IDX 2 -#define mmSDMA2_QUEUE_RESET_REQ 0x007b -#define mmSDMA2_QUEUE_RESET_REQ_BASE_IDX 2 -#define mmSDMA2_GFX_RB_CNTL 0x0080 -#define mmSDMA2_GFX_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_RB_BASE 0x0081 -#define mmSDMA2_GFX_RB_BASE_BASE_IDX 2 -#define mmSDMA2_GFX_RB_BASE_HI 0x0082 -#define mmSDMA2_GFX_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_GFX_RB_RPTR 0x0083 -#define mmSDMA2_GFX_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_GFX_RB_WPTR 0x0085 -#define mmSDMA2_GFX_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_GFX_IB_CNTL 0x008a -#define mmSDMA2_GFX_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_IB_RPTR 0x008b -#define mmSDMA2_GFX_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_GFX_IB_OFFSET 0x008c -#define mmSDMA2_GFX_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_GFX_IB_BASE_LO 0x008d -#define mmSDMA2_GFX_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_GFX_IB_BASE_HI 0x008e -#define mmSDMA2_GFX_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_GFX_IB_SIZE 0x008f -#define mmSDMA2_GFX_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_GFX_SKIP_CNTL 0x0090 -#define mmSDMA2_GFX_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_GFX_DOORBELL 0x0092 -#define mmSDMA2_GFX_DOORBELL_BASE_IDX 2 -#define mmSDMA2_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_STATUS 0x00a8 -#define mmSDMA2_GFX_STATUS_BASE_IDX 2 -#define mmSDMA2_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_GFX_WATERMARK 0x00aa -#define mmSDMA2_GFX_WATERMARK_BASE_IDX 2 -#define mmSDMA2_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_GFX_PREEMPT 0x00b0 -#define mmSDMA2_GFX_PREEMPT_BASE_IDX 2 -#define mmSDMA2_GFX_DUMMY_REG 0x00b1 -#define mmSDMA2_GFX_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA9 0x00c9 -#define mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_DATA10 0x00ca -#define mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_GFX_MIDCMD_CNTL 0x00cb -#define mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_CNTL 0x00d8 -#define mmSDMA2_PAGE_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_BASE 0x00d9 -#define mmSDMA2_PAGE_RB_BASE_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_BASE_HI 0x00da -#define mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_RPTR 0x00db -#define mmSDMA2_PAGE_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_RPTR_HI 0x00dc -#define mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_WPTR 0x00dd -#define mmSDMA2_PAGE_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_WPTR_HI 0x00de -#define mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x00df -#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI 0x00e0 -#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO 0x00e1 -#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_CNTL 0x00e2 -#define mmSDMA2_PAGE_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_RPTR 0x00e3 -#define mmSDMA2_PAGE_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_OFFSET 0x00e4 -#define mmSDMA2_PAGE_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_BASE_LO 0x00e5 -#define mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_BASE_HI 0x00e6 -#define mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_SIZE 0x00e7 -#define mmSDMA2_PAGE_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_PAGE_SKIP_CNTL 0x00e8 -#define mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_CONTEXT_STATUS 0x00e9 -#define mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_PAGE_DOORBELL 0x00ea -#define mmSDMA2_PAGE_DOORBELL_BASE_IDX 2 -#define mmSDMA2_PAGE_STATUS 0x0100 -#define mmSDMA2_PAGE_STATUS_BASE_IDX 2 -#define mmSDMA2_PAGE_DOORBELL_LOG 0x0101 -#define mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_PAGE_WATERMARK 0x0102 -#define mmSDMA2_PAGE_WATERMARK_BASE_IDX 2 -#define mmSDMA2_PAGE_DOORBELL_OFFSET 0x0103 -#define mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_PAGE_CSA_ADDR_LO 0x0104 -#define mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_PAGE_CSA_ADDR_HI 0x0105 -#define mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_IB_SUB_REMAIN 0x0107 -#define mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_PAGE_PREEMPT 0x0108 -#define mmSDMA2_PAGE_PREEMPT_BASE_IDX 2 -#define mmSDMA2_PAGE_DUMMY_REG 0x0109 -#define mmSDMA2_PAGE_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a -#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b -#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_PAGE_RB_AQL_CNTL 0x010c -#define mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_PAGE_MINOR_PTR_UPDATE 0x010d -#define mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA0 0x0118 -#define mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA1 0x0119 -#define mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA2 0x011a -#define mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA3 0x011b -#define mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA4 0x011c -#define mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA5 0x011d -#define mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA6 0x011e -#define mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA7 0x011f -#define mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA8 0x0120 -#define mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA9 0x0121 -#define mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_DATA10 0x0122 -#define mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_PAGE_MIDCMD_CNTL 0x0123 -#define mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_CNTL 0x0130 -#define mmSDMA2_RLC0_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_BASE 0x0131 -#define mmSDMA2_RLC0_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_BASE_HI 0x0132 -#define mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_RPTR 0x0133 -#define mmSDMA2_RLC0_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_RPTR_HI 0x0134 -#define mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_WPTR 0x0135 -#define mmSDMA2_RLC0_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_WPTR_HI 0x0136 -#define mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x0137 -#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI 0x0138 -#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO 0x0139 -#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_CNTL 0x013a -#define mmSDMA2_RLC0_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_RPTR 0x013b -#define mmSDMA2_RLC0_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_OFFSET 0x013c -#define mmSDMA2_RLC0_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_BASE_LO 0x013d -#define mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_BASE_HI 0x013e -#define mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_SIZE 0x013f -#define mmSDMA2_RLC0_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC0_SKIP_CNTL 0x0140 -#define mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_CONTEXT_STATUS 0x0141 -#define mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC0_DOORBELL 0x0142 -#define mmSDMA2_RLC0_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC0_STATUS 0x0158 -#define mmSDMA2_RLC0_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC0_DOORBELL_LOG 0x0159 -#define mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC0_WATERMARK 0x015a -#define mmSDMA2_RLC0_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC0_DOORBELL_OFFSET 0x015b -#define mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC0_CSA_ADDR_LO 0x015c -#define mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC0_CSA_ADDR_HI 0x015d -#define mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_IB_SUB_REMAIN 0x015f -#define mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC0_PREEMPT 0x0160 -#define mmSDMA2_RLC0_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC0_DUMMY_REG 0x0161 -#define mmSDMA2_RLC0_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 -#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 -#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC0_RB_AQL_CNTL 0x0164 -#define mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC0_MINOR_PTR_UPDATE 0x0165 -#define mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA0 0x0170 -#define mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA1 0x0171 -#define mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA2 0x0172 -#define mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA3 0x0173 -#define mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA4 0x0174 -#define mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA5 0x0175 -#define mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA6 0x0176 -#define mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA7 0x0177 -#define mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA8 0x0178 -#define mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA9 0x0179 -#define mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_DATA10 0x017a -#define mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC0_MIDCMD_CNTL 0x017b -#define mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_CNTL 0x0188 -#define mmSDMA2_RLC1_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_BASE 0x0189 -#define mmSDMA2_RLC1_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_BASE_HI 0x018a -#define mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_RPTR 0x018b -#define mmSDMA2_RLC1_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_RPTR_HI 0x018c -#define mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_WPTR 0x018d -#define mmSDMA2_RLC1_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_WPTR_HI 0x018e -#define mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x018f -#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI 0x0190 -#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO 0x0191 -#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_CNTL 0x0192 -#define mmSDMA2_RLC1_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_RPTR 0x0193 -#define mmSDMA2_RLC1_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_OFFSET 0x0194 -#define mmSDMA2_RLC1_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_BASE_LO 0x0195 -#define mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_BASE_HI 0x0196 -#define mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_SIZE 0x0197 -#define mmSDMA2_RLC1_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC1_SKIP_CNTL 0x0198 -#define mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_CONTEXT_STATUS 0x0199 -#define mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC1_DOORBELL 0x019a -#define mmSDMA2_RLC1_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC1_STATUS 0x01b0 -#define mmSDMA2_RLC1_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC1_DOORBELL_LOG 0x01b1 -#define mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC1_WATERMARK 0x01b2 -#define mmSDMA2_RLC1_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC1_DOORBELL_OFFSET 0x01b3 -#define mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC1_CSA_ADDR_LO 0x01b4 -#define mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC1_CSA_ADDR_HI 0x01b5 -#define mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_IB_SUB_REMAIN 0x01b7 -#define mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC1_PREEMPT 0x01b8 -#define mmSDMA2_RLC1_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC1_DUMMY_REG 0x01b9 -#define mmSDMA2_RLC1_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba -#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb -#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC1_RB_AQL_CNTL 0x01bc -#define mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC1_MINOR_PTR_UPDATE 0x01bd -#define mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA0 0x01c8 -#define mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA1 0x01c9 -#define mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA2 0x01ca -#define mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA3 0x01cb -#define mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA4 0x01cc -#define mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA5 0x01cd -#define mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA6 0x01ce -#define mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA7 0x01cf -#define mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA8 0x01d0 -#define mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA9 0x01d1 -#define mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_DATA10 0x01d2 -#define mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC1_MIDCMD_CNTL 0x01d3 -#define mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_CNTL 0x01e0 -#define mmSDMA2_RLC2_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_BASE 0x01e1 -#define mmSDMA2_RLC2_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_BASE_HI 0x01e2 -#define mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_RPTR 0x01e3 -#define mmSDMA2_RLC2_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_RPTR_HI 0x01e4 -#define mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_WPTR 0x01e5 -#define mmSDMA2_RLC2_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_WPTR_HI 0x01e6 -#define mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x01e7 -#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI 0x01e8 -#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO 0x01e9 -#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_CNTL 0x01ea -#define mmSDMA2_RLC2_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_RPTR 0x01eb -#define mmSDMA2_RLC2_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_OFFSET 0x01ec -#define mmSDMA2_RLC2_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_BASE_LO 0x01ed -#define mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_BASE_HI 0x01ee -#define mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_SIZE 0x01ef -#define mmSDMA2_RLC2_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC2_SKIP_CNTL 0x01f0 -#define mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_CONTEXT_STATUS 0x01f1 -#define mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC2_DOORBELL 0x01f2 -#define mmSDMA2_RLC2_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC2_STATUS 0x0208 -#define mmSDMA2_RLC2_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC2_DOORBELL_LOG 0x0209 -#define mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC2_WATERMARK 0x020a -#define mmSDMA2_RLC2_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC2_DOORBELL_OFFSET 0x020b -#define mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC2_CSA_ADDR_LO 0x020c -#define mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC2_CSA_ADDR_HI 0x020d -#define mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_IB_SUB_REMAIN 0x020f -#define mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC2_PREEMPT 0x0210 -#define mmSDMA2_RLC2_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC2_DUMMY_REG 0x0211 -#define mmSDMA2_RLC2_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 -#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 -#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC2_RB_AQL_CNTL 0x0214 -#define mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC2_MINOR_PTR_UPDATE 0x0215 -#define mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA0 0x0220 -#define mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA1 0x0221 -#define mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA2 0x0222 -#define mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA3 0x0223 -#define mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA4 0x0224 -#define mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA5 0x0225 -#define mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA6 0x0226 -#define mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA7 0x0227 -#define mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA8 0x0228 -#define mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA9 0x0229 -#define mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_DATA10 0x022a -#define mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC2_MIDCMD_CNTL 0x022b -#define mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_CNTL 0x0238 -#define mmSDMA2_RLC3_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_BASE 0x0239 -#define mmSDMA2_RLC3_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_BASE_HI 0x023a -#define mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_RPTR 0x023b -#define mmSDMA2_RLC3_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_RPTR_HI 0x023c -#define mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_WPTR 0x023d -#define mmSDMA2_RLC3_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_WPTR_HI 0x023e -#define mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x023f -#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI 0x0240 -#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO 0x0241 -#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_CNTL 0x0242 -#define mmSDMA2_RLC3_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_RPTR 0x0243 -#define mmSDMA2_RLC3_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_OFFSET 0x0244 -#define mmSDMA2_RLC3_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_BASE_LO 0x0245 -#define mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_BASE_HI 0x0246 -#define mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_SIZE 0x0247 -#define mmSDMA2_RLC3_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC3_SKIP_CNTL 0x0248 -#define mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_CONTEXT_STATUS 0x0249 -#define mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC3_DOORBELL 0x024a -#define mmSDMA2_RLC3_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC3_STATUS 0x0260 -#define mmSDMA2_RLC3_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC3_DOORBELL_LOG 0x0261 -#define mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC3_WATERMARK 0x0262 -#define mmSDMA2_RLC3_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC3_DOORBELL_OFFSET 0x0263 -#define mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC3_CSA_ADDR_LO 0x0264 -#define mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC3_CSA_ADDR_HI 0x0265 -#define mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_IB_SUB_REMAIN 0x0267 -#define mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC3_PREEMPT 0x0268 -#define mmSDMA2_RLC3_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC3_DUMMY_REG 0x0269 -#define mmSDMA2_RLC3_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a -#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b -#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC3_RB_AQL_CNTL 0x026c -#define mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC3_MINOR_PTR_UPDATE 0x026d -#define mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA0 0x0278 -#define mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA1 0x0279 -#define mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA2 0x027a -#define mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA3 0x027b -#define mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA4 0x027c -#define mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA5 0x027d -#define mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA6 0x027e -#define mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA7 0x027f -#define mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA8 0x0280 -#define mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA9 0x0281 -#define mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_DATA10 0x0282 -#define mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC3_MIDCMD_CNTL 0x0283 -#define mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_CNTL 0x0290 -#define mmSDMA2_RLC4_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_BASE 0x0291 -#define mmSDMA2_RLC4_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_BASE_HI 0x0292 -#define mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_RPTR 0x0293 -#define mmSDMA2_RLC4_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_RPTR_HI 0x0294 -#define mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_WPTR 0x0295 -#define mmSDMA2_RLC4_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_WPTR_HI 0x0296 -#define mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x0297 -#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI 0x0298 -#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO 0x0299 -#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_CNTL 0x029a -#define mmSDMA2_RLC4_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_RPTR 0x029b -#define mmSDMA2_RLC4_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_OFFSET 0x029c -#define mmSDMA2_RLC4_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_BASE_LO 0x029d -#define mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_BASE_HI 0x029e -#define mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_SIZE 0x029f -#define mmSDMA2_RLC4_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC4_SKIP_CNTL 0x02a0 -#define mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_CONTEXT_STATUS 0x02a1 -#define mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC4_DOORBELL 0x02a2 -#define mmSDMA2_RLC4_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC4_STATUS 0x02b8 -#define mmSDMA2_RLC4_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC4_DOORBELL_LOG 0x02b9 -#define mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC4_WATERMARK 0x02ba -#define mmSDMA2_RLC4_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC4_DOORBELL_OFFSET 0x02bb -#define mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC4_CSA_ADDR_LO 0x02bc -#define mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC4_CSA_ADDR_HI 0x02bd -#define mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_IB_SUB_REMAIN 0x02bf -#define mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC4_PREEMPT 0x02c0 -#define mmSDMA2_RLC4_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC4_DUMMY_REG 0x02c1 -#define mmSDMA2_RLC4_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 -#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 -#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC4_RB_AQL_CNTL 0x02c4 -#define mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC4_MINOR_PTR_UPDATE 0x02c5 -#define mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA0 0x02d0 -#define mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA1 0x02d1 -#define mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA2 0x02d2 -#define mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA3 0x02d3 -#define mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA4 0x02d4 -#define mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA5 0x02d5 -#define mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA6 0x02d6 -#define mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA7 0x02d7 -#define mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA8 0x02d8 -#define mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA9 0x02d9 -#define mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_DATA10 0x02da -#define mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC4_MIDCMD_CNTL 0x02db -#define mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_CNTL 0x02e8 -#define mmSDMA2_RLC5_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_BASE 0x02e9 -#define mmSDMA2_RLC5_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_BASE_HI 0x02ea -#define mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_RPTR 0x02eb -#define mmSDMA2_RLC5_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_RPTR_HI 0x02ec -#define mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_WPTR 0x02ed -#define mmSDMA2_RLC5_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_WPTR_HI 0x02ee -#define mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x02ef -#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI 0x02f0 -#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO 0x02f1 -#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_CNTL 0x02f2 -#define mmSDMA2_RLC5_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_RPTR 0x02f3 -#define mmSDMA2_RLC5_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_OFFSET 0x02f4 -#define mmSDMA2_RLC5_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_BASE_LO 0x02f5 -#define mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_BASE_HI 0x02f6 -#define mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_SIZE 0x02f7 -#define mmSDMA2_RLC5_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC5_SKIP_CNTL 0x02f8 -#define mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_CONTEXT_STATUS 0x02f9 -#define mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC5_DOORBELL 0x02fa -#define mmSDMA2_RLC5_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC5_STATUS 0x0310 -#define mmSDMA2_RLC5_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC5_DOORBELL_LOG 0x0311 -#define mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC5_WATERMARK 0x0312 -#define mmSDMA2_RLC5_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC5_DOORBELL_OFFSET 0x0313 -#define mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC5_CSA_ADDR_LO 0x0314 -#define mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC5_CSA_ADDR_HI 0x0315 -#define mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_IB_SUB_REMAIN 0x0317 -#define mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC5_PREEMPT 0x0318 -#define mmSDMA2_RLC5_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC5_DUMMY_REG 0x0319 -#define mmSDMA2_RLC5_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a -#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b -#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC5_RB_AQL_CNTL 0x031c -#define mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC5_MINOR_PTR_UPDATE 0x031d -#define mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA0 0x0328 -#define mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA1 0x0329 -#define mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA2 0x032a -#define mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA3 0x032b -#define mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA4 0x032c -#define mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA5 0x032d -#define mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA6 0x032e -#define mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA7 0x032f -#define mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA8 0x0330 -#define mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA9 0x0331 -#define mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_DATA10 0x0332 -#define mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC5_MIDCMD_CNTL 0x0333 -#define mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_CNTL 0x0340 -#define mmSDMA2_RLC6_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_BASE 0x0341 -#define mmSDMA2_RLC6_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_BASE_HI 0x0342 -#define mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_RPTR 0x0343 -#define mmSDMA2_RLC6_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_RPTR_HI 0x0344 -#define mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_WPTR 0x0345 -#define mmSDMA2_RLC6_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_WPTR_HI 0x0346 -#define mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x0347 -#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI 0x0348 -#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO 0x0349 -#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_CNTL 0x034a -#define mmSDMA2_RLC6_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_RPTR 0x034b -#define mmSDMA2_RLC6_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_OFFSET 0x034c -#define mmSDMA2_RLC6_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_BASE_LO 0x034d -#define mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_BASE_HI 0x034e -#define mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_SIZE 0x034f -#define mmSDMA2_RLC6_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC6_SKIP_CNTL 0x0350 -#define mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_CONTEXT_STATUS 0x0351 -#define mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC6_DOORBELL 0x0352 -#define mmSDMA2_RLC6_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC6_STATUS 0x0368 -#define mmSDMA2_RLC6_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC6_DOORBELL_LOG 0x0369 -#define mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC6_WATERMARK 0x036a -#define mmSDMA2_RLC6_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC6_DOORBELL_OFFSET 0x036b -#define mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC6_CSA_ADDR_LO 0x036c -#define mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC6_CSA_ADDR_HI 0x036d -#define mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_IB_SUB_REMAIN 0x036f -#define mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC6_PREEMPT 0x0370 -#define mmSDMA2_RLC6_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC6_DUMMY_REG 0x0371 -#define mmSDMA2_RLC6_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 -#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 -#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC6_RB_AQL_CNTL 0x0374 -#define mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC6_MINOR_PTR_UPDATE 0x0375 -#define mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA0 0x0380 -#define mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA1 0x0381 -#define mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA2 0x0382 -#define mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA3 0x0383 -#define mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA4 0x0384 -#define mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA5 0x0385 -#define mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA6 0x0386 -#define mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA7 0x0387 -#define mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA8 0x0388 -#define mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA9 0x0389 -#define mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_DATA10 0x038a -#define mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC6_MIDCMD_CNTL 0x038b -#define mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_CNTL 0x0398 -#define mmSDMA2_RLC7_RB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_BASE 0x0399 -#define mmSDMA2_RLC7_RB_BASE_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_BASE_HI 0x039a -#define mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_RPTR 0x039b -#define mmSDMA2_RLC7_RB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_RPTR_HI 0x039c -#define mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_WPTR 0x039d -#define mmSDMA2_RLC7_RB_WPTR_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_WPTR_HI 0x039e -#define mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x039f -#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI 0x03a0 -#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO 0x03a1 -#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_CNTL 0x03a2 -#define mmSDMA2_RLC7_IB_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_RPTR 0x03a3 -#define mmSDMA2_RLC7_IB_RPTR_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_OFFSET 0x03a4 -#define mmSDMA2_RLC7_IB_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_BASE_LO 0x03a5 -#define mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_BASE_HI 0x03a6 -#define mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_SIZE 0x03a7 -#define mmSDMA2_RLC7_IB_SIZE_BASE_IDX 2 -#define mmSDMA2_RLC7_SKIP_CNTL 0x03a8 -#define mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_CONTEXT_STATUS 0x03a9 -#define mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC7_DOORBELL 0x03aa -#define mmSDMA2_RLC7_DOORBELL_BASE_IDX 2 -#define mmSDMA2_RLC7_STATUS 0x03c0 -#define mmSDMA2_RLC7_STATUS_BASE_IDX 2 -#define mmSDMA2_RLC7_DOORBELL_LOG 0x03c1 -#define mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA2_RLC7_WATERMARK 0x03c2 -#define mmSDMA2_RLC7_WATERMARK_BASE_IDX 2 -#define mmSDMA2_RLC7_DOORBELL_OFFSET 0x03c3 -#define mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA2_RLC7_CSA_ADDR_LO 0x03c4 -#define mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC7_CSA_ADDR_HI 0x03c5 -#define mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_IB_SUB_REMAIN 0x03c7 -#define mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA2_RLC7_PREEMPT 0x03c8 -#define mmSDMA2_RLC7_PREEMPT_BASE_IDX 2 -#define mmSDMA2_RLC7_DUMMY_REG 0x03c9 -#define mmSDMA2_RLC7_DUMMY_REG_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca -#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb -#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA2_RLC7_RB_AQL_CNTL 0x03cc -#define mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA2_RLC7_MINOR_PTR_UPDATE 0x03cd -#define mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA0 0x03d8 -#define mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA1 0x03d9 -#define mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA2 0x03da -#define mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA3 0x03db -#define mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA4 0x03dc -#define mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA5 0x03dd -#define mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA6 0x03de -#define mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA7 0x03df -#define mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA8 0x03e0 -#define mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA9 0x03e1 -#define mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_DATA10 0x03e2 -#define mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA2_RLC7_MIDCMD_CNTL 0x03e3 -#define mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 2 - - -// addressBlock: gc_sdma3_sdma3dec -// base address: 0x71000 -#define mmSDMA3_DEC_START 0x0400 -#define mmSDMA3_DEC_START_BASE_IDX 2 -#define mmSDMA3_GLOBAL_TIMESTAMP_LO 0x040f -#define mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX 2 -#define mmSDMA3_GLOBAL_TIMESTAMP_HI 0x0410 -#define mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX 2 -#define mmSDMA3_PG_CNTL 0x0416 -#define mmSDMA3_PG_CNTL_BASE_IDX 2 -#define mmSDMA3_PG_CTX_LO 0x0417 -#define mmSDMA3_PG_CTX_LO_BASE_IDX 2 -#define mmSDMA3_PG_CTX_HI 0x0418 -#define mmSDMA3_PG_CTX_HI_BASE_IDX 2 -#define mmSDMA3_PG_CTX_CNTL 0x0419 -#define mmSDMA3_PG_CTX_CNTL_BASE_IDX 2 -#define mmSDMA3_POWER_CNTL 0x041a -#define mmSDMA3_POWER_CNTL_BASE_IDX 2 -#define mmSDMA3_CLK_CTRL 0x041b -#define mmSDMA3_CLK_CTRL_BASE_IDX 2 -#define mmSDMA3_CNTL 0x041c -#define mmSDMA3_CNTL_BASE_IDX 2 -#define mmSDMA3_CHICKEN_BITS 0x041d -#define mmSDMA3_CHICKEN_BITS_BASE_IDX 2 -#define mmSDMA3_GB_ADDR_CONFIG 0x041e -#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX 2 -#define mmSDMA3_GB_ADDR_CONFIG_READ 0x041f -#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 2 -#define mmSDMA3_RB_RPTR_FETCH_HI 0x0420 -#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 2 -#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x0421 -#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 2 -#define mmSDMA3_RB_RPTR_FETCH 0x0422 -#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX 2 -#define mmSDMA3_IB_OFFSET_FETCH 0x0423 -#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX 2 -#define mmSDMA3_PROGRAM 0x0424 -#define mmSDMA3_PROGRAM_BASE_IDX 2 -#define mmSDMA3_STATUS_REG 0x0425 -#define mmSDMA3_STATUS_REG_BASE_IDX 2 -#define mmSDMA3_STATUS1_REG 0x0426 -#define mmSDMA3_STATUS1_REG_BASE_IDX 2 -#define mmSDMA3_RD_BURST_CNTL 0x0427 -#define mmSDMA3_RD_BURST_CNTL_BASE_IDX 2 -#define mmSDMA3_HBM_PAGE_CONFIG 0x0428 -#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX 2 -#define mmSDMA3_UCODE_CHECKSUM 0x0429 -#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX 2 -#define mmSDMA3_F32_CNTL 0x042a -#define mmSDMA3_F32_CNTL_BASE_IDX 2 -#define mmSDMA3_FREEZE 0x042b -#define mmSDMA3_FREEZE_BASE_IDX 2 -#define mmSDMA3_PHASE0_QUANTUM 0x042c -#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX 2 -#define mmSDMA3_PHASE1_QUANTUM 0x042d -#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX 2 -#define mmSDMA3_EDC_CONFIG 0x0432 -#define mmSDMA3_EDC_CONFIG_BASE_IDX 2 -#define mmSDMA3_BA_THRESHOLD 0x0433 -#define mmSDMA3_BA_THRESHOLD_BASE_IDX 2 -#define mmSDMA3_ID 0x0434 -#define mmSDMA3_ID_BASE_IDX 2 -#define mmSDMA3_VERSION 0x0435 -#define mmSDMA3_VERSION_BASE_IDX 2 -#define mmSDMA3_EDC_COUNTER 0x0436 -#define mmSDMA3_EDC_COUNTER_BASE_IDX 2 -#define mmSDMA3_EDC_COUNTER_CLEAR 0x0437 -#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX 2 -#define mmSDMA3_STATUS2_REG 0x0438 -#define mmSDMA3_STATUS2_REG_BASE_IDX 2 -#define mmSDMA3_ATOMIC_CNTL 0x0439 -#define mmSDMA3_ATOMIC_CNTL_BASE_IDX 2 -#define mmSDMA3_ATOMIC_PREOP_LO 0x043a -#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX 2 -#define mmSDMA3_ATOMIC_PREOP_HI 0x043b -#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX 2 -#define mmSDMA3_UTCL1_CNTL 0x043c -#define mmSDMA3_UTCL1_CNTL_BASE_IDX 2 -#define mmSDMA3_UTCL1_WATERMK 0x043d -#define mmSDMA3_UTCL1_WATERMK_BASE_IDX 2 -#define mmSDMA3_UTCL1_RD_STATUS 0x043e -#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX 2 -#define mmSDMA3_UTCL1_WR_STATUS 0x043f -#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX 2 -#define mmSDMA3_UTCL1_INV0 0x0440 -#define mmSDMA3_UTCL1_INV0_BASE_IDX 2 -#define mmSDMA3_UTCL1_INV1 0x0441 -#define mmSDMA3_UTCL1_INV1_BASE_IDX 2 -#define mmSDMA3_UTCL1_INV2 0x0442 -#define mmSDMA3_UTCL1_INV2_BASE_IDX 2 -#define mmSDMA3_UTCL1_RD_XNACK0 0x0443 -#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX 2 -#define mmSDMA3_UTCL1_RD_XNACK1 0x0444 -#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX 2 -#define mmSDMA3_UTCL1_WR_XNACK0 0x0445 -#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX 2 -#define mmSDMA3_UTCL1_WR_XNACK1 0x0446 -#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX 2 -#define mmSDMA3_UTCL1_TIMEOUT 0x0447 -#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX 2 -#define mmSDMA3_UTCL1_PAGE 0x0448 -#define mmSDMA3_UTCL1_PAGE_BASE_IDX 2 -#define mmSDMA3_RELAX_ORDERING_LUT 0x044a -#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX 2 -#define mmSDMA3_CHICKEN_BITS_2 0x044b -#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX 2 -#define mmSDMA3_STATUS3_REG 0x044c -#define mmSDMA3_STATUS3_REG_BASE_IDX 2 -#define mmSDMA3_PHYSICAL_ADDR_LO 0x044d -#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_PHYSICAL_ADDR_HI 0x044e -#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_PHASE2_QUANTUM 0x044f -#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX 2 -#define mmSDMA3_ERROR_LOG 0x0450 -#define mmSDMA3_ERROR_LOG_BASE_IDX 2 -#define mmSDMA3_PUB_DUMMY_REG0 0x0451 -#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX 2 -#define mmSDMA3_PUB_DUMMY_REG1 0x0452 -#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX 2 -#define mmSDMA3_PUB_DUMMY_REG2 0x0453 -#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX 2 -#define mmSDMA3_PUB_DUMMY_REG3 0x0454 -#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX 2 -#define mmSDMA3_F32_COUNTER 0x0455 -#define mmSDMA3_F32_COUNTER_BASE_IDX 2 -#define mmSDMA3_CRD_CNTL 0x045b -#define mmSDMA3_CRD_CNTL_BASE_IDX 2 -#define mmSDMA3_AQL_STATUS 0x045f -#define mmSDMA3_AQL_STATUS_BASE_IDX 2 -#define mmSDMA3_EA_DBIT_ADDR_DATA 0x0460 -#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 2 -#define mmSDMA3_EA_DBIT_ADDR_INDEX 0x0461 -#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 2 -#define mmSDMA3_TLBI_GCR_CNTL 0x0462 -#define mmSDMA3_TLBI_GCR_CNTL_BASE_IDX 2 -#define mmSDMA3_TILING_CONFIG 0x0463 -#define mmSDMA3_TILING_CONFIG_BASE_IDX 2 -#define mmSDMA3_INT_STATUS 0x0470 -#define mmSDMA3_INT_STATUS_BASE_IDX 2 -#define mmSDMA3_HOLE_ADDR_LO 0x0472 -#define mmSDMA3_HOLE_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_HOLE_ADDR_HI 0x0473 -#define mmSDMA3_HOLE_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_CLOCK_GATING_REG 0x0475 -#define mmSDMA3_CLOCK_GATING_REG_BASE_IDX 2 -#define mmSDMA3_STATUS4_REG 0x0476 -#define mmSDMA3_STATUS4_REG_BASE_IDX 2 -#define mmSDMA3_SCRATCH_RAM_DATA 0x0477 -#define mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX 2 -#define mmSDMA3_SCRATCH_RAM_ADDR 0x0478 -#define mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX 2 -#define mmSDMA3_TIMESTAMP_CNTL 0x0479 -#define mmSDMA3_TIMESTAMP_CNTL_BASE_IDX 2 -#define mmSDMA3_STATUS5_REG 0x047a -#define mmSDMA3_STATUS5_REG_BASE_IDX 2 -#define mmSDMA3_QUEUE_RESET_REQ 0x047b -#define mmSDMA3_QUEUE_RESET_REQ_BASE_IDX 2 -#define mmSDMA3_GFX_RB_CNTL 0x0480 -#define mmSDMA3_GFX_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_RB_BASE 0x0481 -#define mmSDMA3_GFX_RB_BASE_BASE_IDX 2 -#define mmSDMA3_GFX_RB_BASE_HI 0x0482 -#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_GFX_RB_RPTR 0x0483 -#define mmSDMA3_GFX_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_GFX_RB_RPTR_HI 0x0484 -#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_GFX_RB_WPTR 0x0485 -#define mmSDMA3_GFX_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_GFX_RB_WPTR_HI 0x0486 -#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0x0487 -#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_RB_RPTR_ADDR_HI 0x0488 -#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_GFX_RB_RPTR_ADDR_LO 0x0489 -#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_GFX_IB_CNTL 0x048a -#define mmSDMA3_GFX_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_IB_RPTR 0x048b -#define mmSDMA3_GFX_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_GFX_IB_OFFSET 0x048c -#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_GFX_IB_BASE_LO 0x048d -#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_GFX_IB_BASE_HI 0x048e -#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_GFX_IB_SIZE 0x048f -#define mmSDMA3_GFX_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_GFX_SKIP_CNTL 0x0490 -#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_CONTEXT_STATUS 0x0491 -#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_GFX_DOORBELL 0x0492 -#define mmSDMA3_GFX_DOORBELL_BASE_IDX 2 -#define mmSDMA3_GFX_CONTEXT_CNTL 0x0493 -#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_STATUS 0x04a8 -#define mmSDMA3_GFX_STATUS_BASE_IDX 2 -#define mmSDMA3_GFX_DOORBELL_LOG 0x04a9 -#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_GFX_WATERMARK 0x04aa -#define mmSDMA3_GFX_WATERMARK_BASE_IDX 2 -#define mmSDMA3_GFX_DOORBELL_OFFSET 0x04ab -#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_GFX_CSA_ADDR_LO 0x04ac -#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_GFX_CSA_ADDR_HI 0x04ad -#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_GFX_IB_SUB_REMAIN 0x04af -#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_GFX_PREEMPT 0x04b0 -#define mmSDMA3_GFX_PREEMPT_BASE_IDX 2 -#define mmSDMA3_GFX_DUMMY_REG 0x04b1 -#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x04b2 -#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x04b3 -#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_GFX_RB_AQL_CNTL 0x04b4 -#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_GFX_MINOR_PTR_UPDATE 0x04b5 -#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA0 0x04c0 -#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA1 0x04c1 -#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA2 0x04c2 -#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA3 0x04c3 -#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA4 0x04c4 -#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA5 0x04c5 -#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA6 0x04c6 -#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA7 0x04c7 -#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA8 0x04c8 -#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA9 0x04c9 -#define mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_DATA10 0x04ca -#define mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_GFX_MIDCMD_CNTL 0x04cb -#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_CNTL 0x04d8 -#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_BASE 0x04d9 -#define mmSDMA3_PAGE_RB_BASE_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_BASE_HI 0x04da -#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_RPTR 0x04db -#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_RPTR_HI 0x04dc -#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_WPTR 0x04dd -#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_WPTR_HI 0x04de -#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x04df -#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0x04e0 -#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0x04e1 -#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_CNTL 0x04e2 -#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_RPTR 0x04e3 -#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_OFFSET 0x04e4 -#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_BASE_LO 0x04e5 -#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_BASE_HI 0x04e6 -#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_SIZE 0x04e7 -#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_PAGE_SKIP_CNTL 0x04e8 -#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_CONTEXT_STATUS 0x04e9 -#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_PAGE_DOORBELL 0x04ea -#define mmSDMA3_PAGE_DOORBELL_BASE_IDX 2 -#define mmSDMA3_PAGE_STATUS 0x0500 -#define mmSDMA3_PAGE_STATUS_BASE_IDX 2 -#define mmSDMA3_PAGE_DOORBELL_LOG 0x0501 -#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_PAGE_WATERMARK 0x0502 -#define mmSDMA3_PAGE_WATERMARK_BASE_IDX 2 -#define mmSDMA3_PAGE_DOORBELL_OFFSET 0x0503 -#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_PAGE_CSA_ADDR_LO 0x0504 -#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_PAGE_CSA_ADDR_HI 0x0505 -#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_IB_SUB_REMAIN 0x0507 -#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_PAGE_PREEMPT 0x0508 -#define mmSDMA3_PAGE_PREEMPT_BASE_IDX 2 -#define mmSDMA3_PAGE_DUMMY_REG 0x0509 -#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x050a -#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x050b -#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_PAGE_RB_AQL_CNTL 0x050c -#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_PAGE_MINOR_PTR_UPDATE 0x050d -#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA0 0x0518 -#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA1 0x0519 -#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA2 0x051a -#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA3 0x051b -#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA4 0x051c -#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA5 0x051d -#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA6 0x051e -#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA7 0x051f -#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA8 0x0520 -#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA9 0x0521 -#define mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_DATA10 0x0522 -#define mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_PAGE_MIDCMD_CNTL 0x0523 -#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_CNTL 0x0530 -#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_BASE 0x0531 -#define mmSDMA3_RLC0_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_BASE_HI 0x0532 -#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_RPTR 0x0533 -#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_RPTR_HI 0x0534 -#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_WPTR 0x0535 -#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_WPTR_HI 0x0536 -#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x0537 -#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0x0538 -#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0x0539 -#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_CNTL 0x053a -#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_RPTR 0x053b -#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_OFFSET 0x053c -#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_BASE_LO 0x053d -#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_BASE_HI 0x053e -#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_SIZE 0x053f -#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC0_SKIP_CNTL 0x0540 -#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_CONTEXT_STATUS 0x0541 -#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC0_DOORBELL 0x0542 -#define mmSDMA3_RLC0_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC0_STATUS 0x0558 -#define mmSDMA3_RLC0_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC0_DOORBELL_LOG 0x0559 -#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC0_WATERMARK 0x055a -#define mmSDMA3_RLC0_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC0_DOORBELL_OFFSET 0x055b -#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC0_CSA_ADDR_LO 0x055c -#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC0_CSA_ADDR_HI 0x055d -#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_IB_SUB_REMAIN 0x055f -#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC0_PREEMPT 0x0560 -#define mmSDMA3_RLC0_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC0_DUMMY_REG 0x0561 -#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x0562 -#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x0563 -#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC0_RB_AQL_CNTL 0x0564 -#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC0_MINOR_PTR_UPDATE 0x0565 -#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA0 0x0570 -#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA1 0x0571 -#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA2 0x0572 -#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA3 0x0573 -#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA4 0x0574 -#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA5 0x0575 -#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA6 0x0576 -#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA7 0x0577 -#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA8 0x0578 -#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA9 0x0579 -#define mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_DATA10 0x057a -#define mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC0_MIDCMD_CNTL 0x057b -#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_CNTL 0x0588 -#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_BASE 0x0589 -#define mmSDMA3_RLC1_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_BASE_HI 0x058a -#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_RPTR 0x058b -#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_RPTR_HI 0x058c -#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_WPTR 0x058d -#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_WPTR_HI 0x058e -#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x058f -#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0x0590 -#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0x0591 -#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_CNTL 0x0592 -#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_RPTR 0x0593 -#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_OFFSET 0x0594 -#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_BASE_LO 0x0595 -#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_BASE_HI 0x0596 -#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_SIZE 0x0597 -#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC1_SKIP_CNTL 0x0598 -#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_CONTEXT_STATUS 0x0599 -#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC1_DOORBELL 0x059a -#define mmSDMA3_RLC1_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC1_STATUS 0x05b0 -#define mmSDMA3_RLC1_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC1_DOORBELL_LOG 0x05b1 -#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC1_WATERMARK 0x05b2 -#define mmSDMA3_RLC1_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC1_DOORBELL_OFFSET 0x05b3 -#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC1_CSA_ADDR_LO 0x05b4 -#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC1_CSA_ADDR_HI 0x05b5 -#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_IB_SUB_REMAIN 0x05b7 -#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC1_PREEMPT 0x05b8 -#define mmSDMA3_RLC1_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC1_DUMMY_REG 0x05b9 -#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x05ba -#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x05bb -#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC1_RB_AQL_CNTL 0x05bc -#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC1_MINOR_PTR_UPDATE 0x05bd -#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA0 0x05c8 -#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA1 0x05c9 -#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA2 0x05ca -#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA3 0x05cb -#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA4 0x05cc -#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA5 0x05cd -#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA6 0x05ce -#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA7 0x05cf -#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA8 0x05d0 -#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA9 0x05d1 -#define mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_DATA10 0x05d2 -#define mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC1_MIDCMD_CNTL 0x05d3 -#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_CNTL 0x05e0 -#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_BASE 0x05e1 -#define mmSDMA3_RLC2_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_BASE_HI 0x05e2 -#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_RPTR 0x05e3 -#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_RPTR_HI 0x05e4 -#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_WPTR 0x05e5 -#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_WPTR_HI 0x05e6 -#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x05e7 -#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0x05e8 -#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0x05e9 -#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_CNTL 0x05ea -#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_RPTR 0x05eb -#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_OFFSET 0x05ec -#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_BASE_LO 0x05ed -#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_BASE_HI 0x05ee -#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_SIZE 0x05ef -#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC2_SKIP_CNTL 0x05f0 -#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_CONTEXT_STATUS 0x05f1 -#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC2_DOORBELL 0x05f2 -#define mmSDMA3_RLC2_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC2_STATUS 0x0608 -#define mmSDMA3_RLC2_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC2_DOORBELL_LOG 0x0609 -#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC2_WATERMARK 0x060a -#define mmSDMA3_RLC2_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC2_DOORBELL_OFFSET 0x060b -#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC2_CSA_ADDR_LO 0x060c -#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC2_CSA_ADDR_HI 0x060d -#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_IB_SUB_REMAIN 0x060f -#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC2_PREEMPT 0x0610 -#define mmSDMA3_RLC2_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC2_DUMMY_REG 0x0611 -#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x0612 -#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x0613 -#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC2_RB_AQL_CNTL 0x0614 -#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC2_MINOR_PTR_UPDATE 0x0615 -#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA0 0x0620 -#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA1 0x0621 -#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA2 0x0622 -#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA3 0x0623 -#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA4 0x0624 -#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA5 0x0625 -#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA6 0x0626 -#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA7 0x0627 -#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA8 0x0628 -#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA9 0x0629 -#define mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_DATA10 0x062a -#define mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC2_MIDCMD_CNTL 0x062b -#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_CNTL 0x0638 -#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_BASE 0x0639 -#define mmSDMA3_RLC3_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_BASE_HI 0x063a -#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_RPTR 0x063b -#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_RPTR_HI 0x063c -#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_WPTR 0x063d -#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_WPTR_HI 0x063e -#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x063f -#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0x0640 -#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0x0641 -#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_CNTL 0x0642 -#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_RPTR 0x0643 -#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_OFFSET 0x0644 -#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_BASE_LO 0x0645 -#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_BASE_HI 0x0646 -#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_SIZE 0x0647 -#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC3_SKIP_CNTL 0x0648 -#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_CONTEXT_STATUS 0x0649 -#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC3_DOORBELL 0x064a -#define mmSDMA3_RLC3_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC3_STATUS 0x0660 -#define mmSDMA3_RLC3_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC3_DOORBELL_LOG 0x0661 -#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC3_WATERMARK 0x0662 -#define mmSDMA3_RLC3_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC3_DOORBELL_OFFSET 0x0663 -#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC3_CSA_ADDR_LO 0x0664 -#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC3_CSA_ADDR_HI 0x0665 -#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_IB_SUB_REMAIN 0x0667 -#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC3_PREEMPT 0x0668 -#define mmSDMA3_RLC3_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC3_DUMMY_REG 0x0669 -#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x066a -#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x066b -#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC3_RB_AQL_CNTL 0x066c -#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC3_MINOR_PTR_UPDATE 0x066d -#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA0 0x0678 -#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA1 0x0679 -#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA2 0x067a -#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA3 0x067b -#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA4 0x067c -#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA5 0x067d -#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA6 0x067e -#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA7 0x067f -#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA8 0x0680 -#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA9 0x0681 -#define mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_DATA10 0x0682 -#define mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC3_MIDCMD_CNTL 0x0683 -#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_CNTL 0x0690 -#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_BASE 0x0691 -#define mmSDMA3_RLC4_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_BASE_HI 0x0692 -#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_RPTR 0x0693 -#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_RPTR_HI 0x0694 -#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_WPTR 0x0695 -#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_WPTR_HI 0x0696 -#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x0697 -#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0x0698 -#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0x0699 -#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_CNTL 0x069a -#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_RPTR 0x069b -#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_OFFSET 0x069c -#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_BASE_LO 0x069d -#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_BASE_HI 0x069e -#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_SIZE 0x069f -#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC4_SKIP_CNTL 0x06a0 -#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_CONTEXT_STATUS 0x06a1 -#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC4_DOORBELL 0x06a2 -#define mmSDMA3_RLC4_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC4_STATUS 0x06b8 -#define mmSDMA3_RLC4_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC4_DOORBELL_LOG 0x06b9 -#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC4_WATERMARK 0x06ba -#define mmSDMA3_RLC4_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC4_DOORBELL_OFFSET 0x06bb -#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC4_CSA_ADDR_LO 0x06bc -#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC4_CSA_ADDR_HI 0x06bd -#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_IB_SUB_REMAIN 0x06bf -#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC4_PREEMPT 0x06c0 -#define mmSDMA3_RLC4_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC4_DUMMY_REG 0x06c1 -#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x06c2 -#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x06c3 -#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC4_RB_AQL_CNTL 0x06c4 -#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC4_MINOR_PTR_UPDATE 0x06c5 -#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA0 0x06d0 -#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA1 0x06d1 -#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA2 0x06d2 -#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA3 0x06d3 -#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA4 0x06d4 -#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA5 0x06d5 -#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA6 0x06d6 -#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA7 0x06d7 -#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA8 0x06d8 -#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA9 0x06d9 -#define mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_DATA10 0x06da -#define mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC4_MIDCMD_CNTL 0x06db -#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_CNTL 0x06e8 -#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_BASE 0x06e9 -#define mmSDMA3_RLC5_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_BASE_HI 0x06ea -#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_RPTR 0x06eb -#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_RPTR_HI 0x06ec -#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_WPTR 0x06ed -#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_WPTR_HI 0x06ee -#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x06ef -#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0x06f0 -#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0x06f1 -#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_CNTL 0x06f2 -#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_RPTR 0x06f3 -#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_OFFSET 0x06f4 -#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_BASE_LO 0x06f5 -#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_BASE_HI 0x06f6 -#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_SIZE 0x06f7 -#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC5_SKIP_CNTL 0x06f8 -#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_CONTEXT_STATUS 0x06f9 -#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC5_DOORBELL 0x06fa -#define mmSDMA3_RLC5_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC5_STATUS 0x0710 -#define mmSDMA3_RLC5_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC5_DOORBELL_LOG 0x0711 -#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC5_WATERMARK 0x0712 -#define mmSDMA3_RLC5_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC5_DOORBELL_OFFSET 0x0713 -#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC5_CSA_ADDR_LO 0x0714 -#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC5_CSA_ADDR_HI 0x0715 -#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_IB_SUB_REMAIN 0x0717 -#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC5_PREEMPT 0x0718 -#define mmSDMA3_RLC5_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC5_DUMMY_REG 0x0719 -#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x071a -#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x071b -#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC5_RB_AQL_CNTL 0x071c -#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC5_MINOR_PTR_UPDATE 0x071d -#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA0 0x0728 -#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA1 0x0729 -#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA2 0x072a -#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA3 0x072b -#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA4 0x072c -#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA5 0x072d -#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA6 0x072e -#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA7 0x072f -#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA8 0x0730 -#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA9 0x0731 -#define mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_DATA10 0x0732 -#define mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC5_MIDCMD_CNTL 0x0733 -#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_CNTL 0x0740 -#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_BASE 0x0741 -#define mmSDMA3_RLC6_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_BASE_HI 0x0742 -#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_RPTR 0x0743 -#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_RPTR_HI 0x0744 -#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_WPTR 0x0745 -#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_WPTR_HI 0x0746 -#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x0747 -#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0x0748 -#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0x0749 -#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_CNTL 0x074a -#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_RPTR 0x074b -#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_OFFSET 0x074c -#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_BASE_LO 0x074d -#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_BASE_HI 0x074e -#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_SIZE 0x074f -#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC6_SKIP_CNTL 0x0750 -#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_CONTEXT_STATUS 0x0751 -#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC6_DOORBELL 0x0752 -#define mmSDMA3_RLC6_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC6_STATUS 0x0768 -#define mmSDMA3_RLC6_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC6_DOORBELL_LOG 0x0769 -#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC6_WATERMARK 0x076a -#define mmSDMA3_RLC6_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC6_DOORBELL_OFFSET 0x076b -#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC6_CSA_ADDR_LO 0x076c -#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC6_CSA_ADDR_HI 0x076d -#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_IB_SUB_REMAIN 0x076f -#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC6_PREEMPT 0x0770 -#define mmSDMA3_RLC6_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC6_DUMMY_REG 0x0771 -#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x0772 -#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x0773 -#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC6_RB_AQL_CNTL 0x0774 -#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC6_MINOR_PTR_UPDATE 0x0775 -#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA0 0x0780 -#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA1 0x0781 -#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA2 0x0782 -#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA3 0x0783 -#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA4 0x0784 -#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA5 0x0785 -#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA6 0x0786 -#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA7 0x0787 -#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA8 0x0788 -#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA9 0x0789 -#define mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_DATA10 0x078a -#define mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC6_MIDCMD_CNTL 0x078b -#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_CNTL 0x0798 -#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_BASE 0x0799 -#define mmSDMA3_RLC7_RB_BASE_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_BASE_HI 0x079a -#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_RPTR 0x079b -#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_RPTR_HI 0x079c -#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_WPTR 0x079d -#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_WPTR_HI 0x079e -#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x079f -#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0x07a0 -#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0x07a1 -#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_CNTL 0x07a2 -#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_RPTR 0x07a3 -#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_OFFSET 0x07a4 -#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_BASE_LO 0x07a5 -#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_BASE_HI 0x07a6 -#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_SIZE 0x07a7 -#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX 2 -#define mmSDMA3_RLC7_SKIP_CNTL 0x07a8 -#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_CONTEXT_STATUS 0x07a9 -#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC7_DOORBELL 0x07aa -#define mmSDMA3_RLC7_DOORBELL_BASE_IDX 2 -#define mmSDMA3_RLC7_STATUS 0x07c0 -#define mmSDMA3_RLC7_STATUS_BASE_IDX 2 -#define mmSDMA3_RLC7_DOORBELL_LOG 0x07c1 -#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 2 -#define mmSDMA3_RLC7_WATERMARK 0x07c2 -#define mmSDMA3_RLC7_WATERMARK_BASE_IDX 2 -#define mmSDMA3_RLC7_DOORBELL_OFFSET 0x07c3 -#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 2 -#define mmSDMA3_RLC7_CSA_ADDR_LO 0x07c4 -#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC7_CSA_ADDR_HI 0x07c5 -#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_IB_SUB_REMAIN 0x07c7 -#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 2 -#define mmSDMA3_RLC7_PREEMPT 0x07c8 -#define mmSDMA3_RLC7_PREEMPT_BASE_IDX 2 -#define mmSDMA3_RLC7_DUMMY_REG 0x07c9 -#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x07ca -#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x07cb -#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 2 -#define mmSDMA3_RLC7_RB_AQL_CNTL 0x07cc -#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 2 -#define mmSDMA3_RLC7_MINOR_PTR_UPDATE 0x07cd -#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA0 0x07d8 -#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA1 0x07d9 -#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA2 0x07da -#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA3 0x07db -#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA4 0x07dc -#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA5 0x07dd -#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA6 0x07de -#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA7 0x07df -#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA8 0x07e0 -#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA9 0x07e1 -#define mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_DATA10 0x07e2 -#define mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX 2 -#define mmSDMA3_RLC7_MIDCMD_CNTL 0x07e3 -#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 2 - - -// addressBlock: gccacind -// base address: 0x0 -#define ixPCC_STALL_PATTERN_CTRL 0x0000 -#define ixPWRBRK_STALL_PATTERN_CTRL 0x0001 -#define ixPCC_STALL_PATTERN_1_2 0x0006 -#define ixPCC_STALL_PATTERN_3_4 0x0007 -#define ixPCC_STALL_PATTERN_5_6 0x0008 -#define ixPCC_STALL_PATTERN_7 0x0009 -#define ixPWRBRK_STALL_PATTERN_1_2 0x000a -#define ixPWRBRK_STALL_PATTERN_3_4 0x000b -#define ixPWRBRK_STALL_PATTERN_5_6 0x000c -#define ixPWRBRK_STALL_PATTERN_7 0x000d -#define ixPCC_PWRBRK_HYSTERESIS_CTRL 0x000e -#define ixEDC_STRETCH_PERF_COUNTER 0x000f -#define ixEDC_UNSTRETCH_PERF_COUNTER 0x0010 -#define ixEDC_STRETCH_NUM_PERF_COUNTER 0x0011 -#define ixGC_CAC_ID 0x0020 -#define ixGC_CAC_CNTL 0x0021 -#define ixGC_CAC_OVR_SEL 0x0022 -#define ixGC_CAC_OVR_VAL 0x0023 -#define ixGC_CAC_WEIGHT_BCI_0 0x0024 -#define ixGC_CAC_WEIGHT_CB_0 0x0025 -#define ixGC_CAC_WEIGHT_CB_1 0x0026 -#define ixGC_CAC_WEIGHT_CB_2 0x0027 -#define ixGC_CAC_WEIGHT_CB_3 0x0028 -#define ixGC_CAC_WEIGHT_CB_4 0x0029 -#define ixGC_CAC_WEIGHT_CP_0 0x002a -#define ixGC_CAC_WEIGHT_CP_1 0x002b -#define ixGC_CAC_WEIGHT_DB_0 0x002c -#define ixGC_CAC_WEIGHT_DB_1 0x002d -#define ixGC_CAC_WEIGHT_DB_2 0x002e -#define ixGC_CAC_WEIGHT_DB_3 0x002f -#define ixGC_CAC_WEIGHT_DB_4 0x0030 -#define ixGC_CAC_WEIGHT_GDS_0 0x0031 -#define ixGC_CAC_WEIGHT_GDS_1 0x0032 -#define ixGC_CAC_WEIGHT_GDS_2 0x0033 -#define ixGC_CAC_WEIGHT_LDS_0 0x0034 -#define ixGC_CAC_WEIGHT_LDS_1 0x0035 -#define ixGC_CAC_WEIGHT_LDS_2 0x0036 -#define ixGC_CAC_WEIGHT_LDS_3 0x0037 -#define ixGC_CAC_WEIGHT_LDS_4 0x0038 -#define ixGC_CAC_WEIGHT_PA_0 0x0039 -#define ixGC_CAC_WEIGHT_PA_1 0x003a -#define ixGC_CAC_WEIGHT_PA_2 0x003b -#define ixGC_CAC_WEIGHT_PA_3 0x003c -#define ixGC_CAC_WEIGHT_PC_0 0x003d -#define ixGC_CAC_WEIGHT_SC_0 0x003e -#define ixGC_CAC_WEIGHT_SC_1 0x003f -#define ixGC_CAC_WEIGHT_SC_2 0x0040 -#define ixGC_CAC_WEIGHT_SC_3 0x0041 -#define ixGC_CAC_WEIGHT_SPI_0 0x0042 -#define ixGC_CAC_WEIGHT_SPI_1 0x0043 -#define ixGC_CAC_WEIGHT_SPI_2 0x0044 -#define ixGC_CAC_WEIGHT_SQ_0 0x0045 -#define ixGC_CAC_WEIGHT_SQ_1 0x0046 -#define ixGC_CAC_WEIGHT_SQ_2 0x0047 -#define ixGC_CAC_WEIGHT_SQ_3 0x0048 -#define ixGC_CAC_WEIGHT_SX_0 0x0049 -#define ixGC_CAC_WEIGHT_SXRB_0 0x004a -#define ixGC_CAC_WEIGHT_TA_0 0x004b -#define ixGC_CAC_WEIGHT_TCP_0 0x004c -#define ixGC_CAC_WEIGHT_TCP_1 0x004d -#define ixGC_CAC_WEIGHT_TCP_2 0x004e -#define ixGC_CAC_WEIGHT_TCP_3 0x004f -#define ixGC_CAC_WEIGHT_TD_0 0x0050 -#define ixGC_CAC_WEIGHT_TD_1 0x0051 -#define ixGC_CAC_WEIGHT_TD_2 0x0052 -#define ixGC_CAC_WEIGHT_TD_3 0x0053 -#define ixGC_CAC_WEIGHT_TD_4 0x0054 -#define ixGC_CAC_WEIGHT_TD_5 0x0055 -#define ixGC_CAC_WEIGHT_RMI_0 0x0056 -#define ixGC_CAC_WEIGHT_RMI_1 0x0057 -#define ixGC_CAC_WEIGHT_EA_0 0x0058 -#define ixGC_CAC_WEIGHT_EA_1 0x0059 -#define ixGC_CAC_WEIGHT_EA_2 0x005a -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x005b -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x005c -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x005d -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x005e -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x005f -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0060 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0061 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0062 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0063 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0064 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0065 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x0066 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x0067 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x0068 -#define ixGC_CAC_WEIGHT_CU_0 0x0069 -#define ixGC_CAC_WEIGHT_UTCL1_0 0x006a -#define ixGC_CAC_WEIGHT_GE_0 0x006b -#define ixGC_CAC_WEIGHT_GE_1 0x006c -#define ixGC_CAC_WEIGHT_GE_2 0x006d -#define ixGC_CAC_WEIGHT_GE_3 0x006e -#define ixGC_CAC_WEIGHT_GE_4 0x006f -#define ixGC_CAC_WEIGHT_GE_5 0x0070 -#define ixGC_CAC_WEIGHT_GE_6 0x0071 -#define ixGC_CAC_WEIGHT_GE_7 0x0072 -#define ixGC_CAC_WEIGHT_GE_8 0x0073 -#define ixGC_CAC_WEIGHT_GE_9 0x0074 -#define ixGC_CAC_WEIGHT_GE_10 0x0075 -#define ixGC_CAC_WEIGHT_PMM_0 0x0076 -#define ixGC_CAC_WEIGHT_GL2C_0 0x0077 -#define ixGC_CAC_WEIGHT_GL2C_1 0x0078 -#define ixGC_CAC_WEIGHT_GL2C_2 0x0079 -#define ixGC_CAC_WEIGHT_GUS_0 0x007a -#define ixGC_CAC_WEIGHT_GUS_1 0x007b -#define ixGC_CAC_WEIGHT_PH_0 0x007c -#define ixGC_CAC_WEIGHT_PH_1 0x007d -#define ixGC_CAC_WEIGHT_PH_2 0x007e -#define ixGC_CAC_WEIGHT_PH_3 0x007f -#define ixGC_CAC_WEIGHT_SDMA_0 0x0080 -#define ixGC_CAC_WEIGHT_SDMA_1 0x0081 -#define ixGC_CAC_WEIGHT_SDMA_2 0x0082 -#define ixGC_CAC_WEIGHT_SDMA_3 0x0083 -#define ixGC_CAC_WEIGHT_SDMA_4 0x0084 -#define ixGC_CAC_WEIGHT_SDMA_5 0x0085 -#define ixGC_CAC_WEIGHT_SP_0 0x0086 -#define ixGC_CAC_WEIGHT_SP_1 0x0087 -#define ixGC_CAC_WEIGHT_GL1C_0 0x0088 -#define ixGC_CAC_WEIGHT_GL1C_1 0x0089 -#define ixGC_CAC_WEIGHT_GL1C_2 0x008a -#define ixGC_CAC_WEIGHT_CHC_0 0x008b -#define ixGC_CAC_WEIGHT_CHC_1 0x008c -#define ixGC_CAC_WEIGHT_SQC_0 0x008d -#define ixGC_CAC_WEIGHT_SQC_1 0x008e -#define ixGC_CAC_WEIGHT_RLC_0 0x008f -#define ixGC_CAC_ACC_LDS0 0x0100 -#define ixGC_CAC_ACC_LDS1 0x0101 -#define ixGC_CAC_ACC_LDS2 0x0102 -#define ixGC_CAC_ACC_LDS3 0x0103 -#define ixGC_CAC_ACC_LDS4 0x0104 -#define ixGC_CAC_ACC_LDS5 0x0105 -#define ixGC_CAC_ACC_LDS6 0x0106 -#define ixGC_CAC_ACC_LDS7 0x0107 -#define ixGC_CAC_ACC_LDS8 0x0108 -#define ixGC_CAC_ACC_BCI0 0x0109 -#define ixGC_CAC_ACC_BCI1 0x010a -#define ixGC_CAC_ACC_CB0 0x010b -#define ixGC_CAC_ACC_CB1 0x010c -#define ixGC_CAC_ACC_CB2 0x010d -#define ixGC_CAC_ACC_CB3 0x010e -#define ixGC_CAC_ACC_CB4 0x010f -#define ixGC_CAC_ACC_CB5 0x0110 -#define ixGC_CAC_ACC_CB6 0x0111 -#define ixGC_CAC_ACC_CB7 0x0112 -#define ixGC_CAC_ACC_CB8 0x0113 -#define ixGC_CAC_ACC_CB9 0x0114 -#define ixGC_CAC_ACC_CP0 0x0115 -#define ixGC_CAC_ACC_CP1 0x0116 -#define ixGC_CAC_ACC_CP2 0x0117 -#define ixGC_CAC_ACC_DB0 0x0118 -#define ixGC_CAC_ACC_DB1 0x0119 -#define ixGC_CAC_ACC_DB2 0x011a -#define ixGC_CAC_ACC_DB3 0x011b -#define ixGC_CAC_ACC_DB4 0x011c -#define ixGC_CAC_ACC_DB5 0x011d -#define ixGC_CAC_ACC_DB6 0x011e -#define ixGC_CAC_ACC_DB7 0x011f -#define ixGC_CAC_ACC_DB8 0x0120 -#define ixGC_CAC_ACC_DB9 0x0121 -#define ixGC_CAC_ACC_GDS0 0x0122 -#define ixGC_CAC_ACC_GDS1 0x0123 -#define ixGC_CAC_ACC_GDS2 0x0124 -#define ixGC_CAC_ACC_GDS3 0x0125 -#define ixGC_CAC_ACC_GDS4 0x0126 -#define ixGC_CAC_ACC_GDS5 0x0127 -#define ixGC_CAC_ACC_GDS6 0x0128 -#define ixGC_CAC_ACC_PA0 0x0129 -#define ixGC_CAC_ACC_PA1 0x012a -#define ixGC_CAC_ACC_PA2 0x012b -#define ixGC_CAC_ACC_PA3 0x012c -#define ixGC_CAC_ACC_PA4 0x012d -#define ixGC_CAC_ACC_PA5 0x012e -#define ixGC_CAC_ACC_PA6 0x012f -#define ixGC_CAC_ACC_PA7 0x0130 -#define ixGC_CAC_ACC_PC0 0x0131 -#define ixGC_CAC_ACC_SC0 0x0132 -#define ixGC_CAC_ACC_SC1 0x0133 -#define ixGC_CAC_ACC_SC2 0x0134 -#define ixGC_CAC_ACC_SC3 0x0135 -#define ixGC_CAC_ACC_SC4 0x0136 -#define ixGC_CAC_ACC_SC5 0x0137 -#define ixGC_CAC_ACC_SC6 0x0138 -#define ixGC_CAC_ACC_SC7 0x0139 -#define ixGC_CAC_ACC_SPI0 0x013a -#define ixGC_CAC_ACC_SPI1 0x013b -#define ixGC_CAC_ACC_SPI2 0x013c -#define ixGC_CAC_ACC_SPI3 0x013d -#define ixGC_CAC_ACC_SPI4 0x013e -#define ixGC_CAC_ACC_SPI5 0x013f -#define ixGC_CAC_ACC_SQ0_LOWER 0x0140 -#define ixGC_CAC_ACC_SQ0_UPPER 0x0141 -#define ixGC_CAC_ACC_SQ1_LOWER 0x0142 -#define ixGC_CAC_ACC_SQ1_UPPER 0x0143 -#define ixGC_CAC_ACC_SQ2_LOWER 0x0144 -#define ixGC_CAC_ACC_SQ2_UPPER 0x0145 -#define ixGC_CAC_ACC_SQ3_LOWER 0x0146 -#define ixGC_CAC_ACC_SQ3_UPPER 0x0147 -#define ixGC_CAC_ACC_SQ4_LOWER 0x0148 -#define ixGC_CAC_ACC_SQ4_UPPER 0x0149 -#define ixGC_CAC_ACC_SQ5_LOWER 0x014a -#define ixGC_CAC_ACC_SQ5_UPPER 0x014b -#define ixGC_CAC_ACC_SQ6_LOWER 0x014c -#define ixGC_CAC_ACC_SQ6_UPPER 0x014d -#define ixGC_CAC_ACC_SQ7_LOWER 0x014e -#define ixGC_CAC_ACC_SQ7_UPPER 0x014f -#define ixGC_CAC_ACC_SQ8_LOWER 0x0150 -#define ixGC_CAC_ACC_SQ8_UPPER 0x0151 -#define ixGC_CAC_ACC_SX0 0x0152 -#define ixGC_CAC_ACC_SXRB0 0x0153 -#define ixGC_CAC_ACC_TA0 0x0154 -#define ixGC_CAC_ACC_TCP0 0x0155 -#define ixGC_CAC_ACC_TCP1 0x0156 -#define ixGC_CAC_ACC_TCP2 0x0157 -#define ixGC_CAC_ACC_TCP3 0x0158 -#define ixGC_CAC_ACC_TCP4 0x0159 -#define ixGC_CAC_ACC_TCP5 0x015a -#define ixGC_CAC_ACC_TCP6 0x015b -#define ixGC_CAC_ACC_TCP7 0x015c -#define ixGC_CAC_ACC_TD0 0x015d -#define ixGC_CAC_ACC_TD1 0x015e -#define ixGC_CAC_ACC_TD2 0x015f -#define ixGC_CAC_ACC_TD3 0x0160 -#define ixGC_CAC_ACC_TD4 0x0161 -#define ixGC_CAC_ACC_TD5 0x0162 -#define ixGC_CAC_ACC_TD6 0x0163 -#define ixGC_CAC_ACC_TD7 0x0164 -#define ixGC_CAC_ACC_TD8 0x0165 -#define ixGC_CAC_ACC_TD9 0x0166 -#define ixGC_CAC_ACC_TD10 0x0167 -#define ixGC_CAC_ACC_RMI0 0x0168 -#define ixGC_CAC_ACC_RMI1 0x0169 -#define ixGC_CAC_ACC_RMI2 0x016a -#define ixGC_CAC_ACC_RMI3 0x016b -#define ixGC_CAC_ACC_EA0 0x016c -#define ixGC_CAC_ACC_EA1 0x016d -#define ixGC_CAC_ACC_EA2 0x016e -#define ixGC_CAC_ACC_EA3 0x016f -#define ixGC_CAC_ACC_EA4 0x0170 -#define ixGC_CAC_ACC_EA5 0x0171 -#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0172 -#define ixGC_CAC_ACC_UTCL2_ATCL21 0x0173 -#define ixGC_CAC_ACC_UTCL2_ATCL22 0x0174 -#define ixGC_CAC_ACC_UTCL2_ATCL23 0x0175 -#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0176 -#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x0177 -#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x0178 -#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x0179 -#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x017a -#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x017b -#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x017c -#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x017d -#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x017e -#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x017f -#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0180 -#define ixGC_CAC_ACC_UTCL2_VML20 0x0181 -#define ixGC_CAC_ACC_UTCL2_VML21 0x0182 -#define ixGC_CAC_ACC_UTCL2_VML22 0x0183 -#define ixGC_CAC_ACC_UTCL2_VML23 0x0184 -#define ixGC_CAC_ACC_UTCL2_VML24 0x0185 -#define ixGC_CAC_ACC_UTCL2_WALKER0 0x0186 -#define ixGC_CAC_ACC_UTCL2_WALKER1 0x0187 -#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0188 -#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0189 -#define ixGC_CAC_ACC_UTCL2_WALKER4 0x018a -#define ixGC_CAC_ACC_CU0 0x018b -#define ixGC_CAC_ACC_UTCL10 0x018c -#define ixGC_CAC_ACC_CHC0 0x018d -#define ixGC_CAC_ACC_CHC1 0x018e -#define ixGC_CAC_ACC_CHC2 0x018f -#define ixGC_CAC_ACC_GE0 0x0190 -#define ixGC_CAC_ACC_GE1 0x0191 -#define ixGC_CAC_ACC_GE2 0x0192 -#define ixGC_CAC_ACC_GE3 0x0193 -#define ixGC_CAC_ACC_GE4 0x0194 -#define ixGC_CAC_ACC_GE5 0x0195 -#define ixGC_CAC_ACC_GE6 0x0196 -#define ixGC_CAC_ACC_GE7 0x0197 -#define ixGC_CAC_ACC_GE8 0x0198 -#define ixGC_CAC_ACC_GE9 0x0199 -#define ixGC_CAC_ACC_GE10 0x019a -#define ixGC_CAC_ACC_GE11 0x019b -#define ixGC_CAC_ACC_GE12 0x019c -#define ixGC_CAC_ACC_GE13 0x019d -#define ixGC_CAC_ACC_GE14 0x019e -#define ixGC_CAC_ACC_GE15 0x019f -#define ixGC_CAC_ACC_GE16 0x01a0 -#define ixGC_CAC_ACC_GE17 0x01a1 -#define ixGC_CAC_ACC_GE18 0x01a2 -#define ixGC_CAC_ACC_GE19 0x01a3 -#define ixGC_CAC_ACC_GE20 0x01a4 -#define ixGC_CAC_ACC_PMM0 0x01a5 -#define ixGC_CAC_ACC_GL2C0 0x01a6 -#define ixGC_CAC_ACC_GL2C1 0x01a7 -#define ixGC_CAC_ACC_GL2C2 0x01a8 -#define ixGC_CAC_ACC_GL2C3 0x01a9 -#define ixGC_CAC_ACC_GL2C4 0x01aa -#define ixGC_CAC_ACC_GUS0 0x01ab -#define ixGC_CAC_ACC_GUS1 0x01ac -#define ixGC_CAC_ACC_GUS2 0x01ad -#define ixGC_CAC_ACC_PH0 0x01ae -#define ixGC_CAC_ACC_PH1 0x01af -#define ixGC_CAC_ACC_PH2 0x01b0 -#define ixGC_CAC_ACC_PH3 0x01b1 -#define ixGC_CAC_ACC_PH4 0x01b2 -#define ixGC_CAC_ACC_PH5 0x01b3 -#define ixGC_CAC_ACC_PH6 0x01b4 -#define ixGC_CAC_ACC_PH7 0x01b5 -#define ixGC_CAC_ACC_SDMA0 0x01b6 -#define ixGC_CAC_ACC_SDMA1 0x01b7 -#define ixGC_CAC_ACC_SDMA2 0x01b8 -#define ixGC_CAC_ACC_SDMA3 0x01b9 -#define ixGC_CAC_ACC_SDMA4 0x01ba -#define ixGC_CAC_ACC_SDMA5 0x01bb -#define ixGC_CAC_ACC_SDMA6 0x01bc -#define ixGC_CAC_ACC_SDMA7 0x01bd -#define ixGC_CAC_ACC_SDMA8 0x01be -#define ixGC_CAC_ACC_SDMA9 0x01bf -#define ixGC_CAC_ACC_SDMA10 0x01c0 -#define ixGC_CAC_ACC_SDMA11 0x01c1 -#define ixGC_CAC_ACC_SP0_LOWER 0x01c2 -#define ixGC_CAC_ACC_SP0_UPPER 0x01c3 -#define ixGC_CAC_ACC_SP1_LOWER 0x01c4 -#define ixGC_CAC_ACC_SP1_UPPER 0x01c5 -#define ixGC_CAC_ACC_SP2_LOWER 0x01c6 -#define ixGC_CAC_ACC_SP2_UPPER 0x01c7 -#define ixGC_CAC_ACC_GL1C0 0x01c8 -#define ixGC_CAC_ACC_GL1C1 0x01c9 -#define ixGC_CAC_ACC_GL1C2 0x01ca -#define ixGC_CAC_ACC_GL1C3 0x01cb -#define ixGC_CAC_ACC_GL1C4 0x01cc -#define ixGC_CAC_ACC_SQC0 0x01cd -#define ixGC_CAC_ACC_SQC1 0x01ce -#define ixGC_CAC_ACC_SQC2 0x01cf -#define ixGC_CAC_ACC_RLC0 0x01d0 -#define ixGC_CAC_OVRD_BCI 0x0200 -#define ixGC_CAC_OVRD_CB 0x0201 -#define ixGC_CAC_OVRD_CP 0x0203 -#define ixGC_CAC_OVRD_DB 0x0204 -#define ixGC_CAC_OVRD_GDS 0x0206 -#define ixGC_CAC_OVRD_LDS 0x0207 -#define ixGC_CAC_OVRD_PA 0x0208 -#define ixGC_CAC_OVRD_PC 0x0209 -#define ixGC_CAC_OVRD_SC 0x020a -#define ixGC_CAC_OVRD_SPI 0x020b -#define ixGC_CAC_OVRD_CU 0x020c -#define ixGC_CAC_OVRD_SQ 0x020d -#define ixGC_CAC_OVRD_SX 0x020e -#define ixGC_CAC_OVRD_SXRB 0x020f -#define ixGC_CAC_OVRD_TA 0x0210 -#define ixGC_CAC_OVRD_TCP 0x0211 -#define ixGC_CAC_OVRD_TD 0x0212 -#define ixGC_CAC_OVRD_RMI 0x0213 -#define ixGC_CAC_OVRD_EA 0x0214 -#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0215 -#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0216 -#define ixGC_CAC_OVRD_UTCL2_VML2 0x0217 -#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0218 -#define ixGC_CAC_OVRD_SP 0x0219 -#define ixGC_CAC_OVRD_UTCL1 0x021a -#define ixGC_CAC_OVRD_CHC 0x021b -#define ixGC_CAC_OVRD_GE 0x021c -#define ixGC_CAC_OVRD_PMM 0x021d -#define ixGC_CAC_OVRD_GL2C 0x021e -#define ixGC_CAC_OVRD_GUS 0x021f -#define ixGC_CAC_OVRD_PH 0x0220 -#define ixGC_CAC_OVRD_SDMA 0x0221 -#define ixGC_CAC_OVRD_GL1C 0x0222 -#define ixGC_CAC_OVRD_SQC 0x0223 -#define ixGC_CAC_OVRD_RLC 0x0224 -#define ixGC_CAC_OVRD_GE_HI 0x0225 -#define ixRELEASE_TO_STALL_LUT_1_8 0x0230 -#define ixRELEASE_TO_STALL_LUT_9_16 0x0231 -#define ixRELEASE_TO_STALL_LUT_17_20 0x0232 -#define ixSTALL_TO_RELEASE_LUT_1_4 0x0233 -#define ixSTALL_TO_RELEASE_LUT_5_7 0x0234 -#define ixSTALL_TO_PWRBRK_LUT_1_4 0x0235 -#define ixSTALL_TO_PWRBRK_LUT_5_7 0x0236 -#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x0237 -#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x0238 -#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x0239 -#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x023a -#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x023b -#define ixFIXED_PATTERN_PERF_COUNTER_1 0x023c -#define ixFIXED_PATTERN_PERF_COUNTER_2 0x023d -#define ixFIXED_PATTERN_PERF_COUNTER_3 0x023e -#define ixFIXED_PATTERN_PERF_COUNTER_4 0x023f -#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0240 -#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0241 -#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0242 -#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0243 -#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0244 -#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0245 -#define ixHW_LUT_UPDATE_STATUS 0x0246 - - -// addressBlock: secacind -// base address: 0x0 -#define ixSE_CAC_ID 0x0000 -#define ixSE_CAC_CNTL 0x0001 -#define ixSE_CAC_OVR_SEL 0x0002 -#define ixSE_CAC_OVR_VAL 0x0003 - - -// addressBlock: spmglbind -// base address: 0x0 -#define ixGLB_CPG_SAMPLEDELAY 0x0000 -#define ixGLB_CPC_SAMPLEDELAY 0x0001 -#define ixGLB_CPF_SAMPLEDELAY 0x0002 -#define ixGLB_GDS_SAMPLEDELAY 0x0003 -#define ixGLB_GCR_SAMPLEDELAY 0x0004 -#define ixGLB_PH_SAMPLEDELAY 0x0005 -#define ixGLB_GE1_SAMPLEDELAY 0x0006 -#define ixGLB_GE2DIST_SAMPLEDELAY 0x0007 -#define ixGLB_GUS_SAMPLEDELAY 0x0008 -#define ixGLB_CHA_SAMPLEDELAY 0x0009 -#define ixGLB_CHCG_SAMPLEDELAY 0x000a -#define ixGLB_ATCL2_SAMPLEDELAY 0x000b -#define ixGLB_VML2_SAMPLEDELAY 0x000c -#define ixGLB_SDMA0_SAMPLEDELAY 0x000d -#define ixGLB_SDMA1_SAMPLEDELAY 0x000e -#define ixGLB_SDMA2_SAMPLEDELAY 0x000f -#define ixGLB_SDMA3_SAMPLEDELAY 0x0010 -#define ixGLB_GL2A0_SAMPLEDELAY 0x0011 -#define ixGLB_GL2A1_SAMPLEDELAY 0x0012 -#define ixGLB_GL2A2_SAMPLEDELAY 0x0013 -#define ixGLB_GL2A3_SAMPLEDELAY 0x0014 -#define ixGLB_GL2C0_SAMPLEDELAY 0x0015 -#define ixGLB_GL2C1_SAMPLEDELAY 0x0016 -#define ixGLB_GL2C2_SAMPLEDELAY 0x0017 -#define ixGLB_GL2C3_SAMPLEDELAY 0x0018 -#define ixGLB_GL2C4_SAMPLEDELAY 0x0019 -#define ixGLB_GL2C5_SAMPLEDELAY 0x001a -#define ixGLB_GL2C6_SAMPLEDELAY 0x001b -#define ixGLB_GL2C7_SAMPLEDELAY 0x001c -#define ixGLB_GL2C8_SAMPLEDELAY 0x001d -#define ixGLB_GL2C9_SAMPLEDELAY 0x001e -#define ixGLB_GL2C10_SAMPLEDELAY 0x001f -#define ixGLB_GL2C11_SAMPLEDELAY 0x0020 -#define ixGLB_GL2C12_SAMPLEDELAY 0x0021 -#define ixGLB_GL2C13_SAMPLEDELAY 0x0022 -#define ixGLB_GL2C14_SAMPLEDELAY 0x0023 -#define ixGLB_GL2C15_SAMPLEDELAY 0x0024 -#define ixGLB_EA0_SAMPLEDELAY 0x0025 -#define ixGLB_EA1_SAMPLEDELAY 0x0026 -#define ixGLB_EA2_SAMPLEDELAY 0x0027 -#define ixGLB_EA3_SAMPLEDELAY 0x0028 -#define ixGLB_EA4_SAMPLEDELAY 0x0029 -#define ixGLB_EA5_SAMPLEDELAY 0x002a -#define ixGLB_EA6_SAMPLEDELAY 0x002b -#define ixGLB_EA7_SAMPLEDELAY 0x002c -#define ixGLB_EA8_SAMPLEDELAY 0x002d -#define ixGLB_EA9_SAMPLEDELAY 0x002e -#define ixGLB_EA10_SAMPLEDELAY 0x002f -#define ixGLB_EA11_SAMPLEDELAY 0x0030 -#define ixGLB_EA12_SAMPLEDELAY 0x0031 -#define ixGLB_EA13_SAMPLEDELAY 0x0032 -#define ixGLB_EA14_SAMPLEDELAY 0x0033 -#define ixGLB_EA15_SAMPLEDELAY 0x0034 -#define ixGLB_CHC0_SAMPLEDELAY 0x0035 -#define ixGLB_CHC1_SAMPLEDELAY 0x0036 -#define ixGLB_CHC2_SAMPLEDELAY 0x0037 -#define ixGLB_CHC3_SAMPLEDELAY 0x0038 -#define ixGLB_GE2SE0_SAMPLEDELAY 0x0039 -#define ixGLB_GE2SE1_SAMPLEDELAY 0x003a -#define ixGLB_GE2SE2_SAMPLEDELAY 0x003b -#define ixGLB_GE2SE3_SAMPLEDELAY 0x003c - - -// addressBlock: spmind -// base address: 0x0 -#define ixSE_SPI_SAMPLEDELAY 0x0000 -#define ixSE_SQG_SAMPLEDELAY 0x0001 -#define ixSE_CBR_SAMPLEDELAY 0x0002 -#define ixSE_DBR_SAMPLEDELAY 0x0003 -#define ixSE_PA_SAMPLEDELAY 0x0004 -#define ixSE_SA0SX_SAMPLEDELAY 0x0005 -#define ixSE_SA0GL1A_SAMPLEDELAY 0x0006 -#define ixSE_SA0GL1CG_SAMPLEDELAY 0x0007 -#define ixSE_SA0CB0_SAMPLEDELAY 0x0008 -#define ixSE_SA0CB1_SAMPLEDELAY 0x0009 -#define ixSE_SA0DB0_SAMPLEDELAY 0x000a -#define ixSE_SA0DB1_SAMPLEDELAY 0x000b -#define ixSE_SA0SC0_SAMPLEDELAY 0x000c -#define ixSE_SA0SC1_SAMPLEDELAY 0x000d -#define ixSE_SA0RMI0_SAMPLEDELAY 0x000e -#define ixSE_SA0RMI1_SAMPLEDELAY 0x000f -#define ixSE_SA0GL1C0_SAMPLEDELAY 0x0010 -#define ixSE_SA0GL1C1_SAMPLEDELAY 0x0011 -#define ixSE_SA0GL1C2_SAMPLEDELAY 0x0012 -#define ixSE_SA0GL1C3_SAMPLEDELAY 0x0013 -#define ixSE_SA0WGP00TA0_SAMPLEDELAY 0x0014 -#define ixSE_SA0WGP00TA1_SAMPLEDELAY 0x0015 -#define ixSE_SA0WGP00TD0_SAMPLEDELAY 0x0016 -#define ixSE_SA0WGP00TD1_SAMPLEDELAY 0x0017 -#define ixSE_SA0WGP00TCP0_SAMPLEDELAY 0x0018 -#define ixSE_SA0WGP00TCP1_SAMPLEDELAY 0x0019 -#define ixSE_SA0WGP01TA0_SAMPLEDELAY 0x001a -#define ixSE_SA0WGP01TA1_SAMPLEDELAY 0x001b -#define ixSE_SA0WGP01TD0_SAMPLEDELAY 0x001c -#define ixSE_SA0WGP01TD1_SAMPLEDELAY 0x001d -#define ixSE_SA0WGP01TCP0_SAMPLEDELAY 0x001e -#define ixSE_SA0WGP01TCP1_SAMPLEDELAY 0x001f -#define ixSE_SA0WGP02TA0_SAMPLEDELAY 0x0020 -#define ixSE_SA0WGP02TA1_SAMPLEDELAY 0x0021 -#define ixSE_SA0WGP02TD0_SAMPLEDELAY 0x0022 -#define ixSE_SA0WGP02TD1_SAMPLEDELAY 0x0023 -#define ixSE_SA0WGP02TCP0_SAMPLEDELAY 0x0024 -#define ixSE_SA0WGP02TCP1_SAMPLEDELAY 0x0025 -#define ixSE_SA0WGP03TA0_SAMPLEDELAY 0x0026 -#define ixSE_SA0WGP03TA1_SAMPLEDELAY 0x0027 -#define ixSE_SA0WGP03TD0_SAMPLEDELAY 0x0028 -#define ixSE_SA0WGP03TD1_SAMPLEDELAY 0x0029 -#define ixSE_SA0WGP03TCP0_SAMPLEDELAY 0x002a -#define ixSE_SA0WGP03TCP1_SAMPLEDELAY 0x002b -#define ixSE_SA0WGP04TA0_SAMPLEDELAY 0x002c -#define ixSE_SA0WGP04TA1_SAMPLEDELAY 0x002d -#define ixSE_SA0WGP04TD0_SAMPLEDELAY 0x002e -#define ixSE_SA0WGP04TD1_SAMPLEDELAY 0x002f -#define ixSE_SA0WGP04TCP0_SAMPLEDELAY 0x0030 -#define ixSE_SA0WGP04TCP1_SAMPLEDELAY 0x0031 -#define ixSE_SA1SX_SAMPLEDELAY 0x0032 -#define ixSE_SA1GL1A_SAMPLEDELAY 0x0033 -#define ixSE_SA1GL1CG_SAMPLEDELAY 0x0034 -#define ixSE_SA1CB0_SAMPLEDELAY 0x0035 -#define ixSE_SA1CB1_SAMPLEDELAY 0x0036 -#define ixSE_SA1DB0_SAMPLEDELAY 0x0037 -#define ixSE_SA1DB1_SAMPLEDELAY 0x0038 -#define ixSE_SA1SC0_SAMPLEDELAY 0x0039 -#define ixSE_SA1SC1_SAMPLEDELAY 0x003a -#define ixSE_SA1RMI0_SAMPLEDELAY 0x003b -#define ixSE_SA1RMI1_SAMPLEDELAY 0x003c -#define ixSE_SA1GL1C0_SAMPLEDELAY 0x003d -#define ixSE_SA1GL1C1_SAMPLEDELAY 0x003e -#define ixSE_SA1GL1C2_SAMPLEDELAY 0x003f -#define ixSE_SA1GL1C3_SAMPLEDELAY 0x0040 -#define ixSE_SA1WGP00TA0_SAMPLEDELAY 0x0041 -#define ixSE_SA1WGP00TA1_SAMPLEDELAY 0x0042 -#define ixSE_SA1WGP00TD0_SAMPLEDELAY 0x0043 -#define ixSE_SA1WGP00TD1_SAMPLEDELAY 0x0044 -#define ixSE_SA1WGP00TCP0_SAMPLEDELAY 0x0045 -#define ixSE_SA1WGP00TCP1_SAMPLEDELAY 0x0046 -#define ixSE_SA1WGP01TA0_SAMPLEDELAY 0x0047 -#define ixSE_SA1WGP01TA1_SAMPLEDELAY 0x0048 -#define ixSE_SA1WGP01TD0_SAMPLEDELAY 0x0049 -#define ixSE_SA1WGP01TD1_SAMPLEDELAY 0x004a -#define ixSE_SA1WGP01TCP0_SAMPLEDELAY 0x004b -#define ixSE_SA1WGP01TCP1_SAMPLEDELAY 0x004c -#define ixSE_SA1WGP02TA0_SAMPLEDELAY 0x004d -#define ixSE_SA1WGP02TA1_SAMPLEDELAY 0x004e -#define ixSE_SA1WGP02TD0_SAMPLEDELAY 0x004f -#define ixSE_SA1WGP02TD1_SAMPLEDELAY 0x0050 -#define ixSE_SA1WGP02TCP0_SAMPLEDELAY 0x0051 -#define ixSE_SA1WGP02TCP1_SAMPLEDELAY 0x0052 -#define ixSE_SA1WGP03TA0_SAMPLEDELAY 0x0053 -#define ixSE_SA1WGP03TA1_SAMPLEDELAY 0x0054 -#define ixSE_SA1WGP03TD0_SAMPLEDELAY 0x0055 -#define ixSE_SA1WGP03TD1_SAMPLEDELAY 0x0056 -#define ixSE_SA1WGP03TCP0_SAMPLEDELAY 0x0057 -#define ixSE_SA1WGP03TCP1_SAMPLEDELAY 0x0058 -#define ixSE_SA1WGP04TA0_SAMPLEDELAY 0x0059 -#define ixSE_SA1WGP04TA1_SAMPLEDELAY 0x005a -#define ixSE_SA1WGP04TD0_SAMPLEDELAY 0x005b -#define ixSE_SA1WGP04TD1_SAMPLEDELAY 0x005c -#define ixSE_SA1WGP04TCP0_SAMPLEDELAY 0x005d -#define ixSE_SA1WGP04TCP1_SAMPLEDELAY 0x005e - - -// base address: 0x0 - - -// addressBlock: grtavfsind -// base address: 0x0 -#define ixRTAVFS_REG0 0x0000 -#define ixRTAVFS_REG1 0x0001 -#define ixRTAVFS_REG2 0x0002 -#define ixRTAVFS_REG3 0x0003 -#define ixRTAVFS_REG4 0x0004 -#define ixRTAVFS_REG5 0x0005 -#define ixRTAVFS_REG6 0x0006 -#define ixRTAVFS_REG7 0x0007 -#define ixRTAVFS_REG8 0x0008 -#define ixRTAVFS_REG9 0x0009 -#define ixRTAVFS_REG10 0x000a -#define ixRTAVFS_REG11 0x000b -#define ixRTAVFS_REG12 0x000c -#define ixRTAVFS_REG13 0x000d -#define ixRTAVFS_REG14 0x000e -#define ixRTAVFS_REG15 0x000f -#define ixRTAVFS_REG16 0x0010 -#define ixRTAVFS_REG17 0x0011 -#define ixRTAVFS_REG18 0x0012 -#define ixRTAVFS_REG19 0x0013 -#define ixRTAVFS_REG20 0x0014 -#define ixRTAVFS_REG21 0x0015 -#define ixRTAVFS_REG22 0x0016 -#define ixRTAVFS_REG23 0x0017 -#define ixRTAVFS_REG24 0x0018 -#define ixRTAVFS_REG25 0x0019 -#define ixRTAVFS_REG26 0x001a -#define ixRTAVFS_REG27 0x001b -#define ixRTAVFS_REG28 0x001c -#define ixRTAVFS_REG29 0x001d -#define ixRTAVFS_REG30 0x001e -#define ixRTAVFS_REG31 0x001f -#define ixRTAVFS_REG32 0x0020 -#define ixRTAVFS_REG33 0x0021 -#define ixRTAVFS_REG34 0x0022 -#define ixRTAVFS_REG35 0x0023 -#define ixRTAVFS_REG36 0x0024 -#define ixRTAVFS_REG37 0x0025 -#define ixRTAVFS_REG38 0x0026 -#define ixRTAVFS_REG39 0x0027 -#define ixRTAVFS_REG40 0x0028 -#define ixRTAVFS_REG41 0x0029 -#define ixRTAVFS_REG42 0x002a -#define ixRTAVFS_REG43 0x002b -#define ixRTAVFS_REG44 0x002c -#define ixRTAVFS_REG45 0x002d -#define ixRTAVFS_REG46 0x002e -#define ixRTAVFS_REG47 0x002f -#define ixRTAVFS_REG48 0x0030 -#define ixRTAVFS_REG49 0x0031 -#define ixRTAVFS_REG50 0x0032 -#define ixRTAVFS_REG51 0x0033 -#define ixRTAVFS_REG52 0x0034 -#define ixRTAVFS_REG53 0x0035 -#define ixRTAVFS_REG54 0x0036 -#define ixRTAVFS_REG55 0x0037 -#define ixRTAVFS_REG56 0x0038 -#define ixRTAVFS_REG57 0x0039 -#define ixRTAVFS_REG58 0x003a -#define ixRTAVFS_REG59 0x003b -#define ixRTAVFS_REG60 0x003c -#define ixRTAVFS_REG61 0x003d -#define ixRTAVFS_REG62 0x003e -#define ixRTAVFS_REG63 0x003f -#define ixRTAVFS_REG64 0x0040 -#define ixRTAVFS_REG65 0x0041 -#define ixRTAVFS_REG66 0x0042 -#define ixRTAVFS_REG67 0x0043 -#define ixRTAVFS_REG68 0x0044 -#define ixRTAVFS_REG69 0x0045 -#define ixRTAVFS_REG70 0x0046 -#define ixRTAVFS_REG71 0x0047 -#define ixRTAVFS_REG72 0x0048 -#define ixRTAVFS_REG73 0x0049 -#define ixRTAVFS_REG74 0x004a -#define ixRTAVFS_REG75 0x004b -#define ixRTAVFS_REG76 0x004c -#define ixRTAVFS_REG77 0x004d -#define ixRTAVFS_REG78 0x004e -#define ixRTAVFS_REG79 0x004f -#define ixRTAVFS_REG80 0x0050 -#define ixRTAVFS_REG81 0x0051 -#define ixRTAVFS_REG82 0x0052 -#define ixRTAVFS_REG83 0x0053 -#define ixRTAVFS_REG84 0x0054 -#define ixRTAVFS_REG85 0x0055 -#define ixRTAVFS_REG86 0x0056 -#define ixRTAVFS_REG87 0x0057 -#define ixRTAVFS_REG88 0x0058 -#define ixRTAVFS_REG89 0x0059 -#define ixRTAVFS_REG90 0x005a -#define ixRTAVFS_REG91 0x005b -#define ixRTAVFS_REG92 0x005c -#define ixRTAVFS_REG93 0x005d -#define ixRTAVFS_REG94 0x005e -#define ixRTAVFS_REG95 0x005f -#define ixRTAVFS_REG96 0x0060 -#define ixRTAVFS_REG97 0x0061 -#define ixRTAVFS_REG98 0x0062 -#define ixRTAVFS_REG99 0x0063 -#define ixRTAVFS_REG100 0x0064 -#define ixRTAVFS_REG101 0x0065 -#define ixRTAVFS_REG102 0x0066 -#define ixRTAVFS_REG103 0x0067 -#define ixRTAVFS_REG104 0x0068 -#define ixRTAVFS_REG105 0x0069 -#define ixRTAVFS_REG106 0x006a -#define ixRTAVFS_REG107 0x006b -#define ixRTAVFS_REG108 0x006c -#define ixRTAVFS_REG109 0x006d -#define ixRTAVFS_REG110 0x006e -#define ixRTAVFS_REG111 0x006f -#define ixRTAVFS_REG112 0x0070 -#define ixRTAVFS_REG113 0x0071 -#define ixRTAVFS_REG114 0x0072 -#define ixRTAVFS_REG115 0x0073 -#define ixRTAVFS_REG116 0x0074 -#define ixRTAVFS_REG117 0x0075 -#define ixRTAVFS_REG118 0x0076 -#define ixRTAVFS_REG119 0x0077 -#define ixRTAVFS_REG120 0x0078 -#define ixRTAVFS_REG121 0x0079 -#define ixRTAVFS_REG122 0x007a -#define ixRTAVFS_REG123 0x007b -#define ixRTAVFS_REG124 0x007c -#define ixRTAVFS_REG125 0x007d -#define ixRTAVFS_REG126 0x007e -#define ixRTAVFS_REG127 0x007f -#define ixRTAVFS_REG128 0x0080 -#define ixRTAVFS_REG129 0x0081 -#define ixRTAVFS_REG130 0x0082 -#define ixRTAVFS_REG131 0x0083 -#define ixRTAVFS_REG132 0x0084 -#define ixRTAVFS_REG133 0x0085 -#define ixRTAVFS_REG134 0x0086 -#define ixRTAVFS_REG135 0x0087 -#define ixRTAVFS_REG136 0x0088 -#define ixRTAVFS_REG137 0x0089 -#define ixRTAVFS_REG138 0x008a -#define ixRTAVFS_REG139 0x008b -#define ixRTAVFS_REG140 0x008c -#define ixRTAVFS_REG141 0x008d -#define ixRTAVFS_REG142 0x008e -#define ixRTAVFS_REG143 0x008f -#define ixRTAVFS_REG144 0x0090 -#define ixRTAVFS_REG145 0x0091 -#define ixRTAVFS_REG146 0x0092 -#define ixRTAVFS_REG147 0x0093 -#define ixRTAVFS_REG148 0x0094 -#define ixRTAVFS_REG149 0x0095 -#define ixRTAVFS_REG150 0x0096 -#define ixRTAVFS_REG151 0x0097 -#define ixRTAVFS_REG152 0x0098 -#define ixRTAVFS_REG153 0x0099 -#define ixRTAVFS_REG154 0x009a -#define ixRTAVFS_REG155 0x009b -#define ixRTAVFS_REG156 0x009c -#define ixRTAVFS_REG157 0x009d -#define ixRTAVFS_REG158 0x009e -#define ixRTAVFS_REG159 0x009f -#define ixRTAVFS_REG160 0x00a0 -#define ixRTAVFS_REG161 0x00a1 -#define ixRTAVFS_REG162 0x00a2 -#define ixRTAVFS_REG163 0x00a3 -#define ixRTAVFS_REG164 0x00a4 -#define ixRTAVFS_REG165 0x00a5 - - -// addressBlock: spiind -// base address: 0x0 -#define ixSA_WGP_BLK_ID 0x0000 - - -// addressBlock: sqind -// base address: 0x0 -#define ixSQ_DEBUG_STS_LOCAL 0x0008 -#define ixSQ_WAVE_ACTIVE 0x000a -#define ixSQ_WAVE_VALID_AND_IDLE 0x000b -#define ixSQ_WAVE_MODE 0x0101 -#define ixSQ_WAVE_STATUS 0x0102 -#define ixSQ_WAVE_TRAPSTS 0x0103 -#define ixSQ_WAVE_HW_ID_LEGACY 0x0104 -#define ixSQ_WAVE_GPR_ALLOC 0x0105 -#define ixSQ_WAVE_LDS_ALLOC 0x0106 -#define ixSQ_WAVE_IB_STS 0x0107 -#define ixSQ_WAVE_PC_LO 0x0108 -#define ixSQ_WAVE_PC_HI 0x0109 -#define ixSQ_WAVE_INST_DW0 0x010a -#define ixSQ_WAVE_IB_DBG1 0x010d -#define ixSQ_WAVE_FLUSH_IB 0x010e -#define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0114 -#define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0115 -#define ixSQ_WAVE_HW_ID1 0x0117 -#define ixSQ_WAVE_HW_ID2 0x0118 -#define ixSQ_WAVE_POPS_PACKER 0x0119 -#define ixSQ_WAVE_SCHED_MODE 0x011a -#define ixSQ_WAVE_VGPR_OFFSET 0x011b -#define ixSQ_WAVE_IB_STS2 0x011c -#define ixSQ_WAVE_SHADER_CYCLES 0x011d -#define ixSQ_WAVE_TTMP0 0x026c -#define ixSQ_WAVE_TTMP1 0x026d -#define ixSQ_WAVE_TTMP2 0x026e -#define ixSQ_WAVE_TTMP3 0x026f -#define ixSQ_WAVE_TTMP4 0x0270 -#define ixSQ_WAVE_TTMP5 0x0271 -#define ixSQ_WAVE_TTMP6 0x0272 -#define ixSQ_WAVE_TTMP7 0x0273 -#define ixSQ_WAVE_TTMP8 0x0274 -#define ixSQ_WAVE_TTMP9 0x0275 -#define ixSQ_WAVE_TTMP10 0x0276 -#define ixSQ_WAVE_TTMP11 0x0277 -#define ixSQ_WAVE_TTMP12 0x0278 -#define ixSQ_WAVE_TTMP13 0x0279 -#define ixSQ_WAVE_TTMP14 0x027a -#define ixSQ_WAVE_TTMP15 0x027b -#define ixSQ_WAVE_M0 0x027c -#define ixSQ_WAVE_EXEC_LO 0x027e -#define ixSQ_WAVE_EXEC_HI 0x027f -#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 -#define ixSQ_INTERRUPT_WORD_ERROR 0x20c0 -#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 - - -// addressBlock: didtind -// base address: 0x0 -#define ixDIDT_SQ_CTRL0 0x0000 -#define ixDIDT_SQ_CTRL1 0x0001 -#define ixDIDT_SQ_CTRL2 0x0002 -#define ixDIDT_SQ_CTRL_OCP 0x0003 -#define ixDIDT_SQ_STALL_CTRL 0x0004 -#define ixDIDT_SQ_TUNING_CTRL 0x0005 -#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 -#define ixDIDT_SQ_CTRL3 0x0007 -#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 -#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 -#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a -#define ixDIDT_SQ_STALL_PATTERN_7 0x000b -#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c -#define ixDIDT_SQ_STALL_RELEASE_CNTL0 0x000d -#define ixDIDT_SQ_STALL_RELEASE_CNTL1 0x000e -#define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS 0x000f -#define ixDIDT_SQ_WEIGHT0_3 0x0010 -#define ixDIDT_SQ_WEIGHT4_7 0x0011 -#define ixDIDT_SQ_WEIGHT8_11 0x0012 -#define ixDIDT_SQ_EDC_CTRL 0x0013 -#define ixDIDT_SQ_EDC_THRESHOLD 0x0014 -#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 -#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 -#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 -#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 -#define ixDIDT_SQ_EDC_TIMER_PERIOD 0x0019 -#define ixDIDT_SQ_THROTTLE_CTRL 0x001a -#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001b -#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001c -#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001d -#define ixDIDT_SQ_EDC_STATUS 0x001f -#define ixDIDT_SQ_EDC_OVERFLOW 0x0020 -#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x0021 -#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0x0022 -#define ixDIDT_DB_CTRL0 0x0030 -#define ixDIDT_DB_CTRL1 0x0031 -#define ixDIDT_DB_CTRL2 0x0032 -#define ixDIDT_DB_CTRL_OCP 0x0033 -#define ixDIDT_DB_STALL_CTRL 0x0034 -#define ixDIDT_DB_TUNING_CTRL 0x0035 -#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0036 -#define ixDIDT_DB_CTRL3 0x0037 -#define ixDIDT_DB_STALL_PATTERN_1_2 0x0038 -#define ixDIDT_DB_STALL_PATTERN_3_4 0x0039 -#define ixDIDT_DB_STALL_PATTERN_5_6 0x003a -#define ixDIDT_DB_STALL_PATTERN_7 0x003b -#define ixDIDT_DB_MPD_SCALE_FACTOR 0x003c -#define ixDIDT_DB_STALL_RELEASE_CNTL0 0x003d -#define ixDIDT_DB_STALL_RELEASE_CNTL1 0x003e -#define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS 0x003f -#define ixDIDT_DB_WEIGHT0_3 0x0040 -#define ixDIDT_DB_WEIGHT4_7 0x0041 -#define ixDIDT_DB_WEIGHT8_11 0x0042 -#define ixDIDT_DB_EDC_CTRL 0x0043 -#define ixDIDT_DB_EDC_THRESHOLD 0x0044 -#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0045 -#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0046 -#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0047 -#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0048 -#define ixDIDT_DB_EDC_TIMER_PERIOD 0x0049 -#define ixDIDT_DB_THROTTLE_CTRL 0x004a -#define ixDIDT_DB_EDC_STALL_DELAY_1 0x004b -#define ixDIDT_DB_EDC_STATUS 0x004f -#define ixDIDT_DB_EDC_OVERFLOW 0x0050 -#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x0051 -#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0x0052 -#define ixDIDT_TD_CTRL0 0x0060 -#define ixDIDT_TD_CTRL1 0x0061 -#define ixDIDT_TD_CTRL2 0x0062 -#define ixDIDT_TD_CTRL_OCP 0x0063 -#define ixDIDT_TD_STALL_CTRL 0x0064 -#define ixDIDT_TD_TUNING_CTRL 0x0065 -#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0066 -#define ixDIDT_TD_CTRL3 0x0067 -#define ixDIDT_TD_STALL_PATTERN_1_2 0x0068 -#define ixDIDT_TD_STALL_PATTERN_3_4 0x0069 -#define ixDIDT_TD_STALL_PATTERN_5_6 0x006a -#define ixDIDT_TD_STALL_PATTERN_7 0x006b -#define ixDIDT_TD_MPD_SCALE_FACTOR 0x006c -#define ixDIDT_TD_STALL_RELEASE_CNTL0 0x006d -#define ixDIDT_TD_STALL_RELEASE_CNTL1 0x006e -#define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS 0x006f -#define ixDIDT_TD_WEIGHT0_3 0x0070 -#define ixDIDT_TD_WEIGHT4_7 0x0071 -#define ixDIDT_TD_WEIGHT8_11 0x0072 -#define ixDIDT_TD_EDC_CTRL 0x0073 -#define ixDIDT_TD_EDC_THRESHOLD 0x0074 -#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0075 -#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0076 -#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0077 -#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0078 -#define ixDIDT_TD_EDC_TIMER_PERIOD 0x0079 -#define ixDIDT_TD_THROTTLE_CTRL 0x007a -#define ixDIDT_TD_EDC_STALL_DELAY_1 0x007b -#define ixDIDT_TD_EDC_STALL_DELAY_2 0x007c -#define ixDIDT_TD_EDC_STALL_DELAY_3 0x007d -#define ixDIDT_TD_EDC_STATUS 0x007f -#define ixDIDT_TD_EDC_OVERFLOW 0x0080 -#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x0081 -#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0x0082 -#define ixDIDT_TCP_CTRL0 0x0090 -#define ixDIDT_TCP_CTRL1 0x0091 -#define ixDIDT_TCP_CTRL2 0x0092 -#define ixDIDT_TCP_CTRL_OCP 0x0093 -#define ixDIDT_TCP_STALL_CTRL 0x0094 -#define ixDIDT_TCP_TUNING_CTRL 0x0095 -#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0096 -#define ixDIDT_TCP_CTRL3 0x0097 -#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0098 -#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0099 -#define ixDIDT_TCP_STALL_PATTERN_5_6 0x009a -#define ixDIDT_TCP_STALL_PATTERN_7 0x009b -#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x009c -#define ixDIDT_TCP_STALL_RELEASE_CNTL0 0x009d -#define ixDIDT_TCP_STALL_RELEASE_CNTL1 0x009e -#define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS 0x009f -#define ixDIDT_TCP_WEIGHT0_3 0x00a0 -#define ixDIDT_TCP_WEIGHT4_7 0x00a1 -#define ixDIDT_TCP_WEIGHT8_11 0x00a2 -#define ixDIDT_TCP_EDC_CTRL 0x00a3 -#define ixDIDT_TCP_EDC_THRESHOLD 0x00a4 -#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x00a5 -#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x00a6 -#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x00a7 -#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x00a8 -#define ixDIDT_TCP_EDC_TIMER_PERIOD 0x00a9 -#define ixDIDT_TCP_THROTTLE_CTRL 0x00aa -#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x00ab -#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x00ac -#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x00ad -#define ixDIDT_TCP_EDC_STATUS 0x00af -#define ixDIDT_TCP_EDC_OVERFLOW 0x00b0 -#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x00b1 -#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0x00b2 -#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00c0 -#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00c1 -#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00c2 -#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00c3 - - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/gc_11_0_0_offset.h b/tinygrad/extra/hip_gpu_driver/gc_11_0_0_offset.h deleted file mode 100644 index a3bcdf63..00000000 --- a/tinygrad/extra/hip_gpu_driver/gc_11_0_0_offset.h +++ /dev/null @@ -1,11685 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _gc_11_0_0_OFFSET_HEADER -#define _gc_11_0_0_OFFSET_HEADER - - - -// addressBlock: gc_sdma0_sdma0dec -// base address: 0x4980 -#define regSDMA0_DEC_START 0x0000 -#define regSDMA0_DEC_START_BASE_IDX 0 -#define regSDMA0_F32_MISC_CNTL 0x000b -#define regSDMA0_F32_MISC_CNTL_BASE_IDX 0 -#define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f -#define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 -#define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010 -#define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 -#define regSDMA0_POWER_CNTL 0x001a -#define regSDMA0_POWER_CNTL_BASE_IDX 0 -#define regSDMA0_CNTL 0x001c -#define regSDMA0_CNTL_BASE_IDX 0 -#define regSDMA0_CHICKEN_BITS 0x001d -#define regSDMA0_CHICKEN_BITS_BASE_IDX 0 -#define regSDMA0_GB_ADDR_CONFIG 0x001e -#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 -#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f -#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define regSDMA0_RB_RPTR_FETCH 0x0020 -#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 -#define regSDMA0_RB_RPTR_FETCH_HI 0x0021 -#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0022 -#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define regSDMA0_IB_OFFSET_FETCH 0x0023 -#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 -#define regSDMA0_PROGRAM 0x0024 -#define regSDMA0_PROGRAM_BASE_IDX 0 -#define regSDMA0_STATUS_REG 0x0025 -#define regSDMA0_STATUS_REG_BASE_IDX 0 -#define regSDMA0_STATUS1_REG 0x0026 -#define regSDMA0_STATUS1_REG_BASE_IDX 0 -#define regSDMA0_CNTL1 0x0027 -#define regSDMA0_CNTL1_BASE_IDX 0 -#define regSDMA0_HBM_PAGE_CONFIG 0x0028 -#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 -#define regSDMA0_UCODE_CHECKSUM 0x0029 -#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 -#define regSDMA0_FREEZE 0x002b -#define regSDMA0_FREEZE_BASE_IDX 0 -#define regSDMA0_PROCESS_QUANTUM0 0x002c -#define regSDMA0_PROCESS_QUANTUM0_BASE_IDX 0 -#define regSDMA0_PROCESS_QUANTUM1 0x002d -#define regSDMA0_PROCESS_QUANTUM1_BASE_IDX 0 -#define regSDMA0_WATCHDOG_CNTL 0x002e -#define regSDMA0_WATCHDOG_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE_STATUS0 0x002f -#define regSDMA0_QUEUE_STATUS0_BASE_IDX 0 -#define regSDMA0_EDC_CONFIG 0x0032 -#define regSDMA0_EDC_CONFIG_BASE_IDX 0 -#define regSDMA0_BA_THRESHOLD 0x0033 -#define regSDMA0_BA_THRESHOLD_BASE_IDX 0 -#define regSDMA0_ID 0x0034 -#define regSDMA0_ID_BASE_IDX 0 -#define regSDMA0_VERSION 0x0035 -#define regSDMA0_VERSION_BASE_IDX 0 -#define regSDMA0_EDC_COUNTER 0x0036 -#define regSDMA0_EDC_COUNTER_BASE_IDX 0 -#define regSDMA0_EDC_COUNTER_CLEAR 0x0037 -#define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define regSDMA0_STATUS2_REG 0x0038 -#define regSDMA0_STATUS2_REG_BASE_IDX 0 -#define regSDMA0_ATOMIC_CNTL 0x0039 -#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 -#define regSDMA0_ATOMIC_PREOP_LO 0x003a -#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 -#define regSDMA0_ATOMIC_PREOP_HI 0x003b -#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 -#define regSDMA0_UTCL1_CNTL 0x003c -#define regSDMA0_UTCL1_CNTL_BASE_IDX 0 -#define regSDMA0_UTCL1_WATERMK 0x003d -#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 -#define regSDMA0_UTCL1_TIMEOUT 0x003e -#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 -#define regSDMA0_UTCL1_PAGE 0x003f -#define regSDMA0_UTCL1_PAGE_BASE_IDX 0 -#define regSDMA0_UTCL1_RD_STATUS 0x0040 -#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 -#define regSDMA0_UTCL1_WR_STATUS 0x0041 -#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 -#define regSDMA0_UTCL1_INV0 0x0042 -#define regSDMA0_UTCL1_INV0_BASE_IDX 0 -#define regSDMA0_UTCL1_INV1 0x0043 -#define regSDMA0_UTCL1_INV1_BASE_IDX 0 -#define regSDMA0_UTCL1_INV2 0x0044 -#define regSDMA0_UTCL1_INV2_BASE_IDX 0 -#define regSDMA0_UTCL1_RD_XNACK0 0x0045 -#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 -#define regSDMA0_UTCL1_RD_XNACK1 0x0046 -#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 -#define regSDMA0_UTCL1_WR_XNACK0 0x0047 -#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 -#define regSDMA0_UTCL1_WR_XNACK1 0x0048 -#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 -#define regSDMA0_RELAX_ORDERING_LUT 0x004a -#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 -#define regSDMA0_CHICKEN_BITS_2 0x004b -#define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 -#define regSDMA0_STATUS3_REG 0x004c -#define regSDMA0_STATUS3_REG_BASE_IDX 0 -#define regSDMA0_PHYSICAL_ADDR_LO 0x004d -#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_PHYSICAL_ADDR_HI 0x004e -#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_GLOBAL_QUANTUM 0x004f -#define regSDMA0_GLOBAL_QUANTUM_BASE_IDX 0 -#define regSDMA0_ERROR_LOG 0x0050 -#define regSDMA0_ERROR_LOG_BASE_IDX 0 -#define regSDMA0_PUB_DUMMY_REG0 0x0051 -#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 -#define regSDMA0_PUB_DUMMY_REG1 0x0052 -#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 -#define regSDMA0_PUB_DUMMY_REG2 0x0053 -#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 -#define regSDMA0_PUB_DUMMY_REG3 0x0054 -#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 -#define regSDMA0_F32_COUNTER 0x0055 -#define regSDMA0_F32_COUNTER_BASE_IDX 0 -#define regSDMA0_CRD_CNTL 0x005b -#define regSDMA0_CRD_CNTL_BASE_IDX 0 -#define regSDMA0_RLC_CGCG_CTRL 0x005c -#define regSDMA0_RLC_CGCG_CTRL_BASE_IDX 0 -#define regSDMA0_AQL_STATUS 0x005f -#define regSDMA0_AQL_STATUS_BASE_IDX 0 -#define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 -#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 -#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define regSDMA0_TLBI_GCR_CNTL 0x0062 -#define regSDMA0_TLBI_GCR_CNTL_BASE_IDX 0 -#define regSDMA0_TILING_CONFIG 0x0063 -#define regSDMA0_TILING_CONFIG_BASE_IDX 0 -#define regSDMA0_INT_STATUS 0x0070 -#define regSDMA0_INT_STATUS_BASE_IDX 0 -#define regSDMA0_HOLE_ADDR_LO 0x0072 -#define regSDMA0_HOLE_ADDR_LO_BASE_IDX 0 -#define regSDMA0_HOLE_ADDR_HI 0x0073 -#define regSDMA0_HOLE_ADDR_HI_BASE_IDX 0 -#define regSDMA0_CLOCK_GATING_STATUS 0x0075 -#define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX 0 -#define regSDMA0_STATUS4_REG 0x0076 -#define regSDMA0_STATUS4_REG_BASE_IDX 0 -#define regSDMA0_SCRATCH_RAM_DATA 0x0077 -#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 -#define regSDMA0_SCRATCH_RAM_ADDR 0x0078 -#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 -#define regSDMA0_TIMESTAMP_CNTL 0x0079 -#define regSDMA0_TIMESTAMP_CNTL_BASE_IDX 0 -#define regSDMA0_STATUS5_REG 0x007a -#define regSDMA0_STATUS5_REG_BASE_IDX 0 -#define regSDMA0_QUEUE_RESET_REQ 0x007b -#define regSDMA0_QUEUE_RESET_REQ_BASE_IDX 0 -#define regSDMA0_STATUS6_REG 0x007c -#define regSDMA0_STATUS6_REG_BASE_IDX 0 -#define regSDMA0_UCODE1_CHECKSUM 0x007d -#define regSDMA0_UCODE1_CHECKSUM_BASE_IDX 0 -#define regSDMA0_CE_CTRL 0x007e -#define regSDMA0_CE_CTRL_BASE_IDX 0 -#define regSDMA0_FED_STATUS 0x007f -#define regSDMA0_FED_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_CNTL 0x0080 -#define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_BASE 0x0081 -#define regSDMA0_QUEUE0_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_BASE_HI 0x0082 -#define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_RPTR 0x0083 -#define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_RPTR_HI 0x0084 -#define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_WPTR 0x0085 -#define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_WPTR_HI 0x0086 -#define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI 0x0088 -#define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO 0x0089 -#define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_CNTL 0x008a -#define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_RPTR 0x008b -#define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_OFFSET 0x008c -#define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_BASE_LO 0x008d -#define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_BASE_HI 0x008e -#define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_SIZE 0x008f -#define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE0_SKIP_CNTL 0x0090 -#define regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE0_CONTEXT_STATUS 0x0091 -#define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE0_DOORBELL 0x0092 -#define regSDMA0_QUEUE0_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE0_DOORBELL_LOG 0x00a9 -#define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE0_DOORBELL_OFFSET 0x00ab -#define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE0_CSA_ADDR_LO 0x00ac -#define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE0_CSA_ADDR_HI 0x00ad -#define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_SCHEDULE_CNTL 0x00ae -#define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE0_IB_SUB_REMAIN 0x00af -#define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE0_PREEMPT 0x00b0 -#define regSDMA0_QUEUE0_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE0_DUMMY_REG 0x00b1 -#define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_AQL_CNTL 0x00b4 -#define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE 0x00b5 -#define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE0_RB_PREEMPT 0x00b6 -#define regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0 -#define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA1 0x00c1 -#define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA2 0x00c2 -#define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA3 0x00c3 -#define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA4 0x00c4 -#define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA5 0x00c5 -#define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA6 0x00c6 -#define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA7 0x00c7 -#define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA8 0x00c8 -#define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA9 0x00c9 -#define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_DATA10 0x00ca -#define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb -#define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_CNTL 0x00d8 -#define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_BASE 0x00d9 -#define regSDMA0_QUEUE1_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_BASE_HI 0x00da -#define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_RPTR 0x00db -#define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_RPTR_HI 0x00dc -#define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_WPTR 0x00dd -#define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_WPTR_HI 0x00de -#define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 -#define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 -#define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_CNTL 0x00e2 -#define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_RPTR 0x00e3 -#define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_OFFSET 0x00e4 -#define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_BASE_LO 0x00e5 -#define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_BASE_HI 0x00e6 -#define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_SIZE 0x00e7 -#define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE1_SKIP_CNTL 0x00e8 -#define regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_CONTEXT_STATUS 0x00e9 -#define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE1_DOORBELL 0x00ea -#define regSDMA0_QUEUE1_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE1_DOORBELL_LOG 0x0101 -#define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE1_DOORBELL_OFFSET 0x0103 -#define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE1_CSA_ADDR_LO 0x0104 -#define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE1_CSA_ADDR_HI 0x0105 -#define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_SCHEDULE_CNTL 0x0106 -#define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_IB_SUB_REMAIN 0x0107 -#define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE1_PREEMPT 0x0108 -#define regSDMA0_QUEUE1_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE1_DUMMY_REG 0x0109 -#define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a -#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b -#define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_AQL_CNTL 0x010c -#define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE 0x010d -#define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE1_RB_PREEMPT 0x010e -#define regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA0 0x0118 -#define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA1 0x0119 -#define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA2 0x011a -#define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA3 0x011b -#define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA4 0x011c -#define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA5 0x011d -#define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA6 0x011e -#define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA7 0x011f -#define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA8 0x0120 -#define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA9 0x0121 -#define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_DATA10 0x0122 -#define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE1_MIDCMD_CNTL 0x0123 -#define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_CNTL 0x0130 -#define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_BASE 0x0131 -#define regSDMA0_QUEUE2_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_BASE_HI 0x0132 -#define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_RPTR 0x0133 -#define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_RPTR_HI 0x0134 -#define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_WPTR 0x0135 -#define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_WPTR_HI 0x0136 -#define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI 0x0138 -#define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO 0x0139 -#define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_CNTL 0x013a -#define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_RPTR 0x013b -#define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_OFFSET 0x013c -#define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_BASE_LO 0x013d -#define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_BASE_HI 0x013e -#define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_SIZE 0x013f -#define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE2_SKIP_CNTL 0x0140 -#define regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_CONTEXT_STATUS 0x0141 -#define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE2_DOORBELL 0x0142 -#define regSDMA0_QUEUE2_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE2_DOORBELL_LOG 0x0159 -#define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE2_DOORBELL_OFFSET 0x015b -#define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE2_CSA_ADDR_LO 0x015c -#define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE2_CSA_ADDR_HI 0x015d -#define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_SCHEDULE_CNTL 0x015e -#define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_IB_SUB_REMAIN 0x015f -#define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE2_PREEMPT 0x0160 -#define regSDMA0_QUEUE2_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE2_DUMMY_REG 0x0161 -#define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0162 -#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0163 -#define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_AQL_CNTL 0x0164 -#define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE 0x0165 -#define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE2_RB_PREEMPT 0x0166 -#define regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA0 0x0170 -#define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA1 0x0171 -#define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA2 0x0172 -#define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA3 0x0173 -#define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA4 0x0174 -#define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA5 0x0175 -#define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA6 0x0176 -#define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA7 0x0177 -#define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA8 0x0178 -#define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA9 0x0179 -#define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_DATA10 0x017a -#define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE2_MIDCMD_CNTL 0x017b -#define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_CNTL 0x0188 -#define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_BASE 0x0189 -#define regSDMA0_QUEUE3_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_BASE_HI 0x018a -#define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_RPTR 0x018b -#define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_RPTR_HI 0x018c -#define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_WPTR 0x018d -#define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_WPTR_HI 0x018e -#define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI 0x0190 -#define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO 0x0191 -#define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_CNTL 0x0192 -#define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_RPTR 0x0193 -#define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_OFFSET 0x0194 -#define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_BASE_LO 0x0195 -#define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_BASE_HI 0x0196 -#define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_SIZE 0x0197 -#define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE3_SKIP_CNTL 0x0198 -#define regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_CONTEXT_STATUS 0x0199 -#define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE3_DOORBELL 0x019a -#define regSDMA0_QUEUE3_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE3_DOORBELL_LOG 0x01b1 -#define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE3_DOORBELL_OFFSET 0x01b3 -#define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE3_CSA_ADDR_LO 0x01b4 -#define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE3_CSA_ADDR_HI 0x01b5 -#define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_SCHEDULE_CNTL 0x01b6 -#define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_IB_SUB_REMAIN 0x01b7 -#define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE3_PREEMPT 0x01b8 -#define regSDMA0_QUEUE3_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE3_DUMMY_REG 0x01b9 -#define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x01ba -#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x01bb -#define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_AQL_CNTL 0x01bc -#define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE 0x01bd -#define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE3_RB_PREEMPT 0x01be -#define regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA0 0x01c8 -#define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA1 0x01c9 -#define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA2 0x01ca -#define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA3 0x01cb -#define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA4 0x01cc -#define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA5 0x01cd -#define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA6 0x01ce -#define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA7 0x01cf -#define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA8 0x01d0 -#define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA9 0x01d1 -#define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_DATA10 0x01d2 -#define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE3_MIDCMD_CNTL 0x01d3 -#define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_CNTL 0x01e0 -#define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_BASE 0x01e1 -#define regSDMA0_QUEUE4_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_BASE_HI 0x01e2 -#define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_RPTR 0x01e3 -#define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_RPTR_HI 0x01e4 -#define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_WPTR 0x01e5 -#define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_WPTR_HI 0x01e6 -#define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI 0x01e8 -#define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO 0x01e9 -#define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_CNTL 0x01ea -#define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_RPTR 0x01eb -#define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_OFFSET 0x01ec -#define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_BASE_LO 0x01ed -#define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_BASE_HI 0x01ee -#define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_SIZE 0x01ef -#define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE4_SKIP_CNTL 0x01f0 -#define regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_CONTEXT_STATUS 0x01f1 -#define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE4_DOORBELL 0x01f2 -#define regSDMA0_QUEUE4_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE4_DOORBELL_LOG 0x0209 -#define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE4_DOORBELL_OFFSET 0x020b -#define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE4_CSA_ADDR_LO 0x020c -#define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE4_CSA_ADDR_HI 0x020d -#define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_SCHEDULE_CNTL 0x020e -#define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_IB_SUB_REMAIN 0x020f -#define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE4_PREEMPT 0x0210 -#define regSDMA0_QUEUE4_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE4_DUMMY_REG 0x0211 -#define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0212 -#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0213 -#define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_AQL_CNTL 0x0214 -#define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE 0x0215 -#define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE4_RB_PREEMPT 0x0216 -#define regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA0 0x0220 -#define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA1 0x0221 -#define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA2 0x0222 -#define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA3 0x0223 -#define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA4 0x0224 -#define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA5 0x0225 -#define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA6 0x0226 -#define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA7 0x0227 -#define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA8 0x0228 -#define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA9 0x0229 -#define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_DATA10 0x022a -#define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE4_MIDCMD_CNTL 0x022b -#define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_CNTL 0x0238 -#define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_BASE 0x0239 -#define regSDMA0_QUEUE5_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_BASE_HI 0x023a -#define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_RPTR 0x023b -#define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_RPTR_HI 0x023c -#define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_WPTR 0x023d -#define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_WPTR_HI 0x023e -#define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI 0x0240 -#define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO 0x0241 -#define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_CNTL 0x0242 -#define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_RPTR 0x0243 -#define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_OFFSET 0x0244 -#define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_BASE_LO 0x0245 -#define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_BASE_HI 0x0246 -#define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_SIZE 0x0247 -#define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE5_SKIP_CNTL 0x0248 -#define regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_CONTEXT_STATUS 0x0249 -#define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE5_DOORBELL 0x024a -#define regSDMA0_QUEUE5_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE5_DOORBELL_LOG 0x0261 -#define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE5_DOORBELL_OFFSET 0x0263 -#define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE5_CSA_ADDR_LO 0x0264 -#define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE5_CSA_ADDR_HI 0x0265 -#define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_SCHEDULE_CNTL 0x0266 -#define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_IB_SUB_REMAIN 0x0267 -#define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE5_PREEMPT 0x0268 -#define regSDMA0_QUEUE5_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE5_DUMMY_REG 0x0269 -#define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x026a -#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x026b -#define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_AQL_CNTL 0x026c -#define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE 0x026d -#define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE5_RB_PREEMPT 0x026e -#define regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA0 0x0278 -#define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA1 0x0279 -#define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA2 0x027a -#define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA3 0x027b -#define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA4 0x027c -#define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA5 0x027d -#define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA6 0x027e -#define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA7 0x027f -#define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA8 0x0280 -#define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA9 0x0281 -#define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_DATA10 0x0282 -#define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE5_MIDCMD_CNTL 0x0283 -#define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_CNTL 0x0290 -#define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_BASE 0x0291 -#define regSDMA0_QUEUE6_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_BASE_HI 0x0292 -#define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_RPTR 0x0293 -#define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_RPTR_HI 0x0294 -#define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_WPTR 0x0295 -#define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_WPTR_HI 0x0296 -#define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI 0x0298 -#define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO 0x0299 -#define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_CNTL 0x029a -#define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_RPTR 0x029b -#define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_OFFSET 0x029c -#define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_BASE_LO 0x029d -#define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_BASE_HI 0x029e -#define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_SIZE 0x029f -#define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE6_SKIP_CNTL 0x02a0 -#define regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_CONTEXT_STATUS 0x02a1 -#define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE6_DOORBELL 0x02a2 -#define regSDMA0_QUEUE6_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE6_DOORBELL_LOG 0x02b9 -#define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE6_DOORBELL_OFFSET 0x02bb -#define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE6_CSA_ADDR_LO 0x02bc -#define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE6_CSA_ADDR_HI 0x02bd -#define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_SCHEDULE_CNTL 0x02be -#define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_IB_SUB_REMAIN 0x02bf -#define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE6_PREEMPT 0x02c0 -#define regSDMA0_QUEUE6_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE6_DUMMY_REG 0x02c1 -#define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x02c2 -#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x02c3 -#define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_AQL_CNTL 0x02c4 -#define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE 0x02c5 -#define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE6_RB_PREEMPT 0x02c6 -#define regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA0 0x02d0 -#define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA1 0x02d1 -#define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA2 0x02d2 -#define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA3 0x02d3 -#define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA4 0x02d4 -#define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA5 0x02d5 -#define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA6 0x02d6 -#define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA7 0x02d7 -#define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA8 0x02d8 -#define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA9 0x02d9 -#define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_DATA10 0x02da -#define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE6_MIDCMD_CNTL 0x02db -#define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_CNTL 0x02e8 -#define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_BASE 0x02e9 -#define regSDMA0_QUEUE7_RB_BASE_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_BASE_HI 0x02ea -#define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_RPTR 0x02eb -#define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_RPTR_HI 0x02ec -#define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_WPTR 0x02ed -#define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_WPTR_HI 0x02ee -#define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI 0x02f0 -#define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO 0x02f1 -#define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_CNTL 0x02f2 -#define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_RPTR 0x02f3 -#define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_OFFSET 0x02f4 -#define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_BASE_LO 0x02f5 -#define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_BASE_HI 0x02f6 -#define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_SIZE 0x02f7 -#define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX 0 -#define regSDMA0_QUEUE7_SKIP_CNTL 0x02f8 -#define regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_CONTEXT_STATUS 0x02f9 -#define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA0_QUEUE7_DOORBELL 0x02fa -#define regSDMA0_QUEUE7_DOORBELL_BASE_IDX 0 -#define regSDMA0_QUEUE7_DOORBELL_LOG 0x0311 -#define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA0_QUEUE7_DOORBELL_OFFSET 0x0313 -#define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA0_QUEUE7_CSA_ADDR_LO 0x0314 -#define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE7_CSA_ADDR_HI 0x0315 -#define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_SCHEDULE_CNTL 0x0316 -#define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_IB_SUB_REMAIN 0x0317 -#define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA0_QUEUE7_PREEMPT 0x0318 -#define regSDMA0_QUEUE7_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE7_DUMMY_REG 0x0319 -#define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x031a -#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x031b -#define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_AQL_CNTL 0x031c -#define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE 0x031d -#define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA0_QUEUE7_RB_PREEMPT 0x031e -#define regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA0 0x0328 -#define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA1 0x0329 -#define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA2 0x032a -#define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA3 0x032b -#define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA4 0x032c -#define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA5 0x032d -#define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA6 0x032e -#define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA7 0x032f -#define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA8 0x0330 -#define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA9 0x0331 -#define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_DATA10 0x0332 -#define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA0_QUEUE7_MIDCMD_CNTL 0x0333 -#define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 - - -// addressBlock: gc_sdma0_sdma1dec -// base address: 0x6180 -#define regSDMA1_DEC_START 0x0600 -#define regSDMA1_DEC_START_BASE_IDX 0 -#define regSDMA1_F32_MISC_CNTL 0x060b -#define regSDMA1_F32_MISC_CNTL_BASE_IDX 0 -#define regSDMA1_GLOBAL_TIMESTAMP_LO 0x060f -#define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 -#define regSDMA1_GLOBAL_TIMESTAMP_HI 0x0610 -#define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 -#define regSDMA1_POWER_CNTL 0x061a -#define regSDMA1_POWER_CNTL_BASE_IDX 0 -#define regSDMA1_CNTL 0x061c -#define regSDMA1_CNTL_BASE_IDX 0 -#define regSDMA1_CHICKEN_BITS 0x061d -#define regSDMA1_CHICKEN_BITS_BASE_IDX 0 -#define regSDMA1_GB_ADDR_CONFIG 0x061e -#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 -#define regSDMA1_GB_ADDR_CONFIG_READ 0x061f -#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define regSDMA1_RB_RPTR_FETCH 0x0620 -#define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 -#define regSDMA1_RB_RPTR_FETCH_HI 0x0621 -#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0622 -#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define regSDMA1_IB_OFFSET_FETCH 0x0623 -#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 -#define regSDMA1_PROGRAM 0x0624 -#define regSDMA1_PROGRAM_BASE_IDX 0 -#define regSDMA1_STATUS_REG 0x0625 -#define regSDMA1_STATUS_REG_BASE_IDX 0 -#define regSDMA1_STATUS1_REG 0x0626 -#define regSDMA1_STATUS1_REG_BASE_IDX 0 -#define regSDMA1_CNTL1 0x0627 -#define regSDMA1_CNTL1_BASE_IDX 0 -#define regSDMA1_HBM_PAGE_CONFIG 0x0628 -#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 -#define regSDMA1_UCODE_CHECKSUM 0x0629 -#define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 -#define regSDMA1_FREEZE 0x062b -#define regSDMA1_FREEZE_BASE_IDX 0 -#define regSDMA1_PROCESS_QUANTUM0 0x062c -#define regSDMA1_PROCESS_QUANTUM0_BASE_IDX 0 -#define regSDMA1_PROCESS_QUANTUM1 0x062d -#define regSDMA1_PROCESS_QUANTUM1_BASE_IDX 0 -#define regSDMA1_WATCHDOG_CNTL 0x062e -#define regSDMA1_WATCHDOG_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE_STATUS0 0x062f -#define regSDMA1_QUEUE_STATUS0_BASE_IDX 0 -#define regSDMA1_EDC_CONFIG 0x0632 -#define regSDMA1_EDC_CONFIG_BASE_IDX 0 -#define regSDMA1_BA_THRESHOLD 0x0633 -#define regSDMA1_BA_THRESHOLD_BASE_IDX 0 -#define regSDMA1_ID 0x0634 -#define regSDMA1_ID_BASE_IDX 0 -#define regSDMA1_VERSION 0x0635 -#define regSDMA1_VERSION_BASE_IDX 0 -#define regSDMA1_EDC_COUNTER 0x0636 -#define regSDMA1_EDC_COUNTER_BASE_IDX 0 -#define regSDMA1_EDC_COUNTER_CLEAR 0x0637 -#define regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define regSDMA1_STATUS2_REG 0x0638 -#define regSDMA1_STATUS2_REG_BASE_IDX 0 -#define regSDMA1_ATOMIC_CNTL 0x0639 -#define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 -#define regSDMA1_ATOMIC_PREOP_LO 0x063a -#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 -#define regSDMA1_ATOMIC_PREOP_HI 0x063b -#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 -#define regSDMA1_UTCL1_CNTL 0x063c -#define regSDMA1_UTCL1_CNTL_BASE_IDX 0 -#define regSDMA1_UTCL1_WATERMK 0x063d -#define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 -#define regSDMA1_UTCL1_TIMEOUT 0x063e -#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 -#define regSDMA1_UTCL1_PAGE 0x063f -#define regSDMA1_UTCL1_PAGE_BASE_IDX 0 -#define regSDMA1_UTCL1_RD_STATUS 0x0640 -#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 -#define regSDMA1_UTCL1_WR_STATUS 0x0641 -#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 -#define regSDMA1_UTCL1_INV0 0x0642 -#define regSDMA1_UTCL1_INV0_BASE_IDX 0 -#define regSDMA1_UTCL1_INV1 0x0643 -#define regSDMA1_UTCL1_INV1_BASE_IDX 0 -#define regSDMA1_UTCL1_INV2 0x0644 -#define regSDMA1_UTCL1_INV2_BASE_IDX 0 -#define regSDMA1_UTCL1_RD_XNACK0 0x0645 -#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 -#define regSDMA1_UTCL1_RD_XNACK1 0x0646 -#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 -#define regSDMA1_UTCL1_WR_XNACK0 0x0647 -#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 -#define regSDMA1_UTCL1_WR_XNACK1 0x0648 -#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 -#define regSDMA1_RELAX_ORDERING_LUT 0x064a -#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 -#define regSDMA1_CHICKEN_BITS_2 0x064b -#define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 -#define regSDMA1_STATUS3_REG 0x064c -#define regSDMA1_STATUS3_REG_BASE_IDX 0 -#define regSDMA1_PHYSICAL_ADDR_LO 0x064d -#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_PHYSICAL_ADDR_HI 0x064e -#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_GLOBAL_QUANTUM 0x064f -#define regSDMA1_GLOBAL_QUANTUM_BASE_IDX 0 -#define regSDMA1_ERROR_LOG 0x0650 -#define regSDMA1_ERROR_LOG_BASE_IDX 0 -#define regSDMA1_PUB_DUMMY_REG0 0x0651 -#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 -#define regSDMA1_PUB_DUMMY_REG1 0x0652 -#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 -#define regSDMA1_PUB_DUMMY_REG2 0x0653 -#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 -#define regSDMA1_PUB_DUMMY_REG3 0x0654 -#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 -#define regSDMA1_F32_COUNTER 0x0655 -#define regSDMA1_F32_COUNTER_BASE_IDX 0 -#define regSDMA1_CRD_CNTL 0x065b -#define regSDMA1_CRD_CNTL_BASE_IDX 0 -#define regSDMA1_RLC_CGCG_CTRL 0x065c -#define regSDMA1_RLC_CGCG_CTRL_BASE_IDX 0 -#define regSDMA1_AQL_STATUS 0x065f -#define regSDMA1_AQL_STATUS_BASE_IDX 0 -#define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 -#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 -#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define regSDMA1_TLBI_GCR_CNTL 0x0662 -#define regSDMA1_TLBI_GCR_CNTL_BASE_IDX 0 -#define regSDMA1_TILING_CONFIG 0x0663 -#define regSDMA1_TILING_CONFIG_BASE_IDX 0 -#define regSDMA1_INT_STATUS 0x0670 -#define regSDMA1_INT_STATUS_BASE_IDX 0 -#define regSDMA1_HOLE_ADDR_LO 0x0672 -#define regSDMA1_HOLE_ADDR_LO_BASE_IDX 0 -#define regSDMA1_HOLE_ADDR_HI 0x0673 -#define regSDMA1_HOLE_ADDR_HI_BASE_IDX 0 -#define regSDMA1_CLOCK_GATING_STATUS 0x0675 -#define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX 0 -#define regSDMA1_STATUS4_REG 0x0676 -#define regSDMA1_STATUS4_REG_BASE_IDX 0 -#define regSDMA1_SCRATCH_RAM_DATA 0x0677 -#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 -#define regSDMA1_SCRATCH_RAM_ADDR 0x0678 -#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 -#define regSDMA1_TIMESTAMP_CNTL 0x0679 -#define regSDMA1_TIMESTAMP_CNTL_BASE_IDX 0 -#define regSDMA1_STATUS5_REG 0x067a -#define regSDMA1_STATUS5_REG_BASE_IDX 0 -#define regSDMA1_QUEUE_RESET_REQ 0x067b -#define regSDMA1_QUEUE_RESET_REQ_BASE_IDX 0 -#define regSDMA1_STATUS6_REG 0x067c -#define regSDMA1_STATUS6_REG_BASE_IDX 0 -#define regSDMA1_UCODE1_CHECKSUM 0x067d -#define regSDMA1_UCODE1_CHECKSUM_BASE_IDX 0 -#define regSDMA1_CE_CTRL 0x067e -#define regSDMA1_CE_CTRL_BASE_IDX 0 -#define regSDMA1_FED_STATUS 0x067f -#define regSDMA1_FED_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_CNTL 0x0680 -#define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_BASE 0x0681 -#define regSDMA1_QUEUE0_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_BASE_HI 0x0682 -#define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_RPTR 0x0683 -#define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_RPTR_HI 0x0684 -#define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_WPTR 0x0685 -#define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_WPTR_HI 0x0686 -#define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI 0x0688 -#define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO 0x0689 -#define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_CNTL 0x068a -#define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_RPTR 0x068b -#define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_OFFSET 0x068c -#define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_BASE_LO 0x068d -#define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_BASE_HI 0x068e -#define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_SIZE 0x068f -#define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE0_SKIP_CNTL 0x0690 -#define regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE0_CONTEXT_STATUS 0x0691 -#define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE0_DOORBELL 0x0692 -#define regSDMA1_QUEUE0_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE0_DOORBELL_LOG 0x06a9 -#define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE0_DOORBELL_OFFSET 0x06ab -#define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE0_CSA_ADDR_LO 0x06ac -#define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE0_CSA_ADDR_HI 0x06ad -#define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_SCHEDULE_CNTL 0x06ae -#define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE0_IB_SUB_REMAIN 0x06af -#define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE0_PREEMPT 0x06b0 -#define regSDMA1_QUEUE0_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE0_DUMMY_REG 0x06b1 -#define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x06b2 -#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x06b3 -#define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_AQL_CNTL 0x06b4 -#define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE 0x06b5 -#define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE0_RB_PREEMPT 0x06b6 -#define regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA0 0x06c0 -#define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA1 0x06c1 -#define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA2 0x06c2 -#define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA3 0x06c3 -#define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA4 0x06c4 -#define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA5 0x06c5 -#define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA6 0x06c6 -#define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA7 0x06c7 -#define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA8 0x06c8 -#define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA9 0x06c9 -#define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_DATA10 0x06ca -#define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE0_MIDCMD_CNTL 0x06cb -#define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_CNTL 0x06d8 -#define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_BASE 0x06d9 -#define regSDMA1_QUEUE1_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_BASE_HI 0x06da -#define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_RPTR 0x06db -#define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_RPTR_HI 0x06dc -#define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_WPTR 0x06dd -#define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_WPTR_HI 0x06de -#define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI 0x06e0 -#define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO 0x06e1 -#define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_CNTL 0x06e2 -#define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_RPTR 0x06e3 -#define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_OFFSET 0x06e4 -#define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_BASE_LO 0x06e5 -#define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_BASE_HI 0x06e6 -#define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_SIZE 0x06e7 -#define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE1_SKIP_CNTL 0x06e8 -#define regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_CONTEXT_STATUS 0x06e9 -#define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE1_DOORBELL 0x06ea -#define regSDMA1_QUEUE1_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE1_DOORBELL_LOG 0x0701 -#define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE1_DOORBELL_OFFSET 0x0703 -#define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE1_CSA_ADDR_LO 0x0704 -#define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE1_CSA_ADDR_HI 0x0705 -#define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_SCHEDULE_CNTL 0x0706 -#define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_IB_SUB_REMAIN 0x0707 -#define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE1_PREEMPT 0x0708 -#define regSDMA1_QUEUE1_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE1_DUMMY_REG 0x0709 -#define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x070a -#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x070b -#define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_AQL_CNTL 0x070c -#define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE 0x070d -#define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE1_RB_PREEMPT 0x070e -#define regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA0 0x0718 -#define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA1 0x0719 -#define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA2 0x071a -#define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA3 0x071b -#define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA4 0x071c -#define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA5 0x071d -#define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA6 0x071e -#define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA7 0x071f -#define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA8 0x0720 -#define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA9 0x0721 -#define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_DATA10 0x0722 -#define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE1_MIDCMD_CNTL 0x0723 -#define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_CNTL 0x0730 -#define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_BASE 0x0731 -#define regSDMA1_QUEUE2_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_BASE_HI 0x0732 -#define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_RPTR 0x0733 -#define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_RPTR_HI 0x0734 -#define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_WPTR 0x0735 -#define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_WPTR_HI 0x0736 -#define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI 0x0738 -#define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO 0x0739 -#define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_CNTL 0x073a -#define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_RPTR 0x073b -#define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_OFFSET 0x073c -#define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_BASE_LO 0x073d -#define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_BASE_HI 0x073e -#define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_SIZE 0x073f -#define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE2_SKIP_CNTL 0x0740 -#define regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_CONTEXT_STATUS 0x0741 -#define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE2_DOORBELL 0x0742 -#define regSDMA1_QUEUE2_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE2_DOORBELL_LOG 0x0759 -#define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE2_DOORBELL_OFFSET 0x075b -#define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE2_CSA_ADDR_LO 0x075c -#define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE2_CSA_ADDR_HI 0x075d -#define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_SCHEDULE_CNTL 0x075e -#define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_IB_SUB_REMAIN 0x075f -#define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE2_PREEMPT 0x0760 -#define regSDMA1_QUEUE2_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE2_DUMMY_REG 0x0761 -#define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0762 -#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0763 -#define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_AQL_CNTL 0x0764 -#define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE 0x0765 -#define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE2_RB_PREEMPT 0x0766 -#define regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA0 0x0770 -#define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA1 0x0771 -#define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA2 0x0772 -#define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA3 0x0773 -#define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA4 0x0774 -#define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA5 0x0775 -#define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA6 0x0776 -#define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA7 0x0777 -#define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA8 0x0778 -#define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA9 0x0779 -#define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_DATA10 0x077a -#define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE2_MIDCMD_CNTL 0x077b -#define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_CNTL 0x0788 -#define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_BASE 0x0789 -#define regSDMA1_QUEUE3_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_BASE_HI 0x078a -#define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_RPTR 0x078b -#define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_RPTR_HI 0x078c -#define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_WPTR 0x078d -#define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_WPTR_HI 0x078e -#define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI 0x0790 -#define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO 0x0791 -#define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_CNTL 0x0792 -#define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_RPTR 0x0793 -#define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_OFFSET 0x0794 -#define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_BASE_LO 0x0795 -#define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_BASE_HI 0x0796 -#define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_SIZE 0x0797 -#define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE3_SKIP_CNTL 0x0798 -#define regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_CONTEXT_STATUS 0x0799 -#define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE3_DOORBELL 0x079a -#define regSDMA1_QUEUE3_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE3_DOORBELL_LOG 0x07b1 -#define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE3_DOORBELL_OFFSET 0x07b3 -#define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE3_CSA_ADDR_LO 0x07b4 -#define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE3_CSA_ADDR_HI 0x07b5 -#define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_SCHEDULE_CNTL 0x07b6 -#define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_IB_SUB_REMAIN 0x07b7 -#define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE3_PREEMPT 0x07b8 -#define regSDMA1_QUEUE3_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE3_DUMMY_REG 0x07b9 -#define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x07ba -#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x07bb -#define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_AQL_CNTL 0x07bc -#define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE 0x07bd -#define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE3_RB_PREEMPT 0x07be -#define regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA0 0x07c8 -#define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA1 0x07c9 -#define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA2 0x07ca -#define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA3 0x07cb -#define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA4 0x07cc -#define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA5 0x07cd -#define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA6 0x07ce -#define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA7 0x07cf -#define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA8 0x07d0 -#define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA9 0x07d1 -#define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_DATA10 0x07d2 -#define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE3_MIDCMD_CNTL 0x07d3 -#define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_CNTL 0x07e0 -#define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_BASE 0x07e1 -#define regSDMA1_QUEUE4_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_BASE_HI 0x07e2 -#define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_RPTR 0x07e3 -#define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_RPTR_HI 0x07e4 -#define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_WPTR 0x07e5 -#define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_WPTR_HI 0x07e6 -#define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI 0x07e8 -#define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO 0x07e9 -#define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_CNTL 0x07ea -#define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_RPTR 0x07eb -#define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_OFFSET 0x07ec -#define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_BASE_LO 0x07ed -#define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_BASE_HI 0x07ee -#define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_SIZE 0x07ef -#define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE4_SKIP_CNTL 0x07f0 -#define regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_CONTEXT_STATUS 0x07f1 -#define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE4_DOORBELL 0x07f2 -#define regSDMA1_QUEUE4_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE4_DOORBELL_LOG 0x0809 -#define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE4_DOORBELL_OFFSET 0x080b -#define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE4_CSA_ADDR_LO 0x080c -#define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE4_CSA_ADDR_HI 0x080d -#define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_SCHEDULE_CNTL 0x080e -#define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_IB_SUB_REMAIN 0x080f -#define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE4_PREEMPT 0x0810 -#define regSDMA1_QUEUE4_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE4_DUMMY_REG 0x0811 -#define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0812 -#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0813 -#define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_AQL_CNTL 0x0814 -#define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE 0x0815 -#define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE4_RB_PREEMPT 0x0816 -#define regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA0 0x0820 -#define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA1 0x0821 -#define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA2 0x0822 -#define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA3 0x0823 -#define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA4 0x0824 -#define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA5 0x0825 -#define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA6 0x0826 -#define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA7 0x0827 -#define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA8 0x0828 -#define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA9 0x0829 -#define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_DATA10 0x082a -#define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE4_MIDCMD_CNTL 0x082b -#define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_CNTL 0x0838 -#define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_BASE 0x0839 -#define regSDMA1_QUEUE5_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_BASE_HI 0x083a -#define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_RPTR 0x083b -#define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_RPTR_HI 0x083c -#define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_WPTR 0x083d -#define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_WPTR_HI 0x083e -#define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI 0x0840 -#define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO 0x0841 -#define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_CNTL 0x0842 -#define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_RPTR 0x0843 -#define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_OFFSET 0x0844 -#define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_BASE_LO 0x0845 -#define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_BASE_HI 0x0846 -#define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_SIZE 0x0847 -#define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE5_SKIP_CNTL 0x0848 -#define regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_CONTEXT_STATUS 0x0849 -#define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE5_DOORBELL 0x084a -#define regSDMA1_QUEUE5_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE5_DOORBELL_LOG 0x0861 -#define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE5_DOORBELL_OFFSET 0x0863 -#define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE5_CSA_ADDR_LO 0x0864 -#define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE5_CSA_ADDR_HI 0x0865 -#define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_SCHEDULE_CNTL 0x0866 -#define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_IB_SUB_REMAIN 0x0867 -#define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE5_PREEMPT 0x0868 -#define regSDMA1_QUEUE5_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE5_DUMMY_REG 0x0869 -#define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x086a -#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x086b -#define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_AQL_CNTL 0x086c -#define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE 0x086d -#define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE5_RB_PREEMPT 0x086e -#define regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA0 0x0878 -#define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA1 0x0879 -#define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA2 0x087a -#define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA3 0x087b -#define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA4 0x087c -#define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA5 0x087d -#define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA6 0x087e -#define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA7 0x087f -#define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA8 0x0880 -#define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA9 0x0881 -#define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_DATA10 0x0882 -#define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE5_MIDCMD_CNTL 0x0883 -#define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_CNTL 0x0890 -#define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_BASE 0x0891 -#define regSDMA1_QUEUE6_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_BASE_HI 0x0892 -#define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_RPTR 0x0893 -#define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_RPTR_HI 0x0894 -#define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_WPTR 0x0895 -#define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_WPTR_HI 0x0896 -#define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI 0x0898 -#define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO 0x0899 -#define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_CNTL 0x089a -#define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_RPTR 0x089b -#define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_OFFSET 0x089c -#define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_BASE_LO 0x089d -#define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_BASE_HI 0x089e -#define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_SIZE 0x089f -#define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE6_SKIP_CNTL 0x08a0 -#define regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_CONTEXT_STATUS 0x08a1 -#define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE6_DOORBELL 0x08a2 -#define regSDMA1_QUEUE6_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE6_DOORBELL_LOG 0x08b9 -#define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE6_DOORBELL_OFFSET 0x08bb -#define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE6_CSA_ADDR_LO 0x08bc -#define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE6_CSA_ADDR_HI 0x08bd -#define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_SCHEDULE_CNTL 0x08be -#define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_IB_SUB_REMAIN 0x08bf -#define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE6_PREEMPT 0x08c0 -#define regSDMA1_QUEUE6_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE6_DUMMY_REG 0x08c1 -#define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x08c2 -#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x08c3 -#define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_AQL_CNTL 0x08c4 -#define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE 0x08c5 -#define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE6_RB_PREEMPT 0x08c6 -#define regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA0 0x08d0 -#define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA1 0x08d1 -#define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA2 0x08d2 -#define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA3 0x08d3 -#define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA4 0x08d4 -#define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA5 0x08d5 -#define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA6 0x08d6 -#define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA7 0x08d7 -#define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA8 0x08d8 -#define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA9 0x08d9 -#define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_DATA10 0x08da -#define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE6_MIDCMD_CNTL 0x08db -#define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_CNTL 0x08e8 -#define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_BASE 0x08e9 -#define regSDMA1_QUEUE7_RB_BASE_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_BASE_HI 0x08ea -#define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_RPTR 0x08eb -#define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_RPTR_HI 0x08ec -#define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_WPTR 0x08ed -#define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_WPTR_HI 0x08ee -#define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI 0x08f0 -#define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO 0x08f1 -#define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_CNTL 0x08f2 -#define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_RPTR 0x08f3 -#define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_OFFSET 0x08f4 -#define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_BASE_LO 0x08f5 -#define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_BASE_HI 0x08f6 -#define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_SIZE 0x08f7 -#define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX 0 -#define regSDMA1_QUEUE7_SKIP_CNTL 0x08f8 -#define regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_CONTEXT_STATUS 0x08f9 -#define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 -#define regSDMA1_QUEUE7_DOORBELL 0x08fa -#define regSDMA1_QUEUE7_DOORBELL_BASE_IDX 0 -#define regSDMA1_QUEUE7_DOORBELL_LOG 0x0911 -#define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX 0 -#define regSDMA1_QUEUE7_DOORBELL_OFFSET 0x0913 -#define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 -#define regSDMA1_QUEUE7_CSA_ADDR_LO 0x0914 -#define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE7_CSA_ADDR_HI 0x0915 -#define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_SCHEDULE_CNTL 0x0916 -#define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_IB_SUB_REMAIN 0x0917 -#define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 -#define regSDMA1_QUEUE7_PREEMPT 0x0918 -#define regSDMA1_QUEUE7_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE7_DUMMY_REG 0x0919 -#define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x091a -#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x091b -#define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_AQL_CNTL 0x091c -#define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 -#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE 0x091d -#define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 -#define regSDMA1_QUEUE7_RB_PREEMPT 0x091e -#define regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA0 0x0928 -#define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA1 0x0929 -#define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA2 0x092a -#define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA3 0x092b -#define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA4 0x092c -#define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA5 0x092d -#define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA6 0x092e -#define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA7 0x092f -#define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA8 0x0930 -#define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA9 0x0931 -#define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_DATA10 0x0932 -#define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 -#define regSDMA1_QUEUE7_MIDCMD_CNTL 0x0933 -#define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 - - -// addressBlock: gc_sdma0_sdma0hypdec -// base address: 0x3e200 -#define regSDMA0_UCODE_ADDR 0x5880 -#define regSDMA0_UCODE_ADDR_BASE_IDX 1 -#define regSDMA0_UCODE_DATA 0x5881 -#define regSDMA0_UCODE_DATA_BASE_IDX 1 -#define regSDMA0_UCODE_SELFLOAD_CONTROL 0x5882 -#define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 -#define regSDMA0_BROADCAST_UCODE_ADDR 0x5886 -#define regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1 -#define regSDMA0_BROADCAST_UCODE_DATA 0x5887 -#define regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1 -#define regSDMA0_F32_CNTL 0x589a -#define regSDMA0_F32_CNTL_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma1hypdec -// base address: 0x3e280 -#define regSDMA1_UCODE_ADDR 0x58a0 -#define regSDMA1_UCODE_ADDR_BASE_IDX 1 -#define regSDMA1_UCODE_DATA 0x58a1 -#define regSDMA1_UCODE_DATA_BASE_IDX 1 -#define regSDMA1_UCODE_SELFLOAD_CONTROL 0x58a2 -#define regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 -#define regSDMA1_BROADCAST_UCODE_ADDR 0x58a6 -#define regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX 1 -#define regSDMA1_BROADCAST_UCODE_DATA 0x58a7 -#define regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX 1 -#define regSDMA1_F32_CNTL 0x58ba -#define regSDMA1_F32_CNTL_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma0perfsdec -// base address: 0x37880 -#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x3e20 -#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x3e21 -#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e22 -#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define regSDMA0_PERFCNT_MISC_CNTL 0x3e23 -#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER0_SELECT 0x3e24 -#define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER0_SELECT1 0x3e25 -#define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER1_SELECT 0x3e26 -#define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER1_SELECT1 0x3e27 -#define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma1perfsdec -// base address: 0x378b0 -#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x3e2c -#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x3e2d -#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e2e -#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define regSDMA1_PERFCNT_MISC_CNTL 0x3e2f -#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER0_SELECT 0x3e30 -#define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER0_SELECT1 0x3e31 -#define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER1_SELECT 0x3e32 -#define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER1_SELECT1 0x3e33 -#define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma0perfddec -// base address: 0x35980 -#define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x3660 -#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x3661 -#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER0_LO 0x3662 -#define regSDMA0_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER0_HI 0x3663 -#define regSDMA0_PERFCOUNTER0_HI_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER1_LO 0x3664 -#define regSDMA0_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSDMA0_PERFCOUNTER1_HI 0x3665 -#define regSDMA0_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_sdma0_sdma1perfddec -// base address: 0x359b0 -#define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x366c -#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 -#define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x366d -#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER0_LO 0x366e -#define regSDMA1_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER0_HI 0x366f -#define regSDMA1_PERFCOUNTER0_HI_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER1_LO 0x3670 -#define regSDMA1_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSDMA1_PERFCOUNTER1_HI 0x3671 -#define regSDMA1_PERFCOUNTER1_HI_BASE_IDX 1 - - -// addressBlock: gc_grbmdec -// base address: 0x8000 -#define regGRBM_CNTL 0x0da0 -#define regGRBM_CNTL_BASE_IDX 0 -#define regGRBM_SKEW_CNTL 0x0da1 -#define regGRBM_SKEW_CNTL_BASE_IDX 0 -#define regGRBM_STATUS2 0x0da2 -#define regGRBM_STATUS2_BASE_IDX 0 -#define regGRBM_PWR_CNTL 0x0da3 -#define regGRBM_PWR_CNTL_BASE_IDX 0 -#define regGRBM_STATUS 0x0da4 -#define regGRBM_STATUS_BASE_IDX 0 -#define regGRBM_STATUS_SE0 0x0da5 -#define regGRBM_STATUS_SE0_BASE_IDX 0 -#define regGRBM_STATUS_SE1 0x0da6 -#define regGRBM_STATUS_SE1_BASE_IDX 0 -#define regGRBM_STATUS3 0x0da7 -#define regGRBM_STATUS3_BASE_IDX 0 -#define regGRBM_SOFT_RESET 0x0da8 -#define regGRBM_SOFT_RESET_BASE_IDX 0 -#define regGRBM_GFX_CLKEN_CNTL 0x0dac -#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 -#define regGRBM_WAIT_IDLE_CLOCKS 0x0dad -#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 -#define regGRBM_STATUS_SE2 0x0dae -#define regGRBM_STATUS_SE2_BASE_IDX 0 -#define regGRBM_STATUS_SE3 0x0daf -#define regGRBM_STATUS_SE3_BASE_IDX 0 -#define regGRBM_STATUS_SE4 0x0db0 -#define regGRBM_STATUS_SE4_BASE_IDX 0 -#define regGRBM_STATUS_SE5 0x0db1 -#define regGRBM_STATUS_SE5_BASE_IDX 0 -#define regGRBM_READ_ERROR 0x0db6 -#define regGRBM_READ_ERROR_BASE_IDX 0 -#define regGRBM_READ_ERROR2 0x0db7 -#define regGRBM_READ_ERROR2_BASE_IDX 0 -#define regGRBM_INT_CNTL 0x0db8 -#define regGRBM_INT_CNTL_BASE_IDX 0 -#define regGRBM_TRAP_OP 0x0db9 -#define regGRBM_TRAP_OP_BASE_IDX 0 -#define regGRBM_TRAP_ADDR 0x0dba -#define regGRBM_TRAP_ADDR_BASE_IDX 0 -#define regGRBM_TRAP_ADDR_MSK 0x0dbb -#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 -#define regGRBM_TRAP_WD 0x0dbc -#define regGRBM_TRAP_WD_BASE_IDX 0 -#define regGRBM_TRAP_WD_MSK 0x0dbd -#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 -#define regGRBM_DSM_BYPASS 0x0dbe -#define regGRBM_DSM_BYPASS_BASE_IDX 0 -#define regGRBM_WRITE_ERROR 0x0dbf -#define regGRBM_WRITE_ERROR_BASE_IDX 0 -#define regGRBM_CHIP_REVISION 0x0dc1 -#define regGRBM_CHIP_REVISION_BASE_IDX 0 -#define regGRBM_IH_CREDIT 0x0dc4 -#define regGRBM_IH_CREDIT_BASE_IDX 0 -#define regGRBM_PWR_CNTL2 0x0dc5 -#define regGRBM_PWR_CNTL2_BASE_IDX 0 -#define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 -#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 -#define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 -#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 -#define regGRBM_INVALID_PIPE 0x0dc9 -#define regGRBM_INVALID_PIPE_BASE_IDX 0 -#define regGRBM_FENCE_RANGE0 0x0dca -#define regGRBM_FENCE_RANGE0_BASE_IDX 0 -#define regGRBM_FENCE_RANGE1 0x0dcb -#define regGRBM_FENCE_RANGE1_BASE_IDX 0 -#define regGRBM_SCRATCH_REG0 0x0de0 -#define regGRBM_SCRATCH_REG0_BASE_IDX 0 -#define regGRBM_SCRATCH_REG1 0x0de1 -#define regGRBM_SCRATCH_REG1_BASE_IDX 0 -#define regGRBM_SCRATCH_REG2 0x0de2 -#define regGRBM_SCRATCH_REG2_BASE_IDX 0 -#define regGRBM_SCRATCH_REG3 0x0de3 -#define regGRBM_SCRATCH_REG3_BASE_IDX 0 -#define regGRBM_SCRATCH_REG4 0x0de4 -#define regGRBM_SCRATCH_REG4_BASE_IDX 0 -#define regGRBM_SCRATCH_REG5 0x0de5 -#define regGRBM_SCRATCH_REG5_BASE_IDX 0 -#define regGRBM_SCRATCH_REG6 0x0de6 -#define regGRBM_SCRATCH_REG6_BASE_IDX 0 -#define regGRBM_SCRATCH_REG7 0x0de7 -#define regGRBM_SCRATCH_REG7_BASE_IDX 0 -#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 -#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 - - -// addressBlock: gc_cpdec -// base address: 0x8200 -#define regCP_CPC_DEBUG_CNTL 0x0e20 -#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 -#define regCP_CPC_DEBUG_DATA 0x0e21 -#define regCP_CPC_DEBUG_DATA_BASE_IDX 0 -#define regCP_CPC_STATUS 0x0e24 -#define regCP_CPC_STATUS_BASE_IDX 0 -#define regCP_CPC_BUSY_STAT 0x0e25 -#define regCP_CPC_BUSY_STAT_BASE_IDX 0 -#define regCP_CPC_STALLED_STAT1 0x0e26 -#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 -#define regCP_CPF_STATUS 0x0e27 -#define regCP_CPF_STATUS_BASE_IDX 0 -#define regCP_CPF_BUSY_STAT 0x0e28 -#define regCP_CPF_BUSY_STAT_BASE_IDX 0 -#define regCP_CPF_STALLED_STAT1 0x0e29 -#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 -#define regCP_CPC_BUSY_STAT2 0x0e2a -#define regCP_CPC_BUSY_STAT2_BASE_IDX 0 -#define regCP_CPC_GRBM_FREE_COUNT 0x0e2b -#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 -#define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c -#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 -#define regCP_MEC_ME1_HEADER_DUMP 0x0e2e -#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 -#define regCP_MEC_ME2_HEADER_DUMP 0x0e2f -#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 -#define regCP_CPC_SCRATCH_INDEX 0x0e30 -#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 -#define regCP_CPC_SCRATCH_DATA 0x0e31 -#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 -#define regCP_CPF_GRBM_FREE_COUNT 0x0e32 -#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 -#define regCP_CPF_BUSY_STAT2 0x0e33 -#define regCP_CPF_BUSY_STAT2_BASE_IDX 0 -#define regCP_CPC_HALT_HYST_COUNT 0x0e47 -#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 -#define regCP_STALLED_STAT3 0x0f3c -#define regCP_STALLED_STAT3_BASE_IDX 0 -#define regCP_STALLED_STAT1 0x0f3d -#define regCP_STALLED_STAT1_BASE_IDX 0 -#define regCP_STALLED_STAT2 0x0f3e -#define regCP_STALLED_STAT2_BASE_IDX 0 -#define regCP_BUSY_STAT 0x0f3f -#define regCP_BUSY_STAT_BASE_IDX 0 -#define regCP_STAT 0x0f40 -#define regCP_STAT_BASE_IDX 0 -#define regCP_ME_HEADER_DUMP 0x0f41 -#define regCP_ME_HEADER_DUMP_BASE_IDX 0 -#define regCP_PFP_HEADER_DUMP 0x0f42 -#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 -#define regCP_GRBM_FREE_COUNT 0x0f43 -#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 -#define regCP_PFP_INSTR_PNTR 0x0f45 -#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 -#define regCP_ME_INSTR_PNTR 0x0f46 -#define regCP_ME_INSTR_PNTR_BASE_IDX 0 -#define regCP_MEC1_INSTR_PNTR 0x0f48 -#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 -#define regCP_MEC2_INSTR_PNTR 0x0f49 -#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 -#define regCP_CSF_STAT 0x0f54 -#define regCP_CSF_STAT_BASE_IDX 0 -#define regCP_CNTX_STAT 0x0f58 -#define regCP_CNTX_STAT_BASE_IDX 0 -#define regCP_ME_PREEMPTION 0x0f59 -#define regCP_ME_PREEMPTION_BASE_IDX 0 -#define regCP_RB1_RPTR 0x0f5f -#define regCP_RB1_RPTR_BASE_IDX 0 -#define regCP_RB0_RPTR 0x0f60 -#define regCP_RB0_RPTR_BASE_IDX 0 -#define regCP_RB_RPTR 0x0f60 -#define regCP_RB_RPTR_BASE_IDX 0 -#define regCP_RB_WPTR_DELAY 0x0f61 -#define regCP_RB_WPTR_DELAY_BASE_IDX 0 -#define regCP_RB_WPTR_POLL_CNTL 0x0f62 -#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define regCP_ROQ1_THRESHOLDS 0x0f75 -#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 -#define regCP_ROQ2_THRESHOLDS 0x0f76 -#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 -#define regCP_STQ_THRESHOLDS 0x0f77 -#define regCP_STQ_THRESHOLDS_BASE_IDX 0 -#define regCP_MEQ_THRESHOLDS 0x0f79 -#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 -#define regCP_ROQ_AVAIL 0x0f7a -#define regCP_ROQ_AVAIL_BASE_IDX 0 -#define regCP_STQ_AVAIL 0x0f7b -#define regCP_STQ_AVAIL_BASE_IDX 0 -#define regCP_ROQ2_AVAIL 0x0f7c -#define regCP_ROQ2_AVAIL_BASE_IDX 0 -#define regCP_MEQ_AVAIL 0x0f7d -#define regCP_MEQ_AVAIL_BASE_IDX 0 -#define regCP_CMD_INDEX 0x0f7e -#define regCP_CMD_INDEX_BASE_IDX 0 -#define regCP_CMD_DATA 0x0f7f -#define regCP_CMD_DATA_BASE_IDX 0 -#define regCP_ROQ_RB_STAT 0x0f80 -#define regCP_ROQ_RB_STAT_BASE_IDX 0 -#define regCP_ROQ_IB1_STAT 0x0f81 -#define regCP_ROQ_IB1_STAT_BASE_IDX 0 -#define regCP_ROQ_IB2_STAT 0x0f82 -#define regCP_ROQ_IB2_STAT_BASE_IDX 0 -#define regCP_STQ_STAT 0x0f83 -#define regCP_STQ_STAT_BASE_IDX 0 -#define regCP_STQ_WR_STAT 0x0f84 -#define regCP_STQ_WR_STAT_BASE_IDX 0 -#define regCP_MEQ_STAT 0x0f85 -#define regCP_MEQ_STAT_BASE_IDX 0 -#define regCP_ROQ3_THRESHOLDS 0x0f8c -#define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 -#define regCP_ROQ_DB_STAT 0x0f8d -#define regCP_ROQ_DB_STAT_BASE_IDX 0 -#define regCP_DEBUG_CNTL 0x0f98 -#define regCP_DEBUG_CNTL_BASE_IDX 0 -#define regCP_DEBUG_DATA 0x0f99 -#define regCP_DEBUG_DATA_BASE_IDX 0 -#define regCP_PRIV_VIOLATION_ADDR 0x0f9a -#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 - - -// addressBlock: gc_padec -// base address: 0x8800 -#define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd -#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 -#define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce -#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 -#define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf -#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 -#define regVGT_MC_LAT_CNTL 0x0fd6 -#define regVGT_MC_LAT_CNTL_BASE_IDX 0 -#define regIA_UTCL1_STATUS_2 0x0fd7 -#define regIA_UTCL1_STATUS_2_BASE_IDX 0 -#define regWD_CNTL_STATUS 0x0fdf -#define regWD_CNTL_STATUS_BASE_IDX 0 -#define regCC_GC_PRIM_CONFIG 0x0fe0 -#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 -#define regWD_QOS 0x0fe2 -#define regWD_QOS_BASE_IDX 0 -#define regWD_UTCL1_CNTL 0x0fe3 -#define regWD_UTCL1_CNTL_BASE_IDX 0 -#define regWD_UTCL1_STATUS 0x0fe4 -#define regWD_UTCL1_STATUS_BASE_IDX 0 -#define regIA_UTCL1_CNTL 0x0fe6 -#define regIA_UTCL1_CNTL_BASE_IDX 0 -#define regIA_UTCL1_STATUS 0x0fe7 -#define regIA_UTCL1_STATUS_BASE_IDX 0 -#define regCC_GC_SA_UNIT_DISABLE 0x0fe9 -#define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 -#define regGE_RATE_CNTL_1 0x0ff4 -#define regGE_RATE_CNTL_1_BASE_IDX 0 -#define regGE_RATE_CNTL_2 0x0ff5 -#define regGE_RATE_CNTL_2_BASE_IDX 0 -#define regVGT_SYS_CONFIG 0x1003 -#define regVGT_SYS_CONFIG_BASE_IDX 0 -#define regGE_PRIV_CONTROL 0x1004 -#define regGE_PRIV_CONTROL_BASE_IDX 0 -#define regGE_STATUS 0x1005 -#define regGE_STATUS_BASE_IDX 0 -#define regVGT_GS_MAX_WAVE_ID 0x1009 -#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 -#define regGFX_PIPE_CONTROL 0x100d -#define regGFX_PIPE_CONTROL_BASE_IDX 0 -#define regCC_GC_SHADER_ARRAY_CONFIG 0x100f -#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 -#define regGE2_SE_CNTL_STATUS 0x1011 -#define regGE2_SE_CNTL_STATUS_BASE_IDX 0 -#define regGE_SPI_IF_SAFE_REG 0x1018 -#define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 -#define regGE_PA_IF_SAFE_REG 0x1019 -#define regGE_PA_IF_SAFE_REG_BASE_IDX 0 -#define regPA_CL_CNTL_STATUS 0x1024 -#define regPA_CL_CNTL_STATUS_BASE_IDX 0 -#define regPA_CL_ENHANCE 0x1025 -#define regPA_CL_ENHANCE_BASE_IDX 0 -#define regPA_SU_CNTL_STATUS 0x1034 -#define regPA_SU_CNTL_STATUS_BASE_IDX 0 -#define regPA_SC_FIFO_DEPTH_CNTL 0x1035 -#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 - - -// addressBlock: gc_sqdec -// base address: 0x8c00 -#define regSQ_CONFIG 0x10a0 -#define regSQ_CONFIG_BASE_IDX 0 -#define regSQC_CONFIG 0x10a1 -#define regSQC_CONFIG_BASE_IDX 0 -#define regLDS_CONFIG 0x10a2 -#define regLDS_CONFIG_BASE_IDX 0 -#define regSQ_RANDOM_WAVE_PRI 0x10a3 -#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 -#define regSQG_STATUS 0x10a4 -#define regSQG_STATUS_BASE_IDX 0 -#define regSQ_FIFO_SIZES 0x10a5 -#define regSQ_FIFO_SIZES_BASE_IDX 0 -#define regSQ_DSM_CNTL 0x10a6 -#define regSQ_DSM_CNTL_BASE_IDX 0 -#define regSQ_DSM_CNTL2 0x10a7 -#define regSQ_DSM_CNTL2_BASE_IDX 0 -#define regSP_CONFIG 0x10ab -#define regSP_CONFIG_BASE_IDX 0 -#define regSQ_ARB_CONFIG 0x10ac -#define regSQ_ARB_CONFIG_BASE_IDX 0 -#define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 -#define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 -#define regSQG_GL1H_STATUS 0x10b9 -#define regSQG_GL1H_STATUS_BASE_IDX 0 -#define regSQG_CONFIG 0x10ba -#define regSQG_CONFIG_BASE_IDX 0 -#define regSQ_PERF_SNAPSHOT_CTRL 0x10bb -#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 -#define regCC_GC_SHADER_RATE_CONFIG 0x10bc -#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 -#define regSQ_INTERRUPT_AUTO_MASK 0x10be -#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 -#define regSQ_INTERRUPT_MSG_CTRL 0x10bf -#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 -#define regSQ_WATCH0_ADDR_H 0x10d0 -#define regSQ_WATCH0_ADDR_H_BASE_IDX 0 -#define regSQ_WATCH0_ADDR_L 0x10d1 -#define regSQ_WATCH0_ADDR_L_BASE_IDX 0 -#define regSQ_WATCH0_CNTL 0x10d2 -#define regSQ_WATCH0_CNTL_BASE_IDX 0 -#define regSQ_WATCH1_ADDR_H 0x10d3 -#define regSQ_WATCH1_ADDR_H_BASE_IDX 0 -#define regSQ_WATCH1_ADDR_L 0x10d4 -#define regSQ_WATCH1_ADDR_L_BASE_IDX 0 -#define regSQ_WATCH1_CNTL 0x10d5 -#define regSQ_WATCH1_CNTL_BASE_IDX 0 -#define regSQ_WATCH2_ADDR_H 0x10d6 -#define regSQ_WATCH2_ADDR_H_BASE_IDX 0 -#define regSQ_WATCH2_ADDR_L 0x10d7 -#define regSQ_WATCH2_ADDR_L_BASE_IDX 0 -#define regSQ_WATCH2_CNTL 0x10d8 -#define regSQ_WATCH2_CNTL_BASE_IDX 0 -#define regSQ_WATCH3_ADDR_H 0x10d9 -#define regSQ_WATCH3_ADDR_H_BASE_IDX 0 -#define regSQ_WATCH3_ADDR_L 0x10da -#define regSQ_WATCH3_ADDR_L_BASE_IDX 0 -#define regSQ_WATCH3_CNTL 0x10db -#define regSQ_WATCH3_CNTL_BASE_IDX 0 -#define regSQ_IND_INDEX 0x1118 -#define regSQ_IND_INDEX_BASE_IDX 0 -#define regSQ_IND_DATA 0x1119 -#define regSQ_IND_DATA_BASE_IDX 0 -#define regSQ_CMD 0x111b -#define regSQ_CMD_BASE_IDX 0 - - -// addressBlock: gc_shsdec -// base address: 0x9000 -#define regSX_DEBUG_1 0x11b8 -#define regSX_DEBUG_1_BASE_IDX 0 -#define regSPI_PS_MAX_WAVE_ID 0x11da -#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 -#define regSPI_GFX_CNTL 0x11dc -#define regSPI_GFX_CNTL_BASE_IDX 0 -#define regSPI_DSM_CNTL 0x11e3 -#define regSPI_DSM_CNTL_BASE_IDX 0 -#define regSPI_DSM_CNTL2 0x11e4 -#define regSPI_DSM_CNTL2_BASE_IDX 0 -#define regSPI_EDC_CNT 0x11e5 -#define regSPI_EDC_CNT_BASE_IDX 0 -#define regSPI_CONFIG_PS_CU_EN 0x11f2 -#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 -#define regSPI_WF_LIFETIME_CNTL 0x124a -#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_0 0x124b -#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_1 0x124c -#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_2 0x124d -#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_3 0x124e -#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_4 0x124f -#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 -#define regSPI_WF_LIFETIME_LIMIT_5 0x1250 -#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_0 0x1255 -#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_2 0x1257 -#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_4 0x1259 -#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_6 0x125b -#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_7 0x125c -#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_9 0x125e -#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_11 0x1260 -#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_13 0x1262 -#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_14 0x1263 -#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_15 0x1264 -#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_16 0x1265 -#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_17 0x1266 -#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_18 0x1267 -#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_19 0x1268 -#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_20 0x1269 -#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 -#define regSPI_WF_LIFETIME_STATUS_21 0x126b -#define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 -#define regSPI_LB_CTR_CTRL 0x1274 -#define regSPI_LB_CTR_CTRL_BASE_IDX 0 -#define regSPI_LB_WGP_MASK 0x1275 -#define regSPI_LB_WGP_MASK_BASE_IDX 0 -#define regSPI_LB_DATA_REG 0x1276 -#define regSPI_LB_DATA_REG_BASE_IDX 0 -#define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 -#define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 -#define regSPI_GDS_CREDITS 0x1278 -#define regSPI_GDS_CREDITS_BASE_IDX 0 -#define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 -#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 -#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a -#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 -#define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b -#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 -#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c -#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 -#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d -#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 -#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e -#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 -#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f -#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 -#define regSPI_LB_DATA_WAVES 0x1284 -#define regSPI_LB_DATA_WAVES_BASE_IDX 0 -#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c -#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 -#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d -#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 -#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e -#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 -#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f -#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 -#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 -#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 -#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 -#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 -#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 -#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 -#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 -#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 -#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 -#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 -#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 -#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 - - -// addressBlock: gc_tpdec -// base address: 0x9400 -#define regTD_STATUS 0x12c6 -#define regTD_STATUS_BASE_IDX 0 -#define regTD_DSM_CNTL 0x12cf -#define regTD_DSM_CNTL_BASE_IDX 0 -#define regTD_DSM_CNTL2 0x12d0 -#define regTD_DSM_CNTL2_BASE_IDX 0 -#define regTD_SCRATCH 0x12d3 -#define regTD_SCRATCH_BASE_IDX 0 -#define regTA_CNTL 0x12e1 -#define regTA_CNTL_BASE_IDX 0 -#define regTA_CNTL_AUX 0x12e2 -#define regTA_CNTL_AUX_BASE_IDX 0 -#define regTA_CNTL2 0x12e5 -#define regTA_CNTL2_BASE_IDX 0 -#define regTA_STATUS 0x12e8 -#define regTA_STATUS_BASE_IDX 0 -#define regTA_SCRATCH 0x1304 -#define regTA_SCRATCH_BASE_IDX 0 - - -// addressBlock: gc_gdsdec -// base address: 0x9700 -#define regGDS_CONFIG 0x1360 -#define regGDS_CONFIG_BASE_IDX 0 -#define regGDS_CNTL_STATUS 0x1361 -#define regGDS_CNTL_STATUS_BASE_IDX 0 -#define regGDS_ENHANCE 0x1362 -#define regGDS_ENHANCE_BASE_IDX 0 -#define regGDS_PROTECTION_FAULT 0x1363 -#define regGDS_PROTECTION_FAULT_BASE_IDX 0 -#define regGDS_VM_PROTECTION_FAULT 0x1364 -#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 -#define regGDS_EDC_CNT 0x1365 -#define regGDS_EDC_CNT_BASE_IDX 0 -#define regGDS_EDC_GRBM_CNT 0x1366 -#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 -#define regGDS_EDC_OA_DED 0x1367 -#define regGDS_EDC_OA_DED_BASE_IDX 0 -#define regGDS_DSM_CNTL 0x136a -#define regGDS_DSM_CNTL_BASE_IDX 0 -#define regGDS_EDC_OA_PHY_CNT 0x136b -#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 -#define regGDS_EDC_OA_PIPE_CNT 0x136c -#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 -#define regGDS_DSM_CNTL2 0x136d -#define regGDS_DSM_CNTL2_BASE_IDX 0 - - -// addressBlock: gc_rbdec -// base address: 0x9800 -#define regDB_DEBUG 0x13ac -#define regDB_DEBUG_BASE_IDX 0 -#define regDB_DEBUG2 0x13ad -#define regDB_DEBUG2_BASE_IDX 0 -#define regDB_DEBUG3 0x13ae -#define regDB_DEBUG3_BASE_IDX 0 -#define regDB_DEBUG4 0x13af -#define regDB_DEBUG4_BASE_IDX 0 -#define regDB_ETILE_STUTTER_CONTROL 0x13b0 -#define regDB_ETILE_STUTTER_CONTROL_BASE_IDX 0 -#define regDB_LTILE_STUTTER_CONTROL 0x13b1 -#define regDB_LTILE_STUTTER_CONTROL_BASE_IDX 0 -#define regDB_EQUAD_STUTTER_CONTROL 0x13b2 -#define regDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0 -#define regDB_LQUAD_STUTTER_CONTROL 0x13b3 -#define regDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0 -#define regDB_CREDIT_LIMIT 0x13b4 -#define regDB_CREDIT_LIMIT_BASE_IDX 0 -#define regDB_WATERMARKS 0x13b5 -#define regDB_WATERMARKS_BASE_IDX 0 -#define regDB_SUBTILE_CONTROL 0x13b6 -#define regDB_SUBTILE_CONTROL_BASE_IDX 0 -#define regDB_FREE_CACHELINES 0x13b7 -#define regDB_FREE_CACHELINES_BASE_IDX 0 -#define regDB_FIFO_DEPTH1 0x13b8 -#define regDB_FIFO_DEPTH1_BASE_IDX 0 -#define regDB_FIFO_DEPTH2 0x13b9 -#define regDB_FIFO_DEPTH2_BASE_IDX 0 -#define regDB_LAST_OF_BURST_CONFIG 0x13ba -#define regDB_LAST_OF_BURST_CONFIG_BASE_IDX 0 -#define regDB_RING_CONTROL 0x13bb -#define regDB_RING_CONTROL_BASE_IDX 0 -#define regDB_MEM_ARB_WATERMARKS 0x13bc -#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 -#define regDB_FIFO_DEPTH3 0x13bd -#define regDB_FIFO_DEPTH3_BASE_IDX 0 -#define regDB_DEBUG6 0x13be -#define regDB_DEBUG6_BASE_IDX 0 -#define regDB_EXCEPTION_CONTROL 0x13bf -#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 -#define regDB_DEBUG7 0x13d0 -#define regDB_DEBUG7_BASE_IDX 0 -#define regDB_DEBUG5 0x13d1 -#define regDB_DEBUG5_BASE_IDX 0 -#define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 -#define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 -#define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 -#define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 -#define regDB_FIFO_DEPTH4 0x13d9 -#define regDB_FIFO_DEPTH4_BASE_IDX 0 -#define regCC_RB_REDUNDANCY 0x13dc -#define regCC_RB_REDUNDANCY_BASE_IDX 0 -#define regCC_RB_BACKEND_DISABLE 0x13dd -#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 -#define regGB_ADDR_CONFIG 0x13de -#define regGB_ADDR_CONFIG_BASE_IDX 0 -#define regGB_BACKEND_MAP 0x13df -#define regGB_BACKEND_MAP_BASE_IDX 0 -#define regGB_GPU_ID 0x13e0 -#define regGB_GPU_ID_BASE_IDX 0 -#define regCC_RB_DAISY_CHAIN 0x13e1 -#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 -#define regGB_ADDR_CONFIG_READ 0x13e2 -#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 -#define regCB_HW_CONTROL_4 0x1422 -#define regCB_HW_CONTROL_4_BASE_IDX 0 -#define regCB_HW_CONTROL_3 0x1423 -#define regCB_HW_CONTROL_3_BASE_IDX 0 -#define regCB_HW_CONTROL 0x1424 -#define regCB_HW_CONTROL_BASE_IDX 0 -#define regCB_HW_CONTROL_1 0x1425 -#define regCB_HW_CONTROL_1_BASE_IDX 0 -#define regCB_HW_CONTROL_2 0x1426 -#define regCB_HW_CONTROL_2_BASE_IDX 0 -#define regCB_DCC_CONFIG 0x1427 -#define regCB_DCC_CONFIG_BASE_IDX 0 -#define regCB_HW_MEM_ARBITER_RD 0x1428 -#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 -#define regCB_HW_MEM_ARBITER_WR 0x1429 -#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 -#define regCB_FGCG_SRAM_OVERRIDE 0x142a -#define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 -#define regCB_DCC_CONFIG2 0x142b -#define regCB_DCC_CONFIG2_BASE_IDX 0 -#define regCHICKEN_BITS 0x142d -#define regCHICKEN_BITS_BASE_IDX 0 -#define regCB_CACHE_EVICT_POINTS 0x142e -#define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 - - -// addressBlock: gc_gceadec -// base address: 0xa800 -#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0 -#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1 -#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2 -#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3 -#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define regGCEA_DRAM_RD_GRP2VC_MAP 0x17a4 -#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 -#define regGCEA_DRAM_WR_GRP2VC_MAP 0x17a5 -#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 -#define regGCEA_DRAM_RD_LAZY 0x17a6 -#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 -#define regGCEA_DRAM_WR_LAZY 0x17a7 -#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 -#define regGCEA_DRAM_RD_CAM_CNTL 0x17a8 -#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 -#define regGCEA_DRAM_WR_CAM_CNTL 0x17a9 -#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 -#define regGCEA_DRAM_PAGE_BURST 0x17aa -#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_AGE 0x17ab -#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_AGE 0x17ac -#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_QUEUING 0x17ad -#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_QUEUING 0x17ae -#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_FIXED 0x17af -#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_FIXED 0x17b0 -#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_URGENCY 0x17b1 -#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_URGENCY 0x17b2 -#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5 -#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8 -#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define regGCEA_IO_RD_CLI2GRP_MAP0 0x187d -#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 -#define regGCEA_IO_RD_CLI2GRP_MAP1 0x187e -#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 -#define regGCEA_IO_WR_CLI2GRP_MAP0 0x187f -#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 -#define regGCEA_IO_WR_CLI2GRP_MAP1 0x1880 -#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 -#define regGCEA_IO_RD_COMBINE_FLUSH 0x1881 -#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 -#define regGCEA_IO_WR_COMBINE_FLUSH 0x1882 -#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 -#define regGCEA_IO_GROUP_BURST 0x1883 -#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_AGE 0x1884 -#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_AGE 0x1885 -#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_QUEUING 0x1886 -#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_QUEUING 0x1887 -#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_FIXED 0x1888 -#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_FIXED 0x1889 -#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_URGENCY 0x188a -#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_URGENCY 0x188b -#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c -#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d -#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x188e -#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x188f -#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 -#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x1890 -#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x1891 -#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x1892 -#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 -#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x1893 -#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 -#define regGCEA_SDP_ARB_FINAL 0x1896 -#define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 -#define regGCEA_SDP_IO_PRIORITY 0x1899 -#define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 -#define regGCEA_SDP_CREDITS 0x189a -#define regGCEA_SDP_CREDITS_BASE_IDX 0 -#define regGCEA_SDP_TAG_RESERVE0 0x189b -#define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 -#define regGCEA_SDP_TAG_RESERVE1 0x189c -#define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 -#define regGCEA_SDP_VCC_RESERVE0 0x189d -#define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 -#define regGCEA_SDP_VCC_RESERVE1 0x189e -#define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 - - -// addressBlock: gc_gceadec2 -// base address: 0x9c00 -#define regGCEA_MISC 0x14a2 -#define regGCEA_MISC_BASE_IDX 0 -#define regGCEA_LATENCY_SAMPLING 0x14a3 -#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 -#define regGCEA_MAM_CTRL2 0x14a9 -#define regGCEA_MAM_CTRL2_BASE_IDX 0 -#define regGCEA_MAM_CTRL 0x14ab -#define regGCEA_MAM_CTRL_BASE_IDX 0 -#define regGCEA_EDC_CNT 0x14b2 -#define regGCEA_EDC_CNT_BASE_IDX 0 -#define regGCEA_EDC_CNT2 0x14b3 -#define regGCEA_EDC_CNT2_BASE_IDX 0 -#define regGCEA_DSM_CNTL 0x14b4 -#define regGCEA_DSM_CNTL_BASE_IDX 0 -#define regGCEA_DSM_CNTLA 0x14b5 -#define regGCEA_DSM_CNTLA_BASE_IDX 0 -#define regGCEA_DSM_CNTLB 0x14b6 -#define regGCEA_DSM_CNTLB_BASE_IDX 0 -#define regGCEA_DSM_CNTL2 0x14b7 -#define regGCEA_DSM_CNTL2_BASE_IDX 0 -#define regGCEA_DSM_CNTL2A 0x14b8 -#define regGCEA_DSM_CNTL2A_BASE_IDX 0 -#define regGCEA_DSM_CNTL2B 0x14b9 -#define regGCEA_DSM_CNTL2B_BASE_IDX 0 -#define regGCEA_GL2C_XBR_CREDITS 0x14ba -#define regGCEA_GL2C_XBR_CREDITS_BASE_IDX 0 -#define regGCEA_GL2C_XBR_MAXBURST 0x14bb -#define regGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0 -#define regGCEA_PROBE_CNTL 0x14bc -#define regGCEA_PROBE_CNTL_BASE_IDX 0 -#define regGCEA_PROBE_MAP 0x14bd -#define regGCEA_PROBE_MAP_BASE_IDX 0 -#define regGCEA_ERR_STATUS 0x14be -#define regGCEA_ERR_STATUS_BASE_IDX 0 -#define regGCEA_MISC2 0x14bf -#define regGCEA_MISC2_BASE_IDX 0 - - -// addressBlock: gc_gceadec3 -// base address: 0x9dc0 -#define regGCEA_RRET_MEM_RESERVE 0x1518 -#define regGCEA_RRET_MEM_RESERVE_BASE_IDX 0 -#define regGCEA_EDC_CNT3 0x151a -#define regGCEA_EDC_CNT3_BASE_IDX 0 -#define regGCEA_SDP_ENABLE 0x151e -#define regGCEA_SDP_ENABLE_BASE_IDX 0 - - -// addressBlock: gc_spipdec2 -// base address: 0x9c80 -#define regSPI_PQEV_CTRL 0x14c0 -#define regSPI_PQEV_CTRL_BASE_IDX 0 -#define regSPI_EXP_THROTTLE_CTRL 0x14c3 -#define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 - - -// addressBlock: gc_rmi_rmidec -// base address: 0x2e200 -#define regRMI_GENERAL_CNTL 0x1880 -#define regRMI_GENERAL_CNTL_BASE_IDX 1 -#define regRMI_GENERAL_CNTL1 0x1881 -#define regRMI_GENERAL_CNTL1_BASE_IDX 1 -#define regRMI_GENERAL_STATUS 0x1882 -#define regRMI_GENERAL_STATUS_BASE_IDX 1 -#define regRMI_SUBBLOCK_STATUS0 0x1883 -#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 -#define regRMI_SUBBLOCK_STATUS1 0x1884 -#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 -#define regRMI_SUBBLOCK_STATUS2 0x1885 -#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 -#define regRMI_SUBBLOCK_STATUS3 0x1886 -#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 -#define regRMI_XBAR_CONFIG 0x1887 -#define regRMI_XBAR_CONFIG_BASE_IDX 1 -#define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 -#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 -#define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 -#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 -#define regRMI_DEMUX_CNTL 0x188a -#define regRMI_DEMUX_CNTL_BASE_IDX 1 -#define regRMI_UTCL1_CNTL1 0x188b -#define regRMI_UTCL1_CNTL1_BASE_IDX 1 -#define regRMI_UTCL1_CNTL2 0x188c -#define regRMI_UTCL1_CNTL2_BASE_IDX 1 -#define regRMI_UTC_UNIT_CONFIG 0x188d -#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 -#define regRMI_TCIW_FORMATTER0_CNTL 0x188e -#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 -#define regRMI_TCIW_FORMATTER1_CNTL 0x188f -#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 -#define regRMI_SCOREBOARD_CNTL 0x1890 -#define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 -#define regRMI_SCOREBOARD_STATUS0 0x1891 -#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 -#define regRMI_SCOREBOARD_STATUS1 0x1892 -#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 -#define regRMI_SCOREBOARD_STATUS2 0x1893 -#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 -#define regRMI_XBAR_ARBITER_CONFIG 0x1894 -#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 -#define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 -#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 -#define regRMI_CLOCK_CNTRL 0x1896 -#define regRMI_CLOCK_CNTRL_BASE_IDX 1 -#define regRMI_UTCL1_STATUS 0x1897 -#define regRMI_UTCL1_STATUS_BASE_IDX 1 -#define regRMI_RB_GLX_CID_MAP 0x1898 -#define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 -#define regRMI_SPARE 0x189f -#define regRMI_SPARE_BASE_IDX 1 -#define regRMI_SPARE_1 0x18a0 -#define regRMI_SPARE_1_BASE_IDX 1 -#define regRMI_SPARE_2 0x18a1 -#define regRMI_SPARE_2_BASE_IDX 1 -#define regCC_RMI_REDUNDANCY 0x18a2 -#define regCC_RMI_REDUNDANCY_BASE_IDX 1 - - -// addressBlock: gc_pmmdec -// base address: 0x9f80 -#define regGCR_PIO_CNTL 0x1580 -#define regGCR_PIO_CNTL_BASE_IDX 0 -#define regGCR_PIO_DATA 0x1581 -#define regGCR_PIO_DATA_BASE_IDX 0 -#define regPMM_CNTL 0x1582 -#define regPMM_CNTL_BASE_IDX 0 -#define regPMM_STATUS 0x1583 -#define regPMM_STATUS_BASE_IDX 0 - - -// addressBlock: gc_utcl1dec -// base address: 0x9fb0 -#define regUTCL1_CTRL_1 0x158c -#define regUTCL1_CTRL_1_BASE_IDX 0 -#define regUTCL1_ALOG 0x158f -#define regUTCL1_ALOG_BASE_IDX 0 -#define regUTCL1_STATUS 0x1594 -#define regUTCL1_STATUS_BASE_IDX 0 - - -// addressBlock: gc_gcvmsharedpfdec -// base address: 0xa000 -#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x15a4 -#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 -#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x15a5 -#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 -#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x15a6 -#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 -#define regGCMC_VM_FB_OFFSET 0x15a7 -#define regGCMC_VM_FB_OFFSET_BASE_IDX 0 -#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a8 -#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 -#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a9 -#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 -#define regGCMC_VM_STEERING 0x15aa -#define regGCMC_VM_STEERING_BASE_IDX 0 -#define regGCMC_MEM_POWER_LS 0x15ac -#define regGCMC_MEM_POWER_LS_BASE_IDX 0 -#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x15ad -#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 -#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x15ae -#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 -#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x15af -#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 -#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x15b0 -#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 -#define regGCMC_VM_APT_CNTL 0x15b1 -#define regGCMC_VM_APT_CNTL_BASE_IDX 0 -#define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x15b2 -#define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 -#define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x15b3 -#define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 -#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x15b4 -#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 -#define regGCUTCL2_ICG_CTRL 0x15b5 -#define regGCUTCL2_ICG_CTRL_BASE_IDX 0 -#define regGCUTCL2_CGTT_BUSY_CTRL 0x15b7 -#define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 -#define regGCMC_VM_FB_NOALLOC_CNTL 0x15b8 -#define regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 -#define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x15b9 -#define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 -#define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15bb -#define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 - - -// addressBlock: gc_gcvml2pfdec -// base address: 0xa070 -#define regGCVM_L2_CNTL 0x15bc -#define regGCVM_L2_CNTL_BASE_IDX 0 -#define regGCVM_L2_CNTL2 0x15bd -#define regGCVM_L2_CNTL2_BASE_IDX 0 -#define regGCVM_L2_CNTL3 0x15be -#define regGCVM_L2_CNTL3_BASE_IDX 0 -#define regGCVM_L2_STATUS 0x15bf -#define regGCVM_L2_STATUS_BASE_IDX 0 -#define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c0 -#define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 -#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c1 -#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 -#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15c2 -#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_CNTL 0x15c3 -#define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_CNTL 0x15c4 -#define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15c5 -#define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15c6 -#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15c7 -#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_STATUS 0x15c8 -#define regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15c9 -#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ca -#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15cb -#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 -#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc -#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15d0 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15d1 -#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15d2 -#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 -#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15d3 -#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 -#define regGCVM_L2_CNTL4 0x15d4 -#define regGCVM_L2_CNTL4_BASE_IDX 0 -#define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15d5 -#define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 -#define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15d6 -#define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 -#define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15d7 -#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 -#define regGCVM_L2_CACHE_PARITY_CNTL 0x15d8 -#define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 -#define regGCVM_L2_ICG_CTRL 0x15d9 -#define regGCVM_L2_ICG_CTRL_BASE_IDX 0 -#define regGCVM_L2_CNTL5 0x15da -#define regGCVM_L2_CNTL5_BASE_IDX 0 -#define regGCVM_L2_GCR_CNTL 0x15db -#define regGCVM_L2_GCR_CNTL_BASE_IDX 0 -#define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15dc -#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 -#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15dd -#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 -#define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15de -#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 -#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15df -#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 -#define regGCVM_L2_CGTT_BUSY_CTRL 0x15e0 -#define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 -#define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15e1 -#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 -#define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15e2 -#define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x15e5 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x15e6 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x15e7 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x15e8 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 -#define regGCVM_L2_BANK_SELECT_MASKS 0x15e9 -#define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 -#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15ea -#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 -#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15eb -#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 -#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15ec -#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 -#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15ed -#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 -#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15ee -#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 - - -// addressBlock: gc_gcvmsharedvcdec -// base address: 0xa360 -#define regGCMC_VM_FB_LOCATION_BASE 0x1678 -#define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0 -#define regGCMC_VM_FB_LOCATION_TOP 0x1679 -#define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0 -#define regGCMC_VM_AGP_TOP 0x167a -#define regGCMC_VM_AGP_TOP_BASE_IDX 0 -#define regGCMC_VM_AGP_BOT 0x167b -#define regGCMC_VM_AGP_BOT_BASE_IDX 0 -#define regGCMC_VM_AGP_BASE 0x167c -#define regGCMC_VM_AGP_BASE_BASE_IDX 0 -#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x167d -#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 -#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x167e -#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 -#define regGCMC_VM_MX_L1_TLB_CNTL 0x167f -#define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 - - -// addressBlock: gc_gcvml2vcdec -// base address: 0xa3a0 -#define regGCVM_CONTEXT0_CNTL 0x1688 -#define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT1_CNTL 0x1689 -#define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT2_CNTL 0x168a -#define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT3_CNTL 0x168b -#define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT4_CNTL 0x168c -#define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT5_CNTL 0x168d -#define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT6_CNTL 0x168e -#define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT7_CNTL 0x168f -#define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT8_CNTL 0x1690 -#define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT9_CNTL 0x1691 -#define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT10_CNTL 0x1692 -#define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT11_CNTL 0x1693 -#define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT12_CNTL 0x1694 -#define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT13_CNTL 0x1695 -#define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT14_CNTL 0x1696 -#define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXT15_CNTL 0x1697 -#define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 -#define regGCVM_CONTEXTS_DISABLE 0x1698 -#define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG0_SEM 0x1699 -#define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG1_SEM 0x169a -#define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG2_SEM 0x169b -#define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG3_SEM 0x169c -#define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG4_SEM 0x169d -#define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG5_SEM 0x169e -#define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG6_SEM 0x169f -#define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG7_SEM 0x16a0 -#define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG8_SEM 0x16a1 -#define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG9_SEM 0x16a2 -#define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG10_SEM 0x16a3 -#define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG11_SEM 0x16a4 -#define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG12_SEM 0x16a5 -#define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG13_SEM 0x16a6 -#define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG14_SEM 0x16a7 -#define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG15_SEM 0x16a8 -#define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG16_SEM 0x16a9 -#define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG17_SEM 0x16aa -#define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG0_REQ 0x16ab -#define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG1_REQ 0x16ac -#define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG2_REQ 0x16ad -#define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG3_REQ 0x16ae -#define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG4_REQ 0x16af -#define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG5_REQ 0x16b0 -#define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG6_REQ 0x16b1 -#define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG7_REQ 0x16b2 -#define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG8_REQ 0x16b3 -#define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG9_REQ 0x16b4 -#define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG10_REQ 0x16b5 -#define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG11_REQ 0x16b6 -#define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG12_REQ 0x16b7 -#define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG13_REQ 0x16b8 -#define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG14_REQ 0x16b9 -#define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG15_REQ 0x16ba -#define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG16_REQ 0x16bb -#define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG17_REQ 0x16bc -#define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG0_ACK 0x16bd -#define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG1_ACK 0x16be -#define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG2_ACK 0x16bf -#define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG3_ACK 0x16c0 -#define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG4_ACK 0x16c1 -#define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG5_ACK 0x16c2 -#define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG6_ACK 0x16c3 -#define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG7_ACK 0x16c4 -#define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG8_ACK 0x16c5 -#define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG9_ACK 0x16c6 -#define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG10_ACK 0x16c7 -#define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG11_ACK 0x16c8 -#define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG12_ACK 0x16c9 -#define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG13_ACK 0x16ca -#define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG14_ACK 0x16cb -#define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG15_ACK 0x16cc -#define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG16_ACK 0x16cd -#define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG17_ACK 0x16ce -#define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x16cf -#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x16d0 -#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x16d1 -#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x16d2 -#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x16d3 -#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x16d4 -#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x16d5 -#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x16d6 -#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x16d7 -#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x16d8 -#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x16d9 -#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x16da -#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x16db -#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x16dc -#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x16dd -#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x16de -#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x16df -#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x16e0 -#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x16e1 -#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x16e2 -#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x16e3 -#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x16e4 -#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x16e5 -#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x16e6 -#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x16e7 -#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x16e8 -#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x16e9 -#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x16ea -#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x16eb -#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x16ec -#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x16ed -#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x16ee -#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x16ef -#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x16f0 -#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x16f1 -#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 -#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x16f2 -#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x16f3 -#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16f4 -#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16f5 -#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16f6 -#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16f7 -#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16f8 -#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16f9 -#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16fa -#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16fb -#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16fc -#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16fd -#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16fe -#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ff -#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1700 -#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1701 -#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x1702 -#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x1703 -#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x1704 -#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x1705 -#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x1706 -#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x1707 -#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x1708 -#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x1709 -#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x170a -#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x170b -#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x170c -#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x170d -#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x170e -#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x170f -#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x1710 -#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x1711 -#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x1712 -#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x1713 -#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x1714 -#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x1715 -#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x1716 -#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x1717 -#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x1718 -#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x1719 -#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x171a -#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x171b -#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x171c -#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x171d -#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x171e -#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x171f -#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x1720 -#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x1721 -#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x1722 -#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x1723 -#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x1724 -#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x1725 -#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x1726 -#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x1727 -#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x1728 -#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x1729 -#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x172a -#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x172b -#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x172c -#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x172d -#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x172e -#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x172f -#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x1730 -#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x1731 -#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x1732 -#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x1733 -#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x1734 -#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x1735 -#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x1736 -#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x1737 -#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x1738 -#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x1739 -#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x173a -#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x173b -#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x173c -#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x173d -#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x173e -#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x173f -#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x1740 -#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x1741 -#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x1742 -#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x1743 -#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x1744 -#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x1745 -#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x1746 -#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x1747 -#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x1748 -#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x1749 -#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x174a -#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x174b -#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x174c -#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x174d -#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x174e -#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x174f -#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x1750 -#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x1751 -#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 -#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x1752 -#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 -#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1753 -#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1754 -#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1755 -#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1756 -#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1757 -#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1758 -#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1759 -#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175a -#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175b -#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175c -#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175d -#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175e -#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175f -#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1760 -#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1761 -#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1762 -#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 -#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1763 -#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 - - -// addressBlock: gc_gcvml2perfddec -// base address: 0x35380 -#define regGCVML2_PERFCOUNTER2_0_LO 0x34e0 -#define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_1_LO 0x34e1 -#define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_0_HI 0x34e2 -#define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_1_HI 0x34e3 -#define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1 - - -// addressBlock: gc_gcvml2prdec -// base address: 0x35390 -#define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e4 -#define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e5 -#define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER_LO 0x34e6 -#define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER_HI 0x34e7 -#define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 - - -// addressBlock: gc_gcvml2perfsdec -// base address: 0x37480 -#define regGCVML2_PERFCOUNTER2_0_SELECT 0x3d20 -#define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_1_SELECT 0x3d21 -#define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_0_SELECT1 0x3d22 -#define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_1_SELECT1 0x3d23 -#define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_0_MODE 0x3d24 -#define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1 -#define regGCVML2_PERFCOUNTER2_1_MODE 0x3d25 -#define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1 - - -// addressBlock: gc_gcvml2pldec -// base address: 0x374c0 -#define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d30 -#define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d31 -#define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d32 -#define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d33 -#define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d34 -#define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d35 -#define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d36 -#define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d37 -#define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 -#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d38 -#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER0_CFG 0x3d39 -#define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER1_CFG 0x3d3a -#define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER2_CFG 0x3d3b -#define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER3_CFG 0x3d3c -#define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 -#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3d3d -#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gcvmsharedhvdec -// base address: 0x3ea00 -#define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 -#define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 -#define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 -#define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 -#define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 -#define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 -#define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 -#define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 -#define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 -#define regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 -#define regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a -#define regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b -#define regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c -#define regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d -#define regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e -#define regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 -#define regGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f -#define regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 - - -// addressBlock: gc_gcvml2pspdec -// base address: 0x3f900 -#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e41 -#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e44 -#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_0 0x5e48 -#define regGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_1 0x5e49 -#define regGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_2 0x5e4a -#define regGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_3 0x5e4b -#define regGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_4 0x5e4c -#define regGCMC_VM_MARC_BASE_LO_4_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_5 0x5e4d -#define regGCMC_VM_MARC_BASE_LO_5_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_6 0x5e4e -#define regGCMC_VM_MARC_BASE_LO_6_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_7 0x5e4f -#define regGCMC_VM_MARC_BASE_LO_7_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_8 0x5e50 -#define regGCMC_VM_MARC_BASE_LO_8_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_9 0x5e51 -#define regGCMC_VM_MARC_BASE_LO_9_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_10 0x5e52 -#define regGCMC_VM_MARC_BASE_LO_10_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_11 0x5e53 -#define regGCMC_VM_MARC_BASE_LO_11_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_12 0x5e54 -#define regGCMC_VM_MARC_BASE_LO_12_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_13 0x5e55 -#define regGCMC_VM_MARC_BASE_LO_13_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_14 0x5e56 -#define regGCMC_VM_MARC_BASE_LO_14_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_LO_15 0x5e57 -#define regGCMC_VM_MARC_BASE_LO_15_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_0 0x5e58 -#define regGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_1 0x5e59 -#define regGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_2 0x5e5a -#define regGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_3 0x5e5b -#define regGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_4 0x5e5c -#define regGCMC_VM_MARC_BASE_HI_4_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_5 0x5e5d -#define regGCMC_VM_MARC_BASE_HI_5_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_6 0x5e5e -#define regGCMC_VM_MARC_BASE_HI_6_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_7 0x5e5f -#define regGCMC_VM_MARC_BASE_HI_7_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_8 0x5e60 -#define regGCMC_VM_MARC_BASE_HI_8_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_9 0x5e61 -#define regGCMC_VM_MARC_BASE_HI_9_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_10 0x5e62 -#define regGCMC_VM_MARC_BASE_HI_10_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_11 0x5e63 -#define regGCMC_VM_MARC_BASE_HI_11_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_12 0x5e64 -#define regGCMC_VM_MARC_BASE_HI_12_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_13 0x5e65 -#define regGCMC_VM_MARC_BASE_HI_13_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_14 0x5e66 -#define regGCMC_VM_MARC_BASE_HI_14_BASE_IDX 1 -#define regGCMC_VM_MARC_BASE_HI_15 0x5e67 -#define regGCMC_VM_MARC_BASE_HI_15_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_0 0x5e68 -#define regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_1 0x5e69 -#define regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_2 0x5e6a -#define regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_3 0x5e6b -#define regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_4 0x5e6c -#define regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_5 0x5e6d -#define regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_6 0x5e6e -#define regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_7 0x5e6f -#define regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_8 0x5e70 -#define regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_9 0x5e71 -#define regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_10 0x5e72 -#define regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_11 0x5e73 -#define regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_12 0x5e74 -#define regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_13 0x5e75 -#define regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_14 0x5e76 -#define regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_LO_15 0x5e77 -#define regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_0 0x5e78 -#define regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_1 0x5e79 -#define regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_2 0x5e7a -#define regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_3 0x5e7b -#define regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_4 0x5e7c -#define regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_5 0x5e7d -#define regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_6 0x5e7e -#define regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_7 0x5e7f -#define regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_8 0x5e80 -#define regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_9 0x5e81 -#define regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_10 0x5e82 -#define regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_11 0x5e83 -#define regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_12 0x5e84 -#define regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_13 0x5e85 -#define regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_14 0x5e86 -#define regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX 1 -#define regGCMC_VM_MARC_RELOC_HI_15 0x5e87 -#define regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_0 0x5e88 -#define regGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_1 0x5e89 -#define regGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_2 0x5e8a -#define regGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_3 0x5e8b -#define regGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_4 0x5e8c -#define regGCMC_VM_MARC_LEN_LO_4_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_5 0x5e8d -#define regGCMC_VM_MARC_LEN_LO_5_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_6 0x5e8e -#define regGCMC_VM_MARC_LEN_LO_6_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_7 0x5e8f -#define regGCMC_VM_MARC_LEN_LO_7_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_8 0x5e90 -#define regGCMC_VM_MARC_LEN_LO_8_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_9 0x5e91 -#define regGCMC_VM_MARC_LEN_LO_9_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_10 0x5e92 -#define regGCMC_VM_MARC_LEN_LO_10_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_11 0x5e93 -#define regGCMC_VM_MARC_LEN_LO_11_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_12 0x5e94 -#define regGCMC_VM_MARC_LEN_LO_12_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_13 0x5e95 -#define regGCMC_VM_MARC_LEN_LO_13_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_14 0x5e96 -#define regGCMC_VM_MARC_LEN_LO_14_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_LO_15 0x5e97 -#define regGCMC_VM_MARC_LEN_LO_15_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_0 0x5e98 -#define regGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_1 0x5e99 -#define regGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_2 0x5e9a -#define regGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_3 0x5e9b -#define regGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_4 0x5e9c -#define regGCMC_VM_MARC_LEN_HI_4_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_5 0x5e9d -#define regGCMC_VM_MARC_LEN_HI_5_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_6 0x5e9e -#define regGCMC_VM_MARC_LEN_HI_6_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_7 0x5e9f -#define regGCMC_VM_MARC_LEN_HI_7_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_8 0x5ea0 -#define regGCMC_VM_MARC_LEN_HI_8_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_9 0x5ea1 -#define regGCMC_VM_MARC_LEN_HI_9_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_10 0x5ea2 -#define regGCMC_VM_MARC_LEN_HI_10_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_11 0x5ea3 -#define regGCMC_VM_MARC_LEN_HI_11_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_12 0x5ea4 -#define regGCMC_VM_MARC_LEN_HI_12_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_13 0x5ea5 -#define regGCMC_VM_MARC_LEN_HI_13_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_14 0x5ea6 -#define regGCMC_VM_MARC_LEN_HI_14_BASE_IDX 1 -#define regGCMC_VM_MARC_LEN_HI_15 0x5ea7 -#define regGCMC_VM_MARC_LEN_HI_15_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_0 0x5ea8 -#define regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_1 0x5ea9 -#define regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_2 0x5eaa -#define regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_3 0x5eab -#define regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_4 0x5eac -#define regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_5 0x5ead -#define regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_6 0x5eae -#define regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_7 0x5eaf -#define regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_8 0x5eb0 -#define regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_9 0x5eb1 -#define regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_10 0x5eb2 -#define regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_11 0x5eb3 -#define regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_12 0x5eb4 -#define regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_13 0x5eb5 -#define regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_14 0x5eb6 -#define regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX 1 -#define regGCMC_VM_MARC_PFVF_MAPPING_15 0x5eb7 -#define regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX 1 -#define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5eb8 -#define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 -#define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5eb9 -#define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 - - -// addressBlock: gc_shdec -// base address: 0xb000 -#define regSPI_SHADER_PGM_RSRC4_PS 0x19a1 -#define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_CHKSUM_PS 0x19a6 -#define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC3_PS 0x19a7 -#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_PS 0x19a8 -#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_PS 0x19a9 -#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC1_PS 0x19aa -#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC2_PS 0x19ab -#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_0 0x19ac -#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_1 0x19ad -#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_2 0x19ae -#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_3 0x19af -#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_4 0x19b0 -#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_5 0x19b1 -#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_6 0x19b2 -#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_7 0x19b3 -#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_8 0x19b4 -#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_9 0x19b5 -#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_10 0x19b6 -#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_11 0x19b7 -#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_12 0x19b8 -#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_13 0x19b9 -#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_14 0x19ba -#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_15 0x19bb -#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_16 0x19bc -#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_17 0x19bd -#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_18 0x19be -#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_19 0x19bf -#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_20 0x19c0 -#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_21 0x19c1 -#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_22 0x19c2 -#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_23 0x19c3 -#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_24 0x19c4 -#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_25 0x19c5 -#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_26 0x19c6 -#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_27 0x19c7 -#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_28 0x19c8 -#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_29 0x19c9 -#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_30 0x19ca -#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_PS_31 0x19cb -#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 -#define regSPI_SHADER_REQ_CTRL_PS 0x19d0 -#define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 -#define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 -#define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 -#define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 -#define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 -#define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 -#define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC4_GS 0x1a21 -#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 -#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 -#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_ES_GS 0x1a24 -#define regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_ES_GS 0x1a25 -#define regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 -#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_GS 0x1a28 -#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_GS 0x1a29 -#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a -#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b -#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_0 0x1a2c -#define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_1 0x1a2d -#define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_2 0x1a2e -#define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_3 0x1a2f -#define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_4 0x1a30 -#define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_5 0x1a31 -#define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_6 0x1a32 -#define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_7 0x1a33 -#define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_8 0x1a34 -#define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_9 0x1a35 -#define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_10 0x1a36 -#define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_11 0x1a37 -#define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_12 0x1a38 -#define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_13 0x1a39 -#define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_14 0x1a3a -#define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_15 0x1a3b -#define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_16 0x1a3c -#define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_17 0x1a3d -#define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_18 0x1a3e -#define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_19 0x1a3f -#define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_20 0x1a40 -#define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_21 0x1a41 -#define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_22 0x1a42 -#define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_23 0x1a43 -#define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_24 0x1a44 -#define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_25 0x1a45 -#define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_26 0x1a46 -#define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_27 0x1a47 -#define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_28 0x1a48 -#define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_29 0x1a49 -#define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_30 0x1a4a -#define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_GS_31 0x1a4b -#define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 -#define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c -#define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 -#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d -#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 -#define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 -#define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 -#define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 -#define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 -#define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 -#define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_ES 0x1a68 -#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_ES 0x1a69 -#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 -#define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 -#define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC4_HS 0x1aa1 -#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 -#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 -#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_LS_HS 0x1aa4 -#define regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_LS_HS 0x1aa5 -#define regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 -#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_HS 0x1aa8 -#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_HS 0x1aa9 -#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa -#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 -#define regSPI_SHADER_PGM_RSRC2_HS 0x1aab -#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_0 0x1aac -#define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_1 0x1aad -#define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_2 0x1aae -#define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_3 0x1aaf -#define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 -#define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 -#define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 -#define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 -#define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 -#define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 -#define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 -#define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 -#define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 -#define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 -#define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_14 0x1aba -#define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_15 0x1abb -#define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_16 0x1abc -#define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_17 0x1abd -#define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_18 0x1abe -#define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_19 0x1abf -#define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 -#define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 -#define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 -#define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 -#define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 -#define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 -#define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 -#define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 -#define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 -#define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 -#define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_30 0x1aca -#define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 -#define regSPI_SHADER_USER_DATA_HS_31 0x1acb -#define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 -#define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 -#define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 -#define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 -#define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 -#define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 -#define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 -#define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 -#define regSPI_SHADER_PGM_LO_LS 0x1ae8 -#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 -#define regSPI_SHADER_PGM_HI_LS 0x1ae9 -#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 -#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 -#define regCOMPUTE_DIM_X 0x1ba1 -#define regCOMPUTE_DIM_X_BASE_IDX 0 -#define regCOMPUTE_DIM_Y 0x1ba2 -#define regCOMPUTE_DIM_Y_BASE_IDX 0 -#define regCOMPUTE_DIM_Z 0x1ba3 -#define regCOMPUTE_DIM_Z_BASE_IDX 0 -#define regCOMPUTE_START_X 0x1ba4 -#define regCOMPUTE_START_X_BASE_IDX 0 -#define regCOMPUTE_START_Y 0x1ba5 -#define regCOMPUTE_START_Y_BASE_IDX 0 -#define regCOMPUTE_START_Z 0x1ba6 -#define regCOMPUTE_START_Z_BASE_IDX 0 -#define regCOMPUTE_NUM_THREAD_X 0x1ba7 -#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 -#define regCOMPUTE_NUM_THREAD_Y 0x1ba8 -#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 -#define regCOMPUTE_NUM_THREAD_Z 0x1ba9 -#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 -#define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa -#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 -#define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab -#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 -#define regCOMPUTE_PGM_LO 0x1bac -#define regCOMPUTE_PGM_LO_BASE_IDX 0 -#define regCOMPUTE_PGM_HI 0x1bad -#define regCOMPUTE_PGM_HI_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae -#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf -#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 -#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 -#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 -#define regCOMPUTE_PGM_RSRC1 0x1bb2 -#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 -#define regCOMPUTE_PGM_RSRC2 0x1bb3 -#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 -#define regCOMPUTE_VMID 0x1bb4 -#define regCOMPUTE_VMID_BASE_IDX 0 -#define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 -#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 -#define regCOMPUTE_DESTINATION_EN_SE0 0x1bb6 -#define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 -#define regCOMPUTE_DESTINATION_EN_SE1 0x1bb7 -#define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 -#define regCOMPUTE_TMPRING_SIZE 0x1bb8 -#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 -#define regCOMPUTE_DESTINATION_EN_SE2 0x1bb9 -#define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 -#define regCOMPUTE_DESTINATION_EN_SE3 0x1bba -#define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba -#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 -#define regCOMPUTE_RESTART_X 0x1bbb -#define regCOMPUTE_RESTART_X_BASE_IDX 0 -#define regCOMPUTE_RESTART_Y 0x1bbc -#define regCOMPUTE_RESTART_Y_BASE_IDX 0 -#define regCOMPUTE_RESTART_Z 0x1bbd -#define regCOMPUTE_RESTART_Z_BASE_IDX 0 -#define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe -#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 -#define regCOMPUTE_MISC_RESERVED 0x1bbf -#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_ID 0x1bc0 -#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 -#define regCOMPUTE_THREADGROUP_ID 0x1bc1 -#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 -#define regCOMPUTE_REQ_CTRL 0x1bc2 -#define regCOMPUTE_REQ_CTRL_BASE_IDX 0 -#define regCOMPUTE_USER_ACCUM_0 0x1bc4 -#define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 -#define regCOMPUTE_USER_ACCUM_1 0x1bc5 -#define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 -#define regCOMPUTE_USER_ACCUM_2 0x1bc6 -#define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 -#define regCOMPUTE_USER_ACCUM_3 0x1bc7 -#define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 -#define regCOMPUTE_PGM_RSRC3 0x1bc8 -#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 -#define regCOMPUTE_DDID_INDEX 0x1bc9 -#define regCOMPUTE_DDID_INDEX_BASE_IDX 0 -#define regCOMPUTE_SHADER_CHKSUM 0x1bca -#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bcb -#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bcc -#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bcd -#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 -#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bce -#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bcf -#define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 -#define regCOMPUTE_RELAUNCH 0x1bd0 -#define regCOMPUTE_RELAUNCH_BASE_IDX 0 -#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bd1 -#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 -#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bd2 -#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 -#define regCOMPUTE_RELAUNCH2 0x1bd3 -#define regCOMPUTE_RELAUNCH2_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_0 0x1be0 -#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_1 0x1be1 -#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_2 0x1be2 -#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_3 0x1be3 -#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_4 0x1be4 -#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_5 0x1be5 -#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_6 0x1be6 -#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_7 0x1be7 -#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_8 0x1be8 -#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_9 0x1be9 -#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_10 0x1bea -#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_11 0x1beb -#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_12 0x1bec -#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_13 0x1bed -#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_14 0x1bee -#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 -#define regCOMPUTE_USER_DATA_15 0x1bef -#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d -#define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 -#define regCOMPUTE_DISPATCH_END 0x1c1e -#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 -#define regCOMPUTE_NOWHERE 0x1c1f -#define regCOMPUTE_NOWHERE_BASE_IDX 0 -#define regSH_RESERVED_REG0 0x1c20 -#define regSH_RESERVED_REG0_BASE_IDX 0 -#define regSH_RESERVED_REG1 0x1c21 -#define regSH_RESERVED_REG1_BASE_IDX 0 - - -// addressBlock: gc_cppdec -// base address: 0xc080 -#define regCP_CU_MASK_ADDR_LO 0x1dd2 -#define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 -#define regCP_CU_MASK_ADDR_HI 0x1dd3 -#define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 -#define regCP_CU_MASK_CNTL 0x1dd4 -#define regCP_CU_MASK_CNTL_BASE_IDX 0 -#define regCP_EOPQ_WAIT_TIME 0x1dd5 -#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 -#define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 -#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 -#define regCPC_INT_INFO 0x1dd7 -#define regCPC_INT_INFO_BASE_IDX 0 -#define regCP_VIRT_STATUS 0x1dd8 -#define regCP_VIRT_STATUS_BASE_IDX 0 -#define regCPC_INT_ADDR 0x1dd9 -#define regCPC_INT_ADDR_BASE_IDX 0 -#define regCPC_INT_PASID 0x1dda -#define regCPC_INT_PASID_BASE_IDX 0 -#define regCP_GFX_ERROR 0x1ddb -#define regCP_GFX_ERROR_BASE_IDX 0 -#define regCPG_UTCL1_CNTL 0x1ddc -#define regCPG_UTCL1_CNTL_BASE_IDX 0 -#define regCPC_UTCL1_CNTL 0x1ddd -#define regCPC_UTCL1_CNTL_BASE_IDX 0 -#define regCPF_UTCL1_CNTL 0x1dde -#define regCPF_UTCL1_CNTL_BASE_IDX 0 -#define regCP_AQL_SMM_STATUS 0x1ddf -#define regCP_AQL_SMM_STATUS_BASE_IDX 0 -#define regCP_RB0_BASE 0x1de0 -#define regCP_RB0_BASE_BASE_IDX 0 -#define regCP_RB_BASE 0x1de0 -#define regCP_RB_BASE_BASE_IDX 0 -#define regCP_RB0_CNTL 0x1de1 -#define regCP_RB0_CNTL_BASE_IDX 0 -#define regCP_RB_CNTL 0x1de1 -#define regCP_RB_CNTL_BASE_IDX 0 -#define regCP_RB_RPTR_WR 0x1de2 -#define regCP_RB_RPTR_WR_BASE_IDX 0 -#define regCP_RB0_RPTR_ADDR 0x1de3 -#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 -#define regCP_RB_RPTR_ADDR 0x1de3 -#define regCP_RB_RPTR_ADDR_BASE_IDX 0 -#define regCP_RB0_RPTR_ADDR_HI 0x1de4 -#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 -#define regCP_RB_RPTR_ADDR_HI 0x1de4 -#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define regCP_RB0_BUFSZ_MASK 0x1de5 -#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 -#define regCP_RB_BUFSZ_MASK 0x1de5 -#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 -#define regCP_INT_CNTL 0x1de9 -#define regCP_INT_CNTL_BASE_IDX 0 -#define regCP_INT_STATUS 0x1dea -#define regCP_INT_STATUS_BASE_IDX 0 -#define regCP_DEVICE_ID 0x1deb -#define regCP_DEVICE_ID_BASE_IDX 0 -#define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec -#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define regCP_RING_PRIORITY_CNTS 0x1dec -#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 -#define regCP_ME0_PIPE0_PRIORITY 0x1ded -#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 -#define regCP_RING0_PRIORITY 0x1ded -#define regCP_RING0_PRIORITY_BASE_IDX 0 -#define regCP_ME0_PIPE1_PRIORITY 0x1dee -#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 -#define regCP_RING1_PRIORITY 0x1dee -#define regCP_RING1_PRIORITY_BASE_IDX 0 -#define regCP_FATAL_ERROR 0x1df0 -#define regCP_FATAL_ERROR_BASE_IDX 0 -#define regCP_RB_VMID 0x1df1 -#define regCP_RB_VMID_BASE_IDX 0 -#define regCP_ME0_PIPE0_VMID 0x1df2 -#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 -#define regCP_ME0_PIPE1_VMID 0x1df3 -#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 -#define regCP_RB0_WPTR 0x1df4 -#define regCP_RB0_WPTR_BASE_IDX 0 -#define regCP_RB_WPTR 0x1df4 -#define regCP_RB_WPTR_BASE_IDX 0 -#define regCP_RB0_WPTR_HI 0x1df5 -#define regCP_RB0_WPTR_HI_BASE_IDX 0 -#define regCP_RB_WPTR_HI 0x1df5 -#define regCP_RB_WPTR_HI_BASE_IDX 0 -#define regCP_RB1_WPTR 0x1df6 -#define regCP_RB1_WPTR_BASE_IDX 0 -#define regCP_RB1_WPTR_HI 0x1df7 -#define regCP_RB1_WPTR_HI_BASE_IDX 0 -#define regCP_PROCESS_QUANTUM 0x1df9 -#define regCP_PROCESS_QUANTUM_BASE_IDX 0 -#define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa -#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 -#define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb -#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 -#define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc -#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 -#define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd -#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 -#define regCPG_UTCL1_ERROR 0x1dfe -#define regCPG_UTCL1_ERROR_BASE_IDX 0 -#define regCPC_UTCL1_ERROR 0x1dff -#define regCPC_UTCL1_ERROR_BASE_IDX 0 -#define regCP_RB1_BASE 0x1e00 -#define regCP_RB1_BASE_BASE_IDX 0 -#define regCP_RB1_CNTL 0x1e01 -#define regCP_RB1_CNTL_BASE_IDX 0 -#define regCP_RB1_RPTR_ADDR 0x1e02 -#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 -#define regCP_RB1_RPTR_ADDR_HI 0x1e03 -#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 -#define regCP_RB1_BUFSZ_MASK 0x1e04 -#define regCP_RB1_BUFSZ_MASK_BASE_IDX 0 -#define regCP_INT_CNTL_RING0 0x1e0a -#define regCP_INT_CNTL_RING0_BASE_IDX 0 -#define regCP_INT_CNTL_RING1 0x1e0b -#define regCP_INT_CNTL_RING1_BASE_IDX 0 -#define regCP_INT_STATUS_RING0 0x1e0d -#define regCP_INT_STATUS_RING0_BASE_IDX 0 -#define regCP_INT_STATUS_RING1 0x1e0e -#define regCP_INT_STATUS_RING1_BASE_IDX 0 -#define regCP_ME_F32_INTERRUPT 0x1e13 -#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 -#define regCP_PFP_F32_INTERRUPT 0x1e14 -#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 -#define regCP_MEC1_F32_INTERRUPT 0x1e16 -#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 -#define regCP_MEC2_F32_INTERRUPT 0x1e17 -#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 -#define regCP_PWR_CNTL 0x1e18 -#define regCP_PWR_CNTL_BASE_IDX 0 -#define regCP_ECC_FIRSTOCCURRENCE 0x1e1a -#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 -#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b -#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 -#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c -#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 -#define regGB_EDC_MODE 0x1e1e -#define regGB_EDC_MODE_BASE_IDX 0 -#define regCP_DEBUG 0x1e1f -#define regCP_DEBUG_BASE_IDX 0 -#define regCP_CPC_DEBUG 0x1e21 -#define regCP_CPC_DEBUG_BASE_IDX 0 -#define regCP_PQ_WPTR_POLL_CNTL 0x1e23 -#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 -#define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 -#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 -#define regCP_ME1_PIPE0_INT_CNTL 0x1e25 -#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 -#define regCP_ME1_PIPE1_INT_CNTL 0x1e26 -#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 -#define regCP_ME1_PIPE2_INT_CNTL 0x1e27 -#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 -#define regCP_ME1_PIPE3_INT_CNTL 0x1e28 -#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 -#define regCP_ME2_PIPE0_INT_CNTL 0x1e29 -#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 -#define regCP_ME2_PIPE1_INT_CNTL 0x1e2a -#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 -#define regCP_ME2_PIPE2_INT_CNTL 0x1e2b -#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 -#define regCP_ME2_PIPE3_INT_CNTL 0x1e2c -#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 -#define regCP_ME1_PIPE0_INT_STATUS 0x1e2d -#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 -#define regCP_ME1_PIPE1_INT_STATUS 0x1e2e -#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 -#define regCP_ME1_PIPE2_INT_STATUS 0x1e2f -#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 -#define regCP_ME1_PIPE3_INT_STATUS 0x1e30 -#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 -#define regCP_ME2_PIPE0_INT_STATUS 0x1e31 -#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 -#define regCP_ME2_PIPE1_INT_STATUS 0x1e32 -#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 -#define regCP_ME2_PIPE2_INT_STATUS 0x1e33 -#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 -#define regCP_ME2_PIPE3_INT_STATUS 0x1e34 -#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 -#define regCP_GFX_QUEUE_INDEX 0x1e37 -#define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 -#define regCC_GC_EDC_CONFIG 0x1e38 -#define regCC_GC_EDC_CONFIG_BASE_IDX 0 -#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 -#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define regCP_ME1_PIPE0_PRIORITY 0x1e3a -#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 -#define regCP_ME1_PIPE1_PRIORITY 0x1e3b -#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 -#define regCP_ME1_PIPE2_PRIORITY 0x1e3c -#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 -#define regCP_ME1_PIPE3_PRIORITY 0x1e3d -#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 -#define regCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e -#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 -#define regCP_ME2_PIPE0_PRIORITY 0x1e3f -#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 -#define regCP_ME2_PIPE1_PRIORITY 0x1e40 -#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 -#define regCP_ME2_PIPE2_PRIORITY 0x1e41 -#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 -#define regCP_ME2_PIPE3_PRIORITY 0x1e42 -#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 -#define regCP_PFP_PRGRM_CNTR_START 0x1e44 -#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 -#define regCP_ME_PRGRM_CNTR_START 0x1e45 -#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 -#define regCP_MEC1_PRGRM_CNTR_START 0x1e46 -#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 -#define regCP_MEC2_PRGRM_CNTR_START 0x1e47 -#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 -#define regCP_PFP_INTR_ROUTINE_START 0x1e49 -#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 -#define regCP_ME_INTR_ROUTINE_START 0x1e4a -#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 -#define regCP_MEC1_INTR_ROUTINE_START 0x1e4b -#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 -#define regCP_MEC2_INTR_ROUTINE_START 0x1e4c -#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 -#define regCP_CONTEXT_CNTL 0x1e4d -#define regCP_CONTEXT_CNTL_BASE_IDX 0 -#define regCP_MAX_CONTEXT 0x1e4e -#define regCP_MAX_CONTEXT_BASE_IDX 0 -#define regCP_IQ_WAIT_TIME1 0x1e4f -#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 -#define regCP_IQ_WAIT_TIME2 0x1e50 -#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 -#define regCP_RB0_BASE_HI 0x1e51 -#define regCP_RB0_BASE_HI_BASE_IDX 0 -#define regCP_RB1_BASE_HI 0x1e52 -#define regCP_RB1_BASE_HI_BASE_IDX 0 -#define regCP_VMID_RESET 0x1e53 -#define regCP_VMID_RESET_BASE_IDX 0 -#define regCPC_INT_CNTL 0x1e54 -#define regCPC_INT_CNTL_BASE_IDX 0 -#define regCPC_INT_STATUS 0x1e55 -#define regCPC_INT_STATUS_BASE_IDX 0 -#define regCP_VMID_PREEMPT 0x1e56 -#define regCP_VMID_PREEMPT_BASE_IDX 0 -#define regCPC_INT_CNTX_ID 0x1e57 -#define regCPC_INT_CNTX_ID_BASE_IDX 0 -#define regCP_PQ_STATUS 0x1e58 -#define regCP_PQ_STATUS_BASE_IDX 0 -#define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 -#define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 -#define regCP_MAX_DRAW_COUNT 0x1e5c -#define regCP_MAX_DRAW_COUNT_BASE_IDX 0 -#define regCP_MEC1_F32_INT_DIS 0x1e5d -#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 -#define regCP_MEC2_F32_INT_DIS 0x1e5e -#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 -#define regCP_VMID_STATUS 0x1e5f -#define regCP_VMID_STATUS_BASE_IDX 0 -#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 -#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 -#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 -#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 -#define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 -#define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 -#define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 -#define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 -#define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 -#define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 -#define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 -#define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 -#define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 -#define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 -#define regCPC_OS_PIPES 0x1e67 -#define regCPC_OS_PIPES_BASE_IDX 0 -#define regCP_SUSPEND_RESUME_REQ 0x1e68 -#define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 -#define regCP_SUSPEND_CNTL 0x1e69 -#define regCP_SUSPEND_CNTL_BASE_IDX 0 -#define regCP_IQ_WAIT_TIME3 0x1e6a -#define regCP_IQ_WAIT_TIME3_BASE_IDX 0 -#define regCPC_DDID_BASE_ADDR_LO 0x1e6b -#define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 -#define regCP_DDID_BASE_ADDR_LO 0x1e6b -#define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 -#define regCPC_DDID_BASE_ADDR_HI 0x1e6c -#define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_DDID_BASE_ADDR_HI 0x1e6c -#define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 -#define regCPC_DDID_CNTL 0x1e6d -#define regCPC_DDID_CNTL_BASE_IDX 0 -#define regCP_DDID_CNTL 0x1e6d -#define regCP_DDID_CNTL_BASE_IDX 0 -#define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e -#define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 -#define regCP_GFX_DDID_WPTR 0x1e6f -#define regCP_GFX_DDID_WPTR_BASE_IDX 0 -#define regCP_GFX_DDID_RPTR 0x1e70 -#define regCP_GFX_DDID_RPTR_BASE_IDX 0 -#define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 -#define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 -#define regCP_GFX_HPD_STATUS0 0x1e72 -#define regCP_GFX_HPD_STATUS0_BASE_IDX 0 -#define regCP_GFX_HPD_CONTROL0 0x1e73 -#define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 -#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 -#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 -#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 -#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 -#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 -#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 -#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 -#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 -#define regCP_GFX_INDEX_MUTEX 0x1e78 -#define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 -#define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 -#define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 -#define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a -#define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 -#define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b -#define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 -#define regCP_GFX_MQD_BASE_ADDR 0x1e7e -#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 -#define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f -#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_GFX_HQD_ACTIVE 0x1e80 -#define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 -#define regCP_GFX_HQD_VMID 0x1e81 -#define regCP_GFX_HQD_VMID_BASE_IDX 0 -#define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 -#define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 -#define regCP_GFX_HQD_QUANTUM 0x1e85 -#define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 -#define regCP_GFX_HQD_BASE 0x1e86 -#define regCP_GFX_HQD_BASE_BASE_IDX 0 -#define regCP_GFX_HQD_BASE_HI 0x1e87 -#define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 -#define regCP_GFX_HQD_RPTR 0x1e88 -#define regCP_GFX_HQD_RPTR_BASE_IDX 0 -#define regCP_GFX_HQD_RPTR_ADDR 0x1e89 -#define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 -#define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a -#define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 -#define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b -#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c -#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regCP_RB_DOORBELL_CONTROL 0x1e8d -#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 -#define regCP_GFX_HQD_OFFSET 0x1e8e -#define regCP_GFX_HQD_OFFSET_BASE_IDX 0 -#define regCP_GFX_HQD_CNTL 0x1e8f -#define regCP_GFX_HQD_CNTL_BASE_IDX 0 -#define regCP_GFX_HQD_CSMD_RPTR 0x1e90 -#define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 -#define regCP_GFX_HQD_WPTR 0x1e91 -#define regCP_GFX_HQD_WPTR_BASE_IDX 0 -#define regCP_GFX_HQD_WPTR_HI 0x1e92 -#define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 -#define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 -#define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 -#define regCP_GFX_HQD_MAPPED 0x1e94 -#define regCP_GFX_HQD_MAPPED_BASE_IDX 0 -#define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 -#define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 -#define regCP_GFX_HQD_IQ_TIMER 0x1e96 -#define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 -#define regCP_GFX_HQD_HQ_STATUS0 0x1e98 -#define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 -#define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 -#define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 -#define regCP_GFX_MQD_CONTROL 0x1e9a -#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 -#define regCP_HQD_GFX_CONTROL 0x1e9f -#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 -#define regCP_HQD_GFX_STATUS 0x1ea0 -#define regCP_HQD_GFX_STATUS_BASE_IDX 0 -#define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 -#define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 -#define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 -#define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 -#define regCP_DMA_WATCH0_MASK 0x1ec2 -#define regCP_DMA_WATCH0_MASK_BASE_IDX 0 -#define regCP_DMA_WATCH0_CNTL 0x1ec3 -#define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 -#define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 -#define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 -#define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 -#define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 -#define regCP_DMA_WATCH1_MASK 0x1ec6 -#define regCP_DMA_WATCH1_MASK_BASE_IDX 0 -#define regCP_DMA_WATCH1_CNTL 0x1ec7 -#define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 -#define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 -#define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 -#define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 -#define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 -#define regCP_DMA_WATCH2_MASK 0x1eca -#define regCP_DMA_WATCH2_MASK_BASE_IDX 0 -#define regCP_DMA_WATCH2_CNTL 0x1ecb -#define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 -#define regCP_DMA_WATCH3_ADDR_LO 0x1ecc -#define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 -#define regCP_DMA_WATCH3_ADDR_HI 0x1ecd -#define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 -#define regCP_DMA_WATCH3_MASK 0x1ece -#define regCP_DMA_WATCH3_MASK_BASE_IDX 0 -#define regCP_DMA_WATCH3_CNTL 0x1ecf -#define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 -#define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 -#define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 -#define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 -#define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 -#define regCP_DMA_WATCH_STAT 0x1ed2 -#define regCP_DMA_WATCH_STAT_BASE_IDX 0 -#define regCP_PFP_JT_STAT 0x1ed3 -#define regCP_PFP_JT_STAT_BASE_IDX 0 -#define regCP_MEC_JT_STAT 0x1ed5 -#define regCP_MEC_JT_STAT_BASE_IDX 0 -#define regCP_CPC_BUSY_HYSTERESIS 0x1edb -#define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 -#define regCP_CPF_BUSY_HYSTERESIS1 0x1edc -#define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 -#define regCP_CPF_BUSY_HYSTERESIS2 0x1edd -#define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 -#define regCP_CPG_BUSY_HYSTERESIS1 0x1ede -#define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 -#define regCP_CPG_BUSY_HYSTERESIS2 0x1edf -#define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 -#define regCP_RB_DOORBELL_CLEAR 0x1f28 -#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 -#define regCP_RB0_ACTIVE 0x1f40 -#define regCP_RB0_ACTIVE_BASE_IDX 0 -#define regCP_RB_ACTIVE 0x1f40 -#define regCP_RB_ACTIVE_BASE_IDX 0 -#define regCP_RB1_ACTIVE 0x1f41 -#define regCP_RB1_ACTIVE_BASE_IDX 0 -#define regCP_RB_STATUS 0x1f43 -#define regCP_RB_STATUS_BASE_IDX 0 -#define regCPG_RCIU_CAM_INDEX 0x1f44 -#define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 -#define regCPG_RCIU_CAM_DATA 0x1f45 -#define regCPG_RCIU_CAM_DATA_BASE_IDX 0 -#define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 -#define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 -#define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 -#define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 -#define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 -#define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 -#define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c -#define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 -#define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d -#define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 -#define regCP_SDMA_DMA_DONE 0x1f4e -#define regCP_SDMA_DMA_DONE_BASE_IDX 0 -#define regCP_PFP_SDMA_CS 0x1f4f -#define regCP_PFP_SDMA_CS_BASE_IDX 0 -#define regCP_ME_SDMA_CS 0x1f50 -#define regCP_ME_SDMA_CS_BASE_IDX 0 -#define regCPF_GCR_CNTL 0x1f53 -#define regCPF_GCR_CNTL_BASE_IDX 0 -#define regCPG_UTCL1_STATUS 0x1f54 -#define regCPG_UTCL1_STATUS_BASE_IDX 0 -#define regCPC_UTCL1_STATUS 0x1f55 -#define regCPC_UTCL1_STATUS_BASE_IDX 0 -#define regCPF_UTCL1_STATUS 0x1f56 -#define regCPF_UTCL1_STATUS_BASE_IDX 0 -#define regCP_SD_CNTL 0x1f57 -#define regCP_SD_CNTL_BASE_IDX 0 -#define regCP_SOFT_RESET_CNTL 0x1f59 -#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 -#define regCP_CPC_GFX_CNTL 0x1f5a -#define regCP_CPC_GFX_CNTL_BASE_IDX 0 - - -// addressBlock: gc_spipdec -// base address: 0xc700 -#define regSPI_ARB_PRIORITY 0x1f60 -#define regSPI_ARB_PRIORITY_BASE_IDX 0 -#define regSPI_ARB_CYCLES_0 0x1f61 -#define regSPI_ARB_CYCLES_0_BASE_IDX 0 -#define regSPI_ARB_CYCLES_1 0x1f62 -#define regSPI_ARB_CYCLES_1_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 -#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 -#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 -#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a -#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b -#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c -#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d -#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e -#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f -#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 -#define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 -#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 -#define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 -#define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 -#define regSPI_GDBG_PER_VMID_CNTL 0x1f72 -#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 -#define regSPI_COMPUTE_QUEUE_RESET 0x1f73 -#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 -#define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 -#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 - - -// addressBlock: gc_cpphqddec -// base address: 0xc800 -#define regCP_HPD_UTCL1_CNTL 0x1fa3 -#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 -#define regCP_HPD_UTCL1_ERROR 0x1fa7 -#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 -#define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 -#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 -#define regCP_MQD_BASE_ADDR 0x1fa9 -#define regCP_MQD_BASE_ADDR_BASE_IDX 0 -#define regCP_MQD_BASE_ADDR_HI 0x1faa -#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_ACTIVE 0x1fab -#define regCP_HQD_ACTIVE_BASE_IDX 0 -#define regCP_HQD_VMID 0x1fac -#define regCP_HQD_VMID_BASE_IDX 0 -#define regCP_HQD_PERSISTENT_STATE 0x1fad -#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 -#define regCP_HQD_PIPE_PRIORITY 0x1fae -#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 -#define regCP_HQD_QUEUE_PRIORITY 0x1faf -#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 -#define regCP_HQD_QUANTUM 0x1fb0 -#define regCP_HQD_QUANTUM_BASE_IDX 0 -#define regCP_HQD_PQ_BASE 0x1fb1 -#define regCP_HQD_PQ_BASE_BASE_IDX 0 -#define regCP_HQD_PQ_BASE_HI 0x1fb2 -#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 -#define regCP_HQD_PQ_RPTR 0x1fb3 -#define regCP_HQD_PQ_RPTR_BASE_IDX 0 -#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 -#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 -#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 -#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 -#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 -#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 -#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 -#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 -#define regCP_HQD_PQ_CONTROL 0x1fba -#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 -#define regCP_HQD_IB_BASE_ADDR 0x1fbb -#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 -#define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc -#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_IB_RPTR 0x1fbd -#define regCP_HQD_IB_RPTR_BASE_IDX 0 -#define regCP_HQD_IB_CONTROL 0x1fbe -#define regCP_HQD_IB_CONTROL_BASE_IDX 0 -#define regCP_HQD_IQ_TIMER 0x1fbf -#define regCP_HQD_IQ_TIMER_BASE_IDX 0 -#define regCP_HQD_IQ_RPTR 0x1fc0 -#define regCP_HQD_IQ_RPTR_BASE_IDX 0 -#define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 -#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 -#define regCP_HQD_DMA_OFFLOAD 0x1fc2 -#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 -#define regCP_HQD_OFFLOAD 0x1fc2 -#define regCP_HQD_OFFLOAD_BASE_IDX 0 -#define regCP_HQD_SEMA_CMD 0x1fc3 -#define regCP_HQD_SEMA_CMD_BASE_IDX 0 -#define regCP_HQD_MSG_TYPE 0x1fc4 -#define regCP_HQD_MSG_TYPE_BASE_IDX 0 -#define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 -#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 -#define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 -#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 -#define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 -#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 -#define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 -#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 -#define regCP_HQD_HQ_SCHEDULER0 0x1fc9 -#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 -#define regCP_HQD_HQ_STATUS0 0x1fc9 -#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 -#define regCP_HQD_HQ_CONTROL0 0x1fca -#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 -#define regCP_HQD_HQ_SCHEDULER1 0x1fca -#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 -#define regCP_MQD_CONTROL 0x1fcb -#define regCP_MQD_CONTROL_BASE_IDX 0 -#define regCP_HQD_HQ_STATUS1 0x1fcc -#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 -#define regCP_HQD_HQ_CONTROL1 0x1fcd -#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 -#define regCP_HQD_EOP_BASE_ADDR 0x1fce -#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 -#define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf -#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_EOP_CONTROL 0x1fd0 -#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 -#define regCP_HQD_EOP_RPTR 0x1fd1 -#define regCP_HQD_EOP_RPTR_BASE_IDX 0 -#define regCP_HQD_EOP_WPTR 0x1fd2 -#define regCP_HQD_EOP_WPTR_BASE_IDX 0 -#define regCP_HQD_EOP_EVENTS 0x1fd3 -#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 -#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 -#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 -#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 -#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 -#define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 -#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 -#define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 -#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 -#define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 -#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 -#define regCP_HQD_WG_STATE_OFFSET 0x1fd9 -#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 -#define regCP_HQD_CTX_SAVE_SIZE 0x1fda -#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 -#define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb -#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 -#define regCP_HQD_ERROR 0x1fdc -#define regCP_HQD_ERROR_BASE_IDX 0 -#define regCP_HQD_EOP_WPTR_MEM 0x1fdd -#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 -#define regCP_HQD_AQL_CONTROL 0x1fde -#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 -#define regCP_HQD_PQ_WPTR_LO 0x1fdf -#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 -#define regCP_HQD_PQ_WPTR_HI 0x1fe0 -#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 -#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 -#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 -#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 -#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 -#define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 -#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 -#define regCP_HQD_DDID_RPTR 0x1fe4 -#define regCP_HQD_DDID_RPTR_BASE_IDX 0 -#define regCP_HQD_DDID_WPTR 0x1fe5 -#define regCP_HQD_DDID_WPTR_BASE_IDX 0 -#define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 -#define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 -#define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 -#define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 -#define regCP_HQD_DEQUEUE_STATUS 0x1fe8 -#define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 - - -// addressBlock: gc_tcpdec -// base address: 0xca80 -#define regTCP_WATCH0_ADDR_H 0x2048 -#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 -#define regTCP_WATCH0_ADDR_L 0x2049 -#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 -#define regTCP_WATCH0_CNTL 0x204a -#define regTCP_WATCH0_CNTL_BASE_IDX 0 -#define regTCP_WATCH1_ADDR_H 0x204b -#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 -#define regTCP_WATCH1_ADDR_L 0x204c -#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 -#define regTCP_WATCH1_CNTL 0x204d -#define regTCP_WATCH1_CNTL_BASE_IDX 0 -#define regTCP_WATCH2_ADDR_H 0x204e -#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 -#define regTCP_WATCH2_ADDR_L 0x204f -#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 -#define regTCP_WATCH2_CNTL 0x2050 -#define regTCP_WATCH2_CNTL_BASE_IDX 0 -#define regTCP_WATCH3_ADDR_H 0x2051 -#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 -#define regTCP_WATCH3_ADDR_L 0x2052 -#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 -#define regTCP_WATCH3_CNTL 0x2053 -#define regTCP_WATCH3_CNTL_BASE_IDX 0 - - -// addressBlock: gc_gdspdec -// base address: 0xcc00 -#define regGDS_VMID0_BASE 0x20a0 -#define regGDS_VMID0_BASE_BASE_IDX 0 -#define regGDS_VMID0_SIZE 0x20a1 -#define regGDS_VMID0_SIZE_BASE_IDX 0 -#define regGDS_VMID1_BASE 0x20a2 -#define regGDS_VMID1_BASE_BASE_IDX 0 -#define regGDS_VMID1_SIZE 0x20a3 -#define regGDS_VMID1_SIZE_BASE_IDX 0 -#define regGDS_VMID2_BASE 0x20a4 -#define regGDS_VMID2_BASE_BASE_IDX 0 -#define regGDS_VMID2_SIZE 0x20a5 -#define regGDS_VMID2_SIZE_BASE_IDX 0 -#define regGDS_VMID3_BASE 0x20a6 -#define regGDS_VMID3_BASE_BASE_IDX 0 -#define regGDS_VMID3_SIZE 0x20a7 -#define regGDS_VMID3_SIZE_BASE_IDX 0 -#define regGDS_VMID4_BASE 0x20a8 -#define regGDS_VMID4_BASE_BASE_IDX 0 -#define regGDS_VMID4_SIZE 0x20a9 -#define regGDS_VMID4_SIZE_BASE_IDX 0 -#define regGDS_VMID5_BASE 0x20aa -#define regGDS_VMID5_BASE_BASE_IDX 0 -#define regGDS_VMID5_SIZE 0x20ab -#define regGDS_VMID5_SIZE_BASE_IDX 0 -#define regGDS_VMID6_BASE 0x20ac -#define regGDS_VMID6_BASE_BASE_IDX 0 -#define regGDS_VMID6_SIZE 0x20ad -#define regGDS_VMID6_SIZE_BASE_IDX 0 -#define regGDS_VMID7_BASE 0x20ae -#define regGDS_VMID7_BASE_BASE_IDX 0 -#define regGDS_VMID7_SIZE 0x20af -#define regGDS_VMID7_SIZE_BASE_IDX 0 -#define regGDS_VMID8_BASE 0x20b0 -#define regGDS_VMID8_BASE_BASE_IDX 0 -#define regGDS_VMID8_SIZE 0x20b1 -#define regGDS_VMID8_SIZE_BASE_IDX 0 -#define regGDS_VMID9_BASE 0x20b2 -#define regGDS_VMID9_BASE_BASE_IDX 0 -#define regGDS_VMID9_SIZE 0x20b3 -#define regGDS_VMID9_SIZE_BASE_IDX 0 -#define regGDS_VMID10_BASE 0x20b4 -#define regGDS_VMID10_BASE_BASE_IDX 0 -#define regGDS_VMID10_SIZE 0x20b5 -#define regGDS_VMID10_SIZE_BASE_IDX 0 -#define regGDS_VMID11_BASE 0x20b6 -#define regGDS_VMID11_BASE_BASE_IDX 0 -#define regGDS_VMID11_SIZE 0x20b7 -#define regGDS_VMID11_SIZE_BASE_IDX 0 -#define regGDS_VMID12_BASE 0x20b8 -#define regGDS_VMID12_BASE_BASE_IDX 0 -#define regGDS_VMID12_SIZE 0x20b9 -#define regGDS_VMID12_SIZE_BASE_IDX 0 -#define regGDS_VMID13_BASE 0x20ba -#define regGDS_VMID13_BASE_BASE_IDX 0 -#define regGDS_VMID13_SIZE 0x20bb -#define regGDS_VMID13_SIZE_BASE_IDX 0 -#define regGDS_VMID14_BASE 0x20bc -#define regGDS_VMID14_BASE_BASE_IDX 0 -#define regGDS_VMID14_SIZE 0x20bd -#define regGDS_VMID14_SIZE_BASE_IDX 0 -#define regGDS_VMID15_BASE 0x20be -#define regGDS_VMID15_BASE_BASE_IDX 0 -#define regGDS_VMID15_SIZE 0x20bf -#define regGDS_VMID15_SIZE_BASE_IDX 0 -#define regGDS_GWS_VMID0 0x20c0 -#define regGDS_GWS_VMID0_BASE_IDX 0 -#define regGDS_GWS_VMID1 0x20c1 -#define regGDS_GWS_VMID1_BASE_IDX 0 -#define regGDS_GWS_VMID2 0x20c2 -#define regGDS_GWS_VMID2_BASE_IDX 0 -#define regGDS_GWS_VMID3 0x20c3 -#define regGDS_GWS_VMID3_BASE_IDX 0 -#define regGDS_GWS_VMID4 0x20c4 -#define regGDS_GWS_VMID4_BASE_IDX 0 -#define regGDS_GWS_VMID5 0x20c5 -#define regGDS_GWS_VMID5_BASE_IDX 0 -#define regGDS_GWS_VMID6 0x20c6 -#define regGDS_GWS_VMID6_BASE_IDX 0 -#define regGDS_GWS_VMID7 0x20c7 -#define regGDS_GWS_VMID7_BASE_IDX 0 -#define regGDS_GWS_VMID8 0x20c8 -#define regGDS_GWS_VMID8_BASE_IDX 0 -#define regGDS_GWS_VMID9 0x20c9 -#define regGDS_GWS_VMID9_BASE_IDX 0 -#define regGDS_GWS_VMID10 0x20ca -#define regGDS_GWS_VMID10_BASE_IDX 0 -#define regGDS_GWS_VMID11 0x20cb -#define regGDS_GWS_VMID11_BASE_IDX 0 -#define regGDS_GWS_VMID12 0x20cc -#define regGDS_GWS_VMID12_BASE_IDX 0 -#define regGDS_GWS_VMID13 0x20cd -#define regGDS_GWS_VMID13_BASE_IDX 0 -#define regGDS_GWS_VMID14 0x20ce -#define regGDS_GWS_VMID14_BASE_IDX 0 -#define regGDS_GWS_VMID15 0x20cf -#define regGDS_GWS_VMID15_BASE_IDX 0 -#define regGDS_OA_VMID0 0x20d0 -#define regGDS_OA_VMID0_BASE_IDX 0 -#define regGDS_OA_VMID1 0x20d1 -#define regGDS_OA_VMID1_BASE_IDX 0 -#define regGDS_OA_VMID2 0x20d2 -#define regGDS_OA_VMID2_BASE_IDX 0 -#define regGDS_OA_VMID3 0x20d3 -#define regGDS_OA_VMID3_BASE_IDX 0 -#define regGDS_OA_VMID4 0x20d4 -#define regGDS_OA_VMID4_BASE_IDX 0 -#define regGDS_OA_VMID5 0x20d5 -#define regGDS_OA_VMID5_BASE_IDX 0 -#define regGDS_OA_VMID6 0x20d6 -#define regGDS_OA_VMID6_BASE_IDX 0 -#define regGDS_OA_VMID7 0x20d7 -#define regGDS_OA_VMID7_BASE_IDX 0 -#define regGDS_OA_VMID8 0x20d8 -#define regGDS_OA_VMID8_BASE_IDX 0 -#define regGDS_OA_VMID9 0x20d9 -#define regGDS_OA_VMID9_BASE_IDX 0 -#define regGDS_OA_VMID10 0x20da -#define regGDS_OA_VMID10_BASE_IDX 0 -#define regGDS_OA_VMID11 0x20db -#define regGDS_OA_VMID11_BASE_IDX 0 -#define regGDS_OA_VMID12 0x20dc -#define regGDS_OA_VMID12_BASE_IDX 0 -#define regGDS_OA_VMID13 0x20dd -#define regGDS_OA_VMID13_BASE_IDX 0 -#define regGDS_OA_VMID14 0x20de -#define regGDS_OA_VMID14_BASE_IDX 0 -#define regGDS_OA_VMID15 0x20df -#define regGDS_OA_VMID15_BASE_IDX 0 -#define regGDS_GWS_RESET0 0x20e4 -#define regGDS_GWS_RESET0_BASE_IDX 0 -#define regGDS_GWS_RESET1 0x20e5 -#define regGDS_GWS_RESET1_BASE_IDX 0 -#define regGDS_GWS_RESOURCE_RESET 0x20e6 -#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 -#define regGDS_COMPUTE_MAX_WAVE_ID 0x20e8 -#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 -#define regGDS_OA_RESET_MASK 0x20e9 -#define regGDS_OA_RESET_MASK_BASE_IDX 0 -#define regGDS_OA_RESET 0x20ea -#define regGDS_OA_RESET_BASE_IDX 0 -#define regGDS_CS_CTXSW_STATUS 0x20ed -#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 -#define regGDS_CS_CTXSW_CNT0 0x20ee -#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 -#define regGDS_CS_CTXSW_CNT1 0x20ef -#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 -#define regGDS_CS_CTXSW_CNT2 0x20f0 -#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 -#define regGDS_CS_CTXSW_CNT3 0x20f1 -#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 -#define regGDS_GFX_CTXSW_STATUS 0x20f2 -#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 -#define regGDS_PS_CTXSW_CNT0 0x20f7 -#define regGDS_PS_CTXSW_CNT0_BASE_IDX 0 -#define regGDS_PS_CTXSW_CNT1 0x20f8 -#define regGDS_PS_CTXSW_CNT1_BASE_IDX 0 -#define regGDS_PS_CTXSW_CNT2 0x20f9 -#define regGDS_PS_CTXSW_CNT2_BASE_IDX 0 -#define regGDS_PS_CTXSW_CNT3 0x20fa -#define regGDS_PS_CTXSW_CNT3_BASE_IDX 0 -#define regGDS_PS_CTXSW_IDX 0x20fb -#define regGDS_PS_CTXSW_IDX_BASE_IDX 0 -#define regGDS_GS_CTXSW_CNT0 0x2117 -#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 -#define regGDS_GS_CTXSW_CNT1 0x2118 -#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 -#define regGDS_GS_CTXSW_CNT2 0x2119 -#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 -#define regGDS_GS_CTXSW_CNT3 0x211a -#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 -#define regGDS_MEMORY_CLEAN 0x211f -#define regGDS_MEMORY_CLEAN_BASE_IDX 0 - - -// addressBlock: gc_gusdec -// base address: 0x33000 -#define regGUS_IO_RD_COMBINE_FLUSH 0x2c00 -#define regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1 -#define regGUS_IO_WR_COMBINE_FLUSH 0x2c01 -#define regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1 -#define regGUS_IO_RD_PRI_AGE_RATE 0x2c02 -#define regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1 -#define regGUS_IO_WR_PRI_AGE_RATE 0x2c03 -#define regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1 -#define regGUS_IO_RD_PRI_AGE_COEFF 0x2c04 -#define regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1 -#define regGUS_IO_WR_PRI_AGE_COEFF 0x2c05 -#define regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUEUING 0x2c06 -#define regGUS_IO_RD_PRI_QUEUING_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUEUING 0x2c07 -#define regGUS_IO_WR_PRI_QUEUING_BASE_IDX 1 -#define regGUS_IO_RD_PRI_FIXED 0x2c08 -#define regGUS_IO_RD_PRI_FIXED_BASE_IDX 1 -#define regGUS_IO_WR_PRI_FIXED 0x2c09 -#define regGUS_IO_WR_PRI_FIXED_BASE_IDX 1 -#define regGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a -#define regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1 -#define regGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b -#define regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1 -#define regGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c -#define regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1 -#define regGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d -#define regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e -#define regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f -#define regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT_PRI3 0x2c10 -#define regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT_PRI4 0x2c11 -#define regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT_PRI1 0x2c12 -#define regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT_PRI2 0x2c13 -#define regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT_PRI3 0x2c14 -#define regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT_PRI4 0x2c15 -#define regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16 -#define regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17 -#define regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18 -#define regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1 -#define regGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19 -#define regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a -#define regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b -#define regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c -#define regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1 -#define regGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d -#define regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1 -#define regGUS_DRAM_COMBINE_FLUSH 0x2c1e -#define regGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1 -#define regGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f -#define regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1 -#define regGUS_DRAM_PRI_AGE_RATE 0x2c20 -#define regGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1 -#define regGUS_DRAM_PRI_AGE_COEFF 0x2c21 -#define regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUEUING 0x2c22 -#define regGUS_DRAM_PRI_QUEUING_BASE_IDX 1 -#define regGUS_DRAM_PRI_FIXED 0x2c23 -#define regGUS_DRAM_PRI_FIXED_BASE_IDX 1 -#define regGUS_DRAM_PRI_URGENCY_COEFF 0x2c24 -#define regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1 -#define regGUS_DRAM_PRI_URGENCY_MODE 0x2c25 -#define regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT_PRI1 0x2c26 -#define regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT_PRI2 0x2c27 -#define regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT_PRI3 0x2c28 -#define regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT_PRI4 0x2c29 -#define regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT_PRI5 0x2c2a -#define regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b -#define regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c -#define regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d -#define regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e -#define regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1 -#define regGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f -#define regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1 -#define regGUS_IO_GROUP_BURST 0x2c30 -#define regGUS_IO_GROUP_BURST_BASE_IDX 1 -#define regGUS_DRAM_GROUP_BURST 0x2c31 -#define regGUS_DRAM_GROUP_BURST_BASE_IDX 1 -#define regGUS_SDP_ARB_FINAL 0x2c32 -#define regGUS_SDP_ARB_FINAL_BASE_IDX 1 -#define regGUS_SDP_QOS_VC_PRIORITY 0x2c33 -#define regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1 -#define regGUS_SDP_CREDITS 0x2c34 -#define regGUS_SDP_CREDITS_BASE_IDX 1 -#define regGUS_SDP_TAG_RESERVE0 0x2c35 -#define regGUS_SDP_TAG_RESERVE0_BASE_IDX 1 -#define regGUS_SDP_TAG_RESERVE1 0x2c36 -#define regGUS_SDP_TAG_RESERVE1_BASE_IDX 1 -#define regGUS_SDP_VCC_RESERVE0 0x2c37 -#define regGUS_SDP_VCC_RESERVE0_BASE_IDX 1 -#define regGUS_SDP_VCC_RESERVE1 0x2c38 -#define regGUS_SDP_VCC_RESERVE1_BASE_IDX 1 -#define regGUS_SDP_VCD_RESERVE0 0x2c39 -#define regGUS_SDP_VCD_RESERVE0_BASE_IDX 1 -#define regGUS_SDP_VCD_RESERVE1 0x2c3a -#define regGUS_SDP_VCD_RESERVE1_BASE_IDX 1 -#define regGUS_SDP_REQ_CNTL 0x2c3b -#define regGUS_SDP_REQ_CNTL_BASE_IDX 1 -#define regGUS_MISC 0x2c3c -#define regGUS_MISC_BASE_IDX 1 -#define regGUS_LATENCY_SAMPLING 0x2c3d -#define regGUS_LATENCY_SAMPLING_BASE_IDX 1 -#define regGUS_ERR_STATUS 0x2c3e -#define regGUS_ERR_STATUS_BASE_IDX 1 -#define regGUS_MISC2 0x2c3f -#define regGUS_MISC2_BASE_IDX 1 -#define regGUS_SDP_ENABLE 0x2c45 -#define regGUS_SDP_ENABLE_BASE_IDX 1 -#define regGUS_L1_CH0_CMD_IN 0x2c46 -#define regGUS_L1_CH0_CMD_IN_BASE_IDX 1 -#define regGUS_L1_CH0_CMD_OUT 0x2c47 -#define regGUS_L1_CH0_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_CH0_DATA_IN 0x2c48 -#define regGUS_L1_CH0_DATA_IN_BASE_IDX 1 -#define regGUS_L1_CH0_DATA_OUT 0x2c49 -#define regGUS_L1_CH0_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_CH0_DATA_U_IN 0x2c4a -#define regGUS_L1_CH0_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_CH0_DATA_U_OUT 0x2c4b -#define regGUS_L1_CH0_DATA_U_OUT_BASE_IDX 1 -#define regGUS_L1_CH1_CMD_IN 0x2c4c -#define regGUS_L1_CH1_CMD_IN_BASE_IDX 1 -#define regGUS_L1_CH1_CMD_OUT 0x2c4d -#define regGUS_L1_CH1_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_CH1_DATA_IN 0x2c4e -#define regGUS_L1_CH1_DATA_IN_BASE_IDX 1 -#define regGUS_L1_CH1_DATA_OUT 0x2c4f -#define regGUS_L1_CH1_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_CH1_DATA_U_IN 0x2c50 -#define regGUS_L1_CH1_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_CH1_DATA_U_OUT 0x2c51 -#define regGUS_L1_CH1_DATA_U_OUT_BASE_IDX 1 -#define regGUS_L1_SA0_CMD_IN 0x2c52 -#define regGUS_L1_SA0_CMD_IN_BASE_IDX 1 -#define regGUS_L1_SA0_CMD_OUT 0x2c53 -#define regGUS_L1_SA0_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_SA0_DATA_IN 0x2c54 -#define regGUS_L1_SA0_DATA_IN_BASE_IDX 1 -#define regGUS_L1_SA0_DATA_OUT 0x2c55 -#define regGUS_L1_SA0_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_SA0_DATA_U_IN 0x2c56 -#define regGUS_L1_SA0_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_SA0_DATA_U_OUT 0x2c57 -#define regGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1 -#define regGUS_L1_SA1_CMD_IN 0x2c58 -#define regGUS_L1_SA1_CMD_IN_BASE_IDX 1 -#define regGUS_L1_SA1_CMD_OUT 0x2c59 -#define regGUS_L1_SA1_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_SA1_DATA_IN 0x2c5a -#define regGUS_L1_SA1_DATA_IN_BASE_IDX 1 -#define regGUS_L1_SA1_DATA_OUT 0x2c5b -#define regGUS_L1_SA1_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_SA1_DATA_U_IN 0x2c5c -#define regGUS_L1_SA1_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_SA1_DATA_U_OUT 0x2c5d -#define regGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1 -#define regGUS_L1_SA2_CMD_IN 0x2c5e -#define regGUS_L1_SA2_CMD_IN_BASE_IDX 1 -#define regGUS_L1_SA2_CMD_OUT 0x2c5f -#define regGUS_L1_SA2_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_SA2_DATA_IN 0x2c60 -#define regGUS_L1_SA2_DATA_IN_BASE_IDX 1 -#define regGUS_L1_SA2_DATA_OUT 0x2c61 -#define regGUS_L1_SA2_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_SA2_DATA_U_IN 0x2c62 -#define regGUS_L1_SA2_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_SA2_DATA_U_OUT 0x2c63 -#define regGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1 -#define regGUS_L1_SA3_CMD_IN 0x2c64 -#define regGUS_L1_SA3_CMD_IN_BASE_IDX 1 -#define regGUS_L1_SA3_CMD_OUT 0x2c65 -#define regGUS_L1_SA3_CMD_OUT_BASE_IDX 1 -#define regGUS_L1_SA3_DATA_IN 0x2c66 -#define regGUS_L1_SA3_DATA_IN_BASE_IDX 1 -#define regGUS_L1_SA3_DATA_OUT 0x2c67 -#define regGUS_L1_SA3_DATA_OUT_BASE_IDX 1 -#define regGUS_L1_SA3_DATA_U_IN 0x2c68 -#define regGUS_L1_SA3_DATA_U_IN_BASE_IDX 1 -#define regGUS_L1_SA3_DATA_U_OUT 0x2c69 -#define regGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1 -#define regGUS_MISC3 0x2c6a -#define regGUS_MISC3_BASE_IDX 1 -#define regGUS_WRRSP_FIFO_CNTL 0x2c6b -#define regGUS_WRRSP_FIFO_CNTL_BASE_IDX 1 - - -// addressBlock: gc_gfxdec0 -// base address: 0x28000 -#define regDB_RENDER_CONTROL 0x0000 -#define regDB_RENDER_CONTROL_BASE_IDX 1 -#define regDB_COUNT_CONTROL 0x0001 -#define regDB_COUNT_CONTROL_BASE_IDX 1 -#define regDB_DEPTH_VIEW 0x0002 -#define regDB_DEPTH_VIEW_BASE_IDX 1 -#define regDB_RENDER_OVERRIDE 0x0003 -#define regDB_RENDER_OVERRIDE_BASE_IDX 1 -#define regDB_RENDER_OVERRIDE2 0x0004 -#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 -#define regDB_HTILE_DATA_BASE 0x0005 -#define regDB_HTILE_DATA_BASE_BASE_IDX 1 -#define regDB_DEPTH_SIZE_XY 0x0007 -#define regDB_DEPTH_SIZE_XY_BASE_IDX 1 -#define regDB_DEPTH_BOUNDS_MIN 0x0008 -#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 -#define regDB_DEPTH_BOUNDS_MAX 0x0009 -#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 -#define regDB_STENCIL_CLEAR 0x000a -#define regDB_STENCIL_CLEAR_BASE_IDX 1 -#define regDB_DEPTH_CLEAR 0x000b -#define regDB_DEPTH_CLEAR_BASE_IDX 1 -#define regPA_SC_SCREEN_SCISSOR_TL 0x000c -#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 -#define regPA_SC_SCREEN_SCISSOR_BR 0x000d -#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 -#define regDB_RESERVED_REG_2 0x000f -#define regDB_RESERVED_REG_2_BASE_IDX 1 -#define regDB_Z_INFO 0x0010 -#define regDB_Z_INFO_BASE_IDX 1 -#define regDB_STENCIL_INFO 0x0011 -#define regDB_STENCIL_INFO_BASE_IDX 1 -#define regDB_Z_READ_BASE 0x0012 -#define regDB_Z_READ_BASE_BASE_IDX 1 -#define regDB_STENCIL_READ_BASE 0x0013 -#define regDB_STENCIL_READ_BASE_BASE_IDX 1 -#define regDB_Z_WRITE_BASE 0x0014 -#define regDB_Z_WRITE_BASE_BASE_IDX 1 -#define regDB_STENCIL_WRITE_BASE 0x0015 -#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 -#define regDB_RESERVED_REG_1 0x0016 -#define regDB_RESERVED_REG_1_BASE_IDX 1 -#define regDB_RESERVED_REG_3 0x0017 -#define regDB_RESERVED_REG_3_BASE_IDX 1 -#define regDB_Z_READ_BASE_HI 0x001a -#define regDB_Z_READ_BASE_HI_BASE_IDX 1 -#define regDB_STENCIL_READ_BASE_HI 0x001b -#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 -#define regDB_Z_WRITE_BASE_HI 0x001c -#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 -#define regDB_STENCIL_WRITE_BASE_HI 0x001d -#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 -#define regDB_HTILE_DATA_BASE_HI 0x001e -#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 -#define regDB_RMI_L2_CACHE_CONTROL 0x001f -#define regDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1 -#define regTA_BC_BASE_ADDR 0x0020 -#define regTA_BC_BASE_ADDR_BASE_IDX 1 -#define regTA_BC_BASE_ADDR_HI 0x0021 -#define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 -#define regCOHER_DEST_BASE_HI_0 0x007a -#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 -#define regCOHER_DEST_BASE_HI_1 0x007b -#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 -#define regCOHER_DEST_BASE_HI_2 0x007c -#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 -#define regCOHER_DEST_BASE_HI_3 0x007d -#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 -#define regCOHER_DEST_BASE_2 0x007e -#define regCOHER_DEST_BASE_2_BASE_IDX 1 -#define regCOHER_DEST_BASE_3 0x007f -#define regCOHER_DEST_BASE_3_BASE_IDX 1 -#define regPA_SC_WINDOW_OFFSET 0x0080 -#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 -#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 -#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 -#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 -#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 -#define regPA_SC_CLIPRECT_RULE 0x0083 -#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 -#define regPA_SC_CLIPRECT_0_TL 0x0084 -#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 -#define regPA_SC_CLIPRECT_0_BR 0x0085 -#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 -#define regPA_SC_CLIPRECT_1_TL 0x0086 -#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 -#define regPA_SC_CLIPRECT_1_BR 0x0087 -#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 -#define regPA_SC_CLIPRECT_2_TL 0x0088 -#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 -#define regPA_SC_CLIPRECT_2_BR 0x0089 -#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 -#define regPA_SC_CLIPRECT_3_TL 0x008a -#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 -#define regPA_SC_CLIPRECT_3_BR 0x008b -#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 -#define regPA_SC_EDGERULE 0x008c -#define regPA_SC_EDGERULE_BASE_IDX 1 -#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d -#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 -#define regCB_TARGET_MASK 0x008e -#define regCB_TARGET_MASK_BASE_IDX 1 -#define regCB_SHADER_MASK 0x008f -#define regCB_SHADER_MASK_BASE_IDX 1 -#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 -#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 -#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 -#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 -#define regCOHER_DEST_BASE_0 0x0092 -#define regCOHER_DEST_BASE_0_BASE_IDX 1 -#define regCOHER_DEST_BASE_1 0x0093 -#define regCOHER_DEST_BASE_1_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 -#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 -#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 -#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 -#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 -#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 -#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a -#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b -#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c -#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d -#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e -#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f -#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 -#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 -#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 -#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 -#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 -#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 -#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 -#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 -#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 -#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 -#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa -#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab -#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac -#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad -#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae -#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af -#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 -#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 -#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 -#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 -#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 -#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_0 0x00b4 -#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_0 0x00b5 -#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_1 0x00b6 -#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_1 0x00b7 -#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_2 0x00b8 -#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_2 0x00b9 -#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_3 0x00ba -#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_3 0x00bb -#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_4 0x00bc -#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_4 0x00bd -#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_5 0x00be -#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_5 0x00bf -#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_6 0x00c0 -#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_6 0x00c1 -#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_7 0x00c2 -#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_7 0x00c3 -#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_8 0x00c4 -#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_8 0x00c5 -#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_9 0x00c6 -#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_9 0x00c7 -#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_10 0x00c8 -#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_10 0x00c9 -#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_11 0x00ca -#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_11 0x00cb -#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_12 0x00cc -#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_12 0x00cd -#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_13 0x00ce -#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_13 0x00cf -#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_14 0x00d0 -#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_14 0x00d1 -#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 -#define regPA_SC_VPORT_ZMIN_15 0x00d2 -#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 -#define regPA_SC_VPORT_ZMAX_15 0x00d3 -#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 -#define regPA_SC_RASTER_CONFIG 0x00d4 -#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 -#define regPA_SC_RASTER_CONFIG_1 0x00d5 -#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 -#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 -#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 -#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 -#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 -#define regCP_PERFMON_CNTX_CNTL 0x00d8 -#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 -#define regCP_PIPEID 0x00d9 -#define regCP_PIPEID_BASE_IDX 1 -#define regCP_RINGID 0x00d9 -#define regCP_RINGID_BASE_IDX 1 -#define regCP_VMID 0x00da -#define regCP_VMID_BASE_IDX 1 -#define regCONTEXT_RESERVED_REG0 0x00db -#define regCONTEXT_RESERVED_REG0_BASE_IDX 1 -#define regCONTEXT_RESERVED_REG1 0x00dc -#define regCONTEXT_RESERVED_REG1_BASE_IDX 1 -#define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 -#define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 -#define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 -#define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 -#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 -#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 -#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 -#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 -#define regPA_SC_VRS_RATE_CACHE_CNTL 0x00f9 -#define regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX 1 -#define regPA_SC_VRS_RATE_BASE 0x00fc -#define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 -#define regPA_SC_VRS_RATE_BASE_EXT 0x00fd -#define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 -#define regPA_SC_VRS_RATE_SIZE_XY 0x00fe -#define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 -#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 -#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 -#define regCB_RMI_GL2_CACHE_CONTROL 0x0104 -#define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 -#define regCB_BLEND_RED 0x0105 -#define regCB_BLEND_RED_BASE_IDX 1 -#define regCB_BLEND_GREEN 0x0106 -#define regCB_BLEND_GREEN_BASE_IDX 1 -#define regCB_BLEND_BLUE 0x0107 -#define regCB_BLEND_BLUE_BASE_IDX 1 -#define regCB_BLEND_ALPHA 0x0108 -#define regCB_BLEND_ALPHA_BASE_IDX 1 -#define regCB_FDCC_CONTROL 0x0109 -#define regCB_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COVERAGE_OUT_CONTROL 0x010a -#define regCB_COVERAGE_OUT_CONTROL_BASE_IDX 1 -#define regDB_STENCIL_CONTROL 0x010b -#define regDB_STENCIL_CONTROL_BASE_IDX 1 -#define regDB_STENCILREFMASK 0x010c -#define regDB_STENCILREFMASK_BASE_IDX 1 -#define regDB_STENCILREFMASK_BF 0x010d -#define regDB_STENCILREFMASK_BF_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE 0x010f -#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET 0x0110 -#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE 0x0111 -#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET 0x0112 -#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE 0x0113 -#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET 0x0114 -#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_1 0x0115 -#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_1 0x0116 -#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_1 0x0117 -#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_1 0x0118 -#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_1 0x0119 -#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_1 0x011a -#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_2 0x011b -#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_2 0x011c -#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_2 0x011d -#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_2 0x011e -#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_2 0x011f -#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_2 0x0120 -#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_3 0x0121 -#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_3 0x0122 -#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_3 0x0123 -#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_3 0x0124 -#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_3 0x0125 -#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_3 0x0126 -#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_4 0x0127 -#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_4 0x0128 -#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_4 0x0129 -#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_4 0x012a -#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_4 0x012b -#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_4 0x012c -#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_5 0x012d -#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_5 0x012e -#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_5 0x012f -#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_5 0x0130 -#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_5 0x0131 -#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_5 0x0132 -#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_6 0x0133 -#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_6 0x0134 -#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_6 0x0135 -#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_6 0x0136 -#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_6 0x0137 -#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_6 0x0138 -#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_7 0x0139 -#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_7 0x013a -#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_7 0x013b -#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_7 0x013c -#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_7 0x013d -#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_7 0x013e -#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_8 0x013f -#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_8 0x0140 -#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_8 0x0141 -#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_8 0x0142 -#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_8 0x0143 -#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_8 0x0144 -#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_9 0x0145 -#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_9 0x0146 -#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_9 0x0147 -#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_9 0x0148 -#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_9 0x0149 -#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_9 0x014a -#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_10 0x014b -#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_10 0x014c -#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_10 0x014d -#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_10 0x014e -#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_10 0x014f -#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_10 0x0150 -#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_11 0x0151 -#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_11 0x0152 -#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_11 0x0153 -#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_11 0x0154 -#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_11 0x0155 -#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_11 0x0156 -#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_12 0x0157 -#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_12 0x0158 -#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_12 0x0159 -#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_12 0x015a -#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_12 0x015b -#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_12 0x015c -#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_13 0x015d -#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_13 0x015e -#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_13 0x015f -#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_13 0x0160 -#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_13 0x0161 -#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_13 0x0162 -#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_14 0x0163 -#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_14 0x0164 -#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_14 0x0165 -#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_14 0x0166 -#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_14 0x0167 -#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_14 0x0168 -#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 -#define regPA_CL_VPORT_XSCALE_15 0x0169 -#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 -#define regPA_CL_VPORT_XOFFSET_15 0x016a -#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 -#define regPA_CL_VPORT_YSCALE_15 0x016b -#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 -#define regPA_CL_VPORT_YOFFSET_15 0x016c -#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 -#define regPA_CL_VPORT_ZSCALE_15 0x016d -#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 -#define regPA_CL_VPORT_ZOFFSET_15 0x016e -#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 -#define regPA_CL_UCP_0_X 0x016f -#define regPA_CL_UCP_0_X_BASE_IDX 1 -#define regPA_CL_UCP_0_Y 0x0170 -#define regPA_CL_UCP_0_Y_BASE_IDX 1 -#define regPA_CL_UCP_0_Z 0x0171 -#define regPA_CL_UCP_0_Z_BASE_IDX 1 -#define regPA_CL_UCP_0_W 0x0172 -#define regPA_CL_UCP_0_W_BASE_IDX 1 -#define regPA_CL_UCP_1_X 0x0173 -#define regPA_CL_UCP_1_X_BASE_IDX 1 -#define regPA_CL_UCP_1_Y 0x0174 -#define regPA_CL_UCP_1_Y_BASE_IDX 1 -#define regPA_CL_UCP_1_Z 0x0175 -#define regPA_CL_UCP_1_Z_BASE_IDX 1 -#define regPA_CL_UCP_1_W 0x0176 -#define regPA_CL_UCP_1_W_BASE_IDX 1 -#define regPA_CL_UCP_2_X 0x0177 -#define regPA_CL_UCP_2_X_BASE_IDX 1 -#define regPA_CL_UCP_2_Y 0x0178 -#define regPA_CL_UCP_2_Y_BASE_IDX 1 -#define regPA_CL_UCP_2_Z 0x0179 -#define regPA_CL_UCP_2_Z_BASE_IDX 1 -#define regPA_CL_UCP_2_W 0x017a -#define regPA_CL_UCP_2_W_BASE_IDX 1 -#define regPA_CL_UCP_3_X 0x017b -#define regPA_CL_UCP_3_X_BASE_IDX 1 -#define regPA_CL_UCP_3_Y 0x017c -#define regPA_CL_UCP_3_Y_BASE_IDX 1 -#define regPA_CL_UCP_3_Z 0x017d -#define regPA_CL_UCP_3_Z_BASE_IDX 1 -#define regPA_CL_UCP_3_W 0x017e -#define regPA_CL_UCP_3_W_BASE_IDX 1 -#define regPA_CL_UCP_4_X 0x017f -#define regPA_CL_UCP_4_X_BASE_IDX 1 -#define regPA_CL_UCP_4_Y 0x0180 -#define regPA_CL_UCP_4_Y_BASE_IDX 1 -#define regPA_CL_UCP_4_Z 0x0181 -#define regPA_CL_UCP_4_Z_BASE_IDX 1 -#define regPA_CL_UCP_4_W 0x0182 -#define regPA_CL_UCP_4_W_BASE_IDX 1 -#define regPA_CL_UCP_5_X 0x0183 -#define regPA_CL_UCP_5_X_BASE_IDX 1 -#define regPA_CL_UCP_5_Y 0x0184 -#define regPA_CL_UCP_5_Y_BASE_IDX 1 -#define regPA_CL_UCP_5_Z 0x0185 -#define regPA_CL_UCP_5_Z_BASE_IDX 1 -#define regPA_CL_UCP_5_W 0x0186 -#define regPA_CL_UCP_5_W_BASE_IDX 1 -#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 -#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 -#define regPA_RATE_CNTL 0x0188 -#define regPA_RATE_CNTL_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_0 0x0191 -#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_1 0x0192 -#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_2 0x0193 -#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_3 0x0194 -#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_4 0x0195 -#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_5 0x0196 -#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_6 0x0197 -#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_7 0x0198 -#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_8 0x0199 -#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_9 0x019a -#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_10 0x019b -#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_11 0x019c -#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_12 0x019d -#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_13 0x019e -#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_14 0x019f -#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_15 0x01a0 -#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_16 0x01a1 -#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_17 0x01a2 -#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_18 0x01a3 -#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_19 0x01a4 -#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_20 0x01a5 -#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_21 0x01a6 -#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_22 0x01a7 -#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_23 0x01a8 -#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_24 0x01a9 -#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_25 0x01aa -#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_26 0x01ab -#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_27 0x01ac -#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_28 0x01ad -#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_29 0x01ae -#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_30 0x01af -#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 -#define regSPI_PS_INPUT_CNTL_31 0x01b0 -#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 -#define regSPI_VS_OUT_CONFIG 0x01b1 -#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 -#define regSPI_PS_INPUT_ENA 0x01b3 -#define regSPI_PS_INPUT_ENA_BASE_IDX 1 -#define regSPI_PS_INPUT_ADDR 0x01b4 -#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 -#define regSPI_INTERP_CONTROL_0 0x01b5 -#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 -#define regSPI_PS_IN_CONTROL 0x01b6 -#define regSPI_PS_IN_CONTROL_BASE_IDX 1 -#define regSPI_BARYC_CNTL 0x01b8 -#define regSPI_BARYC_CNTL_BASE_IDX 1 -#define regSPI_TMPRING_SIZE 0x01ba -#define regSPI_TMPRING_SIZE_BASE_IDX 1 -#define regSPI_GFX_SCRATCH_BASE_LO 0x01bb -#define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 -#define regSPI_GFX_SCRATCH_BASE_HI 0x01bc -#define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 -#define regSPI_SHADER_IDX_FORMAT 0x01c2 -#define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 -#define regSPI_SHADER_POS_FORMAT 0x01c3 -#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 -#define regSPI_SHADER_Z_FORMAT 0x01c4 -#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 -#define regSPI_SHADER_COL_FORMAT 0x01c5 -#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 -#define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 -#define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 -#define regSX_PS_DOWNCONVERT 0x01d5 -#define regSX_PS_DOWNCONVERT_BASE_IDX 1 -#define regSX_BLEND_OPT_EPSILON 0x01d6 -#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 -#define regSX_BLEND_OPT_CONTROL 0x01d7 -#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 -#define regSX_MRT0_BLEND_OPT 0x01d8 -#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT1_BLEND_OPT 0x01d9 -#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT2_BLEND_OPT 0x01da -#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT3_BLEND_OPT 0x01db -#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT4_BLEND_OPT 0x01dc -#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT5_BLEND_OPT 0x01dd -#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT6_BLEND_OPT 0x01de -#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 -#define regSX_MRT7_BLEND_OPT 0x01df -#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 -#define regCB_BLEND0_CONTROL 0x01e0 -#define regCB_BLEND0_CONTROL_BASE_IDX 1 -#define regCB_BLEND1_CONTROL 0x01e1 -#define regCB_BLEND1_CONTROL_BASE_IDX 1 -#define regCB_BLEND2_CONTROL 0x01e2 -#define regCB_BLEND2_CONTROL_BASE_IDX 1 -#define regCB_BLEND3_CONTROL 0x01e3 -#define regCB_BLEND3_CONTROL_BASE_IDX 1 -#define regCB_BLEND4_CONTROL 0x01e4 -#define regCB_BLEND4_CONTROL_BASE_IDX 1 -#define regCB_BLEND5_CONTROL 0x01e5 -#define regCB_BLEND5_CONTROL_BASE_IDX 1 -#define regCB_BLEND6_CONTROL 0x01e6 -#define regCB_BLEND6_CONTROL_BASE_IDX 1 -#define regCB_BLEND7_CONTROL 0x01e7 -#define regCB_BLEND7_CONTROL_BASE_IDX 1 -#define regGFX_COPY_STATE 0x01f4 -#define regGFX_COPY_STATE_BASE_IDX 1 -#define regPA_CL_POINT_X_RAD 0x01f5 -#define regPA_CL_POINT_X_RAD_BASE_IDX 1 -#define regPA_CL_POINT_Y_RAD 0x01f6 -#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 -#define regPA_CL_POINT_SIZE 0x01f7 -#define regPA_CL_POINT_SIZE_BASE_IDX 1 -#define regPA_CL_POINT_CULL_RAD 0x01f8 -#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 -#define regVGT_DMA_BASE_HI 0x01f9 -#define regVGT_DMA_BASE_HI_BASE_IDX 1 -#define regVGT_DMA_BASE 0x01fa -#define regVGT_DMA_BASE_BASE_IDX 1 -#define regVGT_DRAW_INITIATOR 0x01fc -#define regVGT_DRAW_INITIATOR_BASE_IDX 1 -#define regVGT_EVENT_ADDRESS_REG 0x01fe -#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 -#define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff -#define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 -#define regDB_DEPTH_CONTROL 0x0200 -#define regDB_DEPTH_CONTROL_BASE_IDX 1 -#define regDB_EQAA 0x0201 -#define regDB_EQAA_BASE_IDX 1 -#define regCB_COLOR_CONTROL 0x0202 -#define regCB_COLOR_CONTROL_BASE_IDX 1 -#define regDB_SHADER_CONTROL 0x0203 -#define regDB_SHADER_CONTROL_BASE_IDX 1 -#define regPA_CL_CLIP_CNTL 0x0204 -#define regPA_CL_CLIP_CNTL_BASE_IDX 1 -#define regPA_SU_SC_MODE_CNTL 0x0205 -#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 -#define regPA_CL_VTE_CNTL 0x0206 -#define regPA_CL_VTE_CNTL_BASE_IDX 1 -#define regPA_CL_VS_OUT_CNTL 0x0207 -#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 -#define regPA_CL_NANINF_CNTL 0x0208 -#define regPA_CL_NANINF_CNTL_BASE_IDX 1 -#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 -#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 -#define regPA_SU_LINE_STIPPLE_SCALE 0x020a -#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 -#define regPA_SU_PRIM_FILTER_CNTL 0x020b -#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 -#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c -#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 -#define regPA_CL_NGG_CNTL 0x020e -#define regPA_CL_NGG_CNTL_BASE_IDX 1 -#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f -#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 -#define regPA_STEREO_CNTL 0x0210 -#define regPA_STEREO_CNTL_BASE_IDX 1 -#define regPA_STATE_STEREO_X 0x0211 -#define regPA_STATE_STEREO_X_BASE_IDX 1 -#define regPA_CL_VRS_CNTL 0x0212 -#define regPA_CL_VRS_CNTL_BASE_IDX 1 -#define regPA_SU_POINT_SIZE 0x0280 -#define regPA_SU_POINT_SIZE_BASE_IDX 1 -#define regPA_SU_POINT_MINMAX 0x0281 -#define regPA_SU_POINT_MINMAX_BASE_IDX 1 -#define regPA_SU_LINE_CNTL 0x0282 -#define regPA_SU_LINE_CNTL_BASE_IDX 1 -#define regPA_SC_LINE_STIPPLE 0x0283 -#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 -#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 -#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 -#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 -#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 -#define regPA_SC_MODE_CNTL_0 0x0292 -#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 -#define regPA_SC_MODE_CNTL_1 0x0293 -#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 -#define regVGT_ENHANCE 0x0294 -#define regVGT_ENHANCE_BASE_IDX 1 -#define regIA_ENHANCE 0x029c -#define regIA_ENHANCE_BASE_IDX 1 -#define regVGT_DMA_SIZE 0x029d -#define regVGT_DMA_SIZE_BASE_IDX 1 -#define regVGT_DMA_MAX_SIZE 0x029e -#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 -#define regVGT_DMA_INDEX_TYPE 0x029f -#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 -#define regWD_ENHANCE 0x02a0 -#define regWD_ENHANCE_BASE_IDX 1 -#define regVGT_PRIMITIVEID_EN 0x02a1 -#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 -#define regVGT_DMA_NUM_INSTANCES 0x02a2 -#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 -#define regVGT_PRIMITIVEID_RESET 0x02a3 -#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 -#define regVGT_EVENT_INITIATOR 0x02a4 -#define regVGT_EVENT_INITIATOR_BASE_IDX 1 -#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 -#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define regVGT_ESGS_RING_ITEMSIZE 0x02ab -#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 -#define regVGT_REUSE_OFF 0x02ad -#define regVGT_REUSE_OFF_BASE_IDX 1 -#define regDB_HTILE_SURFACE 0x02af -#define regDB_HTILE_SURFACE_BASE_IDX 1 -#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 -#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 -#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 -#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 -#define regDB_PRELOAD_CONTROL 0x02b2 -#define regDB_PRELOAD_CONTROL_BASE_IDX 1 -#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca -#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 -#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb -#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 -#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc -#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 -#define regVGT_GS_MAX_VERT_OUT 0x02ce -#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 -#define regGE_NGG_SUBGRP_CNTL 0x02d3 -#define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 -#define regVGT_TESS_DISTRIBUTION 0x02d4 -#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 -#define regVGT_SHADER_STAGES_EN 0x02d5 -#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 -#define regVGT_LS_HS_CONFIG 0x02d6 -#define regVGT_LS_HS_CONFIG_BASE_IDX 1 -#define regVGT_TF_PARAM 0x02db -#define regVGT_TF_PARAM_BASE_IDX 1 -#define regDB_ALPHA_TO_MASK 0x02dc -#define regDB_ALPHA_TO_MASK_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de -#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_CLAMP 0x02df -#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 -#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 -#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 -#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 -#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 -#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 -#define regVGT_GS_INSTANCE_CNT 0x02e4 -#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 -#define regPA_SC_CENTROID_PRIORITY_0 0x02f5 -#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 -#define regPA_SC_CENTROID_PRIORITY_1 0x02f6 -#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 -#define regPA_SC_LINE_CNTL 0x02f7 -#define regPA_SC_LINE_CNTL_BASE_IDX 1 -#define regPA_SC_AA_CONFIG 0x02f8 -#define regPA_SC_AA_CONFIG_BASE_IDX 1 -#define regPA_SU_VTX_CNTL 0x02f9 -#define regPA_SU_VTX_CNTL_BASE_IDX 1 -#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa -#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 -#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb -#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 -#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc -#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 -#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd -#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d -#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 -#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e -#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 -#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f -#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 -#define regPA_SC_SHADER_CONTROL 0x0310 -#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 -#define regPA_SC_BINNER_CNTL_0 0x0311 -#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 -#define regPA_SC_BINNER_CNTL_1 0x0312 -#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 -#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 -#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 -#define regPA_SC_NGG_MODE_CNTL 0x0314 -#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 -#define regPA_SC_BINNER_CNTL_2 0x0315 -#define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 -#define regCB_COLOR0_BASE 0x0318 -#define regCB_COLOR0_BASE_BASE_IDX 1 -#define regCB_COLOR0_VIEW 0x031b -#define regCB_COLOR0_VIEW_BASE_IDX 1 -#define regCB_COLOR0_INFO 0x031c -#define regCB_COLOR0_INFO_BASE_IDX 1 -#define regCB_COLOR0_ATTRIB 0x031d -#define regCB_COLOR0_ATTRIB_BASE_IDX 1 -#define regCB_COLOR0_FDCC_CONTROL 0x031e -#define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR0_DCC_BASE 0x0325 -#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR1_BASE 0x0327 -#define regCB_COLOR1_BASE_BASE_IDX 1 -#define regCB_COLOR1_VIEW 0x032a -#define regCB_COLOR1_VIEW_BASE_IDX 1 -#define regCB_COLOR1_INFO 0x032b -#define regCB_COLOR1_INFO_BASE_IDX 1 -#define regCB_COLOR1_ATTRIB 0x032c -#define regCB_COLOR1_ATTRIB_BASE_IDX 1 -#define regCB_COLOR1_FDCC_CONTROL 0x032d -#define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR1_DCC_BASE 0x0334 -#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR2_BASE 0x0336 -#define regCB_COLOR2_BASE_BASE_IDX 1 -#define regCB_COLOR2_VIEW 0x0339 -#define regCB_COLOR2_VIEW_BASE_IDX 1 -#define regCB_COLOR2_INFO 0x033a -#define regCB_COLOR2_INFO_BASE_IDX 1 -#define regCB_COLOR2_ATTRIB 0x033b -#define regCB_COLOR2_ATTRIB_BASE_IDX 1 -#define regCB_COLOR2_FDCC_CONTROL 0x033c -#define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR2_DCC_BASE 0x0343 -#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR3_BASE 0x0345 -#define regCB_COLOR3_BASE_BASE_IDX 1 -#define regCB_COLOR3_VIEW 0x0348 -#define regCB_COLOR3_VIEW_BASE_IDX 1 -#define regCB_COLOR3_INFO 0x0349 -#define regCB_COLOR3_INFO_BASE_IDX 1 -#define regCB_COLOR3_ATTRIB 0x034a -#define regCB_COLOR3_ATTRIB_BASE_IDX 1 -#define regCB_COLOR3_FDCC_CONTROL 0x034b -#define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR3_DCC_BASE 0x0352 -#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR4_BASE 0x0354 -#define regCB_COLOR4_BASE_BASE_IDX 1 -#define regCB_COLOR4_VIEW 0x0357 -#define regCB_COLOR4_VIEW_BASE_IDX 1 -#define regCB_COLOR4_INFO 0x0358 -#define regCB_COLOR4_INFO_BASE_IDX 1 -#define regCB_COLOR4_ATTRIB 0x0359 -#define regCB_COLOR4_ATTRIB_BASE_IDX 1 -#define regCB_COLOR4_FDCC_CONTROL 0x035a -#define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR4_DCC_BASE 0x0361 -#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR5_BASE 0x0363 -#define regCB_COLOR5_BASE_BASE_IDX 1 -#define regCB_COLOR5_VIEW 0x0366 -#define regCB_COLOR5_VIEW_BASE_IDX 1 -#define regCB_COLOR5_INFO 0x0367 -#define regCB_COLOR5_INFO_BASE_IDX 1 -#define regCB_COLOR5_ATTRIB 0x0368 -#define regCB_COLOR5_ATTRIB_BASE_IDX 1 -#define regCB_COLOR5_FDCC_CONTROL 0x0369 -#define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR5_DCC_BASE 0x0370 -#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR6_BASE 0x0372 -#define regCB_COLOR6_BASE_BASE_IDX 1 -#define regCB_COLOR6_VIEW 0x0375 -#define regCB_COLOR6_VIEW_BASE_IDX 1 -#define regCB_COLOR6_INFO 0x0376 -#define regCB_COLOR6_INFO_BASE_IDX 1 -#define regCB_COLOR6_ATTRIB 0x0377 -#define regCB_COLOR6_ATTRIB_BASE_IDX 1 -#define regCB_COLOR6_FDCC_CONTROL 0x0378 -#define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR6_DCC_BASE 0x037f -#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR7_BASE 0x0381 -#define regCB_COLOR7_BASE_BASE_IDX 1 -#define regCB_COLOR7_VIEW 0x0384 -#define regCB_COLOR7_VIEW_BASE_IDX 1 -#define regCB_COLOR7_INFO 0x0385 -#define regCB_COLOR7_INFO_BASE_IDX 1 -#define regCB_COLOR7_ATTRIB 0x0386 -#define regCB_COLOR7_ATTRIB_BASE_IDX 1 -#define regCB_COLOR7_FDCC_CONTROL 0x0387 -#define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 -#define regCB_COLOR7_DCC_BASE 0x038e -#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 -#define regCB_COLOR0_BASE_EXT 0x0390 -#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR1_BASE_EXT 0x0391 -#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR2_BASE_EXT 0x0392 -#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR3_BASE_EXT 0x0393 -#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR4_BASE_EXT 0x0394 -#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR5_BASE_EXT 0x0395 -#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR6_BASE_EXT 0x0396 -#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR7_BASE_EXT 0x0397 -#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR0_DCC_BASE_EXT 0x03a8 -#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR1_DCC_BASE_EXT 0x03a9 -#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR2_DCC_BASE_EXT 0x03aa -#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR3_DCC_BASE_EXT 0x03ab -#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR4_DCC_BASE_EXT 0x03ac -#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR5_DCC_BASE_EXT 0x03ad -#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR6_DCC_BASE_EXT 0x03ae -#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR7_DCC_BASE_EXT 0x03af -#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 -#define regCB_COLOR0_ATTRIB2 0x03b0 -#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR1_ATTRIB2 0x03b1 -#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR2_ATTRIB2 0x03b2 -#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR3_ATTRIB2 0x03b3 -#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR4_ATTRIB2 0x03b4 -#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR5_ATTRIB2 0x03b5 -#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR6_ATTRIB2 0x03b6 -#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR7_ATTRIB2 0x03b7 -#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 -#define regCB_COLOR0_ATTRIB3 0x03b8 -#define regCB_COLOR0_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR1_ATTRIB3 0x03b9 -#define regCB_COLOR1_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR2_ATTRIB3 0x03ba -#define regCB_COLOR2_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR3_ATTRIB3 0x03bb -#define regCB_COLOR3_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR4_ATTRIB3 0x03bc -#define regCB_COLOR4_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR5_ATTRIB3 0x03bd -#define regCB_COLOR5_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR6_ATTRIB3 0x03be -#define regCB_COLOR6_ATTRIB3_BASE_IDX 1 -#define regCB_COLOR7_ATTRIB3 0x03bf -#define regCB_COLOR7_ATTRIB3_BASE_IDX 1 - - -// addressBlock: gc_pfvf_cpdec -// base address: 0x2a000 -#define regCONFIG_RESERVED_REG0 0x0800 -#define regCONFIG_RESERVED_REG0_BASE_IDX 1 -#define regCONFIG_RESERVED_REG1 0x0801 -#define regCONFIG_RESERVED_REG1_BASE_IDX 1 -#define regCP_MEC_CNTL 0x0802 -#define regCP_MEC_CNTL_BASE_IDX 1 -#define regCP_ME_CNTL 0x0803 -#define regCP_ME_CNTL_BASE_IDX 1 - - -// addressBlock: gc_pfvf_grbmdec -// base address: 0x2a400 -#define regGRBM_GFX_CNTL 0x0900 -#define regGRBM_GFX_CNTL_BASE_IDX 1 -#define regGRBM_NOWHERE 0x0901 -#define regGRBM_NOWHERE_BASE_IDX 1 - - -// addressBlock: gc_pfvf_padec -// base address: 0x2a500 -#define regPA_SC_VRS_SURFACE_CNTL 0x0940 -#define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 -#define regPA_SC_ENHANCE 0x0941 -#define regPA_SC_ENHANCE_BASE_IDX 1 -#define regPA_SC_ENHANCE_1 0x0942 -#define regPA_SC_ENHANCE_1_BASE_IDX 1 -#define regPA_SC_ENHANCE_2 0x0943 -#define regPA_SC_ENHANCE_2_BASE_IDX 1 -#define regPA_SC_ENHANCE_3 0x0944 -#define regPA_SC_ENHANCE_3_BASE_IDX 1 -#define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 -#define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 -#define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 -#define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 -#define regPA_SC_DSM_CNTL 0x0948 -#define regPA_SC_DSM_CNTL_BASE_IDX 1 -#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 -#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 -#define regPA_SC_FIFO_SIZE 0x094a -#define regPA_SC_FIFO_SIZE_BASE_IDX 1 -#define regPA_SC_IF_FIFO_SIZE 0x094b -#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 -#define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c -#define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 -#define regPA_SC_ATM_CNTL 0x094d -#define regPA_SC_ATM_CNTL_BASE_IDX 1 -#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e -#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 -#define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f -#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 -#define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 -#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 -#define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 -#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 -#define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 -#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 -#define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 -#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 -#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 -#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 -#define regPA_SC_BINNER_PERF_CNTL_0 0x0955 -#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 -#define regPA_SC_BINNER_PERF_CNTL_1 0x0956 -#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 -#define regPA_SC_BINNER_PERF_CNTL_2 0x0957 -#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 -#define regPA_SC_BINNER_PERF_CNTL_3 0x0958 -#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b -#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c -#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d -#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 -#define regPA_PH_INTERFACE_FIFO_SIZE 0x095e -#define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 -#define regPA_PH_ENHANCE 0x095f -#define regPA_PH_ENHANCE_BASE_IDX 1 -#define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 -#define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 - - -// addressBlock: gc_pfvf_sqdec -// base address: 0x2a780 -#define regSQ_RUNTIME_CONFIG 0x09e0 -#define regSQ_RUNTIME_CONFIG_BASE_IDX 1 -#define regSQ_DEBUG_STS_GLOBAL 0x09e1 -#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 -#define regSQ_DEBUG_STS_GLOBAL2 0x09e2 -#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 -#define regSH_MEM_BASES 0x09e3 -#define regSH_MEM_BASES_BASE_IDX 1 -#define regSH_MEM_CONFIG 0x09e4 -#define regSH_MEM_CONFIG_BASE_IDX 1 -#define regSQ_DEBUG 0x09e5 -#define regSQ_DEBUG_BASE_IDX 1 -#define regSQ_SHADER_TBA_LO 0x09e6 -#define regSQ_SHADER_TBA_LO_BASE_IDX 1 -#define regSQ_SHADER_TBA_HI 0x09e7 -#define regSQ_SHADER_TBA_HI_BASE_IDX 1 -#define regSQ_SHADER_TMA_LO 0x09e8 -#define regSQ_SHADER_TMA_LO_BASE_IDX 1 -#define regSQ_SHADER_TMA_HI 0x09e9 -#define regSQ_SHADER_TMA_HI_BASE_IDX 1 - - -// addressBlock: gc_pfonly_cpdec -// base address: 0x2e000 -#define regCP_DEBUG_2 0x1800 -#define regCP_DEBUG_2_BASE_IDX 1 -#define regCP_FETCHER_SOURCE 0x1801 -#define regCP_FETCHER_SOURCE_BASE_IDX 1 - - -// addressBlock: gc_pfonly_cpphqddec -// base address: 0x2e080 -#define regCP_HPD_MES_ROQ_OFFSETS 0x1821 -#define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 -#define regCP_HPD_ROQ_OFFSETS 0x1821 -#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 -#define regCP_HPD_STATUS0 0x1822 -#define regCP_HPD_STATUS0_BASE_IDX 1 - - -// addressBlock: gc_pfonly_didtdec -// base address: 0x2e400 -#define regDIDT_INDEX_AUTO_INCR_EN 0x1900 -#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 1 -#define regDIDT_EDC_CTRL 0x1901 -#define regDIDT_EDC_CTRL_BASE_IDX 1 -#define regDIDT_EDC_THROTTLE_CTRL 0x1902 -#define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 -#define regDIDT_EDC_THRESHOLD 0x1903 -#define regDIDT_EDC_THRESHOLD_BASE_IDX 1 -#define regDIDT_EDC_STALL_PATTERN_1_2 0x1904 -#define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 -#define regDIDT_EDC_STALL_PATTERN_3_4 0x1905 -#define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 -#define regDIDT_EDC_STALL_PATTERN_5_6 0x1906 -#define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 -#define regDIDT_EDC_STALL_PATTERN_7 0x1907 -#define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 -#define regDIDT_EDC_STATUS 0x1908 -#define regDIDT_EDC_STATUS_BASE_IDX 1 -#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO 0x1909 -#define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX 1 -#define regDIDT_EDC_OVERFLOW 0x190a -#define regDIDT_EDC_OVERFLOW_BASE_IDX 1 -#define regDIDT_EDC_ROLLING_POWER_DELTA 0x190b -#define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 -#define regDIDT_IND_INDEX 0x190c -#define regDIDT_IND_INDEX_BASE_IDX 1 -#define regDIDT_IND_DATA 0x190d -#define regDIDT_IND_DATA_BASE_IDX 1 - - -// addressBlock: gc_pfonly_spidec -// base address: 0x2e500 -#define regSPI_GDBG_WAVE_CNTL 0x1943 -#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 -#define regSPI_GDBG_TRAP_CONFIG 0x1944 -#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 -#define regSPI_GDBG_WAVE_CNTL3 0x1945 -#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 -#define regSPI_ARB_CNTL_0 0x1949 -#define regSPI_ARB_CNTL_0_BASE_IDX 1 -#define regSPI_FEATURE_CTRL 0x194a -#define regSPI_FEATURE_CTRL_BASE_IDX 1 -#define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b -#define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 -#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e -#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 - - -// addressBlock: gc_pfonly_tcpdec -// base address: 0x2e680 -#define regTCP_INVALIDATE 0x19a0 -#define regTCP_INVALIDATE_BASE_IDX 1 -#define regTCP_STATUS 0x19a1 -#define regTCP_STATUS_BASE_IDX 1 -#define regTCP_CNTL 0x19a2 -#define regTCP_CNTL_BASE_IDX 1 -#define regTCP_CNTL2 0x19a3 -#define regTCP_CNTL2_BASE_IDX 1 -#define regTCP_DEBUG_INDEX 0x19a5 -#define regTCP_DEBUG_INDEX_BASE_IDX 1 -#define regTCP_DEBUG_DATA 0x19a6 -#define regTCP_DEBUG_DATA_BASE_IDX 1 - - -// addressBlock: gc_pfonly_gdsdec -// base address: 0x2e6c0 -#define regGDS_ENHANCE2 0x19b0 -#define regGDS_ENHANCE2_BASE_IDX 1 -#define regGDS_OA_CGPG_RESTORE 0x19b1 -#define regGDS_OA_CGPG_RESTORE_BASE_IDX 1 - - -// addressBlock: gc_pfonly_utcl1dec -// base address: 0x2e600 -#define regUTCL1_CTRL_0 0x1980 -#define regUTCL1_CTRL_0_BASE_IDX 1 -#define regUTCL1_UTCL0_INVREQ_DISABLE 0x1984 -#define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 -#define regUTCL1_CTRL_2 0x1985 -#define regUTCL1_CTRL_2_BASE_IDX 1 -#define regUTCL1_FIFO_SIZING 0x1986 -#define regUTCL1_FIFO_SIZING_BASE_IDX 1 -#define regGCRD_SA0_TARGETS_DISABLE 0x1987 -#define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 -#define regGCRD_SA1_TARGETS_DISABLE 0x1989 -#define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 -#define regGCRD_CREDIT_SAFE 0x198a -#define regGCRD_CREDIT_SAFE_BASE_IDX 1 - - -// addressBlock: gc_pfonly_pmmdec -// base address: 0x2e640 -#define regGCR_GENERAL_CNTL 0x1990 -#define regGCR_GENERAL_CNTL_BASE_IDX 1 -#define regGCR_CMD_STATUS 0x1992 -#define regGCR_CMD_STATUS_BASE_IDX 1 -#define regGCR_SPARE 0x1993 -#define regGCR_SPARE_BASE_IDX 1 -#define regPMM_CNTL2 0x1999 -#define regPMM_CNTL2_BASE_IDX 1 - - -// addressBlock: gc_sedcdec -// base address: 0x2eb00 -#define regSEDC_GL1_GL2_OVERRIDES 0x1ac0 -#define regSEDC_GL1_GL2_OVERRIDES_BASE_IDX 1 - - -// addressBlock: gc_pfonly_gccacdec -// base address: 0x2eb40 -#define regGC_CAC_CTRL_1 0x1ad0 -#define regGC_CAC_CTRL_1_BASE_IDX 1 -#define regGC_CAC_CTRL_2 0x1ad1 -#define regGC_CAC_CTRL_2_BASE_IDX 1 -#define regGC_CAC_AGGR_LOWER 0x1ad2 -#define regGC_CAC_AGGR_LOWER_BASE_IDX 1 -#define regGC_CAC_AGGR_UPPER 0x1ad3 -#define regGC_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE0_CAC_AGGR_LOWER 0x1ad4 -#define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE0_CAC_AGGR_UPPER 0x1ad5 -#define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE1_CAC_AGGR_LOWER 0x1ad6 -#define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE1_CAC_AGGR_UPPER 0x1ad7 -#define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE2_CAC_AGGR_LOWER 0x1ad8 -#define regSE2_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE2_CAC_AGGR_UPPER 0x1ad9 -#define regSE2_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE3_CAC_AGGR_LOWER 0x1ada -#define regSE3_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE3_CAC_AGGR_UPPER 0x1adb -#define regSE3_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE4_CAC_AGGR_LOWER 0x1adc -#define regSE4_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE4_CAC_AGGR_UPPER 0x1add -#define regSE4_CAC_AGGR_UPPER_BASE_IDX 1 -#define regSE5_CAC_AGGR_LOWER 0x1ade -#define regSE5_CAC_AGGR_LOWER_BASE_IDX 1 -#define regSE5_CAC_AGGR_UPPER 0x1adf -#define regSE5_CAC_AGGR_UPPER_BASE_IDX 1 -#define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae4 -#define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae5 -#define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 -#define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE2_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 -#define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE3_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 -#define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE4_CAC_AGGR_GFXCLK_CYCLE 0x1ae9 -#define regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE5_CAC_AGGR_GFXCLK_CYCLE 0x1aea -#define regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 -#define regGC_EDC_CTRL 0x1aed -#define regGC_EDC_CTRL_BASE_IDX 1 -#define regGC_EDC_THRESHOLD 0x1aee -#define regGC_EDC_THRESHOLD_BASE_IDX 1 -#define regGC_EDC_STRETCH_CTRL 0x1aef -#define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 -#define regGC_EDC_STRETCH_THRESHOLD 0x1af0 -#define regGC_EDC_STRETCH_THRESHOLD_BASE_IDX 1 -#define regEDC_HYSTERESIS_CNTL 0x1af1 -#define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 -#define regGC_THROTTLE_CTRL 0x1af2 -#define regGC_THROTTLE_CTRL_BASE_IDX 1 -#define regGC_THROTTLE_CTRL1 0x1af3 -#define regGC_THROTTLE_CTRL1_BASE_IDX 1 -#define regPCC_STALL_PATTERN_CTRL 0x1af4 -#define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 -#define regPWRBRK_STALL_PATTERN_CTRL 0x1af5 -#define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 -#define regPCC_STALL_PATTERN_1_2 0x1af6 -#define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 -#define regPCC_STALL_PATTERN_3_4 0x1af7 -#define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 -#define regPCC_STALL_PATTERN_5_6 0x1af8 -#define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 -#define regPCC_STALL_PATTERN_7 0x1af9 -#define regPCC_STALL_PATTERN_7_BASE_IDX 1 -#define regPWRBRK_STALL_PATTERN_1_2 0x1afa -#define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 -#define regPWRBRK_STALL_PATTERN_3_4 0x1afb -#define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 -#define regPWRBRK_STALL_PATTERN_5_6 0x1afc -#define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 -#define regPWRBRK_STALL_PATTERN_7 0x1afd -#define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 -#define regDIDT_STALL_PATTERN_CTRL 0x1afe -#define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 -#define regDIDT_STALL_PATTERN_1_2 0x1aff -#define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 -#define regDIDT_STALL_PATTERN_3_4 0x1b00 -#define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 -#define regDIDT_STALL_PATTERN_5_6 0x1b01 -#define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 -#define regDIDT_STALL_PATTERN_7 0x1b02 -#define regDIDT_STALL_PATTERN_7_BASE_IDX 1 -#define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b03 -#define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 -#define regEDC_STRETCH_PERF_COUNTER 0x1b04 -#define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 -#define regEDC_UNSTRETCH_PERF_COUNTER 0x1b05 -#define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 -#define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b06 -#define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 -#define regGC_EDC_STATUS 0x1b07 -#define regGC_EDC_STATUS_BASE_IDX 1 -#define regGC_EDC_OVERFLOW 0x1b08 -#define regGC_EDC_OVERFLOW_BASE_IDX 1 -#define regGC_EDC_ROLLING_POWER_DELTA 0x1b09 -#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 -#define regGC_THROTTLE_STATUS 0x1b0a -#define regGC_THROTTLE_STATUS_BASE_IDX 1 -#define regEDC_PERF_COUNTER 0x1b0b -#define regEDC_PERF_COUNTER_BASE_IDX 1 -#define regPCC_PERF_COUNTER 0x1b0c -#define regPCC_PERF_COUNTER_BASE_IDX 1 -#define regPWRBRK_PERF_COUNTER 0x1b0d -#define regPWRBRK_PERF_COUNTER_BASE_IDX 1 -#define regEDC_HYSTERESIS_STAT 0x1b0e -#define regEDC_HYSTERESIS_STAT_BASE_IDX 1 -#define regGC_CAC_WEIGHT_CP_0 0x1b10 -#define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_CP_1 0x1b11 -#define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_EA_0 0x1b12 -#define regGC_CAC_WEIGHT_EA_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_EA_1 0x1b13 -#define regGC_CAC_WEIGHT_EA_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_EA_2 0x1b14 -#define regGC_CAC_WEIGHT_EA_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x1b15 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x1b16 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x1b17 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x1b18 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x1b19 -#define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_VML2_0 0x1b1a -#define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_VML2_1 0x1b1b -#define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_VML2_2 0x1b1c -#define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_WALKER_0 0x1b1d -#define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_WALKER_1 0x1b1e -#define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_UTCL2_WALKER_2 0x1b1f -#define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GDS_0 0x1b20 -#define regGC_CAC_WEIGHT_GDS_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GDS_1 0x1b21 -#define regGC_CAC_WEIGHT_GDS_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GDS_2 0x1b22 -#define regGC_CAC_WEIGHT_GDS_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_0 0x1b23 -#define regGC_CAC_WEIGHT_GE_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_1 0x1b24 -#define regGC_CAC_WEIGHT_GE_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_2 0x1b25 -#define regGC_CAC_WEIGHT_GE_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_3 0x1b26 -#define regGC_CAC_WEIGHT_GE_3_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_4 0x1b27 -#define regGC_CAC_WEIGHT_GE_4_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_5 0x1b28 -#define regGC_CAC_WEIGHT_GE_5_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GE_6 0x1b29 -#define regGC_CAC_WEIGHT_GE_6_BASE_IDX 1 -#define regGC_CAC_WEIGHT_PMM_0 0x1b2e -#define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GL2C_0 0x1b2f -#define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GL2C_1 0x1b30 -#define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GL2C_2 0x1b31 -#define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_PH_0 0x1b32 -#define regGC_CAC_WEIGHT_PH_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_PH_1 0x1b33 -#define regGC_CAC_WEIGHT_PH_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_PH_2 0x1b34 -#define regGC_CAC_WEIGHT_PH_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_PH_3 0x1b35 -#define regGC_CAC_WEIGHT_PH_3_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_0 0x1b36 -#define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_1 0x1b37 -#define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_2 0x1b38 -#define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_3 0x1b39 -#define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_4 0x1b3a -#define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 -#define regGC_CAC_WEIGHT_SDMA_5 0x1b3b -#define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 -#define regGC_CAC_WEIGHT_CHC_0 0x1b3c -#define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_CHC_1 0x1b3d -#define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GUS_0 0x1b3e -#define regGC_CAC_WEIGHT_GUS_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GUS_1 0x1b3f -#define regGC_CAC_WEIGHT_GUS_1_BASE_IDX 1 -#define regGC_CAC_WEIGHT_RLC_0 0x1b40 -#define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 -#define regGC_CAC_WEIGHT_GRBM_0 0x1b44 -#define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 -#define regGC_EDC_CLK_MONITOR_CTRL 0x1b56 -#define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 -#define regGC_CAC_IND_INDEX 0x1b58 -#define regGC_CAC_IND_INDEX_BASE_IDX 1 -#define regGC_CAC_IND_DATA 0x1b59 -#define regGC_CAC_IND_DATA_BASE_IDX 1 -#define regSE_CAC_CTRL_1 0x1b70 -#define regSE_CAC_CTRL_1_BASE_IDX 1 -#define regSE_CAC_CTRL_2 0x1b71 -#define regSE_CAC_CTRL_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TA_0 0x1b72 -#define regSE_CAC_WEIGHT_TA_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_0 0x1b73 -#define regSE_CAC_WEIGHT_TD_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_1 0x1b74 -#define regSE_CAC_WEIGHT_TD_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_2 0x1b75 -#define regSE_CAC_WEIGHT_TD_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_3 0x1b76 -#define regSE_CAC_WEIGHT_TD_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_4 0x1b77 -#define regSE_CAC_WEIGHT_TD_4_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TD_5 0x1b78 -#define regSE_CAC_WEIGHT_TD_5_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TCP_0 0x1b79 -#define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TCP_1 0x1b7a -#define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TCP_2 0x1b7b -#define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_TCP_3 0x1b7c -#define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SQ_0 0x1b7d -#define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SQ_1 0x1b7e -#define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SQ_2 0x1b7f -#define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SP_0 0x1b80 -#define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SP_1 0x1b81 -#define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_LDS_0 0x1b82 -#define regSE_CAC_WEIGHT_LDS_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_LDS_1 0x1b83 -#define regSE_CAC_WEIGHT_LDS_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_LDS_2 0x1b84 -#define regSE_CAC_WEIGHT_LDS_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_LDS_3 0x1b85 -#define regSE_CAC_WEIGHT_LDS_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SQC_0 0x1b87 -#define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SQC_1 0x1b88 -#define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CU_0 0x1b89 -#define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_BCI_0 0x1b8a -#define regSE_CAC_WEIGHT_BCI_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_0 0x1b8b -#define regSE_CAC_WEIGHT_CB_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_1 0x1b8c -#define regSE_CAC_WEIGHT_CB_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_2 0x1b8d -#define regSE_CAC_WEIGHT_CB_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_3 0x1b8e -#define regSE_CAC_WEIGHT_CB_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_4 0x1b8f -#define regSE_CAC_WEIGHT_CB_4_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_5 0x1b90 -#define regSE_CAC_WEIGHT_CB_5_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_6 0x1b91 -#define regSE_CAC_WEIGHT_CB_6_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_7 0x1b92 -#define regSE_CAC_WEIGHT_CB_7_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_8 0x1b93 -#define regSE_CAC_WEIGHT_CB_8_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_9 0x1b94 -#define regSE_CAC_WEIGHT_CB_9_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_10 0x1b95 -#define regSE_CAC_WEIGHT_CB_10_BASE_IDX 1 -#define regSE_CAC_WEIGHT_CB_11 0x1b96 -#define regSE_CAC_WEIGHT_CB_11_BASE_IDX 1 -#define regSE_CAC_WEIGHT_DB_0 0x1b97 -#define regSE_CAC_WEIGHT_DB_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_DB_1 0x1b98 -#define regSE_CAC_WEIGHT_DB_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_DB_2 0x1b99 -#define regSE_CAC_WEIGHT_DB_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_DB_3 0x1b9a -#define regSE_CAC_WEIGHT_DB_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_DB_4 0x1b9b -#define regSE_CAC_WEIGHT_DB_4_BASE_IDX 1 -#define regSE_CAC_WEIGHT_RMI_0 0x1b9c -#define regSE_CAC_WEIGHT_RMI_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_RMI_1 0x1b9d -#define regSE_CAC_WEIGHT_RMI_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SX_0 0x1b9e -#define regSE_CAC_WEIGHT_SX_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SXRB_0 0x1b9f -#define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_UTCL1_0 0x1ba0 -#define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_GL1C_0 0x1ba1 -#define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_GL1C_1 0x1ba2 -#define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_GL1C_2 0x1ba3 -#define regSE_CAC_WEIGHT_GL1C_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SPI_0 0x1ba4 -#define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SPI_1 0x1ba5 -#define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SPI_2 0x1ba6 -#define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_PC_0 0x1ba7 -#define regSE_CAC_WEIGHT_PC_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_PA_0 0x1ba8 -#define regSE_CAC_WEIGHT_PA_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_PA_1 0x1ba9 -#define regSE_CAC_WEIGHT_PA_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_PA_2 0x1baa -#define regSE_CAC_WEIGHT_PA_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_PA_3 0x1bab -#define regSE_CAC_WEIGHT_PA_3_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SC_0 0x1bac -#define regSE_CAC_WEIGHT_SC_0_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SC_1 0x1bad -#define regSE_CAC_WEIGHT_SC_1_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SC_2 0x1bae -#define regSE_CAC_WEIGHT_SC_2_BASE_IDX 1 -#define regSE_CAC_WEIGHT_SC_3 0x1baf -#define regSE_CAC_WEIGHT_SC_3_BASE_IDX 1 -#define regSE_CAC_WINDOW_AGGR_VALUE 0x1bb0 -#define regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX 1 -#define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1bb1 -#define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 -#define regSE_CAC_IND_INDEX 0x1bce -#define regSE_CAC_IND_INDEX_BASE_IDX 1 -#define regSE_CAC_IND_DATA 0x1bcf -#define regSE_CAC_IND_DATA_BASE_IDX 1 - - -// addressBlock: gc_pfonly2_spidec -// base address: 0x2f000 -#define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 -#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 -#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 -#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 -#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 -#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 -#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 -#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 -#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 -#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 -#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a -#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b -#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c -#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d -#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e -#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f -#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 -#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 -#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 -#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 -#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 -#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 -#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 -#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 -#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 -#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 -#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a -#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b -#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c -#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d -#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e -#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 -#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f -#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 - - -// addressBlock: gc_gfxudec -// base address: 0x30000 -#define regCP_EOP_DONE_ADDR_LO 0x2000 -#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 -#define regCP_EOP_DONE_ADDR_HI 0x2001 -#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 -#define regCP_EOP_DONE_DATA_LO 0x2002 -#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 -#define regCP_EOP_DONE_DATA_HI 0x2003 -#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 -#define regCP_EOP_LAST_FENCE_LO 0x2004 -#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 -#define regCP_EOP_LAST_FENCE_HI 0x2005 -#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 -#define regCP_PIPE_STATS_ADDR_LO 0x2018 -#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 -#define regCP_PIPE_STATS_ADDR_HI 0x2019 -#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 -#define regCP_VGT_IAVERT_COUNT_LO 0x201a -#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_IAVERT_COUNT_HI 0x201b -#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_IAPRIM_COUNT_LO 0x201c -#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_IAPRIM_COUNT_HI 0x201d -#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_GSPRIM_COUNT_LO 0x201e -#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_GSPRIM_COUNT_HI 0x201f -#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 -#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 -#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 -#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 -#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 -#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 -#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 -#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 -#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_PA_CINVOC_COUNT_LO 0x2028 -#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_PA_CINVOC_COUNT_HI 0x2029 -#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_PA_CPRIM_COUNT_LO 0x202a -#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 -#define regCP_PA_CPRIM_COUNT_HI 0x202b -#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 -#define regCP_SC_PSINVOC_COUNT0_LO 0x202c -#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 -#define regCP_SC_PSINVOC_COUNT0_HI 0x202d -#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 -#define regCP_SC_PSINVOC_COUNT1_LO 0x202e -#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 -#define regCP_SC_PSINVOC_COUNT1_HI 0x202f -#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 -#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 -#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 -#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_VGT_ASINVOC_COUNT_LO 0x2032 -#define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_VGT_ASINVOC_COUNT_HI 0x2033 -#define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_PIPE_STATS_CONTROL 0x203d -#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 -#define regSCRATCH_REG0 0x2040 -#define regSCRATCH_REG0_BASE_IDX 1 -#define regSCRATCH_REG1 0x2041 -#define regSCRATCH_REG1_BASE_IDX 1 -#define regSCRATCH_REG2 0x2042 -#define regSCRATCH_REG2_BASE_IDX 1 -#define regSCRATCH_REG3 0x2043 -#define regSCRATCH_REG3_BASE_IDX 1 -#define regSCRATCH_REG4 0x2044 -#define regSCRATCH_REG4_BASE_IDX 1 -#define regSCRATCH_REG5 0x2045 -#define regSCRATCH_REG5_BASE_IDX 1 -#define regSCRATCH_REG6 0x2046 -#define regSCRATCH_REG6_BASE_IDX 1 -#define regSCRATCH_REG7 0x2047 -#define regSCRATCH_REG7_BASE_IDX 1 -#define regSCRATCH_REG_ATOMIC 0x2048 -#define regSCRATCH_REG_ATOMIC_BASE_IDX 1 -#define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 -#define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 -#define regCP_APPEND_DDID_CNT 0x204b -#define regCP_APPEND_DDID_CNT_BASE_IDX 1 -#define regCP_APPEND_DATA_HI 0x204c -#define regCP_APPEND_DATA_HI_BASE_IDX 1 -#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d -#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 -#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e -#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 -#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 -#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 -#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 -#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 -#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 -#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 -#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 -#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 -#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define regCP_APPEND_ADDR_LO 0x2058 -#define regCP_APPEND_ADDR_LO_BASE_IDX 1 -#define regCP_APPEND_ADDR_HI 0x2059 -#define regCP_APPEND_ADDR_HI_BASE_IDX 1 -#define regCP_APPEND_DATA 0x205a -#define regCP_APPEND_DATA_BASE_IDX 1 -#define regCP_APPEND_DATA_LO 0x205a -#define regCP_APPEND_DATA_LO_BASE_IDX 1 -#define regCP_APPEND_LAST_CS_FENCE 0x205b -#define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 -#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b -#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 -#define regCP_APPEND_LAST_PS_FENCE 0x205c -#define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 -#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c -#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 -#define regCP_ATOMIC_PREOP_LO 0x205d -#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 -#define regCP_ME_ATOMIC_PREOP_LO 0x205d -#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 -#define regCP_ATOMIC_PREOP_HI 0x205e -#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 -#define regCP_ME_ATOMIC_PREOP_HI 0x205e -#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 -#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f -#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f -#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 -#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 -#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 -#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 -#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 -#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 -#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 -#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 -#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 -#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 -#define regCP_ME_MC_WADDR_LO 0x2069 -#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 -#define regCP_ME_MC_WADDR_HI 0x206a -#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 -#define regCP_ME_MC_WDATA_LO 0x206b -#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 -#define regCP_ME_MC_WDATA_HI 0x206c -#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 -#define regCP_ME_MC_RADDR_LO 0x206d -#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 -#define regCP_ME_MC_RADDR_HI 0x206e -#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 -#define regCP_SEM_WAIT_TIMER 0x206f -#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 -#define regCP_SIG_SEM_ADDR_LO 0x2070 -#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 -#define regCP_SIG_SEM_ADDR_HI 0x2071 -#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 -#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 -#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 -#define regCP_WAIT_SEM_ADDR_LO 0x2075 -#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 -#define regCP_WAIT_SEM_ADDR_HI 0x2076 -#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_PFP_CONTROL 0x2077 -#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 -#define regCP_DMA_ME_CONTROL 0x2078 -#define regCP_DMA_ME_CONTROL_BASE_IDX 1 -#define regCP_DMA_ME_SRC_ADDR 0x2080 -#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 -#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 -#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_ME_DST_ADDR 0x2082 -#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 -#define regCP_DMA_ME_DST_ADDR_HI 0x2083 -#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_ME_COMMAND 0x2084 -#define regCP_DMA_ME_COMMAND_BASE_IDX 1 -#define regCP_DMA_PFP_SRC_ADDR 0x2085 -#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 -#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 -#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_PFP_DST_ADDR 0x2087 -#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 -#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 -#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_PFP_COMMAND 0x2089 -#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 -#define regCP_DMA_CNTL 0x208a -#define regCP_DMA_CNTL_BASE_IDX 1 -#define regCP_DMA_READ_TAGS 0x208b -#define regCP_DMA_READ_TAGS_BASE_IDX 1 -#define regCP_PFP_IB_CONTROL 0x208d -#define regCP_PFP_IB_CONTROL_BASE_IDX 1 -#define regCP_PFP_LOAD_CONTROL 0x208e -#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 -#define regCP_SCRATCH_INDEX 0x208f -#define regCP_SCRATCH_INDEX_BASE_IDX 1 -#define regCP_SCRATCH_DATA 0x2090 -#define regCP_SCRATCH_DATA_BASE_IDX 1 -#define regCP_RB_OFFSET 0x2091 -#define regCP_RB_OFFSET_BASE_IDX 1 -#define regCP_IB2_OFFSET 0x2093 -#define regCP_IB2_OFFSET_BASE_IDX 1 -#define regCP_IB2_PREAMBLE_BEGIN 0x2096 -#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 -#define regCP_IB2_PREAMBLE_END 0x2097 -#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 -#define regCP_DMA_ME_CMD_ADDR_LO 0x209c -#define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 -#define regCP_DMA_ME_CMD_ADDR_HI 0x209d -#define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 -#define regCP_DMA_PFP_CMD_ADDR_LO 0x209e -#define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 -#define regCP_DMA_PFP_CMD_ADDR_HI 0x209f -#define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 -#define regCP_APPEND_CMD_ADDR_LO 0x20a0 -#define regCP_APPEND_CMD_ADDR_LO_BASE_IDX 1 -#define regCP_APPEND_CMD_ADDR_HI 0x20a1 -#define regCP_APPEND_CMD_ADDR_HI_BASE_IDX 1 -#define regUCONFIG_RESERVED_REG0 0x20a2 -#define regUCONFIG_RESERVED_REG0_BASE_IDX 1 -#define regUCONFIG_RESERVED_REG1 0x20a3 -#define regUCONFIG_RESERVED_REG1_BASE_IDX 1 -#define regCP_PA_MSPRIM_COUNT_LO 0x20a4 -#define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 -#define regCP_PA_MSPRIM_COUNT_HI 0x20a5 -#define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 -#define regCP_GE_MSINVOC_COUNT_LO 0x20a6 -#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 -#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 -#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 -#define regCP_IB1_CMD_BUFSZ 0x20c0 -#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 -#define regCP_IB2_CMD_BUFSZ 0x20c1 -#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 -#define regCP_ST_CMD_BUFSZ 0x20c2 -#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 -#define regCP_IB1_BASE_LO 0x20cc -#define regCP_IB1_BASE_LO_BASE_IDX 1 -#define regCP_IB1_BASE_HI 0x20cd -#define regCP_IB1_BASE_HI_BASE_IDX 1 -#define regCP_IB1_BUFSZ 0x20ce -#define regCP_IB1_BUFSZ_BASE_IDX 1 -#define regCP_IB2_BASE_LO 0x20cf -#define regCP_IB2_BASE_LO_BASE_IDX 1 -#define regCP_IB2_BASE_HI 0x20d0 -#define regCP_IB2_BASE_HI_BASE_IDX 1 -#define regCP_IB2_BUFSZ 0x20d1 -#define regCP_IB2_BUFSZ_BASE_IDX 1 -#define regCP_ST_BASE_LO 0x20d2 -#define regCP_ST_BASE_LO_BASE_IDX 1 -#define regCP_ST_BASE_HI 0x20d3 -#define regCP_ST_BASE_HI_BASE_IDX 1 -#define regCP_ST_BUFSZ 0x20d4 -#define regCP_ST_BUFSZ_BASE_IDX 1 -#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 -#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 -#define regCP_EOP_DONE_DATA_CNTL 0x20d6 -#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 -#define regCP_EOP_DONE_CNTX_ID 0x20d7 -#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 -#define regCP_DB_BASE_LO 0x20d8 -#define regCP_DB_BASE_LO_BASE_IDX 1 -#define regCP_DB_BASE_HI 0x20d9 -#define regCP_DB_BASE_HI_BASE_IDX 1 -#define regCP_DB_BUFSZ 0x20da -#define regCP_DB_BUFSZ_BASE_IDX 1 -#define regCP_DB_CMD_BUFSZ 0x20db -#define regCP_DB_CMD_BUFSZ_BASE_IDX 1 -#define regCP_PFP_COMPLETION_STATUS 0x20ec -#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 -#define regCP_PRED_NOT_VISIBLE 0x20ee -#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 -#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 -#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 -#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 -#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 -#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 -#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 -#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 -#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 -#define regCP_DISPATCH_INDR_ADDR 0x20f6 -#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 -#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 -#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 -#define regCP_INDEX_BASE_ADDR 0x20f8 -#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 -#define regCP_INDEX_BASE_ADDR_HI 0x20f9 -#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 -#define regCP_INDEX_TYPE 0x20fa -#define regCP_INDEX_TYPE_BASE_IDX 1 -#define regCP_GDS_BKUP_ADDR 0x20fb -#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 -#define regCP_GDS_BKUP_ADDR_HI 0x20fc -#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 -#define regCP_SAMPLE_STATUS 0x20fd -#define regCP_SAMPLE_STATUS_BASE_IDX 1 -#define regCP_ME_COHER_CNTL 0x20fe -#define regCP_ME_COHER_CNTL_BASE_IDX 1 -#define regCP_ME_COHER_SIZE 0x20ff -#define regCP_ME_COHER_SIZE_BASE_IDX 1 -#define regCP_ME_COHER_SIZE_HI 0x2100 -#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 -#define regCP_ME_COHER_BASE 0x2101 -#define regCP_ME_COHER_BASE_BASE_IDX 1 -#define regCP_ME_COHER_BASE_HI 0x2102 -#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 -#define regCP_ME_COHER_STATUS 0x2103 -#define regCP_ME_COHER_STATUS_BASE_IDX 1 -#define regRLC_GPM_PERF_COUNT_0 0x2140 -#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 -#define regRLC_GPM_PERF_COUNT_1 0x2141 -#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 -#define regGRBM_GFX_INDEX 0x2200 -#define regGRBM_GFX_INDEX_BASE_IDX 1 -#define regVGT_PRIMITIVE_TYPE 0x2242 -#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 -#define regVGT_INDEX_TYPE 0x2243 -#define regVGT_INDEX_TYPE_BASE_IDX 1 -#define regGE_MIN_VTX_INDX 0x2249 -#define regGE_MIN_VTX_INDX_BASE_IDX 1 -#define regGE_INDX_OFFSET 0x224a -#define regGE_INDX_OFFSET_BASE_IDX 1 -#define regGE_MULTI_PRIM_IB_RESET_EN 0x224b -#define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 -#define regVGT_NUM_INDICES 0x224c -#define regVGT_NUM_INDICES_BASE_IDX 1 -#define regVGT_NUM_INSTANCES 0x224d -#define regVGT_NUM_INSTANCES_BASE_IDX 1 -#define regVGT_TF_RING_SIZE 0x224e -#define regVGT_TF_RING_SIZE_BASE_IDX 1 -#define regVGT_HS_OFFCHIP_PARAM 0x224f -#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 -#define regVGT_TF_MEMORY_BASE 0x2250 -#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 -#define regGE_MAX_VTX_INDX 0x2259 -#define regGE_MAX_VTX_INDX_BASE_IDX 1 -#define regVGT_INSTANCE_BASE_ID 0x225a -#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 -#define regGE_CNTL 0x225b -#define regGE_CNTL_BASE_IDX 1 -#define regGE_USER_VGPR1 0x225c -#define regGE_USER_VGPR1_BASE_IDX 1 -#define regGE_USER_VGPR2 0x225d -#define regGE_USER_VGPR2_BASE_IDX 1 -#define regGE_USER_VGPR3 0x225e -#define regGE_USER_VGPR3_BASE_IDX 1 -#define regGE_STEREO_CNTL 0x225f -#define regGE_STEREO_CNTL_BASE_IDX 1 -#define regGE_PC_ALLOC 0x2260 -#define regGE_PC_ALLOC_BASE_IDX 1 -#define regVGT_TF_MEMORY_BASE_HI 0x2261 -#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 -#define regGE_USER_VGPR_EN 0x2262 -#define regGE_USER_VGPR_EN_BASE_IDX 1 -#define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 -#define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 -#define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 -#define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 -#define regVGT_GS_OUT_PRIM_TYPE 0x2266 -#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 -#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 -#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 -#define regPA_SC_LINE_STIPPLE_STATE 0x2281 -#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 -#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 -#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 -#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 -#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 -#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 -#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 -#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b -#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 -#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 -#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 -#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 -#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 -#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 -#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 -#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa -#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab -#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac -#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 -#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_H 0x22b1 -#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_V 0x22b2 -#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 -#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 -#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 -#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 -#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 -#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 -#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 -#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_4 0x2344 -#define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_5 0x2345 -#define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_6 0x2346 -#define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 -#define regSQ_THREAD_TRACE_USERDATA_7 0x2347 -#define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 -#define regSQC_CACHES 0x2348 -#define regSQC_CACHES_BASE_IDX 1 -#define regTA_CS_BC_BASE_ADDR 0x2380 -#define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 -#define regTA_CS_BC_BASE_ADDR_HI 0x2381 -#define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 -#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT0_HI 0x23c1 -#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 -#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT1_HI 0x23c3 -#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 -#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT2_HI 0x23c5 -#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 -#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 -#define regDB_OCCLUSION_COUNT3_HI 0x23c7 -#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 -#define regGDS_RD_ADDR 0x2400 -#define regGDS_RD_ADDR_BASE_IDX 1 -#define regGDS_RD_DATA 0x2401 -#define regGDS_RD_DATA_BASE_IDX 1 -#define regGDS_RD_BURST_ADDR 0x2402 -#define regGDS_RD_BURST_ADDR_BASE_IDX 1 -#define regGDS_RD_BURST_COUNT 0x2403 -#define regGDS_RD_BURST_COUNT_BASE_IDX 1 -#define regGDS_RD_BURST_DATA 0x2404 -#define regGDS_RD_BURST_DATA_BASE_IDX 1 -#define regGDS_WR_ADDR 0x2405 -#define regGDS_WR_ADDR_BASE_IDX 1 -#define regGDS_WR_DATA 0x2406 -#define regGDS_WR_DATA_BASE_IDX 1 -#define regGDS_WR_BURST_ADDR 0x2407 -#define regGDS_WR_BURST_ADDR_BASE_IDX 1 -#define regGDS_WR_BURST_DATA 0x2408 -#define regGDS_WR_BURST_DATA_BASE_IDX 1 -#define regGDS_WRITE_COMPLETE 0x2409 -#define regGDS_WRITE_COMPLETE_BASE_IDX 1 -#define regGDS_ATOM_CNTL 0x240a -#define regGDS_ATOM_CNTL_BASE_IDX 1 -#define regGDS_ATOM_COMPLETE 0x240b -#define regGDS_ATOM_COMPLETE_BASE_IDX 1 -#define regGDS_ATOM_BASE 0x240c -#define regGDS_ATOM_BASE_BASE_IDX 1 -#define regGDS_ATOM_SIZE 0x240d -#define regGDS_ATOM_SIZE_BASE_IDX 1 -#define regGDS_ATOM_OFFSET0 0x240e -#define regGDS_ATOM_OFFSET0_BASE_IDX 1 -#define regGDS_ATOM_OFFSET1 0x240f -#define regGDS_ATOM_OFFSET1_BASE_IDX 1 -#define regGDS_ATOM_DST 0x2410 -#define regGDS_ATOM_DST_BASE_IDX 1 -#define regGDS_ATOM_OP 0x2411 -#define regGDS_ATOM_OP_BASE_IDX 1 -#define regGDS_ATOM_SRC0 0x2412 -#define regGDS_ATOM_SRC0_BASE_IDX 1 -#define regGDS_ATOM_SRC0_U 0x2413 -#define regGDS_ATOM_SRC0_U_BASE_IDX 1 -#define regGDS_ATOM_SRC1 0x2414 -#define regGDS_ATOM_SRC1_BASE_IDX 1 -#define regGDS_ATOM_SRC1_U 0x2415 -#define regGDS_ATOM_SRC1_U_BASE_IDX 1 -#define regGDS_ATOM_READ0 0x2416 -#define regGDS_ATOM_READ0_BASE_IDX 1 -#define regGDS_ATOM_READ0_U 0x2417 -#define regGDS_ATOM_READ0_U_BASE_IDX 1 -#define regGDS_ATOM_READ1 0x2418 -#define regGDS_ATOM_READ1_BASE_IDX 1 -#define regGDS_ATOM_READ1_U 0x2419 -#define regGDS_ATOM_READ1_U_BASE_IDX 1 -#define regGDS_GWS_RESOURCE_CNTL 0x241a -#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 -#define regGDS_GWS_RESOURCE 0x241b -#define regGDS_GWS_RESOURCE_BASE_IDX 1 -#define regGDS_GWS_RESOURCE_CNT 0x241c -#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 -#define regGDS_OA_CNTL 0x241d -#define regGDS_OA_CNTL_BASE_IDX 1 -#define regGDS_OA_COUNTER 0x241e -#define regGDS_OA_COUNTER_BASE_IDX 1 -#define regGDS_OA_ADDRESS 0x241f -#define regGDS_OA_ADDRESS_BASE_IDX 1 -#define regGDS_OA_INCDEC 0x2420 -#define regGDS_OA_INCDEC_BASE_IDX 1 -#define regGDS_OA_RING_SIZE 0x2421 -#define regGDS_OA_RING_SIZE_BASE_IDX 1 -#define regGDS_STRMOUT_DWORDS_WRITTEN_0 0x2422 -#define regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX 1 -#define regGDS_STRMOUT_DWORDS_WRITTEN_1 0x2423 -#define regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX 1 -#define regGDS_STRMOUT_DWORDS_WRITTEN_2 0x2424 -#define regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX 1 -#define regGDS_STRMOUT_DWORDS_WRITTEN_3 0x2425 -#define regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX 1 -#define regGDS_GS_0 0x2426 -#define regGDS_GS_0_BASE_IDX 1 -#define regGDS_GS_1 0x2427 -#define regGDS_GS_1_BASE_IDX 1 -#define regGDS_GS_2 0x2428 -#define regGDS_GS_2_BASE_IDX 1 -#define regGDS_GS_3 0x2429 -#define regGDS_GS_3_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO 0x242a -#define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI 0x242b -#define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO 0x242c -#define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI 0x242d -#define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO 0x242e -#define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI 0x242f -#define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO 0x2430 -#define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI 0x2431 -#define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO 0x2432 -#define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI 0x2433 -#define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO 0x2434 -#define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI 0x2435 -#define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO 0x2436 -#define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI 0x2437 -#define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO 0x2438 -#define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX 1 -#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI 0x2439 -#define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX 1 -#define regSPI_CONFIG_CNTL 0x2440 -#define regSPI_CONFIG_CNTL_BASE_IDX 1 -#define regSPI_CONFIG_CNTL_1 0x2441 -#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 -#define regSPI_CONFIG_CNTL_2 0x2442 -#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 -#define regSPI_WAVE_LIMIT_CNTL 0x2443 -#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 -#define regSPI_GS_THROTTLE_CNTL1 0x2444 -#define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 -#define regSPI_GS_THROTTLE_CNTL2 0x2445 -#define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 -#define regSPI_ATTRIBUTE_RING_BASE 0x2446 -#define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 -#define regSPI_ATTRIBUTE_RING_SIZE 0x2447 -#define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 - - -// addressBlock: gc_cprs64dec -// base address: 0x32000 -#define regCP_MES_PRGRM_CNTR_START 0x2800 -#define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 -#define regCP_MES_INTR_ROUTINE_START 0x2801 -#define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 -#define regCP_MES_MTVEC_LO 0x2801 -#define regCP_MES_MTVEC_LO_BASE_IDX 1 -#define regCP_MES_INTR_ROUTINE_START_HI 0x2802 -#define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 -#define regCP_MES_MTVEC_HI 0x2802 -#define regCP_MES_MTVEC_HI_BASE_IDX 1 -#define regCP_MES_CNTL 0x2807 -#define regCP_MES_CNTL_BASE_IDX 1 -#define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 -#define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 -#define regCP_MES_PIPE0_PRIORITY 0x2809 -#define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 -#define regCP_MES_PIPE1_PRIORITY 0x280a -#define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 -#define regCP_MES_PIPE2_PRIORITY 0x280b -#define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 -#define regCP_MES_PIPE3_PRIORITY 0x280c -#define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 -#define regCP_MES_HEADER_DUMP 0x280d -#define regCP_MES_HEADER_DUMP_BASE_IDX 1 -#define regCP_MES_MIE_LO 0x280e -#define regCP_MES_MIE_LO_BASE_IDX 1 -#define regCP_MES_MIE_HI 0x280f -#define regCP_MES_MIE_HI_BASE_IDX 1 -#define regCP_MES_INTERRUPT 0x2810 -#define regCP_MES_INTERRUPT_BASE_IDX 1 -#define regCP_MES_SCRATCH_INDEX 0x2811 -#define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 -#define regCP_MES_SCRATCH_DATA 0x2812 -#define regCP_MES_SCRATCH_DATA_BASE_IDX 1 -#define regCP_MES_INSTR_PNTR 0x2813 -#define regCP_MES_INSTR_PNTR_BASE_IDX 1 -#define regCP_MES_MSCRATCH_HI 0x2814 -#define regCP_MES_MSCRATCH_HI_BASE_IDX 1 -#define regCP_MES_MSCRATCH_LO 0x2815 -#define regCP_MES_MSCRATCH_LO_BASE_IDX 1 -#define regCP_MES_MSTATUS_LO 0x2816 -#define regCP_MES_MSTATUS_LO_BASE_IDX 1 -#define regCP_MES_MSTATUS_HI 0x2817 -#define regCP_MES_MSTATUS_HI_BASE_IDX 1 -#define regCP_MES_MEPC_LO 0x2818 -#define regCP_MES_MEPC_LO_BASE_IDX 1 -#define regCP_MES_MEPC_HI 0x2819 -#define regCP_MES_MEPC_HI_BASE_IDX 1 -#define regCP_MES_MCAUSE_LO 0x281a -#define regCP_MES_MCAUSE_LO_BASE_IDX 1 -#define regCP_MES_MCAUSE_HI 0x281b -#define regCP_MES_MCAUSE_HI_BASE_IDX 1 -#define regCP_MES_MBADADDR_LO 0x281c -#define regCP_MES_MBADADDR_LO_BASE_IDX 1 -#define regCP_MES_MBADADDR_HI 0x281d -#define regCP_MES_MBADADDR_HI_BASE_IDX 1 -#define regCP_MES_MIP_LO 0x281e -#define regCP_MES_MIP_LO_BASE_IDX 1 -#define regCP_MES_MIP_HI 0x281f -#define regCP_MES_MIP_HI_BASE_IDX 1 -#define regCP_MES_IC_OP_CNTL 0x2820 -#define regCP_MES_IC_OP_CNTL_BASE_IDX 1 -#define regCP_MES_MCYCLE_LO 0x2826 -#define regCP_MES_MCYCLE_LO_BASE_IDX 1 -#define regCP_MES_MCYCLE_HI 0x2827 -#define regCP_MES_MCYCLE_HI_BASE_IDX 1 -#define regCP_MES_MTIME_LO 0x2828 -#define regCP_MES_MTIME_LO_BASE_IDX 1 -#define regCP_MES_MTIME_HI 0x2829 -#define regCP_MES_MTIME_HI_BASE_IDX 1 -#define regCP_MES_MINSTRET_LO 0x282a -#define regCP_MES_MINSTRET_LO_BASE_IDX 1 -#define regCP_MES_MINSTRET_HI 0x282b -#define regCP_MES_MINSTRET_HI_BASE_IDX 1 -#define regCP_MES_MISA_LO 0x282c -#define regCP_MES_MISA_LO_BASE_IDX 1 -#define regCP_MES_MISA_HI 0x282d -#define regCP_MES_MISA_HI_BASE_IDX 1 -#define regCP_MES_MVENDORID_LO 0x282e -#define regCP_MES_MVENDORID_LO_BASE_IDX 1 -#define regCP_MES_MVENDORID_HI 0x282f -#define regCP_MES_MVENDORID_HI_BASE_IDX 1 -#define regCP_MES_MARCHID_LO 0x2830 -#define regCP_MES_MARCHID_LO_BASE_IDX 1 -#define regCP_MES_MARCHID_HI 0x2831 -#define regCP_MES_MARCHID_HI_BASE_IDX 1 -#define regCP_MES_MIMPID_LO 0x2832 -#define regCP_MES_MIMPID_LO_BASE_IDX 1 -#define regCP_MES_MIMPID_HI 0x2833 -#define regCP_MES_MIMPID_HI_BASE_IDX 1 -#define regCP_MES_MHARTID_LO 0x2834 -#define regCP_MES_MHARTID_LO_BASE_IDX 1 -#define regCP_MES_MHARTID_HI 0x2835 -#define regCP_MES_MHARTID_HI_BASE_IDX 1 -#define regCP_MES_DC_BASE_CNTL 0x2836 -#define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 -#define regCP_MES_DC_OP_CNTL 0x2837 -#define regCP_MES_DC_OP_CNTL_BASE_IDX 1 -#define regCP_MES_MTIMECMP_LO 0x2838 -#define regCP_MES_MTIMECMP_LO_BASE_IDX 1 -#define regCP_MES_MTIMECMP_HI 0x2839 -#define regCP_MES_MTIMECMP_HI_BASE_IDX 1 -#define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a -#define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 -#define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b -#define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL1 0x283c -#define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL2 0x283d -#define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL3 0x283e -#define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL4 0x283f -#define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL5 0x2840 -#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 -#define regCP_MES_DOORBELL_CONTROL6 0x2841 -#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 -#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842 -#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 -#define regCP_MES_GP0_LO 0x2843 -#define regCP_MES_GP0_LO_BASE_IDX 1 -#define regCP_MES_GP0_HI 0x2844 -#define regCP_MES_GP0_HI_BASE_IDX 1 -#define regCP_MES_GP1_LO 0x2845 -#define regCP_MES_GP1_LO_BASE_IDX 1 -#define regCP_MES_GP1_HI 0x2846 -#define regCP_MES_GP1_HI_BASE_IDX 1 -#define regCP_MES_GP2_LO 0x2847 -#define regCP_MES_GP2_LO_BASE_IDX 1 -#define regCP_MES_GP2_HI 0x2848 -#define regCP_MES_GP2_HI_BASE_IDX 1 -#define regCP_MES_GP3_LO 0x2849 -#define regCP_MES_GP3_LO_BASE_IDX 1 -#define regCP_MES_GP3_HI 0x284a -#define regCP_MES_GP3_HI_BASE_IDX 1 -#define regCP_MES_GP4_LO 0x284b -#define regCP_MES_GP4_LO_BASE_IDX 1 -#define regCP_MES_GP4_HI 0x284c -#define regCP_MES_GP4_HI_BASE_IDX 1 -#define regCP_MES_GP5_LO 0x284d -#define regCP_MES_GP5_LO_BASE_IDX 1 -#define regCP_MES_GP5_HI 0x284e -#define regCP_MES_GP5_HI_BASE_IDX 1 -#define regCP_MES_GP6_LO 0x284f -#define regCP_MES_GP6_LO_BASE_IDX 1 -#define regCP_MES_GP6_HI 0x2850 -#define regCP_MES_GP6_HI_BASE_IDX 1 -#define regCP_MES_GP7_LO 0x2851 -#define regCP_MES_GP7_LO_BASE_IDX 1 -#define regCP_MES_GP7_HI 0x2852 -#define regCP_MES_GP7_HI_BASE_IDX 1 -#define regCP_MES_GP8_LO 0x2853 -#define regCP_MES_GP8_LO_BASE_IDX 1 -#define regCP_MES_GP8_HI 0x2854 -#define regCP_MES_GP8_HI_BASE_IDX 1 -#define regCP_MES_GP9_LO 0x2855 -#define regCP_MES_GP9_LO_BASE_IDX 1 -#define regCP_MES_GP9_HI 0x2856 -#define regCP_MES_GP9_HI_BASE_IDX 1 -#define regCP_MES_LOCAL_BASE0_LO 0x2883 -#define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 -#define regCP_MES_LOCAL_BASE0_HI 0x2884 -#define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 -#define regCP_MES_LOCAL_MASK0_LO 0x2885 -#define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 -#define regCP_MES_LOCAL_MASK0_HI 0x2886 -#define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 -#define regCP_MES_LOCAL_APERTURE 0x2887 -#define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 -#define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 -#define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 -#define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 -#define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 -#define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a -#define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 -#define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b -#define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 -#define regCP_MES_LOCAL_INSTR_APERTURE 0x288c -#define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 -#define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d -#define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 -#define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e -#define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 -#define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f -#define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 -#define regCP_MES_PERFCOUNT_CNTL 0x2899 -#define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 -#define regCP_MES_PENDING_INTERRUPT 0x289a -#define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 -#define regCP_MES_PRGRM_CNTR_START_HI 0x289d -#define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_16 0x289f -#define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_17 0x28a0 -#define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_18 0x28a1 -#define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_19 0x28a2 -#define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_20 0x28a3 -#define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_21 0x28a4 -#define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_22 0x28a5 -#define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_23 0x28a6 -#define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_24 0x28a7 -#define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_25 0x28a8 -#define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_26 0x28a9 -#define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_27 0x28aa -#define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_28 0x28ab -#define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_29 0x28ac -#define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_30 0x28ad -#define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 -#define regCP_MES_INTERRUPT_DATA_31 0x28ae -#define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 -#define regCP_MES_DC_APERTURE0_BASE 0x28af -#define regCP_MES_DC_APERTURE0_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE0_MASK 0x28b0 -#define regCP_MES_DC_APERTURE0_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE0_CNTL 0x28b1 -#define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE1_BASE 0x28b2 -#define regCP_MES_DC_APERTURE1_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE1_MASK 0x28b3 -#define regCP_MES_DC_APERTURE1_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE1_CNTL 0x28b4 -#define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE2_BASE 0x28b5 -#define regCP_MES_DC_APERTURE2_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE2_MASK 0x28b6 -#define regCP_MES_DC_APERTURE2_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE2_CNTL 0x28b7 -#define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE3_BASE 0x28b8 -#define regCP_MES_DC_APERTURE3_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE3_MASK 0x28b9 -#define regCP_MES_DC_APERTURE3_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE3_CNTL 0x28ba -#define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE4_BASE 0x28bb -#define regCP_MES_DC_APERTURE4_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE4_MASK 0x28bc -#define regCP_MES_DC_APERTURE4_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE4_CNTL 0x28bd -#define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE5_BASE 0x28be -#define regCP_MES_DC_APERTURE5_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE5_MASK 0x28bf -#define regCP_MES_DC_APERTURE5_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE5_CNTL 0x28c0 -#define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE6_BASE 0x28c1 -#define regCP_MES_DC_APERTURE6_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE6_MASK 0x28c2 -#define regCP_MES_DC_APERTURE6_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE6_CNTL 0x28c3 -#define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE7_BASE 0x28c4 -#define regCP_MES_DC_APERTURE7_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE7_MASK 0x28c5 -#define regCP_MES_DC_APERTURE7_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE7_CNTL 0x28c6 -#define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE8_BASE 0x28c7 -#define regCP_MES_DC_APERTURE8_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE8_MASK 0x28c8 -#define regCP_MES_DC_APERTURE8_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE8_CNTL 0x28c9 -#define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE9_BASE 0x28ca -#define regCP_MES_DC_APERTURE9_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE9_MASK 0x28cb -#define regCP_MES_DC_APERTURE9_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE9_CNTL 0x28cc -#define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE10_BASE 0x28cd -#define regCP_MES_DC_APERTURE10_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE10_MASK 0x28ce -#define regCP_MES_DC_APERTURE10_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE10_CNTL 0x28cf -#define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE11_BASE 0x28d0 -#define regCP_MES_DC_APERTURE11_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE11_MASK 0x28d1 -#define regCP_MES_DC_APERTURE11_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE11_CNTL 0x28d2 -#define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE12_BASE 0x28d3 -#define regCP_MES_DC_APERTURE12_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE12_MASK 0x28d4 -#define regCP_MES_DC_APERTURE12_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE12_CNTL 0x28d5 -#define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE13_BASE 0x28d6 -#define regCP_MES_DC_APERTURE13_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE13_MASK 0x28d7 -#define regCP_MES_DC_APERTURE13_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE13_CNTL 0x28d8 -#define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE14_BASE 0x28d9 -#define regCP_MES_DC_APERTURE14_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE14_MASK 0x28da -#define regCP_MES_DC_APERTURE14_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE14_CNTL 0x28db -#define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX 1 -#define regCP_MES_DC_APERTURE15_BASE 0x28dc -#define regCP_MES_DC_APERTURE15_BASE_BASE_IDX 1 -#define regCP_MES_DC_APERTURE15_MASK 0x28dd -#define regCP_MES_DC_APERTURE15_MASK_BASE_IDX 1 -#define regCP_MES_DC_APERTURE15_CNTL 0x28de -#define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX 1 -#define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 -#define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 -#define regCP_MEC_MTVEC_LO 0x2901 -#define regCP_MEC_MTVEC_LO_BASE_IDX 1 -#define regCP_MEC_MTVEC_HI 0x2902 -#define regCP_MEC_MTVEC_HI_BASE_IDX 1 -#define regCP_MEC_ISA_CNTL 0x2903 -#define regCP_MEC_ISA_CNTL_BASE_IDX 1 -#define regCP_MEC_RS64_CNTL 0x2904 -#define regCP_MEC_RS64_CNTL_BASE_IDX 1 -#define regCP_MEC_MIE_LO 0x2905 -#define regCP_MEC_MIE_LO_BASE_IDX 1 -#define regCP_MEC_MIE_HI 0x2906 -#define regCP_MEC_MIE_HI_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT 0x2907 -#define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 -#define regCP_MEC_RS64_INSTR_PNTR 0x2908 -#define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 -#define regCP_MEC_MIP_LO 0x2909 -#define regCP_MEC_MIP_LO_BASE_IDX 1 -#define regCP_MEC_MIP_HI 0x290a -#define regCP_MEC_MIP_HI_BASE_IDX 1 -#define regCP_MEC_DC_BASE_CNTL 0x290b -#define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_OP_CNTL 0x290c -#define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 -#define regCP_MEC_MTIMECMP_LO 0x290d -#define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 -#define regCP_MEC_MTIMECMP_HI 0x290e -#define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 -#define regCP_MEC_GP0_LO 0x2910 -#define regCP_MEC_GP0_LO_BASE_IDX 1 -#define regCP_MEC_GP0_HI 0x2911 -#define regCP_MEC_GP0_HI_BASE_IDX 1 -#define regCP_MEC_GP1_LO 0x2912 -#define regCP_MEC_GP1_LO_BASE_IDX 1 -#define regCP_MEC_GP1_HI 0x2913 -#define regCP_MEC_GP1_HI_BASE_IDX 1 -#define regCP_MEC_GP2_LO 0x2914 -#define regCP_MEC_GP2_LO_BASE_IDX 1 -#define regCP_MEC_GP2_HI 0x2915 -#define regCP_MEC_GP2_HI_BASE_IDX 1 -#define regCP_MEC_GP3_LO 0x2916 -#define regCP_MEC_GP3_LO_BASE_IDX 1 -#define regCP_MEC_GP3_HI 0x2917 -#define regCP_MEC_GP3_HI_BASE_IDX 1 -#define regCP_MEC_GP4_LO 0x2918 -#define regCP_MEC_GP4_LO_BASE_IDX 1 -#define regCP_MEC_GP4_HI 0x2919 -#define regCP_MEC_GP4_HI_BASE_IDX 1 -#define regCP_MEC_GP5_LO 0x291a -#define regCP_MEC_GP5_LO_BASE_IDX 1 -#define regCP_MEC_GP5_HI 0x291b -#define regCP_MEC_GP5_HI_BASE_IDX 1 -#define regCP_MEC_GP6_LO 0x291c -#define regCP_MEC_GP6_LO_BASE_IDX 1 -#define regCP_MEC_GP6_HI 0x291d -#define regCP_MEC_GP6_HI_BASE_IDX 1 -#define regCP_MEC_GP7_LO 0x291e -#define regCP_MEC_GP7_LO_BASE_IDX 1 -#define regCP_MEC_GP7_HI 0x291f -#define regCP_MEC_GP7_HI_BASE_IDX 1 -#define regCP_MEC_GP8_LO 0x2920 -#define regCP_MEC_GP8_LO_BASE_IDX 1 -#define regCP_MEC_GP8_HI 0x2921 -#define regCP_MEC_GP8_HI_BASE_IDX 1 -#define regCP_MEC_GP9_LO 0x2922 -#define regCP_MEC_GP9_LO_BASE_IDX 1 -#define regCP_MEC_GP9_HI 0x2923 -#define regCP_MEC_GP9_HI_BASE_IDX 1 -#define regCP_MEC_LOCAL_BASE0_LO 0x2927 -#define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 -#define regCP_MEC_LOCAL_BASE0_HI 0x2928 -#define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 -#define regCP_MEC_LOCAL_MASK0_LO 0x2929 -#define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 -#define regCP_MEC_LOCAL_MASK0_HI 0x292a -#define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 -#define regCP_MEC_LOCAL_APERTURE 0x292b -#define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 -#define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c -#define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 -#define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d -#define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 -#define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e -#define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 -#define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f -#define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 -#define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 -#define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 -#define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 -#define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 -#define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 -#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 -#define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 -#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 -#define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 -#define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 -#define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 -#define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 -#define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 -#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a -#define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b -#define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c -#define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d -#define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e -#define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f -#define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 -#define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 -#define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 -#define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 -#define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 -#define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 -#define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 -#define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 -#define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 -#define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 -#define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 -#define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE0_BASE 0x294a -#define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE0_MASK 0x294b -#define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE0_CNTL 0x294c -#define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE1_BASE 0x294d -#define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE1_MASK 0x294e -#define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE1_CNTL 0x294f -#define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE2_BASE 0x2950 -#define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE2_MASK 0x2951 -#define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE2_CNTL 0x2952 -#define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE3_BASE 0x2953 -#define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE3_MASK 0x2954 -#define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE3_CNTL 0x2955 -#define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE4_BASE 0x2956 -#define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE4_MASK 0x2957 -#define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE4_CNTL 0x2958 -#define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE5_BASE 0x2959 -#define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE5_MASK 0x295a -#define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE5_CNTL 0x295b -#define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE6_BASE 0x295c -#define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE6_MASK 0x295d -#define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE6_CNTL 0x295e -#define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE7_BASE 0x295f -#define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE7_MASK 0x2960 -#define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE7_CNTL 0x2961 -#define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE8_BASE 0x2962 -#define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE8_MASK 0x2963 -#define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE8_CNTL 0x2964 -#define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE9_BASE 0x2965 -#define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE9_MASK 0x2966 -#define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE9_CNTL 0x2967 -#define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE10_BASE 0x2968 -#define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE10_MASK 0x2969 -#define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE10_CNTL 0x296a -#define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE11_BASE 0x296b -#define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE11_MASK 0x296c -#define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE11_CNTL 0x296d -#define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE12_BASE 0x296e -#define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE12_MASK 0x296f -#define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE12_CNTL 0x2970 -#define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE13_BASE 0x2971 -#define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE13_MASK 0x2972 -#define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE13_CNTL 0x2973 -#define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE14_BASE 0x2974 -#define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE14_MASK 0x2975 -#define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE14_CNTL 0x2976 -#define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE15_BASE 0x2977 -#define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE15_MASK 0x2978 -#define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX 1 -#define regCP_MEC_DC_APERTURE15_CNTL 0x2979 -#define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX 1 -#define regCP_CPC_IC_OP_CNTL 0x297a -#define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 -#define regCP_GFX_CNTL 0x2a00 -#define regCP_GFX_CNTL_BASE_IDX 1 -#define regCP_GFX_RS64_INTERRUPT0 0x2a01 -#define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 -#define regCP_GFX_RS64_INTR_EN0 0x2a02 -#define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 -#define regCP_GFX_RS64_INTR_EN1 0x2a03 -#define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 -#define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 -#define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 -#define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a -#define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b -#define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c -#define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d -#define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e -#define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f -#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 -#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 -#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 -#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 -#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 -#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 -#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 -#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 -#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 -#define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a -#define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b -#define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_MIP_LO0 0x2a1c -#define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_MIP_LO1 0x2a1d -#define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_MIP_HI0 0x2a1e -#define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_MIP_HI1 0x2a1f -#define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 -#define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 -#define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 -#define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 -#define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP0_LO0 0x2a24 -#define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP0_LO1 0x2a25 -#define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP0_HI0 0x2a26 -#define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP0_HI1 0x2a27 -#define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP1_LO0 0x2a28 -#define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP1_LO1 0x2a29 -#define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP1_HI0 0x2a2a -#define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP1_HI1 0x2a2b -#define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP2_LO0 0x2a2c -#define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP2_LO1 0x2a2d -#define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP2_HI0 0x2a2e -#define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP2_HI1 0x2a2f -#define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP3_LO0 0x2a30 -#define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP3_LO1 0x2a31 -#define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP3_HI0 0x2a32 -#define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP3_HI1 0x2a33 -#define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP4_LO0 0x2a34 -#define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP4_LO1 0x2a35 -#define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP4_HI0 0x2a36 -#define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP4_HI1 0x2a37 -#define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP5_LO0 0x2a38 -#define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 -#define regCP_GFX_RS64_GP5_LO1 0x2a39 -#define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 -#define regCP_GFX_RS64_GP5_HI0 0x2a3a -#define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 -#define regCP_GFX_RS64_GP5_HI1 0x2a3b -#define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 -#define regCP_GFX_RS64_GP6_LO 0x2a3c -#define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 -#define regCP_GFX_RS64_GP6_HI 0x2a3d -#define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 -#define regCP_GFX_RS64_GP7_LO 0x2a3e -#define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 -#define regCP_GFX_RS64_GP7_HI 0x2a3f -#define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 -#define regCP_GFX_RS64_GP8_LO 0x2a40 -#define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 -#define regCP_GFX_RS64_GP8_HI 0x2a41 -#define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 -#define regCP_GFX_RS64_GP9_LO 0x2a42 -#define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 -#define regCP_GFX_RS64_GP9_HI 0x2a43 -#define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 -#define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 -#define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 -#define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 -#define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 -#define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 -#define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 -#define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 -#define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 -#define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a -#define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b -#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c -#define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d -#define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e -#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f -#define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 -#define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 -#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 -#define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 -#define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 -#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 -#define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 -#define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 -#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 -#define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 -#define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a -#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b -#define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c -#define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d -#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e -#define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f -#define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 -#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 -#define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 -#define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 -#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 -#define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 -#define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 -#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 -#define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 -#define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 -#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a -#define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b -#define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c -#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d -#define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e -#define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f -#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 -#define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 -#define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 -#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 -#define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 -#define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 -#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 -#define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 -#define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 -#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 -#define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a -#define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b -#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c -#define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d -#define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e -#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f -#define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 -#define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 -#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 -#define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 -#define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 -#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 -#define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 -#define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 -#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 -#define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 -#define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a -#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b -#define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c -#define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d -#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e -#define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f -#define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 -#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 -#define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 -#define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 -#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 -#define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 -#define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 -#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 -#define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 -#define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 -#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a -#define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b -#define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c -#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d -#define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e -#define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f -#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 -#define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 -#define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 -#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 -#define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 -#define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 -#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 -#define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 -#define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 -#define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 -#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 -#define regCP_GFX_RS64_INTERRUPT1 0x2aac -#define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 - - -// addressBlock: gc_gl1dec -// base address: 0x33400 -#define regGL1_DRAM_BURST_MASK 0x2d02 -#define regGL1_DRAM_BURST_MASK_BASE_IDX 1 -#define regGL1_ARB_STATUS 0x2d03 -#define regGL1_ARB_STATUS_BASE_IDX 1 -#define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 -#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 -#define regGL1C_STATUS 0x2d41 -#define regGL1C_STATUS_BASE_IDX 1 -#define regGL1C_UTCL0_CNTL1 0x2d42 -#define regGL1C_UTCL0_CNTL1_BASE_IDX 1 -#define regGL1C_UTCL0_CNTL2 0x2d43 -#define regGL1C_UTCL0_CNTL2_BASE_IDX 1 -#define regGL1C_UTCL0_STATUS 0x2d44 -#define regGL1C_UTCL0_STATUS_BASE_IDX 1 -#define regGL1C_UTCL0_RETRY 0x2d45 -#define regGL1C_UTCL0_RETRY_BASE_IDX 1 - - -// addressBlock: gc_chdec -// base address: 0x33600 -#define regCH_ARB_CTRL 0x2d80 -#define regCH_ARB_CTRL_BASE_IDX 1 -#define regCH_DRAM_BURST_MASK 0x2d82 -#define regCH_DRAM_BURST_MASK_BASE_IDX 1 -#define regCH_ARB_STATUS 0x2d83 -#define regCH_ARB_STATUS_BASE_IDX 1 -#define regCH_DRAM_BURST_CTRL 0x2d84 -#define regCH_DRAM_BURST_CTRL_BASE_IDX 1 -#define regCHA_CHC_CREDITS 0x2d88 -#define regCHA_CHC_CREDITS_BASE_IDX 1 -#define regCHA_CLIENT_FREE_DELAY 0x2d89 -#define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 -#define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c -#define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 -#define regCH_VC5_ENABLE 0x2d94 -#define regCH_VC5_ENABLE_BASE_IDX 1 -#define regCHC_CTRL 0x2dc0 -#define regCHC_CTRL_BASE_IDX 1 -#define regCHC_STATUS 0x2dc1 -#define regCHC_STATUS_BASE_IDX 1 -#define regCHCG_CTRL 0x2dc2 -#define regCHCG_CTRL_BASE_IDX 1 -#define regCHCG_STATUS 0x2dc3 -#define regCHCG_STATUS_BASE_IDX 1 - - -// addressBlock: gc_gl2dec -// base address: 0x33800 -#define regGL2C_CTRL 0x2e00 -#define regGL2C_CTRL_BASE_IDX 1 -#define regGL2C_CTRL2 0x2e01 -#define regGL2C_CTRL2_BASE_IDX 1 -#define regGL2C_ADDR_MATCH_MASK 0x2e03 -#define regGL2C_ADDR_MATCH_MASK_BASE_IDX 1 -#define regGL2C_ADDR_MATCH_SIZE 0x2e04 -#define regGL2C_ADDR_MATCH_SIZE_BASE_IDX 1 -#define regGL2C_WBINVL2 0x2e05 -#define regGL2C_WBINVL2_BASE_IDX 1 -#define regGL2C_SOFT_RESET 0x2e06 -#define regGL2C_SOFT_RESET_BASE_IDX 1 -#define regGL2C_CM_CTRL0 0x2e07 -#define regGL2C_CM_CTRL0_BASE_IDX 1 -#define regGL2C_CM_CTRL1 0x2e08 -#define regGL2C_CM_CTRL1_BASE_IDX 1 -#define regGL2C_CM_STALL 0x2e09 -#define regGL2C_CM_STALL_BASE_IDX 1 -#define regGL2C_CTRL3 0x2e0c -#define regGL2C_CTRL3_BASE_IDX 1 -#define regGL2C_LB_CTR_CTRL 0x2e0d -#define regGL2C_LB_CTR_CTRL_BASE_IDX 1 -#define regGL2C_LB_DATA0 0x2e0e -#define regGL2C_LB_DATA0_BASE_IDX 1 -#define regGL2C_LB_DATA1 0x2e0f -#define regGL2C_LB_DATA1_BASE_IDX 1 -#define regGL2C_LB_DATA2 0x2e10 -#define regGL2C_LB_DATA2_BASE_IDX 1 -#define regGL2C_LB_DATA3 0x2e11 -#define regGL2C_LB_DATA3_BASE_IDX 1 -#define regGL2C_LB_CTR_SEL0 0x2e12 -#define regGL2C_LB_CTR_SEL0_BASE_IDX 1 -#define regGL2C_LB_CTR_SEL1 0x2e13 -#define regGL2C_LB_CTR_SEL1_BASE_IDX 1 -#define regGL2C_CTRL4 0x2e17 -#define regGL2C_CTRL4_BASE_IDX 1 -#define regGL2C_DISCARD_STALL_CTRL 0x2e18 -#define regGL2C_DISCARD_STALL_CTRL_BASE_IDX 1 -#define regGL2A_ADDR_MATCH_CTRL 0x2e20 -#define regGL2A_ADDR_MATCH_CTRL_BASE_IDX 1 -#define regGL2A_ADDR_MATCH_MASK 0x2e21 -#define regGL2A_ADDR_MATCH_MASK_BASE_IDX 1 -#define regGL2A_ADDR_MATCH_SIZE 0x2e22 -#define regGL2A_ADDR_MATCH_SIZE_BASE_IDX 1 -#define regGL2A_PRIORITY_CTRL 0x2e23 -#define regGL2A_PRIORITY_CTRL_BASE_IDX 1 -#define regGL2A_RESP_THROTTLE_CTRL 0x2e2a -#define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX 1 - - -// addressBlock: gc_gl1hdec -// base address: 0x33900 -#define regGL1H_ARB_CTRL 0x2e40 -#define regGL1H_ARB_CTRL_BASE_IDX 1 -#define regGL1H_GL1_CREDITS 0x2e41 -#define regGL1H_GL1_CREDITS_BASE_IDX 1 -#define regGL1H_BURST_MASK 0x2e42 -#define regGL1H_BURST_MASK_BASE_IDX 1 -#define regGL1H_BURST_CTRL 0x2e43 -#define regGL1H_BURST_CTRL_BASE_IDX 1 -#define regGL1H_ARB_STATUS 0x2e44 -#define regGL1H_ARB_STATUS_BASE_IDX 1 - - -// addressBlock: gc_perfddec -// base address: 0x34000 -#define regCPG_PERFCOUNTER1_LO 0x3000 -#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCPG_PERFCOUNTER1_HI 0x3001 -#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCPG_PERFCOUNTER0_LO 0x3002 -#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCPG_PERFCOUNTER0_HI 0x3003 -#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCPC_PERFCOUNTER1_LO 0x3004 -#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCPC_PERFCOUNTER1_HI 0x3005 -#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCPC_PERFCOUNTER0_LO 0x3006 -#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCPC_PERFCOUNTER0_HI 0x3007 -#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCPF_PERFCOUNTER1_LO 0x3008 -#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCPF_PERFCOUNTER1_HI 0x3009 -#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCPF_PERFCOUNTER0_LO 0x300a -#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCPF_PERFCOUNTER0_HI 0x300b -#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCPF_LATENCY_STATS_DATA 0x300c -#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 -#define regCPG_LATENCY_STATS_DATA 0x300d -#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 -#define regCPC_LATENCY_STATS_DATA 0x300e -#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 -#define regGRBM_PERFCOUNTER0_LO 0x3040 -#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGRBM_PERFCOUNTER0_HI 0x3041 -#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGRBM_PERFCOUNTER1_LO 0x3043 -#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGRBM_PERFCOUNTER1_HI 0x3044 -#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGRBM_SE0_PERFCOUNTER_LO 0x3045 -#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE0_PERFCOUNTER_HI 0x3046 -#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE1_PERFCOUNTER_LO 0x3047 -#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE1_PERFCOUNTER_HI 0x3048 -#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE2_PERFCOUNTER_LO 0x3049 -#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE2_PERFCOUNTER_HI 0x304a -#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE3_PERFCOUNTER_LO 0x304b -#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE3_PERFCOUNTER_HI 0x304c -#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE4_PERFCOUNTER_LO 0x304d -#define regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE4_PERFCOUNTER_HI 0x304e -#define regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE5_PERFCOUNTER_LO 0x304f -#define regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE5_PERFCOUNTER_HI 0x3050 -#define regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX 1 -#define regGRBM_SE6_PERFCOUNTER_LO 0x3051 -#define regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX 1 -#define regGRBM_SE6_PERFCOUNTER_HI 0x3052 -#define regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX 1 -#define regGE1_PERFCOUNTER0_LO 0x30a4 -#define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGE1_PERFCOUNTER0_HI 0x30a5 -#define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGE1_PERFCOUNTER1_LO 0x30a6 -#define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGE1_PERFCOUNTER1_HI 0x30a7 -#define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGE1_PERFCOUNTER2_LO 0x30a8 -#define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGE1_PERFCOUNTER2_HI 0x30a9 -#define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGE1_PERFCOUNTER3_LO 0x30aa -#define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGE1_PERFCOUNTER3_HI 0x30ab -#define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER0_LO 0x30ac -#define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER0_HI 0x30ad -#define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER1_LO 0x30ae -#define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER1_HI 0x30af -#define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 -#define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 -#define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 -#define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 -#define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER0_LO 0x30b4 -#define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER0_HI 0x30b5 -#define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER1_LO 0x30b6 -#define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER1_HI 0x30b7 -#define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER2_LO 0x30b8 -#define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER2_HI 0x30b9 -#define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER3_LO 0x30ba -#define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER3_HI 0x30bb -#define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER0_LO 0x3100 -#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER0_HI 0x3101 -#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER1_LO 0x3102 -#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER1_HI 0x3103 -#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER2_LO 0x3104 -#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER2_HI 0x3105 -#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER3_LO 0x3106 -#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER3_HI 0x3107 -#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER0_LO 0x3140 -#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER0_HI 0x3141 -#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER1_LO 0x3142 -#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER1_HI 0x3143 -#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER2_LO 0x3144 -#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER2_HI 0x3145 -#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER3_LO 0x3146 -#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER3_HI 0x3147 -#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER4_LO 0x3148 -#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER4_HI 0x3149 -#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER5_LO 0x314a -#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER5_HI 0x314b -#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER6_LO 0x314c -#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER6_HI 0x314d -#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER7_LO 0x314e -#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER7_HI 0x314f -#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER0_HI 0x3180 -#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER0_LO 0x3181 -#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSPI_PERFCOUNTER1_HI 0x3182 -#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER1_LO 0x3183 -#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSPI_PERFCOUNTER2_HI 0x3184 -#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER2_LO 0x3185 -#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 -#define regSPI_PERFCOUNTER3_HI 0x3186 -#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER3_LO 0x3187 -#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 -#define regSPI_PERFCOUNTER4_HI 0x3188 -#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER4_LO 0x3189 -#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 -#define regSPI_PERFCOUNTER5_HI 0x318a -#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 -#define regSPI_PERFCOUNTER5_LO 0x318b -#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 -#define regPC_PERFCOUNTER0_HI 0x318c -#define regPC_PERFCOUNTER0_HI_BASE_IDX 1 -#define regPC_PERFCOUNTER0_LO 0x318d -#define regPC_PERFCOUNTER0_LO_BASE_IDX 1 -#define regPC_PERFCOUNTER1_HI 0x318e -#define regPC_PERFCOUNTER1_HI_BASE_IDX 1 -#define regPC_PERFCOUNTER1_LO 0x318f -#define regPC_PERFCOUNTER1_LO_BASE_IDX 1 -#define regPC_PERFCOUNTER2_HI 0x3190 -#define regPC_PERFCOUNTER2_HI_BASE_IDX 1 -#define regPC_PERFCOUNTER2_LO 0x3191 -#define regPC_PERFCOUNTER2_LO_BASE_IDX 1 -#define regPC_PERFCOUNTER3_HI 0x3192 -#define regPC_PERFCOUNTER3_HI_BASE_IDX 1 -#define regPC_PERFCOUNTER3_LO 0x3193 -#define regPC_PERFCOUNTER3_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER0_LO 0x31c0 -#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER1_LO 0x31c2 -#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER2_LO 0x31c4 -#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER3_LO 0x31c6 -#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER4_LO 0x31c8 -#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER5_LO 0x31ca -#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER6_LO 0x31cc -#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 -#define regSQ_PERFCOUNTER7_LO 0x31ce -#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER0_LO 0x31e4 -#define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER0_HI 0x31e5 -#define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER1_LO 0x31e6 -#define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER1_HI 0x31e7 -#define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER2_LO 0x31e8 -#define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER2_HI 0x31e9 -#define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER3_LO 0x31ea -#define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER3_HI 0x31eb -#define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER4_LO 0x31ec -#define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER4_HI 0x31ed -#define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER5_LO 0x31ee -#define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER5_HI 0x31ef -#define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER6_LO 0x31f0 -#define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER6_HI 0x31f1 -#define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 -#define regSQG_PERFCOUNTER7_LO 0x31f2 -#define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 -#define regSQG_PERFCOUNTER7_HI 0x31f3 -#define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 -#define regSX_PERFCOUNTER0_LO 0x3240 -#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 -#define regSX_PERFCOUNTER0_HI 0x3241 -#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 -#define regSX_PERFCOUNTER1_LO 0x3242 -#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 -#define regSX_PERFCOUNTER1_HI 0x3243 -#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 -#define regSX_PERFCOUNTER2_LO 0x3244 -#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 -#define regSX_PERFCOUNTER2_HI 0x3245 -#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 -#define regSX_PERFCOUNTER3_LO 0x3246 -#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 -#define regSX_PERFCOUNTER3_HI 0x3247 -#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGCEA_PERFCOUNTER2_LO 0x3260 -#define regGCEA_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGCEA_PERFCOUNTER2_HI 0x3261 -#define regGCEA_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGCEA_PERFCOUNTER_LO 0x3262 -#define regGCEA_PERFCOUNTER_LO_BASE_IDX 1 -#define regGCEA_PERFCOUNTER_HI 0x3263 -#define regGCEA_PERFCOUNTER_HI_BASE_IDX 1 -#define regGDS_PERFCOUNTER0_LO 0x3280 -#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGDS_PERFCOUNTER0_HI 0x3281 -#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGDS_PERFCOUNTER1_LO 0x3282 -#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGDS_PERFCOUNTER1_HI 0x3283 -#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGDS_PERFCOUNTER2_LO 0x3284 -#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGDS_PERFCOUNTER2_HI 0x3285 -#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGDS_PERFCOUNTER3_LO 0x3286 -#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGDS_PERFCOUNTER3_HI 0x3287 -#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 -#define regTA_PERFCOUNTER0_LO 0x32c0 -#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 -#define regTA_PERFCOUNTER0_HI 0x32c1 -#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 -#define regTA_PERFCOUNTER1_LO 0x32c2 -#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 -#define regTA_PERFCOUNTER1_HI 0x32c3 -#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 -#define regTD_PERFCOUNTER0_LO 0x3300 -#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 -#define regTD_PERFCOUNTER0_HI 0x3301 -#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 -#define regTD_PERFCOUNTER1_LO 0x3302 -#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 -#define regTD_PERFCOUNTER1_HI 0x3303 -#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 -#define regTCP_PERFCOUNTER0_LO 0x3340 -#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 -#define regTCP_PERFCOUNTER0_HI 0x3341 -#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 -#define regTCP_PERFCOUNTER1_LO 0x3342 -#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 -#define regTCP_PERFCOUNTER1_HI 0x3343 -#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 -#define regTCP_PERFCOUNTER2_LO 0x3344 -#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 -#define regTCP_PERFCOUNTER2_HI 0x3345 -#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 -#define regTCP_PERFCOUNTER3_LO 0x3346 -#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 -#define regTCP_PERFCOUNTER3_HI 0x3347 -#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 -#define regTCP_PERFCOUNTER_FILTER 0x3348 -#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 -#define regTCP_PERFCOUNTER_FILTER2 0x3349 -#define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 -#define regTCP_PERFCOUNTER_FILTER_EN 0x334a -#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 -#define regGL2C_PERFCOUNTER0_LO 0x3380 -#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGL2C_PERFCOUNTER0_HI 0x3381 -#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGL2C_PERFCOUNTER1_LO 0x3382 -#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGL2C_PERFCOUNTER1_HI 0x3383 -#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGL2C_PERFCOUNTER2_LO 0x3384 -#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGL2C_PERFCOUNTER2_HI 0x3385 -#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGL2C_PERFCOUNTER3_LO 0x3386 -#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGL2C_PERFCOUNTER3_HI 0x3387 -#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGL2A_PERFCOUNTER0_LO 0x3390 -#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGL2A_PERFCOUNTER0_HI 0x3391 -#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGL2A_PERFCOUNTER1_LO 0x3392 -#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGL2A_PERFCOUNTER1_HI 0x3393 -#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGL2A_PERFCOUNTER2_LO 0x3394 -#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGL2A_PERFCOUNTER2_HI 0x3395 -#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGL2A_PERFCOUNTER3_LO 0x3396 -#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGL2A_PERFCOUNTER3_HI 0x3397 -#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGL1C_PERFCOUNTER0_LO 0x33a0 -#define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGL1C_PERFCOUNTER0_HI 0x33a1 -#define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGL1C_PERFCOUNTER1_LO 0x33a2 -#define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGL1C_PERFCOUNTER1_HI 0x33a3 -#define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGL1C_PERFCOUNTER2_LO 0x33a4 -#define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGL1C_PERFCOUNTER2_HI 0x33a5 -#define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGL1C_PERFCOUNTER3_LO 0x33a6 -#define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGL1C_PERFCOUNTER3_HI 0x33a7 -#define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 -#define regCHC_PERFCOUNTER0_LO 0x33c0 -#define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCHC_PERFCOUNTER0_HI 0x33c1 -#define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCHC_PERFCOUNTER1_LO 0x33c2 -#define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCHC_PERFCOUNTER1_HI 0x33c3 -#define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCHC_PERFCOUNTER2_LO 0x33c4 -#define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 -#define regCHC_PERFCOUNTER2_HI 0x33c5 -#define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 -#define regCHC_PERFCOUNTER3_LO 0x33c6 -#define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 -#define regCHC_PERFCOUNTER3_HI 0x33c7 -#define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 -#define regCHCG_PERFCOUNTER0_LO 0x33c8 -#define regCHCG_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCHCG_PERFCOUNTER0_HI 0x33c9 -#define regCHCG_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCHCG_PERFCOUNTER1_LO 0x33ca -#define regCHCG_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCHCG_PERFCOUNTER1_HI 0x33cb -#define regCHCG_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCHCG_PERFCOUNTER2_LO 0x33cc -#define regCHCG_PERFCOUNTER2_LO_BASE_IDX 1 -#define regCHCG_PERFCOUNTER2_HI 0x33cd -#define regCHCG_PERFCOUNTER2_HI_BASE_IDX 1 -#define regCHCG_PERFCOUNTER3_LO 0x33ce -#define regCHCG_PERFCOUNTER3_LO_BASE_IDX 1 -#define regCHCG_PERFCOUNTER3_HI 0x33cf -#define regCHCG_PERFCOUNTER3_HI_BASE_IDX 1 -#define regCB_PERFCOUNTER0_LO 0x3406 -#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCB_PERFCOUNTER0_HI 0x3407 -#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCB_PERFCOUNTER1_LO 0x3408 -#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCB_PERFCOUNTER1_HI 0x3409 -#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCB_PERFCOUNTER2_LO 0x340a -#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 -#define regCB_PERFCOUNTER2_HI 0x340b -#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 -#define regCB_PERFCOUNTER3_LO 0x340c -#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 -#define regCB_PERFCOUNTER3_HI 0x340d -#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 -#define regDB_PERFCOUNTER0_LO 0x3440 -#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 -#define regDB_PERFCOUNTER0_HI 0x3441 -#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 -#define regDB_PERFCOUNTER1_LO 0x3442 -#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 -#define regDB_PERFCOUNTER1_HI 0x3443 -#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 -#define regDB_PERFCOUNTER2_LO 0x3444 -#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 -#define regDB_PERFCOUNTER2_HI 0x3445 -#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 -#define regDB_PERFCOUNTER3_LO 0x3446 -#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 -#define regDB_PERFCOUNTER3_HI 0x3447 -#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 -#define regRLC_PERFCOUNTER0_LO 0x3480 -#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 -#define regRLC_PERFCOUNTER0_HI 0x3481 -#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 -#define regRLC_PERFCOUNTER1_LO 0x3482 -#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 -#define regRLC_PERFCOUNTER1_HI 0x3483 -#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 -#define regRMI_PERFCOUNTER0_LO 0x34c0 -#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 -#define regRMI_PERFCOUNTER0_HI 0x34c1 -#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 -#define regRMI_PERFCOUNTER1_LO 0x34c2 -#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 -#define regRMI_PERFCOUNTER1_HI 0x34c3 -#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 -#define regRMI_PERFCOUNTER2_LO 0x34c4 -#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 -#define regRMI_PERFCOUNTER2_HI 0x34c5 -#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 -#define regRMI_PERFCOUNTER3_LO 0x34c6 -#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 -#define regRMI_PERFCOUNTER3_HI 0x34c7 -#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGCR_PERFCOUNTER0_LO 0x3520 -#define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGCR_PERFCOUNTER0_HI 0x3521 -#define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGCR_PERFCOUNTER1_LO 0x3522 -#define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGCR_PERFCOUNTER1_HI 0x3523 -#define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER0_LO 0x3580 -#define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER0_HI 0x3581 -#define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER1_LO 0x3582 -#define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER1_HI 0x3583 -#define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER2_LO 0x3584 -#define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER2_HI 0x3585 -#define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER3_LO 0x3586 -#define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER3_HI 0x3587 -#define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER4_LO 0x3588 -#define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER4_HI 0x3589 -#define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER5_LO 0x358a -#define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER5_HI 0x358b -#define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER6_LO 0x358c -#define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER6_HI 0x358d -#define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER7_LO 0x358e -#define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER7_HI 0x358f -#define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER0_LO 0x35a0 -#define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER0_HI 0x35a1 -#define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER1_LO 0x35a2 -#define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER1_HI 0x35a3 -#define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER2_LO 0x35a4 -#define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER2_HI 0x35a5 -#define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER3_LO 0x35a6 -#define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER3_HI 0x35a7 -#define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGL1A_PERFCOUNTER0_LO 0x35c0 -#define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGL1A_PERFCOUNTER0_HI 0x35c1 -#define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGL1A_PERFCOUNTER1_LO 0x35c2 -#define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGL1A_PERFCOUNTER1_HI 0x35c3 -#define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGL1A_PERFCOUNTER2_LO 0x35c4 -#define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGL1A_PERFCOUNTER2_HI 0x35c5 -#define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGL1A_PERFCOUNTER3_LO 0x35c6 -#define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGL1A_PERFCOUNTER3_HI 0x35c7 -#define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGL1H_PERFCOUNTER0_LO 0x35d0 -#define regGL1H_PERFCOUNTER0_LO_BASE_IDX 1 -#define regGL1H_PERFCOUNTER0_HI 0x35d1 -#define regGL1H_PERFCOUNTER0_HI_BASE_IDX 1 -#define regGL1H_PERFCOUNTER1_LO 0x35d2 -#define regGL1H_PERFCOUNTER1_LO_BASE_IDX 1 -#define regGL1H_PERFCOUNTER1_HI 0x35d3 -#define regGL1H_PERFCOUNTER1_HI_BASE_IDX 1 -#define regGL1H_PERFCOUNTER2_LO 0x35d4 -#define regGL1H_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGL1H_PERFCOUNTER2_HI 0x35d5 -#define regGL1H_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGL1H_PERFCOUNTER3_LO 0x35d6 -#define regGL1H_PERFCOUNTER3_LO_BASE_IDX 1 -#define regGL1H_PERFCOUNTER3_HI 0x35d7 -#define regGL1H_PERFCOUNTER3_HI_BASE_IDX 1 -#define regCHA_PERFCOUNTER0_LO 0x3600 -#define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 -#define regCHA_PERFCOUNTER0_HI 0x3601 -#define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 -#define regCHA_PERFCOUNTER1_LO 0x3602 -#define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 -#define regCHA_PERFCOUNTER1_HI 0x3603 -#define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 -#define regCHA_PERFCOUNTER2_LO 0x3604 -#define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 -#define regCHA_PERFCOUNTER2_HI 0x3605 -#define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 -#define regCHA_PERFCOUNTER3_LO 0x3606 -#define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 -#define regCHA_PERFCOUNTER3_HI 0x3607 -#define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 -#define regGUS_PERFCOUNTER2_LO 0x3640 -#define regGUS_PERFCOUNTER2_LO_BASE_IDX 1 -#define regGUS_PERFCOUNTER2_HI 0x3641 -#define regGUS_PERFCOUNTER2_HI_BASE_IDX 1 -#define regGUS_PERFCOUNTER_LO 0x3642 -#define regGUS_PERFCOUNTER_LO_BASE_IDX 1 -#define regGUS_PERFCOUNTER_HI 0x3643 -#define regGUS_PERFCOUNTER_HI_BASE_IDX 1 - - -// addressBlock: gc_perfsdec -// base address: 0x36000 -#define regCPG_PERFCOUNTER1_SELECT 0x3800 -#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCPG_PERFCOUNTER0_SELECT1 0x3801 -#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCPG_PERFCOUNTER0_SELECT 0x3802 -#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCPC_PERFCOUNTER1_SELECT 0x3803 -#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCPC_PERFCOUNTER0_SELECT1 0x3804 -#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCPF_PERFCOUNTER1_SELECT 0x3805 -#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCPF_PERFCOUNTER0_SELECT1 0x3806 -#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCPF_PERFCOUNTER0_SELECT 0x3807 -#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCP_PERFMON_CNTL 0x3808 -#define regCP_PERFMON_CNTL_BASE_IDX 1 -#define regCPC_PERFCOUNTER0_SELECT 0x3809 -#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a -#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 -#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b -#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 -#define regCPF_LATENCY_STATS_SELECT 0x380c -#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 -#define regCPG_LATENCY_STATS_SELECT 0x380d -#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 -#define regCPC_LATENCY_STATS_SELECT 0x380e -#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 -#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f -#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 -#define regCP_DRAW_OBJECT 0x3810 -#define regCP_DRAW_OBJECT_BASE_IDX 1 -#define regCP_DRAW_OBJECT_COUNTER 0x3811 -#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 -#define regCP_DRAW_WINDOW_MASK_HI 0x3812 -#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 -#define regCP_DRAW_WINDOW_HI 0x3813 -#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 -#define regCP_DRAW_WINDOW_LO 0x3814 -#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 -#define regCP_DRAW_WINDOW_CNTL 0x3815 -#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 -#define regGRBM_PERFCOUNTER0_SELECT 0x3840 -#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGRBM_PERFCOUNTER1_SELECT 0x3841 -#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 -#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 -#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 -#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 -#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE4_PERFCOUNTER_SELECT 0x3846 -#define regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE5_PERFCOUNTER_SELECT 0x3847 -#define regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_SE6_PERFCOUNTER_SELECT 0x3848 -#define regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX 1 -#define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d -#define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 -#define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e -#define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 -#define regGE1_PERFCOUNTER0_SELECT 0x38a4 -#define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGE1_PERFCOUNTER0_SELECT1 0x38a5 -#define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGE1_PERFCOUNTER1_SELECT 0x38a6 -#define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGE1_PERFCOUNTER1_SELECT1 0x38a7 -#define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGE1_PERFCOUNTER2_SELECT 0x38a8 -#define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGE1_PERFCOUNTER2_SELECT1 0x38a9 -#define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGE1_PERFCOUNTER3_SELECT 0x38aa -#define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGE1_PERFCOUNTER3_SELECT1 0x38ab -#define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac -#define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad -#define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae -#define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af -#define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 -#define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 -#define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 -#define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 -#define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 -#define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 -#define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 -#define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 -#define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 -#define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 -#define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba -#define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb -#define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 -#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 -#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 -#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 -#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 -#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 -#define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER3_SELECT 0x3906 -#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 -#define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 -#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 -#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 -#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 -#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 -#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 -#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 -#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 -#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 -#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER0_SELECT 0x3980 -#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER1_SELECT 0x3981 -#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER2_SELECT 0x3982 -#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER3_SELECT 0x3983 -#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER0_SELECT1 0x3984 -#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regSPI_PERFCOUNTER1_SELECT1 0x3985 -#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regSPI_PERFCOUNTER2_SELECT1 0x3986 -#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regSPI_PERFCOUNTER3_SELECT1 0x3987 -#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regSPI_PERFCOUNTER4_SELECT 0x3988 -#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER5_SELECT 0x3989 -#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define regSPI_PERFCOUNTER_BINS 0x398a -#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 -#define regPC_PERFCOUNTER0_SELECT 0x398c -#define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regPC_PERFCOUNTER1_SELECT 0x398d -#define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regPC_PERFCOUNTER2_SELECT 0x398e -#define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regPC_PERFCOUNTER3_SELECT 0x398f -#define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regPC_PERFCOUNTER0_SELECT1 0x3990 -#define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regPC_PERFCOUNTER1_SELECT1 0x3991 -#define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regPC_PERFCOUNTER2_SELECT1 0x3992 -#define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regPC_PERFCOUNTER3_SELECT1 0x3993 -#define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regSQ_PERFCOUNTER0_SELECT 0x39c0 -#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER1_SELECT 0x39c1 -#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER2_SELECT 0x39c2 -#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER3_SELECT 0x39c3 -#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER4_SELECT 0x39c4 -#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER5_SELECT 0x39c5 -#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER6_SELECT 0x39c6 -#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER7_SELECT 0x39c7 -#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER8_SELECT 0x39c8 -#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER9_SELECT 0x39c9 -#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER10_SELECT 0x39ca -#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER11_SELECT 0x39cb -#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER12_SELECT 0x39cc -#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER13_SELECT 0x39cd -#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER14_SELECT 0x39ce -#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 -#define regSQ_PERFCOUNTER15_SELECT 0x39cf -#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER0_SELECT 0x39d0 -#define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER1_SELECT 0x39d1 -#define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER2_SELECT 0x39d2 -#define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER3_SELECT 0x39d3 -#define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER4_SELECT 0x39d4 -#define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER5_SELECT 0x39d5 -#define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER6_SELECT 0x39d6 -#define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER7_SELECT 0x39d7 -#define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define regSQG_PERFCOUNTER_CTRL 0x39d8 -#define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 -#define regSQG_PERFCOUNTER_CTRL2 0x39da -#define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 -#define regSQG_PERF_SAMPLE_FINISH 0x39db -#define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 -#define regSQ_PERFCOUNTER_CTRL 0x39e0 -#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 -#define regSQ_PERFCOUNTER_CTRL2 0x39e2 -#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 -#define regSQ_THREAD_TRACE_BUF0_BASE 0x39e8 -#define regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 1 -#define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e9 -#define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 -#define regSQ_THREAD_TRACE_BUF1_BASE 0x39ea -#define regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 1 -#define regSQ_THREAD_TRACE_BUF1_SIZE 0x39eb -#define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 -#define regSQ_THREAD_TRACE_CTRL 0x39ec -#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 -#define regSQ_THREAD_TRACE_MASK 0x39ed -#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 -#define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee -#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 -#define regSQ_THREAD_TRACE_WPTR 0x39ef -#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 -#define regSQ_THREAD_TRACE_STATUS 0x39f4 -#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 -#define regSQ_THREAD_TRACE_STATUS2 0x39f5 -#define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 -#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 -#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 -#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 -#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 -#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 -#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 -#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 -#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 -#define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa -#define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 -#define regGCEA_PERFCOUNTER2_SELECT 0x3a00 -#define regGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGCEA_PERFCOUNTER2_SELECT1 0x3a01 -#define regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGCEA_PERFCOUNTER2_MODE 0x3a02 -#define regGCEA_PERFCOUNTER2_MODE_BASE_IDX 1 -#define regGCEA_PERFCOUNTER0_CFG 0x3a03 -#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regGCEA_PERFCOUNTER1_CFG 0x3a04 -#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x3a05 -#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 -#define regSX_PERFCOUNTER0_SELECT 0x3a40 -#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regSX_PERFCOUNTER1_SELECT 0x3a41 -#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regSX_PERFCOUNTER2_SELECT 0x3a42 -#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regSX_PERFCOUNTER3_SELECT 0x3a43 -#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regSX_PERFCOUNTER0_SELECT1 0x3a44 -#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regSX_PERFCOUNTER1_SELECT1 0x3a45 -#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGDS_PERFCOUNTER0_SELECT 0x3a80 -#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGDS_PERFCOUNTER1_SELECT 0x3a81 -#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGDS_PERFCOUNTER2_SELECT 0x3a82 -#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGDS_PERFCOUNTER3_SELECT 0x3a83 -#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGDS_PERFCOUNTER0_SELECT1 0x3a84 -#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGDS_PERFCOUNTER1_SELECT1 0x3a85 -#define regGDS_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGDS_PERFCOUNTER2_SELECT1 0x3a86 -#define regGDS_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGDS_PERFCOUNTER3_SELECT1 0x3a87 -#define regGDS_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regTA_PERFCOUNTER0_SELECT 0x3ac0 -#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 -#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regTA_PERFCOUNTER1_SELECT 0x3ac2 -#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regTD_PERFCOUNTER0_SELECT 0x3b00 -#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regTD_PERFCOUNTER0_SELECT1 0x3b01 -#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regTD_PERFCOUNTER1_SELECT 0x3b02 -#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regTCP_PERFCOUNTER0_SELECT 0x3b40 -#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 -#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regTCP_PERFCOUNTER1_SELECT 0x3b42 -#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 -#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regTCP_PERFCOUNTER2_SELECT 0x3b44 -#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regTCP_PERFCOUNTER3_SELECT 0x3b45 -#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGL2C_PERFCOUNTER0_SELECT 0x3b80 -#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGL2C_PERFCOUNTER0_SELECT1 0x3b81 -#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGL2C_PERFCOUNTER1_SELECT 0x3b82 -#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGL2C_PERFCOUNTER1_SELECT1 0x3b83 -#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGL2C_PERFCOUNTER2_SELECT 0x3b84 -#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGL2C_PERFCOUNTER3_SELECT 0x3b85 -#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGL2A_PERFCOUNTER0_SELECT 0x3b90 -#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGL2A_PERFCOUNTER0_SELECT1 0x3b91 -#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGL2A_PERFCOUNTER1_SELECT 0x3b92 -#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGL2A_PERFCOUNTER1_SELECT1 0x3b93 -#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regGL2A_PERFCOUNTER2_SELECT 0x3b94 -#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGL2A_PERFCOUNTER3_SELECT 0x3b95 -#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 -#define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 -#define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 -#define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGL1C_PERFCOUNTER2_SELECT 0x3ba3 -#define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGL1C_PERFCOUNTER3_SELECT 0x3ba4 -#define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regCHC_PERFCOUNTER0_SELECT 0x3bc0 -#define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 -#define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCHC_PERFCOUNTER1_SELECT 0x3bc2 -#define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCHC_PERFCOUNTER2_SELECT 0x3bc3 -#define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regCHC_PERFCOUNTER3_SELECT 0x3bc4 -#define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regCHCG_PERFCOUNTER0_SELECT 0x3bc6 -#define regCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCHCG_PERFCOUNTER0_SELECT1 0x3bc7 -#define regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCHCG_PERFCOUNTER1_SELECT 0x3bc8 -#define regCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCHCG_PERFCOUNTER2_SELECT 0x3bc9 -#define regCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regCHCG_PERFCOUNTER3_SELECT 0x3bca -#define regCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regCB_PERFCOUNTER_FILTER 0x3c00 -#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 -#define regCB_PERFCOUNTER0_SELECT 0x3c01 -#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCB_PERFCOUNTER0_SELECT1 0x3c02 -#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCB_PERFCOUNTER1_SELECT 0x3c03 -#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCB_PERFCOUNTER2_SELECT 0x3c04 -#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regCB_PERFCOUNTER3_SELECT 0x3c05 -#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regDB_PERFCOUNTER0_SELECT 0x3c40 -#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regDB_PERFCOUNTER0_SELECT1 0x3c41 -#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regDB_PERFCOUNTER1_SELECT 0x3c42 -#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regDB_PERFCOUNTER1_SELECT1 0x3c43 -#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regDB_PERFCOUNTER2_SELECT 0x3c44 -#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regDB_PERFCOUNTER3_SELECT 0x3c46 -#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regRLC_SPM_PERFMON_CNTL 0x3c80 -#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 -#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 -#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 -#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 -#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 -#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 -#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 -#define regRLC_SPM_RING_WRPTR 0x3c84 -#define regRLC_SPM_RING_WRPTR_BASE_IDX 1 -#define regRLC_SPM_RING_RDPTR 0x3c85 -#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 -#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 -#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 -#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 -#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 -#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 -#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 -#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 -#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 -#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a -#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 -#define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b -#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 -#define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 -#define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 -#define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 -#define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 -#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 -#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 -#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 -#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 -#define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 -#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 -#define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 -#define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 -#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 -#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 -#define regRLC_SPM_ACCUM_STATUS 0x3c99 -#define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 -#define regRLC_SPM_ACCUM_CTRL 0x3c9a -#define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 -#define regRLC_SPM_ACCUM_MODE 0x3c9b -#define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 -#define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c -#define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 -#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d -#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 -#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e -#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 -#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f -#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 -#define regRLC_SPM_PAUSE 0x3ca2 -#define regRLC_SPM_PAUSE_BASE_IDX 1 -#define regRLC_SPM_STATUS 0x3ca3 -#define regRLC_SPM_STATUS_BASE_IDX 1 -#define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 -#define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 -#define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 -#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 -#define regRLC_SPM_MODE 0x3cad -#define regRLC_SPM_MODE_BASE_IDX 1 -#define regRLC_SPM_RSPM_REQ_DATA_LO 0x3cae -#define regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX 1 -#define regRLC_SPM_RSPM_REQ_DATA_HI 0x3caf -#define regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX 1 -#define regRLC_SPM_RSPM_REQ_OP 0x3cb0 -#define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 -#define regRLC_SPM_RSPM_RET_DATA 0x3cb1 -#define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 -#define regRLC_SPM_RSPM_RET_OP 0x3cb2 -#define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 -#define regRLC_SPM_SE_RSPM_REQ_DATA_LO 0x3cb3 -#define regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX 1 -#define regRLC_SPM_SE_RSPM_REQ_DATA_HI 0x3cb4 -#define regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX 1 -#define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 -#define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 -#define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 -#define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 -#define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 -#define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 -#define regRLC_SPM_RSPM_CMD 0x3cb8 -#define regRLC_SPM_RSPM_CMD_BASE_IDX 1 -#define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 -#define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 -#define regRLC_SPM_SPARE 0x3cbf -#define regRLC_SPM_SPARE_BASE_IDX 1 -#define regRLC_PERFMON_CNTL 0x3cc0 -#define regRLC_PERFMON_CNTL_BASE_IDX 1 -#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 -#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 -#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 -#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 -#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 -#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 -#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 -#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 -#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 -#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 -#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 -#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 -#define regRMI_PERFCOUNTER0_SELECT 0x3d00 -#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 -#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regRMI_PERFCOUNTER1_SELECT 0x3d02 -#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regRMI_PERFCOUNTER2_SELECT 0x3d03 -#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 -#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regRMI_PERFCOUNTER3_SELECT 0x3d05 -#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regRMI_PERF_COUNTER_CNTL 0x3d06 -#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 -#define regGCR_PERFCOUNTER0_SELECT 0x3d60 -#define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGCR_PERFCOUNTER0_SELECT1 0x3d61 -#define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGCR_PERFCOUNTER1_SELECT 0x3d62 -#define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 -#define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 -#define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 -#define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 -#define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 -#define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 -#define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 -#define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 -#define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 -#define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 -#define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 -#define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 -#define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 -#define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER1_SELECT 0x3da1 -#define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER2_SELECT 0x3da2 -#define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regUTCL1_PERFCOUNTER3_SELECT 0x3da3 -#define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 -#define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 -#define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 -#define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGL1A_PERFCOUNTER2_SELECT 0x3dc3 -#define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGL1A_PERFCOUNTER3_SELECT 0x3dc4 -#define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGL1H_PERFCOUNTER0_SELECT 0x3dd0 -#define regGL1H_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regGL1H_PERFCOUNTER0_SELECT1 0x3dd1 -#define regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regGL1H_PERFCOUNTER1_SELECT 0x3dd2 -#define regGL1H_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regGL1H_PERFCOUNTER2_SELECT 0x3dd3 -#define regGL1H_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGL1H_PERFCOUNTER3_SELECT 0x3dd4 -#define regGL1H_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regCHA_PERFCOUNTER0_SELECT 0x3de0 -#define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 -#define regCHA_PERFCOUNTER0_SELECT1 0x3de1 -#define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 -#define regCHA_PERFCOUNTER1_SELECT 0x3de2 -#define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 -#define regCHA_PERFCOUNTER2_SELECT 0x3de3 -#define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regCHA_PERFCOUNTER3_SELECT 0x3de4 -#define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 -#define regGUS_PERFCOUNTER2_SELECT 0x3e00 -#define regGUS_PERFCOUNTER2_SELECT_BASE_IDX 1 -#define regGUS_PERFCOUNTER2_SELECT1 0x3e01 -#define regGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1 -#define regGUS_PERFCOUNTER2_MODE 0x3e02 -#define regGUS_PERFCOUNTER2_MODE_BASE_IDX 1 -#define regGUS_PERFCOUNTER0_CFG 0x3e03 -#define regGUS_PERFCOUNTER0_CFG_BASE_IDX 1 -#define regGUS_PERFCOUNTER1_CFG 0x3e04 -#define regGUS_PERFCOUNTER1_CFG_BASE_IDX 1 -#define regGUS_PERFCOUNTER_RSLT_CNTL 0x3e05 -#define regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 - - -// addressBlock: gc_grtavfs_grtavfs_dec -// base address: 0x3ac00 -#define regGRTAVFS_RTAVFS_REG_ADDR 0x4b00 -#define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 -#define regGRTAVFS_RTAVFS_WR_DATA 0x4b01 -#define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 -#define regGRTAVFS_GENERAL_0 0x4b02 -#define regGRTAVFS_GENERAL_0_BASE_IDX 1 -#define regGRTAVFS_RTAVFS_RD_DATA 0x4b03 -#define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX 1 -#define regGRTAVFS_RTAVFS_REG_CTRL 0x4b04 -#define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX 1 -#define regGRTAVFS_RTAVFS_REG_STATUS 0x4b05 -#define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX 1 -#define regGRTAVFS_TARG_FREQ 0x4b06 -#define regGRTAVFS_TARG_FREQ_BASE_IDX 1 -#define regGRTAVFS_TARG_VOLT 0x4b07 -#define regGRTAVFS_TARG_VOLT_BASE_IDX 1 -#define regGRTAVFS_SOFT_RESET 0x4b0c -#define regGRTAVFS_SOFT_RESET_BASE_IDX 1 -#define regGRTAVFS_PSM_CNTL 0x4b0d -#define regGRTAVFS_PSM_CNTL_BASE_IDX 1 -#define regGRTAVFS_CLK_CNTL 0x4b0e -#define regGRTAVFS_CLK_CNTL_BASE_IDX 1 - - -// addressBlock: gc_grtavfs_se_grtavfs_dec -// base address: 0x3ad00 -#define regGRTAVFS_SE_RTAVFS_REG_ADDR 0x4b40 -#define regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX 1 -#define regGRTAVFS_SE_RTAVFS_WR_DATA 0x4b41 -#define regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX 1 -#define regGRTAVFS_SE_GENERAL_0 0x4b42 -#define regGRTAVFS_SE_GENERAL_0_BASE_IDX 1 -#define regGRTAVFS_SE_RTAVFS_RD_DATA 0x4b43 -#define regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX 1 -#define regGRTAVFS_SE_RTAVFS_REG_CTRL 0x4b44 -#define regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX 1 -#define regGRTAVFS_SE_RTAVFS_REG_STATUS 0x4b45 -#define regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX 1 -#define regGRTAVFS_SE_TARG_FREQ 0x4b46 -#define regGRTAVFS_SE_TARG_FREQ_BASE_IDX 1 -#define regGRTAVFS_SE_TARG_VOLT 0x4b47 -#define regGRTAVFS_SE_TARG_VOLT_BASE_IDX 1 -#define regGRTAVFS_SE_SOFT_RESET 0x4b4c -#define regGRTAVFS_SE_SOFT_RESET_BASE_IDX 1 -#define regGRTAVFS_SE_PSM_CNTL 0x4b4d -#define regGRTAVFS_SE_PSM_CNTL_BASE_IDX 1 -#define regGRTAVFS_SE_CLK_CNTL 0x4b4e -#define regGRTAVFS_SE_CLK_CNTL_BASE_IDX 1 - - -// addressBlock: gc_grtavfsdec -// base address: 0x3ac00 -#define regRTAVFS_RTAVFS_REG_ADDR 0x4b00 -#define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 -#define regRTAVFS_RTAVFS_WR_DATA 0x4b01 -#define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 - - -// addressBlock: gc_cphypdec -// base address: 0x3e000 -#define regCP_HYP_PFP_UCODE_ADDR 0x5814 -#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 -#define regCP_PFP_UCODE_ADDR 0x5814 -#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 -#define regCP_HYP_PFP_UCODE_DATA 0x5815 -#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 -#define regCP_PFP_UCODE_DATA 0x5815 -#define regCP_PFP_UCODE_DATA_BASE_IDX 1 -#define regCP_HYP_ME_UCODE_ADDR 0x5816 -#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 -#define regCP_ME_RAM_RADDR 0x5816 -#define regCP_ME_RAM_RADDR_BASE_IDX 1 -#define regCP_ME_RAM_WADDR 0x5816 -#define regCP_ME_RAM_WADDR_BASE_IDX 1 -#define regCP_HYP_ME_UCODE_DATA 0x5817 -#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 -#define regCP_ME_RAM_DATA 0x5817 -#define regCP_ME_RAM_DATA_BASE_IDX 1 -#define regCP_HYP_MEC1_UCODE_ADDR 0x581a -#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 -#define regCP_MEC_ME1_UCODE_ADDR 0x581a -#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 -#define regCP_HYP_MEC1_UCODE_DATA 0x581b -#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 -#define regCP_MEC_ME1_UCODE_DATA 0x581b -#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 -#define regCP_HYP_MEC2_UCODE_ADDR 0x581c -#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 -#define regCP_MEC_ME2_UCODE_ADDR 0x581c -#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 -#define regCP_HYP_MEC2_UCODE_DATA 0x581d -#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 -#define regCP_MEC_ME2_UCODE_DATA 0x581d -#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 -#define regCP_PFP_IC_BASE_LO 0x5840 -#define regCP_PFP_IC_BASE_LO_BASE_IDX 1 -#define regCP_PFP_IC_BASE_HI 0x5841 -#define regCP_PFP_IC_BASE_HI_BASE_IDX 1 -#define regCP_PFP_IC_BASE_CNTL 0x5842 -#define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 -#define regCP_PFP_IC_OP_CNTL 0x5843 -#define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 -#define regCP_ME_IC_BASE_LO 0x5844 -#define regCP_ME_IC_BASE_LO_BASE_IDX 1 -#define regCP_ME_IC_BASE_HI 0x5845 -#define regCP_ME_IC_BASE_HI_BASE_IDX 1 -#define regCP_ME_IC_BASE_CNTL 0x5846 -#define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 -#define regCP_ME_IC_OP_CNTL 0x5847 -#define regCP_ME_IC_OP_CNTL_BASE_IDX 1 -#define regCP_CPC_IC_BASE_LO 0x584c -#define regCP_CPC_IC_BASE_LO_BASE_IDX 1 -#define regCP_CPC_IC_BASE_HI 0x584d -#define regCP_CPC_IC_BASE_HI_BASE_IDX 1 -#define regCP_CPC_IC_BASE_CNTL 0x584e -#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 -#define regCP_MES_IC_BASE_LO 0x5850 -#define regCP_MES_IC_BASE_LO_BASE_IDX 1 -#define regCP_MES_MIBASE_LO 0x5850 -#define regCP_MES_MIBASE_LO_BASE_IDX 1 -#define regCP_MES_IC_BASE_HI 0x5851 -#define regCP_MES_IC_BASE_HI_BASE_IDX 1 -#define regCP_MES_MIBASE_HI 0x5851 -#define regCP_MES_MIBASE_HI_BASE_IDX 1 -#define regCP_MES_IC_BASE_CNTL 0x5852 -#define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 -#define regCP_MES_DC_BASE_LO 0x5854 -#define regCP_MES_DC_BASE_LO_BASE_IDX 1 -#define regCP_MES_MDBASE_LO 0x5854 -#define regCP_MES_MDBASE_LO_BASE_IDX 1 -#define regCP_MES_DC_BASE_HI 0x5855 -#define regCP_MES_DC_BASE_HI_BASE_IDX 1 -#define regCP_MES_MDBASE_HI 0x5855 -#define regCP_MES_MDBASE_HI_BASE_IDX 1 -#define regCP_MES_MIBOUND_LO 0x585b -#define regCP_MES_MIBOUND_LO_BASE_IDX 1 -#define regCP_MES_MIBOUND_HI 0x585c -#define regCP_MES_MIBOUND_HI_BASE_IDX 1 -#define regCP_MES_MDBOUND_LO 0x585d -#define regCP_MES_MDBOUND_LO_BASE_IDX 1 -#define regCP_MES_MDBOUND_HI 0x585e -#define regCP_MES_MDBOUND_HI_BASE_IDX 1 -#define regCP_GFX_RS64_DC_BASE0_LO 0x5863 -#define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 -#define regCP_GFX_RS64_DC_BASE1_LO 0x5864 -#define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 -#define regCP_GFX_RS64_DC_BASE0_HI 0x5865 -#define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 -#define regCP_GFX_RS64_DC_BASE1_HI 0x5866 -#define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 -#define regCP_GFX_RS64_MIBOUND_LO 0x586c -#define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 -#define regCP_GFX_RS64_MIBOUND_HI 0x586d -#define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 -#define regCP_MEC_DC_BASE_LO 0x5870 -#define regCP_MEC_DC_BASE_LO_BASE_IDX 1 -#define regCP_MEC_MDBASE_LO 0x5870 -#define regCP_MEC_MDBASE_LO_BASE_IDX 1 -#define regCP_MEC_DC_BASE_HI 0x5871 -#define regCP_MEC_DC_BASE_HI_BASE_IDX 1 -#define regCP_MEC_MDBASE_HI 0x5871 -#define regCP_MEC_MDBASE_HI_BASE_IDX 1 -#define regCP_MEC_MIBOUND_LO 0x5872 -#define regCP_MEC_MIBOUND_LO_BASE_IDX 1 -#define regCP_MEC_MIBOUND_HI 0x5873 -#define regCP_MEC_MIBOUND_HI_BASE_IDX 1 -#define regCP_MEC_MDBOUND_LO 0x5874 -#define regCP_MEC_MDBOUND_LO_BASE_IDX 1 -#define regCP_MEC_MDBOUND_HI 0x5875 -#define regCP_MEC_MDBOUND_HI_BASE_IDX 1 - - -// addressBlock: gc_rlcdec -// base address: 0x3b000 -#define regRLC_CNTL 0x4c00 -#define regRLC_CNTL_BASE_IDX 1 -#define regRLC_F32_UCODE_VERSION 0x4c03 -#define regRLC_F32_UCODE_VERSION_BASE_IDX 1 -#define regRLC_STAT 0x4c04 -#define regRLC_STAT_BASE_IDX 1 -#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c -#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 -#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d -#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 -#define regRLC_GPM_TIMER_INT_0 0x4c0e -#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 -#define regRLC_GPM_TIMER_INT_1 0x4c0f -#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 -#define regRLC_GPM_TIMER_INT_2 0x4c10 -#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 -#define regRLC_GPM_TIMER_INT_3 0x4c11 -#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 -#define regRLC_GPM_TIMER_INT_4 0x4c12 -#define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 -#define regRLC_GPM_TIMER_CTRL 0x4c13 -#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 -#define regRLC_GPM_TIMER_STAT 0x4c14 -#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 -#define regRLC_GPM_LEGACY_INT_STAT 0x4c16 -#define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 -#define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 -#define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 -#define regRLC_INT_STAT 0x4c18 -#define regRLC_INT_STAT_BASE_IDX 1 -#define regRLC_MGCG_CTRL 0x4c1a -#define regRLC_MGCG_CTRL_BASE_IDX 1 -#define regRLC_JUMP_TABLE_RESTORE 0x4c1e -#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 -#define regRLC_PG_DELAY_2 0x4c1f -#define regRLC_PG_DELAY_2_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 -#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 -#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 -#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 -#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 -#define regRLC_UCODE_CNTL 0x4c27 -#define regRLC_UCODE_CNTL_BASE_IDX 1 -#define regRLC_GPM_THREAD_RESET 0x4c28 -#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 -#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 -#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 -#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a -#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 -#define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b -#define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 -#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 -#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 -#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 -#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 -#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 -#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 -#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 -#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 -#define regRLC_CLK_COUNT_CTRL 0x4c34 -#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 -#define regRLC_CLK_COUNT_STAT 0x4c35 -#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_CNTL 0x4c36 -#define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_STAT 0x4c37 -#define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 -#define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 -#define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a -#define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b -#define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c -#define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d -#define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e -#define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f -#define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 -#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 -#define regRLC_GPU_CLOCK_32 0x4c42 -#define regRLC_GPU_CLOCK_32_BASE_IDX 1 -#define regRLC_PG_CNTL 0x4c43 -#define regRLC_PG_CNTL_BASE_IDX 1 -#define regRLC_GPM_THREAD_PRIORITY 0x4c44 -#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 -#define regRLC_GPM_THREAD_ENABLE 0x4c45 -#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 -#define regRLC_RLCG_DOORBELL_RANGE 0x4c47 -#define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 -#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 -#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 -#define regRLC_CGCG_CGLS_CTRL 0x4c49 -#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 -#define regRLC_CGCG_RAMP_CTRL 0x4c4a -#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 -#define regRLC_DYN_PG_STATUS 0x4c4b -#define regRLC_DYN_PG_STATUS_BASE_IDX 1 -#define regRLC_DYN_PG_REQUEST 0x4c4c -#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 -#define regRLC_PG_DELAY 0x4c4d -#define regRLC_PG_DELAY_BASE_IDX 1 -#define regRLC_WGP_STATUS 0x4c4e -#define regRLC_WGP_STATUS_BASE_IDX 1 -#define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 -#define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 -#define regRLC_MAX_PG_WGP 0x4c54 -#define regRLC_MAX_PG_WGP_BASE_IDX 1 -#define regRLC_AUTO_PG_CTRL 0x4c55 -#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 -#define regRLC_SERDES_RD_INDEX 0x4c59 -#define regRLC_SERDES_RD_INDEX_BASE_IDX 1 -#define regRLC_SERDES_RD_DATA_0 0x4c5a -#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 -#define regRLC_SERDES_RD_DATA_1 0x4c5b -#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 -#define regRLC_SERDES_RD_DATA_2 0x4c5c -#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 -#define regRLC_SERDES_RD_DATA_3 0x4c5d -#define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 -#define regRLC_SERDES_MASK 0x4c5e -#define regRLC_SERDES_MASK_BASE_IDX 1 -#define regRLC_SERDES_CTRL 0x4c5f -#define regRLC_SERDES_CTRL_BASE_IDX 1 -#define regRLC_SERDES_DATA 0x4c60 -#define regRLC_SERDES_DATA_BASE_IDX 1 -#define regRLC_SERDES_BUSY 0x4c61 -#define regRLC_SERDES_BUSY_BASE_IDX 1 -#define regRLC_GPM_GENERAL_0 0x4c63 -#define regRLC_GPM_GENERAL_0_BASE_IDX 1 -#define regRLC_GPM_GENERAL_1 0x4c64 -#define regRLC_GPM_GENERAL_1_BASE_IDX 1 -#define regRLC_GPM_GENERAL_2 0x4c65 -#define regRLC_GPM_GENERAL_2_BASE_IDX 1 -#define regRLC_GPM_GENERAL_3 0x4c66 -#define regRLC_GPM_GENERAL_3_BASE_IDX 1 -#define regRLC_GPM_GENERAL_4 0x4c67 -#define regRLC_GPM_GENERAL_4_BASE_IDX 1 -#define regRLC_GPM_GENERAL_5 0x4c68 -#define regRLC_GPM_GENERAL_5_BASE_IDX 1 -#define regRLC_GPM_GENERAL_6 0x4c69 -#define regRLC_GPM_GENERAL_6_BASE_IDX 1 -#define regRLC_GPM_GENERAL_7 0x4c6a -#define regRLC_GPM_GENERAL_7_BASE_IDX 1 -#define regRLC_STATIC_PG_STATUS 0x4c6e -#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 -#define regRLC_GPM_GENERAL_16 0x4c76 -#define regRLC_GPM_GENERAL_16_BASE_IDX 1 -#define regRLC_PG_DELAY_3 0x4c78 -#define regRLC_PG_DELAY_3_BASE_IDX 1 -#define regRLC_GPR_REG1 0x4c79 -#define regRLC_GPR_REG1_BASE_IDX 1 -#define regRLC_GPR_REG2 0x4c7a -#define regRLC_GPR_REG2_BASE_IDX 1 -#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c -#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 -#define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d -#define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 -#define regRLC_GPM_INT_FORCE_TH0 0x4c7e -#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 -#define regRLC_SRM_CNTL 0x4c80 -#define regRLC_SRM_CNTL_BASE_IDX 1 -#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 -#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b -#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c -#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d -#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e -#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f -#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 -#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 -#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 -#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 -#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 -#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 -#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 -#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 -#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 -#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 -#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 -#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a -#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 -#define regRLC_SRM_STAT 0x4c9b -#define regRLC_SRM_STAT_BASE_IDX 1 -#define regRLC_GPM_GENERAL_8 0x4cad -#define regRLC_GPM_GENERAL_8_BASE_IDX 1 -#define regRLC_GPM_GENERAL_9 0x4cae -#define regRLC_GPM_GENERAL_9_BASE_IDX 1 -#define regRLC_GPM_GENERAL_10 0x4caf -#define regRLC_GPM_GENERAL_10_BASE_IDX 1 -#define regRLC_GPM_GENERAL_11 0x4cb0 -#define regRLC_GPM_GENERAL_11_BASE_IDX 1 -#define regRLC_GPM_GENERAL_12 0x4cb1 -#define regRLC_GPM_GENERAL_12_BASE_IDX 1 -#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 -#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 -#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 -#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 -#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 -#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 -#define regRLC_SPM_UTCL1_CNTL 0x4cb5 -#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 -#define regRLC_UTCL1_STATUS_2 0x4cb6 -#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 -#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc -#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 -#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd -#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe -#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 -#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 -#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 -#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 -#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 -#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 -#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 -#define regRLC_CGCG_CGLS_CTRL_3D 0x4cc5 -#define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 -#define regRLC_CGCG_RAMP_CTRL_3D 0x4cc6 -#define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 -#define regRLC_SEMAPHORE_0 0x4cc7 -#define regRLC_SEMAPHORE_0_BASE_IDX 1 -#define regRLC_SEMAPHORE_1 0x4cc8 -#define regRLC_SEMAPHORE_1_BASE_IDX 1 -#define regRLC_SEMAPHORE_2 0x4cc9 -#define regRLC_SEMAPHORE_2_BASE_IDX 1 -#define regRLC_SEMAPHORE_3 0x4cca -#define regRLC_SEMAPHORE_3_BASE_IDX 1 -#define regRLC_PACE_INT_STAT 0x4ccc -#define regRLC_PACE_INT_STAT_BASE_IDX 1 -#define regRLC_UTCL1_STATUS 0x4cd4 -#define regRLC_UTCL1_STATUS_BASE_IDX 1 -#define regRLC_R2I_CNTL_0 0x4cd5 -#define regRLC_R2I_CNTL_0_BASE_IDX 1 -#define regRLC_R2I_CNTL_1 0x4cd6 -#define regRLC_R2I_CNTL_1_BASE_IDX 1 -#define regRLC_R2I_CNTL_2 0x4cd7 -#define regRLC_R2I_CNTL_2_BASE_IDX 1 -#define regRLC_R2I_CNTL_3 0x4cd8 -#define regRLC_R2I_CNTL_3_BASE_IDX 1 -#define regRLC_GPM_INT_STAT_TH0 0x4cdc -#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 -#define regRLC_GPM_GENERAL_13 0x4cdd -#define regRLC_GPM_GENERAL_13_BASE_IDX 1 -#define regRLC_GPM_GENERAL_14 0x4cde -#define regRLC_GPM_GENERAL_14_BASE_IDX 1 -#define regRLC_GPM_GENERAL_15 0x4cdf -#define regRLC_GPM_GENERAL_15_BASE_IDX 1 -#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea -#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb -#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec -#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 -#define regRLC_PACE_INT_DISABLE 0x4ced -#define regRLC_PACE_INT_DISABLE_BASE_IDX 1 -#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef -#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 -#define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 -#define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_STAT 0x4cf2 -#define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 -#define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 -#define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 -#define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 -#define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 -#define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 -#define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 -#define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa -#define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb -#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc -#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 -#define regRLC_RLCV_SPARE_INT 0x4d00 -#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 -#define regRLC_PACE_TIMER_INT_0 0x4d04 -#define regRLC_PACE_TIMER_INT_0_BASE_IDX 1 -#define regRLC_PACE_TIMER_INT_1 0x4d05 -#define regRLC_PACE_TIMER_INT_1_BASE_IDX 1 -#define regRLC_PACE_TIMER_CTRL 0x4d06 -#define regRLC_PACE_TIMER_CTRL_BASE_IDX 1 -#define regRLC_SMU_CLK_REQ 0x4d08 -#define regRLC_SMU_CLK_REQ_BASE_IDX 1 -#define regRLC_CP_STAT_INVAL_STAT 0x4d09 -#define regRLC_CP_STAT_INVAL_STAT_BASE_IDX 1 -#define regRLC_CP_STAT_INVAL_CTRL 0x4d0a -#define regRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1 -#define regRLC_SPARE 0x4d0b -#define regRLC_SPARE_BASE_IDX 1 -#define regRLC_SPP_CTRL 0x4d0c -#define regRLC_SPP_CTRL_BASE_IDX 1 -#define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d -#define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 -#define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e -#define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 -#define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f -#define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 -#define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 -#define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 -#define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 -#define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 -#define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 -#define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 -#define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 -#define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 -#define regRLC_SPP_PROF_INFO_1 0x4d18 -#define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 -#define regRLC_SPP_PROF_INFO_2 0x4d19 -#define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 -#define regRLC_SPP_GLOBAL_SH_ID 0x4d1a -#define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 -#define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b -#define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 -#define regRLC_SPP_STATUS 0x4d1c -#define regRLC_SPP_STATUS_BASE_IDX 1 -#define regRLC_SPP_PVT_STAT_0 0x4d1d -#define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 -#define regRLC_SPP_PVT_STAT_1 0x4d1e -#define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 -#define regRLC_SPP_PVT_STAT_2 0x4d1f -#define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 -#define regRLC_SPP_PVT_STAT_3 0x4d20 -#define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 -#define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 -#define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 -#define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 -#define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 -#define regRLC_SPP_PBB_INFO 0x4d23 -#define regRLC_SPP_PBB_INFO_BASE_IDX 1 -#define regRLC_SPP_RESET 0x4d24 -#define regRLC_SPP_RESET_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_RANGE 0x4d26 -#define regRLC_RLCP_DOORBELL_RANGE_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_CNTL 0x4d27 -#define regRLC_RLCP_DOORBELL_CNTL_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_STAT 0x4d28 -#define regRLC_RLCP_DOORBELL_STAT_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_0_DATA_LO 0x4d29 -#define regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_0_DATA_HI 0x4d2a -#define regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_1_DATA_LO 0x4d2b -#define regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_1_DATA_HI 0x4d2c -#define regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_2_DATA_LO 0x4d2d -#define regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_2_DATA_HI 0x4d2e -#define regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_3_DATA_LO 0x4d2f -#define regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define regRLC_RLCP_DOORBELL_3_DATA_HI 0x4d30 -#define regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define regRLC_CAC_MASK_CNTL 0x4d45 -#define regRLC_CAC_MASK_CNTL_BASE_IDX 1 -#define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 -#define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 -#define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a -#define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b -#define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c -#define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d -#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 -#define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 -#define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 -#define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 -#define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 -#define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 -#define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 -#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 -#define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 -#define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 -#define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a -#define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b -#define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c -#define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d -#define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 -#define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e -#define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 -#define regRLC_GFX_IH_ARBITER_STAT 0x4d5f -#define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 -#define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 -#define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 -#define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 -#define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 -#define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 -#define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 -#define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 -#define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 -#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 -#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 -#define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 -#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 -#define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 -#define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 -#define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 -#define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 -#define regRLC_LX6_CNTL 0x4d80 -#define regRLC_LX6_CNTL_BASE_IDX 1 -#define regRLC_XT_CORE_STATUS 0x4dd4 -#define regRLC_XT_CORE_STATUS_BASE_IDX 1 -#define regRLC_XT_CORE_INTERRUPT 0x4dd5 -#define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 -#define regRLC_XT_CORE_FAULT_INFO 0x4dd6 -#define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 -#define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 -#define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 -#define regRLC_XT_CORE_RESERVED 0x4dd8 -#define regRLC_XT_CORE_RESERVED_BASE_IDX 1 -#define regRLC_XT_INT_VEC_FORCE 0x4dd9 -#define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 -#define regRLC_XT_INT_VEC_CLEAR 0x4dda -#define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 -#define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb -#define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 -#define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc -#define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 -#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 -#define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 -#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 -#define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 -#define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 -#define regRLC_SPP_CAM_ADDR 0x4de8 -#define regRLC_SPP_CAM_ADDR_BASE_IDX 1 -#define regRLC_SPP_CAM_DATA 0x4de9 -#define regRLC_SPP_CAM_DATA_BASE_IDX 1 -#define regRLC_SPP_CAM_EXT_ADDR 0x4dea -#define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 -#define regRLC_SPP_CAM_EXT_DATA 0x4deb -#define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 -#define regRLC_XT_DOORBELL_RANGE 0x4df5 -#define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 -#define regRLC_XT_DOORBELL_CNTL 0x4df6 -#define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 -#define regRLC_XT_DOORBELL_STAT 0x4df7 -#define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 -#define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 -#define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 -#define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 -#define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 -#define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa -#define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 -#define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb -#define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 -#define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc -#define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 -#define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd -#define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 -#define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe -#define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 -#define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff -#define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 -#define regRLC_MEM_SLP_CNTL 0x4e00 -#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 -#define regSMU_RLC_RESPONSE 0x4e01 -#define regSMU_RLC_RESPONSE_BASE_IDX 1 -#define regRLC_RLCV_SAFE_MODE 0x4e02 -#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 -#define regRLC_SMU_SAFE_MODE 0x4e03 -#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 -#define regRLC_RLCV_COMMAND 0x4e04 -#define regRLC_RLCV_COMMAND_BASE_IDX 1 -#define regRLC_SMU_MESSAGE 0x4e05 -#define regRLC_SMU_MESSAGE_BASE_IDX 1 -#define regRLC_SMU_MESSAGE_1 0x4e06 -#define regRLC_SMU_MESSAGE_1_BASE_IDX 1 -#define regRLC_SMU_MESSAGE_2 0x4e07 -#define regRLC_SMU_MESSAGE_2_BASE_IDX 1 -#define regRLC_SRM_GPM_COMMAND 0x4e08 -#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 -#define regRLC_SRM_GPM_ABORT 0x4e09 -#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 -#define regRLC_SMU_COMMAND 0x4e0a -#define regRLC_SMU_COMMAND_BASE_IDX 1 -#define regRLC_SMU_ARGUMENT_1 0x4e0b -#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 -#define regRLC_SMU_ARGUMENT_2 0x4e0c -#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 -#define regRLC_SMU_ARGUMENT_3 0x4e0d -#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 -#define regRLC_SMU_ARGUMENT_4 0x4e0e -#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 -#define regRLC_SMU_ARGUMENT_5 0x4e0f -#define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 -#define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 -#define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 -#define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 -#define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 -#define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 -#define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 -#define regRLC_IMU_MISC 0x4e16 -#define regRLC_IMU_MISC_BASE_IDX 1 -#define regRLC_IMU_RESET_VECTOR 0x4e17 -#define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 - - -// addressBlock: gc_rlcsdec -// base address: 0x3b980 -#define regRLC_RLCS_DEC_START 0x4e60 -#define regRLC_RLCS_DEC_START_BASE_IDX 1 -#define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 -#define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 -#define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 -#define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 -#define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 -#define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 -#define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 -#define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 -#define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 -#define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 -#define regRLC_RLCS_CGCG_REQUEST 0x4e66 -#define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 -#define regRLC_RLCS_CGCG_STATUS 0x4e67 -#define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 -#define regRLC_RLCS_SOC_DS_CNTL 0x4e68 -#define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 -#define regRLC_RLCS_GFX_DS_CNTL 0x4e69 -#define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 -#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6a -#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 -#define regRLC_GPM_STAT 0x4e6b -#define regRLC_GPM_STAT_BASE_IDX 1 -#define regRLC_RLCS_GPM_STAT 0x4e6b -#define regRLC_RLCS_GPM_STAT_BASE_IDX 1 -#define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6c -#define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 -#define regRLC_RLCS_DIDT_FORCE_STALL 0x4e6d -#define regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1 -#define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e -#define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 -#define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f -#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 -#define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 -#define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 -#define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 -#define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 -#define regRLC_RLCS_GPM_STAT_2 0x4e72 -#define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 -#define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 -#define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 -#define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 -#define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 -#define regRLC_RLCS_PG_CHANGE_READ 0x4e75 -#define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 -#define regRLC_RLCS_IH_SEMAPHORE 0x4e76 -#define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 -#define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 -#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 -#define regRLC_RLCS_WGP_STATUS 0x4e78 -#define regRLC_RLCS_WGP_STATUS_BASE_IDX 1 -#define regRLC_RLCS_WGP_READ 0x4e79 -#define regRLC_RLCS_WGP_READ_BASE_IDX 1 -#define regRLC_RLCS_CP_INT_CTRL_1 0x4e7a -#define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 -#define regRLC_RLCS_CP_INT_CTRL_2 0x4e7b -#define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 -#define regRLC_RLCS_CP_INT_INFO_1 0x4e7c -#define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 -#define regRLC_RLCS_CP_INT_INFO_2 0x4e7d -#define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 -#define regRLC_RLCS_SPM_INT_CTRL 0x4e7e -#define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 -#define regRLC_RLCS_SPM_INT_INFO_1 0x4e7f -#define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 -#define regRLC_RLCS_SPM_INT_INFO_2 0x4e80 -#define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 -#define regRLC_RLCS_DSM_TRIG 0x4e81 -#define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 -#define regRLC_RLCS_BOOTLOAD_STATUS 0x4e82 -#define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 -#define regRLC_RLCS_POWER_BRAKE_CNTL 0x4e83 -#define regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1 -#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4e84 -#define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1 -#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e85 -#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 -#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e86 -#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 -#define regRLC_RLCS_CMP_IDLE_CNTL 0x4e87 -#define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_0 0x4e88 -#define regRLC_RLCS_GENERAL_0_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_1 0x4e89 -#define regRLC_RLCS_GENERAL_1_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_2 0x4e8a -#define regRLC_RLCS_GENERAL_2_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_3 0x4e8b -#define regRLC_RLCS_GENERAL_3_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_4 0x4e8c -#define regRLC_RLCS_GENERAL_4_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_5 0x4e8d -#define regRLC_RLCS_GENERAL_5_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_6 0x4e8e -#define regRLC_RLCS_GENERAL_6_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_7 0x4e8f -#define regRLC_RLCS_GENERAL_7_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_8 0x4e90 -#define regRLC_RLCS_GENERAL_8_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_9 0x4e91 -#define regRLC_RLCS_GENERAL_9_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_10 0x4e92 -#define regRLC_RLCS_GENERAL_10_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_11 0x4e93 -#define regRLC_RLCS_GENERAL_11_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_12 0x4e94 -#define regRLC_RLCS_GENERAL_12_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_13 0x4e95 -#define regRLC_RLCS_GENERAL_13_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_14 0x4e96 -#define regRLC_RLCS_GENERAL_14_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_15 0x4e97 -#define regRLC_RLCS_GENERAL_15_BASE_IDX 1 -#define regRLC_RLCS_GENERAL_16 0x4e98 -#define regRLC_RLCS_GENERAL_16_BASE_IDX 1 -#define regRLC_RLCS_AUXILIARY_REG_1 0x4ec5 -#define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 -#define regRLC_RLCS_AUXILIARY_REG_2 0x4ec6 -#define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 -#define regRLC_RLCS_AUXILIARY_REG_3 0x4ec7 -#define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 -#define regRLC_RLCS_AUXILIARY_REG_4 0x4ec8 -#define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 -#define regRLC_RLCS_SPM_SQTT_MODE 0x4ec9 -#define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 -#define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4eca -#define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 -#define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ecb -#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 -#define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ecc -#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 -#define regRLC_RLCS_IMU_VIDCHG_CNTL 0x4ecd -#define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX 1 -#define regRLC_RLCS_EDC_INT_CNTL 0x4ece -#define regRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1 -#define regRLC_RLCS_KMD_LOG_CNTL1 0x4ecf -#define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 -#define regRLC_RLCS_KMD_LOG_CNTL2 0x4ed0 -#define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 -#define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ed1 -#define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 -#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ed2 -#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 -#define regRLC_RLCS_SRM_SRCID_CNTL 0x4ed3 -#define regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX 1 -#define regRLC_RLCS_GCR_DATA_0 0x4ed4 -#define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 -#define regRLC_RLCS_GCR_DATA_1 0x4ed5 -#define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 -#define regRLC_RLCS_GCR_DATA_2 0x4ed6 -#define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 -#define regRLC_RLCS_GCR_DATA_3 0x4ed7 -#define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 -#define regRLC_RLCS_GCR_STATUS 0x4ed8 -#define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 -#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 -#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 -#define regRLC_RLCS_UTCL2_CNTL 0x4eda -#define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb -#define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc -#define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd -#define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede -#define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf -#define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 -#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 -#define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 -#define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 -#define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 -#define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 -#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 -#define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 -#define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 0x4ee5 -#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 0x4ee6 -#define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee7 -#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 -#define regRLC_RLCS_IMU_RLC_STATUS 0x4ee8 -#define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 -#define regRLC_RLCS_RLC_IMU_STATUS 0x4ee9 -#define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_DATA_1 0x4eea -#define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4eeb -#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eec -#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_DATA_0 0x4eed -#define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eee -#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eef -#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 -#define regRLC_RLCS_IMU_RAM_CNTL 0x4ef0 -#define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 -#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4ef1 -#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 -#define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef3 -#define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 -#define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef4 -#define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 -#define regRLC_RLCS_SDMA_INT_STAT 0x4ef5 -#define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 -#define regRLC_RLCS_SDMA_INT_INFO 0x4ef6 -#define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 -#define regRLC_RLCS_PMM_CGCG_CNTL 0x4ef7 -#define regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX 1 -#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO 0x4ef8 -#define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX 1 -#define regRLC_RLCS_GFX_RM_CNTL 0x4efa -#define regRLC_RLCS_GFX_RM_CNTL_BASE_IDX 1 -#define regRLC_RLCS_DEC_END 0x4fff -#define regRLC_RLCS_DEC_END_BASE_IDX 1 - - -// addressBlock: gc_pfvfdec_rlc -// base address: 0x2a600 -#define regRLC_SAFE_MODE 0x0980 -#define regRLC_SAFE_MODE_BASE_IDX 1 -#define regRLC_SPM_SAMPLE_CNT 0x0981 -#define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 -#define regRLC_SPM_MC_CNTL 0x0982 -#define regRLC_SPM_MC_CNTL_BASE_IDX 1 -#define regRLC_SPM_INT_CNTL 0x0983 -#define regRLC_SPM_INT_CNTL_BASE_IDX 1 -#define regRLC_SPM_INT_STATUS 0x0984 -#define regRLC_SPM_INT_STATUS_BASE_IDX 1 -#define regRLC_SPM_INT_INFO_1 0x0985 -#define regRLC_SPM_INT_INFO_1_BASE_IDX 1 -#define regRLC_SPM_INT_INFO_2 0x0986 -#define regRLC_SPM_INT_INFO_2_BASE_IDX 1 -#define regRLC_CSIB_ADDR_LO 0x0987 -#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 -#define regRLC_CSIB_ADDR_HI 0x0988 -#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 -#define regRLC_CSIB_LENGTH 0x0989 -#define regRLC_CSIB_LENGTH_BASE_IDX 1 -#define regRLC_CP_SCHEDULERS 0x098a -#define regRLC_CP_SCHEDULERS_BASE_IDX 1 -#define regRLC_CP_EOF_INT 0x098b -#define regRLC_CP_EOF_INT_BASE_IDX 1 -#define regRLC_CP_EOF_INT_CNT 0x098c -#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 -#define regRLC_SPARE_INT_0 0x098d -#define regRLC_SPARE_INT_0_BASE_IDX 1 -#define regRLC_SPARE_INT_1 0x098e -#define regRLC_SPARE_INT_1_BASE_IDX 1 -#define regRLC_SPARE_INT_2 0x098f -#define regRLC_SPARE_INT_2_BASE_IDX 1 -#define regRLC_PACE_SPARE_INT 0x0990 -#define regRLC_PACE_SPARE_INT_BASE_IDX 1 -#define regRLC_PACE_SPARE_INT_1 0x0991 -#define regRLC_PACE_SPARE_INT_1_BASE_IDX 1 -#define regRLC_RLCV_SPARE_INT_1 0x0992 -#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 - - -// addressBlock: gc_pwrdec -// base address: 0x3c000 -#define regCGTS_TCC_DISABLE 0x5006 -#define regCGTS_TCC_DISABLE_BASE_IDX 1 -#define regCGTT_GS_NGG_CLK_CTRL 0x5087 -#define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 -#define regCGTT_PA_CLK_CTRL 0x5088 -#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 -#define regCGTT_SC_CLK_CTRL0 0x5089 -#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 -#define regCGTT_SC_CLK_CTRL1 0x508a -#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 -#define regCGTT_SC_CLK_CTRL2 0x508b -#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 -#define regCGTT_SQG_CLK_CTRL 0x508d -#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 -#define regSQ_ALU_CLK_CTRL 0x508e -#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 -#define regSQ_TEX_CLK_CTRL 0x508f -#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 -#define regSQ_LDS_CLK_CTRL 0x5090 -#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 -#define regICG_SP_CLK_CTRL 0x5093 -#define regICG_SP_CLK_CTRL_BASE_IDX 1 -#define regTA_CGTT_CTRL 0x509d -#define regTA_CGTT_CTRL_BASE_IDX 1 -#define regDB_CGTT_CLK_CTRL_0 0x50a4 -#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 -#define regCB_CGTT_SCLK_CTRL 0x50a8 -#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 -#define regCGTT_CP_CLK_CTRL 0x50b0 -#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 -#define regCGTT_CPF_CLK_CTRL 0x50b1 -#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 -#define regCGTT_CPC_CLK_CTRL 0x50b2 -#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 -#define regCGTT_RLC_CLK_CTRL 0x50b5 -#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 -#define regCGTT_SC_CLK_CTRL3 0x50bc -#define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 -#define regCGTT_SC_CLK_CTRL4 0x50bd -#define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 -#define regGCEA_ICG_CTRL 0x50c4 -#define regGCEA_ICG_CTRL_BASE_IDX 1 -#define regGL1I_GL1R_MGCG_OVERRIDE 0x50e4 -#define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 -#define regGL1H_ICG_CTRL 0x50e8 -#define regGL1H_ICG_CTRL_BASE_IDX 1 -#define regCHI_CHR_MGCG_OVERRIDE 0x50e9 -#define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 -#define regICG_GL1C_CLK_CTRL 0x50ec -#define regICG_GL1C_CLK_CTRL_BASE_IDX 1 -#define regICG_GL1A_CTRL 0x50f0 -#define regICG_GL1A_CTRL_BASE_IDX 1 -#define regICG_CHA_CTRL 0x50f1 -#define regICG_CHA_CTRL_BASE_IDX 1 -#define regGUS_ICG_CTRL 0x50f4 -#define regGUS_ICG_CTRL_BASE_IDX 1 -#define regCGTT_PH_CLK_CTRL0 0x50f8 -#define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 -#define regCGTT_PH_CLK_CTRL1 0x50f9 -#define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 -#define regCGTT_PH_CLK_CTRL2 0x50fa -#define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 -#define regCGTT_PH_CLK_CTRL3 0x50fb -#define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 -#define regGFX_ICG_GL2C_CTRL 0x50fc -#define regGFX_ICG_GL2C_CTRL_BASE_IDX 1 -#define regGFX_ICG_GL2C_CTRL1 0x50fd -#define regGFX_ICG_GL2C_CTRL1_BASE_IDX 1 -#define regICG_LDS_CLK_CTRL 0x5114 -#define regICG_LDS_CLK_CTRL_BASE_IDX 1 -#define regICG_CHC_CLK_CTRL 0x5140 -#define regICG_CHC_CLK_CTRL_BASE_IDX 1 -#define regICG_CHCG_CLK_CTRL 0x5144 -#define regICG_CHCG_CLK_CTRL_BASE_IDX 1 - - -// addressBlock: gc_hypdec -// base address: 0x3e000 -#define regGFX_PIPE_PRIORITY 0x587f -#define regGFX_PIPE_PRIORITY_BASE_IDX 1 -#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 -#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 -#define regGRBM_GFX_INDEX_SR_DATA 0x5a01 -#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 -#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 -#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 -#define regGRBM_GFX_CNTL_SR_DATA 0x5a03 -#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 -#define regGC_IH_COOKIE_0_PTR 0x5a07 -#define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 -#define regGRBM_SE_REMAP_CNTL 0x5a08 -#define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 -#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 -#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 -#define regRLC_GPU_IOV_CFG_REG6 0x5b06 -#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 -#define regRLC_SDMA0_STATUS 0x5b18 -#define regRLC_SDMA0_STATUS_BASE_IDX 1 -#define regRLC_SDMA1_STATUS 0x5b19 -#define regRLC_SDMA1_STATUS_BASE_IDX 1 -#define regRLC_SDMA2_STATUS 0x5b1a -#define regRLC_SDMA2_STATUS_BASE_IDX 1 -#define regRLC_SDMA3_STATUS 0x5b1b -#define regRLC_SDMA3_STATUS_BASE_IDX 1 -#define regRLC_SDMA0_BUSY_STATUS 0x5b1c -#define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 -#define regRLC_SDMA1_BUSY_STATUS 0x5b1d -#define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 -#define regRLC_SDMA2_BUSY_STATUS 0x5b1e -#define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 -#define regRLC_SDMA3_BUSY_STATUS 0x5b1f -#define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_CFG_REG8 0x5b20 -#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 -#define regRLC_RLCV_TIMER_INT_0 0x5b25 -#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 -#define regRLC_RLCV_TIMER_INT_1 0x5b26 -#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 -#define regRLC_RLCV_TIMER_CTRL 0x5b27 -#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 -#define regRLC_RLCV_TIMER_STAT 0x5b28 -#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c -#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 -#define regRLC_GPU_IOV_VF_MASK 0x5b2d -#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 -#define regRLC_HYP_SEMAPHORE_0 0x5b2e -#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 -#define regRLC_HYP_SEMAPHORE_1 0x5b2f -#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 -#define regRLC_BUSY_CLK_CNTL 0x5b30 -#define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 -#define regRLC_CLK_CNTL 0x5b31 -#define regRLC_CLK_CNTL_BASE_IDX 1 -#define regRLC_PACE_TIMER_STAT 0x5b33 -#define regRLC_PACE_TIMER_STAT_BASE_IDX 1 -#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 -#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 -#define regRLC_GPU_IOV_CFG_REG1 0x5b35 -#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 -#define regRLC_GPU_IOV_CFG_REG2 0x5b36 -#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 -#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 -#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SCH_0 0x5b38 -#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 -#define regRLC_GPU_IOV_SCH_3 0x5b3a -#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 -#define regRLC_GPU_IOV_SCH_1 0x5b3b -#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 -#define regRLC_GPU_IOV_SCH_2 0x5b3c -#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 -#define regRLC_PACE_INT_FORCE 0x5b3d -#define regRLC_PACE_INT_FORCE_BASE_IDX 1 -#define regRLC_PACE_INT_CLEAR 0x5b3e -#define regRLC_PACE_INT_CLEAR_BASE_IDX 1 -#define regRLC_GPU_IOV_INT_STAT 0x5b3f -#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 -#define regRLC_IH_COOKIE 0x5b41 -#define regRLC_IH_COOKIE_BASE_IDX 1 -#define regRLC_IH_COOKIE_CNTL 0x5b42 -#define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 -#define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 -#define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 -#define regRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44 -#define regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1 -#define regRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45 -#define regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1 -#define regRLC_GPU_IOV_F32_CNTL 0x5b46 -#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 -#define regRLC_GPU_IOV_F32_RESET 0x5b47 -#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 -#define regRLC_GPU_IOV_UCODE_ADDR 0x5b48 -#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 -#define regRLC_GPU_IOV_UCODE_DATA 0x5b49 -#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 -#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a -#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 -#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE 0x5b4b -#define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX 1 -#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d -#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 -#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e -#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 -#define regRLC_GPU_IOV_INT_FORCE 0x5b4f -#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 -#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b50 -#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 -#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b51 -#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 -#define regRLC_HYP_SEMAPHORE_2 0x5b52 -#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 -#define regRLC_HYP_SEMAPHORE_3 0x5b53 -#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 -#define regRLC_GPM_UCODE_ADDR 0x5b60 -#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 -#define regRLC_GPM_UCODE_DATA 0x5b61 -#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 -#define regRLC_GPM_IRAM_ADDR 0x5b62 -#define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 -#define regRLC_GPM_IRAM_DATA 0x5b63 -#define regRLC_GPM_IRAM_DATA_BASE_IDX 1 -#define regRLC_RLCP_IRAM_ADDR 0x5b64 -#define regRLC_RLCP_IRAM_ADDR_BASE_IDX 1 -#define regRLC_RLCP_IRAM_DATA 0x5b65 -#define regRLC_RLCP_IRAM_DATA_BASE_IDX 1 -#define regRLC_RLCV_IRAM_ADDR 0x5b66 -#define regRLC_RLCV_IRAM_ADDR_BASE_IDX 1 -#define regRLC_RLCV_IRAM_DATA 0x5b67 -#define regRLC_RLCV_IRAM_DATA_BASE_IDX 1 -#define regRLC_LX6_DRAM_ADDR 0x5b68 -#define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 -#define regRLC_LX6_DRAM_DATA 0x5b69 -#define regRLC_LX6_DRAM_DATA_BASE_IDX 1 -#define regRLC_LX6_IRAM_ADDR 0x5b6a -#define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 -#define regRLC_LX6_IRAM_DATA 0x5b6b -#define regRLC_LX6_IRAM_DATA_BASE_IDX 1 -#define regRLC_PACE_UCODE_ADDR 0x5b6c -#define regRLC_PACE_UCODE_ADDR_BASE_IDX 1 -#define regRLC_PACE_UCODE_DATA 0x5b6d -#define regRLC_PACE_UCODE_DATA_BASE_IDX 1 -#define regRLC_GPM_SCRATCH_ADDR 0x5b6e -#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 -#define regRLC_GPM_SCRATCH_DATA 0x5b6f -#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 -#define regRLC_SRM_DRAM_ADDR 0x5b71 -#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 -#define regRLC_SRM_DRAM_DATA 0x5b72 -#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 -#define regRLC_SRM_ARAM_ADDR 0x5b73 -#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 -#define regRLC_SRM_ARAM_DATA 0x5b74 -#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 -#define regRLC_PACE_SCRATCH_ADDR 0x5b77 -#define regRLC_PACE_SCRATCH_ADDR_BASE_IDX 1 -#define regRLC_PACE_SCRATCH_DATA 0x5b78 -#define regRLC_PACE_SCRATCH_DATA_BASE_IDX 1 -#define regRLC_GTS_OFFSET_LSB 0x5b79 -#define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 -#define regRLC_GTS_OFFSET_MSB 0x5b7a -#define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 -#define regGL2_PIPE_STEER_0 0x5b80 -#define regGL2_PIPE_STEER_0_BASE_IDX 1 -#define regGL2_PIPE_STEER_1 0x5b81 -#define regGL2_PIPE_STEER_1_BASE_IDX 1 -#define regGL2_PIPE_STEER_2 0x5b82 -#define regGL2_PIPE_STEER_2_BASE_IDX 1 -#define regGL2_PIPE_STEER_3 0x5b83 -#define regGL2_PIPE_STEER_3_BASE_IDX 1 -#define regGL1_PIPE_STEER 0x5b84 -#define regGL1_PIPE_STEER_BASE_IDX 1 -#define regCH_PIPE_STEER 0x5b88 -#define regCH_PIPE_STEER_BASE_IDX 1 -#define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 -#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 -#define regGC_USER_PRIM_CONFIG 0x5b91 -#define regGC_USER_PRIM_CONFIG_BASE_IDX 1 -#define regGC_USER_SA_UNIT_DISABLE 0x5b92 -#define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 -#define regGC_USER_RB_REDUNDANCY 0x5b93 -#define regGC_USER_RB_REDUNDANCY_BASE_IDX 1 -#define regGC_USER_RB_BACKEND_DISABLE 0x5b94 -#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 -#define regGC_USER_RMI_REDUNDANCY 0x5b95 -#define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 -#define regCGTS_USER_TCC_DISABLE 0x5b96 -#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 -#define regGC_USER_SHADER_RATE_CONFIG 0x5b97 -#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 -#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 -#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 -#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 -#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 -#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 -#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 -#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 -#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 -#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 -#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca -#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb -#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc -#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd -#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce -#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 -#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf -#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 - - -// addressBlock: gc_pspdec -// base address: 0x3f000 -#define regCP_MES_DM_INDEX_ADDR 0x5c00 -#define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 -#define regCP_MES_DM_INDEX_DATA 0x5c01 -#define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 -#define regCP_MEC_DM_INDEX_ADDR 0x5c02 -#define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 -#define regCP_MEC_DM_INDEX_DATA 0x5c03 -#define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 -#define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 -#define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 -#define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 -#define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 -#define regCPG_PSP_DEBUG 0x5c10 -#define regCPG_PSP_DEBUG_BASE_IDX 1 -#define regCPC_PSP_DEBUG 0x5c11 -#define regCPC_PSP_DEBUG_BASE_IDX 1 -#define regGRBM_SEC_CNTL 0x5e0d -#define regGRBM_SEC_CNTL_BASE_IDX 1 -#define regGRBM_CAM_INDEX 0x5e10 -#define regGRBM_CAM_INDEX_BASE_IDX 1 -#define regGRBM_HYP_CAM_INDEX 0x5e10 -#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 -#define regGRBM_CAM_DATA 0x5e11 -#define regGRBM_CAM_DATA_BASE_IDX 1 -#define regGRBM_HYP_CAM_DATA 0x5e11 -#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 -#define regGRBM_CAM_DATA_UPPER 0x5e12 -#define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 -#define regGRBM_HYP_CAM_DATA_UPPER 0x5e12 -#define regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1 -#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f26 -#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 - - -// addressBlock: gc_gfx_imu_gfx_imudec -// base address: 0x38000 -#define regGFX_IMU_C2PMSG_0 0x4000 -#define regGFX_IMU_C2PMSG_0_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_1 0x4001 -#define regGFX_IMU_C2PMSG_1_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_2 0x4002 -#define regGFX_IMU_C2PMSG_2_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_3 0x4003 -#define regGFX_IMU_C2PMSG_3_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_4 0x4004 -#define regGFX_IMU_C2PMSG_4_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_5 0x4005 -#define regGFX_IMU_C2PMSG_5_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_6 0x4006 -#define regGFX_IMU_C2PMSG_6_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_7 0x4007 -#define regGFX_IMU_C2PMSG_7_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_8 0x4008 -#define regGFX_IMU_C2PMSG_8_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_9 0x4009 -#define regGFX_IMU_C2PMSG_9_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_10 0x400a -#define regGFX_IMU_C2PMSG_10_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_11 0x400b -#define regGFX_IMU_C2PMSG_11_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_12 0x400c -#define regGFX_IMU_C2PMSG_12_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_13 0x400d -#define regGFX_IMU_C2PMSG_13_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_14 0x400e -#define regGFX_IMU_C2PMSG_14_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_15 0x400f -#define regGFX_IMU_C2PMSG_15_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_16 0x4010 -#define regGFX_IMU_C2PMSG_16_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_17 0x4011 -#define regGFX_IMU_C2PMSG_17_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_18 0x4012 -#define regGFX_IMU_C2PMSG_18_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_19 0x4013 -#define regGFX_IMU_C2PMSG_19_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_20 0x4014 -#define regGFX_IMU_C2PMSG_20_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_21 0x4015 -#define regGFX_IMU_C2PMSG_21_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_22 0x4016 -#define regGFX_IMU_C2PMSG_22_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_23 0x4017 -#define regGFX_IMU_C2PMSG_23_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_24 0x4018 -#define regGFX_IMU_C2PMSG_24_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_25 0x4019 -#define regGFX_IMU_C2PMSG_25_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_26 0x401a -#define regGFX_IMU_C2PMSG_26_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_27 0x401b -#define regGFX_IMU_C2PMSG_27_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_28 0x401c -#define regGFX_IMU_C2PMSG_28_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_29 0x401d -#define regGFX_IMU_C2PMSG_29_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_30 0x401e -#define regGFX_IMU_C2PMSG_30_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_31 0x401f -#define regGFX_IMU_C2PMSG_31_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_32 0x4020 -#define regGFX_IMU_C2PMSG_32_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_33 0x4021 -#define regGFX_IMU_C2PMSG_33_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_34 0x4022 -#define regGFX_IMU_C2PMSG_34_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_35 0x4023 -#define regGFX_IMU_C2PMSG_35_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_36 0x4024 -#define regGFX_IMU_C2PMSG_36_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_37 0x4025 -#define regGFX_IMU_C2PMSG_37_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_38 0x4026 -#define regGFX_IMU_C2PMSG_38_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_39 0x4027 -#define regGFX_IMU_C2PMSG_39_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_40 0x4028 -#define regGFX_IMU_C2PMSG_40_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_41 0x4029 -#define regGFX_IMU_C2PMSG_41_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_42 0x402a -#define regGFX_IMU_C2PMSG_42_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_43 0x402b -#define regGFX_IMU_C2PMSG_43_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_44 0x402c -#define regGFX_IMU_C2PMSG_44_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_45 0x402d -#define regGFX_IMU_C2PMSG_45_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_46 0x402e -#define regGFX_IMU_C2PMSG_46_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_47 0x402f -#define regGFX_IMU_C2PMSG_47_BASE_IDX 1 -#define regGFX_IMU_MSG_FLAGS 0x403f -#define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 -#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 -#define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 -#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 -#define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 -#define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 -#define regGFX_IMU_MP1_MUTEX 0x4043 -#define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 -#define regGFX_IMU_RLC_DATA_4 0x4046 -#define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 -#define regGFX_IMU_RLC_DATA_3 0x4047 -#define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 -#define regGFX_IMU_RLC_DATA_2 0x4048 -#define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 -#define regGFX_IMU_RLC_DATA_1 0x4049 -#define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 -#define regGFX_IMU_RLC_DATA_0 0x404a -#define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 -#define regGFX_IMU_RLC_CMD 0x404b -#define regGFX_IMU_RLC_CMD_BASE_IDX 1 -#define regGFX_IMU_RLC_MUTEX 0x404c -#define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 -#define regGFX_IMU_RLC_MSG_STATUS 0x404f -#define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 -#define regRLC_GFX_IMU_DATA_0 0x4052 -#define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 -#define regRLC_GFX_IMU_CMD 0x4053 -#define regRLC_GFX_IMU_CMD_BASE_IDX 1 -#define regGFX_IMU_RLC_STATUS 0x4054 -#define regGFX_IMU_RLC_STATUS_BASE_IDX 1 -#define regGFX_IMU_STATUS 0x4055 -#define regGFX_IMU_STATUS_BASE_IDX 1 -#define regGFX_IMU_SOC_DATA 0x4059 -#define regGFX_IMU_SOC_DATA_BASE_IDX 1 -#define regGFX_IMU_SOC_ADDR 0x405a -#define regGFX_IMU_SOC_ADDR_BASE_IDX 1 -#define regGFX_IMU_SOC_REQ 0x405b -#define regGFX_IMU_SOC_REQ_BASE_IDX 1 -#define regGFX_IMU_VF_CTRL 0x405c -#define regGFX_IMU_VF_CTRL_BASE_IDX 1 -#define regGFX_IMU_TELEMETRY 0x4060 -#define regGFX_IMU_TELEMETRY_BASE_IDX 1 -#define regGFX_IMU_TELEMETRY_DATA 0x4061 -#define regGFX_IMU_TELEMETRY_DATA_BASE_IDX 1 -#define regGFX_IMU_TELEMETRY_TEMPERATURE 0x4062 -#define regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_0 0x4068 -#define regGFX_IMU_SCRATCH_0_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_1 0x4069 -#define regGFX_IMU_SCRATCH_1_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_2 0x406a -#define regGFX_IMU_SCRATCH_2_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_3 0x406b -#define regGFX_IMU_SCRATCH_3_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_4 0x406c -#define regGFX_IMU_SCRATCH_4_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_5 0x406d -#define regGFX_IMU_SCRATCH_5_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_6 0x406e -#define regGFX_IMU_SCRATCH_6_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_7 0x406f -#define regGFX_IMU_SCRATCH_7_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_8 0x4070 -#define regGFX_IMU_SCRATCH_8_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_9 0x4071 -#define regGFX_IMU_SCRATCH_9_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_10 0x4072 -#define regGFX_IMU_SCRATCH_10_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_11 0x4073 -#define regGFX_IMU_SCRATCH_11_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_12 0x4074 -#define regGFX_IMU_SCRATCH_12_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_13 0x4075 -#define regGFX_IMU_SCRATCH_13_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_14 0x4076 -#define regGFX_IMU_SCRATCH_14_BASE_IDX 1 -#define regGFX_IMU_SCRATCH_15 0x4077 -#define regGFX_IMU_SCRATCH_15_BASE_IDX 1 -#define regGFX_IMU_FW_GTS_LO 0x4078 -#define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 -#define regGFX_IMU_FW_GTS_HI 0x4079 -#define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 -#define regGFX_IMU_GTS_OFFSET_LO 0x407a -#define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 -#define regGFX_IMU_GTS_OFFSET_HI 0x407b -#define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 -#define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c -#define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 -#define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d -#define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 -#define regGFX_IMU_CORE_INT_STATUS 0x407f -#define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_MASK 0x4080 -#define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_LVL 0x4081 -#define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_EDGE 0x4082 -#define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_0 0x4083 -#define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_1 0x4084 -#define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_2 0x4085 -#define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_3 0x4086 -#define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_4 0x4087 -#define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_5 0x4088 -#define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_6 0x4089 -#define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_PRI_7 0x408a -#define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 -#define regGFX_IMU_PIC_INT_STATUS 0x408b -#define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 -#define regGFX_IMU_PIC_INTR 0x408c -#define regGFX_IMU_PIC_INTR_BASE_IDX 1 -#define regGFX_IMU_PIC_INTR_ID 0x408d -#define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 -#define regGFX_IMU_IH_CTRL_1 0x4090 -#define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 -#define regGFX_IMU_IH_CTRL_2 0x4091 -#define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 -#define regGFX_IMU_IH_CTRL_3 0x4092 -#define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 -#define regGFX_IMU_IH_STATUS 0x4093 -#define regGFX_IMU_IH_STATUS_BASE_IDX 1 -#define regGFX_IMU_FUSESTRAP 0x4094 -#define regGFX_IMU_SMUIO_VIDCHG_CTRL 0x4098 -#define regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX 1 -#define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c -#define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 -#define regGFX_IMU_CLK_CTRL 0x409d -#define regGFX_IMU_CLK_CTRL_BASE_IDX 1 -#define regGFX_IMU_DOORBELL_CONTROL 0x409e -#define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 -#define regGFX_IMU_RLC_CG_CTRL 0x40a0 -#define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 -#define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 -#define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 -#define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 -#define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 -#define regGFX_IMU_RLC_OVERRIDE 0x40a3 -#define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 -#define regGFX_IMU_DPM_CONTROL 0x40a8 -#define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 -#define regGFX_IMU_DPM_ACC 0x40a9 -#define regGFX_IMU_DPM_ACC_BASE_IDX 1 -#define regGFX_IMU_DPM_REF_COUNTER 0x40aa -#define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 -#define regGFX_IMU_RLC_RAM_INDEX 0x40ac -#define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 -#define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad -#define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 -#define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae -#define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 -#define regGFX_IMU_RLC_RAM_DATA 0x40af -#define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 -#define regGFX_IMU_FENCE_CTRL 0x40b0 -#define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 -#define regGFX_IMU_FENCE_LOG_INIT 0x40b1 -#define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 -#define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 -#define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 -#define regGFX_IMU_PROGRAM_CTR 0x40b5 -#define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 -#define regGFX_IMU_CORE_CTRL 0x40b6 -#define regGFX_IMU_CORE_CTRL_BASE_IDX 1 -#define regGFX_IMU_CORE_STATUS 0x40b7 -#define regGFX_IMU_CORE_STATUS_BASE_IDX 1 -#define regGFX_IMU_PWROKRAW 0x40b8 -#define regGFX_IMU_PWROKRAW_BASE_IDX 1 -#define regGFX_IMU_PWROK 0x40b9 -#define regGFX_IMU_PWROK_BASE_IDX 1 -#define regGFX_IMU_GAP_PWROK 0x40ba -#define regGFX_IMU_GAP_PWROK_BASE_IDX 1 -#define regGFX_IMU_RESETn 0x40bb -#define regGFX_IMU_RESETn_BASE_IDX 1 -#define regGFX_IMU_GFX_RESET_CTRL 0x40bc -#define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 -#define regGFX_IMU_AEB_OVERRIDE 0x40bd -#define regGFX_IMU_AEB_OVERRIDE_BASE_IDX 1 -#define regGFX_IMU_VDCI_RESET_CTRL 0x40be -#define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 -#define regGFX_IMU_GFX_ISO_CTRL 0x40bf -#define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CTRL0 0x40c0 -#define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CTRL1 0x40c1 -#define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 -#define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 -#define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CMP0 0x40c4 -#define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CMP1 0x40c5 -#define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 -#define regGFX_IMU_TIMER0_CMP3 0x40c7 -#define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 -#define regGFX_IMU_TIMER0_VALUE 0x40c8 -#define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CTRL0 0x40c9 -#define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CTRL1 0x40ca -#define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb -#define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc -#define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CMP0 0x40cd -#define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CMP1 0x40ce -#define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 -#define regGFX_IMU_TIMER1_CMP3 0x40d0 -#define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 -#define regGFX_IMU_TIMER1_VALUE 0x40d1 -#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CTRL0 0x40d2 -#define regGFX_IMU_TIMER2_CTRL0_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CTRL1 0x40d3 -#define regGFX_IMU_TIMER2_CTRL1_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CMP_AUTOINC 0x40d4 -#define regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CMP_INTEN 0x40d5 -#define regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CMP0 0x40d6 -#define regGFX_IMU_TIMER2_CMP0_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CMP1 0x40d7 -#define regGFX_IMU_TIMER2_CMP1_BASE_IDX 1 -#define regGFX_IMU_TIMER2_CMP3 0x40d9 -#define regGFX_IMU_TIMER2_CMP3_BASE_IDX 1 -#define regGFX_IMU_TIMER2_VALUE 0x40da -#define regGFX_IMU_TIMER2_VALUE_BASE_IDX 1 -#define regGFX_IMU_FUSE_CTRL 0x40e0 -#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 -#define regGFX_IMU_D_RAM_ADDR 0x40fc -#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 -#define regGFX_IMU_D_RAM_DATA 0x40fd -#define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 -#define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff -#define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 - - -// addressBlock: gc_gfx_imu_gfx_imu_pspdec -// base address: 0x3fe00 -#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 -#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 -#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 -#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 -#define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 -#define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 -#define regGFX_IMU_I_RAM_ADDR 0x5f90 -#define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 -#define regGFX_IMU_I_RAM_DATA 0x5f91 -#define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 - - -// addressBlock: gccacind -// base address: 0x0 -#define ixGC_CAC_ID 0x0000 -#define ixGC_CAC_CNTL 0x0001 -#define ixGC_CAC_ACC_CP0 0x0010 -#define ixGC_CAC_ACC_CP1 0x0011 -#define ixGC_CAC_ACC_CP2 0x0012 -#define ixGC_CAC_ACC_EA0 0x0013 -#define ixGC_CAC_ACC_EA1 0x0014 -#define ixGC_CAC_ACC_EA2 0x0015 -#define ixGC_CAC_ACC_EA3 0x0016 -#define ixGC_CAC_ACC_EA4 0x0017 -#define ixGC_CAC_ACC_EA5 0x0018 -#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x0019 -#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x001a -#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x001b -#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x001c -#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x001d -#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x001e -#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x001f -#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0020 -#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0021 -#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0022 -#define ixGC_CAC_ACC_UTCL2_VML20 0x0023 -#define ixGC_CAC_ACC_UTCL2_VML21 0x0024 -#define ixGC_CAC_ACC_UTCL2_VML22 0x0025 -#define ixGC_CAC_ACC_UTCL2_VML23 0x0026 -#define ixGC_CAC_ACC_UTCL2_VML24 0x0027 -#define ixGC_CAC_ACC_UTCL2_WALKER0 0x0028 -#define ixGC_CAC_ACC_UTCL2_WALKER1 0x0029 -#define ixGC_CAC_ACC_UTCL2_WALKER2 0x002a -#define ixGC_CAC_ACC_UTCL2_WALKER3 0x002b -#define ixGC_CAC_ACC_UTCL2_WALKER4 0x002c -#define ixGC_CAC_ACC_GDS0 0x002d -#define ixGC_CAC_ACC_GDS1 0x002e -#define ixGC_CAC_ACC_GDS2 0x002f -#define ixGC_CAC_ACC_GDS3 0x0030 -#define ixGC_CAC_ACC_GDS4 0x0031 -#define ixGC_CAC_ACC_GE0 0x0032 -#define ixGC_CAC_ACC_GE1 0x0033 -#define ixGC_CAC_ACC_GE2 0x0034 -#define ixGC_CAC_ACC_GE3 0x0035 -#define ixGC_CAC_ACC_GE4 0x0036 -#define ixGC_CAC_ACC_GE5 0x0037 -#define ixGC_CAC_ACC_GE6 0x0038 -#define ixGC_CAC_ACC_GE7 0x0039 -#define ixGC_CAC_ACC_GE8 0x003a -#define ixGC_CAC_ACC_GE9 0x003b -#define ixGC_CAC_ACC_GE10 0x003c -#define ixGC_CAC_ACC_GE11 0x003d -#define ixGC_CAC_ACC_GE12 0x003e -#define ixGC_CAC_ACC_GE13 0x003f -#define ixGC_CAC_ACC_GE14 0x0040 -#define ixGC_CAC_ACC_GE15 0x0041 -#define ixGC_CAC_ACC_GE16 0x0042 -#define ixGC_CAC_ACC_GE17 0x0043 -#define ixGC_CAC_ACC_GE18 0x0044 -#define ixGC_CAC_ACC_GE19 0x0045 -#define ixGC_CAC_ACC_GE20 0x0046 -#define ixGC_CAC_ACC_PMM0 0x0047 -#define ixGC_CAC_ACC_GL2C0 0x0048 -#define ixGC_CAC_ACC_GL2C1 0x0049 -#define ixGC_CAC_ACC_GL2C2 0x004a -#define ixGC_CAC_ACC_GL2C3 0x004b -#define ixGC_CAC_ACC_GL2C4 0x004c -#define ixGC_CAC_ACC_PH0 0x004d -#define ixGC_CAC_ACC_PH1 0x004e -#define ixGC_CAC_ACC_PH2 0x004f -#define ixGC_CAC_ACC_PH3 0x0050 -#define ixGC_CAC_ACC_PH4 0x0051 -#define ixGC_CAC_ACC_PH5 0x0052 -#define ixGC_CAC_ACC_PH6 0x0053 -#define ixGC_CAC_ACC_PH7 0x0054 -#define ixGC_CAC_ACC_SDMA0 0x0055 -#define ixGC_CAC_ACC_SDMA1 0x0056 -#define ixGC_CAC_ACC_SDMA2 0x0057 -#define ixGC_CAC_ACC_SDMA3 0x0058 -#define ixGC_CAC_ACC_SDMA4 0x0059 -#define ixGC_CAC_ACC_SDMA5 0x005a -#define ixGC_CAC_ACC_SDMA6 0x005b -#define ixGC_CAC_ACC_SDMA7 0x005c -#define ixGC_CAC_ACC_SDMA8 0x005d -#define ixGC_CAC_ACC_SDMA9 0x005e -#define ixGC_CAC_ACC_SDMA10 0x005f -#define ixGC_CAC_ACC_SDMA11 0x0060 -#define ixGC_CAC_ACC_CHC0 0x0061 -#define ixGC_CAC_ACC_CHC1 0x0062 -#define ixGC_CAC_ACC_CHC2 0x0063 -#define ixGC_CAC_ACC_GUS0 0x0064 -#define ixGC_CAC_ACC_GUS1 0x0065 -#define ixGC_CAC_ACC_GUS2 0x0066 -#define ixGC_CAC_ACC_RLC0 0x0067 -#define ixRELEASE_TO_STALL_LUT_1_8 0x0100 -#define ixRELEASE_TO_STALL_LUT_9_16 0x0101 -#define ixRELEASE_TO_STALL_LUT_17_20 0x0102 -#define ixSTALL_TO_RELEASE_LUT_1_4 0x0103 -#define ixSTALL_TO_RELEASE_LUT_5_7 0x0104 -#define ixSTALL_TO_PWRBRK_LUT_1_4 0x0105 -#define ixSTALL_TO_PWRBRK_LUT_5_7 0x0106 -#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x0107 -#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x0108 -#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x0109 -#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x010a -#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x010b -#define ixFIXED_PATTERN_PERF_COUNTER_1 0x010c -#define ixFIXED_PATTERN_PERF_COUNTER_2 0x010d -#define ixFIXED_PATTERN_PERF_COUNTER_3 0x010e -#define ixFIXED_PATTERN_PERF_COUNTER_4 0x010f -#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0110 -#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0111 -#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0112 -#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0113 -#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0114 -#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0115 -#define ixHW_LUT_UPDATE_STATUS 0x0116 - - -// addressBlock: secacind -// base address: 0x0 -#define ixSE_CAC_ID 0x0000 -#define ixSE_CAC_CNTL 0x0001 - - -// addressBlock: grtavfsind -// base address: 0x0 -#define ixRTAVFS_REG0 0x0000 -#define ixRTAVFS_REG1 0x0001 -#define ixRTAVFS_REG2 0x0002 -#define ixRTAVFS_REG3 0x0003 -#define ixRTAVFS_REG4 0x0004 -#define ixRTAVFS_REG5 0x0005 -#define ixRTAVFS_REG6 0x0006 -#define ixRTAVFS_REG7 0x0007 -#define ixRTAVFS_REG8 0x0008 -#define ixRTAVFS_REG9 0x0009 -#define ixRTAVFS_REG10 0x000a -#define ixRTAVFS_REG11 0x000b -#define ixRTAVFS_REG12 0x000c -#define ixRTAVFS_REG13 0x000d -#define ixRTAVFS_REG14 0x000e -#define ixRTAVFS_REG15 0x000f -#define ixRTAVFS_REG16 0x0010 -#define ixRTAVFS_REG17 0x0011 -#define ixRTAVFS_REG18 0x0012 -#define ixRTAVFS_REG19 0x0013 -#define ixRTAVFS_REG20 0x0014 -#define ixRTAVFS_REG21 0x0015 -#define ixRTAVFS_REG22 0x0016 -#define ixRTAVFS_REG23 0x0017 -#define ixRTAVFS_REG24 0x0018 -#define ixRTAVFS_REG25 0x0019 -#define ixRTAVFS_REG26 0x001a -#define ixRTAVFS_REG27 0x001b -#define ixRTAVFS_REG28 0x001c -#define ixRTAVFS_REG29 0x001d -#define ixRTAVFS_REG30 0x001e -#define ixRTAVFS_REG31 0x001f -#define ixRTAVFS_REG32 0x0020 -#define ixRTAVFS_REG33 0x0021 -#define ixRTAVFS_REG34 0x0022 -#define ixRTAVFS_REG35 0x0023 -#define ixRTAVFS_REG36 0x0024 -#define ixRTAVFS_REG37 0x0025 -#define ixRTAVFS_REG38 0x0026 -#define ixRTAVFS_REG39 0x0027 -#define ixRTAVFS_REG40 0x0028 -#define ixRTAVFS_REG41 0x0029 -#define ixRTAVFS_REG42 0x002a -#define ixRTAVFS_REG43 0x002b -#define ixRTAVFS_REG44 0x002c -#define ixRTAVFS_REG45 0x002d -#define ixRTAVFS_REG46 0x002e -#define ixRTAVFS_REG47 0x002f -#define ixRTAVFS_REG48 0x0030 -#define ixRTAVFS_REG49 0x0031 -#define ixRTAVFS_REG50 0x0032 -#define ixRTAVFS_REG51 0x0033 -#define ixRTAVFS_REG52 0x0034 -#define ixRTAVFS_REG53 0x0035 -#define ixRTAVFS_REG54 0x0036 -#define ixRTAVFS_REG55 0x0037 -#define ixRTAVFS_REG56 0x0038 -#define ixRTAVFS_REG57 0x0039 -#define ixRTAVFS_REG58 0x003a -#define ixRTAVFS_REG59 0x003b -#define ixRTAVFS_REG60 0x003c -#define ixRTAVFS_REG61 0x003d -#define ixRTAVFS_REG62 0x003e -#define ixRTAVFS_REG63 0x003f -#define ixRTAVFS_REG64 0x0040 -#define ixRTAVFS_REG65 0x0041 -#define ixRTAVFS_REG66 0x0042 -#define ixRTAVFS_REG67 0x0043 -#define ixRTAVFS_REG68 0x0044 -#define ixRTAVFS_REG69 0x0045 -#define ixRTAVFS_REG70 0x0046 -#define ixRTAVFS_REG71 0x0047 -#define ixRTAVFS_REG72 0x0048 -#define ixRTAVFS_REG73 0x0049 -#define ixRTAVFS_REG74 0x004a -#define ixRTAVFS_REG75 0x004b -#define ixRTAVFS_REG76 0x004c -#define ixRTAVFS_REG77 0x004d -#define ixRTAVFS_REG78 0x004e -#define ixRTAVFS_REG79 0x004f -#define ixRTAVFS_REG80 0x0050 -#define ixRTAVFS_REG81 0x0051 -#define ixRTAVFS_REG82 0x0052 -#define ixRTAVFS_REG83 0x0053 -#define ixRTAVFS_REG84 0x0054 -#define ixRTAVFS_REG85 0x0055 -#define ixRTAVFS_REG86 0x0056 -#define ixRTAVFS_REG87 0x0057 -#define ixRTAVFS_REG88 0x0058 -#define ixRTAVFS_REG89 0x0059 -#define ixRTAVFS_REG90 0x005a -#define ixRTAVFS_REG91 0x005b -#define ixRTAVFS_REG92 0x005c -#define ixRTAVFS_REG93 0x005d -#define ixRTAVFS_REG94 0x005e -#define ixRTAVFS_REG95 0x005f -#define ixRTAVFS_REG96 0x0060 -#define ixRTAVFS_REG97 0x0061 -#define ixRTAVFS_REG98 0x0062 -#define ixRTAVFS_REG99 0x0063 -#define ixRTAVFS_REG100 0x0064 -#define ixRTAVFS_REG101 0x0065 -#define ixRTAVFS_REG102 0x0066 -#define ixRTAVFS_REG103 0x0067 -#define ixRTAVFS_REG104 0x0068 -#define ixRTAVFS_REG105 0x0069 -#define ixRTAVFS_REG106 0x006a -#define ixRTAVFS_REG107 0x006b -#define ixRTAVFS_REG108 0x006c -#define ixRTAVFS_REG109 0x006d -#define ixRTAVFS_REG110 0x006e -#define ixRTAVFS_REG111 0x006f -#define ixRTAVFS_REG112 0x0070 -#define ixRTAVFS_REG113 0x0071 -#define ixRTAVFS_REG114 0x0072 -#define ixRTAVFS_REG115 0x0073 -#define ixRTAVFS_REG116 0x0074 -#define ixRTAVFS_REG117 0x0075 -#define ixRTAVFS_REG118 0x0076 -#define ixRTAVFS_REG119 0x0077 -#define ixRTAVFS_REG120 0x0078 -#define ixRTAVFS_REG121 0x0079 -#define ixRTAVFS_REG122 0x007a -#define ixRTAVFS_REG123 0x007b -#define ixRTAVFS_REG124 0x007c -#define ixRTAVFS_REG125 0x007d -#define ixRTAVFS_REG126 0x007e -#define ixRTAVFS_REG127 0x007f -#define ixRTAVFS_REG128 0x0080 -#define ixRTAVFS_REG129 0x0081 -#define ixRTAVFS_REG130 0x0082 -#define ixRTAVFS_REG131 0x0083 -#define ixRTAVFS_REG132 0x0084 -#define ixRTAVFS_REG133 0x0085 -#define ixRTAVFS_REG134 0x0086 -#define ixRTAVFS_REG135 0x0087 -#define ixRTAVFS_REG136 0x0088 -#define ixRTAVFS_REG137 0x0089 -#define ixRTAVFS_REG138 0x008a -#define ixRTAVFS_REG139 0x008b -#define ixRTAVFS_REG140 0x008c -#define ixRTAVFS_REG141 0x008d -#define ixRTAVFS_REG142 0x008e -#define ixRTAVFS_REG143 0x008f -#define ixRTAVFS_REG144 0x0090 -#define ixRTAVFS_REG145 0x0091 -#define ixRTAVFS_REG146 0x0092 -#define ixRTAVFS_REG147 0x0093 -#define ixRTAVFS_REG148 0x0094 -#define ixRTAVFS_REG149 0x0095 -#define ixRTAVFS_REG150 0x0096 -#define ixRTAVFS_REG151 0x0097 -#define ixRTAVFS_REG152 0x0098 -#define ixRTAVFS_REG153 0x0099 -#define ixRTAVFS_REG154 0x009a -#define ixRTAVFS_REG155 0x009b -#define ixRTAVFS_REG156 0x009c -#define ixRTAVFS_REG157 0x009d -#define ixRTAVFS_REG158 0x009e -#define ixRTAVFS_REG159 0x009f -#define ixRTAVFS_REG160 0x00a0 -#define ixRTAVFS_REG161 0x00a1 -#define ixRTAVFS_REG162 0x00a2 -#define ixRTAVFS_REG163 0x00a3 -#define ixRTAVFS_REG164 0x00a4 -#define ixRTAVFS_REG165 0x00a5 -#define ixRTAVFS_REG166 0x00a6 -#define ixRTAVFS_REG167 0x00a7 -#define ixRTAVFS_REG168 0x00a8 -#define ixRTAVFS_REG169 0x00a9 -#define ixRTAVFS_REG170 0x00aa -#define ixRTAVFS_REG171 0x00ab -#define ixRTAVFS_REG172 0x00ac -#define ixRTAVFS_REG173 0x00ad -#define ixRTAVFS_REG174 0x00ae -#define ixRTAVFS_REG175 0x00af -#define ixRTAVFS_REG176 0x00b0 -#define ixRTAVFS_REG177 0x00b1 -#define ixRTAVFS_REG178 0x00b2 -#define ixRTAVFS_REG179 0x00b3 -#define ixRTAVFS_REG180 0x00b4 -#define ixRTAVFS_REG181 0x00b5 -#define ixRTAVFS_REG182 0x00b6 -#define ixRTAVFS_REG183 0x00b7 -#define ixRTAVFS_REG184 0x00b8 -#define ixRTAVFS_REG185 0x00b9 -#define ixRTAVFS_REG186 0x00ba -#define ixRTAVFS_REG187 0x00bb -#define ixRTAVFS_REG188 0x00bc -#define ixRTAVFS_REG189 0x00bd -#define ixRTAVFS_REG190 0x00be -#define ixRTAVFS_REG191 0x00bf -#define ixRTAVFS_REG192 0x00c0 -#define ixRTAVFS_REG193 0x00c1 -#define ixRTAVFS_REG194 0x00c2 - - -// addressBlock: sqind -// base address: 0x0 -#define ixSQ_DEBUG_STS_LOCAL 0x0008 -#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 -#define ixSQ_WAVE_ACTIVE 0x000a -#define ixSQ_WAVE_VALID_AND_IDLE 0x000b -#define ixSQ_WAVE_MODE 0x0101 -#define ixSQ_WAVE_STATUS 0x0102 -#define ixSQ_WAVE_TRAPSTS 0x0103 -#define ixSQ_WAVE_GPR_ALLOC 0x0105 -#define ixSQ_WAVE_LDS_ALLOC 0x0106 -#define ixSQ_WAVE_IB_STS 0x0107 -#define ixSQ_WAVE_PC_LO 0x0108 -#define ixSQ_WAVE_PC_HI 0x0109 -#define ixSQ_WAVE_IB_DBG1 0x010d -#define ixSQ_WAVE_FLUSH_IB 0x010e -#define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0114 -#define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0115 -#define ixSQ_WAVE_HW_ID1 0x0117 -#define ixSQ_WAVE_HW_ID2 0x0118 -#define ixSQ_WAVE_POPS_PACKER 0x0119 -#define ixSQ_WAVE_SCHED_MODE 0x011a -#define ixSQ_WAVE_IB_STS2 0x011c -#define ixSQ_WAVE_SHADER_CYCLES 0x011d -#define ixSQ_WAVE_TTMP0 0x026c -#define ixSQ_WAVE_TTMP1 0x026d -#define ixSQ_WAVE_TTMP3 0x026f -#define ixSQ_WAVE_TTMP4 0x0270 -#define ixSQ_WAVE_TTMP5 0x0271 -#define ixSQ_WAVE_TTMP6 0x0272 -#define ixSQ_WAVE_TTMP7 0x0273 -#define ixSQ_WAVE_TTMP8 0x0274 -#define ixSQ_WAVE_TTMP9 0x0275 -#define ixSQ_WAVE_TTMP10 0x0276 -#define ixSQ_WAVE_TTMP11 0x0277 -#define ixSQ_WAVE_TTMP12 0x0278 -#define ixSQ_WAVE_TTMP13 0x0279 -#define ixSQ_WAVE_TTMP14 0x027a -#define ixSQ_WAVE_TTMP15 0x027b -#define ixSQ_WAVE_M0 0x027d -#define ixSQ_WAVE_EXEC_LO 0x027e -#define ixSQ_WAVE_EXEC_HI 0x027f - - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/hip_ioctl.py b/tinygrad/extra/hip_gpu_driver/hip_ioctl.py deleted file mode 100644 index cd31694e..00000000 --- a/tinygrad/extra/hip_gpu_driver/hip_ioctl.py +++ /dev/null @@ -1,100 +0,0 @@ -# type: ignore -import ctypes, ctypes.util, struct, platform, pathlib, re, time, os -start = time.perf_counter() - -# *** ioctl lib *** -libc = ctypes.CDLL(ctypes.util.find_library("c")) -# platform.processor calls `uname -p` which can return `unknown` on some systems -processor = os.getenv("IOCTL_PROCESSOR") or platform.processor() -IOCTL_SYSCALL = {"aarch64": 0x1d, "x86_64":16}[processor] - -def get_struct(argp, stype): - return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents - -def format_struct(s): - sdats = [] - for field_name, field_type in s._fields_: - dat = getattr(s, field_name) - if isinstance(dat, int): sdats.append(f"{field_name}:0x{dat:X}") - else: sdats.append(f"{field_name}:{dat}") - return sdats - -def install_hook(c_function, python_function): - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - if processor == "aarch64": - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - elif processor == "x86_64": - # 0x0000000000000000: 49 B8 aa aa aa aa aa aa aa aa movabs r8,
- # 0x000000000000000a: 41 FF E0 jmp r8 - tramp = b"\x49\xB8" + struct.pack("Q", python_function_addr) + b"\x41\xFF\xE0" - else: - raise Exception(f"processor {processor} not supported") - - # get real ioctl address - ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - - # hook ioctl - ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7) - assert ret == 0 - libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp)) - -# *** ioctl lib end *** - -import tinygrad.runtime.autogen.kfd as kfd_ioctl -def ioctls_from_header(): - hdr = (pathlib.Path(__file__).parent / "kfd_ioctl.h").read_text().replace("\\\n", "") - pattern = r'#define\s+(AMDKFD_IOC_[A-Z0-9_]+)\s+AMDKFD_IOW?R?\((0x[0-9a-fA-F]+),\s+struct\s([A-Za-z0-9_]+)\)' - matches = re.findall(pattern, hdr, re.MULTILINE) - return {int(nr, 0x10):(name, getattr(kfd_ioctl, "struct_"+sname)) for name, nr, sname in matches} -nrs = ioctls_from_header() - -@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p) -def ioctl(fd, request, argp): - st = time.perf_counter() - ret = libc.syscall(IOCTL_SYSCALL, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp)) - et = time.perf_counter()-st - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - if nr in nrs and itype == 75: - # /dev/kfd - name, stype = nrs[nr] - s = get_struct(argp, stype) - print(f"{(st-start)*1000:7.2f} ms +{et*1000.:7.2f} ms : {ret:2d} = {name:40s}", ' '.join(format_struct(s))) - if name == "AMDKFD_IOC_SVM": - out = ctypes.cast(s.attrs, ctypes.POINTER(kfd_ioctl.struct_kfd_ioctl_svm_attribute)) - for i in range(s.nattr): print(f"{i}: {kfd_ioctl.kfd_ioctl_svm_attr_type__enumvalues[out[i].type]:40s}: {out[i].value:#x}") - else: - print(f"{(st-start)*1000:7.2f} ms +{et*1000.:7.2f} ms : ioctl", - f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", os.readlink(f"/proc/self/fd/{fd}") if fd >= 0 else "") - return ret - -install_hook(libc.ioctl, ioctl) - -# AMD_LOG_LEVEL=4 HSAKMT_DEBUG_LEVEL=7 -if __name__ == "__main__": - print("***** import tinygrad") - from tinygrad import Tensor, Device, TinyJit - print("***** access HIP") - dev = Device["HIP"] - print("***** create tensor a") - a = Tensor([1.,2.]*1024*1024, device="HIP").realize() - print("***** create tensor b") - b = Tensor([3.,4.]*1024*1024, device="HIP").realize() - @TinyJit - def add(a, b): return (a+b).realize() - for i in range(4): - print(f"***** add tensors {i}") - c = add(a, b) - #dev.synchronize() - c = add(b, a) - dev.synchronize() - print(f"***** copyout") - nc = c.numpy() - print(f"***** delete") - del add, a, b, c, dev - print(f"***** done") - os._exit(0) diff --git a/tinygrad/extra/hip_gpu_driver/kfd_ioctl.h b/tinygrad/extra/hip_gpu_driver/kfd_ioctl.h deleted file mode 100644 index af96af17..00000000 --- a/tinygrad/extra/hip_gpu_driver/kfd_ioctl.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef KFD_IOCTL_H_INCLUDED -#define KFD_IOCTL_H_INCLUDED - -#include -#include - -/* - * - 1.1 - initial version - * - 1.3 - Add SMI events support - * - 1.4 - Indicate new SRAM EDC bit in device properties - * - 1.5 - Add SVM API - * - 1.6 - Query clear flags in SVM get_attr API - */ -#define KFD_IOCTL_MAJOR_VERSION 1 -#define KFD_IOCTL_MINOR_VERSION 6 - -struct kfd_ioctl_get_version_args { - __u32 major_version; /* from KFD */ - __u32 minor_version; /* from KFD */ -}; - -/* For kfd_ioctl_create_queue_args.queue_type. */ -#define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 -#define KFD_IOC_QUEUE_TYPE_SDMA 0x1 -#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 -#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 - -#define KFD_MAX_QUEUE_PERCENTAGE 100 -#define KFD_MAX_QUEUE_PRIORITY 15 - -struct kfd_ioctl_create_queue_args { - __u64 ring_base_address; /* to KFD */ - __u64 write_pointer_address; /* from KFD */ - __u64 read_pointer_address; /* from KFD */ - __u64 doorbell_offset; /* from KFD */ - - __u32 ring_size; /* to KFD */ - __u32 gpu_id; /* to KFD */ - __u32 queue_type; /* to KFD */ - __u32 queue_percentage; /* to KFD */ - __u32 queue_priority; /* to KFD */ - __u32 queue_id; /* from KFD */ - - __u64 eop_buffer_address; /* to KFD */ - __u64 eop_buffer_size; /* to KFD */ - __u64 ctx_save_restore_address; /* to KFD */ - __u32 ctx_save_restore_size; /* to KFD */ - __u32 ctl_stack_size; /* to KFD */ -}; - -struct kfd_ioctl_destroy_queue_args { - __u32 queue_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_update_queue_args { - __u64 ring_base_address; /* to KFD */ - - __u32 queue_id; /* to KFD */ - __u32 ring_size; /* to KFD */ - __u32 queue_percentage; /* to KFD */ - __u32 queue_priority; /* to KFD */ -}; - -struct kfd_ioctl_set_cu_mask_args { - __u32 queue_id; /* to KFD */ - __u32 num_cu_mask; /* to KFD */ - __u64 cu_mask_ptr; /* to KFD */ -}; - -struct kfd_ioctl_get_queue_wave_state_args { - __u64 ctl_stack_address; /* to KFD */ - __u32 ctl_stack_used_size; /* from KFD */ - __u32 save_area_used_size; /* from KFD */ - __u32 queue_id; /* to KFD */ - __u32 pad; -}; - -/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ -#define KFD_IOC_CACHE_POLICY_COHERENT 0 -#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 - -struct kfd_ioctl_set_memory_policy_args { - __u64 alternate_aperture_base; /* to KFD */ - __u64 alternate_aperture_size; /* to KFD */ - - __u32 gpu_id; /* to KFD */ - __u32 default_policy; /* to KFD */ - __u32 alternate_policy; /* to KFD */ - __u32 pad; -}; - -/* - * All counters are monotonic. They are used for profiling of compute jobs. - * The profiling is done by userspace. - * - * In case of GPU reset, the counter should not be affected. - */ - -struct kfd_ioctl_get_clock_counters_args { - __u64 gpu_clock_counter; /* from KFD */ - __u64 cpu_clock_counter; /* from KFD */ - __u64 system_clock_counter; /* from KFD */ - __u64 system_clock_freq; /* from KFD */ - - __u32 gpu_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_process_device_apertures { - __u64 lds_base; /* from KFD */ - __u64 lds_limit; /* from KFD */ - __u64 scratch_base; /* from KFD */ - __u64 scratch_limit; /* from KFD */ - __u64 gpuvm_base; /* from KFD */ - __u64 gpuvm_limit; /* from KFD */ - __u32 gpu_id; /* from KFD */ - __u32 pad; -}; - -/* - * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use - * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an - * unlimited number of GPUs. - */ -#define NUM_OF_SUPPORTED_GPUS 7 -struct kfd_ioctl_get_process_apertures_args { - struct kfd_process_device_apertures - process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ - - /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ - __u32 num_of_nodes; - __u32 pad; -}; - -struct kfd_ioctl_get_process_apertures_new_args { - /* User allocated. Pointer to struct kfd_process_device_apertures - * filled in by Kernel - */ - __u64 kfd_process_device_apertures_ptr; - /* to KFD - indicates amount of memory present in - * kfd_process_device_apertures_ptr - * from KFD - Number of entries filled by KFD. - */ - __u32 num_of_nodes; - __u32 pad; -}; - -#define MAX_ALLOWED_NUM_POINTS 100 -#define MAX_ALLOWED_AW_BUFF_SIZE 4096 -#define MAX_ALLOWED_WAC_BUFF_SIZE 128 - -struct kfd_ioctl_dbg_register_args { - __u32 gpu_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_dbg_unregister_args { - __u32 gpu_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_dbg_address_watch_args { - __u64 content_ptr; /* a pointer to the actual content */ - __u32 gpu_id; /* to KFD */ - __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ -}; - -struct kfd_ioctl_dbg_wave_control_args { - __u64 content_ptr; /* a pointer to the actual content */ - __u32 gpu_id; /* to KFD */ - __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ -}; - -/* Matching HSA_EVENTTYPE */ -#define KFD_IOC_EVENT_SIGNAL 0 -#define KFD_IOC_EVENT_NODECHANGE 1 -#define KFD_IOC_EVENT_DEVICESTATECHANGE 2 -#define KFD_IOC_EVENT_HW_EXCEPTION 3 -#define KFD_IOC_EVENT_SYSTEM_EVENT 4 -#define KFD_IOC_EVENT_DEBUG_EVENT 5 -#define KFD_IOC_EVENT_PROFILE_EVENT 6 -#define KFD_IOC_EVENT_QUEUE_EVENT 7 -#define KFD_IOC_EVENT_MEMORY 8 - -#define KFD_IOC_WAIT_RESULT_COMPLETE 0 -#define KFD_IOC_WAIT_RESULT_TIMEOUT 1 -#define KFD_IOC_WAIT_RESULT_FAIL 2 - -#define KFD_SIGNAL_EVENT_LIMIT 4096 - -/* For kfd_event_data.hw_exception_data.reset_type. */ -#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 -#define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 - -/* For kfd_event_data.hw_exception_data.reset_cause. */ -#define KFD_HW_EXCEPTION_GPU_HANG 0 -#define KFD_HW_EXCEPTION_ECC 1 - -/* For kfd_hsa_memory_exception_data.ErrorType */ -#define KFD_MEM_ERR_NO_RAS 0 -#define KFD_MEM_ERR_SRAM_ECC 1 -#define KFD_MEM_ERR_POISON_CONSUMED 2 -#define KFD_MEM_ERR_GPU_HANG 3 - -struct kfd_ioctl_create_event_args { - __u64 event_page_offset; /* from KFD */ - __u32 event_trigger_data; /* from KFD - signal events only */ - __u32 event_type; /* to KFD */ - __u32 auto_reset; /* to KFD */ - __u32 node_id; /* to KFD - only valid for certain - event types */ - __u32 event_id; /* from KFD */ - __u32 event_slot_index; /* from KFD */ -}; - -struct kfd_ioctl_destroy_event_args { - __u32 event_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_set_event_args { - __u32 event_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_reset_event_args { - __u32 event_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_memory_exception_failure { - __u32 NotPresent; /* Page not present or supervisor privilege */ - __u32 ReadOnly; /* Write access to a read-only page */ - __u32 NoExecute; /* Execute access to a page marked NX */ - __u32 imprecise; /* Can't determine the exact fault address */ -}; - -/* memory exception data */ -struct kfd_hsa_memory_exception_data { - struct kfd_memory_exception_failure failure; - __u64 va; - __u32 gpu_id; - __u32 ErrorType; /* 0 = no RAS error, - * 1 = ECC_SRAM, - * 2 = Link_SYNFLOOD (poison), - * 3 = GPU hang (not attributable to a specific cause), - * other values reserved - */ -}; - -/* hw exception data */ -struct kfd_hsa_hw_exception_data { - __u32 reset_type; - __u32 reset_cause; - __u32 memory_lost; - __u32 gpu_id; -}; - -/* Event data */ -struct kfd_event_data { - union { - struct kfd_hsa_memory_exception_data memory_exception_data; - struct kfd_hsa_hw_exception_data hw_exception_data; - }; /* From KFD */ - __u64 kfd_event_data_ext; /* pointer to an extension structure - for future exception types */ - __u32 event_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_wait_events_args { - __u64 events_ptr; /* pointed to struct - kfd_event_data array, to KFD */ - __u32 num_events; /* to KFD */ - __u32 wait_for_all; /* to KFD */ - __u32 timeout; /* to KFD */ - __u32 wait_result; /* from KFD */ -}; - -struct kfd_ioctl_set_scratch_backing_va_args { - __u64 va_addr; /* to KFD */ - __u32 gpu_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_get_tile_config_args { - /* to KFD: pointer to tile array */ - __u64 tile_config_ptr; - /* to KFD: pointer to macro tile array */ - __u64 macro_tile_config_ptr; - /* to KFD: array size allocated by user mode - * from KFD: array size filled by kernel - */ - __u32 num_tile_configs; - /* to KFD: array size allocated by user mode - * from KFD: array size filled by kernel - */ - __u32 num_macro_tile_configs; - - __u32 gpu_id; /* to KFD */ - __u32 gb_addr_config; /* from KFD */ - __u32 num_banks; /* from KFD */ - __u32 num_ranks; /* from KFD */ - /* struct size can be extended later if needed - * without breaking ABI compatibility - */ -}; - -struct kfd_ioctl_set_trap_handler_args { - __u64 tba_addr; /* to KFD */ - __u64 tma_addr; /* to KFD */ - __u32 gpu_id; /* to KFD */ - __u32 pad; -}; - -struct kfd_ioctl_acquire_vm_args { - __u32 drm_fd; /* to KFD */ - __u32 gpu_id; /* to KFD */ -}; - -/* Allocation flags: memory types */ -#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) -#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) -#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) -#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) -#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) -/* Allocation flags: attributes/access options */ -#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) -#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) -#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) -#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) -#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) -#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) -#define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) - -/* Allocate memory for later SVM (shared virtual memory) mapping. - * - * @va_addr: virtual address of the memory to be allocated - * all later mappings on all GPUs will use this address - * @size: size in bytes - * @handle: buffer handle returned to user mode, used to refer to - * this allocation for mapping, unmapping and freeing - * @mmap_offset: for CPU-mapping the allocation by mmapping a render node - * for userptrs this is overloaded to specify the CPU address - * @gpu_id: device identifier - * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above - */ -struct kfd_ioctl_alloc_memory_of_gpu_args { - __u64 va_addr; /* to KFD */ - __u64 size; /* to KFD */ - __u64 handle; /* from KFD */ - __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ - __u32 gpu_id; /* to KFD */ - __u32 flags; -}; - -/* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu - * - * @handle: memory handle returned by alloc - */ -struct kfd_ioctl_free_memory_of_gpu_args { - __u64 handle; /* to KFD */ -}; - -/* Map memory to one or more GPUs - * - * @handle: memory handle returned by alloc - * @device_ids_array_ptr: array of gpu_ids (__u32 per device) - * @n_devices: number of devices in the array - * @n_success: number of devices mapped successfully - * - * @n_success returns information to the caller how many devices from - * the start of the array have mapped the buffer successfully. It can - * be passed into a subsequent retry call to skip those devices. For - * the first call the caller should initialize it to 0. - * - * If the ioctl completes with return code 0 (success), n_success == - * n_devices. - */ -struct kfd_ioctl_map_memory_to_gpu_args { - __u64 handle; /* to KFD */ - __u64 device_ids_array_ptr; /* to KFD */ - __u32 n_devices; /* to KFD */ - __u32 n_success; /* to/from KFD */ -}; - -/* Unmap memory from one or more GPUs - * - * same arguments as for mapping - */ -struct kfd_ioctl_unmap_memory_from_gpu_args { - __u64 handle; /* to KFD */ - __u64 device_ids_array_ptr; /* to KFD */ - __u32 n_devices; /* to KFD */ - __u32 n_success; /* to/from KFD */ -}; - -/* Allocate GWS for specific queue - * - * @queue_id: queue's id that GWS is allocated for - * @num_gws: how many GWS to allocate - * @first_gws: index of the first GWS allocated. - * only support contiguous GWS allocation - */ -struct kfd_ioctl_alloc_queue_gws_args { - __u32 queue_id; /* to KFD */ - __u32 num_gws; /* to KFD */ - __u32 first_gws; /* from KFD */ - __u32 pad; -}; - -struct kfd_ioctl_get_dmabuf_info_args { - __u64 size; /* from KFD */ - __u64 metadata_ptr; /* to KFD */ - __u32 metadata_size; /* to KFD (space allocated by user) - * from KFD (actual metadata size) - */ - __u32 gpu_id; /* from KFD */ - __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ - __u32 dmabuf_fd; /* to KFD */ -}; - -struct kfd_ioctl_import_dmabuf_args { - __u64 va_addr; /* to KFD */ - __u64 handle; /* from KFD */ - __u32 gpu_id; /* to KFD */ - __u32 dmabuf_fd; /* to KFD */ -}; - -/* - * KFD SMI(System Management Interface) events - */ -enum kfd_smi_event { - KFD_SMI_EVENT_NONE = 0, /* not used */ - KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ - KFD_SMI_EVENT_THERMAL_THROTTLE = 2, - KFD_SMI_EVENT_GPU_PRE_RESET = 3, - KFD_SMI_EVENT_GPU_POST_RESET = 4, -}; - -#define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) - -struct kfd_ioctl_smi_events_args { - __u32 gpuid; /* to KFD */ - __u32 anon_fd; /* from KFD */ -}; - -/* Register offset inside the remapped mmio page - */ -enum kfd_mmio_remap { - KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, - KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, -}; - -/* Guarantee host access to memory */ -#define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 -/* Fine grained coherency between all devices with access */ -#define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 -/* Use any GPU in same hive as preferred device */ -#define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 -/* GPUs only read, allows replication */ -#define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 -/* Allow execution on GPU */ -#define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 -/* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ -#define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 - -/** - * kfd_ioctl_svm_op - SVM ioctl operations - * - * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes - * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes - */ -enum kfd_ioctl_svm_op { - KFD_IOCTL_SVM_OP_SET_ATTR, - KFD_IOCTL_SVM_OP_GET_ATTR -}; - -/** kfd_ioctl_svm_location - Enum for preferred and prefetch locations - * - * GPU IDs are used to specify GPUs as preferred and prefetch locations. - * Below definitions are used for system memory or for leaving the preferred - * location unspecified. - */ -enum kfd_ioctl_svm_location { - KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, - KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff -}; - -/** - * kfd_ioctl_svm_attr_type - SVM attribute types - * - * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for - * system memory - * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for - * system memory. Setting this triggers an - * immediate prefetch (migration). - * @KFD_IOCTL_SVM_ATTR_ACCESS: - * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: - * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given - * by the attribute value - * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see - * KFD_IOCTL_SVM_FLAG_...) - * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear - * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity - * (log2 num pages) - */ -enum kfd_ioctl_svm_attr_type { - KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, - KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, - KFD_IOCTL_SVM_ATTR_ACCESS, - KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, - KFD_IOCTL_SVM_ATTR_NO_ACCESS, - KFD_IOCTL_SVM_ATTR_SET_FLAGS, - KFD_IOCTL_SVM_ATTR_CLR_FLAGS, - KFD_IOCTL_SVM_ATTR_GRANULARITY -}; - -/** - * kfd_ioctl_svm_attribute - Attributes as pairs of type and value - * - * The meaning of the @value depends on the attribute type. - * - * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) - * @value: attribute value - */ -struct kfd_ioctl_svm_attribute { - __u32 type; - __u32 value; -}; - -/** - * kfd_ioctl_svm_args - Arguments for SVM ioctl - * - * @op specifies the operation to perform (see enum - * @kfd_ioctl_svm_op). @start_addr and @size are common for all - * operations. - * - * A variable number of attributes can be given in @attrs. - * @nattr specifies the number of attributes. New attributes can be - * added in the future without breaking the ABI. If unknown attributes - * are given, the function returns -EINVAL. - * - * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address - * range. It may overlap existing virtual address ranges. If it does, - * the existing ranges will be split such that the attribute changes - * only apply to the specified address range. - * - * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes - * over all memory in the given range and returns the result as the - * attribute value. If different pages have different preferred or - * prefetch locations, 0xffffffff will be returned for - * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or - * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For - * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be - * aggregated by bitwise AND. That means, a flag will be set in the - * output, if that flag is set for all pages in the range. For - * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be - * aggregated by bitwise NOR. That means, a flag will be set in the - * output, if that flag is clear for all pages in the range. - * The minimum migration granularity throughout the range will be - * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. - * - * Querying of accessibility attributes works by initializing the - * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the - * GPUID being queried. Multiple attributes can be given to allow - * querying multiple GPUIDs. The ioctl function overwrites the - * attribute type to indicate the access for the specified GPU. - */ -struct kfd_ioctl_svm_args { - __u64 start_addr; - __u64 size; - __u32 op; - __u32 nattr; - /* Variable length array of attributes */ - struct kfd_ioctl_svm_attribute attrs[0]; -}; - -/** - * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode - * - * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process - * - * @xnack_enabled indicates whether recoverable page faults should be - * enabled for the current process. 0 means disabled, positive means - * enabled, negative means leave unchanged. If enabled, virtual address - * translations on GFXv9 and later AMD GPUs can return XNACK and retry - * the access until a valid PTE is available. This is used to implement - * device page faults. - * - * On output, @xnack_enabled returns the (new) current mode (0 or - * positive). Therefore, a negative input value can be used to query - * the current mode without changing it. - * - * The XNACK mode fundamentally changes the way SVM managed memory works - * in the driver, with subtle effects on application performance and - * functionality. - * - * Enabling XNACK mode requires shader programs to be compiled - * differently. Furthermore, not all GPUs support changing the mode - * per-process. Therefore changing the mode is only allowed while no - * user mode queues exist in the process. This ensure that no shader - * code is running that may be compiled for the wrong mode. And GPUs - * that cannot change to the requested mode will prevent the XNACK - * mode from occurring. All GPUs used by the process must be in the - * same XNACK mode. - * - * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. - * Therefore those GPUs are not considered for the XNACK mode switch. - * - * Return: 0 on success, -errno on failure - */ -struct kfd_ioctl_set_xnack_mode_args { - __s32 xnack_enabled; -}; - -#define AMDKFD_IOCTL_BASE 'K' -#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) -#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) -#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) -#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) - -#define AMDKFD_IOC_GET_VERSION \ - AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) - -#define AMDKFD_IOC_CREATE_QUEUE \ - AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) - -#define AMDKFD_IOC_DESTROY_QUEUE \ - AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) - -#define AMDKFD_IOC_SET_MEMORY_POLICY \ - AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) - -#define AMDKFD_IOC_GET_CLOCK_COUNTERS \ - AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) - -#define AMDKFD_IOC_GET_PROCESS_APERTURES \ - AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) - -#define AMDKFD_IOC_UPDATE_QUEUE \ - AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) - -#define AMDKFD_IOC_CREATE_EVENT \ - AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) - -#define AMDKFD_IOC_DESTROY_EVENT \ - AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) - -#define AMDKFD_IOC_SET_EVENT \ - AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) - -#define AMDKFD_IOC_RESET_EVENT \ - AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) - -#define AMDKFD_IOC_WAIT_EVENTS \ - AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) - -#define AMDKFD_IOC_DBG_REGISTER \ - AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) - -#define AMDKFD_IOC_DBG_UNREGISTER \ - AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) - -#define AMDKFD_IOC_DBG_ADDRESS_WATCH \ - AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) - -#define AMDKFD_IOC_DBG_WAVE_CONTROL \ - AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) - -#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ - AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) - -#define AMDKFD_IOC_GET_TILE_CONFIG \ - AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) - -#define AMDKFD_IOC_SET_TRAP_HANDLER \ - AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) - -#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ - AMDKFD_IOWR(0x14, \ - struct kfd_ioctl_get_process_apertures_new_args) - -#define AMDKFD_IOC_ACQUIRE_VM \ - AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) - -#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ - AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) - -#define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ - AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) - -#define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ - AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) - -#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ - AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) - -#define AMDKFD_IOC_SET_CU_MASK \ - AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) - -#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ - AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) - -#define AMDKFD_IOC_GET_DMABUF_INFO \ - AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) - -#define AMDKFD_IOC_IMPORT_DMABUF \ - AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) - -#define AMDKFD_IOC_ALLOC_QUEUE_GWS \ - AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) - -#define AMDKFD_IOC_SMI_EVENTS \ - AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) - -#define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) - -#define AMDKFD_IOC_SET_XNACK_MODE \ - AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) - -#define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x22 - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/kfd_pm4_headers_ai.h b/tinygrad/extra/hip_gpu_driver/kfd_pm4_headers_ai.h deleted file mode 100644 index f391bb23..00000000 --- a/tinygrad/extra/hip_gpu_driver/kfd_pm4_headers_ai.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * Copyright 2016-2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef F32_MES_PM4_PACKETS_H -#define F32_MES_PM4_PACKETS_H - -#define uint32_t unsigned int -#define int32_t int - -#ifndef PM4_MES_HEADER_DEFINED -#define PM4_MES_HEADER_DEFINED -union PM4_MES_TYPE_3_HEADER { - struct { - uint32_t reserved1 : 8; /* < reserved */ - uint32_t opcode : 8; /* < IT opcode */ - uint32_t count : 14;/* < number of DWORDs - 1 in the - * information body. - */ - uint32_t type : 2; /* < packet identifier. - * It should be 3 for type 3 packets - */ - }; - uint32_t u32All; -}; -#endif /* PM4_MES_HEADER_DEFINED */ - -#ifndef PM4_MEC_RELEASE_MEM_DEFINED -#define PM4_MEC_RELEASE_MEM_DEFINED - -enum mec_release_mem_event_index_enum { - event_index__mec_release_mem__end_of_pipe = 5, - event_index__mec_release_mem__shader_done = 6 -}; - -enum mec_release_mem_cache_policy_enum { - cache_policy__mec_release_mem__lru = 0, - cache_policy__mec_release_mem__stream = 1 -}; - -enum mec_release_mem_pq_exe_status_enum { - pq_exe_status__mec_release_mem__default = 0, - pq_exe_status__mec_release_mem__phase_update = 1 -}; - -enum mec_release_mem_dst_sel_enum { - dst_sel__mec_release_mem__memory_controller = 0, - dst_sel__mec_release_mem__tc_l2 = 1, - dst_sel__mec_release_mem__queue_write_pointer_register = 2, - dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -}; - -enum mec_release_mem_int_sel_enum { - int_sel__mec_release_mem__none = 0, - int_sel__mec_release_mem__send_interrupt_only = 1, - int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, - int_sel__mec_release_mem__send_data_after_write_confirm = 3, - int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, - int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, - int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -}; - -enum mec_release_mem_data_sel_enum { - data_sel__mec_release_mem__none = 0, - data_sel__mec_release_mem__send_32_bit_low = 1, - data_sel__mec_release_mem__send_64_bit_data = 2, - data_sel__mec_release_mem__send_gpu_clock_counter = 3, - data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, - data_sel__mec_release_mem__store_gds_data_to_memory = 5 -}; - -struct pm4_mec_release_mem { - union { - union PM4_MES_TYPE_3_HEADER header; /*header */ - unsigned int ordinal1; - }; - - union { - struct { - unsigned int event_type:6; - unsigned int reserved1:2; - enum mec_release_mem_event_index_enum event_index:4; - unsigned int tcl1_vol_action_ena:1; - unsigned int tc_vol_action_ena:1; - unsigned int reserved2:1; - unsigned int tc_wb_action_ena:1; - unsigned int tcl1_action_ena:1; - unsigned int tc_action_ena:1; - uint32_t reserved3:1; - uint32_t tc_nc_action_ena:1; - uint32_t tc_wc_action_ena:1; - uint32_t tc_md_action_ena:1; - uint32_t reserved4:3; - enum mec_release_mem_cache_policy_enum cache_policy:2; - uint32_t reserved5:2; - enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; - uint32_t reserved6:2; - } bitfields2; - unsigned int ordinal2; - }; - - union { - struct { - uint32_t reserved7:16; - enum mec_release_mem_dst_sel_enum dst_sel:2; - uint32_t reserved8:6; - enum mec_release_mem_int_sel_enum int_sel:3; - uint32_t reserved9:2; - enum mec_release_mem_data_sel_enum data_sel:3; - } bitfields3; - unsigned int ordinal3; - }; - - union { - struct { - uint32_t reserved10:2; - unsigned int address_lo_32b:30; - } bitfields4; - struct { - uint32_t reserved11:3; - uint32_t address_lo_64b:29; - } bitfields4b; - uint32_t reserved12; - unsigned int ordinal4; - }; - - union { - uint32_t address_hi; - uint32_t reserved13; - uint32_t ordinal5; - }; - - union { - uint32_t data_lo; - uint32_t cmp_data_lo; - struct { - uint32_t dw_offset:16; - uint32_t num_dwords:16; - } bitfields6c; - uint32_t reserved14; - uint32_t ordinal6; - }; - - union { - uint32_t data_hi; - uint32_t cmp_data_hi; - uint32_t reserved15; - uint32_t reserved16; - uint32_t ordinal7; - }; - - uint32_t int_ctxid; - -}; - -#endif - -#ifndef PM4_MEC_WRITE_DATA_DEFINED -#define PM4_MEC_WRITE_DATA_DEFINED - -enum WRITE_DATA_dst_sel_enum { - dst_sel___write_data__mem_mapped_register = 0, - dst_sel___write_data__tc_l2 = 2, - dst_sel___write_data__gds = 3, - dst_sel___write_data__memory = 5, - dst_sel___write_data__memory_mapped_adc_persistent_state = 6, -}; - -enum WRITE_DATA_addr_incr_enum { - addr_incr___write_data__increment_address = 0, - addr_incr___write_data__do_not_increment_address = 1 -}; - -enum WRITE_DATA_wr_confirm_enum { - wr_confirm___write_data__do_not_wait_for_write_confirmation = 0, - wr_confirm___write_data__wait_for_write_confirmation = 1 -}; - -enum WRITE_DATA_cache_policy_enum { - cache_policy___write_data__lru = 0, - cache_policy___write_data__stream = 1 -}; - - -struct pm4_mec_write_data_mmio { - union { - union PM4_MES_TYPE_3_HEADER header; /*header */ - unsigned int ordinal1; - }; - - union { - struct { - unsigned int reserved1:8; - unsigned int dst_sel:4; - unsigned int reserved2:4; - unsigned int addr_incr:1; - unsigned int reserved3:2; - unsigned int resume_vf:1; - unsigned int wr_confirm:1; - unsigned int reserved4:4; - unsigned int cache_policy:2; - unsigned int reserved5:5; - } bitfields2; - unsigned int ordinal2; - }; - - union { - struct { - unsigned int dst_mmreg_addr:18; - unsigned int reserved6:14; - } bitfields3; - unsigned int ordinal3; - }; - - uint32_t reserved7; - - uint32_t data; - -}; - -#endif - -enum { - CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 -}; -#endif - diff --git a/tinygrad/extra/hip_gpu_driver/navi10_sdma_pkt_open.h b/tinygrad/extra/hip_gpu_driver/navi10_sdma_pkt_open.h deleted file mode 100644 index c88284ff..00000000 --- a/tinygrad/extra/hip_gpu_driver/navi10_sdma_pkt_open.h +++ /dev/null @@ -1,4886 +0,0 @@ -/* - * Copyright (C) 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __NAVI10_SDMA_PKT_OPEN_H_ -#define __NAVI10_SDMA_PKT_OPEN_H_ - -#define SDMA_OP_NOP 0 -#define SDMA_OP_COPY 1 -#define SDMA_OP_WRITE 2 -#define SDMA_OP_INDIRECT 4 -#define SDMA_OP_FENCE 5 -#define SDMA_OP_TRAP 6 -#define SDMA_OP_SEM 7 -#define SDMA_OP_POLL_REGMEM 8 -#define SDMA_OP_COND_EXE 9 -#define SDMA_OP_ATOMIC 10 -#define SDMA_OP_CONST_FILL 11 -#define SDMA_OP_PTEPDE 12 -#define SDMA_OP_TIMESTAMP 13 -#define SDMA_OP_SRBM_WRITE 14 -#define SDMA_OP_PRE_EXE 15 -#define SDMA_OP_GPUVM_INV 16 -#define SDMA_OP_GCR_REQ 17 -#define SDMA_OP_DUMMY_TRAP 32 -#define SDMA_SUBOP_TIMESTAMP_SET 0 -#define SDMA_SUBOP_TIMESTAMP_GET 1 -#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 -#define SDMA_SUBOP_COPY_LINEAR 0 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 -#define SDMA_SUBOP_COPY_TILED 1 -#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 -#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 -#define SDMA_SUBOP_COPY_SOA 3 -#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 -#define SDMA_SUBOP_COPY_LINEAR_PHY 8 -#define SDMA_SUBOP_COPY_LINEAR_BC 16 -#define SDMA_SUBOP_COPY_TILED_BC 17 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 -#define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 -#define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 -#define SDMA_SUBOP_WRITE_LINEAR 0 -#define SDMA_SUBOP_WRITE_TILED 1 -#define SDMA_SUBOP_WRITE_TILED_BC 17 -#define SDMA_SUBOP_PTEPDE_GEN 0 -#define SDMA_SUBOP_PTEPDE_COPY 1 -#define SDMA_SUBOP_PTEPDE_RMW 2 -#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 -#define SDMA_SUBOP_DATA_FILL_MULTI 1 -#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 -#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 -#define SDMA_SUBOP_POLL_MEM_VERIFY 3 -#define SDMA_SUBOP_VM_INVALIDATION 4 -#define HEADER_AGENT_DISPATCH 4 -#define HEADER_BARRIER 5 -#define SDMA_OP_AQL_COPY 0 -#define SDMA_OP_AQL_BARRIER_OR 0 - -#define SDMA_GCR_RANGE_IS_PA (1 << 18) -#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) -#define SDMA_GCR_GL2_WB (1 << 15) -#define SDMA_GCR_GL2_INV (1 << 14) -#define SDMA_GCR_GL2_DISCARD (1 << 13) -#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) -#define SDMA_GCR_GL2_US (1 << 10) -#define SDMA_GCR_GL1_INV (1 << 9) -#define SDMA_GCR_GLV_INV (1 << 8) -#define SDMA_GCR_GLK_INV (1 << 7) -#define SDMA_GCR_GLK_WB (1 << 6) -#define SDMA_GCR_GLM_INV (1 << 5) -#define SDMA_GCR_GLM_WB (1 << 4) -#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) -#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) - -/*define for op field*/ -#define SDMA_PKT_HEADER_op_offset 0 -#define SDMA_PKT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_HEADER_op_shift 0 -#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_HEADER_sub_op_offset 0 -#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_HEADER_sub_op_shift 8 -#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) - -/* -** Definitions for SDMA_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) - -/*define for backwards field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 -#define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) - -/*define for dst_ha field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 22 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) - -/*define for src_ha field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 30 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) - -/*define for all field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_mtype field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) - -/*define for dst_l2_policy field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) - -/*define for src_mtype field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) - -/*define for src_l2_policy field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_mtype field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) - -/*define for dst_l2_policy field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) - -/*define for src_mtype field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) - -/*define for src_l2_policy field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) - -/*define for dst_log field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) - -/*define for dst1_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST1_ADDR_LO word*/ -/*define for dst1_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) - -/*define for DST1_ADDR_HI word*/ -/*define for dst1_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) - -/*define for DST2_ADDR_LO word*/ -/*define for dst2_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) - -/*define for DST2_ADDR_HI word*/ -/*define for dst2_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) - -/*define for elementsize field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) - -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) - -/*define for DW_5 word*/ -/*define for src_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_8 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) - -/*define for DW_9 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) - -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) - -/*define for DW_10 word*/ -/*define for dst_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) - -/*define for DW_11 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) - -/*define for DW_12 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) - -/*define for elementsize field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) - -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) - -/*define for DW_5 word*/ -/*define for src_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_8 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) - -/*define for DW_9 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) - -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) - -/*define for DW_10 word*/ -/*define for dst_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) - -/*define for DW_11 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) - -/*define for DW_12 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) - -/*define for dst_ha field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 22 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) - -/*define for src_ha field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 30 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 -#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 -#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 -#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 -#define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 -#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 -#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 -#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) - -/*define for linear_cc field*/ -#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift 20 -#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 -#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 -#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 -#define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 -#define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 -#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 -#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 -#define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 -#define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 -#define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 11 -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 -#define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) - -/*define for videocopy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) - -/*define for TILED_ADDR_LO_0 word*/ -/*define for tiled_addr0_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) - -/*define for TILED_ADDR_HI_0 word*/ -/*define for tiled_addr0_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) - -/*define for TILED_ADDR_LO_1 word*/ -/*define for tiled_addr1_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) - -/*define for TILED_ADDR_HI_1 word*/ -/*define for tiled_addr1_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) - -/*define for DW_5 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) - -/*define for DW_6 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) - -/*define for DW_7 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) - -/*define for DW_8 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) - -/*define for DW_9 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) - -/*define for DW_10 word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_T2T packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 -#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) - -/*define for dcc field*/ -#define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 -#define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) - -/*define for dcc_dir field*/ -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 -#define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) - -/*define for src_width field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) - -/*define for DW_5 word*/ -/*define for src_height field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) - -/*define for src_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) - -/*define for DW_6 word*/ -/*define for src_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) - -/*define for src_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) - -/*define for src_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) - -/*define for src_mip_max field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) - -/*define for src_mip_id field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) - -/*define for DW_10 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) - -/*define for dst_width field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) - -/*define for DW_11 word*/ -/*define for dst_height field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) - -/*define for dst_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) - -/*define for DW_12 word*/ -/*define for dst_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) - -/*define for dst_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) - -/*define for dst_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) - -/*define for dst_mip_max field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 -#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) - -/*define for dst_mip_id field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 -#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) - -/*define for DW_13 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) - -/*define for DW_14 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 -#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 -#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) - -/*define for META_ADDR_LO word*/ -/*define for meta_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) - -/*define for META_ADDR_HI word*/ -/*define for meta_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) - -/*define for META_CONFIG word*/ -/*define for data_format field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 -#define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) - -/*define for color_transform_disable field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 -#define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) - -/*define for alpha_is_on_msb field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 -#define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) - -/*define for number_type field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 -#define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) - -/*define for surface_type field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 -#define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) - -/*define for max_comp_block_size field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 -#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) - -/*define for max_uncomp_block_size field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 -#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) - -/*define for write_compress_enable field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 -#define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) - -/*define for meta_tmz field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 -#define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) - - -/* -** Definitions for SDMA_PKT_COPY_T2T_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) - -/*define for src_width field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) - -/*define for DW_5 word*/ -/*define for src_height field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) - -/*define for src_depth field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) - -/*define for DW_6 word*/ -/*define for src_element_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) - -/*define for src_array_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) - -/*define for src_mit_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) - -/*define for src_tilesplit_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) - -/*define for src_bank_w field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) - -/*define for src_bank_h field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) - -/*define for src_num_bank field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) - -/*define for src_mat_aspt field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) - -/*define for src_pipe_config field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) - -/*define for DW_10 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) - -/*define for dst_width field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) - -/*define for DW_11 word*/ -/*define for dst_height field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) - -/*define for dst_depth field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) - -/*define for DW_12 word*/ -/*define for dst_element_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) - -/*define for dst_array_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) - -/*define for dst_mit_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) - -/*define for dst_tilesplit_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) - -/*define for dst_bank_w field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) - -/*define for dst_bank_h field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) - -/*define for dst_num_bank field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) - -/*define for dst_mat_aspt field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) - -/*define for dst_pipe_config field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) - -/*define for DW_13 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) - -/*define for DW_14 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) - -/*define for dcc field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for tiled_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) - -/*define for tiled_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) - -/*define for DW_4 word*/ -/*define for tiled_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) - -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) - -/*define for DW_5 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) - -/*define for DW_6 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) - -/*define for mip_id field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for linear_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) - -/*define for linear_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) - -/*define for DW_10 word*/ -/*define for linear_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) - -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) - -/*define for DW_11 word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) - -/*define for DW_12 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) - -/*define for DW_13 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) - -/*define for META_ADDR_LO word*/ -/*define for meta_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) - -/*define for META_ADDR_HI word*/ -/*define for meta_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) - -/*define for META_CONFIG word*/ -/*define for data_format field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) - -/*define for color_transform_disable field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) - -/*define for alpha_is_on_msb field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) - -/*define for number_type field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) - -/*define for surface_type field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) - -/*define for max_comp_block_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) - -/*define for max_uncomp_block_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) - -/*define for write_compress_enable field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) - -/*define for meta_tmz field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for tiled_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) - -/*define for tiled_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) - -/*define for DW_4 word*/ -/*define for tiled_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) - -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) - -/*define for DW_5 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) - -/*define for DW_6 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for linear_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) - -/*define for linear_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) - -/*define for DW_10 word*/ -/*define for linear_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) - -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) - -/*define for DW_11 word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) - -/*define for DW_12 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) - -/*define for DW_13 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_STRUCT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) - -/*define for SB_ADDR_LO word*/ -/*define for sb_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) - -/*define for SB_ADDR_HI word*/ -/*define for sb_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) - -/*define for START_INDEX word*/ -/*define for start_index field*/ -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 -#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 -#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) - -/*define for DW_5 word*/ -/*define for stride field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 -#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) - -/*define for struct_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_UNTILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 -#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 -#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF -#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF -#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 -#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 -#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 -#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_TILED_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 -#define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 -#define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) - -/*define for pte_size field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) - -/*define for direction field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_BIT_FOR_DW word*/ -/*define for mask_first_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) - -/*define for mask_last_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) - -/*define for COUNT_IN_32B_XFER word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_RMW packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) - -/*define for mtype field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 -#define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) - -/*define for gcc field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) - -/*define for sys field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) - -/*define for snp field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) - -/*define for gpa field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 -#define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) - -/*define for MASK_LO word*/ -/*define for mask_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) - -/*define for MASK_HI word*/ -/*define for mask_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) - -/*define for VALUE_LO word*/ -/*define for value_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) - -/*define for VALUE_HI word*/ -/*define for value_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_INCR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) - -/*define for INIT_DW0 word*/ -/*define for init_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) - -/*define for INIT_DW1 word*/ -/*define for init_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) - -/*define for INCR_DW0 word*/ -/*define for incr_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) - -/*define for INCR_DW1 word*/ -/*define for incr_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 -#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_INDIRECT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 -#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 -#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) - -/*define for vmid field*/ -#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F -#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 -#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) - -/*define for priv field*/ -#define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 -#define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 -#define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) - -/*define for BASE_LO word*/ -/*define for ib_base_31_0 field*/ -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 -#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) - -/*define for BASE_HI word*/ -/*define for ib_base_63_32 field*/ -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 -#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) - -/*define for IB_SIZE word*/ -/*define for ib_size field*/ -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 -#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) - -/*define for CSA_ADDR_LO word*/ -/*define for csa_addr_31_0 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) - -/*define for CSA_ADDR_HI word*/ -/*define for csa_addr_63_32 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_SEMAPHORE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 -#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) - -/*define for write_one field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 -#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) - -/*define for signal field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 -#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) - -/*define for mailbox field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 -#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_FENCE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_FENCE_HEADER_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_op_shift 0 -#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 -#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) - -/*define for mtype field*/ -#define SDMA_PKT_FENCE_HEADER_mtype_offset 0 -#define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 -#define SDMA_PKT_FENCE_HEADER_mtype_shift 16 -#define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) - -/*define for gcc field*/ -#define SDMA_PKT_FENCE_HEADER_gcc_offset 0 -#define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_gcc_shift 19 -#define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) - -/*define for sys field*/ -#define SDMA_PKT_FENCE_HEADER_sys_offset 0 -#define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_sys_shift 20 -#define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) - -/*define for snp field*/ -#define SDMA_PKT_FENCE_HEADER_snp_offset 0 -#define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_snp_shift 22 -#define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) - -/*define for gpa field*/ -#define SDMA_PKT_FENCE_HEADER_gpa_offset 0 -#define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_gpa_shift 23 -#define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 -#define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 -#define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_FENCE_DATA_data_offset 3 -#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_DATA_data_shift 0 -#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_SRBM_WRITE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) - -/*define for byte_en field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 -#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) - -/*define for ADDR word*/ -/*define for addr field*/ -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 -#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) - -/*define for apertureid field*/ -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 -#define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 -#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 -#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_PRE_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 -#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) - -/*define for dev_sel field*/ -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 -#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_COND_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 -#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) - -/*define for REFERENCE word*/ -/*define for reference field*/ -#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 -#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 -#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_CONSTANT_FILL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) - -/*define for sw field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) - -/*define for fillsize field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 -#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DATA word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 -#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_DATA_FILL_MULTI packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) - -/*define for memlog_clr field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) - -/*define for BYTE_STRIDE word*/ -/*define for byte_stride field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) - -/*define for DMA_COUNT word*/ -/*define for dma_count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for BYTE_COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REGMEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) - -/*define for hdp_flush field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 -#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) - -/*define for func field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 -#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) - -/*define for mem_poll field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 -#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) - -/*define for VALUE word*/ -/*define for value field*/ -#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 -#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 -#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) - -/*define for MASK word*/ -/*define for mask field*/ -#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 -#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 -#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) - -/*define for DW5 word*/ -/*define for interval field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF -#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 -#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) - -/*define for retry_count field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 -#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) - -/*define for SRC_ADDR word*/ -/*define for addr_31_2 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) - -/*define for ea field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - -/*define for START_PAGE word*/ -/*define for addr_31_4 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) - -/*define for PAGE_NUM word*/ -/*define for page_num_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) - - -/* -** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) - -/*define for mode field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) - -/*define for PATTERN word*/ -/*define for pattern field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) - -/*define for CMP0_ADDR_START_LO word*/ -/*define for cmp0_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) - -/*define for CMP0_ADDR_START_HI word*/ -/*define for cmp0_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) - -/*define for CMP0_ADDR_END_LO word*/ -/*define for cmp1_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) - -/*define for CMP0_ADDR_END_HI word*/ -/*define for cmp1_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) - -/*define for CMP1_ADDR_START_LO word*/ -/*define for cmp1_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) - -/*define for CMP1_ADDR_START_HI word*/ -/*define for cmp1_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) - -/*define for CMP1_ADDR_END_LO word*/ -/*define for cmp1_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) - -/*define for CMP1_ADDR_END_HI word*/ -/*define for cmp1_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) - -/*define for REC_ADDR_LO word*/ -/*define for rec_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) - -/*define for REC_ADDR_HI word*/ -/*define for rec_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) - -/*define for RESERVED word*/ -/*define for reserved field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) - - -/* -** Definitions for SDMA_PKT_VM_INVALIDATION packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 -#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) - -/*define for gfx_eng_id field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 -#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) - -/*define for mm_eng_id field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 -#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) - -/*define for INVALIDATEREQ word*/ -/*define for invalidatereq field*/ -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) - -/*define for ADDRESSRANGELO word*/ -/*define for addressrangelo field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) - -/*define for ADDRESSRANGEHI word*/ -/*define for invalidateack field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) - -/*define for addressrangehi field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) - -/*define for reserved field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) - - -/* -** Definitions for SDMA_PKT_ATOMIC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 -#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) - -/*define for loop field*/ -#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 -#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) - -/*define for tmz field*/ -#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 -#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) - -/*define for atomic_op field*/ -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 -#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) - -/*define for SRC_DATA_LO word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) - -/*define for SRC_DATA_HI word*/ -/*define for src_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) - -/*define for CMP_DATA_LO word*/ -/*define for cmp_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) - -/*define for CMP_DATA_HI word*/ -/*define for cmp_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) - -/*define for LOOP_INTERVAL word*/ -/*define for loop_interval field*/ -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_SET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) - -/*define for INIT_DATA_LO word*/ -/*define for init_data_31_0 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) - -/*define for INIT_DATA_HI word*/ -/*define for init_data_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_DUMMY_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_GPUVM_INV packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 -#define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF -#define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 -#define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 -#define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) - -/*define for PAYLOAD1 word*/ -/*define for per_vmid_inv_req field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) - -/*define for flush_type field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) - -/*define for l2_ptes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) - -/*define for l2_pde0 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) - -/*define for l2_pde1 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) - -/*define for l2_pde2 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) - -/*define for l1_ptes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) - -/*define for clr_protection_fault_status_addr field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) - -/*define for log_request field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) - -/*define for four_kilobytes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) - -/*define for PAYLOAD2 word*/ -/*define for s field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) - -/*define for page_va_42_12 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) - -/*define for PAYLOAD3 word*/ -/*define for page_va_47_43 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) - - -/* -** Definitions for SDMA_PKT_GCR_REQ packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 -#define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF -#define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 -#define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 -#define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) - -/*define for PAYLOAD1 word*/ -/*define for base_va_31_7 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 -#define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) - -/*define for PAYLOAD2 word*/ -/*define for base_va_47_32 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) - -/*define for gcr_control_15_0 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) - -/*define for PAYLOAD3 word*/ -/*define for gcr_control_18_16 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) - -/*define for limit_va_31_7 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) - -/*define for PAYLOAD4 word*/ -/*define for limit_va_47_32 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) - -/*define for vmid field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) - - -/* -** Definitions for SDMA_PKT_NOP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_NOP_HEADER_op_offset 0 -#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_op_shift 0 -#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 -#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 -#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) - -/*define for count field*/ -#define SDMA_PKT_NOP_HEADER_count_offset 0 -#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF -#define SDMA_PKT_NOP_HEADER_count_shift 16 -#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_NOP_DATA0_data0_offset 1 -#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_NOP_DATA0_data0_shift 0 -#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) - - -/* -** Definitions for SDMA_AQL_PKT_HEADER packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 -#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 -#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) - - -/* -** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) - -/*define for RETURN_ADDR_LO word*/ -/*define for return_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) - -/*define for RETURN_ADDR_HI word*/ -/*define for return_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for RESERVED_DW10 word*/ -/*define for reserved_dw10 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) - -/*define for RESERVED_DW11 word*/ -/*define for reserved_dw11 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) - -/*define for RESERVED_DW12 word*/ -/*define for reserved_dw12 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -/* -** Definitions for SDMA_AQL_PKT_BARRIER_OR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) - -/*define for DEPENDENT_ADDR_0_LO word*/ -/*define for dependent_addr_0_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) - -/*define for DEPENDENT_ADDR_0_HI word*/ -/*define for dependent_addr_0_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) - -/*define for DEPENDENT_ADDR_1_LO word*/ -/*define for dependent_addr_1_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) - -/*define for DEPENDENT_ADDR_1_HI word*/ -/*define for dependent_addr_1_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) - -/*define for DEPENDENT_ADDR_2_LO word*/ -/*define for dependent_addr_2_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) - -/*define for DEPENDENT_ADDR_2_HI word*/ -/*define for dependent_addr_2_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) - -/*define for DEPENDENT_ADDR_3_LO word*/ -/*define for dependent_addr_3_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) - -/*define for DEPENDENT_ADDR_3_HI word*/ -/*define for dependent_addr_3_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) - -/*define for DEPENDENT_ADDR_4_LO word*/ -/*define for dependent_addr_4_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) - -/*define for DEPENDENT_ADDR_4_HI word*/ -/*define for dependent_addr_4_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) - -/*define for RESERVED_DW12 word*/ -/*define for reserved_dw12 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -#endif /* __NAVI10_SDMA_PKT_OPEN_H_ */ diff --git a/tinygrad/extra/hip_gpu_driver/nvd.h b/tinygrad/extra/hip_gpu_driver/nvd.h deleted file mode 100644 index 631dafb9..00000000 --- a/tinygrad/extra/hip_gpu_driver/nvd.h +++ /dev/null @@ -1,470 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef NVD_H -#define NVD_H - -/** - * Navi's PM4 definitions - */ -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 - -#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) -#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) -#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) -#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) -#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ - ((reg) & 0xFFFF) | \ - ((n) & 0x3FFF) << 16) -#define CP_PACKET2 0x80000000 -#define PACKET2_PAD_SHIFT 0 -#define PACKET2_PAD_MASK (0x3fffffff << 0) - -#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) - -#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ - (((op) & 0xFF) << 8) | \ - ((n) & 0x3FFF) << 16) - -#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) - -/* Packet 3 types */ -#define PACKET3_NOP 0x10 -#define PACKET3_SET_BASE 0x11 -#define PACKET3_BASE_INDEX(x) ((x) << 0) -#define CE_PARTITION_BASE 3 -#define PACKET3_CLEAR_STATE 0x12 -#define PACKET3_INDEX_BUFFER_SIZE 0x13 -#define PACKET3_DISPATCH_DIRECT 0x15 -#define PACKET3_DISPATCH_INDIRECT 0x16 -#define PACKET3_INDIRECT_BUFFER_END 0x17 -#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 -#define PACKET3_ATOMIC_GDS 0x1D -#define PACKET3_ATOMIC_MEM 0x1E -#define PACKET3_OCCLUSION_QUERY 0x1F -#define PACKET3_SET_PREDICATION 0x20 -#define PACKET3_REG_RMW 0x21 -#define PACKET3_COND_EXEC 0x22 -#define PACKET3_PRED_EXEC 0x23 -#define PACKET3_DRAW_INDIRECT 0x24 -#define PACKET3_DRAW_INDEX_INDIRECT 0x25 -#define PACKET3_INDEX_BASE 0x26 -#define PACKET3_DRAW_INDEX_2 0x27 -#define PACKET3_CONTEXT_CONTROL 0x28 -#define PACKET3_INDEX_TYPE 0x2A -#define PACKET3_DRAW_INDIRECT_MULTI 0x2C -#define PACKET3_DRAW_INDEX_AUTO 0x2D -#define PACKET3_NUM_INSTANCES 0x2F -#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 -#define PACKET3_INDIRECT_BUFFER_PRIV 0x32 -#define PACKET3_INDIRECT_BUFFER_CNST 0x33 -#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 -#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 -#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 -#define PACKET3_DRAW_PREAMBLE 0x36 -#define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) ((x) << 8) - /* 0 - register - * 1 - memory (sync - via GRBM) - * 2 - gl2 - * 3 - gds - * 4 - reserved - * 5 - memory (async - direct) - */ -#define WR_ONE_ADDR (1 << 16) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) - /* 0 - me - * 1 - pfp - * 2 - ce - */ -#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 -#define PACKET3_MEM_SEMAPHORE 0x39 -# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) -# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ -# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) -# define PACKET3_SEM_SEL_WAIT (0x7 << 29) -#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A -#define PACKET3_COPY_DW 0x3B -#define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) - /* 0 - always - * 1 - < - * 2 - <= - * 3 - == - * 4 - != - * 5 - >= - * 6 - > - */ -#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) - /* 0 - reg - * 1 - mem - */ -#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) - /* 0 - wait_reg_mem - * 1 - wr_wait_wr_reg - */ -#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) - /* 0 - me - * 1 - pfp - */ -#define PACKET3_INDIRECT_BUFFER 0x3F -#define INDIRECT_BUFFER_VALID (1 << 23) -#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) - /* 0 - LRU - * 1 - Stream - * 2 - Bypass - */ -#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) -#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) -#define PACKET3_COND_INDIRECT_BUFFER 0x3F -#define PACKET3_COPY_DATA 0x40 -#define PACKET3_CP_DMA 0x41 -#define PACKET3_PFP_SYNC_ME 0x42 -#define PACKET3_SURFACE_SYNC 0x43 -#define PACKET3_ME_INITIALIZE 0x44 -#define PACKET3_COND_WRITE 0x45 -#define PACKET3_EVENT_WRITE 0x46 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - */ -#define PACKET3_EVENT_WRITE_EOP 0x47 -#define PACKET3_EVENT_WRITE_EOS 0x48 -#define PACKET3_RELEASE_MEM 0x49 -#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) -#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) -#define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12) -#define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13) -#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) -#define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15) -#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) -#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17) -#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) -#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) -#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) -#define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22) -#define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) - /* 0 - cache_policy__me_release_mem__lru - * 1 - cache_policy__me_release_mem__stream - * 2 - cache_policy__me_release_mem__noa - * 3 - cache_policy__me_release_mem__bypass - */ -#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) - -#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) - /* 0 - discard - * 1 - send low 32bit data - * 2 - send 64bit data - * 3 - send 64bit GPU counter value - * 4 - send 64bit sys counter value - */ -#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) - /* 0 - none - * 1 - interrupt only (DATA_SEL = 0) - * 2 - interrupt when data write is confirmed - */ -#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) - /* 0 - MC - * 1 - TC/L2 - */ - - - -#define PACKET3_PREAMBLE_CNTL 0x4A -# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) -# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) -#define PACKET3_DMA_DATA 0x50 -/* 1. header - * 2. CONTROL - * 3. SRC_ADDR_LO or DATA [31:0] - * 4. SRC_ADDR_HI [31:0] - * 5. DST_ADDR_LO [31:0] - * 6. DST_ADDR_HI [7:0] - * 7. COMMAND [31:26] | BYTE_COUNT [25:0] - */ -/* CONTROL */ -# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) - /* 0 - ME - * 1 - PFP - */ -# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) - /* 0 - LRU - * 1 - Stream - */ -# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) - /* 0 - DST_ADDR using DAS - * 1 - GDS - * 3 - DST_ADDR using L2 - */ -# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) - /* 0 - SRC_ADDR using SAS - * 1 - GDS - * 2 - DATA - * 3 - SRC_ADDR using L2 - */ -# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) -/* COMMAND */ -# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) -# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) -# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) -#define PACKET3_CONTEXT_REG_RMW 0x51 -#define PACKET3_GFX_CNTX_UPDATE 0x52 -#define PACKET3_BLK_CNTX_UPDATE 0x53 -#define PACKET3_INCR_UPDT_STATE 0x55 -#define PACKET3_ACQUIRE_MEM 0x58 -/* 1. HEADER - * 2. COHER_CNTL [30:0] - * 2.1 ENGINE_SEL [31:31] - * 2. COHER_SIZE [31:0] - * 3. COHER_SIZE_HI [7:0] - * 4. COHER_BASE_LO [31:0] - * 5. COHER_BASE_HI [23:0] - * 7. POLL_INTERVAL [15:0] - * 8. GCR_CNTL [18:0] - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) - /* - * 0:NOP - * 1:ALL - * 2:RANGE - * 3:FIRST_LAST - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) - /* - * 0:ALL - * 1:reserved - * 2:RANGE - * 3:FIRST_LAST - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) - /* - * 0:ALL - * 1:VOL - * 2:RANGE - * 3:FIRST_LAST - */ -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) -#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) - /* - * 0: PARALLEL - * 1: FORWARD - * 2: REVERSE - */ -#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) -#define PACKET3_REWIND 0x59 -#define PACKET3_INTERRUPT 0x5A -#define PACKET3_GEN_PDEPTE 0x5B -#define PACKET3_INDIRECT_BUFFER_PASID 0x5C -#define PACKET3_PRIME_UTCL2 0x5D -#define PACKET3_LOAD_UCONFIG_REG 0x5E -#define PACKET3_LOAD_SH_REG 0x5F -#define PACKET3_LOAD_CONFIG_REG 0x60 -#define PACKET3_LOAD_CONTEXT_REG 0x61 -#define PACKET3_LOAD_COMPUTE_STATE 0x62 -#define PACKET3_LOAD_SH_REG_INDEX 0x63 -#define PACKET3_SET_CONFIG_REG 0x68 -#define PACKET3_SET_CONFIG_REG_START 0x00002000 -#define PACKET3_SET_CONFIG_REG_END 0x00002c00 -#define PACKET3_SET_CONTEXT_REG 0x69 -#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 -#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 -#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A -#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 -#define PACKET3_SET_SH_REG_DI 0x72 -#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 -#define PACKET3_SET_SH_REG_DI_MULTI 0x74 -#define PACKET3_GFX_PIPE_LOCK 0x75 -#define PACKET3_SET_SH_REG 0x76 -#define PACKET3_SET_SH_REG_START 0x00002c00 -#define PACKET3_SET_SH_REG_END 0x00003000 -#define PACKET3_SET_SH_REG_OFFSET 0x77 -#define PACKET3_SET_QUEUE_REG 0x78 -#define PACKET3_SET_UCONFIG_REG 0x79 -#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 -#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 -#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A -#define PACKET3_FORWARD_HEADER 0x7C -#define PACKET3_SCRATCH_RAM_WRITE 0x7D -#define PACKET3_SCRATCH_RAM_READ 0x7E -#define PACKET3_LOAD_CONST_RAM 0x80 -#define PACKET3_WRITE_CONST_RAM 0x81 -#define PACKET3_DUMP_CONST_RAM 0x83 -#define PACKET3_INCREMENT_CE_COUNTER 0x84 -#define PACKET3_INCREMENT_DE_COUNTER 0x85 -#define PACKET3_WAIT_ON_CE_COUNTER 0x86 -#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 -#define PACKET3_SWITCH_BUFFER 0x8B -#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C -#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C -#define PACKET3_DISPATCH_DRAW 0x8D -#define PACKET3_DISPATCH_DRAW_ACE 0x8D -#define PACKET3_GET_LOD_STATS 0x8E -#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F -#define PACKET3_FRAME_CONTROL 0x90 -# define FRAME_TMZ (1 << 0) -# define FRAME_CMD(x) ((x) << 28) - /* - * x=0: tmz_begin - * x=1: tmz_end - */ -#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 -#define PACKET3_WAIT_REG_MEM64 0x93 -#define PACKET3_COND_PREEMPT 0x94 -#define PACKET3_HDP_FLUSH 0x95 -#define PACKET3_COPY_DATA_RB 0x96 -#define PACKET3_INVALIDATE_TLBS 0x98 -# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) -# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) -# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) -#define PACKET3_AQL_PACKET 0x99 -#define PACKET3_DMA_DATA_FILL_MULTI 0x9A -#define PACKET3_SET_SH_REG_INDEX 0x9B -#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C -#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D -#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E -#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F -#define PACKET3_SET_RESOURCES 0xA0 -/* 1. header - * 2. CONTROL - * 3. QUEUE_MASK_LO [31:0] - * 4. QUEUE_MASK_HI [31:0] - * 5. GWS_MASK_LO [31:0] - * 6. GWS_MASK_HI [31:0] - * 7. OAC_MASK [15:0] - * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] - */ -# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) -# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) -# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) -#define PACKET3_MAP_PROCESS 0xA1 -#define PACKET3_MAP_QUEUES 0xA2 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. MQD_ADDR_LO [31:0] - * 5. MQD_ADDR_HI [31:0] - * 6. WPTR_ADDR_LO [31:0] - * 7. WPTR_ADDR_HI [31:0] - */ -/* CONTROL */ -# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) -# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) -# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) -# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) -# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) -# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) -# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) -# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) -# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) -/* CONTROL2 */ -# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) -# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) -#define PACKET3_UNMAP_QUEUES 0xA3 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. CONTROL3 - * 5. CONTROL4 - * 6. CONTROL5 - */ -/* CONTROL */ -# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) - /* 0 - PREEMPT_QUEUES - * 1 - RESET_QUEUES - * 2 - DISABLE_PROCESS_QUEUES - * 3 - PREEMPT_QUEUES_NO_UNMAP - */ -# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) -# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) -# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) -/* CONTROL2a */ -# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) -/* CONTROL2b */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) -/* CONTROL3a */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) -/* CONTROL3b */ -# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) -/* CONTROL4 */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) -/* CONTROL5 */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) -#define PACKET3_QUERY_STATUS 0xA4 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. ADDR_LO [31:0] - * 5. ADDR_HI [31:0] - * 6. DATA_LO [31:0] - * 7. DATA_HI [31:0] - */ -/* CONTROL */ -# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) -# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) -# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) -/* CONTROL2a */ -# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) -/* CONTROL2b */ -# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) -# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) -#define PACKET3_RUN_LIST 0xA5 -#define PACKET3_MAP_PROCESS_VM 0xA6 -/* GFX11 */ -#define PACKET3_SET_Q_PREEMPTION_MODE 0xF0 -# define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) -# define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0) - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/sdma_registers.h b/tinygrad/extra/hip_gpu_driver/sdma_registers.h deleted file mode 100644 index 254744f6..00000000 --- a/tinygrad/extra/hip_gpu_driver/sdma_registers.h +++ /dev/null @@ -1,571 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// The University of Illinois/NCSA -// Open Source License (NCSA) -// -// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved. -// -// Developed by: -// -// AMD Research and AMD HSA Software Development -// -// Advanced Micro Devices, Inc. -// -// www.amd.com -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to -// deal with the Software without restriction, including without limitation -// the rights to use, copy, modify, merge, publish, distribute, sublicense, -// and/or sell copies of the Software, and to permit persons to whom the -// Software is furnished to do so, subject to the following conditions: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimers. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimers in -// the documentation and/or other materials provided with the distribution. -// - Neither the names of Advanced Micro Devices, Inc, -// nor the names of its contributors may be used to endorse or promote -// products derived from this Software without specific prior written -// permission. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR -// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -// DEALINGS WITH THE SOFTWARE. -// -//////////////////////////////////////////////////////////////////////////////// - -#ifndef HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ -#define HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ - -#include -#include - -namespace rocr { -namespace AMD { - -// SDMA packet for VI device. -// Reference: http://people.freedesktop.org/~agd5f/dma_packets.txt - -const unsigned int SDMA_OP_COPY = 1; -const unsigned int SDMA_OP_FENCE = 5; -const unsigned int SDMA_OP_TRAP = 6; -const unsigned int SDMA_OP_POLL_REGMEM = 8; -const unsigned int SDMA_OP_ATOMIC = 10; -const unsigned int SDMA_OP_CONST_FILL = 11; -const unsigned int SDMA_OP_TIMESTAMP = 13; -const unsigned int SDMA_OP_GCR = 17; -const unsigned int SDMA_SUBOP_COPY_LINEAR = 0; -const unsigned int SDMA_SUBOP_COPY_LINEAR_RECT = 4; -const unsigned int SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2; -const unsigned int SDMA_SUBOP_USER_GCR = 1; -const unsigned int SDMA_ATOMIC_ADD64 = 47; - -typedef struct SDMA_PKT_COPY_LINEAR_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int extra_info : 16; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int count : 22; - unsigned int reserved_0 : 10; - }; - unsigned int DW_1_DATA; - } COUNT_UNION; - - union { - struct { - unsigned int reserved_0 : 16; - unsigned int dst_swap : 2; - unsigned int reserved_1 : 6; - unsigned int src_swap : 2; - unsigned int reserved_2 : 6; - }; - unsigned int DW_2_DATA; - } PARAMETER_UNION; - - union { - struct { - unsigned int src_addr_31_0 : 32; - }; - unsigned int DW_3_DATA; - } SRC_ADDR_LO_UNION; - - union { - struct { - unsigned int src_addr_63_32 : 32; - }; - unsigned int DW_4_DATA; - } SRC_ADDR_HI_UNION; - - union { - struct { - unsigned int dst_addr_31_0 : 32; - }; - unsigned int DW_5_DATA; - } DST_ADDR_LO_UNION; - - union { - struct { - unsigned int dst_addr_63_32 : 32; - }; - unsigned int DW_6_DATA; - } DST_ADDR_HI_UNION; - - static const size_t kMaxSize_ = 0x3fffe0; -} SDMA_PKT_COPY_LINEAR; - -// linear sub-window -typedef struct SDMA_PKT_COPY_LINEAR_RECT_TAG { - static const unsigned int pitch_bits = 19; - static const unsigned int slice_bits = 28; - static const unsigned int rect_xy_bits = 14; - static const unsigned int rect_z_bits = 11; - - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int reserved : 13; - unsigned int element : 3; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int src_addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } SRC_ADDR_LO_UNION; - - union { - struct { - unsigned int src_addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } SRC_ADDR_HI_UNION; - - union { - struct { - unsigned int src_offset_x : 14; - unsigned int reserved_1 : 2; - unsigned int src_offset_y : 14; - unsigned int reserved_2 : 2; - }; - unsigned int DW_3_DATA; - } SRC_PARAMETER_1_UNION; - - union { - struct { - unsigned int src_offset_z : 11; - unsigned int reserved_1 : 2; - unsigned int src_pitch : pitch_bits; - }; - unsigned int DW_4_DATA; - } SRC_PARAMETER_2_UNION; - - union { - struct { - unsigned int src_slice_pitch : slice_bits; - unsigned int reserved_1 : 4; - }; - unsigned int DW_5_DATA; - } SRC_PARAMETER_3_UNION; - - union { - struct { - unsigned int dst_addr_31_0 : 32; - }; - unsigned int DW_6_DATA; - } DST_ADDR_LO_UNION; - - union { - struct { - unsigned int dst_addr_63_32 : 32; - }; - unsigned int DW_7_DATA; - } DST_ADDR_HI_UNION; - - union { - struct { - unsigned int dst_offset_x : 14; - unsigned int reserved_1 : 2; - unsigned int dst_offset_y : 14; - unsigned int reserved_2 : 2; - }; - unsigned int DW_8_DATA; - } DST_PARAMETER_1_UNION; - - union { - struct { - unsigned int dst_offset_z : 11; - unsigned int reserved_1 : 2; - unsigned int dst_pitch : pitch_bits; - }; - unsigned int DW_9_DATA; - } DST_PARAMETER_2_UNION; - - union { - struct { - unsigned int dst_slice_pitch : slice_bits; - unsigned int reserved_1 : 4; - }; - unsigned int DW_10_DATA; - } DST_PARAMETER_3_UNION; - - union { - struct { - unsigned int rect_x : rect_xy_bits; - unsigned int reserved_1 : 2; - unsigned int rect_y : rect_xy_bits; - unsigned int reserved_2 : 2; - }; - unsigned int DW_11_DATA; - } RECT_PARAMETER_1_UNION; - - union { - struct { - unsigned int rect_z : rect_z_bits; - unsigned int reserved_1 : 5; - unsigned int dst_swap : 2; - unsigned int reserved_2 : 6; - unsigned int src_swap : 2; - unsigned int reserved_3 : 6; - }; - unsigned int DW_12_DATA; - } RECT_PARAMETER_2_UNION; - -} SDMA_PKT_COPY_LINEAR_RECT; - -typedef struct SDMA_PKT_CONSTANT_FILL_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int sw : 2; - unsigned int reserved_0 : 12; - unsigned int fillsize : 2; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int dst_addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } DST_ADDR_LO_UNION; - - union { - struct { - unsigned int dst_addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } DST_ADDR_HI_UNION; - - union { - struct { - unsigned int src_data_31_0 : 32; - }; - unsigned int DW_3_DATA; - } DATA_UNION; - - union { - struct { - unsigned int count : 22; - unsigned int reserved_0 : 10; - }; - unsigned int DW_4_DATA; - } COUNT_UNION; - - static const size_t kMaxSize_ = 0x3fffe0; -} SDMA_PKT_CONSTANT_FILL; - -typedef struct SDMA_PKT_FENCE_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int mtype : 3; - unsigned int gcc : 1; - unsigned int sys : 1; - unsigned int pad1 : 1; - unsigned int snp : 1; - unsigned int gpa : 1; - unsigned int l2_policy : 2; - unsigned int reserved_0 : 6; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } ADDR_LO_UNION; - - union { - struct { - unsigned int addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } ADDR_HI_UNION; - - union { - struct { - unsigned int data : 32; - }; - unsigned int DW_3_DATA; - } DATA_UNION; -} SDMA_PKT_FENCE; - -typedef struct SDMA_PKT_POLL_REGMEM_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int reserved_0 : 10; - unsigned int hdp_flush : 1; - unsigned int reserved_1 : 1; - unsigned int func : 3; - unsigned int mem_poll : 1; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } ADDR_LO_UNION; - - union { - struct { - unsigned int addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } ADDR_HI_UNION; - - union { - struct { - unsigned int value : 32; - }; - unsigned int DW_3_DATA; - } VALUE_UNION; - - union { - struct { - unsigned int mask : 32; - }; - unsigned int DW_4_DATA; - } MASK_UNION; - - union { - struct { - unsigned int interval : 16; - unsigned int retry_count : 12; - unsigned int reserved_0 : 4; - }; - unsigned int DW_5_DATA; - } DW5_UNION; -} SDMA_PKT_POLL_REGMEM; - -typedef struct SDMA_PKT_ATOMIC_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int l : 1; - unsigned int reserved_0 : 8; - unsigned int operation : 7; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } ADDR_LO_UNION; - - union { - struct { - unsigned int addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } ADDR_HI_UNION; - - union { - struct { - unsigned int src_data_31_0 : 32; - }; - unsigned int DW_3_DATA; - } SRC_DATA_LO_UNION; - - union { - struct { - unsigned int src_data_63_32 : 32; - }; - unsigned int DW_4_DATA; - } SRC_DATA_HI_UNION; - - union { - struct { - unsigned int cmp_data_31_0 : 32; - }; - unsigned int DW_5_DATA; - } CMP_DATA_LO_UNION; - - union { - struct { - unsigned int cmp_data_63_32 : 32; - }; - unsigned int DW_6_DATA; - } CMP_DATA_HI_UNION; - - union { - struct { - unsigned int loop_interval : 13; - unsigned int reserved_0 : 19; - }; - unsigned int DW_7_DATA; - } LOOP_UNION; -} SDMA_PKT_ATOMIC; - -typedef struct SDMA_PKT_TIMESTAMP_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int reserved_0 : 16; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int addr_31_0 : 32; - }; - unsigned int DW_1_DATA; - } ADDR_LO_UNION; - - union { - struct { - unsigned int addr_63_32 : 32; - }; - unsigned int DW_2_DATA; - } ADDR_HI_UNION; - -} SDMA_PKT_TIMESTAMP; - -typedef struct SDMA_PKT_TRAP_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int reserved_0 : 16; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int int_ctx : 28; - unsigned int reserved_1 : 4; - }; - unsigned int DW_1_DATA; - } INT_CONTEXT_UNION; -} SDMA_PKT_TRAP; - -// HDP flush packet, no parameters. -typedef struct SDMA_PKT_HDP_FLUSH_TAG { - unsigned int DW_0_DATA; - unsigned int DW_1_DATA; - unsigned int DW_2_DATA; - unsigned int DW_3_DATA; - unsigned int DW_4_DATA; - unsigned int DW_5_DATA; - - // Version of gfx9 sDMA microcode introducing SDMA_PKT_HDP_FLUSH - static const uint16_t kMinVersion_ = 0x1A5; -} SDMA_PKT_HDP_FLUSH; -static const SDMA_PKT_HDP_FLUSH hdp_flush_cmd = {0x8, 0x0, 0x80000000, 0x0, 0x0, 0x0}; - -typedef struct SDMA_PKT_GCR_TAG { - union { - struct { - unsigned int op : 8; - unsigned int sub_op : 8; - unsigned int : 16; - }; - unsigned int DW_0_DATA; - } HEADER_UNION; - - union { - struct { - unsigned int : 7; - unsigned int BaseVA_LO : 25; - }; - unsigned int DW_1_DATA; - } WORD1_UNION; - - union { - struct { - unsigned int BaseVA_HI : 16; - unsigned int GCR_CONTROL_GLI_INV : 2; - unsigned int GCR_CONTROL_GL1_RANGE : 2; - unsigned int GCR_CONTROL_GLM_WB : 1; - unsigned int GCR_CONTROL_GLM_INV : 1; - unsigned int GCR_CONTROL_GLK_WB : 1; - unsigned int GCR_CONTROL_GLK_INV : 1; - unsigned int GCR_CONTROL_GLV_INV : 1; - unsigned int GCR_CONTROL_GL1_INV : 1; - unsigned int GCR_CONTROL_GL2_US : 1; - unsigned int GCR_CONTROL_GL2_RANGE : 2; - unsigned int GCR_CONTROL_GL2_DISCARD : 1; - unsigned int GCR_CONTROL_GL2_INV : 1; - unsigned int GCR_CONTROL_GL2_WB : 1; - }; - unsigned int DW_2_DATA; - } WORD2_UNION; - - union { - struct { - unsigned int GCR_CONTROL_RANGE_IS_PA : 1; - unsigned int GCR_CONTROL_SEQ : 2; - unsigned int : 4; - unsigned int LimitVA_LO : 25; - }; - unsigned int DW_3_DATA; - } WORD3_UNION; - - union { - struct { - unsigned int LimitVA_HI : 16; - unsigned int : 8; - unsigned int VMID : 4; - unsigned int : 4; - }; - unsigned int DW_4_DATA; - } WORD4_UNION; -} SDMA_PKT_GCR; - -} // namespace amd -} // namespace rocr - -#endif // HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ diff --git a/tinygrad/extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h b/tinygrad/extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h deleted file mode 100644 index 6af23e78..00000000 --- a/tinygrad/extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h +++ /dev/null @@ -1,5664 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef __SDMA_V6_0_0_PKT_OPEN_H_ -#define __SDMA_V6_0_0_PKT_OPEN_H_ - -#define SDMA_OP_NOP 0 -#define SDMA_OP_COPY 1 -#define SDMA_OP_WRITE 2 -#define SDMA_OP_INDIRECT 4 -#define SDMA_OP_FENCE 5 -#define SDMA_OP_TRAP 6 -#define SDMA_OP_SEM 7 -#define SDMA_OP_POLL_REGMEM 8 -#define SDMA_OP_COND_EXE 9 -#define SDMA_OP_ATOMIC 10 -#define SDMA_OP_CONST_FILL 11 -#define SDMA_OP_PTEPDE 12 -#define SDMA_OP_TIMESTAMP 13 -#define SDMA_OP_SRBM_WRITE 14 -#define SDMA_OP_PRE_EXE 15 -#define SDMA_OP_GPUVM_INV 16 -#define SDMA_OP_GCR_REQ 17 -#define SDMA_OP_DUMMY_TRAP 32 -#define SDMA_SUBOP_TIMESTAMP_SET 0 -#define SDMA_SUBOP_TIMESTAMP_GET 1 -#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 -#define SDMA_SUBOP_COPY_LINEAR 0 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 -#define SDMA_SUBOP_COPY_TILED 1 -#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 -#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 -#define SDMA_SUBOP_COPY_SOA 3 -#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 -#define SDMA_SUBOP_COPY_LINEAR_PHY 8 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE 36 -#define SDMA_SUBOP_COPY_LINEAR_BC 16 -#define SDMA_SUBOP_COPY_TILED_BC 17 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 -#define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 -#define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 -#define SDMA_SUBOP_WRITE_LINEAR 0 -#define SDMA_SUBOP_WRITE_TILED 1 -#define SDMA_SUBOP_WRITE_TILED_BC 17 -#define SDMA_SUBOP_PTEPDE_GEN 0 -#define SDMA_SUBOP_PTEPDE_COPY 1 -#define SDMA_SUBOP_PTEPDE_RMW 2 -#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 -#define SDMA_SUBOP_MEM_INCR 1 -#define SDMA_SUBOP_DATA_FILL_MULTI 1 -#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 -#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 -#define SDMA_SUBOP_POLL_MEM_VERIFY 3 -#define SDMA_SUBOP_VM_INVALIDATION 4 -#define HEADER_AGENT_DISPATCH 4 -#define HEADER_BARRIER 5 -#define SDMA_OP_AQL_COPY 0 -#define SDMA_OP_AQL_BARRIER_OR 0 - -#define SDMA_GCR_RANGE_IS_PA (1 << 18) -#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) -#define SDMA_GCR_GL2_WB (1 << 15) -#define SDMA_GCR_GL2_INV (1 << 14) -#define SDMA_GCR_GL2_DISCARD (1 << 13) -#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) -#define SDMA_GCR_GL2_US (1 << 10) -#define SDMA_GCR_GL1_INV (1 << 9) -#define SDMA_GCR_GLV_INV (1 << 8) -#define SDMA_GCR_GLK_INV (1 << 7) -#define SDMA_GCR_GLK_WB (1 << 6) -#define SDMA_GCR_GLM_INV (1 << 5) -#define SDMA_GCR_GLM_WB (1 << 4) -#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) -#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) -/* -** Definitions for SDMA_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift) - -/*define for backwards field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 -#define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x3FFFFFFF -#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for dst_cache_policy field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_cache_policy field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) - -/*define for dst_ha field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 19 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) - -/*define for src_ha field*/ -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 27 -#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift) - -/*define for all field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_mtype field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) - -/*define for dst_l2_policy field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) - -/*define for dst_llc field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift 8 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift) - -/*define for src_mtype field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) - -/*define for src_l2_policy field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) - -/*define for src_llc field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift 16 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 17 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) - -/*define for addr_pair_num field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset 1 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift 24 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift) - -/*define for PARAMETER word*/ -/*define for dst_mtype field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) - -/*define for dst_l2_policy field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) - -/*define for dst_llc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift 8 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift) - -/*define for src_mtype field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) - -/*define for src_l2_policy field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) - -/*define for src_llc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift 16 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 17 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) - -/*define for dst_log field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x3FFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) - -/*define for dst2_cache_policy field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift 10 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift) - -/*define for dst1_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) - -/*define for dst1_cache_policy field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift 18 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_cache_policy field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift 26 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST1_ADDR_LO word*/ -/*define for dst1_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) - -/*define for DST1_ADDR_HI word*/ -/*define for dst1_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) - -/*define for DST2_ADDR_LO word*/ -/*define for dst2_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) - -/*define for DST2_ADDR_HI word*/ -/*define for dst2_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift) - -/*define for elementsize field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) - -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) - -/*define for DW_5 word*/ -/*define for src_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_8 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) - -/*define for DW_9 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) - -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) - -/*define for DW_10 word*/ -/*define for dst_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) - -/*define for DW_11 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) - -/*define for DW_12 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) - -/*define for dst_cache_policy field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) - -/*define for src_cache_policy field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift 26 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift) - -/*define for DW_4 word*/ -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift) - -/*define for DW_5 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift) - -/*define for DW_6 word*/ -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift) - -/*define for DW_7 word*/ -/*define for src_slice_pitch_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift) - -/*define for DW_8 word*/ -/*define for src_slice_pitch_47_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask 0x0000FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_11 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift) - -/*define for DW_12 word*/ -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift) - -/*define for DW_13 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift) - -/*define for DW_14 word*/ -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset 14 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift) - -/*define for DW_15 word*/ -/*define for dst_slice_pitch_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset 15 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift) - -/*define for DW_16 word*/ -/*define for dst_slice_pitch_47_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask 0x0000FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift) - -/*define for dst_policy field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift) - -/*define for src_policy field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift 26 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift) - -/*define for DW_17 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset 17 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift) - -/*define for DW_18 word*/ -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift) - -/*define for DW_19 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset 19 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) - -/*define for elementsize field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) - -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) - -/*define for DW_5 word*/ -/*define for src_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_8 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) - -/*define for DW_9 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) - -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) - -/*define for DW_10 word*/ -/*define for dst_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) - -/*define for DW_11 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) - -/*define for DW_12 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) - -/*define for dst_ha field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 19 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) - -/*define for src_ha field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 27 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_TILED_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 -#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 -#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 -#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 -#define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 -#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 -#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 -#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) - -/*define for linear_cache_policy field*/ -#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift 18 -#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) - -/*define for tile_cache_policy field*/ -#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift 26 -#define SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 -#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x3FFFFFFF -#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 -#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 -#define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 -#define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 -#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 -#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 -#define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 -#define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 -#define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 -#define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 12 -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 -#define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift 19 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift) - -/*define for videocopy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) - -/*define for TILED_ADDR_LO_0 word*/ -/*define for tiled_addr0_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) - -/*define for TILED_ADDR_HI_0 word*/ -/*define for tiled_addr0_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) - -/*define for TILED_ADDR_LO_1 word*/ -/*define for tiled_addr1_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) - -/*define for TILED_ADDR_HI_1 word*/ -/*define for tiled_addr1_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) - -/*define for DW_5 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) - -/*define for DW_6 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) - -/*define for DW_7 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) - -/*define for DW_8 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) - -/*define for DW_9 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) - -/*define for DW_10 word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) - -/*define for dst2_cache_policy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) - -/*define for linear_cache_policy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift 18 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) - -/*define for tile_cache_policy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift 26 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x3FFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_T2T packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 -#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) - -/*define for dcc field*/ -#define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 -#define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_T2T_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_cpv_shift 28 -#define SDMA_PKT_COPY_T2T_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift) - -/*define for dcc_dir field*/ -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 -#define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) - -/*define for src_width field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) - -/*define for DW_5 word*/ -/*define for src_height field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) - -/*define for src_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) - -/*define for DW_6 word*/ -/*define for src_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) - -/*define for src_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) - -/*define for src_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) - -/*define for src_mip_max field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) - -/*define for src_mip_id field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) - -/*define for DW_10 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) - -/*define for dst_width field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) - -/*define for DW_11 word*/ -/*define for dst_height field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) - -/*define for dst_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) - -/*define for DW_12 word*/ -/*define for dst_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) - -/*define for dst_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) - -/*define for dst_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) - -/*define for dst_mip_max field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 -#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) - -/*define for dst_mip_id field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 -#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) - -/*define for DW_13 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) - -/*define for DW_14 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 -#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) - -/*define for dst_cache_policy field*/ -#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift 18 -#define SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 -#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) - -/*define for src_cache_policy field*/ -#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift 26 -#define SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift) - -/*define for META_ADDR_LO word*/ -/*define for meta_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) - -/*define for META_ADDR_HI word*/ -/*define for meta_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) - -/*define for META_CONFIG word*/ -/*define for data_format field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F -#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 -#define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) - -/*define for color_transform_disable field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 -#define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) - -/*define for alpha_is_on_msb field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 -#define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) - -/*define for number_type field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 -#define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) - -/*define for surface_type field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 -#define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) - -/*define for meta_llc field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift 14 -#define SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift) - -/*define for max_comp_block_size field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 -#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) - -/*define for max_uncomp_block_size field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 -#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) - -/*define for write_compress_enable field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 -#define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) - -/*define for meta_tmz field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 -#define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) - -/*define for pipe_aligned field*/ -#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset 17 -#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift 31 -#define SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift) - - -/* -** Definitions for SDMA_PKT_COPY_T2T_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) - -/*define for src_width field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) - -/*define for DW_5 word*/ -/*define for src_height field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) - -/*define for src_depth field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) - -/*define for DW_6 word*/ -/*define for src_element_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) - -/*define for src_array_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) - -/*define for src_mit_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) - -/*define for src_tilesplit_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) - -/*define for src_bank_w field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) - -/*define for src_bank_h field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) - -/*define for src_num_bank field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) - -/*define for src_mat_aspt field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) - -/*define for src_pipe_config field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 -#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) - -/*define for DW_10 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) - -/*define for dst_width field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) - -/*define for DW_11 word*/ -/*define for dst_height field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) - -/*define for dst_depth field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF -#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) - -/*define for DW_12 word*/ -/*define for dst_element_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) - -/*define for dst_array_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) - -/*define for dst_mit_mode field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) - -/*define for dst_tilesplit_size field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) - -/*define for dst_bank_w field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) - -/*define for dst_bank_h field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) - -/*define for dst_num_bank field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) - -/*define for dst_mat_aspt field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) - -/*define for dst_pipe_config field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 -#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) - -/*define for DW_13 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) - -/*define for DW_14 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 -#define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 -#define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 -#define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) - -/*define for dcc field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift 28 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for tiled_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) - -/*define for tiled_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) - -/*define for DW_4 word*/ -/*define for tiled_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) - -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) - -/*define for DW_5 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) - -/*define for DW_6 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) - -/*define for mip_id field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for linear_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) - -/*define for linear_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) - -/*define for DW_10 word*/ -/*define for linear_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) - -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) - -/*define for DW_11 word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) - -/*define for DW_12 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) - -/*define for DW_13 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) - -/*define for linear_cache_policy field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) - -/*define for tile_cache_policy field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift 26 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift) - -/*define for META_ADDR_LO word*/ -/*define for meta_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) - -/*define for META_ADDR_HI word*/ -/*define for meta_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) - -/*define for META_CONFIG word*/ -/*define for data_format field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) - -/*define for color_transform_disable field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) - -/*define for alpha_is_on_msb field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) - -/*define for number_type field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) - -/*define for surface_type field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) - -/*define for meta_llc field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift 14 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift) - -/*define for max_comp_block_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) - -/*define for max_uncomp_block_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) - -/*define for write_compress_enable field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) - -/*define for meta_tmz field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) - -/*define for pipe_aligned field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for tiled_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) - -/*define for tiled_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) - -/*define for DW_4 word*/ -/*define for tiled_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) - -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) - -/*define for DW_5 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) - -/*define for DW_6 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for linear_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) - -/*define for linear_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) - -/*define for DW_10 word*/ -/*define for linear_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) - -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) - -/*define for DW_11 word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) - -/*define for DW_12 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) - -/*define for DW_13 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_STRUCT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift 28 -#define SDMA_PKT_COPY_STRUCT_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) - -/*define for SB_ADDR_LO word*/ -/*define for sb_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) - -/*define for SB_ADDR_HI word*/ -/*define for sb_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) - -/*define for START_INDEX word*/ -/*define for start_index field*/ -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 -#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 -#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) - -/*define for DW_5 word*/ -/*define for stride field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 -#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) - -/*define for linear_cache_policy field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift 18 -#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift) - -/*define for struct_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) - -/*define for struct_cache_policy field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask 0x00000007 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift 26 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_UNTILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift 28 -#define SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 -#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask 0x00000007 -#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift 26 -#define SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_cpv_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_cpv_shift 28 -#define SDMA_PKT_WRITE_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 -#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF -#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F -#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF -#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 -#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift 26 -#define SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 -#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 -#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_TILED_BC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 -#define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) - -/*define for array_mode field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F -#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) - -/*define for mit_mode field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) - -/*define for tilesplit_size field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) - -/*define for bank_w field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) - -/*define for bank_h field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) - -/*define for num_bank field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) - -/*define for mat_aspt field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) - -/*define for pipe_config field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F -#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 -#define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 -#define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 -#define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 -#define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 -#define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) - -/*define for cpv field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift 28 -#define SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) - -/*define for dst_cache_policy field*/ -#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset 7 -#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask 0x00000007 -#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift 22 -#define SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift) - -/*define for src_cache_policy field*/ -#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset 7 -#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask 0x00000007 -#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift 29 -#define SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) - -/*define for pte_size field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) - -/*define for direction field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_BIT_FOR_DW word*/ -/*define for mask_first_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) - -/*define for mask_last_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) - -/*define for COUNT_IN_32B_XFER word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_RMW packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) - -/*define for mtype field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 -#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 -#define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) - -/*define for gcc field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) - -/*define for sys field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) - -/*define for snp field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) - -/*define for gpa field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 -#define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) - -/*define for llc_policy field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift 26 -#define SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift 28 -#define SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) - -/*define for MASK_LO word*/ -/*define for mask_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) - -/*define for MASK_HI word*/ -/*define for mask_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) - -/*define for VALUE_LO word*/ -/*define for value_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) - -/*define for VALUE_HI word*/ -/*define for value_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) - -/*define for COUNT word*/ -/*define for num_of_pte field*/ -#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset 7 -#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift 0 -#define SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x) (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift) - - -/* -** Definitions for SDMA_PKT_REGISTER_RMW packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_REGISTER_RMW_HEADER_op_offset 0 -#define SDMA_PKT_REGISTER_RMW_HEADER_op_mask 0x000000FF -#define SDMA_PKT_REGISTER_RMW_HEADER_op_shift 0 -#define SDMA_PKT_REGISTER_RMW_HEADER_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset 0 -#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift 8 -#define SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift) - -/*define for ADDR word*/ -/*define for addr field*/ -#define SDMA_PKT_REGISTER_RMW_ADDR_addr_offset 1 -#define SDMA_PKT_REGISTER_RMW_ADDR_addr_mask 0x000FFFFF -#define SDMA_PKT_REGISTER_RMW_ADDR_addr_shift 0 -#define SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift) - -/*define for aperture_id field*/ -#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset 1 -#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask 0x00000FFF -#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift 20 -#define SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift) - -/*define for MASK word*/ -/*define for mask field*/ -#define SDMA_PKT_REGISTER_RMW_MASK_mask_offset 2 -#define SDMA_PKT_REGISTER_RMW_MASK_mask_mask 0xFFFFFFFF -#define SDMA_PKT_REGISTER_RMW_MASK_mask_shift 0 -#define SDMA_PKT_REGISTER_RMW_MASK_MASK(x) (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift) - -/*define for VALUE word*/ -/*define for value field*/ -#define SDMA_PKT_REGISTER_RMW_VALUE_value_offset 3 -#define SDMA_PKT_REGISTER_RMW_VALUE_value_mask 0xFFFFFFFF -#define SDMA_PKT_REGISTER_RMW_VALUE_value_shift 0 -#define SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x) (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift) - -/*define for MISC word*/ -/*define for stride field*/ -#define SDMA_PKT_REGISTER_RMW_MISC_stride_offset 4 -#define SDMA_PKT_REGISTER_RMW_MISC_stride_mask 0x000FFFFF -#define SDMA_PKT_REGISTER_RMW_MISC_stride_shift 0 -#define SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift) - -/*define for num_of_reg field*/ -#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset 4 -#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask 0x00000FFF -#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift 20 -#define SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_INCR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift 24 -#define SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_cpv_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_WRITE_INCR_HEADER_cpv_shift 28 -#define SDMA_PKT_WRITE_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) - -/*define for INIT_DW0 word*/ -/*define for init_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) - -/*define for INIT_DW1 word*/ -/*define for init_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) - -/*define for INCR_DW0 word*/ -/*define for incr_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) - -/*define for INCR_DW1 word*/ -/*define for incr_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 -#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_INDIRECT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 -#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 -#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) - -/*define for vmid field*/ -#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F -#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 -#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) - -/*define for priv field*/ -#define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 -#define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 -#define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) - -/*define for BASE_LO word*/ -/*define for ib_base_31_0 field*/ -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 -#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) - -/*define for BASE_HI word*/ -/*define for ib_base_63_32 field*/ -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 -#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) - -/*define for IB_SIZE word*/ -/*define for ib_size field*/ -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 -#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) - -/*define for CSA_ADDR_LO word*/ -/*define for csa_addr_31_0 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) - -/*define for CSA_ADDR_HI word*/ -/*define for csa_addr_63_32 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_SEMAPHORE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 -#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) - -/*define for write_one field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 -#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) - -/*define for signal field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 -#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) - -/*define for mailbox field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 -#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_MEM_INCR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_MEM_INCR_HEADER_op_offset 0 -#define SDMA_PKT_MEM_INCR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_MEM_INCR_HEADER_op_shift 0 -#define SDMA_PKT_MEM_INCR_HEADER_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_MEM_INCR_HEADER_sub_op_offset 0 -#define SDMA_PKT_MEM_INCR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_MEM_INCR_HEADER_sub_op_shift 8 -#define SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset 0 -#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift 24 -#define SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift) - -/*define for llc_policy field*/ -#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset 0 -#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask 0x00000001 -#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift 26 -#define SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_MEM_INCR_HEADER_cpv_offset 0 -#define SDMA_PKT_MEM_INCR_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_MEM_INCR_HEADER_cpv_shift 28 -#define SDMA_PKT_MEM_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_VM_INVALIDATION packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF -#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 -#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) - -/*define for gfx_eng_id field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 -#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) - -/*define for mm_eng_id field*/ -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 -#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) - -/*define for INVALIDATEREQ word*/ -/*define for invalidatereq field*/ -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 -#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) - -/*define for ADDRESSRANGELO word*/ -/*define for addressrangelo field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) - -/*define for ADDRESSRANGEHI word*/ -/*define for invalidateack field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) - -/*define for addressrangehi field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) - -/*define for reserved field*/ -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 -#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) - - -/* -** Definitions for SDMA_PKT_FENCE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_FENCE_HEADER_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_op_shift 0 -#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 -#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) - -/*define for mtype field*/ -#define SDMA_PKT_FENCE_HEADER_mtype_offset 0 -#define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 -#define SDMA_PKT_FENCE_HEADER_mtype_shift 16 -#define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) - -/*define for gcc field*/ -#define SDMA_PKT_FENCE_HEADER_gcc_offset 0 -#define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_gcc_shift 19 -#define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) - -/*define for sys field*/ -#define SDMA_PKT_FENCE_HEADER_sys_offset 0 -#define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_sys_shift 20 -#define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) - -/*define for snp field*/ -#define SDMA_PKT_FENCE_HEADER_snp_offset 0 -#define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_snp_shift 22 -#define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) - -/*define for gpa field*/ -#define SDMA_PKT_FENCE_HEADER_gpa_offset 0 -#define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_gpa_shift 23 -#define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 -#define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 -#define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) - -/*define for llc_policy field*/ -#define SDMA_PKT_FENCE_HEADER_llc_policy_offset 0 -#define SDMA_PKT_FENCE_HEADER_llc_policy_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_llc_policy_shift 26 -#define SDMA_PKT_FENCE_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_FENCE_HEADER_cpv_offset 0 -#define SDMA_PKT_FENCE_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_FENCE_HEADER_cpv_shift 28 -#define SDMA_PKT_FENCE_HEADER_CPV(x) (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_FENCE_DATA_data_offset 3 -#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_DATA_data_shift 0 -#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_SRBM_WRITE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) - -/*define for byte_en field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 -#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) - -/*define for ADDR word*/ -/*define for addr field*/ -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 -#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) - -/*define for apertureid field*/ -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF -#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 -#define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 -#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 -#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_PRE_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 -#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) - -/*define for dev_sel field*/ -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 -#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_COND_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 -#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_COND_EXE_HEADER_cache_policy_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_COND_EXE_HEADER_cache_policy_shift 24 -#define SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_COND_EXE_HEADER_cpv_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_COND_EXE_HEADER_cpv_shift 28 -#define SDMA_PKT_COND_EXE_HEADER_CPV(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) - -/*define for REFERENCE word*/ -/*define for reference field*/ -#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 -#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 -#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_CONSTANT_FILL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) - -/*define for sw field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift 24 -#define SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift 28 -#define SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift) - -/*define for fillsize field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 -#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DATA word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x3FFFFFFF -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 -#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_DATA_FILL_MULTI packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift 24 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift 28 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift) - -/*define for memlog_clr field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) - -/*define for BYTE_STRIDE word*/ -/*define for byte_stride field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) - -/*define for DMA_COUNT word*/ -/*define for dma_count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for BYTE_COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REGMEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift 20 -#define SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift 24 -#define SDMA_PKT_POLL_REGMEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift) - -/*define for hdp_flush field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 -#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) - -/*define for func field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 -#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) - -/*define for mem_poll field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 -#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) - -/*define for VALUE word*/ -/*define for value field*/ -#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 -#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 -#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) - -/*define for MASK word*/ -/*define for mask field*/ -#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 -#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 -#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) - -/*define for DW5 word*/ -/*define for interval field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF -#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 -#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) - -/*define for retry_count field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 -#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift 24 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift 28 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift) - -/*define for SRC_ADDR word*/ -/*define for addr_31_2 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) - -/*define for ea field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift 24 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift 28 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - -/*define for START_PAGE word*/ -/*define for addr_31_4 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) - -/*define for PAGE_NUM word*/ -/*define for page_num_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) - - -/* -** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift 24 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift 28 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift) - -/*define for mode field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) - -/*define for PATTERN word*/ -/*define for pattern field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) - -/*define for CMP0_ADDR_START_LO word*/ -/*define for cmp0_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) - -/*define for CMP0_ADDR_START_HI word*/ -/*define for cmp0_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) - -/*define for CMP0_ADDR_END_LO word*/ -/*define for cmp0_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset 4 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift) - -/*define for CMP0_ADDR_END_HI word*/ -/*define for cmp0_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset 5 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift) - -/*define for CMP1_ADDR_START_LO word*/ -/*define for cmp1_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) - -/*define for CMP1_ADDR_START_HI word*/ -/*define for cmp1_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) - -/*define for CMP1_ADDR_END_LO word*/ -/*define for cmp1_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) - -/*define for CMP1_ADDR_END_HI word*/ -/*define for cmp1_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) - -/*define for REC_ADDR_LO word*/ -/*define for rec_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) - -/*define for REC_ADDR_HI word*/ -/*define for rec_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) - -/*define for RESERVED word*/ -/*define for reserved field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) - - -/* -** Definitions for SDMA_PKT_ATOMIC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 -#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) - -/*define for loop field*/ -#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 -#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) - -/*define for tmz field*/ -#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 -#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) - -/*define for cache_policy field*/ -#define SDMA_PKT_ATOMIC_HEADER_cache_policy_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_cache_policy_mask 0x00000007 -#define SDMA_PKT_ATOMIC_HEADER_cache_policy_shift 20 -#define SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_ATOMIC_HEADER_cpv_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_cpv_shift 24 -#define SDMA_PKT_ATOMIC_HEADER_CPV(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift) - -/*define for atomic_op field*/ -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 -#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) - -/*define for SRC_DATA_LO word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) - -/*define for SRC_DATA_HI word*/ -/*define for src_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) - -/*define for CMP_DATA_LO word*/ -/*define for cmp_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) - -/*define for CMP_DATA_HI word*/ -/*define for cmp_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) - -/*define for LOOP_INTERVAL word*/ -/*define for loop_interval field*/ -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_SET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) - -/*define for INIT_DATA_LO word*/ -/*define for init_data_31_0 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) - -/*define for INIT_DATA_HI word*/ -/*define for init_data_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift 24 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift) - -/*define for llc_policy field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask 0x00000001 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift 26 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift 28 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) - -/*define for l2_policy field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask 0x00000003 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift 24 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift) - -/*define for llc_policy field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask 0x00000001 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift 26 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift) - -/*define for cpv field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask 0x00000001 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift 28 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_DUMMY_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_GPUVM_INV packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 -#define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF -#define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 -#define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 -#define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) - -/*define for PAYLOAD1 word*/ -/*define for per_vmid_inv_req field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) - -/*define for flush_type field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) - -/*define for l2_ptes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) - -/*define for l2_pde0 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) - -/*define for l2_pde1 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) - -/*define for l2_pde2 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) - -/*define for l1_ptes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) - -/*define for clr_protection_fault_status_addr field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) - -/*define for log_request field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) - -/*define for four_kilobytes field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 -#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) - -/*define for PAYLOAD2 word*/ -/*define for s field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) - -/*define for page_va_42_12 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 -#define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) - -/*define for PAYLOAD3 word*/ -/*define for page_va_47_43 field*/ -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 -#define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) - - -/* -** Definitions for SDMA_PKT_GCR_REQ packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 -#define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF -#define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 -#define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 -#define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) - -/*define for PAYLOAD1 word*/ -/*define for base_va_31_7 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 -#define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) - -/*define for PAYLOAD2 word*/ -/*define for base_va_47_32 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) - -/*define for gcr_control_15_0 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 -#define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) - -/*define for PAYLOAD3 word*/ -/*define for gcr_control_18_16 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) - -/*define for limit_va_31_7 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 -#define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) - -/*define for PAYLOAD4 word*/ -/*define for limit_va_47_32 field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF -#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) - -/*define for vmid field*/ -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F -#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 -#define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) - - -/* -** Definitions for SDMA_PKT_NOP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_NOP_HEADER_op_offset 0 -#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_op_shift 0 -#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 -#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 -#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) - -/*define for count field*/ -#define SDMA_PKT_NOP_HEADER_count_offset 0 -#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF -#define SDMA_PKT_NOP_HEADER_count_shift 16 -#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_NOP_DATA0_data0_offset 1 -#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_NOP_DATA0_data0_shift 0 -#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) - - -/* -** Definitions for SDMA_AQL_PKT_HEADER packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 -#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 -#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) - -/*define for cpv field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_cpv_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_cpv_mask 0x00000001 -#define SDMA_AQL_PKT_HEADER_HEADER_cpv_shift 28 -#define SDMA_AQL_PKT_HEADER_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift) - - -/* -** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) - -/*define for cpv field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift 28 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) - -/*define for RETURN_ADDR_LO word*/ -/*define for return_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) - -/*define for RETURN_ADDR_HI word*/ -/*define for return_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for dst_cache_policy field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) - -/*define for src_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_cache_policy field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for RESERVED_DW10 word*/ -/*define for reserved_dw10 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) - -/*define for RESERVED_DW11 word*/ -/*define for reserved_dw11 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) - -/*define for RESERVED_DW12 word*/ -/*define for reserved_dw12 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -/* -** Definitions for SDMA_AQL_PKT_BARRIER_OR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) - -/*define for cpv field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask 0x00000001 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift 28 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) - -/*define for DEPENDENT_ADDR_0_LO word*/ -/*define for dependent_addr_0_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) - -/*define for DEPENDENT_ADDR_0_HI word*/ -/*define for dependent_addr_0_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) - -/*define for DEPENDENT_ADDR_1_LO word*/ -/*define for dependent_addr_1_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) - -/*define for DEPENDENT_ADDR_1_HI word*/ -/*define for dependent_addr_1_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) - -/*define for DEPENDENT_ADDR_2_LO word*/ -/*define for dependent_addr_2_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) - -/*define for DEPENDENT_ADDR_2_HI word*/ -/*define for dependent_addr_2_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) - -/*define for DEPENDENT_ADDR_3_LO word*/ -/*define for dependent_addr_3_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) - -/*define for DEPENDENT_ADDR_3_HI word*/ -/*define for dependent_addr_3_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) - -/*define for DEPENDENT_ADDR_4_LO word*/ -/*define for dependent_addr_4_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) - -/*define for DEPENDENT_ADDR_4_HI word*/ -/*define for dependent_addr_4_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) - -/*define for CACHE_POLICY word*/ -/*define for cache_policy0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift) - -/*define for cache_policy1 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift 5 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift) - -/*define for cache_policy2 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift 10 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift) - -/*define for cache_policy3 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift 15 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift) - -/*define for cache_policy4 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift 20 -#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -#endif /* __SDMA_V6_0_0_PKT_OPEN_H_ */ diff --git a/tinygrad/extra/hip_gpu_driver/sienna_cichlid_ip_offset.h b/tinygrad/extra/hip_gpu_driver/sienna_cichlid_ip_offset.h deleted file mode 100644 index 05479047..00000000 --- a/tinygrad/extra/hip_gpu_driver/sienna_cichlid_ip_offset.h +++ /dev/null @@ -1,1166 +0,0 @@ -/* - * Copyright (C) 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sienna_cichlid_ip_offset_HEADER -#define _sienna_cichlid_ip_offset_HEADER - -#define MAX_INSTANCE 7 -#define MAX_SEGMENT 5 - - -struct IP_BASE_INSTANCE { - unsigned int segment[MAX_SEGMENT]; -}; - -struct IP_BASE { - struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; -} __maybe_unused; - - -static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, - { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, - { { 0x00017000, 0x02402000, 0, 0, 0 } }, - { { 0x00017200, 0x02402400, 0, 0, 0 } }, - { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, - { { 0x0001B200, 0x0242DC00, 0, 0, 0 } }, - { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } }; -static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } }, - { { 0x00054000, 0x02425C00, 0, 0, 0 } }, - { { 0x00094000, 0x02426000, 0, 0, 0 } }, - { { 0x000D4000, 0x02426400, 0, 0, 0 } }, - { { 0x00114000, 0x02426800, 0, 0, 0 } }, - { { 0x00154000, 0x02426C00, 0, 0, 0 } }, - { { 0x00194000, 0x02427000, 0, 0, 0 } } } }; -static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; -static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, - { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } }, - { { 0, 0, 0, 0, 0 } } } }; - - -#define ATHUB_BASE__INST0_SEG0 0x00000C00 -#define ATHUB_BASE__INST0_SEG1 0x02408C00 -#define ATHUB_BASE__INST0_SEG2 0 -#define ATHUB_BASE__INST0_SEG3 0 -#define ATHUB_BASE__INST0_SEG4 0 - -#define ATHUB_BASE__INST1_SEG0 0 -#define ATHUB_BASE__INST1_SEG1 0 -#define ATHUB_BASE__INST1_SEG2 0 -#define ATHUB_BASE__INST1_SEG3 0 -#define ATHUB_BASE__INST1_SEG4 0 - -#define ATHUB_BASE__INST2_SEG0 0 -#define ATHUB_BASE__INST2_SEG1 0 -#define ATHUB_BASE__INST2_SEG2 0 -#define ATHUB_BASE__INST2_SEG3 0 -#define ATHUB_BASE__INST2_SEG4 0 - -#define ATHUB_BASE__INST3_SEG0 0 -#define ATHUB_BASE__INST3_SEG1 0 -#define ATHUB_BASE__INST3_SEG2 0 -#define ATHUB_BASE__INST3_SEG3 0 -#define ATHUB_BASE__INST3_SEG4 0 - -#define ATHUB_BASE__INST4_SEG0 0 -#define ATHUB_BASE__INST4_SEG1 0 -#define ATHUB_BASE__INST4_SEG2 0 -#define ATHUB_BASE__INST4_SEG3 0 -#define ATHUB_BASE__INST4_SEG4 0 - -#define ATHUB_BASE__INST5_SEG0 0 -#define ATHUB_BASE__INST5_SEG1 0 -#define ATHUB_BASE__INST5_SEG2 0 -#define ATHUB_BASE__INST5_SEG3 0 -#define ATHUB_BASE__INST5_SEG4 0 - -#define ATHUB_BASE__INST6_SEG0 0 -#define ATHUB_BASE__INST6_SEG1 0 -#define ATHUB_BASE__INST6_SEG2 0 -#define ATHUB_BASE__INST6_SEG3 0 -#define ATHUB_BASE__INST6_SEG4 0 - -#define CLK_BASE__INST0_SEG0 0x00016C00 -#define CLK_BASE__INST0_SEG1 0x02401800 -#define CLK_BASE__INST0_SEG2 0 -#define CLK_BASE__INST0_SEG3 0 -#define CLK_BASE__INST0_SEG4 0 - -#define CLK_BASE__INST1_SEG0 0x00016E00 -#define CLK_BASE__INST1_SEG1 0x02401C00 -#define CLK_BASE__INST1_SEG2 0 -#define CLK_BASE__INST1_SEG3 0 -#define CLK_BASE__INST1_SEG4 0 - -#define CLK_BASE__INST2_SEG0 0x00017000 -#define CLK_BASE__INST2_SEG1 0x02402000 -#define CLK_BASE__INST2_SEG2 0 -#define CLK_BASE__INST2_SEG3 0 -#define CLK_BASE__INST2_SEG4 0 - -#define CLK_BASE__INST3_SEG0 0x00017200 -#define CLK_BASE__INST3_SEG1 0x02402400 -#define CLK_BASE__INST3_SEG2 0 -#define CLK_BASE__INST3_SEG3 0 -#define CLK_BASE__INST3_SEG4 0 - -#define CLK_BASE__INST4_SEG0 0x0001B000 -#define CLK_BASE__INST4_SEG1 0x0242D800 -#define CLK_BASE__INST4_SEG2 0 -#define CLK_BASE__INST4_SEG3 0 -#define CLK_BASE__INST4_SEG4 0 - -#define CLK_BASE__INST5_SEG0 0x0001B200 -#define CLK_BASE__INST5_SEG1 0x0242DC00 -#define CLK_BASE__INST5_SEG2 0 -#define CLK_BASE__INST5_SEG3 0 -#define CLK_BASE__INST5_SEG4 0 - -#define CLK_BASE__INST6_SEG0 0x0001B400 -#define CLK_BASE__INST6_SEG1 0x0242E000 -#define CLK_BASE__INST6_SEG2 0 -#define CLK_BASE__INST6_SEG3 0 -#define CLK_BASE__INST6_SEG4 0 - -#define DF_BASE__INST0_SEG0 0x00007000 -#define DF_BASE__INST0_SEG1 0x0240B800 -#define DF_BASE__INST0_SEG2 0 -#define DF_BASE__INST0_SEG3 0 -#define DF_BASE__INST0_SEG4 0 - -#define DF_BASE__INST1_SEG0 0 -#define DF_BASE__INST1_SEG1 0 -#define DF_BASE__INST1_SEG2 0 -#define DF_BASE__INST1_SEG3 0 -#define DF_BASE__INST1_SEG4 0 - -#define DF_BASE__INST2_SEG0 0 -#define DF_BASE__INST2_SEG1 0 -#define DF_BASE__INST2_SEG2 0 -#define DF_BASE__INST2_SEG3 0 -#define DF_BASE__INST2_SEG4 0 - -#define DF_BASE__INST3_SEG0 0 -#define DF_BASE__INST3_SEG1 0 -#define DF_BASE__INST3_SEG2 0 -#define DF_BASE__INST3_SEG3 0 -#define DF_BASE__INST3_SEG4 0 - -#define DF_BASE__INST4_SEG0 0 -#define DF_BASE__INST4_SEG1 0 -#define DF_BASE__INST4_SEG2 0 -#define DF_BASE__INST4_SEG3 0 -#define DF_BASE__INST4_SEG4 0 - -#define DF_BASE__INST5_SEG0 0 -#define DF_BASE__INST5_SEG1 0 -#define DF_BASE__INST5_SEG2 0 -#define DF_BASE__INST5_SEG3 0 -#define DF_BASE__INST5_SEG4 0 - -#define DF_BASE__INST6_SEG0 0 -#define DF_BASE__INST6_SEG1 0 -#define DF_BASE__INST6_SEG2 0 -#define DF_BASE__INST6_SEG3 0 -#define DF_BASE__INST6_SEG4 0 - -#define DIO_BASE__INST0_SEG0 0x02404000 -#define DIO_BASE__INST0_SEG1 0 -#define DIO_BASE__INST0_SEG2 0 -#define DIO_BASE__INST0_SEG3 0 -#define DIO_BASE__INST0_SEG4 0 - -#define DIO_BASE__INST1_SEG0 0 -#define DIO_BASE__INST1_SEG1 0 -#define DIO_BASE__INST1_SEG2 0 -#define DIO_BASE__INST1_SEG3 0 -#define DIO_BASE__INST1_SEG4 0 - -#define DIO_BASE__INST2_SEG0 0 -#define DIO_BASE__INST2_SEG1 0 -#define DIO_BASE__INST2_SEG2 0 -#define DIO_BASE__INST2_SEG3 0 -#define DIO_BASE__INST2_SEG4 0 - -#define DIO_BASE__INST3_SEG0 0 -#define DIO_BASE__INST3_SEG1 0 -#define DIO_BASE__INST3_SEG2 0 -#define DIO_BASE__INST3_SEG3 0 -#define DIO_BASE__INST3_SEG4 0 - -#define DIO_BASE__INST4_SEG0 0 -#define DIO_BASE__INST4_SEG1 0 -#define DIO_BASE__INST4_SEG2 0 -#define DIO_BASE__INST4_SEG3 0 -#define DIO_BASE__INST4_SEG4 0 - -#define DIO_BASE__INST5_SEG0 0 -#define DIO_BASE__INST5_SEG1 0 -#define DIO_BASE__INST5_SEG2 0 -#define DIO_BASE__INST5_SEG3 0 -#define DIO_BASE__INST5_SEG4 0 - -#define DIO_BASE__INST6_SEG0 0 -#define DIO_BASE__INST6_SEG1 0 -#define DIO_BASE__INST6_SEG2 0 -#define DIO_BASE__INST6_SEG3 0 -#define DIO_BASE__INST6_SEG4 0 - -#define DCN_BASE__INST0_SEG0 0x00000012 -#define DCN_BASE__INST0_SEG1 0x000000C0 -#define DCN_BASE__INST0_SEG2 0x000034C0 -#define DCN_BASE__INST0_SEG3 0x00009000 -#define DCN_BASE__INST0_SEG4 0x02403C00 - -#define DCN_BASE__INST1_SEG0 0 -#define DCN_BASE__INST1_SEG1 0 -#define DCN_BASE__INST1_SEG2 0 -#define DCN_BASE__INST1_SEG3 0 -#define DCN_BASE__INST1_SEG4 0 - -#define DCN_BASE__INST2_SEG0 0 -#define DCN_BASE__INST2_SEG1 0 -#define DCN_BASE__INST2_SEG2 0 -#define DCN_BASE__INST2_SEG3 0 -#define DCN_BASE__INST2_SEG4 0 - -#define DCN_BASE__INST3_SEG0 0 -#define DCN_BASE__INST3_SEG1 0 -#define DCN_BASE__INST3_SEG2 0 -#define DCN_BASE__INST3_SEG3 0 -#define DCN_BASE__INST3_SEG4 0 - -#define DCN_BASE__INST4_SEG0 0 -#define DCN_BASE__INST4_SEG1 0 -#define DCN_BASE__INST4_SEG2 0 -#define DCN_BASE__INST4_SEG3 0 -#define DCN_BASE__INST4_SEG4 0 - -#define DCN_BASE__INST5_SEG0 0 -#define DCN_BASE__INST5_SEG1 0 -#define DCN_BASE__INST5_SEG2 0 -#define DCN_BASE__INST5_SEG3 0 -#define DCN_BASE__INST5_SEG4 0 - -#define DCN_BASE__INST6_SEG0 0 -#define DCN_BASE__INST6_SEG1 0 -#define DCN_BASE__INST6_SEG2 0 -#define DCN_BASE__INST6_SEG3 0 -#define DCN_BASE__INST6_SEG4 0 - -#define DPCS_BASE__INST0_SEG0 0x00000012 -#define DPCS_BASE__INST0_SEG1 0x000000C0 -#define DPCS_BASE__INST0_SEG2 0x000034C0 -#define DPCS_BASE__INST0_SEG3 0x00009000 -#define DPCS_BASE__INST0_SEG4 0x02403C00 - -#define DPCS_BASE__INST1_SEG0 0 -#define DPCS_BASE__INST1_SEG1 0 -#define DPCS_BASE__INST1_SEG2 0 -#define DPCS_BASE__INST1_SEG3 0 -#define DPCS_BASE__INST1_SEG4 0 - -#define DPCS_BASE__INST2_SEG0 0 -#define DPCS_BASE__INST2_SEG1 0 -#define DPCS_BASE__INST2_SEG2 0 -#define DPCS_BASE__INST2_SEG3 0 -#define DPCS_BASE__INST2_SEG4 0 - -#define DPCS_BASE__INST3_SEG0 0 -#define DPCS_BASE__INST3_SEG1 0 -#define DPCS_BASE__INST3_SEG2 0 -#define DPCS_BASE__INST3_SEG3 0 -#define DPCS_BASE__INST3_SEG4 0 - -#define DPCS_BASE__INST4_SEG0 0 -#define DPCS_BASE__INST4_SEG1 0 -#define DPCS_BASE__INST4_SEG2 0 -#define DPCS_BASE__INST4_SEG3 0 -#define DPCS_BASE__INST4_SEG4 0 - -#define DPCS_BASE__INST5_SEG0 0 -#define DPCS_BASE__INST5_SEG1 0 -#define DPCS_BASE__INST5_SEG2 0 -#define DPCS_BASE__INST5_SEG3 0 -#define DPCS_BASE__INST5_SEG4 0 - -#define DPCS_BASE__INST6_SEG0 0 -#define DPCS_BASE__INST6_SEG1 0 -#define DPCS_BASE__INST6_SEG2 0 -#define DPCS_BASE__INST6_SEG3 0 -#define DPCS_BASE__INST6_SEG4 0 - -#define FUSE_BASE__INST0_SEG0 0x00017400 -#define FUSE_BASE__INST0_SEG1 0x02401400 -#define FUSE_BASE__INST0_SEG2 0 -#define FUSE_BASE__INST0_SEG3 0 -#define FUSE_BASE__INST0_SEG4 0 - -#define FUSE_BASE__INST1_SEG0 0 -#define FUSE_BASE__INST1_SEG1 0 -#define FUSE_BASE__INST1_SEG2 0 -#define FUSE_BASE__INST1_SEG3 0 -#define FUSE_BASE__INST1_SEG4 0 - -#define FUSE_BASE__INST2_SEG0 0 -#define FUSE_BASE__INST2_SEG1 0 -#define FUSE_BASE__INST2_SEG2 0 -#define FUSE_BASE__INST2_SEG3 0 -#define FUSE_BASE__INST2_SEG4 0 - -#define FUSE_BASE__INST3_SEG0 0 -#define FUSE_BASE__INST3_SEG1 0 -#define FUSE_BASE__INST3_SEG2 0 -#define FUSE_BASE__INST3_SEG3 0 -#define FUSE_BASE__INST3_SEG4 0 - -#define FUSE_BASE__INST4_SEG0 0 -#define FUSE_BASE__INST4_SEG1 0 -#define FUSE_BASE__INST4_SEG2 0 -#define FUSE_BASE__INST4_SEG3 0 -#define FUSE_BASE__INST4_SEG4 0 - -#define FUSE_BASE__INST5_SEG0 0 -#define FUSE_BASE__INST5_SEG1 0 -#define FUSE_BASE__INST5_SEG2 0 -#define FUSE_BASE__INST5_SEG3 0 -#define FUSE_BASE__INST5_SEG4 0 - -#define FUSE_BASE__INST6_SEG0 0 -#define FUSE_BASE__INST6_SEG1 0 -#define FUSE_BASE__INST6_SEG2 0 -#define FUSE_BASE__INST6_SEG3 0 -#define FUSE_BASE__INST6_SEG4 0 - -#define GC_BASE__INST0_SEG0 0x00001260 -#define GC_BASE__INST0_SEG1 0x0000A000 -#define GC_BASE__INST0_SEG2 0x0001C000 -#define GC_BASE__INST0_SEG3 0x02402C00 -#define GC_BASE__INST0_SEG4 0 - -#define GC_BASE__INST1_SEG0 0 -#define GC_BASE__INST1_SEG1 0 -#define GC_BASE__INST1_SEG2 0 -#define GC_BASE__INST1_SEG3 0 -#define GC_BASE__INST1_SEG4 0 - -#define GC_BASE__INST2_SEG0 0 -#define GC_BASE__INST2_SEG1 0 -#define GC_BASE__INST2_SEG2 0 -#define GC_BASE__INST2_SEG3 0 -#define GC_BASE__INST2_SEG4 0 - -#define GC_BASE__INST3_SEG0 0 -#define GC_BASE__INST3_SEG1 0 -#define GC_BASE__INST3_SEG2 0 -#define GC_BASE__INST3_SEG3 0 -#define GC_BASE__INST3_SEG4 0 - -#define GC_BASE__INST4_SEG0 0 -#define GC_BASE__INST4_SEG1 0 -#define GC_BASE__INST4_SEG2 0 -#define GC_BASE__INST4_SEG3 0 -#define GC_BASE__INST4_SEG4 0 - -#define GC_BASE__INST5_SEG0 0 -#define GC_BASE__INST5_SEG1 0 -#define GC_BASE__INST5_SEG2 0 -#define GC_BASE__INST5_SEG3 0 -#define GC_BASE__INST5_SEG4 0 - -#define GC_BASE__INST6_SEG0 0 -#define GC_BASE__INST6_SEG1 0 -#define GC_BASE__INST6_SEG2 0 -#define GC_BASE__INST6_SEG3 0 -#define GC_BASE__INST6_SEG4 0 - -#define HDA_BASE__INST0_SEG0 0x004C0000 -#define HDA_BASE__INST0_SEG1 0x02404800 -#define HDA_BASE__INST0_SEG2 0 -#define HDA_BASE__INST0_SEG3 0 -#define HDA_BASE__INST0_SEG4 0 - -#define HDA_BASE__INST1_SEG0 0 -#define HDA_BASE__INST1_SEG1 0 -#define HDA_BASE__INST1_SEG2 0 -#define HDA_BASE__INST1_SEG3 0 -#define HDA_BASE__INST1_SEG4 0 - -#define HDA_BASE__INST2_SEG0 0 -#define HDA_BASE__INST2_SEG1 0 -#define HDA_BASE__INST2_SEG2 0 -#define HDA_BASE__INST2_SEG3 0 -#define HDA_BASE__INST2_SEG4 0 - -#define HDA_BASE__INST3_SEG0 0 -#define HDA_BASE__INST3_SEG1 0 -#define HDA_BASE__INST3_SEG2 0 -#define HDA_BASE__INST3_SEG3 0 -#define HDA_BASE__INST3_SEG4 0 - -#define HDA_BASE__INST4_SEG0 0 -#define HDA_BASE__INST4_SEG1 0 -#define HDA_BASE__INST4_SEG2 0 -#define HDA_BASE__INST4_SEG3 0 -#define HDA_BASE__INST4_SEG4 0 - -#define HDA_BASE__INST5_SEG0 0 -#define HDA_BASE__INST5_SEG1 0 -#define HDA_BASE__INST5_SEG2 0 -#define HDA_BASE__INST5_SEG3 0 -#define HDA_BASE__INST5_SEG4 0 - -#define HDA_BASE__INST6_SEG0 0 -#define HDA_BASE__INST6_SEG1 0 -#define HDA_BASE__INST6_SEG2 0 -#define HDA_BASE__INST6_SEG3 0 -#define HDA_BASE__INST6_SEG4 0 - -#define HDP_BASE__INST0_SEG0 0x00000F20 -#define HDP_BASE__INST0_SEG1 0x0240A400 -#define HDP_BASE__INST0_SEG2 0 -#define HDP_BASE__INST0_SEG3 0 -#define HDP_BASE__INST0_SEG4 0 - -#define HDP_BASE__INST1_SEG0 0 -#define HDP_BASE__INST1_SEG1 0 -#define HDP_BASE__INST1_SEG2 0 -#define HDP_BASE__INST1_SEG3 0 -#define HDP_BASE__INST1_SEG4 0 - -#define HDP_BASE__INST2_SEG0 0 -#define HDP_BASE__INST2_SEG1 0 -#define HDP_BASE__INST2_SEG2 0 -#define HDP_BASE__INST2_SEG3 0 -#define HDP_BASE__INST2_SEG4 0 - -#define HDP_BASE__INST3_SEG0 0 -#define HDP_BASE__INST3_SEG1 0 -#define HDP_BASE__INST3_SEG2 0 -#define HDP_BASE__INST3_SEG3 0 -#define HDP_BASE__INST3_SEG4 0 - -#define HDP_BASE__INST4_SEG0 0 -#define HDP_BASE__INST4_SEG1 0 -#define HDP_BASE__INST4_SEG2 0 -#define HDP_BASE__INST4_SEG3 0 -#define HDP_BASE__INST4_SEG4 0 - -#define HDP_BASE__INST5_SEG0 0 -#define HDP_BASE__INST5_SEG1 0 -#define HDP_BASE__INST5_SEG2 0 -#define HDP_BASE__INST5_SEG3 0 -#define HDP_BASE__INST5_SEG4 0 - -#define HDP_BASE__INST6_SEG0 0 -#define HDP_BASE__INST6_SEG1 0 -#define HDP_BASE__INST6_SEG2 0 -#define HDP_BASE__INST6_SEG3 0 -#define HDP_BASE__INST6_SEG4 0 - -#define MMHUB_BASE__INST0_SEG0 0x0001A000 -#define MMHUB_BASE__INST0_SEG1 0x02408800 -#define MMHUB_BASE__INST0_SEG2 0 -#define MMHUB_BASE__INST0_SEG3 0 -#define MMHUB_BASE__INST0_SEG4 0 - -#define MMHUB_BASE__INST1_SEG0 0 -#define MMHUB_BASE__INST1_SEG1 0 -#define MMHUB_BASE__INST1_SEG2 0 -#define MMHUB_BASE__INST1_SEG3 0 -#define MMHUB_BASE__INST1_SEG4 0 - -#define MMHUB_BASE__INST2_SEG0 0 -#define MMHUB_BASE__INST2_SEG1 0 -#define MMHUB_BASE__INST2_SEG2 0 -#define MMHUB_BASE__INST2_SEG3 0 -#define MMHUB_BASE__INST2_SEG4 0 - -#define MMHUB_BASE__INST3_SEG0 0 -#define MMHUB_BASE__INST3_SEG1 0 -#define MMHUB_BASE__INST3_SEG2 0 -#define MMHUB_BASE__INST3_SEG3 0 -#define MMHUB_BASE__INST3_SEG4 0 - -#define MMHUB_BASE__INST4_SEG0 0 -#define MMHUB_BASE__INST4_SEG1 0 -#define MMHUB_BASE__INST4_SEG2 0 -#define MMHUB_BASE__INST4_SEG3 0 -#define MMHUB_BASE__INST4_SEG4 0 - -#define MMHUB_BASE__INST5_SEG0 0 -#define MMHUB_BASE__INST5_SEG1 0 -#define MMHUB_BASE__INST5_SEG2 0 -#define MMHUB_BASE__INST5_SEG3 0 -#define MMHUB_BASE__INST5_SEG4 0 - -#define MMHUB_BASE__INST6_SEG0 0 -#define MMHUB_BASE__INST6_SEG1 0 -#define MMHUB_BASE__INST6_SEG2 0 -#define MMHUB_BASE__INST6_SEG3 0 -#define MMHUB_BASE__INST6_SEG4 0 - -#define MP0_BASE__INST0_SEG0 0x00016000 -#define MP0_BASE__INST0_SEG1 0x00DC0000 -#define MP0_BASE__INST0_SEG2 0x00E00000 -#define MP0_BASE__INST0_SEG3 0x00E40000 -#define MP0_BASE__INST0_SEG4 0x0243FC00 - -#define MP0_BASE__INST1_SEG0 0 -#define MP0_BASE__INST1_SEG1 0 -#define MP0_BASE__INST1_SEG2 0 -#define MP0_BASE__INST1_SEG3 0 -#define MP0_BASE__INST1_SEG4 0 - -#define MP0_BASE__INST2_SEG0 0 -#define MP0_BASE__INST2_SEG1 0 -#define MP0_BASE__INST2_SEG2 0 -#define MP0_BASE__INST2_SEG3 0 -#define MP0_BASE__INST2_SEG4 0 - -#define MP0_BASE__INST3_SEG0 0 -#define MP0_BASE__INST3_SEG1 0 -#define MP0_BASE__INST3_SEG2 0 -#define MP0_BASE__INST3_SEG3 0 -#define MP0_BASE__INST3_SEG4 0 - -#define MP0_BASE__INST4_SEG0 0 -#define MP0_BASE__INST4_SEG1 0 -#define MP0_BASE__INST4_SEG2 0 -#define MP0_BASE__INST4_SEG3 0 -#define MP0_BASE__INST4_SEG4 0 - -#define MP0_BASE__INST5_SEG0 0 -#define MP0_BASE__INST5_SEG1 0 -#define MP0_BASE__INST5_SEG2 0 -#define MP0_BASE__INST5_SEG3 0 -#define MP0_BASE__INST5_SEG4 0 - -#define MP0_BASE__INST6_SEG0 0 -#define MP0_BASE__INST6_SEG1 0 -#define MP0_BASE__INST6_SEG2 0 -#define MP0_BASE__INST6_SEG3 0 -#define MP0_BASE__INST6_SEG4 0 - -#define MP1_BASE__INST0_SEG0 0x00016000 -#define MP1_BASE__INST0_SEG1 0x00DC0000 -#define MP1_BASE__INST0_SEG2 0x00E00000 -#define MP1_BASE__INST0_SEG3 0x00E40000 -#define MP1_BASE__INST0_SEG4 0x0243FC00 - -#define MP1_BASE__INST1_SEG0 0 -#define MP1_BASE__INST1_SEG1 0 -#define MP1_BASE__INST1_SEG2 0 -#define MP1_BASE__INST1_SEG3 0 -#define MP1_BASE__INST1_SEG4 0 - -#define MP1_BASE__INST2_SEG0 0 -#define MP1_BASE__INST2_SEG1 0 -#define MP1_BASE__INST2_SEG2 0 -#define MP1_BASE__INST2_SEG3 0 -#define MP1_BASE__INST2_SEG4 0 - -#define MP1_BASE__INST3_SEG0 0 -#define MP1_BASE__INST3_SEG1 0 -#define MP1_BASE__INST3_SEG2 0 -#define MP1_BASE__INST3_SEG3 0 -#define MP1_BASE__INST3_SEG4 0 - -#define MP1_BASE__INST4_SEG0 0 -#define MP1_BASE__INST4_SEG1 0 -#define MP1_BASE__INST4_SEG2 0 -#define MP1_BASE__INST4_SEG3 0 -#define MP1_BASE__INST4_SEG4 0 - -#define MP1_BASE__INST5_SEG0 0 -#define MP1_BASE__INST5_SEG1 0 -#define MP1_BASE__INST5_SEG2 0 -#define MP1_BASE__INST5_SEG3 0 -#define MP1_BASE__INST5_SEG4 0 - -#define MP1_BASE__INST6_SEG0 0 -#define MP1_BASE__INST6_SEG1 0 -#define MP1_BASE__INST6_SEG2 0 -#define MP1_BASE__INST6_SEG3 0 -#define MP1_BASE__INST6_SEG4 0 - -#define NBIO_BASE__INST0_SEG0 0x00000000 -#define NBIO_BASE__INST0_SEG1 0x00000014 -#define NBIO_BASE__INST0_SEG2 0x00000D20 -#define NBIO_BASE__INST0_SEG3 0x00010400 -#define NBIO_BASE__INST0_SEG4 0x0241B000 - -#define NBIO_BASE__INST1_SEG0 0 -#define NBIO_BASE__INST1_SEG1 0 -#define NBIO_BASE__INST1_SEG2 0 -#define NBIO_BASE__INST1_SEG3 0 -#define NBIO_BASE__INST1_SEG4 0 - -#define NBIO_BASE__INST2_SEG0 0 -#define NBIO_BASE__INST2_SEG1 0 -#define NBIO_BASE__INST2_SEG2 0 -#define NBIO_BASE__INST2_SEG3 0 -#define NBIO_BASE__INST2_SEG4 0 - -#define NBIO_BASE__INST3_SEG0 0 -#define NBIO_BASE__INST3_SEG1 0 -#define NBIO_BASE__INST3_SEG2 0 -#define NBIO_BASE__INST3_SEG3 0 -#define NBIO_BASE__INST3_SEG4 0 - -#define NBIO_BASE__INST4_SEG0 0 -#define NBIO_BASE__INST4_SEG1 0 -#define NBIO_BASE__INST4_SEG2 0 -#define NBIO_BASE__INST4_SEG3 0 -#define NBIO_BASE__INST4_SEG4 0 - -#define NBIO_BASE__INST5_SEG0 0 -#define NBIO_BASE__INST5_SEG1 0 -#define NBIO_BASE__INST5_SEG2 0 -#define NBIO_BASE__INST5_SEG3 0 -#define NBIO_BASE__INST5_SEG4 0 - -#define NBIO_BASE__INST6_SEG0 0 -#define NBIO_BASE__INST6_SEG1 0 -#define NBIO_BASE__INST6_SEG2 0 -#define NBIO_BASE__INST6_SEG3 0 -#define NBIO_BASE__INST6_SEG4 0 - -#define OSSSYS_BASE__INST0_SEG0 0x000010A0 -#define OSSSYS_BASE__INST0_SEG1 0x0240A000 -#define OSSSYS_BASE__INST0_SEG2 0 -#define OSSSYS_BASE__INST0_SEG3 0 -#define OSSSYS_BASE__INST0_SEG4 0 - -#define OSSSYS_BASE__INST1_SEG0 0 -#define OSSSYS_BASE__INST1_SEG1 0 -#define OSSSYS_BASE__INST1_SEG2 0 -#define OSSSYS_BASE__INST1_SEG3 0 -#define OSSSYS_BASE__INST1_SEG4 0 - -#define OSSSYS_BASE__INST2_SEG0 0 -#define OSSSYS_BASE__INST2_SEG1 0 -#define OSSSYS_BASE__INST2_SEG2 0 -#define OSSSYS_BASE__INST2_SEG3 0 -#define OSSSYS_BASE__INST2_SEG4 0 - -#define OSSSYS_BASE__INST3_SEG0 0 -#define OSSSYS_BASE__INST3_SEG1 0 -#define OSSSYS_BASE__INST3_SEG2 0 -#define OSSSYS_BASE__INST3_SEG3 0 -#define OSSSYS_BASE__INST3_SEG4 0 - -#define OSSSYS_BASE__INST4_SEG0 0 -#define OSSSYS_BASE__INST4_SEG1 0 -#define OSSSYS_BASE__INST4_SEG2 0 -#define OSSSYS_BASE__INST4_SEG3 0 -#define OSSSYS_BASE__INST4_SEG4 0 - -#define OSSSYS_BASE__INST5_SEG0 0 -#define OSSSYS_BASE__INST5_SEG1 0 -#define OSSSYS_BASE__INST5_SEG2 0 -#define OSSSYS_BASE__INST5_SEG3 0 -#define OSSSYS_BASE__INST5_SEG4 0 - -#define OSSSYS_BASE__INST6_SEG0 0 -#define OSSSYS_BASE__INST6_SEG1 0 -#define OSSSYS_BASE__INST6_SEG2 0 -#define OSSSYS_BASE__INST6_SEG3 0 -#define OSSSYS_BASE__INST6_SEG4 0 - -#define PCIE0_BASE__INST0_SEG0 0x00000000 -#define PCIE0_BASE__INST0_SEG1 0x00000014 -#define PCIE0_BASE__INST0_SEG2 0x00000D20 -#define PCIE0_BASE__INST0_SEG3 0x00010400 -#define PCIE0_BASE__INST0_SEG4 0x0241B000 - -#define PCIE0_BASE__INST1_SEG0 0 -#define PCIE0_BASE__INST1_SEG1 0 -#define PCIE0_BASE__INST1_SEG2 0 -#define PCIE0_BASE__INST1_SEG3 0 -#define PCIE0_BASE__INST1_SEG4 0 - -#define PCIE0_BASE__INST2_SEG0 0 -#define PCIE0_BASE__INST2_SEG1 0 -#define PCIE0_BASE__INST2_SEG2 0 -#define PCIE0_BASE__INST2_SEG3 0 -#define PCIE0_BASE__INST2_SEG4 0 - -#define PCIE0_BASE__INST3_SEG0 0 -#define PCIE0_BASE__INST3_SEG1 0 -#define PCIE0_BASE__INST3_SEG2 0 -#define PCIE0_BASE__INST3_SEG3 0 -#define PCIE0_BASE__INST3_SEG4 0 - -#define PCIE0_BASE__INST4_SEG0 0 -#define PCIE0_BASE__INST4_SEG1 0 -#define PCIE0_BASE__INST4_SEG2 0 -#define PCIE0_BASE__INST4_SEG3 0 -#define PCIE0_BASE__INST4_SEG4 0 - -#define PCIE0_BASE__INST5_SEG0 0 -#define PCIE0_BASE__INST5_SEG1 0 -#define PCIE0_BASE__INST5_SEG2 0 -#define PCIE0_BASE__INST5_SEG3 0 -#define PCIE0_BASE__INST5_SEG4 0 - -#define PCIE0_BASE__INST6_SEG0 0 -#define PCIE0_BASE__INST6_SEG1 0 -#define PCIE0_BASE__INST6_SEG2 0 -#define PCIE0_BASE__INST6_SEG3 0 -#define PCIE0_BASE__INST6_SEG4 0 - -#define SDMA0_BASE__INST0_SEG0 0x00001260 -#define SDMA0_BASE__INST0_SEG1 0x0000A000 -#define SDMA0_BASE__INST0_SEG2 0x0001C000 -#define SDMA0_BASE__INST0_SEG3 0x02402C00 -#define SDMA0_BASE__INST0_SEG4 0 - -#define SDMA0_BASE__INST1_SEG0 0 -#define SDMA0_BASE__INST1_SEG1 0 -#define SDMA0_BASE__INST1_SEG2 0 -#define SDMA0_BASE__INST1_SEG3 0 -#define SDMA0_BASE__INST1_SEG4 0 - -#define SDMA0_BASE__INST2_SEG0 0 -#define SDMA0_BASE__INST2_SEG1 0 -#define SDMA0_BASE__INST2_SEG2 0 -#define SDMA0_BASE__INST2_SEG3 0 -#define SDMA0_BASE__INST2_SEG4 0 - -#define SDMA0_BASE__INST3_SEG0 0 -#define SDMA0_BASE__INST3_SEG1 0 -#define SDMA0_BASE__INST3_SEG2 0 -#define SDMA0_BASE__INST3_SEG3 0 -#define SDMA0_BASE__INST3_SEG4 0 - -#define SDMA0_BASE__INST4_SEG0 0 -#define SDMA0_BASE__INST4_SEG1 0 -#define SDMA0_BASE__INST4_SEG2 0 -#define SDMA0_BASE__INST4_SEG3 0 -#define SDMA0_BASE__INST4_SEG4 0 - -#define SDMA0_BASE__INST5_SEG0 0 -#define SDMA0_BASE__INST5_SEG1 0 -#define SDMA0_BASE__INST5_SEG2 0 -#define SDMA0_BASE__INST5_SEG3 0 -#define SDMA0_BASE__INST5_SEG4 0 - -#define SDMA0_BASE__INST6_SEG0 0 -#define SDMA0_BASE__INST6_SEG1 0 -#define SDMA0_BASE__INST6_SEG2 0 -#define SDMA0_BASE__INST6_SEG3 0 -#define SDMA0_BASE__INST6_SEG4 0 - -#define SDMA1_BASE__INST0_SEG0 0x00001260 -#define SDMA1_BASE__INST0_SEG1 0x0000A000 -#define SDMA1_BASE__INST0_SEG2 0x0001C000 -#define SDMA1_BASE__INST0_SEG3 0x02402C00 -#define SDMA1_BASE__INST0_SEG4 0 - -#define SDMA1_BASE__INST1_SEG0 0 -#define SDMA1_BASE__INST1_SEG1 0 -#define SDMA1_BASE__INST1_SEG2 0 -#define SDMA1_BASE__INST1_SEG3 0 -#define SDMA1_BASE__INST1_SEG4 0 - -#define SDMA1_BASE__INST2_SEG0 0 -#define SDMA1_BASE__INST2_SEG1 0 -#define SDMA1_BASE__INST2_SEG2 0 -#define SDMA1_BASE__INST2_SEG3 0 -#define SDMA1_BASE__INST2_SEG4 0 - -#define SDMA1_BASE__INST3_SEG0 0 -#define SDMA1_BASE__INST3_SEG1 0 -#define SDMA1_BASE__INST3_SEG2 0 -#define SDMA1_BASE__INST3_SEG3 0 -#define SDMA1_BASE__INST3_SEG4 0 - -#define SDMA1_BASE__INST4_SEG0 0 -#define SDMA1_BASE__INST4_SEG1 0 -#define SDMA1_BASE__INST4_SEG2 0 -#define SDMA1_BASE__INST4_SEG3 0 -#define SDMA1_BASE__INST4_SEG4 0 - -#define SDMA1_BASE__INST5_SEG0 0 -#define SDMA1_BASE__INST5_SEG1 0 -#define SDMA1_BASE__INST5_SEG2 0 -#define SDMA1_BASE__INST5_SEG3 0 -#define SDMA1_BASE__INST5_SEG4 0 - -#define SDMA1_BASE__INST6_SEG0 0 -#define SDMA1_BASE__INST6_SEG1 0 -#define SDMA1_BASE__INST6_SEG2 0 -#define SDMA1_BASE__INST6_SEG3 0 -#define SDMA1_BASE__INST6_SEG4 0 - -#define SMUIO_BASE__INST0_SEG0 0x00016800 -#define SMUIO_BASE__INST0_SEG1 0x00016A00 -#define SMUIO_BASE__INST0_SEG2 0x00440000 -#define SMUIO_BASE__INST0_SEG3 0x02401000 -#define SMUIO_BASE__INST0_SEG4 0 - -#define SMUIO_BASE__INST1_SEG0 0 -#define SMUIO_BASE__INST1_SEG1 0 -#define SMUIO_BASE__INST1_SEG2 0 -#define SMUIO_BASE__INST1_SEG3 0 -#define SMUIO_BASE__INST1_SEG4 0 - -#define SMUIO_BASE__INST2_SEG0 0 -#define SMUIO_BASE__INST2_SEG1 0 -#define SMUIO_BASE__INST2_SEG2 0 -#define SMUIO_BASE__INST2_SEG3 0 -#define SMUIO_BASE__INST2_SEG4 0 - -#define SMUIO_BASE__INST3_SEG0 0 -#define SMUIO_BASE__INST3_SEG1 0 -#define SMUIO_BASE__INST3_SEG2 0 -#define SMUIO_BASE__INST3_SEG3 0 -#define SMUIO_BASE__INST3_SEG4 0 - -#define SMUIO_BASE__INST4_SEG0 0 -#define SMUIO_BASE__INST4_SEG1 0 -#define SMUIO_BASE__INST4_SEG2 0 -#define SMUIO_BASE__INST4_SEG3 0 -#define SMUIO_BASE__INST4_SEG4 0 - -#define SMUIO_BASE__INST5_SEG0 0 -#define SMUIO_BASE__INST5_SEG1 0 -#define SMUIO_BASE__INST5_SEG2 0 -#define SMUIO_BASE__INST5_SEG3 0 -#define SMUIO_BASE__INST5_SEG4 0 - -#define SMUIO_BASE__INST6_SEG0 0 -#define SMUIO_BASE__INST6_SEG1 0 -#define SMUIO_BASE__INST6_SEG2 0 -#define SMUIO_BASE__INST6_SEG3 0 -#define SMUIO_BASE__INST6_SEG4 0 - -#define THM_BASE__INST0_SEG0 0x00016600 -#define THM_BASE__INST0_SEG1 0x02400C00 -#define THM_BASE__INST0_SEG2 0 -#define THM_BASE__INST0_SEG3 0 -#define THM_BASE__INST0_SEG4 0 - -#define THM_BASE__INST1_SEG0 0 -#define THM_BASE__INST1_SEG1 0 -#define THM_BASE__INST1_SEG2 0 -#define THM_BASE__INST1_SEG3 0 -#define THM_BASE__INST1_SEG4 0 - -#define THM_BASE__INST2_SEG0 0 -#define THM_BASE__INST2_SEG1 0 -#define THM_BASE__INST2_SEG2 0 -#define THM_BASE__INST2_SEG3 0 -#define THM_BASE__INST2_SEG4 0 - -#define THM_BASE__INST3_SEG0 0 -#define THM_BASE__INST3_SEG1 0 -#define THM_BASE__INST3_SEG2 0 -#define THM_BASE__INST3_SEG3 0 -#define THM_BASE__INST3_SEG4 0 - -#define THM_BASE__INST4_SEG0 0 -#define THM_BASE__INST4_SEG1 0 -#define THM_BASE__INST4_SEG2 0 -#define THM_BASE__INST4_SEG3 0 -#define THM_BASE__INST4_SEG4 0 - -#define THM_BASE__INST5_SEG0 0 -#define THM_BASE__INST5_SEG1 0 -#define THM_BASE__INST5_SEG2 0 -#define THM_BASE__INST5_SEG3 0 -#define THM_BASE__INST5_SEG4 0 - -#define THM_BASE__INST6_SEG0 0 -#define THM_BASE__INST6_SEG1 0 -#define THM_BASE__INST6_SEG2 0 -#define THM_BASE__INST6_SEG3 0 -#define THM_BASE__INST6_SEG4 0 - -#define UMC_BASE__INST0_SEG0 0x00014000 -#define UMC_BASE__INST0_SEG1 0x02425800 -#define UMC_BASE__INST0_SEG2 0 -#define UMC_BASE__INST0_SEG3 0 -#define UMC_BASE__INST0_SEG4 0 - -#define UMC_BASE__INST1_SEG0 0x00054000 -#define UMC_BASE__INST1_SEG1 0x02425C00 -#define UMC_BASE__INST1_SEG2 0 -#define UMC_BASE__INST1_SEG3 0 -#define UMC_BASE__INST1_SEG4 0 - -#define UMC_BASE__INST2_SEG0 0x00094000 -#define UMC_BASE__INST2_SEG1 0x02426000 -#define UMC_BASE__INST2_SEG2 0 -#define UMC_BASE__INST2_SEG3 0 -#define UMC_BASE__INST2_SEG4 0 - -#define UMC_BASE__INST3_SEG0 0x000D4000 -#define UMC_BASE__INST3_SEG1 0x02426400 -#define UMC_BASE__INST3_SEG2 0 -#define UMC_BASE__INST3_SEG3 0 -#define UMC_BASE__INST3_SEG4 0 - -#define UMC_BASE__INST4_SEG0 0x00114000 -#define UMC_BASE__INST4_SEG1 0x02426800 -#define UMC_BASE__INST4_SEG2 0 -#define UMC_BASE__INST4_SEG3 0 -#define UMC_BASE__INST4_SEG4 0 - -#define UMC_BASE__INST5_SEG0 0x00154000 -#define UMC_BASE__INST5_SEG1 0x02426C00 -#define UMC_BASE__INST5_SEG2 0 -#define UMC_BASE__INST5_SEG3 0 -#define UMC_BASE__INST5_SEG4 0 - -#define UMC_BASE__INST6_SEG0 0x00194000 -#define UMC_BASE__INST6_SEG1 0x02427000 -#define UMC_BASE__INST6_SEG2 0 -#define UMC_BASE__INST6_SEG3 0 -#define UMC_BASE__INST6_SEG4 0 - -#define USB0_BASE__INST0_SEG0 0x0242A800 -#define USB0_BASE__INST0_SEG1 0x05B00000 -#define USB0_BASE__INST0_SEG2 0 -#define USB0_BASE__INST0_SEG3 0 -#define USB0_BASE__INST0_SEG4 0 - -#define USB0_BASE__INST1_SEG0 0 -#define USB0_BASE__INST1_SEG1 0 -#define USB0_BASE__INST1_SEG2 0 -#define USB0_BASE__INST1_SEG3 0 -#define USB0_BASE__INST1_SEG4 0 - -#define USB0_BASE__INST2_SEG0 0 -#define USB0_BASE__INST2_SEG1 0 -#define USB0_BASE__INST2_SEG2 0 -#define USB0_BASE__INST2_SEG3 0 -#define USB0_BASE__INST2_SEG4 0 - -#define USB0_BASE__INST3_SEG0 0 -#define USB0_BASE__INST3_SEG1 0 -#define USB0_BASE__INST3_SEG2 0 -#define USB0_BASE__INST3_SEG3 0 -#define USB0_BASE__INST3_SEG4 0 - -#define USB0_BASE__INST4_SEG0 0 -#define USB0_BASE__INST4_SEG1 0 -#define USB0_BASE__INST4_SEG2 0 -#define USB0_BASE__INST4_SEG3 0 -#define USB0_BASE__INST4_SEG4 0 - -#define USB0_BASE__INST5_SEG0 0 -#define USB0_BASE__INST5_SEG1 0 -#define USB0_BASE__INST5_SEG2 0 -#define USB0_BASE__INST5_SEG3 0 -#define USB0_BASE__INST5_SEG4 0 - -#define USB0_BASE__INST6_SEG0 0 -#define USB0_BASE__INST6_SEG1 0 -#define USB0_BASE__INST6_SEG2 0 -#define USB0_BASE__INST6_SEG3 0 -#define USB0_BASE__INST6_SEG4 0 - -#define VCN_BASE__INST0_SEG0 0x00007800 -#define VCN_BASE__INST0_SEG1 0x00007E00 -#define VCN_BASE__INST0_SEG2 0x02403000 -#define VCN_BASE__INST0_SEG3 0 -#define VCN_BASE__INST0_SEG4 0 - -#define VCN_BASE__INST1_SEG0 0x00007B00 -#define VCN_BASE__INST1_SEG1 0x00012000 -#define VCN_BASE__INST1_SEG2 0x02445000 -#define VCN_BASE__INST1_SEG3 0 -#define VCN_BASE__INST1_SEG4 0 - -#define VCN_BASE__INST2_SEG0 0 -#define VCN_BASE__INST2_SEG1 0 -#define VCN_BASE__INST2_SEG2 0 -#define VCN_BASE__INST2_SEG3 0 -#define VCN_BASE__INST2_SEG4 0 - -#define VCN_BASE__INST3_SEG0 0 -#define VCN_BASE__INST3_SEG1 0 -#define VCN_BASE__INST3_SEG2 0 -#define VCN_BASE__INST3_SEG3 0 -#define VCN_BASE__INST3_SEG4 0 - -#define VCN_BASE__INST4_SEG0 0 -#define VCN_BASE__INST4_SEG1 0 -#define VCN_BASE__INST4_SEG2 0 -#define VCN_BASE__INST4_SEG3 0 -#define VCN_BASE__INST4_SEG4 0 - -#define VCN_BASE__INST5_SEG0 0 -#define VCN_BASE__INST5_SEG1 0 -#define VCN_BASE__INST5_SEG2 0 -#define VCN_BASE__INST5_SEG3 0 -#define VCN_BASE__INST5_SEG4 0 - -#define VCN_BASE__INST6_SEG0 0 -#define VCN_BASE__INST6_SEG1 0 -#define VCN_BASE__INST6_SEG2 0 -#define VCN_BASE__INST6_SEG3 0 -#define VCN_BASE__INST6_SEG4 0 - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/soc15d.h b/tinygrad/extra/hip_gpu_driver/soc15d.h deleted file mode 100644 index b9cbeb38..00000000 --- a/tinygrad/extra/hip_gpu_driver/soc15d.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef SOC15_H -#define SOC15_H - -#define GFX9_NUM_GFX_RINGS 1 -#define GFX9_NUM_COMPUTE_RINGS 8 - -/* - * PM4 - */ -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 - -#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) -#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) -#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) -#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) -#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ - ((reg) & 0xFFFF) | \ - ((n) & 0x3FFF) << 16) -#define CP_PACKET2 0x80000000 -#define PACKET2_PAD_SHIFT 0 -#define PACKET2_PAD_MASK (0x3fffffff << 0) - -#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) - -#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ - (((op) & 0xFF) << 8) | \ - ((n) & 0x3FFF) << 16) - -#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) - -#define PACKETJ_CONDITION_CHECK0 0 -#define PACKETJ_CONDITION_CHECK1 1 -#define PACKETJ_CONDITION_CHECK2 2 -#define PACKETJ_CONDITION_CHECK3 3 -#define PACKETJ_CONDITION_CHECK4 4 -#define PACKETJ_CONDITION_CHECK5 5 -#define PACKETJ_CONDITION_CHECK6 6 -#define PACKETJ_CONDITION_CHECK7 7 - -#define PACKETJ_TYPE0 0 -#define PACKETJ_TYPE1 1 -#define PACKETJ_TYPE2 2 -#define PACKETJ_TYPE3 3 -#define PACKETJ_TYPE4 4 -#define PACKETJ_TYPE5 5 -#define PACKETJ_TYPE6 6 -#define PACKETJ_TYPE7 7 - -#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \ - ((r & 0x3F) << 18) | \ - ((cond & 0xF) << 24) | \ - ((type & 0xF) << 28)) - -#define CP_PACKETJ_NOP 0x60000000 -#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF) -#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F) -#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF) -#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF) - -/* Packet 3 types */ -#define PACKET3_NOP 0x10 -#define PACKET3_SET_BASE 0x11 -#define PACKET3_BASE_INDEX(x) ((x) << 0) -#define CE_PARTITION_BASE 3 -#define PACKET3_CLEAR_STATE 0x12 -#define PACKET3_INDEX_BUFFER_SIZE 0x13 -#define PACKET3_DISPATCH_DIRECT 0x15 -#define PACKET3_DISPATCH_INDIRECT 0x16 -#define PACKET3_ATOMIC_GDS 0x1D -#define PACKET3_ATOMIC_MEM 0x1E -#define PACKET3_OCCLUSION_QUERY 0x1F -#define PACKET3_SET_PREDICATION 0x20 -#define PACKET3_REG_RMW 0x21 -#define PACKET3_COND_EXEC 0x22 -#define PACKET3_PRED_EXEC 0x23 -#define PACKET3_DRAW_INDIRECT 0x24 -#define PACKET3_DRAW_INDEX_INDIRECT 0x25 -#define PACKET3_INDEX_BASE 0x26 -#define PACKET3_DRAW_INDEX_2 0x27 -#define PACKET3_CONTEXT_CONTROL 0x28 -#define PACKET3_INDEX_TYPE 0x2A -#define PACKET3_DRAW_INDIRECT_MULTI 0x2C -#define PACKET3_DRAW_INDEX_AUTO 0x2D -#define PACKET3_NUM_INSTANCES 0x2F -#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 -#define PACKET3_INDIRECT_BUFFER_CONST 0x33 -#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 -#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 -#define PACKET3_DRAW_PREAMBLE 0x36 -#define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) ((x) << 8) - /* 0 - register - * 1 - memory (sync - via GRBM) - * 2 - gl2 - * 3 - gds - * 4 - reserved - * 5 - memory (async - direct) - */ -#define WR_ONE_ADDR (1 << 16) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) - /* 0 - me - * 1 - pfp - * 2 - ce - */ -#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 -#define PACKET3_MEM_SEMAPHORE 0x39 -# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) -# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ -# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) -# define PACKET3_SEM_SEL_WAIT (0x7 << 29) -#define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) - /* 0 - always - * 1 - < - * 2 - <= - * 3 - == - * 4 - != - * 5 - >= - * 6 - > - */ -#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) - /* 0 - reg - * 1 - mem - */ -#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) - /* 0 - wait_reg_mem - * 1 - wr_wait_wr_reg - */ -#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) - /* 0 - me - * 1 - pfp - */ -#define PACKET3_INDIRECT_BUFFER 0x3F -#define INDIRECT_BUFFER_VALID (1 << 23) -#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) - /* 0 - LRU - * 1 - Stream - * 2 - Bypass - */ -#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) -#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) -#define PACKET3_COPY_DATA 0x40 -#define PACKET3_PFP_SYNC_ME 0x42 -#define PACKET3_COND_WRITE 0x45 -#define PACKET3_EVENT_WRITE 0x46 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - */ -#define PACKET3_RELEASE_MEM 0x49 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) -#define EOP_TCL1_VOL_ACTION_EN (1 << 12) -#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ -#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ -#define EOP_TCL1_ACTION_EN (1 << 16) -#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ -#define EOP_TC_NC_ACTION_EN (1 << 19) -#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ -#define EOP_EXEC (1 << 28) /* For Trailing Fence */ - -#define DATA_SEL(x) ((x) << 29) - /* 0 - discard - * 1 - send low 32bit data - * 2 - send 64bit data - * 3 - send 64bit GPU counter value - * 4 - send 64bit sys counter value - */ -#define INT_SEL(x) ((x) << 24) - /* 0 - none - * 1 - interrupt only (DATA_SEL = 0) - * 2 - interrupt when data write is confirmed - */ -#define DST_SEL(x) ((x) << 16) - /* 0 - MC - * 1 - TC/L2 - */ - - - -#define PACKET3_PREAMBLE_CNTL 0x4A -# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) -# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) -#define PACKET3_DMA_DATA 0x50 -/* 1. header - * 2. CONTROL - * 3. SRC_ADDR_LO or DATA [31:0] - * 4. SRC_ADDR_HI [31:0] - * 5. DST_ADDR_LO [31:0] - * 6. DST_ADDR_HI [7:0] - * 7. COMMAND [30:21] | BYTE_COUNT [20:0] - */ -/* CONTROL */ -# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) - /* 0 - ME - * 1 - PFP - */ -# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) - /* 0 - LRU - * 1 - Stream - */ -# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) - /* 0 - DST_ADDR using DAS - * 1 - GDS - * 3 - DST_ADDR using L2 - */ -# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) - /* 0 - SRC_ADDR using SAS - * 1 - GDS - * 2 - DATA - * 3 - SRC_ADDR using L2 - */ -# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) -/* COMMAND */ -# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) -# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) -# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) -#define PACKET3_ACQUIRE_MEM 0x58 -/* 1. HEADER - * 2. COHER_CNTL [30:0] - * 2.1 ENGINE_SEL [31:31] - * 3. COHER_SIZE [31:0] - * 4. COHER_SIZE_HI [7:0] - * 5. COHER_BASE_LO [31:0] - * 6. COHER_BASE_HI [23:0] - * 7. POLL_INTERVAL [15:0] - */ -/* COHER_CNTL fields for CP_COHER_CNTL */ -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29) -#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30) -#define PACKET3_REWIND 0x59 -#define PACKET3_LOAD_UCONFIG_REG 0x5E -#define PACKET3_LOAD_SH_REG 0x5F -#define PACKET3_LOAD_CONFIG_REG 0x60 -#define PACKET3_LOAD_CONTEXT_REG 0x61 -#define PACKET3_SET_CONFIG_REG 0x68 -#define PACKET3_SET_CONFIG_REG_START 0x00002000 -#define PACKET3_SET_CONFIG_REG_END 0x00002c00 -#define PACKET3_SET_CONTEXT_REG 0x69 -#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 -#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 -#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 -#define PACKET3_SET_SH_REG 0x76 -#define PACKET3_SET_SH_REG_START 0x00002c00 -#define PACKET3_SET_SH_REG_END 0x00003000 -#define PACKET3_SET_SH_REG_OFFSET 0x77 -#define PACKET3_SET_QUEUE_REG 0x78 -#define PACKET3_SET_UCONFIG_REG 0x79 -#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 -#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 -#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) -#define PACKET3_SCRATCH_RAM_WRITE 0x7D -#define PACKET3_SCRATCH_RAM_READ 0x7E -#define PACKET3_LOAD_CONST_RAM 0x80 -#define PACKET3_WRITE_CONST_RAM 0x81 -#define PACKET3_DUMP_CONST_RAM 0x83 -#define PACKET3_INCREMENT_CE_COUNTER 0x84 -#define PACKET3_INCREMENT_DE_COUNTER 0x85 -#define PACKET3_WAIT_ON_CE_COUNTER 0x86 -#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 -#define PACKET3_SWITCH_BUFFER 0x8B -#define PACKET3_FRAME_CONTROL 0x90 -# define FRAME_TMZ (1 << 0) -# define FRAME_CMD(x) ((x) << 28) - /* - * x=0: tmz_begin - * x=1: tmz_end - */ - -#define PACKET3_INVALIDATE_TLBS 0x98 -# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) -# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) -# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) -# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) -#define PACKET3_SET_RESOURCES 0xA0 -/* 1. header - * 2. CONTROL - * 3. QUEUE_MASK_LO [31:0] - * 4. QUEUE_MASK_HI [31:0] - * 5. GWS_MASK_LO [31:0] - * 6. GWS_MASK_HI [31:0] - * 7. OAC_MASK [15:0] - * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] - */ -# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) -# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) -# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) -#define PACKET3_MAP_QUEUES 0xA2 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. MQD_ADDR_LO [31:0] - * 5. MQD_ADDR_HI [31:0] - * 6. WPTR_ADDR_LO [31:0] - * 7. WPTR_ADDR_HI [31:0] - */ -/* CONTROL */ -# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) -# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) -# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) -# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) -# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) -# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) -# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) -# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) -# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) -/* CONTROL2 */ -# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) -# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) -#define PACKET3_UNMAP_QUEUES 0xA3 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. CONTROL3 - * 5. CONTROL4 - * 6. CONTROL5 - */ -/* CONTROL */ -# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) - /* 0 - PREEMPT_QUEUES - * 1 - RESET_QUEUES - * 2 - DISABLE_PROCESS_QUEUES - * 3 - PREEMPT_QUEUES_NO_UNMAP - */ -# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) -# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) -# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) -/* CONTROL2a */ -# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) -/* CONTROL2b */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) -/* CONTROL3a */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) -/* CONTROL3b */ -# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) -/* CONTROL4 */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) -/* CONTROL5 */ -# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) -#define PACKET3_QUERY_STATUS 0xA4 -/* 1. header - * 2. CONTROL - * 3. CONTROL2 - * 4. ADDR_LO [31:0] - * 5. ADDR_HI [31:0] - * 6. DATA_LO [31:0] - * 7. DATA_HI [31:0] - */ -/* CONTROL */ -# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) -# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) -# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) -/* CONTROL2a */ -# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) -/* CONTROL2b */ -# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) -# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) - -#define PACKET3_RUN_CLEANER_SHADER 0xD2 -/* 1. header - * 2. RESERVED [31:0] - */ - -#define VCE_CMD_NO_OP 0x00000000 -#define VCE_CMD_END 0x00000001 -#define VCE_CMD_IB 0x00000002 -#define VCE_CMD_FENCE 0x00000003 -#define VCE_CMD_TRAP 0x00000004 -#define VCE_CMD_IB_AUTO 0x00000005 -#define VCE_CMD_SEMAPHORE 0x00000006 - -#define VCE_CMD_IB_VM 0x00000102 -#define VCE_CMD_WAIT_GE 0x00000106 -#define VCE_CMD_UPDATE_PTB 0x00000107 -#define VCE_CMD_FLUSH_TLB 0x00000108 -#define VCE_CMD_REG_WRITE 0x00000109 -#define VCE_CMD_REG_WAIT 0x0000010a - -#define HEVC_ENC_CMD_NO_OP 0x00000000 -#define HEVC_ENC_CMD_END 0x00000001 -#define HEVC_ENC_CMD_FENCE 0x00000003 -#define HEVC_ENC_CMD_TRAP 0x00000004 -#define HEVC_ENC_CMD_IB_VM 0x00000102 -#define HEVC_ENC_CMD_REG_WRITE 0x00000109 -#define HEVC_ENC_CMD_REG_WAIT 0x0000010a - -#endif diff --git a/tinygrad/extra/hip_gpu_driver/soc21_enum.h b/tinygrad/extra/hip_gpu_driver/soc21_enum.h deleted file mode 100644 index 07d98bff..00000000 --- a/tinygrad/extra/hip_gpu_driver/soc21_enum.h +++ /dev/null @@ -1,22477 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ -#if !defined (_soc21_ENUM_HEADER) -#define _soc21_ENUM_HEADER - -#ifndef _DRIVER_BUILD -#ifndef GL_ZERO -#define GL__ZERO BLEND_ZERO -#define GL__ONE BLEND_ONE -#define GL__SRC_COLOR BLEND_SRC_COLOR -#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR -#define GL__DST_COLOR BLEND_DST_COLOR -#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR -#define GL__SRC_ALPHA BLEND_SRC_ALPHA -#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA -#define GL__DST_ALPHA BLEND_DST_ALPHA -#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA -#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE -#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR -#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR -#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA -#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA -#endif -#endif - -/******************************************************* - * Chip Enums - *******************************************************/ - -/* - * DSM_DATA_SEL enum - */ - -typedef enum DSM_DATA_SEL { -DSM_DATA_SEL_DISABLE = 0x00000000, -DSM_DATA_SEL_0 = 0x00000001, -DSM_DATA_SEL_1 = 0x00000002, -DSM_DATA_SEL_BOTH = 0x00000003, -} DSM_DATA_SEL; - -/* - * DSM_ENABLE_ERROR_INJECT enum - */ - -typedef enum DSM_ENABLE_ERROR_INJECT { -DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, -DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, -} DSM_ENABLE_ERROR_INJECT; - -/* - * DSM_SELECT_INJECT_DELAY enum - */ - -typedef enum DSM_SELECT_INJECT_DELAY { -DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, -DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, -} DSM_SELECT_INJECT_DELAY; - -/* - * DSM_SINGLE_WRITE enum - */ - -typedef enum DSM_SINGLE_WRITE { -DSM_SINGLE_WRITE_DIS = 0x00000000, -DSM_SINGLE_WRITE_EN = 0x00000001, -} DSM_SINGLE_WRITE; - -/* - * ENUM_NUM_SIMD_PER_CU enum - */ - -typedef enum ENUM_NUM_SIMD_PER_CU { -NUM_SIMD_PER_CU = 0x00000002, -} ENUM_NUM_SIMD_PER_CU; - -/* - * GATCL1RequestType enum - */ - -typedef enum GATCL1RequestType { -GATCL1_TYPE_NORMAL = 0x00000000, -GATCL1_TYPE_SHOOTDOWN = 0x00000001, -GATCL1_TYPE_BYPASS = 0x00000002, -} GATCL1RequestType; - -/* - * GL0V_CACHE_POLICIES enum - */ - -typedef enum GL0V_CACHE_POLICIES { -GL0V_CACHE_POLICY_MISS_LRU = 0x00000000, -GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001, -GL0V_CACHE_POLICY_HIT_LRU = 0x00000002, -GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003, -} GL0V_CACHE_POLICIES; - -/* - * GL1_CACHE_POLICIES enum - */ - -typedef enum GL1_CACHE_POLICIES { -GL1_CACHE_POLICY_MISS_LRU = 0x00000000, -GL1_CACHE_POLICY_MISS_EVICT = 0x00000001, -GL1_CACHE_POLICY_HIT_LRU = 0x00000002, -GL1_CACHE_POLICY_HIT_EVICT = 0x00000003, -} GL1_CACHE_POLICIES; - -/* - * GL1_CACHE_STORE_POLICIES enum - */ - -typedef enum GL1_CACHE_STORE_POLICIES { -GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000, -} GL1_CACHE_STORE_POLICIES; - -/* - * GL2_CACHE_POLICIES enum - */ - -typedef enum GL2_CACHE_POLICIES { -GL2_CACHE_POLICY_LRU = 0x00000000, -GL2_CACHE_POLICY_STREAM = 0x00000001, -GL2_CACHE_POLICY_NOA = 0x00000002, -GL2_CACHE_POLICY_BYPASS = 0x00000003, -} GL2_CACHE_POLICIES; - -/* - * Hdp_SurfaceEndian enum - */ - -typedef enum Hdp_SurfaceEndian { -HDP_ENDIAN_NONE = 0x00000000, -HDP_ENDIAN_8IN16 = 0x00000001, -HDP_ENDIAN_8IN32 = 0x00000002, -HDP_ENDIAN_8IN64 = 0x00000003, -} Hdp_SurfaceEndian; - -/* - * MTYPE enum - */ - -typedef enum MTYPE { -MTYPE_C_RW_US = 0x00000000, -MTYPE_RESERVED_1 = 0x00000001, -MTYPE_C_RO_S = 0x00000002, -MTYPE_UC = 0x00000003, -MTYPE_C_RW_S = 0x00000004, -MTYPE_RESERVED_5 = 0x00000005, -MTYPE_C_RO_US = 0x00000006, -MTYPE_RESERVED_7 = 0x00000007, -} MTYPE; - -/* - * PERFMON_COUNTER_MODE enum - */ - -typedef enum PERFMON_COUNTER_MODE { -PERFMON_COUNTER_MODE_ACCUM = 0x00000000, -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, -PERFMON_COUNTER_MODE_MAX = 0x00000002, -PERFMON_COUNTER_MODE_DIRTY = 0x00000003, -PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, -PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, -} PERFMON_COUNTER_MODE; - -/* - * PERFMON_SPM_MODE enum - */ - -typedef enum PERFMON_SPM_MODE { -PERFMON_SPM_MODE_OFF = 0x00000000, -PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, -PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, -PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, -PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, -PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, -PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, -PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, -PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, -} PERFMON_SPM_MODE; - -/* - * RMI_CID enum - */ - -typedef enum RMI_CID { -RMI_CID_CC = 0x00000000, -RMI_CID_FC = 0x00000001, -RMI_CID_CM = 0x00000002, -RMI_CID_DC = 0x00000003, -RMI_CID_Z = 0x00000004, -RMI_CID_S = 0x00000005, -RMI_CID_TILE = 0x00000006, -RMI_CID_ZPCPSD = 0x00000007, -} RMI_CID; - -/* - * ReadPolicy enum - */ - -typedef enum ReadPolicy { -CACHE_LRU_RD = 0x00000000, -CACHE_STREAM_RD = 0x00000001, -CACHE_NOA = 0x00000002, -RESERVED_RDPOLICY = 0x00000003, -} ReadPolicy; - -/* - * SDMA_PERFMON_SEL enum - */ - -typedef enum SDMA_PERFMON_SEL { -SDMA_PERFMON_SEL_CYCLE = 0x00000000, -SDMA_PERFMON_SEL_IDLE = 0x00000001, -SDMA_PERFMON_SEL_REG_IDLE = 0x00000002, -SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003, -SDMA_PERFMON_SEL_RB_FULL = 0x00000004, -SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005, -SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006, -SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007, -SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008, -SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009, -SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a, -SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b, -SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c, -SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d, -SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e, -SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, -SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010, -SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011, -SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012, -SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013, -SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014, -SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015, -SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016, -SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017, -SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a, -SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b, -SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c, -SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d, -SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e, -SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f, -SDMA_PERFMON_SEL_INT_IDLE = 0x00000020, -SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021, -SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022, -SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023, -SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024, -SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025, -SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027, -SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028, -SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029, -SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a, -SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b, -SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c, -SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d, -SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030, -SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033, -SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034, -SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035, -SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036, -SDMA_PERFMON_SEL_GFX_SELECT = 0x00000037, -SDMA_PERFMON_SEL_RLC0_SELECT = 0x00000038, -SDMA_PERFMON_SEL_RLC1_SELECT = 0x00000039, -SDMA_PERFMON_SEL_PAGE_SELECT = 0x0000003a, -SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b, -SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c, -SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d, -SDMA_PERFMON_SEL_DOORBELL = 0x0000003e, -SDMA_PERFMON_SEL_F32_L1_WR_VLD = 0x0000003f, -SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040, -SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041, -SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042, -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043, -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044, -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, -SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047, -SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048, -SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049, -SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a, -SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b, -SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c, -SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d, -SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e, -SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f, -SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050, -SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051, -SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052, -SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053, -SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054, -SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055, -SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056, -SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057, -SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058, -SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, -SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, -SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, -SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, -SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d, -SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e, -SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f, -SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060, -SDMA_PERFMON_SEL_GCR_SEND = 0x00000061, -SDMA_PERFMON_SEL_GCR_RTN = 0x00000062, -SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063, -SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064, -} SDMA_PERFMON_SEL; - -/* - * SDMA_PERF_SEL enum - */ - -typedef enum SDMA_PERF_SEL { -SDMA_PERF_SEL_CYCLE = 0x00000000, -SDMA_PERF_SEL_IDLE = 0x00000001, -SDMA_PERF_SEL_REG_IDLE = 0x00000002, -SDMA_PERF_SEL_RB_EMPTY = 0x00000003, -SDMA_PERF_SEL_RB_FULL = 0x00000004, -SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, -SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, -SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, -SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, -SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, -SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, -SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, -SDMA_PERF_SEL_EX_IDLE = 0x0000000d, -SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, -SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, -SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, -SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, -SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, -SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, -SDMA_PERF_SEL_SEM_IDLE = 0x00000018, -SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, -SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, -SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, -SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, -SDMA_PERF_SEL_INT_IDLE = 0x0000001e, -SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, -SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, -SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, -SDMA_PERF_SEL_NUM_PACKET = 0x00000023, -SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, -SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, -SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, -SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, -SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, -SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, -SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, -SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, -SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, -SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, -SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, -SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, -SDMA_PERF_SEL_GFX_SELECT = 0x00000035, -SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, -SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, -SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, -SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, -SDMA_PERF_SEL_DOORBELL = 0x0000003c, -SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, -SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, -SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, -SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, -SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041, -SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042, -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043, -SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044, -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045, -SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046, -SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047, -SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048, -SDMA_PERF_SEL_UTCL2_FREE = 0x00000049, -SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a, -SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b, -SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c, -SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d, -SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e, -SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f, -SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050, -SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051, -SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052, -SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053, -SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054, -SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055, -SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056, -SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057, -SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058, -SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059, -SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a, -SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b, -SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c, -SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d, -SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e, -SDMA_PERF_SEL_TLBI_SEND = 0x0000005f, -SDMA_PERF_SEL_TLBI_RTN = 0x00000060, -SDMA_PERF_SEL_GCR_SEND = 0x00000061, -SDMA_PERF_SEL_GCR_RTN = 0x00000062, -SDMA_PERF_SEL_CGCG_FENCE = 0x00000063, -SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064, -SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065, -SDMA_PERF_SEL_F32_CH_WR_REQ = 0x00000066, -SDMA_PERF_SEL_F32_CH_WR_RET = 0x00000067, -SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 0x00000068, -SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 0x00000069, -SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a, -SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b, -SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c, -SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d, -SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e, -SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f, -SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070, -SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071, -SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072, -SDMA_PERF_SEL_CMD_OP_START = 0x00000073, -SDMA_PERF_SEL_CMD_OP_END = 0x00000074, -SDMA_PERF_SEL_CE_BUSY = 0x00000075, -SDMA_PERF_SEL_CE_BUSY_START = 0x00000076, -SDMA_PERF_SEL_CE_BUSY_END = 0x00000077, -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000078, -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000079, -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x0000007a, -SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b, -SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c, -SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d, -SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e, -} SDMA_PERF_SEL; - -/* - * TCC_CACHE_POLICIES enum - */ - -typedef enum TCC_CACHE_POLICIES { -TCC_CACHE_POLICY_LRU = 0x00000000, -TCC_CACHE_POLICY_STREAM = 0x00000001, -} TCC_CACHE_POLICIES; - -/* - * TCC_MTYPE enum - */ - -typedef enum TCC_MTYPE { -MTYPE_NC = 0x00000000, -MTYPE_WC = 0x00000001, -MTYPE_CC = 0x00000002, -} TCC_MTYPE; - -/* - * UTCL0FaultType enum - */ - -typedef enum UTCL0FaultType { -UTCL0_XNACK_SUCCESS = 0x00000000, -UTCL0_XNACK_RETRY = 0x00000001, -UTCL0_XNACK_PRT = 0x00000002, -UTCL0_XNACK_NO_RETRY = 0x00000003, -} UTCL0FaultType; - -/* - * UTCL0RequestType enum - */ - -typedef enum UTCL0RequestType { -UTCL0_TYPE_NORMAL = 0x00000000, -UTCL0_TYPE_SHOOTDOWN = 0x00000001, -UTCL0_TYPE_BYPASS = 0x00000002, -} UTCL0RequestType; - -/* - * UTCL1FaultType enum - */ - -typedef enum UTCL1FaultType { -UTCL1_XNACK_SUCCESS = 0x00000000, -UTCL1_XNACK_RETRY = 0x00000001, -UTCL1_XNACK_PRT = 0x00000002, -UTCL1_XNACK_NO_RETRY = 0x00000003, -} UTCL1FaultType; - -/* - * UTCL1RequestType enum - */ - -typedef enum UTCL1RequestType { -UTCL1_TYPE_NORMAL = 0x00000000, -UTCL1_TYPE_SHOOTDOWN = 0x00000001, -UTCL1_TYPE_BYPASS = 0x00000002, -} UTCL1RequestType; - -/* - * VMEMCMD_RETURN_ORDER enum - */ - -typedef enum VMEMCMD_RETURN_ORDER { -VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000, -VMEMCMD_RETURN_IN_ORDER = 0x00000001, -VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002, -} VMEMCMD_RETURN_ORDER; - -/* - * WritePolicy enum - */ - -typedef enum WritePolicy { -CACHE_LRU_WR = 0x00000000, -CACHE_STREAM = 0x00000001, -CACHE_NOA_WR = 0x00000002, -CACHE_BYPASS = 0x00000003, -} WritePolicy; - -/******************************************************* - * CNVC_CFG Enums - *******************************************************/ - -/* - * CNVC_BYPASS enum - */ - -typedef enum CNVC_BYPASS { -CNVC_BYPASS_DISABLE = 0x00000000, -CNVC_BYPASS_EN = 0x00000001, -} CNVC_BYPASS; - -/* - * CNVC_COEF_FORMAT_ENUM enum - */ - -typedef enum CNVC_COEF_FORMAT_ENUM { -CNVC_FIX_S2_13 = 0x00000000, -CNVC_FIX_S3_12 = 0x00000001, -} CNVC_COEF_FORMAT_ENUM; - -/* - * CNVC_ENABLE enum - */ - -typedef enum CNVC_ENABLE { -CNVC_DIS = 0x00000000, -CNVC_EN = 0x00000001, -} CNVC_ENABLE; - -/* - * CNVC_PENDING enum - */ - -typedef enum CNVC_PENDING { -CNVC_NOT_PENDING = 0x00000000, -CNVC_YES_PENDING = 0x00000001, -} CNVC_PENDING; - -/* - * COLOR_KEYER_MODE enum - */ - -typedef enum COLOR_KEYER_MODE { -FORCE_00 = 0x00000000, -FORCE_FF = 0x00000001, -RANGE_00 = 0x00000002, -RANGE_FF = 0x00000003, -} COLOR_KEYER_MODE; - -/* - * DENORM_TRUNCATE enum - */ - -typedef enum DENORM_TRUNCATE { -CNVC_ROUND = 0x00000000, -CNVC_TRUNCATE = 0x00000001, -} DENORM_TRUNCATE; - -/* - * FORMAT_CROSSBAR enum - */ - -typedef enum FORMAT_CROSSBAR { -FORMAT_CROSSBAR_R = 0x00000000, -FORMAT_CROSSBAR_G = 0x00000001, -FORMAT_CROSSBAR_B = 0x00000002, -} FORMAT_CROSSBAR; - -/* - * PIX_EXPAND_MODE enum - */ - -typedef enum PIX_EXPAND_MODE { -PIX_DYNAMIC_EXPANSION = 0x00000000, -PIX_ZERO_EXPANSION = 0x00000001, -} PIX_EXPAND_MODE; - -/* - * PRE_CSC_MODE_ENUM enum - */ - -typedef enum PRE_CSC_MODE_ENUM { -PRE_CSC_BYPASS = 0x00000000, -PRE_CSC_SET_A = 0x00000001, -PRE_CSC_SET_B = 0x00000002, -} PRE_CSC_MODE_ENUM; - -/* - * PRE_DEGAM_MODE enum - */ - -typedef enum PRE_DEGAM_MODE { -PRE_DEGAM_BYPASS = 0x00000000, -PRE_DEGAM_ENABLE = 0x00000001, -} PRE_DEGAM_MODE; - -/* - * PRE_DEGAM_SELECT enum - */ - -typedef enum PRE_DEGAM_SELECT { -PRE_DEGAM_SRGB = 0x00000000, -PRE_DEGAM_GAMMA_22 = 0x00000001, -PRE_DEGAM_GAMMA_24 = 0x00000002, -PRE_DEGAM_GAMMA_26 = 0x00000003, -PRE_DEGAM_BT2020 = 0x00000004, -PRE_DEGAM_BT2100PQ = 0x00000005, -PRE_DEGAM_BT2100HLG = 0x00000006, -} PRE_DEGAM_SELECT; - -/* - * SURFACE_PIXEL_FORMAT enum - */ - -typedef enum SURFACE_PIXEL_FORMAT { -ARGB1555 = 0x00000001, -RGBA5551 = 0x00000002, -RGB565 = 0x00000003, -BGR565 = 0x00000004, -ARGB4444 = 0x00000005, -RGBA4444 = 0x00000006, -ARGB8888 = 0x00000008, -RGBA8888 = 0x00000009, -ARGB2101010 = 0x0000000a, -RGBA1010102 = 0x0000000b, -AYCrCb8888 = 0x0000000c, -YCrCbA8888 = 0x0000000d, -ACrYCb8888 = 0x0000000e, -CrYCbA8888 = 0x0000000f, -ARGB16161616_10MSB = 0x00000010, -RGBA16161616_10MSB = 0x00000011, -ARGB16161616_10LSB = 0x00000012, -RGBA16161616_10LSB = 0x00000013, -ARGB16161616_12MSB = 0x00000014, -RGBA16161616_12MSB = 0x00000015, -ARGB16161616_12LSB = 0x00000016, -RGBA16161616_12LSB = 0x00000017, -ARGB16161616_FLOAT = 0x00000018, -RGBA16161616_FLOAT = 0x00000019, -ARGB16161616_UNORM = 0x0000001a, -RGBA16161616_UNORM = 0x0000001b, -ARGB16161616_SNORM = 0x0000001c, -RGBA16161616_SNORM = 0x0000001d, -AYCrCb16161616_10MSB = 0x00000020, -AYCrCb16161616_10LSB = 0x00000021, -YCrCbA16161616_10MSB = 0x00000022, -YCrCbA16161616_10LSB = 0x00000023, -ACrYCb16161616_10MSB = 0x00000024, -ACrYCb16161616_10LSB = 0x00000025, -CrYCbA16161616_10MSB = 0x00000026, -CrYCbA16161616_10LSB = 0x00000027, -AYCrCb16161616_12MSB = 0x00000028, -AYCrCb16161616_12LSB = 0x00000029, -YCrCbA16161616_12MSB = 0x0000002a, -YCrCbA16161616_12LSB = 0x0000002b, -ACrYCb16161616_12MSB = 0x0000002c, -ACrYCb16161616_12LSB = 0x0000002d, -CrYCbA16161616_12MSB = 0x0000002e, -CrYCbA16161616_12LSB = 0x0000002f, -Y8_CrCb88_420_PLANAR = 0x00000040, -Y8_CbCr88_420_PLANAR = 0x00000041, -Y10_CrCb1010_420_PLANAR = 0x00000042, -Y10_CbCr1010_420_PLANAR = 0x00000043, -Y12_CrCb1212_420_PLANAR = 0x00000044, -Y12_CbCr1212_420_PLANAR = 0x00000045, -YCrYCb8888_422_PACKED = 0x00000048, -YCbYCr8888_422_PACKED = 0x00000049, -CrYCbY8888_422_PACKED = 0x0000004a, -CbYCrY8888_422_PACKED = 0x0000004b, -YCrYCb10101010_422_PACKED = 0x0000004c, -YCbYCr10101010_422_PACKED = 0x0000004d, -CrYCbY10101010_422_PACKED = 0x0000004e, -CbYCrY10101010_422_PACKED = 0x0000004f, -YCrYCb12121212_422_PACKED = 0x00000050, -YCbYCr12121212_422_PACKED = 0x00000051, -CrYCbY12121212_422_PACKED = 0x00000052, -CbYCrY12121212_422_PACKED = 0x00000053, -RGB111110_FIX = 0x00000070, -BGR101111_FIX = 0x00000071, -ACrYCb2101010 = 0x00000072, -CrYCbA1010102 = 0x00000073, -RGBE = 0x00000074, -RGB111110_FLOAT = 0x00000076, -BGR101111_FLOAT = 0x00000077, -MONO_8 = 0x00000078, -MONO_10MSB = 0x00000079, -MONO_10LSB = 0x0000007a, -MONO_12MSB = 0x0000007b, -MONO_12LSB = 0x0000007c, -MONO_16 = 0x0000007d, -} SURFACE_PIXEL_FORMAT; - -/* - * XNORM enum - */ - -typedef enum XNORM { -XNORM_A = 0x00000000, -XNORM_B = 0x00000001, -} XNORM; - -/******************************************************* - * CNVC_CUR Enums - *******************************************************/ - -/* - * CUR_ENABLE enum - */ - -typedef enum CUR_ENABLE { -CUR_DIS = 0x00000000, -CUR_EN = 0x00000001, -} CUR_ENABLE; - -/* - * CUR_EXPAND_MODE enum - */ - -typedef enum CUR_EXPAND_MODE { -CUR_DYNAMIC_EXPANSION = 0x00000000, -CUR_ZERO_EXPANSION = 0x00000001, -} CUR_EXPAND_MODE; - -/* - * CUR_INV_CLAMP enum - */ - -typedef enum CUR_INV_CLAMP { -CUR_CLAMP_DIS = 0x00000000, -CUR_CLAMP_EN = 0x00000001, -} CUR_INV_CLAMP; - -/* - * CUR_MODE enum - */ - -typedef enum CUR_MODE { -MONO_2BIT = 0x00000000, -COLOR_24BIT_1BIT_AND = 0x00000001, -COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, -COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, -COLOR_64BIT_FP_PREMULT = 0x00000004, -COLOR_64BIT_FP_UNPREMULT = 0x00000005, -} CUR_MODE; - -/* - * CUR_PENDING enum - */ - -typedef enum CUR_PENDING { -CUR_NOT_PENDING = 0x00000000, -CUR_YES_PENDING = 0x00000001, -} CUR_PENDING; - -/* - * CUR_ROM_EN enum - */ - -typedef enum CUR_ROM_EN { -CUR_FP_NO_ROM = 0x00000000, -CUR_FP_USE_ROM = 0x00000001, -} CUR_ROM_EN; - -/******************************************************* - * DSCL Enums - *******************************************************/ - -/* - * COEF_RAM_SELECT_RD enum - */ - -typedef enum COEF_RAM_SELECT_RD { -COEF_RAM_SELECT_BACK = 0x00000000, -COEF_RAM_SELECT_CURRENT = 0x00000001, -} COEF_RAM_SELECT_RD; - -/* - * DSCL_MODE_SEL enum - */ - -typedef enum DSCL_MODE_SEL { -DSCL_MODE_SCALING_444_BYPASS = 0x00000000, -DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001, -DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002, -DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003, -DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004, -DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005, -DSCL_MODE_DSCL_BYPASS = 0x00000006, -} DSCL_MODE_SEL; - -/* - * LB_ALPHA_EN enum - */ - -typedef enum LB_ALPHA_EN { -LB_ALPHA_DISABLE = 0x00000000, -LB_ALPHA_ENABLE = 0x00000001, -} LB_ALPHA_EN; - -/* - * LB_INTERLEAVE_EN enum - */ - -typedef enum LB_INTERLEAVE_EN { -LB_INTERLEAVE_DISABLE = 0x00000000, -LB_INTERLEAVE_ENABLE = 0x00000001, -} LB_INTERLEAVE_EN; - -/* - * LB_MEMORY_CONFIG enum - */ - -typedef enum LB_MEMORY_CONFIG { -LB_MEMORY_CONFIG_0 = 0x00000000, -LB_MEMORY_CONFIG_1 = 0x00000001, -LB_MEMORY_CONFIG_2 = 0x00000002, -LB_MEMORY_CONFIG_3 = 0x00000003, -} LB_MEMORY_CONFIG; - -/* - * OBUF_BYPASS_SEL enum - */ - -typedef enum OBUF_BYPASS_SEL { -OBUF_BYPASS_DIS = 0x00000000, -OBUF_BYPASS_EN = 0x00000001, -} OBUF_BYPASS_SEL; - -/* - * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum - */ - -typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL { -OBUF_FULL_RECOUT = 0x00000000, -OBUF_HALF_RECOUT = 0x00000001, -} OBUF_IS_HALF_RECOUT_WIDTH_SEL; - -/* - * OBUF_USE_FULL_BUFFER_SEL enum - */ - -typedef enum OBUF_USE_FULL_BUFFER_SEL { -OBUF_RECOUT = 0x00000000, -OBUF_FULL = 0x00000001, -} OBUF_USE_FULL_BUFFER_SEL; - -/* - * SCL_2TAP_HARDCODE enum - */ - -typedef enum SCL_2TAP_HARDCODE { -SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000, -SCL_COEF_2TAP_HARDCODE_ON = 0x00000001, -} SCL_2TAP_HARDCODE; - -/* - * SCL_ALPHA_COEF enum - */ - -typedef enum SCL_ALPHA_COEF { -SCL_ALPHA_COEF_FIRST = 0x00000000, -SCL_ALPHA_COEF_SECOND = 0x00000001, -} SCL_ALPHA_COEF; - -/* - * SCL_AUTOCAL_MODE enum - */ - -typedef enum SCL_AUTOCAL_MODE { -AUTOCAL_MODE_OFF = 0x00000000, -AUTOCAL_MODE_AUTOSCALE = 0x00000001, -AUTOCAL_MODE_AUTOCENTER = 0x00000002, -AUTOCAL_MODE_AUTOREPLICATE = 0x00000003, -} SCL_AUTOCAL_MODE; - -/* - * SCL_BOUNDARY enum - */ - -typedef enum SCL_BOUNDARY { -SCL_BOUNDARY_EDGE = 0x00000000, -SCL_BOUNDARY_BLACK = 0x00000001, -} SCL_BOUNDARY; - -/* - * SCL_CHROMA_COEF enum - */ - -typedef enum SCL_CHROMA_COEF { -SCL_CHROMA_COEF_FIRST = 0x00000000, -SCL_CHROMA_COEF_SECOND = 0x00000001, -} SCL_CHROMA_COEF; - -/* - * SCL_COEF_FILTER_TYPE_SEL enum - */ - -typedef enum SCL_COEF_FILTER_TYPE_SEL { -SCL_COEF_LUMA_VERT_FILTER = 0x00000000, -SCL_COEF_LUMA_HORZ_FILTER = 0x00000001, -SCL_COEF_CHROMA_VERT_FILTER = 0x00000002, -SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003, -} SCL_COEF_FILTER_TYPE_SEL; - -/* - * SCL_COEF_RAM_SEL enum - */ - -typedef enum SCL_COEF_RAM_SEL { -SCL_COEF_RAM_SEL_0 = 0x00000000, -SCL_COEF_RAM_SEL_1 = 0x00000001, -} SCL_COEF_RAM_SEL; - -/* - * SCL_SHARP_EN enum - */ - -typedef enum SCL_SHARP_EN { -SCL_SHARP_DISABLE = 0x00000000, -SCL_SHARP_ENABLE = 0x00000001, -} SCL_SHARP_EN; - -/******************************************************* - * CM Enums - *******************************************************/ - -/* - * CMC_3DLUT_30BIT_ENUM enum - */ - -typedef enum CMC_3DLUT_30BIT_ENUM { -CMC_3DLUT_36BIT = 0x00000000, -CMC_3DLUT_30BIT = 0x00000001, -} CMC_3DLUT_30BIT_ENUM; - -/* - * CMC_3DLUT_RAM_SEL enum - */ - -typedef enum CMC_3DLUT_RAM_SEL { -CMC_RAM0_ACCESS = 0x00000000, -CMC_RAM1_ACCESS = 0x00000001, -CMC_RAM2_ACCESS = 0x00000002, -CMC_RAM3_ACCESS = 0x00000003, -} CMC_3DLUT_RAM_SEL; - -/* - * CMC_3DLUT_SIZE_ENUM enum - */ - -typedef enum CMC_3DLUT_SIZE_ENUM { -CMC_3DLUT_17CUBE = 0x00000000, -CMC_3DLUT_9CUBE = 0x00000001, -} CMC_3DLUT_SIZE_ENUM; - -/* - * CMC_LUT_2_CONFIG_ENUM enum - */ - -typedef enum CMC_LUT_2_CONFIG_ENUM { -CMC_LUT_2CFG_NO_MEMORY = 0x00000000, -CMC_LUT_2CFG_MEMORY_A = 0x00000001, -CMC_LUT_2CFG_MEMORY_B = 0x00000002, -} CMC_LUT_2_CONFIG_ENUM; - -/* - * CMC_LUT_2_MODE_ENUM enum - */ - -typedef enum CMC_LUT_2_MODE_ENUM { -CMC_LUT_2_MODE_BYPASS = 0x00000000, -CMC_LUT_2_MODE_RAMA_LUT = 0x00000001, -CMC_LUT_2_MODE_RAMB_LUT = 0x00000002, -} CMC_LUT_2_MODE_ENUM; - -/* - * CMC_LUT_NUM_SEG enum - */ - -typedef enum CMC_LUT_NUM_SEG { -CMC_SEGMENTS_1 = 0x00000000, -CMC_SEGMENTS_2 = 0x00000001, -CMC_SEGMENTS_4 = 0x00000002, -CMC_SEGMENTS_8 = 0x00000003, -CMC_SEGMENTS_16 = 0x00000004, -CMC_SEGMENTS_32 = 0x00000005, -CMC_SEGMENTS_64 = 0x00000006, -CMC_SEGMENTS_128 = 0x00000007, -} CMC_LUT_NUM_SEG; - -/* - * CMC_LUT_RAM_SEL enum - */ - -typedef enum CMC_LUT_RAM_SEL { -CMC_RAMA_ACCESS = 0x00000000, -CMC_RAMB_ACCESS = 0x00000001, -} CMC_LUT_RAM_SEL; - -/* - * CM_BYPASS enum - */ - -typedef enum CM_BYPASS { -NON_BYPASS = 0x00000000, -BYPASS_EN = 0x00000001, -} CM_BYPASS; - -/* - * CM_COEF_FORMAT_ENUM enum - */ - -typedef enum CM_COEF_FORMAT_ENUM { -FIX_S2_13 = 0x00000000, -FIX_S3_12 = 0x00000001, -} CM_COEF_FORMAT_ENUM; - -/* - * CM_DATA_SIGNED enum - */ - -typedef enum CM_DATA_SIGNED { -UNSIGNED = 0x00000000, -SIGNED = 0x00000001, -} CM_DATA_SIGNED; - -/* - * CM_EN enum - */ - -typedef enum CM_EN { -CM_DISABLE = 0x00000000, -CM_ENABLE = 0x00000001, -} CM_EN; - -/* - * CM_GAMMA_LUT_MODE_ENUM enum - */ - -typedef enum CM_GAMMA_LUT_MODE_ENUM { -BYPASS = 0x00000000, -RESERVED_1 = 0x00000001, -RAM_LUT = 0x00000002, -RESERVED_3 = 0x00000003, -} CM_GAMMA_LUT_MODE_ENUM; - -/* - * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum - */ - -typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM { -ENABLE_PWL = 0x00000000, -DISABLE_PWL = 0x00000001, -} CM_GAMMA_LUT_PWL_DISABLE_ENUM; - -/* - * CM_GAMMA_LUT_SEL_ENUM enum - */ - -typedef enum CM_GAMMA_LUT_SEL_ENUM { -RAMA = 0x00000000, -RAMB = 0x00000001, -} CM_GAMMA_LUT_SEL_ENUM; - -/* - * CM_GAMUT_REMAP_MODE_ENUM enum - */ - -typedef enum CM_GAMUT_REMAP_MODE_ENUM { -BYPASS_GAMUT = 0x00000000, -GAMUT_COEF = 0x00000001, -GAMUT_COEF_B = 0x00000002, -} CM_GAMUT_REMAP_MODE_ENUM; - -/* - * CM_LUT_2_CONFIG_ENUM enum - */ - -typedef enum CM_LUT_2_CONFIG_ENUM { -LUT_2CFG_NO_MEMORY = 0x00000000, -LUT_2CFG_MEMORY_A = 0x00000001, -LUT_2CFG_MEMORY_B = 0x00000002, -} CM_LUT_2_CONFIG_ENUM; - -/* - * CM_LUT_2_MODE_ENUM enum - */ - -typedef enum CM_LUT_2_MODE_ENUM { -LUT_2_MODE_BYPASS = 0x00000000, -LUT_2_MODE_RAMA_LUT = 0x00000001, -LUT_2_MODE_RAMB_LUT = 0x00000002, -} CM_LUT_2_MODE_ENUM; - -/* - * CM_LUT_4_CONFIG_ENUM enum - */ - -typedef enum CM_LUT_4_CONFIG_ENUM { -LUT_4CFG_NO_MEMORY = 0x00000000, -LUT_4CFG_ROM_A = 0x00000001, -LUT_4CFG_ROM_B = 0x00000002, -LUT_4CFG_MEMORY_A = 0x00000003, -LUT_4CFG_MEMORY_B = 0x00000004, -} CM_LUT_4_CONFIG_ENUM; - -/* - * CM_LUT_4_MODE_ENUM enum - */ - -typedef enum CM_LUT_4_MODE_ENUM { -LUT_4_MODE_BYPASS = 0x00000000, -LUT_4_MODE_ROMA_LUT = 0x00000001, -LUT_4_MODE_ROMB_LUT = 0x00000002, -LUT_4_MODE_RAMA_LUT = 0x00000003, -LUT_4_MODE_RAMB_LUT = 0x00000004, -} CM_LUT_4_MODE_ENUM; - -/* - * CM_LUT_CONFIG_MODE enum - */ - -typedef enum CM_LUT_CONFIG_MODE { -DIFFERENT_RGB = 0x00000000, -ALL_USE_R = 0x00000001, -} CM_LUT_CONFIG_MODE; - -/* - * CM_LUT_NUM_SEG enum - */ - -typedef enum CM_LUT_NUM_SEG { -SEGMENTS_1 = 0x00000000, -SEGMENTS_2 = 0x00000001, -SEGMENTS_4 = 0x00000002, -SEGMENTS_8 = 0x00000003, -SEGMENTS_16 = 0x00000004, -SEGMENTS_32 = 0x00000005, -SEGMENTS_64 = 0x00000006, -SEGMENTS_128 = 0x00000007, -} CM_LUT_NUM_SEG; - -/* - * CM_LUT_RAM_SEL enum - */ - -typedef enum CM_LUT_RAM_SEL { -RAMA_ACCESS = 0x00000000, -RAMB_ACCESS = 0x00000001, -} CM_LUT_RAM_SEL; - -/* - * CM_LUT_READ_COLOR_SEL enum - */ - -typedef enum CM_LUT_READ_COLOR_SEL { -BLUE_LUT = 0x00000000, -GREEN_LUT = 0x00000001, -RED_LUT = 0x00000002, -} CM_LUT_READ_COLOR_SEL; - -/* - * CM_LUT_READ_DBG enum - */ - -typedef enum CM_LUT_READ_DBG { -DISABLE_DEBUG = 0x00000000, -ENABLE_DEBUG = 0x00000001, -} CM_LUT_READ_DBG; - -/* - * CM_PENDING enum - */ - -typedef enum CM_PENDING { -CM_NOT_PENDING = 0x00000000, -CM_YES_PENDING = 0x00000001, -} CM_PENDING; - -/* - * CM_POST_CSC_MODE_ENUM enum - */ - -typedef enum CM_POST_CSC_MODE_ENUM { -BYPASS_POST_CSC = 0x00000000, -COEF_POST_CSC = 0x00000001, -COEF_POST_CSC_B = 0x00000002, -} CM_POST_CSC_MODE_ENUM; - -/* - * CM_WRITE_BASE_ONLY enum - */ - -typedef enum CM_WRITE_BASE_ONLY { -WRITE_BOTH = 0x00000000, -WRITE_BASE_ONLY = 0x00000001, -} CM_WRITE_BASE_ONLY; - -/******************************************************* - * DPP_TOP Enums - *******************************************************/ - -/* - * CRC_CUR_SEL enum - */ - -typedef enum CRC_CUR_SEL { -CRC_CUR_0 = 0x00000000, -CRC_CUR_1 = 0x00000001, -} CRC_CUR_SEL; - -/* - * CRC_INTERLACE_SEL enum - */ - -typedef enum CRC_INTERLACE_SEL { -CRC_INTERLACE_0 = 0x00000000, -CRC_INTERLACE_1 = 0x00000001, -CRC_INTERLACE_2 = 0x00000002, -CRC_INTERLACE_3 = 0x00000003, -} CRC_INTERLACE_SEL; - -/* - * CRC_IN_CUR_SEL enum - */ - -typedef enum CRC_IN_CUR_SEL { -CRC_IN_CUR_0 = 0x00000000, -CRC_IN_CUR_1 = 0x00000001, -CRC_IN_CUR_2 = 0x00000002, -CRC_IN_CUR_3 = 0x00000003, -} CRC_IN_CUR_SEL; - -/* - * CRC_IN_PIX_SEL enum - */ - -typedef enum CRC_IN_PIX_SEL { -CRC_IN_PIX_0 = 0x00000000, -CRC_IN_PIX_1 = 0x00000001, -CRC_IN_PIX_2 = 0x00000002, -CRC_IN_PIX_3 = 0x00000003, -CRC_IN_PIX_4 = 0x00000004, -CRC_IN_PIX_5 = 0x00000005, -CRC_IN_PIX_6 = 0x00000006, -CRC_IN_PIX_7 = 0x00000007, -} CRC_IN_PIX_SEL; - -/* - * CRC_SRC_SEL enum - */ - -typedef enum CRC_SRC_SEL { -CRC_SRC_0 = 0x00000000, -CRC_SRC_1 = 0x00000001, -CRC_SRC_2 = 0x00000002, -CRC_SRC_3 = 0x00000003, -} CRC_SRC_SEL; - -/* - * CRC_STEREO_SEL enum - */ - -typedef enum CRC_STEREO_SEL { -CRC_STEREO_0 = 0x00000000, -CRC_STEREO_1 = 0x00000001, -CRC_STEREO_2 = 0x00000002, -CRC_STEREO_3 = 0x00000003, -} CRC_STEREO_SEL; - -/* - * TEST_CLK_SEL enum - */ - -typedef enum TEST_CLK_SEL { -TEST_CLK_SEL_0 = 0x00000000, -TEST_CLK_SEL_1 = 0x00000001, -TEST_CLK_SEL_2 = 0x00000002, -TEST_CLK_SEL_3 = 0x00000003, -TEST_CLK_SEL_4 = 0x00000004, -TEST_CLK_SEL_5 = 0x00000005, -TEST_CLK_SEL_6 = 0x00000006, -TEST_CLK_SEL_7 = 0x00000007, -} TEST_CLK_SEL; - -/******************************************************* - * DC_PERFMON Enums - *******************************************************/ - -/* - * PERFCOUNTER_ACTIVE enum - */ - -typedef enum PERFCOUNTER_ACTIVE { -PERFCOUNTER_IS_IDLE = 0x00000000, -PERFCOUNTER_IS_ACTIVE = 0x00000001, -} PERFCOUNTER_ACTIVE; - -/* - * PERFCOUNTER_CNT0_STATE enum - */ - -typedef enum PERFCOUNTER_CNT0_STATE { -PERFCOUNTER_CNT0_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT0_STATE_START = 0x00000001, -PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT0_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT0_STATE; - -/* - * PERFCOUNTER_CNT1_STATE enum - */ - -typedef enum PERFCOUNTER_CNT1_STATE { -PERFCOUNTER_CNT1_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT1_STATE_START = 0x00000001, -PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT1_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT1_STATE; - -/* - * PERFCOUNTER_CNT2_STATE enum - */ - -typedef enum PERFCOUNTER_CNT2_STATE { -PERFCOUNTER_CNT2_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT2_STATE_START = 0x00000001, -PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT2_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT2_STATE; - -/* - * PERFCOUNTER_CNT3_STATE enum - */ - -typedef enum PERFCOUNTER_CNT3_STATE { -PERFCOUNTER_CNT3_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT3_STATE_START = 0x00000001, -PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT3_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT3_STATE; - -/* - * PERFCOUNTER_CNT4_STATE enum - */ - -typedef enum PERFCOUNTER_CNT4_STATE { -PERFCOUNTER_CNT4_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT4_STATE_START = 0x00000001, -PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT4_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT4_STATE; - -/* - * PERFCOUNTER_CNT5_STATE enum - */ - -typedef enum PERFCOUNTER_CNT5_STATE { -PERFCOUNTER_CNT5_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT5_STATE_START = 0x00000001, -PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT5_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT5_STATE; - -/* - * PERFCOUNTER_CNT6_STATE enum - */ - -typedef enum PERFCOUNTER_CNT6_STATE { -PERFCOUNTER_CNT6_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT6_STATE_START = 0x00000001, -PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT6_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT6_STATE; - -/* - * PERFCOUNTER_CNT7_STATE enum - */ - -typedef enum PERFCOUNTER_CNT7_STATE { -PERFCOUNTER_CNT7_STATE_RESET = 0x00000000, -PERFCOUNTER_CNT7_STATE_START = 0x00000001, -PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002, -PERFCOUNTER_CNT7_STATE_HW = 0x00000003, -} PERFCOUNTER_CNT7_STATE; - -/* - * PERFCOUNTER_CNTL_SEL enum - */ - -typedef enum PERFCOUNTER_CNTL_SEL { -PERFCOUNTER_CNTL_SEL_0 = 0x00000000, -PERFCOUNTER_CNTL_SEL_1 = 0x00000001, -PERFCOUNTER_CNTL_SEL_2 = 0x00000002, -PERFCOUNTER_CNTL_SEL_3 = 0x00000003, -PERFCOUNTER_CNTL_SEL_4 = 0x00000004, -PERFCOUNTER_CNTL_SEL_5 = 0x00000005, -PERFCOUNTER_CNTL_SEL_6 = 0x00000006, -PERFCOUNTER_CNTL_SEL_7 = 0x00000007, -} PERFCOUNTER_CNTL_SEL; - -/* - * PERFCOUNTER_CNTOFF_START_DIS enum - */ - -typedef enum PERFCOUNTER_CNTOFF_START_DIS { -PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000, -PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001, -} PERFCOUNTER_CNTOFF_START_DIS; - -/* - * PERFCOUNTER_COUNTED_VALUE_TYPE enum - */ - -typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000, -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001, -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002, -} PERFCOUNTER_COUNTED_VALUE_TYPE; - -/* - * PERFCOUNTER_CVALUE_SEL enum - */ - -typedef enum PERFCOUNTER_CVALUE_SEL { -PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000, -PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001, -PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002, -PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003, -PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004, -PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005, -PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006, -PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007, -} PERFCOUNTER_CVALUE_SEL; - -/* - * PERFCOUNTER_HW_CNTL_SEL enum - */ - -typedef enum PERFCOUNTER_HW_CNTL_SEL { -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000, -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001, -} PERFCOUNTER_HW_CNTL_SEL; - -/* - * PERFCOUNTER_HW_STOP1_SEL enum - */ - -typedef enum PERFCOUNTER_HW_STOP1_SEL { -PERFCOUNTER_HW_STOP1_0 = 0x00000000, -PERFCOUNTER_HW_STOP1_1 = 0x00000001, -} PERFCOUNTER_HW_STOP1_SEL; - -/* - * PERFCOUNTER_HW_STOP2_SEL enum - */ - -typedef enum PERFCOUNTER_HW_STOP2_SEL { -PERFCOUNTER_HW_STOP2_0 = 0x00000000, -PERFCOUNTER_HW_STOP2_1 = 0x00000001, -} PERFCOUNTER_HW_STOP2_SEL; - -/* - * PERFCOUNTER_INC_MODE enum - */ - -typedef enum PERFCOUNTER_INC_MODE { -PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000, -PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001, -PERFCOUNTER_INC_MODE_LSB = 0x00000002, -PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003, -PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004, -} PERFCOUNTER_INC_MODE; - -/* - * PERFCOUNTER_INT_EN enum - */ - -typedef enum PERFCOUNTER_INT_EN { -PERFCOUNTER_INT_DISABLE = 0x00000000, -PERFCOUNTER_INT_ENABLE = 0x00000001, -} PERFCOUNTER_INT_EN; - -/* - * PERFCOUNTER_INT_TYPE enum - */ - -typedef enum PERFCOUNTER_INT_TYPE { -PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000, -PERFCOUNTER_INT_TYPE_PULSE = 0x00000001, -} PERFCOUNTER_INT_TYPE; - -/* - * PERFCOUNTER_OFF_MASK enum - */ - -typedef enum PERFCOUNTER_OFF_MASK { -PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000, -PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001, -} PERFCOUNTER_OFF_MASK; - -/* - * PERFCOUNTER_RESTART_EN enum - */ - -typedef enum PERFCOUNTER_RESTART_EN { -PERFCOUNTER_RESTART_DISABLE = 0x00000000, -PERFCOUNTER_RESTART_ENABLE = 0x00000001, -} PERFCOUNTER_RESTART_EN; - -/* - * PERFCOUNTER_RUNEN_MODE enum - */ - -typedef enum PERFCOUNTER_RUNEN_MODE { -PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000, -PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001, -} PERFCOUNTER_RUNEN_MODE; - -/* - * PERFCOUNTER_STATE_SEL0 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL0 { -PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL0; - -/* - * PERFCOUNTER_STATE_SEL1 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL1 { -PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL1; - -/* - * PERFCOUNTER_STATE_SEL2 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL2 { -PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL2; - -/* - * PERFCOUNTER_STATE_SEL3 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL3 { -PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL3; - -/* - * PERFCOUNTER_STATE_SEL4 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL4 { -PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL4; - -/* - * PERFCOUNTER_STATE_SEL5 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL5 { -PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL5; - -/* - * PERFCOUNTER_STATE_SEL6 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL6 { -PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL6; - -/* - * PERFCOUNTER_STATE_SEL7 enum - */ - -typedef enum PERFCOUNTER_STATE_SEL7 { -PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000, -PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001, -} PERFCOUNTER_STATE_SEL7; - -/* - * PERFMON_CNTOFF_AND_OR enum - */ - -typedef enum PERFMON_CNTOFF_AND_OR { -PERFMON_CNTOFF_OR = 0x00000000, -PERFMON_CNTOFF_AND = 0x00000001, -} PERFMON_CNTOFF_AND_OR; - -/* - * PERFMON_CNTOFF_INT_EN enum - */ - -typedef enum PERFMON_CNTOFF_INT_EN { -PERFMON_CNTOFF_INT_DISABLE = 0x00000000, -PERFMON_CNTOFF_INT_ENABLE = 0x00000001, -} PERFMON_CNTOFF_INT_EN; - -/* - * PERFMON_CNTOFF_INT_TYPE enum - */ - -typedef enum PERFMON_CNTOFF_INT_TYPE { -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000, -PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001, -} PERFMON_CNTOFF_INT_TYPE; - -/* - * PERFMON_STATE enum - */ - -typedef enum PERFMON_STATE { -PERFMON_STATE_RESET = 0x00000000, -PERFMON_STATE_START = 0x00000001, -PERFMON_STATE_FREEZE = 0x00000002, -PERFMON_STATE_HW = 0x00000003, -} PERFMON_STATE; - -/******************************************************* - * HUBP Enums - *******************************************************/ - -/* - * BIGK_FRAGMENT_SIZE enum - */ - -typedef enum BIGK_FRAGMENT_SIZE { -VM_PG_SIZE_4KB = 0x00000000, -VM_PG_SIZE_8KB = 0x00000001, -VM_PG_SIZE_16KB = 0x00000002, -VM_PG_SIZE_32KB = 0x00000003, -VM_PG_SIZE_64KB = 0x00000004, -VM_PG_SIZE_128KB = 0x00000005, -VM_PG_SIZE_256KB = 0x00000006, -VM_PG_SIZE_512KB = 0x00000007, -VM_PG_SIZE_1024KB = 0x00000008, -VM_PG_SIZE_2048KB = 0x00000009, -} BIGK_FRAGMENT_SIZE; - -/* - * CHUNK_SIZE enum - */ - -typedef enum CHUNK_SIZE { -CHUNK_SIZE_1KB = 0x00000000, -CHUNK_SIZE_2KB = 0x00000001, -CHUNK_SIZE_4KB = 0x00000002, -CHUNK_SIZE_8KB = 0x00000003, -CHUNK_SIZE_16KB = 0x00000004, -CHUNK_SIZE_32KB = 0x00000005, -CHUNK_SIZE_64KB = 0x00000006, -} CHUNK_SIZE; - -/* - * COMPAT_LEVEL enum - */ - -typedef enum COMPAT_LEVEL { -ADDR_GEN_ZERO = 0x00000000, -ADDR_GEN_ONE = 0x00000001, -ADDR_GEN_TWO = 0x00000002, -ADDR_RESERVED = 0x00000003, -} COMPAT_LEVEL; - -/* - * DPTE_GROUP_SIZE enum - */ - -typedef enum DPTE_GROUP_SIZE { -DPTE_GROUP_SIZE_64B = 0x00000000, -DPTE_GROUP_SIZE_128B = 0x00000001, -DPTE_GROUP_SIZE_256B = 0x00000002, -DPTE_GROUP_SIZE_512B = 0x00000003, -DPTE_GROUP_SIZE_1024B = 0x00000004, -DPTE_GROUP_SIZE_2048B = 0x00000005, -} DPTE_GROUP_SIZE; - -/* - * FORCE_ONE_ROW_FOR_FRAME enum - */ - -typedef enum FORCE_ONE_ROW_FOR_FRAME { -FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000, -FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001, -} FORCE_ONE_ROW_FOR_FRAME; - -/* - * HUBP_BLANK_EN enum - */ - -typedef enum HUBP_BLANK_EN { -HUBP_BLANK_SW_DEASSERT = 0x00000000, -HUBP_BLANK_SW_ASSERT = 0x00000001, -} HUBP_BLANK_EN; - -/* - * HUBP_IN_BLANK enum - */ - -typedef enum HUBP_IN_BLANK { -HUBP_IN_ACTIVE = 0x00000000, -HUBP_IN_VBLANK = 0x00000001, -} HUBP_IN_BLANK; - -/* - * HUBP_MEASURE_WIN_MODE_DCFCLK enum - */ - -typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK { -HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000, -HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001, -HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002, -HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003, -} HUBP_MEASURE_WIN_MODE_DCFCLK; - -/* - * HUBP_NO_OUTSTANDING_REQ enum - */ - -typedef enum HUBP_NO_OUTSTANDING_REQ { -OUTSTANDING_REQ = 0x00000000, -NO_OUTSTANDING_REQ = 0x00000001, -} HUBP_NO_OUTSTANDING_REQ; - -/* - * HUBP_SOFT_RESET enum - */ - -typedef enum HUBP_SOFT_RESET { -HUBP_SOFT_RESET_ON = 0x00000000, -HUBP_SOFT_RESET_OFF = 0x00000001, -} HUBP_SOFT_RESET; - -/* - * HUBP_TTU_DISABLE enum - */ - -typedef enum HUBP_TTU_DISABLE { -HUBP_TTU_ENABLED = 0x00000000, -HUBP_TTU_DISABLED = 0x00000001, -} HUBP_TTU_DISABLE; - -/* - * HUBP_VREADY_AT_OR_AFTER_VSYNC enum - */ - -typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC { -VREADY_BEFORE_VSYNC = 0x00000000, -VREADY_AT_OR_AFTER_VSYNC = 0x00000001, -} HUBP_VREADY_AT_OR_AFTER_VSYNC; - -/* - * HUBP_VTG_SEL enum - */ - -typedef enum HUBP_VTG_SEL { -VTG_SEL_0 = 0x00000000, -VTG_SEL_1 = 0x00000001, -VTG_SEL_2 = 0x00000002, -VTG_SEL_3 = 0x00000003, -VTG_SEL_4 = 0x00000004, -VTG_SEL_5 = 0x00000005, -} HUBP_VTG_SEL; - -/* - * H_MIRROR_EN enum - */ - -typedef enum H_MIRROR_EN { -HW_MIRRORING_DISABLE = 0x00000000, -HW_MIRRORING_ENABLE = 0x00000001, -} H_MIRROR_EN; - -/* - * LEGACY_PIPE_INTERLEAVE enum - */ - -typedef enum LEGACY_PIPE_INTERLEAVE { -LEGACY_PIPE_INTERLEAVE_256B = 0x00000000, -LEGACY_PIPE_INTERLEAVE_512B = 0x00000001, -} LEGACY_PIPE_INTERLEAVE; - -/* - * META_CHUNK_SIZE enum - */ - -typedef enum META_CHUNK_SIZE { -META_CHUNK_SIZE_1KB = 0x00000000, -META_CHUNK_SIZE_2KB = 0x00000001, -META_CHUNK_SIZE_4KB = 0x00000002, -META_CHUNK_SIZE_8KB = 0x00000003, -} META_CHUNK_SIZE; - -/* - * META_LINEAR enum - */ - -typedef enum META_LINEAR { -META_SURF_TILED = 0x00000000, -META_SURF_LINEAR = 0x00000001, -} META_LINEAR; - -/* - * MIN_CHUNK_SIZE enum - */ - -typedef enum MIN_CHUNK_SIZE { -NO_MIN_CHUNK_SIZE = 0x00000000, -MIN_CHUNK_SIZE_256B = 0x00000001, -MIN_CHUNK_SIZE_512B = 0x00000002, -MIN_CHUNK_SIZE_1024B = 0x00000003, -} MIN_CHUNK_SIZE; - -/* - * MIN_META_CHUNK_SIZE enum - */ - -typedef enum MIN_META_CHUNK_SIZE { -NO_MIN_META_CHUNK_SIZE = 0x00000000, -MIN_META_CHUNK_SIZE_64B = 0x00000001, -MIN_META_CHUNK_SIZE_128B = 0x00000002, -MIN_META_CHUNK_SIZE_256B = 0x00000003, -} MIN_META_CHUNK_SIZE; - -/* - * PIPE_ALIGNED enum - */ - -typedef enum PIPE_ALIGNED { -PIPE_UNALIGNED_SURF = 0x00000000, -PIPE_ALIGNED_SURF = 0x00000001, -} PIPE_ALIGNED; - -/* - * PTE_BUFFER_MODE enum - */ - -typedef enum PTE_BUFFER_MODE { -PTE_BUFFER_MODE_0 = 0x00000000, -PTE_BUFFER_MODE_1 = 0x00000001, -} PTE_BUFFER_MODE; - -/* - * PTE_ROW_HEIGHT_LINEAR enum - */ - -typedef enum PTE_ROW_HEIGHT_LINEAR { -PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000, -PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001, -PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002, -PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003, -PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004, -PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005, -PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006, -PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007, -} PTE_ROW_HEIGHT_LINEAR; - -/* - * ROTATION_ANGLE enum - */ - -typedef enum ROTATION_ANGLE { -ROTATE_0_DEGREES = 0x00000000, -ROTATE_90_DEGREES = 0x00000001, -ROTATE_180_DEGREES = 0x00000002, -ROTATE_270_DEGREES = 0x00000003, -} ROTATION_ANGLE; - -/* - * SWATH_HEIGHT enum - */ - -typedef enum SWATH_HEIGHT { -SWATH_HEIGHT_1L = 0x00000000, -SWATH_HEIGHT_2L = 0x00000001, -SWATH_HEIGHT_4L = 0x00000002, -SWATH_HEIGHT_8L = 0x00000003, -SWATH_HEIGHT_16L = 0x00000004, -} SWATH_HEIGHT; - -/* - * USE_MALL_FOR_CURSOR enum - */ - -typedef enum USE_MALL_FOR_CURSOR { -USE_MALL_FOR_CURSOR_0 = 0x00000000, -USE_MALL_FOR_CURSOR_1 = 0x00000001, -} USE_MALL_FOR_CURSOR; - -/* - * USE_MALL_FOR_PSTATE_CHANGE enum - */ - -typedef enum USE_MALL_FOR_PSTATE_CHANGE { -USE_MALL_FOR_PSTATE_CHANGE_0 = 0x00000000, -USE_MALL_FOR_PSTATE_CHANGE_1 = 0x00000001, -} USE_MALL_FOR_PSTATE_CHANGE; - -/* - * USE_MALL_FOR_STATIC_SCREEN enum - */ - -typedef enum USE_MALL_FOR_STATIC_SCREEN { -USE_MALL_FOR_STATIC_SCREEN_0 = 0x00000000, -USE_MALL_FOR_STATIC_SCREEN_1 = 0x00000001, -} USE_MALL_FOR_STATIC_SCREEN; - -/* - * VMPG_SIZE enum - */ - -typedef enum VMPG_SIZE { -VMPG_SIZE_4KB = 0x00000000, -VMPG_SIZE_64KB = 0x00000001, -} VMPG_SIZE; - -/* - * VM_GROUP_SIZE enum - */ - -typedef enum VM_GROUP_SIZE { -VM_GROUP_SIZE_64B = 0x00000000, -VM_GROUP_SIZE_128B = 0x00000001, -VM_GROUP_SIZE_256B = 0x00000002, -VM_GROUP_SIZE_512B = 0x00000003, -VM_GROUP_SIZE_1024B = 0x00000004, -VM_GROUP_SIZE_2048B = 0x00000005, -} VM_GROUP_SIZE; - -/******************************************************* - * HUBPREQ Enums - *******************************************************/ - -/* - * DFQ_MIN_FREE_ENTRIES enum - */ - -typedef enum DFQ_MIN_FREE_ENTRIES { -DFQ_MIN_FREE_ENTRIES_0 = 0x00000000, -DFQ_MIN_FREE_ENTRIES_1 = 0x00000001, -DFQ_MIN_FREE_ENTRIES_2 = 0x00000002, -DFQ_MIN_FREE_ENTRIES_3 = 0x00000003, -DFQ_MIN_FREE_ENTRIES_4 = 0x00000004, -DFQ_MIN_FREE_ENTRIES_5 = 0x00000005, -DFQ_MIN_FREE_ENTRIES_6 = 0x00000006, -DFQ_MIN_FREE_ENTRIES_7 = 0x00000007, -} DFQ_MIN_FREE_ENTRIES; - -/* - * DFQ_NUM_ENTRIES enum - */ - -typedef enum DFQ_NUM_ENTRIES { -DFQ_NUM_ENTRIES_0 = 0x00000000, -DFQ_NUM_ENTRIES_1 = 0x00000001, -DFQ_NUM_ENTRIES_2 = 0x00000002, -DFQ_NUM_ENTRIES_3 = 0x00000003, -DFQ_NUM_ENTRIES_4 = 0x00000004, -DFQ_NUM_ENTRIES_5 = 0x00000005, -DFQ_NUM_ENTRIES_6 = 0x00000006, -DFQ_NUM_ENTRIES_7 = 0x00000007, -DFQ_NUM_ENTRIES_8 = 0x00000008, -} DFQ_NUM_ENTRIES; - -/* - * DFQ_SIZE enum - */ - -typedef enum DFQ_SIZE { -DFQ_SIZE_0 = 0x00000000, -DFQ_SIZE_1 = 0x00000001, -DFQ_SIZE_2 = 0x00000002, -DFQ_SIZE_3 = 0x00000003, -DFQ_SIZE_4 = 0x00000004, -DFQ_SIZE_5 = 0x00000005, -DFQ_SIZE_6 = 0x00000006, -DFQ_SIZE_7 = 0x00000007, -} DFQ_SIZE; - -/* - * DMDATA_VM_DONE enum - */ - -typedef enum DMDATA_VM_DONE { -DMDATA_VM_IS_NOT_DONE = 0x00000000, -DMDATA_VM_IS_DONE = 0x00000001, -} DMDATA_VM_DONE; - -/* - * EXPANSION_MODE enum - */ - -typedef enum EXPANSION_MODE { -EXPANSION_MODE_ZERO = 0x00000000, -EXPANSION_MODE_CONSERVATIVE = 0x00000001, -EXPANSION_MODE_OPTIMAL = 0x00000002, -} EXPANSION_MODE; - -/* - * FLIP_RATE enum - */ - -typedef enum FLIP_RATE { -FLIP_RATE_0 = 0x00000000, -FLIP_RATE_1 = 0x00000001, -FLIP_RATE_2 = 0x00000002, -FLIP_RATE_3 = 0x00000003, -FLIP_RATE_4 = 0x00000004, -FLIP_RATE_5 = 0x00000005, -FLIP_RATE_6 = 0x00000006, -FLIP_RATE_7 = 0x00000007, -} FLIP_RATE; - -/* - * INT_MASK enum - */ - -typedef enum INT_MASK { -INT_DISABLED = 0x00000000, -INT_ENABLED = 0x00000001, -} INT_MASK; - -/* - * PIPE_IN_FLUSH_URGENT enum - */ - -typedef enum PIPE_IN_FLUSH_URGENT { -PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000, -PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001, -} PIPE_IN_FLUSH_URGENT; - -/* - * PRQ_MRQ_FLUSH_URGENT enum - */ - -typedef enum PRQ_MRQ_FLUSH_URGENT { -PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000, -PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001, -} PRQ_MRQ_FLUSH_URGENT; - -/* - * ROW_TTU_MODE enum - */ - -typedef enum ROW_TTU_MODE { -END_OF_ROW_MODE = 0x00000000, -WATERMARK_MODE = 0x00000001, -} ROW_TTU_MODE; - -/* - * SURFACE_DCC enum - */ - -typedef enum SURFACE_DCC { -SURFACE_IS_NOT_DCC = 0x00000000, -SURFACE_IS_DCC = 0x00000001, -} SURFACE_DCC; - -/* - * SURFACE_DCC_IND_128B enum - */ - -typedef enum SURFACE_DCC_IND_128B { -SURFACE_DCC_IS_NOT_IND_128B = 0x00000000, -SURFACE_DCC_IS_IND_128B = 0x00000001, -} SURFACE_DCC_IND_128B; - -/* - * SURFACE_DCC_IND_64B enum - */ - -typedef enum SURFACE_DCC_IND_64B { -SURFACE_DCC_IS_NOT_IND_64B = 0x00000000, -SURFACE_DCC_IS_IND_64B = 0x00000001, -} SURFACE_DCC_IND_64B; - -/* - * SURFACE_DCC_IND_BLK enum - */ - -typedef enum SURFACE_DCC_IND_BLK { -SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000, -SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001, -SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002, -SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003, -} SURFACE_DCC_IND_BLK; - -/* - * SURFACE_FLIP_AWAY_INT_TYPE enum - */ - -typedef enum SURFACE_FLIP_AWAY_INT_TYPE { -SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000, -SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001, -} SURFACE_FLIP_AWAY_INT_TYPE; - -/* - * SURFACE_FLIP_EXEC_DEBUG_MODE enum - */ - -typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE { -SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000, -SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001, -} SURFACE_FLIP_EXEC_DEBUG_MODE; - -/* - * SURFACE_FLIP_INT_TYPE enum - */ - -typedef enum SURFACE_FLIP_INT_TYPE { -SURFACE_FLIP_INT_LEVEL = 0x00000000, -SURFACE_FLIP_INT_PULSE = 0x00000001, -} SURFACE_FLIP_INT_TYPE; - -/* - * SURFACE_FLIP_IN_STEREOSYNC enum - */ - -typedef enum SURFACE_FLIP_IN_STEREOSYNC { -SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000, -SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001, -} SURFACE_FLIP_IN_STEREOSYNC; - -/* - * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum - */ - -typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC { -FLIP_ANY_FRAME = 0x00000000, -FLIP_LEFT_EYE = 0x00000001, -FLIP_RIGHT_EYE = 0x00000002, -SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003, -} SURFACE_FLIP_MODE_FOR_STEREOSYNC; - -/* - * SURFACE_FLIP_STEREO_SELECT_DISABLE enum - */ - -typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE { -SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000, -SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001, -} SURFACE_FLIP_STEREO_SELECT_DISABLE; - -/* - * SURFACE_FLIP_STEREO_SELECT_POLARITY enum - */ - -typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY { -SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000, -SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001, -} SURFACE_FLIP_STEREO_SELECT_POLARITY; - -/* - * SURFACE_FLIP_TYPE enum - */ - -typedef enum SURFACE_FLIP_TYPE { -SURFACE_V_FLIP = 0x00000000, -SURFACE_I_FLIP = 0x00000001, -} SURFACE_FLIP_TYPE; - -/* - * SURFACE_FLIP_VUPDATE_SKIP_NUM enum - */ - -typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM { -SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000, -SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001, -SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002, -SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003, -SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004, -SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005, -SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006, -SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007, -SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008, -SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009, -SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a, -SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b, -SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c, -SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d, -SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e, -SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f, -} SURFACE_FLIP_VUPDATE_SKIP_NUM; - -/* - * SURFACE_INUSE_RAED_NO_LATCH enum - */ - -typedef enum SURFACE_INUSE_RAED_NO_LATCH { -SURFACE_INUSE_IS_LATCHED = 0x00000000, -SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001, -} SURFACE_INUSE_RAED_NO_LATCH; - -/* - * SURFACE_TMZ enum - */ - -typedef enum SURFACE_TMZ { -SURFACE_IS_NOT_TMZ = 0x00000000, -SURFACE_IS_TMZ = 0x00000001, -} SURFACE_TMZ; - -/* - * SURFACE_UPDATE_LOCK enum - */ - -typedef enum SURFACE_UPDATE_LOCK { -SURFACE_UPDATE_IS_UNLOCKED = 0x00000000, -SURFACE_UPDATE_IS_LOCKED = 0x00000001, -} SURFACE_UPDATE_LOCK; - -/******************************************************* - * HUBPRET Enums - *******************************************************/ - -/* - * CROSSBAR_FOR_ALPHA enum - */ - -typedef enum CROSSBAR_FOR_ALPHA { -ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000, -Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001, -CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002, -CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003, -} CROSSBAR_FOR_ALPHA; - -/* - * CROSSBAR_FOR_CB_B enum - */ - -typedef enum CROSSBAR_FOR_CB_B { -ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000, -Y_G_DATA_ONTO_CB_B_PORT = 0x00000001, -CB_B_DATA_ONTO_CB_B_PORT = 0x00000002, -CR_R_DATA_ONTO_CB_B_PORT = 0x00000003, -} CROSSBAR_FOR_CB_B; - -/* - * CROSSBAR_FOR_CR_R enum - */ - -typedef enum CROSSBAR_FOR_CR_R { -ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000, -Y_G_DATA_ONTO_CR_R_PORT = 0x00000001, -CB_B_DATA_ONTO_CR_R_PORT = 0x00000002, -CR_R_DATA_ONTO_CR_R_PORT = 0x00000003, -} CROSSBAR_FOR_CR_R; - -/* - * CROSSBAR_FOR_Y_G enum - */ - -typedef enum CROSSBAR_FOR_Y_G { -ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000, -Y_G_DATA_ONTO_Y_G_PORT = 0x00000001, -CB_B_DATA_ONTO_Y_G_PORT = 0x00000002, -CR_R_DATA_ONTO_Y_G_PORT = 0x00000003, -} CROSSBAR_FOR_Y_G; - -/* - * DETILE_BUFFER_PACKER_ENABLE enum - */ - -typedef enum DETILE_BUFFER_PACKER_ENABLE { -DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000, -DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001, -} DETILE_BUFFER_PACKER_ENABLE; - -/* - * MEM_PWR_DIS_MODE enum - */ - -typedef enum MEM_PWR_DIS_MODE { -MEM_POWER_DIS_MODE_ENABLE = 0x00000000, -MEM_POWER_DIS_MODE_DISABLE = 0x00000001, -} MEM_PWR_DIS_MODE; - -/* - * MEM_PWR_FORCE_MODE enum - */ - -typedef enum MEM_PWR_FORCE_MODE { -MEM_POWER_FORCE_MODE_OFF = 0x00000000, -MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001, -MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002, -MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003, -} MEM_PWR_FORCE_MODE; - -/* - * MEM_PWR_STATUS enum - */ - -typedef enum MEM_PWR_STATUS { -MEM_POWER_STATUS_ON = 0x00000000, -MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001, -MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002, -MEM_POWER_STATUS_SHUT_DOWN = 0x00000003, -} MEM_PWR_STATUS; - -/* - * PIPE_INT_MASK_MODE enum - */ - -typedef enum PIPE_INT_MASK_MODE { -PIPE_INT_MASK_MODE_DISABLE = 0x00000000, -PIPE_INT_MASK_MODE_ENABLE = 0x00000001, -} PIPE_INT_MASK_MODE; - -/* - * PIPE_INT_TYPE_MODE enum - */ - -typedef enum PIPE_INT_TYPE_MODE { -PIPE_INT_TYPE_MODE_DISABLE = 0x00000000, -PIPE_INT_TYPE_MODE_ENABLE = 0x00000001, -} PIPE_INT_TYPE_MODE; - -/* - * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum - */ - -typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE { -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, -} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; - -/******************************************************* - * CURSOR Enums - *******************************************************/ - -/* - * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum - */ - -typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE { -CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, -CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, -CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, -} CROB_MEM_PWR_LIGHT_SLEEP_MODE; - -/* - * CURSOR_2X_MAGNIFY enum - */ - -typedef enum CURSOR_2X_MAGNIFY { -CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000, -CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001, -} CURSOR_2X_MAGNIFY; - -/* - * CURSOR_ENABLE enum - */ - -typedef enum CURSOR_ENABLE { -CURSOR_IS_DISABLE = 0x00000000, -CURSOR_IS_ENABLE = 0x00000001, -} CURSOR_ENABLE; - -/* - * CURSOR_LINES_PER_CHUNK enum - */ - -typedef enum CURSOR_LINES_PER_CHUNK { -CURSOR_LINE_PER_CHUNK_1 = 0x00000000, -CURSOR_LINE_PER_CHUNK_2 = 0x00000001, -CURSOR_LINE_PER_CHUNK_4 = 0x00000002, -CURSOR_LINE_PER_CHUNK_8 = 0x00000003, -CURSOR_LINE_PER_CHUNK_16 = 0x00000004, -} CURSOR_LINES_PER_CHUNK; - -/* - * CURSOR_MODE enum - */ - -typedef enum CURSOR_MODE { -CURSOR_MONO_2BIT = 0x00000000, -CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001, -CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002, -CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003, -CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004, -CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005, -} CURSOR_MODE; - -/* - * CURSOR_PERFMON_LATENCY_MEASURE_EN enum - */ - -typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN { -CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000, -CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001, -} CURSOR_PERFMON_LATENCY_MEASURE_EN; - -/* - * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum - */ - -typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL { -CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000, -CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001, -} CURSOR_PERFMON_LATENCY_MEASURE_SEL; - -/* - * CURSOR_PITCH enum - */ - -typedef enum CURSOR_PITCH { -CURSOR_PITCH_64_PIXELS = 0x00000000, -CURSOR_PITCH_128_PIXELS = 0x00000001, -CURSOR_PITCH_256_PIXELS = 0x00000002, -} CURSOR_PITCH; - -/* - * CURSOR_REQ_MODE enum - */ - -typedef enum CURSOR_REQ_MODE { -CURSOR_REQUEST_NORMALLY = 0x00000000, -CURSOR_REQUEST_EARLY = 0x00000001, -} CURSOR_REQ_MODE; - -/* - * CURSOR_SNOOP enum - */ - -typedef enum CURSOR_SNOOP { -CURSOR_IS_NOT_SNOOP = 0x00000000, -CURSOR_IS_SNOOP = 0x00000001, -} CURSOR_SNOOP; - -/* - * CURSOR_STEREO_EN enum - */ - -typedef enum CURSOR_STEREO_EN { -CURSOR_STEREO_IS_DISABLED = 0x00000000, -CURSOR_STEREO_IS_ENABLED = 0x00000001, -} CURSOR_STEREO_EN; - -/* - * CURSOR_SURFACE_TMZ enum - */ - -typedef enum CURSOR_SURFACE_TMZ { -CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000, -CURSOR_SURFACE_IS_TMZ = 0x00000001, -} CURSOR_SURFACE_TMZ; - -/* - * CURSOR_SYSTEM enum - */ - -typedef enum CURSOR_SYSTEM { -CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000, -CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001, -} CURSOR_SYSTEM; - -/* - * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum - */ - -typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS { -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000, -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001, -} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; - -/* - * DMDATA_DONE enum - */ - -typedef enum DMDATA_DONE { -DMDATA_NOT_SENT_TO_DIG = 0x00000000, -DMDATA_SENT_TO_DIG = 0x00000001, -} DMDATA_DONE; - -/* - * DMDATA_MODE enum - */ - -typedef enum DMDATA_MODE { -DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000, -DMDATA_HARDWARE_UPDATE_MODE = 0x00000001, -} DMDATA_MODE; - -/* - * DMDATA_QOS_MODE enum - */ - -typedef enum DMDATA_QOS_MODE { -DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000, -DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001, -} DMDATA_QOS_MODE; - -/* - * DMDATA_REPEAT enum - */ - -typedef enum DMDATA_REPEAT { -DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000, -DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001, -} DMDATA_REPEAT; - -/* - * DMDATA_UNDERFLOW enum - */ - -typedef enum DMDATA_UNDERFLOW { -DMDATA_NOT_UNDERFLOW = 0x00000000, -DMDATA_UNDERFLOWED = 0x00000001, -} DMDATA_UNDERFLOW; - -/* - * DMDATA_UNDERFLOW_CLEAR enum - */ - -typedef enum DMDATA_UNDERFLOW_CLEAR { -DMDATA_DONT_CLEAR = 0x00000000, -DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001, -} DMDATA_UNDERFLOW_CLEAR; - -/* - * DMDATA_UPDATED enum - */ - -typedef enum DMDATA_UPDATED { -DMDATA_NOT_UPDATED = 0x00000000, -DMDATA_WAS_UPDATED = 0x00000001, -} DMDATA_UPDATED; - -/******************************************************* - * HUBBUB_SDPIF Enums - *******************************************************/ - -/* - * RESPONSE_STATUS enum - */ - -typedef enum RESPONSE_STATUS { -OKAY = 0x00000000, -EXOKAY = 0x00000001, -SLVERR = 0x00000002, -DECERR = 0x00000003, -EARLY = 0x00000004, -OKAY_NODATA = 0x00000005, -PROTVIOL = 0x00000006, -TRANSERR = 0x00000007, -CMPTO = 0x00000008, -CRS = 0x0000000c, -} RESPONSE_STATUS; - -/******************************************************* - * HUBBUB_RET_PATH Enums - *******************************************************/ - -/* - * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum - */ - -typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE { -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000, -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001, -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002, -} DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE; - -/* - * DCHUBBUB_MEM_PWR_DIS_MODE enum - */ - -typedef enum DCHUBBUB_MEM_PWR_DIS_MODE { -DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000, -DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001, -} DCHUBBUB_MEM_PWR_DIS_MODE; - -/* - * DCHUBBUB_MEM_PWR_MODE enum - */ - -typedef enum DCHUBBUB_MEM_PWR_MODE { -DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000, -DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001, -DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002, -DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003, -} DCHUBBUB_MEM_PWR_MODE; - -/******************************************************* - * MPC_CFG Enums - *******************************************************/ - -/* - * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum - */ - -typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET { -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, -} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; - -/* - * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum - */ - -typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET { -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, -} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; - -/* - * MPC_CFG_ADR_VUPDATE_LOCK_SET enum - */ - -typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET { -MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000, -MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001, -} MPC_CFG_ADR_VUPDATE_LOCK_SET; - -/* - * MPC_CFG_CFG_VUPDATE_LOCK_SET enum - */ - -typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET { -MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000, -MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001, -} MPC_CFG_CFG_VUPDATE_LOCK_SET; - -/* - * MPC_CFG_CUR_VUPDATE_LOCK_SET enum - */ - -typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET { -MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000, -MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001, -} MPC_CFG_CUR_VUPDATE_LOCK_SET; - -/* - * MPC_CFG_MPC_TEST_CLK_SEL enum - */ - -typedef enum MPC_CFG_MPC_TEST_CLK_SEL { -MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000, -MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001, -MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002, -MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003, -} MPC_CFG_MPC_TEST_CLK_SEL; - -/* - * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum - */ - -typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN { -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, -} MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN; - -/* - * MPC_CRC_CALC_INTERLACE_MODE enum - */ - -typedef enum MPC_CRC_CALC_INTERLACE_MODE { -MPC_CRC_INTERLACE_MODE_TOP = 0x00000000, -MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, -MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002, -MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003, -} MPC_CRC_CALC_INTERLACE_MODE; - -/* - * MPC_CRC_CALC_MODE enum - */ - -typedef enum MPC_CRC_CALC_MODE { -MPC_CRC_ONE_SHOT_MODE = 0x00000000, -MPC_CRC_CONTINUOUS_MODE = 0x00000001, -} MPC_CRC_CALC_MODE; - -/* - * MPC_CRC_CALC_STEREO_MODE enum - */ - -typedef enum MPC_CRC_CALC_STEREO_MODE { -MPC_CRC_STEREO_MODE_LEFT = 0x00000000, -MPC_CRC_STEREO_MODE_RIGHT = 0x00000001, -MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002, -MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003, -} MPC_CRC_CALC_STEREO_MODE; - -/* - * MPC_CRC_SOURCE_SELECT enum - */ - -typedef enum MPC_CRC_SOURCE_SELECT { -MPC_CRC_SOURCE_SEL_DPP = 0x00000000, -MPC_CRC_SOURCE_SEL_OPP = 0x00000001, -MPC_CRC_SOURCE_SEL_DWB = 0x00000002, -MPC_CRC_SOURCE_SEL_OTHER = 0x00000003, -} MPC_CRC_SOURCE_SELECT; - -/* - * MPC_DEBUG_BUS1_DATA_SELECT enum - */ - -typedef enum MPC_DEBUG_BUS1_DATA_SELECT { -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0x00000000, -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 0x00000001, -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 0x00000002, -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 0x00000003, -} MPC_DEBUG_BUS1_DATA_SELECT; - -/* - * MPC_DEBUG_BUS2_DATA_SELECT enum - */ - -typedef enum MPC_DEBUG_BUS2_DATA_SELECT { -MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0x00000000, -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 0x00000001, -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 0x00000002, -MPC_DEBUG_BUS2_DATA_SELECT_RES = 0x00000003, -} MPC_DEBUG_BUS2_DATA_SELECT; - -/* - * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum - */ - -typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT { -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0x00000000, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 0x00000001, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 0x00000002, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 0x00000003, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 0x00000004, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 0x00000005, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 0x00000006, -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 0x00000007, -} MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT; - -/* - * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum - */ - -typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT { -MPC_DEBUG_BUS_MPCC_BYTE0 = 0x00000000, -MPC_DEBUG_BUS_MPCC_BYTE1 = 0x00000001, -MPC_DEBUG_BUS_MPCC_BYTE2 = 0x00000002, -MPC_DEBUG_BUS_MPCC_BYTE3 = 0x00000003, -} MPC_DEBUG_BUS_MPCC_BYTE_SELECT; - -/******************************************************* - * MPC_OCSC Enums - *******************************************************/ - -/* - * MPC_OCSC_COEF_FORMAT enum - */ - -typedef enum MPC_OCSC_COEF_FORMAT { -MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000, -MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001, -} MPC_OCSC_COEF_FORMAT; - -/* - * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum - */ - -typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN { -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, -} MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN; - -/* - * MPC_OUT_CSC_MODE enum - */ - -typedef enum MPC_OUT_CSC_MODE { -MPC_OUT_CSC_MODE_0 = 0x00000000, -MPC_OUT_CSC_MODE_1 = 0x00000001, -MPC_OUT_CSC_MODE_2 = 0x00000002, -MPC_OUT_CSC_MODE_RSV = 0x00000003, -} MPC_OUT_CSC_MODE; - -/* - * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum - */ - -typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE { -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006, -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007, -} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; - -/* - * MPC_OUT_RATE_CONTROL_DISABLE_SET enum - */ - -typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET { -MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000, -MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001, -} MPC_OUT_RATE_CONTROL_DISABLE_SET; - -/******************************************************* - * MPCC Enums - *******************************************************/ - -/* - * MPCC_BG_COLOR_BPC enum - */ - -typedef enum MPCC_BG_COLOR_BPC { -MPCC_BG_COLOR_BPC_8bit = 0x00000000, -MPCC_BG_COLOR_BPC_9bit = 0x00000001, -MPCC_BG_COLOR_BPC_10bit = 0x00000002, -MPCC_BG_COLOR_BPC_11bit = 0x00000003, -MPCC_BG_COLOR_BPC_12bit = 0x00000004, -} MPCC_BG_COLOR_BPC; - -/* - * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum - */ - -typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY { -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000, -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001, -} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; - -/* - * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum - */ - -typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE { -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000, -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001, -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002, -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003, -} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; - -/* - * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum - */ - -typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE { -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000, -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001, -} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; - -/* - * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum - */ - -typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE { -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000, -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001, -} MPCC_CONTROL_MPCC_BOT_GAIN_MODE; - -/* - * MPCC_CONTROL_MPCC_MODE enum - */ - -typedef enum MPCC_CONTROL_MPCC_MODE { -MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000, -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001, -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002, -MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003, -} MPCC_CONTROL_MPCC_MODE; - -/* - * MPCC_SM_CONTROL_MPCC_SM_EN enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_EN { -MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001, -} MPCC_SM_CONTROL_MPCC_SM_EN; - -/* - * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT { -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001, -} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; - -/* - * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL { -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003, -} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; - -/* - * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL { -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002, -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003, -} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; - -/* - * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT { -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001, -} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; - -/* - * MPCC_SM_CONTROL_MPCC_SM_MODE enum - */ - -typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE { -MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000, -MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002, -MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004, -MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006, -} MPCC_SM_CONTROL_MPCC_SM_MODE; - -/* - * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum - */ - -typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN { -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, -} MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN; - -/******************************************************* - * MPCC_OGAM Enums - *******************************************************/ - -/* - * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum - */ - -typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM { -MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, -MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, -} MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM; - -/* - * MPCC_GAMUT_REMAP_MODE_ENUM enum - */ - -typedef enum MPCC_GAMUT_REMAP_MODE_ENUM { -MPCC_GAMUT_REMAP_MODE_0 = 0x00000000, -MPCC_GAMUT_REMAP_MODE_1 = 0x00000001, -MPCC_GAMUT_REMAP_MODE_2 = 0x00000002, -MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003, -} MPCC_GAMUT_REMAP_MODE_ENUM; - -/* - * MPCC_OGAM_LUT_2_CONFIG_ENUM enum - */ - -typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM { -MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000, -MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001, -MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002, -} MPCC_OGAM_LUT_2_CONFIG_ENUM; - -/* - * MPCC_OGAM_LUT_CONFIG_MODE enum - */ - -typedef enum MPCC_OGAM_LUT_CONFIG_MODE { -MPCC_OGAM_DIFFERENT_RGB = 0x00000000, -MPCC_OGAM_ALL_USE_R = 0x00000001, -} MPCC_OGAM_LUT_CONFIG_MODE; - -/* - * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum - */ - -typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM { -MPCC_OGAM_ENABLE_PWL = 0x00000000, -MPCC_OGAM_DISABLE_PWL = 0x00000001, -} MPCC_OGAM_LUT_PWL_DISABLE_ENUM; - -/* - * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum - */ - -typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL { -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000, -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001, -} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; - -/* - * MPCC_OGAM_LUT_RAM_SEL enum - */ - -typedef enum MPCC_OGAM_LUT_RAM_SEL { -MPCC_OGAM_RAMA_ACCESS = 0x00000000, -MPCC_OGAM_RAMB_ACCESS = 0x00000001, -} MPCC_OGAM_LUT_RAM_SEL; - -/* - * MPCC_OGAM_LUT_READ_COLOR_SEL enum - */ - -typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL { -MPCC_OGAM_BLUE_LUT = 0x00000000, -MPCC_OGAM_GREEN_LUT = 0x00000001, -MPCC_OGAM_RED_LUT = 0x00000002, -} MPCC_OGAM_LUT_READ_COLOR_SEL; - -/* - * MPCC_OGAM_LUT_READ_DBG enum - */ - -typedef enum MPCC_OGAM_LUT_READ_DBG { -MPCC_OGAM_DISABLE_DEBUG = 0x00000000, -MPCC_OGAM_ENABLE_DEBUG = 0x00000001, -} MPCC_OGAM_LUT_READ_DBG; - -/* - * MPCC_OGAM_LUT_SEL_ENUM enum - */ - -typedef enum MPCC_OGAM_LUT_SEL_ENUM { -MPCC_OGAM_RAMA = 0x00000000, -MPCC_OGAM_RAMB = 0x00000001, -} MPCC_OGAM_LUT_SEL_ENUM; - -/* - * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum - */ - -typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM { -MPCC_OGAM_MODE_0 = 0x00000000, -MPCC_OGAM_MODE_RSV1 = 0x00000001, -MPCC_OGAM_MODE_2 = 0x00000002, -MPCC_OGAM_MODE_RSV = 0x00000003, -} MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM; - -/* - * MPCC_OGAM_NUM_SEG enum - */ - -typedef enum MPCC_OGAM_NUM_SEG { -MPCC_OGAM_SEGMENTS_1 = 0x00000000, -MPCC_OGAM_SEGMENTS_2 = 0x00000001, -MPCC_OGAM_SEGMENTS_4 = 0x00000002, -MPCC_OGAM_SEGMENTS_8 = 0x00000003, -MPCC_OGAM_SEGMENTS_16 = 0x00000004, -MPCC_OGAM_SEGMENTS_32 = 0x00000005, -MPCC_OGAM_SEGMENTS_64 = 0x00000006, -MPCC_OGAM_SEGMENTS_128 = 0x00000007, -} MPCC_OGAM_NUM_SEG; - -/* - * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum - */ - -typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN { -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000, -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001, -} MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN; - -/******************************************************* - * MPCC_MCM Enums - *******************************************************/ - -/* - * MPCC_MCM_3DLUT_30BIT_ENUM enum - */ - -typedef enum MPCC_MCM_3DLUT_30BIT_ENUM { -MPCC_MCM_3DLUT_36BIT = 0x00000000, -MPCC_MCM_3DLUT_30BIT = 0x00000001, -} MPCC_MCM_3DLUT_30BIT_ENUM; - -/* - * MPCC_MCM_3DLUT_RAM_SEL enum - */ - -typedef enum MPCC_MCM_3DLUT_RAM_SEL { -MPCC_MCM_RAM0_ACCESS = 0x00000000, -MPCC_MCM_RAM1_ACCESS = 0x00000001, -MPCC_MCM_RAM2_ACCESS = 0x00000002, -MPCC_MCM_RAM3_ACCESS = 0x00000003, -} MPCC_MCM_3DLUT_RAM_SEL; - -/* - * MPCC_MCM_3DLUT_SIZE_ENUM enum - */ - -typedef enum MPCC_MCM_3DLUT_SIZE_ENUM { -MPCC_MCM_3DLUT_17CUBE = 0x00000000, -MPCC_MCM_3DLUT_9CUBE = 0x00000001, -} MPCC_MCM_3DLUT_SIZE_ENUM; - -/* - * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum - */ - -typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM { -MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000, -MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001, -MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002, -MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003, -} MPCC_MCM_GAMMA_LUT_MODE_ENUM; - -/* - * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum - */ - -typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM { -MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000, -MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001, -} MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM; - -/* - * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum - */ - -typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM { -MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000, -MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001, -} MPCC_MCM_GAMMA_LUT_SEL_ENUM; - -/* - * MPCC_MCM_LUT_2_MODE_ENUM enum - */ - -typedef enum MPCC_MCM_LUT_2_MODE_ENUM { -MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000, -MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001, -MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002, -} MPCC_MCM_LUT_2_MODE_ENUM; - -/* - * MPCC_MCM_LUT_CONFIG_MODE enum - */ - -typedef enum MPCC_MCM_LUT_CONFIG_MODE { -MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000, -MPCC_MCM_LUT_ALL_USE_R = 0x00000001, -} MPCC_MCM_LUT_CONFIG_MODE; - -/* - * MPCC_MCM_LUT_NUM_SEG enum - */ - -typedef enum MPCC_MCM_LUT_NUM_SEG { -MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000, -MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001, -MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002, -MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003, -MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004, -MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005, -MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006, -MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007, -} MPCC_MCM_LUT_NUM_SEG; - -/* - * MPCC_MCM_LUT_RAM_SEL enum - */ - -typedef enum MPCC_MCM_LUT_RAM_SEL { -MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000, -MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001, -} MPCC_MCM_LUT_RAM_SEL; - -/* - * MPCC_MCM_LUT_READ_COLOR_SEL enum - */ - -typedef enum MPCC_MCM_LUT_READ_COLOR_SEL { -MPCC_MCM_LUT_BLUE_LUT = 0x00000000, -MPCC_MCM_LUT_GREEN_LUT = 0x00000001, -MPCC_MCM_LUT_RED_LUT = 0x00000002, -} MPCC_MCM_LUT_READ_COLOR_SEL; - -/* - * MPCC_MCM_LUT_READ_DBG enum - */ - -typedef enum MPCC_MCM_LUT_READ_DBG { -MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000, -MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001, -} MPCC_MCM_LUT_READ_DBG; - -/* - * MPCC_MCM_MEM_PWR_FORCE_ENUM enum - */ - -typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM { -MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000, -MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001, -MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002, -MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003, -} MPCC_MCM_MEM_PWR_FORCE_ENUM; - -/* - * MPCC_MCM_MEM_PWR_STATE_ENUM enum - */ - -typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM { -MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000, -MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001, -MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002, -MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003, -} MPCC_MCM_MEM_PWR_STATE_ENUM; - -/******************************************************* - * ABM Enums - *******************************************************/ - -/******************************************************* - * DPG Enums - *******************************************************/ - -/* - * ENUM_DPG_BIT_DEPTH enum - */ - -typedef enum ENUM_DPG_BIT_DEPTH { -ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000, -ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001, -ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002, -ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003, -} ENUM_DPG_BIT_DEPTH; - -/* - * ENUM_DPG_DYNAMIC_RANGE enum - */ - -typedef enum ENUM_DPG_DYNAMIC_RANGE { -ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000, -ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001, -} ENUM_DPG_DYNAMIC_RANGE; - -/* - * ENUM_DPG_EN enum - */ - -typedef enum ENUM_DPG_EN { -ENUM_DPG_DISABLE = 0x00000000, -ENUM_DPG_ENABLE = 0x00000001, -} ENUM_DPG_EN; - -/* - * ENUM_DPG_FIELD_POLARITY enum - */ - -typedef enum ENUM_DPG_FIELD_POLARITY { -ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000, -ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001, -} ENUM_DPG_FIELD_POLARITY; - -/* - * ENUM_DPG_MODE enum - */ - -typedef enum ENUM_DPG_MODE { -ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000, -ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001, -ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002, -ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003, -ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004, -ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005, -ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006, -ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007, -} ENUM_DPG_MODE; - -/******************************************************* - * FMT Enums - *******************************************************/ - -/* - * FMTMEM_PWR_DIS_CTRL enum - */ - -typedef enum FMTMEM_PWR_DIS_CTRL { -FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} FMTMEM_PWR_DIS_CTRL; - -/* - * FMTMEM_PWR_FORCE_CTRL enum - */ - -typedef enum FMTMEM_PWR_FORCE_CTRL { -FMTMEM_NO_FORCE_REQUEST = 0x00000000, -FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} FMTMEM_PWR_FORCE_CTRL; - -/* - * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000, -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001, -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002, -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003, -} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; - -/* - * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000, -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001, -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002, -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003, -} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; - -/* - * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000, -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001, -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002, -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003, -} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; - -/* - * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000, -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001, -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002, -} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; - -/* - * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000, -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001, -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002, -} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; - -/* - * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000, -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001, -} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; - -/* - * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000, -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001, -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002, -} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; - -/* - * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum - */ - -typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000, -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001, -} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; - -/* - * FMT_CLAMP_CNTL_COLOR_FORMAT enum - */ - -typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000, -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001, -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002, -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003, -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004, -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005, -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006, -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007, -} FMT_CLAMP_CNTL_COLOR_FORMAT; - -/* - * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum - */ - -typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000, -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001, -} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; - -/* - * FMT_CONTROL_PIXEL_ENCODING enum - */ - -typedef enum FMT_CONTROL_PIXEL_ENCODING { -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000, -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001, -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002, -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003, -} FMT_CONTROL_PIXEL_ENCODING; - -/* - * FMT_CONTROL_SUBSAMPLING_MODE enum - */ - -typedef enum FMT_CONTROL_SUBSAMPLING_MODE { -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000, -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001, -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002, -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003, -} FMT_CONTROL_SUBSAMPLING_MODE; - -/* - * FMT_CONTROL_SUBSAMPLING_ORDER enum - */ - -typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000, -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001, -} FMT_CONTROL_SUBSAMPLING_ORDER; - -/* - * FMT_DEBUG_CNTL_COLOR_SELECT enum - */ - -typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { -FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000, -FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001, -FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002, -FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003, -} FMT_DEBUG_CNTL_COLOR_SELECT; - -/* - * FMT_DYNAMIC_EXP_MODE enum - */ - -typedef enum FMT_DYNAMIC_EXP_MODE { -FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000, -FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001, -} FMT_DYNAMIC_EXP_MODE; - -/* - * FMT_FRAME_RANDOM_ENABLE_CONTROL enum - */ - -typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL { -FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000, -FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001, -} FMT_FRAME_RANDOM_ENABLE_CONTROL; - -/* - * FMT_POWER_STATE_ENUM enum - */ - -typedef enum FMT_POWER_STATE_ENUM { -FMT_POWER_STATE_ENUM_ON = 0x00000000, -FMT_POWER_STATE_ENUM_LS = 0x00000001, -FMT_POWER_STATE_ENUM_DS = 0x00000002, -FMT_POWER_STATE_ENUM_SD = 0x00000003, -} FMT_POWER_STATE_ENUM; - -/* - * FMT_RGB_RANDOM_ENABLE_CONTROL enum - */ - -typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL { -FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000, -FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001, -} FMT_RGB_RANDOM_ENABLE_CONTROL; - -/* - * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum - */ - -typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL { -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000, -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001, -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002, -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003, -} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; - -/* - * FMT_SPATIAL_DITHER_MODE enum - */ - -typedef enum FMT_SPATIAL_DITHER_MODE { -FMT_SPATIAL_DITHER_MODE_0 = 0x00000000, -FMT_SPATIAL_DITHER_MODE_1 = 0x00000001, -FMT_SPATIAL_DITHER_MODE_2 = 0x00000002, -FMT_SPATIAL_DITHER_MODE_3 = 0x00000003, -} FMT_SPATIAL_DITHER_MODE; - -/* - * FMT_STEREOSYNC_OVERRIDE_CONTROL enum - */ - -typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL { -FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000, -FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001, -} FMT_STEREOSYNC_OVERRIDE_CONTROL; - -/* - * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum - */ - -typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000, -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001, -} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; - -/******************************************************* - * OPPBUF Enums - *******************************************************/ - -/* - * OPPBUF_DISPLAY_SEGMENTATION enum - */ - -typedef enum OPPBUF_DISPLAY_SEGMENTATION { -OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000, -OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001, -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002, -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003, -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004, -} OPPBUF_DISPLAY_SEGMENTATION; - -/******************************************************* - * OPP_PIPE Enums - *******************************************************/ - -/* - * OPP_PIPE_CLOCK_ENABLE_CONTROL enum - */ - -typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL { -OPP_PIPE_CLOCK_DISABLE = 0x00000000, -OPP_PIPE_CLOCK_ENABLE = 0x00000001, -} OPP_PIPE_CLOCK_ENABLE_CONTROL; - -/* - * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum - */ - -typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL { -OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000, -OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001, -} OPP_PIPE_DIGTIAL_BYPASS_CONTROL; - -/******************************************************* - * OPP_PIPE_CRC Enums - *******************************************************/ - -/* - * OPP_PIPE_CRC_CONT_EN enum - */ - -typedef enum OPP_PIPE_CRC_CONT_EN { -OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000, -OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001, -} OPP_PIPE_CRC_CONT_EN; - -/* - * OPP_PIPE_CRC_EN enum - */ - -typedef enum OPP_PIPE_CRC_EN { -OPP_PIPE_CRC_DISABLE = 0x00000000, -OPP_PIPE_CRC_ENABLE = 0x00000001, -} OPP_PIPE_CRC_EN; - -/* - * OPP_PIPE_CRC_INTERLACE_EN enum - */ - -typedef enum OPP_PIPE_CRC_INTERLACE_EN { -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000, -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001, -} OPP_PIPE_CRC_INTERLACE_EN; - -/* - * OPP_PIPE_CRC_INTERLACE_MODE enum - */ - -typedef enum OPP_PIPE_CRC_INTERLACE_MODE { -OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000, -OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002, -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003, -} OPP_PIPE_CRC_INTERLACE_MODE; - -/* - * OPP_PIPE_CRC_ONE_SHOT_PENDING enum - */ - -typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING { -OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000, -OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001, -} OPP_PIPE_CRC_ONE_SHOT_PENDING; - -/* - * OPP_PIPE_CRC_PIXEL_SELECT enum - */ - -typedef enum OPP_PIPE_CRC_PIXEL_SELECT { -OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000, -OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001, -OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002, -OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003, -} OPP_PIPE_CRC_PIXEL_SELECT; - -/* - * OPP_PIPE_CRC_SOURCE_SELECT enum - */ - -typedef enum OPP_PIPE_CRC_SOURCE_SELECT { -OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000, -OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001, -} OPP_PIPE_CRC_SOURCE_SELECT; - -/* - * OPP_PIPE_CRC_STEREO_EN enum - */ - -typedef enum OPP_PIPE_CRC_STEREO_EN { -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000, -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001, -} OPP_PIPE_CRC_STEREO_EN; - -/* - * OPP_PIPE_CRC_STEREO_MODE enum - */ - -typedef enum OPP_PIPE_CRC_STEREO_MODE { -OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000, -OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001, -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002, -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003, -} OPP_PIPE_CRC_STEREO_MODE; - -/******************************************************* - * OPP_TOP Enums - *******************************************************/ - -/* - * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum - */ - -typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL { -DEBUG_BUS_SELECT_ABM0 = 0x00000000, -DEBUG_BUS_SELECT_ABM1 = 0x00000001, -DEBUG_BUS_SELECT_ABM2 = 0x00000002, -DEBUG_BUS_SELECT_ABM3 = 0x00000003, -DEBUG_BUS_SELECT_ABM_RESERVED0 = 0x00000004, -DEBUG_BUS_SELECT_ABM_RESERVED1 = 0x00000005, -} OPP_ABM_DEBUG_BUS_SELECT_CONTROL; - -/* - * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum - */ - -typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL { -DEBUG_BUS_SELECT_DPG0 = 0x00000000, -DEBUG_BUS_SELECT_DPG1 = 0x00000001, -DEBUG_BUS_SELECT_DPG2 = 0x00000002, -DEBUG_BUS_SELECT_DPG3 = 0x00000003, -DEBUG_BUS_SELECT_DPG_RESERVED0 = 0x00000004, -DEBUG_BUS_SELECT_DPG_RESERVED1 = 0x00000005, -} OPP_DPG_DEBUG_BUS_SELECT_CONTROL; - -/* - * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum - */ - -typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL { -DEBUG_BUS_SELECT_FMT0 = 0x00000000, -DEBUG_BUS_SELECT_FMT1 = 0x00000001, -DEBUG_BUS_SELECT_FMT2 = 0x00000002, -DEBUG_BUS_SELECT_FMT3 = 0x00000003, -DEBUG_BUS_SELECT_FMT_RESERVED0 = 0x00000004, -DEBUG_BUS_SELECT_FMT_RESERVED1 = 0x00000005, -} OPP_FMT_DEBUG_BUS_SELECT_CONTROL; - -/* - * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum - */ - -typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL { -DEBUG_BUS_SELECT_OPPBUF0 = 0x00000000, -DEBUG_BUS_SELECT_OPPBUF1 = 0x00000001, -DEBUG_BUS_SELECT_OPPBUF2 = 0x00000002, -DEBUG_BUS_SELECT_OPPBUF3 = 0x00000003, -DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 0x00000004, -DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 0x00000005, -} OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL; - -/* - * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum - */ - -typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL { -DEBUG_BUS_SELECT_OPP_PIPE0 = 0x00000000, -DEBUG_BUS_SELECT_OPP_PIPE1 = 0x00000001, -DEBUG_BUS_SELECT_OPP_PIPE2 = 0x00000002, -DEBUG_BUS_SELECT_OPP_PIPE3 = 0x00000003, -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 0x00000004, -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 0x00000005, -} OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL; - -/* - * OPP_TEST_CLK_SEL_CONTROL enum - */ - -typedef enum OPP_TEST_CLK_SEL_CONTROL { -OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000, -OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001, -OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002, -OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003, -OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004, -OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005, -OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006, -OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007, -OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008, -OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009, -OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a, -OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b, -OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c, -OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d, -} OPP_TEST_CLK_SEL_CONTROL; - -/* - * OPP_TOP_CLOCK_ENABLE_STATUS enum - */ - -typedef enum OPP_TOP_CLOCK_ENABLE_STATUS { -OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000, -OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001, -} OPP_TOP_CLOCK_ENABLE_STATUS; - -/* - * OPP_TOP_CLOCK_GATING_CONTROL enum - */ - -typedef enum OPP_TOP_CLOCK_GATING_CONTROL { -OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000, -OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001, -} OPP_TOP_CLOCK_GATING_CONTROL; - -/******************************************************* - * DSCRM Enums - *******************************************************/ - -/* - * ENUM_DSCRM_EN enum - */ - -typedef enum ENUM_DSCRM_EN { -ENUM_DSCRM_DISABLE = 0x00000000, -ENUM_DSCRM_ENABLE = 0x00000001, -} ENUM_DSCRM_EN; - -/******************************************************* - * OTG Enums - *******************************************************/ - -/* - * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum - */ - -typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000, -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001, -} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; - -/* - * MASTER_UPDATE_LOCK_SEL enum - */ - -typedef enum MASTER_UPDATE_LOCK_SEL { -MASTER_UPDATE_LOCK_SEL_0 = 0x00000000, -MASTER_UPDATE_LOCK_SEL_1 = 0x00000001, -MASTER_UPDATE_LOCK_SEL_2 = 0x00000002, -MASTER_UPDATE_LOCK_SEL_3 = 0x00000003, -MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004, -MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005, -} MASTER_UPDATE_LOCK_SEL; - -/* - * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum - */ - -typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000, -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001, -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002, -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003, -} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; - -/* - * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum - */ - -typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN { -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001, -} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; - -/* - * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum - */ - -typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB { -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001, -} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; - -/* - * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum - */ - -typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR { -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001, -} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; - -/* - * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum - */ - -typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE { -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002, -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003, -} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; - -/* - * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum - */ - -typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL { -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000, -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001, -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002, -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003, -} OTG_CONTROL_OTG_DISABLE_POINT_CNTL; - -/* - * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum - */ - -typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL { -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000, -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001, -} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; - -/* - * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum - */ - -typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY { -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000, -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001, -} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; - -/* - * OTG_CONTROL_OTG_MASTER_EN enum - */ - -typedef enum OTG_CONTROL_OTG_MASTER_EN { -OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000, -OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001, -} OTG_CONTROL_OTG_MASTER_EN; - -/* - * OTG_CONTROL_OTG_OUT_MUX enum - */ - -typedef enum OTG_CONTROL_OTG_OUT_MUX { -OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000, -OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001, -OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002, -} OTG_CONTROL_OTG_OUT_MUX; - -/* - * OTG_CONTROL_OTG_START_POINT_CNTL enum - */ - -typedef enum OTG_CONTROL_OTG_START_POINT_CNTL { -OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000, -OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001, -} OTG_CONTROL_OTG_START_POINT_CNTL; - -/* - * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum - */ - -typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN { -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000, -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001, -} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; - -/* - * OTG_CRC_CNTL_OTG_CRC1_EN enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC1_EN { -OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000, -OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001, -} OTG_CRC_CNTL_OTG_CRC1_EN; - -/* - * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN { -OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001, -} OTG_CRC_CNTL_OTG_CRC_CONT_EN; - -/* - * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE { -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001, -} OTG_CRC_CNTL_OTG_CRC_CONT_MODE; - -/* - * OTG_CRC_CNTL_OTG_CRC_EN enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_EN { -OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001, -} OTG_CRC_CNTL_OTG_CRC_EN; - -/* - * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE { -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001, -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002, -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003, -} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; - -/* - * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE { -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001, -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002, -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003, -} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; - -/* - * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum - */ - -typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS { -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000, -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001, -} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; - -/* - * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum - */ - -typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT { -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006, -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007, -} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; - -/* - * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum - */ - -typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT { -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006, -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007, -} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; - -/* - * OTG_DIG_UPDATE_VCOUNT_MODE enum - */ - -typedef enum OTG_DIG_UPDATE_VCOUNT_MODE { -OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000, -OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001, -} OTG_DIG_UPDATE_VCOUNT_MODE; - -/* - * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum - */ - -typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE { -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000, -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001, -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002, -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003, -} OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE; - -/* - * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum - */ - -typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY { -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000, -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001, -} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; - -/* - * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum - */ - -typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME { -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000, -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001, -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002, -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003, -} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; - -/* - * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum - */ - -typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN { -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000, -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001, -} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; - -/* - * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum - */ - -typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY { -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001, -} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; - -/* - * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum - */ - -typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY { -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001, -} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; - -/* - * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum - */ - -typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT { -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012, -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013, -} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; - -/* - * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum - */ - -typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK { -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001, -} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; - -/* - * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum - */ - -typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR { -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001, -} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; - -/* - * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum - */ - -typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE { -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003, -} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; - -/* - * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum - */ - -typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL { -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000, -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001, -} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; - -/* - * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum - */ - -typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL { -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000, -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001, -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002, -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003, -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004, -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005, -} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; - -/* - * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum - */ - -typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL { -DIG_UPDATE_EYE_SEL_BOTH = 0x00000000, -DIG_UPDATE_EYE_SEL_LEFT = 0x00000001, -DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002, -} OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL; - -/* - * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum - */ - -typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL { -DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000, -DIG_UPDATE_FIELD_SEL_TOP = 0x00000001, -DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002, -DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003, -} OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL; - -/* - * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum - */ - -typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD { -MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000, -MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001, -MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002, -MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003, -} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; - -/* - * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum - */ - -typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL { -MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000, -MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001, -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002, -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003, -} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; - -/* - * OTG_GLOBAL_UPDATE_LOCK_EN enum - */ - -typedef enum OTG_GLOBAL_UPDATE_LOCK_EN { -OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000, -OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001, -} OTG_GLOBAL_UPDATE_LOCK_EN; - -/* - * OTG_GSL_MASTER_MODE enum - */ - -typedef enum OTG_GSL_MASTER_MODE { -OTG_GSL_MASTER_MODE_0 = 0x00000000, -OTG_GSL_MASTER_MODE_1 = 0x00000001, -OTG_GSL_MASTER_MODE_2 = 0x00000002, -OTG_GSL_MASTER_MODE_3 = 0x00000003, -} OTG_GSL_MASTER_MODE; - -/* - * OTG_HORZ_REPETITION_COUNT enum - */ - -typedef enum OTG_HORZ_REPETITION_COUNT { -OTG_HORZ_REPETITION_COUNT_0 = 0x00000000, -OTG_HORZ_REPETITION_COUNT_1 = 0x00000001, -OTG_HORZ_REPETITION_COUNT_2 = 0x00000002, -OTG_HORZ_REPETITION_COUNT_3 = 0x00000003, -OTG_HORZ_REPETITION_COUNT_4 = 0x00000004, -OTG_HORZ_REPETITION_COUNT_5 = 0x00000005, -OTG_HORZ_REPETITION_COUNT_6 = 0x00000006, -OTG_HORZ_REPETITION_COUNT_7 = 0x00000007, -OTG_HORZ_REPETITION_COUNT_8 = 0x00000008, -OTG_HORZ_REPETITION_COUNT_9 = 0x00000009, -OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a, -OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b, -OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c, -OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d, -OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e, -OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f, -} OTG_HORZ_REPETITION_COUNT; - -/* - * OTG_H_SYNC_A_POL enum - */ - -typedef enum OTG_H_SYNC_A_POL { -OTG_H_SYNC_A_POL_HIGH = 0x00000000, -OTG_H_SYNC_A_POL_LOW = 0x00000001, -} OTG_H_SYNC_A_POL; - -/* - * OTG_H_TIMING_DIV_MODE enum - */ - -typedef enum OTG_H_TIMING_DIV_MODE { -OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000, -OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001, -OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002, -OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003, -} OTG_H_TIMING_DIV_MODE; - -/* - * OTG_H_TIMING_DIV_MODE_MANUAL enum - */ - -typedef enum OTG_H_TIMING_DIV_MODE_MANUAL { -OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000, -OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001, -} OTG_H_TIMING_DIV_MODE_MANUAL; - -/* - * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum - */ - -typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE { -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000, -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001, -} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; - -/* - * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum - */ - -typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD { -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000, -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001, -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002, -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003, -} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; - -/* - * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; - -/* - * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK { -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; - -/* - * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum - */ - -typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE { -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000, -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001, -} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; - -/* - * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum - */ - -typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE { -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000, -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001, -} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; - -/* - * OTG_MASTER_UPDATE_LOCK_DB_EN enum - */ - -typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN { -OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000, -OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001, -} OTG_MASTER_UPDATE_LOCK_DB_EN; - -/* - * OTG_MASTER_UPDATE_LOCK_GSL_EN enum - */ - -typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN { -OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000, -OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001, -} OTG_MASTER_UPDATE_LOCK_GSL_EN; - -/* - * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum - */ - -typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE { -OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000, -OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001, -} OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE; - -/* - * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum - */ - -typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL { -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000, -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001, -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002, -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003, -} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; - -/* - * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum - */ - -typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR { -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000, -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001, -} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; - -/* - * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum - */ - -typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR { -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000, -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001, -} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; - -/* - * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum - */ - -typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE { -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000, -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001, -} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; - -/* - * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum - */ - -typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE { -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000, -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001, -} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; - -/* - * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum - */ - -typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE { -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000, -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001, -} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; - -/* - * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum - */ - -typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE { -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000, -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001, -} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; - -/* - * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum - */ - -typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL { -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000, -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001, -} OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL; - -/* - * OTG_STEREO_CONTROL_OTG_STEREO_EN enum - */ - -typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN { -OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000, -OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001, -} OTG_STEREO_CONTROL_OTG_STEREO_EN; - -/* - * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum - */ - -typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY { -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000, -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001, -} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; - -/* - * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum - */ - -typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY { -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000, -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001, -} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; - -/* - * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum - */ - -typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE { -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000, -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001, -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002, -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003, -} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; - -/* - * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum - */ - -typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR { -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000, -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001, -} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; - -/* - * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum - */ - -typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT { -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006, -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007, -} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; - -/* - * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum - */ - -typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN { -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000, -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001, -} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; - -/* - * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum - */ - -typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT { -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, -} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; - -/* - * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum - */ - -typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT { -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017, -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018, -} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; - -/* - * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum - */ - -typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL { -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, -} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; - -/* - * OTG_TRIGA_FREQUENCY_SELECT enum - */ - -typedef enum OTG_TRIGA_FREQUENCY_SELECT { -OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000, -OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001, -OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002, -OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003, -} OTG_TRIGA_FREQUENCY_SELECT; - -/* - * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum - */ - -typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL { -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, -} OTG_TRIGA_RISING_EDGE_DETECT_CNTL; - -/* - * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum - */ - -typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR { -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000, -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001, -} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; - -/* - * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum - */ - -typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT { -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006, -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007, -} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; - -/* - * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum - */ - -typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN { -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000, -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001, -} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; - -/* - * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum - */ - -typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT { -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005, -} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; - -/* - * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum - */ - -typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT { -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017, -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018, -} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; - -/* - * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum - */ - -typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL { -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000, -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001, -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002, -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003, -} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; - -/* - * OTG_TRIGB_FREQUENCY_SELECT enum - */ - -typedef enum OTG_TRIGB_FREQUENCY_SELECT { -OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000, -OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001, -OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002, -OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003, -} OTG_TRIGB_FREQUENCY_SELECT; - -/* - * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum - */ - -typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL { -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000, -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001, -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002, -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003, -} OTG_TRIGB_RISING_EDGE_DETECT_CNTL; - -/* - * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum - */ - -typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK { -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000, -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001, -} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; - -/* - * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR { -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; - -/* - * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE { -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; - -/* - * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE { -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; - -/* - * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; - -/* - * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR { -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; - -/* - * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE { -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; - -/* - * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE { -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; - -/* - * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR { -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; - -/* - * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE { -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; - -/* - * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum - */ - -typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE { -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000, -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001, -} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; - -/* - * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum - */ - -typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE { -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000, -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001, -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002, -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003, -} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; - -/* - * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum - */ - -typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR { -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000, -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001, -} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; - -/* - * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum - */ - -typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR { -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000, -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001, -} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; - -/* - * OTG_VUPDATE_BLOCK_DISABLE enum - */ - -typedef enum OTG_VUPDATE_BLOCK_DISABLE { -OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000, -OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001, -} OTG_VUPDATE_BLOCK_DISABLE; - -/* - * OTG_V_SYNC_A_POL enum - */ - -typedef enum OTG_V_SYNC_A_POL { -OTG_V_SYNC_A_POL_HIGH = 0x00000000, -OTG_V_SYNC_A_POL_LOW = 0x00000001, -} OTG_V_SYNC_A_POL; - -/* - * OTG_V_SYNC_MODE enum - */ - -typedef enum OTG_V_SYNC_MODE { -OTG_V_SYNC_MODE_HSYNC = 0x00000000, -OTG_V_SYNC_MODE_HBLANK = 0x00000001, -} OTG_V_SYNC_MODE; - -/* - * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum - */ - -typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD { -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000, -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001, -} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; - -/* - * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum - */ - -typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT { -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000, -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001, -} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; - -/* - * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum - */ - -typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC { -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000, -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001, -} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; - -/* - * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum - */ - -typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL { -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000, -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001, -} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; - -/* - * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum - */ - -typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL { -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000, -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001, -} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; - -/* - * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum - */ - -typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK { -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000, -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001, -} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK; - -/******************************************************* - * OPTC_MISC Enums - *******************************************************/ - -/* - * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum - */ - -typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL { -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000, -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001, -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002, -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003, -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004, -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005, -} OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL; - -/******************************************************* - * DMCUB Enums - *******************************************************/ - -/* - * DC_DMCUB_INT_TYPE enum - */ - -typedef enum DC_DMCUB_INT_TYPE { -INT_LEVEL = 0x00000000, -INT_PULSE = 0x00000001, -} DC_DMCUB_INT_TYPE; - -/* - * DC_DMCUB_TIMER_WINDOW enum - */ - -typedef enum DC_DMCUB_TIMER_WINDOW { -BITS_31_0 = 0x00000000, -BITS_32_1 = 0x00000001, -BITS_33_2 = 0x00000002, -BITS_34_3 = 0x00000003, -BITS_35_4 = 0x00000004, -BITS_36_5 = 0x00000005, -BITS_37_6 = 0x00000006, -BITS_38_7 = 0x00000007, -} DC_DMCUB_TIMER_WINDOW; - -/******************************************************* - * RBBMIF Enums - *******************************************************/ - -/* - * INVALID_REG_ACCESS_TYPE enum - */ - -typedef enum INVALID_REG_ACCESS_TYPE { -REG_UNALLOCATED_ADDR_WRITE = 0x00000000, -REG_UNALLOCATED_ADDR_READ = 0x00000001, -REG_VIRTUAL_WRITE = 0x00000002, -REG_VIRTUAL_READ = 0x00000003, -REG_SECURE_VIOLATE_WRITE = 0x00000004, -REG_SECURE_VIOLATE_READ = 0x00000005, -} INVALID_REG_ACCESS_TYPE; - -/******************************************************* - * IHC Enums - *******************************************************/ - -/* - * DMU_DC_GPU_TIMER_READ_SELECT enum - */ - -typedef enum DMU_DC_GPU_TIMER_READ_SELECT { -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007, -RESERVED_8 = 0x00000008, -RESERVED_9 = 0x00000009, -RESERVED_10 = 0x0000000a, -RESERVED_11 = 0x0000000b, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013, -RESERVED_20 = 0x00000014, -RESERVED_21 = 0x00000015, -RESERVED_22 = 0x00000016, -RESERVED_23 = 0x00000017, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f, -RESERVED_32 = 0x00000020, -RESERVED_33 = 0x00000021, -RESERVED_34 = 0x00000022, -RESERVED_35 = 0x00000023, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b, -RESERVED_44 = 0x0000002c, -RESERVED_45 = 0x0000002d, -RESERVED_46 = 0x0000002e, -RESERVED_47 = 0x0000002f, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037, -RESERVED_56 = 0x00000038, -RESERVED_57 = 0x00000039, -RESERVED_58 = 0x0000003a, -RESERVED_59 = 0x0000003b, -RESERVED_60 = 0x0000003c, -RESERVED_61 = 0x0000003d, -RESERVED_62 = 0x0000003e, -RESERVED_63 = 0x0000003f, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047, -RESERVED_72 = 0x00000048, -RESERVED_73 = 0x00000049, -RESERVED_74 = 0x0000004a, -RESERVED_75 = 0x0000004b, -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c, -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d, -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e, -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f, -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050, -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051, -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052, -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053, -RESERVED_84 = 0x00000054, -RESERVED_85 = 0x00000055, -RESERVED_86 = 0x00000056, -RESERVED_87 = 0x00000057, -RESERVED_88 = 0x00000058, -RESERVED_89 = 0x00000059, -RESERVED_90 = 0x0000005a, -RESERVED_91 = 0x0000005b, -} DMU_DC_GPU_TIMER_READ_SELECT; - -/* - * DMU_DC_GPU_TIMER_START_POSITION enum - */ - -typedef enum DMU_DC_GPU_TIMER_START_POSITION { -DMU_GPU_TIMER_START_0_END_27 = 0x00000000, -DMU_GPU_TIMER_START_1_END_28 = 0x00000001, -DMU_GPU_TIMER_START_2_END_29 = 0x00000002, -DMU_GPU_TIMER_START_3_END_30 = 0x00000003, -DMU_GPU_TIMER_START_4_END_31 = 0x00000004, -DMU_GPU_TIMER_START_6_END_33 = 0x00000005, -DMU_GPU_TIMER_START_8_END_35 = 0x00000006, -DMU_GPU_TIMER_START_10_END_37 = 0x00000007, -} DMU_DC_GPU_TIMER_START_POSITION; - -/* - * IHC_INTERRUPT_DEST enum - */ - -typedef enum IHC_INTERRUPT_DEST { -INTERRUPT_SENT_TO_IH = 0x00000000, -INTERRUPT_SENT_TO_DMCUB = 0x00000001, -} IHC_INTERRUPT_DEST; - -/* - * IHC_INTERRUPT_LINE_STATUS enum - */ - -typedef enum IHC_INTERRUPT_LINE_STATUS { -INTERRUPT_LINE_NOT_ASSERTED = 0x00000000, -INTERRUPT_LINE_ASSERTED = 0x00000001, -} IHC_INTERRUPT_LINE_STATUS; - -/******************************************************* - * DMU_MISC Enums - *******************************************************/ - -/* - * DC_SMU_INTERRUPT_ENABLE enum - */ - -typedef enum DC_SMU_INTERRUPT_ENABLE { -DISABLE_THE_INTERRUPT = 0x00000000, -ENABLE_THE_INTERRUPT = 0x00000001, -} DC_SMU_INTERRUPT_ENABLE; - -/* - * DMU_CLOCK_ON enum - */ - -typedef enum DMU_CLOCK_ON { -DMU_CLOCK_STATUS_ON = 0x00000000, -DMU_CLOCK_STATUS_OFF = 0x00000001, -} DMU_CLOCK_ON; - -/* - * SMU_INTR enum - */ - -typedef enum SMU_INTR { -SMU_MSG_INTR_NOOP = 0x00000000, -SET_SMU_MSG_INTR = 0x00000001, -} SMU_INTR; - -/******************************************************* - * DCCG Enums - *******************************************************/ - -/* - * ALLOW_SR_ON_TRANS_REQ enum - */ - -typedef enum ALLOW_SR_ON_TRANS_REQ { -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000, -ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001, -} ALLOW_SR_ON_TRANS_REQ; - -/* - * AMCLOCK_ENABLE enum - */ - -typedef enum AMCLOCK_ENABLE { -ENABLE_AMCLK0 = 0x00000000, -ENABLE_AMCLK1 = 0x00000001, -} AMCLOCK_ENABLE; - -/* - * CLEAR_SMU_INTR enum - */ - -typedef enum CLEAR_SMU_INTR { -SMU_INTR_STATUS_NOOP = 0x00000000, -SMU_INTR_STATUS_CLEAR = 0x00000001, -} CLEAR_SMU_INTR; - -/* - * CLOCK_BRANCH_SOFT_RESET enum - */ - -typedef enum CLOCK_BRANCH_SOFT_RESET { -CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000, -CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001, -} CLOCK_BRANCH_SOFT_RESET; - -/* - * DCCG_AUDIO_DTO0_SOURCE_SEL enum - */ - -typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000, -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001, -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002, -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003, -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004, -} DCCG_AUDIO_DTO0_SOURCE_SEL; - -/* - * DCCG_AUDIO_DTO2_SOURCE_SEL enum - */ - -typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000, -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001, -} DCCG_AUDIO_DTO2_SOURCE_SEL; - -/* - * DCCG_AUDIO_DTO_SEL enum - */ - -typedef enum DCCG_AUDIO_DTO_SEL { -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000, -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001, -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002, -DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 0x00000003, -} DCCG_AUDIO_DTO_SEL; - -/* - * DCCG_AUDIO_DTO_USE_512FBR_DTO enum - */ - -typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000, -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001, -} DCCG_AUDIO_DTO_USE_512FBR_DTO; - -/* - * DCCG_DBG_BLOCK_SEL enum - */ - -typedef enum DCCG_DBG_BLOCK_SEL { -DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000, -DCCG_DBG_BLOCK_SEL_PMON = 0x00000001, -DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002, -} DCCG_DBG_BLOCK_SEL; - -/* - * DCCG_DBG_EN enum - */ - -typedef enum DCCG_DBG_EN { -DCCG_DBG_EN_DISABLE = 0x00000000, -DCCG_DBG_EN_ENABLE = 0x00000001, -} DCCG_DBG_EN; - -/* - * DCCG_DEEP_COLOR_CNTL enum - */ - -typedef enum DCCG_DEEP_COLOR_CNTL { -DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000, -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001, -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002, -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003, -} DCCG_DEEP_COLOR_CNTL; - -/* - * DCCG_FIFO_ERRDET_OVR_EN enum - */ - -typedef enum DCCG_FIFO_ERRDET_OVR_EN { -DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000, -DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001, -} DCCG_FIFO_ERRDET_OVR_EN; - -/* - * DCCG_FIFO_ERRDET_RESET enum - */ - -typedef enum DCCG_FIFO_ERRDET_RESET { -DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000, -DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001, -} DCCG_FIFO_ERRDET_RESET; - -/* - * DCCG_FIFO_ERRDET_STATE enum - */ - -typedef enum DCCG_FIFO_ERRDET_STATE { -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000, -DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001, -} DCCG_FIFO_ERRDET_STATE; - -/* - * DCCG_PERF_MODE_HSYNC enum - */ - -typedef enum DCCG_PERF_MODE_HSYNC { -DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000, -DCCG_PERF_MODE_HSYNC_START = 0x00000001, -} DCCG_PERF_MODE_HSYNC; - -/* - * DCCG_PERF_MODE_VSYNC enum - */ - -typedef enum DCCG_PERF_MODE_VSYNC { -DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000, -DCCG_PERF_MODE_VSYNC_START = 0x00000001, -} DCCG_PERF_MODE_VSYNC; - -/* - * DCCG_PERF_OTG_SELECT enum - */ - -typedef enum DCCG_PERF_OTG_SELECT { -DCCG_PERF_SEL_OTG0 = 0x00000000, -DCCG_PERF_SEL_OTG1 = 0x00000001, -DCCG_PERF_SEL_OTG2 = 0x00000002, -DCCG_PERF_SEL_OTG3 = 0x00000003, -DCCG_PERF_SEL_RESERVED = 0x00000004, -} DCCG_PERF_OTG_SELECT; - -/* - * DCCG_PERF_RUN enum - */ - -typedef enum DCCG_PERF_RUN { -DCCG_PERF_RUN_NOOP = 0x00000000, -DCCG_PERF_RUN_START = 0x00000001, -} DCCG_PERF_RUN; - -/* - * DC_MEM_GLOBAL_PWR_REQ_DIS enum - */ - -typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000, -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001, -} DC_MEM_GLOBAL_PWR_REQ_DIS; - -/* - * DIO_FIFO_ERROR enum - */ - -typedef enum DIO_FIFO_ERROR { -DIO_FIFO_ERROR_00 = 0x00000000, -DIO_FIFO_ERROR_01 = 0x00000001, -DIO_FIFO_ERROR_10 = 0x00000002, -DIO_FIFO_ERROR_11 = 0x00000003, -} DIO_FIFO_ERROR; - -/* - * DISABLE_CLOCK_GATING enum - */ - -typedef enum DISABLE_CLOCK_GATING { -CLOCK_GATING_ENABLED = 0x00000000, -CLOCK_GATING_DISABLED = 0x00000001, -} DISABLE_CLOCK_GATING; - -/* - * DISABLE_CLOCK_GATING_IN_DCO enum - */ - -typedef enum DISABLE_CLOCK_GATING_IN_DCO { -CLOCK_GATING_ENABLED_IN_DCO = 0x00000000, -CLOCK_GATING_DISABLED_IN_DCO = 0x00000001, -} DISABLE_CLOCK_GATING_IN_DCO; - -/* - * DISPCLK_CHG_FWD_CORR_DISABLE enum - */ - -typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000, -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001, -} DISPCLK_CHG_FWD_CORR_DISABLE; - -/* - * DISPCLK_FREQ_RAMP_DONE enum - */ - -typedef enum DISPCLK_FREQ_RAMP_DONE { -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000, -DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001, -} DISPCLK_FREQ_RAMP_DONE; - -/* - * DPREFCLK_SRC_SEL enum - */ - -typedef enum DPREFCLK_SRC_SEL { -DPREFCLK_SRC_SEL_CK = 0x00000000, -DPREFCLK_SRC_SEL_P0PLL = 0x00000001, -DPREFCLK_SRC_SEL_P1PLL = 0x00000002, -DPREFCLK_SRC_SEL_P2PLL = 0x00000003, -} DPREFCLK_SRC_SEL; - -/* - * DP_DTO_DS_DISABLE enum - */ - -typedef enum DP_DTO_DS_DISABLE { -DP_DTO_DESPREAD_DISABLE = 0x00000000, -DP_DTO_DESPREAD_ENABLE = 0x00000001, -} DP_DTO_DS_DISABLE; - -/* - * DS_HW_CAL_ENABLE enum - */ - -typedef enum DS_HW_CAL_ENABLE { -DS_HW_CAL_DIS = 0x00000000, -DS_HW_CAL_EN = 0x00000001, -} DS_HW_CAL_ENABLE; - -/* - * DS_JITTER_COUNT_SRC_SEL enum - */ - -typedef enum DS_JITTER_COUNT_SRC_SEL { -DS_JITTER_COUNT_SRC_SEL0 = 0x00000000, -DS_JITTER_COUNT_SRC_SEL1 = 0x00000001, -} DS_JITTER_COUNT_SRC_SEL; - -/* - * DS_REF_SRC enum - */ - -typedef enum DS_REF_SRC { -DS_REF_IS_XTALIN = 0x00000000, -DS_REF_IS_EXT_GENLOCK = 0x00000001, -DS_REF_IS_PCIE = 0x00000002, -} DS_REF_SRC; - -/* - * DVOACLKC_IN_PHASE enum - */ - -typedef enum DVOACLKC_IN_PHASE { -DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, -DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001, -} DVOACLKC_IN_PHASE; - -/* - * DVOACLKC_MVP_IN_PHASE enum - */ - -typedef enum DVOACLKC_MVP_IN_PHASE { -DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, -DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001, -} DVOACLKC_MVP_IN_PHASE; - -/* - * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum - */ - -typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000, -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001, -} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; - -/* - * DVOACLKD_IN_PHASE enum - */ - -typedef enum DVOACLKD_IN_PHASE { -DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000, -DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001, -} DVOACLKD_IN_PHASE; - -/* - * DVOACLK_COARSE_SKEW_CNTL enum - */ - -typedef enum DVOACLK_COARSE_SKEW_CNTL { -DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, -DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, -DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, -DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, -DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004, -DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005, -DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006, -DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007, -DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008, -DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009, -DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a, -DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b, -DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c, -DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d, -DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e, -DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f, -DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010, -DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011, -DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012, -DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013, -DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014, -DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015, -DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016, -DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017, -DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018, -DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019, -DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a, -DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b, -DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c, -DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d, -DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e, -} DVOACLK_COARSE_SKEW_CNTL; - -/* - * DVOACLK_FINE_SKEW_CNTL enum - */ - -typedef enum DVOACLK_FINE_SKEW_CNTL { -DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000, -DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001, -DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002, -DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003, -DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004, -DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005, -DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006, -DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007, -} DVOACLK_FINE_SKEW_CNTL; - -/* - * DVO_ENABLE_RST enum - */ - -typedef enum DVO_ENABLE_RST { -DVO_ENABLE_RST_DISABLE = 0x00000000, -DVO_ENABLE_RST_ENABLE = 0x00000001, -} DVO_ENABLE_RST; - -/* - * ENABLE enum - */ - -typedef enum ENABLE { -DISABLE_THE_FEATURE = 0x00000000, -ENABLE_THE_FEATURE = 0x00000001, -} ENABLE; - -/* - * ENABLE_CLOCK enum - */ - -typedef enum ENABLE_CLOCK { -ENABLE_THE_REFCLK = 0x00000000, -ENABLE_THE_FUNC_CLOCK = 0x00000001, -} ENABLE_CLOCK; - -/* - * FORCE_DISABLE_CLOCK enum - */ - -typedef enum FORCE_DISABLE_CLOCK { -NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000, -FORCE_THE_CLOCK_DISABLED = 0x00000001, -} FORCE_DISABLE_CLOCK; - -/* - * HDMICHARCLK_SRC_SEL enum - */ - -typedef enum HDMICHARCLK_SRC_SEL { -HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000, -HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001, -HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002, -HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003, -HDMICHARCLK_SRC_SEL_UNIPHYE = 0x00000004, -HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000005, -} HDMICHARCLK_SRC_SEL; - -/* - * HDMISTREAMCLK_DTO_FORCE_DIS enum - */ - -typedef enum HDMISTREAMCLK_DTO_FORCE_DIS { -DTO_FORCE_NO_BYPASS = 0x00000000, -DTO_FORCE_BYPASS = 0x00000001, -} HDMISTREAMCLK_DTO_FORCE_DIS; - -/* - * HDMISTREAMCLK_SRC_SEL enum - */ - -typedef enum HDMISTREAMCLK_SRC_SEL { -SEL_REFCLK0 = 0x00000000, -SEL_DTBCLK0 = 0x00000001, -SEL_DTBCLK1 = 0x00000002, -} HDMISTREAMCLK_SRC_SEL; - -/* - * JITTER_REMOVE_DISABLE enum - */ - -typedef enum JITTER_REMOVE_DISABLE { -ENABLE_JITTER_REMOVAL = 0x00000000, -DISABLE_JITTER_REMOVAL = 0x00000001, -} JITTER_REMOVE_DISABLE; - -/* - * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum - */ - -typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, -MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, -} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; - -/* - * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum - */ - -typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000, -MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001, -} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; - -/* - * OTG_ADD_PIXEL enum - */ - -typedef enum OTG_ADD_PIXEL { -OTG_ADD_PIXEL_NOOP = 0x00000000, -OTG_ADD_PIXEL_FORCE = 0x00000001, -} OTG_ADD_PIXEL; - -/* - * OTG_DROP_PIXEL enum - */ - -typedef enum OTG_DROP_PIXEL { -OTG_DROP_PIXEL_NOOP = 0x00000000, -OTG_DROP_PIXEL_FORCE = 0x00000001, -} OTG_DROP_PIXEL; - -/* - * PHYSYMCLK_FORCE_EN enum - */ - -typedef enum PHYSYMCLK_FORCE_EN { -PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000, -PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001, -} PHYSYMCLK_FORCE_EN; - -/* - * PHYSYMCLK_FORCE_SRC_SEL enum - */ - -typedef enum PHYSYMCLK_FORCE_SRC_SEL { -PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000, -PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001, -PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002, -} PHYSYMCLK_FORCE_SRC_SEL; - -/* - * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum - */ - -typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000, -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001, -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002, -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003, -PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004, -} PIPE_PHYPLL_PIXEL_RATE_SOURCE; - -/* - * PIPE_PIXEL_RATE_PLL_SOURCE enum - */ - -typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000, -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001, -} PIPE_PIXEL_RATE_PLL_SOURCE; - -/* - * PIPE_PIXEL_RATE_SOURCE enum - */ - -typedef enum PIPE_PIXEL_RATE_SOURCE { -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000, -PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001, -PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002, -} PIPE_PIXEL_RATE_SOURCE; - -/* - * PLL_CFG_IF_SOFT_RESET enum - */ - -typedef enum PLL_CFG_IF_SOFT_RESET { -PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000, -PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001, -} PLL_CFG_IF_SOFT_RESET; - -/* - * SYMCLK_FE_FORCE_EN enum - */ - -typedef enum SYMCLK_FE_FORCE_EN { -SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000, -SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001, -} SYMCLK_FE_FORCE_EN; - -/* - * SYMCLK_FE_FORCE_SRC enum - */ - -typedef enum SYMCLK_FE_FORCE_SRC { -SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000, -SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001, -SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002, -SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003, -SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000004, -} SYMCLK_FE_FORCE_SRC; - -/* - * TEST_CLK_DIV_SEL enum - */ - -typedef enum TEST_CLK_DIV_SEL { -NO_DIV = 0x00000000, -DIV_2 = 0x00000001, -DIV_4 = 0x00000002, -DIV_8 = 0x00000003, -} TEST_CLK_DIV_SEL; - -/* - * VSYNC_CNT_LATCH_MASK enum - */ - -typedef enum VSYNC_CNT_LATCH_MASK { -VSYNC_CNT_LATCH_MASK_0 = 0x00000000, -VSYNC_CNT_LATCH_MASK_1 = 0x00000001, -} VSYNC_CNT_LATCH_MASK; - -/* - * VSYNC_CNT_RESET_SEL enum - */ - -typedef enum VSYNC_CNT_RESET_SEL { -VSYNC_CNT_RESET_SEL_0 = 0x00000000, -VSYNC_CNT_RESET_SEL_1 = 0x00000001, -} VSYNC_CNT_RESET_SEL; - -/* - * XTAL_REF_CLOCK_SOURCE_SEL enum - */ - -typedef enum XTAL_REF_CLOCK_SOURCE_SEL { -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000, -XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001, -} XTAL_REF_CLOCK_SOURCE_SEL; - -/* - * XTAL_REF_SEL enum - */ - -typedef enum XTAL_REF_SEL { -XTAL_REF_SEL_1X = 0x00000000, -XTAL_REF_SEL_2X = 0x00000001, -} XTAL_REF_SEL; - -/******************************************************* - * HPD Enums - *******************************************************/ - -/* - * HPD_INT_CONTROL_ACK enum - */ - -typedef enum HPD_INT_CONTROL_ACK { -HPD_INT_CONTROL_ACK_0 = 0x00000000, -HPD_INT_CONTROL_ACK_1 = 0x00000001, -} HPD_INT_CONTROL_ACK; - -/* - * HPD_INT_CONTROL_POLARITY enum - */ - -typedef enum HPD_INT_CONTROL_POLARITY { -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000, -HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001, -} HPD_INT_CONTROL_POLARITY; - -/* - * HPD_INT_CONTROL_RX_INT_ACK enum - */ - -typedef enum HPD_INT_CONTROL_RX_INT_ACK { -HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000, -HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001, -} HPD_INT_CONTROL_RX_INT_ACK; - -/******************************************************* - * DP Enums - *******************************************************/ - -/* - * DPHY_8B10B_CUR_DISP enum - */ - -typedef enum DPHY_8B10B_CUR_DISP { -DPHY_8B10B_CUR_DISP_ZERO = 0x00000000, -DPHY_8B10B_CUR_DISP_ONE = 0x00000001, -} DPHY_8B10B_CUR_DISP; - -/* - * DPHY_8B10B_RESET enum - */ - -typedef enum DPHY_8B10B_RESET { -DPHY_8B10B_NOT_RESET = 0x00000000, -DPHY_8B10B_RESETET = 0x00000001, -} DPHY_8B10B_RESET; - -/* - * DPHY_ALT_SCRAMBLER_RESET_EN enum - */ - -typedef enum DPHY_ALT_SCRAMBLER_RESET_EN { -DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000, -DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001, -} DPHY_ALT_SCRAMBLER_RESET_EN; - -/* - * DPHY_ALT_SCRAMBLER_RESET_SEL enum - */ - -typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL { -DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000, -DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001, -} DPHY_ALT_SCRAMBLER_RESET_SEL; - -/* - * DPHY_ATEST_SEL_LANE0 enum - */ - -typedef enum DPHY_ATEST_SEL_LANE0 { -DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000, -DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001, -} DPHY_ATEST_SEL_LANE0; - -/* - * DPHY_ATEST_SEL_LANE1 enum - */ - -typedef enum DPHY_ATEST_SEL_LANE1 { -DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000, -DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001, -} DPHY_ATEST_SEL_LANE1; - -/* - * DPHY_ATEST_SEL_LANE2 enum - */ - -typedef enum DPHY_ATEST_SEL_LANE2 { -DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000, -DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001, -} DPHY_ATEST_SEL_LANE2; - -/* - * DPHY_ATEST_SEL_LANE3 enum - */ - -typedef enum DPHY_ATEST_SEL_LANE3 { -DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000, -DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001, -} DPHY_ATEST_SEL_LANE3; - -/* - * DPHY_BYPASS enum - */ - -typedef enum DPHY_BYPASS { -DPHY_8B10B_OUTPUT = 0x00000000, -DPHY_DBG_OUTPUT = 0x00000001, -} DPHY_BYPASS; - -/* - * DPHY_CRC_CONT_EN enum - */ - -typedef enum DPHY_CRC_CONT_EN { -DPHY_CRC_ONE_SHOT = 0x00000000, -DPHY_CRC_CONTINUOUS = 0x00000001, -} DPHY_CRC_CONT_EN; - -/* - * DPHY_CRC_EN enum - */ - -typedef enum DPHY_CRC_EN { -DPHY_CRC_DISABLED = 0x00000000, -DPHY_CRC_ENABLED = 0x00000001, -} DPHY_CRC_EN; - -/* - * DPHY_CRC_FIELD enum - */ - -typedef enum DPHY_CRC_FIELD { -DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000, -DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001, -} DPHY_CRC_FIELD; - -/* - * DPHY_CRC_MST_PHASE_ERROR_ACK enum - */ - -typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000, -DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001, -} DPHY_CRC_MST_PHASE_ERROR_ACK; - -/* - * DPHY_CRC_SEL enum - */ - -typedef enum DPHY_CRC_SEL { -DPHY_CRC_LANE0_SELECTED = 0x00000000, -DPHY_CRC_LANE1_SELECTED = 0x00000001, -DPHY_CRC_LANE2_SELECTED = 0x00000002, -DPHY_CRC_LANE3_SELECTED = 0x00000003, -} DPHY_CRC_SEL; - -/* - * DPHY_FEC_ENABLE enum - */ - -typedef enum DPHY_FEC_ENABLE { -DPHY_FEC_DISABLED = 0x00000000, -DPHY_FEC_ENABLED = 0x00000001, -} DPHY_FEC_ENABLE; - -/* - * DPHY_FEC_READY enum - */ - -typedef enum DPHY_FEC_READY { -DPHY_FEC_READY_EN = 0x00000000, -DPHY_FEC_READY_DIS = 0x00000001, -} DPHY_FEC_READY; - -/* - * DPHY_LOAD_BS_COUNT_START enum - */ - -typedef enum DPHY_LOAD_BS_COUNT_START { -DPHY_LOAD_BS_COUNT_STARTED = 0x00000000, -DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001, -} DPHY_LOAD_BS_COUNT_START; - -/* - * DPHY_PRBS_EN enum - */ - -typedef enum DPHY_PRBS_EN { -DPHY_PRBS_DISABLE = 0x00000000, -DPHY_PRBS_ENABLE = 0x00000001, -} DPHY_PRBS_EN; - -/* - * DPHY_PRBS_SEL enum - */ - -typedef enum DPHY_PRBS_SEL { -DPHY_PRBS7_SELECTED = 0x00000000, -DPHY_PRBS23_SELECTED = 0x00000001, -DPHY_PRBS11_SELECTED = 0x00000002, -} DPHY_PRBS_SEL; - -/* - * DPHY_RX_FAST_TRAINING_CAPABLE enum - */ - -typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000, -DPHY_FAST_TRAINING_CAPABLE = 0x00000001, -} DPHY_RX_FAST_TRAINING_CAPABLE; - -/* - * DPHY_SCRAMBLER_ADVANCE enum - */ - -typedef enum DPHY_SCRAMBLER_ADVANCE { -DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000, -DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001, -} DPHY_SCRAMBLER_ADVANCE; - -/* - * DPHY_SCRAMBLER_DIS enum - */ - -typedef enum DPHY_SCRAMBLER_DIS { -DPHY_SCR_ENABLED = 0x00000000, -DPHY_SCR_DISABLED = 0x00000001, -} DPHY_SCRAMBLER_DIS; - -/* - * DPHY_SCRAMBLER_KCODE enum - */ - -typedef enum DPHY_SCRAMBLER_KCODE { -DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000, -DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001, -} DPHY_SCRAMBLER_KCODE; - -/* - * DPHY_SCRAMBLER_SEL enum - */ - -typedef enum DPHY_SCRAMBLER_SEL { -DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000, -DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001, -} DPHY_SCRAMBLER_SEL; - -/* - * DPHY_SKEW_BYPASS enum - */ - -typedef enum DPHY_SKEW_BYPASS { -DPHY_WITH_SKEW = 0x00000000, -DPHY_NO_SKEW = 0x00000001, -} DPHY_SKEW_BYPASS; - -/* - * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum - */ - -typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM { -DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000, -DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001, -} DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM; - -/* - * DPHY_SW_FAST_TRAINING_START enum - */ - -typedef enum DPHY_SW_FAST_TRAINING_START { -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000, -DPHY_SW_FAST_TRAINING_STARTED = 0x00000001, -} DPHY_SW_FAST_TRAINING_START; - -/* - * DPHY_TRAINING_PATTERN_SEL enum - */ - -typedef enum DPHY_TRAINING_PATTERN_SEL { -DPHY_TRAINING_PATTERN_1 = 0x00000000, -DPHY_TRAINING_PATTERN_2 = 0x00000001, -DPHY_TRAINING_PATTERN_3 = 0x00000002, -DPHY_TRAINING_PATTERN_4 = 0x00000003, -} DPHY_TRAINING_PATTERN_SEL; - -/* - * DP_COMPONENT_DEPTH enum - */ - -typedef enum DP_COMPONENT_DEPTH { -DP_COMPONENT_DEPTH_6BPC = 0x00000000, -DP_COMPONENT_DEPTH_8BPC = 0x00000001, -DP_COMPONENT_DEPTH_10BPC = 0x00000002, -DP_COMPONENT_DEPTH_12BPC = 0x00000003, -DP_COMPONENT_DEPTH_16BPC = 0x00000004, -} DP_COMPONENT_DEPTH; - -/* - * DP_CP_ENCRYPTION_TYPE enum - */ - -typedef enum DP_CP_ENCRYPTION_TYPE { -DP_CP_ENCRYPTION_TYPE_0 = 0x00000000, -DP_CP_ENCRYPTION_TYPE_1 = 0x00000001, -} DP_CP_ENCRYPTION_TYPE; - -/* - * DP_DPHY_8B10B_EXT_DISP enum - */ - -typedef enum DP_DPHY_8B10B_EXT_DISP { -DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000, -DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001, -} DP_DPHY_8B10B_EXT_DISP; - -/* - * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum - */ - -typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000, -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001, -} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; - -/* - * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum - */ - -typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000, -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001, -} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; - -/* - * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum - */ - -typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000, -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001, -} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; - -/* - * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum - */ - -typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { -DP_DPHY_HBR2_PASS_THROUGH = 0x00000000, -DP_DPHY_HBR2_PATTERN_1 = 0x00000001, -DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002, -DP_DPHY_HBR2_PATTERN_3 = 0x00000003, -DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006, -} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; - -/* - * DP_DSC_MODE enum - */ - -typedef enum DP_DSC_MODE { -DP_DSC_DISABLE = 0x00000000, -DP_DSC_444_SIMPLE_422 = 0x00000001, -DP_DSC_NATIVE_422_420 = 0x00000002, -} DP_DSC_MODE; - -/* - * DP_EMBEDDED_PANEL_MODE enum - */ - -typedef enum DP_EMBEDDED_PANEL_MODE { -DP_EXTERNAL_PANEL = 0x00000000, -DP_EMBEDDED_PANEL = 0x00000001, -} DP_EMBEDDED_PANEL_MODE; - -/* - * DP_LINK_TRAINING_COMPLETE enum - */ - -typedef enum DP_LINK_TRAINING_COMPLETE { -DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000, -DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001, -} DP_LINK_TRAINING_COMPLETE; - -/* - * DP_LINK_TRAINING_SWITCH_MODE enum - */ - -typedef enum DP_LINK_TRAINING_SWITCH_MODE { -DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000, -DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001, -} DP_LINK_TRAINING_SWITCH_MODE; - -/* - * DP_ML_PHY_SEQ_MODE enum - */ - -typedef enum DP_ML_PHY_SEQ_MODE { -DP_ML_PHY_SEQ_LINE_NUM = 0x00000000, -DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001, -} DP_ML_PHY_SEQ_MODE; - -/* - * DP_MSA_V_TIMING_OVERRIDE_EN enum - */ - -typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { -MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000, -MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001, -} DP_MSA_V_TIMING_OVERRIDE_EN; - -/* - * DP_MSE_BLANK_CODE enum - */ - -typedef enum DP_MSE_BLANK_CODE { -DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000, -DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001, -} DP_MSE_BLANK_CODE; - -/* - * DP_MSE_LINK_LINE enum - */ - -typedef enum DP_MSE_LINK_LINE { -DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000, -DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001, -DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002, -DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003, -} DP_MSE_LINK_LINE; - -/* - * DP_MSE_SAT_ENCRYPT0 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT0 { -DP_MSE_SAT_ENCRYPT0_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT0_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT0; - -/* - * DP_MSE_SAT_ENCRYPT1 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT1 { -DP_MSE_SAT_ENCRYPT1_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT1_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT1; - -/* - * DP_MSE_SAT_ENCRYPT2 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT2 { -DP_MSE_SAT_ENCRYPT2_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT2_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT2; - -/* - * DP_MSE_SAT_ENCRYPT3 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT3 { -DP_MSE_SAT_ENCRYPT3_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT3_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT3; - -/* - * DP_MSE_SAT_ENCRYPT4 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT4 { -DP_MSE_SAT_ENCRYPT4_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT4_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT4; - -/* - * DP_MSE_SAT_ENCRYPT5 enum - */ - -typedef enum DP_MSE_SAT_ENCRYPT5 { -DP_MSE_SAT_ENCRYPT5_DISABLED = 0x00000000, -DP_MSE_SAT_ENCRYPT5_ENABLED = 0x00000001, -} DP_MSE_SAT_ENCRYPT5; - -/* - * DP_MSE_SAT_UPDATE_ACT enum - */ - -typedef enum DP_MSE_SAT_UPDATE_ACT { -DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000, -DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001, -DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002, -} DP_MSE_SAT_UPDATE_ACT; - -/* - * DP_MSE_TIMESTAMP_MODE enum - */ - -typedef enum DP_MSE_TIMESTAMP_MODE { -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000, -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001, -} DP_MSE_TIMESTAMP_MODE; - -/* - * DP_MSE_ZERO_ENCODER enum - */ - -typedef enum DP_MSE_ZERO_ENCODER { -DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000, -DP_MSE_ZERO_FE_ENCODER = 0x00000001, -} DP_MSE_ZERO_ENCODER; - -/* - * DP_MSO_NUM_OF_SST_LINKS enum - */ - -typedef enum DP_MSO_NUM_OF_SST_LINKS { -DP_MSO_ONE_SSTLINK = 0x00000000, -DP_MSO_TWO_SSTLINK = 0x00000001, -DP_MSO_FOUR_SSTLINK = 0x00000002, -} DP_MSO_NUM_OF_SST_LINKS; - -/* - * DP_PIXEL_ENCODING enum - */ - -typedef enum DP_PIXEL_ENCODING { -DP_PIXEL_ENCODING_RGB444 = 0x00000000, -DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, -DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, -DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, -DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, -DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, -} DP_PIXEL_ENCODING; - -/* - * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum - */ - -typedef enum DP_PIXEL_PER_CYCLE_PROCESSING_NUM { -DP_ONE_PIXEL_PER_CYCLE = 0x00000000, -DP_TWO_PIXEL_PER_CYCLE = 0x00000001, -} DP_PIXEL_PER_CYCLE_PROCESSING_NUM; - -/* - * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum - */ - -typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, -} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; - -/* - * DP_SEC_ASP_PRIORITY enum - */ - -typedef enum DP_SEC_ASP_PRIORITY { -DP_SEC_ASP_LOW_PRIORITY = 0x00000000, -DP_SEC_ASP_HIGH_PRIORITY = 0x00000001, -} DP_SEC_ASP_PRIORITY; - -/* - * DP_SEC_AUDIO_MUTE enum - */ - -typedef enum DP_SEC_AUDIO_MUTE { -DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000, -DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001, -} DP_SEC_AUDIO_MUTE; - -/* - * DP_SEC_COLLISION_ACK enum - */ - -typedef enum DP_SEC_COLLISION_ACK { -DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000, -DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001, -} DP_SEC_COLLISION_ACK; - -/* - * DP_SEC_GSP0_PRIORITY enum - */ - -typedef enum DP_SEC_GSP0_PRIORITY { -SEC_GSP0_PRIORITY_LOW = 0x00000000, -SEC_GSP0_PRIORITY_HIGH = 0x00000001, -} DP_SEC_GSP0_PRIORITY; - -/* - * DP_SEC_GSP_SEND enum - */ - -typedef enum DP_SEC_GSP_SEND { -NOT_SENT = 0x00000000, -FORCE_SENT = 0x00000001, -} DP_SEC_GSP_SEND; - -/* - * DP_SEC_GSP_SEND_ANY_LINE enum - */ - -typedef enum DP_SEC_GSP_SEND_ANY_LINE { -SEND_AT_LINK_NUMBER = 0x00000000, -SEND_AT_EARLIEST_TIME = 0x00000001, -} DP_SEC_GSP_SEND_ANY_LINE; - -/* - * DP_SEC_GSP_SEND_PPS enum - */ - -typedef enum DP_SEC_GSP_SEND_PPS { -SEND_NORMAL_PACKET = 0x00000000, -SEND_PPS_PACKET = 0x00000001, -} DP_SEC_GSP_SEND_PPS; - -/* - * DP_SEC_LINE_REFERENCE enum - */ - -typedef enum DP_SEC_LINE_REFERENCE { -REFER_TO_DP_SOF = 0x00000000, -REFER_TO_OTG_SOF = 0x00000001, -} DP_SEC_LINE_REFERENCE; - -/* - * DP_SEC_TIMESTAMP_MODE enum - */ - -typedef enum DP_SEC_TIMESTAMP_MODE { -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000, -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001, -} DP_SEC_TIMESTAMP_MODE; - -/* - * DP_STEER_OVERFLOW_ACK enum - */ - -typedef enum DP_STEER_OVERFLOW_ACK { -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000, -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, -} DP_STEER_OVERFLOW_ACK; - -/* - * DP_STEER_OVERFLOW_MASK enum - */ - -typedef enum DP_STEER_OVERFLOW_MASK { -DP_STEER_OVERFLOW_MASKED = 0x00000000, -DP_STEER_OVERFLOW_UNMASK = 0x00000001, -} DP_STEER_OVERFLOW_MASK; - -/* - * DP_SYNC_POLARITY enum - */ - -typedef enum DP_SYNC_POLARITY { -DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000, -DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001, -} DP_SYNC_POLARITY; - -/* - * DP_TU_OVERFLOW_ACK enum - */ - -typedef enum DP_TU_OVERFLOW_ACK { -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000, -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001, -} DP_TU_OVERFLOW_ACK; - -/* - * DP_UDI_LANES enum - */ - -typedef enum DP_UDI_LANES { -DP_UDI_1_LANE = 0x00000000, -DP_UDI_2_LANES = 0x00000001, -DP_UDI_LANES_RESERVED = 0x00000002, -DP_UDI_4_LANES = 0x00000003, -} DP_UDI_LANES; - -/* - * DP_VID_ENHANCED_FRAME_MODE enum - */ - -typedef enum DP_VID_ENHANCED_FRAME_MODE { -VID_NORMAL_FRAME_MODE = 0x00000000, -VID_ENHANCED_MODE = 0x00000001, -} DP_VID_ENHANCED_FRAME_MODE; - -/* - * DP_VID_M_N_DOUBLE_BUFFER_MODE enum - */ - -typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000, -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001, -} DP_VID_M_N_DOUBLE_BUFFER_MODE; - -/* - * DP_VID_M_N_GEN_EN enum - */ - -typedef enum DP_VID_M_N_GEN_EN { -DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000, -DP_VID_M_N_CALC_AUTO = 0x00000001, -} DP_VID_M_N_GEN_EN; - -/* - * DP_VID_N_MUL enum - */ - -typedef enum DP_VID_N_MUL { -DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000, -DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001, -DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002, -DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003, -} DP_VID_N_MUL; - -/* - * DP_VID_STREAM_DISABLE_ACK enum - */ - -typedef enum DP_VID_STREAM_DISABLE_ACK { -ID_STREAM_DISABLE_NO_ACK = 0x00000000, -ID_STREAM_DISABLE_ACKED = 0x00000001, -} DP_VID_STREAM_DISABLE_ACK; - -/* - * DP_VID_STREAM_DISABLE_MASK enum - */ - -typedef enum DP_VID_STREAM_DISABLE_MASK { -VID_STREAM_DISABLE_MASKED = 0x00000000, -VID_STREAM_DISABLE_UNMASK = 0x00000001, -} DP_VID_STREAM_DISABLE_MASK; - -/* - * DP_VID_STREAM_DIS_DEFER enum - */ - -typedef enum DP_VID_STREAM_DIS_DEFER { -DP_VID_STREAM_DIS_NO_DEFER = 0x00000000, -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001, -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002, -} DP_VID_STREAM_DIS_DEFER; - -/* - * DP_VID_VBID_FIELD_POL enum - */ - -typedef enum DP_VID_VBID_FIELD_POL { -DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000, -DP_VID_VBID_FIELD_POL_INV = 0x00000001, -} DP_VID_VBID_FIELD_POL; - -/* - * FEC_ACTIVE_STATUS enum - */ - -typedef enum FEC_ACTIVE_STATUS { -DPHY_FEC_NOT_ACTIVE = 0x00000000, -DPHY_FEC_ACTIVE = 0x00000001, -} FEC_ACTIVE_STATUS; - -/******************************************************* - * DIG Enums - *******************************************************/ - -/* - * DIG_BE_CNTL_HPD_SELECT enum - */ - -typedef enum DIG_BE_CNTL_HPD_SELECT { -DIG_BE_CNTL_HPD1 = 0x00000000, -DIG_BE_CNTL_HPD2 = 0x00000001, -DIG_BE_CNTL_HPD3 = 0x00000002, -DIG_BE_CNTL_HPD4 = 0x00000003, -DIG_BE_CNTL_HPD5 = 0x00000004, -DIG_BE_CNTL_NO_HPD = 0x00000005, -} DIG_BE_CNTL_HPD_SELECT; - -/* - * DIG_BE_CNTL_MODE enum - */ - -typedef enum DIG_BE_CNTL_MODE { -DIG_BE_DP_SST_MODE = 0x00000000, -DIG_BE_RESERVED1 = 0x00000001, -DIG_BE_TMDS_DVI_MODE = 0x00000002, -DIG_BE_TMDS_HDMI_MODE = 0x00000003, -DIG_BE_RESERVED4 = 0x00000004, -DIG_BE_DP_MST_MODE = 0x00000005, -DIG_BE_RESERVED2 = 0x00000006, -DIG_BE_RESERVED3 = 0x00000007, -} DIG_BE_CNTL_MODE; - -/* - * DIG_DIGITAL_BYPASS_ENABLE enum - */ - -typedef enum DIG_DIGITAL_BYPASS_ENABLE { -DIG_DIGITAL_BYPASS_OFF = 0x00000000, -DIG_DIGITAL_BYPASS_ON = 0x00000001, -} DIG_DIGITAL_BYPASS_ENABLE; - -/* - * DIG_DIGITAL_BYPASS_SEL enum - */ - -typedef enum DIG_DIGITAL_BYPASS_SEL { -DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000, -DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001, -DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002, -DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003, -DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004, -DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005, -DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006, -} DIG_DIGITAL_BYPASS_SEL; - -/* - * DIG_FE_CNTL_SOURCE_SELECT enum - */ - -typedef enum DIG_FE_CNTL_SOURCE_SELECT { -DIG_FE_SOURCE_FROM_OTG0 = 0x00000000, -DIG_FE_SOURCE_FROM_OTG1 = 0x00000001, -DIG_FE_SOURCE_FROM_OTG2 = 0x00000002, -DIG_FE_SOURCE_FROM_OTG3 = 0x00000003, -DIG_FE_SOURCE_RESERVED = 0x00000004, -} DIG_FE_CNTL_SOURCE_SELECT; - -/* - * DIG_FE_CNTL_STEREOSYNC_SELECT enum - */ - -typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { -DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000, -DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001, -DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002, -DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003, -DIG_FE_STEREOSYNC_RESERVED = 0x00000004, -} DIG_FE_CNTL_STEREOSYNC_SELECT; - -/* - * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum - */ - -typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX { -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000, -DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001, -} DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX; - -/* - * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum - */ - -typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL { -DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000, -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001, -} DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL; - -/* - * DIG_FIFO_FORCE_RECAL_AVERAGE enum - */ - -typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE { -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000, -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001, -} DIG_FIFO_FORCE_RECAL_AVERAGE; - -/* - * DIG_FIFO_OUTPUT_PROCESSING_MODE enum - */ - -typedef enum DIG_FIFO_OUTPUT_PROCESSING_MODE { -DIG_FIFO_1_PIX_PER_CYCLE = 0x00000000, -DIG_FIFO_2_PIX_PER_CYCLE = 0x00000001, -} DIG_FIFO_OUTPUT_PROCESSING_MODE; - -/* - * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum - */ - -typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR { -DIG_FIFO_NO_ERROR_OCCURRED = 0x00000000, -DIG_FIFO_UNDERFLOW_OCCURRED = 0x00000001, -DIG_FIFO_OVERFLOW_OCCURRED = 0x00000002, -} DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR; - -/* - * DIG_FIFO_READ_CLOCK_SRC enum - */ - -typedef enum DIG_FIFO_READ_CLOCK_SRC { -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000, -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001, -} DIG_FIFO_READ_CLOCK_SRC; - -/* - * DIG_INPUT_PIXEL_SEL enum - */ - -typedef enum DIG_INPUT_PIXEL_SEL { -DIG_ALL_PIXEL = 0x00000000, -DIG_EVEN_PIXEL_ONLY = 0x00000001, -DIG_ODD_PIXEL_ONLY = 0x00000002, -} DIG_INPUT_PIXEL_SEL; - -/* - * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum - */ - -typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { -DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000, -DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001, -} DIG_OUTPUT_CRC_CNTL_LINK_SEL; - -/* - * DIG_OUTPUT_CRC_DATA_SEL enum - */ - -typedef enum DIG_OUTPUT_CRC_DATA_SEL { -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000, -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001, -DIG_OUTPUT_CRC_FOR_VBI = 0x00000002, -DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003, -} DIG_OUTPUT_CRC_DATA_SEL; - -/* - * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum - */ - -typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000, -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001, -} DIG_RANDOM_PATTERN_SEED_RAN_PAT; - -/* - * DIG_SL_PIXEL_GROUPING enum - */ - -typedef enum DIG_SL_PIXEL_GROUPING { -DIG_SINGLETON_PIXELS = 0x00000000, -DIG_PAIR_PIXELS = 0x00000001, -} DIG_SL_PIXEL_GROUPING; - -/* - * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum - */ - -typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000, -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001, -} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; - -/* - * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum - */ - -typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { -DIG_10BIT_TEST_PATTERN = 0x00000000, -DIG_ALTERNATING_TEST_PATTERN = 0x00000001, -} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; - -/* - * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum - */ - -typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { -DIG_TEST_PATTERN_NORMAL = 0x00000000, -DIG_TEST_PATTERN_RANDOM = 0x00000001, -} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; - -/* - * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum - */ - -typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { -DIG_RANDOM_PATTERN_ENABLED = 0x00000000, -DIG_RANDOM_PATTERN_RESETED = 0x00000001, -} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; - -/* - * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum - */ - -typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { -DIG_IN_NORMAL_OPERATION = 0x00000000, -DIG_IN_DEBUG_MODE = 0x00000001, -} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; - -/* - * DOLBY_VISION_ENABLE enum - */ - -typedef enum DOLBY_VISION_ENABLE { -DOLBY_VISION_DISABLED = 0x00000000, -DOLBY_VISION_ENABLED = 0x00000001, -} DOLBY_VISION_ENABLE; - -/* - * HDMI_ACP_SEND enum - */ - -typedef enum HDMI_ACP_SEND { -HDMI_ACP_NOT_SEND = 0x00000000, -HDMI_ACP_PKT_SEND = 0x00000001, -} HDMI_ACP_SEND; - -/* - * HDMI_ACR_AUDIO_PRIORITY enum - */ - -typedef enum HDMI_ACR_AUDIO_PRIORITY { -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, -} HDMI_ACR_AUDIO_PRIORITY; - -/* - * HDMI_ACR_CONT enum - */ - -typedef enum HDMI_ACR_CONT { -HDMI_ACR_CONT_DISABLE = 0x00000000, -HDMI_ACR_CONT_ENABLE = 0x00000001, -} HDMI_ACR_CONT; - -/* - * HDMI_ACR_N_MULTIPLE enum - */ - -typedef enum HDMI_ACR_N_MULTIPLE { -HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000, -HDMI_ACR_1_MULTIPLE = 0x00000001, -HDMI_ACR_2_MULTIPLE = 0x00000002, -HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003, -HDMI_ACR_4_MULTIPLE = 0x00000004, -HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005, -HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006, -HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007, -} HDMI_ACR_N_MULTIPLE; - -/* - * HDMI_ACR_SELECT enum - */ - -typedef enum HDMI_ACR_SELECT { -HDMI_ACR_SELECT_HW = 0x00000000, -HDMI_ACR_SELECT_32K = 0x00000001, -HDMI_ACR_SELECT_44K = 0x00000002, -HDMI_ACR_SELECT_48K = 0x00000003, -} HDMI_ACR_SELECT; - -/* - * HDMI_ACR_SEND enum - */ - -typedef enum HDMI_ACR_SEND { -HDMI_ACR_NOT_SEND = 0x00000000, -HDMI_ACR_PKT_SEND = 0x00000001, -} HDMI_ACR_SEND; - -/* - * HDMI_ACR_SOURCE enum - */ - -typedef enum HDMI_ACR_SOURCE { -HDMI_ACR_SOURCE_HW = 0x00000000, -HDMI_ACR_SOURCE_SW = 0x00000001, -} HDMI_ACR_SOURCE; - -/* - * HDMI_AUDIO_DELAY_EN enum - */ - -typedef enum HDMI_AUDIO_DELAY_EN { -HDMI_AUDIO_DELAY_DISABLE = 0x00000000, -HDMI_AUDIO_DELAY_58CLK = 0x00000001, -HDMI_AUDIO_DELAY_56CLK = 0x00000002, -HDMI_AUDIO_DELAY_RESERVED = 0x00000003, -} HDMI_AUDIO_DELAY_EN; - -/* - * HDMI_AUDIO_INFO_CONT enum - */ - -typedef enum HDMI_AUDIO_INFO_CONT { -HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000, -HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001, -} HDMI_AUDIO_INFO_CONT; - -/* - * HDMI_AUDIO_INFO_SEND enum - */ - -typedef enum HDMI_AUDIO_INFO_SEND { -HDMI_AUDIO_INFO_NOT_SEND = 0x00000000, -HDMI_AUDIO_INFO_PKT_SEND = 0x00000001, -} HDMI_AUDIO_INFO_SEND; - -/* - * HDMI_CLOCK_CHANNEL_RATE enum - */ - -typedef enum HDMI_CLOCK_CHANNEL_RATE { -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000, -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001, -} HDMI_CLOCK_CHANNEL_RATE; - -/* - * HDMI_DATA_SCRAMBLE_EN enum - */ - -typedef enum HDMI_DATA_SCRAMBLE_EN { -HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000, -HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001, -} HDMI_DATA_SCRAMBLE_EN; - -/* - * HDMI_DEEP_COLOR_DEPTH enum - */ - -typedef enum HDMI_DEEP_COLOR_DEPTH { -HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000, -HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001, -HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002, -HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003, -} HDMI_DEEP_COLOR_DEPTH; - -/* - * HDMI_DEFAULT_PAHSE enum - */ - -typedef enum HDMI_DEFAULT_PAHSE { -HDMI_DEFAULT_PHASE_IS_0 = 0x00000000, -HDMI_DEFAULT_PHASE_IS_1 = 0x00000001, -} HDMI_DEFAULT_PAHSE; - -/* - * HDMI_ERROR_ACK enum - */ - -typedef enum HDMI_ERROR_ACK { -HDMI_ERROR_ACK_INT = 0x00000000, -HDMI_ERROR_NOT_ACK = 0x00000001, -} HDMI_ERROR_ACK; - -/* - * HDMI_ERROR_MASK enum - */ - -typedef enum HDMI_ERROR_MASK { -HDMI_ERROR_MASK_INT = 0x00000000, -HDMI_ERROR_NOT_MASK = 0x00000001, -} HDMI_ERROR_MASK; - -/* - * HDMI_GC_AVMUTE enum - */ - -typedef enum HDMI_GC_AVMUTE { -HDMI_GC_AVMUTE_SET = 0x00000000, -HDMI_GC_AVMUTE_UNSET = 0x00000001, -} HDMI_GC_AVMUTE; - -/* - * HDMI_GC_AVMUTE_CONT enum - */ - -typedef enum HDMI_GC_AVMUTE_CONT { -HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000, -HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001, -} HDMI_GC_AVMUTE_CONT; - -/* - * HDMI_GC_CONT enum - */ - -typedef enum HDMI_GC_CONT { -HDMI_GC_CONT_DISABLE = 0x00000000, -HDMI_GC_CONT_ENABLE = 0x00000001, -} HDMI_GC_CONT; - -/* - * HDMI_GC_SEND enum - */ - -typedef enum HDMI_GC_SEND { -HDMI_GC_NOT_SEND = 0x00000000, -HDMI_GC_PKT_SEND = 0x00000001, -} HDMI_GC_SEND; - -/* - * HDMI_GENERIC_CONT enum - */ - -typedef enum HDMI_GENERIC_CONT { -HDMI_GENERIC_CONT_DISABLE = 0x00000000, -HDMI_GENERIC_CONT_ENABLE = 0x00000001, -} HDMI_GENERIC_CONT; - -/* - * HDMI_GENERIC_SEND enum - */ - -typedef enum HDMI_GENERIC_SEND { -HDMI_GENERIC_NOT_SEND = 0x00000000, -HDMI_GENERIC_PKT_SEND = 0x00000001, -} HDMI_GENERIC_SEND; - -/* - * HDMI_ISRC_CONT enum - */ - -typedef enum HDMI_ISRC_CONT { -HDMI_ISRC_CONT_DISABLE = 0x00000000, -HDMI_ISRC_CONT_ENABLE = 0x00000001, -} HDMI_ISRC_CONT; - -/* - * HDMI_ISRC_SEND enum - */ - -typedef enum HDMI_ISRC_SEND { -HDMI_ISRC_NOT_SEND = 0x00000000, -HDMI_ISRC_PKT_SEND = 0x00000001, -} HDMI_ISRC_SEND; - -/* - * HDMI_KEEPOUT_MODE enum - */ - -typedef enum HDMI_KEEPOUT_MODE { -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000, -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001, -} HDMI_KEEPOUT_MODE; - -/* - * HDMI_METADATA_ENABLE enum - */ - -typedef enum HDMI_METADATA_ENABLE { -HDMI_METADATA_NOT_SEND = 0x00000000, -HDMI_METADATA_PKT_SEND = 0x00000001, -} HDMI_METADATA_ENABLE; - -/* - * HDMI_MPEG_INFO_CONT enum - */ - -typedef enum HDMI_MPEG_INFO_CONT { -HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000, -HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001, -} HDMI_MPEG_INFO_CONT; - -/* - * HDMI_MPEG_INFO_SEND enum - */ - -typedef enum HDMI_MPEG_INFO_SEND { -HDMI_MPEG_INFO_NOT_SEND = 0x00000000, -HDMI_MPEG_INFO_PKT_SEND = 0x00000001, -} HDMI_MPEG_INFO_SEND; - -/* - * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum - */ - -typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000, -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001, -} HDMI_NO_EXTRA_NULL_PACKET_FILLED; - -/* - * HDMI_NULL_SEND enum - */ - -typedef enum HDMI_NULL_SEND { -HDMI_NULL_NOT_SEND = 0x00000000, -HDMI_NULL_PKT_SEND = 0x00000001, -} HDMI_NULL_SEND; - -/* - * HDMI_PACKET_GEN_VERSION enum - */ - -typedef enum HDMI_PACKET_GEN_VERSION { -HDMI_PACKET_GEN_VERSION_OLD = 0x00000000, -HDMI_PACKET_GEN_VERSION_NEW = 0x00000001, -} HDMI_PACKET_GEN_VERSION; - -/* - * HDMI_PACKET_LINE_REFERENCE enum - */ - -typedef enum HDMI_PACKET_LINE_REFERENCE { -HDMI_PKT_LINE_REF_VSYNC = 0x00000000, -HDMI_PKT_LINE_REF_OTGSOF = 0x00000001, -} HDMI_PACKET_LINE_REFERENCE; - -/* - * HDMI_PACKING_PHASE_OVERRIDE enum - */ - -typedef enum HDMI_PACKING_PHASE_OVERRIDE { -HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000, -HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001, -} HDMI_PACKING_PHASE_OVERRIDE; - -/* - * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum - */ - -typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000, -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001, -} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; - -/* - * TMDS_COLOR_FORMAT enum - */ - -typedef enum TMDS_COLOR_FORMAT { -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000, -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001, -TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002, -TMDS_COLOR_FORMAT_RESERVED = 0x00000003, -} TMDS_COLOR_FORMAT; - -/* - * TMDS_CTL0_DATA_INVERT enum - */ - -typedef enum TMDS_CTL0_DATA_INVERT { -TMDS_CTL0_DATA_NORMAL = 0x00000000, -TMDS_CTL0_DATA_INVERT_EN = 0x00000001, -} TMDS_CTL0_DATA_INVERT; - -/* - * TMDS_CTL0_DATA_MODULATION enum - */ - -typedef enum TMDS_CTL0_DATA_MODULATION { -TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000, -TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001, -TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002, -TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003, -} TMDS_CTL0_DATA_MODULATION; - -/* - * TMDS_CTL0_DATA_SEL enum - */ - -typedef enum TMDS_CTL0_DATA_SEL { -TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000, -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, -TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002, -TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003, -TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004, -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005, -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006, -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007, -} TMDS_CTL0_DATA_SEL; - -/* - * TMDS_CTL0_PATTERN_OUT_EN enum - */ - -typedef enum TMDS_CTL0_PATTERN_OUT_EN { -TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000, -TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001, -} TMDS_CTL0_PATTERN_OUT_EN; - -/* - * TMDS_CTL1_DATA_INVERT enum - */ - -typedef enum TMDS_CTL1_DATA_INVERT { -TMDS_CTL1_DATA_NORMAL = 0x00000000, -TMDS_CTL1_DATA_INVERT_EN = 0x00000001, -} TMDS_CTL1_DATA_INVERT; - -/* - * TMDS_CTL1_DATA_MODULATION enum - */ - -typedef enum TMDS_CTL1_DATA_MODULATION { -TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000, -TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001, -TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002, -TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003, -} TMDS_CTL1_DATA_MODULATION; - -/* - * TMDS_CTL1_DATA_SEL enum - */ - -typedef enum TMDS_CTL1_DATA_SEL { -TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000, -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, -TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002, -TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003, -TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004, -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005, -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006, -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007, -} TMDS_CTL1_DATA_SEL; - -/* - * TMDS_CTL1_PATTERN_OUT_EN enum - */ - -typedef enum TMDS_CTL1_PATTERN_OUT_EN { -TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000, -TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001, -} TMDS_CTL1_PATTERN_OUT_EN; - -/* - * TMDS_CTL2_DATA_INVERT enum - */ - -typedef enum TMDS_CTL2_DATA_INVERT { -TMDS_CTL2_DATA_NORMAL = 0x00000000, -TMDS_CTL2_DATA_INVERT_EN = 0x00000001, -} TMDS_CTL2_DATA_INVERT; - -/* - * TMDS_CTL2_DATA_MODULATION enum - */ - -typedef enum TMDS_CTL2_DATA_MODULATION { -TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000, -TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001, -TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002, -TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003, -} TMDS_CTL2_DATA_MODULATION; - -/* - * TMDS_CTL2_DATA_SEL enum - */ - -typedef enum TMDS_CTL2_DATA_SEL { -TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000, -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, -TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002, -TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003, -TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004, -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005, -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006, -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007, -} TMDS_CTL2_DATA_SEL; - -/* - * TMDS_CTL2_PATTERN_OUT_EN enum - */ - -typedef enum TMDS_CTL2_PATTERN_OUT_EN { -TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000, -TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001, -} TMDS_CTL2_PATTERN_OUT_EN; - -/* - * TMDS_CTL3_DATA_INVERT enum - */ - -typedef enum TMDS_CTL3_DATA_INVERT { -TMDS_CTL3_DATA_NORMAL = 0x00000000, -TMDS_CTL3_DATA_INVERT_EN = 0x00000001, -} TMDS_CTL3_DATA_INVERT; - -/* - * TMDS_CTL3_DATA_MODULATION enum - */ - -typedef enum TMDS_CTL3_DATA_MODULATION { -TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000, -TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001, -TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002, -TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003, -} TMDS_CTL3_DATA_MODULATION; - -/* - * TMDS_CTL3_DATA_SEL enum - */ - -typedef enum TMDS_CTL3_DATA_SEL { -TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000, -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001, -TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002, -TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003, -TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004, -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005, -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006, -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007, -} TMDS_CTL3_DATA_SEL; - -/* - * TMDS_CTL3_PATTERN_OUT_EN enum - */ - -typedef enum TMDS_CTL3_PATTERN_OUT_EN { -TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000, -TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001, -} TMDS_CTL3_PATTERN_OUT_EN; - -/* - * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum - */ - -typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000, -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001, -} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; - -/* - * TMDS_PIXEL_ENCODING enum - */ - -typedef enum TMDS_PIXEL_ENCODING { -TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000, -TMDS_PIXEL_ENCODING_422 = 0x00000001, -} TMDS_PIXEL_ENCODING; - -/* - * TMDS_REG_TEST_OUTPUTA_CNTLA enum - */ - -typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000, -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001, -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002, -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003, -} TMDS_REG_TEST_OUTPUTA_CNTLA; - -/* - * TMDS_REG_TEST_OUTPUTB_CNTLB enum - */ - -typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000, -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001, -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002, -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003, -} TMDS_REG_TEST_OUTPUTB_CNTLB; - -/* - * TMDS_STEREOSYNC_CTL_SEL_REG enum - */ - -typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { -TMDS_STEREOSYNC_CTL0 = 0x00000000, -TMDS_STEREOSYNC_CTL1 = 0x00000001, -TMDS_STEREOSYNC_CTL2 = 0x00000002, -TMDS_STEREOSYNC_CTL3 = 0x00000003, -} TMDS_STEREOSYNC_CTL_SEL_REG; - -/* - * TMDS_SYNC_PHASE enum - */ - -typedef enum TMDS_SYNC_PHASE { -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, -TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001, -} TMDS_SYNC_PHASE; - -/* - * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000, -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; - -/* - * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000, -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; - -/* - * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000, -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; - -/* - * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000, -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; - -/* - * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000, -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; - -/* - * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000, -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001, -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002, -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003, -} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; - -/* - * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000, -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; - -/* - * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000, -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; - -/* - * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000, -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; - -/* - * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum - */ - -typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000, -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001, -} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; - -/* - * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum - */ - -typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000, -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001, -} TMDS_TRANSMITTER_ENABLE_HPD_MASK; - -/* - * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum - */ - -typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001, -} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; - -/* - * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum - */ - -typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000, -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001, -} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; - -/******************************************************* - * DP_AUX Enums - *******************************************************/ - -/* - * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum - */ - -typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000, -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001, -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002, -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003, -} DP_AUX_ARB_CONTROL_ARB_PRIORITY; - -/* - * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum - */ - -typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000, -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001, -} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; - -/* - * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum - */ - -typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000, -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001, -} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; - -/* - * DP_AUX_ARB_STATUS enum - */ - -typedef enum DP_AUX_ARB_STATUS { -DP_AUX_IDLE = 0x00000000, -DP_AUX_IN_USE_LS = 0x00000001, -DP_AUX_IN_USE_GTC = 0x00000002, -DP_AUX_IN_USE_SW = 0x00000003, -DP_AUX_IN_USE_PHYWAKE = 0x00000004, -} DP_AUX_ARB_STATUS; - -/* - * DP_AUX_CONTROL_HPD_SEL enum - */ - -typedef enum DP_AUX_CONTROL_HPD_SEL { -DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000, -DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001, -DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002, -DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003, -DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004, -DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000005, -} DP_AUX_CONTROL_HPD_SEL; - -/* - * DP_AUX_CONTROL_TEST_MODE enum - */ - -typedef enum DP_AUX_CONTROL_TEST_MODE { -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000, -DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001, -} DP_AUX_CONTROL_TEST_MODE; - -/* - * DP_AUX_DEFINITE_ERR_REACHED_ACK enum - */ - -typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000, -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001, -} DP_AUX_DEFINITE_ERR_REACHED_ACK; - -/* - * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000, -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001, -} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; - -/* - * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000, -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001, -} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; - -/* - * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000, -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001, -} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; - -/* - * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000, -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001, -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002, -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003, -} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; - -/* - * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000, -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001, -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002, -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003, -} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; - -/* - * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006, -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007, -} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; - -/* - * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum - */ - -typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006, -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007, -} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; - -/* - * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum - */ - -typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006, -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007, -} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; - -/* - * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum - */ - -typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000, -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001, -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002, -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003, -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004, -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005, -} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; - -/* - * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum - */ - -typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000, -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001, -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002, -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003, -} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; - -/* - * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum - */ - -typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000, -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001, -} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; - -/* - * DP_AUX_ERR_OCCURRED_ACK enum - */ - -typedef enum DP_AUX_ERR_OCCURRED_ACK { -DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000, -DP_AUX_ERR_OCCURRED__ACK = 0x00000001, -} DP_AUX_ERR_OCCURRED_ACK; - -/* - * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum - */ - -typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000, -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001, -} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; - -/* - * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum - */ - -typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000, -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001, -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002, -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003, -} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; - -/* - * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum - */ - -typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000, -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001, -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002, -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003, -} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; - -/* - * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum - */ - -typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000, -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001, -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002, -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003, -} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; - -/* - * DP_AUX_INT_ACK enum - */ - -typedef enum DP_AUX_INT_ACK { -DP_AUX_INT__NOT_ACK = 0x00000000, -DP_AUX_INT__ACK = 0x00000001, -} DP_AUX_INT_ACK; - -/* - * DP_AUX_LS_UPDATE_ACK enum - */ - -typedef enum DP_AUX_LS_UPDATE_ACK { -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000, -DP_AUX_INT_LS_UPDATE_ACK = 0x00000001, -} DP_AUX_LS_UPDATE_ACK; - -/* - * DP_AUX_PHY_WAKE_PRIORITY enum - */ - -typedef enum DP_AUX_PHY_WAKE_PRIORITY { -DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000, -DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001, -} DP_AUX_PHY_WAKE_PRIORITY; - -/* - * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum - */ - -typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000, -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001, -} DP_AUX_POTENTIAL_ERR_REACHED_ACK; - -/* - * DP_AUX_RESET enum - */ - -typedef enum DP_AUX_RESET { -DP_AUX_RESET_DEASSERTED = 0x00000000, -DP_AUX_RESET_ASSERTED = 0x00000001, -} DP_AUX_RESET; - -/* - * DP_AUX_RESET_DONE enum - */ - -typedef enum DP_AUX_RESET_DONE { -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000, -DP_AUX_RESET_SEQUENCE_DONE = 0x00000001, -} DP_AUX_RESET_DONE; - -/* - * DP_AUX_RX_TIMEOUT_LEN_MUL enum - */ - -typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL { -DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000, -DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001, -DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002, -DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003, -} DP_AUX_RX_TIMEOUT_LEN_MUL; - -/* - * DP_AUX_SW_CONTROL_LS_READ_TRIG enum - */ - -typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000, -DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001, -} DP_AUX_SW_CONTROL_LS_READ_TRIG; - -/* - * DP_AUX_SW_CONTROL_SW_GO enum - */ - -typedef enum DP_AUX_SW_CONTROL_SW_GO { -DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000, -DP_AUX_SW_CONTROL_SW__GO = 0x00000001, -} DP_AUX_SW_CONTROL_SW_GO; - -/* - * DP_AUX_TX_PRECHARGE_LEN_MUL enum - */ - -typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL { -DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000, -DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001, -DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002, -DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003, -} DP_AUX_TX_PRECHARGE_LEN_MUL; - -/******************************************************* - * DOUT_I2C Enums - *******************************************************/ - -/* - * DOUT_I2C_ACK enum - */ - -typedef enum DOUT_I2C_ACK { -DOUT_I2C_NO_ACK = 0x00000000, -DOUT_I2C_ACK_TO_CLEAN = 0x00000001, -} DOUT_I2C_ACK; - -/* - * DOUT_I2C_ARBITRATION_ABORT_XFER enum - */ - -typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000, -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001, -} DOUT_I2C_ARBITRATION_ABORT_XFER; - -/* - * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum - */ - -typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000, -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001, -} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; - -/* - * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum - */ - -typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000, -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001, -} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; - -/* - * DOUT_I2C_ARBITRATION_SW_PRIORITY enum - */ - -typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000, -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001, -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002, -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003, -} DOUT_I2C_ARBITRATION_SW_PRIORITY; - -/* - * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum - */ - -typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000, -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001, -} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; - -/* - * DOUT_I2C_CONTROL_DBG_REF_SEL enum - */ - -typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { -DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000, -DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001, -} DOUT_I2C_CONTROL_DBG_REF_SEL; - -/* - * DOUT_I2C_CONTROL_DDC_SELECT enum - */ - -typedef enum DOUT_I2C_CONTROL_DDC_SELECT { -DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000, -DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001, -DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002, -DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003, -DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004, -DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000005, -} DOUT_I2C_CONTROL_DDC_SELECT; - -/* - * DOUT_I2C_CONTROL_GO enum - */ - -typedef enum DOUT_I2C_CONTROL_GO { -DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000, -DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001, -} DOUT_I2C_CONTROL_GO; - -/* - * DOUT_I2C_CONTROL_SEND_RESET enum - */ - -typedef enum DOUT_I2C_CONTROL_SEND_RESET { -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000, -DOUT_I2C_CONTROL__SEND_RESET = 0x00000001, -} DOUT_I2C_CONTROL_SEND_RESET; - -/* - * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum - */ - -typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH { -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000, -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001, -} DOUT_I2C_CONTROL_SEND_RESET_LENGTH; - -/* - * DOUT_I2C_CONTROL_SOFT_RESET enum - */ - -typedef enum DOUT_I2C_CONTROL_SOFT_RESET { -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000, -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001, -} DOUT_I2C_CONTROL_SOFT_RESET; - -/* - * DOUT_I2C_CONTROL_SW_STATUS_RESET enum - */ - -typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000, -DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001, -} DOUT_I2C_CONTROL_SW_STATUS_RESET; - -/* - * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum - */ - -typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { -DOUT_I2C_CONTROL_TRANS0 = 0x00000000, -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001, -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002, -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003, -} DOUT_I2C_CONTROL_TRANSACTION_COUNT; - -/* - * DOUT_I2C_DATA_INDEX_WRITE enum - */ - -typedef enum DOUT_I2C_DATA_INDEX_WRITE { -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000, -DOUT_I2C_DATA__INDEX_WRITE = 0x00000001, -} DOUT_I2C_DATA_INDEX_WRITE; - -/* - * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum - */ - -typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001, -} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; - -/* - * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum - */ - -typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000, -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001, -} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; - -/* - * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum - */ - -typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000, -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001, -} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; - -/* - * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum - */ - -typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000, -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001, -} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; - -/* - * DOUT_I2C_DDC_SPEED_THRESHOLD enum - */ - -typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000, -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001, -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002, -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003, -} DOUT_I2C_DDC_SPEED_THRESHOLD; - -/* - * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum - */ - -typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000, -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001, -} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; - -/* - * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum - */ - -typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000, -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001, -} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; - -/* - * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum - */ - -typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000, -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001, -} DOUT_I2C_TRANSACTION_STOP_ON_NACK; - -/******************************************************* - * DIO_MISC Enums - *******************************************************/ - -/* - * CLOCK_GATING_EN enum - */ - -typedef enum CLOCK_GATING_EN { -CLOCK_GATING_ENABLE = 0x00000000, -CLOCK_GATING_DISABLE = 0x00000001, -} CLOCK_GATING_EN; - -/* - * DAC_MUX_SELECT enum - */ - -typedef enum DAC_MUX_SELECT { -DAC_MUX_SELECT_DACA = 0x00000000, -DAC_MUX_SELECT_DACB = 0x00000001, -} DAC_MUX_SELECT; - -/* - * DIOMEM_PWR_DIS_CTRL enum - */ - -typedef enum DIOMEM_PWR_DIS_CTRL { -DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} DIOMEM_PWR_DIS_CTRL; - -/* - * DIOMEM_PWR_FORCE_CTRL enum - */ - -typedef enum DIOMEM_PWR_FORCE_CTRL { -DIOMEM_NO_FORCE_REQUEST = 0x00000000, -DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} DIOMEM_PWR_FORCE_CTRL; - -/* - * DIOMEM_PWR_FORCE_CTRL2 enum - */ - -typedef enum DIOMEM_PWR_FORCE_CTRL2 { -DIOMEM_NO_FORCE_REQ = 0x00000000, -DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, -} DIOMEM_PWR_FORCE_CTRL2; - -/* - * DIOMEM_PWR_SEL_CTRL enum - */ - -typedef enum DIOMEM_PWR_SEL_CTRL { -DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, -DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, -DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, -} DIOMEM_PWR_SEL_CTRL; - -/* - * DIOMEM_PWR_SEL_CTRL2 enum - */ - -typedef enum DIOMEM_PWR_SEL_CTRL2 { -DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000, -DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, -} DIOMEM_PWR_SEL_CTRL2; - -/* - * DIO_DBG_BLOCK_SEL enum - */ - -typedef enum DIO_DBG_BLOCK_SEL { -DIO_DBG_BLOCK_SEL_DIO = 0x00000000, -DIO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b, -DIO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c, -DIO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d, -DIO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e, -DIO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f, -DIO_DBG_BLOCK_SEL_DIGA = 0x00000012, -DIO_DBG_BLOCK_SEL_DIGB = 0x00000013, -DIO_DBG_BLOCK_SEL_DIGC = 0x00000014, -DIO_DBG_BLOCK_SEL_DIGD = 0x00000015, -DIO_DBG_BLOCK_SEL_DIGE = 0x00000016, -DIO_DBG_BLOCK_SEL_DPFE_A = 0x00000019, -DIO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a, -DIO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b, -DIO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c, -DIO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d, -DIO_DBG_BLOCK_SEL_DPA = 0x00000020, -DIO_DBG_BLOCK_SEL_DPB = 0x00000021, -DIO_DBG_BLOCK_SEL_DPC = 0x00000022, -DIO_DBG_BLOCK_SEL_DPD = 0x00000023, -DIO_DBG_BLOCK_SEL_DPE = 0x00000024, -DIO_DBG_BLOCK_SEL_AUX0 = 0x00000027, -DIO_DBG_BLOCK_SEL_AUX1 = 0x00000028, -DIO_DBG_BLOCK_SEL_AUX2 = 0x00000029, -DIO_DBG_BLOCK_SEL_AUX3 = 0x0000002a, -DIO_DBG_BLOCK_SEL_AUX4 = 0x0000002b, -DIO_DBG_BLOCK_SEL_PERFMON_DIO = 0x0000002d, -DIO_DBG_BLOCK_SEL_RESERVED = 0x0000002e, -} DIO_DBG_BLOCK_SEL; - -/* - * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum - */ - -typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE { -DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000, -DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001, -} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE; - -/* - * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum - */ - -typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE { -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000, -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001, -} DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE; - -/* - * ENUM_DIO_DCN_ACTIVE_STATUS enum - */ - -typedef enum ENUM_DIO_DCN_ACTIVE_STATUS { -ENUM_DCN_NOT_ACTIVE = 0x00000000, -ENUM_DCN_ACTIVE = 0x00000001, -} ENUM_DIO_DCN_ACTIVE_STATUS; - -/* - * GENERIC_STEREOSYNC_SEL enum - */ - -typedef enum GENERIC_STEREOSYNC_SEL { -GENERIC_STEREOSYNC_SEL_D1 = 0x00000000, -GENERIC_STEREOSYNC_SEL_D2 = 0x00000001, -GENERIC_STEREOSYNC_SEL_D3 = 0x00000002, -GENERIC_STEREOSYNC_SEL_D4 = 0x00000003, -GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000004, -} GENERIC_STEREOSYNC_SEL; - -/* - * PM_ASSERT_RESET enum - */ - -typedef enum PM_ASSERT_RESET { -PM_ASSERT_RESET_0 = 0x00000000, -PM_ASSERT_RESET_1 = 0x00000001, -} PM_ASSERT_RESET; - -/* - * SOFT_RESET enum - */ - -typedef enum SOFT_RESET { -SOFT_RESET_0 = 0x00000000, -SOFT_RESET_1 = 0x00000001, -} SOFT_RESET; - -/* - * TMDS_MUX_SELECT enum - */ - -typedef enum TMDS_MUX_SELECT { -TMDS_MUX_SELECT_B = 0x00000000, -TMDS_MUX_SELECT_G = 0x00000001, -TMDS_MUX_SELECT_R = 0x00000002, -TMDS_MUX_SELECT_RESERVED = 0x00000003, -} TMDS_MUX_SELECT; - -/******************************************************* - * DME Enums - *******************************************************/ - -/* - * DME_MEM_POWER_STATE_ENUM enum - */ - -typedef enum DME_MEM_POWER_STATE_ENUM { -DME_MEM_POWER_STATE_ENUM_ON = 0x00000000, -DME_MEM_POWER_STATE_ENUM_LS = 0x00000001, -DME_MEM_POWER_STATE_ENUM_DS = 0x00000002, -DME_MEM_POWER_STATE_ENUM_SD = 0x00000003, -} DME_MEM_POWER_STATE_ENUM; - -/* - * DME_MEM_PWR_DIS_CTRL enum - */ - -typedef enum DME_MEM_PWR_DIS_CTRL { -DME_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -DME_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} DME_MEM_PWR_DIS_CTRL; - -/* - * DME_MEM_PWR_FORCE_CTRL enum - */ - -typedef enum DME_MEM_PWR_FORCE_CTRL { -DME_MEM_NO_FORCE_REQUEST = 0x00000000, -DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -DME_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} DME_MEM_PWR_FORCE_CTRL; - -/* - * METADATA_HUBP_SEL enum - */ - -typedef enum METADATA_HUBP_SEL { -METADATA_HUBP_SEL_0 = 0x00000000, -METADATA_HUBP_SEL_1 = 0x00000001, -METADATA_HUBP_SEL_2 = 0x00000002, -METADATA_HUBP_SEL_3 = 0x00000003, -METADATA_HUBP_SEL_RESERVED = 0x00000004, -} METADATA_HUBP_SEL; - -/* - * METADATA_STREAM_TYPE_SEL enum - */ - -typedef enum METADATA_STREAM_TYPE_SEL { -METADATA_STREAM_DP = 0x00000000, -METADATA_STREAM_DVE = 0x00000001, -} METADATA_STREAM_TYPE_SEL; - -/******************************************************* - * VPG Enums - *******************************************************/ - -/* - * VPG_MEM_PWR_DIS_CTRL enum - */ - -typedef enum VPG_MEM_PWR_DIS_CTRL { -VPG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -VPG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} VPG_MEM_PWR_DIS_CTRL; - -/* - * VPG_MEM_PWR_FORCE_CTRL enum - */ - -typedef enum VPG_MEM_PWR_FORCE_CTRL { -VPG_MEM_NO_FORCE_REQ = 0x00000000, -VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001, -} VPG_MEM_PWR_FORCE_CTRL; - -/******************************************************* - * AFMT Enums - *******************************************************/ - -/* - * AFMT_ACP_TYPE enum - */ - -typedef enum AFMT_ACP_TYPE { -ACP_TYPE_GENERIC_AUDIO = 0x00000000, -ACP_TYPE_ICE60958_AUDIO = 0x00000001, -ACP_TYPE_DVD_AUDIO = 0x00000002, -ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, -} AFMT_ACP_TYPE; - -/* - * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum - */ - -typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { -AFMT_AUDIO_CRC_CH0_SIG = 0x00000000, -AFMT_AUDIO_CRC_CH1_SIG = 0x00000001, -AFMT_AUDIO_CRC_CH2_SIG = 0x00000002, -AFMT_AUDIO_CRC_CH3_SIG = 0x00000003, -AFMT_AUDIO_CRC_CH4_SIG = 0x00000004, -AFMT_AUDIO_CRC_CH5_SIG = 0x00000005, -AFMT_AUDIO_CRC_CH6_SIG = 0x00000006, -AFMT_AUDIO_CRC_CH7_SIG = 0x00000007, -AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008, -AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009, -AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a, -AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b, -AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c, -AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d, -AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e, -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f, -} AFMT_AUDIO_CRC_CONTROL_CH_SEL; - -/* - * AFMT_AUDIO_CRC_CONTROL_CONT enum - */ - -typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { -AFMT_AUDIO_CRC_ONESHOT = 0x00000000, -AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001, -} AFMT_AUDIO_CRC_CONTROL_CONT; - -/* - * AFMT_AUDIO_CRC_CONTROL_SOURCE enum - */ - -typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000, -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001, -} AFMT_AUDIO_CRC_CONTROL_SOURCE; - -/* - * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum - */ - -typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000, -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001, -} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; - -/* - * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum - */ - -typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { -AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000, -AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001, -} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; - -/* - * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum - */ - -typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000, -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001, -} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; - -/* - * AFMT_AUDIO_SRC_CONTROL_SELECT enum - */ - -typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000, -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001, -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002, -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003, -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004, -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005, -} AFMT_AUDIO_SRC_CONTROL_SELECT; - -/* - * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum - */ - -typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS { -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000, -HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001, -} AFMT_HDMI_AUDIO_SEND_MAX_PACKETS; - -/* - * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum - */ - -typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000, -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, -} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; - -/* - * AFMT_INTERRUPT_STATUS_CHG_MASK enum - */ - -typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { -AFMT_INTERRUPT_DISABLE = 0x00000000, -AFMT_INTERRUPT_ENABLE = 0x00000001, -} AFMT_INTERRUPT_STATUS_CHG_MASK; - -/* - * AFMT_MEM_PWR_DIS_CTRL enum - */ - -typedef enum AFMT_MEM_PWR_DIS_CTRL { -AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -AFMT_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} AFMT_MEM_PWR_DIS_CTRL; - -/* - * AFMT_MEM_PWR_FORCE_CTRL enum - */ - -typedef enum AFMT_MEM_PWR_FORCE_CTRL { -AFMT_MEM_NO_FORCE_REQUEST = 0x00000000, -AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} AFMT_MEM_PWR_FORCE_CTRL; - -/* - * AFMT_RAMP_CONTROL0_SIGN enum - */ - -typedef enum AFMT_RAMP_CONTROL0_SIGN { -AFMT_RAMP_SIGNED = 0x00000000, -AFMT_RAMP_UNSIGNED = 0x00000001, -} AFMT_RAMP_CONTROL0_SIGN; - -/* - * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum - */ - -typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE { -AFMT_ACP_SOURCE_FROM_AZALIA = 0x00000000, -AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 0x00000001, -} AFMT_VBI_PACKET_CONTROL_ACP_SOURCE; - -/* - * AUDIO_LAYOUT_SELECT enum - */ - -typedef enum AUDIO_LAYOUT_SELECT { -AUDIO_LAYOUT_0 = 0x00000000, -AUDIO_LAYOUT_1 = 0x00000001, -} AUDIO_LAYOUT_SELECT; - -/******************************************************* - * HPO_TOP Enums - *******************************************************/ - -/* - * HPO_TOP_CLOCK_GATING_DISABLE enum - */ - -typedef enum HPO_TOP_CLOCK_GATING_DISABLE { -HPO_TOP_CLOCK_GATING_EN = 0x00000000, -HPO_TOP_CLOCK_GATING_DIS = 0x00000001, -} HPO_TOP_CLOCK_GATING_DISABLE; - -/* - * HPO_TOP_TEST_CLK_SEL enum - */ - -typedef enum HPO_TOP_TEST_CLK_SEL { -HPO_TOP_PERMANENT_DISPCLK = 0x00000000, -HPO_TOP_REGISTER_GATED_DISPCLK = 0x00000001, -HPO_TOP_PERMANENT_SOCCLK = 0x00000002, -HPO_TOP_TEST_CLOCK_RESERVED = 0x00000003, -HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 0x00000004, -HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 0x00000005, -HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 0x00000006, -HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007, -HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008, -HPO_TOP_PERMANENT_HDMICHARCLK0 = 0x00000009, -HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 0x0000000a, -HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 0x0000000b, -} HPO_TOP_TEST_CLK_SEL; - -/******************************************************* - * DP_STREAM_MAPPER Enums - *******************************************************/ - -/* - * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum - */ - -typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET { -DP_STREAM_MAPPER_LINK0 = 0x00000000, -DP_STREAM_MAPPER_LINK1 = 0x00000001, -DP_STREAM_MAPPER_RESERVED = 0x00000002, -} DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET; - -/******************************************************* - * HDMI_STREAM_ENC Enums - *******************************************************/ - -/* - * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum - */ - -typedef enum HDMI_STREAM_ENC_DB_DISABLE_CONTROL { -HDMI_STREAM_ENC_DB_ENABLE = 0x00000000, -HDMI_STREAM_ENC_DB_DISABLE = 0x00000001, -} HDMI_STREAM_ENC_DB_DISABLE_CONTROL; - -/* - * HDMI_STREAM_ENC_DSC_MODE enum - */ - -typedef enum HDMI_STREAM_ENC_DSC_MODE { -STREAM_DSC_DISABLE = 0x00000000, -STREAM_DSC_444_RGB = 0x00000001, -STREAM_DSC_NATIVE_422_420 = 0x00000002, -} HDMI_STREAM_ENC_DSC_MODE; - -/* - * HDMI_STREAM_ENC_ENABLE_CONTROL enum - */ - -typedef enum HDMI_STREAM_ENC_ENABLE_CONTROL { -HDMI_STREAM_ENC_DISABLE = 0x00000000, -HDMI_STREAM_ENC_ENABLE = 0x00000001, -} HDMI_STREAM_ENC_ENABLE_CONTROL; - -/* - * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum - */ - -typedef enum HDMI_STREAM_ENC_ODM_COMBINE_MODE { -STREAM_ODM_COMBINE_1_SEGMENT = 0x00000000, -STREAM_ODM_COMBINE_2_SEGMENT = 0x00000001, -STREAM_ODM_COMBINE_RESERVED = 0x00000002, -STREAM_ODM_COMBINE_4_SEGMENT = 0x00000003, -} HDMI_STREAM_ENC_ODM_COMBINE_MODE; - -/* - * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum - */ - -typedef enum HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR { -HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000, -HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001, -HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002, -} HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; - -/* - * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum - */ - -typedef enum HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT { -HDMI_STREAM_ENC_HARDWARE = 0x00000000, -HDMI_STREAM_ENC_PROGRAMMABLE = 0x00000001, -} HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT; - -/* - * HDMI_STREAM_ENC_PIXEL_ENCODING enum - */ - -typedef enum HDMI_STREAM_ENC_PIXEL_ENCODING { -STREAM_PIXEL_ENCODING_444_RGB = 0x00000000, -STREAM_PIXEL_ENCODING_422 = 0x00000001, -STREAM_PIXEL_ENCODING_420 = 0x00000002, -} HDMI_STREAM_ENC_PIXEL_ENCODING; - -/* - * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum - */ - -typedef enum HDMI_STREAM_ENC_READ_CLOCK_CONTROL { -HDMI_STREAM_ENC_DCCG = 0x00000000, -HDMI_STREAM_ENC_DISPLAY_PIPE = 0x00000001, -} HDMI_STREAM_ENC_READ_CLOCK_CONTROL; - -/* - * HDMI_STREAM_ENC_RESET_CONTROL enum - */ - -typedef enum HDMI_STREAM_ENC_RESET_CONTROL { -HDMI_STREAM_ENC_NOT_RESET = 0x00000000, -HDMI_STREAM_ENC_RESET = 0x00000001, -} HDMI_STREAM_ENC_RESET_CONTROL; - -/* - * HDMI_STREAM_ENC_STREAM_ACTIVE enum - */ - -typedef enum HDMI_STREAM_ENC_STREAM_ACTIVE { -HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000, -HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001, -} HDMI_STREAM_ENC_STREAM_ACTIVE; - -/******************************************************* - * HDMI_TB_ENC Enums - *******************************************************/ - -/* - * BORROWBUFFER_MEM_POWER_STATE_ENUM enum - */ - -typedef enum BORROWBUFFER_MEM_POWER_STATE_ENUM { -BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0x00000000, -BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 0x00000001, -BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 0x00000002, -BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 0x00000003, -} BORROWBUFFER_MEM_POWER_STATE_ENUM; - -/* - * HDMI_BORROW_MODE enum - */ - -typedef enum HDMI_BORROW_MODE { -TB_BORROW_MODE_NONE = 0x00000000, -TB_BORROW_MODE_ACTIVE = 0x00000001, -TB_BORROW_MODE_BLANK = 0x00000002, -TB_BORROW_MODE_RESERVED = 0x00000003, -} HDMI_BORROW_MODE; - -/* - * HDMI_TB_ENC_ACP_SEND enum - */ - -typedef enum HDMI_TB_ENC_ACP_SEND { -TB_ACP_NOT_SEND = 0x00000000, -TB_ACP_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_ACP_SEND; - -/* - * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum - */ - -typedef enum HDMI_TB_ENC_ACR_AUDIO_PRIORITY { -TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000, -TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001, -} HDMI_TB_ENC_ACR_AUDIO_PRIORITY; - -/* - * HDMI_TB_ENC_ACR_CONT enum - */ - -typedef enum HDMI_TB_ENC_ACR_CONT { -TB_ACR_CONT_DISABLE = 0x00000000, -TB_ACR_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_ACR_CONT; - -/* - * HDMI_TB_ENC_ACR_N_MULTIPLE enum - */ - -typedef enum HDMI_TB_ENC_ACR_N_MULTIPLE { -TB_ACR_0_MULTIPLE_RESERVED = 0x00000000, -TB_ACR_1_MULTIPLE = 0x00000001, -TB_ACR_2_MULTIPLE = 0x00000002, -TB_ACR_3_MULTIPLE_RESERVED = 0x00000003, -TB_ACR_4_MULTIPLE = 0x00000004, -TB_ACR_5_MULTIPLE_RESERVED = 0x00000005, -TB_ACR_6_MULTIPLE_RESERVED = 0x00000006, -TB_ACR_7_MULTIPLE_RESERVED = 0x00000007, -} HDMI_TB_ENC_ACR_N_MULTIPLE; - -/* - * HDMI_TB_ENC_ACR_SELECT enum - */ - -typedef enum HDMI_TB_ENC_ACR_SELECT { -TB_ACR_SELECT_HW = 0x00000000, -TB_ACR_SELECT_32K = 0x00000001, -TB_ACR_SELECT_44K = 0x00000002, -TB_ACR_SELECT_48K = 0x00000003, -} HDMI_TB_ENC_ACR_SELECT; - -/* - * HDMI_TB_ENC_ACR_SEND enum - */ - -typedef enum HDMI_TB_ENC_ACR_SEND { -TB_ACR_NOT_SEND = 0x00000000, -TB_ACR_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_ACR_SEND; - -/* - * HDMI_TB_ENC_ACR_SOURCE enum - */ - -typedef enum HDMI_TB_ENC_ACR_SOURCE { -TB_ACR_SOURCE_HW = 0x00000000, -TB_ACR_SOURCE_SW = 0x00000001, -} HDMI_TB_ENC_ACR_SOURCE; - -/* - * HDMI_TB_ENC_AUDIO_INFO_CONT enum - */ - -typedef enum HDMI_TB_ENC_AUDIO_INFO_CONT { -TB_AUDIO_INFO_CONT_DISABLE = 0x00000000, -TB_AUDIO_INFO_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_AUDIO_INFO_CONT; - -/* - * HDMI_TB_ENC_AUDIO_INFO_SEND enum - */ - -typedef enum HDMI_TB_ENC_AUDIO_INFO_SEND { -TB_AUDIO_INFO_NOT_SEND = 0x00000000, -TB_AUDIO_INFO_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_AUDIO_INFO_SEND; - -/* - * HDMI_TB_ENC_CRC_SRC_SEL enum - */ - -typedef enum HDMI_TB_ENC_CRC_SRC_SEL { -TB_CRC_TB_ENC_INPUT = 0x00000000, -TB_CRC_DSC_PACKER = 0x00000001, -TB_CRC_DEEP_COLOR_PACKER = 0x00000002, -TB_CRC_ENCRYPTOR_INPUT = 0x00000003, -} HDMI_TB_ENC_CRC_SRC_SEL; - -/* - * HDMI_TB_ENC_CRC_TYPE enum - */ - -typedef enum HDMI_TB_ENC_CRC_TYPE { -TB_CRC_ALL_TRIBYTES = 0x00000000, -TB_CRC_ACTIVE_TRIBYTES = 0x00000001, -TB_CRC_DATAISLAND_TRIBYTES = 0x00000002, -TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 0x00000003, -} HDMI_TB_ENC_CRC_TYPE; - -/* - * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum - */ - -typedef enum HDMI_TB_ENC_DEEP_COLOR_DEPTH { -TB_DEEP_COLOR_DEPTH_24BPP = 0x00000000, -TB_DEEP_COLOR_DEPTH_30BPP = 0x00000001, -TB_DEEP_COLOR_DEPTH_36BPP = 0x00000002, -TB_DEEP_COLOR_DEPTH_RESERVED = 0x00000003, -} HDMI_TB_ENC_DEEP_COLOR_DEPTH; - -/* - * HDMI_TB_ENC_DEFAULT_PAHSE enum - */ - -typedef enum HDMI_TB_ENC_DEFAULT_PAHSE { -TB_DEFAULT_PHASE_IS_0 = 0x00000000, -TB_DEFAULT_PHASE_IS_1 = 0x00000001, -} HDMI_TB_ENC_DEFAULT_PAHSE; - -/* - * HDMI_TB_ENC_DSC_MODE enum - */ - -typedef enum HDMI_TB_ENC_DSC_MODE { -TB_DSC_DISABLE = 0x00000000, -TB_DSC_444_RGB = 0x00000001, -TB_DSC_NATIVE_422_420 = 0x00000002, -} HDMI_TB_ENC_DSC_MODE; - -/* - * HDMI_TB_ENC_ENABLE enum - */ - -typedef enum HDMI_TB_ENC_ENABLE { -TB_DISABLE = 0x00000000, -TB_ENABLE = 0x00000001, -} HDMI_TB_ENC_ENABLE; - -/* - * HDMI_TB_ENC_GC_AVMUTE enum - */ - -typedef enum HDMI_TB_ENC_GC_AVMUTE { -TB_GC_AVMUTE_SET = 0x00000000, -TB_GC_AVMUTE_UNSET = 0x00000001, -} HDMI_TB_ENC_GC_AVMUTE; - -/* - * HDMI_TB_ENC_GC_AVMUTE_CONT enum - */ - -typedef enum HDMI_TB_ENC_GC_AVMUTE_CONT { -TB_GC_AVMUTE_CONT_DISABLE = 0x00000000, -TB_GC_AVMUTE_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_GC_AVMUTE_CONT; - -/* - * HDMI_TB_ENC_GC_CONT enum - */ - -typedef enum HDMI_TB_ENC_GC_CONT { -TB_GC_CONT_DISABLE = 0x00000000, -TB_GC_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_GC_CONT; - -/* - * HDMI_TB_ENC_GC_SEND enum - */ - -typedef enum HDMI_TB_ENC_GC_SEND { -TB_GC_NOT_SEND = 0x00000000, -TB_GC_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_GC_SEND; - -/* - * HDMI_TB_ENC_GENERIC_CONT enum - */ - -typedef enum HDMI_TB_ENC_GENERIC_CONT { -TB_GENERIC_CONT_DISABLE = 0x00000000, -TB_GENERIC_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_GENERIC_CONT; - -/* - * HDMI_TB_ENC_GENERIC_LOCK_EN enum - */ - -typedef enum HDMI_TB_ENC_GENERIC_LOCK_EN { -HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0x00000000, -HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 0x00000001, -} HDMI_TB_ENC_GENERIC_LOCK_EN; - -/* - * HDMI_TB_ENC_GENERIC_SEND enum - */ - -typedef enum HDMI_TB_ENC_GENERIC_SEND { -TB_GENERIC_NOT_SEND = 0x00000000, -TB_GENERIC_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_GENERIC_SEND; - -/* - * HDMI_TB_ENC_ISRC_CONT enum - */ - -typedef enum HDMI_TB_ENC_ISRC_CONT { -TB_ISRC_CONT_DISABLE = 0x00000000, -TB_ISRC_CONT_ENABLE = 0x00000001, -} HDMI_TB_ENC_ISRC_CONT; - -/* - * HDMI_TB_ENC_ISRC_SEND enum - */ - -typedef enum HDMI_TB_ENC_ISRC_SEND { -TB_ISRC_NOT_SEND = 0x00000000, -TB_ISRC_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_ISRC_SEND; - -/* - * HDMI_TB_ENC_METADATA_ENABLE enum - */ - -typedef enum HDMI_TB_ENC_METADATA_ENABLE { -TB_METADATA_NOT_SEND = 0x00000000, -TB_METADATA_PKT_SEND = 0x00000001, -} HDMI_TB_ENC_METADATA_ENABLE; - -/* - * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum - */ - -typedef enum HDMI_TB_ENC_PACKET_LINE_REFERENCE { -TB_PKT_LINE_REF_END_OF_ACTIVE = 0x00000000, -TB_PKT_LINE_REF_OTGSOF = 0x00000001, -} HDMI_TB_ENC_PACKET_LINE_REFERENCE; - -/* - * HDMI_TB_ENC_PIXEL_ENCODING enum - */ - -typedef enum HDMI_TB_ENC_PIXEL_ENCODING { -TB_PIXEL_ENCODING_444_RGB = 0x00000000, -TB_PIXEL_ENCODING_422 = 0x00000001, -TB_PIXEL_ENCODING_420 = 0x00000002, -} HDMI_TB_ENC_PIXEL_ENCODING; - -/* - * HDMI_TB_ENC_RESET enum - */ - -typedef enum HDMI_TB_ENC_RESET { -TB_NOT_RESET = 0x00000000, -TB_RESET = 0x00000001, -} HDMI_TB_ENC_RESET; - -/* - * HDMI_TB_ENC_SYNC_PHASE enum - */ - -typedef enum HDMI_TB_ENC_SYNC_PHASE { -TB_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000, -TB_SYNC_PHASE_ON_FRAME_START = 0x00000001, -} HDMI_TB_ENC_SYNC_PHASE; - -/* - * INPUT_FIFO_ERROR_TYPE enum - */ - -typedef enum INPUT_FIFO_ERROR_TYPE { -TB_NO_ERROR_OCCURRED = 0x00000000, -TB_OVERFLOW_OCCURRED = 0x00000001, -} INPUT_FIFO_ERROR_TYPE; - -/******************************************************* - * DP_STREAM_ENC Enums - *******************************************************/ - -/* - * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum - */ - -typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR { -DP_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000, -DP_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001, -DP_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002, -} DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; - -/* - * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum - */ - -typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT { -DP_STREAM_ENC_HARDWARE = 0x00000000, -DP_STREAM_ENC_PROGRAMMABLE = 0x00000001, -} DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT; - -/* - * DP_STREAM_ENC_READ_CLOCK_CONTROL enum - */ - -typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL { -DP_STREAM_ENC_DCCG = 0x00000000, -DP_STREAM_ENC_DISPLAY_PIPE = 0x00000001, -} DP_STREAM_ENC_READ_CLOCK_CONTROL; - -/* - * DP_STREAM_ENC_RESET_CONTROL enum - */ - -typedef enum DP_STREAM_ENC_RESET_CONTROL { -DP_STREAM_ENC_NOT_RESET = 0x00000000, -DP_STREAM_ENC_RESET = 0x00000001, -} DP_STREAM_ENC_RESET_CONTROL; - -/* - * DP_STREAM_ENC_STREAM_ACTIVE enum - */ - -typedef enum DP_STREAM_ENC_STREAM_ACTIVE { -DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000, -DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001, -} DP_STREAM_ENC_STREAM_ACTIVE; - -/******************************************************* - * DP_SYM32_ENC Enums - *******************************************************/ - -/* - * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE { -DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0x00000000, -DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 0x00000001, -} ENUM_DP_SYM32_ENC_AUDIO_MUTE; - -/* - * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE { -DP_SYM32_ENC_ONE_SHOT_MODE = 0x00000000, -DP_SYM32_ENC_CONTINUOUS_MODE = 0x00000001, -} ENUM_DP_SYM32_ENC_CONTINUOUS_MODE; - -/* - * ENUM_DP_SYM32_ENC_CRC_VALID enum - */ - -typedef enum ENUM_DP_SYM32_ENC_CRC_VALID { -DP_SYM32_ENC_CRC_NOT_VALID = 0x00000000, -DP_SYM32_ENC_CRC_VALID = 0x00000001, -} ENUM_DP_SYM32_ENC_CRC_VALID; - -/* - * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum - */ - -typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH { -DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0x00000000, -DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 0x00000001, -DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 0x00000002, -DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 0x00000003, -} ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH; - -/* - * ENUM_DP_SYM32_ENC_ENABLE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_ENABLE { -DP_SYM32_ENC_DISABLE = 0x00000000, -DP_SYM32_ENC_ENABLE = 0x00000001, -} ENUM_DP_SYM32_ENC_ENABLE; - -/* - * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum - */ - -typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED { -DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0x00000000, -DP_SYM32_ENC_GSP_DEADLINE_MISSED = 0x00000001, -} ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED; - -/* - * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum - */ - -typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION { -DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0x00000000, -DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 0x00000001, -} ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION; - -/* - * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE { -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0x00000000, -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 0x00000001, -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 0x00000002, -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 0x00000003, -} ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE; - -/* - * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum - */ - -typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING { -DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0x00000000, -DP_SYM32_ENC_GSP_TRIGGER_PENDING = 0x00000001, -} ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING; - -/* - * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum - */ - -typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM { -DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0x00000000, -DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM; - -/* - * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum - */ - -typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS { -DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0x00000000, -DP_SYM32_ENC_OVERFLOW_OCCURRED = 0x00000001, -} ENUM_DP_SYM32_ENC_OVERFLOW_STATUS; - -/* - * ENUM_DP_SYM32_ENC_PENDING enum - */ - -typedef enum ENUM_DP_SYM32_ENC_PENDING { -DP_SYM32_ENC_NOT_PENDING = 0x00000000, -DP_SYM32_ENC_PENDING = 0x00000001, -} ENUM_DP_SYM32_ENC_PENDING; - -/* - * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum - */ - -typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING { -DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000, -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 0x00000001, -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 0x00000002, -DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 0x00000003, -} ENUM_DP_SYM32_ENC_PIXEL_ENCODING; - -/* - * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE { -DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0x00000000, -DP_SYM32_ENC_COMPRESSED_FORMAT = 0x00000001, -} ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE; - -/* - * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum - */ - -typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM { -DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0x00000000, -DP_SYM32_ENC_POWER_STATE_ENUM_LS = 0x00000001, -DP_SYM32_ENC_POWER_STATE_ENUM_DS = 0x00000002, -DP_SYM32_ENC_POWER_STATE_ENUM_SD = 0x00000003, -} ENUM_DP_SYM32_ENC_POWER_STATE_ENUM; - -/* - * ENUM_DP_SYM32_ENC_RESET enum - */ - -typedef enum ENUM_DP_SYM32_ENC_RESET { -DP_SYM32_ENC_NOT_RESET = 0x00000000, -DP_SYM32_ENC_RESET = 0x00000001, -} ENUM_DP_SYM32_ENC_RESET; - -/* - * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum - */ - -typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY { -DP_SYM32_ENC_SDP_LOW_PRIORITY = 0x00000000, -DP_SYM32_ENC_SDP_HIGH_PRIORITY = 0x00000001, -} ENUM_DP_SYM32_ENC_SDP_PRIORITY; - -/* - * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum - */ - -typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE { -DP_SYM32_ENC_DP_SOF = 0x00000000, -DP_SYM32_ENC_OTG_SOF = 0x00000001, -} ENUM_DP_SYM32_ENC_SOF_REFERENCE; - -/* - * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum - */ - -typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER { -DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0x00000000, -DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 0x00000001, -DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 0x00000002, -} ENUM_DP_SYM32_ENC_VID_STREAM_DEFER; - -/******************************************************* - * DP_DPHY_SYM32 Enums - *******************************************************/ - -/* - * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT { -DP_DPHY_SYM32_CRC_END_LLCP = 0x00000000, -DP_DPHY_SYM32_CRC_END_PS_ONLY = 0x00000001, -DP_DPHY_SYM32_CRC_END_PS_LT_SR = 0x00000002, -DP_DPHY_SYM32_CRC_END_PS_ANY = 0x00000003, -} ENUM_DP_DPHY_SYM32_CRC_END_EVENT; - -/* - * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT { -DP_DPHY_SYM32_CRC_START_LLCP = 0x00000000, -DP_DPHY_SYM32_CRC_START_PS_ONLY = 0x00000001, -DP_DPHY_SYM32_CRC_START_PS_LT_SR = 0x00000002, -DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 0x00000003, -DP_DPHY_SYM32_CRC_START_TP_START = 0x00000004, -} ENUM_DP_DPHY_SYM32_CRC_START_EVENT; - -/* - * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE { -DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0x00000000, -DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001, -DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 0x00000002, -} ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE; - -/* - * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS { -DP_DPHY_SYM32_CRC_USE_END_EVENT = 0x00000000, -DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 0x00000001, -} ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS; - -/* - * ENUM_DP_DPHY_SYM32_ENABLE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_ENABLE { -DP_DPHY_SYM32_DISABLE = 0x00000000, -DP_DPHY_SYM32_ENABLE = 0x00000001, -} ENUM_DP_DPHY_SYM32_ENABLE; - -/* - * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE { -DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0x00000000, -DP_DPHY_SYM32_ENCRYPT_TYPE1 = 0x00000001, -} ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE; - -/* - * ENUM_DP_DPHY_SYM32_MODE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_MODE { -DP_DPHY_SYM32_LT_TPS1 = 0x00000000, -DP_DPHY_SYM32_LT_TPS2 = 0x00000001, -DP_DPHY_SYM32_ACTIVE = 0x00000002, -DP_DPHY_SYM32_TEST = 0x00000003, -} ENUM_DP_DPHY_SYM32_MODE; - -/* - * ENUM_DP_DPHY_SYM32_NUM_LANES enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES { -DP_DPHY_SYM32_1LANE = 0x00000000, -DP_DPHY_SYM32_2LANE = 0x00000001, -DP_DPHY_SYM32_RESERVED = 0x00000002, -DP_DPHY_SYM32_4LANE = 0x00000003, -} ENUM_DP_DPHY_SYM32_NUM_LANES; - -/* - * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING { -DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0x00000000, -DP_DPHY_SYM32_RATE_UPDATE_PENDING = 0x00000001, -} ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING; - -/* - * ENUM_DP_DPHY_SYM32_RESET enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_RESET { -DP_DPHY_SYM32_NOT_RESET = 0x00000000, -DP_DPHY_SYM32_RESET = 0x00000001, -} ENUM_DP_DPHY_SYM32_RESET; - -/* - * ENUM_DP_DPHY_SYM32_RESET_STATUS enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS { -DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0x00000000, -DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 0x00000001, -} ENUM_DP_DPHY_SYM32_RESET_STATUS; - -/* - * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE { -DP_DPHY_SYM32_SAT_NO_UPDATE = 0x00000000, -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 0x00000001, -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 0x00000002, -} ENUM_DP_DPHY_SYM32_SAT_UPDATE; - -/* - * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING { -DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0x00000000, -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001, -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002, -} ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING; - -/* - * ENUM_DP_DPHY_SYM32_STATUS enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_STATUS { -DP_DPHY_SYM32_STATUS_IDLE = 0x00000000, -DP_DPHY_SYM32_STATUS_ENABLED = 0x00000001, -} ENUM_DP_DPHY_SYM32_STATUS; - -/* - * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE { -DP_DPHY_SYM32_STREAM_OVR_NONE = 0x00000000, -DP_DPHY_SYM32_STREAM_OVR_REPLACE = 0x00000001, -DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 0x00000002, -} ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE; - -/* - * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE { -DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0x00000000, -DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 0x00000001, -} ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE; - -/* - * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL { -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0x00000000, -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 0x00000001, -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 0x00000002, -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 0x00000003, -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 0x00000004, -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 0x00000005, -} ENUM_DP_DPHY_SYM32_TP_PRBS_SEL; - -/* - * ENUM_DP_DPHY_SYM32_TP_SELECT enum - */ - -typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT { -DP_DPHY_SYM32_TP_SELECT_TPS1 = 0x00000000, -DP_DPHY_SYM32_TP_SELECT_TPS2 = 0x00000001, -DP_DPHY_SYM32_TP_SELECT_PRBS = 0x00000002, -DP_DPHY_SYM32_TP_SELECT_CUSTOM = 0x00000003, -DP_DPHY_SYM32_TP_SELECT_SQUARE = 0x00000004, -} ENUM_DP_DPHY_SYM32_TP_SELECT; - -/******************************************************* - * APG Enums - *******************************************************/ - -/* - * APG_AUDIO_CRC_CONTROL_CH_SEL enum - */ - -typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL { -APG_AUDIO_CRC_CH0_SIG = 0x00000000, -APG_AUDIO_CRC_CH1_SIG = 0x00000001, -APG_AUDIO_CRC_CH2_SIG = 0x00000002, -APG_AUDIO_CRC_CH3_SIG = 0x00000003, -APG_AUDIO_CRC_CH4_SIG = 0x00000004, -APG_AUDIO_CRC_CH5_SIG = 0x00000005, -APG_AUDIO_CRC_CH6_SIG = 0x00000006, -APG_AUDIO_CRC_CH7_SIG = 0x00000007, -APG_AUDIO_CRC_RESERVED_8 = 0x00000008, -APG_AUDIO_CRC_RESERVED_9 = 0x00000009, -APG_AUDIO_CRC_RESERVED_10 = 0x0000000a, -APG_AUDIO_CRC_RESERVED_11 = 0x0000000b, -APG_AUDIO_CRC_RESERVED_12 = 0x0000000c, -APG_AUDIO_CRC_RESERVED_13 = 0x0000000d, -APG_AUDIO_CRC_RESERVED_14 = 0x0000000e, -APG_AUDIO_CRC_RESERVED_15 = 0x0000000f, -} APG_AUDIO_CRC_CONTROL_CH_SEL; - -/* - * APG_AUDIO_CRC_CONTROL_CONT enum - */ - -typedef enum APG_AUDIO_CRC_CONTROL_CONT { -APG_AUDIO_CRC_ONESHOT = 0x00000000, -APG_AUDIO_CRC_CONTINUOUS = 0x00000001, -} APG_AUDIO_CRC_CONTROL_CONT; - -/* - * APG_DBG_ACP_TYPE enum - */ - -typedef enum APG_DBG_ACP_TYPE { -APG_ACP_TYPE_GENERIC_AUDIO = 0x00000000, -APG_ACP_TYPE_ICE60958_AUDIO = 0x00000001, -APG_ACP_TYPE_DVD_AUDIO = 0x00000002, -APG_ACP_TYPE_SUPER_AUDIO_CD = 0x00000003, -} APG_DBG_ACP_TYPE; - -/* - * APG_DBG_AUDIO_DTO_BASE enum - */ - -typedef enum APG_DBG_AUDIO_DTO_BASE { -BASE_RATE_48KHZ = 0x00000000, -BASE_RATE_44P1KHZ = 0x00000001, -} APG_DBG_AUDIO_DTO_BASE; - -/* - * APG_DBG_AUDIO_DTO_DIV enum - */ - -typedef enum APG_DBG_AUDIO_DTO_DIV { -DIVISOR_BY1 = 0x00000000, -DIVISOR_BY2_RESERVED = 0x00000001, -DIVISOR_BY3 = 0x00000002, -DIVISOR_BY4_RESERVED = 0x00000003, -DIVISOR_BY5_RESERVED = 0x00000004, -DIVISOR_BY6_RESERVED = 0x00000005, -DIVISOR_BY7_RESERVED = 0x00000006, -DIVISOR_BY8_RESERVED = 0x00000007, -} APG_DBG_AUDIO_DTO_DIV; - -/* - * APG_DBG_AUDIO_DTO_MULTI enum - */ - -typedef enum APG_DBG_AUDIO_DTO_MULTI { -MULTIPLE_BY1 = 0x00000000, -MULTIPLE_BY2 = 0x00000001, -MULTIPLE_BY3_RESERVED = 0x00000002, -MULTIPLE_BY4 = 0x00000003, -MULTIPLE_RESERVED = 0x00000004, -} APG_DBG_AUDIO_DTO_MULTI; - -/* - * APG_DBG_MUX_SEL enum - */ - -typedef enum APG_DBG_MUX_SEL { -APG_FUNCTIONAL_MODE = 0x00000000, -APG_DEBUG_AUDIO_MODE = 0x00000001, -} APG_DBG_MUX_SEL; - -/* - * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum - */ - -typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE { -APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000, -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001, -} APG_DP_ASP_CHANNEL_COUNT_OVERRIDE; - -/* - * APG_MEM_POWER_STATE enum - */ - -typedef enum APG_MEM_POWER_STATE { -APG_MEM_POWER_STATE_ON = 0x00000000, -APG_MEM_POWER_STATE_LS = 0x00000001, -APG_MEM_POWER_STATE_DS = 0x00000002, -APG_MEM_POWER_STATE_SD = 0x00000003, -} APG_MEM_POWER_STATE; - -/* - * APG_MEM_PWR_DIS_CTRL enum - */ - -typedef enum APG_MEM_PWR_DIS_CTRL { -APG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000, -APG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001, -} APG_MEM_PWR_DIS_CTRL; - -/* - * APG_MEM_PWR_FORCE_CTRL enum - */ - -typedef enum APG_MEM_PWR_FORCE_CTRL { -APG_MEM_NO_FORCE_REQUEST = 0x00000000, -APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -APG_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} APG_MEM_PWR_FORCE_CTRL; - -/* - * APG_PACKET_CONTROL_ACP_SOURCE enum - */ - -typedef enum APG_PACKET_CONTROL_ACP_SOURCE { -APG_ACP_SOURCE_NO_OVERRIDE = 0x00000000, -APG_ACP_OVERRIDE = 0x00000001, -} APG_PACKET_CONTROL_ACP_SOURCE; - -/* - * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum - */ - -typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE { -APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0x00000000, -APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 0x00000001, -} APG_PACKET_CONTROL_AUDIO_INFO_SOURCE; - -/* - * APG_RAMP_CONTROL_SIGN enum - */ - -typedef enum APG_RAMP_CONTROL_SIGN { -APG_RAMP_SIGNED = 0x00000000, -APG_RAMP_UNSIGNED = 0x00000001, -} APG_RAMP_CONTROL_SIGN; - -/******************************************************* - * DCIO Enums - *******************************************************/ - -/* - * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum - */ - -typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000, -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001, -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002, -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003, -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004, -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005, -} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; - -/* - * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum - */ - -typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { -DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000, -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001, -DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002, -} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; - -/* - * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum - */ - -typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000, -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001, -} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; - -/* - * DCIO_DBG_ASYNC_4BIT_SEL enum - */ - -typedef enum DCIO_DBG_ASYNC_4BIT_SEL { -DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000, -DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001, -DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002, -DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003, -DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004, -DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005, -DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006, -DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007, -} DCIO_DBG_ASYNC_4BIT_SEL; - -/* - * DCIO_DBG_ASYNC_BLOCK_SEL enum - */ - -typedef enum DCIO_DBG_ASYNC_BLOCK_SEL { -DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000, -DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001, -DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002, -DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 0x00000003, -} DCIO_DBG_ASYNC_BLOCK_SEL; - -/* - * DCIO_DCRXPHY_SOFT_RESET enum - */ - -typedef enum DCIO_DCRXPHY_SOFT_RESET { -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000, -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001, -} DCIO_DCRXPHY_SOFT_RESET; - -/* - * DCIO_DC_GENERICA_SEL enum - */ - -typedef enum DCIO_DC_GENERICA_SEL { -DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001, -DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a, -DCIO_GENERICA_SEL_SYNCEN = 0x0000000b, -} DCIO_DC_GENERICA_SEL; - -/* - * DCIO_DC_GENERICB_SEL enum - */ - -typedef enum DCIO_DC_GENERICB_SEL { -DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001, -DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a, -DCIO_GENERICB_SEL_SYNCEN = 0x0000000b, -} DCIO_DC_GENERICB_SEL; - -/* - * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum - */ - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000, -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001, -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002, -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003, -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004, -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005, -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; - -/* - * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum - */ - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { -DCIO_UNIPHYA_FBDIV_CLK = 0x00000000, -DCIO_UNIPHYB_FBDIV_CLK = 0x00000001, -DCIO_UNIPHYC_FBDIV_CLK = 0x00000002, -DCIO_UNIPHYD_FBDIV_CLK = 0x00000003, -DCIO_UNIPHYE_FBDIV_CLK = 0x00000004, -DCIO_UNIPHYF_FBDIV_CLK = 0x00000005, -DCIO_UNIPHYG_FBDIV_CLK = 0x00000006, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; - -/* - * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum - */ - -typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000, -DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001, -DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002, -DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003, -DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004, -DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005, -DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006, -} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; - -/* - * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum - */ - -typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000, -DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001, -DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002, -DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003, -DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004, -DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005, -DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006, -} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; - -/* - * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum - */ - -typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000, -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001, -} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; - -/* - * DCIO_DC_GPU_TIMER_READ_SELECT enum - */ - -typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003, -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004, -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005, -} DCIO_DC_GPU_TIMER_READ_SELECT; - -/* - * DCIO_DC_GPU_TIMER_START_POSITION enum - */ - -typedef enum DCIO_DC_GPU_TIMER_START_POSITION { -DCIO_GPU_TIMER_START_0_END_27 = 0x00000000, -DCIO_GPU_TIMER_START_1_END_28 = 0x00000001, -DCIO_GPU_TIMER_START_2_END_29 = 0x00000002, -DCIO_GPU_TIMER_START_3_END_30 = 0x00000003, -DCIO_GPU_TIMER_START_4_END_31 = 0x00000004, -DCIO_GPU_TIMER_START_6_END_33 = 0x00000005, -DCIO_GPU_TIMER_START_8_END_35 = 0x00000006, -DCIO_GPU_TIMER_START_10_END_37 = 0x00000007, -} DCIO_DC_GPU_TIMER_START_POSITION; - -/* - * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum - */ - -typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000, -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001, -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002, -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003, -} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; - -/* - * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum - */ - -typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000, -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001, -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002, -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003, -} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; - -/* - * DCIO_DIO_EXT_VSYNC_MASK enum - */ - -typedef enum DCIO_DIO_EXT_VSYNC_MASK { -DCIO_EXT_VSYNC_MASK_NONE = 0x00000000, -DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001, -DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002, -DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003, -DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004, -DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005, -DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006, -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007, -} DCIO_DIO_EXT_VSYNC_MASK; - -/* - * DCIO_DIO_OTG_EXT_VSYNC_MUX enum - */ - -typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX { -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000, -DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001, -DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002, -DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003, -DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004, -DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005, -DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006, -DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007, -} DCIO_DIO_OTG_EXT_VSYNC_MUX; - -/* - * DCIO_DPCS_INTERRUPT_MASK enum - */ - -typedef enum DCIO_DPCS_INTERRUPT_MASK { -DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000, -DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001, -} DCIO_DPCS_INTERRUPT_MASK; - -/* - * DCIO_DPCS_INTERRUPT_TYPE enum - */ - -typedef enum DCIO_DPCS_INTERRUPT_TYPE { -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000, -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001, -} DCIO_DPCS_INTERRUPT_TYPE; - -/* - * DCIO_DSYNC_SOFT_RESET enum - */ - -typedef enum DCIO_DSYNC_SOFT_RESET { -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000, -DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001, -} DCIO_DSYNC_SOFT_RESET; - -/* - * DCIO_GENLK_CLK_GSL_MASK enum - */ - -typedef enum DCIO_GENLK_CLK_GSL_MASK { -DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000, -DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001, -DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002, -} DCIO_GENLK_CLK_GSL_MASK; - -/* - * DCIO_GENLK_VSYNC_GSL_MASK enum - */ - -typedef enum DCIO_GENLK_VSYNC_GSL_MASK { -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000, -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002, -} DCIO_GENLK_VSYNC_GSL_MASK; - -/* - * DCIO_GSL_SEL enum - */ - -typedef enum DCIO_GSL_SEL { -DCIO_GSL_SEL_GROUP_0 = 0x00000000, -DCIO_GSL_SEL_GROUP_1 = 0x00000001, -DCIO_GSL_SEL_GROUP_2 = 0x00000002, -} DCIO_GSL_SEL; - -/* - * DCIO_PHY_HPO_ENC_SRC_SEL enum - */ - -typedef enum DCIO_PHY_HPO_ENC_SRC_SEL { -HPO_SRC0 = 0x00000000, -HPO_SRC_RESERVED = 0x00000001, -} DCIO_PHY_HPO_ENC_SRC_SEL; - -/* - * DCIO_SWAPLOCK_A_GSL_MASK enum - */ - -typedef enum DCIO_SWAPLOCK_A_GSL_MASK { -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000, -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001, -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002, -} DCIO_SWAPLOCK_A_GSL_MASK; - -/* - * DCIO_SWAPLOCK_B_GSL_MASK enum - */ - -typedef enum DCIO_SWAPLOCK_B_GSL_MASK { -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000, -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001, -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002, -} DCIO_SWAPLOCK_B_GSL_MASK; - -/* - * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum - */ - -typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002, -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003, -} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; - -/* - * DCIO_UNIPHY_IMPCAL_SEL enum - */ - -typedef enum DCIO_UNIPHY_IMPCAL_SEL { -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000, -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001, -} DCIO_UNIPHY_IMPCAL_SEL; - -/* - * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum - */ - -typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000, -DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001, -} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; - -/* - * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum - */ - -typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000, -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001, -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002, -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003, -} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; - -/******************************************************* - * DCIO_CHIP Enums - *******************************************************/ - -/* - * DCIOCHIP_AUX_ALL_PWR_OK enum - */ - -typedef enum DCIOCHIP_AUX_ALL_PWR_OK { -DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000, -DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001, -} DCIOCHIP_AUX_ALL_PWR_OK; - -/* - * DCIOCHIP_AUX_CSEL0P9 enum - */ - -typedef enum DCIOCHIP_AUX_CSEL0P9 { -DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000, -DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001, -} DCIOCHIP_AUX_CSEL0P9; - -/* - * DCIOCHIP_AUX_CSEL1P1 enum - */ - -typedef enum DCIOCHIP_AUX_CSEL1P1 { -DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000, -DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001, -} DCIOCHIP_AUX_CSEL1P1; - -/* - * DCIOCHIP_AUX_FALLSLEWSEL enum - */ - -typedef enum DCIOCHIP_AUX_FALLSLEWSEL { -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000, -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001, -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002, -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003, -} DCIOCHIP_AUX_FALLSLEWSEL; - -/* - * DCIOCHIP_AUX_HYS_TUNE enum - */ - -typedef enum DCIOCHIP_AUX_HYS_TUNE { -DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000, -DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001, -DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002, -DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003, -} DCIOCHIP_AUX_HYS_TUNE; - -/* - * DCIOCHIP_AUX_RECEIVER_SEL enum - */ - -typedef enum DCIOCHIP_AUX_RECEIVER_SEL { -DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000, -DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001, -DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002, -DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003, -} DCIOCHIP_AUX_RECEIVER_SEL; - -/* - * DCIOCHIP_AUX_RSEL0P9 enum - */ - -typedef enum DCIOCHIP_AUX_RSEL0P9 { -DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000, -DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001, -} DCIOCHIP_AUX_RSEL0P9; - -/* - * DCIOCHIP_AUX_RSEL1P1 enum - */ - -typedef enum DCIOCHIP_AUX_RSEL1P1 { -DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000, -DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001, -} DCIOCHIP_AUX_RSEL1P1; - -/* - * DCIOCHIP_AUX_SPIKESEL enum - */ - -typedef enum DCIOCHIP_AUX_SPIKESEL { -DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000, -DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001, -} DCIOCHIP_AUX_SPIKESEL; - -/* - * DCIOCHIP_AUX_VOD_TUNE enum - */ - -typedef enum DCIOCHIP_AUX_VOD_TUNE { -DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000, -DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001, -DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002, -DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003, -} DCIOCHIP_AUX_VOD_TUNE; - -/* - * DCIOCHIP_GPIO_MASK_EN enum - */ - -typedef enum DCIOCHIP_GPIO_MASK_EN { -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000, -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001, -} DCIOCHIP_GPIO_MASK_EN; - -/* - * DCIOCHIP_HPD_SEL enum - */ - -typedef enum DCIOCHIP_HPD_SEL { -DCIOCHIP_HPD_SEL_ASYNC = 0x00000000, -DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001, -} DCIOCHIP_HPD_SEL; - -/* - * DCIOCHIP_I2C_COMPSEL enum - */ - -typedef enum DCIOCHIP_I2C_COMPSEL { -DCIOCHIP_I2C_REC_SCHMIT = 0x00000000, -DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001, -} DCIOCHIP_I2C_COMPSEL; - -/* - * DCIOCHIP_I2C_FALLSLEWSEL enum - */ - -typedef enum DCIOCHIP_I2C_FALLSLEWSEL { -DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000, -DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001, -DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002, -DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003, -} DCIOCHIP_I2C_FALLSLEWSEL; - -/* - * DCIOCHIP_I2C_RECEIVER_SEL enum - */ - -typedef enum DCIOCHIP_I2C_RECEIVER_SEL { -DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000, -DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001, -DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002, -DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003, -} DCIOCHIP_I2C_RECEIVER_SEL; - -/* - * DCIOCHIP_I2C_VPH_1V2_EN enum - */ - -typedef enum DCIOCHIP_I2C_VPH_1V2_EN { -DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000, -DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001, -} DCIOCHIP_I2C_VPH_1V2_EN; - -/* - * DCIOCHIP_INVERT enum - */ - -typedef enum DCIOCHIP_INVERT { -DCIOCHIP_POL_NON_INVERT = 0x00000000, -DCIOCHIP_POL_INVERT = 0x00000001, -} DCIOCHIP_INVERT; - -/* - * DCIOCHIP_MASK enum - */ - -typedef enum DCIOCHIP_MASK { -DCIOCHIP_MASK_DISABLE = 0x00000000, -DCIOCHIP_MASK_ENABLE = 0x00000001, -} DCIOCHIP_MASK; - -/* - * DCIOCHIP_PAD_MODE enum - */ - -typedef enum DCIOCHIP_PAD_MODE { -DCIOCHIP_PAD_MODE_DDC = 0x00000000, -DCIOCHIP_PAD_MODE_DP = 0x00000001, -} DCIOCHIP_PAD_MODE; - -/* - * DCIOCHIP_PD_EN enum - */ - -typedef enum DCIOCHIP_PD_EN { -DCIOCHIP_PD_EN_NOTALLOW = 0x00000000, -DCIOCHIP_PD_EN_ALLOW = 0x00000001, -} DCIOCHIP_PD_EN; - -/* - * DCIOCHIP_REF_27_SRC_SEL enum - */ - -typedef enum DCIOCHIP_REF_27_SRC_SEL { -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000, -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001, -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002, -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003, -} DCIOCHIP_REF_27_SRC_SEL; - -/******************************************************* - * PWRSEQ Enums - *******************************************************/ - -/* - * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum - */ - -typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000, -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001, -} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; - -/* - * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum - */ - -typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN { -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000, -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001, -} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN; - -/* - * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum - */ - -typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000, -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001, -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002, -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003, -} PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; - -/* - * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum - */ - -typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN { -PWRSEQ_BL_PWM_DISABLE = 0x00000000, -PWRSEQ_BL_PWM_ENABLE = 0x00000001, -} PWRSEQ_BL_PWM_CNTL_BL_PWM_EN; - -/* - * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum - */ - -typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { -PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0x00000000, -PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 0x00000001, -} PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; - -/* - * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum - */ - -typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000, -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001, -} PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; - -/* - * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum - */ - -typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000, -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001, -} PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; - -/* - * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum - */ - -typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK { -PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000, -PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001, -} PWRSEQ_BL_PWM_GRP1_REG_LOCK; - -/* - * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum - */ - -typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START { -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000, -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001, -} PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START; - -/* - * PWRSEQ_GPIO_MASK_EN enum - */ - -typedef enum PWRSEQ_GPIO_MASK_EN { -PWRSEQ_GPIO_MASK_EN_HARDWARE = 0x00000000, -PWRSEQ_GPIO_MASK_EN_SOFTWARE = 0x00000001, -} PWRSEQ_GPIO_MASK_EN; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON { -PWRSEQ_PANEL_BLON_OFF = 0x00000000, -PWRSEQ_PANEL_BLON_ON = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL { -PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0x00000000, -PWRSEQ_PANEL_BLON_POL_INVERT = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON { -PWRSEQ_PANEL_DIGON_OFF = 0x00000000, -PWRSEQ_PANEL_DIGON_ON = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL { -PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0x00000000, -PWRSEQ_PANEL_DIGON_POL_INVERT = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL { -PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0x00000000, -PWRSEQ_PANEL_SYNCEN_POL_INVERT = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL; - -/* - * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE { -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000, -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE; - -/* - * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum - */ - -typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN { -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0x00000000, -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001, -} PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN; - -/******************************************************* - * AZCONTROLLER Enums - *******************************************************/ - -/* - * AZ_CORB_SIZE enum - */ - -typedef enum AZ_CORB_SIZE { -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000, -AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001, -AZ_CORB_SIZE_256ENTRIES = 0x00000002, -AZ_CORB_SIZE_RESERVED = 0x00000003, -} AZ_CORB_SIZE; - -/* - * AZ_GLOBAL_CAPABILITIES enum - */ - -typedef enum AZ_GLOBAL_CAPABILITIES { -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000, -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001, -} AZ_GLOBAL_CAPABILITIES; - -/* - * AZ_RIRB_SIZE enum - */ - -typedef enum AZ_RIRB_SIZE { -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000, -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001, -AZ_RIRB_SIZE_256ENTRIES = 0x00000002, -AZ_RIRB_SIZE_UNDEFINED = 0x00000003, -} AZ_RIRB_SIZE; - -/* - * AZ_RIRB_WRITE_POINTER_RESET enum - */ - -typedef enum AZ_RIRB_WRITE_POINTER_RESET { -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000, -AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001, -} AZ_RIRB_WRITE_POINTER_RESET; - -/* - * AZ_STATE_CHANGE_STATUS enum - */ - -typedef enum AZ_STATE_CHANGE_STATUS { -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000, -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001, -} AZ_STATE_CHANGE_STATUS; - -/* - * CORB_READ_POINTER_RESET enum - */ - -typedef enum CORB_READ_POINTER_RESET { -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000, -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001, -} CORB_READ_POINTER_RESET; - -/* - * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum - */ - -typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000, -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001, -} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; - -/* - * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum - */ - -typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000, -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001, -} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; - -/* - * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum - */ - -typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000, -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001, -} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; - -/* - * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum - */ - -typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000, -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001, -} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; - -/* - * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum - */ - -typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000, -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001, -} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; - -/* - * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum - */ - -typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000, -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001, -} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; - -/* - * GLOBAL_CONTROL_CONTROLLER_RESET enum - */ - -typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000, -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001, -} GLOBAL_CONTROL_CONTROLLER_RESET; - -/* - * GLOBAL_CONTROL_FLUSH_CONTROL enum - */ - -typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000, -FLUSH_CONTROL_FLUSH_STARTED = 0x00000001, -} GLOBAL_CONTROL_FLUSH_CONTROL; - -/* - * GLOBAL_STATUS_FLUSH_STATUS enum - */ - -typedef enum GLOBAL_STATUS_FLUSH_STATUS { -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000, -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001, -} GLOBAL_STATUS_FLUSH_STATUS; - -/* - * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum - */ - -typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000, -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001, -} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; - -/* - * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum - */ - -typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000, -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001, -} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; - -/* - * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum - */ - -typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, -} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; - -/* - * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum - */ - -typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000, -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001, -} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; - -/* - * STREAM_0_SYNCHRONIZATION enum - */ - -typedef enum STREAM_0_SYNCHRONIZATION { -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, -} STREAM_0_SYNCHRONIZATION; - -/* - * STREAM_10_SYNCHRONIZATION enum - */ - -typedef enum STREAM_10_SYNCHRONIZATION { -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_10_SYNCHRONIZATION; - -/* - * STREAM_11_SYNCHRONIZATION enum - */ - -typedef enum STREAM_11_SYNCHRONIZATION { -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_11_SYNCHRONIZATION; - -/* - * STREAM_12_SYNCHRONIZATION enum - */ - -typedef enum STREAM_12_SYNCHRONIZATION { -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_12_SYNCHRONIZATION; - -/* - * STREAM_13_SYNCHRONIZATION enum - */ - -typedef enum STREAM_13_SYNCHRONIZATION { -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_13_SYNCHRONIZATION; - -/* - * STREAM_14_SYNCHRONIZATION enum - */ - -typedef enum STREAM_14_SYNCHRONIZATION { -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_14_SYNCHRONIZATION; - -/* - * STREAM_15_SYNCHRONIZATION enum - */ - -typedef enum STREAM_15_SYNCHRONIZATION { -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_15_SYNCHRONIZATION; - -/* - * STREAM_1_SYNCHRONIZATION enum - */ - -typedef enum STREAM_1_SYNCHRONIZATION { -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, -} STREAM_1_SYNCHRONIZATION; - -/* - * STREAM_2_SYNCHRONIZATION enum - */ - -typedef enum STREAM_2_SYNCHRONIZATION { -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, -} STREAM_2_SYNCHRONIZATION; - -/* - * STREAM_3_SYNCHRONIZATION enum - */ - -typedef enum STREAM_3_SYNCHRONIZATION { -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000, -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001, -} STREAM_3_SYNCHRONIZATION; - -/* - * STREAM_4_SYNCHRONIZATION enum - */ - -typedef enum STREAM_4_SYNCHRONIZATION { -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_4_SYNCHRONIZATION; - -/* - * STREAM_5_SYNCHRONIZATION enum - */ - -typedef enum STREAM_5_SYNCHRONIZATION { -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_5_SYNCHRONIZATION; - -/* - * STREAM_6_SYNCHRONIZATION enum - */ - -typedef enum STREAM_6_SYNCHRONIZATION { -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_6_SYNCHRONIZATION; - -/* - * STREAM_7_SYNCHRONIZATION enum - */ - -typedef enum STREAM_7_SYNCHRONIZATION { -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_7_SYNCHRONIZATION; - -/* - * STREAM_8_SYNCHRONIZATION enum - */ - -typedef enum STREAM_8_SYNCHRONIZATION { -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_8_SYNCHRONIZATION; - -/* - * STREAM_9_SYNCHRONIZATION enum - */ - -typedef enum STREAM_9_SYNCHRONIZATION { -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000, -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001, -} STREAM_9_SYNCHRONIZATION; - -/******************************************************* - * AZENDPOINT Enums - *******************************************************/ - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; - -/* - * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum - */ - -typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000, -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001, -} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE { -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e, -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f, -} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; - -/* - * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum - */ - -typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000, -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001, -} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; - -/******************************************************* - * AZF0CONTROLLER Enums - *******************************************************/ - -/* - * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum - */ - -typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET { -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000, -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001, -} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; - -/* - * MEM_PWR_DIS_CTRL enum - */ - -typedef enum MEM_PWR_DIS_CTRL { -ENABLE_MEM_PWR_CTRL = 0x00000000, -DISABLE_MEM_PWR_CTRL = 0x00000001, -} MEM_PWR_DIS_CTRL; - -/* - * MEM_PWR_FORCE_CTRL enum - */ - -typedef enum MEM_PWR_FORCE_CTRL { -NO_FORCE_REQUEST = 0x00000000, -FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} MEM_PWR_FORCE_CTRL; - -/* - * MEM_PWR_FORCE_CTRL2 enum - */ - -typedef enum MEM_PWR_FORCE_CTRL2 { -NO_FORCE_REQ = 0x00000000, -FORCE_LIGHT_SLEEP_REQ = 0x00000001, -} MEM_PWR_FORCE_CTRL2; - -/* - * MEM_PWR_SEL_CTRL enum - */ - -typedef enum MEM_PWR_SEL_CTRL { -DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, -DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001, -DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002, -} MEM_PWR_SEL_CTRL; - -/* - * MEM_PWR_SEL_CTRL2 enum - */ - -typedef enum MEM_PWR_SEL_CTRL2 { -DYNAMIC_DEEP_SLEEP_EN = 0x00000000, -DYNAMIC_LIGHT_SLEEP_EN = 0x00000001, -} MEM_PWR_SEL_CTRL2; - -/******************************************************* - * AZF0ROOT Enums - *******************************************************/ - -/* - * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum - */ - -typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006, -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007, -} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; - -/* - * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum - */ - -typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006, -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007, -} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; - -/******************************************************* - * AZINPUTENDPOINT Enums - *******************************************************/ - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; - -/* - * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000, -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; - -/* - * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum - */ - -typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000, -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001, -} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; - -/******************************************************* - * AZROOT Enums - *******************************************************/ - -/* - * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum - */ - -typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000, -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001, -} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; - -/******************************************************* - * AZF0STREAM Enums - *******************************************************/ - -/* - * AZ_LATENCY_COUNTER_CONTROL enum - */ - -typedef enum AZ_LATENCY_COUNTER_CONTROL { -AZ_LATENCY_COUNTER_NO_RESET = 0x00000000, -AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001, -} AZ_LATENCY_COUNTER_CONTROL; - -/******************************************************* - * AZSTREAM Enums - *******************************************************/ - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; - -/* - * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; - -/* - * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005, -} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; - -/* - * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f, -} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; - -/* - * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007, -} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; - -/* - * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004, -} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; - -/* - * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum - */ - -typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000, -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001, -} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; - -/******************************************************* - * AZF0ENDPOINT Enums - *******************************************************/ - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; - -/* - * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; - -/* - * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000, -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001, -} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; - -/* - * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; - -/* - * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum - */ - -typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, -} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; - -/******************************************************* - * AZF0INPUTENDPOINT Enums - *******************************************************/ - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; - -/* - * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; - -/* - * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum - */ - -typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000, -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001, -} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; - -/******************************************************* - * DSCC Enums - *******************************************************/ - -/* - * DSCC_BITS_PER_COMPONENT_ENUM enum - */ - -typedef enum DSCC_BITS_PER_COMPONENT_ENUM { -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, -} DSCC_BITS_PER_COMPONENT_ENUM; - -/* - * DSCC_DSC_VERSION_MAJOR_ENUM enum - */ - -typedef enum DSCC_DSC_VERSION_MAJOR_ENUM { -DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001, -} DSCC_DSC_VERSION_MAJOR_ENUM; - -/* - * DSCC_DSC_VERSION_MINOR_ENUM enum - */ - -typedef enum DSCC_DSC_VERSION_MINOR_ENUM { -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001, -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002, -} DSCC_DSC_VERSION_MINOR_ENUM; - -/* - * DSCC_ENABLE_ENUM enum - */ - -typedef enum DSCC_ENABLE_ENUM { -DSCC_ENABLE_ENUM_DISABLED = 0x00000000, -DSCC_ENABLE_ENUM_ENABLED = 0x00000001, -} DSCC_ENABLE_ENUM; - -/* - * DSCC_ICH_RESET_ENUM enum - */ - -typedef enum DSCC_ICH_RESET_ENUM { -DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001, -DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002, -DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004, -DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008, -} DSCC_ICH_RESET_ENUM; - -/* - * DSCC_LINEBUF_DEPTH_ENUM enum - */ - -typedef enum DSCC_LINEBUF_DEPTH_ENUM { -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008, -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009, -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a, -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b, -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c, -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d, -} DSCC_LINEBUF_DEPTH_ENUM; - -/* - * DSCC_MEM_PWR_DIS_ENUM enum - */ - -typedef enum DSCC_MEM_PWR_DIS_ENUM { -DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000, -DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001, -} DSCC_MEM_PWR_DIS_ENUM; - -/* - * DSCC_MEM_PWR_FORCE_ENUM enum - */ - -typedef enum DSCC_MEM_PWR_FORCE_ENUM { -DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000, -DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, -DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002, -DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003, -} DSCC_MEM_PWR_FORCE_ENUM; - -/* - * POWER_STATE_ENUM enum - */ - -typedef enum POWER_STATE_ENUM { -POWER_STATE_ENUM_ON = 0x00000000, -POWER_STATE_ENUM_LS = 0x00000001, -POWER_STATE_ENUM_DS = 0x00000002, -POWER_STATE_ENUM_SD = 0x00000003, -} POWER_STATE_ENUM; - -/******************************************************* - * DSCCIF Enums - *******************************************************/ - -/* - * DSCCIF_BITS_PER_COMPONENT_ENUM enum - */ - -typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM { -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008, -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a, -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c, -} DSCCIF_BITS_PER_COMPONENT_ENUM; - -/* - * DSCCIF_ENABLE_ENUM enum - */ - -typedef enum DSCCIF_ENABLE_ENUM { -DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000, -DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001, -} DSCCIF_ENABLE_ENUM; - -/* - * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum - */ - -typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM { -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000, -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001, -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002, -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003, -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004, -} DSCCIF_INPUT_PIXEL_FORMAT_ENUM; - -/******************************************************* - * DSC_TOP Enums - *******************************************************/ - -/* - * CLOCK_GATING_DISABLE_ENUM enum - */ - -typedef enum CLOCK_GATING_DISABLE_ENUM { -CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000, -CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001, -} CLOCK_GATING_DISABLE_ENUM; - -/* - * ENABLE_ENUM enum - */ - -typedef enum ENABLE_ENUM { -ENABLE_ENUM_DISABLED = 0x00000000, -ENABLE_ENUM_ENABLED = 0x00000001, -} ENABLE_ENUM; - -/* - * TEST_CLOCK_MUX_SELECT_ENUM enum - */ - -typedef enum TEST_CLOCK_MUX_SELECT_ENUM { -TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000, -TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001, -TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002, -TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003, -TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004, -TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005, -} TEST_CLOCK_MUX_SELECT_ENUM; - -/******************************************************* - * DWB_TOP Enums - *******************************************************/ - -/* - * DWB_CRC_CONT_EN_ENUM enum - */ - -typedef enum DWB_CRC_CONT_EN_ENUM { -DWB_CRC_CONT_EN_ONE_SHOT = 0x00000000, -DWB_CRC_CONT_EN_CONT = 0x00000001, -} DWB_CRC_CONT_EN_ENUM; - -/* - * DWB_CRC_SRC_SEL_ENUM enum - */ - -typedef enum DWB_CRC_SRC_SEL_ENUM { -DWB_CRC_SRC_SEL_DWB_IN = 0x00000000, -DWB_CRC_SRC_SEL_OGAM_OUT = 0x00000001, -DWB_CRC_SRC_SEL_DWB_OUT = 0x00000002, -} DWB_CRC_SRC_SEL_ENUM; - -/* - * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum - */ - -typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM { -DWB_DATA_OVERFLOW_INT_TYPE_0 = 0x00000000, -DWB_DATA_OVERFLOW_INT_TYPE_1 = 0x00000001, -} DWB_DATA_OVERFLOW_INT_TYPE_ENUM; - -/* - * DWB_DATA_OVERFLOW_TYPE_ENUM enum - */ - -typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM { -DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0x00000000, -DWB_DATA_OVERFLOW_TYPE_BUFFER = 0x00000001, -DWB_DATA_OVERFLOW_TYPE_VUPDATE = 0x00000002, -DWB_DATA_OVERFLOW_TYPE_VREADY = 0x00000003, -} DWB_DATA_OVERFLOW_TYPE_ENUM; - -/* - * DWB_DEBUG_SEL_ENUM enum - */ - -typedef enum DWB_DEBUG_SEL_ENUM { -DWB_DEBUG_SEL_FC = 0x00000000, -DWB_DEBUG_SEL_RESERVED = 0x00000001, -DWB_DEBUG_SEL_DWBCP = 0x00000002, -DWB_DEBUG_SEL_PERFMON = 0x00000003, -} DWB_DEBUG_SEL_ENUM; - -/* - * DWB_MEM_PWR_FORCE_ENUM enum - */ - -typedef enum DWB_MEM_PWR_FORCE_ENUM { -DWB_MEM_PWR_FORCE_DIS = 0x00000000, -DWB_MEM_PWR_FORCE_LS = 0x00000001, -DWB_MEM_PWR_FORCE_DS = 0x00000002, -DWB_MEM_PWR_FORCE_SD = 0x00000003, -} DWB_MEM_PWR_FORCE_ENUM; - -/* - * DWB_MEM_PWR_STATE_ENUM enum - */ - -typedef enum DWB_MEM_PWR_STATE_ENUM { -DWB_MEM_PWR_STATE_ON = 0x00000000, -DWB_MEM_PWR_STATE_LS = 0x00000001, -DWB_MEM_PWR_STATE_DS = 0x00000002, -DWB_MEM_PWR_STATE_SD = 0x00000003, -} DWB_MEM_PWR_STATE_ENUM; - -/* - * DWB_TEST_CLK_SEL_ENUM enum - */ - -typedef enum DWB_TEST_CLK_SEL_ENUM { -DWB_TEST_CLK_SEL_R = 0x00000000, -DWB_TEST_CLK_SEL_G = 0x00000001, -DWB_TEST_CLK_SEL_P = 0x00000002, -} DWB_TEST_CLK_SEL_ENUM; - -/* - * FC_EYE_SELECTION_ENUM enum - */ - -typedef enum FC_EYE_SELECTION_ENUM { -FC_EYE_SELECTION_STEREO_DIS = 0x00000000, -FC_EYE_SELECTION_LEFT_EYE = 0x00000001, -FC_EYE_SELECTION_RIGHT_EYE = 0x00000002, -} FC_EYE_SELECTION_ENUM; - -/* - * FC_FRAME_CAPTURE_RATE_ENUM enum - */ - -typedef enum FC_FRAME_CAPTURE_RATE_ENUM { -FC_FRAME_CAPTURE_RATE_FULL = 0x00000000, -FC_FRAME_CAPTURE_RATE_HALF = 0x00000001, -FC_FRAME_CAPTURE_RATE_THIRD = 0x00000002, -FC_FRAME_CAPTURE_RATE_QUARTER = 0x00000003, -} FC_FRAME_CAPTURE_RATE_ENUM; - -/* - * FC_STEREO_EYE_POLARITY_ENUM enum - */ - -typedef enum FC_STEREO_EYE_POLARITY_ENUM { -FC_STEREO_EYE_POLARITY_LEFT = 0x00000000, -FC_STEREO_EYE_POLARITY_RIGHT = 0x00000001, -} FC_STEREO_EYE_POLARITY_ENUM; - -/******************************************************* - * DWBCP Enums - *******************************************************/ - -/* - * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum - */ - -typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM { -DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000, -DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001, -} DWB_GAMUT_REMAP_COEF_FORMAT_ENUM; - -/* - * DWB_GAMUT_REMAP_MODE_ENUM enum - */ - -typedef enum DWB_GAMUT_REMAP_MODE_ENUM { -DWB_GAMUT_REMAP_MODE_BYPASS = 0x00000000, -DWB_GAMUT_REMAP_MODE_COEF_A = 0x00000001, -DWB_GAMUT_REMAP_MODE_COEF_B = 0x00000002, -DWB_GAMUT_REMAP_MODE_RESERVED = 0x00000003, -} DWB_GAMUT_REMAP_MODE_ENUM; - -/* - * DWB_LUT_NUM_SEG enum - */ - -typedef enum DWB_LUT_NUM_SEG { -DWB_SEGMENTS_1 = 0x00000000, -DWB_SEGMENTS_2 = 0x00000001, -DWB_SEGMENTS_4 = 0x00000002, -DWB_SEGMENTS_8 = 0x00000003, -DWB_SEGMENTS_16 = 0x00000004, -DWB_SEGMENTS_32 = 0x00000005, -DWB_SEGMENTS_64 = 0x00000006, -DWB_SEGMENTS_128 = 0x00000007, -} DWB_LUT_NUM_SEG; - -/* - * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum - */ - -typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM { -DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0x00000000, -DWB_OGAM_LUT_CONFIG_MODE_SAME = 0x00000001, -} DWB_OGAM_LUT_CONFIG_MODE_ENUM; - -/* - * DWB_OGAM_LUT_HOST_SEL_ENUM enum - */ - -typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM { -DWB_OGAM_LUT_HOST_SEL_RAMA = 0x00000000, -DWB_OGAM_LUT_HOST_SEL_RAMB = 0x00000001, -} DWB_OGAM_LUT_HOST_SEL_ENUM; - -/* - * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum - */ - -typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM { -DWB_OGAM_LUT_READ_COLOR_SEL_B = 0x00000000, -DWB_OGAM_LUT_READ_COLOR_SEL_G = 0x00000001, -DWB_OGAM_LUT_READ_COLOR_SEL_R = 0x00000002, -DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 0x00000003, -} DWB_OGAM_LUT_READ_COLOR_SEL_ENUM; - -/* - * DWB_OGAM_LUT_READ_DBG_ENUM enum - */ - -typedef enum DWB_OGAM_LUT_READ_DBG_ENUM { -DWB_OGAM_LUT_READ_DBG_DISABLE = 0x00000000, -DWB_OGAM_LUT_READ_DBG_ENABLE = 0x00000001, -} DWB_OGAM_LUT_READ_DBG_ENUM; - -/* - * DWB_OGAM_MODE_ENUM enum - */ - -typedef enum DWB_OGAM_MODE_ENUM { -DWB_OGAM_MODE_BYPASS = 0x00000000, -DWB_OGAM_MODE_RESERVED = 0x00000001, -DWB_OGAM_MODE_RAM_LUT_ENABLED = 0x00000002, -} DWB_OGAM_MODE_ENUM; - -/* - * DWB_OGAM_PWL_DISABLE_ENUM enum - */ - -typedef enum DWB_OGAM_PWL_DISABLE_ENUM { -DWB_OGAM_PWL_DISABLE_FALSE = 0x00000000, -DWB_OGAM_PWL_DISABLE_TRUE = 0x00000001, -} DWB_OGAM_PWL_DISABLE_ENUM; - -/* - * DWB_OGAM_SELECT_ENUM enum - */ - -typedef enum DWB_OGAM_SELECT_ENUM { -DWB_OGAM_SELECT_A = 0x00000000, -DWB_OGAM_SELECT_B = 0x00000001, -} DWB_OGAM_SELECT_ENUM; - -/******************************************************* - * RDPCSPIPE Enums - *******************************************************/ - -/* - * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN { -RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0x00000000, -RDPCSPIPE_EXT_PCLK_EN_ENABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN { -RDPCSPIPE_APBCLK_DISABLE = 0x00000000, -RDPCSPIPE_APBCLK_ENABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON { -RDPCS_PIPE_CLK_CLOCK_OFF = 0x00000000, -RDPCS_PIPE_CLK_CLOCK_ON = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN { -RDPCS_PIPE_CLK_DISABLE = 0x00000000, -RDPCS_PIPE_CLK_ENABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS { -RDPCS_PIPE_CLK_GATE_ENABLE = 0x00000000, -RDPCS_PIPE_CLK_GATE_DISABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON { -RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0x00000000, -RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON { -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000, -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN { -RDPCSPIPE_SRAMCLK_DISABLE = 0x00000000, -RDPCSPIPE_SRAMCLK_ENABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS { -RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0x00000000, -RDPCSPIPE_SRAMCLK_GATE_DISABLE = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS; - -/* - * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum - */ - -typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS { -RDPCSPIPE_SRAMCLK_NOT_PASS = 0x00000000, -RDPCSPIPE_SRAMCLK_PASS = 0x00000001, -} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS; - -/* - * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum - */ - -typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN { -RDPCS_PIPE_FIFO_DISABLE = 0x00000000, -RDPCS_PIPE_FIFO_ENABLE = 0x00000001, -} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN; - -/* - * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum - */ - -typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN { -RDPCS_PIPE_FIFO_LANE_DISABLE = 0x00000000, -RDPCS_PIPE_FIFO_LANE_ENABLE = 0x00000001, -} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN; - -/* - * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum - */ - -typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET { -RDPCS_PIPE_SOFT_RESET_DISABLE = 0x00000000, -RDPCS_PIPE_SOFT_RESET_ENABLE = 0x00000001, -} RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET; - -/* - * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum - */ - -typedef enum RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET { -RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0x00000000, -RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 0x00000001, -} RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET; - -/* - * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum - */ - -typedef enum RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK { -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0x00000000, -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK; - -/* - * RDPCSPIPE_DBG_OCLA_SEL enum - */ - -typedef enum RDPCSPIPE_DBG_OCLA_SEL { -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0x00000000, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 0x00000001, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 0x00000002, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 0x00000003, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 0x00000004, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 0x00000005, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 0x00000006, -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 0x00000007, -} RDPCSPIPE_DBG_OCLA_SEL; - -/* - * RDPCSPIPE_ENC_TYPE enum - */ - -typedef enum RDPCSPIPE_ENC_TYPE { -HDMI_TMDS_OR_DP_8B10B = 0x00000000, -HDMI_FRL = 0x00000001, -DP_128B132B = 0x00000002, -} RDPCSPIPE_ENC_TYPE; - -/* - * RDPCSPIPE_FIFO_EMPTY enum - */ - -typedef enum RDPCSPIPE_FIFO_EMPTY { -RDPCSPIPE_FIFO_NOT_EMPTY = 0x00000000, -RDPCSPIPE_FIFO_IS_EMPTY = 0x00000001, -} RDPCSPIPE_FIFO_EMPTY; - -/* - * RDPCSPIPE_FIFO_FULL enum - */ - -typedef enum RDPCSPIPE_FIFO_FULL { -RDPCSPIPE_FIFO_NOT_FULL = 0x00000000, -RDPCSPIPE_FIFO_IS_FULL = 0x00000001, -} RDPCSPIPE_FIFO_FULL; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK { -RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0x00000000, -RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE { -RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0x00000000, -RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK { -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000, -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE { -RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000, -RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK { -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000, -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK { -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0x00000000, -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK; - -/* - * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum - */ - -typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK { -RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000, -RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK; - -/* - * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum - */ - -typedef enum RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK { -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0x00000000, -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 0x00000001, -} RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK; - -/* - * RDPCSPIPE_PACK_MODE enum - */ - -typedef enum RDPCSPIPE_PACK_MODE { -TIGHT_PACK = 0x00000000, -LOOSE_PACK = 0x00000001, -} RDPCSPIPE_PACK_MODE; - -/* - * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL { -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0x00000000, -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 0x00000001, -} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL; - -/* - * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL { -RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0x00000000, -RDPCSPIPE_PHY_CR_PARA_SEL_CR = 0x00000001, -} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL; - -/* - * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE { -RDPCSPIPE_PHY_REF_RANGE_0 = 0x00000000, -RDPCSPIPE_PHY_REF_RANGE_1 = 0x00000001, -RDPCSPIPE_PHY_REF_RANGE_2 = 0x00000002, -RDPCSPIPE_PHY_REF_RANGE_3 = 0x00000003, -RDPCSPIPE_PHY_REF_RANGE_4 = 0x00000004, -RDPCSPIPE_PHY_REF_RANGE_5 = 0x00000005, -RDPCSPIPE_PHY_REF_RANGE_6 = 0x00000006, -RDPCSPIPE_PHY_REF_RANGE_7 = 0x00000007, -} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE; - -/* - * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE { -RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0x00000000, -RDPCSPIPE_SRAM_EXT_LD_DONE = 0x00000001, -} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE; - -/* - * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE { -RDPCSPIPE_SRAM_INIT_NOT_DONE = 0x00000000, -RDPCSPIPE_SRAM_INIT_DONE = 0x00000001, -} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE; - -/* - * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV { -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000, -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001, -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002, -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003, -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004, -} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV; - -/* - * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV { -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000, -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001, -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002, -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003, -} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV; - -/* - * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV { -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006, -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007, -} RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV; - -/* - * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL { -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0x00000000, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 0x00000001, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 0x00000002, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 0x00000003, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 0x00000004, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 0x00000005, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 0x00000006, -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 0x00000007, -} RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL; - -/* - * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT { -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000, -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001, -} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT; - -/* - * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE { -RDPCSPIPE_PHY_DP_TX_RATE = 0x00000000, -RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 0x00000001, -RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 0x00000002, -} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE; - -/* - * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH { -RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0x00000000, -RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 0x00000001, -RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 0x00000002, -RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 0x00000003, -} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH; - -/* - * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum - */ - -typedef enum RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE { -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000, -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 0x00000001, -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002, -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003, -} RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE; - -/* - * RDPCSPIPE_PHY_IF_WIDTH enum - */ - -typedef enum RDPCSPIPE_PHY_IF_WIDTH { -PHY_IF_WIDTH_10BIT = 0x00000000, -PHY_IF_WIDTH_20BIT = 0x00000001, -PHY_IF_WIDTH_40BIT = 0x00000002, -PHY_IF_WIDTH_80BIT = 0x00000003, -} RDPCSPIPE_PHY_IF_WIDTH; - -/* - * RDPCSPIPE_PHY_RATE enum - */ - -typedef enum RDPCSPIPE_PHY_RATE { -PHY_DP_RATE_1P62 = 0x00000000, -PHY_DP_RATE_2P7 = 0x00000001, -PHY_DP_RATE_5P4 = 0x00000002, -PHY_DP_RATE_8P1 = 0x00000003, -PHY_DP_RATE_2P16 = 0x00000004, -PHY_DP_RATE_2P43 = 0x00000005, -PHY_DP_RATE_3P24 = 0x00000006, -PHY_DP_RATE_4P32 = 0x00000007, -PHY_DP_RATE_10P = 0x00000008, -PHY_DP_RATE_13P5 = 0x00000009, -PHY_DP_RATE_20P = 0x0000000a, -PHY_CUSTOM_RATE = 0x0000000f, -} RDPCSPIPE_PHY_RATE; - -/* - * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum - */ - -typedef enum RDPCSPIPE_PHY_REF_ALT_CLK_EN { -RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0x00000000, -RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 0x00000001, -} RDPCSPIPE_PHY_REF_ALT_CLK_EN; - -/* - * RDPCSPIPE_TEST_CLK_SEL enum - */ - -typedef enum RDPCSPIPE_TEST_CLK_SEL { -RDPCSPIPE_TEST_CLK_SEL_NONE = 0x00000000, -RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 0x00000001, -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002, -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003, -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004, -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005, -RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 0x00000006, -RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007, -RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008, -RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009, -RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a, -RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b, -RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c, -RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d, -RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e, -RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f, -RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 0x00000010, -RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 0x00000011, -} RDPCSPIPE_TEST_CLK_SEL; - -/* - * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum - */ - -typedef enum RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB { -RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0x00000000, -RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 0x00000001, -} RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB; - -/* - * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum - */ - -typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE { -RDPCSPIPE_MEM_PWR_NO_FORCE = 0x00000000, -RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 0x00000001, -RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 0x00000002, -RDPCSPIPE_MEM_PWR_SHUT_DOWN = 0x00000003, -} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE; - -/* - * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum - */ - -typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE { -RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0x00000000, -RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001, -RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002, -RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003, -} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE; - -/* - * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum - */ - -typedef enum RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK { -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000, -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 0x00000001, -} RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK; - -/******************************************************* - * GDS Enums - *******************************************************/ - -/* - * GDS_PERFCOUNT_SELECT enum - */ - -typedef enum GDS_PERFCOUNT_SELECT { -GDS_PERF_SEL_WR_COMP = 0x00000000, -GDS_PERF_SEL_WBUF_WR = 0x00000001, -GDS_PERF_SEL_SE0_NORET = 0x00000002, -GDS_PERF_SEL_SE0_RET = 0x00000003, -GDS_PERF_SEL_SE0_ORD_CNT = 0x00000004, -GDS_PERF_SEL_SE0_2COMP_REQ = 0x00000005, -GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 0x00000006, -GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 0x00000007, -GDS_PERF_SEL_SE0_GDS_WR_OP = 0x00000008, -GDS_PERF_SEL_SE0_GDS_RD_OP = 0x00000009, -GDS_PERF_SEL_SE0_GDS_ATOM_OP = 0x0000000a, -GDS_PERF_SEL_SE0_GDS_REL_OP = 0x0000000b, -GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 0x0000000c, -GDS_PERF_SEL_SE0_GDS_BYTE_OP = 0x0000000d, -GDS_PERF_SEL_SE0_GDS_SHORT_OP = 0x0000000e, -GDS_PERF_SEL_SE1_NORET = 0x0000000f, -GDS_PERF_SEL_SE1_RET = 0x00000010, -GDS_PERF_SEL_SE1_ORD_CNT = 0x00000011, -GDS_PERF_SEL_SE1_2COMP_REQ = 0x00000012, -GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 0x00000013, -GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 0x00000014, -GDS_PERF_SEL_SE1_GDS_WR_OP = 0x00000015, -GDS_PERF_SEL_SE1_GDS_RD_OP = 0x00000016, -GDS_PERF_SEL_SE1_GDS_ATOM_OP = 0x00000017, -GDS_PERF_SEL_SE1_GDS_REL_OP = 0x00000018, -GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 0x00000019, -GDS_PERF_SEL_SE1_GDS_BYTE_OP = 0x0000001a, -GDS_PERF_SEL_SE1_GDS_SHORT_OP = 0x0000001b, -GDS_PERF_SEL_SE2_NORET = 0x0000001c, -GDS_PERF_SEL_SE2_RET = 0x0000001d, -GDS_PERF_SEL_SE2_ORD_CNT = 0x0000001e, -GDS_PERF_SEL_SE2_2COMP_REQ = 0x0000001f, -GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 0x00000020, -GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 0x00000021, -GDS_PERF_SEL_SE2_GDS_WR_OP = 0x00000022, -GDS_PERF_SEL_SE2_GDS_RD_OP = 0x00000023, -GDS_PERF_SEL_SE2_GDS_ATOM_OP = 0x00000024, -GDS_PERF_SEL_SE2_GDS_REL_OP = 0x00000025, -GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 0x00000026, -GDS_PERF_SEL_SE2_GDS_BYTE_OP = 0x00000027, -GDS_PERF_SEL_SE2_GDS_SHORT_OP = 0x00000028, -GDS_PERF_SEL_SE3_NORET = 0x00000029, -GDS_PERF_SEL_SE3_RET = 0x0000002a, -GDS_PERF_SEL_SE3_ORD_CNT = 0x0000002b, -GDS_PERF_SEL_SE3_2COMP_REQ = 0x0000002c, -GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 0x0000002d, -GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 0x0000002e, -GDS_PERF_SEL_SE3_GDS_WR_OP = 0x0000002f, -GDS_PERF_SEL_SE3_GDS_RD_OP = 0x00000030, -GDS_PERF_SEL_SE3_GDS_ATOM_OP = 0x00000031, -GDS_PERF_SEL_SE3_GDS_REL_OP = 0x00000032, -GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 0x00000033, -GDS_PERF_SEL_SE3_GDS_BYTE_OP = 0x00000034, -GDS_PERF_SEL_SE3_GDS_SHORT_OP = 0x00000035, -GDS_PERF_SEL_SE4_NORET = 0x00000036, -GDS_PERF_SEL_SE4_RET = 0x00000037, -GDS_PERF_SEL_SE4_ORD_CNT = 0x00000038, -GDS_PERF_SEL_SE4_2COMP_REQ = 0x00000039, -GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 0x0000003a, -GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 0x0000003b, -GDS_PERF_SEL_SE4_GDS_WR_OP = 0x0000003c, -GDS_PERF_SEL_SE4_GDS_RD_OP = 0x0000003d, -GDS_PERF_SEL_SE4_GDS_ATOM_OP = 0x0000003e, -GDS_PERF_SEL_SE4_GDS_REL_OP = 0x0000003f, -GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 0x00000040, -GDS_PERF_SEL_SE4_GDS_BYTE_OP = 0x00000041, -GDS_PERF_SEL_SE4_GDS_SHORT_OP = 0x00000042, -GDS_PERF_SEL_SE5_NORET = 0x00000043, -GDS_PERF_SEL_SE5_RET = 0x00000044, -GDS_PERF_SEL_SE5_ORD_CNT = 0x00000045, -GDS_PERF_SEL_SE5_2COMP_REQ = 0x00000046, -GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 0x00000047, -GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 0x00000048, -GDS_PERF_SEL_SE5_GDS_WR_OP = 0x00000049, -GDS_PERF_SEL_SE5_GDS_RD_OP = 0x0000004a, -GDS_PERF_SEL_SE5_GDS_ATOM_OP = 0x0000004b, -GDS_PERF_SEL_SE5_GDS_REL_OP = 0x0000004c, -GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 0x0000004d, -GDS_PERF_SEL_SE5_GDS_BYTE_OP = 0x0000004e, -GDS_PERF_SEL_SE5_GDS_SHORT_OP = 0x0000004f, -GDS_PERF_SEL_SE6_NORET = 0x00000050, -GDS_PERF_SEL_SE6_RET = 0x00000051, -GDS_PERF_SEL_SE6_ORD_CNT = 0x00000052, -GDS_PERF_SEL_SE6_2COMP_REQ = 0x00000053, -GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 0x00000054, -GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 0x00000055, -GDS_PERF_SEL_SE6_GDS_WR_OP = 0x00000056, -GDS_PERF_SEL_SE6_GDS_RD_OP = 0x00000057, -GDS_PERF_SEL_SE6_GDS_ATOM_OP = 0x00000058, -GDS_PERF_SEL_SE6_GDS_REL_OP = 0x00000059, -GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 0x0000005a, -GDS_PERF_SEL_SE6_GDS_BYTE_OP = 0x0000005b, -GDS_PERF_SEL_SE6_GDS_SHORT_OP = 0x0000005c, -GDS_PERF_SEL_SE7_NORET = 0x0000005d, -GDS_PERF_SEL_SE7_RET = 0x0000005e, -GDS_PERF_SEL_SE7_ORD_CNT = 0x0000005f, -GDS_PERF_SEL_SE7_2COMP_REQ = 0x00000060, -GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 0x00000061, -GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 0x00000062, -GDS_PERF_SEL_SE7_GDS_WR_OP = 0x00000063, -GDS_PERF_SEL_SE7_GDS_RD_OP = 0x00000064, -GDS_PERF_SEL_SE7_GDS_ATOM_OP = 0x00000065, -GDS_PERF_SEL_SE7_GDS_REL_OP = 0x00000066, -GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 0x00000067, -GDS_PERF_SEL_SE7_GDS_BYTE_OP = 0x00000068, -GDS_PERF_SEL_SE7_GDS_SHORT_OP = 0x00000069, -GDS_PERF_SEL_GWS_RELEASED = 0x0000006a, -GDS_PERF_SEL_GWS_BYPASS = 0x0000006b, -} GDS_PERFCOUNT_SELECT; - -/******************************************************* - * CB Enums - *******************************************************/ - -/* - * BlendOp enum - */ - -typedef enum BlendOp { -BLEND_ZERO = 0x00000000, -BLEND_ONE = 0x00000001, -BLEND_SRC_COLOR = 0x00000002, -BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, -BLEND_SRC_ALPHA = 0x00000004, -BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, -BLEND_DST_ALPHA = 0x00000006, -BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, -BLEND_DST_COLOR = 0x00000008, -BLEND_ONE_MINUS_DST_COLOR = 0x00000009, -BLEND_SRC_ALPHA_SATURATE = 0x0000000a, -BLEND_CONSTANT_COLOR = 0x0000000b, -BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000c, -BLEND_SRC1_COLOR = 0x0000000d, -BLEND_INV_SRC1_COLOR = 0x0000000e, -BLEND_SRC1_ALPHA = 0x0000000f, -BLEND_INV_SRC1_ALPHA = 0x00000010, -BLEND_CONSTANT_ALPHA = 0x00000011, -BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000012, -} BlendOp; - -/* - * BlendOpt enum - */ - -typedef enum BlendOpt { -FORCE_OPT_AUTO = 0x00000000, -FORCE_OPT_DISABLE = 0x00000001, -FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, -FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, -} BlendOpt; - -/* - * CBMode enum - */ - -typedef enum CBMode { -CB_DISABLE = 0x00000000, -CB_NORMAL = 0x00000001, -CB_ELIMINATE_FAST_CLEAR = 0x00000002, -CB_DCC_DECOMPRESS = 0x00000003, -CB_RESERVED = 0x00000004, -} CBMode; - -/* - * CBPerfClearFilterSel enum - */ - -typedef enum CBPerfClearFilterSel { -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, -} CBPerfClearFilterSel; - -/* - * CBPerfOpFilterSel enum - */ - -typedef enum CBPerfOpFilterSel { -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, -CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, -} CBPerfOpFilterSel; - -/* - * CBPerfSel enum - */ - -typedef enum CBPerfSel { -CB_PERF_SEL_NONE = 0x00000000, -CB_PERF_SEL_DRAWN_PIXEL = 0x00000001, -CB_PERF_SEL_DRAWN_QUAD = 0x00000002, -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000003, -CB_PERF_SEL_DRAWN_TILE = 0x00000004, -CB_PERF_SEL_FILTER_DRAWN_PIXEL = 0x00000005, -CB_PERF_SEL_FILTER_DRAWN_QUAD = 0x00000006, -CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 0x00000007, -CB_PERF_SEL_FILTER_DRAWN_TILE = 0x00000008, -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 0x00000009, -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 0x0000000a, -CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 0x0000000b, -CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 0x0000000c, -CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x0000000d, -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000000e, -CB_PERF_SEL_CC_MC_READ_REQUEST = 0x0000000f, -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000010, -CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 0x00000011, -CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 0x00000012, -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 0x00000013, -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 0x00000014, -CB_PERF_SEL_RESERVED_21 = 0x00000015, -CB_PERF_SEL_RESERVED_22 = 0x00000016, -CB_PERF_SEL_RESERVED_23 = 0x00000017, -CB_PERF_SEL_RESERVED_24 = 0x00000018, -CB_PERF_SEL_RESERVED_25 = 0x00000019, -CB_PERF_SEL_RESERVED_26 = 0x0000001a, -CB_PERF_SEL_RESERVED_27 = 0x0000001b, -CB_PERF_SEL_RESERVED_28 = 0x0000001c, -CB_PERF_SEL_RESERVED_29 = 0x0000001d, -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 0x0000001e, -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 0x0000001f, -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 0x00000020, -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 0x00000021, -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 0x00000022, -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 0x00000023, -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 0x00000024, -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 0x00000025, -CB_PERF_SEL_RESERVED_38 = 0x00000026, -CB_PERF_SEL_RESERVED_39 = 0x00000027, -CB_PERF_SEL_RESERVED_40 = 0x00000028, -CB_PERF_SEL_RESERVED_41 = 0x00000029, -CB_PERF_SEL_RESERVED_42 = 0x0000002a, -CB_PERF_SEL_RESERVED_43 = 0x0000002b, -CB_PERF_SEL_RESERVED_44 = 0x0000002c, -CB_PERF_SEL_RESERVED_45 = 0x0000002d, -CB_PERF_SEL_RESERVED_46 = 0x0000002e, -CB_PERF_SEL_RESERVED_47 = 0x0000002f, -CB_PERF_SEL_RESERVED_48 = 0x00000030, -CB_PERF_SEL_RESERVED_49 = 0x00000031, -CB_PERF_SEL_STATIC_CLOCK_EN = 0x00000032, -CB_PERF_SEL_PERFMON_CLOCK_EN = 0x00000033, -CB_PERF_SEL_BLEND_CLOCK_EN = 0x00000034, -CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 0x00000035, -CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 0x00000036, -CB_PERF_SEL_GRBM_CLOCK_EN = 0x00000037, -CB_PERF_SEL_MEMARB_CLOCK_EN = 0x00000038, -CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 0x00000039, -CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 0x0000003a, -CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 0x0000003b, -CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 0x0000003c, -CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 0x0000003d, -CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 0x0000003e, -CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 0x0000003f, -CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x00000040, -CB_PERF_SEL_RESERVED_65 = 0x00000041, -CB_PERF_SEL_RESERVED_66 = 0x00000042, -CB_PERF_SEL_RESERVED_67 = 0x00000043, -CB_PERF_SEL_RESERVED_68 = 0x00000044, -CB_PERF_SEL_RESERVED_69 = 0x00000045, -CB_PERF_SEL_RESERVED_70 = 0x00000046, -CB_PERF_SEL_RESERVED_71 = 0x00000047, -CB_PERF_SEL_RESERVED_72 = 0x00000048, -CB_PERF_SEL_RESERVED_73 = 0x00000049, -CB_PERF_SEL_RESERVED_74 = 0x0000004a, -CB_PERF_SEL_RESERVED_75 = 0x0000004b, -CB_PERF_SEL_RESERVED_76 = 0x0000004c, -CB_PERF_SEL_RESERVED_77 = 0x0000004d, -CB_PERF_SEL_RESERVED_78 = 0x0000004e, -CB_PERF_SEL_RESERVED_79 = 0x0000004f, -CB_PERF_SEL_RESERVED_80 = 0x00000050, -CB_PERF_SEL_RESERVED_81 = 0x00000051, -CB_PERF_SEL_RESERVED_82 = 0x00000052, -CB_PERF_SEL_RESERVED_83 = 0x00000053, -CB_PERF_SEL_RESERVED_84 = 0x00000054, -CB_PERF_SEL_RESERVED_85 = 0x00000055, -CB_PERF_SEL_RESERVED_86 = 0x00000056, -CB_PERF_SEL_RESERVED_87 = 0x00000057, -CB_PERF_SEL_RESERVED_88 = 0x00000058, -CB_PERF_SEL_RESERVED_89 = 0x00000059, -CB_PERF_SEL_RESERVED_90 = 0x0000005a, -CB_PERF_SEL_RESERVED_91 = 0x0000005b, -CB_PERF_SEL_RESERVED_92 = 0x0000005c, -CB_PERF_SEL_RESERVED_93 = 0x0000005d, -CB_PERF_SEL_RESERVED_94 = 0x0000005e, -CB_PERF_SEL_RESERVED_95 = 0x0000005f, -CB_PERF_SEL_RESERVED_96 = 0x00000060, -CB_PERF_SEL_RESERVED_97 = 0x00000061, -CB_PERF_SEL_RESERVED_98 = 0x00000062, -CB_PERF_SEL_RESERVED_99 = 0x00000063, -CB_PERF_SEL_CC_TAG_HIT = 0x00000064, -CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000065, -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000066, -CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 0x00000067, -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000068, -CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000069, -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000006a, -CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000006b, -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x0000006c, -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x0000006d, -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x0000006e, -CB_PERF_SEL_CC_CACHE_STALL = 0x0000006f, -CB_PERF_SEL_CC_CACHE_FLUSH = 0x00000070, -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x00000071, -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x00000072, -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x00000073, -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000074, -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000075, -CB_PERF_SEL_RESERVED_118 = 0x00000076, -CB_PERF_SEL_RESERVED_119 = 0x00000077, -CB_PERF_SEL_RESERVED_120 = 0x00000078, -CB_PERF_SEL_RESERVED_121 = 0x00000079, -CB_PERF_SEL_RESERVED_122 = 0x0000007a, -CB_PERF_SEL_RESERVED_123 = 0x0000007b, -CB_PERF_SEL_RESERVED_124 = 0x0000007c, -CB_PERF_SEL_RESERVED_125 = 0x0000007d, -CB_PERF_SEL_RESERVED_126 = 0x0000007e, -CB_PERF_SEL_RESERVED_127 = 0x0000007f, -CB_PERF_SEL_RESERVED_128 = 0x00000080, -CB_PERF_SEL_RESERVED_129 = 0x00000081, -CB_PERF_SEL_RESERVED_130 = 0x00000082, -CB_PERF_SEL_RESERVED_131 = 0x00000083, -CB_PERF_SEL_RESERVED_132 = 0x00000084, -CB_PERF_SEL_RESERVED_133 = 0x00000085, -CB_PERF_SEL_RESERVED_134 = 0x00000086, -CB_PERF_SEL_RESERVED_135 = 0x00000087, -CB_PERF_SEL_RESERVED_136 = 0x00000088, -CB_PERF_SEL_RESERVED_137 = 0x00000089, -CB_PERF_SEL_RESERVED_138 = 0x0000008a, -CB_PERF_SEL_RESERVED_139 = 0x0000008b, -CB_PERF_SEL_RESERVED_140 = 0x0000008c, -CB_PERF_SEL_RESERVED_141 = 0x0000008d, -CB_PERF_SEL_RESERVED_142 = 0x0000008e, -CB_PERF_SEL_RESERVED_143 = 0x0000008f, -CB_PERF_SEL_RESERVED_144 = 0x00000090, -CB_PERF_SEL_RESERVED_145 = 0x00000091, -CB_PERF_SEL_RESERVED_146 = 0x00000092, -CB_PERF_SEL_RESERVED_147 = 0x00000093, -CB_PERF_SEL_RESERVED_148 = 0x00000094, -CB_PERF_SEL_RESERVED_149 = 0x00000095, -CB_PERF_SEL_DCC_CACHE_PERF_HIT = 0x00000096, -CB_PERF_SEL_DCC_CACHE_TAG_MISS = 0x00000097, -CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 0x00000098, -CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 0x00000099, -CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000009a, -CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000009b, -CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000009c, -CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 0x0000009d, -CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 0x0000009e, -CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 0x0000009f, -CB_PERF_SEL_DCC_CACHE_STALL = 0x000000a0, -CB_PERF_SEL_DCC_CACHE_FLUSH = 0x000000a1, -CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 0x000000a2, -CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000a3, -CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 0x000000a4, -CB_PERF_SEL_RESERVED_165 = 0x000000a5, -CB_PERF_SEL_RESERVED_166 = 0x000000a6, -CB_PERF_SEL_RESERVED_167 = 0x000000a7, -CB_PERF_SEL_RESERVED_168 = 0x000000a8, -CB_PERF_SEL_RESERVED_169 = 0x000000a9, -CB_PERF_SEL_RESERVED_170 = 0x000000aa, -CB_PERF_SEL_RESERVED_171 = 0x000000ab, -CB_PERF_SEL_RESERVED_172 = 0x000000ac, -CB_PERF_SEL_RESERVED_173 = 0x000000ad, -CB_PERF_SEL_RESERVED_174 = 0x000000ae, -CB_PERF_SEL_RESERVED_175 = 0x000000af, -CB_PERF_SEL_RESERVED_176 = 0x000000b0, -CB_PERF_SEL_RESERVED_177 = 0x000000b1, -CB_PERF_SEL_RESERVED_178 = 0x000000b2, -CB_PERF_SEL_RESERVED_179 = 0x000000b3, -CB_PERF_SEL_RESERVED_180 = 0x000000b4, -CB_PERF_SEL_RESERVED_181 = 0x000000b5, -CB_PERF_SEL_RESERVED_182 = 0x000000b6, -CB_PERF_SEL_RESERVED_183 = 0x000000b7, -CB_PERF_SEL_RESERVED_184 = 0x000000b8, -CB_PERF_SEL_RESERVED_185 = 0x000000b9, -CB_PERF_SEL_RESERVED_186 = 0x000000ba, -CB_PERF_SEL_RESERVED_187 = 0x000000bb, -CB_PERF_SEL_RESERVED_188 = 0x000000bc, -CB_PERF_SEL_RESERVED_189 = 0x000000bd, -CB_PERF_SEL_RESERVED_190 = 0x000000be, -CB_PERF_SEL_RESERVED_191 = 0x000000bf, -CB_PERF_SEL_RESERVED_192 = 0x000000c0, -CB_PERF_SEL_RESERVED_193 = 0x000000c1, -CB_PERF_SEL_RESERVED_194 = 0x000000c2, -CB_PERF_SEL_RESERVED_195 = 0x000000c3, -CB_PERF_SEL_RESERVED_196 = 0x000000c4, -CB_PERF_SEL_RESERVED_197 = 0x000000c5, -CB_PERF_SEL_RESERVED_198 = 0x000000c6, -CB_PERF_SEL_RESERVED_199 = 0x000000c7, -CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000c8, -CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000c9, -CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000ca, -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000cb, -CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 0x000000cc, -CB_PERF_SEL_RESERVED_205 = 0x000000cd, -CB_PERF_SEL_RESERVED_206 = 0x000000ce, -CB_PERF_SEL_RESERVED_207 = 0x000000cf, -CB_PERF_SEL_RESERVED_208 = 0x000000d0, -CB_PERF_SEL_RESERVED_209 = 0x000000d1, -CB_PERF_SEL_RESERVED_210 = 0x000000d2, -CB_PERF_SEL_RESERVED_211 = 0x000000d3, -CB_PERF_SEL_RESERVED_212 = 0x000000d4, -CB_PERF_SEL_RESERVED_213 = 0x000000d5, -CB_PERF_SEL_RESERVED_214 = 0x000000d6, -CB_PERF_SEL_RESERVED_215 = 0x000000d7, -CB_PERF_SEL_RESERVED_216 = 0x000000d8, -CB_PERF_SEL_RESERVED_217 = 0x000000d9, -CB_PERF_SEL_RESERVED_218 = 0x000000da, -CB_PERF_SEL_RESERVED_219 = 0x000000db, -CB_PERF_SEL_RESERVED_220 = 0x000000dc, -CB_PERF_SEL_RESERVED_221 = 0x000000dd, -CB_PERF_SEL_RESERVED_222 = 0x000000de, -CB_PERF_SEL_RESERVED_223 = 0x000000df, -CB_PERF_SEL_RESERVED_224 = 0x000000e0, -CB_PERF_SEL_RESERVED_225 = 0x000000e1, -CB_PERF_SEL_RESERVED_226 = 0x000000e2, -CB_PERF_SEL_RESERVED_227 = 0x000000e3, -CB_PERF_SEL_RESERVED_228 = 0x000000e4, -CB_PERF_SEL_RESERVED_229 = 0x000000e5, -CB_PERF_SEL_RESERVED_230 = 0x000000e6, -CB_PERF_SEL_RESERVED_231 = 0x000000e7, -CB_PERF_SEL_RESERVED_232 = 0x000000e8, -CB_PERF_SEL_RESERVED_233 = 0x000000e9, -CB_PERF_SEL_RESERVED_234 = 0x000000ea, -CB_PERF_SEL_RESERVED_235 = 0x000000eb, -CB_PERF_SEL_RESERVED_236 = 0x000000ec, -CB_PERF_SEL_RESERVED_237 = 0x000000ed, -CB_PERF_SEL_RESERVED_238 = 0x000000ee, -CB_PERF_SEL_RESERVED_239 = 0x000000ef, -CB_PERF_SEL_RESERVED_240 = 0x000000f0, -CB_PERF_SEL_RESERVED_241 = 0x000000f1, -CB_PERF_SEL_RESERVED_242 = 0x000000f2, -CB_PERF_SEL_RESERVED_243 = 0x000000f3, -CB_PERF_SEL_RESERVED_244 = 0x000000f4, -CB_PERF_SEL_RESERVED_245 = 0x000000f5, -CB_PERF_SEL_RESERVED_246 = 0x000000f6, -CB_PERF_SEL_RESERVED_247 = 0x000000f7, -CB_PERF_SEL_RESERVED_248 = 0x000000f8, -CB_PERF_SEL_RESERVED_249 = 0x000000f9, -CB_PERF_SEL_EVENT = 0x000000fa, -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x000000fb, -CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x000000fc, -CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x000000fd, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x000000fe, -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x000000ff, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000100, -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000101, -CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000102, -CB_PERF_SEL_RESERVED_259 = 0x00000103, -CB_PERF_SEL_RESERVED_260 = 0x00000104, -CB_PERF_SEL_RESERVED_261 = 0x00000105, -CB_PERF_SEL_RESERVED_262 = 0x00000106, -CB_PERF_SEL_RESERVED_263 = 0x00000107, -CB_PERF_SEL_RESERVED_264 = 0x00000108, -CB_PERF_SEL_RESERVED_265 = 0x00000109, -CB_PERF_SEL_RESERVED_266 = 0x0000010a, -CB_PERF_SEL_RESERVED_267 = 0x0000010b, -CB_PERF_SEL_RESERVED_268 = 0x0000010c, -CB_PERF_SEL_RESERVED_269 = 0x0000010d, -CB_PERF_SEL_RESERVED_270 = 0x0000010e, -CB_PERF_SEL_RESERVED_271 = 0x0000010f, -CB_PERF_SEL_RESERVED_272 = 0x00000110, -CB_PERF_SEL_RESERVED_273 = 0x00000111, -CB_PERF_SEL_RESERVED_274 = 0x00000112, -CB_PERF_SEL_RESERVED_275 = 0x00000113, -CB_PERF_SEL_RESERVED_276 = 0x00000114, -CB_PERF_SEL_RESERVED_277 = 0x00000115, -CB_PERF_SEL_RESERVED_278 = 0x00000116, -CB_PERF_SEL_RESERVED_279 = 0x00000117, -CB_PERF_SEL_RESERVED_280 = 0x00000118, -CB_PERF_SEL_RESERVED_281 = 0x00000119, -CB_PERF_SEL_RESERVED_282 = 0x0000011a, -CB_PERF_SEL_RESERVED_283 = 0x0000011b, -CB_PERF_SEL_RESERVED_284 = 0x0000011c, -CB_PERF_SEL_RESERVED_285 = 0x0000011d, -CB_PERF_SEL_RESERVED_286 = 0x0000011e, -CB_PERF_SEL_RESERVED_287 = 0x0000011f, -CB_PERF_SEL_RESERVED_288 = 0x00000120, -CB_PERF_SEL_RESERVED_289 = 0x00000121, -CB_PERF_SEL_RESERVED_290 = 0x00000122, -CB_PERF_SEL_RESERVED_291 = 0x00000123, -CB_PERF_SEL_RESERVED_292 = 0x00000124, -CB_PERF_SEL_RESERVED_293 = 0x00000125, -CB_PERF_SEL_RESERVED_294 = 0x00000126, -CB_PERF_SEL_RESERVED_295 = 0x00000127, -CB_PERF_SEL_RESERVED_296 = 0x00000128, -CB_PERF_SEL_RESERVED_297 = 0x00000129, -CB_PERF_SEL_RESERVED_298 = 0x0000012a, -CB_PERF_SEL_RESERVED_299 = 0x0000012b, -CB_PERF_SEL_NACK_CC_READ = 0x0000012c, -CB_PERF_SEL_NACK_CC_WRITE = 0x0000012d, -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x0000012e, -CB_PERF_SEL_RESERVED_303 = 0x0000012f, -CB_PERF_SEL_RESERVED_304 = 0x00000130, -CB_PERF_SEL_RESERVED_305 = 0x00000131, -CB_PERF_SEL_RESERVED_306 = 0x00000132, -CB_PERF_SEL_RESERVED_307 = 0x00000133, -CB_PERF_SEL_RESERVED_308 = 0x00000134, -CB_PERF_SEL_RESERVED_309 = 0x00000135, -CB_PERF_SEL_RESERVED_310 = 0x00000136, -CB_PERF_SEL_RESERVED_311 = 0x00000137, -CB_PERF_SEL_RESERVED_312 = 0x00000138, -CB_PERF_SEL_RESERVED_313 = 0x00000139, -CB_PERF_SEL_RESERVED_314 = 0x0000013a, -CB_PERF_SEL_RESERVED_315 = 0x0000013b, -CB_PERF_SEL_RESERVED_316 = 0x0000013c, -CB_PERF_SEL_RESERVED_317 = 0x0000013d, -CB_PERF_SEL_RESERVED_318 = 0x0000013e, -CB_PERF_SEL_RESERVED_319 = 0x0000013f, -CB_PERF_SEL_RESERVED_320 = 0x00000140, -CB_PERF_SEL_RESERVED_321 = 0x00000141, -CB_PERF_SEL_RESERVED_322 = 0x00000142, -CB_PERF_SEL_RESERVED_323 = 0x00000143, -CB_PERF_SEL_RESERVED_324 = 0x00000144, -CB_PERF_SEL_RESERVED_325 = 0x00000145, -CB_PERF_SEL_RESERVED_326 = 0x00000146, -CB_PERF_SEL_RESERVED_327 = 0x00000147, -CB_PERF_SEL_RESERVED_328 = 0x00000148, -CB_PERF_SEL_RESERVED_329 = 0x00000149, -CB_PERF_SEL_RESERVED_330 = 0x0000014a, -CB_PERF_SEL_RESERVED_331 = 0x0000014b, -CB_PERF_SEL_RESERVED_332 = 0x0000014c, -CB_PERF_SEL_RESERVED_333 = 0x0000014d, -CB_PERF_SEL_RESERVED_334 = 0x0000014e, -CB_PERF_SEL_RESERVED_335 = 0x0000014f, -CB_PERF_SEL_RESERVED_336 = 0x00000150, -CB_PERF_SEL_RESERVED_337 = 0x00000151, -CB_PERF_SEL_RESERVED_338 = 0x00000152, -CB_PERF_SEL_RESERVED_339 = 0x00000153, -CB_PERF_SEL_RESERVED_340 = 0x00000154, -CB_PERF_SEL_RESERVED_341 = 0x00000155, -CB_PERF_SEL_RESERVED_342 = 0x00000156, -CB_PERF_SEL_RESERVED_343 = 0x00000157, -CB_PERF_SEL_RESERVED_344 = 0x00000158, -CB_PERF_SEL_RESERVED_345 = 0x00000159, -CB_PERF_SEL_RESERVED_346 = 0x0000015a, -CB_PERF_SEL_RESERVED_347 = 0x0000015b, -CB_PERF_SEL_RESERVED_348 = 0x0000015c, -CB_PERF_SEL_RESERVED_349 = 0x0000015d, -CB_PERF_SEL_RESERVED_350 = 0x0000015e, -CB_PERF_SEL_RESERVED_351 = 0x0000015f, -CB_PERF_SEL_RESERVED_352 = 0x00000160, -CB_PERF_SEL_RESERVED_353 = 0x00000161, -CB_PERF_SEL_RESERVED_354 = 0x00000162, -CB_PERF_SEL_RESERVED_355 = 0x00000163, -CB_PERF_SEL_RESERVED_356 = 0x00000164, -CB_PERF_SEL_RESERVED_357 = 0x00000165, -CB_PERF_SEL_RESERVED_358 = 0x00000166, -CB_PERF_SEL_RESERVED_359 = 0x00000167, -CB_PERF_SEL_RESERVED_360 = 0x00000168, -CB_PERF_SEL_RESERVED_361 = 0x00000169, -CB_PERF_SEL_RESERVED_362 = 0x0000016a, -CB_PERF_SEL_RESERVED_363 = 0x0000016b, -CB_PERF_SEL_RESERVED_364 = 0x0000016c, -CB_PERF_SEL_RESERVED_365 = 0x0000016d, -CB_PERF_SEL_RESERVED_366 = 0x0000016e, -CB_PERF_SEL_RESERVED_367 = 0x0000016f, -CB_PERF_SEL_RESERVED_368 = 0x00000170, -CB_PERF_SEL_RESERVED_369 = 0x00000171, -CB_PERF_SEL_RESERVED_370 = 0x00000172, -CB_PERF_SEL_RESERVED_371 = 0x00000173, -CB_PERF_SEL_RESERVED_372 = 0x00000174, -CB_PERF_SEL_RESERVED_373 = 0x00000175, -CB_PERF_SEL_RESERVED_374 = 0x00000176, -CB_PERF_SEL_RESERVED_375 = 0x00000177, -CB_PERF_SEL_RESERVED_376 = 0x00000178, -CB_PERF_SEL_RESERVED_377 = 0x00000179, -CB_PERF_SEL_RESERVED_378 = 0x0000017a, -CB_PERF_SEL_RESERVED_379 = 0x0000017b, -CB_PERF_SEL_RESERVED_380 = 0x0000017c, -CB_PERF_SEL_RESERVED_381 = 0x0000017d, -CB_PERF_SEL_RESERVED_382 = 0x0000017e, -CB_PERF_SEL_RESERVED_383 = 0x0000017f, -CB_PERF_SEL_RESERVED_384 = 0x00000180, -CB_PERF_SEL_RESERVED_385 = 0x00000181, -CB_PERF_SEL_RESERVED_386 = 0x00000182, -CB_PERF_SEL_RESERVED_387 = 0x00000183, -CB_PERF_SEL_RESERVED_388 = 0x00000184, -CB_PERF_SEL_RESERVED_389 = 0x00000185, -CB_PERF_SEL_RESERVED_390 = 0x00000186, -CB_PERF_SEL_RESERVED_391 = 0x00000187, -CB_PERF_SEL_RESERVED_392 = 0x00000188, -CB_PERF_SEL_RESERVED_393 = 0x00000189, -CB_PERF_SEL_RESERVED_394 = 0x0000018a, -CB_PERF_SEL_RESERVED_395 = 0x0000018b, -CB_PERF_SEL_RESERVED_396 = 0x0000018c, -CB_PERF_SEL_RESERVED_397 = 0x0000018d, -CB_PERF_SEL_RESERVED_398 = 0x0000018e, -CB_PERF_SEL_RESERVED_399 = 0x0000018f, -CB_PERF_SEL_RESERVED_400 = 0x00000190, -CB_PERF_SEL_RESERVED_401 = 0x00000191, -CB_PERF_SEL_RESERVED_402 = 0x00000192, -CB_PERF_SEL_RESERVED_403 = 0x00000193, -CB_PERF_SEL_RESERVED_404 = 0x00000194, -CB_PERF_SEL_RESERVED_405 = 0x00000195, -CB_PERF_SEL_RESERVED_406 = 0x00000196, -CB_PERF_SEL_RESERVED_407 = 0x00000197, -CB_PERF_SEL_RESERVED_408 = 0x00000198, -CB_PERF_SEL_RESERVED_409 = 0x00000199, -CB_PERF_SEL_RESERVED_410 = 0x0000019a, -CB_PERF_SEL_RESERVED_411 = 0x0000019b, -CB_PERF_SEL_RESERVED_412 = 0x0000019c, -CB_PERF_SEL_RESERVED_413 = 0x0000019d, -CB_PERF_SEL_RESERVED_414 = 0x0000019e, -CB_PERF_SEL_RESERVED_415 = 0x0000019f, -CB_PERF_SEL_RESERVED_416 = 0x000001a0, -CB_PERF_SEL_RESERVED_417 = 0x000001a1, -CB_PERF_SEL_RESERVED_418 = 0x000001a2, -CB_PERF_SEL_RESERVED_419 = 0x000001a3, -CB_PERF_SEL_RESERVED_420 = 0x000001a4, -CB_PERF_SEL_RESERVED_421 = 0x000001a5, -CB_PERF_SEL_RESERVED_422 = 0x000001a6, -CB_PERF_SEL_RESERVED_423 = 0x000001a7, -CB_PERF_SEL_RESERVED_424 = 0x000001a8, -CB_PERF_SEL_RESERVED_425 = 0x000001a9, -CB_PERF_SEL_RESERVED_426 = 0x000001aa, -CB_PERF_SEL_RESERVED_427 = 0x000001ab, -CB_PERF_SEL_RESERVED_428 = 0x000001ac, -CB_PERF_SEL_RESERVED_429 = 0x000001ad, -CB_PERF_SEL_RESERVED_430 = 0x000001ae, -CB_PERF_SEL_RESERVED_431 = 0x000001af, -CB_PERF_SEL_RESERVED_432 = 0x000001b0, -CB_PERF_SEL_RESERVED_433 = 0x000001b1, -CB_PERF_SEL_RESERVED_434 = 0x000001b2, -CB_PERF_SEL_RESERVED_435 = 0x000001b3, -CB_PERF_SEL_RESERVED_436 = 0x000001b4, -CB_PERF_SEL_RESERVED_437 = 0x000001b5, -CB_PERF_SEL_RESERVED_438 = 0x000001b6, -CB_PERF_SEL_RESERVED_439 = 0x000001b7, -CB_PERF_SEL_RESERVED_440 = 0x000001b8, -CB_PERF_SEL_RESERVED_441 = 0x000001b9, -CB_PERF_SEL_RESERVED_442 = 0x000001ba, -CB_PERF_SEL_RESERVED_443 = 0x000001bb, -CB_PERF_SEL_RESERVED_444 = 0x000001bc, -CB_PERF_SEL_RESERVED_445 = 0x000001bd, -CB_PERF_SEL_RESERVED_446 = 0x000001be, -CB_PERF_SEL_RESERVED_447 = 0x000001bf, -CB_PERF_SEL_RESERVED_448 = 0x000001c0, -CB_PERF_SEL_RESERVED_449 = 0x000001c1, -CB_PERF_SEL_RESERVED_450 = 0x000001c2, -CB_PERF_SEL_RESERVED_451 = 0x000001c3, -CB_PERF_SEL_RESERVED_452 = 0x000001c4, -CB_PERF_SEL_RESERVED_453 = 0x000001c5, -CB_PERF_SEL_RESERVED_454 = 0x000001c6, -CB_PERF_SEL_RESERVED_455 = 0x000001c7, -CB_PERF_SEL_RESERVED_456 = 0x000001c8, -CB_PERF_SEL_RESERVED_457 = 0x000001c9, -CB_PERF_SEL_RESERVED_458 = 0x000001ca, -CB_PERF_SEL_RESERVED_459 = 0x000001cb, -CB_PERF_SEL_RESERVED_460 = 0x000001cc, -CB_PERF_SEL_RESERVED_461 = 0x000001cd, -CB_PERF_SEL_RESERVED_462 = 0x000001ce, -CB_PERF_SEL_RESERVED_463 = 0x000001cf, -CB_PERF_SEL_RESERVED_464 = 0x000001d0, -CB_PERF_SEL_RESERVED_465 = 0x000001d1, -} CBPerfSel; - -/* - * CBRamList enum - */ - -typedef enum CBRamList { -CB_DCG_CCC_CAS_TAG_ARRAY = 0x00000000, -CB_DCG_CCC_CAS_FRAG_PTR = 0x00000001, -CB_DCG_CCC_CAS_COLOR_PTR = 0x00000002, -CB_DCG_CCC_CAS_SURF_PARAM = 0x00000003, -CB_DCG_CCC_CAS_KEYID = 0x00000004, -CB_DCG_BACKEND_RDLAT_FIFO = 0x00000005, -CB_DCG_FRONTEND_RDLAT_FIFO = 0x00000006, -CB_DCG_SRC_FIFO = 0x00000007, -CB_DCG_COLOR_STORE = 0x00000008, -CB_DCG_COLOR_STORE_DIRTY_BYTE = 0x00000009, -CB_DCG_FMASK_CACHE_STORE = 0x0000000a, -CB_DCG_READ_SKID_FIFO = 0x0000000b, -CB_DCG_QUAD_PTR_FIFO = 0x0000000c, -CB_DCG_OUTPUT_FIFO = 0x0000000d, -CB_DCG_DCC_CACHE = 0x0000000e, -CB_DCG_DCC_DIRTY_BITS = 0x0000000f, -CB_DCG_QBLOCK_ALLOC = 0x00000010, -} CBRamList; - -/* - * CmaskCode enum - */ - -typedef enum CmaskCode { -CMASK_CLR00_F0 = 0x00000000, -CMASK_CLR00_F1 = 0x00000001, -CMASK_CLR00_F2 = 0x00000002, -CMASK_CLR00_FX = 0x00000003, -CMASK_CLR01_F0 = 0x00000004, -CMASK_CLR01_F1 = 0x00000005, -CMASK_CLR01_F2 = 0x00000006, -CMASK_CLR01_FX = 0x00000007, -CMASK_CLR10_F0 = 0x00000008, -CMASK_CLR10_F1 = 0x00000009, -CMASK_CLR10_F2 = 0x0000000a, -CMASK_CLR10_FX = 0x0000000b, -CMASK_CLR11_F0 = 0x0000000c, -CMASK_CLR11_F1 = 0x0000000d, -CMASK_CLR11_F2 = 0x0000000e, -CMASK_CLR11_FX = 0x0000000f, -} CmaskCode; - -/* - * CombFunc enum - */ - -typedef enum CombFunc { -COMB_DST_PLUS_SRC = 0x00000000, -COMB_SRC_MINUS_DST = 0x00000001, -COMB_MIN_DST_SRC = 0x00000002, -COMB_MAX_DST_SRC = 0x00000003, -COMB_DST_MINUS_SRC = 0x00000004, -} CombFunc; - -/* - * MemArbMode enum - */ - -typedef enum MemArbMode { -MEM_ARB_MODE_FIXED = 0x00000000, -MEM_ARB_MODE_AGE = 0x00000001, -MEM_ARB_MODE_WEIGHT = 0x00000002, -MEM_ARB_MODE_BOTH = 0x00000003, -} MemArbMode; - -/* - * SourceFormat enum - */ - -typedef enum SourceFormat { -EXPORT_4C_32BPC = 0x00000000, -EXPORT_4C_16BPC = 0x00000001, -EXPORT_2C_32BPC_GR = 0x00000002, -EXPORT_2C_32BPC_AR = 0x00000003, -} SourceFormat; - -/******************************************************* - * SC Enums - *******************************************************/ - -/* - * BinEventCntl enum - */ - -typedef enum BinEventCntl { -BINNER_BREAK_BATCH = 0x00000000, -BINNER_PIPELINE = 0x00000001, -BINNER_DROP = 0x00000002, -BINNER_PIPELINE_BREAK = 0x00000003, -} BinEventCntl; - -/* - * BinMapMode enum - */ - -typedef enum BinMapMode { -BIN_MAP_MODE_NONE = 0x00000000, -BIN_MAP_MODE_RTA_INDEX = 0x00000001, -BIN_MAP_MODE_POPS = 0x00000002, -} BinMapMode; - -/* - * BinSizeExtend enum - */ - -typedef enum BinSizeExtend { -BIN_SIZE_32_PIXELS = 0x00000000, -BIN_SIZE_64_PIXELS = 0x00000001, -BIN_SIZE_128_PIXELS = 0x00000002, -BIN_SIZE_256_PIXELS = 0x00000003, -BIN_SIZE_512_PIXELS = 0x00000004, -} BinSizeExtend; - -/* - * BinningMode enum - */ - -typedef enum BinningMode { -BINNING_ALLOWED = 0x00000000, -FORCE_BINNING_ON = 0x00000001, -DISABLE_BINNING_USE_NEW_SC = 0x00000002, -DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, -} BinningMode; - -/* - * CovToShaderSel enum - */ - -typedef enum CovToShaderSel { -INPUT_COVERAGE = 0x00000000, -INPUT_INNER_COVERAGE = 0x00000001, -INPUT_DEPTH_COVERAGE = 0x00000002, -RAW = 0x00000003, -} CovToShaderSel; - -/* - * PkrMap enum - */ - -typedef enum PkrMap { -RASTER_CONFIG_PKR_MAP_0 = 0x00000000, -RASTER_CONFIG_PKR_MAP_1 = 0x00000001, -RASTER_CONFIG_PKR_MAP_2 = 0x00000002, -RASTER_CONFIG_PKR_MAP_3 = 0x00000003, -} PkrMap; - -/* - * PkrXsel enum - */ - -typedef enum PkrXsel { -RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, -RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, -RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, -RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, -} PkrXsel; - -/* - * PkrXsel2 enum - */ - -typedef enum PkrXsel2 { -RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, -RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, -RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, -RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, -} PkrXsel2; - -/* - * PkrYsel enum - */ - -typedef enum PkrYsel { -RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, -RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, -RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, -RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, -} PkrYsel; - -/* - * RbMap enum - */ - -typedef enum RbMap { -RASTER_CONFIG_RB_MAP_0 = 0x00000000, -RASTER_CONFIG_RB_MAP_1 = 0x00000001, -RASTER_CONFIG_RB_MAP_2 = 0x00000002, -RASTER_CONFIG_RB_MAP_3 = 0x00000003, -} RbMap; - -/* - * RbXsel enum - */ - -typedef enum RbXsel { -RASTER_CONFIG_RB_XSEL_0 = 0x00000000, -RASTER_CONFIG_RB_XSEL_1 = 0x00000001, -} RbXsel; - -/* - * RbXsel2 enum - */ - -typedef enum RbXsel2 { -RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, -RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, -RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, -RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, -} RbXsel2; - -/* - * RbYsel enum - */ - -typedef enum RbYsel { -RASTER_CONFIG_RB_YSEL_0 = 0x00000000, -RASTER_CONFIG_RB_YSEL_1 = 0x00000001, -} RbYsel; - -/* - * SC_PERFCNT_SEL enum - */ - -typedef enum SC_PERFCNT_SEL { -SC_SRPS_WINDOW_VALID = 0x00000000, -SC_PSSW_WINDOW_VALID = 0x00000001, -SC_TPQZ_WINDOW_VALID = 0x00000002, -SC_QZQP_WINDOW_VALID = 0x00000003, -SC_TRPK_WINDOW_VALID = 0x00000004, -SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, -SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, -SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, -SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, -SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, -SC_STARVED_BY_PA = 0x0000000a, -SC_STALLED_BY_PRIMFIFO = 0x0000000b, -SC_STALLED_BY_DB_TILE = 0x0000000c, -SC_STARVED_BY_DB_TILE = 0x0000000d, -SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, -SC_STALLED_BY_TILEFIFO = 0x0000000f, -SC_STALLED_BY_DB_QUAD = 0x00000010, -SC_STARVED_BY_DB_QUAD = 0x00000011, -SC_STALLED_BY_QUADFIFO = 0x00000012, -SC_STALLED_BY_BCI = 0x00000013, -SC_STALLED_BY_SPI = 0x00000014, -SC_SCISSOR_DISCARD = 0x00000015, -SC_BB_DISCARD = 0x00000016, -SC_SUPERTILE_COUNT = 0x00000017, -SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, -SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, -SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, -SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, -SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, -SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, -SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, -SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, -SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, -SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, -SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, -SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, -SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, -SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, -SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, -SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, -SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, -SC_TILE_PER_PRIM_H0 = 0x00000029, -SC_TILE_PER_PRIM_H1 = 0x0000002a, -SC_TILE_PER_PRIM_H2 = 0x0000002b, -SC_TILE_PER_PRIM_H3 = 0x0000002c, -SC_TILE_PER_PRIM_H4 = 0x0000002d, -SC_TILE_PER_PRIM_H5 = 0x0000002e, -SC_TILE_PER_PRIM_H6 = 0x0000002f, -SC_TILE_PER_PRIM_H7 = 0x00000030, -SC_TILE_PER_PRIM_H8 = 0x00000031, -SC_TILE_PER_PRIM_H9 = 0x00000032, -SC_TILE_PER_PRIM_H10 = 0x00000033, -SC_TILE_PER_PRIM_H11 = 0x00000034, -SC_TILE_PER_PRIM_H12 = 0x00000035, -SC_TILE_PER_PRIM_H13 = 0x00000036, -SC_TILE_PER_PRIM_H14 = 0x00000037, -SC_TILE_PER_PRIM_H15 = 0x00000038, -SC_TILE_PER_PRIM_H16 = 0x00000039, -SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, -SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, -SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, -SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, -SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, -SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, -SC_TILE_PER_SUPERTILE_H6 = 0x00000040, -SC_TILE_PER_SUPERTILE_H7 = 0x00000041, -SC_TILE_PER_SUPERTILE_H8 = 0x00000042, -SC_TILE_PER_SUPERTILE_H9 = 0x00000043, -SC_TILE_PER_SUPERTILE_H10 = 0x00000044, -SC_TILE_PER_SUPERTILE_H11 = 0x00000045, -SC_TILE_PER_SUPERTILE_H12 = 0x00000046, -SC_TILE_PER_SUPERTILE_H13 = 0x00000047, -SC_TILE_PER_SUPERTILE_H14 = 0x00000048, -SC_TILE_PER_SUPERTILE_H15 = 0x00000049, -SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, -SC_TILE_PICKED_H1 = 0x0000004b, -SC_TILE_PICKED_H2 = 0x0000004c, -SC_TILE_PICKED_H3 = 0x0000004d, -SC_TILE_PICKED_H4 = 0x0000004e, -SC_QZ0_TILE_COUNT = 0x0000004f, -SC_QZ1_TILE_COUNT = 0x00000050, -SC_QZ2_TILE_COUNT = 0x00000051, -SC_QZ3_TILE_COUNT = 0x00000052, -SC_QZ0_TILE_COVERED_COUNT = 0x00000053, -SC_QZ1_TILE_COVERED_COUNT = 0x00000054, -SC_QZ2_TILE_COVERED_COUNT = 0x00000055, -SC_QZ3_TILE_COVERED_COUNT = 0x00000056, -SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, -SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058, -SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059, -SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a, -SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, -SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, -SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, -SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, -SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, -SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, -SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, -SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, -SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, -SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, -SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, -SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, -SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, -SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, -SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, -SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, -SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, -SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c, -SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d, -SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e, -SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f, -SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070, -SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071, -SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072, -SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073, -SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074, -SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075, -SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076, -SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077, -SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078, -SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079, -SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a, -SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b, -SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c, -SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d, -SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e, -SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f, -SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080, -SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081, -SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082, -SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083, -SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084, -SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085, -SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086, -SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087, -SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088, -SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089, -SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a, -SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b, -SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c, -SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d, -SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e, -SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f, -SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090, -SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091, -SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092, -SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093, -SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094, -SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095, -SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096, -SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097, -SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098, -SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099, -SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a, -SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b, -SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c, -SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d, -SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e, -SC_QZ0_QUAD_COUNT = 0x0000009f, -SC_QZ1_QUAD_COUNT = 0x000000a0, -SC_QZ2_QUAD_COUNT = 0x000000a1, -SC_QZ3_QUAD_COUNT = 0x000000a2, -SC_P0_HIZ_TILE_COUNT = 0x000000a3, -SC_P1_HIZ_TILE_COUNT = 0x000000a4, -SC_P2_HIZ_TILE_COUNT = 0x000000a5, -SC_P3_HIZ_TILE_COUNT = 0x000000a6, -SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, -SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, -SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, -SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, -SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, -SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, -SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, -SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, -SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, -SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, -SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, -SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, -SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, -SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, -SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, -SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, -SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, -SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8, -SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9, -SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba, -SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb, -SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc, -SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd, -SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be, -SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf, -SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0, -SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1, -SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2, -SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3, -SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4, -SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5, -SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6, -SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7, -SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8, -SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9, -SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca, -SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb, -SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc, -SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd, -SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce, -SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf, -SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0, -SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1, -SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2, -SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3, -SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4, -SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5, -SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6, -SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7, -SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8, -SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9, -SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da, -SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db, -SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc, -SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd, -SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de, -SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df, -SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0, -SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1, -SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2, -SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3, -SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4, -SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5, -SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6, -SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7, -SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8, -SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9, -SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea, -SC_P0_HIZ_QUAD_COUNT = 0x000000eb, -SC_P1_HIZ_QUAD_COUNT = 0x000000ec, -SC_P2_HIZ_QUAD_COUNT = 0x000000ed, -SC_P3_HIZ_QUAD_COUNT = 0x000000ee, -SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, -SC_P1_DETAIL_QUAD_COUNT = 0x000000f0, -SC_P2_DETAIL_QUAD_COUNT = 0x000000f1, -SC_P3_DETAIL_QUAD_COUNT = 0x000000f2, -SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, -SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, -SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, -SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, -SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, -SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, -SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, -SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, -SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, -SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, -SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, -SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, -SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, -SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100, -SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101, -SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102, -SC_EARLYZ_QUAD_COUNT = 0x00000103, -SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, -SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, -SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, -SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, -SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, -SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, -SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, -SC_PKR_4X2_FILL_QUAD = 0x0000010b, -SC_PKR_END_OF_VECTOR = 0x0000010c, -SC_PKR_CONTROL_XFER = 0x0000010d, -SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, -SC_REG_SCLK_BUSY = 0x0000010f, -SC_GRP0_DYN_SCLK_BUSY = 0x00000110, -SC_GRP1_DYN_SCLK_BUSY = 0x00000111, -SC_GRP2_DYN_SCLK_BUSY = 0x00000112, -SC_GRP3_DYN_SCLK_BUSY = 0x00000113, -SC_GRP4_DYN_SCLK_BUSY = 0x00000114, -SC_PA0_SC_DATA_FIFO_RD = 0x00000115, -SC_PA0_SC_DATA_FIFO_WE = 0x00000116, -SC_PA1_SC_DATA_FIFO_RD = 0x00000117, -SC_PA1_SC_DATA_FIFO_WE = 0x00000118, -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, -SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, -SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, -SC_PS_ARB_SC_BUSY = 0x0000011e, -SC_PS_ARB_PA_SC_BUSY = 0x0000011f, -SC_PA2_SC_DATA_FIFO_RD = 0x00000120, -SC_PA2_SC_DATA_FIFO_WE = 0x00000121, -SC_PA3_SC_DATA_FIFO_RD = 0x00000122, -SC_PA3_SC_DATA_FIFO_WE = 0x00000123, -SC_PA_SC_DEALLOC_0_0_WE = 0x00000124, -SC_PA_SC_DEALLOC_0_1_WE = 0x00000125, -SC_PA_SC_DEALLOC_1_0_WE = 0x00000126, -SC_PA_SC_DEALLOC_1_1_WE = 0x00000127, -SC_PA_SC_DEALLOC_2_0_WE = 0x00000128, -SC_PA_SC_DEALLOC_2_1_WE = 0x00000129, -SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a, -SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b, -SC_PA0_SC_EOP_WE = 0x0000012c, -SC_PA0_SC_EOPG_WE = 0x0000012d, -SC_PA0_SC_EVENT_WE = 0x0000012e, -SC_PA1_SC_EOP_WE = 0x0000012f, -SC_PA1_SC_EOPG_WE = 0x00000130, -SC_PA1_SC_EVENT_WE = 0x00000131, -SC_PA2_SC_EOP_WE = 0x00000132, -SC_PA2_SC_EOPG_WE = 0x00000133, -SC_PA2_SC_EVENT_WE = 0x00000134, -SC_PA3_SC_EOP_WE = 0x00000135, -SC_PA3_SC_EOPG_WE = 0x00000136, -SC_PA3_SC_EVENT_WE = 0x00000137, -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138, -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139, -SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a, -SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b, -SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c, -SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d, -SC_PA0_SC_FPOV_WE = 0x0000013e, -SC_PA1_SC_FPOV_WE = 0x0000013f, -SC_PA2_SC_FPOV_WE = 0x00000140, -SC_PA3_SC_FPOV_WE = 0x00000141, -SC_PA0_SC_LPOV_WE = 0x00000142, -SC_PA1_SC_LPOV_WE = 0x00000143, -SC_PA2_SC_LPOV_WE = 0x00000144, -SC_PA3_SC_LPOV_WE = 0x00000145, -SC_SPI_DEALLOC_0_0 = 0x00000146, -SC_SPI_DEALLOC_0_1 = 0x00000147, -SC_SPI_DEALLOC_0_2 = 0x00000148, -SC_SPI_DEALLOC_1_0 = 0x00000149, -SC_SPI_DEALLOC_1_1 = 0x0000014a, -SC_SPI_DEALLOC_1_2 = 0x0000014b, -SC_SPI_DEALLOC_2_0 = 0x0000014c, -SC_SPI_DEALLOC_2_1 = 0x0000014d, -SC_SPI_DEALLOC_2_2 = 0x0000014e, -SC_SPI_DEALLOC_3_0 = 0x0000014f, -SC_SPI_DEALLOC_3_1 = 0x00000150, -SC_SPI_DEALLOC_3_2 = 0x00000151, -SC_SPI_FPOV_0 = 0x00000152, -SC_SPI_FPOV_1 = 0x00000153, -SC_SPI_FPOV_2 = 0x00000154, -SC_SPI_FPOV_3 = 0x00000155, -SC_SPI_EVENT = 0x00000156, -SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, -SC_PS_TS_EVENT_FIFO_POP = 0x00000158, -SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, -SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, -SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b, -SC_EOP_SYNC_WINDOW = 0x0000015c, -SC_PA0_SC_NULL_WE = 0x0000015d, -SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, -SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f, -SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, -SC_PA0_SC_DEALLOC_0_RD = 0x00000161, -SC_PA0_SC_DEALLOC_1_RD = 0x00000162, -SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163, -SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164, -SC_PA1_SC_DEALLOC_0_RD = 0x00000165, -SC_PA1_SC_DEALLOC_1_RD = 0x00000166, -SC_PA1_SC_NULL_WE = 0x00000167, -SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168, -SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169, -SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a, -SC_PA2_SC_DEALLOC_0_RD = 0x0000016b, -SC_PA2_SC_DEALLOC_1_RD = 0x0000016c, -SC_PA2_SC_NULL_WE = 0x0000016d, -SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e, -SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f, -SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170, -SC_PA3_SC_DEALLOC_0_RD = 0x00000171, -SC_PA3_SC_DEALLOC_1_RD = 0x00000172, -SC_PA3_SC_NULL_WE = 0x00000173, -SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174, -SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, -SC_PS_PA0_SC_FIFO_FULL = 0x00000176, -SC_RESERVED_0 = 0x00000177, -SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178, -SC_PS_PA1_SC_FIFO_FULL = 0x00000179, -SC_RESERVED_1 = 0x0000017a, -SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b, -SC_PS_PA2_SC_FIFO_FULL = 0x0000017c, -SC_RESERVED_2 = 0x0000017d, -SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e, -SC_PS_PA3_SC_FIFO_FULL = 0x0000017f, -SC_RESERVED_3 = 0x00000180, -SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181, -SC_BUSY_CNT_NOT_ZERO = 0x00000182, -SC_BM_BUSY = 0x00000183, -SC_BACKEND_BUSY = 0x00000184, -SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, -SC_SCB_BUSY = 0x00000186, -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, -SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, -SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, -SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, -SC_PBB_BUSY = 0x00000193, -SC_PBB_BUSY_AND_NO_SENDS = 0x00000194, -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, -SC_PBB_NUM_BINS = 0x00000196, -SC_PBB_END_OF_BIN = 0x00000197, -SC_PBB_END_OF_BATCH = 0x00000198, -SC_PBB_PRIMBIN_PROCESSED = 0x00000199, -SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, -SC_PBB_NONBINNED_PRIM = 0x0000019b, -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, -SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7, -SC_POPS_FORCE_EOV = 0x000001a8, -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9, -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa, -SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab, -SC_FULL_FULL_QUAD = 0x000001ac, -SC_FULL_HALF_QUAD = 0x000001ad, -SC_FULL_QTR_QUAD = 0x000001ae, -SC_HALF_FULL_QUAD = 0x000001af, -SC_HALF_HALF_QUAD = 0x000001b0, -SC_HALF_QTR_QUAD = 0x000001b1, -SC_QTR_FULL_QUAD = 0x000001b2, -SC_QTR_HALF_QUAD = 0x000001b3, -SC_QTR_QTR_QUAD = 0x000001b4, -SC_GRP5_DYN_SCLK_BUSY = 0x000001b5, -SC_GRP6_DYN_SCLK_BUSY = 0x000001b6, -SC_GRP7_DYN_SCLK_BUSY = 0x000001b7, -SC_GRP8_DYN_SCLK_BUSY = 0x000001b8, -SC_GRP9_DYN_SCLK_BUSY = 0x000001b9, -SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba, -SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb, -SC_PK_BUSY = 0x000001bc, -SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd, -SC_PK_DEALLOC_WAVE_BREAK = 0x000001be, -SC_SPI_SEND = 0x000001bf, -SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0, -SC_SPI_CREDIT_AT_MAX = 0x000001c1, -SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2, -SC_BCI_SEND = 0x000001c3, -SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4, -SC_BCI_CREDIT_AT_MAX = 0x000001c5, -SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6, -SC_SPIBC_FULL_FREEZE = 0x000001c7, -SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8, -SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9, -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da, -SC_DB0_TILE_INTERFACE_BUSY = 0x000001db, -SC_DB0_TILE_INTERFACE_SEND = 0x000001dc, -SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd, -SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de, -SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df, -SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0, -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1, -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2, -SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3, -SC_DB1_TILE_INTERFACE_SEND = 0x000001e4, -SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5, -SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6, -SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7, -SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8, -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9, -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea, -SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb, -SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec, -SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed, -SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee, -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef, -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0, -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1, -SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2, -SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3, -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4, -SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 0x000001f5, -SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6, -SC_STALLED_BY_DB0_TILEFIFO = 0x000001f7, -SC_DB0_QUAD_INTF_SEND = 0x000001f8, -SC_DB0_QUAD_INTF_BUSY = 0x000001f9, -SC_DB0_QUAD_INTF_STALLED_BY_DB = 0x000001fa, -SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 0x000001fb, -SC_DB0_QUAD_INTF_IDLE = 0x000001fc, -SC_DB1_QUAD_INTF_SEND = 0x000001fd, -SC_STALLED_BY_DB1_TILEFIFO = 0x000001fe, -SC_DB1_QUAD_INTF_BUSY = 0x000001ff, -SC_DB1_QUAD_INTF_STALLED_BY_DB = 0x00000200, -SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 0x00000201, -SC_DB1_QUAD_INTF_IDLE = 0x00000202, -SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 0x00000203, -SC_PKR_WAVE_BREAK_FULL_TILE = 0x00000204, -SC_FSR_WALKED = 0x00000205, -SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206, -SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207, -SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 0x00000208, -SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209, -SC_DB0_TILE_MASK_FIFO_FULL = 0x0000020a, -SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 0x0000020b, -SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x0000020c, -SC_DB1_TILE_MASK_FIFO_FULL = 0x0000020d, -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e, -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f, -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210, -SC_PS_PM_PFF_PW_FULL = 0x00000211, -SC_PS_PM_ZFF_PW_FULL = 0x00000212, -SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 0x00000213, -SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 0x00000214, -SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x00000215, -SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x00000216, -SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 0x00000217, -SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 0x00000218, -SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 0x00000219, -SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 0x0000021a, -SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 0x0000021b, -SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 0x0000021c, -SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x0000021d, -SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 0x0000021e, -SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f, -SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 0x00000220, -SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 0x00000221, -SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 0x00000222, -SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 0x00000223, -SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224, -SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225, -SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226, -SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227, -SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 0x00000228, -SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 0x00000229, -SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 0x0000022a, -SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 0x0000022b, -SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 0x0000022c, -SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 0x0000022d, -SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 0x0000022e, -SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 0x0000022f, -SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 0x00000230, -SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 0x00000231, -SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 0x00000232, -SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 0x00000233, -SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 0x00000234, -SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 0x00000235, -SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 0x00000236, -SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 0x00000237, -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 0x00000238, -SC_PBB_RESERVED = 0x00000239, -SC_BM_BE0_STALLED = 0x0000023a, -SC_BM_BE1_STALLED = 0x0000023b, -SC_BM_BE2_STALLED = 0x0000023c, -SC_BM_BE3_STALLED = 0x0000023d, -SC_BM_MULTI_ACCUM_1_BE_STALLED = 0x0000023e, -SC_BM_MULTI_ACCUM_2_BE_STALLED = 0x0000023f, -SC_BM_MULTI_ACCUM_3_BE_STALLED = 0x00000240, -SC_BM_MULTI_ACCUM_4_BE_STALLED = 0x00000241, -} SC_PERFCNT_SEL; - -/* - * ScMap enum - */ - -typedef enum ScMap { -RASTER_CONFIG_SC_MAP_0 = 0x00000000, -RASTER_CONFIG_SC_MAP_1 = 0x00000001, -RASTER_CONFIG_SC_MAP_2 = 0x00000002, -RASTER_CONFIG_SC_MAP_3 = 0x00000003, -} ScMap; - -/* - * ScUncertaintyRegionMode enum - */ - -typedef enum ScUncertaintyRegionMode { -SC_HALF_LSB = 0x00000000, -SC_LSB_ONE_SIDED = 0x00000001, -SC_LSB_TWO_SIDED = 0x00000002, -} ScUncertaintyRegionMode; - -/* - * ScUncertaintyRegionMult enum - */ - -typedef enum ScUncertaintyRegionMult { -SC_UR_1X = 0x00000000, -SC_UR_2X = 0x00000001, -SC_UR_4X = 0x00000002, -SC_UR_8X = 0x00000003, -} ScUncertaintyRegionMult; - -/* - * ScXsel enum - */ - -typedef enum ScXsel { -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, -} ScXsel; - -/* - * ScYsel enum - */ - -typedef enum ScYsel { -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, -} ScYsel; - -/* - * SeMap enum - */ - -typedef enum SeMap { -RASTER_CONFIG_SE_MAP_0 = 0x00000000, -RASTER_CONFIG_SE_MAP_1 = 0x00000001, -RASTER_CONFIG_SE_MAP_2 = 0x00000002, -RASTER_CONFIG_SE_MAP_3 = 0x00000003, -} SeMap; - -/* - * SePairMap enum - */ - -typedef enum SePairMap { -RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, -RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, -RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, -RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, -} SePairMap; - -/* - * SePairXsel enum - */ - -typedef enum SePairXsel { -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, -} SePairXsel; - -/* - * SePairYsel enum - */ - -typedef enum SePairYsel { -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, -} SePairYsel; - -/* - * SeXsel enum - */ - -typedef enum SeXsel { -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, -} SeXsel; - -/* - * SeYsel enum - */ - -typedef enum SeYsel { -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, -} SeYsel; - -/* - * VRSCombinerModeSC enum - */ - -typedef enum VRSCombinerModeSC { -SC_VRS_COMB_MODE_PASSTHRU = 0x00000000, -SC_VRS_COMB_MODE_OVERRIDE = 0x00000001, -SC_VRS_COMB_MODE_MIN = 0x00000002, -SC_VRS_COMB_MODE_MAX = 0x00000003, -SC_VRS_COMB_MODE_SATURATE = 0x00000004, -} VRSCombinerModeSC; - -/* - * VRSrate enum - */ - -typedef enum VRSrate { -VRS_SHADING_RATE_1X1 = 0x00000000, -VRS_SHADING_RATE_1X2 = 0x00000001, -VRS_SHADING_RATE_UNDEFINED0 = 0x00000002, -VRS_SHADING_RATE_UNDEFINED1 = 0x00000003, -VRS_SHADING_RATE_2X1 = 0x00000004, -VRS_SHADING_RATE_2X2 = 0x00000005, -VRS_SHADING_RATE_2X4 = 0x00000006, -VRS_SHADING_RATE_UNDEFINED2 = 0x00000007, -VRS_SHADING_RATE_UNDEFINED3 = 0x00000008, -VRS_SHADING_RATE_4X2 = 0x00000009, -VRS_SHADING_RATE_4X4 = 0x0000000a, -VRS_SHADING_RATE_UNDEFINED4 = 0x0000000b, -VRS_SHADING_RATE_16X_SSAA = 0x0000000c, -VRS_SHADING_RATE_8X_SSAA = 0x0000000d, -VRS_SHADING_RATE_4X_SSAA = 0x0000000e, -VRS_SHADING_RATE_2X_SSAA = 0x0000000f, -} VRSrate; - -/******************************************************* - * TC Enums - *******************************************************/ - -/* - * TC_EA_CID enum - */ - -typedef enum TC_EA_CID { -TC_EA_CID_RT = 0x00000000, -TC_EA_CID_FMASK = 0x00000001, -TC_EA_CID_DCC = 0x00000002, -TC_EA_CID_TCPMETA = 0x00000003, -TC_EA_CID_Z = 0x00000004, -TC_EA_CID_STENCIL = 0x00000005, -TC_EA_CID_HTILE = 0x00000006, -TC_EA_CID_MISC = 0x00000007, -TC_EA_CID_TCP = 0x00000008, -TC_EA_CID_SQC = 0x00000009, -TC_EA_CID_CPF = 0x0000000a, -TC_EA_CID_CPG = 0x0000000b, -TC_EA_CID_IA = 0x0000000c, -TC_EA_CID_WD = 0x0000000d, -TC_EA_CID_PA = 0x0000000e, -TC_EA_CID_UTCL2_TPI = 0x0000000f, -} TC_EA_CID; - -/* - * TC_NACKS enum - */ - -typedef enum TC_NACKS { -TC_NACK_NO_FAULT = 0x00000000, -TC_NACK_PAGE_FAULT = 0x00000001, -TC_NACK_PROTECTION_FAULT = 0x00000002, -TC_NACK_DATA_ERROR = 0x00000003, -} TC_NACKS; - -/* - * TC_OP enum - */ - -typedef enum TC_OP { -TC_OP_READ = 0x00000000, -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, -TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, -TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, -TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, -TC_OP_RESERVED_FADD_RTN_32 = 0x00000005, -TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, -TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, -TC_OP_PROBE_FILTER = 0x0000000c, -TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, -TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, -TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, -TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, -TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, -TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, -TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, -TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, -TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, -TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, -TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, -TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, -TC_OP_WBINVL1_VOL = 0x0000001a, -TC_OP_WBINVL1_SD = 0x0000001b, -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, -TC_OP_WRITE = 0x00000020, -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, -TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, -TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, -TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, -TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, -TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, -TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, -TC_OP_WBINVL2_SD = 0x0000002c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, -TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, -TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, -TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, -TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, -TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, -TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, -TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, -TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, -TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, -TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, -TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, -TC_OP_WBL2_NC = 0x0000003a, -TC_OP_WBL2_WC = 0x0000003b, -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, -TC_OP_WBINVL1 = 0x00000040, -TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, -TC_OP_ATOMIC_FMIN_32 = 0x00000042, -TC_OP_ATOMIC_FMAX_32 = 0x00000043, -TC_OP_RESERVED_FOP_32_0 = 0x00000044, -TC_OP_RESERVED_FADD_32 = 0x00000045, -TC_OP_RESERVED_FOP_32_2 = 0x00000046, -TC_OP_ATOMIC_SWAP_32 = 0x00000047, -TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, -TC_OP_INV_METADATA = 0x0000004c, -TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, -TC_OP_ATOMIC_ADD_32 = 0x0000004f, -TC_OP_ATOMIC_SUB_32 = 0x00000050, -TC_OP_ATOMIC_SMIN_32 = 0x00000051, -TC_OP_ATOMIC_UMIN_32 = 0x00000052, -TC_OP_ATOMIC_SMAX_32 = 0x00000053, -TC_OP_ATOMIC_UMAX_32 = 0x00000054, -TC_OP_ATOMIC_AND_32 = 0x00000055, -TC_OP_ATOMIC_OR_32 = 0x00000056, -TC_OP_ATOMIC_XOR_32 = 0x00000057, -TC_OP_ATOMIC_INC_32 = 0x00000058, -TC_OP_ATOMIC_DEC_32 = 0x00000059, -TC_OP_INVL2_NC = 0x0000005a, -TC_OP_NOP_RTN0 = 0x0000005b, -TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, -TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, -TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, -TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, -TC_OP_WBINVL2 = 0x00000060, -TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, -TC_OP_ATOMIC_FMIN_64 = 0x00000062, -TC_OP_ATOMIC_FMAX_64 = 0x00000063, -TC_OP_RESERVED_FOP_64_0 = 0x00000064, -TC_OP_RESERVED_FOP_64_1 = 0x00000065, -TC_OP_RESERVED_FOP_64_2 = 0x00000066, -TC_OP_ATOMIC_SWAP_64 = 0x00000067, -TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, -TC_OP_ATOMIC_ADD_64 = 0x0000006f, -TC_OP_ATOMIC_SUB_64 = 0x00000070, -TC_OP_ATOMIC_SMIN_64 = 0x00000071, -TC_OP_ATOMIC_UMIN_64 = 0x00000072, -TC_OP_ATOMIC_SMAX_64 = 0x00000073, -TC_OP_ATOMIC_UMAX_64 = 0x00000074, -TC_OP_ATOMIC_AND_64 = 0x00000075, -TC_OP_ATOMIC_OR_64 = 0x00000076, -TC_OP_ATOMIC_XOR_64 = 0x00000077, -TC_OP_ATOMIC_INC_64 = 0x00000078, -TC_OP_ATOMIC_DEC_64 = 0x00000079, -TC_OP_WBINVL2_NC = 0x0000007a, -TC_OP_NOP_ACK = 0x0000007b, -TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, -TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, -TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, -TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, -} TC_OP; - -/* - * TC_OP_MASKS enum - */ - -typedef enum TC_OP_MASKS { -TC_OP_MASK_FLUSH_DENROM = 0x00000008, -TC_OP_MASK_64 = 0x00000020, -TC_OP_MASK_NO_RTN = 0x00000040, -} TC_OP_MASKS; - -/******************************************************* - * GL2 Enums - *******************************************************/ - -/* - * GL2_EA_CID enum - */ - -typedef enum GL2_EA_CID { -GL2_EA_CID_CLIENT = 0x00000000, -GL2_EA_CID_SDMA = 0x00000001, -GL2_EA_CID_RLC = 0x00000002, -GL2_EA_CID_SQC = 0x00000003, -GL2_EA_CID_CP = 0x00000004, -GL2_EA_CID_CPDMA = 0x00000005, -GL2_EA_CID_UTCL2 = 0x00000006, -GL2_EA_CID_RT = 0x00000007, -GL2_EA_CID_FMASK = 0x00000008, -GL2_EA_CID_DCC = 0x00000009, -GL2_EA_CID_Z_STENCIL = 0x0000000a, -GL2_EA_CID_ZPCPSD = 0x0000000b, -GL2_EA_CID_HTILE = 0x0000000c, -GL2_EA_CID_MES = 0x0000000d, -GL2_EA_CID_TCPMETA = 0x0000000f, -} GL2_EA_CID; - -/* - * GL2_NACKS enum - */ - -typedef enum GL2_NACKS { -GL2_NACK_NO_FAULT = 0x00000000, -GL2_NACK_PAGE_FAULT = 0x00000001, -GL2_NACK_PROTECTION_FAULT = 0x00000002, -GL2_NACK_DATA_ERROR = 0x00000003, -} GL2_NACKS; - -/* - * GL2_OP enum - */ - -typedef enum GL2_OP { -GL2_OP_READ = 0x00000000, -GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, -GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, -GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, -GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, -GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, -GL2_OP_PROBE_FILTER = 0x0000000c, -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d, -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, -GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, -GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010, -GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, -GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, -GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, -GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, -GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015, -GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016, -GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017, -GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018, -GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019, -GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 0x0000001a, -GL2_OP_WRITE = 0x00000020, -GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, -GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, -GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, -GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, -GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, -GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, -GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030, -GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, -GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, -GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, -GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, -GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035, -GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036, -GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037, -GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038, -GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039, -GL2_OP_GL1_INV = 0x00000040, -GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, -GL2_OP_ATOMIC_FMIN_32 = 0x00000042, -GL2_OP_ATOMIC_FMAX_32 = 0x00000043, -GL2_OP_ATOMIC_SWAP_32 = 0x00000047, -GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048, -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, -GL2_OP_ATOMIC_UMIN_8 = 0x0000004c, -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d, -GL2_OP_ATOMIC_ADD_32 = 0x0000004f, -GL2_OP_ATOMIC_SUB_32 = 0x00000050, -GL2_OP_ATOMIC_SMIN_32 = 0x00000051, -GL2_OP_ATOMIC_UMIN_32 = 0x00000052, -GL2_OP_ATOMIC_SMAX_32 = 0x00000053, -GL2_OP_ATOMIC_UMAX_32 = 0x00000054, -GL2_OP_ATOMIC_AND_32 = 0x00000055, -GL2_OP_ATOMIC_OR_32 = 0x00000056, -GL2_OP_ATOMIC_XOR_32 = 0x00000057, -GL2_OP_ATOMIC_INC_32 = 0x00000058, -GL2_OP_ATOMIC_DEC_32 = 0x00000059, -GL2_OP_NOP_RTN0 = 0x0000005b, -GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, -GL2_OP_ATOMIC_FMIN_64 = 0x00000062, -GL2_OP_ATOMIC_FMAX_64 = 0x00000063, -GL2_OP_ATOMIC_SWAP_64 = 0x00000067, -GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068, -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, -GL2_OP_ATOMIC_ADD_64 = 0x0000006f, -GL2_OP_ATOMIC_SUB_64 = 0x00000070, -GL2_OP_ATOMIC_SMIN_64 = 0x00000071, -GL2_OP_ATOMIC_UMIN_64 = 0x00000072, -GL2_OP_ATOMIC_SMAX_64 = 0x00000073, -GL2_OP_ATOMIC_UMAX_64 = 0x00000074, -GL2_OP_ATOMIC_AND_64 = 0x00000075, -GL2_OP_ATOMIC_OR_64 = 0x00000076, -GL2_OP_ATOMIC_XOR_64 = 0x00000077, -GL2_OP_ATOMIC_INC_64 = 0x00000078, -GL2_OP_ATOMIC_DEC_64 = 0x00000079, -GL2_OP_ATOMIC_UMAX_8 = 0x0000007a, -GL2_OP_NOP_ACK = 0x0000007b, -} GL2_OP; - -/* - * GL2_OP_MASKS enum - */ - -typedef enum GL2_OP_MASKS { -GL2_OP_MASK_FLUSH_DENROM = 0x00000008, -GL2_OP_MASK_64 = 0x00000020, -GL2_OP_MASK_NO_RTN = 0x00000040, -} GL2_OP_MASKS; - -/******************************************************* - * RLC Enums - *******************************************************/ - -/* - * RLC_DOORBELL_MODE enum - */ - -typedef enum RLC_DOORBELL_MODE { -RLC_DOORBELL_MODE_DISABLE = 0x00000000, -RLC_DOORBELL_MODE_ENABLE = 0x00000001, -RLC_DOORBELL_MODE_ENABLE_PF = 0x00000002, -RLC_DOORBELL_MODE_ENABLE_PF_VF = 0x00000003, -} RLC_DOORBELL_MODE; - -/* - * RLC_PERFCOUNTER_SEL enum - */ - -typedef enum RLC_PERFCOUNTER_SEL { -RLC_PERF_SEL_POWER_FEATURE_0 = 0x00000000, -RLC_PERF_SEL_POWER_FEATURE_1 = 0x00000001, -RLC_PERF_SEL_CP_INTERRUPT = 0x00000002, -RLC_PERF_SEL_GRBM_INTERRUPT = 0x00000003, -RLC_PERF_SEL_SPM_INTERRUPT = 0x00000004, -RLC_PERF_SEL_IH_INTERRUPT = 0x00000005, -RLC_PERF_SEL_SERDES_COMMAND_WRITE = 0x00000006, -} RLC_PERFCOUNTER_SEL; - -/* - * RLC_PERFMON_STATE enum - */ - -typedef enum RLC_PERFMON_STATE { -RLC_PERFMON_STATE_RESET = 0x00000000, -RLC_PERFMON_STATE_ENABLE = 0x00000001, -RLC_PERFMON_STATE_DISABLE = 0x00000002, -RLC_PERFMON_STATE_RESERVED_3 = 0x00000003, -RLC_PERFMON_STATE_RESERVED_4 = 0x00000004, -RLC_PERFMON_STATE_RESERVED_5 = 0x00000005, -RLC_PERFMON_STATE_RESERVED_6 = 0x00000006, -RLC_PERFMON_STATE_ROLLOVER = 0x00000007, -} RLC_PERFMON_STATE; - -/* - * RSPM_CMD enum - */ - -typedef enum RSPM_CMD { -RSPM_CMD_INVALID = 0x00000000, -RSPM_CMD_IDLE = 0x00000001, -RSPM_CMD_CALIBRATE = 0x00000002, -RSPM_CMD_SPM_RESET = 0x00000003, -RSPM_CMD_SPM_START = 0x00000004, -RSPM_CMD_SPM_STOP = 0x00000005, -RSPM_CMD_PERF_RESET = 0x00000006, -RSPM_CMD_PERF_SAMPLE = 0x00000007, -RSPM_CMD_PROF_START = 0x00000008, -RSPM_CMD_PROF_STOP = 0x00000009, -RSPM_CMD_FORCE_SAMPLE = 0x0000000a, -} RSPM_CMD; - -/******************************************************* - * SPI Enums - *******************************************************/ - -/* - * CLKGATE_BASE_MODE enum - */ - -typedef enum CLKGATE_BASE_MODE { -MULT_8 = 0x00000000, -MULT_16 = 0x00000001, -} CLKGATE_BASE_MODE; - -/* - * CLKGATE_SM_MODE enum - */ - -typedef enum CLKGATE_SM_MODE { -ON_SEQ = 0x00000000, -OFF_SEQ = 0x00000001, -PROG_SEQ = 0x00000002, -READ_SEQ = 0x00000003, -SM_MODE_RESERVED = 0x00000004, -} CLKGATE_SM_MODE; - -/* - * SPI_FOG_MODE enum - */ - -typedef enum SPI_FOG_MODE { -SPI_FOG_NONE = 0x00000000, -SPI_FOG_EXP = 0x00000001, -SPI_FOG_EXP2 = 0x00000002, -SPI_FOG_LINEAR = 0x00000003, -} SPI_FOG_MODE; - -/* - * SPI_LB_WAVES_SELECT enum - */ - -typedef enum SPI_LB_WAVES_SELECT { -HS_GS = 0x00000000, -PS = 0x00000001, -CS_NA = 0x00000002, -SPI_LB_WAVES_RSVD = 0x00000003, -} SPI_LB_WAVES_SELECT; - -/* - * SPI_PERFCNT_SEL enum - */ - -typedef enum SPI_PERFCNT_SEL { -SPI_PERF_GS_WINDOW_VALID = 0x00000001, -SPI_PERF_GS_BUSY = 0x00000002, -SPI_PERF_GS_CRAWLER_STALL = 0x00000003, -SPI_PERF_GS_EVENT_WAVE = 0x00000004, -SPI_PERF_GS_WAVE = 0x00000005, -SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000006, -SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000007, -SPI_PERF_GS_FIRST_SUBGRP = 0x00000008, -SPI_PERF_GS_HS_DEALLOC = 0x00000009, -SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000000a, -SPI_PERF_GS_POS0_STALL = 0x0000000b, -SPI_PERF_GS_POS1_STALL = 0x0000000c, -SPI_PERF_GS_INDX0_STALL = 0x0000000d, -SPI_PERF_GS_INDX1_STALL = 0x0000000e, -SPI_PERF_GS_PWS_STALL = 0x0000000f, -SPI_PERF_HS_WINDOW_VALID = 0x00000015, -SPI_PERF_HS_BUSY = 0x00000016, -SPI_PERF_HS_CRAWLER_STALL = 0x00000017, -SPI_PERF_HS_FIRST_WAVE = 0x00000018, -SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000019, -SPI_PERF_HS_EVENT_WAVE = 0x0000001a, -SPI_PERF_HS_WAVE = 0x0000001b, -SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000001c, -SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000001d, -SPI_PERF_HS_PWS_STALL = 0x0000001e, -SPI_PERF_CSGN_WINDOW_VALID = 0x00000025, -SPI_PERF_CSGN_BUSY = 0x00000026, -SPI_PERF_CSGN_NUM_THREADGROUPS = 0x00000027, -SPI_PERF_CSGN_CRAWLER_STALL = 0x00000028, -SPI_PERF_CSGN_EVENT_WAVE = 0x00000029, -SPI_PERF_CSGN_WAVE = 0x0000002a, -SPI_PERF_CSGN_PWS_STALL = 0x0000002b, -SPI_PERF_CSN_WINDOW_VALID = 0x0000002c, -SPI_PERF_CSN_BUSY = 0x0000002d, -SPI_PERF_CSN_NUM_THREADGROUPS = 0x0000002e, -SPI_PERF_CSN_CRAWLER_STALL = 0x0000002f, -SPI_PERF_CSN_EVENT_WAVE = 0x00000030, -SPI_PERF_CSN_WAVE = 0x00000031, -SPI_PERF_PS0_WINDOW_VALID = 0x00000035, -SPI_PERF_PS1_WINDOW_VALID = 0x00000036, -SPI_PERF_PS2_WINDOW_VALID = 0x00000037, -SPI_PERF_PS3_WINDOW_VALID = 0x00000038, -SPI_PERF_PS0_BUSY = 0x00000039, -SPI_PERF_PS1_BUSY = 0x0000003a, -SPI_PERF_PS2_BUSY = 0x0000003b, -SPI_PERF_PS3_BUSY = 0x0000003c, -SPI_PERF_PS0_ACTIVE = 0x0000003d, -SPI_PERF_PS1_ACTIVE = 0x0000003e, -SPI_PERF_PS2_ACTIVE = 0x0000003f, -SPI_PERF_PS3_ACTIVE = 0x00000040, -SPI_PERF_PS0_DEALLOC = 0x00000041, -SPI_PERF_PS1_DEALLOC = 0x00000042, -SPI_PERF_PS2_DEALLOC = 0x00000043, -SPI_PERF_PS3_DEALLOC = 0x00000044, -SPI_PERF_PS0_EVENT_WAVE = 0x00000045, -SPI_PERF_PS1_EVENT_WAVE = 0x00000046, -SPI_PERF_PS2_EVENT_WAVE = 0x00000047, -SPI_PERF_PS3_EVENT_WAVE = 0x00000048, -SPI_PERF_PS0_WAVE = 0x00000049, -SPI_PERF_PS1_WAVE = 0x0000004a, -SPI_PERF_PS2_WAVE = 0x0000004b, -SPI_PERF_PS3_WAVE = 0x0000004c, -SPI_PERF_PS0_OPT_WAVE = 0x0000004d, -SPI_PERF_PS1_OPT_WAVE = 0x0000004e, -SPI_PERF_PS2_OPT_WAVE = 0x0000004f, -SPI_PERF_PS3_OPT_WAVE = 0x00000050, -SPI_PERF_PS0_PRIM_BIN0 = 0x00000051, -SPI_PERF_PS1_PRIM_BIN0 = 0x00000052, -SPI_PERF_PS2_PRIM_BIN0 = 0x00000053, -SPI_PERF_PS3_PRIM_BIN0 = 0x00000054, -SPI_PERF_PS0_PRIM_BIN1 = 0x00000055, -SPI_PERF_PS1_PRIM_BIN1 = 0x00000056, -SPI_PERF_PS2_PRIM_BIN1 = 0x00000057, -SPI_PERF_PS3_PRIM_BIN1 = 0x00000058, -SPI_PERF_PS0_CRAWLER_STALL = 0x00000059, -SPI_PERF_PS1_CRAWLER_STALL = 0x0000005a, -SPI_PERF_PS2_CRAWLER_STALL = 0x0000005b, -SPI_PERF_PS3_CRAWLER_STALL = 0x0000005c, -SPI_PERF_PS_PERS_UPD_FULL0 = 0x0000005d, -SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000005e, -SPI_PERF_PS0_2_WAVE_GROUPS = 0x0000005f, -SPI_PERF_PS1_2_WAVE_GROUPS = 0x00000060, -SPI_PERF_PS2_2_WAVE_GROUPS = 0x00000061, -SPI_PERF_PS3_2_WAVE_GROUPS = 0x00000062, -SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 0x00000063, -SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 0x00000064, -SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 0x00000065, -SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 0x00000066, -SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 0x00000067, -SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 0x00000068, -SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 0x00000069, -SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 0x0000006a, -SPI_PERF_PS_PWS_STALL = 0x0000006b, -SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000008d, -SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000008e, -SPI_PERF_RA_WR_CTL_FULL = 0x0000008f, -SPI_PERF_RA_REQ_NO_ALLOC = 0x00000090, -SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000091, -SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000092, -SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000093, -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000094, -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000095, -SPI_PERF_RA_RES_STALL_PS = 0x00000096, -SPI_PERF_RA_RES_STALL_GS = 0x00000097, -SPI_PERF_RA_RES_STALL_HS = 0x00000098, -SPI_PERF_RA_RES_STALL_CSG = 0x00000099, -SPI_PERF_RA_RES_STALL_CSN = 0x0000009a, -SPI_PERF_RA_TMP_STALL_PS = 0x0000009b, -SPI_PERF_RA_TMP_STALL_GS = 0x0000009c, -SPI_PERF_RA_TMP_STALL_HS = 0x0000009d, -SPI_PERF_RA_TMP_STALL_CSG = 0x0000009e, -SPI_PERF_RA_TMP_STALL_CSN = 0x0000009f, -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x000000a0, -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x000000a1, -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x000000a2, -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x000000a3, -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a4, -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a5, -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a6, -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a7, -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a8, -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a9, -SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000aa, -SPI_PERF_RA_LDS_CU_FULL_HS = 0x000000ab, -SPI_PERF_RA_LDS_CU_FULL_GS = 0x000000ac, -SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000ad, -SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000ae, -SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000af, -SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b0, -SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b1, -SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b2, -SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b3, -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b4, -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b5, -SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b6, -SPI_PERF_RA_WVLIM_STALL_GS = 0x000000b7, -SPI_PERF_RA_WVLIM_STALL_HS = 0x000000b8, -SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000b9, -SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000ba, -SPI_PERF_RA_GS_LOCK = 0x000000bb, -SPI_PERF_RA_HS_LOCK = 0x000000bc, -SPI_PERF_RA_CSG_LOCK = 0x000000bd, -SPI_PERF_RA_CSN_LOCK = 0x000000be, -SPI_PERF_RA_RSV_UPD = 0x000000bf, -SPI_PERF_RA_PRE_ALLOC_STALL = 0x000000c0, -SPI_PERF_RA_GFX_UNDER_TUNNEL = 0x000000c1, -SPI_PERF_RA_CSC_UNDER_TUNNEL = 0x000000c2, -SPI_PERF_RA_WVALLOC_STALL = 0x000000c3, -SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 0x000000c4, -SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 0x000000c5, -SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 0x000000c6, -SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 0x000000c7, -SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 0x000000c8, -SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 0x000000c9, -SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 0x000000ca, -SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 0x000000cb, -SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 0x000000cc, -SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 0x000000cd, -SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 0x000000ce, -SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 0x000000cf, -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 0x000000d0, -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 0x000000d1, -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 0x000000d2, -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 0x000000d3, -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 0x000000d4, -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 0x000000d5, -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 0x000000d6, -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 0x000000d7, -SPI_PERF_EXP_ARB_COL_CNT = 0x000000d8, -SPI_PERF_EXP_ARB_POS_CNT = 0x000000d9, -SPI_PERF_EXP_ARB_GDS_CNT = 0x000000da, -SPI_PERF_EXP_ARB_IDX_CNT = 0x000000db, -SPI_PERF_EXP_WITH_CONFLICT = 0x000000dc, -SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 0x000000dd, -SPI_PERF_GS_EXP_DONE = 0x000000de, -SPI_PERF_PS_EXP_DONE = 0x000000df, -SPI_PERF_PS_EXP_ARB_CONFLICT = 0x000000e0, -SPI_PERF_PS_EXP_ALLOC = 0x000000e1, -SPI_PERF_PS0_WAVEID_STARVED = 0x000000e2, -SPI_PERF_PS1_WAVEID_STARVED = 0x000000e3, -SPI_PERF_PS2_WAVEID_STARVED = 0x000000e4, -SPI_PERF_PS3_WAVEID_STARVED = 0x000000e5, -SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 0x000000e6, -SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 0x000000e7, -SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 0x000000e8, -SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 0x000000e9, -SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 0x000000ea, -SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 0x000000eb, -SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 0x000000ec, -SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 0x000000ed, -SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 0x000000ee, -SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 0x000000ef, -SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 0x000000f0, -SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 0x000000f1, -SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 0x000000f2, -SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 0x000000f3, -SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 0x000000f4, -SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 0x000000f5, -SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000f6, -SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000fd, -SPI_PERF_EXPORT_SCB0_STALL = 0x000000fe, -SPI_PERF_EXPORT_SCB1_STALL = 0x000000ff, -SPI_PERF_EXPORT_SCB2_STALL = 0x00000100, -SPI_PERF_EXPORT_SCB3_STALL = 0x00000101, -SPI_PERF_EXPORT_DB0_STALL = 0x00000102, -SPI_PERF_EXPORT_DB1_STALL = 0x00000103, -SPI_PERF_EXPORT_DB2_STALL = 0x00000104, -SPI_PERF_EXPORT_DB3_STALL = 0x00000105, -SPI_PERF_EXPORT_DB4_STALL = 0x00000106, -SPI_PERF_EXPORT_DB5_STALL = 0x00000107, -SPI_PERF_EXPORT_DB6_STALL = 0x00000108, -SPI_PERF_EXPORT_DB7_STALL = 0x00000109, -SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x0000010a, -SPI_PERF_GS_NGG_STALL_MSG_VAL = 0x0000010b, -SPI_PERF_SWC_PS_WR = 0x0000010c, -SPI_PERF_SWC_GS_WR = 0x0000010d, -SPI_PERF_SWC_HS_WR = 0x0000010e, -SPI_PERF_SWC_CSGN_WR = 0x0000010f, -SPI_PERF_SWC_CSN_WR = 0x00000110, -SPI_PERF_VWC_PS_WR = 0x00000111, -SPI_PERF_VWC_ES_WR = 0x00000112, -SPI_PERF_VWC_GS_WR = 0x00000113, -SPI_PERF_VWC_LS_WR = 0x00000114, -SPI_PERF_VWC_HS_WR = 0x00000115, -SPI_PERF_VWC_CSGN_WR = 0x00000116, -SPI_PERF_VWC_CSN_WR = 0x00000117, -SPI_PERF_EXP_THROT_UPSTEP = 0x00000118, -SPI_PERF_EXP_THROT_DOWNSTEP = 0x00000119, -SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 0x0000011a, -SPI_PERF_BUSY = 0x0000011b, -} SPI_PERFCNT_SEL; - -/* - * SPI_PNT_SPRITE_OVERRIDE enum - */ - -typedef enum SPI_PNT_SPRITE_OVERRIDE { -SPI_PNT_SPRITE_SEL_0 = 0x00000000, -SPI_PNT_SPRITE_SEL_1 = 0x00000001, -SPI_PNT_SPRITE_SEL_S = 0x00000002, -SPI_PNT_SPRITE_SEL_T = 0x00000003, -SPI_PNT_SPRITE_SEL_NONE = 0x00000004, -} SPI_PNT_SPRITE_OVERRIDE; - -/* - * SPI_PS_LDS_GROUP_SIZE enum - */ - -typedef enum SPI_PS_LDS_GROUP_SIZE { -SPI_PS_LDS_GROUP_1 = 0x00000000, -SPI_PS_LDS_GROUP_2 = 0x00000001, -SPI_PS_LDS_GROUP_4 = 0x00000002, -} SPI_PS_LDS_GROUP_SIZE; - -/* - * SPI_SAMPLE_CNTL enum - */ - -typedef enum SPI_SAMPLE_CNTL { -CENTROIDS_ONLY = 0x00000000, -CENTERS_ONLY = 0x00000001, -CENTROIDS_AND_CENTERS = 0x00000002, -UNDEF = 0x00000003, -} SPI_SAMPLE_CNTL; - -/* - * SPI_SHADER_EX_FORMAT enum - */ - -typedef enum SPI_SHADER_EX_FORMAT { -SPI_SHADER_ZERO = 0x00000000, -SPI_SHADER_32_R = 0x00000001, -SPI_SHADER_32_GR = 0x00000002, -SPI_SHADER_32_AR = 0x00000003, -SPI_SHADER_FP16_ABGR = 0x00000004, -SPI_SHADER_UNORM16_ABGR = 0x00000005, -SPI_SHADER_SNORM16_ABGR = 0x00000006, -SPI_SHADER_UINT16_ABGR = 0x00000007, -SPI_SHADER_SINT16_ABGR = 0x00000008, -SPI_SHADER_32_ABGR = 0x00000009, -} SPI_SHADER_EX_FORMAT; - -/* - * SPI_SHADER_FORMAT enum - */ - -typedef enum SPI_SHADER_FORMAT { -SPI_SHADER_NONE = 0x00000000, -SPI_SHADER_1COMP = 0x00000001, -SPI_SHADER_2COMP = 0x00000002, -SPI_SHADER_4COMPRESS = 0x00000003, -SPI_SHADER_4COMP = 0x00000004, -} SPI_SHADER_FORMAT; - -/******************************************************* - * SQ Enums - *******************************************************/ - -/* - * SH_MEM_ADDRESS_MODE enum - */ - -typedef enum SH_MEM_ADDRESS_MODE { -SH_MEM_ADDRESS_MODE_64 = 0x00000000, -SH_MEM_ADDRESS_MODE_32 = 0x00000001, -} SH_MEM_ADDRESS_MODE; - -/* - * SH_MEM_ALIGNMENT_MODE enum - */ - -typedef enum SH_MEM_ALIGNMENT_MODE { -SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, -SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, -} SH_MEM_ALIGNMENT_MODE; - -/* - * SQG_PERF_SEL enum - */ - -typedef enum SQG_PERF_SEL { -SQG_PERF_SEL_NONE = 0x00000000, -SQG_PERF_SEL_MSG_BUS_BUSY = 0x00000001, -SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000002, -SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000003, -SQG_PERF_SEL_EXP_BUS0_BUSY = 0x00000004, -SQG_PERF_SEL_EXP_BUS1_BUSY = 0x00000005, -SQG_PERF_SEL_TTRACE_REQS = 0x00000006, -SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000007, -SQG_PERF_SEL_TTRACE_STALL = 0x00000008, -SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000009, -SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x0000000a, -SQG_PERF_SEL_EVENTS = 0x0000000b, -SQG_PERF_SEL_WAVES_RESTORED = 0x0000000c, -SQG_PERF_SEL_WAVES_SAVED = 0x0000000d, -SQG_PERF_SEL_ACCUM_PREV = 0x0000000e, -SQG_PERF_SEL_CYCLES = 0x0000000f, -SQG_PERF_SEL_BUSY_CYCLES = 0x00000010, -SQG_PERF_SEL_WAVE_CYCLES = 0x00000011, -SQG_PERF_SEL_MSG = 0x00000012, -SQG_PERF_SEL_MSG_INTERRUPT = 0x00000013, -SQG_PERF_SEL_WAVES = 0x00000014, -SQG_PERF_SEL_WAVES_32 = 0x00000015, -SQG_PERF_SEL_WAVES_64 = 0x00000016, -SQG_PERF_SEL_LEVEL_WAVES = 0x00000017, -SQG_PERF_SEL_ITEMS = 0x00000018, -SQG_PERF_SEL_WAVE32_ITEMS = 0x00000019, -SQG_PERF_SEL_WAVE64_ITEMS = 0x0000001a, -SQG_PERF_SEL_PS_QUADS = 0x0000001b, -SQG_PERF_SEL_WAVES_EQ_64 = 0x0000001c, -SQG_PERF_SEL_WAVES_EQ_32 = 0x0000001d, -SQG_PERF_SEL_WAVES_LT_64 = 0x0000001e, -SQG_PERF_SEL_WAVES_LT_48 = 0x0000001f, -SQG_PERF_SEL_WAVES_LT_32 = 0x00000020, -SQG_PERF_SEL_WAVES_LT_16 = 0x00000021, -SQG_PERF_SEL_DUMMY_LAST = 0x00000022, -} SQG_PERF_SEL; - -/* - * SQ_CAC_POWER_SEL enum - */ - -typedef enum SQ_CAC_POWER_SEL { -SQ_CAC_POWER_VALU = 0x00000000, -SQ_CAC_POWER_VALU0 = 0x00000001, -SQ_CAC_POWER_VALU1 = 0x00000002, -SQ_CAC_POWER_VALU2 = 0x00000003, -SQ_CAC_POWER_GPR_RD = 0x00000004, -SQ_CAC_POWER_GPR_WR = 0x00000005, -SQ_CAC_POWER_LDS_BUSY = 0x00000006, -SQ_CAC_POWER_ALU_BUSY = 0x00000007, -SQ_CAC_POWER_TEX_BUSY = 0x00000008, -} SQ_CAC_POWER_SEL; - -/* - * SQ_EDC_INFO_SOURCE enum - */ - -typedef enum SQ_EDC_INFO_SOURCE { -SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, -SQ_EDC_INFO_SOURCE_INST = 0x00000001, -SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, -SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, -SQ_EDC_INFO_SOURCE_LDS = 0x00000004, -SQ_EDC_INFO_SOURCE_GDS = 0x00000005, -SQ_EDC_INFO_SOURCE_TA = 0x00000006, -} SQ_EDC_INFO_SOURCE; - -/* - * SQ_IBUF_ST enum - */ - -typedef enum SQ_IBUF_ST { -SQ_IBUF_IB_IDLE = 0x00000000, -SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, -SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, -SQ_IBUF_IB_LE_4DW = 0x00000003, -SQ_IBUF_IB_WAIT_DRET = 0x00000004, -SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, -SQ_IBUF_IB_DRET = 0x00000006, -SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, -} SQ_IBUF_ST; - -/* - * SQ_IMG_FILTER_TYPE enum - */ - -typedef enum SQ_IMG_FILTER_TYPE { -SQ_IMG_FILTER_MODE_BLEND = 0x00000000, -SQ_IMG_FILTER_MODE_MIN = 0x00000001, -SQ_IMG_FILTER_MODE_MAX = 0x00000002, -} SQ_IMG_FILTER_TYPE; - -/* - * SQ_IND_CMD_CMD enum - */ - -typedef enum SQ_IND_CMD_CMD { -SQ_IND_CMD_CMD_NULL = 0x00000000, -SQ_IND_CMD_CMD_SETHALT = 0x00000001, -SQ_IND_CMD_CMD_SAVECTX = 0x00000002, -SQ_IND_CMD_CMD_KILL = 0x00000003, -SQ_IND_CMD_CMD_TRAP_AFTER_INST = 0x00000004, -SQ_IND_CMD_CMD_TRAP = 0x00000005, -SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, -SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, -SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008, -} SQ_IND_CMD_CMD; - -/* - * SQ_IND_CMD_MODE enum - */ - -typedef enum SQ_IND_CMD_MODE { -SQ_IND_CMD_MODE_SINGLE = 0x00000000, -SQ_IND_CMD_MODE_BROADCAST = 0x00000001, -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, -SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, -SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, -} SQ_IND_CMD_MODE; - -/* - * SQ_INST_STR_ST enum - */ - -typedef enum SQ_INST_STR_ST { -SQ_INST_STR_IB_WAVE_NORML = 0x00000000, -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000004, -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005, -} SQ_INST_STR_ST; - -/* - * SQ_INST_TYPE enum - */ - -typedef enum SQ_INST_TYPE { -SQ_INST_TYPE_VALU = 0x00000000, -SQ_INST_TYPE_SCALAR = 0x00000001, -SQ_INST_TYPE_TEX = 0x00000002, -SQ_INST_TYPE_LDS = 0x00000003, -SQ_INST_TYPE_LDS_DIRECT = 0x00000004, -SQ_INST_TYPE_EXP = 0x00000005, -SQ_INST_TYPE_MSG = 0x00000006, -SQ_INST_TYPE_BARRIER = 0x00000007, -SQ_INST_TYPE_BRANCH_NOT_TAKEN = 0x00000008, -SQ_INST_TYPE_BRANCH_TAKEN = 0x00000009, -SQ_INST_TYPE_JUMP = 0x0000000a, -SQ_INST_TYPE_OTHER = 0x0000000b, -SQ_INST_TYPE_NONE = 0x0000000c, -} SQ_INST_TYPE; - -/* - * SQ_LLC_CTL enum - */ - -typedef enum SQ_LLC_CTL { -SQ_LLC_0 = 0x00000000, -SQ_LLC_1 = 0x00000001, -SQ_LLC_RSVD_2 = 0x00000002, -SQ_LLC_BYPASS = 0x00000003, -} SQ_LLC_CTL; - -/* - * SQ_NO_INST_ISSUE enum - */ - -typedef enum SQ_NO_INST_ISSUE { -SQ_NO_INST_ISSUE_NO_INSTS = 0x00000000, -SQ_NO_INST_ISSUE_ALU_DEP = 0x00000001, -SQ_NO_INST_ISSUE_S_WAITCNT = 0x00000002, -SQ_NO_INST_ISSUE_NO_ARB_WIN = 0x00000003, -SQ_NO_INST_ISSUE_SLEEP_WAIT = 0x00000004, -SQ_NO_INST_ISSUE_BARRIER_WAIT = 0x00000005, -SQ_NO_INST_ISSUE_OTHER = 0x00000006, -} SQ_NO_INST_ISSUE; - -/* - * SQ_OOB_SELECT enum - */ - -typedef enum SQ_OOB_SELECT { -SQ_OOB_INDEX_AND_OFFSET = 0x00000000, -SQ_OOB_INDEX_ONLY = 0x00000001, -SQ_OOB_NUM_RECORDS_0 = 0x00000002, -SQ_OOB_COMPLETE = 0x00000003, -} SQ_OOB_SELECT; - -/* - * SQ_PERF_SEL enum - */ - -typedef enum SQ_PERF_SEL { -SQ_PERF_SEL_NONE = 0x00000000, -SQ_PERF_SEL_ACCUM_PREV = 0x00000001, -SQ_PERF_SEL_CYCLES = 0x00000002, -SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, -SQ_PERF_SEL_WAVES = 0x00000004, -SQ_PERF_SEL_WAVES_32 = 0x00000005, -SQ_PERF_SEL_WAVES_64 = 0x00000006, -SQ_PERF_SEL_LEVEL_WAVES = 0x00000007, -SQ_PERF_SEL_ITEMS = 0x00000008, -SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009, -SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a, -SQ_PERF_SEL_PS_QUADS = 0x0000000b, -SQ_PERF_SEL_EVENTS = 0x0000000c, -SQ_PERF_SEL_WAVES_EQ_32 = 0x0000000d, -SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000e, -SQ_PERF_SEL_WAVES_LT_64 = 0x0000000f, -SQ_PERF_SEL_WAVES_LT_48 = 0x00000010, -SQ_PERF_SEL_WAVES_LT_32 = 0x00000011, -SQ_PERF_SEL_WAVES_LT_16 = 0x00000012, -SQ_PERF_SEL_WAVES_RESTORED = 0x00000013, -SQ_PERF_SEL_WAVES_SAVED = 0x00000014, -SQ_PERF_SEL_MSG = 0x00000015, -SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016, -SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000017, -SQ_PERF_SEL_WAVE_CYCLES = 0x00000018, -SQ_PERF_SEL_WAVE_READY = 0x00000019, -SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001a, -SQ_PERF_SEL_WAIT_INST_VALU = 0x0000001b, -SQ_PERF_SEL_WAIT_INST_SCA = 0x0000001c, -SQ_PERF_SEL_WAIT_INST_LDS = 0x0000001d, -SQ_PERF_SEL_WAIT_INST_TEX = 0x0000001e, -SQ_PERF_SEL_WAIT_INST_FLAT = 0x0000001f, -SQ_PERF_SEL_WAIT_INST_VMEM = 0x00000020, -SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000021, -SQ_PERF_SEL_WAIT_INST_BR_MSG = 0x00000022, -SQ_PERF_SEL_WAIT_ANY = 0x00000023, -SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000024, -SQ_PERF_SEL_WAIT_CNT_VMVS = 0x00000025, -SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000026, -SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000027, -SQ_PERF_SEL_WAIT_TTRACE = 0x00000028, -SQ_PERF_SEL_WAIT_IFETCH = 0x00000029, -SQ_PERF_SEL_WAIT_BARRIER = 0x0000002a, -SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x0000002b, -SQ_PERF_SEL_WAIT_SLEEP = 0x0000002c, -SQ_PERF_SEL_WAIT_DELAY_ALU = 0x0000002d, -SQ_PERF_SEL_WAIT_DEPCTR = 0x0000002e, -SQ_PERF_SEL_WAIT_OTHER = 0x0000002f, -SQ_PERF_SEL_INSTS_ALL = 0x00000030, -SQ_PERF_SEL_INSTS_BRANCH = 0x00000031, -SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000032, -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x00000033, -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 0x00000034, -SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000035, -SQ_PERF_SEL_INSTS_GDS = 0x00000036, -SQ_PERF_SEL_INSTS_EXP = 0x00000037, -SQ_PERF_SEL_INSTS_FLAT = 0x00000038, -SQ_PERF_SEL_INSTS_LDS = 0x00000039, -SQ_PERF_SEL_INSTS_SALU = 0x0000003a, -SQ_PERF_SEL_INSTS_SMEM = 0x0000003b, -SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000003c, -SQ_PERF_SEL_INSTS_SENDMSG = 0x0000003d, -SQ_PERF_SEL_INSTS_VALU = 0x0000003e, -SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x0000003f, -SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000040, -SQ_PERF_SEL_INSTS_TEX = 0x00000041, -SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000042, -SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000043, -SQ_PERF_SEL_INSTS_DELAY_ALU = 0x00000044, -SQ_PERF_SEL_INSTS_INTERNAL = 0x00000045, -SQ_PERF_SEL_INSTS_WAVE32 = 0x00000046, -SQ_PERF_SEL_INSTS_WAVE32_FLAT = 0x00000047, -SQ_PERF_SEL_INSTS_WAVE32_LDS = 0x00000048, -SQ_PERF_SEL_INSTS_WAVE32_VALU = 0x00000049, -SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 0x0000004a, -SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 0x0000004b, -SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 0x0000004c, -SQ_PERF_SEL_INSTS_WAVE32_TEX = 0x0000004d, -SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 0x0000004e, -SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 0x0000004f, -SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000050, -SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000051, -SQ_PERF_SEL_WAVE32_INSTS = 0x00000052, -SQ_PERF_SEL_WAVE64_INSTS = 0x00000053, -SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000054, -SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000055, -SQ_PERF_SEL_INST_LEVEL_EXP = 0x00000056, -SQ_PERF_SEL_INST_LEVEL_GDS = 0x00000057, -SQ_PERF_SEL_INST_LEVEL_LDS = 0x00000058, -SQ_PERF_SEL_INST_LEVEL_SMEM = 0x00000059, -SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x0000005a, -SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x0000005b, -SQ_PERF_SEL_IFETCH_REQS = 0x0000005c, -SQ_PERF_SEL_IFETCH_LEVEL = 0x0000005d, -SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000005e, -SQ_PERF_SEL_VALU_SGATHER_STALL = 0x0000005f, -SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x00000060, -SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000061, -SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000062, -SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000063, -SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000064, -SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000065, -SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 0x00000066, -SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000067, -SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000068, -SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000069, -SQ_PERF_SEL_INST_CYCLES_VMEM = 0x0000006a, -SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x0000006b, -SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x0000006c, -SQ_PERF_SEL_INST_CYCLES_LDS = 0x0000006d, -SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000006e, -SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000006f, -SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x00000070, -SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000071, -SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000072, -SQ_PERF_SEL_VALU_STARVE = 0x00000073, -SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x00000074, -SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x00000075, -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000076, -SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000077, -SQ_PERF_SEL_VMEM_BUS_STALL = 0x00000078, -SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000079, -SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000007a, -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000007b, -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000007c, -SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x0000007d, -SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x0000007e, -SQ_PERF_SEL_SALU_PIPE_STALL = 0x0000007f, -SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x00000080, -SQ_PERF_SEL_MSG_BUS_BUSY = 0x00000081, -SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x00000082, -SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000083, -SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000084, -SQ_PERF_SEL_EXP_BUS0_BUSY = 0x00000085, -SQ_PERF_SEL_EXP_BUS1_BUSY = 0x00000086, -SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x00000087, -SQ_PERF_SEL_USER0 = 0x00000088, -SQ_PERF_SEL_USER1 = 0x00000089, -SQ_PERF_SEL_USER2 = 0x0000008a, -SQ_PERF_SEL_USER3 = 0x0000008b, -SQ_PERF_SEL_USER4 = 0x0000008c, -SQ_PERF_SEL_USER5 = 0x0000008d, -SQ_PERF_SEL_USER6 = 0x0000008e, -SQ_PERF_SEL_USER7 = 0x0000008f, -SQ_PERF_SEL_USER8 = 0x00000090, -SQ_PERF_SEL_USER9 = 0x00000091, -SQ_PERF_SEL_USER10 = 0x00000092, -SQ_PERF_SEL_USER11 = 0x00000093, -SQ_PERF_SEL_USER12 = 0x00000094, -SQ_PERF_SEL_USER13 = 0x00000095, -SQ_PERF_SEL_USER14 = 0x00000096, -SQ_PERF_SEL_USER15 = 0x00000097, -SQ_PERF_SEL_USER_LEVEL0 = 0x00000098, -SQ_PERF_SEL_USER_LEVEL1 = 0x00000099, -SQ_PERF_SEL_USER_LEVEL2 = 0x0000009a, -SQ_PERF_SEL_USER_LEVEL3 = 0x0000009b, -SQ_PERF_SEL_USER_LEVEL4 = 0x0000009c, -SQ_PERF_SEL_USER_LEVEL5 = 0x0000009d, -SQ_PERF_SEL_USER_LEVEL6 = 0x0000009e, -SQ_PERF_SEL_USER_LEVEL7 = 0x0000009f, -SQ_PERF_SEL_USER_LEVEL8 = 0x000000a0, -SQ_PERF_SEL_USER_LEVEL9 = 0x000000a1, -SQ_PERF_SEL_USER_LEVEL10 = 0x000000a2, -SQ_PERF_SEL_USER_LEVEL11 = 0x000000a3, -SQ_PERF_SEL_USER_LEVEL12 = 0x000000a4, -SQ_PERF_SEL_USER_LEVEL13 = 0x000000a5, -SQ_PERF_SEL_USER_LEVEL14 = 0x000000a6, -SQ_PERF_SEL_USER_LEVEL15 = 0x000000a7, -SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000a8, -SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a9, -SQ_PERF_SEL_INSTS_VALU_TRANS = 0x000000aa, -SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 0x000000ab, -SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 0x000000ac, -SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 0x000000ad, -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 0x000000ae, -SQ_PERF_SEL_INSTS_VALU_VINTERP = 0x000000af, -SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 0x000000b0, -SQ_PERF_SEL_OVERFLOW_PREV = 0x000000b1, -SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 0x000000b2, -SQ_PERF_SEL_INSTS_VALU_1_PASS = 0x000000b3, -SQ_PERF_SEL_INSTS_VALU_2_PASS = 0x000000b4, -SQ_PERF_SEL_INSTS_VALU_4_PASS = 0x000000b5, -SQ_PERF_SEL_INSTS_VALU_DP = 0x000000b6, -SQ_PERF_SEL_SP_CONST_CYCLES = 0x000000b7, -SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 0x000000b8, -SQ_PERF_SEL_ITEMS_VALU = 0x000000b9, -SQ_PERF_SEL_ITEMS_MAX_VALU = 0x000000ba, -SQ_PERF_SEL_ITEM_CYCLES_VMEM = 0x000000bb, -SQ_PERF_SEL_DUMMY_END = 0x000000bc, -SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, -SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x00000100, -SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x00000101, -SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x00000102, -SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000103, -SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000104, -SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000105, -SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000106, -SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000107, -SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000108, -SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000109, -SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000010a, -SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000010b, -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010c, -SQC_PERF_SEL_ICACHE_REQ = 0x0000010d, -SQC_PERF_SEL_ICACHE_HITS = 0x0000010e, -SQC_PERF_SEL_ICACHE_MISSES = 0x0000010f, -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000110, -SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000111, -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000112, -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000113, -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000114, -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000115, -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000116, -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000117, -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000118, -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000119, -SQC_PERF_SEL_TC_REQ = 0x0000011a, -SQC_PERF_SEL_TC_INST_REQ = 0x0000011b, -SQC_PERF_SEL_TC_DATA_READ_REQ = 0x0000011c, -SQC_PERF_SEL_TC_STALL = 0x0000011d, -SQC_PERF_SEL_TC_STARVE = 0x0000011e, -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000011f, -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000120, -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000121, -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000122, -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000123, -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000124, -SQC_PERF_SEL_DCACHE_REQ = 0x00000125, -SQC_PERF_SEL_DCACHE_HITS = 0x00000126, -SQC_PERF_SEL_DCACHE_MISSES = 0x00000127, -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000128, -SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000129, -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012a, -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x0000012b, -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000012c, -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000012d, -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000012e, -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000012f, -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000130, -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000131, -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000132, -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000133, -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000134, -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000135, -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000136, -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000137, -SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000138, -SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000139, -SQC_PERF_SEL_TD_VGPR_BUSY = 0x0000013a, -SQC_PERF_SEL_LDS_VGPR_BUSY = 0x0000013b, -SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 0x0000013c, -SQC_PERF_SEL_ICACHE_GCR = 0x0000013d, -SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000013e, -SQC_PERF_SEL_DCACHE_GCR = 0x0000013f, -SQC_PERF_SEL_DCACHE_GCR_HITS = 0x00000140, -SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x00000141, -SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x00000142, -SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 0x00000143, -SQC_PERF_SEL_DUMMY_LAST = 0x00000144, -SP_PERF_SEL_DST_BUF_ALLOC_STALL = 0x000001c0, -SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 0x000001c1, -SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 0x000001c2, -SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 0x000001c3, -SP_PERF_SEL_DST_BUF_ODD_DIRTY = 0x000001c4, -SP_PERF_SEL_SRC_CACHE_HIT_B0 = 0x000001c5, -SP_PERF_SEL_SRC_CACHE_HIT_B1 = 0x000001c6, -SP_PERF_SEL_SRC_CACHE_HIT_B2 = 0x000001c7, -SP_PERF_SEL_SRC_CACHE_HIT_B3 = 0x000001c8, -SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 0x000001c9, -SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 0x000001ca, -SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 0x000001cb, -SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 0x000001cc, -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 0x000001cd, -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 0x000001ce, -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 0x000001cf, -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 0x000001d0, -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 0x000001d1, -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 0x000001d2, -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 0x000001d3, -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 0x000001d4, -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 0x000001d5, -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 0x000001d6, -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 0x000001d7, -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 0x000001d8, -SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 0x000001d9, -SP_PERF_SEL_VALU_OPERAND = 0x000001da, -SP_PERF_SEL_VALU_VGPR_OPERAND = 0x000001db, -SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 0x000001dc, -SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 0x000001dd, -SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 0x000001de, -SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 0x000001df, -SP_PERF_SEL_VALU_STALL = 0x000001e0, -SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 0x000001e1, -SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 0x000001e2, -SP_PERF_SEL_VALU_STALL_VDST_FWD = 0x000001e3, -SP_PERF_SEL_VALU_STALL_SDST_FWD = 0x000001e4, -SP_PERF_SEL_VALU_STALL_DST_STALL = 0x000001e5, -SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6, -SP_PERF_SEL_VGPR_VMEM_RD = 0x000001e7, -SP_PERF_SEL_VGPR_EXP_RD = 0x000001e8, -SP_PERF_SEL_VGPR_SPI_WR = 0x000001e9, -SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 0x000001ea, -SP_PERF_SEL_VGPR_WR = 0x000001eb, -SP_PERF_SEL_VGPR_RD = 0x000001ec, -SP_PERF_SEL_DUMMY_LAST = 0x000001ed, -SQ_PERF_SEL_NONE2 = 0x000001ff, -} SQ_PERF_SEL; - -/* - * SQ_ROUND_MODE enum - */ - -typedef enum SQ_ROUND_MODE { -SQ_ROUND_NEAREST_EVEN = 0x00000000, -SQ_ROUND_PLUS_INFINITY = 0x00000001, -SQ_ROUND_MINUS_INFINITY = 0x00000002, -SQ_ROUND_TO_ZERO = 0x00000003, -} SQ_ROUND_MODE; - -/* - * SQ_RSRC_BUF_TYPE enum - */ - -typedef enum SQ_RSRC_BUF_TYPE { -SQ_RSRC_BUF = 0x00000000, -SQ_RSRC_BUF_RSVD_1 = 0x00000001, -SQ_RSRC_BUF_RSVD_2 = 0x00000002, -SQ_RSRC_BUF_RSVD_3 = 0x00000003, -} SQ_RSRC_BUF_TYPE; - -/* - * SQ_RSRC_FLAT_TYPE enum - */ - -typedef enum SQ_RSRC_FLAT_TYPE { -SQ_RSRC_FLAT_RSVD_0 = 0x00000000, -SQ_RSRC_FLAT = 0x00000001, -SQ_RSRC_FLAT_RSVD_2 = 0x00000002, -SQ_RSRC_FLAT_RSVD_3 = 0x00000003, -} SQ_RSRC_FLAT_TYPE; - -/* - * SQ_RSRC_IMG_TYPE enum - */ - -typedef enum SQ_RSRC_IMG_TYPE { -SQ_RSRC_IMG_RSVD_0 = 0x00000000, -SQ_RSRC_IMG_RSVD_1 = 0x00000001, -SQ_RSRC_IMG_RSVD_2 = 0x00000002, -SQ_RSRC_IMG_RSVD_3 = 0x00000003, -SQ_RSRC_IMG_RSVD_4 = 0x00000004, -SQ_RSRC_IMG_RSVD_5 = 0x00000005, -SQ_RSRC_IMG_RSVD_6 = 0x00000006, -SQ_RSRC_IMG_RSVD_7 = 0x00000007, -SQ_RSRC_IMG_1D = 0x00000008, -SQ_RSRC_IMG_2D = 0x00000009, -SQ_RSRC_IMG_3D = 0x0000000a, -SQ_RSRC_IMG_CUBE = 0x0000000b, -SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, -SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, -SQ_RSRC_IMG_2D_MSAA = 0x0000000e, -SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, -} SQ_RSRC_IMG_TYPE; - -/* - * SQ_SEL_XYZW01 enum - */ - -typedef enum SQ_SEL_XYZW01 { -SQ_SEL_0 = 0x00000000, -SQ_SEL_1 = 0x00000001, -SQ_SEL_N_BC_1 = 0x00000002, -SQ_SEL_RESERVED_1 = 0x00000003, -SQ_SEL_X = 0x00000004, -SQ_SEL_Y = 0x00000005, -SQ_SEL_Z = 0x00000006, -SQ_SEL_W = 0x00000007, -} SQ_SEL_XYZW01; - -/* - * SQ_TEX_ANISO_RATIO enum - */ - -typedef enum SQ_TEX_ANISO_RATIO { -SQ_TEX_ANISO_RATIO_1 = 0x00000000, -SQ_TEX_ANISO_RATIO_2 = 0x00000001, -SQ_TEX_ANISO_RATIO_4 = 0x00000002, -SQ_TEX_ANISO_RATIO_8 = 0x00000003, -SQ_TEX_ANISO_RATIO_16 = 0x00000004, -} SQ_TEX_ANISO_RATIO; - -/* - * SQ_TEX_BORDER_COLOR enum - */ - -typedef enum SQ_TEX_BORDER_COLOR { -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, -SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, -} SQ_TEX_BORDER_COLOR; - -/* - * SQ_TEX_CLAMP enum - */ - -typedef enum SQ_TEX_CLAMP { -SQ_TEX_WRAP = 0x00000000, -SQ_TEX_MIRROR = 0x00000001, -SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, -SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, -SQ_TEX_CLAMP_BORDER = 0x00000006, -SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, -} SQ_TEX_CLAMP; - -/* - * SQ_TEX_DEPTH_COMPARE enum - */ - -typedef enum SQ_TEX_DEPTH_COMPARE { -SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, -SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, -SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, -SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, -SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, -} SQ_TEX_DEPTH_COMPARE; - -/* - * SQ_TEX_MIP_FILTER enum - */ - -typedef enum SQ_TEX_MIP_FILTER { -SQ_TEX_MIP_FILTER_NONE = 0x00000000, -SQ_TEX_MIP_FILTER_POINT = 0x00000001, -SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, -} SQ_TEX_MIP_FILTER; - -/* - * SQ_TEX_XY_FILTER enum - */ - -typedef enum SQ_TEX_XY_FILTER { -SQ_TEX_XY_FILTER_POINT = 0x00000000, -SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, -SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, -} SQ_TEX_XY_FILTER; - -/* - * SQ_TEX_Z_FILTER enum - */ - -typedef enum SQ_TEX_Z_FILTER { -SQ_TEX_Z_FILTER_NONE = 0x00000000, -SQ_TEX_Z_FILTER_POINT = 0x00000001, -SQ_TEX_Z_FILTER_LINEAR = 0x00000002, -} SQ_TEX_Z_FILTER; - -/* - * SQ_TT_MODE enum - */ - -typedef enum SQ_TT_MODE { -SQ_TT_MODE_OFF = 0x00000000, -SQ_TT_MODE_ON = 0x00000001, -SQ_TT_MODE_GLOBAL = 0x00000002, -SQ_TT_MODE_DETAIL = 0x00000003, -} SQ_TT_MODE; - -/* - * SQ_TT_RT_FREQ enum - */ - -typedef enum SQ_TT_RT_FREQ { -SQ_TT_RT_FREQ_NEVER = 0x00000000, -SQ_TT_RT_FREQ_1024_CLK = 0x00000001, -SQ_TT_RT_FREQ_4096_CLK = 0x00000002, -} SQ_TT_RT_FREQ; - -/* - * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum - */ - -typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE { -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 0x00000001, -SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 0x00000002, -} SQ_TT_TOKEN_MASK_INST_EXCLUDE; - -/* - * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum - */ - -typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT { -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0x00000000, -SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 0x00000001, -} SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT; - -/* - * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum - */ - -typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE { -SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 0x00000001, -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 0x00000002, -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 0x00000004, -} SQ_TT_TOKEN_MASK_REG_EXCLUDE; - -/* - * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum - */ - -typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT { -SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0x00000000, -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 0x00000001, -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 0x00000002, -} SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT; - -/* - * SQ_TT_TOKEN_MASK_REG_INCLUDE enum - */ - -typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE { -SQ_TT_TOKEN_MASK_SQDEC_BIT = 0x00000001, -SQ_TT_TOKEN_MASK_SHDEC_BIT = 0x00000002, -SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 0x00000004, -SQ_TT_TOKEN_MASK_COMP_BIT = 0x00000008, -SQ_TT_TOKEN_MASK_CONTEXT_BIT = 0x00000010, -SQ_TT_TOKEN_MASK_CONFIG_BIT = 0x00000020, -SQ_TT_TOKEN_MASK_ALL_BIT = 0x00000040, -SQ_TT_TOKEN_MASK_RSVD_BIT = 0x00000080, -} SQ_TT_TOKEN_MASK_REG_INCLUDE; - -/* - * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum - */ - -typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT { -SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0x00000000, -SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 0x00000001, -SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 0x00000002, -SQ_TT_TOKEN_MASK_COMP_SHIFT = 0x00000003, -SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 0x00000004, -SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 0x00000005, -SQ_TT_TOKEN_MASK_ALL_SHIFT = 0x00000006, -SQ_TT_TOKEN_MASK_RSVD_SHIFT = 0x00000007, -} SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT; - -/* - * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum - */ - -typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT { -SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0x00000000, -SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 0x00000001, -SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 0x00000002, -SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 0x00000003, -SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 0x00000004, -SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 0x00000005, -SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 0x00000006, -SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 0x00000007, -SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 0x00000008, -SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 0x00000009, -SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 0x0000000a, -SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 0x0000000b, -} SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT; - -/* - * SQ_TT_UTIL_TIMER enum - */ - -typedef enum SQ_TT_UTIL_TIMER { -SQ_TT_UTIL_TIMER_100_CLK = 0x00000000, -SQ_TT_UTIL_TIMER_250_CLK = 0x00000001, -} SQ_TT_UTIL_TIMER; - -/* - * SQ_TT_WAVESTART_MODE enum - */ - -typedef enum SQ_TT_WAVESTART_MODE { -SQ_TT_WAVESTART_MODE_SHORT = 0x00000000, -SQ_TT_WAVESTART_MODE_ALLOC = 0x00000001, -SQ_TT_WAVESTART_MODE_PBB_ID = 0x00000002, -} SQ_TT_WAVESTART_MODE; - -/* - * SQ_TT_WTYPE_INCLUDE enum - */ - -typedef enum SQ_TT_WTYPE_INCLUDE { -SQ_TT_WTYPE_INCLUDE_PS_BIT = 0x00000001, -SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 0x00000002, -SQ_TT_WTYPE_INCLUDE_GS_BIT = 0x00000004, -SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 0x00000008, -SQ_TT_WTYPE_INCLUDE_HS_BIT = 0x00000010, -SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 0x00000020, -SQ_TT_WTYPE_INCLUDE_CS_BIT = 0x00000040, -} SQ_TT_WTYPE_INCLUDE; - -/* - * SQ_TT_WTYPE_INCLUDE_SHIFT enum - */ - -typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT { -SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0x00000000, -SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 0x00000001, -SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 0x00000002, -SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 0x00000003, -SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 0x00000004, -SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 0x00000005, -SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 0x00000006, -} SQ_TT_WTYPE_INCLUDE_SHIFT; - -/* - * SQ_WATCH_MODES enum - */ - -typedef enum SQ_WATCH_MODES { -SQ_WATCH_MODE_READ = 0x00000000, -SQ_WATCH_MODE_NONREAD = 0x00000001, -SQ_WATCH_MODE_ATOMIC = 0x00000002, -SQ_WATCH_MODE_ALL = 0x00000003, -} SQ_WATCH_MODES; - -/* - * SQ_WAVE_FWD_PROG_INTERVAL enum - */ - -typedef enum SQ_WAVE_FWD_PROG_INTERVAL { -SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0x00000000, -SQ_WAVE_FWD_PROG_INTERVAL_256 = 0x00000001, -SQ_WAVE_FWD_PROG_INTERVAL_1024 = 0x00000002, -SQ_WAVE_FWD_PROG_INTERVAL_4096 = 0x00000003, -} SQ_WAVE_FWD_PROG_INTERVAL; - -/* - * SQ_WAVE_IB_ECC_ST enum - */ - -typedef enum SQ_WAVE_IB_ECC_ST { -SQ_WAVE_IB_ECC_CLEAN = 0x00000000, -SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, -SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, -} SQ_WAVE_IB_ECC_ST; - -/* - * SQ_WAVE_SCHED_MODES enum - */ - -typedef enum SQ_WAVE_SCHED_MODES { -SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000, -SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001, -SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 0x00000002, -} SQ_WAVE_SCHED_MODES; - -/* - * SQ_WAVE_TYPE enum - */ - -typedef enum SQ_WAVE_TYPE { -SQ_WAVE_TYPE_PS = 0x00000000, -SQ_WAVE_TYPE_RSVD0 = 0x00000001, -SQ_WAVE_TYPE_GS = 0x00000002, -SQ_WAVE_TYPE_RSVD1 = 0x00000003, -SQ_WAVE_TYPE_HS = 0x00000004, -SQ_WAVE_TYPE_RSVD2 = 0x00000005, -SQ_WAVE_TYPE_CS = 0x00000006, -SQ_WAVE_TYPE_PS1 = 0x00000007, -SQ_WAVE_TYPE_PS2 = 0x00000008, -SQ_WAVE_TYPE_PS3 = 0x00000009, -} SQ_WAVE_TYPE; - -/* - * SQ_WAVE_TYPE value - */ - -#define SQ_WAVE_TYPE_PS0 0x00000000 - -/* - * SQIND_PARTITIONS value - */ - -#define SQIND_GLOBAL_REGS_OFFSET 0x00000000 -#define SQIND_GLOBAL_REGS_SIZE 0x00000008 -#define SQIND_LOCAL_REGS_OFFSET 0x00000008 -#define SQIND_LOCAL_REGS_SIZE 0x00000008 -#define SQIND_WAVE_HWREGS_OFFSET 0x00000100 -#define SQIND_WAVE_HWREGS_SIZE 0x00000100 -#define SQIND_WAVE_SGPRS_OFFSET 0x00000200 -#define SQIND_WAVE_SGPRS_SIZE 0x00000200 -#define SQIND_WAVE_VGPRS_OFFSET 0x00000400 -#define SQIND_WAVE_VGPRS_SIZE 0x00000400 - -/* - * SQ_GFXDEC value - */ - -#define SQ_GFXDEC_BEGIN 0x0000a000 -#define SQ_GFXDEC_END 0x0000c000 -#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a - -/* - * SQDEC value - */ - -#define SQDEC_BEGIN 0x00002300 -#define SQDEC_END 0x000023ff - -/* - * SQPERFSDEC value - */ - -#define SQPERFSDEC_BEGIN 0x0000d9c0 -#define SQPERFSDEC_END 0x0000da40 - -/* - * SQPERFDDEC value - */ - -#define SQPERFDDEC_BEGIN 0x0000d1c0 -#define SQPERFDDEC_END 0x0000d240 - -/* - * SQGFXUDEC value - */ - -#define SQGFXUDEC_BEGIN 0x0000c330 -#define SQGFXUDEC_END 0x0000c380 - -/* - * SQPWRDEC value - */ - -#define SQPWRDEC_BEGIN 0x0000f08c -#define SQPWRDEC_END 0x0000f094 - -/* - * SQ_DISPATCHER value - */ - -#define SQ_DISPATCHER_GFX_MIN 0x00000010 -#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 - -/* - * SQ_MAX value - */ - -#define SQ_MAX_PGM_SGPRS 0x00000068 -#define SQ_MAX_PGM_VGPRS 0x00000100 - -/* - * SQ_EXCP_BITS value - */ - -#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 -#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 -#define SQ_EX_MODE_EXCP_INVALID 0x00000000 -#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 -#define SQ_EX_MODE_EXCP_DIV0 0x00000002 -#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 -#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 -#define SQ_EX_MODE_EXCP_INEXACT 0x00000005 -#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 -#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 -#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 - -/* - * SQ_EXCP_HI_BITS value - */ - -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 -#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 - -/* - * HW_INSERTED_INST_ID value - */ - -#define INST_ID_PRIV_START 0x80000000 -#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 -#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 -#define INST_ID_HW_TRAP 0xfffffff2 -#define INST_ID_KILL_SEQ 0xfffffff3 -#define INST_ID_SPI_WREXEC 0xfffffff4 -#define INST_ID_HW_TRAP_GET_TBA 0xfffffff5 -#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe - -/* - * SIMM16_WAITCNT_PARTITIONS value - */ - -#define SIMM16_WAITCNT_EXP_CNT_START 0x00000000 -#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 -#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000004 -#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000006 -#define SIMM16_WAITCNT_VM_CNT_START 0x0000000a -#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000006 -#define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000 -#define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001 -#define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001 -#define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001 -#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002 -#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003 -#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000006 -#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001 -#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000007 -#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001 -#define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000008 -#define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003 -#define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000b -#define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000005 - -/* - * SIMM16_WAIT_EVENT_PARTITIONS value - */ - -#define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000 -#define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001 - -/* - * SQ_WAVE_IB_DEP_COUNTER_SIZES value - */ - -#define SQ_WAVE_IB_DEP_SA_SDST_SIZE 0x00000004 -#define SQ_WAVE_IB_DEP_SA_EXEC_SIZE 0x00000002 -#define SQ_WAVE_IB_DEP_SA_M0_SIZE 0x00000001 -#define SQ_WAVE_IB_DEP_VM_VSRC_SIZE 0x00000004 -#define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE 0x00000001 -#define SQ_WAVE_IB_DEP_VA_SSRC_SIZE 0x00000003 -#define SQ_WAVE_IB_DEP_VA_SDST_SIZE 0x00000004 -#define SQ_WAVE_IB_DEP_VA_VCC_SIZE 0x00000003 -#define SQ_WAVE_IB_DEP_VA_EXEC_SIZE 0x00000002 -#define SQ_WAVE_IB_DEP_VA_VDST_SIZE 0x00000005 -#define SQ_WAVE_IB_DEP_LDS_DIR_SIZE 0x00000003 - -/* - * SQ_EDC_FUE_CNTL_BITS value - */ - -#define SQ_EDC_FUE_CNTL_SIMD0 0x00000000 -#define SQ_EDC_FUE_CNTL_SIMD1 0x00000001 -#define SQ_EDC_FUE_CNTL_SIMD2 0x00000002 -#define SQ_EDC_FUE_CNTL_SIMD3 0x00000003 -#define SQ_EDC_FUE_CNTL_SQ 0x00000004 -#define SQ_EDC_FUE_CNTL_LDS 0x00000005 -#define SQ_EDC_FUE_CNTL_TD 0x00000006 -#define SQ_EDC_FUE_CNTL_TA 0x00000007 -#define SQ_EDC_FUE_CNTL_TCP 0x00000008 - -/******************************************************* - * COMP Enums - *******************************************************/ - -/* - * CSCNTL_TYPE enum - */ - -typedef enum CSCNTL_TYPE { -CSCNTL_TYPE_TG = 0x00000000, -CSCNTL_TYPE_STATE = 0x00000001, -CSCNTL_TYPE_EVENT = 0x00000002, -CSCNTL_TYPE_PRIVATE = 0x00000003, -} CSCNTL_TYPE; - -/* - * CSDATA_TYPE enum - */ - -typedef enum CSDATA_TYPE { -CSDATA_TYPE_TG = 0x00000000, -CSDATA_TYPE_STATE = 0x00000001, -CSDATA_TYPE_EVENT = 0x00000002, -CSDATA_TYPE_PRIVATE = 0x00000003, -} CSDATA_TYPE; - -/* - * CSDATA_TYPE_WIDTH value - */ - -#define CSDATA_TYPE_WIDTH 0x00000002 - -/* - * CSDATA_ADDR_WIDTH value - */ - -#define CSDATA_ADDR_WIDTH 0x00000007 - -/* - * CSDATA_DATA_WIDTH value - */ - -#define CSDATA_DATA_WIDTH 0x00000020 - -/* - * CSCNTL_TYPE_WIDTH value - */ - -#define CSCNTL_TYPE_WIDTH 0x00000002 - -/* - * CSCNTL_ADDR_WIDTH value - */ - -#define CSCNTL_ADDR_WIDTH 0x00000007 - -/* - * CSCNTL_DATA_WIDTH value - */ - -#define CSCNTL_DATA_WIDTH 0x00000020 - -/******************************************************* - * GE Enums - *******************************************************/ - -/* - * GE1_PERFCOUNT_SELECT enum - */ - -typedef enum GE1_PERFCOUNT_SELECT { -ge1_assembler_busy = 0x00000000, -ge1_assembler_stalled = 0x00000001, -ge1_dma_busy = 0x00000002, -ge1_dma_lat_bin_0 = 0x00000003, -ge1_dma_lat_bin_1 = 0x00000004, -ge1_dma_lat_bin_2 = 0x00000005, -ge1_dma_lat_bin_3 = 0x00000006, -ge1_dma_lat_bin_4 = 0x00000007, -ge1_dma_lat_bin_5 = 0x00000008, -ge1_dma_lat_bin_6 = 0x00000009, -ge1_dma_lat_bin_7 = 0x0000000a, -ge1_dma_return_cl0 = 0x0000000b, -ge1_dma_return_cl1 = 0x0000000c, -ge1_dma_utcl1_consecutive_retry_event = 0x0000000d, -ge1_dma_utcl1_request_event = 0x0000000e, -ge1_dma_utcl1_retry_event = 0x0000000f, -ge1_dma_utcl1_stall_event = 0x00000010, -ge1_dma_utcl1_stall_utcl2_event = 0x00000011, -ge1_dma_utcl1_translation_hit_event = 0x00000012, -ge1_dma_utcl1_translation_miss_event = 0x00000013, -ge1_assembler_dma_starved = 0x00000014, -ge1_rbiu_di_fifo_stalled_p0 = 0x00000015, -ge1_rbiu_di_fifo_starved_p0 = 0x00000016, -ge1_rbiu_dr_fifo_stalled_p0 = 0x00000017, -ge1_rbiu_dr_fifo_starved_p0 = 0x00000018, -ge1_sclk_reg_vld = 0x00000019, -ge1_stat_busy = 0x0000001a, -ge1_stat_no_dma_busy = 0x0000001b, -ge1_pipe0_to_pipe1 = 0x0000001c, -ge1_pipe1_to_pipe0 = 0x0000001d, -ge1_dma_return_size_cl0 = 0x0000001e, -ge1_dma_return_size_cl1 = 0x0000001f, -ge1_small_draws_one_instance = 0x00000020, -ge1_sclk_input_vld = 0x00000021, -ge1_prim_group_limit_hit = 0x00000022, -ge1_unopt_multi_instance_draws = 0x00000023, -ge1_rbiu_di_fifo_stalled_p1 = 0x00000024, -ge1_rbiu_di_fifo_starved_p1 = 0x00000025, -ge1_rbiu_dr_fifo_stalled_p1 = 0x00000026, -ge1_rbiu_dr_fifo_starved_p1 = 0x00000027, -} GE1_PERFCOUNT_SELECT; - -/* - * GE2_DIST_PERFCOUNT_SELECT enum - */ - -typedef enum GE2_DIST_PERFCOUNT_SELECT { -ge_dist_hs_done = 0x00000000, -ge_dist_hs_done_latency_se0 = 0x00000001, -ge_dist_hs_done_latency_se1 = 0x00000002, -ge_dist_hs_done_latency_se2 = 0x00000003, -ge_dist_hs_done_latency_se3 = 0x00000004, -ge_dist_hs_done_latency_se4 = 0x00000005, -ge_dist_hs_done_latency_se5 = 0x00000006, -ge_dist_hs_done_latency_se6 = 0x00000007, -ge_dist_hs_done_latency_se7 = 0x00000008, -ge_dist_inside_tf_bin_0 = 0x00000009, -ge_dist_inside_tf_bin_1 = 0x0000000a, -ge_dist_inside_tf_bin_2 = 0x0000000b, -ge_dist_inside_tf_bin_3 = 0x0000000c, -ge_dist_inside_tf_bin_4 = 0x0000000d, -ge_dist_inside_tf_bin_5 = 0x0000000e, -ge_dist_inside_tf_bin_6 = 0x0000000f, -ge_dist_inside_tf_bin_7 = 0x00000010, -ge_dist_inside_tf_bin_8 = 0x00000011, -ge_dist_null_patch = 0x00000012, -ge_dist_sclk_core_vld = 0x00000013, -ge_dist_sclk_wd_te11_vld = 0x00000014, -ge_dist_tfreq_lat_bin_0 = 0x00000015, -ge_dist_tfreq_lat_bin_1 = 0x00000016, -ge_dist_tfreq_lat_bin_2 = 0x00000017, -ge_dist_tfreq_lat_bin_3 = 0x00000018, -ge_dist_tfreq_lat_bin_4 = 0x00000019, -ge_dist_tfreq_lat_bin_5 = 0x0000001a, -ge_dist_tfreq_lat_bin_6 = 0x0000001b, -ge_dist_tfreq_lat_bin_7 = 0x0000001c, -ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d, -ge_dist_tfreq_utcl1_request_event = 0x0000001e, -ge_dist_tfreq_utcl1_retry_event = 0x0000001f, -ge_dist_tfreq_utcl1_stall_event = 0x00000020, -ge_dist_tfreq_utcl1_stall_utcl2_event = 0x00000021, -ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022, -ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023, -ge_dist_vs_pc_stall = 0x00000024, -ge_dist_pc_feorder_fifo_full = 0x00000025, -ge_dist_pc_ge_manager_busy = 0x00000026, -ge_dist_pc_req_stall_se0 = 0x00000027, -ge_dist_pc_req_stall_se1 = 0x00000028, -ge_dist_pc_req_stall_se2 = 0x00000029, -ge_dist_pc_req_stall_se3 = 0x0000002a, -ge_dist_pc_req_stall_se4 = 0x0000002b, -ge_dist_pc_req_stall_se5 = 0x0000002c, -ge_dist_pc_req_stall_se6 = 0x0000002d, -ge_dist_pc_req_stall_se7 = 0x0000002e, -ge_dist_pc_space_zero = 0x0000002f, -ge_dist_sclk_input_vld = 0x00000030, -ge_dist_reserved = 0x00000031, -ge_dist_wd_te11_busy = 0x00000032, -ge_dist_te11_starved = 0x00000033, -ge_dist_switch_mode_stall = 0x00000034, -ge_all_tf_eq = 0x00000035, -ge_all_tf2 = 0x00000036, -ge_all_tf3 = 0x00000037, -ge_all_tf4 = 0x00000038, -ge_all_tf5 = 0x00000039, -ge_all_tf6 = 0x0000003a, -ge_se0_te11_starved_on_hs_done = 0x0000003b, -ge_se1_te11_starved_on_hs_done = 0x0000003c, -ge_se2_te11_starved_on_hs_done = 0x0000003d, -ge_se3_te11_starved_on_hs_done = 0x0000003e, -ge_se4_te11_starved_on_hs_done = 0x0000003f, -ge_se5_te11_starved_on_hs_done = 0x00000040, -ge_se6_te11_starved_on_hs_done = 0x00000041, -ge_se7_te11_starved_on_hs_done = 0x00000042, -ge_dist_op_fifo_full_starve = 0x00000043, -ge_dist_hs_done_se0 = 0x00000044, -ge_dist_hs_done_se1 = 0x00000045, -ge_dist_hs_done_se2 = 0x00000046, -ge_dist_hs_done_se3 = 0x00000047, -ge_dist_hs_done_se4 = 0x00000048, -ge_dist_hs_done_se5 = 0x00000049, -ge_dist_hs_done_se6 = 0x0000004a, -ge_dist_hs_done_se7 = 0x0000004b, -ge_dist_hs_done_latency = 0x0000004c, -ge_dist_distributer_busy = 0x0000004d, -ge_tf_ret_data_stalling_hs_done = 0x0000004e, -ge_num_of_no_dist_patches = 0x0000004f, -ge_num_of_donut_dist_patches = 0x00000050, -ge_num_of_patch_dist_patches = 0x00000051, -ge_num_of_se_switches_due_to_patch_accum = 0x00000052, -ge_num_of_se_switches_due_to_donut = 0x00000053, -ge_num_of_se_switches_due_to_trap = 0x00000054, -ge_num_of_hs_alloc_events = 0x00000055, -ge_agm_gcr_req = 0x00000056, -ge_agm_gcr_tag_stall = 0x00000057, -ge_agm_gcr_crd_stall = 0x00000058, -ge_agm_gcr_stall = 0x00000059, -ge_agm_gcr_latency = 0x0000005a, -ge_distclk_vld = 0x0000005b, -} GE2_DIST_PERFCOUNT_SELECT; - -/* - * GE2_SE_PERFCOUNT_SELECT enum - */ - -typedef enum GE2_SE_PERFCOUNT_SELECT { -ge_se_ds_prims = 0x00000000, -ge_se_es_thread_groups = 0x00000001, -ge_se_esvert_stalled_gsprim = 0x00000002, -ge_se_hs_tfm_stall = 0x00000003, -ge_se_hs_tgs_active_high_water_mark = 0x00000004, -ge_se_hs_thread_groups = 0x00000005, -ge_se_reused_es_indices = 0x00000006, -ge_se_sclk_ngg_vld = 0x00000007, -ge_se_sclk_te11_vld = 0x00000008, -ge_se_spi_esvert_eov = 0x00000009, -ge_se_spi_esvert_stalled = 0x0000000a, -ge_se_spi_esvert_starved_busy = 0x0000000b, -ge_se_spi_esvert_valid = 0x0000000c, -ge_se_spi_gsprim_cont = 0x0000000d, -ge_se_spi_gsprim_eov = 0x0000000e, -ge_se_spi_gsprim_stalled = 0x0000000f, -ge_se_spi_gsprim_starved_busy = 0x00000010, -ge_se_spi_gsprim_valid = 0x00000011, -ge_se_spi_gssubgrp_is_event = 0x00000012, -ge_se_spi_gssubgrp_send = 0x00000013, -ge_se_spi_hsvert_eov = 0x00000014, -ge_se_spi_hsvert_stalled = 0x00000015, -ge_se_spi_hsvert_starved_busy = 0x00000016, -ge_se_spi_hsvert_valid = 0x00000017, -ge_se_spi_hswave_is_event = 0x00000018, -ge_se_spi_hswave_send = 0x00000019, -ge_se_spi_lsvert_eov = 0x0000001a, -ge_se_spi_lsvert_stalled = 0x0000001b, -ge_se_spi_lsvert_starved_busy = 0x0000001c, -ge_se_spi_lsvert_valid = 0x0000001d, -ge_se_spi_hsvert_fifo_full_stall = 0x0000001e, -ge_se_spi_tgrp_fifo_stall = 0x0000001f, -ge_spi_hsgrp_spi_stall = 0x00000020, -ge_se_spi_gssubgrp_event_window_active = 0x00000021, -ge_se_hs_input_stall = 0x00000022, -ge_se_sending_vert_or_prim = 0x00000023, -ge_se_sclk_input_vld = 0x00000024, -ge_spi_lswave_fifo_full_stall = 0x00000025, -ge_spi_hswave_fifo_full_stall = 0x00000026, -ge_hs_tif_stall = 0x00000027, -ge_csb_spi_bp = 0x00000028, -ge_ngg_starving_for_pc_grant = 0x00000029, -ge_pa0_csb_eop = 0x0000002a, -ge_pa1_csb_eop = 0x0000002b, -ge_ngg_starved_idle = 0x0000002c, -ge_gsprim_send = 0x0000002d, -ge_esvert_send = 0x0000002e, -ge_ngg_starved_after_work = 0x0000002f, -ge_ngg_subgrp_fifo_stall = 0x00000030, -ge_ngg_ord_id_req_stall = 0x00000031, -ge_ngg_indx_bus_stall = 0x00000032, -ge_hs_stall_tfmm_fifo_full = 0x00000033, -ge_gs_issue_rtr_stalled = 0x00000034, -ge_gsprim_stalled_esvert = 0x00000035, -ge_gsthread_stalled = 0x00000036, -ge_te11_stall_prim_funnel = 0x00000037, -ge_te11_stall_vert_funnel = 0x00000038, -ge_ngg_attr_grp_alloc = 0x00000039, -ge_ngg_attr_discard_alloc = 0x0000003a, -ge_ngg_pc_space_not_avail = 0x0000003b, -ge_ngg_agm_req_stall = 0x0000003c, -ge_ngg_spi_esvert_partial_eov = 0x0000003d, -ge_ngg_spi_gsprim_partial_eov = 0x0000003e, -ge_spi_gsgrp_valid = 0x0000003f, -ge_ngg_attr_grp_latency = 0x00000040, -ge_ngg_reuse_prim_limit_hit = 0x00000041, -ge_ngg_reuse_vert_limit_hit = 0x00000042, -ge_te11_con_stall = 0x00000043, -ge_te11_compactor_starved = 0x00000044, -ge_ngg_stall_tess_off_tess_on = 0x00000045, -ge_ngg_stall_tess_on_tess_off = 0x00000046, -} GE2_SE_PERFCOUNT_SELECT; - -/* - * VGT_DETECT_ONE enum - */ - -typedef enum VGT_DETECT_ONE { -ENABLE_TF1_OPT = 0x00000000, -DISABLE_TF1_OPT = 0x00000001, -} VGT_DETECT_ONE; - -/* - * VGT_DETECT_ZERO enum - */ - -typedef enum VGT_DETECT_ZERO { -ENABLE_TF0_OPT = 0x00000000, -DISABLE_TF0_OPT = 0x00000001, -} VGT_DETECT_ZERO; - -/* - * VGT_DIST_MODE enum - */ - -typedef enum VGT_DIST_MODE { -NO_DIST = 0x00000000, -PATCHES = 0x00000001, -DONUTS = 0x00000002, -TRAPEZOIDS = 0x00000003, -} VGT_DIST_MODE; - -/* - * VGT_DI_INDEX_SIZE enum - */ - -typedef enum VGT_DI_INDEX_SIZE { -DI_INDEX_SIZE_16_BIT = 0x00000000, -DI_INDEX_SIZE_32_BIT = 0x00000001, -DI_INDEX_SIZE_8_BIT = 0x00000002, -} VGT_DI_INDEX_SIZE; - -/* - * VGT_DI_MAJOR_MODE_SELECT enum - */ - -typedef enum VGT_DI_MAJOR_MODE_SELECT { -DI_MAJOR_MODE_0 = 0x00000000, -DI_MAJOR_MODE_1 = 0x00000001, -} VGT_DI_MAJOR_MODE_SELECT; - -/* - * VGT_DI_PRIM_TYPE enum - */ - -typedef enum VGT_DI_PRIM_TYPE { -DI_PT_NONE = 0x00000000, -DI_PT_POINTLIST = 0x00000001, -DI_PT_LINELIST = 0x00000002, -DI_PT_LINESTRIP = 0x00000003, -DI_PT_TRILIST = 0x00000004, -DI_PT_TRIFAN = 0x00000005, -DI_PT_TRISTRIP = 0x00000006, -DI_PT_2D_RECTANGLE = 0x00000007, -DI_PT_UNUSED_1 = 0x00000008, -DI_PT_PATCH = 0x00000009, -DI_PT_LINELIST_ADJ = 0x0000000a, -DI_PT_LINESTRIP_ADJ = 0x0000000b, -DI_PT_TRILIST_ADJ = 0x0000000c, -DI_PT_TRISTRIP_ADJ = 0x0000000d, -DI_PT_UNUSED_3 = 0x0000000e, -DI_PT_UNUSED_4 = 0x0000000f, -DI_PT_UNUSED_5 = 0x00000010, -DI_PT_RECTLIST = 0x00000011, -DI_PT_LINELOOP = 0x00000012, -DI_PT_QUADLIST = 0x00000013, -DI_PT_QUADSTRIP = 0x00000014, -DI_PT_POLYGON = 0x00000015, -} VGT_DI_PRIM_TYPE; - -/* - * VGT_DI_SOURCE_SELECT enum - */ - -typedef enum VGT_DI_SOURCE_SELECT { -DI_SRC_SEL_DMA = 0x00000000, -DI_SRC_SEL_IMMEDIATE = 0x00000001, -DI_SRC_SEL_AUTO_INDEX = 0x00000002, -DI_SRC_SEL_RESERVED = 0x00000003, -} VGT_DI_SOURCE_SELECT; - -/* - * VGT_DMA_BUF_TYPE enum - */ - -typedef enum VGT_DMA_BUF_TYPE { -VGT_DMA_BUF_MEM = 0x00000000, -VGT_DMA_BUF_RING = 0x00000001, -VGT_DMA_BUF_SETUP = 0x00000002, -VGT_DMA_PTR_UPDATE = 0x00000003, -} VGT_DMA_BUF_TYPE; - -/* - * VGT_DMA_SWAP_MODE enum - */ - -typedef enum VGT_DMA_SWAP_MODE { -VGT_DMA_SWAP_NONE = 0x00000000, -VGT_DMA_SWAP_16_BIT = 0x00000001, -VGT_DMA_SWAP_32_BIT = 0x00000002, -VGT_DMA_SWAP_WORD = 0x00000003, -} VGT_DMA_SWAP_MODE; - -/* - * VGT_EVENT_TYPE enum - */ - -typedef enum VGT_EVENT_TYPE { -Reserved_0x00 = 0x00000000, -SAMPLE_STREAMOUTSTATS1 = 0x00000001, -SAMPLE_STREAMOUTSTATS2 = 0x00000002, -SAMPLE_STREAMOUTSTATS3 = 0x00000003, -CACHE_FLUSH_TS = 0x00000004, -CONTEXT_DONE = 0x00000005, -CACHE_FLUSH = 0x00000006, -CS_PARTIAL_FLUSH = 0x00000007, -VGT_STREAMOUT_SYNC = 0x00000008, -Reserved_0x09 = 0x00000009, -VGT_STREAMOUT_RESET = 0x0000000a, -END_OF_PIPE_INCR_DE = 0x0000000b, -END_OF_PIPE_IB_END = 0x0000000c, -RST_PIX_CNT = 0x0000000d, -BREAK_BATCH = 0x0000000e, -VS_PARTIAL_FLUSH = 0x0000000f, -PS_PARTIAL_FLUSH = 0x00000010, -FLUSH_HS_OUTPUT = 0x00000011, -FLUSH_DFSM = 0x00000012, -RESET_TO_LOWEST_VGT = 0x00000013, -CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, -WAIT_SYNC = 0x00000015, -CACHE_FLUSH_AND_INV_EVENT = 0x00000016, -PERFCOUNTER_START = 0x00000017, -PERFCOUNTER_STOP = 0x00000018, -PIPELINESTAT_START = 0x00000019, -PIPELINESTAT_STOP = 0x0000001a, -PERFCOUNTER_SAMPLE = 0x0000001b, -FLUSH_ES_OUTPUT = 0x0000001c, -BIN_CONF_OVERRIDE_CHECK = 0x0000001d, -SAMPLE_PIPELINESTAT = 0x0000001e, -SO_VGTSTREAMOUT_FLUSH = 0x0000001f, -SAMPLE_STREAMOUTSTATS = 0x00000020, -RESET_VTX_CNT = 0x00000021, -BLOCK_CONTEXT_DONE = 0x00000022, -CS_CONTEXT_DONE = 0x00000023, -VGT_FLUSH = 0x00000024, -TGID_ROLLOVER = 0x00000025, -SQ_NON_EVENT = 0x00000026, -SC_SEND_DB_VPZ = 0x00000027, -BOTTOM_OF_PIPE_TS = 0x00000028, -FLUSH_SX_TS = 0x00000029, -DB_CACHE_FLUSH_AND_INV = 0x0000002a, -FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, -FLUSH_AND_INV_DB_META = 0x0000002c, -FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, -FLUSH_AND_INV_CB_META = 0x0000002e, -CS_DONE = 0x0000002f, -PS_DONE = 0x00000030, -FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, -SX_CB_RAT_ACK_REQUEST = 0x00000032, -THREAD_TRACE_START = 0x00000033, -THREAD_TRACE_STOP = 0x00000034, -THREAD_TRACE_MARKER = 0x00000035, -THREAD_TRACE_DRAW = 0x00000036, -THREAD_TRACE_FINISH = 0x00000037, -PIXEL_PIPE_STAT_CONTROL = 0x00000038, -PIXEL_PIPE_STAT_DUMP = 0x00000039, -PIXEL_PIPE_STAT_RESET = 0x0000003a, -CONTEXT_SUSPEND = 0x0000003b, -OFFCHIP_HS_DEALLOC = 0x0000003c, -ENABLE_NGG_PIPELINE = 0x0000003d, -ENABLE_LEGACY_PIPELINE = 0x0000003e, -DRAW_DONE = 0x0000003f, -} VGT_EVENT_TYPE; - -/* - * VGT_GROUP_CONV_SEL enum - */ - -typedef enum VGT_GROUP_CONV_SEL { -VGT_GRP_INDEX_16 = 0x00000000, -VGT_GRP_INDEX_32 = 0x00000001, -VGT_GRP_UINT_16 = 0x00000002, -VGT_GRP_UINT_32 = 0x00000003, -VGT_GRP_SINT_16 = 0x00000004, -VGT_GRP_SINT_32 = 0x00000005, -VGT_GRP_FLOAT_32 = 0x00000006, -VGT_GRP_AUTO_PRIM = 0x00000007, -VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, -} VGT_GROUP_CONV_SEL; - -/* - * VGT_GS_MODE_TYPE enum - */ - -typedef enum VGT_GS_MODE_TYPE { -GS_OFF = 0x00000000, -GS_SCENARIO_A = 0x00000001, -GS_SCENARIO_B = 0x00000002, -GS_SCENARIO_G = 0x00000003, -GS_SCENARIO_C = 0x00000004, -SPRITE_EN = 0x00000005, -} VGT_GS_MODE_TYPE; - -/* - * VGT_GS_OUTPRIM_TYPE enum - */ - -typedef enum VGT_GS_OUTPRIM_TYPE { -POINTLIST = 0x00000000, -LINESTRIP = 0x00000001, -TRISTRIP = 0x00000002, -RECT_2D = 0x00000003, -RECTLIST = 0x00000004, -} VGT_GS_OUTPRIM_TYPE; - -/* - * VGT_INDEX_TYPE_MODE enum - */ - -typedef enum VGT_INDEX_TYPE_MODE { -VGT_INDEX_16 = 0x00000000, -VGT_INDEX_32 = 0x00000001, -VGT_INDEX_8 = 0x00000002, -} VGT_INDEX_TYPE_MODE; - -/* - * VGT_OUTPATH_SELECT enum - */ - -typedef enum VGT_OUTPATH_SELECT { -VGT_OUTPATH_VTX_REUSE = 0x00000000, -VGT_OUTPATH_GS_BLOCK = 0x00000001, -VGT_OUTPATH_HS_BLOCK = 0x00000002, -VGT_OUTPATH_PRIM_GEN = 0x00000003, -VGT_OUTPATH_TE_PRIM_GEN = 0x00000004, -VGT_OUTPATH_TE_GS_BLOCK = 0x00000005, -VGT_OUTPATH_TE_OUTPUT = 0x00000006, -} VGT_OUTPATH_SELECT; - -/* - * VGT_OUT_PRIM_TYPE enum - */ - -typedef enum VGT_OUT_PRIM_TYPE { -VGT_OUT_POINT = 0x00000000, -VGT_OUT_LINE = 0x00000001, -VGT_OUT_TRI = 0x00000002, -VGT_OUT_RECT_V0 = 0x00000003, -VGT_OUT_RECT_V1 = 0x00000004, -VGT_OUT_RECT_V2 = 0x00000005, -VGT_OUT_RECT_V3 = 0x00000006, -VGT_OUT_2D_RECT = 0x00000007, -VGT_TE_QUAD = 0x00000008, -VGT_TE_PRIM_INDEX_LINE = 0x00000009, -VGT_TE_PRIM_INDEX_TRI = 0x0000000a, -VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, -VGT_OUT_LINE_ADJ = 0x0000000c, -VGT_OUT_TRI_ADJ = 0x0000000d, -VGT_OUT_PATCH = 0x0000000e, -} VGT_OUT_PRIM_TYPE; - -/* - * VGT_RDREQ_POLICY enum - */ - -typedef enum VGT_RDREQ_POLICY { -VGT_POLICY_LRU = 0x00000000, -VGT_POLICY_STREAM = 0x00000001, -VGT_POLICY_BYPASS = 0x00000002, -} VGT_RDREQ_POLICY; - -/* - * VGT_STAGES_ES_EN enum - */ - -typedef enum VGT_STAGES_ES_EN { -ES_STAGE_OFF = 0x00000000, -ES_STAGE_DS = 0x00000001, -ES_STAGE_REAL = 0x00000002, -RESERVED_ES = 0x00000003, -} VGT_STAGES_ES_EN; - -/* - * VGT_STAGES_GS_EN enum - */ - -typedef enum VGT_STAGES_GS_EN { -GS_STAGE_OFF = 0x00000000, -GS_STAGE_ON = 0x00000001, -} VGT_STAGES_GS_EN; - -/* - * VGT_STAGES_HS_EN enum - */ - -typedef enum VGT_STAGES_HS_EN { -HS_STAGE_OFF = 0x00000000, -HS_STAGE_ON = 0x00000001, -} VGT_STAGES_HS_EN; - -/* - * VGT_STAGES_LS_EN enum - */ - -typedef enum VGT_STAGES_LS_EN { -LS_STAGE_OFF = 0x00000000, -LS_STAGE_ON = 0x00000001, -CS_STAGE_ON = 0x00000002, -RESERVED_LS = 0x00000003, -} VGT_STAGES_LS_EN; - -/* - * VGT_STAGES_VS_EN enum - */ - -typedef enum VGT_STAGES_VS_EN { -VS_STAGE_REAL = 0x00000000, -VS_STAGE_DS = 0x00000001, -VS_STAGE_COPY_SHADER = 0x00000002, -RESERVED_VS = 0x00000003, -} VGT_STAGES_VS_EN; - -/* - * VGT_TESS_PARTITION enum - */ - -typedef enum VGT_TESS_PARTITION { -PART_INTEGER = 0x00000000, -PART_POW2 = 0x00000001, -PART_FRAC_ODD = 0x00000002, -PART_FRAC_EVEN = 0x00000003, -} VGT_TESS_PARTITION; - -/* - * VGT_TESS_TOPOLOGY enum - */ - -typedef enum VGT_TESS_TOPOLOGY { -OUTPUT_POINT = 0x00000000, -OUTPUT_LINE = 0x00000001, -OUTPUT_TRIANGLE_CW = 0x00000002, -OUTPUT_TRIANGLE_CCW = 0x00000003, -} VGT_TESS_TOPOLOGY; - -/* - * VGT_TESS_TYPE enum - */ - -typedef enum VGT_TESS_TYPE { -TESS_ISOLINE = 0x00000000, -TESS_TRIANGLE = 0x00000001, -TESS_QUAD = 0x00000002, -} VGT_TESS_TYPE; - -/* - * WD_IA_DRAW_REG_XFER enum - */ - -typedef enum WD_IA_DRAW_REG_XFER { -WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, -WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002, -WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003, -WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 0x00000004, -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 0x00000005, -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 0x00000006, -WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 0x00000007, -WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 0x00000008, -} WD_IA_DRAW_REG_XFER; - -/* - * WD_IA_DRAW_SOURCE enum - */ - -typedef enum WD_IA_DRAW_SOURCE { -WD_IA_DRAW_SOURCE_DMA = 0x00000000, -WD_IA_DRAW_SOURCE_IMMD = 0x00000001, -WD_IA_DRAW_SOURCE_AUTO = 0x00000002, -WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, -} WD_IA_DRAW_SOURCE; - -/* - * WD_IA_DRAW_TYPE enum - */ - -typedef enum WD_IA_DRAW_TYPE { -WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, -WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, -WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, -WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, -WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, -WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, -WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, -WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, -} WD_IA_DRAW_TYPE; - -/* - * GS_THREADID_SIZE value - */ - -#define GSTHREADID_SIZE 0x00000002 - -/******************************************************* - * GB Enums - *******************************************************/ - -/* - * GB_EDC_DED_MODE enum - */ - -typedef enum GB_EDC_DED_MODE { -GB_EDC_DED_MODE_LOG = 0x00000000, -GB_EDC_DED_MODE_HALT = 0x00000001, -GB_EDC_DED_MODE_INT_HALT = 0x00000002, -} GB_EDC_DED_MODE; - -/* - * VALUE_GB_TILING_CONFIG_TABLE_SIZE value - */ - -#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 - -/* - * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value - */ - -#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010 - -/******************************************************* - * GLX Enums - *******************************************************/ - -/* - * CHA_PERF_SEL enum - */ - -typedef enum CHA_PERF_SEL { -CHA_PERF_SEL_BUSY = 0x00000000, -CHA_PERF_SEL_STALL_CHC0 = 0x00000001, -CHA_PERF_SEL_STALL_CHC1 = 0x00000002, -CHA_PERF_SEL_STALL_CHC2 = 0x00000003, -CHA_PERF_SEL_STALL_CHC3 = 0x00000004, -CHA_PERF_SEL_STALL_CHC4 = 0x00000005, -CHA_PERF_SEL_STALL_CHC5 = 0x00000006, -CHA_PERF_SEL_REQUEST_CHC0 = 0x00000007, -CHA_PERF_SEL_REQUEST_CHC1 = 0x00000008, -CHA_PERF_SEL_REQUEST_CHC2 = 0x00000009, -CHA_PERF_SEL_REQUEST_CHC3 = 0x0000000a, -CHA_PERF_SEL_REQUEST_CHC4 = 0x0000000b, -CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x0000000c, -CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000d, -CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000e, -CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000f, -CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 0x00000010, -CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x00000011, -CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x00000012, -CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x00000013, -CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000014, -CHA_PERF_SEL_IO_32B_WDS_CHC4 = 0x00000015, -CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000016, -CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000017, -CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000018, -CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000019, -CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 0x0000001a, -CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x0000001b, -CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x0000001c, -CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x0000001d, -CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x0000001e, -CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 0x0000001f, -CHA_PERF_SEL_ARB_REQUESTS = 0x00000020, -CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000021, -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x00000022, -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x00000023, -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x00000024, -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x00000025, -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 0x00000026, -CHA_PERF_SEL_CYCLE = 0x00000027, -} CHA_PERF_SEL; - -/* - * CHCG_PERF_SEL enum - */ - -typedef enum CHCG_PERF_SEL { -CHCG_PERF_SEL_CYCLE = 0x00000000, -CHCG_PERF_SEL_BUSY = 0x00000001, -CHCG_PERF_SEL_STARVE = 0x00000002, -CHCG_PERF_SEL_ARB_RET_LEVEL = 0x00000003, -CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, -CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, -CHCG_PERF_SEL_REQ = 0x00000006, -CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, -CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, -CHCG_PERF_SEL_REQ_NOP_ACK = 0x00000009, -CHCG_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, -CHCG_PERF_SEL_REQ_READ = 0x0000000b, -CHCG_PERF_SEL_REQ_READ_128B = 0x0000000c, -CHCG_PERF_SEL_REQ_READ_32B = 0x0000000d, -CHCG_PERF_SEL_REQ_READ_64B = 0x0000000e, -CHCG_PERF_SEL_REQ_WRITE = 0x0000000f, -CHCG_PERF_SEL_REQ_WRITE_32B = 0x00000010, -CHCG_PERF_SEL_REQ_WRITE_64B = 0x00000011, -CHCG_PERF_SEL_STALL_GUS_GL1 = 0x00000012, -CHCG_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, -CHCG_PERF_SEL_REQ_CLIENT0 = 0x00000014, -CHCG_PERF_SEL_REQ_CLIENT1 = 0x00000015, -CHCG_PERF_SEL_REQ_CLIENT2 = 0x00000016, -CHCG_PERF_SEL_REQ_CLIENT3 = 0x00000017, -CHCG_PERF_SEL_REQ_CLIENT4 = 0x00000018, -CHCG_PERF_SEL_REQ_CLIENT5 = 0x00000019, -CHCG_PERF_SEL_REQ_CLIENT6 = 0x0000001a, -CHCG_PERF_SEL_REQ_CLIENT7 = 0x0000001b, -CHCG_PERF_SEL_REQ_CLIENT8 = 0x0000001c, -CHCG_PERF_SEL_REQ_CLIENT9 = 0x0000001d, -CHCG_PERF_SEL_REQ_CLIENT10 = 0x0000001e, -CHCG_PERF_SEL_REQ_CLIENT11 = 0x0000001f, -CHCG_PERF_SEL_REQ_CLIENT12 = 0x00000020, -CHCG_PERF_SEL_REQ_CLIENT13 = 0x00000021, -CHCG_PERF_SEL_REQ_CLIENT14 = 0x00000022, -CHCG_PERF_SEL_REQ_CLIENT15 = 0x00000023, -CHCG_PERF_SEL_REQ_CLIENT16 = 0x00000024, -CHCG_PERF_SEL_REQ_CLIENT17 = 0x00000025, -CHCG_PERF_SEL_REQ_CLIENT18 = 0x00000026, -CHCG_PERF_SEL_REQ_CLIENT19 = 0x00000027, -CHCG_PERF_SEL_REQ_CLIENT20 = 0x00000028, -CHCG_PERF_SEL_REQ_CLIENT21 = 0x00000029, -CHCG_PERF_SEL_REQ_CLIENT22 = 0x0000002a, -CHCG_PERF_SEL_REQ_CLIENT23 = 0x0000002b, -} CHCG_PERF_SEL; - -/* - * CHC_PERF_SEL enum - */ - -typedef enum CHC_PERF_SEL { -CHC_PERF_SEL_CYCLE = 0x00000000, -CHC_PERF_SEL_BUSY = 0x00000001, -CHC_PERF_SEL_STARVE = 0x00000002, -CHC_PERF_SEL_ARB_RET_LEVEL = 0x00000003, -CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004, -CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005, -CHC_PERF_SEL_REQ = 0x00000006, -CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007, -CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008, -CHC_PERF_SEL_REQ_NOP_ACK = 0x00000009, -CHC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a, -CHC_PERF_SEL_REQ_READ = 0x0000000b, -CHC_PERF_SEL_REQ_READ_128B = 0x0000000c, -CHC_PERF_SEL_REQ_READ_32B = 0x0000000d, -CHC_PERF_SEL_REQ_READ_64B = 0x0000000e, -CHC_PERF_SEL_REQ_WRITE = 0x0000000f, -CHC_PERF_SEL_REQ_WRITE_32B = 0x00000010, -CHC_PERF_SEL_REQ_WRITE_64B = 0x00000011, -CHC_PERF_SEL_STALL_GL2_GL1 = 0x00000012, -CHC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013, -CHC_PERF_SEL_REQ_CLIENT0 = 0x00000014, -CHC_PERF_SEL_REQ_CLIENT1 = 0x00000015, -CHC_PERF_SEL_REQ_CLIENT2 = 0x00000016, -CHC_PERF_SEL_REQ_CLIENT3 = 0x00000017, -CHC_PERF_SEL_REQ_CLIENT4 = 0x00000018, -CHC_PERF_SEL_REQ_CLIENT5 = 0x00000019, -CHC_PERF_SEL_REQ_CLIENT6 = 0x0000001a, -CHC_PERF_SEL_REQ_CLIENT7 = 0x0000001b, -CHC_PERF_SEL_REQ_CLIENT8 = 0x0000001c, -CHC_PERF_SEL_REQ_CLIENT9 = 0x0000001d, -CHC_PERF_SEL_REQ_CLIENT10 = 0x0000001e, -CHC_PERF_SEL_REQ_CLIENT11 = 0x0000001f, -CHC_PERF_SEL_REQ_CLIENT12 = 0x00000020, -CHC_PERF_SEL_REQ_CLIENT13 = 0x00000021, -CHC_PERF_SEL_REQ_CLIENT14 = 0x00000022, -CHC_PERF_SEL_REQ_CLIENT15 = 0x00000023, -CHC_PERF_SEL_REQ_CLIENT16 = 0x00000024, -CHC_PERF_SEL_REQ_CLIENT17 = 0x00000025, -CHC_PERF_SEL_REQ_CLIENT18 = 0x00000026, -CHC_PERF_SEL_REQ_CLIENT19 = 0x00000027, -CHC_PERF_SEL_REQ_CLIENT20 = 0x00000028, -CHC_PERF_SEL_REQ_CLIENT21 = 0x00000029, -CHC_PERF_SEL_REQ_CLIENT22 = 0x0000002a, -CHC_PERF_SEL_REQ_CLIENT23 = 0x0000002b, -} CHC_PERF_SEL; - -/* - * GL1A_PERF_SEL enum - */ - -typedef enum GL1A_PERF_SEL { -GL1A_PERF_SEL_BUSY = 0x00000000, -GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001, -GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002, -GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003, -GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004, -GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000005, -GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000006, -GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000007, -GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000008, -GL1A_PERF_SEL_WDS_32B_GL1C0 = 0x00000009, -GL1A_PERF_SEL_WDS_32B_GL1C1 = 0x0000000a, -GL1A_PERF_SEL_WDS_32B_GL1C2 = 0x0000000b, -GL1A_PERF_SEL_WDS_32B_GL1C3 = 0x0000000c, -GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 0x0000000d, -GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 0x0000000e, -GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 0x0000000f, -GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 0x00000010, -GL1A_PERF_SEL_ARB_REQUESTS = 0x00000011, -GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012, -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000013, -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000014, -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000015, -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000016, -GL1A_PERF_SEL_CYCLE = 0x00000017, -} GL1A_PERF_SEL; - -/* - * GL1C_PERF_SEL enum - */ - -typedef enum GL1C_PERF_SEL { -GL1C_PERF_SEL_CYCLE = 0x00000000, -GL1C_PERF_SEL_BUSY = 0x00000001, -GL1C_PERF_SEL_STARVE = 0x00000002, -GL1C_PERF_SEL_ARB_RET_LEVEL = 0x00000003, -GL1C_PERF_SEL_GL2_REQ_READ = 0x00000004, -GL1C_PERF_SEL_GL2_REQ_READ_128B = 0x00000005, -GL1C_PERF_SEL_GL2_REQ_READ_32B = 0x00000006, -GL1C_PERF_SEL_GL2_REQ_READ_64B = 0x00000007, -GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000008, -GL1C_PERF_SEL_GL2_REQ_WRITE = 0x00000009, -GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 0x0000000a, -GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 0x0000000b, -GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x0000000c, -GL1C_PERF_SEL_GL2_REQ_PREFETCH = 0x0000000d, -GL1C_PERF_SEL_REQ = 0x0000000e, -GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x0000000f, -GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000010, -GL1C_PERF_SEL_REQ_SHADER_INV = 0x00000011, -GL1C_PERF_SEL_REQ_MISS = 0x00000012, -GL1C_PERF_SEL_REQ_NOP_ACK = 0x00000013, -GL1C_PERF_SEL_REQ_NOP_RTN0 = 0x00000014, -GL1C_PERF_SEL_REQ_READ = 0x00000015, -GL1C_PERF_SEL_REQ_READ_128B = 0x00000016, -GL1C_PERF_SEL_REQ_READ_32B = 0x00000017, -GL1C_PERF_SEL_REQ_READ_64B = 0x00000018, -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 0x00000019, -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 0x0000001a, -GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 0x0000001b, -GL1C_PERF_SEL_REQ_WRITE = 0x0000001c, -GL1C_PERF_SEL_REQ_WRITE_32B = 0x0000001d, -GL1C_PERF_SEL_REQ_WRITE_64B = 0x0000001e, -GL1C_PERF_SEL_STALL_GL2_GL1 = 0x0000001f, -GL1C_PERF_SEL_STALL_LFIFO_FULL = 0x00000020, -GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 0x00000021, -GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 0x00000022, -GL1C_PERF_SEL_STALL_GCR_INV = 0x00000023, -GL1C_PERF_SEL_STALL_VM = 0x00000024, -GL1C_PERF_SEL_REQ_CLIENT0 = 0x00000025, -GL1C_PERF_SEL_REQ_CLIENT1 = 0x00000026, -GL1C_PERF_SEL_REQ_CLIENT2 = 0x00000027, -GL1C_PERF_SEL_REQ_CLIENT3 = 0x00000028, -GL1C_PERF_SEL_REQ_CLIENT4 = 0x00000029, -GL1C_PERF_SEL_REQ_CLIENT5 = 0x0000002a, -GL1C_PERF_SEL_REQ_CLIENT6 = 0x0000002b, -GL1C_PERF_SEL_REQ_CLIENT7 = 0x0000002c, -GL1C_PERF_SEL_REQ_CLIENT8 = 0x0000002d, -GL1C_PERF_SEL_REQ_CLIENT9 = 0x0000002e, -GL1C_PERF_SEL_REQ_CLIENT10 = 0x0000002f, -GL1C_PERF_SEL_REQ_CLIENT11 = 0x00000030, -GL1C_PERF_SEL_REQ_CLIENT12 = 0x00000031, -GL1C_PERF_SEL_REQ_CLIENT13 = 0x00000032, -GL1C_PERF_SEL_REQ_CLIENT14 = 0x00000033, -GL1C_PERF_SEL_REQ_CLIENT15 = 0x00000034, -GL1C_PERF_SEL_REQ_CLIENT16 = 0x00000035, -GL1C_PERF_SEL_REQ_CLIENT17 = 0x00000036, -GL1C_PERF_SEL_REQ_CLIENT18 = 0x00000037, -GL1C_PERF_SEL_REQ_CLIENT19 = 0x00000038, -GL1C_PERF_SEL_REQ_CLIENT20 = 0x00000039, -GL1C_PERF_SEL_REQ_CLIENT21 = 0x0000003a, -GL1C_PERF_SEL_REQ_CLIENT22 = 0x0000003b, -GL1C_PERF_SEL_REQ_CLIENT23 = 0x0000003c, -GL1C_PERF_SEL_REQ_CLIENT24 = 0x0000003d, -GL1C_PERF_SEL_REQ_CLIENT25 = 0x0000003e, -GL1C_PERF_SEL_REQ_CLIENT26 = 0x0000003f, -GL1C_PERF_SEL_REQ_CLIENT27 = 0x00000040, -GL1C_PERF_SEL_UTCL0_REQUEST = 0x00000041, -GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000042, -GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000043, -GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000044, -GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000045, -GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000046, -GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000047, -GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000048, -GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000049, -GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000004a, -GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000004b, -GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000004c, -GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000004d, -GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000004e, -GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000004f, -GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000050, -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000051, -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000052, -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000053, -} GL1C_PERF_SEL; - -/******************************************************* - * GL1H Enums - *******************************************************/ - -/* - * GL1H_REQ_PERF_SEL enum - */ - -typedef enum GL1H_REQ_PERF_SEL { -GL1H_REQ_PERF_SEL_BUSY = 0x00000000, -GL1H_REQ_PERF_SEL_STALL_GL1_0 = 0x00000001, -GL1H_REQ_PERF_SEL_STALL_GL1_1 = 0x00000002, -GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 0x00000003, -GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 0x00000004, -GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 0x00000005, -GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 0x00000006, -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 0x00000007, -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 0x00000008, -GL1H_REQ_PERF_SEL_ARB_REQUESTS = 0x00000009, -GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x0000000a, -GL1H_REQ_PERF_SEL_CYCLE = 0x0000000b, -} GL1H_REQ_PERF_SEL; - -/******************************************************* - * TA Enums - *******************************************************/ - -/* - * TA_PERFCOUNT_SEL enum - */ - -typedef enum TA_PERFCOUNT_SEL { -TA_PERF_SEL_NULL = 0x00000000, -TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001, -TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002, -TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003, -TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004, -TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005, -TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006, -TA_PERF_SEL_gradient_busy = 0x00000007, -TA_PERF_SEL_gradient_fifo_busy = 0x00000008, -TA_PERF_SEL_lod_busy = 0x00000009, -TA_PERF_SEL_lod_fifo_busy = 0x0000000a, -TA_PERF_SEL_addresser_busy = 0x0000000b, -TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, -TA_PERF_SEL_aligner_busy = 0x0000000d, -TA_PERF_SEL_write_path_busy = 0x0000000e, -TA_PERF_SEL_ta_busy = 0x0000000f, -TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010, -TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011, -TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012, -TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013, -TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014, -TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015, -TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016, -TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017, -TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018, -TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019, -TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a, -TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b, -TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c, -TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d, -TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e, -TA_PERF_SEL_total_wavefronts = 0x00000020, -TA_PERF_SEL_gradient_cycles = 0x00000021, -TA_PERF_SEL_walker_cycles = 0x00000022, -TA_PERF_SEL_aligner_cycles = 0x00000023, -TA_PERF_SEL_image_wavefronts = 0x00000024, -TA_PERF_SEL_image_read_wavefronts = 0x00000025, -TA_PERF_SEL_image_store_wavefronts = 0x00000026, -TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, -TA_PERF_SEL_image_sampler_total_cycles = 0x00000028, -TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029, -TA_PERF_SEL_flat_total_cycles = 0x0000002a, -TA_PERF_SEL_bvh_total_cycles = 0x0000002b, -TA_PERF_SEL_buffer_wavefronts = 0x0000002c, -TA_PERF_SEL_buffer_load_wavefronts = 0x0000002d, -TA_PERF_SEL_buffer_store_wavefronts = 0x0000002e, -TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, -TA_PERF_SEL_buffer_total_cycles = 0x00000031, -TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032, -TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033, -TA_PERF_SEL_buffer_has_index_instructions = 0x00000034, -TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035, -TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, -TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, -TA_PERF_SEL_image_sampler_wavefronts = 0x00000038, -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, -TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, -TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, -TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, -TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, -TA_PERF_SEL_color_1_cycle_quads = 0x00000040, -TA_PERF_SEL_color_2_cycle_quads = 0x00000041, -TA_PERF_SEL_color_3_cycle_quads = 0x00000042, -TA_PERF_SEL_mip_1_cycle_quads = 0x00000044, -TA_PERF_SEL_mip_2_cycle_quads = 0x00000045, -TA_PERF_SEL_vol_1_cycle_quads = 0x00000046, -TA_PERF_SEL_vol_2_cycle_quads = 0x00000047, -TA_PERF_SEL_sampler_op_quads = 0x00000048, -TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, -TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, -TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, -TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, -TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, -TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, -TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, -TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, -TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, -TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, -TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, -TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, -TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, -TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, -TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, -TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, -TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, -TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, -TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, -TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, -TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, -TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, -TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, -TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, -TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, -TA_PERF_SEL_store_write_data_input_cycles = 0x00000062, -TA_PERF_SEL_store_write_data_output_cycles = 0x00000063, -TA_PERF_SEL_flat_wavefronts = 0x00000064, -TA_PERF_SEL_flat_load_wavefronts = 0x00000065, -TA_PERF_SEL_flat_store_wavefronts = 0x00000066, -TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, -TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068, -TA_PERF_SEL_register_clk_valid_cycles = 0x00000069, -TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a, -TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b, -TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 0x0000006c, -TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d, -TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e, -TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072, -TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073, -TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074, -TA_PERF_SEL_store_has_x_instructions = 0x00000075, -TA_PERF_SEL_store_has_y_instructions = 0x00000076, -TA_PERF_SEL_store_has_z_instructions = 0x00000077, -TA_PERF_SEL_store_has_w_instructions = 0x00000078, -TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079, -TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a, -TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b, -TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c, -TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d, -TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e, -TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f, -TA_PERF_SEL_in_busy = 0x00000080, -TA_PERF_SEL_in_fifos_busy = 0x00000081, -TA_PERF_SEL_in_cfifo_busy = 0x00000082, -TA_PERF_SEL_in_qfifo_busy = 0x00000083, -TA_PERF_SEL_in_wfifo_busy = 0x00000084, -TA_PERF_SEL_in_rfifo_busy = 0x00000085, -TA_PERF_SEL_bf_busy = 0x00000086, -TA_PERF_SEL_ns_busy = 0x00000087, -TA_PERF_SEL_smp_busy_ns_idle = 0x00000088, -TA_PERF_SEL_smp_idle_ns_busy = 0x00000089, -TA_PERF_SEL_vmemcmd_cycles = 0x00000090, -TA_PERF_SEL_vmemreq_cycles = 0x00000091, -TA_PERF_SEL_in_waiting_on_req_cycles = 0x00000092, -TA_PERF_SEL_in_addr_cycles = 0x00000096, -TA_PERF_SEL_in_data_cycles = 0x00000097, -TA_PERF_SEL_latency_ram_weights_written_cycles = 0x0000009a, -TA_PERF_SEL_latency_ram_ws_required_quads = 0x0000009b, -TA_PERF_SEL_latency_ram_whv_required_quads = 0x0000009c, -TA_PERF_SEL_latency_ram_ws_required_instructions = 0x0000009d, -TA_PERF_SEL_latency_ram_whv_required_instructions = 0x0000009e, -TA_PERF_SEL_latency_ram_ref_required_instructions = 0x0000009f, -TA_PERF_SEL_point_sampled_quads = 0x000000a0, -TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2, -TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3, -TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4, -TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5, -TA_PERF_SEL_num_unlit_nodes_ta_opt = 0x000000ad, -TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae, -TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af, -TA_PERF_SEL_num_of_bvh_valid_first_tri = 0x000000b0, -TA_PERF_SEL_num_of_bvh_valid_second_tri = 0x000000b1, -TA_PERF_SEL_num_of_bvh_valid_third_tri = 0x000000b2, -TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 0x000000b3, -TA_PERF_SEL_num_of_bvh_valid_fp16_box = 0x000000b4, -TA_PERF_SEL_num_of_bvh_valid_fp32_box = 0x000000b5, -TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 0x000000b6, -TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 0x000000b7, -TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 0x000000b8, -TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 0x000000b9, -TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 0x000000ba, -TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 0x000000bb, -TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 0x000000bc, -TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 0x000000bd, -TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 0x000000be, -TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 0x000000bf, -TA_PERF_SEL_image_sampler_1_op_burst = 0x000000c0, -TA_PERF_SEL_image_sampler_2to3_op_burst = 0x000000c1, -TA_PERF_SEL_image_sampler_4to7_op_burst = 0x000000c2, -TA_PERF_SEL_image_sampler_ge8_op_burst = 0x000000c3, -TA_PERF_SEL_image_linked_1_op_burst = 0x000000c4, -TA_PERF_SEL_image_linked_2to3_op_burst = 0x000000c5, -TA_PERF_SEL_image_linked_4to7_op_burst = 0x000000c6, -TA_PERF_SEL_image_linked_ge8_op_burst = 0x000000c7, -TA_PERF_SEL_image_bvh_1_op_burst = 0x000000c8, -TA_PERF_SEL_image_bvh_2to3_op_burst = 0x000000c9, -TA_PERF_SEL_image_bvh_4to7_op_burst = 0x000000ca, -TA_PERF_SEL_image_bvh_ge8_op_burst = 0x000000cb, -TA_PERF_SEL_image_nosampler_1_op_burst = 0x000000cc, -TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd, -TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce, -TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf, -TA_PERF_SEL_buffer_flat_1_op_burst = 0x000000d0, -TA_PERF_SEL_buffer_flat_2to3_op_burst = 0x000000d1, -TA_PERF_SEL_buffer_flat_4to31_op_burst = 0x000000d2, -TA_PERF_SEL_buffer_flat_ge32_op_burst = 0x000000d3, -TA_PERF_SEL_write_1_op_burst = 0x000000d4, -TA_PERF_SEL_write_2to3_op_burst = 0x000000d5, -TA_PERF_SEL_write_4to31_op_burst = 0x000000d6, -TA_PERF_SEL_write_ge32_op_burst = 0x000000d7, -TA_PERF_SEL_ibubble_1_cycle_burst = 0x000000d8, -TA_PERF_SEL_ibubble_2to3_cycle_burst = 0x000000d9, -TA_PERF_SEL_ibubble_4to15_cycle_burst = 0x000000da, -TA_PERF_SEL_ibubble_16to31_cycle_burst = 0x000000db, -TA_PERF_SEL_ibubble_32to63_cycle_burst = 0x000000dc, -TA_PERF_SEL_ibubble_ge64_cycle_burst = 0x000000dd, -TA_PERF_SEL_sampler_clk_valid_cycles = 0x000000e0, -TA_PERF_SEL_nonsampler_clk_valid_cycles = 0x000000e1, -TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2, -TA_PERF_SEL_write_data_clk_valid_cycles = 0x000000e3, -TA_PERF_SEL_gradient_clk_valid_cycles = 0x000000e4, -TA_PERF_SEL_lod_aniso_clk_valid_cycles = 0x000000e5, -TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6, -TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7, -TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8, -TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9, -TA_PERF_SEL_aligner_clk_valid_cycles = 0x000000ea, -TA_PERF_SEL_tcreq_clk_valid_cycles = 0x000000eb, -} TA_PERFCOUNT_SEL; - -/* - * TEX_BC_SWIZZLE enum - */ - -typedef enum TEX_BC_SWIZZLE { -TEX_BC_Swizzle_XYZW = 0x00000000, -TEX_BC_Swizzle_XWYZ = 0x00000001, -TEX_BC_Swizzle_WZYX = 0x00000002, -TEX_BC_Swizzle_WXYZ = 0x00000003, -TEX_BC_Swizzle_ZYXW = 0x00000004, -TEX_BC_Swizzle_YXWZ = 0x00000005, -} TEX_BC_SWIZZLE; - -/* - * TEX_BORDER_COLOR_TYPE enum - */ - -typedef enum TEX_BORDER_COLOR_TYPE { -TEX_BorderColor_TransparentBlack = 0x00000000, -TEX_BorderColor_OpaqueBlack = 0x00000001, -TEX_BorderColor_OpaqueWhite = 0x00000002, -TEX_BorderColor_Register = 0x00000003, -} TEX_BORDER_COLOR_TYPE; - -/* - * TEX_CHROMA_KEY enum - */ - -typedef enum TEX_CHROMA_KEY { -TEX_ChromaKey_Disabled = 0x00000000, -TEX_ChromaKey_Kill = 0x00000001, -TEX_ChromaKey_Blend = 0x00000002, -TEX_ChromaKey_RESERVED_3 = 0x00000003, -} TEX_CHROMA_KEY; - -/* - * TEX_CLAMP enum - */ - -typedef enum TEX_CLAMP { -TEX_Clamp_Repeat = 0x00000000, -TEX_Clamp_Mirror = 0x00000001, -TEX_Clamp_ClampToLast = 0x00000002, -TEX_Clamp_MirrorOnceToLast = 0x00000003, -TEX_Clamp_ClampHalfToBorder = 0x00000004, -TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, -TEX_Clamp_ClampToBorder = 0x00000006, -TEX_Clamp_MirrorOnceToBorder = 0x00000007, -} TEX_CLAMP; - -/* - * TEX_COORD_TYPE enum - */ - -typedef enum TEX_COORD_TYPE { -TEX_CoordType_Unnormalized = 0x00000000, -TEX_CoordType_Normalized = 0x00000001, -} TEX_COORD_TYPE; - -/* - * TEX_DEPTH_COMPARE_FUNCTION enum - */ - -typedef enum TEX_DEPTH_COMPARE_FUNCTION { -TEX_DepthCompareFunction_Never = 0x00000000, -TEX_DepthCompareFunction_Less = 0x00000001, -TEX_DepthCompareFunction_Equal = 0x00000002, -TEX_DepthCompareFunction_LessEqual = 0x00000003, -TEX_DepthCompareFunction_Greater = 0x00000004, -TEX_DepthCompareFunction_NotEqual = 0x00000005, -TEX_DepthCompareFunction_GreaterEqual = 0x00000006, -TEX_DepthCompareFunction_Always = 0x00000007, -} TEX_DEPTH_COMPARE_FUNCTION; - -/* - * TEX_FORMAT_COMP enum - */ - -typedef enum TEX_FORMAT_COMP { -TEX_FormatComp_Unsigned = 0x00000000, -TEX_FormatComp_Signed = 0x00000001, -TEX_FormatComp_UnsignedBiased = 0x00000002, -TEX_FormatComp_RESERVED_3 = 0x00000003, -} TEX_FORMAT_COMP; - -/* - * TEX_MAX_ANISO_RATIO enum - */ - -typedef enum TEX_MAX_ANISO_RATIO { -TEX_MaxAnisoRatio_1to1 = 0x00000000, -TEX_MaxAnisoRatio_2to1 = 0x00000001, -TEX_MaxAnisoRatio_4to1 = 0x00000002, -TEX_MaxAnisoRatio_8to1 = 0x00000003, -TEX_MaxAnisoRatio_16to1 = 0x00000004, -TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, -TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, -TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, -} TEX_MAX_ANISO_RATIO; - -/* - * TEX_MIP_FILTER enum - */ - -typedef enum TEX_MIP_FILTER { -TEX_MipFilter_None = 0x00000000, -TEX_MipFilter_Point = 0x00000001, -TEX_MipFilter_Linear = 0x00000002, -TEX_MipFilter_Point_Aniso_Adj = 0x00000003, -} TEX_MIP_FILTER; - -/* - * TEX_REQUEST_SIZE enum - */ - -typedef enum TEX_REQUEST_SIZE { -TEX_RequestSize_32B = 0x00000000, -TEX_RequestSize_64B = 0x00000001, -TEX_RequestSize_128B = 0x00000002, -TEX_RequestSize_2X64B = 0x00000003, -} TEX_REQUEST_SIZE; - -/* - * TEX_SAMPLER_TYPE enum - */ - -typedef enum TEX_SAMPLER_TYPE { -TEX_SamplerType_Invalid = 0x00000000, -TEX_SamplerType_Valid = 0x00000001, -} TEX_SAMPLER_TYPE; - -/* - * TEX_XY_FILTER enum - */ - -typedef enum TEX_XY_FILTER { -TEX_XYFilter_Point = 0x00000000, -TEX_XYFilter_Linear = 0x00000001, -TEX_XYFilter_AnisoPoint = 0x00000002, -TEX_XYFilter_AnisoLinear = 0x00000003, -} TEX_XY_FILTER; - -/* - * TEX_Z_FILTER enum - */ - -typedef enum TEX_Z_FILTER { -TEX_ZFilter_None = 0x00000000, -TEX_ZFilter_Point = 0x00000001, -TEX_ZFilter_Linear = 0x00000002, -TEX_ZFilter_RESERVED_3 = 0x00000003, -} TEX_Z_FILTER; - -/* - * TVX_TYPE enum - */ - -typedef enum TVX_TYPE { -TVX_Type_InvalidTextureResource = 0x00000000, -TVX_Type_InvalidVertexBuffer = 0x00000001, -TVX_Type_ValidTextureResource = 0x00000002, -TVX_Type_ValidVertexBuffer = 0x00000003, -} TVX_TYPE; - -/******************************************************* - * TCP Enums - *******************************************************/ - -/* - * TA_TC_ADDR_MODES enum - */ - -typedef enum TA_TC_ADDR_MODES { -TA_TC_ADDR_MODE_DEFAULT = 0x00000000, -TA_TC_ADDR_MODE_COMP0 = 0x00000001, -TA_TC_ADDR_MODE_COMP1 = 0x00000002, -TA_TC_ADDR_MODE_COMP2 = 0x00000003, -TA_TC_ADDR_MODE_COMP3 = 0x00000004, -TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, -TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, -} TA_TC_ADDR_MODES; - -/* - * TA_TC_REQ_MODES enum - */ - -typedef enum TA_TC_REQ_MODES { -TA_TC_REQ_MODE_BORDER = 0x00000000, -TA_TC_REQ_MODE_TEX2 = 0x00000001, -TA_TC_REQ_MODE_TEX1 = 0x00000002, -TA_TC_REQ_MODE_TEX0 = 0x00000003, -TA_TC_REQ_MODE_NORMAL = 0x00000004, -TA_TC_REQ_MODE_DWORD = 0x00000005, -TA_TC_REQ_MODE_BYTE = 0x00000006, -TA_TC_REQ_MODE_BYTE_NV = 0x00000007, -} TA_TC_REQ_MODES; - -/* - * TCP_CACHE_POLICIES enum - */ - -typedef enum TCP_CACHE_POLICIES { -TCP_CACHE_POLICY_MISS_LRU = 0x00000000, -TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, -TCP_CACHE_POLICY_HIT_LRU = 0x00000002, -TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, -} TCP_CACHE_POLICIES; - -/* - * TCP_CACHE_STORE_POLICIES enum - */ - -typedef enum TCP_CACHE_STORE_POLICIES { -TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, -TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, -} TCP_CACHE_STORE_POLICIES; - -/* - * TCP_DSM_DATA_SEL enum - */ - -typedef enum TCP_DSM_DATA_SEL { -TCP_DSM_DISABLE = 0x00000000, -TCP_DSM_SEL0 = 0x00000001, -TCP_DSM_SEL1 = 0x00000002, -TCP_DSM_SEL_BOTH = 0x00000003, -} TCP_DSM_DATA_SEL; - -/* - * TCP_DSM_INJECT_SEL enum - */ - -typedef enum TCP_DSM_INJECT_SEL { -TCP_DSM_INJECT_SEL0 = 0x00000000, -TCP_DSM_INJECT_SEL1 = 0x00000001, -TCP_DSM_INJECT_SEL2 = 0x00000002, -TCP_DSM_INJECT_SEL3 = 0x00000003, -} TCP_DSM_INJECT_SEL; - -/* - * TCP_DSM_SINGLE_WRITE enum - */ - -typedef enum TCP_DSM_SINGLE_WRITE { -TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, -TCP_DSM_SINGLE_WRITE_EN = 0x00000001, -} TCP_DSM_SINGLE_WRITE; - -/* - * TCP_OPCODE_TYPE enum - */ - -typedef enum TCP_OPCODE_TYPE { -TCP_OPCODE_READ = 0x00000000, -TCP_OPCODE_WRITE = 0x00000001, -TCP_OPCODE_ATOMIC = 0x00000002, -TCP_OPCODE_INV = 0x00000003, -TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004, -TCP_OPCODE_SAMPLER = 0x00000005, -TCP_OPCODE_LOAD = 0x00000006, -TCP_OPCODE_GATHERH = 0x00000007, -} TCP_OPCODE_TYPE; - -/* - * TCP_PERFCOUNT_SELECT enum - */ - -typedef enum TCP_PERFCOUNT_SELECT { -TCP_PERF_SEL_GATE_EN1 = 0x00000000, -TCP_PERF_SEL_GATE_EN2 = 0x00000001, -TCP_PERF_SEL_TA_REQ = 0x00000002, -TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000003, -TCP_PERF_SEL_TA_REQ_READ = 0x00000004, -TCP_PERF_SEL_TA_REQ_WRITE = 0x00000005, -TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x00000006, -TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x00000007, -TCP_PERF_SEL_TA_REQ_GL0_INV = 0x00000008, -TCP_PERF_SEL_REQ = 0x00000009, -TCP_PERF_SEL_REQ_READ = 0x0000000a, -TCP_PERF_SEL_REQ_READ_HIT_EVICT = 0x0000000b, -TCP_PERF_SEL_REQ_READ_HIT_LRU = 0x0000000c, -TCP_PERF_SEL_REQ_READ_MISS_EVICT = 0x0000000d, -TCP_PERF_SEL_REQ_WRITE = 0x0000000e, -TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 0x0000000f, -TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 0x00000010, -TCP_PERF_SEL_REQ_NON_READ = 0x00000011, -TCP_PERF_SEL_REQ_MISS = 0x00000012, -TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 0x00000013, -TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 0x00000014, -TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 0x00000015, -TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 0x00000016, -TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 0x00000017, -TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 0x00000018, -TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 0x00000019, -TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 0x0000001a, -TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 0x0000001b, -TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 0x0000001c, -TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 0x0000001d, -TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 0x0000001e, -TCP_PERF_SEL_GL1_REQ_READ = 0x0000001f, -TCP_PERF_SEL_GL1_REQ_READ_128B = 0x00000020, -TCP_PERF_SEL_GL1_REQ_READ_64B = 0x00000021, -TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000022, -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000023, -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000024, -TCP_PERF_SEL_GL1_READ_LATENCY = 0x00000025, -TCP_PERF_SEL_GL1_WRITE_LATENCY = 0x00000026, -TCP_PERF_SEL_TCP_LATENCY = 0x00000027, -TCP_PERF_SEL_TCP_TA_REQ_STALL = 0x00000028, -TCP_PERF_SEL_TA_TCP_REQ_STARVE = 0x00000029, -TCP_PERF_SEL_DATA_FIFO_STALL = 0x0000002a, -TCP_PERF_SEL_LOD_STALL = 0x0000002b, -TCP_PERF_SEL_POWER_STALL = 0x0000002c, -TCP_PERF_SEL_ALLOC_STALL = 0x0000002d, -TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000002e, -TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 0x0000002f, -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 0x00000030, -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 0x00000031, -TCP_PERF_SEL_LFIFO_STALL = 0x00000032, -TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 0x00000033, -TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 0x00000034, -TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 0x00000035, -TCP_PERF_SEL_GL1_GRANT_READ_STALL = 0x00000036, -TCP_PERF_SEL_GL1_PENDING_STALL = 0x00000037, -TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 0x00000038, -TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 0x00000039, -TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 0x0000003a, -TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 0x0000003b, -TCP_PERF_SEL_READ_DATACONFLICT_STALL = 0x0000003c, -TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 0x0000003d, -TCP_PERF_SEL_TD_TCP_STALL = 0x0000003e, -} TCP_PERFCOUNT_SELECT; - -/* - * TCP_WATCH_MODES enum - */ - -typedef enum TCP_WATCH_MODES { -TCP_WATCH_MODE_READ = 0x00000000, -TCP_WATCH_MODE_NONREAD = 0x00000001, -TCP_WATCH_MODE_ATOMIC = 0x00000002, -TCP_WATCH_MODE_ALL = 0x00000003, -} TCP_WATCH_MODES; - -/******************************************************* - * TD Enums - *******************************************************/ - -/* - * TD_PERFCOUNT_SEL enum - */ - -typedef enum TD_PERFCOUNT_SEL { -TD_PERF_SEL_none = 0x00000000, -TD_PERF_SEL_td_busy = 0x00000001, -TD_PERF_SEL_input_busy = 0x00000002, -TD_PERF_SEL_sampler_lerp_busy = 0x00000003, -TD_PERF_SEL_sampler_out_busy = 0x00000004, -TD_PERF_SEL_nofilter_busy = 0x00000005, -TD_PERF_SEL_ray_tracing_bvh4_busy = 0x00000006, -TD_PERF_SEL_sampler_core_sclk_en = 0x00000007, -TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008, -TD_PERF_SEL_sampler_bilerp_sclk_en = 0x00000009, -TD_PERF_SEL_sampler_bypass_sclk_en = 0x0000000a, -TD_PERF_SEL_sampler_minmax_sclk_en = 0x0000000b, -TD_PERF_SEL_sampler_accum_sclk_en = 0x0000000c, -TD_PERF_SEL_sampler_format_flt_sclk_en = 0x0000000d, -TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e, -TD_PERF_SEL_sampler_out_sclk_en = 0x0000000f, -TD_PERF_SEL_nofilter_sclk_en = 0x00000010, -TD_PERF_SEL_nofilter_d32_sclk_en = 0x00000011, -TD_PERF_SEL_nofilter_d16_sclk_en = 0x00000012, -TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 0x00000016, -TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 0x00000017, -TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 0x00000018, -TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 0x00000019, -TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a, -TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b, -TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c, -TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 0x0000001d, -TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 0x0000001e, -TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 0x0000001f, -TD_PERF_SEL_core_state_ram_max_cnt = 0x00000020, -TD_PERF_SEL_core_state_rams_read = 0x00000021, -TD_PERF_SEL_weight_data_rams_read = 0x00000022, -TD_PERF_SEL_reference_data_rams_read = 0x00000023, -TD_PERF_SEL_tc_td_ram_fifo_full = 0x00000024, -TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 0x00000025, -TD_PERF_SEL_tc_td_data_fifo_full = 0x00000026, -TD_PERF_SEL_input_state_fifo_full = 0x00000027, -TD_PERF_SEL_ta_data_stall = 0x00000028, -TD_PERF_SEL_tc_data_stall = 0x00000029, -TD_PERF_SEL_tc_ram_stall = 0x0000002a, -TD_PERF_SEL_lds_stall = 0x0000002b, -TD_PERF_SEL_sampler_pkr_full = 0x0000002c, -TD_PERF_SEL_sampler_pkr_full_due_to_arb = 0x0000002d, -TD_PERF_SEL_nofilter_pkr_full = 0x0000002e, -TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f, -TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 0x00000030, -TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 0x00000031, -TD_PERF_SEL_gather4_instr = 0x00000032, -TD_PERF_SEL_gather4h_instr = 0x00000033, -TD_PERF_SEL_sample_instr = 0x00000036, -TD_PERF_SEL_sample_c_instr = 0x00000037, -TD_PERF_SEL_load_instr = 0x00000038, -TD_PERF_SEL_ldfptr_instr = 0x00000039, -TD_PERF_SEL_write_ack_instr = 0x0000003a, -TD_PERF_SEL_d16_en_instr = 0x0000003b, -TD_PERF_SEL_bypassLerp_instr = 0x0000003c, -TD_PERF_SEL_min_max_filter_instr = 0x0000003d, -TD_PERF_SEL_one_comp_return_instr = 0x0000003e, -TD_PERF_SEL_two_comp_return_instr = 0x0000003f, -TD_PERF_SEL_three_comp_return_instr = 0x00000040, -TD_PERF_SEL_four_comp_return_instr = 0x00000041, -TD_PERF_SEL_user_defined_border = 0x00000042, -TD_PERF_SEL_white_border = 0x00000043, -TD_PERF_SEL_opaque_black_border = 0x00000044, -TD_PERF_SEL_lod_warn_from_ta = 0x00000045, -TD_PERF_SEL_instruction_dest_is_lds = 0x00000046, -TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047, -TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048, -TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049, -TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a, -TD_PERF_SEL_out_of_order_instr = 0x0000004b, -TD_PERF_SEL_total_num_instr = 0x0000004c, -TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d, -TD_PERF_SEL_total_num_sampler_instr = 0x0000004e, -TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f, -TD_PERF_SEL_total_num_nofilter_instr = 0x00000050, -TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051, -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 0x00000052, -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 0x00000053, -TD_PERF_SEL_mixmode_instr = 0x00000054, -TD_PERF_SEL_mixmode_resource = 0x00000055, -TD_PERF_SEL_status_packet = 0x00000056, -TD_PERF_SEL_address_cmd_poison = 0x00000057, -TD_PERF_SEL_data_poison = 0x00000058, -TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059, -TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a, -TD_PERF_SEL_done_scoreboard_not_empty = 0x0000005b, -TD_PERF_SEL_done_scoreboard_is_full = 0x0000005c, -TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d, -TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e, -TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f, -TD_PERF_SEL_nofilter_insert_extra_comps = 0x00000060, -TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061, -TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062, -TD_PERF_SEL_msaa_load_instr = 0x00000063, -TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064, -TD_PERF_SEL_blend_prt_with_prt_default_1 = 0x00000065, -TD_PERF_SEL_resmap_instr = 0x00000066, -TD_PERF_SEL_prt_ack_instr = 0x00000067, -TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068, -TD_PERF_SEL_resmap_with_aniso_filtering = 0x00000069, -TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a, -TD_PERF_SEL_resmap_with_cubemap_corner = 0x0000006b, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 0x0000006c, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 0x0000006d, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 0x0000006e, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 0x0000006f, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 0x00000070, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 0x00000071, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 0x00000072, -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 0x00000073, -TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 0x00000074, -TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 0x00000075, -TD_PERF_SEL_ray_tracing_bvh4_tri_node = 0x00000076, -TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 0x00000077, -TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 0x00000078, -TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 0x00000079, -TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 0x0000007a, -TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 0x0000007b, -TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 0x0000007c, -TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 0x0000007d, -TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 0x0000007e, -TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 0x0000007f, -TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 0x00000080, -TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 0x00000081, -TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 0x00000082, -TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083, -TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084, -TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085, -TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086, -TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087, -TD_PERF_SEL_burst_bin_sampler_1 = 0x00000088, -TD_PERF_SEL_burst_bin_sampler_2to8 = 0x00000089, -TD_PERF_SEL_burst_bin_sampler_9to16 = 0x0000008a, -TD_PERF_SEL_burst_bin_sampler_gt16 = 0x0000008b, -TD_PERF_SEL_burst_bin_gather_1 = 0x0000008c, -TD_PERF_SEL_burst_bin_gather_2to8 = 0x0000008d, -TD_PERF_SEL_burst_bin_gather_9to16 = 0x0000008e, -TD_PERF_SEL_burst_bin_gather_gt16 = 0x0000008f, -TD_PERF_SEL_burst_bin_nofilter_1 = 0x00000090, -TD_PERF_SEL_burst_bin_nofilter_2to4 = 0x00000091, -TD_PERF_SEL_burst_bin_nofilter_5to7 = 0x00000092, -TD_PERF_SEL_burst_bin_nofilter_8to16 = 0x00000093, -TD_PERF_SEL_burst_bin_nofilter_gt16 = 0x00000094, -TD_PERF_SEL_burst_bin_bvh4_1 = 0x00000095, -TD_PERF_SEL_burst_bin_bvh4_2to8 = 0x00000096, -TD_PERF_SEL_burst_bin_bvh4_9to16 = 0x00000097, -TD_PERF_SEL_burst_bin_bvh4_gt16 = 0x00000098, -TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 0x00000099, -TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 0x0000009a, -TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 0x0000009b, -TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 0x0000009c, -TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 0x0000009d, -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 0x0000009e, -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 0x0000009f, -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 0x000000a0, -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 0x000000a1, -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 0x000000a2, -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 0x000000a3, -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 0x000000a4, -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 0x000000a5, -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 0x000000a6, -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 0x000000a7, -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 0x000000a8, -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 0x000000a9, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae, -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af, -TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 0x000000b0, -TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 0x000000b1, -TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 0x000000b2, -TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 0x000000b3, -TD_PERF_SEL_preempting_nofilter_max_cnt = 0x000000b4, -TD_PERF_SEL_sampler_lerp0_active = 0x000000b5, -TD_PERF_SEL_sampler_lerp1_active = 0x000000b6, -TD_PERF_SEL_sampler_lerp2_active = 0x000000b7, -TD_PERF_SEL_sampler_lerp3_active = 0x000000b8, -TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000b9, -TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000ba, -TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bb, -TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000bc, -TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000bd, -TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000be, -TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000bf, -TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 0x000000c0, -} TD_PERFCOUNT_SEL; - -/******************************************************* - * GL2C Enums - *******************************************************/ - -/* - * GL2A_PERF_SEL enum - */ - -typedef enum GL2A_PERF_SEL { -GL2A_PERF_SEL_NONE = 0x00000000, -GL2A_PERF_SEL_CYCLE = 0x00000001, -GL2A_PERF_SEL_BUSY = 0x00000002, -GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003, -GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004, -GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005, -GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006, -GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007, -GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008, -GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009, -GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 0x0000000b, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 0x0000000c, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 0x0000000d, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 0x0000000e, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 0x0000000f, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 0x00000010, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 0x00000011, -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 0x00000012, -GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013, -GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014, -GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015, -GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016, -GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017, -GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018, -GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019, -GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a, -GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b, -GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c, -GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d, -GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e, -GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f, -GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020, -GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021, -GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022, -GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023, -GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024, -GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025, -GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026, -GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027, -GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028, -GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029, -GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a, -GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b, -GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c, -GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d, -GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e, -GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f, -GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030, -GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031, -GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032, -GL2A_PERF_SEL_RTN_CLIENT8 = 0x00000033, -GL2A_PERF_SEL_RTN_CLIENT9 = 0x00000034, -GL2A_PERF_SEL_RTN_CLIENT10 = 0x00000035, -GL2A_PERF_SEL_RTN_CLIENT11 = 0x00000036, -GL2A_PERF_SEL_RTN_CLIENT12 = 0x00000037, -GL2A_PERF_SEL_RTN_CLIENT13 = 0x00000038, -GL2A_PERF_SEL_RTN_CLIENT14 = 0x00000039, -GL2A_PERF_SEL_RTN_CLIENT15 = 0x0000003a, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x0000003b, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x0000003c, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x0000003d, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x0000003e, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x0000003f, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000040, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000041, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x00000042, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 0x00000043, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 0x00000044, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049, -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a, -GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 0x0000004b, -GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 0x0000004c, -GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 0x0000004d, -GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 0x0000004e, -GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 0x0000004f, -GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 0x00000050, -GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 0x00000051, -GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 0x00000052, -GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 0x00000053, -GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 0x00000054, -GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 0x00000055, -GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 0x00000056, -GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 0x00000057, -GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 0x00000058, -GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 0x00000059, -GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 0x0000005a, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 0x0000005b, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 0x0000005c, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 0x0000005d, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 0x0000005e, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 0x0000005f, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 0x00000060, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 0x00000061, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 0x00000062, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 0x00000063, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 0x00000064, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 0x00000065, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 0x00000067, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 0x00000068, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 0x00000069, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 0x0000006a, -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 0x0000006b, -} GL2A_PERF_SEL; - -/* - * GL2C_PERF_SEL enum - */ - -typedef enum GL2C_PERF_SEL { -GL2C_PERF_SEL_NONE = 0x00000000, -GL2C_PERF_SEL_CYCLE = 0x00000001, -GL2C_PERF_SEL_BUSY = 0x00000002, -GL2C_PERF_SEL_REQ = 0x00000003, -GL2C_PERF_SEL_VOL_REQ = 0x00000004, -GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005, -GL2C_PERF_SEL_READ = 0x00000006, -GL2C_PERF_SEL_WRITE = 0x00000007, -GL2C_PERF_SEL_ATOMIC = 0x00000008, -GL2C_PERF_SEL_NOP_ACK = 0x00000009, -GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a, -GL2C_PERF_SEL_PROBE = 0x0000000b, -GL2C_PERF_SEL_PROBE_ALL = 0x0000000c, -GL2C_PERF_SEL_INTERNAL_PROBE = 0x0000000d, -GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000e, -GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000f, -GL2C_PERF_SEL_CLIENT0_REQ = 0x00000010, -GL2C_PERF_SEL_CLIENT1_REQ = 0x00000011, -GL2C_PERF_SEL_CLIENT2_REQ = 0x00000012, -GL2C_PERF_SEL_CLIENT3_REQ = 0x00000013, -GL2C_PERF_SEL_CLIENT4_REQ = 0x00000014, -GL2C_PERF_SEL_CLIENT5_REQ = 0x00000015, -GL2C_PERF_SEL_CLIENT6_REQ = 0x00000016, -GL2C_PERF_SEL_CLIENT7_REQ = 0x00000017, -GL2C_PERF_SEL_CLIENT8_REQ = 0x00000018, -GL2C_PERF_SEL_CLIENT9_REQ = 0x00000019, -GL2C_PERF_SEL_CLIENT10_REQ = 0x0000001a, -GL2C_PERF_SEL_CLIENT11_REQ = 0x0000001b, -GL2C_PERF_SEL_CLIENT12_REQ = 0x0000001c, -GL2C_PERF_SEL_CLIENT13_REQ = 0x0000001d, -GL2C_PERF_SEL_CLIENT14_REQ = 0x0000001e, -GL2C_PERF_SEL_CLIENT15_REQ = 0x0000001f, -GL2C_PERF_SEL_C_RW_S_REQ = 0x00000020, -GL2C_PERF_SEL_C_RW_US_REQ = 0x00000021, -GL2C_PERF_SEL_C_RO_S_REQ = 0x00000022, -GL2C_PERF_SEL_C_RO_US_REQ = 0x00000023, -GL2C_PERF_SEL_UC_REQ = 0x00000024, -GL2C_PERF_SEL_LRU_REQ = 0x00000025, -GL2C_PERF_SEL_STREAM_REQ = 0x00000026, -GL2C_PERF_SEL_BYPASS_REQ = 0x00000027, -GL2C_PERF_SEL_NOA_REQ = 0x00000028, -GL2C_PERF_SEL_SHARED_REQ = 0x00000029, -GL2C_PERF_SEL_HIT = 0x0000002a, -GL2C_PERF_SEL_MISS = 0x0000002b, -GL2C_PERF_SEL_FULL_HIT = 0x0000002c, -GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x0000002d, -GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x0000002e, -GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x0000002f, -GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000030, -GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000031, -GL2C_PERF_SEL_UNCACHED_WRITE = 0x00000032, -GL2C_PERF_SEL_WRITEBACK = 0x00000033, -GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x00000034, -GL2C_PERF_SEL_EVICT = 0x00000035, -GL2C_PERF_SEL_NORMAL_EVICT = 0x00000036, -GL2C_PERF_SEL_PROBE_EVICT = 0x00000037, -GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000038, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000039, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x0000003a, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x0000003b, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x0000003c, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x0000003d, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x0000003e, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x0000003f, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x00000040, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 0x00000041, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 0x00000042, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 0x00000043, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 0x00000044, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 0x00000045, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 0x00000046, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 0x00000047, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 0x00000048, -GL2C_PERF_SEL_READ_32_REQ = 0x00000049, -GL2C_PERF_SEL_READ_64_REQ = 0x0000004a, -GL2C_PERF_SEL_READ_128_REQ = 0x0000004b, -GL2C_PERF_SEL_WRITE_32_REQ = 0x0000004c, -GL2C_PERF_SEL_WRITE_64_REQ = 0x0000004d, -GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x0000004e, -GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x0000004f, -GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x00000050, -GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x00000051, -GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x00000052, -GL2C_PERF_SEL_MC_WRREQ = 0x00000053, -GL2C_PERF_SEL_EA_WRREQ_SNOOP = 0x00000054, -GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000055, -GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x00000056, -GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000057, -GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000058, -GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000059, -GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x0000005a, -GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000005b, -GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x0000005c, -GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x0000005d, -GL2C_PERF_SEL_EA_ATOMIC = 0x0000005e, -GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x0000005f, -GL2C_PERF_SEL_MC_RDREQ = 0x00000060, -GL2C_PERF_SEL_EA_RDREQ_SNOOP = 0x00000061, -GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x00000062, -GL2C_PERF_SEL_EA_RDREQ_32B = 0x00000063, -GL2C_PERF_SEL_EA_RDREQ_64B = 0x00000064, -GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000065, -GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000066, -GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000067, -GL2C_PERF_SEL_EA_RD_MDC_32B = 0x00000068, -GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000069, -GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000006a, -GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000006b, -GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000006c, -GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x0000006d, -GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x0000006e, -GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x0000006f, -GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x00000070, -GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x00000071, -GL2C_PERF_SEL_ONION_READ = 0x00000072, -GL2C_PERF_SEL_ONION_WRITE = 0x00000073, -GL2C_PERF_SEL_IO_READ = 0x00000074, -GL2C_PERF_SEL_IO_WRITE = 0x00000075, -GL2C_PERF_SEL_GARLIC_READ = 0x00000076, -GL2C_PERF_SEL_GARLIC_WRITE = 0x00000077, -GL2C_PERF_SEL_EA_OUTSTANDING = 0x00000078, -GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000079, -GL2C_PERF_SEL_SRC_FIFO_FULL = 0x0000007a, -GL2C_PERF_SEL_TAG_STALL = 0x0000007b, -GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000007c, -GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000007d, -GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000007e, -GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000007f, -GL2C_PERF_SEL_TAG_PROBE_STALL = 0x00000080, -GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000081, -GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000082, -GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x00000083, -GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000084, -GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000085, -GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000086, -GL2C_PERF_SEL_BUBBLE = 0x00000087, -GL2C_PERF_SEL_IB_REQ = 0x00000088, -GL2C_PERF_SEL_IB_STALL = 0x00000089, -GL2C_PERF_SEL_IB_TAG_STALL = 0x0000008a, -GL2C_PERF_SEL_IB_CM_STALL = 0x0000008b, -GL2C_PERF_SEL_RETURN_ACK = 0x0000008c, -GL2C_PERF_SEL_RETURN_DATA = 0x0000008d, -GL2C_PERF_SEL_EA_RDRET_NACK = 0x0000008e, -GL2C_PERF_SEL_EA_WRRET_NACK = 0x0000008f, -GL2C_PERF_SEL_GL2A_LEVEL = 0x00000090, -GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000091, -GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000092, -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000093, -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000094, -GL2C_PERF_SEL_GCR_INV = 0x00000095, -GL2C_PERF_SEL_GCR_WB = 0x00000096, -GL2C_PERF_SEL_GCR_DISCARD = 0x00000097, -GL2C_PERF_SEL_GCR_RANGE = 0x00000098, -GL2C_PERF_SEL_GCR_ALL = 0x00000099, -GL2C_PERF_SEL_GCR_VOL = 0x0000009a, -GL2C_PERF_SEL_GCR_UNSHARED = 0x0000009b, -GL2C_PERF_SEL_GCR_MDC_INV = 0x0000009c, -GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x0000009d, -GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x0000009e, -GL2C_PERF_SEL_GCR_MDC_INV_ALL = 0x0000009f, -GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x000000a0, -GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x000000a1, -GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x000000a2, -GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 0x000000a3, -GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x000000a4, -GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x000000a5, -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x000000a6, -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x000000a7, -GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x000000a8, -GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x000000a9, -GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x000000aa, -GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x000000ab, -GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x000000ac, -GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x000000ad, -GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x000000ae, -GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x000000af, -GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000b0, -GL2C_PERF_SEL_MDC_INV_METADATA = 0x000000b1, -GL2C_PERF_SEL_MDC_REQ = 0x000000b2, -GL2C_PERF_SEL_MDC_LEVEL = 0x000000b3, -GL2C_PERF_SEL_MDC_TAG_HIT = 0x000000b4, -GL2C_PERF_SEL_MDC_SECTOR_HIT = 0x000000b5, -GL2C_PERF_SEL_MDC_SECTOR_MISS = 0x000000b6, -GL2C_PERF_SEL_MDC_TAG_STALL = 0x000000b7, -GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000b8, -GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000b9, -GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000ba, -GL2C_PERF_SEL_CM_CHANNEL0_REQ = 0x000000bb, -GL2C_PERF_SEL_CM_CHANNEL1_REQ = 0x000000bc, -GL2C_PERF_SEL_CM_CHANNEL2_REQ = 0x000000bd, -GL2C_PERF_SEL_CM_CHANNEL3_REQ = 0x000000be, -GL2C_PERF_SEL_CM_CHANNEL4_REQ = 0x000000bf, -GL2C_PERF_SEL_CM_CHANNEL5_REQ = 0x000000c0, -GL2C_PERF_SEL_CM_CHANNEL6_REQ = 0x000000c1, -GL2C_PERF_SEL_CM_CHANNEL7_REQ = 0x000000c2, -GL2C_PERF_SEL_CM_CHANNEL8_REQ = 0x000000c3, -GL2C_PERF_SEL_CM_CHANNEL9_REQ = 0x000000c4, -GL2C_PERF_SEL_CM_CHANNEL10_REQ = 0x000000c5, -GL2C_PERF_SEL_CM_CHANNEL11_REQ = 0x000000c6, -GL2C_PERF_SEL_CM_CHANNEL12_REQ = 0x000000c7, -GL2C_PERF_SEL_CM_CHANNEL13_REQ = 0x000000c8, -GL2C_PERF_SEL_CM_CHANNEL14_REQ = 0x000000c9, -GL2C_PERF_SEL_CM_CHANNEL15_REQ = 0x000000ca, -GL2C_PERF_SEL_CM_CHANNEL16_REQ = 0x000000cb, -GL2C_PERF_SEL_CM_CHANNEL17_REQ = 0x000000cc, -GL2C_PERF_SEL_CM_CHANNEL18_REQ = 0x000000cd, -GL2C_PERF_SEL_CM_CHANNEL19_REQ = 0x000000ce, -GL2C_PERF_SEL_CM_CHANNEL20_REQ = 0x000000cf, -GL2C_PERF_SEL_CM_CHANNEL21_REQ = 0x000000d0, -GL2C_PERF_SEL_CM_CHANNEL22_REQ = 0x000000d1, -GL2C_PERF_SEL_CM_CHANNEL23_REQ = 0x000000d2, -GL2C_PERF_SEL_CM_CHANNEL24_REQ = 0x000000d3, -GL2C_PERF_SEL_CM_CHANNEL25_REQ = 0x000000d4, -GL2C_PERF_SEL_CM_CHANNEL26_REQ = 0x000000d5, -GL2C_PERF_SEL_CM_CHANNEL27_REQ = 0x000000d6, -GL2C_PERF_SEL_CM_CHANNEL28_REQ = 0x000000d7, -GL2C_PERF_SEL_CM_CHANNEL29_REQ = 0x000000d8, -GL2C_PERF_SEL_CM_CHANNEL30_REQ = 0x000000d9, -GL2C_PERF_SEL_CM_CHANNEL31_REQ = 0x000000da, -GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 0x000000db, -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000dc, -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000dd, -GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 0x000000de, -GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 0x000000df, -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 0x000000e0, -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 0x000000e1, -GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 0x000000e2, -GL2C_PERF_SEL_CM_COMP_READ_REQ = 0x000000e3, -GL2C_PERF_SEL_CM_READ_BACK_REQ = 0x000000e4, -GL2C_PERF_SEL_CM_METADATA_WR_REQ = 0x000000e5, -GL2C_PERF_SEL_CM_WR_ACK_REQ = 0x000000e6, -GL2C_PERF_SEL_CM_NO_ACK_REQ = 0x000000e7, -GL2C_PERF_SEL_CM_NOOP_REQ = 0x000000e8, -GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 0x000000e9, -GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 0x000000ea, -GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 0x000000eb, -GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 0x000000ec, -GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 0x000000ed, -GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 0x000000ee, -GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 0x000000ef, -GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 0x000000f0, -GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 0x000000f1, -GL2C_PERF_SEL_CM_RVF_FULL = 0x000000f2, -GL2C_PERF_SEL_CM_SDR_FULL = 0x000000f3, -GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 0x000000f4, -GL2C_PERF_SEL_CM_DCC_STALL = 0x000000f5, -GL2C_PERF_SEL_CM_DCC_IN_XFC = 0x000000f6, -GL2C_PERF_SEL_CM_DCC_OUT_XFC = 0x000000f7, -GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 0x000000f8, -GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 0x000000f9, -GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 0x000000fa, -GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 0x000000fb, -GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 0x000000fc, -GL2C_PERF_SEL_CM_DCC_OUT_CONST = 0x000000fd, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 0x000000fe, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 0x000000ff, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 0x00000100, -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 0x00000101, -} GL2C_PERF_SEL; - -/******************************************************* - * GRBM Enums - *******************************************************/ - -/* - * GRBM_PERF_SEL enum - */ - -typedef enum GRBM_PERF_SEL { -GRBM_PERF_SEL_COUNT = 0x00000000, -GRBM_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, -GRBM_PERF_SEL_CP_BUSY = 0x00000003, -GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, -GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, -GRBM_PERF_SEL_CB_BUSY = 0x00000006, -GRBM_PERF_SEL_DB_BUSY = 0x00000007, -GRBM_PERF_SEL_PA_BUSY = 0x00000008, -GRBM_PERF_SEL_SC_BUSY = 0x00000009, -GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, -GRBM_PERF_SEL_SX_BUSY = 0x0000000c, -GRBM_PERF_SEL_TA_BUSY = 0x0000000d, -GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, -GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, -GRBM_PERF_SEL_GDS_BUSY = 0x00000019, -GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, -GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, -GRBM_PERF_SEL_TCP_BUSY = 0x0000001c, -GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, -GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, -GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, -GRBM_PERF_SEL_GE_BUSY = 0x00000020, -GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021, -GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, -GRBM_PERF_SEL_EA_BUSY = 0x00000023, -GRBM_PERF_SEL_RMI_BUSY = 0x00000024, -GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, -GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027, -GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028, -GRBM_PERF_SEL_SDMA_BUSY = 0x00000029, -GRBM_PERF_SEL_CH_BUSY = 0x0000002a, -GRBM_PERF_SEL_PH_BUSY = 0x0000002b, -GRBM_PERF_SEL_PMM_BUSY = 0x0000002c, -GRBM_PERF_SEL_GUS_BUSY = 0x0000002d, -GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e, -GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 0x0000002f, -GRBM_PERF_SEL_GL1H_BUSY = 0x00000030, -GRBM_PERF_SEL_PC_BUSY = 0x00000031, -} GRBM_PERF_SEL; - -/* - * GRBM_SE0_PERF_SEL enum - */ - -typedef enum GRBM_SE0_PERF_SEL { -GRBM_SE0_PERF_SEL_COUNT = 0x00000000, -GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE0_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE0_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE0_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE0_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE0_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE0_PERF_SEL; - -/* - * GRBM_SE1_PERF_SEL enum - */ - -typedef enum GRBM_SE1_PERF_SEL { -GRBM_SE1_PERF_SEL_COUNT = 0x00000000, -GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE1_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE1_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE1_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE1_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE1_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE1_PERF_SEL; - -/* - * GRBM_SE2_PERF_SEL enum - */ - -typedef enum GRBM_SE2_PERF_SEL { -GRBM_SE2_PERF_SEL_COUNT = 0x00000000, -GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE2_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE2_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE2_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE2_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE2_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE2_PERF_SEL; - -/* - * GRBM_SE3_PERF_SEL enum - */ - -typedef enum GRBM_SE3_PERF_SEL { -GRBM_SE3_PERF_SEL_COUNT = 0x00000000, -GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE3_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE3_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE3_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE3_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE3_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE3_PERF_SEL; - -/* - * GRBM_SE4_PERF_SEL enum - */ - -typedef enum GRBM_SE4_PERF_SEL { -GRBM_SE4_PERF_SEL_COUNT = 0x00000000, -GRBM_SE4_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE4_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE4_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE4_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE4_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE4_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE4_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE4_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE4_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE4_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE4_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE4_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE4_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE4_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE4_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE4_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE4_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE4_PERF_SEL; - -/* - * GRBM_SE5_PERF_SEL enum - */ - -typedef enum GRBM_SE5_PERF_SEL { -GRBM_SE5_PERF_SEL_COUNT = 0x00000000, -GRBM_SE5_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE5_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE5_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE5_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE5_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE5_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE5_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE5_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE5_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE5_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE5_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE5_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE5_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE5_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE5_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE5_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE5_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE5_PERF_SEL; - -/* - * GRBM_SE6_PERF_SEL enum - */ - -typedef enum GRBM_SE6_PERF_SEL { -GRBM_SE6_PERF_SEL_COUNT = 0x00000000, -GRBM_SE6_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE6_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE6_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE6_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE6_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE6_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE6_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE6_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE6_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE6_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE6_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE6_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE6_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE6_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE6_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE6_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE6_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE6_PERF_SEL; - -/* - * GRBM_SE7_PERF_SEL enum - */ - -typedef enum GRBM_SE7_PERF_SEL { -GRBM_SE7_PERF_SEL_COUNT = 0x00000000, -GRBM_SE7_PERF_SEL_USER_DEFINED = 0x00000001, -GRBM_SE7_PERF_SEL_CB_BUSY = 0x00000002, -GRBM_SE7_PERF_SEL_DB_BUSY = 0x00000003, -GRBM_SE7_PERF_SEL_SC_BUSY = 0x00000004, -GRBM_SE7_PERF_SEL_SPI_BUSY = 0x00000006, -GRBM_SE7_PERF_SEL_SX_BUSY = 0x00000007, -GRBM_SE7_PERF_SEL_TA_BUSY = 0x00000008, -GRBM_SE7_PERF_SEL_CB_CLEAN = 0x00000009, -GRBM_SE7_PERF_SEL_DB_CLEAN = 0x0000000a, -GRBM_SE7_PERF_SEL_PA_BUSY = 0x0000000c, -GRBM_SE7_PERF_SEL_BCI_BUSY = 0x0000000e, -GRBM_SE7_PERF_SEL_RMI_BUSY = 0x0000000f, -GRBM_SE7_PERF_SEL_UTCL1_BUSY = 0x00000010, -GRBM_SE7_PERF_SEL_TCP_BUSY = 0x00000011, -GRBM_SE7_PERF_SEL_GL1CC_BUSY = 0x00000012, -GRBM_SE7_PERF_SEL_GL1H_BUSY = 0x00000013, -GRBM_SE7_PERF_SEL_PC_BUSY = 0x00000014, -} GRBM_SE7_PERF_SEL; - -/* - * PIPE_COMPAT_LEVEL enum - */ - -typedef enum PIPE_COMPAT_LEVEL { -GEN_ZERO = 0x00000000, -GEN_ONE = 0x00000001, -GEN_TWO = 0x00000002, -GEN_RESERVED = 0x00000003, -} PIPE_COMPAT_LEVEL; - -/******************************************************* - * CP Enums - *******************************************************/ - -/* - * CPC_LATENCY_STATS_SEL enum - */ - -typedef enum CPC_LATENCY_STATS_SEL { -CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, -CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, -CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, -CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, -CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, -CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, -CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006, -CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007, -CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008, -} CPC_LATENCY_STATS_SEL; - -/* - * CPC_PERFCOUNT_SEL enum - */ - -typedef enum CPC_PERFCOUNT_SEL { -CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 0x00000009, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a, -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 0x00000011, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012, -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, -CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019, -CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a, -CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b, -CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c, -CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d, -CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e, -CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f, -CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020, -CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021, -CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022, -CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023, -CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024, -CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025, -CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026, -CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027, -CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028, -CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029, -CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a, -CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b, -CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c, -CPC_PERF_SEL_MES_THREAD0 = 0x0000002d, -CPC_PERF_SEL_MES_THREAD1 = 0x0000002e, -} CPC_PERFCOUNT_SEL; - -/* - * CPF_LATENCY_STATS_SEL enum - */ - -typedef enum CPF_LATENCY_STATS_SEL { -CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, -CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, -CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, -CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, -CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, -CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, -CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006, -CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007, -CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008, -CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009, -CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a, -CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b, -} CPF_LATENCY_STATS_SEL; - -/* - * CPF_PERFCOUNTWINDOW_SEL enum - */ - -typedef enum CPF_PERFCOUNTWINDOW_SEL { -CPF_PERFWINDOW_SEL_CSF = 0x00000000, -CPF_PERFWINDOW_SEL_HQD1 = 0x00000001, -CPF_PERFWINDOW_SEL_HQD2 = 0x00000002, -CPF_PERFWINDOW_SEL_RDMA = 0x00000003, -CPF_PERFWINDOW_SEL_RWPP = 0x00000004, -} CPF_PERFCOUNTWINDOW_SEL; - -/* - * CPF_PERFCOUNT_SEL enum - */ - -typedef enum CPF_PERFCOUNT_SEL { -CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007, -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, -CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, -CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x0000000f, -CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000010, -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, -CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013, -CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014, -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015, -CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016, -CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017, -CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018, -CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019, -CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a, -CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b, -CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c, -CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d, -CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e, -CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f, -CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020, -CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021, -CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022, -CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023, -CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024, -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025, -CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026, -CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027, -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 0x00000028, -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 0x00000029, -CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 0x0000002a, -CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 0x0000002b, -} CPF_PERFCOUNT_SEL; - -/* - * CPF_SCRATCH_REG_ATOMIC_OP enum - */ - -typedef enum CPF_SCRATCH_REG_ATOMIC_OP { -CPF_SCRATCH_REG_ATOMIC_ADD = 0x00000000, -CPF_SCRATCH_REG_ATOMIC_SUB = 0x00000001, -CPF_SCRATCH_REG_ATOMIC_OR = 0x00000002, -CPF_SCRATCH_REG_ATOMIC_AND = 0x00000003, -CPF_SCRATCH_REG_ATOMIC_NOT = 0x00000004, -CPF_SCRATCH_REG_ATOMIC_MIN = 0x00000005, -CPF_SCRATCH_REG_ATOMIC_MAX = 0x00000006, -CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 0x00000007, -} CPF_SCRATCH_REG_ATOMIC_OP; - -/* - * CPG_LATENCY_STATS_SEL enum - */ - -typedef enum CPG_LATENCY_STATS_SEL { -CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000, -CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001, -CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002, -CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003, -CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004, -CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005, -CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006, -CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007, -CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008, -CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009, -CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a, -CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b, -CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c, -CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d, -CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e, -CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f, -CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010, -CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011, -} CPG_LATENCY_STATS_SEL; - -/* - * CPG_PERFCOUNTWINDOW_SEL enum - */ - -typedef enum CPG_PERFCOUNTWINDOW_SEL { -CPG_PERFWINDOW_SEL_PFP = 0x00000000, -CPG_PERFWINDOW_SEL_ME = 0x00000001, -CPG_PERFWINDOW_SEL_CE = 0x00000002, -CPG_PERFWINDOW_SEL_MES = 0x00000003, -CPG_PERFWINDOW_SEL_MEC1 = 0x00000004, -CPG_PERFWINDOW_SEL_MEC2 = 0x00000005, -CPG_PERFWINDOW_SEL_DFY = 0x00000006, -CPG_PERFWINDOW_SEL_DMA = 0x00000007, -CPG_PERFWINDOW_SEL_SHADOW = 0x00000008, -CPG_PERFWINDOW_SEL_RB = 0x00000009, -CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a, -CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b, -CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c, -CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d, -CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e, -CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f, -CPG_PERFWINDOW_SEL_MEMWR = 0x00000010, -CPG_PERFWINDOW_SEL_MEMRD = 0x00000011, -CPG_PERFWINDOW_SEL_VGT0 = 0x00000012, -CPG_PERFWINDOW_SEL_VGT1 = 0x00000013, -CPG_PERFWINDOW_SEL_APPEND = 0x00000014, -CPG_PERFWINDOW_SEL_QURD = 0x00000015, -CPG_PERFWINDOW_SEL_DDID = 0x00000016, -CPG_PERFWINDOW_SEL_SR = 0x00000017, -CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018, -CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019, -CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a, -CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b, -CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c, -CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d, -CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e, -} CPG_PERFCOUNTWINDOW_SEL; - -/* - * CPG_PERFCOUNT_SEL enum - */ - -typedef enum CPG_PERFCOUNT_SEL { -CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, -CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, -CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, -CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, -CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022, -CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023, -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, -CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031, -CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032, -CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033, -CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034, -CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035, -CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036, -CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037, -CPG_PERF_SEL_CPG_TCIU_STALL = 0x00000038, -CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039, -CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a, -CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b, -CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c, -CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d, -CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e, -CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f, -CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040, -CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041, -CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042, -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043, -CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044, -CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045, -CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046, -CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047, -CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048, -CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049, -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a, -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b, -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c, -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d, -CPG_PERF_SEL_DMA_BUSY = 0x0000004e, -CPG_PERF_SEL_DMA_STARVED = 0x0000004f, -CPG_PERF_SEL_DMA_STALLED = 0x00000050, -CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051, -CPG_PERF_SEL_PFP_PWS_STALLED0 = 0x00000052, -CPG_PERF_SEL_ME_PWS_STALLED0 = 0x00000053, -CPG_PERF_SEL_PFP_PWS_STALLED1 = 0x00000054, -CPG_PERF_SEL_ME_PWS_STALLED1 = 0x00000055, -} CPG_PERFCOUNT_SEL; - -/* - * CP_ALPHA_TAG_RAM_SEL enum - */ - -typedef enum CP_ALPHA_TAG_RAM_SEL { -CPG_TAG_RAM = 0x00000000, -CPC_TAG_RAM = 0x00000001, -CPF_TAG_RAM = 0x00000002, -RSV_TAG_RAM = 0x00000003, -} CP_ALPHA_TAG_RAM_SEL; - -/* - * CP_DDID_CNTL_MODE enum - */ - -typedef enum CP_DDID_CNTL_MODE { -STALL = 0x00000000, -OVERRUN = 0x00000001, -} CP_DDID_CNTL_MODE; - -/* - * CP_DDID_CNTL_SIZE enum - */ - -typedef enum CP_DDID_CNTL_SIZE { -SIZE_8K = 0x00000000, -SIZE_16K = 0x00000001, -} CP_DDID_CNTL_SIZE; - -/* - * CP_DDID_CNTL_VMID_SEL enum - */ - -typedef enum CP_DDID_CNTL_VMID_SEL { -DDID_VMID_PIPE = 0x00000000, -DDID_VMID_CNTL = 0x00000001, -} CP_DDID_CNTL_VMID_SEL; - -/* - * CP_ME_ID enum - */ - -typedef enum CP_ME_ID { -ME_ID0 = 0x00000000, -ME_ID1 = 0x00000001, -ME_ID2 = 0x00000002, -ME_ID3 = 0x00000003, -} CP_ME_ID; - -/* - * CP_PERFMON_ENABLE_MODE enum - */ - -typedef enum CP_PERFMON_ENABLE_MODE { -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, -} CP_PERFMON_ENABLE_MODE; - -/* - * CP_PERFMON_STATE enum - */ - -typedef enum CP_PERFMON_STATE { -CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, -CP_PERFMON_STATE_START_COUNTING = 0x00000001, -CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, -CP_PERFMON_STATE_RESERVED_3 = 0x00000003, -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} CP_PERFMON_STATE; - -/* - * CP_PIPE_ID enum - */ - -typedef enum CP_PIPE_ID { -PIPE_ID0 = 0x00000000, -PIPE_ID1 = 0x00000001, -PIPE_ID2 = 0x00000002, -PIPE_ID3 = 0x00000003, -} CP_PIPE_ID; - -/* - * CP_RING_ID enum - */ - -typedef enum CP_RING_ID { -RINGID0 = 0x00000000, -RINGID1 = 0x00000001, -RINGID2 = 0x00000002, -RINGID3 = 0x00000003, -} CP_RING_ID; - -/* - * SPM_PERFMON_STATE enum - */ - -typedef enum SPM_PERFMON_STATE { -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, -STRM_PERFMON_STATE_START_COUNTING = 0x00000001, -STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, -STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, -} SPM_PERFMON_STATE; - -/* - * SEM_RESPONSE value - */ - -#define SEM_ECC_ERROR 0x00000000 -#define SEM_TRANS_ERROR 0x00000001 -#define SEM_RESP_FAILED 0x00000002 -#define SEM_RESP_PASSED 0x00000003 - -/* - * IQ_RETRY_TYPE value - */ - -#define IQ_QUEUE_SLEEP 0x00000000 -#define IQ_OFFLOAD_RETRY 0x00000001 -#define IQ_SCH_WAVE_MSG 0x00000002 -#define IQ_SEM_REARM 0x00000003 -#define IQ_DEQUEUE_RETRY 0x00000004 - -/* - * IQ_INTR_TYPE value - */ - -#define IQ_INTR_TYPE_PQ 0x00000000 -#define IQ_INTR_TYPE_IB 0x00000001 -#define IQ_INTR_TYPE_MQD 0x00000002 - -/* - * VMID_SIZE value - */ - -#define VMID_SZ 0x00000004 - -/* - * SRCID_SECURE value - */ - -#define SRCID_RLC 0x00000000 -#define SRCID_RLCV 0x00000006 -#define SRCID_SECURE_CP 0x00000007 -#define SRCID_NONSECURE_CP 0x00000001 -#define SRCID_SECURE_CP_RCIU 0x00000007 -#define SRCID_NONSECURE_CP_RCIU 0x00000001 - -/* - * CONFIG_SPACE value - */ - -#define CONFIG_SPACE_START 0x00002000 -#define CONFIG_SPACE_END 0x00009fff - -/* - * CONFIG_SPACE1 value - */ - -#define CONFIG_SPACE1_START 0x00002000 -#define CONFIG_SPACE1_END 0x00002bff - -/* - * CONFIG_SPACE2 value - */ - -#define CONFIG_SPACE2_START 0x00003000 -#define CONFIG_SPACE2_END 0x00009fff - -/* - * UCONFIG_SPACE value - */ - -#define UCONFIG_SPACE_START 0x0000c000 -#define UCONFIG_SPACE_END 0x0000ffff - -/* - * PERSISTENT_SPACE value - */ - -#define PERSISTENT_SPACE_START 0x00002c00 -#define PERSISTENT_SPACE_END 0x00002fff - -/* - * CONTEXT_SPACE value - */ - -#define CONTEXT_SPACE_START 0x0000a000 -#define CONTEXT_SPACE_END 0x0000a3ff - -/******************************************************* - * SX Enums - *******************************************************/ - -/* - * SX_BLEND_OPT enum - */ - -typedef enum SX_BLEND_OPT { -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, -} SX_BLEND_OPT; - -/* - * SX_DOWNCONVERT_FORMAT enum - */ - -typedef enum SX_DOWNCONVERT_FORMAT { -SX_RT_EXPORT_NO_CONVERSION = 0x00000000, -SX_RT_EXPORT_32_R = 0x00000001, -SX_RT_EXPORT_32_A = 0x00000002, -SX_RT_EXPORT_10_11_11 = 0x00000003, -SX_RT_EXPORT_2_10_10_10 = 0x00000004, -SX_RT_EXPORT_8_8_8_8 = 0x00000005, -SX_RT_EXPORT_5_6_5 = 0x00000006, -SX_RT_EXPORT_1_5_5_5 = 0x00000007, -SX_RT_EXPORT_4_4_4_4 = 0x00000008, -SX_RT_EXPORT_16_16_GR = 0x00000009, -SX_RT_EXPORT_16_16_AR = 0x0000000a, -SX_RT_EXPORT_9_9_9_E5 = 0x0000000b, -SX_RT_EXPORT_2_10_10_10_7E3 = 0x0000000c, -SX_RT_EXPORT_2_10_10_10_6E4 = 0x0000000d, -} SX_DOWNCONVERT_FORMAT; - -/* - * SX_OPT_COMB_FCN enum - */ - -typedef enum SX_OPT_COMB_FCN { -OPT_COMB_NONE = 0x00000000, -OPT_COMB_ADD = 0x00000001, -OPT_COMB_SUBTRACT = 0x00000002, -OPT_COMB_MIN = 0x00000003, -OPT_COMB_MAX = 0x00000004, -OPT_COMB_REVSUBTRACT = 0x00000005, -OPT_COMB_BLEND_DISABLED = 0x00000006, -OPT_COMB_SAFE_ADD = 0x00000007, -} SX_OPT_COMB_FCN; - -/* - * SX_PERFCOUNTER_VALS enum - */ - -typedef enum SX_PERFCOUNTER_VALS { -SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, -SX_PERF_SEL_PA_REQ = 0x00000001, -SX_PERF_SEL_PA_POS = 0x00000002, -SX_PERF_SEL_CLOCK = 0x00000003, -SX_PERF_SEL_GATE_EN1 = 0x00000004, -SX_PERF_SEL_GATE_EN2 = 0x00000005, -SX_PERF_SEL_GATE_EN3 = 0x00000006, -SX_PERF_SEL_GATE_EN4 = 0x00000007, -SX_PERF_SEL_SH_POS_STARVE = 0x00000008, -SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, -SX_PERF_SEL_SH_POS_STALL = 0x0000000a, -SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, -SX_PERF_SEL_DB0_PIXELS = 0x0000000c, -SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, -SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, -SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, -SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, -SX_PERF_SEL_DB1_PIXELS = 0x00000011, -SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, -SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, -SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, -SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, -SX_PERF_SEL_DB2_PIXELS = 0x00000016, -SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, -SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, -SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, -SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, -SX_PERF_SEL_DB3_PIXELS = 0x0000001b, -SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, -SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, -SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, -SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, -SX_PERF_SEL_COL_BUSY = 0x00000020, -SX_PERF_SEL_POS_BUSY = 0x00000021, -SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 0x00000022, -SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 0x00000023, -SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 0x00000024, -SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 0x00000025, -SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 0x00000026, -SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 0x00000027, -SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 0x00000028, -SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 0x00000029, -SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 0x0000002a, -SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 0x0000002b, -SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 0x0000002c, -SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 0x0000002d, -SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 0x0000002e, -SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 0x0000002f, -SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 0x00000030, -SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 0x00000031, -SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 0x00000032, -SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 0x00000033, -SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 0x00000034, -SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 0x00000035, -SX_PERF_SEL_PA_REQ_LATENCY = 0x00000036, -SX_PERF_SEL_POS_SCBD_STALL = 0x00000037, -SX_PERF_SEL_CLOCK_DROP_STALL = 0x00000038, -SX_PERF_SEL_GATE_EN5 = 0x00000039, -SX_PERF_SEL_GATE_EN6 = 0x0000003a, -SX_PERF_SEL_DB0_SIZE = 0x0000003b, -SX_PERF_SEL_DB1_SIZE = 0x0000003c, -SX_PERF_SEL_DB2_SIZE = 0x0000003d, -SX_PERF_SEL_DB3_SIZE = 0x0000003e, -SX_PERF_SEL_IDX_STALL_CYCLES = 0x0000003f, -SX_PERF_SEL_IDX_IDLE_CYCLES = 0x00000040, -SX_PERF_SEL_IDX_REQ = 0x00000041, -SX_PERF_SEL_IDX_RET = 0x00000042, -SX_PERF_SEL_IDX_REQ_LATENCY = 0x00000043, -SX_PERF_SEL_IDX_SCBD_STALL = 0x00000044, -SX_PERF_SEL_GATE_EN7 = 0x00000045, -SX_PERF_SEL_GATE_EN8 = 0x00000046, -SX_PERF_SEL_SH_IDX_STARVE = 0x00000047, -SX_PERF_SEL_IDX_BUSY = 0x00000048, -SX_PERF_SEL_PA_POS_BANK_CONF = 0x00000049, -SX_PERF_SEL_DB0_END_OF_WAVE = 0x0000004a, -SX_PERF_SEL_DB0_4X2_DISCARD = 0x0000004b, -SX_PERF_SEL_DB1_END_OF_WAVE = 0x0000004c, -SX_PERF_SEL_DB1_4X2_DISCARD = 0x0000004d, -SX_PERF_SEL_DB2_END_OF_WAVE = 0x0000004e, -SX_PERF_SEL_DB2_4X2_DISCARD = 0x0000004f, -SX_PERF_SEL_DB3_END_OF_WAVE = 0x00000050, -SX_PERF_SEL_DB3_4X2_DISCARD = 0x00000051, -} SX_PERFCOUNTER_VALS; - -/******************************************************* - * DB Enums - *******************************************************/ - -/* - * CompareFrag enum - */ - -typedef enum CompareFrag { -FRAG_NEVER = 0x00000000, -FRAG_LESS = 0x00000001, -FRAG_EQUAL = 0x00000002, -FRAG_LEQUAL = 0x00000003, -FRAG_GREATER = 0x00000004, -FRAG_NOTEQUAL = 0x00000005, -FRAG_GEQUAL = 0x00000006, -FRAG_ALWAYS = 0x00000007, -} CompareFrag; - -/* - * ConservativeZExport enum - */ - -typedef enum ConservativeZExport { -EXPORT_ANY_Z = 0x00000000, -EXPORT_LESS_THAN_Z = 0x00000001, -EXPORT_GREATER_THAN_Z = 0x00000002, -EXPORT_RESERVED = 0x00000003, -} ConservativeZExport; - -/* - * DFSMFlushEvents enum - */ - -typedef enum DFSMFlushEvents { -DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, -DB_FLUSH_AND_INV_DB_META = 0x00000001, -DB_CACHE_FLUSH = 0x00000002, -DB_CACHE_FLUSH_TS = 0x00000003, -DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, -DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, -DB_VPORT_CHANGED_EVENT = 0x00000006, -DB_CONTEXT_DONE_EVENT = 0x00000007, -DB_BREAK_BATCH_EVENT = 0x00000008, -DB_INVOKE_CHANGE_EVENT = 0x00000009, -DB_CONTEXT_SUSPEND_EVENT = 0x0000000a, -} DFSMFlushEvents; - -/* - * DbMemArbWatermarks enum - */ - -typedef enum DbMemArbWatermarks { -TRANSFERRED_64_BYTES = 0x00000000, -TRANSFERRED_128_BYTES = 0x00000001, -TRANSFERRED_256_BYTES = 0x00000002, -TRANSFERRED_512_BYTES = 0x00000003, -TRANSFERRED_1024_BYTES = 0x00000004, -TRANSFERRED_2048_BYTES = 0x00000005, -TRANSFERRED_4096_BYTES = 0x00000006, -TRANSFERRED_8192_BYTES = 0x00000007, -} DbMemArbWatermarks; - -/* - * DbPRTFaultBehavior enum - */ - -typedef enum DbPRTFaultBehavior { -FAULT_ZERO = 0x00000000, -FAULT_ONE = 0x00000001, -FAULT_FAIL = 0x00000002, -FAULT_PASS = 0x00000003, -} DbPRTFaultBehavior; - -/* - * DbPSLControl enum - */ - -typedef enum DbPSLControl { -PSLC_AUTO = 0x00000000, -PSLC_ON_HANG_ONLY = 0x00000001, -PSLC_ASAP = 0x00000002, -PSLC_COUNTDOWN = 0x00000003, -} DbPSLControl; - -/* - * ForceControl enum - */ - -typedef enum ForceControl { -FORCE_OFF = 0x00000000, -FORCE_ENABLE = 0x00000001, -FORCE_DISABLE = 0x00000002, -FORCE_RESERVED = 0x00000003, -} ForceControl; - -/* - * OreoMode enum - */ - -typedef enum OreoMode { -OMODE_BLEND = 0x00000000, -OMODE_O_THEN_B = 0x00000001, -OMODE_P_THEN_O_THEN_B = 0x00000002, -OMODE_RESERVED_3 = 0x00000003, -} OreoMode; - -/* - * PerfCounter_Vals enum - */ - -typedef enum PerfCounter_Vals { -DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, -DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, -DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, -DB_PERF_SEL_SC_DB_tile_events = 0x00000003, -DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, -DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, -DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, -DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, -DB_PERF_SEL_hiz_tile_culled = 0x00000008, -DB_PERF_SEL_his_tile_culled = 0x00000009, -DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, -DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, -DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, -DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, -DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, -DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, -DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, -DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, -DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, -DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, -DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, -DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, -DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, -DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, -DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, -DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, -DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, -DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, -DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, -DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, -DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, -DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, -DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, -DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, -DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, -DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, -DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, -DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, -DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, -DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, -DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, -DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, -DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, -DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, -DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, -DB_PERF_SEL_tile_rd_sends = 0x00000030, -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, -DB_PERF_SEL_quad_rd_sends = 0x00000032, -DB_PERF_SEL_quad_rd_busy = 0x00000033, -DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, -DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, -DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, -DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, -DB_PERF_SEL_quad_rd_panic = 0x00000038, -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, -DB_PERF_SEL_quad_rdret_sends = 0x0000003a, -DB_PERF_SEL_quad_rdret_busy = 0x0000003b, -DB_PERF_SEL_tile_wr_sends = 0x0000003c, -DB_PERF_SEL_tile_wr_acks = 0x0000003d, -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, -DB_PERF_SEL_quad_wr_sends = 0x0000003f, -DB_PERF_SEL_quad_wr_busy = 0x00000040, -DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, -DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, -DB_PERF_SEL_quad_wr_acks = 0x00000043, -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, -DB_PERF_SEL_Tile_Cache_misses = 0x00000045, -DB_PERF_SEL_Tile_Cache_hits = 0x00000046, -DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, -DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, -DB_PERF_SEL_Tile_Cache_starves = 0x00000049, -DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, -DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, -DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, -DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, -DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, -DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, -DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, -DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, -DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, -DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, -DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, -DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, -DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, -DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, -DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, -DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, -DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, -DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, -DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, -DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, -DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, -DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, -DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, -DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, -DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, -DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, -DB_PERF_SEL_Z_Cache_frees = 0x0000006c, -DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, -DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, -DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, -DB_PERF_SEL_Plane_Cache_starves = 0x00000070, -DB_PERF_SEL_Plane_Cache_frees = 0x00000071, -DB_PERF_SEL_flush_expanded_stencil = 0x00000072, -DB_PERF_SEL_flush_compressed_stencil = 0x00000073, -DB_PERF_SEL_flush_single_stencil = 0x00000074, -DB_PERF_SEL_planes_flushed = 0x00000075, -DB_PERF_SEL_flush_1plane = 0x00000076, -DB_PERF_SEL_flush_2plane = 0x00000077, -DB_PERF_SEL_flush_3plane = 0x00000078, -DB_PERF_SEL_flush_4plane = 0x00000079, -DB_PERF_SEL_flush_5plane = 0x0000007a, -DB_PERF_SEL_flush_6plane = 0x0000007b, -DB_PERF_SEL_flush_7plane = 0x0000007c, -DB_PERF_SEL_flush_8plane = 0x0000007d, -DB_PERF_SEL_flush_9plane = 0x0000007e, -DB_PERF_SEL_flush_10plane = 0x0000007f, -DB_PERF_SEL_flush_11plane = 0x00000080, -DB_PERF_SEL_flush_12plane = 0x00000081, -DB_PERF_SEL_flush_13plane = 0x00000082, -DB_PERF_SEL_flush_14plane = 0x00000083, -DB_PERF_SEL_flush_15plane = 0x00000084, -DB_PERF_SEL_flush_16plane = 0x00000085, -DB_PERF_SEL_flush_expanded_z = 0x00000086, -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, -DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, -DB_PERF_SEL_dk_tile_sends = 0x00000089, -DB_PERF_SEL_dk_tile_busy = 0x0000008a, -DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, -DB_PERF_SEL_dk_tile_stalls = 0x0000008c, -DB_PERF_SEL_dk_squad_sends = 0x0000008d, -DB_PERF_SEL_dk_squad_busy = 0x0000008e, -DB_PERF_SEL_dk_squad_stalls = 0x0000008f, -DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, -DB_PERF_SEL_qc_busy = 0x00000092, -DB_PERF_SEL_qc_xfc = 0x00000093, -DB_PERF_SEL_qc_conflicts = 0x00000094, -DB_PERF_SEL_qc_full_stall = 0x00000095, -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, -DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, -DB_PERF_SEL_tl_busy = 0x00000099, -DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, -DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, -DB_PERF_SEL_tl_stencil_stall = 0x0000009c, -DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, -DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, -DB_PERF_SEL_tl_events = 0x0000009f, -DB_PERF_SEL_tl_summarize_squads = 0x000000a0, -DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, -DB_PERF_SEL_tl_expand_squads = 0x000000a2, -DB_PERF_SEL_tl_preZ_squads = 0x000000a3, -DB_PERF_SEL_tl_postZ_squads = 0x000000a4, -DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, -DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, -DB_PERF_SEL_tl_tile_ops = 0x000000a7, -DB_PERF_SEL_tl_in_xfc = 0x000000a8, -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, -DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, -DB_PERF_SEL_tl_out_xfc = 0x000000ab, -DB_PERF_SEL_tl_out_squads = 0x000000ac, -DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, -DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, -DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, -DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, -DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, -DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, -DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, -DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, -DB_PERF_SEL_sc_kick_start = 0x000000b5, -DB_PERF_SEL_sc_kick_end = 0x000000b6, -DB_PERF_SEL_clock_reg_active = 0x000000b7, -DB_PERF_SEL_clock_main_active = 0x000000b8, -DB_PERF_SEL_clock_mem_export_active = 0x000000b9, -DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, -DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, -DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, -DB_PERF_SEL_etr_out_send = 0x000000bd, -DB_PERF_SEL_etr_out_busy = 0x000000be, -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, -DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, -DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, -DB_PERF_SEL_esr_ps_vic_busy = 0x000000c2, -DB_PERF_SEL_esr_ps_vic_stall = 0x000000c3, -DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, -DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, -DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, -DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, -DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, -DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, -DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, -DB_PERF_SEL_postzl_se_busy = 0x000000cb, -DB_PERF_SEL_postzl_se_stall = 0x000000cc, -DB_PERF_SEL_postzl_partial_launch = 0x000000cd, -DB_PERF_SEL_postzl_full_launch = 0x000000ce, -DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, -DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, -DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, -DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2, -DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, -DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, -DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, -DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, -DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, -DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, -DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, -DB_PERF_SEL_mi_wrreq_stall = 0x000000da, -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, -DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, -DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, -DB_PERF_SEL_prezl_src_in_stall = 0x000000de, -DB_PERF_SEL_prezl_src_in_squads = 0x000000df, -DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, -DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, -DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, -DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, -DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, -DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, -DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, -DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, -DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, -DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, -DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, -DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, -DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, -DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, -DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3, -DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, -DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, -DB_PERF_SEL_flush_compressed = 0x000000f6, -DB_PERF_SEL_flush_plane_le4 = 0x000000f7, -DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, -DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, -DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, -DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, -DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, -DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, -DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, -DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, -DB_PERF_SEL_di_dt_stall = 0x00000100, -Spare_257 = 0x00000101, -DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102, -DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103, -DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104, -DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000105, -DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000106, -DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000107, -DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000108, -DB_PERF_SEL_CB_DB_rdreq_sends = 0x00000109, -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010a, -DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010b, -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010c, -DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010d, -DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010e, -DB_PERF_SEL_DB_CB_wrret_ack = 0x0000010f, -DB_PERF_SEL_DB_CB_wrret_nack = 0x00000110, -DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111, -DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112, -DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113, -DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114, -DB_PERF_SEL_unmapped_z_tile_culled = 0x00000115, -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116, -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117, -DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000118, -DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000119, -DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x0000011a, -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x0000011b, -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x0000011c, -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000011d, -DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000011e, -DB_PERF_SEL_DB_CB_context_dones = 0x0000011f, -DB_PERF_SEL_DB_CB_eop_dones = 0x00000120, -DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121, -DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122, -DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123, -DB_PERF_SEL_SC_DB_tile_backface = 0x00000124, -DB_PERF_SEL_SC_DB_quad_quads = 0x00000125, -DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126, -DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127, -DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128, -DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129, -DB_PERF_SEL_DB_SC_quad_double_quad = 0x0000012a, -DB_PERF_SEL_SX_DB_quad_export_quads = 0x0000012b, -DB_PERF_SEL_SX_DB_quad_double_format = 0x0000012c, -DB_PERF_SEL_SX_DB_quad_fast_format = 0x0000012d, -DB_PERF_SEL_SX_DB_quad_slow_format = 0x0000012e, -DB_PERF_SEL_quad_rd_sends_unc = 0x0000012f, -DB_PERF_SEL_quad_rd_mi_stall_unc = 0x00000130, -DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 0x00000131, -DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 0x00000132, -DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 0x00000133, -DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 0x00000134, -DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135, -DB_PERF_SEL_noz_waiting_for_postz_done = 0x00000136, -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 0x00000137, -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 0x00000138, -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 0x00000139, -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 0x0000013a, -DB_PERF_SEL_RMI_rd_tile_32byte_req = 0x0000013b, -DB_PERF_SEL_RMI_rd_z_32byte_req = 0x0000013c, -DB_PERF_SEL_RMI_rd_s_32byte_req = 0x0000013d, -DB_PERF_SEL_RMI_wr_tile_32byte_req = 0x0000013e, -DB_PERF_SEL_RMI_wr_z_32byte_req = 0x0000013f, -DB_PERF_SEL_RMI_wr_s_32byte_req = 0x00000140, -DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 0x00000141, -DB_PERF_SEL_RMI_rd_tile_32byte_ret = 0x00000142, -DB_PERF_SEL_RMI_rd_z_32byte_ret = 0x00000143, -DB_PERF_SEL_RMI_rd_s_32byte_ret = 0x00000144, -DB_PERF_SEL_RMI_wr_tile_32byte_ack = 0x00000145, -DB_PERF_SEL_RMI_wr_z_32byte_ack = 0x00000146, -DB_PERF_SEL_RMI_wr_s_32byte_ack = 0x00000147, -DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 0x00000148, -DB_PERF_SEL_esr_vic_sqq_busy = 0x00000149, -DB_PERF_SEL_esr_vic_sqq_stall = 0x0000014a, -DB_PERF_SEL_esr_psi_vic_tile_rate = 0x0000014b, -DB_PERF_SEL_esr_vic_footprint_match_2x2 = 0x0000014c, -DB_PERF_SEL_esr_vic_footprint_match_2x1 = 0x0000014d, -DB_PERF_SEL_esr_vic_footprint_match_1x2 = 0x0000014e, -DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f, -DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150, -DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151, -DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152, -DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153, -DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154, -DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155, -DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 0x00000156, -DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 0x00000157, -DB_PERF_SEL_ts_events_pws_enable = 0x00000158, -DB_PERF_SEL_ps_events_pws_enable = 0x00000159, -DB_PERF_SEL_cs_events_pws_enable = 0x0000015a, -DB_PERF_SEL_DB_SC_quad_noz_tiles = 0x0000015b, -DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 0x0000015c, -} PerfCounter_Vals; - -/* - * PixelPipeCounterId enum - */ - -typedef enum PixelPipeCounterId { -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, -PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, -PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, -PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, -} PixelPipeCounterId; - -/* - * PixelPipeStride enum - */ - -typedef enum PixelPipeStride { -PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, -PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, -PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, -PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, -} PixelPipeStride; - -/* - * RingCounterControl enum - */ - -typedef enum RingCounterControl { -COUNTER_RING_SPLIT = 0x00000000, -COUNTER_RING_0 = 0x00000001, -COUNTER_RING_1 = 0x00000002, -} RingCounterControl; - -/* - * StencilOp enum - */ - -typedef enum StencilOp { -STENCIL_KEEP = 0x00000000, -STENCIL_ZERO = 0x00000001, -STENCIL_ONES = 0x00000002, -STENCIL_REPLACE_TEST = 0x00000003, -STENCIL_REPLACE_OP = 0x00000004, -STENCIL_ADD_CLAMP = 0x00000005, -STENCIL_SUB_CLAMP = 0x00000006, -STENCIL_INVERT = 0x00000007, -STENCIL_ADD_WRAP = 0x00000008, -STENCIL_SUB_WRAP = 0x00000009, -STENCIL_AND = 0x0000000a, -STENCIL_OR = 0x0000000b, -STENCIL_XOR = 0x0000000c, -STENCIL_NAND = 0x0000000d, -STENCIL_NOR = 0x0000000e, -STENCIL_XNOR = 0x0000000f, -} StencilOp; - -/* - * ZLimitSumm enum - */ - -typedef enum ZLimitSumm { -FORCE_SUMM_OFF = 0x00000000, -FORCE_SUMM_MINZ = 0x00000001, -FORCE_SUMM_MAXZ = 0x00000002, -FORCE_SUMM_BOTH = 0x00000003, -} ZLimitSumm; - -/* - * ZModeForce enum - */ - -typedef enum ZModeForce { -NO_FORCE = 0x00000000, -FORCE_EARLY_Z = 0x00000001, -FORCE_LATE_Z = 0x00000002, -FORCE_RE_Z = 0x00000003, -} ZModeForce; - -/* - * ZOrder enum - */ - -typedef enum ZOrder { -LATE_Z = 0x00000000, -EARLY_Z_THEN_LATE_Z = 0x00000001, -RE_Z = 0x00000002, -EARLY_Z_THEN_RE_Z = 0x00000003, -} ZOrder; - -/* - * ZSamplePosition enum - */ - -typedef enum ZSamplePosition { -Z_SAMPLE_CENTER = 0x00000000, -Z_SAMPLE_CENTROID = 0x00000001, -} ZSamplePosition; - -/* - * ZpassControl enum - */ - -typedef enum ZpassControl { -ZPASS_DISABLE = 0x00000000, -ZPASS_SAMPLES = 0x00000001, -ZPASS_PIXELS = 0x00000002, -} ZpassControl; - -/******************************************************* - * PA Enums - *******************************************************/ - -/* - * SU_PERFCNT_SEL enum - */ - -typedef enum SU_PERFCNT_SEL { -PERF_PAPC_PASX_REQ = 0x00000000, -PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, -PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, -PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, -PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, -PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, -PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, -PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, -PERF_PAPC_PA_INPUT_PRIM = 0x00000008, -PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, -PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, -PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, -PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, -PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, -PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, -PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, -PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, -PERF_PAPC_SU_INPUT_PRIM = 0x00000031, -PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, -PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, -PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, -PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, -PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, -PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, -PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, -PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, -PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, -PERF_PAPC_PASX_REC_IDLE = 0x00000050, -PERF_PAPC_PASX_REC_BUSY = 0x00000051, -PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, -PERF_PAPC_PASX_REC_STALLED = 0x00000053, -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, -PERF_PAPC_CCGSM_IDLE = 0x00000056, -PERF_PAPC_CCGSM_BUSY = 0x00000057, -PERF_PAPC_CCGSM_STALLED = 0x00000058, -PERF_PAPC_CLPRIM_IDLE = 0x00000059, -PERF_PAPC_CLPRIM_BUSY = 0x0000005a, -PERF_PAPC_CLPRIM_STALLED = 0x0000005b, -PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, -PERF_PAPC_CLIPSM_IDLE = 0x0000005d, -PERF_PAPC_CLIPSM_BUSY = 0x0000005e, -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, -PERF_PAPC_CLIPGA_IDLE = 0x00000064, -PERF_PAPC_CLIPGA_BUSY = 0x00000065, -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, -PERF_PAPC_CLIPGA_STALLED = 0x00000067, -PERF_PAPC_CLIP_IDLE = 0x00000068, -PERF_PAPC_CLIP_BUSY = 0x00000069, -PERF_PAPC_SU_IDLE = 0x0000006a, -PERF_PAPC_SU_BUSY = 0x0000006b, -PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, -PERF_PAPC_SU_STALLED_SC = 0x0000006d, -PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, -PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, -PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, -PERF_PAPC_PASX_SE0_REQ = 0x00000072, -PERF_PAPC_PASX_SE1_REQ = 0x00000073, -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, -PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, -PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, -PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, -PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, -PERF_PAPC_SU_CULLED_PRIM = 0x00000087, -PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, -PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, -PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, -PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, -PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, -PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, -PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, -PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099, -PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a, -PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b, -PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c, -PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d, -PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e, -PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f, -PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0, -PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1, -PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2, -PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3, -PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4, -PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5, -PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6, -PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7, -PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8, -PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000aa, -PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ab, -PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ac, -PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ad, -PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ae, -PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000af, -PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000b0, -PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b1, -PERF_PA_VERTEX_FIFO_FULL = 0x000000b3, -PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x000000b4, -PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x000000b6, -PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 0x000000b7, -PERF_PA_PIPE0_SWITCHED_GEN = 0x000000b9, -PERF_PA_PIPE1_SWITCHED_GEN = 0x000000ba, -PERF_ENGG_CSB_MACHINE_IS_STARVED = 0x000000bc, -PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000bd, -PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x000000be, -PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 0x000000bf, -PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 0x000000c0, -PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 0x000000c1, -PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 0x000000c2, -PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 0x000000c3, -PERF_ENGG_CSB_NULL_SUBGROUP = 0x000000c4, -PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 0x000000c5, -PERF_ENGG_CSB_GE_MEMORY_FULL = 0x000000c6, -PERF_ENGG_CSB_GE_MEMORY_EMPTY = 0x000000c7, -PERF_ENGG_CSB_SPI_MEMORY_FULL = 0x000000c8, -PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 0x000000c9, -PERF_ENGG_CSB_DELAY_BIN00 = 0x000000ca, -PERF_ENGG_CSB_DELAY_BIN01 = 0x000000cb, -PERF_ENGG_CSB_DELAY_BIN02 = 0x000000cc, -PERF_ENGG_CSB_DELAY_BIN03 = 0x000000cd, -PERF_ENGG_CSB_DELAY_BIN04 = 0x000000ce, -PERF_ENGG_CSB_DELAY_BIN05 = 0x000000cf, -PERF_ENGG_CSB_DELAY_BIN06 = 0x000000d0, -PERF_ENGG_CSB_DELAY_BIN07 = 0x000000d1, -PERF_ENGG_CSB_DELAY_BIN08 = 0x000000d2, -PERF_ENGG_CSB_DELAY_BIN09 = 0x000000d3, -PERF_ENGG_CSB_DELAY_BIN10 = 0x000000d4, -PERF_ENGG_CSB_DELAY_BIN11 = 0x000000d5, -PERF_ENGG_CSB_DELAY_BIN12 = 0x000000d6, -PERF_ENGG_CSB_DELAY_BIN13 = 0x000000d7, -PERF_ENGG_CSB_DELAY_BIN14 = 0x000000d8, -PERF_ENGG_CSB_DELAY_BIN15 = 0x000000d9, -PERF_ENGG_CSB_SPI_DELAY_BIN00 = 0x000000da, -PERF_ENGG_CSB_SPI_DELAY_BIN01 = 0x000000db, -PERF_ENGG_CSB_SPI_DELAY_BIN02 = 0x000000dc, -PERF_ENGG_CSB_SPI_DELAY_BIN03 = 0x000000dd, -PERF_ENGG_CSB_SPI_DELAY_BIN04 = 0x000000de, -PERF_ENGG_CSB_SPI_DELAY_BIN05 = 0x000000df, -PERF_ENGG_CSB_SPI_DELAY_BIN06 = 0x000000e0, -PERF_ENGG_CSB_SPI_DELAY_BIN07 = 0x000000e1, -PERF_ENGG_CSB_SPI_DELAY_BIN08 = 0x000000e2, -PERF_ENGG_CSB_SPI_DELAY_BIN09 = 0x000000e3, -PERF_ENGG_CSB_SPI_DELAY_BIN10 = 0x000000e4, -PERF_ENGG_INDEX_REQ_NULL_REQUEST = 0x000000e5, -PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 0x000000e6, -PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 0x000000e7, -PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 0x000000e8, -PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 0x000000e9, -PERF_ENGG_INDEX_REQ_STARVED = 0x000000ea, -PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000eb, -PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000ec, -PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000ed, -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x000000ee, -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x000000ef, -PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000f0, -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x000000f1, -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000f2, -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000f3, -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000f4, -PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 0x000000f5, -PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f6, -PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f7, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f8, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f9, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000fa, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000fb, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000fc, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000fd, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000fe, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000ff, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x00000100, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x00000101, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 0x00000102, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 0x00000103, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 0x00000104, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 0x00000105, -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 0x00000106, -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000107, -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000108, -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000109, -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x0000010a, -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x0000010b, -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x0000010c, -PERF_ENGG_POS_REQ_STARVED = 0x0000010d, -PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x0000010e, -PERF_ENGG_BUSY = 0x0000010f, -PERF_CLIPSM_CULL_PRIMS_CNT = 0x00000110, -PERF_PH_SEND_1_SC = 0x00000111, -PERF_PH_SEND_2_SC = 0x00000112, -PERF_PH_SEND_3_SC = 0x00000113, -PERF_PH_SEND_4_SC = 0x00000114, -PERF_OUTPUT_PRIM_1_SC = 0x00000115, -PERF_OUTPUT_PRIM_2_SC = 0x00000116, -PERF_OUTPUT_PRIM_3_SC = 0x00000117, -PERF_OUTPUT_PRIM_4_SC = 0x00000118, -} SU_PERFCNT_SEL; - -/******************************************************* - * PH Enums - *******************************************************/ - -/* - * PH_PERFCNT_SEL enum - */ - -typedef enum PH_PERFCNT_SEL { -PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0x00000000, -PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001, -PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002, -PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003, -PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 0x00000004, -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005, -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006, -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007, -PH_PERF_SEL_SC0_ARB_BUSY = 0x00000008, -PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 0x00000009, -PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a, -PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 0x0000000b, -PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c, -PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 0x0000000d, -PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e, -PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f, -PH_PERF_SEL_SC0_SEND = 0x00000010, -PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011, -PH_PERF_SEL_SC0_CREDIT_AT_MAX = 0x00000012, -PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013, -PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014, -PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015, -PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016, -PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017, -PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 0x00000018, -PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 0x00000019, -PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 0x0000001a, -PH_PERF_SEL_SC0_PA0_FIFO_FULL = 0x0000001b, -PH_PERF_SEL_SC0_PA0_NULL_WE = 0x0000001c, -PH_PERF_SEL_SC0_PA0_EVENT_WE = 0x0000001d, -PH_PERF_SEL_SC0_PA0_FPOV_WE = 0x0000001e, -PH_PERF_SEL_SC0_PA0_LPOV_WE = 0x0000001f, -PH_PERF_SEL_SC0_PA0_EOP_WE = 0x00000020, -PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021, -PH_PERF_SEL_SC0_PA0_EOPG_WE = 0x00000022, -PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 0x00000023, -PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 0x00000024, -PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 0x00000025, -PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 0x00000026, -PH_PERF_SEL_SC0_PA1_FIFO_FULL = 0x00000027, -PH_PERF_SEL_SC0_PA1_NULL_WE = 0x00000028, -PH_PERF_SEL_SC0_PA1_EVENT_WE = 0x00000029, -PH_PERF_SEL_SC0_PA1_FPOV_WE = 0x0000002a, -PH_PERF_SEL_SC0_PA1_LPOV_WE = 0x0000002b, -PH_PERF_SEL_SC0_PA1_EOP_WE = 0x0000002c, -PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d, -PH_PERF_SEL_SC0_PA1_EOPG_WE = 0x0000002e, -PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 0x0000002f, -PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 0x00000030, -PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 0x00000031, -PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 0x00000032, -PH_PERF_SEL_SC0_PA2_FIFO_FULL = 0x00000033, -PH_PERF_SEL_SC0_PA2_NULL_WE = 0x00000034, -PH_PERF_SEL_SC0_PA2_EVENT_WE = 0x00000035, -PH_PERF_SEL_SC0_PA2_FPOV_WE = 0x00000036, -PH_PERF_SEL_SC0_PA2_LPOV_WE = 0x00000037, -PH_PERF_SEL_SC0_PA2_EOP_WE = 0x00000038, -PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039, -PH_PERF_SEL_SC0_PA2_EOPG_WE = 0x0000003a, -PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 0x0000003b, -PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 0x0000003c, -PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 0x0000003d, -PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 0x0000003e, -PH_PERF_SEL_SC0_PA3_FIFO_FULL = 0x0000003f, -PH_PERF_SEL_SC0_PA3_NULL_WE = 0x00000040, -PH_PERF_SEL_SC0_PA3_EVENT_WE = 0x00000041, -PH_PERF_SEL_SC0_PA3_FPOV_WE = 0x00000042, -PH_PERF_SEL_SC0_PA3_LPOV_WE = 0x00000043, -PH_PERF_SEL_SC0_PA3_EOP_WE = 0x00000044, -PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045, -PH_PERF_SEL_SC0_PA3_EOPG_WE = 0x00000046, -PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 0x00000047, -PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 0x00000048, -PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 0x00000049, -PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 0x0000004a, -PH_PERF_SEL_SC0_PA4_FIFO_FULL = 0x0000004b, -PH_PERF_SEL_SC0_PA4_NULL_WE = 0x0000004c, -PH_PERF_SEL_SC0_PA4_EVENT_WE = 0x0000004d, -PH_PERF_SEL_SC0_PA4_FPOV_WE = 0x0000004e, -PH_PERF_SEL_SC0_PA4_LPOV_WE = 0x0000004f, -PH_PERF_SEL_SC0_PA4_EOP_WE = 0x00000050, -PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051, -PH_PERF_SEL_SC0_PA4_EOPG_WE = 0x00000052, -PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 0x00000053, -PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 0x00000054, -PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 0x00000055, -PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 0x00000056, -PH_PERF_SEL_SC0_PA5_FIFO_FULL = 0x00000057, -PH_PERF_SEL_SC0_PA5_NULL_WE = 0x00000058, -PH_PERF_SEL_SC0_PA5_EVENT_WE = 0x00000059, -PH_PERF_SEL_SC0_PA5_FPOV_WE = 0x0000005a, -PH_PERF_SEL_SC0_PA5_LPOV_WE = 0x0000005b, -PH_PERF_SEL_SC0_PA5_EOP_WE = 0x0000005c, -PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d, -PH_PERF_SEL_SC0_PA5_EOPG_WE = 0x0000005e, -PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 0x0000005f, -PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 0x00000060, -PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 0x00000061, -PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 0x00000062, -PH_PERF_SEL_SC0_PA6_FIFO_FULL = 0x00000063, -PH_PERF_SEL_SC0_PA6_NULL_WE = 0x00000064, -PH_PERF_SEL_SC0_PA6_EVENT_WE = 0x00000065, -PH_PERF_SEL_SC0_PA6_FPOV_WE = 0x00000066, -PH_PERF_SEL_SC0_PA6_LPOV_WE = 0x00000067, -PH_PERF_SEL_SC0_PA6_EOP_WE = 0x00000068, -PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069, -PH_PERF_SEL_SC0_PA6_EOPG_WE = 0x0000006a, -PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 0x0000006b, -PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 0x0000006c, -PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 0x0000006d, -PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 0x0000006e, -PH_PERF_SEL_SC0_PA7_FIFO_FULL = 0x0000006f, -PH_PERF_SEL_SC0_PA7_NULL_WE = 0x00000070, -PH_PERF_SEL_SC0_PA7_EVENT_WE = 0x00000071, -PH_PERF_SEL_SC0_PA7_FPOV_WE = 0x00000072, -PH_PERF_SEL_SC0_PA7_LPOV_WE = 0x00000073, -PH_PERF_SEL_SC0_PA7_EOP_WE = 0x00000074, -PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075, -PH_PERF_SEL_SC0_PA7_EOPG_WE = 0x00000076, -PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 0x00000077, -PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 0x00000078, -PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079, -PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a, -PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b, -PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c, -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d, -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e, -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f, -PH_PERF_SEL_SC1_ARB_BUSY = 0x00000080, -PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 0x00000081, -PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082, -PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 0x00000083, -PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084, -PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 0x00000085, -PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086, -PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 0x00000087, -PH_PERF_SEL_SC1_SEND = 0x00000088, -PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089, -PH_PERF_SEL_SC1_CREDIT_AT_MAX = 0x0000008a, -PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b, -PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c, -PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d, -PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e, -PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f, -PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 0x00000090, -PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 0x00000091, -PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 0x00000092, -PH_PERF_SEL_SC1_PA0_FIFO_FULL = 0x00000093, -PH_PERF_SEL_SC1_PA0_NULL_WE = 0x00000094, -PH_PERF_SEL_SC1_PA0_EVENT_WE = 0x00000095, -PH_PERF_SEL_SC1_PA0_FPOV_WE = 0x00000096, -PH_PERF_SEL_SC1_PA0_LPOV_WE = 0x00000097, -PH_PERF_SEL_SC1_PA0_EOP_WE = 0x00000098, -PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099, -PH_PERF_SEL_SC1_PA0_EOPG_WE = 0x0000009a, -PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 0x0000009b, -PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 0x0000009c, -PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 0x0000009d, -PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 0x0000009e, -PH_PERF_SEL_SC1_PA1_FIFO_FULL = 0x0000009f, -PH_PERF_SEL_SC1_PA1_NULL_WE = 0x000000a0, -PH_PERF_SEL_SC1_PA1_EVENT_WE = 0x000000a1, -PH_PERF_SEL_SC1_PA1_FPOV_WE = 0x000000a2, -PH_PERF_SEL_SC1_PA1_LPOV_WE = 0x000000a3, -PH_PERF_SEL_SC1_PA1_EOP_WE = 0x000000a4, -PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5, -PH_PERF_SEL_SC1_PA1_EOPG_WE = 0x000000a6, -PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 0x000000a7, -PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 0x000000a8, -PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 0x000000a9, -PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 0x000000aa, -PH_PERF_SEL_SC1_PA2_FIFO_FULL = 0x000000ab, -PH_PERF_SEL_SC1_PA2_NULL_WE = 0x000000ac, -PH_PERF_SEL_SC1_PA2_EVENT_WE = 0x000000ad, -PH_PERF_SEL_SC1_PA2_FPOV_WE = 0x000000ae, -PH_PERF_SEL_SC1_PA2_LPOV_WE = 0x000000af, -PH_PERF_SEL_SC1_PA2_EOP_WE = 0x000000b0, -PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1, -PH_PERF_SEL_SC1_PA2_EOPG_WE = 0x000000b2, -PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 0x000000b3, -PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 0x000000b4, -PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 0x000000b5, -PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 0x000000b6, -PH_PERF_SEL_SC1_PA3_FIFO_FULL = 0x000000b7, -PH_PERF_SEL_SC1_PA3_NULL_WE = 0x000000b8, -PH_PERF_SEL_SC1_PA3_EVENT_WE = 0x000000b9, -PH_PERF_SEL_SC1_PA3_FPOV_WE = 0x000000ba, -PH_PERF_SEL_SC1_PA3_LPOV_WE = 0x000000bb, -PH_PERF_SEL_SC1_PA3_EOP_WE = 0x000000bc, -PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd, -PH_PERF_SEL_SC1_PA3_EOPG_WE = 0x000000be, -PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 0x000000bf, -PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 0x000000c0, -PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 0x000000c1, -PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 0x000000c2, -PH_PERF_SEL_SC1_PA4_FIFO_FULL = 0x000000c3, -PH_PERF_SEL_SC1_PA4_NULL_WE = 0x000000c4, -PH_PERF_SEL_SC1_PA4_EVENT_WE = 0x000000c5, -PH_PERF_SEL_SC1_PA4_FPOV_WE = 0x000000c6, -PH_PERF_SEL_SC1_PA4_LPOV_WE = 0x000000c7, -PH_PERF_SEL_SC1_PA4_EOP_WE = 0x000000c8, -PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9, -PH_PERF_SEL_SC1_PA4_EOPG_WE = 0x000000ca, -PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 0x000000cb, -PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 0x000000cc, -PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 0x000000cd, -PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 0x000000ce, -PH_PERF_SEL_SC1_PA5_FIFO_FULL = 0x000000cf, -PH_PERF_SEL_SC1_PA5_NULL_WE = 0x000000d0, -PH_PERF_SEL_SC1_PA5_EVENT_WE = 0x000000d1, -PH_PERF_SEL_SC1_PA5_FPOV_WE = 0x000000d2, -PH_PERF_SEL_SC1_PA5_LPOV_WE = 0x000000d3, -PH_PERF_SEL_SC1_PA5_EOP_WE = 0x000000d4, -PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5, -PH_PERF_SEL_SC1_PA5_EOPG_WE = 0x000000d6, -PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 0x000000d7, -PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 0x000000d8, -PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 0x000000d9, -PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 0x000000da, -PH_PERF_SEL_SC1_PA6_FIFO_FULL = 0x000000db, -PH_PERF_SEL_SC1_PA6_NULL_WE = 0x000000dc, -PH_PERF_SEL_SC1_PA6_EVENT_WE = 0x000000dd, -PH_PERF_SEL_SC1_PA6_FPOV_WE = 0x000000de, -PH_PERF_SEL_SC1_PA6_LPOV_WE = 0x000000df, -PH_PERF_SEL_SC1_PA6_EOP_WE = 0x000000e0, -PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1, -PH_PERF_SEL_SC1_PA6_EOPG_WE = 0x000000e2, -PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 0x000000e3, -PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 0x000000e4, -PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 0x000000e5, -PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 0x000000e6, -PH_PERF_SEL_SC1_PA7_FIFO_FULL = 0x000000e7, -PH_PERF_SEL_SC1_PA7_NULL_WE = 0x000000e8, -PH_PERF_SEL_SC1_PA7_EVENT_WE = 0x000000e9, -PH_PERF_SEL_SC1_PA7_FPOV_WE = 0x000000ea, -PH_PERF_SEL_SC1_PA7_LPOV_WE = 0x000000eb, -PH_PERF_SEL_SC1_PA7_EOP_WE = 0x000000ec, -PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed, -PH_PERF_SEL_SC1_PA7_EOPG_WE = 0x000000ee, -PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 0x000000ef, -PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 0x000000f0, -PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1, -PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2, -PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3, -PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4, -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5, -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6, -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7, -PH_PERF_SEL_SC2_ARB_BUSY = 0x000000f8, -PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 0x000000f9, -PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa, -PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 0x000000fb, -PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc, -PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 0x000000fd, -PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe, -PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff, -PH_PERF_SEL_SC2_SEND = 0x00000100, -PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101, -PH_PERF_SEL_SC2_CREDIT_AT_MAX = 0x00000102, -PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103, -PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104, -PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105, -PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106, -PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107, -PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 0x00000108, -PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 0x00000109, -PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 0x0000010a, -PH_PERF_SEL_SC2_PA0_FIFO_FULL = 0x0000010b, -PH_PERF_SEL_SC2_PA0_NULL_WE = 0x0000010c, -PH_PERF_SEL_SC2_PA0_EVENT_WE = 0x0000010d, -PH_PERF_SEL_SC2_PA0_FPOV_WE = 0x0000010e, -PH_PERF_SEL_SC2_PA0_LPOV_WE = 0x0000010f, -PH_PERF_SEL_SC2_PA0_EOP_WE = 0x00000110, -PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111, -PH_PERF_SEL_SC2_PA0_EOPG_WE = 0x00000112, -PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 0x00000113, -PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 0x00000114, -PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 0x00000115, -PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 0x00000116, -PH_PERF_SEL_SC2_PA1_FIFO_FULL = 0x00000117, -PH_PERF_SEL_SC2_PA1_NULL_WE = 0x00000118, -PH_PERF_SEL_SC2_PA1_EVENT_WE = 0x00000119, -PH_PERF_SEL_SC2_PA1_FPOV_WE = 0x0000011a, -PH_PERF_SEL_SC2_PA1_LPOV_WE = 0x0000011b, -PH_PERF_SEL_SC2_PA1_EOP_WE = 0x0000011c, -PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d, -PH_PERF_SEL_SC2_PA1_EOPG_WE = 0x0000011e, -PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 0x0000011f, -PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 0x00000120, -PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 0x00000121, -PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 0x00000122, -PH_PERF_SEL_SC2_PA2_FIFO_FULL = 0x00000123, -PH_PERF_SEL_SC2_PA2_NULL_WE = 0x00000124, -PH_PERF_SEL_SC2_PA2_EVENT_WE = 0x00000125, -PH_PERF_SEL_SC2_PA2_FPOV_WE = 0x00000126, -PH_PERF_SEL_SC2_PA2_LPOV_WE = 0x00000127, -PH_PERF_SEL_SC2_PA2_EOP_WE = 0x00000128, -PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129, -PH_PERF_SEL_SC2_PA2_EOPG_WE = 0x0000012a, -PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 0x0000012b, -PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 0x0000012c, -PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 0x0000012d, -PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 0x0000012e, -PH_PERF_SEL_SC2_PA3_FIFO_FULL = 0x0000012f, -PH_PERF_SEL_SC2_PA3_NULL_WE = 0x00000130, -PH_PERF_SEL_SC2_PA3_EVENT_WE = 0x00000131, -PH_PERF_SEL_SC2_PA3_FPOV_WE = 0x00000132, -PH_PERF_SEL_SC2_PA3_LPOV_WE = 0x00000133, -PH_PERF_SEL_SC2_PA3_EOP_WE = 0x00000134, -PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135, -PH_PERF_SEL_SC2_PA3_EOPG_WE = 0x00000136, -PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 0x00000137, -PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 0x00000138, -PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 0x00000139, -PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 0x0000013a, -PH_PERF_SEL_SC2_PA4_FIFO_FULL = 0x0000013b, -PH_PERF_SEL_SC2_PA4_NULL_WE = 0x0000013c, -PH_PERF_SEL_SC2_PA4_EVENT_WE = 0x0000013d, -PH_PERF_SEL_SC2_PA4_FPOV_WE = 0x0000013e, -PH_PERF_SEL_SC2_PA4_LPOV_WE = 0x0000013f, -PH_PERF_SEL_SC2_PA4_EOP_WE = 0x00000140, -PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141, -PH_PERF_SEL_SC2_PA4_EOPG_WE = 0x00000142, -PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 0x00000143, -PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 0x00000144, -PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 0x00000145, -PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 0x00000146, -PH_PERF_SEL_SC2_PA5_FIFO_FULL = 0x00000147, -PH_PERF_SEL_SC2_PA5_NULL_WE = 0x00000148, -PH_PERF_SEL_SC2_PA5_EVENT_WE = 0x00000149, -PH_PERF_SEL_SC2_PA5_FPOV_WE = 0x0000014a, -PH_PERF_SEL_SC2_PA5_LPOV_WE = 0x0000014b, -PH_PERF_SEL_SC2_PA5_EOP_WE = 0x0000014c, -PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d, -PH_PERF_SEL_SC2_PA5_EOPG_WE = 0x0000014e, -PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 0x0000014f, -PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 0x00000150, -PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 0x00000151, -PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 0x00000152, -PH_PERF_SEL_SC2_PA6_FIFO_FULL = 0x00000153, -PH_PERF_SEL_SC2_PA6_NULL_WE = 0x00000154, -PH_PERF_SEL_SC2_PA6_EVENT_WE = 0x00000155, -PH_PERF_SEL_SC2_PA6_FPOV_WE = 0x00000156, -PH_PERF_SEL_SC2_PA6_LPOV_WE = 0x00000157, -PH_PERF_SEL_SC2_PA6_EOP_WE = 0x00000158, -PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159, -PH_PERF_SEL_SC2_PA6_EOPG_WE = 0x0000015a, -PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 0x0000015b, -PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 0x0000015c, -PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 0x0000015d, -PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 0x0000015e, -PH_PERF_SEL_SC2_PA7_FIFO_FULL = 0x0000015f, -PH_PERF_SEL_SC2_PA7_NULL_WE = 0x00000160, -PH_PERF_SEL_SC2_PA7_EVENT_WE = 0x00000161, -PH_PERF_SEL_SC2_PA7_FPOV_WE = 0x00000162, -PH_PERF_SEL_SC2_PA7_LPOV_WE = 0x00000163, -PH_PERF_SEL_SC2_PA7_EOP_WE = 0x00000164, -PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165, -PH_PERF_SEL_SC2_PA7_EOPG_WE = 0x00000166, -PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 0x00000167, -PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 0x00000168, -PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169, -PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a, -PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b, -PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c, -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d, -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e, -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f, -PH_PERF_SEL_SC3_ARB_BUSY = 0x00000170, -PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 0x00000171, -PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172, -PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 0x00000173, -PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174, -PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 0x00000175, -PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176, -PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 0x00000177, -PH_PERF_SEL_SC3_SEND = 0x00000178, -PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179, -PH_PERF_SEL_SC3_CREDIT_AT_MAX = 0x0000017a, -PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b, -PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c, -PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d, -PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e, -PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f, -PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 0x00000180, -PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 0x00000181, -PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 0x00000182, -PH_PERF_SEL_SC3_PA0_FIFO_FULL = 0x00000183, -PH_PERF_SEL_SC3_PA0_NULL_WE = 0x00000184, -PH_PERF_SEL_SC3_PA0_EVENT_WE = 0x00000185, -PH_PERF_SEL_SC3_PA0_FPOV_WE = 0x00000186, -PH_PERF_SEL_SC3_PA0_LPOV_WE = 0x00000187, -PH_PERF_SEL_SC3_PA0_EOP_WE = 0x00000188, -PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189, -PH_PERF_SEL_SC3_PA0_EOPG_WE = 0x0000018a, -PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 0x0000018b, -PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 0x0000018c, -PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 0x0000018d, -PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 0x0000018e, -PH_PERF_SEL_SC3_PA1_FIFO_FULL = 0x0000018f, -PH_PERF_SEL_SC3_PA1_NULL_WE = 0x00000190, -PH_PERF_SEL_SC3_PA1_EVENT_WE = 0x00000191, -PH_PERF_SEL_SC3_PA1_FPOV_WE = 0x00000192, -PH_PERF_SEL_SC3_PA1_LPOV_WE = 0x00000193, -PH_PERF_SEL_SC3_PA1_EOP_WE = 0x00000194, -PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195, -PH_PERF_SEL_SC3_PA1_EOPG_WE = 0x00000196, -PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 0x00000197, -PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 0x00000198, -PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 0x00000199, -PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 0x0000019a, -PH_PERF_SEL_SC3_PA2_FIFO_FULL = 0x0000019b, -PH_PERF_SEL_SC3_PA2_NULL_WE = 0x0000019c, -PH_PERF_SEL_SC3_PA2_EVENT_WE = 0x0000019d, -PH_PERF_SEL_SC3_PA2_FPOV_WE = 0x0000019e, -PH_PERF_SEL_SC3_PA2_LPOV_WE = 0x0000019f, -PH_PERF_SEL_SC3_PA2_EOP_WE = 0x000001a0, -PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1, -PH_PERF_SEL_SC3_PA2_EOPG_WE = 0x000001a2, -PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 0x000001a3, -PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 0x000001a4, -PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 0x000001a5, -PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 0x000001a6, -PH_PERF_SEL_SC3_PA3_FIFO_FULL = 0x000001a7, -PH_PERF_SEL_SC3_PA3_NULL_WE = 0x000001a8, -PH_PERF_SEL_SC3_PA3_EVENT_WE = 0x000001a9, -PH_PERF_SEL_SC3_PA3_FPOV_WE = 0x000001aa, -PH_PERF_SEL_SC3_PA3_LPOV_WE = 0x000001ab, -PH_PERF_SEL_SC3_PA3_EOP_WE = 0x000001ac, -PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad, -PH_PERF_SEL_SC3_PA3_EOPG_WE = 0x000001ae, -PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 0x000001af, -PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 0x000001b0, -PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 0x000001b1, -PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 0x000001b2, -PH_PERF_SEL_SC3_PA4_FIFO_FULL = 0x000001b3, -PH_PERF_SEL_SC3_PA4_NULL_WE = 0x000001b4, -PH_PERF_SEL_SC3_PA4_EVENT_WE = 0x000001b5, -PH_PERF_SEL_SC3_PA4_FPOV_WE = 0x000001b6, -PH_PERF_SEL_SC3_PA4_LPOV_WE = 0x000001b7, -PH_PERF_SEL_SC3_PA4_EOP_WE = 0x000001b8, -PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9, -PH_PERF_SEL_SC3_PA4_EOPG_WE = 0x000001ba, -PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 0x000001bb, -PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 0x000001bc, -PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 0x000001bd, -PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 0x000001be, -PH_PERF_SEL_SC3_PA5_FIFO_FULL = 0x000001bf, -PH_PERF_SEL_SC3_PA5_NULL_WE = 0x000001c0, -PH_PERF_SEL_SC3_PA5_EVENT_WE = 0x000001c1, -PH_PERF_SEL_SC3_PA5_FPOV_WE = 0x000001c2, -PH_PERF_SEL_SC3_PA5_LPOV_WE = 0x000001c3, -PH_PERF_SEL_SC3_PA5_EOP_WE = 0x000001c4, -PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5, -PH_PERF_SEL_SC3_PA5_EOPG_WE = 0x000001c6, -PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 0x000001c7, -PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 0x000001c8, -PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 0x000001c9, -PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 0x000001ca, -PH_PERF_SEL_SC3_PA6_FIFO_FULL = 0x000001cb, -PH_PERF_SEL_SC3_PA6_NULL_WE = 0x000001cc, -PH_PERF_SEL_SC3_PA6_EVENT_WE = 0x000001cd, -PH_PERF_SEL_SC3_PA6_FPOV_WE = 0x000001ce, -PH_PERF_SEL_SC3_PA6_LPOV_WE = 0x000001cf, -PH_PERF_SEL_SC3_PA6_EOP_WE = 0x000001d0, -PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1, -PH_PERF_SEL_SC3_PA6_EOPG_WE = 0x000001d2, -PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 0x000001d3, -PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 0x000001d4, -PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 0x000001d5, -PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 0x000001d6, -PH_PERF_SEL_SC3_PA7_FIFO_FULL = 0x000001d7, -PH_PERF_SEL_SC3_PA7_NULL_WE = 0x000001d8, -PH_PERF_SEL_SC3_PA7_EVENT_WE = 0x000001d9, -PH_PERF_SEL_SC3_PA7_FPOV_WE = 0x000001da, -PH_PERF_SEL_SC3_PA7_LPOV_WE = 0x000001db, -PH_PERF_SEL_SC3_PA7_EOP_WE = 0x000001dc, -PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd, -PH_PERF_SEL_SC3_PA7_EOPG_WE = 0x000001de, -PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 0x000001df, -PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 0x000001e0, -PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1, -PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2, -PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3, -PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4, -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5, -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6, -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7, -PH_PERF_SEL_SC4_ARB_BUSY = 0x000001e8, -PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 0x000001e9, -PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea, -PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 0x000001eb, -PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec, -PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 0x000001ed, -PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee, -PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef, -PH_PERF_SEL_SC4_SEND = 0x000001f0, -PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1, -PH_PERF_SEL_SC4_CREDIT_AT_MAX = 0x000001f2, -PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3, -PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4, -PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5, -PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6, -PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7, -PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 0x000001f8, -PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 0x000001f9, -PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 0x000001fa, -PH_PERF_SEL_SC4_PA0_FIFO_FULL = 0x000001fb, -PH_PERF_SEL_SC4_PA0_NULL_WE = 0x000001fc, -PH_PERF_SEL_SC4_PA0_EVENT_WE = 0x000001fd, -PH_PERF_SEL_SC4_PA0_FPOV_WE = 0x000001fe, -PH_PERF_SEL_SC4_PA0_LPOV_WE = 0x000001ff, -PH_PERF_SEL_SC4_PA0_EOP_WE = 0x00000200, -PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201, -PH_PERF_SEL_SC4_PA0_EOPG_WE = 0x00000202, -PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 0x00000203, -PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 0x00000204, -PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 0x00000205, -PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 0x00000206, -PH_PERF_SEL_SC4_PA1_FIFO_FULL = 0x00000207, -PH_PERF_SEL_SC4_PA1_NULL_WE = 0x00000208, -PH_PERF_SEL_SC4_PA1_EVENT_WE = 0x00000209, -PH_PERF_SEL_SC4_PA1_FPOV_WE = 0x0000020a, -PH_PERF_SEL_SC4_PA1_LPOV_WE = 0x0000020b, -PH_PERF_SEL_SC4_PA1_EOP_WE = 0x0000020c, -PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d, -PH_PERF_SEL_SC4_PA1_EOPG_WE = 0x0000020e, -PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 0x0000020f, -PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 0x00000210, -PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 0x00000211, -PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 0x00000212, -PH_PERF_SEL_SC4_PA2_FIFO_FULL = 0x00000213, -PH_PERF_SEL_SC4_PA2_NULL_WE = 0x00000214, -PH_PERF_SEL_SC4_PA2_EVENT_WE = 0x00000215, -PH_PERF_SEL_SC4_PA2_FPOV_WE = 0x00000216, -PH_PERF_SEL_SC4_PA2_LPOV_WE = 0x00000217, -PH_PERF_SEL_SC4_PA2_EOP_WE = 0x00000218, -PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219, -PH_PERF_SEL_SC4_PA2_EOPG_WE = 0x0000021a, -PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 0x0000021b, -PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 0x0000021c, -PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 0x0000021d, -PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 0x0000021e, -PH_PERF_SEL_SC4_PA3_FIFO_FULL = 0x0000021f, -PH_PERF_SEL_SC4_PA3_NULL_WE = 0x00000220, -PH_PERF_SEL_SC4_PA3_EVENT_WE = 0x00000221, -PH_PERF_SEL_SC4_PA3_FPOV_WE = 0x00000222, -PH_PERF_SEL_SC4_PA3_LPOV_WE = 0x00000223, -PH_PERF_SEL_SC4_PA3_EOP_WE = 0x00000224, -PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225, -PH_PERF_SEL_SC4_PA3_EOPG_WE = 0x00000226, -PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 0x00000227, -PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 0x00000228, -PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 0x00000229, -PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 0x0000022a, -PH_PERF_SEL_SC4_PA4_FIFO_FULL = 0x0000022b, -PH_PERF_SEL_SC4_PA4_NULL_WE = 0x0000022c, -PH_PERF_SEL_SC4_PA4_EVENT_WE = 0x0000022d, -PH_PERF_SEL_SC4_PA4_FPOV_WE = 0x0000022e, -PH_PERF_SEL_SC4_PA4_LPOV_WE = 0x0000022f, -PH_PERF_SEL_SC4_PA4_EOP_WE = 0x00000230, -PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231, -PH_PERF_SEL_SC4_PA4_EOPG_WE = 0x00000232, -PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 0x00000233, -PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 0x00000234, -PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 0x00000235, -PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 0x00000236, -PH_PERF_SEL_SC4_PA5_FIFO_FULL = 0x00000237, -PH_PERF_SEL_SC4_PA5_NULL_WE = 0x00000238, -PH_PERF_SEL_SC4_PA5_EVENT_WE = 0x00000239, -PH_PERF_SEL_SC4_PA5_FPOV_WE = 0x0000023a, -PH_PERF_SEL_SC4_PA5_LPOV_WE = 0x0000023b, -PH_PERF_SEL_SC4_PA5_EOP_WE = 0x0000023c, -PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d, -PH_PERF_SEL_SC4_PA5_EOPG_WE = 0x0000023e, -PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 0x0000023f, -PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 0x00000240, -PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 0x00000241, -PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 0x00000242, -PH_PERF_SEL_SC4_PA6_FIFO_FULL = 0x00000243, -PH_PERF_SEL_SC4_PA6_NULL_WE = 0x00000244, -PH_PERF_SEL_SC4_PA6_EVENT_WE = 0x00000245, -PH_PERF_SEL_SC4_PA6_FPOV_WE = 0x00000246, -PH_PERF_SEL_SC4_PA6_LPOV_WE = 0x00000247, -PH_PERF_SEL_SC4_PA6_EOP_WE = 0x00000248, -PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249, -PH_PERF_SEL_SC4_PA6_EOPG_WE = 0x0000024a, -PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 0x0000024b, -PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 0x0000024c, -PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 0x0000024d, -PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 0x0000024e, -PH_PERF_SEL_SC4_PA7_FIFO_FULL = 0x0000024f, -PH_PERF_SEL_SC4_PA7_NULL_WE = 0x00000250, -PH_PERF_SEL_SC4_PA7_EVENT_WE = 0x00000251, -PH_PERF_SEL_SC4_PA7_FPOV_WE = 0x00000252, -PH_PERF_SEL_SC4_PA7_LPOV_WE = 0x00000253, -PH_PERF_SEL_SC4_PA7_EOP_WE = 0x00000254, -PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255, -PH_PERF_SEL_SC4_PA7_EOPG_WE = 0x00000256, -PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 0x00000257, -PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 0x00000258, -PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259, -PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a, -PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b, -PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c, -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d, -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e, -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f, -PH_PERF_SEL_SC5_ARB_BUSY = 0x00000260, -PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 0x00000261, -PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262, -PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 0x00000263, -PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264, -PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 0x00000265, -PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266, -PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 0x00000267, -PH_PERF_SEL_SC5_SEND = 0x00000268, -PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269, -PH_PERF_SEL_SC5_CREDIT_AT_MAX = 0x0000026a, -PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b, -PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c, -PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d, -PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e, -PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f, -PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 0x00000270, -PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 0x00000271, -PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 0x00000272, -PH_PERF_SEL_SC5_PA0_FIFO_FULL = 0x00000273, -PH_PERF_SEL_SC5_PA0_NULL_WE = 0x00000274, -PH_PERF_SEL_SC5_PA0_EVENT_WE = 0x00000275, -PH_PERF_SEL_SC5_PA0_FPOV_WE = 0x00000276, -PH_PERF_SEL_SC5_PA0_LPOV_WE = 0x00000277, -PH_PERF_SEL_SC5_PA0_EOP_WE = 0x00000278, -PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279, -PH_PERF_SEL_SC5_PA0_EOPG_WE = 0x0000027a, -PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 0x0000027b, -PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 0x0000027c, -PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 0x0000027d, -PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 0x0000027e, -PH_PERF_SEL_SC5_PA1_FIFO_FULL = 0x0000027f, -PH_PERF_SEL_SC5_PA1_NULL_WE = 0x00000280, -PH_PERF_SEL_SC5_PA1_EVENT_WE = 0x00000281, -PH_PERF_SEL_SC5_PA1_FPOV_WE = 0x00000282, -PH_PERF_SEL_SC5_PA1_LPOV_WE = 0x00000283, -PH_PERF_SEL_SC5_PA1_EOP_WE = 0x00000284, -PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285, -PH_PERF_SEL_SC5_PA1_EOPG_WE = 0x00000286, -PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 0x00000287, -PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 0x00000288, -PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 0x00000289, -PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 0x0000028a, -PH_PERF_SEL_SC5_PA2_FIFO_FULL = 0x0000028b, -PH_PERF_SEL_SC5_PA2_NULL_WE = 0x0000028c, -PH_PERF_SEL_SC5_PA2_EVENT_WE = 0x0000028d, -PH_PERF_SEL_SC5_PA2_FPOV_WE = 0x0000028e, -PH_PERF_SEL_SC5_PA2_LPOV_WE = 0x0000028f, -PH_PERF_SEL_SC5_PA2_EOP_WE = 0x00000290, -PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291, -PH_PERF_SEL_SC5_PA2_EOPG_WE = 0x00000292, -PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 0x00000293, -PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 0x00000294, -PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 0x00000295, -PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 0x00000296, -PH_PERF_SEL_SC5_PA3_FIFO_FULL = 0x00000297, -PH_PERF_SEL_SC5_PA3_NULL_WE = 0x00000298, -PH_PERF_SEL_SC5_PA3_EVENT_WE = 0x00000299, -PH_PERF_SEL_SC5_PA3_FPOV_WE = 0x0000029a, -PH_PERF_SEL_SC5_PA3_LPOV_WE = 0x0000029b, -PH_PERF_SEL_SC5_PA3_EOP_WE = 0x0000029c, -PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d, -PH_PERF_SEL_SC5_PA3_EOPG_WE = 0x0000029e, -PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 0x0000029f, -PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 0x000002a0, -PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 0x000002a1, -PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 0x000002a2, -PH_PERF_SEL_SC5_PA4_FIFO_FULL = 0x000002a3, -PH_PERF_SEL_SC5_PA4_NULL_WE = 0x000002a4, -PH_PERF_SEL_SC5_PA4_EVENT_WE = 0x000002a5, -PH_PERF_SEL_SC5_PA4_FPOV_WE = 0x000002a6, -PH_PERF_SEL_SC5_PA4_LPOV_WE = 0x000002a7, -PH_PERF_SEL_SC5_PA4_EOP_WE = 0x000002a8, -PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9, -PH_PERF_SEL_SC5_PA4_EOPG_WE = 0x000002aa, -PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 0x000002ab, -PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 0x000002ac, -PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 0x000002ad, -PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 0x000002ae, -PH_PERF_SEL_SC5_PA5_FIFO_FULL = 0x000002af, -PH_PERF_SEL_SC5_PA5_NULL_WE = 0x000002b0, -PH_PERF_SEL_SC5_PA5_EVENT_WE = 0x000002b1, -PH_PERF_SEL_SC5_PA5_FPOV_WE = 0x000002b2, -PH_PERF_SEL_SC5_PA5_LPOV_WE = 0x000002b3, -PH_PERF_SEL_SC5_PA5_EOP_WE = 0x000002b4, -PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5, -PH_PERF_SEL_SC5_PA5_EOPG_WE = 0x000002b6, -PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 0x000002b7, -PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 0x000002b8, -PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 0x000002b9, -PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 0x000002ba, -PH_PERF_SEL_SC5_PA6_FIFO_FULL = 0x000002bb, -PH_PERF_SEL_SC5_PA6_NULL_WE = 0x000002bc, -PH_PERF_SEL_SC5_PA6_EVENT_WE = 0x000002bd, -PH_PERF_SEL_SC5_PA6_FPOV_WE = 0x000002be, -PH_PERF_SEL_SC5_PA6_LPOV_WE = 0x000002bf, -PH_PERF_SEL_SC5_PA6_EOP_WE = 0x000002c0, -PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1, -PH_PERF_SEL_SC5_PA6_EOPG_WE = 0x000002c2, -PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 0x000002c3, -PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 0x000002c4, -PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 0x000002c5, -PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 0x000002c6, -PH_PERF_SEL_SC5_PA7_FIFO_FULL = 0x000002c7, -PH_PERF_SEL_SC5_PA7_NULL_WE = 0x000002c8, -PH_PERF_SEL_SC5_PA7_EVENT_WE = 0x000002c9, -PH_PERF_SEL_SC5_PA7_FPOV_WE = 0x000002ca, -PH_PERF_SEL_SC5_PA7_LPOV_WE = 0x000002cb, -PH_PERF_SEL_SC5_PA7_EOP_WE = 0x000002cc, -PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd, -PH_PERF_SEL_SC5_PA7_EOPG_WE = 0x000002ce, -PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 0x000002cf, -PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 0x000002d0, -PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1, -PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2, -PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3, -PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4, -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5, -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6, -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7, -PH_PERF_SEL_SC6_ARB_BUSY = 0x000002d8, -PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 0x000002d9, -PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da, -PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 0x000002db, -PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc, -PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 0x000002dd, -PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de, -PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 0x000002df, -PH_PERF_SEL_SC6_SEND = 0x000002e0, -PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1, -PH_PERF_SEL_SC6_CREDIT_AT_MAX = 0x000002e2, -PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3, -PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4, -PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5, -PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6, -PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7, -PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 0x000002e8, -PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 0x000002e9, -PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 0x000002ea, -PH_PERF_SEL_SC6_PA0_FIFO_FULL = 0x000002eb, -PH_PERF_SEL_SC6_PA0_NULL_WE = 0x000002ec, -PH_PERF_SEL_SC6_PA0_EVENT_WE = 0x000002ed, -PH_PERF_SEL_SC6_PA0_FPOV_WE = 0x000002ee, -PH_PERF_SEL_SC6_PA0_LPOV_WE = 0x000002ef, -PH_PERF_SEL_SC6_PA0_EOP_WE = 0x000002f0, -PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1, -PH_PERF_SEL_SC6_PA0_EOPG_WE = 0x000002f2, -PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 0x000002f3, -PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 0x000002f4, -PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 0x000002f5, -PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 0x000002f6, -PH_PERF_SEL_SC6_PA1_FIFO_FULL = 0x000002f7, -PH_PERF_SEL_SC6_PA1_NULL_WE = 0x000002f8, -PH_PERF_SEL_SC6_PA1_EVENT_WE = 0x000002f9, -PH_PERF_SEL_SC6_PA1_FPOV_WE = 0x000002fa, -PH_PERF_SEL_SC6_PA1_LPOV_WE = 0x000002fb, -PH_PERF_SEL_SC6_PA1_EOP_WE = 0x000002fc, -PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd, -PH_PERF_SEL_SC6_PA1_EOPG_WE = 0x000002fe, -PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 0x000002ff, -PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 0x00000300, -PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 0x00000301, -PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 0x00000302, -PH_PERF_SEL_SC6_PA2_FIFO_FULL = 0x00000303, -PH_PERF_SEL_SC6_PA2_NULL_WE = 0x00000304, -PH_PERF_SEL_SC6_PA2_EVENT_WE = 0x00000305, -PH_PERF_SEL_SC6_PA2_FPOV_WE = 0x00000306, -PH_PERF_SEL_SC6_PA2_LPOV_WE = 0x00000307, -PH_PERF_SEL_SC6_PA2_EOP_WE = 0x00000308, -PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309, -PH_PERF_SEL_SC6_PA2_EOPG_WE = 0x0000030a, -PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 0x0000030b, -PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 0x0000030c, -PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 0x0000030d, -PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 0x0000030e, -PH_PERF_SEL_SC6_PA3_FIFO_FULL = 0x0000030f, -PH_PERF_SEL_SC6_PA3_NULL_WE = 0x00000310, -PH_PERF_SEL_SC6_PA3_EVENT_WE = 0x00000311, -PH_PERF_SEL_SC6_PA3_FPOV_WE = 0x00000312, -PH_PERF_SEL_SC6_PA3_LPOV_WE = 0x00000313, -PH_PERF_SEL_SC6_PA3_EOP_WE = 0x00000314, -PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315, -PH_PERF_SEL_SC6_PA3_EOPG_WE = 0x00000316, -PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 0x00000317, -PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 0x00000318, -PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 0x00000319, -PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 0x0000031a, -PH_PERF_SEL_SC6_PA4_FIFO_FULL = 0x0000031b, -PH_PERF_SEL_SC6_PA4_NULL_WE = 0x0000031c, -PH_PERF_SEL_SC6_PA4_EVENT_WE = 0x0000031d, -PH_PERF_SEL_SC6_PA4_FPOV_WE = 0x0000031e, -PH_PERF_SEL_SC6_PA4_LPOV_WE = 0x0000031f, -PH_PERF_SEL_SC6_PA4_EOP_WE = 0x00000320, -PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321, -PH_PERF_SEL_SC6_PA4_EOPG_WE = 0x00000322, -PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 0x00000323, -PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 0x00000324, -PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 0x00000325, -PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 0x00000326, -PH_PERF_SEL_SC6_PA5_FIFO_FULL = 0x00000327, -PH_PERF_SEL_SC6_PA5_NULL_WE = 0x00000328, -PH_PERF_SEL_SC6_PA5_EVENT_WE = 0x00000329, -PH_PERF_SEL_SC6_PA5_FPOV_WE = 0x0000032a, -PH_PERF_SEL_SC6_PA5_LPOV_WE = 0x0000032b, -PH_PERF_SEL_SC6_PA5_EOP_WE = 0x0000032c, -PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d, -PH_PERF_SEL_SC6_PA5_EOPG_WE = 0x0000032e, -PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 0x0000032f, -PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 0x00000330, -PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 0x00000331, -PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 0x00000332, -PH_PERF_SEL_SC6_PA6_FIFO_FULL = 0x00000333, -PH_PERF_SEL_SC6_PA6_NULL_WE = 0x00000334, -PH_PERF_SEL_SC6_PA6_EVENT_WE = 0x00000335, -PH_PERF_SEL_SC6_PA6_FPOV_WE = 0x00000336, -PH_PERF_SEL_SC6_PA6_LPOV_WE = 0x00000337, -PH_PERF_SEL_SC6_PA6_EOP_WE = 0x00000338, -PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339, -PH_PERF_SEL_SC6_PA6_EOPG_WE = 0x0000033a, -PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 0x0000033b, -PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 0x0000033c, -PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 0x0000033d, -PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 0x0000033e, -PH_PERF_SEL_SC6_PA7_FIFO_FULL = 0x0000033f, -PH_PERF_SEL_SC6_PA7_NULL_WE = 0x00000340, -PH_PERF_SEL_SC6_PA7_EVENT_WE = 0x00000341, -PH_PERF_SEL_SC6_PA7_FPOV_WE = 0x00000342, -PH_PERF_SEL_SC6_PA7_LPOV_WE = 0x00000343, -PH_PERF_SEL_SC6_PA7_EOP_WE = 0x00000344, -PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345, -PH_PERF_SEL_SC6_PA7_EOPG_WE = 0x00000346, -PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 0x00000347, -PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 0x00000348, -PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349, -PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a, -PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b, -PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c, -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d, -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e, -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f, -PH_PERF_SEL_SC7_ARB_BUSY = 0x00000350, -PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 0x00000351, -PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352, -PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 0x00000353, -PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354, -PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 0x00000355, -PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356, -PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 0x00000357, -PH_PERF_SEL_SC7_SEND = 0x00000358, -PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359, -PH_PERF_SEL_SC7_CREDIT_AT_MAX = 0x0000035a, -PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b, -PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c, -PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d, -PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e, -PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f, -PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 0x00000360, -PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 0x00000361, -PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 0x00000362, -PH_PERF_SEL_SC7_PA0_FIFO_FULL = 0x00000363, -PH_PERF_SEL_SC7_PA0_NULL_WE = 0x00000364, -PH_PERF_SEL_SC7_PA0_EVENT_WE = 0x00000365, -PH_PERF_SEL_SC7_PA0_FPOV_WE = 0x00000366, -PH_PERF_SEL_SC7_PA0_LPOV_WE = 0x00000367, -PH_PERF_SEL_SC7_PA0_EOP_WE = 0x00000368, -PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369, -PH_PERF_SEL_SC7_PA0_EOPG_WE = 0x0000036a, -PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 0x0000036b, -PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 0x0000036c, -PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 0x0000036d, -PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 0x0000036e, -PH_PERF_SEL_SC7_PA1_FIFO_FULL = 0x0000036f, -PH_PERF_SEL_SC7_PA1_NULL_WE = 0x00000370, -PH_PERF_SEL_SC7_PA1_EVENT_WE = 0x00000371, -PH_PERF_SEL_SC7_PA1_FPOV_WE = 0x00000372, -PH_PERF_SEL_SC7_PA1_LPOV_WE = 0x00000373, -PH_PERF_SEL_SC7_PA1_EOP_WE = 0x00000374, -PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375, -PH_PERF_SEL_SC7_PA1_EOPG_WE = 0x00000376, -PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 0x00000377, -PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 0x00000378, -PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 0x00000379, -PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 0x0000037a, -PH_PERF_SEL_SC7_PA2_FIFO_FULL = 0x0000037b, -PH_PERF_SEL_SC7_PA2_NULL_WE = 0x0000037c, -PH_PERF_SEL_SC7_PA2_EVENT_WE = 0x0000037d, -PH_PERF_SEL_SC7_PA2_FPOV_WE = 0x0000037e, -PH_PERF_SEL_SC7_PA2_LPOV_WE = 0x0000037f, -PH_PERF_SEL_SC7_PA2_EOP_WE = 0x00000380, -PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381, -PH_PERF_SEL_SC7_PA2_EOPG_WE = 0x00000382, -PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 0x00000383, -PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 0x00000384, -PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 0x00000385, -PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 0x00000386, -PH_PERF_SEL_SC7_PA3_FIFO_FULL = 0x00000387, -PH_PERF_SEL_SC7_PA3_NULL_WE = 0x00000388, -PH_PERF_SEL_SC7_PA3_EVENT_WE = 0x00000389, -PH_PERF_SEL_SC7_PA3_FPOV_WE = 0x0000038a, -PH_PERF_SEL_SC7_PA3_LPOV_WE = 0x0000038b, -PH_PERF_SEL_SC7_PA3_EOP_WE = 0x0000038c, -PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d, -PH_PERF_SEL_SC7_PA3_EOPG_WE = 0x0000038e, -PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 0x0000038f, -PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 0x00000390, -PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 0x00000391, -PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 0x00000392, -PH_PERF_SEL_SC7_PA4_FIFO_FULL = 0x00000393, -PH_PERF_SEL_SC7_PA4_NULL_WE = 0x00000394, -PH_PERF_SEL_SC7_PA4_EVENT_WE = 0x00000395, -PH_PERF_SEL_SC7_PA4_FPOV_WE = 0x00000396, -PH_PERF_SEL_SC7_PA4_LPOV_WE = 0x00000397, -PH_PERF_SEL_SC7_PA4_EOP_WE = 0x00000398, -PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399, -PH_PERF_SEL_SC7_PA4_EOPG_WE = 0x0000039a, -PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 0x0000039b, -PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 0x0000039c, -PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 0x0000039d, -PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 0x0000039e, -PH_PERF_SEL_SC7_PA5_FIFO_FULL = 0x0000039f, -PH_PERF_SEL_SC7_PA5_NULL_WE = 0x000003a0, -PH_PERF_SEL_SC7_PA5_EVENT_WE = 0x000003a1, -PH_PERF_SEL_SC7_PA5_FPOV_WE = 0x000003a2, -PH_PERF_SEL_SC7_PA5_LPOV_WE = 0x000003a3, -PH_PERF_SEL_SC7_PA5_EOP_WE = 0x000003a4, -PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5, -PH_PERF_SEL_SC7_PA5_EOPG_WE = 0x000003a6, -PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 0x000003a7, -PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 0x000003a8, -PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 0x000003a9, -PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 0x000003aa, -PH_PERF_SEL_SC7_PA6_FIFO_FULL = 0x000003ab, -PH_PERF_SEL_SC7_PA6_NULL_WE = 0x000003ac, -PH_PERF_SEL_SC7_PA6_EVENT_WE = 0x000003ad, -PH_PERF_SEL_SC7_PA6_FPOV_WE = 0x000003ae, -PH_PERF_SEL_SC7_PA6_LPOV_WE = 0x000003af, -PH_PERF_SEL_SC7_PA6_EOP_WE = 0x000003b0, -PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1, -PH_PERF_SEL_SC7_PA6_EOPG_WE = 0x000003b2, -PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 0x000003b3, -PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 0x000003b4, -PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 0x000003b5, -PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 0x000003b6, -PH_PERF_SEL_SC7_PA7_FIFO_FULL = 0x000003b7, -PH_PERF_SEL_SC7_PA7_NULL_WE = 0x000003b8, -PH_PERF_SEL_SC7_PA7_EVENT_WE = 0x000003b9, -PH_PERF_SEL_SC7_PA7_FPOV_WE = 0x000003ba, -PH_PERF_SEL_SC7_PA7_LPOV_WE = 0x000003bb, -PH_PERF_SEL_SC7_PA7_EOP_WE = 0x000003bc, -PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd, -PH_PERF_SEL_SC7_PA7_EOPG_WE = 0x000003be, -PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 0x000003bf, -PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 0x000003c0, -PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 0x000003c1, -PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 0x000003c2, -PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 0x000003c3, -PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 0x000003c4, -PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 0x000003c5, -PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 0x000003c6, -PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 0x000003c7, -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 0x000003c8, -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 0x000003c9, -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 0x000003ca, -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 0x000003cb, -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 0x000003cc, -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 0x000003cd, -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 0x000003ce, -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 0x000003cf, -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0, -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1, -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2, -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3, -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4, -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5, -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6, -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7, -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8, -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9, -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da, -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db, -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc, -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd, -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de, -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df, -PH_PERF_SC0_FIFO_STATUS_0 = 0x000003e0, -PH_PERF_SC0_FIFO_STATUS_1 = 0x000003e1, -PH_PERF_SC0_FIFO_STATUS_2 = 0x000003e2, -PH_PERF_SC0_FIFO_STATUS_3 = 0x000003e3, -PH_PERF_SC1_FIFO_STATUS_0 = 0x000003e4, -PH_PERF_SC1_FIFO_STATUS_1 = 0x000003e5, -PH_PERF_SC1_FIFO_STATUS_2 = 0x000003e6, -PH_PERF_SC1_FIFO_STATUS_3 = 0x000003e7, -PH_PERF_SC2_FIFO_STATUS_0 = 0x000003e8, -PH_PERF_SC2_FIFO_STATUS_1 = 0x000003e9, -PH_PERF_SC2_FIFO_STATUS_2 = 0x000003ea, -PH_PERF_SC2_FIFO_STATUS_3 = 0x000003eb, -PH_PERF_SC3_FIFO_STATUS_0 = 0x000003ec, -PH_PERF_SC3_FIFO_STATUS_1 = 0x000003ed, -PH_PERF_SC3_FIFO_STATUS_2 = 0x000003ee, -PH_PERF_SC3_FIFO_STATUS_3 = 0x000003ef, -PH_PERF_SC4_FIFO_STATUS_0 = 0x000003f0, -PH_PERF_SC4_FIFO_STATUS_1 = 0x000003f1, -PH_PERF_SC4_FIFO_STATUS_2 = 0x000003f2, -PH_PERF_SC4_FIFO_STATUS_3 = 0x000003f3, -PH_PERF_SC5_FIFO_STATUS_0 = 0x000003f4, -PH_PERF_SC5_FIFO_STATUS_1 = 0x000003f5, -PH_PERF_SC5_FIFO_STATUS_2 = 0x000003f6, -PH_PERF_SC5_FIFO_STATUS_3 = 0x000003f7, -PH_PERF_SC6_FIFO_STATUS_0 = 0x000003f8, -PH_PERF_SC6_FIFO_STATUS_1 = 0x000003f9, -PH_PERF_SC6_FIFO_STATUS_2 = 0x000003fa, -PH_PERF_SC6_FIFO_STATUS_3 = 0x000003fb, -PH_PERF_SC7_FIFO_STATUS_0 = 0x000003fc, -PH_PERF_SC7_FIFO_STATUS_1 = 0x000003fd, -PH_PERF_SC7_FIFO_STATUS_2 = 0x000003fe, -PH_PERF_SC7_FIFO_STATUS_3 = 0x000003ff, -} PH_PERFCNT_SEL; - -/* - * PhSPIstatusMode enum - */ - -typedef enum PhSPIstatusMode { -PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0x00000000, -PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001, -PH_SPI_MODE_DISABLED = 0x00000002, -} PhSPIstatusMode; - -/******************************************************* - * RMI Enums - *******************************************************/ - -/* - * RMIPerfSel enum - */ - -typedef enum RMIPerfSel { -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000000, -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000001, -} RMIPerfSel; - -/******************************************************* - * PMM Enums - *******************************************************/ - -/* - * GCRPerfSel enum - */ - -typedef enum GCRPerfSel { -GCR_PERF_SEL_NONE = 0x00000000, -GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001, -GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002, -GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003, -GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004, -GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005, -GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006, -GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007, -GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008, -GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009, -GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a, -GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b, -GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c, -GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d, -GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e, -GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f, -GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010, -GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011, -GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012, -GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013, -GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014, -GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015, -GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016, -GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017, -GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018, -GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019, -GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a, -GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b, -GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c, -GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d, -GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e, -GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f, -GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020, -GCR_PERF_SEL_CPC_ALL_REQ = 0x00000021, -GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000022, -GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000023, -GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000024, -GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000025, -GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000026, -GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000027, -GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000028, -GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000029, -GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000002a, -GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000002b, -GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000002c, -GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000002d, -GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000002e, -GCR_PERF_SEL_CPC_TCP_REQ = 0x0000002f, -GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 0x00000030, -GCR_PERF_SEL_CPG_ALL_REQ = 0x00000031, -GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000032, -GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000033, -GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000034, -GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000035, -GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000036, -GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000037, -GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000038, -GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000039, -GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000003a, -GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000003b, -GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000003c, -GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000003d, -GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000003e, -GCR_PERF_SEL_CPG_TCP_REQ = 0x0000003f, -GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 0x00000040, -GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041, -GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042, -GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043, -GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044, -GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045, -GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046, -GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047, -GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048, -GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049, -GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a, -GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b, -GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c, -GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d, -GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e, -GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f, -GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 0x00000050, -GCR_PERF_SEL_VIRT_REQ = 0x00000051, -GCR_PERF_SEL_PHY_REQ = 0x00000052, -GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053, -GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054, -GCR_PERF_SEL_ALL_REQ = 0x00000055, -GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056, -GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057, -GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058, -GCR_PERF_SEL_UTCL2_REQ = 0x00000059, -GCR_PERF_SEL_UTCL2_RET = 0x0000005a, -GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b, -GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c, -GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d, -GCR_PERF_SEL_RLC_ALL_REQ = 0x0000005e, -GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 0x0000005f, -GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 0x00000060, -GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 0x00000061, -GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 0x00000062, -GCR_PERF_SEL_RLC_GL2_ALL_REQ = 0x00000063, -GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 0x00000064, -GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 0x00000065, -GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 0x00000066, -GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 0x00000067, -GCR_PERF_SEL_RLC_GL1_ALL_REQ = 0x00000068, -GCR_PERF_SEL_RLC_METADATA_REQ = 0x00000069, -GCR_PERF_SEL_RLC_SQC_DATA_REQ = 0x0000006a, -GCR_PERF_SEL_RLC_SQC_INST_REQ = 0x0000006b, -GCR_PERF_SEL_RLC_TCP_REQ = 0x0000006c, -GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 0x0000006d, -GCR_PERF_SEL_PM_ALL_REQ = 0x0000006e, -GCR_PERF_SEL_PM_GL2_RANGE_REQ = 0x0000006f, -GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 0x00000070, -GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 0x00000071, -GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 0x00000072, -GCR_PERF_SEL_PM_GL2_ALL_REQ = 0x00000073, -GCR_PERF_SEL_PM_GL1_RANGE_REQ = 0x00000074, -GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 0x00000075, -GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 0x00000076, -GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 0x00000077, -GCR_PERF_SEL_PM_GL1_ALL_REQ = 0x00000078, -GCR_PERF_SEL_PM_METADATA_REQ = 0x00000079, -GCR_PERF_SEL_PM_SQC_DATA_REQ = 0x0000007a, -GCR_PERF_SEL_PM_SQC_INST_REQ = 0x0000007b, -GCR_PERF_SEL_PM_TCP_REQ = 0x0000007c, -GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 0x0000007d, -GCR_PERF_SEL_PIO_ALL_REQ = 0x0000007e, -GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 0x0000007f, -GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 0x00000080, -GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 0x00000081, -GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 0x00000082, -GCR_PERF_SEL_PIO_GL2_ALL_REQ = 0x00000083, -GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 0x00000084, -GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 0x00000085, -GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 0x00000086, -GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 0x00000087, -GCR_PERF_SEL_PIO_GL1_ALL_REQ = 0x00000088, -GCR_PERF_SEL_PIO_METADATA_REQ = 0x00000089, -GCR_PERF_SEL_PIO_SQC_DATA_REQ = 0x0000008a, -GCR_PERF_SEL_PIO_SQC_INST_REQ = 0x0000008b, -GCR_PERF_SEL_PIO_TCP_REQ = 0x0000008c, -GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 0x0000008d, -} GCRPerfSel; - -/******************************************************* - * UTCL1 Enums - *******************************************************/ - -/* - * UTCL1PerfSel enum - */ - -typedef enum UTCL1PerfSel { -UTCL1_PERF_SEL_NONE = 0x00000000, -UTCL1_PERF_SEL_REQS = 0x00000001, -UTCL1_PERF_SEL_HITS = 0x00000002, -UTCL1_PERF_SEL_MISSES = 0x00000003, -UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 0x00000004, -UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 0x00000005, -UTCL1_PERF_SEL_UTCL2_REQS = 0x00000006, -UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 0x00000007, -UTCL1_PERF_SEL_UTCL2_RET_FAULT = 0x00000008, -UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 0x00000009, -UTCL1_PERF_SEL_STALL_MH_FULL = 0x0000000a, -UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b, -UTCL1_PERF_SEL_UTCL2_RET_CNT = 0x0000000c, -UTCL1_PERF_SEL_RTNS = 0x0000000d, -UTCL1_PERF_SEL_XLAT_REQ_BUSY = 0x0000000e, -UTCL1_PERF_SEL_BYPASS_REQS = 0x0000000f, -UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000010, -UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 0x00000011, -UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 0x00000012, -UTCL1_PERF_SEL_CP_INVREQS = 0x00000013, -UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 0x00000014, -UTCL1_PERF_SEL_RANGE_INVREQS = 0x00000015, -UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 0x00000016, -} UTCL1PerfSel; - -/******************************************************* - * IH Enums - *******************************************************/ - -/* - * IH_CLIENT_TYPE enum - */ - -typedef enum IH_CLIENT_TYPE { -IH_GFX_VMID_CLIENT = 0x00000000, -IH_MM_VMID_CLIENT = 0x00000001, -IH_MULTI_VMID_CLIENT = 0x00000002, -IH_CLIENT_TYPE_RESERVED = 0x00000003, -} IH_CLIENT_TYPE; - -/* - * IH_INTERFACE_TYPE enum - */ - -typedef enum IH_INTERFACE_TYPE { -IH_LEGACY_INTERFACE = 0x00000000, -IH_REGISTER_WRITE_INTERFACE = 0x00000001, -} IH_INTERFACE_TYPE; - -/* - * IH_PERF_SEL enum - */ - -typedef enum IH_PERF_SEL { -IH_PERF_SEL_CYCLE = 0x00000000, -IH_PERF_SEL_IDLE = 0x00000001, -IH_PERF_SEL_INPUT_IDLE = 0x00000002, -IH_PERF_SEL_BUFFER_IDLE = 0x00000003, -IH_PERF_SEL_RB0_FULL = 0x00000004, -IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, -IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, -IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, -IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, -IH_PERF_SEL_MC_WR_IDLE = 0x00000009, -IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, -IH_PERF_SEL_MC_WR_STALL = 0x0000000b, -IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, -IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, -IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, -IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, -IH_PERF_SEL_RB1_FULL = 0x00000010, -IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, -IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012, -IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, -IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, -IH_PERF_SEL_RB2_FULL = 0x00000015, -IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, -IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017, -IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, -IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, -IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a, -IH_PERF_SEL_SELF_IV_VALID = 0x0000001b, -IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c, -IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001d, -IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001e, -IH_PERF_SEL_RB0_FULL_VF2 = 0x0000001f, -IH_PERF_SEL_RB0_FULL_VF3 = 0x00000020, -IH_PERF_SEL_RB0_FULL_VF4 = 0x00000021, -IH_PERF_SEL_RB0_FULL_VF5 = 0x00000022, -IH_PERF_SEL_RB0_FULL_VF6 = 0x00000023, -IH_PERF_SEL_RB0_FULL_VF7 = 0x00000024, -IH_PERF_SEL_RB0_FULL_VF8 = 0x00000025, -IH_PERF_SEL_RB0_FULL_VF9 = 0x00000026, -IH_PERF_SEL_RB0_FULL_VF10 = 0x00000027, -IH_PERF_SEL_RB0_FULL_VF11 = 0x00000028, -IH_PERF_SEL_RB0_FULL_VF12 = 0x00000029, -IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002a, -IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002b, -IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002c, -IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002d, -IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002e, -IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x0000002f, -IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000030, -IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000031, -IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000032, -IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000033, -IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000034, -IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000035, -IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000036, -IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000037, -IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000038, -IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x00000039, -IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003a, -IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003b, -IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003c, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003d, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003e, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x0000003f, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000040, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000041, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000042, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000043, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000044, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000045, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000046, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000047, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000048, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x00000049, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004a, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004b, -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004c, -IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004d, -IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004e, -IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x0000004f, -IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000050, -IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000051, -IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000052, -IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000053, -IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000054, -IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000055, -IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000056, -IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000057, -IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000058, -IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x00000059, -IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005a, -IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005b, -IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005c, -IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005d, -IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005e, -IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x0000005f, -IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000060, -IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000061, -IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000062, -IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000063, -IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000064, -IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000065, -IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000066, -IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000067, -IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000068, -IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x00000069, -IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006a, -IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006b, -IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006c, -IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006d, -IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006e, -IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x0000006f, -IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000070, -IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000071, -IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000072, -IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000073, -IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000074, -IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000075, -IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000076, -IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000077, -IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000078, -IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x00000079, -IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007a, -IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007b, -IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007c, -IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007d, -IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007e, -IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x0000007f, -IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000080, -IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000081, -IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000082, -IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000083, -IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000084, -IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000085, -IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000086, -IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000087, -IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000088, -IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x00000089, -IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008a, -IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008b, -IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008c, -IH_PERF_SEL_CLIENT0_INT = 0x0000008d, -IH_PERF_SEL_CLIENT1_INT = 0x0000008e, -IH_PERF_SEL_CLIENT2_INT = 0x0000008f, -IH_PERF_SEL_CLIENT3_INT = 0x00000090, -IH_PERF_SEL_CLIENT4_INT = 0x00000091, -IH_PERF_SEL_CLIENT5_INT = 0x00000092, -IH_PERF_SEL_CLIENT6_INT = 0x00000093, -IH_PERF_SEL_CLIENT7_INT = 0x00000094, -IH_PERF_SEL_CLIENT8_INT = 0x00000095, -IH_PERF_SEL_CLIENT9_INT = 0x00000096, -IH_PERF_SEL_CLIENT10_INT = 0x00000097, -IH_PERF_SEL_CLIENT11_INT = 0x00000098, -IH_PERF_SEL_CLIENT12_INT = 0x00000099, -IH_PERF_SEL_CLIENT13_INT = 0x0000009a, -IH_PERF_SEL_CLIENT14_INT = 0x0000009b, -IH_PERF_SEL_CLIENT15_INT = 0x0000009c, -IH_PERF_SEL_CLIENT16_INT = 0x0000009d, -IH_PERF_SEL_CLIENT17_INT = 0x0000009e, -IH_PERF_SEL_CLIENT18_INT = 0x0000009f, -IH_PERF_SEL_CLIENT19_INT = 0x000000a0, -IH_PERF_SEL_CLIENT20_INT = 0x000000a1, -IH_PERF_SEL_CLIENT21_INT = 0x000000a2, -IH_PERF_SEL_CLIENT22_INT = 0x000000a3, -IH_PERF_SEL_CLIENT23_INT = 0x000000a4, -IH_PERF_SEL_CLIENT24_INT = 0x000000a5, -IH_PERF_SEL_CLIENT25_INT = 0x000000a6, -IH_PERF_SEL_CLIENT26_INT = 0x000000a7, -IH_PERF_SEL_CLIENT27_INT = 0x000000a8, -IH_PERF_SEL_CLIENT28_INT = 0x000000a9, -IH_PERF_SEL_CLIENT29_INT = 0x000000aa, -IH_PERF_SEL_CLIENT30_INT = 0x000000ab, -IH_PERF_SEL_CLIENT31_INT = 0x000000ac, -IH_PERF_SEL_RB1_FULL_VF0 = 0x000000ad, -IH_PERF_SEL_RB1_FULL_VF1 = 0x000000ae, -IH_PERF_SEL_RB1_FULL_VF2 = 0x000000af, -IH_PERF_SEL_RB1_FULL_VF3 = 0x000000b0, -IH_PERF_SEL_RB1_FULL_VF4 = 0x000000b1, -IH_PERF_SEL_RB1_FULL_VF5 = 0x000000b2, -IH_PERF_SEL_RB1_FULL_VF6 = 0x000000b3, -IH_PERF_SEL_RB1_FULL_VF7 = 0x000000b4, -IH_PERF_SEL_RB1_FULL_VF8 = 0x000000b5, -IH_PERF_SEL_RB1_FULL_VF9 = 0x000000b6, -IH_PERF_SEL_RB1_FULL_VF10 = 0x000000b7, -IH_PERF_SEL_RB1_FULL_VF11 = 0x000000b8, -IH_PERF_SEL_RB1_FULL_VF12 = 0x000000b9, -IH_PERF_SEL_RB1_FULL_VF13 = 0x000000ba, -IH_PERF_SEL_RB1_FULL_VF14 = 0x000000bb, -IH_PERF_SEL_RB1_FULL_VF15 = 0x000000bc, -IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000bd, -IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000be, -IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000bf, -IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000c0, -IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000c1, -IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000c2, -IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000c3, -IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000c4, -IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000c5, -IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000c6, -IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000c7, -IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000c8, -IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000c9, -IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000ca, -IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000cb, -IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000cc, -IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x000000cd, -IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x000000ce, -IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x000000cf, -IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x000000d0, -IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x000000d1, -IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x000000d2, -IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x000000d3, -IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x000000d4, -IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x000000d5, -IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x000000d6, -IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x000000d7, -IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x000000d8, -IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x000000d9, -IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x000000da, -IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x000000db, -IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x000000dc, -IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x000000dd, -IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x000000de, -IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x000000df, -IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x000000e0, -IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x000000e1, -IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x000000e2, -IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x000000e3, -IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x000000e4, -IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x000000e5, -IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x000000e6, -IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x000000e7, -IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x000000e8, -IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x000000e9, -IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x000000ea, -IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x000000eb, -IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x000000ec, -IH_PERF_SEL_RB2_FULL_VF0 = 0x000000ed, -IH_PERF_SEL_RB2_FULL_VF1 = 0x000000ee, -IH_PERF_SEL_RB2_FULL_VF2 = 0x000000ef, -IH_PERF_SEL_RB2_FULL_VF3 = 0x000000f0, -IH_PERF_SEL_RB2_FULL_VF4 = 0x000000f1, -IH_PERF_SEL_RB2_FULL_VF5 = 0x000000f2, -IH_PERF_SEL_RB2_FULL_VF6 = 0x000000f3, -IH_PERF_SEL_RB2_FULL_VF7 = 0x000000f4, -IH_PERF_SEL_RB2_FULL_VF8 = 0x000000f5, -IH_PERF_SEL_RB2_FULL_VF9 = 0x000000f6, -IH_PERF_SEL_RB2_FULL_VF10 = 0x000000f7, -IH_PERF_SEL_RB2_FULL_VF11 = 0x000000f8, -IH_PERF_SEL_RB2_FULL_VF12 = 0x000000f9, -IH_PERF_SEL_RB2_FULL_VF13 = 0x000000fa, -IH_PERF_SEL_RB2_FULL_VF14 = 0x000000fb, -IH_PERF_SEL_RB2_FULL_VF15 = 0x000000fc, -IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x000000fd, -IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x000000fe, -IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x000000ff, -IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x00000100, -IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000101, -IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000102, -IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000103, -IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000104, -IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000105, -IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000106, -IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000107, -IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000108, -IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000109, -IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x0000010a, -IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000010b, -IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000010c, -IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000010d, -IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000010e, -IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000010f, -IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x00000110, -IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000111, -IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000112, -IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000113, -IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000114, -IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000115, -IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000116, -IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000117, -IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000118, -IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000119, -IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x0000011a, -IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000011b, -IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000011c, -IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000011d, -IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000011e, -IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000011f, -IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x00000120, -IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000121, -IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000122, -IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000123, -IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000124, -IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000125, -IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000126, -IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000127, -IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000128, -IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000129, -IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x0000012a, -IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000012b, -IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000012c, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x0000012d, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x0000012e, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x0000012f, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000130, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x00000131, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x00000132, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x00000133, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x00000134, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x00000135, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x00000136, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000137, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000138, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x00000139, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x0000013a, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x0000013b, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x0000013c, -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x0000013d, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x0000013e, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x0000013f, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x00000140, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x00000141, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x00000142, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x00000143, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x00000144, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x00000145, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000146, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000147, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000148, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000149, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x0000014a, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x0000014b, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x0000014c, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x0000014d, -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x0000014e, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000014f, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x00000150, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x00000151, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x00000152, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x00000153, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x00000154, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000155, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000156, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000157, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000158, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000159, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x0000015a, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x0000015b, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x0000015c, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x0000015d, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x0000015e, -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000015f, -IH_PERF_SEL_RB0_LOAD_RPTR = 0x00000160, -IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 0x00000161, -IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 0x00000162, -IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 0x00000163, -IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 0x00000164, -IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 0x00000165, -IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 0x00000166, -IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 0x00000167, -IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 0x00000168, -IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 0x00000169, -IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 0x0000016a, -IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 0x0000016b, -IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 0x0000016c, -IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 0x0000016d, -IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 0x0000016e, -IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 0x0000016f, -IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 0x00000170, -IH_PERF_SEL_RB1_LOAD_RPTR = 0x00000171, -IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 0x00000172, -IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 0x00000173, -IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 0x00000174, -IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 0x00000175, -IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 0x00000176, -IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 0x00000177, -IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 0x00000178, -IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 0x00000179, -IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 0x0000017a, -IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 0x0000017b, -IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 0x0000017c, -IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 0x0000017d, -IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 0x0000017e, -IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 0x0000017f, -IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 0x00000180, -IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 0x00000181, -IH_PERF_SEL_RB2_LOAD_RPTR = 0x00000182, -IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 0x00000183, -IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 0x00000184, -IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 0x00000185, -IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 0x00000186, -IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 0x00000187, -IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 0x00000188, -IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 0x00000189, -IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 0x0000018a, -IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 0x0000018b, -IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 0x0000018c, -IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 0x0000018d, -IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 0x0000018e, -IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 0x0000018f, -IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 0x00000190, -IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 0x00000191, -IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 0x00000192, -} IH_PERF_SEL; - -/* - * IH_RING_ID enum - */ - -typedef enum IH_RING_ID { -IH_RING_ID_INTERRUPT = 0x00000000, -IH_RING_ID_REQUEST = 0x00000001, -IH_RING_ID_TRANSLATION = 0x00000002, -IH_RING_ID_RESERVED = 0x00000003, -} IH_RING_ID; - -/* - * IH_VF_RB_SELECT enum - */ - -typedef enum IH_VF_RB_SELECT { -IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000, -IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001, -IH_VF_RB_SELECT_PF = 0x00000002, -IH_VF_RB_SELECT_RESERVED = 0x00000003, -} IH_VF_RB_SELECT; - -/******************************************************* - * SEM Enums - *******************************************************/ - -/* - * SEM_PERF_SEL enum - */ - -typedef enum SEM_PERF_SEL { -SEM_PERF_SEL_CYCLE = 0x00000000, -SEM_PERF_SEL_IDLE = 0x00000001, -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, -SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 0x00000004, -SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 0x00000005, -SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000006, -SEM_PERF_SEL_UVD1_REQ_SIGNAL = 0x00000007, -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000008, -SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000009, -SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x0000000a, -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x0000000b, -SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x0000000c, -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000d, -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000e, -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000f, -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x00000010, -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x00000011, -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x00000012, -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000013, -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000014, -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000015, -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000016, -SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000017, -SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000018, -SEM_PERF_SEL_SDMA2_REQ_WAIT = 0x00000019, -SEM_PERF_SEL_SDMA3_REQ_WAIT = 0x0000001a, -SEM_PERF_SEL_UVD_REQ_WAIT = 0x0000001b, -SEM_PERF_SEL_UVD1_REQ_WAIT = 0x0000001c, -SEM_PERF_SEL_VCE0_REQ_WAIT = 0x0000001d, -SEM_PERF_SEL_ACP_REQ_WAIT = 0x0000001e, -SEM_PERF_SEL_ISP_REQ_WAIT = 0x0000001f, -SEM_PERF_SEL_VCE1_REQ_WAIT = 0x00000020, -SEM_PERF_SEL_VP8_REQ_WAIT = 0x00000021, -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x00000022, -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x00000023, -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x00000024, -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x00000025, -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000026, -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000027, -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000028, -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000029, -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x0000002a, -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x0000002b, -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x0000002c, -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x0000002d, -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x0000002e, -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x0000002f, -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x00000030, -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x00000031, -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x00000032, -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x00000033, -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x00000034, -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x00000035, -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000036, -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000037, -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000038, -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000039, -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x0000003a, -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x0000003b, -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x0000003c, -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x0000003d, -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x0000003e, -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x0000003f, -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x00000040, -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x00000041, -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x00000042, -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x00000043, -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x00000044, -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x00000045, -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000046, -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000047, -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000048, -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000049, -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x0000004a, -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x0000004b, -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x0000004c, -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x0000004d, -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x0000004e, -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x0000004f, -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x00000050, -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x00000051, -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x00000052, -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x00000053, -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x00000054, -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x00000055, -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000056, -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000057, -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000058, -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000059, -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x0000005a, -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x0000005b, -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x0000005c, -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x0000005d, -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x0000005e, -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x0000005f, -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x00000060, -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x00000061, -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x00000062, -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x00000063, -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x00000064, -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x00000065, -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000066, -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000067, -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000068, -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000069, -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x0000006a, -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x0000006b, -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x0000006c, -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x0000006d, -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x0000006e, -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x0000006f, -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x00000070, -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x00000071, -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x00000072, -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x00000073, -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x00000074, -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x00000075, -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000076, -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000077, -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000078, -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000079, -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x0000007a, -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x0000007b, -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x0000007c, -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x0000007d, -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x0000007e, -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x0000007f, -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x00000080, -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x00000081, -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x00000082, -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x00000083, -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x00000084, -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x00000085, -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000086, -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000087, -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000088, -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000089, -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x0000008a, -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x0000008b, -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x0000008c, -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x0000008d, -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x0000008e, -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x0000008f, -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x00000090, -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x00000091, -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x00000092, -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x00000093, -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x00000094, -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x00000095, -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000096, -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000097, -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000098, -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000099, -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x0000009a, -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x0000009b, -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x0000009c, -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x0000009d, -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x0000009e, -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x0000009f, -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x000000a0, -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x000000a1, -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x000000a2, -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x000000a3, -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x000000a4, -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x000000a5, -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a6, -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a7, -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a8, -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a9, -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000aa, -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000ab, -SEM_PERF_SEL_MC_RD_REQ = 0x000000ac, -SEM_PERF_SEL_MC_RD_RET = 0x000000ad, -SEM_PERF_SEL_MC_WR_REQ = 0x000000ae, -SEM_PERF_SEL_MC_WR_RET = 0x000000af, -SEM_PERF_SEL_ATC_REQ = 0x000000b0, -SEM_PERF_SEL_ATC_RET = 0x000000b1, -SEM_PERF_SEL_ATC_XNACK = 0x000000b2, -SEM_PERF_SEL_ATC_INVALIDATION = 0x000000b3, -SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000b4, -} SEM_PERF_SEL; - -/******************************************************* - * LSDMA Enums - *******************************************************/ - -/* - * LSDMA_PERF_SEL enum - */ - -typedef enum LSDMA_PERF_SEL { -LSDMA_PERF_SEL_CYCLE = 0x00000000, -LSDMA_PERF_SEL_IDLE = 0x00000001, -LSDMA_PERF_SEL_REG_IDLE = 0x00000002, -LSDMA_PERF_SEL_RB_EMPTY = 0x00000003, -LSDMA_PERF_SEL_RB_FULL = 0x00000004, -LSDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, -LSDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, -LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, -LSDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, -LSDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, -LSDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, -LSDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, -LSDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, -LSDMA_PERF_SEL_EX_IDLE = 0x0000000d, -LSDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, -LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, -LSDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, -LSDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, -LSDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, -LSDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, -LSDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, -LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, -LSDMA_PERF_SEL_SEM_IDLE = 0x00000018, -LSDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, -LSDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, -LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, -LSDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, -LSDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, -LSDMA_PERF_SEL_INT_IDLE = 0x0000001e, -LSDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, -LSDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, -LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, -LSDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, -LSDMA_PERF_SEL_NUM_PACKET = 0x00000023, -LSDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, -LSDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, -LSDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, -LSDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, -LSDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, -LSDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, -LSDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, -LSDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, -LSDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, -LSDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, -LSDMA_PERF_SEL_CE_RD_STALL = 0x00000033, -LSDMA_PERF_SEL_CE_WR_STALL = 0x00000034, -LSDMA_PERF_SEL_GFX_SELECT = 0x00000035, -LSDMA_PERF_SEL_RLC0_SELECT = 0x00000036, -LSDMA_PERF_SEL_RLC1_SELECT = 0x00000037, -LSDMA_PERF_SEL_PAGE_SELECT = 0x00000038, -LSDMA_PERF_SEL_CTX_CHANGE = 0x00000039, -LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, -LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, -LSDMA_PERF_SEL_DOORBELL = 0x0000003c, -LSDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, -LSDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, -LSDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, -LSDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, -LSDMA_PERF_SEL_CE_L1_STALL = 0x00000041, -LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, -LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, -LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, -LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, -LSDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, -LSDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, -LSDMA_PERF_SEL_ATCL2_FREE = 0x00000048, -LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, -LSDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, -LSDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, -LSDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, -LSDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, -LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, -LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, -LSDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, -LSDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, -LSDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, -LSDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, -LSDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, -LSDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, -LSDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, -LSDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, -LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, -LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, -LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, -LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, -LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, -LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, -LSDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 0x0000005f, -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 0x00000060, -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 0x00000061, -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 0x00000062, -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 0x00000063, -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 0x00000064, -LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 0x00000065, -LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 0x00000066, -LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 0x00000067, -LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 0x00000068, -LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 0x00000069, -LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 0x0000006a, -LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000006b, -LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x0000006c, -LSDMA_PERF_SEL_CMD_OP_MATCH = 0x0000006d, -LSDMA_PERF_SEL_CMD_OP_START = 0x0000006e, -LSDMA_PERF_SEL_CMD_OP_END = 0x0000006f, -LSDMA_PERF_SEL_CE_BUSY = 0x00000070, -LSDMA_PERF_SEL_CE_BUSY_START = 0x00000071, -LSDMA_PERF_SEL_CE_BUSY_END = 0x00000072, -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000073, -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074, -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x00000075, -LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 0x00000076, -LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 0x00000077, -LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 0x00000078, -LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 0x00000079, -LSDMA_PERF_SEL_DRAM_ECC = 0x0000007a, -LSDMA_PERF_SEL_NACK_GEN_ERR = 0x0000007b, -} LSDMA_PERF_SEL; - -/******************************************************* - * SMUIO_ROM Enums - *******************************************************/ - -/* - * ROM_SIGNATURE value - */ - -#define ROM_SIGNATURE 0x0000aa55 - -/******************************************************* - * UVD_EFC Enums - *******************************************************/ - -/* - * EFC_SURFACE_PIXEL_FORMAT enum - */ - -typedef enum EFC_SURFACE_PIXEL_FORMAT { -EFC_ARGB1555 = 0x00000001, -EFC_RGBA5551 = 0x00000002, -EFC_RGB565 = 0x00000003, -EFC_BGR565 = 0x00000004, -EFC_ARGB4444 = 0x00000005, -EFC_RGBA4444 = 0x00000006, -EFC_ARGB8888 = 0x00000008, -EFC_RGBA8888 = 0x00000009, -EFC_ARGB2101010 = 0x0000000a, -EFC_RGBA1010102 = 0x0000000b, -EFC_AYCrCb8888 = 0x0000000c, -EFC_YCrCbA8888 = 0x0000000d, -EFC_ACrYCb8888 = 0x0000000e, -EFC_CrYCbA8888 = 0x0000000f, -EFC_ARGB16161616_10MSB = 0x00000010, -EFC_RGBA16161616_10MSB = 0x00000011, -EFC_ARGB16161616_10LSB = 0x00000012, -EFC_RGBA16161616_10LSB = 0x00000013, -EFC_ARGB16161616_12MSB = 0x00000014, -EFC_RGBA16161616_12MSB = 0x00000015, -EFC_ARGB16161616_12LSB = 0x00000016, -EFC_RGBA16161616_12LSB = 0x00000017, -EFC_ARGB16161616_FLOAT = 0x00000018, -EFC_RGBA16161616_FLOAT = 0x00000019, -EFC_ARGB16161616_UNORM = 0x0000001a, -EFC_RGBA16161616_UNORM = 0x0000001b, -EFC_ARGB16161616_SNORM = 0x0000001c, -EFC_RGBA16161616_SNORM = 0x0000001d, -EFC_AYCrCb16161616_10MSB = 0x00000020, -EFC_AYCrCb16161616_10LSB = 0x00000021, -EFC_YCrCbA16161616_10MSB = 0x00000022, -EFC_YCrCbA16161616_10LSB = 0x00000023, -EFC_ACrYCb16161616_10MSB = 0x00000024, -EFC_ACrYCb16161616_10LSB = 0x00000025, -EFC_CrYCbA16161616_10MSB = 0x00000026, -EFC_CrYCbA16161616_10LSB = 0x00000027, -EFC_AYCrCb16161616_12MSB = 0x00000028, -EFC_AYCrCb16161616_12LSB = 0x00000029, -EFC_YCrCbA16161616_12MSB = 0x0000002a, -EFC_YCrCbA16161616_12LSB = 0x0000002b, -EFC_ACrYCb16161616_12MSB = 0x0000002c, -EFC_ACrYCb16161616_12LSB = 0x0000002d, -EFC_CrYCbA16161616_12MSB = 0x0000002e, -EFC_CrYCbA16161616_12LSB = 0x0000002f, -EFC_Y8_CrCb88_420_PLANAR = 0x00000040, -EFC_Y8_CbCr88_420_PLANAR = 0x00000041, -EFC_Y10_CrCb1010_420_PLANAR = 0x00000042, -EFC_Y10_CbCr1010_420_PLANAR = 0x00000043, -EFC_Y12_CrCb1212_420_PLANAR = 0x00000044, -EFC_Y12_CbCr1212_420_PLANAR = 0x00000045, -EFC_YCrYCb8888_422_PACKED = 0x00000048, -EFC_YCbYCr8888_422_PACKED = 0x00000049, -EFC_CrYCbY8888_422_PACKED = 0x0000004a, -EFC_CbYCrY8888_422_PACKED = 0x0000004b, -EFC_YCrYCb10101010_422_PACKED = 0x0000004c, -EFC_YCbYCr10101010_422_PACKED = 0x0000004d, -EFC_CrYCbY10101010_422_PACKED = 0x0000004e, -EFC_CbYCrY10101010_422_PACKED = 0x0000004f, -EFC_YCrYCb12121212_422_PACKED = 0x00000050, -EFC_YCbYCr12121212_422_PACKED = 0x00000051, -EFC_CrYCbY12121212_422_PACKED = 0x00000052, -EFC_CbYCrY12121212_422_PACKED = 0x00000053, -EFC_RGB111110_FIX = 0x00000070, -EFC_BGR101111_FIX = 0x00000071, -EFC_ACrYCb2101010 = 0x00000072, -EFC_CrYCbA1010102 = 0x00000073, -EFC_RGB111110_FLOAT = 0x00000076, -EFC_BGR101111_FLOAT = 0x00000077, -EFC_MONO_8 = 0x00000078, -EFC_MONO_10MSB = 0x00000079, -EFC_MONO_10LSB = 0x0000007a, -EFC_MONO_12MSB = 0x0000007b, -EFC_MONO_12LSB = 0x0000007c, -EFC_MONO_16 = 0x0000007d, -} EFC_SURFACE_PIXEL_FORMAT; - -#endif /*_soc21_ENUM_HEADER*/ diff --git a/tinygrad/extra/hip_gpu_driver/test_kfd_2.py b/tinygrad/extra/hip_gpu_driver/test_kfd_2.py deleted file mode 100644 index caa42447..00000000 --- a/tinygrad/extra/hip_gpu_driver/test_kfd_2.py +++ /dev/null @@ -1,207 +0,0 @@ -import os, ctypes, pathlib, re, fcntl, functools, mmap, time -import tinygrad.runtime.autogen.kfd as kfd -from tinygrad.helpers import to_mv, getenv -from extra.hip_gpu_driver import hip_ioctl -import tinygrad.runtime.autogen.hsa as hsa -from hexdump import hexdump - -libc = ctypes.CDLL("libc.so.6") -libc.memset.argtypes = [ctypes.c_void_p, ctypes.c_char, ctypes.c_int] -libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] -libc.mmap.restype = ctypes.c_void_p -MAP_NORESERVE = 0x4000 -MAP_FIXED = 0x10 - -def kfd_ioctl(idir, nr, user_struct, fd, **kwargs): - made = user_struct(**kwargs) - ret = fcntl.ioctl(fd, (idir<<30) | (ctypes.sizeof(user_struct)<<16) | (ord('K')<<8) | nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def format_struct(s): - sdats = [] - for field_name, field_type in s._fields_: - dat = getattr(s, field_name) - if isinstance(dat, int): sdats.append(f"{field_name}:0x{dat:X}") - else: sdats.append(f"{field_name}:{dat}") - return sdats - -idirs = {"IOW": 1, "IOR": 2, "IOWR": 3} -def ioctls_from_header(): - hdr = pathlib.Path("/usr/include/linux/kfd_ioctl.h").read_text().replace("\\\n", "") - pattern = r'#define\s+(AMDKFD_IOC_[A-Z0-9_]+)\s+AMDKFD_(IOW?R?)\((0x[0-9a-fA-F]+),\s+struct\s([A-Za-z0-9_]+)\)' - matches = re.findall(pattern, hdr, re.MULTILINE) - - fxns = {} - for name, idir, nr, sname in matches: - fxns[name.replace("AMDKFD_IOC_", "").lower()] = functools.partial(kfd_ioctl, idirs[idir], int(nr, 0x10), getattr(kfd, "struct_"+sname)) - return type("KIO", (object, ), fxns) -kio = ioctls_from_header() - -# sudo su -c "echo 'file drivers/gpu/drm/amd/* +p' > /sys/kernel/debug/dynamic_debug/control" - -def gpu_alloc_userptr(fd, size, flags): - addr = libc.mmap(0, size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED|mmap.MAP_ANONYMOUS, -1, 0) - assert addr != 0xffffffffffffffff - mem = kio.alloc_memory_of_gpu(fd, va_addr=addr, size=size, gpu_id=GPU_ID, flags=flags, mmap_offset=addr) - return mem - -def gpu_alloc(fd, size, flags): - addr = libc.mmap(0, size, 0, mmap.MAP_PRIVATE|mmap.MAP_ANONYMOUS|MAP_NORESERVE, -1, 0) - assert addr != 0xffffffffffffffff - mem = kio.alloc_memory_of_gpu(fd, va_addr=addr, size=size, gpu_id=GPU_ID, flags=flags) - buf = libc.mmap(mem.va_addr, mem.size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED|MAP_FIXED, drm_fd, mem.mmap_offset) - assert buf != 0xffffffffffffffff - assert addr == buf == mem.va_addr - return mem - -if __name__ == "__main__": - fd = os.open("/dev/kfd", os.O_RDWR) - gpu_num = getenv("GPU", 0) - drm_fd = os.open(f"/dev/dri/renderD{128+gpu_num}", os.O_RDWR) - with open(f"/sys/devices/virtual/kfd/kfd/topology/nodes/{1+gpu_num}/gpu_id", "r") as f: GPU_ID = int(f.read()) - - #ver = kio.get_version(fd) - st = kio.acquire_vm(fd, drm_fd=drm_fd, gpu_id=GPU_ID) - #exit(0) - - # 0xF0000001 = KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC | KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE - # 0xD6000002 = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE - # 0xD6000004 = KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE - # 0x94000010 = KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE - #addr = libc.mmap(0, 0x1000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_PRIVATE|mmap.MAP_ANONYMOUS, -1, 0) - #addr = libc.mmap(0, 0x1000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED|mmap.MAP_ANONYMOUS, -1, 0) - #mem = kio.AMDKFD_IOC_ALLOC_MEMORY_OF_GPU(fd, va_addr=addr, size=0x1000, gpu_id=GPU_ID, flags=0xD6000004) - - #mem = gpu_alloc(fd, 0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM | - # kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | - # kfd.KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - #arr = (ctypes.c_int32 * 1)(GPU_ID) - #stm = kio.map_memory_to_gpu(fd, handle=mem.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - - arr = (ctypes.c_int32 * 1)(GPU_ID) - rw_ptr = gpu_alloc(fd, 0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=rw_ptr.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - event_page = gpu_alloc(fd, 0x8000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=event_page.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - ring_base = gpu_alloc_userptr(fd, 0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=ring_base.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - signals = gpu_alloc_userptr(fd, 0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=signals.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - eop_buffer = gpu_alloc(fd, 0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=eop_buffer.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - ctx_save_restore_address = gpu_alloc(fd, 0x2C02000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | - kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE) - stm = kio.map_memory_to_gpu(fd, handle=ctx_save_restore_address.handle, device_ids_array_ptr=ctypes.addressof(arr), n_devices=1) - assert stm.n_success == 1 - - #113.00 ms + 0.00 ms : 0 = AMDKFD_IOC_CREATE_QUEUE ring_base_address:0x797465200000 write_pointer_address:0x79751C068038 read_pointer_address:0x79751C068080 doorbell_offset:0x0 ring_size:0x800000 gpu_id:0x433D queue_type:0x2 queue_per - #centage:0x64 queue_priority:0x7 queue_id:0x0 eop_buffer_address:0x79751C064000 eop_buffer_size:0x1000 ctx_save_restore_address:0x796E52400000 ctx_save_restore_size:0x2BEA000 ctl_stack_size:0xA000 - - #113.84 ms + 0.59 ms : 0 = AMDKFD_IOC_CREATE_QUEUE ring_base_address:0x71AC3F600000 write_pointer_address:0x71B302AB0038 read_pointer_address:0x71B302AB0080 doorbell_offset:0xD0CF400000000008 ring_size:0x800000 gpu_id:0x433D queue_typ - #e:0x2 queue_percentage:0x64 queue_priority:0x7 queue_id:0x1 eop_buffer_address:0x71B302AAC000 eop_buffer_size:0x1000 ctx_save_restore_address:0x71AC3C800000 ctx_save_restore_size:0x2BEA000 ctl_stack_size:0xA000 - - #define KFD_MMAP_TYPE_SHIFT 62 - #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) - evt = kio.create_event(fd, event_page_offset=event_page.handle, auto_reset=1) - - nq = kio.create_queue(fd, ring_base_address=ring_base.va_addr, ring_size=0x1000, gpu_id=GPU_ID, - queue_type=kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE, - queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, - eop_buffer_address=eop_buffer.va_addr, eop_buffer_size=0x1000, - ctx_save_restore_address=ctx_save_restore_address.va_addr, ctx_save_restore_size=0x2C02000, - ctl_stack_size = 0xa000, - # write_pointer_address and read_pointer_address are on GART - #write_pointer_address=0xaaaabbbb, read_pointer_address=0xaaaacccc) - write_pointer_address=rw_ptr.va_addr+0, read_pointer_address=rw_ptr.va_addr+0x8) - doorbell = libc.mmap(0, 8192, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, fd, nq.doorbell_offset) - print("doorbell", hex(doorbell)) - - to_mv(signals.va_addr, 0x40) - - """ - hexdump(to_mv(event_page.va_addr, 0x40)) - kio.set_event(fd, event_id=evt.event_id) - hexdump(to_mv(event_page.va_addr, 0x40)) - kio.reset_event(fd, event_id=evt.event_id) - hexdump(to_mv(event_page.va_addr, 0x40)) - """ - - # KFD_EVENT_TYPE_SIGNAL - - BARRIER_HEADER = 1 << hsa.HSA_PACKET_HEADER_BARRIER - BARRIER_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE - BARRIER_HEADER |= hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE - BARRIER_HEADER |= hsa.HSA_PACKET_TYPE_BARRIER_AND << hsa.HSA_PACKET_HEADER_TYPE - - AQL_PACKET_SIZE = ctypes.sizeof(hsa.hsa_kernel_dispatch_packet_t) - EMPTY_SIGNAL = hsa.hsa_signal_t() - - ds = to_mv(rw_ptr.va_addr, 0x100).cast("Q") - ds[0] = 1 #ring_base.va_addr + AQL_PACKET_SIZE - ds[1] = 0 #ring_base.va_addr - #libc.memset(rw_ptr.va_addr, 0xaa, 0x100) - #hexdump(to_mv(rw_ptr.va_addr, 0x100)) - - #packet = hsa.hsa_barrier_and_packet_t.from_address(rw_ptr.va_addr+0x38) - packet = hsa.hsa_barrier_and_packet_t.from_address(ring_base.va_addr) - packet.reserved0 = 0 - packet.reserved1 = 0 - for i in range(5): packet.dep_signal[i] = EMPTY_SIGNAL - #packet.dep_signal[0] = hsa.hsa_signal_t(evt.event_id) - packet.reserved2 = 0 - #packet.completion_signal = EMPTY_SIGNAL - packet.completion_signal = hsa.hsa_signal_t(signals.va_addr) - packet.header = BARRIER_HEADER - hexdump(to_mv(ring_base.va_addr, AQL_PACKET_SIZE)) - - # _HsaEventData - to_mv(signals.va_addr, 0x40).cast("Q")[0] = 1 - to_mv(signals.va_addr, 0x40).cast("Q")[1] = 1 - #to_mv(signals.va_addr, 0x40).cast("Q")[2] = event_page - to_mv(signals.va_addr, 0x40).cast("Q")[2] = event_page.va_addr + evt.event_slot_index*8 # HWData2=HWAddress - to_mv(signals.va_addr, 0x40).cast("Q")[3] = evt.event_trigger_data # HWData3=HWData - print(hex(ds[0]), hex(ds[1]), hex(ds[2])) - hexdump(to_mv(signals.va_addr, 0x40)) - - # 10 08 49 3E 46 77 00 00 - - - # ring doorbell - print(hex(to_mv(doorbell, 0x10).cast("I")[0])) - #to_mv(doorbell, 0x10).cast("I")[0] = 0xffffffff - to_mv(doorbell, 0x10).cast("I")[0] = 0 - - evt_arr = (kfd.struct_kfd_event_data * 1)() - evt_arr[0].event_id = evt.event_id - kio.wait_events(fd, events_ptr=ctypes.addressof(evt_arr), num_events=1, wait_for_all=0, timeout=1000) - - print(hex(ds[0]), hex(ds[1]), hex(ds[2])) - hexdump(to_mv(signals.va_addr, 0x40)) - - #nq = kio.create_queue(fd, ring_base_address=buf, ring_size=0x1000, gpu_id=GPU_ID, - # queue_type=kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE, - # queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, write_pointer_address=buf+8, read_pointer_address=buf+0x10) - #print(nq) - - #mv = to_mv(buf, 0x1000) - #addr = libc.mmap(0, 0x1000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_PRIVATE|mmap.MAP_ANONYMOUS, -1, 0) - - #print('\n'.join(format_struct(ver))) - #print('\n'.join(format_struct(st))) diff --git a/tinygrad/extra/hip_gpu_driver/test_pm4.py b/tinygrad/extra/hip_gpu_driver/test_pm4.py deleted file mode 100644 index d0cf9200..00000000 --- a/tinygrad/extra/hip_gpu_driver/test_pm4.py +++ /dev/null @@ -1,156 +0,0 @@ -import time -from hexdump import hexdump -from tinygrad import Tensor, Device -import tinygrad.runtime.autogen.amd_gpu as amd_gpu -import tinygrad.runtime.autogen.kfd as kfd -import tinygrad.runtime.autogen.hsa as hsa -from tinygrad.runtime.ops_amd import kio, AMDProgram -from tinygrad.helpers import to_mv - -DISPATCH_INIT_VALUE = 0x21 | 0x8000 - -#mmCOMPUTE_START_X = 0x2e04 -#mmCOMPUTE_PGM_LO = 0x2e0c - -BASE_ADDR = 0x00001260 -PACKET3_SET_SH_REG_START = 0x2c00 -SUB = PACKET3_SET_SH_REG_START - BASE_ADDR - -regCOMPUTE_PGM_LO = 0x1bac - SUB -regCOMPUTE_START_X = 0x1ba4 - SUB -regCOMPUTE_NUM_THREAD_X = 0x1ba7 - SUB -regCOMPUTE_USER_DATA_0 = 0x1be0 - SUB -regCOMPUTE_USER_DATA_8 = 0x1be8 - SUB - -regCOMPUTE_PGM_RSRC1 = 0x1bb2 - SUB -regCOMPUTE_PGM_RSRC2 = 0x1bb3 - SUB - -# DEBUG=6 python3 extra/hip_gpu_driver/test_pm4.py -# sudo umr -i 1 -s amd744c.gfx1100 --sbank 1 1 2 | grep regCOMPUTE - -# 0x00009025 - -COMPUTE_SHADER_EN = 1 -USE_THREAD_DIMENSIONS = 1 << 5 -CS_W32_EN = 1 << 15 - -def format_struct(s): - sdats = [] - for field_name, field_type in s._fields_: - dat = getattr(s, field_name) - if isinstance(dat, int): sdats.append(f"{field_name}:0x{dat:X}") - else: sdats.append(f"{field_name}:{dat}") - return sdats - -if __name__ == "__main__": - dev = Device["KFD"] - - a = Tensor([0.,1.,2.], device="KFD").realize() - b = a + 7 - b.uop.buffer.allocate() - si = b.schedule()[-1] - runner = dev.get_runner(*si.ast) - prg: AMDProgram = runner.clprg - print("device initted") - - # Compute Queue - - gart_compute = dev._gpu_alloc(0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT, uncached=True) - eop_buffer = dev._gpu_alloc(0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - compute_ring = dev._gpu_alloc(0x800000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT, uncached=True) - ctx_save_restore_address = dev._gpu_alloc(0x2C02000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - compute_queue = kio.create_queue(dev.kfd, ring_base_address=compute_ring.va_addr, ring_size=compute_ring.size, gpu_id=dev.gpu_id, - queue_type=kfd.KFD_IOC_QUEUE_TYPE_COMPUTE, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE, queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, - #eop_buffer_address=eop_buffer.va_addr, eop_buffer_size=eop_buffer.size, - #ctx_save_restore_address=ctx_save_restore_address.va_addr, ctx_save_restore_size=ctx_save_restore_address.size, - #ctl_stack_size = 0xa000, - write_pointer_address=gart_compute.va_addr, read_pointer_address=gart_compute.va_addr+8) - compute_doorbell = to_mv(dev.doorbells + compute_queue.doorbell_offset - dev.doorbells_base, 4).cast("I") - - #scratch = dev._gpu_alloc(0x10000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - ka = to_mv(dev.kernargs_ptr, 0x10).cast("Q") - ka[0] = b.uop.buffer._buf.va_addr - ka[1] = a.uop.buffer._buf.va_addr - - compute_read_pointer = to_mv(compute_queue.read_pointer_address, 8).cast("Q") - compute_write_pointer = to_mv(compute_queue.write_pointer_address, 8).cast("Q") - - hexdump(to_mv(prg.handle, 0x40)) - code = hsa.amd_kernel_code_t.from_address(prg.handle) - - #print(format_struct(code)) - #print("code") - #hexdump(to_mv(code_ptr, 0x100)) - #runner.local_size = [2,1,1] - - print(runner.local_size, runner.global_size) - - #pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 6), mmCOMPUTE_PGM_LO, - # prg.handle&0xFFFFFFFF, prg.handle>>32, 0, 0, (scratch.va_addr>>8)&0xFFFFFFFF, scratch.va_addr>>40] - code_ptr = (prg.handle + code.kernel_code_entry_byte_offset) >> 8 - pm4_cmd = [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 6), regCOMPUTE_PGM_LO, code_ptr&0xFFFFFFFF, code_ptr>>32, 0, 0, 0, 0] - pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 2), regCOMPUTE_PGM_RSRC1, code.compute_pgm_rsrc1, code.compute_pgm_rsrc2] - pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 2), regCOMPUTE_USER_DATA_0, dev.kernargs_ptr&0xFFFFFFFF, dev.kernargs_ptr>>32] - #pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 2), regCOMPUTE_USER_DATA_0, 0, 0] - pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 8), regCOMPUTE_START_X, 0,0,0, - runner.local_size[0],runner.local_size[1],runner.local_size[2],0,0] - # disabled USE_THREAD_DIMENSIONS - pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_DISPATCH_DIRECT, 3), - runner.global_size[0],runner.global_size[1],runner.global_size[2], CS_W32_EN | COMPUTE_SHADER_EN] - - #pm4_cmd = [amd_gpu.PACKET3(amd_gpu.PACKET3_NOP, 0x3fff)]*0x200 - - """ - addr=0x0 - sz=(1 << 64)-1 - gli=0 - glv=0 - glk=0 - gl1=0 - gl2=0 - pm4_cmd = [amd_gpu.PACKET3(amd_gpu.PACKET3_ACQUIRE_MEM, 6), 0, - sz & 0xffffffff, (sz >> 32) & 0xff, addr & 0xffffffff, (addr >> 32) & 0xffffff, 0, - amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(gli) | amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(glk) | \ - amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(glv) | amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(gl1) | \ - amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(gl2)] - print(pm4_cmd) - """ - - wptr = 0 - pm4_buffer_view = to_mv(compute_ring.va_addr, compute_ring.size).cast("I") - - for j in range(0x80000): - for i, value in enumerate(pm4_cmd): pm4_buffer_view[wptr+i] = value - wptr += len(pm4_cmd) - - compute_write_pointer[0] = wptr - compute_doorbell[0] = wptr - for k in range(10): - done = compute_read_pointer[0] == compute_write_pointer[0] - print(compute_read_pointer[0], compute_write_pointer[0], done) - if done: break - time.sleep(0.01) - break - #break - - #print(compute_read_pointer[0]) - #time.sleep(0.05) - #print(compute_read_pointer[0]) - - #time.sleep(100) - - print(a.numpy()) - print(b.numpy()) - exit(0) - - #pm4_cmd = [amd_gpu.PACKET3(amd_gpu.PACKET3_SET_SH_REG, 8), mmCOMPUTE_PGM_LO, 0,0,0,1,1,1,0,0] - - - #pm4_cmd += [amd_gpu.PACKET3(amd_gpu.PACKET3_DISPATCH_DIRECT, )] - - - #pm4_cmd = [amd_gpu.PACKET3(amd_gpu.PACKET3_ACQUIRE_MEM, 6), 0, - # sz & 0xffffffff, (sz >> 32) & 0xff, addr & 0xffffffff, (addr >> 32) & 0xffffff, 0, - # amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(gli) | amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(glk) | \ - # amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(glv) | amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(gl1) | \ - # amd_gpu.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(gl2)] diff --git a/tinygrad/extra/hip_gpu_driver/test_sdma_fun.py b/tinygrad/extra/hip_gpu_driver/test_sdma_fun.py deleted file mode 100644 index deb6ad00..00000000 --- a/tinygrad/extra/hip_gpu_driver/test_sdma_fun.py +++ /dev/null @@ -1,43 +0,0 @@ -import ctypes, mmap, time -from tinygrad.runtime.ops_amd import AMDDevice, kio, sdma_pkts, libc -import tinygrad.runtime.autogen.amd_sdma as amd_sdma -import tinygrad.runtime.autogen.kfd as kfd -from tinygrad.helpers import to_mv - -if __name__ == "__main__": - dev = AMDDevice() - - sdma_ring = dev._gpu_alloc(1 << 22, kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR, uncached=True) - gart = dev._gpu_alloc(0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT, uncached=True) - sdma_queue = kio.create_queue(AMDDevice.kfd, - ring_base_address=sdma_ring.va_addr, ring_size=sdma_ring.size, gpu_id=dev.gpu_id, - queue_type=kfd.KFD_IOC_QUEUE_TYPE_SDMA, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE, queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, - write_pointer_address=gart.va_addr + 0x100, read_pointer_address=gart.va_addr + 0x108) - - doorbells_base = sdma_queue.doorbell_offset & (~0xfff) - doorbells = libc.mmap(0, 8192, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, AMDDevice.kfd, doorbells_base) - - sdma_read_pointer = to_mv(sdma_queue.read_pointer_address, 8).cast("Q") - sdma_write_pointer = to_mv(sdma_queue.write_pointer_address, 8).cast("Q") - sdma_doorbell = to_mv(doorbells + sdma_queue.doorbell_offset - doorbells_base, 4).cast("I") - - test_write_page = dev._gpu_alloc(0x1000, kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR, uncached=True) - cmd = sdma_pkts.timestamp(op=amd_sdma.SDMA_OP_TIMESTAMP, sub_op=amd_sdma.SDMA_SUBOP_TIMESTAMP_GET_GLOBAL, addr=test_write_page.va_addr) - - sdma_doorbell_value = 0 - def blit_sdma_command(cmd): - ctypes.memmove(sdma_ring.va_addr + (sdma_doorbell_value % sdma_ring.size), ctypes.addressof(cmd), sz:=ctypes.sizeof(cmd)) - return sz - - while True: - sdma_doorbell_value += blit_sdma_command(cmd) - sdma_write_pointer[0] = sdma_doorbell_value - sdma_doorbell[0] = sdma_doorbell_value - while sdma_read_pointer[0] != sdma_write_pointer[0]: continue - tm = to_mv(test_write_page.va_addr, 0x1000).cast("Q")[0]/1e8 - print(f"{tm:.3f} s @ 0x{sdma_ring.va_addr + (sdma_doorbell_value % sdma_ring.size):X} R:0x{sdma_queue.read_pointer_address:X} W:0x{sdma_queue.write_pointer_address:X}") - time.sleep(0.01) - - - - diff --git a/tinygrad/extra/hip_gpu_driver/vega10_sdma_pkt_open.h b/tinygrad/extra/hip_gpu_driver/vega10_sdma_pkt_open.h deleted file mode 100644 index 8de4ccce..00000000 --- a/tinygrad/extra/hip_gpu_driver/vega10_sdma_pkt_open.h +++ /dev/null @@ -1,3335 +0,0 @@ -/* - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __VEGA10_SDMA_PKT_OPEN_H_ -#define __VEGA10_SDMA_PKT_OPEN_H_ - -#define SDMA_OP_NOP 0 -#define SDMA_OP_COPY 1 -#define SDMA_OP_WRITE 2 -#define SDMA_OP_INDIRECT 4 -#define SDMA_OP_FENCE 5 -#define SDMA_OP_TRAP 6 -#define SDMA_OP_SEM 7 -#define SDMA_OP_POLL_REGMEM 8 -#define SDMA_OP_COND_EXE 9 -#define SDMA_OP_ATOMIC 10 -#define SDMA_OP_CONST_FILL 11 -#define SDMA_OP_PTEPDE 12 -#define SDMA_OP_TIMESTAMP 13 -#define SDMA_OP_SRBM_WRITE 14 -#define SDMA_OP_PRE_EXE 15 -#define SDMA_OP_DUMMY_TRAP 16 -#define SDMA_SUBOP_TIMESTAMP_SET 0 -#define SDMA_SUBOP_TIMESTAMP_GET 1 -#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 -#define SDMA_SUBOP_COPY_LINEAR 0 -#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 -#define SDMA_SUBOP_COPY_TILED 1 -#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 -#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 -#define SDMA_SUBOP_COPY_SOA 3 -#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 -#define SDMA_SUBOP_COPY_LINEAR_PHY 8 -#define SDMA_SUBOP_WRITE_LINEAR 0 -#define SDMA_SUBOP_WRITE_TILED 1 -#define SDMA_SUBOP_PTEPDE_GEN 0 -#define SDMA_SUBOP_PTEPDE_COPY 1 -#define SDMA_SUBOP_PTEPDE_RMW 2 -#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 -#define SDMA_SUBOP_DATA_FILL_MULTI 1 -#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 -#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 -#define SDMA_SUBOP_POLL_MEM_VERIFY 3 -#define HEADER_AGENT_DISPATCH 4 -#define HEADER_BARRIER 5 -#define SDMA_OP_AQL_COPY 0 -#define SDMA_OP_AQL_BARRIER_OR 0 - -/*define for op field*/ -#define SDMA_PKT_HEADER_op_offset 0 -#define SDMA_PKT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_HEADER_op_shift 0 -#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_HEADER_sub_op_offset 0 -#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_HEADER_sub_op_shift 8 -#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) - -/*define for all field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) - -/*define for dst_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) - -/*define for dst_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) - -/*define for dst_log field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) - -/*define for dst_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) - -/*define for dst_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) - -/*define for src_gcc field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) - -/*define for src_sys field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) - -/*define for src_snoop field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) - -/*define for src_gpa field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) - -/*define for dst1_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST1_ADDR_LO word*/ -/*define for dst1_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) - -/*define for DST1_ADDR_HI word*/ -/*define for dst1_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) - -/*define for DST2_ADDR_LO word*/ -/*define for dst2_addr_31_0 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) - -/*define for DST2_ADDR_HI word*/ -/*define for dst2_addr_63_32 field*/ -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 -#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) - -/*define for elementsize field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) - -/*define for src_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) - -/*define for DW_5 word*/ -/*define for src_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_8 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) - -/*define for DW_9 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) - -/*define for dst_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) - -/*define for DW_10 word*/ -/*define for dst_slice_pitch field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) - -/*define for DW_11 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) - -/*define for DW_12 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 -#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20 -#define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 -#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 -#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 -#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) - -/*define for epitch field*/ -#define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5 -#define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF -#define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16 -#define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 -#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 -#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 -#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 -#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 -#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 -#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) - -/*define for videocopy field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) - -/*define for broadcast field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 -#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) - -/*define for TILED_ADDR_LO_0 word*/ -/*define for tiled_addr0_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) - -/*define for TILED_ADDR_HI_0 word*/ -/*define for tiled_addr0_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) - -/*define for TILED_ADDR_LO_1 word*/ -/*define for tiled_addr1_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) - -/*define for TILED_ADDR_HI_1 word*/ -/*define for tiled_addr1_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) - -/*define for DW_5 word*/ -/*define for width field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) - -/*define for DW_6 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) - -/*define for DW_7 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) - -/*define for epitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) - -/*define for DW_8 word*/ -/*define for x field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) - -/*define for y field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) - -/*define for DW_9 word*/ -/*define for z field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) - -/*define for DW_10 word*/ -/*define for dst2_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 -#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for LINEAR_PITCH word*/ -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) - -/*define for LINEAR_SLICE_PITCH word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 -#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_COPY_T2T packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 -#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0 -#define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20 -#define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for src_x field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) - -/*define for src_y field*/ -#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 -#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) - -/*define for DW_4 word*/ -/*define for src_z field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) - -/*define for src_width field*/ -#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 -#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) - -/*define for DW_5 word*/ -/*define for src_height field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) - -/*define for src_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) - -/*define for DW_6 word*/ -/*define for src_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) - -/*define for src_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) - -/*define for src_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) - -/*define for src_epitch field*/ -#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6 -#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF -#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16 -#define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for dst_x field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) - -/*define for dst_y field*/ -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) - -/*define for DW_10 word*/ -/*define for dst_z field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) - -/*define for dst_width field*/ -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 -#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) - -/*define for DW_11 word*/ -/*define for dst_height field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 -#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) - -/*define for dst_depth field*/ -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 -#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) - -/*define for DW_12 word*/ -/*define for dst_element_size field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 -#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) - -/*define for dst_swizzle_mode field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) - -/*define for dst_dimension field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 -#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) - -/*define for dst_epitch field*/ -#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12 -#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF -#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16 -#define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) - -/*define for DW_13 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 -#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) - -/*define for DW_14 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 -#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) - -/*define for dst_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 -#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 -#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 -#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) - -/*define for mip_id field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) - -/*define for TILED_ADDR_LO word*/ -/*define for tiled_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) - -/*define for TILED_ADDR_HI word*/ -/*define for tiled_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for tiled_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) - -/*define for tiled_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) - -/*define for DW_4 word*/ -/*define for tiled_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) - -/*define for width field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) - -/*define for DW_5 word*/ -/*define for height field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) - -/*define for DW_6 word*/ -/*define for element_size field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) - -/*define for epitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) - -/*define for DW_9 word*/ -/*define for linear_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) - -/*define for linear_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) - -/*define for DW_10 word*/ -/*define for linear_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) - -/*define for linear_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) - -/*define for DW_11 word*/ -/*define for linear_slice_pitch field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) - -/*define for DW_12 word*/ -/*define for rect_x field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) - -/*define for rect_y field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) - -/*define for DW_13 word*/ -/*define for rect_z field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) - -/*define for tile_sw field*/ -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 -#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) - - -/* -** Definitions for SDMA_PKT_COPY_STRUCT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 -#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) - -/*define for tmz field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 -#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) - -/*define for detile field*/ -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 -#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 -#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) - -/*define for SB_ADDR_LO word*/ -/*define for sb_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) - -/*define for SB_ADDR_HI word*/ -/*define for sb_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) - -/*define for START_INDEX word*/ -/*define for start_index field*/ -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 -#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 -#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 -#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) - -/*define for DW_5 word*/ -/*define for stride field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF -#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) - -/*define for linear_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 -#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) - -/*define for struct_sw field*/ -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 -#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 -#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) - -/*define for LINEAR_ADDR_LO word*/ -/*define for linear_addr_31_0 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) - -/*define for LINEAR_ADDR_HI word*/ -/*define for linear_addr_63_32 field*/ -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 -#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_UNTILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 -#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_TILED packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) - -/*define for encrypt field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 -#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) - -/*define for tmz field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 -#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) - -/*define for mip_max field*/ -#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0 -#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F -#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20 -#define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DW_3 word*/ -/*define for width field*/ -#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 -#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) - -/*define for DW_4 word*/ -/*define for height field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) - -/*define for depth field*/ -#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 -#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) - -/*define for DW_5 word*/ -/*define for element_size field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 -#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) - -/*define for swizzle_mode field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F -#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 -#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) - -/*define for dimension field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 -#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) - -/*define for epitch field*/ -#define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5 -#define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF -#define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) - -/*define for DW_6 word*/ -/*define for x field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) - -/*define for y field*/ -#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 -#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF -#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 -#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) - -/*define for DW_7 word*/ -/*define for z field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF -#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 -#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) - -/*define for sw field*/ -#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 -#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 -#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 -#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF -#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 -#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 -#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) - -/*define for pte_size field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) - -/*define for direction field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) - -/*define for ptepde_op field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_BIT_FOR_DW word*/ -/*define for mask_first_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) - -/*define for mask_last_xfer field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) - -/*define for COUNT_IN_32B_XFER word*/ -/*define for count field*/ -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 -#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) - - -/* -** Definitions for SDMA_PKT_PTEPDE_RMW packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) - -/*define for gcc field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) - -/*define for sys field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) - -/*define for snp field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 -#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) - -/*define for gpa field*/ -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 -#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 -#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) - -/*define for MASK_LO word*/ -/*define for mask_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) - -/*define for MASK_HI word*/ -/*define for mask_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) - -/*define for VALUE_LO word*/ -/*define for value_31_0 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) - -/*define for VALUE_HI word*/ -/*define for value_63_32 field*/ -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 -#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) - - -/* -** Definitions for SDMA_PKT_WRITE_INCR packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 -#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 -#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for MASK_DW0 word*/ -/*define for mask_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) - -/*define for MASK_DW1 word*/ -/*define for mask_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) - -/*define for INIT_DW0 word*/ -/*define for init_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) - -/*define for INIT_DW1 word*/ -/*define for init_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) - -/*define for INCR_DW0 word*/ -/*define for incr_dw0 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) - -/*define for INCR_DW1 word*/ -/*define for incr_dw1 field*/ -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF -#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 -#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 -#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF -#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 -#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_INDIRECT packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 -#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 -#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) - -/*define for vmid field*/ -#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 -#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F -#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 -#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) - -/*define for BASE_LO word*/ -/*define for ib_base_31_0 field*/ -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 -#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) - -/*define for BASE_HI word*/ -/*define for ib_base_63_32 field*/ -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 -#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) - -/*define for IB_SIZE word*/ -/*define for ib_size field*/ -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF -#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 -#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) - -/*define for CSA_ADDR_LO word*/ -/*define for csa_addr_31_0 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) - -/*define for CSA_ADDR_HI word*/ -/*define for csa_addr_63_32 field*/ -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 -#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_SEMAPHORE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 -#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) - -/*define for write_one field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 -#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) - -/*define for signal field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 -#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) - -/*define for mailbox field*/ -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 -#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 -#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_FENCE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_FENCE_HEADER_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_op_shift 0 -#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 -#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 -#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_FENCE_DATA_data_offset 3 -#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_FENCE_DATA_data_shift 0 -#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_SRBM_WRITE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 -#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) - -/*define for byte_en field*/ -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F -#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 -#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) - -/*define for ADDR word*/ -/*define for addr field*/ -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF -#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 -#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) - -/*define for DATA word*/ -/*define for data field*/ -#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 -#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF -#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 -#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) - - -/* -** Definitions for SDMA_PKT_PRE_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 -#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) - -/*define for dev_sel field*/ -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF -#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 -#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_COND_EXE packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 -#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 -#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 -#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) - -/*define for REFERENCE word*/ -/*define for reference field*/ -#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 -#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF -#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 -#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) - -/*define for EXEC_COUNT word*/ -/*define for exec_count field*/ -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF -#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 -#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) - - -/* -** Definitions for SDMA_PKT_CONSTANT_FILL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) - -/*define for sw field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 -#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) - -/*define for fillsize field*/ -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 -#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 -#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for DATA word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 -#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF -#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 -#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_DATA_FILL_MULTI packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) - -/*define for memlog_clr field*/ -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 -#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) - -/*define for BYTE_STRIDE word*/ -/*define for byte_stride field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) - -/*define for DMA_COUNT word*/ -/*define for dma_count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for BYTE_COUNT word*/ -/*define for count field*/ -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 -#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REGMEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) - -/*define for hdp_flush field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 -#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) - -/*define for func field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 -#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 -#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) - -/*define for mem_poll field*/ -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 -#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 -#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) - -/*define for VALUE word*/ -/*define for value field*/ -#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 -#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 -#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) - -/*define for MASK word*/ -/*define for mask field*/ -#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 -#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 -#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) - -/*define for DW5 word*/ -/*define for interval field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF -#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 -#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) - -/*define for retry_count field*/ -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF -#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 -#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) - - -/* -** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) - -/*define for SRC_ADDR word*/ -/*define for addr_31_2 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) - -/*define for ea field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) - -/*define for DST_ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) - -/*define for START_PAGE word*/ -/*define for addr_31_4 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) - -/*define for PAGE_NUM word*/ -/*define for page_num_31_0 field*/ -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 -#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) - - -/* -** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) - -/*define for mode field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 -#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) - -/*define for PATTERN word*/ -/*define for pattern field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) - -/*define for CMP0_ADDR_START_LO word*/ -/*define for cmp0_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) - -/*define for CMP0_ADDR_START_HI word*/ -/*define for cmp0_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) - -/*define for CMP0_ADDR_END_LO word*/ -/*define for cmp1_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) - -/*define for CMP0_ADDR_END_HI word*/ -/*define for cmp1_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) - -/*define for CMP1_ADDR_START_LO word*/ -/*define for cmp1_start_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) - -/*define for CMP1_ADDR_START_HI word*/ -/*define for cmp1_start_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) - -/*define for CMP1_ADDR_END_LO word*/ -/*define for cmp1_end_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) - -/*define for CMP1_ADDR_END_HI word*/ -/*define for cmp1_end_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) - -/*define for REC_ADDR_LO word*/ -/*define for rec_31_0 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) - -/*define for REC_ADDR_HI word*/ -/*define for rec_63_32 field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) - -/*define for RESERVED word*/ -/*define for reserved field*/ -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 -#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) - - -/* -** Definitions for SDMA_PKT_ATOMIC packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF -#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 -#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) - -/*define for loop field*/ -#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 -#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) - -/*define for tmz field*/ -#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 -#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 -#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) - -/*define for atomic_op field*/ -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F -#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 -#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) - -/*define for ADDR_LO word*/ -/*define for addr_31_0 field*/ -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) - -/*define for ADDR_HI word*/ -/*define for addr_63_32 field*/ -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 -#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) - -/*define for SRC_DATA_LO word*/ -/*define for src_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) - -/*define for SRC_DATA_HI word*/ -/*define for src_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) - -/*define for CMP_DATA_LO word*/ -/*define for cmp_data_31_0 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) - -/*define for CMP_DATA_HI word*/ -/*define for cmp_data_63_32 field*/ -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 -#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) - -/*define for LOOP_INTERVAL word*/ -/*define for loop_interval field*/ -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 -#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_SET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) - -/*define for INIT_DATA_LO word*/ -/*define for init_data_31_0 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) - -/*define for INIT_DATA_HI word*/ -/*define for init_data_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) - -/*define for WRITE_ADDR_LO word*/ -/*define for write_addr_31_3 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) - -/*define for WRITE_ADDR_HI word*/ -/*define for write_addr_63_32 field*/ -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 -#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) - - -/* -** Definitions for SDMA_PKT_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_DUMMY_TRAP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 -#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) - -/*define for INT_CONTEXT word*/ -/*define for int_context field*/ -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 -#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) - - -/* -** Definitions for SDMA_PKT_NOP packet -*/ - -/*define for HEADER word*/ -/*define for op field*/ -#define SDMA_PKT_NOP_HEADER_op_offset 0 -#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_op_shift 0 -#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) - -/*define for sub_op field*/ -#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 -#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF -#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 -#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) - -/*define for count field*/ -#define SDMA_PKT_NOP_HEADER_count_offset 0 -#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF -#define SDMA_PKT_NOP_HEADER_count_shift 16 -#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) - -/*define for DATA0 word*/ -/*define for data0 field*/ -#define SDMA_PKT_NOP_DATA0_data0_offset 1 -#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF -#define SDMA_PKT_NOP_DATA0_data0_shift 0 -#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) - - -/* -** Definitions for SDMA_AQL_PKT_HEADER packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 -#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 -#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) - - -/* -** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) - -/*define for RETURN_ADDR_LO word*/ -/*define for return_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) - -/*define for RETURN_ADDR_HI word*/ -/*define for return_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) - -/*define for COUNT word*/ -/*define for count field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) - -/*define for PARAMETER word*/ -/*define for dst_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) - -/*define for src_sw field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 -#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) - -/*define for SRC_ADDR_LO word*/ -/*define for src_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) - -/*define for SRC_ADDR_HI word*/ -/*define for src_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) - -/*define for DST_ADDR_LO word*/ -/*define for dst_addr_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) - -/*define for DST_ADDR_HI word*/ -/*define for dst_addr_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) - -/*define for RESERVED_DW10 word*/ -/*define for reserved_dw10 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) - -/*define for RESERVED_DW11 word*/ -/*define for reserved_dw11 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) - -/*define for RESERVED_DW12 word*/ -/*define for reserved_dw12 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -/* -** Definitions for SDMA_AQL_PKT_BARRIER_OR packet -*/ - -/*define for HEADER word*/ -/*define for format field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) - -/*define for barrier field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) - -/*define for acquire_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) - -/*define for release_fence_scope field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) - -/*define for reserved field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) - -/*define for op field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) - -/*define for subop field*/ -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 -#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) - -/*define for RESERVED_DW1 word*/ -/*define for reserved_dw1 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) - -/*define for DEPENDENT_ADDR_0_LO word*/ -/*define for dependent_addr_0_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) - -/*define for DEPENDENT_ADDR_0_HI word*/ -/*define for dependent_addr_0_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) - -/*define for DEPENDENT_ADDR_1_LO word*/ -/*define for dependent_addr_1_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) - -/*define for DEPENDENT_ADDR_1_HI word*/ -/*define for dependent_addr_1_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) - -/*define for DEPENDENT_ADDR_2_LO word*/ -/*define for dependent_addr_2_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) - -/*define for DEPENDENT_ADDR_2_HI word*/ -/*define for dependent_addr_2_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) - -/*define for DEPENDENT_ADDR_3_LO word*/ -/*define for dependent_addr_3_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) - -/*define for DEPENDENT_ADDR_3_HI word*/ -/*define for dependent_addr_3_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) - -/*define for DEPENDENT_ADDR_4_LO word*/ -/*define for dependent_addr_4_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) - -/*define for DEPENDENT_ADDR_4_HI word*/ -/*define for dependent_addr_4_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) - -/*define for RESERVED_DW12 word*/ -/*define for reserved_dw12 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) - -/*define for RESERVED_DW13 word*/ -/*define for reserved_dw13 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) - -/*define for COMPLETION_SIGNAL_LO word*/ -/*define for completion_signal_31_0 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) - -/*define for COMPLETION_SIGNAL_HI word*/ -/*define for completion_signal_63_32 field*/ -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 -#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) - - -#endif /* __SDMA_PKT_OPEN_H_ */ diff --git a/tinygrad/extra/hip_large_kernel.py b/tinygrad/extra/hip_large_kernel.py deleted file mode 100644 index 783e30f5..00000000 --- a/tinygrad/extra/hip_large_kernel.py +++ /dev/null @@ -1,25 +0,0 @@ -from tinygrad.device import Device, Buffer -from tinygrad.dtype import dtypes, _to_np_dtype - -dev = Device.default -mbin = dev.compiler.compile(""" -typedef long unsigned int size_t; -extern "C" __attribute__((device, const)) size_t __ockl_get_group_id(unsigned int); -extern "C" __attribute__((global)) void __attribute__((amdgpu_flat_work_group_size(1, 1))) write_ones(signed char* data0) { - int gidx0 = __ockl_get_group_id(0); /* 16 */ - int gidx1 = __ockl_get_group_id(1); /* 1026048 */ - *(data0+(gidx0+gidx1*1)) = 1; -} -""") -dev.compiler.disassemble(mbin) -buf0 = Buffer(Device.DEFAULT, 1*65537, dtypes.uint8).ensure_allocated() - -prg = dev.runtime("write_ones", mbin) -prg(buf0._buf, global_size=(1,65537,1), local_size=(1,1,1), wait=True) - -import numpy as np -def to_np(buf): return np.frombuffer(buf.as_buffer().cast(buf.dtype.base.fmt), dtype=_to_np_dtype(buf.dtype.base)) - -big = to_np(buf0) -print(big) -print((big-1).nonzero()) diff --git a/tinygrad/extra/hiprtc/hiprtc_runtime.h b/tinygrad/extra/hiprtc/hiprtc_runtime.h deleted file mode 100644 index b390504e..00000000 --- a/tinygrad/extra/hiprtc/hiprtc_runtime.h +++ /dev/null @@ -1,15143 +0,0 @@ -#pragma clang diagnostic ignored "-Weverything" - -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/out/ubuntu-22.04/22.04/build/hip-on-rocclr/hipamd/src/hiprtc/hip_rtc_gen/hipRTC_header.h" -# 1 "" 1 -# 1 "" 3 -# 845 "" 3 -# 1 "" 1 -# 1 "" 2 -# 1 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 1 3 -# 33 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 3 -extern "C" { - __attribute__((__visibility__("default"))) - __attribute__((weak)) - __attribute__((noreturn)) - __attribute__((device)) void __cxa_pure_virtual(void) { - __builtin_trap(); - } - __attribute__((__visibility__("default"))) - __attribute__((weak)) - __attribute__((noreturn)) - __attribute__((device)) void __cxa_deleted_virtual(void) { - __builtin_trap(); - } -} -# 57 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 3 -typedef long unsigned int size_t; -# 74 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 3 -typedef long unsigned int __hip_size_t; - - -extern "C" { - - - -extern "C" __attribute__((device)) unsigned long long __ockl_dm_alloc(unsigned long long __size); -extern "C" __attribute__((device)) void __ockl_dm_dealloc(unsigned long long __addr); -# 95 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 3 -__attribute__((weak)) inline __attribute__((device)) void *malloc(__hip_size_t __size) { - return (void *) __ockl_dm_alloc(__size); -} -__attribute__((weak)) inline __attribute__((device)) void free(void *__ptr) { - __ockl_dm_dealloc((unsigned long long)__ptr); -} -# 124 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 3 -} - - -# 1 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_libdevice_declares.h" 1 3 -# 14 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_libdevice_declares.h" 3 -extern "C" { - - - -__attribute__((device)) __attribute__((const)) float __ocml_acos_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_acosh_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_asin_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_asinh_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_atan2_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_atan_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_atanh_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_cbrt_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_ceil_f32(float); -__attribute__((device)) __attribute__((const)) __attribute__((device)) float __ocml_copysign_f32(float, - float); -__attribute__((device)) float __ocml_cos_f32(float); -__attribute__((device)) float __ocml_native_cos_f32(float); -__attribute__((device)) __attribute__((pure)) __attribute__((device)) float __ocml_cosh_f32(float); -__attribute__((device)) float __ocml_cospi_f32(float); -__attribute__((device)) float __ocml_i0_f32(float); -__attribute__((device)) float __ocml_i1_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_erfc_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_erfcinv_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_erfcx_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_erf_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_erfinv_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_exp10_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_native_exp10_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_exp2_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_exp_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_native_exp_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_expm1_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_fabs_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_fdim_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_floor_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_fma_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_fmax_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_fmin_f32(float, float); -__attribute__((device)) __attribute__((const)) __attribute__((device)) float __ocml_fmod_f32(float, - float); -__attribute__((device)) float __ocml_frexp_f32(float, - __attribute__((address_space(5))) int *); -__attribute__((device)) __attribute__((const)) float __ocml_hypot_f32(float, float); -__attribute__((device)) __attribute__((const)) int __ocml_ilogb_f32(float); -__attribute__((device)) __attribute__((const)) int __ocml_isfinite_f32(float); -__attribute__((device)) __attribute__((const)) int __ocml_isinf_f32(float); -__attribute__((device)) __attribute__((const)) int __ocml_isnan_f32(float); -__attribute__((device)) float __ocml_j0_f32(float); -__attribute__((device)) float __ocml_j1_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_ldexp_f32(float, int); -__attribute__((device)) float __ocml_lgamma_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_log10_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_native_log10_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_log1p_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_log2_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_native_log2_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_logb_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_log_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_native_log_f32(float); -__attribute__((device)) float __ocml_modf_f32(float, - __attribute__((address_space(5))) float *); -__attribute__((device)) __attribute__((const)) float __ocml_nearbyint_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_nextafter_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_len3_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_len4_f32(float, float, float, - float); -__attribute__((device)) __attribute__((pure)) float __ocml_ncdf_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_ncdfinv_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_pow_f32(float, float); -__attribute__((device)) __attribute__((pure)) float __ocml_pown_f32(float, int); -__attribute__((device)) __attribute__((pure)) float __ocml_rcbrt_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_remainder_f32(float, float); -__attribute__((device)) float __ocml_remquo_f32(float, float, - __attribute__((address_space(5))) int *); -__attribute__((device)) __attribute__((const)) float __ocml_rhypot_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_rint_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_rlen3_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_rlen4_f32(float, float, float, - float); -__attribute__((device)) __attribute__((const)) float __ocml_round_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_rsqrt_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_scalb_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_scalbn_f32(float, int); -__attribute__((device)) __attribute__((const)) int __ocml_signbit_f32(float); -__attribute__((device)) float __ocml_sincos_f32(float, - __attribute__((address_space(5))) float *); -__attribute__((device)) float __ocml_sincospi_f32(float, - __attribute__((address_space(5))) float *); -__attribute__((device)) float __ocml_sin_f32(float); -__attribute__((device)) float __ocml_native_sin_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_sinh_f32(float); -__attribute__((device)) float __ocml_sinpi_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_sqrt_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_native_sqrt_f32(float); -__attribute__((device)) float __ocml_tan_f32(float); -__attribute__((device)) __attribute__((pure)) float __ocml_tanh_f32(float); -__attribute__((device)) float __ocml_tgamma_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_trunc_f32(float); -__attribute__((device)) float __ocml_y0_f32(float); -__attribute__((device)) float __ocml_y1_f32(float); - - -__attribute__((device)) __attribute__((const)) float __ocml_add_rte_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_add_rtn_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_add_rtp_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_add_rtz_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_sub_rte_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_sub_rtn_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_sub_rtp_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_sub_rtz_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_mul_rte_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_mul_rtn_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_mul_rtp_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_mul_rtz_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_div_rte_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_div_rtn_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_div_rtp_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_div_rtz_f32(float, float); -__attribute__((device)) __attribute__((const)) float __ocml_sqrt_rte_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_sqrt_rtn_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_sqrt_rtp_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_sqrt_rtz_f32(float); -__attribute__((device)) __attribute__((const)) float __ocml_fma_rte_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_fma_rtn_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_fma_rtp_f32(float, float, float); -__attribute__((device)) __attribute__((const)) float __ocml_fma_rtz_f32(float, float, float); - -__attribute__((device)) inline __attribute__((const)) float -__llvm_amdgcn_cos_f32(float __x) { - return __builtin_amdgcn_cosf(__x); -} -__attribute__((device)) inline __attribute__((const)) float -__llvm_amdgcn_rcp_f32(float __x) { - return __builtin_amdgcn_rcpf(__x); -} -__attribute__((device)) inline __attribute__((const)) float -__llvm_amdgcn_rsq_f32(float __x) { - return __builtin_amdgcn_rsqf(__x); -} -__attribute__((device)) inline __attribute__((const)) float -__llvm_amdgcn_sin_f32(float __x) { - return __builtin_amdgcn_sinf(__x); -} - - - - -__attribute__((device)) __attribute__((const)) double __ocml_acos_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_acosh_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_asin_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_asinh_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_atan2_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_atan_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_atanh_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_cbrt_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_ceil_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_copysign_f64(double, double); -__attribute__((device)) double __ocml_cos_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_cosh_f64(double); -__attribute__((device)) double __ocml_cospi_f64(double); -__attribute__((device)) double __ocml_i0_f64(double); -__attribute__((device)) double __ocml_i1_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_erfc_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_erfcinv_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_erfcx_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_erf_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_erfinv_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_exp10_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_exp2_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_exp_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_expm1_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_fabs_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_fdim_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_floor_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_fma_f64(double, double, double); -__attribute__((device)) __attribute__((const)) double __ocml_fmax_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_fmin_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_fmod_f64(double, double); -__attribute__((device)) double __ocml_frexp_f64(double, - __attribute__((address_space(5))) int *); -__attribute__((device)) __attribute__((const)) double __ocml_hypot_f64(double, double); -__attribute__((device)) __attribute__((const)) int __ocml_ilogb_f64(double); -__attribute__((device)) __attribute__((const)) int __ocml_isfinite_f64(double); -__attribute__((device)) __attribute__((const)) int __ocml_isinf_f64(double); -__attribute__((device)) __attribute__((const)) int __ocml_isnan_f64(double); -__attribute__((device)) double __ocml_j0_f64(double); -__attribute__((device)) double __ocml_j1_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_ldexp_f64(double, int); -__attribute__((device)) double __ocml_lgamma_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_log10_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_log1p_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_log2_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_logb_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_log_f64(double); -__attribute__((device)) double __ocml_modf_f64(double, - __attribute__((address_space(5))) double *); -__attribute__((device)) __attribute__((const)) double __ocml_nearbyint_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_nextafter_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_len3_f64(double, double, - double); -__attribute__((device)) __attribute__((const)) double __ocml_len4_f64(double, double, double, - double); -__attribute__((device)) __attribute__((pure)) double __ocml_ncdf_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_ncdfinv_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_pow_f64(double, double); -__attribute__((device)) __attribute__((pure)) double __ocml_pown_f64(double, int); -__attribute__((device)) __attribute__((pure)) double __ocml_rcbrt_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_remainder_f64(double, double); -__attribute__((device)) double __ocml_remquo_f64(double, double, - __attribute__((address_space(5))) int *); -__attribute__((device)) __attribute__((const)) double __ocml_rhypot_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_rint_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_rlen3_f64(double, double, - double); -__attribute__((device)) __attribute__((const)) double __ocml_rlen4_f64(double, double, - double, double); -__attribute__((device)) __attribute__((const)) double __ocml_round_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_rsqrt_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_scalb_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_scalbn_f64(double, int); -__attribute__((device)) __attribute__((const)) int __ocml_signbit_f64(double); -__attribute__((device)) double __ocml_sincos_f64(double, - __attribute__((address_space(5))) double *); -__attribute__((device)) double -__ocml_sincospi_f64(double, __attribute__((address_space(5))) double *); -__attribute__((device)) double __ocml_sin_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_sinh_f64(double); -__attribute__((device)) double __ocml_sinpi_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_sqrt_f64(double); -__attribute__((device)) double __ocml_tan_f64(double); -__attribute__((device)) __attribute__((pure)) double __ocml_tanh_f64(double); -__attribute__((device)) double __ocml_tgamma_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_trunc_f64(double); -__attribute__((device)) double __ocml_y0_f64(double); -__attribute__((device)) double __ocml_y1_f64(double); - - -__attribute__((device)) __attribute__((const)) double __ocml_add_rte_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_add_rtn_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_add_rtp_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_add_rtz_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_sub_rte_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_sub_rtn_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_sub_rtp_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_sub_rtz_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_mul_rte_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_mul_rtn_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_mul_rtp_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_mul_rtz_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_div_rte_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_div_rtn_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_div_rtp_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_div_rtz_f64(double, double); -__attribute__((device)) __attribute__((const)) double __ocml_sqrt_rte_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_sqrt_rtn_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_sqrt_rtp_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_sqrt_rtz_f64(double); -__attribute__((device)) __attribute__((const)) double __ocml_fma_rte_f64(double, double, - double); -__attribute__((device)) __attribute__((const)) double __ocml_fma_rtn_f64(double, double, - double); -__attribute__((device)) __attribute__((const)) double __ocml_fma_rtp_f64(double, double, - double); -__attribute__((device)) __attribute__((const)) double __ocml_fma_rtz_f64(double, double, - double); - -__attribute__((device)) inline __attribute__((const)) double -__llvm_amdgcn_rcp_f64(double __x) { - return __builtin_amdgcn_rcp(__x); -} -__attribute__((device)) inline __attribute__((const)) double -__llvm_amdgcn_rsq_f64(double __x) { - return __builtin_amdgcn_rsq(__x); -} - -__attribute__((device)) __attribute__((const)) _Float16 __ocml_ceil_f16(_Float16); -__attribute__((device)) _Float16 __ocml_cos_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_cvtrtn_f16_f32(float); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_cvtrtp_f16_f32(float); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_cvtrtz_f16_f32(float); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_exp_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_exp10_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_exp2_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_floor_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_fma_f16(_Float16, _Float16, - _Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_fmax_f16(_Float16, _Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_fmin_f16(_Float16, _Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_fabs_f16(_Float16); -__attribute__((device)) __attribute__((const)) int __ocml_isinf_f16(_Float16); -__attribute__((device)) __attribute__((const)) int __ocml_isnan_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_log_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_log10_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_log2_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __llvm_amdgcn_rcp_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_rint_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_rsqrt_f16(_Float16); -__attribute__((device)) _Float16 __ocml_sin_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_sqrt_f16(_Float16); -__attribute__((device)) __attribute__((const)) _Float16 __ocml_trunc_f16(_Float16); -__attribute__((device)) __attribute__((pure)) _Float16 __ocml_pown_f16(_Float16, int); - -typedef _Float16 __2f16 __attribute__((ext_vector_type(2))); -typedef short __2i16 __attribute__((ext_vector_type(2))); - - -__attribute__((device)) __attribute__((const)) float __ockl_fdot2(__2f16 a, __2f16 b, - float c, bool s); - - - - -__attribute__((device)) __attribute__((const)) __2f16 __ocml_ceil_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_fabs_2f16(__2f16); -__attribute__((device)) __2f16 __ocml_cos_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_exp_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_exp10_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_exp2_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_floor_2f16(__2f16); -__attribute__((device)) __attribute__((const)) -__2f16 __ocml_fma_2f16(__2f16, __2f16, __2f16); -__attribute__((device)) __attribute__((const)) __2i16 __ocml_isinf_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2i16 __ocml_isnan_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_log_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_log10_2f16(__2f16); -__attribute__((device)) __attribute__((pure)) __2f16 __ocml_log2_2f16(__2f16); -__attribute__((device)) inline __2f16 -__llvm_amdgcn_rcp_2f16(__2f16 __x) -{ - return (__2f16)(__llvm_amdgcn_rcp_f16(__x.x), __llvm_amdgcn_rcp_f16(__x.y)); -} -__attribute__((device)) __attribute__((const)) __2f16 __ocml_rint_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_rsqrt_2f16(__2f16); -__attribute__((device)) __2f16 __ocml_sin_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_sqrt_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_trunc_2f16(__2f16); -__attribute__((device)) __attribute__((const)) __2f16 __ocml_pown_2f16(__2f16, __2i16); - - -} -# 128 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 2 3 -# 1 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 1 3 -# 94 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -long unsigned int __make_mantissa_base8(const char *__tagp __attribute__((nonnull))) { - long unsigned int __r = 0; - while (*__tagp != '\0') { - char __tmp = *__tagp; - - if (__tmp >= '0' && __tmp <= '7') - __r = (__r * 8u) + __tmp - '0'; - else - return 0; - - ++__tagp; - } - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -long unsigned int __make_mantissa_base10(const char *__tagp __attribute__((nonnull))) { - long unsigned int __r = 0; - while (*__tagp != '\0') { - char __tmp = *__tagp; - - if (__tmp >= '0' && __tmp <= '9') - __r = (__r * 10u) + __tmp - '0'; - else - return 0; - - ++__tagp; - } - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -long unsigned int __make_mantissa_base16(const char *__tagp __attribute__((nonnull))) { - long unsigned int __r = 0; - while (*__tagp != '\0') { - char __tmp = *__tagp; - - if (__tmp >= '0' && __tmp <= '9') - __r = (__r * 16u) + __tmp - '0'; - else if (__tmp >= 'a' && __tmp <= 'f') - __r = (__r * 16u) + __tmp - 'a' + 10; - else if (__tmp >= 'A' && __tmp <= 'F') - __r = (__r * 16u) + __tmp - 'A' + 10; - else - return 0; - - ++__tagp; - } - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -long unsigned int __make_mantissa(const char *__tagp __attribute__((nonnull))) { - if (*__tagp == '0') { - ++__tagp; - - if (*__tagp == 'x' || *__tagp == 'X') - return __make_mantissa_base16(__tagp); - else - return __make_mantissa_base8(__tagp); - } - - return __make_mantissa_base10(__tagp); -} - - - -static __attribute__((device)) inline __attribute__((always_inline)) -int abs(int __x) { - int __sgn = __x >> (sizeof(int) * 8 - 1); - return (__x ^ __sgn) - __sgn; -} -static __attribute__((device)) inline __attribute__((always_inline)) -long labs(long __x) { - long __sgn = __x >> (sizeof(long) * 8 - 1); - return (__x ^ __sgn) - __sgn; -} -static __attribute__((device)) inline __attribute__((always_inline)) -long long llabs(long long __x) { - long long __sgn = __x >> (sizeof(long long) * 8 - 1); - return (__x ^ __sgn) - __sgn; -} - - -static __attribute__((device)) inline __attribute__((always_inline)) -float acosf(float __x) { return __ocml_acos_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float acoshf(float __x) { return __ocml_acosh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float asinf(float __x) { return __ocml_asin_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float asinhf(float __x) { return __ocml_asinh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float atan2f(float __x, float __y) { return __ocml_atan2_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float atanf(float __x) { return __ocml_atan_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float atanhf(float __x) { return __ocml_atanh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float cbrtf(float __x) { return __ocml_cbrt_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float ceilf(float __x) { return __ocml_ceil_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float copysignf(float __x, float __y) { return __ocml_copysign_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float cosf(float __x) { return __ocml_cos_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float coshf(float __x) { return __ocml_cosh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float cospif(float __x) { return __ocml_cospi_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float cyl_bessel_i0f(float __x) { return __ocml_i0_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float cyl_bessel_i1f(float __x) { return __ocml_i1_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float erfcf(float __x) { return __ocml_erfc_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float erfcinvf(float __x) { return __ocml_erfcinv_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float erfcxf(float __x) { return __ocml_erfcx_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float erff(float __x) { return __ocml_erf_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float erfinvf(float __x) { return __ocml_erfinv_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float exp10f(float __x) { return __ocml_exp10_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float exp2f(float __x) { return __ocml_exp2_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float expf(float __x) { return __ocml_exp_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float expm1f(float __x) { return __ocml_expm1_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fabsf(float __x) { return __builtin_fabsf(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fdimf(float __x, float __y) { return __ocml_fdim_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fdividef(float __x, float __y) { return __x / __y; } - -static __attribute__((device)) inline __attribute__((always_inline)) -float floorf(float __x) { return __ocml_floor_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fmaf(float __x, float __y, float __z) { - return __ocml_fma_f32(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float fmaxf(float __x, float __y) { return __ocml_fmax_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fminf(float __x, float __y) { return __ocml_fmin_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float fmodf(float __x, float __y) { return __ocml_fmod_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float frexpf(float __x, int *__nptr) { - int __tmp; - - - - float __r = - __ocml_frexp_f32(__x, (__attribute__((address_space(5))) int *)&__tmp); - *__nptr = __tmp; - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float hypotf(float __x, float __y) { return __ocml_hypot_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -int ilogbf(float __x) { return __ocml_ilogb_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __finitef(float __x) { return __ocml_isfinite_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __isinff(float __x) { return __ocml_isinf_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __isnanf(float __x) { return __ocml_isnan_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float j0f(float __x) { return __ocml_j0_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float j1f(float __x) { return __ocml_j1_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float jnf(int __n, float __x) { - - - - if (__n == 0) - return j0f(__x); - if (__n == 1) - return j1f(__x); - - float __x0 = j0f(__x); - float __x1 = j1f(__x); - for (int __i = 1; __i < __n; ++__i) { - float __x2 = (2 * __i) / __x * __x1 - __x0; - __x0 = __x1; - __x1 = __x2; - } - - return __x1; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float ldexpf(float __x, int __e) { return __ocml_ldexp_f32(__x, __e); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float lgammaf(float __x) { return __ocml_lgamma_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long long int llrintf(float __x) { return __ocml_rint_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long long int llroundf(float __x) { return __ocml_round_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float log10f(float __x) { return __ocml_log10_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float log1pf(float __x) { return __ocml_log1p_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float log2f(float __x) { return __ocml_log2_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float log2fi(int __x) { return __ocml_log2_f32((float) __x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float logbf(float __x) { return __ocml_logb_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float logf(float __x) { return __ocml_log_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long int lrintf(float __x) { return __ocml_rint_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long int lroundf(float __x) { return __ocml_round_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float modff(float __x, float *__iptr) { - float __tmp; - - - - float __r = - __ocml_modf_f32(__x, (__attribute__((address_space(5))) float *)&__tmp); - *__iptr = __tmp; - return __r; -} - - - -static __attribute__((device)) inline __attribute__((always_inline)) -float nanf(const char *__tagp __attribute__((nonnull))) { - union { - float val; - struct ieee_float { - unsigned int mantissa : 22; - unsigned int quiet : 1; - unsigned int exponent : 8; - unsigned int sign : 1; - } bits; - } __tmp; - static_assert((sizeof(__tmp.val)) == (sizeof(__tmp.bits)), ""); - - __tmp.bits.sign = 0u; - __tmp.bits.exponent = ~0u; - __tmp.bits.quiet = 1u; - __tmp.bits.mantissa = __make_mantissa(__tagp); - - return __tmp.val; -} - - -static __attribute__((device)) inline __attribute__((always_inline)) -float nearbyintf(float __x) { return __ocml_nearbyint_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float nextafterf(float __x, float __y) { - return __ocml_nextafter_f32(__x, __y); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float norm3df(float __x, float __y, float __z) { - return __ocml_len3_f32(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float norm4df(float __x, float __y, float __z, float __w) { - return __ocml_len4_f32(__x, __y, __z, __w); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float normcdff(float __x) { return __ocml_ncdf_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float normcdfinvf(float __x) { return __ocml_ncdfinv_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float normf(int __dim, - const float *__a) { - float __r = 0; - while (__dim--) { - __r += __a[0] * __a[0]; - ++__a; - } - - return __ocml_sqrt_f32(__r); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float powf(float __x, float __y) { return __ocml_pow_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float powif(float __x, int __y) { return __ocml_pown_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -int powii(int __base, int __exp) { - if (__exp < 0 ) - return -1; - int __result = 1; - for (;;) { - if (__exp & 1) - __result *= __base; - __exp >>= 1; - if (!__exp) - break; - __base *= __base; - } - return __result; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float rcbrtf(float __x) { return __ocml_rcbrt_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float remainderf(float __x, float __y) { - return __ocml_remainder_f32(__x, __y); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float remquof(float __x, float __y, int *__quo) { - int __tmp; - - - - float __r = __ocml_remquo_f32( - __x, __y, (__attribute__((address_space(5))) int *)&__tmp); - *__quo = __tmp; - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float rhypotf(float __x, float __y) { return __ocml_rhypot_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float rintf(float __x) { return __ocml_rint_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float rnorm3df(float __x, float __y, float __z) { - return __ocml_rlen3_f32(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float rnorm4df(float __x, float __y, float __z, float __w) { - return __ocml_rlen4_f32(__x, __y, __z, __w); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float rnormf(int __dim, - const float *__a) { - float __r = 0; - while (__dim--) { - __r += __a[0] * __a[0]; - ++__a; - } - - return __ocml_rsqrt_f32(__r); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float roundf(float __x) { return __ocml_round_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float rsqrtf(float __x) { return __ocml_rsqrt_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float scalblnf(float __x, long int __n) { - return (__n < 9223372036854775807L) ? __ocml_scalbn_f32(__x, __n) - : __ocml_scalb_f32(__x, __n); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float scalbnf(float __x, int __n) { return __ocml_scalbn_f32(__x, __n); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __signbitf(float __x) { return __ocml_signbit_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -void sincosf(float __x, float *__sinptr, float *__cosptr) { - float __tmp; - - - - *__sinptr = - __ocml_sincos_f32(__x, (__attribute__((address_space(5))) float *)&__tmp); - *__cosptr = __tmp; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -void sincospif(float __x, float *__sinptr, float *__cosptr) { - float __tmp; - - - - *__sinptr = __ocml_sincospi_f32( - __x, (__attribute__((address_space(5))) float *)&__tmp); - *__cosptr = __tmp; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float sinf(float __x) { return __ocml_sin_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float sinhf(float __x) { return __ocml_sinh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float sinpif(float __x) { return __ocml_sinpi_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float sqrtf(float __x) { return __ocml_sqrt_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float tanf(float __x) { return __ocml_tan_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float tanhf(float __x) { return __ocml_tanh_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float tgammaf(float __x) { return __ocml_tgamma_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float truncf(float __x) { return __ocml_trunc_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float y0f(float __x) { return __ocml_y0_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float y1f(float __x) { return __ocml_y1_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float ynf(int __n, float __x) { - - - - - if (__n == 0) - return y0f(__x); - if (__n == 1) - return y1f(__x); - - float __x0 = y0f(__x); - float __x1 = y1f(__x); - for (int __i = 1; __i < __n; ++__i) { - float __x2 = (2 * __i) / __x * __x1 - __x0; - __x0 = __x1; - __x1 = __x2; - } - - return __x1; -} - - - -static __attribute__((device)) inline __attribute__((always_inline)) -float __cosf(float __x) { return __ocml_native_cos_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __exp10f(float __x) { return __ocml_native_exp10_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __expf(float __x) { return __ocml_native_exp_f32(__x); } -# 627 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fadd_rn(float __x, float __y) { return __x + __y; } -# 641 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fdiv_rn(float __x, float __y) { return __x / __y; } - - -static __attribute__((device)) inline __attribute__((always_inline)) -float __fdividef(float __x, float __y) { return __x / __y; } -# 666 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fmaf_rn(float __x, float __y, float __z) { - return __ocml_fma_f32(__x, __y, __z); -} -# 682 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fmul_rn(float __x, float __y) { return __x * __y; } -# 696 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __frcp_rn(float __x) { return 1.0f / __x; } - - -static __attribute__((device)) inline __attribute__((always_inline)) -float __frsqrt_rn(float __x) { return __llvm_amdgcn_rsq_f32(__x); } -# 713 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fsqrt_rn(float __x) { return __ocml_native_sqrt_f32(__x); } -# 727 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -float __fsub_rn(float __x, float __y) { return __x - __y; } - - -static __attribute__((device)) inline __attribute__((always_inline)) -float __log10f(float __x) { return __ocml_native_log10_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __log2f(float __x) { return __ocml_native_log2_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __logf(float __x) { return __ocml_native_log_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __powf(float __x, float __y) { return __ocml_pow_f32(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __saturatef(float __x) { return (__x < 0) ? 0 : ((__x > 1) ? 1 : __x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -void __sincosf(float __x, float *__sinptr, float *__cosptr) { - *__sinptr = __ocml_native_sin_f32(__x); - *__cosptr = __ocml_native_cos_f32(__x); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float __sinf(float __x) { return __ocml_native_sin_f32(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float __tanf(float __x) { return __ocml_tan_f32(__x); } - - - - -static __attribute__((device)) inline __attribute__((always_inline)) -double acos(double __x) { return __ocml_acos_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double acosh(double __x) { return __ocml_acosh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double asin(double __x) { return __ocml_asin_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double asinh(double __x) { return __ocml_asinh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double atan(double __x) { return __ocml_atan_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double atan2(double __x, double __y) { return __ocml_atan2_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double atanh(double __x) { return __ocml_atanh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double cbrt(double __x) { return __ocml_cbrt_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double ceil(double __x) { return __ocml_ceil_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double copysign(double __x, double __y) { - return __ocml_copysign_f64(__x, __y); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double cos(double __x) { return __ocml_cos_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double cosh(double __x) { return __ocml_cosh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double cospi(double __x) { return __ocml_cospi_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double cyl_bessel_i0(double __x) { return __ocml_i0_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double cyl_bessel_i1(double __x) { return __ocml_i1_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double erf(double __x) { return __ocml_erf_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double erfc(double __x) { return __ocml_erfc_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double erfcinv(double __x) { return __ocml_erfcinv_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double erfcx(double __x) { return __ocml_erfcx_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double erfinv(double __x) { return __ocml_erfinv_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double exp(double __x) { return __ocml_exp_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double exp10(double __x) { return __ocml_exp10_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double exp2(double __x) { return __ocml_exp2_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double expm1(double __x) { return __ocml_expm1_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double fabs(double __x) { return __builtin_fabs(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double fdim(double __x, double __y) { return __ocml_fdim_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double floor(double __x) { return __ocml_floor_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double fma(double __x, double __y, double __z) { - return __ocml_fma_f64(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double fmax(double __x, double __y) { return __ocml_fmax_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double fmin(double __x, double __y) { return __ocml_fmin_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double fmod(double __x, double __y) { return __ocml_fmod_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double frexp(double __x, int *__nptr) { - int __tmp; - - - - double __r = - __ocml_frexp_f64(__x, (__attribute__((address_space(5))) int *)&__tmp); - *__nptr = __tmp; - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double hypot(double __x, double __y) { return __ocml_hypot_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -int ilogb(double __x) { return __ocml_ilogb_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __finite(double __x) { return __ocml_isfinite_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __isinf(double __x) { return __ocml_isinf_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __isnan(double __x) { return __ocml_isnan_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double j0(double __x) { return __ocml_j0_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double j1(double __x) { return __ocml_j1_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double jn(int __n, double __x) { - - - - - if (__n == 0) - return j0(__x); - if (__n == 1) - return j1(__x); - - double __x0 = j0(__x); - double __x1 = j1(__x); - for (int __i = 1; __i < __n; ++__i) { - double __x2 = (2 * __i) / __x * __x1 - __x0; - __x0 = __x1; - __x1 = __x2; - } - return __x1; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double ldexp(double __x, int __e) { return __ocml_ldexp_f64(__x, __e); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double lgamma(double __x) { return __ocml_lgamma_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long long int llrint(double __x) { return __ocml_rint_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long long int llround(double __x) { return __ocml_round_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double log(double __x) { return __ocml_log_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double log10(double __x) { return __ocml_log10_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double log1p(double __x) { return __ocml_log1p_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double log2(double __x) { return __ocml_log2_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double logb(double __x) { return __ocml_logb_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long int lrint(double __x) { return __ocml_rint_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -long int lround(double __x) { return __ocml_round_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double modf(double __x, double *__iptr) { - double __tmp; - - - - double __r = - __ocml_modf_f64(__x, (__attribute__((address_space(5))) double *)&__tmp); - *__iptr = __tmp; - - return __r; -} - - - -static __attribute__((device)) inline __attribute__((always_inline)) -double nan(const char *__tagp) { - - union { - double val; - struct ieee_double { - long unsigned int mantissa : 51; - unsigned int quiet : 1; - unsigned int exponent : 11; - unsigned int sign : 1; - } bits; - } __tmp; - static_assert((sizeof(__tmp.val)) == (sizeof(__tmp.bits)), ""); - - __tmp.bits.sign = 0u; - __tmp.bits.exponent = ~0u; - __tmp.bits.quiet = 1u; - __tmp.bits.mantissa = __make_mantissa(__tagp); - - return __tmp.val; - - - - - - -} - - -static __attribute__((device)) inline __attribute__((always_inline)) -double nearbyint(double __x) { return __ocml_nearbyint_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double nextafter(double __x, double __y) { - return __ocml_nextafter_f64(__x, __y); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double norm(int __dim, - const double *__a) { - double __r = 0; - while (__dim--) { - __r += __a[0] * __a[0]; - ++__a; - } - - return __ocml_sqrt_f64(__r); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double norm3d(double __x, double __y, double __z) { - return __ocml_len3_f64(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double norm4d(double __x, double __y, double __z, double __w) { - return __ocml_len4_f64(__x, __y, __z, __w); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double normcdf(double __x) { return __ocml_ncdf_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double normcdfinv(double __x) { return __ocml_ncdfinv_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double pow(double __x, double __y) { return __ocml_pow_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double powi(double __x, int __y) { return __ocml_pown_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double rcbrt(double __x) { return __ocml_rcbrt_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double remainder(double __x, double __y) { - return __ocml_remainder_f64(__x, __y); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double remquo(double __x, double __y, int *__quo) { - int __tmp; - - - - double __r = __ocml_remquo_f64( - __x, __y, (__attribute__((address_space(5))) int *)&__tmp); - *__quo = __tmp; - - return __r; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double rhypot(double __x, double __y) { return __ocml_rhypot_f64(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double rint(double __x) { return __ocml_rint_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double rnorm(int __dim, - const double *__a) { - double __r = 0; - while (__dim--) { - __r += __a[0] * __a[0]; - ++__a; - } - - return __ocml_rsqrt_f64(__r); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double rnorm3d(double __x, double __y, double __z) { - return __ocml_rlen3_f64(__x, __y, __z); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double rnorm4d(double __x, double __y, double __z, double __w) { - return __ocml_rlen4_f64(__x, __y, __z, __w); -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double round(double __x) { return __ocml_round_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double rsqrt(double __x) { return __ocml_rsqrt_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double scalbln(double __x, long int __n) { - return (__n < 9223372036854775807L) ? __ocml_scalbn_f64(__x, __n) - : __ocml_scalb_f64(__x, __n); -} -static __attribute__((device)) inline __attribute__((always_inline)) -double scalbn(double __x, int __n) { return __ocml_scalbn_f64(__x, __n); } - -static __attribute__((device)) inline __attribute__((always_inline)) -bool __signbit(double __x) { return __ocml_signbit_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double sin(double __x) { return __ocml_sin_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -void sincos(double __x, double *__sinptr, double *__cosptr) { - double __tmp; - - - - *__sinptr = __ocml_sincos_f64( - __x, (__attribute__((address_space(5))) double *)&__tmp); - *__cosptr = __tmp; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -void sincospi(double __x, double *__sinptr, double *__cosptr) { - double __tmp; - - - - *__sinptr = __ocml_sincospi_f64( - __x, (__attribute__((address_space(5))) double *)&__tmp); - *__cosptr = __tmp; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -double sinh(double __x) { return __ocml_sinh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double sinpi(double __x) { return __ocml_sinpi_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double sqrt(double __x) { return __ocml_sqrt_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double tan(double __x) { return __ocml_tan_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double tanh(double __x) { return __ocml_tanh_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double tgamma(double __x) { return __ocml_tgamma_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double trunc(double __x) { return __ocml_trunc_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double y0(double __x) { return __ocml_y0_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double y1(double __x) { return __ocml_y1_f64(__x); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double yn(int __n, double __x) { - - - - - if (__n == 0) - return y0(__x); - if (__n == 1) - return y1(__x); - - double __x0 = y0(__x); - double __x1 = y1(__x); - for (int __i = 1; __i < __n; ++__i) { - double __x2 = (2 * __i) / __x * __x1 - __x0; - __x0 = __x1; - __x1 = __x2; - } - - return __x1; -} -# 1190 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __dadd_rn(double __x, double __y) { return __x + __y; } -# 1212 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __ddiv_rn(double __x, double __y) { return __x / __y; } -# 1234 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __dmul_rn(double __x, double __y) { return __x * __y; } -# 1248 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __drcp_rn(double __x) { return 1.0 / __x; } -# 1262 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __dsqrt_rn(double __x) { return __ocml_sqrt_f64(__x); } -# 1284 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __dsub_rn(double __x, double __y) { return __x - __y; } -# 1306 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) -double __fma_rn(double __x, double __y, double __z) { - return __ocml_fma_f64(__x, __y, __z); -} -# 1325 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_math.h" 3 -template static __attribute__((device)) inline __attribute__((always_inline)) T min(T __arg1, T __arg2) { - return (__arg1 < __arg2) ? __arg1 : __arg2; -} - -template static __attribute__((device)) inline __attribute__((always_inline)) T max(T __arg1, T __arg2) { - return (__arg1 > __arg2) ? __arg1 : __arg2; -} - - -static __attribute__((device)) inline __attribute__((always_inline)) int min(int __arg1, int __arg2) { - return (__arg1 < __arg2) ? __arg1 : __arg2; -} -static __attribute__((device)) inline __attribute__((always_inline)) int max(int __arg1, int __arg2) { - return (__arg1 > __arg2) ? __arg1 : __arg2; -} - -static __attribute__((device)) inline __attribute__((always_inline)) -float max(float __x, float __y) { return fmaxf(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double max(double __x, double __y) { return fmax(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -float min(float __x, float __y) { return fminf(__x, __y); } - -static __attribute__((device)) inline __attribute__((always_inline)) -double min(double __x, double __y) { return fmin(__x, __y); } -# 129 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 2 3 -# 1 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_stdlib.h" 1 3 -# 130 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 2 3 - - -# 1 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 1 3 -# 41 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) double abs(double __x) { return ::fabs(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float abs(float __x) { return ::fabsf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) long long abs(long long __n) { return ::llabs(__n); } -static __attribute__((device)) inline __attribute__((always_inline)) long abs(long __n) { return ::labs(__n); } -static __attribute__((device)) inline __attribute__((always_inline)) float fma(float __x, float __y, float __z) { - return ::fmaf(__x, __y, __z); -} -# 61 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) float frexp(float __arg, int *__exp) { - return ::frexpf(__arg, __exp); -} -# 93 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) bool isinf(float __x) { return ::__isinff(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool isinf(double __x) { return ::__isinf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool isfinite(float __x) { return ::__finitef(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool isfinite(double __x) { return ::__finite(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool isnan(float __x) { return ::__isnanf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool isnan(double __x) { return ::__isnan(__x); } - - - - - -static __attribute__((device)) inline __attribute__((always_inline)) bool isgreater(float __x, float __y) { - return __builtin_isgreater(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isgreater(double __x, double __y) { - return __builtin_isgreater(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isgreaterequal(float __x, float __y) { - return __builtin_isgreaterequal(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isgreaterequal(double __x, double __y) { - return __builtin_isgreaterequal(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isless(float __x, float __y) { - return __builtin_isless(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isless(double __x, double __y) { - return __builtin_isless(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool islessequal(float __x, float __y) { - return __builtin_islessequal(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool islessequal(double __x, double __y) { - return __builtin_islessequal(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool islessgreater(float __x, float __y) { - return __builtin_islessgreater(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool islessgreater(double __x, double __y) { - return __builtin_islessgreater(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isnormal(float __x) { - return __builtin_isnormal(__x); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isnormal(double __x) { - return __builtin_isnormal(__x); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isunordered(float __x, float __y) { - return __builtin_isunordered(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool isunordered(double __x, double __y) { - return __builtin_isunordered(__x, __y); -} -static __attribute__((device)) inline __attribute__((always_inline)) float modf(float __x, float *__iptr) { - return ::modff(__x, __iptr); -} -static __attribute__((device)) inline __attribute__((always_inline)) float pow(float __base, int __iexp) { - return ::powif(__base, __iexp); -} -static __attribute__((device)) inline __attribute__((always_inline)) double pow(double __base, int __iexp) { - return ::powi(__base, __iexp); -} -static __attribute__((device)) inline __attribute__((always_inline)) float remquo(float __x, float __y, int *__quo) { - return ::remquof(__x, __y, __quo); -} -static __attribute__((device)) inline __attribute__((always_inline)) float scalbln(float __x, long int __n) { - return ::scalblnf(__x, __n); -} -static __attribute__((device)) inline __attribute__((always_inline)) bool signbit(float __x) { return ::__signbitf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) bool signbit(double __x) { return ::__signbit(__x); } - - - - - - -static __attribute__((device)) inline __attribute__((always_inline)) _Float16 fma(_Float16 __x, _Float16 __y, - _Float16 __z) { - return __ocml_fma_f16(__x, __y, __z); -} -static __attribute__((device)) inline __attribute__((always_inline)) _Float16 pow(_Float16 __base, int __iexp) { - return __ocml_pown_f16(__base, __iexp); -} -# 202 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -static __attribute__((device)) inline __attribute__((always_inline)) float acos(float __x) { return acosf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float acosh(float __x) { return acoshf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float asin(float __x) { return asinf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float asinh(float __x) { return asinhf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float atan(float __x) { return atanf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float atan2(float __x, float __y) { return atan2f(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float atanh(float __x) { return atanhf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float cbrt(float __x) { return cbrtf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float ceil(float __x) { return ceilf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float copysign(float __x, float __y) { return copysignf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float cos(float __x) { return cosf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float cosh(float __x) { return coshf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float erf(float __x) { return erff(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float erfc(float __x) { return erfcf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float exp(float __x) { return expf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float exp2(float __x) { return exp2f(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float expm1(float __x) { return expm1f(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float fabs(float __x) { return fabsf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float fdim(float __x, float __y) { return fdimf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float floor(float __x) { return floorf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float fmax(float __x, float __y) { return fmaxf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float fmin(float __x, float __y) { return fminf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float fmod(float __x, float __y) { return fmodf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float hypot(float __x, float __y) { return hypotf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) int ilogb(float __x) { return ilogbf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float ldexp(float __x, int __y) { return ldexpf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float lgamma(float __x) { return lgammaf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float log(float __x) { return logf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float log10(float __x) { return log10f(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float log1p(float __x) { return log1pf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float log2(float __x) { return log2f(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float logb(float __x) { return logbf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) long long llrint(float __x) { return llrintf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) long long llround(float __x) { return llroundf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) long lrint(float __x) { return lrintf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) long lround(float __x) { return lroundf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float nearbyint(float __x) { return nearbyintf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float nextafter(float __x, float __y) { return nextafterf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float pow(float __x, float __y) { return powf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float remainder(float __x, float __y) { return remainderf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float rint(float __x) { return rintf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float round(float __x) { return roundf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float scalbn(float __x, int __y) { return scalbnf(__x, __y); } -static __attribute__((device)) inline __attribute__((always_inline)) float sin(float __x) { return sinf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float sinh(float __x) { return sinhf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float sqrt(float __x) { return sqrtf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float tan(float __x) { return tanf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float tanh(float __x) { return tanhf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float tgamma(float __x) { return tgammaf(__x); } -static __attribute__((device)) inline __attribute__((always_inline)) float trunc(float __x) { return truncf(__x); } -# 265 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -template struct __hip_enable_if {}; - -template struct __hip_enable_if { typedef __T type; }; - -namespace __hip { -template struct is_integral { - enum { value = 0 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; -template <> struct is_integral { - enum { value = 1 }; -}; - - -template struct is_arithmetic { - enum { value = 0 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; -template <> struct is_arithmetic { - enum { value = 1 }; -}; - -struct true_type { - static const __attribute__((constant)) bool value = true; -}; -struct false_type { - static const __attribute__((constant)) bool value = false; -}; - -template struct is_same : public false_type {}; -template struct is_same<__T, __T> : public true_type {}; - -template struct add_rvalue_reference { typedef __T &&type; }; - -template typename add_rvalue_reference<__T>::type declval(); - - - - -template struct __numeric_type { - static void __test(...); - static _Float16 __test(_Float16); - static float __test(float); - static double __test(char); - static double __test(int); - static double __test(unsigned); - static double __test(long); - static double __test(unsigned long); - static double __test(long long); - static double __test(unsigned long long); - static double __test(double); - - static double __test(long double); - - typedef decltype(__test(declval<_Tp>())) type; - static const bool value = !is_same::value; -}; - -template <> struct __numeric_type { static const bool value = true; }; - -template ::value &&__numeric_type<_A2>::value - &&__numeric_type<_A3>::value> -class __promote_imp { -public: - static const bool value = false; -}; - -template -class __promote_imp<_A1, _A2, _A3, true> { -private: - typedef typename __promote_imp<_A1>::type __type1; - typedef typename __promote_imp<_A2>::type __type2; - typedef typename __promote_imp<_A3>::type __type3; - -public: - typedef decltype(__type1() + __type2() + __type3()) type; - static const bool value = true; -}; - -template class __promote_imp<_A1, _A2, void, true> { -private: - typedef typename __promote_imp<_A1>::type __type1; - typedef typename __promote_imp<_A2>::type __type2; - -public: - typedef decltype(__type1() + __type2()) type; - static const bool value = true; -}; - -template class __promote_imp<_A1, void, void, true> { -public: - typedef typename __numeric_type<_A1>::type type; - static const bool value = true; -}; - -template -class __promote : public __promote_imp<_A1, _A2, _A3> {}; - -} -# 478 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type acos(__T __x) { return ::acos((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type acosh(__T __x) { return ::acosh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type asin(__T __x) { return ::asin((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type asinh(__T __x) { return ::asinh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type atan(__T __x) { return ::atan((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type atan2(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return atan2((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type atanh(__T __x) { return ::atanh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type cbrt(__T __x) { return ::cbrt((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type ceil(__T __x) { return ::ceil((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type copysign(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return copysign((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type cos(__T __x) { return ::cos((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type cosh(__T __x) { return ::cosh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type erf(__T __x) { return ::erf((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type erfc(__T __x) { return ::erfc((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type exp(__T __x) { return ::exp((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type exp2(__T __x) { return ::exp2((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type expm1(__T __x) { return ::expm1((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type fabs(__T __x) { return ::fabs((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type fdim(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return fdim((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type floor(__T __x) { return ::floor((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type fmax(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return fmax((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type fmin(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return fmin((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type fmod(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return fmod((__result_type)__x, (__result_type)__y); } - - - -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type hypot(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return hypot((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, int>::type ilogb(__T __x) { return ::ilogb((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, bool>::type isfinite(__T __x) { return ::isfinite((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type isgreater(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return isgreater((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type isgreaterequal(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return isgreaterequal((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, bool>::type isinf(__T __x) { return ::isinf((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type isless(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return isless((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type islessequal(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return islessequal((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type islessgreater(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return islessgreater((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, bool>::type isnan(__T __x) { return ::isnan((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, bool>::type isnormal(__T __x) { return ::isnormal((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type isunordered(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return isunordered((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type lgamma(__T __x) { return ::lgamma((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type log(__T __x) { return ::log((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type log10(__T __x) { return ::log10((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type log1p(__T __x) { return ::log1p((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type log2(__T __x) { return ::log2((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type logb(__T __x) { return ::logb((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, long long>::type llrint(__T __x) { return ::llrint((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, long long>::type llround(__T __x) { return ::llround((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, long>::type lrint(__T __x) { return ::lrint((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, long>::type lround(__T __x) { return ::lround((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type nearbyint(__T __x) { return ::nearbyint((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type nextafter(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return nextafter((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type pow(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return pow((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type remainder(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return remainder((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type rint(__T __x) { return ::rint((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type round(__T __x) { return ::round((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, bool>::type signbit(__T __x) { return ::signbit((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type sin(__T __x) { return ::sin((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type sinh(__T __x) { return ::sinh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type sqrt(__T __x) { return ::sqrt((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type tan(__T __x) { return ::tan((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type tanh(__T __x) { return ::tanh((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type tgamma(__T __x) { return ::tgamma((double)__x); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type trunc(__T __x) { return ::trunc((double)__x); } - - -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type max(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return max((__result_type)__x, (__result_type)__y); } -template static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value, typename __hip::__promote<__T1, __T2>::type>::type min(__T1 __x, __T2 __y) { typedef typename __hip::__promote<__T1, __T2>::type __result_type; return min((__result_type)__x, (__result_type)__y); } - - - -template -static __attribute__((device)) inline __attribute__((always_inline)) typename __hip_enable_if< - __hip::is_arithmetic<__T1>::value && __hip::is_arithmetic<__T2>::value && - __hip::is_arithmetic<__T3>::value, - typename __hip::__promote<__T1, __T2, __T3>::type>::type -fma(__T1 __x, __T2 __y, __T3 __z) { - typedef typename __hip::__promote<__T1, __T2, __T3>::type __result_type; - return ::fma((__result_type)__x, (__result_type)__y, (__result_type)__z); -} -# 568 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type - frexp(__T __x, int *__exp) { - return ::frexp((double)__x, __exp); -} - -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type - ldexp(__T __x, int __exp) { - return ::ldexp((double)__x, __exp); -} - -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type - modf(__T __x, double *__exp) { - return ::modf((double)__x, __exp); -} - - -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_arithmetic<__T1>::value && - __hip::is_arithmetic<__T2>::value, - typename __hip::__promote<__T1, __T2>::type>::type - remquo(__T1 __x, __T2 __y, int *__quo) { - typedef typename __hip::__promote<__T1, __T2>::type __result_type; - return ::remquo((__result_type)__x, (__result_type)__y, __quo); -} -# 610 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_cmath.h" 3 -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type - scalbln(__T __x, long int __exp) { - return ::scalbln((double)__x, __exp); -} - -template -static __attribute__((device)) inline __attribute__((always_inline)) - typename __hip_enable_if<__hip::is_integral<__T>::value, double>::type - scalbn(__T __x, int __exp) { - return ::scalbn((double)__x, __exp); -} -# 133 "/opt/rocm-6.0.0/lib/llvm/lib/clang/17.0.0/include/__clang_hip_runtime_wrapper.h" 2 3 -# 2 "" 2 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/out/ubuntu-22.04/22.04/build/hip-on-rocclr/hipamd/src/hiprtc/hip_rtc_gen/hipRTC_header.h" 2 - - - - -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 1 3 -# 58 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/out/ubuntu-22.04/22.04/build/hip-on-rocclr/hipamd/include/hip/hip_version.h" 1 3 -# 59 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 2 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_common.h" 1 3 -# 27 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_common.h" 3 -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wreserved-macro-identifier" -# 97 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_common.h" 3 -#pragma clang diagnostic pop -# 60 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 2 3 - - -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 1 3 -# 32 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_common.h" 1 3 -# 33 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 2 3 -# 43 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -extern "C" { -# 54 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -const char* amd_dbgapi_get_build_name(); -# 63 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -const char* amd_dbgapi_get_git_hash(); -# 72 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -size_t amd_dbgapi_get_build_id(); - - -} -# 92 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; -typedef signed int int32_t; -typedef signed long long int64_t; -namespace std { -using ::uint32_t; -using ::uint64_t; -using ::int32_t; -using ::int64_t; -} -# 124 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/hip_ldg.h" 1 3 -# 27 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/hip_ldg.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 1 3 -# 31 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/host_defines.h" 1 3 -# 38 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/host_defines.h" 3 -namespace __hip_internal { -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; -typedef signed char int8_t; -typedef signed short int16_t; -typedef signed int int32_t; -typedef signed long long int64_t; - -template struct integral_constant { - static constexpr const _Tp value = __v; - typedef _Tp value_type; - typedef integral_constant type; - constexpr operator value_type() const { return value; } - constexpr value_type operator()() const { return value; } -}; -template constexpr const _Tp integral_constant<_Tp, __v>::value; - -typedef integral_constant true_type; -typedef integral_constant false_type; - -template using bool_constant = integral_constant; -typedef bool_constant true_type; -typedef bool_constant false_type; - -template struct enable_if {}; -template struct enable_if { typedef __T type; }; - -template struct true_or_false_type : public false_type {}; -template<> struct true_or_false_type : public true_type {}; - -template struct is_integral : public false_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; - -template struct is_arithmetic : public false_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; - -template struct is_floating_point : public false_type {}; -template<> struct is_floating_point : public true_type {}; -template<> struct is_floating_point : public true_type {}; -template<> struct is_floating_point : public true_type {}; - -template struct is_same : public false_type {}; -template struct is_same<__T, __T> : public true_type {}; - -template::value> - struct is_signed : public false_type {}; -template - struct is_signed<_Tp, true> : public true_or_false_type<_Tp(-1) < _Tp(0)> {}; - -template struct char_traits; -template> class basic_istream; -template> class basic_ostream; -typedef basic_istream istream; -typedef basic_ostream ostream; - -template - struct is_standard_layout - : public integral_constant - { }; - -template - struct is_trivial - : public integral_constant - { }; -} -typedef __hip_internal::uint8_t __hip_uint8_t; -typedef __hip_internal::uint16_t __hip_uint16_t; -typedef __hip_internal::uint32_t __hip_uint32_t; -typedef __hip_internal::uint64_t __hip_uint64_t; -typedef __hip_internal::int8_t __hip_int8_t; -typedef __hip_internal::int16_t __hip_int16_t; -typedef __hip_internal::int32_t __hip_int32_t; -typedef __hip_internal::int64_t __hip_int64_t; -# 32 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 2 3 -# 52 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 3 -namespace std { -using ::size_t; - -template struct integral_constant { - static constexpr const _Tp value = __v; - typedef _Tp value_type; - typedef integral_constant type; - constexpr operator value_type() const { return value; } - constexpr value_type operator()() const { return value; } -}; -template constexpr const _Tp integral_constant<_Tp, __v>::value; - -typedef integral_constant true_type; -typedef integral_constant false_type; - -template using bool_constant = integral_constant; -typedef bool_constant true_type; -typedef bool_constant false_type; - -template struct enable_if {}; -template struct enable_if { typedef __T type; }; - -template struct true_or_false_type : public false_type {}; -template<> struct true_or_false_type : public true_type {}; - -template struct is_integral : public false_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; -template <> struct is_integral : public true_type {}; - -template struct is_arithmetic : public false_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; -template <> struct is_arithmetic : public true_type {}; - -template struct is_floating_point : public false_type {}; -template<> struct is_floating_point : public true_type {}; -template<> struct is_floating_point : public true_type {}; -template<> struct is_floating_point : public true_type {}; - -template struct is_same : public false_type {}; -template struct is_same<__T, __T> : public true_type {}; - -template::value> - struct is_signed : public false_type {}; -template - struct is_signed<_Tp, true> : public true_or_false_type<_Tp(-1) < _Tp(0)> {}; - -template struct is_convertible - : public true_or_false_type<__is_convertible_to(_T1, _T2)> {}; - -template struct char_traits; -template> class basic_istream; -template> class basic_ostream; -typedef basic_istream istream; -typedef basic_ostream ostream; - -template struct is_scalar : public integral_constant {}; -} - - - namespace hip_impl { - inline - constexpr - unsigned int next_pot(unsigned int x) { - - return 1u << (32u - __builtin_clz(x - 1u)); - } - } - - template struct HIP_vector_base; - - template - struct HIP_vector_base { - using Native_vec_ = T __attribute__((ext_vector_type(1))); - - union { - Native_vec_ data; - struct { - T x; - }; - }; - - using value_type = T; - - __attribute__((device)) - HIP_vector_base() = default; - __attribute__((device)) - explicit - constexpr - HIP_vector_base(T x_) noexcept : data{x_} {} - __attribute__((device)) - constexpr - HIP_vector_base(const HIP_vector_base&) = default; - __attribute__((device)) - constexpr - HIP_vector_base(HIP_vector_base&&) = default; - __attribute__((device)) - ~HIP_vector_base() = default; - __attribute__((device)) - HIP_vector_base& operator=(const HIP_vector_base&) = default; - }; - - template - struct HIP_vector_base { - using Native_vec_ = T __attribute__((ext_vector_type(2))); - - union - - - - { - Native_vec_ data; - struct { - T x; - T y; - }; - }; - - using value_type = T; - - __attribute__((device)) - HIP_vector_base() = default; - __attribute__((device)) - explicit - constexpr - HIP_vector_base(T x_) noexcept : data{x_, x_} {} - __attribute__((device)) - constexpr - HIP_vector_base(T x_, T y_) noexcept : data{x_, y_} {} - __attribute__((device)) - constexpr - HIP_vector_base(const HIP_vector_base&) = default; - __attribute__((device)) - constexpr - HIP_vector_base(HIP_vector_base&&) = default; - __attribute__((device)) - ~HIP_vector_base() = default; - __attribute__((device)) - HIP_vector_base& operator=(const HIP_vector_base&) = default; - }; - - template - struct HIP_vector_base { - struct Native_vec_ { - T d[3]; - - __attribute__((device)) - Native_vec_() = default; - - __attribute__((device)) - explicit - constexpr - Native_vec_(T x_) noexcept : d{x_, x_, x_} {} - __attribute__((device)) - constexpr - Native_vec_(T x_, T y_, T z_) noexcept : d{x_, y_, z_} {} - __attribute__((device)) - constexpr - Native_vec_(const Native_vec_&) = default; - __attribute__((device)) - constexpr - Native_vec_(Native_vec_&&) = default; - __attribute__((device)) - ~Native_vec_() = default; - - __attribute__((device)) - Native_vec_& operator=(const Native_vec_&) = default; - __attribute__((device)) - Native_vec_& operator=(Native_vec_&&) = default; - - __attribute__((device)) - T& operator[](unsigned int idx) noexcept { return d[idx]; } - __attribute__((device)) - T operator[](unsigned int idx) const noexcept { return d[idx]; } - - __attribute__((device)) - Native_vec_& operator+=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] += x_.d[i]; - return *this; - } - __attribute__((device)) - Native_vec_& operator-=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] -= x_.d[i]; - return *this; - } - - __attribute__((device)) - Native_vec_& operator*=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] *= x_.d[i]; - return *this; - } - __attribute__((device)) - Native_vec_& operator/=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] /= x_.d[i]; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_ operator-() const noexcept - { - auto r{*this}; - for (auto&& x : r.d) x = -x; - return r; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_ operator~() const noexcept - { - auto r{*this}; - for (auto&& x : r.d) x = ~x; - return r; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator%=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] %= x_.d[i]; - return *this; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator^=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] ^= x_.d[i]; - return *this; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator|=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] |= x_.d[i]; - return *this; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator&=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] &= x_.d[i]; - return *this; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator>>=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] >>= x_.d[i]; - return *this; - } - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - Native_vec_& operator<<=(const Native_vec_& x_) noexcept - { - for (auto i = 0u; i != 3u; ++i) d[i] <<= x_.d[i]; - return *this; - } - - - - - - - using Vec3_cmp = int __attribute__((vector_size(4 * sizeof(int)))); - - __attribute__((device)) - Vec3_cmp operator==(const Native_vec_& x_) const noexcept - { - return Vec3_cmp{d[0] == x_.d[0], d[1] == x_.d[1], d[2] == x_.d[2]}; - } - }; - - union { - Native_vec_ data; - struct { - T x; - T y; - T z; - }; - }; - - using value_type = T; - - __attribute__((device)) - HIP_vector_base() = default; - __attribute__((device)) - explicit - constexpr - HIP_vector_base(T x_) noexcept : data{x_, x_, x_} {} - __attribute__((device)) - constexpr - HIP_vector_base(T x_, T y_, T z_) noexcept : data{x_, y_, z_} {} - __attribute__((device)) - constexpr - HIP_vector_base(const HIP_vector_base&) = default; - __attribute__((device)) - constexpr - HIP_vector_base(HIP_vector_base&&) = default; - __attribute__((device)) - ~HIP_vector_base() = default; - - __attribute__((device)) - HIP_vector_base& operator=(const HIP_vector_base&) = default; - __attribute__((device)) - HIP_vector_base& operator=(HIP_vector_base&&) = default; - }; - - template - struct HIP_vector_base { - using Native_vec_ = T __attribute__((ext_vector_type(4))); - - union - - - - { - Native_vec_ data; - struct { - T x; - T y; - T z; - T w; - }; - }; - - using value_type = T; - - __attribute__((device)) - HIP_vector_base() = default; - __attribute__((device)) - explicit - constexpr - HIP_vector_base(T x_) noexcept : data{x_, x_, x_, x_} {} - __attribute__((device)) - constexpr - HIP_vector_base(T x_, T y_, T z_, T w_) noexcept : data{x_, y_, z_, w_} {} - __attribute__((device)) - constexpr - HIP_vector_base(const HIP_vector_base&) = default; - __attribute__((device)) - constexpr - HIP_vector_base(HIP_vector_base&&) = default; - __attribute__((device)) - ~HIP_vector_base() = default; - __attribute__((device)) - HIP_vector_base& operator=(const HIP_vector_base&) = default; - }; - - template - struct HIP_vector_type : public HIP_vector_base { - using HIP_vector_base::data; - using typename HIP_vector_base::Native_vec_; - - __attribute__((device)) - HIP_vector_type() = default; - template< - typename U, - typename std::enable_if< - std::is_convertible::value>::type* = nullptr> - __attribute__((device)) - explicit - constexpr - HIP_vector_type(U x_) noexcept - : HIP_vector_base{static_cast(x_)} - {} - template< - typename... Us, - typename std::enable_if< - (rank > 1) && sizeof...(Us) == rank>::type* = nullptr> - __attribute__((device)) - constexpr - HIP_vector_type(Us... xs) noexcept - : HIP_vector_base{static_cast(xs)...} - {} - __attribute__((device)) - constexpr - HIP_vector_type(const HIP_vector_type&) = default; - __attribute__((device)) - constexpr - HIP_vector_type(HIP_vector_type&&) = default; - __attribute__((device)) - ~HIP_vector_type() = default; - - __attribute__((device)) - HIP_vector_type& operator=(const HIP_vector_type&) = default; - __attribute__((device)) - HIP_vector_type& operator=(HIP_vector_type&&) = default; - - - __attribute__((device)) - HIP_vector_type& operator++() noexcept - { - return *this += HIP_vector_type{1}; - } - __attribute__((device)) - HIP_vector_type operator++(int) noexcept - { - auto tmp(*this); - ++*this; - return tmp; - } - - __attribute__((device)) - HIP_vector_type& operator--() noexcept - { - return *this -= HIP_vector_type{1}; - } - __attribute__((device)) - HIP_vector_type operator--(int) noexcept - { - auto tmp(*this); - --*this; - return tmp; - } - - __attribute__((device)) - HIP_vector_type& operator+=(const HIP_vector_type& x) noexcept - { - data += x.data; - return *this; - } - template< - typename U, - typename std::enable_if< - std::is_convertible{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator+=(U x) noexcept - { - return *this += HIP_vector_type{x}; - } - - __attribute__((device)) - HIP_vector_type& operator-=(const HIP_vector_type& x) noexcept - { - data -= x.data; - return *this; - } - template< - typename U, - typename std::enable_if< - std::is_convertible{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator-=(U x) noexcept - { - return *this -= HIP_vector_type{x}; - } - - __attribute__((device)) - HIP_vector_type& operator*=(const HIP_vector_type& x) noexcept - { - data *= x.data; - return *this; - } - - friend __attribute__((device)) inline constexpr HIP_vector_type operator*( - HIP_vector_type x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{ x } *= y; - } - - template< - typename U, - typename std::enable_if< - std::is_convertible{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator*=(U x) noexcept - { - return *this *= HIP_vector_type{x}; - } - - friend __attribute__((device)) inline constexpr HIP_vector_type operator/( - HIP_vector_type x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{ x } /= y; - } - - __attribute__((device)) - HIP_vector_type& operator/=(const HIP_vector_type& x) noexcept - { - data /= x.data; - return *this; - } - template< - typename U, - typename std::enable_if< - std::is_convertible{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator/=(U x) noexcept - { - return *this /= HIP_vector_type{x}; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type operator-() const noexcept - { - auto tmp(*this); - tmp.data = -tmp.data; - return tmp; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type operator~() const noexcept - { - HIP_vector_type r{*this}; - r.data = ~r.data; - return r; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator%=(const HIP_vector_type& x) noexcept - { - data %= x.data; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator^=(const HIP_vector_type& x) noexcept - { - data ^= x.data; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator|=(const HIP_vector_type& x) noexcept - { - data |= x.data; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator&=(const HIP_vector_type& x) noexcept - { - data &= x.data; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator>>=(const HIP_vector_type& x) noexcept - { - data >>= x.data; - return *this; - } - - template< - typename U = T, - typename std::enable_if{}>::type* = nullptr> - __attribute__((device)) - HIP_vector_type& operator<<=(const HIP_vector_type& x) noexcept - { - data <<= x.data; - return *this; - } - }; - - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator+( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} += y; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator+( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} += HIP_vector_type{y}; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator+( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} += y; - } - - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator-( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} -= y; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator-( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} -= HIP_vector_type{y}; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator-( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} -= y; - } - - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator*( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} *= HIP_vector_type{y}; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator*( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} *= y; - } - - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator/( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} /= HIP_vector_type{y}; - } - template - __attribute__((device)) - inline - constexpr - HIP_vector_type operator/( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} /= y; - } - - template - __attribute__((device)) - inline - constexpr - bool _hip_any_zero(const V& x, int n) noexcept - { - return - (n == -1) ? true : ((x[n] == 0) ? false : _hip_any_zero(x, n - 1)); - } - - template - __attribute__((device)) - inline - constexpr - bool operator==( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return _hip_any_zero(x.data == y.data, n - 1); - } - template - __attribute__((device)) - inline - constexpr - bool operator==(const HIP_vector_type& x, U y) noexcept - { - return x == HIP_vector_type{y}; - } - template - __attribute__((device)) - inline - constexpr - bool operator==(U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} == y; - } - - template - __attribute__((device)) - inline - constexpr - bool operator!=( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return !(x == y); - } - template - __attribute__((device)) - inline - constexpr - bool operator!=(const HIP_vector_type& x, U y) noexcept - { - return !(x == y); - } - template - __attribute__((device)) - inline - constexpr - bool operator!=(U x, const HIP_vector_type& y) noexcept - { - return !(x == y); - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator%( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} %= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator%( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} %= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator%( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} %= y; - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator^( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} ^= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator^( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} ^= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator^( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} ^= y; - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator|( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} |= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator|( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} |= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator|( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} |= y; - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator&( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} &= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator&( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} &= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator&( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} &= y; - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator>>( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} >>= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator>>( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} >>= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator>>( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} >>= y; - } - - template< - typename T, - unsigned int n, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator<<( - const HIP_vector_type& x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} <<= y; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator<<( - const HIP_vector_type& x, U y) noexcept - { - return HIP_vector_type{x} <<= HIP_vector_type{y}; - } - template< - typename T, - unsigned int n, - typename U, - typename std::enable_if::value>::type, - typename std::enable_if{}>* = nullptr> - __attribute__((device)) - inline - constexpr - HIP_vector_type operator<<( - U x, const HIP_vector_type& y) noexcept - { - return HIP_vector_type{x} <<= y; - } - - - - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 1 && rankU >= 1), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type(static_cast(u.x)); - }; - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 2 && rankU == 1), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type (static_cast(u.x), static_cast(0)); - }; - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 2 && rankU >= 2), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type (static_cast(u.x), static_cast(u.y)); - }; - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 4 && rankU == 1), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type (static_cast(u.x), static_cast(0), - static_cast(0), static_cast(0)); - }; - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 4 && rankU == 2), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type(static_cast(u.x), static_cast(u.y), - static_cast(0), static_cast(0)); - }; - - template - inline __attribute__((always_inline)) __attribute__((device)) typename std::enable_if<(rankT == 4 && rankU == 4), - const HIP_vector_type>::type - __hipMapVector(const HIP_vector_type& u) { - return HIP_vector_type (static_cast(u.x), static_cast(u.y), - static_cast(u.z), static_cast(u.w)); - }; -# 1135 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 3 -using uchar1 = HIP_vector_type; using uchar2 = HIP_vector_type; using uchar3 = HIP_vector_type; using uchar4 = HIP_vector_type;; -using char1 = HIP_vector_type; using char2 = HIP_vector_type; using char3 = HIP_vector_type; using char4 = HIP_vector_type;; -using ushort1 = HIP_vector_type; using ushort2 = HIP_vector_type; using ushort3 = HIP_vector_type; using ushort4 = HIP_vector_type;; -using short1 = HIP_vector_type; using short2 = HIP_vector_type; using short3 = HIP_vector_type; using short4 = HIP_vector_type;; -using uint1 = HIP_vector_type; using uint2 = HIP_vector_type; using uint3 = HIP_vector_type; using uint4 = HIP_vector_type;; -using int1 = HIP_vector_type; using int2 = HIP_vector_type; using int3 = HIP_vector_type; using int4 = HIP_vector_type;; -using ulong1 = HIP_vector_type; using ulong2 = HIP_vector_type; using ulong3 = HIP_vector_type; using ulong4 = HIP_vector_type;; -using long1 = HIP_vector_type; using long2 = HIP_vector_type; using long3 = HIP_vector_type; using long4 = HIP_vector_type;; -using ulonglong1 = HIP_vector_type; using ulonglong2 = HIP_vector_type; using ulonglong3 = HIP_vector_type; using ulonglong4 = HIP_vector_type;; -using longlong1 = HIP_vector_type; using longlong2 = HIP_vector_type; using longlong3 = HIP_vector_type; using longlong4 = HIP_vector_type;; -using float1 = HIP_vector_type; using float2 = HIP_vector_type; using float3 = HIP_vector_type; using float4 = HIP_vector_type;; -using double1 = HIP_vector_type; using double2 = HIP_vector_type; using double3 = HIP_vector_type; using double4 = HIP_vector_type;; -# 2117 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_vector_types.h" 3 -static inline __attribute__((device)) uchar1 make_uchar1(unsigned char x) { uchar1 r{x}; return r; }; -static inline __attribute__((device)) uchar2 make_uchar2(unsigned char x, unsigned char y) { uchar2 r{x, y}; return r; }; -static inline __attribute__((device)) uchar3 make_uchar3(unsigned char x, unsigned char y, unsigned char z) { uchar3 r{x, y, z}; return r; }; -static inline __attribute__((device)) uchar4 make_uchar4(unsigned char x, unsigned char y, unsigned char z, unsigned char w) { uchar4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) char1 make_char1(signed char x) { char1 r{x}; return r; }; -static inline __attribute__((device)) char2 make_char2(signed char x, signed char y) { char2 r{x, y}; return r; }; -static inline __attribute__((device)) char3 make_char3(signed char x, signed char y, signed char z) { char3 r{x, y, z}; return r; }; -static inline __attribute__((device)) char4 make_char4(signed char x, signed char y, signed char z, signed char w) { char4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) ushort1 make_ushort1(unsigned short x) { ushort1 r{x}; return r; }; -static inline __attribute__((device)) ushort2 make_ushort2(unsigned short x, unsigned short y) { ushort2 r{x, y}; return r; }; -static inline __attribute__((device)) ushort3 make_ushort3(unsigned short x, unsigned short y, unsigned short z) { ushort3 r{x, y, z}; return r; }; -static inline __attribute__((device)) ushort4 make_ushort4(unsigned short x, unsigned short y, unsigned short z, unsigned short w) { ushort4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) short1 make_short1(signed short x) { short1 r{x}; return r; }; -static inline __attribute__((device)) short2 make_short2(signed short x, signed short y) { short2 r{x, y}; return r; }; -static inline __attribute__((device)) short3 make_short3(signed short x, signed short y, signed short z) { short3 r{x, y, z}; return r; }; -static inline __attribute__((device)) short4 make_short4(signed short x, signed short y, signed short z, signed short w) { short4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) uint1 make_uint1(unsigned int x) { uint1 r{x}; return r; }; -static inline __attribute__((device)) uint2 make_uint2(unsigned int x, unsigned int y) { uint2 r{x, y}; return r; }; -static inline __attribute__((device)) uint3 make_uint3(unsigned int x, unsigned int y, unsigned int z) { uint3 r{x, y, z}; return r; }; -static inline __attribute__((device)) uint4 make_uint4(unsigned int x, unsigned int y, unsigned int z, unsigned int w) { uint4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) int1 make_int1(signed int x) { int1 r{x}; return r; }; -static inline __attribute__((device)) int2 make_int2(signed int x, signed int y) { int2 r{x, y}; return r; }; -static inline __attribute__((device)) int3 make_int3(signed int x, signed int y, signed int z) { int3 r{x, y, z}; return r; }; -static inline __attribute__((device)) int4 make_int4(signed int x, signed int y, signed int z, signed int w) { int4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) float1 make_float1(float x) { float1 r{x}; return r; }; -static inline __attribute__((device)) float2 make_float2(float x, float y) { float2 r{x, y}; return r; }; -static inline __attribute__((device)) float3 make_float3(float x, float y, float z) { float3 r{x, y, z}; return r; }; -static inline __attribute__((device)) float4 make_float4(float x, float y, float z, float w) { float4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) double1 make_double1(double x) { double1 r{x}; return r; }; -static inline __attribute__((device)) double2 make_double2(double x, double y) { double2 r{x, y}; return r; }; -static inline __attribute__((device)) double3 make_double3(double x, double y, double z) { double3 r{x, y, z}; return r; }; -static inline __attribute__((device)) double4 make_double4(double x, double y, double z, double w) { double4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) ulong1 make_ulong1(unsigned long x) { ulong1 r{x}; return r; }; -static inline __attribute__((device)) ulong2 make_ulong2(unsigned long x, unsigned long y) { ulong2 r{x, y}; return r; }; -static inline __attribute__((device)) ulong3 make_ulong3(unsigned long x, unsigned long y, unsigned long z) { ulong3 r{x, y, z}; return r; }; -static inline __attribute__((device)) ulong4 make_ulong4(unsigned long x, unsigned long y, unsigned long z, unsigned long w) { ulong4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) long1 make_long1(signed long x) { long1 r{x}; return r; }; -static inline __attribute__((device)) long2 make_long2(signed long x, signed long y) { long2 r{x, y}; return r; }; -static inline __attribute__((device)) long3 make_long3(signed long x, signed long y, signed long z) { long3 r{x, y, z}; return r; }; -static inline __attribute__((device)) long4 make_long4(signed long x, signed long y, signed long z, signed long w) { long4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) ulonglong1 make_ulonglong1(unsigned long long x) { ulonglong1 r{x}; return r; }; -static inline __attribute__((device)) ulonglong2 make_ulonglong2(unsigned long long x, unsigned long long y) { ulonglong2 r{x, y}; return r; }; -static inline __attribute__((device)) ulonglong3 make_ulonglong3(unsigned long long x, unsigned long long y, unsigned long long z) { ulonglong3 r{x, y, z}; return r; }; -static inline __attribute__((device)) ulonglong4 make_ulonglong4(unsigned long long x, unsigned long long y, unsigned long long z, unsigned long long w) { ulonglong4 r{x, y, z, w}; return r; }; - -static inline __attribute__((device)) longlong1 make_longlong1(signed long long x) { longlong1 r{x}; return r; }; -static inline __attribute__((device)) longlong2 make_longlong2(signed long long x, signed long long y) { longlong2 r{x, y}; return r; }; -static inline __attribute__((device)) longlong3 make_longlong3(signed long long x, signed long long y, signed long long z) { longlong3 r{x, y, z}; return r; }; -static inline __attribute__((device)) longlong4 make_longlong4(signed long long x, signed long long y, signed long long z, signed long long w) { longlong4 r{x, y, z, w}; return r; }; -# 28 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/hip_ldg.h" 2 3 - - -__attribute__((device)) inline static char __ldg(const char* ptr) { return *ptr; } - -__attribute__((device)) inline static char2 __ldg(const char2* ptr) { return *ptr; } - -__attribute__((device)) inline static char4 __ldg(const char4* ptr) { return *ptr; } - -__attribute__((device)) inline static signed char __ldg(const signed char* ptr) { return ptr[0]; } - -__attribute__((device)) inline static unsigned char __ldg(const unsigned char* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static short __ldg(const short* ptr) { return ptr[0]; } - -__attribute__((device)) inline static short2 __ldg(const short2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static short4 __ldg(const short4* ptr) { return ptr[0]; } - -__attribute__((device)) inline static unsigned short __ldg(const unsigned short* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static int __ldg(const int* ptr) { return ptr[0]; } - -__attribute__((device)) inline static int2 __ldg(const int2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static int4 __ldg(const int4* ptr) { return ptr[0]; } - -__attribute__((device)) inline static unsigned int __ldg(const unsigned int* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static long __ldg(const long* ptr) { return ptr[0]; } - -__attribute__((device)) inline static unsigned long __ldg(const unsigned long* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static long long __ldg(const long long* ptr) { return ptr[0]; } - -__attribute__((device)) inline static longlong2 __ldg(const longlong2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static unsigned long long __ldg(const unsigned long long* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static uchar2 __ldg(const uchar2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static uchar4 __ldg(const uchar4* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static ushort2 __ldg(const ushort2* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static uint2 __ldg(const uint2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static uint4 __ldg(const uint4* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static ulonglong2 __ldg(const ulonglong2* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static float __ldg(const float* ptr) { return ptr[0]; } - -__attribute__((device)) inline static float2 __ldg(const float2* ptr) { return ptr[0]; } - -__attribute__((device)) inline static float4 __ldg(const float4* ptr) { return ptr[0]; } - - -__attribute__((device)) inline static double __ldg(const double* ptr) { return ptr[0]; } - -__attribute__((device)) inline static double2 __ldg(const double2* ptr) { return ptr[0]; } -# 125 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 2 3 -# 250 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_runtime.h" 3 -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_num_groups(unsigned int); -struct __HIP_BlockIdx { - __attribute__((device)) - std::uint32_t operator()(std::uint32_t x) const noexcept { return __ockl_get_group_id(x); } -}; -struct __HIP_BlockDim { - __attribute__((device)) - std::uint32_t operator()(std::uint32_t x) const noexcept { - return __ockl_get_local_size(x); - } -}; -struct __HIP_GridDim { - __attribute__((device)) - std::uint32_t operator()(std::uint32_t x) const noexcept { - return __ockl_get_num_groups(x); - } -}; -struct __HIP_ThreadIdx { - __attribute__((device)) - std::uint32_t operator()(std::uint32_t x) const noexcept { - return __ockl_get_local_id(x); - } -}; - - -typedef struct dim3 { - uint32_t x; - uint32_t y; - uint32_t z; - - constexpr __attribute__((device)) dim3(uint32_t _x = 1, uint32_t _y = 1, uint32_t _z = 1) : x(_x), y(_y), z(_z){}; - -} dim3; - - -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_global_size(unsigned int); - - -template struct __HIP_Coordinates { - using R = decltype(F{}(0)); - - struct __X { - __attribute__((device)) operator R() const noexcept { return F{}(0); } - __attribute__((device)) R operator+=(const R& rhs) { return F{}(0) + rhs; } - }; - struct __Y { - __attribute__((device)) operator R() const noexcept { return F{}(1); } - __attribute__((device)) R operator+=(const R& rhs) { return F{}(1) + rhs; } - }; - struct __Z { - __attribute__((device)) operator R() const noexcept { return F{}(2); } - __attribute__((device)) R operator+=(const R& rhs) { return F{}(2) + rhs; } - }; - - - __attribute__((weak)) - - __attribute__((device)) static constexpr __X x{}; - - __attribute__((weak)) - - __attribute__((device)) static constexpr __Y y{}; - - __attribute__((weak)) - - __attribute__((device)) static constexpr __Z z{}; - - __attribute__((device)) operator dim3() const { return dim3(x, y, z); } -}; - -template -constexpr typename __HIP_Coordinates::__X __HIP_Coordinates::x; -template -constexpr typename __HIP_Coordinates::__Y __HIP_Coordinates::y; -template -constexpr typename __HIP_Coordinates::__Z __HIP_Coordinates::z; - -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_GridDim>::__X, - __HIP_Coordinates<__HIP_BlockDim>::__X) noexcept { - return __ockl_get_global_size(0); -} -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_BlockDim>::__X, - __HIP_Coordinates<__HIP_GridDim>::__X) noexcept { - return __ockl_get_global_size(0); -} -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_GridDim>::__Y, - __HIP_Coordinates<__HIP_BlockDim>::__Y) noexcept { - return __ockl_get_global_size(1); -} -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_BlockDim>::__Y, - __HIP_Coordinates<__HIP_GridDim>::__Y) noexcept { - return __ockl_get_global_size(1); -} -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_GridDim>::__Z, - __HIP_Coordinates<__HIP_BlockDim>::__Z) noexcept { - return __ockl_get_global_size(2); -} -inline -__attribute__((device)) -std::uint32_t operator*(__HIP_Coordinates<__HIP_BlockDim>::__Z, - __HIP_Coordinates<__HIP_GridDim>::__Z) noexcept { - return __ockl_get_global_size(2); -} - -static constexpr __HIP_Coordinates<__HIP_BlockDim> blockDim{}; -static constexpr __HIP_Coordinates<__HIP_BlockIdx> blockIdx{}; -static constexpr __HIP_Coordinates<__HIP_GridDim> gridDim{}; -static constexpr __HIP_Coordinates<__HIP_ThreadIdx> threadIdx{}; - - -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); - - - - -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); - - - - -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); - - - - -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_num_groups(unsigned int); -# 63 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 2 3 -# 73 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_vector_types.h" 1 3 -# 74 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_runtime.h" 2 3 -# 6 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/out/ubuntu-22.04/22.04/build/hip-on-rocclr/hipamd/src/hiprtc/hip_rtc_gen/hipRTC_header.h" 2 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_bfloat16.h" 1 3 -# 37 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_bfloat16.h" 3 -# 1 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_bfloat16.h" 1 3 -# 55 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_bfloat16.h" 3 -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wshadow" -struct hip_bfloat16 -{ - __hip_uint16_t data; - - enum truncate_t - { - truncate - }; - - __attribute__((device)) hip_bfloat16() = default; - - - explicit __attribute__((device)) hip_bfloat16(float f) - : data(float_to_bfloat16(f)) - { - } - - explicit __attribute__((device)) hip_bfloat16(float f, truncate_t) - : data(truncate_float_to_bfloat16(f)) - { - } - - - __attribute__((device)) operator float() const - { - union - { - uint32_t int32; - float fp32; - } u = {uint32_t(data) << 16}; - return u.fp32; - } - - __attribute__((device)) hip_bfloat16 &operator=(const float& f) - { - data = float_to_bfloat16(f); - return *this; - } - - static __attribute__((device)) hip_bfloat16 round_to_bfloat16(float f) - { - hip_bfloat16 output; - output.data = float_to_bfloat16(f); - return output; - } - - static __attribute__((device)) hip_bfloat16 round_to_bfloat16(float f, truncate_t) - { - hip_bfloat16 output; - output.data = truncate_float_to_bfloat16(f); - return output; - } - -private: - static __attribute__((device)) __hip_uint16_t float_to_bfloat16(float f) - { - union - { - float fp32; - uint32_t int32; - } u = {f}; - if(~u.int32 & 0x7f800000) - { -# 136 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_bfloat16.h" 3 - u.int32 += 0x7fff + ((u.int32 >> 16) & 1); - } - else if(u.int32 & 0xffff) - { -# 148 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_bfloat16.h" 3 - u.int32 |= 0x10000; - } - return __hip_uint16_t(u.int32 >> 16); - } - - - static __attribute__((device)) __hip_uint16_t truncate_float_to_bfloat16(float f) - { - union - { - float fp32; - uint32_t int32; - } u = {f}; - return __hip_uint16_t(u.int32 >> 16) | (!(~u.int32 & 0x7f800000) && (u.int32 & 0xffff)); - } -}; -#pragma clang diagnostic pop - -typedef struct -{ - __hip_uint16_t data; -} hip_bfloat16_public; - -static_assert(__hip_internal::is_standard_layout{}, - "hip_bfloat16 is not a standard layout type, and thus is " - "incompatible with C."); - -static_assert(__hip_internal::is_trivial{}, - "hip_bfloat16 is not a trivial type, and thus is " - "incompatible with C."); -# 189 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/clr/hipamd/include/hip/amd_detail/amd_hip_bfloat16.h" 3 -inline __attribute__((device)) hip_bfloat16 operator+(hip_bfloat16 a) -{ - return a; -} -inline __attribute__((device)) hip_bfloat16 operator-(hip_bfloat16 a) -{ - a.data ^= 0x8000; - return a; -} -inline __attribute__((device)) hip_bfloat16 operator+(hip_bfloat16 a, hip_bfloat16 b) -{ - return hip_bfloat16(float(a) + float(b)); -} -inline __attribute__((device)) hip_bfloat16 operator-(hip_bfloat16 a, hip_bfloat16 b) -{ - return hip_bfloat16(float(a) - float(b)); -} -inline __attribute__((device)) hip_bfloat16 operator*(hip_bfloat16 a, hip_bfloat16 b) -{ - return hip_bfloat16(float(a) * float(b)); -} -inline __attribute__((device)) hip_bfloat16 operator/(hip_bfloat16 a, hip_bfloat16 b) -{ - return hip_bfloat16(float(a) / float(b)); -} -inline __attribute__((device)) bool operator<(hip_bfloat16 a, hip_bfloat16 b) -{ - return float(a) < float(b); -} -inline __attribute__((device)) bool operator==(hip_bfloat16 a, hip_bfloat16 b) -{ - return float(a) == float(b); -} -inline __attribute__((device)) bool operator>(hip_bfloat16 a, hip_bfloat16 b) -{ - return b < a; -} -inline __attribute__((device)) bool operator<=(hip_bfloat16 a, hip_bfloat16 b) -{ - return !(a > b); -} -inline __attribute__((device)) bool operator!=(hip_bfloat16 a, hip_bfloat16 b) -{ - return !(a == b); -} -inline __attribute__((device)) bool operator>=(hip_bfloat16 a, hip_bfloat16 b) -{ - return !(a < b); -} -inline __attribute__((device)) hip_bfloat16& operator+=(hip_bfloat16& a, hip_bfloat16 b) -{ - return a = a + b; -} -inline __attribute__((device)) hip_bfloat16& operator-=(hip_bfloat16& a, hip_bfloat16 b) -{ - return a = a - b; -} -inline __attribute__((device)) hip_bfloat16& operator*=(hip_bfloat16& a, hip_bfloat16 b) -{ - return a = a * b; -} -inline __attribute__((device)) hip_bfloat16& operator/=(hip_bfloat16& a, hip_bfloat16 b) -{ - return a = a / b; -} -inline __attribute__((device)) hip_bfloat16& operator++(hip_bfloat16& a) -{ - return a += hip_bfloat16(1.0f); -} -inline __attribute__((device)) hip_bfloat16& operator--(hip_bfloat16& a) -{ - return a -= hip_bfloat16(1.0f); -} -inline __attribute__((device)) hip_bfloat16 operator++(hip_bfloat16& a, int) -{ - hip_bfloat16 orig = a; - ++a; - return orig; -} -inline __attribute__((device)) hip_bfloat16 operator--(hip_bfloat16& a, int) -{ - hip_bfloat16 orig = a; - --a; - return orig; -} - -namespace std -{ - constexpr __attribute__((device)) bool isinf(hip_bfloat16 a) - { - return !(~a.data & 0x7f80) && !(a.data & 0x7f); - } - constexpr __attribute__((device)) bool isnan(hip_bfloat16 a) - { - return !(~a.data & 0x7f80) && +(a.data & 0x7f); - } - constexpr __attribute__((device)) bool iszero(hip_bfloat16 a) - { - return !(a.data & 0x7fff); - } -} -# 38 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/external/hip-on-vdi/include/hip/hip_bfloat16.h" 2 3 -# 7 "/long_pathname_so_that_rpms_can_package_the_debug_info/src/out/ubuntu-22.04/22.04/build/hip-on-rocclr/hipamd/src/hiprtc/hip_rtc_gen/hipRTC_header.h" 2 - -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wreserved-id-macro" -#pragma clang diagnostic ignored "-Wc++98-compat-pedantic" -#pragma clang diagnostic ignored "-Wreserved-macro-identifier" -#pragma clang diagnostic ignored "-Wundef" -#define __device__ __attribute__((device)) -#define __host__ __attribute__((host)) -#define __global__ __attribute__((global)) -#define __constant__ __attribute__((constant)) -#define __shared__ __attribute__((shared)) -#define __align__(x) __attribute__((aligned(x))) -#if !defined(__has_feature) || !__has_feature(cuda_noinline_keyword) -#define __noinline__ __attribute__((noinline)) -#endif -#define __forceinline__ inline __attribute__((always_inline)) -#if __HIP_NO_IMAGE_SUPPORT -#define __hip_img_chk__ __attribute__((unavailable("The image/texture API not supported on the device"))) -#else -#define __hip_img_chk__ -#endif -#define launch_bounds_impl0(requiredMaxThreadsPerBlock) \ - __attribute__((amdgpu_flat_work_group_size(1, requiredMaxThreadsPerBlock))) -#define launch_bounds_impl1(requiredMaxThreadsPerBlock, minBlocksPerMultiprocessor) \ - __attribute__((amdgpu_flat_work_group_size(1, requiredMaxThreadsPerBlock), \ - amdgpu_waves_per_eu(minBlocksPerMultiprocessor))) -#define select_impl_(_1, _2, impl_, ...) impl_ -#define __launch_bounds__(...) \ - select_impl_(__VA_ARGS__, launch_bounds_impl1, launch_bounds_impl0)(__VA_ARGS__) -#define HIP_INCLUDE_HIP_HIP_RUNTIME_H -#define _HIP_BFLOAT16_H_ -#define HIP_INCLUDE_HIP_MATH_FUNCTIONS_H -#define HIP_INCLUDE_HIP_HIP_VECTOR_TYPES_H -#if !__HIP_NO_STD_DEFS__ -#if defined(__HIPRTC_PTRDIFF_T_IS_LONG_LONG__) && __HIPRTC_PTRDIFF_T_IS_LONG_LONG__==1 -typedef long long ptrdiff_t; -#else -typedef __PTRDIFF_TYPE__ ptrdiff_t; -#endif -typedef long clock_t; -namespace std { -using ::ptrdiff_t; -using ::clock_t; -} -#endif // __HIP_NO_STD_DEFS__ -#pragma clang diagnostic pop/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_HIP_COMMON_H -#define HIP_INCLUDE_HIP_HIP_COMMON_H - -#if defined(__clang__) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wreserved-macro-identifier" -#endif -// Common code included at start of every hip file. -// Auto enable __HIP_PLATFORM_AMD__ if compiling on AMD platform -// Other compiler (GCC,ICC,etc) need to set one of these macros explicitly -#if defined(__clang__) && defined(__HIP__) -#ifndef __HIP_PLATFORM_AMD__ -#define __HIP_PLATFORM_AMD__ -#endif -#endif // defined(__clang__) && defined(__HIP__) - -// Auto enable __HIP_PLATFORM_NVIDIA__ if compiling with NVIDIA platform -#if defined(__NVCC__) || (defined(__clang__) && defined(__CUDA__) && !defined(__HIP__)) -#ifndef __HIP_PLATFORM_NVIDIA__ -#define __HIP_PLATFORM_NVIDIA__ -#endif - -#ifdef __CUDACC__ -#define __HIPCC__ -#endif - -#endif //__NVCC__ - -// Auto enable __HIP_DEVICE_COMPILE__ if compiled in HCC or NVCC device path -#if (defined(__HCC_ACCELERATOR__) && __HCC_ACCELERATOR__ != 0) || \ - (defined(__CUDA_ARCH__) && __CUDA_ARCH__ != 0) -#define __HIP_DEVICE_COMPILE__ 1 -#endif - -#ifdef __GNUC__ -#define HIP_PUBLIC_API __attribute__ ((visibility ("default"))) -#define HIP_INTERNAL_EXPORTED_API __attribute__ ((visibility ("default"))) -#else -#define HIP_PUBLIC_API -#define HIP_INTERNAL_EXPORTED_API -#endif - -#if __HIP_DEVICE_COMPILE__ == 0 -// 32-bit Atomics -#define __HIP_ARCH_HAS_GLOBAL_INT32_ATOMICS__ (0) -#define __HIP_ARCH_HAS_GLOBAL_FLOAT_ATOMIC_EXCH__ (0) -#define __HIP_ARCH_HAS_SHARED_INT32_ATOMICS__ (0) -#define __HIP_ARCH_HAS_SHARED_FLOAT_ATOMIC_EXCH__ (0) -#define __HIP_ARCH_HAS_FLOAT_ATOMIC_ADD__ (0) - -// 64-bit Atomics -#define __HIP_ARCH_HAS_GLOBAL_INT64_ATOMICS__ (0) -#define __HIP_ARCH_HAS_SHARED_INT64_ATOMICS__ (0) - -// Doubles -#define __HIP_ARCH_HAS_DOUBLES__ (0) - -// Warp cross-lane operations -#define __HIP_ARCH_HAS_WARP_VOTE__ (0) -#define __HIP_ARCH_HAS_WARP_BALLOT__ (0) -#define __HIP_ARCH_HAS_WARP_SHUFFLE__ (0) -#define __HIP_ARCH_HAS_WARP_FUNNEL_SHIFT__ (0) - -// Sync -#define __HIP_ARCH_HAS_THREAD_FENCE_SYSTEM__ (0) -#define __HIP_ARCH_HAS_SYNC_THREAD_EXT__ (0) - -// Misc -#define __HIP_ARCH_HAS_SURFACE_FUNCS__ (0) -#define __HIP_ARCH_HAS_3DGRID__ (0) -#define __HIP_ARCH_HAS_DYNAMIC_PARALLEL__ (0) -#endif - -#if defined(__clang__) -#pragma clang diagnostic pop -#endif - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_LIBRARY_TYPES_H -#define HIP_INCLUDE_HIP_LIBRARY_TYPES_H - -#if !defined(__HIPCC_RTC__) -#include -#endif - -#if defined(__HIP_PLATFORM_AMD__) && !defined(__HIP_PLATFORM_NVIDIA__) - -typedef enum hipDataType { - HIP_R_32F = 0, - HIP_R_64F = 1, - HIP_R_16F = 2, - HIP_R_8I = 3, - HIP_C_32F = 4, - HIP_C_64F = 5, - HIP_C_16F = 6, - HIP_C_8I = 7, - HIP_R_8U = 8, - HIP_C_8U = 9, - HIP_R_32I = 10, - HIP_C_32I = 11, - HIP_R_32U = 12, - HIP_C_32U = 13, - HIP_R_16BF = 14, - HIP_C_16BF = 15, - HIP_R_4I = 16, - HIP_C_4I = 17, - HIP_R_4U = 18, - HIP_C_4U = 19, - HIP_R_16I = 20, - HIP_C_16I = 21, - HIP_R_16U = 22, - HIP_C_16U = 23, - HIP_R_64I = 24, - HIP_C_64I = 25, - HIP_R_64U = 26, - HIP_C_64U = 27, - // HIP specific Data Types - HIP_R_8F_E4M3_FNUZ = 1000, - HIP_R_8F_E5M2_FNUZ = 1001 -} hipDataType; - -typedef enum hipLibraryPropertyType { - HIP_LIBRARY_MAJOR_VERSION, - HIP_LIBRARY_MINOR_VERSION, - HIP_LIBRARY_PATCH_LEVEL -} hipLibraryPropertyType; - -#elif !defined(__HIP_PLATFORM_AMD__) && defined(__HIP_PLATFORM_NVIDIA__) -#include "library_types.h" -#else -#error("Must define exactly one of __HIP_PLATFORM_AMD__ or __HIP_PLATFORM_NVIDIA__"); -#endif - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_DRIVER_TYPES_H -#define HIP_INCLUDE_HIP_DRIVER_TYPES_H - -#if !defined(__HIPCC_RTC__) -#include -#endif - -#if !defined(__HIP_PLATFORM_AMD__) && defined(__HIP_PLATFORM_NVIDIA__) -#include "driver_types.h" -#elif defined(__HIP_PLATFORM_AMD__) && !defined(__HIP_PLATFORM_NVIDIA__) - -#if !defined(__HIPCC_RTC__) -#ifndef __cplusplus -#include -#endif -#endif // !defined(__HIPCC_RTC__) -typedef void* hipDeviceptr_t; -typedef enum hipChannelFormatKind { - hipChannelFormatKindSigned = 0, - hipChannelFormatKindUnsigned = 1, - hipChannelFormatKindFloat = 2, - hipChannelFormatKindNone = 3 -}hipChannelFormatKind; -typedef struct hipChannelFormatDesc { - int x; - int y; - int z; - int w; - enum hipChannelFormatKind f; -}hipChannelFormatDesc; -#define HIP_TRSA_OVERRIDE_FORMAT 0x01 -#define HIP_TRSF_READ_AS_INTEGER 0x01 -#define HIP_TRSF_NORMALIZED_COORDINATES 0x02 -#define HIP_TRSF_SRGB 0x10 - -typedef struct hipArray* hipArray_t; -typedef const struct hipArray* hipArray_const_t; -typedef enum hipArray_Format { - HIP_AD_FORMAT_UNSIGNED_INT8 = 0x01, - HIP_AD_FORMAT_UNSIGNED_INT16 = 0x02, - HIP_AD_FORMAT_UNSIGNED_INT32 = 0x03, - HIP_AD_FORMAT_SIGNED_INT8 = 0x08, - HIP_AD_FORMAT_SIGNED_INT16 = 0x09, - HIP_AD_FORMAT_SIGNED_INT32 = 0x0a, - HIP_AD_FORMAT_HALF = 0x10, - HIP_AD_FORMAT_FLOAT = 0x20 -}hipArray_Format; -typedef struct HIP_ARRAY_DESCRIPTOR { - size_t Width; - size_t Height; - enum hipArray_Format Format; - unsigned int NumChannels; -}HIP_ARRAY_DESCRIPTOR; -typedef struct HIP_ARRAY3D_DESCRIPTOR { - size_t Width; - size_t Height; - size_t Depth; - enum hipArray_Format Format; - unsigned int NumChannels; - unsigned int Flags; -}HIP_ARRAY3D_DESCRIPTOR; -#if !defined(__HIPCC_RTC__) -typedef struct hip_Memcpy2D { - size_t srcXInBytes; - size_t srcY; - hipMemoryType srcMemoryType; - const void* srcHost; - hipDeviceptr_t srcDevice; - hipArray_t srcArray; - size_t srcPitch; - size_t dstXInBytes; - size_t dstY; - hipMemoryType dstMemoryType; - void* dstHost; - hipDeviceptr_t dstDevice; - hipArray_t dstArray; - size_t dstPitch; - size_t WidthInBytes; - size_t Height; -} hip_Memcpy2D; -#endif // !defined(__HIPCC_RTC__) -typedef struct hipMipmappedArray { - void* data; - struct hipChannelFormatDesc desc; - unsigned int type; - unsigned int width; - unsigned int height; - unsigned int depth; - unsigned int min_mipmap_level; - unsigned int max_mipmap_level; - unsigned int flags; - enum hipArray_Format format; - unsigned int num_channels; -} hipMipmappedArray; -typedef struct hipMipmappedArray* hipMipmappedArray_t; -typedef hipMipmappedArray_t hipmipmappedArray; -typedef const struct hipMipmappedArray* hipMipmappedArray_const_t; -/** - * hip resource types - */ -typedef enum hipResourceType { - hipResourceTypeArray = 0x00, - hipResourceTypeMipmappedArray = 0x01, - hipResourceTypeLinear = 0x02, - hipResourceTypePitch2D = 0x03 -}hipResourceType; -typedef enum HIPresourcetype_enum { - HIP_RESOURCE_TYPE_ARRAY = 0x00, /**< Array resoure */ - HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY = 0x01, /**< Mipmapped array resource */ - HIP_RESOURCE_TYPE_LINEAR = 0x02, /**< Linear resource */ - HIP_RESOURCE_TYPE_PITCH2D = 0x03 /**< Pitch 2D resource */ -} HIPresourcetype, hipResourcetype; -/** - * hip address modes - */ -typedef enum HIPaddress_mode_enum { - HIP_TR_ADDRESS_MODE_WRAP = 0, - HIP_TR_ADDRESS_MODE_CLAMP = 1, - HIP_TR_ADDRESS_MODE_MIRROR = 2, - HIP_TR_ADDRESS_MODE_BORDER = 3 -} HIPaddress_mode; -/** - * hip filter modes - */ -typedef enum HIPfilter_mode_enum { - HIP_TR_FILTER_MODE_POINT = 0, - HIP_TR_FILTER_MODE_LINEAR = 1 -} HIPfilter_mode; -/** - * Texture descriptor - */ -typedef struct HIP_TEXTURE_DESC_st { - HIPaddress_mode addressMode[3]; /**< Address modes */ - HIPfilter_mode filterMode; /**< Filter mode */ - unsigned int flags; /**< Flags */ - unsigned int maxAnisotropy; /**< Maximum anisotropy ratio */ - HIPfilter_mode mipmapFilterMode; /**< Mipmap filter mode */ - float mipmapLevelBias; /**< Mipmap level bias */ - float minMipmapLevelClamp; /**< Mipmap minimum level clamp */ - float maxMipmapLevelClamp; /**< Mipmap maximum level clamp */ - float borderColor[4]; /**< Border Color */ - int reserved[12]; -} HIP_TEXTURE_DESC; -/** - * hip texture resource view formats - */ -typedef enum hipResourceViewFormat { - hipResViewFormatNone = 0x00, - hipResViewFormatUnsignedChar1 = 0x01, - hipResViewFormatUnsignedChar2 = 0x02, - hipResViewFormatUnsignedChar4 = 0x03, - hipResViewFormatSignedChar1 = 0x04, - hipResViewFormatSignedChar2 = 0x05, - hipResViewFormatSignedChar4 = 0x06, - hipResViewFormatUnsignedShort1 = 0x07, - hipResViewFormatUnsignedShort2 = 0x08, - hipResViewFormatUnsignedShort4 = 0x09, - hipResViewFormatSignedShort1 = 0x0a, - hipResViewFormatSignedShort2 = 0x0b, - hipResViewFormatSignedShort4 = 0x0c, - hipResViewFormatUnsignedInt1 = 0x0d, - hipResViewFormatUnsignedInt2 = 0x0e, - hipResViewFormatUnsignedInt4 = 0x0f, - hipResViewFormatSignedInt1 = 0x10, - hipResViewFormatSignedInt2 = 0x11, - hipResViewFormatSignedInt4 = 0x12, - hipResViewFormatHalf1 = 0x13, - hipResViewFormatHalf2 = 0x14, - hipResViewFormatHalf4 = 0x15, - hipResViewFormatFloat1 = 0x16, - hipResViewFormatFloat2 = 0x17, - hipResViewFormatFloat4 = 0x18, - hipResViewFormatUnsignedBlockCompressed1 = 0x19, - hipResViewFormatUnsignedBlockCompressed2 = 0x1a, - hipResViewFormatUnsignedBlockCompressed3 = 0x1b, - hipResViewFormatUnsignedBlockCompressed4 = 0x1c, - hipResViewFormatSignedBlockCompressed4 = 0x1d, - hipResViewFormatUnsignedBlockCompressed5 = 0x1e, - hipResViewFormatSignedBlockCompressed5 = 0x1f, - hipResViewFormatUnsignedBlockCompressed6H = 0x20, - hipResViewFormatSignedBlockCompressed6H = 0x21, - hipResViewFormatUnsignedBlockCompressed7 = 0x22 -}hipResourceViewFormat; -typedef enum HIPresourceViewFormat_enum -{ - HIP_RES_VIEW_FORMAT_NONE = 0x00, /**< No resource view format (use underlying resource format) */ - HIP_RES_VIEW_FORMAT_UINT_1X8 = 0x01, /**< 1 channel unsigned 8-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_2X8 = 0x02, /**< 2 channel unsigned 8-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_4X8 = 0x03, /**< 4 channel unsigned 8-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_1X8 = 0x04, /**< 1 channel signed 8-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_2X8 = 0x05, /**< 2 channel signed 8-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_4X8 = 0x06, /**< 4 channel signed 8-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_1X16 = 0x07, /**< 1 channel unsigned 16-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_2X16 = 0x08, /**< 2 channel unsigned 16-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_4X16 = 0x09, /**< 4 channel unsigned 16-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_1X16 = 0x0a, /**< 1 channel signed 16-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_2X16 = 0x0b, /**< 2 channel signed 16-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_4X16 = 0x0c, /**< 4 channel signed 16-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_1X32 = 0x0d, /**< 1 channel unsigned 32-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_2X32 = 0x0e, /**< 2 channel unsigned 32-bit integers */ - HIP_RES_VIEW_FORMAT_UINT_4X32 = 0x0f, /**< 4 channel unsigned 32-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_1X32 = 0x10, /**< 1 channel signed 32-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_2X32 = 0x11, /**< 2 channel signed 32-bit integers */ - HIP_RES_VIEW_FORMAT_SINT_4X32 = 0x12, /**< 4 channel signed 32-bit integers */ - HIP_RES_VIEW_FORMAT_FLOAT_1X16 = 0x13, /**< 1 channel 16-bit floating point */ - HIP_RES_VIEW_FORMAT_FLOAT_2X16 = 0x14, /**< 2 channel 16-bit floating point */ - HIP_RES_VIEW_FORMAT_FLOAT_4X16 = 0x15, /**< 4 channel 16-bit floating point */ - HIP_RES_VIEW_FORMAT_FLOAT_1X32 = 0x16, /**< 1 channel 32-bit floating point */ - HIP_RES_VIEW_FORMAT_FLOAT_2X32 = 0x17, /**< 2 channel 32-bit floating point */ - HIP_RES_VIEW_FORMAT_FLOAT_4X32 = 0x18, /**< 4 channel 32-bit floating point */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC1 = 0x19, /**< Block compressed 1 */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC2 = 0x1a, /**< Block compressed 2 */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC3 = 0x1b, /**< Block compressed 3 */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC4 = 0x1c, /**< Block compressed 4 unsigned */ - HIP_RES_VIEW_FORMAT_SIGNED_BC4 = 0x1d, /**< Block compressed 4 signed */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC5 = 0x1e, /**< Block compressed 5 unsigned */ - HIP_RES_VIEW_FORMAT_SIGNED_BC5 = 0x1f, /**< Block compressed 5 signed */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H = 0x20, /**< Block compressed 6 unsigned half-float */ - HIP_RES_VIEW_FORMAT_SIGNED_BC6H = 0x21, /**< Block compressed 6 signed half-float */ - HIP_RES_VIEW_FORMAT_UNSIGNED_BC7 = 0x22 /**< Block compressed 7 */ -} HIPresourceViewFormat; -/** - * HIP resource descriptor - */ -typedef struct hipResourceDesc { - enum hipResourceType resType; - union { - struct { - hipArray_t array; - } array; - struct { - hipMipmappedArray_t mipmap; - } mipmap; - struct { - void* devPtr; - struct hipChannelFormatDesc desc; - size_t sizeInBytes; - } linear; - struct { - void* devPtr; - struct hipChannelFormatDesc desc; - size_t width; - size_t height; - size_t pitchInBytes; - } pitch2D; - } res; -}hipResourceDesc; -typedef struct HIP_RESOURCE_DESC_st -{ - HIPresourcetype resType; /**< Resource type */ - union { - struct { - hipArray_t hArray; /**< HIP array */ - } array; - struct { - hipMipmappedArray_t hMipmappedArray; /**< HIP mipmapped array */ - } mipmap; - struct { - hipDeviceptr_t devPtr; /**< Device pointer */ - hipArray_Format format; /**< Array format */ - unsigned int numChannels; /**< Channels per array element */ - size_t sizeInBytes; /**< Size in bytes */ - } linear; - struct { - hipDeviceptr_t devPtr; /**< Device pointer */ - hipArray_Format format; /**< Array format */ - unsigned int numChannels; /**< Channels per array element */ - size_t width; /**< Width of the array in elements */ - size_t height; /**< Height of the array in elements */ - size_t pitchInBytes; /**< Pitch between two rows in bytes */ - } pitch2D; - struct { - int reserved[32]; - } reserved; - } res; - unsigned int flags; /**< Flags (must be zero) */ -} HIP_RESOURCE_DESC; -/** - * hip resource view descriptor - */ -struct hipResourceViewDesc { - enum hipResourceViewFormat format; - size_t width; - size_t height; - size_t depth; - unsigned int firstMipmapLevel; - unsigned int lastMipmapLevel; - unsigned int firstLayer; - unsigned int lastLayer; -}; -/** - * Resource view descriptor - */ -typedef struct HIP_RESOURCE_VIEW_DESC_st -{ - HIPresourceViewFormat format; /**< Resource view format */ - size_t width; /**< Width of the resource view */ - size_t height; /**< Height of the resource view */ - size_t depth; /**< Depth of the resource view */ - unsigned int firstMipmapLevel; /**< First defined mipmap level */ - unsigned int lastMipmapLevel; /**< Last defined mipmap level */ - unsigned int firstLayer; /**< First layer index */ - unsigned int lastLayer; /**< Last layer index */ - unsigned int reserved[16]; -} HIP_RESOURCE_VIEW_DESC; -/** - * Memory copy types - * - */ -#if !defined(__HIPCC_RTC__) -typedef enum hipMemcpyKind { - hipMemcpyHostToHost = 0, ///< Host-to-Host Copy - hipMemcpyHostToDevice = 1, ///< Host-to-Device Copy - hipMemcpyDeviceToHost = 2, ///< Device-to-Host Copy - hipMemcpyDeviceToDevice = 3, ///< Device-to-Device Copy - hipMemcpyDefault = - 4 ///< Runtime will automatically determine copy-kind based on virtual addresses. -} hipMemcpyKind; -typedef struct hipPitchedPtr { - void* ptr; - size_t pitch; - size_t xsize; - size_t ysize; -}hipPitchedPtr; -typedef struct hipExtent { - size_t width; // Width in elements when referring to array memory, in bytes when referring to - // linear memory - size_t height; - size_t depth; -}hipExtent; -typedef struct hipPos { - size_t x; - size_t y; - size_t z; -}hipPos; -typedef struct hipMemcpy3DParms { - hipArray_t srcArray; - struct hipPos srcPos; - struct hipPitchedPtr srcPtr; - hipArray_t dstArray; - struct hipPos dstPos; - struct hipPitchedPtr dstPtr; - struct hipExtent extent; - enum hipMemcpyKind kind; -} hipMemcpy3DParms; -typedef struct HIP_MEMCPY3D { - size_t srcXInBytes; - size_t srcY; - size_t srcZ; - size_t srcLOD; - hipMemoryType srcMemoryType; - const void* srcHost; - hipDeviceptr_t srcDevice; - hipArray_t srcArray; - size_t srcPitch; - size_t srcHeight; - size_t dstXInBytes; - size_t dstY; - size_t dstZ; - size_t dstLOD; - hipMemoryType dstMemoryType; - void* dstHost; - hipDeviceptr_t dstDevice; - hipArray_t dstArray; - size_t dstPitch; - size_t dstHeight; - size_t WidthInBytes; - size_t Height; - size_t Depth; -} HIP_MEMCPY3D; -static inline struct hipPitchedPtr make_hipPitchedPtr(void* d, size_t p, size_t xsz, - size_t ysz) { - struct hipPitchedPtr s; - s.ptr = d; - s.pitch = p; - s.xsize = xsz; - s.ysize = ysz; - return s; -} -static inline struct hipPos make_hipPos(size_t x, size_t y, size_t z) { - struct hipPos p; - p.x = x; - p.y = y; - p.z = z; - return p; -} -static inline struct hipExtent make_hipExtent(size_t w, size_t h, size_t d) { - struct hipExtent e; - e.width = w; - e.height = h; - e.depth = d; - return e; -} -typedef enum hipFunction_attribute { - HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK, - HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES, - HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES, - HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES, - HIP_FUNC_ATTRIBUTE_NUM_REGS, - HIP_FUNC_ATTRIBUTE_PTX_VERSION, - HIP_FUNC_ATTRIBUTE_BINARY_VERSION, - HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA, - HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES, - HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT, - HIP_FUNC_ATTRIBUTE_MAX -} hipFunction_attribute; - -typedef enum hipPointer_attribute { - HIP_POINTER_ATTRIBUTE_CONTEXT = 1, ///< The context on which a pointer was allocated - ///< @warning - not supported in HIP - HIP_POINTER_ATTRIBUTE_MEMORY_TYPE, ///< memory type describing location of a pointer - HIP_POINTER_ATTRIBUTE_DEVICE_POINTER,///< address at which the pointer is allocated on device - HIP_POINTER_ATTRIBUTE_HOST_POINTER, ///< address at which the pointer is allocated on host - HIP_POINTER_ATTRIBUTE_P2P_TOKENS, ///< A pair of tokens for use with linux kernel interface - ///< @warning - not supported in HIP - HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS, ///< Synchronize every synchronous memory operation - ///< initiated on this region - HIP_POINTER_ATTRIBUTE_BUFFER_ID, ///< Unique ID for an allocated memory region - HIP_POINTER_ATTRIBUTE_IS_MANAGED, ///< Indicates if the pointer points to managed memory - HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL,///< device ordinal of a device on which a pointer - ///< was allocated or registered - HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE, ///< if this pointer maps to an allocation - ///< that is suitable for hipIpcGetMemHandle - ///< @warning - not supported in HIP - HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR,///< Starting address for this requested pointer - HIP_POINTER_ATTRIBUTE_RANGE_SIZE, ///< Size of the address range for this requested pointer - HIP_POINTER_ATTRIBUTE_MAPPED, ///< tells if this pointer is in a valid address range - ///< that is mapped to a backing allocation - HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES,///< Bitmask of allowed hipmemAllocationHandleType - ///< for this allocation @warning - not supported in HIP - HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE, ///< returns if the memory referenced by - ///< this pointer can be used with the GPUDirect RDMA API - ///< @warning - not supported in HIP - HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS, ///< Returns the access flags the device associated with - ///< for the corresponding memory referenced by the ptr - HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE ///< Returns the mempool handle for the allocation if - ///< it was allocated from a mempool - ///< @warning - not supported in HIP -} hipPointer_attribute; - -#endif // !defined(__HIPCC_RTC__) -#else -#error("Must define exactly one of __HIP_PLATFORM_AMD__ or __HIP_PLATFORM_NVIDIA__"); -#endif -#endif -/* -Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -/** - * @file surface_types.h - * @brief Defines surface types for HIP runtime. - */ - -#ifndef HIP_INCLUDE_HIP_SURFACE_TYPES_H -#define HIP_INCLUDE_HIP_SURFACE_TYPES_H - -#if defined(__clang__) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wreserved-identifier" -#endif - -#if !defined(__HIPCC_RTC__) -#include -#endif - -/** - * An opaque value that represents a hip surface object - */ -struct __hip_surface; -typedef struct __hip_surface* hipSurfaceObject_t; - -/** - * hip surface reference - */ -struct surfaceReference { - hipSurfaceObject_t surfaceObject; -}; - -/** - * hip surface boundary modes - */ -enum hipSurfaceBoundaryMode { - hipBoundaryModeZero = 0, - hipBoundaryModeTrap = 1, - hipBoundaryModeClamp = 2 -}; - -#if defined(__clang__) -#pragma clang diagnostic pop -#endif - -#endif /* !HIP_INCLUDE_HIP_SURFACE_TYPES_H */ -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_CHANNEL_DESCRIPTOR_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_CHANNEL_DESCRIPTOR_H - -#if !defined(__HIPCC_RTC__) -#include -#include -#include -#endif - -#ifdef __cplusplus - -extern "C" HIP_PUBLIC_API -hipChannelFormatDesc hipCreateChannelDesc(int x, int y, int z, int w, hipChannelFormatKind f); - -static inline hipChannelFormatDesc hipCreateChannelDescHalf() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindFloat); -} - -static inline hipChannelFormatDesc hipCreateChannelDescHalf1() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindFloat); -} - -static inline hipChannelFormatDesc hipCreateChannelDescHalf2() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindFloat); -} - -static inline hipChannelFormatDesc hipCreateChannelDescHalf4() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindFloat); -} - -template -static inline hipChannelFormatDesc hipCreateChannelDesc() { - return hipCreateChannelDesc(0, 0, 0, 0, hipChannelFormatKindNone); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(char) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed char) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned char) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned char) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed char) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned char) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed char) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindSigned); -} - -#ifndef __GNUC__ // vector3 is the same as vector4 -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned char) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed char) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindSigned); -} -#endif - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned char) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed char) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed short) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed short) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindSigned); -} - -#ifndef __GNUC__ -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed short) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindSigned); -} -#endif - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned short) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed short) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned int) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed int) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned int) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed int) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned int) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed int) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindSigned); -} - -#ifndef __GNUC__ -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned int) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed int) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindSigned); -} -#endif - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned int) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed int) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(float) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindFloat); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(float) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindFloat); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(float) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindFloat); -} - -#ifndef __GNUC__ -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(float) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindFloat); -} -#endif - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(float) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindFloat); -} - -#if !defined(__LP64__) - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned long) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed long) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned long) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed long) * 8; - return hipCreateChannelDesc(e, 0, 0, 0, hipChannelFormatKindSigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned long) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed long) * 8; - return hipCreateChannelDesc(e, e, 0, 0, hipChannelFormatKindSigned); -} - -#ifndef __GNUC__ -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned long) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed long) * 8; - return hipCreateChannelDesc(e, e, e, 0, hipChannelFormatKindSigned); -} -#endif - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(unsigned long) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindUnsigned); -} - -template <> -inline hipChannelFormatDesc hipCreateChannelDesc() { - int e = (int)sizeof(signed long) * 8; - return hipCreateChannelDesc(e, e, e, e, hipChannelFormatKindSigned); -} -#endif /* !__LP64__ */ - -#else - -struct hipChannelFormatDesc hipCreateChannelDesc(int x, int y, int z, int w, - enum hipChannelFormatKind f); - -#endif /* __cplusplus */ - -#endif /* !HIP_INCLUDE_HIP_AMD_DETAIL_CHANNEL_DESCRIPTOR_H */ -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_TEXTURE_TYPES_H -#define HIP_INCLUDE_HIP_TEXTURE_TYPES_H - -#if defined(__clang__) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wreserved-identifier" -#pragma clang diagnostic ignored "-Wreserved-macro-identifier" -#pragma clang diagnostic ignored "-Wc++98-compat" -#endif - -#if !defined(__HIPCC_RTC__) -#include -#endif - -#if !defined(__HIP_PLATFORM_AMD__) && defined(__HIP_PLATFORM_NVIDIA__) -#include "texture_types.h" -#elif defined(__HIP_PLATFORM_AMD__) && !defined(__HIP_PLATFORM_NVIDIA__) -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -#if !defined(__HIPCC_RTC__) -#include -#include -#include -#endif // !defined(__HIPCC_RTC__) - -#define hipTextureType1D 0x01 -#define hipTextureType2D 0x02 -#define hipTextureType3D 0x03 -#define hipTextureTypeCubemap 0x0C -#define hipTextureType1DLayered 0xF1 -#define hipTextureType2DLayered 0xF2 -#define hipTextureTypeCubemapLayered 0xFC - -/** - * Should be same as HSA_IMAGE_OBJECT_SIZE_DWORD/HSA_SAMPLER_OBJECT_SIZE_DWORD - */ -#define HIP_IMAGE_OBJECT_SIZE_DWORD 12 -#define HIP_SAMPLER_OBJECT_SIZE_DWORD 8 -#define HIP_SAMPLER_OBJECT_OFFSET_DWORD HIP_IMAGE_OBJECT_SIZE_DWORD -#define HIP_TEXTURE_OBJECT_SIZE_DWORD (HIP_IMAGE_OBJECT_SIZE_DWORD + HIP_SAMPLER_OBJECT_SIZE_DWORD) - -/** - * An opaque value that represents a hip texture object - */ -struct __hip_texture; -typedef struct __hip_texture* hipTextureObject_t; - -/** - * hip texture address modes - */ -enum hipTextureAddressMode { - hipAddressModeWrap = 0, - hipAddressModeClamp = 1, - hipAddressModeMirror = 2, - hipAddressModeBorder = 3 -}; - -/** - * hip texture filter modes - */ -enum hipTextureFilterMode { hipFilterModePoint = 0, hipFilterModeLinear = 1 }; - -/** - * hip texture read modes - */ -enum hipTextureReadMode { hipReadModeElementType = 0, hipReadModeNormalizedFloat = 1 }; - -/** - * hip texture reference - */ -typedef struct textureReference { - int normalized; - enum hipTextureReadMode readMode;// used only for driver API's - enum hipTextureFilterMode filterMode; - enum hipTextureAddressMode addressMode[3]; // Texture address mode for up to 3 dimensions - struct hipChannelFormatDesc channelDesc; - int sRGB; // Perform sRGB->linear conversion during texture read - unsigned int maxAnisotropy; // Limit to the anisotropy ratio - enum hipTextureFilterMode mipmapFilterMode; - float mipmapLevelBias; - float minMipmapLevelClamp; - float maxMipmapLevelClamp; - - hipTextureObject_t textureObject; - int numChannels; - enum hipArray_Format format; -}textureReference; - -/** - * hip texture descriptor - */ -typedef struct hipTextureDesc { - enum hipTextureAddressMode addressMode[3]; // Texture address mode for up to 3 dimensions - enum hipTextureFilterMode filterMode; - enum hipTextureReadMode readMode; - int sRGB; // Perform sRGB->linear conversion during texture read - float borderColor[4]; - int normalizedCoords; - unsigned int maxAnisotropy; - enum hipTextureFilterMode mipmapFilterMode; - float mipmapLevelBias; - float minMipmapLevelClamp; - float maxMipmapLevelClamp; -}hipTextureDesc; - -#if __cplusplus - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -#if __HIP__ -#define __HIP_TEXTURE_ATTRIB __attribute__((device_builtin_texture_type)) -#else -#define __HIP_TEXTURE_ATTRIB -#endif - -typedef textureReference* hipTexRef; - -template -struct __HIP_TEXTURE_ATTRIB texture : public textureReference { - texture(int norm = 0, enum hipTextureFilterMode fMode = hipFilterModePoint, - enum hipTextureAddressMode aMode = hipAddressModeClamp) { - normalized = norm; - readMode = mode; - filterMode = fMode; - addressMode[0] = aMode; - addressMode[1] = aMode; - addressMode[2] = aMode; - channelDesc = hipCreateChannelDesc(); - sRGB = 0; - textureObject = nullptr; - maxAnisotropy = 0; - mipmapLevelBias = 0; - minMipmapLevelClamp = 0; - maxMipmapLevelClamp = 0; - } - - texture(int norm, enum hipTextureFilterMode fMode, enum hipTextureAddressMode aMode, - struct hipChannelFormatDesc desc) { - normalized = norm; - readMode = mode; - filterMode = fMode; - addressMode[0] = aMode; - addressMode[1] = aMode; - addressMode[2] = aMode; - channelDesc = desc; - sRGB = 0; - textureObject = nullptr; - maxAnisotropy = 0; - mipmapLevelBias = 0; - minMipmapLevelClamp = 0; - maxMipmapLevelClamp = 0; - } -}; - -#endif /* __cplusplus */ - -#else -#error("Must define exactly one of __HIP_PLATFORM_AMD__ or __HIP_PLATFORM_NVIDIA__"); -#endif - -#if defined(__clang__) -#pragma clang diagnostic pop -#endif - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if !defined(__HIPCC_RTC__) -#include -#endif - -extern "C" { - -#define ADDRESS_SPACE_CONSTANT __attribute__((address_space(4))) - -__device__ float4::Native_vec_ __ockl_image_load_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, int c); - -__device__ float4::Native_vec_ __ockl_image_load_1Db(unsigned int ADDRESS_SPACE_CONSTANT*i, int c); - -__device__ float4::Native_vec_ __ockl_image_load_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_load_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_load_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_load_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_load_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int f); - -__device__ float4::Native_vec_ __ockl_image_load_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int f); - -__device__ float4::Native_vec_ __ockl_image_load_lod_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, int c, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int f, int l); - -__device__ float4::Native_vec_ __ockl_image_load_lod_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int f, int l); - -__device__ void __ockl_image_store_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, int c, float4::Native_vec_ p); - -__device__ void __ockl_image_store_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, float4::Native_vec_ p); - -__device__ void __ockl_image_store_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, float4::Native_vec_ p); - -__device__ void __ockl_image_store_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, float4::Native_vec_ p); - -__device__ void __ockl_image_store_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, float4::Native_vec_ p); - -__device__ void __ockl_image_store_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int f, float4::Native_vec_ p); - -__device__ void __ockl_image_store_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int f, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, int c, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, int2::Native_vec_ c, int f, int l, float4::Native_vec_ p); - -__device__ void __ockl_image_store_lod_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, int4::Native_vec_ c, int f, int l, float4::Native_vec_ p); - -__device__ float4::Native_vec_ __ockl_image_sample_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float c); - -__device__ float4::Native_vec_ __ockl_image_sample_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_sample_grad_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float c, float dx, float dy); - -__device__ float4::Native_vec_ __ockl_image_sample_grad_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c, float dx, float dy); - -__device__ float4::Native_vec_ __ockl_image_sample_grad_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c, float2::Native_vec_ dx, float2::Native_vec_ dy); - -__device__ float4::Native_vec_ __ockl_image_sample_grad_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float2::Native_vec_ dx, float2::Native_vec_ dy); - -__device__ float4::Native_vec_ __ockl_image_sample_grad_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float4::Native_vec_ dx, float4::Native_vec_ dy); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_1D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_1Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_2Da(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_3D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_CM(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_sample_lod_CMa(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float4::Native_vec_ c, float l); - -__device__ float4::Native_vec_ __ockl_image_gather4r_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_gather4g_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_gather4b_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ float4::Native_vec_ __ockl_image_gather4a_2D(unsigned int ADDRESS_SPACE_CONSTANT*i, unsigned int ADDRESS_SPACE_CONSTANT*s, float2::Native_vec_ c); - -__device__ int __ockl_image_channel_data_type_1D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_1Da(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_1Db(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_2D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_2Da(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_2Dad(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_2Dd(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_3D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_CM(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_data_type_CMa(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_1D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_1Da(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_1Db(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_2D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_2Da(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_2Dad(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_2Dd(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_3D(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_CM(unsigned int ADDRESS_SPACE_CONSTANT* i); - -__device__ int __ockl_image_channel_order_CMa(unsigned int ADDRESS_SPACE_CONSTANT* i); - -} -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if defined(__cplusplus) - -#if !defined(__HIPCC_RTC__) -#include -#include -#include -#include -#endif // !defined(__HIPCC_RTC__) - -#define TEXTURE_PARAMETERS_INIT \ - unsigned int ADDRESS_SPACE_CONSTANT* i = (unsigned int ADDRESS_SPACE_CONSTANT*)t.textureObject; \ - unsigned int ADDRESS_SPACE_CONSTANT* s = i + HIP_SAMPLER_OBJECT_OFFSET_DWORD; - -template -struct __hip_is_tex_surf_scalar_channel_type -{ - static constexpr bool value = - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value; -}; - -template -struct __hip_is_tex_surf_channel_type -{ - static constexpr bool value = - __hip_is_tex_surf_scalar_channel_type::value; -}; - -template< - typename T, - unsigned int rank> -struct __hip_is_tex_surf_channel_type> -{ - static constexpr bool value = - __hip_is_tex_surf_scalar_channel_type::value && - ((rank == 1) || - (rank == 2) || - (rank == 4)); -}; - -template -struct __hip_is_tex_normalized_channel_type -{ - static constexpr bool value = - std::is_same::value || - std::is_same::value || - std::is_same::value || - std::is_same::value; -}; - -template< - typename T, - unsigned int rank> -struct __hip_is_tex_normalized_channel_type> -{ - static constexpr bool value = - __hip_is_tex_normalized_channel_type::value && - ((rank == 1) || - (rank == 2) || - (rank == 4)); -}; - -template < - typename T, - hipTextureReadMode readMode, - typename Enable = void> -struct __hip_tex_ret -{ - static_assert(std::is_same::value, "Invalid channel type!"); -}; - -/* - * Map from device function return U to scalar texture type T - */ -template -__forceinline__ __device__ -typename std::enable_if< - __hip_is_tex_surf_scalar_channel_type::value, const T>::type -__hipMapFrom(const U &u) { - if constexpr (sizeof(T) < sizeof(float)) { - union { - U u; - int i; - } d = { u }; - return static_cast(d.i); - } else { // sizeof(T) == sizeof(float) - union { - U u; - T t; - } d = { u }; - return d.t; - } -} - -/* - * Map from device function return U to vector texture type T - */ -template -__forceinline__ __device__ -typename std::enable_if< - __hip_is_tex_surf_scalar_channel_type::value, const T>::type -__hipMapFrom(const U &u) { - if constexpr (sizeof(typename T::value_type) < sizeof(float)) { - union { - U u; - int4 i4; - } d = { u }; - return __hipMapVector(d.i4); - } else { // sizeof(typename T::value_type) == sizeof(float) - union { - U u; - T t; - } d = { u }; - return d.t; - } -} - -/* - * Map from scalar texture type T to device function input U - */ -template -__forceinline__ __device__ -typename std::enable_if< -__hip_is_tex_surf_scalar_channel_type::value, const U>::type -__hipMapTo(const T &t) { - if constexpr (sizeof(T) < sizeof(float)) { - union { - U u; - int i; - } d = { 0 }; - d.i = static_cast(t); - return d.u; - } else { // sizeof(T) == sizeof(float) - union { - U u; - T t; - } d = { 0 }; - d.t = t; - return d.u; - } -} - -/* - * Map from vector texture type T to device function input U - */ -template -__forceinline__ __device__ -typename std::enable_if< - __hip_is_tex_surf_scalar_channel_type::value, const U>::type -__hipMapTo(const T &t) { - if constexpr (sizeof(typename T::value_type) < sizeof(float)) { - union { - U u; - int4 i4; - } d = { 0 }; - d.i4 = __hipMapVector(t); - return d.u; - } else { // sizeof(typename T::value_type) == sizeof(float) - union { - U u; - T t; - } d = { 0 }; - d.t = t; - return d.u; - } -} - -template < - typename T, - hipTextureReadMode readMode> -using __hip_tex_ret_t = typename __hip_tex_ret::type; - -template -struct __hip_tex_ret< - T, - hipReadModeElementType, - typename std::enable_if<__hip_is_tex_surf_channel_type::value, bool>::type> -{ - using type = T; -}; - -template< - typename T, - unsigned int rank> -struct __hip_tex_ret< - HIP_vector_type, - hipReadModeElementType, - typename std::enable_if<__hip_is_tex_surf_channel_type>::value, bool>::type> -{ - using type = HIP_vector_type<__hip_tex_ret_t, rank>; -}; - -template -struct __hip_tex_ret< - T, - hipReadModeNormalizedFloat, - typename std::enable_if<__hip_is_tex_normalized_channel_type::value, bool>::type> -{ - using type = float; -}; - -template< - typename T, - unsigned int rank> -struct __hip_tex_ret< - HIP_vector_type, - hipReadModeNormalizedFloat, - typename std::enable_if<__hip_is_tex_normalized_channel_type>::value, bool>::type> -{ - using type = HIP_vector_type<__hip_tex_ret_t, rank>; -}; - - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1Dfetch(texture t, int x) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_load_1Db(i, x); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1D(texture t, float x) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_1D(i, s, x); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2D(texture t, float x, float y) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_2D(i, s, float2(x, y).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1DLayered(texture t, float x, int layer) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_1Da(i, s, float2(x, layer).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2DLayered(texture t, float x, float y, int layer) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_2Da(i, s, float4(x, y, layer, 0.0f).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex3D(texture t, float x, float y, float z) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_3D(i, s, float4(x, y, z, 0.0f).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemap(texture t, float x, float y, float z) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_CM(i, s, float4(x, y, z, 0.0f).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1DLod(texture t, float x, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_1D(i, s, x, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2DLod(texture t, float x, float y, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_2D(i, s, float2(x, y).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1DLayeredLod(texture t, float x, int layer, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_1Da(i, s, float2(x, layer).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2DLayeredLod(texture t, float x, float y, int layer, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_2Da(i, s, float4(x, y, layer, 0.0f).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex3DLod(texture t, float x, float y, float z, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_3D(i, s, float4(x, y, z, 0.0f).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemapLod(texture t, float x, float y, float z, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_CM(i, s, float4(x, y, z, 0.0f).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemapLayered(texture t, float x, float y, float z, int layer) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_CMa(i, s, float4(x, y, z, layer).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemapLayeredLod(texture t, float x, float y, float z, int layer, float level) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_lod_CMa(i, s, float4(x, y, z, layer).data, level); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemapGrad(texture t, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - TEXTURE_PARAMETERS_INIT; - // TODO missing in device libs. - // auto tmp = __ockl_image_sample_grad_CM(i, s, float4(x, y, z, 0.0f).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - // return __hipMapFrom<__hip_tex_ret_t>(tmp); - return {}; -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t texCubemapLayeredGrad(texture t, float x, float y, float z, int layer, float4 dPdx, float4 dPdy) -{ - TEXTURE_PARAMETERS_INIT; - // TODO missing in device libs. - // auto tmp = __ockl_image_sample_grad_CMa(i, s, float4(x, y, z, layer).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - // return __hipMapFrom<__hip_tex_ret_t>(tmp); - return {}; -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1DGrad(texture t, float x, float dPdx, float dPdy) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_grad_1D(i, s, x, dPdx, dPdy); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2DGrad(texture t, float x, float y, float2 dPdx, float2 dPdy) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_grad_2D(i, s, float2(x, y).data, float2(dPdx.x, dPdx.y).data, float2(dPdy.x, dPdy.y).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex1DLayeredGrad(texture t, float x, int layer, float dPdx, float dPdy) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_grad_1Da(i, s, float2(x, layer).data, dPdx, dPdy); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex2DLayeredGrad(texture t, float x, float y, int layer, float2 dPdx, float2 dPdy) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_grad_2Da(i, s, float4(x, y, layer, 0.0f).data, float2(dPdx.x, dPdx.y).data, float2(dPdy.x, dPdy.y).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex_ret_t tex3DGrad(texture t, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - TEXTURE_PARAMETERS_INIT; - auto tmp = __ockl_image_sample_grad_3D(i, s, float4(x, y, z, 0.0f).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - return __hipMapFrom<__hip_tex_ret_t>(tmp); -} - -template < - typename T, - hipTextureReadMode readMode, - typename Enable = void> -struct __hip_tex2dgather_ret -{ - static_assert(std::is_same::value, "Invalid channel type!"); -}; - -template < - typename T, - hipTextureReadMode readMode> -using __hip_tex2dgather_ret_t = typename __hip_tex2dgather_ret::type; - -template -struct __hip_tex2dgather_ret< - T, - hipReadModeElementType, - typename std::enable_if<__hip_is_tex_surf_channel_type::value, bool>::type> -{ - using type = HIP_vector_type; -}; - -template< - typename T, - unsigned int rank> -struct __hip_tex2dgather_ret< - HIP_vector_type, - hipReadModeElementType, - typename std::enable_if<__hip_is_tex_surf_channel_type>::value, bool>::type> -{ - using type = HIP_vector_type; -}; - -template -struct __hip_tex2dgather_ret< - T, - hipReadModeNormalizedFloat, - typename std::enable_if<__hip_is_tex_normalized_channel_type::value, bool>::type> -{ - using type = float4; -}; - -template -static __forceinline__ __device__ __hip_img_chk__ __hip_tex2dgather_ret_t tex2Dgather(texture t, float x, float y, int comp=0) -{ - TEXTURE_PARAMETERS_INIT; - switch (comp) { - case 1: { - auto tmp = __ockl_image_gather4g_2D(i, s, float2(x, y).data); - return __hipMapFrom<__hip_tex2dgather_ret_t>(tmp); - } - case 2: { - auto tmp = __ockl_image_gather4b_2D(i, s, float2(x, y).data); - return __hipMapFrom<__hip_tex2dgather_ret_t>(tmp); - } - case 3: { - auto tmp = __ockl_image_gather4a_2D(i, s, float2(x, y).data); - return __hipMapFrom<__hip_tex2dgather_ret_t>(tmp); - } - default: { - auto tmp = __ockl_image_gather4r_2D(i, s, float2(x, y).data); - return __hipMapFrom<__hip_tex2dgather_ret_t>(tmp); - } - } - return {}; -} - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if defined(__cplusplus) - -#if !defined(__HIPCC_RTC__) -#include -#include -#include -#include -#include -#endif // !defined(__HIPCC_RTC__) - -#define TEXTURE_OBJECT_PARAMETERS_INIT \ - unsigned int ADDRESS_SPACE_CONSTANT* i = (unsigned int ADDRESS_SPACE_CONSTANT*)textureObject; \ - unsigned int ADDRESS_SPACE_CONSTANT* s = i + HIP_SAMPLER_OBJECT_OFFSET_DWORD; - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1Dfetch(hipTextureObject_t textureObject, int x) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_load_1Db(i, x); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1Dfetch(T *ptr, hipTextureObject_t textureObject, int x) -{ - *ptr = tex1Dfetch(textureObject, x); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1D(hipTextureObject_t textureObject, float x) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_1D(i, s, x); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1D(T *ptr, hipTextureObject_t textureObject, float x) -{ - *ptr = tex1D(textureObject, x); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2D(hipTextureObject_t textureObject, float x, float y) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_2D(i, s, float2(x, y).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2D(T *ptr, hipTextureObject_t textureObject, float x, float y) -{ - *ptr = tex2D(textureObject, x, y); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex3D(hipTextureObject_t textureObject, float x, float y, float z) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_3D(i, s, float4(x, y, z, 0.0f).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex3D(T *ptr, hipTextureObject_t textureObject, float x, float y, float z) -{ - *ptr = tex3D(textureObject, x, y, z); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1DLayered(hipTextureObject_t textureObject, float x, int layer) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_1Da(i, s, float2(x, layer).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1DLayered(T *ptr, hipTextureObject_t textureObject, float x, int layer) -{ - *ptr = tex1DLayered(textureObject, x, layer); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2DLayered(hipTextureObject_t textureObject, float x, float y, int layer) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_2Da(i, s, float4(x, y, layer, 0.0f).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2DLayered(T *ptr, hipTextureObject_t textureObject, float x, float y, int layer) -{ - *ptr = tex1DLayered(textureObject, x, y, layer); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemap(hipTextureObject_t textureObject, float x, float y, float z) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_CM(i, s, float4(x, y, z, 0.0f).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemap(T *ptr, hipTextureObject_t textureObject, float x, float y, float z) -{ - *ptr = texCubemap(textureObject, x, y, z); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemapLayered(hipTextureObject_t textureObject, float x, float y, float z, int layer) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_CMa(i, s, float4(x, y, z, layer).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemapLayered(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, int layer) -{ - *ptr = texCubemapLayered(textureObject, x, y, z, layer); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2Dgather(hipTextureObject_t textureObject, float x, float y, int comp = 0) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - switch (comp) { - case 1: { - auto tmp = __ockl_image_gather4r_2D(i, s, float2(x, y).data); - return __hipMapFrom(tmp); - break; - } - case 2: { - auto tmp = __ockl_image_gather4g_2D(i, s, float2(x, y).data); - return __hipMapFrom(tmp); - break; - } - case 3: { - auto tmp = __ockl_image_gather4b_2D(i, s, float2(x, y).data); - return __hipMapFrom(tmp); - break; - } - default: { - auto tmp = __ockl_image_gather4a_2D(i, s, float2(x, y).data); - return __hipMapFrom(tmp); - break; - } - } - return {}; -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2Dgather(T *ptr, hipTextureObject_t textureObject, float x, float y, int comp = 0) -{ - *ptr = texCubemapLayered(textureObject, x, y, comp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1DLod(hipTextureObject_t textureObject, float x, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_lod_1D(i, s, x, level); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1DLod(T *ptr, hipTextureObject_t textureObject, float x, float level) -{ - *ptr = tex1DLod(textureObject, x, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2DLod(hipTextureObject_t textureObject, float x, float y, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_lod_2D(i, s, float2(x, y).data, level); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2DLod(T *ptr, hipTextureObject_t textureObject, float x, float y, float level) -{ - *ptr = tex2DLod(textureObject, x, y, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex3DLod(hipTextureObject_t textureObject, float x, float y, float z, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_lod_3D(i, s, float4(x, y, z, 0.0f).data, level); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex3DLod(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, float level) -{ - *ptr = tex3DLod(textureObject, x, y, z, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1DLayeredLod(hipTextureObject_t textureObject, float x, int layer, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_1Da(i, s, float2(x, layer).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1DLayeredLod(T *ptr, hipTextureObject_t textureObject, float x, int layer, float level) -{ - *ptr = tex1DLayeredLod(textureObject, x, layer, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2DLayeredLod(hipTextureObject_t textureObject, float x, float y, int layer, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_2Da(i, s, float4(x, y, layer, 0.0f).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2DLayeredLod(T *ptr, hipTextureObject_t textureObject, float x, float y, int layer, float level) -{ - *ptr = tex2DLayeredLod(textureObject, x, y, layer, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemapLod(hipTextureObject_t textureObject, float x, float y, float z, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_lod_CM(i, s, float4(x, y, z, 0.0f).data, level); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemapLod(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, float level) -{ - *ptr = texCubemapLod(textureObject, x, y, z, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemapGrad(hipTextureObject_t textureObject, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - // TODO missing in device libs. - // auto tmp = __ockl_image_sample_grad_CM(i, s, float4(x, y, z, 0.0f).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - // return __hipMapFrom(tmp); - return {}; -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemapGrad(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - *ptr = texCubemapGrad(textureObject, x, y, z, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemapLayeredLod(hipTextureObject_t textureObject, float x, float y, float z, int layer, float level) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_lod_CMa(i, s, float4(x, y, z, layer).data, level); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemapLayeredLod(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, int layer, float level) -{ - *ptr = texCubemapLayeredLod(textureObject, x, y, z, layer, level); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1DGrad(hipTextureObject_t textureObject, float x, float dPdx, float dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_grad_1D(i, s, x, dPdx, dPdy); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1DGrad(T *ptr, hipTextureObject_t textureObject, float x, float dPdx, float dPdy) -{ - *ptr = tex1DGrad(textureObject, x, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2DGrad(hipTextureObject_t textureObject, float x, float y, float2 dPdx, float2 dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_grad_2D(i, s, float2(x, y).data, float2(dPdx.x, dPdx.y).data, float2(dPdy.x, dPdy.y).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2DGrad(T *ptr, hipTextureObject_t textureObject, float x, float y, float2 dPdx, float2 dPdy) -{ - *ptr = tex2DGrad(textureObject, x, y, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex3DGrad(hipTextureObject_t textureObject, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_grad_3D(i, s, float4(x, y, z, 0.0f).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex3DGrad(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, float4 dPdx, float4 dPdy) -{ - *ptr = tex3DGrad(textureObject, x, y, z, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex1DLayeredGrad(hipTextureObject_t textureObject, float x, int layer, float dPdx, float dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_grad_1Da(i, s, float2(x, layer).data, dPdx, dPdy); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex1DLayeredGrad(T *ptr, hipTextureObject_t textureObject, float x, int layer, float dPdx, float dPdy) -{ - *ptr = tex1DLayeredGrad(textureObject, x, layer, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T tex2DLayeredGrad(hipTextureObject_t textureObject, float x, float y, int layer, float2 dPdx, float2 dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - auto tmp = __ockl_image_sample_grad_2Da(i, s, float4(x, y, layer, 0.0f).data, float2(dPdx.x, dPdx.y).data, float2(dPdy.x, dPdy.y).data); - return __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void tex2DLayeredGrad(T *ptr, hipTextureObject_t textureObject, float x, float y, int layer, float2 dPdx, float2 dPdy) -{ - *ptr = tex2DLayeredGrad(textureObject, x, y, layer, dPdx, dPdy); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ T texCubemapLayeredGrad(hipTextureObject_t textureObject, float x, float y, float z, int layer, float4 dPdx, float4 dPdy) -{ - TEXTURE_OBJECT_PARAMETERS_INIT - // TODO missing in device libs. - // auto tmp = __ockl_image_sample_grad_CMa(i, s, float4(x, y, z, layer).data, float4(dPdx.x, dPdx.y, dPdx.z, 0.0f).data, float4(dPdy.x, dPdy.y, dPdy.z, 0.0f).data); - // return __hipMapFrom(tmp); - return {}; -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void texCubemapLayeredGrad(T *ptr, hipTextureObject_t textureObject, float x, float y, float z, int layer, float4 dPdx, float4 dPdy) -{ - *ptr = texCubemapLayeredGrad(textureObject, x, y, z, layer, dPdx, dPdy); -} - -#endif -/* -Copyright (c) 2018 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_SURFACE_FUNCTIONS_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_SURFACE_FUNCTIONS_H - -#if defined(__cplusplus) - -#if !defined(__HIPCC_RTC__) -#include -#include -#include -#include -#endif - -#if defined(__HIPCC_RTC__) -#define __HOST_DEVICE__ __device__ -#else -#define __HOST_DEVICE__ __host__ __device__ -#endif - -#define __HIP_SURFACE_OBJECT_PARAMETERS_INIT \ - unsigned int ADDRESS_SPACE_CONSTANT* i = (unsigned int ADDRESS_SPACE_CONSTANT*)surfObj; - -// CUDA is using byte address, need map to pixel address for HIP -static __HOST_DEVICE__ __forceinline__ int __hipGetPixelAddr(int x, int format, int order) { - /* - * use below format index to generate format LUT - typedef enum { - HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0, - HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555 = 5, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565 = 6, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010 = 7, - HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8, - HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9, - HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12, - HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13, - HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14, - HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT = 15 - } hsa_ext_image_channel_type_t; - */ - static const int FormatLUT[] = { 0, 1, 0, 1, 3, 1, 1, 1, 0, 1, 2, 0, 1, 2, 1, 2 }; - x = FormatLUT[format] == 3 ? x / FormatLUT[format] : x >> FormatLUT[format]; - - /* - * use below order index to generate order LUT - typedef enum { - HSA_EXT_IMAGE_CHANNEL_ORDER_A = 0, - HSA_EXT_IMAGE_CHANNEL_ORDER_R = 1, - HSA_EXT_IMAGE_CHANNEL_ORDER_RX = 2, - HSA_EXT_IMAGE_CHANNEL_ORDER_RG = 3, - HSA_EXT_IMAGE_CHANNEL_ORDER_RGX = 4, - HSA_EXT_IMAGE_CHANNEL_ORDER_RA = 5, - HSA_EXT_IMAGE_CHANNEL_ORDER_RGB = 6, - HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX = 7, - HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA = 8, - HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA = 9, - HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB = 10, - HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR = 11, - HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB = 12, - HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX = 13, - HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA = 14, - HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA = 15, - HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY = 16, - HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE = 17, - HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH = 18, - HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19 - } hsa_ext_image_channel_order_t; - */ - static const int OrderLUT[] = { 0, 0, 1, 1, 3, 1, 3, 2, 2, 2, 2, 2, 3, 2, 2, 2, 0, 0, 0, 0 }; - return x = OrderLUT[order] == 3 ? x / OrderLUT[order] : x >> OrderLUT[order]; -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf1Dread(T* data, hipSurfaceObject_t surfObj, int x, - int boundaryMode = hipBoundaryModeZero) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_1D(i), __ockl_image_channel_order_1D(i)); - auto tmp = __ockl_image_load_1D(i, x); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf1Dwrite(T data, hipSurfaceObject_t surfObj, int x) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_1D(i), __ockl_image_channel_order_1D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_1D(i, x, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf2Dread(T* data, hipSurfaceObject_t surfObj, int x, int y) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __ockl_image_load_2D(i, int2(x, y).data); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf2Dwrite(T data, hipSurfaceObject_t surfObj, int x, int y) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_2D(i, int2(x, y).data, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf3Dread(T* data, hipSurfaceObject_t surfObj, int x, int y, int z) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_3D(i), __ockl_image_channel_order_3D(i)); - auto tmp = __ockl_image_load_3D(i, int4(x, y, z, 0).data); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf3Dwrite(T data, hipSurfaceObject_t surfObj, int x, int y, int z) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_3D(i), __ockl_image_channel_order_3D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_3D(i, int4(x, y, z, 0).data, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf1DLayeredread(T* data, hipSurfaceObject_t surfObj, int x, int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_1D(i), __ockl_image_channel_order_1D(i)); - auto tmp = __ockl_image_load_lod_1D(i, x, layer); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf1DLayeredwrite(T data, hipSurfaceObject_t surfObj, int x, int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_1D(i), __ockl_image_channel_order_1D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_lod_1D(i, x, layer, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf2DLayeredread(T* data, hipSurfaceObject_t surfObj, int x, int y, int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __ockl_image_load_lod_2D(i, int2(x, y).data, layer); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surf2DLayeredwrite(T data, hipSurfaceObject_t surfObj, int x, int y, int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_lod_2D(i, int2(x, y).data, layer, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surfCubemapread(T* data, hipSurfaceObject_t surfObj, int x, int y, int face) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __ockl_image_load_CM(i, int2(x, y).data, face); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surfCubemapwrite(T data, hipSurfaceObject_t surfObj, int x, int y, int face) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_CM(i, int2(x, y).data, face, tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surfCubemapLayeredread(T* data, hipSurfaceObject_t surfObj, int x, int y, int face, - int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __ockl_image_load_lod_CM(i, int2(x, y).data, face, layer); - *data = __hipMapFrom(tmp); -} - -template < - typename T, - typename std::enable_if<__hip_is_tex_surf_channel_type::value>::type* = nullptr> -static __device__ __hip_img_chk__ void surfCubemapLayeredwrite(T* data, hipSurfaceObject_t surfObj, int x, int y, int face, - int layer) { - __HIP_SURFACE_OBJECT_PARAMETERS_INIT - x = __hipGetPixelAddr(x, __ockl_image_channel_data_type_2D(i), __ockl_image_channel_order_2D(i)); - auto tmp = __hipMapTo(data); - __ockl_image_store_lod_CM(i, int2(x, y).data, face, layer, tmp); -} - -#endif - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COMPLEX_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COMPLEX_H - -#if !defined(__HIPCC_RTC__) -#include "hip/amd_detail/amd_hip_vector_types.h" -#endif - -#if defined(__HIPCC_RTC__) -#define __HOST_DEVICE__ __device__ -#else -#define __HOST_DEVICE__ __host__ __device__ -// TODO: Clang has a bug which allows device functions to call std functions -// when std functions are introduced into default namespace by using statement. -// math.h may be included after this bug is fixed. -#if __cplusplus -#include -#else -#include "math.h" -#endif -#endif // !defined(__HIPCC_RTC__) - -#if __cplusplus -#define COMPLEX_NEG_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type operator-(const type& op) { \ - type ret; \ - ret.x = -op.x; \ - ret.y = -op.y; \ - return ret; \ - } - -#define COMPLEX_EQ_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline bool operator==(const type& lhs, const type& rhs) { \ - return lhs.x == rhs.x && lhs.y == rhs.y; \ - } - -#define COMPLEX_NE_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline bool operator!=(const type& lhs, const type& rhs) { \ - return !(lhs == rhs); \ - } - -#define COMPLEX_ADD_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type operator+(const type& lhs, const type& rhs) { \ - type ret; \ - ret.x = lhs.x + rhs.x; \ - ret.y = lhs.y + rhs.y; \ - return ret; \ - } - -#define COMPLEX_SUB_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type operator-(const type& lhs, const type& rhs) { \ - type ret; \ - ret.x = lhs.x - rhs.x; \ - ret.y = lhs.y - rhs.y; \ - return ret; \ - } - -#define COMPLEX_MUL_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type operator*(const type& lhs, const type& rhs) { \ - type ret; \ - ret.x = lhs.x * rhs.x - lhs.y * rhs.y; \ - ret.y = lhs.x * rhs.y + lhs.y * rhs.x; \ - return ret; \ - } - -#define COMPLEX_DIV_OP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type operator/(const type& lhs, const type& rhs) { \ - type ret; \ - ret.x = (lhs.x * rhs.x + lhs.y * rhs.y); \ - ret.y = (rhs.x * lhs.y - lhs.x * rhs.y); \ - ret.x = ret.x / (rhs.x * rhs.x + rhs.y * rhs.y); \ - ret.y = ret.y / (rhs.x * rhs.x + rhs.y * rhs.y); \ - return ret; \ - } - -#define COMPLEX_ADD_PREOP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type& operator+=(type& lhs, const type& rhs) { \ - lhs.x += rhs.x; \ - lhs.y += rhs.y; \ - return lhs; \ - } - -#define COMPLEX_SUB_PREOP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type& operator-=(type& lhs, const type& rhs) { \ - lhs.x -= rhs.x; \ - lhs.y -= rhs.y; \ - return lhs; \ - } - -#define COMPLEX_MUL_PREOP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type& operator*=(type& lhs, const type& rhs) { \ - type temp{lhs}; \ - lhs.x = rhs.x * temp.x - rhs.y * temp.y; \ - lhs.y = rhs.y * temp.x + rhs.x * temp.y; \ - return lhs; \ - } - -#define COMPLEX_DIV_PREOP_OVERLOAD(type) \ - __HOST_DEVICE__ static inline type& operator/=(type& lhs, const type& rhs) { \ - type temp; \ - temp.x = (lhs.x*rhs.x + lhs.y * rhs.y) / (rhs.x*rhs.x + rhs.y*rhs.y); \ - temp.y = (lhs.y * rhs.x - lhs.x * rhs.y) / (rhs.x*rhs.x + rhs.y*rhs.y); \ - lhs = temp; \ - return lhs; \ - } - -#define COMPLEX_SCALAR_PRODUCT(type, type1) \ - __HOST_DEVICE__ static inline type operator*(const type& lhs, type1 rhs) { \ - type ret; \ - ret.x = lhs.x * rhs; \ - ret.y = lhs.y * rhs; \ - return ret; \ - } - -#endif - -typedef float2 hipFloatComplex; - -__HOST_DEVICE__ static inline float hipCrealf(hipFloatComplex z) { return z.x; } - -__HOST_DEVICE__ static inline float hipCimagf(hipFloatComplex z) { return z.y; } - -__HOST_DEVICE__ static inline hipFloatComplex make_hipFloatComplex(float a, float b) { - hipFloatComplex z; - z.x = a; - z.y = b; - return z; -} - -__HOST_DEVICE__ static inline hipFloatComplex hipConjf(hipFloatComplex z) { - hipFloatComplex ret; - ret.x = z.x; - ret.y = -z.y; - return ret; -} - -__HOST_DEVICE__ static inline float hipCsqabsf(hipFloatComplex z) { - return z.x * z.x + z.y * z.y; -} - -__HOST_DEVICE__ static inline hipFloatComplex hipCaddf(hipFloatComplex p, hipFloatComplex q) { - return make_hipFloatComplex(p.x + q.x, p.y + q.y); -} - -__HOST_DEVICE__ static inline hipFloatComplex hipCsubf(hipFloatComplex p, hipFloatComplex q) { - return make_hipFloatComplex(p.x - q.x, p.y - q.y); -} - -__HOST_DEVICE__ static inline hipFloatComplex hipCmulf(hipFloatComplex p, hipFloatComplex q) { - return make_hipFloatComplex(p.x * q.x - p.y * q.y, p.y * q.x + p.x * q.y); -} - -__HOST_DEVICE__ static inline hipFloatComplex hipCdivf(hipFloatComplex p, hipFloatComplex q) { - float sqabs = hipCsqabsf(q); - hipFloatComplex ret; - ret.x = (p.x * q.x + p.y * q.y) / sqabs; - ret.y = (p.y * q.x - p.x * q.y) / sqabs; - return ret; -} - -__HOST_DEVICE__ static inline float hipCabsf(hipFloatComplex z) { return sqrtf(hipCsqabsf(z)); } - - -typedef double2 hipDoubleComplex; - -__HOST_DEVICE__ static inline double hipCreal(hipDoubleComplex z) { return z.x; } - -__HOST_DEVICE__ static inline double hipCimag(hipDoubleComplex z) { return z.y; } - -__HOST_DEVICE__ static inline hipDoubleComplex make_hipDoubleComplex(double a, double b) { - hipDoubleComplex z; - z.x = a; - z.y = b; - return z; -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipConj(hipDoubleComplex z) { - hipDoubleComplex ret; - ret.x = z.x; - ret.y = -z.y; - return ret; -} - -__HOST_DEVICE__ static inline double hipCsqabs(hipDoubleComplex z) { - return z.x * z.x + z.y * z.y; -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipCadd(hipDoubleComplex p, hipDoubleComplex q) { - return make_hipDoubleComplex(p.x + q.x, p.y + q.y); -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipCsub(hipDoubleComplex p, hipDoubleComplex q) { - return make_hipDoubleComplex(p.x - q.x, p.y - q.y); -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipCmul(hipDoubleComplex p, hipDoubleComplex q) { - return make_hipDoubleComplex(p.x * q.x - p.y * q.y, p.y * q.x + p.x * q.y); -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipCdiv(hipDoubleComplex p, hipDoubleComplex q) { - double sqabs = hipCsqabs(q); - hipDoubleComplex ret; - ret.x = (p.x * q.x + p.y * q.y) / sqabs; - ret.y = (p.y * q.x - p.x * q.y) / sqabs; - return ret; -} - -__HOST_DEVICE__ static inline double hipCabs(hipDoubleComplex z) { return sqrt(hipCsqabs(z)); } - - -#if __cplusplus - -COMPLEX_NEG_OP_OVERLOAD(hipFloatComplex) -COMPLEX_EQ_OP_OVERLOAD(hipFloatComplex) -COMPLEX_NE_OP_OVERLOAD(hipFloatComplex) -COMPLEX_ADD_OP_OVERLOAD(hipFloatComplex) -COMPLEX_SUB_OP_OVERLOAD(hipFloatComplex) -COMPLEX_MUL_OP_OVERLOAD(hipFloatComplex) -COMPLEX_DIV_OP_OVERLOAD(hipFloatComplex) -COMPLEX_ADD_PREOP_OVERLOAD(hipFloatComplex) -COMPLEX_SUB_PREOP_OVERLOAD(hipFloatComplex) -COMPLEX_MUL_PREOP_OVERLOAD(hipFloatComplex) -COMPLEX_DIV_PREOP_OVERLOAD(hipFloatComplex) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, unsigned short) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, signed short) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, unsigned int) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, signed int) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, float) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, unsigned long) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, signed long) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, double) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, signed long long) -COMPLEX_SCALAR_PRODUCT(hipFloatComplex, unsigned long long) - -COMPLEX_NEG_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_EQ_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_NE_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_ADD_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_SUB_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_MUL_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_DIV_OP_OVERLOAD(hipDoubleComplex) -COMPLEX_ADD_PREOP_OVERLOAD(hipDoubleComplex) -COMPLEX_SUB_PREOP_OVERLOAD(hipDoubleComplex) -COMPLEX_MUL_PREOP_OVERLOAD(hipDoubleComplex) -COMPLEX_DIV_PREOP_OVERLOAD(hipDoubleComplex) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, unsigned short) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, signed short) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, unsigned int) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, signed int) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, float) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, unsigned long) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, signed long) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, double) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, signed long long) -COMPLEX_SCALAR_PRODUCT(hipDoubleComplex, unsigned long long) - -#endif - - -typedef hipFloatComplex hipComplex; - -__HOST_DEVICE__ static inline hipComplex make_hipComplex(float x, float y) { - return make_hipFloatComplex(x, y); -} - -__HOST_DEVICE__ static inline hipFloatComplex hipComplexDoubleToFloat(hipDoubleComplex z) { - return make_hipFloatComplex((float)z.x, (float)z.y); -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipComplexFloatToDouble(hipFloatComplex z) { - return make_hipDoubleComplex((double)z.x, (double)z.y); -} - -__HOST_DEVICE__ static inline hipComplex hipCfmaf(hipComplex p, hipComplex q, hipComplex r) { - float real = (p.x * q.x) + r.x; - float imag = (q.x * p.y) + r.y; - - real = -(p.y * q.y) + real; - imag = (p.x * q.y) + imag; - - return make_hipComplex(real, imag); -} - -__HOST_DEVICE__ static inline hipDoubleComplex hipCfma(hipDoubleComplex p, hipDoubleComplex q, - hipDoubleComplex r) { - double real = (p.x * q.x) + r.x; - double imag = (q.x * p.y) + r.y; - - real = -(p.y * q.y) + real; - imag = (p.x * q.y) + imag; - - return make_hipDoubleComplex(real, imag); -} - -#endif //HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COMPLEX_H -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ -#ifndef AMD_HIP_MATH_CONSTANTS_H -#define AMD_HIP_MATH_CONSTANTS_H - -// single precision constants -#define HIP_INF_F __int_as_float(0x7f800000U) -#define HIP_NAN_F __int_as_float(0x7fffffffU) -#define HIP_MIN_DENORM_F __int_as_float(0x00000001U) -#define HIP_MAX_NORMAL_F __int_as_float(0x7f7fffffU) -#define HIP_NEG_ZERO_F __int_as_float(0x80000000U) -#define HIP_ZERO_F 0.0F -#define HIP_ONE_F 1.0F -#define HIP_SQRT_HALF_F 0.707106781F -#define HIP_SQRT_HALF_HI_F 0.707106781F -#define HIP_SQRT_HALF_LO_F 1.210161749e-08F -#define HIP_SQRT_TWO_F 1.414213562F -#define HIP_THIRD_F 0.333333333F -#define HIP_PIO4_F 0.785398163F -#define HIP_PIO2_F 1.570796327F -#define HIP_3PIO4_F 2.356194490F -#define HIP_2_OVER_PI_F 0.636619772F -#define HIP_SQRT_2_OVER_PI_F 0.797884561F -#define HIP_PI_F 3.141592654F -#define HIP_L2E_F 1.442695041F -#define HIP_L2T_F 3.321928094F -#define HIP_LG2_F 0.301029996F -#define HIP_LGE_F 0.434294482F -#define HIP_LN2_F 0.693147181F -#define HIP_LNT_F 2.302585093F -#define HIP_LNPI_F 1.144729886F -#define HIP_TWO_TO_M126_F 1.175494351e-38F -#define HIP_TWO_TO_126_F 8.507059173e37F -#define HIP_NORM_HUGE_F 3.402823466e38F -#define HIP_TWO_TO_23_F 8388608.0F -#define HIP_TWO_TO_24_F 16777216.0F -#define HIP_TWO_TO_31_F 2147483648.0F -#define HIP_TWO_TO_32_F 4294967296.0F -#define HIP_REMQUO_BITS_F 3U -#define HIP_REMQUO_MASK_F (~((~0U)<::Native_vec_, - HIP_vector_base::Native_vec_, - int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot2( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - unsigned int, bool); - -__device__ -__attribute__((const)) -int __ockl_sdot4( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot4( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - unsigned int, bool); - -__device__ -__attribute__((const)) -int __ockl_sdot8(int, int, int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot8(unsigned int, unsigned int, unsigned int, bool); -#endif - -#if !__CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ -// BEGIN FLOAT -__device__ -__attribute__((const)) -float __ocml_acos_f32(float); -__device__ -__attribute__((pure)) -float __ocml_acosh_f32(float); -__device__ -__attribute__((const)) -float __ocml_asin_f32(float); -__device__ -__attribute__((pure)) -float __ocml_asinh_f32(float); -__device__ -__attribute__((const)) -float __ocml_atan2_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_atan_f32(float); -__device__ -__attribute__((pure)) -float __ocml_atanh_f32(float); -__device__ -__attribute__((pure)) -float __ocml_cbrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_ceil_f32(float); -__device__ -__attribute__((const)) -__device__ -float __ocml_copysign_f32(float, float); -__device__ -float __ocml_cos_f32(float); -__device__ -float __ocml_native_cos_f32(float); -__device__ -__attribute__((pure)) -__device__ -float __ocml_cosh_f32(float); -__device__ -float __ocml_cospi_f32(float); -__device__ -float __ocml_i0_f32(float); -__device__ -float __ocml_i1_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfc_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfcinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfcx_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erf_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_exp10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp2_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_exp_f32(float); -__device__ -__attribute__((pure)) -float __ocml_expm1_f32(float); -__device__ -__attribute__((const)) -float __ocml_fabs_f32(float); -__device__ -__attribute__((const)) -float __ocml_fdim_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_floor_f32(float); -__device__ -__attribute__((const)) -float __ocml_fma_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fmax_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_fmin_f32(float, float); -__device__ -__attribute__((const)) -__device__ -float __ocml_fmod_f32(float, float); -__device__ -float __ocml_frexp_f32(float, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -float __ocml_hypot_f32(float, float); -__device__ -__attribute__((const)) -int __ocml_ilogb_f32(float); -__device__ -__attribute__((const)) -int __ocml_isfinite_f32(float); -__device__ -__attribute__((const)) -int __ocml_isinf_f32(float); -__device__ -__attribute__((const)) -int __ocml_isnan_f32(float); -__device__ -float __ocml_j0_f32(float); -__device__ -float __ocml_j1_f32(float); -__device__ -__attribute__((const)) -float __ocml_ldexp_f32(float, int); -__device__ -float __ocml_lgamma_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log1p_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log2_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log2_f32(float); -__device__ -__attribute__((const)) -float __ocml_logb_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log_f32(float); -__device__ -float __ocml_modf_f32(float, __attribute__((address_space(5))) float*); -__device__ -__attribute__((const)) -float __ocml_nearbyint_f32(float); -__device__ -__attribute__((const)) -float __ocml_nextafter_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_len3_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_len4_f32(float, float, float, float); -__device__ -__attribute__((pure)) -float __ocml_ncdf_f32(float); -__device__ -__attribute__((pure)) -float __ocml_ncdfinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_pow_f32(float, float); -__device__ -__attribute__((pure)) -float __ocml_pown_f32(float, int); -__device__ -__attribute__((pure)) -float __ocml_rcbrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_remainder_f32(float, float); -__device__ -float __ocml_remquo_f32(float, float, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -float __ocml_rhypot_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_rint_f32(float); -__device__ -__attribute__((const)) -float __ocml_rlen3_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_rlen4_f32(float, float, float, float); -__device__ -__attribute__((const)) -float __ocml_round_f32(float); -__device__ -__attribute__((pure)) -float __ocml_rsqrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_scalb_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_scalbn_f32(float, int); -__device__ -__attribute__((const)) -int __ocml_signbit_f32(float); -__device__ -float __ocml_sincos_f32(float, __attribute__((address_space(5))) float*); -__device__ -float __ocml_sincospi_f32(float, __attribute__((address_space(5))) float*); -__device__ -float __ocml_sin_f32(float); -__device__ -float __ocml_native_sin_f32(float); -__device__ -__attribute__((pure)) -float __ocml_sinh_f32(float); -__device__ -float __ocml_sinpi_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_native_sqrt_f32(float); -__device__ -float __ocml_tan_f32(float); -__device__ -__attribute__((pure)) -float __ocml_tanh_f32(float); -__device__ -float __ocml_tgamma_f32(float); -__device__ -__attribute__((const)) -float __ocml_trunc_f32(float); -__device__ -float __ocml_y0_f32(float); -__device__ -float __ocml_y1_f32(float); - -// BEGIN INTRINSICS -__device__ -__attribute__((const)) -float __ocml_add_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rte_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtn_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtp_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtz_f32(float); -__device__ -__attribute__((const)) -float __ocml_fma_rte_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtn_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtp_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtz_f32(float, float, float); -// END INTRINSICS -// END FLOAT - -// BEGIN DOUBLE -__device__ -__attribute__((const)) -double __ocml_acos_f64(double); -__device__ -__attribute__((pure)) -double __ocml_acosh_f64(double); -__device__ -__attribute__((const)) -double __ocml_asin_f64(double); -__device__ -__attribute__((pure)) -double __ocml_asinh_f64(double); -__device__ -__attribute__((const)) -double __ocml_atan2_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_atan_f64(double); -__device__ -__attribute__((pure)) -double __ocml_atanh_f64(double); -__device__ -__attribute__((pure)) -double __ocml_cbrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_ceil_f64(double); -__device__ -__attribute__((const)) -double __ocml_copysign_f64(double, double); -__device__ -double __ocml_cos_f64(double); -__device__ -__attribute__((pure)) -double __ocml_cosh_f64(double); -__device__ -double __ocml_cospi_f64(double); -__device__ -double __ocml_i0_f64(double); -__device__ -double __ocml_i1_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfc_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfcinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfcx_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erf_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp10_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp2_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp_f64(double); -__device__ -__attribute__((pure)) -double __ocml_expm1_f64(double); -__device__ -__attribute__((const)) -double __ocml_fabs_f64(double); -__device__ -__attribute__((const)) -double __ocml_fdim_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_floor_f64(double); -__device__ -__attribute__((const)) -double __ocml_fma_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fmax_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_fmin_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_fmod_f64(double, double); -__device__ -double __ocml_frexp_f64(double, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -double __ocml_hypot_f64(double, double); -__device__ -__attribute__((const)) -int __ocml_ilogb_f64(double); -__device__ -__attribute__((const)) -int __ocml_isfinite_f64(double); -__device__ -__attribute__((const)) -int __ocml_isinf_f64(double); -__device__ -__attribute__((const)) -int __ocml_isnan_f64(double); -__device__ -double __ocml_j0_f64(double); -__device__ -double __ocml_j1_f64(double); -__device__ -__attribute__((const)) -double __ocml_ldexp_f64(double, int); -__device__ -double __ocml_lgamma_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log10_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log1p_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log2_f64(double); -__device__ -__attribute__((const)) -double __ocml_logb_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log_f64(double); -__device__ -double __ocml_modf_f64(double, __attribute__((address_space(5))) double*); -__device__ -__attribute__((const)) -double __ocml_nearbyint_f64(double); -__device__ -__attribute__((const)) -double __ocml_nextafter_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_len3_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_len4_f64(double, double, double, double); -__device__ -__attribute__((pure)) -double __ocml_ncdf_f64(double); -__device__ -__attribute__((pure)) -double __ocml_ncdfinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_pow_f64(double, double); -__device__ -__attribute__((pure)) -double __ocml_pown_f64(double, int); -__device__ -__attribute__((pure)) -double __ocml_rcbrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_remainder_f64(double, double); -__device__ -double __ocml_remquo_f64( - double, double, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -double __ocml_rhypot_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_rint_f64(double); -__device__ -__attribute__((const)) -double __ocml_rlen3_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_rlen4_f64(double, double, double, double); -__device__ -__attribute__((const)) -double __ocml_round_f64(double); -__device__ -__attribute__((pure)) -double __ocml_rsqrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_scalb_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_scalbn_f64(double, int); -__device__ -__attribute__((const)) -int __ocml_signbit_f64(double); -__device__ -double __ocml_sincos_f64(double, __attribute__((address_space(5))) double*); -__device__ -double __ocml_sincospi_f64(double, __attribute__((address_space(5))) double*); -__device__ -double __ocml_sin_f64(double); -__device__ -__attribute__((pure)) -double __ocml_sinh_f64(double); -__device__ -double __ocml_sinpi_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_f64(double); -__device__ -double __ocml_tan_f64(double); -__device__ -__attribute__((pure)) -double __ocml_tanh_f64(double); -__device__ -double __ocml_tgamma_f64(double); -__device__ -__attribute__((const)) -double __ocml_trunc_f64(double); -__device__ -double __ocml_y0_f64(double); -__device__ -double __ocml_y1_f64(double); - -// BEGIN INTRINSICS -__device__ -__attribute__((const)) -double __ocml_add_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rte_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtn_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtp_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtz_f64(double); -__device__ -__attribute__((const)) -double __ocml_fma_rte_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtn_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtp_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtz_f64(double, double, double); -// END INTRINSICS -// END DOUBLE - -#endif // !__CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ - -#if defined(__cplusplus) - } // extern "C" -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -/** - * @file amd_detail/device_library_decls.h - * @brief Contains declarations for types and functions in device library. - * Uses int64_t and uint64_t instead of long, long long, unsigned - * long and unsigned long long types for device library API - * declarations. - */ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_DEVICE_LIBRARY_DECLS_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_DEVICE_LIBRARY_DECLS_H - -#if !defined(__HIPCC_RTC__) -#include "hip/amd_detail/host_defines.h" -#endif - -typedef unsigned char uchar; -typedef unsigned short ushort; -typedef unsigned int uint; -typedef unsigned long ulong; -typedef unsigned long long ullong; - -extern "C" __device__ __attribute__((const)) bool __ockl_wfany_i32(int); -extern "C" __device__ __attribute__((const)) bool __ockl_wfall_i32(int); -extern "C" __device__ uint __ockl_activelane_u32(void); - -extern "C" __device__ __attribute__((const)) uint __ockl_mul24_u32(uint, uint); -extern "C" __device__ __attribute__((const)) int __ockl_mul24_i32(int, int); -extern "C" __device__ __attribute__((const)) uint __ockl_mul_hi_u32(uint, uint); -extern "C" __device__ __attribute__((const)) int __ockl_mul_hi_i32(int, int); -extern "C" __device__ __attribute__((const)) uint __ockl_sadd_u32(uint, uint, uint); - -extern "C" __device__ __attribute__((const)) uchar __ockl_clz_u8(uchar); -extern "C" __device__ __attribute__((const)) ushort __ockl_clz_u16(ushort); -extern "C" __device__ __attribute__((const)) uint __ockl_clz_u32(uint); -extern "C" __device__ __attribute__((const)) uint64_t __ockl_clz_u64(uint64_t); - -extern "C" __device__ __attribute__((const)) float __ocml_floor_f32(float); -extern "C" __device__ __attribute__((const)) float __ocml_rint_f32(float); -extern "C" __device__ __attribute__((const)) float __ocml_ceil_f32(float); -extern "C" __device__ __attribute__((const)) float __ocml_trunc_f32(float); - -extern "C" __device__ __attribute__((const)) float __ocml_fmin_f32(float, float); -extern "C" __device__ __attribute__((const)) float __ocml_fmax_f32(float, float); - -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtn_f32_f64(double); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtp_f32_f64(double); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtz_f32_f64(double); - -extern "C" __device__ __attribute__((const)) _Float16 __ocml_cvtrtn_f16_f32(float); -extern "C" __device__ __attribute__((const)) _Float16 __ocml_cvtrtp_f16_f32(float); -extern "C" __device__ __attribute__((const)) _Float16 __ocml_cvtrtz_f16_f32(float); - -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtn_f32_s32(int); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtp_f32_s32(int); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtz_f32_s32(int); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtn_f32_u32(uint32_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtp_f32_u32(uint32_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtz_f32_u32(uint32_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtn_f32_s64(int64_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtp_f32_s64(int64_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtz_f32_s64(int64_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtn_f32_u64(uint64_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtp_f32_u64(uint64_t); -extern "C" __device__ __attribute__((const)) float __ocml_cvtrtz_f32_u64(uint64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtn_f64_s64(int64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtp_f64_s64(int64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtz_f64_s64(int64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtn_f64_u64(uint64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtp_f64_u64(uint64_t); -extern "C" __device__ __attribute__((const)) double __ocml_cvtrtz_f64_u64(uint64_t); - -extern "C" __device__ __attribute__((convergent)) void __ockl_gws_init(uint nwm1, uint rid); -extern "C" __device__ __attribute__((convergent)) void __ockl_gws_barrier(uint nwm1, uint rid); - -extern "C" __device__ __attribute__((const)) uint32_t __ockl_lane_u32(); -extern "C" __device__ __attribute__((const)) int __ockl_grid_is_valid(void); -extern "C" __device__ __attribute__((convergent)) void __ockl_grid_sync(void); -extern "C" __device__ __attribute__((const)) uint __ockl_multi_grid_num_grids(void); -extern "C" __device__ __attribute__((const)) uint __ockl_multi_grid_grid_rank(void); -extern "C" __device__ __attribute__((const)) uint __ockl_multi_grid_size(void); -extern "C" __device__ __attribute__((const)) uint __ockl_multi_grid_thread_rank(void); -extern "C" __device__ __attribute__((const)) int __ockl_multi_grid_is_valid(void); -extern "C" __device__ __attribute__((convergent)) void __ockl_multi_grid_sync(void); - -extern "C" __device__ void __ockl_atomic_add_noret_f32(float*, float); - -extern "C" __device__ __attribute__((convergent)) int __ockl_wgred_add_i32(int a); -extern "C" __device__ __attribute__((convergent)) int __ockl_wgred_and_i32(int a); -extern "C" __device__ __attribute__((convergent)) int __ockl_wgred_or_i32(int a); - -extern "C" __device__ uint64_t __ockl_fprintf_stderr_begin(); -extern "C" __device__ uint64_t __ockl_fprintf_append_args(uint64_t msg_desc, uint32_t num_args, - uint64_t value0, uint64_t value1, - uint64_t value2, uint64_t value3, - uint64_t value4, uint64_t value5, - uint64_t value6, uint32_t is_last); -extern "C" __device__ uint64_t __ockl_fprintf_append_string_n(uint64_t msg_desc, const char* data, - uint64_t length, uint32_t is_last); - -// Introduce local address space -#define __local __attribute__((address_space(3))) - -#ifdef __HIP_DEVICE_COMPILE__ -__device__ inline static __local void* __to_local(unsigned x) { return (__local void*)x; } -#endif //__HIP_DEVICE_COMPILE__ - -// Using hip.amdgcn.bc - sync threads -#define __CLK_LOCAL_MEM_FENCE 0x01 -typedef unsigned __cl_mem_fence_flags; - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_DEVICE_FUNCTIONS_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_DEVICE_FUNCTIONS_H - -#if !defined(__HIPCC_RTC__) -#include -#include "host_defines.h" -#include "math_fwd.h" -#include -#include -#include -#include -#endif // !defined(__HIPCC_RTC__) - -#if defined(__clang__) && defined(__HIP__) -extern "C" __device__ int printf(const char *fmt, ...); -#else -template -static inline __device__ void printf(const char* format, All... all) {} -#endif // __HIP_CLANG_ONLY__ - -extern "C" __device__ unsigned long long __ockl_steadyctr_u64(); - -/* -Integer Intrinsics -*/ - -// integer intrinsic function __poc __clz __ffs __brev -__device__ static inline unsigned int __popc(unsigned int input) { - return __builtin_popcount(input); -} -__device__ static inline unsigned int __popcll(unsigned long long int input) { - return __builtin_popcountll(input); -} - -__device__ static inline int __clz(int input) { - return __ockl_clz_u32((uint)input); -} - -__device__ static inline int __clzll(long long int input) { - return __ockl_clz_u64((uint64_t)input); -} - -__device__ static inline unsigned int __ffs(unsigned int input) { - return ( input == 0 ? -1 : __builtin_ctz(input) ) + 1; -} - -__device__ static inline unsigned int __ffsll(unsigned long long int input) { - return ( input == 0 ? -1 : __builtin_ctzll(input) ) + 1; -} - -__device__ static inline unsigned int __ffs(int input) { - return ( input == 0 ? -1 : __builtin_ctz(input) ) + 1; -} - -__device__ static inline unsigned int __ffsll(long long int input) { - return ( input == 0 ? -1 : __builtin_ctzll(input) ) + 1; -} - -// Given a 32/64-bit value exec mask and an integer value base (between 0 and WAVEFRONT_SIZE), -// find the n-th (given by offset) set bit in the exec mask from the base bit, and return the bit position. -// If not found, return -1. -__device__ static int32_t __fns64(uint64_t mask, uint32_t base, int32_t offset) { - uint64_t temp_mask = mask; - int32_t temp_offset = offset; - - if (offset == 0) { - temp_mask &= (1 << base); - temp_offset = 1; - } - else if (offset < 0) { - temp_mask = __builtin_bitreverse64(mask); - base = 63 - base; - temp_offset = -offset; - } - - temp_mask = temp_mask & ((~0ULL) << base); - if (__builtin_popcountll(temp_mask) < temp_offset) - return -1; - int32_t total = 0; - for (int i = 0x20; i > 0; i >>= 1) { - uint64_t temp_mask_lo = temp_mask & ((1ULL << i) - 1); - int32_t pcnt = __builtin_popcountll(temp_mask_lo); - if (pcnt < temp_offset) { - temp_mask = temp_mask >> i; - temp_offset -= pcnt; - total += i; - } - else { - temp_mask = temp_mask_lo; - } - } - if (offset < 0) - return 63 - total; - else - return total; -} - -__device__ static int32_t __fns32(uint64_t mask, uint32_t base, int32_t offset) { - uint64_t temp_mask = mask; - int32_t temp_offset = offset; - if (offset == 0) { - temp_mask &= (1 << base); - temp_offset = 1; - } - else if (offset < 0) { - temp_mask = __builtin_bitreverse64(mask); - base = 63 - base; - temp_offset = -offset; - } - temp_mask = temp_mask & ((~0ULL) << base); - if (__builtin_popcountll(temp_mask) < temp_offset) - return -1; - int32_t total = 0; - for (int i = 0x20; i > 0; i >>= 1) { - uint64_t temp_mask_lo = temp_mask & ((1ULL << i) - 1); - int32_t pcnt = __builtin_popcountll(temp_mask_lo); - if (pcnt < temp_offset) { - temp_mask = temp_mask >> i; - temp_offset -= pcnt; - total += i; - } - else { - temp_mask = temp_mask_lo; - } - } - if (offset < 0) - return 63 - total; - else - return total; -} -__device__ static inline unsigned int __brev(unsigned int input) { - return __builtin_bitreverse32(input); -} - -__device__ static inline unsigned long long int __brevll(unsigned long long int input) { - return __builtin_bitreverse64(input); -} - -__device__ static inline unsigned int __lastbit_u32_u64(uint64_t input) { - return input == 0 ? -1 : __builtin_ctzl(input); -} - -__device__ static inline unsigned int __bitextract_u32(unsigned int src0, unsigned int src1, unsigned int src2) { - uint32_t offset = src1 & 31; - uint32_t width = src2 & 31; - return width == 0 ? 0 : (src0 << (32 - offset - width)) >> (32 - width); -} - -__device__ static inline uint64_t __bitextract_u64(uint64_t src0, unsigned int src1, unsigned int src2) { - uint64_t offset = src1 & 63; - uint64_t width = src2 & 63; - return width == 0 ? 0 : (src0 << (64 - offset - width)) >> (64 - width); -} - -__device__ static inline unsigned int __bitinsert_u32(unsigned int src0, unsigned int src1, unsigned int src2, unsigned int src3) { - uint32_t offset = src2 & 31; - uint32_t width = src3 & 31; - uint32_t mask = (1 << width) - 1; - return ((src0 & ~(mask << offset)) | ((src1 & mask) << offset)); -} - -__device__ static inline uint64_t __bitinsert_u64(uint64_t src0, uint64_t src1, unsigned int src2, unsigned int src3) { - uint64_t offset = src2 & 63; - uint64_t width = src3 & 63; - uint64_t mask = (1ULL << width) - 1; - return ((src0 & ~(mask << offset)) | ((src1 & mask) << offset)); -} - -__device__ inline unsigned int __funnelshift_l(unsigned int lo, unsigned int hi, unsigned int shift) -{ - uint32_t mask_shift = shift & 31; - return mask_shift == 0 ? hi : __builtin_amdgcn_alignbit(hi, lo, 32 - mask_shift); -} - -__device__ inline unsigned int __funnelshift_lc(unsigned int lo, unsigned int hi, unsigned int shift) -{ - uint32_t min_shift = shift >= 32 ? 32 : shift; - return min_shift == 0 ? hi : __builtin_amdgcn_alignbit(hi, lo, 32 - min_shift); -} - -__device__ inline unsigned int __funnelshift_r(unsigned int lo, unsigned int hi, unsigned int shift) -{ - return __builtin_amdgcn_alignbit(hi, lo, shift); -} - -__device__ inline unsigned int __funnelshift_rc(unsigned int lo, unsigned int hi, unsigned int shift) -{ - return shift >= 32 ? hi : __builtin_amdgcn_alignbit(hi, lo, shift); -} - -__device__ static unsigned int __byte_perm(unsigned int x, unsigned int y, unsigned int s); -__device__ static unsigned int __hadd(int x, int y); -__device__ static int __mul24(int x, int y); -__device__ static long long int __mul64hi(long long int x, long long int y); -__device__ static int __mulhi(int x, int y); -__device__ static int __rhadd(int x, int y); -__device__ static unsigned int __sad(int x, int y,unsigned int z); -__device__ static unsigned int __uhadd(unsigned int x, unsigned int y); -__device__ static int __umul24(unsigned int x, unsigned int y); -__device__ static unsigned long long int __umul64hi(unsigned long long int x, unsigned long long int y); -__device__ static unsigned int __umulhi(unsigned int x, unsigned int y); -__device__ static unsigned int __urhadd(unsigned int x, unsigned int y); -__device__ static unsigned int __usad(unsigned int x, unsigned int y, unsigned int z); - -struct ucharHolder { - union { - unsigned char c[4]; - unsigned int ui; - }; -} __attribute__((aligned(4))); - -struct uchar2Holder { - union { - unsigned int ui[2]; - unsigned char c[8]; - }; -} __attribute__((aligned(8))); - -__device__ -static inline unsigned int __byte_perm(unsigned int x, unsigned int y, unsigned int s) { - struct uchar2Holder cHoldVal; - struct ucharHolder cHoldKey; - cHoldKey.ui = s; - cHoldVal.ui[0] = x; - cHoldVal.ui[1] = y; - unsigned int result; - result = cHoldVal.c[cHoldKey.c[0] & 0x07]; - result += (cHoldVal.c[(cHoldKey.c[0] & 0x70) >> 4] << 8); - result += (cHoldVal.c[cHoldKey.c[1] & 0x07] << 16); - result += (cHoldVal.c[(cHoldKey.c[1] & 0x70) >> 4] << 24); - return result; -} - -__device__ static inline unsigned int __hadd(int x, int y) { - int z = x + y; - int sign = z & 0x8000000; - int value = z & 0x7FFFFFFF; - return ((value) >> 1 || sign); -} - -__device__ static inline int __mul24(int x, int y) { - return __ockl_mul24_i32(x, y); -} - -__device__ static inline long long __mul64hi(long long int x, long long int y) { - ulong x0 = (ulong)x & 0xffffffffUL; - long x1 = x >> 32; - ulong y0 = (ulong)y & 0xffffffffUL; - long y1 = y >> 32; - ulong z0 = x0*y0; - long t = x1*y0 + (z0 >> 32); - long z1 = t & 0xffffffffL; - long z2 = t >> 32; - z1 = x0*y1 + z1; - return x1*y1 + z2 + (z1 >> 32); -} - -__device__ static inline int __mulhi(int x, int y) { - return __ockl_mul_hi_i32(x, y); -} - -__device__ static inline int __rhadd(int x, int y) { - int z = x + y + 1; - int sign = z & 0x8000000; - int value = z & 0x7FFFFFFF; - return ((value) >> 1 || sign); -} -__device__ static inline unsigned int __sad(int x, int y, unsigned int z) { - return x > y ? x - y + z : y - x + z; -} -__device__ static inline unsigned int __uhadd(unsigned int x, unsigned int y) { - return (x + y) >> 1; -} -__device__ static inline int __umul24(unsigned int x, unsigned int y) { - return __ockl_mul24_u32(x, y); -} - -__device__ -static inline unsigned long long __umul64hi(unsigned long long int x, unsigned long long int y) { - ulong x0 = x & 0xffffffffUL; - ulong x1 = x >> 32; - ulong y0 = y & 0xffffffffUL; - ulong y1 = y >> 32; - ulong z0 = x0*y0; - ulong t = x1*y0 + (z0 >> 32); - ulong z1 = t & 0xffffffffUL; - ulong z2 = t >> 32; - z1 = x0*y1 + z1; - return x1*y1 + z2 + (z1 >> 32); -} - -__device__ static inline unsigned int __umulhi(unsigned int x, unsigned int y) { - return __ockl_mul_hi_u32(x, y); -} -__device__ static inline unsigned int __urhadd(unsigned int x, unsigned int y) { - return (x + y + 1) >> 1; -} -__device__ static inline unsigned int __usad(unsigned int x, unsigned int y, unsigned int z) { - return __ockl_sadd_u32(x, y, z); -} - -__device__ static inline unsigned int __lane_id() { - return __builtin_amdgcn_mbcnt_hi( - -1, __builtin_amdgcn_mbcnt_lo(-1, 0)); -} - -__device__ -static inline unsigned int __mbcnt_lo(unsigned int x, unsigned int y) {return __builtin_amdgcn_mbcnt_lo(x,y);}; - -__device__ -static inline unsigned int __mbcnt_hi(unsigned int x, unsigned int y) {return __builtin_amdgcn_mbcnt_hi(x,y);}; - -/* -HIP specific device functions -*/ - -#if !defined(__HIPCC_RTC__) -#include "amd_warp_functions.h" -#endif - -#define MASK1 0x00ff00ff -#define MASK2 0xff00ff00 - -__device__ static inline char4 __hip_hc_add8pk(char4 in1, char4 in2) { - char4 out; - unsigned one1 = in1.w & MASK1; - unsigned one2 = in2.w & MASK1; - out.w = (one1 + one2) & MASK1; - one1 = in1.w & MASK2; - one2 = in2.w & MASK2; - out.w = out.w | ((one1 + one2) & MASK2); - return out; -} - -__device__ static inline char4 __hip_hc_sub8pk(char4 in1, char4 in2) { - char4 out; - unsigned one1 = in1.w & MASK1; - unsigned one2 = in2.w & MASK1; - out.w = (one1 - one2) & MASK1; - one1 = in1.w & MASK2; - one2 = in2.w & MASK2; - out.w = out.w | ((one1 - one2) & MASK2); - return out; -} - -__device__ static inline char4 __hip_hc_mul8pk(char4 in1, char4 in2) { - char4 out; - unsigned one1 = in1.w & MASK1; - unsigned one2 = in2.w & MASK1; - out.w = (one1 * one2) & MASK1; - one1 = in1.w & MASK2; - one2 = in2.w & MASK2; - out.w = out.w | ((one1 * one2) & MASK2); - return out; -} - -__device__ static inline float __double2float_rd(double x) { - return __ocml_cvtrtn_f32_f64(x); -} -__device__ static inline float __double2float_rn(double x) { return x; } -__device__ static inline float __double2float_ru(double x) { - return __ocml_cvtrtp_f32_f64(x); -} -__device__ static inline float __double2float_rz(double x) { - return __ocml_cvtrtz_f32_f64(x); -} - -__device__ static inline int __double2hiint(double x) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - - int tmp[2]; - __builtin_memcpy(tmp, &x, sizeof(tmp)); - - return tmp[1]; -} -__device__ static inline int __double2loint(double x) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - - int tmp[2]; - __builtin_memcpy(tmp, &x, sizeof(tmp)); - - return tmp[0]; -} - -__device__ static inline int __double2int_rd(double x) { return (int)__ocml_floor_f64(x); } -__device__ static inline int __double2int_rn(double x) { return (int)__ocml_rint_f64(x); } -__device__ static inline int __double2int_ru(double x) { return (int)__ocml_ceil_f64(x); } -__device__ static inline int __double2int_rz(double x) { return (int)x; } - -__device__ static inline long long int __double2ll_rd(double x) { - return (long long)__ocml_floor_f64(x); -} -__device__ static inline long long int __double2ll_rn(double x) { - return (long long)__ocml_rint_f64(x); -} -__device__ static inline long long int __double2ll_ru(double x) { - return (long long)__ocml_ceil_f64(x); -} -__device__ static inline long long int __double2ll_rz(double x) { return (long long)x; } - -__device__ static inline unsigned int __double2uint_rd(double x) { - return (unsigned int)__ocml_floor_f64(x); -} -__device__ static inline unsigned int __double2uint_rn(double x) { - return (unsigned int)__ocml_rint_f64(x); -} -__device__ static inline unsigned int __double2uint_ru(double x) { - return (unsigned int)__ocml_ceil_f64(x); -} -__device__ static inline unsigned int __double2uint_rz(double x) { return (unsigned int)x; } - -__device__ static inline unsigned long long int __double2ull_rd(double x) { - return (unsigned long long int)__ocml_floor_f64(x); -} -__device__ static inline unsigned long long int __double2ull_rn(double x) { - return (unsigned long long int)__ocml_rint_f64(x); -} -__device__ static inline unsigned long long int __double2ull_ru(double x) { - return (unsigned long long int)__ocml_ceil_f64(x); -} -__device__ static inline unsigned long long int __double2ull_rz(double x) { - return (unsigned long long int)x; -} -__device__ static inline long long int __double_as_longlong(double x) { - static_assert(sizeof(long long) == sizeof(double), ""); - - long long tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -/* -__device__ unsigned short __float2half_rn(float x); -__device__ float __half2float(unsigned short); - -The above device function are not a valid . -Use -__device__ __half __float2half_rn(float x); -__device__ float __half2float(__half); -from hip_fp16.h - -CUDA implements half as unsigned short whereas, HIP doesn't. - -*/ - -__device__ static inline int __float2int_rd(float x) { return (int)__ocml_floor_f32(x); } -__device__ static inline int __float2int_rn(float x) { return (int)__ocml_rint_f32(x); } -__device__ static inline int __float2int_ru(float x) { return (int)__ocml_ceil_f32(x); } -__device__ static inline int __float2int_rz(float x) { return (int)__ocml_trunc_f32(x); } - -__device__ static inline long long int __float2ll_rd(float x) { - return (long long int)__ocml_floor_f32(x); -} -__device__ static inline long long int __float2ll_rn(float x) { - return (long long int)__ocml_rint_f32(x); -} -__device__ static inline long long int __float2ll_ru(float x) { - return (long long int)__ocml_ceil_f32(x); -} -__device__ static inline long long int __float2ll_rz(float x) { return (long long int)x; } - -__device__ static inline unsigned int __float2uint_rd(float x) { - return (unsigned int)__ocml_floor_f32(x); -} -__device__ static inline unsigned int __float2uint_rn(float x) { - return (unsigned int)__ocml_rint_f32(x); -} -__device__ static inline unsigned int __float2uint_ru(float x) { - return (unsigned int)__ocml_ceil_f32(x); -} -__device__ static inline unsigned int __float2uint_rz(float x) { return (unsigned int)x; } - -__device__ static inline unsigned long long int __float2ull_rd(float x) { - return (unsigned long long int)__ocml_floor_f32(x); -} -__device__ static inline unsigned long long int __float2ull_rn(float x) { - return (unsigned long long int)__ocml_rint_f32(x); -} -__device__ static inline unsigned long long int __float2ull_ru(float x) { - return (unsigned long long int)__ocml_ceil_f32(x); -} -__device__ static inline unsigned long long int __float2ull_rz(float x) { - return (unsigned long long int)x; -} - -__device__ static inline int __float_as_int(float x) { - static_assert(sizeof(int) == sizeof(float), ""); - - int tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -__device__ static inline unsigned int __float_as_uint(float x) { - static_assert(sizeof(unsigned int) == sizeof(float), ""); - - unsigned int tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -__device__ static inline double __hiloint2double(int hi, int lo) { - static_assert(sizeof(double) == sizeof(uint64_t), ""); - - uint64_t tmp0 = (static_cast(hi) << 32ull) | static_cast(lo); - double tmp1; - __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - - return tmp1; -} - -__device__ static inline double __int2double_rn(int x) { return (double)x; } - -__device__ static inline float __int2float_rd(int x) { - return __ocml_cvtrtn_f32_s32(x); -} -__device__ static inline float __int2float_rn(int x) { return (float)x; } -__device__ static inline float __int2float_ru(int x) { - return __ocml_cvtrtp_f32_s32(x); -} -__device__ static inline float __int2float_rz(int x) { - return __ocml_cvtrtz_f32_s32(x); -} - -__device__ static inline float __int_as_float(int x) { - static_assert(sizeof(float) == sizeof(int), ""); - - float tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -__device__ static inline double __ll2double_rd(long long int x) { - return __ocml_cvtrtn_f64_s64(x); -} -__device__ static inline double __ll2double_rn(long long int x) { return (double)x; } -__device__ static inline double __ll2double_ru(long long int x) { - return __ocml_cvtrtp_f64_s64(x); -} -__device__ static inline double __ll2double_rz(long long int x) { - return __ocml_cvtrtz_f64_s64(x); -} - -__device__ static inline float __ll2float_rd(long long int x) { - return __ocml_cvtrtn_f32_s64(x); -} -__device__ static inline float __ll2float_rn(long long int x) { return (float)x; } -__device__ static inline float __ll2float_ru(long long int x) { - return __ocml_cvtrtp_f32_s64(x); -} -__device__ static inline float __ll2float_rz(long long int x) { - return __ocml_cvtrtz_f32_s64(x); -} - -__device__ static inline double __longlong_as_double(long long int x) { - static_assert(sizeof(double) == sizeof(long long), ""); - - double tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -__device__ static inline double __uint2double_rn(unsigned int x) { return (double)x; } - -__device__ static inline float __uint2float_rd(unsigned int x) { - return __ocml_cvtrtn_f32_u32(x); -} -__device__ static inline float __uint2float_rn(unsigned int x) { return (float)x; } -__device__ static inline float __uint2float_ru(unsigned int x) { - return __ocml_cvtrtp_f32_u32(x); -} -__device__ static inline float __uint2float_rz(unsigned int x) { - return __ocml_cvtrtz_f32_u32(x); -} - -__device__ static inline float __uint_as_float(unsigned int x) { - static_assert(sizeof(float) == sizeof(unsigned int), ""); - - float tmp; - __builtin_memcpy(&tmp, &x, sizeof(tmp)); - - return tmp; -} - -__device__ static inline double __ull2double_rd(unsigned long long int x) { - return __ocml_cvtrtn_f64_u64(x); -} -__device__ static inline double __ull2double_rn(unsigned long long int x) { return (double)x; } -__device__ static inline double __ull2double_ru(unsigned long long int x) { - return __ocml_cvtrtp_f64_u64(x); -} -__device__ static inline double __ull2double_rz(unsigned long long int x) { - return __ocml_cvtrtz_f64_u64(x); -} - -__device__ static inline float __ull2float_rd(unsigned long long int x) { - return __ocml_cvtrtn_f32_u64(x); -} -__device__ static inline float __ull2float_rn(unsigned long long int x) { return (float)x; } -__device__ static inline float __ull2float_ru(unsigned long long int x) { - return __ocml_cvtrtp_f32_u64(x); -} -__device__ static inline float __ull2float_rz(unsigned long long int x) { - return __ocml_cvtrtz_f32_u64(x); -} - -#if defined(__clang__) && defined(__HIP__) - -// Clock functions -__device__ long long int __clock64(); -__device__ long long int __clock(); -__device__ long long int clock64(); -__device__ long long int clock(); -__device__ long long int wall_clock64(); -// hip.amdgcn.bc - named sync -__device__ void __named_sync(); - -#ifdef __HIP_DEVICE_COMPILE__ - -// Clock function to return GPU core cycle count. -// GPU can change its core clock frequency at runtime. The maximum frequency can be queried -// through hipDeviceAttributeClockRate attribute. -__device__ -inline __attribute((always_inline)) -long long int __clock64() { -#if __has_builtin(__builtin_amdgcn_s_memtime) - // Exists on gfx8, gfx9, gfx10.1, gfx10.2, gfx10.3 - return (long long int) __builtin_amdgcn_s_memtime(); -#else - // Subject to change when better solution available - return (long long int) __builtin_readcyclecounter(); -#endif -} - -__device__ -inline __attribute((always_inline)) -long long int __clock() { return __clock64(); } - -// Clock function to return wall clock count at a constant frequency that can be queried -// through hipDeviceAttributeWallClockRate attribute. -__device__ -inline __attribute__((always_inline)) -long long int wall_clock64() { - return (long long int) __ockl_steadyctr_u64(); -} - -__device__ -inline __attribute__((always_inline)) -long long int clock64() { return __clock64(); } - -__device__ -inline __attribute__((always_inline)) -long long int clock() { return __clock(); } - -// hip.amdgcn.bc - named sync -__device__ -inline -void __named_sync() { __builtin_amdgcn_s_barrier(); } - -#endif // __HIP_DEVICE_COMPILE__ - -// warp vote function __all __any __ballot -__device__ -inline -int __all(int predicate) { - return __ockl_wfall_i32(predicate); -} - -__device__ -inline -int __any(int predicate) { - return __ockl_wfany_i32(predicate); -} - -// XXX from llvm/include/llvm/IR/InstrTypes.h -#define ICMP_NE 33 - -__device__ -inline -unsigned long long int __ballot(int predicate) { - return __builtin_amdgcn_uicmp(predicate, 0, ICMP_NE); -} - -__device__ -inline -unsigned long long int __ballot64(int predicate) { - return __builtin_amdgcn_uicmp(predicate, 0, ICMP_NE); -} - -// hip.amdgcn.bc - lanemask -__device__ -inline -uint64_t __lanemask_gt() -{ - uint32_t lane = __ockl_lane_u32(); - if (lane == 63) - return 0; - uint64_t ballot = __ballot64(1); - uint64_t mask = (~((uint64_t)0)) << (lane + 1); - return mask & ballot; -} - -__device__ -inline -uint64_t __lanemask_lt() -{ - uint32_t lane = __ockl_lane_u32(); - int64_t ballot = __ballot64(1); - uint64_t mask = ((uint64_t)1 << lane) - (uint64_t)1; - return mask & ballot; -} - -__device__ -inline -uint64_t __lanemask_eq() -{ - uint32_t lane = __ockl_lane_u32(); - int64_t mask = ((uint64_t)1 << lane); - return mask; -} - - -__device__ inline void* __local_to_generic(void* p) { return p; } - -#ifdef __HIP_DEVICE_COMPILE__ -__device__ -inline -void* __get_dynamicgroupbaseptr() -{ - // Get group segment base pointer. - return (char*)__local_to_generic((void*)__to_local(__builtin_amdgcn_groupstaticsize())); -} -#else -__device__ -void* __get_dynamicgroupbaseptr(); -#endif // __HIP_DEVICE_COMPILE__ - -__device__ -inline -void *__amdgcn_get_dynamicgroupbaseptr() { - return __get_dynamicgroupbaseptr(); -} - -// Memory Fence Functions -__device__ -inline -static void __threadfence() -{ - __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "agent"); -} - -__device__ -inline -static void __threadfence_block() -{ - __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup"); -} - -__device__ -inline -static void __threadfence_system() -{ - __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, ""); -} - -// abort -__device__ -inline -__attribute__((weak)) -void abort() { - return __builtin_trap(); -} - -// The noinline attribute helps encapsulate the printf expansion, -// which otherwise has a performance impact just by increasing the -// size of the calling function. Additionally, the weak attribute -// allows the function to exist as a global although its definition is -// included in every compilation unit. -#if defined(_WIN32) || defined(_WIN64) -extern "C" __device__ __attribute__((noinline)) __attribute__((weak)) -void _wassert(const wchar_t *_msg, const wchar_t *_file, unsigned _line) { - // FIXME: Need `wchar_t` support to generate assertion message. - __builtin_trap(); -} -#else /* defined(_WIN32) || defined(_WIN64) */ -extern "C" __device__ __attribute__((noinline)) __attribute__((weak)) -void __assert_fail(const char *assertion, - const char *file, - unsigned int line, - const char *function) -{ - const char fmt[] = "%s:%u: %s: Device-side assertion `%s' failed.\n"; - - // strlen is not available as a built-in yet, so we create our own - // loop in a macro. With a string literal argument, the compiler - // usually manages to replace the loop with a constant. - // - // The macro does not check for null pointer, since all the string - // arguments are defined to be constant literals when called from - // the assert() macro. - // - // NOTE: The loop below includes the null terminator in the length - // as required by append_string_n(). -#define __hip_get_string_length(LEN, STR) \ - do { \ - const char *tmp = STR; \ - while (*tmp++); \ - LEN = tmp - STR; \ - } while (0) - - auto msg = __ockl_fprintf_stderr_begin(); - int len = 0; - __hip_get_string_length(len, fmt); - msg = __ockl_fprintf_append_string_n(msg, fmt, len, 0); - __hip_get_string_length(len, file); - msg = __ockl_fprintf_append_string_n(msg, file, len, 0); - msg = __ockl_fprintf_append_args(msg, 1, line, 0, 0, 0, 0, 0, 0, 0); - __hip_get_string_length(len, function); - msg = __ockl_fprintf_append_string_n(msg, function, len, 0); - __hip_get_string_length(len, assertion); - __ockl_fprintf_append_string_n(msg, assertion, len, /* is_last = */ 1); - -#undef __hip_get_string_length - - __builtin_trap(); -} - -extern "C" __device__ __attribute__((noinline)) __attribute__((weak)) -void __assertfail() -{ - // ignore all the args for now. - __builtin_trap(); -} -#endif /* defined(_WIN32) || defined(_WIN64) */ - -__device__ inline static void __work_group_barrier(__cl_mem_fence_flags flags) { - if (flags) { - __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); - __builtin_amdgcn_s_barrier(); - __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); - } else { - __builtin_amdgcn_s_barrier(); - } -} - -__device__ -inline -static void __barrier(int n) -{ - __work_group_barrier((__cl_mem_fence_flags)n); -} - -__device__ -inline -__attribute__((convergent)) -void __syncthreads() -{ - __barrier(__CLK_LOCAL_MEM_FENCE); -} - -__device__ -inline -__attribute__((convergent)) -int __syncthreads_count(int predicate) -{ - return __ockl_wgred_add_i32(!!predicate); -} - -__device__ -inline -__attribute__((convergent)) -int __syncthreads_and(int predicate) -{ - return __ockl_wgred_and_i32(!!predicate); -} - -__device__ -inline -__attribute__((convergent)) -int __syncthreads_or(int predicate) -{ - return __ockl_wgred_or_i32(!!predicate); -} - -// hip.amdgcn.bc - device routine -/* - HW_ID Register bit structure for RDNA2 & RDNA3 - WAVE_ID 4:0 Wave id within the SIMD. - SIMD_ID 9:8 SIMD_ID within the WGP: [0] = row, [1] = column. - WGP_ID 13:10 Physical WGP ID. - SA_ID 16 Shader Array ID - SE_ID 20:18 Shader Engine the wave is assigned to for gfx11 - SE_ID 19:18 Shader Engine the wave is assigned to for gfx10 - DP_RATE 31:29 Number of double-precision float units per SIMD - - HW_ID Register bit structure for GCN and CDNA - WAVE_ID 3:0 Wave buffer slot number. 0-9. - SIMD_ID 5:4 SIMD which the wave is assigned to within the CU. - PIPE_ID 7:6 Pipeline from which the wave was dispatched. - CU_ID 11:8 Compute Unit the wave is assigned to. - SH_ID 12 Shader Array (within an SE) the wave is assigned to. - SE_ID 15:13 Shader Engine the wave is assigned to for gfx908, gfx90a, gfx940-942 - 14:13 Shader Engine the wave is assigned to for Vega. - TG_ID 19:16 Thread-group ID - VM_ID 23:20 Virtual Memory ID - QUEUE_ID 26:24 Queue from which this wave was dispatched. - STATE_ID 29:27 State ID (graphics only, not compute). - ME_ID 31:30 Micro-engine ID. - - XCC_ID Register bit structure for gfx940 - XCC_ID 3:0 XCC the wave is assigned to. - */ - -#if (defined (__GFX10__) || defined (__GFX11__)) - #define HW_ID 23 -#else - #define HW_ID 4 -#endif - -#if (defined(__GFX10__) || defined(__GFX11__)) - #define HW_ID_WGP_ID_SIZE 4 - #define HW_ID_WGP_ID_OFFSET 10 -#else - #define HW_ID_CU_ID_SIZE 4 - #define HW_ID_CU_ID_OFFSET 8 -#endif - -#if (defined(__gfx908__) || defined(__gfx90a__) || \ - defined(__GFX11__)) - #define HW_ID_SE_ID_SIZE 3 -#else //4 SEs/XCC for gfx940-942 - #define HW_ID_SE_ID_SIZE 2 -#endif -#if (defined(__GFX10__) || defined(__GFX11__)) - #define HW_ID_SE_ID_OFFSET 18 - #define HW_ID_SA_ID_OFFSET 16 - #define HW_ID_SA_ID_SIZE 1 -#else - #define HW_ID_SE_ID_OFFSET 13 -#endif - -#if (defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__)) - #define XCC_ID 20 - #define XCC_ID_XCC_ID_SIZE 4 - #define XCC_ID_XCC_ID_OFFSET 0 -#endif - -#if (!defined(__HIP_NO_IMAGE_SUPPORT) && \ - (defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__))) - #define __HIP_NO_IMAGE_SUPPORT 1 -#endif - -/* - Encoding of parameter bitmask - HW_ID 5:0 HW_ID - OFFSET 10:6 Range: 0..31 - SIZE 15:11 Range: 1..32 - */ - -#define GETREG_IMMED(SZ,OFF,REG) (((SZ) << 11) | ((OFF) << 6) | (REG)) - -/* - __smid returns the wave's assigned Compute Unit and Shader Engine. - The Compute Unit, CU_ID returned in bits 3:0, and Shader Engine, SE_ID in bits 5:4. - Note: the results vary over time. - SZ minus 1 since SIZE is 1-based. -*/ -__device__ -inline -unsigned __smid(void) -{ - unsigned se_id = __builtin_amdgcn_s_getreg( - GETREG_IMMED(HW_ID_SE_ID_SIZE-1, HW_ID_SE_ID_OFFSET, HW_ID)); - #if (defined(__GFX10__) || defined(__GFX11__)) - unsigned wgp_id = __builtin_amdgcn_s_getreg( - GETREG_IMMED(HW_ID_WGP_ID_SIZE - 1, HW_ID_WGP_ID_OFFSET, HW_ID)); - unsigned sa_id = __builtin_amdgcn_s_getreg( - GETREG_IMMED(HW_ID_SA_ID_SIZE - 1, HW_ID_SA_ID_OFFSET, HW_ID)); - #else - #if (defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__)) - unsigned xcc_id = __builtin_amdgcn_s_getreg( - GETREG_IMMED(XCC_ID_XCC_ID_SIZE - 1, XCC_ID_XCC_ID_OFFSET, XCC_ID)); - #endif - unsigned cu_id = __builtin_amdgcn_s_getreg( - GETREG_IMMED(HW_ID_CU_ID_SIZE - 1, HW_ID_CU_ID_OFFSET, HW_ID)); - #endif - #if (defined(__GFX10__) || defined(__GFX11__)) - unsigned temp = se_id; - temp = (temp << HW_ID_SA_ID_SIZE) | sa_id; - temp = (temp << HW_ID_WGP_ID_SIZE) | wgp_id; - return temp; - //TODO : CU Mode impl - #elif (defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__)) - unsigned temp = xcc_id; - temp = (temp << HW_ID_SE_ID_SIZE) | se_id; - temp = (temp << HW_ID_CU_ID_SIZE) | cu_id; - return temp; - #else - return (se_id << HW_ID_CU_ID_SIZE) + cu_id; - #endif -} - -/** - * Map HIP_DYNAMIC_SHARED to "extern __shared__" for compatibility with old HIP applications - * To be removed in a future release. - */ -#define HIP_DYNAMIC_SHARED(type, var) extern __shared__ type var[]; -#define HIP_DYNAMIC_SHARED_ATTRIBUTE - -#endif //defined(__clang__) && defined(__HIP__) - - -// loop unrolling -static inline __device__ void* __hip_hc_memcpy(void* dst, const void* src, size_t size) { - auto dstPtr = static_cast(dst); - auto srcPtr = static_cast(src); - - while (size >= 4u) { - dstPtr[0] = srcPtr[0]; - dstPtr[1] = srcPtr[1]; - dstPtr[2] = srcPtr[2]; - dstPtr[3] = srcPtr[3]; - - size -= 4u; - srcPtr += 4u; - dstPtr += 4u; - } - switch (size) { - case 3: - dstPtr[2] = srcPtr[2]; - case 2: - dstPtr[1] = srcPtr[1]; - case 1: - dstPtr[0] = srcPtr[0]; - } - - return dst; -} - -static inline __device__ void* __hip_hc_memset(void* dst, unsigned char val, size_t size) { - auto dstPtr = static_cast(dst); - - while (size >= 4u) { - dstPtr[0] = val; - dstPtr[1] = val; - dstPtr[2] = val; - dstPtr[3] = val; - - size -= 4u; - dstPtr += 4u; - } - switch (size) { - case 3: - dstPtr[2] = val; - case 2: - dstPtr[1] = val; - case 1: - dstPtr[0] = val; - } - - return dst; -} -#ifndef __OPENMP_AMDGCN__ -static inline __device__ void* memcpy(void* dst, const void* src, size_t size) { - return __hip_hc_memcpy(dst, src, size); -} - -static inline __device__ void* memset(void* ptr, int val, size_t size) { - unsigned char val8 = static_cast(val); - return __hip_hc_memset(ptr, val8, size); -} -#endif // !__OPENMP_AMDGCN__ - -#endif -/* -Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_WARP_FUNCTIONS_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_WARP_FUNCTIONS_H - -__device__ static inline unsigned __hip_ds_bpermute(int index, unsigned src) { - union { int i; unsigned u; float f; } tmp; tmp.u = src; - tmp.i = __builtin_amdgcn_ds_bpermute(index, tmp.i); - return tmp.u; -} - -__device__ static inline float __hip_ds_bpermutef(int index, float src) { - union { int i; unsigned u; float f; } tmp; tmp.f = src; - tmp.i = __builtin_amdgcn_ds_bpermute(index, tmp.i); - return tmp.f; -} - -__device__ static inline unsigned __hip_ds_permute(int index, unsigned src) { - union { int i; unsigned u; float f; } tmp; tmp.u = src; - tmp.i = __builtin_amdgcn_ds_permute(index, tmp.i); - return tmp.u; -} - -__device__ static inline float __hip_ds_permutef(int index, float src) { - union { int i; unsigned u; float f; } tmp; tmp.f = src; - tmp.i = __builtin_amdgcn_ds_permute(index, tmp.i); - return tmp.f; -} - -#define __hip_ds_swizzle(src, pattern) __hip_ds_swizzle_N<(pattern)>((src)) -#define __hip_ds_swizzlef(src, pattern) __hip_ds_swizzlef_N<(pattern)>((src)) - -template -__device__ static inline unsigned __hip_ds_swizzle_N(unsigned int src) { - union { int i; unsigned u; float f; } tmp; tmp.u = src; - tmp.i = __builtin_amdgcn_ds_swizzle(tmp.i, pattern); - return tmp.u; -} - -template -__device__ static inline float __hip_ds_swizzlef_N(float src) { - union { int i; unsigned u; float f; } tmp; tmp.f = src; - tmp.i = __builtin_amdgcn_ds_swizzle(tmp.i, pattern); - return tmp.f; -} - -#define __hip_move_dpp(src, dpp_ctrl, row_mask, bank_mask, bound_ctrl) \ - __hip_move_dpp_N<(dpp_ctrl), (row_mask), (bank_mask), (bound_ctrl)>((src)) - -template -__device__ static inline int __hip_move_dpp_N(int src) { - return __builtin_amdgcn_mov_dpp(src, dpp_ctrl, row_mask, bank_mask, - bound_ctrl); -} - -static constexpr int warpSize = __AMDGCN_WAVEFRONT_SIZE; - -__device__ -inline -int __shfl(int var, int src_lane, int width = warpSize) { - int self = __lane_id(); - int index = (src_lane & (width - 1)) + (self & ~(width-1)); - return __builtin_amdgcn_ds_bpermute(index<<2, var); -} -__device__ -inline -unsigned int __shfl(unsigned int var, int src_lane, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.u = var; - tmp.i = __shfl(tmp.i, src_lane, width); - return tmp.u; -} -__device__ -inline -float __shfl(float var, int src_lane, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.f = var; - tmp.i = __shfl(tmp.i, src_lane, width); - return tmp.f; -} -__device__ -inline -double __shfl(double var, int src_lane, int width = warpSize) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - static_assert(sizeof(double) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl(tmp[0], src_lane, width); - tmp[1] = __shfl(tmp[1], src_lane, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - double tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -long __shfl(long var, int src_lane, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(long) == 2 * sizeof(int), ""); - static_assert(sizeof(long) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl(tmp[0], src_lane, width); - tmp[1] = __shfl(tmp[1], src_lane, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(long) == sizeof(int), ""); - return static_cast(__shfl(static_cast(var), src_lane, width)); - #endif -} -__device__ -inline -unsigned long __shfl(unsigned long var, int src_lane, int width = warpSize) { - #ifndef _MSC_VER - static_assert(sizeof(unsigned long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long) == sizeof(uint64_t), ""); - - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl(tmp[0], src_lane, width); - tmp[1] = __shfl(tmp[1], src_lane, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(unsigned long) == sizeof(unsigned int), ""); - return static_cast(__shfl(static_cast(var), src_lane, width)); - #endif -} -__device__ -inline -long long __shfl(long long var, int src_lane, int width = warpSize) -{ - static_assert(sizeof(long long) == 2 * sizeof(int), ""); - static_assert(sizeof(long long) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl(tmp[0], src_lane, width); - tmp[1] = __shfl(tmp[1], src_lane, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -unsigned long long __shfl(unsigned long long var, int src_lane, int width = warpSize) { - static_assert(sizeof(unsigned long long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long long) == sizeof(uint64_t), ""); - - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl(tmp[0], src_lane, width); - tmp[1] = __shfl(tmp[1], src_lane, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} - -__device__ -inline -int __shfl_up(int var, unsigned int lane_delta, int width = warpSize) { - int self = __lane_id(); - int index = self - lane_delta; - index = (index < (self & ~(width-1)))?self:index; - return __builtin_amdgcn_ds_bpermute(index<<2, var); -} -__device__ -inline -unsigned int __shfl_up(unsigned int var, unsigned int lane_delta, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.u = var; - tmp.i = __shfl_up(tmp.i, lane_delta, width); - return tmp.u; -} -__device__ -inline -float __shfl_up(float var, unsigned int lane_delta, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.f = var; - tmp.i = __shfl_up(tmp.i, lane_delta, width); - return tmp.f; -} -__device__ -inline -double __shfl_up(double var, unsigned int lane_delta, int width = warpSize) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - static_assert(sizeof(double) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_up(tmp[0], lane_delta, width); - tmp[1] = __shfl_up(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - double tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -long __shfl_up(long var, unsigned int lane_delta, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(long) == 2 * sizeof(int), ""); - static_assert(sizeof(long) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_up(tmp[0], lane_delta, width); - tmp[1] = __shfl_up(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(long) == sizeof(int), ""); - return static_cast(__shfl_up(static_cast(var), lane_delta, width)); - #endif -} - -__device__ -inline -unsigned long __shfl_up(unsigned long var, unsigned int lane_delta, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(unsigned long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long) == sizeof(uint64_t), ""); - - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_up(tmp[0], lane_delta, width); - tmp[1] = __shfl_up(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(unsigned long) == sizeof(unsigned int), ""); - return static_cast(__shfl_up(static_cast(var), lane_delta, width)); - #endif -} - -__device__ -inline -long long __shfl_up(long long var, unsigned int lane_delta, int width = warpSize) -{ - static_assert(sizeof(long long) == 2 * sizeof(int), ""); - static_assert(sizeof(long long) == sizeof(uint64_t), ""); - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_up(tmp[0], lane_delta, width); - tmp[1] = __shfl_up(tmp[1], lane_delta, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} - -__device__ -inline -unsigned long long __shfl_up(unsigned long long var, unsigned int lane_delta, int width = warpSize) -{ - static_assert(sizeof(unsigned long long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long long) == sizeof(uint64_t), ""); - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_up(tmp[0], lane_delta, width); - tmp[1] = __shfl_up(tmp[1], lane_delta, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} - -__device__ -inline -int __shfl_down(int var, unsigned int lane_delta, int width = warpSize) { - int self = __lane_id(); - int index = self + lane_delta; - index = (int)((self&(width-1))+lane_delta) >= width?self:index; - return __builtin_amdgcn_ds_bpermute(index<<2, var); -} -__device__ -inline -unsigned int __shfl_down(unsigned int var, unsigned int lane_delta, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.u = var; - tmp.i = __shfl_down(tmp.i, lane_delta, width); - return tmp.u; -} -__device__ -inline -float __shfl_down(float var, unsigned int lane_delta, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.f = var; - tmp.i = __shfl_down(tmp.i, lane_delta, width); - return tmp.f; -} -__device__ -inline -double __shfl_down(double var, unsigned int lane_delta, int width = warpSize) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - static_assert(sizeof(double) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_down(tmp[0], lane_delta, width); - tmp[1] = __shfl_down(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - double tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -long __shfl_down(long var, unsigned int lane_delta, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(long) == 2 * sizeof(int), ""); - static_assert(sizeof(long) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_down(tmp[0], lane_delta, width); - tmp[1] = __shfl_down(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(long) == sizeof(int), ""); - return static_cast(__shfl_down(static_cast(var), lane_delta, width)); - #endif -} -__device__ -inline -unsigned long __shfl_down(unsigned long var, unsigned int lane_delta, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(unsigned long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long) == sizeof(uint64_t), ""); - - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_down(tmp[0], lane_delta, width); - tmp[1] = __shfl_down(tmp[1], lane_delta, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(unsigned long) == sizeof(unsigned int), ""); - return static_cast(__shfl_down(static_cast(var), lane_delta, width)); - #endif -} -__device__ -inline -long long __shfl_down(long long var, unsigned int lane_delta, int width = warpSize) -{ - static_assert(sizeof(long long) == 2 * sizeof(int), ""); - static_assert(sizeof(long long) == sizeof(uint64_t), ""); - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_down(tmp[0], lane_delta, width); - tmp[1] = __shfl_down(tmp[1], lane_delta, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -unsigned long long __shfl_down(unsigned long long var, unsigned int lane_delta, int width = warpSize) -{ - static_assert(sizeof(unsigned long long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long long) == sizeof(uint64_t), ""); - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_down(tmp[0], lane_delta, width); - tmp[1] = __shfl_down(tmp[1], lane_delta, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} - -__device__ -inline -int __shfl_xor(int var, int lane_mask, int width = warpSize) { - int self = __lane_id(); - int index = self^lane_mask; - index = index >= ((self+width)&~(width-1))?self:index; - return __builtin_amdgcn_ds_bpermute(index<<2, var); -} -__device__ -inline -unsigned int __shfl_xor(unsigned int var, int lane_mask, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.u = var; - tmp.i = __shfl_xor(tmp.i, lane_mask, width); - return tmp.u; -} -__device__ -inline -float __shfl_xor(float var, int lane_mask, int width = warpSize) { - union { int i; unsigned u; float f; } tmp; tmp.f = var; - tmp.i = __shfl_xor(tmp.i, lane_mask, width); - return tmp.f; -} -__device__ -inline -double __shfl_xor(double var, int lane_mask, int width = warpSize) { - static_assert(sizeof(double) == 2 * sizeof(int), ""); - static_assert(sizeof(double) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_xor(tmp[0], lane_mask, width); - tmp[1] = __shfl_xor(tmp[1], lane_mask, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - double tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -long __shfl_xor(long var, int lane_mask, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(long) == 2 * sizeof(int), ""); - static_assert(sizeof(long) == sizeof(uint64_t), ""); - - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_xor(tmp[0], lane_mask, width); - tmp[1] = __shfl_xor(tmp[1], lane_mask, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(long) == sizeof(int), ""); - return static_cast(__shfl_xor(static_cast(var), lane_mask, width)); - #endif -} -__device__ -inline -unsigned long __shfl_xor(unsigned long var, int lane_mask, int width = warpSize) -{ - #ifndef _MSC_VER - static_assert(sizeof(unsigned long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long) == sizeof(uint64_t), ""); - - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_xor(tmp[0], lane_mask, width); - tmp[1] = __shfl_xor(tmp[1], lane_mask, width); - - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; - #else - static_assert(sizeof(unsigned long) == sizeof(unsigned int), ""); - return static_cast(__shfl_xor(static_cast(var), lane_mask, width)); - #endif -} -__device__ -inline -long long __shfl_xor(long long var, int lane_mask, int width = warpSize) -{ - static_assert(sizeof(long long) == 2 * sizeof(int), ""); - static_assert(sizeof(long long) == sizeof(uint64_t), ""); - int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_xor(tmp[0], lane_mask, width); - tmp[1] = __shfl_xor(tmp[1], lane_mask, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} -__device__ -inline -unsigned long long __shfl_xor(unsigned long long var, int lane_mask, int width = warpSize) -{ - static_assert(sizeof(unsigned long long) == 2 * sizeof(unsigned int), ""); - static_assert(sizeof(unsigned long long) == sizeof(uint64_t), ""); - unsigned int tmp[2]; __builtin_memcpy(tmp, &var, sizeof(tmp)); - tmp[0] = __shfl_xor(tmp[0], lane_mask, width); - tmp[1] = __shfl_xor(tmp[1], lane_mask, width); - uint64_t tmp0 = (static_cast(tmp[1]) << 32ull) | static_cast(tmp[0]); - unsigned long long tmp1; __builtin_memcpy(&tmp1, &tmp0, sizeof(tmp0)); - return tmp1; -} - -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -/** - * @file amd_detail/hip_cooperative_groups_helper.h - * - * @brief Device side implementation of cooperative group feature. - * - * Defines helper constructs and APIs which aid the types and device API - * wrappers defined within `amd_detail/hip_cooperative_groups.h`. - */ -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_HELPER_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_HELPER_H - -#if __cplusplus -#if !defined(__HIPCC_RTC__) -#include // threadId, blockId -#include -#endif -#if !defined(__align__) -#define __align__(x) __attribute__((aligned(x))) -#endif - -#if !defined(__CG_QUALIFIER__) -#define __CG_QUALIFIER__ __device__ __forceinline__ -#endif - -#if !defined(__CG_STATIC_QUALIFIER__) -#define __CG_STATIC_QUALIFIER__ __device__ static __forceinline__ -#endif - -#if !defined(_CG_STATIC_CONST_DECL_) -#define _CG_STATIC_CONST_DECL_ static constexpr -#endif - -#if __AMDGCN_WAVEFRONT_SIZE == 32 -using lane_mask = unsigned int; -#else -using lane_mask = unsigned long long int; -#endif - -namespace cooperative_groups { - -/* Global scope */ -template -using is_power_of_2 = std::integral_constant; - -template -using is_valid_wavefront = std::integral_constant; - -template -using is_valid_tile_size = - std::integral_constant::value && is_valid_wavefront::value>; - -template -using is_valid_type = - std::integral_constant::value || std::is_floating_point::value>; - -namespace internal { - -/** -* @brief Enums representing different cooperative group types -* @note This enum is only applicable on Linux. -* - */ -typedef enum { - cg_invalid, - cg_multi_grid, - cg_grid, - cg_workgroup, - cg_tiled_group, - cg_coalesced_group -} group_type; -/** - * @ingroup CooperativeG - * @{ - * This section describes the cooperative groups functions of HIP runtime API. - * - * The cooperative groups provides flexible thread parallel programming algorithms, threads - * cooperate and share data to perform collective computations. - * - * @note Cooperative groups feature is implemented on Linux, under developement - * on Windows. - * - */ -/** - * - * @brief Functionalities related to multi-grid cooperative group type - * @note The following cooperative groups functions are only applicable on Linux. - * - */ -namespace multi_grid { - -__CG_STATIC_QUALIFIER__ uint32_t num_grids() { - return static_cast(__ockl_multi_grid_num_grids()); } - -__CG_STATIC_QUALIFIER__ uint32_t grid_rank() { - return static_cast(__ockl_multi_grid_grid_rank()); } - -__CG_STATIC_QUALIFIER__ uint32_t size() { return static_cast(__ockl_multi_grid_size()); } - -__CG_STATIC_QUALIFIER__ uint32_t thread_rank() { - return static_cast(__ockl_multi_grid_thread_rank()); } - -__CG_STATIC_QUALIFIER__ bool is_valid() { return static_cast(__ockl_multi_grid_is_valid()); } - -__CG_STATIC_QUALIFIER__ void sync() { __ockl_multi_grid_sync(); } - -} // namespace multi_grid - -/** - * @brief Functionalities related to grid cooperative group type - * @note The following cooperative groups functions are only applicable on Linux. - */ -namespace grid { - -__CG_STATIC_QUALIFIER__ uint32_t size() { - return static_cast((blockDim.z * gridDim.z) * (blockDim.y * gridDim.y) * - (blockDim.x * gridDim.x)); -} - -__CG_STATIC_QUALIFIER__ uint32_t thread_rank() { - // Compute global id of the workgroup to which the current thread belongs to - uint32_t blkIdx = static_cast((blockIdx.z * gridDim.y * gridDim.x) + - (blockIdx.y * gridDim.x) + (blockIdx.x)); - - // Compute total number of threads being passed to reach current workgroup - // within grid - uint32_t num_threads_till_current_workgroup = - static_cast(blkIdx * (blockDim.x * blockDim.y * blockDim.z)); - - // Compute thread local rank within current workgroup - uint32_t local_thread_rank = static_cast((threadIdx.z * blockDim.y * blockDim.x) + - (threadIdx.y * blockDim.x) + (threadIdx.x)); - - return (num_threads_till_current_workgroup + local_thread_rank); -} - -__CG_STATIC_QUALIFIER__ bool is_valid() { return static_cast(__ockl_grid_is_valid()); } - -__CG_STATIC_QUALIFIER__ void sync() { __ockl_grid_sync(); } - -} // namespace grid - -/** - * @brief Functionalities related to `workgroup` (thread_block in CUDA terminology) - * cooperative group type - * @note The following cooperative groups functions are only applicable on Linux. - */ -namespace workgroup { - -__CG_STATIC_QUALIFIER__ dim3 group_index() { - return (dim3(static_cast(blockIdx.x), static_cast(blockIdx.y), - static_cast(blockIdx.z))); -} - -__CG_STATIC_QUALIFIER__ dim3 thread_index() { - return (dim3(static_cast(threadIdx.x), static_cast(threadIdx.y), - static_cast(threadIdx.z))); -} - -__CG_STATIC_QUALIFIER__ uint32_t size() { - return (static_cast(blockDim.x * blockDim.y * blockDim.z)); -} - -__CG_STATIC_QUALIFIER__ uint32_t thread_rank() { - return (static_cast((threadIdx.z * blockDim.y * blockDim.x) + - (threadIdx.y * blockDim.x) + (threadIdx.x))); -} - -__CG_STATIC_QUALIFIER__ bool is_valid() { - return true; -} - -__CG_STATIC_QUALIFIER__ void sync() { __syncthreads(); } - -__CG_STATIC_QUALIFIER__ dim3 block_dim() { - return (dim3(static_cast(blockDim.x), static_cast(blockDim.y), - static_cast(blockDim.z))); -} - -} // namespace workgroup - -namespace tiled_group { - -// enforce ordering for memory intructions -__CG_STATIC_QUALIFIER__ void sync() { __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "agent"); } - -} // namespace tiled_group - -namespace coalesced_group { - -// enforce ordering for memory intructions -__CG_STATIC_QUALIFIER__ void sync() { __builtin_amdgcn_fence(__ATOMIC_ACQ_REL, "agent"); } - -// Masked bit count -// -// For each thread, this function returns the number of active threads which -// have i-th bit of x set and come before the current thread. -__CG_STATIC_QUALIFIER__ unsigned int masked_bit_count(lane_mask x, unsigned int add = 0) { - unsigned int counter=0; - #if __AMDGCN_WAVEFRONT_SIZE == 32 - counter = __builtin_amdgcn_mbcnt_lo(x, add); - #else - counter = __builtin_amdgcn_mbcnt_lo(static_cast(x), add); - counter = __builtin_amdgcn_mbcnt_hi(static_cast(x >> 32), counter); - #endif - - return counter; -} - -} // namespace coalesced_group - - -} // namespace internal - -} // namespace cooperative_groups -/** -* @} -*/ - -#endif // __cplusplus -#endif // HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_HELPER_H -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -/** - * @file amd_detail/hip_cooperative_groups.h - * - * @brief Device side implementation of `Cooperative Group` feature. - * - * Defines new types and device API wrappers related to `Cooperative Group` - * feature, which the programmer can directly use in his kernel(s) in order to - * make use of this feature. - */ -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_H - -#if __cplusplus -#if !defined(__HIPCC_RTC__) -#include -#endif - -#define __hip_abort() \ - { abort(); } -#if defined(NDEBUG) -#define __hip_assert(COND) -#else -#define __hip_assert(COND) \ - { \ - if (!COND) { \ - __hip_abort(); \ - } \ - } -#endif - -namespace cooperative_groups { - -/** @brief The base type of all cooperative group types - * - * \details Holds the key properties of a constructed cooperative group types - * object, like the group type, its size, etc - * - * @note Cooperative groups feature is implemented on Linux, under developement - * on Windows. - */ -class thread_group { - protected: - uint32_t _type; // thread_group type - uint32_t _size; // total number of threads in the tread_group - uint64_t _mask; // Lanemask for coalesced and tiled partitioned group types, - // LSB represents lane 0, and MSB represents lane 63 - - // Construct a thread group, and set thread group type and other essential - // thread group properties. This generic thread group is directly constructed - // only when the group is supposed to contain only the calling the thread - // (throurh the API - `this_thread()`), and in all other cases, this thread - // group object is a sub-object of some other derived thread group object - __CG_QUALIFIER__ thread_group(internal::group_type type, uint32_t size = static_cast(0), - uint64_t mask = static_cast(0)) { - _type = type; - _size = size; - _mask = mask; - } - - struct _tiled_info { - bool is_tiled; - unsigned int size; - unsigned int meta_group_rank; - unsigned int meta_group_size; - }; - - struct _coalesced_info { - lane_mask member_mask; - unsigned int size; - struct _tiled_info tiled_info; - } coalesced_info; - - friend __CG_QUALIFIER__ thread_group tiled_partition(const thread_group& parent, - unsigned int tile_size); - friend class thread_block; - - public: - // Total number of threads in the thread group, and this serves the purpose - // for all derived cooperative group types since their `size` is directly - // saved during the construction - __CG_QUALIFIER__ uint32_t size() const { return _size; } - __CG_QUALIFIER__ unsigned int cg_type() const { return _type; } - // Rank of the calling thread within [0, size()) - __CG_QUALIFIER__ uint32_t thread_rank() const; - // Is this cooperative group type valid? - __CG_QUALIFIER__ bool is_valid() const; - // synchronize the threads in the thread group - __CG_QUALIFIER__ void sync() const; -}; -/** - *------------------------------------------------------------------------------------------------- - *------------------------------------------------------------------------------------------------- - * @defgroup CooperativeG Cooperative Groups - * @ingroup API - * @{ - * This section describes the cooperative groups functions of HIP runtime API. - * - * The cooperative groups provides flexible thread parallel programming algorithms, threads - * cooperate and share data to perform collective computations. - * - * @note Cooperative groups feature is implemented on Linux, under developement - * on Windows. - * - */ -/** \brief The multi-grid cooperative group type - * - * \details Represents an inter-device cooperative group type where the - * participating threads within the group spans across multple - * devices, running the (same) kernel on these devices - * @note The multi-grid cooperative group type is implemented on Linux, under developement - * on Windows. - */ -class multi_grid_group : public thread_group { - // Only these friend functions are allowed to construct an object of this class - // and access its resources - friend __CG_QUALIFIER__ multi_grid_group this_multi_grid(); - - protected: - // Construct mutli-grid thread group (through the API this_multi_grid()) - explicit __CG_QUALIFIER__ multi_grid_group(uint32_t size) - : thread_group(internal::cg_multi_grid, size) {} - - public: - // Number of invocations participating in this multi-grid group. In other - // words, the number of GPUs - __CG_QUALIFIER__ uint32_t num_grids() { return internal::multi_grid::num_grids(); } - // Rank of this invocation. In other words, an ID number within the range - // [0, num_grids()) of the GPU, this kernel is running on - __CG_QUALIFIER__ uint32_t grid_rank() { return internal::multi_grid::grid_rank(); } - __CG_QUALIFIER__ uint32_t thread_rank() const { return internal::multi_grid::thread_rank(); } - __CG_QUALIFIER__ bool is_valid() const { return internal::multi_grid::is_valid(); } - __CG_QUALIFIER__ void sync() const { internal::multi_grid::sync(); } -}; - -/** @brief User exposed API interface to construct multi-grid cooperative - * group type object - `multi_grid_group` - * - * \details User is not allowed to directly construct an object of type - * `multi_grid_group`. Instead, he should construct it through this - * API function - * @note This multi-grid cooperative API type is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ multi_grid_group this_multi_grid() { - return multi_grid_group(internal::multi_grid::size()); -} - -/** @brief The grid cooperative group type - * - * \details Represents an inter-workgroup cooperative group type where the - * participating threads within the group spans across multiple - * workgroups running the (same) kernel on the same device - * @note This is implemented on Linux, under developement - * on Windows. - */ -class grid_group : public thread_group { - // Only these friend functions are allowed to construct an object of this class - // and access its resources - friend __CG_QUALIFIER__ grid_group this_grid(); - - protected: - // Construct grid thread group (through the API this_grid()) - explicit __CG_QUALIFIER__ grid_group(uint32_t size) : thread_group(internal::cg_grid, size) {} - - public: - __CG_QUALIFIER__ uint32_t thread_rank() const { return internal::grid::thread_rank(); } - __CG_QUALIFIER__ bool is_valid() const { return internal::grid::is_valid(); } - __CG_QUALIFIER__ void sync() const { internal::grid::sync(); } -}; - -/** @brief User exposed API interface to construct grid cooperative group type - * object - `grid_group` - * - * \details User is not allowed to directly construct an object of type - * `multi_grid_group`. Instead, he should construct it through this - * API function - * @note This function is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ grid_group this_grid() { return grid_group(internal::grid::size()); } - -/** @brief The workgroup (thread-block in CUDA terminology) cooperative group - * type - * - * \details Represents an intra-workgroup cooperative group type where the - * participating threads within the group are exactly the same threads - * which are participated in the currently executing `workgroup` - * @note This is implemented on Linux, under developement - * on Windows. - */ -class thread_block : public thread_group { - // Only these friend functions are allowed to construct an object of thi - // class and access its resources - friend __CG_QUALIFIER__ thread_block this_thread_block(); - friend __CG_QUALIFIER__ thread_group tiled_partition(const thread_group& parent, - unsigned int tile_size); - friend __CG_QUALIFIER__ thread_group tiled_partition(const thread_block& parent, - unsigned int tile_size); - protected: - // Construct a workgroup thread group (through the API this_thread_block()) - explicit __CG_QUALIFIER__ thread_block(uint32_t size) - : thread_group(internal::cg_workgroup, size) {} - - __CG_QUALIFIER__ thread_group new_tiled_group(unsigned int tile_size) const { - const bool pow2 = ((tile_size & (tile_size - 1)) == 0); - // Invalid tile size, assert - if (!tile_size || (tile_size > __AMDGCN_WAVEFRONT_SIZE) || !pow2) { - __hip_assert(false && "invalid tile size") - } - - thread_group tiledGroup = thread_group(internal::cg_tiled_group, tile_size); - tiledGroup.coalesced_info.tiled_info.size = tile_size; - tiledGroup.coalesced_info.tiled_info.is_tiled = true; - tiledGroup.coalesced_info.tiled_info.meta_group_rank = thread_rank() / tile_size; - tiledGroup.coalesced_info.tiled_info.meta_group_size = (size() + tile_size - 1) / tile_size; - return tiledGroup; - } - - public: - // 3-dimensional block index within the grid - __CG_STATIC_QUALIFIER__ dim3 group_index() { return internal::workgroup::group_index(); } - // 3-dimensional thread index within the block - __CG_STATIC_QUALIFIER__ dim3 thread_index() { return internal::workgroup::thread_index(); } - __CG_STATIC_QUALIFIER__ uint32_t thread_rank() { return internal::workgroup::thread_rank(); } - __CG_STATIC_QUALIFIER__ uint32_t size() { return internal::workgroup::size(); } - __CG_STATIC_QUALIFIER__ bool is_valid() { return internal::workgroup::is_valid(); } - __CG_STATIC_QUALIFIER__ void sync() { internal::workgroup::sync(); } - __CG_QUALIFIER__ dim3 group_dim() { return internal::workgroup::block_dim(); } -}; - -/** \brief User exposed API interface to construct workgroup cooperative - * group type object - `thread_block`. - * - * \details User is not allowed to directly construct an object of type - * `thread_block`. Instead, he should construct it through this API - * function. - * @note This function is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ thread_block this_thread_block() { - return thread_block(internal::workgroup::size()); -} - -/** \brief The tiled_group cooperative group type - * - * \details Represents one tiled thread group in a wavefront. - * This group type also supports sub-wave level intrinsics. - * @note This is implemented on Linux, under developement - * on Windows. - */ - -class tiled_group : public thread_group { - private: - friend __CG_QUALIFIER__ thread_group tiled_partition(const thread_group& parent, - unsigned int tile_size); - friend __CG_QUALIFIER__ tiled_group tiled_partition(const tiled_group& parent, - unsigned int tile_size); - - __CG_QUALIFIER__ tiled_group new_tiled_group(unsigned int tile_size) const { - const bool pow2 = ((tile_size & (tile_size - 1)) == 0); - - if (!tile_size || (tile_size > __AMDGCN_WAVEFRONT_SIZE) || !pow2) { - __hip_assert(false && "invalid tile size") - } - - if (size() <= tile_size) { - return *this; - } - - tiled_group tiledGroup = tiled_group(tile_size); - tiledGroup.coalesced_info.tiled_info.is_tiled = true; - return tiledGroup; - } - - protected: - explicit __CG_QUALIFIER__ tiled_group(unsigned int tileSize) - : thread_group(internal::cg_tiled_group, tileSize) { - coalesced_info.tiled_info.size = tileSize; - coalesced_info.tiled_info.is_tiled = true; - } - - public: - __CG_QUALIFIER__ unsigned int size() const { return (coalesced_info.tiled_info.size); } - - __CG_QUALIFIER__ unsigned int thread_rank() const { - return (internal::workgroup::thread_rank() & (coalesced_info.tiled_info.size - 1)); - } - - __CG_QUALIFIER__ void sync() const { - internal::tiled_group::sync(); - } -}; - -/** \brief The coalesced_group cooperative group type - * - * \details Represents a active thread group in a wavefront. - * This group type also supports sub-wave level intrinsics. - * @note This is implemented on Linux, under developement - * on Windows. - */ -class coalesced_group : public thread_group { - private: - friend __CG_QUALIFIER__ coalesced_group coalesced_threads(); - friend __CG_QUALIFIER__ thread_group tiled_partition(const thread_group& parent, unsigned int tile_size); - friend __CG_QUALIFIER__ coalesced_group tiled_partition(const coalesced_group& parent, unsigned int tile_size); - - __CG_QUALIFIER__ coalesced_group new_tiled_group(unsigned int tile_size) const { - const bool pow2 = ((tile_size & (tile_size - 1)) == 0); - - if (!tile_size || (tile_size > size()) || !pow2) { - return coalesced_group(0); - } - - // If a tiled group is passed to be partitioned further into a coalesced_group. - // prepare a mask for further partitioning it so that it stays coalesced. - if (coalesced_info.tiled_info.is_tiled) { - unsigned int base_offset = (thread_rank() & (~(tile_size - 1))); - unsigned int masklength = min(static_cast(size()) - base_offset, tile_size); - lane_mask member_mask = static_cast(-1) >> (__AMDGCN_WAVEFRONT_SIZE - masklength); - - member_mask <<= (__lane_id() & ~(tile_size - 1)); - coalesced_group coalesced_tile = coalesced_group(member_mask); - coalesced_tile.coalesced_info.tiled_info.is_tiled = true; - coalesced_tile.coalesced_info.tiled_info.meta_group_rank = thread_rank() / tile_size; - coalesced_tile.coalesced_info.tiled_info.meta_group_size = size() / tile_size; - return coalesced_tile; - } - // Here the parent coalesced_group is not partitioned. - else { - lane_mask member_mask = 0; - unsigned int tile_rank = 0; - int lanes_to_skip = ((thread_rank()) / tile_size) * tile_size; - - for (unsigned int i = 0; i < __AMDGCN_WAVEFRONT_SIZE; i++) { - lane_mask active = coalesced_info.member_mask & (1 << i); - // Make sure the lane is active - if (active) { - if (lanes_to_skip <= 0 && tile_rank < tile_size) { - // Prepare a member_mask that is appropriate for a tile - member_mask |= active; - tile_rank++; - } - lanes_to_skip--; - } - } - coalesced_group coalesced_tile = coalesced_group(member_mask); - coalesced_tile.coalesced_info.tiled_info.meta_group_rank = thread_rank() / tile_size; - coalesced_tile.coalesced_info.tiled_info.meta_group_size = - (size() + tile_size - 1) / tile_size; - return coalesced_tile; - } - return coalesced_group(0); - } - - protected: - // Constructor - explicit __CG_QUALIFIER__ coalesced_group(lane_mask member_mask) - : thread_group(internal::cg_coalesced_group) { - coalesced_info.member_mask = member_mask; // Which threads are active - coalesced_info.size = __popcll(coalesced_info.member_mask); // How many threads are active - coalesced_info.tiled_info.is_tiled = false; // Not a partitioned group - coalesced_info.tiled_info.meta_group_rank = 0; - coalesced_info.tiled_info.meta_group_size = 1; - } - - public: - __CG_QUALIFIER__ unsigned int size() const { - return coalesced_info.size; - } - - __CG_QUALIFIER__ unsigned int thread_rank() const { - return internal::coalesced_group::masked_bit_count(coalesced_info.member_mask); - } - - __CG_QUALIFIER__ void sync() const { - internal::coalesced_group::sync(); - } - - __CG_QUALIFIER__ unsigned int meta_group_rank() const { - return coalesced_info.tiled_info.meta_group_rank; - } - - __CG_QUALIFIER__ unsigned int meta_group_size() const { - return coalesced_info.tiled_info.meta_group_size; - } - - template - __CG_QUALIFIER__ T shfl(T var, int srcRank) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - - srcRank = srcRank % static_cast(size()); - - int lane = (size() == __AMDGCN_WAVEFRONT_SIZE) ? srcRank - : (__AMDGCN_WAVEFRONT_SIZE == 64) ? __fns64(coalesced_info.member_mask, 0, (srcRank + 1)) - : __fns32(coalesced_info.member_mask, 0, (srcRank + 1)); - - return __shfl(var, lane, __AMDGCN_WAVEFRONT_SIZE); - } - - template - __CG_QUALIFIER__ T shfl_down(T var, unsigned int lane_delta) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - - // Note: The cuda implementation appears to use the remainder of lane_delta - // and WARP_SIZE as the shift value rather than lane_delta itself. - // This is not described in the documentation and is not done here. - - if (size() == __AMDGCN_WAVEFRONT_SIZE) { - return __shfl_down(var, lane_delta, __AMDGCN_WAVEFRONT_SIZE); - } - - int lane; - if (__AMDGCN_WAVEFRONT_SIZE == 64) { - lane = __fns64(coalesced_info.member_mask, __lane_id(), lane_delta + 1); - } - else { - lane = __fns32(coalesced_info.member_mask, __lane_id(), lane_delta + 1); - } - - if (lane == -1) { - lane = __lane_id(); - } - - return __shfl(var, lane, __AMDGCN_WAVEFRONT_SIZE); - } - - template - __CG_QUALIFIER__ T shfl_up(T var, unsigned int lane_delta) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - - // Note: The cuda implementation appears to use the remainder of lane_delta - // and WARP_SIZE as the shift value rather than lane_delta itself. - // This is not described in the documentation and is not done here. - - if (size() == __AMDGCN_WAVEFRONT_SIZE) { - return __shfl_up(var, lane_delta, __AMDGCN_WAVEFRONT_SIZE); - } - - int lane; - if (__AMDGCN_WAVEFRONT_SIZE == 64) { - lane = __fns64(coalesced_info.member_mask, __lane_id(), -(lane_delta + 1)); - } - else if (__AMDGCN_WAVEFRONT_SIZE == 32) { - lane = __fns32(coalesced_info.member_mask, __lane_id(), -(lane_delta + 1)); - } - - if (lane == -1) { - lane = __lane_id(); - } - - return __shfl(var, lane, __AMDGCN_WAVEFRONT_SIZE); - } -}; - -/** \brief User exposed API to create coalesced groups. - * - * \details A collective operation that groups all active lanes into a new thread group. - * @note This function is implemented on Linux, under developement - * on Windows. - */ - -__CG_QUALIFIER__ coalesced_group coalesced_threads() { - return cooperative_groups::coalesced_group(__builtin_amdgcn_read_exec()); -} - -/** - * Implemenation of all publicly exposed base class APIs - * @note This function is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ uint32_t thread_group::thread_rank() const { - switch (this->_type) { - case internal::cg_multi_grid: { - return (static_cast(this)->thread_rank()); - } - case internal::cg_grid: { - return (static_cast(this)->thread_rank()); - } - case internal::cg_workgroup: { - return (static_cast(this)->thread_rank()); - } - case internal::cg_tiled_group: { - return (static_cast(this)->thread_rank()); - } - case internal::cg_coalesced_group: { - return (static_cast(this)->thread_rank()); - } - default: { - __hip_assert(false && "invalid cooperative group type") - return -1; - } - } -} -/** - * Implemenation of all publicly exposed thread group API - * @note This function is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ bool thread_group::is_valid() const { - switch (this->_type) { - case internal::cg_multi_grid: { - return (static_cast(this)->is_valid()); - } - case internal::cg_grid: { - return (static_cast(this)->is_valid()); - } - case internal::cg_workgroup: { - return (static_cast(this)->is_valid()); - } - case internal::cg_tiled_group: { - return (static_cast(this)->is_valid()); - } - case internal::cg_coalesced_group: { - return (static_cast(this)->is_valid()); - } - default: { - __hip_assert(false && "invalid cooperative group type") - return false; - } - } -} -/** - * Implemenation of all publicly exposed thread group sync API - * @note This function is implemented on Linux, under developement - * on Windows. - */ -__CG_QUALIFIER__ void thread_group::sync() const { - switch (this->_type) { - case internal::cg_multi_grid: { - static_cast(this)->sync(); - break; - } - case internal::cg_grid: { - static_cast(this)->sync(); - break; - } - case internal::cg_workgroup: { - static_cast(this)->sync(); - break; - } - case internal::cg_tiled_group: { - static_cast(this)->sync(); - break; - } - case internal::cg_coalesced_group: { - static_cast(this)->sync(); - break; - } - default: { - __hip_assert(false && "invalid cooperative group type") - } - } -} - -/** - * Implemenation of publicly exposed `wrapper` API on top of basic cooperative - * group type APIs - * @note This function is implemented on Linux, under developement - * on Windows. - */ -template __CG_QUALIFIER__ uint32_t group_size(CGTy const& g) { return g.size(); } -/** - * Implemenation of publicly exposed `wrapper` API on top of basic cooperative - * group type APIs - * @note This function is implemented on Linux, under developement - * on Windows. - */ -template __CG_QUALIFIER__ uint32_t thread_rank(CGTy const& g) { - return g.thread_rank(); -} -/** - * Implemenation of publicly exposed `wrapper` API on top of basic cooperative - * group type APIs - * @note This function is implemented on Linux, under developement - * on Windows. - */ -template __CG_QUALIFIER__ bool is_valid(CGTy const& g) { return g.is_valid(); } -/** - * Implemenation of publicly exposed `wrapper` API on top of basic cooperative - * group type APIs - * @note This function is implemented on Linux, under developement - * on Windows. - */ -template __CG_QUALIFIER__ void sync(CGTy const& g) { g.sync(); } -/** - * template class tile_base - * @note This class is implemented on Linux, under developement - * on Windows. - */ -template class tile_base { - protected: - _CG_STATIC_CONST_DECL_ unsigned int numThreads = tileSize; - - public: - // Rank of the thread within this tile - _CG_STATIC_CONST_DECL_ unsigned int thread_rank() { - return (internal::workgroup::thread_rank() & (numThreads - 1)); - } - - // Number of threads within this tile - __CG_STATIC_QUALIFIER__ unsigned int size() { return numThreads; } -}; -/** - * template class thread_block_tile_base - * @note This class is implemented on Linux, under developement - * on Windows. - */ -template class thread_block_tile_base : public tile_base { - static_assert(is_valid_tile_size::value, - "Tile size is either not a power of 2 or greater than the wavefront size"); - using tile_base::numThreads; - - public: - __CG_STATIC_QUALIFIER__ void sync() { - internal::tiled_group::sync(); - } - - template __CG_QUALIFIER__ T shfl(T var, int srcRank) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - return (__shfl(var, srcRank, numThreads)); - } - - template __CG_QUALIFIER__ T shfl_down(T var, unsigned int lane_delta) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - return (__shfl_down(var, lane_delta, numThreads)); - } - - template __CG_QUALIFIER__ T shfl_up(T var, unsigned int lane_delta) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - return (__shfl_up(var, lane_delta, numThreads)); - } - - template __CG_QUALIFIER__ T shfl_xor(T var, unsigned int laneMask) const { - static_assert(is_valid_type::value, "Neither an integer or float type."); - return (__shfl_xor(var, laneMask, numThreads)); - } -}; -/** \brief User exposed API that captures the state of the parent group pre-partition - */ -template -class parent_group_info { -public: - // Returns the linear rank of the group within the set of tiles partitioned - // from a parent group (bounded by meta_group_size) - __CG_STATIC_QUALIFIER__ unsigned int meta_group_rank() { - return ParentCGTy::thread_rank() / tileSize; - } - - // Returns the number of groups created when the parent group was partitioned. - __CG_STATIC_QUALIFIER__ unsigned int meta_group_size() { - return (ParentCGTy::size() + tileSize - 1) / tileSize; - } -}; - -/** \brief Group type - thread_block_tile - * - * \details Represents one tile of thread group. - * @note This type is implemented on Linux, under developement - * on Windows. - */ -template -class thread_block_tile_type : public thread_block_tile_base, - public tiled_group, - public parent_group_info { - _CG_STATIC_CONST_DECL_ unsigned int numThreads = tileSize; - protected: - __CG_QUALIFIER__ thread_block_tile_type() : tiled_group(numThreads) { - coalesced_info.tiled_info.size = numThreads; - coalesced_info.tiled_info.is_tiled = true; - } -}; - -// Partial template specialization -template -class thread_block_tile_type : public thread_block_tile_base, - public tiled_group - { - _CG_STATIC_CONST_DECL_ unsigned int numThreads = tileSize; - - typedef thread_block_tile_base tbtBase; - - protected: - - __CG_QUALIFIER__ thread_block_tile_type(unsigned int meta_group_rank, unsigned int meta_group_size) - : tiled_group(numThreads) { - coalesced_info.tiled_info.size = numThreads; - coalesced_info.tiled_info.is_tiled = true; - coalesced_info.tiled_info.meta_group_rank = meta_group_rank; - coalesced_info.tiled_info.meta_group_size = meta_group_size; - } - - public: - using tbtBase::size; - using tbtBase::sync; - using tbtBase::thread_rank; - - __CG_QUALIFIER__ unsigned int meta_group_rank() const { - return coalesced_info.tiled_info.meta_group_rank; - } - - __CG_QUALIFIER__ unsigned int meta_group_size() const { - return coalesced_info.tiled_info.meta_group_size; - } -// end of operative group -/** -* @} -*/ -}; - - -/** \brief User exposed API to partition groups. - * - * \details A collective operation that partitions the parent group into a one-dimensional, - * row-major, tiling of subgroups. - */ - -__CG_QUALIFIER__ thread_group tiled_partition(const thread_group& parent, unsigned int tile_size) { - if (parent.cg_type() == internal::cg_tiled_group) { - const tiled_group* cg = static_cast(&parent); - return cg->new_tiled_group(tile_size); - } - else if(parent.cg_type() == internal::cg_coalesced_group) { - const coalesced_group* cg = static_cast(&parent); - return cg->new_tiled_group(tile_size); - } - else { - const thread_block* tb = static_cast(&parent); - return tb->new_tiled_group(tile_size); - } -} - -// Thread block type overload -__CG_QUALIFIER__ thread_group tiled_partition(const thread_block& parent, unsigned int tile_size) { - return (parent.new_tiled_group(tile_size)); -} - -__CG_QUALIFIER__ tiled_group tiled_partition(const tiled_group& parent, unsigned int tile_size) { - return (parent.new_tiled_group(tile_size)); -} - -// If a coalesced group is passed to be partitioned, it should remain coalesced -__CG_QUALIFIER__ coalesced_group tiled_partition(const coalesced_group& parent, unsigned int tile_size) { - return (parent.new_tiled_group(tile_size)); -} - -template class thread_block_tile; - -namespace impl { -template class thread_block_tile_internal; - -template -class thread_block_tile_internal : public thread_block_tile_type { - protected: - template - __CG_QUALIFIER__ thread_block_tile_internal( - const thread_block_tile_internal& g) - : thread_block_tile_type(g.meta_group_rank(), g.meta_group_size()) {} - - __CG_QUALIFIER__ thread_block_tile_internal(const thread_block& g) - : thread_block_tile_type() {} -}; -} // namespace impl - -template -class thread_block_tile : public impl::thread_block_tile_internal { - protected: - __CG_QUALIFIER__ thread_block_tile(const ParentCGTy& g) - : impl::thread_block_tile_internal(g) {} - - public: - __CG_QUALIFIER__ operator thread_block_tile() const { - return thread_block_tile(*this); - } -}; - - -template -class thread_block_tile : public impl::thread_block_tile_internal { - template friend class thread_block_tile; - - protected: - public: - template - __CG_QUALIFIER__ thread_block_tile(const thread_block_tile& g) - : impl::thread_block_tile_internal(g) {} -}; - -template class thread_block_tile; - -namespace impl { -template struct tiled_partition_internal; - -template -struct tiled_partition_internal : public thread_block_tile { - __CG_QUALIFIER__ tiled_partition_internal(const thread_block& g) - : thread_block_tile(g) {} -}; - -} // namespace impl - -/** \brief User exposed API to partition groups. - * - * \details This constructs a templated class derieved from thread_group. - * The template defines tile size of the new thread group at compile time. - */ -template -__CG_QUALIFIER__ thread_block_tile tiled_partition(const ParentCGTy& g) { - static_assert(is_valid_tile_size::value, - "Tiled partition with size > wavefront size. Currently not supported "); - return impl::tiled_partition_internal(g); -} -} // namespace cooperative_groups - -#endif // __cplusplus -#endif // HIP_INCLUDE_HIP_AMD_DETAIL_HIP_COOPERATIVE_GROUPS_H -/* -Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#ifdef __cplusplus - -/** - * @brief Unsafe floating point rmw atomic add. - * - * Performs a relaxed read-modify-write floating point atomic add with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated to have the original value plus \p value - * - * @note This operation currently only performs different operations for - * the gfx90a target. Other devices continue to use safe atomics. - * - * It can be used to generate code that uses fast hardware floating point atomic - * operations which may handle rounding and subnormal values differently than - * non-atomic floating point operations. - * - * The operation is not always safe and can have undefined behavior unless - * following condition are met: - * - * - \p addr is at least 4 bytes aligned - * - If \p addr is a global segment address, it is in a coarse grain allocation. - * Passing in global segment addresses in fine grain allocations will result in - * undefined behavior and is not supported. - * - * @param [in,out] addr Pointer to value to be increment by \p value. - * @param [in] value Value by \p addr is to be incremented. - * @return Original value contained in \p addr. - */ -__device__ inline float unsafeAtomicAdd(float* addr, float value) { -#if defined(__gfx90a__) && \ - __has_builtin(__builtin_amdgcn_is_shared) && \ - __has_builtin(__builtin_amdgcn_is_private) && \ - __has_builtin(__builtin_amdgcn_ds_atomic_fadd_f32) && \ - __has_builtin(__builtin_amdgcn_global_atomic_fadd_f32) - if (__builtin_amdgcn_is_shared( - (const __attribute__((address_space(0))) void*)addr)) - return __builtin_amdgcn_ds_atomic_fadd_f32(addr, value); - else if (__builtin_amdgcn_is_private( - (const __attribute__((address_space(0))) void*)addr)) { - float temp = *addr; - *addr = temp + value; - return temp; - } - else - return __builtin_amdgcn_global_atomic_fadd_f32(addr, value); -#elif __has_builtin(__hip_atomic_fetch_add) - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else - return __atomic_fetch_add(addr, value, __ATOMIC_RELAXED); -#endif -} - -/** - * @brief Unsafe floating point rmw atomic max. - * - * Performs a relaxed read-modify-write floating point atomic max with - * device memory scope. The original value at \p addr is returned and - * the value at \p addr is replaced by \p val if greater. - * - * @note This operation is currently identical to that performed by - * atomicMax and is included for completeness. - * - * @param [in,out] addr Pointer to value to be updated - * @param [in] val Value used to update the value at \p addr. - * @return Original value contained in \p addr. - */ -__device__ inline float unsafeAtomicMax(float* addr, float val) { - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -} - -/** - * @brief Unsafe floating point rmw atomic min. - * - * Performs a relaxed read-modify-write floating point atomic min with - * device memory scope. The original value at \p addr is returned and - * the value at \p addr is replaced by \p val if lesser. - * - * @note This operation is currently identical to that performed by - * atomicMin and is included for completeness. - * - * @param [in,out] addr Pointer to value to be updated - * @param [in] val Value used to update the value at \p addr. - * @return Original value contained in \p addr. - */ -__device__ inline float unsafeAtomicMin(float* addr, float val) { - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -} - -/** - * @brief Unsafe double precision rmw atomic add. - * - * Performs a relaxed read-modify-write double precision atomic add with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated to have the original value plus \p value - * - * @note This operation currently only performs different operations for - * the gfx90a target. Other devices continue to use safe atomics. - * - * It can be used to generate code that uses fast hardware floating point atomic - * operations which may handle rounding and subnormal values differently than - * non-atomic floating point operations. - * - * The operation is not always safe and can have undefined behavior unless - * following condition are met: - * - * - \p addr is at least 8 byte aligned - * - If \p addr is a global segment address, it is in a coarse grain allocation. - * Passing in global segment addresses in fine grain allocations will result in - * undefined behavior and are not supported. - * - * @param [in,out] addr Pointer to value to be updated. - * @param [in] value Value by \p addr is to be incremented. - * @return Original value contained in \p addr. - */ -__device__ inline double unsafeAtomicAdd(double* addr, double value) { -#if defined(__gfx90a__) && __has_builtin(__builtin_amdgcn_flat_atomic_fadd_f64) - return __builtin_amdgcn_flat_atomic_fadd_f64(addr, value); -#elif defined (__hip_atomic_fetch_add) - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else - return __atomic_fetch_add(addr, value, __ATOMIC_RELAXED); -#endif -} - -/** - * @brief Unsafe double precision rmw atomic max. - * - * Performs a relaxed read-modify-write double precision atomic max with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated with \p val if greater. - * - * @note This operation currently only performs different operations for - * the gfx90a target. Other devices continue to use safe atomics. - * - * It can be used to generate code that uses fast hardware floating point atomic - * operations which may handle rounding and subnormal values differently than - * non-atomic floating point operations. - * - * The operation is not always safe and can have undefined behavior unless - * following condition are met: - * - * - \p addr is at least 8 byte aligned - * - If \p addr is a global segment address, it is in a coarse grain allocation. - * Passing in global segment addresses in fine grain allocations will result in - * undefined behavior and are not supported. - * - * @param [in,out] addr Pointer to value to be updated. - * @param [in] val Value used to updated the contents at \p addr - * @return Original value contained at \p addr. - */ -__device__ inline double unsafeAtomicMax(double* addr, double val) { -#if (defined(__gfx90a__) || defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__)) && \ - __has_builtin(__builtin_amdgcn_flat_atomic_fmax_f64) - return __builtin_amdgcn_flat_atomic_fmax_f64(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif -#endif -} - -/** - * @brief Unsafe double precision rmw atomic min. - * - * Performs a relaxed read-modify-write double precision atomic min with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated with \p val if lesser. - * - * @note This operation currently only performs different operations for - * the gfx90a target. Other devices continue to use safe atomics. - * - * It can be used to generate code that uses fast hardware floating point atomic - * operations which may handle rounding and subnormal values differently than - * non-atomic floating point operations. - * - * The operation is not always safe and can have undefined behavior unless - * following condition are met: - * - * - \p addr is at least 8 byte aligned - * - If \p addr is a global segment address, it is in a coarse grain allocation. - * Passing in global segment addresses in fine grain allocations will result in - * undefined behavior and are not supported. - * - * @param [in,out] addr Pointer to value to be updated. - * @param [in] val Value used to updated the contents at \p addr - * @return Original value contained at \p addr. - */ -__device__ inline double unsafeAtomicMin(double* addr, double val) { -#if (defined(__gfx90a__) || defined(__gfx940__) || defined(__gfx941__) || defined(__gfx942__)) && \ - __has_builtin(__builtin_amdgcn_flat_atomic_fmin_f64) - return __builtin_amdgcn_flat_atomic_fmin_f64(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif -#endif -} - -/** - * @brief Safe floating point rmw atomic add. - * - * Performs a relaxed read-modify-write floating point atomic add with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated to have the original value plus \p value - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be increment by \p value. - * @param [in] value Value by \p addr is to be incremented. - * @return Original value contained in \p addr. - */ -__device__ inline float safeAtomicAdd(float* addr, float value) { -#if defined(__gfx908__) || defined(__gfx941__) \ - || ((defined(__gfx90a__) || defined(__gfx940__) || defined(__gfx942__)) \ - && !__has_builtin(__hip_atomic_fetch_add)) - // On gfx908, we can generate unsafe FP32 atomic add that does not follow all - // IEEE rules when -munsafe-fp-atomics is passed. Do a CAS loop emulation instead. - // On gfx941, we can generate unsafe FP32 atomic add that may not always happen atomically, - // so we need to force a CAS loop emulation to ensure safety. - // On gfx90a, gfx940 and gfx942 if we do not have the __hip_atomic_fetch_add builtin, we - // need to force a CAS loop here. - float old_val; -#if __has_builtin(__hip_atomic_load) - old_val = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else // !__has_builtin(__hip_atomic_load) - old_val = __uint_as_float(__atomic_load_n(reinterpret_cast(addr), __ATOMIC_RELAXED)); -#endif // __has_builtin(__hip_atomic_load) - float expected, temp; - do { - temp = expected = old_val; -#if __has_builtin(__hip_atomic_compare_exchange_strong) - __hip_atomic_compare_exchange_strong(addr, &expected, old_val + value, __ATOMIC_RELAXED, - __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else // !__has_builtin(__hip_atomic_compare_exchange_strong) - __atomic_compare_exchange_n(addr, &expected, old_val + value, false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); -#endif // __has_builtin(__hip_atomic_compare_exchange_strong) - old_val = expected; - } while (__float_as_uint(temp) != __float_as_uint(old_val)); - return old_val; -#elif defined(__gfx90a__) - // On gfx90a, with the __hip_atomic_fetch_add builtin, relaxed system-scope - // atomics will produce safe CAS loops, but are otherwise not different than - // agent-scope atomics. This logic is only applicable for gfx90a, and should - // not be assumed on other architectures. - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#elif __has_builtin(__hip_atomic_fetch_add) - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else - return __atomic_fetch_add(addr, value, __ATOMIC_RELAXED); -#endif -} - -/** - * @brief Safe floating point rmw atomic max. - * - * Performs a relaxed read-modify-write floating point atomic max with - * device memory scope. The original value at \p addr is returned and - * the value at \p addr is replaced by \p val if greater. - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be updated - * @param [in] val Value used to update the value at \p addr. - * @return Original value contained in \p addr. - */ -__device__ inline float safeAtomicMax(float* addr, float val) { - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -} - -/** - * @brief Safe floating point rmw atomic min. - * - * Performs a relaxed read-modify-write floating point atomic min with - * device memory scope. The original value at \p addr is returned and - * the value at \p addr is replaced by \p val if lesser. - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be updated - * @param [in] val Value used to update the value at \p addr. - * @return Original value contained in \p addr. - */ -__device__ inline float safeAtomicMin(float* addr, float val) { - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -} - -/** - * @brief Safe double precision rmw atomic add. - * - * Performs a relaxed read-modify-write double precision atomic add with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated to have the original value plus \p value - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be increment by \p value. - * @param [in] value Value by \p addr is to be incremented. - * @return Original value contained in \p addr. - */ -__device__ inline double safeAtomicAdd(double* addr, double value) { -#if defined(__gfx90a__) && __has_builtin(__hip_atomic_fetch_add) - // On gfx90a, with the __hip_atomic_fetch_add builtin, relaxed system-scope - // atomics will produce safe CAS loops, but are otherwise not different than - // agent-scope atomics. This logic is only applicable for gfx90a, and should - // not be assumed on other architectures. - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#elif defined(__gfx90a__) - // On gfx90a, if we do not have the __hip_atomic_fetch_add builtin, we need to - // force a CAS loop here. - double old_val; -#if __has_builtin(__hip_atomic_load) - old_val = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else // !__has_builtin(__hip_atomic_load) - old_val = __longlong_as_double(__atomic_load_n(reinterpret_cast(addr), __ATOMIC_RELAXED)); -#endif // __has_builtin(__hip_atomic_load) - double expected, temp; - do { - temp = expected = old_val; -#if __has_builtin(__hip_atomic_compare_exchange_strong) - __hip_atomic_compare_exchange_strong(addr, &expected, old_val + value, __ATOMIC_RELAXED, - __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else // !__has_builtin(__hip_atomic_compare_exchange_strong) - __atomic_compare_exchange_n(addr, &expected, old_val + value, false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); -#endif // __has_builtin(__hip_atomic_compare_exchange_strong) - old_val = expected; - } while (__double_as_longlong(temp) != __double_as_longlong(old_val)); - return old_val; -#else // !defined(__gfx90a__) -#if __has_builtin(__hip_atomic_fetch_add) - return __hip_atomic_fetch_add(addr, value, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#else // !__has_builtin(__hip_atomic_fetch_add) - return __atomic_fetch_add(addr, value, __ATOMIC_RELAXED); -#endif // __has_builtin(__hip_atomic_fetch_add) -#endif -} - -/** - * @brief Safe double precision rmw atomic max. - * - * Performs a relaxed read-modify-write double precision atomic max with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated with \p val if greater. - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be updated. - * @param [in] val Value used to updated the contents at \p addr - * @return Original value contained at \p addr. - */ -__device__ inline double safeAtomicMax(double* addr, double val) { - #if __has_builtin(__builtin_amdgcn_is_private) - if (__builtin_amdgcn_is_private( - (const __attribute__((address_space(0))) void*)addr)) { - double old = *addr; - *addr = __builtin_fmax(old, val); - return old; - } else { - #endif - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif - #if __has_builtin(__builtin_amdgcn_is_private) - } - #endif -} - -/** - * @brief Safe double precision rmw atomic min. - * - * Performs a relaxed read-modify-write double precision atomic min with - * device memory scope. Original value at \p addr is returned and - * the value of \p addr is updated with \p val if lesser. - * - * @note This operation ensures that, on all targets, we produce safe atomics. - * This will be the case even when -munsafe-fp-atomics is passed into the compiler. - * - * @param [in,out] addr Pointer to value to be updated. - * @param [in] val Value used to updated the contents at \p addr - * @return Original value contained at \p addr. - */ -__device__ inline double safeAtomicMin(double* addr, double val) { - #if __has_builtin(__builtin_amdgcn_is_private) - if (__builtin_amdgcn_is_private( - (const __attribute__((address_space(0))) void*)addr)) { - double old = *addr; - *addr = __builtin_fmin(old, val); - return old; - } else { - #endif - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif - #if __has_builtin(__builtin_amdgcn_is_private) - } - #endif -} - -#endif -/* -Copyright (c) 2015 - Present Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if !defined(__HIPCC_RTC__) -#include "amd_device_functions.h" -#endif - -#if __has_builtin(__hip_atomic_compare_exchange_strong) - -template struct Cond_t; - -template struct Cond_t { using type = T; }; -template struct Cond_t { using type = F; }; - -#if !__HIP_DEVICE_COMPILE__ -//TODO: Remove this after compiler pre-defines the following Macros. -#define __HIP_MEMORY_SCOPE_SINGLETHREAD 1 -#define __HIP_MEMORY_SCOPE_WAVEFRONT 2 -#define __HIP_MEMORY_SCOPE_WORKGROUP 3 -#define __HIP_MEMORY_SCOPE_AGENT 4 -#define __HIP_MEMORY_SCOPE_SYSTEM 5 -#endif - -#if !defined(__HIPCC_RTC__) -#include "amd_hip_unsafe_atomics.h" -#endif - -// Atomic expanders -template< - int mem_order = __ATOMIC_SEQ_CST, - int mem_scope= __HIP_MEMORY_SCOPE_SYSTEM, - typename T, - typename Op, - typename F> -inline -__attribute__((always_inline, device)) -T hip_cas_expander(T* p, T x, Op op, F f) noexcept -{ - using FP = __attribute__((address_space(0))) const void*; - - __device__ - extern bool is_shared_workaround(FP) asm("llvm.amdgcn.is.shared"); - - if (is_shared_workaround((FP)p)) - return f(); - - using U = typename Cond_t< - sizeof(T) == sizeof(unsigned int), unsigned int, unsigned long long>::type; - - auto q = reinterpret_cast(p); - - U tmp0{__hip_atomic_load(q, mem_order, mem_scope)}; - U tmp1; - do { - tmp1 = tmp0; - - op(reinterpret_cast(tmp1), x); - } while (!__hip_atomic_compare_exchange_strong(q, &tmp0, tmp1, mem_order, - mem_order, mem_scope)); - - return reinterpret_cast(tmp0); -} - -template< - int mem_order = __ATOMIC_SEQ_CST, - int mem_scope= __HIP_MEMORY_SCOPE_SYSTEM, - typename T, - typename Cmp, - typename F> -inline -__attribute__((always_inline, device)) -T hip_cas_extrema_expander(T* p, T x, Cmp cmp, F f) noexcept -{ - using FP = __attribute__((address_space(0))) const void*; - - __device__ - extern bool is_shared_workaround(FP) asm("llvm.amdgcn.is.shared"); - - if (is_shared_workaround((FP)p)) - return f(); - - using U = typename Cond_t< - sizeof(T) == sizeof(unsigned int), unsigned int, unsigned long long>::type; - - auto q = reinterpret_cast(p); - - U tmp{__hip_atomic_load(q, mem_order, mem_scope)}; - while (cmp(x, reinterpret_cast(tmp)) && - !__hip_atomic_compare_exchange_strong(q, &tmp, x, mem_order, mem_order, - mem_scope)); - - return reinterpret_cast(tmp); -} - -__device__ -inline -int atomicCAS(int* address, int compare, int val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -int atomicCAS_system(int* address, int compare, int val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -unsigned int atomicCAS(unsigned int* address, unsigned int compare, unsigned int val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -unsigned int atomicCAS_system(unsigned int* address, unsigned int compare, unsigned int val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -unsigned long atomicCAS(unsigned long* address, unsigned long compare, unsigned long val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -unsigned long atomicCAS_system(unsigned long* address, unsigned long compare, unsigned long val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -unsigned long long atomicCAS(unsigned long long* address, unsigned long long compare, - unsigned long long val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -unsigned long long atomicCAS_system(unsigned long long* address, unsigned long long compare, - unsigned long long val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -float atomicCAS(float* address, float compare, float val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -float atomicCAS_system(float* address, float compare, float val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -double atomicCAS(double* address, double compare, double val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - return compare; -} - -__device__ -inline -double atomicCAS_system(double* address, double compare, double val) { - __hip_atomic_compare_exchange_strong(address, &compare, val, __ATOMIC_RELAXED, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - return compare; -} - -__device__ -inline -int atomicAdd(int* address, int val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -int atomicAdd_system(int* address, int val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned int atomicAdd(unsigned int* address, unsigned int val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned int atomicAdd_system(unsigned int* address, unsigned int val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long atomicAdd(unsigned long* address, unsigned long val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long atomicAdd_system(unsigned long* address, unsigned long val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long long atomicAdd(unsigned long long* address, unsigned long long val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long long atomicAdd_system(unsigned long long* address, unsigned long long val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -float atomicAdd(float* address, float val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, val); -#else - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif -} - -__device__ -inline -float atomicAdd_system(float* address, float val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -#if !defined(__HIPCC_RTC__) -DEPRECATED("use atomicAdd instead") -#endif // !defined(__HIPCC_RTC__) -__device__ -inline -void atomicAddNoRet(float* address, float val) -{ - __ockl_atomic_add_noret_f32(address, val); -} - -__device__ -inline -double atomicAdd(double* address, double val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, val); -#else - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif -} - -__device__ -inline -double atomicAdd_system(double* address, double val) { - return __hip_atomic_fetch_add(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -int atomicSub(int* address, int val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -int atomicSub_system(int* address, int val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned int atomicSub(unsigned int* address, unsigned int val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned int atomicSub_system(unsigned int* address, unsigned int val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long atomicSub(unsigned long* address, unsigned long val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long atomicSub_system(unsigned long* address, unsigned long val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long long atomicSub(unsigned long long* address, unsigned long long val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long long atomicSub_system(unsigned long long* address, unsigned long long val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -float atomicSub(float* address, float val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, -val); -#else - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif -} - -__device__ -inline -float atomicSub_system(float* address, float val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -double atomicSub(double* address, double val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, -val); -#else - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif -} - -__device__ -inline -double atomicSub_system(double* address, double val) { - return __hip_atomic_fetch_add(address, -val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -int atomicExch(int* address, int val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -int atomicExch_system(int* address, int val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned int atomicExch(unsigned int* address, unsigned int val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned int atomicExch_system(unsigned int* address, unsigned int val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long atomicExch(unsigned long* address, unsigned long val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long atomicExch_system(unsigned long* address, unsigned long val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -unsigned long long atomicExch(unsigned long long* address, unsigned long long val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -unsigned long long atomicExch_system(unsigned long long* address, unsigned long long val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -float atomicExch(float* address, float val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -float atomicExch_system(float* address, float val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -double atomicExch(double* address, double val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -} - -__device__ -inline -double atomicExch_system(double* address, double val) { - return __hip_atomic_exchange(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -__device__ -inline -int atomicMin(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](int x, int y) { return x < y; }, [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -int atomicMin_system(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](int x, int y) { return x < y; }, [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicMin(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned int x, unsigned int y) { return x < y; }, [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ - -} - -__device__ -inline -unsigned int atomicMin_system(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned int x, unsigned int y) { return x < y; }, [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicMin(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long x, unsigned long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicMin_system(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long x, unsigned long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicMin(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long long x, unsigned long long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicMin_system(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long long x, unsigned long long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -long long atomicMin(long long* address, long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](long long x, long long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -long long atomicMin_system(long long* address, long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](long long x, long long y) { return x < y; }, - [=]() { - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_min(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -float atomicMin(float* addr, float val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicMin(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -#endif -} - -__device__ -inline -float atomicMin_system(float* address, float val) { - unsigned int* uaddr { reinterpret_cast(address) }; - #if __has_builtin(__hip_atomic_load) - unsigned int tmp {__hip_atomic_load(uaddr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM)}; - #else - unsigned int tmp {__atomic_load_n(uaddr, __ATOMIC_RELAXED)}; - #endif - float value = __uint_as_float(tmp); - - while (val < value) { - value = atomicCAS_system(address, value, val); - } - - return value; -} - -__device__ -inline -double atomicMin(double* addr, double val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicMin(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value > val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) > val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif -#endif -} - -__device__ -inline -double atomicMin_system(double* address, double val) { - unsigned long long* uaddr { reinterpret_cast(address) }; - #if __has_builtin(__hip_atomic_load) - unsigned long long tmp {__hip_atomic_load(uaddr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM)}; - #else - unsigned long long tmp {__atomic_load_n(uaddr, __ATOMIC_RELAXED)}; - #endif - double value = __longlong_as_double(tmp); - - while (val < value) { - value = atomicCAS_system(address, value, val); - } - - return value; -} - -__device__ -inline -int atomicMax(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](int x, int y) { return y < x; }, [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -int atomicMax_system(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](int x, int y) { return y < x; }, [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicMax(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned int x, unsigned int y) { return y < x; }, [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicMax_system(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned int x, unsigned int y) { return y < x; }, [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicMax(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long x, unsigned long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicMax_system(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long x, unsigned long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicMax(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long long x, unsigned long long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicMax_system(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long long x, unsigned long long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -long long atomicMax(long long* address, long long val) { - #if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](long long x, long long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -long long atomicMax_system(long long* address, long long val) { -#if defined(__gfx941__) - return hip_cas_extrema_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](long long x, long long y) { return y < x; }, - [=]() { - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_max(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -float atomicMax(float* addr, float val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicMax(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - float value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned int *uaddr = (unsigned int *)addr; - unsigned int value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __uint_as_float(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __float_as_uint(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __uint_as_float(value); - #endif -#endif -} - -__device__ -inline -float atomicMax_system(float* address, float val) { - unsigned int* uaddr { reinterpret_cast(address) }; - #if __has_builtin(__hip_atomic_load) - unsigned int tmp {__hip_atomic_load(uaddr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM)}; - #else - unsigned int tmp {__atomic_load_n(uaddr, __ATOMIC_RELAXED)}; - #endif - float value = __uint_as_float(tmp); - - while (value < val) { - value = atomicCAS_system(address, value, val); - } - - return value; -} - -__device__ -inline -double atomicMax(double* addr, double val) { -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicMax(addr, val); -#else - #if __has_builtin(__hip_atomic_load) && \ - __has_builtin(__hip_atomic_compare_exchange_strong) - double value = __hip_atomic_load(addr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - bool done = false; - while (!done && value < val) { - done = __hip_atomic_compare_exchange_strong(addr, &value, val, - __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); - } - return value; - #else - unsigned long long *uaddr = (unsigned long long *)addr; - unsigned long long value = __atomic_load_n(uaddr, __ATOMIC_RELAXED); - bool done = false; - while (!done && __longlong_as_double(value) < val) { - done = __atomic_compare_exchange_n(uaddr, &value, __double_as_longlong(val), false, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); - } - return __longlong_as_double(value); - #endif -#endif -} - -__device__ -inline -double atomicMax_system(double* address, double val) { - unsigned long long* uaddr { reinterpret_cast(address) }; - #if __has_builtin(__hip_atomic_load) - unsigned long long tmp {__hip_atomic_load(uaddr, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM)}; - #else - unsigned long long tmp {__atomic_load_n(uaddr, __ATOMIC_RELAXED)}; - #endif - double value = __longlong_as_double(tmp); - - while (value < val) { - value = atomicCAS_system(address, value, val); - } - - return value; -} - -__device__ -inline -unsigned int atomicInc(unsigned int* address, unsigned int val) -{ -#if defined(__gfx941__) - __device__ - extern - unsigned int __builtin_amdgcn_atomic_inc( - unsigned int*, - unsigned int, - unsigned int, - unsigned int, - bool) __asm("llvm.amdgcn.atomic.inc.i32.p0i32"); - - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned int& x, unsigned int y) { x = (x >= y) ? 0 : (x + 1); }, - [=]() { - return - __builtin_amdgcn_atomic_inc(address, val, __ATOMIC_RELAXED, 1, false); - }); -#else - return __builtin_amdgcn_atomic_inc32(address, val, __ATOMIC_RELAXED, "agent"); -#endif // __gfx941__ - -} - -__device__ -inline -unsigned int atomicDec(unsigned int* address, unsigned int val) -{ -#if defined(__gfx941__) - __device__ - extern - unsigned int __builtin_amdgcn_atomic_dec( - unsigned int*, - unsigned int, - unsigned int, - unsigned int, - bool) __asm("llvm.amdgcn.atomic.dec.i32.p0i32"); - - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned int& x, unsigned int y) { x = (!x || x > y) ? y : (x - 1); }, - [=]() { - return - __builtin_amdgcn_atomic_dec(address, val, __ATOMIC_RELAXED, 1, false); - }); -#else - return __builtin_amdgcn_atomic_dec32(address, val, __ATOMIC_RELAXED, "agent"); -#endif // __gfx941__ - -} - -__device__ -inline -int atomicAnd(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](int& x, int y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -int atomicAnd_system(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](int& x, int y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicAnd(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned int& x, unsigned int y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicAnd_system(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned int& x, unsigned int y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicAnd(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned long& x, unsigned long y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicAnd_system(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned long& x, unsigned long y) { x &= y; }, [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicAnd(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long long& x, unsigned long long y) { x &= y; }, - [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicAnd_system(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long long& x, unsigned long long y) { x &= y; }, - [=]() { - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_and(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -int atomicOr(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](int& x, int y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -int atomicOr_system(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](int& x, int y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicOr(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned int& x, unsigned int y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicOr_system(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned int& x, unsigned int y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicOr(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned long& x, unsigned long y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicOr_system(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned long& x, unsigned long y) { x |= y; }, [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicOr(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long long& x, unsigned long long y) { x |= y; }, - [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicOr_system(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, - val, - [](unsigned long long& x, unsigned long long y) { x |= y; }, - [=]() { - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_or(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -int atomicXor(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](int& x, int y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -int atomicXor_system(int* address, int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](int& x, int y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicXor(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned int& x, unsigned int y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned int atomicXor_system(unsigned int* address, unsigned int val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned int& x, unsigned int y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicXor(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, val, [](unsigned long& x, unsigned long y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long atomicXor_system(unsigned long* address, unsigned long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM>( - address, val, [](unsigned long& x, unsigned long y) { x ^= y; }, [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_SYSTEM); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicXor(unsigned long long* address, unsigned long long val) { -#if defined(__gfx941__) - return hip_cas_expander<__ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT>( - address, - val, - [](unsigned long long& x, unsigned long long y) { x ^= y; }, - [=]() { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, - __HIP_MEMORY_SCOPE_AGENT); - }); -#else - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); -#endif // __gfx941__ -} - -__device__ -inline -unsigned long long atomicXor_system(unsigned long long* address, unsigned long long val) { - return __hip_atomic_fetch_xor(address, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); -} - -#else // __hip_atomic_compare_exchange_strong - -__device__ -inline -int atomicCAS(int* address, int compare, int val) -{ - __atomic_compare_exchange_n( - address, &compare, val, false, __ATOMIC_RELAXED, __ATOMIC_RELAXED); - - return compare; -} -__device__ -inline -unsigned int atomicCAS( - unsigned int* address, unsigned int compare, unsigned int val) -{ - __atomic_compare_exchange_n( - address, &compare, val, false, __ATOMIC_RELAXED, __ATOMIC_RELAXED); - - return compare; -} -__device__ -inline -unsigned long long atomicCAS( - unsigned long long* address, - unsigned long long compare, - unsigned long long val) -{ - __atomic_compare_exchange_n( - address, &compare, val, false, __ATOMIC_RELAXED, __ATOMIC_RELAXED); - - return compare; -} - -__device__ -inline -int atomicAdd(int* address, int val) -{ - return __atomic_fetch_add(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicAdd(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_add(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicAdd( - unsigned long long* address, unsigned long long val) -{ - return __atomic_fetch_add(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -float atomicAdd(float* address, float val) -{ -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, val); -#else - return __atomic_fetch_add(address, val, __ATOMIC_RELAXED); -#endif -} - -#if !defined(__HIPCC_RTC__) -DEPRECATED("use atomicAdd instead") -#endif // !defined(__HIPCC_RTC__) -__device__ -inline -void atomicAddNoRet(float* address, float val) -{ - __ockl_atomic_add_noret_f32(address, val); -} - -__device__ -inline -double atomicAdd(double* address, double val) -{ -#if defined(__AMDGCN_UNSAFE_FP_ATOMICS__) - return unsafeAtomicAdd(address, val); -#else - return __atomic_fetch_add(address, val, __ATOMIC_RELAXED); -#endif -} - -__device__ -inline -int atomicSub(int* address, int val) -{ - return __atomic_fetch_sub(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicSub(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_sub(address, val, __ATOMIC_RELAXED); -} - -__device__ -inline -int atomicExch(int* address, int val) -{ - return __atomic_exchange_n(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicExch(unsigned int* address, unsigned int val) -{ - return __atomic_exchange_n(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicExch(unsigned long long* address, unsigned long long val) -{ - return __atomic_exchange_n(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -float atomicExch(float* address, float val) -{ - return __uint_as_float(__atomic_exchange_n( - reinterpret_cast(address), - __float_as_uint(val), - __ATOMIC_RELAXED)); -} - -__device__ -inline -int atomicMin(int* address, int val) -{ - return __atomic_fetch_min(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicMin(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_min(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicMin( - unsigned long long* address, unsigned long long val) -{ - unsigned long long tmp{__atomic_load_n(address, __ATOMIC_RELAXED)}; - while (val < tmp) { - const auto tmp1 = __atomic_load_n(address, __ATOMIC_RELAXED); - - if (tmp1 != tmp) { tmp = tmp1; continue; } - - tmp = atomicCAS(address, tmp, val); - } - - return tmp; -} -__device__ inline long long atomicMin(long long* address, long long val) { - long long tmp{__atomic_load_n(address, __ATOMIC_RELAXED)}; - while (val < tmp) { - const auto tmp1 = __atomic_load_n(address, __ATOMIC_RELAXED); - - if (tmp1 != tmp) { - tmp = tmp1; - continue; - } - - tmp = atomicCAS(address, tmp, val); - } - return tmp; -} - -__device__ -inline -int atomicMax(int* address, int val) -{ - return __atomic_fetch_max(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicMax(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_max(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicMax( - unsigned long long* address, unsigned long long val) -{ - unsigned long long tmp{__atomic_load_n(address, __ATOMIC_RELAXED)}; - while (tmp < val) { - const auto tmp1 = __atomic_load_n(address, __ATOMIC_RELAXED); - - if (tmp1 != tmp) { tmp = tmp1; continue; } - - tmp = atomicCAS(address, tmp, val); - } - - return tmp; -} -__device__ inline long long atomicMax(long long* address, long long val) { - long long tmp{__atomic_load_n(address, __ATOMIC_RELAXED)}; - while (tmp < val) { - const auto tmp1 = __atomic_load_n(address, __ATOMIC_RELAXED); - - if (tmp1 != tmp) { - tmp = tmp1; - continue; - } - - tmp = atomicCAS(address, tmp, val); - } - return tmp; -} - -__device__ -inline -unsigned int atomicInc(unsigned int* address, unsigned int val) -{ - return __builtin_amdgcn_atomic_inc32(address, val, __ATOMIC_RELAXED, "agent"); -} - -__device__ -inline -unsigned int atomicDec(unsigned int* address, unsigned int val) -{ - return __builtin_amdgcn_atomic_dec32(address, val, __ATOMIC_RELAXED, "agent"); -} - -__device__ -inline -int atomicAnd(int* address, int val) -{ - return __atomic_fetch_and(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicAnd(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_and(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicAnd( - unsigned long long* address, unsigned long long val) -{ - return __atomic_fetch_and(address, val, __ATOMIC_RELAXED); -} - -__device__ -inline -int atomicOr(int* address, int val) -{ - return __atomic_fetch_or(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicOr(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_or(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicOr( - unsigned long long* address, unsigned long long val) -{ - return __atomic_fetch_or(address, val, __ATOMIC_RELAXED); -} - -__device__ -inline -int atomicXor(int* address, int val) -{ - return __atomic_fetch_xor(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned int atomicXor(unsigned int* address, unsigned int val) -{ - return __atomic_fetch_xor(address, val, __ATOMIC_RELAXED); -} -__device__ -inline -unsigned long long atomicXor( - unsigned long long* address, unsigned long long val) -{ - return __atomic_fetch_xor(address, val, __ATOMIC_RELAXED); -} - -#endif // __hip_atomic_compare_exchange_strong -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if !defined(__HIPCC_RTC__) -#include "host_defines.h" -#include "amd_hip_vector_types.h" // For Native_vec_ -#endif - -#if defined(__cplusplus) - extern "C" { -#endif - -// DOT FUNCTIONS -#if defined(__clang__) && defined(__HIP__) -__device__ -__attribute__((const)) -int __ockl_sdot2( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot2( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - unsigned int, bool); - -__device__ -__attribute__((const)) -int __ockl_sdot4( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot4( - HIP_vector_base::Native_vec_, - HIP_vector_base::Native_vec_, - unsigned int, bool); - -__device__ -__attribute__((const)) -int __ockl_sdot8(int, int, int, bool); - -__device__ -__attribute__((const)) -unsigned int __ockl_udot8(unsigned int, unsigned int, unsigned int, bool); -#endif - -#if !__CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ -// BEGIN FLOAT -__device__ -__attribute__((const)) -float __ocml_acos_f32(float); -__device__ -__attribute__((pure)) -float __ocml_acosh_f32(float); -__device__ -__attribute__((const)) -float __ocml_asin_f32(float); -__device__ -__attribute__((pure)) -float __ocml_asinh_f32(float); -__device__ -__attribute__((const)) -float __ocml_atan2_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_atan_f32(float); -__device__ -__attribute__((pure)) -float __ocml_atanh_f32(float); -__device__ -__attribute__((pure)) -float __ocml_cbrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_ceil_f32(float); -__device__ -__attribute__((const)) -__device__ -float __ocml_copysign_f32(float, float); -__device__ -float __ocml_cos_f32(float); -__device__ -float __ocml_native_cos_f32(float); -__device__ -__attribute__((pure)) -__device__ -float __ocml_cosh_f32(float); -__device__ -float __ocml_cospi_f32(float); -__device__ -float __ocml_i0_f32(float); -__device__ -float __ocml_i1_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfc_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfcinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfcx_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erf_f32(float); -__device__ -__attribute__((pure)) -float __ocml_erfinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_exp10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp2_f32(float); -__device__ -__attribute__((pure)) -float __ocml_exp_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_exp_f32(float); -__device__ -__attribute__((pure)) -float __ocml_expm1_f32(float); -__device__ -__attribute__((const)) -float __ocml_fabs_f32(float); -__device__ -__attribute__((const)) -float __ocml_fdim_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_floor_f32(float); -__device__ -__attribute__((const)) -float __ocml_fma_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fmax_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_fmin_f32(float, float); -__device__ -__attribute__((const)) -__device__ -float __ocml_fmod_f32(float, float); -__device__ -float __ocml_frexp_f32(float, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -float __ocml_hypot_f32(float, float); -__device__ -__attribute__((const)) -int __ocml_ilogb_f32(float); -__device__ -__attribute__((const)) -int __ocml_isfinite_f32(float); -__device__ -__attribute__((const)) -int __ocml_isinf_f32(float); -__device__ -__attribute__((const)) -int __ocml_isnan_f32(float); -__device__ -float __ocml_j0_f32(float); -__device__ -float __ocml_j1_f32(float); -__device__ -__attribute__((const)) -float __ocml_ldexp_f32(float, int); -__device__ -float __ocml_lgamma_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log10_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log1p_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log2_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log2_f32(float); -__device__ -__attribute__((const)) -float __ocml_logb_f32(float); -__device__ -__attribute__((pure)) -float __ocml_log_f32(float); -__device__ -__attribute__((pure)) -float __ocml_native_log_f32(float); -__device__ -float __ocml_modf_f32(float, __attribute__((address_space(5))) float*); -__device__ -__attribute__((const)) -float __ocml_nearbyint_f32(float); -__device__ -__attribute__((const)) -float __ocml_nextafter_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_len3_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_len4_f32(float, float, float, float); -__device__ -__attribute__((pure)) -float __ocml_ncdf_f32(float); -__device__ -__attribute__((pure)) -float __ocml_ncdfinv_f32(float); -__device__ -__attribute__((pure)) -float __ocml_pow_f32(float, float); -__device__ -__attribute__((pure)) -float __ocml_pown_f32(float, int); -__device__ -__attribute__((pure)) -float __ocml_rcbrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_remainder_f32(float, float); -__device__ -float __ocml_remquo_f32(float, float, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -float __ocml_rhypot_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_rint_f32(float); -__device__ -__attribute__((const)) -float __ocml_rlen3_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_rlen4_f32(float, float, float, float); -__device__ -__attribute__((const)) -float __ocml_round_f32(float); -__device__ -__attribute__((pure)) -float __ocml_rsqrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_scalb_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_scalbn_f32(float, int); -__device__ -__attribute__((const)) -int __ocml_signbit_f32(float); -__device__ -float __ocml_sincos_f32(float, __attribute__((address_space(5))) float*); -__device__ -float __ocml_sincospi_f32(float, __attribute__((address_space(5))) float*); -__device__ -float __ocml_sin_f32(float); -__device__ -float __ocml_native_sin_f32(float); -__device__ -__attribute__((pure)) -float __ocml_sinh_f32(float); -__device__ -float __ocml_sinpi_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_f32(float); -__device__ -__attribute__((const)) -float __ocml_native_sqrt_f32(float); -__device__ -float __ocml_tan_f32(float); -__device__ -__attribute__((pure)) -float __ocml_tanh_f32(float); -__device__ -float __ocml_tgamma_f32(float); -__device__ -__attribute__((const)) -float __ocml_trunc_f32(float); -__device__ -float __ocml_y0_f32(float); -__device__ -float __ocml_y1_f32(float); - -// BEGIN INTRINSICS -__device__ -__attribute__((const)) -float __ocml_add_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_add_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sub_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_mul_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rte_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtn_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtp_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_div_rtz_f32(float, float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rte_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtn_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtp_f32(float); -__device__ -__attribute__((const)) -float __ocml_sqrt_rtz_f32(float); -__device__ -__attribute__((const)) -float __ocml_fma_rte_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtn_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtp_f32(float, float, float); -__device__ -__attribute__((const)) -float __ocml_fma_rtz_f32(float, float, float); -// END INTRINSICS -// END FLOAT - -// BEGIN DOUBLE -__device__ -__attribute__((const)) -double __ocml_acos_f64(double); -__device__ -__attribute__((pure)) -double __ocml_acosh_f64(double); -__device__ -__attribute__((const)) -double __ocml_asin_f64(double); -__device__ -__attribute__((pure)) -double __ocml_asinh_f64(double); -__device__ -__attribute__((const)) -double __ocml_atan2_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_atan_f64(double); -__device__ -__attribute__((pure)) -double __ocml_atanh_f64(double); -__device__ -__attribute__((pure)) -double __ocml_cbrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_ceil_f64(double); -__device__ -__attribute__((const)) -double __ocml_copysign_f64(double, double); -__device__ -double __ocml_cos_f64(double); -__device__ -__attribute__((pure)) -double __ocml_cosh_f64(double); -__device__ -double __ocml_cospi_f64(double); -__device__ -double __ocml_i0_f64(double); -__device__ -double __ocml_i1_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfc_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfcinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfcx_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erf_f64(double); -__device__ -__attribute__((pure)) -double __ocml_erfinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp10_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp2_f64(double); -__device__ -__attribute__((pure)) -double __ocml_exp_f64(double); -__device__ -__attribute__((pure)) -double __ocml_expm1_f64(double); -__device__ -__attribute__((const)) -double __ocml_fabs_f64(double); -__device__ -__attribute__((const)) -double __ocml_fdim_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_floor_f64(double); -__device__ -__attribute__((const)) -double __ocml_fma_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fmax_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_fmin_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_fmod_f64(double, double); -__device__ -double __ocml_frexp_f64(double, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -double __ocml_hypot_f64(double, double); -__device__ -__attribute__((const)) -int __ocml_ilogb_f64(double); -__device__ -__attribute__((const)) -int __ocml_isfinite_f64(double); -__device__ -__attribute__((const)) -int __ocml_isinf_f64(double); -__device__ -__attribute__((const)) -int __ocml_isnan_f64(double); -__device__ -double __ocml_j0_f64(double); -__device__ -double __ocml_j1_f64(double); -__device__ -__attribute__((const)) -double __ocml_ldexp_f64(double, int); -__device__ -double __ocml_lgamma_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log10_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log1p_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log2_f64(double); -__device__ -__attribute__((const)) -double __ocml_logb_f64(double); -__device__ -__attribute__((pure)) -double __ocml_log_f64(double); -__device__ -double __ocml_modf_f64(double, __attribute__((address_space(5))) double*); -__device__ -__attribute__((const)) -double __ocml_nearbyint_f64(double); -__device__ -__attribute__((const)) -double __ocml_nextafter_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_len3_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_len4_f64(double, double, double, double); -__device__ -__attribute__((pure)) -double __ocml_ncdf_f64(double); -__device__ -__attribute__((pure)) -double __ocml_ncdfinv_f64(double); -__device__ -__attribute__((pure)) -double __ocml_pow_f64(double, double); -__device__ -__attribute__((pure)) -double __ocml_pown_f64(double, int); -__device__ -__attribute__((pure)) -double __ocml_rcbrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_remainder_f64(double, double); -__device__ -double __ocml_remquo_f64( - double, double, __attribute__((address_space(5))) int*); -__device__ -__attribute__((const)) -double __ocml_rhypot_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_rint_f64(double); -__device__ -__attribute__((const)) -double __ocml_rlen3_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_rlen4_f64(double, double, double, double); -__device__ -__attribute__((const)) -double __ocml_round_f64(double); -__device__ -__attribute__((pure)) -double __ocml_rsqrt_f64(double); -__device__ -__attribute__((const)) -double __ocml_scalb_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_scalbn_f64(double, int); -__device__ -__attribute__((const)) -int __ocml_signbit_f64(double); -__device__ -double __ocml_sincos_f64(double, __attribute__((address_space(5))) double*); -__device__ -double __ocml_sincospi_f64(double, __attribute__((address_space(5))) double*); -__device__ -double __ocml_sin_f64(double); -__device__ -__attribute__((pure)) -double __ocml_sinh_f64(double); -__device__ -double __ocml_sinpi_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_f64(double); -__device__ -double __ocml_tan_f64(double); -__device__ -__attribute__((pure)) -double __ocml_tanh_f64(double); -__device__ -double __ocml_tgamma_f64(double); -__device__ -__attribute__((const)) -double __ocml_trunc_f64(double); -__device__ -double __ocml_y0_f64(double); -__device__ -double __ocml_y1_f64(double); - -// BEGIN INTRINSICS -__device__ -__attribute__((const)) -double __ocml_add_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_add_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sub_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_mul_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rte_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtn_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtp_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_div_rtz_f64(double, double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rte_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtn_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtp_f64(double); -__device__ -__attribute__((const)) -double __ocml_sqrt_rtz_f64(double); -__device__ -__attribute__((const)) -double __ocml_fma_rte_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtn_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtp_f64(double, double, double); -__device__ -__attribute__((const)) -double __ocml_fma_rtz_f64(double, double, double); -// END INTRINSICS -// END DOUBLE - -#endif // !__CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ - -#if defined(__cplusplus) - } // extern "C" -#endif -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -// /* -// Half Math Functions -// */ -#if !defined(__HIPCC_RTC__) -#include "host_defines.h" -#endif -#ifndef __CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ -extern "C" -{ - __device__ __attribute__((const)) _Float16 __ocml_ceil_f16(_Float16); - __device__ _Float16 __ocml_cos_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_exp_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_exp10_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_exp2_f16(_Float16); - __device__ __attribute__((const)) _Float16 __ocml_floor_f16(_Float16); - __device__ __attribute__((const)) - _Float16 __ocml_fma_f16(_Float16, _Float16, _Float16); - __device__ __attribute__((const)) _Float16 __ocml_fabs_f16(_Float16); - __device__ __attribute__((const)) int __ocml_isinf_f16(_Float16); - __device__ __attribute__((const)) int __ocml_isnan_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_log_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_log10_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_log2_f16(_Float16); - __device__ __attribute__((pure)) _Float16 __ocml_pown_f16(_Float16, int); - __device__ __attribute__((const)) _Float16 __ocml_rint_f16(_Float16); - __device__ __attribute__((const)) _Float16 __ocml_rsqrt_f16(_Float16); - __device__ _Float16 __ocml_sin_f16(_Float16); - __device__ __attribute__((const)) _Float16 __ocml_sqrt_f16(_Float16); - __device__ __attribute__((const)) _Float16 __ocml_trunc_f16(_Float16); - __device__ __attribute__((const)) _Float16 __ocml_fmax_f16(_Float16, _Float16); - __device__ __attribute__((const)) _Float16 __ocml_fmin_f16(_Float16, _Float16); - - typedef _Float16 __2f16 __attribute__((ext_vector_type(2))); - typedef short __2i16 __attribute__((ext_vector_type(2))); - - #if defined(__clang__) && defined(__HIP__) - __device__ __attribute__((const)) float __ockl_fdot2(__2f16 a, __2f16 b, float c, bool s); - #endif - - __device__ __attribute__((const)) __2f16 __ocml_ceil_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_fabs_2f16(__2f16); - __device__ __2f16 __ocml_cos_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_exp_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_exp10_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_exp2_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_floor_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_fma_2f16(__2f16, __2f16, __2f16); - __device__ __attribute__((const)) __2i16 __ocml_isinf_2f16(__2f16); - __device__ __attribute__((const)) __2i16 __ocml_isnan_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_log_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_log10_2f16(__2f16); - __device__ __attribute__((pure)) __2f16 __ocml_log2_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_rint_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_rsqrt_2f16(__2f16); - __device__ __2f16 __ocml_sin_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_sqrt_2f16(__2f16); - __device__ __attribute__((const)) __2f16 __ocml_trunc_2f16(__2f16); - - __device__ __attribute__((const)) _Float16 __ocml_cvtrtn_f16_f32(float); - __device__ __attribute__((const)) _Float16 __ocml_cvtrtp_f16_f32(float); - __device__ __attribute__((const)) _Float16 __ocml_cvtrtz_f16_f32(float); - -} -#endif // !__CLANG_HIP_RUNTIME_WRAPPER_INCLUDED__ -//TODO: remove these after they get into clang header __clang_hip_libdevice_declares.h' -extern "C" { - __device__ __attribute__((const)) _Float16 __ocml_fmax_f16(_Float16, _Float16); - __device__ __attribute__((const)) _Float16 __ocml_fmin_f16(_Float16, _Float16); - __device__ __attribute__((const)) _Float16 __ocml_cvtrtn_f16_f32(float); - __device__ __attribute__((const)) _Float16 __ocml_cvtrtp_f16_f32(float); - __device__ __attribute__((const)) _Float16 __ocml_cvtrtz_f16_f32(float); -} -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once -#ifndef HIP_INCLUDE_HIP_AMD_DETAIL_HIP_FP16_H -#define HIP_INCLUDE_HIP_AMD_DETAIL_HIP_FP16_H - -#if defined(__HIPCC_RTC__) - #define __HOST_DEVICE__ __device__ -#else - #define __HOST_DEVICE__ __host__ __device__ - #include - #include "hip/amd_detail/host_defines.h" - #include - #if defined(__cplusplus) - #include - #include - #include -#endif -#endif // !defined(__HIPCC_RTC__) - -#if defined(__clang__) && defined(__HIP__) - typedef _Float16 _Float16_2 __attribute__((ext_vector_type(2))); - - struct __half_raw { - union { - static_assert(sizeof(_Float16) == sizeof(unsigned short), ""); - - _Float16 data; - unsigned short x; - }; - }; - - struct __half2_raw { - union { - static_assert(sizeof(_Float16_2) == sizeof(unsigned short[2]), ""); - - struct { - __half_raw x; - __half_raw y; - }; - _Float16_2 data; - }; - }; - - #if defined(__cplusplus) - #if !defined(__HIPCC_RTC__) - #include "hip_fp16_math_fwd.h" - #include "amd_hip_vector_types.h" - #include "host_defines.h" - #include "amd_device_functions.h" - #include "amd_warp_functions.h" - #endif - namespace std - { - template<> struct is_floating_point<_Float16> : std::true_type {}; - } - - template - using Enable_if_t = typename std::enable_if::type; - - // BEGIN STRUCT __HALF - struct __half { - protected: - union { - static_assert(sizeof(_Float16) == sizeof(unsigned short), ""); - - _Float16 data; - unsigned short __x; - }; - public: - // CREATORS - __HOST_DEVICE__ - __half() = default; - __HOST_DEVICE__ - __half(const __half_raw& x) : data{x.data} {} - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - __HOST_DEVICE__ - __half(decltype(data) x) : data{x} {} - template< - typename T, - Enable_if_t{}>* = nullptr> - __HOST_DEVICE__ - __half(T x) : data{static_cast<_Float16>(x)} {} - #endif - __HOST_DEVICE__ - __half(const __half&) = default; - __HOST_DEVICE__ - __half(__half&&) = default; - __HOST_DEVICE__ - ~__half() = default; - - // CREATORS - DEVICE ONLY - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - template< - typename T, Enable_if_t{}>* = nullptr> - __HOST_DEVICE__ - __half(T x) : data{static_cast<_Float16>(x)} {} - #endif - - // MANIPULATORS - __HOST_DEVICE__ - __half& operator=(const __half&) = default; - __HOST_DEVICE__ - __half& operator=(__half&&) = default; - __HOST_DEVICE__ - __half& operator=(const __half_raw& x) - { - data = x.data; - return *this; - } - __HOST_DEVICE__ - volatile __half& operator=(const __half_raw& x) volatile - { - data = x.data; - return *this; - } - volatile __half& operator=(const volatile __half_raw& x) volatile - { - data = x.data; - return *this; - } - __half& operator=(__half_raw&& x) - { - data = x.data; - return *this; - } - volatile __half& operator=(__half_raw&& x) volatile - { - data = x.data; - return *this; - } - volatile __half& operator=(volatile __half_raw&& x) volatile - { - data = x.data; - return *this; - } - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - template< - typename T, - Enable_if_t{}>* = nullptr> - __HOST_DEVICE__ - __half& operator=(T x) - { - data = static_cast<_Float16>(x); - return *this; - } - #endif - - // MANIPULATORS - DEVICE ONLY - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - template< - typename T, Enable_if_t{}>* = nullptr> - __device__ - __half& operator=(T x) - { - data = static_cast<_Float16>(x); - return *this; - } - #endif - - #if !defined(__HIP_NO_HALF_OPERATORS__) - __device__ - __half& operator+=(const __half& x) - { - data += x.data; - return *this; - } - __device__ - __half& operator-=(const __half& x) - { - data -= x.data; - return *this; - } - __device__ - __half& operator*=(const __half& x) - { - data *= x.data; - return *this; - } - __device__ - __half& operator/=(const __half& x) - { - data /= x.data; - return *this; - } - __device__ - __half& operator++() { ++data; return *this; } - __device__ - __half operator++(int) - { - __half tmp{*this}; - ++*this; - return tmp; - } - __device__ - __half& operator--() { --data; return *this; } - __device__ - __half operator--(int) - { - __half tmp{*this}; - --*this; - return tmp; - } - #endif - - // ACCESSORS - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - template< - typename T, - Enable_if_t{}>* = nullptr> - __HOST_DEVICE__ - operator T() const { return data; } - #endif - __HOST_DEVICE__ - operator __half_raw() const { return __half_raw{data}; } - __HOST_DEVICE__ - operator __half_raw() const volatile - { - return __half_raw{data}; - } - - #if !defined(__HIP_NO_HALF_CONVERSIONS__) - template< - typename T, Enable_if_t{}>* = nullptr> - __HOST_DEVICE__ - operator T() const { return data; } - #endif - - #if !defined(__HIP_NO_HALF_OPERATORS__) - __device__ - __half operator+() const { return *this; } - __device__ - __half operator-() const - { - __half tmp{*this}; - tmp.data = -tmp.data; - return tmp; - } - #endif - - // FRIENDS - #if !defined(__HIP_NO_HALF_OPERATORS__) - friend - inline - __device__ - __half operator+(const __half& x, const __half& y) - { - return __half{x} += y; - } - friend - inline - __device__ - __half operator-(const __half& x, const __half& y) - { - return __half{x} -= y; - } - friend - inline - __device__ - __half operator*(const __half& x, const __half& y) - { - return __half{x} *= y; - } - friend - inline - __device__ - __half operator/(const __half& x, const __half& y) - { - return __half{x} /= y; - } - friend - inline - __device__ - bool operator==(const __half& x, const __half& y) - { - return x.data == y.data; - } - friend - inline - __device__ - bool operator!=(const __half& x, const __half& y) - { - return !(x == y); - } - friend - inline - __device__ - bool operator<(const __half& x, const __half& y) - { - return x.data < y.data; - } - friend - inline - __device__ - bool operator>(const __half& x, const __half& y) - { - return y.data < x.data; - } - friend - inline - __device__ - bool operator<=(const __half& x, const __half& y) - { - return !(y < x); - } - friend - inline - __device__ - bool operator>=(const __half& x, const __half& y) - { - return !(x < y); - } - #endif // !defined(__HIP_NO_HALF_OPERATORS__) - }; - // END STRUCT __HALF - - // BEGIN STRUCT __HALF2 - struct __half2 { - public: - union { - static_assert( - sizeof(_Float16_2) == sizeof(unsigned short[2]), ""); - - struct { - __half x; - __half y; - }; - _Float16_2 data; - }; - - // CREATORS - __HOST_DEVICE__ - __half2() = default; - __HOST_DEVICE__ - __half2(const __half2_raw& xx) : data{xx.data} {} - __HOST_DEVICE__ - __half2(decltype(data) xx) : data{xx} {} - __HOST_DEVICE__ - __half2(const __half& xx, const __half& yy) - : - data{static_cast<__half_raw>(xx).data, - static_cast<__half_raw>(yy).data} - {} - __HOST_DEVICE__ - __half2(const __half2&) = default; - __HOST_DEVICE__ - __half2(__half2&&) = default; - __HOST_DEVICE__ - ~__half2() = default; - - // MANIPULATORS - __HOST_DEVICE__ - __half2& operator=(const __half2&) = default; - __HOST_DEVICE__ - __half2& operator=(__half2&&) = default; - __HOST_DEVICE__ - __half2& operator=(const __half2_raw& xx) - { - data = xx.data; - return *this; - } - - // MANIPULATORS - DEVICE ONLY - #if !defined(__HIP_NO_HALF_OPERATORS__) - __device__ - __half2& operator+=(const __half2& xx) - { - data += xx.data; - return *this; - } - __device__ - __half2& operator-=(const __half2& xx) - { - data -= xx.data; - return *this; - } - __device__ - __half2& operator*=(const __half2& xx) - { - data *= xx.data; - return *this; - } - __device__ - __half2& operator/=(const __half2& xx) - { - data /= xx.data; - return *this; - } - __device__ - __half2& operator++() { return *this += _Float16_2{1, 1}; } - __device__ - __half2 operator++(int) - { - __half2 tmp{*this}; - ++*this; - return tmp; - } - __device__ - __half2& operator--() { return *this -= _Float16_2{1, 1}; } - __device__ - __half2 operator--(int) - { - __half2 tmp{*this}; - --*this; - return tmp; - } - #endif - - // ACCESSORS - __HOST_DEVICE__ - operator decltype(data)() const { return data; } - __HOST_DEVICE__ - operator __half2_raw() const { - __half2_raw r; - r.data = data; - return r; - } - - // ACCESSORS - DEVICE ONLY - #if !defined(__HIP_NO_HALF_OPERATORS__) - __device__ - __half2 operator+() const { return *this; } - __device__ - __half2 operator-() const - { - __half2 tmp{*this}; - tmp.data = -tmp.data; - return tmp; - } - #endif - - // FRIENDS - #if !defined(__HIP_NO_HALF_OPERATORS__) - friend - inline - __device__ - __half2 operator+(const __half2& xx, const __half2& yy) - { - return __half2{xx} += yy; - } - friend - inline - __device__ - __half2 operator-(const __half2& xx, const __half2& yy) - { - return __half2{xx} -= yy; - } - friend - inline - __device__ - __half2 operator*(const __half2& xx, const __half2& yy) - { - return __half2{xx} *= yy; - } - friend - inline - __device__ - __half2 operator/(const __half2& xx, const __half2& yy) - { - return __half2{xx} /= yy; - } - friend - inline - __device__ - bool operator==(const __half2& xx, const __half2& yy) - { - auto r = xx.data == yy.data; - return r.x != 0 && r.y != 0; - } - friend - inline - __device__ - bool operator!=(const __half2& xx, const __half2& yy) - { - return !(xx == yy); - } - friend - inline - __device__ - bool operator<(const __half2& xx, const __half2& yy) - { - auto r = xx.data < yy.data; - return r.x != 0 && r.y != 0; - } - friend - inline - __device__ - bool operator>(const __half2& xx, const __half2& yy) - { - return yy < xx; - } - friend - inline - __device__ - bool operator<=(const __half2& xx, const __half2& yy) - { - return !(yy < xx); - } - friend - inline - __device__ - bool operator>=(const __half2& xx, const __half2& yy) - { - return !(xx < yy); - } - #endif // !defined(__HIP_NO_HALF_OPERATORS__) - }; - // END STRUCT __HALF2 - - namespace - { - inline - __HOST_DEVICE__ - __half2 make_half2(__half x, __half y) - { - return __half2{x, y}; - } - - inline - __HOST_DEVICE__ - __half __low2half(__half2 x) - { - return __half{__half_raw{static_cast<__half2_raw>(x).data.x}}; - } - - inline - __HOST_DEVICE__ - __half __high2half(__half2 x) - { - return __half{__half_raw{static_cast<__half2_raw>(x).data.y}}; - } - - inline - __HOST_DEVICE__ - __half2 __half2half2(__half x) - { - return __half2{x, x}; - } - - inline - __HOST_DEVICE__ - __half2 __halves2half2(__half x, __half y) - { - return __half2{x, y}; - } - - inline - __HOST_DEVICE__ - __half2 __low2half2(__half2 x) - { - return __half2{ - _Float16_2{ - static_cast<__half2_raw>(x).data.x, - static_cast<__half2_raw>(x).data.x}}; - } - - inline - __HOST_DEVICE__ - __half2 __high2half2(__half2 x) - { - return __half2{ - _Float16_2{ - static_cast<__half2_raw>(x).data.y, - static_cast<__half2_raw>(x).data.y}}; - } - - inline - __HOST_DEVICE__ - __half2 __lows2half2(__half2 x, __half2 y) - { - return __half2{ - _Float16_2{ - static_cast<__half2_raw>(x).data.x, - static_cast<__half2_raw>(y).data.x}}; - } - - inline - __HOST_DEVICE__ - __half2 __highs2half2(__half2 x, __half2 y) - { - return __half2{ - _Float16_2{ - static_cast<__half2_raw>(x).data.y, - static_cast<__half2_raw>(y).data.y}}; - } - - inline - __HOST_DEVICE__ - __half2 __lowhigh2highlow(__half2 x) - { - return __half2{ - _Float16_2{ - static_cast<__half2_raw>(x).data.y, - static_cast<__half2_raw>(x).data.x}}; - } - - // Bitcasts - inline - __device__ - short __half_as_short(__half x) - { - return static_cast<__half_raw>(x).x; - } - - inline - __device__ - unsigned short __half_as_ushort(__half x) - { - return static_cast<__half_raw>(x).x; - } - - inline - __device__ - __half __short_as_half(short x) - { - __half_raw r; r.x = x; - return r; - } - - inline - __device__ - __half __ushort_as_half(unsigned short x) - { - __half_raw r; r.x = x; - return r; - } - - // float -> half | half2 - inline - __HOST_DEVICE__ - __half __float2half(float x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __HOST_DEVICE__ - __half __float2half_rn(float x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - #if !defined(__HIPCC_RTC__) - // TODO: rounding behaviour is not correct for host functions. - inline - __host__ - __half __float2half_rz(float x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __host__ - __half __float2half_rd(float x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __host__ - __half __float2half_ru(float x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - #endif - inline - __device__ - __half __float2half_rz(float x) - { - return __half_raw{__ocml_cvtrtz_f16_f32(x)}; - } - inline - __device__ - __half __float2half_rd(float x) - { - return __half_raw{__ocml_cvtrtn_f16_f32(x)}; - } - inline - __device__ - __half __float2half_ru(float x) - { - return __half_raw{__ocml_cvtrtp_f16_f32(x)}; - } - inline - __HOST_DEVICE__ - __half2 __float2half2_rn(float x) - { - return __half2{ - _Float16_2{ - static_cast<_Float16>(x), static_cast<_Float16>(x)}}; - } - inline - __HOST_DEVICE__ - __half2 __floats2half2_rn(float x, float y) - { - return __half2{_Float16_2{ - static_cast<_Float16>(x), static_cast<_Float16>(y)}}; - } - inline - __HOST_DEVICE__ - __half2 __float22half2_rn(float2 x) - { - return __floats2half2_rn(x.x, x.y); - } - - // half | half2 -> float - inline - __HOST_DEVICE__ - float __half2float(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __HOST_DEVICE__ - float __low2float(__half2 x) - { - return static_cast<__half2_raw>(x).data.x; - } - inline - __HOST_DEVICE__ - float __high2float(__half2 x) - { - return static_cast<__half2_raw>(x).data.y; - } - inline - __HOST_DEVICE__ - float2 __half22float2(__half2 x) - { - return make_float2( - static_cast<__half2_raw>(x).data.x, - static_cast<__half2_raw>(x).data.y); - } - - // half -> int - inline - __device__ - int __half2int_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - int __half2int_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - int __half2int_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - int __half2int_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // int -> half - inline - __device__ - __half __int2half_rn(int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __int2half_rz(int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __int2half_rd(int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __int2half_ru(int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // half -> short - inline - __device__ - short __half2short_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - short __half2short_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - short __half2short_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - short __half2short_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // short -> half - inline - __device__ - __half __short2half_rn(short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __short2half_rz(short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __short2half_rd(short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __short2half_ru(short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // half -> long long - inline - __device__ - long long __half2ll_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - long long __half2ll_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - long long __half2ll_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - long long __half2ll_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // long long -> half - inline - __device__ - __half __ll2half_rn(long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ll2half_rz(long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ll2half_rd(long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ll2half_ru(long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // half -> unsigned int - inline - __device__ - unsigned int __half2uint_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned int __half2uint_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned int __half2uint_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned int __half2uint_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // unsigned int -> half - inline - __device__ - __half __uint2half_rn(unsigned int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __uint2half_rz(unsigned int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __uint2half_rd(unsigned int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __uint2half_ru(unsigned int x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // half -> unsigned short - inline - __device__ - unsigned short __half2ushort_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned short __half2ushort_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned short __half2ushort_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned short __half2ushort_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // unsigned short -> half - inline - __device__ - __half __ushort2half_rn(unsigned short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ushort2half_rz(unsigned short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ushort2half_rd(unsigned short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ushort2half_ru(unsigned short x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // half -> unsigned long long - inline - __device__ - unsigned long long __half2ull_rn(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned long long __half2ull_rz(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned long long __half2ull_rd(__half x) - { - return static_cast<__half_raw>(x).data; - } - inline - __device__ - unsigned long long __half2ull_ru(__half x) - { - return static_cast<__half_raw>(x).data; - } - - // unsigned long long -> half - inline - __device__ - __half __ull2half_rn(unsigned long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ull2half_rz(unsigned long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ull2half_rd(unsigned long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - inline - __device__ - __half __ull2half_ru(unsigned long long x) - { - return __half_raw{static_cast<_Float16>(x)}; - } - - // Load primitives - inline - __device__ - __half __ldg(const __half* ptr) { return *ptr; } - inline - __device__ - __half __ldcg(const __half* ptr) { return *ptr; } - inline - __device__ - __half __ldca(const __half* ptr) { return *ptr; } - inline - __device__ - __half __ldcs(const __half* ptr) { return *ptr; } - - inline - __HOST_DEVICE__ - __half2 __ldg(const __half2* ptr) { return *ptr; } - inline - __HOST_DEVICE__ - __half2 __ldcg(const __half2* ptr) { return *ptr; } - inline - __HOST_DEVICE__ - __half2 __ldca(const __half2* ptr) { return *ptr; } - inline - __HOST_DEVICE__ - __half2 __ldcs(const __half2* ptr) { return *ptr; } - - // Relations - inline - __device__ - bool __heq(__half x, __half y) - { - return static_cast<__half_raw>(x).data == - static_cast<__half_raw>(y).data; - } - inline - __device__ - bool __hne(__half x, __half y) - { - return static_cast<__half_raw>(x).data != - static_cast<__half_raw>(y).data; - } - inline - __device__ - bool __hle(__half x, __half y) - { - return static_cast<__half_raw>(x).data <= - static_cast<__half_raw>(y).data; - } - inline - __device__ - bool __hge(__half x, __half y) - { - return static_cast<__half_raw>(x).data >= - static_cast<__half_raw>(y).data; - } - inline - __device__ - bool __hlt(__half x, __half y) - { - return static_cast<__half_raw>(x).data < - static_cast<__half_raw>(y).data; - } - inline - __device__ - bool __hgt(__half x, __half y) - { - return static_cast<__half_raw>(x).data > - static_cast<__half_raw>(y).data; - } - inline __device__ - bool __hequ(__half x, __half y) { - return !(static_cast<__half_raw>(x).data < static_cast<__half_raw>(y).data) && - !(static_cast<__half_raw>(x).data > static_cast<__half_raw>(y).data); - } - inline __device__ - bool __hneu(__half x, __half y) { - return !(static_cast<__half_raw>(x).data == static_cast<__half_raw>(y).data); - } - inline __device__ - bool __hleu(__half x, __half y) { - return !(static_cast<__half_raw>(x).data > static_cast<__half_raw>(y).data); - } - inline - __device__ - bool __hgeu(__half x, __half y) { - return !(static_cast<__half_raw>(x).data < static_cast<__half_raw>(y).data); - } - inline - __device__ - bool __hltu(__half x, __half y) { - return !(static_cast<__half_raw>(x).data >= static_cast<__half_raw>(y).data); - } - inline - __device__ - bool __hgtu(__half x, __half y) { - return !(static_cast<__half_raw>(x).data <= static_cast<__half_raw>(y).data); - } - - inline - __HOST_DEVICE__ - __half2 __heq2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data == - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hne2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data != - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hle2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data <= - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hge2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data >= - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hlt2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data < - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hgt2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(x).data > - static_cast<__half2_raw>(y).data; - return __builtin_convertvector(-r, _Float16_2); - } - inline __HOST_DEVICE__ - __half2 __hequ2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data < static_cast<__half2_raw>(y).data) && - !(static_cast<__half2_raw>(x).data > static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hneu2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data == static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hleu2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data > static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hgeu2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data < static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hltu2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data >= static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - inline - __HOST_DEVICE__ - __half2 __hgtu2(__half2 x, __half2 y) { - auto r = !(static_cast<__half2_raw>(x).data <= static_cast<__half2_raw>(y).data); - return __builtin_convertvector(-r, _Float16_2); - } - - inline - __HOST_DEVICE__ - bool __hbeq2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__heq2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hbne2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hne2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hble2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hle2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hbge2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hge2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hblt2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hlt2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hbgt2(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hgt2(x, y)); - return r.data.x != 0 && r.data.y != 0; - } - inline - __HOST_DEVICE__ - bool __hbequ2(__half2 x, __half2 y) { return __hbeq2(x, y); } - inline - __HOST_DEVICE__ - bool __hbneu2(__half2 x, __half2 y) { return __hbne2(x, y); } - inline - __HOST_DEVICE__ - bool __hbleu2(__half2 x, __half2 y) { return __hble2(x, y); } - inline - __HOST_DEVICE__ - bool __hbgeu2(__half2 x, __half2 y) { return __hbge2(x, y); } - inline - __HOST_DEVICE__ - bool __hbltu2(__half2 x, __half2 y) { return __hblt2(x, y); } - inline - __HOST_DEVICE__ - bool __hbgtu2(__half2 x, __half2 y) { return __hbgt2(x, y); } - inline - __device__ - __half __hmax(const __half x, const __half y) { - return __half_raw{__ocml_fmax_f16(static_cast<__half_raw>(x).data, - static_cast<__half_raw>(y).data)}; - } - inline - __device__ - __half __hmax_nan(const __half x, const __half y) { - if(__ocml_isnan_f16(static_cast<__half_raw>(x).data)) { - return x; - } else if (__ocml_isnan_f16(static_cast<__half_raw>(y).data)) { - return y; - } - return __hmax(x, y); - } - inline - __device__ - __half __hmin(const __half x, const __half y) { - return __half_raw{__ocml_fmin_f16(static_cast<__half_raw>(x).data, - static_cast<__half_raw>(y).data)}; - } - inline - __device__ - __half __hmin_nan(const __half x, const __half y) { - if(__ocml_isnan_f16(static_cast<__half_raw>(x).data)) { - return x; - } else if (__ocml_isnan_f16(static_cast<__half_raw>(y).data)) { - return y; - } - return __hmin(x, y); - } - - // Arithmetic - inline - __device__ - __half __clamp_01(__half x) - { - auto r = static_cast<__half_raw>(x); - - if (__hlt(x, __half_raw{0})) return __half_raw{0}; - if (__hlt(__half_raw{1}, x)) return __half_raw{1}; - return r; - } - - inline - __device__ - __half __hadd(__half x, __half y) - { - return __half_raw{ - static_cast<__half_raw>(x).data + - static_cast<__half_raw>(y).data}; - } - inline - __device__ - __half __habs(__half x) - { - return __half_raw{ - __ocml_fabs_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half __hsub(__half x, __half y) - { - return __half_raw{ - static_cast<__half_raw>(x).data - - static_cast<__half_raw>(y).data}; - } - inline - __device__ - __half __hmul(__half x, __half y) - { - return __half_raw{ - static_cast<__half_raw>(x).data * - static_cast<__half_raw>(y).data}; - } - inline - __device__ - __half __hadd_sat(__half x, __half y) - { - return __clamp_01(__hadd(x, y)); - } - inline - __device__ - __half __hsub_sat(__half x, __half y) - { - return __clamp_01(__hsub(x, y)); - } - inline - __device__ - __half __hmul_sat(__half x, __half y) - { - return __clamp_01(__hmul(x, y)); - } - inline - __device__ - __half __hfma(__half x, __half y, __half z) - { - return __half_raw{__ocml_fma_f16( - static_cast<__half_raw>(x).data, - static_cast<__half_raw>(y).data, - static_cast<__half_raw>(z).data)}; - } - inline - __device__ - __half __hfma_sat(__half x, __half y, __half z) - { - return __clamp_01(__hfma(x, y, z)); - } - inline - __device__ - __half __hdiv(__half x, __half y) - { - return __half_raw{ - static_cast<__half_raw>(x).data / - static_cast<__half_raw>(y).data}; - } - - inline - __HOST_DEVICE__ - __half2 __hadd2(__half2 x, __half2 y) - { - return __half2{ - static_cast<__half2_raw>(x).data + - static_cast<__half2_raw>(y).data}; - } - inline - __HOST_DEVICE__ - __half2 __habs2(__half2 x) - { - return __half2{ - __ocml_fabs_2f16(static_cast<__half2_raw>(x).data)}; - } - inline - __HOST_DEVICE__ - __half2 __hsub2(__half2 x, __half2 y) - { - return __half2{ - static_cast<__half2_raw>(x).data - - static_cast<__half2_raw>(y).data}; - } - inline - __HOST_DEVICE__ - __half2 __hmul2(__half2 x, __half2 y) - { - return __half2{ - static_cast<__half2_raw>(x).data * - static_cast<__half2_raw>(y).data}; - } - inline - __HOST_DEVICE__ - __half2 __hadd2_sat(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hadd2(x, y)); - return __half2{ - __clamp_01(__half_raw{r.data.x}), - __clamp_01(__half_raw{r.data.y})}; - } - inline - __HOST_DEVICE__ - __half2 __hsub2_sat(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hsub2(x, y)); - return __half2{ - __clamp_01(__half_raw{r.data.x}), - __clamp_01(__half_raw{r.data.y})}; - } - inline - __HOST_DEVICE__ - __half2 __hmul2_sat(__half2 x, __half2 y) - { - auto r = static_cast<__half2_raw>(__hmul2(x, y)); - return __half2{ - __clamp_01(__half_raw{r.data.x}), - __clamp_01(__half_raw{r.data.y})}; - } - inline - __HOST_DEVICE__ - __half2 __hfma2(__half2 x, __half2 y, __half2 z) - { - return __half2{__ocml_fma_2f16(x, y, z)}; - } - inline - __HOST_DEVICE__ - __half2 __hfma2_sat(__half2 x, __half2 y, __half2 z) - { - auto r = static_cast<__half2_raw>(__hfma2(x, y, z)); - return __half2{ - __clamp_01(__half_raw{r.data.x}), - __clamp_01(__half_raw{r.data.y})}; - } - inline - __HOST_DEVICE__ - __half2 __h2div(__half2 x, __half2 y) - { - return __half2{ - static_cast<__half2_raw>(x).data / - static_cast<__half2_raw>(y).data}; - } - - // Math functions - #if defined(__clang__) && defined(__HIP__) - inline - __device__ - float amd_mixed_dot(__half2 a, __half2 b, float c, bool saturate) { - return __ockl_fdot2(static_cast<__half2_raw>(a).data, - static_cast<__half2_raw>(b).data, - c, saturate); - } - #endif - inline - __device__ - __half htrunc(__half x) - { - return __half_raw{ - __ocml_trunc_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hceil(__half x) - { - return __half_raw{ - __ocml_ceil_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hfloor(__half x) - { - return __half_raw{ - __ocml_floor_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hrint(__half x) - { - return __half_raw{ - __ocml_rint_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hsin(__half x) - { - return __half_raw{ - __ocml_sin_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hcos(__half x) - { - return __half_raw{ - __ocml_cos_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hexp(__half x) - { - return __half_raw{ - __ocml_exp_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hexp2(__half x) - { - return __half_raw{ - __ocml_exp2_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hexp10(__half x) - { - return __half_raw{ - __ocml_exp10_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hlog2(__half x) - { - return __half_raw{ - __ocml_log2_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hlog(__half x) - { - return __half_raw{ - __ocml_log_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hlog10(__half x) - { - return __half_raw{ - __ocml_log10_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hrcp(__half x) - { - return __half_raw{ - static_cast<_Float16>(1.0f) /static_cast<__half_raw>(x).data}; - } - inline - __device__ - __half hrsqrt(__half x) - { - return __half_raw{ - __ocml_rsqrt_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - __half hsqrt(__half x) - { - return __half_raw{ - __ocml_sqrt_f16(static_cast<__half_raw>(x).data)}; - } - inline - __device__ - bool __hisinf(__half x) - { - return __ocml_isinf_f16(static_cast<__half_raw>(x).data); - } - inline - __device__ - bool __hisnan(__half x) - { - return __ocml_isnan_f16(static_cast<__half_raw>(x).data); - } - inline - __device__ - __half __hneg(__half x) - { - return __half_raw{-static_cast<__half_raw>(x).data}; - } - - inline - __HOST_DEVICE__ - __half2 h2trunc(__half2 x) - { - return __half2{__ocml_trunc_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2ceil(__half2 x) - { - return __half2{__ocml_ceil_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2floor(__half2 x) - { - return __half2{__ocml_floor_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2rint(__half2 x) - { - return __half2{__ocml_rint_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2sin(__half2 x) - { - return __half2{__ocml_sin_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2cos(__half2 x) - { - return __half2{__ocml_cos_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2exp(__half2 x) - { - return __half2{__ocml_exp_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2exp2(__half2 x) - { - return __half2{__ocml_exp2_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2exp10(__half2 x) - { - return __half2{__ocml_exp10_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2log2(__half2 x) - { - return __half2{__ocml_log2_2f16(x)}; - } - inline - __HOST_DEVICE__ - __half2 h2log(__half2 x) { return __ocml_log_2f16(x); } - inline - __HOST_DEVICE__ - __half2 h2log10(__half2 x) { return __ocml_log10_2f16(x); } - inline - __HOST_DEVICE__ - __half2 h2rcp(__half2 x) { - return _Float16_2{ - _Float16_2{static_cast<_Float16>(1.0f), static_cast<_Float16>(1.0f)} / x.data}; - } - inline - __HOST_DEVICE__ - __half2 h2rsqrt(__half2 x) { return __ocml_rsqrt_2f16(x); } - inline - __HOST_DEVICE__ - __half2 h2sqrt(__half2 x) { return __ocml_sqrt_2f16(x); } - inline - __HOST_DEVICE__ - __half2 __hisinf2(__half2 x) - { - auto r = __ocml_isinf_2f16(x); - return __half2{_Float16_2{ - static_cast<_Float16>(r.x), static_cast<_Float16>(r.y)}}; - } - inline - __HOST_DEVICE__ - __half2 __hisnan2(__half2 x) - { - auto r = __ocml_isnan_2f16(x); - return __half2{_Float16_2{ - static_cast<_Float16>(r.x), static_cast<_Float16>(r.y)}}; - } - inline - __HOST_DEVICE__ - __half2 __hneg2(__half2 x) - { - return __half2{-static_cast<__half2_raw>(x).data}; - } - } // Anonymous namespace. - - #if !defined(HIP_NO_HALF) - using half = __half; - using half2 = __half2; - #endif - __device__ - inline - __half __shfl(__half var, int src_lane, int width = warpSize) { - union { int i; __half h; } tmp; tmp.h = var; - tmp.i = __shfl(tmp.i, src_lane, width); - return tmp.h; - } - __device__ - inline - __half2 __shfl(__half2 var, int src_lane, int width = warpSize) { - union { int i; __half2 h; } tmp; tmp.h = var; - tmp.i = __shfl(tmp.i, src_lane, width); - return tmp.h; - } - __device__ - inline - __half __shfl_up(__half var, unsigned int lane_delta, int width = warpSize) { - union { int i; __half h; } tmp; tmp.h = var; - tmp.i = __shfl_up(tmp.i, lane_delta, width); - return tmp.h; - } - __device__ - inline - __half2 __shfl_up(__half2 var, unsigned int lane_delta, int width = warpSize) { - union { int i; __half2 h; } tmp; tmp.h = var; - tmp.i = __shfl_up(tmp.i, lane_delta, width); - return tmp.h; - } - __device__ - inline - __half __shfl_down(__half var, unsigned int lane_delta, int width = warpSize) { - union { int i; __half h; } tmp; tmp.h = var; - tmp.i = __shfl_down(tmp.i, lane_delta, width); - return tmp.h; - } - __device__ - inline - __half2 __shfl_down(__half2 var, unsigned int lane_delta, int width = warpSize) { - union { int i; __half2 h; } tmp; tmp.h = var; - tmp.i = __shfl_down(tmp.i, lane_delta, width); - return tmp.h; - } - __device__ - inline - __half __shfl_xor(__half var, int lane_mask, int width = warpSize) { - union { int i; __half h; } tmp; tmp.h = var; - tmp.i = __shfl_xor(tmp.i, lane_mask, width); - return tmp.h; - } - __device__ - inline - __half2 __shfl_xor(__half2 var, int lane_mask, int width = warpSize) { - union { int i; __half2 h; } tmp; tmp.h = var; - tmp.i = __shfl_xor(tmp.i, lane_mask, width); - return tmp.h; - } - #endif // defined(__cplusplus) -#elif defined(__GNUC__) - #if !defined(__HIPCC_RTC__) - #include "hip_fp16_gcc.h" - #endif -#endif // !defined(__clang__) && defined(__GNUC__) - -#endif // HIP_INCLUDE_HIP_AMD_DETAIL_HIP_FP16_H -/* -Copyright (c) 2015 - 2023 Advanced Micro Devices, Inc. All rights reserved. - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. -*/ - -#pragma once - -#if !defined(__HIPCC_RTC__) -#include "hip_fp16_math_fwd.h" -#include "amd_hip_vector_types.h" -#include "math_fwd.h" - -#include - -#include -// assert.h is only for the host version of assert. -// The device version of assert is implemented in hip/amd_detail/hip_runtime.h. -// Users should include hip_runtime.h for the device version of assert. -#if !__HIP_DEVICE_COMPILE__ -#include -#endif -#include -#include -#include -#endif // !defined(__HIPCC_RTC__) - -#if _LIBCPP_VERSION && __HIP__ -namespace std { -template <> -struct __numeric_type<_Float16> -{ - static _Float16 __test(_Float16); - - typedef _Float16 type; - static const bool value = true; -}; -} -#endif // _LIBCPP_VERSION - -#pragma push_macro("__DEVICE__") -#pragma push_macro("__RETURN_TYPE") - -#define __DEVICE__ static __device__ -#define __RETURN_TYPE bool - -// DOT FUNCTIONS -#if __HIP_CLANG_ONLY__ -__DEVICE__ -inline -int amd_mixed_dot(short2 a, short2 b, int c, bool saturate) { - return __ockl_sdot2(a.data, b.data, c, saturate); -} -__DEVICE__ -inline -uint amd_mixed_dot(ushort2 a, ushort2 b, uint c, bool saturate) { - return __ockl_udot2(a.data, b.data, c, saturate); -} -__DEVICE__ -inline -int amd_mixed_dot(char4 a, char4 b, int c, bool saturate) { - return __ockl_sdot4(a.data, b.data, c, saturate); -} -__DEVICE__ -inline -uint amd_mixed_dot(uchar4 a, uchar4 b, uint c, bool saturate) { - return __ockl_udot4(a.data, b.data, c, saturate); -} -__DEVICE__ -inline -int amd_mixed_dot(int a, int b, int c, bool saturate) { - return __ockl_sdot8(a, b, c, saturate); -} -__DEVICE__ -inline -uint amd_mixed_dot(uint a, uint b, uint c, bool saturate) { - return __ockl_udot8(a, b, c, saturate); -} -#endif - -#pragma pop_macro("__DEVICE__") -#pragma pop_macro("__RETURN_TYPE") -// For backward compatibility. -// There are HIP applications e.g. TensorFlow, expecting __HIP_ARCH_* macros -// defined after including math_functions.h. -#if !defined(__HIPCC_RTC__) -#include -#endif diff --git a/tinygrad/extra/hook_cuda.py b/tinygrad/extra/hook_cuda.py deleted file mode 100644 index 05a4e765..00000000 --- a/tinygrad/extra/hook_cuda.py +++ /dev/null @@ -1,241 +0,0 @@ -import ctypes, struct, platform, pathlib, os, binascii -from hexdump import hexdump -from tinygrad.helpers import to_mv, DEBUG, getenv -from tinygrad.runtime.autogen import libc, cuda -from tinygrad.device import CPUProgram -from tinygrad.runtime.support.elf import elf_loader -from tinygrad.runtime.ops_cuda import cu_time_execution - -def _hook(fxn_address_value, tramp): - page_address = (fxn_address_value//0x1000)*0x1000 - ret = libc.mprotect(page_address, 0x2000, 7) - assert ret == 0 - libc.memcpy(fxn_address_value, tramp, len(tramp)) - ret = libc.mprotect(page_address, 0x2000, 5) - assert ret == 0 - CPUProgram.rt_lib["__clear_cache"](fxn_address_value, fxn_address_value + len(tramp)) - -def install_hook(c_function, python_function): - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - if (processor:=platform.processor()) == "aarch64": - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - elif processor == "x86_64": - # 0x0000000000000000: 49 BB aa aa aa aa aa aa aa aa movabs r11,
- # 0x000000000000000a: 41 FF E3 jmp r11 - tramp = b"\x49\xBB" + struct.pack("Q", python_function_addr) + b"\x41\xFF\xE3" - else: - raise Exception(f"processor {processor} not supported") - tramp = ctypes.create_string_buffer(tramp) - - # get real function address - fxn_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - fxn_address_value = fxn_address.contents.value - #print(f"** hooking function at 0x{fxn_address_value}") - - orig_save = (ctypes.c_char*len(tramp))() - libc.memcpy(orig_save, fxn_address_value, len(tramp)) - _hook(fxn_address_value, tramp) - - def original(*args): - _hook(fxn_address_value, orig_save) - ret = c_function(*args) - _hook(fxn_address_value, tramp) - return ret - return original - -hooked = {} - -allocated_memory = {} -function_names = {} - -seen_modules = set() - -@ctypes.CFUNCTYPE(ctypes.c_int) -def dummy(): - print("**** dummy function hook ****") - return -1 - -@ctypes.CFUNCTYPE(*([cuda.cuInit.restype] + cuda.cuInit.argtypes)) -def cuInit(flags): - print("call cuInit", flags) - return hooked["cuInit"](flags) - -@ctypes.CFUNCTYPE(*([cuda.cuMemHostAlloc.restype] + cuda.cuMemHostAlloc.argtypes)) -def cuMemHostAlloc(pp, bytesize, flags): - print(f"cuMemHostAlloc {bytesize}") - return hooked["cuMemHostAlloc"](pp, bytesize, flags) - -@ctypes.CFUNCTYPE(*([cuda.cuModuleLoadData.restype] + cuda.cuModuleLoadData.argtypes)) -def cuModuleLoadData(module, image): - ret = hooked["cuModuleLoadData"](module, image) - module_address = ctypes.addressof(module.contents.contents) - print(f"cuModuleLoadData 0x{image:x} -> 0x{module_address:X}") - seen_modules.add(module_address) - - #images, sections, relocs = elf_loader(bytes(to_mv(image, 0x100000))) - #for s in sections: print(s) - - #print('\n'.join([x for x in maps.split("\n") if 'libcuda' in x])) - - #hexdump(to_mv(image, 0x1000)) - #image, sections, relocs = elf_loader(to_mv(image)) - #print(sections) - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuModuleGetFunction.restype] + cuda.cuModuleGetFunction.argtypes)) -def cuModuleGetFunction(hfunc, hmod, name): - ret = hooked["cuModuleGetFunction"](hfunc, hmod, name) - python_name = ctypes.string_at(name).decode() - - # pip install git+https://github.com/wbenny/pydemangler.git - import pydemangler - demangled_name = pydemangler.demangle(python_name) - if demangled_name is not None: python_name = demangled_name - - print(f"called cuModuleGetFunction 0x{ctypes.addressof(hmod.contents):X} {python_name}") - function_names[ctypes.addressof(hfunc.contents.contents)] = python_name - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuMemAlloc_v2.restype] + cuda.cuMemAlloc_v2.argtypes)) -def cuMemAlloc_v2(dptr, bytesize): - ret = hooked["cuMemAlloc_v2"](dptr, bytesize) - cuda_address = ctypes.addressof(dptr.contents) - allocated_memory[cuda_address] = bytesize - print(f"cuMemAlloc_v2 {bytesize} 0x{cuda_address:X}") - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuLaunchKernel.restype] + cuda.cuLaunchKernel.argtypes)) -def cuLaunchKernel(f, gridDimX, gridDimY, gridDimZ, blockDimX, blockDimY, blockDimZ, sharedMemBytes, hStream, kernelParams, extra): - tm = cu_time_execution(lambda: - hooked["cuLaunchKernel"](f, gridDimX, gridDimY, gridDimZ, blockDimX, blockDimY, blockDimZ, sharedMemBytes, hStream, kernelParams, extra), True) - - name = function_names[ctypes.addressof(f.contents)] - print(f"{tm*1e6:9.2f} us -- cuLaunchKernel <<{gridDimX:6d}, {gridDimY:5d}, {gridDimZ:5d}>>", - f"<<{blockDimX:4d}, {blockDimY:4d}, {blockDimZ:4d}>> {sharedMemBytes} {name}") - - if extra: hexdump(to_mv(extra, 0x100)) - - if getenv("PARAMS") and kernelParams: - #print(f"params @ 0x{ctypes.addressof(kernelParams.contents):X}") - params = [] - while True: - ret = cuda.cuFuncGetParamInfo(f, len(params), ctypes.byref(paramOffset:=ctypes.c_size_t()), ctypes.byref(paramSize:=ctypes.c_size_t())) - if ret != 0: break - params.append((paramOffset.value, paramSize.value)) - #params_dat = to_mv(kernelParams.contents, params[-1][0] + params[-1][1]) - params_ptr = to_mv(kernelParams, len(params)*8).cast("Q") - #params_dat = to_mv(kernelParams.contents, params[-1][0] + params[-1][1]) - for i,(off,sz) in enumerate(params): - hexdump(to_mv(params_ptr[i], sz)) - - - #hexdump(params_dat) - #for i,(off,sz) in enumerate(params): - # print(f"{i}: offset:{off:3d} size:{sz:3d}") # --", binascii.hexlify(dat).decode()) - # hexdump(params_dat[off:off+sz]) - #if name == "exp2_kernel_vectorized4_kernel": - # ptr_0 = struct.unpack("Q", params_dat[0x10:0x18])[0] - # hexdump(to_mv(ptr_0, 0x80)) - #ptr_1 = struct.unpack("Q", to_mv(ptr_0, 8))[0] - - #print(f"params 0x{ctypes.addressof(kernelParams):X}") - #hexdump(to_mv(kernelParams, 0x100)) - #print(f"data 0x{to_mv(kernelParams, 8).cast('Q')[0]:X}") - #hexdump(to_mv(kernelParams.contents, 0x80)) - #for i,addr in enumerate(to_mv(kernelParams.contents, 0x100).cast("Q")): print(f"{i*8:3d}: {addr:X}") - - return 0 - -if __name__ == "__main__": - #out = cuda.CUmoduleLoadingMode() - #print(cuda.cuModuleGetLoadingMode(ctypes.byref(out))) - #print(out.value) - - hooked['cuInit'] = install_hook(cuda.cuInit, cuInit) - hooked['cuModuleGetFunction'] = install_hook(cuda.cuModuleGetFunction, cuModuleGetFunction) - hooked['cuLaunchKernel'] = install_hook(cuda.cuLaunchKernel, cuLaunchKernel) - - # memory stuff - hooked['cuMemAlloc_v2'] = install_hook(cuda.cuMemAlloc_v2, cuMemAlloc_v2) - hooked['cuMemHostAlloc'] = install_hook(cuda.cuMemHostAlloc, cuMemHostAlloc) - - # module loading + not used module loading - hooked['cuModuleLoadData'] = install_hook(cuda.cuModuleLoadData, cuModuleLoadData) - install_hook(cuda.cuModuleLoad, dummy) - install_hook(cuda.cuModuleLoadDataEx, dummy) - install_hook(cuda.cuModuleLoadFatBinary, dummy) - - # library stuff (doesn't seem used) - #install_hook(cuda.cuLibraryLoadData, dummy) - #install_hook(cuda.cuLibraryLoadFromFile, dummy) - #install_hook(cuda.cuLibraryGetModule, dummy) - - #install_hook(cuda.cuMemAllocManaged, dummy) - - # unused - #install_hook(cuda.cuFuncGetModule, dummy) - #install_hook(cuda.cuModuleGetGlobal_v2, dummy) - - # hook v1 - #install_hook(cuda._libraries['libcuda.so'].cuModuleGetGlobal, dummy) - #install_hook(cuda._libraries['libcuda.so'].cuMemAlloc, dummy) - #install_hook(cuda._libraries['libcuda.so'].cuLinkComplete, dummy) - - #nvjitlink = ctypes.CDLL("/home/tiny/.local/lib/python3.10/site-packages/nvidia/nvjitlink/lib/libnvJitLink.so.12") - #install_hook(nvjitlink.nvJitLinkCreate, dummy) - #nvrtc = ctypes.CDLL("/home/tiny/.local/lib/python3.10/site-packages/nvidia/cuda_nvrtc/lib/libnvrtc.so.11.2") - #nvrtc = ctypes.CDLL("/usr/local/cuda-12.4/targets/x86_64-linux/lib/libnvrtc.so.12.4.127") - #from tinygrad.runtime.autogen import nvrtc - #install_hook(nvrtc.nvrtcCreateProgram, dummy) - #install_hook(nvrtc.nvJitLinkCreate, dummy) - - #import tinygrad.runtime.autogen.nvrtc as nvrtc - #install_hook(nvrtc.nvJitLinkCreate, dummy) - #install_hook(nvrtc.nvrtcCreateProgram, dummy) - - #hooked['cuLinkCreate'] = install_hook(cuda.cuLinkCreate, dummy) - - if getenv("TINYGRAD"): - from tinygrad import Tensor - (Tensor.zeros(6, device="CUDA").contiguous()*2).realize() - exit(0) - - print("importing torch...") - import torch - print("torch", torch.__version__, torch.__file__) - - if getenv("RESNET"): - import torchvision.models as models - model = models.resnet18(pretrained=True) - model = model.cuda() - model.eval() - - if getenv("COMPILE"): model = torch.compile(model) - - X = torch.rand(getenv("BS", 1), 3, 288, 288, device='cuda') - model(X) - - print("\n\n\n****** second run ******\n") - model(X) - else: - a = torch.zeros(4, 4).cuda() - b = torch.zeros(4, 4).cuda() - print("tensor created") - print(f"a: 0x{a.data_ptr():X}") - print(f"b: 0x{b.data_ptr():X}") - a += 1 - b += 2 - a = a.exp2() - b = b.exp2() - a += b - #c = a @ b - print("tensor math done", a.cpu().numpy()) - - # confirm cuda library is right - #maps = pathlib.Path("/proc/self/maps").read_text() - #print('\n'.join([x for x in maps.split("\n") if 'cuda' in x or 'nv' in x])) diff --git a/tinygrad/extra/huggingface_onnx/collect_metadata.py b/tinygrad/extra/huggingface_onnx/collect_metadata.py deleted file mode 100644 index 0a3d1eda..00000000 --- a/tinygrad/extra/huggingface_onnx/collect_metadata.py +++ /dev/null @@ -1,85 +0,0 @@ -import yaml, time, requests, argparse -from pathlib import Path -from huggingface_hub import list_models, HfApi -from tinygrad.helpers import tqdm - -HUGGINGFACE_URL = "https://huggingface.co" -SKIPPED_FILES = [ - "fp16", "int8", "uint8", "quantized", # numerical accuracy issues - "avx2", "arm64", "avx512", "avx512_vnni", # numerical accuracy issues - "q4", "q4f16", "bnb4", # unimplemented quantization - "model_O4", # requires non cpu ort runner and MemcpyFromHost op - "merged", # TODO implement attribute with graph type and Loop op -] -SKIPPED_REPO_PATHS = [ - # Invalid model-index - "AdamCodd/vit-base-nsfw-detector", - # TODO: implement attribute with graph type and Loop op - "minishlab/potion-base-8M", "minishlab/M2V_base_output", "minishlab/potion-retrieval-32M", - # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, GroupQueryAttention - "HuggingFaceTB/SmolLM2-360M-Instruct", - # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, RotaryEmbedding, MultiHeadAttention - "HuggingFaceTB/SmolLM2-1.7B-Instruct", - # TODO: implmement RandomNormalLike - "stabilityai/stable-diffusion-xl-base-1.0", "stabilityai/sdxl-turbo", 'SimianLuo/LCM_Dreamshaper_v7', - # TODO: implement NonZero - "mangoapps/fb_zeroshot_mnli_onnx", - # TODO huge Concat in here with 1024 (1, 3, 32, 32) Tensors, and maybe a MOD bug with const folding - "briaai/RMBG-2.0", -] - -def get_top_repos(n: int, sort: str) -> list[str]: # list["FacebookAI/xlm-roberta-large", ...] - print(f"** Getting top {n} models sorted by {sort} **") - repos = [] - i = 0 - for model in list_models(filter="onnx", sort=sort): - if model.id in SKIPPED_REPO_PATHS: continue - print(f"{i+1}/{n}: {model.id} ({getattr(model, sort)})") - repos.append(model.id) - i += 1 - if i == n: break - return repos - -def get_metadata(repos:list[str]) -> dict: - api = HfApi() - repos_metadata = {"repositories": {}} - total_size = 0 - - # TODO: speed head requests up with async? - for repo in tqdm(repos, desc="Getting metadata"): - files_metadata = [] - model_info = api.model_info(repo) - - for file in model_info.siblings: - filename = file.rfilename - if not (filename.endswith('.onnx') or filename.endswith('.onnx_data')): continue - if any(skip_str in filename for skip_str in SKIPPED_FILES): continue - head = requests.head(f"{HUGGINGFACE_URL}/{repo}/resolve/main/{filename}", allow_redirects=True) - file_size = file.size or int(head.headers.get('Content-Length', 0)) - files_metadata.append({"file": filename, "size": f"{file_size/1e6:.2f}MB"}) - total_size += file_size - - repos_metadata["repositories"][repo] = { - "url": f"{HUGGINGFACE_URL}/{repo}", - "download_path": None, - "files": files_metadata, - } - repos_metadata['total_size'] = f"{total_size/1e9:.2f}GB" - repos_metadata['created_at'] = time.strftime("%Y-%m-%dT%H:%M:%SZ", time.gmtime()) - return repos_metadata - -if __name__ == "__main__": - sort = "downloads" # recent 30 days downloads - huggingface_onnx_dir = Path(__file__).parent - - parser = argparse.ArgumentParser(description="Produces a YAML file with metadata of top huggingface onnx models") - parser.add_argument("--limit", type=int, required=True, help="Number of top repositories to process (e.g., 100)") - parser.add_argument("--output", type=str, default="huggingface_repos.yaml", help="Output YAML file name to save the report") - args = parser.parse_args() - - top_repos = get_top_repos(args.limit, sort) - metadata = get_metadata(top_repos) - yaml_path = huggingface_onnx_dir / args.output - with open(yaml_path, 'w') as f: - yaml.dump(metadata, f, sort_keys=False) - print(f"YAML saved to: {str(yaml_path)}") diff --git a/tinygrad/extra/huggingface_onnx/download_models.py b/tinygrad/extra/huggingface_onnx/download_models.py deleted file mode 100644 index e79e0e85..00000000 --- a/tinygrad/extra/huggingface_onnx/download_models.py +++ /dev/null @@ -1,29 +0,0 @@ -import yaml, argparse -from pathlib import Path -from huggingface_hub import snapshot_download - -def download_models(yaml_file: str, download_dir: str) -> None: - with open(yaml_file, 'r') as f: metadata = yaml.safe_load(f) - n = len(metadata["repositories"]) - - for i, (model_id, model_data) in enumerate(metadata["repositories"].items()): - print(f"Downloading {i+1}/{n}: {model_id}...") - allow_patterns = [file_info["file"] for file_info in model_data["files"]] - root_path = Path(snapshot_download(repo_id=model_id, allow_patterns=allow_patterns, cache_dir=download_dir)) - # download configs too (the sizes are small) - snapshot_download(repo_id=model_id, allow_patterns=["*config.json"], cache_dir=download_dir) - print(f"Downloaded model files to: {root_path}") - model_data["download_path"] = str(root_path) - - # Save the updated metadata back to the YAML file - with open(yaml_file, 'w') as f: yaml.dump(metadata, f, sort_keys=False) - print("Download completed according to YAML file.") - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Download models from Huggingface Hub based on a YAML configuration file.") - parser.add_argument("input", type=str, help="Path to the input YAML configuration file containing model information.") - args = parser.parse_args() - - models_folder = Path(__file__).parent / "models" - models_folder.mkdir(parents=True, exist_ok=True) - download_models(args.input, str(models_folder)) \ No newline at end of file diff --git a/tinygrad/extra/huggingface_onnx/run_models.py b/tinygrad/extra/huggingface_onnx/run_models.py deleted file mode 100644 index af920f8c..00000000 --- a/tinygrad/extra/huggingface_onnx/run_models.py +++ /dev/null @@ -1,137 +0,0 @@ -import onnx, yaml, tempfile, time, collections, pprint, argparse, json -from pathlib import Path -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from extra.onnx import get_onnx_ops -from extra.onnx_helpers import validate, get_example_inputs - -def get_config(root_path: Path): - ret = {} - for path in root_path.rglob("*config.json"): - config = json.load(path.open()) - if isinstance(config, dict): - ret.update(config) - return ret - -def run_huggingface_validate(onnx_model_path, config, rtol, atol): - onnx_model = onnx_load(onnx_model_path) - onnx_runner = OnnxRunner(onnx_model) - inputs = get_example_inputs(onnx_runner.graph_inputs, config) - validate(onnx_model_path, inputs, rtol=rtol, atol=atol) - -def get_tolerances(file_name): # -> rtol, atol - # TODO very high rtol atol - if "fp16" in file_name: return 9e-2, 9e-2 - if any(q in file_name for q in ["int8", "uint8", "quantized"]): return 4, 4 - return 4e-3, 3e-2 - -def validate_repos(models:dict[str, tuple[Path, Path]]): - print(f"** Validating {len(model_paths)} models **") - for model_id, (root_path, relative_path) in models.items(): - print(f"validating model {model_id}") - model_path = root_path / relative_path - onnx_file_name = model_path.stem - config = get_config(root_path) - rtol, atol = get_tolerances(onnx_file_name) - st = time.time() - run_huggingface_validate(model_path, config, rtol, atol) - et = time.time() - st - print(f"passed, took {et:.2f}s") - -def retrieve_op_stats(models:dict[str, tuple[Path, Path]]) -> dict: - ret = {} - op_counter = collections.Counter() - unsupported_ops = collections.defaultdict(set) - supported_ops = get_onnx_ops() - print(f"** Retrieving stats from {len(model_paths)} models **") - for model_id, (root_path, relative_path) in models.items(): - print(f"examining {model_id}") - model_path = root_path / relative_path - onnx_runner = OnnxRunner(onnx.load(model_path)) - for node in onnx_runner.graph_nodes: - op_counter[node.op] += 1 - if node.op not in supported_ops: - unsupported_ops[node.op].add(model_id) - del onnx_runner - ret["unsupported_ops"] = {k:list(v) for k, v in unsupported_ops.items()} - ret["op_counter"] = op_counter.most_common() - return ret - -def debug_run(model_path, truncate, config, rtol, atol): - if truncate != -1: - model = onnx.load(model_path) - nodes_up_to_limit = list(model.graph.node)[:truncate + 1] - new_output_values = [onnx.helper.make_empty_tensor_value_info(output_name) for output_name in nodes_up_to_limit[-1].output] - model.graph.ClearField("node") - model.graph.node.extend(nodes_up_to_limit) - model.graph.ClearField("output") - model.graph.output.extend(new_output_values) - with tempfile.NamedTemporaryFile(suffix=model_path.suffix) as tmp: - onnx.save(model, tmp.name) - run_huggingface_validate(tmp.name, config, rtol, atol) - else: - run_huggingface_validate(model_path, config, rtol, atol) - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Huggingface ONNX Model Validator and Ops Checker") - parser.add_argument("input", type=str, help="Path to the input YAML configuration file containing model information.") - parser.add_argument("--check_ops", action="store_true", default=False, - help="Check support for ONNX operations in models from the YAML file") - parser.add_argument("--validate", action="store_true", default=False, - help="Validate correctness of models from the YAML file") - parser.add_argument("--debug", type=str, default="", - help="""Validates without explicitly needing a YAML or models pre-installed. - provide repo id (e.g. "minishlab/potion-base-8M") to validate all onnx models inside the repo - provide onnx model path (e.g. "minishlab/potion-base-8M/onnx/model.onnx") to validate only that one model - """) - parser.add_argument("--truncate", type=int, default=-1, help="Truncate the ONNX model so intermediate results can be validated") - args = parser.parse_args() - - if not (args.check_ops or args.validate or args.debug): - parser.error("Please provide either --validate, --check_ops, or --debug.") - if args.truncate != -1 and not args.debug: - parser.error("--truncate and --debug should be used together for debugging") - - if args.check_ops or args.validate: - with open(args.input, 'r') as f: - data = yaml.safe_load(f) - assert all(repo["download_path"] is not None for repo in data["repositories"].values()), "please run `download_models.py` for this yaml" - model_paths = { - model_id + "/" + model["file"]: (Path(repo["download_path"]), Path(model["file"])) - for model_id, repo in data["repositories"].items() - for model in repo["files"] - if model["file"].endswith(".onnx") - } - - if args.check_ops: - pprint.pprint(retrieve_op_stats(model_paths)) - - if args.validate: - validate_repos(model_paths) - - if args.debug: - from huggingface_hub import snapshot_download - download_dir = Path(__file__).parent / "models" - path:list[str] = args.debug.split("/") - if len(path) == 2: - # repo id - # validates all onnx models inside repo - repo_id = "/".join(path) - root_path = Path(snapshot_download(repo_id=repo_id, allow_patterns=["*.onnx", "*.onnx_data"], cache_dir=download_dir)) - snapshot_download(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=download_dir) - config = get_config(root_path) - for onnx_model in root_path.rglob("*.onnx"): - rtol, atol = get_tolerances(onnx_model.name) - print(f"validating {onnx_model.relative_to(root_path)} with truncate={args.truncate}, {rtol=}, {atol=}") - debug_run(onnx_model, -1, config, rtol, atol) - else: - # model id - # only validate the specified onnx model - onnx_model = path[-1] - assert path[-1].endswith(".onnx") - repo_id, relative_path = "/".join(path[:2]), "/".join(path[2:]) - root_path = Path(snapshot_download(repo_id=repo_id, allow_patterns=[relative_path], cache_dir=download_dir)) - snapshot_download(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=download_dir) - config = get_config(root_path) - rtol, atol = get_tolerances(onnx_model) - print(f"validating {relative_path} with truncate={args.truncate}, {rtol=}, {atol=}") - debug_run(root_path / relative_path, args.truncate, config, rtol, atol) \ No newline at end of file diff --git a/tinygrad/extra/introspection.py b/tinygrad/extra/introspection.py deleted file mode 100644 index 06865147..00000000 --- a/tinygrad/extra/introspection.py +++ /dev/null @@ -1,49 +0,0 @@ -import gc -from tinygrad.helpers import prod -from tinygrad.uop.ops import UOp -from tinygrad.device import Buffer -from tinygrad import Tensor, GlobalCounters - -def print_objects(): - #gc.collect() - tensors = [x for x in gc.get_objects() if isinstance(x, Tensor)] - tensor_ram_used = sum([prod(x.shape)*4 for x in tensors]) - lazybuffers = [x for x in gc.get_objects() if isinstance(x, UOp)] - gpubuffers = [x for x in gc.get_objects() if isinstance(x, Buffer) and hasattr(x, "_buf")] - realized_buffers = [x.realized for x in lazybuffers if x.base == x and x.realized] - gpubuffers_orphaned = [x for x in gpubuffers if x not in realized_buffers] - - print(f"{len(tensors)} tensors allocated in {tensor_ram_used/1e9:.2f} GB, GPU using {GlobalCounters.mem_used/1e9:.2f} GB") - print(f"{len(lazybuffers)} lazybuffers {len(realized_buffers)} realized, {len(gpubuffers)} GPU buffers") - print(f"{len(gpubuffers_orphaned)} GPU buffers are orphaned") - - cnt = 0 - for tb in gpubuffers_orphaned: - bb = gc.get_referrers(tb) - for b in bb: - if b is not gpubuffers and b is not gpubuffers_orphaned: - print(tb, "\nreference", type(b), str(b)[0:150]) - for x in gc.get_referrers(b): - print("double reference", str(x)[0:100]) - print("\n") - if cnt == 10: - break - cnt += 1 - - for x in gpubuffers_orphaned: - if getattr(x, '_buf', None): del x._buf - if getattr(x, '_image', None): del x._image - - return len(gpubuffers_orphaned) - -""" -import gc - -def print_ram(): - print(GlobalCounters.mem_used/1e9, sum([prod(x.shape)*4 for x in gc.get_objects() if isinstance(x, Tensor)])/1e9) - img_count = sum([x.is_image() for x in gc.get_objects() if isinstance(x, OpenCLBuffer)]) - print("img_count", img_count) - buffer_bytes = sum([x.cl.size for x in gc.get_objects() if isinstance(x, CLBuffer)]) - image_bytes = sum([x.cl.row_pitch*x.cl.height for x in gc.get_objects() if isinstance(x, CLImage)]) - print("buffer bytes", buffer_bytes/1e9, "image bytes", image_bytes/1e9, "sum", (buffer_bytes+image_bytes)/1e9) -""" diff --git a/tinygrad/extra/junk/sentencepiece_model_pb2.py b/tinygrad/extra/junk/sentencepiece_model_pb2.py deleted file mode 100644 index 5de978fa..00000000 --- a/tinygrad/extra/junk/sentencepiece_model_pb2.py +++ /dev/null @@ -1,45 +0,0 @@ -# -*- coding: utf-8 -*- -# Generated by the protocol buffer compiler. DO NOT EDIT! -# source: sentencepiece_model.proto -# Protobuf Python Version: 4.25.1 -"""Generated protocol buffer code.""" -from google.protobuf import descriptor as _descriptor -from google.protobuf import descriptor_pool as _descriptor_pool -from google.protobuf import symbol_database as _symbol_database -from google.protobuf.internal import builder as _builder -# @@protoc_insertion_point(imports) - -_sym_db = _symbol_database.Default() - - - - -DESCRIPTOR = _descriptor_pool.Default().AddSerializedFile(b'\n\x19sentencepiece_model.proto\x12\rsentencepiece\"\x80\x0c\n\x0bTrainerSpec\x12\r\n\x05input\x18\x01 \x03(\t\x12\x14\n\x0cinput_format\x18\x07 \x01(\t\x12\x14\n\x0cmodel_prefix\x18\x02 \x01(\t\x12\x41\n\nmodel_type\x18\x03 \x01(\x0e\x32$.sentencepiece.TrainerSpec.ModelType:\x07UNIGRAM\x12\x18\n\nvocab_size\x18\x04 \x01(\x05:\x04\x38\x30\x30\x30\x12\x17\n\x0f\x61\x63\x63\x65pt_language\x18\x05 \x03(\t\x12 \n\x15self_test_sample_size\x18\x06 \x01(\x05:\x01\x30\x12*\n\x1b\x65nable_differential_privacy\x18\x32 \x01(\x08:\x05\x66\x61lse\x12+\n differential_privacy_noise_level\x18\x33 \x01(\x02:\x01\x30\x12\x32\n\'differential_privacy_clipping_threshold\x18\x34 \x01(\x04:\x01\x30\x12\"\n\x12\x63haracter_coverage\x18\n \x01(\x02:\x06\x30.9995\x12\x1e\n\x13input_sentence_size\x18\x0b \x01(\x04:\x01\x30\x12$\n\x16shuffle_input_sentence\x18\x13 \x01(\x08:\x04true\x12 \n\x14mining_sentence_size\x18\x0c \x01(\x05\x42\x02\x18\x01\x12\"\n\x16training_sentence_size\x18\r \x01(\x05\x42\x02\x18\x01\x12(\n\x17seed_sentencepiece_size\x18\x0e \x01(\x05:\x07\x31\x30\x30\x30\x30\x30\x30\x12\x1e\n\x10shrinking_factor\x18\x0f \x01(\x02:\x04\x30.75\x12!\n\x13max_sentence_length\x18\x12 \x01(\x05:\x04\x34\x31\x39\x32\x12\x17\n\x0bnum_threads\x18\x10 \x01(\x05:\x02\x31\x36\x12\x1d\n\x12num_sub_iterations\x18\x11 \x01(\x05:\x01\x32\x12$\n\x18max_sentencepiece_length\x18\x14 \x01(\x05:\x02\x31\x36\x12%\n\x17split_by_unicode_script\x18\x15 \x01(\x08:\x04true\x12\x1d\n\x0fsplit_by_number\x18\x17 \x01(\x08:\x04true\x12!\n\x13split_by_whitespace\x18\x16 \x01(\x08:\x04true\x12)\n\x1atreat_whitespace_as_suffix\x18\x18 \x01(\x08:\x05\x66\x61lse\x12+\n\x1c\x61llow_whitespace_only_pieces\x18\x1a \x01(\x08:\x05\x66\x61lse\x12\x1b\n\x0csplit_digits\x18\x19 \x01(\x08:\x05\x66\x61lse\x12#\n\x19pretokenization_delimiter\x18\x35 \x01(\t:\x00\x12\x17\n\x0f\x63ontrol_symbols\x18\x1e \x03(\t\x12\x1c\n\x14user_defined_symbols\x18\x1f \x03(\t\x12\x16\n\x0erequired_chars\x18$ \x01(\t\x12\x1c\n\rbyte_fallback\x18# \x01(\x08:\x05\x66\x61lse\x12+\n\x1dvocabulary_output_piece_score\x18 \x01(\x08:\x04true\x12\x1e\n\x10hard_vocab_limit\x18! \x01(\x08:\x04true\x12\x1c\n\ruse_all_vocab\x18\" \x01(\x08:\x05\x66\x61lse\x12\x11\n\x06unk_id\x18( \x01(\x05:\x01\x30\x12\x11\n\x06\x62os_id\x18) \x01(\x05:\x01\x31\x12\x11\n\x06\x65os_id\x18* \x01(\x05:\x01\x32\x12\x12\n\x06pad_id\x18+ \x01(\x05:\x02-1\x12\x18\n\tunk_piece\x18- \x01(\t:\x05\x12\x16\n\tbos_piece\x18. \x01(\t:\x03\x12\x17\n\teos_piece\x18/ \x01(\t:\x04\x12\x18\n\tpad_piece\x18\x30 \x01(\t:\x05\x12\x1a\n\x0bunk_surface\x18, \x01(\t:\x05 \xe2\x81\x87 \x12+\n\x1ctrain_extremely_large_corpus\x18\x31 \x01(\x08:\x05\x66\x61lse\"5\n\tModelType\x12\x0b\n\x07UNIGRAM\x10\x01\x12\x07\n\x03\x42PE\x10\x02\x12\x08\n\x04WORD\x10\x03\x12\x08\n\x04\x43HAR\x10\x04*\t\x08\xc8\x01\x10\x80\x80\x80\x80\x02\"\xd1\x01\n\x0eNormalizerSpec\x12\x0c\n\x04name\x18\x01 \x01(\t\x12\x1c\n\x14precompiled_charsmap\x18\x02 \x01(\x0c\x12\x1e\n\x10\x61\x64\x64_dummy_prefix\x18\x03 \x01(\x08:\x04true\x12&\n\x18remove_extra_whitespaces\x18\x04 \x01(\x08:\x04true\x12 \n\x12\x65scape_whitespaces\x18\x05 \x01(\x08:\x04true\x12\x1e\n\x16normalization_rule_tsv\x18\x06 \x01(\t*\t\x08\xc8\x01\x10\x80\x80\x80\x80\x02\"y\n\x0cSelfTestData\x12\x33\n\x07samples\x18\x01 \x03(\x0b\x32\".sentencepiece.SelfTestData.Sample\x1a)\n\x06Sample\x12\r\n\x05input\x18\x01 \x01(\t\x12\x10\n\x08\x65xpected\x18\x02 \x01(\t*\t\x08\xc8\x01\x10\x80\x80\x80\x80\x02\"\xfe\x03\n\nModelProto\x12\x37\n\x06pieces\x18\x01 \x03(\x0b\x32\'.sentencepiece.ModelProto.SentencePiece\x12\x30\n\x0ctrainer_spec\x18\x02 \x01(\x0b\x32\x1a.sentencepiece.TrainerSpec\x12\x36\n\x0fnormalizer_spec\x18\x03 \x01(\x0b\x32\x1d.sentencepiece.NormalizerSpec\x12\x33\n\x0eself_test_data\x18\x04 \x01(\x0b\x32\x1b.sentencepiece.SelfTestData\x12\x38\n\x11\x64\x65normalizer_spec\x18\x05 \x01(\x0b\x32\x1d.sentencepiece.NormalizerSpec\x1a\xd2\x01\n\rSentencePiece\x12\r\n\x05piece\x18\x01 \x01(\t\x12\r\n\x05score\x18\x02 \x01(\x02\x12\x42\n\x04type\x18\x03 \x01(\x0e\x32,.sentencepiece.ModelProto.SentencePiece.Type:\x06NORMAL\"T\n\x04Type\x12\n\n\x06NORMAL\x10\x01\x12\x0b\n\x07UNKNOWN\x10\x02\x12\x0b\n\x07\x43ONTROL\x10\x03\x12\x10\n\x0cUSER_DEFINED\x10\x04\x12\x08\n\x04\x42YTE\x10\x06\x12\n\n\x06UNUSED\x10\x05*\t\x08\xc8\x01\x10\x80\x80\x80\x80\x02*\t\x08\xc8\x01\x10\x80\x80\x80\x80\x02\x42\x02H\x03') - -_globals = globals() -_builder.BuildMessageAndEnumDescriptors(DESCRIPTOR, _globals) -_builder.BuildTopDescriptorsAndMessages(DESCRIPTOR, 'sentencepiece_model_pb2', _globals) -if _descriptor._USE_C_DESCRIPTORS == False: - _globals['DESCRIPTOR']._options = None - _globals['DESCRIPTOR']._serialized_options = b'H\003' - _globals['_TRAINERSPEC'].fields_by_name['mining_sentence_size']._options = None - _globals['_TRAINERSPEC'].fields_by_name['mining_sentence_size']._serialized_options = b'\030\001' - _globals['_TRAINERSPEC'].fields_by_name['training_sentence_size']._options = None - _globals['_TRAINERSPEC'].fields_by_name['training_sentence_size']._serialized_options = b'\030\001' - _globals['_TRAINERSPEC']._serialized_start=45 - _globals['_TRAINERSPEC']._serialized_end=1581 - _globals['_TRAINERSPEC_MODELTYPE']._serialized_start=1517 - _globals['_TRAINERSPEC_MODELTYPE']._serialized_end=1570 - _globals['_NORMALIZERSPEC']._serialized_start=1584 - _globals['_NORMALIZERSPEC']._serialized_end=1793 - _globals['_SELFTESTDATA']._serialized_start=1795 - _globals['_SELFTESTDATA']._serialized_end=1916 - _globals['_SELFTESTDATA_SAMPLE']._serialized_start=1864 - _globals['_SELFTESTDATA_SAMPLE']._serialized_end=1905 - _globals['_MODELPROTO']._serialized_start=1919 - _globals['_MODELPROTO']._serialized_end=2429 - _globals['_MODELPROTO_SENTENCEPIECE']._serialized_start=2208 - _globals['_MODELPROTO_SENTENCEPIECE']._serialized_end=2418 - _globals['_MODELPROTO_SENTENCEPIECE_TYPE']._serialized_start=2323 - _globals['_MODELPROTO_SENTENCEPIECE_TYPE']._serialized_end=2407 -# @@protoc_insertion_point(module_scope) diff --git a/tinygrad/extra/lr_scheduler.py b/tinygrad/extra/lr_scheduler.py deleted file mode 100644 index 87ff077a..00000000 --- a/tinygrad/extra/lr_scheduler.py +++ /dev/null @@ -1,91 +0,0 @@ -import math -from typing import List -from tinygrad.nn.optim import Optimizer -from tinygrad.tensor import Tensor - -class LR_Scheduler: - def __init__(self, optimizer: Optimizer): - self.optimizer = optimizer - self.epoch_counter = Tensor([0], requires_grad=False, device=self.optimizer.device) - - def get_lr(self): pass - - def schedule_step(self) -> list[Tensor]: return [self.epoch_counter.assign(self.epoch_counter + 1), self.optimizer.lr.assign(self.get_lr())] - def step(self) -> None: Tensor.realize(*self.schedule_step()) - -class LRSchedulerGroup: - def __init__(self, *schedulers: LR_Scheduler): self.schedulers = schedulers - def step(self) -> None: - for s in self.schedulers: s.step() - -class MultiStepLR(LR_Scheduler): - def __init__(self, optimizer: Optimizer, milestones: List[int], gamma=0.1): - super().__init__(optimizer) - self.milestones = milestones - self.gamma = gamma - - def get_lr(self) -> Tensor: - if self.epoch_counter.numpy()[0] not in self.milestones: - return self.optimizer.lr - return self.optimizer.lr * self.gamma - -class ReduceLROnPlateau(LR_Scheduler): - def __init__(self, optimizer: Optimizer, mode="min", factor=0.1, patience=10, threshold=1e-4, threshold_mode="rel"): - assert mode in ["min", "max"] and threshold_mode in ["rel", "abs"] - super().__init__(optimizer) - self.mode, self.factor, self.patience, self.threshold, self.threshold_mode = mode, factor, patience, threshold, threshold_mode - self.best = float('inf') if mode == "min" else float('-inf') - self.bad_epoch = 0 - - if mode == "min": self.threshold *= -1 - - def is_better(self, current: float) -> bool: - dynamic_threshold = self.best*(1+self.threshold) if self.threshold_mode == "rel" else self.best+self.threshold - if self.mode == "min": - return current < dynamic_threshold - return current > dynamic_threshold - - def step(self, current: float) -> None: - self.epoch_counter.assign(self.epoch_counter + 1).realize() - if self.is_better(current): - self.bad_epoch = 0 - self.best = current - else: - self.bad_epoch += 1 - - if self.bad_epoch > self.patience: - self.optimizer.lr *= self.factor - self.bad_epoch = 0 - -class CosineAnnealingLR(LR_Scheduler): - def __init__(self, optimizer: Optimizer, T_max: int, eta_min=0): - super().__init__(optimizer) - self.T_max = T_max - self.eta_min = eta_min - self.eta_max = optimizer.lr.numpy()[0] - - def get_lr(self) -> Tensor: - lr = self.eta_min + 0.5 * (self.eta_max - self.eta_min) * (1 + math.cos((self.epoch_counter.numpy()[0]/self.T_max) * math.pi)) - return Tensor([lr], device=self.optimizer.device, dtype=self.optimizer.lr.dtype) - -class OneCycleLR(LR_Scheduler): - def __init__(self, optimizer: Optimizer, max_lr: float, div_factor: float, final_div_factor: float, total_steps: int, pct_start: float, - anneal_strategy: str = 'linear', cycle_momentum: bool = False): - super().__init__(optimizer) - self.initial_lr = max_lr / div_factor - self.max_lr = max_lr - self.min_lr = self.initial_lr / final_div_factor - self.total_steps = total_steps - self.pct_start = pct_start - assert anneal_strategy == 'linear', 'only linear annealing supported' - assert not cycle_momentum, 'cycle momentum not supported' - self.optimizer.lr.assign(self.get_lr()).realize() # update the initial LR - - @staticmethod - def _annealing_linear(start: float, end: float, pct: Tensor) -> Tensor: return (pct*(end-start)+start) - - def get_lr(self) -> Tensor: - return (self.epoch_counter < self.total_steps*self.pct_start).where( - self._annealing_linear(self.initial_lr, self.max_lr, self.epoch_counter/(self.total_steps*self.pct_start)), - self._annealing_linear(self.max_lr, self.min_lr, (self.epoch_counter-(self.total_steps*self.pct_start))/(self.total_steps*(1-self.pct_start))) - ).cast(self.optimizer.lr.dtype) diff --git a/tinygrad/extra/mcts_search.py b/tinygrad/extra/mcts_search.py deleted file mode 100644 index 9090c902..00000000 --- a/tinygrad/extra/mcts_search.py +++ /dev/null @@ -1,175 +0,0 @@ -from __future__ import annotations -from typing import List, Optional, Dict, cast -import numpy as np -np.set_printoptions(suppress=True) -import math, functools, time, random, statistics -from tinygrad.helpers import DEBUG, getenv, CACHELEVEL, diskcache_get, diskcache_put, colored, Profiling -from tinygrad.codegen.kernel import Kernel -from tinygrad.device import Buffer, Device, CompileError -from tinygrad.engine.search import _ensure_buffer_alloc, get_kernel_actions, _time_program - -class MCTSNode: - def __init__(self, kernel:Kernel, parent=None): - self.kernel:Kernel = kernel - self.t = math.inf - self.n = 0 - self.tm = math.inf - self.i = -1 - self.parents: List[MCTSNode] = [parent] if parent is not None else [] - self.children: Optional[List[MCTSNode]] = None - self.removed_children: List[MCTSNode] = [] - -def expand_node(node:MCTSNode): - assert node.children is None - node.children = [MCTSNode(x, node) for x in get_kernel_actions(node.kernel, include_0=False).values()] - -def remove_node(node:MCTSNode): - for parent in node.parents: - assert parent.children is not None - parent.children.remove(node) - parent.removed_children.append(node) - -C = math.sqrt(2) -TEMP = 0.5 -def _sample_tree(node:MCTSNode, best_tm:float) -> MCTSNode: - if node.children is None or len(node.children) == 0: return node - unexplored_children = [] - explored_children = [] - ucb_explored_children: List[float] = [] - for child in node.children: - if child.n == 0: unexplored_children.append(child) - else: - ucb = -child.t/best_tm + C*math.sqrt(math.log(node.n)/child.n) - if not math.isinf(ucb): - explored_children.append(child) - ucb_explored_children.append(ucb) - if len(unexplored_children): return random.choice(unexplored_children) - if not len(explored_children): return node - # safe softmax - ucb_exp = np.exp((np.array(ucb_explored_children)-max(ucb_explored_children))/TEMP) - return _sample_tree(explored_children[np.random.choice(len(ucb_exp), p=ucb_exp/np.sum(ucb_exp))], best_tm) - -# this will expand/remove sometimes -def sample_tree(root:MCTSNode, best_tm:float) -> Optional[MCTSNode]: - if root.children is None: expand_node(root) - while root.children: - # tree traversal - node = _sample_tree(root, best_tm) - - if node.children is not None and len(node.children) == 0: - remove_node(node) - continue - - # node expansion - if node.n != 0: - if node.children is None: expand_node(node) - assert node.children is not None - if len(node.children) == 0: - remove_node(node) - continue - node = random.choice(node.children) - return node - return None - -def backprop(bnode:MCTSNode, tm, strength=1.0): - if bnode.t > tm: bnode.t = tm - bnode.n += strength - for parent in bnode.parents: backprop(parent, tm, strength/len(bnode.parents)) - -graph_mcts_cnt = 0 -def mcts_search(lin:Kernel, rawbufs:List[Buffer], amt:int) -> Kernel: - global graph_mcts_cnt - # TODO: copied from BEAM - key = {"ast": lin.ast.key, "amt": amt, "device": lin.opts.device, "suffix": lin.opts.suffix} - if not getenv("IGNORE_MCTS_CACHE") and CACHELEVEL >= 1 and (val:=diskcache_get("mcts_search", key)) is not None: - ret = lin.copy() - for o in val[len(lin.applied_opts):]: ret.apply_opt(o) - return ret - - rawbufs = _ensure_buffer_alloc(rawbufs) - var_vals = {k:(k.vmax+k.vmin)//2 for k in lin.ast.variables()} - dev = Device[lin.opts.device] - root = MCTSNode(lin) - - st = time.perf_counter() - best, best_idx, best_tm = lin, 0, math.inf - seen_libs: Dict[bytes, MCTSNode] = {} - seen_asts: Dict[bytes, MCTSNode] = {} - compile_time, runtime_time = 0.0, 0.0 - for i in range(amt): - node = sample_tree(root, best_tm) # sample and expand - if node is None: break # finished the whole tree - node.i = i # when was node explored - - opt_ast = node.kernel.get_optimized_ast() - if (sibling_node:=seen_asts.get(opt_ast.key, None)) is not None: - # early check for same optimized AST hit - remove_node(node) - tm = sibling_node.t - else: - seen_asts[opt_ast.key] = node - - # lowering (50% of the time) - p = node.kernel.to_program(name_override="test") - - # rollout - tm1 = time.perf_counter() - try: - lib = dev.compiler.compile(p.src) - except CompileError: - # NOTE: many of these "compiler errors" are caused by bad code output from the lowerer - lib = None - tm2 = time.perf_counter() - if lib is None: - tm = math.inf - else: - if (sibling_node:=seen_libs.get(lib, None)) is not None: - # NOTE: these should all be caught by the AST check, need to canonicalize - # remove this node, it's a duplicate - remove_node(node) - tm = sibling_node.t - else: - seen_libs[lib] = node - try: tm = statistics.median(_time_program(p, lib, var_vals, rawbufs, cnt=3, early_stop=best_tm*5/1e6))*1e6 - except RuntimeError: tm = math.inf - node.tm = tm - tm3 = time.perf_counter() - compile_time += tm2-tm1 - runtime_time += tm3-tm2 - - # mock rollout - #node.tm = tm = random.random() + 0.1 - - if tm < best_tm: best, best_idx, best_tm = node.kernel, i, tm - et = time.perf_counter() - st - if DEBUG>=2: print(f"\r{et:7.2f}s {colored(f'{compile_time*100/et:3.0f}%', 'cyan')} {colored(f'{runtime_time*100/et:3.0f}%', 'red')}: {tm:12.2f} us best: {best_tm:12.2f} us @ {best_idx+1:4d} {i+1:4d}/{amt:4d} {int(round((i+1)/et)):4d}/s {node.kernel.colored_shape()}\033[K", end="") # noqa: E501 - - # backprop - backprop(node, tm) - if DEBUG>=2: print() - - if getenv("MCTSGRAPH"): - import networkx as nx - import os - GRAPHPATH = "/tmp/net" - def save_graph(G, fn, opt=""): - print("saving", G, f"to {fn}.svg") - nx.drawing.nx_pydot.write_dot(G, f'{fn}.dot') - os.system(f'dot {opt} -Tsvg {fn}.dot -o {fn}.svg') - - G = nx.DiGraph() - def add_node(node:MCTSNode): - if node.n == 0: return - for parent in node.parents: G.add_edge(parent, node) - gopts = node.kernel.applied_opts - edge_lbl = f"{str(gopts[-1].op)[7:]} {gopts[-1].axis} {gopts[-1].arg}" if len(gopts) else "ROOT" - G.add_node(node, label=f"{node.i+1}\n{node.tm:.2f} us\n{edge_lbl}\nt {node.t:.2f}\nn {node.n}", - fillcolor="#80ff8080" if node.tm == best_tm else "#ffff8080", style='filled' if node.t == best_tm else '') - if node.children is not None: - for child in node.children+node.removed_children: add_node(child) - add_node(root) - save_graph(G, f"{GRAPHPATH}.{graph_mcts_cnt}.mcts", '-Grankdir=LR') - graph_mcts_cnt += 1 - - if CACHELEVEL >= 1: diskcache_put("mcts_search", key, best.applied_opts) - return best diff --git a/tinygrad/extra/mmapeak/mmapeak.py b/tinygrad/extra/mmapeak/mmapeak.py deleted file mode 100644 index 032a6d79..00000000 --- a/tinygrad/extra/mmapeak/mmapeak.py +++ /dev/null @@ -1,79 +0,0 @@ -import pathlib -from tinygrad.device import Device -from tinygrad.runtime.ops_amd import AMDProgram, HIPCompiler -import time -import os - -NUM_WORKGROUPS = 96 -WAVE_SIZE = 32 -NUM_WAVES = 2 -FLOPS_PER_MATMUL = 16*16*16*2 -INTERNAL_LOOP = 1_000_000 -INSTRUCTIONS_PER_LOOP = 1_000 - -assemblyTemplate = (pathlib.Path(__file__).parent / "template.s").read_text() - -def launchBenchmark(instruction, vgprIndices, dense = True): - if dense: - instructions = "{} v[0:{}], v[{}:{}], v[{}:{}], 1\n".format(instruction, vgprIndices[0], - vgprIndices[1], vgprIndices[2], - vgprIndices[1], vgprIndices[2]) * INSTRUCTIONS_PER_LOOP - else: - instructions = "{} v[0:{}], v[{}:{}], v[{}:{}], v{}\n".format(instruction, vgprIndices[0], - vgprIndices[1], vgprIndices[2], - vgprIndices[3], vgprIndices[4], - vgprIndices[5]) * INSTRUCTIONS_PER_LOOP - src = assemblyTemplate.replace("INSTRUCTION", instructions) - lib = COMPILER.compile(src) - fxn = AMDProgram(DEV, "matmul", lib) - start = time.perf_counter() - fxn(global_size=(NUM_WORKGROUPS,1,1), local_size=(WAVE_SIZE*NUM_WAVES,1,1), wait=True) #For some reason the returned time is very small after the first kernel execution - end = time.perf_counter() - elapsed = end-start - FLOPs = FLOPS_PER_MATMUL * NUM_WAVES * NUM_WORKGROUPS * INTERNAL_LOOP * INSTRUCTIONS_PER_LOOP - print("{:<29} : {} T(FL)OPS".format(instruction, round(FLOPs/elapsed/10**12, 2))) - -if __name__=="__main__": - DEVICENUM = os.getenv("DEVICENUM", "0") - try: - DEV = Device['AMD:' + DEVICENUM] - except: - raise RuntimeError("Error while initiating AMD device") - - if (ARCH := DEV.arch) not in ['gfx1100', 'gfx1201']: - raise RuntimeError("only gfx1100 and gfx1201 supported") - COMPILER = HIPCompiler(ARCH) - - if ARCH == 'gfx1100': - launchBenchmark("v_wmma_bf16_16x16x16_bf16", (7,8,15)) - launchBenchmark("v_wmma_f16_16x16x16_f16", (7,8,15)) - launchBenchmark("v_wmma_f32_16x16x16_bf16", (7,8,15)) - launchBenchmark("v_wmma_f32_16x16x16_f16", (7,8,15)) - launchBenchmark("v_wmma_i32_16x16x16_iu4", (7,8,9)) - launchBenchmark("v_wmma_i32_16x16x16_iu8", (7,8,11)) - if ARCH == 'gfx1201': - NUM_WORKGROUPS = 64 - launchBenchmark("v_wmma_bf16_16x16x16_bf16", (3,4,7)) - launchBenchmark("v_wmma_f16_16x16x16_f16", (3,4,7)) - launchBenchmark("v_wmma_f32_16x16x16_bf16", (7,8,11)) - launchBenchmark("v_wmma_f32_16x16x16_f16", (7,8,11)) - launchBenchmark("v_wmma_i32_16x16x16_iu4", (7,8,8)) - launchBenchmark("v_wmma_i32_16x16x16_iu8", (7,8,9)) - launchBenchmark("v_wmma_f32_16x16x16_fp8_fp8", (7,8,9)) - launchBenchmark("v_wmma_f32_16x16x16_fp8_bf8", (7,8,9)) - launchBenchmark("v_wmma_f32_16x16x16_bf8_fp8", (7,8,9)) - launchBenchmark("v_wmma_f32_16x16x16_bf8_bf8", (7,8,9)) - FLOPS_PER_MATMUL = 16*16*32*2 - launchBenchmark("v_wmma_i32_16X16X32_iu4", (7,8,9)) - launchBenchmark("v_swmmac_f32_16x16x32_f16", (7,8,11,12,19,20), False) - launchBenchmark("v_swmmac_f32_16x16x32_bf16", (7,8,11,12,19,20), False) - launchBenchmark("v_swmmac_f16_16x16x32_f16", (3,4,7,8,15,16), False) - launchBenchmark("v_swmmac_bf16_16x16x32_bf16", (3,4,7,8,15,16), False) - launchBenchmark("v_swmmac_i32_16x16x32_iu8", (7,8,9,10,13,14), False) - launchBenchmark("v_swmmac_i32_16x16x32_iu4", (7,8,8,9,10,11), False) - launchBenchmark("v_swmmac_f32_16x16x32_fp8_fp8", (7,8,9,10,13,14), False) - launchBenchmark("v_swmmac_f32_16x16x32_fp8_bf8", (7,8,9,10,13,14), False) - launchBenchmark("v_swmmac_f32_16x16x32_bf8_fp8", (7,8,9,10,13,14), False) - launchBenchmark("v_swmmac_f32_16x16x32_bf8_bf8", (7,8,9,10,13,14), False) - FLOPS_PER_MATMUL = 16*16*64*2 - launchBenchmark("v_swmmac_i32_16x16x64_iu4", (7,8,9,10,13,14), False) \ No newline at end of file diff --git a/tinygrad/extra/mmapeak/template.s b/tinygrad/extra/mmapeak/template.s deleted file mode 100644 index f3fc5f2b..00000000 --- a/tinygrad/extra/mmapeak/template.s +++ /dev/null @@ -1,41 +0,0 @@ - .text - .globl matmul - .p2align 8 - .type matmul,@function -matmul: - s_mov_b32 s1, 1000000 - s_mov_b32 s2, 0 - inner_loop: - INSTRUCTION - s_sub_u32 s1, s1, 1 - s_cmp_lg_i32 s1, s2 - s_cbranch_scc1 inner_loop - s_endpgm - -.rodata -.p2align 6 -.amdhsa_kernel matmul - .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr - .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr - .amdhsa_wavefront_size32 1 -.end_amdhsa_kernel - -.amdgpu_metadata ---- -amdhsa.version: - - 1 - - 0 -amdhsa.kernels: - - .name: matmul - .symbol: matmul.kd - .kernarg_segment_size: 0 - .group_segment_fixed_size: 0 - .private_segment_fixed_size: 0 - .kernarg_segment_align: 4 - .wavefront_size: 32 - .sgpr_count: 8 - .vgpr_count: 32 - .max_flat_workgroup_size: 1024 - .args: -... -.end_amdgpu_metadata \ No newline at end of file diff --git a/tinygrad/extra/models/bert.py b/tinygrad/extra/models/bert.py deleted file mode 100644 index a3edcb2c..00000000 --- a/tinygrad/extra/models/bert.py +++ /dev/null @@ -1,299 +0,0 @@ -import re, os -from pathlib import Path -from tinygrad.tensor import Tensor, cast -from tinygrad import nn, dtypes -from tinygrad.helpers import fetch, get_child -from tinygrad.nn.state import get_parameters - -# allow for monkeypatching -Embedding = nn.Embedding -Linear = nn.Linear -LayerNorm = nn.LayerNorm - -class BertForQuestionAnswering: - def __init__(self, hidden_size=1024, intermediate_size=4096, max_position_embeddings=512, num_attention_heads=16, num_hidden_layers=24, type_vocab_size=2, vocab_size=30522, attention_probs_dropout_prob=0.1, hidden_dropout_prob=0.1): - self.bert = Bert(hidden_size, intermediate_size, max_position_embeddings, num_attention_heads, num_hidden_layers, type_vocab_size, vocab_size, attention_probs_dropout_prob, hidden_dropout_prob) - self.qa_outputs = Linear(hidden_size, 2) - - def load_from_pretrained(self): - fn = Path(__file__).parents[1] / "weights/bert_for_qa.pt" - fetch("https://zenodo.org/record/3733896/files/model.pytorch?download=1", fn) - fn_vocab = Path(__file__).parents[1] / "weights/bert_vocab.txt" - fetch("https://zenodo.org/record/3733896/files/vocab.txt?download=1", fn_vocab) - - import torch - with open(fn, "rb") as f: - state_dict = torch.load(f, map_location="cpu") - - for k, v in state_dict.items(): - if "dropout" in k: continue # skip dropout - if "pooler" in k: continue # skip pooler - get_child(self, k).assign(v.numpy()).realize() - - def __call__(self, input_ids:Tensor, attention_mask:Tensor, token_type_ids:Tensor): - sequence_output = self.bert(input_ids, attention_mask, token_type_ids) - logits = self.qa_outputs(sequence_output) - start_logits, end_logits = logits.chunk(2, dim=-1) - start_logits = start_logits.reshape(-1, 1) - end_logits = end_logits.reshape(-1, 1) - - return Tensor.stack(start_logits, end_logits) - -class BertForPretraining: - def __init__(self, hidden_size:int=1024, intermediate_size:int=4096, max_position_embeddings:int=512, num_attention_heads:int=16, num_hidden_layers:int=24, type_vocab_size:int=2, vocab_size:int=30522, attention_probs_dropout_prob:float=0.1, hidden_dropout_prob:float=0.1): - """Default is BERT-large""" - self.bert = Bert(hidden_size, intermediate_size, max_position_embeddings, num_attention_heads, num_hidden_layers, type_vocab_size, vocab_size, attention_probs_dropout_prob, hidden_dropout_prob) - self.cls = BertPreTrainingHeads(hidden_size, vocab_size, self.bert.embeddings.word_embeddings.weight) - - def __call__(self, input_ids:Tensor, attention_mask:Tensor, masked_lm_positions:Tensor, token_type_ids:Tensor): - output = self.bert(input_ids, attention_mask, token_type_ids) - return self.cls(output, masked_lm_positions) - - # Reference has residual on denominator: https://github.com/mlcommons/training/blob/master/language_model/tensorflow/bert/run_pretraining.py#L315 - def sparse_categorical_crossentropy(self, predictions:Tensor, labels:Tensor, ignore_index=-1): - log_probs, loss_mask = predictions.log_softmax(dtype=dtypes.float), (labels != ignore_index) - y_counter = Tensor.arange(predictions.shape[-1], requires_grad=False, device=predictions.device).unsqueeze(0).expand(labels.numel(), predictions.shape[-1]) - y = ((y_counter == labels.flatten().reshape(-1, 1)) * loss_mask.reshape(-1, 1)).reshape(*labels.shape, predictions.shape[-1]) - return -((log_probs * y).sum()) / (loss_mask.sum() + 1e-5) # Small constant to avoid division by zero - - def loss(self, prediction_logits:Tensor, seq_relationship_logits:Tensor, masked_lm_ids:Tensor, masked_lm_weights:Tensor, next_sentence_labels:Tensor): - masked_lm_loss = self.sparse_categorical_crossentropy(prediction_logits, masked_lm_ids, ignore_index=masked_lm_weights) - next_sentence_loss = seq_relationship_logits.binary_crossentropy_logits(next_sentence_labels) - return masked_lm_loss + next_sentence_loss - - def accuracy(self, prediction_logits:Tensor, seq_relationship_logits:Tensor, masked_lm_ids:Tensor, masked_lm_weights:Tensor, next_sentence_labels:Tensor): - valid = masked_lm_ids != 0 - masked_lm_predictions = prediction_logits.argmax(-1) - masked_lm_correct = (masked_lm_predictions == masked_lm_ids) * valid - masked_lm_loss = self.sparse_categorical_crossentropy(prediction_logits, masked_lm_ids, ignore_index=masked_lm_weights) - - seq_relationship_predictions = seq_relationship_logits.argmax(-1) - seq_relationship_correct = (seq_relationship_predictions == next_sentence_labels) - next_sentence_loss = seq_relationship_logits.binary_crossentropy_logits(next_sentence_labels) - - # NOTE: .float().sum() to prevent overflow with large BS since default acc of bool is in default_float - # TODO: is it okay that next_sentence_loss is half here? - return masked_lm_correct.float().sum() / valid.float().sum(), seq_relationship_correct.float().mean(), masked_lm_loss, next_sentence_loss.float() - - def load_from_pretrained(self, tf_weight_path:str=Path(__file__).parent.parent / "datasets" / "wiki"): - os.environ['TF_CPP_MIN_LOG_LEVEL'] = '2' # Mute tf flag info - # load from tensorflow - import tensorflow as tf - import numpy as np - - state_dict = {} - for name, _ in tf.train.list_variables(str(tf_weight_path)): - state_dict[name] = tf.train.load_variable(str(tf_weight_path), name) - - for k, v in state_dict.items(): - m = k.split("/") - if any(n in ["adam_v", "adam_m", "global_step", "LAMB", "LAMB_1", "beta1_power", "beta2_power"] for n in m): - continue - - pointer = self - n = m[-1] # this is just to stop python from complaining about possibly unbound local variable - for i, n in enumerate(m): - if re.fullmatch(r'[A-Za-z]+_\d+', n): - l = re.split(r'_(\d+)', n)[:-1] - else: - l = [n] - if l[0] in ["kernel", "gamma", "output_weights"]: - pointer = getattr(pointer, "weight") - elif l[0] in ["output_bias", "beta"]: - pointer = getattr(pointer, "bias") - elif l[0] == "pooler": - pointer = getattr(getattr(self, "cls"), "pooler") - else: - pointer = getattr(pointer, l[0]) - if len(l) == 2: # layers - pointer = pointer[int(l[1])] - if n[-11:] == "_embeddings": - pointer = getattr(pointer, "weight") - elif n == "kernel": - v = np.transpose(v) - cast(Tensor, pointer).assign(v).realize() - - params = get_parameters(self) - count = 0 - for p in params: - param_count = 1 - for s in p.shape: - param_count *= s - count += param_count - print(f"Total parameters: {count / 1000 / 1000}M") - return self - -class BertPreTrainingHeads: - def __init__(self, hidden_size:int, vocab_size:int, embeddings_weight:Tensor): - self.predictions = BertLMPredictionHead(hidden_size, vocab_size, embeddings_weight) - self.pooler = BertPooler(hidden_size) - self.seq_relationship = Linear(hidden_size, 2) - - def __call__(self, sequence_output:Tensor, masked_lm_positions:Tensor): - prediction_logits = self.predictions(gather(sequence_output, masked_lm_positions)) - seq_relationship_logits = self.seq_relationship(self.pooler(sequence_output)) - return prediction_logits, seq_relationship_logits - -class BertLMPredictionHead: - def __init__(self, hidden_size:int, vocab_size:int, embeddings_weight:Tensor): - self.transform = BertPredictionHeadTransform(hidden_size) - self.embedding_weight = embeddings_weight - self.bias = Tensor.zeros(vocab_size, dtype=dtypes.float32) - - def __call__(self, hidden_states:Tensor): - return self.transform(hidden_states) @ self.embedding_weight.T + self.bias - -class BertPredictionHeadTransform: - def __init__(self, hidden_size:int): - self.dense = Linear(hidden_size, hidden_size) - self.LayerNorm = LayerNorm(hidden_size, eps=1e-12) - - def __call__(self, hidden_states:Tensor): - return self.LayerNorm(gelu(self.dense(hidden_states))) - -class BertPooler: - def __init__(self, hidden_size:int): - self.dense = Linear(hidden_size, hidden_size) - - def __call__(self, hidden_states:Tensor): - return self.dense(hidden_states[:, 0]).tanh() - -def gather(prediction_logits:Tensor, masked_lm_positions:Tensor): - counter = Tensor.arange(prediction_logits.shape[1], device=prediction_logits.device, requires_grad=False).reshape(1, 1, prediction_logits.shape[1]).expand(*masked_lm_positions.shape, prediction_logits.shape[1]) - onehot = counter == masked_lm_positions.unsqueeze(2).expand(*masked_lm_positions.shape, prediction_logits.shape[1]) - return onehot @ prediction_logits - -class Bert: - def __init__(self, hidden_size, intermediate_size, max_position_embeddings, num_attention_heads, num_hidden_layers, type_vocab_size, vocab_size, attention_probs_dropout_prob, hidden_dropout_prob): - self.embeddings = BertEmbeddings(hidden_size, max_position_embeddings, type_vocab_size, vocab_size, hidden_dropout_prob) - self.encoder = BertEncoder(hidden_size, intermediate_size, num_attention_heads, num_hidden_layers, attention_probs_dropout_prob, hidden_dropout_prob) - - def __call__(self, input_ids, attention_mask, token_type_ids): - extended_attention_mask = attention_mask.unsqueeze(1).unsqueeze(2) - extended_attention_mask = (1.0 - extended_attention_mask) * -10000.0 - - embedding_output = self.embeddings(input_ids, token_type_ids) - encoder_outputs = self.encoder(embedding_output, extended_attention_mask) - - return encoder_outputs - -class BertEmbeddings: - def __init__(self, hidden_size, max_position_embeddings, type_vocab_size, vocab_size, hidden_dropout_prob): - self.word_embeddings = Embedding(vocab_size, hidden_size) - self.position_embeddings = Embedding(max_position_embeddings, hidden_size) - self.token_type_embeddings = Embedding(type_vocab_size, hidden_size) - self.LayerNorm = LayerNorm(hidden_size, eps=1e-12) - self.dropout = hidden_dropout_prob - - def __call__(self, input_ids, token_type_ids): - input_shape = input_ids.shape - seq_length = input_shape[1] - - position_ids = Tensor.arange(seq_length, requires_grad=False, device=input_ids.device).unsqueeze(0).expand(*input_shape) - words_embeddings = self.word_embeddings(input_ids) - position_embeddings = self.position_embeddings(position_ids) - token_type_embeddings = self.token_type_embeddings(token_type_ids) - - embeddings = words_embeddings + position_embeddings + token_type_embeddings - embeddings = self.LayerNorm(embeddings) - embeddings = embeddings.dropout(self.dropout) - return embeddings - -class BertEncoder: - def __init__(self, hidden_size, intermediate_size, num_attention_heads, num_hidden_layers, attention_probs_dropout_prob, hidden_dropout_prob): - self.layer = [BertLayer(hidden_size, intermediate_size, num_attention_heads, attention_probs_dropout_prob, hidden_dropout_prob) for _ in range(num_hidden_layers)] - - def __call__(self, hidden_states, attention_mask): - for layer in self.layer: - hidden_states = layer(hidden_states, attention_mask) - return hidden_states - -class BertLayer: - def __init__(self, hidden_size, intermediate_size, num_attention_heads, attention_probs_dropout_prob, hidden_dropout_prob): - self.attention = BertAttention(hidden_size, num_attention_heads, attention_probs_dropout_prob, hidden_dropout_prob) - self.intermediate = BertIntermediate(hidden_size, intermediate_size) - self.output = BertOutput(hidden_size, intermediate_size, hidden_dropout_prob) - - def __call__(self, hidden_states, attention_mask): - attention_output = self.attention(hidden_states, attention_mask) - intermediate_output = self.intermediate(attention_output) - layer_output = self.output(intermediate_output, attention_output) - return layer_output - -class BertOutput: - def __init__(self, hidden_size, intermediate_size, hidden_dropout_prob): - self.dense = Linear(intermediate_size, hidden_size) - self.LayerNorm = LayerNorm(hidden_size, eps=1e-12) - self.dropout = hidden_dropout_prob - - def __call__(self, hidden_states, input_tensor): - hidden_states = self.dense(hidden_states) - hidden_states = hidden_states.dropout(self.dropout) - hidden_states = self.LayerNorm(hidden_states + input_tensor) - return hidden_states - -def gelu(x): - return x * 0.5 * (1.0 + (x / 1.41421).erf()) - -class BertIntermediate: - def __init__(self, hidden_size, intermediate_size): - self.dense = Linear(hidden_size, intermediate_size) - - def __call__(self, hidden_states): - x = self.dense(hidden_states) - # tinygrad gelu is openai gelu but we need the original bert gelu - return gelu(x) - -class BertAttention: - def __init__(self, hidden_size, num_attention_heads, attention_probs_dropout_prob, hidden_dropout_prob): - self.self = BertSelfAttention(hidden_size, num_attention_heads, attention_probs_dropout_prob) - self.output = BertSelfOutput(hidden_size, hidden_dropout_prob) - - def __call__(self, hidden_states, attention_mask): - self_output = self.self(hidden_states, attention_mask) - attention_output = self.output(self_output, hidden_states) - return attention_output - -class BertSelfAttention: - def __init__(self, hidden_size, num_attention_heads, attention_probs_dropout_prob): - self.num_attention_heads = num_attention_heads - self.attention_head_size = int(hidden_size / num_attention_heads) - self.all_head_size = self.num_attention_heads * self.attention_head_size - - self.query = Linear(hidden_size, self.all_head_size) - self.key = Linear(hidden_size, self.all_head_size) - self.value = Linear(hidden_size, self.all_head_size) - - self.dropout = attention_probs_dropout_prob - - def __call__(self, hidden_states, attention_mask): - mixed_query_layer = self.query(hidden_states) - mixed_key_layer = self.key(hidden_states) - mixed_value_layer = self.value(hidden_states) - - query_layer = self.transpose_for_scores(mixed_query_layer) - key_layer = self.transpose_for_scores(mixed_key_layer) - value_layer = self.transpose_for_scores(mixed_value_layer) - - context_layer = Tensor.scaled_dot_product_attention(query_layer, key_layer, value_layer, attention_mask, self.dropout) - - context_layer = context_layer.transpose(1, 2) - context_layer = context_layer.reshape(context_layer.shape[0], context_layer.shape[1], self.all_head_size) - - return context_layer - - def transpose_for_scores(self, x): - x = x.reshape(x.shape[0], x.shape[1], self.num_attention_heads, self.attention_head_size) - return x.transpose(1, 2) - -class BertSelfOutput: - def __init__(self, hidden_size, hidden_dropout_prob): - self.dense = Linear(hidden_size, hidden_size) - self.LayerNorm = LayerNorm(hidden_size, eps=1e-12) - self.dropout = hidden_dropout_prob - - def __call__(self, hidden_states, input_tensor): - hidden_states = self.dense(hidden_states) - hidden_states = hidden_states.dropout(self.dropout) - hidden_states = self.LayerNorm(hidden_states + input_tensor) - return hidden_states diff --git a/tinygrad/extra/models/clip.py b/tinygrad/extra/models/clip.py deleted file mode 100644 index 7b176fcd..00000000 --- a/tinygrad/extra/models/clip.py +++ /dev/null @@ -1,463 +0,0 @@ -from tinygrad import Tensor, dtypes -from tinygrad.helpers import fetch -from tinygrad.nn import Linear, LayerNorm, Embedding, Conv2d - -from typing import List, Optional, Union, Tuple, Dict -from abc import ABC, abstractmethod -from functools import lru_cache -from PIL import Image -import numpy as np -import re, gzip - -@lru_cache() -def default_bpe(): - # Clip tokenizer, taken from https://github.com/openai/CLIP/blob/main/clip/simple_tokenizer.py (MIT license) - return fetch("https://github.com/openai/CLIP/raw/main/clip/bpe_simple_vocab_16e6.txt.gz", "bpe_simple_vocab_16e6.txt.gz") - -class Tokenizer: - """ - Namespace for CLIP Text Tokenizer components. - """ - - @staticmethod - def get_pairs(word): - """ - Return set of symbol pairs in a word. - Word is represented as tuple of symbols (symbols being variable-length strings). - """ - return set(zip(word, word[1:])) - @staticmethod - def whitespace_clean(text): - text = re.sub(r'\s+', ' ', text) - text = text.strip() - return text - @staticmethod - def bytes_to_unicode(): - """ - Returns list of utf-8 byte and a corresponding list of unicode strings. - The reversible bpe codes work on unicode strings. - This means you need a large # of unicode characters in your vocab if you want to avoid UNKs. - When you're at something like a 10B token dataset you end up needing around 5K for decent coverage. - This is a significant percentage of your normal, say, 32K bpe vocab. - To avoid that, we want lookup tables between utf-8 bytes and unicode strings. - And avoids mapping to whitespace/control characters the bpe code barfs on. - """ - bs = list(range(ord("!"), ord("~")+1))+list(range(ord("¡"), ord("¬")+1))+list(range(ord("®"), ord("ÿ")+1)) - cs = bs[:] - n = 0 - for b in range(2**8): - if b not in bs: - bs.append(b) - cs.append(2**8+n) - n += 1 - cs = [chr(n) for n in cs] - return dict(zip(bs, cs)) - class ClipTokenizer: - def __init__(self): - self.byte_encoder = Tokenizer.bytes_to_unicode() - merges = gzip.open(default_bpe()).read().decode("utf-8").split('\n') - merges = merges[1:49152-256-2+1] - merges = [tuple(merge.split()) for merge in merges] - vocab = list(Tokenizer.bytes_to_unicode().values()) - vocab = vocab + [v+'' for v in vocab] - for merge in merges: - vocab.append(''.join(merge)) - vocab.extend(['<|startoftext|>', '<|endoftext|>']) - self.encoder = dict(zip(vocab, range(len(vocab)))) - self.bpe_ranks = dict(zip(merges, range(len(merges)))) - self.cache = {'<|startoftext|>': '<|startoftext|>', '<|endoftext|>': '<|endoftext|>'} - self.pat = re.compile(r"""<\|startoftext\|>|<\|endoftext\|>|'s|'t|'re|'ve|'m|'ll|'d|[^\s]+""", re.IGNORECASE) - - def bpe(self, token): - if token in self.cache: - return self.cache[token] - word = tuple(token[:-1]) + ( token[-1] + '',) - pairs = Tokenizer.get_pairs(word) - - if not pairs: - return token+'' - - while True: - bigram = min(pairs, key = lambda pair: self.bpe_ranks.get(pair, float('inf'))) - if bigram not in self.bpe_ranks: - break - first, second = bigram - new_word = [] - i = 0 - while i < len(word): - try: - j = word.index(first, i) - new_word.extend(word[i:j]) - i = j - except Exception: - new_word.extend(word[i:]) - break - - if word[i] == first and i < len(word)-1 and word[i+1] == second: - new_word.append(first+second) - i += 2 - else: - new_word.append(word[i]) - i += 1 - new_word = tuple(new_word) - word = new_word - if len(word) == 1: - break - pairs = Tokenizer.get_pairs(word) - word = ' '.join(word) - self.cache[token] = word - return word - - def encode(self, text:str, pad_with_zeros:bool=False) -> List[int]: - bpe_tokens: List[int] = [] - text = Tokenizer.whitespace_clean(text.strip()).lower() - for token in re.findall(self.pat, text): - token = ''.join(self.byte_encoder[b] for b in token.encode('utf-8')) - bpe_tokens.extend(self.encoder[bpe_token] for bpe_token in self.bpe(token).split(' ')) - # Truncation, keeping two slots for start and end tokens. - if len(bpe_tokens) > 75: - bpe_tokens = bpe_tokens[:75] - return [49406] + bpe_tokens + [49407] + ([0] if pad_with_zeros else [49407]) * (77 - len(bpe_tokens) - 2) - - -class Embedder(ABC): - input_key: str - @abstractmethod - def __call__(self, x:Union[str,List[str],Tensor]) -> Union[Tensor,Tuple[Tensor,...]]: - pass - - -class Closed: - """ - Namespace for OpenAI CLIP model components. - """ - class ClipMlp: - def __init__(self): - self.fc1 = Linear(768, 3072) - self.fc2 = Linear(3072, 768) - - def __call__(self, h:Tensor) -> Tensor: - h = self.fc1(h) - h = h.quick_gelu() - h = self.fc2(h) - return h - - class ClipAttention: - def __init__(self): - self.embed_dim = 768 - self.num_heads = 12 - self.head_dim = self.embed_dim // self.num_heads - self.k_proj = Linear(self.embed_dim, self.embed_dim) - self.v_proj = Linear(self.embed_dim, self.embed_dim) - self.q_proj = Linear(self.embed_dim, self.embed_dim) - self.out_proj = Linear(self.embed_dim, self.embed_dim) - - def __call__(self, hidden_states:Tensor, causal_attention_mask:Tensor) -> Tensor: - bsz, tgt_len, embed_dim = hidden_states.shape - q,k,v = self.q_proj(hidden_states), self.k_proj(hidden_states), self.v_proj(hidden_states) - q,k,v = [x.reshape(bsz, tgt_len, self.num_heads, self.head_dim).transpose(1, 2) for x in (q,k,v)] - attn_output = Tensor.scaled_dot_product_attention(q, k, v, attn_mask=causal_attention_mask) - return self.out_proj(attn_output.transpose(1, 2).reshape(bsz, tgt_len, embed_dim)) - - class ClipEncoderLayer: - def __init__(self): - self.self_attn = Closed.ClipAttention() - self.layer_norm1 = LayerNorm(768) - self.mlp = Closed.ClipMlp() - self.layer_norm2 = LayerNorm(768) - - def __call__(self, hidden_states:Tensor, causal_attention_mask:Tensor) -> Tensor: - residual = hidden_states - hidden_states = self.layer_norm1(hidden_states) - hidden_states = self.self_attn(hidden_states, causal_attention_mask) - hidden_states = residual + hidden_states - - residual = hidden_states - hidden_states = self.layer_norm2(hidden_states) - hidden_states = self.mlp(hidden_states) - hidden_states = residual + hidden_states - - return hidden_states - - class ClipTextEmbeddings: - def __init__(self): - self.token_embedding = Embedding(49408, 768) - self.position_embedding = Embedding(77, 768) - - def __call__(self, input_ids:Tensor, position_ids:Tensor) -> Tensor: - return self.token_embedding(input_ids) + self.position_embedding(position_ids) - - class ClipEncoder: - def __init__(self, layer_count:int=12): - self.layers = [Closed.ClipEncoderLayer() for _ in range(layer_count)] - - def __call__(self, x:Tensor, causal_attention_mask:Tensor, ret_layer_idx:Optional[int]=None) -> Tensor: - # the indexing of layers is NOT off by 1, the original code considers the "input" as the first hidden state - layers = self.layers if ret_layer_idx is None else self.layers[:ret_layer_idx] - for l in layers: - x = l(x, causal_attention_mask) - return x - - class ClipTextTransformer: - def __init__(self, ret_layer_idx:Optional[int]=None): - self.embeddings = Closed.ClipTextEmbeddings() - self.encoder = Closed.ClipEncoder() - self.final_layer_norm = LayerNorm(768) - self.ret_layer_idx = ret_layer_idx - - def __call__(self, input_ids:Tensor) -> Tensor: - x = self.embeddings(input_ids, Tensor.arange(input_ids.shape[1]).reshape(1, -1)) - x = self.encoder(x, Tensor.full((1, 1, 77, 77), float("-inf")).triu(1), self.ret_layer_idx) - return self.final_layer_norm(x) if (self.ret_layer_idx is None) else x - - class ClipTextModel: - def __init__(self, ret_layer_idx:Optional[int]): - self.text_model = Closed.ClipTextTransformer(ret_layer_idx=ret_layer_idx) - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/encoders/modules.py#L331 -class FrozenClosedClipEmbedder(Embedder): - def __init__(self, ret_layer_idx:Optional[int]=None): - self.tokenizer = Tokenizer.ClipTokenizer() - self.transformer = Closed.ClipTextModel(ret_layer_idx) - self.input_key = "txt" - - def __call__(self, texts:Union[str,List[str],Tensor]) -> Union[Tensor,Tuple[Tensor,...]]: - if isinstance(texts, str): texts = [texts] - assert isinstance(texts, (list,tuple)), f"expected list of strings, got {type(texts).__name__}" - tokens = Tensor.cat(*[Tensor(self.tokenizer.encode(text)) for text in texts], dim=0) - return self.transformer.text_model(tokens.reshape(len(texts),-1)) - - -class Open: - """ - Namespace for OpenCLIP model components. - """ - class MultiheadAttention: - def __init__(self, dims:int, n_heads:int): - self.dims = dims - self.n_heads = n_heads - self.d_head = self.dims // self.n_heads - - self.in_proj_bias = Tensor.empty(3*dims) - self.in_proj_weight = Tensor.empty(3*dims, dims) - self.out_proj = Linear(dims, dims) - - def __call__(self, x:Tensor, attn_mask:Optional[Tensor]=None) -> Tensor: - T,B,C = x.shape - - proj = x.linear(self.in_proj_weight.T, self.in_proj_bias) - proj = proj.unflatten(-1, (3,C)).unsqueeze(0).transpose(0, -2) - - q,k,v = [y.reshape(T, B*self.n_heads, self.d_head).transpose(0, 1).reshape(B, self.n_heads, T, self.d_head) for y in proj.chunk(3)] - - attn_output = Tensor.scaled_dot_product_attention(q, k, v, attn_mask=attn_mask) - attn_output = attn_output.permute(2, 0, 1, 3).reshape(T*B, C) - - attn_output = self.out_proj(attn_output) - attn_output = attn_output.reshape(T, B, C) - - return attn_output - - class Mlp: - def __init__(self, dims, hidden_dims): - self.c_fc = Linear(dims, hidden_dims) - self.c_proj = Linear(hidden_dims, dims) - - def __call__(self, x:Tensor) -> Tensor: - return x.sequential([self.c_fc, Tensor.gelu, self.c_proj]) - - # https://github.com/mlfoundations/open_clip/blob/58e4e39aaabc6040839b0d2a7e8bf20979e4558a/src/open_clip/transformer.py#L210 - class ResidualAttentionBlock: - def __init__(self, dims:int, n_heads:int, mlp_ratio:float): - self.ln_1 = LayerNorm(dims) - self.attn = Open.MultiheadAttention(dims, n_heads) - - self.ln_2 = LayerNorm(dims) - self.mlp = Open.Mlp(dims, int(dims * mlp_ratio)) - - def __call__(self, x:Tensor, attn_mask:Optional[Tensor]=None, transpose:bool=False) -> Tensor: - q_x = self.ln_1(x) - attn_out = self.attn(q_x.transpose(0, 1) if transpose else q_x, attn_mask=attn_mask) - attn_out = attn_out.transpose(0, 1) if transpose else attn_out - x = x + attn_out - x = x + self.mlp(self.ln_2(x)) - return x - - # https://github.com/mlfoundations/open_clip/blob/58e4e39aaabc6040839b0d2a7e8bf20979e4558a/src/open_clip/transformer.py#L317 - class ClipTransformer: - def __init__(self, dims:int, layers:int, n_heads:int, mlp_ratio:float=4.0): - self.resblocks = [ - Open.ResidualAttentionBlock(dims, n_heads, mlp_ratio) for _ in range(layers) - ] - - def __call__(self, x:Tensor, attn_mask:Optional[Tensor]=None) -> Tensor: - for r in self.resblocks: - x = r(x, attn_mask=attn_mask, transpose=True) - return x - - # https://github.com/mlfoundations/open_clip/blob/58e4e39aaabc6040839b0d2a7e8bf20979e4558a/src/open_clip/model.py#L220 - # https://github.com/mlfoundations/open_clip/blob/58e4e39aaabc6040839b0d2a7e8bf20979e4558a/src/open_clip/transformer.py#L661 - class ClipTextTransformer: - def __init__(self, width:int, n_heads:int, layers:int, vocab_size:int=49408, ctx_length:int=77): - self.token_embedding = Embedding(vocab_size, width) - self.positional_embedding = Tensor.empty(ctx_length, width) - self.transformer = Open.ClipTransformer(width, layers, n_heads) - self.ln_final = LayerNorm(width) - self.text_projection = Tensor.empty(width, width) - self.attn_mask = Tensor.full((77, 77), float("-inf")).triu(1).realize() - - def __call__(self, text:Tensor) -> Tensor: - seq_len = text.shape[1] - - x = self.token_embedding(text) - x = x + self.positional_embedding[:seq_len] - x = self.transformer(x, attn_mask=self.attn_mask) - x = self.ln_final(x) - - pooled = x[:, text.argmax(dim=-1)] @ self.text_projection - return pooled - - class ClipVisionTransformer: - def __init__(self, width:int, layers:int, d_head:int, image_size:int, patch_size:int): - grid_size = image_size // patch_size - n_heads = width // d_head - assert n_heads * d_head == width - - self.conv1 = Conv2d(3, width, kernel_size=patch_size, stride=patch_size, bias=False) - - self.class_embedding = Tensor.empty(width) - self.positional_embedding = Tensor.empty(grid_size * grid_size + 1, width) - self.transformer = Open.ClipTransformer(width, layers, n_heads) - self.ln_pre = LayerNorm(width) - self.ln_post = LayerNorm(width) - self.proj = Tensor.empty(width, 1024) - - def __call__(self, x:Tensor) -> Tensor: - x = self.conv1(x) - x = x.reshape(x.shape[0], x.shape[1], -1).permute(0, 2, 1) - x = self.class_embedding.reshape(1, 1, -1).expand(x.shape[0], 1, -1).cat(x, dim=1) - x = x + self.positional_embedding - - x = self.ln_pre(x) - x = self.transformer(x) - x = self.ln_post(x) - - pooled = x[:, 0] @ self.proj - return pooled - - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/encoders/modules.py#L396 -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/encoders/modules.py#L498 -class FrozenOpenClipEmbedder(Embedder): - def __init__(self, dims:int, n_heads:int, layers:int, return_pooled:bool, ln_penultimate:bool=False): - self.tokenizer = Tokenizer.ClipTokenizer() - self.model = Open.ClipTextTransformer(dims, n_heads, layers) - self.return_pooled = return_pooled - self.input_key = "txt" - self.ln_penultimate = ln_penultimate - - def tokenize(self, text:str, device:Optional[str]=None) -> Tensor: - return Tensor(self.tokenizer.encode(text, pad_with_zeros=True), dtype=dtypes.int64, device=device).reshape(1,-1) - - def text_transformer_forward(self, x:Tensor, attn_mask:Optional[Tensor]=None): - for r in self.model.transformer.resblocks: - x, penultimate = r(x, attn_mask=attn_mask), x - return x.permute(1, 0, 2), penultimate.permute(1, 0, 2) - - def embed_tokens(self, tokens:Tensor) -> Union[Tensor,Tuple[Tensor,...]]: - x = self.model.token_embedding(tokens).add(self.model.positional_embedding).permute(1,0,2) - x, penultimate = self.text_transformer_forward(x, attn_mask=self.model.attn_mask) - - if self.ln_penultimate: - penultimate = self.model.ln_final(penultimate) - - if self.return_pooled: - x = self.model.ln_final(x) - index = tokens.argmax(axis=-1).reshape(-1,1,1).expand(x.shape[0],1,x.shape[-1]) - pooled = x.gather(1, index).squeeze(1) @ self.model.text_projection - return penultimate, pooled - else: - return penultimate - - def __call__(self, texts:Union[str,List[str],Tensor]) -> Union[Tensor,Tuple[Tensor,...]]: - if isinstance(texts, str): texts = [texts] - assert isinstance(texts, (list,tuple)), f"expected list of strings, got {type(texts).__name__}" - tokens = Tensor.cat(*[self.tokenize(text) for text in texts], dim=0) - return self.embed_tokens(tokens) - - -clip_configs: Dict = { - "ViT-H-14": { - "dims": 1024, - "vision_cfg": { - "width": 1280, - "layers": 32, - "d_head": 80, - "image_size": 224, - "patch_size": 14, - }, - "text_cfg": { - "width": 1024, - "n_heads": 16, - "layers": 24, - "ctx_length": 77, - "vocab_size": 49408, - }, - "return_pooled": False, - "ln_penultimate": True, - } -} - -class OpenClipEncoder: - def __init__(self, dims:int, text_cfg:Dict, vision_cfg:Dict, **_): - self.visual = Open.ClipVisionTransformer(**vision_cfg) - - text = Open.ClipTextTransformer(**text_cfg) - self.transformer = text.transformer - self.token_embedding = text.token_embedding - self.positional_embedding = text.positional_embedding - self.ln_final = text.ln_final - self.text_projection = text.text_projection - - self.attn_mask = Tensor.full((77, 77), float("-inf")).triu(1).realize() - self.mean = Tensor([0.48145466, 0.45782750, 0.40821073]).reshape(-1, 1, 1) - self.std = Tensor([0.26862954, 0.26130258, 0.27577711]).reshape(-1, 1, 1) - - # TODO: - # Should be doable in pure tinygrad, would just require some work and verification. - # This is very desirable since it would allow for full generation->evaluation in a single JIT call. - def prepare_image(self, image:Image.Image) -> Tensor: - SIZE = 224 - w, h = image.size - scale = min(SIZE / h, SIZE / w) - image = image.resize((max(int(w*scale),SIZE),max(int(h*scale),SIZE)), Image.Resampling.BICUBIC) - w, h = image.size - if w > SIZE: - left = (w - SIZE) // 2 - image = image.crop((left, left+SIZE, 0, SIZE)) - elif h > SIZE: - top = (h - SIZE) // 2 - image = image.crop((0, SIZE, top, top+SIZE)) - - x = Tensor(np.array(image.convert('RGB')), device=self.std.device) - x = x.permute(2, 0, 1).cast(dtypes.float32) / 255.0 - return (x - self.mean) / self.std - - def encode_tokens(self, tokens:Tensor) -> Tensor: - x = self.token_embedding(tokens) - x = x + self.positional_embedding - x = self.transformer(x, attn_mask=self.attn_mask) - x = self.ln_final(x) - x = x[:, tokens.argmax(axis=-1)] - x = x @ self.text_projection - return x - - def get_clip_score(self, tokens:Tensor, image:Tensor) -> Tensor: - image_features: Tensor = self.visual(image) - image_features /= image_features.square().sum(-1, keepdim=True).sqrt() # Frobenius Norm - - text_features = self.encode_tokens(tokens) - text_features /= text_features.square().sum(-1, keepdim=True).sqrt() # Frobenius Norm - - return (image_features * text_features).sum(axis=-1) diff --git a/tinygrad/extra/models/convnext.py b/tinygrad/extra/models/convnext.py deleted file mode 100644 index 7fb0da19..00000000 --- a/tinygrad/extra/models/convnext.py +++ /dev/null @@ -1,64 +0,0 @@ -from tinygrad.tensor import Tensor -from tinygrad.nn import Conv2d, LayerNorm, LayerNorm2d, Linear -from tinygrad.helpers import fetch, get_child - -class Block: - def __init__(self, dim): - self.dwconv = Conv2d(dim, dim, kernel_size=7, padding=3, groups=dim) - self.norm = LayerNorm(dim, eps=1e-6) - self.pwconv1 = Linear(dim, 4 * dim) - self.pwconv2 = Linear(4 * dim, dim) - self.gamma = Tensor.ones(dim) - - def __call__(self, x:Tensor): - return x + x.sequential([ - self.dwconv, lambda x: x.permute(0, 2, 3, 1), self.norm, - self.pwconv1, Tensor.gelu, self.pwconv2, lambda x: (self.gamma * x).permute(0, 3, 1, 2) - ]) - -class ConvNeXt: - def __init__(self, in_chans=3, num_classes=1000, depths=[3, 3, 9, 3], dims=[96, 192, 384, 768]): - self.downsample_layers = [ - [Conv2d(in_chans, dims[0], kernel_size=4, stride=4), LayerNorm2d(dims[0], eps=1e-6)], - *[[LayerNorm2d(dims[i], eps=1e-6), Conv2d(dims[i], dims[i+1], kernel_size=2, stride=2)] for i in range(len(dims)-1)] - ] - self.stages = [[Block(dims[i]) for _ in range(depths[i])] for i in range(len(dims))] - self.norm = LayerNorm(dims[-1]) - self.head = Linear(dims[-1], num_classes) - - def __call__(self, x:Tensor): - for downsample, stage in zip(self.downsample_layers, self.stages): - x = x.sequential(downsample).sequential(stage) - return x.mean([-2, -1]).sequential([self.norm, self.head]) - -# *** model definition is done *** - -versions = { - "tiny": {"depths": [3, 3, 9, 3], "dims": [96, 192, 384, 768]}, - "small": {"depths": [3, 3, 27, 3], "dims": [96, 192, 384, 768]}, - "base": {"depths": [3, 3, 9, 3], "dims": [128, 256, 512, 1024]}, - "large": {"depths": [3, 3, 27, 3], "dims": [192, 384, 768, 1536]}, - "xlarge": {"depths": [3, 3, 27, 3], "dims": [256, 512, 1024, 2048]} -} - -def get_model(version, load_weights=False): - model = ConvNeXt(**versions[version]) - if load_weights: - from tinygrad.nn.state import torch_load - weights = torch_load(fetch(f'https://dl.fbaipublicfiles.com/convnext/convnext_{version}_1k_224_ema.pth'))['model'] - for k,v in weights.items(): - mv = get_child(model, k) - mv.assign(v.reshape(mv.shape).to(mv.device)).realize() - return model - -if __name__ == "__main__": - model = get_model("tiny", True) - - # load image - from test.models.test_efficientnet import chicken_img, preprocess, _LABELS - img = Tensor(preprocess(chicken_img)) - - Tensor.training = False - - out = model(img).numpy() - print(_LABELS[out.argmax()]) diff --git a/tinygrad/extra/models/efficientnet.py b/tinygrad/extra/models/efficientnet.py deleted file mode 100644 index 81bda3d2..00000000 --- a/tinygrad/extra/models/efficientnet.py +++ /dev/null @@ -1,164 +0,0 @@ -import math -from tinygrad.tensor import Tensor -from tinygrad.nn import BatchNorm2d -from tinygrad.helpers import get_child, fetch -from tinygrad.nn.state import torch_load - -class MBConvBlock: - def __init__(self, kernel_size, strides, expand_ratio, input_filters, output_filters, se_ratio, has_se, track_running_stats=True): - oup = expand_ratio * input_filters - if expand_ratio != 1: - self._expand_conv = Tensor.glorot_uniform(oup, input_filters, 1, 1) - self._bn0 = BatchNorm2d(oup, track_running_stats=track_running_stats) - else: - self._expand_conv = None - - self.strides = strides - if strides == (2,2): - self.pad = [(kernel_size-1)//2-1, (kernel_size-1)//2]*2 - else: - self.pad = [(kernel_size-1)//2]*4 - - self._depthwise_conv = Tensor.glorot_uniform(oup, 1, kernel_size, kernel_size) - self._bn1 = BatchNorm2d(oup, track_running_stats=track_running_stats) - - self.has_se = has_se - if self.has_se: - num_squeezed_channels = max(1, int(input_filters * se_ratio)) - self._se_reduce = Tensor.glorot_uniform(num_squeezed_channels, oup, 1, 1) - self._se_reduce_bias = Tensor.zeros(num_squeezed_channels) - self._se_expand = Tensor.glorot_uniform(oup, num_squeezed_channels, 1, 1) - self._se_expand_bias = Tensor.zeros(oup) - - self._project_conv = Tensor.glorot_uniform(output_filters, oup, 1, 1) - self._bn2 = BatchNorm2d(output_filters, track_running_stats=track_running_stats) - - def __call__(self, inputs): - x = inputs - if self._expand_conv is not None: - x = self._bn0(x.conv2d(self._expand_conv)).swish() - x = x.conv2d(self._depthwise_conv, padding=self.pad, stride=self.strides, groups=self._depthwise_conv.shape[0]) - x = self._bn1(x).swish() - - if self.has_se: - x_squeezed = x.avg_pool2d(kernel_size=x.shape[2:4]) - x_squeezed = x_squeezed.conv2d(self._se_reduce, self._se_reduce_bias).swish() - x_squeezed = x_squeezed.conv2d(self._se_expand, self._se_expand_bias) - x = x.mul(x_squeezed.sigmoid()) - - x = self._bn2(x.conv2d(self._project_conv)) - if x.shape == inputs.shape: - x = x.add(inputs) - return x - -class EfficientNet: - def __init__(self, number=0, classes=1000, has_se=True, track_running_stats=True, input_channels=3, has_fc_output=True): - self.number = number - global_params = [ - # width, depth - (1.0, 1.0), # b0 - (1.0, 1.1), # b1 - (1.1, 1.2), # b2 - (1.2, 1.4), # b3 - (1.4, 1.8), # b4 - (1.6, 2.2), # b5 - (1.8, 2.6), # b6 - (2.0, 3.1), # b7 - (2.2, 3.6), # b8 - (4.3, 5.3), # l2 - ][max(number,0)] - - def round_filters(filters): - multiplier = global_params[0] - divisor = 8 - filters *= multiplier - new_filters = max(divisor, int(filters + divisor / 2) // divisor * divisor) - if new_filters < 0.9 * filters: # prevent rounding by more than 10% - new_filters += divisor - return int(new_filters) - - def round_repeats(repeats): - return int(math.ceil(global_params[1] * repeats)) - - out_channels = round_filters(32) - self._conv_stem = Tensor.glorot_uniform(out_channels, input_channels, 3, 3) - self._bn0 = BatchNorm2d(out_channels, track_running_stats=track_running_stats) - blocks_args = [ - [1, 3, (1,1), 1, 32, 16, 0.25], - [2, 3, (2,2), 6, 16, 24, 0.25], - [2, 5, (2,2), 6, 24, 40, 0.25], - [3, 3, (2,2), 6, 40, 80, 0.25], - [3, 5, (1,1), 6, 80, 112, 0.25], - [4, 5, (2,2), 6, 112, 192, 0.25], - [1, 3, (1,1), 6, 192, 320, 0.25], - ] - - if self.number == -1: - blocks_args = [ - [1, 3, (2,2), 1, 32, 40, 0.25], - [1, 3, (2,2), 1, 40, 80, 0.25], - [1, 3, (2,2), 1, 80, 192, 0.25], - [1, 3, (2,2), 1, 192, 320, 0.25], - ] - elif self.number == -2: - blocks_args = [ - [1, 9, (8,8), 1, 32, 320, 0.25], - ] - - self._blocks = [] - for num_repeats, kernel_size, strides, expand_ratio, input_filters, output_filters, se_ratio in blocks_args: - input_filters, output_filters = round_filters(input_filters), round_filters(output_filters) - for n in range(round_repeats(num_repeats)): - self._blocks.append(MBConvBlock(kernel_size, strides, expand_ratio, input_filters, output_filters, se_ratio, has_se=has_se, track_running_stats=track_running_stats)) - input_filters = output_filters - strides = (1,1) - - in_channels = round_filters(320) - out_channels = round_filters(1280) - self._conv_head = Tensor.glorot_uniform(out_channels, in_channels, 1, 1) - self._bn1 = BatchNorm2d(out_channels, track_running_stats=track_running_stats) - if has_fc_output: - self._fc = Tensor.glorot_uniform(out_channels, classes) - self._fc_bias = Tensor.zeros(classes) - else: - self._fc = None - - def forward(self, x): - x = self._bn0(x.conv2d(self._conv_stem, padding=(0,1,0,1), stride=2)).swish() - x = x.sequential(self._blocks) - x = self._bn1(x.conv2d(self._conv_head)).swish() - x = x.avg_pool2d(kernel_size=x.shape[2:4]) - x = x.reshape(shape=(-1, x.shape[1])) - return x.linear(self._fc, self._fc_bias) if self._fc is not None else x - - def load_from_pretrained(self): - model_urls = { - 0: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b0-355c32eb.pth", - 1: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b1-f1951068.pth", - 2: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b2-8bb594d6.pth", - 3: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b3-5fb5a3c3.pth", - 4: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b4-6ed6700e.pth", - 5: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b5-b6417697.pth", - 6: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b6-c76e70fd.pth", - 7: "https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b7-dcc49843.pth" - } - - b0 = torch_load(fetch(model_urls[self.number])) - for k,v in b0.items(): - if k.endswith("num_batches_tracked"): continue - for cat in ['_conv_head', '_conv_stem', '_depthwise_conv', '_expand_conv', '_fc', '_project_conv', '_se_reduce', '_se_expand']: - if cat in k: - k = k.replace('.bias', '_bias') - k = k.replace('.weight', '') - - #print(k, v.shape) - mv:Tensor = get_child(self, k) - vnp = v #.astype(np.float32) - vnp = vnp if k != '_fc' else vnp.T - #vnp = vnp if vnp.shape != () else np.array([vnp]) - - if mv.shape == vnp.shape: - mv.replace(vnp.to(mv.device)) - else: - print("MISMATCH SHAPE IN %s, %r %r" % (k, mv.shape, vnp.shape)) - diff --git a/tinygrad/extra/models/inception.py b/tinygrad/extra/models/inception.py deleted file mode 100644 index cf77a63e..00000000 --- a/tinygrad/extra/models/inception.py +++ /dev/null @@ -1,342 +0,0 @@ -from tinygrad import Tensor -from tinygrad.nn import Conv2d, BatchNorm2d, Linear -from tinygrad.nn.state import load_state_dict, torch_load -from tinygrad.helpers import fetch - -from typing import Optional, Dict -import numpy as np -from scipy import linalg - -# Base Inception Model - -class BasicConv2d: - def __init__(self, in_ch:int, out_ch:int, **kwargs): - self.conv = Conv2d(in_ch, out_ch, bias=False, **kwargs) - self.bn = BatchNorm2d(out_ch, eps=0.001) - - def __call__(self, x:Tensor) -> Tensor: - return x.sequential([self.conv, self.bn, Tensor.relu]) - -class InceptionA: - def __init__(self, in_ch:int, pool_feat:int): - self.branch1x1 = BasicConv2d(in_ch, 64, kernel_size=1) - - self.branch5x5_1 = BasicConv2d(in_ch, 48, kernel_size=1) - self.branch5x5_2 = BasicConv2d(48, 64, kernel_size=5, padding=2) - - self.branch3x3dbl_1 = BasicConv2d(in_ch, 64, kernel_size=1) - self.branch3x3dbl_2 = BasicConv2d(64, 96, kernel_size=(3,3), padding=1) - self.branch3x3dbl_3 = BasicConv2d(96, 96, kernel_size=(3,3), padding=1) - - self.branch_pool = BasicConv2d(in_ch, pool_feat, kernel_size=1) - - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - self.branch1x1(x), - x.sequential([self.branch5x5_1, self.branch5x5_2]), - x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2, self.branch3x3dbl_3]), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1)), - ] - return Tensor.cat(*outputs, dim=1) - -class InceptionB: - def __init__(self, in_ch:int): - self.branch3x3 = BasicConv2d(in_ch, 384, kernel_size=(3,3), stride=2) - - self.branch3x3dbl_1 = BasicConv2d(in_ch, 64, kernel_size=1) - self.branch3x3dbl_2 = BasicConv2d(64, 96, kernel_size=(3,3), padding=1) - self.branch3x3dbl_3 = BasicConv2d(96, 96, kernel_size=(3,3), stride=2) - - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - self.branch3x3(x), - x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2, self.branch3x3dbl_3]), - x.max_pool2d(kernel_size=(3,3), stride=2, dilation=1), - ] - return Tensor.cat(*outputs, dim=1) - -class InceptionC: - def __init__(self, in_ch, ch_7x7): - self.branch1x1 = BasicConv2d(in_ch, 192, kernel_size=1) - - self.branch7x7_1 = BasicConv2d(in_ch, ch_7x7, kernel_size=1) - self.branch7x7_2 = BasicConv2d(ch_7x7, ch_7x7, kernel_size=(1, 7), padding=(0, 3)) - self.branch7x7_3 = BasicConv2d(ch_7x7, 192, kernel_size=(7, 1), padding=(3, 0)) - - self.branch7x7dbl_1 = BasicConv2d(in_ch, ch_7x7, kernel_size=1) - self.branch7x7dbl_2 = BasicConv2d(ch_7x7, ch_7x7, kernel_size=(7, 1), padding=(3, 0)) - self.branch7x7dbl_3 = BasicConv2d(ch_7x7, ch_7x7, kernel_size=(1, 7), padding=(0, 3)) - self.branch7x7dbl_4 = BasicConv2d(ch_7x7, ch_7x7, kernel_size=(7, 1), padding=(3, 0)) - self.branch7x7dbl_5 = BasicConv2d(ch_7x7, 192, kernel_size=(1, 7), padding=(0, 3)) - - self.branch_pool = BasicConv2d(in_ch, 192, kernel_size=1) - - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - self.branch1x1(x), - x.sequential([self.branch7x7_1, self.branch7x7_2, self.branch7x7_3]), - x.sequential([self.branch7x7dbl_1, self.branch7x7dbl_2, self.branch7x7dbl_3, self.branch7x7dbl_4, self.branch7x7dbl_5]), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1)), - ] - return Tensor.cat(*outputs, dim=1) - -class InceptionD: - def __init__(self, in_ch:int): - self.branch3x3_1 = BasicConv2d(in_ch, 192, kernel_size=1) - self.branch3x3_2 = BasicConv2d(192, 320, kernel_size=(3,3), stride=2) - - self.branch7x7x3_1 = BasicConv2d(in_ch, 192, kernel_size=1) - self.branch7x7x3_2 = BasicConv2d(192, 192, kernel_size=(1, 7), padding=(0, 3)) - self.branch7x7x3_3 = BasicConv2d(192, 192, kernel_size=(7, 1), padding=(3, 0)) - self.branch7x7x3_4 = BasicConv2d(192, 192, kernel_size=(3,3), stride=2) - - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - x.sequential([self.branch3x3_1, self.branch3x3_2]), - x.sequential([self.branch7x7x3_1, self.branch7x7x3_2, self.branch7x7x3_3, self.branch7x7x3_4]), - x.max_pool2d(kernel_size=(3,3), stride=2, dilation=1), - ] - return Tensor.cat(*outputs, dim=1) - -class InceptionE: - def __init__(self, in_ch:int): - self.branch1x1 = BasicConv2d(in_ch, 320, kernel_size=1) - - self.branch3x3_1 = BasicConv2d(in_ch, 384, kernel_size=1) - self.branch3x3_2a = BasicConv2d(384, 384, kernel_size=(1, 3), padding=(0, 1)) - self.branch3x3_2b = BasicConv2d(384, 384, kernel_size=(3, 1), padding=(1, 0)) - - self.branch3x3dbl_1 = BasicConv2d(in_ch, 448, kernel_size=1) - self.branch3x3dbl_2 = BasicConv2d(448, 384, kernel_size=(3,3), padding=1) - self.branch3x3dbl_3a = BasicConv2d(384, 384, kernel_size=(1, 3), padding=(0, 1)) - self.branch3x3dbl_3b = BasicConv2d(384, 384, kernel_size=(3, 1), padding=(1, 0)) - - self.branch_pool = BasicConv2d(in_ch, 192, kernel_size=1) - - def __call__(self, x:Tensor) -> Tensor: - branch3x3 = self.branch3x3_1(x) - branch3x3dbl = x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2]) - outputs = [ - self.branch1x1(x), - Tensor.cat(self.branch3x3_2a(branch3x3), self.branch3x3_2b(branch3x3), dim=1), - Tensor.cat(self.branch3x3dbl_3a(branch3x3dbl), self.branch3x3dbl_3b(branch3x3dbl), dim=1), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1)), - ] - return Tensor.cat(*outputs, dim=1) - -class InceptionAux: - def __init__(self, in_ch:int, num_classes:int): - self.conv0 = BasicConv2d(in_ch, 128, kernel_size=1) - self.conv1 = BasicConv2d(128, 768, kernel_size=5) - self.fc = Linear(768, num_classes) - - def __call__(self, x:Tensor) -> Tensor: - x = x.avg_pool2d(kernel_size=5, stride=3, padding=1).sequential([self.conv0, self.conv1]) - x = x.avg_pool2d(kernel_size=1, padding=1).reshape(x.shape[0],-1) - return self.fc(x) - -class Inception3: - def __init__(self, num_classes:int=1008, cls_map:Optional[Dict]=None): - def get_cls(key1:str, key2:str, default): - return default if cls_map is None else cls_map.get(key1, cls_map.get(key2, default)) - - self.transform_input = False - self.Conv2d_1a_3x3 = BasicConv2d(3, 32, kernel_size=(3,3), stride=2) - self.Conv2d_2a_3x3 = BasicConv2d(32, 32, kernel_size=(3,3)) - self.Conv2d_2b_3x3 = BasicConv2d(32, 64, kernel_size=(3,3), padding=1) - self.maxpool1 = lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=2, padding=1) - self.Conv2d_3b_1x1 = BasicConv2d(64, 80, kernel_size=1) - self.Conv2d_4a_3x3 = BasicConv2d(80, 192, kernel_size=(3,3)) - self.maxpool2 = lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=2, padding=1) - self.Mixed_5b = get_cls("A1","A",InceptionA)(192, pool_feat=32) - self.Mixed_5c = get_cls("A2","A",InceptionA)(256, pool_feat=64) - self.Mixed_5d = get_cls("A3","A",InceptionA)(288, pool_feat=64) - self.Mixed_6a = get_cls("B1","B",InceptionB)(288) - self.Mixed_6b = get_cls("C1","C",InceptionC)(768, ch_7x7=128) - self.Mixed_6c = get_cls("C2","C",InceptionC)(768, ch_7x7=160) - self.Mixed_6d = get_cls("C3","C",InceptionC)(768, ch_7x7=160) - self.Mixed_6e = get_cls("C4","C",InceptionC)(768, ch_7x7=192) - self.Mixed_7a = get_cls("D1","D",InceptionD)(768) - self.Mixed_7b = get_cls("E1","E",InceptionE)(1280) - self.Mixed_7c = get_cls("E2","E",InceptionE)(2048) - self.avgpool = lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8), padding=1) - self.fc = Linear(2048, num_classes) - - def __call__(self, x:Tensor) -> Tensor: - return x.sequential([ - self.Conv2d_1a_3x3, - self.Conv2d_2a_3x3, - self.Conv2d_2b_3x3, - self.maxpool1, - - self.Conv2d_3b_1x1, - self.Conv2d_4a_3x3, - self.maxpool2, - - self.Mixed_5b, - self.Mixed_5c, - self.Mixed_5d, - self.Mixed_6a, - self.Mixed_6b, - self.Mixed_6c, - self.Mixed_6d, - self.Mixed_6e, - - self.Mixed_7a, - self.Mixed_7b, - self.Mixed_7c, - self.avgpool, - - lambda y: y.reshape(x.shape[0],-1), - self.fc, - ]) - - -# FID Inception Variation - -class FidInceptionA(InceptionA): - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - self.branch1x1(x), - x.sequential([self.branch5x5_1, self.branch5x5_2]), - x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2, self.branch3x3dbl_3]), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1, count_include_pad=False)) - ] - return Tensor.cat(*outputs, dim=1) - -class FidInceptionC(InceptionC): - def __call__(self, x:Tensor) -> Tensor: - outputs = [ - self.branch1x1(x), - x.sequential([self.branch7x7_1, self.branch7x7_2, self.branch7x7_3]), - x.sequential([self.branch7x7dbl_1, self.branch7x7dbl_2, self.branch7x7dbl_3, self.branch7x7dbl_4, self.branch7x7dbl_5]), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1, count_include_pad=False)) - ] - return Tensor.cat(*outputs, dim=1) - -class FidInceptionE1(InceptionE): - def __call__(self, x:Tensor) -> Tensor: - branch3x3 = self.branch3x3_1(x) - branch3x3dbl = x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2]) - outputs = [ - self.branch1x1(x), - Tensor.cat(self.branch3x3_2a(branch3x3), self.branch3x3_2b(branch3x3), dim=1), - Tensor.cat(self.branch3x3dbl_3a(branch3x3dbl), self.branch3x3dbl_3b(branch3x3dbl), dim=1), - self.branch_pool(x.avg_pool2d(kernel_size=(3,3), stride=1, padding=1, count_include_pad=False)), - ] - return Tensor.cat(*outputs, dim=1) - -class FidInceptionE2(InceptionE): - def __call__(self, x:Tensor) -> Tensor: - branch3x3 = self.branch3x3_1(x) - branch3x3dbl = x.sequential([self.branch3x3dbl_1, self.branch3x3dbl_2]) - outputs = [ - self.branch1x1(x), - Tensor.cat(self.branch3x3_2a(branch3x3), self.branch3x3_2b(branch3x3), dim=1), - Tensor.cat(self.branch3x3dbl_3a(branch3x3dbl), self.branch3x3dbl_3b(branch3x3dbl), dim=1), - self.branch_pool(x.max_pool2d(kernel_size=(3,3), stride=1, padding=1)), - ] - return Tensor.cat(*outputs, dim=1) - -class FidInceptionV3: - m1: Optional[np.ndarray] = None - s1: Optional[np.ndarray] = None - - def __init__(self): - inception = Inception3(cls_map={ - "A": FidInceptionA, - "C": FidInceptionC, - "E1": FidInceptionE1, - "E2": FidInceptionE2, - }) - - self.Conv2d_1a_3x3 = inception.Conv2d_1a_3x3 - self.Conv2d_2a_3x3 = inception.Conv2d_2a_3x3 - self.Conv2d_2b_3x3 = inception.Conv2d_2b_3x3 - - self.Conv2d_3b_1x1 = inception.Conv2d_3b_1x1 - self.Conv2d_4a_3x3 = inception.Conv2d_4a_3x3 - - self.Mixed_5b = inception.Mixed_5b - self.Mixed_5c = inception.Mixed_5c - self.Mixed_5d = inception.Mixed_5d - self.Mixed_6a = inception.Mixed_6a - self.Mixed_6b = inception.Mixed_6b - self.Mixed_6c = inception.Mixed_6c - self.Mixed_6d = inception.Mixed_6d - self.Mixed_6e = inception.Mixed_6e - - self.Mixed_7a = inception.Mixed_7a - self.Mixed_7b = inception.Mixed_7b - self.Mixed_7c = inception.Mixed_7c - - def load_from_pretrained(self): - state_dict = torch_load(str(fetch("https://github.com/mseitzer/pytorch-fid/releases/download/fid_weights/pt_inception-2015-12-05-6726825d.pth", "pt_inception-2015-12-05-6726825d.pth"))) - for k,v in state_dict.items(): - if k.endswith(".num_batches_tracked"): - state_dict[k] = v.reshape(1) - load_state_dict(self, state_dict) - return self - - def __call__(self, x:Tensor) -> Tensor: - x = x.interpolate((299,299), mode="linear") - x = (x * 2) - 1 - x = x.sequential([ - self.Conv2d_1a_3x3, - self.Conv2d_2a_3x3, - self.Conv2d_2b_3x3, - lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=2, dilation=1), - - self.Conv2d_3b_1x1, - self.Conv2d_4a_3x3, - lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=2, dilation=1), - - self.Mixed_5b, - self.Mixed_5c, - self.Mixed_5d, - self.Mixed_6a, - self.Mixed_6b, - self.Mixed_6c, - self.Mixed_6d, - self.Mixed_6e, - - self.Mixed_7a, - self.Mixed_7b, - self.Mixed_7c, - lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8)), - ]) - return x - - def compute_score(self, inception_activations:Tensor, val_stats_path:str) -> float: - if self.m1 is None and self.s1 is None: - with np.load(val_stats_path) as f: - self.m1, self.s1 = f['mu'][:], f['sigma'][:] - assert self.m1 is not None and self.s1 is not None - - m2 = inception_activations.mean(axis=0).numpy() - s2 = np.cov(inception_activations.numpy(), rowvar=False) - - return calculate_frechet_distance(self.m1, self.s1, m2, s2) - -def calculate_frechet_distance(mu1:np.ndarray, sigma1:np.ndarray, mu2:np.ndarray, sigma2:np.ndarray, eps:float=1e-6) -> float: - mu1 = np.atleast_1d(mu1) - mu2 = np.atleast_1d(mu2) - sigma1 = np.atleast_2d(sigma1) - sigma2 = np.atleast_2d(sigma2) - assert mu1.shape == mu2.shape and sigma1.shape == sigma2.shape - - diff = mu1 - mu2 - covmean, _ = linalg.sqrtm(sigma1.dot(sigma2), disp=False) - if not np.isfinite(covmean).all(): - offset = np.eye(sigma1.shape[0]) * eps - covmean = linalg.sqrtm((sigma1 + offset).dot(sigma2 + offset)) - - if np.iscomplexobj(covmean): - if not np.allclose(np.diagonal(covmean).imag, 0, atol=1e-3): - m = np.max(np.abs(covmean.imag)) - raise ValueError(f"Imaginary component {m}") - covmean = covmean.real - - tr_covmean = np.trace(covmean) - - return diff.dot(diff) + np.trace(sigma1) + np.trace(sigma2) - 2*tr_covmean diff --git a/tinygrad/extra/models/llama.py b/tinygrad/extra/models/llama.py deleted file mode 100644 index 002c0cce..00000000 --- a/tinygrad/extra/models/llama.py +++ /dev/null @@ -1,254 +0,0 @@ -from typing import Union, Optional, Any -import collections -from tinygrad import Tensor, Variable, TinyJit, dtypes, nn, Device -from tinygrad.helpers import getenv, DEBUG - -# https://github.com/facebookresearch/llama/blob/1076b9c51c77ad06e9d7ba8a4c6df775741732bd/llama/model.py#L47 -def precompute_freqs_cis(dim: int, end: int, theta: float = 10000.0) -> Tensor: - freqs = 1.0 / (theta ** (Tensor.arange(0, dim, 2)[:(dim // 2)] / dim)) - freqs = Tensor.arange(end).unsqueeze(dim=1) * freqs.unsqueeze(dim=0) - return Tensor.stack(freqs.cos(), freqs.sin(), dim=-1).reshape(1, end, 1, dim//2, 2) - -# matches meta, non hugging face weights -# (a+i*b) * (c+i*d) = (ac-bd) + i*(ad+bc) -def complex_mult(A, c, d): - a,b = A[..., 0:1], A[..., 1:2] - ro = a*c - b*d - co = a*d + b*c - return ro.cat(co, dim=-1) - -def apply_rotary_emb(xq:Tensor, xk:Tensor, freqs_cis:Tensor) -> tuple[Tensor, Tensor]: - assert freqs_cis.shape[1] == xq.shape[1] == xk.shape[1], f"freqs_cis shape mismatch {freqs_cis.shape} xq:{xq.shape} xk:{xk.shape}" - xq = xq.reshape(*xq.shape[0:-1], -1, 2) - xk = xk.reshape(*xk.shape[0:-1], -1, 2) - assert len(xq.shape) == len(xk.shape) == len(freqs_cis.shape) == 5 - c, d = freqs_cis[..., 0:1], freqs_cis[..., 1:2] - xq_out = complex_mult(xq, c, d) - xk_out = complex_mult(xk, c, d) - return xq_out.flatten(3), xk_out.flatten(3) - -def repeat_kv(x:Tensor, n_rep:int) -> Tensor: - bs, seqlen, n_kv_heads, head_dim = x.shape - if n_rep == 1: return x - # NOTE: this is different from x.repeat((1, 1, n_rep, 1)) - return x.repeat((1, 1, 1, n_rep)).reshape(bs, seqlen, n_kv_heads * n_rep, head_dim) - -class Attention: - def __init__(self, dim, n_heads, n_kv_heads=None, max_context=0, linear=nn.Linear, qk_norm:float|None=None): - self.n_heads = n_heads - self.n_kv_heads = n_kv_heads if n_kv_heads is not None else n_heads # n_kv_heads != n_heads implies MQA [arxiv/2307.09288, A.2.1] - self.head_dim = dim // n_heads - self.n_rep = self.n_heads // self.n_kv_heads - self.max_context = max_context - - self.wq = linear(dim, self.n_heads * self.head_dim, bias=False) - self.wk = linear(dim, self.n_kv_heads * self.head_dim, bias=False) - self.wv = linear(dim, self.n_kv_heads * self.head_dim, bias=False) - self.wo = linear(self.n_heads * self.head_dim, dim, bias=False) - - self.q_norm = nn.RMSNorm(dim, qk_norm) if qk_norm is not None else None - self.k_norm = nn.RMSNorm(dim, qk_norm) if qk_norm is not None else None - - def __call__(self, x:Tensor, start_pos:Union[Variable,int], freqs_cis:Tensor, mask:Optional[Tensor]=None) -> Tensor: - if getenv("WQKV"): - if not hasattr(self, 'wqkv'): self.wqkv = Tensor.cat(self.wq.weight, self.wk.weight, self.wv.weight) - xqkv = x @ self.wqkv.T - xq, xk, xv = xqkv.split([self.wq.weight.shape[0], self.wk.weight.shape[0], self.wv.weight.shape[0]], dim=2) - else: - xq, xk, xv = self.wq(x), self.wk(x), self.wv(x) - - if self.q_norm is not None and self.k_norm is not None: - xq = self.q_norm(xq) - xk = self.k_norm(xk) - - xq = xq.reshape(xq.shape[0], xq.shape[1], self.n_heads, self.head_dim) - xk = xk.reshape(xk.shape[0], xk.shape[1], self.n_kv_heads, self.head_dim) - xv = xv.reshape(xv.shape[0], xv.shape[1], self.n_kv_heads, self.head_dim) - - xq, xk = apply_rotary_emb(xq, xk, freqs_cis) - bsz, seqlen, _, _ = xq.shape - - # create kv cache - if self.max_context: - if not hasattr(self, "cache_kv"): - self.cache_kv = Tensor.zeros(2, bsz, self.max_context, self.n_kv_heads, self.head_dim, dtype=x.dtype).contiguous().realize() - if isinstance(x.device, tuple): - # TODO: instead of specifying how to shard, it can follow how xk and xv are being sharded - self.cache_kv.shard_((x.device), axis=3 if getenv("SHARD_KVCACHE") else None).realize() - - # update the cache - assert xk.dtype == xv.dtype == self.cache_kv.dtype, f"{xk.dtype=}, {xv.dtype=}, {self.cache_kv.dtype=}" - self.cache_kv[:, :, start_pos:start_pos+seqlen, :, :].assign(Tensor.stack(xk, xv)).realize() - - keys = self.cache_kv[0, :, 0:start_pos+seqlen, :, :] - values = self.cache_kv[1, :, 0:start_pos+seqlen, :, :] - else: - assert start_pos == 0 - keys, values = xk, xv - - keys, values = repeat_kv(keys, self.n_rep), repeat_kv(values, self.n_rep) - xq, keys, values = xq.transpose(1, 2), keys.transpose(1, 2), values.transpose(1, 2) - attn = xq.scaled_dot_product_attention(keys, values, mask).transpose(1, 2) - attn = attn.reshape(bsz, seqlen, -1) - return self.wo(attn) - -class FeedForward: - def __init__(self, dim:int, hidden_dim:int, linear=nn.Linear): - self.w1 = linear(dim, hidden_dim, bias=False) - self.w2 = linear(hidden_dim, dim, bias=False) - self.w3 = linear(dim, hidden_dim, bias=False) # the gate in Gated Linear Unit - - def __call__(self, x:Tensor) -> Tensor: - return self.w2(self.w1(x).silu() * self.w3(x)) # SwiGLU [arxiv/2002.05202, eq (5)] - -class TransformerBlock: - def __init__(self, dim:int, hidden_dim:int, n_heads:int, n_kv_heads:int, norm_eps:float, max_context:int, linear=nn.Linear, - feed_forward=FeedForward, qk_norm=None): - self.attention = Attention(dim, n_heads, n_kv_heads, max_context, linear, qk_norm) - self.feed_forward = feed_forward(dim, hidden_dim, linear) - self.attention_norm = nn.RMSNorm(dim, norm_eps) - self.ffn_norm = nn.RMSNorm(dim, norm_eps) - - def __call__(self, x:Tensor, start_pos:Union[Variable,int], freqs_cis:Tensor, mask:Optional[Tensor]): - h = x + self.attention(self.attention_norm(x), start_pos, freqs_cis, mask) - return (h + self.feed_forward(self.ffn_norm(h))).contiguous() - -# standard openai sampling -def sample(logits: Tensor, temp: float, k: int, p: float, af: float, ap: float): - assert logits.ndim == 1, "only works on 1d tensors" - assert 0 <= p <= 1, "p must be between 0 and 1" - assert 0 <= k <= logits.numel(), "k must be between 0 and numel" - - # if temperature is very low just use argmax - if temp < 1e-6: return logits.argmax() - - logits = logits.to(Device.DEFAULT) - - # alpha sampling - if af or ap: - if not hasattr(sample, "alpha_counter"): - setattr(sample, "alpha_counter", Tensor.zeros_like(logits, dtype=dtypes.int32).contiguous()) - logits = logits - (sample.alpha_counter * af + (sample.alpha_counter > 0) * ap) - - # replace NaNs with -inf - logits = (logits != logits).where(-float("inf"), logits) - - # softmax - t = (logits / temp).softmax() - - counter, counter2 = Tensor.arange(t.numel(), device=logits.device).contiguous(), Tensor.arange(t.numel() - 1, -1, -1, device=logits.device).contiguous() - # top k - if k: - output, output_indices = Tensor.zeros(k, device=logits.device).contiguous(), Tensor.zeros(k, device=logits.device, dtype=dtypes.int32).contiguous() - for i in range(k): - t_argmax = (t.numel() - ((t == (t_max := t.max())) * counter2).max() - 1).cast(dtypes.default_int) - output = output + t_max.unsqueeze(0).pad(((i, k - i - 1),)) - output_indices = output_indices + t_argmax.unsqueeze(0).pad(((i, k - i - 1),)) - t = (counter == t_argmax).where(0, t) - - # approximate top p - # because we are already limited to top k elements we can do top p "without sorting" - output_cumsum = output[::-1].cumsum()[::-1] + t.sum() - output = (output_cumsum >= (1 - p)) * output - output_indices = (output_cumsum >= (1 - p)) * output_indices - - # sample - output_idx = output.multinomial() - output_token = output_indices[output_idx] - else: - output_token = t.multinomial() - - # increase alpha counter - if af or ap: - sample.alpha_counter = (counter == output_token).where(sample.alpha_counter + 1, sample.alpha_counter) - - return output_token - -class Transformer: - def __init__(self, dim:int, hidden_dim:int, n_heads:int, n_layers:int, norm_eps:float, vocab_size, linear=nn.Linear, embedding=nn.Embedding, - n_kv_heads=None, rope_theta=10000, max_context=1024, jit=True, feed_forward=FeedForward, qk_norm=None): - self.layers = [TransformerBlock(dim, hidden_dim, n_heads, n_kv_heads, norm_eps, max_context, linear, feed_forward=feed_forward, qk_norm=qk_norm) for _ in range(n_layers)] - self.norm = nn.RMSNorm(dim, norm_eps) - self.tok_embeddings = embedding(vocab_size, dim) - self.output = nn.Linear(dim, vocab_size, bias=False) if embedding == nn.Embedding else linear(dim, vocab_size, bias=False) - self.max_context = max_context - self.freqs_cis = precompute_freqs_cis(dim // n_heads, self.max_context * 2, rope_theta).contiguous() - self.forward_jit = TinyJit(self.forward) if jit else None - - def forward(self, tokens:Tensor, start_pos:Union[Variable,int], temperature:float, top_k:int, top_p:float, alpha_f:float, alpha_p:float): - _bsz, seqlen = tokens.shape - h = self.tok_embeddings(tokens) - - self.freqs_cis = self.freqs_cis.cast(h.dtype).kernelize() - freqs_cis = self.freqs_cis[:, start_pos:start_pos+seqlen, :, :, :] - - mask = Tensor.full((1, 1, seqlen, start_pos+seqlen), float("-inf"), dtype=h.dtype, device=h.device).triu(start_pos+1).kernelize() if seqlen > 1 else None - for layer in self.layers: h = layer(h, start_pos, freqs_cis, mask) - logits = self.output(self.norm(h)).float()[:, -1, :] - - return sample(logits.flatten(), temperature, top_k, top_p, alpha_f, alpha_p).kernelize() - - def __call__(self, tokens:Tensor, start_pos:int, temperature:float=0.0, top_k:int=0, top_p:float=0.8, alpha_f:float=0.0, alpha_p:float=0.0): - # TODO: better way to handle the first call v.s. the rest? - if tokens.shape[0:2] == (1,1) and self.forward_jit is not None and start_pos != 0: - return self.forward_jit(tokens, Variable("start_pos", 1, self.max_context-1).bind(start_pos), temperature, top_k, top_p, alpha_f, alpha_p) - return self.forward(tokens, start_pos, temperature, top_k, top_p, alpha_f, alpha_p) - -# *** helpers *** - -# TODO: n_kv_heads should support None -def convert_from_huggingface(weights:dict[str, Tensor], n_layers: int, n_heads: int, n_kv_heads: int, permute_layers: bool = True): - # huggingface stores Q and K permuted! it is mostly correct without this, but without it makes RoPE different, so it will diverge after 10+ toks. - def permute(v: Tensor, n_heads: int): - return v.reshape(n_heads, 2, v.shape[0] // n_heads // 2, v.shape[1] if len(v.shape) > 1 else 1).transpose(1, 2).reshape(*v.shape[:2]) - - keymap = { - "model.embed_tokens.weight": "tok_embeddings.weight", - **{f"model.layers.{l}.input_layernorm.weight": f"layers.{l}.attention_norm.weight" for l in range(n_layers)}, - **{f"model.layers.{l}.self_attn.{x}_norm.weight": f"layers.{l}.attention.{x}_norm.weight" for x in ["q", "k"] for l in range(n_layers)}, - **{f"model.layers.{l}.self_attn.{x}_proj.weight": f"layers.{l}.attention.w{x}.weight" for x in ["q", "k", "v", "o"] for l in range(n_layers)}, - **{f"model.layers.{l}.self_attn.{x}_proj.bias": f"layers.{l}.attention.w{x}.bias" for x in ["q", "k", "v", "o"] for l in range(n_layers)}, - **{f"model.layers.{l}.post_attention_layernorm.weight": f"layers.{l}.ffn_norm.weight" for l in range(n_layers)}, - **{f"model.layers.{l}.mlp.{x}_proj.weight": f"layers.{l}.feed_forward.w{y}.weight" for x, y in {"gate": "1", "down": "2", "up": "3"}.items() for l in range(n_layers)}, - **{f"model.layers.{l}.mlp.gate.weight": f"layers.{l}.feed_forward.gate.weight" for l in range(n_layers)}, - "model.norm.weight": "norm.weight", - "lm_head.weight": "output.weight", - } - sd = {} - experts = collections.defaultdict(dict) - for k, v in weights.items(): - if ".rotary_emb." in k: continue - v = v.to(Device.DEFAULT) - if "model.layers" in k: - if ("q_proj" in k or "q_norm" in k) and permute_layers: v = permute(v, n_heads) - elif ("k_proj" in k or "k_norm" in k) and permute_layers: v = permute(v, n_kv_heads) - if '.mlp.experts.' in k: - # support MoE models - _, _, layer, _, _, expert, name, _ = k.split('.') - experts[f'layers.{layer}.feed_forward.{name}'][int(expert)] = v - continue - sd[keymap[k]] = v - for k,v in experts.items(): sd[k] = Tensor.stack(*[v[i] for i in range(len(v))]) - return sd - -def convert_from_gguf(weights:dict[str, Tensor], n_layers:int): - keymap = { - "token_embd.weight": "tok_embeddings.weight", - **{f"blk.{l}.attn_norm.weight": f"layers.{l}.attention_norm.weight" for l in range(n_layers)}, - **{f"blk.{l}.attn_{x}.weight": f"layers.{l}.attention.w{x}.weight" for x in ["q", "k", "v"] for l in range(n_layers)}, - **{f"blk.{l}.attn_output.weight": f"layers.{l}.attention.wo.weight" for l in range(n_layers)}, - **{f"blk.{l}.ffn_norm.weight": f"layers.{l}.ffn_norm.weight" for l in range(n_layers)}, - **{f"blk.{l}.ffn_{x}.weight": f"layers.{l}.feed_forward.w{y}.weight" for x, y in {"gate": "1", "down": "2", "up": "3"}.items() for l in range(n_layers)}, - "output_norm.weight": "norm.weight", - "rope_freqs.weight": "rope_freqs.weight", - } - sd = {keymap[k]: v for k,v in weights.items()} - sd["output.weight"] = weights["token_embd.weight"] - return sd - -def fix_bf16(weights:dict[Any, Tensor]): - if getenv("SUPPORT_BF16", 1): - # TODO: without casting to float16, 70B llama OOM on tinybox. - return {k:v.cast(dtypes.float32).cast(dtypes.float16) if v.dtype == dtypes.bfloat16 else v for k,v in weights.items()} - # TODO: check if device supports bf16 - return {k:v.llvm_bf16_cast(dtypes.half).to(v.device) if v.dtype == dtypes.bfloat16 else v for k,v in weights.items()} diff --git a/tinygrad/extra/models/mask_rcnn.py b/tinygrad/extra/models/mask_rcnn.py deleted file mode 100644 index 052ccd23..00000000 --- a/tinygrad/extra/models/mask_rcnn.py +++ /dev/null @@ -1,1214 +0,0 @@ -import re -import math -import os -import numpy as np -from pathlib import Path -from tinygrad import nn, Tensor, dtypes -from tinygrad.tensor import _to_np_dtype -from tinygrad.helpers import get_child, fetch -from tinygrad.nn.state import torch_load -from examples.mlperf.helpers import BoxCoder -from extra.models.resnet import ResNet -from extra.models.retinanet import nms as _box_nms - -USE_NP_GATHER = os.getenv('FULL_TINYGRAD', '0') == '0' - -def rint(tensor): - x = (tensor*2).cast(dtypes.int32).contiguous().cast(dtypes.float32)/2 - return (x<0).where(x.floor(), x.ceil()) - -def nearest_interpolate(tensor, scale_factor): - bs, c, py, px = tensor.shape - return tensor.reshape(bs, c, py, 1, px, 1).expand(bs, c, py, scale_factor, px, scale_factor).reshape(bs, c, py * scale_factor, px * scale_factor) - -def meshgrid(x, y): - grid_x = Tensor.cat(*[x[idx:idx+1].expand(y.shape).unsqueeze(0) for idx in range(x.shape[0])]) - grid_y = Tensor.cat(*[y.unsqueeze(0)]*x.shape[0]) - return grid_x.reshape(-1, 1), grid_y.reshape(-1, 1) - -def topk(input_, k, dim=-1, largest=True, sorted=False): - k = min(k, input_.shape[dim]-1) - input_ = input_.numpy() - if largest: input_ *= -1 - ind = np.argpartition(input_, k, axis=dim) - if largest: input_ *= -1 - ind = np.take(ind, np.arange(k), axis=dim) # k non-sorted indices - input_ = np.take_along_axis(input_, ind, axis=dim) # k non-sorted values - if not sorted: return Tensor(input_), ind - if largest: input_ *= -1 - ind_part = np.argsort(input_, axis=dim) - ind = np.take_along_axis(ind, ind_part, axis=dim) - if largest: input_ *= -1 - val = np.take_along_axis(input_, ind_part, axis=dim) - return Tensor(val), ind - -# This is very slow for large arrays, or indices -def _gather(array, indices): - indices = indices.float().to(array.device) - reshape_arg = [1]*array.ndim + [array.shape[-1]] - return Tensor.where( - indices.unsqueeze(indices.ndim).expand(*indices.shape, array.shape[-1]) == Tensor.arange(array.shape[-1]).reshape(*reshape_arg).expand(*indices.shape, array.shape[-1]), - array, 0, - ).sum(indices.ndim) - -# TODO: replace npgather with a faster gather using tinygrad only -# NOTE: this blocks the gradient -def npgather(array,indices): - if isinstance(array, Tensor): array = array.numpy() - if isinstance(indices, Tensor): indices = indices.numpy() - if isinstance(indices, list): indices = np.asarray(indices) - return Tensor(array[indices.astype(int)]) - -def get_strides(shape): - prod = [1] - for idx in range(len(shape)-1, -1, -1): prod.append(prod[-1] * shape[idx]) - # something about ints is broken with gpu, cuda - return Tensor(prod[::-1][1:], dtype=dtypes.int32).unsqueeze(0) - -# with keys as integer array for all axes -def tensor_getitem(tensor, *keys): - # something about ints is broken with gpu, cuda - flat_keys = Tensor.stack(*[key.expand((sum(keys)).shape).reshape(-1) for key in keys], dim=1).cast(dtypes.int32) - strides = get_strides(tensor.shape) - idxs = (flat_keys * strides).sum(1) - gatherer = npgather if USE_NP_GATHER else _gather - return gatherer(tensor.reshape(-1), idxs).reshape(sum(keys).shape) - - -# for gather with indicies only on axis=0 -def tensor_gather(tensor, indices): - if not isinstance(indices, Tensor): - indices = Tensor(indices, requires_grad=False) - if len(tensor.shape) > 2: - rem_shape = list(tensor.shape)[1:] - tensor = tensor.reshape(tensor.shape[0], -1) - else: - rem_shape = None - if len(tensor.shape) > 1: - tensor = tensor.T - repeat_arg = [1]*(tensor.ndim-1) + [tensor.shape[-2]] - indices = indices.unsqueeze(indices.ndim).repeat(repeat_arg) - ret = _gather(tensor, indices) - if rem_shape: - ret = ret.reshape([indices.shape[0]] + rem_shape) - else: - ret = _gather(tensor, indices) - del indices - return ret - - -class LastLevelMaxPool: - def __call__(self, x): return [Tensor.max_pool2d(x, 1, 2)] - - -# transpose -FLIP_LEFT_RIGHT = 0 -FLIP_TOP_BOTTOM = 1 - - -def permute_and_flatten(layer:Tensor, N, A, C, H, W): - layer = layer.reshape(N, -1, C, H, W) - layer = layer.permute(0, 3, 4, 1, 2) - layer = layer.reshape(N, -1, C) - return layer - - -class BoxList: - def __init__(self, bbox, image_size, mode="xyxy"): - if not isinstance(bbox, Tensor): - bbox = Tensor(bbox) - if bbox.ndim != 2: - raise ValueError( - "bbox should have 2 dimensions, got {}".format(bbox.ndim) - ) - if bbox.shape[-1] != 4: - raise ValueError( - "last dimenion of bbox should have a " - "size of 4, got {}".format(bbox.shape[-1]) - ) - if mode not in ("xyxy", "xywh"): - raise ValueError("mode should be 'xyxy' or 'xywh'") - - self.bbox = bbox - self.size = image_size # (image_width, image_height) - self.mode = mode - self.extra_fields = {} - - def __repr__(self): - s = self.__class__.__name__ + "(" - s += "num_boxes={}, ".format(len(self)) - s += "image_width={}, ".format(self.size[0]) - s += "image_height={}, ".format(self.size[1]) - s += "mode={})".format(self.mode) - return s - - def area(self): - box = self.bbox - if self.mode == "xyxy": - TO_REMOVE = 1 - area = (box[:, 2] - box[:, 0] + TO_REMOVE) * (box[:, 3] - box[:, 1] + TO_REMOVE) - elif self.mode == "xywh": - area = box[:, 2] * box[:, 3] - return area - - def add_field(self, field, field_data): - self.extra_fields[field] = field_data - - def get_field(self, field): - return self.extra_fields[field] - - def has_field(self, field): - return field in self.extra_fields - - def fields(self): - return list(self.extra_fields.keys()) - - def _copy_extra_fields(self, bbox): - for k, v in bbox.extra_fields.items(): - self.extra_fields[k] = v - - def convert(self, mode): - if mode == self.mode: - return self - xmin, ymin, xmax, ymax = self._split_into_xyxy() - if mode == "xyxy": - bbox = Tensor.cat(*(xmin, ymin, xmax, ymax), dim=-1) - bbox = BoxList(bbox, self.size, mode=mode) - else: - TO_REMOVE = 1 - bbox = Tensor.cat( - *(xmin, ymin, xmax - xmin + TO_REMOVE, ymax - ymin + TO_REMOVE), dim=-1 - ) - bbox = BoxList(bbox, self.size, mode=mode) - bbox._copy_extra_fields(self) - return bbox - - def _split_into_xyxy(self): - if self.mode == "xyxy": - xmin, ymin, xmax, ymax = self.bbox.chunk(4, dim=-1) - return xmin, ymin, xmax, ymax - if self.mode == "xywh": - TO_REMOVE = 1 - xmin, ymin, w, h = self.bbox.chunk(4, dim=-1) - return ( - xmin, - ymin, - xmin + (w - TO_REMOVE).clamp(min=0), - ymin + (h - TO_REMOVE).clamp(min=0), - ) - - def resize(self, size, *args, **kwargs): - ratios = tuple(float(s) / float(s_orig) for s, s_orig in zip(size, self.size)) - if ratios[0] == ratios[1]: - ratio = ratios[0] - scaled_box = self.bbox * ratio - bbox = BoxList(scaled_box, size, mode=self.mode) - for k, v in self.extra_fields.items(): - if not isinstance(v, Tensor): - v = v.resize(size, *args, **kwargs) - bbox.add_field(k, v) - return bbox - - ratio_width, ratio_height = ratios - xmin, ymin, xmax, ymax = self._split_into_xyxy() - scaled_xmin = xmin * ratio_width - scaled_xmax = xmax * ratio_width - scaled_ymin = ymin * ratio_height - scaled_ymax = ymax * ratio_height - scaled_box = Tensor.cat( - *(scaled_xmin, scaled_ymin, scaled_xmax, scaled_ymax), dim=-1 - ) - bbox = BoxList(scaled_box, size, mode="xyxy") - for k, v in self.extra_fields.items(): - if not isinstance(v, Tensor): - v = v.resize(size, *args, **kwargs) - bbox.add_field(k, v) - - return bbox.convert(self.mode) - - def transpose(self, method): - image_width, image_height = self.size - xmin, ymin, xmax, ymax = self._split_into_xyxy() - if method == FLIP_LEFT_RIGHT: - TO_REMOVE = 1 - transposed_xmin = image_width - xmax - TO_REMOVE - transposed_xmax = image_width - xmin - TO_REMOVE - transposed_ymin = ymin - transposed_ymax = ymax - elif method == FLIP_TOP_BOTTOM: - transposed_xmin = xmin - transposed_xmax = xmax - transposed_ymin = image_height - ymax - transposed_ymax = image_height - ymin - - transposed_boxes = Tensor.cat( - *(transposed_xmin, transposed_ymin, transposed_xmax, transposed_ymax), dim=-1 - ) - bbox = BoxList(transposed_boxes, self.size, mode="xyxy") - for k, v in self.extra_fields.items(): - if not isinstance(v, Tensor): - v = v.transpose(method) - bbox.add_field(k, v) - return bbox.convert(self.mode) - - def clip_to_image(self, remove_empty=True): - TO_REMOVE = 1 - bb1 = self.bbox.clip(min_=0, max_=self.size[0] - TO_REMOVE)[:, 0] - bb2 = self.bbox.clip(min_=0, max_=self.size[1] - TO_REMOVE)[:, 1] - bb3 = self.bbox.clip(min_=0, max_=self.size[0] - TO_REMOVE)[:, 2] - bb4 = self.bbox.clip(min_=0, max_=self.size[1] - TO_REMOVE)[:, 3] - self.bbox = Tensor.stack(bb1, bb2, bb3, bb4, dim=1) - if remove_empty: - box = self.bbox - keep = (box[:, 3] > box[:, 1]) & (box[:, 2] > box[:, 0]) - return self[keep] - return self - - def __getitem__(self, item): - if isinstance(item, list): - if len(item) == 0: - return [] - if sum(item) == len(item) and isinstance(item[0], bool): - return self - bbox = BoxList(tensor_gather(self.bbox, item), self.size, self.mode) - for k, v in self.extra_fields.items(): - bbox.add_field(k, tensor_gather(v, item)) - return bbox - - def __len__(self): - return self.bbox.shape[0] - - -def cat_boxlist(bboxes): - size = bboxes[0].size - mode = bboxes[0].mode - fields = set(bboxes[0].fields()) - cat_box_list = [bbox.bbox for bbox in bboxes if bbox.bbox.shape[0] > 0] - - if len(cat_box_list) > 0: - cat_boxes = BoxList(Tensor.cat(*cat_box_list, dim=0), size, mode) - else: - cat_boxes = BoxList(bboxes[0].bbox, size, mode) - for field in fields: - cat_field_list = [bbox.get_field(field) for bbox in bboxes if bbox.get_field(field).shape[0] > 0] - - if len(cat_box_list) > 0: - data = Tensor.cat(*cat_field_list, dim=0) - else: - data = bboxes[0].get_field(field) - - cat_boxes.add_field(field, data) - - return cat_boxes - - -class FPN: - def __init__(self, in_channels_list, out_channels): - self.inner_blocks, self.layer_blocks = [], [] - for in_channels in in_channels_list: - self.inner_blocks.append(nn.Conv2d(in_channels, out_channels, kernel_size=1)) - self.layer_blocks.append(nn.Conv2d(out_channels, out_channels, kernel_size=3, padding=1)) - self.top_block = LastLevelMaxPool() - - def __call__(self, x: Tensor): - last_inner = self.inner_blocks[-1](x[-1]) - results = [] - results.append(self.layer_blocks[-1](last_inner)) - for feature, inner_block, layer_block in zip( - x[:-1][::-1], self.inner_blocks[:-1][::-1], self.layer_blocks[:-1][::-1] - ): - if not inner_block: - continue - inner_top_down = nearest_interpolate(last_inner, scale_factor=2) - inner_lateral = inner_block(feature) - last_inner = inner_lateral + inner_top_down - layer_result = layer_block(last_inner) - results.insert(0, layer_result) - last_results = self.top_block(results[-1]) - results.extend(last_results) - - return tuple(results) - - -class ResNetFPN: - def __init__(self, resnet, out_channels=256): - self.out_channels = out_channels - self.body = resnet - in_channels_stage2 = 256 - in_channels_list = [ - in_channels_stage2, - in_channels_stage2 * 2, - in_channels_stage2 * 4, - in_channels_stage2 * 8, - ] - self.fpn = FPN(in_channels_list, out_channels) - - def __call__(self, x): - x = self.body(x) - return self.fpn(x) - - -class AnchorGenerator: - def __init__( - self, - sizes=(32, 64, 128, 256, 512), - aspect_ratios=(0.5, 1.0, 2.0), - anchor_strides=(4, 8, 16, 32, 64), - straddle_thresh=0, - ): - if len(anchor_strides) == 1: - anchor_stride = anchor_strides[0] - cell_anchors = [ - generate_anchors(anchor_stride, sizes, aspect_ratios) - ] - else: - if len(anchor_strides) != len(sizes): - raise RuntimeError("FPN should have #anchor_strides == #sizes") - - cell_anchors = [ - generate_anchors( - anchor_stride, - size if isinstance(size, (tuple, list)) else (size,), - aspect_ratios - ) - for anchor_stride, size in zip(anchor_strides, sizes) - ] - self.strides = anchor_strides - self.cell_anchors = cell_anchors - self.straddle_thresh = straddle_thresh - - def num_anchors_per_location(self): - return [cell_anchors.shape[0] for cell_anchors in self.cell_anchors] - - def grid_anchors(self, grid_sizes): - anchors = [] - for size, stride, base_anchors in zip( - grid_sizes, self.strides, self.cell_anchors - ): - grid_height, grid_width = size - device = base_anchors.device - shifts_x = Tensor.arange( - start=0, stop=grid_width * stride, step=stride, dtype=dtypes.float32, device=device - ) - shifts_y = Tensor.arange( - start=0, stop=grid_height * stride, step=stride, dtype=dtypes.float32, device=device - ) - shift_y, shift_x = meshgrid(shifts_y, shifts_x) - shift_x = shift_x.reshape(-1) - shift_y = shift_y.reshape(-1) - shifts = Tensor.stack(shift_x, shift_y, shift_x, shift_y, dim=1) - - anchors.append( - (shifts.reshape(-1, 1, 4) + base_anchors.reshape(1, -1, 4)).reshape(-1, 4) - ) - - return anchors - - def add_visibility_to(self, boxlist): - image_width, image_height = boxlist.size - anchors = boxlist.bbox - if self.straddle_thresh >= 0: - inds_inside = ( - (anchors[:, 0] >= -self.straddle_thresh) - * (anchors[:, 1] >= -self.straddle_thresh) - * (anchors[:, 2] < image_width + self.straddle_thresh) - * (anchors[:, 3] < image_height + self.straddle_thresh) - ) - else: - device = anchors.device - inds_inside = Tensor.ones(anchors.shape[0], dtype=dtypes.uint8, device=device) - boxlist.add_field("visibility", inds_inside) - - def __call__(self, image_list, feature_maps): - grid_sizes = [feature_map.shape[-2:] for feature_map in feature_maps] - anchors_over_all_feature_maps = self.grid_anchors(grid_sizes) - anchors = [] - for (image_height, image_width) in image_list.image_sizes: - anchors_in_image = [] - for anchors_per_feature_map in anchors_over_all_feature_maps: - boxlist = BoxList( - anchors_per_feature_map, (image_width, image_height), mode="xyxy" - ) - self.add_visibility_to(boxlist) - anchors_in_image.append(boxlist) - anchors.append(anchors_in_image) - return anchors - - -def generate_anchors( - stride=16, sizes=(32, 64, 128, 256, 512), aspect_ratios=(0.5, 1, 2) -): - return _generate_anchors(stride, Tensor(list(sizes)) / stride, Tensor(list(aspect_ratios))) - - -def _generate_anchors(base_size, scales, aspect_ratios): - anchor = Tensor([1, 1, base_size, base_size]) - 1 - anchors = _ratio_enum(anchor, aspect_ratios) - anchors = Tensor.cat( - *[_scale_enum(anchors[i, :], scales).reshape(-1, 4) for i in range(anchors.shape[0])] - ) - return anchors - - -def _whctrs(anchor): - w = anchor[2] - anchor[0] + 1 - h = anchor[3] - anchor[1] + 1 - x_ctr = anchor[0] + 0.5 * (w - 1) - y_ctr = anchor[1] + 0.5 * (h - 1) - return w, h, x_ctr, y_ctr - - -def _mkanchors(ws, hs, x_ctr, y_ctr): - ws = ws[:, None] - hs = hs[:, None] - anchors = Tensor.cat(*( - x_ctr - 0.5 * (ws - 1), - y_ctr - 0.5 * (hs - 1), - x_ctr + 0.5 * (ws - 1), - y_ctr + 0.5 * (hs - 1), - ), dim=1) - return anchors - - -def _ratio_enum(anchor, ratios): - w, h, x_ctr, y_ctr = _whctrs(anchor) - size = w * h - size_ratios = size / ratios - ws = rint(Tensor.sqrt(size_ratios)) - hs = rint(ws * ratios) - anchors = _mkanchors(ws, hs, x_ctr, y_ctr) - return anchors - - -def _scale_enum(anchor, scales): - w, h, x_ctr, y_ctr = _whctrs(anchor) - ws = w * scales - hs = h * scales - anchors = _mkanchors(ws, hs, x_ctr, y_ctr) - return anchors - - -class RPNHead: - def __init__(self, in_channels, num_anchors): - self.conv = nn.Conv2d(in_channels, 256, kernel_size=3, padding=1) - self.cls_logits = nn.Conv2d(256, num_anchors, kernel_size=1) - self.bbox_pred = nn.Conv2d(256, num_anchors * 4, kernel_size=1) - - def __call__(self, x): - logits = [] - bbox_reg = [] - for feature in x: - t = Tensor.relu(self.conv(feature)) - logits.append(self.cls_logits(t)) - bbox_reg.append(self.bbox_pred(t)) - return logits, bbox_reg - - -def boxlist_nms(boxlist, nms_thresh, max_proposals=-1, score_field="scores"): - if nms_thresh <= 0: - return boxlist - mode = boxlist.mode - boxlist = boxlist.convert("xyxy") - boxes = boxlist.bbox - score = boxlist.get_field(score_field) - keep = _box_nms(boxes.numpy(), score.numpy(), nms_thresh) - if max_proposals > 0: - keep = keep[:max_proposals] - boxlist = boxlist[keep] - return boxlist.convert(mode) - - -def remove_small_boxes(boxlist, min_size): - xywh_boxes = boxlist.convert("xywh").bbox - _, _, ws, hs = xywh_boxes.chunk(4, dim=1) - keep = (( - (ws >= min_size) * (hs >= min_size) - ) > 0).reshape(-1) - if keep.sum().numpy() == len(boxlist): - return boxlist - else: - keep = keep.numpy().nonzero()[0] - return boxlist[keep] - - -class RPNPostProcessor: - # Not used in Loss calculation - def __init__( - self, - pre_nms_top_n, - post_nms_top_n, - nms_thresh, - min_size, - box_coder=None, - fpn_post_nms_top_n=None, - ): - self.pre_nms_top_n = pre_nms_top_n - self.post_nms_top_n = post_nms_top_n - self.nms_thresh = nms_thresh - self.min_size = min_size - - if box_coder is None: - box_coder = BoxCoder(weights=(1.0, 1.0, 1.0, 1.0)) - self.box_coder = box_coder - - if fpn_post_nms_top_n is None: - fpn_post_nms_top_n = post_nms_top_n - self.fpn_post_nms_top_n = fpn_post_nms_top_n - - def forward_for_single_feature_map(self, anchors, objectness, box_regression): - device = objectness.device - N, A, H, W = objectness.shape - objectness = permute_and_flatten(objectness, N, A, 1, H, W).reshape(N, -1) - objectness = objectness.sigmoid() - - box_regression = permute_and_flatten(box_regression, N, A, 4, H, W) - - num_anchors = A * H * W - - pre_nms_top_n = min(self.pre_nms_top_n, num_anchors) - objectness, topk_idx = topk(objectness, pre_nms_top_n, dim=1, sorted=False) - concat_anchors = Tensor.cat(*[a.bbox for a in anchors], dim=0).reshape(N, -1, 4) - image_shapes = [box.size for box in anchors] - - box_regression_list = [] - concat_anchors_list = [] - for batch_idx in range(N): - box_regression_list.append(tensor_gather(box_regression[batch_idx], topk_idx[batch_idx])) - concat_anchors_list.append(tensor_gather(concat_anchors[batch_idx], topk_idx[batch_idx])) - - box_regression = Tensor.stack(*box_regression_list) - concat_anchors = Tensor.stack(*concat_anchors_list) - - proposals = self.box_coder.decode( - box_regression.reshape(-1, 4), concat_anchors.reshape(-1, 4) - ) - - proposals = proposals.reshape(N, -1, 4) - - result = [] - for proposal, score, im_shape in zip(proposals, objectness, image_shapes): - boxlist = BoxList(proposal, im_shape, mode="xyxy") - boxlist.add_field("objectness", score) - boxlist = boxlist.clip_to_image(remove_empty=False) - boxlist = remove_small_boxes(boxlist, self.min_size) - boxlist = boxlist_nms( - boxlist, - self.nms_thresh, - max_proposals=self.post_nms_top_n, - score_field="objectness", - ) - result.append(boxlist) - return result - - def __call__(self, anchors, objectness, box_regression): - sampled_boxes = [] - num_levels = len(objectness) - anchors = list(zip(*anchors)) - for a, o, b in zip(anchors, objectness, box_regression): - sampled_boxes.append(self.forward_for_single_feature_map(a, o, b)) - - boxlists = list(zip(*sampled_boxes)) - boxlists = [cat_boxlist(boxlist) for boxlist in boxlists] - - if num_levels > 1: - boxlists = self.select_over_all_levels(boxlists) - - return boxlists - - def select_over_all_levels(self, boxlists): - num_images = len(boxlists) - for i in range(num_images): - objectness = boxlists[i].get_field("objectness") - post_nms_top_n = min(self.fpn_post_nms_top_n, objectness.shape[0]) - _, inds_sorted = topk(objectness, - post_nms_top_n, dim=0, sorted=False - ) - boxlists[i] = boxlists[i][inds_sorted] - return boxlists - - -class RPN: - def __init__(self, in_channels): - self.anchor_generator = AnchorGenerator() - - in_channels = 256 - head = RPNHead( - in_channels, self.anchor_generator.num_anchors_per_location()[0] - ) - rpn_box_coder = BoxCoder(weights=(1.0, 1.0, 1.0, 1.0)) - box_selector_test = RPNPostProcessor( - pre_nms_top_n=1000, - post_nms_top_n=1000, - nms_thresh=0.7, - min_size=0, - box_coder=rpn_box_coder, - fpn_post_nms_top_n=1000 - ) - self.head = head - self.box_selector_test = box_selector_test - - def __call__(self, images, features, targets=None): - objectness, rpn_box_regression = self.head(features) - anchors = self.anchor_generator(images, features) - boxes = self.box_selector_test(anchors, objectness, rpn_box_regression) - return boxes, {} - - -def make_conv3x3( - in_channels, - out_channels, - dilation=1, - stride=1, - use_gn=False, -): - conv = nn.Conv2d( - in_channels, - out_channels, - kernel_size=3, - stride=stride, - padding=dilation, - dilation=dilation, - bias=False if use_gn else True - ) - return conv - - -class MaskRCNNFPNFeatureExtractor: - def __init__(self): - resolution = 14 - scales = (0.25, 0.125, 0.0625, 0.03125) - sampling_ratio = 2 - pooler = Pooler( - output_size=(resolution, resolution), - scales=scales, - sampling_ratio=sampling_ratio, - ) - input_size = 256 - self.pooler = pooler - - use_gn = False - layers = (256, 256, 256, 256) - dilation = 1 - self.mask_fcn1 = make_conv3x3(input_size, layers[0], dilation=dilation, stride=1, use_gn=use_gn) - self.mask_fcn2 = make_conv3x3(layers[0], layers[1], dilation=dilation, stride=1, use_gn=use_gn) - self.mask_fcn3 = make_conv3x3(layers[1], layers[2], dilation=dilation, stride=1, use_gn=use_gn) - self.mask_fcn4 = make_conv3x3(layers[2], layers[3], dilation=dilation, stride=1, use_gn=use_gn) - self.blocks = [self.mask_fcn1, self.mask_fcn2, self.mask_fcn3, self.mask_fcn4] - - def __call__(self, x, proposals): - x = self.pooler(x, proposals) - for layer in self.blocks: - if x is not None: - x = Tensor.relu(layer(x)) - return x - - -class MaskRCNNC4Predictor: - def __init__(self): - num_classes = 81 - dim_reduced = 256 - num_inputs = dim_reduced - self.conv5_mask = nn.ConvTranspose2d(num_inputs, dim_reduced, 2, 2, 0) - self.mask_fcn_logits = nn.Conv2d(dim_reduced, num_classes, 1, 1, 0) - - def __call__(self, x): - x = Tensor.relu(self.conv5_mask(x)) - return self.mask_fcn_logits(x) - - -class FPN2MLPFeatureExtractor: - def __init__(self, cfg): - resolution = 7 - scales = (0.25, 0.125, 0.0625, 0.03125) - sampling_ratio = 2 - pooler = Pooler( - output_size=(resolution, resolution), - scales=scales, - sampling_ratio=sampling_ratio, - ) - input_size = 256 * resolution ** 2 - representation_size = 1024 - self.pooler = pooler - self.fc6 = nn.Linear(input_size, representation_size) - self.fc7 = nn.Linear(representation_size, representation_size) - - def __call__(self, x, proposals): - x = self.pooler(x, proposals) - x = x.reshape(x.shape[0], -1) - x = Tensor.relu(self.fc6(x)) - x = Tensor.relu(self.fc7(x)) - return x - - -def _bilinear_interpolate( - input, # [N, C, H, W] - roi_batch_ind, # [K] - y, # [K, PH, IY] - x, # [K, PW, IX] - ymask, # [K, IY] - xmask, # [K, IX] -): - _, channels, height, width = input.shape - y = y.clip(min_=0.0, max_=float(height-1)) - x = x.clip(min_=0.0, max_=float(width-1)) - - # Tensor.where doesnt work well with int32 data so cast to float32 - y_low = y.cast(dtypes.int32).contiguous().float().contiguous() - x_low = x.cast(dtypes.int32).contiguous().float().contiguous() - - y_high = Tensor.where(y_low >= height - 1, float(height - 1), y_low + 1) - y_low = Tensor.where(y_low >= height - 1, float(height - 1), y_low) - - x_high = Tensor.where(x_low >= width - 1, float(width - 1), x_low + 1) - x_low = Tensor.where(x_low >= width - 1, float(width - 1), x_low) - - ly = y - y_low - lx = x - x_low - hy = 1.0 - ly - hx = 1.0 - lx - - def masked_index( - y, # [K, PH, IY] - x, # [K, PW, IX] - ): - if ymask is not None: - assert xmask is not None - y = Tensor.where(ymask[:, None, :], y, 0) - x = Tensor.where(xmask[:, None, :], x, 0) - key1 = roi_batch_ind[:, None, None, None, None, None] - key2 = Tensor.arange(channels, device=input.device)[None, :, None, None, None, None] - key3 = y[:, None, :, None, :, None] - key4 = x[:, None, None, :, None, :] - return tensor_getitem(input,key1,key2,key3,key4) # [K, C, PH, PW, IY, IX] - - v1 = masked_index(y_low, x_low) - v2 = masked_index(y_low, x_high) - v3 = masked_index(y_high, x_low) - v4 = masked_index(y_high, x_high) - - # all ws preemptively [K, C, PH, PW, IY, IX] - def outer_prod(y, x): - return y[:, None, :, None, :, None] * x[:, None, None, :, None, :] - - w1 = outer_prod(hy, hx) - w2 = outer_prod(hy, lx) - w3 = outer_prod(ly, hx) - w4 = outer_prod(ly, lx) - - val = w1*v1 + w2*v2 + w3*v3 + w4*v4 - return val - -#https://pytorch.org/vision/main/_modules/torchvision/ops/roi_align.html#roi_align -def _roi_align(input, rois, spatial_scale, pooled_height, pooled_width, sampling_ratio, aligned): - orig_dtype = input.dtype - _, _, height, width = input.shape - ph = Tensor.arange(pooled_height, device=input.device) - pw = Tensor.arange(pooled_width, device=input.device) - - roi_batch_ind = rois[:, 0].cast(dtypes.int32).contiguous() - offset = 0.5 if aligned else 0.0 - roi_start_w = rois[:, 1] * spatial_scale - offset - roi_start_h = rois[:, 2] * spatial_scale - offset - roi_end_w = rois[:, 3] * spatial_scale - offset - roi_end_h = rois[:, 4] * spatial_scale - offset - - roi_width = roi_end_w - roi_start_w - roi_height = roi_end_h - roi_start_h - if not aligned: - roi_width = roi_width.maximum(1.0) - roi_height = roi_height.maximum(1.0) - - bin_size_h = roi_height / pooled_height - bin_size_w = roi_width / pooled_width - - exact_sampling = sampling_ratio > 0 - roi_bin_grid_h = sampling_ratio if exact_sampling else (roi_height / pooled_height).ceil() - roi_bin_grid_w = sampling_ratio if exact_sampling else (roi_width / pooled_width).ceil() - - if exact_sampling: - count = max(roi_bin_grid_h * roi_bin_grid_w, 1) - iy = Tensor.arange(roi_bin_grid_h, device=input.device) - ix = Tensor.arange(roi_bin_grid_w, device=input.device) - ymask = None - xmask = None - else: - count = (roi_bin_grid_h * roi_bin_grid_w).maximum(1) - iy = Tensor.arange(height, device=input.device) - ix = Tensor.arange(width, device=input.device) - ymask = iy[None, :] < roi_bin_grid_h[:, None] - xmask = ix[None, :] < roi_bin_grid_w[:, None] - - def from_K(t): - return t[:, None, None] - - y = ( - from_K(roi_start_h) - + ph[None, :, None] * from_K(bin_size_h) - + (iy[None, None, :] + 0.5) * from_K(bin_size_h / roi_bin_grid_h) - ) - x = ( - from_K(roi_start_w) - + pw[None, :, None] * from_K(bin_size_w) - + (ix[None, None, :] + 0.5) * from_K(bin_size_w / roi_bin_grid_w) - ) - - val = _bilinear_interpolate(input, roi_batch_ind, y, x, ymask, xmask) - if not exact_sampling: - val = ymask[:, None, None, None, :, None].where(val, 0) - val = xmask[:, None, None, None, None, :].where(val, 0) - - output = val.sum((-1, -2)) - if isinstance(count, Tensor): - output /= count[:, None, None, None] - else: - output /= count - - output = output.cast(orig_dtype) - return output - -class ROIAlign: - def __init__(self, output_size, spatial_scale, sampling_ratio): - self.output_size = output_size - self.spatial_scale = spatial_scale - self.sampling_ratio = sampling_ratio - - def __call__(self, input, rois): - output = _roi_align( - input, rois, self.spatial_scale, self.output_size[0], self.output_size[1], self.sampling_ratio, aligned=False - ) - return output - - -class LevelMapper: - def __init__(self, k_min, k_max, canonical_scale=224, canonical_level=4, eps=1e-6): - self.k_min = k_min - self.k_max = k_max - self.s0 = canonical_scale - self.lvl0 = canonical_level - self.eps = eps - - def __call__(self, boxlists): - s = Tensor.sqrt(Tensor.cat(*[boxlist.area() for boxlist in boxlists])) - target_lvls = (self.lvl0 + Tensor.log2(s / self.s0 + self.eps)).floor() - target_lvls = target_lvls.clip(min_=self.k_min, max_=self.k_max) - return target_lvls - self.k_min - - -class Pooler: - def __init__(self, output_size, scales, sampling_ratio): - self.output_size = output_size - self.scales = scales - self.sampling_ratio = sampling_ratio - poolers = [] - for scale in scales: - poolers.append( - ROIAlign( - output_size, spatial_scale=scale, sampling_ratio=sampling_ratio - ) - ) - self.poolers = poolers - self.output_size = output_size - lvl_min = -math.log2(scales[0]) - lvl_max = -math.log2(scales[-1]) - self.map_levels = LevelMapper(lvl_min, lvl_max) - - def convert_to_roi_format(self, boxes): - concat_boxes = Tensor.cat(*[b.bbox for b in boxes], dim=0) - device, dtype = concat_boxes.device, concat_boxes.dtype - ids = Tensor.cat( - *[ - Tensor.full((len(b), 1), i, dtype=dtype, device=device) - for i, b in enumerate(boxes) - ], - dim=0, - ) - if concat_boxes.shape[0] != 0: - rois = Tensor.cat(*[ids, concat_boxes], dim=1) - return rois - - def __call__(self, x, boxes): - num_levels = len(self.poolers) - rois = self.convert_to_roi_format(boxes) - if rois is not None: - if num_levels == 1: - return self.poolers[0](x[0], rois) - - levels = self.map_levels(boxes) - results = [] - all_idxs = [] - for level, (per_level_feature, pooler) in enumerate(zip(x, self.poolers)): - # this is fine because no grad will flow through index - idx_in_level = (levels.numpy() == level).nonzero()[0] - if len(idx_in_level) > 0: - rois_per_level = tensor_gather(rois, idx_in_level) - pooler_output = pooler(per_level_feature, rois_per_level) - all_idxs.extend(idx_in_level) - results.append(pooler_output) - - return tensor_gather(Tensor.cat(*results), [x[0] for x in sorted({i:idx for i, idx in enumerate(all_idxs)}.items(), key=lambda x: x[1])]) - - -class FPNPredictor: - def __init__(self): - num_classes = 81 - representation_size = 1024 - self.cls_score = nn.Linear(representation_size, num_classes) - num_bbox_reg_classes = num_classes - self.bbox_pred = nn.Linear(representation_size, num_bbox_reg_classes * 4) - - def __call__(self, x): - scores = self.cls_score(x) - bbox_deltas = self.bbox_pred(x) - return scores, bbox_deltas - - -class PostProcessor: - # Not used in training - def __init__( - self, - score_thresh=0.05, - nms=0.5, - detections_per_img=100, - box_coder=None, - cls_agnostic_bbox_reg=False - ): - self.score_thresh = score_thresh - self.nms = nms - self.detections_per_img = detections_per_img - if box_coder is None: - box_coder = BoxCoder(weights=(10., 10., 5., 5.)) - self.box_coder = box_coder - self.cls_agnostic_bbox_reg = cls_agnostic_bbox_reg - - def __call__(self, x, boxes): - class_logits, box_regression = x - class_prob = Tensor.softmax(class_logits, -1) - image_shapes = [box.size for box in boxes] - boxes_per_image = [len(box) for box in boxes] - concat_boxes = Tensor.cat(*[a.bbox for a in boxes], dim=0) - - if self.cls_agnostic_bbox_reg: - box_regression = box_regression[:, -4:] - proposals = self.box_coder.decode( - box_regression.reshape(sum(boxes_per_image), -1), concat_boxes - ) - if self.cls_agnostic_bbox_reg: - proposals = proposals.repeat([1, class_prob.shape[1]]) - num_classes = class_prob.shape[1] - proposals = proposals.unsqueeze(0) - class_prob = class_prob.unsqueeze(0) - results = [] - for prob, boxes_per_img, image_shape in zip( - class_prob, proposals, image_shapes - ): - boxlist = self.prepare_boxlist(boxes_per_img, prob, image_shape) - boxlist = boxlist.clip_to_image(remove_empty=False) - boxlist = self.filter_results(boxlist, num_classes) - results.append(boxlist) - return results - - def prepare_boxlist(self, boxes, scores, image_shape): - boxes = boxes.reshape(-1, 4) - scores = scores.reshape(-1) - boxlist = BoxList(boxes, image_shape, mode="xyxy") - boxlist.add_field("scores", scores) - return boxlist - - def filter_results(self, boxlist, num_classes): - boxes = boxlist.bbox.reshape(-1, num_classes * 4) - scores = boxlist.get_field("scores").reshape(-1, num_classes) - - device = scores.device - result = [] - scores = scores.numpy() - boxes = boxes.numpy() - inds_all = scores > self.score_thresh - for j in range(1, num_classes): - inds = inds_all[:, j].nonzero()[0] - # This needs to be done in numpy because it can create empty arrays - scores_j = scores[inds, j] - boxes_j = boxes[inds, j * 4: (j + 1) * 4] - boxes_j = Tensor(boxes_j) - scores_j = Tensor(scores_j) - boxlist_for_class = BoxList(boxes_j, boxlist.size, mode="xyxy") - boxlist_for_class.add_field("scores", scores_j) - if len(boxlist_for_class): - boxlist_for_class = boxlist_nms( - boxlist_for_class, self.nms - ) - num_labels = len(boxlist_for_class) - boxlist_for_class.add_field( - "labels", Tensor.full((num_labels,), j, device=device) - ) - result.append(boxlist_for_class) - - result = cat_boxlist(result) - number_of_detections = len(result) - - if number_of_detections > self.detections_per_img > 0: - cls_scores = result.get_field("scores") - image_thresh, _ = topk(cls_scores, k=self.detections_per_img) - image_thresh = image_thresh.numpy()[-1] - keep = (cls_scores.numpy() >= image_thresh).nonzero()[0] - result = result[keep] - return result - - -class RoIBoxHead: - def __init__(self, in_channels): - self.feature_extractor = FPN2MLPFeatureExtractor(in_channels) - self.predictor = FPNPredictor() - self.post_processor = PostProcessor( - score_thresh=0.05, - nms=0.5, - detections_per_img=100, - box_coder=BoxCoder(weights=(10., 10., 5., 5.)), - cls_agnostic_bbox_reg=False - ) - - def __call__(self, features, proposals, targets=None): - x = self.feature_extractor(features, proposals) - class_logits, box_regression = self.predictor(x) - if not Tensor.training: - result = self.post_processor((class_logits, box_regression), proposals) - return x, result, {} - - -class MaskPostProcessor: - # Not used in loss calculation - def __call__(self, x, boxes): - mask_prob = x.sigmoid().numpy() - num_masks = x.shape[0] - labels = [bbox.get_field("labels") for bbox in boxes] - labels = Tensor.cat(*labels).numpy().astype(np.int32) - index = np.arange(num_masks) - mask_prob = mask_prob[index, labels][:, None] - boxes_per_image, cumsum = [], 0 - for box in boxes: - cumsum += len(box) - boxes_per_image.append(cumsum) - # using numpy here as Tensor.chunk doesnt have custom chunk sizes - mask_prob = np.split(mask_prob, boxes_per_image, axis=0) - results = [] - for prob, box in zip(mask_prob, boxes): - bbox = BoxList(box.bbox, box.size, mode="xyxy") - for field in box.fields(): - bbox.add_field(field, box.get_field(field)) - prob = Tensor(prob) - bbox.add_field("mask", prob) - results.append(bbox) - - return results - - -class Mask: - def __init__(self): - self.feature_extractor = MaskRCNNFPNFeatureExtractor() - self.predictor = MaskRCNNC4Predictor() - self.post_processor = MaskPostProcessor() - - def __call__(self, features, proposals, targets=None): - x = self.feature_extractor(features, proposals) - if x is not None: - mask_logits = self.predictor(x) - if not Tensor.training: - result = self.post_processor(mask_logits, proposals) - return x, result, {} - return x, [], {} - - -class RoIHeads: - def __init__(self, in_channels): - self.box = RoIBoxHead(in_channels) - self.mask = Mask() - - def __call__(self, features, proposals, targets=None): - x, detections, _ = self.box(features, proposals, targets) - x, detections, _ = self.mask(features, detections, targets) - return x, detections, {} - - -class ImageList(object): - def __init__(self, tensors, image_sizes): - self.tensors = tensors - self.image_sizes = image_sizes - - def to(self, *args, **kwargs): - cast_tensor = self.tensors.to(*args, **kwargs) - return ImageList(cast_tensor, self.image_sizes) - - -def to_image_list(tensors, size_divisible=32): - # Preprocessing - if isinstance(tensors, Tensor) and size_divisible > 0: - tensors = [tensors] - - if isinstance(tensors, ImageList): - return tensors - elif isinstance(tensors, Tensor): - # single tensor shape can be inferred - assert tensors.ndim == 4 - image_sizes = [tensor.shape[-2:] for tensor in tensors] - return ImageList(tensors, image_sizes) - elif isinstance(tensors, (tuple, list)): - max_size = tuple(max(s) for s in zip(*[img.shape for img in tensors])) - if size_divisible > 0: - - stride = size_divisible - max_size = list(max_size) - max_size[1] = int(math.ceil(max_size[1] / stride) * stride) - max_size[2] = int(math.ceil(max_size[2] / stride) * stride) - max_size = tuple(max_size) - - batch_shape = (len(tensors),) + max_size - batched_imgs = np.zeros(batch_shape, dtype=_to_np_dtype(tensors[0].dtype)) - for img, pad_img in zip(tensors, batched_imgs): - pad_img[: img.shape[0], : img.shape[1], : img.shape[2]] += img.numpy() - - batched_imgs = Tensor(batched_imgs) - image_sizes = [im.shape[-2:] for im in tensors] - - return ImageList(batched_imgs, image_sizes) - else: - raise TypeError("Unsupported type for to_image_list: {}".format(type(tensors))) - - -class MaskRCNN: - def __init__(self, backbone: ResNet): - self.backbone = ResNetFPN(backbone, out_channels=256) - self.rpn = RPN(self.backbone.out_channels) - self.roi_heads = RoIHeads(self.backbone.out_channels) - - def load_from_pretrained(self): - fn = Path('./') / "weights/maskrcnn.pt" - fetch("https://download.pytorch.org/models/maskrcnn/e2e_mask_rcnn_R_50_FPN_1x.pth", fn) - - state_dict = torch_load(fn)['model'] - loaded_keys = [] - for k, v in state_dict.items(): - if "module." in k: - k = k.replace("module.", "") - if "stem." in k: - k = k.replace("stem.", "") - if "fpn_inner" in k: - block_index = int(re.search(r"fpn_inner(\d+)", k).group(1)) - k = re.sub(r"fpn_inner\d+", f"inner_blocks.{block_index - 1}", k) - if "fpn_layer" in k: - block_index = int(re.search(r"fpn_layer(\d+)", k).group(1)) - k = re.sub(r"fpn_layer\d+", f"layer_blocks.{block_index - 1}", k) - loaded_keys.append(k) - get_child(self, k).assign(v.numpy()).realize() - return loaded_keys - - def __call__(self, images): - images = to_image_list(images) - features = self.backbone(images.tensors) - proposals, _ = self.rpn(images, features) - x, result, _ = self.roi_heads(features, proposals) - return result - - -if __name__ == '__main__': - resnet = resnet = ResNet(50, num_classes=None, stride_in_1x1=True) - model = MaskRCNN(backbone=resnet) - model.load_from_pretrained() diff --git a/tinygrad/extra/models/resnet.py b/tinygrad/extra/models/resnet.py deleted file mode 100644 index 016f1d07..00000000 --- a/tinygrad/extra/models/resnet.py +++ /dev/null @@ -1,170 +0,0 @@ -import tinygrad.nn as nn -from tinygrad import Tensor, dtypes -from tinygrad.nn.state import torch_load -from tinygrad.helpers import fetch, get_child - -# allow monkeypatching in layer implementations -BatchNorm = nn.BatchNorm2d -Conv2d = nn.Conv2d -Linear = nn.Linear - - -class BasicBlock: - expansion = 1 - - def __init__(self, in_planes, planes, stride=1, groups=1, base_width=64): - assert groups == 1 and base_width == 64, "BasicBlock only supports groups=1 and base_width=64" - self.conv1 = Conv2d(in_planes, planes, kernel_size=3, stride=stride, padding=1, bias=False) - self.bn1 = BatchNorm(planes) - self.conv2 = Conv2d(planes, planes, kernel_size=3, padding=1, stride=1, bias=False) - self.bn2 = BatchNorm(planes) - self.downsample = [] - if stride != 1 or in_planes != self.expansion*planes: - self.downsample = [ - Conv2d(in_planes, self.expansion*planes, kernel_size=1, stride=stride, bias=False), - BatchNorm(self.expansion*planes) - ] - - def __call__(self, x): - out = self.bn1(self.conv1(x)).relu() - out = self.bn2(self.conv2(out)) - out = out + x.sequential(self.downsample) - out = out.relu() - return out - - -class Bottleneck: - # NOTE: stride_in_1x1=False, this is the v1.5 variant - expansion = 4 - - def __init__(self, in_planes, planes, stride=1, stride_in_1x1=False, groups=1, base_width=64): - width = int(planes * (base_width / 64.0)) * groups - # NOTE: the original implementation places stride at the first convolution (self.conv1), control with stride_in_1x1 - self.conv1 = Conv2d(in_planes, width, kernel_size=1, stride=stride if stride_in_1x1 else 1, bias=False) - self.bn1 = BatchNorm(width) - self.conv2 = Conv2d(width, width, kernel_size=3, padding=1, stride=1 if stride_in_1x1 else stride, groups=groups, bias=False) - self.bn2 = BatchNorm(width) - self.conv3 = Conv2d(width, self.expansion*planes, kernel_size=1, bias=False) - self.bn3 = BatchNorm(self.expansion*planes) - self.downsample = [] - if stride != 1 or in_planes != self.expansion*planes: - self.downsample = [ - Conv2d(in_planes, self.expansion*planes, kernel_size=1, stride=stride, bias=False), - BatchNorm(self.expansion*planes) - ] - - def __call__(self, x): - out = self.bn1(self.conv1(x)).relu() - out = self.bn2(self.conv2(out)).relu() - out = self.bn3(self.conv3(out)) - out = out + x.sequential(self.downsample) - out = out.relu() - return out - -class ResNet: - def __init__(self, num, num_classes=None, groups=1, width_per_group=64, stride_in_1x1=False): - self.num = num - self.block = { - 18: BasicBlock, - 34: BasicBlock, - 50: Bottleneck, - 101: Bottleneck, - 152: Bottleneck - }[num] - - self.num_blocks = { - 18: [2,2,2,2], - 34: [3,4,6,3], - 50: [3,4,6,3], - 101: [3,4,23,3], - 152: [3,8,36,3] - }[num] - - self.in_planes = 64 - - self.groups = groups - self.base_width = width_per_group - self.conv1 = Conv2d(3, 64, kernel_size=7, stride=2, bias=False, padding=3) - self.bn1 = BatchNorm(64) - self.layer1 = self._make_layer(self.block, 64, self.num_blocks[0], stride=1, stride_in_1x1=stride_in_1x1) - self.layer2 = self._make_layer(self.block, 128, self.num_blocks[1], stride=2, stride_in_1x1=stride_in_1x1) - self.layer3 = self._make_layer(self.block, 256, self.num_blocks[2], stride=2, stride_in_1x1=stride_in_1x1) - self.layer4 = self._make_layer(self.block, 512, self.num_blocks[3], stride=2, stride_in_1x1=stride_in_1x1) - self.fc = Linear(512 * self.block.expansion, num_classes) if num_classes is not None else None - - def _make_layer(self, block, planes, num_blocks, stride, stride_in_1x1): - strides = [stride] + [1] * (num_blocks-1) - layers = [] - for stride in strides: - if block == Bottleneck: - layers.append(block(self.in_planes, planes, stride, stride_in_1x1, self.groups, self.base_width)) - else: - layers.append(block(self.in_planes, planes, stride, self.groups, self.base_width)) - self.in_planes = planes * block.expansion - return layers - - def forward(self, x): - is_feature_only = self.fc is None - if is_feature_only: features = [] - out = self.bn1(self.conv1(x)).relu() - out = out.pad([1,1,1,1]).max_pool2d((3,3), 2) - out = out.sequential(self.layer1) - if is_feature_only: features.append(out) - out = out.sequential(self.layer2) - if is_feature_only: features.append(out) - out = out.sequential(self.layer3) - if is_feature_only: features.append(out) - out = out.sequential(self.layer4) - if is_feature_only: features.append(out) - if not is_feature_only: - out = out.mean([2,3]) - out = self.fc(out.cast(dtypes.float32)) - return out - return features - - def __call__(self, x:Tensor) -> Tensor: - return self.forward(x) - - def load_from_pretrained(self): - model_urls = { - (18, 1, 64): 'https://download.pytorch.org/models/resnet18-5c106cde.pth', - (34, 1, 64): 'https://download.pytorch.org/models/resnet34-333f7ec4.pth', - (50, 1, 64): 'https://download.pytorch.org/models/resnet50-19c8e357.pth', - (50, 32, 4): 'https://download.pytorch.org/models/resnext50_32x4d-7cdf4587.pth', - (101, 1, 64): 'https://download.pytorch.org/models/resnet101-5d3b4d8f.pth', - (152, 1, 64): 'https://download.pytorch.org/models/resnet152-b121ed2d.pth', - } - - self.url = model_urls[(self.num, self.groups, self.base_width)] - for k, dat in torch_load(fetch(self.url)).items(): - try: - obj: Tensor = get_child(self, k) - except AttributeError as e: - if 'fc.' in k and self.fc is None: - continue - - raise e - - if 'fc.' in k and obj.shape != dat.shape: - print("skipping fully connected layer") - continue # Skip FC if transfer learning - - if 'bn' not in k and 'downsample' not in k: assert obj.shape == dat.shape, (k, obj.shape, dat.shape) - obj.assign(dat.to(obj.device).reshape(obj.shape)) - -ResNet18 = lambda num_classes=1000: ResNet(18, num_classes=num_classes) -ResNet34 = lambda num_classes=1000: ResNet(34, num_classes=num_classes) -ResNet50 = lambda num_classes=1000: ResNet(50, num_classes=num_classes) -ResNet101 = lambda num_classes=1000: ResNet(101, num_classes=num_classes) -ResNet152 = lambda num_classes=1000: ResNet(152, num_classes=num_classes) -ResNeXt50_32X4D = lambda num_classes=1000: ResNet(50, num_classes=num_classes, groups=32, width_per_group=4) - -if __name__ == "__main__": - model = ResNet18() - model.load_from_pretrained() - from tinygrad import Context, GlobalCounters, TinyJit - jmodel = TinyJit(model) - jmodel(Tensor.rand(1, 3, 224, 224)).realize() - GlobalCounters.reset() - jmodel(Tensor.rand(1, 3, 224, 224)).realize() - for i in range(10): jmodel(Tensor.rand(1, 3, 224, 224)) diff --git a/tinygrad/extra/models/retinanet.py b/tinygrad/extra/models/retinanet.py deleted file mode 100644 index 37514266..00000000 --- a/tinygrad/extra/models/retinanet.py +++ /dev/null @@ -1,263 +0,0 @@ -import math -from tinygrad import Tensor, dtypes -from tinygrad.helpers import flatten, get_child -from examples.mlperf.helpers import generate_anchors, BoxCoder -from examples.mlperf.losses import sigmoid_focal_loss, l1_loss -from extra.models.resnet import ResNet -import tinygrad.nn as nn -import numpy as np - -ConvFPN = ConvHead = ConvClassificationHeadLogits = nn.Conv2d - -def nms(boxes, scores, thresh=0.5): - x1, y1, x2, y2 = np.rollaxis(boxes, 1) - areas = (x2 - x1 + 1) * (y2 - y1 + 1) - to_process, keep = scores.argsort()[::-1], [] - while to_process.size > 0: - cur, to_process = to_process[0], to_process[1:] - keep.append(cur) - inter_x1 = np.maximum(x1[cur], x1[to_process]) - inter_y1 = np.maximum(y1[cur], y1[to_process]) - inter_x2 = np.minimum(x2[cur], x2[to_process]) - inter_y2 = np.minimum(y2[cur], y2[to_process]) - inter_area = np.maximum(0, inter_x2 - inter_x1 + 1) * np.maximum(0, inter_y2 - inter_y1 + 1) - iou = inter_area / (areas[cur] + areas[to_process] - inter_area) - to_process = to_process[np.where(iou <= thresh)[0]] - return keep - -def decode_bbox(offsets, anchors): - dx, dy, dw, dh = np.rollaxis(offsets, 1) - widths, heights = anchors[:, 2] - anchors[:, 0], anchors[:, 3] - anchors[:, 1] - cx, cy = anchors[:, 0] + 0.5 * widths, anchors[:, 1] + 0.5 * heights - pred_cx, pred_cy = dx * widths + cx, dy * heights + cy - pred_w, pred_h = np.exp(dw) * widths, np.exp(dh) * heights - pred_x1, pred_y1 = pred_cx - 0.5 * pred_w, pred_cy - 0.5 * pred_h - pred_x2, pred_y2 = pred_cx + 0.5 * pred_w, pred_cy + 0.5 * pred_h - return np.stack([pred_x1, pred_y1, pred_x2, pred_y2], axis=1, dtype=np.float32) - -class RetinaNet: - def __init__(self, backbone:ResNet, num_classes:int=264, num_anchors:int=9, scales:list[int]|None=None, aspect_ratios:list[float]|None=None): - assert isinstance(backbone, ResNet) - scales = tuple((i, int(i*2**(1/3)), int(i*2**(2/3))) for i in 2**np.arange(5, 10)) if scales is None else scales - aspect_ratios = ((0.5, 1.0, 2.0),) * len(scales) if aspect_ratios is None else aspect_ratios - self.num_anchors, self.num_classes = num_anchors, num_classes - assert len(scales) == len(aspect_ratios) and all(self.num_anchors == len(s) * len(ar) for s, ar in zip(scales, aspect_ratios)) - - self.backbone = ResNetFPN(backbone) - self.head = RetinaHead(self.backbone.out_channels, num_anchors=num_anchors, num_classes=num_classes) - - def __call__(self, x:Tensor, **kwargs): - return self.forward(x, **kwargs) - - def forward(self, x:Tensor, **kwargs): - return self.head(self.backbone(x), **kwargs) - - def load_from_pretrained(self): - model_urls = { - (50, 1, 64): "https://download.pytorch.org/models/retinanet_resnet50_fpn_coco-eeacb38b.pth", - (50, 32, 4): "https://zenodo.org/record/6605272/files/retinanet_model_10.zip", - } - self.url = model_urls[(self.backbone.body.num, self.backbone.body.groups, self.backbone.body.base_width)] - from torch.hub import load_state_dict_from_url - state_dict = load_state_dict_from_url(self.url, progress=True, map_location='cpu') - state_dict = state_dict['model'] if 'model' in state_dict.keys() else state_dict - for k, v in state_dict.items(): - obj = get_child(self, k) - dat = v.detach().numpy() - assert obj.shape == dat.shape, (k, obj.shape, dat.shape) - obj.assign(dat) - - # predictions: (BS, (H1W1+...+HmWm)A, 4 + K) - def postprocess_detections(self, predictions, input_size=(800, 800), image_sizes=None, orig_image_sizes=None, score_thresh=0.05, topk_candidates=1000, nms_thresh=0.5): - anchors = generate_anchors(input_size) - grid_sizes = self.backbone.compute_grid_sizes(input_size) - split_idx = np.cumsum([int(self.num_anchors * sz[0] * sz[1]) for sz in grid_sizes[:-1]]) - detections = [] - for i, predictions_per_image in enumerate(predictions): - h, w = input_size if image_sizes is None else image_sizes[i] - - predictions_per_image = np.split(predictions_per_image, split_idx) - offsets_per_image = [br[:, :4] for br in predictions_per_image] - scores_per_image = [cl[:, 4:] for cl in predictions_per_image] - - image_boxes, image_scores, image_labels = [], [], [] - for offsets_per_level, scores_per_level, anchors_per_level in zip(offsets_per_image, scores_per_image, anchors): - # remove low scoring boxes - scores_per_level = scores_per_level.flatten() - keep_idxs = scores_per_level > score_thresh - scores_per_level = scores_per_level[keep_idxs] - - # keep topk - topk_idxs = np.where(keep_idxs)[0] - num_topk = min(len(topk_idxs), topk_candidates) - sort_idxs = scores_per_level.argsort()[-num_topk:][::-1] - topk_idxs, scores_per_level = topk_idxs[sort_idxs], scores_per_level[sort_idxs] - - # bbox coords from offsets - anchor_idxs = topk_idxs // self.num_classes - labels_per_level = topk_idxs % self.num_classes - boxes_per_level = decode_bbox(offsets_per_level[anchor_idxs], anchors_per_level[anchor_idxs]) - # clip to image size - clipped_x = boxes_per_level[:, 0::2].clip(0, w) - clipped_y = boxes_per_level[:, 1::2].clip(0, h) - boxes_per_level = np.stack([clipped_x, clipped_y], axis=2).reshape(-1, 4) - - image_boxes.append(boxes_per_level) - image_scores.append(scores_per_level) - image_labels.append(labels_per_level) - - image_boxes = np.concatenate(image_boxes) - image_scores = np.concatenate(image_scores) - image_labels = np.concatenate(image_labels) - - # nms for each class - keep_mask = np.zeros_like(image_scores, dtype=bool) - for class_id in np.unique(image_labels): - curr_indices = np.where(image_labels == class_id)[0] - curr_keep_indices = nms(image_boxes[curr_indices], image_scores[curr_indices], nms_thresh) - keep_mask[curr_indices[curr_keep_indices]] = True - keep = np.where(keep_mask)[0] - keep = keep[image_scores[keep].argsort()[::-1]] - - # resize bboxes back to original size - image_boxes = image_boxes[keep] - if orig_image_sizes is not None: - resized_x = image_boxes[:, 0::2] * orig_image_sizes[i][1] / w - resized_y = image_boxes[:, 1::2] * orig_image_sizes[i][0] / h - image_boxes = np.stack([resized_x, resized_y], axis=2).reshape(-1, 4) - # xywh format - image_boxes = np.concatenate([image_boxes[:, :2], image_boxes[:, 2:] - image_boxes[:, :2]], axis=1) - - detections.append({"boxes":image_boxes, "scores":image_scores[keep], "labels":image_labels[keep]}) - return detections - -class ClassificationHead: - def __init__(self, in_channels:int, num_anchors:int, num_classes:int): - self.num_classes = num_classes - self.conv = flatten([(ConvHead(in_channels, in_channels, kernel_size=3, padding=1), lambda x: x.relu()) for _ in range(4)]) - self.cls_logits = ConvClassificationHeadLogits(in_channels, num_anchors * num_classes, kernel_size=3, padding=1) - - def __call__(self, x:Tensor, labels:Tensor|None=None, matches:Tensor|None=None): - out = [self.cls_logits(feat.sequential(self.conv)).permute(0, 2, 3, 1).reshape(feat.shape[0], -1, self.num_classes) for feat in x] - out = out[0].cat(*out[1:], dim=1) - - if Tensor.training: - assert labels is not None and matches is not None, "labels and matches should be passed in when training" - return self._compute_loss(out.cast(dtypes.float32), labels, matches) - - return out.sigmoid() - - def _compute_loss(self, x:Tensor, labels:Tensor, matches:Tensor) -> Tensor: - labels = ((labels + 1) * (fg_idxs := matches >= 0) - 1).one_hot(num_classes=x.shape[-1]) - valid_idxs = (matches != -2).reshape(matches.shape[0], -1, 1) - loss = valid_idxs.where(sigmoid_focal_loss(x, labels), 0).sum((-1, -2)) - loss = (loss / fg_idxs.sum(-1)).sum() / matches.shape[0] - return loss - -class RegressionHead: - def __init__(self, in_channels:int, num_anchors:int, box_coder:BoxCoder|None=None): - self.conv = flatten([(ConvHead(in_channels, in_channels, kernel_size=3, padding=1), lambda x: x.relu()) for _ in range(4)]) - self.bbox_reg = ConvHead(in_channels, num_anchors * 4, kernel_size=3, padding=1) - - if box_coder is None: - box_coder = BoxCoder((1.0, 1.0, 1.0, 1.0)) - self.box_coder = box_coder - - def __call__(self, x:Tensor, bboxes:Tensor|None=None, matches:Tensor|None=None, anchors:Tensor|None=None): - out = [self.bbox_reg(feat.sequential(self.conv)).permute(0, 2, 3, 1).reshape(feat.shape[0], -1, 4) for feat in x] - out = out[0].cat(*out[1:], dim=1) - - if Tensor.training: - assert bboxes is not None and matches is not None and anchors is not None, "bboxes, matches, and anchors should be passed in when training" - return self._compute_loss(out, bboxes, matches, anchors) - - return out - - def _compute_loss(self, x:Tensor, bboxes:Tensor, matches:Tensor, anchors:Tensor) -> Tensor: - mask = (fg_idxs := matches >= 0).reshape(matches.shape[0], -1, 1) - x = x * mask - tgt = self.box_coder.encode(bboxes, anchors) * mask - loss = l1_loss(x, tgt).sum((-1, -2)) - loss = (loss / fg_idxs.sum(-1)).sum() / matches.shape[0] - return loss - -class RetinaHead: - def __init__(self, in_channels:int, num_anchors:int, num_classes:int): - self.classification_head = ClassificationHead(in_channels, num_anchors, num_classes) - self.regression_head = RegressionHead(in_channels, num_anchors) - - def __call__(self, x:Tensor, **kwargs) -> Tensor|dict[str, Tensor]: - if Tensor.training: - return { - "classification_loss": self.classification_head(x, labels=kwargs["labels"], matches=kwargs["matches"]), - "regression_loss": self.regression_head(x, bboxes=kwargs["bboxes"], matches=kwargs["matches"], anchors=kwargs["anchors"]) - } - - pred_bbox, pred_class = self.regression_head(x), self.classification_head(x) - out = pred_bbox.cat(pred_class, dim=-1) - return out - -class ResNetFPN: - def __init__(self, resnet:ResNet, out_channels:int=256, returned_layers:list[int]=[2, 3, 4]): - self.out_channels = out_channels - self.body = resnet - in_channels_list = [(self.body.in_planes // 8) * 2 ** (i - 1) for i in returned_layers] - self.fpn = FPN(in_channels_list, out_channels) - - # this is needed to decouple inference from postprocessing (anchors generation) - def compute_grid_sizes(self, input_size): - return np.ceil(np.array(input_size)[None, :] / 2 ** np.arange(3, 8)[:, None]) - - def __call__(self, x:Tensor): - out = self.body.bn1(self.body.conv1(x)).relu() - out = out.pad([1,1,1,1]).max_pool2d((3,3), 2) - out = out.sequential(self.body.layer1) - p3 = out.sequential(self.body.layer2) - p4 = p3.sequential(self.body.layer3) - p5 = p4.sequential(self.body.layer4) - return self.fpn([p3, p4, p5]) - -class ExtraFPNBlock: - def __init__(self, in_channels:int, out_channels:int): - self.p6 = ConvFPN(in_channels, out_channels, kernel_size=3, stride=2, padding=1) - self.p7 = ConvFPN(out_channels, out_channels, kernel_size=3, stride=2, padding=1) - self.use_P5 = in_channels == out_channels - - def __call__(self, p:Tensor, c:Tensor): - p5, c5 = p[-1], c[-1] - x = p5 if self.use_P5 else c5 - p6 = self.p6(x) - p7 = self.p7(p6.relu()) - p.extend([p6, p7]) - return p - -class FPN: - def __init__(self, in_channels_list:list[int], out_channels:int, extra_blocks:ExtraFPNBlock|None=None): - self.inner_blocks, self.layer_blocks = [], [] - for in_channels in in_channels_list: - self.inner_blocks.append(ConvFPN(in_channels, out_channels, kernel_size=1)) - self.layer_blocks.append(ConvFPN(out_channels, out_channels, kernel_size=3, padding=1)) - self.extra_blocks = ExtraFPNBlock(256, 256) if extra_blocks is None else extra_blocks - - def __call__(self, x:Tensor): - last_inner = self.inner_blocks[-1](x[-1]) - results = [self.layer_blocks[-1](last_inner)] - for idx in range(len(x) - 2, -1, -1): - inner_lateral = self.inner_blocks[idx](x[idx]) - - # upsample to inner_lateral's shape - (ih, iw), (oh, ow), prefix = last_inner.shape[-2:], inner_lateral.shape[-2:], last_inner.shape[:-2] - eh, ew = math.ceil(oh / ih), math.ceil(ow / iw) - inner_top_down = last_inner.reshape(*prefix, ih, 1, iw, 1).expand(*prefix, ih, eh, iw, ew).reshape(*prefix, ih*eh, iw*ew)[:, :, :oh, :ow] - - last_inner = inner_lateral + inner_top_down - results.insert(0, self.layer_blocks[idx](last_inner)) - if self.extra_blocks is not None: - results = self.extra_blocks(results, x) - return results - -if __name__ == "__main__": - from extra.models.resnet import ResNeXt50_32X4D - backbone = ResNeXt50_32X4D() - retina = RetinaNet(backbone) - retina.load_from_pretrained() diff --git a/tinygrad/extra/models/rnnt.py b/tinygrad/extra/models/rnnt.py deleted file mode 100644 index 8382aae6..00000000 --- a/tinygrad/extra/models/rnnt.py +++ /dev/null @@ -1,202 +0,0 @@ -from tinygrad.tensor import Tensor -from tinygrad.engine.jit import TinyJit -from tinygrad.nn import Linear, Embedding -from tinygrad.helpers import fetch -import numpy as np -from pathlib import Path - - -class RNNT: - def __init__(self, input_features=240, vocab_size=29, enc_hidden_size=1024, pred_hidden_size=320, joint_hidden_size=512, pre_enc_layers=2, post_enc_layers=3, pred_layers=2, stack_time_factor=2, dropout=0.32): - self.encoder = Encoder(input_features, enc_hidden_size, pre_enc_layers, post_enc_layers, stack_time_factor, dropout) - self.prediction = Prediction(vocab_size, pred_hidden_size, pred_layers, dropout) - self.joint = Joint(vocab_size, pred_hidden_size, enc_hidden_size, joint_hidden_size, dropout) - - @TinyJit - def __call__(self, x, y, hc=None): - f, _ = self.encoder(x, None) - g, _ = self.prediction(y, hc, Tensor.ones(1, requires_grad=False)) - out = self.joint(f, g) - return out.realize() - - def decode(self, x, x_lens): - logits, logit_lens = self.encoder(x, x_lens) - outputs = [] - for b in range(logits.shape[0]): - inseq = logits[b, :, :].unsqueeze(1) - logit_len = logit_lens[b] - seq = self._greedy_decode(inseq, int(np.ceil(logit_len.numpy()).item())) - outputs.append(seq) - return outputs - - def _greedy_decode(self, logits, logit_len): - hc = Tensor.zeros(self.prediction.rnn.layers, 2, self.prediction.hidden_size, requires_grad=False) - labels = [] - label = Tensor.zeros(1, 1, requires_grad=False) - mask = Tensor.zeros(1, requires_grad=False) - for time_idx in range(logit_len): - logit = logits[time_idx, :, :].unsqueeze(0) - not_blank = True - added = 0 - while not_blank and added < 30: - if len(labels) > 0: - mask = (mask + 1).clip(0, 1) - label = Tensor([[labels[-1] if labels[-1] <= 28 else labels[-1] - 1]], requires_grad=False) + 1 - 1 - jhc = self._pred_joint(Tensor(logit.numpy()), label, hc, mask) - k = jhc[0, 0, :29].argmax(axis=0).numpy() - not_blank = k != 28 - if not_blank: - labels.append(k) - hc = jhc[:, :, 29:] + 1 - 1 - added += 1 - return labels - - @TinyJit - def _pred_joint(self, logit, label, hc, mask): - g, hc = self.prediction(label, hc, mask) - j = self.joint(logit, g)[0] - j = j.pad(((0, 1), (0, 1), (0, 0))) - out = j.cat(hc, dim=2) - return out.realize() - - def load_from_pretrained(self): - fn = Path(__file__).parents[1] / "weights/rnnt.pt" - fetch("https://zenodo.org/record/3662521/files/DistributedDataParallel_1576581068.9962234-epoch-100.pt?download=1", fn) - - import torch - with open(fn, "rb") as f: - state_dict = torch.load(f, map_location="cpu")["state_dict"] - - # encoder - for i in range(2): - self.encoder.pre_rnn.cells[i].weights_ih.assign(state_dict[f"encoder.pre_rnn.lstm.weight_ih_l{i}"].numpy()) - self.encoder.pre_rnn.cells[i].weights_hh.assign(state_dict[f"encoder.pre_rnn.lstm.weight_hh_l{i}"].numpy()) - self.encoder.pre_rnn.cells[i].bias_ih.assign(state_dict[f"encoder.pre_rnn.lstm.bias_ih_l{i}"].numpy()) - self.encoder.pre_rnn.cells[i].bias_hh.assign(state_dict[f"encoder.pre_rnn.lstm.bias_hh_l{i}"].numpy()) - for i in range(3): - self.encoder.post_rnn.cells[i].weights_ih.assign(state_dict[f"encoder.post_rnn.lstm.weight_ih_l{i}"].numpy()) - self.encoder.post_rnn.cells[i].weights_hh.assign(state_dict[f"encoder.post_rnn.lstm.weight_hh_l{i}"].numpy()) - self.encoder.post_rnn.cells[i].bias_ih.assign(state_dict[f"encoder.post_rnn.lstm.bias_ih_l{i}"].numpy()) - self.encoder.post_rnn.cells[i].bias_hh.assign(state_dict[f"encoder.post_rnn.lstm.bias_hh_l{i}"].numpy()) - - # prediction - self.prediction.emb.weight.assign(state_dict["prediction.embed.weight"].numpy()) - for i in range(2): - self.prediction.rnn.cells[i].weights_ih.assign(state_dict[f"prediction.dec_rnn.lstm.weight_ih_l{i}"].numpy()) - self.prediction.rnn.cells[i].weights_hh.assign(state_dict[f"prediction.dec_rnn.lstm.weight_hh_l{i}"].numpy()) - self.prediction.rnn.cells[i].bias_ih.assign(state_dict[f"prediction.dec_rnn.lstm.bias_ih_l{i}"].numpy()) - self.prediction.rnn.cells[i].bias_hh.assign(state_dict[f"prediction.dec_rnn.lstm.bias_hh_l{i}"].numpy()) - - # joint - self.joint.l1.weight.assign(state_dict["joint_net.0.weight"].numpy()) - self.joint.l1.bias.assign(state_dict["joint_net.0.bias"].numpy()) - self.joint.l2.weight.assign(state_dict["joint_net.3.weight"].numpy()) - self.joint.l2.bias.assign(state_dict["joint_net.3.bias"].numpy()) - - -class LSTMCell: - def __init__(self, input_size, hidden_size, dropout): - self.dropout = dropout - - self.weights_ih = Tensor.uniform(hidden_size * 4, input_size) - self.bias_ih = Tensor.uniform(hidden_size * 4) - self.weights_hh = Tensor.uniform(hidden_size * 4, hidden_size) - self.bias_hh = Tensor.uniform(hidden_size * 4) - - def __call__(self, x, hc): - gates = x.linear(self.weights_ih.T, self.bias_ih) + hc[:x.shape[0]].linear(self.weights_hh.T, self.bias_hh) - - i, f, g, o = gates.chunk(4, 1) - i, f, g, o = i.sigmoid(), f.sigmoid(), g.tanh(), o.sigmoid() - - c = (f * hc[x.shape[0]:]) + (i * g) - h = (o * c.tanh()).dropout(self.dropout) - - return Tensor.cat(h, c).realize() - - -class LSTM: - def __init__(self, input_size, hidden_size, layers, dropout): - self.input_size = input_size - self.hidden_size = hidden_size - self.layers = layers - - self.cells = [LSTMCell(input_size, hidden_size, dropout) if i == 0 else LSTMCell(hidden_size, hidden_size, dropout if i != layers - 1 else 0) for i in range(layers)] - - def __call__(self, x, hc): - @TinyJit - def _do_step(x_, hc_): - return self.do_step(x_, hc_) - - if hc is None: - hc = Tensor.zeros(self.layers, 2 * x.shape[1], self.hidden_size, requires_grad=False) - - output = None - for t in range(x.shape[0]): - hc = _do_step(x[t] + 1 - 1, hc) # TODO: why do we need to do this? - if output is None: - output = hc[-1:, :x.shape[1]] - else: - output = output.cat(hc[-1:, :x.shape[1]], dim=0).realize() - - return output, hc - - def do_step(self, x, hc): - new_hc = [x] - for i, cell in enumerate(self.cells): - new_hc.append(cell(new_hc[i][:x.shape[0]], hc[i])) - return Tensor.stack(*new_hc[1:]).realize() - - -class StackTime: - def __init__(self, factor): - self.factor = factor - - def __call__(self, x, x_lens): - x = x.pad(((0, (-x.shape[0]) % self.factor), (0, 0), (0, 0))) - x = x.reshape(x.shape[0] // self.factor, x.shape[1], x.shape[2] * self.factor) - return x, x_lens / self.factor if x_lens is not None else None - - -class Encoder: - def __init__(self, input_size, hidden_size, pre_layers, post_layers, stack_time_factor, dropout): - self.pre_rnn = LSTM(input_size, hidden_size, pre_layers, dropout) - self.stack_time = StackTime(stack_time_factor) - self.post_rnn = LSTM(stack_time_factor * hidden_size, hidden_size, post_layers, dropout) - - def __call__(self, x, x_lens): - x, _ = self.pre_rnn(x, None) - x, x_lens = self.stack_time(x, x_lens) - x, _ = self.post_rnn(x, None) - return x.transpose(0, 1), x_lens - - -class Prediction: - def __init__(self, vocab_size, hidden_size, layers, dropout): - self.hidden_size = hidden_size - - self.emb = Embedding(vocab_size - 1, hidden_size) - self.rnn = LSTM(hidden_size, hidden_size, layers, dropout) - - def __call__(self, x, hc, m): - emb = self.emb(x) * m - x_, hc = self.rnn(emb.transpose(0, 1), hc) - return x_.transpose(0, 1), hc - - -class Joint: - def __init__(self, vocab_size, pred_hidden_size, enc_hidden_size, joint_hidden_size, dropout): - self.dropout = dropout - - self.l1 = Linear(pred_hidden_size + enc_hidden_size, joint_hidden_size) - self.l2 = Linear(joint_hidden_size, vocab_size) - - def __call__(self, f, g): - (_, T, H), (B, U, H2) = f.shape, g.shape - f = f.unsqueeze(2).expand(B, T, U, H) - g = g.unsqueeze(1).expand(B, T, U, H2) - - inp = f.cat(g, dim=3) - t = self.l1(inp).relu() - t = t.dropout(self.dropout) - return self.l2(t) diff --git a/tinygrad/extra/models/t5.py b/tinygrad/extra/models/t5.py deleted file mode 100644 index fd0ba34a..00000000 --- a/tinygrad/extra/models/t5.py +++ /dev/null @@ -1,288 +0,0 @@ -# pip3 install sentencepiece - -# adapted from https://github.com/huggingface/transformers/blob/main/src/transformers/models/t5/modeling_t5.py - -# coding=utf-8 -# Copyright 2018 Mesh TensorFlow authors, T5 Authors and HuggingFace Inc. team. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -"""Tinygrad T5 model.""" -from tinygrad import nn, Tensor, dtypes - -import math -from dataclasses import dataclass -from typing import List, Union, Optional, Tuple -from pathlib import Path -from sentencepiece import SentencePieceProcessor - -# default config is t5-xxl -@dataclass -class T5Config: - d_ff:int = 10240 - d_kv:int = 64 - d_model:int = 4096 - layer_norm_epsilon:float = 1e-6 - num_decoder_layers:int = 24 - num_heads:int = 64 - num_layers:int = 24 - relative_attention_num_buckets:int = 32 - relative_attention_max_distance:int = 128 - vocab_size:int = 32128 - -class T5Tokenizer: - def __init__(self, spiece_path): - self.spp = SentencePieceProcessor(str(spiece_path)) - - def encode(self, text:str, max_length:int) -> List[int]: - encoded = self.spp.Encode(text) - if len(encoded) > max_length - 1: encoded = encoded[:max_length - 1] - return encoded + [1] + [0]*(max_length - len(encoded) - 1) - -class T5LayerNorm: - def __init__(self, hidden_size:int, eps:float=1e-6): - """ - Construct a layernorm module in the T5 style. No bias and no subtraction of mean. - """ - self.weight = Tensor.ones(hidden_size) - self.variance_epsilon = eps - - def __call__(self, hidden_states:Tensor) -> Tensor: - # T5 uses a layer_norm which only scales and doesn't shift, which is also known as Root Mean - # Square Layer Normalization https://arxiv.org/abs/1910.07467 thus varience is calculated - # w/o mean and there is no bias. Additionally we want to make sure that the accumulation for - # half-precision inputs is done in fp32 - - variance = hidden_states.cast(dtypes.float32).pow(2).mean(-1, keepdim=True) - hidden_states = hidden_states * Tensor.rsqrt(variance + self.variance_epsilon) - - # convert into half-precision if necessary - if self.weight.dtype in [dtypes.float16, dtypes.bfloat16]: - hidden_states = hidden_states.cast(self.weight.dtype) - - return self.weight * hidden_states - - -class T5DenseGatedActDense: - def __init__(self, config:T5Config): - self.wi_0 = nn.Linear(config.d_model, config.d_ff, bias=False) - self.wi_1 = nn.Linear(config.d_model, config.d_ff, bias=False) - self.wo = nn.Linear(config.d_ff, config.d_model, bias=False) - - def __call__(self, hidden_states:Tensor) -> Tensor: - hidden_gelu = self.wi_0(hidden_states).gelu() - hidden_linear = self.wi_1(hidden_states) - hidden_states = hidden_gelu * hidden_linear - hidden_states = self.wo(hidden_states) - return hidden_states - - -class T5LayerFF: - def __init__(self, config:T5Config): - self.DenseReluDense = T5DenseGatedActDense(config) - self.layer_norm = T5LayerNorm(config.d_model, eps=config.layer_norm_epsilon) - - def __call__(self, hidden_states:Tensor) -> Tensor: - forwarded_states = self.layer_norm(hidden_states) - forwarded_states = self.DenseReluDense(forwarded_states) - hidden_states = hidden_states + forwarded_states - return hidden_states - - -class T5Attention: - def __init__(self, config:T5Config, has_relative_attention_bias:bool=False): - self.has_relative_attention_bias = has_relative_attention_bias - self.relative_attention_num_buckets = config.relative_attention_num_buckets - self.relative_attention_max_distance = config.relative_attention_max_distance - self.d_model = config.d_model - self.key_value_proj_dim = config.d_kv - self.n_heads = config.num_heads - self.inner_dim = self.n_heads * self.key_value_proj_dim - - # Mesh TensorFlow initialization to avoid scaling before softmax - self.q = nn.Linear(self.d_model, self.inner_dim, bias=False) - self.k = nn.Linear(self.d_model, self.inner_dim, bias=False) - self.v = nn.Linear(self.d_model, self.inner_dim, bias=False) - self.o = nn.Linear(self.inner_dim, self.d_model, bias=False) - - if self.has_relative_attention_bias: - self.relative_attention_bias = nn.Embedding(self.relative_attention_num_buckets, self.n_heads) - - @staticmethod - def _relative_position_bucket(relative_position:Tensor, num_buckets:int=32, max_distance:int=128) -> Tensor: - """ - Adapted from Mesh Tensorflow: - https://github.com/tensorflow/mesh/blob/0cb87fe07da627bf0b7e60475d59f95ed6b5be3d/mesh_tensorflow/transformer/transformer_layers.py#L593 - - Translate relative position to a bucket number for relative attention. The relative position is defined as - memory_position - query_position, i.e. the distance in tokens from the attending position to the attended-to - position. If bidirectional=False, then positive relative positions are invalid. We use smaller buckets for - small absolute relative_position and larger buckets for larger absolute relative_positions. All relative - positions >=max_distance map to the same bucket. All relative positions <=-max_distance map to the same bucket. - This should allow for more graceful generalization to longer sequences than the model has been trained on - - Args: - relative_position: an int32 Tensor - bidirectional: a boolean - whether the attention is bidirectional - num_buckets: an integer - max_distance: an integer - - Returns: - a Tensor with the same shape as relative_position, containing int32 values in the range [0, num_buckets) - """ - relative_buckets = Tensor.zeros_like(relative_position) - num_buckets //= 2 - relative_buckets += (relative_position > 0).cast(dtypes.long) * num_buckets - relative_position = Tensor.abs(relative_position) - - # half of the buckets are for exact increments in positions - max_exact = num_buckets // 2 - is_small = relative_position < max_exact - - # The other half of the buckets are for logarithmically bigger bins in positions up to max_distance - relative_position_if_large = max_exact + ( - Tensor.log(relative_position.float() / max_exact) - / math.log(max_distance / max_exact) - * (num_buckets - max_exact) - ).cast(dtypes.long) - - relative_position_if_large = Tensor.min( - Tensor.stack( - relative_position_if_large, Tensor.full_like(relative_position_if_large, num_buckets - 1) - ), - axis=0, - ) - relative_buckets += Tensor.where(is_small, relative_position, relative_position_if_large) - return relative_buckets - - def compute_bias(self, query_length, key_length, device=None) -> Tensor: - """Compute binned relative position bias""" - if device is None: - device = self.relative_attention_bias.weight.device - context_position = Tensor.arange(query_length, dtype=dtypes.long, device=device)[:, None] - memory_position = Tensor.arange(key_length, dtype=dtypes.long, device=device)[None, :] - relative_position = memory_position - context_position # shape (query_length, key_length) - relative_position_bucket = self._relative_position_bucket( - relative_position, # shape (query_length, key_length) - num_buckets=self.relative_attention_num_buckets, - max_distance=self.relative_attention_max_distance, - ) - values = self.relative_attention_bias(relative_position_bucket) # shape (query_length, key_length, num_heads) - values = values.permute([2, 0, 1]).unsqueeze(0) # shape (1, num_heads, query_length, key_length) - return values - - def __call__(self, hidden_states:Tensor, position_bias:Optional[Tensor]=None) -> Tuple[Tensor,Tensor]: - """ - Self-attention (if key_value_states is None) or attention over source sentence (provided by key_value_states). - """ - # Input is (batch_size, seq_length, dim) - batch_size, key_length = hidden_states.shape[:2] - - def shape(states): - """projection""" - return states.view(batch_size, -1, self.n_heads, self.key_value_proj_dim).transpose(1, 2) - - def unshape(states): - """reshape""" - return states.transpose(1, 2).contiguous().view(batch_size, -1, self.inner_dim) - - def project(hidden_states, proj_layer): - """projects hidden states correctly to key/query states""" - # self-attn - # (batch_size, n_heads, seq_length, dim_per_head) - return shape(proj_layer(hidden_states)) - - # get query states - query_states = shape(self.q(hidden_states)) # (batch_size, n_heads, seq_length, dim_per_head) - - # get key/value states - key_states = project(hidden_states, self.k) - value_states = project(hidden_states, self.v) - - # compute scores - scores = Tensor.matmul(query_states, key_states.transpose(3, 2)) - - if position_bias is None: - position_bias = self.compute_bias(key_length, key_length, device=scores.device) - - scores += position_bias - attn_weights = Tensor.softmax(scores.float(), axis=-1).cast(scores.dtype) # (batch_size, n_heads, seq_length, key_length) - - attn_output = unshape(Tensor.matmul(attn_weights, value_states)) # (batch_size, seq_length, dim) - attn_output = self.o(attn_output) - - return attn_output, position_bias - - -class T5LayerSelfAttention: - def __init__(self, config:T5Config, has_relative_attention_bias:bool=False): - self.SelfAttention = T5Attention(config, has_relative_attention_bias=has_relative_attention_bias) - self.layer_norm = T5LayerNorm(config.d_model, eps=config.layer_norm_epsilon) - - def __call__(self, hidden_states:Tensor, position_bias:Optional[Tensor]=None) -> Tuple[Tensor, Tensor]: - normed_hidden_states = self.layer_norm(hidden_states) - attention_output, position_bias = self.SelfAttention(normed_hidden_states, position_bias=position_bias) - return hidden_states + attention_output, position_bias - - -class T5Block: - def __init__(self, config:T5Config, has_relative_attention_bias:bool=False): - self.layer = (T5LayerSelfAttention(config, has_relative_attention_bias=has_relative_attention_bias), - T5LayerFF(config)) - - def __call__(self, hidden_states:Tensor, position_bias:Optional[Tensor]=None) -> Tuple[Tensor, Tensor]: - self_attention_outputs, position_bias = self.layer[0](hidden_states, position_bias=position_bias) - hidden_states = self_attention_outputs - - # Apply Feed Forward layer - hidden_states = self.layer[-1](hidden_states) - - return hidden_states, position_bias - - -class T5Stack: - def __init__(self, config:T5Config, embed_tokens:nn.Embedding): - self.config = config - self.embed_tokens = embed_tokens - self.block = [T5Block(config, has_relative_attention_bias=bool(i == 0)) for i in range(config.num_layers)] - self.final_layer_norm = T5LayerNorm(config.d_model, eps=config.layer_norm_epsilon) - - def __call__(self, input_ids:Tensor) -> Tensor: - input_ids = input_ids.view(-1, input_ids.shape[-1]) - - hidden_states, position_bias = self.embed_tokens(input_ids), None - - for layer_module in self.block: - hidden_states, position_bias = layer_module(hidden_states, position_bias=position_bias) - - return self.final_layer_norm(hidden_states) - - -class T5EncoderModel: - def __init__(self, config:T5Config): - self.shared = nn.Embedding(config.vocab_size, config.d_model) - self.encoder = T5Stack(config, self.shared) - - def __call__(self, input_ids:Tensor) -> Tensor: - return self.encoder(input_ids) - -class T5Embedder: - def __init__(self, max_length:int, spiece_path:Union[str, Path]): - self.tokenizer = T5Tokenizer(spiece_path) - self.max_length = max_length - config = T5Config() - self.encoder = T5EncoderModel(config) - - def __call__(self, texts:Union[str, List[str]]) -> Tensor: - if isinstance(texts, str): texts = [texts] - toks = Tensor.cat(*[Tensor(self.tokenizer.encode(text, self.max_length)) for text in texts], dim=0) - return self.encoder(toks) \ No newline at end of file diff --git a/tinygrad/extra/models/transformer.py b/tinygrad/extra/models/transformer.py deleted file mode 100644 index 4753e507..00000000 --- a/tinygrad/extra/models/transformer.py +++ /dev/null @@ -1,61 +0,0 @@ -from tinygrad import Tensor - -class TransformerBlock: - def __init__(self, embed_dim, num_heads, ff_dim, prenorm=False, act=lambda x: x.relu(), dropout=0.1): - assert embed_dim % num_heads == 0, "embed_dim must be divisible by num_heads" - - self.num_heads = num_heads - self.head_size = embed_dim // num_heads - self.prenorm, self.act = prenorm, act - self.dropout = dropout - - self.query = (Tensor.scaled_uniform(embed_dim, embed_dim), Tensor.zeros(embed_dim)) - self.key = (Tensor.scaled_uniform(embed_dim, embed_dim), Tensor.zeros(embed_dim)) - self.value = (Tensor.scaled_uniform(embed_dim, embed_dim), Tensor.zeros(embed_dim)) - - self.out = (Tensor.scaled_uniform(embed_dim, embed_dim), Tensor.zeros(embed_dim)) - - self.ff1 = (Tensor.scaled_uniform(embed_dim, ff_dim), Tensor.zeros(ff_dim)) - self.ff2 = (Tensor.scaled_uniform(ff_dim, embed_dim), Tensor.zeros(embed_dim)) - - self.ln1 = (Tensor.ones(embed_dim), Tensor.zeros(embed_dim)) - self.ln2 = (Tensor.ones(embed_dim), Tensor.zeros(embed_dim)) - - def attn(self, x): - # x: (bs, time, embed_dim) -> (bs, time, embed_dim) - query, key, value = [x.linear(*y).reshape(shape=(x.shape[0], -1, self.num_heads, self.head_size)).transpose(1,2) for y in [self.query, self.key, self.value]] - attention = Tensor.scaled_dot_product_attention(query, key, value).transpose(1,2) - return attention.reshape(shape=(x.shape[0], -1, self.num_heads * self.head_size)).linear(*self.out) - - def __call__(self, x): - if self.prenorm: - x = x + self.attn(x.layernorm().linear(*self.ln1)).dropout(self.dropout) - x = x + self.act(x.layernorm().linear(*self.ln2).linear(*self.ff1)).linear(*self.ff2).dropout(self.dropout) - else: - x = x + self.attn(x).dropout(self.dropout) - x = x.layernorm().linear(*self.ln1) - x = x + self.act(x.linear(*self.ff1)).linear(*self.ff2).dropout(self.dropout) - x = x.layernorm().linear(*self.ln2) - return x - -class Transformer: - def __init__(self, syms, maxlen, layers, embed_dim, num_heads, ff_dim): - self.maxlen, self.syms = maxlen, syms - self.embed = Tensor.scaled_uniform(maxlen+syms, embed_dim, requires_grad=False) - self.tbs = [TransformerBlock(embed_dim, num_heads, ff_dim) for _ in range(layers)] - self.final = Tensor.scaled_uniform(embed_dim, syms) - - def forward(self, x): - bs = x.shape[0] - - maxlen_eye = Tensor.eye(x.shape[1]) - maxlen_eye = maxlen_eye.unsqueeze(0).expand([bs, *maxlen_eye.shape]) - - onehot_feat = x.int().one_hot(self.syms) - - onehot = maxlen_eye.cat(onehot_feat, dim=2).flatten(end_dim=1) - - x = onehot.dot(self.embed).reshape((bs, x.shape[1], -1)) - x = x.sequential(self.tbs) - x = x.reshape((-1, x.shape[-1])).dot(self.final).log_softmax() - return x.reshape((bs, -1, x.shape[-1])) diff --git a/tinygrad/extra/models/unet.py b/tinygrad/extra/models/unet.py deleted file mode 100644 index 94d2e954..00000000 --- a/tinygrad/extra/models/unet.py +++ /dev/null @@ -1,255 +0,0 @@ -from tinygrad import Tensor, dtypes -from tinygrad.nn import Linear, Conv2d, GroupNorm, LayerNorm -from tinygrad.device import is_dtype_supported -from typing import Optional, Union, List, Any, Tuple -import math - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/util.py#L207 -def timestep_embedding(timesteps:Tensor, dim:int, max_period=10000): - half = dim // 2 - freqs = (-math.log(max_period) * Tensor.arange(half, device=timesteps.device) / half).exp() - args = timesteps.unsqueeze(1) * freqs.unsqueeze(0) - out = Tensor.cat(args.cos(), args.sin(), dim=-1) - return out.cast(dtypes.float16) if is_dtype_supported(dtypes.float16) else out - -class ResBlock: - def __init__(self, channels:int, emb_channels:int, out_channels:int): - self.in_layers = [ - GroupNorm(32, channels), - Tensor.silu, - Conv2d(channels, out_channels, 3, padding=1), - ] - self.emb_layers = [ - Tensor.silu, - Linear(emb_channels, out_channels), - ] - self.out_layers = [ - GroupNorm(32, out_channels), - Tensor.silu, - lambda x: x, # needed for weights loading code to work - Conv2d(out_channels, out_channels, 3, padding=1), - ] - self.skip_connection = Conv2d(channels, out_channels, 1) if channels != out_channels else (lambda x: x) - - def __call__(self, x:Tensor, emb:Tensor) -> Tensor: - h = x.sequential(self.in_layers) - emb_out = emb.sequential(self.emb_layers) - h = h + emb_out.reshape(*emb_out.shape, 1, 1) - h = h.sequential(self.out_layers) - return self.skip_connection(x) + h - -class CrossAttention: - def __init__(self, query_dim:int, ctx_dim:int, n_heads:int, d_head:int): - self.to_q = Linear(query_dim, n_heads*d_head, bias=False) - self.to_k = Linear(ctx_dim, n_heads*d_head, bias=False) - self.to_v = Linear(ctx_dim, n_heads*d_head, bias=False) - self.num_heads = n_heads - self.head_size = d_head - self.to_out = [Linear(n_heads*d_head, query_dim)] - - def __call__(self, x:Tensor, ctx:Optional[Tensor]=None) -> Tensor: - ctx = x if ctx is None else ctx - q,k,v = self.to_q(x), self.to_k(ctx), self.to_v(ctx) - q,k,v = [y.reshape(x.shape[0], -1, self.num_heads, self.head_size).transpose(1,2) for y in (q,k,v)] - attention = Tensor.scaled_dot_product_attention(q, k, v).transpose(1,2) - h_ = attention.reshape(x.shape[0], -1, self.num_heads * self.head_size) - return h_.sequential(self.to_out) - -class GEGLU: - def __init__(self, dim_in:int, dim_out:int): - self.proj = Linear(dim_in, dim_out * 2) - self.dim_out = dim_out - - def __call__(self, x:Tensor) -> Tensor: - x, gate = self.proj(x).chunk(2, dim=-1) - return x * gate.gelu() - -class FeedForward: - def __init__(self, dim:int, mult:int=4): - self.net = [ - GEGLU(dim, dim*mult), - lambda x: x, # needed for weights loading code to work - Linear(dim*mult, dim) - ] - - def __call__(self, x:Tensor) -> Tensor: - return x.sequential(self.net) - -class BasicTransformerBlock: - def __init__(self, dim:int, ctx_dim:int, n_heads:int, d_head:int): - self.attn1 = CrossAttention(dim, dim, n_heads, d_head) - self.ff = FeedForward(dim) - self.attn2 = CrossAttention(dim, ctx_dim, n_heads, d_head) - self.norm1 = LayerNorm(dim) - self.norm2 = LayerNorm(dim) - self.norm3 = LayerNorm(dim) - - def __call__(self, x:Tensor, ctx:Optional[Tensor]=None) -> Tensor: - x = x + self.attn1(self.norm1(x)) - x = x + self.attn2(self.norm2(x), ctx=ctx) - x = x + self.ff(self.norm3(x)) - return x - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/attention.py#L619 -class SpatialTransformer: - def __init__(self, channels:int, n_heads:int, d_head:int, ctx_dim:Union[int,List[int]], use_linear:bool, depth:int=1): - if isinstance(ctx_dim, int): - ctx_dim = [ctx_dim]*depth - else: - assert isinstance(ctx_dim, list) and depth == len(ctx_dim) - self.norm = GroupNorm(32, channels) - assert channels == n_heads * d_head - self.proj_in = Linear(channels, channels) if use_linear else Conv2d(channels, channels, 1) - self.transformer_blocks = [BasicTransformerBlock(channels, ctx_dim[d], n_heads, d_head) for d in range(depth)] - self.proj_out = Linear(channels, channels) if use_linear else Conv2d(channels, channels, 1) - self.use_linear = use_linear - - def __call__(self, x:Tensor, ctx:Optional[Tensor]=None) -> Tensor: - b, c, h, w = x.shape - x_in = x - x = self.norm(x) - ops = [ (lambda z: z.reshape(b, c, h*w).permute(0,2,1)), (lambda z: self.proj_in(z)) ] - x = x.sequential(ops if self.use_linear else ops[::-1]) - for block in self.transformer_blocks: - x = block(x, ctx=ctx) - ops = [ (lambda z: self.proj_out(z)), (lambda z: z.permute(0,2,1).reshape(b, c, h, w)) ] - x = x.sequential(ops if self.use_linear else ops[::-1]) - return x + x_in - -class Downsample: - def __init__(self, channels:int): - self.op = Conv2d(channels, channels, 3, stride=2, padding=1) - - def __call__(self, x:Tensor) -> Tensor: - return self.op(x) - -class Upsample: - def __init__(self, channels:int): - self.conv = Conv2d(channels, channels, 3, padding=1) - - def __call__(self, x:Tensor) -> Tensor: - bs,c,py,px = x.shape - z = x.reshape(bs, c, py, 1, px, 1).expand(bs, c, py, 2, px, 2).reshape(bs, c, py*2, px*2) - return self.conv(z) - -# https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/modules/diffusionmodules/openaimodel.py#L472 -class UNetModel: - def __init__(self, adm_in_ch:Optional[int], in_ch:int, out_ch:int, model_ch:int, attention_resolutions:List[int], num_res_blocks:int, channel_mult:List[int], transformer_depth:List[int], ctx_dim:Union[int,List[int]], use_linear:bool=False, d_head:Optional[int]=None, n_heads:Optional[int]=None): - self.model_ch = model_ch - self.num_res_blocks = [num_res_blocks] * len(channel_mult) - - self.attention_resolutions = attention_resolutions - self.d_head = d_head - self.n_heads = n_heads - def get_d_and_n_heads(dims:int) -> Tuple[int,int]: - if self.d_head is None: - assert self.n_heads is not None, f"d_head and n_heads cannot both be None" - return dims // self.n_heads, self.n_heads - else: - assert self.n_heads is None, f"d_head and n_heads cannot both be non-None" - return self.d_head, dims // self.d_head - - time_embed_dim = model_ch * 4 - self.time_embed = [ - Linear(model_ch, time_embed_dim), - Tensor.silu, - Linear(time_embed_dim, time_embed_dim), - ] - - if adm_in_ch is not None: - self.label_emb = [ - [ - Linear(adm_in_ch, time_embed_dim), - Tensor.silu, - Linear(time_embed_dim, time_embed_dim), - ] - ] - - self.input_blocks: List[Any] = [ - [Conv2d(in_ch, model_ch, 3, padding=1)] - ] - input_block_channels = [model_ch] - ch = model_ch - ds = 1 - for idx, mult in enumerate(channel_mult): - for _ in range(self.num_res_blocks[idx]): - layers: List[Any] = [ - ResBlock(ch, time_embed_dim, model_ch*mult), - ] - ch = mult * model_ch - if ds in attention_resolutions: - d_head, n_heads = get_d_and_n_heads(ch) - layers.append(SpatialTransformer(ch, n_heads, d_head, ctx_dim, use_linear, depth=transformer_depth[idx])) - - self.input_blocks.append(layers) - input_block_channels.append(ch) - - if idx != len(channel_mult) - 1: - self.input_blocks.append([ - Downsample(ch), - ]) - input_block_channels.append(ch) - ds *= 2 - - d_head, n_heads = get_d_and_n_heads(ch) - self.middle_block: List = [ - ResBlock(ch, time_embed_dim, ch), - SpatialTransformer(ch, n_heads, d_head, ctx_dim, use_linear, depth=transformer_depth[-1]), - ResBlock(ch, time_embed_dim, ch), - ] - - self.output_blocks = [] - for idx, mult in list(enumerate(channel_mult))[::-1]: - for i in range(self.num_res_blocks[idx] + 1): - ich = input_block_channels.pop() - layers = [ - ResBlock(ch + ich, time_embed_dim, model_ch*mult), - ] - ch = model_ch * mult - - if ds in attention_resolutions: - d_head, n_heads = get_d_and_n_heads(ch) - layers.append(SpatialTransformer(ch, n_heads, d_head, ctx_dim, use_linear, depth=transformer_depth[idx])) - - if idx > 0 and i == self.num_res_blocks[idx]: - layers.append(Upsample(ch)) - ds //= 2 - self.output_blocks.append(layers) - - self.out = [ - GroupNorm(32, ch), - Tensor.silu, - Conv2d(model_ch, out_ch, 3, padding=1), - ] - - def __call__(self, x:Tensor, tms:Tensor, ctx:Tensor, y:Optional[Tensor]=None) -> Tensor: - t_emb = timestep_embedding(tms, self.model_ch) - emb = t_emb.sequential(self.time_embed) - - if y is not None: - assert y.shape[0] == x.shape[0] - emb = emb + y.sequential(self.label_emb[0]) - - if is_dtype_supported(dtypes.float16): - emb = emb.cast(dtypes.float16) - ctx = ctx.cast(dtypes.float16) - x = x .cast(dtypes.float16) - - def run(x:Tensor, bb) -> Tensor: - if isinstance(bb, ResBlock): x = bb(x, emb) - elif isinstance(bb, SpatialTransformer): x = bb(x, ctx) - else: x = bb(x) - return x - - saved_inputs = [] - for b in self.input_blocks: - for bb in b: - x = run(x, bb) - saved_inputs.append(x) - for bb in self.middle_block: - x = run(x, bb) - for b in self.output_blocks: - x = x.cat(saved_inputs.pop(), dim=1) - for bb in b: - x = run(x, bb) - return x.sequential(self.out) diff --git a/tinygrad/extra/models/unet3d.py b/tinygrad/extra/models/unet3d.py deleted file mode 100644 index 1b2558c8..00000000 --- a/tinygrad/extra/models/unet3d.py +++ /dev/null @@ -1,59 +0,0 @@ -from pathlib import Path -import torch -from tinygrad import nn -from tinygrad.tensor import Tensor -from tinygrad.helpers import fetch, get_child - -class DownsampleBlock: - def __init__(self, c0, c1, stride=2): - self.conv1 = [nn.Conv2d(c0, c1, kernel_size=(3,3,3), stride=stride, padding=(1,1,1,1,1,1), bias=False), nn.InstanceNorm(c1), Tensor.relu] - self.conv2 = [nn.Conv2d(c1, c1, kernel_size=(3,3,3), padding=(1,1,1,1,1,1), bias=False), nn.InstanceNorm(c1), Tensor.relu] - - def __call__(self, x): - return x.sequential(self.conv1).sequential(self.conv2) - -class UpsampleBlock: - def __init__(self, c0, c1): - self.upsample_conv = [nn.ConvTranspose2d(c0, c1, kernel_size=(2,2,2), stride=2)] - self.conv1 = [nn.Conv2d(2 * c1, c1, kernel_size=(3,3,3), padding=(1,1,1,1,1,1), bias=False), nn.InstanceNorm(c1), Tensor.relu] - self.conv2 = [nn.Conv2d(c1, c1, kernel_size=(3,3,3), padding=(1,1,1,1,1,1), bias=False), nn.InstanceNorm(c1), Tensor.relu] - - def __call__(self, x, skip): - x = x.sequential(self.upsample_conv) - x = Tensor.cat(x, skip, dim=1) - return x.sequential(self.conv1).sequential(self.conv2) - -class UNet3D: - def __init__(self, in_channels=1, n_class=3): - filters = [32, 64, 128, 256, 320] - inp, out = filters[:-1], filters[1:] - self.input_block = DownsampleBlock(in_channels, filters[0], stride=1) - self.downsample = [DownsampleBlock(i, o) for i, o in zip(inp, out)] - self.bottleneck = DownsampleBlock(filters[-1], filters[-1]) - self.upsample = [UpsampleBlock(filters[-1], filters[-1])] + [UpsampleBlock(i, o) for i, o in zip(out[::-1], inp[::-1])] - self.output = {"conv": nn.Conv2d(filters[0], n_class, kernel_size=(1, 1, 1))} - - def __call__(self, x): - x = self.input_block(x) - outputs = [x] - for downsample in self.downsample: - x = downsample(x) - outputs.append(x) - x = self.bottleneck(x) - for upsample, skip in zip(self.upsample, outputs[::-1]): - x = upsample(x, skip) - x = self.output["conv"](x) - return x - - def load_from_pretrained(self): - fn = Path(__file__).parents[1] / "weights" / "unet-3d.ckpt" - fetch("https://zenodo.org/record/5597155/files/3dunet_kits19_pytorch.ptc?download=1", fn) - state_dict = torch.jit.load(fn, map_location=torch.device("cpu")).state_dict() - for k, v in state_dict.items(): - obj = get_child(self, k) - assert obj.shape == v.shape, (k, obj.shape, v.shape) - obj.assign(v.numpy()) - -if __name__ == "__main__": - mdl = UNet3D() - mdl.load_from_pretrained() diff --git a/tinygrad/extra/models/vit.py b/tinygrad/extra/models/vit.py deleted file mode 100644 index a4657084..00000000 --- a/tinygrad/extra/models/vit.py +++ /dev/null @@ -1,73 +0,0 @@ -import numpy as np -from tinygrad.tensor import Tensor -from tinygrad.helpers import fetch -from extra.models.transformer import TransformerBlock - -class ViT: - def __init__(self, layers=12, embed_dim=192, num_heads=3): - self.embedding = (Tensor.uniform(embed_dim, 3, 16, 16), Tensor.zeros(embed_dim)) - self.embed_dim = embed_dim - self.cls = Tensor.ones(1, 1, embed_dim) - self.pos_embedding = Tensor.ones(1, 197, embed_dim) - self.tbs = [ - TransformerBlock(embed_dim=embed_dim, num_heads=num_heads, ff_dim=embed_dim*4, - prenorm=True, act=lambda x: x.gelu()) - for i in range(layers)] - self.encoder_norm = (Tensor.uniform(embed_dim), Tensor.zeros(embed_dim)) - self.head = (Tensor.uniform(embed_dim, 1000), Tensor.zeros(1000)) - - def patch_embed(self, x): - x = x.conv2d(*self.embedding, stride=16) - x = x.reshape(shape=(x.shape[0], x.shape[1], -1)).permute(order=(0,2,1)) - return x - - def forward(self, x): - ce = self.cls.add(Tensor.zeros(x.shape[0],1,1)) - pe = self.patch_embed(x) - x = ce.cat(pe, dim=1) - x = x.add(self.pos_embedding).sequential(self.tbs) - x = x.layernorm().linear(*self.encoder_norm) - return x[:, 0].linear(*self.head) - - def load_from_pretrained(m): - # https://github.com/rwightman/pytorch-image-models/blob/master/timm/models/vision_transformer.py - if m.embed_dim == 192: - url = "https://storage.googleapis.com/vit_models/augreg/Ti_16-i21k-300ep-lr_0.001-aug_none-wd_0.03-do_0.0-sd_0.0--imagenet2012-steps_20k-lr_0.03-res_224.npz" - elif m.embed_dim == 768: - url = "https://storage.googleapis.com/vit_models/augreg/B_16-i21k-300ep-lr_0.001-aug_medium1-wd_0.1-do_0.0-sd_0.0--imagenet2012-steps_20k-lr_0.01-res_224.npz" - else: - raise Exception("no pretrained weights for configuration") - dat = np.load(fetch(url)) - - #for x in dat.keys(): - # print(x, dat[x].shape, dat[x].dtype) - - m.embedding[0].assign(np.transpose(dat['embedding/kernel'], (3,2,0,1))) - m.embedding[1].assign(dat['embedding/bias']) - - m.cls.assign(dat['cls']) - - m.head[0].assign(dat['head/kernel']) - m.head[1].assign(dat['head/bias']) - - m.pos_embedding.assign(dat['Transformer/posembed_input/pos_embedding']) - m.encoder_norm[0].assign(dat['Transformer/encoder_norm/scale']) - m.encoder_norm[1].assign(dat['Transformer/encoder_norm/bias']) - - for i in range(12): - m.tbs[i].query[0].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/query/kernel'].reshape(m.embed_dim, m.embed_dim)) - m.tbs[i].query[1].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/query/bias'].reshape(m.embed_dim)) - m.tbs[i].key[0].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/key/kernel'].reshape(m.embed_dim, m.embed_dim)) - m.tbs[i].key[1].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/key/bias'].reshape(m.embed_dim)) - m.tbs[i].value[0].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/value/kernel'].reshape(m.embed_dim, m.embed_dim)) - m.tbs[i].value[1].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/value/bias'].reshape(m.embed_dim)) - m.tbs[i].out[0].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/out/kernel'].reshape(m.embed_dim, m.embed_dim)) - m.tbs[i].out[1].assign(dat[f'Transformer/encoderblock_{i}/MultiHeadDotProductAttention_1/out/bias'].reshape(m.embed_dim)) - m.tbs[i].ff1[0].assign(dat[f'Transformer/encoderblock_{i}/MlpBlock_3/Dense_0/kernel']) - m.tbs[i].ff1[1].assign(dat[f'Transformer/encoderblock_{i}/MlpBlock_3/Dense_0/bias']) - m.tbs[i].ff2[0].assign(dat[f'Transformer/encoderblock_{i}/MlpBlock_3/Dense_1/kernel']) - m.tbs[i].ff2[1].assign(dat[f'Transformer/encoderblock_{i}/MlpBlock_3/Dense_1/bias']) - m.tbs[i].ln1[0].assign(dat[f'Transformer/encoderblock_{i}/LayerNorm_0/scale']) - m.tbs[i].ln1[1].assign(dat[f'Transformer/encoderblock_{i}/LayerNorm_0/bias']) - m.tbs[i].ln2[0].assign(dat[f'Transformer/encoderblock_{i}/LayerNorm_2/scale']) - m.tbs[i].ln2[1].assign(dat[f'Transformer/encoderblock_{i}/LayerNorm_2/bias']) diff --git a/tinygrad/extra/multitensor.py b/tinygrad/extra/multitensor.py deleted file mode 100644 index af7ddc30..00000000 --- a/tinygrad/extra/multitensor.py +++ /dev/null @@ -1,59 +0,0 @@ -import numpy as np -from tinygrad import Tensor, Device, GlobalCounters -from tinygrad.helpers import Timing - -d0, d1 = f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2" -N = 256 -FLOPS = N*N*N*2 - -# LazyBuffer should make three fields lists: self.st (all must have the same shape), self.realized, and self.device - -def explicit_shard_W_axis_1(X, W): - Xs = [X.to(d0), X.to(d1)] - Ws = [W[:, :N//2].to(d0), W[:, N//2:].to(d1)] # TODO: these shouldn't make copies on the original device - # pad them to form the correct size - Ws = [Ws[0].pad((None, (0,N//2))), Ws[1].pad((None, (N//2,0)))] - for x in Xs: assert x.shape == X.shape - for w in Ws: assert w.shape == W.shape - - # TODO: it shouldn't be faster with these realize - for x in Xs+Ws: x.realize() - def lm(x:Tensor, w:Tensor): - # these are movement ops on the local device - x = x.reshape(N, 1, N).expand(N, N, N) - w = w.T.reshape(1, N, N).expand(N, N, N) - m = x*w - assert m.uop.st.views[0].mask is not None - ret = m.sum(2) - return ret - #Os = [lm(Xs[0], Ws[0]), lm(Xs[1], Ws[1])] - Os = [Xs[0] @ Ws[0], Xs[1] @ Ws[1]] - for x in Os: x.realize() - return Os[0].to(Device.DEFAULT) + Os[1].to(Device.DEFAULT) - - #return Tensor.cat(*[x.to(Device.DEFAULT) for x in Os], dim=1) # TODO: someday we can remove this copy too - -def matmul(X, W): - return explicit_shard_W_axis_1(X, W) - #return X@W - -if __name__ == "__main__": - with Timing("init devices: "): - Device[d0], Device[d1] - - with Timing("create tensors: "): - X = Tensor.kaiming_uniform(N, N).realize() - W = Tensor.kaiming_uniform(N, N).realize() - - #with Timing("warmup: "): - # O = matmul(X, W).numpy() - - GlobalCounters.reset() - print("******** multiply start") - with Timing("******** multiply done: ", lambda x: f" {FLOPS/x:.2f} GFLOPS"): - O = matmul(X, W).realize() - Device[Device.DEFAULT].synchronize() - - with Timing("testing: "): - val = X.numpy() @ W.numpy() - np.testing.assert_allclose(val, O.numpy(), atol=1e-5) diff --git a/tinygrad/extra/nv_gpu_driver/clc6c0qmd.h b/tinygrad/extra/nv_gpu_driver/clc6c0qmd.h deleted file mode 100644 index e22f3fe6..00000000 --- a/tinygrad/extra/nv_gpu_driver/clc6c0qmd.h +++ /dev/null @@ -1,763 +0,0 @@ -/******************************************************************************* - Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -/* AUTO GENERATED FILE -- DO NOT EDIT */ - -#ifndef __CLC6C0QMD_H__ -#define __CLC6C0QMD_H__ - -/* -** Queue Meta Data, Version 02_03 - */ - -// The below C preprocessor definitions describe "multi-word" structures, where -// fields may have bit numbers beyond 32. For example, MW(127:96) means -// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" -// syntax is to distinguish from similar "X:Y" single-word definitions: the -// macros historically used for single-word definitions would fail with -// multi-word definitions. -// -// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel -// interface layer of nvidia.ko for an example of how to manipulate -// these MW(X:Y) definitions. - -#define NVC6C0_QMDV02_03_OUTER_PUT MW(30:0) -#define NVC6C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) -#define NVC6C0_QMDV02_03_OUTER_GET MW(62:32) -#define NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC6C0_QMDV02_03_INNER_GET MW(94:64) -#define NVC6C0_QMDV02_03_INNER_OVERFLOW MW(95:95) -#define NVC6C0_QMDV02_03_INNER_PUT MW(126:96) -#define NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC6C0_QMDV02_03_QMD_GROUP_ID MW(133:128) -#define NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_IS_QUEUE MW(136:136) -#define NVC6C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_QMD_RESERVED_B MW(159:144) -#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC6C0_QMDV02_03_QMD_RESERVED_C MW(185:185) -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) -#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC6C0_QMDV02_03_QMD_RESERVED_D MW(335:328) -#define NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) -#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC6C0_QMDV02_03_SAMPLER_INDEX MW(382:382) -#define NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC6C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) -#define NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) -#define NVC6C0_QMDV02_03_QMD_RESERVED13A MW(447:432) -#define NVC6C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) -#define NVC6C0_QMDV02_03_QMD_RESERVED14A MW(479:464) -#define NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) -#define NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) -#define NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) -#define NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) -#define NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) -#define NVC6C0_QMDV02_03_QMD_VERSION MW(579:576) -#define NVC6C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) -#define NVC6C0_QMDV02_03_QMD_RESERVED_H MW(591:584) -#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) -#define NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) -#define NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) -#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC6C0_QMDV02_03_QMD_RESERVED_J MW(783:776) -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV02_03_QMD_RESERVED_K MW(791:791) -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) -#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC6C0_QMDV02_03_QMD_RESERVED_L MW(879:872) -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV02_03_QMD_RESERVED_M MW(887:887) -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) -#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC6C0_QMDV02_03_QMD_RESERVED_N MW(954:952) -#define NVC6C0_QMDV02_03_BARRIER_COUNT MW(959:955) -#define NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC6C0_QMDV02_03_REGISTER_COUNT MW(991:984) -#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) -#define NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) -#define NVC6C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) -#define NVC6C0_QMDV02_03_SASS_VERSION MW(1023:1016) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) -#define NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) -#define NVC6C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) -#define NVC6C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC6C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) -#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC6C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) -#define NVC6C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) -#define NVC6C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) -#define NVC6C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) -#define NVC6C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) -#define NVC6C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) -#define NVC6C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) -#define NVC6C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) -#define NVC6C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) -#define NVC6C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 02_04 - */ - -#define NVC6C0_QMDV02_04_OUTER_PUT MW(30:0) -#define NVC6C0_QMDV02_04_OUTER_OVERFLOW MW(31:31) -#define NVC6C0_QMDV02_04_OUTER_GET MW(62:32) -#define NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC6C0_QMDV02_04_INNER_GET MW(94:64) -#define NVC6C0_QMDV02_04_INNER_OVERFLOW MW(95:95) -#define NVC6C0_QMDV02_04_INNER_PUT MW(126:96) -#define NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC6C0_QMDV02_04_QMD_GROUP_ID MW(133:128) -#define NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_IS_QUEUE MW(136:136) -#define NVC6C0_QMDV02_04_IS_QUEUE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_IS_QUEUE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE MW(141:141) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION MW(144:142) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH MW(145:145) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE MW(146:146) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION MW(149:147) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH MW(150:150) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_DEPENDENCE_COUNTER MW(157:151) -#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION MW(158:158) -#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_QMD_RESERVED_B MW(159:159) -#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST MW(185:185) -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) -#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC6C0_QMDV02_04_QMD_RESERVED_D MW(335:328) -#define NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE MW(366:366) -#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE MW(369:368) -#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC6C0_QMDV02_04_SAMPLER_INDEX MW(382:382) -#define NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE MW(383:383) -#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CTA_RASTER_WIDTH MW(415:384) -#define NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT MW(431:416) -#define NVC6C0_QMDV02_04_QMD_RESERVED13A MW(447:432) -#define NVC6C0_QMDV02_04_CTA_RASTER_DEPTH MW(463:448) -#define NVC6C0_QMDV02_04_QMD_RESERVED14A MW(479:464) -#define NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER MW(511:480) -#define NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) -#define NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE MW(561:544) -#define NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) -#define NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) -#define NVC6C0_QMDV02_04_QMD_VERSION MW(579:576) -#define NVC6C0_QMDV02_04_QMD_MAJOR_VERSION MW(583:580) -#define NVC6C0_QMDV02_04_QMD_RESERVED_H MW(591:584) -#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_REGISTER_COUNT_V MW(656:648) -#define NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) -#define NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) -#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER MW(767:736) -#define NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER MW(775:768) -#define NVC6C0_QMDV02_04_QMD_RESERVED_J MW(783:776) -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP MW(790:788) -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV02_04_QMD_RESERVED_K MW(791:791) -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT MW(793:792) -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE MW(794:794) -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE MW(799:799) -#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE0_PAYLOAD MW(831:800) -#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER MW(863:832) -#define NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER MW(871:864) -#define NVC6C0_QMDV02_04_QMD_RESERVED_L MW(879:872) -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP MW(886:884) -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV02_04_QMD_RESERVED_M MW(887:887) -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT MW(889:888) -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE MW(890:890) -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE MW(895:895) -#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV02_04_RELEASE1_PAYLOAD MW(927:896) -#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) -#define NVC6C0_QMDV02_04_QMD_RESERVED_N MW(954:952) -#define NVC6C0_QMDV02_04_BARRIER_COUNT MW(959:955) -#define NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) -#define NVC6C0_QMDV02_04_QMD_RESERVED_G MW(991:984) -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE MW(1009:1001) -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE MW(1011:1010) -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 -#define NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 -#define NVC6C0_QMDV02_04_QMD_RESERVED_A MW(1015:1012) -#define NVC6C0_QMDV02_04_SASS_VERSION MW(1023:1016) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER MW(1567:1536) -#define NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER MW(1584:1568) -#define NVC6C0_QMDV02_04_QMD_RESERVED_S MW(1599:1585) -#define NVC6C0_QMDV02_04_HW_ONLY_INNER_GET MW(1630:1600) -#define NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) -#define NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT MW(1662:1632) -#define NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE MW(1663:1663) -#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) -#define NVC6C0_QMDV02_04_QMD_RESERVED_Q MW(1694:1694) -#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) -#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) -#define NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER MW(1734:1728) -#define NVC6C0_QMDV02_04_QMD_RESERVED_I MW(1759:1735) -#define NVC6C0_QMDV02_04_QMD_SPARE_H MW(1791:1760) -#define NVC6C0_QMDV02_04_QMD_SPARE_I MW(1823:1792) -#define NVC6C0_QMDV02_04_QMD_SPARE_J MW(1855:1824) -#define NVC6C0_QMDV02_04_QMD_SPARE_K MW(1887:1856) -#define NVC6C0_QMDV02_04_QMD_SPARE_L MW(1919:1888) -#define NVC6C0_QMDV02_04_QMD_SPARE_M MW(1951:1920) -#define NVC6C0_QMDV02_04_QMD_SPARE_N MW(1983:1952) -#define NVC6C0_QMDV02_04_DEBUG_ID_UPPER MW(2015:1984) -#define NVC6C0_QMDV02_04_DEBUG_ID_LOWER MW(2047:2016) - - -/* -** Queue Meta Data, Version 03_00 - */ - -#define NVC6C0_QMDV03_00_OUTER_PUT MW(30:0) -#define NVC6C0_QMDV03_00_OUTER_OVERFLOW MW(31:31) -#define NVC6C0_QMDV03_00_OUTER_GET MW(62:32) -#define NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63) -#define NVC6C0_QMDV03_00_INNER_GET MW(94:64) -#define NVC6C0_QMDV03_00_INNER_OVERFLOW MW(95:95) -#define NVC6C0_QMDV03_00_INNER_PUT MW(126:96) -#define NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127) -#define NVC6C0_QMDV03_00_QMD_GROUP_ID MW(133:128) -#define NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134) -#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) -#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_IS_QUEUE MW(136:136) -#define NVC6C0_QMDV03_00_IS_QUEUE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_IS_QUEUE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) -#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_QMD_RESERVED04A MW(139:138) -#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140) -#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_QMD_RESERVED04B MW(141:141) -#define NVC6C0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142) -#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158) -#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_QMD_RESERVED04C MW(159:159) -#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185) -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189) -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190) -#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192) -#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224) -#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240) -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) -#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) -#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) -#define NVC6C0_QMDV03_00_QMD_RESERVED_D MW(335:328) -#define NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352) -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) -#define NVC6C0_QMDV03_00_QMD_RESERVED11A MW(366:366) -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368) -#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370) -#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_QMD_RESERVED11B MW(377:372) -#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378) -#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVC6C0_QMDV03_00_QMD_RESERVED11C MW(381:379) -#define NVC6C0_QMDV03_00_SAMPLER_INDEX MW(382:382) -#define NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383) -#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384) -#define NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416) -#define NVC6C0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521) -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522) -#define NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) -#define NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544) -#define NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562) -#define NVC6C0_QMDV03_00_QMD_RESERVED17A MW(568:568) -#define NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569) -#define NVC6C0_QMDV03_00_QMD_RESERVED17B MW(575:575) -#define NVC6C0_QMDV03_00_QMD_VERSION MW(579:576) -#define NVC6C0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580) -#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592) -#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608) -#define NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_REGISTER_COUNT_V MW(656:648) -#define NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657) -#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663) -#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) -#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672) -#define NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704) -#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736) -#define NVC6C0_QMDV03_00_BARRIER_COUNT MW(767:763) -#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768) -#define NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800) -#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A MW(818:808) -#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819) -#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820) -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV03_00_RELEASE0_ENABLE MW(823:823) -#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824) -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826) -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE MW(828:827) -#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829) -#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830) -#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832) -#define NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864) -#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896) -#define NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928) -#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A MW(946:936) -#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947) -#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948) -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV03_00_RELEASE1_ENABLE MW(951:951) -#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952) -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954) -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE MW(956:955) -#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957) -#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958) -#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960) -#define NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) -#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536) -#define NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568) -#define NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600) -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632) -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641) -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650) -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 -#define NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 -#define NVC6C0_QMDV03_00_SASS_VERSION MW(1663:1656) -#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664) -#define NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696) -#define NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A MW(1714:1704) -#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715) -#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716) -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007 -#define NVC6C0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719) -#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720) -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722) -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE MW(1724:1723) -#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725) -#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726) -#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728) -#define NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760) -#define NVC6C0_QMDV03_00_QMD_SPARE_I MW(1823:1792) -#define NVC6C0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824) -#define NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855) -#define NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856) -#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888) -#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919) -#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920) -#define NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1958:1952) -#define NVC6C0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984) -#define NVC6C0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016) - - - -#endif // #ifndef __CLC6C0QMD_H__ diff --git a/tinygrad/extra/nv_gpu_driver/clcec0qmd.h b/tinygrad/extra/nv_gpu_driver/clcec0qmd.h deleted file mode 100644 index 4ee8a129..00000000 --- a/tinygrad/extra/nv_gpu_driver/clcec0qmd.h +++ /dev/null @@ -1,863 +0,0 @@ -/******************************************************************************* - Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. - -*******************************************************************************/ - -#ifndef __CLCEC0QMD_H__ -#define __CLCEC0QMD_H__ - -/* -** Queue Meta Data, Version 05_00 - */ - -#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(29:0) -#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(30:30) -#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(31:31) -#define NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(63:32) -#define NVCEC0_QMDV05_00_INNER_GET MW(94:64) -#define NVCEC0_QMDV05_00_INNER_OVERFLOW MW(95:95) -#define NVCEC0_QMDV05_00_INNER_PUT MW(126:96) -#define NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW MW(127:127) -#define NVCEC0_QMDV05_00_DEPENDENCE_COUNTER MW(143:128) -#define NVCEC0_QMDV05_00_QMD_GROUP_ID MW(149:144) -#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(150:150) -#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_QMD_TYPE MW(153:151) -#define NVCEC0_QMDV05_00_QMD_TYPE_QUEUE 0x00000000 -#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL 0x00000001 -#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA 0x00000002 -#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA 0x00000003 -#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA 0x00000004 -#define NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005 -#define NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK MW(157:154) -#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS MW(158:158) -#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID MW(159:159) -#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER MW(207:192) -#define NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID MW(210:208) -#define NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK MW(218:211) -#define NVCEC0_QMDV05_00_GRID_WIDTH_RESUME MW(255:224) -#define NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME MW(271:256) -#define NVCEC0_QMDV05_00_GRID_DEPTH_RESUME MW(287:272) -#define NVCEC0_QMDV05_00_RELEASE_ENABLE(i) MW((288+(i)*16):(288+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE(i) MW((290+(i)*16):(289+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE(i) MW((291+(i)*16):(291+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE(i) MW((292+(i)*16):(292+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP(i) MW((295+(i)*16):(293+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX 0x00000002 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC 0x00000003 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC 0x00000004 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND 0x00000005 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR 0x00000006 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR 0x00000007 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT(i) MW((297+(i)*16):(296+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE(i) MW((299+(i)*16):(298+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 -#define NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 -#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B(i) MW((300+(i)*16):(300+(i)*16)) -#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO(i) MW((303+(i)*16):(301+(i)*16)) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE MW(336:336) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION MW(339:337) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH MW(340:340) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION MW(341:341) -#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST MW(342:342) -#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE MW(343:343) -#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE MW(344:344) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION MW(347:345) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH MW(348:348) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL MW(349:349) -#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE MW(350:350) -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE MW(351:351) -#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CORRELATION_ID MW(383:352) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER MW(415:384) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER MW(447:416) -#define NVCEC0_QMDV05_00_SASS_VERSION MW(455:448) -#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT MW(456:456) -#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVCEC0_QMDV05_00_SAMPLER_INDEX MW(457:457) -#define NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(463:458) -#define NVCEC0_QMDV05_00_QMD_MINOR_VERSION MW(467:464) -#define NVCEC0_QMDV05_00_QMD_MAJOR_VERSION MW(471:468) -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(472:472) -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(473:473) -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE MW(474:474) -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE MW(475:475) -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE MW(476:476) -#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(477:477) -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(478:478) -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(479:479) -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER MW(511:480) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER MW(536:512) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(575:544) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(607:576) -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(615:608) -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID MW(621:616) -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(622:622) -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(623:623) -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE MW(625:624) -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE MW(626:626) -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE MW(627:627) -#define NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM MW(635:628) -#define NVCEC0_QMDV05_00_SYNC_DOMAIN_ID MW(637:636) -#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(638:638) -#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT MW(639:639) -#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID MW(671:640) -#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID MW(703:672) -#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(721:714) -#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM MW(729:722) -#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID MW(730:730) -#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID MW(731:731) -#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE MW(732:732) -#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE MW(733:733) -#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE MW(734:734) -#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE MW(735:735) -#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP MW(743:736) -#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP MW(751:744) -#define NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER MW(759:752) -#define NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER MW(767:760) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER MW(799:768) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER MW(824:800) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER MW(863:832) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER MW(895:864) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER MW(927:896) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER MW(952:928) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER MW(991:960) -#define NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER MW(1023:992) -#define NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 MW(1055:1024) -#define NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 MW(1076:1056) -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE MW(1085:1077) -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE MW(1087:1086) -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 -#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 MW(1103:1088) -#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 MW(1119:1104) -#define NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 MW(1127:1120) -#define NVCEC0_QMDV05_00_REGISTER_COUNT MW(1136:1128) -#define NVCEC0_QMDV05_00_BARRIER_COUNT MW(1141:1137) -#define NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE MW(1147:1142) -#define NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 MW(1162:1152) -#define NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(1168:1163) -#define NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(1174:1169) -#define NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(1180:1175) -#define NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE MW(1181:1181) -#define NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 MW(1199:1184) -#define NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 MW(1215:1200) -#define NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT MW(1223:1216) -#define NVCEC0_QMDV05_00_GRID_WIDTH MW(1279:1248) -#define NVCEC0_QMDV05_00_GRID_HEIGHT MW(1295:1280) -#define NVCEC0_QMDV05_00_GRID_DEPTH MW(1327:1312) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1375+(i)*64):(1344+(i)*64)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i) MW((1394+(i)*64):(1376+(i)*64)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1407+(i)*64):(1395+(i)*64)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID(i) MW((1856+(i)*4):(1856+(i)*4)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH(i) MW((1858+(i)*4):(1857+(i)*4)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE 0x00000000 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE 0x00000001 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST 0x00000002 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1859+(i)*4):(1859+(i)*4)) -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(1919:1888) -#define NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1936:1920) -#define NVCEC0_QMDV05_00_GPC_CGA_WIDTH MW(2053:2048) -#define NVCEC0_QMDV05_00_GPC_CGA_HEIGHT MW(2061:2056) -#define NVCEC0_QMDV05_00_GPC_CGA_DEPTH MW(2069:2064) -#define NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE MW(2075:2072) -#define NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE MW(2079:2076) -#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE MW(2111:2111) -#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING 0x00000000 -#define NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST 0x00000001 -#define NVCEC0_QMDV05_00_GPU_CGA_WIDTH MW(2127:2112) -#define NVCEC0_QMDV05_00_GPU_CGA_HEIGHT MW(2143:2128) -#define NVCEC0_QMDV05_00_GPU_CGA_DEPTH MW(2159:2144) -#define NVCEC0_QMDV05_00_DEBUG_ID_LOWER MW(2207:2176) -#define NVCEC0_QMDV05_00_DEBUG_ID_UPPER MW(2239:2208) -#define NVCEC0_QMDV05_00_TPC_DISABLE_MASK(i) MW((2271+(i)*32):(2240+(i)*32)) -#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME MW(2527:2496) -#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME MW(2543:2528) -#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME MW(2559:2544) -#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME MW(2563:2560) -#define NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME MW(2567:2564) -#define NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(2596:2592) -#define NVCEC0_QMDV05_00_HW_ONLY_INNER_GET MW(2654:2624) -#define NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT MW(2686:2656) -#define NVCEC0_QMDV05_00_OUTER_PUT MW(3038:3008) -#define NVCEC0_QMDV05_00_OUTER_OVERFLOW MW(3039:3039) -#define NVCEC0_QMDV05_00_OUTER_GET MW(3070:3040) -#define NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW MW(3071:3071) - - -/* -** Queue Meta Data, Version 05_00 (inferred arrays) - */ - -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE(i) MW((336+(i)*8):(336+(i)*8)) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION(i) MW((339+(i)*8):(337+(i)*8)) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH(i) MW((340+(i)*8):(340+(i)*8)) -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER(i) MW((415+(i)*32):(384+(i)*32)) - - -/* -** Queue Meta Data, Version 05_01 - */ - -#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(29:0) -#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(30:30) -#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(31:31) -#define NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(63:32) -#define NVCEC0_QMDV05_01_INNER_GET MW(94:64) -#define NVCEC0_QMDV05_01_INNER_OVERFLOW MW(95:95) -#define NVCEC0_QMDV05_01_INNER_PUT MW(126:96) -#define NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW MW(127:127) -#define NVCEC0_QMDV05_01_DEPENDENCE_COUNTER MW(143:128) -#define NVCEC0_QMDV05_01_QMD_GROUP_ID MW(149:144) -#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(150:150) -#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_QMD_TYPE MW(153:151) -#define NVCEC0_QMDV05_01_QMD_TYPE_QUEUE 0x00000000 -#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL 0x00000001 -#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA 0x00000002 -#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA 0x00000003 -#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA 0x00000004 -#define NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005 -#define NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK MW(157:154) -#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS MW(158:158) -#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID MW(159:159) -#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE MW(184:160) -#define NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER MW(207:192) -#define NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID MW(210:208) -#define NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK MW(218:211) -#define NVCEC0_QMDV05_01_GRID_WIDTH_RESUME MW(255:224) -#define NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME MW(271:256) -#define NVCEC0_QMDV05_01_GRID_DEPTH_RESUME MW(287:272) -#define NVCEC0_QMDV05_01_RELEASE_ENABLE(i) MW((288+(i)*16):(288+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE(i) MW((290+(i)*16):(289+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE(i) MW((291+(i)*16):(291+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE(i) MW((292+(i)*16):(292+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP(i) MW((295+(i)*16):(293+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX 0x00000002 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC 0x00000003 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC 0x00000004 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND 0x00000005 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR 0x00000006 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR 0x00000007 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT(i) MW((297+(i)*16):(296+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE(i) MW((299+(i)*16):(298+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 -#define NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 -#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B(i) MW((300+(i)*16):(300+(i)*16)) -#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO(i) MW((303+(i)*16):(301+(i)*16)) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE MW(336:336) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION MW(339:337) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH MW(340:340) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION MW(341:341) -#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST MW(342:342) -#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE MW(343:343) -#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE MW(344:344) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION MW(347:345) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH MW(348:348) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL MW(349:349) -#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE MW(350:350) -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE MW(351:351) -#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CORRELATION_ID MW(383:352) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER MW(415:384) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER MW(447:416) -#define NVCEC0_QMDV05_01_SASS_VERSION MW(455:448) -#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT MW(456:456) -#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVCEC0_QMDV05_01_SAMPLER_INDEX MW(457:457) -#define NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(463:458) -#define NVCEC0_QMDV05_01_QMD_MINOR_VERSION MW(467:464) -#define NVCEC0_QMDV05_01_QMD_MAJOR_VERSION MW(471:468) -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(472:472) -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(473:473) -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE MW(474:474) -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE MW(475:475) -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE MW(476:476) -#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(477:477) -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(478:478) -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(479:479) -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER MW(511:480) -#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER MW(536:512) -#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(575:544) -#define NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(607:576) -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(615:608) -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID MW(621:616) -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(622:622) -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(623:623) -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE MW(625:624) -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE MW(626:626) -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE MW(627:627) -#define NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM MW(635:628) -#define NVCEC0_QMDV05_01_SYNC_DOMAIN_ID MW(637:636) -#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(638:638) -#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT MW(639:639) -#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID MW(671:640) -#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID MW(703:672) -#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM MW(721:714) -#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM MW(729:722) -#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID MW(730:730) -#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID MW(731:731) -#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE MW(732:732) -#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE MW(733:733) -#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE MW(734:734) -#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE MW(735:735) -#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP MW(743:736) -#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP MW(751:744) -#define NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER MW(759:752) -#define NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER MW(767:760) -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4(i) MW((799+(i)*416):(768+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4(i) MW((820+(i)*416):(800+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE(i) MW((829+(i)*416):(821+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE(i) MW((831+(i)*416):(830+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0(i) MW((847+(i)*416):(832+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1(i) MW((863+(i)*416):(848+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2(i) MW((871+(i)*416):(864+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT(i) MW((880+(i)*416):(872+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT(i) MW((885+(i)*416):(881+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID(i) MW((886+(i)*416):(886+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH(i) MW((888+(i)*416):(887+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST 0x00000002 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE(i) MW((889+(i)*416):(889+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE(i) MW((895+(i)*416):(890+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7(i) MW((906+(i)*416):(896+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE(i) MW((912+(i)*416):(907+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE(i) MW((918+(i)*416):(913+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE(i) MW((924+(i)*416):(919+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE(i) MW((925+(i)*416):(925+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4(i) MW((943+(i)*416):(928+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4(i) MW((959+(i)*416):(944+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6(i) MW((991+(i)*416):(960+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6(i) MW((1010+(i)*416):(992+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4(i) MW((1023+(i)*416):(1011+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6(i) MW((1055+(i)*416):(1024+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6(i) MW((1074+(i)*416):(1056+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4(i) MW((1087+(i)*416):(1075+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID(i) MW((1088+(i)*416):(1088+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH(i) MW((1090+(i)*416):(1089+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST 0x00000002 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE(i) MW((1091+(i)*416):(1091+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT(i) MW((1099+(i)*416):(1092+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH(i) MW((1151+(i)*416):(1120+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT(i) MW((1167+(i)*416):(1152+(i)*416)) -#define NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH(i) MW((1183+(i)*416):(1168+(i)*416)) - - -/* -** Queue Meta Data, Version 05_01 (inferred arrays) - */ - -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE(i) MW((336+(i)*8):(336+(i)*8)) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION(i) MW((339+(i)*8):(337+(i)*8)) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH(i) MW((340+(i)*8):(340+(i)*8)) -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER(i) MW((415+(i)*32):(384+(i)*32)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID(i,j) MW((886+(i)*416+(j)*202):(886+(i)*416+(j)*202)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH(i,j) MW((888+(i)*416+(j)*202):(887+(i)*416+(j)*202)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST 0x00000002 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE(i,j) MW((889+(i)*416+(j)*202):(889+(i)*416+(j)*202)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6(i,j) MW((991+(i)*416+(j)*64):(960+(i)*416+(j)*64)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6(i,j) MW((1010+(i)*416+(j)*64):(992+(i)*416+(j)*64)) -#define NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4(i,j) MW((1023+(i)*416+(j)*64):(1011+(i)*416+(j)*64)) - - -/* -** Queue Meta Data, Version 04_01 - */ - -#define NVCEC0_QMDV04_01_DEPENDENCE_COUNTER MW(15:0) -#define NVCEC0_QMDV04_01_QMD_GROUP_ID MW(21:16) -#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(22:22) -#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_QMD_TYPE MW(25:23) -#define NVCEC0_QMDV04_01_QMD_TYPE_QUEUE 0x00000000 -#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL 0x00000001 -#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA 0x00000002 -#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA 0x00000003 -#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA 0x00000004 -#define NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA 0x00000005 -#define NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID MW(28:28) -#define NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID MW(29:29) -#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS MW(30:30) -#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID MW(31:31) -#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE MW(56:32) -#define NVCEC0_QMDV04_01_INNER_GET MW(94:64) -#define NVCEC0_QMDV04_01_INNER_OVERFLOW MW(95:95) -#define NVCEC0_QMDV04_01_INNER_PUT MW(126:96) -#define NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW MW(127:127) -#define NVCEC0_QMDV04_01_HW_ONLY_INNER_GET MW(190:160) -#define NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT MW(222:192) -#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(253:224) -#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(254:254) -#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(287:256) -#define NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER MW(303:288) -#define NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(304:304) -#define NVCEC0_QMDV04_01_RELEASE_ENABLE(i) MW((320+(i)*16):(320+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE(i) MW((322+(i)*16):(321+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 -#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE(i) MW((323+(i)*16):(323+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE(i) MW((324+(i)*16):(324+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP(i) MW((327+(i)*16):(325+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX 0x00000002 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC 0x00000003 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC 0x00000004 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND 0x00000005 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR 0x00000006 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR 0x00000007 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT(i) MW((329+(i)*16):(328+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE(i) MW((331+(i)*16):(330+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 -#define NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 -#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B(i) MW((332+(i)*16):(332+(i)*16)) -#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO(i) MW((335+(i)*16):(333+(i)*16)) -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE(i) MW((368+(i)*5):(368+(i)*5)) -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION(i) MW((371+(i)*5):(369+(i)*5)) -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT 0x00000000 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE 0x00000001 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH(i) MW((372+(i)*5):(372+(i)*5)) -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION MW(378:378) -#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST MW(379:379) -#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE MW(380:380) -#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL MW(381:381) -#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE MW(382:382) -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CORRELATION_ID MW(415:384) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID(i) MW((416+(i)*4):(416+(i)*4)) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH(i) MW((418+(i)*4):(417+(i)*4)) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE 0x00000000 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE 0x00000001 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST 0x00000002 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE(i) MW((419+(i)*4):(419+(i)*4)) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER MW(479:448) -#define NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER MW(511:480) -#define NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(535:512) -#define NVCEC0_QMDV04_01_SASS_VERSION MW(543:536) -#define NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(567:544) -#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT MW(568:568) -#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 -#define NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 -#define NVCEC0_QMDV04_01_SAMPLER_INDEX MW(569:569) -#define NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 -#define NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 MW(575:570) -#define NVCEC0_QMDV04_01_QMD_MINOR_VERSION MW(579:576) -#define NVCEC0_QMDV04_01_QMD_MAJOR_VERSION MW(583:580) -#define NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE MW(601:584) -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(602:602) -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(603:603) -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE MW(604:604) -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE MW(605:605) -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE MW(606:606) -#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(607:607) -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(613:608) -#define NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(619:614) -#define NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(625:620) -#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE MW(626:626) -#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER MW(671:640) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER MW(696:672) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER MW(735:704) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER MW(767:736) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER MW(799:768) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER MW(824:800) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER MW(863:832) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER MW(895:864) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER MW(927:896) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER MW(952:928) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER MW(991:960) -#define NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER MW(1023:992) -#define NVCEC0_QMDV04_01_GRID_WIDTH MW(1055:1024) -#define NVCEC0_QMDV04_01_GRID_HEIGHT MW(1071:1056) -#define NVCEC0_QMDV04_01_GRID_DEPTH MW(1103:1088) -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(1127:1120) -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID MW(1133:1128) -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(1134:1134) -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(1135:1135) -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE MW(1137:1136) -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 -#define NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 -#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS MW(1138:1138) -#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE MW(1139:1139) -#define NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM MW(1147:1140) -#define NVCEC0_QMDV04_01_SYNC_DOMAIN_ID MW(1149:1148) -#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH MW(1150:1150) -#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT MW(1151:1151) -#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 MW(1167:1152) -#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 MW(1183:1168) -#define NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 MW(1191:1184) -#define NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT MW(1199:1192) -#define NVCEC0_QMDV04_01_REGISTER_COUNT MW(1208:1200) -#define NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE MW(1210:1210) -#define NVCEC0_QMDV04_01_BARRIER_COUNT MW(1215:1211) -#define NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER MW(1247:1216) -#define NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER MW(1272:1248) -#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP MW(1287:1280) -#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP MW(1295:1288) -#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER MW(1303:1296) -#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER MW(1311:1304) -#define NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM MW(1319:1312) -#define NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM MW(1327:1320) -#define NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE MW(1333:1328) -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(1375:1344) -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1392:1376) -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE MW(1401:1393) -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE MW(1403:1402) -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 -#define NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE MW(1406:1406) -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE MW(1407:1407) -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 -#define NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 -#define NVCEC0_QMDV04_01_GRID_WIDTH_RESUME MW(1439:1408) -#define NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME MW(1455:1440) -#define NVCEC0_QMDV04_01_GRID_DEPTH_RESUME MW(1471:1456) -#define NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID MW(1503:1472) -#define NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID MW(1535:1504) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i) MW((1567+(i)*64):(1536+(i)*64)) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i) MW((1586+(i)*64):(1568+(i)*64)) -#define NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1599+(i)*64):(1587+(i)*64)) -#define NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD MW(2135:2128) -#define NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 MW(2140:2136) -#define NVCEC0_QMDV04_01_GPC_CGA_WIDTH MW(2149:2144) -#define NVCEC0_QMDV04_01_GPC_CGA_HEIGHT MW(2157:2152) -#define NVCEC0_QMDV04_01_GPC_CGA_DEPTH MW(2165:2160) -#define NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE MW(2171:2168) -#define NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE MW(2175:2172) -#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE MW(2207:2207) -#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING 0x00000000 -#define NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST 0x00000001 -#define NVCEC0_QMDV04_01_GPU_CGA_WIDTH MW(2223:2208) -#define NVCEC0_QMDV04_01_GPU_CGA_HEIGHT MW(2239:2224) -#define NVCEC0_QMDV04_01_GPU_CGA_DEPTH MW(2255:2240) -#define NVCEC0_QMDV04_01_DEBUG_ID_LOWER MW(2399:2368) -#define NVCEC0_QMDV04_01_DEBUG_ID_UPPER MW(2431:2400) -#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK(i) MW((2463+(i)*32):(2432+(i)*32)) -#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME MW(2591:2560) -#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME MW(2607:2592) -#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME MW(2623:2608) -#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME MW(2627:2624) -#define NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME MW(2631:2628) -#define NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER(i) MW((2719+(i)*32):(2688+(i)*32)) -#define NVCEC0_QMDV04_01_OUTER_PUT MW(3038:3008) -#define NVCEC0_QMDV04_01_OUTER_OVERFLOW MW(3039:3039) -#define NVCEC0_QMDV04_01_OUTER_GET MW(3070:3040) -#define NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW MW(3071:3071) - - - -#endif // #ifndef __CLCEC0QMD_H__ diff --git a/tinygrad/extra/nv_gpu_driver/nv_ioctl.py b/tinygrad/extra/nv_gpu_driver/nv_ioctl.py deleted file mode 100644 index 30a6c183..00000000 --- a/tinygrad/extra/nv_gpu_driver/nv_ioctl.py +++ /dev/null @@ -1,275 +0,0 @@ -# type: ignore -import ctypes, ctypes.util, struct, platform, pathlib, re, time, os, signal -from tinygrad.helpers import from_mv, to_mv, getenv, init_c_struct_t -from hexdump import hexdump -start = time.perf_counter() - -# *** ioctl lib *** -libc = ctypes.CDLL(ctypes.util.find_library("c")) -processor = platform.processor() -IOCTL_SYSCALL = {"aarch64": 0x1d, "x86_64":16}[processor] -MMAP_SYSCALL = {"aarch64": 0xde, "x86_64":0x09}[processor] - -def get_struct(argp, stype): - return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents - -def dump_struct(st): - if getenv("IOCTL", 0) == 0: return - print("\t", st.__class__.__name__, end=" { ") - for v in type(st)._fields_: print(f"{v[0]}={getattr(st, v[0])}", end=" ") - print("}") - -def format_struct(s): - sdats = [] - for field in s._fields_: - dat = getattr(s, field[0]) - if isinstance(dat, int): sdats.append(f"{field[0]}:0x{dat:X}") - else: sdats.append(f"{field[0]}:{dat}") - return sdats - -real_func_pool = {} -def install_hook(c_function, python_function): - orig_func = (ctypes.c_char*4096)() - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - if processor == "aarch64": - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - elif processor == "x86_64": - # 0x0000000000000000: 49 BB aa aa aa aa aa aa aa aa movabs r11,
- # 0x000000000000000a: 41 FF E3 jmp r11 - tramp = b"\x49\xBB" + struct.pack("Q", python_function_addr) + b"\x41\xFF\xE3" - else: - raise Exception(f"processor {processor} not supported") - - # get real ioctl address - ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - - # hook ioctl - ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7) - assert ret == 0 - ret = libc.mprotect(ctypes.c_ulong((ctypes.addressof(orig_func)//0x1000)*0x1000), 0x3000, 7) - assert ret == 0 - libc.memcpy(orig_func, ioctl_address.contents, 0x1000) - libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp)) - return orig_func - -# *** ioctl lib end *** -import tinygrad.runtime.autogen.nv_gpu as nv_gpu -nvescs = {getattr(nv_gpu, x):x for x in dir(nv_gpu) if x.startswith("NV_ESC")} -nvcmds = {getattr(nv_gpu, x):(x, getattr(nv_gpu, "struct_"+x+"_PARAMS", getattr(nv_gpu, "struct_"+x.replace("_CMD_", "_")+"_PARAMS", None))) for x in dir(nv_gpu) if \ - x.startswith("NV") and x[6:].startswith("_CTRL_") and isinstance(getattr(nv_gpu, x), int)} - -def get_classes(): - hdrpy = (pathlib.Path(__file__).parent.parent.parent / "tinygrad/runtime/autogen/nv_gpu.py").read_text() - clss = re.search(r'NV01_ROOT.*?NV_SEMAPHORE_SURFACE = \(0x000000da\) # macro', hdrpy, re.DOTALL).group() - pattern = r'([0-9a-zA-Z_]*) = +\((0x[0-9a-fA-F]+)\)' - matches = re.findall(pattern, clss, re.MULTILINE) - return {int(num, base=16):name for name, num in matches} -nvclasses = get_classes() -nvuvms = {getattr(nv_gpu, x):x for x in dir(nv_gpu) if x.startswith("UVM_") and nv_gpu.__dict__.get(x+"_PARAMS")} -nvqcmds = {int(getattr(nv_gpu, x)):x for x in dir(nv_gpu) if x[:7] in {"NVC6C0_", "NVC56F_", "NVC6B5_"} and isinstance(getattr(nv_gpu, x), int)} - -global_ioctl_id = 0 -gpus_user_modes = [] -gpus_mmio = [] -gpus_fifo = [] - -@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p) -def ioctl(fd, request, argp): - global global_ioctl_id, gpus_user_modes, gpus_mmio - global_ioctl_id += 1 - st = time.perf_counter() - ret = libc.syscall(IOCTL_SYSCALL, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp)) - et = time.perf_counter()-st - fn = os.readlink(f"/proc/self/fd/{fd}") - #print(f"ioctl {request:8x} {fn:20s}") - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - if getenv("IOCTL", 0) >= 1: print(f"#{global_ioctl_id}: ", end="") - if itype == ord(nv_gpu.NV_IOCTL_MAGIC): - if nr == nv_gpu.NV_ESC_RM_CONTROL: - s = get_struct(argp, nv_gpu.NVOS54_PARAMETERS) - if s.cmd in nvcmds: - name, struc = nvcmds[s.cmd] - if getenv("IOCTL", 0) >= 1: - print(f"NV_ESC_RM_CONTROL cmd={name:30s} hClient={s.hClient}, hObject={s.hObject}, flags={s.flags}, params={s.params}, paramsSize={s.paramsSize}, status={s.status}") - - if struc is not None: dump_struct(get_struct(s.params, struc)) - elif hasattr(nv_gpu, name+"_PARAMS"): dump_struct(get_struct(argp, getattr(nv_gpu, name+"_PARAMS"))) - elif name == "NVA06C_CTRL_CMD_GPFIFO_SCHEDULE": dump_struct(get_struct(argp, nv_gpu.NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS)) - elif name == "NV83DE_CTRL_CMD_GET_MAPPINGS": dump_struct(get_struct(s.params, nv_gpu.NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS)) - else: - if getenv("IOCTL", 0) >= 1: print("unhandled cmd", hex(s.cmd)) - # format_struct(s) - # print(f"{(st-start)*1000:7.2f} ms +{et*1000.:7.2f} ms : {ret:2d} = {name:40s}", ' '.join(format_struct(s))) - elif nr == nv_gpu.NV_ESC_RM_ALLOC: - s = get_struct(argp, nv_gpu.NVOS21_PARAMETERS) - if getenv("IOCTL", 0) >= 1: print(f"NV_ESC_RM_ALLOC hClass={nvclasses.get(s.hClass, f'unk=0x{s.hClass:X}'):30s}, hRoot={s.hRoot}, hObjectParent={s.hObjectParent}, pAllocParms={s.pAllocParms}, hObjectNew={s.hObjectNew} status={s.status}") - if s.pAllocParms is not None: - if s.hClass == nv_gpu.NV01_DEVICE_0: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV0080_ALLOC_PARAMETERS)) - if s.hClass == nv_gpu.FERMI_VASPACE_A: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_VASPACE_ALLOCATION_PARAMETERS)) - if s.hClass == nv_gpu.NV50_MEMORY_VIRTUAL: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS)) - if s.hClass == nv_gpu.NV1_MEMORY_USER: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS)) - if s.hClass == nv_gpu.NV1_MEMORY_SYSTEM: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_MEMORY_ALLOCATION_PARAMS)) - if s.hClass == nv_gpu.GT200_DEBUGGER: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV83DE_ALLOC_PARAMETERS)) - if s.hClass == nv_gpu.AMPERE_CHANNEL_GPFIFO_A: - sx = get_struct(s.pAllocParms, nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS) - dump_struct(sx) - gpus_fifo.append((sx.gpFifoOffset, sx.gpFifoEntries)) - if s.hClass == nv_gpu.KEPLER_CHANNEL_GROUP_A: dump_struct(get_struct(s.pAllocParms, nv_gpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS)) - if s.hClass == nv_gpu.TURING_USERMODE_A: gpus_user_modes.append(s.hObjectNew) - elif nr == nv_gpu.NV_ESC_RM_MAP_MEMORY: - # nv_ioctl_nvos33_parameters_with_fd - if getenv("IOCTL", 0) >= 1: - s = get_struct(argp, nv_gpu.NVOS33_PARAMETERS) - print(f"NV_ESC_RM_MAP_MEMORY hClient={s.hClient}, hDevice={s.hDevice}, hMemory={s.hMemory}, length={s.length} flags={s.flags} pLinearAddress={s.pLinearAddress}") - elif nr == nv_gpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: - if getenv("IOCTL", 0) >= 1: - s = get_struct(argp, nv_gpu.NVOS56_PARAMETERS) - print(f"NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO hClient={s.hClient}, hDevice={s.hDevice}, hMemory={s.hMemory}, pOldCpuAddress={s.pOldCpuAddress} pNewCpuAddress={s.pNewCpuAddress} status={s.status}") - elif nr == nv_gpu.NV_ESC_RM_ALLOC_MEMORY: - if getenv("IOCTL", 0) >= 1: - s = get_struct(argp, nv_gpu.nv_ioctl_nvos02_parameters_with_fd) - print(f"NV_ESC_RM_ALLOC_MEMORY fd={s.fd}, hRoot={s.params.hRoot}, hObjectParent={s.params.hObjectParent}, hObjectNew={s.params.hObjectNew}, hClass={s.params.hClass}, flags={s.params.flags}, pMemory={s.params.pMemory}, limit={s.params.limit}, status={s.params.status}") - elif nr == nv_gpu.NV_ESC_ALLOC_OS_EVENT: - if getenv("IOCTL", 0) >= 1: - s = get_struct(argp, nv_gpu.nv_ioctl_alloc_os_event_t) - print(f"NV_ESC_ALLOC_OS_EVENT hClient={s.hClient} hDevice={s.hDevice} fd={s.fd} Status={s.Status}") - elif nr == nv_gpu.NV_ESC_REGISTER_FD: - if getenv("IOCTL", 0) >= 1: - s = get_struct(argp, nv_gpu.nv_ioctl_register_fd_t) - print(f"NV_ESC_REGISTER_FD fd={s.ctl_fd}") - elif nr in nvescs: - if getenv("IOCTL", 0) >= 1: print(nvescs[nr]) - else: - if getenv("IOCTL", 0) >= 1: print("unhandled NR", nr) - elif fn.endswith("nvidia-uvm"): - if getenv("IOCTL", 0) >= 1: - print(f"{nvuvms.get(request, f'UVM UNKNOWN {request=}')}") - if nvuvms.get(request) is not None: dump_struct(get_struct(argp, getattr(nv_gpu, nvuvms.get(request)+"_PARAMS"))) - if nvuvms.get(request) == "UVM_MAP_EXTERNAL_ALLOCATION": - st = get_struct(argp, getattr(nv_gpu, nvuvms.get(request)+"_PARAMS")) - for i in range(st.gpuAttributesCount): - print("perGpuAttributes[{i}] = ", end="") - dump_struct(st.perGpuAttributes[i]) - - if getenv("IOCTL") >= 2: print("ioctl", f"{idir=} {size=} {itype=} {nr=} {fd=} {ret=}", fn) - return ret - -@ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long) -def _mmap(addr, length, prot, flags, fd, offset): - mmap_type = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long) - orig_mmap = mmap_type(ctypes.addressof(orig_mmap_mv)) - ret = orig_mmap(addr, length, prot, flags, fd, offset) - # ll = os.readlink(f"/proc/self/fd/{fd}") if fd >= 0 else "" - print(f"mmap {addr=}, {length=}, {prot=}, {flags=}, {fd=}, {offset=} {ret=}") - return ret - -install_hook(libc.ioctl, ioctl) -if getenv("IOCTL") >= 3: orig_mmap_mv = install_hook(libc.mmap, _mmap) - -import collections -old_gpputs = collections.defaultdict(int) -def _dump_gpfifo(mark): - launches = [] - - # print("_dump_gpfifo:", mark) - for start, size in gpus_fifo: - gpfifo_controls = nv_gpu.AmpereAControlGPFifo.from_address(start+size*8) - gpfifo = to_mv(start, size * 8).cast("Q") - while old_gpputs[start] != gpfifo_controls.GPPut: - addr = ((gpfifo[old_gpputs[start]] & ((1 << 40)-1)) >> 2) << 2 - pckt_cnt = (gpfifo[old_gpputs[start]]>>42)&((1 << 20)-1) - - # print(f"\t{i}: 0x{gpfifo[i % size]:x}: addr:0x{addr:x} packets:{pckt_cnt} sync:{(gpfifo[i % size] >> 63) & 0x1} fetch:{gpfifo[i % size] & 0x1}") - x = _dump_qmd(addr, pckt_cnt) - if isinstance(x, list): launches += x - old_gpputs[start] += 1 - old_gpputs[start] %= size - return launches - -import types -def make_qmd_struct_type(): - fields: List[Tuple[str, Union[Type[ctypes.c_uint64], Type[ctypes.c_uint32]], Any]] = [] - bits = [(name,dt) for name,dt in nv_gpu.__dict__.items() if name.startswith("NVC6C0_QMDV03_00") and isinstance(dt, tuple)] - bits += [(name+f"_{i}",dt(i)) for name,dt in nv_gpu.__dict__.items() for i in range(8) if name.startswith("NVC6C0_QMDV03_00") and callable(dt)] - bits = sorted(bits, key=lambda x: x[1][1]) - for i,(name, data) in enumerate(bits): - if i > 0 and (gap:=(data[1] - bits[i-1][1][0] - 1)) != 0: fields.append((f"_reserved{i}", ctypes.c_uint32, gap)) - fields.append((name.replace("NVC6C0_QMDV03_00_", "").lower(), ctypes.c_uint32, data[0]-data[1]+1)) - if len(fields) >= 2 and fields[-2][0].endswith('_lower') and fields[-1][0].endswith('_upper') and fields[-1][0][:-6] == fields[-2][0][:-6]: - fields = fields[:-2] + [(fields[-1][0][:-6], ctypes.c_uint64, fields[-1][2] + fields[-2][2])] - return init_c_struct_t(tuple(fields)) -qmd_struct_t = make_qmd_struct_type() -assert ctypes.sizeof(qmd_struct_t) == 0x40 * 4 - -def _dump_qmd(address, packets): - qmds = [] - gpfifo = to_mv(address, packets * 4).cast("I") - - i = 0 - while i < packets: - dat = gpfifo[i] - typ = (dat>>28) & 0xF - if typ == 0: break - size = (dat>>16) & 0xFFF - subc = (dat>>13) & 7 - mthd = (dat<<2) & 0x7FFF - method_name = nvqcmds.get(mthd, f"unknown method #{mthd}") - if getenv("IOCTL", 0) >= 1: - print(f"\t\t{method_name}, {typ=} {size=} {subc=} {mthd=}") - for j in range(size): print(f"\t\t\t{j}: {gpfifo[i+j+1]} | 0x{gpfifo[i+j+1]:x}") - if mthd == 792: - qmds.append(qmd_struct_t.from_address(address + 12 + i * 4)) - elif mthd == nv_gpu.NVC6C0_SEND_PCAS_A: - qmds.append(qmd_struct_t.from_address(gpfifo[i+1] << 8)) - - i += size + 1 - return qmds - -# This is to be used in fuzzer, check cuda/nv side by side. -# Return a state which should be compare and compare function. -def before_launch(): _dump_gpfifo("before launch") -def collect_last_launch_state(): return _dump_gpfifo("after launch") - -def compare_launch_state(states, good_states): - states = states or list() - good_states = good_states or list() - if len(states) != 1 or len(good_states) != 1: - return False, f"Some states not captured. {len(states)}!=1 || {len(good_states)}!=1" - - for i in range(len(states)): - state, good_state = states[i], good_states[i] - - for n in ['qmd_major_version', 'invalidate_shader_data_cache', 'invalidate_shader_data_cache', - 'sm_global_caching_enable', 'invalidate_texture_header_cache', 'invalidate_texture_sampler_cache', - 'barrier_count', 'sampler_index', 'api_visible_call_limit', 'cwd_membar_type', 'sass_version', - 'max_sm_config_shared_mem_size', 'register_count_v', 'shared_memory_size']: - if getattr(state, n) != getattr(good_state, n): - return False, f"Field {n} mismatch: {getattr(state, n)} vs {getattr(good_state, n)}" - - # Allow NV to allocate more, at least this is not exact problem, so ignore it here. - # Hmm, CUDA minimum is 0x640, is this hw-required minimum (will check)? - if state.shader_local_memory_high_size < good_state.shader_local_memory_high_size and good_state.shader_local_memory_high_size > 0x640: - return False, f"Field shader_local_memory_high_size mismatch: {state.shader_local_memory_high_size}vs{good_state.shader_local_memory_high_size}" - - # TODO: Can't request more, since it might not be optimal, but need to investigate their formula for this.. #7133 - if state.min_sm_config_shared_mem_size > good_state.min_sm_config_shared_mem_size and good_state.min_sm_config_shared_mem_size > 5: - return (False, - f"Field min_sm_config_shared_mem_size mismatch: {state.min_sm_config_shared_mem_size}vs{good_state.min_sm_config_shared_mem_size}") - if state.target_sm_config_shared_mem_size > good_state.target_sm_config_shared_mem_size and good_state.target_sm_config_shared_mem_size > 5: - return (False, - f"Field target_sm_config_shared_mem_size mismatch: {state.target_sm_config_shared_mem_size}vs{good_state.target_sm_config_shared_mem_size}") - - for i in range(8): - if i in {1, 7}: continue # shaders don't use that. what's cuda put here? - n = f"constant_buffer_valid_{i}" - if getattr(state, n) != getattr(good_state, n): - return False, f"Field {n} mismatch: {getattr(state, n)} vs {getattr(good_state, n)}" - - return True, "PASS" - -# IOCTL=1 PTX=1 CUDA=1 python3 test/test_ops.py TestOps.test_tiny_add \ No newline at end of file diff --git a/tinygrad/extra/onnx.py b/tinygrad/extra/onnx.py deleted file mode 100644 index f89bdbb2..00000000 --- a/tinygrad/extra/onnx.py +++ /dev/null @@ -1,835 +0,0 @@ -from types import SimpleNamespace -from typing import Any, Sequence, cast, Literal, Callable -import dataclasses, functools, io, math, types -from tinygrad.tensor import Tensor, _broadcast_shape, ReductionStr -from tinygrad.helpers import getenv, DEBUG, all_same, prod, flatten, make_tuple, argsort -from tinygrad.dtype import DType, ConstType, dtypes, ImageDType -from tinygrad.device import is_dtype_supported, Device - -# ***** protobuf parsing ****** -from onnx import AttributeProto, ModelProto, TensorProto, TypeProto, helper -import numpy as np - -def has_field(onnx_type: TypeProto|SimpleNamespace, field): - if isinstance(onnx_type, TypeProto): return onnx_type.HasField(field) - return hasattr(onnx_type, field) - -def dtype_parse(onnx_dtype: int) -> DType: - supported: dict[int, DType] = { - TensorProto.FLOAT:dtypes.float32, TensorProto.UINT8:dtypes.uint8, TensorProto.INT8:dtypes.int8, - TensorProto.UINT16:dtypes.uint16, TensorProto.INT16:dtypes.int16, TensorProto.INT32:dtypes.int32, TensorProto.INT64:dtypes.int64, - TensorProto.BOOL:dtypes.bool, TensorProto.FLOAT16:dtypes.float32, TensorProto.DOUBLE:dtypes.double, TensorProto.UINT32:dtypes.uint32, - TensorProto.UINT64:dtypes.uint64, TensorProto.BFLOAT16:dtypes.bfloat16, - } - unsupported = { - TensorProto.UNDEFINED, TensorProto.STRING, TensorProto.COMPLEX64, TensorProto.COMPLEX128, TensorProto.FLOAT8E4M3FN, TensorProto.FLOAT8E4M3FNUZ, - TensorProto.FLOAT8E5M2, TensorProto.FLOAT8E5M2FNUZ, TensorProto.UINT4, TensorProto.INT4 - } - if onnx_dtype in unsupported: raise NotImplementedError(f"onnx dtype {TensorProto.DataType.Name(onnx_dtype)} is not supported") - return supported[onnx_dtype] if is_dtype_supported(supported[onnx_dtype]) else dtypes.float - -def attribute_parse(onnx_attribute: AttributeProto): - supported: dict[AttributeProto.AttributeType, Callable[[AttributeProto], Any]] = { - AttributeProto.FLOAT: lambda a: float(a.f), AttributeProto.INT: lambda a: int(a.i), - AttributeProto.STRING: lambda a: a.s.data().tobytes().decode("utf8") if isinstance(a.s, Tensor) else a.s.decode("utf8"), - AttributeProto.TENSOR: lambda a: buffer_parse(a.t), - AttributeProto.FLOATS: lambda a: tuple(float(x) for x in a.floats), AttributeProto.INTS: lambda a: tuple(int(x) for x in a.ints), - AttributeProto.STRINGS: lambda a: tuple(x.data().tobytes().decode("utf8") for x in a.strings) - } - unsupported = { - AttributeProto.UNDEFINED, AttributeProto.GRAPH, AttributeProto.SPARSE_TENSOR, AttributeProto.TYPE_PROTO, AttributeProto.TENSORS, - AttributeProto.GRAPHS, AttributeProto.SPARSE_TENSORS, AttributeProto.TYPE_PROTOS - } - if onnx_attribute.type in unsupported: - raise NotImplementedError(f"attribute with type {AttributeProto.AttributeType.Name(onnx_attribute.type)} is not supported") - return supported[onnx_attribute.type](onnx_attribute) - -def buffer_parse(onnx_tensor: TensorProto) -> Tensor: - if onnx_tensor.string_data: raise NotImplementedError("Parsing for buffer with string data is not implemented.") - dtype, shape = dtype_parse(onnx_tensor.data_type), tuple(onnx_tensor.dims) - data = None - if len(onnx_tensor.float_data): data = onnx_tensor.float_data - elif len(onnx_tensor.int32_data): data = onnx_tensor.int32_data - elif len(onnx_tensor.int64_data): data = onnx_tensor.int64_data - elif len(onnx_tensor.double_data): data = onnx_tensor.double_data - elif len(onnx_tensor.uint64_data): data = onnx_tensor.uint64_data - if isinstance(data, Tensor): - if len(data) == 1: return Tensor(data.tolist()[0], dtype=dtype).reshape(shape) - return data.cast(dtype).reshape(shape).to(Device.DEFAULT) - if has_field(onnx_tensor, "raw_data"): - if onnx_tensor.data_type == TensorProto.FLOAT16: - np_buffer = np.frombuffer(onnx_tensor.raw_data.data().tobytes(), - dtype=helper.tensor_dtype_to_np_dtype(onnx_tensor.data_type)).copy().reshape(shape) - if np_buffer.size == 1: return Tensor(np_buffer.item(), dtype=dtype).reshape(shape) - return Tensor(np_buffer, dtype=dtype) - ret = onnx_tensor.raw_data.bitcast(dtype).reshape(shape).to(Device.DEFAULT) - if shape == (): ret = Tensor(ret.item(), dtype=dtype).reshape(shape) - return ret - return Tensor(None) - -def type_parse(onnx_type: TypeProto): - elem_type = onnx_type - if has_field(elem_type, "map_type") or has_field(elem_type, "sparse_tensor_type") or has_field(elem_type, "opaque_type"): - raise NotImplementedError("parsing for map_type, sparse_tensor_type and opaque_type are not implemented") - if is_optional := has_field(elem_type, "optional_type"): elem_type = elem_type.optional_type.elem_type - if is_sequence := has_field(elem_type, "sequence_type"): elem_type = elem_type.sequence_type.elem_type - if has_field(elem_type, "tensor_type"): - shape = tuple(getattr(d, "dim_param", None) or getattr(d, "dim_value") for d in elem_type.tensor_type.shape.dim) \ - if has_field(elem_type.tensor_type, "shape") else None # test_identity_sequence_cpu - dtype = dtype_parse(elem_type.tensor_type.elem_type) - return OnnxValue(shape, dtype, is_optional, is_sequence) - raise RuntimeError(f"TypeProto was not parsed properly: {onnx_type=}") - -# ***** onnx spec ***** -@dataclasses.dataclass(frozen=True) -class OnnxValue: - shape: tuple[str|int, ...] - dtype: DType - is_optional: bool - is_sequence: bool - -@dataclasses.dataclass(frozen=True) -class OnnxNode: - num: int - op: str - inputs: tuple[str, ...] - outputs: tuple[str, ...] - opts: dict[str, Any] - -# ***** python const ***** -required_input_python_consts: dict[str, tuple[int, ...]] = { - "Tile": (1,), "Range": (0,1,2), "Expand": (1,), "Reshape": (1,), "Squeeze": (1,), "Unsqueeze": (1,), "Trilu": (1,), "ConstantOfShape": (0,), - "CumSum": (1,), "TopK": (1,), "Pad": (1,2,3), "MaxUnpool": (2,), "Dropout": (1,2), "CenterCropPad": (1,), "OneHot": (1,), "Compress": (1,), - "ImageDecoder": (0,), "AffineGrid": (1,), "Resize": (1,2,3), "Upsample": (1,), "Split": (1,), "Slice": (1,2,3,4), - **{"Reduce"+r: (1,) for r in ("Max", "Min", "Sum", "Mean", "SumSquare", "Prod", "L1", "L2", "LogSum", "LogSumExp")}, - **{optim: (1,) for optim in ("Adam", "Adagrad", "Momentum")} -} - -cache_misses = 0 -@functools.cache -def _cached_to_python_const(t:Tensor): - if t.dtype is dtypes.uint8: return t.data().tobytes() - if 0 in t.shape: return [] - return t.tolist() - -# Tensor -> python value cache for parameters -def to_python_const(t:Any, op:str, idx:int) -> list[ConstType]|ConstType|bytes: - if idx not in required_input_python_consts.get(op, ()) or not isinstance(t, Tensor): return t - global cache_misses - ret = _cached_to_python_const(t) - if (info := _cached_to_python_const.cache_info()).misses > cache_misses and DEBUG >= 3: - print(f"Cache miss for {t}") - cache_misses = info.misses - return ret - -# ***** runner ****** -debug = int(getenv("DEBUGONNX", "0")) -limit = int(getenv("ONNXLIMIT", "-1")) -class OnnxRunner: - def __init__(self, model: ModelProto|SimpleNamespace): - # parse model protobuf - self.is_training = any(n.domain in {"ai.onnx.training", "ai.onnx.preview.training"} for n in model.graph.node) - self.old_training = Tensor.training - Tensor.training = True if self.is_training else False - self.graph_values = {"": None, **{x.name:buffer_parse(x) for x in model.graph.initializer}} - self.graph_inputs = {x.name:type_parse(x.type) for x in model.graph.input if x.name not in self.graph_values} - self.graph_outputs = tuple(x.name for x in model.graph.output) - self.graph_nodes = tuple(OnnxNode(num, n.op_type, tuple(n.input), tuple(n.output), {x.name:attribute_parse(x) for x in n.attribute}) - for num,n in enumerate(model.graph.node)) - self.opset_version = model.opset_import[0].version - self.variable_dims: dict[str, int] = {} - - self.onnx_ops = onnx_ops - - def _parse_input(self, name: str, value: Any, spec: OnnxValue): - if spec.is_optional and value is None: return None - # TODO: need true float16 for dtype checking - if spec.is_sequence: - if not isinstance(value, Sequence): raise RuntimeError(f"{name} received {value}, expected a sequence type") - sequence = [Tensor(v, dtype=spec.dtype, requires_grad=self.is_training) if not isinstance(v, Tensor) else v for v in value] - if not all_same(tuple(t.shape for t in sequence)): raise RuntimeError(f"Shapes for {name} sequence must be homogeneous") - return sequence - tensor = Tensor(value, dtype=spec.dtype, requires_grad=self.is_training) if not isinstance(value, Tensor) else value - for dim, (onnx_dim, user_dim_input) in enumerate(zip(spec.shape, tensor.shape, strict=True)): - if isinstance(onnx_dim, str): - onnx_dim = self.variable_dims[onnx_dim] if onnx_dim in self.variable_dims else self.variable_dims.setdefault(onnx_dim, int(user_dim_input)) - if user_dim_input != onnx_dim: raise RuntimeError(f"{name} has mismatch on {dim=}. Expected {onnx_dim}, received {user_dim_input}.") - return tensor - - def _dispatch_op(self, op, inps, opts): - if op in self.onnx_ops: - fxn = self.onnx_ops[op] - if isinstance(fxn, dict): - for k in sorted(fxn.keys()): - if k <= self.opset_version: - real_fxn = fxn[k] - else: real_fxn = fxn - return real_fxn(*inps, **opts) - raise NotImplementedError(f"{op=} not supported") - - def get_empty_input_data(self, device:str|None=None) -> dict[str, Tensor]: - return {name:Tensor.empty(*spec.shape, device=device, dtype=spec.dtype) for name, spec in self.graph_inputs.items()} - - def __call__(self, inputs:dict[str, Any], debug=debug): - for name, input_spec in self.graph_inputs.items(): - if name not in inputs: raise RuntimeError(f"Please provide input data for {name}") - self.graph_values[name] = self._parse_input(name, inputs[name], input_spec) - - for node in self.graph_nodes: - inps = [to_python_const(self.graph_values[name], node.op, i) for i,name in enumerate(node.inputs)] - opts = node.opts - - # provide additional opts - if node.op == "Split" and 'num_outputs' not in opts: opts['num_outputs'] = len(node.outputs) - if node.op == "Gradient": opts['intermediate_tensors'] = self.graph_values - - if debug >= 1: print(f"{node.num}: op '{node.op}' opt {opts}") - if debug >= 2 and node.inputs: print("\tinputs:\n" + "\n".join(f"\t\t{x} - {i!r}" for x,i in zip(node.inputs, inps))) - ret = self._dispatch_op(node.op, inps, opts) - ret = ret if isinstance(ret, tuple) else (ret,) - if debug >= 2: print("\toutputs:\n" + "\n".join(f"\t\t{x} - {o!r}" for x,o in zip(node.outputs, ret))) - - self.graph_values.update(dict(zip(node.outputs, ret[:len(node.outputs)], strict=True))) - - if node.num == limit: - Tensor.training = self.old_training - return {name:self.graph_values[name] for name in node.outputs} - Tensor.training = self.old_training - return {name:self.graph_values[name] for name in self.graph_outputs} - -#################### -##### ONNX OPS ##### -#################### -def get_onnx_ops(): - # ***** helper functions ***** - def _axes(axes, noop_with_empty_axes): return axes or ([] if noop_with_empty_axes else None) - - # (padding_top, padding_left, ..., padding_bottom, padding_right, ...) -> (padding_left, padding_right, padding_top, padding_bottom, ...) - def _onnx_pads_to_tiny_pads(pads): return tuple(flatten(reversed(list(zip(pads, pads[len(pads)//2:]))))) - - AUTO_PAD_OPTIONS = Literal["NOTSET", "SAME_UPPER", "SAME_LOWER", "VALID"] - # (padding_height, padding_width) -> (padding_top, padding_left, padding_bottom, padding_right) - def _auto_pad(pads, auto_pad: AUTO_PAD_OPTIONS): - if auto_pad == "SAME_UPPER": return [pads[i]//2 for i in range(len(pads))] + [pads[i]-pads[i]//2 for i in range(len(pads))] - return [pads[i]-pads[i]//2 for i in range(len(pads))] + [pads[i]//2 for i in range(len(pads))] - - def _resolve_pool_pads(x:Tensor, p_, k_, d_, s_, auto_pad:AUTO_PAD_OPTIONS): - if auto_pad == "VALID": return [0]*(len(k_)*2) - i_, (s_,d_,p_) = x.shape[-len(k_):], (make_tuple(x, len(k_)*2) for x in (s_, d_, p_)) - if auto_pad == "NOTSET": return _onnx_pads_to_tiny_pads(p_ if len(p_)==len(k_)*2 else p_*2) - o_ = [((i - (1 if auto_pad in ("SAME_UPPER", "SAME_LOWER") else k)) // s + 1) for i,k,s in zip(i_, k_, s_)] - return _onnx_pads_to_tiny_pads(_auto_pad([(o-1)*s+k-i for o,i,k,s in zip(o_, i_, k_, s_)], auto_pad)) - - def _clamp_cast(x:Tensor, dtype:DType): return x.clamp(dtypes.min(dtype), dtypes.max(dtype)).cast(dtype) - - def _prepare_quantize(x:Tensor, scale:Tensor, zero_point:Tensor|int, axis=1, block_size=0): - if axis < 0: axis += x.ndim - # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/op_quantize_linear.py#L31 - def reshape(val:Tensor): - if val.numel() == 1: return val - if block_size == 0: return val.reshape([val.shape[0] if dim == axis else 1 for dim in range(x.ndim)]) - return val.repeat_interleave(block_size, axis) - return (reshape(scale), reshape(zero_point) if isinstance(zero_point, Tensor) else zero_point) - - def _op_integer(op, inputs:list[Tensor], zero_points:list[Tensor], **opts): - adjusted_inputs = [inp.int() - zp for inp, zp in zip(inputs, zero_points)] - return op(*adjusted_inputs, **opts) - - def _qlinearop_quantized(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): - # op execution is done in quantized int - out = _op_integer(op, inputs, zero_points, **opts) - assert dtypes.is_int(out.dtype), "quantized op should've done math in int" - out_quantized = (out * prod(scales) / out_scale).round() + out_zero_point - return _clamp_cast(out_quantized, out_zero_point.dtype) - - def _qlinearop_float(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): - # op execution is done in float32 - dequantized_inputs = [(inp.int() - zp) * scale for inp, zp, scale in zip(inputs, zero_points, scales)] - out = op(*dequantized_inputs, **opts) - assert dtypes.is_float(out.dtype), "op should've done math in float" - out_quantized = (out / out_scale).round() + out_zero_point - return _clamp_cast(out_quantized, out_zero_point.dtype) - - def _onnx_training(input_group_size): - def __decorator(func): - def ___wrapper(R:Tensor, T:int, *inputs:Tensor, **kwargs): - R = R.detach() - groups = len(inputs) // input_group_size - ret = [func(R, T, *inps, **kwargs) for inps in (inputs[i::groups] for i in range(groups))] - return tuple(flatten(zip(*ret))) - return ___wrapper - return __decorator - - # ***** Property/Graph Ops ***** - def Identity(x:Tensor): return x - def Constant(sparse_value:Tensor|None=None, value:Tensor|None=None, value_float:float|None=None, value_floats:list[float]|None=None, - value_int:int|None=None, value_ints:list[int]|None=None, value_string:str|None=None, value_strings:list[str]|None=None): - if value is not None: return value - if value_float is not None: return Tensor(value_float, dtype=dtypes.float32, requires_grad=False) - if value_floats is not None: return Tensor(list(value_floats), dtype=dtypes.float32, requires_grad=False) - if value_int is not None: return Tensor(value_int, dtype=dtypes.int64, requires_grad=False) - if value_ints is not None: return Tensor(list(value_ints), dtype=dtypes.int64, requires_grad=False) - if value_string is not None or value_strings is not None and sparse_value is not None: - raise NotImplementedError('Constant OP not implemented for value_string, value_strings and sparse_value') - - def Range(start:float|int, limit:float|int, delta:float|int): return Tensor.arange(start=start, stop=limit, step=delta) - - def ImageDecoder(encoded_stream:bytes, pixel_format="RGB"): - try: import PIL.Image - except ImportError as e: raise ImportError("Pillow must be installed for the ImageDecoder operator") from e - img = PIL.Image.open(io.BytesIO(encoded_stream)) - if pixel_format == "BGR": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3).flip(-1) - if pixel_format == "RGB": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3) - if pixel_format == "Grayscale": return Tensor(img.convert("L").tobytes(), dtype=dtypes.uint8).reshape(*img.size, 1) - raise ValueError(f"pixel_format={pixel_format!r} is not supported.") - - def EyeLike(x:Tensor, dtype:int|None=None, k:int=0): - ret = Tensor.eye(cast(int, min(x.shape)), dtype=dtype_parse(dtype) if dtype is not None else x.dtype) - return ret if x.size(0) == x.size(1) else ret.pad(tuple(None if d == ret.size(0) else (k, d-ret.shape[0]-k) for d in x.shape)) - - def OptionalHasElement(x:Tensor|None=None): return Tensor(x is not None and x.numel() > 0) - def OptionalGetElement(x:Tensor|None=None): return x if x is not None else Tensor([]) - def ConstantOfShape(shape:list[int], value:Tensor|None=None): - if value is None: value = Tensor(0, dtype=dtypes.float32) - if shape == [0]: return Tensor([], dtype=value.dtype) - return value.expand(shape) - - def Size(data:Tensor): return data.numel() - def Shape(data:Tensor, end:int|None=None, start:int=0): return Tensor(data.shape[start:end], dtype=dtypes.int64) - - # ***** Unary Ops (math) ***** - def Not(x:Tensor): return x.logical_not() - def Clip(x: Tensor, min:Tensor|None=None, max:Tensor|None=None): return x if min is None and max is None else x.clip(min, max) - def IsInf(x:Tensor, detect_negative:int=1, detect_positive:int=1): return x.isinf(bool(detect_positive), bool(detect_negative)) - - # ***** Unary Ops (activation) ***** - def Softmax_1(x:Tensor, axis:int=1): return x.softmax(axis) - def Softmax_13(x:Tensor, axis:int=-1): return x.softmax(axis) - Softmax = {1:Softmax_1, 13:Softmax_13} - def HardSigmoid(x:Tensor, alpha:float=0.2, beta:float=0.5): return (alpha*x + beta).clip(0, 1) - def Gelu(x:Tensor, approximate:str|None=None): return x.gelu() if approximate == "tanh" else 0.5 * x * (1 + (x/math.sqrt(2)).erf()) - def BiasGelu(x: Tensor, bias: Tensor, approximate: str | None = None) -> Tensor: return Gelu(x + bias, approximate) - def FastGelu(x:Tensor, bias:Tensor|None=None): return (x + bias).gelu() if bias is not None else x.gelu() # this is tanh approximated - def PRelu(X:Tensor, slope:Tensor): return (X > 0).where(X, X * slope) - def LeakyRelu(X:Tensor, alpha:float=0.01): return X.leaky_relu(alpha) - def ThresholdedRelu(X:Tensor, alpha:float=1.0): return (X > alpha).where(X, 0) - def LogSoftmax(x: Tensor, axis:int=-1): return x.log_softmax(axis) - def Binarizer(x:Tensor, threshold:float=0.0): return (x > threshold).float() - - # ***** Unary Ops (broadcasted) ***** - def Add(x:Tensor,y:Tensor, broadcast=None, axis=None): return x + y if x.dtype == dtypes.float or isinstance(x.dtype, ImageDType) else (x + y).cast(x.dtype) - def Sub(x:Tensor|int,y:Tensor): return x - y # some test has input as int - def Div(x:Tensor,y:Tensor): return x.div(y, rounding_mode='trunc' if dtypes.is_int(x.dtype) else None) - def Less(x:Tensor,y:Tensor): return x < y - def LessOrEqual(x:Tensor,y:Tensor): return x <= y - def Greater(x:Tensor,y:Tensor): return x > y - def GreaterOrEqual(x:Tensor,y:Tensor): return x >= y - def Equal(x:Tensor,y:Tensor): return x == y - def And(x:Tensor,y:Tensor): return (x==y).where(x, False) - def Or(x:Tensor,y:Tensor): return (x==y).where(x, True) - def Xor(x:Tensor,y:Tensor): return x.bool().bitwise_xor(y.bool()) - def BitwiseAnd(x:Tensor,y:Tensor): return x & y - def BitwiseOr(x:Tensor,y:Tensor): return x | y - def BitwiseXor(x:Tensor,y:Tensor): return x ^ y - def BitwiseNot(x:Tensor): return ~x - def Mod(x:Tensor,y:Tensor,fmod=0): - if fmod: return x - x.div(y, rounding_mode="trunc") * y - return x % y - - # ***** Casting Ops ***** - # TODO: saturate - def Cast(x:Tensor, to:int, saturate:int=1): return x.cast(dtype_parse(to)) - def CastLike(x:Tensor, target_type:Tensor, saturate:int=1): return x.cast(target_type.dtype) - - # ***** Reduce Ops ***** - def Max(*data_0:Tensor): return functools.reduce(Tensor.maximum, data_0) - def Min(*data_0:Tensor): return functools.reduce(Tensor.minimum, data_0) - def Sum(*data_0:Tensor): return functools.reduce(Tensor.add, data_0) - def Mean(*data_0:Tensor): return Sum(*data_0) / len(data_0) - def ReduceMax(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.max(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceMin(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.min(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.sum(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceMean(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.mean(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceSumSquare(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.square(), axes, keepdims, noop_with_empty_axes) - def ReduceProd(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.prod(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceL1(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.abs(), axes, keepdims, noop_with_empty_axes) - def ReduceL2(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSumSquare(data, axes, keepdims, noop_with_empty_axes).sqrt() - def ReduceLogSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data, axes, keepdims, noop_with_empty_axes).log() - def ReduceLogSumExp(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.exp(), axes, keepdims, noop_with_empty_axes).log() - def ArgMax(x:Tensor, axis:int=0, keepdims:int=1, select_last_index:int=0): - if select_last_index: return ((x.shape[axis]-1) - x.flip(axis).argmax(axis, keepdim=keepdims)).cast(dtypes.int64) - return x.argmax(axis, keepdim=keepdims).cast(dtypes.int64) - def ArgMin(x, axis:int=0, keepdims:int=1, select_last_index:int=0): - return ArgMax(-x, axis=axis, keepdims=keepdims, select_last_index=select_last_index) - - # ***** Movement Ops ***** - def Reshape(data:Tensor, shape:list[int], allowzero:int=0): - return data.reshape([x if x != 0 else (0 if allowzero else data.shape[i]) for i,x in enumerate(shape)]) - def Flatten(x:Tensor, axis:int=1): return x.reshape(prod(x.shape[0:axis]), -1) - def Expand(x:Tensor, shape:list[int]): return x.expand(_broadcast_shape(x.shape, tuple(shape))) - def Shrink(x:Tensor, bias:float=0.0, lambd:float=0.5): return (x < -lambd)*(x+bias) + (x > lambd)*(x-bias) - def Transpose(x:Tensor, perm:list[int]|None=None): return x.permute(order=perm or list(range(x.ndim)[::-1])) - - def Squeeze(data:Tensor, axes:list[int]|None=None): - return data.squeeze() if axes is None else functools.reduce(lambda d, dim: d.squeeze(dim), sorted(axes, reverse=True), data) - def Unsqueeze(data:Tensor, axes:list[int]): return functools.reduce(lambda d, dim: d.unsqueeze(dim), sorted(axes), data) - - def Tile(x:Tensor, repeats:list[int]): return x.repeat(repeats) - def Concat(*xs:Tensor, axis:int): return Tensor.cat(*xs, dim=axis) - def Slice(data:Tensor, starts:list[int], ends:list[int], axes:list[int]|None=None, steps:list[int]|None=None): - axes = axes or list(range(data.ndim)) - steps = steps or [1]*data.ndim - slices = [slice(0,x,1) for x in data.shape] - for i, axis in enumerate(axes): slices[axis] = slice(starts[i], ends[i], steps[i]) - return data[tuple(slices)] - - def Split(data:Tensor, split:list[int]|None=None, num_outputs:int=0, axis:int=0): - sz = data.shape[axis] - if split is None: split = [sz // num_outputs + (1 if i < sz % num_outputs else 0) for i in range(num_outputs)] - return data.split(split, axis) - - def Pad(x:Tensor, pads:list[int], constant_value:ConstType|None=None, axes:list[int]|None=None, - mode:Literal["constant", "reflect", "edge", "wrap"]="constant", value=0): - value = constant_value or value - axes = axes or list(range(x.ndim)) - real_pads = [0] * (x.ndim*2) - for i,axis in enumerate(axes): real_pads[axis%x.ndim], real_pads[axis%x.ndim+x.ndim] = pads[i], pads[i+len(axes)] - return x.pad(padding=_onnx_pads_to_tiny_pads(real_pads), mode={"edge":"replicate", "wrap":"circular"}.get(mode, mode), value=value) - - def CenterCropPad(t:Tensor, shape:list[int], axes:list[int]|None=None): - shrink_arg:list[None|tuple[int,int]] = [None] * t.ndim - pad_arg:list[None|tuple[int,int]] = [None] * t.ndim - for s, x in zip(shape, axes or range(t.ndim)): - tx = t.shape[x] - if s < tx: shrink_arg[x] = (tx//2 - (s+1)//2, tx//2 + s//2) - elif s > tx: pad_arg[x] = ((s-tx)//2, (s-tx+1)//2) - return t.shrink(tuple(shrink_arg)).pad(tuple(pad_arg)) - - # ***** Processing Ops ***** - def AveragePool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, count_include_pad:int=0, - dilations:list[int]|int=1, pads:list[int]|int=0, strides:list[int]|int=1): - return X.avg_pool2d(kernel_shape, strides, dilations, _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad), - ceil_mode=ceil_mode, count_include_pad=count_include_pad) - - def MaxPool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, dilations:list[int]|int=1, pads:list[int]|int=0, - storage_order:int=0, strides:list[int]|int=1): - pads = _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad) - ret, idx = X.max_pool2d(kernel_shape, strides, dilations, pads, ceil_mode=ceil_mode, return_indices=True) - return ret, idx.transpose(-2, -1).cast(dtypes.int64) if storage_order else idx.cast(dtypes.int64) - - def Conv(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, - kernel_shape:list[int]|None=None, pads:list[int]|int=0, strides:list[int]|int=1): - return X.conv2d(W, B, stride=strides, groups=group, dilation=dilations, - padding=_resolve_pool_pads(X, pads, kernel_shape or W.shape[2:], dilations, strides, auto_pad)) - - def ConvTranspose(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, - kernel_shape:list[int]|None=None, pads:list[int]|None=None, output_shape:list[int]|None=None, output_padding:list[int]|int=0, - strides:list[int]|int=1): - input_shape, kernel_shape = X.shape[2:], (kernel_shape or W.shape[2:]) - strides, dilations, output_padding = (make_tuple(x, len(input_shape)) for x in (strides, dilations, output_padding)) - if output_shape is not None: # we pad according to output_shape - pads = _auto_pad([s*(i-1) + op + ((k-1)*d+1) - os for s,i,op,k,d,os in - zip(strides, input_shape, output_padding, kernel_shape, dilations, output_shape)], auto_pad) - if pads is None: # we generate pads - output_shape = output_shape or [X.shape[i+2] * strides[i] for i in range(len(strides))] - pads = [strides[i]*(input_shape[i]-1) + output_padding[i] + ((kernel_shape[i]-1)*dilations[i]+1)-output_shape[i] for i in range(len(input_shape))] - pads = _auto_pad(pads, auto_pad) if auto_pad != "NOTSET" else [0] * len(input_shape) * 2 - pads = _onnx_pads_to_tiny_pads(pads) - return X.conv_transpose2d(W, B, stride=strides, groups=group, dilation=dilations, padding=pads, output_padding=output_padding) - - def MaxUnpool(xT: Tensor, xI: Tensor, outshape: list[int]|None=None, kernel_shape:list[int]=None, pads:list[int]|int=0, strides:list[int]|int=1): - return Tensor.max_unpool2d(xT, xI, kernel_shape, strides, 1, pads, outshape if outshape is None else tuple(outshape)) - - def GlobalAveragePool(X:Tensor): return X.mean(axis=tuple(range(2, X.ndim)), keepdim=True) - def GlobalMaxPool(X:Tensor): return X.max(axis=tuple(range(2, X.ndim)), keepdim=True) - - def Gemm(A:Tensor, B:Tensor, C:Tensor|None=None, alpha:float=1.0, beta:float=1.0, transA:int=0, transB:int=0, broadcast=0): - ret = alpha * (A.transpose(transA) @ B.transpose(transB)) - if C is not None: ret = ret + beta * (C if broadcast == 0 else C.reshape([-1 if i < len(C.shape) else 1 for i in range(ret.ndim)][::-1])) - return ret - - def Einsum(*Inputs:list[Tensor], equation:str): return Tensor.einsum(equation, *Inputs) - - def CumSum(X:Tensor, axis:int|list, exclusive:int=0, reverse:int=0): - axis = X._resolve_dim(axis[0] if isinstance(axis, list) else axis) - if reverse: X = X.flip(axis) - if exclusive: X = X.pad(tuple((1,0) if i == axis else None for i in range(X.ndim)))\ - .shrink(tuple((0,X.shape[axis]) if i == axis else None for i in range(X.ndim))) - return X.cumsum(axis).flip(axis) if reverse else X.cumsum(axis) - - def Trilu(x:Tensor, k:int=0, upper:int=1): return x.triu(k) if upper else x.tril(k) - - def Resize(X:Tensor, roi:list[float]|None=None, scales:list[float]|None=None, sizes:list[int]|None=None, antialias:int=0, - axes:list[int]|None=None, coordinate_transformation_mode:str='half_pixel', cubic_coeff_a:float=-0.75, exclude_outside:int=0, - extrapolation_value:float=0.0, keep_aspect_ratio_policy:str='stretch', mode:str='nearest', nearest_mode:str='round_prefer_floor'): - def _apply_nearest_mode(index: Tensor, input_dim, mode: str): - if mode == "round_prefer_floor": index = (index - 0.5).ceil() - elif mode == "round_prefer_ceil": index = (index + 0.5).floor() - elif mode in ["floor", "ceil"]: index = getattr(index, mode)() - else: raise ValueError(f"invalid {nearest_mode=}") - return index.cast(dtypes.int32).clip(0, input_dim-1) - def _apply_transformation(index: Tensor, input_dim, scale_dim, mode): - # TODO: needs more testing, not confident in this - # NOTE: their reference implementation differ from the implementation in their reference docs - # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/op_resize.py - # https://github.com/onnx/onnx/blob/main/docs/Operators.md#Resize - output_dim = scale_dim * input_dim - if mode == "half_pixel": index = (index + 0.5) / scale_dim - 0.5 - elif mode == "align_corners": index = index * (input_dim - 1) / (output_dim - 1) if output_dim != 1 else Tensor([0]) - elif mode == "asymmetric": index = index / scale_dim - elif mode == "pytorch_half_pixel": index = (index + 0.5) / scale_dim - 0.5 if output_dim != 1 else Tensor([-0.5]) - elif mode == "half_pixel_symmetric": index = input_dim / 2 * (1 - int(output_dim) / output_dim) + (index + 0.5) / scale_dim - 0.5 - else: raise NotImplementedError(f"invalid {coordinate_transformation_mode=}") - return index.clip(0, input_dim-1) - - scales, sizes = (None if scales is None else scales[2-(X.ndim-len(scales)):]), (None if sizes is None else sizes[2-(X.ndim-len(sizes)):]) - # we pre permute the axes and permute back after resize - axes, input_shape, = (axes or list(range(X.ndim))), cast(tuple[int, ...], X.shape[2:]), - perm = [a for a in range(len(X.shape)) if a not in axes] + list(axes) - X = X.permute(*perm) - - if sizes is not None: - if keep_aspect_ratio_policy in ["not_larger", "not_smaller"]: - scale_fxn = min if keep_aspect_ratio_policy == "not_larger" else max - scales = [scale_fxn([sizes[i] / input_shape[i] for i in range(len(input_shape)) if i+2 in axes])] * 2 - sizes = [int((scales[0] * input_shape[i]) + 0.5) if i+2 in axes else input_shape[i] for i in range(X.ndim-2)] - else: - scales = [size / input_shape for size, input_shape in zip(sizes, input_shape)] - else: - sizes = [int(sc*sh) for sc, sh in zip(scales, input_shape)] - - # NOTE: this transformation makes it so that we can't just call Tensor.interpolate - # in Tensor.interpolate, we use indexes without any transformation - indexes = [] - for shape, size, scale in zip(input_shape, sizes, scales): - indexes.append(_apply_transformation(Tensor.arange(size), shape, scale, coordinate_transformation_mode)) - - if mode == "nearest": - indexes = [_apply_nearest_mode(index, shape, nearest_mode) for (index, shape) in zip(indexes, input_shape)] - X = X[(..., *Tensor.meshgrid(*indexes))] - if mode == "linear": - expand = list(X.shape) - for i in range(-len(sizes), 0): - reshape, index = [1] * X.ndim, indexes[i] - reshape[i] = expand[i] = sizes[i] - low, high, perc = [y.reshape(reshape).expand(expand) for y in (index.floor().int(), index.ceil().int(), index - index.floor())] - X = X.gather(i, low).lerp(X.gather(i, high), perc) - if mode == "cubic": raise NotImplementedError("cubic interpolation is not implemented") - return X.permute(*argsort(perm)) if perm else X - def Upsample(X, scales, mode): return Resize(X=X, scales=scales, mode=mode) # deprecated - - def TopK(X:Tensor, K:int|list[int], axis:int=-1, largest:int=1, sorted:int=1): - val, idx = X.topk(K if isinstance(K, int) else K[0], axis, largest, sorted) - return val, idx.cast(dtypes.int64) - - # ***** Neural Network Ops ***** - def BatchNormalization(X:Tensor, scale:Tensor, B:Tensor, input_mean:Tensor, input_var:Tensor, epsilon:float=1e-05, momentum:float=0.9, - training_mode:int=0, spatial=1, is_test=0): - if training_mode: - x_detached = X.detach() - current_mean = x_detached.mean(axis=(0,2,3)) - y = (x_detached - current_mean.reshape(shape=[1, -1, 1, 1])) - current_var = (y*y).mean(axis=(0,2,3)) - current_invstd = current_var.add(epsilon).rsqrt() - - running_mean = input_mean * momentum + current_mean * (1 - momentum) - running_var = input_var * momentum + current_var * (1 - momentum) - - return X.batchnorm(scale, B, current_mean, current_invstd), running_mean, running_var - return X.batchnorm(scale, B, input_mean, (input_var + epsilon).rsqrt()) - def GroupNormalization(x:Tensor, scale:Tensor, bias:Tensor, num_groups:int, epsilon:float=1e-05): - x = x.reshape(x.shape[0], num_groups, -1).layernorm(eps=epsilon).reshape(x.shape) - return x * scale.reshape(1, -1, *[1] * (x.ndim-2)) + bias.reshape(1, -1, *[1] * (x.ndim-2)) - def InstanceNormalization(x:Tensor, scale:Tensor, bias:Tensor, epsilon:float=1e-05): - return GroupNormalization(x, scale, bias, num_groups=x.shape[1], epsilon=epsilon) - def LayerNormalization(x:Tensor, scale:Tensor, bias:Tensor, axis:int=-1, epsilon:float=1e-05, stash_type:int=1): - assert stash_type == 1, "only float32 is supported" - axes = tuple(i for i in range(axis if axis >= 0 else x.ndim + axis, x.ndim)) - mean = x.mean(axis=axes, keepdim=True) - return x.layernorm(axes, epsilon).mul(scale).add(bias), mean, (x.sub(mean)).square().mean(axis=axes, keepdim=True).add(epsilon).rsqrt() - def SkipLayerNormalization(x:Tensor, skip:Tensor, gamma:Tensor, beta:Tensor|None=None, bias:Tensor|None=None, epsilon:float=1e-12): - x = x + skip - if bias is not None: x = x + bias - ret = x.layernorm(eps=epsilon) * gamma - if beta is not None: ret = ret + beta - return ret, None, None, x - def EmbedLayerNormalization(input_ids: Tensor, segment_ids:Tensor, word_embedding:Tensor, position_embedding:Tensor, - segment_embedding:Tensor, gamma=None, beta=None, mask:Tensor|None=None, - position_ids:Tensor|None=None, epsilon=1e-12, mask_index_type=0): - # https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#com.microsoft.EmbedLayerNormalization - assert (segment_ids is None) is (segment_embedding is None) - assert mask is None and not mask_index_type, "functionality not supported yet" # TODO - input_shape = input_ids.shape - seq_length = input_shape[1] - compute_seg_emb = (segment_embedding is not None and segment_ids is not None) - vocab_size, max_position_embeddings = word_embedding.shape[0], position_embedding.shape[0] - type_vocab_size = (segment_embedding.shape[0] if compute_seg_emb else None) - - def embedding(x:Tensor, vocab_size, weight:Tensor) -> Tensor: - return x.unsqueeze(-1).expand(*x.shape, vocab_size)._one_hot_along_dim(vocab_size) @ weight - - # bert embedding layer - if position_ids is None: position_ids = Tensor.arange(seq_length, requires_grad=False).unsqueeze(0).expand(*input_shape) - wrd_embedding_res = embedding(input_ids, vocab_size, word_embedding) - pos_embedding_res = embedding(position_ids, max_position_embeddings, position_embedding) - seg_embedding_res = embedding(segment_ids, type_vocab_size, segment_embedding) if compute_seg_emb else None - - embedding_sum = wrd_embedding_res + pos_embedding_res - if seg_embedding_res is not None: embedding_sum = embedding_sum + seg_embedding_res - out = embedding_sum.layernorm(eps=epsilon) * gamma + beta - return out, None, embedding_sum - def MeanVarianceNormalization(x:Tensor, axis:list[int]=[0,2,3]): - return (x - x.mean(axis, keepdim=True)) / (x.std(axis, keepdim=True, correction=0) + 1e-9) - - def OneHot(indices:Tensor, depth:float|int|list, values:Tensor, axis:int=-1): - # Scalar or Rank 1 tensor containing exactly one element - depth = int(depth[0] if isinstance(depth, list) else depth) - indices = indices.int() - indices = (indices < 0).where(indices+depth, indices) - return indices.unsqueeze(axis)._one_hot_along_dim(depth, dim=axis).where(values[1], values[0]) - - def DepthToSpace(X:Tensor, blocksize:int, mode:str="DCR"): - return X.rearrange("b (c h1 w1) h w -> b c (h h1) (w w1)" if mode=="CRD" else "b (h1 w1 c) h w -> b c (h h1) (w w1)", h1=blocksize, w1=blocksize) - def SpaceToDepth(X:Tensor, blocksize:int): - return X.rearrange("b c (h h1) (w w1) -> b (h1 w1 c) h w", h1=blocksize, w1=blocksize) - - # Reimplemented here because you need legacy RNG for passing ONNX tests. - def Dropout_7(data:Tensor, ratio:float=0.5, training_mode:bool=False, seed:int|None=None): - if not training_mode: return data, Tensor.ones(data.shape, dtype=dtypes.bool) # if mask is requested as output it will contain all True's. - mask = Tensor(np.random.RandomState(seed).random(cast(tuple[int,...], data.shape)) >= ratio, requires_grad=False, device=data.device) - return data * mask * (1/(1.0 - ratio)), mask - # 6 with 'is_test' needed for https://github.com/MTlab/onnx2caffe/raw/refs/heads/master/model/MobileNetV2.onnx - def Dropout_6(data:Tensor, ratio:float=0.5, is_test=0): return Dropout_7(data, ratio, training_mode=not is_test) - Dropout = {6:Dropout_6, 7:Dropout_7} - - def LRN(x:Tensor, size:int, alpha:float=1e-4, beta:float=0.75, bias:float=1.0): - pooled_x = (x**2).rearrange('b c h w -> b 1 c (h w)').pad((0,0,(size-1)//2, size//2)).avg_pool2d((size, 1), 1) - return x / (pooled_x.reshape(x.shape) * alpha + bias).pow(beta) - - def NegativeLogLikelihoodLoss(x:Tensor, target:Tensor, weight:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): - return x.nll_loss(target, weight, ignore_index, reduction) - def SoftmaxCrossEntropyLoss(scores:Tensor, labels:Tensor, weights:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): - log_probs = scores.log_softmax(1) - return log_probs.nll_loss(labels, weights, ignore_index, reduction), log_probs - - def AffineGrid(theta:Tensor, size:list[int], align_corners:int=0): - N, _, *spatial_dims = size - def generate_grid(steps): - return Tensor.linspace(-1, 1, steps, device=theta.device) if align_corners else Tensor.linspace(-1+1/steps, 1-1/steps, steps, device=theta.device) - grids = Tensor.meshgrid(*(generate_grid(d) for d in spatial_dims)) - base_grid = Tensor.stack(*reversed(grids), Tensor.ones_like(grids[0], device=theta.device), dim=-1) - base_grid = base_grid.reshape(1, prod(spatial_dims), len(grids)+1).expand(N, -1, -1) - return (base_grid @ theta.transpose(1, 2)).reshape(N, *spatial_dims, -1) - - def Attention(x:Tensor, weights:Tensor, bias:Tensor|None=None, mask_index:Tensor|None=None, past:Tensor|None=None, attention_bias:Tensor|None=None, - past_sequence_length:Tensor|None=None, do_rotary:int=0, mask_filter_value:float=-10000.0, num_heads:int|None=None, - past_present_share_buffer:int|None=None, qkv_hidden_sizes:list[int]|None=None, rotary_embedding_dim:int|None=None, - scale:float|None=None, unidirectional:int=0): - assert not do_rotary and not attention_bias, "TODO" - if qkv_hidden_sizes is None: qkv_hidden_sizes = [weights.shape[1] // 3] * 3 - qkv = x.linear(weights, bias) - q, k, v = qkv.split(qkv_hidden_sizes, dim=2) - - batch_size, seq_len, _ = x.shape - q_head_size, k_head_size, v_head_size = (sz // num_heads for sz in qkv_hidden_sizes) - q, k, v = (x.reshape(batch_size, seq_len, num_heads, hsz).transpose(1, 2) for x, hsz in zip((q, k, v), (q_head_size, k_head_size, v_head_size))) - - present = None - if past is not None: - k, v = past[0].cat(k, dim=2), past[1].cat(v, dim=2) - present = k.stack(v) - - if scale is None: scale = 1.0 / math.sqrt(q_head_size) - attn_scores = q @ k.transpose(-1, -2) * scale - - if mask_index is not None: - assert 4 >= mask_index.ndim >= 1, f"{mask_index.ndim=}" - if mask_index.ndim != 1: mask = mask_index.bool() - else: - if mask_index.shape[0] == batch_size: - mask = Tensor.arange(attn_scores.shape[-1], requires_grad=False, device=mask_index.device).unsqueeze(0) < mask_index.unsqueeze(1) - elif mask_index.shape[0] == 2*batch_size: - end_positions = mask_index[:batch_size] - start_positions = mask_index[batch_size:] - arange = Tensor.arange(seq_len).unsqueeze(0) - mask = (arange < end_positions.unsqueeze(1)) & (arange >= start_positions.unsqueeze(1)) - else: raise NotImplementedError("mask_index with shape (3 * batch_size + 2) is not implemented") - while mask.ndim < 4: mask = mask.unsqueeze(1) - attn_scores = mask.where(attn_scores, mask_filter_value) - - if unidirectional: - causal_mask = Tensor.ones((seq_len, seq_len), dtype=dtypes.bool).tril() - attn_scores = causal_mask.where(attn_scores, mask_filter_value) - - output = attn_scores.softmax(-1) @ v - output = output.transpose(1, 2).reshape(batch_size, seq_len, -1) - return output, present - - # ***** Indexing Ops ***** - def ArrayFeatureExtractor(x:Tensor, indices:Tensor): return x[..., indices] - - def Gather(x:Tensor, indices:Tensor, axis:int=0): - if indices.numel() < 9: # NOTE lessor kernels for smaller indices but kernel number increases depending on size of indices - x_sh = list(x.shape) - ret_shape = x_sh[:axis] + list(indices.shape) + x_sh[axis+1:] - if indices.ndim > 1: indices = indices.flatten() - indices = [_cached_to_python_const(indices)] if indices.shape == () else _cached_to_python_const(indices) - indices = [x_sh[axis]+x if x<0 else x for x in indices] - args = [[(0,x) if j != axis else (i,i+1) for j, x in enumerate(x_sh)] for i in indices] # type: ignore - return x.shrink(arg=tuple(args[0])).cat(*[x.shrink(arg=tuple(arg)) for arg in args[1:]], dim=axis).reshape(ret_shape) - # NOTE faster gather, fixed number of kernels, but exceeds limited kernels for openpilot - return x[tuple([slice(None) if i != axis else indices for i in range(x.ndim)])] - def Scatter(*args, **kwargs): return ScatterElements(*args, **kwargs) # deprecated - - def GatherND(x:Tensor, indices:Tensor, batch_dims:int=0): - if batch_dims == 0: return x[tuple(i.squeeze(-1) for i in indices.split(1, -1))] - x_shape, i_shape = x.shape, indices.shape - b = math.prod(x.shape[dim] for dim in range(batch_dims)) - # NOTE: each batched dim of both input and indices are equal - x = x.reshape(b, *x.shape[batch_dims:]) - indices = indices.reshape(b, *indices.shape[batch_dims:]) - b_idx = Tensor.arange(b, device=x.device).reshape(b, *(1,)*(indices.ndim - 2)).expand(*indices.shape[:-1]) - ret = x[(b_idx,) + tuple(i.squeeze(-1) for i in indices.split(1, -1))] - return ret.reshape(*x_shape[:batch_dims], *i_shape[batch_dims:-1], *ret.shape[indices.ndim-1:]) - def ScatterND(x:Tensor, indices:Tensor, updates:Tensor, reduction:Literal["none", "add", "mul"]='none'): - assert updates.shape == indices.shape[:-1] + x.shape[cast(int, indices.shape[-1]):] - x = x.contiguous() - for index, u in zip(indices.split(1, 0), updates.split(1, 0)): - i = tuple(idx.squeeze(-1) for idx in index.squeeze(0).split(1, -1)) - u = u.squeeze(0) - if reduction == "none": x[i] = u - elif reduction == "add": x[i] += u - elif reduction == "mul": x[i] *= u - else: raise NotImplementedError("reduction doesn't support max or min") - return x - - def ScatterElements(x: Tensor, indices: Tensor, updates: Tensor, axis=0, reduction:Literal["none", "add", "mul", "min", "max"]="none"): - indices = (indices < 0).where(x.shape[axis], 0) + indices - if reduction == "none": return x.scatter(axis, indices, updates) - return x.scatter_reduce(axis, indices, updates, {"add": "sum", "mul": "prod", "min": "amin", "max": "amax"}.get(reduction)) - def GatherElements(x:Tensor, indices:Tensor, axis:int): - indices = (indices < 0).where(x.shape[axis], 0) + indices - return x.gather(axis, indices) - - def Compress(inp:Tensor, condition:list[bool], axis:int|None=None): - if axis is None: - inp = inp.flatten() - axis = 0 - if axis < 0: axis += inp.ndim - con = Tensor([i for i,cond in enumerate(condition) if cond]) # compress in python - return inp[tuple(con if i == axis else slice(None) for i in range(inp.ndim))] - - # ***** Quantization Ops ***** - def QuantizeLinear(x:Tensor, y_scale:Tensor, y_zero_point:Tensor|int=0, axis:int=1, block_size:int=0, output_dtype:int=0, saturate=1): - out_dtype = y_zero_point.dtype if isinstance(y_zero_point, Tensor) else dtype_parse(output_dtype) if output_dtype else dtypes.uint8 - y_scale, y_zero_point = _prepare_quantize(x, y_scale, y_zero_point, axis, block_size) - if out_dtype == dtypes.uchar: - # this appears to work in practice, at least for uchar out_dtype. it folds with the quantize stuff - ret = _clamp_cast((x / y_scale + 0.4999999 + y_zero_point).int(), out_dtype) - else: - ret = _clamp_cast(((x / y_scale).round() + y_zero_point), out_dtype) - return ret.contiguous() - - def DynamicQuantizeLinear(x: Tensor): - # only support uint8 - qmin, qmax = dtypes.min(dtypes.uint8), dtypes.max(dtypes.uint8) - scale = (x.max().maximum(0) + ((-x).max()).maximum(0)) / (qmax - qmin) - zero_point = _clamp_cast((qmin - x.min() / scale).round(), dtypes.uint8) - y = _clamp_cast((x / scale).round() + zero_point, dtypes.uint8) - return y, scale, zero_point - - def DequantizeLinear(x:Tensor, x_scale:Tensor, x_zero_point:Tensor|int=0, axis:int=1, block_size:int=0): - x_scale, x_zero_point = _prepare_quantize(x, x_scale, x_zero_point, axis, block_size) - return ((x.int() - x_zero_point) * x_scale).cast(x_scale.dtype) - - def QLinearConv(x:Tensor, x_scale:Tensor, x_zero_point:Tensor|int, w:Tensor, w_scale:Tensor, w_zero_point:Tensor|int, y_scale:Tensor, - y_zero_point: Tensor|int, B:Tensor|None=None, **opts): - return _qlinearop_quantized(Conv, [x,w], [x_zero_point,w_zero_point], [x_scale,w_scale], y_scale, y_zero_point, **{"B":B, **opts}) - - def QLinearMatMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor|int, b:Tensor, b_scale:Tensor, b_zero_point:Tensor|int, y_scale:Tensor, - y_zero_point:Tensor|int) -> Tensor: - return _qlinearop_quantized(Tensor.matmul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], y_scale, y_zero_point) - - def QLinearAdd(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): - return _qlinearop_float(Tensor.add, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) - - def QLinearMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): - return _qlinearop_quantized(Tensor.mul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) - - def QLinearGlobalAveragePool(X:Tensor, x_scale:Tensor, x_zero_point:Tensor, y_scale:Tensor, y_zero_point:Tensor, channels_last:int): - assert channels_last == 0, "TODO NHWC" - return _qlinearop_float(GlobalAveragePool, [X], [x_zero_point], [x_scale], y_scale, y_zero_point) - - def ConvInteger(x: Tensor, w: Tensor, x_zero_point: Tensor | int = 0, w_zero_point: Tensor | int = 0, B: Tensor | None = None, **opts) -> Tensor: - return _op_integer(Conv, [x,w], [x_zero_point,w_zero_point], **{"B":B, **opts}) - - def MatMulInteger(A: Tensor, B: Tensor, a_zero_point: Tensor | int = 0, b_zero_point: Tensor | int = 0) -> Tensor: - return _op_integer(Tensor.matmul, [A,B], [a_zero_point,b_zero_point]) - - # ***** Training Ops ***** - # NOTE: onnx training ops actually don't need the state for optim, all the ops work in a functional way, but we still can reuse optim.py code - @_onnx_training(3) - def Adagrad(R:Tensor, T:int, *inputs:Tensor, decay_factor:float=0.0, epsilon:float=0.0, norm_coefficient:float=0.0): - X, G, H = (i.detach() for i in inputs) - grad = norm_coefficient * X + G - H.assign(H + grad.square()) - up = grad / (H.sqrt() + epsilon) - r = R / (1 + T * decay_factor) - X.assign(X.detach() - r * up) - return [X, H] - - @_onnx_training(4) - def Adam(R:Tensor, T:int, *inputs:Tensor, alpha:float=0.9, beta:float=0.999, epsilon:float=0.0, norm_coefficient:float=0.0, - norm_coefficient_post:float=0.0): - from tinygrad.nn.optim import Adam as TinyAdam - X, G, V, H = inputs - G, V, H = G.detach(), V.detach(), H.detach() - X.grad = norm_coefficient * X.detach() + G - opt = TinyAdam([X], b1=alpha, b2=beta, eps=epsilon) - opt.m, opt.v, opt.lr = [V], [H], R - # need no-op for m_hat and v_hat if T == 0 - if T == 0: opt.b1_t, opt.b2_t = opt.b1_t.zeros_like(), opt.b2_t.zeros_like() - else: - # `T-1` since it's applied again at the start of `_step` - opt.b1_t = Tensor([alpha**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) - opt.b2_t = Tensor([beta**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) - opt.step() - X = (1 - norm_coefficient_post) * X - return [X, V, H] - - @_onnx_training(3) - def Momentum(R:Tensor, T:int, *inputs:Tensor, alpha:float, beta:float, mode:str, norm_coefficient:float): - X, G, V = (i.detach() for i in inputs) - grad = norm_coefficient * X + G - # NOTE: this beta_adjusted term makes it so we can't use SGD for nesterov - beta_adjusted = beta if T > 0 else 1 - V.assign(alpha * V + grad * beta_adjusted) - X.assign(X - R * (V if mode == "standard" else (grad + alpha * V))) - return [X, V] - - def Gradient(*inputs:Tensor, y:str, intermediate_tensors:dict[str, Tensor], **_): - intermediate_tensors[y].backward() - return tuple([t.grad for t in inputs]) - - return { - # Tensor ops - **{op: getattr(Tensor, op.lower()) for op in ("Neg", "Reciprocal", "Pow", "Sqrt", "Sign", "Abs", "Exp", "Log", "Mish", "Sin", "Cos", "Tan", - "Asin", "Acos", "Atan", "Relu", "Sigmoid", "MatMul", "Floor", "Ceil", "IsNaN", "Softplus", "HardSwish", "Where", "Mul", "Sinh", "Cosh", - "Tanh", "Softsign", "Asinh", "Acosh", "Atanh", "Elu", "Celu", "Selu", "Round", "Erf")}, - # Implemented ops - **{name:obj for name,obj in locals().items() if isinstance(obj, types.FunctionType) and not name.startswith("_") and name[0].isupper()}, - # Version ops - **{name:obj for name,obj in locals().items() if isinstance(obj, dict)}, - } - -onnx_ops = get_onnx_ops() diff --git a/tinygrad/extra/onnx_helpers.py b/tinygrad/extra/onnx_helpers.py deleted file mode 100644 index d2a8bb96..00000000 --- a/tinygrad/extra/onnx_helpers.py +++ /dev/null @@ -1,65 +0,0 @@ -from tinygrad import Tensor -from tinygrad.tensor import _to_np_dtype -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from extra.onnx import OnnxValue -import numpy as np -import onnxruntime as ort - -def get_example_inputs(graph_inputs:dict[str, OnnxValue], config={}): - def _get_shape(onnx_shape: tuple[str|int]): - shape = [] - for onnx_dim in onnx_shape: - match onnx_dim: - case int(): shape.append(onnx_dim) - case "width" | "height": - size = config.get("size", {}) - shape.append(size) if isinstance(size, int) else shape.append(size.get(onnx_dim, 224)) - case "sequence" | "sequence_length" | "decoder_sequence_length": shape.append(64) - case "encoder_sequence_length": shape.append(config.get("nb_max_frames", 64)) - case "past_decoder_sequence_length" | "encoder_sequence_length_out": shape.append(64) - case "encoder_sequence_length / 2": shape.append(32) - case "batch_size": shape.append(1) - case "num_channels": shape.append(config.get("in_channels", 3)) - case "num_channels_latent": shape.append(config.get("latent_channels", 4)) - case "height_latent" | "width_latent": shape.append(config.get("sample_size", 1024) // 8) - case "feature_size": shape.append(config.get("num_mel_bins", 128)) - case _: shape.append(1) - return shape - def _get_value(name, shape, dtype): - match name: - case "input_ids": - vocab_size = config.get("text_config", {}).get("vocab_size") or config.get("vocab_size", 32) - val = np.random.randint(0, vocab_size-1, shape) - case "attention_mask": val = np.random.randint(0, 2, size=shape) - case "token_type_ids": val = np.random.randint(0, config.get("type_vocab_size", 2), shape) - case "image_tensor": val = np.random.randint(0, 256, shape) - case "task_id": return Tensor(0, dtype=dtype) - case _: val = np.random.uniform(size=shape) * 8 - return Tensor(val.astype(_to_np_dtype(dtype))).realize() - - ret: dict[str, Tensor] = {} - for name, spec in graph_inputs.items(): - assert not spec.is_optional and not spec.is_sequence, "only allow tensor input for now" - shape = _get_shape(spec.shape) - value = _get_value(name, shape, spec.dtype) - ret.update({name:value}) - return ret - -def validate(onnx_file, inputs, rtol=1e-5, atol=1e-5): - run_onnx = OnnxRunner(onnx_load(onnx_file)) - - ort_options = ort.SessionOptions() - ort_options.log_severity_level = 3 - ort_sess = ort.InferenceSession(onnx_file, ort_options, ["CPUExecutionProvider"]) - np_inputs = {k:v.numpy() if isinstance(v, Tensor) else v for k,v in inputs.items()} - out_names = list(run_onnx.graph_outputs) - out_values = ort_sess.run(out_names, np_inputs) - ort_out = dict(zip(out_names, out_values)) - - tinygrad_out = run_onnx(inputs) - - assert tinygrad_out.keys() == ort_out.keys() - for k in tinygrad_out.keys(): - tiny_v, onnx_v = tinygrad_out[k], ort_out[k] - if tiny_v is None: assert onnx_v is None, f"{k}: {tiny_v=}, {onnx_v=}" - else: np.testing.assert_allclose(tiny_v.numpy(), onnx_v, rtol=rtol, atol=atol, err_msg=f"For tensor '{k}' in {tinygrad_out.keys()}") \ No newline at end of file diff --git a/tinygrad/extra/onnx_parser.py b/tinygrad/extra/onnx_parser.py deleted file mode 100644 index 7cb07950..00000000 --- a/tinygrad/extra/onnx_parser.py +++ /dev/null @@ -1,204 +0,0 @@ -# https://github.com/onnx/onnx/blob/main/onnx/onnx.proto3 - -import os, pathlib, struct -from io import BufferedReader -from typing import Tuple, Union -from types import SimpleNamespace -from tinygrad.nn.state import TensorIO -from tinygrad.tensor import Tensor, dtypes - -# Protobuf Wire Types -WIRETYPE_VARINT = 0; WIRETYPE_FIXED64 = 1; WIRETYPE_LENGTH_DELIMITED = 2; WIRETYPE_START_GROUP = 3; WIRETYPE_END_GROUP = 4; WIRETYPE_FIXED32 = 5 # noqa: E702 - -# TensorProto.DataType -class TensorDataType: - UNDEFINED = 0; FLOAT = 1; UINT8 = 2; INT8 = 3; UINT16 = 4; INT16 = 5; INT32 = 6; INT64 = 7 # noqa: E702 - STRING = 8; BOOL = 9; FLOAT16 = 10; DOUBLE = 11; UINT32 = 12; UINT64 = 13; COMPLEX64 = 14; COMPLEX128 = 15; BFLOAT16 = 16 # noqa: E702 - -# AttributeProto.AttributeType -class AttributeType: - UNDEFINED = 0; FLOAT = 1; INT = 2; STRING = 3; TENSOR = 4; GRAPH = 5; SPARSE_TENSOR = 11; TYPE_PROTO = 13; FLOATS = 6; INTS = 7 # noqa: E702 - STRINGS = 8; TENSORS = 9; GRAPHS = 10; SPARSE_TENSORS = 12; TYPE_PROTOS = 14 # noqa: E702 - -class PBType: FLOAT = 1; INT = 2; STRING = 3; FLOATS = 4; INTS = 5; STRINGS = 6; BYTES = 7; SUB = 8 # noqa: E702 - -PB_INFOS = { - "OperatorSetIdProto": {1: ("domain", PBType.STRING), 2: ("version", PBType.INT)}, - "StringStringEntryProto": {1: ("key", PBType.STRING), 2: ("value", PBType.STRING)}, - "TensorProto": {1: ("dims", PBType.INT, True), 2: ("data_type", PBType.INT), 4: ("float_data", PBType.FLOATS), - 13: ("external_data", PBType.SUB, True, "StringStringEntryProto"), 14: ("data_location", PBType.INT), - 5: ("int32_data", PBType.INTS), 7: ("int64_data", PBType.INTS), 8: ("name", PBType.STRING), 9: ("raw_data", PBType.BYTES)}, - "TensorShapeProtoDimension": {1: ("dim_value", PBType.INT), 2: ("dim_param", PBType.STRING)}, - "TensorShapeProto": {1: ("dim", PBType.SUB, True, "TensorShapeProtoDimension")}, - "ModelProto": {1: ("ir_version", PBType.INT), 5: ("model_version", PBType.INT), - 2: ("producer_name", PBType.STRING), 3: ("producer_version", PBType.STRING), 4: ("domain", PBType.STRING), 6: ("doc_string", PBType.STRING), - 7: ("graph", PBType.SUB, False, ("GraphProto", lambda: {"node": [], "initializer": [], "input": [], "output": [], "value_info": []})), - 8: ("opset_import",PBType.SUB, True, "OperatorSetIdProto")}, - "GraphProto": {2: ("name", PBType.STRING), 10: ("doc_string", PBType.STRING), - 1: ("node", PBType.SUB, True, ("NodeProto", lambda: {"input": [], "output": [], "attribute": [], "domain": None})), - 5: ("initializer", PBType.SUB, True, ("TensorProto", lambda: {"dims": [], "float_data": [], "int32_data": [], "string_data": [], - "int64_data": [], "double_data": [], "uint64_data": []})), - 11: ("input", PBType.SUB, True, "ValueInfoProto"), 12: ("output", PBType.SUB, True, "ValueInfoProto")}, - "NodeProto": { 1: ("input", PBType.STRING, True), 2: ("output", PBType.STRING, True), 3: ("name", PBType.STRING), - 4: ("op_type", PBType.STRING), 6: ("doc_string", PBType.STRING), 7: ("domain", PBType.STRING), - 5: ("attribute", PBType.SUB, True, ("AttributeProto", lambda: {"floats": [], "ints": [], "strings": []}))}, - "AttributeProto": {1: ("name", PBType.STRING), 20: ("type", PBType.INT), 3: ("i", PBType.INT), 8: ("ints", PBType.INT, True), - 2: ("f", PBType.FLOAT), 7: ("floats", PBType.FLOAT, True), 4: ("s", PBType.BYTES), 9: ("strings", PBType.BYTES, True), - 5:("t", PBType.SUB, False, ("TensorProto", lambda: {"dims": [], "float_data": [], "int32_data": [], "string_data": [], "int64_data": [], - "double_data": [], "uint64_data": []}))}, - "ValueInfoProto": {1: ("name", PBType.STRING), 2: ("type", PBType.SUB, False, "TypeProto"), 3: ("doc_string", PBType.STRING)}, - "TypeProto": {1: ("tensor_type", PBType.SUB, False, "TypeProtoTensor"), 4: ("sequence_type", PBType.SUB, False, "TypeProtoSequence"), - 9: ("optional_type", PBType.SUB, False, "TypeProtoOptional"), 6: ("denotation", PBType.STRING)}, - "TypeProtoSequence": {1: ("elem_type", PBType.SUB, False, "TypeProto")}, - "TypeProtoOptional": {1: ("elem_type", PBType.SUB, False, "TypeProto")}, - "TypeProtoTensor": {1: ("elem_type", PBType.INT), 2: ("shape", PBType.SUB, False, ("TensorShapeProto", lambda: {"dim": []}))}, -} - -def onnx_load(fn: Union[Tensor, str, pathlib.Path], load_external_data: bool=True): - parser = OnnxParser(fn, load_external_data) - onnx_model = parser.parse() - model = dict_to_namespace(onnx_model) - return model - -def gen_result(obj: dict, key_name, val, repeated: bool): - if repeated: obj.setdefault(key_name, []).append(val) - else: obj[key_name] = val - -def dict_to_namespace(d): - if isinstance(d, dict): return SimpleNamespace(**{k: dict_to_namespace(v) for k, v in d.items()}) - elif isinstance(d, list): return [dict_to_namespace(i) for i in d] - return d - -class OnnxParser: - def __init__(self, inp: Union[Tensor, str, pathlib.Path], load_external_data: bool=True): - self.file_path: Union[pathlib.Path, None] = None - self.load_external_data = load_external_data - if not isinstance(inp, Tensor): - self.file_path = pathlib.Path(inp) - self.tensor = Tensor(self.file_path) - else: self.tensor = inp - self.attr_func_dict = { PBType.BYTES: self._handle_bytes, PBType.SUB: self._handle_sub_message, PBType.FLOATS: self._handle_packed_floats, - PBType.INT: self._handle_int64, PBType.INTS: self._handle_packed_int64s, PBType.STRING: self._handle_string, PBType.FLOAT: self._handle_float} - self.registered_handles = {} - for pb_name in PB_INFOS: - res = {} - for fid, config in PB_INFOS[pb_name].items(): - parser_fn, repeated = None, False - if len(config) == 2: name, attr = config - elif len(config) == 3: name, attr, repeated = config - elif len(config) == 4: name, attr, repeated, parser_fn = config - handler_fn = self.attr_func_dict[attr] - def _wrapper_handler(obj, reader, wt, h=handler_fn, n=name, p=parser_fn, r=repeated): return h(obj, n, reader, wt, parser_func=p, repeated=r) - _wrapper_handler._debug_info = f"{fid}, {name} => {handler_fn}" - res[fid] = _wrapper_handler - self.registered_handles[pb_name] = res - - def parse(self): - reader = BufferedReader(TensorIO(self.tensor)) - return self._parse_message(reader, "ModelProto", lambda: {"opset_import": [], "domain": None, "graph": None}) - - def decode_varint(self, reader: BufferedReader) -> int: - result = 0 - shift = 0 - while True: - data = reader.read(1) - if data == b"": raise EOFError("decode_varint EOF") - result |= (data[0] & 0x7F) << shift - if not (data[0] & 0x80): return result - shift += 7 - if shift >= 70: raise ValueError("Varint too long") - - def skip_field_value(self, reader: BufferedReader, wire_type): - if wire_type == WIRETYPE_VARINT: self.decode_varint(reader) - elif wire_type == WIRETYPE_FIXED64: reader.seek(8, os.SEEK_CUR) - elif wire_type == WIRETYPE_FIXED32: reader.seek(4, os.SEEK_CUR) - elif wire_type == WIRETYPE_LENGTH_DELIMITED: reader.seek(self.decode_varint(reader), os.SEEK_CUR) - else: raise ValueError(f"Unknown wire type: {wire_type}") - - def _parse_message(self, reader, message_field_handlers_name, initial_obj_factory=lambda: {}): - message_field_handlers = self.registered_handles[message_field_handlers_name] - obj = initial_obj_factory() - while True: - try: - tag_val = self.decode_varint(reader) - field_number = tag_val >> 3 - wire_type = tag_val & 0x07 - if handler := message_field_handlers.get(field_number): - handler(obj, reader, wire_type) - else: self.skip_field_value(reader, wire_type) - except EOFError: break - if message_field_handlers_name == "TensorProto" and self.load_external_data and obj.get("data_location", 0) == 1: self._parse_external_data(obj) - return obj - - def _handle_delimited(self, reader:BufferedReader, use_tensor=False) -> Tuple[bytes, Tensor]: - str_len = self.decode_varint(reader) - if not use_tensor: return reader.read(str_len) - res = reader.raw._tensor[reader.tell():(reader.tell()+str_len)] - reader.seek(str_len, os.SEEK_CUR) - return res - - def _handle_string(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): - if wire_type != WIRETYPE_LENGTH_DELIMITED: raise ValueError(f"Expected length-delimited for string field '{key_name}'") - value = self._handle_delimited(reader) - gen_result(obj, key_name, value.decode("utf-8"), repeated) - - def _handle_bytes(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): - if wire_type != WIRETYPE_LENGTH_DELIMITED: raise ValueError(f"Expected length-delimited for bytes field '{key_name}'") - value = self._handle_delimited(reader, use_tensor=True) - gen_result(obj, key_name, value, repeated) - - def _handle_int64(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): - if wire_type != WIRETYPE_VARINT: raise ValueError(f"Expected varint for int64 field '{key_name}'") - val = self.decode_varint(reader) - gen_result(obj, key_name, val - 2**64 if val & (1 << 63) else val, repeated) - - def _handle_float(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): - if wire_type != WIRETYPE_FIXED32: raise ValueError(f"Expected fixed32 for float field '{key_name}'") - val, = struct.unpack(" None: - open(LOGOPS, "a").write(str(args[0]).replace("\n", "").replace(" ", "")+"\n") - return None - -if __name__ == "__main__": - _pmap("kernel", extract_ast) diff --git a/tinygrad/extra/optimization/extract_policynet.py b/tinygrad/extra/optimization/extract_policynet.py deleted file mode 100644 index da8aa0d4..00000000 --- a/tinygrad/extra/optimization/extract_policynet.py +++ /dev/null @@ -1,114 +0,0 @@ -import os, sys, sqlite3, pickle, random -from tqdm import tqdm, trange -from copy import deepcopy -from tinygrad.nn import Linear -from tinygrad.tensor import Tensor -from tinygrad.nn.optim import Adam -from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.engine.search import actions -from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, assert_same_lin -from tinygrad.codegen.kernel import Kernel -from tinygrad.helpers import getenv - -# stuff needed to unpack a kernel -from tinygrad.uop.ops import LazyOp, TernaryOps, BinaryOps, UnaryOps, ReduceOps, BufferOps, MemBuffer, ConstBuffer -from tinygrad.dtype import dtypes -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.uop.ops import Variable -inf, nan = float('inf'), float('nan') -from tinygrad.codegen.kernel import Opt, OptOps - -INNER = 256 -class PolicyNet: - def __init__(self): - self.l1 = Linear(1021,INNER) - self.l2 = Linear(INNER,INNER) - self.l3 = Linear(INNER,1+len(actions)) - def __call__(self, x): - x = self.l1(x).relu() - x = self.l2(x).relu().dropout(0.9) - return self.l3(x).log_softmax() - -def dataset_from_cache(fn): - conn = sqlite3.connect(fn) - cur = conn.cursor() - cur.execute("SELECT * FROM beam_search") - X,A = [], [] - for f in tqdm(cur.fetchall()): - Xs,As = [], [] - try: - lin = Kernel(eval(f[0])) - opts = pickle.loads(f[-1]) - for o in opts: - Xs.append(lin_to_feats(lin, use_sts=True)) - As.append(actions.index(o)) - lin.apply_opt(o) - Xs.append(lin_to_feats(lin, use_sts=True)) - As.append(0) - except Exception: - pass - X += Xs - A += As - return X,A - -if __name__ == "__main__": - if getenv("REGEN"): - X,V = dataset_from_cache(sys.argv[1] if len(sys.argv) > 1 else "/tmp/tinygrad_cache") - safe_save({"X": Tensor(X), "V": Tensor(V)}, "/tmp/dataset_policy") - else: - ld = safe_load("/tmp/dataset_policy") - X,V = ld['X'].numpy(), ld['V'].numpy() - - print(X.shape, V.shape) - order = list(range(X.shape[0])) - random.shuffle(order) - X, V = X[order], V[order] - - ratio = -256 - X_test, V_test = Tensor(X[ratio:]), Tensor(V[ratio:]) - X,V = X[:ratio], V[:ratio] - print(X.shape, V.shape) - - net = PolicyNet() - #if os.path.isfile("/tmp/policynet.safetensors"): load_state_dict(net, safe_load("/tmp/policynet.safetensors")) - optim = Adam(get_parameters(net)) - - def get_minibatch(X,Y,bs): - xs, ys = [], [] - for _ in range(bs): - sel = random.randint(0, len(X)-1) - xs.append(X[sel]) - ys.append(Y[sel]) - return Tensor(xs), Tensor(ys) - - Tensor.training = True - losses = [] - test_losses = [] - test_accuracy = 0 - test_loss = float('inf') - for i in (t:=trange(500)): - x,y = get_minibatch(X,V,bs=256) - out = net(x) - loss = out.sparse_categorical_crossentropy(y) - optim.zero_grad() - loss.backward() - optim.step() - cat = out.argmax(axis=-1) - accuracy = (cat == y).mean() - t.set_description(f"loss {loss.numpy():7.2f} accuracy {accuracy.numpy()*100:7.2f}%, test loss {test_loss:7.2f} test accuracy {test_accuracy*100:7.2f}%") - - losses.append(loss.numpy().item()) - test_losses.append(test_loss) - if i % 10: - out = net(X_test) - test_loss = out.sparse_categorical_crossentropy(V_test).square().mean().numpy().item() - cat = out.argmax(axis=-1) - test_accuracy = (cat == y).mean().numpy() - - safe_save(get_state_dict(net), "/tmp/policynet.safetensors") - - import matplotlib.pyplot as plt - plt.plot(losses[10:]) - plt.plot(test_losses[10:]) - plt.show() diff --git a/tinygrad/extra/optimization/extract_sa_pairs.py b/tinygrad/extra/optimization/extract_sa_pairs.py deleted file mode 100644 index 224d9c63..00000000 --- a/tinygrad/extra/optimization/extract_sa_pairs.py +++ /dev/null @@ -1,129 +0,0 @@ -import sys, sqlite3, pickle, math -from collections import defaultdict -from tqdm import tqdm, trange -import numpy as np - -# stuff needed to unpack a kernel -from tinygrad.uop.ops import LazyOp, TernaryOps, BinaryOps, UnaryOps, ReduceOps, BufferOps, MemBuffer, ConstBuffer -from tinygrad.dtype import dtypes -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.uop.ops import Variable -inf, nan = float('inf'), float('nan') -from tinygrad.codegen.kernel import Opt, OptOps - -# more stuff -from tinygrad.codegen.kernel import Kernel -from tinygrad.engine.search import actions -from extra.optimization.helpers import lin_to_feats -from extra.optimization.pretrain_valuenet import ValueNet -from tinygrad.nn.optim import Adam -from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -import random -from tinygrad.tensor import Tensor -from tinygrad.helpers import getenv - -def dataset_from_cache(fn): - conn = sqlite3.connect(fn) - cur = conn.cursor() - cur.execute("SELECT * FROM time_linearizer") - grouped = defaultdict(dict) - for f in tqdm(cur.fetchall()): grouped[f[0]][f[1:-1]] = pickle.loads(f[-1]) - - opts_to_outcome = {} - - for ast,sk in grouped.items(): - cnts = defaultdict(int) - for sks,tm in sk.items(): - if sks[1] != 1: continue - opts = eval(sks[0]) - cnts[(len(opts), sks[1])] += 1 - opts_to_outcome[(ast, tuple(opts))] = tm - #print(cnts) - - S,A,V = [], [], [] - for ast,k in tqdm(opts_to_outcome): - if len(k) == 0: continue - old_tm = min(opts_to_outcome[(ast,k[:-1])]) - new_tm = min(opts_to_outcome[(ast,k)]) - if math.isinf(old_tm) or math.isinf(new_tm) or old_tm < 1e-9 or new_tm < 1e-9: continue - try: - lin = Kernel(eval(ast)) - except Exception: - continue - lin.apply_opts(k[:-1]) - act = k[-1] - log_ratio = math.log(old_tm/new_tm) - #print(f"ratio: {old_tm/new_tm:6.2f}x (log {log_ratio:5.2f}) from {str(act):50s} on {lin.colored_shape()}") - S.append(lin_to_feats(lin, use_sts=True)) - A.append(actions.index(act)) - V.append([log_ratio]) # NOTE: i have written the bug many times with this having the wrong dim - - S, A, V = np.array(S), np.array(A), np.array(V, dtype=np.float32) - X = np.zeros((S.shape[0], S.shape[1]+len(actions)), dtype=np.float32) - X[:, :S.shape[1]] = S - X[range(S.shape[0]), S.shape[1]+A] = 1.0 - return X, V - -def log_likelihood(x:Tensor, mu:Tensor, log_sigma:Tensor): - #print(x.shape, mu.shape, log_sigma.shape) - #return (x-mu).abs() * (-log_sigma).exp() + log_sigma - return (x-mu).square() * (-2*log_sigma).exp() / 2 + log_sigma - -if __name__ == "__main__": - if getenv("REGEN"): - X,V = dataset_from_cache(sys.argv[1] if len(sys.argv) > 1 else "/tmp/tinygrad_cache") - safe_save({"X": Tensor(X), "V": Tensor(V)}, "/tmp/dataset") - else: - ld = safe_load("/tmp/dataset") - X,V = ld['X'].numpy(), ld['V'].numpy() - - print(X.shape, V.shape) - order = list(range(X.shape[0])) - random.shuffle(order) - X, V = X[order], V[order] - - ratio = -512 - X_test, V_test = Tensor(X[ratio:]), Tensor(V[ratio:]) - X,V = X[:ratio], V[:ratio] - print(X.shape, V.shape) - - #print(X[0], V[0]) - #print(X[-1], V[-1]) - print(X.shape) - - net = ValueNet(X.shape[1], 2) - optim = Adam(get_parameters(net)) - - def get_minibatch(X,Y,bs): - xs, ys = [], [] - #random.seed(1337) - for _ in range(bs): - sel = random.randint(0, len(X)-1) - xs.append(X[sel]) - ys.append(Y[sel]) - return Tensor(xs), Tensor(ys) - - Tensor.training = True - losses = [] - test_losses = [] - test_loss = float('inf') - for i in (t:=trange(2000)): - x,y = get_minibatch(X,V,bs=256) - out = net(x) - #loss = (out-y).square().mean() - loss = log_likelihood(y, out[:, 0:1], out[:, 1:2]).mean() - optim.zero_grad() - loss.backward() - optim.step() - t.set_description(f"loss {loss.numpy():7.2f}, test loss {test_loss:7.2f}") - losses.append(loss.numpy().item()) - test_losses.append(test_loss) - if i % 10: test_loss = (net(X_test)[:, 0:1]-V_test).square().mean().numpy().item() - - safe_save(get_state_dict(net), "/tmp/qnet.safetensors") - - import matplotlib.pyplot as plt - plt.plot(losses[20:]) - plt.plot(test_losses[20:]) - plt.show() diff --git a/tinygrad/extra/optimization/generate_dataset.sh b/tinygrad/extra/optimization/generate_dataset.sh deleted file mode 100755 index 66473154..00000000 --- a/tinygrad/extra/optimization/generate_dataset.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash -export PAGE_SIZE=1 -export PYTHONPATH=. -export LOGOPS=/tmp/ops -export CAPTURE_PROCESS_REPLAY=1 -rm $LOGOPS -test/external/process_replay/reset.py - -python3 -m pytest -n=auto test/ --ignore=test/unit --durations=20 -STEPS=3 python3 examples/hlb_cifar10.py -WINO=1 STEPS=3 python3 examples/hlb_cifar10.py -python3 examples/stable_diffusion.py --noshow -python3 examples/llama.py --prompt "hello" --count 5 -python3 examples/gpt2.py --count 5 -HALF=1 python3 examples/gpt2.py --count 5 -python3 examples/beautiful_mnist.py -python3 examples/beautiful_cartpole.py -python3 examples/mlperf/model_spec.py -python3 examples/yolov8.py ./test/models/efficientnet/Chicken.jpg -examples/openpilot/go.sh -JIT=2 BIG=1 MPS=1 pytest -n=auto test/ --ignore=test/test_fusion_op.py --ignore=test/test_linearizer_failures.py --ignore=test/test_gc.py --ignore=test/test_speed_v_torch.py --ignore=test/test_jit.py -JIT=2 BIG=1 MPS=1 python -m pytest test/test_gc.py -JIT=2 BIG=1 MPS=1 python -m pytest test/test_jit.py -JIT=2 BIG=1 MPS=1 python -m pytest test/test_speed_v_torch.py - -# extract, sort and uniq -extra/optimization/extract_dataset.py -sort -u /tmp/ops > /tmp/sops -ls -lh /tmp/ops /tmp/sops diff --git a/tinygrad/extra/optimization/get_action_space.py b/tinygrad/extra/optimization/get_action_space.py deleted file mode 100644 index f443d7c6..00000000 --- a/tinygrad/extra/optimization/get_action_space.py +++ /dev/null @@ -1,31 +0,0 @@ -import random -from extra.optimization.helpers import load_worlds, ast_str_to_lin -from tinygrad.engine.search import actions -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.helpers import tqdm - -tactions = set() -def test_rebuild(lin): - linr = Kernel(lin.ast) - for o in lin.applied_opts: - assert o in actions, f"{o} is not in actions" - tactions.add(o) - linr.apply_opt(o) - - assert len(lin.sts) == len(linr.sts) - for st1,st2 in zip(lin.sts, linr.sts): - assert st1 == st2, f"{st1} != {st2}" - -if __name__ == "__main__": - ast_strs = load_worlds(False, False, False) - random.shuffle(ast_strs) - ast_strs = ast_strs[:2000] - for ast_str in tqdm(ast_strs): - lin = ast_str_to_lin(ast_str) - #if not lin.apply_tensor_cores(): - lin.apply_opts(hand_coded_optimizations(lin)) - test_rebuild(lin) - - print(len(tactions), len(actions)) - print(sorted(list(tactions))) diff --git a/tinygrad/extra/optimization/helpers.py b/tinygrad/extra/optimization/helpers.py deleted file mode 100644 index 73006092..00000000 --- a/tinygrad/extra/optimization/helpers.py +++ /dev/null @@ -1,122 +0,0 @@ -# stuff needed to unpack a kernel -from tinygrad import Variable -from tinygrad.codegen.kernel import Opt, OptOps -from tinygrad.uop.ops import UOp, Ops, KernelInfo -from tinygrad.dtype import dtypes, PtrDType -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -inf, nan = float('inf'), float('nan') -UOps = Ops - -# kernel unpacker -from tinygrad.codegen.kernel import Kernel -def ast_str_to_ast(ast_str:str) -> UOp: return eval(ast_str) -def ast_str_to_lin(ast_str:str, opts=None): return Kernel(ast_str_to_ast(ast_str), opts=opts) -def kern_str_to_lin(kern_str:str, opts=None): - (ast, applied_opts,) = eval(kern_str) - k = Kernel(ast, opts=opts) - k.apply_opts(applied_opts) - return k - -# load worlds, a dataset of about 12k kernels -import gzip -from pathlib import Path -import random -from tinygrad.helpers import dedup, DEBUG -def load_worlds(filter_reduce=True, filter_noimage=True, filter_novariable=True): - fn = Path(__file__).parent.parent / "datasets/sops.gz" - ast_strs = dedup(gzip.open(fn).read().decode('utf-8').strip().split("\n")) - assert len(ast_strs) > 5000, f"dataset size = {len(ast_strs)} is too small" - if DEBUG >= 1: print(f"loaded {len(ast_strs)=} before filters") - if filter_reduce: ast_strs = [x for x in ast_strs if "REDUCE_AXIS" in x] - if filter_noimage: ast_strs = [x for x in ast_strs if "dtypes.image" not in x] - if filter_novariable: ast_strs = [x for x in ast_strs if "DEFINE_VAR" not in x] - if DEBUG >= 1: print(f"loaded {len(ast_strs)=} after filters {filter_reduce=}, {filter_noimage=}, {filter_novariable=}") - random.seed(1337) - random.shuffle(ast_strs) - return ast_strs - -def assert_same_lin(l1, l2): - assert l1.colored_shape() == l2.colored_shape() - assert all(x==y for x,y in zip(l1.sts, l2.sts)) - -# get features -import math - -MAX_DIMS = 16 -MAX_BUFS = 9 -def lin_to_feats(lin:Kernel, use_sts=True): - assert lin.shape_len < MAX_DIMS, "too many dims" - - all_colors = ["blue", "cyan", "white", "green", "red", "magenta", "yellow"] - lc = [all_colors.index(x) for x in lin.colors()] - - ret = [] - # before, some generic linearizer stuff - ret.append(lin.upcasted) - ret.append(lin.local_dims) - - # first, the full shape, including the colors - for s,os,c in zip(lin.full_shape,lin.output_shape,lc): - if isinstance(s, UOp): - ret.append(False) - ret += [0]*9 - else: - ret.append(True) - ret.append(math.log2(s)) - ret.append(min(33, s)) - ret.append(math.log2(os)) - ret.append(min(33, os)) - ret.append(s%2 == 0) - ret.append(s%3 == 0) - ret.append(s%4 == 0) - ret.append(s%8 == 0) - ret.append(s%16 == 0) - cc = [0]*7 - cc[c] = 1 - ret += cc - ret += [0] * (17*(MAX_DIMS-len(lin.full_shape))) - ret = [float(x) for x in ret] - - if use_sts: - my_sts = dedup([(x.shape == lin.full_shape, x.real_strides(), any(v.mask is not None for v in x.views), len(x.views)) for x in lin.sts]) - assert len(my_sts) < MAX_BUFS - sts_len = 3 + 5*MAX_DIMS - for s in my_sts: - ret.append(s[0]) # reduce - ret.append(s[2]) # has mask - ret.append(s[3]) # len views - for d in s[1]: - ret.append(d is None) - ret.append(d == 0) - ret.append(d == 1) - ret.append(min(33, d) if d is not None else -1) - if d is not None and d >= 1: ret.append(math.log2(d)) - else: ret.append(-1) - ret += [0] * (5*(MAX_DIMS - len(s[1]))) - ret += [0] * (sts_len*(MAX_BUFS - len(my_sts))) - assert len(ret) == 1021, f"wrong len {len(ret)}" - else: - assert len(ret) == 274, f"wrong len {len(ret)}" - return ret - -from tinygrad.device import Device, Buffer -from tinygrad.engine.search import _ensure_buffer_alloc, _time_program -from tinygrad.helpers import to_function_name, CACHELEVEL, diskcache_get, diskcache_put - -def time_linearizer(lin:Kernel, rawbufs:list[Buffer], allow_test_size=True, max_global_size=65536, cnt=3, disable_cache=False, clear_l2=False) -> float: # noqa: E501 - key = {"ast": lin.ast.key, "opts": str(lin.applied_opts), "allow_test_size": allow_test_size, - "max_global_size": max_global_size, "clear_l2": clear_l2, "device": lin.opts.device, "suffix": lin.opts.suffix} - if not disable_cache and CACHELEVEL >= 2 and (val:=diskcache_get("time_linearizer", key)) is not None: return min(val) - - dev = Device[lin.opts.device] - assert dev.compiler is not None - - rawbufs = _ensure_buffer_alloc(rawbufs) - var_vals: dict[Variable, int] = {k:int(k.vmax+k.vmin)//2 for k in lin.ast.variables()} - p = lin.to_program() - tms = _time_program(p, dev.compiler.compile(p.src), var_vals, rawbufs, - max_global_size=max_global_size if allow_test_size else None, clear_l2=clear_l2, cnt=cnt, name=to_function_name(lin.name)) - - if CACHELEVEL >= 2: diskcache_put("time_linearizer", key, tms) - return min(tms) diff --git a/tinygrad/extra/optimization/pretrain_valuenet.py b/tinygrad/extra/optimization/pretrain_valuenet.py deleted file mode 100644 index 312aec6f..00000000 --- a/tinygrad/extra/optimization/pretrain_valuenet.py +++ /dev/null @@ -1,88 +0,0 @@ -from tinygrad.codegen.kernel import Kernel -from tqdm import tqdm, trange -import math -import random -from tinygrad.tensor import Tensor -from tinygrad.nn import Linear -from tinygrad.nn.optim import Adam -from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict - -# stuff needed to unpack a kernel -from tinygrad.uop.ops import LazyOp, TernaryOps, BinaryOps, UnaryOps, ReduceOps, BufferOps, MemBuffer, ConstBuffer -from tinygrad.dtype import dtypes -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.uop.ops import Variable -inf, nan = float('inf'), float('nan') -from tinygrad.codegen.kernel import Opt, OptOps - -from extra.optimization.helpers import lin_to_feats, MAX_DIMS - -# NOTE: this is not real value of the state, it's just a prediction of the runtime -INNER = 512 -class ValueNet: - def __init__(self, feats=240, out=1): - self.l1 = Linear(feats,INNER) - self.l2 = Linear(INNER,INNER) - self.l3 = Linear(INNER,INNER) - self.l4 = Linear(INNER,out) - def __call__(self, x): - x = self.l1(x).relu() - x = self.l2(x).relu() - x = self.l3(x).relu().dropout(0.8) - return self.l4(x) - -if __name__ == "__main__": - net = ValueNet() - optim = Adam(get_parameters(net)) - - TEST_SIZE = 256 - - dset = open("/tmp/logtm").read().strip().split("\n") - random.seed(1337) - random.shuffle(dset) - - X,Y = [], [] - for i,x in enumerate(tqdm(dset)): - ast, opts, tms = eval(x) - lin = Kernel(ast) - for o in opts: lin.apply_opt(o) - if lin.shape_len >= MAX_DIMS: continue - if min(tms) == float('inf'): continue - X.append(lin_to_feats(lin)) - Y.append([math.log(min(tms))]) - print(f"got {len(X)} samples") - - X_test,Y_test = Tensor(X[-TEST_SIZE:]), Tensor(Y[-TEST_SIZE:]) - X,Y = X[:-TEST_SIZE], Y[:-TEST_SIZE] - - def get_minibatch(X,Y,bs): - xs, ys = [], [] - for _ in range(bs): - sel = random.randint(0, len(X)-1) - xs.append(X[sel]) - ys.append(Y[sel]) - return Tensor(xs), Tensor(ys) - - Tensor.training = True - losses = [] - test_losses = [] - test_loss = float('inf') - for i in (t:=trange(2000)): - x,y = get_minibatch(X,Y,bs=256) - out = net(x) - loss = (out-y).square().mean() - optim.zero_grad() - loss.backward() - optim.step() - t.set_description(f"loss {loss.numpy():7.2f}, test loss {test_loss:7.2f}") - losses.append(loss.numpy().item()) - test_losses.append(test_loss) - if i % 10: test_loss = (net(X_test)-Y_test).square().mean().numpy().item() - - safe_save(get_state_dict(net), "/tmp/valuenet.safetensors") - - import matplotlib.pyplot as plt - plt.plot(losses[200:]) - plt.plot(test_losses[200:]) - plt.show() diff --git a/tinygrad/extra/optimization/rl.py b/tinygrad/extra/optimization/rl.py deleted file mode 100644 index f0507095..00000000 --- a/tinygrad/extra/optimization/rl.py +++ /dev/null @@ -1,76 +0,0 @@ -import os -import numpy as np -import math, random -from tinygrad.tensor import Tensor -from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.engine.search import actions, bufs_from_lin, get_kernel_actions -from tinygrad.nn.optim import Adam -from extra.optimization.extract_policynet import PolicyNet -from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, time_linearizer - -if __name__ == "__main__": - net = PolicyNet() - if os.path.isfile("/tmp/policynet.safetensors"): load_state_dict(net, safe_load("/tmp/policynet.safetensors")) - optim = Adam(get_parameters(net)) - - ast_strs = load_worlds() - - # select a world - all_feats, all_acts, all_rews = [], [], [] - while 1: - Tensor.training = False - lin = ast_str_to_lin(random.choice(ast_strs)) - rawbufs = bufs_from_lin(lin) - tm = last_tm = base_tm = time_linearizer(lin, rawbufs) - - # take actions - feats, acts, rews = [], [], [] - while 1: - feat = lin_to_feats(lin) - feats.append(feat) - probs = net(Tensor([feat])).exp()[0].numpy() - - # mask valid actions - valid_action_mask = np.zeros((len(actions)+1), dtype=np.float32) - for x in get_kernel_actions(lin): valid_action_mask[x] = 1 - probs *= valid_action_mask - probs /= sum(probs) - - act = np.random.choice(len(probs), p=probs) - acts.append(act) - if act == 0: - rews.append(0) - break - try: - lin.apply_opt(actions[act-1]) - tm = time_linearizer(lin, rawbufs) - if math.isinf(tm): raise Exception("failed") - rews.append(((last_tm-tm)/base_tm)) - last_tm = tm - except Exception: - rews.append(-0.5) - break - #print(f"{tm*1e6:10.2f}", lin.colored_shape()) - - assert len(feats) == len(acts) and len(acts) == len(rews) - #print(rews) - print(f"***** EPISODE {len(rews)} steps, {sum(rews):5.2f} reward, {base_tm*1e6:12.2f} -> {tm*1e6:12.2f} : {lin.colored_shape()}") - all_feats += feats - all_acts += acts - # rewards to go - for i in range(len(rews)-2, -1, -1): rews[i] += rews[i+1] - all_rews += rews - - BS = 32 - if len(all_feats) >= BS: - Tensor.training = True - x = Tensor(all_feats[:BS]) - mask = np.zeros((BS, len(actions)+1), dtype=np.float32) - mask[range(BS), all_acts[:BS]] = all_rews[:BS] - loss = -(net(x) * Tensor(mask)).mean() - optim.zero_grad() - loss.backward() - optim.step() - all_feats = all_feats[BS:] - all_acts = all_acts[BS:] - all_rews = all_rews[BS:] diff --git a/tinygrad/extra/optimization/run_qnet.py b/tinygrad/extra/optimization/run_qnet.py deleted file mode 100644 index 65acae19..00000000 --- a/tinygrad/extra/optimization/run_qnet.py +++ /dev/null @@ -1,32 +0,0 @@ -from typing import List, Tuple -from tinygrad.codegen.kernel import Kernel -from tinygrad.engine.search import get_kernel_actions, actions - -_net = None -def beam_q_estimate(beam:List[Tuple[Kernel, float]]) -> List[Tuple[Kernel, float]]: - global _net - if _net is None: - from tinygrad.nn.state import load_state_dict, safe_load - from extra.optimization.pretrain_valuenet import ValueNet - _net = ValueNet(1021+len(actions), 2) - load_state_dict(_net, safe_load("/tmp/qnet.safetensors"), verbose=False) - from tinygrad.tensor import Tensor - from tinygrad.helpers import Context - from extra.optimization.helpers import lin_to_feats - import numpy as np - feats = [] - lins = [] - base_tms = [] - for lin,tm in beam: - lin_feats = lin_to_feats(lin) - for a,v in get_kernel_actions(lin, include_0=False).items(): - acts = np.zeros(len(actions)) - acts[a-1] = 1.0 - feats.append(np.concatenate([lin_feats, acts])) - lins.append(v) - base_tms.append(tm) - with Context(BEAM=0): - with Tensor.train(False): - preds = _net(Tensor(feats)).numpy() - pred_time = np.array(base_tms) / np.exp(preds[:, 0]) - return sorted(zip(lins, pred_time), key=lambda x: x[1]) diff --git a/tinygrad/extra/optimization/search.py b/tinygrad/extra/optimization/search.py deleted file mode 100644 index 469487da..00000000 --- a/tinygrad/extra/optimization/search.py +++ /dev/null @@ -1,34 +0,0 @@ -import argparse -from extra.optimization.helpers import ast_str_to_lin, time_linearizer - -from tinygrad import dtypes -from tinygrad.helpers import BEAM, getenv -from tinygrad.device import Device, Compiled -from tinygrad.codegen.kernel import Kernel -from tinygrad.engine.search import beam_search, bufs_from_lin - - -if __name__ == '__main__': - parser = argparse.ArgumentParser(description="Run a search for the optimal opts for a kernel", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--ast", type=str, default=None, help="the ast for the kernel to be optimized") - parser.add_argument("--file", type=str, default=None, help="a file containing asts to be optimized, one per line") - args = parser.parse_args() - - device: Compiled = Device[Device.DEFAULT] - print(f"optimizing for {Device.DEFAULT}") - - if args.ast is not None: - ast_strs = [args.ast] - elif args.file is not None: - with open(args.file, 'r') as file: - ast_strs = file.readlines() - - for i, ast_str in enumerate(ast_strs): - print(f"optimizing {i}/{len(ast_strs)}\nast={ast_str}") - lin = ast_str_to_lin(ast_str, opts=device.renderer) - rawbufs = bufs_from_lin(lin) - lin = beam_search(lin, rawbufs, getenv("BEAM", 8), bool(getenv("BEAM_ESTIMATE", 1))) - - tm = time_linearizer(lin, rawbufs, allow_test_size=False, cnt=10) - print(f"final time {tm*1e6:9.0f} us: {lin.colored_shape()}") - print(lin.applied_opts) diff --git a/tinygrad/extra/optimization/test_beam_search.py b/tinygrad/extra/optimization/test_beam_search.py deleted file mode 100644 index 24c3f943..00000000 --- a/tinygrad/extra/optimization/test_beam_search.py +++ /dev/null @@ -1,81 +0,0 @@ -import unittest -import numpy as np - -from tinygrad.helpers import BEAM, Timing, CI, Context -from tinygrad import Variable, Tensor -from tinygrad.nn import Conv2d - -def rand(*shape): - return Tensor(np.random.rand(*shape).astype(np.float32)) - -class TestBeamSearch(unittest.TestCase): - def setUp(self): - self.old_beam = BEAM.value - BEAM.value = 2 - def tearDown(self): - BEAM.value = self.old_beam - - def test_variable_ast_beam(self): - with Context(IGNORE_OOB=1): - a = rand(3, 3).reshape((Variable("a", 1, 10).bind(3), 3)) - a = (a+1).realize() - - def test_big_prime_number(self): - a = rand(367, 367) - b = rand(367, 367) - c = (a@b).realize() - np.testing.assert_allclose(c.numpy(), a.numpy() @ b.numpy(), atol=1e-4, rtol=1e-4) - - def test_big_prime_number_max(self): - a = -rand(367, 367) - b = rand(367, 367) - # if incorrectly padded 0, the max would be 0 instead of a negative number - c = (a*b).max(1) - np.testing.assert_allclose(c.numpy(), (a.numpy() * b.numpy()).max(1), atol=1e-4, rtol=1e-4) - - def test_big_prime_number_sum(self): - a = rand(367, 367) - b = rand(367, 367) - # if incorrectly padded 0, the sum would be inf - c = (a/b).sum(1).realize() - np.testing.assert_allclose(c.numpy(), (a.numpy() / b.numpy()).sum(1), atol=1e-4, rtol=1e-4) - - def test_variable_big_prime_number(self): - v = Variable("v", 1, 400).bind(367) - a = rand(367, 367) - b = rand(367, 367) - with Context(IGNORE_OOB=1): - c = (a.reshape(367, v) @ b.reshape(v, 367)).realize() - np.testing.assert_allclose(c.numpy(), a.numpy() @ b.numpy(), atol=1e-4, rtol=1e-4) - - def test_variable_shrink_prime_number(self): - v = Variable("v", 1, 400).bind(367) - a = rand(400, 367) - with Context(IGNORE_OOB=1): - b = (a.shrink(((0,v), None))+1).reshape(367,367).realize() - np.testing.assert_allclose(b.numpy(), a.numpy()[:367]+1, atol=1e-4, rtol=1e-4) - - def test_no_mutate_rawbuffers(self): - a = rand(3, 3).realize() - desired = a.numpy() + 1 - a.assign(a+1) - actual = a.numpy() - np.testing.assert_allclose(actual, desired) - - @unittest.skipIf(CI, "flaky. CL_OUT_OF_RESOURCES") - def test_conv_beam(self): - c = Conv2d(3, 16, (3,3)) - x = rand(1,3,32,32) - with Timing(): - c(x).realize() - - @unittest.skip("flaky, Fatal Python error: Floating point exception") - def test_large_ast(self): - a = Tensor.rand(3, 3) - for _ in range(5): - for _ in range(4): - a = (a + a) * a - a.realize() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/extra/optimization/test_helpers.py b/tinygrad/extra/optimization/test_helpers.py deleted file mode 100644 index bd11f3d7..00000000 --- a/tinygrad/extra/optimization/test_helpers.py +++ /dev/null @@ -1,19 +0,0 @@ -import unittest - -from extra.optimization.helpers import load_worlds - -class TestKernelDataset(unittest.TestCase): - def test_load_worlds_filters(self): - all_kernels = load_worlds(filter_reduce=False, filter_noimage=False, filter_novariable=False) - - reduce_kernels = load_worlds(filter_reduce=True, filter_noimage=False, filter_novariable=False) - self.assertGreater(len(all_kernels), len(reduce_kernels)) - - image_kernels = load_worlds(filter_reduce=False, filter_noimage=True, filter_novariable=False) - self.assertGreater(len(all_kernels), len(image_kernels)) - - variable_kernels = load_worlds(filter_reduce=False, filter_noimage=False, filter_novariable=True) - self.assertGreater(len(all_kernels), len(variable_kernels)) - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/extra/optimization/test_net.py b/tinygrad/extra/optimization/test_net.py deleted file mode 100644 index 68a023f0..00000000 --- a/tinygrad/extra/optimization/test_net.py +++ /dev/null @@ -1,67 +0,0 @@ -import numpy as np -import math -import random -np.set_printoptions(suppress=True) -from copy import deepcopy -from tinygrad.helpers import getenv, colored -from tinygrad.tensor import Tensor -from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.engine.search import bufs_from_lin, actions, get_kernel_actions -from tinygrad.codegen.heuristic import hand_coded_optimizations -from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, time_linearizer -from extra.optimization.extract_policynet import PolicyNet -from extra.optimization.pretrain_valuenet import ValueNet - -VALUE = getenv("VALUE") - -if __name__ == "__main__": - if VALUE: - net = ValueNet() - load_state_dict(net, safe_load("/tmp/valuenet.safetensors")) - else: - net = PolicyNet() - load_state_dict(net, safe_load("/tmp/policynet.safetensors")) - - ast_strs = load_worlds() - - # real randomness - random.seed() - random.shuffle(ast_strs) - - wins = 0 - for ep_num,ast_str in enumerate(ast_strs): - print("\nEPISODE", ep_num, f"win {wins*100/max(1,ep_num):.2f}%") - lin = ast_str_to_lin(ast_str) - rawbufs = bufs_from_lin(lin) - - linhc = deepcopy(lin) - linhc.applied_opts(hand_coded_optimizations(linhc)) - tmhc = time_linearizer(linhc, rawbufs) - print(f"{tmhc*1e6:10.2f} HC ", linhc.colored_shape()) - - pred_time = float('nan') - tm = float('inf') - while 1: - if VALUE: - acts,feats = [], [] - for k,v in get_kernel_actions(lin).items(): - acts.append(k) - feats.append(lin_to_feats(v)) - preds = net(Tensor(feats)) - pred_time = math.exp(preds.numpy().min()) - act = acts[preds.numpy().argmin()] - else: - probs = net(Tensor([lin_to_feats(lin)])) - dist = probs.exp().numpy() - act = dist.argmax() - if act == 0: break - try: - lin.apply_opt(actions[act-1]) - except Exception: - print("FAILED") - break - tm = time_linearizer(lin, rawbufs) - print(f"{tm*1e6:10.2f} {pred_time*1e6:10.2f}", lin.colored_shape()) - - print(f"{colored('BEAT', 'green') if tm < tmhc else colored('lost', 'red')} hand coded {tmhc/tm:5.2f}x") - wins += int(tm < tmhc) \ No newline at end of file diff --git a/tinygrad/extra/optimization/test_time_linearizer.py b/tinygrad/extra/optimization/test_time_linearizer.py deleted file mode 100644 index 4bfb1f0f..00000000 --- a/tinygrad/extra/optimization/test_time_linearizer.py +++ /dev/null @@ -1,21 +0,0 @@ -from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer -from tinygrad.engine.search import bufs_from_lin, get_kernel_actions - -if __name__ == "__main__": - ast_strs = load_worlds() - for i, ast_str in enumerate(ast_strs): - lin = ast_str_to_lin(ast_str) - rawbufs = bufs_from_lin(lin) - test_tm = time_linearizer(lin, rawbufs) - if test_tm < 1e-2: continue - print(f"EXAMPLE {i}") - acted_lins = get_kernel_actions(lin) - ok_avg, short_avg = 0, 0 - for k,v in acted_lins.items(): - tm1 = time_linearizer(v, rawbufs) - tm2 = time_linearizer(v, rawbufs) - tm3 = time_linearizer(v, rawbufs, False) - print(v.colored_shape(50), f"{tm1*1e3:10.2f} {tm2*1e3:10.2f} {tm3*1e3:10.2f} : {((tm1-tm2)/tm1)*100:5.2f}% vs {((tm1-tm3)/tm1)*100:5.2f}%") - ok_avg += (tm1-tm2)/tm1 - short_avg += (tm1-tm3)/tm1 - print(f"{ok_avg/len(acted_lins)*100:5.2f}% vs {short_avg/len(acted_lins)*100:5.2f}%") diff --git a/tinygrad/extra/profiler/index.html b/tinygrad/extra/profiler/index.html deleted file mode 100644 index 637d02d1..00000000 --- a/tinygrad/extra/profiler/index.html +++ /dev/null @@ -1,173 +0,0 @@ - - - - tinygrad profiler - - - - - - - - - - diff --git a/tinygrad/extra/qcom_gpu_driver/a6xx.xml.h b/tinygrad/extra/qcom_gpu_driver/a6xx.xml.h deleted file mode 100644 index 75e60eef..00000000 --- a/tinygrad/extra/qcom_gpu_driver/a6xx.xml.h +++ /dev/null @@ -1,16783 +0,0 @@ -#ifndef A6XX_XML -#define A6XX_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng gen_header.py tool in this git repository: -http://gitlab.freedesktop.org/mesa/mesa/ -git clone https://gitlab.freedesktop.org/mesa/mesa.git - -The rules-ng-ng source files this header was generated from are: - -- /Users/slava/dev/mesa/src/freedreno/registers/adreno/a6xx.xml ( 337844 bytes, from Tue Jul 2 00:22:42 2024) -- /Users/slava/dev/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1582 bytes, from Mon Jun 17 18:03:38 2024) -- /Users/slava/dev/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15485 bytes, from Mon Jun 17 18:03:38 2024) -- /Users/slava/dev/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 86290 bytes, from Mon Jun 17 18:03:38 2024) - -Copyright (C) 2013-2024 by the following authors: -- Rob Clark Rob Clark -- Ilia Mirkin Ilia Mirkin - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -*/ - -#ifdef __KERNEL__ -#include -#define assert(x) BUG_ON(!(x)) -#else -#include -#endif - -#ifdef __cplusplus -#define __struct_cast(X) -#else -#define __struct_cast(X) (struct X) -#endif - -enum vgt_event_type { - VS_DEALLOC = 0, - PS_DEALLOC = 1, - VS_DONE_TS = 2, - PS_DONE_TS = 3, - CACHE_FLUSH_TS = 4, - CONTEXT_DONE = 5, - CACHE_FLUSH = 6, - VIZQUERY_START = 7, - HLSQ_FLUSH = 7, - VIZQUERY_END = 8, - SC_WAIT_WC = 9, - WRITE_PRIMITIVE_COUNTS = 9, - START_PRIMITIVE_CTRS = 11, - STOP_PRIMITIVE_CTRS = 12, - RST_PIX_CNT = 13, - RST_VTX_CNT = 14, - TILE_FLUSH = 15, - STAT_EVENT = 16, - CACHE_FLUSH_AND_INV_TS_EVENT = 20, - ZPASS_DONE = 21, - CACHE_FLUSH_AND_INV_EVENT = 22, - RB_DONE_TS = 22, - PERFCOUNTER_START = 23, - PERFCOUNTER_STOP = 24, - VS_FETCH_DONE = 27, - FACENESS_FLUSH = 28, - WT_DONE_TS = 8, - START_FRAGMENT_CTRS = 13, - STOP_FRAGMENT_CTRS = 14, - START_COMPUTE_CTRS = 15, - STOP_COMPUTE_CTRS = 16, - FLUSH_SO_0 = 17, - FLUSH_SO_1 = 18, - FLUSH_SO_2 = 19, - FLUSH_SO_3 = 20, - PC_CCU_INVALIDATE_DEPTH = 24, - PC_CCU_INVALIDATE_COLOR = 25, - PC_CCU_RESOLVE_TS = 26, - PC_CCU_FLUSH_DEPTH_TS = 28, - PC_CCU_FLUSH_COLOR_TS = 29, - BLIT = 30, - LRZ_FLIP_BUFFER = 36, - LRZ_CLEAR = 37, - LRZ_FLUSH = 38, - BLIT_OP_FILL_2D = 39, - BLIT_OP_COPY_2D = 40, - UNK_40 = 40, - BLIT_OP_SCALE_2D = 42, - CONTEXT_DONE_2D = 43, - UNK_2C = 44, - UNK_2D = 45, - CACHE_INVALIDATE = 49, - LABEL = 63, - DUMMY_EVENT = 1, - CCU_INVALIDATE_DEPTH = 24, - CCU_INVALIDATE_COLOR = 25, - CCU_RESOLVE_CLEAN = 26, - CCU_FLUSH_DEPTH = 28, - CCU_FLUSH_COLOR = 29, - CCU_RESOLVE = 30, - CCU_END_RESOLVE_GROUP = 31, - CCU_CLEAN_DEPTH = 32, - CCU_CLEAN_COLOR = 33, - CACHE_RESET = 48, - CACHE_CLEAN = 49, - CACHE_FLUSH7 = 50, - CACHE_INVALIDATE7 = 51, -}; - -enum pc_di_primtype { - DI_PT_NONE = 0, - DI_PT_POINTLIST_PSIZE = 1, - DI_PT_LINELIST = 2, - DI_PT_LINESTRIP = 3, - DI_PT_TRILIST = 4, - DI_PT_TRIFAN = 5, - DI_PT_TRISTRIP = 6, - DI_PT_LINELOOP = 7, - DI_PT_RECTLIST = 8, - DI_PT_POINTLIST = 9, - DI_PT_LINE_ADJ = 10, - DI_PT_LINESTRIP_ADJ = 11, - DI_PT_TRI_ADJ = 12, - DI_PT_TRISTRIP_ADJ = 13, - DI_PT_PATCHES0 = 31, - DI_PT_PATCHES1 = 32, - DI_PT_PATCHES2 = 33, - DI_PT_PATCHES3 = 34, - DI_PT_PATCHES4 = 35, - DI_PT_PATCHES5 = 36, - DI_PT_PATCHES6 = 37, - DI_PT_PATCHES7 = 38, - DI_PT_PATCHES8 = 39, - DI_PT_PATCHES9 = 40, - DI_PT_PATCHES10 = 41, - DI_PT_PATCHES11 = 42, - DI_PT_PATCHES12 = 43, - DI_PT_PATCHES13 = 44, - DI_PT_PATCHES14 = 45, - DI_PT_PATCHES15 = 46, - DI_PT_PATCHES16 = 47, - DI_PT_PATCHES17 = 48, - DI_PT_PATCHES18 = 49, - DI_PT_PATCHES19 = 50, - DI_PT_PATCHES20 = 51, - DI_PT_PATCHES21 = 52, - DI_PT_PATCHES22 = 53, - DI_PT_PATCHES23 = 54, - DI_PT_PATCHES24 = 55, - DI_PT_PATCHES25 = 56, - DI_PT_PATCHES26 = 57, - DI_PT_PATCHES27 = 58, - DI_PT_PATCHES28 = 59, - DI_PT_PATCHES29 = 60, - DI_PT_PATCHES30 = 61, - DI_PT_PATCHES31 = 62, -}; - -enum pc_di_src_sel { - DI_SRC_SEL_DMA = 0, - DI_SRC_SEL_IMMEDIATE = 1, - DI_SRC_SEL_AUTO_INDEX = 2, - DI_SRC_SEL_AUTO_XFB = 3, -}; - -enum pc_di_face_cull_sel { - DI_FACE_CULL_NONE = 0, - DI_FACE_CULL_FETCH = 1, - DI_FACE_BACKFACE_CULL = 2, - DI_FACE_FRONTFACE_CULL = 3, -}; - -enum pc_di_index_size { - INDEX_SIZE_IGN = 0, - INDEX_SIZE_16_BIT = 0, - INDEX_SIZE_32_BIT = 1, - INDEX_SIZE_8_BIT = 2, - INDEX_SIZE_INVALID = 0, -}; - -enum pc_di_vis_cull_mode { - IGNORE_VISIBILITY = 0, - USE_VISIBILITY = 1, -}; - -enum adreno_pm4_packet_type { - CP_TYPE0_PKT = 0x00000000, - CP_TYPE1_PKT = 0x40000000, - CP_TYPE2_PKT = 0x80000000, - CP_TYPE3_PKT = 0xc0000000, - CP_TYPE4_PKT = 0x40000000, - CP_TYPE7_PKT = 0x70000000, -}; - -enum adreno_pm4_type3_packets { - CP_ME_INIT = 72, - CP_NOP = 16, - CP_PREEMPT_ENABLE = 28, - CP_PREEMPT_TOKEN = 30, - CP_INDIRECT_BUFFER = 63, - CP_INDIRECT_BUFFER_CHAIN = 87, - CP_INDIRECT_BUFFER_PFD = 55, - CP_WAIT_FOR_IDLE = 38, - CP_WAIT_REG_MEM = 60, - CP_WAIT_REG_EQ = 82, - CP_WAIT_REG_GTE = 83, - CP_WAIT_UNTIL_READ = 92, - CP_WAIT_IB_PFD_COMPLETE = 93, - CP_REG_RMW = 33, - CP_SET_BIN_DATA = 47, - CP_SET_BIN_DATA5 = 47, - CP_REG_TO_MEM = 62, - CP_MEM_WRITE = 61, - CP_MEM_WRITE_CNTR = 79, - CP_COND_EXEC = 68, - CP_COND_WRITE = 69, - CP_COND_WRITE5 = 69, - CP_EVENT_WRITE = 70, - CP_EVENT_WRITE7 = 70, - CP_EVENT_WRITE_SHD = 88, - CP_EVENT_WRITE_CFL = 89, - CP_EVENT_WRITE_ZPD = 91, - CP_RUN_OPENCL = 49, - CP_DRAW_INDX = 34, - CP_DRAW_INDX_2 = 54, - CP_DRAW_INDX_BIN = 52, - CP_DRAW_INDX_2_BIN = 53, - CP_VIZ_QUERY = 35, - CP_SET_STATE = 37, - CP_SET_CONSTANT = 45, - CP_IM_LOAD = 39, - CP_IM_LOAD_IMMEDIATE = 43, - CP_LOAD_CONSTANT_CONTEXT = 46, - CP_INVALIDATE_STATE = 59, - CP_SET_SHADER_BASES = 74, - CP_SET_BIN_MASK = 80, - CP_SET_BIN_SELECT = 81, - CP_CONTEXT_UPDATE = 94, - CP_INTERRUPT = 64, - CP_IM_STORE = 44, - CP_SET_DRAW_INIT_FLAGS = 75, - CP_SET_PROTECTED_MODE = 95, - CP_BOOTSTRAP_UCODE = 111, - CP_LOAD_STATE = 48, - CP_LOAD_STATE4 = 48, - CP_COND_INDIRECT_BUFFER_PFE = 58, - CP_COND_INDIRECT_BUFFER_PFD = 50, - CP_INDIRECT_BUFFER_PFE = 63, - CP_SET_BIN = 76, - CP_TEST_TWO_MEMS = 113, - CP_REG_WR_NO_CTXT = 120, - CP_RECORD_PFP_TIMESTAMP = 17, - CP_SET_SECURE_MODE = 102, - CP_WAIT_FOR_ME = 19, - CP_SET_DRAW_STATE = 67, - CP_DRAW_INDX_OFFSET = 56, - CP_DRAW_INDIRECT = 40, - CP_DRAW_INDX_INDIRECT = 41, - CP_DRAW_INDIRECT_MULTI = 42, - CP_DRAW_AUTO = 36, - CP_DRAW_PRED_ENABLE_GLOBAL = 25, - CP_DRAW_PRED_ENABLE_LOCAL = 26, - CP_DRAW_PRED_SET = 78, - CP_WIDE_REG_WRITE = 116, - CP_SCRATCH_TO_REG = 77, - CP_REG_TO_SCRATCH = 74, - CP_WAIT_MEM_WRITES = 18, - CP_COND_REG_EXEC = 71, - CP_MEM_TO_REG = 66, - CP_EXEC_CS_INDIRECT = 65, - CP_EXEC_CS = 51, - CP_PERFCOUNTER_ACTION = 80, - CP_SMMU_TABLE_UPDATE = 83, - CP_SET_MARKER = 101, - CP_SET_PSEUDO_REG = 86, - CP_CONTEXT_REG_BUNCH = 92, - CP_YIELD_ENABLE = 28, - CP_SKIP_IB2_ENABLE_GLOBAL = 29, - CP_SKIP_IB2_ENABLE_LOCAL = 35, - CP_SET_SUBDRAW_SIZE = 53, - CP_WHERE_AM_I = 98, - CP_SET_VISIBILITY_OVERRIDE = 100, - CP_PREEMPT_ENABLE_GLOBAL = 105, - CP_PREEMPT_ENABLE_LOCAL = 106, - CP_CONTEXT_SWITCH_YIELD = 107, - CP_SET_RENDER_MODE = 108, - CP_COMPUTE_CHECKPOINT = 110, - CP_MEM_TO_MEM = 115, - CP_BLIT = 44, - CP_REG_TEST = 57, - CP_SET_MODE = 99, - CP_LOAD_STATE6_GEOM = 50, - CP_LOAD_STATE6_FRAG = 52, - CP_LOAD_STATE6 = 54, - IN_IB_PREFETCH_END = 23, - IN_SUBBLK_PREFETCH = 31, - IN_INSTR_PREFETCH = 32, - IN_INSTR_MATCH = 71, - IN_CONST_PREFETCH = 73, - IN_INCR_UPDT_STATE = 85, - IN_INCR_UPDT_CONST = 86, - IN_INCR_UPDT_INSTR = 87, - PKT4 = 4, - IN_IB_END = 10, - IN_GMU_INTERRUPT = 11, - IN_PREEMPT = 15, - CP_SCRATCH_WRITE = 76, - CP_REG_TO_MEM_OFFSET_MEM = 116, - CP_REG_TO_MEM_OFFSET_REG = 114, - CP_WAIT_MEM_GTE = 20, - CP_WAIT_TWO_REGS = 112, - CP_MEMCPY = 117, - CP_SET_BIN_DATA5_OFFSET = 46, - CP_SET_UNK_BIN_DATA = 45, - CP_CONTEXT_SWITCH = 84, - CP_SET_CTXSWITCH_IB = 85, - CP_REG_WRITE = 109, - CP_START_BIN = 80, - CP_END_BIN = 81, - CP_PREEMPT_DISABLE = 108, - CP_WAIT_TIMESTAMP = 20, - CP_GLOBAL_TIMESTAMP = 21, - CP_LOCAL_TIMESTAMP = 22, - CP_THREAD_CONTROL = 23, - CP_RESOURCE_LIST = 24, - CP_BV_BR_COUNT_OPS = 27, - CP_MODIFY_TIMESTAMP = 28, - CP_CONTEXT_REG_BUNCH2 = 93, - CP_MEM_TO_SCRATCH_MEM = 73, - CP_FIXED_STRIDE_DRAW_TABLE = 127, - CP_RESET_CONTEXT_STATE = 31, - CP_CCHE_INVALIDATE = 58, -}; - -enum adreno_state_block { - SB_VERT_TEX = 0, - SB_VERT_MIPADDR = 1, - SB_FRAG_TEX = 2, - SB_FRAG_MIPADDR = 3, - SB_VERT_SHADER = 4, - SB_GEOM_SHADER = 5, - SB_FRAG_SHADER = 6, - SB_COMPUTE_SHADER = 7, -}; - -enum adreno_state_type { - ST_SHADER = 0, - ST_CONSTANTS = 1, -}; - -enum adreno_state_src { - SS_DIRECT = 0, - SS_INVALID_ALL_IC = 2, - SS_INVALID_PART_IC = 3, - SS_INDIRECT = 4, - SS_INDIRECT_TCM = 5, - SS_INDIRECT_STM = 6, -}; - -enum a4xx_state_block { - SB4_VS_TEX = 0, - SB4_HS_TEX = 1, - SB4_DS_TEX = 2, - SB4_GS_TEX = 3, - SB4_FS_TEX = 4, - SB4_CS_TEX = 5, - SB4_VS_SHADER = 8, - SB4_HS_SHADER = 9, - SB4_DS_SHADER = 10, - SB4_GS_SHADER = 11, - SB4_FS_SHADER = 12, - SB4_CS_SHADER = 13, - SB4_SSBO = 14, - SB4_CS_SSBO = 15, -}; - -enum a4xx_state_type { - ST4_SHADER = 0, - ST4_CONSTANTS = 1, - ST4_UBO = 2, -}; - -enum a4xx_state_src { - SS4_DIRECT = 0, - SS4_INDIRECT = 2, -}; - -enum a6xx_state_block { - SB6_VS_TEX = 0, - SB6_HS_TEX = 1, - SB6_DS_TEX = 2, - SB6_GS_TEX = 3, - SB6_FS_TEX = 4, - SB6_CS_TEX = 5, - SB6_VS_SHADER = 8, - SB6_HS_SHADER = 9, - SB6_DS_SHADER = 10, - SB6_GS_SHADER = 11, - SB6_FS_SHADER = 12, - SB6_CS_SHADER = 13, - SB6_IBO = 14, - SB6_CS_IBO = 15, -}; - -enum a6xx_state_type { - ST6_SHADER = 0, - ST6_CONSTANTS = 1, - ST6_UBO = 2, - ST6_IBO = 3, -}; - -enum a6xx_state_src { - SS6_DIRECT = 0, - SS6_BINDLESS = 1, - SS6_INDIRECT = 2, - SS6_UBO = 3, -}; - -enum a4xx_index_size { - INDEX4_SIZE_8_BIT = 0, - INDEX4_SIZE_16_BIT = 1, - INDEX4_SIZE_32_BIT = 2, -}; - -enum a6xx_patch_type { - TESS_QUADS = 0, - TESS_TRIANGLES = 1, - TESS_ISOLINES = 2, -}; - -enum a6xx_draw_indirect_opcode { - INDIRECT_OP_NORMAL = 2, - INDIRECT_OP_INDEXED = 4, - INDIRECT_OP_INDIRECT_COUNT = 6, - INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7, -}; - -enum cp_draw_pred_src { - PRED_SRC_MEM = 5, -}; - -enum cp_draw_pred_test { - NE_0_PASS = 0, - EQ_0_PASS = 1, -}; - -enum cp_cond_function { - WRITE_ALWAYS = 0, - WRITE_LT = 1, - WRITE_LE = 2, - WRITE_EQ = 3, - WRITE_NE = 4, - WRITE_GE = 5, - WRITE_GT = 6, -}; - -enum poll_memory_type { - POLL_REGISTER = 0, - POLL_MEMORY = 1, - POLL_SCRATCH = 2, - POLL_ON_CHIP = 3, -}; - -enum render_mode_cmd { - BYPASS = 1, - BINNING = 2, - GMEM = 3, - BLIT2D = 5, - BLIT2DSCALE = 7, - END2D = 8, -}; - -enum event_write_src { - EV_WRITE_USER_32B = 0, - EV_WRITE_USER_64B = 1, - EV_WRITE_TIMESTAMP_SUM = 2, - EV_WRITE_ALWAYSON = 3, - EV_WRITE_REGS_CONTENT = 4, -}; - -enum event_write_dst { - EV_DST_RAM = 0, - EV_DST_ONCHIP = 1, -}; - -enum cp_blit_cmd { - BLIT_OP_FILL = 0, - BLIT_OP_COPY = 1, - BLIT_OP_SCALE = 3, -}; - -enum a6xx_marker { - RM6_BYPASS = 1, - RM6_BINNING = 2, - RM6_GMEM = 4, - RM6_ENDVIS = 5, - RM6_RESOLVE = 6, - RM6_YIELD = 7, - RM6_COMPUTE = 8, - RM6_BLIT2DSCALE = 12, - RM6_IB1LIST_START = 13, - RM6_IB1LIST_END = 14, - RM6_IFPC_ENABLE = 256, - RM6_IFPC_DISABLE = 257, -}; - -enum pseudo_reg { - SMMU_INFO = 0, - NON_SECURE_SAVE_ADDR = 1, - SECURE_SAVE_ADDR = 2, - NON_PRIV_SAVE_ADDR = 3, - COUNTER = 4, - DRAW_STRM_ADDRESS = 8, - DRAW_STRM_SIZE_ADDRESS = 9, - PRIM_STRM_ADDRESS = 10, - UNK_STRM_ADDRESS = 11, - UNK_STRM_SIZE_ADDRESS = 12, - BINDLESS_BASE_0_ADDR = 16, - BINDLESS_BASE_1_ADDR = 17, - BINDLESS_BASE_2_ADDR = 18, - BINDLESS_BASE_3_ADDR = 19, - BINDLESS_BASE_4_ADDR = 20, - BINDLESS_BASE_5_ADDR = 21, - BINDLESS_BASE_6_ADDR = 22, -}; - -enum source_type { - SOURCE_REG = 0, - SOURCE_SCRATCH_MEM = 1, -}; - -enum compare_mode { - PRED_TEST = 1, - REG_COMPARE = 2, - RENDER_MODE = 3, - REG_COMPARE_IMM = 4, - THREAD_MODE = 5, -}; - -enum ctxswitch_ib { - RESTORE_IB = 0, - YIELD_RESTORE_IB = 1, - SAVE_IB = 2, - RB_SAVE_IB = 3, -}; - -enum reg_tracker { - TRACK_CNTL_REG = 1, - TRACK_RENDER_CNTL = 2, - UNK_EVENT_WRITE = 4, - TRACK_LRZ = 8, -}; - -enum ts_wait_value_src { - TS_WAIT_GE_32B = 0, - TS_WAIT_GE_64B = 1, - TS_WAIT_GE_TIMESTAMP_SUM = 2, -}; - -enum ts_wait_type { - TS_WAIT_RAM = 0, - TS_WAIT_ONCHIP = 1, -}; - -enum pipe_count_op { - PIPE_CLEAR_BV_BR = 1, - PIPE_SET_BR_OFFSET = 2, - PIPE_BR_WAIT_FOR_BV = 3, - PIPE_BV_WAIT_FOR_BR = 4, -}; - -enum timestamp_op { - MODIFY_TIMESTAMP_CLEAR = 0, - MODIFY_TIMESTAMP_ADD_GLOBAL = 1, - MODIFY_TIMESTAMP_ADD_LOCAL = 2, -}; - -enum cp_thread { - CP_SET_THREAD_BR = 1, - CP_SET_THREAD_BV = 2, - CP_SET_THREAD_BOTH = 3, -}; - -#define REG_CP_LOAD_STATE_0 0x00000000 -#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff -#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 -static inline unsigned int CP_LOAD_STATE_0_DST_OFF(unsigned int val) -{ - return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 -#define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 -static inline unsigned int CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) -{ - return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 -#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 -static inline unsigned int CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) -{ - return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 -static inline unsigned int CP_LOAD_STATE_0_NUM_UNIT(unsigned int val) -{ - return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE_1 0x00000001 -#define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 -#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 -static inline unsigned int CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) -{ - return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 -static inline unsigned int CP_LOAD_STATE_1_EXT_SRC_ADDR(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE4_0 0x00000000 -#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff -#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 -static inline unsigned int CP_LOAD_STATE4_0_DST_OFF(unsigned int val) -{ - return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 -#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 -static inline unsigned int CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) -{ - return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 -#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 -static inline unsigned int CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) -{ - return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 -static inline unsigned int CP_LOAD_STATE4_0_NUM_UNIT(unsigned int val) -{ - return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE4_1 0x00000001 -#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 -#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 -static inline unsigned int CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) -{ - return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 -static inline unsigned int CP_LOAD_STATE4_1_EXT_SRC_ADDR(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE4_2 0x00000002 -#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff -#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 -static inline unsigned int CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(unsigned int val) -{ - return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; -} - -#define REG_CP_LOAD_STATE6_0 0x00000000 -#define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff -#define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 -static inline unsigned int CP_LOAD_STATE6_0_DST_OFF(unsigned int val) -{ - return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; -} -#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 -#define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 -static inline unsigned int CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; -} -#define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 -#define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 -static inline unsigned int CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; -} -#define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 -#define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 -static inline unsigned int CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) -{ - return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; -} -#define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 -#define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 -static inline unsigned int CP_LOAD_STATE6_0_NUM_UNIT(unsigned int val) -{ - return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; -} - -#define REG_CP_LOAD_STATE6_1 0x00000001 -#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc -#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 -static inline unsigned int CP_LOAD_STATE6_1_EXT_SRC_ADDR(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; -} - -#define REG_CP_LOAD_STATE6_2 0x00000002 -#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff -#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 -static inline unsigned int CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(unsigned int val) -{ - return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; -} - -#define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001 - -#define REG_CP_DRAW_INDX_0 0x00000000 -#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff -#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_0_VIZ_QUERY(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; -} - -#define REG_CP_DRAW_INDX_1 0x00000001 -#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 -static inline unsigned int CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 -#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 -static inline unsigned int CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 -#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 -static inline unsigned int CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_1_NOT_EOP 0x00001000 -#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 -#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 -#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 -static inline unsigned int CP_DRAW_INDX_1_NUM_INSTANCES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_2 0x00000002 -#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_2_NUM_INDICES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_3 0x00000003 -#define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff -#define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_3_INDX_BASE(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; -} - -#define REG_CP_DRAW_INDX_4 0x00000004 -#define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff -#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_4_INDX_SIZE(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; -} - -#define REG_CP_DRAW_INDX_2_0 0x00000000 -#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff -#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_2_0_VIZ_QUERY(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; -} - -#define REG_CP_DRAW_INDX_2_1 0x00000001 -#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 -static inline unsigned int CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 -#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 -static inline unsigned int CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 -#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 -static inline unsigned int CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) -{ - return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 -#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 -#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 -#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 -#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 -static inline unsigned int CP_DRAW_INDX_2_1_NUM_INSTANCES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_2_2 0x00000002 -#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_2_2_NUM_INDICES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 -#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 -static inline unsigned int CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 -static inline unsigned int CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 -static inline unsigned int CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000 -#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12 -static inline unsigned int CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000 -#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000 - -#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 -#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 -#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_2_NUM_INDICES(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 -#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_3_FIRST_INDX(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004 -#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005 -#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 - -#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006 -#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_4_INDX_BASE(unsigned long long val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; -} - -#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 -#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 -static inline unsigned int CP_DRAW_INDX_OFFSET_5_INDX_SIZE(unsigned int val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 -#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 -#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 -#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 - -#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 -#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff -#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDIRECT_1_INDIRECT(unsigned int val) -{ - return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; -} - -#define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 -#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 -#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; -} - -#define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001 - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK; -} -#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 -#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 -#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(unsigned int val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 -#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(unsigned int val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; -} - -#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 -#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff -#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 -static inline unsigned int A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(unsigned int val) -{ - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 -#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 -#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001 - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 -#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 -#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 -#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff -#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 -static inline unsigned int A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(unsigned int val) -{ - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; -} - -#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004 - -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000 -#define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000 - -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001 -#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f -#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK; -} -#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00 -#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8 -static inline unsigned int A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(unsigned int val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK; -} - -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 - -#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 - -#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 - -#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 - -#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 - -#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 - -#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008 - -#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a - -#define REG_CP_DRAW_AUTO_0 0x00000000 -#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0 -static inline unsigned int CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK; -} -#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6 -static inline unsigned int CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK; -} -#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300 -#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8 -static inline unsigned int CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK; -} -#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00 -#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10 -static inline unsigned int CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK; -} -#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000 -#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12 -static inline unsigned int CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK; -} -#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000 -#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000 - -#define REG_CP_DRAW_AUTO_1 0x00000001 -#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff -#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0 -static inline unsigned int CP_DRAW_AUTO_1_NUM_INSTANCES(unsigned int val) -{ - return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK; -} - -#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002 - -#define REG_CP_DRAW_AUTO_4 0x00000004 -#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff -#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0 -static inline unsigned int CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(unsigned int val) -{ - return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK; -} - -#define REG_CP_DRAW_AUTO_5 0x00000005 -#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff -#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0 -static inline unsigned int CP_DRAW_AUTO_5_STRIDE(unsigned int val) -{ - return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK; -} - -#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 -#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 - -#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000 -#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001 - -#define REG_CP_DRAW_PRED_SET_0 0x00000000 -#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0 -#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4 -static inline unsigned int CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) -{ - return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK; -} -#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100 -#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8 -static inline unsigned int CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) -{ - return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK; -} - -#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 - -#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*i0 ) - -static inline unsigned int REG_CP_SET_DRAW_STATE__0(unsigned int i0) { return 0x00000000 + 0x3*i0; } -#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff -#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 -static inline unsigned int CP_SET_DRAW_STATE__0_COUNT(unsigned int val) -{ - return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; -} -#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 -#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 -#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 -#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 -#define CP_SET_DRAW_STATE__0_BINNING 0x00100000 -#define CP_SET_DRAW_STATE__0_GMEM 0x00200000 -#define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000 -#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 -#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 -static inline unsigned int CP_SET_DRAW_STATE__0_GROUP_ID(unsigned int val) -{ - return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; -} - -static inline unsigned int REG_CP_SET_DRAW_STATE__1(unsigned int i0) { return 0x00000001 + 0x3*i0; } -#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff -#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 -static inline unsigned int CP_SET_DRAW_STATE__1_ADDR_LO(unsigned int val) -{ - return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; -} - -static inline unsigned int REG_CP_SET_DRAW_STATE__2(unsigned int i0) { return 0x00000002 + 0x3*i0; } -#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff -#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 -static inline unsigned int CP_SET_DRAW_STATE__2_ADDR_HI(unsigned int val) -{ - return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; -} - -#define REG_CP_SET_BIN_0 0x00000000 - -#define REG_CP_SET_BIN_1 0x00000001 -#define CP_SET_BIN_1_X1__MASK 0x0000ffff -#define CP_SET_BIN_1_X1__SHIFT 0 -static inline unsigned int CP_SET_BIN_1_X1(unsigned int val) -{ - return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; -} -#define CP_SET_BIN_1_Y1__MASK 0xffff0000 -#define CP_SET_BIN_1_Y1__SHIFT 16 -static inline unsigned int CP_SET_BIN_1_Y1(unsigned int val) -{ - return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; -} - -#define REG_CP_SET_BIN_2 0x00000002 -#define CP_SET_BIN_2_X2__MASK 0x0000ffff -#define CP_SET_BIN_2_X2__SHIFT 0 -static inline unsigned int CP_SET_BIN_2_X2(unsigned int val) -{ - return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; -} -#define CP_SET_BIN_2_Y2__MASK 0xffff0000 -#define CP_SET_BIN_2_Y2__SHIFT 16 -static inline unsigned int CP_SET_BIN_2_Y2(unsigned int val) -{ - return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; -} - -#define REG_CP_SET_BIN_DATA_0 0x00000000 -#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff -#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA_0_BIN_DATA_ADDR(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; -} - -#define REG_CP_SET_BIN_DATA_1 0x00000001 -#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff -#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; -} - -#define REG_CP_SET_BIN_DATA5_0 0x00000000 -#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 -#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 -static inline unsigned int CP_SET_BIN_DATA5_0_VSC_SIZE(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; -} -#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 -#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 -static inline unsigned int CP_SET_BIN_DATA5_0_VSC_N(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; -} - -#define REG_CP_SET_BIN_DATA5_1 0x00000001 -#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_2 0x00000002 -#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff -#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; -} - -#define REG_CP_SET_BIN_DATA5_3 0x00000003 -#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_4 0x00000004 -#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff -#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; -} - -#define REG_CP_SET_BIN_DATA5_5 0x00000005 -#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff -#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK; -} - -#define REG_CP_SET_BIN_DATA5_6 0x00000006 -#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff -#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK; -} - -#define REG_CP_SET_BIN_DATA5_7 0x00000007 - -#define REG_CP_SET_BIN_DATA5_9 0x00000009 - -#define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000 -#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000 -#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16 -static inline unsigned int CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK; -} -#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000 -#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22 -static inline unsigned int CP_SET_BIN_DATA5_OFFSET_0_VSC_N(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK; -} - -#define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001 -#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff -#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK; -} - -#define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002 -#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff -#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK; -} - -#define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003 -#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff -#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0 -static inline unsigned int CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(unsigned int val) -{ - return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK; -} - -#define REG_CP_REG_RMW_0 0x00000000 -#define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff -#define CP_REG_RMW_0_DST_REG__SHIFT 0 -static inline unsigned int CP_REG_RMW_0_DST_REG(unsigned int val) -{ - return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK; -} -#define CP_REG_RMW_0_ROTATE__MASK 0x1f000000 -#define CP_REG_RMW_0_ROTATE__SHIFT 24 -static inline unsigned int CP_REG_RMW_0_ROTATE(unsigned int val) -{ - return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK; -} -#define CP_REG_RMW_0_SRC1_ADD 0x20000000 -#define CP_REG_RMW_0_SRC1_IS_REG 0x40000000 -#define CP_REG_RMW_0_SRC0_IS_REG 0x80000000 - -#define REG_CP_REG_RMW_1 0x00000001 -#define CP_REG_RMW_1_SRC0__MASK 0xffffffff -#define CP_REG_RMW_1_SRC0__SHIFT 0 -static inline unsigned int CP_REG_RMW_1_SRC0(unsigned int val) -{ - return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK; -} - -#define REG_CP_REG_RMW_2 0x00000002 -#define CP_REG_RMW_2_SRC1__MASK 0xffffffff -#define CP_REG_RMW_2_SRC1__SHIFT 0 -static inline unsigned int CP_REG_RMW_2_SRC1(unsigned int val) -{ - return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK; -} - -#define REG_CP_REG_TO_MEM_0 0x00000000 -#define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff -#define CP_REG_TO_MEM_0_REG__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_0_REG(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; -} -#define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000 -#define CP_REG_TO_MEM_0_CNT__SHIFT 18 -static inline unsigned int CP_REG_TO_MEM_0_CNT(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; -} -#define CP_REG_TO_MEM_0_64B 0x40000000 -#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 - -#define REG_CP_REG_TO_MEM_1 0x00000001 -#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff -#define CP_REG_TO_MEM_1_DEST__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_1_DEST(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; -} - -#define REG_CP_REG_TO_MEM_2 0x00000002 -#define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff -#define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_2_DEST_HI(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000 -#define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff -#define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_REG_0_REG(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK; -} -#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000 -#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18 -static inline unsigned int CP_REG_TO_MEM_OFFSET_REG_0_CNT(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK; -} -#define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000 -#define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000 - -#define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001 -#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_REG_1_DEST(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002 -#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003 -#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff -#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK; -} -#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000 - -#define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000 -#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff -#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_0_REG(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK; -} -#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000 -#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_0_CNT(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK; -} -#define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000 -#define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000 - -#define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001 -#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_1_DEST(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002 -#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003 -#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK; -} - -#define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004 -#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff -#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0 -static inline unsigned int CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(unsigned int val) -{ - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK; -} - -#define REG_CP_MEM_TO_REG_0 0x00000000 -#define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff -#define CP_MEM_TO_REG_0_REG__SHIFT 0 -static inline unsigned int CP_MEM_TO_REG_0_REG(unsigned int val) -{ - return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; -} -#define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 -#define CP_MEM_TO_REG_0_CNT__SHIFT 19 -static inline unsigned int CP_MEM_TO_REG_0_CNT(unsigned int val) -{ - return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; -} -#define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000 -#define CP_MEM_TO_REG_0_UNK31 0x80000000 - -#define REG_CP_MEM_TO_REG_1 0x00000001 -#define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff -#define CP_MEM_TO_REG_1_SRC__SHIFT 0 -static inline unsigned int CP_MEM_TO_REG_1_SRC(unsigned int val) -{ - return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; -} - -#define REG_CP_MEM_TO_REG_2 0x00000002 -#define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff -#define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 -static inline unsigned int CP_MEM_TO_REG_2_SRC_HI(unsigned int val) -{ - return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; -} - -#define REG_CP_MEM_TO_MEM_0 0x00000000 -#define CP_MEM_TO_MEM_0_NEG_A 0x00000001 -#define CP_MEM_TO_MEM_0_NEG_B 0x00000002 -#define CP_MEM_TO_MEM_0_NEG_C 0x00000004 -#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 -#define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000 -#define CP_MEM_TO_MEM_0_UNK31 0x80000000 - -#define REG_CP_MEMCPY_0 0x00000000 -#define CP_MEMCPY_0_DWORDS__MASK 0xffffffff -#define CP_MEMCPY_0_DWORDS__SHIFT 0 -static inline unsigned int CP_MEMCPY_0_DWORDS(unsigned int val) -{ - return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK; -} - -#define REG_CP_MEMCPY_1 0x00000001 -#define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff -#define CP_MEMCPY_1_SRC_LO__SHIFT 0 -static inline unsigned int CP_MEMCPY_1_SRC_LO(unsigned int val) -{ - return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK; -} - -#define REG_CP_MEMCPY_2 0x00000002 -#define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff -#define CP_MEMCPY_2_SRC_HI__SHIFT 0 -static inline unsigned int CP_MEMCPY_2_SRC_HI(unsigned int val) -{ - return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK; -} - -#define REG_CP_MEMCPY_3 0x00000003 -#define CP_MEMCPY_3_DST_LO__MASK 0xffffffff -#define CP_MEMCPY_3_DST_LO__SHIFT 0 -static inline unsigned int CP_MEMCPY_3_DST_LO(unsigned int val) -{ - return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK; -} - -#define REG_CP_MEMCPY_4 0x00000004 -#define CP_MEMCPY_4_DST_HI__MASK 0xffffffff -#define CP_MEMCPY_4_DST_HI__SHIFT 0 -static inline unsigned int CP_MEMCPY_4_DST_HI(unsigned int val) -{ - return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK; -} - -#define REG_CP_REG_TO_SCRATCH_0 0x00000000 -#define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff -#define CP_REG_TO_SCRATCH_0_REG__SHIFT 0 -static inline unsigned int CP_REG_TO_SCRATCH_0_REG(unsigned int val) -{ - return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK; -} -#define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000 -#define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20 -static inline unsigned int CP_REG_TO_SCRATCH_0_SCRATCH(unsigned int val) -{ - return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK; -} -#define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000 -#define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24 -static inline unsigned int CP_REG_TO_SCRATCH_0_CNT(unsigned int val) -{ - return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK; -} - -#define REG_CP_SCRATCH_TO_REG_0 0x00000000 -#define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff -#define CP_SCRATCH_TO_REG_0_REG__SHIFT 0 -static inline unsigned int CP_SCRATCH_TO_REG_0_REG(unsigned int val) -{ - return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK; -} -#define CP_SCRATCH_TO_REG_0_UNK18 0x00040000 -#define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000 -#define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20 -static inline unsigned int CP_SCRATCH_TO_REG_0_SCRATCH(unsigned int val) -{ - return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK; -} -#define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000 -#define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24 -static inline unsigned int CP_SCRATCH_TO_REG_0_CNT(unsigned int val) -{ - return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK; -} - -#define REG_CP_SCRATCH_WRITE_0 0x00000000 -#define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000 -#define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20 -static inline unsigned int CP_SCRATCH_WRITE_0_SCRATCH(unsigned int val) -{ - return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK; -} - -#define REG_CP_MEM_WRITE_0 0x00000000 -#define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff -#define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0 -static inline unsigned int CP_MEM_WRITE_0_ADDR_LO(unsigned int val) -{ - return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK; -} - -#define REG_CP_MEM_WRITE_1 0x00000001 -#define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff -#define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0 -static inline unsigned int CP_MEM_WRITE_1_ADDR_HI(unsigned int val) -{ - return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK; -} - -#define REG_CP_COND_WRITE_0 0x00000000 -#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 -#define CP_COND_WRITE_0_FUNCTION__SHIFT 0 -static inline unsigned int CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) -{ - return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; -} -#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 -#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 - -#define REG_CP_COND_WRITE_1 0x00000001 -#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff -#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 -static inline unsigned int CP_COND_WRITE_1_POLL_ADDR(unsigned int val) -{ - return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; -} - -#define REG_CP_COND_WRITE_2 0x00000002 -#define CP_COND_WRITE_2_REF__MASK 0xffffffff -#define CP_COND_WRITE_2_REF__SHIFT 0 -static inline unsigned int CP_COND_WRITE_2_REF(unsigned int val) -{ - return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; -} - -#define REG_CP_COND_WRITE_3 0x00000003 -#define CP_COND_WRITE_3_MASK__MASK 0xffffffff -#define CP_COND_WRITE_3_MASK__SHIFT 0 -static inline unsigned int CP_COND_WRITE_3_MASK(unsigned int val) -{ - return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; -} - -#define REG_CP_COND_WRITE_4 0x00000004 -#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff -#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 -static inline unsigned int CP_COND_WRITE_4_WRITE_ADDR(unsigned int val) -{ - return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; -} - -#define REG_CP_COND_WRITE_5 0x00000005 -#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff -#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 -static inline unsigned int CP_COND_WRITE_5_WRITE_DATA(unsigned int val) -{ - return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; -} - -#define REG_CP_COND_WRITE5_0 0x00000000 -#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 -#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) -{ - return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; -} -#define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 -#define CP_COND_WRITE5_0_POLL__MASK 0x00000030 -#define CP_COND_WRITE5_0_POLL__SHIFT 4 -static inline unsigned int CP_COND_WRITE5_0_POLL(enum poll_memory_type val) -{ - return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK; -} -#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 - -#define REG_CP_COND_WRITE5_1 0x00000001 -#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff -#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_1_POLL_ADDR_LO(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; -} - -#define REG_CP_COND_WRITE5_2 0x00000002 -#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff -#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_2_POLL_ADDR_HI(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; -} - -#define REG_CP_COND_WRITE5_3 0x00000003 -#define CP_COND_WRITE5_3_REF__MASK 0xffffffff -#define CP_COND_WRITE5_3_REF__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_3_REF(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; -} - -#define REG_CP_COND_WRITE5_4 0x00000004 -#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff -#define CP_COND_WRITE5_4_MASK__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_4_MASK(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; -} - -#define REG_CP_COND_WRITE5_5 0x00000005 -#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff -#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_5_WRITE_ADDR_LO(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; -} - -#define REG_CP_COND_WRITE5_6 0x00000006 -#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff -#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_6_WRITE_ADDR_HI(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; -} - -#define REG_CP_COND_WRITE5_7 0x00000007 -#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff -#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 -static inline unsigned int CP_COND_WRITE5_7_WRITE_DATA(unsigned int val) -{ - return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; -} - -#define REG_CP_WAIT_MEM_GTE_0 0x00000000 -#define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff -#define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0 -static inline unsigned int CP_WAIT_MEM_GTE_0_RESERVED(unsigned int val) -{ - return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK; -} - -#define REG_CP_WAIT_MEM_GTE_1 0x00000001 -#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff -#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0 -static inline unsigned int CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(unsigned int val) -{ - return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK; -} - -#define REG_CP_WAIT_MEM_GTE_2 0x00000002 -#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff -#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0 -static inline unsigned int CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(unsigned int val) -{ - return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK; -} - -#define REG_CP_WAIT_MEM_GTE_3 0x00000003 -#define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff -#define CP_WAIT_MEM_GTE_3_REF__SHIFT 0 -static inline unsigned int CP_WAIT_MEM_GTE_3_REF(unsigned int val) -{ - return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK; -} - -#define REG_CP_WAIT_REG_MEM_0 0x00000000 -#define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007 -#define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) -{ - return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; -} -#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 -#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030 -#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4 -static inline unsigned int CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val) -{ - return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK; -} -#define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 - -#define REG_CP_WAIT_REG_MEM_1 0x00000001 -#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff -#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_1_POLL_ADDR_LO(unsigned int val) -{ - return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK; -} - -#define REG_CP_WAIT_REG_MEM_2 0x00000002 -#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff -#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_2_POLL_ADDR_HI(unsigned int val) -{ - return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK; -} - -#define REG_CP_WAIT_REG_MEM_3 0x00000003 -#define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff -#define CP_WAIT_REG_MEM_3_REF__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_3_REF(unsigned int val) -{ - return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK; -} - -#define REG_CP_WAIT_REG_MEM_4 0x00000004 -#define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff -#define CP_WAIT_REG_MEM_4_MASK__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_4_MASK(unsigned int val) -{ - return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK; -} - -#define REG_CP_WAIT_REG_MEM_5 0x00000005 -#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff -#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0 -static inline unsigned int CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(unsigned int val) -{ - return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK; -} - -#define REG_CP_WAIT_TWO_REGS_0 0x00000000 -#define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff -#define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0 -static inline unsigned int CP_WAIT_TWO_REGS_0_REG0(unsigned int val) -{ - return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK; -} - -#define REG_CP_WAIT_TWO_REGS_1 0x00000001 -#define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff -#define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0 -static inline unsigned int CP_WAIT_TWO_REGS_1_REG1(unsigned int val) -{ - return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK; -} - -#define REG_CP_WAIT_TWO_REGS_2 0x00000002 -#define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff -#define CP_WAIT_TWO_REGS_2_REF__SHIFT 0 -static inline unsigned int CP_WAIT_TWO_REGS_2_REF(unsigned int val) -{ - return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_0 0x00000000 - -#define REG_CP_DISPATCH_COMPUTE_1 0x00000001 -#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 -static inline unsigned int CP_DISPATCH_COMPUTE_1_X(unsigned int val) -{ - return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_2 0x00000002 -#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 -static inline unsigned int CP_DISPATCH_COMPUTE_2_Y(unsigned int val) -{ - return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; -} - -#define REG_CP_DISPATCH_COMPUTE_3 0x00000003 -#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff -#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 -static inline unsigned int CP_DISPATCH_COMPUTE_3_Z(unsigned int val) -{ - return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; -} - -#define REG_CP_SET_RENDER_MODE_0 0x00000000 -#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff -#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) -{ - return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; -} - -#define REG_CP_SET_RENDER_MODE_1 0x00000001 -#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff -#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_1_ADDR_0_LO(unsigned int val) -{ - return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; -} - -#define REG_CP_SET_RENDER_MODE_2 0x00000002 -#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff -#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_2_ADDR_0_HI(unsigned int val) -{ - return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; -} - -#define REG_CP_SET_RENDER_MODE_3 0x00000003 -#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 -#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 - -#define REG_CP_SET_RENDER_MODE_4 0x00000004 - -#define REG_CP_SET_RENDER_MODE_5 0x00000005 -#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff -#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_5_ADDR_1_LEN(unsigned int val) -{ - return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; -} - -#define REG_CP_SET_RENDER_MODE_6 0x00000006 -#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff -#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_6_ADDR_1_LO(unsigned int val) -{ - return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; -} - -#define REG_CP_SET_RENDER_MODE_7 0x00000007 -#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff -#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 -static inline unsigned int CP_SET_RENDER_MODE_7_ADDR_1_HI(unsigned int val) -{ - return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 -#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 -static inline unsigned int CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(unsigned int val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 -#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 -static inline unsigned int CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(unsigned int val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 - -#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 - -#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 -#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0 -static inline unsigned int CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(unsigned int val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 -#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 -static inline unsigned int CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(unsigned int val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 -#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 -static inline unsigned int CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(unsigned int val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; -} - -#define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 - -#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 - -#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 -#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff -#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 -static inline unsigned int CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(unsigned int val) -{ - return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; -} - -#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 -#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff -#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 -static inline unsigned int CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(unsigned int val) -{ - return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; -} - -#define REG_CP_EVENT_WRITE_0 0x00000000 -#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff -#define CP_EVENT_WRITE_0_EVENT__SHIFT 0 -static inline unsigned int CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) -{ - return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; -} -#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 -#define CP_EVENT_WRITE_0_IRQ 0x80000000 - -#define REG_CP_EVENT_WRITE_1 0x00000001 -#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff -#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 -static inline unsigned int CP_EVENT_WRITE_1_ADDR_0_LO(unsigned int val) -{ - return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; -} - -#define REG_CP_EVENT_WRITE_2 0x00000002 -#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff -#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 -static inline unsigned int CP_EVENT_WRITE_2_ADDR_0_HI(unsigned int val) -{ - return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; -} - -#define REG_CP_EVENT_WRITE_3 0x00000003 - -#define REG_CP_EVENT_WRITE7_0 0x00000000 -#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff -#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0 -static inline unsigned int CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val) -{ - return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK; -} -#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000 -#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000 -#define CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF 0x00004000 -#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000 -#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000 -#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000 -#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000 -#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000 -#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20 -static inline unsigned int CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val) -{ - return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK; -} -#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000 -#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24 -static inline unsigned int CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val) -{ - return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK; -} -#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000 - -#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001 -#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff -#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0 -static inline unsigned int EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(unsigned int val) -{ - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK; -} - -#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002 -#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff -#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0 -static inline unsigned int EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(unsigned int val) -{ - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK; -} - -#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003 -#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff -#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 -static inline unsigned int EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(unsigned int val) -{ - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; -} - -#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004 -#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff -#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 -static inline unsigned int EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(unsigned int val) -{ - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; -} - -#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001 -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0 -static inline unsigned int EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(unsigned int val) -{ - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK; -} - -#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003 -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 -static inline unsigned int EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(unsigned int val) -{ - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; -} - -#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004 -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff -#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 -static inline unsigned int EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(unsigned int val) -{ - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; -} - -#define REG_CP_BLIT_0 0x00000000 -#define CP_BLIT_0_OP__MASK 0x0000000f -#define CP_BLIT_0_OP__SHIFT 0 -static inline unsigned int CP_BLIT_0_OP(enum cp_blit_cmd val) -{ - return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; -} - -#define REG_CP_BLIT_1 0x00000001 -#define CP_BLIT_1_SRC_X1__MASK 0x00003fff -#define CP_BLIT_1_SRC_X1__SHIFT 0 -static inline unsigned int CP_BLIT_1_SRC_X1(unsigned int val) -{ - return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; -} -#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 -#define CP_BLIT_1_SRC_Y1__SHIFT 16 -static inline unsigned int CP_BLIT_1_SRC_Y1(unsigned int val) -{ - return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; -} - -#define REG_CP_BLIT_2 0x00000002 -#define CP_BLIT_2_SRC_X2__MASK 0x00003fff -#define CP_BLIT_2_SRC_X2__SHIFT 0 -static inline unsigned int CP_BLIT_2_SRC_X2(unsigned int val) -{ - return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; -} -#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 -#define CP_BLIT_2_SRC_Y2__SHIFT 16 -static inline unsigned int CP_BLIT_2_SRC_Y2(unsigned int val) -{ - return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; -} - -#define REG_CP_BLIT_3 0x00000003 -#define CP_BLIT_3_DST_X1__MASK 0x00003fff -#define CP_BLIT_3_DST_X1__SHIFT 0 -static inline unsigned int CP_BLIT_3_DST_X1(unsigned int val) -{ - return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; -} -#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 -#define CP_BLIT_3_DST_Y1__SHIFT 16 -static inline unsigned int CP_BLIT_3_DST_Y1(unsigned int val) -{ - return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; -} - -#define REG_CP_BLIT_4 0x00000004 -#define CP_BLIT_4_DST_X2__MASK 0x00003fff -#define CP_BLIT_4_DST_X2__SHIFT 0 -static inline unsigned int CP_BLIT_4_DST_X2(unsigned int val) -{ - return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; -} -#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 -#define CP_BLIT_4_DST_Y2__SHIFT 16 -static inline unsigned int CP_BLIT_4_DST_Y2(unsigned int val) -{ - return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; -} - -#define REG_CP_EXEC_CS_0 0x00000000 - -#define REG_CP_EXEC_CS_1 0x00000001 -#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff -#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 -static inline unsigned int CP_EXEC_CS_1_NGROUPS_X(unsigned int val) -{ - return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; -} - -#define REG_CP_EXEC_CS_2 0x00000002 -#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff -#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 -static inline unsigned int CP_EXEC_CS_2_NGROUPS_Y(unsigned int val) -{ - return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; -} - -#define REG_CP_EXEC_CS_3 0x00000003 -#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff -#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 -static inline unsigned int CP_EXEC_CS_3_NGROUPS_Z(unsigned int val) -{ - return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; -} - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 -#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff -#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 -static inline unsigned int A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(unsigned int val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; -} - -#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 -static inline unsigned int A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(unsigned int val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; -} -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 -static inline unsigned int A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(unsigned int val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; -} -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 -#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 -static inline unsigned int A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(unsigned int val) -{ - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; -} - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 -#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff -#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 -static inline unsigned int A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(unsigned int val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; -} - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 -#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff -#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 -static inline unsigned int A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(unsigned int val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; -} - -#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 -static inline unsigned int A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(unsigned int val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; -} -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 -static inline unsigned int A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(unsigned int val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; -} -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 -#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 -static inline unsigned int A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(unsigned int val) -{ - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; -} - -#define REG_A6XX_CP_SET_MARKER_0 0x00000000 -#define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff -#define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0 -static inline unsigned int A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val) -{ - return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK; -} -#define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f -#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0 -static inline unsigned int A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) -{ - return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; -} - -#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*i0 ) - -static inline unsigned int REG_A6XX_CP_SET_PSEUDO_REG__0(unsigned int i0) { return 0x00000000 + 0x3*i0; } -#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff -#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 -static inline unsigned int A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) -{ - return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; -} - -static inline unsigned int REG_A6XX_CP_SET_PSEUDO_REG__1(unsigned int i0) { return 0x00000001 + 0x3*i0; } -#define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff -#define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 -static inline unsigned int A6XX_CP_SET_PSEUDO_REG__1_LO(unsigned int val) -{ - return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK; -} - -static inline unsigned int REG_A6XX_CP_SET_PSEUDO_REG__2(unsigned int i0) { return 0x00000002 + 0x3*i0; } -#define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff -#define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 -static inline unsigned int A6XX_CP_SET_PSEUDO_REG__2_HI(unsigned int val) -{ - return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK; -} - -#define REG_A6XX_CP_REG_TEST_0 0x00000000 -#define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff -#define A6XX_CP_REG_TEST_0_REG__SHIFT 0 -static inline unsigned int A6XX_CP_REG_TEST_0_REG(unsigned int val) -{ - return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; -} -#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff -#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0 -static inline unsigned int A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(unsigned int val) -{ - return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK; -} -#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000 -#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18 -static inline unsigned int A6XX_CP_REG_TEST_0_SOURCE(enum source_type val) -{ - return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK; -} -#define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 -#define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 -static inline unsigned int A6XX_CP_REG_TEST_0_BIT(unsigned int val) -{ - return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK; -} -#define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000 -#define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000 -#define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT 26 -static inline unsigned int A6XX_CP_REG_TEST_0_PRED_BIT(unsigned int val) -{ - return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK; -} -#define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000 - -#define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001 - -#define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002 - -#define REG_CP_COND_REG_EXEC_0 0x00000000 -#define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff -#define CP_COND_REG_EXEC_0_REG0__SHIFT 0 -static inline unsigned int CP_COND_REG_EXEC_0_REG0(unsigned int val) -{ - return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK; -} -#define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000 -#define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT 18 -static inline unsigned int CP_COND_REG_EXEC_0_PRED_BIT(unsigned int val) -{ - return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK; -} -#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000 -#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000 -#define CP_COND_REG_EXEC_0_BINNING 0x02000000 -#define CP_COND_REG_EXEC_0_GMEM 0x04000000 -#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 -#define CP_COND_REG_EXEC_0_BV 0x02000000 -#define CP_COND_REG_EXEC_0_BR 0x04000000 -#define CP_COND_REG_EXEC_0_LPAC 0x08000000 -#define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 -#define CP_COND_REG_EXEC_0_MODE__SHIFT 28 -static inline unsigned int CP_COND_REG_EXEC_0_MODE(enum compare_mode val) -{ - return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; -} - -#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001 -#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff -#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 -static inline unsigned int PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(unsigned int val) -{ - return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK; -} - -#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001 -#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff -#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0 -static inline unsigned int REG_COMPARE_CP_COND_REG_EXEC_1_REG1(unsigned int val) -{ - return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK; -} -#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000 - -#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001 -#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff -#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 -static inline unsigned int RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(unsigned int val) -{ - return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; -} - -#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001 -#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff -#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0 -static inline unsigned int REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(unsigned int val) -{ - return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK; -} - -#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001 -#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff -#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 -static inline unsigned int THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(unsigned int val) -{ - return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; -} - -#define REG_CP_COND_REG_EXEC_2 0x00000002 -#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff -#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0 -static inline unsigned int CP_COND_REG_EXEC_2_DWORDS(unsigned int val) -{ - return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK; -} - -#define REG_CP_COND_EXEC_0 0x00000000 -#define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff -#define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0 -static inline unsigned int CP_COND_EXEC_0_ADDR0_LO(unsigned int val) -{ - return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK; -} - -#define REG_CP_COND_EXEC_1 0x00000001 -#define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff -#define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0 -static inline unsigned int CP_COND_EXEC_1_ADDR0_HI(unsigned int val) -{ - return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK; -} - -#define REG_CP_COND_EXEC_2 0x00000002 -#define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff -#define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0 -static inline unsigned int CP_COND_EXEC_2_ADDR1_LO(unsigned int val) -{ - return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK; -} - -#define REG_CP_COND_EXEC_3 0x00000003 -#define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff -#define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0 -static inline unsigned int CP_COND_EXEC_3_ADDR1_HI(unsigned int val) -{ - return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK; -} - -#define REG_CP_COND_EXEC_4 0x00000004 -#define CP_COND_EXEC_4_REF__MASK 0xffffffff -#define CP_COND_EXEC_4_REF__SHIFT 0 -static inline unsigned int CP_COND_EXEC_4_REF(unsigned int val) -{ - return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK; -} - -#define REG_CP_COND_EXEC_5 0x00000005 -#define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff -#define CP_COND_EXEC_5_DWORDS__SHIFT 0 -static inline unsigned int CP_COND_EXEC_5_DWORDS(unsigned int val) -{ - return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK; -} - -#define REG_CP_SET_CTXSWITCH_IB_0 0x00000000 -#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff -#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0 -static inline unsigned int CP_SET_CTXSWITCH_IB_0_ADDR_LO(unsigned int val) -{ - return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK; -} - -#define REG_CP_SET_CTXSWITCH_IB_1 0x00000001 -#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff -#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0 -static inline unsigned int CP_SET_CTXSWITCH_IB_1_ADDR_HI(unsigned int val) -{ - return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK; -} - -#define REG_CP_SET_CTXSWITCH_IB_2 0x00000002 -#define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff -#define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0 -static inline unsigned int CP_SET_CTXSWITCH_IB_2_DWORDS(unsigned int val) -{ - return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK; -} -#define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000 -#define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20 -static inline unsigned int CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) -{ - return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK; -} - -#define REG_CP_REG_WRITE_0 0x00000000 -#define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f -#define CP_REG_WRITE_0_TRACKER__SHIFT 0 -static inline unsigned int CP_REG_WRITE_0_TRACKER(enum reg_tracker val) -{ - return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK; -} - -#define REG_CP_REG_WRITE_1 0x00000001 - -#define REG_CP_REG_WRITE_2 0x00000002 - -#define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000 -#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff -#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0 -static inline unsigned int CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(unsigned int val) -{ - return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK; -} - -#define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001 -#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff -#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0 -static inline unsigned int CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(unsigned int val) -{ - return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK; -} -#define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000 -#define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16 -static inline unsigned int CP_SMMU_TABLE_UPDATE_1_ASID(unsigned int val) -{ - return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK; -} - -#define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002 -#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff -#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0 -static inline unsigned int CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(unsigned int val) -{ - return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK; -} - -#define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003 -#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff -#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0 -static inline unsigned int CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(unsigned int val) -{ - return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK; -} - -#define REG_CP_START_BIN_BIN_COUNT 0x00000000 - -#define REG_CP_START_BIN_PREFIX_ADDR 0x00000001 - -#define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003 - -#define REG_CP_START_BIN_BODY_DWORDS 0x00000004 - -#define REG_CP_WAIT_TIMESTAMP_0 0x00000000 -#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003 -#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0 -static inline unsigned int CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val) -{ - return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK; -} -#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010 -#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4 -static inline unsigned int CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val) -{ - return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK; -} - -#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001 - -#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001 - -#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003 - -#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004 - -#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000 -#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f -#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0 -static inline unsigned int CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val) -{ - return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK; -} - -#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001 -#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff -#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0 -static inline unsigned int CP_BV_BR_COUNT_OPS_1_BR_OFFSET(unsigned int val) -{ - return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK; -} - -#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000 -#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff -#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0 -static inline unsigned int CP_MODIFY_TIMESTAMP_0_ADD(unsigned int val) -{ - return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK; -} -#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000 -#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28 -static inline unsigned int CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val) -{ - return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK; -} - -#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000 -#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f -#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0 -static inline unsigned int CP_MEM_TO_SCRATCH_MEM_0_CNT(unsigned int val) -{ - return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK; -} - -#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001 -#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f -#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0 -static inline unsigned int CP_MEM_TO_SCRATCH_MEM_1_OFFSET(unsigned int val) -{ - return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK; -} - -#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002 -#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff -#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0 -static inline unsigned int CP_MEM_TO_SCRATCH_MEM_2_SRC(unsigned int val) -{ - return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK; -} - -#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003 -#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff -#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0 -static inline unsigned int CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(unsigned int val) -{ - return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK; -} - -#define REG_CP_THREAD_CONTROL_0 0x00000000 -#define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003 -#define CP_THREAD_CONTROL_0_THREAD__SHIFT 0 -static inline unsigned int CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) -{ - return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK; -} -#define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000 -#define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000 - -#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000 - -#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002 -#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff -#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0 -static inline unsigned int CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(unsigned int val) -{ - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK; -} -#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000 -#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20 -static inline unsigned int CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(unsigned int val) -{ - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK; -} - -#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003 -#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff -#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0 -static inline unsigned int CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(unsigned int val) -{ - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK; -} - -#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000 -#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001 -#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002 -#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004 - -enum chip { - A2XX = 2, - A3XX = 3, - A4XX = 4, - A5XX = 5, - A6XX = 6, - A7XX = 7, -}; - -enum adreno_pa_su_sc_draw { - PC_DRAW_POINTS = 0, - PC_DRAW_LINES = 1, - PC_DRAW_TRIANGLES = 2, -}; - -enum adreno_compare_func { - FUNC_NEVER = 0, - FUNC_LESS = 1, - FUNC_EQUAL = 2, - FUNC_LEQUAL = 3, - FUNC_GREATER = 4, - FUNC_NOTEQUAL = 5, - FUNC_GEQUAL = 6, - FUNC_ALWAYS = 7, -}; - -enum adreno_stencil_op { - STENCIL_KEEP = 0, - STENCIL_ZERO = 1, - STENCIL_REPLACE = 2, - STENCIL_INCR_CLAMP = 3, - STENCIL_DECR_CLAMP = 4, - STENCIL_INVERT = 5, - STENCIL_INCR_WRAP = 6, - STENCIL_DECR_WRAP = 7, -}; - -enum adreno_rb_blend_factor { - FACTOR_ZERO = 0, - FACTOR_ONE = 1, - FACTOR_SRC_COLOR = 4, - FACTOR_ONE_MINUS_SRC_COLOR = 5, - FACTOR_SRC_ALPHA = 6, - FACTOR_ONE_MINUS_SRC_ALPHA = 7, - FACTOR_DST_COLOR = 8, - FACTOR_ONE_MINUS_DST_COLOR = 9, - FACTOR_DST_ALPHA = 10, - FACTOR_ONE_MINUS_DST_ALPHA = 11, - FACTOR_CONSTANT_COLOR = 12, - FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, - FACTOR_CONSTANT_ALPHA = 14, - FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, - FACTOR_SRC_ALPHA_SATURATE = 16, - FACTOR_SRC1_COLOR = 20, - FACTOR_ONE_MINUS_SRC1_COLOR = 21, - FACTOR_SRC1_ALPHA = 22, - FACTOR_ONE_MINUS_SRC1_ALPHA = 23, -}; - -enum adreno_rb_surface_endian { - ENDIAN_NONE = 0, - ENDIAN_8IN16 = 1, - ENDIAN_8IN32 = 2, - ENDIAN_16IN32 = 3, - ENDIAN_8IN64 = 4, - ENDIAN_8IN128 = 5, -}; - -enum adreno_rb_dither_mode { - DITHER_DISABLE = 0, - DITHER_ALWAYS = 1, - DITHER_IF_ALPHA_OFF = 2, -}; - -enum adreno_rb_depth_format { - DEPTHX_16 = 0, - DEPTHX_24_8 = 1, - DEPTHX_32 = 2, -}; - -enum adreno_rb_copy_control_mode { - RB_COPY_RESOLVE = 1, - RB_COPY_CLEAR = 2, - RB_COPY_DEPTH_STENCIL = 5, -}; - -enum a3xx_rop_code { - ROP_CLEAR = 0, - ROP_NOR = 1, - ROP_AND_INVERTED = 2, - ROP_COPY_INVERTED = 3, - ROP_AND_REVERSE = 4, - ROP_INVERT = 5, - ROP_XOR = 6, - ROP_NAND = 7, - ROP_AND = 8, - ROP_EQUIV = 9, - ROP_NOOP = 10, - ROP_OR_INVERTED = 11, - ROP_COPY = 12, - ROP_OR_REVERSE = 13, - ROP_OR = 14, - ROP_SET = 15, -}; - -enum a3xx_render_mode { - RB_RENDERING_PASS = 0, - RB_TILING_PASS = 1, - RB_RESOLVE_PASS = 2, - RB_COMPUTE_PASS = 3, -}; - -enum a3xx_msaa_samples { - MSAA_ONE = 0, - MSAA_TWO = 1, - MSAA_FOUR = 2, - MSAA_EIGHT = 3, -}; - -enum a3xx_threadmode { - MULTI = 0, - SINGLE = 1, -}; - -enum a3xx_instrbuffermode { - CACHE = 0, - BUFFER = 1, -}; - -enum a3xx_threadsize { - TWO_QUADS = 0, - FOUR_QUADS = 1, -}; - -enum a3xx_color_swap { - WZYX = 0, - WXYZ = 1, - ZYXW = 2, - XYZW = 3, -}; - -enum a3xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, -}; - -enum a4xx_tess_spacing { - EQUAL_SPACING = 0, - ODD_SPACING = 2, - EVEN_SPACING = 3, -}; - -enum a5xx_address_mode { - ADDR_32B = 0, - ADDR_64B = 1, -}; - -enum a5xx_line_mode { - BRESENHAM = 0, - RECTANGULAR = 1, -}; - -enum a6xx_tex_prefetch_cmd { - TEX_PREFETCH_UNK0 = 0, - TEX_PREFETCH_SAM = 1, - TEX_PREFETCH_GATHER4R = 2, - TEX_PREFETCH_GATHER4G = 3, - TEX_PREFETCH_GATHER4B = 4, - TEX_PREFETCH_GATHER4A = 5, - TEX_PREFETCH_UNK6 = 6, - TEX_PREFETCH_UNK7 = 7, -}; - -#define REG_AXXX_CP_RB_BASE 0x000001c0 - -#define REG_AXXX_CP_RB_CNTL 0x000001c1 -#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f -#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 -static inline unsigned int AXXX_CP_RB_CNTL_BUFSZ(unsigned int val) -{ - return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; -} -#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 -#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 -static inline unsigned int AXXX_CP_RB_CNTL_BLKSZ(unsigned int val) -{ - return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; -} -#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 -#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 -static inline unsigned int AXXX_CP_RB_CNTL_BUF_SWAP(unsigned int val) -{ - return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; -} -#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 -#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 -#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 - -#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 -#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 -#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 -static inline unsigned int AXXX_CP_RB_RPTR_ADDR_SWAP(unsigned int val) -{ - return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; -} -#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc -#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 -static inline unsigned int AXXX_CP_RB_RPTR_ADDR_ADDR(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; -} - -#define REG_AXXX_CP_RB_RPTR 0x000001c4 - -#define REG_AXXX_CP_RB_WPTR 0x000001c5 - -#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 - -#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 - -#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 - -#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 -static inline unsigned int AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(unsigned int val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; -} -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 -static inline unsigned int AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(unsigned int val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; -} -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 -#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 -static inline unsigned int AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(unsigned int val) -{ - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; -} - -#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 -#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 -#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 -static inline unsigned int AXXX_CP_MEQ_THRESHOLDS_MEQ_END(unsigned int val) -{ - return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; -} -#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 -#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 -static inline unsigned int AXXX_CP_MEQ_THRESHOLDS_ROQ_END(unsigned int val) -{ - return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; -} - -#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 -#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f -#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 -static inline unsigned int AXXX_CP_CSQ_AVAIL_RING(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; -} -#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 -#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 -static inline unsigned int AXXX_CP_CSQ_AVAIL_IB1(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; -} -#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 -#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 -static inline unsigned int AXXX_CP_CSQ_AVAIL_IB2(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; -} - -#define REG_AXXX_CP_STQ_AVAIL 0x000001d8 -#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f -#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 -static inline unsigned int AXXX_CP_STQ_AVAIL_ST(unsigned int val) -{ - return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; -} - -#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 -#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f -#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 -static inline unsigned int AXXX_CP_MEQ_AVAIL_MEQ(unsigned int val) -{ - return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; -} - -#define REG_AXXX_SCRATCH_UMSK 0x000001dc -#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff -#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 -static inline unsigned int AXXX_SCRATCH_UMSK_UMSK(unsigned int val) -{ - return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; -} -#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 -#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 -static inline unsigned int AXXX_SCRATCH_UMSK_SWAP(unsigned int val) -{ - return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; -} - -#define REG_AXXX_SCRATCH_ADDR 0x000001dd - -#define REG_AXXX_CP_ME_RDADDR 0x000001ea - -#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec - -#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed - -#define REG_AXXX_CP_INT_CNTL 0x000001f2 -#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 -#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 -#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 -#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 -#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 -#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 -#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 -#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 -#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 - -#define REG_AXXX_CP_INT_STATUS 0x000001f3 - -#define REG_AXXX_CP_INT_ACK 0x000001f4 - -#define REG_AXXX_CP_ME_CNTL 0x000001f6 -#define AXXX_CP_ME_CNTL_BUSY 0x20000000 -#define AXXX_CP_ME_CNTL_HALT 0x10000000 - -#define REG_AXXX_CP_ME_STATUS 0x000001f7 - -#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 - -#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 - -#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa - -#define REG_AXXX_CP_DEBUG 0x000001fc -#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 -#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 -#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 -#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 -#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 -#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 -#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 -#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 - -#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd -#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 -static inline unsigned int AXXX_CP_CSQ_RB_STAT_RPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 -static inline unsigned int AXXX_CP_CSQ_RB_STAT_WPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe -#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 -static inline unsigned int AXXX_CP_CSQ_IB1_STAT_RPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 -static inline unsigned int AXXX_CP_CSQ_IB1_STAT_WPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff -#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f -#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 -static inline unsigned int AXXX_CP_CSQ_IB2_STAT_RPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; -} -#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 -#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 -static inline unsigned int AXXX_CP_CSQ_IB2_STAT_WPTR(unsigned int val) -{ - return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; -} - -#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 - -#define REG_AXXX_CP_STQ_ST_STAT 0x00000443 - -#define REG_AXXX_CP_ST_BASE 0x0000044d - -#define REG_AXXX_CP_ST_BUFSZ 0x0000044e - -#define REG_AXXX_CP_MEQ_STAT 0x0000044f - -#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 - -#define REG_AXXX_CP_BIN_MASK_LO 0x00000454 - -#define REG_AXXX_CP_BIN_MASK_HI 0x00000455 - -#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 - -#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 - -#define REG_AXXX_CP_IB1_BASE 0x00000458 - -#define REG_AXXX_CP_IB1_BUFSZ 0x00000459 - -#define REG_AXXX_CP_IB2_BASE 0x0000045a - -#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b - -#define REG_AXXX_CP_STAT 0x0000047f -#define AXXX_CP_STAT_CP_BUSY 0x80000000 -#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 -#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 -#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 -#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 -#define AXXX_CP_STAT_ME_BUSY 0x04000000 -#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 -#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 -#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 -#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 -#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 -#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 -#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 -#define AXXX_CP_STAT_PFP_BUSY 0x00020000 -#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 -#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 -#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 -#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 -#define AXXX_CP_STAT_CSF_BUSY 0x00000400 -#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 -#define AXXX_CP_STAT_EVENT_BUSY 0x00000100 -#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 -#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 -#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 -#define AXXX_CP_STAT_RCIU_BUSY 0x00000010 -#define AXXX_CP_STAT_RBIU_BUSY 0x00000008 -#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 -#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 -#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 - -#define REG_AXXX_CP_SCRATCH_REG0 0x00000578 - -#define REG_AXXX_CP_SCRATCH_REG1 0x00000579 - -#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a - -#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b - -#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c - -#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d - -#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e - -#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f - -#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 - -#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 - -#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 - -#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 - -#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 - -#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 - -#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 - -#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 - -#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 - -#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 - -#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a - -#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b - -#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c - -#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d - -#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 - -#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 - -enum a6xx_tile_mode { - TILE6_LINEAR = 0, - TILE6_2 = 2, - TILE6_3 = 3, -}; - -enum a6xx_format { - FMT6_A8_UNORM = 2, - FMT6_8_UNORM = 3, - FMT6_8_SNORM = 4, - FMT6_8_UINT = 5, - FMT6_8_SINT = 6, - FMT6_4_4_4_4_UNORM = 8, - FMT6_5_5_5_1_UNORM = 10, - FMT6_1_5_5_5_UNORM = 12, - FMT6_5_6_5_UNORM = 14, - FMT6_8_8_UNORM = 15, - FMT6_8_8_SNORM = 16, - FMT6_8_8_UINT = 17, - FMT6_8_8_SINT = 18, - FMT6_L8_A8_UNORM = 19, - FMT6_16_UNORM = 21, - FMT6_16_SNORM = 22, - FMT6_16_FLOAT = 23, - FMT6_16_UINT = 24, - FMT6_16_SINT = 25, - FMT6_8_8_8_UNORM = 33, - FMT6_8_8_8_SNORM = 34, - FMT6_8_8_8_UINT = 35, - FMT6_8_8_8_SINT = 36, - FMT6_8_8_8_8_UNORM = 48, - FMT6_8_8_8_X8_UNORM = 49, - FMT6_8_8_8_8_SNORM = 50, - FMT6_8_8_8_8_UINT = 51, - FMT6_8_8_8_8_SINT = 52, - FMT6_9_9_9_E5_FLOAT = 53, - FMT6_10_10_10_2_UNORM = 54, - FMT6_10_10_10_2_UNORM_DEST = 55, - FMT6_10_10_10_2_SNORM = 57, - FMT6_10_10_10_2_UINT = 58, - FMT6_10_10_10_2_SINT = 59, - FMT6_11_11_10_FLOAT = 66, - FMT6_16_16_UNORM = 67, - FMT6_16_16_SNORM = 68, - FMT6_16_16_FLOAT = 69, - FMT6_16_16_UINT = 70, - FMT6_16_16_SINT = 71, - FMT6_32_UNORM = 72, - FMT6_32_SNORM = 73, - FMT6_32_FLOAT = 74, - FMT6_32_UINT = 75, - FMT6_32_SINT = 76, - FMT6_32_FIXED = 77, - FMT6_16_16_16_UNORM = 88, - FMT6_16_16_16_SNORM = 89, - FMT6_16_16_16_FLOAT = 90, - FMT6_16_16_16_UINT = 91, - FMT6_16_16_16_SINT = 92, - FMT6_16_16_16_16_UNORM = 96, - FMT6_16_16_16_16_SNORM = 97, - FMT6_16_16_16_16_FLOAT = 98, - FMT6_16_16_16_16_UINT = 99, - FMT6_16_16_16_16_SINT = 100, - FMT6_32_32_UNORM = 101, - FMT6_32_32_SNORM = 102, - FMT6_32_32_FLOAT = 103, - FMT6_32_32_UINT = 104, - FMT6_32_32_SINT = 105, - FMT6_32_32_FIXED = 106, - FMT6_32_32_32_UNORM = 112, - FMT6_32_32_32_SNORM = 113, - FMT6_32_32_32_UINT = 114, - FMT6_32_32_32_SINT = 115, - FMT6_32_32_32_FLOAT = 116, - FMT6_32_32_32_FIXED = 117, - FMT6_32_32_32_32_UNORM = 128, - FMT6_32_32_32_32_SNORM = 129, - FMT6_32_32_32_32_FLOAT = 130, - FMT6_32_32_32_32_UINT = 131, - FMT6_32_32_32_32_SINT = 132, - FMT6_32_32_32_32_FIXED = 133, - FMT6_G8R8B8R8_422_UNORM = 140, - FMT6_R8G8R8B8_422_UNORM = 141, - FMT6_R8_G8B8_2PLANE_420_UNORM = 142, - FMT6_NV21 = 143, - FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, - FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, - FMT6_NV12_Y = 148, - FMT6_NV12_UV = 149, - FMT6_NV12_VU = 150, - FMT6_NV12_4R = 151, - FMT6_NV12_4R_Y = 152, - FMT6_NV12_4R_UV = 153, - FMT6_P010 = 154, - FMT6_P010_Y = 155, - FMT6_P010_UV = 156, - FMT6_TP10 = 157, - FMT6_TP10_Y = 158, - FMT6_TP10_UV = 159, - FMT6_Z24_UNORM_S8_UINT = 160, - FMT6_ETC2_RG11_UNORM = 171, - FMT6_ETC2_RG11_SNORM = 172, - FMT6_ETC2_R11_UNORM = 173, - FMT6_ETC2_R11_SNORM = 174, - FMT6_ETC1 = 175, - FMT6_ETC2_RGB8 = 176, - FMT6_ETC2_RGBA8 = 177, - FMT6_ETC2_RGB8A1 = 178, - FMT6_DXT1 = 179, - FMT6_DXT3 = 180, - FMT6_DXT5 = 181, - FMT6_RGTC1_UNORM = 183, - FMT6_RGTC1_SNORM = 184, - FMT6_RGTC2_UNORM = 187, - FMT6_RGTC2_SNORM = 188, - FMT6_BPTC_UFLOAT = 190, - FMT6_BPTC_FLOAT = 191, - FMT6_BPTC = 192, - FMT6_ASTC_4x4 = 193, - FMT6_ASTC_5x4 = 194, - FMT6_ASTC_5x5 = 195, - FMT6_ASTC_6x5 = 196, - FMT6_ASTC_6x6 = 197, - FMT6_ASTC_8x5 = 198, - FMT6_ASTC_8x6 = 199, - FMT6_ASTC_8x8 = 200, - FMT6_ASTC_10x5 = 201, - FMT6_ASTC_10x6 = 202, - FMT6_ASTC_10x8 = 203, - FMT6_ASTC_10x10 = 204, - FMT6_ASTC_12x10 = 205, - FMT6_ASTC_12x12 = 206, - FMT6_Z24_UINT_S8_UINT = 234, - FMT6_NONE = 255, -}; - -enum a6xx_polygon_mode { - POLYMODE6_POINTS = 1, - POLYMODE6_LINES = 2, - POLYMODE6_TRIANGLES = 3, -}; - -enum a6xx_depth_format { - DEPTH6_NONE = 0, - DEPTH6_16 = 1, - DEPTH6_24_8 = 2, - DEPTH6_32 = 4, -}; - -enum a6xx_shader_id { - A6XX_TP0_TMO_DATA = 9, - A6XX_TP0_SMO_DATA = 10, - A6XX_TP0_MIPMAP_BASE_DATA = 11, - A6XX_TP1_TMO_DATA = 25, - A6XX_TP1_SMO_DATA = 26, - A6XX_TP1_MIPMAP_BASE_DATA = 27, - A6XX_SP_INST_DATA = 41, - A6XX_SP_LB_0_DATA = 42, - A6XX_SP_LB_1_DATA = 43, - A6XX_SP_LB_2_DATA = 44, - A6XX_SP_LB_3_DATA = 45, - A6XX_SP_LB_4_DATA = 46, - A6XX_SP_LB_5_DATA = 47, - A6XX_SP_CB_BINDLESS_DATA = 48, - A6XX_SP_CB_LEGACY_DATA = 49, - A6XX_SP_UAV_DATA = 50, - A6XX_SP_INST_TAG = 51, - A6XX_SP_CB_BINDLESS_TAG = 52, - A6XX_SP_TMO_UMO_TAG = 53, - A6XX_SP_SMO_TAG = 54, - A6XX_SP_STATE_DATA = 55, - A6XX_HLSQ_CHUNK_CVS_RAM = 73, - A6XX_HLSQ_CHUNK_CPS_RAM = 74, - A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, - A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, - A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, - A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, - A6XX_HLSQ_CVS_MISC_RAM = 80, - A6XX_HLSQ_CPS_MISC_RAM = 81, - A6XX_HLSQ_INST_RAM = 82, - A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, - A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, - A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, - A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, - A6XX_HLSQ_INST_RAM_TAG = 87, - A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, - A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, - A6XX_HLSQ_PWR_REST_RAM = 90, - A6XX_HLSQ_PWR_REST_TAG = 91, - A6XX_HLSQ_DATAPATH_META = 96, - A6XX_HLSQ_FRONTEND_META = 97, - A6XX_HLSQ_INDIRECT_META = 98, - A6XX_HLSQ_BACKEND_META = 99, - A6XX_SP_LB_6_DATA = 112, - A6XX_SP_LB_7_DATA = 113, - A6XX_HLSQ_INST_RAM_1 = 115, -}; - -enum a7xx_statetype_id { - A7XX_TP0_NCTX_REG = 0, - A7XX_TP0_CTX0_3D_CVS_REG = 1, - A7XX_TP0_CTX0_3D_CPS_REG = 2, - A7XX_TP0_CTX1_3D_CVS_REG = 3, - A7XX_TP0_CTX1_3D_CPS_REG = 4, - A7XX_TP0_CTX2_3D_CPS_REG = 5, - A7XX_TP0_CTX3_3D_CPS_REG = 6, - A7XX_TP0_TMO_DATA = 9, - A7XX_TP0_SMO_DATA = 10, - A7XX_TP0_MIPMAP_BASE_DATA = 11, - A7XX_SP_NCTX_REG = 32, - A7XX_SP_CTX0_3D_CVS_REG = 33, - A7XX_SP_CTX0_3D_CPS_REG = 34, - A7XX_SP_CTX1_3D_CVS_REG = 35, - A7XX_SP_CTX1_3D_CPS_REG = 36, - A7XX_SP_CTX2_3D_CPS_REG = 37, - A7XX_SP_CTX3_3D_CPS_REG = 38, - A7XX_SP_INST_DATA = 39, - A7XX_SP_INST_DATA_1 = 40, - A7XX_SP_LB_0_DATA = 41, - A7XX_SP_LB_1_DATA = 42, - A7XX_SP_LB_2_DATA = 43, - A7XX_SP_LB_3_DATA = 44, - A7XX_SP_LB_4_DATA = 45, - A7XX_SP_LB_5_DATA = 46, - A7XX_SP_LB_6_DATA = 47, - A7XX_SP_LB_7_DATA = 48, - A7XX_SP_CB_RAM = 49, - A7XX_SP_LB_13_DATA = 50, - A7XX_SP_LB_14_DATA = 51, - A7XX_SP_INST_TAG = 52, - A7XX_SP_INST_DATA_2 = 53, - A7XX_SP_TMO_TAG = 54, - A7XX_SP_SMO_TAG = 55, - A7XX_SP_STATE_DATA = 56, - A7XX_SP_HWAVE_RAM = 57, - A7XX_SP_L0_INST_BUF = 58, - A7XX_SP_LB_8_DATA = 59, - A7XX_SP_LB_9_DATA = 60, - A7XX_SP_LB_10_DATA = 61, - A7XX_SP_LB_11_DATA = 62, - A7XX_SP_LB_12_DATA = 63, - A7XX_HLSQ_DATAPATH_DSTR_META = 64, - A7XX_HLSQ_L2STC_TAG_RAM = 67, - A7XX_HLSQ_L2STC_INFO_CMD = 68, - A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69, - A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70, - A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71, - A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72, - A7XX_HLSQ_CHUNK_CVS_RAM = 73, - A7XX_HLSQ_CHUNK_CPS_RAM = 74, - A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, - A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, - A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, - A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, - A7XX_HLSQ_CVS_MISC_RAM = 79, - A7XX_HLSQ_CPS_MISC_RAM = 80, - A7XX_HLSQ_CPS_MISC_RAM_1 = 81, - A7XX_HLSQ_INST_RAM = 82, - A7XX_HLSQ_GFX_CVS_CONST_RAM = 83, - A7XX_HLSQ_GFX_CPS_CONST_RAM = 84, - A7XX_HLSQ_CVS_MISC_RAM_TAG = 85, - A7XX_HLSQ_CPS_MISC_RAM_TAG = 86, - A7XX_HLSQ_INST_RAM_TAG = 87, - A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, - A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, - A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90, - A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91, - A7XX_HLSQ_INST_RAM_1 = 92, - A7XX_HLSQ_STPROC_META = 93, - A7XX_HLSQ_BV_BE_META = 94, - A7XX_HLSQ_INST_RAM_2 = 95, - A7XX_HLSQ_DATAPATH_META = 96, - A7XX_HLSQ_FRONTEND_META = 97, - A7XX_HLSQ_INDIRECT_META = 98, - A7XX_HLSQ_BACKEND_META = 99, -}; - -enum a6xx_debugbus_id { - A6XX_DBGBUS_CP = 1, - A6XX_DBGBUS_RBBM = 2, - A6XX_DBGBUS_VBIF = 3, - A6XX_DBGBUS_HLSQ = 4, - A6XX_DBGBUS_UCHE = 5, - A6XX_DBGBUS_DPM = 6, - A6XX_DBGBUS_TESS = 7, - A6XX_DBGBUS_PC = 8, - A6XX_DBGBUS_VFDP = 9, - A6XX_DBGBUS_VPC = 10, - A6XX_DBGBUS_TSE = 11, - A6XX_DBGBUS_RAS = 12, - A6XX_DBGBUS_VSC = 13, - A6XX_DBGBUS_COM = 14, - A6XX_DBGBUS_LRZ = 16, - A6XX_DBGBUS_A2D = 17, - A6XX_DBGBUS_CCUFCHE = 18, - A6XX_DBGBUS_GMU_CX = 19, - A6XX_DBGBUS_RBP = 20, - A6XX_DBGBUS_DCS = 21, - A6XX_DBGBUS_DBGC = 22, - A6XX_DBGBUS_CX = 23, - A6XX_DBGBUS_GMU_GX = 24, - A6XX_DBGBUS_TPFCHE = 25, - A6XX_DBGBUS_GBIF_GX = 26, - A6XX_DBGBUS_GPC = 29, - A6XX_DBGBUS_LARC = 30, - A6XX_DBGBUS_HLSQ_SPTP = 31, - A6XX_DBGBUS_RB_0 = 32, - A6XX_DBGBUS_RB_1 = 33, - A6XX_DBGBUS_RB_2 = 34, - A6XX_DBGBUS_UCHE_WRAPPER = 36, - A6XX_DBGBUS_CCU_0 = 40, - A6XX_DBGBUS_CCU_1 = 41, - A6XX_DBGBUS_CCU_2 = 42, - A6XX_DBGBUS_VFD_0 = 56, - A6XX_DBGBUS_VFD_1 = 57, - A6XX_DBGBUS_VFD_2 = 58, - A6XX_DBGBUS_VFD_3 = 59, - A6XX_DBGBUS_VFD_4 = 60, - A6XX_DBGBUS_VFD_5 = 61, - A6XX_DBGBUS_SP_0 = 64, - A6XX_DBGBUS_SP_1 = 65, - A6XX_DBGBUS_SP_2 = 66, - A6XX_DBGBUS_TPL1_0 = 72, - A6XX_DBGBUS_TPL1_1 = 73, - A6XX_DBGBUS_TPL1_2 = 74, - A6XX_DBGBUS_TPL1_3 = 75, - A6XX_DBGBUS_TPL1_4 = 76, - A6XX_DBGBUS_TPL1_5 = 77, - A6XX_DBGBUS_SPTP_0 = 88, - A6XX_DBGBUS_SPTP_1 = 89, - A6XX_DBGBUS_SPTP_2 = 90, - A6XX_DBGBUS_SPTP_3 = 91, - A6XX_DBGBUS_SPTP_4 = 92, - A6XX_DBGBUS_SPTP_5 = 93, -}; - -enum a7xx_state_location { - A7XX_HLSQ_STATE = 0, - A7XX_HLSQ_DP = 1, - A7XX_SP_TOP = 2, - A7XX_USPTP = 3, - A7XX_HLSQ_DP_STR = 4, -}; - -enum a7xx_pipe { - A7XX_PIPE_NONE = 0, - A7XX_PIPE_BR = 1, - A7XX_PIPE_BV = 2, - A7XX_PIPE_LPAC = 3, -}; - -enum a7xx_cluster { - A7XX_CLUSTER_NONE = 0, - A7XX_CLUSTER_FE = 1, - A7XX_CLUSTER_SP_VS = 2, - A7XX_CLUSTER_PC_VS = 3, - A7XX_CLUSTER_GRAS = 4, - A7XX_CLUSTER_SP_PS = 5, - A7XX_CLUSTER_VPC_PS = 6, - A7XX_CLUSTER_PS = 7, -}; - -enum a7xx_debugbus_id { - A7XX_DBGBUS_CP_0_0 = 1, - A7XX_DBGBUS_CP_0_1 = 2, - A7XX_DBGBUS_RBBM = 3, - A7XX_DBGBUS_GBIF_GX = 5, - A7XX_DBGBUS_GBIF_CX = 6, - A7XX_DBGBUS_HLSQ = 7, - A7XX_DBGBUS_UCHE_0 = 9, - A7XX_DBGBUS_UCHE_1 = 10, - A7XX_DBGBUS_TESS_BR = 13, - A7XX_DBGBUS_TESS_BV = 14, - A7XX_DBGBUS_PC_BR = 17, - A7XX_DBGBUS_PC_BV = 18, - A7XX_DBGBUS_VFDP_BR = 21, - A7XX_DBGBUS_VFDP_BV = 22, - A7XX_DBGBUS_VPC_BR = 25, - A7XX_DBGBUS_VPC_BV = 26, - A7XX_DBGBUS_TSE_BR = 29, - A7XX_DBGBUS_TSE_BV = 30, - A7XX_DBGBUS_RAS_BR = 33, - A7XX_DBGBUS_RAS_BV = 34, - A7XX_DBGBUS_VSC = 37, - A7XX_DBGBUS_COM_0 = 39, - A7XX_DBGBUS_LRZ_BR = 43, - A7XX_DBGBUS_LRZ_BV = 44, - A7XX_DBGBUS_UFC_0 = 47, - A7XX_DBGBUS_UFC_1 = 48, - A7XX_DBGBUS_GMU_GX = 55, - A7XX_DBGBUS_DBGC = 59, - A7XX_DBGBUS_CX = 60, - A7XX_DBGBUS_GMU_CX = 61, - A7XX_DBGBUS_GPC_BR = 62, - A7XX_DBGBUS_GPC_BV = 63, - A7XX_DBGBUS_LARC = 66, - A7XX_DBGBUS_HLSQ_SPTP = 68, - A7XX_DBGBUS_RB_0 = 70, - A7XX_DBGBUS_RB_1 = 71, - A7XX_DBGBUS_RB_2 = 72, - A7XX_DBGBUS_RB_3 = 73, - A7XX_DBGBUS_RB_4 = 74, - A7XX_DBGBUS_RB_5 = 75, - A7XX_DBGBUS_UCHE_WRAPPER = 102, - A7XX_DBGBUS_CCU_0 = 106, - A7XX_DBGBUS_CCU_1 = 107, - A7XX_DBGBUS_CCU_2 = 108, - A7XX_DBGBUS_CCU_3 = 109, - A7XX_DBGBUS_CCU_4 = 110, - A7XX_DBGBUS_CCU_5 = 111, - A7XX_DBGBUS_VFD_BR_0 = 138, - A7XX_DBGBUS_VFD_BR_1 = 139, - A7XX_DBGBUS_VFD_BR_2 = 140, - A7XX_DBGBUS_VFD_BR_3 = 141, - A7XX_DBGBUS_VFD_BR_4 = 142, - A7XX_DBGBUS_VFD_BR_5 = 143, - A7XX_DBGBUS_VFD_BR_6 = 144, - A7XX_DBGBUS_VFD_BR_7 = 145, - A7XX_DBGBUS_VFD_BV_0 = 202, - A7XX_DBGBUS_VFD_BV_1 = 203, - A7XX_DBGBUS_VFD_BV_2 = 204, - A7XX_DBGBUS_VFD_BV_3 = 205, - A7XX_DBGBUS_USP_0 = 234, - A7XX_DBGBUS_USP_1 = 235, - A7XX_DBGBUS_USP_2 = 236, - A7XX_DBGBUS_USP_3 = 237, - A7XX_DBGBUS_USP_4 = 238, - A7XX_DBGBUS_USP_5 = 239, - A7XX_DBGBUS_TP_0 = 266, - A7XX_DBGBUS_TP_1 = 267, - A7XX_DBGBUS_TP_2 = 268, - A7XX_DBGBUS_TP_3 = 269, - A7XX_DBGBUS_TP_4 = 270, - A7XX_DBGBUS_TP_5 = 271, - A7XX_DBGBUS_TP_6 = 272, - A7XX_DBGBUS_TP_7 = 273, - A7XX_DBGBUS_TP_8 = 274, - A7XX_DBGBUS_TP_9 = 275, - A7XX_DBGBUS_TP_10 = 276, - A7XX_DBGBUS_TP_11 = 277, - A7XX_DBGBUS_USPTP_0 = 330, - A7XX_DBGBUS_USPTP_1 = 331, - A7XX_DBGBUS_USPTP_2 = 332, - A7XX_DBGBUS_USPTP_3 = 333, - A7XX_DBGBUS_USPTP_4 = 334, - A7XX_DBGBUS_USPTP_5 = 335, - A7XX_DBGBUS_USPTP_6 = 336, - A7XX_DBGBUS_USPTP_7 = 337, - A7XX_DBGBUS_USPTP_8 = 338, - A7XX_DBGBUS_USPTP_9 = 339, - A7XX_DBGBUS_USPTP_10 = 340, - A7XX_DBGBUS_USPTP_11 = 341, - A7XX_DBGBUS_CCHE_0 = 396, - A7XX_DBGBUS_CCHE_1 = 397, - A7XX_DBGBUS_CCHE_2 = 398, - A7XX_DBGBUS_VPC_DSTR_0 = 408, - A7XX_DBGBUS_VPC_DSTR_1 = 409, - A7XX_DBGBUS_VPC_DSTR_2 = 410, - A7XX_DBGBUS_HLSQ_DP_STR_0 = 411, - A7XX_DBGBUS_HLSQ_DP_STR_1 = 412, - A7XX_DBGBUS_HLSQ_DP_STR_2 = 413, - A7XX_DBGBUS_HLSQ_DP_STR_3 = 414, - A7XX_DBGBUS_HLSQ_DP_STR_4 = 415, - A7XX_DBGBUS_HLSQ_DP_STR_5 = 416, - A7XX_DBGBUS_UFC_DSTR_0 = 443, - A7XX_DBGBUS_UFC_DSTR_1 = 444, - A7XX_DBGBUS_UFC_DSTR_2 = 445, - A7XX_DBGBUS_CGC_SUBCORE = 446, - A7XX_DBGBUS_CGC_CORE = 447, -}; - -enum a6xx_cp_perfcounter_select { - PERF_CP_ALWAYS_COUNT = 0, - PERF_CP_BUSY_GFX_CORE_IDLE = 1, - PERF_CP_BUSY_CYCLES = 2, - PERF_CP_NUM_PREEMPTIONS = 3, - PERF_CP_PREEMPTION_REACTION_DELAY = 4, - PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, - PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, - PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, - PERF_CP_PREDICATED_DRAWS_KILLED = 8, - PERF_CP_MODE_SWITCH = 9, - PERF_CP_ZPASS_DONE = 10, - PERF_CP_CONTEXT_DONE = 11, - PERF_CP_CACHE_FLUSH = 12, - PERF_CP_LONG_PREEMPTIONS = 13, - PERF_CP_SQE_I_CACHE_STARVE = 14, - PERF_CP_SQE_IDLE = 15, - PERF_CP_SQE_PM4_STARVE_RB_IB = 16, - PERF_CP_SQE_PM4_STARVE_SDS = 17, - PERF_CP_SQE_MRB_STARVE = 18, - PERF_CP_SQE_RRB_STARVE = 19, - PERF_CP_SQE_VSD_STARVE = 20, - PERF_CP_VSD_DECODE_STARVE = 21, - PERF_CP_SQE_PIPE_OUT_STALL = 22, - PERF_CP_SQE_SYNC_STALL = 23, - PERF_CP_SQE_PM4_WFI_STALL = 24, - PERF_CP_SQE_SYS_WFI_STALL = 25, - PERF_CP_SQE_T4_EXEC = 26, - PERF_CP_SQE_LOAD_STATE_EXEC = 27, - PERF_CP_SQE_SAVE_SDS_STATE = 28, - PERF_CP_SQE_DRAW_EXEC = 29, - PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, - PERF_CP_SQE_EXEC_PROFILED = 31, - PERF_CP_MEMORY_POOL_EMPTY = 32, - PERF_CP_MEMORY_POOL_SYNC_STALL = 33, - PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, - PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, - PERF_CP_AHB_STALL_SQE_GMU = 36, - PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, - PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, - PERF_CP_CLUSTER0_EMPTY = 39, - PERF_CP_CLUSTER1_EMPTY = 40, - PERF_CP_CLUSTER2_EMPTY = 41, - PERF_CP_CLUSTER3_EMPTY = 42, - PERF_CP_CLUSTER4_EMPTY = 43, - PERF_CP_CLUSTER5_EMPTY = 44, - PERF_CP_PM4_DATA = 45, - PERF_CP_PM4_HEADERS = 46, - PERF_CP_VBIF_READ_BEATS = 47, - PERF_CP_VBIF_WRITE_BEATS = 48, - PERF_CP_SQE_INSTR_COUNTER = 49, -}; - -enum a6xx_rbbm_perfcounter_select { - PERF_RBBM_ALWAYS_COUNT = 0, - PERF_RBBM_ALWAYS_ON = 1, - PERF_RBBM_TSE_BUSY = 2, - PERF_RBBM_RAS_BUSY = 3, - PERF_RBBM_PC_DCALL_BUSY = 4, - PERF_RBBM_PC_VSD_BUSY = 5, - PERF_RBBM_STATUS_MASKED = 6, - PERF_RBBM_COM_BUSY = 7, - PERF_RBBM_DCOM_BUSY = 8, - PERF_RBBM_VBIF_BUSY = 9, - PERF_RBBM_VSC_BUSY = 10, - PERF_RBBM_TESS_BUSY = 11, - PERF_RBBM_UCHE_BUSY = 12, - PERF_RBBM_HLSQ_BUSY = 13, -}; - -enum a6xx_pc_perfcounter_select { - PERF_PC_BUSY_CYCLES = 0, - PERF_PC_WORKING_CYCLES = 1, - PERF_PC_STALL_CYCLES_VFD = 2, - PERF_PC_STALL_CYCLES_TSE = 3, - PERF_PC_STALL_CYCLES_VPC = 4, - PERF_PC_STALL_CYCLES_UCHE = 5, - PERF_PC_STALL_CYCLES_TESS = 6, - PERF_PC_STALL_CYCLES_TSE_ONLY = 7, - PERF_PC_STALL_CYCLES_VPC_ONLY = 8, - PERF_PC_PASS1_TF_STALL_CYCLES = 9, - PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, - PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, - PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, - PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, - PERF_PC_STARVE_CYCLES_DI = 14, - PERF_PC_VIS_STREAMS_LOADED = 15, - PERF_PC_INSTANCES = 16, - PERF_PC_VPC_PRIMITIVES = 17, - PERF_PC_DEAD_PRIM = 18, - PERF_PC_LIVE_PRIM = 19, - PERF_PC_VERTEX_HITS = 20, - PERF_PC_IA_VERTICES = 21, - PERF_PC_IA_PRIMITIVES = 22, - PERF_PC_GS_PRIMITIVES = 23, - PERF_PC_HS_INVOCATIONS = 24, - PERF_PC_DS_INVOCATIONS = 25, - PERF_PC_VS_INVOCATIONS = 26, - PERF_PC_GS_INVOCATIONS = 27, - PERF_PC_DS_PRIMITIVES = 28, - PERF_PC_VPC_POS_DATA_TRANSACTION = 29, - PERF_PC_3D_DRAWCALLS = 30, - PERF_PC_2D_DRAWCALLS = 31, - PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, - PERF_TESS_BUSY_CYCLES = 33, - PERF_TESS_WORKING_CYCLES = 34, - PERF_TESS_STALL_CYCLES_PC = 35, - PERF_TESS_STARVE_CYCLES_PC = 36, - PERF_PC_TSE_TRANSACTION = 37, - PERF_PC_TSE_VERTEX = 38, - PERF_PC_TESS_PC_UV_TRANS = 39, - PERF_PC_TESS_PC_UV_PATCHES = 40, - PERF_PC_TESS_FACTOR_TRANS = 41, -}; - -enum a6xx_vfd_perfcounter_select { - PERF_VFD_BUSY_CYCLES = 0, - PERF_VFD_STALL_CYCLES_UCHE = 1, - PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, - PERF_VFD_STALL_CYCLES_SP_INFO = 3, - PERF_VFD_STALL_CYCLES_SP_ATTR = 4, - PERF_VFD_STARVE_CYCLES_UCHE = 5, - PERF_VFD_RBUFFER_FULL = 6, - PERF_VFD_ATTR_INFO_FIFO_FULL = 7, - PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, - PERF_VFD_NUM_ATTRIBUTES = 9, - PERF_VFD_UPPER_SHADER_FIBERS = 10, - PERF_VFD_LOWER_SHADER_FIBERS = 11, - PERF_VFD_MODE_0_FIBERS = 12, - PERF_VFD_MODE_1_FIBERS = 13, - PERF_VFD_MODE_2_FIBERS = 14, - PERF_VFD_MODE_3_FIBERS = 15, - PERF_VFD_MODE_4_FIBERS = 16, - PERF_VFD_TOTAL_VERTICES = 17, - PERF_VFDP_STALL_CYCLES_VFD = 18, - PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, - PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, - PERF_VFDP_STARVE_CYCLES_PC = 21, - PERF_VFDP_VS_STAGE_WAVES = 22, -}; - -enum a6xx_hlsq_perfcounter_select { - PERF_HLSQ_BUSY_CYCLES = 0, - PERF_HLSQ_STALL_CYCLES_UCHE = 1, - PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, - PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, - PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, - PERF_HLSQ_UCHE_LATENCY_COUNT = 5, - PERF_HLSQ_FS_STAGE_1X_WAVES = 6, - PERF_HLSQ_FS_STAGE_2X_WAVES = 7, - PERF_HLSQ_QUADS = 8, - PERF_HLSQ_CS_INVOCATIONS = 9, - PERF_HLSQ_COMPUTE_DRAWCALLS = 10, - PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, - PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, - PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, - PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, - PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, - PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, - PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, - PERF_HLSQ_STALL_CYCLES_VPC = 18, - PERF_HLSQ_PIXELS = 19, - PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, -}; - -enum a6xx_vpc_perfcounter_select { - PERF_VPC_BUSY_CYCLES = 0, - PERF_VPC_WORKING_CYCLES = 1, - PERF_VPC_STALL_CYCLES_UCHE = 2, - PERF_VPC_STALL_CYCLES_VFD_WACK = 3, - PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, - PERF_VPC_STALL_CYCLES_PC = 5, - PERF_VPC_STALL_CYCLES_SP_LM = 6, - PERF_VPC_STARVE_CYCLES_SP = 7, - PERF_VPC_STARVE_CYCLES_LRZ = 8, - PERF_VPC_PC_PRIMITIVES = 9, - PERF_VPC_SP_COMPONENTS = 10, - PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, - PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, - PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, - PERF_VPC_LM_TRANSACTION = 14, - PERF_VPC_STREAMOUT_TRANSACTION = 15, - PERF_VPC_VS_BUSY_CYCLES = 16, - PERF_VPC_PS_BUSY_CYCLES = 17, - PERF_VPC_VS_WORKING_CYCLES = 18, - PERF_VPC_PS_WORKING_CYCLES = 19, - PERF_VPC_STARVE_CYCLES_RB = 20, - PERF_VPC_NUM_VPCRAM_READ_POS = 21, - PERF_VPC_WIT_FULL_CYCLES = 22, - PERF_VPC_VPCRAM_FULL_CYCLES = 23, - PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, - PERF_VPC_NUM_VPCRAM_WRITE = 25, - PERF_VPC_NUM_VPCRAM_READ_SO = 26, - PERF_VPC_NUM_ATTR_REQ_LM = 27, -}; - -enum a6xx_tse_perfcounter_select { - PERF_TSE_BUSY_CYCLES = 0, - PERF_TSE_CLIPPING_CYCLES = 1, - PERF_TSE_STALL_CYCLES_RAS = 2, - PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, - PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, - PERF_TSE_STARVE_CYCLES_PC = 5, - PERF_TSE_INPUT_PRIM = 6, - PERF_TSE_INPUT_NULL_PRIM = 7, - PERF_TSE_TRIVAL_REJ_PRIM = 8, - PERF_TSE_CLIPPED_PRIM = 9, - PERF_TSE_ZERO_AREA_PRIM = 10, - PERF_TSE_FACENESS_CULLED_PRIM = 11, - PERF_TSE_ZERO_PIXEL_PRIM = 12, - PERF_TSE_OUTPUT_NULL_PRIM = 13, - PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, - PERF_TSE_CINVOCATION = 15, - PERF_TSE_CPRIMITIVES = 16, - PERF_TSE_2D_INPUT_PRIM = 17, - PERF_TSE_2D_ALIVE_CYCLES = 18, - PERF_TSE_CLIP_PLANES = 19, -}; - -enum a6xx_ras_perfcounter_select { - PERF_RAS_BUSY_CYCLES = 0, - PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, - PERF_RAS_STALL_CYCLES_LRZ = 2, - PERF_RAS_STARVE_CYCLES_TSE = 3, - PERF_RAS_SUPER_TILES = 4, - PERF_RAS_8X4_TILES = 5, - PERF_RAS_MASKGEN_ACTIVE = 6, - PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, - PERF_RAS_FULLY_COVERED_8X4_TILES = 8, - PERF_RAS_PRIM_KILLED_INVISILBE = 9, - PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, - PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, - PERF_RAS_BLOCKS = 12, -}; - -enum a6xx_uche_perfcounter_select { - PERF_UCHE_BUSY_CYCLES = 0, - PERF_UCHE_STALL_CYCLES_ARBITER = 1, - PERF_UCHE_VBIF_LATENCY_CYCLES = 2, - PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, - PERF_UCHE_VBIF_READ_BEATS_TP = 4, - PERF_UCHE_VBIF_READ_BEATS_VFD = 5, - PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, - PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, - PERF_UCHE_VBIF_READ_BEATS_SP = 8, - PERF_UCHE_READ_REQUESTS_TP = 9, - PERF_UCHE_READ_REQUESTS_VFD = 10, - PERF_UCHE_READ_REQUESTS_HLSQ = 11, - PERF_UCHE_READ_REQUESTS_LRZ = 12, - PERF_UCHE_READ_REQUESTS_SP = 13, - PERF_UCHE_WRITE_REQUESTS_LRZ = 14, - PERF_UCHE_WRITE_REQUESTS_SP = 15, - PERF_UCHE_WRITE_REQUESTS_VPC = 16, - PERF_UCHE_WRITE_REQUESTS_VSC = 17, - PERF_UCHE_EVICTS = 18, - PERF_UCHE_BANK_REQ0 = 19, - PERF_UCHE_BANK_REQ1 = 20, - PERF_UCHE_BANK_REQ2 = 21, - PERF_UCHE_BANK_REQ3 = 22, - PERF_UCHE_BANK_REQ4 = 23, - PERF_UCHE_BANK_REQ5 = 24, - PERF_UCHE_BANK_REQ6 = 25, - PERF_UCHE_BANK_REQ7 = 26, - PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, - PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, - PERF_UCHE_GMEM_READ_BEATS = 29, - PERF_UCHE_TPH_REF_FULL = 30, - PERF_UCHE_TPH_VICTIM_FULL = 31, - PERF_UCHE_TPH_EXT_FULL = 32, - PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, - PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, - PERF_UCHE_DCMP_LATENCY_CYCLES = 35, - PERF_UCHE_VBIF_READ_BEATS_PC = 36, - PERF_UCHE_READ_REQUESTS_PC = 37, - PERF_UCHE_RAM_READ_REQ = 38, - PERF_UCHE_RAM_WRITE_REQ = 39, -}; - -enum a6xx_tp_perfcounter_select { - PERF_TP_BUSY_CYCLES = 0, - PERF_TP_STALL_CYCLES_UCHE = 1, - PERF_TP_LATENCY_CYCLES = 2, - PERF_TP_LATENCY_TRANS = 3, - PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, - PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, - PERF_TP_L1_CACHELINE_REQUESTS = 6, - PERF_TP_L1_CACHELINE_MISSES = 7, - PERF_TP_SP_TP_TRANS = 8, - PERF_TP_TP_SP_TRANS = 9, - PERF_TP_OUTPUT_PIXELS = 10, - PERF_TP_FILTER_WORKLOAD_16BIT = 11, - PERF_TP_FILTER_WORKLOAD_32BIT = 12, - PERF_TP_QUADS_RECEIVED = 13, - PERF_TP_QUADS_OFFSET = 14, - PERF_TP_QUADS_SHADOW = 15, - PERF_TP_QUADS_ARRAY = 16, - PERF_TP_QUADS_GRADIENT = 17, - PERF_TP_QUADS_1D = 18, - PERF_TP_QUADS_2D = 19, - PERF_TP_QUADS_BUFFER = 20, - PERF_TP_QUADS_3D = 21, - PERF_TP_QUADS_CUBE = 22, - PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, - PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, - PERF_TP_OUTPUT_PIXELS_POINT = 25, - PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, - PERF_TP_OUTPUT_PIXELS_MIP = 27, - PERF_TP_OUTPUT_PIXELS_ANISO = 28, - PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, - PERF_TP_FLAG_CACHE_REQUESTS = 30, - PERF_TP_FLAG_CACHE_MISSES = 31, - PERF_TP_L1_5_L2_REQUESTS = 32, - PERF_TP_2D_OUTPUT_PIXELS = 33, - PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, - PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, - PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, - PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, - PERF_TP_TPA2TPC_TRANS = 38, - PERF_TP_L1_MISSES_ASTC_1TILE = 39, - PERF_TP_L1_MISSES_ASTC_2TILE = 40, - PERF_TP_L1_MISSES_ASTC_4TILE = 41, - PERF_TP_L1_5_L2_COMPRESS_REQS = 42, - PERF_TP_L1_5_L2_COMPRESS_MISS = 43, - PERF_TP_L1_BANK_CONFLICT = 44, - PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, - PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, - PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, - PERF_TP_FRONTEND_WORKING_CYCLES = 48, - PERF_TP_L1_TAG_WORKING_CYCLES = 49, - PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, - PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, - PERF_TP_BACKEND_WORKING_CYCLES = 52, - PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, - PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, - PERF_TP_STARVE_CYCLES_SP = 55, - PERF_TP_STARVE_CYCLES_UCHE = 56, -}; - -enum a6xx_sp_perfcounter_select { - PERF_SP_BUSY_CYCLES = 0, - PERF_SP_ALU_WORKING_CYCLES = 1, - PERF_SP_EFU_WORKING_CYCLES = 2, - PERF_SP_STALL_CYCLES_VPC = 3, - PERF_SP_STALL_CYCLES_TP = 4, - PERF_SP_STALL_CYCLES_UCHE = 5, - PERF_SP_STALL_CYCLES_RB = 6, - PERF_SP_NON_EXECUTION_CYCLES = 7, - PERF_SP_WAVE_CONTEXTS = 8, - PERF_SP_WAVE_CONTEXT_CYCLES = 9, - PERF_SP_FS_STAGE_WAVE_CYCLES = 10, - PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, - PERF_SP_VS_STAGE_WAVE_CYCLES = 12, - PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, - PERF_SP_FS_STAGE_DURATION_CYCLES = 14, - PERF_SP_VS_STAGE_DURATION_CYCLES = 15, - PERF_SP_WAVE_CTRL_CYCLES = 16, - PERF_SP_WAVE_LOAD_CYCLES = 17, - PERF_SP_WAVE_EMIT_CYCLES = 18, - PERF_SP_WAVE_NOP_CYCLES = 19, - PERF_SP_WAVE_WAIT_CYCLES = 20, - PERF_SP_WAVE_FETCH_CYCLES = 21, - PERF_SP_WAVE_IDLE_CYCLES = 22, - PERF_SP_WAVE_END_CYCLES = 23, - PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, - PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, - PERF_SP_WAVE_JOIN_CYCLES = 26, - PERF_SP_LM_LOAD_INSTRUCTIONS = 27, - PERF_SP_LM_STORE_INSTRUCTIONS = 28, - PERF_SP_LM_ATOMICS = 29, - PERF_SP_GM_LOAD_INSTRUCTIONS = 30, - PERF_SP_GM_STORE_INSTRUCTIONS = 31, - PERF_SP_GM_ATOMICS = 32, - PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, - PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, - PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, - PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, - PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, - PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, - PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, - PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, - PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, - PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, - PERF_SP_VS_INSTRUCTIONS = 43, - PERF_SP_FS_INSTRUCTIONS = 44, - PERF_SP_ADDR_LOCK_COUNT = 45, - PERF_SP_UCHE_READ_TRANS = 46, - PERF_SP_UCHE_WRITE_TRANS = 47, - PERF_SP_EXPORT_VPC_TRANS = 48, - PERF_SP_EXPORT_RB_TRANS = 49, - PERF_SP_PIXELS_KILLED = 50, - PERF_SP_ICL1_REQUESTS = 51, - PERF_SP_ICL1_MISSES = 52, - PERF_SP_HS_INSTRUCTIONS = 53, - PERF_SP_DS_INSTRUCTIONS = 54, - PERF_SP_GS_INSTRUCTIONS = 55, - PERF_SP_CS_INSTRUCTIONS = 56, - PERF_SP_GPR_READ = 57, - PERF_SP_GPR_WRITE = 58, - PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, - PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, - PERF_SP_LM_BANK_CONFLICTS = 61, - PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, - PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, - PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, - PERF_SP_LM_WORKING_CYCLES = 65, - PERF_SP_DISPATCHER_WORKING_CYCLES = 66, - PERF_SP_SEQUENCER_WORKING_CYCLES = 67, - PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, - PERF_SP_STARVE_CYCLES_HLSQ = 69, - PERF_SP_NON_EXECUTION_LS_CYCLES = 70, - PERF_SP_WORKING_EU = 71, - PERF_SP_ANY_EU_WORKING = 72, - PERF_SP_WORKING_EU_FS_STAGE = 73, - PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, - PERF_SP_WORKING_EU_VS_STAGE = 75, - PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, - PERF_SP_WORKING_EU_CS_STAGE = 77, - PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, - PERF_SP_GPR_READ_PREFETCH = 79, - PERF_SP_GPR_READ_CONFLICT = 80, - PERF_SP_GPR_WRITE_CONFLICT = 81, - PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, - PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, - PERF_SP_EXECUTABLE_WAVES = 84, -}; - -enum a6xx_rb_perfcounter_select { - PERF_RB_BUSY_CYCLES = 0, - PERF_RB_STALL_CYCLES_HLSQ = 1, - PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, - PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, - PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, - PERF_RB_STARVE_CYCLES_SP = 5, - PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, - PERF_RB_STARVE_CYCLES_CCU = 7, - PERF_RB_STARVE_CYCLES_Z_PLANE = 8, - PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, - PERF_RB_Z_WORKLOAD = 10, - PERF_RB_HLSQ_ACTIVE = 11, - PERF_RB_Z_READ = 12, - PERF_RB_Z_WRITE = 13, - PERF_RB_C_READ = 14, - PERF_RB_C_WRITE = 15, - PERF_RB_TOTAL_PASS = 16, - PERF_RB_Z_PASS = 17, - PERF_RB_Z_FAIL = 18, - PERF_RB_S_FAIL = 19, - PERF_RB_BLENDED_FXP_COMPONENTS = 20, - PERF_RB_BLENDED_FP16_COMPONENTS = 21, - PERF_RB_PS_INVOCATIONS = 22, - PERF_RB_2D_ALIVE_CYCLES = 23, - PERF_RB_2D_STALL_CYCLES_A2D = 24, - PERF_RB_2D_STARVE_CYCLES_SRC = 25, - PERF_RB_2D_STARVE_CYCLES_SP = 26, - PERF_RB_2D_STARVE_CYCLES_DST = 27, - PERF_RB_2D_VALID_PIXELS = 28, - PERF_RB_3D_PIXELS = 29, - PERF_RB_BLENDER_WORKING_CYCLES = 30, - PERF_RB_ZPROC_WORKING_CYCLES = 31, - PERF_RB_CPROC_WORKING_CYCLES = 32, - PERF_RB_SAMPLER_WORKING_CYCLES = 33, - PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, - PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, - PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, - PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, - PERF_RB_STALL_CYCLES_VPC = 38, - PERF_RB_2D_INPUT_TRANS = 39, - PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, - PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, - PERF_RB_BLENDED_FP32_COMPONENTS = 42, - PERF_RB_COLOR_PIX_TILES = 43, - PERF_RB_STALL_CYCLES_CCU = 44, - PERF_RB_EARLY_Z_ARB3_GRANT = 45, - PERF_RB_LATE_Z_ARB3_GRANT = 46, - PERF_RB_EARLY_Z_SKIP_GRANT = 47, -}; - -enum a6xx_vsc_perfcounter_select { - PERF_VSC_BUSY_CYCLES = 0, - PERF_VSC_WORKING_CYCLES = 1, - PERF_VSC_STALL_CYCLES_UCHE = 2, - PERF_VSC_EOT_NUM = 3, - PERF_VSC_INPUT_TILES = 4, -}; - -enum a6xx_ccu_perfcounter_select { - PERF_CCU_BUSY_CYCLES = 0, - PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, - PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, - PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, - PERF_CCU_DEPTH_BLOCKS = 4, - PERF_CCU_COLOR_BLOCKS = 5, - PERF_CCU_DEPTH_BLOCK_HIT = 6, - PERF_CCU_COLOR_BLOCK_HIT = 7, - PERF_CCU_PARTIAL_BLOCK_READ = 8, - PERF_CCU_GMEM_READ = 9, - PERF_CCU_GMEM_WRITE = 10, - PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, - PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, - PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, - PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, - PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, - PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, - PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, - PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, - PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, - PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, - PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, - PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, - PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, - PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, - PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, - PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, - PERF_CCU_2D_RD_REQ = 27, - PERF_CCU_2D_WR_REQ = 28, -}; - -enum a6xx_lrz_perfcounter_select { - PERF_LRZ_BUSY_CYCLES = 0, - PERF_LRZ_STARVE_CYCLES_RAS = 1, - PERF_LRZ_STALL_CYCLES_RB = 2, - PERF_LRZ_STALL_CYCLES_VSC = 3, - PERF_LRZ_STALL_CYCLES_VPC = 4, - PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, - PERF_LRZ_STALL_CYCLES_UCHE = 6, - PERF_LRZ_LRZ_READ = 7, - PERF_LRZ_LRZ_WRITE = 8, - PERF_LRZ_READ_LATENCY = 9, - PERF_LRZ_MERGE_CACHE_UPDATING = 10, - PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, - PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, - PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, - PERF_LRZ_FULL_8X8_TILES = 14, - PERF_LRZ_PARTIAL_8X8_TILES = 15, - PERF_LRZ_TILE_KILLED = 16, - PERF_LRZ_TOTAL_PIXEL = 17, - PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, - PERF_LRZ_FULLY_COVERED_TILES = 19, - PERF_LRZ_PARTIAL_COVERED_TILES = 20, - PERF_LRZ_FEEDBACK_ACCEPT = 21, - PERF_LRZ_FEEDBACK_DISCARD = 22, - PERF_LRZ_FEEDBACK_STALL = 23, - PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, - PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, - PERF_LRZ_STALL_CYCLES_VC = 26, - PERF_LRZ_RAS_MASK_TRANS = 27, -}; - -enum a6xx_cmp_perfcounter_select { - PERF_CMPDECMP_STALL_CYCLES_ARB = 0, - PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, - PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, - PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, - PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, - PERF_CMPDECMP_VBIF_READ_REQUEST = 5, - PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, - PERF_CMPDECMP_VBIF_READ_DATA = 7, - PERF_CMPDECMP_VBIF_WRITE_DATA = 8, - PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, - PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, - PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, - PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, - PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, - PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, - PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, - PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, - PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, - PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, - PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, - PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, - PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, - PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, - PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, - PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, - PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, - PERF_CMPDECMP_2D_RD_DATA = 28, - PERF_CMPDECMP_2D_WR_DATA = 29, - PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, - PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, - PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, - PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, - PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, - PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, - PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, - PERF_CMPDECMP_2D_BUSY_CYCLES = 37, - PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, - PERF_CMPDECMP_2D_PIXELS = 39, -}; - -enum a6xx_2d_ifmt { - R2D_UNORM8 = 16, - R2D_INT32 = 7, - R2D_INT16 = 6, - R2D_INT8 = 5, - R2D_FLOAT32 = 4, - R2D_FLOAT16 = 3, - R2D_UNORM8_SRGB = 1, - R2D_RAW = 0, -}; - -enum a6xx_ztest_mode { - A6XX_EARLY_Z = 0, - A6XX_LATE_Z = 1, - A6XX_EARLY_LRZ_LATE_Z = 2, - A6XX_INVALID_ZTEST = 3, -}; - -enum a6xx_tess_spacing { - TESS_EQUAL = 0, - TESS_FRACTIONAL_ODD = 2, - TESS_FRACTIONAL_EVEN = 3, -}; - -enum a6xx_tess_output { - TESS_POINTS = 0, - TESS_LINES = 1, - TESS_CW_TRIS = 2, - TESS_CCW_TRIS = 3, -}; - -enum a7xx_cp_perfcounter_select { - A7XX_PERF_CP_NEVER_COUNT = 0, - A7XX_PERF_CP_ALWAYS_COUNT = 1, - A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = 2, - A7XX_PERF_CP_BUSY_CYCLES = 3, - A7XX_PERF_CP_NUM_PREEMPTIONS = 4, - A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = 5, - A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 6, - A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = 7, - A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 8, - A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = 9, - A7XX_PERF_CP_MODE_SWITCH = 10, - A7XX_PERF_CP_ZPASS_DONE = 11, - A7XX_PERF_CP_CONTEXT_DONE = 12, - A7XX_PERF_CP_CACHE_FLUSH = 13, - A7XX_PERF_CP_LONG_PREEMPTIONS = 14, - A7XX_PERF_CP_SQE_I_CACHE_STARVE = 15, - A7XX_PERF_CP_SQE_IDLE = 16, - A7XX_PERF_CP_SQE_PM4_STARVE_RB = 17, - A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = 18, - A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = 19, - A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = 20, - A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = 21, - A7XX_PERF_CP_SQE_PM4_STARVE_SDS = 22, - A7XX_PERF_CP_SQE_MRB_STARVE = 23, - A7XX_PERF_CP_SQE_RRB_STARVE = 24, - A7XX_PERF_CP_SQE_VSD_STARVE = 25, - A7XX_PERF_CP_VSD_DECODE_STARVE = 26, - A7XX_PERF_CP_SQE_PIPE_OUT_STALL = 27, - A7XX_PERF_CP_SQE_SYNC_STALL = 28, - A7XX_PERF_CP_SQE_PM4_WFI_STALL = 29, - A7XX_PERF_CP_SQE_SYS_WFI_STALL = 30, - A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = 31, - A7XX_PERF_CP_OUTPUT_BLOCKED = 32, - A7XX_PERF_CP_SQE_T4_EXEC = 33, - A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = 34, - A7XX_PERF_CP_SQE_SAVE_SDS_STATE = 35, - A7XX_PERF_CP_SQE_DRAW_EXEC = 36, - A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 37, - A7XX_PERF_CP_SQE_EXEC_PROFILED = 38, - A7XX_PERF_CP_MEMORY_POOL_EMPTY = 39, - A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = 40, - A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = 41, - A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = 42, - A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = 43, - A7XX_PERF_CP_AHB_STALL_SQE_GMU = 44, - A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = 45, - A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = 46, - A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = 47, - A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = 48, - A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = 49, - A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = 50, - A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = 51, - A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = 52, - A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = 53, - A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = 54, - A7XX_PERF_CP_CLUSTER_PS_EMPTY = 55, - A7XX_PERF_CP_PM4_DATA = 56, - A7XX_PERF_CP_PM4_HEADERS = 57, - A7XX_PERF_CP_VBIF_READ_BEATS = 58, - A7XX_PERF_CP_VBIF_WRITE_BEATS = 59, - A7XX_PERF_CP_SQE_INSTR_COUNTER = 60, - A7XX_PERF_CP_CLUSTER_FE_US_FULL = 61, - A7XX_PERF_CP_CLUSTER_FE_S_FULL = 62, - A7XX_PERF_CP_CLUSTER_SP_VS_FULL = 63, - A7XX_PERF_CP_CLUSTER_VPC_US_FULL = 64, - A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = 65, - A7XX_PERF_CP_CLUSTER_GRAS_FULL = 66, - A7XX_PERF_CP_CLUSTER_SP_PS_FULL = 67, - A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = 68, - A7XX_PERF_CP_CLUSTER_PS_FULL = 69, - A7XX_PERF_CP_ICACHE_MISSES = 70, - A7XX_PERF_CP_ICACHE_HITS = 71, - A7XX_PERF_CP_ICACHE_STALL = 72, - A7XX_PERF_CP_DCACHE_MISSES = 73, - A7XX_PERF_CP_DCACHE_HITS = 74, - A7XX_PERF_CP_DCACHE_STALLS = 75, - A7XX_PERF_CP_AQE_SQE_STALL = 76, - A7XX_PERF_CP_SQE_AQE_STARVE = 77, - A7XX_PERF_CP_ISR_CYCLES = 78, - A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = 79, - A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = 80, - A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = 81, - A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = 82, - A7XX_PERF_CP_S_SKEW_BUFFER_FULL = 83, - A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = 84, -}; - -enum a7xx_rbbm_perfcounter_select { - A7XX_PERF_RBBM_NEVER_COUNT = 0, - A7XX_PERF_RBBM_US_ALWAYS_COUNT = 1, - A7XX_PERF_RBBM_US_ALWAYS_ON = 2, - A7XX_PERF_RBBM_US_STATUS_MASKED = 3, - A7XX_PERF_RBBM_US_PC_BUSY = 4, - A7XX_PERF_RBBM_US_COM_BUSY = 5, - A7XX_PERF_RBBM_US_DCOM_BUSY = 6, - A7XX_PERF_RBBM_US_VBIF_BUSY = 7, - A7XX_PERF_RBBM_US_VSC_BUSY = 8, - A7XX_PERF_RBBM_US_UCHE_BUSY = 9, - A7XX_PERF_RBBM_US_HLSQ_BUSY = 10, - A7XX_PERF_RBBM_S_HLSQ_BUSY = 11, - A7XX_PERF_RBBM_S_PC_BUSY = 12, - A7XX_PERF_RBBM_S_TESS_BUSY = 13, - A7XX_PERF_RBBM_S_TSEFE_BUSY = 14, - A7XX_PERF_RBBM_S_TSEBE_BUSY = 15, - A7XX_PERF_RBBM_S_RAS_BUSY = 16, -}; - -enum a7xx_pc_perfcounter_select { - A7XX_PERF_PC_NEVER_COUNT = 0, - A7XX_PERF_PC_US_BUSY_CYCLES = 1, - A7XX_PERF_PC_US_WORKING_CYCLES = 2, - A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = 3, - A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = 4, - A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = 5, - A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = 6, - A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = 7, - A7XX_PERF_PC_US_STARVE_CYCLES_DI = 8, - A7XX_PERF_PC_US_VIS_STREAMS_LOADED = 9, - A7XX_PERF_PC_US_INSTANCES = 10, - A7XX_PERF_PC_US_DEAD_PRIM = 11, - A7XX_PERF_PC_US_SLICE_LIVE_PRIM = 12, - A7XX_PERF_PC_US_3D_DRAWCALLS = 13, - A7XX_PERF_PC_US_2D_DRAWCALLS = 14, - A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = 15, - A7XX_PERF_PC_US_MESH_DRAWS = 16, - A7XX_PERF_PC_US_MESH_DEAD_DRAWS = 17, - A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = 18, - A7XX_PERF_PC_US_MESH_DEAD_PRIM = 19, - A7XX_PERF_PC_US_MESH_LIVE_PRIM = 20, - A7XX_PERF_PC_US_MESH_PA_EN_PRIM = 21, - A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = 22, - A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = 23, - A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = 24, - A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = 25, - A7XX_PERF_PC_US_PREDRAW_STALLS = 26, - A7XX_PERF_PC_US_DP0_INPUT_STALLS = 27, - A7XX_PERF_PC_US_DP1_INPUT_STALLS = 28, - A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = 29, - A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = 30, - A7XX_PERF_PC_US_PASSPAIR_STALL = 31, - A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = 32, - A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = 33, - A7XX_PERF_PC_US_UCHE_0_TRANS = 34, - A7XX_PERF_PC_US_UCHE_1_TRANS = 35, - A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = 36, - A7XX_PERF_PC_US_BV_STARVED_BY_RARB = 37, - A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = 38, - A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = 39, - A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = 40, - A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = 41, - A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = 42, - A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = 43, - A7XX_PERF_PC_US_DP0_RARB_FULL = 44, - A7XX_PERF_PC_US_DP1_RARB_FULL = 45, - A7XX_PERF_PC_US_DP0_LIVE_PRIM = 46, - A7XX_PERF_PC_US_DP1_LIVE_PRIM = 47, - A7XX_PERF_PC_US_BV2BR_SWITCH = 48, - A7XX_PERF_PC_US_BR2BV_SWITCH = 49, - A7XX_PERF_PC_US_STALL_CYCLES_PC_S = 50, - A7XX_PERF_PC_RESERVED_51 = 51, - A7XX_PERF_PC_RESERVED_52 = 52, - A7XX_PERF_PC_RESERVED_53 = 53, - A7XX_PERF_PC_RESERVED_54 = 54, - A7XX_PERF_PC_RESERVED_55 = 55, - A7XX_PERF_PC_RESERVED_56 = 56, - A7XX_PERF_PC_RESERVED_57 = 57, - A7XX_PERF_PC_RESERVED_58 = 58, - A7XX_PERF_PC_RESERVED_59 = 59, - A7XX_PERF_PC_S_BUSY_CYCLES = 60, - A7XX_PERF_PC_S_WORKING_CYCLES = 61, - A7XX_PERF_PC_S_STALL_CYCLES_VFD = 62, - A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = 63, - A7XX_PERF_PC_S_STALL_CYCLES_TESS = 64, - A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = 65, - A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = 66, - A7XX_PERF_PC_S_VPC_PRIMITIVES = 67, - A7XX_PERF_PC_S_VERTEX_HITS = 68, - A7XX_PERF_PC_S_IA_VERTICES = 69, - A7XX_PERF_PC_S_IA_PRIMITIVES = 70, - A7XX_PERF_PC_S_HS_INVOCATIONS = 71, - A7XX_PERF_PC_S_DS_INVOCATIONS = 72, - A7XX_PERF_PC_S_VS_INVOCATIONS = 73, - A7XX_PERF_PC_S_GS_INVOCATIONS = 74, - A7XX_PERF_PC_S_DS_PRIMITIVES = 75, - A7XX_PERF_PC_S_TESS_BUSY_CYCLES = 76, - A7XX_PERF_PC_S_TESS_WORKING_CYCLES = 77, - A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = 78, - A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = 79, - A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = 80, - A7XX_PERF_PC_S_TESS_PID_ACTIVE = 81, - A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = 82, - A7XX_PERF_PC_S_TESS_FACTOR_TRANS = 83, - A7XX_PERF_PC_S_TESS_PC_UV_TRANS = 84, - A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = 85, - A7XX_PERF_PC_S_MESH_VS_WAVES = 86, -}; - -enum a7xx_vfd_perfcounter_select { - A7XX_PERF_VFD_NEVER_COUNT = 0, - A7XX_PERF_VFD_BUSY_CYCLES = 1, - A7XX_PERF_VFD_STALL_CYCLES_UCHE = 2, - A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = 3, - A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = 4, - A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = 5, - A7XX_PERF_VFD_STARVE_CYCLES_UCHE = 6, - A7XX_PERF_VFD_RBUFFER_FULL = 7, - A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = 8, - A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = 9, - A7XX_PERF_VFD_NUM_ATTRIBUTES = 10, - A7XX_PERF_VFD_UPPER_SHADER_FIBERS = 11, - A7XX_PERF_VFD_LOWER_SHADER_FIBERS = 12, - A7XX_PERF_VFD_MODE_0_FIBERS = 13, - A7XX_PERF_VFD_MODE_1_FIBERS = 14, - A7XX_PERF_VFD_MODE_2_FIBERS = 15, - A7XX_PERF_VFD_MODE_3_FIBERS = 16, - A7XX_PERF_VFD_MODE_4_FIBERS = 17, - A7XX_PERF_VFD_TOTAL_VERTICES = 18, - A7XX_PERF_VFDP_STALL_CYCLES_VFD = 19, - A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = 20, - A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = 21, - A7XX_PERF_VFDP_STARVE_CYCLES_PC = 22, - A7XX_PERF_VFDP_VS_STAGE_WAVES = 23, - A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = 24, - A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = 25, -}; - -enum a7xx_hlsq_perfcounter_select { - A7XX_PERF_HLSQ_NEVER_COUNT = 0, - A7XX_PERF_HLSQ_BUSY_CYCLES = 1, - A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, - A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, - A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, - A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = 5, - A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = 6, - A7XX_PERF_HLSQ_RESERVED_7 = 7, - A7XX_PERF_HLSQ_RESERVED_8 = 8, - A7XX_PERF_HLSQ_RESERVED_9 = 9, - A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = 10, - A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, - A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, - A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, - A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, - A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, - A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, - A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, - A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = 18, - A7XX_PERF_HLSQ_RESERVED_19 = 19, - A7XX_PERF_HLSQ_RESERVED_20 = 20, - A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = 21, - A7XX_PERF_HLSQ_FS_STALL_CYCLES = 22, - A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = 23, - A7XX_PERF_HLSQ_BV_STALL_CYCLES = 24, - A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = 25, - A7XX_PERF_HLSQ_FS_DEREF_CYCLES = 26, - A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = 27, - A7XX_PERF_HLSQ_BV_DEREF_CYCLES = 28, - A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = 29, - A7XX_PERF_HLSQ_FS_S2W_CYCLES = 30, - A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = 31, - A7XX_PERF_HLSQ_BV_S2W_CYCLES = 32, - A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = 33, - A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = 34, - A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = 35, - A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = 36, - A7XX_PERF_HLSQ_RESERVED_37 = 37, - A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = 38, - A7XX_PERF_HLSQ_FS_STARVING_SP = 39, - A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = 40, - A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = 41, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = 42, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = 43, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = 44, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = 45, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = 46, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = 47, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = 48, - A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = 49, - A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = 50, - A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = 51, - A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = 52, - A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = 53, - A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = 54, - A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = 55, - A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = 56, - A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = 57, - A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = 58, - A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = 59, - A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = 60, - A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = 61, - A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = 62, - A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = 63, - A7XX_PERF_HLSQ_L2STC_REQ_SP = 64, - A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = 65, - A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = 66, - A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = 67, - A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = 68, - A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = 69, - A7XX_PERF_HLSQ_L2STC_REQ_UCHE = 70, - A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = 71, - A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = 72, - A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = 73, - A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = 74, - A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = 75, - A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = 76, - A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = 77, - A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = 78, - A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = 79, - A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = 80, - A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = 81, - A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = 82, - A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = 83, - A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = 84, - A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = 85, - A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = 86, - A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = 87, - A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = 88, - A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = 89, - A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = 90, - A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = 91, - A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = 92, - A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = 93, - A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = 94, - A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = 95, - A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = 96, - A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = 97, - A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = 98, - A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = 99, - A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = 100, - A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = 101, - A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = 102, - A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = 103, - A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = 104, - A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = 105, - A7XX_PERF_HLSQ_PRIMITIVE_COUNT = 106, - A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = 107, - A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = 108, - A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = 109, - A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = 110, - A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = 111, -}; - -enum a7xx_vpc_perfcounter_select { - A7XX_PERF_VPC_NEVER_COUNT = 0, - A7XX_PERF_VPC_FE_BUSY_CYCLES = 1, - A7XX_PERF_VPC_FE_WORKING_CYCLES = 2, - A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = 3, - A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = 4, - A7XX_PERF_VPC_FE_PC_PRIMITIVES = 5, - A7XX_PERF_VPC_FE_SP_COMPONENTS = 6, - A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = 7, - A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = 8, - A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = 9, - A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = 10, - A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = 11, - A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = 12, - A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = 13, - A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = 14, - A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = 15, - A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = 16, - A7XX_PERF_VPC_FE_GS_PRIMITIVES = 17, - A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = 18, - A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = 19, - A7XX_PERF_VPC_FE_NUM_WM_HIT = 20, - A7XX_PERF_VPC_FE_STALL_DQ_WACK = 21, - A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = 22, - A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = 23, - A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = 24, - A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = 25, - A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = 26, - A7XX_PERF_VPC_FE_BOTTLENECK = 27, - A7XX_PERF_VPC_US_BUSY_CYCLES = 28, - A7XX_PERF_VPC_US_WORKING_CYCLES = 29, - A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = 30, - A7XX_PERF_VPC_US_PTUS_FULL = 31, - A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = 32, - A7XX_PERF_VPC_US_STALL_CYCLES_VSC = 33, - A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = 34, - A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = 35, - A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = 36, - A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = 37, - A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = 38, - A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = 39, - A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = 40, - A7XX_PERF_VPC_US_BOTTLENECK = 41, - A7XX_PERF_VPC_RESERVED_42 = 42, - A7XX_PERF_VPC_RESERVED_43 = 43, - A7XX_PERF_VPC_RESERVED_44 = 44, - A7XX_PERF_VPC_BE_BUSY_CYCLES = 45, - A7XX_PERF_VPC_BE_WORKING_CYCLES = 46, - A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = 47, - A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = 48, - A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = 49, - A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = 50, - A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = 51, - A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = 52, - A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = 53, - A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = 54, - A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = 55, - A7XX_PERF_VPC_BE_NUM_PA_REQ = 56, - A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = 57, - A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = 58, - A7XX_PERF_VPC_BE_LM_TRANSACTION = 59, - A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = 60, - A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = 61, - A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = 62, - A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = 63, - A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = 64, - A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = 65, - A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = 66, - A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = 67, - A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = 68, - A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = 69, - A7XX_PERF_VPC_BE_BOTTLENECK = 70, -}; - -enum a7xx_tse_perfcounter_select { - A7XX_PERF_TSE_NEVER_COUNT = 0, - A7XX_PERF_TSE_BE_BUSY_CYCLES = 1, - A7XX_PERF_TSE_BE_CLIPPING_CYCLES = 2, - A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = 3, - A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = 4, - A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = 5, - A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = 6, - A7XX_PERF_TSE_BE_INPUT_PRIM = 7, - A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = 8, - A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = 9, - A7XX_PERF_TSE_BE_CLIPPED_PRIM = 10, - A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = 11, - A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = 12, - A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = 13, - A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = 14, - A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = 15, - A7XX_PERF_TSE_BE_CINVOCATION = 16, - A7XX_PERF_TSE_BE_CPRIMITIVES = 17, - A7XX_PERF_TSE_BE_2D_INPUT_PRIM = 18, - A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = 19, - A7XX_PERF_TSE_BE_CLIP_PLANES = 20, - A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = 21, - A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = 22, - A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 23, - A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 24, - A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = 25, - A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = 26, - A7XX_PERF_TSE_BE_EXCLUDED_PRIM = 27, - A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = 28, - A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = 29, - A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = 30, - A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = 31, - A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = 32, - A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = 33, - A7XX_PERF_TSE_FE_BUSY_CYCLES = 34, - A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = 35, - A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = 36, - A7XX_PERF_TSE_FE_INPUT_PRIM = 37, - A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = 38, - A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = 39, - A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = 40, - A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = 41, - A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = 42, - A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = 43, - A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = 44, - A7XX_PERF_TSE_FE_CINVOCATION = 45, - A7XX_PERF_TSE_FE_CPRIMITIVES = 46, - A7XX_PERF_TSE_FE_CLIP_PLANES = 47, - A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = 48, - A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = 49, - A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 50, - A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 51, - A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = 52, - A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = 53, - A7XX_PERF_TSE_FE_EXCLUDED_PRIM = 54, - A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = 55, - A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = 56, - A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = 57, - A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = 58, - A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = 59, - A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = 60, - A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = 61, -}; - -enum a7xx_ras_perfcounter_select { - A7XX_PERF_RAS_NEVER_COUNT = 0, - A7XX_PERF_RAS_BUSY_CYCLES = 1, - A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 2, - A7XX_PERF_RAS_STALL_CYCLES_LRZ = 3, - A7XX_PERF_RAS_STARVE_CYCLES_TSE = 4, - A7XX_PERF_RAS_SUPER_TILES = 5, - A7XX_PERF_RAS_8X4_TILES = 6, - A7XX_PERF_RAS_MASKGEN_ACTIVE = 7, - A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = 8, - A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = 9, - A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = 10, - A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 11, - A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = 12, - A7XX_PERF_RAS_BLOCKS = 13, - A7XX_PERF_RAS_FALSE_PARTIAL_STILE = 14, - A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = 15, - A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = 16, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = 17, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = 18, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = 19, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = 20, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = 21, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = 22, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = 23, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = 24, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = 25, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = 26, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = 27, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = 28, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = 29, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = 30, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = 31, - A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = 32, -}; - -enum a7xx_uche_perfcounter_select { - A7XX_PERF_UCHE_NEVER_COUNT = 0, - A7XX_PERF_UCHE_BUSY_CYCLES = 1, - A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = 2, - A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = 3, - A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = 4, - A7XX_PERF_UCHE_STALL_CYCLES_DECMP = 5, - A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = 6, - A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = 7, - A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = 8, - A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = 9, - A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = 10, - A7XX_PERF_UCHE_READ_REQUESTS_SP = 11, - A7XX_PERF_UCHE_READ_REQUESTS_TP = 12, - A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = 13, - A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = 14, - A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = 15, - A7XX_PERF_UCHE_READ_REQUESTS_VFD = 16, - A7XX_PERF_UCHE_READ_REQUESTS_VPC = 17, - A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = 18, - A7XX_PERF_UCHE_READ_REQUESTS_LRZ = 19, - A7XX_PERF_UCHE_READ_REQUESTS_PC = 20, - A7XX_PERF_UCHE_WRITE_REQUESTS_SP = 21, - A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = 22, - A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = 23, - A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = 24, - A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = 25, - A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = 26, - A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = 27, - A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = 28, - A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = 29, - A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = 30, - A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = 31, - A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = 32, - A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = 33, - A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = 34, - A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = 35, - A7XX_PERF_UCHE_GMEM_READ_BEATS = 36, - A7XX_PERF_UCHE_GMEM_WRITE_BEATS = 37, - A7XX_PERF_UCHE_UBWC_READ_BEATS = 38, - A7XX_PERF_UCHE_UBWC_WRITE_BEATS = 39, - A7XX_PERF_UCHE_EVICTS = 40, - A7XX_PERF_UCHE_BANK_REQ0 = 41, - A7XX_PERF_UCHE_BANK_REQ1 = 42, - A7XX_PERF_UCHE_BANK_REQ2 = 43, - A7XX_PERF_UCHE_BANK_REQ3 = 44, - A7XX_PERF_UCHE_BANK_REQ4 = 45, - A7XX_PERF_UCHE_BANK_REQ5 = 46, - A7XX_PERF_UCHE_BANK_REQ6 = 47, - A7XX_PERF_UCHE_BANK_REQ7 = 48, - A7XX_PERF_UCHE_TPH_REF_FULL = 49, - A7XX_PERF_UCHE_TPH_VICTIM_FULL = 50, - A7XX_PERF_UCHE_TPH_EXT_FULL = 51, - A7XX_PERF_UCHE_RAM_READ_REQ = 52, - A7XX_PERF_UCHE_RAM_WRITE_REQ = 53, - A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = 54, - A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = 55, - A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = 56, - A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = 57, - A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = 58, - A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = 59, - A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = 60, - A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = 61, - A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = 62, - A7XX_PERF_UCHE_EVICTS_SP = 63, - A7XX_PERF_UCHE_EVICTS_LRZ = 64, - A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = 65, - A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = 66, - A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = 67, - A7XX_PERF_BYPC_FULL = 68, - A7XX_PERF_BYPC_FULL_CCHE_STALL = 69, - A7XX_PERF_BYPC_VHUB_STALL = 70, - A7XX_PERF_BYPD_FULL = 71, - A7XX_PERF_BYPD_FULL_GBIF_STALL = 72, - A7XX_PERF_VHUB_PTABLE_FULL = 73, - A7XX_PERF_DHUB_PTABLE_FULL = 74, - A7XX_PERF_UCHE_RESERVED_75 = 75, - A7XX_PERF_UCHE_RESERVED_76 = 76, - A7XX_PERF_UCHE_RESERVED_77 = 77, - A7XX_PERF_UCHE_RESERVED_78 = 78, - A7XX_PERF_UCHE_RESERVED_79 = 79, - A7XX_PERF_UCHE_RESERVED_80 = 80, - A7XX_PERF_UCHE_RESERVED_81 = 81, - A7XX_PERF_UCHE_RESERVED_82 = 82, - A7XX_PERF_UCHE_RESERVED_83 = 83, - A7XX_PERF_UCHE_RESERVED_84 = 84, - A7XX_PERF_UCHE_RESERVED_85 = 85, - A7XX_PERF_UCHE_RESERVED_86 = 86, - A7XX_PERF_UCHE_RESERVED_87 = 87, - A7XX_PERF_UCHE_RESERVED_88 = 88, - A7XX_PERF_UCHE_RESERVED_89 = 89, - A7XX_PERF_UCHE_RESERVED_90 = 90, - A7XX_PERF_UCHE_RESERVED_91 = 91, - A7XX_PERF_UCHE_RESERVED_92 = 92, - A7XX_PERF_UCHE_RESERVED_93 = 93, - A7XX_PERF_UCHE_RESERVED_94 = 94, - A7XX_PERF_UCHE_RESERVED_95 = 95, - A7XX_PERF_UCHE_RESERVED_96 = 96, - A7XX_PERF_UCHE_RESERVED_97 = 97, - A7XX_PERF_UCHE_RESERVED_98 = 98, - A7XX_PERF_UCHE_RESERVED_99 = 99, - A7XX_PERF_UCHE_RESERVED_100 = 100, - A7XX_PERF_UCHE_RESERVED_101 = 101, - A7XX_PERF_UCHE_RESERVED_102 = 102, - A7XX_PERF_UCHE_RESERVED_103 = 103, - A7XX_PERF_UCHE_RESERVED_104 = 104, - A7XX_PERF_UCHE_RESERVED_105 = 105, - A7XX_PERF_UCHE_RESERVED_106 = 106, - A7XX_PERF_UCHE_RESERVED_107 = 107, - A7XX_PERF_UCHE_RESERVED_108 = 108, - A7XX_PERF_UCHE_RESERVED_109 = 109, - A7XX_PERF_UCHE_RESERVED_110 = 110, - A7XX_PERF_UCHE_RESERVED_111 = 111, - A7XX_PERF_UCHE_RESERVED_112 = 112, - A7XX_PERF_UCHE_RESERVED_113 = 113, - A7XX_PERF_UCHE_RESERVED_114 = 114, - A7XX_PERF_UCHE_RESERVED_115 = 115, - A7XX_PERF_UCHE_RESERVED_116 = 116, - A7XX_PERF_UCHE_RESERVED_117 = 117, - A7XX_PERF_UCHE_RESERVED_118 = 118, - A7XX_PERF_UCHE_RESERVED_119 = 119, - A7XX_PERF_UCHE_RESERVED_120 = 120, - A7XX_PERF_UCHE_RESERVED_121 = 121, - A7XX_PERF_UCHE_RESERVED_122 = 122, - A7XX_PERF_UCHE_RESERVED_123 = 123, - A7XX_PERF_UCHE_RESERVED_124 = 124, - A7XX_PERF_UCHE_RESERVED_125 = 125, - A7XX_PERF_UCHE_RESERVED_126 = 126, - A7XX_PERF_UCHE_RESERVED_127 = 127, - A7XX_PERF_CCHE_BUSY_CYCLES = 128, - A7XX_PERF_CCHE_STALL_CYCLES_UCHE = 129, - A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = 130, - A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = 131, - A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = 132, - A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = 133, - A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = 134, - A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = 135, - A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = 136, - A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = 137, - A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = 138, - A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = 139, - A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = 140, - A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = 141, - A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = 142, - A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = 143, - A7XX_PERF_CCHE_READ_REQUESTS_LRZ = 144, - A7XX_PERF_CCHE_READ_REQUESTS_VPC = 145, - A7XX_PERF_CCHE_WRITE_REQUESTS_SP = 146, - A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = 147, - A7XX_PERF_CCHE_READ_REQUESTS_GMEM = 148, - A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = 149, - A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = 150, - A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = 151, - A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = 152, - A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = 153, - A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = 154, - A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = 155, - A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = 156, - A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = 157, - A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = 158, - A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = 159, - A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = 160, - A7XX_PERF_CCHE_BANK_REQ0 = 161, - A7XX_PERF_CCHE_BANK_REQ1 = 162, - A7XX_PERF_CCHE_BANK_REQ2 = 163, - A7XX_PERF_CCHE_BANK_REQ3 = 164, - A7XX_PERF_CCHE_BANK_REQ4 = 165, - A7XX_PERF_CCHE_BANK_REQ5 = 166, - A7XX_PERF_CCHE_BANK_REQ6 = 167, - A7XX_PERF_CCHE_BANK_REQ7 = 168, - A7XX_PERF_CCHE_BANK_REQ8 = 169, - A7XX_PERF_CCHE_BANK_REQ9 = 170, - A7XX_PERF_CCHE_BANK_REQ10 = 171, - A7XX_PERF_CCHE_BANK_REQ11 = 172, - A7XX_PERF_CCHE_BANK_REQ12 = 173, - A7XX_PERF_CCHE_BANK_REQ13 = 174, - A7XX_PERF_CCHE_BANK_REQ14 = 175, - A7XX_PERF_CCHE_BANK_REQ15 = 176, - A7XX_PERF_CCHE_GBANK_REQ0 = 177, - A7XX_PERF_CCHE_GBANK_REQ1 = 178, - A7XX_PERF_CCHE_GBANK_REQ2 = 179, - A7XX_PERF_CCHE_GBANK_REQ3 = 180, - A7XX_PERF_CCHE_TPH_REF_FULL = 181, - A7XX_PERF_CCHE_TPH_VICTIM_FULL = 182, - A7XX_PERF_CCHE_TPH_EXT_FULL = 183, - A7XX_PERF_CCHE_RAM_READ_REQ = 184, - A7XX_PERF_CCHE_RAM_WRITE_REQ = 185, - A7XX_PERF_CCHE_TPH_CONFLICT_CL = 186, - A7XX_PERF_CCHE_DBANK_CONFLICT = 187, - A7XX_PERF_CCHE_TPH_QUEUE_FULL = 188, - A7XX_PERF_CCHE_DPH_QUEUE_FULL = 189, - A7XX_PERF_CCHE_OPH_QUEUE_FULL = 190, - A7XX_PERF_CCHE_WACK_QUEUE_FULL = 191, - A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = 192, - A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = 193, - A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = 194, - A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = 195, - A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = 196, - A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = 197, - A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = 198, - A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = 199, - A7XX_PERF_CCHE_STALL_CYCLES_TP = 200, -}; - -enum a7xx_tp_perfcounter_select { - A7XX_PERF_TP_NEVER_COUNT = 0, - A7XX_PERF_TP_BUSY_CYCLES = 1, - A7XX_PERF_TP_STALL_CYCLES_UCHE = 2, - A7XX_PERF_TP_LATENCY_CYCLES = 3, - A7XX_PERF_TP_LATENCY_TRANS = 4, - A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = 5, - A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = 6, - A7XX_PERF_TP_L1_CACHELINE_REQUESTS = 7, - A7XX_PERF_TP_L1_CACHELINE_MISSES = 8, - A7XX_PERF_TP_SP_TP_TRANS = 9, - A7XX_PERF_TP_TP_SP_TRANS = 10, - A7XX_PERF_TP_OUTPUT_PIXELS = 11, - A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = 12, - A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = 13, - A7XX_PERF_TP_QUADS_RECEIVED = 14, - A7XX_PERF_TP_QUADS_OFFSET = 15, - A7XX_PERF_TP_QUADS_SHADOW = 16, - A7XX_PERF_TP_QUADS_ARRAY = 17, - A7XX_PERF_TP_QUADS_GRADIENT = 18, - A7XX_PERF_TP_QUADS_1D = 19, - A7XX_PERF_TP_QUADS_2D = 20, - A7XX_PERF_TP_QUADS_BUFFER = 21, - A7XX_PERF_TP_QUADS_3D = 22, - A7XX_PERF_TP_QUADS_CUBE = 23, - A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = 24, - A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = 25, - A7XX_PERF_TP_OUTPUT_PIXELS_POINT = 26, - A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = 27, - A7XX_PERF_TP_OUTPUT_PIXELS_MIP = 28, - A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = 29, - A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 30, - A7XX_PERF_TP_FLAG_CACHE_REQUESTS = 31, - A7XX_PERF_TP_FLAG_CACHE_MISSES = 32, - A7XX_PERF_TP_L1_5_L2_REQUESTS = 33, - A7XX_PERF_TP_2D_OUTPUT_PIXELS = 34, - A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = 35, - A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 36, - A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = 37, - A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = 38, - A7XX_PERF_TP_TPA2TPC_TRANS = 39, - A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = 40, - A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = 41, - A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = 42, - A7XX_PERF_TP_L1_5_COMPRESS_REQS = 43, - A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = 44, - A7XX_PERF_TP_L1_BANK_CONFLICT = 45, - A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = 46, - A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = 47, - A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = 48, - A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = 49, - A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = 50, - A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 51, - A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 52, - A7XX_PERF_TP_BACKEND_WORKING_CYCLES = 53, - A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, - A7XX_PERF_TP_STARVE_CYCLES_SP = 55, - A7XX_PERF_TP_STARVE_CYCLES_UCHE = 56, - A7XX_PERF_TP_STALL_CYCLES_UFC = 57, - A7XX_PERF_TP_FORMAT_DECOMP_POINT = 58, - A7XX_PERF_TP_FILTER_POINT_FP16 = 59, - A7XX_PERF_TP_FILTER_POINT_FP32 = 60, - A7XX_PERF_TP_LATENCY_FIFO_FULL = 61, - A7XX_PERF_TP_RESERVED_62 = 62, - A7XX_PERF_TP_RESERVED_63 = 63, - A7XX_PERF_TP_RESERVED_64 = 64, - A7XX_PERF_TP_RESERVED_65 = 65, - A7XX_PERF_TP_RESERVED_66 = 66, - A7XX_PERF_TP_RESERVED_67 = 67, - A7XX_PERF_TP_RESERVED_68 = 68, - A7XX_PERF_TP_RESERVED_69 = 69, - A7XX_PERF_TP_RESERVED_70 = 70, - A7XX_PERF_TP_RESERVED_71 = 71, - A7XX_PERF_TP_RESERVED_72 = 72, - A7XX_PERF_TP_RESERVED_73 = 73, - A7XX_PERF_TP_RESERVED_74 = 74, - A7XX_PERF_TP_RESERVED_75 = 75, - A7XX_PERF_TP_RESERVED_76 = 76, - A7XX_PERF_TP_RESERVED_77 = 77, - A7XX_PERF_TP_RESERVED_78 = 78, - A7XX_PERF_TP_RESERVED_79 = 79, - A7XX_PERF_TP_RESERVED_80 = 80, - A7XX_PERF_TP_RESERVED_81 = 81, - A7XX_PERF_TP_RESERVED_82 = 82, - A7XX_PERF_TP_RESERVED_83 = 83, - A7XX_PERF_TP_RESERVED_84 = 84, - A7XX_PERF_TP_RESERVED_85 = 85, - A7XX_PERF_TP_RESERVED_86 = 86, - A7XX_PERF_TP_RESERVED_87 = 87, - A7XX_PERF_TP_RESERVED_88 = 88, - A7XX_PERF_TP_RESERVED_89 = 89, - A7XX_PERF_TP_RESERVED_90 = 90, - A7XX_PERF_TP_RESERVED_91 = 91, - A7XX_PERF_TP_RESERVED_92 = 92, - A7XX_PERF_TP_RESERVED_93 = 93, - A7XX_PERF_TP_RESERVED_94 = 94, - A7XX_PERF_TP_RESERVED_95 = 95, - A7XX_PERF_TP_RESERVED_96 = 96, - A7XX_PERF_TP_RESERVED_97 = 97, - A7XX_PERF_TP_RESERVED_98 = 98, - A7XX_PERF_TP_RESERVED_99 = 99, - A7XX_PERF_TP_RESERVED_100 = 100, - A7XX_PERF_TP_RESERVED_101 = 101, - A7XX_PERF_TP_RESERVED_102 = 102, - A7XX_PERF_TP_RESERVED_103 = 103, - A7XX_PERF_TP_RESERVED_104 = 104, - A7XX_PERF_TP_RESERVED_105 = 105, - A7XX_PERF_TP_RESERVED_106 = 106, - A7XX_PERF_TP_RESERVED_107 = 107, - A7XX_PERF_TP_RESERVED_108 = 108, - A7XX_PERF_TP_RESERVED_109 = 109, - A7XX_PERF_TP_RESERVED_110 = 110, - A7XX_PERF_TP_RESERVED_111 = 111, - A7XX_PERF_TP_RESERVED_112 = 112, - A7XX_PERF_TP_RESERVED_113 = 113, - A7XX_PERF_TP_RESERVED_114 = 114, - A7XX_PERF_TP_RESERVED_115 = 115, - A7XX_PERF_TP_RESERVED_116 = 116, - A7XX_PERF_TP_RESERVED_117 = 117, - A7XX_PERF_TP_RESERVED_118 = 118, - A7XX_PERF_TP_RESERVED_119 = 119, - A7XX_PERF_TP_RESERVED_120 = 120, - A7XX_PERF_TP_RESERVED_121 = 121, - A7XX_PERF_TP_RESERVED_122 = 122, - A7XX_PERF_TP_RESERVED_123 = 123, - A7XX_PERF_TP_RESERVED_124 = 124, - A7XX_PERF_TP_RESERVED_125 = 125, - A7XX_PERF_TP_RESERVED_126 = 126, - A7XX_PERF_TP_RESERVED_127 = 127, - A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = 128, - A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = 129, - A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = 130, - A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = 131, - A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = 132, -}; - -enum a7xx_sp_perfcounter_select { - A7XX_PERF_SP_NEVER_COUNT = 0, - A7XX_PERF_SP_BUSY_CYCLES = 1, - A7XX_PERF_SP_ALU_WORKING_CYCLES = 2, - A7XX_PERF_SP_STALL_CYCLES_VPC_BE = 3, - A7XX_PERF_SP_STALL_CYCLES_TP = 4, - A7XX_PERF_SP_STALL_CYCLES_UCHE = 5, - A7XX_PERF_SP_STALL_CYCLES_RB = 6, - A7XX_PERF_SP_NON_EXECUTION_CYCLES = 7, - A7XX_PERF_SP_WAVE_CONTEXTS = 8, - A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = 9, - A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = 10, - A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, - A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = 12, - A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, - A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = 14, - A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = 15, - A7XX_PERF_SP_WAVE_CTRL_CYCLES = 16, - A7XX_PERF_SP_WAVE_LOAD_CYCLES = 17, - A7XX_PERF_SP_WAVE_EMIT_CYCLES = 18, - A7XX_PERF_SP_WAVE_NOP_CYCLES = 19, - A7XX_PERF_SP_WAVE_WAIT_CYCLES = 20, - A7XX_PERF_SP_WAVE_FETCH_CYCLES = 21, - A7XX_PERF_SP_WAVE_IDLE_CYCLES = 22, - A7XX_PERF_SP_WAVE_END_CYCLES = 23, - A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, - A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, - A7XX_PERF_SP_WAVE_JOIN_CYCLES = 26, - A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = 27, - A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = 28, - A7XX_PERF_SP_LM_ATOMICS = 29, - A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = 30, - A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = 31, - A7XX_PERF_SP_GM_ATOMICS = 32, - A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, - A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, - A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, - A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, - A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, - A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, - A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, - A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, - A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, - A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, - A7XX_PERF_SP_VS_INSTRUCTIONS = 43, - A7XX_PERF_SP_FS_INSTRUCTIONS = 44, - A7XX_PERF_SP_ADDR_LOCK_COUNT = 45, - A7XX_PERF_SP_UCHE_READ_TRANS = 46, - A7XX_PERF_SP_UCHE_WRITE_TRANS = 47, - A7XX_PERF_SP_EXPORT_VPC_TRANS = 48, - A7XX_PERF_SP_EXPORT_RB_TRANS = 49, - A7XX_PERF_SP_PIXELS_KILLED = 50, - A7XX_PERF_SP_ICL1_REQUESTS = 51, - A7XX_PERF_SP_ICL1_MISSES = 52, - A7XX_PERF_SP_HS_INSTRUCTIONS = 53, - A7XX_PERF_SP_DS_INSTRUCTIONS = 54, - A7XX_PERF_SP_GS_INSTRUCTIONS = 55, - A7XX_PERF_SP_CS_INSTRUCTIONS = 56, - A7XX_PERF_SP_GPR_READ = 57, - A7XX_PERF_SP_GPR_WRITE = 58, - A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, - A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, - A7XX_PERF_SP_LM_BANK_CONFLICTS = 61, - A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, - A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, - A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, - A7XX_PERF_SP_LM_WORKING_CYCLES = 65, - A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = 66, - A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = 67, - A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, - A7XX_PERF_SP_STARVE_CYCLES_HLSQ = 69, - A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = 70, - A7XX_PERF_SP_WORKING_EU = 71, - A7XX_PERF_SP_ANY_EU_WORKING = 72, - A7XX_PERF_SP_WORKING_EU_FS_STAGE = 73, - A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, - A7XX_PERF_SP_WORKING_EU_VS_STAGE = 75, - A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, - A7XX_PERF_SP_WORKING_EU_CS_STAGE = 77, - A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, - A7XX_PERF_SP_GPR_READ_PREFETCH = 79, - A7XX_PERF_SP_GPR_READ_CONFLICT = 80, - A7XX_PERF_SP_GPR_WRITE_CONFLICT = 81, - A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, - A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, - A7XX_PERF_SP_EXECUTABLE_WAVES = 84, - A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = 85, - A7XX_PERF_SP_RESERVED_86 = 86, - A7XX_PERF_SP_BYPASS_BUSY_CYCLES = 87, - A7XX_PERF_SP_ANY_EU_WORKING_LPAC = 88, - A7XX_PERF_SP_WAVE_ALU_CYCLES = 89, - A7XX_PERF_SP_WAVE_EFU_CYCLES = 90, - A7XX_PERF_SP_WAVE_INT_CYCLES = 91, - A7XX_PERF_SP_WAVE_CSP_CYCLES = 92, - A7XX_PERF_SP_EWAVE_CONTEXTS = 93, - A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = 94, - A7XX_PERF_SP_LPAC_BUSY_CYCLES = 95, - A7XX_PERF_SP_LPAC_INSTRUCTIONS = 96, - A7XX_PERF_SP_FS_STAGE_1X_WAVES = 97, - A7XX_PERF_SP_FS_STAGE_2X_WAVES = 98, - A7XX_PERF_SP_QUADS = 99, - A7XX_PERF_SP_CS_INVOCATIONS = 100, - A7XX_PERF_SP_PIXELS = 101, - A7XX_PERF_SP_LPAC_DRAWCALLS = 102, - A7XX_PERF_SP_PI_WORKING_CYCLES = 103, - A7XX_PERF_SP_WAVE_INPUT_CYCLES = 104, - A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = 105, - A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = 106, - A7XX_PERF_SP_WAVE_HWAVE_SYNC = 107, - A7XX_PERF_SP_OUTPUT_3D_PIXELS = 108, - A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = 109, - A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = 110, - A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = 111, - A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = 112, - A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = 113, - A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = 114, - A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = 115, - A7XX_PERF_SP_ALU_GPR_READ_CYCLES = 116, - A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = 117, - A7XX_PERF_SP_LM_FULL_CYCLES = 118, - A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = 119, - A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = 120, - A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = 121, - A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = 122, - A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = 123, - A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = 124, - A7XX_PERF_SP_RTU_BUSY_CYCLES = 125, - A7XX_PERF_SP_RTU_L0_HITS = 126, - A7XX_PERF_SP_RTU_L0_MISSES = 127, - A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = 128, - A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = 129, - A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = 130, - A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = 131, - A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = 132, - A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = 133, - A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = 134, - A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = 135, - A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = 136, - A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = 137, - A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = 138, - A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = 139, - A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = 140, - A7XX_PERF_SP_STCHE_MISS_INC_VS = 141, - A7XX_PERF_SP_STCHE_MISS_INC_FS = 142, - A7XX_PERF_SP_STCHE_MISS_INC_BV = 143, - A7XX_PERF_SP_STCHE_MISS_INC_LPAC = 144, - A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = 145, - A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = 146, - A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = 147, - A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = 148, - A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = 149, - A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = 150, - A7XX_PERF_SP_EFU_WORKING_CYCLES = 151, - A7XX_PERF_SP_BRANCH_TAKEN = 152, - A7XX_PERF_SP_BRANCH_NOT_TAKEN = 153, - A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = 154, - A7XX_PERF_SP_BRANCH_INS_COUNT = 155, - A7XX_PERF_SP_PREDICT_TAKEN = 156, - A7XX_PERF_SP_PREDICT_NOT_TAKEN = 157, - A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = 158, - A7XX_PERF_SP_PREDICT_INS_COUNT = 159, - A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = 160, - A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = 161, - A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = 162, - A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = 163, - A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = 164, - A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = 165, - A7XX_PERF_SP_LB_READ_XFER_ALU = 166, - A7XX_PERF_SP_LB_ALU_READ_CONS = 167, - A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = 168, - A7XX_PERF_SP_LB_WRITE_XFER_VPC = 169, - A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = 170, - A7XX_PERF_SP_LB_LDST_RW_LM = 171, - A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = 172, - A7XX_PERF_SP_LB_LDST_WRITE_CONS = 173, - A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = 174, - A7XX_PERF_SP_GPR_READ_BANK = 175, - A7XX_PERF_SP_GPR_WRITE_BANK = 176, - A7XX_PERF_SP_VS_WAVE_REQ_PENDING = 177, - A7XX_PERF_SP_FS_WAVE_REQ_PENDING = 178, - A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = 179, - A7XX_PERF_SP_WAVE_SPLIT_CNT = 180, - A7XX_PERF_SP_FS_OOO_WAVE_ACC = 181, -}; - -enum a7xx_rb_perfcounter_select { - A7XX_PERF_RB_NEVER_COUNT = 0, - A7XX_PERF_RB_BUSY_CYCLES = 1, - A7XX_PERF_RB_STALL_CYCLES_HLSQ = 2, - A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = 3, - A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = 4, - A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = 5, - A7XX_PERF_RB_STARVE_CYCLES_SP = 6, - A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = 7, - A7XX_PERF_RB_STARVE_CYCLES_CCU = 8, - A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = 9, - A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = 10, - A7XX_PERF_RB_Z_WORKLOAD = 11, - A7XX_PERF_RB_HLSQ_ACTIVE = 12, - A7XX_PERF_RB_Z_READ = 13, - A7XX_PERF_RB_Z_WRITE = 14, - A7XX_PERF_RB_C_READ = 15, - A7XX_PERF_RB_C_WRITE = 16, - A7XX_PERF_RB_TOTAL_PASS = 17, - A7XX_PERF_RB_Z_PASS = 18, - A7XX_PERF_RB_Z_FAIL = 19, - A7XX_PERF_RB_S_FAIL = 20, - A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = 21, - A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = 22, - A7XX_PERF_RB_PS_INVOCATIONS = 23, - A7XX_PERF_RB_2D_ALIVE_CYCLES = 24, - A7XX_PERF_RB_2D_STARVE_CYCLES_SP = 25, - A7XX_PERF_RB_2D_VALID_PIXELS = 26, - A7XX_PERF_RB_3D_PIXELS = 27, - A7XX_PERF_RB_BLENDER_WORKING_CYCLES = 28, - A7XX_PERF_RB_ZPROC_WORKING_CYCLES = 29, - A7XX_PERF_RB_CPROC_WORKING_CYCLES = 30, - A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = 31, - A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 32, - A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 33, - A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 34, - A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 35, - A7XX_PERF_RB_STALL_CYCLES_VPC_BE = 36, - A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = 37, - A7XX_PERF_RB_COLOR_PIX_TILES = 38, - A7XX_PERF_RB_STALL_CYCLES_CCU = 39, - A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = 40, - A7XX_PERF_RB_LATE_Z_ARB3_GRANT = 41, - A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = 42, - A7XX_PERF_RB_VRS_1X1_QUADS = 43, - A7XX_PERF_RB_VRS_2X1_QUADS = 44, - A7XX_PERF_RB_VRS_1X2_QUADS = 45, - A7XX_PERF_RB_VRS_2X2_QUADS = 46, - A7XX_PERF_RB_VRS_2X4_QUADS = 47, - A7XX_PERF_RB_VRS_4X2_QUADS = 48, - A7XX_PERF_RB_VRS_4X4_QUADS = 49, -}; - -enum a7xx_vsc_perfcounter_select { - A7XX_PERF_VSC_NEVER_COUNT = 0, - A7XX_PERF_VSC_BUSY_CYCLES = 1, - A7XX_PERF_VSC_WORKING_CYCLES = 2, - A7XX_PERF_VSC_STALL_CYCLES_UCHE = 3, - A7XX_PERF_VSC_EOT_NUM = 4, - A7XX_PERF_VSC_INPUT_TILES = 5, - A7XX_PERF_VSC_TILE_COMP_TRAN = 6, - A7XX_PERF_VSC_TILE_BYPASS_TRAN = 7, -}; - -enum a7xx_ccu_perfcounter_select { - A7XX_PERF_CCU_NEVER_COUNT = 0, - A7XX_PERF_CCU_BUSY_CYCLES = 1, - A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 2, - A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 3, - A7XX_PERF_CCU_DEPTH_BLOCKS = 4, - A7XX_PERF_CCU_COLOR_BLOCKS = 5, - A7XX_PERF_CCU_DEPTH_BLOCK_HIT = 6, - A7XX_PERF_CCU_COLOR_BLOCK_HIT = 7, - A7XX_PERF_CCU_PARTIAL_BLOCK_READ = 8, - A7XX_PERF_CCU_GMEM_READ = 9, - A7XX_PERF_CCU_GMEM_WRITE = 10, - A7XX_PERF_CCU_2D_RD_REQ = 11, - A7XX_PERF_CCU_2D_WR_REQ = 12, - A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = 13, - A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = 14, - A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = 15, - A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = 16, - A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = 17, - A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = 18, - A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = 19, - A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = 20, - A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = 21, - A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = 22, - A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = 23, - A7XX_PERF_CCU_COLOR_EVB_STALL = 24, - A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = 25, - A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = 26, - A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = 27, - A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = 28, - A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = 29, - A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = 30, - A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = 31, - A7XX_PERF_CCU_RESERVED_32 = 32, - A7XX_PERF_CCU_RESERVED_33 = 33, - A7XX_PERF_CCU_RESERVED_34 = 34, - A7XX_PERF_CCU_RESERVED_35 = 35, - A7XX_PERF_CCU_RESERVED_36 = 36, - A7XX_PERF_CCU_RESERVED_37 = 37, - A7XX_PERF_CCU_RESERVED_38 = 38, - A7XX_PERF_CCU_RESERVED_39 = 39, - A7XX_PERF_CCU_RESERVED_40 = 40, - A7XX_PERF_CCU_RESERVED_41 = 41, - A7XX_PERF_CCU_RESERVED_42 = 42, - A7XX_PERF_CCU_RESERVED_43 = 43, - A7XX_PERF_CCU_RESERVED_44 = 44, - A7XX_PERF_CCU_RESERVED_45 = 45, - A7XX_PERF_CCU_RESERVED_46 = 46, - A7XX_PERF_CCU_RESERVED_47 = 47, - A7XX_PERF_CCU_RESERVED_48 = 48, - A7XX_PERF_CCU_RESERVED_49 = 49, - A7XX_PERF_CCU_RESERVED_50 = 50, - A7XX_PERF_CCU_RESERVED_51 = 51, - A7XX_PERF_CCU_RESERVED_52 = 52, - A7XX_PERF_CCU_RESERVED_53 = 53, - A7XX_PERF_CCU_RESERVED_54 = 54, - A7XX_PERF_CCU_RESERVED_55 = 55, - A7XX_PERF_CCU_RESERVED_56 = 56, - A7XX_PERF_CCU_RESERVED_57 = 57, - A7XX_PERF_CCU_RESERVED_58 = 58, - A7XX_PERF_CCU_RESERVED_59 = 59, - A7XX_PERF_CCU_RESERVED_60 = 60, - A7XX_PERF_CCU_RESERVED_61 = 61, - A7XX_PERF_CCU_RESERVED_62 = 62, - A7XX_PERF_CCU_RESERVED_63 = 63, - A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = 64, - A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = 65, - A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = 66, - A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = 67, - A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = 68, - A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = 69, - A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = 70, - A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = 71, - A7XX_PERF_UFC_L0_SP_REQUESTS = 72, - A7XX_PERF_UFC_L0_SP_FILTER_HIT = 73, - A7XX_PERF_UFC_L0_SP_FILTER_MISS = 74, - A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = 75, - A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = 76, - A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = 77, - A7XX_PERF_CCU_RESERVED_78 = 78, - A7XX_PERF_CCU_RESERVED_79 = 79, - A7XX_PERF_CCU_RESERVED_80 = 80, - A7XX_PERF_CCU_RESERVED_81 = 81, - A7XX_PERF_CCU_RESERVED_82 = 82, - A7XX_PERF_CCU_RESERVED_83 = 83, - A7XX_PERF_CCU_RESERVED_84 = 84, - A7XX_PERF_CCU_RESERVED_85 = 85, - A7XX_PERF_CCU_RESERVED_86 = 86, - A7XX_PERF_CCU_RESERVED_87 = 87, - A7XX_PERF_CCU_RESERVED_88 = 88, - A7XX_PERF_CCU_RESERVED_89 = 89, - A7XX_PERF_CCU_RESERVED_90 = 90, - A7XX_PERF_CCU_RESERVED_91 = 91, - A7XX_PERF_CCU_RESERVED_92 = 92, - A7XX_PERF_CCU_RESERVED_93 = 93, - A7XX_PERF_CCU_RESERVED_94 = 94, - A7XX_PERF_CCU_RESERVED_95 = 95, - A7XX_PERF_CCU_RESERVED_96 = 96, - A7XX_PERF_CCU_RESERVED_97 = 97, - A7XX_PERF_CCU_RESERVED_98 = 98, - A7XX_PERF_CCU_RESERVED_99 = 99, - A7XX_PERF_CCU_RESERVED_100 = 100, - A7XX_PERF_CCU_RESERVED_101 = 101, - A7XX_PERF_CCU_RESERVED_102 = 102, - A7XX_PERF_CCU_RESERVED_103 = 103, - A7XX_PERF_CCU_RESERVED_104 = 104, - A7XX_PERF_CCU_RESERVED_105 = 105, - A7XX_PERF_CCU_RESERVED_106 = 106, - A7XX_PERF_CCU_RESERVED_107 = 107, - A7XX_PERF_CCU_RESERVED_108 = 108, - A7XX_PERF_CCU_RESERVED_109 = 109, - A7XX_PERF_CCU_RESERVED_110 = 110, - A7XX_PERF_CCU_RESERVED_111 = 111, - A7XX_PERF_CCU_RESERVED_112 = 112, - A7XX_PERF_CCU_RESERVED_113 = 113, - A7XX_PERF_CCU_RESERVED_114 = 114, - A7XX_PERF_CCU_RESERVED_115 = 115, - A7XX_PERF_CCU_RESERVED_116 = 116, - A7XX_PERF_CCU_RESERVED_117 = 117, - A7XX_PERF_CCU_RESERVED_118 = 118, - A7XX_PERF_CCU_RESERVED_119 = 119, - A7XX_PERF_CCU_RESERVED_120 = 120, - A7XX_PERF_CCU_RESERVED_121 = 121, - A7XX_PERF_CCU_RESERVED_122 = 122, - A7XX_PERF_CCU_RESERVED_123 = 123, - A7XX_PERF_CCU_RESERVED_124 = 124, - A7XX_PERF_CCU_RESERVED_125 = 125, - A7XX_PERF_CCU_RESERVED_126 = 126, - A7XX_PERF_CCU_RESERVED_127 = 127, - A7XX_PERF_CRE_RESOLVE_EVENTS = 128, - A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = 129, - A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = 130, - A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = 131, - A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = 132, - A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = 133, - A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = 134, - A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = 135, - A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = 136, -}; - -enum a7xx_lrz_perfcounter_select { - A7XX_PERF_LRZ_NEVER_COUNT = 0, - A7XX_PERF_LRZ_BUSY_CYCLES = 1, - A7XX_PERF_LRZ_STARVE_CYCLES_RAS = 2, - A7XX_PERF_LRZ_STALL_CYCLES_RB = 3, - A7XX_PERF_LRZ_STALL_CYCLES_VSC = 4, - A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = 5, - A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = 6, - A7XX_PERF_LRZ_STALL_CYCLES_UCHE = 7, - A7XX_PERF_LRZ_LRZ_READ = 8, - A7XX_PERF_LRZ_LRZ_WRITE = 9, - A7XX_PERF_LRZ_READ_LATENCY = 10, - A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = 11, - A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 12, - A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = 13, - A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 14, - A7XX_PERF_LRZ_FULL_8X8_TILES = 15, - A7XX_PERF_LRZ_PARTIAL_8X8_TILES = 16, - A7XX_PERF_LRZ_TILE_KILLED = 17, - A7XX_PERF_LRZ_TOTAL_PIXEL = 18, - A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 19, - A7XX_PERF_LRZ_FEEDBACK_ACCEPT = 20, - A7XX_PERF_LRZ_FEEDBACK_DISCARD = 21, - A7XX_PERF_LRZ_FEEDBACK_STALL = 22, - A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 23, - A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = 24, - A7XX_PERF_LRZ_RAS_MASK_TRANS = 25, - A7XX_PERF_LRZ_STALL_CYCLES_MVC = 26, - A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = 27, - A7XX_PERF_LRZ_TILE_KILLED_BY_Z = 28, - A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = 29, - A7XX_PERF_LRZ_NUM_FLOCK = 30, -}; - -enum a7xx_cmp_perfcounter_select { - A7XX_PERF_CMPDECMP_NEVER_COUNT = 0, - A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = 1, - A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 2, - A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 3, - A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = 4, - A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 5, - A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = 6, - A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = 7, - A7XX_PERF_CMPDECMP_VBIF_READ_DATA = 8, - A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = 9, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 10, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 11, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 12, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 13, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 14, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 15, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 16, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 17, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 18, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 19, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 20, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 21, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 22, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 23, - A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 24, - A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 25, - A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 26, - A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 27, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 28, - A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 29, - A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = 30, - A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = 31, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = 32, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = 33, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = 34, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = 35, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = 36, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = 37, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = 38, - A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = 39, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = 40, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = 41, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = 42, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = 43, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = 44, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = 45, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = 46, - A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = 47, -}; - -enum a7xx_gbif_perfcounter_select { - A7XX_PERF_GBIF_NEVER_COUNT = 0, - A7XX_PERF_GBIF_RESERVED_1 = 1, - A7XX_PERF_GBIF_RESERVED_2 = 2, - A7XX_PERF_GBIF_RESERVED_3 = 3, - A7XX_PERF_GBIF_RESERVED_4 = 4, - A7XX_PERF_GBIF_RESERVED_5 = 5, - A7XX_PERF_GBIF_RESERVED_6 = 6, - A7XX_PERF_GBIF_RESERVED_7 = 7, - A7XX_PERF_GBIF_RESERVED_8 = 8, - A7XX_PERF_GBIF_RESERVED_9 = 9, - A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = 10, - A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = 11, - A7XX_PERF_GBIF_RESERVED_12 = 12, - A7XX_PERF_GBIF_RESERVED_13 = 13, - A7XX_PERF_GBIF_RESERVED_14 = 14, - A7XX_PERF_GBIF_RESERVED_15 = 15, - A7XX_PERF_GBIF_RESERVED_16 = 16, - A7XX_PERF_GBIF_RESERVED_17 = 17, - A7XX_PERF_GBIF_RESERVED_18 = 18, - A7XX_PERF_GBIF_RESERVED_19 = 19, - A7XX_PERF_GBIF_RESERVED_20 = 20, - A7XX_PERF_GBIF_RESERVED_21 = 21, - A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = 22, - A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = 23, - A7XX_PERF_GBIF_RESERVED_24 = 24, - A7XX_PERF_GBIF_RESERVED_25 = 25, - A7XX_PERF_GBIF_RESERVED_26 = 26, - A7XX_PERF_GBIF_RESERVED_27 = 27, - A7XX_PERF_GBIF_RESERVED_28 = 28, - A7XX_PERF_GBIF_RESERVED_29 = 29, - A7XX_PERF_GBIF_RESERVED_30 = 30, - A7XX_PERF_GBIF_RESERVED_31 = 31, - A7XX_PERF_GBIF_RESERVED_32 = 32, - A7XX_PERF_GBIF_RESERVED_33 = 33, - A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = 34, - A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = 35, - A7XX_PERF_GBIF_RESERVED_36 = 36, - A7XX_PERF_GBIF_RESERVED_37 = 37, - A7XX_PERF_GBIF_RESERVED_38 = 38, - A7XX_PERF_GBIF_RESERVED_39 = 39, - A7XX_PERF_GBIF_RESERVED_40 = 40, - A7XX_PERF_GBIF_RESERVED_41 = 41, - A7XX_PERF_GBIF_RESERVED_42 = 42, - A7XX_PERF_GBIF_RESERVED_43 = 43, - A7XX_PERF_GBIF_RESERVED_44 = 44, - A7XX_PERF_GBIF_RESERVED_45 = 45, - A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = 46, - A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = 47, - A7XX_PERF_GBIF_RESERVED_48 = 48, - A7XX_PERF_GBIF_RESERVED_49 = 49, - A7XX_PERF_GBIF_RESERVED_50 = 50, - A7XX_PERF_GBIF_RESERVED_51 = 51, - A7XX_PERF_GBIF_RESERVED_52 = 52, - A7XX_PERF_GBIF_RESERVED_53 = 53, - A7XX_PERF_GBIF_RESERVED_54 = 54, - A7XX_PERF_GBIF_RESERVED_55 = 55, - A7XX_PERF_GBIF_RESERVED_56 = 56, - A7XX_PERF_GBIF_RESERVED_57 = 57, - A7XX_PERF_GBIF_RESERVED_58 = 58, - A7XX_PERF_GBIF_RESERVED_59 = 59, - A7XX_PERF_GBIF_RESERVED_60 = 60, - A7XX_PERF_GBIF_RESERVED_61 = 61, - A7XX_PERF_GBIF_RESERVED_62 = 62, - A7XX_PERF_GBIF_RESERVED_63 = 63, - A7XX_PERF_GBIF_RESERVED_64 = 64, - A7XX_PERF_GBIF_RESERVED_65 = 65, - A7XX_PERF_GBIF_RESERVED_66 = 66, - A7XX_PERF_GBIF_RESERVED_67 = 67, - A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = 68, - A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = 69, - A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = 70, - A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = 71, - A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = 72, - A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = 73, - A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = 74, - A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = 75, - A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = 76, - A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = 77, - A7XX_PERF_GBIF_RESERVED_78 = 78, - A7XX_PERF_GBIF_RESERVED_79 = 79, - A7XX_PERF_GBIF_RESERVED_80 = 80, - A7XX_PERF_GBIF_RESERVED_81 = 81, - A7XX_PERF_GBIF_RESERVED_82 = 82, - A7XX_PERF_GBIF_RESERVED_83 = 83, - A7XX_PERF_GBIF_RESERVED_84 = 84, - A7XX_PERF_GBIF_RESERVED_85 = 85, - A7XX_PERF_GBIF_RESERVED_86 = 86, - A7XX_PERF_GBIF_RESERVED_87 = 87, - A7XX_PERF_GBIF_RESERVED_88 = 88, - A7XX_PERF_GBIF_RESERVED_89 = 89, - A7XX_PERF_GBIF_RESERVED_90 = 90, - A7XX_PERF_GBIF_RESERVED_91 = 91, - A7XX_PERF_GBIF_RESERVED_92 = 92, - A7XX_PERF_GBIF_RESERVED_93 = 93, - A7XX_PERF_GBIF_RESERVED_94 = 94, - A7XX_PERF_GBIF_RESERVED_95 = 95, - A7XX_PERF_GBIF_RESERVED_96 = 96, - A7XX_PERF_GBIF_RESERVED_97 = 97, - A7XX_PERF_GBIF_RESERVED_98 = 98, - A7XX_PERF_GBIF_RESERVED_99 = 99, - A7XX_PERF_GBIF_RESERVED_100 = 100, - A7XX_PERF_GBIF_RESERVED_101 = 101, - A7XX_PERF_GBIF_RESERVED_102 = 102, - A7XX_PERF_GBIF_RESERVED_103 = 103, - A7XX_PERF_GBIF_RESERVED_104 = 104, - A7XX_PERF_GBIF_RESERVED_105 = 105, - A7XX_PERF_GBIF_RESERVED_106 = 106, - A7XX_PERF_GBIF_RESERVED_107 = 107, - A7XX_PERF_GBIF_RESERVED_108 = 108, - A7XX_PERF_GBIF_RESERVED_109 = 109, - A7XX_PERF_GBIF_RESERVED_110 = 110, - A7XX_PERF_GBIF_RESERVED_111 = 111, - A7XX_PERF_GBIF_RESERVED_112 = 112, - A7XX_PERF_GBIF_RESERVED_113 = 113, - A7XX_PERF_GBIF_RESERVED_114 = 114, - A7XX_PERF_GBIF_RESERVED_115 = 115, - A7XX_PERF_GBIF_RESERVED_116 = 116, - A7XX_PERF_GBIF_RESERVED_117 = 117, - A7XX_PERF_GBIF_RESERVED_118 = 118, - A7XX_PERF_GBIF_RESERVED_119 = 119, - A7XX_PERF_GBIF_RESERVED_120 = 120, - A7XX_PERF_GBIF_RESERVED_121 = 121, - A7XX_PERF_GBIF_RESERVED_122 = 122, - A7XX_PERF_GBIF_RESERVED_123 = 123, - A7XX_PERF_GBIF_RESERVED_124 = 124, - A7XX_PERF_GBIF_RESERVED_125 = 125, - A7XX_PERF_GBIF_RESERVED_126 = 126, - A7XX_PERF_GBIF_RESERVED_127 = 127, - A7XX_PERF_GBIF_RESERVED_128 = 128, - A7XX_PERF_GBIF_RESERVED_129 = 129, - A7XX_PERF_GBIF_RESERVED_130 = 130, - A7XX_PERF_GBIF_RESERVED_131 = 131, - A7XX_PERF_GBIF_RESERVED_132 = 132, - A7XX_PERF_GBIF_RESERVED_133 = 133, - A7XX_PERF_GBIF_RESERVED_134 = 134, - A7XX_PERF_GBIF_RESERVED_135 = 135, - A7XX_PERF_GBIF_RESERVED_136 = 136, - A7XX_PERF_GBIF_RESERVED_137 = 137, - A7XX_PERF_GBIF_RESERVED_138 = 138, - A7XX_PERF_GBIF_RESERVED_139 = 139, - A7XX_PERF_GBIF_RESERVED_140 = 140, - A7XX_PERF_GBIF_RESERVED_141 = 141, - A7XX_PERF_GBIF_RESERVED_142 = 142, - A7XX_PERF_GBIF_RESERVED_143 = 143, - A7XX_PERF_GBIF_RESERVED_144 = 144, - A7XX_PERF_GBIF_RESERVED_145 = 145, - A7XX_PERF_GBIF_RESERVED_146 = 146, - A7XX_PERF_GBIF_RESERVED_147 = 147, - A7XX_PERF_GBIF_RESERVED_148 = 148, - A7XX_PERF_GBIF_RESERVED_149 = 149, - A7XX_PERF_GBIF_RESERVED_150 = 150, - A7XX_PERF_GBIF_RESERVED_151 = 151, - A7XX_PERF_GBIF_RESERVED_152 = 152, - A7XX_PERF_GBIF_RESERVED_153 = 153, - A7XX_PERF_GBIF_RESERVED_154 = 154, - A7XX_PERF_GBIF_RESERVED_155 = 155, - A7XX_PERF_GBIF_RESERVED_156 = 156, - A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = 157, - A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = 158, - A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = 159, - A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = 160, - A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = 161, -}; - -enum a7xx_ufc_perfcounter_select { - A7XX_PERF_UFC_NEVER_COUNT = 0, - A7XX_PERF_UFC_BUSY_CYCLES = 1, - A7XX_PERF_UFC_READ_DATA_VBIF = 2, - A7XX_PERF_UFC_WRITE_DATA_VBIF = 3, - A7XX_PERF_UFC_READ_REQUEST_VBIF = 4, - A7XX_PERF_UFC_WRITE_REQUEST_VBIF = 5, - A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = 6, - A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = 7, - A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = 8, - A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = 9, - A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = 10, - A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = 11, - A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = 12, - A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = 13, - A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = 14, - A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = 15, - A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = 16, - A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = 17, - A7XX_PERF_UFC_MAIN_TP_RD_NRDY = 18, - A7XX_PERF_UFC_MAIN_TP_RD_RDY = 19, - A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = 20, - A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = 21, - A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = 22, - A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = 23, - A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = 24, - A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = 25, - A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = 26, - A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = 27, - A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = 28, - A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = 29, - A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = 30, - A7XX_PERF_UFC_LOCK_STALLED_CYCLES = 31, - A7XX_PERF_UFC_MISS_LATENCY_CYCLES = 32, - A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = 33, - A7XX_PERF_UFC_L1_CRE_REQUESTS = 34, - A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = 35, - A7XX_PERF_UFC_L1_CRE_FILTER_HIT = 36, - A7XX_PERF_UFC_L1_CRE_FILTER_MISS = 37, - A7XX_PERF_UFC_L1_SP_REQUESTS = 38, - A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = 39, - A7XX_PERF_UFC_L1_SP_FILTER_HIT = 40, - A7XX_PERF_UFC_L1_SP_FILTER_MISS = 41, - A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = 42, - A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = 43, - A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = 44, - A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = 45, - A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = 46, -}; - -enum a6xx_sequenced_thread_dist { - DIST_SCREEN_COORD = 0, - DIST_ALL_TO_RB0 = 1, -}; - -enum a6xx_single_prim_mode { - NO_FLUSH = 0, - FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, - FLUSH_PER_OVERLAP = 3, -}; - -enum a6xx_raster_mode { - TYPE_TILED = 0, - TYPE_WRITER = 1, -}; - -enum a6xx_raster_direction { - LR_TB = 0, - RL_TB = 1, - LR_BT = 2, - RB_BT = 3, -}; - -enum a6xx_render_mode { - RENDERING_PASS = 0, - BINNING_PASS = 1, -}; - -enum a6xx_buffers_location { - BUFFERS_IN_GMEM = 0, - BUFFERS_IN_SYSMEM = 3, -}; - -enum a6xx_lrz_dir_status { - LRZ_DIR_LE = 1, - LRZ_DIR_GE = 2, - LRZ_DIR_INVALID = 3, -}; - -enum a6xx_fragcoord_sample_mode { - FRAGCOORD_CENTER = 0, - FRAGCOORD_SAMPLE = 3, -}; - -enum a6xx_rotation { - ROTATE_0 = 0, - ROTATE_90 = 1, - ROTATE_180 = 2, - ROTATE_270 = 3, - ROTATE_HFLIP = 4, - ROTATE_VFLIP = 5, -}; - -enum a6xx_ccu_cache_size { - CCU_CACHE_SIZE_FULL = 0, - CCU_CACHE_SIZE_HALF = 1, - CCU_CACHE_SIZE_QUARTER = 2, - CCU_CACHE_SIZE_EIGHTH = 3, -}; - -enum a6xx_varying_interp_mode { - INTERP_SMOOTH = 0, - INTERP_FLAT = 1, - INTERP_ZERO = 2, - INTERP_ONE = 3, -}; - -enum a6xx_varying_ps_repl_mode { - PS_REPL_NONE = 0, - PS_REPL_S = 1, - PS_REPL_T = 2, - PS_REPL_ONE_MINUS_T = 3, -}; - -enum a6xx_threadsize { - THREAD64 = 0, - THREAD128 = 1, -}; - -enum a6xx_bindless_descriptor_size { - BINDLESS_DESCRIPTOR_16B = 1, - BINDLESS_DESCRIPTOR_64B = 3, -}; - -enum a6xx_isam_mode { - ISAMMODE_CL = 1, - ISAMMODE_GL = 2, -}; - -enum a7xx_cs_yalign { - CS_YALIGN_1 = 8, - CS_YALIGN_2 = 4, - CS_YALIGN_4 = 2, - CS_YALIGN_8 = 1, -}; - -enum a6xx_tex_filter { - A6XX_TEX_NEAREST = 0, - A6XX_TEX_LINEAR = 1, - A6XX_TEX_ANISO = 2, - A6XX_TEX_CUBIC = 3, -}; - -enum a6xx_tex_clamp { - A6XX_TEX_REPEAT = 0, - A6XX_TEX_CLAMP_TO_EDGE = 1, - A6XX_TEX_MIRROR_REPEAT = 2, - A6XX_TEX_CLAMP_TO_BORDER = 3, - A6XX_TEX_MIRROR_CLAMP = 4, -}; - -enum a6xx_tex_aniso { - A6XX_TEX_ANISO_1 = 0, - A6XX_TEX_ANISO_2 = 1, - A6XX_TEX_ANISO_4 = 2, - A6XX_TEX_ANISO_8 = 3, - A6XX_TEX_ANISO_16 = 4, -}; - -enum a6xx_reduction_mode { - A6XX_REDUCTION_MODE_AVERAGE = 0, - A6XX_REDUCTION_MODE_MIN = 1, - A6XX_REDUCTION_MODE_MAX = 2, -}; - -enum a6xx_tex_swiz { - A6XX_TEX_X = 0, - A6XX_TEX_Y = 1, - A6XX_TEX_Z = 2, - A6XX_TEX_W = 3, - A6XX_TEX_ZERO = 4, - A6XX_TEX_ONE = 5, -}; - -enum a6xx_tex_type { - A6XX_TEX_1D = 0, - A6XX_TEX_2D = 1, - A6XX_TEX_CUBE = 2, - A6XX_TEX_3D = 3, - A6XX_TEX_BUFFER = 4, -}; - -#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 -#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 -#define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010 -#define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020 -#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 -#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 -#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 -#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 -#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 -#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 -#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 -#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 -#define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000 -#define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000 -#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 -#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 -#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 -#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000 -#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 -#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 -#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 -#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 -#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 -#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 -#define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 -#define A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION 0x20000000 -#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 -#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 - -#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 -#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 -#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 -#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 -#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 -#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 -#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 -#define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100 -#define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200 -#define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400 -#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800 -#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000 -#define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000 -#define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000 -#define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 -#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 -#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 - -#define REG_A6XX_CP_RB_BASE 0x00000800 - -#define REG_A6XX_CP_RB_CNTL 0x00000802 - -#define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804 - -#define REG_A6XX_CP_RB_RPTR 0x00000806 - -#define REG_A6XX_CP_RB_WPTR 0x00000807 - -#define REG_A6XX_CP_SQE_CNTL 0x00000808 - -#define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 -#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 - -#define REG_A6XX_CP_HW_FAULT 0x00000821 - -#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 -#define REG_A6XX_CP_PROTECT_STATUS 0x00000824 - -#define REG_A6XX_CP_STATUS_1 0x00000825 - -#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 - -#define REG_A6XX_CP_MISC_CNTL 0x00000840 - -#define REG_A6XX_CP_APRIV_CNTL 0x00000844 -#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040 -#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020 -#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008 -#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004 -#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002 -#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001 - -#define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 - -#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 -#define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff -#define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; -} -#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 -#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; -} -#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 -#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; -} -#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 -#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; -} - -#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 -#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff -#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; -} -#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 -#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; -} - -#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 - -#define REG_A6XX_CP_CHICKEN_DBG 0x00000841 - -#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 - -#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 - -#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f -#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008 -#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 -#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 - -#define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_CP_SCRATCH_REG(unsigned int i0) { return 0x00000883 + 0x1*i0; } - -#define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_CP_PROTECT_REG(unsigned int i0) { return 0x00000850 + 0x1*i0; } -#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff -#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 -static inline unsigned int A6XX_CP_PROTECT_REG_BASE_ADDR(unsigned int val) -{ - return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; -} -#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 -#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 -static inline unsigned int A6XX_CP_PROTECT_REG_MASK_LEN(unsigned int val) -{ - return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; -} -#define A6XX_CP_PROTECT_REG_READ 0x80000000 - -#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 - -#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3 - -#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5 - -#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7 - -#define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab - -#define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*i0 ) - -#define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*i0 ) - -#define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 - -#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 - -#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 - -#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 - -#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 - -#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a - -#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b - -#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c - -#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d - -#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e - -#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f - -#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 - -#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 - -#define REG_A6XX_CP_IB1_BASE 0x00000928 - -#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a - -#define REG_A6XX_CP_IB2_BASE 0x0000092b - -#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d - -#define REG_A6XX_CP_SDS_BASE 0x0000092e - -#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 - -#define REG_A6XX_CP_MRB_BASE 0x00000931 - -#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 - -#define REG_A6XX_CP_VSD_BASE 0x00000934 - -#define REG_A6XX_CP_ROQ_RB_STAT 0x00000939 -#define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_RB_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_RB_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a -#define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_IB1_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_IB1_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b -#define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_IB2_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_IB2_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c -#define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_SDS_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_SDS_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d -#define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_MRB_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_MRB_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e -#define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff -#define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0 -static inline unsigned int A6XX_CP_ROQ_VSD_STAT_RPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK; -} -#define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000 -#define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_VSD_STAT_WPTR(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK; -} - -#define REG_A6XX_CP_IB1_DWORDS 0x00000943 - -#define REG_A6XX_CP_IB2_DWORDS 0x00000944 - -#define REG_A6XX_CP_SDS_DWORDS 0x00000945 - -#define REG_A6XX_CP_MRB_DWORDS 0x00000946 - -#define REG_A6XX_CP_VSD_DWORDS 0x00000947 - -#define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948 -#define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_RB_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK; -} - -#define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949 -#define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_IB1_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK; -} - -#define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a -#define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_IB2_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK; -} - -#define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b -#define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_SDS_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK; -} - -#define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c -#define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_MRB_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK; -} - -#define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d -#define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000 -#define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16 -static inline unsigned int A6XX_CP_ROQ_AVAIL_VSD_REM(unsigned int val) -{ - return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK; -} - -#define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980 - -#define REG_A6XX_CP_AHB_CNTL 0x0000098d - -#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 - -#define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00 -#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000 -#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12 -static inline unsigned int A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK; -} -#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700 -#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8 -static inline unsigned int A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK; -} -#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030 -#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4 -static inline unsigned int A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(unsigned int val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK; -} - -#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 - -#define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03 -#define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000 -#define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12 -static inline unsigned int A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK; -} -#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700 -#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8 -static inline unsigned int A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK; -} -#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030 -#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4 -static inline unsigned int A7XX_CP_APERTURE_CNTL_CD_CONTEXT(unsigned int val) -{ - return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK; -} - -#define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 - -#define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 - -#define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81 - -#define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82 - -#define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83 - -#define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84 - -#define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85 - -#define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86 - -#define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87 - -#define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88 - -#define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96 - -#define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97 - -#define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98 - -#define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a - -#define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b - -#define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0 - -#define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada - -#define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a - -#define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b - -#define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c - -#define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27 - -#define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28 - -#define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29 - -#define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a - -#define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31 - -#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 - -#define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35 - -#define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36 - -#define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40 - -#define REG_A6XX_CP_LPAC_SQE_CNTL 0x00000b81 - -#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 - -#define REG_A7XX_CP_AQE_INSTR_BASE_0 0x00000b70 - -#define REG_A7XX_CP_AQE_INSTR_BASE_1 0x00000b72 - -#define REG_A7XX_CP_AQE_APRIV_CNTL 0x00000b78 - -#define REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 0x00000ba8 - -#define REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 0x00000ba9 - -#define REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 0x00000bac - -#define REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 0x00000bad - -#define REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 0x00000bb0 - -#define REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 0x00000bb1 - -#define REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 0x00000bb4 - -#define REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 0x00000bb5 - -#define REG_A7XX_CP_AQE_STAT_ADDR_0 0x00000bb8 - -#define REG_A7XX_CP_AQE_STAT_ADDR_1 0x00000bb9 - -#define REG_A7XX_CP_AQE_STAT_DATA_0 0x00000bbc - -#define REG_A7XX_CP_AQE_STAT_DATA_1 0x00000bbd - -#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 - -#define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 - -#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 -#define REG_A6XX_RBBM_STATUS 0x00000210 -#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 -#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 -#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 -#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 -#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 -#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 -#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 -#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 -#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 -#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 -#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 -#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 -#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 -#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 -#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 -#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 -#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 -#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 -#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 -#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 -#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 -#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 -#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 -#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 - -#define REG_A6XX_RBBM_STATUS1 0x00000211 - -#define REG_A6XX_RBBM_STATUS2 0x00000212 - -#define REG_A6XX_RBBM_STATUS3 0x00000213 -#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 - -#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 - -#define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260 - -#define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284 - -#define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285 - -#define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286 - -#define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287 - -#define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 - -#define REG_A7XX_RBBM_SW_FUSE_INT_STATUS 0x000002c0 - -#define REG_A7XX_RBBM_SW_FUSE_INT_MASK 0x000002c1 - -#define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*i0 ) - -#define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 - -#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*i0 ) - -#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b - -#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e - -#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f - -#define REG_A6XX_RBBM_ISDB_CNT 0x00000533 - -#define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534 - -#define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535 - -#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 - -#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 - -#define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 - -#define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 - -#define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 - -#define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 - -#define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 - -#define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 - -#define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 - -#define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 - -#define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a - -#define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b - -#define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c - -#define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d - -#define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e - -#define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f - -#define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 - -#define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 - -#define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 - -#define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 - -#define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 - -#define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 - -#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 - -#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800 - -#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 - -#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 - -#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 - -#define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00 - -#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 - -#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 - -#define REG_A6XX_RBBM_GBIF_HALT 0x00000016 - -#define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 - -#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c -#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 - -#define REG_A7XX_RBBM_GBIF_HALT 0x00000016 - -#define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017 - -#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f - -#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 -#define REG_A6XX_RBBM_INT_0_MASK 0x00000038 -#define REG_A7XX_RBBM_INT_2_MASK 0x0000003a - -#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 - -#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 - -#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 - -#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 - -#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 - -#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad - -#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba - -#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb - -#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc - -#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd - -#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be - -#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca - -#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce - -#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 - -#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da - -#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de - -#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df - -#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 - -#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 - -#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea - -#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee - -#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa - -#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 - -#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 - -#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 - -#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 - -#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 - -#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 - -#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 - -#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a - -#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b - -#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c - -#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d - -#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e - -#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f - -#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 - -#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 - -#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 - -#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 - -#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 - -#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 - -#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 - -#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 - -#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 - -#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 - -#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a - -#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b - -#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c - -#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d - -#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e - -#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f - -#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 - -#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 - -#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 - -#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 -#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 - -#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 - -#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 - -#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 - -#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 - -#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 - -#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 - -#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 - -#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a - -#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b - -#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f - -#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 - -#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 -#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 -#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a - -#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e - -#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f - -#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; -} -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 -#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 -static inline unsigned int A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(unsigned int val) -{ - return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; -} - -#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f - -#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 - -#define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*i0 ) - -#define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8 -#define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001 - -#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 - -#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 - -#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 - -#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 - -#define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05 - -#define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07 - -#define REG_A6XX_UCHE_TRAP_BASE 0x00000e09 - -#define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b - -#define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d - -#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 - -#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 - -#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 -#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff -#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 -static inline unsigned int A6XX_UCHE_CLIENT_PF_PERFSEL(unsigned int val) -{ - return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; -} - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*i0 ) - -#define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a - -#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c - -#define REG_A6XX_VBIF_VERSION 0x00003000 - -#define REG_A6XX_VBIF_CLKON 0x00003001 -#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 - -#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a - -#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 - -#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 - -#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 - -#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 - -#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 -#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f -#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 -static inline unsigned int A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(unsigned int val) -{ - return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; -} - -#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 - -#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 -#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff -#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 -static inline unsigned int A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(unsigned int val) -{ - return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; -} - -#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c - -#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 - -#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 - -#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 - -#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 - -#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 - -#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 - -#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da - -#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db - -#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 - -#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 - -#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a - -#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 - -#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 - -#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 - -#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 - -#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 - -#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 - -#define REG_A6XX_GBIF_HALT 0x00003c45 - -#define REG_A6XX_GBIF_HALT_ACK 0x00003c46 - -#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 - -#define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1 - -#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 - -#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 - -#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 - -#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 - -#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 - -#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 - -#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 - -#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 - -#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca - -#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb - -#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc - -#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd - -#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce - -#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf - -#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 - -#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 - -#define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 - -#define REG_A6XX_VSC_BIN_SIZE 0x00000c02 -#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff -#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 -static inline unsigned int A6XX_VSC_BIN_SIZE_WIDTH(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; -} -#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 -#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 -static inline unsigned int A6XX_VSC_BIN_SIZE_HEIGHT(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; -} - -#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 - -#define REG_A6XX_VSC_BIN_COUNT 0x00000c06 -#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe -#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 -static inline unsigned int A6XX_VSC_BIN_COUNT_NX(unsigned int val) -{ - return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; -} -#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 -#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 -static inline unsigned int A6XX_VSC_BIN_COUNT_NY(unsigned int val) -{ - return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; -} - -#define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VSC_PIPE_CONFIG_REG(unsigned int i0) { return 0x00000c10 + 0x1*i0; } -#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff -#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 -static inline unsigned int A6XX_VSC_PIPE_CONFIG_REG_X(unsigned int val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 -#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 -static inline unsigned int A6XX_VSC_PIPE_CONFIG_REG_Y(unsigned int val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 -#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 -static inline unsigned int A6XX_VSC_PIPE_CONFIG_REG_W(unsigned int val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; -} -#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 -#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 -static inline unsigned int A6XX_VSC_PIPE_CONFIG_REG_H(unsigned int val) -{ - return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; -} - -#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 - -#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 - -#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 - -#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 - -#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 - -#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 - -#define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VSC_STATE_REG(unsigned int i0) { return 0x00000c38 + 0x1*i0; } - -#define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VSC_PRIM_STRM_SIZE_REG(unsigned int i0) { return 0x00000c58 + 0x1*i0; } - -#define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VSC_DRAW_STRM_SIZE_REG(unsigned int i0) { return 0x00000c78 + 0x1*i0; } - -#define REG_A7XX_VSC_UNKNOWN_0D08 0x00000d08 - -#define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10 - -#define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11 - -#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 - -#define REG_A6XX_GRAS_CL_CNTL 0x00008000 -#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 -#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 -#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 -#define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020 -#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 -#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 -#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 -#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 - -#define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 -#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; -} -#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 -#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 -static inline unsigned int A6XX_GRAS_VS_CL_CNTL_CULL_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; -} - -#define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 -#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; -} -#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 -#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 -static inline unsigned int A6XX_GRAS_DS_CL_CNTL_CULL_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; -} - -#define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 -#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; -} -#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 -#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 -static inline unsigned int A6XX_GRAS_GS_CL_CNTL_CULL_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; -} - -#define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 - -#define REG_A6XX_GRAS_CNTL 0x00008005 -#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 -#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 -#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 -#define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 -#define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 -#define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 -#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 -#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 -static inline unsigned int A6XX_GRAS_CNTL_COORD_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; -} -#define A6XX_GRAS_CNTL_UNK10 0x00000400 -#define A6XX_GRAS_CNTL_UNK11 0x00000800 - -#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(unsigned int val) -{ - return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; -} -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 -#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 -static inline unsigned int A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(unsigned int val) -{ - return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; -} - -#define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007 - -#define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008 - -#define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009 - -#define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a - -#define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b - -#define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c - -#define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*i0 ) - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_XOFFSET(unsigned int i0) { return 0x00008010 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_XOFFSET(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_XSCALE(unsigned int i0) { return 0x00008011 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_XSCALE(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_YOFFSET(unsigned int i0) { return 0x00008012 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_YOFFSET(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_YSCALE(unsigned int i0) { return 0x00008013 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_YSCALE(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_ZOFFSET(unsigned int i0) { return 0x00008014 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_ZOFFSET(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_VPORT_ZSCALE(unsigned int i0) { return 0x00008015 + 0x6*i0; } -#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff -#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_VPORT_ZSCALE(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; -} - -#define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_GRAS_CL_Z_CLAMP_MIN(unsigned int i0) { return 0x00008070 + 0x2*i0; } -#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff -#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_Z_CLAMP_MIN(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_CL_Z_CLAMP_MAX(unsigned int i0) { return 0x00008071 + 0x2*i0; } -#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff -#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 -static inline unsigned int A6XX_GRAS_CL_Z_CLAMP_MAX(float val) -{ - return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; -} - -#define REG_A6XX_GRAS_SU_CNTL 0x00008090 -#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 -#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 -#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 -#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 -#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 -static inline unsigned int A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) -{ - return ((((int)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; -} -#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 -#define A6XX_GRAS_SU_CNTL_UNK12 0x00001000 -#define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 -#define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 -static inline unsigned int A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) -{ - return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; -} -#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 -#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 -static inline unsigned int A6XX_GRAS_SU_CNTL_UNK15(unsigned int val) -{ - return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; -} -#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000 -#define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000 -#define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000 -#define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000 -#define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20 -static inline unsigned int A6XX_GRAS_SU_CNTL_UNK20(unsigned int val) -{ - return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK; -} - -#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 -#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff -#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) -{ - return ((((unsigned int)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; -} -#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 -#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 -static inline unsigned int A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) -{ - return ((((unsigned int)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; -} - -#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 -#define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff -#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_POINT_SIZE(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; -} - -#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 -#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 -#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) -{ - return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; -} - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 -#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; -} - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; -} - -#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff -#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) -{ - return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; -} - -#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline unsigned int A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008 - -#define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 -static inline unsigned int A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(unsigned int val) -{ - return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; -} -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 -#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 -static inline unsigned int A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(unsigned int val) -{ - return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; -} - -#define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a -#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 -#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 - -#define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b -#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 -#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 - -#define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c -#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 -#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 - -#define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d -#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 -#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 - -#define REG_A6XX_GRAS_SC_CNTL 0x000080a0 -#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 -#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; -} -#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 -#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 -static inline unsigned int A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; -} -#define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 -#define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 -static inline unsigned int A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; -} -#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 -#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 -static inline unsigned int A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; -} -#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 -#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 -static inline unsigned int A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; -} -#define A6XX_GRAS_SC_CNTL_UNK9 0x00000200 -#define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00 -#define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10 -static inline unsigned int A6XX_GRAS_SC_CNTL_ROTATION(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK; -} -#define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 - -#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 -#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f -#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 -static inline unsigned int A6XX_GRAS_BIN_CONTROL_BINW(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 -#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 -static inline unsigned int A6XX_GRAS_BIN_CONTROL_BINH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 -#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 -static inline unsigned int A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) -{ - return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 -#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 -#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 -static inline unsigned int A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) -{ - return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 -#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 -static inline unsigned int A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; -} -#define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000 - -#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 -#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004 -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008 - -#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 -#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 -#define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 -#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 - -#define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; -} - -#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; -} -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; -} - -#define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7 - -#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af - -#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(unsigned int i0) { return 0x000080b0 + 0x2*i0; } -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; -} -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(unsigned int i0) { return 0x000080b1 + 0x2*i0; } -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; -} -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 -#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(unsigned int i0) { return 0x000080d0 + 0x2*i0; } -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; -} -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; -} - -static inline unsigned int REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(unsigned int i0) { return 0x000080d1 + 0x2*i0; } -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; -} -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 -#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; -} -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; -} - -#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; -} -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 -#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; -} - -#define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4 - -#define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5 - -#define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6 - -#define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8 - -#define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9 - -#define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa - -#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 -#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 -#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 -#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 -#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 -#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 -#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 -#define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0 -#define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6 -static inline unsigned int A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) -{ - return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK; -} -#define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 -#define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 -#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800 -#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11 -static inline unsigned int A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK; -} - -#define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 -#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 -#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 -#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 -static inline unsigned int A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) -{ - return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; -} - -#define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 -#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; -} - -#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 - -#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 -#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff -#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 -static inline unsigned int A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 -#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 -static inline unsigned int A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 - -#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 -#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 - -#define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a -#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff -#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0 -static inline unsigned int A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(unsigned int val) -{ - return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK; -} -#define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000 -#define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16 -static inline unsigned int A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(unsigned int val) -{ - return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK; -} -#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000 -#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28 -static inline unsigned int A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(unsigned int val) -{ - return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; -} - -#define REG_A7XX_GRAS_LRZ_CNTL2 0x0000810b -#define A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR 0x00000001 -#define A7XX_GRAS_LRZ_CNTL2_FC_ENABLE 0x00000002 - -#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 - -#define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111 -#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff -#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0 -static inline unsigned int A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) -{ - return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK; -} - -#define REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO 0x00008113 -#define A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline unsigned int A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} -#define A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 0x00000008 - -#define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120 - -#define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121 - -#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 -#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 -#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 -#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 -#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_UNK4(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 -#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 -#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 -#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 -#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_UNK17(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 -#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 -#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_MASK(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 -#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 -#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 -static inline unsigned int A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) -{ - return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; -} -#define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000 - -#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 -#define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00 -#define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8 -static inline unsigned int A6XX_GRAS_2D_SRC_TL_X(int val) -{ - return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 -#define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00 -#define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8 -static inline unsigned int A6XX_GRAS_2D_SRC_BR_X(int val) -{ - return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 -#define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00 -#define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8 -static inline unsigned int A6XX_GRAS_2D_SRC_TL_Y(int val) -{ - return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 -#define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00 -#define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8 -static inline unsigned int A6XX_GRAS_2D_SRC_BR_Y(int val) -{ - return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_DST_TL 0x00008405 -#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff -#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_2D_DST_TL_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; -} -#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 -#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_2D_DST_TL_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_DST_BR 0x00008406 -#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff -#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_2D_DST_BR_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; -} -#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 -#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_2D_DST_BR_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 - -#define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 - -#define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 - -#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a -#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff -#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_2D_RESOLVE_CNTL_1_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; -} -#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 -#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; -} - -#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b -#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff -#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 -static inline unsigned int A6XX_GRAS_2D_RESOLVE_CNTL_2_X(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; -} -#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 -#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 -static inline unsigned int A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(unsigned int val) -{ - return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; -} - -#define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 -#define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 -#define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 - -#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 - -#define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*i0 ) - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*i0 ) - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*i0 ) - -#define REG_A6XX_RB_BIN_CONTROL 0x00008800 -#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f -#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 -static inline unsigned int A6XX_RB_BIN_CONTROL_BINW(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; -} -#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 -#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 -static inline unsigned int A6XX_RB_BIN_CONTROL_BINH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; -} -#define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 -#define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 -static inline unsigned int A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) -{ - return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; -} -#define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 -#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 -#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 -static inline unsigned int A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) -{ - return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; -} -#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 -#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 -static inline unsigned int A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; -} - -#define REG_A7XX_RB_BIN_CONTROL 0x00008800 -#define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f -#define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0 -static inline unsigned int A7XX_RB_BIN_CONTROL_BINW(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK; -} -#define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 -#define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8 -static inline unsigned int A7XX_RB_BIN_CONTROL_BINH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK; -} -#define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 -#define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 -static inline unsigned int A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) -{ - return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK; -} -#define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 -#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 -#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 -static inline unsigned int A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(unsigned int val) -{ - return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; -} - -#define REG_A6XX_RB_RENDER_CNTL 0x00008801 -#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 -#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 -static inline unsigned int A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; -} -#define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 -#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 -#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 -#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 -static inline unsigned int A6XX_RB_RENDER_CNTL_UNK8(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; -} -#define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 -#define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 -static inline unsigned int A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; -} -#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 -#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 -static inline unsigned int A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; -} -#define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 -#define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 -#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 -#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 -#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 -static inline unsigned int A6XX_RB_RENDER_CNTL_FLAG_MRTS(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; -} - -#define REG_A7XX_RB_RENDER_CNTL 0x00008801 -#define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 -#define A7XX_RB_RENDER_CNTL_BINNING 0x00000080 -#define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 -#define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 -static inline unsigned int A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) -{ - return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK; -} -#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 -#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 -static inline unsigned int A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) -{ - return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; -} -#define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 -#define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 - -#define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116 -#define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080 - -#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 -#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004 -#define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008 - -#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 -#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 -#define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 -#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 - -#define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; -} - -#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; -} -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; -} - -#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 -#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 -#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 -#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 -#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 -#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 -#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 -#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 -#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 -static inline unsigned int A6XX_RB_RENDER_CONTROL0_COORD_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; -} -#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 - -#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a -#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 -#define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002 -#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 -#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 -#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 -#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 -static inline unsigned int A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) -{ - return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; -} -#define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040 -#define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 -#define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 - -#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b -#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 -#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 -#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 -#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 - -#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c -#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f -#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 -static inline unsigned int A6XX_RB_FS_OUTPUT_CNTL1_MRT(unsigned int val) -{ - return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; -} - -#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d -#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT0(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT1(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT2(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT3(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT4(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT5(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT6(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; -} -#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline unsigned int A6XX_RB_RENDER_COMPONENTS_RT7(unsigned int val) -{ - return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; -} - -#define REG_A6XX_RB_DITHER_CNTL 0x0000880e -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; -} -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 -static inline unsigned int A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) -{ - return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; -} - -#define REG_A6XX_RB_SRGB_CNTL 0x0000880f -#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 -#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 - -#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 -#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 - -#define REG_A6XX_RB_UNKNOWN_8811 0x00008811 - -#define REG_A7XX_RB_UNKNOWN_8812 0x00008812 - -#define REG_A6XX_RB_UNKNOWN_8818 0x00008818 - -#define REG_A6XX_RB_UNKNOWN_8819 0x00008819 - -#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a - -#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b - -#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c - -#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d - -#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e - -#define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*i0 ) - -static inline unsigned int REG_A6XX_RB_MRT_CONTROL(unsigned int i0) { return 0x00008820 + 0x8*i0; } -#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 -#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 -#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 -#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 -#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 -static inline unsigned int A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) -{ - return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; -} -#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 -#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 -static inline unsigned int A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(unsigned int val) -{ - return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; -} - -static inline unsigned int REG_A6XX_RB_MRT_BLEND_CONTROL(unsigned int i0) { return 0x00008821 + 0x8*i0; } -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 -#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; -} -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 -#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 -static inline unsigned int A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) -{ - return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; -} - -static inline unsigned int REG_A6XX_RB_MRT_BUF_INFO(unsigned int i0) { return 0x00008822 + 0x8*i0; } -#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 -#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 -static inline unsigned int A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400 -#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 -#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 -static inline unsigned int A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} - -static inline unsigned int REG_A7XX_RB_MRT_BUF_INFO(unsigned int i0) { return 0x00008822 + 0x8*i0; } -#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; -} -#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 -#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 -static inline unsigned int A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; -} -#define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400 -#define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800 -#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 -#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 -static inline unsigned int A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; -} - -static inline unsigned int REG_A6XX_RB_MRT_PITCH(unsigned int i0) { return 0x00008823 + 0x8*i0; } -#define A6XX_RB_MRT_PITCH__MASK 0xffffffff -#define A6XX_RB_MRT_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_MRT_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; -} - -static inline unsigned int REG_A6XX_RB_MRT_ARRAY_PITCH(unsigned int i0) { return 0x00008824 + 0x8*i0; } -#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff -#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_MRT_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; -} - -static inline unsigned int REG_A6XX_RB_MRT_BASE(unsigned int i0) { return 0x00008825 + 0x8*i0; } - -static inline unsigned int REG_A6XX_RB_MRT_BASE_GMEM(unsigned int i0) { return 0x00008827 + 0x8*i0; } - -#define REG_A6XX_RB_BLEND_RED_F32 0x00008860 -#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_RED_F32__SHIFT 0 -static inline unsigned int A6XX_RB_BLEND_RED_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 -#define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 -static inline unsigned int A6XX_RB_BLEND_GREEN_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 -#define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 -static inline unsigned int A6XX_RB_BLEND_BLUE_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; -} - -#define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 -#define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff -#define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 -static inline unsigned int A6XX_RB_BLEND_ALPHA_F32(float val) -{ - return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; -} - -#define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff -#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 -static inline unsigned int A6XX_RB_ALPHA_CONTROL_ALPHA_REF(unsigned int val) -{ - return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; -} -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 -#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 -static inline unsigned int A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; -} - -#define REG_A6XX_RB_BLEND_CNTL 0x00008865 -#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff -#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 -static inline unsigned int A6XX_RB_BLEND_CNTL_ENABLE_BLEND(unsigned int val) -{ - return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; -} -#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 -#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 -#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 -#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 -#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 -#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 -static inline unsigned int A6XX_RB_BLEND_CNTL_SAMPLE_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; -} - -#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 -#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 -#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 -static inline unsigned int A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) -{ - return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; -} - -#define REG_A6XX_RB_DEPTH_CNTL 0x00008871 -#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 -#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 -#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c -#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 -static inline unsigned int A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; -} -#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 -#define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 -#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 - -#define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114 -#define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 - -#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 -#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline unsigned int A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} -#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 -#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 -static inline unsigned int A6XX_RB_DEPTH_BUFFER_INFO_UNK3(unsigned int val) -{ - return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; -} - -#define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872 -#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 -#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 -static inline unsigned int A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) -{ - return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; -} -#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 -#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 -static inline unsigned int A7XX_RB_DEPTH_BUFFER_INFO_UNK3(unsigned int val) -{ - return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; -} -#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060 -#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5 -static inline unsigned int A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) -{ - return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK; -} -#define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080 - -#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 -#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff -#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_DEPTH_BUFFER_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 -#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff -#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 - -#define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 -#define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff -#define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 -static inline unsigned int A6XX_RB_Z_BOUNDS_MIN(float val) -{ - return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; -} - -#define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 -#define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff -#define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 -static inline unsigned int A6XX_RB_Z_BOUNDS_MAX(float val) -{ - return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; -} - -#define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 -#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 -#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 -#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 -#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 -#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 -#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 -#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 -#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 -#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; -} -#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 -#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 -static inline unsigned int A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) -{ - return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; -} - -#define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115 -#define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001 - -#define REG_A6XX_RB_STENCIL_INFO 0x00008881 -#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 -#define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 - -#define REG_A7XX_RB_STENCIL_INFO 0x00008881 -#define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 -#define A7XX_RB_STENCIL_INFO_UNK1 0x00000002 -#define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c -#define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2 -static inline unsigned int A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) -{ - return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK; -} - -#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 -#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff -#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_STENCIL_BUFFER_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; -} - -#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 -#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff -#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 - -#define REG_A6XX_RB_STENCILREF 0x00008887 -#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff -#define A6XX_RB_STENCILREF_REF__SHIFT 0 -static inline unsigned int A6XX_RB_STENCILREF_REF(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; -} -#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 -#define A6XX_RB_STENCILREF_BFREF__SHIFT 8 -static inline unsigned int A6XX_RB_STENCILREF_BFREF(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; -} - -#define REG_A6XX_RB_STENCILMASK 0x00008888 -#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff -#define A6XX_RB_STENCILMASK_MASK__SHIFT 0 -static inline unsigned int A6XX_RB_STENCILMASK_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; -} -#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 -#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 -static inline unsigned int A6XX_RB_STENCILMASK_BFMASK(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; -} - -#define REG_A6XX_RB_STENCILWRMASK 0x00008889 -#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff -#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 -static inline unsigned int A6XX_RB_STENCILWRMASK_WRMASK(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; -} -#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 -#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 -static inline unsigned int A6XX_RB_STENCILWRMASK_BFWRMASK(unsigned int val) -{ - return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; -} - -#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 -#define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff -#define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 -static inline unsigned int A6XX_RB_WINDOW_OFFSET_X(unsigned int val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; -} -#define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 -#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 -static inline unsigned int A6XX_RB_WINDOW_OFFSET_Y(unsigned int val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 -#define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001 -#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 - -#define REG_A6XX_RB_LRZ_CNTL 0x00008898 -#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 - -#define REG_A7XX_RB_UNKNOWN_8899 0x00008899 - -#define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 -#define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff -#define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 -static inline unsigned int A6XX_RB_Z_CLAMP_MIN(float val) -{ - return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; -} - -#define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 -#define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff -#define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 -static inline unsigned int A6XX_RB_Z_CLAMP_MAX(float val) -{ - return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; -} - -#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 -#define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff -#define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 -static inline unsigned int A6XX_RB_UNKNOWN_88D0_UNK0(unsigned int val) -{ - return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; -} -#define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 -#define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 -static inline unsigned int A6XX_RB_UNKNOWN_88D0_UNK16(unsigned int val) -{ - return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; -} - -#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 -#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff -#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_SCISSOR_TL_X(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; -} -#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 -#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 -static inline unsigned int A6XX_RB_BLIT_SCISSOR_TL_Y(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; -} - -#define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 -#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff -#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_SCISSOR_BR_X(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; -} -#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 -#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 -static inline unsigned int A6XX_RB_BLIT_SCISSOR_BR_Y(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; -} - -#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 -#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f -#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 -static inline unsigned int A6XX_RB_BIN_CONTROL2_BINW(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; -} -#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 -#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 -static inline unsigned int A6XX_RB_BIN_CONTROL2_BINH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; -} - -#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 -#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff -#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 -static inline unsigned int A6XX_RB_WINDOW_OFFSET2_X(unsigned int val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; -} -#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 -#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 -static inline unsigned int A6XX_RB_WINDOW_OFFSET2_Y(unsigned int val) -{ - return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; -} - -#define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5 -#define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018 -#define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3 -static inline unsigned int A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK; -} - -#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 - -#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 -#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 -#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 -#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 -#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 -static inline unsigned int A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 -#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 -static inline unsigned int A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 -#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 -static inline unsigned int A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 - -#define REG_A6XX_RB_BLIT_DST 0x000088d8 - -#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da -#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff -#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_DST_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db -#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff -#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_DST_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc - -#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de -#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; -} -#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 -#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 -static inline unsigned int A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x7f)); - return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 - -#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 - -#define REG_A6XX_RB_BLIT_INFO 0x000088e3 -#define A6XX_RB_BLIT_INFO_UNK0 0x00000001 -#define A6XX_RB_BLIT_INFO_GMEM 0x00000002 -#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 -#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 -#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 -#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 -static inline unsigned int A6XX_RB_BLIT_INFO_CLEAR_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; -} -#define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300 -#define A6XX_RB_BLIT_INFO_LAST__SHIFT 8 -static inline unsigned int A6XX_RB_BLIT_INFO_LAST(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK; -} -#define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000 -#define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12 -static inline unsigned int A6XX_RB_BLIT_INFO_BUFFER_ID(unsigned int val) -{ - return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; -} - -#define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4 -#define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001 - -#define REG_A7XX_RB_CCU_CNTL2 0x000088e5 -#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001 -#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0 -static inline unsigned int A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(unsigned int val) -{ - return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK; -} -#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004 -#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2 -static inline unsigned int A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(unsigned int val) -{ - return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK; -} -#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00 -#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10 -static inline unsigned int A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) -{ - return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK; -} -#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000 -#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12 -static inline unsigned int A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK; -} -#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000 -#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21 -static inline unsigned int A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) -{ - return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK; -} -#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000 -#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23 -static inline unsigned int A7XX_RB_CCU_CNTL2_COLOR_OFFSET(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK; -} - -#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 - -#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 - -#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 -#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 -#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline unsigned int A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x7f)); - return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 - -#define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 -static inline unsigned int A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(unsigned int val) -{ - return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; -} -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 -#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline unsigned int A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x7f)); - return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*i0 ) - -static inline unsigned int REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(unsigned int i0) { return 0x00008903 + 0x3*i0; } - -static inline unsigned int REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(unsigned int i0) { return 0x00008905 + 0x3*i0; } -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; -} -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 -#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 -static inline unsigned int A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0x7f)); - return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 - -#define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 - -#define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 - -#define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 - -#define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 - -#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 -#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 -#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 -#define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 -#define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_UNK4(unsigned int val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 -#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 -#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 -#define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 -#define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_UNK17(unsigned int val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 -#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 -#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_MASK(unsigned int val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 -#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 -#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 -static inline unsigned int A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) -{ - return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; -} -#define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000 - -#define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 - -#define REG_A6XX_RB_2D_DST_INFO 0x00008c17 -#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 -#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 -static inline unsigned int A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; -} -#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 -static inline unsigned int A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; -} -#define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 -#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 -#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 -#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 -static inline unsigned int A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; -} -#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 -#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 -#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 -#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 -#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 -#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 -#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 -#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 -#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 -static inline unsigned int A6XX_RB_2D_DST_INFO_UNK23(unsigned int val) -{ - return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; -} -#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 - -#define REG_A6XX_RB_2D_DST 0x00008c18 - -#define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a -#define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff -#define A6XX_RB_2D_DST_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_2D_DST_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b - -#define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d -#define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff -#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_2D_DST_PLANE_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e - -#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 - -#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 -#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff -#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_2D_DST_FLAGS_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 - -#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 -#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff -#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 -static inline unsigned int A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; -} - -#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c - -#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d - -#define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e - -#define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f - -#define REG_A7XX_RB_UNKNOWN_8C34 0x00008c34 - -#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 - -#define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04 - -#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 - -#define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06 - -#define REG_A6XX_RB_CCU_CNTL 0x00008e07 -#define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 -#define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 -#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 -#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 -static inline unsigned int A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(unsigned int val) -{ - return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK; -} -#define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200 -#define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9 -static inline unsigned int A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(unsigned int val) -{ - return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; -} -#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00 -#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10 -static inline unsigned int A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) -{ - return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK; -} -#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 -#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 -static inline unsigned int A6XX_RB_CCU_CNTL_DEPTH_OFFSET(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; -} -#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000 -#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21 -static inline unsigned int A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) -{ - return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK; -} -#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 -#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 -static inline unsigned int A6XX_RB_CCU_CNTL_COLOR_OFFSET(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; -} - -#define REG_A7XX_RB_CCU_CNTL 0x00008e07 -#define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 -#define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 - -#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 -#define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 -#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 -#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 -static inline unsigned int A6XX_RB_NC_MODE_CNTL_LOWER_BIT(unsigned int val) -{ - return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; -} -#define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 -#define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 -#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 -#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 -static inline unsigned int A6XX_RB_NC_MODE_CNTL_UPPER_BIT(unsigned int val) -{ - return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; -} -#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 -#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 -#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 -static inline unsigned int A6XX_RB_NC_MODE_CNTL_UNK12(unsigned int val) -{ - return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; -} - -#define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09 - -#define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*i0 ) - -#define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*i0 ) - -#define REG_A6XX_RB_CMP_DBG_ECO_CNTL 0x00008e28 - -#define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*i0 ) - -#define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*i0 ) - -#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b - -#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d - -#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 - -#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 - -#define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79 - -#define REG_A6XX_VPC_GS_PARAM 0x00009100 -#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff -#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_PARAM_LINELENGTHLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; -} - -#define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; -} -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; -} -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; -} -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311 -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK; -} -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312 -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK; -} -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313 -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK; -} -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; -} -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 -#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 -static inline unsigned int A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; -} - -#define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 -#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; -} -#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; -} -#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 -#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; -} -#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; -} -#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 -#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; -} -#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; -} -#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314 -#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK; -} -#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK; -} -#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315 -#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK; -} -#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK; -} -#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316 -#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff -#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK; -} -#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 -#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK; -} -#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 -#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; -} - -#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 -#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 -#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 - -#define REG_A6XX_VPC_POLYGON_MODE 0x00009108 -#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 -#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 -static inline unsigned int A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) -{ - return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; -} - -#define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109 -#define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 -#define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 -#define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 -#define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008 - -#define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 -static inline unsigned int A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(unsigned int val) -{ - return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; -} -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 -static inline unsigned int A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(unsigned int val) -{ - return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; -} -#define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 -#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 -static inline unsigned int A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) -{ - return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; -} -#define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000 - -#define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b - -#define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c -#define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001 -#define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 -#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c -#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 -static inline unsigned int A7XX_VPC_MULTIVIEW_CNTL_VIEWS(unsigned int val) -{ - return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK; -} - -#define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VPC_VARYING_INTERP_MODE(unsigned int i0) { return 0x00009200 + 0x1*i0; } - -#define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VPC_VARYING_PS_REPL_MODE(unsigned int i0) { return 0x00009208 + 0x1*i0; } - -#define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 - -#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 - -#define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VPC_VAR_DISABLE(unsigned int i0) { return 0x00009212 + 0x1*i0; } - -#define REG_A6XX_VPC_SO_CNTL 0x00009216 -#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff -#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 -static inline unsigned int A6XX_VPC_SO_CNTL_ADDR(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; -} -#define A6XX_VPC_SO_CNTL_RESET 0x00010000 - -#define REG_A6XX_VPC_SO_PROG 0x00009217 -#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 -#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 -static inline unsigned int A6XX_VPC_SO_PROG_A_BUF(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; -} -#define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc -#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 -static inline unsigned int A6XX_VPC_SO_PROG_A_OFF(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; -} -#define A6XX_VPC_SO_PROG_A_EN 0x00000800 -#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 -#define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 -static inline unsigned int A6XX_VPC_SO_PROG_B_BUF(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; -} -#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 -#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 -static inline unsigned int A6XX_VPC_SO_PROG_B_OFF(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; -} -#define A6XX_VPC_SO_PROG_B_EN 0x00800000 - -#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 - -#define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*i0 ) - -static inline unsigned int REG_A6XX_VPC_SO_BUFFER_BASE(unsigned int i0) { return 0x0000921a + 0x7*i0; } - -static inline unsigned int REG_A6XX_VPC_SO_BUFFER_SIZE(unsigned int i0) { return 0x0000921c + 0x7*i0; } - -static inline unsigned int REG_A6XX_VPC_SO_BUFFER_STRIDE(unsigned int i0) { return 0x0000921d + 0x7*i0; } - -static inline unsigned int REG_A6XX_VPC_SO_BUFFER_OFFSET(unsigned int i0) { return 0x0000921e + 0x7*i0; } - -static inline unsigned int REG_A6XX_VPC_SO_FLUSH_BASE(unsigned int i0) { return 0x0000921f + 0x7*i0; } - -#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 -#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 - -#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 - -#define REG_A6XX_VPC_VS_PACK 0x00009301 -#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_VPC_VS_PACK_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; -} -#define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 -#define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_VS_PACK_POSITIONLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; -} -#define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 -#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_VS_PACK_PSIZELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; -} -#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 -#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 -static inline unsigned int A6XX_VPC_VS_PACK_EXTRAPOS(unsigned int val) -{ - return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; -} - -#define REG_A6XX_VPC_GS_PACK 0x00009302 -#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_VPC_GS_PACK_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; -} -#define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 -#define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_GS_PACK_POSITIONLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; -} -#define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 -#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_GS_PACK_PSIZELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; -} -#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 -#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 -static inline unsigned int A6XX_VPC_GS_PACK_EXTRAPOS(unsigned int val) -{ - return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; -} - -#define REG_A6XX_VPC_DS_PACK 0x00009303 -#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_VPC_DS_PACK_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; -} -#define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 -#define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_DS_PACK_POSITIONLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; -} -#define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 -#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 -static inline unsigned int A6XX_VPC_DS_PACK_PSIZELOC(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; -} -#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 -#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 -static inline unsigned int A6XX_VPC_DS_PACK_EXTRAPOS(unsigned int val) -{ - return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; -} - -#define REG_A6XX_VPC_CNTL_0 0x00009304 -#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff -#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 -static inline unsigned int A6XX_VPC_CNTL_0_NUMNONPOSVAR(unsigned int val) -{ - return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; -} -#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 -#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 -static inline unsigned int A6XX_VPC_CNTL_0_PRIMIDLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; -} -#define A6XX_VPC_CNTL_0_VARYING 0x00010000 -#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 -#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 -static inline unsigned int A6XX_VPC_CNTL_0_VIEWIDLOC(unsigned int val) -{ - return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; -} - -#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 -#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 -#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 -static inline unsigned int A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; -} -#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 -#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 -static inline unsigned int A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; -} -#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 -#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 -static inline unsigned int A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; -} -#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 -#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 -static inline unsigned int A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; -} -#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 -#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 -static inline unsigned int A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(unsigned int val) -{ - return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; -} - -#define REG_A6XX_VPC_SO_DISABLE 0x00009306 -#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 - -#define REG_A7XX_VPC_POLYGON_MODE2 0x00009307 -#define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003 -#define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0 -static inline unsigned int A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) -{ - return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK; -} - -#define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308 -#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff -#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 -static inline unsigned int A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(unsigned int val) -{ - return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; -} - -#define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309 -#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff -#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0 -static inline unsigned int A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(unsigned int val) -{ - return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK; -} - -#define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09 -#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff -#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 -static inline unsigned int A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(unsigned int val) -{ - return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; -} - -#define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 - -#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 - -#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 - -#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*i0 ) - -#define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*i0 ) - -#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 - -#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 -#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff -#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 -static inline unsigned int A6XX_PC_HS_INPUT_SIZE_SIZE(unsigned int val) -{ - return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; -} -#define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000 - -#define REG_A6XX_PC_TESS_CNTL 0x00009802 -#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 -#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 -static inline unsigned int A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) -{ - return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; -} -#define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c -#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 -static inline unsigned int A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) -{ - return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; -} - -#define REG_A6XX_PC_RESTART_INDEX 0x00009803 - -#define REG_A6XX_PC_MODE_CNTL 0x00009804 - -#define REG_A6XX_PC_POWER_CNTL 0x00009805 - -#define REG_A6XX_PC_PS_CNTL 0x00009806 -#define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001 - -#define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 -#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 -#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 -static inline unsigned int A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(unsigned int val) -{ - return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; -} - -#define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a -#define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 - -#define REG_A6XX_PC_DRAW_CMD 0x00009840 -#define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff -#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_PC_DRAW_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; -} - -#define REG_A6XX_PC_DISPATCH_CMD 0x00009841 -#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff -#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_PC_DISPATCH_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; -} - -#define REG_A6XX_PC_EVENT_CMD 0x00009842 -#define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 -#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 -static inline unsigned int A6XX_PC_EVENT_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; -} -#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f -#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 -static inline unsigned int A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) -{ - return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; -} - -#define REG_A6XX_PC_MARKER 0x00009880 - -#define REG_A6XX_PC_POLYGON_MODE 0x00009981 -#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 -#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 -static inline unsigned int A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) -{ - return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; -} - -#define REG_A7XX_PC_POLYGON_MODE 0x00009809 -#define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 -#define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0 -static inline unsigned int A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) -{ - return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK; -} - -#define REG_A6XX_PC_RASTER_CNTL 0x00009980 -#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 -#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 -static inline unsigned int A6XX_PC_RASTER_CNTL_STREAM(unsigned int val) -{ - return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; -} -#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 - -#define REG_A7XX_PC_RASTER_CNTL 0x00009107 -#define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 -#define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0 -static inline unsigned int A7XX_PC_RASTER_CNTL_STREAM(unsigned int val) -{ - return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK; -} -#define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004 - -#define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317 -#define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003 -#define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0 -static inline unsigned int A7XX_PC_RASTER_CNTL_V2_STREAM(unsigned int val) -{ - return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK; -} -#define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004 - -#define REG_A7XX_PC_TESS_PARAM_SIZE 0x00009885 - -#define REG_A7XX_PC_TESS_FACTOR_SIZE 0x00009886 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 -#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 -#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 -#define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 -#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 - -#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 -#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 -#define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 -#define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 -#define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 -#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 -#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 -static inline unsigned int A6XX_PC_VS_OUT_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; -} -#define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000 - -#define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 -#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 -#define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 -#define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 -#define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 -#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 -#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 -static inline unsigned int A6XX_PC_GS_OUT_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; -} -#define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000 - -#define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 -#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 -#define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 -#define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 -#define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 -#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 -#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 -static inline unsigned int A6XX_PC_HS_OUT_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; -} -#define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000 - -#define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 -#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff -#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; -} -#define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 -#define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 -#define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 -#define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 -#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 -#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 -static inline unsigned int A6XX_PC_DS_OUT_CNTL_CLIP_MASK(unsigned int val) -{ - return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; -} -#define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 -static inline unsigned int A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(unsigned int val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 -static inline unsigned int A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(unsigned int val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 -#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 -static inline unsigned int A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; -} -#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000 - -#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 -#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff -#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 -static inline unsigned int A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(unsigned int val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; -} - -#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 -#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 -#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 -#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c -#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 -static inline unsigned int A6XX_PC_MULTIVIEW_CNTL_VIEWS(unsigned int val) -{ - return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; -} - -#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 - -#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 -#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f -#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 -static inline unsigned int A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) -{ - return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; -} -#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 -#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 -static inline unsigned int A6XX_PC_2D_EVENT_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; -} - -#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 - -#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 - -#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 - -#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 - -#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 - -#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 - -#define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810 - -#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b -#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f -#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 -static inline unsigned int A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) -{ - return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; -} -#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 -#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 -static inline unsigned int A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) -{ - return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; -} -#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 -#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 -static inline unsigned int A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; -} -#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 -#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 -static inline unsigned int A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) -{ - return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; -} -#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 -#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 -static inline unsigned int A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) -{ - return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; -} -#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 -#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 - -#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c - -#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d - -#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 -#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff -#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 -static inline unsigned int A6XX_PC_VSTREAM_CONTROL_UNK0(unsigned int val) -{ - return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; -} -#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 -#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 -static inline unsigned int A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(unsigned int val) -{ - return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; -} -#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 -#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 -static inline unsigned int A6XX_PC_VSTREAM_CONTROL_VSC_N(unsigned int val) -{ - return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; -} - -#define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 - -#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 - -#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c -#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 - -#define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24 - -#define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*i0 ) - -#define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*i0 ) - -#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 - -#define REG_A6XX_VFD_CONTROL_0 0x0000a000 -#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f -#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_0_FETCH_CNT(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; -} -#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 -#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 -static inline unsigned int A6XX_VFD_CONTROL_0_DECODE_CNT(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; -} - -#define REG_A6XX_VFD_CONTROL_1 0x0000a001 -#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff -#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_1_REGID4VTX(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; -} -#define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 -static inline unsigned int A6XX_VFD_CONTROL_1_REGID4INST(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; -} -#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 -#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 -static inline unsigned int A6XX_VFD_CONTROL_1_REGID4PRIMID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; -} -#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 -#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 -static inline unsigned int A6XX_VFD_CONTROL_1_REGID4VIEWID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; -} - -#define REG_A6XX_VFD_CONTROL_2 0x0000a002 -#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff -#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; -} -#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 -static inline unsigned int A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; -} - -#define REG_A6XX_VFD_CONTROL_3 0x0000a003 -#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff -#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_3_REGID_DSPRIMID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; -} -#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 -static inline unsigned int A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; -} -#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 -#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 -static inline unsigned int A6XX_VFD_CONTROL_3_REGID_TESSX(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; -} -#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 -#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 -static inline unsigned int A6XX_VFD_CONTROL_3_REGID_TESSY(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; -} - -#define REG_A6XX_VFD_CONTROL_4 0x0000a004 -#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff -#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_4_UNK0(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; -} - -#define REG_A6XX_VFD_CONTROL_5 0x0000a005 -#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff -#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 -static inline unsigned int A6XX_VFD_CONTROL_5_REGID_GSHEADER(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; -} -#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 -#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 -static inline unsigned int A6XX_VFD_CONTROL_5_UNK8(unsigned int val) -{ - return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; -} - -#define REG_A6XX_VFD_CONTROL_6 0x0000a006 -#define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001 - -#define REG_A6XX_VFD_MODE_CNTL 0x0000a007 -#define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 -#define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 -static inline unsigned int A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) -{ - return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; -} - -#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 -#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 -#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 -#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c -#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 -static inline unsigned int A6XX_VFD_MULTIVIEW_CNTL_VIEWS(unsigned int val) -{ - return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; -} - -#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 -#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 -#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 - -#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e - -#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f - -#define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*i0 ) - -static inline unsigned int REG_A6XX_VFD_FETCH_BASE(unsigned int i0) { return 0x0000a010 + 0x4*i0; } - -static inline unsigned int REG_A6XX_VFD_FETCH_SIZE(unsigned int i0) { return 0x0000a012 + 0x4*i0; } - -static inline unsigned int REG_A6XX_VFD_FETCH_STRIDE(unsigned int i0) { return 0x0000a013 + 0x4*i0; } - -#define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_VFD_DECODE_INSTR(unsigned int i0) { return 0x0000a090 + 0x2*i0; } -#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f -#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 -static inline unsigned int A6XX_VFD_DECODE_INSTR_IDX(unsigned int val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; -} -#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 -#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 -static inline unsigned int A6XX_VFD_DECODE_INSTR_OFFSET(unsigned int val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; -} -#define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 -#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 -#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 -static inline unsigned int A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; -} -#define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 -#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 -static inline unsigned int A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; -} -#define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 -#define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 - -static inline unsigned int REG_A6XX_VFD_DECODE_STEP_RATE(unsigned int i0) { return 0x0000a091 + 0x2*i0; } - -#define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_VFD_DEST_CNTL_INSTR(unsigned int i0) { return 0x0000a0d0 + 0x1*i0; } -#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f -#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 -static inline unsigned int A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(unsigned int val) -{ - return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; -} -#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 -#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 -static inline unsigned int A6XX_VFD_DEST_CNTL_INSTR_REGID(unsigned int val) -{ - return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; -} - -#define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 - -#define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600 - -#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*i0 ) - -#define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*i0 ) - -#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 -#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 -#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 - -#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 - -#define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 -#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f -#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 -static inline unsigned int A6XX_SP_VS_PRIMITIVE_CNTL_OUT(unsigned int val) -{ - return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; -} -#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 -#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 -static inline unsigned int A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; -} - -#define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_VS_OUT_REG(unsigned int i0) { return 0x0000a803 + 0x1*i0; } -#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff -#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 -static inline unsigned int A6XX_SP_VS_OUT_REG_A_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; -} -#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline unsigned int A6XX_SP_VS_OUT_REG_A_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; -} -#define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 -static inline unsigned int A6XX_SP_VS_OUT_REG_B_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; -} -#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline unsigned int A6XX_SP_VS_OUT_REG_B_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; -} - -#define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_VS_VPC_DST_REG(unsigned int i0) { return 0x0000a813 + 0x1*i0; } -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline unsigned int A6XX_SP_VS_VPC_DST_REG_OUTLOC0(unsigned int val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline unsigned int A6XX_SP_VS_VPC_DST_REG_OUTLOC1(unsigned int val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline unsigned int A6XX_SP_VS_VPC_DST_REG_OUTLOC2(unsigned int val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline unsigned int A6XX_SP_VS_VPC_DST_REG_OUTLOC3(unsigned int val) -{ - return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b - -#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c - -#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e -#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f - -#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 -#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 - -#define REG_A6XX_SP_VS_CONFIG 0x0000a823 -#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_VS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_VS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_VS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 - -#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 -#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d - -#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 -#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 - -#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 - -#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 - -#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 - -#define REG_A6XX_SP_HS_OBJ_START 0x0000a834 - -#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 -#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 - -#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 -#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a - -#define REG_A6XX_SP_HS_CONFIG 0x0000a83b -#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_HS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_HS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_HS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c - -#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d -#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f - -#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 -#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 - -#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 - -#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 -#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f -#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 -static inline unsigned int A6XX_SP_DS_PRIMITIVE_CNTL_OUT(unsigned int val) -{ - return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; -} -#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 -#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 -static inline unsigned int A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; -} - -#define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_DS_OUT_REG(unsigned int i0) { return 0x0000a843 + 0x1*i0; } -#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff -#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 -static inline unsigned int A6XX_SP_DS_OUT_REG_A_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; -} -#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline unsigned int A6XX_SP_DS_OUT_REG_A_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; -} -#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 -static inline unsigned int A6XX_SP_DS_OUT_REG_B_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; -} -#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline unsigned int A6XX_SP_DS_OUT_REG_B_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; -} - -#define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_DS_VPC_DST_REG(unsigned int i0) { return 0x0000a853 + 0x1*i0; } -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline unsigned int A6XX_SP_DS_VPC_DST_REG_OUTLOC0(unsigned int val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline unsigned int A6XX_SP_DS_VPC_DST_REG_OUTLOC1(unsigned int val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline unsigned int A6XX_SP_DS_VPC_DST_REG_OUTLOC2(unsigned int val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline unsigned int A6XX_SP_DS_VPC_DST_REG_OUTLOC3(unsigned int val) -{ - return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b - -#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c - -#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e -#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f - -#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 -#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 - -#define REG_A6XX_SP_DS_CONFIG 0x0000a863 -#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_DS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_DS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_DS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 - -#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 -#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868 - -#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 -#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 - -#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 - -#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 - -#define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 -#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f -#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 -static inline unsigned int A6XX_SP_GS_PRIMITIVE_CNTL_OUT(unsigned int val) -{ - return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; -} -#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 -#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 -static inline unsigned int A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; -} - -#define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_GS_OUT_REG(unsigned int i0) { return 0x0000a874 + 0x1*i0; } -#define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff -#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 -static inline unsigned int A6XX_SP_GS_OUT_REG_A_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; -} -#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 -#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 -static inline unsigned int A6XX_SP_GS_OUT_REG_A_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; -} -#define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 -#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 -static inline unsigned int A6XX_SP_GS_OUT_REG_B_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; -} -#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 -#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 -static inline unsigned int A6XX_SP_GS_OUT_REG_B_COMPMASK(unsigned int val) -{ - return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; -} - -#define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_GS_VPC_DST_REG(unsigned int i0) { return 0x0000a884 + 0x1*i0; } -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 -static inline unsigned int A6XX_SP_GS_VPC_DST_REG_OUTLOC0(unsigned int val) -{ - return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; -} -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 -static inline unsigned int A6XX_SP_GS_VPC_DST_REG_OUTLOC1(unsigned int val) -{ - return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; -} -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 -static inline unsigned int A6XX_SP_GS_VPC_DST_REG_OUTLOC2(unsigned int val) -{ - return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; -} -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 -#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 -static inline unsigned int A6XX_SP_GS_VPC_DST_REG_OUTLOC3(unsigned int val) -{ - return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; -} - -#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c - -#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d - -#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f -#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 - -#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 -#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 - -#define REG_A6XX_SP_GS_CONFIG 0x0000a894 -#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_GS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_GS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_GS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 - -#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 -#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899 - -#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 - -#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 - -#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 - -#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 - -#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 - -#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa - -#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac - -#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae - -#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 -#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline unsigned int A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000 -#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 -#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 -#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 -#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 -#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 - -#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 - -#define REG_A6XX_SP_FS_OBJ_START 0x0000a983 - -#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 -#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 - -#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 -#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_BLEND_CNTL 0x0000a989 -#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff -#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 -static inline unsigned int A6XX_SP_BLEND_CNTL_ENABLE_BLEND(unsigned int val) -{ - return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; -} -#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 -#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 -#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 - -#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a -#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 -#define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 - -#define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b -#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f -#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT0(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT1(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT2(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT3(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT4(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT5(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT6(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; -} -#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 -#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 -static inline unsigned int A6XX_SP_FS_RENDER_COMPONENTS_RT7(unsigned int val) -{ - return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; -} - -#define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c -#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 -#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 -#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 -static inline unsigned int A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; -} -#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 -#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 -static inline unsigned int A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; -} -#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 -#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 -static inline unsigned int A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; -} - -#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d -#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f -#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 -static inline unsigned int A6XX_SP_FS_OUTPUT_CNTL1_MRT(unsigned int val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; -} - -#define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_FS_OUTPUT_REG(unsigned int i0) { return 0x0000a98e + 0x1*i0; } -#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff -#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 -static inline unsigned int A6XX_SP_FS_OUTPUT_REG_REGID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; -} -#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 - -#define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_FS_MRT_REG(unsigned int i0) { return 0x0000a996 + 0x1*i0; } -#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; -} -#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 -#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 -#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 - -#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e -#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 -#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 -static inline unsigned int A6XX_SP_FS_PREFETCH_CNTL_COUNT(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; -} -#define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 -#define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010 -#define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 -#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0 -#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6 -static inline unsigned int A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK; -} -#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000 -#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16 -static inline unsigned int A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK; -} - -#define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_FS_PREFETCH_CMD(unsigned int i0) { return 0x0000a99f + 0x1*i0; } -#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f -#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_SRC(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; -} -#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 -#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; -} -#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 -#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_TEX_ID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; -} -#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 -#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_DST(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; -} -#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 -#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_WRMASK(unsigned int val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; -} -#define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 -#define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000 -#define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000 -#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000 -#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29 -static inline unsigned int A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) -{ - return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; -} - -#define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*i0 ) - -static inline unsigned int REG_A7XX_SP_FS_PREFETCH_CMD(unsigned int i0) { return 0x0000a99f + 0x1*i0; } -#define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f -#define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_SRC(unsigned int val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK; -} -#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380 -#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(unsigned int val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; -} -#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00 -#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_TEX_ID(unsigned int val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; -} -#define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000 -#define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_DST(unsigned int val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK; -} -#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000 -#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_WRMASK(unsigned int val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; -} -#define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000 -#define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000 -#define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000 -#define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26 -static inline unsigned int A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) -{ - return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK; -} - -#define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*i0 ) - -static inline unsigned int REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(unsigned int i0) { return 0x0000a9a3 + 0x1*i0; } -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 -static inline unsigned int A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; -} -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 -static inline unsigned int A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(unsigned int val) -{ - return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; -} - -#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 - -#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 - -#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 -#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 -#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 -#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 -static inline unsigned int A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e -#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 -static inline unsigned int A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 -#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 -static inline unsigned int A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 -#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 -#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 -static inline unsigned int A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline unsigned int A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 -#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 -#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 - -#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 -#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f -#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 -static inline unsigned int A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(unsigned int val) -{ - return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; -} -#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 -#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 - -#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 - -#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 - -#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 - -#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 -#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff -#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 -static inline unsigned int A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(unsigned int val) -{ - assert(!(val & 0x1ff)); - return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; -} -#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 -#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 -static inline unsigned int A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(unsigned int val) -{ - return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; -} - -#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 - -#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 -#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff -#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 -static inline unsigned int A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; -} -#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 - -#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba - -#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb -#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_CS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_CS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_CS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc - -#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd -#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff -#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 -static inline unsigned int A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(unsigned int val) -{ - assert(!(val & 0x7ff)); - return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; -} - -#define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be - -#define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5 - -#define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 -#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff -#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 -static inline unsigned int A6XX_SP_CS_CNTL_0_WGIDCONSTID(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; -} -#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 -#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 -static inline unsigned int A6XX_SP_CS_CNTL_0_WGSIZECONSTID(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; -} -#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 -#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 -static inline unsigned int A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; -} -#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 -#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 -static inline unsigned int A6XX_SP_CS_CNTL_0_LOCALIDREGID(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; -} - -#define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 -#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff -#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 -static inline unsigned int A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(unsigned int val) -{ - return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; -} -#define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 -#define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 -#define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 -static inline unsigned int A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; -} -#define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 - -#define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3 -#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff -#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 -static inline unsigned int A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(unsigned int val) -{ - return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; -} -#define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100 -#define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8 -static inline unsigned int A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK; -} -#define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200 -#define A7XX_SP_CS_CNTL_1_UNK15 0x00008000 - -#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 - -#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 - -#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 - -#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 - -#define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000a9e8 + 0x2*i0; } -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*i0 ) - -static inline unsigned int REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000a9e8 + 0x2*i0; } -#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A6XX_SP_CS_IBO 0x0000a9f2 - -#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 - -#define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01 - -#define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02 -#define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001 - -#define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT0(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT1(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT2(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT3(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT4(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT5(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT6(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK; -} -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000 -#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28 -static inline unsigned int A7XX_SP_PS_ALIASED_COMPONENTS_RT7(unsigned int val) -{ - return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK; -} - -#define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2 - -#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 -#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 -#define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 -#define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 -static inline unsigned int A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) -{ - return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; -} -#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 - -#define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01 - -#define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02 - -#define REG_A6XX_SP_FS_CONFIG 0x0000ab04 -#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 -#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 -#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 -#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 -#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 -#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 -#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 -static inline unsigned int A6XX_SP_FS_CONFIG_NTEX(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; -} -#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 -#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 -static inline unsigned int A6XX_SP_FS_CONFIG_NSAMP(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; -} -#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 -#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 -static inline unsigned int A6XX_SP_FS_CONFIG_NIBO(unsigned int val) -{ - return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; -} - -#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 - -#define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000ab10 + 0x2*i0; } -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*i0 ) - -static inline unsigned int REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000ab0a + 0x2*i0; } -#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A6XX_SP_IBO 0x0000ab1a - -#define REG_A6XX_SP_IBO_COUNT 0x0000ab20 - -#define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22 - -#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 -#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 -#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 -#define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 -#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 -#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 -static inline unsigned int A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; -} -#define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 -#define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 -#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 -static inline unsigned int A6XX_SP_2D_DST_FORMAT_MASK(unsigned int val) -{ - return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; -} - -#define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf -#define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001 -#define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002 -#define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004 -#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 -#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 -static inline unsigned int A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; -} -#define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800 -#define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 -#define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 -static inline unsigned int A7XX_SP_2D_DST_FORMAT_MASK(unsigned int val) -{ - return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK; -} - -#define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 - -#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 - -#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 - -#define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 - -#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 -#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 - -#define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06 - -#define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08 - -#define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09 - -#define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a - -#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f -#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 -#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 -#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 -#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 -#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 -#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 - -#define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*i0 ) - -#define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*i0 ) - -#define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a - -#define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b - -#define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c - -#define REG_A7XX_SP_READ_SEL 0x0000ae6d -#define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000 -#define A7XX_SP_READ_SEL_LOCATION__SHIFT 18 -static inline unsigned int A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) -{ - return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK; -} -#define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000 -#define A7XX_SP_READ_SEL_PIPE__SHIFT 16 -static inline unsigned int A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) -{ - return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK; -} -#define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00 -#define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8 -static inline unsigned int A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) -{ - return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK; -} -#define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0 -#define A7XX_SP_READ_SEL_USPTP__SHIFT 4 -static inline unsigned int A7XX_SP_READ_SEL_USPTP(unsigned int val) -{ - return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK; -} -#define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f -#define A7XX_SP_READ_SEL_SPTP__SHIFT 0 -static inline unsigned int A7XX_SP_READ_SEL_SPTP(unsigned int val) -{ - return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK; -} - -#define REG_A7XX_SP_DBG_CNTL 0x0000ae71 - -#define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73 - -#define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*i0 ) - -#define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 - -#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 - -#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 - -#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 - -#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 - -#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 - -#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 -#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c -#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 -static inline unsigned int A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(unsigned int val) -{ - return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; -} - -#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 -#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 -#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 -static inline unsigned int A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; -} -#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 - -#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 - -#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 -#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 -#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 - -#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; -} - -#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; -} -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 -#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 -static inline unsigned int A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) -{ - return ((((int)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; -} - -#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 -#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff -#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 -static inline unsigned int A6XX_SP_TP_WINDOW_OFFSET_X(unsigned int val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 -#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 -static inline unsigned int A6XX_SP_TP_WINDOW_OFFSET_Y(unsigned int val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 -#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 -#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 -static inline unsigned int A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) -{ - return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; -} -#define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc -#define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 -static inline unsigned int A6XX_SP_TP_MODE_CNTL_UNK3(unsigned int val) -{ - return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; -} - -#define REG_A7XX_SP_UNKNOWN_B310 0x0000b310 - -#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 -#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 -static inline unsigned int A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 -static inline unsigned int A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 -#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 -#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 -#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 -static inline unsigned int A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 -#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 -#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 -static inline unsigned int A6XX_SP_PS_2D_SRC_INFO_UNK23(unsigned int val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; -} -#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 - -#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 -#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff -#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 -static inline unsigned int A6XX_SP_PS_2D_SRC_SIZE_WIDTH(unsigned int val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; -} -#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 -#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 -static inline unsigned int A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(unsigned int val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; -} - -#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 - -#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 -#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff -#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 -static inline unsigned int A6XX_SP_PS_2D_SRC_PITCH_UNK0(unsigned int val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; -} -#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 -#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 -static inline unsigned int A6XX_SP_PS_2D_SRC_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; -} - -#define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0 -#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff -#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; -} -#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 -#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 -static inline unsigned int A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; -} -#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 -#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 -static inline unsigned int A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; -} -#define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 -#define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 -#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 -#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 -static inline unsigned int A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; -} -#define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 -#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 -#define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 -static inline unsigned int A7XX_SP_PS_2D_SRC_INFO_UNK23(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK; -} -#define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 - -#define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1 -#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff -#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_SRC_SIZE_WIDTH(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; -} -#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 -#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 -static inline unsigned int A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; -} - -#define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2 - -#define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4 -#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff -#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_SRC_PITCH_UNK0(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; -} -#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 -#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 -static inline unsigned int A7XX_SP_PS_2D_SRC_PITCH_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; -} - -#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 - -#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 -#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff -#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 -static inline unsigned int A6XX_SP_PS_2D_SRC_PLANE_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; -} - -#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 - -#define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5 - -#define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7 -#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff -#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_SRC_PLANE_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; -} - -#define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8 - -#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca - -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 -static inline unsigned int A6XX_SP_PS_2D_SRC_FLAGS_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; -} - -#define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca - -#define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc -#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff -#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_SRC_FLAGS_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; -} - -#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd - -#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce - -#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf - -#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 - -#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 -#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff -#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 -static inline unsigned int A6XX_SP_WINDOW_OFFSET_X(unsigned int val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 -#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 -static inline unsigned int A6XX_SP_WINDOW_OFFSET_Y(unsigned int val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd - -#define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce - -#define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf - -#define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0 - -#define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1 -#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff -#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0 -static inline unsigned int A7XX_SP_PS_2D_WINDOW_OFFSET_X(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK; -} -#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000 -#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16 -static inline unsigned int A7XX_SP_PS_2D_WINDOW_OFFSET_Y(unsigned int val) -{ - return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2 - -#define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21 -#define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff -#define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0 -static inline unsigned int A7XX_SP_WINDOW_OFFSET_X(unsigned int val) -{ - return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK; -} -#define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 -#define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16 -static inline unsigned int A7XX_SP_WINDOW_OFFSET_Y(unsigned int val) -{ - return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 - -#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 - -#define REG_A6XX_TPL1_DBG_ECO_CNTL1 0x0000b602 -#define A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND 0x00040000 - -#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 -#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 -#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 -#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 -static inline unsigned int A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(unsigned int val) -{ - return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; -} -#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 -#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 -#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 -static inline unsigned int A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(unsigned int val) -{ - return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; -} -#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 -#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 -static inline unsigned int A6XX_TPL1_NC_MODE_CNTL_UNK6(unsigned int val) -{ - return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; -} - -#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c - -#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 - -#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 - -#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a - -#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b - -#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*i0 ) - -#define REG_A7XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*i0 ) - -#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 -#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_VS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 -#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_HS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 -#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_DS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 -#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_GS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_VS_CNTL 0x0000a827 -#define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_VS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f -#define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_HS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_DS_CNTL 0x0000a867 -#define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_DS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_GS_CNTL 0x0000a898 -#define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_GS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa -#define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001 - -#define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac - -#define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad - -#define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae -#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff -#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0 -static inline unsigned int A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(unsigned int val) -{ - return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK; -} -#define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100 -#define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200 - -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 - -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 - -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 - -#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 -#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 -#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 -static inline unsigned int A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; -} -#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 -#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc -#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 -static inline unsigned int A6XX_HLSQ_FS_CNTL_0_UNK2(unsigned int val) -{ - return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; -} - -#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 - -#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 -#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 -#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 -#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CONTROL_2_REG_FACEREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline unsigned int A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline unsigned int A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} -#define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 -#define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 -static inline unsigned int A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 -#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; -} -#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 -static inline unsigned int A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; -} -#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 -static inline unsigned int A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; -} -#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 -#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 -static inline unsigned int A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 -#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; -} -#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 -static inline unsigned int A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; -} -#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 -#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 -static inline unsigned int A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 -#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 -static inline unsigned int A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; -} - -#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 -static inline unsigned int A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; -} - -#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6 -#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 -#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 -static inline unsigned int A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; -} -#define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 -#define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc -#define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 -static inline unsigned int A7XX_HLSQ_FS_CNTL_0_UNK2(unsigned int val) -{ - return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK; -} - -#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 -#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 -#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; -} - -#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CONTROL_2_REG_FACEREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline unsigned int A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline unsigned int A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 -static inline unsigned int A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; -} - -#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 -static inline unsigned int A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 -static inline unsigned int A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 -static inline unsigned int A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; -} - -#define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca -#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; -} -#define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 -static inline unsigned int A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; -} -#define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 -static inline unsigned int A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; -} -#define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 -static inline unsigned int A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; -} - -#define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb -#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; -} -#define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 -static inline unsigned int A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; -} - -#define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd -#define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 -#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 -#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; -} -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 -#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 -#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 -#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 -#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 -#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 -#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; -} - -#define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 -#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff -#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; -} - -#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 -#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 -#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 -static inline unsigned int A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 -#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 -static inline unsigned int A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; -} -#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 -#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 -static inline unsigned int A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; -} - -#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 -#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; -} -#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 -#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 -#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 -static inline unsigned int A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; -} -#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a - -#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b - -#define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4 -#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 -#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; -} -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; -} -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; -} -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 -#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5 -#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6 -#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7 -#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8 -#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9 -#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; -} - -#define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da -#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff -#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; -} - -#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc - -#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd - -#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de - -#define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db -#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff -#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 -static inline unsigned int A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; -} -#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 -#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 -static inline unsigned int A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; -} -#define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800 -#define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000 -#define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000 -#define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000 -#define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27 -static inline unsigned int A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) -{ - return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK; -} - -#define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2 -static inline unsigned int A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK; -} -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000 -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12 -static inline unsigned int A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK; -} -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000 -#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22 -static inline unsigned int A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(unsigned int val) -{ - return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK; -} - -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 - -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 - -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 - -#define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000b9c0 + 0x2*i0; } -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 -#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f -#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 -static inline unsigned int A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(unsigned int val) -{ - return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; -} -#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 -#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 - -#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 -#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff -#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_DRAW_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; -} - -#define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 -#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff -#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_HLSQ_DISPATCH_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; -} - -#define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 -#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 -#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 -static inline unsigned int A6XX_HLSQ_EVENT_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; -} -#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f -#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 -static inline unsigned int A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) -{ - return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; -} - -#define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 -#define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 -#define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 -#define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 -#define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 -#define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 -#define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 -#define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 -#define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 -#define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 -#define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 -#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 -#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 -static inline unsigned int A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(unsigned int val) -{ - return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; -} -#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 -#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 -static inline unsigned int A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(unsigned int val) -{ - return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; -} - -#define REG_A7XX_HLSQ_DRAW_CMD 0x0000ab1c -#define A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff -#define A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A7XX_HLSQ_DRAW_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK; -} - -#define REG_A7XX_HLSQ_DISPATCH_CMD 0x0000ab1d -#define A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff -#define A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 -static inline unsigned int A7XX_HLSQ_DISPATCH_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; -} - -#define REG_A7XX_HLSQ_EVENT_CMD 0x0000ab1e -#define A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 -#define A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 -static inline unsigned int A7XX_HLSQ_EVENT_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK; -} -#define A7XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f -#define A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 -static inline unsigned int A7XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) -{ - return ((val) << A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A7XX_HLSQ_EVENT_CMD_EVENT__MASK; -} - -#define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f -#define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 -#define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 -#define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 -#define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 -#define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 -#define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 -#define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 -#define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 -#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00 -#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 -static inline unsigned int A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(unsigned int val) -{ - return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; -} -#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000 -#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17 -static inline unsigned int A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(unsigned int val) -{ - return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; -} - -#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 -#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A6XX_HLSQ_FS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; -} -#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 -#define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03 -#define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff -#define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 -static inline unsigned int A7XX_HLSQ_FS_CNTL_CONSTLEN(unsigned int val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK; -} -#define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100 -#define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 - -#define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*i0 ) - -#define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 -#define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 - -#define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*i0 ) - -static inline unsigned int REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(unsigned int i0) { return 0x0000bb20 + 0x2*i0; } -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 -static inline unsigned int A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) -{ - return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; -} -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline unsigned int A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(unsigned long long val) -{ - assert(!(val & 0x3)); - return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; -} - -#define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 -#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 -#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 -static inline unsigned int A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; -} -#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f -#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 -static inline unsigned int A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) -{ - return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; -} - -#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 - -#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 - -#define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04 - -#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 - -#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*i0 ) - -#define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 - -#define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 - -#define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2 - -#define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4 - -#define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6 - -#define REG_A6XX_CP_EVENT_START 0x0000d600 -#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff -#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_CP_EVENT_START_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; -} - -#define REG_A6XX_CP_EVENT_END 0x0000d601 -#define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff -#define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_CP_EVENT_END_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; -} - -#define REG_A6XX_CP_2D_EVENT_START 0x0000d700 -#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff -#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_CP_2D_EVENT_START_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; -} - -#define REG_A6XX_CP_2D_EVENT_END 0x0000d701 -#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff -#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 -static inline unsigned int A6XX_CP_2D_EVENT_END_STATE_ID(unsigned int val) -{ - return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; -} - -#define REG_A6XX_TEX_SAMP_0 0x00000000 -#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 -#define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 -#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 -static inline unsigned int A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) -{ - return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; -} -#define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 -#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 -static inline unsigned int A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) -{ - return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 -#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 -static inline unsigned int A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 -#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 -static inline unsigned int A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; -} -#define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 -#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 -static inline unsigned int A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) -{ - return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; -} -#define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 -#define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 -static inline unsigned int A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) -{ - return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; -} -#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 -#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 -static inline unsigned int A6XX_TEX_SAMP_0_LOD_BIAS(float val) -{ - return ((((int)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; -} - -#define REG_A6XX_TEX_SAMP_1 0x00000001 -#define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 -#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e -#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 -static inline unsigned int A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) -{ - return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; -} -#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 -#define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 -#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 -#define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 -#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 -static inline unsigned int A6XX_TEX_SAMP_1_MAX_LOD(float val) -{ - return ((((unsigned int)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; -} -#define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 -#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 -static inline unsigned int A6XX_TEX_SAMP_1_MIN_LOD(float val) -{ - return ((((unsigned int)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; -} - -#define REG_A6XX_TEX_SAMP_2 0x00000002 -#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 -#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 -static inline unsigned int A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) -{ - return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; -} -#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 -#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 -#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 -static inline unsigned int A6XX_TEX_SAMP_2_BCOLOR(unsigned int val) -{ - return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; -} - -#define REG_A6XX_TEX_SAMP_3 0x00000003 - -#define REG_A6XX_TEX_CONST_0 0x00000000 -#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 -#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) -{ - return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; -} -#define A6XX_TEX_CONST_0_SRGB 0x00000004 -#define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 -#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 -static inline unsigned int A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 -#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 -static inline unsigned int A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 -#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 -static inline unsigned int A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; -} -#define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 -#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 -static inline unsigned int A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) -{ - return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; -} -#define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 -#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 -static inline unsigned int A6XX_TEX_CONST_0_MIPLVLS(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; -} -#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 -#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 -#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 -#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 -static inline unsigned int A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) -{ - return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; -} -#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 -#define A6XX_TEX_CONST_0_FMT__SHIFT 22 -static inline unsigned int A6XX_TEX_CONST_0_FMT(enum a6xx_format val) -{ - return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; -} -#define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 -#define A6XX_TEX_CONST_0_SWAP__SHIFT 30 -static inline unsigned int A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) -{ - return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; -} - -#define REG_A6XX_TEX_CONST_1 0x00000001 -#define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff -#define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_1_WIDTH(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; -} -#define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 -#define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 -static inline unsigned int A6XX_TEX_CONST_1_HEIGHT(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; -} - -#define REG_A6XX_TEX_CONST_2 0x00000002 -#define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0 -#define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4 -static inline unsigned int A6XX_TEX_CONST_2_STRUCTSIZETEXELS(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK; -} -#define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000 -#define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16 -static inline unsigned int A6XX_TEX_CONST_2_STARTOFFSETTEXELS(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK; -} -#define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f -#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_2_PITCHALIGN(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; -} -#define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 -#define A6XX_TEX_CONST_2_PITCH__SHIFT 7 -static inline unsigned int A6XX_TEX_CONST_2_PITCH(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; -} -#define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 -#define A6XX_TEX_CONST_2_TYPE__SHIFT 29 -static inline unsigned int A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) -{ - return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; -} - -#define REG_A6XX_TEX_CONST_3 0x00000003 -#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff -#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_3_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; -} -#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 -#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 -static inline unsigned int A6XX_TEX_CONST_3_MIN_LAYERSZ(unsigned int val) -{ - assert(!(val & 0xfff)); - return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; -} -#define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 -#define A6XX_TEX_CONST_3_FLAG 0x10000000 - -#define REG_A6XX_TEX_CONST_4 0x00000004 -#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 -#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 -static inline unsigned int A6XX_TEX_CONST_4_BASE_LO(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; -} - -#define REG_A6XX_TEX_CONST_5 0x00000005 -#define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff -#define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_5_BASE_HI(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; -} -#define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 -#define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 -static inline unsigned int A6XX_TEX_CONST_5_DEPTH(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; -} - -#define REG_A6XX_TEX_CONST_6 0x00000006 -#define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff -#define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) -{ - return ((((unsigned int)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK; -} -#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 -#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 -static inline unsigned int A6XX_TEX_CONST_6_PLANE_PITCH(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; -} - -#define REG_A6XX_TEX_CONST_7 0x00000007 -#define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 -#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 -static inline unsigned int A6XX_TEX_CONST_7_FLAG_LO(unsigned int val) -{ - assert(!(val & 0x1f)); - return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; -} - -#define REG_A6XX_TEX_CONST_8 0x00000008 -#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff -#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_8_FLAG_HI(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; -} - -#define REG_A6XX_TEX_CONST_9 0x00000009 -#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff -#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(unsigned int val) -{ - assert(!(val & 0xf)); - return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; -} - -#define REG_A6XX_TEX_CONST_10 0x0000000a -#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f -#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 -static inline unsigned int A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(unsigned int val) -{ - assert(!(val & 0x3f)); - return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; -} -#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 -#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 -static inline unsigned int A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; -} -#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 -#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 -static inline unsigned int A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(unsigned int val) -{ - return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; -} - -#define REG_A6XX_TEX_CONST_11 0x0000000b - -#define REG_A6XX_TEX_CONST_12 0x0000000c - -#define REG_A6XX_TEX_CONST_13 0x0000000d - -#define REG_A6XX_TEX_CONST_14 0x0000000e - -#define REG_A6XX_TEX_CONST_15 0x0000000f - -#define REG_A6XX_UBO_0 0x00000000 -#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff -#define A6XX_UBO_0_BASE_LO__SHIFT 0 -static inline unsigned int A6XX_UBO_0_BASE_LO(unsigned int val) -{ - return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; -} - -#define REG_A6XX_UBO_1 0x00000001 -#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff -#define A6XX_UBO_1_BASE_HI__SHIFT 0 -static inline unsigned int A6XX_UBO_1_BASE_HI(unsigned int val) -{ - return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; -} -#define A6XX_UBO_1_SIZE__MASK 0xfffe0000 -#define A6XX_UBO_1_SIZE__SHIFT 17 -static inline unsigned int A6XX_UBO_1_SIZE(unsigned int val) -{ - return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; -} - -#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 - -#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 - -#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 - -#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 - -#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 - -#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 - -#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 - -#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 - -#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 - -#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 - -#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 - -#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 - -#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da - -#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db - -#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 -#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; -} -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 -#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 -static inline unsigned int A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(unsigned int val) -{ - return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; -} - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f - -#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 - -#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 - -#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 - -#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 - -#define REG_A7XX_CX_MISC_SW_FUSE_VALUE 0x00000400 -#define A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND 0x00000001 -#define A7XX_CX_MISC_SW_FUSE_VALUE_LPAC 0x00000002 -#define A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING 0x00000004 - -#ifdef __cplusplus -template constexpr inline uint16_t CMD_REGS[] = {}; -template constexpr inline uint16_t RP_BLIT_REGS[] = {}; -template<> constexpr inline uint16_t CMD_REGS[] = { - 0xc03, - 0xc04, - 0xc30, - 0xc31, - 0xc32, - 0xc33, - 0xc34, - 0xc35, - 0xc36, - 0xc37, - 0xce2, - 0xce3, - 0xce4, - 0xce5, - 0xce6, - 0xce7, - 0xe10, - 0xe11, - 0xe12, - 0xe17, - 0xe19, - 0x8008, - 0x8009, - 0x800a, - 0x800b, - 0x800c, - 0x8099, - 0x80a7, - 0x80af, - 0x80f4, - 0x80f5, - 0x80f5, - 0x80f6, - 0x80f6, - 0x80f7, - 0x80f8, - 0x80f9, - 0x80f9, - 0x80fa, - 0x80fa, - 0x80fb, - 0x810a, - 0x8110, - 0x8120, - 0x8121, - 0x8600, - 0x880e, - 0x8811, - 0x8818, - 0x8819, - 0x881a, - 0x881b, - 0x881c, - 0x881d, - 0x881e, - 0x8864, - 0x8891, - 0x8899, - 0x88e5, - 0x88f0, - 0x8927, - 0x8928, - 0x8c34, - 0x8e01, - 0x8e04, - 0x8e06, - 0x8e07, - 0x8e09, - 0x8e79, - 0x9218, - 0x9219, - 0x921a, - 0x921b, - 0x921c, - 0x921d, - 0x921e, - 0x921f, - 0x9220, - 0x9221, - 0x9222, - 0x9223, - 0x9224, - 0x9225, - 0x9226, - 0x9227, - 0x9228, - 0x9229, - 0x922a, - 0x922b, - 0x922c, - 0x922d, - 0x922e, - 0x922f, - 0x9230, - 0x9231, - 0x9232, - 0x9233, - 0x9234, - 0x9235, - 0x9236, - 0x9300, - 0x9600, - 0x9601, - 0x9602, - 0x9810, - 0x9811, - 0x9885, - 0x9886, - 0x9e24, - 0x9e72, - 0xa007, - 0xa009, - 0xa600, - 0xa82d, - 0xa82f, - 0xa868, - 0xa899, - 0xa8a0, - 0xa8a1, - 0xa8a2, - 0xa8a3, - 0xa8a4, - 0xa8a5, - 0xa8a6, - 0xa8a7, - 0xa8a8, - 0xa8a9, - 0xa8aa, - 0xa8ab, - 0xa8ac, - 0xa8ad, - 0xa8ae, - 0xa8af, - 0xa9a8, - 0xa9ac, - 0xa9ad, - 0xa9b0, - 0xa9b1, - 0xa9b2, - 0xa9b3, - 0xa9b4, - 0xa9b5, - 0xa9b6, - 0xa9b7, - 0xa9b8, - 0xa9b9, - 0xa9ba, - 0xa9bb, - 0xa9bc, - 0xa9bd, - 0xa9be, - 0xa9c2, - 0xa9c3, - 0xa9c5, - 0xa9cd, - 0xa9df, - 0xa9e2, - 0xa9e3, - 0xa9e6, - 0xa9e7, - 0xa9e8, - 0xa9e9, - 0xa9ea, - 0xa9eb, - 0xa9ec, - 0xa9ed, - 0xa9ee, - 0xa9ef, - 0xa9f0, - 0xa9f1, - 0xa9f2, - 0xa9f3, - 0xa9f4, - 0xa9f5, - 0xa9f6, - 0xa9f7, - 0xaa01, - 0xaa02, - 0xaa03, - 0xaaf2, - 0xab01, - 0xab02, - 0xab1a, - 0xab1b, - 0xab1f, - 0xab20, - 0xab22, - 0xae00, - 0xae03, - 0xae04, - 0xae06, - 0xae08, - 0xae09, - 0xae0a, - 0xae0f, - 0xae6a, - 0xae6b, - 0xae6c, - 0xae73, - 0xb180, - 0xb181, - 0xb182, - 0xb183, - 0xb302, - 0xb303, - 0xb309, - 0xb310, - 0xb600, - 0xb602, - 0xb608, - 0xb609, - 0xb60a, - 0xb60b, - 0xb60c, -}; -template<> constexpr inline uint16_t CMD_REGS[] = { - 0xc03, - 0xc04, - 0xc30, - 0xc31, - 0xc32, - 0xc33, - 0xc34, - 0xc35, - 0xc36, - 0xc37, - 0xe12, - 0xe17, - 0xe19, - 0x8099, - 0x80af, - 0x810a, - 0x8110, - 0x8600, - 0x880e, - 0x8811, - 0x8818, - 0x8819, - 0x881a, - 0x881b, - 0x881c, - 0x881d, - 0x881e, - 0x8864, - 0x8891, - 0x88f0, - 0x8927, - 0x8928, - 0x8e01, - 0x8e04, - 0x8e07, - 0x9210, - 0x9211, - 0x9218, - 0x9219, - 0x921a, - 0x921b, - 0x921c, - 0x921d, - 0x921e, - 0x921f, - 0x9220, - 0x9221, - 0x9222, - 0x9223, - 0x9224, - 0x9225, - 0x9226, - 0x9227, - 0x9228, - 0x9229, - 0x922a, - 0x922b, - 0x922c, - 0x922d, - 0x922e, - 0x922f, - 0x9230, - 0x9231, - 0x9232, - 0x9233, - 0x9234, - 0x9235, - 0x9236, - 0x9300, - 0x9600, - 0x9601, - 0x9602, - 0x9e08, - 0x9e09, - 0x9e72, - 0xa007, - 0xa009, - 0xa8a0, - 0xa8a1, - 0xa8a2, - 0xa8a3, - 0xa8a4, - 0xa8a5, - 0xa8a6, - 0xa8a7, - 0xa8a8, - 0xa8a9, - 0xa8aa, - 0xa8ab, - 0xa8ac, - 0xa8ad, - 0xa8ae, - 0xa8af, - 0xa9a8, - 0xa9b0, - 0xa9b1, - 0xa9b2, - 0xa9b3, - 0xa9b4, - 0xa9b5, - 0xa9b6, - 0xa9b7, - 0xa9b8, - 0xa9b9, - 0xa9ba, - 0xa9bb, - 0xa9bc, - 0xa9bd, - 0xa9c2, - 0xa9c3, - 0xa9e2, - 0xa9e3, - 0xa9e6, - 0xa9e7, - 0xa9e8, - 0xa9e9, - 0xa9ea, - 0xa9eb, - 0xa9ec, - 0xa9ed, - 0xa9ee, - 0xa9ef, - 0xa9f0, - 0xa9f1, - 0xaaf2, - 0xab1a, - 0xab1b, - 0xab20, - 0xae00, - 0xae03, - 0xae04, - 0xae0f, - 0xb180, - 0xb181, - 0xb182, - 0xb183, - 0xb302, - 0xb303, - 0xb309, - 0xb600, - 0xb602, - 0xb605, - 0xb987, - 0xb9d0, - 0xbb08, - 0xbb11, - 0xbb20, - 0xbb21, - 0xbb22, - 0xbb23, - 0xbb24, - 0xbb25, - 0xbb26, - 0xbb27, - 0xbb28, - 0xbb29, - 0xbe00, - 0xbe01, - 0xbe04, -}; -template<> constexpr inline uint16_t RP_BLIT_REGS[] = { - 0xc02, - 0xc06, - 0xc10, - 0xc11, - 0xc12, - 0xc13, - 0xc14, - 0xc15, - 0xc16, - 0xc17, - 0xc18, - 0xc19, - 0xc1a, - 0xc1b, - 0xc1c, - 0xc1d, - 0xc1e, - 0xc1f, - 0xc20, - 0xc21, - 0xc22, - 0xc23, - 0xc24, - 0xc25, - 0xc26, - 0xc27, - 0xc28, - 0xc29, - 0xc2a, - 0xc2b, - 0xc2c, - 0xc2d, - 0xc2e, - 0xc2f, - 0xc38, - 0xc39, - 0xc3a, - 0xc3b, - 0xc3c, - 0xc3d, - 0xc3e, - 0xc3f, - 0xc40, - 0xc41, - 0xc42, - 0xc43, - 0xc44, - 0xc45, - 0xc46, - 0xc47, - 0xc48, - 0xc49, - 0xc4a, - 0xc4b, - 0xc4c, - 0xc4d, - 0xc4e, - 0xc4f, - 0xc50, - 0xc51, - 0xc52, - 0xc53, - 0xc54, - 0xc55, - 0xc56, - 0xc57, - 0xd08, - 0x8000, - 0x8001, - 0x8002, - 0x8003, - 0x8004, - 0x8005, - 0x8006, - 0x8007, - 0x8010, - 0x8011, - 0x8012, - 0x8013, - 0x8014, - 0x8015, - 0x8016, - 0x8017, - 0x8018, - 0x8019, - 0x801a, - 0x801b, - 0x801c, - 0x801d, - 0x801e, - 0x801f, - 0x8020, - 0x8021, - 0x8022, - 0x8023, - 0x8024, - 0x8025, - 0x8026, - 0x8027, - 0x8028, - 0x8029, - 0x802a, - 0x802b, - 0x802c, - 0x802d, - 0x802e, - 0x802f, - 0x8030, - 0x8031, - 0x8032, - 0x8033, - 0x8034, - 0x8035, - 0x8036, - 0x8037, - 0x8038, - 0x8039, - 0x803a, - 0x803b, - 0x803c, - 0x803d, - 0x803e, - 0x803f, - 0x8040, - 0x8041, - 0x8042, - 0x8043, - 0x8044, - 0x8045, - 0x8046, - 0x8047, - 0x8048, - 0x8049, - 0x804a, - 0x804b, - 0x804c, - 0x804d, - 0x804e, - 0x804f, - 0x8050, - 0x8051, - 0x8052, - 0x8053, - 0x8054, - 0x8055, - 0x8056, - 0x8057, - 0x8058, - 0x8059, - 0x805a, - 0x805b, - 0x805c, - 0x805d, - 0x805e, - 0x805f, - 0x8060, - 0x8061, - 0x8062, - 0x8063, - 0x8064, - 0x8065, - 0x8066, - 0x8067, - 0x8068, - 0x8069, - 0x806a, - 0x806b, - 0x806c, - 0x806d, - 0x806e, - 0x806f, - 0x8070, - 0x8071, - 0x8072, - 0x8073, - 0x8074, - 0x8075, - 0x8076, - 0x8077, - 0x8078, - 0x8079, - 0x807a, - 0x807b, - 0x807c, - 0x807d, - 0x807e, - 0x807f, - 0x8080, - 0x8081, - 0x8082, - 0x8083, - 0x8084, - 0x8085, - 0x8086, - 0x8087, - 0x8088, - 0x8089, - 0x808a, - 0x808b, - 0x808c, - 0x808d, - 0x808e, - 0x808f, - 0x8090, - 0x8091, - 0x8092, - 0x8094, - 0x8095, - 0x8096, - 0x8097, - 0x8098, - 0x809b, - 0x809c, - 0x809d, - 0x80a0, - 0x80a1, - 0x80a2, - 0x80a3, - 0x80a4, - 0x80a5, - 0x80a6, - 0x80b0, - 0x80b1, - 0x80b2, - 0x80b3, - 0x80b4, - 0x80b5, - 0x80b6, - 0x80b7, - 0x80b8, - 0x80b9, - 0x80ba, - 0x80bb, - 0x80bc, - 0x80bd, - 0x80be, - 0x80bf, - 0x80c0, - 0x80c1, - 0x80c2, - 0x80c3, - 0x80c4, - 0x80c5, - 0x80c6, - 0x80c7, - 0x80c8, - 0x80c9, - 0x80ca, - 0x80cb, - 0x80cc, - 0x80cd, - 0x80ce, - 0x80cf, - 0x80d0, - 0x80d1, - 0x80d2, - 0x80d3, - 0x80d4, - 0x80d5, - 0x80d6, - 0x80d7, - 0x80d8, - 0x80d9, - 0x80da, - 0x80db, - 0x80dc, - 0x80dd, - 0x80de, - 0x80df, - 0x80e0, - 0x80e1, - 0x80e2, - 0x80e3, - 0x80e4, - 0x80e5, - 0x80e6, - 0x80e7, - 0x80e8, - 0x80e9, - 0x80ea, - 0x80eb, - 0x80ec, - 0x80ed, - 0x80ee, - 0x80ef, - 0x80f0, - 0x80f1, - 0x8100, - 0x8101, - 0x8102, - 0x8103, - 0x8104, - 0x8105, - 0x8106, - 0x8107, - 0x8109, - 0x810b, - 0x8113, - 0x8114, - 0x8115, - 0x8116, - 0x8400, - 0x8401, - 0x8402, - 0x8403, - 0x8404, - 0x8405, - 0x8406, - 0x840a, - 0x840b, - 0x8800, - 0x8801, - 0x8802, - 0x8803, - 0x8804, - 0x8805, - 0x8806, - 0x8809, - 0x880a, - 0x880b, - 0x880c, - 0x880d, - 0x880f, - 0x8810, - 0x8812, - 0x8820, - 0x8821, - 0x8822, - 0x8823, - 0x8824, - 0x8825, - 0x8826, - 0x8827, - 0x8828, - 0x8829, - 0x882a, - 0x882b, - 0x882c, - 0x882d, - 0x882e, - 0x882f, - 0x8830, - 0x8831, - 0x8832, - 0x8833, - 0x8834, - 0x8835, - 0x8836, - 0x8837, - 0x8838, - 0x8839, - 0x883a, - 0x883b, - 0x883c, - 0x883d, - 0x883e, - 0x883f, - 0x8840, - 0x8841, - 0x8842, - 0x8843, - 0x8844, - 0x8845, - 0x8846, - 0x8847, - 0x8848, - 0x8849, - 0x884a, - 0x884b, - 0x884c, - 0x884d, - 0x884e, - 0x884f, - 0x8850, - 0x8851, - 0x8852, - 0x8853, - 0x8854, - 0x8855, - 0x8856, - 0x8857, - 0x8858, - 0x8859, - 0x885a, - 0x885b, - 0x885c, - 0x885d, - 0x885e, - 0x885f, - 0x8860, - 0x8861, - 0x8862, - 0x8863, - 0x8865, - 0x8870, - 0x8871, - 0x8872, - 0x8873, - 0x8874, - 0x8875, - 0x8876, - 0x8877, - 0x8878, - 0x8879, - 0x8880, - 0x8881, - 0x8882, - 0x8883, - 0x8884, - 0x8885, - 0x8886, - 0x8887, - 0x8888, - 0x8889, - 0x8890, - 0x8898, - 0x88c0, - 0x88c1, - 0x88d0, - 0x88d1, - 0x88d2, - 0x88d3, - 0x88d4, - 0x88d5, - 0x88d6, - 0x88d7, - 0x88d8, - 0x88d9, - 0x88da, - 0x88db, - 0x88dc, - 0x88dd, - 0x88de, - 0x88df, - 0x88e0, - 0x88e1, - 0x88e2, - 0x88e3, - 0x88e4, - 0x8900, - 0x8901, - 0x8902, - 0x8903, - 0x8904, - 0x8905, - 0x8906, - 0x8907, - 0x8908, - 0x8909, - 0x890a, - 0x890b, - 0x890c, - 0x890d, - 0x890e, - 0x890f, - 0x8910, - 0x8911, - 0x8912, - 0x8913, - 0x8914, - 0x8915, - 0x8916, - 0x8917, - 0x8918, - 0x8919, - 0x891a, - 0x8c00, - 0x8c01, - 0x8c17, - 0x8c18, - 0x8c19, - 0x8c1a, - 0x8c1b, - 0x8c1c, - 0x8c1d, - 0x8c1e, - 0x8c1f, - 0x8c20, - 0x8c21, - 0x8c22, - 0x8c23, - 0x8c24, - 0x8c25, - 0x8c2c, - 0x8c2d, - 0x8c2e, - 0x8c2f, - 0x9101, - 0x9102, - 0x9103, - 0x9104, - 0x9105, - 0x9106, - 0x9107, - 0x9108, - 0x9109, - 0x910a, - 0x910b, - 0x910c, - 0x9200, - 0x9201, - 0x9202, - 0x9203, - 0x9204, - 0x9205, - 0x9206, - 0x9207, - 0x9208, - 0x9209, - 0x920a, - 0x920b, - 0x920c, - 0x920d, - 0x920e, - 0x920f, - 0x9212, - 0x9213, - 0x9214, - 0x9215, - 0x9216, - 0x9217, - 0x9301, - 0x9302, - 0x9303, - 0x9304, - 0x9305, - 0x9306, - 0x9307, - 0x9308, - 0x9309, - 0x9311, - 0x9312, - 0x9313, - 0x9314, - 0x9315, - 0x9316, - 0x9317, - 0x9800, - 0x9801, - 0x9802, - 0x9803, - 0x9804, - 0x9805, - 0x9806, - 0x9808, - 0x9809, - 0x9b00, - 0x9b01, - 0x9b02, - 0x9b03, - 0x9b04, - 0x9b05, - 0x9b07, - 0x9b08, - 0x9b09, - 0xa000, - 0xa001, - 0xa002, - 0xa003, - 0xa004, - 0xa005, - 0xa006, - 0xa008, - 0xa00e, - 0xa00f, - 0xa010, - 0xa011, - 0xa012, - 0xa013, - 0xa014, - 0xa015, - 0xa016, - 0xa017, - 0xa018, - 0xa019, - 0xa01a, - 0xa01b, - 0xa01c, - 0xa01d, - 0xa01e, - 0xa01f, - 0xa020, - 0xa021, - 0xa022, - 0xa023, - 0xa024, - 0xa025, - 0xa026, - 0xa027, - 0xa028, - 0xa029, - 0xa02a, - 0xa02b, - 0xa02c, - 0xa02d, - 0xa02e, - 0xa02f, - 0xa030, - 0xa031, - 0xa032, - 0xa033, - 0xa034, - 0xa035, - 0xa036, - 0xa037, - 0xa038, - 0xa039, - 0xa03a, - 0xa03b, - 0xa03c, - 0xa03d, - 0xa03e, - 0xa03f, - 0xa040, - 0xa041, - 0xa042, - 0xa043, - 0xa044, - 0xa045, - 0xa046, - 0xa047, - 0xa048, - 0xa049, - 0xa04a, - 0xa04b, - 0xa04c, - 0xa04d, - 0xa04e, - 0xa04f, - 0xa050, - 0xa051, - 0xa052, - 0xa053, - 0xa054, - 0xa055, - 0xa056, - 0xa057, - 0xa058, - 0xa059, - 0xa05a, - 0xa05b, - 0xa05c, - 0xa05d, - 0xa05e, - 0xa05f, - 0xa060, - 0xa061, - 0xa062, - 0xa063, - 0xa064, - 0xa065, - 0xa066, - 0xa067, - 0xa068, - 0xa069, - 0xa06a, - 0xa06b, - 0xa06c, - 0xa06d, - 0xa06e, - 0xa06f, - 0xa070, - 0xa071, - 0xa072, - 0xa073, - 0xa074, - 0xa075, - 0xa076, - 0xa077, - 0xa078, - 0xa079, - 0xa07a, - 0xa07b, - 0xa07c, - 0xa07d, - 0xa07e, - 0xa07f, - 0xa080, - 0xa081, - 0xa082, - 0xa083, - 0xa084, - 0xa085, - 0xa086, - 0xa087, - 0xa088, - 0xa089, - 0xa08a, - 0xa08b, - 0xa08c, - 0xa08d, - 0xa08e, - 0xa08f, - 0xa090, - 0xa091, - 0xa092, - 0xa093, - 0xa094, - 0xa095, - 0xa096, - 0xa097, - 0xa098, - 0xa099, - 0xa09a, - 0xa09b, - 0xa09c, - 0xa09d, - 0xa09e, - 0xa09f, - 0xa0a0, - 0xa0a1, - 0xa0a2, - 0xa0a3, - 0xa0a4, - 0xa0a5, - 0xa0a6, - 0xa0a7, - 0xa0a8, - 0xa0a9, - 0xa0aa, - 0xa0ab, - 0xa0ac, - 0xa0ad, - 0xa0ae, - 0xa0af, - 0xa0b0, - 0xa0b1, - 0xa0b2, - 0xa0b3, - 0xa0b4, - 0xa0b5, - 0xa0b6, - 0xa0b7, - 0xa0b8, - 0xa0b9, - 0xa0ba, - 0xa0bb, - 0xa0bc, - 0xa0bd, - 0xa0be, - 0xa0bf, - 0xa0c0, - 0xa0c1, - 0xa0c2, - 0xa0c3, - 0xa0c4, - 0xa0c5, - 0xa0c6, - 0xa0c7, - 0xa0c8, - 0xa0c9, - 0xa0ca, - 0xa0cb, - 0xa0cc, - 0xa0cd, - 0xa0ce, - 0xa0cf, - 0xa0d0, - 0xa0d1, - 0xa0d2, - 0xa0d3, - 0xa0d4, - 0xa0d5, - 0xa0d6, - 0xa0d7, - 0xa0d8, - 0xa0d9, - 0xa0da, - 0xa0db, - 0xa0dc, - 0xa0dd, - 0xa0de, - 0xa0df, - 0xa0e0, - 0xa0e1, - 0xa0e2, - 0xa0e3, - 0xa0e4, - 0xa0e5, - 0xa0e6, - 0xa0e7, - 0xa0e8, - 0xa0e9, - 0xa0ea, - 0xa0eb, - 0xa0ec, - 0xa0ed, - 0xa0ee, - 0xa0ef, - 0xa0f8, - 0xa800, - 0xa802, - 0xa803, - 0xa804, - 0xa805, - 0xa806, - 0xa807, - 0xa808, - 0xa809, - 0xa80a, - 0xa80b, - 0xa80c, - 0xa80d, - 0xa80e, - 0xa80f, - 0xa810, - 0xa811, - 0xa812, - 0xa813, - 0xa814, - 0xa815, - 0xa816, - 0xa817, - 0xa818, - 0xa819, - 0xa81a, - 0xa81b, - 0xa81c, - 0xa81d, - 0xa81e, - 0xa81f, - 0xa820, - 0xa821, - 0xa822, - 0xa823, - 0xa824, - 0xa825, - 0xa827, - 0xa830, - 0xa831, - 0xa832, - 0xa833, - 0xa834, - 0xa835, - 0xa836, - 0xa837, - 0xa838, - 0xa839, - 0xa83a, - 0xa83b, - 0xa83c, - 0xa83d, - 0xa83f, - 0xa840, - 0xa842, - 0xa843, - 0xa844, - 0xa845, - 0xa846, - 0xa847, - 0xa848, - 0xa849, - 0xa84a, - 0xa84b, - 0xa84c, - 0xa84d, - 0xa84e, - 0xa84f, - 0xa850, - 0xa851, - 0xa852, - 0xa853, - 0xa854, - 0xa855, - 0xa856, - 0xa857, - 0xa858, - 0xa859, - 0xa85a, - 0xa85b, - 0xa85c, - 0xa85d, - 0xa85e, - 0xa85f, - 0xa860, - 0xa861, - 0xa862, - 0xa863, - 0xa864, - 0xa865, - 0xa867, - 0xa870, - 0xa871, - 0xa872, - 0xa873, - 0xa874, - 0xa875, - 0xa876, - 0xa877, - 0xa878, - 0xa879, - 0xa87a, - 0xa87b, - 0xa87c, - 0xa87d, - 0xa87e, - 0xa87f, - 0xa880, - 0xa881, - 0xa882, - 0xa883, - 0xa884, - 0xa885, - 0xa886, - 0xa887, - 0xa888, - 0xa889, - 0xa88a, - 0xa88b, - 0xa88c, - 0xa88d, - 0xa88e, - 0xa88f, - 0xa890, - 0xa891, - 0xa892, - 0xa893, - 0xa894, - 0xa895, - 0xa896, - 0xa898, - 0xa980, - 0xa982, - 0xa983, - 0xa984, - 0xa985, - 0xa986, - 0xa987, - 0xa988, - 0xa989, - 0xa98a, - 0xa98b, - 0xa98c, - 0xa98d, - 0xa98e, - 0xa98f, - 0xa990, - 0xa991, - 0xa992, - 0xa993, - 0xa994, - 0xa995, - 0xa996, - 0xa997, - 0xa998, - 0xa999, - 0xa99a, - 0xa99b, - 0xa99c, - 0xa99d, - 0xa99e, - 0xa99f, - 0xa9a0, - 0xa9a1, - 0xa9a2, - 0xa9a3, - 0xa9a4, - 0xa9a5, - 0xa9a6, - 0xa9a7, - 0xa9a9, - 0xa9aa, - 0xa9ae, - 0xa9bf, - 0xa9c6, - 0xa9c7, - 0xa9c8, - 0xa9c9, - 0xa9ca, - 0xa9cb, - 0xa9d4, - 0xa9d5, - 0xa9d6, - 0xa9d7, - 0xa9d8, - 0xa9d9, - 0xa9da, - 0xa9db, - 0xa9dc, - 0xa9dd, - 0xa9de, - 0xa9e0, - 0xa9e1, - 0xa9e4, - 0xa9e5, - 0xab00, - 0xab03, - 0xab04, - 0xab05, - 0xab0a, - 0xab0b, - 0xab0c, - 0xab0d, - 0xab0e, - 0xab0f, - 0xab10, - 0xab11, - 0xab12, - 0xab13, - 0xab14, - 0xab15, - 0xab16, - 0xab17, - 0xab18, - 0xab19, - 0xab21, - 0xb2c0, - 0xb2c2, - 0xb2c3, - 0xb2ca, - 0xb2cb, - 0xb2cc, - 0xb2d2, - 0xb300, - 0xb301, - 0xb304, - 0xb305, - 0xb306, - 0xb307, -}; -template<> constexpr inline uint16_t RP_BLIT_REGS[] = { - 0xc02, - 0xc06, - 0xc10, - 0xc11, - 0xc12, - 0xc13, - 0xc14, - 0xc15, - 0xc16, - 0xc17, - 0xc18, - 0xc19, - 0xc1a, - 0xc1b, - 0xc1c, - 0xc1d, - 0xc1e, - 0xc1f, - 0xc20, - 0xc21, - 0xc22, - 0xc23, - 0xc24, - 0xc25, - 0xc26, - 0xc27, - 0xc28, - 0xc29, - 0xc2a, - 0xc2b, - 0xc2c, - 0xc2d, - 0xc2e, - 0xc2f, - 0xc38, - 0xc39, - 0xc3a, - 0xc3b, - 0xc3c, - 0xc3d, - 0xc3e, - 0xc3f, - 0xc40, - 0xc41, - 0xc42, - 0xc43, - 0xc44, - 0xc45, - 0xc46, - 0xc47, - 0xc48, - 0xc49, - 0xc4a, - 0xc4b, - 0xc4c, - 0xc4d, - 0xc4e, - 0xc4f, - 0xc50, - 0xc51, - 0xc52, - 0xc53, - 0xc54, - 0xc55, - 0xc56, - 0xc57, - 0xc58, - 0xc59, - 0xc5a, - 0xc5b, - 0xc5c, - 0xc5d, - 0xc5e, - 0xc5f, - 0xc60, - 0xc61, - 0xc62, - 0xc63, - 0xc64, - 0xc65, - 0xc66, - 0xc67, - 0xc68, - 0xc69, - 0xc6a, - 0xc6b, - 0xc6c, - 0xc6d, - 0xc6e, - 0xc6f, - 0xc70, - 0xc71, - 0xc72, - 0xc73, - 0xc74, - 0xc75, - 0xc76, - 0xc77, - 0xc78, - 0xc79, - 0xc7a, - 0xc7b, - 0xc7c, - 0xc7d, - 0xc7e, - 0xc7f, - 0xc80, - 0xc81, - 0xc82, - 0xc83, - 0xc84, - 0xc85, - 0xc86, - 0xc87, - 0xc88, - 0xc89, - 0xc8a, - 0xc8b, - 0xc8c, - 0xc8d, - 0xc8e, - 0xc8f, - 0xc90, - 0xc91, - 0xc92, - 0xc93, - 0xc94, - 0xc95, - 0xc96, - 0xc97, - 0x8000, - 0x8001, - 0x8002, - 0x8003, - 0x8004, - 0x8005, - 0x8006, - 0x8010, - 0x8011, - 0x8012, - 0x8013, - 0x8014, - 0x8015, - 0x8016, - 0x8017, - 0x8018, - 0x8019, - 0x801a, - 0x801b, - 0x801c, - 0x801d, - 0x801e, - 0x801f, - 0x8020, - 0x8021, - 0x8022, - 0x8023, - 0x8024, - 0x8025, - 0x8026, - 0x8027, - 0x8028, - 0x8029, - 0x802a, - 0x802b, - 0x802c, - 0x802d, - 0x802e, - 0x802f, - 0x8030, - 0x8031, - 0x8032, - 0x8033, - 0x8034, - 0x8035, - 0x8036, - 0x8037, - 0x8038, - 0x8039, - 0x803a, - 0x803b, - 0x803c, - 0x803d, - 0x803e, - 0x803f, - 0x8040, - 0x8041, - 0x8042, - 0x8043, - 0x8044, - 0x8045, - 0x8046, - 0x8047, - 0x8048, - 0x8049, - 0x804a, - 0x804b, - 0x804c, - 0x804d, - 0x804e, - 0x804f, - 0x8050, - 0x8051, - 0x8052, - 0x8053, - 0x8054, - 0x8055, - 0x8056, - 0x8057, - 0x8058, - 0x8059, - 0x805a, - 0x805b, - 0x805c, - 0x805d, - 0x805e, - 0x805f, - 0x8060, - 0x8061, - 0x8062, - 0x8063, - 0x8064, - 0x8065, - 0x8066, - 0x8067, - 0x8068, - 0x8069, - 0x806a, - 0x806b, - 0x806c, - 0x806d, - 0x806e, - 0x806f, - 0x8070, - 0x8071, - 0x8072, - 0x8073, - 0x8074, - 0x8075, - 0x8076, - 0x8077, - 0x8078, - 0x8079, - 0x807a, - 0x807b, - 0x807c, - 0x807d, - 0x807e, - 0x807f, - 0x8080, - 0x8081, - 0x8082, - 0x8083, - 0x8084, - 0x8085, - 0x8086, - 0x8087, - 0x8088, - 0x8089, - 0x808a, - 0x808b, - 0x808c, - 0x808d, - 0x808e, - 0x808f, - 0x8090, - 0x8091, - 0x8092, - 0x8094, - 0x8095, - 0x8096, - 0x8097, - 0x8098, - 0x809b, - 0x809c, - 0x809d, - 0x80a0, - 0x80a1, - 0x80a2, - 0x80a3, - 0x80a4, - 0x80a5, - 0x80a6, - 0x80b0, - 0x80b1, - 0x80b2, - 0x80b3, - 0x80b4, - 0x80b5, - 0x80b6, - 0x80b7, - 0x80b8, - 0x80b9, - 0x80ba, - 0x80bb, - 0x80bc, - 0x80bd, - 0x80be, - 0x80bf, - 0x80c0, - 0x80c1, - 0x80c2, - 0x80c3, - 0x80c4, - 0x80c5, - 0x80c6, - 0x80c7, - 0x80c8, - 0x80c9, - 0x80ca, - 0x80cb, - 0x80cc, - 0x80cd, - 0x80ce, - 0x80cf, - 0x80d0, - 0x80d1, - 0x80d2, - 0x80d3, - 0x80d4, - 0x80d5, - 0x80d6, - 0x80d7, - 0x80d8, - 0x80d9, - 0x80da, - 0x80db, - 0x80dc, - 0x80dd, - 0x80de, - 0x80df, - 0x80e0, - 0x80e1, - 0x80e2, - 0x80e3, - 0x80e4, - 0x80e5, - 0x80e6, - 0x80e7, - 0x80e8, - 0x80e9, - 0x80ea, - 0x80eb, - 0x80ec, - 0x80ed, - 0x80ee, - 0x80ef, - 0x80f0, - 0x80f1, - 0x8100, - 0x8101, - 0x8102, - 0x8103, - 0x8104, - 0x8105, - 0x8106, - 0x8107, - 0x8109, - 0x8114, - 0x8115, - 0x8400, - 0x8401, - 0x8402, - 0x8403, - 0x8404, - 0x8405, - 0x8406, - 0x840a, - 0x840b, - 0x8800, - 0x8801, - 0x8802, - 0x8803, - 0x8804, - 0x8805, - 0x8806, - 0x8809, - 0x880a, - 0x880b, - 0x880c, - 0x880d, - 0x880f, - 0x8810, - 0x8820, - 0x8821, - 0x8822, - 0x8823, - 0x8824, - 0x8825, - 0x8826, - 0x8827, - 0x8828, - 0x8829, - 0x882a, - 0x882b, - 0x882c, - 0x882d, - 0x882e, - 0x882f, - 0x8830, - 0x8831, - 0x8832, - 0x8833, - 0x8834, - 0x8835, - 0x8836, - 0x8837, - 0x8838, - 0x8839, - 0x883a, - 0x883b, - 0x883c, - 0x883d, - 0x883e, - 0x883f, - 0x8840, - 0x8841, - 0x8842, - 0x8843, - 0x8844, - 0x8845, - 0x8846, - 0x8847, - 0x8848, - 0x8849, - 0x884a, - 0x884b, - 0x884c, - 0x884d, - 0x884e, - 0x884f, - 0x8850, - 0x8851, - 0x8852, - 0x8853, - 0x8854, - 0x8855, - 0x8856, - 0x8857, - 0x8858, - 0x8859, - 0x885a, - 0x885b, - 0x885c, - 0x885d, - 0x885e, - 0x885f, - 0x8860, - 0x8861, - 0x8862, - 0x8863, - 0x8865, - 0x8870, - 0x8871, - 0x8872, - 0x8873, - 0x8874, - 0x8875, - 0x8876, - 0x8877, - 0x8878, - 0x8879, - 0x8880, - 0x8881, - 0x8882, - 0x8883, - 0x8884, - 0x8885, - 0x8886, - 0x8887, - 0x8888, - 0x8889, - 0x8890, - 0x8898, - 0x88c0, - 0x88c1, - 0x88d0, - 0x88d1, - 0x88d2, - 0x88d3, - 0x88d4, - 0x88d5, - 0x88d6, - 0x88d7, - 0x88d8, - 0x88d9, - 0x88da, - 0x88db, - 0x88dc, - 0x88dd, - 0x88de, - 0x88df, - 0x88e0, - 0x88e1, - 0x88e2, - 0x88e3, - 0x8900, - 0x8901, - 0x8902, - 0x8903, - 0x8904, - 0x8905, - 0x8906, - 0x8907, - 0x8908, - 0x8909, - 0x890a, - 0x890b, - 0x890c, - 0x890d, - 0x890e, - 0x890f, - 0x8910, - 0x8911, - 0x8912, - 0x8913, - 0x8914, - 0x8915, - 0x8916, - 0x8917, - 0x8918, - 0x8919, - 0x891a, - 0x8a00, - 0x8a10, - 0x8a20, - 0x8a30, - 0x8c00, - 0x8c01, - 0x8c17, - 0x8c18, - 0x8c19, - 0x8c1a, - 0x8c1b, - 0x8c1c, - 0x8c1d, - 0x8c1e, - 0x8c1f, - 0x8c20, - 0x8c21, - 0x8c22, - 0x8c23, - 0x8c24, - 0x8c25, - 0x8c2c, - 0x8c2d, - 0x8c2e, - 0x8c2f, - 0x9100, - 0x9101, - 0x9102, - 0x9103, - 0x9104, - 0x9105, - 0x9106, - 0x9107, - 0x9108, - 0x9200, - 0x9201, - 0x9202, - 0x9203, - 0x9204, - 0x9205, - 0x9206, - 0x9207, - 0x9208, - 0x9209, - 0x920a, - 0x920b, - 0x920c, - 0x920d, - 0x920e, - 0x920f, - 0x9212, - 0x9213, - 0x9214, - 0x9215, - 0x9216, - 0x9217, - 0x9301, - 0x9302, - 0x9303, - 0x9304, - 0x9305, - 0x9306, - 0x9311, - 0x9312, - 0x9313, - 0x9314, - 0x9315, - 0x9316, - 0x9800, - 0x9801, - 0x9802, - 0x9803, - 0x9804, - 0x9805, - 0x9806, - 0x9808, - 0x9980, - 0x9981, - 0x9b00, - 0x9b01, - 0x9b02, - 0x9b03, - 0x9b04, - 0x9b05, - 0x9b06, - 0x9b07, - 0x9b08, - 0xa000, - 0xa001, - 0xa002, - 0xa003, - 0xa004, - 0xa005, - 0xa006, - 0xa008, - 0xa00e, - 0xa00f, - 0xa010, - 0xa011, - 0xa012, - 0xa013, - 0xa014, - 0xa015, - 0xa016, - 0xa017, - 0xa018, - 0xa019, - 0xa01a, - 0xa01b, - 0xa01c, - 0xa01d, - 0xa01e, - 0xa01f, - 0xa020, - 0xa021, - 0xa022, - 0xa023, - 0xa024, - 0xa025, - 0xa026, - 0xa027, - 0xa028, - 0xa029, - 0xa02a, - 0xa02b, - 0xa02c, - 0xa02d, - 0xa02e, - 0xa02f, - 0xa030, - 0xa031, - 0xa032, - 0xa033, - 0xa034, - 0xa035, - 0xa036, - 0xa037, - 0xa038, - 0xa039, - 0xa03a, - 0xa03b, - 0xa03c, - 0xa03d, - 0xa03e, - 0xa03f, - 0xa040, - 0xa041, - 0xa042, - 0xa043, - 0xa044, - 0xa045, - 0xa046, - 0xa047, - 0xa048, - 0xa049, - 0xa04a, - 0xa04b, - 0xa04c, - 0xa04d, - 0xa04e, - 0xa04f, - 0xa050, - 0xa051, - 0xa052, - 0xa053, - 0xa054, - 0xa055, - 0xa056, - 0xa057, - 0xa058, - 0xa059, - 0xa05a, - 0xa05b, - 0xa05c, - 0xa05d, - 0xa05e, - 0xa05f, - 0xa060, - 0xa061, - 0xa062, - 0xa063, - 0xa064, - 0xa065, - 0xa066, - 0xa067, - 0xa068, - 0xa069, - 0xa06a, - 0xa06b, - 0xa06c, - 0xa06d, - 0xa06e, - 0xa06f, - 0xa070, - 0xa071, - 0xa072, - 0xa073, - 0xa074, - 0xa075, - 0xa076, - 0xa077, - 0xa078, - 0xa079, - 0xa07a, - 0xa07b, - 0xa07c, - 0xa07d, - 0xa07e, - 0xa07f, - 0xa080, - 0xa081, - 0xa082, - 0xa083, - 0xa084, - 0xa085, - 0xa086, - 0xa087, - 0xa088, - 0xa089, - 0xa08a, - 0xa08b, - 0xa08c, - 0xa08d, - 0xa08e, - 0xa08f, - 0xa090, - 0xa091, - 0xa092, - 0xa093, - 0xa094, - 0xa095, - 0xa096, - 0xa097, - 0xa098, - 0xa099, - 0xa09a, - 0xa09b, - 0xa09c, - 0xa09d, - 0xa09e, - 0xa09f, - 0xa0a0, - 0xa0a1, - 0xa0a2, - 0xa0a3, - 0xa0a4, - 0xa0a5, - 0xa0a6, - 0xa0a7, - 0xa0a8, - 0xa0a9, - 0xa0aa, - 0xa0ab, - 0xa0ac, - 0xa0ad, - 0xa0ae, - 0xa0af, - 0xa0b0, - 0xa0b1, - 0xa0b2, - 0xa0b3, - 0xa0b4, - 0xa0b5, - 0xa0b6, - 0xa0b7, - 0xa0b8, - 0xa0b9, - 0xa0ba, - 0xa0bb, - 0xa0bc, - 0xa0bd, - 0xa0be, - 0xa0bf, - 0xa0c0, - 0xa0c1, - 0xa0c2, - 0xa0c3, - 0xa0c4, - 0xa0c5, - 0xa0c6, - 0xa0c7, - 0xa0c8, - 0xa0c9, - 0xa0ca, - 0xa0cb, - 0xa0cc, - 0xa0cd, - 0xa0ce, - 0xa0cf, - 0xa0d0, - 0xa0d1, - 0xa0d2, - 0xa0d3, - 0xa0d4, - 0xa0d5, - 0xa0d6, - 0xa0d7, - 0xa0d8, - 0xa0d9, - 0xa0da, - 0xa0db, - 0xa0dc, - 0xa0dd, - 0xa0de, - 0xa0df, - 0xa0e0, - 0xa0e1, - 0xa0e2, - 0xa0e3, - 0xa0e4, - 0xa0e5, - 0xa0e6, - 0xa0e7, - 0xa0e8, - 0xa0e9, - 0xa0ea, - 0xa0eb, - 0xa0ec, - 0xa0ed, - 0xa0ee, - 0xa0ef, - 0xa0f8, - 0xa800, - 0xa802, - 0xa803, - 0xa804, - 0xa805, - 0xa806, - 0xa807, - 0xa808, - 0xa809, - 0xa80a, - 0xa80b, - 0xa80c, - 0xa80d, - 0xa80e, - 0xa80f, - 0xa810, - 0xa811, - 0xa812, - 0xa813, - 0xa814, - 0xa815, - 0xa816, - 0xa817, - 0xa818, - 0xa819, - 0xa81a, - 0xa81b, - 0xa81c, - 0xa81d, - 0xa81e, - 0xa81f, - 0xa820, - 0xa821, - 0xa822, - 0xa823, - 0xa824, - 0xa825, - 0xa830, - 0xa831, - 0xa832, - 0xa833, - 0xa834, - 0xa835, - 0xa836, - 0xa837, - 0xa838, - 0xa839, - 0xa83a, - 0xa83b, - 0xa83c, - 0xa83d, - 0xa840, - 0xa842, - 0xa843, - 0xa844, - 0xa845, - 0xa846, - 0xa847, - 0xa848, - 0xa849, - 0xa84a, - 0xa84b, - 0xa84c, - 0xa84d, - 0xa84e, - 0xa84f, - 0xa850, - 0xa851, - 0xa852, - 0xa853, - 0xa854, - 0xa855, - 0xa856, - 0xa857, - 0xa858, - 0xa859, - 0xa85a, - 0xa85b, - 0xa85c, - 0xa85d, - 0xa85e, - 0xa85f, - 0xa860, - 0xa861, - 0xa862, - 0xa863, - 0xa864, - 0xa865, - 0xa870, - 0xa871, - 0xa872, - 0xa873, - 0xa874, - 0xa875, - 0xa876, - 0xa877, - 0xa878, - 0xa879, - 0xa87a, - 0xa87b, - 0xa87c, - 0xa87d, - 0xa87e, - 0xa87f, - 0xa880, - 0xa881, - 0xa882, - 0xa883, - 0xa884, - 0xa885, - 0xa886, - 0xa887, - 0xa888, - 0xa889, - 0xa88a, - 0xa88b, - 0xa88c, - 0xa88d, - 0xa88e, - 0xa88f, - 0xa890, - 0xa891, - 0xa892, - 0xa893, - 0xa894, - 0xa895, - 0xa896, - 0xa980, - 0xa982, - 0xa983, - 0xa984, - 0xa985, - 0xa986, - 0xa987, - 0xa988, - 0xa989, - 0xa98a, - 0xa98b, - 0xa98c, - 0xa98d, - 0xa98e, - 0xa98f, - 0xa990, - 0xa991, - 0xa992, - 0xa993, - 0xa994, - 0xa995, - 0xa996, - 0xa997, - 0xa998, - 0xa999, - 0xa99a, - 0xa99b, - 0xa99c, - 0xa99d, - 0xa99e, - 0xa99f, - 0xa9a0, - 0xa9a1, - 0xa9a2, - 0xa9a3, - 0xa9a4, - 0xa9a5, - 0xa9a6, - 0xa9a7, - 0xa9a9, - 0xa9e0, - 0xa9e1, - 0xa9e4, - 0xa9e5, - 0xab00, - 0xab04, - 0xab05, - 0xab10, - 0xab11, - 0xab12, - 0xab13, - 0xab14, - 0xab15, - 0xab16, - 0xab17, - 0xab18, - 0xab19, - 0xacc0, - 0xb300, - 0xb301, - 0xb304, - 0xb305, - 0xb306, - 0xb307, - 0xb4c0, - 0xb4c1, - 0xb4c2, - 0xb4c3, - 0xb4c4, - 0xb4ca, - 0xb4cb, - 0xb4cc, - 0xb4d1, - 0xb800, - 0xb801, - 0xb802, - 0xb803, - 0xb980, - 0xb982, - 0xb983, - 0xb984, - 0xb985, - 0xb986, - 0xb990, - 0xb991, - 0xb992, - 0xb993, - 0xb994, - 0xb995, - 0xb996, - 0xb997, - 0xb998, - 0xb999, - 0xb99a, - 0xb99b, - 0xb9c0, - 0xb9c1, - 0xb9c2, - 0xb9c3, - 0xb9c4, - 0xb9c5, - 0xb9c6, - 0xb9c7, - 0xb9c8, - 0xb9c9, - 0xbb10, -}; -#endif - -#endif /* A6XX_XML */ diff --git a/tinygrad/extra/qcom_gpu_driver/adreno_pm4.xml b/tinygrad/extra/qcom_gpu_driver/adreno_pm4.xml deleted file mode 100644 index 1b687eed..00000000 --- a/tinygrad/extra/qcom_gpu_driver/adreno_pm4.xml +++ /dev/null @@ -1,2265 +0,0 @@ - - - - - - - - - - - Flushes dirty data from UCHE, and also writes a GPU timestamp to - the address if one is provided. - - - - - - - - - - - - - - - - - - - If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed - sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main - memory, skipping UCHE. - - - - - - Writes the GPU timestamp to the address that follows, once RB - access and flushes are complete. - - - - - - - - - - - - - - - - - - - - - Invalidates depth attachment data from the CCU. We assume this - happens in the last stage. - - - - - Invalidates color attachment data from the CCU. We assume this - happens in the last stage. - - - - - Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, - along with its registers, would be better named RESOLVE). - - - - - Flushes depth attachment data from the CCU. We assume this - happens in the last stage. - - - - - Flushes color attachment data from the CCU. We assume this - happens in the last stage. - - - - - 2D blit to resolve GMEM to system memory (skipping CCU) at the - end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for - more general blitting. - - - - - Clears based on GRAS_LRZ_CNTL configuration, could clear - fast-clear buffer or LRZ direction. - LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which - could be expressed by enum: - CUR_DIR_DISABLED = 0x0 - CUR_DIR_GE = 0x1 - CUR_DIR_LE = 0x2 - CUR_DIR_UNSET = 0x3 - Clear of direction means setting the direction to CUR_DIR_UNSET. - - - - - - - - - - - - - - - Invalidates UCHE. - - - - - - - - Doesn't seem to do anything - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - initialize CP's micro-engine - - skip N 32-bit words to get to the next packet - - - indirect buffer dispatch. prefetch parser uses this packet - type to determine whether to pre-fetch the IB - - - - - - Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to - another buffer at the same level. Must be at the end of IB, and - doesn't work with draw state IB's. - - - indirect buffer dispatch. same as IB, but init is pipelined - - - Waits for the IDLE state of the engine before further drawing. - This is pipelined, so the CP may continue. - - - wait until a register or memory location is a specific value - - wait until a register location is equal to a specific value - - wait until a register location is >= a specific value - - wait until a read completes - - wait until all base/size writes from an IB_PFD packet have completed - - - register read/modify/write - - Set binning configuration registers - - - reads register in chip and writes to memory - - write N 32-bit words to memory - - write CP_PROG_COUNTER value to memory - - conditional execution of a sequence of packets - - conditional write to memory or register - - - generate an event that creates a write to memory when completed - - - generate a VS|PS_done event - - generate a cache flush done event - - generate a z_pass done event - - - not sure the real name, but this seems to be what is used for - opencl, instead of CP_DRAW_INDX.. - - - initiate fetch of index buffer and draw - - draw using supplied indices in packet - - initiate fetch of index buffer and binIDs and draw - - initiate fetch of bin IDs and draw using supplied indices - - begin/end initiator for viz query extent processing - - fetch state sub-blocks and initiate shader code DMAs - - load constant into chip and to memory - - load sequencer instruction memory (pointer-based) - - load sequencer instruction memory (code embedded in packet) - - load constants from a location in memory - - selective invalidation of state pointers - - dynamically changes shader instruction memory partition - - sets the 64-bit BIN_MASK register in the PFP - - sets the 64-bit BIN_SELECT register in the PFP - - updates the current context, if needed - - generate interrupt from the command stream - - copy sequencer instruction memory to system memory - - - - - - - - sets draw initiator flags register in PFP, gets bitwise-ORed into - every draw initiator - - - sets the register protection mode - - - - - - load high level sequencer command - - - Conditionally load a IB based on a flag, prefetch enabled - - Conditionally load a IB based on a flag, prefetch disabled - - Load a buffer with pre-fetch enabled - - Set bin (?) - - - test 2 memory locations to dword values specified - - - Write register, ignoring context state for context sensitive registers - - - Record the real-time when this packet is processed by PFP - - - - - - PFP waits until the FIFO between the PFP and the ME is empty - - - - - Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple - groups of registers. Looks like it can be used to create state - objects in GPU memory, and on state change only emit pointer - (via CP_SET_DRAW_STATE), which should be nice for reducing CPU - overhead: - - (A4x) save PM4 stream pointers to execute upon a visible draw - - - - - - - - - - Enable or disable predication globally. Also resets the - predicate to "passing" and the local bit to enabled when - enabling global predication. - - - - - Enable or disable predication locally. Unlike globally enabling - predication, this packet doesn't touch any other state. - Predication only happens when enabled globally and locally and a - predicate has been set. This should be used for internal draws - which aren't supposed to use the predication state: - - CP_DRAW_PRED_ENABLE_LOCAL(0) - ... do draw... - CP_DRAW_PRED_ENABLE_LOCAL(1) - - - - - Latch a draw predicate into the internal register. - - - - - for A4xx - Write to register with address that does not fit into type-0 pkt - - - - copy from ME scratch RAM to a register - - - Copy from REG to ME scratch RAM - - - Wait for memory writes to complete - - - Conditional execution based on register comparison - - - Memory to REG copy - - - - - - - for a5xx - - - - - - Tells CP the current mode of GPU operation - - Instruct CP to set a few internal CP registers - - - - - - - Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and - nothing is left in the visibility stream, then - CP_INDIRECT_BUFFER will be skipped, and draws will early return - from their IB. - - - - - - - - - - - - - - - - - - - - General purpose 2D blit engine for image transfers and mipmap - generation. Reads through UCHE, writes through the CCU cache in - the PS stage. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords, - and forcibly switch to the indicated context. - - - - - - - - - - These first appear in a650_sqe.bin. They can in theory be used - to loop any sequence of IB1 commands, but in practice they are - used to loop over bins. There is a fixed-size per-iteration - prefix, used to set per-bin state, and then the following IB1 - commands are executed until CP_END_BIN which are always the same - for each iteration and usually contain a list of - CP_INDIRECT_BUFFER calls to IB2 commands which setup state and - execute restore/draw/save commands. This replaces the previous - technique of just repeating the CP_INDIRECT_BUFFER calls and - "unrolling" the loop. - - - - - Make next dword 1 to disable preemption, 0 to re-enable it. - - - - - - - - - Can clear BV/BR counters, or wait until one catches up to another - - Clears, adds to local, or adds to global timestamp - - - - - Write to a scratch memory that is read by CP_REG_TEST with - SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. - However it uses the same memory space. - - - - - Executes an array of fixed-size command buffers where each - buffer is assumed to have one draw call, skipping buffers with - non-visible draw calls. - - - - Reset various on-chip state used for synchronization - - - - - - Load state, a3xx (and later?) - - - - - - - - - - - - - - - - - inline with the CP_LOAD_STATE packet - - - - - in buffer pointed to by EXT_SRC_ADDR - - - - - - - - - - - - - - - - - - Load state, a4xx+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Load state, a6xx+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - SS6_UBO used by the a6xx vulkan blob with tesselation constants - in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) - to load constants from a UBO loaded with DST_OFF = 14 and offset 0, - EXT_SRC_ADDR = 0xe0000 - (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will - be updated for each draw to {draw_id, first_vertex, first_instance, 0} - value of 0 disables it - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Read a 64-bit value at the given address and - test if it equals/doesn't equal 0. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - value at offset 0 always seems to be 0x00000000.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Like CP_SET_BIN_DATA5, but set the pointers as offsets from the - pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful - for Vulkan where these values aren't known when the command - stream is recorded. - - - - - - - - - - - - - - - - - - - - - - - - Modifies DST_REG using two sources that can either be registers - or immediates. If SRC1_ADD is set, then do the following: - - $dst = (($dst & $src0) rot $rotate) + $src1 - - Otherwise: - - $dst = (($dst & $src0) rot $rotate) | $src1 - - Here "rot" means rotate left. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Like CP_REG_TO_MEM, but the memory address to write to can be - offsetted using either one or two registers or scratch - registers. - - - - - - - - - - - - - - - - - - - - - - - - Like CP_REG_TO_MEM, but the memory address to write to can be - offsetted using a DWORD in memory. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Wait until a memory value is greater than or equal to the - reference, using signed comparison. - - - - - - - - - - - - - - - - - - - This uses the same internal comparison as CP_COND_WRITE, - but waits until the comparison is true instead. It busy-loops in - the CP for the given number of cycles before trying again. - - - - - - - - - - - - - - - - - - - - - - - - - - - Waits for REG0 to not be 0 or REG1 to not equal REF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tell CP the current operation mode, indicates save and restore procedure - - - - - - - - - - - - - - - - - - - - - - - - - - Set internal CP registers, used to indicate context save data addresses - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. - So: - - opcode: CP_REG_TEST (39) (2 dwords) - { REG = 0xc10 | BIT = 0 } - 0000: 70b90001 00000c10 - opcode: CP_COND_REG_EXEC (47) (3 dwords) - 0000: 70c70002 10000000 00000004 - opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) - - Will execute the CP_INDIRECT_BUFFER only if b0 in the register at - offset 0x0c10 is 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Executes the following DWORDs of commands if the dword at ADDR0 - is not equal to 0 and the dword at ADDR1 is less than REF - (signed comparison). - - - - - - - - - - - - - - - - - - - - - - - - Used by the userspace driver to set various IB's which are - executed during context save/restore for handling - state that isn't restored by the - context switch routine itself. - - - - Executed unconditionally when switching back to the context. - - - - Executed when switching back after switching - away during execution of - a CP_SET_MARKER packet with RM6_YIELD as the - payload *and* the normal save routine was - bypassed for a shorter one. I think this is - connected to the "skipsaverestore" bit set by - the kernel when preempting. - - - - - Executed when switching away from the context, - except for context switches initiated via - CP_YIELD. - - - - - This can only be set by the RB (i.e. the kernel) - and executes with protected mode off, but - is otherwise similar to SAVE_IB. - - Note, kgsl calls this CP_KMD_AMBLE_TYPE - - - - - - - - - - - - - - - - - - - Keep shadow copies of these registers and only set them - when drawing, avoiding redundant writes: - - VPC_CNTL_0 - - HLSQ_CONTROL_1_REG - - HLSQ_UNKNOWN_B980 - - - - Track RB_RENDER_CNTL, and insert a WFI in the following - situation: - - There is a write that disables binning - - There was a draw with binning left enabled, but in - BYPASS mode - Presumably this is a hang workaround? - - - - Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of - the data to write is 0. Used by the Vulkan blob with - PC_MULTIVIEW_CNTL, but this isn't predicated on particular - register(s) like the others. - - - - Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and - GRAS_LRZ_DEPTH_VIEW with previous values, and if one of - the following is true: - - GRAS_LRZ_CNTL::GREATER has changed - - GRAS_LRZ_CNTL::DIR has changed, the old value is not - CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED - - GRAS_LRZ_DEPTH_VIEW has changed - then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE - forced to 1. - Only exists in a650_sqe.fw. - - - - - - - - - - - - - Note that the SMMU's definition of TTBRn can take different forms - depending on the pgtable format. But a5xx+ only uses aarch64 - format. - - - - - - - - - - Unused, does not apply to aarch64 pgtable format - - - - - - - - - - - - - Size of prefix for each bin. For each bin index i, the - prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are - executed in an IB2 before the IB1 commands following - this packet. - - - - Number of dwords after this packet until CP_END_BIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Best guess is that it is a faster way to fetch all the VSC_STATE registers - and keep them in a local scratch memory instead of fetching every time - when skipping IBs. - - - - - - Scratch memory size is 48 dwords` - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tinygrad/extra/qcom_gpu_driver/gen.sh b/tinygrad/extra/qcom_gpu_driver/gen.sh deleted file mode 100755 index ad5d8b2f..00000000 --- a/tinygrad/extra/qcom_gpu_driver/gen.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/usr/bin/sh -clang2py msm_kgsl.h -o msm_kgsl.py \ No newline at end of file diff --git a/tinygrad/extra/qcom_gpu_driver/msm_kgsl.h b/tinygrad/extra/qcom_gpu_driver/msm_kgsl.h deleted file mode 100644 index cae035d3..00000000 --- a/tinygrad/extra/qcom_gpu_driver/msm_kgsl.h +++ /dev/null @@ -1,1451 +0,0 @@ -#ifndef _UAPI_MSM_KGSL_H -#define _UAPI_MSM_KGSL_H - -#include -#include -#define size_t unsigned long -#define uint64_t unsigned long - -/* - * The KGSL version has proven not to be very useful in userspace if features - * are cherry picked into other trees out of order so it is frozen as of 3.14. - * It is left here for backwards compatabilty and as a reminder that - * software releases are never linear. Also, I like pie. - */ - -#define KGSL_VERSION_MAJOR 3 -#define KGSL_VERSION_MINOR 14 - -/* - * We have traditionally mixed context and issueibcmds / command batch flags - * together into a big flag stew. This worked fine until we started adding a - * lot more command batch flags and we started running out of bits. Turns out - * we have a bit of room in the context type / priority mask that we could use - * for command batches, but that means we need to split out the flags into two - * coherent sets. - * - * If any future definitions are for both context and cmdbatch add both defines - * and link the cmdbatch to the context define as we do below. Otherwise feel - * free to add exclusive bits to either set. - */ - -/* --- context flags --- */ -#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 -#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 -#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 -#define KGSL_CONTEXT_PREAMBLE 0x00000010 -#define KGSL_CONTEXT_TRASH_STATE 0x00000020 -#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 -#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_END_OF_FRAME 0x00000100 -#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 -/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */ -#define KGSL_CONTEXT_SYNC 0x00000400 -#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800 - -#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000 -#define KGSL_CONTEXT_PRIORITY_SHIFT 12 -#define KGSL_CONTEXT_PRIORITY_UNDEF 0 - -#define KGSL_CONTEXT_IFH_NOP 0x00010000 -#define KGSL_CONTEXT_SECURE 0x00020000 - -#define KGSL_CONTEXT_PREEMPT_STYLE_MASK 0x0E000000 -#define KGSL_CONTEXT_PREEMPT_STYLE_SHIFT 25 -#define KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT 0x0 -#define KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER 0x1 -#define KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN 0x2 - -#define KGSL_CONTEXT_TYPE_MASK 0x01F00000 -#define KGSL_CONTEXT_TYPE_SHIFT 20 -#define KGSL_CONTEXT_TYPE_ANY 0 -#define KGSL_CONTEXT_TYPE_GL 1 -#define KGSL_CONTEXT_TYPE_CL 2 -#define KGSL_CONTEXT_TYPE_C2D 3 -#define KGSL_CONTEXT_TYPE_RS 4 -#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E - -#define KGSL_CONTEXT_INVALID 0xffffffff - -/* - * --- command batch flags --- - * The bits that are linked to a KGSL_CONTEXT equivalent are either legacy - * definitions or bits that are valid for both contexts and cmdbatches. To be - * safe the other 8 bits that are still available in the context field should be - * omitted here in case we need to share - the other bits are available for - * cmdbatch only flags as needed - */ -#define KGSL_CMDBATCH_MEMLIST 0x00000001 -#define KGSL_CMDBATCH_MARKER 0x00000002 -#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST /* 0x004 */ -#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH /* 0x008 */ -#define KGSL_CMDBATCH_PROFILING 0x00000010 -#define KGSL_CMDBATCH_PROFILING_KTIME 0x00000020 -#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME /* 0x100 */ -#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC /* 0x400 */ -#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT /* 0x800 */ - -/* - * Reserve bits [16:19] and bits [28:31] for possible bits shared between - * contexts and command batches. Update this comment as new flags are added. - */ - -/* - * gpu_command_object flags - these flags communicate the type of command or - * memory object being submitted for a GPU command - */ - -/* Flags for GPU command objects */ -#define KGSL_CMDLIST_IB 0x00000001U -#define KGSL_CMDLIST_CTXTSWITCH_PREAMBLE 0x00000002U -#define KGSL_CMDLIST_IB_PREAMBLE 0x00000004U - -/* Flags for GPU command memory objects */ -#define KGSL_OBJLIST_MEMOBJ 0x00000008U -#define KGSL_OBJLIST_PROFILE 0x00000010U - -/* Flags for GPU command sync points */ -#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0 -#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1 - -/* --- Memory allocation flags --- */ - -/* General allocation hints */ -#define KGSL_MEMFLAGS_SECURE 0x00000008ULL -#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000U -#define KGSL_MEMFLAGS_GPUWRITEONLY 0x02000000U -#define KGSL_MEMFLAGS_FORCE_32BIT 0x100000000ULL - -/* Memory caching hints */ -#define KGSL_CACHEMODE_MASK 0x0C000000U -#define KGSL_CACHEMODE_SHIFT 26 - -#define KGSL_CACHEMODE_WRITECOMBINE 0 -#define KGSL_CACHEMODE_UNCACHED 1 -#define KGSL_CACHEMODE_WRITETHROUGH 2 -#define KGSL_CACHEMODE_WRITEBACK 3 - -#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000ULL - -/* Memory types for which allocations are made */ -#define KGSL_MEMTYPE_MASK 0x0000FF00 -#define KGSL_MEMTYPE_SHIFT 8 - -#define KGSL_MEMTYPE_OBJECTANY 0 -#define KGSL_MEMTYPE_FRAMEBUFFER 1 -#define KGSL_MEMTYPE_RENDERBUFFER 2 -#define KGSL_MEMTYPE_ARRAYBUFFER 3 -#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 -#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 -#define KGSL_MEMTYPE_TEXTURE 6 -#define KGSL_MEMTYPE_SURFACE 7 -#define KGSL_MEMTYPE_EGL_SURFACE 8 -#define KGSL_MEMTYPE_GL 9 -#define KGSL_MEMTYPE_CL 10 -#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 -#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 -#define KGSL_MEMTYPE_CL_IMAGE_MAP 13 -#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 -#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 -#define KGSL_MEMTYPE_COMMAND 16 -#define KGSL_MEMTYPE_2D 17 -#define KGSL_MEMTYPE_EGL_IMAGE 18 -#define KGSL_MEMTYPE_EGL_SHADOW 19 -#define KGSL_MEMTYPE_MULTISAMPLE 20 -#define KGSL_MEMTYPE_KERNEL 255 - -/* - * Alignment hint, passed as the power of 2 exponent. - * i.e 4k (2^12) would be 12, 64k (2^16)would be 16. - */ -#define KGSL_MEMALIGN_MASK 0x00FF0000 -#define KGSL_MEMALIGN_SHIFT 16 - -enum kgsl_user_mem_type { - KGSL_USER_MEM_TYPE_PMEM = 0x00000000, - KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, - KGSL_USER_MEM_TYPE_ADDR = 0x00000002, - KGSL_USER_MEM_TYPE_ION = 0x00000003, - /* - * ION type is retained for backwards compatibilty but Ion buffers are - * dma-bufs so try to use that naming if we can - */ - KGSL_USER_MEM_TYPE_DMABUF = 0x00000003, - KGSL_USER_MEM_TYPE_MAX = 0x00000007, -}; -#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0 -#define KGSL_MEMFLAGS_USERMEM_SHIFT 5 - -/* - * Unfortunately, enum kgsl_user_mem_type starts at 0 which does not - * leave a good value for allocated memory. In the flags we use - * 0 to indicate allocated memory and thus need to add 1 to the enum - * values. - */ -#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) - -#define KGSL_MEMFLAGS_NOT_USERMEM 0 -#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) -#define KGSL_MEMFLAGS_USERMEM_ASHMEM \ - KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) -#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) -#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) - -/* --- generic KGSL flag values --- */ - -#define KGSL_FLAGS_NORMALMODE 0x00000000 -#define KGSL_FLAGS_SAFEMODE 0x00000001 -#define KGSL_FLAGS_INITIALIZED0 0x00000002 -#define KGSL_FLAGS_INITIALIZED 0x00000004 -#define KGSL_FLAGS_STARTED 0x00000008 -#define KGSL_FLAGS_ACTIVE 0x00000010 -#define KGSL_FLAGS_RESERVED0 0x00000020 -#define KGSL_FLAGS_RESERVED1 0x00000040 -#define KGSL_FLAGS_RESERVED2 0x00000080 -#define KGSL_FLAGS_SOFT_RESET 0x00000100 -#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 - -/* Server Side Sync Timeout in milliseconds */ -#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 - -/* - * Reset status values for context - */ -enum kgsl_ctx_reset_stat { - KGSL_CTX_STAT_NO_ERROR = 0x00000000, - KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, - KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, - KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 -}; - -#define KGSL_CONVERT_TO_MBPS(val) \ - (val*1000*1000U) - -/* device id */ -enum kgsl_deviceid { - KGSL_DEVICE_3D0 = 0x00000000, - KGSL_DEVICE_MAX -}; - -struct kgsl_devinfo { - - unsigned int device_id; - /* chip revision id - * coreid:8 majorrev:8 minorrev:8 patch:8 - */ - unsigned int chip_id; - unsigned int mmu_enabled; - unsigned long gmem_gpubaseaddr; - /* - * This field contains the adreno revision - * number 200, 205, 220, etc... - */ - unsigned int gpu_id; - size_t gmem_sizebytes; -}; - -/* - * struct kgsl_devmemstore - this structure defines the region of memory - * that can be mmap()ed from this driver. The timestamp fields are volatile - * because they are written by the GPU - * @soptimestamp: Start of pipeline timestamp written by GPU before the - * commands in concern are processed - * @sbz: Unused, kept for 8 byte alignment - * @eoptimestamp: End of pipeline timestamp written by GPU after the - * commands in concern are processed - * @sbz2: Unused, kept for 8 byte alignment - * @preempted: Indicates if the context was preempted - * @sbz3: Unused, kept for 8 byte alignment - * @ref_wait_ts: Timestamp on which to generate interrupt, unused now. - * @sbz4: Unused, kept for 8 byte alignment - * @current_context: The current context the GPU is working on - * @sbz5: Unused, kept for 8 byte alignment - */ -struct kgsl_devmemstore { - volatile unsigned int soptimestamp; - unsigned int sbz; - volatile unsigned int eoptimestamp; - unsigned int sbz2; - volatile unsigned int preempted; - unsigned int sbz3; - volatile unsigned int ref_wait_ts; - unsigned int sbz4; - unsigned int current_context; - unsigned int sbz5; -}; - -#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \ - ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \ - offsetof(struct kgsl_devmemstore, field)) - -/* timestamp id*/ -enum kgsl_timestamp_type { - KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */ - KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/ - KGSL_TIMESTAMP_QUEUED = 0x00000003, -}; - -/* property types - used with kgsl_device_getproperty */ -#define KGSL_PROP_DEVICE_INFO 0x1 -#define KGSL_PROP_DEVICE_SHADOW 0x2 -#define KGSL_PROP_DEVICE_POWER 0x3 -#define KGSL_PROP_SHMEM 0x4 -#define KGSL_PROP_SHMEM_APERTURES 0x5 -#define KGSL_PROP_MMU_ENABLE 0x6 -#define KGSL_PROP_INTERRUPT_WAITS 0x7 -#define KGSL_PROP_VERSION 0x8 -#define KGSL_PROP_GPU_RESET_STAT 0x9 -#define KGSL_PROP_PWRCTRL 0xE -#define KGSL_PROP_PWR_CONSTRAINT 0x12 -#define KGSL_PROP_UCHE_GMEM_VADDR 0x13 -#define KGSL_PROP_SP_GENERIC_MEM 0x14 -#define KGSL_PROP_UCODE_VERSION 0x15 -#define KGSL_PROP_GPMU_VERSION 0x16 -#define KGSL_PROP_DEVICE_BITNESS 0x18 - -struct kgsl_shadowprop { - unsigned long gpuaddr; - size_t size; - unsigned int flags; /* contains KGSL_FLAGS_ values */ -}; - -struct kgsl_version { - unsigned int drv_major; - unsigned int drv_minor; - unsigned int dev_major; - unsigned int dev_minor; -}; - -struct kgsl_sp_generic_mem { - uint64_t local; - uint64_t pvt; -}; - -struct kgsl_ucode_version { - unsigned int pfp; - unsigned int pm4; -}; - -struct kgsl_gpmu_version { - unsigned int major; - unsigned int minor; - unsigned int features; -}; - -/* Performance counter groups */ - -#define KGSL_PERFCOUNTER_GROUP_CP 0x0 -#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1 -#define KGSL_PERFCOUNTER_GROUP_PC 0x2 -#define KGSL_PERFCOUNTER_GROUP_VFD 0x3 -#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4 -#define KGSL_PERFCOUNTER_GROUP_VPC 0x5 -#define KGSL_PERFCOUNTER_GROUP_TSE 0x6 -#define KGSL_PERFCOUNTER_GROUP_RAS 0x7 -#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8 -#define KGSL_PERFCOUNTER_GROUP_TP 0x9 -#define KGSL_PERFCOUNTER_GROUP_SP 0xA -#define KGSL_PERFCOUNTER_GROUP_RB 0xB -#define KGSL_PERFCOUNTER_GROUP_PWR 0xC -#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD -#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE -#define KGSL_PERFCOUNTER_GROUP_MH 0xF -#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10 -#define KGSL_PERFCOUNTER_GROUP_SQ 0x11 -#define KGSL_PERFCOUNTER_GROUP_SX 0x12 -#define KGSL_PERFCOUNTER_GROUP_TCF 0x13 -#define KGSL_PERFCOUNTER_GROUP_TCM 0x14 -#define KGSL_PERFCOUNTER_GROUP_TCR 0x15 -#define KGSL_PERFCOUNTER_GROUP_L2 0x16 -#define KGSL_PERFCOUNTER_GROUP_VSC 0x17 -#define KGSL_PERFCOUNTER_GROUP_CCU 0x18 -#define KGSL_PERFCOUNTER_GROUP_LRZ 0x19 -#define KGSL_PERFCOUNTER_GROUP_CMP 0x1A -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B -#define KGSL_PERFCOUNTER_GROUP_SP_PWR 0x1C -#define KGSL_PERFCOUNTER_GROUP_TP_PWR 0x1D -#define KGSL_PERFCOUNTER_GROUP_RB_PWR 0x1E -#define KGSL_PERFCOUNTER_GROUP_CCU_PWR 0x1F -#define KGSL_PERFCOUNTER_GROUP_UCHE_PWR 0x20 -#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21 -#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22 -#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23 -#define KGSL_PERFCOUNTER_GROUP_MAX 0x24 - -#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF -#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE - -/* structure holds list of ibs */ -struct kgsl_ibdesc { - unsigned long gpuaddr; - unsigned long __pad; - size_t sizedwords; - unsigned int ctrl; -}; - -/** - * struct kgsl_cmdbatch_profiling_buffer - * @wall_clock_s: Ringbuffer submission time (seconds). - * If KGSL_CMDBATCH_PROFILING_KTIME is set, time is provided - * in kernel clocks, otherwise wall clock time is used. - * @wall_clock_ns: Ringbuffer submission time (nanoseconds). - * If KGSL_CMDBATCH_PROFILING_KTIME is set time is provided - * in kernel clocks, otherwise wall clock time is used. - * @gpu_ticks_queued: GPU ticks at ringbuffer submission - * @gpu_ticks_submitted: GPU ticks when starting cmdbatch execution - * @gpu_ticks_retired: GPU ticks when finishing cmdbatch execution - * - * This structure defines the profiling buffer used to measure cmdbatch - * execution time - */ -struct kgsl_cmdbatch_profiling_buffer { - uint64_t wall_clock_s; - uint64_t wall_clock_ns; - uint64_t gpu_ticks_queued; - uint64_t gpu_ticks_submitted; - uint64_t gpu_ticks_retired; -}; - -/* ioctls */ -#define KGSL_IOC_TYPE 0x09 - -/* get misc info about the GPU - type should be a value from enum kgsl_property_type - value points to a structure that varies based on type - sizebytes is sizeof() that structure - for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo - this structure contaings hardware versioning info. - for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop - this is used to find mmap() offset and sizes for mapping - struct kgsl_memstore into userspace. -*/ -struct kgsl_device_getproperty { - unsigned int type; - void __user *value; - size_t sizebytes; -}; - -#define IOCTL_KGSL_DEVICE_GETPROPERTY \ - _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) - -/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012 - */ - -/* block until the GPU has executed past a given timestamp - * timeout is in milliseconds. - */ -struct kgsl_device_waittimestamp { - unsigned int timestamp; - unsigned int timeout; -}; - -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \ - _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) - -struct kgsl_device_waittimestamp_ctxtid { - unsigned int context_id; - unsigned int timestamp; - unsigned int timeout; -}; - -#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \ - _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) - -/* DEPRECATED: issue indirect commands to the GPU. - * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE - * ibaddr and sizedwords must specify a subset of a buffer created - * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM - * flags may be a mask of KGSL_CONTEXT_ values - * timestamp is a returned counter value which can be passed to - * other ioctls to determine when the commands have been executed by - * the GPU. - * - * This fucntion is deprecated - consider using IOCTL_KGSL_SUBMIT_COMMANDS - * instead - */ -struct kgsl_ringbuffer_issueibcmds { - unsigned int drawctxt_id; - unsigned long ibdesc_addr; - unsigned int numibs; - unsigned int timestamp; /*output param */ - unsigned int flags; -}; - -#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \ - _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) - -/* read the most recently executed timestamp value - * type should be a value from enum kgsl_timestamp_type - */ -struct kgsl_cmdstream_readtimestamp { - unsigned int type; - unsigned int timestamp; /*output param */ -}; - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \ - _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \ - _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) - -/* free memory when the GPU reaches a given timestamp. - * gpuaddr specify a memory region created by a - * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call - * type should be a value from enum kgsl_timestamp_type - */ -struct kgsl_cmdstream_freememontimestamp { - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \ - _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) - -/* Previous versions of this header had incorrectly defined - IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead - of a write only ioctl. To ensure binary compatability, the following - #define will be used to intercept the incorrect ioctl -*/ - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \ - _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) - -/* create a draw context, which is used to preserve GPU state. - * The flags field may contain a mask KGSL_CONTEXT_* values - */ -struct kgsl_drawctxt_create { - unsigned int flags; - unsigned int drawctxt_id; /*output param */ -}; - -#define IOCTL_KGSL_DRAWCTXT_CREATE \ - _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) - -/* destroy a draw context */ -struct kgsl_drawctxt_destroy { - unsigned int drawctxt_id; -}; - -#define IOCTL_KGSL_DRAWCTXT_DESTROY \ - _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) - -/* add a block of pmem, fb, ashmem or user allocated address - * into the GPU address space */ -struct kgsl_map_user_mem { - int fd; - unsigned long gpuaddr; /*output param */ - size_t len; - size_t offset; - unsigned long hostptr; /*input param */ - enum kgsl_user_mem_type memtype; - unsigned int flags; -}; - -#define IOCTL_KGSL_MAP_USER_MEM \ - _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) - -struct kgsl_cmdstream_readtimestamp_ctxtid { - unsigned int context_id; - unsigned int type; - unsigned int timestamp; /*output param */ -}; - -#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \ - _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) - -struct kgsl_cmdstream_freememontimestamp_ctxtid { - unsigned int context_id; - unsigned long gpuaddr; - unsigned int type; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \ - _IOW(KGSL_IOC_TYPE, 0x17, \ - struct kgsl_cmdstream_freememontimestamp_ctxtid) - -/* add a block of pmem or fb into the GPU address space */ -struct kgsl_sharedmem_from_pmem { - int pmem_fd; - unsigned long gpuaddr; /*output param */ - unsigned int len; - unsigned int offset; -}; - -#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \ - _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) - -/* remove memory from the GPU's address space */ -struct kgsl_sharedmem_free { - unsigned long gpuaddr; -}; - -#define IOCTL_KGSL_SHAREDMEM_FREE \ - _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) - -struct kgsl_cff_user_event { - unsigned char cff_opcode; - unsigned int op1; - unsigned int op2; - unsigned int op3; - unsigned int op4; - unsigned int op5; - unsigned int __pad[2]; -}; - -#define IOCTL_KGSL_CFF_USER_EVENT \ - _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) - -struct kgsl_gmem_desc { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int pitch; -}; - -struct kgsl_buffer_desc { - void *hostptr; - unsigned long gpuaddr; - int size; - unsigned int format; - unsigned int pitch; - unsigned int enabled; -}; - -struct kgsl_bind_gmem_shadow { - unsigned int drawctxt_id; - struct kgsl_gmem_desc gmem_desc; - unsigned int shadow_x; - unsigned int shadow_y; - struct kgsl_buffer_desc shadow_buffer; - unsigned int buffer_id; -}; - -#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \ - _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) - -/* add a block of memory into the GPU address space */ - -/* - * IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC deprecated 09/2012 - * use IOCTL_KGSL_GPUMEM_ALLOC instead - */ - -struct kgsl_sharedmem_from_vmalloc { - unsigned long gpuaddr; /*output param */ - unsigned int hostptr; - unsigned int flags; -}; - -#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) - -/* - * This is being deprecated in favor of IOCTL_KGSL_GPUMEM_CACHE_SYNC which - * supports both directions (flush and invalidate). This code will still - * work, but by definition it will do a flush of the cache which might not be - * what you want to have happen on a buffer following a GPU operation. It is - * safer to go with IOCTL_KGSL_GPUMEM_CACHE_SYNC - */ - -#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \ - _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) - -struct kgsl_drawctxt_set_bin_base_offset { - unsigned int drawctxt_id; - unsigned int offset; -}; - -#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \ - _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) - -enum kgsl_cmdwindow_type { - KGSL_CMDWINDOW_MIN = 0x00000000, - KGSL_CMDWINDOW_2D = 0x00000000, - KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */ - KGSL_CMDWINDOW_MMU = 0x00000002, - KGSL_CMDWINDOW_ARBITER = 0x000000FF, - KGSL_CMDWINDOW_MAX = 0x000000FF, -}; - -/* write to the command window */ -struct kgsl_cmdwindow_write { - enum kgsl_cmdwindow_type target; - unsigned int addr; - unsigned int data; -}; - -#define IOCTL_KGSL_CMDWINDOW_WRITE \ - _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) - -struct kgsl_gpumem_alloc { - unsigned long gpuaddr; /* output param */ - size_t size; - unsigned int flags; -}; - -#define IOCTL_KGSL_GPUMEM_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) - -struct kgsl_cff_syncmem { - unsigned long gpuaddr; - size_t len; - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_CFF_SYNCMEM \ - _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) - -/* - * A timestamp event allows the user space to register an action following an - * expired timestamp. Note IOCTL_KGSL_TIMESTAMP_EVENT has been redefined to - * _IOWR to support fences which need to return a fd for the priv parameter. - */ - -struct kgsl_timestamp_event { - int type; /* Type of event (see list below) */ - unsigned int timestamp; /* Timestamp to trigger event on */ - unsigned int context_id; /* Context for the timestamp */ - void __user *priv; /* Pointer to the event specific blob */ - size_t len; /* Size of the event specific blob */ -}; - -#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD \ - _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) - -/* A genlock timestamp event releases an existing lock on timestamp expire */ - -#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 - -struct kgsl_timestamp_event_genlock { - int handle; /* Handle of the genlock lock to release */ -}; - -/* A fence timestamp event releases an existing lock on timestamp expire */ - -#define KGSL_TIMESTAMP_EVENT_FENCE 2 - -struct kgsl_timestamp_event_fence { - int fence_fd; /* Fence to signal */ -}; - -/* - * Set a property within the kernel. Uses the same structure as - * IOCTL_KGSL_GETPROPERTY - */ - -#define IOCTL_KGSL_SETPROPERTY \ - _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) - -#define IOCTL_KGSL_TIMESTAMP_EVENT \ - _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) - -/** - * struct kgsl_gpumem_alloc_id - argument to IOCTL_KGSL_GPUMEM_ALLOC_ID - * @id: returned id value for this allocation. - * @flags: mask of KGSL_MEM* values requested and actual flags on return. - * @size: requested size of the allocation and actual size on return. - * @mmapsize: returned size to pass to mmap() which may be larger than 'size' - * @gpuaddr: returned GPU address for the allocation - * - * Allocate memory for access by the GPU. The flags and size fields are echoed - * back by the kernel, so that the caller can know if the request was - * adjusted. - * - * Supported flags: - * KGSL_MEMFLAGS_GPUREADONLY: the GPU will be unable to write to the buffer - * KGSL_MEMTYPE*: usage hint for debugging aid - * KGSL_MEMALIGN*: alignment hint, may be ignored or adjusted by the kernel. - * KGSL_MEMFLAGS_USE_CPU_MAP: If set on call and return, the returned GPU - * address will be 0. Calling mmap() will set the GPU address. - */ -struct kgsl_gpumem_alloc_id { - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long gpuaddr; -/* private: reserved for future use*/ - unsigned long __pad[2]; -}; - -#define IOCTL_KGSL_GPUMEM_ALLOC_ID \ - _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id) - -/** - * struct kgsl_gpumem_free_id - argument to IOCTL_KGSL_GPUMEM_FREE_ID - * @id: GPU allocation id to free - * - * Free an allocation by id, in case a GPU address has not been assigned or - * is unknown. Freeing an allocation by id with this ioctl or by GPU address - * with IOCTL_KGSL_SHAREDMEM_FREE are equivalent. - */ -struct kgsl_gpumem_free_id { - unsigned int id; -/* private: reserved for future use*/ - unsigned int __pad; -}; - -#define IOCTL_KGSL_GPUMEM_FREE_ID \ - _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id) - -/** - * struct kgsl_gpumem_get_info - argument to IOCTL_KGSL_GPUMEM_GET_INFO - * @gpuaddr: GPU address to query. Also set on return. - * @id: GPU allocation id to query. Also set on return. - * @flags: returned mask of KGSL_MEM* values. - * @size: returned size of the allocation. - * @mmapsize: returned size to pass mmap(), which may be larger than 'size' - * @useraddr: returned address of the userspace mapping for this buffer - * - * This ioctl allows querying of all user visible attributes of an existing - * allocation, by either the GPU address or the id returned by a previous - * call to IOCTL_KGSL_GPUMEM_ALLOC_ID. Legacy allocation ioctls may not - * return all attributes so this ioctl can be used to look them up if needed. - * - */ -struct kgsl_gpumem_get_info { - unsigned long gpuaddr; - unsigned int id; - unsigned int flags; - size_t size; - size_t mmapsize; - unsigned long useraddr; -/* private: reserved for future use*/ - unsigned long __pad[4]; -}; - -#define IOCTL_KGSL_GPUMEM_GET_INFO\ - _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info) - -/** - * struct kgsl_gpumem_sync_cache - argument to IOCTL_KGSL_GPUMEM_SYNC_CACHE - * @gpuaddr: GPU address of the buffer to sync. - * @id: id of the buffer to sync. Either gpuaddr or id is sufficient. - * @op: a mask of KGSL_GPUMEM_CACHE_* values - * @offset: offset into the buffer - * @length: number of bytes starting from offset to perform - * the cache operation on - * - * Sync the L2 cache for memory headed to and from the GPU - this replaces - * KGSL_SHAREDMEM_FLUSH_CACHE since it can handle cache management for both - * directions - * - */ -struct kgsl_gpumem_sync_cache { - unsigned long gpuaddr; - unsigned int id; - unsigned int op; - size_t offset; - size_t length; -}; - -#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0) -#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN - -#define KGSL_GPUMEM_CACHE_INV (1 << 1) -#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV - -#define KGSL_GPUMEM_CACHE_FLUSH \ - (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) - -/* Flag to ensure backwards compatibility of kgsl_gpumem_sync_cache struct */ -#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U) - -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE \ - _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache) - -/** - * struct kgsl_perfcounter_get - argument to IOCTL_KGSL_PERFCOUNTER_GET - * @groupid: Performance counter group ID - * @countable: Countable to select within the group - * @offset: Return offset of the reserved LO counter - * @offset_hi: Return offset of the reserved HI counter - * - * Get an available performance counter from a specified groupid. The offset - * of the performance counter will be returned after successfully assigning - * the countable to the counter for the specified group. An error will be - * returned and an offset of 0 if the groupid is invalid or there are no - * more counters left. After successfully getting a perfcounter, the user - * must call kgsl_perfcounter_put(groupid, contable) when finished with - * the perfcounter to clear up perfcounter resources. - * - */ -struct kgsl_perfcounter_get { - unsigned int groupid; - unsigned int countable; - unsigned int offset; - unsigned int offset_hi; -/* private: reserved for future use */ - unsigned int __pad; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_GET \ - _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get) - -/** - * struct kgsl_perfcounter_put - argument to IOCTL_KGSL_PERFCOUNTER_PUT - * @groupid: Performance counter group ID - * @countable: Countable to release within the group - * - * Put an allocated performance counter to allow others to have access to the - * resource that was previously taken. This is only to be called after - * successfully getting a performance counter from kgsl_perfcounter_get(). - * - */ -struct kgsl_perfcounter_put { - unsigned int groupid; - unsigned int countable; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_PUT \ - _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put) - -/** - * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY - * @groupid: Performance counter group ID - * @countable: Return active countables array - * @size: Size of active countables array - * @max_counters: Return total number counters for the group ID - * - * Query the available performance counters given a groupid. The array - * *countables is used to return the current active countables in counters. - * The size of the array is passed in so the kernel will only write at most - * size or counter->size for the group id. The total number of available - * counters for the group ID is returned in max_counters. - * If the array or size passed in are invalid, then only the maximum number - * of counters will be returned, no data will be written to *countables. - * If the groupid is invalid an error code will be returned. - * - */ -struct kgsl_perfcounter_query { - unsigned int groupid; - /* Array to return the current countable for up to size counters */ - unsigned int __user *countables; - unsigned int count; - unsigned int max_counters; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_QUERY \ - _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query) - -/** - * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY - * @groupid: Performance counter group IDs - * @countable: Performance counter countable IDs - * @value: Return performance counter reads - * @size: Size of all arrays (groupid/countable pair and return value) - * - * Read in the current value of a performance counter given by the groupid - * and countable. - * - */ - -struct kgsl_perfcounter_read_group { - unsigned int groupid; - unsigned int countable; - unsigned long long value; -}; - -struct kgsl_perfcounter_read { - struct kgsl_perfcounter_read_group __user *reads; - unsigned int count; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_PERFCOUNTER_READ \ - _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read) -/* - * struct kgsl_gpumem_sync_cache_bulk - argument to - * IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK - * @id_list: list of GPU buffer ids of the buffers to sync - * @count: number of GPU buffer ids in id_list - * @op: a mask of KGSL_GPUMEM_CACHE_* values - * - * Sync the cache for memory headed to and from the GPU. Certain - * optimizations can be made on the cache operation based on the total - * size of the working set of memory to be managed. - */ -struct kgsl_gpumem_sync_cache_bulk { - unsigned int __user *id_list; - unsigned int count; - unsigned int op; -/* private: reserved for future use */ - unsigned int __pad[2]; /* For future binary compatibility */ -}; - -#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK \ - _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk) - -/* - * struct kgsl_cmd_syncpoint_timestamp - * @context_id: ID of a KGSL context - * @timestamp: GPU timestamp - * - * This structure defines a syncpoint comprising a context/timestamp pair. A - * list of these may be passed by IOCTL_KGSL_SUBMIT_COMMANDS to define - * dependencies that must be met before the command can be submitted to the - * hardware - */ -struct kgsl_cmd_syncpoint_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; - -struct kgsl_cmd_syncpoint_fence { - int fd; -}; - -/** - * struct kgsl_cmd_syncpoint - Define a sync point for a command batch - * @type: type of sync point defined here - * @priv: Pointer to the type specific buffer - * @size: Size of the type specific buffer - * - * This structure contains pointers defining a specific command sync point. - * The pointer and size should point to a type appropriate structure. - */ -struct kgsl_cmd_syncpoint { - int type; - void __user *priv; - size_t size; -}; - -/* Flag to indicate that the cmdlist may contain memlists */ -#define KGSL_IBDESC_MEMLIST 0x1 - -/* Flag to point out the cmdbatch profiling buffer in the memlist */ -#define KGSL_IBDESC_PROFILING_BUFFER 0x2 - -/** - * struct kgsl_submit_commands - Argument to IOCTL_KGSL_SUBMIT_COMMANDS - * @context_id: KGSL context ID that owns the commands - * @flags: - * @cmdlist: User pointer to a list of kgsl_ibdesc structures - * @numcmds: Number of commands listed in cmdlist - * @synclist: User pointer to a list of kgsl_cmd_syncpoint structures - * @numsyncs: Number of sync points listed in synclist - * @timestamp: On entry the a user defined timestamp, on exist the timestamp - * assigned to the command batch - * - * This structure specifies a command to send to the GPU hardware. This is - * similar to kgsl_issueibcmds expect that it doesn't support the legacy way to - * submit IB lists and it adds sync points to block the IB until the - * dependencies are satisified. This entry point is the new and preferred way - * to submit commands to the GPU. The memory list can be used to specify all - * memory that is referrenced in the current set of commands. - */ - -struct kgsl_submit_commands { - unsigned int context_id; - unsigned int flags; - struct kgsl_ibdesc __user *cmdlist; - unsigned int numcmds; - struct kgsl_cmd_syncpoint __user *synclist; - unsigned int numsyncs; - unsigned int timestamp; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -#define IOCTL_KGSL_SUBMIT_COMMANDS \ - _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands) - -/** - * struct kgsl_device_constraint - device constraint argument - * @context_id: KGSL context ID - * @type: type of constraint i.e pwrlevel/none - * @data: constraint data - * @size: size of the constraint data - */ -struct kgsl_device_constraint { - unsigned int type; - unsigned int context_id; - void __user *data; - size_t size; -}; - -/* Constraint Type*/ -#define KGSL_CONSTRAINT_NONE 0 -#define KGSL_CONSTRAINT_PWRLEVEL 1 - -/* PWRLEVEL constraint level*/ -/* set to min frequency */ -#define KGSL_CONSTRAINT_PWR_MIN 0 -/* set to max frequency */ -#define KGSL_CONSTRAINT_PWR_MAX 1 - -struct kgsl_device_constraint_pwrlevel { - unsigned int level; -}; - -/** - * struct kgsl_syncsource_create - Argument to IOCTL_KGSL_SYNCSOURCE_CREATE - * @id: returned id for the syncsource that was created. - * - * This ioctl creates a userspace sync timeline. - */ - -struct kgsl_syncsource_create { - unsigned int id; -/* private: reserved for future use */ - unsigned int __pad[3]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_CREATE \ - _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create) - -/** - * struct kgsl_syncsource_destroy - Argument to IOCTL_KGSL_SYNCSOURCE_DESTROY - * @id: syncsource id to destroy - * - * This ioctl creates a userspace sync timeline. - */ - -struct kgsl_syncsource_destroy { - unsigned int id; -/* private: reserved for future use */ - unsigned int __pad[3]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_DESTROY \ - _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy) - -/** - * struct kgsl_syncsource_create_fence - Argument to - * IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE - * @id: syncsource id - * @fence_fd: returned sync_fence fd - * - * Create a fence that may be signaled by userspace by calling - * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE. There are no order dependencies between - * these fences. - */ -struct kgsl_syncsource_create_fence { - unsigned int id; - int fence_fd; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -/** - * struct kgsl_syncsource_signal_fence - Argument to - * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE - * @id: syncsource id - * @fence_fd: sync_fence fd to signal - * - * Signal a fence that was created by a IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE - * call using the same syncsource id. This allows a fence to be shared - * to other processes but only signaled by the process owning the fd - * used to create the fence. - */ -#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE \ - _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence) - -struct kgsl_syncsource_signal_fence { - unsigned int id; - int fence_fd; -/* private: reserved for future use */ - unsigned int __pad[4]; -}; - -#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE \ - _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence) - -/** - * struct kgsl_cff_sync_gpuobj - Argument to IOCTL_KGSL_CFF_SYNC_GPUOBJ - * @offset: Offset into the GPU object to sync - * @length: Number of bytes to sync - * @id: ID of the GPU object to sync - */ -struct kgsl_cff_sync_gpuobj { - uint64_t offset; - uint64_t length; - unsigned int id; -}; - -#define IOCTL_KGSL_CFF_SYNC_GPUOBJ \ - _IOW(KGSL_IOC_TYPE, 0x44, struct kgsl_cff_sync_gpuobj) - -/** - * struct kgsl_gpuobj_alloc - Argument to IOCTL_KGSL_GPUOBJ_ALLOC - * @size: Size in bytes of the object to allocate - * @flags: mask of KGSL_MEMFLAG_* bits - * @va_len: Size in bytes of the virtual region to allocate - * @mmapsize: Returns the mmap() size of the object - * @id: Returns the GPU object ID of the new object - * @metadata_len: Length of the metdata to copy from the user - * @metadata: Pointer to the user specified metadata to store for the object - */ -struct kgsl_gpuobj_alloc { - uint64_t size; - uint64_t flags; - uint64_t va_len; - uint64_t mmapsize; - unsigned int id; - unsigned int metadata_len; - uint64_t metadata; -}; - -/* Let the user know that this header supports the gpuobj metadata */ -#define KGSL_GPUOBJ_ALLOC_METADATA_MAX 64 - -#define IOCTL_KGSL_GPUOBJ_ALLOC \ - _IOWR(KGSL_IOC_TYPE, 0x45, struct kgsl_gpuobj_alloc) - -/** - * struct kgsl_gpuobj_free - Argument to IOCTL_KGLS_GPUOBJ_FREE - * @flags: Mask of: KGSL_GUPOBJ_FREE_ON_EVENT - * @priv: Pointer to the private object if KGSL_GPUOBJ_FREE_ON_EVENT is - * specified - * @id: ID of the GPU object to free - * @type: If KGSL_GPUOBJ_FREE_ON_EVENT is specified, the type of asynchronous - * event to free on - * @len: Length of the data passed in priv - */ -struct kgsl_gpuobj_free { - uint64_t flags; - uint64_t __user priv; - unsigned int id; - unsigned int type; - unsigned int len; -}; - -#define KGSL_GPUOBJ_FREE_ON_EVENT 1 - -#define KGSL_GPU_EVENT_TIMESTAMP 1 -#define KGSL_GPU_EVENT_FENCE 2 - -/** - * struct kgsl_gpu_event_timestamp - Specifies a timestamp event to free a GPU - * object on - * @context_id: ID of the timestamp event to wait for - * @timestamp: Timestamp of the timestamp event to wait for - */ -struct kgsl_gpu_event_timestamp { - unsigned int context_id; - unsigned int timestamp; -}; - -/** - * struct kgsl_gpu_event_fence - Specifies a fence ID to to free a GPU object on - * @fd: File descriptor for the fence - */ -struct kgsl_gpu_event_fence { - int fd; -}; - -#define IOCTL_KGSL_GPUOBJ_FREE \ - _IOW(KGSL_IOC_TYPE, 0x46, struct kgsl_gpuobj_free) - -/** - * struct kgsl_gpuobj_info - argument to IOCTL_KGSL_GPUOBJ_INFO - * @gpuaddr: GPU address of the object - * @flags: Current flags for the object - * @size: Size of the object - * @va_len: VA size of the object - * @va_addr: Virtual address of the object (if it is mapped) - * id - GPU object ID of the object to query - */ -struct kgsl_gpuobj_info { - uint64_t gpuaddr; - uint64_t flags; - uint64_t size; - uint64_t va_len; - uint64_t va_addr; - unsigned int id; -}; - -#define IOCTL_KGSL_GPUOBJ_INFO \ - _IOWR(KGSL_IOC_TYPE, 0x47, struct kgsl_gpuobj_info) - -/** - * struct kgsl_gpuobj_import - argument to IOCTL_KGSL_GPUOBJ_IMPORT - * @priv: Pointer to the private data for the import type - * @priv_len: Length of the private data - * @flags: Mask of KGSL_MEMFLAG_ flags - * @type: Type of the import (KGSL_USER_MEM_TYPE_*) - * @id: Returns the ID of the new GPU object - */ -struct kgsl_gpuobj_import { - uint64_t __user priv; - uint64_t priv_len; - uint64_t flags; - unsigned int type; - unsigned int id; -}; - -/** - * struct kgsl_gpuobj_import_dma_buf - import a dmabuf object - * @fd: File descriptor for the dma-buf object - */ -struct kgsl_gpuobj_import_dma_buf { - int fd; -}; - -/** - * struct kgsl_gpuobj_import_useraddr - import an object based on a useraddr - * @virtaddr: Virtual address of the object to import - */ -struct kgsl_gpuobj_import_useraddr { - uint64_t virtaddr; -}; - -#define IOCTL_KGSL_GPUOBJ_IMPORT \ - _IOWR(KGSL_IOC_TYPE, 0x48, struct kgsl_gpuobj_import) - -/** - * struct kgsl_gpuobj_sync_obj - Individual GPU object to sync - * @offset: Offset within the GPU object to sync - * @length: Number of bytes to sync - * @id: ID of the GPU object to sync - * @op: Cache operation to execute - */ - -struct kgsl_gpuobj_sync_obj { - uint64_t offset; - uint64_t length; - unsigned int id; - unsigned int op; -}; - -/** - * struct kgsl_gpuobj_sync - Argument for IOCTL_KGSL_GPUOBJ_SYNC - * @objs: Pointer to an array of kgsl_gpuobj_sync_obj structs - * @obj_len: Size of each item in the array - * @count: Number of items in the array - */ - -struct kgsl_gpuobj_sync { - uint64_t __user objs; - unsigned int obj_len; - unsigned int count; -}; - -#define IOCTL_KGSL_GPUOBJ_SYNC \ - _IOW(KGSL_IOC_TYPE, 0x49, struct kgsl_gpuobj_sync) - -/** - * struct kgsl_command_object - GPU command object - * @offset: GPU address offset of the object - * @gpuaddr: GPU address of the object - * @size: Size of the object - * @flags: Current flags for the object - * @id - GPU command object ID - */ -struct kgsl_command_object { - uint64_t offset; - uint64_t gpuaddr; - uint64_t size; - unsigned int flags; - unsigned int id; -}; - -/** - * struct kgsl_command_syncpoint - GPU syncpoint object - * @priv: Pointer to the type specific buffer - * @size: Size of the type specific buffer - * @type: type of sync point defined here - */ -struct kgsl_command_syncpoint { - uint64_t __user priv; - uint64_t size; - unsigned int type; -}; - -/** - * struct kgsl_command_object - Argument for IOCTL_KGSL_GPU_COMMAND - * @flags: Current flags for the object - * @cmdlist: List of kgsl_command_objects for submission - * @cmd_size: Size of kgsl_command_objects structure - * @numcmds: Number of kgsl_command_objects in command list - * @objlist: List of kgsl_command_objects for tracking - * @obj_size: Size of kgsl_command_objects structure - * @numobjs: Number of kgsl_command_objects in object list - * @synclist: List of kgsl_command_syncpoints - * @sync_size: Size of kgsl_command_syncpoint structure - * @numsyncs: Number of kgsl_command_syncpoints in syncpoint list - * @context_id: Context ID submittin ghte kgsl_gpu_command - * @timestamp: Timestamp for the submitted commands - */ -struct kgsl_gpu_command { - uint64_t flags; - uint64_t __user cmdlist; - unsigned int cmdsize; - unsigned int numcmds; - uint64_t __user objlist; - unsigned int objsize; - unsigned int numobjs; - uint64_t __user synclist; - unsigned int syncsize; - unsigned int numsyncs; - unsigned int context_id; - unsigned int timestamp; -}; - -#define IOCTL_KGSL_GPU_COMMAND \ - _IOWR(KGSL_IOC_TYPE, 0x4A, struct kgsl_gpu_command) - -/** - * struct kgsl_preemption_counters_query - argument to - * IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY - * @counters: Return preemption counters array - * @size_user: Size allocated by userspace - * @size_priority_level: Size of preemption counters for each - * priority level - * @max_priority_level: Return max number of priority levels - * - * Query the available preemption counters. The array counters - * is used to return preemption counters. The size of the array - * is passed in so the kernel will only write at most size_user - * or max available preemption counters. The total number of - * preemption counters is returned in max_priority_level. If the - * array or size passed in are invalid, then an error is - * returned back. - */ -struct kgsl_preemption_counters_query { - uint64_t __user counters; - unsigned int size_user; - unsigned int size_priority_level; - unsigned int max_priority_level; -}; - -#define IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY \ - _IOWR(KGSL_IOC_TYPE, 0x4B, struct kgsl_preemption_counters_query) - -/** - * struct kgsl_gpuobj_set_info - argument for IOCTL_KGSL_GPUOBJ_SET_INFO - * @flags: Flags to indicate which paramaters to change - * @metadata: If KGSL_GPUOBJ_SET_INFO_METADATA is set, a pointer to the new - * metadata - * @id: GPU memory object ID to change - * @metadata_len: If KGSL_GPUOBJ_SET_INFO_METADATA is set, the length of the - * new metadata string - * @type: If KGSL_GPUOBJ_SET_INFO_TYPE is set, the new type of the memory object - */ - -#define KGSL_GPUOBJ_SET_INFO_METADATA (1 << 0) -#define KGSL_GPUOBJ_SET_INFO_TYPE (1 << 1) - -struct kgsl_gpuobj_set_info { - uint64_t flags; - uint64_t metadata; - unsigned int id; - unsigned int metadata_len; - unsigned int type; -}; - -#define IOCTL_KGSL_GPUOBJ_SET_INFO \ - _IOW(KGSL_IOC_TYPE, 0x4C, struct kgsl_gpuobj_set_info) - -#endif /* _UAPI_MSM_KGSL_H */ diff --git a/tinygrad/extra/qcom_gpu_driver/msm_kgsl.py b/tinygrad/extra/qcom_gpu_driver/msm_kgsl.py deleted file mode 100644 index 870ad572..00000000 --- a/tinygrad/extra/qcom_gpu_driver/msm_kgsl.py +++ /dev/null @@ -1,1035 +0,0 @@ -# type: ignore -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - - -# values for enumeration 'kgsl_user_mem_type' -kgsl_user_mem_type__enumvalues = { - 0: 'KGSL_USER_MEM_TYPE_PMEM', - 1: 'KGSL_USER_MEM_TYPE_ASHMEM', - 2: 'KGSL_USER_MEM_TYPE_ADDR', - 3: 'KGSL_USER_MEM_TYPE_ION', - 3: 'KGSL_USER_MEM_TYPE_DMABUF', - 7: 'KGSL_USER_MEM_TYPE_MAX', -} -KGSL_USER_MEM_TYPE_PMEM = 0 -KGSL_USER_MEM_TYPE_ASHMEM = 1 -KGSL_USER_MEM_TYPE_ADDR = 2 -KGSL_USER_MEM_TYPE_ION = 3 -KGSL_USER_MEM_TYPE_DMABUF = 3 -KGSL_USER_MEM_TYPE_MAX = 7 -kgsl_user_mem_type = ctypes.c_uint32 # enum - -# values for enumeration 'kgsl_ctx_reset_stat' -kgsl_ctx_reset_stat__enumvalues = { - 0: 'KGSL_CTX_STAT_NO_ERROR', - 1: 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 2: 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 3: 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', -} -KGSL_CTX_STAT_NO_ERROR = 0 -KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 1 -KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 2 -KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 3 -kgsl_ctx_reset_stat = ctypes.c_uint32 # enum - -# values for enumeration 'kgsl_deviceid' -kgsl_deviceid__enumvalues = { - 0: 'KGSL_DEVICE_3D0', - 1: 'KGSL_DEVICE_MAX', -} -KGSL_DEVICE_3D0 = 0 -KGSL_DEVICE_MAX = 1 -kgsl_deviceid = ctypes.c_uint32 # enum -class struct_kgsl_devinfo(Structure): - pass - -struct_kgsl_devinfo._pack_ = 1 # source:False -struct_kgsl_devinfo._fields_ = [ - ('device_id', ctypes.c_uint32), - ('chip_id', ctypes.c_uint32), - ('mmu_enabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gmem_gpubaseaddr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('gmem_sizebytes', ctypes.c_uint64), -] - -class struct_kgsl_devmemstore(Structure): - pass - -struct_kgsl_devmemstore._pack_ = 1 # source:False -struct_kgsl_devmemstore._fields_ = [ - ('soptimestamp', ctypes.c_uint32), - ('sbz', ctypes.c_uint32), - ('eoptimestamp', ctypes.c_uint32), - ('sbz2', ctypes.c_uint32), - ('preempted', ctypes.c_uint32), - ('sbz3', ctypes.c_uint32), - ('ref_wait_ts', ctypes.c_uint32), - ('sbz4', ctypes.c_uint32), - ('current_context', ctypes.c_uint32), - ('sbz5', ctypes.c_uint32), -] - - -# values for enumeration 'kgsl_timestamp_type' -kgsl_timestamp_type__enumvalues = { - 1: 'KGSL_TIMESTAMP_CONSUMED', - 2: 'KGSL_TIMESTAMP_RETIRED', - 3: 'KGSL_TIMESTAMP_QUEUED', -} -KGSL_TIMESTAMP_CONSUMED = 1 -KGSL_TIMESTAMP_RETIRED = 2 -KGSL_TIMESTAMP_QUEUED = 3 -kgsl_timestamp_type = ctypes.c_uint32 # enum -class struct_kgsl_shadowprop(Structure): - pass - -struct_kgsl_shadowprop._pack_ = 1 # source:False -struct_kgsl_shadowprop._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_version(Structure): - pass - -struct_kgsl_version._pack_ = 1 # source:False -struct_kgsl_version._fields_ = [ - ('drv_major', ctypes.c_uint32), - ('drv_minor', ctypes.c_uint32), - ('dev_major', ctypes.c_uint32), - ('dev_minor', ctypes.c_uint32), -] - -class struct_kgsl_sp_generic_mem(Structure): - pass - -struct_kgsl_sp_generic_mem._pack_ = 1 # source:False -struct_kgsl_sp_generic_mem._fields_ = [ - ('local', ctypes.c_uint64), - ('pvt', ctypes.c_uint64), -] - -class struct_kgsl_ucode_version(Structure): - pass - -struct_kgsl_ucode_version._pack_ = 1 # source:False -struct_kgsl_ucode_version._fields_ = [ - ('pfp', ctypes.c_uint32), - ('pm4', ctypes.c_uint32), -] - -class struct_kgsl_gpmu_version(Structure): - pass - -struct_kgsl_gpmu_version._pack_ = 1 # source:False -struct_kgsl_gpmu_version._fields_ = [ - ('major', ctypes.c_uint32), - ('minor', ctypes.c_uint32), - ('features', ctypes.c_uint32), -] - -class struct_kgsl_ibdesc(Structure): - pass - -struct_kgsl_ibdesc._pack_ = 1 # source:False -struct_kgsl_ibdesc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64), - ('sizedwords', ctypes.c_uint64), - ('ctrl', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_cmdbatch_profiling_buffer(Structure): - pass - -struct_kgsl_cmdbatch_profiling_buffer._pack_ = 1 # source:False -struct_kgsl_cmdbatch_profiling_buffer._fields_ = [ - ('wall_clock_s', ctypes.c_uint64), - ('wall_clock_ns', ctypes.c_uint64), - ('gpu_ticks_queued', ctypes.c_uint64), - ('gpu_ticks_submitted', ctypes.c_uint64), - ('gpu_ticks_retired', ctypes.c_uint64), -] - -class struct_kgsl_device_getproperty(Structure): - pass - -struct_kgsl_device_getproperty._pack_ = 1 # source:False -struct_kgsl_device_getproperty._fields_ = [ - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('value', ctypes.POINTER(None)), - ('sizebytes', ctypes.c_uint64), -] - -class struct_kgsl_device_waittimestamp(Structure): - pass - -struct_kgsl_device_waittimestamp._pack_ = 1 # source:False -struct_kgsl_device_waittimestamp._fields_ = [ - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -class struct_kgsl_device_waittimestamp_ctxtid(Structure): - pass - -struct_kgsl_device_waittimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_device_waittimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -class struct_kgsl_ringbuffer_issueibcmds(Structure): - pass - -struct_kgsl_ringbuffer_issueibcmds._pack_ = 1 # source:False -struct_kgsl_ringbuffer_issueibcmds._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ibdesc_addr', ctypes.c_uint64), - ('numibs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_kgsl_cmdstream_readtimestamp(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp._pack_ = 1 # source:False -struct_kgsl_cmdstream_readtimestamp._fields_ = [ - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_cmdstream_freememontimestamp(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp._pack_ = 1 # source:False -struct_kgsl_cmdstream_freememontimestamp._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_drawctxt_create(Structure): - pass - -struct_kgsl_drawctxt_create._pack_ = 1 # source:False -struct_kgsl_drawctxt_create._fields_ = [ - ('flags', ctypes.c_uint32), - ('drawctxt_id', ctypes.c_uint32), -] - -class struct_kgsl_drawctxt_destroy(Structure): - pass - -struct_kgsl_drawctxt_destroy._pack_ = 1 # source:False -struct_kgsl_drawctxt_destroy._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), -] - -class struct_kgsl_map_user_mem(Structure): - pass - -struct_kgsl_map_user_mem._pack_ = 1 # source:False -struct_kgsl_map_user_mem._fields_ = [ - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('hostptr', ctypes.c_uint64), - ('memtype', kgsl_user_mem_type), - ('flags', ctypes.c_uint32), -] - -class struct_kgsl_cmdstream_readtimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_cmdstream_readtimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_cmdstream_freememontimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_cmdstream_freememontimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_sharedmem_from_pmem(Structure): - pass - -struct_kgsl_sharedmem_from_pmem._pack_ = 1 # source:False -struct_kgsl_sharedmem_from_pmem._fields_ = [ - ('pmem_fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint32), - ('offset', ctypes.c_uint32), -] - -class struct_kgsl_sharedmem_free(Structure): - pass - -struct_kgsl_sharedmem_free._pack_ = 1 # source:False -struct_kgsl_sharedmem_free._fields_ = [ - ('gpuaddr', ctypes.c_uint64), -] - -class struct_kgsl_cff_user_event(Structure): - pass - -struct_kgsl_cff_user_event._pack_ = 1 # source:False -struct_kgsl_cff_user_event._fields_ = [ - ('cff_opcode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('op1', ctypes.c_uint32), - ('op2', ctypes.c_uint32), - ('op3', ctypes.c_uint32), - ('op4', ctypes.c_uint32), - ('op5', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -class struct_kgsl_gmem_desc(Structure): - pass - -struct_kgsl_gmem_desc._pack_ = 1 # source:False -struct_kgsl_gmem_desc._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), -] - -class struct_kgsl_buffer_desc(Structure): - pass - -struct_kgsl_buffer_desc._pack_ = 1 # source:False -struct_kgsl_buffer_desc._fields_ = [ - ('hostptr', ctypes.POINTER(None)), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_int32), - ('format', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), - ('enabled', ctypes.c_uint32), -] - -class struct_kgsl_bind_gmem_shadow(Structure): - pass - -struct_kgsl_bind_gmem_shadow._pack_ = 1 # source:False -struct_kgsl_bind_gmem_shadow._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('gmem_desc', struct_kgsl_gmem_desc), - ('shadow_x', ctypes.c_uint32), - ('shadow_y', ctypes.c_uint32), - ('shadow_buffer', struct_kgsl_buffer_desc), - ('buffer_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_sharedmem_from_vmalloc(Structure): - pass - -struct_kgsl_sharedmem_from_vmalloc._pack_ = 1 # source:False -struct_kgsl_sharedmem_from_vmalloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('hostptr', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -class struct_kgsl_drawctxt_set_bin_base_offset(Structure): - pass - -struct_kgsl_drawctxt_set_bin_base_offset._pack_ = 1 # source:False -struct_kgsl_drawctxt_set_bin_base_offset._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('offset', ctypes.c_uint32), -] - - -# values for enumeration 'kgsl_cmdwindow_type' -kgsl_cmdwindow_type__enumvalues = { - 0: 'KGSL_CMDWINDOW_MIN', - 0: 'KGSL_CMDWINDOW_2D', - 1: 'KGSL_CMDWINDOW_3D', - 2: 'KGSL_CMDWINDOW_MMU', - 255: 'KGSL_CMDWINDOW_ARBITER', - 255: 'KGSL_CMDWINDOW_MAX', -} -KGSL_CMDWINDOW_MIN = 0 -KGSL_CMDWINDOW_2D = 0 -KGSL_CMDWINDOW_3D = 1 -KGSL_CMDWINDOW_MMU = 2 -KGSL_CMDWINDOW_ARBITER = 255 -KGSL_CMDWINDOW_MAX = 255 -kgsl_cmdwindow_type = ctypes.c_uint32 # enum -class struct_kgsl_cmdwindow_write(Structure): - pass - -struct_kgsl_cmdwindow_write._pack_ = 1 # source:False -struct_kgsl_cmdwindow_write._fields_ = [ - ('target', kgsl_cmdwindow_type), - ('addr', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -class struct_kgsl_gpumem_alloc(Structure): - pass - -struct_kgsl_gpumem_alloc._pack_ = 1 # source:False -struct_kgsl_gpumem_alloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_cff_syncmem(Structure): - pass - -struct_kgsl_cff_syncmem._pack_ = 1 # source:False -struct_kgsl_cff_syncmem._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('__pad', ctypes.c_uint32 * 2), -] - -class struct_kgsl_timestamp_event(Structure): - pass - -struct_kgsl_timestamp_event._pack_ = 1 # source:False -struct_kgsl_timestamp_event._fields_ = [ - ('type', ctypes.c_int32), - ('timestamp', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('len', ctypes.c_uint64), -] - -class struct_kgsl_timestamp_event_genlock(Structure): - pass - -struct_kgsl_timestamp_event_genlock._pack_ = 1 # source:False -struct_kgsl_timestamp_event_genlock._fields_ = [ - ('handle', ctypes.c_int32), -] - -class struct_kgsl_timestamp_event_fence(Structure): - pass - -struct_kgsl_timestamp_event_fence._pack_ = 1 # source:False -struct_kgsl_timestamp_event_fence._fields_ = [ - ('fence_fd', ctypes.c_int32), -] - -class struct_kgsl_gpumem_alloc_id(Structure): - pass - -struct_kgsl_gpumem_alloc_id._pack_ = 1 # source:False -struct_kgsl_gpumem_alloc_id._fields_ = [ - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 2), -] - -class struct_kgsl_gpumem_free_id(Structure): - pass - -struct_kgsl_gpumem_free_id._pack_ = 1 # source:False -struct_kgsl_gpumem_free_id._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), -] - -class struct_kgsl_gpumem_get_info(Structure): - pass - -struct_kgsl_gpumem_get_info._pack_ = 1 # source:False -struct_kgsl_gpumem_get_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('useraddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 4), -] - -class struct_kgsl_gpumem_sync_cache(Structure): - pass - -struct_kgsl_gpumem_sync_cache._pack_ = 1 # source:False -struct_kgsl_gpumem_sync_cache._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), -] - -class struct_kgsl_perfcounter_get(Structure): - pass - -struct_kgsl_perfcounter_get._pack_ = 1 # source:False -struct_kgsl_perfcounter_get._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('offset_hi', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), -] - -class struct_kgsl_perfcounter_put(Structure): - pass - -struct_kgsl_perfcounter_put._pack_ = 1 # source:False -struct_kgsl_perfcounter_put._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -class struct_kgsl_perfcounter_query(Structure): - pass - -struct_kgsl_perfcounter_query._pack_ = 1 # source:False -struct_kgsl_perfcounter_query._fields_ = [ - ('groupid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('countables', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('max_counters', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -class struct_kgsl_perfcounter_read_group(Structure): - pass - -struct_kgsl_perfcounter_read_group._pack_ = 1 # source:False -struct_kgsl_perfcounter_read_group._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('value', ctypes.c_uint64), -] - -class struct_kgsl_perfcounter_read(Structure): - pass - -struct_kgsl_perfcounter_read._pack_ = 1 # source:False -struct_kgsl_perfcounter_read._fields_ = [ - ('reads', ctypes.POINTER(struct_kgsl_perfcounter_read_group)), - ('count', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpumem_sync_cache_bulk(Structure): - pass - -struct_kgsl_gpumem_sync_cache_bulk._pack_ = 1 # source:False -struct_kgsl_gpumem_sync_cache_bulk._fields_ = [ - ('id_list', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -class struct_kgsl_cmd_syncpoint_timestamp(Structure): - pass - -struct_kgsl_cmd_syncpoint_timestamp._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_cmd_syncpoint_fence(Structure): - pass - -struct_kgsl_cmd_syncpoint_fence._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint_fence._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_cmd_syncpoint(Structure): - pass - -struct_kgsl_cmd_syncpoint._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint._fields_ = [ - ('type', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), -] - -class struct_kgsl_submit_commands(Structure): - pass - -struct_kgsl_submit_commands._pack_ = 1 # source:False -struct_kgsl_submit_commands._fields_ = [ - ('context_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('cmdlist', ctypes.POINTER(struct_kgsl_ibdesc)), - ('numcmds', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('synclist', ctypes.POINTER(struct_kgsl_cmd_syncpoint)), - ('numsyncs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 4), -] - -class struct_kgsl_device_constraint(Structure): - pass - -struct_kgsl_device_constraint._pack_ = 1 # source:False -struct_kgsl_device_constraint._fields_ = [ - ('type', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('data', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), -] - -class struct_kgsl_device_constraint_pwrlevel(Structure): - pass - -struct_kgsl_device_constraint_pwrlevel._pack_ = 1 # source:False -struct_kgsl_device_constraint_pwrlevel._fields_ = [ - ('level', ctypes.c_uint32), -] - -class struct_kgsl_syncsource_create(Structure): - pass - -struct_kgsl_syncsource_create._pack_ = 1 # source:False -struct_kgsl_syncsource_create._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), -] - -class struct_kgsl_syncsource_destroy(Structure): - pass - -struct_kgsl_syncsource_destroy._pack_ = 1 # source:False -struct_kgsl_syncsource_destroy._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), -] - -class struct_kgsl_syncsource_create_fence(Structure): - pass - -struct_kgsl_syncsource_create_fence._pack_ = 1 # source:False -struct_kgsl_syncsource_create_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), -] - -class struct_kgsl_syncsource_signal_fence(Structure): - pass - -struct_kgsl_syncsource_signal_fence._pack_ = 1 # source:False -struct_kgsl_syncsource_signal_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), -] - -class struct_kgsl_cff_sync_gpuobj(Structure): - pass - -struct_kgsl_cff_sync_gpuobj._pack_ = 1 # source:False -struct_kgsl_cff_sync_gpuobj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpuobj_alloc(Structure): - pass - -struct_kgsl_gpuobj_alloc._pack_ = 1 # source:False -struct_kgsl_gpuobj_alloc._fields_ = [ - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('metadata', ctypes.c_uint64), -] - -class struct_kgsl_gpuobj_free(Structure): - pass - -struct_kgsl_gpuobj_free._pack_ = 1 # source:False -struct_kgsl_gpuobj_free._fields_ = [ - ('flags', ctypes.c_uint64), - ('priv', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpu_event_timestamp(Structure): - pass - -struct_kgsl_gpu_event_timestamp._pack_ = 1 # source:False -struct_kgsl_gpu_event_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_gpu_event_fence(Structure): - pass - -struct_kgsl_gpu_event_fence._pack_ = 1 # source:False -struct_kgsl_gpu_event_fence._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_gpuobj_info(Structure): - pass - -struct_kgsl_gpuobj_info._pack_ = 1 # source:False -struct_kgsl_gpuobj_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('va_addr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpuobj_import(Structure): - pass - -struct_kgsl_gpuobj_import._pack_ = 1 # source:False -struct_kgsl_gpuobj_import._fields_ = [ - ('priv', ctypes.c_uint64), - ('priv_len', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('id', ctypes.c_uint32), -] - -class struct_kgsl_gpuobj_import_dma_buf(Structure): - pass - -struct_kgsl_gpuobj_import_dma_buf._pack_ = 1 # source:False -struct_kgsl_gpuobj_import_dma_buf._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_gpuobj_import_useraddr(Structure): - pass - -struct_kgsl_gpuobj_import_useraddr._pack_ = 1 # source:False -struct_kgsl_gpuobj_import_useraddr._fields_ = [ - ('virtaddr', ctypes.c_uint64), -] - -class struct_kgsl_gpuobj_sync_obj(Structure): - pass - -struct_kgsl_gpuobj_sync_obj._pack_ = 1 # source:False -struct_kgsl_gpuobj_sync_obj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), -] - -class struct_kgsl_gpuobj_sync(Structure): - pass - -struct_kgsl_gpuobj_sync._pack_ = 1 # source:False -struct_kgsl_gpuobj_sync._fields_ = [ - ('objs', ctypes.c_uint64), - ('obj_len', ctypes.c_uint32), - ('count', ctypes.c_uint32), -] - -class struct_kgsl_command_object(Structure): - pass - -struct_kgsl_command_object._pack_ = 1 # source:False -struct_kgsl_command_object._fields_ = [ - ('offset', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('id', ctypes.c_uint32), -] - -class struct_kgsl_command_syncpoint(Structure): - pass - -struct_kgsl_command_syncpoint._pack_ = 1 # source:False -struct_kgsl_command_syncpoint._fields_ = [ - ('priv', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpu_command(Structure): - pass - -struct_kgsl_gpu_command._pack_ = 1 # source:False -struct_kgsl_gpu_command._fields_ = [ - ('flags', ctypes.c_uint64), - ('cmdlist', ctypes.c_uint64), - ('cmdsize', ctypes.c_uint32), - ('numcmds', ctypes.c_uint32), - ('objlist', ctypes.c_uint64), - ('objsize', ctypes.c_uint32), - ('numobjs', ctypes.c_uint32), - ('synclist', ctypes.c_uint64), - ('syncsize', ctypes.c_uint32), - ('numsyncs', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_preemption_counters_query(Structure): - pass - -struct_kgsl_preemption_counters_query._pack_ = 1 # source:False -struct_kgsl_preemption_counters_query._fields_ = [ - ('counters', ctypes.c_uint64), - ('size_user', ctypes.c_uint32), - ('size_priority_level', ctypes.c_uint32), - ('max_priority_level', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpuobj_set_info(Structure): - pass - -struct_kgsl_gpuobj_set_info._pack_ = 1 # source:False -struct_kgsl_gpuobj_set_info._fields_ = [ - ('flags', ctypes.c_uint64), - ('metadata', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -__all__ = \ - ['KGSL_CMDWINDOW_2D', 'KGSL_CMDWINDOW_3D', - 'KGSL_CMDWINDOW_ARBITER', 'KGSL_CMDWINDOW_MAX', - 'KGSL_CMDWINDOW_MIN', 'KGSL_CMDWINDOW_MMU', - 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_NO_ERROR', - 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', 'KGSL_DEVICE_3D0', - 'KGSL_DEVICE_MAX', 'KGSL_TIMESTAMP_CONSUMED', - 'KGSL_TIMESTAMP_QUEUED', 'KGSL_TIMESTAMP_RETIRED', - 'KGSL_USER_MEM_TYPE_ADDR', 'KGSL_USER_MEM_TYPE_ASHMEM', - 'KGSL_USER_MEM_TYPE_DMABUF', 'KGSL_USER_MEM_TYPE_ION', - 'KGSL_USER_MEM_TYPE_MAX', 'KGSL_USER_MEM_TYPE_PMEM', - 'kgsl_cmdwindow_type', 'kgsl_ctx_reset_stat', 'kgsl_deviceid', - 'kgsl_timestamp_type', 'kgsl_user_mem_type', - 'struct_kgsl_bind_gmem_shadow', 'struct_kgsl_buffer_desc', - 'struct_kgsl_cff_sync_gpuobj', 'struct_kgsl_cff_syncmem', - 'struct_kgsl_cff_user_event', 'struct_kgsl_cmd_syncpoint', - 'struct_kgsl_cmd_syncpoint_fence', - 'struct_kgsl_cmd_syncpoint_timestamp', - 'struct_kgsl_cmdbatch_profiling_buffer', - 'struct_kgsl_cmdstream_freememontimestamp', - 'struct_kgsl_cmdstream_freememontimestamp_ctxtid', - 'struct_kgsl_cmdstream_readtimestamp', - 'struct_kgsl_cmdstream_readtimestamp_ctxtid', - 'struct_kgsl_cmdwindow_write', 'struct_kgsl_command_object', - 'struct_kgsl_command_syncpoint', 'struct_kgsl_device_constraint', - 'struct_kgsl_device_constraint_pwrlevel', - 'struct_kgsl_device_getproperty', - 'struct_kgsl_device_waittimestamp', - 'struct_kgsl_device_waittimestamp_ctxtid', 'struct_kgsl_devinfo', - 'struct_kgsl_devmemstore', 'struct_kgsl_drawctxt_create', - 'struct_kgsl_drawctxt_destroy', - 'struct_kgsl_drawctxt_set_bin_base_offset', - 'struct_kgsl_gmem_desc', 'struct_kgsl_gpmu_version', - 'struct_kgsl_gpu_command', 'struct_kgsl_gpu_event_fence', - 'struct_kgsl_gpu_event_timestamp', 'struct_kgsl_gpumem_alloc', - 'struct_kgsl_gpumem_alloc_id', 'struct_kgsl_gpumem_free_id', - 'struct_kgsl_gpumem_get_info', 'struct_kgsl_gpumem_sync_cache', - 'struct_kgsl_gpumem_sync_cache_bulk', 'struct_kgsl_gpuobj_alloc', - 'struct_kgsl_gpuobj_free', 'struct_kgsl_gpuobj_import', - 'struct_kgsl_gpuobj_import_dma_buf', - 'struct_kgsl_gpuobj_import_useraddr', 'struct_kgsl_gpuobj_info', - 'struct_kgsl_gpuobj_set_info', 'struct_kgsl_gpuobj_sync', - 'struct_kgsl_gpuobj_sync_obj', 'struct_kgsl_ibdesc', - 'struct_kgsl_map_user_mem', 'struct_kgsl_perfcounter_get', - 'struct_kgsl_perfcounter_put', 'struct_kgsl_perfcounter_query', - 'struct_kgsl_perfcounter_read', - 'struct_kgsl_perfcounter_read_group', - 'struct_kgsl_preemption_counters_query', - 'struct_kgsl_ringbuffer_issueibcmds', 'struct_kgsl_shadowprop', - 'struct_kgsl_sharedmem_free', 'struct_kgsl_sharedmem_from_pmem', - 'struct_kgsl_sharedmem_from_vmalloc', - 'struct_kgsl_sp_generic_mem', 'struct_kgsl_submit_commands', - 'struct_kgsl_syncsource_create', - 'struct_kgsl_syncsource_create_fence', - 'struct_kgsl_syncsource_destroy', - 'struct_kgsl_syncsource_signal_fence', - 'struct_kgsl_timestamp_event', - 'struct_kgsl_timestamp_event_fence', - 'struct_kgsl_timestamp_event_genlock', - 'struct_kgsl_ucode_version', 'struct_kgsl_version'] diff --git a/tinygrad/extra/qcom_gpu_driver/opencl_ioctl.py b/tinygrad/extra/qcom_gpu_driver/opencl_ioctl.py deleted file mode 100644 index ea1896bd..00000000 --- a/tinygrad/extra/qcom_gpu_driver/opencl_ioctl.py +++ /dev/null @@ -1,284 +0,0 @@ -# type: ignore -import ctypes, ctypes.util, struct, fcntl, re -from hexdump import hexdump -from copy import deepcopy -import pathlib, sys -from tinygrad.helpers import to_mv, getenv -from tinygrad.runtime.autogen import adreno -sys.path.append(pathlib.Path(__file__).parent.parent.parent.as_posix()) - -IOCTL = getenv("IOCTL", 0) - -ops = {} -import xml.etree.ElementTree as ET -xml = ET.parse(pathlib.Path(__file__).parent / "adreno_pm4.xml") -for child in xml.getroot(): - if 'name' in child.attrib and child.attrib['name'] == "adreno_pm4_type3_packets": - for sc in child: - if 'name' in sc.attrib and ('variants' not in sc.attrib or sc.attrib['variants'] != "A2XX"): - ops[int(sc.attrib['value'], 0x10)] = sc.attrib['name'] -#print(ops) -#exit(0) - -CAPTURED_STATE = {} - -REGS = {} -for k, v in adreno.__dict__.items(): - if k.startswith("REG_") and isinstance(v, int) and v > 1024: REGS[v] = k - -from extra.qcom_gpu_driver import msm_kgsl -def ioctls_from_header(): - hdr = (pathlib.Path(__file__).parent.parent.parent / "extra/qcom_gpu_driver/msm_kgsl.h").read_text().replace("\\\n", "") - pattern = r'#define\s+(IOCTL_KGSL_[A-Z0-9_]+)\s+_IOWR?\(KGSL_IOC_TYPE,\s+(0x[0-9a-fA-F]+),\s+struct\s([A-Za-z0-9_]+)\)' - matches = re.findall(pattern, hdr, re.MULTILINE) - return {int(nr, 0x10):(name, getattr(msm_kgsl, "struct_"+sname)) for name, nr, sname in matches} - -nrs = ioctls_from_header() - -# https://github.com/ensc/dietlibc/blob/master/include/sys/aarch64-ioctl.h - -def get_struct(argp, stype): - return ctypes.cast(ctypes.c_void_p(argp), ctypes.POINTER(stype)).contents - -def format_struct(s): - sdats = [] - for field_name, field_type in s._fields_: - if field_name in {"__pad", "PADDING_0"}: continue - dat = getattr(s, field_name) - if isinstance(dat, int): sdats.append(f"{field_name}:0x{dat:X}") - else: sdats.append(f"{field_name}:{dat}") - return sdats - -import mmap -mmaped = {} -def get_mem(addr, vlen): - for k,v in mmaped.items(): - if k <= addr and addr < k+len(v): - return v[addr-k:addr-k+vlen] - # hope it was mmapped by someone else - return bytes(to_mv(addr, vlen)) - -def hprint(vals): - ret = [] - for v in vals: - if v > 31: ret.append(f"{v:#x}") - else: ret.append(f"{v}") - return f"({','.join(ret)})" - -ST6_SHADER = 0 -ST6_CONSTANTS = 1 -ST6_UBO = 2 -ST6_IBO = 3 - -SB6_CS_TEX = 5 -SB6_CS_SHADER = 13 - -def parse_cmd_buf(dat): - global CAPTURED_STATE - - ptr = 0 - while ptr < len(dat): - cmd = struct.unpack("I", dat[ptr:ptr+4])[0] - if (cmd>>24) == 0x70: - # packet with opcode and opcode specific payload (replace pkt3 starting with a5xx) - opcode, size = ((cmd>>16)&0x7F), cmd&0x3FFF - vals = struct.unpack("I"*size, dat[ptr+4:ptr+4+4*size]) - if IOCTL > 0: print(f"{ptr:3X} -- typ 7: {size=:3d}, {opcode=:#x} {ops[opcode]}", hprint(vals)) - if ops[opcode] == "CP_LOAD_STATE6_FRAG": # for compute shaders CP_LOAD_STATE6_FRAG is used - dst_off = vals[0] & 0x3FFF - state_type = (vals[0]>>14) & 0x3 - state_src = (vals[0]>>16) & 0x3 - state_block = (vals[0]>>18) & 0xF # 13 = SB4_CS_SHADER - num_unit = vals[0]>>22 - if IOCTL > 0: print(f"{num_unit=} {state_block=} {state_src=} {state_type=} {dst_off=}") - - if "LOAD_FRAGS" not in CAPTURED_STATE: CAPTURED_STATE['LOAD_FRAGS'] = [] - CAPTURED_STATE['LOAD_FRAGS'].append((state_block, state_type, num_unit, dst_off)) - - if state_block == SB6_CS_SHADER: - from extra.disassemblers.adreno import disasm_raw - if state_type == ST6_SHADER and IOCTL > 2: - disasm_raw(get_mem(((vals[2] << 32) | vals[1]), num_unit * 128)) - if state_type == ST6_CONSTANTS: - x = get_mem(((vals[2] << 32) | vals[1]), num_unit*4) - CAPTURED_STATE['constants'] = x[:] - if IOCTL > 2: - print('constants') - hexdump(x) - if state_type == ST6_IBO: - ibos_bytes = get_mem((vals[2] << 32) | vals[1], num_unit * 16 * 4) - CAPTURED_STATE['ibos'] = ibos_bytes[:] - if IOCTL > 1: - print('texture ibos') - hexdump(ibos_bytes) - elif state_block == SB6_CS_TEX: - if state_type == ST6_SHADER: - samplers_bytes = get_mem((vals[2] << 32) | vals[1], num_unit * 4 * 4) - CAPTURED_STATE['samplers'] = samplers_bytes[:] - if IOCTL > 1: - print('texture samplers') - hexdump(samplers_bytes) - if state_type == ST6_CONSTANTS: - descriptors_bytes = get_mem((vals[2] << 32) | vals[1], 1600) - CAPTURED_STATE['descriptors'] = descriptors_bytes[:] - if IOCTL > 1: - print('texture descriptors') - hexdump(descriptors_bytes) - - elif ops[opcode] == "CP_REG_TO_MEM": - reg, cnt, b64, accum = vals[0] & 0x3FFFF, (vals[0] >> 18) & 0xFFF, (vals[0] >> 30) & 0x1, (vals[0] >> 31) & 0x1 - dest = vals[1] | (vals[2] << 32) - if IOCTL > 0: print(f"{reg=} {cnt=} {b64=} {accum=} {dest=:#x}") - ptr += 4*size - elif (cmd>>28) == 0x4: - # write one or more registers (replace pkt0 starting with a5xx) - offset, size = ((cmd>>8)&0x7FFFF), cmd&0x7F - reg_name = REGS.get(offset, f"reg {offset=:#x}") - vals = struct.unpack("I"*size, dat[ptr+4:ptr+4+4*size]) - if IOCTL > 0: print(f"{ptr:3X} -- typ 4: {size=:3d}, {reg_name}", hprint(vals)) - for vi,v in enumerate(vals): CAPTURED_STATE[offset+vi] = v - if offset == adreno.REG_A6XX_SP_CS_CONFIG: - val = vals[0] - if IOCTL > 0: - print(f"\tBINDLESS_TEX={(val >> 0) & 0b1}") - print(f"\tBINDLESS_SAMP={(val >> 1) & 0b1}") - print(f"\tBINDLESS_IBO={(val >> 2) & 0b1}") - print(f"\tBINDLESS_UBO={(val >> 3) & 0b1}") - print(f"\tEN={(val >> 8) & 0b1}") - print(f"\tNTEX={(val >> 9) & 0b11111111}") - print(f"\tNSAMP={(val >> 17) & 0b11111}") - print(f"\tNIBO={(val >> 22) & 0b1111111}") - if offset == 0xa9b0: - if IOCTL > 0: - print(f'THREADSIZE-{(vals[0] >> 20)&0x1}\nEARLYPREAMBLE-{(vals[0] >> 23) & 0x1}\nMERGEDREGS-{(vals[0] >> 3) & 0x1}\nTHREADMODE-{vals[0] & 0x1}\nHALFREGFOOTPRINT-{(vals[0] >> 1) & 0x3f}\nFULLREGFOOTPRINT-{(vals[0] >> 7) & 0x3f}\nBRANCHSTACK-{(vals[0] >> 14) & 0x3f}\n') - print(f'SP_CS_UNKNOWN_A9B1-{vals[1]}\nSP_CS_BRANCH_COND-{vals[2]}\nSP_CS_OBJ_FIRST_EXEC_OFFSET-{vals[3]}\nSP_CS_OBJ_START-{vals[4] | (vals[5] << 32)}\nSP_CS_PVT_MEM_PARAM-{vals[6]}\nSP_CS_PVT_MEM_ADDR-{vals[7] | (vals[8] << 32)}\nSP_CS_PVT_MEM_SIZE-{vals[9]}') - if offset == 0xb180: - if IOCTL > 0: - print('border color offset', hex(vals[1] << 32 | vals[0])) - hexdump(get_mem(vals[1] << 32 | vals[0], 0x200)) - ptr += 4*size - else: - if IOCTL > 0: - print("unk", hex(cmd)) - ptr += 4 - -@ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_ulong, ctypes.c_void_p) -def ioctl(fd, request, argp): - ret = libc.syscall(0x1d, ctypes.c_int(fd), ctypes.c_ulong(request), ctypes.c_void_p(argp)) - - idir, size, itype, nr = (request>>30), (request>>16)&0x3FFF, (request>>8)&0xFF, request&0xFF - if nr in nrs and itype == 9: - name, stype = nrs[nr] - s = get_struct(argp, stype) - if IOCTL > 0: print(f"{ret:2d} = {name:40s}", ' '.join(format_struct(s))) - if name == "IOCTL_KGSL_GPUOBJ_INFO": pass - # mmaped[s.gpuaddr] = mmap.mmap(fd, s.size, offset=s.id*0x1000) - if name == "IOCTL_KGSL_GPU_COMMAND": - for i in range(s.numcmds): - cmd = get_struct(s.cmdlist+ctypes.sizeof(msm_kgsl.struct_kgsl_command_object)*i, msm_kgsl.struct_kgsl_command_object) - if IOCTL > 0: print(f"cmd {i}:", format_struct(cmd)) - parse_cmd_buf(get_mem(cmd.gpuaddr, cmd.size)) - for i in range(s.numobjs): - obj = get_struct(s.objlist+s.objsize*i, msm_kgsl.struct_kgsl_command_object) - if IOCTL > 0: - print(f"obj {i}:", format_struct(obj)) - print(format_struct(msm_kgsl.struct_kgsl_cmdbatch_profiling_buffer.from_buffer_copy(get_mem(obj.gpuaddr, obj.size)))) - #hexdump(get_mem(obj.gpuaddr, obj.size)) - else: - #print(f"ioctl({fd=}, (dir:{idir}, size:0x{size:3X}, type:{itype:d}, nr:0x{nr:2X}), {argp=:X}) = {ret=}") - pass - - return ret - -def install_hook(c_function, python_function): - # AARCH64 trampoline to ioctl - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value) - - # get real ioctl address - ioctl_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - - # hook ioctl - libc = ctypes.CDLL(ctypes.util.find_library("libc")) - ret = libc.mprotect(ctypes.c_ulong((ioctl_address.contents.value//0x1000)*0x1000), 0x2000, 7) - assert ret == 0 - libc.memcpy(ioctl_address.contents, ctypes.create_string_buffer(tramp), len(tramp)) - -libc = ctypes.CDLL(ctypes.util.find_library("libc")) -install_hook(libc.ioctl, ioctl) - -def before_launch(): - global CAPTURED_STATE - CAPTURED_STATE.clear() -def collect_last_launch_state(): - global CAPTURED_STATE - return deepcopy(CAPTURED_STATE) -def compare_launch_state(state, good_state): - cmp = [ - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_NTEX__MASK), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_NSAMP__MASK), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_NIBO__MASK), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_ENABLED), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_BINDLESS_TEX), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_BINDLESS_SAMP), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_BINDLESS_IBO), - (adreno.REG_A6XX_SP_CS_CONFIG, adreno.A6XX_SP_CS_CONFIG_BINDLESS_UBO), - - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE), - (adreno.REG_A6XX_SP_CS_CTRL_REG0, adreno.A6XX_SP_CS_CTRL_REG0_MERGEDREGS), - - (adreno.REG_A6XX_SP_CS_PVT_MEM_PARAM, adreno.A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK), - (adreno.REG_A6XX_SP_CS_PVT_MEM_PARAM, adreno.A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK), - - (adreno.REG_A6XX_SP_CS_UNKNOWN_A9B1, adreno.A6XX_SP_CS_UNKNOWN_A9B1_UNK5), - (adreno.REG_A6XX_SP_CS_UNKNOWN_A9B1, adreno.A6XX_SP_CS_UNKNOWN_A9B1_UNK6), - - (adreno.REG_A6XX_SP_CS_BRANCH_COND, 0xffffffff), - - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, adreno.A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, adreno.A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, adreno.A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, adreno.A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK), - - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_1, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_2, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_3, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_4, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_5, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_NDRANGE_6, 0xffffffff), - - (adreno.REG_A6XX_HLSQ_CS_CNTL_0, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_CNTL_1, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y, 0xffffffff), - (adreno.REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z, 0xffffffff), - ] - - for x,m in cmp: - print(f"Field {REGS[x]}, mask: 0x{m:X} cmp: {state.get(x, 0) & m} vs {good_state.get(x, 0) & m}") - if state.get(x, 0) & m != good_state.get(x, 0) & m: - return False, f"Field {REGS[x]}, mask: 0x{m:X} mismatch: {state.get(x, 0) & m} vs {good_state.get(x, 0) & m}" - - for n in ['descriptors', 'ibos']: - if n not in good_state: continue - mv1, mv2 = state.get(n), good_state.get(n) - - if len(mv1) != len(mv2): return False, f"{n}: len mismatch {len(mv1)} != {len(mv2)}" - mv1 = memoryview(bytearray(mv1)).cast('I') - mv2 = memoryview(bytearray(mv2)).cast('I') - for i in range(len(mv2)): - if i % 8 == 5 or i % 8 == 4: continue # addresses - if mv1[i]!=mv2[i]: return False, f"{n}: content mismatch {i} {mv1[i]} {mv2[i]}" - - for n in ['samplers']: - if n not in good_state: continue - mv1, mv2 = state.get(n), good_state.get(n) - if len(mv1) != len(mv2): return False, f"{n}: len mismatch {len(mv1)} != {len(mv2)}" - if any(mv1[i]!=mv2[i] for i in range(len(mv1))): return False, f"{n}: content mismatch" - - return True, "PASS" diff --git a/tinygrad/extra/qcom_gpu_driver/qcom_opencl_interop.py b/tinygrad/extra/qcom_gpu_driver/qcom_opencl_interop.py deleted file mode 100644 index d595ba34..00000000 --- a/tinygrad/extra/qcom_gpu_driver/qcom_opencl_interop.py +++ /dev/null @@ -1,87 +0,0 @@ -import ctypes, array -from hexdump import hexdump -from tinygrad.runtime.ops_gpu import GPUDevice -from tinygrad.helpers import getenv, to_mv, mv_address -from tinygrad.dtype import dtypes -from tinygrad import Tensor, TinyJit -from tinygrad.runtime.autogen import opencl as cl -if getenv("IOCTL"): import extra.qcom_gpu_driver.opencl_ioctl # noqa: F401 # pylint: disable=unused-import - -# create raw opencl buffer. -gdev = GPUDevice() -cl_buf = cl.clCreateBuffer(gdev.context, cl.CL_MEM_READ_WRITE, 0x100, None, status := ctypes.c_int32()) -assert status.value == 0 - -# fill it with something for fun -data = memoryview(array.array('I', [i for i in range(64)])) -cl.clEnqueueWriteBuffer(gdev.queue, cl_buf, False, 0, 0x100, mv_address(data), 0, None, None) -cl.clFinish(gdev.queue) # wait writes to complete - -# get raw gpu pointer from opencl buffer. - -## get buf desc -hexdump(to_mv(ctypes.addressof(cl_buf), 0x40)) -cl_buf_desc_ptr = to_mv(ctypes.addressof(cl_buf), 8).cast('Q')[0] - -## get buf device ptr -hexdump(to_mv(cl_buf_desc_ptr, 0x100)) -rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] # offset 0xA0 is a raw gpu pointer. - -# create QCOM tensor with the externally managed buffer -x = Tensor.from_blob(rawbuf_ptr, (8, 8), dtype=dtypes.int, device='QCOM') -y = (x + 1).numpy() -print(y) - -# all calculations are done, save to free the object -cl.clReleaseMemObject(cl_buf) - -# all together with jit -@TinyJit -def calc(x): return x + 2 - -for i in range(4): - cl_buf = cl.clCreateBuffer(gdev.context, cl.CL_MEM_READ_WRITE, 2*2*4, None, status := ctypes.c_int32()) - assert status.value == 0 - data = memoryview(array.array('I', [x+i for x in range(2*2)])) - cl.clEnqueueWriteBuffer(gdev.queue, cl_buf, False, 0, 2*2*4, mv_address(data), 0, None, None) - cl.clFinish(gdev.queue) # wait writes to complete - - cl_buf_desc_ptr = to_mv(ctypes.addressof(cl_buf), 8).cast('Q')[0] - rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] - - y = calc(x = Tensor.from_blob(rawbuf_ptr, (2, 2), dtype=dtypes.int, device='QCOM')).numpy() - print(f'jit {i}\n', y) - - # all calculations are done, save to free the object - cl.clReleaseMemObject(cl_buf) - -# now images! - -h, w = 128, 128 -cl_img = cl.clCreateImage2D(gdev.context, cl.CL_MEM_READ_WRITE, cl.cl_image_format(cl.CL_RGBA, cl.CL_FLOAT), w, h, 0, None, status := ctypes.c_int32()) -assert status.value == 0 - -# fill it with something for fun -data = memoryview(array.array('f', [i for i in range(h*w*4)])) -cl.clEnqueueWriteImage(gdev.queue, cl_img, False, (ctypes.c_size_t * 3)(0,0,0), (ctypes.c_size_t * 3)(w,h,1), 0, 0, mv_address(data), 0, None, None) -cl.clFinish(gdev.queue) # wait writes to complete - -# get raw gpu pointer from opencl buffer. - -## get buf desc -hexdump(to_mv(ctypes.addressof(cl_img), 0x40)) -cl_buf_desc_ptr = to_mv(ctypes.addressof(cl_img), 8).cast('Q')[0] - -## get buf device ptr -hexdump(to_mv(cl_buf_desc_ptr, 0x100)) -rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] # offset 0xA0 is a raw gpu pointer. - -# create QCOM tensor with the externally managed buffer -# dtypes.imageh = cl.cl_image_format(cl.CL_RGBA, cl.CL_HALF_FLOAT) -# dtypes.imagef = cl.cl_image_format(cl.CL_RGBA, cl.CL_FLOAT) -x = Tensor.from_blob(rawbuf_ptr, (h*w*4,), dtype=dtypes.imagef((h,w)), device='QCOM') -y = (x + 1).numpy() -print(y) - -# all calculations are done, save to free the object -cl.clReleaseMemObject(cl_img) diff --git a/tinygrad/extra/reduce_speed.py b/tinygrad/extra/reduce_speed.py deleted file mode 100644 index 36bd0d3d..00000000 --- a/tinygrad/extra/reduce_speed.py +++ /dev/null @@ -1,128 +0,0 @@ -import numpy as np -import ctypes -from tinygrad import Tensor, GlobalCounters, Context -from tinygrad.engine.realize import lower_schedule, CompiledRunner -from tinygrad.device import CPUProgram -from dataclasses import replace -from keystone import Ks, KS_ARCH_ARM64, KS_MODE_LITTLE_ENDIAN - -# only the memory access, over 100 GB/s! (sometimes) -reduce_asm = """ -movi v0.2d, #0000000000000000 -mov w9, #0x30 -mov w10, #0x20 -mov x8, #-0x10 -movi v1.2d, #0000000000000000 -movk w9, #0x300, lsl #16 -movi v2.2d, #0000000000000000 -movk w10, #0x200, lsl #16 -movi v3.2d, #0000000000000000 -mov w11, #0x1000000 -mov w12, #0x3ffff0 -loop: -ldp q4, q5, [x1] -add x13, x1, x11 -add x15, x1, x10 -add x14, x1, x9 -add x8, x8, #0x10 -cmp x8, x12 -ldp q6, q7, [x1, #0x20] -add x1, x1, #0x40 -ldp q4, q5, [x13] -ldp q6, q7, [x13, #0x20] -ldp q4, q5, [x15, #-0x20] -ldp q6, q7, [x15] -ldp q4, q5, [x14, #-0x30] -ldp q6, q7, [x14, #-0x10] -b.lo loop -fadd v0.4s, v1.4s, v0.4s -fadd v0.4s, v2.4s, v0.4s -fadd v0.4s, v3.4s, v0.4s -dup v1.4s, v0.s[1] -dup v2.4s, v0.s[2] -fadd v1.4s, v0.4s, v1.4s -dup v0.4s, v0.s[3] -fadd v1.4s, v2.4s, v1.4s -fadd v0.4s, v0.4s, v1.4s -str s0, [x0] -ret -""" - -ks = Ks(KS_ARCH_ARM64, KS_MODE_LITTLE_ENDIAN) -arm_bytecode, _ = ks.asm(reduce_asm) -arm_bytecode = bytes(arm_bytecode) - -reduce_src = """ -// data1 is 16M inputs -typedef float float4 __attribute__((aligned(32),vector_size(16))); -void reduce(float* restrict data0, float* restrict data1) { - float4 acc0 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc1 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc2 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc3 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc4 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc5 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc6 = {0.0f, 0.0f, 0.0f, 0.0f}; - float4 acc7 = {0.0f, 0.0f, 0.0f, 0.0f}; - float* data1_1 = data1+4194304; - float* data1_2 = data1+(4194304*2); - float* data1_3 = data1+(4194304*3); - for (int ridx0 = 0; ridx0 < 16777216/4; ridx0+=16) { - float4 val0 = *(float4*)((data1+(ridx0+0))); - float4 val1 = *(float4*)((data1+(ridx0+4))); - float4 val2 = *(float4*)((data1+(ridx0+8))); - float4 val3 = *(float4*)((data1+(ridx0+12))); - acc0 += val0; - acc1 += val1; - acc2 += val2; - acc3 += val3; - val0 = *(float4*)((data1_1+(ridx0+0))); - val1 = *(float4*)((data1_1+(ridx0+4))); - val2 = *(float4*)((data1_1+(ridx0+8))); - val3 = *(float4*)((data1_1+(ridx0+12))); - acc4 += val0; - acc5 += val1; - acc6 += val2; - acc7 += val3; - val0 = *(float4*)((data1_2+(ridx0+0))); - val1 = *(float4*)((data1_2+(ridx0+4))); - val2 = *(float4*)((data1_2+(ridx0+8))); - val3 = *(float4*)((data1_2+(ridx0+12))); - acc0 += val0; - acc1 += val1; - acc2 += val2; - acc3 += val3; - val0 = *(float4*)((data1_3+(ridx0+0))); - val1 = *(float4*)((data1_3+(ridx0+4))); - val2 = *(float4*)((data1_3+(ridx0+8))); - val3 = *(float4*)((data1_3+(ridx0+12))); - acc4 += val0; - acc5 += val1; - acc6 += val2; - acc7 += val3; - } - float4 out = acc0+acc1+acc2+acc3+acc4+acc5+acc6+acc7; - *(data0+0) = out[0]+out[1]+out[2]+out[3]; -} -""" - -if __name__ == "__main__": - a = Tensor(np_array:=(np.random.default_rng().random((4096, 4096), dtype=np.float32)-0.5)).realize() - with Context(SPLIT_REDUCEOP=0): - # TODO: make it easy to alter the OptOps for a ScheduleItem - GlobalCounters.reset() - out = a.sum() - sis = out.schedule() - for i,(_,ei) in enumerate(lower_schedule(sis)): - if i == 0: - # change the source code - prg_spec = ei.prg.p - prg_spec = replace(prg_spec, name="reduce", src=reduce_src) - prg = CompiledRunner(prg_spec) - # change the assembly - #prg._prg = CPUProgram(prg_spec.name, arm_bytecode) - print("buffer at:",hex(ctypes.addressof(ei.bufs[1]._buf))) - ei = replace(ei, prg=prg) - ei.run() - print(out.item()) - np.testing.assert_allclose(out.item(), np_array.sum(), atol=1, rtol=1e-4) diff --git a/tinygrad/extra/remu/Cargo.lock b/tinygrad/extra/remu/Cargo.lock deleted file mode 100644 index da9b2bf6..00000000 --- a/tinygrad/extra/remu/Cargo.lock +++ /dev/null @@ -1,66 +0,0 @@ -# This file is automatically @generated by Cargo. -# It is not intended for manual editing. -version = 4 - -[[package]] -name = "autocfg" -version = "1.1.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" - -[[package]] -name = "cfg-if" -version = "1.0.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" - -[[package]] -name = "crunchy" -version = "0.2.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7a81dae078cea95a014a339291cec439d2f232ebe854a9d672b796c6afafa9b7" - -[[package]] -name = "float-cmp" -version = "0.9.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "98de4bbd547a563b716d8dfa9aad1cb19bfab00f4fa09a6a4ed21dbcf44ce9c4" -dependencies = [ - "num-traits", -] - -[[package]] -name = "half" -version = "2.3.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bc52e53916c08643f1b56ec082790d1e86a32e58dc5268f897f313fbae7b4872" -dependencies = [ - "cfg-if", - "crunchy", - "num-traits", -] - -[[package]] -name = "libm" -version = "0.2.8" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4ec2a862134d2a7d32d7983ddcdd1c4923530833c9f2ea1a44fc5fa473989058" - -[[package]] -name = "num-traits" -version = "0.2.17" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "39e3200413f237f41ab11ad6d161bc7239c84dcb631773ccd7de3dfe4b5c267c" -dependencies = [ - "autocfg", - "libm", -] - -[[package]] -name = "remu" -version = "0.1.0" -dependencies = [ - "float-cmp", - "half", - "num-traits", -] diff --git a/tinygrad/extra/remu/Cargo.toml b/tinygrad/extra/remu/Cargo.toml deleted file mode 100644 index 85b4e244..00000000 --- a/tinygrad/extra/remu/Cargo.toml +++ /dev/null @@ -1,15 +0,0 @@ -[package] -name = "remu" -version = "0.1.0" -edition = "2021" -rust-version = "1.80.0" - -[lib] -crate-type = ["cdylib"] - -[dependencies] -half = { version = "2.3.1", features = ["num-traits"] } -num-traits = "0.2.17" - -[dev-dependencies] -float-cmp = "0.9.0" diff --git a/tinygrad/extra/remu/README.md b/tinygrad/extra/remu/README.md deleted file mode 100644 index 3746ea07..00000000 --- a/tinygrad/extra/remu/README.md +++ /dev/null @@ -1,80 +0,0 @@ -## Intro - -Remu is an RDNA3 emulator built to test correctness of RDNA3 code. It is used in [tinygrad's AMD CI](https://github.com/tinygrad/tinygrad). - -Most of the common instructions are implemented, but some formats like IMG are not supported. - -Remu is only for testing correctness of program output, it is not a cycle accurate simulator. - -## Build Locally - -Remu is written in Rust. Make sure you have [Cargo](https://doc.rust-lang.org/cargo/getting-started/installation.html). - -To build the project, run: - -```bash -cargo build --release --manifest-path ./extra/remu/Cargo.toml -``` - -This will produce a binary in the `extra/remu/target/release` directory. - -## Usage with tinygrad - -The latest binaries are released in https://github.com/Qazalin/remu/releases. Alternatively, you can [build locally](#build-locally). - -Tinygrad does not yet output RDNA3 kernels directly. You can either install comgr or use `AMD_LLVM=1` if you have [LLVM@19](https://github.com/tinygrad/tinygrad/blob/e2ed673c946c8f1774d816c75e52a994c2dd8a88/.github/actions/setup-tinygrad/action.yml#L208). - -`PYTHONPATH="." MOCKGPU=1 AMD=1 python test/test_tiny.py TestTiny.test_plus` runs an emulated RDNA3 kernel with Remu. - -Add `DEBUG=6` to see Remu's logs. - -### DEBUG output - -Remu runs each thread one at a time in a nested for loop, see lib.rs. The DEBUG output prints information about the current thread. - -The DEBUG output has 3 sections: - -``` -<------------ 1 ----------> <--- 2 ---> <--------------------------------------- 3 ------------------------------------------> -[0 0 0 ] [0 0 0 ] 0 F4080100 SMEM { op: 2, sdata: 4, sbase: 0, offset: 0, soffset: 124, glc: false, dlc: false } -``` - -#### Section 1: Grid info - -`[gid.x, gid.y, gid.z], [lid.x, lid.y, lid.z]` of the current thread. - -#### Section 2: Wave info - -` ` - -RDNA3 divides threads into chunks of 32. Each thread is assigned to a "lane" from 0-31. - -In Remu, even though all threads run one at a time, each 32 thread chunk (a wave) shares state like SGPR, VGPR, LDS, EXEC mask, etc. -Remu can simulate up to one wave sync instruction. -For more details, see work_group.rs. - -Section 2 can have a green or gray color. - -Green = The thread is actively executing the instruction. - -Gray = The thread has been "turned off" by the EXEC mask, it skips execution of some instructions. (refer to "EXECute Mask" on [page 23](https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna3-shader-instruction-set-architecture-feb-2023_0.pdf#page=23) of ISA docs for more details.) - -To see the colors in action, try running `DEBUG=6 PYTHONPATH="." MOCKGPU=1 AMD=1 python test/test_ops.py TestOps.test_arange_big`. See how only lane 0 writes to global memory: -``` -[255 0 0 ] [0 0 0 ] 0 DC6A0000 FLAT { op: 26, offset: 0, dlc: false, glc: false, slc: false, seg: 2, addr: 8, data: 0, saddr: 0, sve: false, vdst: 0 } -[255 0 0 ] [1 0 0 ] 1 DC6A0000 -[255 0 0 ] [2 0 0 ] 2 DC6A0000 -[255 0 0 ] [3 0 0 ] 3 DC6A0000 -[255 0 0 ] [3 0 0 ] 4 DC6A0000 -``` - -#### Section 3: Decoded Instruction - -This prints the instruction type and all the parsed bitfields. - -Remu output vs llvm-objdump: - -``` -s_load_b64 s[0:1], s[0:1], 0x10 // 00000000160C: F4040000 F8000010 -SMEM { op: 1, sdata: 0, sbase: 0, offset: 16, soffset: 124, glc: false, dlc: false } -``` diff --git a/tinygrad/extra/remu/rustfmt.toml b/tinygrad/extra/remu/rustfmt.toml deleted file mode 100644 index bc30bf42..00000000 --- a/tinygrad/extra/remu/rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -max_width = 150 diff --git a/tinygrad/extra/remu/src/helpers.rs b/tinygrad/extra/remu/src/helpers.rs deleted file mode 100644 index 09deca32..00000000 --- a/tinygrad/extra/remu/src/helpers.rs +++ /dev/null @@ -1,156 +0,0 @@ -use half::f16; -use num_traits::{float::FloatCore, PrimInt, Unsigned}; - -pub fn bits(word: T, hi: usize, lo: usize) -> T where T: PrimInt + Unsigned { - assert!(hi >= lo); - let width = hi - lo + 1; - (word >> lo) & ((T::one() << width) - T::one()) -} - -pub fn nth(val: u32, pos: usize) -> u32 { - (val >> (31 - pos as u32)) & 1 -} -pub fn f16_lo(val: u32) -> f16 { - f16::from_bits((val & 0xffff) as u16) -} -pub fn f16_hi(val: u32) -> f16 { - f16::from_bits(((val >> 16) & 0xffff) as u16) -} - -pub fn sign_ext(num: u64, bits: usize) -> i64 { - let mut value = num; - let is_negative = (value >> (bits - 1)) & 1 != 0; - if is_negative { - value |= !0 << bits; - } - value as i64 -} - -pub trait IEEEClass { - fn exponent(&self) -> T; -} -impl IEEEClass for f32 { - fn exponent(&self) -> u32 { - (self.to_bits() & 0b01111111100000000000000000000000) >> 23 - } -} -impl IEEEClass for f16 { - fn exponent(&self) -> u16 { - (self.to_bits() & 0b0111110000000000) >> 10 - } -} -impl IEEEClass for f64 { - fn exponent(&self) -> u64 { - (self.to_bits() & 0b0111111111110000000000000000000000000000000000000000000000000000) >> 52 - } -} - -pub trait VOPModifier { - fn negate(&self, pos: usize, modifier: usize) -> T; - fn absolute(&self, pos: usize, modifier: usize) -> T; -} -impl VOPModifier for T -where - T: FloatCore, -{ - fn negate(&self, pos: usize, modifier: usize) -> T { - match (modifier >> pos) & 1 { - 1 => -*self, - _ => *self, - } - } - fn absolute(&self, pos: usize, modifier: usize) -> T { - match (modifier >> pos) & 1 { - 1 => self.abs(), - _ => *self, - } - } -} - -pub fn extract_mantissa(x: f64) -> f64 { - if x.is_infinite() || x.is_nan() { - return x; - } - let bits = x.to_bits(); - let mantissa_mask: u64 = 0x000FFFFFFFFFFFFF; - let bias: u64 = 1023; - let normalized_mantissa_bits = (bits & mantissa_mask) | ((bias - 1) << 52); - return f64::from_bits(normalized_mantissa_bits); -} -pub fn ldexp(x: f64, exp: i32) -> f64 { - x * 2f64.powi(exp) -} - -#[cfg(test)] -mod tests { - use super::*; - #[test] - fn test_extract_mantissa() { - assert_eq!(extract_mantissa(2.0f64), 0.5); - } - - #[test] - fn test_normal_exponent() { - assert_eq!(2.5f32.exponent(), 128); - assert_eq!(1.17549435e-38f32.exponent(), 1); - assert_eq!(f32::INFINITY.exponent(), 255); - assert_eq!(f32::NEG_INFINITY.exponent(), 255); - } - - #[test] - fn test_denormal_exponent() { - assert_eq!(1.0e-40f32.exponent(), 0); - assert_eq!(1.0e-42f32.exponent(), 0); - assert_eq!(1.0e-44f32.exponent(), 0); - assert_eq!((1.17549435e-38f32 / 2.0).exponent(), 0); - } - - #[test] - fn test_normal_exponent_f16() { - assert_eq!(f16::from_f32(3.14f32).exponent(), 16); - assert_eq!(f16::NEG_INFINITY.exponent(), 31); - assert_eq!(f16::INFINITY.exponent(), 31); - } - - #[test] - fn test_neg() { - assert_eq!(0.3_f32.negate(0, 0b001), -0.3_f32); - assert_eq!(0.3_f32.negate(1, 0b010), -0.3_f32); - assert_eq!(0.3_f32.negate(2, 0b100), -0.3_f32); - assert_eq!(0.3_f32.negate(0, 0b110), 0.3_f32); - assert_eq!(0.3_f32.negate(1, 0b010), -0.3_f32); - assert_eq!(0.0_f32.negate(0, 0b001).to_bits(), (-0.0f32).to_bits()); - assert_eq!((-0.0_f32).negate(0, 0b001).to_bits(), 0); - } - - #[test] - fn test_sign_ext() { - assert_eq!(sign_ext(0b000000000000000101000, 21), 40); - assert_eq!(sign_ext(0b111111111111111011000, 21), -40); - assert_eq!(sign_ext(0b000000000000000000000, 21), 0); - assert_eq!(sign_ext(0b111111111111111111111, 21), -1); - assert_eq!(sign_ext(0b111000000000000000000, 21), -262144); - assert_eq!(sign_ext(0b000111111111111111111, 21), 262143); - assert_eq!(sign_ext(7608, 13), -584); - } -} - -use std::sync::LazyLock; -pub static DEBUG: LazyLock = LazyLock::new(|| std::env::var("DEBUG").map(|v| v.parse::().unwrap_or(0) >= 6).unwrap_or(false)); - -pub fn colored(st:&str, color:&str) -> String { - let ansi_code = match color { - "green" => format!("\x1b[{};2;39;176;139m", 38), - "gray" => format!("\x1b[{};2;169;169;169m", 38), - _ => format!("\x1b[{};2;255;255;255m", 38), - }; - format!("{}{}{}", ansi_code, st, "\x1b[0m") -} - -#[macro_export] -macro_rules! todo_instr { - ($x:expr) => {{ - println!("{:08X}", $x); - Err(1) - }}; -} diff --git a/tinygrad/extra/remu/src/lib.rs b/tinygrad/extra/remu/src/lib.rs deleted file mode 100644 index 74b972bf..00000000 --- a/tinygrad/extra/remu/src/lib.rs +++ /dev/null @@ -1,32 +0,0 @@ -use crate::work_group::WorkGroup; -use std::os::raw::c_char; -use std::slice; -mod helpers; -mod rdna3; -mod state; -mod thread; -mod work_group; - -#[no_mangle] -pub extern "C" fn run_asm(lib: *const c_char, lib_sz: u32, gx: u32, gy: u32, gz: u32, lx: u32, ly: u32, lz: u32, args_ptr: *const u64) -> i32 { - if lib.is_null() || (lib_sz % 4) != 0 { - panic!("Pointer is null or length is not properly aligned to 4 bytes"); - } - let kernel = unsafe { slice::from_raw_parts(lib as *const u32, (lib_sz / 4) as usize).to_vec() }; - let dispatch_dim = match (gy != 1, gz != 1) { - (true, true) => 3, - (true, false) => 2, - _ => 1, - }; - for gx in 0..gx { - for gy in 0..gy { - for gz in 0..gz { - let mut wg = WorkGroup::new(dispatch_dim, [gx, gy, gz], [lx, ly, lz], &kernel, args_ptr); - if let Err(err) = wg.exec_waves() { - return err; - } - } - } - } - 0 -} diff --git a/tinygrad/extra/remu/src/rdna3.rs b/tinygrad/extra/remu/src/rdna3.rs deleted file mode 100644 index 83ce61e3..00000000 --- a/tinygrad/extra/remu/src/rdna3.rs +++ /dev/null @@ -1,223 +0,0 @@ -use crate::helpers::{bits, sign_ext}; - -#[derive(Debug, PartialEq)] -pub enum Instruction { - SOP2 { op: u8, ssrc0: u8, ssrc1: u8, sdst: u8 }, - SOP1 { op: u8, ssrc0: u8, sdst: u8 }, - SOPK { op: u8, simm16: i16, sdst: u8 }, - SOPP { op: u8, simm16: i16 }, - SOPC { op: u8, ssrc0: u8, ssrc1: u8 }, - - SMEM { op: u8, sdata: u8, sbase: u8, offset: i32, soffset: u8, glc: bool, dlc: bool }, - - VOP1 { op: u8, vdst: u8, src: u16 }, - VOP2 { op: u8, vdst: u8, vsrc: u8, src: u16 }, - VOPC { op: u8, vsrc: u8, src: u16 }, - VOP3 { op: u32, opsel: u8, cm: bool, abs: u8, vdst: u8, neg: u8, omod: u8, src2: u16, src1: u16, src0: u16 }, - VOP3SD { op: u32, cm: bool, sdst: u8, vdst: u8, neg: u8, omod: u8, src2: u16, src1: u16, src0: u16 }, - VOP3P { op: u8, vdst: u8, neg_hi: u8, opsel: u8, opsel_hi: u8, opsel_hi2: bool, cm: bool, src2: u16, src1: u16, src0: u16, neg: u8 }, - VOPD { opx: u8, opy: u8, vdstx: u8, vdsty: u8, vsrcx1: u8, vsrcy1: u8, srcx0: u16, srcy0: u16 }, - - DS { op: u8, gds: bool, offset1: u8, offset0: u8, vdst: u8, data1: u8, data0: u8, addr: u8 }, - - FLAT { op: u8, offset: u16, dlc: bool, glc: bool, slc: bool, seg: u8, addr: u8, data: u8, saddr: u8, sve: bool, vdst: u8 } -} - -const VOP3SD_OPS: [u32; 7] = [764, 765, 766, 767, 768, 769, 770]; - -pub fn decode(word:u32, word1:Option<&u32>) -> Instruction { - match bits(word, 31, 30) { - 0b11 => { - let word = (*word1.unwrap() as u64) << 32 | (word as u64); - match bits(word, 29, 26) { - 0b1101 => { - let sbase = (bits(word, 5, 0) as u8) << 1; - let sdata = bits(word, 12, 6) as u8; - let dlc = bits(word, 13, 13) != 0; - let glc = bits(word, 14, 14) != 0; - let op = bits(word, 25, 18) as u8; - let offset = sign_ext(bits(word, 52, 32), 21) as i32; - let soffset = bits(word, 63, 57) as u8; - Instruction::SMEM { sbase, sdata, dlc, glc, op, offset, soffset } - } - 0b0101 => { - let op = bits(word, 25, 16) as u32; - let vdst = bits(word, 7, 0) as u8; - let cm = bits(word, 15, 15) != 0; - let src0 = bits(word, 40, 32) as u16; - let src1 = bits(word, 49, 41) as u16; - let src2 = bits(word, 58, 50) as u16; - let omod = bits(word, 60, 59) as u8; - let neg = bits(word, 63, 61) as u8; - if VOP3SD_OPS.contains(&op) { - let sdst = bits(word, 14, 8) as u8; - Instruction::VOP3SD { op, vdst, sdst, cm, src0, src1, src2, omod, neg } - } else { - let abs = bits(word, 10, 8) as u8; - let opsel = bits(word, 14, 11) as u8; - Instruction::VOP3 { opsel, cm, abs, vdst, neg, omod, src2, src1, src0, op } - } - } - 0b0011 => { - let op = bits(word, 22, 16) as u8; - let vdst = bits(word, 7, 0) as u8; - let neg_hi = bits(word, 10, 8) as u8; - let opsel = bits(word, 13, 11) as u8; - let opsel_hi2 = bits(word, 14, 14) != 0; - let cm = bits(word, 15, 15) != 0; - let src0 = bits(word, 40, 32) as u16; - let src1 = bits(word, 49, 41) as u16; - let src2 = bits(word, 58, 50) as u16; - let opsel_hi = bits(word, 60, 59) as u8; - let neg = bits(word, 63, 61) as u8; - Instruction::VOP3P { op, vdst, neg_hi, opsel, opsel_hi, opsel_hi2, cm, src0, src1, src2, neg } - } - 0b0110 => { - let offset0 = bits(word, 7, 0) as u8; - let offset1 = bits(word, 15, 8) as u8; - let gds = bits(word, 17, 17) != 0; - let op = bits(word, 25, 18) as u8; - let addr = bits(word, 39, 32) as u8; - let data0 = bits(word, 47, 40) as u8; - let data1 = bits(word, 55, 48) as u8; - let vdst = bits(word, 63, 56) as u8; - Instruction::DS { op, gds, offset1, offset0, vdst, data1, data0, addr } - } - 0b0111 => { - let offset = bits(word, 12, 0) as u16; - let dlc = bits(word, 13, 13) != 0; - let glc = bits(word, 14, 14) != 0; - let slc = bits(word, 15, 15) != 0; - let seg = bits(word, 17, 16) as u8; - let op = bits(word, 24, 18) as u8; - let addr = bits(word, 39, 32) as u8; - let data = bits(word, 47, 40) as u8; - let saddr = bits(word, 54, 48) as u8; - let sve = bits(word, 55, 55) != 0; - let vdst = bits(word, 63, 56) as u8; - Instruction::FLAT { offset, dlc, glc, slc, seg, op, addr, data, saddr, sve, vdst } - }, - 0b0010 => { - let srcx0 = bits(word, 8, 0) as u16; - let vsrcx1 = bits(word, 16, 9) as u8; - let opy = bits(word, 21, 17) as u8; - let opx = bits(word, 25, 22) as u8; - let srcy0 = bits(word, 40, 32) as u16; - let vsrcy1 = bits(word, 48, 41) as u8; - let vdsty = bits(word, 55, 49) as u8; - let vdstx = bits(word, 63, 56) as u8; - Instruction::VOPD { opx, opy, vdstx, vdsty, vsrcx1, vsrcy1, srcx0, srcy0 } - } - _ => todo!(), - } - } - 0b10 => { - let ssrc0 = bits(word, 7, 0) as u8; - let ssrc1 = bits(word, 15, 8) as u8; - let simm16 = word as i16; - let sdst = bits(word, 22, 16) as u8; - match bits(word, 29, 23) { - 0b1111101 => Instruction::SOP1 { ssrc0, sdst, op: bits(word, 15, 8) as u8 }, - 0b1111110 => Instruction::SOPC { ssrc0, ssrc1, op: bits(word, 22, 16) as u8 }, - 0b1111111 => Instruction::SOPP { simm16, op: bits(word, 22, 16) as u8 }, - _ => { - match bits(word, 29, 28) { - 0b11 => Instruction::SOPK { simm16, sdst, op: bits(word, 27, 23) as u8 }, - _ => Instruction::SOP2 { ssrc0, ssrc1, sdst, op: bits(word, 29, 23) as u8 } - } - } - } - } - _ => { - let vdst = bits(word, 24, 17) as u8; - let src = bits(word, 8, 0) as u16; - let vsrc = bits(word, 16, 9) as u8; - match bits(word, 30, 25) { - 0b111110 => Instruction::VOPC { vsrc, src, op: bits(word, 24, 17) as u8 }, - 0b111111 => Instruction::VOP1 { vdst, src, op: vsrc }, - _ => Instruction::VOP2 { vdst, vsrc, src, op: bits(word, 30, 25) as u8 }, - } - }, - } -} - -#[cfg(test)] -mod test_rdna3 { - use super::*; - - use std::process::{Stdio, Command}; - use std::io::{Result, Write}; - - const LLVM_ARGS: &[&str; 3] = &["--arch=amdgcn", "--mcpu=gfx1100", "--triple=amdgcn-amd-amdhsa"]; - const OFFSET_PRG: usize = 16; - const NULL: u8 = 124; - - fn llvm_assemble(asm: &str) -> Result> { - let mut proc = Command::new("llvm-mc").args(LLVM_ARGS).args(["-filetype=obj", "-o", "-"]).stdin(Stdio::piped()).stdout(Stdio::piped()).spawn()?; - proc.stdin.as_mut().unwrap().write_all(asm.as_bytes())?; - let out = proc.wait_with_output()?; - match out.status.success() { - true => Ok(out.stdout), - false => Err(std::io::Error::new(std::io::ErrorKind::Other, "llvm-mc err")), - } - } - - fn llvm_disassemble(code: &Vec) -> Result { - let mut proc = Command::new("llvm-objdump").args(LLVM_ARGS).args(["--disassemble", "-"]).stdin(Stdio::piped()).stdout(Stdio::piped()).spawn()?; - proc.stdin.as_mut().unwrap().write_all(code)?; - let out = proc.wait_with_output()?; - match out.status.success() { - true => Ok(String::from_utf8(out.stdout).unwrap()), - false => Err(std::io::Error::new(std::io::ErrorKind::Other, "llvm-objdump err")), - } - } - - fn test_decode(asm: &str) -> Instruction { - let lib = llvm_assemble(asm).unwrap(); - println!("{}", llvm_disassemble(&lib).unwrap()); - let stream: Vec = lib.chunks_exact(4).map(|chunk| u32::from_le_bytes(chunk.try_into().unwrap())).skip(OFFSET_PRG).collect(); - decode(stream[0], stream.get(1)) - } - - #[test] - fn test_decode_smem() { - assert_eq!(test_decode("s_load_b128 s[4:7], s[0:1], null"), Instruction::SMEM { op: 2, sdata: 4, sbase: 0, offset: 0, soffset: NULL, glc: false, dlc: false }); - assert_eq!(test_decode("s_load_b32 s10, s[0:1], 0xc"), Instruction::SMEM { op: 0, sdata: 10, sbase: 0, offset: 0xc, soffset: NULL, glc: false, dlc: false }); - assert_eq!(test_decode("s_load_b32 s0, s[4:5], s6"), Instruction::SMEM { op: 0, sdata: 0, sbase: 4, offset: 0, soffset: 6, glc: false, dlc: false }); - assert_eq!(test_decode("s_load_b32 s0, s[4:5], glc dlc"), Instruction::SMEM { op: 0, sdata: 0, sbase: 4, offset: 0, soffset: NULL, glc: true, dlc: true }); - assert_eq!(test_decode("s_load_b32 s0, s[4:5], glc"), Instruction::SMEM { op: 0, sdata: 0, sbase: 4, offset: 0, soffset: NULL, glc: true, dlc: false }); - assert_eq!(test_decode("s_load_b32 s0, s[4:5], -20"), Instruction::SMEM { op: 0, sdata: 0, sbase: 4, offset: -20, soffset: NULL, glc: false, dlc: false }); - assert_eq!(test_decode("s_load_b32 s0, s[4:5], -1048576"), Instruction::SMEM { op: 0, sdata: 0, sbase: 4, offset: -1048576, soffset: NULL, glc: false, dlc: false }); - } - - #[test] - fn test_decode_salu() { - assert_eq!(test_decode("s_add_u32 s1 s2 s3"), Instruction::SOP2 { op: 0, ssrc0: 2, ssrc1: 3, sdst: 1 }); - assert_eq!(test_decode("s_add_u32 vcc_hi exec_lo vcc_lo"), Instruction::SOP2 { op: 0, ssrc0: 126, ssrc1: 106, sdst: 107 }); - assert_eq!(test_decode("s_mov_b32 s1 -0.5"), Instruction::SOP1 { op: 0, ssrc0: 241, sdst: 1 }); - assert_eq!(test_decode("s_cmpk_eq_i32 s0 -30"), Instruction::SOPK { op: 3, sdst: 0, simm16: -30 }); - assert_eq!(test_decode("s_cmpk_eq_u32 s0 65535"), Instruction::SOPK { op: 9, sdst: 0, simm16: -1 }); - assert_eq!(test_decode("s_cmp_ge_i32 s1 s2"), Instruction::SOPC { op: 3, ssrc0: 1, ssrc1: 2 }); - } - - #[test] - fn test_decode_valu_e32() { - assert_eq!(test_decode("v_mov_b32 v0, v0"), Instruction::VOP1 { op: 1, vdst: 0, src: 256 }); - assert_eq!(test_decode("v_mov_b32 v0, s0"), Instruction::VOP1 { op: 1, vdst: 0, src: 0 }); - assert_eq!(test_decode("v_cmp_t_f32 v1, v0"), Instruction::VOPC { op: 31, vsrc: 0, src: 257 }); - } - - #[test] - fn test_decode_valu_e64() { - assert_eq!(test_decode("v_log_f32_e64 v2, |v0|"), Instruction::VOP3 { op: 423, vdst: 2, src0: 256, src1: 0, src2: 0, abs: 0b001, neg: 0, opsel: 0, omod: 0, cm: false }); - assert_eq!(test_decode("v_div_scale_f32 v2, s1, v0, v1, v2"), Instruction::VOP3SD { op: 764, cm: false, vdst: 2, sdst: 1, src0: 256, src1: 257, src2: 258, omod: 0, neg: 0 }); - assert_eq!(test_decode("v_pk_add_i16 v1, v0, v2"), Instruction::VOP3P { op: 2, vdst: 1, neg_hi: 0, opsel: 0, opsel_hi: 3, opsel_hi2: true, cm: false, src2: 0, src1: 258, src0: 256, neg: 0 }); - } - - #[test] - fn test_decode_ds() { - assert_eq!(test_decode("ds_add_u32 v2, v4 offset:16"), Instruction::DS { op: 0, gds: false, offset1: 0, offset0: 0x10, vdst: 0, data1: 0, data0: 4, addr: 2 }); - assert_eq!(test_decode("ds_store_b32 v0, v1, offset: 0x04 gds"), Instruction::DS { op: 13, gds: true, offset1: 0, offset0: 0x04, vdst: 0, data1: 0, data0: 1, addr: 0 }); - assert_eq!(test_decode("ds_load_u8 v1, v0 offset:16"), Instruction::DS { op: 58, gds: false, offset1: 0, offset0: 16, vdst: 1, data1: 0, data0: 0, addr: 0 }); - } -} diff --git a/tinygrad/extra/remu/src/state.rs b/tinygrad/extra/remu/src/state.rs deleted file mode 100644 index bd0971b0..00000000 --- a/tinygrad/extra/remu/src/state.rs +++ /dev/null @@ -1,254 +0,0 @@ -use std::ops::{Index, IndexMut}; - -pub trait Register { - fn read64(&self, idx: usize) -> u64; - fn write64(&mut self, idx: usize, addr: u64); -} -impl Register for T where T: Index + IndexMut { - fn read64(&self, idx: usize) -> u64 { - let lsb = self[idx] as u64; - let msb = self[idx + 1] as u64; - (msb << 32) | lsb - } - - fn write64(&mut self, idx: usize, value: u64) { - self[idx] = (value & 0xffffffff) as u32; - self[idx + 1] = ((value & (0xffffffff << 32)) >> 32) as u32; - } -} - -#[derive(Debug, Clone)] -pub struct VGPR { - values: [[u32; 256]; 32], - pub default_lane: Option, -} -impl Index for VGPR { - type Output = u32; - fn index(&self, index: usize) -> &Self::Output { - &self.values[self.default_lane.unwrap()][index] - } -} -impl IndexMut for VGPR { - fn index_mut(&mut self, index: usize) -> &mut Self::Output { - &mut self.values[self.default_lane.unwrap()][index] - } -} -impl VGPR { - pub fn new() -> Self { - VGPR { - values: [[0; 256]; 32], - default_lane: None, - } - } - pub fn get_lane(&self, lane: usize) -> [u32; 256] { - *self.values.get(lane).unwrap() - } - pub fn get_lane_mut(&mut self, lane: usize) -> &mut [u32; 256] { - self.values.get_mut(lane).unwrap() - } -} - -pub trait Value { - fn mut_hi16(&mut self, val: u16); - fn mut_lo16(&mut self, val: u16); -} -impl Value for u32 { - fn mut_hi16(&mut self, val: u16) { - *self = ((val as u32) << 16) | (*self as u16 as u32); - } - fn mut_lo16(&mut self, val: u16) { - *self = ((((*self & (0xffff << 16)) >> 16) as u32) << 16) | val as u32; - } -} - -#[derive(Debug, Clone, Copy)] -pub struct WaveValue { - pub value: u32, - pub warp_size: usize, - pub default_lane: Option, - pub mutations: Option<[bool; 32]>, -} -impl WaveValue { - pub fn new(value: u32, warp_size: usize) -> Self { - Self { - value, - warp_size, - default_lane: None, - mutations: None, - } - } - pub fn read(&self) -> bool { - (self.value >> self.default_lane.unwrap()) & 1 == 1 - } - pub fn set_lane(&mut self, value: bool) { - if self.mutations.is_none() { - self.mutations = Some([false; 32]) - } - self.mutations.as_mut().unwrap()[self.default_lane.unwrap()] = value; - } - pub fn apply_muts(&mut self) { - self.value = 0; - for lane in 0..self.warp_size { - if self.mutations.unwrap()[lane] { - self.value |= 1 << lane; - } - } - } -} - -#[derive(Clone, Debug)] -pub struct VecDataStore { - pub data: Vec, -} - -impl VecDataStore { - pub fn new() -> Self { - Self { data: Vec::new() } - } - pub fn write(&mut self, addr: usize, val: u32) { - if addr + 4 >= self.data.len() { - self.data.resize(self.data.len() + addr + 5, 0); - } - self.data[addr..addr + 4].iter_mut().enumerate().for_each(|(i, x)| { - *x = val.to_le_bytes()[i]; - }); - } - pub fn write64(&mut self, addr: usize, val: u64) { - self.write(addr, (val & 0xffffffff) as u32); - self.write(addr + 4, ((val & (0xffffffff << 32)) >> 32) as u32); - } - pub fn read(&self, addr: usize) -> u32 { - let mut bytes: [u8; 4] = [0; 4]; - bytes.copy_from_slice(&self.data[addr + 0..addr + 4]); - u32::from_le_bytes(bytes) - } - pub fn read64(&mut self, addr: usize) -> u64 { - let lsb = self.read(addr); - let msb = self.read(addr + 4); - ((msb as u64) << 32) | lsb as u64 - } -} - -#[cfg(test)] -mod test_state { - use super::*; - - #[test] - fn test_wave_value() { - let mut val = WaveValue::new(0b11000000000000011111111111101110, 32); - val.default_lane = Some(0); - assert!(!val.read()); - val.default_lane = Some(31); - assert!(val.read()); - } - - #[test] - fn test_wave_value_small() { - let mut val = WaveValue::new(0, 1); - val.default_lane = Some(0); - assert!(!val.read()); - assert_eq!(val.value, 0); - val.set_lane(true); - val.apply_muts(); - assert!(val.read()); - assert_eq!(val.value, 1); - } - - #[test] - fn test_wave_value_small_alt() { - let mut val = WaveValue::new(0, 2); - val.default_lane = Some(0); - assert!(!val.read()); - assert_eq!(val.value, 0); - val.set_lane(true); - val.apply_muts(); - assert!(val.read()); - assert_eq!(val.value, 1); - } - - #[test] - fn test_wave_value_exec() { - let warp_size = 32; - let val = WaveValue::new(u32::MAX, warp_size); - assert_eq!(val.value, u32::MAX); - let warp_size = 3; - let val = WaveValue::new((1 << warp_size) - 1, warp_size); - assert_eq!(val.value, 7) - } - - #[test] - fn test_wave_value_toggle_one() { - let warp_size = 2; - let mut val = WaveValue::new(0b11, warp_size); - // 0 - val.default_lane = Some(0); - val.set_lane(false); - // 1 - val.default_lane = Some(1); - val.set_lane(true); - val.apply_muts(); - assert_eq!(val.value, 2); - } - - #[test] - fn test_wave_value_mutate_small() { - let mut val = WaveValue::new(0, 2); - val.default_lane = Some(0); - assert!(!val.read()); - assert_eq!(val.value, 0); - val.set_lane(true); - val.apply_muts(); - assert!(val.read()); - assert_eq!(val.value, 1); - } - - #[test] - fn test_wave_value_mutations() { - let mut val = WaveValue::new(0b10001, 32); - val.default_lane = Some(0); - val.set_lane(false); - assert!(val.mutations.unwrap().iter().all(|x| !x)); - val.default_lane = Some(1); - val.set_lane(true); - assert_eq!(val.value, 0b10001); - assert_eq!( - val.mutations, - Some([ - false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, - false, false, false, false, false, false, false, false, false, false, false, false, false, - ]) - ); - - val.apply_muts(); - assert_eq!(val.value, 0b10); - } - - #[test] - fn test_write16() { - let mut vgpr = VGPR::new(); - vgpr.default_lane = Some(0); - vgpr[0] = 0b11100000000000001111111111111111; - vgpr[0].mut_lo16(0b1011101111111110); - assert_eq!(vgpr[0], 0b11100000000000001011101111111110); - } - - #[test] - fn test_write16hi() { - let mut vgpr = VGPR::new(); - vgpr.default_lane = Some(0); - vgpr[0] = 0b11100000000000001111111111111111; - vgpr[0].mut_hi16(0b1011101111111110); - assert_eq!(vgpr[0], 0b10111011111111101111111111111111); - } - - #[test] - fn test_vgpr() { - let mut vgpr = VGPR::new(); - vgpr.default_lane = Some(0); - vgpr[0] = 42; - vgpr.default_lane = Some(10); - vgpr[0] = 10; - assert_eq!(vgpr.get_lane(0)[0], 42); - assert_eq!(vgpr.get_lane(10)[0], 10); - } -} diff --git a/tinygrad/extra/remu/src/thread.rs b/tinygrad/extra/remu/src/thread.rs deleted file mode 100644 index 4cb84a56..00000000 --- a/tinygrad/extra/remu/src/thread.rs +++ /dev/null @@ -1,3731 +0,0 @@ -use crate::helpers::{extract_mantissa, f16_hi, f16_lo, ldexp, nth, sign_ext, IEEEClass, VOPModifier}; -use crate::helpers::DEBUG; -use crate::state::{Register, Value, VecDataStore, WaveValue, VGPR}; -use crate::todo_instr; -use half::{bf16, f16}; -use crate::rdna3::{Instruction, decode}; -use num_traits::Float; - -pub const SGPR_COUNT: usize = 128; -pub const VCC: usize = 106; -pub const EXEC: usize = 126; -pub const NULL_SRC: usize = 124; -pub const SGPR_SRC: usize = 105; - -const VGPR_COUNT: usize = 256; -const SIMM_SRC: usize = 255; - -pub const END_PRG: u32 = 0xbfb00000; - -pub struct Thread<'a> { - pub scalar_reg: &'a mut [u32; SGPR_COUNT], - pub scc: &'a mut u32, // SCC is physically an sgpr, unclear which one - - pub vec_reg: &'a mut VGPR, - pub vcc: &'a mut WaveValue, - pub exec: &'a mut WaveValue, - - pub lds: &'a mut VecDataStore, - pub sds: &'a mut VecDataStore, - - pub pc_offset: usize, - pub stream: Vec, - pub simm: Option, - pub sgpr_co: &'a mut Option<(usize, WaveValue)>, - pub warp_size: usize, - pub scalar: bool, -} - -impl<'a> Thread<'a> { - pub fn interpret(&mut self) -> Result<(), i32> { - let instruction = self.stream[self.pc_offset]; - let decoded = decode(self.stream[self.pc_offset], self.stream.get(self.pc_offset+1)); - if *DEBUG { - print!("{:?}", decoded); - } - if let Instruction::SMEM { sbase, sdata, op, offset, soffset, .. } = decoded { - let _ = self.u64_instr(); - let soffset: u32 = self.val(soffset as usize); - - // TODO: refactor vcc_lo to store in scalar register 106 - let base_addr = match sbase as usize { - VCC => ((self.scalar_reg[107] as u64) << 32) | self.vcc.value as u64, - s => self.scalar_reg.read64(s), - }; - let addr = (base_addr as i64 + offset as i64 + soffset as i64) as u64; - - match op { - 0..=4 => (0..2_usize.pow(op as u32)).for_each(|i| { - let ret = unsafe { *((addr + (4 * i as u64)) as *const u32) }; - self.write_to_sdst(sdata as usize + i, ret); - }), - _ => todo_instr!(instruction)?, - }; - self.scalar = true; - } - else if let Instruction::SOP1 { ssrc0, op, sdst } = decoded { - let src = ssrc0 as usize; - let sdst = sdst as usize; - - match op { - 1 => { - let s0 = self.val(src); - let ret = match op { - 1 => s0, - _ => todo_instr!(instruction)?, - }; - self.scalar_reg.write64(sdst as usize, ret); - } - _ => { - let s0 = self.val(src); - let ret = match op { - 0 => s0, - 10 => self.clz_i32_u32(s0), - 12 => self.cls_i32(s0), - 4 => s0.reverse_bits(), - 14 => s0 as i8 as i32 as u32, - 15 => s0 as i16 as i32 as u32, - 16 | 18 => { - let sdst: u32 = self.val(sdst as usize); - if op == 16 { - sdst & !(1 << (s0 & 0x1f)) - } else { - sdst | (1 << (s0 & 0x1f)) - } - } - 21 => { - let s0 = s0 as i32; - let ret = s0.abs(); - *self.scc = (ret != 0) as u32; - ret as u32 - } - 30 => { - let ret = !s0; - *self.scc = (ret != 0) as u32; - ret - } - 32 | 34 | 48 => { - let saveexec = self.exec.value; - self.exec.value = match op { - 32 => s0 & saveexec, - 34 => s0 | saveexec, - 48 => s0 & !saveexec, - _ => todo_instr!(instruction)?, - }; - *self.scc = (self.exec.value != 0) as u32; - saveexec - } - _ => todo_instr!(instruction)?, - }; - - self.write_to_sdst(sdst, ret); - } - }; - self.scalar = true; - } - else if let Instruction::SOPC { ssrc0, ssrc1, op } = decoded { - let s0 = ssrc0 as usize; - let s1 = ssrc1 as usize; - - fn scmp(s0: T, s1: T, offset: u8, op: u8) -> bool - where - T: PartialOrd + PartialEq, - { - match op - offset { - 0 => s0 == s1, - 1 => s0 != s1, - 2 => s0 > s1, - 3 => s0 >= s1, - 4 => s0 < s1, - _ => s0 <= s1, - } - } - *self.scc = match op { - 0..=5 => { - let (s0, s1): (u32, u32) = (self.val(s0), self.val(s1)); - scmp(s0 as i32, s1 as i32, 0, op) - } - 6..=11 => { - let (s0, s1): (u32, u32) = (self.val(s0), self.val(s1)); - scmp(s0, s1, 6, op) - } - 12 => { - let (s0, s1): (u32, u32) = (self.val(s0), self.val(s1)); - s0 & (1 << (s1 & 0x1F)) == 0 - } - 13 => { - let (s0, s1): (u32, u32) = (self.val(s0), self.val(s1)); - s0 & (1 << (s1 & 0x1F)) == 1 - } - 16 | 17 => { - let (s0, s1): (u64, u64) = (self.val(s0), self.val(s1)); - scmp(s0, s1, 16, op) - } - _ => todo_instr!(instruction)?, - } as u32; - self.scalar = true; - } - else if let Instruction::SOPP { simm16, op } = decoded { - - match op { - 32..=42 => { - let should_jump = match op { - 32 => true, - 33 => *self.scc == 0, - 34 => *self.scc == 1, - 35 => self.vcc.value == 0, - 36 => self.vcc.value != 0, - 37 => self.exec.value == 0, - 38 => self.exec.value != 0, - _ => todo_instr!(instruction)?, - }; - if should_jump { - self.pc_offset = (self.pc_offset as i64 + simm16 as i64) as usize; - } - } - _ => todo_instr!(instruction)?, - }; - self.scalar = true; - } - else if let Instruction::SOPK { simm16, sdst, op } = decoded { - let simm = simm16 as u16; - let sdst = sdst as usize; - let s0: u32 = self.val(sdst); - - match op { - 0 => self.write_to_sdst(sdst, simm as i16 as i32 as u32), - 3..=8 => { - let s1 = simm as i16 as i64; - let s0 = s0 as i32 as i64; - *self.scc = match op { - 3 => s0 == s1, - 4 => s0 != s1, - 5 => s0 > s1, - 7 => s0 < s1, - _ => todo_instr!(instruction)?, - } as u32 - } - 9..=14 => { - let s1 = simm as u16 as u32; - *self.scc = match op { - 9 => s0 == s1, - 10 => s0 != s1, - 11 => s0 > s1, - 12 => s0 >= s1, - 13 => s0 < s1, - 14 => s0 <= s1, - _ => todo_instr!(instruction)?, - } as u32 - } - 15 => { - let temp = s0 as i32; - let simm16 = simm as i16; - let dest = (temp as i64 + simm16 as i64) as i32; - self.write_to_sdst(sdst, dest as u32); - let temp_sign = ((temp >> 31) & 1) as u32; - let simm_sign = ((simm16 >> 15) & 1) as u32; - let dest_sign = ((dest >> 31) & 1) as u32; - *self.scc = ((temp_sign == simm_sign) && (temp_sign != dest_sign)) as u32; - } - 16 => { - let simm16 = simm as i16; - let ret = (s0 as i32 * simm16 as i32) as u32; - self.write_to_sdst(sdst, ret); - } - _ => todo_instr!(instruction)?, - }; - self.scalar = true; - } - else if let Instruction::SOP2 { ssrc0, ssrc1, sdst, op } = decoded { - let s0 = ssrc0 as usize; - let s1 = ssrc1 as usize; - let sdst = sdst as usize; - - match op { - 23 | 25 | 27 => { - let (s0, s1): (u64, u64) = (self.val(s0), self.val(s1)); - let ret = match op { - 23 => s0 & s1, - 25 => s0 | s1, - 27 => s0 ^ s1, - _ => todo_instr!(instruction)?, - }; - self.scalar_reg.write64(sdst as usize, ret); - *self.scc = (ret != 0) as u32; - } - 9 | 13 | 11 | 40 | 41 => { - let (s0, s1): (u64, u32) = (self.val(s0), self.val(s1)); - let ret = match op { - 9 => { - let ret = s0 << (s1 & 0x3f); - (ret, Some(ret != 0)) - } - 11 => { - let ret = s0 >> (s1 & 0x3f); - (ret as u64, Some(ret != 0)) - } - 13 => { - let ret = (s0 as i64) >> (s1 & 0x3f); - (ret as u64, Some(ret != 0)) - } - 40 => { - let ret = (s0 >> (s1 & 0x3f)) & ((1 << ((s1 >> 16) & 0x7f)) - 1); - (ret as u64, Some(ret != 0)) - } - 41 => { - let s0 = s0 as i64; - let mut ret = (s0 >> (s1 & 0x3f)) & ((1 << ((s1 >> 16) & 0x7f)) - 1); - let shift = 64 - ((s1 >> 16) & 0x7f); - ret = (ret << shift) >> shift; - (ret as u64, Some(ret != 0)) - } - _ => todo_instr!(instruction)?, - }; - self.scalar_reg.write64(sdst as usize, ret.0); - if let Some(val) = ret.1 { - *self.scc = val as u32 - } - } - _ => { - let (s0, s1): (u32, u32) = (self.val(s0), self.val(s1)); - let ret = match op { - 0 | 4 => { - let (s0, s1) = (s0 as u64, s1 as u64); - let ret = match op { - 0 => s0 + s1, - 4 => s0 + s1 + *self.scc as u64, - _ => todo_instr!(instruction)?, - }; - (ret as u32, Some(ret >= 0x100000000)) - } - 1 => (s0 - s1, Some(s1 > s0)), - 5 => (s0 - s1 - *self.scc, Some((s1 as u64 + *self.scc as u64) > s0 as u64)), - 2 | 3 => { - let s0 = s0 as i32 as i64; - let s1 = s1 as i32 as i64; - let ret = match op { - 2 => s0 + s1, - 3 => s0 - s1, - _ => todo_instr!(instruction)?, - }; - let overflow = (nth(s0 as u32, 31) == nth(s1 as u32, 31)) && (nth(s0 as u32, 31) != nth(ret as u32, 31)); - - (ret as i32 as u32, Some(overflow)) - } - (8..=17) => { - let s1 = s1 & 0x1f; - let ret = match op { - 8 => s0 << s1, - 10 => s0 >> s1, - 12 => ((s0 as i32) >> (s1 as i32)) as u32, - _ => todo_instr!(instruction)?, - }; - (ret, Some(ret != 0)) - } - (18..=21) => { - let scc = match op { - 18 => (s0 as i32) < (s1 as i32), - 19 => s0 < s1, - 20 => (s0 as i32) > (s1 as i32), - 21 => s0 > s1, - _ => todo_instr!(instruction)?, - }; - let ret = match scc { - true => s0, - false => s1, - }; - (ret, Some(scc)) - } - (22..=26) | 34 | 36 => { - let ret = match op { - 22 => s0 & s1, - 24 => s0 | s1, - 26 => s0 ^ s1, - 34 => s0 & !s1, - 36 => s0 | !s1, - _ => todo_instr!(instruction)?, - }; - (ret, Some(ret != 0)) - } - 38 => { - let ret = (s0 >> (s1 & 0x1f)) & ((1 << ((s1 >> 16) & 0x7f)) - 1); - (ret, Some(ret != 0)) - } - 39 => { - let s0 = s0 as i32; - let mut ret = (s0 >> (s1 & 0x1f)) & ((1 << ((s1 >> 16) & 0x1f)) - 1); - let shift = 32 - ((s1 >> 16) & 0x7f); - ret = (ret << shift) >> shift; - (ret as u32, Some(ret != 0)) - } - 44 => (((s0 as i32) * (s1 as i32)) as u32, None), - 45 => (((s0 as u64) * (s1 as u64) >> 32) as u32, None), - 46 => ((((s0 as i32 as i64 * s1 as i32 as i64) as u64) >> 32u64) as i32 as u32, None), - 48 => match *self.scc != 0 { - true => (s0, None), - false => (s1, None), - }, - 50..=53 => { - let (s0, s1) = match op { - 50 => (s0 as u16, s1 as u16), - 51 => (s0 as u16, (s1 >> 16) as u16), - 52 => ((s0 >> 16) as u16, (s1 >> 16) as u16), - _ => ((s0 >> 16) as u16, s1 as u16), - }; - (((s1 as u32) << 16) | (s0 as u32), None) - } - _ => todo_instr!(instruction)?, - }; - - self.write_to_sdst(sdst, ret.0); - if let Some(val) = ret.1 { - *self.scc = val as u32 - } - } - }; - self.scalar = true; - } - // vopp - else if instruction >> 24 == 0b11001100 { - let instr = self.u64_instr(); - let vdst = (instr & 0xff) as usize; - let clmp = (instr >> 15) & 0x1; - assert_eq!([clmp], [0]); - let op = (instr >> 16) & 0x7f; - - let mut src = |x: usize| -> (u16, u16, u32) { - let val: u32 = self.val(x); - match x { - 255 => { - let val_lo: u16 = self.val(x); - (val_lo, val_lo, val) - } - (240..=247) => { - let val_lo: u16 = self.val(x); - (val_lo, f16::from_bits(0).to_bits(), val) - } - _ => ((val & 0xffff) as u16, ((val >> 16) & 0xffff) as u16, val), - } - }; - - let s = [32, 41, 50].iter().map(|x| ((instr >> x) & 0x1ff) as usize).collect::>(); - let src_parts = s.iter().map(|x| src(*x)).collect::>(); - - let b = |i: usize| (instr >> i) & 0x1 != 0; - let neg_hi = ((instr >> 8) & 0x7) as usize; - let neg = ((instr >> 61) & 0x7) as usize; - let opsel = [b(11), b(12), b(13)]; - let opsel_hi = [b(59), b(60), b(14)]; - - match op { - 0..=18 => { - let fxn = |x, y, z| -> u16 { - match op { - 0 => x * y + z, - 1 => x * y, - 2 => x + y, - 3 => x - y, - 4 => y << (x & 0xf), - 5 => y >> (x & 0xf), - 6 => ((y as i16) >> ((x as i16) & 0xf)) as u16, - 7 => i16::max(x as i16, y as i16) as u16, - 8 => i16::min(x as i16, y as i16) as u16, - 9 => x * y + z, - 10 => x + y, - 11 => x - y, - 12 => u16::max(x, y), - 13 => u16::min(x, y), - _ => { - let (x, y, z) = (f16::from_bits(x), f16::from_bits(y), f16::from_bits(z)); - let ret = match op { - 14 => f16::mul_add(x, y, z), - 15 => x + y, - 16 => x * y, - 17 => f16::min(x, y), - 18 => f16::max(x, y), - _ => unreachable!("op should be in range 0..=18, got {op}"), - }; - ret.to_bits() - } - } - }; - let src = |opsel: [bool; 3]| { - opsel - .iter() - .enumerate() - .map(|(i, sel)| { - if (14..=19).contains(&op) { - let half = |x, n| f16::from_bits(x).negate(i, n).to_bits(); - match sel { - true => half(src_parts[i].1, neg), - false => half(src_parts[i].0, neg_hi), - } - } else { - match sel { - true => src_parts[i].1, - false => src_parts[i].0, - } - } - }) - .collect::>() - }; - let (src_hi, src_lo) = (src(opsel_hi), src(opsel)); - let ret = ((fxn(src_hi[0], src_hi[1], src_hi[2]) as u32) << 16) | (fxn(src_lo[0], src_lo[1], src_lo[2]) as u32); - - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - 32..=34 => { - let src: Vec = src_parts - .iter() - .enumerate() - .map(|(i, (lo, hi, full))| { - if !opsel_hi[i] { - f32::from_bits(*full).absolute(i, neg_hi) - } else if opsel[i] { - f32::from(f16::from_bits(*hi)).absolute(i, neg_hi) - } else { - f32::from(f16::from_bits(*lo)).absolute(i, neg_hi) - } - }) - .collect(); - let ret = match op { - 32 => f32::mul_add(src[0], src[1], src[2]).to_bits(), - 33 | 34 => { - let ret = f16::from_f32(f32::mul_add(src[0], src[1], src[2])).to_bits(); - match op { - 33 => (self.vec_reg[vdst] & 0xffff0000) | (ret as u32), - 34 => (self.vec_reg[vdst] & 0x0000ffff) | ((ret as u32) << 16), - _ => todo_instr!(instruction)?, - } - } - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - 64..=69 => { - match op { - 64 => { - let a = self.wmma_b16_16x16(s[0]).map(|v| f16::from_bits(v).to_f32()); - let b = self.wmma_b16_16x16(s[1]).map(|v| f16::from_bits(v).to_f32()); - let c = self.wmma_b32_16x16(s[2]).map(|v| f32::from_bits(v)); - let ret = wmma(a.collect(), b.collect(), c.collect()); - for (i, val) in ret.into_iter().enumerate() { - let lane = i % 32; - self.vec_reg.get_lane_mut(lane)[(i / 32) + vdst] = val.to_bits(); - } - } - 65 => { - let a = self.wmma_b16_16x16(s[0]).map(|v| bf16::from_bits(v).to_f32()); - let b = self.wmma_b16_16x16(s[1]).map(|v| bf16::from_bits(v).to_f32()); - let c = self.wmma_b32_16x16(s[2]).map(|v| f32::from_bits(v)); - let ret = wmma(a.collect(), b.collect(), c.collect()); - for (i, val) in ret.into_iter().enumerate() { - let register = (i / 32) + vdst; - let lane = i % 32; - self.vec_reg.get_lane_mut(lane)[register] = val.to_bits() - } - } - 66 => { - let a = self.wmma_b16_16x16(s[0]).map(|v| f16::from_bits(v)); - let b = self.wmma_b16_16x16(s[1]).map(|v| f16::from_bits(v)); - let c = self.wmma_b32_16x16(s[2]).map(|v| f16::from_bits(v as u16)); - let ret = wmma(a.collect(), b.collect(), c.collect()); - for (i, val) in ret.into_iter().enumerate() { - let register = (i / 32) + vdst; - let lane = i % 32; - self.vec_reg.get_lane_mut(lane)[register].mut_lo16(val.to_bits()); - } - } - _ => todo_instr!(instruction)?, - }; - self.scalar = true; - } - _ => todo_instr!(instruction)?, - } - } - else if let Instruction::VOP1 { src, op, vdst } = decoded { - let s0 = src as usize; - let vdst = vdst as usize; - - match op { - 3 | 15 | 21 | 23 | 25 | 26 | 60 | 61 | 47 | 49 => { - let s0: u64 = self.val(s0); - match op { - 3 | 15 | 21 | 23 | 25 | 26 | 60 | 61 | 47 | 49 => { - let s0 = f64::from_bits(s0); - match op { - 23 | 25 | 26 | 61 | 47 | 49 => { - let ret = match op { - 23 => f64::trunc(s0), - 25 => { - let mut temp = f64::floor(s0 + 0.5); - if f64::floor(s0) % 2.0 != 0.0 && f64::fract(s0) == 0.5 { - temp -= 1.0; - } - temp - } - 26 => f64::floor(s0), - 47 => 1.0 / s0, - 49 => 1.0 / f64::sqrt(s0), - 61 => extract_mantissa(s0), - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg.write64(vdst, ret.to_bits()) - } - } - _ => { - let ret = match op { - 3 => s0 as i32 as u32, - 15 => (s0 as f32).to_bits(), - 21 => s0 as u32, - 60 => match (s0 == f64::INFINITY) || (s0 == f64::NEG_INFINITY) || s0.is_nan() { - true => 0, - false => (s0.exponent() as i32 - 1023 + 1) as u32, - }, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - } - } - _ => todo_instr!(instruction)?, - } - } - 84..=97 => { - let s0 = f16::from_bits(self.val(s0)); - let ret = match op { - 84 => f16::recip(s0), - 85 => f16::sqrt(s0), - 87 => f16::log2(s0), - 88 => f16::exp2(s0), - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret.to_bits() as u32; - } - } - _ => { - let s0: u32 = self.val(s0); - match op { - 4 | 16 | 22 => { - let ret = match op { - 4 => (s0 as i32 as f64).to_bits(), - 22 => (s0 as f64).to_bits(), - 16 => (f32::from_bits(s0) as f64).to_bits(), - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg.write64(vdst, ret) - } - } - 2 => { - let idx = self.exec.value.trailing_zeros() as usize; - self.scalar_reg[vdst] = self.vec_reg.get_lane(idx)[(instruction & 0x1ff) as usize - VGPR_COUNT]; - } - _ => { - let ret = match op { - 1 => s0, - 5 => (s0 as i32 as f32).to_bits(), - 6 => (s0 as f32).to_bits(), - 7 => f32::from_bits(s0) as u32, - 8 => f32::from_bits(s0) as i32 as u32, - 10 => f16::from_f32(f32::from_bits(s0)).to_bits() as u32, - 11 => f32::from(f16::from_bits(s0 as u16)).to_bits(), - 17 => ((s0 & 0xff) as f32).to_bits(), - 18 => (((s0 >> 8) & 0xff) as f32).to_bits(), - 19 => (((s0 >> 16) & 0xff) as f32).to_bits(), - 20 => (((s0 >> 24) & 0xff) as f32).to_bits(), - 56 => s0.reverse_bits(), - 57 => self.clz_i32_u32(s0), - 33..=51 => { - let s0 = f32::from_bits(s0); - match op { - 33 => s0.trunc(), - 34 => { - let mut d0 = s0.trunc(); - if s0 > 0.0 && s0 != d0 { - d0 += 1.0; - } - d0 - } - 35 => { - let mut temp = f32::floor(s0 + 0.5); - if f32::floor(s0) % 2.0 != 0.0 && f32::fract(s0) == 0.5 { - temp -= 1.0; - } - temp - } - 36 => { - let mut d0 = s0.trunc(); - if s0 < 0.0 && s0 != d0 { - d0 -= 1.0; - } - d0 - } - 37 => f32::exp2(s0), - 39 => f32::log2(s0), - 42 => 1.0 / s0, - 43 => 1.0 / s0, - 51 => f32::sqrt(s0), - _ => todo_instr!(instruction)?, - } - .to_bits() - } - 55 => !s0, - 59 => self.cls_i32(s0), - 80 => f16::from_f32(s0 as u16 as f32).to_bits() as u32, - 81 => f16::from_f32(s0 as i16 as f32).to_bits() as u32, - 82 => f32::from(f16::from_bits(s0 as u16)) as u32, - 83 => f32::from(f16::from_bits(s0 as u16)) as i16 as u32, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - } - } - } - } - // vopd - else if instruction >> 26 == 0b110010 { - let instr = self.u64_instr(); - let sx = instr & 0x1ff; - let vx = (instr >> 9) & 0xff; - let srcx0 = self.val(sx as usize); - let vsrcx1 = self.vec_reg[(vx) as usize] as u32; - let opy = (instr >> 17) & 0x1f; - let sy = (instr >> 32) & 0x1ff; - let vy = (instr >> 41) & 0xff; - let opx = (instr >> 22) & 0xf; - let srcy0 = match sy { - 255 => match sx { - 255 => srcx0, - _ => self.val(sy as usize), - }, - _ => self.val(sy as usize), - }; - let vsrcy1 = self.vec_reg[(vy) as usize]; - - let vdstx = ((instr >> 56) & 0xff) as usize; - // LSB is the opposite of VDSTX[0] - let vdsty = (((instr >> 49) & 0x7f) << 1 | ((vdstx as u64 & 1) ^ 1)) as usize; - - for (op, s0, s1, dst) in ([(opx, srcx0, vsrcx1, vdstx), (opy, srcy0, vsrcy1, vdsty)]).iter() { - let ret = match *op { - 0 | 1 | 2 | 3 | 4 | 5 | 6 | 10 | 11 => { - let s0 = f32::from_bits(*s0 as u32); - let s1 = f32::from_bits(*s1 as u32); - match *op { - 0 => f32::mul_add(s0, s1, f32::from_bits(self.vec_reg[*dst])), - 1 => f32::mul_add(s0, s1, f32::from_bits(self.val(SIMM_SRC))), - 2 => f32::mul_add(s0, f32::from_bits(self.val(SIMM_SRC)), s1), - 3 => s0 * s1, - 4 => s0 + s1, - 5 => s0 - s1, - 6 => s1 - s0, - 10 => f32::max(s0, s1), - 11 => f32::min(s0, s1), - _ => todo_instr!(instruction)?, - } - .to_bits() - } - 8 => *s0, - 9 => match self.vcc.read() { - true => *s1, - false => *s0, - }, - 16 => s0 + s1, - 17 => s1 << s0, - 18 => s0 & s1, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[*dst] = ret; - }; - } - } - // vopc - else if let Instruction::VOPC { vsrc, src, op } = decoded { - let s0 = src as usize; - let s1 = vsrc as usize; - let op = op as u32; - - let dest_offset = if op >= 128 { 128 } else { 0 }; - let ret = match op { - (0..=15) | 125 | (128..=143) => { - let s0 = f16::from_bits(self.val(s0)); - let s1 = f16::from_bits(self.vec_reg[s1] as u16); - match op { - 125 => self.cmp_class_f16(s0, s1.to_bits()), - _ => self.cmpf(s0, s1, op - dest_offset), - } - } - (16..=31) | 126 | (144..=159) => { - let s0 = f32::from_bits(self.val(s0)); - let s1 = f32::from_bits(self.vec_reg[s1]); - match op { - 126 => self.cmp_class_f32(s0, s1.to_bits()), - _ => self.cmpf(s0, s1, op - 16 - dest_offset), - } - } - (32..=47) | 127 | (160..=174) => { - let s0 = self.val(s0); - match op { - 127 => { - let s1 = self.val(s1); - self.cmp_class_f64(s0, s1) - } - _ => { - let s1 = f64::from_bits(self.vec_reg.read64(s1)); - self.cmpf(s0, s1, op - 32 - dest_offset) - } - } - } - (49..=54) | (177..=182) => { - let (s0, s1): (u16, u16) = (self.val(s0), self.vec_reg[s1] as u16); - self.cmpi(s0 as i16, s1 as i16, op - 48 - dest_offset) - } - (57..=62) | (185..=190) => { - let (s0, s1): (u16, u16) = (self.val(s0), self.vec_reg[s1] as u16); - self.cmpi(s0, s1, op - 56 - dest_offset) - } - (64..=71) | (192..=199) => { - let (s0, s1): (u32, u32) = (self.val(s0), self.vec_reg[s1]); - self.cmpi(s0 as i32, s1 as i32, op - 64 - dest_offset) - } - (72..=79) | (200..=207) => { - let (s0, s1): (u32, u32) = (self.val(s0), self.vec_reg[s1]); - self.cmpi(s0, s1, op - 72 - dest_offset) - } - (80..=87) | (208..=215) => { - let (s0, s1): (u64, u64) = (self.val(s0), self.vec_reg.read64(s1)); - self.cmpi(s0 as i64, s1 as i64, op - 80 - dest_offset) - } - (88..=95) | (216..=223) => { - let (s0, s1): (u64, u64) = (self.val(s0), self.vec_reg.read64(s1)); - self.cmpi(s0, s1, op - 88 - dest_offset) - } - _ => todo_instr!(instruction)?, - }; - - if self.exec.read() { - match op >= 128 { - true => self.exec.set_lane(ret), - false => self.vcc.set_lane(ret), - }; - } - } - else if let Instruction::VOP2 { vsrc, src, vdst, op } = decoded { - let s0 = src as usize; - let s1 = self.vec_reg[vsrc as usize]; - let vdst = vdst as usize; - - match op { - (50..=60) => { - let (s0, s1) = (f16::from_bits(self.val(s0)), f16::from_bits(s1 as u16)); - let ret = match op { - 50 => s0 + s1, - 51 => s0 - s1, - 53 => s0 * s1, - 54 => f16::mul_add(s0, s1, f16::from_bits(self.vec_reg[vdst] as u16)), - 55 => f16::mul_add(s0, f16::from_bits(self.val(SIMM_SRC)), s1), - 56 => f16::mul_add(s0, s1, f16::from_bits(self.val(SIMM_SRC))), - 57 => f16::max(s0, s1), - 58 => f16::min(s0, s1), - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret.to_bits() as u32; - } - } - _ => { - let s0 = self.val(s0); - let ret = match op { - 1 => match self.vcc.read() { - true => s1, - false => s0, - }, - 2 => { - let mut acc = f32::from_bits(self.vec_reg[vdst]); - acc += f32::from(f16_lo(s0)) * f32::from(f16_lo(s1)); - acc += f32::from(f16_hi(s0)) * f32::from(f16_hi(s1)); - acc.to_bits() - } - - 3 | 4 | 5 | 8 | 15 | 16 | 43 | 44 | 45 => { - let (s0, s1) = (f32::from_bits(s0), f32::from_bits(s1)); - match op { - 3 => s0 + s1, - 4 => s0 - s1, - 5 => s1 - s0, - 8 => s0 * s1, - 15 => f32::min(s0, s1), - 16 => f32::max(s0, s1), - 43 => f32::mul_add(s0, s1, f32::from_bits(self.vec_reg[vdst])), - 44 => f32::mul_add(s0, f32::from_bits(self.val(SIMM_SRC)), s1), - 45 => f32::mul_add(s0, s1, f32::from_bits(self.val(SIMM_SRC))), - _ => todo_instr!(instruction)?, - } - .to_bits() - } - 9 => { - let s0 = sign_ext((s0 & 0xffffff) as u64, 24) as i32; - let s1 = sign_ext((s1 & 0xffffff) as u64, 24) as i32; - (s0 * s1) as u32 - } - 17 | 18 | 26 => { - let (s0, s1) = (s0 as i32, s1 as i32); - (match op { - 17 => i32::min(s0, s1), - 18 => i32::max(s0, s1), - 26 => s1 >> s0, - _ => todo_instr!(instruction)?, - }) as u32 - } - 32 => { - let temp = s0 as u64 + s1 as u64 + self.vcc.read() as u64; - self.vcc.set_lane(temp >= 0x100000000); - temp as u32 - } - 33 | 34 => { - let temp = match op { - 33 => s0 - s1 - self.vcc.read() as u32, - 34 => s1 - s0 - self.vcc.read() as u32, - _ => todo_instr!(instruction)?, - }; - self.vcc.set_lane((s1 as u64 + self.vcc.read() as u64) > s0 as u64); - temp - } - 11 => s0 * s1, - 19 => u32::min(s0, s1), - 20 => u32::max(s0, s1), - 24 => s1 << s0, - 25 => s1 >> s0, - 27 => s0 & s1, - 28 => s0 | s1, - 29 => s0 ^ s1, - 37 => s0 + s1, - 38 => s0 - s1, - 39 => s1 - s0, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - }; - } - // vop3 - else if instruction >> 26 == 0b110101 { - let instr = self.u64_instr(); - - let op = ((instr >> 16) & 0x3ff) as u32; - match op { - 764 | 765 | 288 | 289 | 290 | 766 | 768 | 769 => { - let vdst = (instr & 0xff) as usize; - let sdst = ((instr >> 8) & 0x7f) as usize; - let f = |i: u32| -> usize { ((instr >> i) & 0x1ff) as usize }; - let (s0, s1, s2) = (f(32), f(41), f(50)); - let mut carry_in = WaveValue::new(self.val(s2), self.warp_size); - carry_in.default_lane = self.vcc.default_lane; - let omod = (instr >> 59) & 0x3; - let _neg = (instr >> 61) & 0x7; - let clmp = (instr >> 15) & 0x1; - assert_eq!(omod, 0); - assert_eq!(clmp, 0); - - let vcc = match op { - 766 => { - let (s0, s1, s2): (u32, u32, u64) = (self.val(s0), self.val(s1), self.val(s2)); - let (mul_result, overflow_mul) = (s0 as u64).overflowing_mul(s1 as u64); - let (ret, overflow_add) = mul_result.overflowing_add(s2); - let overflowed = overflow_mul || overflow_add; - if self.exec.read() { - self.vec_reg.write64(vdst, ret); - } - overflowed - } - 765 => { - assert!(f64::from_bits(self.val(s2)).exponent() <= 1076); - let ret = ldexp(self.val(s0), 128); - if self.exec.read() { - self.vec_reg.write64(vdst, ret.to_bits()); - } - false - } - _ => { - let (s0, s1, _s2): (u32, u32, u32) = (self.val(s0), self.val(s1), self.val(s2)); - let (ret, vcc) = match op { - 288 => { - let ret = s0 as u64 + s1 as u64 + carry_in.read() as u64; - (ret as u32, ret >= 0x100000000) - } - 289 => { - let ret = (s0 as u64).wrapping_sub(s1 as u64).wrapping_sub(carry_in.read() as u64); - (ret as u32, s1 as u64 + (carry_in.read() as u64) > s0 as u64) - } - 290 => { - let ret = (s1 as u64).wrapping_sub(s0 as u64).wrapping_sub(carry_in.read() as u64); - (ret as u32, s1 as u64 + (carry_in.read() as u64) > s0 as u64) - } - 764 => (0, false), // NOTE: div scaling isn't required - 768 => { - let ret = s0 as u64 + s1 as u64; - (ret as u32, ret >= 0x100000000) - } - 769 => { - let ret = s0.wrapping_sub(s1); - (ret as u32, s1 > s0) - } - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - vcc - } - }; - - match sdst { - VCC => self.vcc.set_lane(vcc), - NULL_SRC => {} - _ => self.set_sgpr_co(sdst, vcc), - } - } - _ => { - let vdst = (instr & 0xff) as usize; - let abs = ((instr >> 8) & 0x7) as usize; - let opsel = ((instr >> 11) & 0xf) as usize; - let cm = (instr >> 15) & 0x1; - - let s = |n: usize| ((instr >> n) & 0x1ff) as usize; - let src = (s(32), s(41), s(50)); - - let omod = (instr >> 59) & 0x3; - let neg = ((instr >> 61) & 0x7) as usize; - assert_eq!(omod, 0); - assert_eq!(cm, 0); - assert_eq!(opsel, 0); - - match op { - // VOPC using VOP3 encoding - 0..=255 => { - let dest_offset = if op >= 128 { 128 } else { 0 }; - let ret = match op { - (0..=15) | 125 | (128..=143) => { - let (s0, s1) = (self.val(src.0), self.val(src.1)); - let s0 = f16::from_bits(s0).negate(0, neg).absolute(0, abs); - let s1 = f16::from_bits(s1).negate(1, neg).absolute(1, abs); - match op { - 125 => self.cmp_class_f16(s0, s1.to_bits()), - _ => self.cmpf(s0, s1, op - dest_offset), - } - } - (16..=31) | 126 | (144..=159) => { - let (s0, s1) = (self.val(src.0), self.val(src.1)); - let s0 = f32::from_bits(s0).negate(0, neg).absolute(0, abs); - let s1 = f32::from_bits(s1).negate(1, neg).absolute(1, abs); - match op { - 126 => self.cmp_class_f32(s0, s1.to_bits()), - _ => self.cmpf(s0, s1, op - 16 - dest_offset), - } - } - (32..=47) | 127 | (160..=174) => { - let s0: f64 = self.val(src.0); - let s0 = s0.negate(0, neg).absolute(0, abs); - match op { - 127 => { - let s1 = self.val(src.1); - self.cmp_class_f64(s0, s1) - } - _ => { - let s1 = self.val(src.1); - let s1 = f64::from_bits(s1).negate(1, neg).absolute(1, abs); - self.cmpf(s0, s1, op - 32 - dest_offset) - } - } - } - (49..=54) | (177..=182) => { - let (s0, s1): (u16, u16) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0 as i16, s1 as i16, op - 48 - dest_offset) - } - (57..=62) | (185..=190) => { - let (s0, s1): (u16, u16) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0, s1, op - 56 - dest_offset) - } - (64..=71) | (192..=199) => { - let (s0, s1): (u32, u32) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0 as i32, s1 as i32, op - 64 - dest_offset) - } - (72..=79) | (200..=207) => { - let (s0, s1): (u32, u32) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0, s1, op - 72 - dest_offset) - } - (80..=87) | (208..=215) => { - let (s0, s1): (u64, u64) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0 as i64, s1 as i64, op - 80 - dest_offset) - } - (88..=95) | (216..=223) => { - let (s0, s1): (u64, u64) = (self.val(src.0), self.val(src.1)); - self.cmpi(s0, s1, op - 88 - dest_offset) - } - _ => todo_instr!(instruction)?, - }; - - if self.exec.read() { - match vdst { - 0..=SGPR_SRC | 107 => self.set_sgpr_co(vdst, ret), - VCC => self.vcc.set_lane(ret), - EXEC => self.exec.set_lane(ret), - _ => todo_instr!(instruction)?, - } - } - } - 828..=830 => { - let (s0, s1, _s2): (u32, u64, u64) = (self.val(src.0), self.val(src.1), self.val(src.2)); - let shift = s0 & 0x3f; - let ret = match op { - 828 => s1 << shift, - 829 => s1 >> shift, - 830 => ((s1 as i64) >> shift) as u64, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg.write64(vdst, ret) - } - } - 407 | 532 | 552 | 568 | (807..=811) => { - let (_s0, _s1, _s2): (f64, f64, f64) = (self.val(src.0), self.val(src.1), self.val(src.2)); - let s0 = _s0.negate(0, neg).absolute(0, abs); - let s1 = _s1.negate(1, neg).absolute(1, abs); - let s2 = _s2.negate(2, neg).absolute(2, abs); - let ret = match op { - 407 => f64::trunc(s0), - 532 => f64::mul_add(s0, s1, s2), - 552 => { - assert!(s0.is_normal()); - s0 - } - 807 => s0 + s1, - 808 => s0 * s1, - 809 => f64::min(s0, s1), - 810 => f64::max(s0, s1), - 811 => { - let s1: u32 = self.val(src.1); - s0 * 2f64.powi(s1 as i32) - } - 568 => { - assert!(!self.vcc.read()); - f64::mul_add(s0, s1, s2) - } - _ => todo_instr!(instruction)?, - } - .to_bits(); - if self.exec.read() { - self.vec_reg.write64(vdst, ret) - } - } - 306 | 309 | 310 | 313 | 596 | 584 | 585 | 588 => { - let (s0, s1, s2) = (self.val(src.0), self.val(src.1), self.val(src.2)); - let s0 = f16::from_bits(s0).negate(0, neg).absolute(0, abs); - let s1 = f16::from_bits(s1).negate(1, neg).absolute(1, abs); - let s2 = f16::from_bits(s2).negate(1, neg).absolute(1, abs); - let ret = match op { - 309 => s0 * s1, - 310 => f16::mul_add(s0, s1, f16::from_bits(self.vec_reg[vdst] as u16)), - 306 => s0 + s1, - 584 => f16::mul_add(s0, s1, s2), - 585 => f16::min(f16::min(s0, s1), s2), - 588 => f16::max(f16::max(s0, s1), s2), - 596 => s2 / s1, - 313 => f16::max(s0, s1), - 314 => f16::min(s0, s1), - _ => todo_instr!(instruction)?, - } - .to_bits(); - if self.exec.read() { - self.vec_reg[vdst] = ret as u32; - } - } - 394 => { - let s0 = f32::from_bits(self.val(src.0)).negate(0, neg).absolute(0, abs); - if self.exec.read() { - self.vec_reg[vdst].mut_lo16(f16::from_f32(s0).to_bits()); - } - } - 467 => { - let s0 = f16::from_bits(self.val(src.0)).negate(0, neg).absolute(0, abs); - if self.exec.read() { - self.vec_reg[vdst] = s0.to_f32() as i16 as u32; - } - } - 395 => { - let s0 = f16::from_bits(self.val(src.0)).negate(0, neg).absolute(0, abs); - if self.exec.read() { - self.vec_reg[vdst] = f32::from(s0).to_bits(); - } - } - 399 => { - let s0: f64 = self.val(src.0); - let s0 = s0.negate(0, neg).absolute(0, abs); - if self.exec.read() { - self.vec_reg[vdst] = (s0 as f32).to_bits(); - } - } - 785 => { - let (s0, s1) = (self.val(src.0), self.val(src.1)); - if self.exec.read() { - self.vec_reg[vdst] = (f16::from_bits(s1).to_bits() as u32) << 16 | f16::from_bits(s0).to_bits() as u32; - } - } - _ => { - let (s0, s1, s2) = (self.val(src.0), self.val(src.1), self.val(src.2)); - match op { - 865 => { - if self.exec.read() { - self.vec_reg.get_lane_mut(s1 as usize)[vdst] = s0; - } - return Ok(()); - } - 864 => { - let val = self.vec_reg.get_lane(s1 as usize)[src.0 - VGPR_COUNT]; - self.write_to_sdst(vdst, val); - return Ok(()); - } - 826 => { - if self.exec.read() { - self.vec_reg[vdst].mut_lo16(((s1 as i16) >> (s0 & 0xf)) as u16); - } - return Ok(()); - } - 587 | 577 | 590 | 771 | 772 | 773 | 777 | 779 | 824 | 825 => { - let (s0, s1, s2) = (s0 as u16, s1 as u16, s2 as u16); - let ret = match op { - 587 => u16::min(u16::min(s0, s1), s2), - 590 => u16::max(u16::max(s0, s1), s2), - 577 => s0 * s1 + s2, - 771 => s0 + s1, - 772 => s0 - s1, - 773 => s0 * s1, - 777 => u16::max(s0, s1), - 779 => u16::min(s0, s1), - 824 => s1 << s0, - 825 => s1 >> s0, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst].mut_lo16(ret); - } - return Ok(()); - } - 586 | 589 | 778 | 780 | 781 | 782 => { - let (s0, s1, s2) = (s0 as i16, s1 as i16, s2 as i16); - let ret = match op { - 586 => i16::min(i16::min(s0, s1), s2), - 589 => i16::max(i16::max(s0, s1), s2), - 778 => i16::max(s0, s1), - 780 => i16::min(s0, s1), - 781 => s0 + s1, - 782 => s0 - s1, - _ => todo_instr!(instruction)?, - }; - if self.exec.read() { - self.vec_reg[vdst].mut_lo16(ret as u16); - } - return Ok(()); - } - _ => {} - } - - let ret = match op { - 257 | 259 | 299 | 260 | 261 | 264 | 272 | 392 | 426 | 531 | 537 | 540 | 551 | 567 | 796 => { - let s0 = f32::from_bits(s0).negate(0, neg).absolute(0, abs); - let s1 = f32::from_bits(s1).negate(1, neg).absolute(1, abs); - let s2 = f32::from_bits(s2).negate(2, neg).absolute(2, abs); - match op { - 259 => s0 + s1, - 260 => s0 - s1, - 261 => s1 - s0, - 264 => s0 * s1, - 272 => f32::max(s0, s1), - 299 => f32::mul_add(s0, s1, f32::from_bits(self.vec_reg[vdst])), - 426 => s0.recip(), - 531 => f32::mul_add(s0, s1, s2), - 537 => f32::min(f32::min(s0, s1), s2), - 540 => f32::max(f32::max(s0, s1), s2), - 551 => s2 / s1, - 567 => { - let ret = f32::mul_add(s0, s1, s2); - match self.vcc.read() { - true => 2.0_f32.powi(32) * ret, - false => ret, - } - } - 796 => s0 * 2f32.powi(s1.to_bits() as i32), - // cnd_mask isn't a float only ALU but supports neg - 257 => { - let mut cond = WaveValue::new(s2.to_bits(), self.warp_size); - cond.default_lane = self.vcc.default_lane; - match cond.read() { - true => s1, - false => s0, - } - } - 392 => f32::from_bits(s0 as i32 as u32), - _ => todo_instr!(instruction)?, - } - .to_bits() - } - _ => { - if neg != 0 { - todo_instr!(instruction)? - } - match op { - 529 => { - let s0 = s0 as i32; - let shift = 32 - (s2 & 0x1f); - let mask: i32 = 1 << (s2 & 0x1f); - let ret = (s0 >> (s1 & 0x1f)) & (mask.wrapping_sub(1)); - ((ret << shift) >> shift) as u32 - } - 522 | 541 | 538 | 544 | 814 => { - let (s0, s1, s2) = (s0 as i32, s1 as i32, s2 as i32); - - (match op { - 522 => { - let s0 = sign_ext((s0 & 0xffffff) as u64, 24) as i32; - let s1 = sign_ext((s1 & 0xffffff) as u64, 24) as i32; - s0 * s1 + s2 - } - 538 => i32::min(i32::min(s0, s1), s2), - 541 => i32::max(i32::max(s0, s1), s2), - 544 => { - if (i32::max(i32::max(s0, s1), s2)) == s0 { - i32::max(s1, s2) - } else if (i32::max(i32::max(s0, s1), s2)) == s1 { - i32::max(s0, s2) - } else { - i32::max(s0, s1) - } - } - 814 => ((s0 as i64) * (s1 as i64) >> 32) as i32, - _ => todo_instr!(instruction)?, - }) as u32 - } - 275 => u32::min(s0, s1), - 276 => u32::max(s0, s1), - 280 => s1 << s0, - 281 => s1 >> s0, - 283 => s0 & s1, - 284 => s0 | s1, - 285 => s0 ^ s1, - 286 => !(s0 ^ s1), - 523 => s0 * s1 + s2, // TODO 24 bit trunc - 528 => (s0 >> s1) & ((1 << s2) - 1), - 530 => (s0 & s1) | (!s0 & s2), - 534 => { - let val = ((s0 as u64) << 32) | (s1 as u64); - let shift = (s2 & 0x1F) as u64; - ((val >> shift) & 0xffffffff) as u32 - } - 542 => u32::max(u32::max(s0, s1), s2), - 576 => s0 ^ s1 ^ s2, - 580 => { - fn byte_permute(data: u64, sel: u32) -> u8 { - let bytes = data.to_ne_bytes(); - match sel { - 13..=u32::MAX => 0xff, - 12 => 0x00, - 11 => ((bytes[7] & 0x80) != 0) as u8 * 0xff, - 10 => ((bytes[5] & 0x80) != 0) as u8 * 0xff, - 9 => ((bytes[3] & 0x80) != 0) as u8 * 0xff, - 8 => ((bytes[1] & 0x80) != 0) as u8 * 0xff, - _ => bytes[sel as usize], - } - } - let combined = ((s0 as u64) << 32) | s1 as u64; - let d0 = ((byte_permute(combined, s2 >> 24) as u32) << 24) - | ((byte_permute(combined, (s2 >> 16) & 0xFF) as u32) << 16) - | ((byte_permute(combined, (s2 >> 8) & 0xFF) as u32) << 8) - | (byte_permute(combined, s2 & 0xFF) as u32); - d0 - } - 581 => (s0 ^ s1) + s2, - 582 => (s0 << s1) + s2, - 583 => (s0 + s1) << s2, - 597 => s0 + s1 + s2, - 598 => (s0 << s1) | s2, - 599 => (s0 & s1) | s2, - 600 => s0 | s1 | s2, - 798 => { - let mut ret = s1; - (0..=31).into_iter().for_each(|i| ret += nth(s0, i)); - ret - } - 812 => s0 * s1, - 813 => ((s0 as u64) * (s1 as u64) >> 32) as u32, - _ => todo_instr!(instruction)?, - } - } - }; - if self.exec.read() { - self.vec_reg[vdst] = ret; - } - } - }; - } - } - } else if let Instruction::DS { op, gds, addr, data0, offset0, data1, offset1, vdst } = decoded { - let _ = self.u64_instr(); - if gds { - return todo_instr!(instruction)?; - } - if !self.exec.read() { - return Ok(()); - } - - let [data0, data1, vdst] = [data0 as usize, data1 as usize, vdst as usize]; - let lds_base = self.vec_reg[addr as usize]; - let single_addr = || (lds_base + u16::from_le_bytes([offset0, offset1]) as u32) as usize; - let double_addr = |adj: u32| { - let addr0 = lds_base + offset0 as u32 * adj; - let addr1 = lds_base + offset1 as u32 * adj; - (addr0 as usize, addr1 as usize) - }; - - match op { - // load - 54 | 118 | 254 | 255 => { - let dwords = match op { - 255 => 4, - 254 => 3, - 118 => 2, - _ => 1, - }; - (0..dwords).for_each(|i| { - self.vec_reg[vdst + i] = self.lds.read(single_addr() + 4 * i); - }); - } - 58 => self.vec_reg[vdst] = self.lds.read(single_addr()) as u8 as u32, - 60 => self.vec_reg[vdst] = self.lds.read(single_addr()) as u16 as u32, - 55 => { - let (addr0, addr1) = double_addr(4); - self.vec_reg[vdst] = self.lds.read(addr0); - self.vec_reg[vdst + 1] = self.lds.read(addr1); - } - 119 => { - let (addr0, addr1) = double_addr(8); - self.vec_reg.write64(vdst, self.lds.read64(addr0)); - self.vec_reg.write64(vdst + 2, self.lds.read64(addr1)); - } - // store - 13 | 77 | 222 | 223 => { - let dwords = match op { - 223 => 4, - 222 => 3, - 77 => 2, - _ => 1, - }; - (0..dwords).for_each(|i| { - self.lds.write(single_addr() + 4 * i, self.vec_reg[data0 + i]); - }) - } - 30 => { - let addr = single_addr(); - if addr + 1 >= self.lds.data.len() { - self.lds.data.resize(self.lds.data.len() + addr + 2, 0); - } - self.lds.data[addr..addr + 1].iter_mut().enumerate().for_each(|(i, x)| { - *x = (self.vec_reg[data0] as u8).to_le_bytes()[i]; - }); - } - 31 | 161 => { - let addr = single_addr(); - if addr + 2 >= self.lds.data.len() { - self.lds.data.resize(self.lds.data.len() + addr + 3, 0); - } - let b32 = self.vec_reg[data0]; - self.lds.data[addr..addr + 2].iter_mut().enumerate().for_each(|(i, x)| { - *x = (if op == 31 { b32 as u16 } else { ((b32 >> 16) & 0xffff) as u16 }).to_le_bytes()[i]; - }); - } - 14 => { - let (addr0, addr1) = double_addr(4); - self.lds.write(addr0, self.vec_reg[data0]); - self.lds.write(addr1, self.vec_reg[data1]); - } - 78 => { - let (addr0, addr1) = double_addr(8); - self.lds.write64(addr0, self.vec_reg.read64(data0)); - self.lds.write64(addr1, self.vec_reg.read64(data1)); - } - _ => todo_instr!(instruction)?, - } - } - // global - // flat - else if instruction >> 26 == 0b110111 { - let instr = self.u64_instr(); - if !self.exec.read() { - return Ok(()); - } - let offset = sign_ext(instr & 0x1fff, 13); - let seg = (instr >> 16) & 0x3; - let op = ((instr >> 18) & 0x7f) as usize; - let addr = ((instr >> 32) & 0xff) as usize; - let data = ((instr >> 40) & 0xff) as usize; - let saddr = ((instr >> 48) & 0x7f) as usize; - let vdst = ((instr >> 56) & 0xff) as usize; - - let saddr_val: u32 = self.val(saddr); - let saddr_off = saddr_val == 0x7F || saddr == NULL_SRC; - - match seg { - 1 => { - let sve = ((instr >> 50) & 0x1) != 0; - - let addr = match (sve, saddr_off) { - (true, true) => offset as u64 as usize, - (false, false) => saddr_val as usize, - _ => todo_instr!(instruction)?, - }; - match op { - // load - 20..=23 => (0..op - 19).for_each(|i| { - self.vec_reg[vdst + i] = self.sds.read(addr + 4 * i); - }), - // store - 26..=29 => (0..op - 25).for_each(|i| { - self.sds.write(addr + 4 * i, self.vec_reg[data + i]); - }), - _ => todo_instr!(instruction)?, - } - } - 2 => { - let addr = match saddr_off { - true => self.vec_reg.read64(addr) as i64 + (offset as i64), - false => { - let scalar_addr = self.scalar_reg.read64(saddr); - let vgpr_offset = self.vec_reg[addr]; - scalar_addr as i64 + vgpr_offset as i64 + offset - } - } as u64; - - unsafe { - match op { - // load - 16 => self.vec_reg[vdst] = *(addr as *const u8) as u32, - 17 => self.vec_reg[vdst] = *(addr as *const i8) as u32, - 18 => self.vec_reg[vdst] = *(addr as *const u16) as u32, - 19 => self.vec_reg[vdst] = *(addr as *const i16) as u32, - - 20..=23 => (0..op - 19).for_each(|i| { - self.vec_reg[vdst + i] = *((addr + 4 * i as u64) as *const u32); - }), - 32 => self.vec_reg[vdst].mut_lo16(*(addr as *const u16)), - 35 => self.vec_reg[vdst].mut_hi16(*(addr as *const u16)), - // store - 24 => *(addr as *mut u8) = self.vec_reg[data] as u8, - 25 => *(addr as *mut u16) = self.vec_reg[data] as u16, - 26..=29 => (0..op - 25).for_each(|i| { - *((addr + 4 * i as u64) as u64 as *mut u32) = self.vec_reg[data + i]; - }), - 37 => *(addr as *mut u16) = ((self.vec_reg[data] >> 16) & 0xffff) as u16, - _ => todo_instr!(instruction)?, - }; - } - } - _ => todo_instr!(instruction)?, - }; - } - // mubuf - else if instruction >> 26 == 0b111000 { - let instr = self.u64_instr(); - let op = ((instr >> 18) & 0x7f) as usize; - match op { - 43 => {} // NOTE: remu doesn't have an l0 cache, it just has the software managed lds - _ => todo_instr!(instruction)?, - }; - } else { - todo_instr!(instruction)?; - } - Ok(()) - } - - fn cmpf(&self, s0: T, s1: T, offset: u32) -> bool - where - T: Float + std::fmt::Display, - { - return match offset { - 0 => true, - 1 => s0 < s1, - 2 => s0 == s1, - 3 => s0 <= s1, - 4 => s0 > s1, - 5 => s0 != s1, - 6 => s0 >= s1, - 7 => (!s0.is_nan()) && (!s1.is_nan()), - 8 => s0.is_nan() || s1.is_nan(), - 9 => !(s0 >= s1), - 10 => !(s0 != s1), - 11 => !(s0 > s1), - 12 => !(s0 <= s1), - 13 => !(s0 == s1), - 14 => !(s0 < s1), - 15 => true, - _ => panic!("invalid offset for float compare {offset}"), - }; - } - fn cmp_class_f64(&self, s0: f64, s1: u32) -> bool { - let offset = match s0 { - _ if s0.is_nan() => 1, - _ if s0.is_infinite() => match s0.signum() == -1.0 { - true => 2, - false => 9, - }, - _ if s0.exponent() > 0 => match s0.signum() == -1.0 { - true => 3, - false => 8, - }, - _ if s0.abs() > 0.0 => match s0.signum() == -1.0 { - true => 4, - false => 7, - }, - _ => match s0.signum() == -1.0 { - true => 5, - false => 6, - }, - }; - ((s1 >> offset) & 1) != 0 - } - fn cmp_class_f32(&self, s0: f32, s1: u32) -> bool { - let offset = match s0 { - _ if (s0 as f64).is_nan() => 1, - _ if s0.exponent() == 255 => match s0.signum() == -1.0 { - true => 2, - false => 9, - }, - _ if s0.exponent() > 0 => match s0.signum() == -1.0 { - true => 3, - false => 8, - }, - _ if s0.abs() as f64 > 0.0 => match s0.signum() == -1.0 { - true => 4, - false => 7, - }, - _ => match s0.signum() == -1.0 { - true => 5, - false => 6, - }, - }; - ((s1 >> offset) & 1) != 0 - } - fn cmp_class_f16(&self, s0: f16, s1: u16) -> bool { - let offset = match s0 { - _ if (f64::from(s0)).is_nan() => 1, - _ if s0.exponent() == 31 => match s0.signum() == f16::NEG_ONE { - true => 2, - false => 9, - }, - _ if s0.exponent() > 0 => match s0.signum() == f16::NEG_ONE { - true => 3, - false => 8, - }, - _ if f64::from(s0.abs()) > 0.0 => match s0.signum() == f16::NEG_ONE { - true => 4, - false => 7, - }, - _ => match s0.signum() == f16::NEG_ONE { - true => 5, - false => 6, - }, - }; - ((s1 >> offset) & 1) != 0 - } - fn cmpi(&self, s0: T, s1: T, offset: u32) -> bool - where - T: PartialOrd + PartialEq, - { - return match offset { - 0 => false, - 1 => s0 < s1, - 2 => s0 == s1, - 3 => s0 <= s1, - 4 => s0 > s1, - 5 => s0 != s1, - 6 => s0 >= s1, - 7 => true, - _ => panic!("invalid offset for integer compare {offset}"), - }; - } - fn cls_i32(&self, s0: u32) -> u32 { - let mut ret: i32 = -1; - let s0 = s0 as i32; - for i in (1..=31).into_iter() { - if s0 >> (31 - i as u32) != s0 >> 31 { - ret = i; - break; - } - } - ret as u32 - } - fn clz_i32_u32(&self, s0: u32) -> u32 { - let mut ret: i32 = -1; - for i in (0..=31).into_iter() { - if s0 >> (31 - i as u32) == 1 { - ret = i; - break; - } - } - ret as u32 - } - - /* ALU utils */ - fn _common_srcs(&mut self, code: usize) -> u32 { - match code { - VCC => self.vcc.value, - 107 => self.scalar_reg[code as usize], - EXEC => self.exec.value, - NULL_SRC | 128 => 0, - 253 => *self.scc as u32, - 255 => match self.simm { - None => { - let val = self.stream[self.pc_offset + 1]; - self.simm = Some(val); - self.pc_offset += 1; - val - } - Some(val) => val, - }, - _ => todo!("resolve_src={code}"), - } - } - fn write_to_sdst(&mut self, sdst_bf: usize, val: u32) { - match sdst_bf { - // NOTE: remu is only wave32, vcc_hi is treated as a regular SGPR - 0..=SGPR_SRC | 107 => self.scalar_reg[sdst_bf] = val, - VCC => self.vcc.value = val, - 126 => self.exec.value = val, - _ => todo!("write to sdst {}", sdst_bf), - } - } - fn set_sgpr_co(&mut self, idx: usize, val: bool) { - let mut wv = self.sgpr_co.map(|(_, wv)| wv).unwrap_or_else(|| WaveValue::new(0, self.warp_size)); - wv.default_lane = self.vcc.default_lane; - wv.set_lane(val); - *self.sgpr_co = Some((idx, wv)); - } - - fn u64_instr(&mut self) -> u64 { - let msb = self.stream[self.pc_offset + 1] as u64; - let instr = msb << 32 | self.stream[self.pc_offset] as u64; - self.pc_offset += 1; - return instr; - } - - fn wmma_b16_16x16(&'a self, vsrc: usize) -> impl Iterator + 'a { - (0..16).flat_map(move |i| { - let lane = self.vec_reg.get_lane(i); - (vsrc..=vsrc + 7).flat_map(move |j| { - let val = lane[j - VGPR_COUNT]; - [(val & 0xffff) as u16, (val >> 16) as u16] - }) - }) - } - - fn wmma_b32_16x16(&'a self, vsrc: usize) -> impl Iterator + 'a { - (0..256).map(move |i| self.vec_reg.get_lane(i % 32)[(i / 32) + vsrc - VGPR_COUNT]) - } -} - -fn wmma(a: Vec, b: Vec, c: Vec) -> [T; 256] { - let mut ret = [T::zero(); 256]; - for row in 0..16 { - for col in 0..16 { - let mut sum = T::zero(); - for k in 0..16 { - let a_val = a[row * 16 + k]; - let b_val = b[col * 16 + k]; - sum = sum + (a_val * b_val); - } - let c_val = c[row * 16 + col]; - ret[row * 16 + col] = sum + c_val; - } - } - ret -} - -pub trait ALUSrc { - fn val(&mut self, code: usize) -> T; -} -impl ALUSrc for Thread<'_> { - fn val(&mut self, code: usize) -> u16 { - match code { - 0..=SGPR_SRC => self.scalar_reg[code] as u16, - VGPR_COUNT..=511 => self.vec_reg[code - VGPR_COUNT] as u16, - 129..=192 => (code - 128) as u16, - 193..=208 => ((code - 192) as i16 * -1) as u16, - 240..=247 => f16::from_f32( - [ - (240, 0.5_f32), - (241, -0.5_f32), - (242, 1_f32), - (243, -1.0_f32), - (244, 2.0_f32), - (245, -2.0_f32), - (246, 4.0_f32), - (247, -4.0_f32), - ] - .iter() - .find(|x| x.0 == code) - .unwrap() - .1, - ) - .to_bits(), - _ => self._common_srcs(code) as u16, - } - } -} -impl ALUSrc for Thread<'_> { - fn val(&mut self, code: usize) -> u32 { - match code { - 0..=SGPR_SRC => self.scalar_reg[code], - VGPR_COUNT..=511 => self.vec_reg[code - VGPR_COUNT], - 129..=192 => (code - 128) as u32, - 193..=208 => ((code - 192) as i32 * -1) as u32, - 240..=247 => [ - (240, 0.5_f32), - (241, -0.5_f32), - (242, 1_f32), - (243, -1.0_f32), - (244, 2.0_f32), - (245, -2.0_f32), - (246, 4.0_f32), - (247, -4.0_f32), - ] - .iter() - .find(|x| x.0 == code) - .unwrap() - .1 - .to_bits(), - _ => self._common_srcs(code), - } - } -} -impl ALUSrc for Thread<'_> { - fn val(&mut self, code: usize) -> u64 { - match code { - 0..=SGPR_SRC => self.scalar_reg.read64(code), - VGPR_COUNT..=511 => self.vec_reg.read64(code - VGPR_COUNT), - 129..=192 => (code - 128) as u64, - 193..=208 => ((code - 192) as i64 * -1) as u64, - 240..=247 => [ - (240, 0.5_f64), - (241, -0.5_f64), - (242, 1_f64), - (243, -1.0_f64), - (244, 2.0_f64), - (245, -2.0_f64), - (246, 4.0_f64), - (247, -4.0_f64), - ] - .iter() - .find(|x| x.0 == code) - .unwrap() - .1 - .to_bits(), - _ => self._common_srcs(code) as u64, - } - } -} -impl ALUSrc for Thread<'_> { - fn val(&mut self, code: usize) -> f64 { - let uret: u64 = self.val(code); - match code { - SIMM_SRC => f64::from_bits(uret << 32), - _ => f64::from_bits(uret), - } - } -} - -#[cfg(test)] -mod test_alu_utils { - use super::*; - - #[test] - fn test_write_to_sdst_sgpr() { - let mut thread = _helper_test_thread(); - thread.write_to_sdst(10, 200); - assert_eq!(thread.scalar_reg[10], 200); - } - - #[test] - fn test_write_to_sdst_vcc_val() { - let mut thread = _helper_test_thread(); - let val = 0b1011101011011011111011101111; - thread.write_to_sdst(VCC, val); - assert_eq!(thread.vcc.value, 195935983); - } - - #[test] - fn test_clz_i32_u32() { - let thread = _helper_test_thread(); - assert_eq!(thread.clz_i32_u32(0x00000000), 0xffffffff); - assert_eq!(thread.clz_i32_u32(0x0000cccc), 16); - assert_eq!(thread.clz_i32_u32(0xffff3333), 0); - assert_eq!(thread.clz_i32_u32(0x7fffffff), 1); - assert_eq!(thread.clz_i32_u32(0x80000000), 0); - assert_eq!(thread.clz_i32_u32(0xffffffff), 0); - } - - #[test] - fn test_cls_i32() { - let thread = _helper_test_thread(); - assert_eq!(thread.cls_i32(0x00000000), 0xffffffff); - assert_eq!(thread.cls_i32(0x0000cccc), 16); - assert_eq!(thread.cls_i32(0xffff3333), 16); - assert_eq!(thread.cls_i32(0x7fffffff), 1); - assert_eq!(thread.cls_i32(0x80000000), 1); - } - - #[test] - fn test_sgpr_co_init() { - let mut thread = _helper_test_thread(); - thread.vcc.default_lane = Some(0); - thread.set_sgpr_co(10, true); - thread.vcc.default_lane = Some(1); - assert_eq!(thread.sgpr_co.unwrap().0, 10); - assert_eq!(thread.sgpr_co.unwrap().1.mutations.unwrap()[0], true); - thread.set_sgpr_co(10, true); - assert_eq!(thread.sgpr_co.unwrap().0, 10); - assert_eq!(thread.sgpr_co.unwrap().1.mutations.unwrap()[1], true); - assert_eq!(thread.sgpr_co.unwrap().1.mutations.unwrap()[0], true); - } -} - -#[cfg(test)] -mod test_smem { - use super::*; - - #[test] - fn test_s_load_b32_simple() { - let mut thread = _helper_test_thread(); - let mut buf = vec![0u8; 4]; - let a: u32 = 0xDEADBEEF; - unsafe { - *(buf.as_mut_ptr() as *mut u32) = a; - } - let base_addr = buf.as_ptr() as u64; - thread.scalar_reg.write64(0, base_addr); - r(&vec![0xF4000040, 0xF8000000, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[1], a); - std::mem::forget(buf); - } - - #[test] - fn test_s_load_b32_vcc() { - let mut thread = _helper_test_thread(); - let mut buf = vec![0u8; 4]; - let a: u32 = 0xDEADBEEF; - unsafe { - *(buf.as_mut_ptr() as *mut u32) = a; - } - let base_addr = buf.as_ptr() as u64; - thread.scalar_reg.write64(0, base_addr); - r(&vec![0xF4001A80, 0xF8000000, END_PRG], &mut thread); - assert_eq!(thread.vcc.value, a); - std::mem::forget(buf); - } - - #[test] - fn test_s_load_b32_vcc_addr() { - let mut thread = _helper_test_thread(); - let mut buf = vec![0u8; 4]; - let a: u32 = 0xDEADBEEF; - unsafe { - *(buf.as_mut_ptr() as *mut u32) = a; - } - let addr = buf.as_ptr() as u64; - // NOTE: vcc is an alias for s[106:107] - thread.scalar_reg.write64(VCC, addr); - // TODO: vcc_lo should just read from s106 - thread.vcc.value = (addr & 0xffffffff) as u32; - r(&vec![0xF4000035, 0xF8000000, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[0], a); - std::mem::forget(buf); - } -} - -#[cfg(test)] -mod test_sop1 { - use super::*; - - #[test] - fn test_s_brev_b32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[5] = 8; - r(&vec![0xBE850405, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[5], 268435456); - } - - #[test] - fn test_s_mov_b64() { - let mut thread = _helper_test_thread(); - thread.scalar_reg.write64(16, 5236523008); - r(&vec![0xBE880110, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg.read64(8), 5236523008); - assert_eq!(thread.scalar, true); - } - - #[test] - fn test_mov_exec() { - let mut thread = _helper_test_thread(); - thread.exec.value = 0b11111111110111111110111111111111; - r(&vec![0xBE80007E, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[0], 0b11111111110111111110111111111111); - } - - #[test] - fn test_s_mov_b32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[15] = 42; - r(&vec![0xbe82000f, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[2], 42); - } - - #[test] - fn test_s_bitset0_b32() { - [ - [ - 0b11111111111111111111111111111111, - 0b00000000000000000000000000000001, - 0b11111111111111111111111111111101, - ], - [ - 0b11111111111111111111111111111111, - 0b00000000000000000000000000000010, - 0b11111111111111111111111111111011, - ], - ] - .iter() - .for_each(|[a, b, ret]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[20] = *a; - thread.scalar_reg[10] = *b; - r(&vec![0xBE94100A, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[20], *ret); - }); - } - - #[test] - fn test_s_bitset1_b32() { - [ - [ - 0b00000000000000000000000000000000, - 0b00000000000000000000000000000001, - 0b00000000000000000000000000000010, - ], - [ - 0b00000000000000000000000000000000, - 0b00000000000000000000000000000010, - 0b00000000000000000000000000000100, - ], - ] - .iter() - .for_each(|[a, b, ret]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[20] = *a; - thread.scalar_reg[10] = *b; - r(&vec![0xbe94120a, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[20], *ret); - }); - } - - #[test] - fn test_s_not_b32() { - [[0, 4294967295, 1], [1, 4294967294, 1], [u32::MAX, 0, 0]] - .iter() - .for_each(|[a, ret, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[10] = *a; - r(&vec![0xBE8A1E0A, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[10], *ret); - assert_eq!(*thread.scc, *scc); - }); - } -} - -#[cfg(test)] -mod test_sopk { - use super::*; - - #[test] - fn test_cmp_zero_extend() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[20] = 0xcd14; - r(&vec![0xB494CD14, END_PRG], &mut thread); - assert_eq!(*thread.scc, 1); - - r(&vec![0xB194CD14, END_PRG], &mut thread); - assert_eq!(*thread.scc, 0); - } - - #[test] - fn test_cmp_sign_extend() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[6] = 0x2db4; - r(&vec![0xB1862DB4, END_PRG], &mut thread); - assert_eq!(*thread.scc, 1); - - r(&vec![0xB1862DB4, END_PRG], &mut thread); - assert_eq!(*thread.scc, 1); - } -} - -#[cfg(test)] -mod test_sop2 { - use super::*; - - #[test] - fn test_xor_exec() { - let mut thread = _helper_test_thread(); - thread.exec.value = 0b10010010010010010010010010010010; - thread.scalar_reg[2] = 0b11111111111111111111111111111111; - r(&vec![0x8D02027E, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[2], 1840700269); - } - - #[test] - fn test_s_add_u32() { - [[10, 20, 30, 0], [u32::MAX, 10, 9, 1], [u32::MAX, 0, u32::MAX, 0]] - .iter() - .for_each(|[a, b, expected, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = *a; - thread.scalar_reg[6] = *b; - r(&vec![0x80060206, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[6], *expected); - assert_eq!(*thread.scc, *scc); - }); - } - - #[test] - fn test_s_addc_u32() { - [[10, 20, 31, 1, 0], [10, 20, 30, 0, 0], [u32::MAX, 10, 10, 1, 1]] - .iter() - .for_each(|[a, b, expected, scc_before, scc_after]| { - let mut thread = _helper_test_thread(); - *thread.scc = *scc_before; - thread.scalar_reg[7] = *a; - thread.scalar_reg[3] = *b; - r(&vec![0x82070307, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[7], *expected); - assert_eq!(*thread.scc, *scc_after); - }); - } - - #[test] - fn test_s_add_i32() { - [[-10, 20, 10, 0], [i32::MAX, 1, -2147483648, 1]] - .iter() - .for_each(|[a, b, expected, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[14] = *a as u32; - thread.scalar_reg[10] = *b as u32; - r(&vec![0x81060E0A, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[6], *expected as u32); - assert_eq!(*thread.scc, *scc as u32); - }); - } - - #[test] - fn test_s_sub_i32() { - [[-10, 20, -30, 0], [i32::MAX, -1, -2147483648, 1]] - .iter() - .for_each(|[a, b, expected, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[13] = *a as u32; - thread.scalar_reg[8] = *b as u32; - r(&vec![0x818C080D, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[12], *expected as u32); - assert_eq!(*thread.scc, *scc as u32); - }); - } - - #[test] - fn test_s_lshl_b32() { - [[20, 40, 1], [0, 0, 0]].iter().for_each(|[a, expected, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[15] = *a as u32; - r(&vec![0x8408810F, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[8], *expected as u32); - assert_eq!(*thread.scc, *scc as u32); - }); - } - - #[test] - fn test_s_lshl_b64() { - let mut thread = _helper_test_thread(); - thread.scalar_reg.write64(2, u64::MAX - 30); - r(&vec![0x84828202, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[2], 4294967172); - assert_eq!(thread.scalar_reg[3], 4294967295); - assert_eq!(*thread.scc, 1); - } - - #[test] - fn test_s_ashr_i32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = 36855; - r(&vec![0x86039F02, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 0); - assert_eq!(*thread.scc, 0); - } - - #[test] - fn test_source_vcc() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[10] = 0x55; - thread.vcc.value = 29; - r(&vec![0x8B140A6A, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[20], 21); - } - - #[test] - fn test_s_min_i32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = -42i32 as u32; - thread.scalar_reg[3] = -92i32 as u32; - r(&vec![0x89020203, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[2], -92i32 as u32); - assert_eq!(*thread.scc, 1); - } - - #[test] - fn test_s_mul_hi_u32() { - [[u32::MAX, 10, 9], [u32::MAX / 2, 4, 1]].iter().for_each(|[a, b, expected]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = *a; - thread.scalar_reg[8] = *b; - r(&vec![0x96810800, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[1], *expected); - }); - } - - #[test] - fn test_s_mul_hi_i32() { - [[(u64::MAX) as i32, (u64::MAX / 2) as i32, 0], [2, -2, -1]] - .iter() - .for_each(|[a, b, expected]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = *a as u32; - thread.scalar_reg[8] = *b as u32; - r(&vec![0x97010800, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[1], *expected as u32); - }); - } - - #[test] - fn test_s_mul_i32() { - [[40, 2, 80], [-10, -10, 100]].iter().for_each(|[a, b, expected]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = *a as u32; - thread.scalar_reg[6] = *b as u32; - r(&vec![0x96000600, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[0], *expected as u32); - }); - } - - #[test] - fn test_s_bfe_u64() { - [[2, 4, 2, 0], [800, 400, 32, 0], [-10i32 as u32, 3, 246, 0], [u32::MAX, u32::MAX, 255, 0]] - .iter() - .for_each(|[a_lo, a_hi, ret_lo, ret_hi]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[6] = *a_lo; - thread.scalar_reg[7] = *a_hi; - r(&vec![0x940cff06, 524288, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[12], *ret_lo); - assert_eq!(thread.scalar_reg[13], *ret_hi); - }); - } - - #[test] - fn test_s_bfe_i64() { - [[131073, 0, 1, 0, 0x100000], [-2, 0, -2, -1, 524288], [2, 0, 2, 0, 524288]] - .iter() - .for_each(|[a_lo, a_hi, ret_lo, ret_hi, shift]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[6] = *a_lo as u32; - thread.scalar_reg[7] = *a_hi as u32; - r(&vec![0x948cff06, *shift as u32, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[12], *ret_lo as u32); - assert_eq!(thread.scalar_reg[13], *ret_hi as u32); - }); - } - - #[test] - fn test_s_bfe_u32() { - [ - [67305985, 2], - [0b100000000110111111100000001, 0b1111111], - [0b100000000100000000000000001, 0b0], - [0b100000000111000000000000001, 0b10000000], - [0b100000000111111111100000001, 0b11111111], - ] - .iter() - .for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = *a; - r(&vec![0x9303FF00, 0x00080008, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], *ret); - }); - } - - #[test] - fn test_s_pack_xx_b32_b16() { - let mut thread = _helper_test_thread(); - // ll - thread.scalar_reg[0] = 0x12345678; - r(&vec![0x9903ff00, 0x9ABCDEF0, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 0xdef05678); - // lh - r(&vec![0x9983ff00, 0x9ABCDEF0, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 0x9abc5678); - // hh - r(&vec![0x9a03ff00, 0x9ABCDEF0, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 2596016692); - // hl - r(&vec![0x9a83ff00, 0x9ABCDEF0, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 3740275252); - } -} - -#[cfg(test)] -mod test_sopc { - use super::*; - - #[test] - fn test_s_bitcmp0_b32() { - [[0b00, 0b1, 0], [0b01, 0b1, 1], [0b10, 0b1, 1], [0b10000000, 0b1, 0]] - .iter() - .for_each(|[s0, s1, scc]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[3] = *s0; - thread.scalar_reg[4] = *s1; - r(&vec![0xBF0C0304, END_PRG], &mut thread); - assert_eq!(*thread.scc, *scc); - }) - } -} - -#[cfg(test)] -mod test_vopd { - use super::*; - - #[test] - fn test_inline_const_vopx_only() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = f32::to_bits(0.5); - let constant = f32::from_bits(0x39a8b099); - thread.vec_reg[1] = 10; - r(&vec![0xC8D000FF, 0x00000080, 0x39A8B099, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 0.5 * constant); - assert_eq!(thread.vec_reg[1], 0); - } - - #[test] - fn test_inline_const_vopy_only() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 10; - thread.vec_reg[1] = 10; - r(&vec![0xCA100080, 0x000000FF, 0x3E15F480, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 0); - assert_eq!(thread.vec_reg[1], 0x3e15f480); - - let mut thread = _helper_test_thread(); - thread.vec_reg[18] = f32::to_bits(2.0); - thread.vec_reg[32] = f32::to_bits(4.0); - thread.vec_reg[7] = 10; - r(&vec![0xC9204112, 0x00060EFF, 0x0000006E, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 2.0f32 + 4.0f32); - assert_eq!(thread.vec_reg[7], 120); - } - - #[test] - fn test_inline_const_shared() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = f32::to_bits(2.0); - thread.vec_reg[3] = f32::to_bits(4.0); - let constant = f32::from_bits(0x3e800000); - r(&vec![0xC8C604FF, 0x020206FF, 0x3E800000, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[2]), 2.0 * constant); - assert_eq!(f32::from_bits(thread.vec_reg[3]), 4.0 * constant); - } - - #[test] - fn test_simm_op_shared_1() { - let mut thread = _helper_test_thread(); - thread.vec_reg[23] = f32::to_bits(4.0); - thread.vec_reg[12] = f32::to_bits(2.0); - - thread.vec_reg[13] = f32::to_bits(10.0); - thread.vec_reg[24] = f32::to_bits(3.0); - - let simm = f32::from_bits(0x3e000000); - r(&vec![0xC8841917, 0x0C0C1B18, 0x3E000000, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[12]), 4.0 * simm + 2.0); - assert_eq!(f32::from_bits(thread.vec_reg[13]), 3.0 * simm + 10.0); - } - - #[test] - fn test_simm_op_shared_2() { - let mut thread = _helper_test_thread(); - thread.vec_reg[29] = f32::to_bits(4.0); - thread.vec_reg[10] = f32::to_bits(2.0); - - thread.vec_reg[11] = f32::to_bits(10.0); - thread.vec_reg[26] = f32::to_bits(6.5); - - let simm = 0.125; - r(&vec![0xC880151D, 0x0A0A34FF, 0x3E000000, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[10]), 4.0 * simm + 2.0); - assert_eq!(f32::from_bits(thread.vec_reg[11]), simm * 6.5 + 10.0); - } - - #[test] - fn test_add_mov() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = f32::to_bits(10.5); - r(&vec![0xC9100300, 0x00000080, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 10.5); - assert_eq!(thread.vec_reg[1], 0); - } - - #[test] - fn test_max_add() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = f32::to_bits(5.0); - thread.vec_reg[3] = f32::to_bits(2.0); - thread.vec_reg[1] = f32::to_bits(2.0); - r(&vec![0xCA880280, 0x01000700, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 7.0); - assert_eq!(f32::from_bits(thread.vec_reg[1]), 2.0); - } -} -#[cfg(test)] -mod test_vop1 { - use super::*; - use float_cmp::approx_eq; - - #[test] - fn test_v_cvt_f32_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, 2.0f64.to_bits()); - r(&vec![0xD58F0101, 0x00000100, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[1]), 2.0); - thread.vec_reg.write64(0, (-2.0f64).to_bits()); - r(&vec![0xD58F0101, 0x00000100, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[1]), 2.0); - } - - #[test] - fn test_v_mov_b32_srrc_const0() { - let mut thread = _helper_test_thread(); - r(&vec![0x7e000280, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 0); - r(&vec![0x7e020280, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 0); - r(&vec![0x7e040280, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 0); - } - - #[test] - fn test_v_mov_b32_srrc_register() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[6] = 31; - r(&vec![0x7e020206, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 31); - } - - fn helper_test_fexp(val: f32) -> f32 { - let mut thread = _helper_test_thread(); - thread.vec_reg[6] = val.to_bits(); - r(&vec![0x7E0C4B06, END_PRG], &mut thread); - f32::from_bits(thread.vec_reg[6]) - } - - #[test] - fn test_fexp_1ulp() { - let test_values = [-2.0, -1.0, 0.0, 1.0, 2.0, 3.0]; - for &val in test_values.iter() { - let expected = (2.0_f32).powf(val); - assert!((helper_test_fexp(val) - expected).abs() <= f32::EPSILON); - } - } - - #[test] - fn test_fexp_flush_denormals() { - assert_eq!(helper_test_fexp(f32::from_bits(0xff800000)), 0.0); - assert_eq!(helper_test_fexp(f32::from_bits(0x80000000)), 1.0); - assert_eq!(helper_test_fexp(f32::from_bits(0x7f800000)), f32::from_bits(0x7f800000)); - } - - #[test] - fn test_cast_f32_i32() { - let mut thread = _helper_test_thread(); - [(10.42, 10i32), (-20.08, -20i32)].iter().for_each(|(src, expected)| { - thread.scalar_reg[2] = f32::to_bits(*src); - r(&vec![0x7E001002, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0] as i32, *expected); - }) - } - - #[test] - fn test_cast_f32_u32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[4] = 2; - r(&vec![0x7E000C04, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 1073741824); - } - - #[test] - fn test_cast_u32_f32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 1325400062; - r(&vec![0x7E000F00, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 2147483392); - } - - #[test] - fn test_cast_i32_f32() { - let mut thread = _helper_test_thread(); - [(10.0, 10i32), (-20.0, -20i32)].iter().for_each(|(expected, src)| { - thread.vec_reg[0] = *src as u32; - r(&vec![0x7E000B00, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), *expected); - }) - } - - #[test] - fn test_v_readfirstlane_b32_basic() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 2147483392; - r(&vec![0x7E060500, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], 2147483392); - } - - #[test] - fn test_v_readfirstlane_b32_fancy() { - let mut thread = _helper_test_thread(); - thread.vec_reg.get_lane_mut(0)[13] = 44; - thread.vec_reg.get_lane_mut(1)[13] = 22; - thread.exec.value = 0b00000000000000000000000000000010; - thread.exec.default_lane = Some(2); - r(&vec![0x7E1A050D, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[13], 22); - - thread.exec.value = 0b00000000000000000000000000000000; - thread.exec.default_lane = Some(1); - r(&vec![0x7E1A050D, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[13], 44); - - thread.exec.value = 0b10000000000000000000000000000000; - thread.vec_reg.get_lane_mut(31)[13] = 88; - thread.exec.default_lane = Some(1); - r(&vec![0x7E1A050D, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[13], 88); - } - - #[test] - fn test_v_cls_i32() { - fn t(val: u32) -> u32 { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = val; - r(&vec![0x7E087702, END_PRG], &mut thread); - return thread.vec_reg[4]; - } - - assert_eq!(t(0x00000000), 0xffffffff); - assert_eq!(t(0x40000000), 1); - assert_eq!(t(0x80000000), 1); - assert_eq!(t(0x0fffffff), 4); - assert_eq!(t(0xffff0000), 16); - assert_eq!(t(0xfffffffe), 31); - } - - #[test] - fn test_v_rndne_f32() { - [ - [1.2344, 1.0], - [2.3, 2.0], // [0.5f32, 0.0f32], - [0.51, 1.0], - [f32::from_bits(1186963295), f32::from_bits(1186963456)], - ] - .iter() - .for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = f32::to_bits(*a); - r(&vec![0x7E024700, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[1]), *ret); - }) - } - - #[test] - fn test_v_rndne_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0x652b82fe; - thread.vec_reg[1] = 0x40071547; - r(&vec![0x7E043300, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 0); - assert_eq!(thread.vec_reg[3], 1074266112); - } - - #[test] - fn test_v_cvt_i32_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = 0; - thread.vec_reg[3] = 0x40080000; - r(&vec![0x7E080702, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 3); - } - - #[test] - fn test_v_frexp_mant_f64() { - [[2.0, 0.5], [1.0, 0.5], [0.54, 0.54], [f64::NAN, f64::NAN]] - .iter() - .for_each(|[x, expected]| { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, f64::to_bits(*x)); - r(&vec![0x7E047B00, END_PRG], &mut thread); - let ret = f64::from_bits(thread.vec_reg.read64(2)); - if ret.is_nan() { - assert!(ret.is_nan() && expected.is_nan()); - } else { - assert_eq!(f64::from_bits(thread.vec_reg.read64(2)), *expected) - } - }) - } - - #[test] - fn test_v_rcp_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0; - thread.vec_reg[1] = 1073741824; - r(&vec![0x7E045F00, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 0); - assert_eq!(thread.vec_reg[3], 1071644672); - } - - #[test] - fn test_v_frexp_exp_i32_f64() { - [(3573412790272.0, 42), (69.0, 7), (2.0, 2), (f64::NEG_INFINITY, 0)] - .iter() - .for_each(|(x, ret)| { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, f64::to_bits(*x)); - r(&vec![0x7E047900, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], *ret); - }) - } - - #[test] - fn test_v_rsq_f64() { - [(2.0, 0.707)].iter().for_each(|(x, ret)| { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, f64::to_bits(*x)); - println!("{} {}", thread.vec_reg[0], thread.vec_reg[1]); - r(&vec![0x7E046300, END_PRG], &mut thread); - assert!(approx_eq!(f64, f64::from_bits(thread.vec_reg.read64(2)), *ret, (0.01, 2))); - }) - } -} - -#[cfg(test)] -mod test_vopc { - use super::*; - - #[test] - fn test_v_cmp_gt_i32() { - let mut thread = _helper_test_thread(); - - thread.vec_reg[1] = (4_i32 * -1) as u32; - r(&vec![0x7c8802c1, END_PRG], &mut thread); - assert_eq!(thread.vcc.read(), true); - - thread.vec_reg[1] = 4; - r(&vec![0x7c8802c1, END_PRG], &mut thread); - assert_eq!(thread.vcc.read(), false); - } - - #[test] - fn test_v_cmpx_nlt_f32() { - let mut thread = _helper_test_thread(); - thread.exec.value = 0b010011; - thread.vec_reg[0] = f32::to_bits(0.9); - thread.vec_reg[3] = f32::to_bits(0.4); - r(&vec![0x7D3C0700, END_PRG], &mut thread); - assert_eq!(thread.exec.read(), true); - } - - #[test] - fn test_v_cmpx_gt_i32_e32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[3] = 100; - r(&vec![0x7D8806FF, 0x00000041, END_PRG], &mut thread); - assert_eq!(thread.exec.read(), false); - - thread.vec_reg[3] = -20i32 as u32; - r(&vec![0x7D8806FF, 0x00000041, END_PRG], &mut thread); - assert_eq!(thread.exec.read(), true); - } - - #[test] - fn test_cmp_class_f32() { - let thread = _helper_test_thread(); - assert!(!thread.cmp_class_f32(f32::NAN, 0b00001)); - assert!(thread.cmp_class_f32(f32::NAN, 0b00010)); - - assert!(thread.cmp_class_f32(f32::INFINITY, 0b00000000000000000000001000000000)); - assert!(!thread.cmp_class_f32(f32::INFINITY, 0b00000000000000000000000000000010)); - - assert!(thread.cmp_class_f32(f32::NEG_INFINITY, 0b00000000000000000000000000000100)); - assert!(!thread.cmp_class_f32(f32::NEG_INFINITY, 0b00000000000000000000010000000000)); - - assert!(!thread.cmp_class_f32(0.752, 0b00000000000000000000000000000000)); - assert!(thread.cmp_class_f32(0.752, 0b00000000000000000000000100000000)); - - assert!(!thread.cmp_class_f32(-0.752, 0b00000000000000000000010000000000)); - assert!(thread.cmp_class_f32(-0.752, 0b00000000000000000000010000001000)); - - assert!(!thread.cmp_class_f32(1.0e-42, 0b11111111111111111111111101111111)); - assert!(thread.cmp_class_f32(1.0e-42, 0b00000000000000000000000010000000)); - - assert!(thread.cmp_class_f32(-1.0e-42, 0b00000000000000000000000000010000)); - assert!(!thread.cmp_class_f32(-1.0e-42, 0b11111111111111111111111111101111)); - - assert!(thread.cmp_class_f32(-0.0, 0b00000000000000000000000000100000)); - assert!(thread.cmp_class_f32(0.0, 0b00000000000000000000000001000000)); - } - - #[test] - fn test_cmp_class_f64() { - let thread = _helper_test_thread(); - - assert!(!thread.cmp_class_f64(f64::NAN, 0b00001)); - assert!(thread.cmp_class_f64(f64::NAN, 0b00010)); - - assert!(thread.cmp_class_f64(f64::INFINITY, 0b00000000000000000000001000000000)); - assert!(!thread.cmp_class_f64(f64::INFINITY, 0b00000000000000000000000000000010)); - - assert!(thread.cmp_class_f64(f64::NEG_INFINITY, 0b00000000000000000000000000000100)); - assert!(!thread.cmp_class_f64(f64::NEG_INFINITY, 0b00000000000000000000010000000000)); - - assert!(!thread.cmp_class_f64(0.752, 0b00000000000000000000000000000000)); - assert!(thread.cmp_class_f64(0.752, 0b00000000000000000000000100000000)); - - assert!(!thread.cmp_class_f64(-1.0e-42, 0b00000000000000000000000000010000)); - assert!(thread.cmp_class_f64(-1.0e-42, 0b11111111111111111111111111101111)); - - assert!(thread.cmp_class_f64(-0.0, 0b00000000000000000000000000100000)); - assert!(thread.cmp_class_f64(0.0, 0b00000000000000000000000001000000)); - } -} -#[cfg(test)] -mod test_vop2 { - use super::*; - - #[test] - fn test_v_add_f32_e32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = f32::to_bits(42.0); - thread.vec_reg[0] = f32::to_bits(1.0); - r(&vec![0x06000002, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 43.0); - } - - #[test] - fn test_v_and_b32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[10] = 15; - r(&vec![0x36141482, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[10], 2); - } - - #[test] - fn test_v_mul_f32_e32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = f32::to_bits(21.0); - thread.vec_reg[4] = f32::to_bits(2.0); - r(&vec![0x10060504, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[3]), 42.0); - } - - #[test] - fn test_v_ashrrev_i32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 4294967295; - r(&vec![0x3402009F, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1] as i32, -1); - } - - #[test] - fn test_v_mul_i32_i24() { - [ - [18, 0x64, 1800], - [0b10000000000000000000000000, 0b1, 0], - [0b100000000000000000000000, 0b1, 0b11111111100000000000000000000000], - ] - .iter() - .for_each(|[a, b, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = *a; - r(&vec![0x124E02FF, *b, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[39], *ret); - }); - } - - #[test] - fn test_v_add_nc_u32_const() { - let mut thread = _helper_test_thread(); - thread.vec_reg[18] = 7; - r(&vec![0x4A3024B8, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[24], 63); - } - - #[test] - fn test_v_add_nc_u32_sint() { - let mut thread = _helper_test_thread(); - thread.vec_reg[14] = 7; - thread.vec_reg[6] = 4294967279; - r(&vec![0x4A0C1D06, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[6], 4294967286); - } -} - -#[cfg(test)] -mod test_vopsd { - use super::*; - - #[test] - fn test_v_add_co_u32_scalar_co_zero() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[10] = 0; - thread.vcc.default_lane = Some(1); - thread.vec_reg.default_lane = Some(1); - thread.vec_reg[10] = u32::MAX; - thread.vec_reg[20] = 20; - r(&vec![0xD7000A0A, 0x0002290A, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[10], 19); - assert_eq!(thread.scalar_reg[10], 2); - } - - #[test] - fn test_v_add_co_u32_scalar_co_override() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[10] = 0b11111111111111111111111111111111; - thread.vcc.default_lane = Some(2); - thread.vec_reg.default_lane = Some(2); - thread.vec_reg[10] = u32::MAX; - thread.vec_reg[20] = 20; - r(&vec![0xD7000A0A, 0x0002290A, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[10], 19); - // NOTE: the co mask only writes to the bit that it needs to write, then at the _wave_ - // level, the final result accumulates - assert_eq!(thread.scalar_reg[10], 0b100); - } - - #[test] - fn test_v_add_co_ci_u32() { - [[0, 0, 0b0], [1, -1i32 as usize, 0b10]].iter().for_each(|[lane_id, result, carry_out]| { - let mut thread = _helper_test_thread(); - thread.vcc.default_lane = Some(*lane_id); - thread.vec_reg.default_lane = Some(*lane_id); - thread.scalar_reg[20] = 0b10; - thread.vec_reg[1] = 2; - thread.vec_reg[2] = 2; - r(&vec![0xD5211401, 0x00520501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], *result as u32); - assert_eq!(thread.scalar_reg[20], *carry_out as u32); - }) - } - - #[test] - fn test_v_sub_co_ci_u32() { - [[3, 2, 0b1000], [2, 0, 0b100]].iter().for_each(|[lane_id, result, carry_out]| { - let mut thread = _helper_test_thread(); - thread.vcc.default_lane = Some(*lane_id); - thread.vec_reg.default_lane = Some(*lane_id); - thread.scalar_reg[20] = 0b1010; - thread.vec_reg[1] = *lane_id as u32; - thread.vec_reg[2] = u32::MAX - 1; - r(&vec![0xD5201401, 0x00520501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], *result as u32); - assert_eq!(thread.scalar_reg[20], *carry_out as u32); - }) - } - - #[test] - fn test_v_mad_u64_u32() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(3, u64::MAX - 3); - thread.scalar_reg[13] = 3; - thread.scalar_reg[10] = 1; - r(&vec![0xD6FE0D06, 0x040C140D, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.read64(6), u64::MAX); - assert_eq!(thread.scalar_reg[13], 0); - - thread.vec_reg.write64(3, u64::MAX - 3); - thread.scalar_reg[13] = 4; - thread.scalar_reg[10] = 1; - r(&vec![0xD6FE0D06, 0x040C140D, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[6], 0); - assert_eq!(thread.vec_reg[7], 0); - assert_eq!(thread.scalar_reg[13], 1); - } - - #[test] - fn test_v_add_co_u32() { - let mut thread = _helper_test_thread(); - thread.vcc.default_lane = Some(1); - thread.vec_reg[2] = u32::MAX; - thread.vec_reg[3] = 3; - r(&vec![0xD7000D02, 0x00020503, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 2); - assert_eq!(thread.scalar_reg[13], 0b10); - } - - #[test] - fn test_v_sub_co_u32() { - [[69, 0, 69, 0], [100, 200, 4294967196, 1]].iter().for_each(|[a, b, ret, scc]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[4] = *a; - thread.vec_reg[15] = *b; - r(&vec![0xD7016A04, 0x00021F04, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], *ret); - assert_eq!(thread.vcc.read(), *scc != 0); - }) - } - - #[test] - fn test_return_value_exec_zero() { - let mut thread = _helper_test_thread(); - thread.exec.value = 0b11111111111111111111111111111101; - thread.vcc.default_lane = Some(1); - thread.exec.default_lane = Some(1); - thread.vec_reg[2] = u32::MAX; - thread.vec_reg[3] = 3; - r(&vec![0xD7000D02, 0x00020503, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], u32::MAX); - assert_eq!(thread.scalar_reg[13], 0b10); - } - - #[test] - fn test_v_div_scale_f64() { - let mut thread = _helper_test_thread(); - let v = -0.41614683654714246; - thread.vec_reg.write64(0, f64::to_bits(v)); - thread.vec_reg.write64(2, f64::to_bits(v)); - thread.vec_reg.write64(4, f64::to_bits(0.909)); - r(&vec![0xD6FD7C06, 0x04120500, END_PRG], &mut thread); - thread.vec_reg[6] = 1465086470; - thread.vec_reg[7] = 3218776614; - let ret = f64::from_bits(thread.vec_reg.read64(6)); - assert_eq!(ret, v); - } -} - -#[cfg(test)] -mod test_vop3 { - use super::*; - use float_cmp::approx_eq; - - fn helper_test_vop3(op: u32, a: f32, b: f32) -> f32 { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = f32::to_bits(a); - thread.scalar_reg[6] = f32::to_bits(b); - r(&vec![op, 0x00000006, END_PRG], &mut thread); - return f32::from_bits(thread.vec_reg[0]); - } - - #[test] - fn test_v_add_f32() { - assert_eq!(helper_test_vop3(0xd5030000, 0.4, 0.2), 0.6); - } - - #[test] - fn test_v_mul_f16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1].mut_lo16(f16::from_f32(2.0).to_bits()); - thread.vec_reg[2].mut_lo16(f16::from_f32(4.0).to_bits()); - r(&vec![0xD5350000, 0x00020501, END_PRG], &mut thread); - assert_eq!(f16::from_bits(thread.vec_reg[0] as u16), f16::from_f32(8.0)); - } - - #[test] - fn test_v_max_f32() { - assert_eq!(helper_test_vop3(0xd5100000, 0.4, 0.2), 0.4); - assert_eq!(helper_test_vop3(0xd5100000, 0.2, 0.8), 0.8); - } - - #[test] - fn test_v_mul_f32() { - assert_eq!(helper_test_vop3(0xd5080000, 0.4, 0.2), 0.4 * 0.2); - } - - #[test] - fn test_signed_src() { - // v0, max(s2, s2) - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = f32::to_bits(0.5); - r(&vec![0xd5100000, 0x00000402, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 0.5); - - // v1, max(-s2, -s2) - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = f32::to_bits(0.5); - r(&vec![0xd5100001, 0x60000402, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[1]), -0.5); - } - - #[test] - fn test_cnd_mask_cond_src_sgpr() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[3] = 0b001; - r(&vec![0xD5010000, 0x000D0280, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 1); - - thread.scalar_reg[3] = 0b00; - r(&vec![0xD5010000, 0x000D0280, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 0); - } - - #[test] - fn test_cnd_mask_cond_src_vcclo() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = 20; - thread.vec_reg[0] = 100; - r(&vec![0xD5010002, 0x41AA0102, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 20); - } - - #[test] - fn test_cnd_mask_float_const() { - let mut thread = _helper_test_thread(); - thread.vcc.value = 0b00000010; - thread.vcc.default_lane = Some(0); - r(&vec![0xD5010003, 0x01A9E480, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3], 0); - - thread.vcc.value = 0b00000010; - thread.vcc.default_lane = Some(1); - r(&vec![0xD5010003, 0x01A9E480, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[3]), 1.0); - } - - #[test] - fn test_v_cndmask_b32_e64_neg() { - [[0.0f32, -0.0], [-0.0f32, 0.0], [1.0f32, -1.0], [-1.0f32, 1.0]].iter().for_each(|[input, ret]| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[0] = false as u32; - thread.vec_reg[3] = input.to_bits(); - r(&vec![0xD5010003, 0x2001FF03, 0x80000000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3], ret.to_bits()); - }); - } - - #[test] - fn test_v_mul_hi_i32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = -2i32 as u32; - r(&vec![0xD72E0003, 0x000204FF, 0x2E8BA2E9, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3] as i32, -1); - - thread.vec_reg[2] = 2; - r(&vec![0xD72E0003, 0x000204FF, 0x2E8BA2E9, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3], 0); - } - - #[test] - fn test_v_writelane_b32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[8] = 25056; - r(&vec![0xD7610004, 0x00010008, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.get_lane(0)[4], 25056); - - thread.scalar_reg[9] = 25056; - r(&vec![0xD7610004, 0x00010209, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.get_lane(1)[4], 25056); - } - - #[test] - fn test_v_readlane_b32() { - let mut thread = _helper_test_thread(); - thread.vec_reg.get_lane_mut(15)[4] = 0b1111; - r(&vec![0xD760006A, 0x00011F04, END_PRG], &mut thread); - assert_eq!(thread.vcc.read(), true); - } - - #[test] - fn test_v_lshlrev_b64() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(2, 100); - thread.vec_reg[4] = 2; - r(&vec![0xD73C0002, 0x00020504, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.read64(2), 400); - } - - #[test] - fn test_v_lshrrev_b64() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(2, 100); - thread.vec_reg[4] = 2; - r(&vec![0xd73d0002, 0x00020504, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.read64(2), 25); - } - - #[test] - fn test_v_add_f64_neg_modifier() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0x652b82fe; - thread.vec_reg[1] = 0x40071547; - thread.vec_reg[2] = 0; - thread.vec_reg[3] = 0x40080000; - r(&vec![0xD7270004, 0x40020500, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 1519362112); - assert_eq!(thread.vec_reg[5], 3216856851); - } - - #[test] - fn test_v_cvt_f32_f16_abs_modifier() { - [[0.4, 0.4], [-0.4, 0.4]].iter().for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = f16::from_f32_const(*a).to_bits() as u32; - r(&vec![0xD58B0102, 0x00000101, END_PRG], &mut thread); - assert!(approx_eq!(f32, f32::from_bits(thread.vec_reg[2]), *ret, (0.01, 2))); - }); - } - - #[test] - fn test_v_alignbit_b32() { - let mut thread = _helper_test_thread(); - thread.scalar_reg[4] = 5340353; - thread.scalar_reg[10] = 3072795146; - thread.vec_reg[0] = 8; - r(&vec![0xD6160001, 0x04001404, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 3250005794); - } - - #[test] - fn test_v_bfe_i32() { - [ - [0b00000000000000000000000000000001, -1], - [0b00000000000000000000000000000000, 0], - [0b00000000000000000000000000000010, 0], - ] - .iter() - .for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = *a as u32; - r(&vec![0xD6110005, 0x02050102, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5] as i32, *ret); - }); - - [ - [0b00000000000000000000000000000010, -2], - [0b00000000000000000000000000000001, 1], - [0b00000000000000000000000000000100, 0], - ] - .iter() - .for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = *a as u32; - r(&vec![0xD6110005, 0x02090102, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5] as i32, *ret); - }); - - [ - [0b00100000000000000000000000000000, 0b100000000000000000000000000000], - [0b00000000000000001000000000000000, 0b1000000000000000], - [-1, -1], - ] - .iter() - .for_each(|[a, ret]| { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = *a as u32; - r(&vec![0xD6110005, 0x03050102, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5] as i32, *ret); - }); - } - - #[test] - fn test_v_ashrrev_i16() { - let mut thread = _helper_test_thread(); - [ - [0b10000000000000000000000000000000, 0], - [0b10000000000000000000000000000111, 3], - [0b0000000000000000, 0], - [0b1000000000000000, 0b1100000000000000], - [0b0100000000000000, 0b0010000000000000], - [0b0010000000000000, 0b0001000000000000], - [0b1010000000000000, 0b1101000000000000], - [0b1110000000000000, 0b1111000000000000], - [0b0110000000000000, 0b0011000000000000], - ] - .iter() - .for_each(|[a, ret]| { - thread.vec_reg[2] = *a; - thread.scalar_reg[1] = 1; - r(&vec![0xd73a0005, 0b11000001100000010000000001, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], *ret); - }); - - [ - [0b1000000000000000, 0b1111, 0b1111111111111111], - [0b1000000000000000, 0b11111, 0b1111111111111111], - [0b1000000000000000, 0b0111, 0b1111111100000000], - ] - .iter() - .for_each(|[a, shift, ret]| { - thread.vec_reg[2] = *a; - thread.scalar_reg[1] = *shift; - r(&vec![0xd73a0005, 0b11000001100000010000000001, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], *ret); - }); - - thread.vec_reg[5] = 0b11100000000000001111111111111111; - thread.vec_reg[2] = 0b0100000000000000; - thread.scalar_reg[1] = 1; - r(&vec![0xd73a0005, 0b11000001100000010000000001, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 0b11100000000000000010000000000000); - } - - #[test] - fn test_v_add_nc_u16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[5] = 10; - thread.vec_reg[8] = 20; - r(&vec![0xD7030005, 0x00021105, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 30); - } - - #[test] - fn test_v_mul_lo_u16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[5] = 2; - thread.vec_reg[15] = 0; - r(&vec![0xD705000F, 0x00010B05, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[15], 10); - - thread.vec_reg[5] = 2; - thread.vec_reg[15] = 0b10000000000000000000000000000000; - r(&vec![0xD705000F, 0x00010B05, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[15], 0b10000000000000000000000000000000 + 10); - } - - #[test] - fn test_v_cmp_gt_u16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = 52431; - thread.scalar_reg[5] = 0; - r(&vec![0xD43C0005, 0x000202FF, 0x00003334, END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[5], 0); - } - - #[test] - fn test_v_cmp_ngt_f32_abs() { - [(0.5f32, 0.5f32, 1), (-0.5, 0.5, 1), (0.1, 0.2, 0), (-0.1, 0.2, 0)] - .iter() - .for_each(|(x, y, ret)| { - let mut thread = _helper_test_thread(); - thread.scalar_reg[2] = x.to_bits(); - r(&vec![0xD41B0203, 0x000004FF, y.to_bits(), END_PRG], &mut thread); - assert_eq!(thread.scalar_reg[3], *ret); - }) - } - #[test] - fn test_fma() { - fn v_fma_f32(a: u32, b: u32, c: u32, ret: u32) { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = b; - thread.scalar_reg[3] = c; - r(&vec![0xD6130000, 0x000E02FF, a, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], ret); - } - fn v_fmac_f32(a: u32, b: u32, c: u32, ret: u32) { - let mut thread = _helper_test_thread(); - thread.scalar_reg[1] = a; - thread.scalar_reg[2] = b; - thread.vec_reg[0] = c; - r(&vec![0xd52b0000, 0x401, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], ret); - } - [[0xbfc90fda, 1186963456, 1192656896, 3204127872]].iter().for_each(|[a, b, c, ret]| { - v_fma_f32(*a, *b, *c, *ret); - v_fmac_f32(*a, *b, *c, *ret); - }) - } - - #[test] - fn test_v_perm_b32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = 15944; - thread.vec_reg[0] = 84148480; - r(&vec![0xD644000F, 0x03FE0101, 0x05040100, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[15], 1044906240); - } - - #[test] - fn test_v_mul_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0x5a8fa040; - thread.vec_reg[1] = 0xbfbd5713; - thread.vec_reg[2] = 0x3b39803f; - thread.vec_reg[3] = 0x3c7abc9e; - r(&vec![0xD7280004, 0x00020500, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 1602589062); - assert_eq!(thread.vec_reg[5], 3158868912); - } - - #[test] - fn test_v_fma_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0x5a8fa040; - thread.vec_reg[1] = 0xbfbd5713; - thread.vec_reg[2] = 0xfefa39ef; - thread.vec_reg[3] = 0x3fe62e42; - thread.vec_reg[4] = 0x5f859186; - thread.vec_reg[5] = 0xbc4883b0; - r(&vec![0xD6140006, 0x04120500, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[6], 3883232879); - assert_eq!(thread.vec_reg[7], 3216266823); - } - - #[test] - fn test_v_fma_f64_const() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = 0xf690ecbf; - thread.vec_reg[1] = 0x3fdf2b4f; - thread.vec_reg[2] = 0xe7756e6f; - thread.vec_reg[3] = 0xbfb45647; - r(&vec![0xD6140004, 0x03CA0500, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 962012421); - assert_eq!(thread.vec_reg[5], 1072612110); - } - - #[test] - fn test_v_ldexp_f64() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, f64::to_bits(5.0)); - thread.vec_reg[2] = 3; - thread.vec_reg[3] = 3; - r(&vec![0xD72B0000, 0x00020500, END_PRG], &mut thread); - let val = f64::from_bits(thread.vec_reg.read64(0)); - assert_eq!(val, 40.0); - } - - #[test] - fn test_simm_resolve_int_in_double_op() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, 3.0f64.to_bits()); - let simm = 0xFFFFFFE0; - r(&vec![0xD72B0002, 0x0001FF00, simm, END_PRG], &mut thread); - assert_eq!(f64::from_bits(thread.vec_reg.read64(2)), 3.0 * 2.0.powi(-32)); - } - - #[test] - fn test_simm_resolve_double_in_double_op() { - let mut thread = _helper_test_thread(); - thread.vec_reg.write64(0, 2.0f64.to_bits()); - let simm = 0x40080000; - r(&vec![0xD7280000, 0x000200FF, simm, END_PRG], &mut thread); - assert_eq!(f64::from_bits(thread.vec_reg.read64(0)), 6.0); - } -} - -#[cfg(test)] -mod test_vopp { - use super::*; - - #[test] - fn test_v_fma_mix_f32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = 1065353216; - thread.scalar_reg[2] = 3217620992; - thread.vec_reg[1] = 15360; - r(&vec![0xCC204403, 0x04040502, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3], 3205627904); - - thread.vec_reg[2] = 1065353216; - thread.scalar_reg[2] = 3217620992; - thread.vec_reg[1] = 48128; - r(&vec![0xCC204403, 0x04040502, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[3], 3205627904); - } - - #[test] - fn test_packed_opsel_000_op_000() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = 1; - thread.vec_reg[2] = 2; - thread.vec_reg[3] = 3; - r(&vec![0xCC090004, 0x040E0501, 0xBFB00000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1010000000000000101); - } - - #[test] - fn test_packed_opsel_001_op_100() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = 1; - thread.vec_reg[2] = 2; - thread.vec_reg[3] = 3; - r(&vec![0xCC092004, 0x0C0E0501, 0xBFB00000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b110000000000000010); - } - - #[test] - fn test_packed_inline_const_int() { - let mut thread = _helper_test_thread(); - thread.vec_reg[1] = 1; - thread.vec_reg[2] = 2; - thread.vec_reg[3] = 3; - - r(&vec![0xCC090004, 0x020E0501, 0xBFB00000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1010000000000000101); - - r(&vec![0xCC090804, 0x0A0E0501, 0xBFB00000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b110000000000000011); - - r(&vec![0xCC096004, 0x020E0501, 0xBFB00000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b100000000000000010); - - r(&vec![0xCC090004, 0x03FE0501, 0x00000080, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 8519810); - } - - #[test] - fn test_pk_fma_f16_inline_const() { - let mut thread = _helper_test_thread(); - thread.vec_reg[2] = 0x393a35f6; - thread.vec_reg[3] = 0x2800; - - r(&vec![0xCC0E0004, 0x03FE0702, 0x0000A400, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 2618596372); - - r(&vec![0xCC0E0004, 0x0BFE0702, 0x0000A400, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 485006356); - - r(&vec![0xCC0E0004, 0x1BFE0702, 0x0000A400, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 2751503380); - - r(&vec![0xCC0E0804, 0x03FE0702, 0x0000A400, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 2618563816); - - r(&vec![0xCC0E1804, 0x03FE0702, 0x0000A400, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 2618598400); - } - - #[test] - fn test_v_fma_mixhilo_f16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[11] = 1065353216; - thread.vec_reg[7] = 3047825943; - thread.vec_reg[16] = 3047825943; - - thread.vec_reg[14] = 0b10101010101010101111111111111111; - r(&vec![0xCC21000E, 0x04420F0B, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[14], 0b10101010101010101000000000101011); - - thread.vec_reg[14] = 0b10101010101010101111111111111111; - r(&vec![0xCC22000E, 0x04420F0B, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[14], 0b10000000001010111111111111111111); - } - - #[test] - fn test_v_pk_lshlrev_b16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[3] = 0b1010101011101101; - - r(&vec![0xCC044004, 0x0002068E, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1000000000000000100000000000000); - - r(&vec![0xCC044004, 0x1002068E, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b100000000000000); - - r(&vec![0xCC044004, 0x100206FF, 0x00010002, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1010101110110100); - r(&vec![0xCC044004, 0x100206FF, 0x05012002, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1010101110110100); - - r(&vec![0xCC044004, 0x100206FF, 0x0503E00F, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1000000000000000); - r(&vec![0xCC044004, 0x100206FF, 0x0503E007, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b111011010000000); - r(&vec![0xCC044004, 0x100206FF, 0x0503E01F, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[4], 0b1000000000000000); - } - - #[test] - fn test_pk_fma_with_neg() { - let mut thread = _helper_test_thread(); - let a1 = f16::from_f32(1.0); - let b1 = f16::from_f32(2.0); - let c1 = f16::from_f32(3.0); - - let a2 = f16::from_f32(4.0); - let b2 = f16::from_f32(5.0); - let c2 = f16::from_f32(6.0); - - thread.vec_reg[0] = (a1.to_bits() as u32) << 16 | (a2.to_bits() as u32); - thread.vec_reg[9] = (b1.to_bits() as u32) << 16 | (b2.to_bits() as u32); - thread.vec_reg[10] = (c1.to_bits() as u32) << 16 | (c2.to_bits() as u32); - - r(&vec![0xCC0E3805, 0x042A1300, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 1317029120); - - r(&vec![0xCC0E3805, 0x242A1300, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 1317026816); - - r(&vec![0xCC0E3B05, 0x042A1300, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 1317029120); - - r(&vec![0xCC0E3905, 0x042A1300, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[5], 3405792512); - } - - #[test] - fn test_pk_add_f16_with_float_const() { - let mut thread = _helper_test_thread(); - let a1 = f16::from_f32(5.0); - let a2 = f16::from_f32(10.0); - - thread.vec_reg[1] = (a1.to_bits() as u32) << 16 | (a2.to_bits() as u32); - r(&vec![0xCC0F4002, 0x0001E501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 1233144192); - - r(&vec![0xCC0F5002, 0x0001E501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 1233144064); - - r(&vec![0xCC0F5002, 0x1001E501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 1224755456); - - r(&vec![0xCC0F5802, 0x1801E501, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[2], 1157645568); - } -} - -#[cfg(test)] -mod test_flat { - use super::*; - use std::alloc::{alloc, handle_alloc_error, Layout}; - - #[test] - fn test_scratch_swap_values() { - let mut thread = _helper_test_thread(); - thread.vec_reg[13] = 42; - thread.vec_reg[14] = 10; - r( - &vec![ - 0xDC690096, 0x007C0D00, 0xDC69001E, 0x007C0E00, 0xDC51001E, 0x0D7C0000, 0xDC510096, 0x0E7C0000, END_PRG, - ], - &mut thread, - ); - assert_eq!(thread.vec_reg[13], 10); - assert_eq!(thread.vec_reg[14], 42); - } - - #[test] - fn test_scratch_load_dword_offset() { - let mut thread = _helper_test_thread(); - thread.vec_reg[14] = 14; - thread.vec_reg[15] = 23; - r(&vec![0xDC6D000A, 0x007C0E00, 0xDC51000A, 0x0E7C0000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[14], 14); - - r(&vec![0xDC6D000A, 0x007C0E00, 0xDC51000E, 0x0E7C0000, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[14], 23); - } - - #[test] - fn test_global_load_d16_hi_b16() { - let mut thread = _helper_test_thread(); - thread.vec_reg[13] = 0b10101011101101001111111111111111; - unsafe { - let layout = Layout::new::(); - let ptr = alloc(layout); - if ptr.is_null() { - handle_alloc_error(layout) - } - *(ptr as *mut u16) = 42; - thread.vec_reg.write64(10, ptr as u64); - } - r(&vec![0xDC8E0000, 0x0D7C000A, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[13], 0b00000000001010101111111111111111); - } -} - -#[cfg(test)] -mod test_lds { - use super::*; - #[test] - fn test_ds_load_offset() { - let mut thread = _helper_test_thread(); - thread.lds.write(256, 69); - thread.vec_reg[9] = 0; - r(&vec![0xD8D80100, 0x01000009, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 69); - - thread.lds.write(800, 69); - thread.vec_reg[9] = 0; - r(&vec![0xD8D80320, 0x01000009, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 69); - - thread.lds.write(3, 69); - thread.vec_reg[9] = 0; - r(&vec![0xD8D80003, 0x01000009, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[1], 69); - } - - #[test] - fn test_ds_load_dwords() { - let mut thread = _helper_test_thread(); - thread.lds.write(0, 100); - thread.lds.write(4, 200); - thread.vec_reg[9] = 0; - r(&vec![0xD9D80000, 0x00000009, END_PRG], &mut thread); - assert_eq!(thread.vec_reg.read64(0), 858993459300); - - thread.lds.write(0, 1); - thread.lds.write(4, 2); - thread.lds.write(8, 3); - thread.lds.write(12, 4); - thread.vec_reg[9] = 0; - r(&vec![0xDBFC0000, 0x00000009, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 1); - assert_eq!(thread.vec_reg[1], 2); - assert_eq!(thread.vec_reg[2], 3); - assert_eq!(thread.vec_reg[3], 4); - } - - #[test] - fn test_ds_load_u8() { - let mut thread = _helper_test_thread(); - thread.lds.write(0, 17); - thread.vec_reg[0] = 0; - r(&vec![0xD8E80000, 0x00000100, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 17); - - thread.lds.write(0, 264); - thread.vec_reg[0] = 0; - r(&vec![0xD8E80000, 0x00000100, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 8); - - thread.lds.write(8, 23); - thread.vec_reg[0] = 0; - r(&vec![0xD8E80008, 0x00000100, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 23); - - thread.lds.write(16, 29); - thread.vec_reg[0] = 0; - r(&vec![0xD8E80010, 0x00000100, END_PRG], &mut thread); - assert_eq!(thread.vec_reg[0], 29); - } - - #[test] - fn test_ds_store_dwords() { - let mut thread = _helper_test_thread(); - thread.vec_reg[9] = 69; - thread.vec_reg[0] = 0; - r(&vec![0xD83403E8, 0x00000900, END_PRG], &mut thread); - assert_eq!(thread.lds.read(1000), 69); - } - - #[test] - fn test_ds_store_half() { - let mut thread = _helper_test_thread(); - thread.vec_reg[9].mut_lo16(f16::from_f32(1.2).to_bits()); - thread.vec_reg[9].mut_hi16(f16::from_f32(4.3).to_bits()); - thread.vec_reg[0] = 0; - thread.vec_reg[1] = 2; - r(&vec![0xDA840000, 0x00000900, 0xD87C0000, 0x00000901, END_PRG], &mut thread); - assert_eq!(thread.lds.read(0) as u16, f16::from_f32(4.3).to_bits()); - assert_eq!(thread.lds.read(2) as u16, f16::from_f32(1.2).to_bits()); - } -} -#[allow(dead_code)] -fn r(prg: &Vec, thread: &mut Thread) { - let mut pc = 0; - let instructions = prg.to_vec(); - thread.pc_offset = 0; - if thread.exec.value == 0 { - thread.exec.value = u32::MAX; - } - - loop { - if instructions[pc] == END_PRG { - break; - } - if instructions[pc] == 0xbfb60003 || instructions[pc] >> 20 == 0xbf8 { - pc += 1; - continue; - } - thread.pc_offset = 0; - thread.stream = instructions[pc..instructions.len()].to_vec(); - thread.interpret().unwrap(); - thread.simm = None; - if thread.vcc.mutations.is_some() { - thread.vcc.apply_muts(); - thread.vcc.mutations = None; - } - if thread.exec.mutations.is_some() { - thread.exec.apply_muts(); - thread.exec.mutations = None; - } - if let Some((idx, mut wv)) = thread.sgpr_co { - wv.apply_muts(); - thread.scalar_reg[*idx] = wv.value; - } - if *DEBUG { - println!() - } - pc = ((pc as isize) + 1 + (thread.pc_offset as isize)) as usize; - } -} -fn _helper_test_thread() -> Thread<'static> { - let static_lds: &'static mut VecDataStore = Box::leak(Box::new(VecDataStore::new())); - let static_sgpr: &'static mut [u32; SGPR_COUNT] = Box::leak(Box::new([0; SGPR_COUNT])); - let static_vgpr: &'static mut VGPR = Box::leak(Box::new(VGPR::new())); - let static_scc: &'static mut u32 = Box::leak(Box::new(0)); - let static_exec: &'static mut WaveValue = Box::leak(Box::new(WaveValue::new(u32::MAX, 32))); - let static_vcc: &'static mut WaveValue = Box::leak(Box::new(WaveValue::new(0, 32))); - let static_sds: &'static mut VecDataStore = Box::leak(Box::new(VecDataStore::new())); - let static_co: &'static mut Option<(usize, WaveValue)> = Box::leak(Box::new(None)); - - let thread = Thread { - scalar_reg: static_sgpr, - vec_reg: static_vgpr, - scc: static_scc, - vcc: static_vcc, - exec: static_exec, - lds: static_lds, - sds: static_sds, - simm: None, - pc_offset: 0, - stream: vec![], - sgpr_co: static_co, - warp_size: 32, - scalar: false, - }; - thread.vec_reg.default_lane = Some(0); - thread.vcc.default_lane = Some(0); - thread.exec.default_lane = Some(0); - return thread; -} diff --git a/tinygrad/extra/remu/src/work_group.rs b/tinygrad/extra/remu/src/work_group.rs deleted file mode 100644 index f1b0a7d8..00000000 --- a/tinygrad/extra/remu/src/work_group.rs +++ /dev/null @@ -1,233 +0,0 @@ -use crate::helpers::{colored, DEBUG}; -use crate::state::{Register, VecDataStore, WaveValue, VGPR}; -use crate::thread::{Thread, END_PRG, SGPR_COUNT}; -use std::collections::HashMap; - -pub const WAVE_SIZE: usize = 32; - -pub struct WorkGroup<'a> { - dispatch_dim: u32, - id: [u32; 3], - lds: VecDataStore, - kernel: &'a Vec, - kernel_args: *const u64, - launch_bounds: [u32; 3], - wave_state: HashMap, -} - -#[derive(Debug, Clone)] -struct WaveState { - scalar_reg: [u32; SGPR_COUNT], - scc: u32, - vcc: WaveValue, - exec: WaveValue, - vec_reg: VGPR, - pc: usize, - sds: HashMap, -} - -const SYNCS: [u32; 4] = [0xBF89FC07, 0xBC7C0000, 0xBF890007, 0xbFB60003]; -const S_BARRIER: u32 = 0xBFBD0000; -impl<'a> WorkGroup<'a> { - pub fn new(dispatch_dim: u32, id: [u32; 3], launch_bounds: [u32; 3], kernel: &'a Vec, kernel_args: *const u64) -> Self { - Self { dispatch_dim, id, kernel, launch_bounds, kernel_args, lds: VecDataStore::new(), wave_state: HashMap::new() } - } - - pub fn exec_waves(&mut self) -> Result<(), i32> { - let mut threads = vec![]; - for z in 0..self.launch_bounds[2] { - for y in 0..self.launch_bounds[1] { - for x in 0..self.launch_bounds[0] { - threads.push([x, y, z]) - } - } - } - let waves = threads.chunks(WAVE_SIZE).collect::>(); - - let mut sync = false; - for (i, x) in self.kernel.iter().enumerate() { - if i != 0 && *x == S_BARRIER { - sync = true; - break; - } - } - - for _ in 0..=(sync as usize) { - for w in waves.iter().enumerate() { - self.exec_wave(w)? - } - } - Ok(()) - } - - fn exec_wave(&mut self, (wave_id, threads): (usize, &&[[u32; 3]])) -> Result<(), i32> { - let (mut scalar_reg, mut scc, mut pc, mut vec_reg, mut vcc, mut exec, mut sds) = match self.wave_state.get(&wave_id) { - None => { - let mut scalar_reg = [0; SGPR_COUNT]; - scalar_reg.write64(0, self.kernel_args as u64); - - let [gx, gy, gz] = self.id; - match self.dispatch_dim { - 3 => (scalar_reg[13], scalar_reg[14], scalar_reg[15]) = (gx, gy, gz), - 2 => (scalar_reg[14], scalar_reg[15]) = (gx, gy), - _ => scalar_reg[15] = gx, - } - - let mut vec_reg = VGPR::new(); - for (t, [x, y, z]) in threads.iter().enumerate() { - vec_reg.get_lane_mut(t)[0] = match &self.launch_bounds { - [_, 1, 1] => *x, - _ => (z << 20) | (y << 10) | x, - } - } - - let vcc = WaveValue::new(0, threads.len()); - let active = (!0u32).wrapping_shr(32 - (threads.len() as u32)); - let exec = WaveValue::new(active, threads.len()); - - let sds = (0..=31).map(|i| (i, VecDataStore::new())).collect(); - (scalar_reg, 0, 0, vec_reg, vcc, exec, sds) - } - - Some(val) => { - let val = val.clone(); - (val.scalar_reg, val.scc, val.pc, val.vec_reg, val.vcc, val.exec, val.sds) - } - }; - - loop { - if self.kernel[pc] == END_PRG { - break Ok(()); - } - if self.kernel[pc] == S_BARRIER && self.wave_state.get(&wave_id).is_none() { - self.wave_state.insert(wave_id, WaveState { scalar_reg, scc, vec_reg, vcc, exec, pc, sds }); - break Ok(()); - } - if self.kernel[pc] == S_BARRIER || SYNCS.contains(&self.kernel[pc]) || self.kernel[pc] >> 20 == 0xbf8 || self.kernel[pc] == 0x7E000000 { - pc += 1; - continue; - } - - let mut sgpr_co = None; - for (lane_id, [x, y, z]) in threads.iter().enumerate() { - vec_reg.default_lane = Some(lane_id); - vcc.default_lane = Some(lane_id); - exec.default_lane = Some(lane_id); - if *DEBUG { - let lane = format!("{:<2} {:08X} ", lane_id, self.kernel[pc]); - let state = match exec.read() { - true => "green", - false => "gray", - }; - let [id0, id1, id2] = self.id; - print!("[{id0:<3} {id1:<3} {id2:<3}] [{x:<3} {y:<3} {z:<3}] {}", colored(&lane, state)); - } - let mut thread = Thread { - scalar_reg: &mut scalar_reg, - scc: &mut scc, - vec_reg: &mut vec_reg, - vcc: &mut vcc, - exec: &mut exec, - lds: &mut self.lds, - sds: &mut sds.get_mut(&lane_id).unwrap(), - pc_offset: 0, - stream: self.kernel[pc..self.kernel.len()].to_vec(), - scalar: false, - simm: None, - warp_size: threads.len(), - sgpr_co: &mut sgpr_co, - }; - thread.interpret()?; - if *DEBUG { - println!(); - } - if thread.scalar { - pc = ((pc as isize) + 1 + (thread.pc_offset as isize)) as usize; - break; - } - if lane_id == threads.len() - 1 { - pc = ((pc as isize) + 1 + (thread.pc_offset as isize)) as usize; - } - } - - if vcc.mutations.is_some() { - vcc.apply_muts(); - vcc.mutations = None; - } - if exec.mutations.is_some() { - exec.apply_muts(); - exec.mutations = None; - } - if let Some((idx, mut wv)) = sgpr_co.take() { - wv.apply_muts(); - scalar_reg[idx] = wv.value; - } - } - } -} - -#[cfg(test)] -mod test_workgroup { - use super::*; - - // TODO: make this generic by adding the assembler - fn global_store_sgpr(addr: u64, instructions: Vec, src: u32) -> Vec { - [ - instructions, - vec![ - 0x7E020200 + src, - 0x7E0402FF, - addr as u32, - 0x7E0602FF, - (addr >> 32) as u32, - 0xDC6A0000, - 0x007C0102, - ], - vec![END_PRG], - ] - .concat() - } - - #[test] - fn test_wave_value_state_vcc() { - let mut ret: u32 = 0; - let kernel = vec![ - 0xBEEA00FF, - 0b11111111111111111111111111111111, // initial vcc state - 0x7E140282, - 0x7C94010A, // cmp blockDim.x == 2 - ]; - let addr = (&mut ret as *mut u32) as u64; - let kernel = global_store_sgpr(addr, kernel, 106); - let mut wg = WorkGroup::new(1, [0, 0, 0], [3, 1, 1], &kernel, [addr].as_ptr()); - wg.exec_waves().unwrap(); - assert_eq!(ret, 0b100); - } - - #[test] - fn test_wave_value_state_exec() { - let mut ret: u32 = 0; - let kernel = vec![ - 0xBEFE00FF, - 0b11111111111111111111111111111111, - 0x7E140282, - 0x7D9C010A, // cmpx blockDim.x <= 2 - ]; - let addr = (&mut ret as *mut u32) as u64; - let kernel = global_store_sgpr(addr, kernel, 126); - let mut wg = WorkGroup::new(1, [0, 0, 0], [4, 1, 1], &kernel, [addr].as_ptr()); - wg.exec_waves().unwrap(); - assert_eq!(ret, 0b0111); - } - - #[test] - fn test_wave_value_sgpr_co() { - let mut ret: u32 = 0; - let kernel = vec![0xBE8D00FF, 0x7FFFFFFF, 0x7E1402FF, u32::MAX, 0xD700000A, 0x0002010A]; - let addr = (&mut ret as *mut u32) as u64; - let kernel = global_store_sgpr(addr, kernel, 0); - let mut wg = WorkGroup::new(1, [0, 0, 0], [5, 1, 1], &kernel, [addr].as_ptr()); - wg.exec_waves().unwrap(); - assert_eq!(ret, 0b11110); - } -} diff --git a/tinygrad/extra/remu/test/hwtest.py b/tinygrad/extra/remu/test/hwtest.py deleted file mode 100644 index 76bd2f6e..00000000 --- a/tinygrad/extra/remu/test/hwtest.py +++ /dev/null @@ -1,202 +0,0 @@ -import numpy as np -import unittest -import subprocess, struct, math -from typing import cast -from tinygrad.runtime.ops_amd import AMDProgram, AMDDevice -from tinygrad import Tensor, dtypes, Device -from tinygrad.helpers import diskcache, OSX, getenv - -@diskcache -def assemble(code:str) -> bytes: - try: - LLVM_MC = "llvm-mc" if OSX else "/opt/rocm/llvm/bin/llvm-mc" - return subprocess.run([LLVM_MC, "--arch=amdgcn", "--mcpu=gfx1100", "--triple=amdgcn-amd-amdhsa", "-filetype=obj", "-o", "-"], - input=code.encode("utf-8"), stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True).stdout - except subprocess.CalledProcessError as e: - print("stderr:") - print(e.stderr.decode()) - raise - -# copied from extra/rdna -def get_prg(code:str, v_cnt:int, s_cnt:int): - function_name = "test" - metadata = f""" -amdhsa.kernels: -- .args: - - .address_space: global - .name: buf_0 - .offset: 0 - .size: 8 - .type_name: unsigned int* - .value_kind: global_buffer - .group_segment_fixed_size: 0 - .kernarg_segment_align: 8 - .kernarg_segment_size: 8 - .language: OpenCL C - .language_version: - - 1 - - 2 - .max_flat_workgroup_size: 256 - .name: test - .private_segment_fixed_size: 0 - .sgpr_count: {s_cnt} - .sgpr_spill_count: 0 - .symbol: test.kd - .uses_dynamic_stack: false - .vgpr_count: {v_cnt} - .vgpr_spill_count: 0 - .wavefront_size: 32 -amdhsa.target: amdgcn-amd-amdhsa--gfx1100 -amdhsa.version: -- 1 -- 2 - """ - boilerplate_start = f""" - .rodata - .global {function_name}.kd - .type {function_name}.kd,STT_OBJECT - .align 0x10 - .amdhsa_kernel {function_name}""" - kernel_desc = { - '.amdhsa_group_segment_fixed_size': 0, '.amdhsa_private_segment_fixed_size': 0, '.amdhsa_kernarg_size': 0, - '.amdhsa_next_free_vgpr': v_cnt, # this matters! - '.amdhsa_reserve_vcc': 0, '.amdhsa_reserve_xnack_mask': 0, - '.amdhsa_next_free_sgpr': s_cnt, - '.amdhsa_float_round_mode_32': 0, '.amdhsa_float_round_mode_16_64': 0, '.amdhsa_float_denorm_mode_32': 3, '.amdhsa_float_denorm_mode_16_64': 3, - '.amdhsa_dx10_clamp': 1, '.amdhsa_ieee_mode': 1, '.amdhsa_fp16_overflow': 0, - '.amdhsa_workgroup_processor_mode': 1, '.amdhsa_memory_ordered': 1, '.amdhsa_forward_progress': 0, '.amdhsa_enable_private_segment': 0, - '.amdhsa_system_sgpr_workgroup_id_x': 1, '.amdhsa_system_sgpr_workgroup_id_y': 1, '.amdhsa_system_sgpr_workgroup_id_z': 1, - '.amdhsa_system_sgpr_workgroup_info': 0, '.amdhsa_system_vgpr_workitem_id': 2, # is amdhsa_system_vgpr_workitem_id real? - '.amdhsa_exception_fp_ieee_invalid_op': 0, '.amdhsa_exception_fp_denorm_src': 0, - '.amdhsa_exception_fp_ieee_div_zero': 0, '.amdhsa_exception_fp_ieee_overflow': 0, '.amdhsa_exception_fp_ieee_underflow': 0, - '.amdhsa_exception_fp_ieee_inexact': 0, '.amdhsa_exception_int_div_zero': 0, - '.amdhsa_user_sgpr_dispatch_ptr': 0, '.amdhsa_user_sgpr_queue_ptr': 0, '.amdhsa_user_sgpr_kernarg_segment_ptr': 1, - '.amdhsa_user_sgpr_dispatch_id': 0, '.amdhsa_user_sgpr_private_segment_size': 0, '.amdhsa_wavefront_size32': 1, '.amdhsa_uses_dynamic_stack': 0} - code_start = f""".end_amdhsa_kernel - .text - .global {function_name} - .type {function_name},@function - .p2align 8 - {function_name}: - """ - ret = ".amdgpu_metadata\n" + metadata + ".end_amdgpu_metadata" + boilerplate_start + "\n" + '\n'.join("%s %d" % x for x in kernel_desc.items()) \ - + "\n" + code_start + code + f"\n.size {function_name}, .-{function_name}" - return AMDProgram(cast(AMDDevice, Device["AMD"]), function_name, assemble(ret)) - -def get_output(s:str, n_threads:int=1): - assert n_threads <= 32 - code = "\n".join(["s_load_b64 s[0:1], s[0:1], null", "v_lshlrev_b32_e32 v0, 2, v0", s, - "s_waitcnt 0", - "global_store_b32 v0, v1, s[0:1]", - "s_nop 0", "s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)", "s_endpgm"]) - test = Tensor.zeros((n_threads,), dtype=dtypes.uint32).contiguous().realize().uop.buffer - prg = get_prg(code, 32, 32) - prg(test._buf, global_size=(1, 1, 1), local_size=(n_threads, 1, 1), wait=True) - return test.numpy() - -def f16_to_bits(x:float) -> int: return struct.unpack(' float: return struct.unpack(' int: return struct.unpack('= 1: print(colored(f"fuzzing {len(toposorts)} schedule permutations", "yellow")) - - # setup ground truth - ground_truth: Dict[UOp, memoryview] = {} - assign_targets: Dict[UOp, UOp] = {} - # IMPORTANT: freeze prerealized bufs before ScheduleItem exec - prerealized: Dict[UOp, memoryview] = {} - seed = Tensor._seed - ts,_ = toposorts[0] - for lsi in ts: - for out in lsi.outputs: - # freeze assign state before exec - if out.op is Ops.ASSIGN: - prerealized[out] = out.buffer.as_buffer() - assign_targets[out.srcs[1]] = out - for x in lsi.inputs: - if x not in ground_truth and x.device != "NPY": prerealized[x] = x.buffer.as_buffer() - si = ScheduleItem(lsi.ast, tuple(x.buffer for x in lsi.outputs+lsi.inputs if x.size != 0), lsi.metadata) - _exec_si(si, seed) - for out in lsi.outputs: - ground_truth[out] = out.buffer.as_buffer() - del out.srcs # only schedule the LazyBuffer in this fuzz run - - # exec and validate each permutation with new Buffers - for i, (ts, ctx) in enumerate(toposorts[1:]): - if DEBUG >= 1: print(colored(f"testing permutation {i} {ctx}", "yellow")) - rawbufs: Dict[UOp, Buffer] = {} - for lsi in ts: - for out in lsi.outputs: - base = rawbufs[lsi.inputs[0]].base if out.op is Ops.BUFFER_VIEW else None - rawbufs[out] = Buffer(out.buffer.device, out.buffer.size, out.buffer.dtype, base=base) - if out.op is Ops.ASSIGN: rawbufs[out].ensure_allocated().copyin(prerealized[out]) - for x in lsi.inputs: - if x not in rawbufs: - # override the assign_target after ASSIGN - if x in assign_targets and assign_targets[x] in rawbufs: rawbufs[x] = rawbufs[assign_targets[x]] - elif x.device == "NPY": rawbufs[x] = x.buffer - # copy the pre realized input - else: rawbufs[x] = Buffer(x.buffer.device, x.buffer.size, x.buffer.dtype, initial_value=bytes(prerealized[x])) - si = ScheduleItem(lsi.ast, tuple(rawbufs[x] for x in lsi.bufs if x.size != 0), lsi.metadata) - _exec_si(si, seed) - for out in lsi.outputs: - outbuf = np.frombuffer(rawbufs[out].as_buffer(), _to_np_dtype(out.dtype)) - try: np.testing.assert_allclose(outbuf, np.frombuffer(ground_truth[out], _to_np_dtype(out.dtype)), atol=1e-2, rtol=1e-2) - except Exception as e: - print(f"FAILED FOR {out}") - raise e - -def _exec_si(si:ScheduleItem, seed:int): - ei = lower_schedule_item(si) - if len(capturing): capturing[0].add(ei) - ei.run() - -T = TypeVar("T") -def find_all_toposorts(graph:DefaultDict[T, List[T]], in_degree:Union[DefaultDict[T, int], Dict[T, int]]) -> List[Tuple[T, ...]]: - visited: Set[T] = set() - ret: List[Tuple[T, ...]] = [] - path: List[T] = [] - - def recurse_paths(path:List[T]): - for v, d in in_degree.items(): - if d != 0 or v in visited: continue - for u in graph[v]: in_degree[u] -= 1 - path.append(v) - visited.add(v) - recurse_paths(path) - if len(ret) >= FUZZ_SCHEDULE_MAX_PATHS: return - # backtrack - for u in graph[v]: in_degree[u] += 1 - path.pop() - visited.remove(v) - if len(path) == len(in_degree): ret.append(tuple(path)) - recurse_paths(path) - - if len(ret) == 0: raise RuntimeError("detected cycle in the graph") - # verify all paths are unique - assert len(ret) == len(set(ret)) - return ret diff --git a/tinygrad/extra/setup_mock_amd_osx.sh b/tinygrad/extra/setup_mock_amd_osx.sh deleted file mode 100755 index e710a808..00000000 --- a/tinygrad/extra/setup_mock_amd_osx.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/bash -INSTALL_PATH="${1:-/opt/homebrew/lib}" -if [ ! -d "$INSTALL_PATH" ]; then - USER=$(whoami) - echo "No path $INSTALL_PATH. Will create. Might need your password..." - echo "You can stop now and provide any location as an argument where you want to save the libs (note, that not default locations should be in LD_LIBRARY_PATH, so tinygrad can find the libs)." - echo "Press any key or symbol to continue..." - read -n 1 -s - - sudo mkdir -p "$INSTALL_PATH" - sudo chown -R "$USER":staff "$INSTALL_PATH" -fi - -# Download libremu.dylib -curl -s https://api.github.com/repos/Qazalin/remu/releases/latest | \ - jq -r '.assets[] | select(.name == "libremu.dylib").browser_download_url' | \ - xargs curl -L -o $INSTALL_PATH/libremu.dylib - -# Download libamd_comgr.dylib -curl -s https://api.github.com/repos/tinygrad/amdcomgr_dylib/releases/latest | \ - jq -r '.assets[] | select(.name == "libamd_comgr.dylib").browser_download_url' | \ - xargs curl -L -o $INSTALL_PATH/libamd_comgr.dylib diff --git a/tinygrad/extra/setup_mock_nv_osx.sh b/tinygrad/extra/setup_mock_nv_osx.sh deleted file mode 100755 index 43817174..00000000 --- a/tinygrad/extra/setup_mock_nv_osx.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash -e -cd /tmp -brew install cmake ninja llvm@15 zlib glew flex bison boost zstd ncurses -if [ ! -d "gpuocelot" ]; then - git clone --recurse-submodules https://github.com/gpuocelot/gpuocelot.git --depth 1 -fi -cd gpuocelot/ocelot -git checkout b16039dc940dc6bc4ea0a98380495769ff35ed99 -mkdir -p build -cd build -cmake .. -Wno-dev -G Ninja -DOCELOT_BUILD_TOOLS=OFF -DCMAKE_BUILD_ALWAYS=0 -DBUILD_TESTS_CUDA=OFF -DBISON_EXECUTABLE=/opt/homebrew/opt/bison/bin/bison -ninja -sudo cp libgpuocelot.dylib /usr/local/lib/ diff --git a/tinygrad/extra/sqtt/README.md b/tinygrad/extra/sqtt/README.md deleted file mode 100644 index ccd36279..00000000 --- a/tinygrad/extra/sqtt/README.md +++ /dev/null @@ -1,33 +0,0 @@ -# SQTT Profiling - -## Getting SQ Thread Trace - -Only supported on 7900XTX, requires either AM (`rmmod amdgpu`) or disabling power gating on AMD (`ppfeaturemask=0xffff3fff`, don't forget to rebuild initramfs) - -SQTT is implemented on top of normal tinygrad PROFILE=1, `PROFILE=1 SQTT=1` to get profile pickle with sqtt data embedded in it. - -`SQTT_BUFFER_SIZE=X` to change size of SQTT buffer (per shader engine, 6 SEs on 7900xtx) in megabytes, default 256. - -`SQTT_ITRACE_SE_MASK=X` to select for which shader engines instruction tracing will be enabled, -1 is all, 0 is none (instruction tracing disabled), >0 is -bitfield/mask for SEs to enable instruction tracing on. Masking shader engines will give smaller file sizes at a cost of less hits and kernels that -don't have any wavefront on first simd of shdaer engine with instruction tracing enabled will not have instruction timings. -The default is 2 (second shader engine only), only one for file size reasons, second instead of first because dispatch starts from it so there is -greater chance that kernels with small global size will have instruction tracing data. - -Note that instruction tracing might not be available for kernels with small global dims, this is not a bug, but it can be improved with various hacks -to the point where it can reliably trace a kernel consisting of a single wavefront (am only, not quite reliable under amdgpu due to waves sometimes -being dispatched starting from different simds). More info in comments in ops_amd.py - -## Converting pickled profile with SQTT data into RGP file - -```bash -extra/sqtt/rgptool.py create "/tmp/profile.pkl.$USER" -o /tmp/gpu0.rgp -``` - -Then load gpu0.rgp into Radeon GPU Profiler. It works just fine both in wine (macos, native version available for linux) and via ssh X forwarding - -If multiplle gpus are used you can select which one to export with `-d` like this: - -```bash -extra/sqtt/rgptool.py create "/tmp/profile.pkl.$USER" -d 'AMD:5' -o /tmp/gpu5.rgp -``` diff --git a/tinygrad/extra/sqtt/rgptool.py b/tinygrad/extra/sqtt/rgptool.py deleted file mode 100755 index a0d499e6..00000000 --- a/tinygrad/extra/sqtt/rgptool.py +++ /dev/null @@ -1,330 +0,0 @@ -#!/usr/bin/env python3 -from __future__ import annotations -import argparse, ctypes, struct, hashlib, pickle, code, typing, functools -import tinygrad.runtime.autogen.sqtt as sqtt -from tinygrad.device import ProfileEvent, ProfileDeviceEvent, ProfileProgramEvent -from tinygrad.runtime.ops_amd import ProfileSQTTEvent -from tinygrad.helpers import round_up, flatten, all_same -from dataclasses import dataclass - -CHUNK_CLASSES = { - sqtt.SQTT_FILE_CHUNK_TYPE_ASIC_INFO: sqtt.struct_sqtt_file_chunk_asic_info, - sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DESC: sqtt.struct_sqtt_file_chunk_sqtt_desc, - sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DATA: sqtt.struct_sqtt_file_chunk_sqtt_data, - sqtt.SQTT_FILE_CHUNK_TYPE_API_INFO: sqtt.struct_sqtt_file_chunk_api_info, - sqtt.SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS: sqtt.struct_sqtt_file_chunk_queue_event_timings, - sqtt.SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION: sqtt.struct_sqtt_file_chunk_clock_calibration, - sqtt.SQTT_FILE_CHUNK_TYPE_CPU_INFO: sqtt.struct_sqtt_file_chunk_cpu_info, - sqtt.SQTT_FILE_CHUNK_TYPE_SPM_DB: sqtt.struct_sqtt_file_chunk_spm_db, - sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE: sqtt.struct_sqtt_file_chunk_code_object_database, - sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS: sqtt.struct_sqtt_file_chunk_code_object_loader_events, - sqtt.SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION: sqtt.struct_sqtt_file_chunk_pso_correlation, -} - -def pretty(val, pad=0) -> str: - if isinstance(val, (ctypes.Structure, ctypes.Union)): - nl = '\n' # old python versions don't support \ in f-strings - return f"{val.__class__.__name__}({nl}{' '*(pad+2)}{(f', {nl}'+' '*(pad+2)).join([f'{field[0]}={pretty(getattr(val, field[0]), pad=pad+2)}' for field in val._fields_])}{nl}{' '*pad})" - if isinstance(val, ctypes.Array): - return f"[{', '.join(map(pretty, val))}]" - if isinstance(val, int) and val >= 1024: return hex(val) - return repr(val) - -@dataclass(frozen=True) -class RGPChunk: - header: sqtt.Structure - data: list[typing.Any]|list[tuple[typing.Any, bytes]]|bytes|None = None - def print(self): - print(pretty(self.header)) - # if isinstance(self.data, bytes): print(repr(self.data)) - if isinstance(self.data, list): - for dchunk in self.data: - if isinstance(dchunk, tuple): - print(pretty(dchunk[0])) - # print(repr(dchunk[1])) - else: - print(pretty(dchunk)) - # TODO: `def fixup` and true immutability - def to_bytes(self, offset:int) -> bytes: - cid = self.header.header.chunk_id.type - match cid: - case _ if cid in {sqtt.SQTT_FILE_CHUNK_TYPE_ASIC_INFO, sqtt.SQTT_FILE_CHUNK_TYPE_CPU_INFO, sqtt.SQTT_FILE_CHUNK_TYPE_API_INFO, sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DESC}: - self.header.header.size_in_bytes = ctypes.sizeof(self.header) - return bytes(self.header) - case sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DATA: - assert isinstance(self.data, bytes) - self.header.header.size_in_bytes = ctypes.sizeof(self.header) + len(self.data) - self.header.offset = offset+ctypes.sizeof(self.header) - self.header.size = len(self.data) - return bytes(self.header) + self.data - case sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE: - assert isinstance(self.data, list) - data_codb = typing.cast(list[tuple[sqtt.struct_sqtt_code_object_database_record, bytes]], self.data) - ret = bytearray() - sz = ctypes.sizeof(self.header)+sum([ctypes.sizeof(record_hdr)+round_up(len(record_blob), 4) for record_hdr,record_blob in data_codb]) - self.header.header.size_in_bytes = sz - self.header.offset = offset - self.header.record_count = len(data_codb) - self.header.size = sz - ret += self.header - for record_hdr,record_blob in data_codb: - record_hdr.size = round_up(len(record_blob), 4) - ret += record_hdr - ret += record_blob.ljust(4, b'\x00') - return ret - case sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS: - assert isinstance(self.data, list) - data_lev = typing.cast(list[tuple[sqtt.struct_sqtt_code_object_loader_events_record]], self.data) - self.header.header.size_in_bytes = ctypes.sizeof(self.header)+ctypes.sizeof(sqtt.struct_sqtt_code_object_loader_events_record)*len(data_lev) - self.header.offset = offset - self.header.record_size = ctypes.sizeof(sqtt.struct_sqtt_code_object_loader_events_record) - self.header.record_count = len(data_lev) - return bytes(self.header) + b''.join(map(bytes, data_lev)) - case sqtt.SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION: - assert isinstance(self.data, list) - data_pso = typing.cast(list[tuple[sqtt.struct_sqtt_pso_correlation_record]], self.data) - self.header.header.size_in_bytes = ctypes.sizeof(self.header)+ctypes.sizeof(sqtt.struct_sqtt_pso_correlation_record)*len(data_pso) - self.header.offset = offset - self.header.record_size = ctypes.sizeof(sqtt.struct_sqtt_pso_correlation_record) - self.header.record_count = len(data_pso) - return bytes(self.header) + b''.join(map(bytes, data_pso)) - case _: raise NotImplementedError(pretty(self.header)) - -@dataclass(frozen=True) -class RGP: - header: sqtt.struct_sqtt_file_header - chunks: list[RGPChunk] - @staticmethod - def from_bytes(blob: bytes) -> RGP: - file_header = sqtt.struct_sqtt_file_header.from_buffer_copy(blob) - assert file_header.magic_number == sqtt.SQTT_FILE_MAGIC_NUMBER and file_header.version_major == sqtt.SQTT_FILE_VERSION_MAJOR - i = file_header.chunk_offset - chunks = [] - while i < len(blob): - assert i%4==0, hex(i) - hdr = sqtt.struct_sqtt_file_chunk_header.from_buffer_copy(blob, i) - cid = hdr.chunk_id.type - header: ctypes.Structure - match cid: - case _ if cid in {sqtt.SQTT_FILE_CHUNK_TYPE_RESERVED, sqtt.SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS, sqtt.SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION, sqtt.SQTT_FILE_CHUNK_TYPE_SPM_DB}: - chunk = None - case sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE: - header = sqtt.struct_sqtt_file_chunk_code_object_database.from_buffer_copy(blob, i) - j = header.offset + ctypes.sizeof(header) - data: list = [] - while j < header.offset + header.size: - rec_hdr: ctypes.Structure = sqtt.struct_sqtt_code_object_database_record.from_buffer_copy(blob, j) - data.append((rec_hdr, elf:=blob[j+ctypes.sizeof(rec_hdr):j+ctypes.sizeof(rec_hdr)+rec_hdr.size])) - assert elf[:4] == b'\x7fELF', repr(elf[:16]) - j += ctypes.sizeof(rec_hdr)+rec_hdr.size - assert len(data) == header.record_count - chunk = RGPChunk(header, data) - case sqtt.SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS: - header = sqtt.struct_sqtt_file_chunk_code_object_loader_events.from_buffer_copy(blob, i) - data = [sqtt.struct_sqtt_code_object_loader_events_record.from_buffer_copy(blob, header.offset+ctypes.sizeof(header)+j*header.record_size) - for j in range(header.record_count)] - chunk = RGPChunk(header, data) - case sqtt.SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION: - header = sqtt.struct_sqtt_file_chunk_pso_correlation.from_buffer_copy(blob, i) - data = [sqtt.struct_sqtt_pso_correlation_record.from_buffer_copy(blob, header.offset+ctypes.sizeof(header)+j*header.record_size) - for j in range(header.record_count)] - chunk = RGPChunk(header, data) - case sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DATA: - header = sqtt.struct_sqtt_file_chunk_sqtt_data.from_buffer_copy(blob, i) - chunk = RGPChunk(header, blob[header.offset:header.offset+header.size]) - case _ if cid in {sqtt.SQTT_FILE_CHUNK_TYPE_ASIC_INFO, sqtt.SQTT_FILE_CHUNK_TYPE_CPU_INFO, sqtt.SQTT_FILE_CHUNK_TYPE_API_INFO, - sqtt.SQTT_FILE_CHUNK_TYPE_SQTT_DESC}: - chunk = RGPChunk(CHUNK_CLASSES[cid].from_buffer_copy(blob, i)) - case _: - chunk = None - print(f"unknown chunk id {cid}") - if chunk is not None: chunks.append(chunk) - i += hdr.size_in_bytes - assert i == len(blob), f'{i} != {len(blob)}' - return RGP(file_header, chunks) - @staticmethod - def from_profile(profile_pickled, device:str|None=None): - profile: list[ProfileEvent] = pickle.loads(profile_pickled) - device_events = {x.device:x for x in profile if isinstance(x, ProfileDeviceEvent) and x.device.startswith('AMD')} - if device is None: - if len(device_events) == 0: raise RuntimeError('No supported devices found in profile') - if len(device_events) > 1: raise RuntimeError(f"More than one supported device found, select which one to export: {', '.join(device_events.keys())}") - _, device_event = device_events.popitem() - else: - if device not in device_events: raise RuntimeError(f"Device {device} not found in profile, devices in profile: {', '.join(device_events.keys())} ") - device_event = device_events[device] - sqtt_events = [x for x in profile if isinstance(x, ProfileSQTTEvent) and x.device == device_event.device] - if len(sqtt_events) == 0: raise RuntimeError(f"Device {device_event.device} doesn't contain SQTT data") - sqtt_itrace_enabled = any([event.itrace for event in sqtt_events]) - sqtt_itrace_masked = not all_same([event.itrace for event in sqtt_events]) - sqtt_itrace_se_mask = functools.reduce(lambda a,b: a|b, [int(event.itrace) << event.se for event in sqtt_events], 0) if sqtt_itrace_masked else 0 - load_events = [x for x in profile if isinstance(x, ProfileProgramEvent) and x.device == device_event.device] - loads = [(event.base, struct.unpack(' bytes: - ret = bytearray() - ret += self.header - for chunk in self.chunks: - ret += chunk.to_bytes(len(ret)) - return bytes(ret) - def print(self): - print(pretty(self.header)) - for chunk in self.chunks: chunk.print() - -if __name__ == '__main__': - parser = argparse.ArgumentParser(prog='rgptool', description='A tool to create (from pickled tinygrad profile), inspect and modify Radeon GPU Profiler files') - parser.add_argument('command') - parser.add_argument('input') - parser.add_argument('-d', '--device') - parser.add_argument('-o', '--output') - args = parser.parse_args() - - with open(args.input, 'rb') as fd: input_bytes = fd.read() - - match args.command: - case 'print': - rgp = RGP.from_bytes(input_bytes) - rgp.print() - case 'create': - rgp = RGP.from_profile(input_bytes, device=args.device) - # rgp.to_bytes() # fixup - # rgp.print() - case 'repl': - rgp = RGP.from_bytes(input_bytes) - code.interact(local=locals()) - case _: raise RuntimeError(args.command) - - if args.output is not None: - with open(args.output, 'wb+') as fd: fd.write(rgp.to_bytes()) diff --git a/tinygrad/extra/sqtt/sqtt.h b/tinygrad/extra/sqtt/sqtt.h deleted file mode 100644 index 77565584..00000000 --- a/tinygrad/extra/sqtt/sqtt.h +++ /dev/null @@ -1,840 +0,0 @@ -#include - -// Original definition in pal is in c++ and clang2py can't autogen it correctly -// Most of this is copy pasted from mesa/src/amd/common/ac_rgp.{h, c} - -/* - * Copyright 2020 Advanced Micro Devices, Inc. - * Copyright 2020 Valve Corporation - * - * SPDX-License-Identifier: MIT - */ - -#define SQTT_FILE_MAGIC_NUMBER 0x50303042 -#define SQTT_FILE_VERSION_MAJOR 1 -#define SQTT_FILE_VERSION_MINOR 5 - -#define SQTT_GPU_NAME_MAX_SIZE 256 -#define SQTT_MAX_NUM_SE 32 -#define SQTT_SA_PER_SE 2 -#define SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS 4 - -struct sqtt_data_info { - uint32_t cur_offset; - uint32_t trace_status; - union { - uint32_t gfx9_write_counter; - uint32_t gfx10_dropped_cntr; - }; -}; - -struct sqtt_data_se { - struct sqtt_data_info info; - void *data_ptr; - uint32_t shader_engine; - uint32_t compute_unit; -}; - - -enum sqtt_version -{ - SQTT_VERSION_NONE = 0x0, - SQTT_VERSION_2_2 = 0x5, /* GFX8 */ - SQTT_VERSION_2_3 = 0x6, /* GFX9 */ - SQTT_VERSION_2_4 = 0x7, /* GFX10+ */ - SQTT_VERSION_3_2 = 0xb, /* GFX11+ */ -}; - -enum sqtt_file_chunk_type -{ - SQTT_FILE_CHUNK_TYPE_ASIC_INFO, - SQTT_FILE_CHUNK_TYPE_SQTT_DESC, - SQTT_FILE_CHUNK_TYPE_SQTT_DATA, - SQTT_FILE_CHUNK_TYPE_API_INFO, - SQTT_FILE_CHUNK_TYPE_RESERVED, - SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS, - SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION, - SQTT_FILE_CHUNK_TYPE_CPU_INFO, - SQTT_FILE_CHUNK_TYPE_SPM_DB, - SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE, - SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS, - SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION, - SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE, - SQTT_FILE_CHUNK_TYPE_COUNT -}; - - -struct sqtt_file_chunk_id { - int32_t type : 8; - int32_t index : 8; - int32_t reserved : 16; -}; - -struct sqtt_file_chunk_header { - struct sqtt_file_chunk_id chunk_id; - uint16_t minor_version; - uint16_t major_version; - int32_t size_in_bytes; - int32_t padding; -}; - -struct sqtt_file_header_flags { - union { - struct { - uint32_t is_semaphore_queue_timing_etw : 1; - uint32_t no_queue_semaphore_timestamps : 1; - uint32_t reserved : 30; - }; - - uint32_t value; - }; -}; - -struct sqtt_file_header { - uint32_t magic_number; - uint32_t version_major; - uint32_t version_minor; - struct sqtt_file_header_flags flags; - int32_t chunk_offset; - int32_t second; - int32_t minute; - int32_t hour; - int32_t day_in_month; - int32_t month; - int32_t year; - int32_t day_in_week; - int32_t day_in_year; - int32_t is_daylight_savings; -}; - -struct sqtt_file_chunk_cpu_info { - struct sqtt_file_chunk_header header; - uint32_t vendor_id[4]; - uint32_t processor_brand[12]; - uint32_t reserved[2]; - uint64_t cpu_timestamp_freq; - uint32_t clock_speed; - uint32_t num_logical_cores; - uint32_t num_physical_cores; - uint32_t system_ram_size; -}; - -enum sqtt_file_chunk_asic_info_flags -{ - SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING = (1 << 0), - SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED = (1 << 1) -}; - -enum sqtt_gpu_type -{ - SQTT_GPU_TYPE_UNKNOWN = 0x0, - SQTT_GPU_TYPE_INTEGRATED = 0x1, - SQTT_GPU_TYPE_DISCRETE = 0x2, - SQTT_GPU_TYPE_VIRTUAL = 0x3 -}; - -enum sqtt_gfxip_level -{ - SQTT_GFXIP_LEVEL_NONE = 0x0, - SQTT_GFXIP_LEVEL_GFXIP_6 = 0x1, - SQTT_GFXIP_LEVEL_GFXIP_7 = 0x2, - SQTT_GFXIP_LEVEL_GFXIP_8 = 0x3, - SQTT_GFXIP_LEVEL_GFXIP_8_1 = 0x4, - SQTT_GFXIP_LEVEL_GFXIP_9 = 0x5, - SQTT_GFXIP_LEVEL_GFXIP_10_1 = 0x7, - SQTT_GFXIP_LEVEL_GFXIP_10_3 = 0x9, - SQTT_GFXIP_LEVEL_GFXIP_11_0 = 0xc, -}; - -enum sqtt_memory_type -{ - SQTT_MEMORY_TYPE_UNKNOWN = 0x0, - SQTT_MEMORY_TYPE_DDR = 0x1, - SQTT_MEMORY_TYPE_DDR2 = 0x2, - SQTT_MEMORY_TYPE_DDR3 = 0x3, - SQTT_MEMORY_TYPE_DDR4 = 0x4, - SQTT_MEMORY_TYPE_DDR5 = 0x5, - SQTT_MEMORY_TYPE_GDDR3 = 0x10, - SQTT_MEMORY_TYPE_GDDR4 = 0x11, - SQTT_MEMORY_TYPE_GDDR5 = 0x12, - SQTT_MEMORY_TYPE_GDDR6 = 0x13, - SQTT_MEMORY_TYPE_HBM = 0x20, - SQTT_MEMORY_TYPE_HBM2 = 0x21, - SQTT_MEMORY_TYPE_HBM3 = 0x22, - SQTT_MEMORY_TYPE_LPDDR4 = 0x30, - SQTT_MEMORY_TYPE_LPDDR5 = 0x31, -}; - -struct sqtt_file_chunk_asic_info { - struct sqtt_file_chunk_header header; - uint64_t flags; - uint64_t trace_shader_core_clock; - uint64_t trace_memory_clock; - int32_t device_id; - int32_t device_revision_id; - int32_t vgprs_per_simd; - int32_t sgprs_per_simd; - int32_t shader_engines; - int32_t compute_unit_per_shader_engine; - int32_t simd_per_compute_unit; - int32_t wavefronts_per_simd; - int32_t minimum_vgpr_alloc; - int32_t vgpr_alloc_granularity; - int32_t minimum_sgpr_alloc; - int32_t sgpr_alloc_granularity; - int32_t hardware_contexts; - enum sqtt_gpu_type gpu_type; - enum sqtt_gfxip_level gfxip_level; - int32_t gpu_index; - int32_t gds_size; - int32_t gds_per_shader_engine; - int32_t ce_ram_size; - int32_t ce_ram_size_graphics; - int32_t ce_ram_size_compute; - int32_t max_number_of_dedicated_cus; - int64_t vram_size; - int32_t vram_bus_width; - int32_t l2_cache_size; - int32_t l1_cache_size; - int32_t lds_size; - char gpu_name[SQTT_GPU_NAME_MAX_SIZE]; - float alu_per_clock; - float texture_per_clock; - float prims_per_clock; - float pixels_per_clock; - uint64_t gpu_timestamp_frequency; - uint64_t max_shader_core_clock; - uint64_t max_memory_clock; - uint32_t memory_ops_per_clock; - enum sqtt_memory_type memory_chip_type; - uint32_t lds_granularity; - uint16_t cu_mask[SQTT_MAX_NUM_SE][SQTT_SA_PER_SE]; - char reserved1[128]; - uint32_t active_pixel_packer_mask[SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS]; - char reserved2[16]; - uint32_t gl1_cache_size; - uint32_t instruction_cache_size; - uint32_t scalar_cache_size; - uint32_t mall_cache_size; - char padding[4]; -}; - -enum sqtt_api_type -{ - SQTT_API_TYPE_DIRECTX_12, - SQTT_API_TYPE_VULKAN, - SQTT_API_TYPE_GENERIC, - SQTT_API_TYPE_OPENCL -}; - -enum sqtt_instruction_trace_mode -{ - SQTT_INSTRUCTION_TRACE_DISABLED = 0x0, - SQTT_INSTRUCTION_TRACE_FULL_FRAME = 0x1, - SQTT_INSTRUCTION_TRACE_API_PSO = 0x2, -}; - -enum sqtt_profiling_mode -{ - SQTT_PROFILING_MODE_PRESENT = 0x0, - SQTT_PROFILING_MODE_USER_MARKERS = 0x1, - SQTT_PROFILING_MODE_INDEX = 0x2, - SQTT_PROFILING_MODE_TAG = 0x3, -}; - -union sqtt_profiling_mode_data { - struct { - char start[256]; - char end[256]; - } user_marker_profiling_data; - - struct { - uint32_t start; - uint32_t end; - } index_profiling_data; - - struct { - uint32_t begin_hi; - uint32_t begin_lo; - uint32_t end_hi; - uint32_t end_lo; - } tag_profiling_data; -}; - -union sqtt_instruction_trace_data { - struct { - uint64_t api_pso_filter; - } api_pso_data; - - struct { - uint32_t mask; - } shader_engine_filter; -}; - -struct sqtt_file_chunk_api_info { - struct sqtt_file_chunk_header header; - enum sqtt_api_type api_type; - uint16_t major_version; - uint16_t minor_version; - enum sqtt_profiling_mode profiling_mode; - uint32_t reserved; - union sqtt_profiling_mode_data profiling_mode_data; - enum sqtt_instruction_trace_mode instruction_trace_mode; - uint32_t reserved2; - union sqtt_instruction_trace_data instruction_trace_data; -}; - - -struct sqtt_code_object_database_record { - uint32_t size; -}; - -struct sqtt_file_chunk_code_object_database { - struct sqtt_file_chunk_header header; - uint32_t offset; - uint32_t flags; - uint32_t size; - uint32_t record_count; -}; - - -struct sqtt_code_object_loader_events_record { - uint32_t loader_event_type; - uint32_t reserved; - uint64_t base_address; - uint64_t code_object_hash[2]; - uint64_t time_stamp; -}; - -struct sqtt_file_chunk_code_object_loader_events { - struct sqtt_file_chunk_header header; - uint32_t offset; - uint32_t flags; - uint32_t record_size; - uint32_t record_count; -}; - -struct sqtt_pso_correlation_record { - uint64_t api_pso_hash; - uint64_t pipeline_hash[2]; - char api_level_obj_name[64]; -}; - -struct sqtt_file_chunk_pso_correlation { - struct sqtt_file_chunk_header header; - uint32_t offset; - uint32_t flags; - uint32_t record_size; - uint32_t record_count; -}; - -struct sqtt_file_chunk_sqtt_desc { - struct sqtt_file_chunk_header header; - int32_t shader_engine_index; - enum sqtt_version sqtt_version; - union { - struct { - int32_t instrumentation_version; - } v0; - struct { - int16_t instrumentation_spec_version; - int16_t instrumentation_api_version; - int32_t compute_unit_index; - } v1; - }; -}; - -struct sqtt_file_chunk_sqtt_data { - struct sqtt_file_chunk_header header; - int32_t offset; /* in bytes */ - int32_t size; /* in bytes */ -}; - -struct sqtt_file_chunk_queue_event_timings { - struct sqtt_file_chunk_header header; - uint32_t queue_info_table_record_count; - uint32_t queue_info_table_size; - uint32_t queue_event_table_record_count; - uint32_t queue_event_table_size; -}; - - -enum sqtt_queue_type { - SQTT_QUEUE_TYPE_UNKNOWN = 0x0, - SQTT_QUEUE_TYPE_UNIVERSAL = 0x1, - SQTT_QUEUE_TYPE_COMPUTE = 0x2, - SQTT_QUEUE_TYPE_DMA = 0x3, -}; - -enum sqtt_engine_type { - SQTT_ENGINE_TYPE_UNKNOWN = 0x0, - SQTT_ENGINE_TYPE_UNIVERSAL = 0x1, - SQTT_ENGINE_TYPE_COMPUTE = 0x2, - SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = 0x3, - SQTT_ENGINE_TYPE_DMA = 0x4, - SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = 0x7, - SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = 0x8, -}; - -struct sqtt_queue_hardware_info { - union { - struct { - int32_t queue_type : 8; - int32_t engine_type : 8; - uint32_t reserved : 16; - }; - uint32_t value; - }; -}; - - -struct sqtt_queue_info_record { - uint64_t queue_id; - uint64_t queue_context; - struct sqtt_queue_hardware_info hardware_info; - uint32_t reserved; -}; - -enum sqtt_queue_event_type { - SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT, - SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE, - SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE, - SQTT_QUEUE_TIMING_EVENT_PRESENT -}; - -struct sqtt_queue_event_record { - enum sqtt_queue_event_type event_type; - uint32_t sqtt_cb_id; - uint64_t frame_index; - uint32_t queue_info_index; - uint32_t submit_sub_index; - uint64_t api_id; - uint64_t cpu_timestamp; - uint64_t gpu_timestamps[2]; -}; - -struct sqtt_file_chunk_clock_calibration { - struct sqtt_file_chunk_header header; - uint64_t cpu_timestamp; - uint64_t gpu_timestamp; - uint64_t reserved; -}; - -enum elf_gfxip_level -{ - EF_AMDGPU_MACH_AMDGCN_GFX801 = 0x028, - EF_AMDGPU_MACH_AMDGCN_GFX900 = 0x02c, - EF_AMDGPU_MACH_AMDGCN_GFX1010 = 0x033, - EF_AMDGPU_MACH_AMDGCN_GFX1030 = 0x036, - EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041, -}; - -struct sqtt_file_chunk_spm_db { - struct sqtt_file_chunk_header header; - uint32_t flags; - uint32_t preamble_size; - uint32_t num_timestamps; - uint32_t num_spm_counter_info; - uint32_t spm_counter_info_size; - uint32_t sample_interval; -}; - -/** - * Identifiers for RGP SQ thread-tracing markers (Table 1) - */ -enum rgp_sqtt_marker_identifier -{ - RGP_SQTT_MARKER_IDENTIFIER_EVENT = 0x0, - RGP_SQTT_MARKER_IDENTIFIER_CB_START = 0x1, - RGP_SQTT_MARKER_IDENTIFIER_CB_END = 0x2, - RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START = 0x3, - RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END = 0x4, - RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT = 0x5, - RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API = 0x6, - RGP_SQTT_MARKER_IDENTIFIER_SYNC = 0x7, - RGP_SQTT_MARKER_IDENTIFIER_PRESENT = 0x8, - RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION = 0x9, - RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS = 0xA, - RGP_SQTT_MARKER_IDENTIFIER_RESERVED2 = 0xB, - RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE = 0xC, - RGP_SQTT_MARKER_IDENTIFIER_RESERVED4 = 0xD, - RGP_SQTT_MARKER_IDENTIFIER_RESERVED5 = 0xE, - RGP_SQTT_MARKER_IDENTIFIER_RESERVED6 = 0xF -}; - -/** - * Command buffer IDs used in RGP SQ thread-tracing markers (only 20 bits). - */ -union rgp_sqtt_marker_cb_id { - struct { - uint32_t per_frame : 1; /* Must be 1, frame-based command buffer ID. */ - uint32_t frame_index : 7; - uint32_t cb_index : 12; /* Command buffer index within the frame. */ - uint32_t reserved : 12; - } per_frame_cb_id; - - struct { - uint32_t per_frame : 1; /* Must be 0, global command buffer ID. */ - uint32_t cb_index : 19; /* Global command buffer index. */ - uint32_t reserved : 12; - } global_cb_id; - - uint32_t all; -}; - -/** - * RGP SQ thread-tracing marker for the start of a command buffer. (Table 2) - */ -struct rgp_sqtt_marker_cb_start { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t cb_id : 20; - uint32_t queue : 5; - }; - uint32_t dword01; - }; - union { - uint32_t device_id_low; - uint32_t dword02; - }; - union { - uint32_t device_id_high; - uint32_t dword03; - }; - union { - uint32_t queue_flags; - uint32_t dword04; - }; -}; - -/** - * - * RGP SQ thread-tracing marker for the end of a command buffer. (Table 3) - */ -struct rgp_sqtt_marker_cb_end { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t cb_id : 20; - uint32_t reserved : 5; - }; - uint32_t dword01; - }; - union { - uint32_t device_id_low; - uint32_t dword02; - }; - union { - uint32_t device_id_high; - uint32_t dword03; - }; -}; - -/** - * API types used in RGP SQ thread-tracing markers for the "General API" - * packet. - */ -enum rgp_sqtt_marker_general_api_type -{ - ApiCmdBindPipeline = 0, - ApiCmdBindDescriptorSets = 1, - ApiCmdBindIndexBuffer = 2, - ApiCmdBindVertexBuffers = 3, - ApiCmdDraw = 4, - ApiCmdDrawIndexed = 5, - ApiCmdDrawIndirect = 6, - ApiCmdDrawIndexedIndirect = 7, - ApiCmdDrawIndirectCountAMD = 8, - ApiCmdDrawIndexedIndirectCountAMD = 9, - ApiCmdDispatch = 10, - ApiCmdDispatchIndirect = 11, - ApiCmdCopyBuffer = 12, - ApiCmdCopyImage = 13, - ApiCmdBlitImage = 14, - ApiCmdCopyBufferToImage = 15, - ApiCmdCopyImageToBuffer = 16, - ApiCmdUpdateBuffer = 17, - ApiCmdFillBuffer = 18, - ApiCmdClearColorImage = 19, - ApiCmdClearDepthStencilImage = 20, - ApiCmdClearAttachments = 21, - ApiCmdResolveImage = 22, - ApiCmdWaitEvents = 23, - ApiCmdPipelineBarrier = 24, - ApiCmdBeginQuery = 25, - ApiCmdEndQuery = 26, - ApiCmdResetQueryPool = 27, - ApiCmdWriteTimestamp = 28, - ApiCmdCopyQueryPoolResults = 29, - ApiCmdPushConstants = 30, - ApiCmdBeginRenderPass = 31, - ApiCmdNextSubpass = 32, - ApiCmdEndRenderPass = 33, - ApiCmdExecuteCommands = 34, - ApiCmdSetViewport = 35, - ApiCmdSetScissor = 36, - ApiCmdSetLineWidth = 37, - ApiCmdSetDepthBias = 38, - ApiCmdSetBlendConstants = 39, - ApiCmdSetDepthBounds = 40, - ApiCmdSetStencilCompareMask = 41, - ApiCmdSetStencilWriteMask = 42, - ApiCmdSetStencilReference = 43, - ApiCmdDrawIndirectCount = 44, - ApiCmdDrawIndexedIndirectCount = 45, - /* gap */ - ApiCmdDrawMeshTasksEXT = 47, - ApiCmdDrawMeshTasksIndirectCountEXT = 48, - ApiCmdDrawMeshTasksIndirectEXT = 49, - - ApiRayTracingSeparateCompiled = 0x800000, - ApiInvalid = 0xffffffff -}; - -/** - * RGP SQ thread-tracing marker for a "General API" instrumentation packet. - */ -struct rgp_sqtt_marker_general_api { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t api_type : 20; - uint32_t is_end : 1; - uint32_t reserved : 4; - }; - uint32_t dword01; - }; -}; - -/** - * API types used in RGP SQ thread-tracing markers (Table 16). - */ -enum rgp_sqtt_marker_event_type -{ - EventCmdDraw = 0, - EventCmdDrawIndexed = 1, - EventCmdDrawIndirect = 2, - EventCmdDrawIndexedIndirect = 3, - EventCmdDrawIndirectCountAMD = 4, - EventCmdDrawIndexedIndirectCountAMD = 5, - EventCmdDispatch = 6, - EventCmdDispatchIndirect = 7, - EventCmdCopyBuffer = 8, - EventCmdCopyImage = 9, - EventCmdBlitImage = 10, - EventCmdCopyBufferToImage = 11, - EventCmdCopyImageToBuffer = 12, - EventCmdUpdateBuffer = 13, - EventCmdFillBuffer = 14, - EventCmdClearColorImage = 15, - EventCmdClearDepthStencilImage = 16, - EventCmdClearAttachments = 17, - EventCmdResolveImage = 18, - EventCmdWaitEvents = 19, - EventCmdPipelineBarrier = 20, - EventCmdResetQueryPool = 21, - EventCmdCopyQueryPoolResults = 22, - EventRenderPassColorClear = 23, - EventRenderPassDepthStencilClear = 24, - EventRenderPassResolve = 25, - EventInternalUnknown = 26, - EventCmdDrawIndirectCount = 27, - EventCmdDrawIndexedIndirectCount = 28, - /* gap */ - EventCmdTraceRaysKHR = 30, - EventCmdTraceRaysIndirectKHR = 31, - EventCmdBuildAccelerationStructuresKHR = 32, - EventCmdBuildAccelerationStructuresIndirectKHR = 33, - EventCmdCopyAccelerationStructureKHR = 34, - EventCmdCopyAccelerationStructureToMemoryKHR = 35, - EventCmdCopyMemoryToAccelerationStructureKHR = 36, - /* gap */ - EventCmdDrawMeshTasksEXT = 41, - EventCmdDrawMeshTasksIndirectCountEXT = 42, - EventCmdDrawMeshTasksIndirectEXT = 43, - EventUnknown = 0x7fff, - EventInvalid = 0xffffffff -}; - -/** - * "Event (Per-draw/dispatch)" RGP SQ thread-tracing marker. (Table 4) - */ -struct rgp_sqtt_marker_event { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t api_type : 24; - uint32_t has_thread_dims : 1; - }; - uint32_t dword01; - }; - union { - struct { - uint32_t cb_id : 20; - uint32_t vertex_offset_reg_idx : 4; - uint32_t instance_offset_reg_idx : 4; - uint32_t draw_index_reg_idx : 4; - }; - uint32_t dword02; - }; - union { - uint32_t cmd_id; - uint32_t dword03; - }; -}; - -/** - * Per-dispatch specific marker where workgroup dims are included. - */ -struct rgp_sqtt_marker_event_with_dims { - struct rgp_sqtt_marker_event event; - uint32_t thread_x; - uint32_t thread_y; - uint32_t thread_z; -}; - -/** - * "Barrier Start" RGP SQTT instrumentation marker (Table 5) - */ -struct rgp_sqtt_marker_barrier_start { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t cb_id : 20; - uint32_t reserved : 5; - }; - uint32_t dword01; - }; - union { - struct { - uint32_t driver_reason : 31; - uint32_t internal : 1; - }; - uint32_t dword02; - }; -}; - -/** - * "Barrier End" RGP SQTT instrumentation marker (Table 6) - */ -struct rgp_sqtt_marker_barrier_end { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t cb_id : 20; - uint32_t wait_on_eop_ts : 1; - uint32_t vs_partial_flush : 1; - uint32_t ps_partial_flush : 1; - uint32_t cs_partial_flush : 1; - uint32_t pfp_sync_me : 1; - }; - uint32_t dword01; - }; - union { - struct { - uint32_t sync_cp_dma : 1; - uint32_t inval_tcp : 1; - uint32_t inval_sqI : 1; - uint32_t inval_sqK : 1; - uint32_t flush_tcc : 1; - uint32_t inval_tcc : 1; - uint32_t flush_cb : 1; - uint32_t inval_cb : 1; - uint32_t flush_db : 1; - uint32_t inval_db : 1; - uint32_t num_layout_transitions : 16; - uint32_t inval_gl1 : 1; - uint32_t wait_on_ts : 1; - uint32_t eop_ts_bottom_of_pipe : 1; - uint32_t eos_ts_ps_done : 1; - uint32_t eos_ts_cs_done : 1; - uint32_t reserved : 1; - }; - uint32_t dword02; - }; -}; - -/** - * "Layout Transition" RGP SQTT instrumentation marker (Table 7) - */ -struct rgp_sqtt_marker_layout_transition { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t depth_stencil_expand : 1; - uint32_t htile_hiz_range_expand : 1; - uint32_t depth_stencil_resummarize : 1; - uint32_t dcc_decompress : 1; - uint32_t fmask_decompress : 1; - uint32_t fast_clear_eliminate : 1; - uint32_t fmask_color_expand : 1; - uint32_t init_mask_ram : 1; - uint32_t reserved1 : 17; - }; - uint32_t dword01; - }; - union { - struct { - uint32_t reserved2 : 32; - }; - uint32_t dword02; - }; -}; - -/** - * "User Event" RGP SQTT instrumentation marker (Table 8) - */ -struct rgp_sqtt_marker_user_event { - union { - struct { - uint32_t identifier : 4; - uint32_t reserved0 : 8; - uint32_t data_type : 8; - uint32_t reserved1 : 12; - }; - uint32_t dword01; - }; -}; -struct rgp_sqtt_marker_user_event_with_length { - struct rgp_sqtt_marker_user_event user_event; - uint32_t length; -}; - -enum rgp_sqtt_marker_user_event_type -{ - UserEventTrigger = 0, - UserEventPop, - UserEventPush, - UserEventObjectName, -}; - -/** - * "Pipeline bind" RGP SQTT instrumentation marker (Table 12) - */ -struct rgp_sqtt_marker_pipeline_bind { - union { - struct { - uint32_t identifier : 4; - uint32_t ext_dwords : 3; - uint32_t bind_point : 1; - uint32_t cb_id : 20; - uint32_t reserved : 4; - }; - uint32_t dword01; - }; - union { - uint32_t api_pso_hash[2]; - struct { - uint32_t dword02; - uint32_t dword03; - }; - }; -}; diff --git a/tinygrad/extra/thneed.py b/tinygrad/extra/thneed.py deleted file mode 100644 index c59f6368..00000000 --- a/tinygrad/extra/thneed.py +++ /dev/null @@ -1,287 +0,0 @@ -# this can be constructed from a cl_cache or loaded from a thneed file -import time -import struct -import json -import traceback -import numpy as np -from tinygrad.runtime.ops_gpu import CLProgram, compile_gpu -from tinygrad.device import Device -from tinygrad.helpers import DEBUG, getenv -from collections import defaultdict -import pyopencl as cl -from tinygrad.runtime.ops_gpu import OSX_TIMING_RATIO -CL = Device["GPU"] - -DEBUGCL = getenv("DEBUGCL", 0) -FLOAT16 = getenv("FLOAT16", 0) - -class Thneed: - def __init__(self, cl_cache=[], inputs={}): - self.cl_cache, self.inputs = cl_cache[:], inputs - self.gobj = 0 - - # build graph - # NOTE: if CLCACHE=1, this is wrong! - nodes = defaultdict(lambda: {'in_edges': [], 'out_edges': []}) - for _, args in self.cl_cache: - # output is always the first parameter - for a in args[3:]: - nodes[a]['out_edges'].append(args[2]) - nodes[args[2]]['in_edges'].append(a) - - # get buffers to save - self.buffers_to_save = set() - self.outputs = [] - for n in nodes.keys(): - if len(nodes[n]['in_edges']) == 0: - self.buffers_to_save.add(n) - if len(nodes[n]['out_edges']) == 0: - self.outputs.append(n) - - fake_inputs = [] - for k,n in self.inputs.items(): - if n in self.buffers_to_save: - self.buffers_to_save.remove(n) - else: - print(f"WARNING: {k} was not a used input, removing it") - fake_inputs.append(k) - for k in fake_inputs: - del self.inputs[k] - - def load(self, input_fn): - float32 = not FLOAT16 - - mf = cl.mem_flags - image_fmt = cl.ImageFormat(cl.channel_order.RGBA, cl.channel_type.FLOAT if float32 else cl.channel_type.HALF_FLOAT) - image_fmt_32 = cl.ImageFormat(cl.channel_order.RGBA, cl.channel_type.FLOAT) - - with open(input_fn, "rb") as f: - json_len = struct.unpack("I", f.read(4))[0] - jdat = json.loads(f.read(json_len).decode('latin_1')) - weights = f.read() - - # load in the buffers - bufs = {'\x00\x00\x00\x00\x00\x00\x00\x00': None} - bufs_loaded = {} - ptr = 0 - for o in jdat['objects']: - #print(o) - if o['needs_load']: - nptr = ptr + o['size'] - o['data'] = weights[ptr:nptr] - ptr = nptr - - if o['arg_type'] == "image2d_t" or o['arg_type'] == "image1d_t": - tfmt = image_fmt_32 if 'float32' in o and o['float32'] else image_fmt - if o['arg_type'] == "image2d_t": - if 'buffer_id' in o and o['height'] == 1 and not bufs_loaded[o['buffer_id']]: - # hack: use a image1d since we can back that with a buffer - buf = cl.Image(CL.ctx, mf.READ_WRITE, tfmt, shape=(o['width'],), buffer=bufs[o['buffer_id']]) - else: - # buffer isn't supported in image2d, copy buffer into image - if 'buffer_id' in o and bufs_loaded[o['buffer_id']]: - arr = np.zeros(bufs[o['buffer_id']].size // 2, dtype=np.float16) - cl.enqueue_copy(CL.queue, arr, bufs[o['buffer_id']]) - buf = cl.Image(CL.ctx, mf.READ_WRITE | mf.COPY_HOST_PTR, tfmt, - shape=(o['width'], o['height']), pitches=(o['row_pitch'],), hostbuf=arr) - elif o['needs_load']: - buf = cl.Image(CL.ctx, mf.READ_WRITE | mf.COPY_HOST_PTR, tfmt, - shape=(o['width'], o['height']), pitches=(o['row_pitch'],), hostbuf=o['data']) - else: - buf = cl.Image(CL.ctx, mf.READ_WRITE, tfmt, shape=(o['width'], o['height'])) - if o['arg_type'] == "image1d_t": - assert not o['needs_load'] - assert not bufs_loaded[o['buffer_id']] - buf = cl.Image(CL.ctx, mf.READ_WRITE, tfmt, shape=(o['width'],), buffer=bufs[o['buffer_id']]) - else: - if 'data' in o: - buf = cl.Buffer(CL.ctx, mf.READ_WRITE | mf.COPY_HOST_PTR, hostbuf=o['data']) - else: - # zero out buffers - buf = cl.Buffer(CL.ctx, mf.READ_WRITE | mf.COPY_HOST_PTR, hostbuf=b'\x00'*o['size']) - - bufs[o['id']] = buf - bufs_loaded[o['id']] = 'data' in o - # if it's loaded, it's saved - if 'data' in o: - self.buffers_to_save.add(buf) - - # load binaries - prgs = {} - for o in jdat['binaries']: - nptr = ptr + o['length'] - prgs[o['name']] = CLProgram(Device["GPU"], o['name'], weights[ptr:nptr]) - ptr = nptr - - # populate the cl_cache - for i,k in enumerate(jdat['kernels']): - kernel = prgs[k['name']] - aaa = [] - for j,(a,sz) in enumerate(zip(k['args'], k['args_size'])): - if len(a) == 0: - aa = cl.LocalMemory(sz) - elif len(a) == 4: - a = a.encode('latin_1') - aa = np.uint32(struct.unpack("I", a)[0]) - elif len(a) == 2: - a = a.encode('latin_1') - aa = np.uint16(struct.unpack("H", a)[0]) - elif len(a) == 8: - #print(i,j,struct.unpack("Q", a.encode('latin_1'))[0]) - aa = bufs[a] - aaa.append(aa) - self.cl_cache.append((kernel, [k['global_work_size'], k['local_work_size'], *aaa])) - - if DEBUG >= 1: print(f"thneed: total bufs loaded: {len(bufs.keys())}") - - # load inputs - for k in jdat['inputs']: - self.inputs[k['name']] = bufs[k['buffer_id']] - - # load outputs - for k in jdat['outputs']: - self.outputs.append(bufs[k['buffer_id']]) - - - def save(self, output_fn): - # this is the struct that will be saved - jdat = {"binaries": [], "programs": {}, "kernels": [], "objects": []} - - # build the pieces of this struct - weights = [] - binaries = [] - saved_objs = set() - saved_binaries = set() - for prg, args in self.cl_cache: - # get binaries for saving - if prg.name not in saved_binaries: - binary = prg.clprogram.get_info(cl.program_info.BINARIES) - assert len(binary) == 1 - jdat['binaries'].append({"name":prg.name, "length":len(binary[0])}) - binaries.append(binary[0]) - saved_binaries.add(prg.name) - - # get the args from the kernel, some need the data saved - targs, args_size = [], [] - argdtypes = [None]*(len(args)-2) - for a,d in zip(args[2:], argdtypes): - if d == np.int16: - targs.append(struct.pack("H", a).decode("latin_1")) - args_size.append(2) - elif d == np.int32: - targs.append(struct.pack("I", a).decode("latin_1")) - args_size.append(4) - elif isinstance(a, cl.LocalMemory): - targs.append("") - args_size.append(a.size) - elif d is None: - if getattr(a, "global_id", None) is None: - setattr(a, "global_id", self.gobj) - self.gobj += 1 - ptr = struct.pack("Q", a.global_id).decode("latin_1") - if ptr not in saved_objs: - if isinstance(a, cl.Buffer): - needs_load = a in self.buffers_to_save - jdat['objects'].append({ - "id": ptr, "arg_type": "float*", "needs_load": needs_load, "size": a.size, - }) - if needs_load: - data = np.empty(a.size//4, dtype=np.float32) - cl.enqueue_copy(CL.queue, data, a, is_blocking=True) - weights.append(data.tobytes()) - elif isinstance(a, cl.Image): - assert a.format == cl.ImageFormat(cl.channel_order.RGBA, cl.channel_type.HALF_FLOAT if FLOAT16 else cl.channel_type.FLOAT), "wrong type" - needs_load = a in self.buffers_to_save - row_pitch = (a.shape[0]*4*(2 if FLOAT16 else 4) + 63)//64 * 64 - size = row_pitch * a.shape[1] - # this is *2 if float16 and *4 if float32 - buf = cl.Buffer(CL.ctx, cl.mem_flags.READ_WRITE, size=size * (2 if FLOAT16 else 1)) - - # zero out the buffer - cl.enqueue_copy(CL.queue, buf, b'\x00'*buf.size, is_blocking=True) - - CLProgram(CL, "from_image_strided", compile_gpu(""" - __kernel void from_image_strided(read_only image2d_t in, __global float4 *out, int row_pitch) { - const sampler_t smp = CLK_NORMALIZED_COORDS_FALSE | CLK_ADDRESS_CLAMP | CLK_FILTER_NEAREST; - int2 l; - l.y = get_global_id(1); - l.x = get_global_id(0); - out[l.y*row_pitch + l.x] = read_imagef(in, smp, l); - } - """), bufs=2, vars=1)(a, buf, row_pitch//(4*(2 if FLOAT16 else 4)), global_size=a.shape) - - # multiple of 32 isn't enough - jdat['objects'].append({ - "id": ptr, "needs_load": needs_load, "size": size, "arg_type": "image2d_t", - "width": a.shape[0], "height": a.shape[1], "row_pitch": row_pitch, "float32": not FLOAT16, - }) - - if needs_load: - data = np.empty(size//(2 if FLOAT16 else 4), dtype=np.float32) - cl.enqueue_copy(CL.queue, data, buf, is_blocking=True) - if FLOAT16: data = data.astype(np.float16) - weights.append(data.tobytes()) - else: - raise Exception("unknown object", a) - #print(jdat['objects'][-1]) - saved_objs.add(ptr) - targs.append(ptr) - args_size.append(8) - else: - raise Exception("idk this type") - - # save the kernel itself - jdat['kernels'].append({ - "name": prg.name, - "work_dim": len(args[0]), - "global_work_size": args[0], - # TODO: C++ thneed requires a local_work_size, so we fill it with ones - "local_work_size": [1 for _ in args[0]] if args[1] is None else args[1], - "num_args": len(args)-2, - "args": targs, - "args_size": args_size - }) - - jdat['outputs'] = [{ - "buffer_id": struct.pack("Q", x.global_id).decode("latin_1"), - "size": x.size, - } for x in self.outputs] - - jdat['inputs'] = [{ - "buffer_id": struct.pack("Q", v.global_id).decode("latin_1"), - "size": v.size, - "name": k - } for k,v in self.inputs.items()][::-1] - - print(f"saving thneed to {output_fn}") - with open(output_fn, "wb") as f: - j = json.dumps(jdat, ensure_ascii=False).encode('latin_1') - f.write(struct.pack("I", len(j))) - f.write(j) - f.write(b''.join(weights)) - f.write(b''.join(binaries)) - - def run(self): - events = [] - st = time.monotonic() - for prg, args in self.cl_cache: - events.append(prg.clprg(CL.queue, *args)) - mt = time.monotonic() - Device["GPU"].synchronize() - et = time.monotonic() - st - print(f"submit in {(mt-st)*1000.0:.2f} ms, total runtime is {et*1000.0:.2f} ms") - - if DEBUGCL >= 2: - for i, ((prg, args), e) in enumerate(zip(self.cl_cache, events)): - print(f"{i:3d} {prg.name:25s} " + "queued @ %5.2f ms, submit @ %5.2fms, start @ %5.2f ms, end @ %5.2f ms" % tuple((x*OSX_TIMING_RATIO - st*1e9)/1e6 for x in [e.profile.queued, e.profile.submit, e.profile.start, e.profile.end])) - if DEBUGCL >= 1: - total_runtime = 0 - for i, ((prg, args), e) in enumerate(zip(self.cl_cache, events)): - runtime = (e.profile.end - e.profile.start) * OSX_TIMING_RATIO - print(f"{i:3d} time {total_runtime/1e6:5.2f} ms running {prg.name:25s} with {str(args[0]):15s} {str(args[1]):15s} count {len(args)-2:2d} runtime {runtime/1e3:7.2f} us {(getattr(prg, 'op_estimate', float('nan')))/runtime:9.2f} GFLOPS -> {args[2].shape if hasattr(args[2], 'shape') else args[2].size}") - if hasattr(prg, 'prg') and ((DEBUGCL >= 2 and getenv("PRINT_KERNEL", -1) == i) or DEBUGCL >= 3): - print(prg.prg) - total_runtime += runtime - print(f"total runtime: {total_runtime/1e6:.2f} ms wall time: {et*1000.0:.2f} ms") - return total_runtime/1e9 - return et diff --git a/tinygrad/extra/threefry.py b/tinygrad/extra/threefry.py deleted file mode 100644 index 6de61734..00000000 --- a/tinygrad/extra/threefry.py +++ /dev/null @@ -1,16 +0,0 @@ -if __name__ == "__main__": - import os - if "DEBUG" not in os.environ: os.environ["DEBUG"] = "2" - - from tinygrad import Tensor, GlobalCounters - from tinygrad.helpers import getenv - - if (seed := getenv("SEED", 0)) != 0: - Tensor.manual_seed(seed) - print(f"using seed {Tensor._seed}") - - for N in [10_000_000, 100_000_000, 1_000_000_000]: - GlobalCounters.reset() - t = Tensor.rand(N) - t.realize() - print(f"N {N:>20_}, global_ops {GlobalCounters.global_ops:>20_}, global_mem {GlobalCounters.global_mem:>20_}") diff --git a/tinygrad/extra/to_movement_ops.py b/tinygrad/extra/to_movement_ops.py deleted file mode 100644 index 68d4ef3d..00000000 --- a/tinygrad/extra/to_movement_ops.py +++ /dev/null @@ -1,154 +0,0 @@ -import itertools -from enum import Enum, auto -from collections import defaultdict -from typing import List, Tuple, DefaultDict -from extra.optimization.helpers import load_worlds, ast_str_to_ast -from tinygrad.helpers import prod, tqdm -from tinygrad.uop.ops import UOp, Ops -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.uop.ops import sym_infer -from tinygrad.tensor import Tensor - -class MovementOps(Enum): RESHAPE = auto(); PERMUTE = auto(); EXPAND = auto(); PAD = auto(); SHRINK = auto(); STRIDE = auto(); AS_STRIDED = auto() # noqa: E702 - -def apply_mop(st: Tensor|ShapeTracker, mop_arg: Tuple[MovementOps, Tuple]) -> ShapeTracker: - mop, arg = mop_arg - if mop == MovementOps.RESHAPE: - # shapetracker doesn't allow flattening with -1 but required for MovementOps.RESHAPE - if arg == (-1,): return st.reshape((prod(st.shape),)) - return st.reshape(arg) - if mop == MovementOps.PERMUTE: return st.permute(arg) - if mop == MovementOps.EXPAND: - if len(arg) != len(st.shape): st = st.reshape((1,*st.shape)) - return st.expand(arg) - if mop == MovementOps.PAD: return st.pad(arg) - if mop == MovementOps.SHRINK: return st.shrink(arg) - if mop == MovementOps.STRIDE: - assert all(x in [-1, 1] for x in arg) - return st.flip(tuple(i for i,x in enumerate(arg) if x == -1)) - raise ValueError("invalid mop") - -def make_scratch_st(st: ShapeTracker) -> ShapeTracker: - return ShapeTracker.from_shape((get_buffer_size(st.views[0].shape, st.views[0].strides, st.views[0].offset, st.views[0].mask),)) - -# ShapeTracker to an equivalent series of MovementOps (https://github.com/tinygrad/tinygrad/pull/2216) -def to_movement_ops(st: ShapeTracker) -> List[Tuple[MovementOps, Tuple]]: - to_apply:List[Tuple[MovementOps, Tuple]] = [] - for i, v in enumerate(st.views): - real_shape = tuple(y-x for x,y in v.mask) if v.mask else v.shape - offset = v.offset + sum(st*(s-1) for s,st in zip(real_shape, v.strides) if st<0) - real_offset = offset + (sum(x*st for (x,_),st in zip(v.mask, v.strides)) if v.mask else 0) - real_real_shape = [s for s,st in zip(real_shape, v.strides) if st] - strides: List[int] = [abs(st) if isinstance(st,int) else st for st in v.strides if st] - buffer_size = sum((s-1)*st for s,st in zip(real_real_shape,strides)) + 1 - if i: buffer_size = prod(st.views[i-1].shape) - real_offset if real_shape else 1 - def sort_by_strides(shape, strides): return sorted(zip(shape, strides), key=lambda k: (k[1],-k[0]), reverse=True), sorted(range(len(strides)), key=lambda k: (strides[k],-real_real_shape[k]), reverse=True) - ordered_shape_strides, order = sort_by_strides(real_real_shape, strides) - to_apply.extend([(MovementOps.RESHAPE, (-1,)), (MovementOps.SHRINK, ((real_offset, real_offset+buffer_size),))]) - if strides: - if (ordered_shape_strides[0][0]*ordered_shape_strides[0][1])-buffer_size>0: to_apply.append((MovementOps.PAD, ((0, (ordered_shape_strides[0][0] * ordered_shape_strides[0][1]) - buffer_size),))) - for i, shape_stride in enumerate(ordered_shape_strides): - if i0 else buffer_size - to_apply.append((MovementOps.EXPAND, (shape_stride[0], *(s[0] for s in ordered_shape_strides[:i]), remaining_buffer))) - to_apply.append((MovementOps.PERMUTE, (*range(1,i+1), 0, i+1))) - to_apply.append((MovementOps.RESHAPE, (*(s[0] for s in ordered_shape_strides[:i]), shape_stride[0]*remaining_buffer))) - to_apply.append((MovementOps.PAD, (*((0,0) for _ in range(i)), (0, shape_stride[0]*shape_stride[1])))) - to_apply.append((MovementOps.RESHAPE, (*(s[0] for s in ordered_shape_strides[:i+1]), remaining_buffer+shape_stride[1]))) - ordered_shape_strides[i] = (ordered_shape_strides[i][0], remaining_buffer+shape_stride[1]) - else: - to_apply.append((MovementOps.SHRINK, (*((0, s[0]) for s in ordered_shape_strides[:i]), (0, shape_stride[0]*shape_stride[1])))) - to_apply.append((MovementOps.RESHAPE, (*[s[0] for s in ordered_shape_strides[:i+1]], shape_stride[1]))) - to_apply.extend([(MovementOps.SHRINK, (*[(0, s[0]) for s in ordered_shape_strides], (0,1))), (MovementOps.RESHAPE, tuple(s[0] for s in ordered_shape_strides))]) - if order != list(range(len(order))): to_apply.append((MovementOps.PERMUTE, tuple(order.index(i) for i in range(len(strides))))) - to_apply.append((MovementOps.RESHAPE, tuple(s if st else 1 for s,st in zip(real_shape, v.strides)))) - if any(i<0 for i in v.strides): to_apply.append((MovementOps.STRIDE, tuple(-1 if st<0 else 1 for st in v.strides))) - # then, we apply pre expand pads - if v.mask is not None: - pre_expand_pads = tuple((x,s-y) if st != 0 else (0,0) for (x,y),s,st in zip(v.mask, v.shape, v.strides)) - post_expand_pads = tuple((x,s-y) if st == 0 else (0,0) for (x,y),s,st in zip(v.mask, v.shape, v.strides)) - if any(x != (0,0) for x in pre_expand_pads): - to_apply.append((MovementOps.PAD, pre_expand_pads)) - real_shape = tuple(x+s[0]+s[1] for x,s in zip(real_shape, pre_expand_pads)) - # then, we do any expands - if any(s != 1 and st == 0 for s,st in zip(real_shape, v.strides)): to_apply.append((MovementOps.EXPAND, real_shape)) - # lastly, we apply post expand pads - if v.mask is not None and any(x != (0,0) for x in post_expand_pads): to_apply.append((MovementOps.PAD, post_expand_pads)) - - scratch_st = make_scratch_st(st) - ret = [] - seen = {} # {shapetracker: list of mops to generate that shapetracker} - for mop_arg in to_apply: - scratch_st = apply_mop(scratch_st, mop_arg) - if scratch_st in seen: - ret = seen[scratch_st][:] - else: - if len(ret) and ret[-1][0] == MovementOps.RESHAPE and mop_arg[0] == MovementOps.RESHAPE: - ret[-1] = mop_arg - else: - if mop_arg == (MovementOps.RESHAPE, -1): mop_arg = (MovementOps.RESHAPE, (prod(st.shape),)) - ret.append(mop_arg) - seen[scratch_st] = ret[:] - return ret - -def get_real_view(shape, strides, offset, mask): - real_shape = tuple(y-x for x,y in mask) if mask else shape - offset = offset + sum(st * (s-1) for s,st in zip(real_shape, strides) if st<0) - real_offset = offset + (sum(x*st for (x,_),st in zip(mask, strides)) if mask else 0) - real_real_shape = [s for s,st in zip(real_shape, strides) if st] - strides = [abs(st) if isinstance(st,int) else st for st in strides if st] - return real_real_shape, strides, real_offset - -def get_buffer_size(shape, strides, offset, mask): - real_real_shape, strides, real_offset = get_real_view(shape, strides, offset, mask) - return real_offset + sum((s-1)*st for s, st in zip(real_real_shape,strides)) + 1 - -def st_equivalent(st1: ShapeTracker, st2: ShapeTracker): - if (idxs1:=st1.expr_idxs()) == (idxs2:=st2.expr_idxs()): return True - idx1, valid1 = idxs1 - idx2, valid2 = idxs2 - # always invalid - if valid1 == 0 and valid2 == 0: return True - - var1 = idx1.vars() | valid1.vars() - var2 = idx2.vars() | valid2.vars() - # Maybe there are cases that vars are different yet the sts are the same? - if var1 != var2: return False - - # brute force over the vars range - vs = list(var1) - for i, ranges in enumerate(itertools.product(*[range(v.min, v.max+1) for v in vs])): - if i > 1000: - print("WARNING: did not search all possible combinations") - break - var_vals = {k:v for k,v in zip(vs, ranges)} - r1 = sym_infer(idx1, var_vals) if sym_infer(valid1, var_vals) else 0 - r2 = sym_infer(idx2, var_vals) if sym_infer(valid2, var_vals) else 0 - if r1 != r2: return False - - return True - -c: DefaultDict[int,int] = defaultdict(int) -def test_rebuild(st: ShapeTracker): - rebuilt_st = make_scratch_st(st) - mops = to_movement_ops(st) - c[len(mops)] += 1 - for mop_arg in mops: rebuilt_st = apply_mop(rebuilt_st, mop_arg) - rebuilt_st = rebuilt_st.simplify() - # why is the "all(x == 0 for x in rebuilt_st.views[-1].strides)" hack needed? - assert st_equivalent(st, rebuilt_st) or all(x == 0 for x in rebuilt_st.views[-1].strides), f"mismatch {st} {rebuilt_st}" - last_v1 = st.views[-1] - last_v2 = rebuilt_st.views[-1] - assert last_v1.shape == last_v2.shape, f"{last_v1.shape} != {last_v2.shape}" - -def test_rebuild_bufferop_st(ast:UOp): - if ast.op is Ops.SHAPETRACKER: - test_rebuild(ast.arg) - for src in ast.src: test_rebuild_bufferop_st(src) - -if __name__ == "__main__": - ast_strs = load_worlds(False, False, True)[:2000] - for ast_str in tqdm(ast_strs): - test_rebuild_bufferop_st(ast_str_to_ast(ast_str)) - - print(f"avg length of mop = {sum(k*v for k,v in c.items()) / sum(c.values()):.2f}") diff --git a/tinygrad/extra/torch_backend/.gitignore b/tinygrad/extra/torch_backend/.gitignore deleted file mode 100644 index 1269488f..00000000 --- a/tinygrad/extra/torch_backend/.gitignore +++ /dev/null @@ -1 +0,0 @@ -data diff --git a/tinygrad/extra/torch_backend/backend.py b/tinygrad/extra/torch_backend/backend.py deleted file mode 100644 index 17c8083f..00000000 --- a/tinygrad/extra/torch_backend/backend.py +++ /dev/null @@ -1,643 +0,0 @@ -# ruff: noqa: E501, A001, A002, A006 -# A001 Variable `input` is shadowing a Python builtin -# A002 Function argument `input` is shadowing a Python builtin -# A006 Lambda argument `input` is shadowing a Python builtin -from tinygrad import Tensor, dtypes, Device -from tinygrad.uop.ops import Ops -from tinygrad.helpers import getenv, prod -import torch.lib -TORCH_DEBUG = getenv("TORCH_DEBUG") -import torch, pathlib, math, operator, functools, inspect -torch.autograd.grad_mode.set_multithreading_enabled(False) -from tinygrad.dtype import _from_torch_dtype, _to_torch_dtype - -# https://pytorch.org/docs/stable/torch.compiler_ir.html - -def _from_torch_device(device: torch.device): return f"{Device.DEFAULT}:{device.index or 0}" -def _to_torch_device(device: str): return torch.device("tiny", int(device.partition(":")[2] or 0)) - -import torch.utils.cpp_extension -mod = torch.utils.cpp_extension.load(name="custom_device_extension", sources=[str(pathlib.Path(__file__).parent / "wrapped_tensor.cpp")]) -def wrap(x:Tensor) -> torch.Tensor: return mod.wrap(x, _to_torch_dtype(x.dtype), _to_torch_device(x.device).index) -def unwrap(x:torch.Tensor) -> Tensor: - assert isinstance(x, torch.Tensor), f"x isn't {type(x)}" - return mod.unwrap(x) -class TinyBackend: - def is_initialized(self): return True - def is_available(self): return True - def current_device(self): return 0 - def _is_in_bad_fork(self): return False - def manual_seed_all(self, seed: int): Tensor.manual_seed(seed) - def device_count(self): return getenv("GPUS", 1) # TODO: device count in tiny? -torch.utils.rename_privateuse1_backend("tiny") -torch._register_device_module("tiny", TinyBackend()) -torch.utils.generate_methods_for_privateuse1_backend() -aten = torch.ops.aten - -# track view relationships for in place operations -def is_view(tensor: Tensor): return hasattr(tensor, "_view_base") -def canonical_base(view: Tensor): return getattr(view, "_view_base", view) -def derived_views(base: Tensor): return [t for tref in getattr(base, "_views", set()) if (t:=tref()) is not None] -def wrap_view_op(fn): - def _wrap(*args,**kwargs): - args = [unwrap(x) if isinstance(x, torch.Tensor) else x for x in args] - kwargs = {k:unwrap(v) if isinstance(v, torch.Tensor) else v for k,v in kwargs.items()} - ret = fn(*args,**kwargs) - ret._view_base = base = canonical_base(args[0]) - if not hasattr(base, "_views"): base._views = set() - base._views.add(weakref.ref(ret)) - return wrap(ret) - return _wrap - -view_ops = { - "aten.view": Tensor.reshape, - "aten._unsafe_view": Tensor.reshape, # when are views unsafe, and do we care? - "aten.view.dtype": lambda self,dtype: self.bitcast(_from_torch_dtype(dtype)), - "aten.expand": Tensor.expand, - "aten.t": Tensor.transpose, - "aten.transpose.int": Tensor.transpose, - "aten.squeeze.dim": Tensor.squeeze, - "aten.unsqueeze": Tensor.unsqueeze, - "aten.detach": Tensor.detach, -} - -for k,v in view_ops.items(): torch.library.impl(k.replace("aten.", "aten::"), "privateuseone")(wrap_view_op(v)) - -# in place operations with views -def realize_with_views(self: Tensor, views: Tensor): - if not self.uop.st.contiguous: self.replace(self.contiguous()) - self.replace(self.clone().realize()) - for v in views: - if v.uop.base.op is Ops.BUFFER_VIEW: continue # skip subbuffer, we just use the real buffer view - ret = self - st = ShapeTracker(self.uop.st.views + v.uop.st.views) # TODO: is this right? - for mo in cached_to_movement_ops(self.shape, st): ret = apply_mop(ret, mo) - v.replace(ret) -def maybe_realize_storage(self: Tensor) -> bool: - if realize:=is_view(self): realize_with_views((base:=canonical_base(self)), derived_views(base)) - return realize -def inplace_fn(outvars: str|list[str]): - if type(outvars) is str: outvars = [outvars] - def decorator(fn): - sig = inspect.signature(fn) - def wrapper(*args, **kwargs): - bound = sig.bind(*args, **kwargs) - outs = [kwargs.get(v, bound.arguments.get(v)) for v in outvars] - outs = [unwrap(o) if isinstance(o, torch.Tensor) else o for o in outs] - realize = any(maybe_realize_storage(o) for o in outs) - ret = fn(*args, **kwargs) - if realize: Tensor.realize(*(o for o in outs)) - return ret - return wrapper - return decorator - -# *** bad functions on CPU *** - -@torch.library.impl("aten::_index_put_impl_", "privateuseone") -@inplace_fn("self") -def _index_put_impl_(self, indices, values, accumulate=False, unsafe=False): - # TODO: move to tinygrad - ret = aten._index_put_impl_(self.cpu(), [x.cpu() if isinstance(x, torch.Tensor) else None for x in indices], values.cpu(), accumulate, unsafe).to(self.device) - return wrap(unwrap(self).assign(unwrap(ret))) - -@torch.library.impl("aten::index_put", "privateuseone") -def index_put(self, indices, values, accumulate=False): - return aten.index_put(self.cpu(), [z.cpu() if isinstance(z, torch.Tensor) else None for z in indices], values.clone().cpu(), accumulate).tiny() - -@torch.library.impl("aten::isin.Tensor_Tensor_out", "privateuseone") -def isin_tensor_tensor_out(x, y, *, assume_unique=False, invert=False, out=None): return out.copy_(aten.isin(x.cpu(), y.cpu(), assume_unique=assume_unique, invert=invert).tiny()) - -@torch.library.impl("aten::randperm.generator_out", "privateuseone") -def randperm_generator(n, generator=None, out=None): - return out.copy_(wrap(Tensor.randperm(n, generator=generator, device=unwrap(out).device))) - -@torch.library.impl("aten::cummax", "privateuseone") -def cummax(self, dim): - # TODO: support cummax with indices to match torch - cummax, indices = aten.cummax(self.cpu(), dim) - return (cummax.tiny(), indices.tiny()) - -@torch.library.impl("aten::nonzero", "privateuseone") -# TODO: move to tinygrad -def nonzero(self): return aten.nonzero(self.cpu()).tiny() - -@torch.library.impl("aten::_linalg_eigh", "privateuseone") -# TODO: move to tinygrad -def _linalg_eigh(self, UPLO: str = 'U'): - w, v = torch.linalg.eigh(self.cpu(), UPLO=UPLO) - return w.tiny(), v.tiny() - -def upsample_backward(grad_out, output_size, input_size, *args, f=None): return f(grad_out.cpu(), output_size, input_size, *args).tiny() - -for i in [ - "upsample_linear1d_backward", "upsample_nearest1d_backward", "_upsample_nearest_exact1d_backward", - "upsample_nearest2d_backward", "_upsample_nearest_exact2d_backward", - "upsample_nearest3d_backward", "_upsample_nearest_exact3d_backward", - "upsample_trilinear3d_backward", "upsample_bilinear2d_backward" -]: - torch.library.impl(f"aten::{i}", "privateuseone")(functools.partial(upsample_backward, f=getattr(aten, i))) - -# *** end bad functions on CPU *** - -@torch.library.impl("aten::index.Tensor", "privateuseone") -def index_tensor(x, y): - return wrap(unwrap(x)[[unwrap(_y.to(x.device)) if _y is not None else slice(None) for _y in y]]) - -@torch.library.impl("aten::zero_", "privateuseone") -@inplace_fn("x") -def zero_(x): - if TORCH_DEBUG: print(f"zero_ {x.shape}") - tt = unwrap(x) - # NOTE: unconditional contiguous covers if x is contiguous (match it) or if x is view (realize for inplace) - # TODO: consolidate - tt.assign(tt.zeros_like().contiguous()) - -@torch.library.impl("aten::fill_.Scalar", "privateuseone") -@inplace_fn("x") -def fill_scalar(x, y): - if TORCH_DEBUG: print(f"fill_.Scalar {x.shape} {y}") - tt = unwrap(x) - tt.assign(tt.full_like(y).contiguous()) - -@torch.library.impl("aten::_local_scalar_dense", "privateuseone") -def _local_scalar_dense(tensor): return unwrap(tensor).item() - -@functools.cache -def cached_to_movement_ops(shape, st) -> list: - mops = to_movement_ops(st) - if mops[0] == (MovementOps.RESHAPE, shape): mops = mops[1:] - return mops - -from tinygrad.shape.shapetracker import ShapeTracker, View -from extra.to_movement_ops import to_movement_ops, apply_mop, MovementOps -@torch.library.impl("aten::as_strided", "privateuseone") -def as_strided(tensor:torch.Tensor, size, stride, storage_offset=None): - storage_offset = storage_offset or tensor.storage_offset() - @wrap_view_op - def _as_strided(tensor:Tensor, size, stride, storage_offset=None): - # multiple as_strided do not compound - base = canonical_base(tensor) - # TODO: this is heavyweight - st = ShapeTracker(base.uop.st.views + (View.create(tuple(size), tuple(stride), storage_offset),)) - ret = base - if TORCH_DEBUG >= 1: print("**** as_strided", tensor.shape, size, stride, st) - if prod(size) == 1: return ret.flatten()[storage_offset].reshape(size) - for mo in cached_to_movement_ops(tuple(base.shape), st): ret = apply_mop(ret, mo) - return ret - return _as_strided(tensor, size, stride, storage_offset) - -@torch.library.impl("aten::empty_strided", "privateuseone") -def empty_strided(size, stride, dtype, layout=None, device=None, pin_memory=False): - if TORCH_DEBUG: print(f"empty_strided {size=} {stride=} {dtype=} {layout=} {device=} {pin_memory=}") - ret = Tensor.empty(*size, dtype=_from_torch_dtype(dtype), device=_from_torch_device(device)).contiguous() - # TODO: should return with requested strides - return wrap(ret) - -@torch.library.impl("aten::empty.memory_format", "privateuseone") -def empty_memory_format(size, dtype=None, layout=None, device=None, pin_memory=False, memory_format=None): - if TORCH_DEBUG: print(f"empty.memory_format {size=} {dtype=} {layout=} {device=} {pin_memory=} {memory_format=}") - ret = Tensor.empty(*size, dtype=_from_torch_dtype(dtype or torch.get_default_dtype()), device=_from_torch_device(device)).contiguous() - return wrap(ret) - -@torch.library.impl("aten::max_pool2d_with_indices", "privateuseone") -def max_pool2d_with_indices(self:torch.Tensor, kernel_size:tuple[int, ...], stride=None, padding=0, dilation=1, ceil_mode=False): - # TODO: supprt stride [] in tinygrad? - if stride is not None and len(stride) == 0: stride = None - ret, idx = unwrap(self).max_pool2d(kernel_size, stride, dilation, padding, ceil_mode, return_indices=True) - return (wrap(ret), wrap(idx.cast(dtypes.int64))) - -@torch.library.impl("aten::max_pool2d_with_indices_backward", "privateuseone") -def max_pool2d_with_indices_backward(grad_out:torch.Tensor, self:torch.Tensor, kernel_size:tuple[int, ...], stride=None, padding=0, dilation=1, ceil_mode=False, indices=None): - return wrap(Tensor.max_unpool2d(unwrap(grad_out), unwrap(indices), output_size=unwrap(self).shape)) - -@torch.library.impl("aten::max_unpool2d", "privateuseone") -def max_unpool2d(self:torch.Tensor, indices:torch.Tensor, output_size): - return wrap(unwrap(self).max_unpool2d(unwrap(indices), output_size=output_size)) - -@torch.library.impl("aten::arange", "privateuseone") -def arange(end, dtype=None, device=None, pin_memory=None): - return wrap(Tensor.arange(0, end, dtype=_from_torch_dtype(dtype or torch.get_default_dtype()))) - -@torch.library.impl("aten::arange.start", "privateuseone") -def arange_start(start, end, dtype=None, device=None, pin_memory=None): - return wrap(Tensor.arange(start, end, dtype=_from_torch_dtype(dtype or torch.get_default_dtype()))) - -@torch.library.impl("aten::arange.start_step", "privateuseone") -def arange_start_step(start, end, step, dtype=None, device=None, pin_memory=None): - return wrap(Tensor.arange(start, end, step, dtype=_from_torch_dtype(dtype or torch.get_default_dtype()))) - -@torch.library.impl("aten::convolution_overrideable", "privateuseone") -def convolution_overrideable(input, weight, bias, stride, padding, dilation, transposed, output_padding, groups): - if TORCH_DEBUG >= 1: - print(f"convolution {input.shape=} {weight.shape=} {stride=} {padding=} {dilation=} {transposed=} {output_padding=} {groups=}") - input, weight, bias = unwrap(input), unwrap(weight), unwrap(bias) if bias is not None else None - # TODO: fix test_biased_conv2d fails without realize() - if not transposed: return wrap(input.conv2d(weight, bias, groups=groups, stride=stride, dilation=dilation, padding=padding).realize()) - return wrap(input.conv_transpose2d(weight, bias, groups=groups, stride=stride, dilation=dilation, padding=padding, output_padding=output_padding).realize()) - -@torch.library.impl("aten::convolution_backward_overrideable", "privateuseone") -def convolution_backward_overrideable(grad_out, input, weight, stride, padding, dilation, transposed, output_padding, groups, output_mask): - if TORCH_DEBUG >= 1: - print(f"convolution_backward {input.shape=} {weight.shape=} {stride=} {padding=} {dilation=} {transposed=} {output_padding=} {groups=}") - grad_out, input, weight, bias = unwrap(grad_out), unwrap(input), unwrap(weight), Tensor.zeros(weight.shape[0], device=_from_torch_device(weight.device)) - if not transposed: out = Tensor.conv2d(input, weight, bias, groups=groups, stride=stride, dilation=dilation, padding=padding) - else: - bias = Tensor.zeros(weight.shape[1] * groups) - out = Tensor.conv_transpose2d(input, weight, bias, groups=groups, stride=stride, dilation=dilation, padding=padding, output_padding=output_padding) - grads = out.gradient(*[t for t,m in zip([input, weight, bias], output_mask) if m], gradient=grad_out) - return tuple([wrap(grads.pop(0)) if m else None for m in output_mask]) - -@torch.library.impl("aten::slice.Tensor", "privateuseone") -@wrap_view_op -def slice_tensor(self, dim=0, start=None, end=None, step=1): - slices = [slice(None)] * self.ndim - slices[dim] = slice(start, end, step) - return self[slices] - -@torch.library.impl("aten::slice_backward", "privateuseone") -def slice_backward(grad_out, input_sizes, dim, start, end, step): - grad_input = Tensor.zeros(input_sizes).contiguous() - slices = [slice(None)] * len(input_sizes) - slices[dim] = slice(start, end, step) - grad_input[slices] = unwrap(grad_out) - return wrap(grad_input) - -@torch.library.impl("aten::select_backward", "privateuseone") -def select_backward(grad_out, input_sizes, dim, index): - grad_input = Tensor.zeros(input_sizes).contiguous() - slices = [slice(None)] * len(input_sizes) - slices[dim] = index - grad_input[slices] = unwrap(grad_out) - return wrap(grad_input) - -def avg_pool(self, kernel_size, stride=[], padding=0, ceil_mode=False, count_include_pad=True, divisor_override=None): - return wrap(unwrap(self).avg_pool2d(kernel_size, stride if stride != [] else None, padding=padding, ceil_mode=ceil_mode, count_include_pad=count_include_pad)) - -def avg_pool_backward(grad_out, self, kernel_size, stride=None, padding=0, ceil_mode=False, count_include_pad=True, divisor_override=None): - self, grad_out = unwrap(self), unwrap(grad_out) - out = Tensor.avg_pool2d(self, kernel_size, stride if stride != [] else None, dilation=1, padding=padding, ceil_mode=ceil_mode, count_include_pad=count_include_pad) - return wrap(out.gradient(self, gradient=grad_out)[0]) - -for dim in [2, 3]: - torch.library.impl(f"aten::avg_pool{dim}d", "privateuseone")(avg_pool) - torch.library.impl(f"aten::avg_pool{dim}d_backward", "privateuseone")(avg_pool_backward) - -def pad_forward(self, padding, mode=None): return wrap(Tensor.pad(unwrap(self), padding, mode=mode)) - -def pad_backward(grad_out, self, padding, mode): - self, grad_out = unwrap(self), unwrap(grad_out) - out = Tensor.pad(self, padding, mode=mode) - return wrap(out.gradient(self, gradient=grad_out)[0]) - -for dim in [1, 2, 3]: - for pad_type, mode in [("replication", "replicate"), ("reflection", "reflect")]: - torch.library.impl(f"aten::{pad_type}_pad{dim}d", "privateuseone")(functools.partial(pad_forward, mode=mode)) - torch.library.impl(f"aten::{pad_type}_pad{dim}d_backward", "privateuseone")(functools.partial(pad_backward, mode=mode)) - -def upsample(self, size, align_corners=False, mode=None): return wrap(Tensor.interpolate(unwrap(self), size, mode=mode, align_corners=align_corners)) -for i,pre in enumerate(["", "bi", "tri"]): - torch.library.impl(f"aten::upsample_{pre}linear{i+1}d", "privateuseone")(functools.partial(upsample, mode="linear")) - torch.library.impl(f"aten::upsample_nearest{i+1}d", "privateuseone")(functools.partial(upsample, mode="nearest")) - torch.library.impl(f"aten::_upsample_nearest_exact{i+1}d", "privateuseone")(functools.partial(upsample, mode="nearest-exact")) - -@torch.library.impl("aten::scatter_add.out", "privateuseone") -@inplace_fn("out") -def scatter_add(self, dim, index, src, out): - self, index, src, out = unwrap(self), unwrap(index), unwrap(src), unwrap(out) - if self.shape == (): return wrap(out.assign(src)) - return wrap(out.assign(Tensor.scatter_reduce(self, dim, index, src, reduce='sum'))) - -@torch.library.impl("aten::_copy_from", "privateuseone") -def _copy_from(src: torch.Tensor, dest, non_blocking=False): - realize = dest.is_tiny and maybe_realize_storage(unwrap(dest)) - cast_dtype = _from_torch_dtype(dest.dtype) - if src.is_tiny and dest.is_tiny: - to_device = _from_torch_device(dest.device) - src,dest = unwrap(src),unwrap(dest) - # TODO we need to properly match dest shape and strides, not blindly assign - if dest.uop.st.contiguous or dest.uop.is_realized: src = src.contiguous() # this only solves some cases - dest.assign(src.cast(cast_dtype).to(to_device)) - if realize: Tensor.realize(dest) - elif src.is_tiny and dest.is_cpu: - # TODO: is there a better way? - dest.resize_(src.numel()).resize_(src.shape) - dest.copy_(torch.from_numpy(unwrap(src).cast(cast_dtype).numpy())) - elif src.is_cpu and dest.is_tiny: - to_device = _from_torch_device(dest.device) - # TODO we need to properly match dest shape and strides, not blindly assign - unwrap(dest).assign(Tensor(src.numpy()).cast(cast_dtype).to(to_device)) - if realize: Tensor.realize(unwrap(dest)) - else: - raise NotImplementedError(f"can't copy from {src.device} -> {dest.device}") - -@torch.library.impl("aten::cat.out", "privateuseone") -@inplace_fn("out") -def cat_out(tensors, dim=0, out=None): - unwrap(out).assign(Tensor.cat(*[unwrap(x) for x in tensors], dim=dim)) - -@torch.library.impl("aten::topk.values", "privateuseone") -@inplace_fn(["values", "indices"]) -def topk_values(input, k, dim=None, largest=True, sorted=True, values=None, indices=None): - out_values, out_indices = unwrap(input).topk(k, dim if dim is not None else -1, largest, sorted) - unwrap(values).assign(out_values) - unwrap(indices).assign(out_indices.cast(dtypes.int64)) - return wrap(out_values), wrap(out_indices) - -@torch.library.impl("aten::sort.values_stable", "privateuseone") -@inplace_fn(["values", "indices"]) -def sort_values(input, dim=-1, descending=False, stable=True, values=None, indices=None): - out_values, out_indices = unwrap(input).sort(dim, descending) - unwrap(values).assign(out_values) - unwrap(indices).assign(out_indices.cast(dtypes.int64)) - return wrap(out_values), wrap(out_indices) - -# register some decompositions -from torch._decomp import get_decompositions -decomps = [ - aten.native_batch_norm, aten.native_batch_norm_backward, - aten.native_layer_norm_backward, - aten.addmm, - aten.addcmul, - aten.addcdiv, - aten._log_softmax_backward_data, - aten.threshold_backward, - aten.softplus_backward, - aten.elu, # elu has a scale + input_scale param - aten.elu_backward, - aten.softplus, - aten.threshold, - aten.nll_loss_forward, - aten.nll_loss_backward, - # AttributeError: 'int' object has no attribute '_broadcasted' - aten.sigmoid_backward, - aten.tanh_backward, - aten.sinc, - aten._prelu_kernel, - aten.softshrink, - aten.hardshrink, - aten.log_sigmoid_forward, - aten.isneginf, - aten.isposinf, - aten.nan_to_num, - aten.logit, - aten.rsub, - aten.index_select, - aten.native_dropout, aten.native_dropout_backward, - aten._softmax_backward_data, aten.embedding_dense_backward, - aten.linalg_vector_norm, - aten.binary_cross_entropy, aten.binary_cross_entropy_backward, - aten.upsample_nearest2d.out, - # activations - aten.hardswish, aten.hardswish_backward, - aten.hardtanh, aten.hardtanh_backward, - aten.gelu, aten.gelu_backward, - aten.logical_and, - aten.randint, - aten.eye, - aten.hardsigmoid_backward, - aten.leaky_relu_backward, - aten.nll_loss2d_forward, - aten.unfold_backward, - # NOTE: many of these don't work or cause infinite loops - #aten.var_mean, - #aten.var, - #aten.rsqrt, - #aten.max_pool2d_with_indices, - # NOTE: these are prims - #aten.digamma, - #aten.erfinv, - #aten.lgamma, - # this needs copy_strided - #aten.lerp, -] -for k,v in get_decompositions(decomps).items(): - key = str(k._schema).split("(")[0] - if TORCH_DEBUG >= 2: print("register decomp for", k) - torch.library.impl(key, "privateuseone")(v) - -# NOTE: we should only implement the "out" form, it should be 0 overhead -# TODO: due to issue with empty / is_realized, it is slow to use assign so we use replace -# the goal is to make as much as we can this -simple_tensor_methods = [ - # unary (ish) - "log", "log2", "sqrt", "rsqrt", "sign", "silu", "hardsigmoid", "exp", "exp2", "neg", "reciprocal", "bitwise_not", - "sigmoid", "clamp", "mish", "erf", "leaky_relu", - # trig - "acos", "acosh", "cos", "cosh", "asin", "asinh", "sin", "sinh", "atan", "atanh", "tan", "tanh", - # rounding - "ceil", "round", "floor", "trunc", - # binary - "mul", "div", "maximum", "minimum", "copysign", - # modify - "tril", "triu", - # reduce - "all", "any", "argmax", "argmin", "cumsum", "cumprod", - # complex - "avg_pool2d", "linspace"] - -tiny_backend_out = {**{f"aten.{x}.out":getattr(Tensor,x) for x in simple_tensor_methods}, **{ - "aten.add.out": lambda input,other,alpha=1: input+alpha*other, - "aten.sub.out": lambda input,other,alpha=1: input-alpha*other, # NOTE: this is also needed to handle reverse - "aten.div.out_mode": Tensor.div, - "aten.mul.out": operator.mul, - "aten.bmm.out": operator.matmul, - # NOTE: because these methods have a name with "Tensor" in them, they can't go in simple tensor methods - "aten.remainder.Tensor_out": Tensor.mod, - "aten.pow.Tensor_Tensor_out": Tensor.pow, - "aten.pow.Tensor_Scalar_out": Tensor.pow, - "aten.pow.Scalar_out": lambda input,exponent: input**exponent, - "aten.bitwise_and.Tensor_out": Tensor.bitwise_and, - "aten.bitwise_or.Tensor_out": Tensor.bitwise_or, - "aten.bitwise_xor.Tensor_out": Tensor.bitwise_xor, - "aten.eq.Tensor_out": Tensor.eq, "aten.eq.Scalar_out": Tensor.eq, - "aten.ne.Tensor_out": Tensor.ne, "aten.ne.Scalar_out": Tensor.ne, - "aten.ge.Tensor_out": Tensor.__ge__, "aten.ge.Scalar_out": Tensor.__ge__, - "aten.gt.Tensor_out": Tensor.__gt__, "aten.gt.Scalar_out": Tensor.__gt__, - "aten.lt.Tensor_out": Tensor.__lt__, "aten.lt.Scalar_out": Tensor.__lt__, - "aten.le.Tensor_out": Tensor.__le__, "aten.le.Scalar_out": Tensor.__le__, - "aten.clamp_max.Tensor_out": lambda input,max_: input.clamp(max_=max_), - "aten.clamp_min.Tensor_out": lambda input,min_: input.clamp(min_=min_), - "aten.fmod.Tensor_out": lambda input,other: input-input.div(other, rounding_mode="trunc")*other, - # TODO: this might result in overflow issues - "aten.round.decimals_out": lambda self,decimals: (self*10**decimals).round()/10**decimals, - # TODO: support this in tinygrad - "aten.bitwise_left_shift.Tensor_out": lambda x,y: x*(2**y), - "aten.bitwise_right_shift.Tensor_out": lambda x,y: x//(2**y), - # not in tinygrad. are there decomps for these? - "aten.log10.out": lambda self: self.log2() * (math.log(2) / math.log(10)), - "aten.log1p.out": lambda self: (self+1).log(), - "aten.expm1.out": lambda self: self.exp() - 1, - "aten.fmax.out": lambda input,other: Tensor.where(input.isnan() & ~other.isnan(), other, Tensor.where(~input.isnan() & other.isnan(), input, Tensor.maximum(input, other))), - "aten.fmin.out": lambda input,other: Tensor.where(input.isnan() & ~other.isnan(), other, Tensor.where(~input.isnan() & other.isnan(), input, Tensor.minimum(input, other))), - "aten.amax.out": lambda self,dim=None: self.max(axis=dim), - # TODO: this gets the shape wrong - #"aten.arange.start_out": Tensor.arange, - "aten.lerp.Scalar_out": Tensor.lerp, - "aten.scatter.value_out": Tensor.scatter, - "aten.where.self_out": Tensor.where, - "aten.prod.int_out": Tensor.prod, - "aten.scatter.src_out": Tensor.scatter, - # NOTE: axis=[] in torch means all, change tinygrad? - "aten.sum.IntList_out": lambda self,axis,keepdim=False,dtype=None: - self.sum(axis if axis is None or len(axis) else None, keepdim, - dtype = _from_torch_dtype(dtype) if dtype is not None else None), -}} - -# we add the "out" here -def wrap_out(f): - @inplace_fn("out") - def _wrap_out(*args, **kwargs): - out = kwargs.pop('out') - assigned = f(*args, **kwargs) - if getenv("ALLOW_DTYPE_MISMATCH", 1): assigned = assigned.cast(out.dtype) - assert out.shape == assigned.shape, f"shape mismatch: {assigned.shape} -> {out.shape}" - assert out.device == assigned.device, f"device mismatch: {assigned.device} -> {out.device}" - assert out.dtype == assigned.dtype, f"dtype mismatch: {assigned.dtype} -> {out.dtype}" - if out.uop.is_realized: assigned = assigned.contiguous() # TODO: how does this map to torch's semantics - return out.assign(assigned) - return _wrap_out - -tiny_backend = {**{k:wrap_out(v) for k,v in tiny_backend_out.items()}, **{ - "aten.remainder.Scalar_Tensor": lambda x,y: x%y, - "aten.floor_divide": lambda x,y: x//y, - "aten.floor_divide_.Tensor": inplace_fn("x")(lambda x,y: x.assign(x//y)), - # TODO: use tinygrad methods, but they require x to be unsigned - "aten.__lshift__.Scalar": lambda x,y: x*(2**y), - "aten.__ilshift__.Scalar": inplace_fn("x")(lambda x,y: x.assign(x*(2**y))), - "aten.__rshift__.Scalar": lambda x,y: x//(2**y), - "aten.__irshift__.Scalar": inplace_fn("x")(lambda x,y: x.assign(x//(2**y))), - # relu doesn't have an out form? - "aten.relu": Tensor.relu, - "aten.relu_": inplace_fn("x")(lambda x: x.assign(x.relu())), - "aten.mean": Tensor.mean, - "aten.mean.dim": Tensor.mean, - "aten.min": Tensor.min, - "aten.max": Tensor.max, - "aten.mm": Tensor.matmul, - "aten.mv": Tensor.matmul, - "aten.dot": Tensor.dot, - "aten.prod": Tensor.prod, - "aten.isnan": Tensor.isnan, - "aten.std.correction": Tensor.std, - "aten.std_mean.correction": Tensor.std_mean, - "aten.var.correction": Tensor.var, - "aten.var_mean.correction": Tensor.var_mean, - "aten.scatter.value": Tensor.scatter, - "aten.scatter.value_reduce": Tensor.scatter, - "aten.gather": lambda self, dim, index: self.gather(dim, index.cast(dtypes.int)), - "aten.where.self": Tensor.where, # NOTE: this is needed as well as the out type - "aten.repeat": lambda x,*repeats: Tensor.repeat(x,*repeats).contiguous(), # not a view - "aten._softmax": lambda self,dim,half_to_float: self.softmax(dim), - "aten._log_softmax": lambda self,dim,half_to_float: self.log_softmax(dim), - "aten.random_": inplace_fn("self")(lambda self: - self.assign(Tensor.randint(*self.shape, low=dtypes.min(self.dtype), high=dtypes.max(self.dtype), device=self.device, dtype=self.dtype))), - "aten.random_.from": inplace_fn("self")(lambda self, from_, to: - self.assign(Tensor.randint(*self.shape, low=from_, high=to, device=self.device, dtype=self.dtype))), - "aten.uniform_": inplace_fn("self")(lambda self, low=0, high=1: self.assign(Tensor.uniform(*self.shape, low=low, high=high, dtype=self.dtype))), - "aten.normal_": inplace_fn("self")(lambda self, mean=0, std=1: self.assign(Tensor.normal(*self.shape, mean=mean, std=std, dtype=self.dtype))), - # these don't work in out form, they have size 0 - "aten.abs": Tensor.abs, - "aten.logical_not": Tensor.logical_not, - "aten.logical_or_": inplace_fn("x")(lambda x, y: x.assign(x | y)), - "aten.multinomial": Tensor.multinomial, - "aten.masked_fill_.Scalar": inplace_fn("self")(lambda self, mask, value: self.assign(self.masked_fill(mask, value))), - "aten.masked_fill_.Tensor": inplace_fn("self")(lambda self, mask, value: self.assign(self.masked_fill(mask, value))), - "aten.masked_fill.Scalar": Tensor.masked_fill, - "aten.masked_fill.Tensor": Tensor.masked_fill, - "aten.masked_select": Tensor.masked_select, - "aten.all": Tensor.all, - "aten.sgn": Tensor.sign, - "aten.acos": Tensor.acos, - "aten.any": Tensor.any, - "aten.bitwise_not": Tensor.bitwise_not, - "aten.argmax": Tensor.argmax, - "aten.argmin": Tensor.argmin, - "aten.asinh": Tensor.asinh, - "aten.mul": Tensor.mul, - "aten.atanh": Tensor.atanh, - "aten.fill_.Tensor": Tensor.full, # TODO: looks wrong - "aten.flip": Tensor.flip, - "aten.scatter_reduce.two": Tensor.scatter_reduce, - "aten.squeeze_.dim": lambda self, dim: self.replace(self.squeeze(dim), allow_shape_mismatch=True), # TODO: inplace view op, here? - "aten.add.Tensor": lambda input,other,alpha=1: input+alpha*other, - "aten.linspace": lambda start, stop, steps, dtype=None, **kwargs: - Tensor.linspace(start, stop, steps, **({"dtype": _from_torch_dtype(dtype)} if dtype is not None else {})), - "aten.topk": Tensor.topk, - "aten.constant_pad_nd": lambda self, padding, value=0.0: self.pad(padding, mode="constant", value=value).contiguous(), - "aten.cumsum": lambda self, dim: self.cumsum(dim).contiguous(), # TODO: fix test_simple_cumsum, fails without contiguous for shapes >512 - "aten.logsumexp": lambda self, axis, keepdim=False: self.logsumexp(axis[0], keepdim=keepdim), - "aten.roll": Tensor.roll, - "aten.logcumsumexp": Tensor.logcumsumexp, - "aten.lerp.Tensor": Tensor.lerp, - "aten.ones_like": lambda self, dtype=None, device=None, **kwargs: - self.ones_like(**{k: v for k, v in {"dtype": _from_torch_dtype(dtype) if dtype else None, - "device": _from_torch_device(device) if device else None}.items() if v is not None}), - "aten.max.dim": lambda self, dim, keepdim=False: (self.max(dim, keepdim), self.argmax(dim, keepdim).cast(dtype=dtypes.int64)), - "aten.unfold": Tensor.unfold, -}} - -def wrap_fxn(k,f): - def nf(*args, **kwargs): - if TORCH_DEBUG: - print(k, len(args), [x.shape if isinstance(x, torch.Tensor) else x for x in args], - {k:v.shape if isinstance(v, torch.Tensor) else v for k,v in kwargs.items()}) - args = [unwrap(x) if isinstance(x, torch.Tensor) else x for x in args] - kwargs = {k:unwrap(v) if isinstance(v, torch.Tensor) else v for k,v in kwargs.items()} - out = f(*args, **kwargs) - if isinstance(out, Tensor): return wrap(out) - elif isinstance(out, tuple): return tuple(wrap(x) for x in out) - else: raise RuntimeError(f"unknown output type {type(out)}") - return nf - -for k,v in tiny_backend.items(): torch.library.impl(k.replace("aten.", "aten::"), "privateuseone")(wrap_fxn(k,v)) - -@torch.library.impl("aten::equal", "privateuseone") -def equal(x: torch.Tensor, y: torch.Tensor): return (x==y).all().item() - -if TORCH_DEBUG: - from torch.utils._python_dispatch import TorchDispatchMode - class DispatchLog(TorchDispatchMode): - def __torch_dispatch__(self, func, types, args=(), kwargs=None): - #print(f"Dispatch Log: {func}(*{args}, **{kwargs})") - print(f"Dispatch Log: {func}") - return func(*args, **(kwargs or {})) - (_dispatch_log:=DispatchLog()).__enter__() # NOTE: must be kept alive - -# NOTE: patch torch optimizer step to avoid continously growing the computation graph -import weakref -_torch_modules_with_buffers: weakref.WeakSet[torch.nn.Module] = weakref.WeakSet() -def register_torch_buffer(mod, _name, _buffer): _torch_modules_with_buffers.add(mod) -def get_real_tinygrad_buffers(): - res = set() - for mod in _torch_modules_with_buffers: - for _,b in mod.named_buffers(recurse=False): - if b is not None and b.is_tiny: - res.add(unwrap(b)) - return res -torch.nn.modules.module.register_module_buffer_registration_hook(register_torch_buffer) - -from torch.nn.modules import Module -def backward_hook(model:Module, _grad_input, _grad_out): - grads_to_realize = [unwrap(p.grad) for p in model.parameters() if p.grad is not None] - if len(grads_to_realize): Tensor.realize(*grads_to_realize) -def module_hook(module:Module, _name, _submodule): module.register_backward_hook(backward_hook) -torch.nn.modules.module.register_module_module_registration_hook(module_hook) - -def realize_optimizer_step(optimizer: torch.optim.Optimizer, *args, **kwargs): - tinygrad_tensors = [] - for param_group in optimizer.param_groups: - for param in param_group["params"]: - if param is None: continue - tinygrad_tensors.append(param.data) - for state_dict in optimizer.state.values(): - for _, value in state_dict.items(): - if torch.is_tensor(value): tinygrad_tensors.append(value) - real_tinygrad_tensors = [unwrap(x) for x in tinygrad_tensors if x.is_tiny] - real_tinygrad_tensors += get_real_tinygrad_buffers() - if len(real_tinygrad_tensors): Tensor.realize(*real_tinygrad_tensors) - -_optimizer_init = torch.optim.Optimizer.__init__ -def _optimizer_patched_init(self, *args, **kwargs): - _optimizer_init(self, *args, **kwargs) - self.register_step_post_hook(realize_optimizer_step) -torch.optim.Optimizer.__init__ = _optimizer_patched_init diff --git a/tinygrad/extra/torch_backend/backend2.py b/tinygrad/extra/torch_backend/backend2.py deleted file mode 100644 index 9ce3bb23..00000000 --- a/tinygrad/extra/torch_backend/backend2.py +++ /dev/null @@ -1,47 +0,0 @@ -# NOTE: this is probably the wrong backend to work on, you want backend.py -# discussion about this in #pytorch-backend on our Discord -# this is using high level debug features from torch and we should integrate deeper - -from tinygrad import Tensor -import torch, contextlib -from torch.utils._python_dispatch import TorchDispatchMode -from tinygrad.dtype import _from_torch_dtype - -def empty_memory_format(size, dtype=None, layout=None, device=None, pin_memory=False, memory_format=None): - return TTensor(Tensor.empty(*size, dtype=_from_torch_dtype(dtype))) - -# NOTE: if we have a way to change wrap/unwrap, these can be the same methods from backend.py -tiny_backend = { - "aten.empty.memory_format": empty_memory_format, - "aten.view.default": lambda x,sz: TTensor(x.tiny.reshape(sz)), - "aten.abs.default": lambda x: TTensor(x.tiny.abs()), - "aten.eq.Tensor": lambda x,y: TTensor(x.tiny == y.tiny), - "aten.bitwise_and.Tensor": lambda x,y: TTensor(x.tiny & y.tiny), - "aten.ne.Scalar": lambda x,y: TTensor(x.tiny != y), - "aten.mul.Tensor": lambda x,y: TTensor(x.tiny * y.tiny), - "aten.masked_select.default": lambda x,y: TTensor(Tensor(x.tiny.numpy()[y.tiny.numpy()])), -} - -class TTensor(torch.Tensor): - tiny: Tensor - context = contextlib.nullcontext - - @staticmethod - def __new__(cls, tiny, *args, **kwargs): - out = torch.Tensor._make_wrapper_subclass(cls, tiny.shape) - torch._C._set_throw_on_mutable_data_ptr(out) - out.tiny = tiny - return out - def __repr__(self): return super().__repr__(tensor_contents=f"{self.tiny}") - def __torch_dispatch__(cls, func, types, args, kwargs=None): - print(f"Dispatch Log: {func}(*{[type(x) for x in args]}, **{kwargs.keys()})") - #print(f"Dispatch Log: {func}(*{args}, **{kwargs})") - new_func = tiny_backend.get(str(func), None) - if new_func is None: raise NotImplementedError(f"add support for {func}") - return new_func(*args, **(kwargs or {})) - -class Dispatcher(TorchDispatchMode): __torch_dispatch__ = TTensor.__torch_dispatch__ -Dispatcher().__enter__() - -if __name__ == "__main__": - a = torch.empty((4,), dtype=torch.int) diff --git a/tinygrad/extra/torch_backend/example.py b/tinygrad/extra/torch_backend/example.py deleted file mode 100644 index cc7ab159..00000000 --- a/tinygrad/extra/torch_backend/example.py +++ /dev/null @@ -1,21 +0,0 @@ -from PIL import Image -from tinygrad.helpers import getenv -import torch, torchvision, pathlib -import torchvision.transforms as transforms -import extra.torch_backend.backend -device = "tiny" -torch.set_default_device(device) - -if __name__ == "__main__": - img = Image.open(pathlib.Path(__file__).parent.parent.parent / "test/models/efficientnet/Chicken.jpg").convert('RGB') - transform = transforms.Compose([ - transforms.Resize(256), transforms.CenterCrop(224), transforms.ToTensor(), - transforms.Normalize(mean=[0.485, 0.456, 0.406], std=[0.229, 0.224, 0.225]) - ]) - img = transform(img).unsqueeze(0).to(device) - - model = torchvision.models.resnet18(weights=torchvision.models.ResNet18_Weights.DEFAULT) - if getenv("EVAL", 1): model.eval() - out = model(img).detach().cpu().numpy() - print("output:", out.shape, out.argmax()) - assert out.argmax() == 7 # cock diff --git a/tinygrad/extra/torch_backend/test.py b/tinygrad/extra/torch_backend/test.py deleted file mode 100644 index 5d84226b..00000000 --- a/tinygrad/extra/torch_backend/test.py +++ /dev/null @@ -1,210 +0,0 @@ -# simple tests -import unittest -import torch -import numpy as np -from tinygrad.helpers import getenv, Context, GlobalCounters -if getenv("TINY_BACKEND2"): - import extra.torch_backend.backend2 - device = "cpu" -else: - import extra.torch_backend.backend - device = "tiny" - -class TestTorchBackend(unittest.TestCase): - def test_randperm_generator_out(self): - n = 10 - out = torch.empty(n, dtype=torch.long, device=device) - res = torch.randperm(n, out=out).cpu().numpy() - np.testing.assert_equal(set(res), set(range(n))) - np.testing.assert_equal(out.cpu().numpy(), res) - - res2 = torch.randperm(n).cpu().numpy() - np.testing.assert_equal(set(res2), set(range(n))) - - def test_numpy_ones(self): - a = torch.ones(4, device=device) - np.testing.assert_equal(a.cpu().numpy(), [1,1,1,1]) - - def test_numpy_ones(self): - a = torch.ones(4, dtype=torch.int32, device=device) - assert a.dtype == torch.int32 - np.testing.assert_equal(a.cpu().numpy(), [1,1,1,1]) - - def test_plus(self): - a = torch.ones(4, device=device) - b = torch.ones(4, device=device) - c = a+b - np.testing.assert_equal(c.cpu().numpy(), [2,2,2,2]) - - def test_expand(self): - a = torch.Tensor([1,2,3,4]).to(device) - out = a.reshape(4,1).expand(4,4) - np.testing.assert_equal(out.cpu().numpy(), [[1,1,1,1],[2,2,2,2],[3,3,3,3],[4,4,4,4]]) - - def test_reshape(self): - a = torch.Tensor([[1,2],[3,4]]).to(device) - np.testing.assert_equal(a.reshape(4).cpu().numpy(), [1,2,3,4]) - np.testing.assert_equal(a.reshape(2,1,2).cpu().numpy(), [[[1,2]],[[3,4]]]) - np.testing.assert_equal(a.unsqueeze(1).cpu().numpy(), [[[1,2]],[[3,4]]]) - np.testing.assert_equal(a.unsqueeze(1).unsqueeze(1).cpu().numpy(), [[[[1,2]]],[[[3,4]]]]) - np.testing.assert_equal(a.unsqueeze(1).unsqueeze(1).squeeze().cpu().numpy(), [[1,2],[3,4]]) - - def test_permute(self): - a = torch.Tensor([[1,2],[3,4]]).to(device) - print(a.stride()) - null = a.permute(0,1) - perm = a.permute(1,0) - back = perm.permute(1,0) - np.testing.assert_equal(a.cpu().numpy(), [[1,2],[3,4]]) - np.testing.assert_equal(null.cpu().numpy(), [[1,2],[3,4]]) - np.testing.assert_equal(perm.cpu().numpy(), [[1,3],[2,4]]) - np.testing.assert_equal(back.cpu().numpy(), [[1,2],[3,4]]) - - def test_shrink(self): - a = torch.Tensor([1,2,3,4]).to(device) - np.testing.assert_equal(a[:3].cpu().numpy(), [1,2,3]) - np.testing.assert_equal(a[1:].cpu().numpy(), [2,3,4]) - - def test_as_strided(self): - a = torch.arange(70, device=device).reshape(1,1,10,7) - a = a.as_strided((1,1,10,5), (0,0,7,1), storage_offset=0) - a = a.as_strided((1,1,5,5), (50,50,7,1), storage_offset=21) - np.testing.assert_equal(a.cpu().numpy().sum(-1), [[[115,150,185,220,255]]]) - - def test_plus_inplace(self): - a = torch.ones(4, device=device) - b = torch.ones(4, device=device) - a += b - a += b - np.testing.assert_equal(a.cpu().numpy(), [3,3,3,3]) - - def test_exp2(self): - a = torch.ones(4, device=device) - b = a.exp2() - np.testing.assert_equal(b.cpu().numpy(), [2,2,2,2]) - - def test_amax(self): - x = torch.tensor([[[ 1.5, 2.3, 3.1, 4.7], - [ 5.2, 6.8, 7.4, 12.9], - [ 9.0, 12.3, 11.6, 10.1]], - [[13.2, 16.9, 15.5, 14.1], - [17.1, 24.9, 19.8, 20.2], - [21.0, 22.3, 23.6, 18.4]]], device=device) - - y1 = torch.amax(x) - expected = np.array([24.9], dtype=np.float32) - np.testing.assert_equal(y1.cpu().numpy(), expected) - - y2 = torch.amax(x, dim=(1,2)) - expected = np.array([12.9, 24.9], dtype=np.float32) - np.testing.assert_equal(y2.cpu().numpy(), expected) - - y3 = torch.amax(x, dim=2) - expected = np.array([[4.7, 12.9, 12.3], [16.9, 24.9, 23.6]], dtype=np.float32) - np.testing.assert_equal(y3.cpu().numpy(), expected) - - def test_isfinite(self): - a = torch.ones(4, device=device) - np.testing.assert_equal(torch.isfinite(a).cpu().numpy(), [True, True, True, True]) - - def test_eq(self): - a = torch.ones(4, device=device) - b = torch.ones(4, device=device) - c = a == b - print(c.cpu()) - - def test_maxpool2d_backward(self): - x = torch.arange(3*3, device=device).reshape(1, 1, 3, 3).requires_grad_(True) - torch.nn.functional.max_pool2d(x, kernel_size=2, stride=1).sum().backward() - np.testing.assert_equal(x.grad.squeeze().cpu().numpy(), [[0, 0, 0], [0, 1, 1], [0, 1, 1]]) - - def test_copy_cast(self): - x = torch.zeros(4, device=device, dtype=torch.int64) - y = torch.ones(4, device=device, dtype=torch.float32).to(dtype=torch.int64) - res1 = x ^ y # an operation that only works on int types - print(res1.cpu()) - y = y.cpu().float().to(device=device, dtype=torch.int64) - res2 = x ^ y - print(res2.cpu()) - - def test_topk(self): - # test topk return_types - a = torch.tensor([1, 3, 2, 4], device=device) - out = torch.topk(a, k=2) - np.testing.assert_equal(out.values.cpu().numpy(), [4, 3]) - np.testing.assert_equal(out.indices.cpu().numpy(), [3, 1]) - - def test_masked_select(self): - a = torch.tensor([4, 3, 2, 1], device=device) - mask = torch.tensor([True, False, True, False], device=device) - out = torch.masked_select(a, mask) - np.testing.assert_equal(out.cpu().numpy(), [4, 2]) - mask = torch.tensor(True, device=device) - out = torch.masked_select(a, mask) - np.testing.assert_equal(out.cpu().numpy(), [4, 3, 2, 1]) - - def test_isin_tensor_tensor_out(self): - a = torch.tensor([1, 2, 3], device=device) - b = torch.tensor([2, 4], device=device) - expected_base = torch.tensor([False, True, False], device=device) - for assume_unique in [False, True]: - for invert, expected in [(False, expected_base), (True, ~expected_base)]: - out = torch.empty_like(a, dtype=torch.bool) - res = torch.ops.aten.isin.Tensor_Tensor_out(a, b, invert=invert, assume_unique=assume_unique, out=out) - np.testing.assert_equal(out.cpu().numpy(), expected.cpu().numpy()) - - def test_uniform(self): - for torch_dtype in [torch.float32, torch.float16]: - a = torch.rand(10, 10, device=device, dtype=torch_dtype) - self.assertEqual(a.dtype, torch_dtype) - - def test_normal(self): - for torch_dtype in [torch.float32, torch.float16]: - a = torch.randn(10, 10, device=device, dtype=torch_dtype) - self.assertEqual(a.dtype, torch_dtype) - - def test_equal(self): - tensor_a = torch.tensor([[1, 2], [3, 4]], device=device) - tensor_b = torch.tensor([[1, 2], [3, 4]], device=device) - tensor_c = torch.tensor([[1, 2], [1, 2]], device=device) - assert torch.equal(tensor_a, tensor_b) - assert not torch.equal(tensor_a, tensor_c) - - def test_linalg_eigh(self): - a = torch.tensor([[1, 2], [2, 1]], dtype=torch.float32, device=device) - w, v = torch.linalg.eigh(a) - np.testing.assert_equal(w.cpu().numpy(), [-1, 3]) - recon = (v @ torch.diag(w) @ v.T).cpu().numpy() - np.testing.assert_allclose(recon, a.cpu().numpy(), atol=1e-6) - - def test_scalar_assign(self): - a = torch.tensor([1, 2, 3], device=device) - a[1] = 4 - np.testing.assert_equal(a.cpu().numpy(), [1, 4, 3]) - - @unittest.skip("meh") - def test_str(self): - a = torch.ones(4, device=device) - print(str(a)) - - @unittest.skip("failed") - def test_floor_div(self): - a = torch.tensor([10., 7., 5.], device=device) - b = torch.tensor([3., 2., 2.], device=device) - result = a // b - np.testing.assert_equal(result.cpu().numpy(), [3., 3., 2.]) - - def test_mnist_index(self): - with Context(FUSE_ARANGE=1, SPLIT_REDUCEOP=0): - GlobalCounters.reset() - from tinygrad.nn.datasets import mnist - X_train, Y_train, _, _ = mnist() - X_train = torch.tensor(X_train.float().numpy(), device=device) - Y_train = torch.tensor(Y_train.cast('int64').numpy(), device=device) - samples = torch.randint(0, X_train.shape[0], (32,)) - X,Y = X_train[samples], Y_train[samples] - X.cpu(), Y.cpu() - self.assertLessEqual(GlobalCounters.global_ops, 10_000_000) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/extra/torch_backend/test_compile.py b/tinygrad/extra/torch_backend/test_compile.py deleted file mode 100644 index 9becdbf3..00000000 --- a/tinygrad/extra/torch_backend/test_compile.py +++ /dev/null @@ -1,36 +0,0 @@ -# https://pytorch.org/tutorials/intermediate/torch_compile_tutorial.html -import torch -import torch._dynamo -from extra.torch_backend.backend import unwrap, wrap - -from torch._dynamo.backends.registry import register_backend -from torch._functorch.aot_autograd import aot_module_simplified - -from tinygrad import Tensor, TinyJit - -@register_backend -def tiny(gm:torch.fx.GraphModule, sample_inputs): - def my_compiler(gm:torch.fx.GraphModule, sample_inputs): - # TODO: the jit should capture the graph directly, not need three runs. this is a planned tinygrad refactor after becomes_map - @TinyJit - def tiny_function(*args:Tensor): - outs = gm(*[wrap(x) for x in args]) - for x in outs: unwrap(x).realize() - return outs - # TODO: this should be able to pass in .tiny() Tensors, not need to convert them. it tries to access Storage if you pass in. - def torch_function(*args:torch.Tensor): return tiny_function(*[unwrap(x.tiny()) for x in args]) - return torch_function - return aot_module_simplified(gm, sample_inputs, decompositions={}, fw_compiler=my_compiler) - -if __name__ == "__main__": - def foo(x, y): - a = torch.sin(x) - b = torch.cos(y) - return a + b - - print("calling compile") - opt_foo1 = torch.compile(foo, backend="tiny") - print("compiled") - for i in range(5): - out = opt_foo1(torch.randn(10, 10), torch.randn(10, 10)) - print(out.device) diff --git a/tinygrad/extra/torch_backend/test_inplace.py b/tinygrad/extra/torch_backend/test_inplace.py deleted file mode 100644 index e6f171f0..00000000 --- a/tinygrad/extra/torch_backend/test_inplace.py +++ /dev/null @@ -1,71 +0,0 @@ -import unittest -import torch -import tinygrad.frontend.torch -torch.set_default_device("tiny") -import numpy as np - -class TestTorchBackendInplace(unittest.TestCase): - def test_zero(self): - a = torch.ones(4) - a.zero_() - np.testing.assert_equal(a.cpu().numpy(), [0,0,0,0]) - - def test_view_zero(self): - a = torch.ones(4) - a.view((2, 2)).zero_() - np.testing.assert_equal(a.cpu().numpy(), [0,0,0,0]) - - def test_slice_zero(self): - a = torch.ones(4) - a[2:].zero_() - np.testing.assert_equal(a.cpu().numpy(), [1,1,0,0]) - - def test_slice_permute_zero(self): - a = torch.ones((3,2)) - a.permute(1,0)[1:].zero_() - np.testing.assert_equal(a.cpu().numpy(), [[1,0],[1,0],[1,0]]) - - def test_slice_fill(self): - a = torch.zeros(4) - a[2:].fill_(2) - np.testing.assert_equal(a.cpu().numpy(), [0,0,2,2]) - - def test_slice_mul(self): - a = torch.ones(4) - a[:2] *= 3 - a[2:] *= 2 - np.testing.assert_equal(a.cpu().numpy(), [3,3,2,2]) - - def test_stacked_mul(self): - a = torch.ones((3,3)) - b = a[1:,1:].permute(1,0) - c = b[1:,:] - b *= 2 - c *= 3 - np.testing.assert_equal(a.cpu().numpy(), [[1,1,1],[1,2,6],[1,2,6]]) - - def test_flatten_reshape_add(self): - a = torch.zeros((2,2,12,32)) - b = a.flatten() - c = b.reshape((48,32)) - a += 1 - b += 1 - c += 1 - np.testing.assert_equal(c.cpu().numpy(), torch.full((48,32),3).cpu().numpy()) - - def test_noncontig(self): - a = torch.empty_strided((4,4),(1,4), dtype=torch.int64) - # self.assertFalse(a.is_contiguous()) # TODO: we are contiguous when it's not required - a.zero_() - b = a.view((4,4)) - b[1:3,:] += 1 - np.testing.assert_equal(a.cpu().numpy(), [[0]*4,[1]*4,[1]*4,[0]*4]) - - def test_detach(self): - a = torch.zeros(4) - d = a.detach() - d += torch.arange(4) - np.testing.assert_array_equal(a.cpu(), torch.arange(4).cpu()) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/extra/torch_backend/test_multigpu.py b/tinygrad/extra/torch_backend/test_multigpu.py deleted file mode 100644 index 9a218981..00000000 --- a/tinygrad/extra/torch_backend/test_multigpu.py +++ /dev/null @@ -1,29 +0,0 @@ -import unittest -from tinygrad.helpers import getenv -import torch -import tinygrad.frontend.torch -torch.set_default_device("tiny") -import numpy as np - -@unittest.skipIf(getenv("GPUS",1)<=1, "only single GPU") -class TestTorchBackendMultiGPU(unittest.TestCase): - def test_transfer(self): - a = torch.Tensor([[1,2],[3,4]]).to("tiny:0") - b = torch.Tensor([[3,2],[1,0]]).to("tiny:1") - self.assertNotEqual(a.device, b.device) - np.testing.assert_array_equal(a.cpu(), a.to("tiny:1").cpu()) - np.testing.assert_array_equal(b.cpu(), b.to("tiny:1").cpu()) - - def test_basic_ops(self): - a = torch.Tensor([[1,2],[3,4]]).to("tiny:0") - b = torch.Tensor([[3,2],[1,0]]).to("tiny:1") - c1 = a + b.to("tiny:0") - c2 = b + a.to("tiny:1") - np.testing.assert_array_equal(c1.cpu(), torch.full((2,2),4).cpu()) - np.testing.assert_array_equal(c1.cpu(), c2.cpu()) - - # TODO: torch.distributed functions - -if __name__ == "__main__": - unittest.main() - diff --git a/tinygrad/extra/torch_backend/torch_tests.py b/tinygrad/extra/torch_backend/torch_tests.py deleted file mode 100644 index cd8505c0..00000000 --- a/tinygrad/extra/torch_backend/torch_tests.py +++ /dev/null @@ -1,43 +0,0 @@ -import sys -import unittest -import torch -import extra.torch_backend.backend - -from torch.testing._internal.common_utils import TestCase, is_privateuse1_backend_available -assert is_privateuse1_backend_available() and torch._C._get_privateuse1_backend_name() == "tiny" -from torch.testing._internal.common_device_type import ops, onlyOn, instantiate_device_type_tests -from torch.testing._internal.common_methods_invocations import unary_ufuncs, binary_ufuncs, reduction_ops, shape_funcs - -def to_cpu(arg): return arg.to(device="cpu") if isinstance(arg, torch.Tensor) else arg -def filter_funcs(ufuncs): return [x for x in ufuncs if not x.name.startswith("_refs") and not x.name.startswith("special")] - -class TestTinyBackend(TestCase): - def _test(self, device, dtype, op): - samples = op.sample_inputs(device, dtype) - for sample in samples: - tiny_results = op(sample.input, *sample.args, **sample.kwargs) - tiny_results = sample.output_process_fn_grad(tiny_results) - - cpu_sample = sample.transform(to_cpu) - cpu_results = op(cpu_sample.input, *cpu_sample.args, **cpu_sample.kwargs) - cpu_results = cpu_sample.output_process_fn_grad(cpu_results) - - self.assertEqual(tiny_results, cpu_results, atol=1e-3, rtol=1e-3) - - @ops(filter_funcs(unary_ufuncs), allowed_dtypes=[torch.float]) - def test_unary(self, device, dtype, op): self._test(device, dtype, op) - - @ops(filter_funcs(binary_ufuncs), allowed_dtypes=[torch.float]) - def test_binary(self, device, dtype, op): self._test(device, dtype, op) - - @ops(filter_funcs(reduction_ops), allowed_dtypes=[torch.float]) - def test_reduction(self, device, dtype, op): self._test(device, dtype, op) - - # none of these pass - #@ops(shape_funcs) - #def test_shape(self, device, dtype, op): self._test(device, dtype, op) - -instantiate_device_type_tests(TestTinyBackend, globals(), only_for=["tiny"]) - -if __name__ == "__main__": - unittest.main(verbosity=2) diff --git a/tinygrad/extra/torch_backend/wrapped_tensor.cpp b/tinygrad/extra/torch_backend/wrapped_tensor.cpp deleted file mode 100644 index 3e5f19fc..00000000 --- a/tinygrad/extra/torch_backend/wrapped_tensor.cpp +++ /dev/null @@ -1,144 +0,0 @@ -#include -#include -#include -#include -#include - -// register guard -namespace at { -namespace detail { -//C10_REGISTER_GUARD_IMPL(PrivateUse1, c10::impl::NoOpDeviceGuardImpl); -// NOTE: pytorch's no-op class throws error on backwards with events/streams -// TODO: why are there events in autograd? -struct CustomNoOpDeviceGuardImpl : public c10::impl::DeviceGuardImplInterface -{ - static const DeviceType D = DeviceType::PrivateUse1; - CustomNoOpDeviceGuardImpl() = default; - DeviceType type() const override { - return D; - } - Device exchangeDevice(Device) const override { - return Device(D, 0); // no-op - } - Device getDevice() const override { - return Device(D, 0); - } - void setDevice(Device) const override { - // no-op - } - void uncheckedSetDevice(Device) const noexcept override { - // no-op - } - Stream getStream(Device) const noexcept override { - // no-op - return Stream(Stream::DEFAULT, Device(D, 0)); - } - Stream getDefaultStream(Device) const override { - // no-op - return Stream(Stream::DEFAULT, Device(D, 0)); - } - Stream getStreamFromGlobalPool(Device, bool isHighPriority = false) - const override { - // no-op - (void)isHighPriority; - return Stream(Stream::DEFAULT, Device(D, 0)); - } - Stream getNewStream(Device, int priority = 0) const override { - // no-op - (void)priority; - return Stream(Stream::DEFAULT, Device(D, 0)); - } - // NB: These do NOT set the current device - Stream exchangeStream(Stream) const noexcept override { - // no-op - return Stream(Stream::DEFAULT, Device(D, 0)); - } - DeviceIndex deviceCount() const noexcept override { - return 1; - } - // Event-related functions - void record( - void** /*event*/, - const Stream& /*stream*/, - const DeviceIndex /*device_index*/, - const EventFlag /*flag*/) const override { - //TORCH_CHECK(false, D, " backend doesn't support events."); - } - void block(void* /*event*/, const Stream& /*stream*/) const override { - //TORCH_CHECK(false, D, " backend doesn't support events.") - } - bool queryEvent(void* /*event*/) const override { - //TORCH_CHECK(false, D, " backend doesn't support events.") - return true; - } - void destroyEvent(void* /*event*/, const DeviceIndex /*device_index*/) - const noexcept override {} - // Stream-related functions - bool queryStream(const Stream& /*stream*/) const override { - return true; - } - void synchronizeStream(const Stream& /*stream*/) const override { - // Don't wait for anything. - } -}; -C10_REGISTER_GUARD_IMPL(PrivateUse1, CustomNoOpDeviceGuardImpl); -} - -template -struct TinyOpaqueTensorImpl : public OpaqueTensorImpl { - TinyOpaqueTensorImpl( - at::DispatchKeySet key_set, - const caffe2::TypeMeta data_type, - c10::Device device, - OpaqueHandle opaque_handle, - c10::IntArrayRef sizes, - c10::IntArrayRef strides, - int64_t storage_offset) - : OpaqueTensorImpl(key_set, data_type, device, opaque_handle, sizes) { - this->sizes_and_strides_.set_strides(strides); - this->storage_offset_ = storage_offset; - } -}; -} - -struct OpenRegHooksInterface : public at::PrivateUse1HooksInterface { - // NOTE: no idea what this is - bool hasPrimaryContext(c10::DeviceIndex device_index) const override { return true; } -}; - -int register_hook() { - at::RegisterPrivateUse1HooksInterface(new OpenRegHooksInterface()); - return 0; -} -int temp_register_hook = register_hook(); - -at::Tensor wrap_tensor(py::object &py_obj, c10::ScalarType dtype, c10::DeviceIndex device_index) { - // TODO: we have to get the dtype and the shape from the tinygrad Tensor - std::vector sizes = py_obj.attr("shape").cast>(); - - py::list views = py_obj.attr("uop").attr("st").attr("views"); - std::vector strides = views[views.size() - 1].attr("strides").cast>(); - int64_t storage_offset = 0; - for (auto& v: views) { - storage_offset += v.attr("offset").cast(); // TODO: is this correct? - } - - return at::detail::make_tensor>>( - at::DispatchKeySet(at::DispatchKey::PrivateUse1), - c10::scalarTypeToTypeMeta(dtype), - at::Device(at::kPrivateUse1, device_index), - std::make_shared(py_obj.release().ptr(), getPyInterpreter()), - sizes, strides, storage_offset); -} - -py::object unwrap_tensor(const at::Tensor &tensor) { - auto* impl = tensor.unsafeGetTensorImpl(); - auto* opaque_impl = static_cast>*>(impl); - std::shared_ptr tiny = opaque_impl->opaque_handle(); - return py::reinterpret_borrow(tiny->ptr(getPyInterpreter())); -} - -PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) { - m.def("wrap", &wrap_tensor); - m.def("unwrap", &unwrap_tensor); -} diff --git a/tinygrad/extra/torch_hook/hook_cuda.py b/tinygrad/extra/torch_hook/hook_cuda.py deleted file mode 100644 index 2e5ad907..00000000 --- a/tinygrad/extra/torch_hook/hook_cuda.py +++ /dev/null @@ -1,214 +0,0 @@ -import ctypes, struct, platform, pathlib, os, binascii, itertools -from hexdump import hexdump -from tinygrad.helpers import to_mv, DEBUG, getenv, colored, time_to_str -from tinygrad.runtime.autogen import libc, cuda -from tinygrad.device import CPUProgram, Device -from tinygrad.runtime.support.elf import elf_loader -from tinygrad.runtime.ops_cuda import cu_time_execution - -print(f"hooking CUDA runtime, running with {Device.DEFAULT}") - -# TODO: regen and make cuda 12 default? -cuda.cuFuncGetParamInfo = cuda._libraries['libcuda.so'].cuFuncGetParamInfo -cuda.cuFuncGetParamInfo.restype = cuda.CUresult -cuda.cuFuncGetParamInfo.argtypes = [cuda.CUfunction, cuda.size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] - -ignore_dispatch = [False] # default valus is False -def push_ignore_dispatch(val): - global ignore_dispatch - ignore_dispatch.append(val) - -def pop_ignore_dispatch(): - global ignore_dispatch - ignore_dispatch.pop() - -hooked = {} -def _hook(fxn_address_value, tramp): - page_address = (fxn_address_value//0x1000)*0x1000 - ret = libc.mprotect(page_address, 0x2000, 7) - assert ret == 0 - libc.memcpy(fxn_address_value, tramp, len(tramp)) - ret = libc.mprotect(page_address, 0x2000, 5) - assert ret == 0 - CPUProgram.rt_lib["__clear_cache"](fxn_address_value, fxn_address_value + len(tramp)) - -def install_hook(c_function, python_function): - python_function_addr = ctypes.cast(ctypes.byref(python_function), ctypes.POINTER(ctypes.c_ulong)).contents.value - # AARCH64 trampoline to ioctl - if (processor:=platform.processor()) == "aarch64": - # 0x0000000000000000: 70 00 00 10 adr x16, #0xc - # 0x0000000000000004: 10 02 40 F9 ldr x16, [x16] - # 0x0000000000000008: 00 02 1F D6 br x16 - tramp = b"\x70\x00\x00\x10\x10\x02\x40\xf9\x00\x02\x1f\xd6" - tramp += struct.pack("Q", python_function_addr) - elif processor == "x86_64": - # 0x0000000000000000: 49 BB aa aa aa aa aa aa aa aa movabs r11,
- # 0x000000000000000a: 41 FF E3 jmp r11 - tramp = b"\x49\xBB" + struct.pack("Q", python_function_addr) + b"\x41\xFF\xE3" - else: - raise Exception(f"processor {processor} not supported") - tramp = ctypes.create_string_buffer(tramp) - - # get real function address - fxn_address = ctypes.cast(ctypes.byref(c_function), ctypes.POINTER(ctypes.c_ulong)) - fxn_address_value = fxn_address.contents.value - #print(f"** hooking function at 0x{fxn_address_value}") - - orig_save = (ctypes.c_char*len(tramp))() - libc.memcpy(orig_save, fxn_address_value, len(tramp)) - _hook(fxn_address_value, tramp) - - def original(*args): - _hook(fxn_address_value, orig_save) - ret = c_function(*args) - _hook(fxn_address_value, tramp) - return ret - return original - -allocated_memory_enum = 0 -allocated_memory = {} -function_names = {} -tiny_devs = {} - -seen_modules = set() - -global_events = [] -class HookEvent: pass -class HookMemAllocEvent(HookEvent): - def __init__(self, cuda_address, bytesize, enum): self.cuda_address, self.bytesize, self.enum = cuda_address, bytesize, enum - def __repr__(self): return f"tensor alloc: {self.enum}: {self.cuda_address:#x} - {self.bytesize:#x} bytes" -class HookConstParamEvent(HookEvent): - def __init__(self, value): self.value = value - def __repr__(self): return f"const({self.value:#x})" -class HookTensorParamEvent(HookEvent): - def __init__(self, cuda_address, offset, enum): self.cuda_address, self.offset, self.enum = cuda_address, offset, enum - def __repr__(self): return f"tensor{self.enum}({self.cuda_address:#x}, {self.offset=:#x})" -class HookKernelCallEvent(HookEvent): - def __init__(self, grid, block, tm, ptm, name, params): self.grid, self.block, self.tm, self.ptm, self.name, self.params = grid, block, tm, ptm, name, params - def __repr__(self): return f"kernel call <<{self.grid}>> <<{self.block}>> {self.ptm}\n | {self.params}\n | {self.name}" - -def collect_events(clear=False): - global global_events - x = global_events - if clear: global_events = [] - return x - -@ctypes.CFUNCTYPE(*([cuda.cuDeviceGet.restype] + cuda.cuDeviceGet.argtypes)) -def cuDeviceGet(device, ordinal): - tiny_devs[ordinal] = Device[f"{Device.DEFAULT}:{ordinal}"] - device.contents.value = ordinal - return cuda.CUDA_SUCCESS - -@ctypes.CFUNCTYPE(*([cuda.cuMemHostAlloc.restype] + cuda.cuMemHostAlloc.argtypes)) -def cuMemHostAlloc(pp, bytesize, flags): - print(f"cuMemHostAlloc {bytesize}") - return hooked["cuMemHostAlloc"](pp, bytesize, flags) - -@ctypes.CFUNCTYPE(*([cuda.cuModuleLoadData.restype] + cuda.cuModuleLoadData.argtypes)) -def cuModuleLoadData(module, image): - ret = hooked["cuModuleLoadData"](module, image) - module_address = ctypes.addressof(module.contents.contents) - seen_modules.add(module_address) - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuModuleGetFunction.restype] + cuda.cuModuleGetFunction.argtypes)) -def cuModuleGetFunction(hfunc, hmod, name): - ret = hooked["cuModuleGetFunction"](hfunc, hmod, name) - python_name = ctypes.string_at(name).decode() - - # pip install git+https://github.com/wbenny/pydemangler.git - import pydemangler - demangled_name = pydemangler.demangle(python_name) - if demangled_name is not None: python_name = demangled_name - - # print(f"called cuModuleGetFunction 0x{ctypes.addressof(hmod.contents):X} {python_name}") - function_names[ctypes.addressof(hfunc.contents.contents)] = python_name - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuMemAlloc_v2.restype] + cuda.cuMemAlloc_v2.argtypes)) -def cuMemAlloc_v2(dptr, bytesize): - global allocated_memory_enum, text_prefix - - ret = hooked["cuMemAlloc_v2"](dptr, bytesize) - cuda_address = dptr.contents.value - allocated_memory[cuda_address] = (bytesize, allocated_memory_enum) - - global_events.append(HookMemAllocEvent(cuda_address, bytesize, allocated_memory_enum)) - if DEBUG >= 3: print(global_events[-1]) - - allocated_memory_enum += 1 - return ret - -@ctypes.CFUNCTYPE(*([cuda.cuLaunchKernel.restype] + cuda.cuLaunchKernel.argtypes)) -def cuLaunchKernel(f, gridDimX, gridDimY, gridDimZ, blockDimX, blockDimY, blockDimZ, sharedMemBytes, hStream, kernelParams, extra): - global ignore_dispatch - - name = function_names[ctypes.addressof(f.contents)] - if ignore_dispatch[-1]: - if DEBUG >= 4: print(f"ignoring dispatch {name}") - return 0 - - tm = cu_time_execution(lambda: - hooked["cuLaunchKernel"](f, gridDimX, gridDimY, gridDimZ, blockDimX, blockDimY, blockDimZ, sharedMemBytes, hStream, kernelParams, extra), True) - - ptm = colored(time_to_str(tm, w=9), "yellow" if tm > 0.01 else "green") - - params = [] - while True: - ret = cuda.cuFuncGetParamInfo(f, len(params), ctypes.byref(paramOffset:=ctypes.c_size_t()), ctypes.byref(paramSize:=ctypes.c_size_t())) - if ret != 0: break - params.append((paramOffset.value, paramSize.value)) - - ev_params = [] - if extra: params_ptr = to_mv(extra, 5*8).cast("Q") - else: params_ptr = to_mv(kernelParams, len(params)*8).cast("Q") - - for i,(off,sz) in enumerate(params): - sz_to_let = {1: 'B', 2: 'H', 4: 'I', 8: 'Q'} - if sz >= 8: - for j in range(sz//8): - if extra: value = to_mv(params_ptr[1] + off, sz).cast("Q")[0] - else: value = to_mv(params_ptr[i] + j*8, 8).cast('Q')[0] - - has_in_allocated_mem, lcoff, alnum = False, 0, -1 - for taddr, (tsz, talnum) in allocated_memory.items(): - if taddr <= value < taddr + tsz: - has_in_allocated_mem = True - lcoff = value - taddr - alnum = talnum - break - - if has_in_allocated_mem: ev_params.append(HookTensorParamEvent(value, lcoff, alnum)) - else: ev_params.append(HookConstParamEvent(value)) - else: - if extra: value = to_mv(params_ptr[1] + off, sz).cast(sz_to_let[sz])[0] - else: value = to_mv(params_ptr[i], sz).cast(sz_to_let[sz])[0] - ev_params.append(HookConstParamEvent(value)) - - global_events.append(HookKernelCallEvent((gridDimX, gridDimY, gridDimZ), (blockDimX, blockDimY, blockDimZ), tm, ptm, name, ev_params)) - if DEBUG >= 3: print(global_events[-1]) - - return 0 - -def create_hook(func_name, restype, argtypes): - def hook_template(*args): - # print(func_name, flush=True) - return hooked[func_name](*args) - return ctypes.CFUNCTYPE(restype, *argtypes)(hook_template) - -def install_hooks(): - hooked['cuModuleGetFunction'] = install_hook(cuda.cuModuleGetFunction, cuModuleGetFunction) - hooked['cuLaunchKernel'] = install_hook(cuda.cuLaunchKernel, cuLaunchKernel) - - # memory stuff - hooked['cuMemAlloc_v2'] = install_hook(cuda.cuMemAlloc_v2, cuMemAlloc_v2) - hooked['cuMemHostAlloc'] = install_hook(cuda.cuMemHostAlloc, cuMemHostAlloc) - - # module loading + not used module loading - hooked['cuModuleLoadData'] = install_hook(cuda.cuModuleLoadData, cuModuleLoadData) - -NVPROFILER = os.environ.get("NV_COMPUTE_PROFILER_PERFWORKS_DIR", None) # realize and wait each aten call -if NVPROFILER is None: install_hooks() -else: - print("Detected NSIGHT Profiled, hooking not avail.") - cuda._libraries['libcuda.so'] = ctypes.CDLL(NVPROFILER + "/libcuda-injection.so") diff --git a/tinygrad/extra/torch_hook/hook_torch.py b/tinygrad/extra/torch_hook/hook_torch.py deleted file mode 100644 index 8f718076..00000000 --- a/tinygrad/extra/torch_hook/hook_torch.py +++ /dev/null @@ -1,150 +0,0 @@ -import ctypes, struct, platform, pathlib, os, binascii, itertools -from hexdump import hexdump -from tinygrad.device import Device -from tinygrad import Tensor -from tinygrad.dtype import _from_torch_dtype -from tinygrad.helpers import to_mv, DEBUG, getenv, colored, time_to_str - -import extra.torch_hook.hook_cuda as hook_cuda - -# settings to profile gemm in the __main__ example: TINY_MIRROR=1;CUDA=1;RUN_ONLY=9 -# nvprof sample command (this will sample all kernels): -# ncu --export ~/nvprof_data --force-overwrite --rule AchievedOccupancy --rule Compute --rule LaunchConfiguration --rule Memory --rule PMSamplingData --rule SOLBottleneck --rule TheoreticalOccupancy --rule WorkloadImbalance python3 extra/torch_hook/hook_torch.py -# or just run nsight compute from the host to the machine. - -TINY_MIRROR = getenv("TINY_MIRROR", 1) # should mirror aten ops to tiny backend -RUN_ONLY = getenv("RUN_ONLY", -1) # run only a specific aten call -REALIZE = getenv("REALIZE", 1) # realize and wait each aten call -WRAP_TINY = getenv("WRAP_TINY", TINY_MIRROR) # reuse cuda tensors -FULL_KERN_NAME = getenv("FULL_KERN_NAME", 0) # print full kernel name - -print("importing torch...") -import torch -print("importing torch done:", torch.__version__, torch.__file__) - -if TINY_MIRROR: - print("importing tiny torch") - import extra.torch_backend.backend as tiny_torch - print("importing tiny torch done") - -torch.set_default_device("cuda") - -cuda_to_tiny_mappings = {} - -enumerator_aten_calls = itertools.count(0) -from torch.utils._python_dispatch import TorchDispatchMode -class DispatchLog(TorchDispatchMode): - def __torch_dispatch__(self, func, types, args, kwargs=None): - txt_args = [] - should_call_tiny = kwargs.get('device') is not None and kwargs['device'].type == "cuda" - - def can_print_arg(arg): - return args is None or isinstance(arg, (str, int, float, bool)) - - def create_tiny_mapping(arg): - if WRAP_TINY: - tt = Tensor.from_blob(arg.data_ptr(), arg.shape, dtype=_from_torch_dtype(arg.dtype)) - cuda_to_tiny_mappings[arg] = tiny_torch.wrap(tt) - - for i,arg in enumerate(args): - if torch.is_tensor(arg): - if arg.device.type == "cuda": - should_call_tiny = True - if WRAP_TINY: create_tiny_mapping(arg) - txt_args.append(f"tensor({arg.shape} {arg.device} {arg.dtype})") - elif can_print_arg(arg): txt_args.append(f'{arg}') - else: txt_args.append(f"{type(arg)}") - for k,v in (kwargs or {}).items(): - if torch.is_tensor(v): - if arg.device.type == "cuda": - should_call_tiny = True - if WRAP_TINY: create_tiny_mapping(arg) - txt_args.append(f"{k}:tensor({v.shape} {v.device} {v.dtype})") - elif can_print_arg(arg): txt_args.append(f'{k}:{arg}"') - else: txt_args.append(f"{type(arg)}") - - # magenta-colored kerenls mirrored to tiny backend. - aten_id = next(enumerator_aten_calls) - should_call_tiny = TINY_MIRROR and should_call_tiny - print(colored(f"#{aten_id} {func}", "magenta" if should_call_tiny else "cyan") + "("+", ".join(txt_args)+")", flush=True) - - # ignore dispatches if needed - hook_cuda.push_ignore_dispatch(RUN_ONLY >= 0 and RUN_ONLY != aten_id) - orig_x = func(*args, **(kwargs or {})) - - def print_events(evs, name, out_addr): - for ev in evs: - if isinstance(ev, hook_cuda.HookKernelCallEvent): - txt_params = [] - for param in ev.params: - if isinstance(param, hook_cuda.HookTensorParamEvent): - is_out = param.cuda_address == out_addr - txt_params += [f"{'result ' if is_out else ''}Tensor{param.enum}({param.cuda_address:#x})"] - - just_kern_name = ev.name - if not FULL_KERN_NAME: - just_kern_name = ev.name.replace("(anonymous namespace)", "").replace("void ", "").split("<")[0].split("(")[0].split("::")[-1] - print(f"\t {name} kernel {just_kern_name} {ev.grid} {ev.block} {ev.ptm}\n\t\t({', '.join(txt_params)})") - else: print("\t", name, ev) - - if REALIZE: - torch.cuda.synchronize() - cuda_events = hook_cuda.collect_events(clear=True) - print_events(cuda_events, colored("cuda", "cyan"), orig_x.data_ptr() if torch.is_tensor(orig_x) else 0x0) - - if should_call_tiny: - # replace with tiny tensor - tiny_args, tiny_kwargs = [], {} - for arg in args: - if torch.is_tensor(arg): tiny_args.append(cuda_to_tiny_mappings[arg]) - else: tiny_args.append(arg) - - for k,v in (kwargs or {}).items(): - if torch.is_tensor(v): tiny_kwargs[k] = cuda_to_tiny_mappings[v] - else: tiny_kwargs[k] = v - if 'device' in tiny_kwargs and kwargs['device'].type == "cuda": - tiny_kwargs['device'] = torch.device("tiny") - - tiny_x = func(*tiny_args, **tiny_kwargs) - - # TODO: this is a hack, any way to do this better? - if REALIZE: - out_addr = 0x0 - _ = tiny_x.cpu().numpy() - if torch.is_tensor(tiny_x) and tiny_x.device.type == "tiny": - tt = tiny_torch.unwrap(tiny_x) - try: out_addr = tt.uop.buffer._buf.value - except Exception: pass - tiny_events = hook_cuda.collect_events(clear=True) - print_events(tiny_events, colored("tiny", "magenta"), out_addr) - - if not WRAP_TINY: cuda_to_tiny_mappings[orig_x] = tiny_x - - hook_cuda.pop_ignore_dispatch() - return orig_x -DispatchLog().__enter__() - -if __name__ == "__main__": - if getenv("RESNET"): - import torchvision.models as models - model = models.resnet18(pretrained=True) - model = model.cuda() - model.eval() - - if getenv("COMPILE"): model = torch.compile(model) - - X = torch.rand(getenv("BS", 1), 3, 288, 288, device='cuda') - model(X) - - print("\n\n\n****** second run ******\n") - model(X) - else: - a = torch.randn(64, 64) - b = torch.randn(64, 64) - a += 1 - b += 2 - a = a.exp2() - b = b.exp2() - a += b - c = a @ b - print("tensor math done", c.cpu().numpy()) diff --git a/tinygrad/extra/training.py b/tinygrad/extra/training.py deleted file mode 100644 index d134e68b..00000000 --- a/tinygrad/extra/training.py +++ /dev/null @@ -1,58 +0,0 @@ -import numpy as np -from tinygrad.tensor import Tensor -from tinygrad.helpers import CI, trange -from tinygrad.engine.jit import TinyJit - - -def train(model, X_train, Y_train, optim, steps, BS=128, lossfn=lambda out,y: out.sparse_categorical_crossentropy(y), - transform=lambda x: x, target_transform=lambda x: x, noloss=False, allow_jit=True): - - def train_step(x, y): - # network - out = model.forward(x) if hasattr(model, 'forward') else model(x) - loss = lossfn(out, y) - optim.zero_grad() - loss.backward() - if noloss: del loss - optim.step() - if noloss: return (None, None) - cat = out.argmax(axis=-1) - accuracy = (cat == y).mean() - return loss.realize(), accuracy.realize() - - if allow_jit: train_step = TinyJit(train_step) - - with Tensor.train(): - losses, accuracies = [], [] - for i in (t := trange(steps, disable=CI)): - samp = np.random.randint(0, X_train.shape[0], size=(BS)) - x = Tensor(transform(X_train[samp]), requires_grad=False) - y = Tensor(target_transform(Y_train[samp])) - loss, accuracy = train_step(x, y) - # printing - if not noloss: - loss, accuracy = loss.numpy(), accuracy.numpy() - losses.append(loss) - accuracies.append(accuracy) - t.set_description("loss %.2f accuracy %.2f" % (loss, accuracy)) - return [losses, accuracies] - - -def evaluate(model, X_test, Y_test, num_classes=None, BS=128, return_predict=False, transform=lambda x: x, - target_transform=lambda y: y): - Tensor.training = False - def numpy_eval(Y_test, num_classes): - Y_test_preds_out = np.zeros(list(Y_test.shape)+[num_classes]) - for i in trange((len(Y_test)-1)//BS+1, disable=CI): - x = Tensor(transform(X_test[i*BS:(i+1)*BS])) - out = model.forward(x) if hasattr(model, 'forward') else model(x) - Y_test_preds_out[i*BS:(i+1)*BS] = out.numpy() - Y_test_preds = np.argmax(Y_test_preds_out, axis=-1) - Y_test = target_transform(Y_test) - return (Y_test == Y_test_preds).mean(), Y_test_preds - - if num_classes is None: num_classes = Y_test.max().astype(int)+1 - acc, Y_test_pred = numpy_eval(Y_test, num_classes) - print("test set accuracy is %f" % acc) - return (acc, Y_test_pred) if return_predict else acc - diff --git a/tinygrad/extra/transfer_speed.py b/tinygrad/extra/transfer_speed.py deleted file mode 100644 index 9abe475a..00000000 --- a/tinygrad/extra/transfer_speed.py +++ /dev/null @@ -1,18 +0,0 @@ -from tinygrad import Tensor, Device - -#N = 1024 -N = 32 -t = Tensor.rand(N, N, N, device="CPU").realize() -d1 = Device.DEFAULT + ":1" -d2 = Device.DEFAULT + ":2" -d3 = Device.DEFAULT + ":3" - -for i in range(3): - t.to_(d1) - t.realize() - # t.to_("CPU") - # t.realize() - t.to_(d2) - t.realize() - t.to_(d3) - t.realize() diff --git a/tinygrad/extra/usbgpu/.gitignore b/tinygrad/extra/usbgpu/.gitignore deleted file mode 100644 index b18935f3..00000000 --- a/tinygrad/extra/usbgpu/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -Software/ -fw.zip \ No newline at end of file diff --git a/tinygrad/extra/usbgpu/legacy/nvme_speed.py b/tinygrad/extra/usbgpu/legacy/nvme_speed.py deleted file mode 100644 index 88a9b525..00000000 --- a/tinygrad/extra/usbgpu/legacy/nvme_speed.py +++ /dev/null @@ -1,23 +0,0 @@ -import array, time, ctypes, struct, random -from hexdump import hexdump -from tinygrad.runtime.support.usb import ASM24Controller, WriteOp, ScsiWriteOp -from tinygrad.runtime.autogen import pci -from tinygrad.helpers import Timing -from tinygrad import Device - -usb = ASM24Controller() - -def real_scsi_write(): - self.exec_ops([ScsiWriteOp(buf, lba)]) - -for i in range(256): - xxx = (ctypes.c_uint8 * 4096)() - dfg = random.randint(0, 255) - for i in range(len(xxx)): xxx[i] = dfg - # print(dfg, usb.read(0xf000, 0x10)) - st = time.perf_counter_ns() - usb.scsi_write(bytes(xxx), lba=0x1000 + i) - en = time.perf_counter_ns() - print("mb/s is ", (0x1000) / (en - st) * 1e9 / 1024 / 1024) - -exit(0) diff --git a/tinygrad/extra/usbgpu/legacy/patch_exp.py b/tinygrad/extra/usbgpu/legacy/patch_exp.py deleted file mode 100755 index 9b39037a..00000000 --- a/tinygrad/extra/usbgpu/legacy/patch_exp.py +++ /dev/null @@ -1,88 +0,0 @@ -#!/usr/bin/env python3 -import sys -import zlib - -def patch(input_filepath, output_filepath, patches): - with open(input_filepath, 'rb') as infile: data = bytearray(infile.read()) - - for offset, expected_bytes, new_bytes in patches: - if len(expected_bytes) != len(new_bytes): - print(len(expected_bytes), len(new_bytes)) - raise ValueError("Expected bytes and new bytes must be the same length") - - if offset + len(new_bytes) > len(data): return False - current_bytes = data[offset:offset + len(expected_bytes)] - assert bytes(current_bytes) == expected_bytes, f"Expected {expected_bytes} at offset {offset:x}, but got {current_bytes}" - data[offset:offset + len(new_bytes)] = new_bytes - - checksum = sum(data[4:-6]) & 0xff - crc32 = zlib.crc32(data[4:-6]).to_bytes(4, 'little') - data[-5] = checksum - data[-4] = crc32[0] - data[-3] = crc32[1] - data[-2] = crc32[2] - data[-1] = crc32[3] - - with open(output_filepath, 'wb') as outfile: - outfile.write(data) - - return True - -patches = [ - # (0x3903 + 1 + 4, b'\x8a', b'\x8b'), - # (0x3cf9 + 1 + 4, b'\x8a', b'\x8b'), # this is the one which triggered... - - (0x2a0d + 1 + 4, b'\x0a', b'\x05'), # write handle exit with code 5 (?) - # (0x40e1 + 4, b'\x90\x06\xe6\x04\xf0\x78\x0d\xe6\xfe\x24\x71\x12\x1b\x0b\x60\x0b\x74\x08', b'\x7f\x00\x12\x53\x21\x12\x1c\xfc\x74\x01\xf6\x90\x90\x94\x74\x10\xf0\x22') - # (0x29ad + 1 + 4, b'\x09', b'\x05'), # write handle exit with code 5 (?) - # (0x40ef + 0 + 4, b'\x60', b'\x70'), # jz -> jnz - # (0x40e1 + 0 + 4, b'\x90', b'\x22'), # jmp -> ret - # (0x40fa + 0 + 4, b'\x80', b'\x22'), - # (0x40e1 + 0 + 4, b'\x90\x06\xe6\x04\xf0', b'\x7f\x00\x02\x41\x7c'), # jmp -> ret -] - -next_traphandler = 0 -def add_traphandler(addr, sec): - global next_traphandler, patches - - trap_addr = 0x6000 + next_traphandler * 0x20 - return_addr = addr + len(sec) - cntr_addr = 0x3000 + next_traphandler - patches += [ - (addr + 4, sec, b'\x02' + trap_addr.to_bytes(2, 'big') + b'\x22'*(len(sec)-3)), - (trap_addr + 4, b'\x00' * (21 + len(sec)), - b'\xc0\xe0\xc0\x82\xc0\x83\x90' + cntr_addr.to_bytes(2, 'big') + b'\xe0\x04\xf0\xd0\x83\xd0\x82\xd0\xe0' + sec + b'\x02' + return_addr.to_bytes(2, 'big')), - ] - next_traphandler += 1 - -# add_traphandler(0x0206, b'\xed\x54\x06') # fill_scsi_resp -# add_traphandler(0x40d9, b'\x78\x6a\xe6') # fill_scsi_to_usb_transport -# add_traphandler(0x4d44, b'\x78\x6a\xe6') # FUN_CODE_4d44 -# add_traphandler(0x4784, b'\x78\x6a\xe6') # FUN_CODE_4784 -# add_traphandler(0x3e81, b'\x90\xc5\x16') # FUN_CODE_3e81 -# add_traphandler(0x32a5, b'\x78\x6a\xe6') # FUN_CODE_32a5 -# add_traphandler(0x2a10, b'\x90\xc4\x51') # FUN_CODE_2a10 -# add_traphandler(0x2608, b'\x12\x16\x87') # FUN_CODE_2608 -# add_traphandler(0x0e78, b'\x90\xc8\x02') # main usb entry -# add_traphandler(0x102f, b'\x12\x18\x0d') # possible scsi entry parser -# add_traphandler(0x1198, b'\x12\x18\x0d') # close_to_scsi_parse_1_and_set_c47a_to_0xff caller to scsi -# add_traphandler(0x180d, b'\x90\x0a\x7d') # close_to_scsi_parse -# add_traphandler(0x1114, b'\x75\x37\x00') # entry into if ((DAT_EXTMEM_c802 >> 2 & 1) != 0) { in main usb entry -# add_traphandler(0x113a, b'\x90\x90\x00') # exit from scsi parse loop -# add_traphandler(0x117b, b'\xd0\x07\xd0\x06') # exit from main usb entry - - -# add_traphandler(0x2f81, b'\x90\x0a\x59') # main loop? 8 -# add_traphandler(0xc7a7, b'\x90\x09\xfa') # call smth in write path 9 -# add_traphandler(0x2fcb, b'\x90\x0a\x59') # if ((DAT_EXTMEM_0ae2 != 0) && (DAT_EXTMEM_0ae2 != 0x10)) { -# add_traphandler(0x2fc0, b'\x90\x0a\xe2') # submain loop 11 -# add_traphandler(0x30be, b'\x90\x0a\x5a') # aft sub loop 12 -# add_traphandler(0x3076, b'\x12\x03\x59') # call to call_wait_for_nvme??(); 13 -# add_traphandler(0x30ad, b'\x12\x04\xe4') # call to call_wait_for_nvme??(); 14 - -# add_traphandler(0x2608, b'\x12\x16\x87') # FUN_CODE_2608 -# add_traphandler(0x10ee, b'\x90\x04\x64') # iniside trap handler -# add_traphandler(0x10e0, b'\x90\xc8\x06') # iniside trap handler -# add_traphandler(0x4977, b'\x90\x0a\xa8') # waiter for nvme??? - -assert patch(sys.argv[1], sys.argv[2], patches) is True diff --git a/tinygrad/extra/usbgpu/legacy/wr_speed.py b/tinygrad/extra/usbgpu/legacy/wr_speed.py deleted file mode 100644 index e157022d..00000000 --- a/tinygrad/extra/usbgpu/legacy/wr_speed.py +++ /dev/null @@ -1,22 +0,0 @@ -import array, time, ctypes, struct, random -from hexdump import hexdump -from tinygrad.runtime.support.usb import ASMController, WriteOp -from tinygrad.runtime.autogen import pci -from tinygrad.helpers import Timing -from tinygrad import Device - -usb = ASMController() - -xxx = (ctypes.c_uint8 * 4096)() -dfg = random.randint(0, 255) -for i in range(len(xxx)): xxx[i] = dfg - -print(dfg, usb.read(0xf000, 0x10)) - -with Timing(): - for i in range(64): usb.scsi_write(xxx) - -with Timing(): - for i in range(64): usb.read(0xf000, 0x1000) - -exit(0) diff --git a/tinygrad/extra/usbgpu/patch.py b/tinygrad/extra/usbgpu/patch.py deleted file mode 100755 index e9e62682..00000000 --- a/tinygrad/extra/usbgpu/patch.py +++ /dev/null @@ -1,88 +0,0 @@ -#!/usr/bin/env python3 -import sys, os, zlib, struct, hashlib -from hexdump import hexdump -from tinygrad.helpers import DEBUG, getenv, fetch -from tinygrad.runtime.support.usb import USB3 - -def patch(input_filepath, file_hash, patches): - with open(input_filepath, 'rb') as infile: data = bytearray(infile.read()) - - if_hash = hashlib.md5(data).hexdigest() - if if_hash != file_hash: - raise ValueError(f"File hash mismatch: expected {file_hash}, got {if_hash}") - - for offset, expected_bytes, new_bytes in patches: - if len(expected_bytes) != len(new_bytes): - raise ValueError("Expected bytes and new bytes must be the same length") - - if offset + len(new_bytes) > len(data): return False - current_bytes = data[offset:offset + len(expected_bytes)] - assert bytes(current_bytes) == expected_bytes, f"Expected {expected_bytes} at offset {offset:x}, but got {current_bytes}" - data[offset:offset + len(new_bytes)] = new_bytes - - checksum = sum(data[4:-6]) & 0xff - crc32 = zlib.crc32(data[4:-6]).to_bytes(4, 'little') - data[-5] = checksum - data[-4] = crc32[0] - data[-3] = crc32[1] - data[-2] = crc32[2] - data[-1] = crc32[3] - return data - -path = os.path.dirname(os.path.abspath(__file__)) -file_hash = "5284e618d96ef804c06f47f3b73656b7" -file_path = os.path.join(path, "Software/AS_USB4_240417_85_00_00.bin") - -if not os.path.exists(file_path): - url = "https://web.archive.org/web/20250430124720/https://www.station-drivers.com/index.php/en/component/remository/func-download/6341/chk,3ef8b04704a18eb2fc57ff60382379ad/no_html,1/lang,en-gb/" - os.system(f'curl -o "{path}/fw.zip" "{url}"') - os.system(f'unzip -o "{path}/fw.zip" "Software/AS_USB4_240417_85_00_00.bin" -d "{path}"') - -patches = [(0x2a0d + 1 + 4, b'\x0a', b'\x05')] -patched_fw = patch(file_path, file_hash, patches) - -vendor, device = [int(x, base=16) for x in getenv("USBDEV", "174C:2464").split(":")] -try: dev = USB3(vendor, device, 0x81, 0x83, 0x02, 0x04) -except RuntimeError as e: - raise RuntimeError(f'{e}. You can set USBDEV environment variable to your device\'s vendor and device ID (e.g., USBDEV="174C:2464")') from e - -config1 = bytes([ - 0xFF, 0xFF, 0xFF, 0xFF, 0x41, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, 0x42, 0x30, 0x30, 0x36, 0x30, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x74, 0x69, 0x6E, 0x79, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x74, 0x69, 0x6E, 0x79, - 0xFF, 0xFF, 0xFF, 0xFF, 0x55, 0x53, 0x42, 0x20, 0x33, 0x2E, 0x32, 0x20, 0x50, 0x43, 0x49, 0x65, - 0x20, 0x54, 0x69, 0x6E, 0x79, 0x45, 0x6E, 0x63, 0x6C, 0x6F, 0x73, 0x75, 0x72, 0x65, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x54, 0x69, 0x6E, 0x79, 0x45, 0x6E, 0x63, 0x6C, 0x6F, 0x73, 0x75, 0x72, - 0x65, 0xFF, 0xFF, 0xFF, 0xD1, 0xAD, 0x01, 0x00, 0x00, 0x01, 0xCF, 0xFF, 0x02, 0xFF, 0x5A, 0x94]) - -config2 = bytes([ - 0xFF, 0xFF, 0xFF, 0xFF, 0x47, 0x6F, 0x70, 0x6F, 0x64, 0x20, 0x47, 0x72, 0x6F, 0x75, 0x70, 0x20, - 0x4C, 0x69, 0x6D, 0x69, 0x74, 0x65, 0x64, 0x2E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x55, 0x53, 0x42, 0x34, - 0x20, 0x4E, 0x56, 0x4D, 0x65, 0x20, 0x53, 0x53, 0x44, 0x20, 0x50, 0x72, 0x6F, 0x20, 0x45, 0x6E, - 0x63, 0x6C, 0x6F, 0x73, 0x75, 0x72, 0x65, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x8C, 0xBF, 0xFF, 0x97, 0xC1, 0xF3, 0xFF, 0xFF, 0x01, 0x2D, 0x66, 0xD6, - 0x66, 0x06, 0x00, 0xC0, 0x87, 0x01, 0x5A, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCA, 0x01, 0x66, 0xD6, - 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xA5, 0x67]) - -part1 = patched_fw[:0xff00] -part2 = patched_fw[0xff00:] - -# config patch -cdb = struct.pack('>BBB12x', 0xe1, 0x50, 0x0) -dev.send_batch(cdbs=[cdb], odata=[config1]) - -cdb = struct.pack('>BBB12x', 0xe1, 0x50, 0x1) -dev.send_batch(cdbs=[cdb], odata=[config2]) - -cdb = struct.pack('>BBI', 0xe3, 0x50, len(part1)) -dev.send_batch(cdbs=[cdb], odata=[part1]) - -cdb = struct.pack('>BBI', 0xe3, 0xd0, len(part2)) -dev.send_batch(cdbs=[cdb], odata=[part2]) - -cdb = struct.pack('>BB13x', 0xe8, 0x51) -dev.send_batch(cdbs=[cdb]) - -print("done, you can disconnect the controller!") diff --git a/tinygrad/extra/usbgpu/scan_pci.py b/tinygrad/extra/usbgpu/scan_pci.py deleted file mode 100644 index 4eb60c40..00000000 --- a/tinygrad/extra/usbgpu/scan_pci.py +++ /dev/null @@ -1,67 +0,0 @@ -import array, time -from hexdump import hexdump -from tinygrad.runtime.support.usb import ASM24Controller -from tinygrad.runtime.autogen import pci - -usb = ASM24Controller() - -def print_cfg(bus, dev): - cfg = [] - for i in range(0, 256, 4): - cfg.append(usb.pcie_cfg_req(i, bus=bus, dev=dev, fn=0, value=None, size=4)) - - print("bus={}, dev={}".format(bus, dev)) - dmp = bytearray(array.array('I', cfg)) - hexdump(dmp) - return dmp - -def rescan_bus(bus, gpu_bus): - print("set PCI_SUBORDINATE_BUS bus={} to {}".format(bus, gpu_bus)) - usb.pcie_cfg_req(pci.PCI_SUBORDINATE_BUS, bus=bus, dev=0, fn=0, value=gpu_bus, size=1) - usb.pcie_cfg_req(pci.PCI_SECONDARY_BUS, bus=bus, dev=0, fn=0, value=bus+1, size=1) - usb.pcie_cfg_req(pci.PCI_PRIMARY_BUS, bus=bus, dev=0, fn=0, value=max(0, bus-1), size=1) - - print("rescan bus={}".format(bus)) - usb.pcie_cfg_req(pci.PCI_BRIDGE_CONTROL, bus=bus, dev=0, fn=0, value=pci.PCI_BRIDGE_CTL_BUS_RESET, size=1) - time.sleep(0.1) - usb.pcie_cfg_req(pci.PCI_BRIDGE_CONTROL, bus=bus, dev=0, fn=0, value=pci.PCI_BRIDGE_CTL_PARITY|pci.PCI_BRIDGE_CTL_SERR, size=1) - - usb.pcie_cfg_req(pci.PCI_MEMORY_BASE, bus=bus, dev=0, fn=0, value=0x1000, size=2) - usb.pcie_cfg_req(pci.PCI_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0x2000, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_BASE, bus=bus, dev=0, fn=0, value=0x2000, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0xffff, size=2) - -print_cfg(0, 0) -rescan_bus(0, gpu_bus=4) - -print_cfg(1, 0) -rescan_bus(1, gpu_bus=4) - -time.sleep(0.1) -print_cfg(2, 0) - -def setup_bus(bus, gpu_bus): - print("setup bus={}".format(bus)) - usb.pcie_cfg_req(pci.PCI_SUBORDINATE_BUS, bus=bus, dev=0, fn=0, value=gpu_bus, size=1) - usb.pcie_cfg_req(pci.PCI_SECONDARY_BUS, bus=bus, dev=0, fn=0, value=bus+1, size=1) - usb.pcie_cfg_req(pci.PCI_PRIMARY_BUS, bus=bus, dev=0, fn=0, value=max(0, bus-1), size=1) - - usb.pcie_cfg_req(pci.PCI_BRIDGE_CONTROL, bus=bus, dev=0, fn=0, value=pci.PCI_BRIDGE_CTL_BUS_RESET, size=1) - usb.pcie_cfg_req(pci.PCI_BRIDGE_CONTROL, bus=bus, dev=0, fn=0, value=pci.PCI_BRIDGE_CTL_PARITY|pci.PCI_BRIDGE_CTL_SERR, size=1) - usb.pcie_cfg_req(pci.PCI_COMMAND, bus=bus, dev=0, fn=0, value=pci.PCI_COMMAND_IO | pci.PCI_COMMAND_MEMORY | pci.PCI_COMMAND_MASTER, size=1) - - usb.pcie_cfg_req(pci.PCI_MEMORY_BASE, bus=bus, dev=0, fn=0, value=0x1000, size=2) - usb.pcie_cfg_req(pci.PCI_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0x2000, size=2) - - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_BASE, bus=bus, dev=0, fn=0, value=0x2000, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0xffff, size=2) - -setup_bus(2, gpu_bus=4) -print_cfg(3, 0) - -setup_bus(3, gpu_bus=4) -dmp = print_cfg(4, 0) -print(dmp[0:4]) -assert dmp[0:4] in (b"\x02\x10\x80\x74", b"\x02\x10\x4c\x74", b"\x02\x10\x50\x75"), "GPU NOT FOUND!" - -print("GPU FOUND!") diff --git a/tinygrad/extra/webgpu/webgpu.h b/tinygrad/extra/webgpu/webgpu.h deleted file mode 100644 index 0614d45d..00000000 --- a/tinygrad/extra/webgpu/webgpu.h +++ /dev/null @@ -1,4265 +0,0 @@ -// BSD 3-Clause License -// -// Copyright (c) 2019, "WebGPU native" developers -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#ifdef __EMSCRIPTEN__ -#error "Do not include this header. Emscripten already provides headers needed for WebGPU." -#endif - -#ifndef WEBGPU_H_ -#define WEBGPU_H_ - -#define WGPU_BREAKING_CHANGE_STRING_VIEW_LABELS -#define WGPU_BREAKING_CHANGE_STRING_VIEW_OUTPUT_STRUCTS -#define WGPU_BREAKING_CHANGE_STRING_VIEW_CALLBACKS - -#if defined(WGPU_SHARED_LIBRARY) -# if defined(_WIN32) -# if defined(WGPU_IMPLEMENTATION) -# define WGPU_EXPORT __declspec(dllexport) -# else -# define WGPU_EXPORT __declspec(dllimport) -# endif -# else // defined(_WIN32) -# if defined(WGPU_IMPLEMENTATION) -# define WGPU_EXPORT __attribute__((visibility("default"))) -# else -# define WGPU_EXPORT -# endif -# endif // defined(_WIN32) -#else // defined(WGPU_SHARED_LIBRARY) -# define WGPU_EXPORT -#endif // defined(WGPU_SHARED_LIBRARY) - -#if !defined(WGPU_OBJECT_ATTRIBUTE) -#define WGPU_OBJECT_ATTRIBUTE -#endif -#if !defined(WGPU_ENUM_ATTRIBUTE) -#define WGPU_ENUM_ATTRIBUTE -#endif -#if !defined(WGPU_STRUCTURE_ATTRIBUTE) -#define WGPU_STRUCTURE_ATTRIBUTE -#endif -#if !defined(WGPU_FUNCTION_ATTRIBUTE) -#define WGPU_FUNCTION_ATTRIBUTE -#endif -#if !defined(WGPU_NULLABLE) -#define WGPU_NULLABLE -#endif - -#define WGPU_BREAKING_CHANGE_DROP_DESCRIPTOR - -#include -#include - -#if defined(__cplusplus) -# if __cplusplus >= 201103L -# define WGPU_MAKE_INIT_STRUCT(type, value) (type value) -# else -# define WGPU_MAKE_INIT_STRUCT(type, value) value -# endif -#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L -# define WGPU_MAKE_INIT_STRUCT(type, value) ((type) value) -#else -# define WGPU_MAKE_INIT_STRUCT(type, value) value -#endif - -#define WGPU_ARRAY_LAYER_COUNT_UNDEFINED UINT32_MAX -#define WGPU_COPY_STRIDE_UNDEFINED UINT32_MAX -#define WGPU_DEPTH_SLICE_UNDEFINED UINT32_MAX -#define WGPU_LIMIT_U32_UNDEFINED UINT32_MAX -#define WGPU_LIMIT_U64_UNDEFINED UINT64_MAX -#define WGPU_MIP_LEVEL_COUNT_UNDEFINED UINT32_MAX -#define WGPU_QUERY_SET_INDEX_UNDEFINED UINT32_MAX -#define WGPU_STRLEN SIZE_MAX -#define WGPU_WHOLE_MAP_SIZE SIZE_MAX -#define WGPU_WHOLE_SIZE UINT64_MAX - -typedef uint64_t WGPUFlags; -typedef uint32_t WGPUBool; - -typedef struct WGPUAdapterImpl* WGPUAdapter WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUBindGroupImpl* WGPUBindGroup WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUBindGroupLayoutImpl* WGPUBindGroupLayout WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUBufferImpl* WGPUBuffer WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUCommandBufferImpl* WGPUCommandBuffer WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUCommandEncoderImpl* WGPUCommandEncoder WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUComputePassEncoderImpl* WGPUComputePassEncoder WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUComputePipelineImpl* WGPUComputePipeline WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUDeviceImpl* WGPUDevice WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUExternalTextureImpl* WGPUExternalTexture WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUInstanceImpl* WGPUInstance WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUPipelineLayoutImpl* WGPUPipelineLayout WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUQuerySetImpl* WGPUQuerySet WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUQueueImpl* WGPUQueue WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPURenderBundleImpl* WGPURenderBundle WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPURenderBundleEncoderImpl* WGPURenderBundleEncoder WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPURenderPassEncoderImpl* WGPURenderPassEncoder WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPURenderPipelineImpl* WGPURenderPipeline WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUSamplerImpl* WGPUSampler WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUShaderModuleImpl* WGPUShaderModule WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUSharedBufferMemoryImpl* WGPUSharedBufferMemory WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUSharedFenceImpl* WGPUSharedFence WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUSharedTextureMemoryImpl* WGPUSharedTextureMemory WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUSurfaceImpl* WGPUSurface WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUTextureImpl* WGPUTexture WGPU_OBJECT_ATTRIBUTE; -typedef struct WGPUTextureViewImpl* WGPUTextureView WGPU_OBJECT_ATTRIBUTE; - -// Structure forward declarations -struct WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER; -struct WGPUAdapterPropertiesD3D; -struct WGPUAdapterPropertiesSubgroups; -struct WGPUAdapterPropertiesVk; -struct WGPUBindGroupEntry; -struct WGPUBlendComponent; -struct WGPUBufferBindingLayout; -struct WGPUBufferHostMappedPointer; -struct WGPUBufferMapCallbackInfo; -struct WGPUColor; -struct WGPUColorTargetStateExpandResolveTextureDawn; -struct WGPUCompilationInfoCallbackInfo; -struct WGPUComputePassTimestampWrites; -struct WGPUCopyTextureForBrowserOptions; -struct WGPUCreateComputePipelineAsyncCallbackInfo; -struct WGPUCreateRenderPipelineAsyncCallbackInfo; -struct WGPUDawnWGSLBlocklist; -struct WGPUDawnAdapterPropertiesPowerPreference; -struct WGPUDawnBufferDescriptorErrorInfoFromWireClient; -struct WGPUDawnEncoderInternalUsageDescriptor; -struct WGPUDawnExperimentalImmediateDataLimits; -struct WGPUDawnExperimentalSubgroupLimits; -struct WGPUDawnRenderPassColorAttachmentRenderToSingleSampled; -struct WGPUDawnShaderModuleSPIRVOptionsDescriptor; -struct WGPUDawnTexelCopyBufferRowAlignmentLimits; -struct WGPUDawnTextureInternalUsageDescriptor; -struct WGPUDawnTogglesDescriptor; -struct WGPUDawnWireWGSLControl; -struct WGPUDeviceLostCallbackInfo; -struct WGPUDrmFormatProperties; -struct WGPUExtent2D; -struct WGPUExtent3D; -struct WGPUExternalTextureBindingEntry; -struct WGPUExternalTextureBindingLayout; -struct WGPUFormatCapabilities; -struct WGPUFuture; -struct WGPUInstanceFeatures; -struct WGPULimits; -struct WGPUMemoryHeapInfo; -struct WGPUMultisampleState; -struct WGPUOrigin2D; -struct WGPUOrigin3D; -struct WGPUPipelineLayoutStorageAttachment; -struct WGPUPopErrorScopeCallbackInfo; -struct WGPUPrimitiveState; -struct WGPUQueueWorkDoneCallbackInfo; -struct WGPURenderPassDepthStencilAttachment; -struct WGPURenderPassDescriptorExpandResolveRect; -struct WGPURenderPassMaxDrawCount; -struct WGPURenderPassTimestampWrites; -struct WGPURequestAdapterCallbackInfo; -struct WGPURequestAdapterOptions; -struct WGPURequestDeviceCallbackInfo; -struct WGPUSamplerBindingLayout; -struct WGPUShaderModuleCompilationOptions; -struct WGPUShaderSourceSPIRV; -struct WGPUSharedBufferMemoryBeginAccessDescriptor; -struct WGPUSharedBufferMemoryEndAccessState; -struct WGPUSharedBufferMemoryProperties; -struct WGPUSharedFenceDXGISharedHandleDescriptor; -struct WGPUSharedFenceDXGISharedHandleExportInfo; -struct WGPUSharedFenceMTLSharedEventDescriptor; -struct WGPUSharedFenceMTLSharedEventExportInfo; -struct WGPUSharedFenceExportInfo; -struct WGPUSharedFenceSyncFDDescriptor; -struct WGPUSharedFenceSyncFDExportInfo; -struct WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor; -struct WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo; -struct WGPUSharedFenceVkSemaphoreZirconHandleDescriptor; -struct WGPUSharedFenceVkSemaphoreZirconHandleExportInfo; -struct WGPUSharedTextureMemoryD3DSwapchainBeginState; -struct WGPUSharedTextureMemoryDXGISharedHandleDescriptor; -struct WGPUSharedTextureMemoryEGLImageDescriptor; -struct WGPUSharedTextureMemoryIOSurfaceDescriptor; -struct WGPUSharedTextureMemoryAHardwareBufferDescriptor; -struct WGPUSharedTextureMemoryBeginAccessDescriptor; -struct WGPUSharedTextureMemoryDmaBufPlane; -struct WGPUSharedTextureMemoryEndAccessState; -struct WGPUSharedTextureMemoryOpaqueFDDescriptor; -struct WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor; -struct WGPUSharedTextureMemoryVkImageLayoutBeginState; -struct WGPUSharedTextureMemoryVkImageLayoutEndState; -struct WGPUSharedTextureMemoryZirconHandleDescriptor; -struct WGPUStaticSamplerBindingLayout; -struct WGPUStencilFaceState; -struct WGPUStorageTextureBindingLayout; -struct WGPUStringView; -struct WGPUSupportedFeatures; -struct WGPUSurfaceCapabilities; -struct WGPUSurfaceConfiguration; -struct WGPUSurfaceDescriptorFromWindowsCoreWindow; -struct WGPUSurfaceDescriptorFromWindowsSwapChainPanel; -struct WGPUSurfaceSourceXCBWindow; -struct WGPUSurfaceSourceAndroidNativeWindow; -struct WGPUSurfaceSourceMetalLayer; -struct WGPUSurfaceSourceWaylandSurface; -struct WGPUSurfaceSourceWindowsHWND; -struct WGPUSurfaceSourceXlibWindow; -struct WGPUSurfaceTexture; -struct WGPUTextureBindingLayout; -struct WGPUTextureBindingViewDimensionDescriptor; -struct WGPUTextureDataLayout; -struct WGPUUncapturedErrorCallbackInfo; -struct WGPUVertexAttribute; -struct WGPUYCbCrVkDescriptor; -struct WGPUAHardwareBufferProperties; -struct WGPUAdapterInfo; -struct WGPUAdapterPropertiesMemoryHeaps; -struct WGPUBindGroupDescriptor; -struct WGPUBindGroupLayoutEntry; -struct WGPUBlendState; -struct WGPUBufferDescriptor; -struct WGPUCommandBufferDescriptor; -struct WGPUCommandEncoderDescriptor; -struct WGPUCompilationMessage; -struct WGPUComputePassDescriptor; -struct WGPUConstantEntry; -struct WGPUDawnCacheDeviceDescriptor; -struct WGPUDepthStencilState; -struct WGPUDrmFormatCapabilities; -struct WGPUExternalTextureDescriptor; -struct WGPUFutureWaitInfo; -struct WGPUImageCopyBuffer; -struct WGPUImageCopyExternalTexture; -struct WGPUImageCopyTexture; -struct WGPUInstanceDescriptor; -struct WGPUPipelineLayoutDescriptor; -struct WGPUPipelineLayoutPixelLocalStorage; -struct WGPUQuerySetDescriptor; -struct WGPUQueueDescriptor; -struct WGPURenderBundleDescriptor; -struct WGPURenderBundleEncoderDescriptor; -struct WGPURenderPassColorAttachment; -struct WGPURenderPassStorageAttachment; -struct WGPURequiredLimits; -struct WGPUSamplerDescriptor; -struct WGPUShaderModuleDescriptor; -struct WGPUShaderSourceWGSL; -struct WGPUSharedBufferMemoryDescriptor; -struct WGPUSharedFenceDescriptor; -struct WGPUSharedTextureMemoryAHardwareBufferProperties; -struct WGPUSharedTextureMemoryDescriptor; -struct WGPUSharedTextureMemoryDmaBufDescriptor; -struct WGPUSharedTextureMemoryProperties; -struct WGPUSupportedLimits; -struct WGPUSurfaceDescriptor; -struct WGPUSurfaceSourceCanvasHTMLSelector_Emscripten; -struct WGPUTextureDescriptor; -struct WGPUTextureViewDescriptor; -struct WGPUVertexBufferLayout; -struct WGPUBindGroupLayoutDescriptor; -struct WGPUColorTargetState; -struct WGPUCompilationInfo; -struct WGPUComputeState; -struct WGPUDeviceDescriptor; -struct WGPURenderPassDescriptor; -struct WGPURenderPassPixelLocalStorage; -struct WGPUVertexState; -struct WGPUComputePipelineDescriptor; -struct WGPUFragmentState; -struct WGPURenderPipelineDescriptor; - -typedef enum WGPUWGSLFeatureName { - WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures = 0x00000001, - WGPUWGSLFeatureName_Packed4x8IntegerDotProduct = 0x00000002, - WGPUWGSLFeatureName_UnrestrictedPointerParameters = 0x00000003, - WGPUWGSLFeatureName_PointerCompositeAccess = 0x00000004, - WGPUWGSLFeatureName_ChromiumTestingUnimplemented = 0x00050000, - WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental = 0x00050001, - WGPUWGSLFeatureName_ChromiumTestingExperimental = 0x00050002, - WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch = 0x00050003, - WGPUWGSLFeatureName_ChromiumTestingShipped = 0x00050004, - WGPUWGSLFeatureName_Force32 = 0x7FFFFFFF -} WGPUWGSLFeatureName WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUAdapterType { - WGPUAdapterType_DiscreteGPU = 0x00000001, - WGPUAdapterType_IntegratedGPU = 0x00000002, - WGPUAdapterType_CPU = 0x00000003, - WGPUAdapterType_Unknown = 0x00000004, - WGPUAdapterType_Force32 = 0x7FFFFFFF -} WGPUAdapterType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUAddressMode { - WGPUAddressMode_Undefined = 0x00000000, - WGPUAddressMode_ClampToEdge = 0x00000001, - WGPUAddressMode_Repeat = 0x00000002, - WGPUAddressMode_MirrorRepeat = 0x00000003, - WGPUAddressMode_Force32 = 0x7FFFFFFF -} WGPUAddressMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUAlphaMode { - WGPUAlphaMode_Opaque = 0x00000001, - WGPUAlphaMode_Premultiplied = 0x00000002, - WGPUAlphaMode_Unpremultiplied = 0x00000003, - WGPUAlphaMode_Force32 = 0x7FFFFFFF -} WGPUAlphaMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBackendType { - WGPUBackendType_Undefined = 0x00000000, - WGPUBackendType_Null = 0x00000001, - WGPUBackendType_WebGPU = 0x00000002, - WGPUBackendType_D3D11 = 0x00000003, - WGPUBackendType_D3D12 = 0x00000004, - WGPUBackendType_Metal = 0x00000005, - WGPUBackendType_Vulkan = 0x00000006, - WGPUBackendType_OpenGL = 0x00000007, - WGPUBackendType_OpenGLES = 0x00000008, - WGPUBackendType_Force32 = 0x7FFFFFFF -} WGPUBackendType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBlendFactor { - WGPUBlendFactor_Undefined = 0x00000000, - WGPUBlendFactor_Zero = 0x00000001, - WGPUBlendFactor_One = 0x00000002, - WGPUBlendFactor_Src = 0x00000003, - WGPUBlendFactor_OneMinusSrc = 0x00000004, - WGPUBlendFactor_SrcAlpha = 0x00000005, - WGPUBlendFactor_OneMinusSrcAlpha = 0x00000006, - WGPUBlendFactor_Dst = 0x00000007, - WGPUBlendFactor_OneMinusDst = 0x00000008, - WGPUBlendFactor_DstAlpha = 0x00000009, - WGPUBlendFactor_OneMinusDstAlpha = 0x0000000A, - WGPUBlendFactor_SrcAlphaSaturated = 0x0000000B, - WGPUBlendFactor_Constant = 0x0000000C, - WGPUBlendFactor_OneMinusConstant = 0x0000000D, - WGPUBlendFactor_Src1 = 0x0000000E, - WGPUBlendFactor_OneMinusSrc1 = 0x0000000F, - WGPUBlendFactor_Src1Alpha = 0x00000010, - WGPUBlendFactor_OneMinusSrc1Alpha = 0x00000011, - WGPUBlendFactor_Force32 = 0x7FFFFFFF -} WGPUBlendFactor WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBlendOperation { - WGPUBlendOperation_Undefined = 0x00000000, - WGPUBlendOperation_Add = 0x00000001, - WGPUBlendOperation_Subtract = 0x00000002, - WGPUBlendOperation_ReverseSubtract = 0x00000003, - WGPUBlendOperation_Min = 0x00000004, - WGPUBlendOperation_Max = 0x00000005, - WGPUBlendOperation_Force32 = 0x7FFFFFFF -} WGPUBlendOperation WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBufferBindingType { - WGPUBufferBindingType_BindingNotUsed = 0x00000000, - WGPUBufferBindingType_Uniform = 0x00000001, - WGPUBufferBindingType_Storage = 0x00000002, - WGPUBufferBindingType_ReadOnlyStorage = 0x00000003, - WGPUBufferBindingType_Force32 = 0x7FFFFFFF -} WGPUBufferBindingType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBufferMapAsyncStatus { - WGPUBufferMapAsyncStatus_Success = 0x00000001, - WGPUBufferMapAsyncStatus_InstanceDropped = 0x00000002, - WGPUBufferMapAsyncStatus_ValidationError = 0x00000003, - WGPUBufferMapAsyncStatus_Unknown = 0x00000004, - WGPUBufferMapAsyncStatus_DeviceLost = 0x00000005, - WGPUBufferMapAsyncStatus_DestroyedBeforeCallback = 0x00000006, - WGPUBufferMapAsyncStatus_UnmappedBeforeCallback = 0x00000007, - WGPUBufferMapAsyncStatus_MappingAlreadyPending = 0x00000008, - WGPUBufferMapAsyncStatus_OffsetOutOfRange = 0x00000009, - WGPUBufferMapAsyncStatus_SizeOutOfRange = 0x0000000A, - WGPUBufferMapAsyncStatus_Force32 = 0x7FFFFFFF -} WGPUBufferMapAsyncStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUBufferMapState { - WGPUBufferMapState_Unmapped = 0x00000001, - WGPUBufferMapState_Pending = 0x00000002, - WGPUBufferMapState_Mapped = 0x00000003, - WGPUBufferMapState_Force32 = 0x7FFFFFFF -} WGPUBufferMapState WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCallbackMode { - WGPUCallbackMode_WaitAnyOnly = 0x00000001, - WGPUCallbackMode_AllowProcessEvents = 0x00000002, - WGPUCallbackMode_AllowSpontaneous = 0x00000003, - WGPUCallbackMode_Force32 = 0x7FFFFFFF -} WGPUCallbackMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCompareFunction { - WGPUCompareFunction_Undefined = 0x00000000, - WGPUCompareFunction_Never = 0x00000001, - WGPUCompareFunction_Less = 0x00000002, - WGPUCompareFunction_Equal = 0x00000003, - WGPUCompareFunction_LessEqual = 0x00000004, - WGPUCompareFunction_Greater = 0x00000005, - WGPUCompareFunction_NotEqual = 0x00000006, - WGPUCompareFunction_GreaterEqual = 0x00000007, - WGPUCompareFunction_Always = 0x00000008, - WGPUCompareFunction_Force32 = 0x7FFFFFFF -} WGPUCompareFunction WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCompilationInfoRequestStatus { - WGPUCompilationInfoRequestStatus_Success = 0x00000001, - WGPUCompilationInfoRequestStatus_InstanceDropped = 0x00000002, - WGPUCompilationInfoRequestStatus_Error = 0x00000003, - WGPUCompilationInfoRequestStatus_DeviceLost = 0x00000004, - WGPUCompilationInfoRequestStatus_Unknown = 0x00000005, - WGPUCompilationInfoRequestStatus_Force32 = 0x7FFFFFFF -} WGPUCompilationInfoRequestStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCompilationMessageType { - WGPUCompilationMessageType_Error = 0x00000001, - WGPUCompilationMessageType_Warning = 0x00000002, - WGPUCompilationMessageType_Info = 0x00000003, - WGPUCompilationMessageType_Force32 = 0x7FFFFFFF -} WGPUCompilationMessageType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCompositeAlphaMode { - WGPUCompositeAlphaMode_Auto = 0x00000000, - WGPUCompositeAlphaMode_Opaque = 0x00000001, - WGPUCompositeAlphaMode_Premultiplied = 0x00000002, - WGPUCompositeAlphaMode_Unpremultiplied = 0x00000003, - WGPUCompositeAlphaMode_Inherit = 0x00000004, - WGPUCompositeAlphaMode_Force32 = 0x7FFFFFFF -} WGPUCompositeAlphaMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCreatePipelineAsyncStatus { - WGPUCreatePipelineAsyncStatus_Success = 0x00000001, - WGPUCreatePipelineAsyncStatus_InstanceDropped = 0x00000002, - WGPUCreatePipelineAsyncStatus_ValidationError = 0x00000003, - WGPUCreatePipelineAsyncStatus_InternalError = 0x00000004, - WGPUCreatePipelineAsyncStatus_DeviceLost = 0x00000005, - WGPUCreatePipelineAsyncStatus_DeviceDestroyed = 0x00000006, - WGPUCreatePipelineAsyncStatus_Unknown = 0x00000007, - WGPUCreatePipelineAsyncStatus_Force32 = 0x7FFFFFFF -} WGPUCreatePipelineAsyncStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUCullMode { - WGPUCullMode_Undefined = 0x00000000, - WGPUCullMode_None = 0x00000001, - WGPUCullMode_Front = 0x00000002, - WGPUCullMode_Back = 0x00000003, - WGPUCullMode_Force32 = 0x7FFFFFFF -} WGPUCullMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUDeviceLostReason { - WGPUDeviceLostReason_Unknown = 0x00000001, - WGPUDeviceLostReason_Destroyed = 0x00000002, - WGPUDeviceLostReason_InstanceDropped = 0x00000003, - WGPUDeviceLostReason_FailedCreation = 0x00000004, - WGPUDeviceLostReason_Force32 = 0x7FFFFFFF -} WGPUDeviceLostReason WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUErrorFilter { - WGPUErrorFilter_Validation = 0x00000001, - WGPUErrorFilter_OutOfMemory = 0x00000002, - WGPUErrorFilter_Internal = 0x00000003, - WGPUErrorFilter_Force32 = 0x7FFFFFFF -} WGPUErrorFilter WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUErrorType { - WGPUErrorType_NoError = 0x00000001, - WGPUErrorType_Validation = 0x00000002, - WGPUErrorType_OutOfMemory = 0x00000003, - WGPUErrorType_Internal = 0x00000004, - WGPUErrorType_Unknown = 0x00000005, - WGPUErrorType_DeviceLost = 0x00000006, - WGPUErrorType_Force32 = 0x7FFFFFFF -} WGPUErrorType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUExternalTextureRotation { - WGPUExternalTextureRotation_Rotate0Degrees = 0x00000001, - WGPUExternalTextureRotation_Rotate90Degrees = 0x00000002, - WGPUExternalTextureRotation_Rotate180Degrees = 0x00000003, - WGPUExternalTextureRotation_Rotate270Degrees = 0x00000004, - WGPUExternalTextureRotation_Force32 = 0x7FFFFFFF -} WGPUExternalTextureRotation WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUFeatureLevel { - WGPUFeatureLevel_Undefined = 0x00000000, - WGPUFeatureLevel_Compatibility = 0x00000001, - WGPUFeatureLevel_Core = 0x00000002, - WGPUFeatureLevel_Force32 = 0x7FFFFFFF -} WGPUFeatureLevel WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUFeatureName { - WGPUFeatureName_DepthClipControl = 0x00000001, - WGPUFeatureName_Depth32FloatStencil8 = 0x00000002, - WGPUFeatureName_TimestampQuery = 0x00000003, - WGPUFeatureName_TextureCompressionBC = 0x00000004, - WGPUFeatureName_TextureCompressionETC2 = 0x00000005, - WGPUFeatureName_TextureCompressionASTC = 0x00000006, - WGPUFeatureName_IndirectFirstInstance = 0x00000007, - WGPUFeatureName_ShaderF16 = 0x00000008, - WGPUFeatureName_RG11B10UfloatRenderable = 0x00000009, - WGPUFeatureName_BGRA8UnormStorage = 0x0000000A, - WGPUFeatureName_Float32Filterable = 0x0000000B, - WGPUFeatureName_Float32Blendable = 0x0000000C, - WGPUFeatureName_Subgroups = 0x0000000D, - WGPUFeatureName_SubgroupsF16 = 0x0000000E, - WGPUFeatureName_DawnInternalUsages = 0x00050000, - WGPUFeatureName_DawnMultiPlanarFormats = 0x00050001, - WGPUFeatureName_DawnNative = 0x00050002, - WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses = 0x00050003, - WGPUFeatureName_ImplicitDeviceSynchronization = 0x00050004, - WGPUFeatureName_ChromiumExperimentalImmediateData = 0x00050005, - WGPUFeatureName_TransientAttachments = 0x00050006, - WGPUFeatureName_MSAARenderToSingleSampled = 0x00050007, - WGPUFeatureName_DualSourceBlending = 0x00050008, - WGPUFeatureName_D3D11MultithreadProtected = 0x00050009, - WGPUFeatureName_ANGLETextureSharing = 0x0005000A, - WGPUFeatureName_PixelLocalStorageCoherent = 0x0005000B, - WGPUFeatureName_PixelLocalStorageNonCoherent = 0x0005000C, - WGPUFeatureName_Unorm16TextureFormats = 0x0005000D, - WGPUFeatureName_Snorm16TextureFormats = 0x0005000E, - WGPUFeatureName_MultiPlanarFormatExtendedUsages = 0x0005000F, - WGPUFeatureName_MultiPlanarFormatP010 = 0x00050010, - WGPUFeatureName_HostMappedPointer = 0x00050011, - WGPUFeatureName_MultiPlanarRenderTargets = 0x00050012, - WGPUFeatureName_MultiPlanarFormatNv12a = 0x00050013, - WGPUFeatureName_FramebufferFetch = 0x00050014, - WGPUFeatureName_BufferMapExtendedUsages = 0x00050015, - WGPUFeatureName_AdapterPropertiesMemoryHeaps = 0x00050016, - WGPUFeatureName_AdapterPropertiesD3D = 0x00050017, - WGPUFeatureName_AdapterPropertiesVk = 0x00050018, - WGPUFeatureName_R8UnormStorage = 0x00050019, - WGPUFeatureName_FormatCapabilities = 0x0005001A, - WGPUFeatureName_DrmFormatCapabilities = 0x0005001B, - WGPUFeatureName_Norm16TextureFormats = 0x0005001C, - WGPUFeatureName_MultiPlanarFormatNv16 = 0x0005001D, - WGPUFeatureName_MultiPlanarFormatNv24 = 0x0005001E, - WGPUFeatureName_MultiPlanarFormatP210 = 0x0005001F, - WGPUFeatureName_MultiPlanarFormatP410 = 0x00050020, - WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation = 0x00050021, - WGPUFeatureName_SharedTextureMemoryAHardwareBuffer = 0x00050022, - WGPUFeatureName_SharedTextureMemoryDmaBuf = 0x00050023, - WGPUFeatureName_SharedTextureMemoryOpaqueFD = 0x00050024, - WGPUFeatureName_SharedTextureMemoryZirconHandle = 0x00050025, - WGPUFeatureName_SharedTextureMemoryDXGISharedHandle = 0x00050026, - WGPUFeatureName_SharedTextureMemoryD3D11Texture2D = 0x00050027, - WGPUFeatureName_SharedTextureMemoryIOSurface = 0x00050028, - WGPUFeatureName_SharedTextureMemoryEGLImage = 0x00050029, - WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD = 0x0005002A, - WGPUFeatureName_SharedFenceSyncFD = 0x0005002B, - WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle = 0x0005002C, - WGPUFeatureName_SharedFenceDXGISharedHandle = 0x0005002D, - WGPUFeatureName_SharedFenceMTLSharedEvent = 0x0005002E, - WGPUFeatureName_SharedBufferMemoryD3D12Resource = 0x0005002F, - WGPUFeatureName_StaticSamplers = 0x00050030, - WGPUFeatureName_YCbCrVulkanSamplers = 0x00050031, - WGPUFeatureName_ShaderModuleCompilationOptions = 0x00050032, - WGPUFeatureName_DawnLoadResolveTexture = 0x00050033, - WGPUFeatureName_DawnPartialLoadResolveTexture = 0x00050034, - WGPUFeatureName_MultiDrawIndirect = 0x00050035, - WGPUFeatureName_ClipDistances = 0x00050036, - WGPUFeatureName_DawnTexelCopyBufferRowAlignment = 0x00050037, - WGPUFeatureName_FlexibleTextureViews = 0x00050038, - WGPUFeatureName_Force32 = 0x7FFFFFFF -} WGPUFeatureName WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUFilterMode { - WGPUFilterMode_Undefined = 0x00000000, - WGPUFilterMode_Nearest = 0x00000001, - WGPUFilterMode_Linear = 0x00000002, - WGPUFilterMode_Force32 = 0x7FFFFFFF -} WGPUFilterMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUFrontFace { - WGPUFrontFace_Undefined = 0x00000000, - WGPUFrontFace_CCW = 0x00000001, - WGPUFrontFace_CW = 0x00000002, - WGPUFrontFace_Force32 = 0x7FFFFFFF -} WGPUFrontFace WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUIndexFormat { - WGPUIndexFormat_Undefined = 0x00000000, - WGPUIndexFormat_Uint16 = 0x00000001, - WGPUIndexFormat_Uint32 = 0x00000002, - WGPUIndexFormat_Force32 = 0x7FFFFFFF -} WGPUIndexFormat WGPU_ENUM_ATTRIBUTE; -typedef enum WGPULoadOp { - WGPULoadOp_Undefined = 0x00000000, - WGPULoadOp_Load = 0x00000001, - WGPULoadOp_Clear = 0x00000002, - WGPULoadOp_ExpandResolveTexture = 0x00050003, - WGPULoadOp_Force32 = 0x7FFFFFFF -} WGPULoadOp WGPU_ENUM_ATTRIBUTE; -typedef enum WGPULoggingType { - WGPULoggingType_Verbose = 0x00000001, - WGPULoggingType_Info = 0x00000002, - WGPULoggingType_Warning = 0x00000003, - WGPULoggingType_Error = 0x00000004, - WGPULoggingType_Force32 = 0x7FFFFFFF -} WGPULoggingType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUMapAsyncStatus { - WGPUMapAsyncStatus_Success = 0x00000001, - WGPUMapAsyncStatus_InstanceDropped = 0x00000002, - WGPUMapAsyncStatus_Error = 0x00000003, - WGPUMapAsyncStatus_Aborted = 0x00000004, - WGPUMapAsyncStatus_Unknown = 0x00000005, - WGPUMapAsyncStatus_Force32 = 0x7FFFFFFF -} WGPUMapAsyncStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUMipmapFilterMode { - WGPUMipmapFilterMode_Undefined = 0x00000000, - WGPUMipmapFilterMode_Nearest = 0x00000001, - WGPUMipmapFilterMode_Linear = 0x00000002, - WGPUMipmapFilterMode_Force32 = 0x7FFFFFFF -} WGPUMipmapFilterMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUOptionalBool { - WGPUOptionalBool_False = 0x00000000, - WGPUOptionalBool_True = 0x00000001, - WGPUOptionalBool_Undefined = 0x00000002, - WGPUOptionalBool_Force32 = 0x7FFFFFFF -} WGPUOptionalBool WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUPopErrorScopeStatus { - WGPUPopErrorScopeStatus_Success = 0x00000001, - WGPUPopErrorScopeStatus_InstanceDropped = 0x00000002, - WGPUPopErrorScopeStatus_Force32 = 0x7FFFFFFF -} WGPUPopErrorScopeStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUPowerPreference { - WGPUPowerPreference_Undefined = 0x00000000, - WGPUPowerPreference_LowPower = 0x00000001, - WGPUPowerPreference_HighPerformance = 0x00000002, - WGPUPowerPreference_Force32 = 0x7FFFFFFF -} WGPUPowerPreference WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUPresentMode { - WGPUPresentMode_Fifo = 0x00000001, - WGPUPresentMode_FifoRelaxed = 0x00000002, - WGPUPresentMode_Immediate = 0x00000003, - WGPUPresentMode_Mailbox = 0x00000004, - WGPUPresentMode_Force32 = 0x7FFFFFFF -} WGPUPresentMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUPrimitiveTopology { - WGPUPrimitiveTopology_Undefined = 0x00000000, - WGPUPrimitiveTopology_PointList = 0x00000001, - WGPUPrimitiveTopology_LineList = 0x00000002, - WGPUPrimitiveTopology_LineStrip = 0x00000003, - WGPUPrimitiveTopology_TriangleList = 0x00000004, - WGPUPrimitiveTopology_TriangleStrip = 0x00000005, - WGPUPrimitiveTopology_Force32 = 0x7FFFFFFF -} WGPUPrimitiveTopology WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUQueryType { - WGPUQueryType_Occlusion = 0x00000001, - WGPUQueryType_Timestamp = 0x00000002, - WGPUQueryType_Force32 = 0x7FFFFFFF -} WGPUQueryType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUQueueWorkDoneStatus { - WGPUQueueWorkDoneStatus_Success = 0x00000001, - WGPUQueueWorkDoneStatus_InstanceDropped = 0x00000002, - WGPUQueueWorkDoneStatus_Error = 0x00000003, - WGPUQueueWorkDoneStatus_Unknown = 0x00000004, - WGPUQueueWorkDoneStatus_DeviceLost = 0x00000005, - WGPUQueueWorkDoneStatus_Force32 = 0x7FFFFFFF -} WGPUQueueWorkDoneStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPURequestAdapterStatus { - WGPURequestAdapterStatus_Success = 0x00000001, - WGPURequestAdapterStatus_InstanceDropped = 0x00000002, - WGPURequestAdapterStatus_Unavailable = 0x00000003, - WGPURequestAdapterStatus_Error = 0x00000004, - WGPURequestAdapterStatus_Unknown = 0x00000005, - WGPURequestAdapterStatus_Force32 = 0x7FFFFFFF -} WGPURequestAdapterStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPURequestDeviceStatus { - WGPURequestDeviceStatus_Success = 0x00000001, - WGPURequestDeviceStatus_InstanceDropped = 0x00000002, - WGPURequestDeviceStatus_Error = 0x00000003, - WGPURequestDeviceStatus_Unknown = 0x00000004, - WGPURequestDeviceStatus_Force32 = 0x7FFFFFFF -} WGPURequestDeviceStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUSType { - WGPUSType_ShaderSourceSPIRV = 0x00000001, - WGPUSType_ShaderSourceWGSL = 0x00000002, - WGPUSType_RenderPassMaxDrawCount = 0x00000003, - WGPUSType_SurfaceSourceMetalLayer = 0x00000004, - WGPUSType_SurfaceSourceWindowsHWND = 0x00000005, - WGPUSType_SurfaceSourceXlibWindow = 0x00000006, - WGPUSType_SurfaceSourceWaylandSurface = 0x00000007, - WGPUSType_SurfaceSourceAndroidNativeWindow = 0x00000008, - WGPUSType_SurfaceSourceXCBWindow = 0x00000009, - WGPUSType_AdapterPropertiesSubgroups = 0x0000000A, - WGPUSType_TextureBindingViewDimensionDescriptor = 0x00020000, - WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten = 0x00040000, - WGPUSType_SurfaceDescriptorFromWindowsCoreWindow = 0x00050000, - WGPUSType_ExternalTextureBindingEntry = 0x00050001, - WGPUSType_ExternalTextureBindingLayout = 0x00050002, - WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel = 0x00050003, - WGPUSType_DawnTextureInternalUsageDescriptor = 0x00050004, - WGPUSType_DawnEncoderInternalUsageDescriptor = 0x00050005, - WGPUSType_DawnInstanceDescriptor = 0x00050006, - WGPUSType_DawnCacheDeviceDescriptor = 0x00050007, - WGPUSType_DawnAdapterPropertiesPowerPreference = 0x00050008, - WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient = 0x00050009, - WGPUSType_DawnTogglesDescriptor = 0x0005000A, - WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor = 0x0005000B, - WGPUSType_RequestAdapterOptionsLUID = 0x0005000C, - WGPUSType_RequestAdapterOptionsGetGLProc = 0x0005000D, - WGPUSType_RequestAdapterOptionsD3D11Device = 0x0005000E, - WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled = 0x0005000F, - WGPUSType_RenderPassPixelLocalStorage = 0x00050010, - WGPUSType_PipelineLayoutPixelLocalStorage = 0x00050011, - WGPUSType_BufferHostMappedPointer = 0x00050012, - WGPUSType_DawnExperimentalSubgroupLimits = 0x00050013, - WGPUSType_AdapterPropertiesMemoryHeaps = 0x00050014, - WGPUSType_AdapterPropertiesD3D = 0x00050015, - WGPUSType_AdapterPropertiesVk = 0x00050016, - WGPUSType_DawnWireWGSLControl = 0x00050017, - WGPUSType_DawnWGSLBlocklist = 0x00050018, - WGPUSType_DrmFormatCapabilities = 0x00050019, - WGPUSType_ShaderModuleCompilationOptions = 0x0005001A, - WGPUSType_ColorTargetStateExpandResolveTextureDawn = 0x0005001B, - WGPUSType_RenderPassDescriptorExpandResolveRect = 0x0005001C, - WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor = 0x0005001D, - WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor = 0x0005001E, - WGPUSType_SharedTextureMemoryDmaBufDescriptor = 0x0005001F, - WGPUSType_SharedTextureMemoryOpaqueFDDescriptor = 0x00050020, - WGPUSType_SharedTextureMemoryZirconHandleDescriptor = 0x00050021, - WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor = 0x00050022, - WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor = 0x00050023, - WGPUSType_SharedTextureMemoryIOSurfaceDescriptor = 0x00050024, - WGPUSType_SharedTextureMemoryEGLImageDescriptor = 0x00050025, - WGPUSType_SharedTextureMemoryInitializedBeginState = 0x00050026, - WGPUSType_SharedTextureMemoryInitializedEndState = 0x00050027, - WGPUSType_SharedTextureMemoryVkImageLayoutBeginState = 0x00050028, - WGPUSType_SharedTextureMemoryVkImageLayoutEndState = 0x00050029, - WGPUSType_SharedTextureMemoryD3DSwapchainBeginState = 0x0005002A, - WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor = 0x0005002B, - WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo = 0x0005002C, - WGPUSType_SharedFenceSyncFDDescriptor = 0x0005002D, - WGPUSType_SharedFenceSyncFDExportInfo = 0x0005002E, - WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor = 0x0005002F, - WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo = 0x00050030, - WGPUSType_SharedFenceDXGISharedHandleDescriptor = 0x00050031, - WGPUSType_SharedFenceDXGISharedHandleExportInfo = 0x00050032, - WGPUSType_SharedFenceMTLSharedEventDescriptor = 0x00050033, - WGPUSType_SharedFenceMTLSharedEventExportInfo = 0x00050034, - WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor = 0x00050035, - WGPUSType_StaticSamplerBindingLayout = 0x00050036, - WGPUSType_YCbCrVkDescriptor = 0x00050037, - WGPUSType_SharedTextureMemoryAHardwareBufferProperties = 0x00050038, - WGPUSType_AHardwareBufferProperties = 0x00050039, - WGPUSType_DawnExperimentalImmediateDataLimits = 0x0005003A, - WGPUSType_DawnTexelCopyBufferRowAlignmentLimits = 0x0005003B, - WGPUSType_Force32 = 0x7FFFFFFF -} WGPUSType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUSamplerBindingType { - WGPUSamplerBindingType_BindingNotUsed = 0x00000000, - WGPUSamplerBindingType_Filtering = 0x00000001, - WGPUSamplerBindingType_NonFiltering = 0x00000002, - WGPUSamplerBindingType_Comparison = 0x00000003, - WGPUSamplerBindingType_Force32 = 0x7FFFFFFF -} WGPUSamplerBindingType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUSharedFenceType { - WGPUSharedFenceType_VkSemaphoreOpaqueFD = 0x00000001, - WGPUSharedFenceType_SyncFD = 0x00000002, - WGPUSharedFenceType_VkSemaphoreZirconHandle = 0x00000003, - WGPUSharedFenceType_DXGISharedHandle = 0x00000004, - WGPUSharedFenceType_MTLSharedEvent = 0x00000005, - WGPUSharedFenceType_Force32 = 0x7FFFFFFF -} WGPUSharedFenceType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUStatus { - WGPUStatus_Success = 0x00000001, - WGPUStatus_Error = 0x00000002, - WGPUStatus_Force32 = 0x7FFFFFFF -} WGPUStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUStencilOperation { - WGPUStencilOperation_Undefined = 0x00000000, - WGPUStencilOperation_Keep = 0x00000001, - WGPUStencilOperation_Zero = 0x00000002, - WGPUStencilOperation_Replace = 0x00000003, - WGPUStencilOperation_Invert = 0x00000004, - WGPUStencilOperation_IncrementClamp = 0x00000005, - WGPUStencilOperation_DecrementClamp = 0x00000006, - WGPUStencilOperation_IncrementWrap = 0x00000007, - WGPUStencilOperation_DecrementWrap = 0x00000008, - WGPUStencilOperation_Force32 = 0x7FFFFFFF -} WGPUStencilOperation WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUStorageTextureAccess { - WGPUStorageTextureAccess_BindingNotUsed = 0x00000000, - WGPUStorageTextureAccess_WriteOnly = 0x00000001, - WGPUStorageTextureAccess_ReadOnly = 0x00000002, - WGPUStorageTextureAccess_ReadWrite = 0x00000003, - WGPUStorageTextureAccess_Force32 = 0x7FFFFFFF -} WGPUStorageTextureAccess WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUStoreOp { - WGPUStoreOp_Undefined = 0x00000000, - WGPUStoreOp_Store = 0x00000001, - WGPUStoreOp_Discard = 0x00000002, - WGPUStoreOp_Force32 = 0x7FFFFFFF -} WGPUStoreOp WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUSurfaceGetCurrentTextureStatus { - WGPUSurfaceGetCurrentTextureStatus_Success = 0x00000001, - WGPUSurfaceGetCurrentTextureStatus_Timeout = 0x00000002, - WGPUSurfaceGetCurrentTextureStatus_Outdated = 0x00000003, - WGPUSurfaceGetCurrentTextureStatus_Lost = 0x00000004, - WGPUSurfaceGetCurrentTextureStatus_OutOfMemory = 0x00000005, - WGPUSurfaceGetCurrentTextureStatus_DeviceLost = 0x00000006, - WGPUSurfaceGetCurrentTextureStatus_Error = 0x00000007, - WGPUSurfaceGetCurrentTextureStatus_Force32 = 0x7FFFFFFF -} WGPUSurfaceGetCurrentTextureStatus WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUTextureAspect { - WGPUTextureAspect_Undefined = 0x00000000, - WGPUTextureAspect_All = 0x00000001, - WGPUTextureAspect_StencilOnly = 0x00000002, - WGPUTextureAspect_DepthOnly = 0x00000003, - WGPUTextureAspect_Plane0Only = 0x00050000, - WGPUTextureAspect_Plane1Only = 0x00050001, - WGPUTextureAspect_Plane2Only = 0x00050002, - WGPUTextureAspect_Force32 = 0x7FFFFFFF -} WGPUTextureAspect WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUTextureDimension { - WGPUTextureDimension_Undefined = 0x00000000, - WGPUTextureDimension_1D = 0x00000001, - WGPUTextureDimension_2D = 0x00000002, - WGPUTextureDimension_3D = 0x00000003, - WGPUTextureDimension_Force32 = 0x7FFFFFFF -} WGPUTextureDimension WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUTextureFormat { - WGPUTextureFormat_Undefined = 0x00000000, - WGPUTextureFormat_R8Unorm = 0x00000001, - WGPUTextureFormat_R8Snorm = 0x00000002, - WGPUTextureFormat_R8Uint = 0x00000003, - WGPUTextureFormat_R8Sint = 0x00000004, - WGPUTextureFormat_R16Uint = 0x00000005, - WGPUTextureFormat_R16Sint = 0x00000006, - WGPUTextureFormat_R16Float = 0x00000007, - WGPUTextureFormat_RG8Unorm = 0x00000008, - WGPUTextureFormat_RG8Snorm = 0x00000009, - WGPUTextureFormat_RG8Uint = 0x0000000A, - WGPUTextureFormat_RG8Sint = 0x0000000B, - WGPUTextureFormat_R32Float = 0x0000000C, - WGPUTextureFormat_R32Uint = 0x0000000D, - WGPUTextureFormat_R32Sint = 0x0000000E, - WGPUTextureFormat_RG16Uint = 0x0000000F, - WGPUTextureFormat_RG16Sint = 0x00000010, - WGPUTextureFormat_RG16Float = 0x00000011, - WGPUTextureFormat_RGBA8Unorm = 0x00000012, - WGPUTextureFormat_RGBA8UnormSrgb = 0x00000013, - WGPUTextureFormat_RGBA8Snorm = 0x00000014, - WGPUTextureFormat_RGBA8Uint = 0x00000015, - WGPUTextureFormat_RGBA8Sint = 0x00000016, - WGPUTextureFormat_BGRA8Unorm = 0x00000017, - WGPUTextureFormat_BGRA8UnormSrgb = 0x00000018, - WGPUTextureFormat_RGB10A2Uint = 0x00000019, - WGPUTextureFormat_RGB10A2Unorm = 0x0000001A, - WGPUTextureFormat_RG11B10Ufloat = 0x0000001B, - WGPUTextureFormat_RGB9E5Ufloat = 0x0000001C, - WGPUTextureFormat_RG32Float = 0x0000001D, - WGPUTextureFormat_RG32Uint = 0x0000001E, - WGPUTextureFormat_RG32Sint = 0x0000001F, - WGPUTextureFormat_RGBA16Uint = 0x00000020, - WGPUTextureFormat_RGBA16Sint = 0x00000021, - WGPUTextureFormat_RGBA16Float = 0x00000022, - WGPUTextureFormat_RGBA32Float = 0x00000023, - WGPUTextureFormat_RGBA32Uint = 0x00000024, - WGPUTextureFormat_RGBA32Sint = 0x00000025, - WGPUTextureFormat_Stencil8 = 0x00000026, - WGPUTextureFormat_Depth16Unorm = 0x00000027, - WGPUTextureFormat_Depth24Plus = 0x00000028, - WGPUTextureFormat_Depth24PlusStencil8 = 0x00000029, - WGPUTextureFormat_Depth32Float = 0x0000002A, - WGPUTextureFormat_Depth32FloatStencil8 = 0x0000002B, - WGPUTextureFormat_BC1RGBAUnorm = 0x0000002C, - WGPUTextureFormat_BC1RGBAUnormSrgb = 0x0000002D, - WGPUTextureFormat_BC2RGBAUnorm = 0x0000002E, - WGPUTextureFormat_BC2RGBAUnormSrgb = 0x0000002F, - WGPUTextureFormat_BC3RGBAUnorm = 0x00000030, - WGPUTextureFormat_BC3RGBAUnormSrgb = 0x00000031, - WGPUTextureFormat_BC4RUnorm = 0x00000032, - WGPUTextureFormat_BC4RSnorm = 0x00000033, - WGPUTextureFormat_BC5RGUnorm = 0x00000034, - WGPUTextureFormat_BC5RGSnorm = 0x00000035, - WGPUTextureFormat_BC6HRGBUfloat = 0x00000036, - WGPUTextureFormat_BC6HRGBFloat = 0x00000037, - WGPUTextureFormat_BC7RGBAUnorm = 0x00000038, - WGPUTextureFormat_BC7RGBAUnormSrgb = 0x00000039, - WGPUTextureFormat_ETC2RGB8Unorm = 0x0000003A, - WGPUTextureFormat_ETC2RGB8UnormSrgb = 0x0000003B, - WGPUTextureFormat_ETC2RGB8A1Unorm = 0x0000003C, - WGPUTextureFormat_ETC2RGB8A1UnormSrgb = 0x0000003D, - WGPUTextureFormat_ETC2RGBA8Unorm = 0x0000003E, - WGPUTextureFormat_ETC2RGBA8UnormSrgb = 0x0000003F, - WGPUTextureFormat_EACR11Unorm = 0x00000040, - WGPUTextureFormat_EACR11Snorm = 0x00000041, - WGPUTextureFormat_EACRG11Unorm = 0x00000042, - WGPUTextureFormat_EACRG11Snorm = 0x00000043, - WGPUTextureFormat_ASTC4x4Unorm = 0x00000044, - WGPUTextureFormat_ASTC4x4UnormSrgb = 0x00000045, - WGPUTextureFormat_ASTC5x4Unorm = 0x00000046, - WGPUTextureFormat_ASTC5x4UnormSrgb = 0x00000047, - WGPUTextureFormat_ASTC5x5Unorm = 0x00000048, - WGPUTextureFormat_ASTC5x5UnormSrgb = 0x00000049, - WGPUTextureFormat_ASTC6x5Unorm = 0x0000004A, - WGPUTextureFormat_ASTC6x5UnormSrgb = 0x0000004B, - WGPUTextureFormat_ASTC6x6Unorm = 0x0000004C, - WGPUTextureFormat_ASTC6x6UnormSrgb = 0x0000004D, - WGPUTextureFormat_ASTC8x5Unorm = 0x0000004E, - WGPUTextureFormat_ASTC8x5UnormSrgb = 0x0000004F, - WGPUTextureFormat_ASTC8x6Unorm = 0x00000050, - WGPUTextureFormat_ASTC8x6UnormSrgb = 0x00000051, - WGPUTextureFormat_ASTC8x8Unorm = 0x00000052, - WGPUTextureFormat_ASTC8x8UnormSrgb = 0x00000053, - WGPUTextureFormat_ASTC10x5Unorm = 0x00000054, - WGPUTextureFormat_ASTC10x5UnormSrgb = 0x00000055, - WGPUTextureFormat_ASTC10x6Unorm = 0x00000056, - WGPUTextureFormat_ASTC10x6UnormSrgb = 0x00000057, - WGPUTextureFormat_ASTC10x8Unorm = 0x00000058, - WGPUTextureFormat_ASTC10x8UnormSrgb = 0x00000059, - WGPUTextureFormat_ASTC10x10Unorm = 0x0000005A, - WGPUTextureFormat_ASTC10x10UnormSrgb = 0x0000005B, - WGPUTextureFormat_ASTC12x10Unorm = 0x0000005C, - WGPUTextureFormat_ASTC12x10UnormSrgb = 0x0000005D, - WGPUTextureFormat_ASTC12x12Unorm = 0x0000005E, - WGPUTextureFormat_ASTC12x12UnormSrgb = 0x0000005F, - WGPUTextureFormat_R16Unorm = 0x00050000, - WGPUTextureFormat_RG16Unorm = 0x00050001, - WGPUTextureFormat_RGBA16Unorm = 0x00050002, - WGPUTextureFormat_R16Snorm = 0x00050003, - WGPUTextureFormat_RG16Snorm = 0x00050004, - WGPUTextureFormat_RGBA16Snorm = 0x00050005, - WGPUTextureFormat_R8BG8Biplanar420Unorm = 0x00050006, - WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm = 0x00050007, - WGPUTextureFormat_R8BG8A8Triplanar420Unorm = 0x00050008, - WGPUTextureFormat_R8BG8Biplanar422Unorm = 0x00050009, - WGPUTextureFormat_R8BG8Biplanar444Unorm = 0x0005000A, - WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm = 0x0005000B, - WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm = 0x0005000C, - WGPUTextureFormat_External = 0x0005000D, - WGPUTextureFormat_Force32 = 0x7FFFFFFF -} WGPUTextureFormat WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUTextureSampleType { - WGPUTextureSampleType_BindingNotUsed = 0x00000000, - WGPUTextureSampleType_Float = 0x00000001, - WGPUTextureSampleType_UnfilterableFloat = 0x00000002, - WGPUTextureSampleType_Depth = 0x00000003, - WGPUTextureSampleType_Sint = 0x00000004, - WGPUTextureSampleType_Uint = 0x00000005, - WGPUTextureSampleType_Force32 = 0x7FFFFFFF -} WGPUTextureSampleType WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUTextureViewDimension { - WGPUTextureViewDimension_Undefined = 0x00000000, - WGPUTextureViewDimension_1D = 0x00000001, - WGPUTextureViewDimension_2D = 0x00000002, - WGPUTextureViewDimension_2DArray = 0x00000003, - WGPUTextureViewDimension_Cube = 0x00000004, - WGPUTextureViewDimension_CubeArray = 0x00000005, - WGPUTextureViewDimension_3D = 0x00000006, - WGPUTextureViewDimension_Force32 = 0x7FFFFFFF -} WGPUTextureViewDimension WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUVertexFormat { - WGPUVertexFormat_Uint8 = 0x00000001, - WGPUVertexFormat_Uint8x2 = 0x00000002, - WGPUVertexFormat_Uint8x4 = 0x00000003, - WGPUVertexFormat_Sint8 = 0x00000004, - WGPUVertexFormat_Sint8x2 = 0x00000005, - WGPUVertexFormat_Sint8x4 = 0x00000006, - WGPUVertexFormat_Unorm8 = 0x00000007, - WGPUVertexFormat_Unorm8x2 = 0x00000008, - WGPUVertexFormat_Unorm8x4 = 0x00000009, - WGPUVertexFormat_Snorm8 = 0x0000000A, - WGPUVertexFormat_Snorm8x2 = 0x0000000B, - WGPUVertexFormat_Snorm8x4 = 0x0000000C, - WGPUVertexFormat_Uint16 = 0x0000000D, - WGPUVertexFormat_Uint16x2 = 0x0000000E, - WGPUVertexFormat_Uint16x4 = 0x0000000F, - WGPUVertexFormat_Sint16 = 0x00000010, - WGPUVertexFormat_Sint16x2 = 0x00000011, - WGPUVertexFormat_Sint16x4 = 0x00000012, - WGPUVertexFormat_Unorm16 = 0x00000013, - WGPUVertexFormat_Unorm16x2 = 0x00000014, - WGPUVertexFormat_Unorm16x4 = 0x00000015, - WGPUVertexFormat_Snorm16 = 0x00000016, - WGPUVertexFormat_Snorm16x2 = 0x00000017, - WGPUVertexFormat_Snorm16x4 = 0x00000018, - WGPUVertexFormat_Float16 = 0x00000019, - WGPUVertexFormat_Float16x2 = 0x0000001A, - WGPUVertexFormat_Float16x4 = 0x0000001B, - WGPUVertexFormat_Float32 = 0x0000001C, - WGPUVertexFormat_Float32x2 = 0x0000001D, - WGPUVertexFormat_Float32x3 = 0x0000001E, - WGPUVertexFormat_Float32x4 = 0x0000001F, - WGPUVertexFormat_Uint32 = 0x00000020, - WGPUVertexFormat_Uint32x2 = 0x00000021, - WGPUVertexFormat_Uint32x3 = 0x00000022, - WGPUVertexFormat_Uint32x4 = 0x00000023, - WGPUVertexFormat_Sint32 = 0x00000024, - WGPUVertexFormat_Sint32x2 = 0x00000025, - WGPUVertexFormat_Sint32x3 = 0x00000026, - WGPUVertexFormat_Sint32x4 = 0x00000027, - WGPUVertexFormat_Unorm10_10_10_2 = 0x00000028, - WGPUVertexFormat_Unorm8x4BGRA = 0x00000029, - WGPUVertexFormat_Force32 = 0x7FFFFFFF -} WGPUVertexFormat WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUVertexStepMode { - WGPUVertexStepMode_Undefined = 0x00000000, - WGPUVertexStepMode_Vertex = 0x00000001, - WGPUVertexStepMode_Instance = 0x00000002, - WGPUVertexStepMode_Force32 = 0x7FFFFFFF -} WGPUVertexStepMode WGPU_ENUM_ATTRIBUTE; -typedef enum WGPUWaitStatus { - WGPUWaitStatus_Success = 0x00000001, - WGPUWaitStatus_TimedOut = 0x00000002, - WGPUWaitStatus_UnsupportedTimeout = 0x00000003, - WGPUWaitStatus_UnsupportedCount = 0x00000004, - WGPUWaitStatus_UnsupportedMixedSources = 0x00000005, - WGPUWaitStatus_Unknown = 0x00000006, - WGPUWaitStatus_Force32 = 0x7FFFFFFF -} WGPUWaitStatus WGPU_ENUM_ATTRIBUTE; - -typedef WGPUFlags WGPUBufferUsage; -static const WGPUBufferUsage WGPUBufferUsage_None = 0x0000000000000000; -static const WGPUBufferUsage WGPUBufferUsage_MapRead = 0x0000000000000001; -static const WGPUBufferUsage WGPUBufferUsage_MapWrite = 0x0000000000000002; -static const WGPUBufferUsage WGPUBufferUsage_CopySrc = 0x0000000000000004; -static const WGPUBufferUsage WGPUBufferUsage_CopyDst = 0x0000000000000008; -static const WGPUBufferUsage WGPUBufferUsage_Index = 0x0000000000000010; -static const WGPUBufferUsage WGPUBufferUsage_Vertex = 0x0000000000000020; -static const WGPUBufferUsage WGPUBufferUsage_Uniform = 0x0000000000000040; -static const WGPUBufferUsage WGPUBufferUsage_Storage = 0x0000000000000080; -static const WGPUBufferUsage WGPUBufferUsage_Indirect = 0x0000000000000100; -static const WGPUBufferUsage WGPUBufferUsage_QueryResolve = 0x0000000000000200; -typedef WGPUFlags WGPUColorWriteMask; -static const WGPUColorWriteMask WGPUColorWriteMask_None = 0x0000000000000000; -static const WGPUColorWriteMask WGPUColorWriteMask_Red = 0x0000000000000001; -static const WGPUColorWriteMask WGPUColorWriteMask_Green = 0x0000000000000002; -static const WGPUColorWriteMask WGPUColorWriteMask_Blue = 0x0000000000000004; -static const WGPUColorWriteMask WGPUColorWriteMask_Alpha = 0x0000000000000008; -static const WGPUColorWriteMask WGPUColorWriteMask_All = 0x000000000000000F; -typedef WGPUFlags WGPUHeapProperty; -static const WGPUHeapProperty WGPUHeapProperty_DeviceLocal = 0x0000000000000001; -static const WGPUHeapProperty WGPUHeapProperty_HostVisible = 0x0000000000000002; -static const WGPUHeapProperty WGPUHeapProperty_HostCoherent = 0x0000000000000004; -static const WGPUHeapProperty WGPUHeapProperty_HostUncached = 0x0000000000000008; -static const WGPUHeapProperty WGPUHeapProperty_HostCached = 0x0000000000000010; -typedef WGPUFlags WGPUMapMode; -static const WGPUMapMode WGPUMapMode_None = 0x0000000000000000; -static const WGPUMapMode WGPUMapMode_Read = 0x0000000000000001; -static const WGPUMapMode WGPUMapMode_Write = 0x0000000000000002; -typedef WGPUFlags WGPUShaderStage; -static const WGPUShaderStage WGPUShaderStage_None = 0x0000000000000000; -static const WGPUShaderStage WGPUShaderStage_Vertex = 0x0000000000000001; -static const WGPUShaderStage WGPUShaderStage_Fragment = 0x0000000000000002; -static const WGPUShaderStage WGPUShaderStage_Compute = 0x0000000000000004; -typedef WGPUFlags WGPUTextureUsage; -static const WGPUTextureUsage WGPUTextureUsage_None = 0x0000000000000000; -static const WGPUTextureUsage WGPUTextureUsage_CopySrc = 0x0000000000000001; -static const WGPUTextureUsage WGPUTextureUsage_CopyDst = 0x0000000000000002; -static const WGPUTextureUsage WGPUTextureUsage_TextureBinding = 0x0000000000000004; -static const WGPUTextureUsage WGPUTextureUsage_StorageBinding = 0x0000000000000008; -static const WGPUTextureUsage WGPUTextureUsage_RenderAttachment = 0x0000000000000010; -static const WGPUTextureUsage WGPUTextureUsage_TransientAttachment = 0x0000000000000020; -static const WGPUTextureUsage WGPUTextureUsage_StorageAttachment = 0x0000000000000040; -typedef void (*WGPUBufferMapCallback)(WGPUBufferMapAsyncStatus status, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCallback)(void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCompilationInfoCallback)(WGPUCompilationInfoRequestStatus status, struct WGPUCompilationInfo const * compilationInfo, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCreateComputePipelineAsyncCallback)(WGPUCreatePipelineAsyncStatus status, WGPUComputePipeline pipeline, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCreateRenderPipelineAsyncCallback)(WGPUCreatePipelineAsyncStatus status, WGPURenderPipeline pipeline, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef size_t (*WGPUDawnLoadCacheDataFunction)(void const * key, size_t keySize, void * value, size_t valueSize, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUDawnStoreCacheDataFunction)(void const * key, size_t keySize, void const * value, size_t valueSize, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUDeviceLostCallback)(WGPUDeviceLostReason reason, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUDeviceLostCallbackNew)(WGPUDevice const * device, WGPUDeviceLostReason reason, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUErrorCallback)(WGPUErrorType type, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPULoggingCallback)(WGPULoggingType type, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUPopErrorScopeCallback)(WGPUPopErrorScopeStatus status, WGPUErrorType type, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProc)(void) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUQueueWorkDoneCallback)(WGPUQueueWorkDoneStatus status, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPURequestAdapterCallback)(WGPURequestAdapterStatus status, WGPUAdapter adapter, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPURequestDeviceCallback)(WGPURequestDeviceStatus status, WGPUDevice device, struct WGPUStringView message, void * userdata) WGPU_FUNCTION_ATTRIBUTE; - -// Callback function pointers -typedef void (*WGPUBufferMapCallback2)(WGPUMapAsyncStatus status, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCompilationInfoCallback2)(WGPUCompilationInfoRequestStatus status, struct WGPUCompilationInfo const * compilationInfo, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCreateComputePipelineAsyncCallback2)(WGPUCreatePipelineAsyncStatus status, WGPUComputePipeline pipeline, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUCreateRenderPipelineAsyncCallback2)(WGPUCreatePipelineAsyncStatus status, WGPURenderPipeline pipeline, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUDeviceLostCallback2)(WGPUDevice const * device, WGPUDeviceLostReason reason, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUPopErrorScopeCallback2)(WGPUPopErrorScopeStatus status, WGPUErrorType type, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUQueueWorkDoneCallback2)(WGPUQueueWorkDoneStatus status, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPURequestAdapterCallback2)(WGPURequestAdapterStatus status, WGPUAdapter adapter, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPURequestDeviceCallback2)(WGPURequestDeviceStatus status, WGPUDevice device, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUUncapturedErrorCallback)(WGPUDevice const * device, WGPUErrorType type, struct WGPUStringView message, void* userdata1, void* userdata2) WGPU_FUNCTION_ATTRIBUTE; - -typedef struct WGPUChainedStruct { - struct WGPUChainedStruct const * next; - WGPUSType sType; -} WGPUChainedStruct WGPU_STRUCTURE_ATTRIBUTE; - -typedef struct WGPUChainedStructOut { - struct WGPUChainedStructOut * next; - WGPUSType sType; -} WGPUChainedStructOut WGPU_STRUCTURE_ATTRIBUTE; - - -#define WGPU_COMMA , - -typedef struct WGPUBufferMapCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUBufferMapCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUBufferMapCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BUFFER_MAP_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUBufferMapCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUCompilationInfoCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUCompilationInfoCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUCompilationInfoCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPILATION_INFO_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUCompilationInfoCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUCreateComputePipelineAsyncCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUCreateComputePipelineAsyncCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUCreateComputePipelineAsyncCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_CREATE_COMPUTE_PIPELINE_ASYNC_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUCreateComputePipelineAsyncCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUCreateRenderPipelineAsyncCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUCreateRenderPipelineAsyncCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUCreateRenderPipelineAsyncCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_CREATE_RENDER_PIPELINE_ASYNC_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUCreateRenderPipelineAsyncCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUDeviceLostCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUDeviceLostCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUDeviceLostCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DEVICE_LOST_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUDeviceLostCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUPopErrorScopeCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUPopErrorScopeCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUPopErrorScopeCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_POP_ERROR_SCOPE_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUPopErrorScopeCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUQueueWorkDoneCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPUQueueWorkDoneCallback2 callback; - void* userdata1; - void* userdata2; -} WGPUQueueWorkDoneCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_QUEUE_WORK_DONE_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUQueueWorkDoneCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPURequestAdapterCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPURequestAdapterCallback2 callback; - void* userdata1; - void* userdata2; -} WGPURequestAdapterCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUEST_ADAPTER_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPURequestAdapterCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPURequestDeviceCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUCallbackMode mode; - WGPURequestDeviceCallback2 callback; - void* userdata1; - void* userdata2; -} WGPURequestDeviceCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUEST_DEVICE_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPURequestDeviceCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUUncapturedErrorCallbackInfo2 { - WGPUChainedStruct const* nextInChain; - WGPUUncapturedErrorCallback callback; - void* userdata1; - void* userdata2; -} WGPUUncapturedErrorCallbackInfo2 WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_UNCAPTURED_ERROR_CALLBACK_INFO_2_INIT WGPU_MAKE_INIT_STRUCT(WGPUUncapturedErrorCallbackInfo2, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata1=*/nullptr WGPU_COMMA \ - /*.userdata2=*/nullptr WGPU_COMMA \ -}) - - -typedef struct WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER { - WGPUBool unused; -} WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_INTERNAL__HAVE_EMDAWNWEBGPU_HEADER_INIT WGPU_MAKE_INIT_STRUCT(WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER, { \ - /*.unused=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUAdapterInfo -typedef struct WGPUAdapterPropertiesD3D { - WGPUChainedStructOut chain; - uint32_t shaderModel; -} WGPUAdapterPropertiesD3D WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ADAPTER_PROPERTIES_D3D_INIT WGPU_MAKE_INIT_STRUCT(WGPUAdapterPropertiesD3D, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_AdapterPropertiesD3D} WGPU_COMMA \ - /*.shaderModel=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUAdapterInfo -typedef struct WGPUAdapterPropertiesSubgroups { - WGPUChainedStructOut chain; - uint32_t subgroupMinSize; - uint32_t subgroupMaxSize; -} WGPUAdapterPropertiesSubgroups WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ADAPTER_PROPERTIES_SUBGROUPS_INIT WGPU_MAKE_INIT_STRUCT(WGPUAdapterPropertiesSubgroups, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_AdapterPropertiesSubgroups} WGPU_COMMA \ - /*.subgroupMinSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.subgroupMaxSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -// Can be chained in WGPUAdapterInfo -typedef struct WGPUAdapterPropertiesVk { - WGPUChainedStructOut chain; - uint32_t driverVersion; -} WGPUAdapterPropertiesVk WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ADAPTER_PROPERTIES_VK_INIT WGPU_MAKE_INIT_STRUCT(WGPUAdapterPropertiesVk, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_AdapterPropertiesVk} WGPU_COMMA \ - /*.driverVersion=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUBindGroupEntry { - WGPUChainedStruct const * nextInChain; - uint32_t binding; - WGPU_NULLABLE WGPUBuffer buffer; - uint64_t offset; - uint64_t size; - WGPU_NULLABLE WGPUSampler sampler; - WGPU_NULLABLE WGPUTextureView textureView; -} WGPUBindGroupEntry WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BIND_GROUP_ENTRY_INIT WGPU_MAKE_INIT_STRUCT(WGPUBindGroupEntry, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.binding=*/{} WGPU_COMMA \ - /*.buffer=*/nullptr WGPU_COMMA \ - /*.offset=*/0 WGPU_COMMA \ - /*.size=*/WGPU_WHOLE_SIZE WGPU_COMMA \ - /*.sampler=*/nullptr WGPU_COMMA \ - /*.textureView=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUBlendComponent { - WGPUBlendOperation operation; - WGPUBlendFactor srcFactor; - WGPUBlendFactor dstFactor; -} WGPUBlendComponent WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BLEND_COMPONENT_INIT WGPU_MAKE_INIT_STRUCT(WGPUBlendComponent, { \ - /*.operation=*/WGPUBlendOperation_Add WGPU_COMMA \ - /*.srcFactor=*/WGPUBlendFactor_One WGPU_COMMA \ - /*.dstFactor=*/WGPUBlendFactor_Zero WGPU_COMMA \ -}) - -typedef struct WGPUBufferBindingLayout { - WGPUChainedStruct const * nextInChain; - WGPUBufferBindingType type; - WGPUBool hasDynamicOffset; - uint64_t minBindingSize; -} WGPUBufferBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BUFFER_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUBufferBindingLayout, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.type=*/WGPUBufferBindingType_BindingNotUsed WGPU_COMMA \ - /*.hasDynamicOffset=*/false WGPU_COMMA \ - /*.minBindingSize=*/0 WGPU_COMMA \ -}) - -// Can be chained in WGPUBufferDescriptor -typedef struct WGPUBufferHostMappedPointer { - WGPUChainedStruct chain; - void * pointer; - WGPUCallback disposeCallback; - void * userdata; -} WGPUBufferHostMappedPointer WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BUFFER_HOST_MAPPED_POINTER_INIT WGPU_MAKE_INIT_STRUCT(WGPUBufferHostMappedPointer, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_BufferHostMappedPointer} WGPU_COMMA \ - /*.pointer=*/{} WGPU_COMMA \ - /*.disposeCallback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUBufferMapCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUBufferMapCallback callback; - void * userdata; -} WGPUBufferMapCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BUFFER_MAP_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUBufferMapCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUColor { - double r; - double g; - double b; - double a; -} WGPUColor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COLOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUColor, { \ - /*.r=*/{} WGPU_COMMA \ - /*.g=*/{} WGPU_COMMA \ - /*.b=*/{} WGPU_COMMA \ - /*.a=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUColorTargetState -typedef struct WGPUColorTargetStateExpandResolveTextureDawn { - WGPUChainedStruct chain; - WGPUBool enabled; -} WGPUColorTargetStateExpandResolveTextureDawn WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COLOR_TARGET_STATE_EXPAND_RESOLVE_TEXTURE_DAWN_INIT WGPU_MAKE_INIT_STRUCT(WGPUColorTargetStateExpandResolveTextureDawn, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ColorTargetStateExpandResolveTextureDawn} WGPU_COMMA \ - /*.enabled=*/false WGPU_COMMA \ -}) - -typedef struct WGPUCompilationInfoCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUCompilationInfoCallback callback; - void * userdata; -} WGPUCompilationInfoCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPILATION_INFO_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUCompilationInfoCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUComputePassTimestampWrites { - WGPUQuerySet querySet; - uint32_t beginningOfPassWriteIndex; - uint32_t endOfPassWriteIndex; -} WGPUComputePassTimestampWrites WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPUTE_PASS_TIMESTAMP_WRITES_INIT WGPU_MAKE_INIT_STRUCT(WGPUComputePassTimestampWrites, { \ - /*.querySet=*/{} WGPU_COMMA \ - /*.beginningOfPassWriteIndex=*/WGPU_QUERY_SET_INDEX_UNDEFINED WGPU_COMMA \ - /*.endOfPassWriteIndex=*/WGPU_QUERY_SET_INDEX_UNDEFINED WGPU_COMMA \ -}) - -typedef struct WGPUCopyTextureForBrowserOptions { - WGPUChainedStruct const * nextInChain; - WGPUBool flipY; - WGPUBool needsColorSpaceConversion; - WGPUAlphaMode srcAlphaMode; - WGPU_NULLABLE float const * srcTransferFunctionParameters; - WGPU_NULLABLE float const * conversionMatrix; - WGPU_NULLABLE float const * dstTransferFunctionParameters; - WGPUAlphaMode dstAlphaMode; - WGPUBool internalUsage; -} WGPUCopyTextureForBrowserOptions WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COPY_TEXTURE_FOR_BROWSER_OPTIONS_INIT WGPU_MAKE_INIT_STRUCT(WGPUCopyTextureForBrowserOptions, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.flipY=*/false WGPU_COMMA \ - /*.needsColorSpaceConversion=*/false WGPU_COMMA \ - /*.srcAlphaMode=*/WGPUAlphaMode_Unpremultiplied WGPU_COMMA \ - /*.srcTransferFunctionParameters=*/nullptr WGPU_COMMA \ - /*.conversionMatrix=*/nullptr WGPU_COMMA \ - /*.dstTransferFunctionParameters=*/nullptr WGPU_COMMA \ - /*.dstAlphaMode=*/WGPUAlphaMode_Unpremultiplied WGPU_COMMA \ - /*.internalUsage=*/false WGPU_COMMA \ -}) - -typedef struct WGPUCreateComputePipelineAsyncCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUCreateComputePipelineAsyncCallback callback; - void * userdata; -} WGPUCreateComputePipelineAsyncCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_CREATE_COMPUTE_PIPELINE_ASYNC_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUCreateComputePipelineAsyncCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUCreateRenderPipelineAsyncCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUCreateRenderPipelineAsyncCallback callback; - void * userdata; -} WGPUCreateRenderPipelineAsyncCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_CREATE_RENDER_PIPELINE_ASYNC_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUCreateRenderPipelineAsyncCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUInstanceDescriptor -typedef struct WGPUDawnWGSLBlocklist { - WGPUChainedStruct chain; - size_t blocklistedFeatureCount; - const char* const * blocklistedFeatures; -} WGPUDawnWGSLBlocklist WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_WGSL_BLOCKLIST_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnWGSLBlocklist, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnWGSLBlocklist} WGPU_COMMA \ - /*.blocklistedFeatureCount=*/0 WGPU_COMMA \ - /*.blocklistedFeatures=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUAdapterInfo -typedef struct WGPUDawnAdapterPropertiesPowerPreference { - WGPUChainedStructOut chain; - WGPUPowerPreference powerPreference; -} WGPUDawnAdapterPropertiesPowerPreference WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_ADAPTER_PROPERTIES_POWER_PREFERENCE_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnAdapterPropertiesPowerPreference, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnAdapterPropertiesPowerPreference} WGPU_COMMA \ - /*.powerPreference=*/WGPUPowerPreference_Undefined WGPU_COMMA \ -}) - -// Can be chained in WGPUBufferDescriptor -typedef struct WGPUDawnBufferDescriptorErrorInfoFromWireClient { - WGPUChainedStruct chain; - WGPUBool outOfMemory; -} WGPUDawnBufferDescriptorErrorInfoFromWireClient WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_BUFFER_DESCRIPTOR_ERROR_INFO_FROM_WIRE_CLIENT_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnBufferDescriptorErrorInfoFromWireClient, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient} WGPU_COMMA \ - /*.outOfMemory=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUCommandEncoderDescriptor -typedef struct WGPUDawnEncoderInternalUsageDescriptor { - WGPUChainedStruct chain; - WGPUBool useInternalUsages; -} WGPUDawnEncoderInternalUsageDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_ENCODER_INTERNAL_USAGE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnEncoderInternalUsageDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnEncoderInternalUsageDescriptor} WGPU_COMMA \ - /*.useInternalUsages=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUSupportedLimits -typedef struct WGPUDawnExperimentalImmediateDataLimits { - WGPUChainedStructOut chain; - uint32_t maxImmediateDataRangeByteSize; -} WGPUDawnExperimentalImmediateDataLimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_EXPERIMENTAL_IMMEDIATE_DATA_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnExperimentalImmediateDataLimits, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnExperimentalImmediateDataLimits} WGPU_COMMA \ - /*.maxImmediateDataRangeByteSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -// Can be chained in WGPUSupportedLimits -typedef struct WGPUDawnExperimentalSubgroupLimits { - WGPUChainedStructOut chain; - uint32_t minSubgroupSize; - uint32_t maxSubgroupSize; -} WGPUDawnExperimentalSubgroupLimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_EXPERIMENTAL_SUBGROUP_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnExperimentalSubgroupLimits, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnExperimentalSubgroupLimits} WGPU_COMMA \ - /*.minSubgroupSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxSubgroupSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -// Can be chained in WGPURenderPassColorAttachment -typedef struct WGPUDawnRenderPassColorAttachmentRenderToSingleSampled { - WGPUChainedStruct chain; - uint32_t implicitSampleCount; -} WGPUDawnRenderPassColorAttachmentRenderToSingleSampled WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_RENDER_PASS_COLOR_ATTACHMENT_RENDER_TO_SINGLE_SAMPLED_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnRenderPassColorAttachmentRenderToSingleSampled, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled} WGPU_COMMA \ - /*.implicitSampleCount=*/1 WGPU_COMMA \ -}) - -// Can be chained in WGPUShaderModuleDescriptor -typedef struct WGPUDawnShaderModuleSPIRVOptionsDescriptor { - WGPUChainedStruct chain; - WGPUBool allowNonUniformDerivatives; -} WGPUDawnShaderModuleSPIRVOptionsDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_SHADER_MODULE_SPIRV_OPTIONS_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnShaderModuleSPIRVOptionsDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor} WGPU_COMMA \ - /*.allowNonUniformDerivatives=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUSupportedLimits -typedef struct WGPUDawnTexelCopyBufferRowAlignmentLimits { - WGPUChainedStructOut chain; - uint32_t minTexelCopyBufferRowAlignment; -} WGPUDawnTexelCopyBufferRowAlignmentLimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_TEXEL_COPY_BUFFER_ROW_ALIGNMENT_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnTexelCopyBufferRowAlignmentLimits, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnTexelCopyBufferRowAlignmentLimits} WGPU_COMMA \ - /*.minTexelCopyBufferRowAlignment=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -// Can be chained in WGPUTextureDescriptor -typedef struct WGPUDawnTextureInternalUsageDescriptor { - WGPUChainedStruct chain; - WGPUTextureUsage internalUsage; -} WGPUDawnTextureInternalUsageDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_TEXTURE_INTERNAL_USAGE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnTextureInternalUsageDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnTextureInternalUsageDescriptor} WGPU_COMMA \ - /*.internalUsage=*/WGPUTextureUsage_None WGPU_COMMA \ -}) - -// Can be chained in WGPUInstanceDescriptor -// Can be chained in WGPURequestAdapterOptions -// Can be chained in WGPUDeviceDescriptor -typedef struct WGPUDawnTogglesDescriptor { - WGPUChainedStruct chain; - size_t enabledToggleCount; - const char* const * enabledToggles; - size_t disabledToggleCount; - const char* const * disabledToggles; -} WGPUDawnTogglesDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_TOGGLES_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnTogglesDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnTogglesDescriptor} WGPU_COMMA \ - /*.enabledToggleCount=*/0 WGPU_COMMA \ - /*.enabledToggles=*/{} WGPU_COMMA \ - /*.disabledToggleCount=*/0 WGPU_COMMA \ - /*.disabledToggles=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUInstanceDescriptor -typedef struct WGPUDawnWireWGSLControl { - WGPUChainedStruct chain; - WGPUBool enableExperimental; - WGPUBool enableUnsafe; - WGPUBool enableTesting; -} WGPUDawnWireWGSLControl WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_WIRE_WGSL_CONTROL_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnWireWGSLControl, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnWireWGSLControl} WGPU_COMMA \ - /*.enableExperimental=*/false WGPU_COMMA \ - /*.enableUnsafe=*/false WGPU_COMMA \ - /*.enableTesting=*/false WGPU_COMMA \ -}) - -typedef struct WGPUDeviceLostCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUDeviceLostCallbackNew callback; - void * userdata; -} WGPUDeviceLostCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DEVICE_LOST_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUDeviceLostCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/WGPUCallbackMode_WaitAnyOnly WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUDrmFormatProperties { - uint64_t modifier; - uint32_t modifierPlaneCount; -} WGPUDrmFormatProperties WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DRM_FORMAT_PROPERTIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUDrmFormatProperties, { \ - /*.modifier=*/{} WGPU_COMMA \ - /*.modifierPlaneCount=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUExtent2D { - uint32_t width; - uint32_t height; -} WGPUExtent2D WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_EXTENT_2D_INIT WGPU_MAKE_INIT_STRUCT(WGPUExtent2D, { \ - /*.width=*/{} WGPU_COMMA \ - /*.height=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUExtent3D { - uint32_t width; - uint32_t height; - uint32_t depthOrArrayLayers; -} WGPUExtent3D WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_EXTENT_3D_INIT WGPU_MAKE_INIT_STRUCT(WGPUExtent3D, { \ - /*.width=*/{} WGPU_COMMA \ - /*.height=*/1 WGPU_COMMA \ - /*.depthOrArrayLayers=*/1 WGPU_COMMA \ -}) - -// Can be chained in WGPUBindGroupEntry -typedef struct WGPUExternalTextureBindingEntry { - WGPUChainedStruct chain; - WGPUExternalTexture externalTexture; -} WGPUExternalTextureBindingEntry WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_EXTERNAL_TEXTURE_BINDING_ENTRY_INIT WGPU_MAKE_INIT_STRUCT(WGPUExternalTextureBindingEntry, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ExternalTextureBindingEntry} WGPU_COMMA \ - /*.externalTexture=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUBindGroupLayoutEntry -typedef struct WGPUExternalTextureBindingLayout { - WGPUChainedStruct chain; -} WGPUExternalTextureBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_EXTERNAL_TEXTURE_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUExternalTextureBindingLayout, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ExternalTextureBindingLayout} WGPU_COMMA \ -}) - -typedef struct WGPUFormatCapabilities { - WGPUChainedStructOut * nextInChain; -} WGPUFormatCapabilities WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_FORMAT_CAPABILITIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUFormatCapabilities, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUFuture { - uint64_t id; -} WGPUFuture WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_FUTURE_INIT WGPU_MAKE_INIT_STRUCT(WGPUFuture, { \ - /*.id=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUInstanceFeatures { - WGPUChainedStruct const * nextInChain; - WGPUBool timedWaitAnyEnable; - size_t timedWaitAnyMaxCount; -} WGPUInstanceFeatures WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_INSTANCE_FEATURES_INIT WGPU_MAKE_INIT_STRUCT(WGPUInstanceFeatures, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.timedWaitAnyEnable=*/false WGPU_COMMA \ - /*.timedWaitAnyMaxCount=*/0 WGPU_COMMA \ -}) - -typedef struct WGPULimits { - uint32_t maxTextureDimension1D; - uint32_t maxTextureDimension2D; - uint32_t maxTextureDimension3D; - uint32_t maxTextureArrayLayers; - uint32_t maxBindGroups; - uint32_t maxBindGroupsPlusVertexBuffers; - uint32_t maxBindingsPerBindGroup; - uint32_t maxDynamicUniformBuffersPerPipelineLayout; - uint32_t maxDynamicStorageBuffersPerPipelineLayout; - uint32_t maxSampledTexturesPerShaderStage; - uint32_t maxSamplersPerShaderStage; - uint32_t maxStorageBuffersPerShaderStage; - uint32_t maxStorageTexturesPerShaderStage; - uint32_t maxUniformBuffersPerShaderStage; - uint64_t maxUniformBufferBindingSize; - uint64_t maxStorageBufferBindingSize; - uint32_t minUniformBufferOffsetAlignment; - uint32_t minStorageBufferOffsetAlignment; - uint32_t maxVertexBuffers; - uint64_t maxBufferSize; - uint32_t maxVertexAttributes; - uint32_t maxVertexBufferArrayStride; - uint32_t maxInterStageShaderComponents; - uint32_t maxInterStageShaderVariables; - uint32_t maxColorAttachments; - uint32_t maxColorAttachmentBytesPerSample; - uint32_t maxComputeWorkgroupStorageSize; - uint32_t maxComputeInvocationsPerWorkgroup; - uint32_t maxComputeWorkgroupSizeX; - uint32_t maxComputeWorkgroupSizeY; - uint32_t maxComputeWorkgroupSizeZ; - uint32_t maxComputeWorkgroupsPerDimension; - uint32_t maxStorageBuffersInVertexStage; - uint32_t maxStorageTexturesInVertexStage; - uint32_t maxStorageBuffersInFragmentStage; - uint32_t maxStorageTexturesInFragmentStage; -} WGPULimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPULimits, { \ - /*.maxTextureDimension1D=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxTextureDimension2D=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxTextureDimension3D=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxTextureArrayLayers=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxBindGroups=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxBindGroupsPlusVertexBuffers=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxBindingsPerBindGroup=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxDynamicUniformBuffersPerPipelineLayout=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxDynamicStorageBuffersPerPipelineLayout=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxSampledTexturesPerShaderStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxSamplersPerShaderStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageBuffersPerShaderStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageTexturesPerShaderStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxUniformBuffersPerShaderStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxUniformBufferBindingSize=*/WGPU_LIMIT_U64_UNDEFINED WGPU_COMMA \ - /*.maxStorageBufferBindingSize=*/WGPU_LIMIT_U64_UNDEFINED WGPU_COMMA \ - /*.minUniformBufferOffsetAlignment=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.minStorageBufferOffsetAlignment=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxVertexBuffers=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxBufferSize=*/WGPU_LIMIT_U64_UNDEFINED WGPU_COMMA \ - /*.maxVertexAttributes=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxVertexBufferArrayStride=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxInterStageShaderComponents=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxInterStageShaderVariables=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxColorAttachments=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxColorAttachmentBytesPerSample=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeWorkgroupStorageSize=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeInvocationsPerWorkgroup=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeWorkgroupSizeX=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeWorkgroupSizeY=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeWorkgroupSizeZ=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxComputeWorkgroupsPerDimension=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageBuffersInVertexStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageTexturesInVertexStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageBuffersInFragmentStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ - /*.maxStorageTexturesInFragmentStage=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -typedef struct WGPUMemoryHeapInfo { - WGPUHeapProperty properties; - uint64_t size; -} WGPUMemoryHeapInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_MEMORY_HEAP_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUMemoryHeapInfo, { \ - /*.properties=*/{} WGPU_COMMA \ - /*.size=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUMultisampleState { - WGPUChainedStruct const * nextInChain; - uint32_t count; - uint32_t mask; - WGPUBool alphaToCoverageEnabled; -} WGPUMultisampleState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_MULTISAMPLE_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUMultisampleState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.count=*/1 WGPU_COMMA \ - /*.mask=*/0xFFFFFFFF WGPU_COMMA \ - /*.alphaToCoverageEnabled=*/false WGPU_COMMA \ -}) - -typedef struct WGPUOrigin2D { - uint32_t x; - uint32_t y; -} WGPUOrigin2D WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ORIGIN_2D_INIT WGPU_MAKE_INIT_STRUCT(WGPUOrigin2D, { \ - /*.x=*/0 WGPU_COMMA \ - /*.y=*/0 WGPU_COMMA \ -}) - -typedef struct WGPUOrigin3D { - uint32_t x; - uint32_t y; - uint32_t z; -} WGPUOrigin3D WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ORIGIN_3D_INIT WGPU_MAKE_INIT_STRUCT(WGPUOrigin3D, { \ - /*.x=*/0 WGPU_COMMA \ - /*.y=*/0 WGPU_COMMA \ - /*.z=*/0 WGPU_COMMA \ -}) - -typedef struct WGPUPipelineLayoutStorageAttachment { - uint64_t offset; - WGPUTextureFormat format; -} WGPUPipelineLayoutStorageAttachment WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_PIPELINE_LAYOUT_STORAGE_ATTACHMENT_INIT WGPU_MAKE_INIT_STRUCT(WGPUPipelineLayoutStorageAttachment, { \ - /*.offset=*/0 WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUPopErrorScopeCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUPopErrorScopeCallback callback; - WGPUErrorCallback oldCallback; - void * userdata; -} WGPUPopErrorScopeCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_POP_ERROR_SCOPE_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUPopErrorScopeCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/WGPUCallbackMode_WaitAnyOnly WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.oldCallback=*/{} WGPU_COMMA \ - /*.userdata=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUPrimitiveState { - WGPUChainedStruct const * nextInChain; - WGPUPrimitiveTopology topology; - WGPUIndexFormat stripIndexFormat; - WGPUFrontFace frontFace; - WGPUCullMode cullMode; - WGPUBool unclippedDepth; -} WGPUPrimitiveState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_PRIMITIVE_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUPrimitiveState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.topology=*/WGPUPrimitiveTopology_TriangleList WGPU_COMMA \ - /*.stripIndexFormat=*/WGPUIndexFormat_Undefined WGPU_COMMA \ - /*.frontFace=*/WGPUFrontFace_CCW WGPU_COMMA \ - /*.cullMode=*/WGPUCullMode_None WGPU_COMMA \ - /*.unclippedDepth=*/false WGPU_COMMA \ -}) - -typedef struct WGPUQueueWorkDoneCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPUQueueWorkDoneCallback callback; - void * userdata; -} WGPUQueueWorkDoneCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_QUEUE_WORK_DONE_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUQueueWorkDoneCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPURenderPassDepthStencilAttachment { - WGPUTextureView view; - WGPULoadOp depthLoadOp; - WGPUStoreOp depthStoreOp; - float depthClearValue; - WGPUBool depthReadOnly; - WGPULoadOp stencilLoadOp; - WGPUStoreOp stencilStoreOp; - uint32_t stencilClearValue; - WGPUBool stencilReadOnly; -} WGPURenderPassDepthStencilAttachment WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_DEPTH_STENCIL_ATTACHMENT_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassDepthStencilAttachment, { \ - /*.view=*/{} WGPU_COMMA \ - /*.depthLoadOp=*/WGPULoadOp_Undefined WGPU_COMMA \ - /*.depthStoreOp=*/WGPUStoreOp_Undefined WGPU_COMMA \ - /*.depthClearValue=*/NAN WGPU_COMMA \ - /*.depthReadOnly=*/false WGPU_COMMA \ - /*.stencilLoadOp=*/WGPULoadOp_Undefined WGPU_COMMA \ - /*.stencilStoreOp=*/WGPUStoreOp_Undefined WGPU_COMMA \ - /*.stencilClearValue=*/0 WGPU_COMMA \ - /*.stencilReadOnly=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPURenderPassDescriptor -typedef struct WGPURenderPassDescriptorExpandResolveRect { - WGPUChainedStruct chain; - uint32_t x; - uint32_t y; - uint32_t width; - uint32_t height; -} WGPURenderPassDescriptorExpandResolveRect WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_DESCRIPTOR_EXPAND_RESOLVE_RECT_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassDescriptorExpandResolveRect, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_RenderPassDescriptorExpandResolveRect} WGPU_COMMA \ - /*.x=*/{} WGPU_COMMA \ - /*.y=*/{} WGPU_COMMA \ - /*.width=*/{} WGPU_COMMA \ - /*.height=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPURenderPassDescriptor -typedef struct WGPURenderPassMaxDrawCount { - WGPUChainedStruct chain; - uint64_t maxDrawCount; -} WGPURenderPassMaxDrawCount WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_MAX_DRAW_COUNT_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassMaxDrawCount, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_RenderPassMaxDrawCount} WGPU_COMMA \ - /*.maxDrawCount=*/50000000 WGPU_COMMA \ -}) - -typedef struct WGPURenderPassTimestampWrites { - WGPUQuerySet querySet; - uint32_t beginningOfPassWriteIndex; - uint32_t endOfPassWriteIndex; -} WGPURenderPassTimestampWrites WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_TIMESTAMP_WRITES_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassTimestampWrites, { \ - /*.querySet=*/{} WGPU_COMMA \ - /*.beginningOfPassWriteIndex=*/WGPU_QUERY_SET_INDEX_UNDEFINED WGPU_COMMA \ - /*.endOfPassWriteIndex=*/WGPU_QUERY_SET_INDEX_UNDEFINED WGPU_COMMA \ -}) - -typedef struct WGPURequestAdapterCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPURequestAdapterCallback callback; - void * userdata; -} WGPURequestAdapterCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUEST_ADAPTER_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPURequestAdapterCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPURequestAdapterOptions { - WGPUChainedStruct const * nextInChain; - WGPU_NULLABLE WGPUSurface compatibleSurface; - WGPUFeatureLevel featureLevel; - WGPUPowerPreference powerPreference; - WGPUBackendType backendType; - WGPUBool forceFallbackAdapter; - WGPUBool compatibilityMode; -} WGPURequestAdapterOptions WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUEST_ADAPTER_OPTIONS_INIT WGPU_MAKE_INIT_STRUCT(WGPURequestAdapterOptions, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.compatibleSurface=*/nullptr WGPU_COMMA \ - /*.featureLevel=*/WGPUFeatureLevel_Core WGPU_COMMA \ - /*.powerPreference=*/WGPUPowerPreference_Undefined WGPU_COMMA \ - /*.backendType=*/WGPUBackendType_Undefined WGPU_COMMA \ - /*.forceFallbackAdapter=*/false WGPU_COMMA \ - /*.compatibilityMode=*/false WGPU_COMMA \ -}) - -typedef struct WGPURequestDeviceCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUCallbackMode mode; - WGPURequestDeviceCallback callback; - void * userdata; -} WGPURequestDeviceCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUEST_DEVICE_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPURequestDeviceCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.mode=*/{} WGPU_COMMA \ - /*.callback=*/{} WGPU_COMMA \ - /*.userdata=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSamplerBindingLayout { - WGPUChainedStruct const * nextInChain; - WGPUSamplerBindingType type; -} WGPUSamplerBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SAMPLER_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUSamplerBindingLayout, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.type=*/WGPUSamplerBindingType_BindingNotUsed WGPU_COMMA \ -}) - -// Can be chained in WGPUShaderModuleDescriptor -typedef struct WGPUShaderModuleCompilationOptions { - WGPUChainedStruct chain; - WGPUBool strictMath; -} WGPUShaderModuleCompilationOptions WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHADER_MODULE_COMPILATION_OPTIONS_INIT WGPU_MAKE_INIT_STRUCT(WGPUShaderModuleCompilationOptions, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ShaderModuleCompilationOptions} WGPU_COMMA \ - /*.strictMath=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUShaderModuleDescriptor -typedef struct WGPUShaderSourceSPIRV { - WGPUChainedStruct chain; - uint32_t codeSize; - uint32_t const * code; -} WGPUShaderSourceSPIRV WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHADER_SOURCE_SPIRV_INIT WGPU_MAKE_INIT_STRUCT(WGPUShaderSourceSPIRV, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ShaderSourceSPIRV} WGPU_COMMA \ - /*.codeSize=*/{} WGPU_COMMA \ - /*.code=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedBufferMemoryBeginAccessDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUBool initialized; - size_t fenceCount; - WGPUSharedFence const * fences; - uint64_t const * signaledValues; -} WGPUSharedBufferMemoryBeginAccessDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_BUFFER_MEMORY_BEGIN_ACCESS_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedBufferMemoryBeginAccessDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.initialized=*/{} WGPU_COMMA \ - /*.fenceCount=*/0 WGPU_COMMA \ - /*.fences=*/{} WGPU_COMMA \ - /*.signaledValues=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedBufferMemoryEndAccessState { - WGPUChainedStructOut * nextInChain; - WGPUBool initialized; - size_t fenceCount; - WGPUSharedFence const * fences; - uint64_t const * signaledValues; -} WGPUSharedBufferMemoryEndAccessState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_BUFFER_MEMORY_END_ACCESS_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedBufferMemoryEndAccessState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.initialized=*/{} WGPU_COMMA \ - /*.fenceCount=*/0 WGPU_COMMA \ - /*.fences=*/{} WGPU_COMMA \ - /*.signaledValues=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedBufferMemoryProperties { - WGPUChainedStructOut * nextInChain; - WGPUBufferUsage usage; - uint64_t size; -} WGPUSharedBufferMemoryProperties WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_BUFFER_MEMORY_PROPERTIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedBufferMemoryProperties, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.usage=*/{} WGPU_COMMA \ - /*.size=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceDescriptor -typedef struct WGPUSharedFenceDXGISharedHandleDescriptor { - WGPUChainedStruct chain; - void * handle; -} WGPUSharedFenceDXGISharedHandleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_DXGI_SHARED_HANDLE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceDXGISharedHandleDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceDXGISharedHandleDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceExportInfo -typedef struct WGPUSharedFenceDXGISharedHandleExportInfo { - WGPUChainedStructOut chain; - void * handle; -} WGPUSharedFenceDXGISharedHandleExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_DXGI_SHARED_HANDLE_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceDXGISharedHandleExportInfo, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceDXGISharedHandleExportInfo} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceDescriptor -typedef struct WGPUSharedFenceMTLSharedEventDescriptor { - WGPUChainedStruct chain; - void * sharedEvent; -} WGPUSharedFenceMTLSharedEventDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_MTL_SHARED_EVENT_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceMTLSharedEventDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceMTLSharedEventDescriptor} WGPU_COMMA \ - /*.sharedEvent=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceExportInfo -typedef struct WGPUSharedFenceMTLSharedEventExportInfo { - WGPUChainedStructOut chain; - void * sharedEvent; -} WGPUSharedFenceMTLSharedEventExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_MTL_SHARED_EVENT_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceMTLSharedEventExportInfo, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceMTLSharedEventExportInfo} WGPU_COMMA \ - /*.sharedEvent=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedFenceExportInfo { - WGPUChainedStructOut * nextInChain; - WGPUSharedFenceType type; -} WGPUSharedFenceExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceExportInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.type=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceDescriptor -typedef struct WGPUSharedFenceSyncFDDescriptor { - WGPUChainedStruct chain; - int handle; -} WGPUSharedFenceSyncFDDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_SYNC_FD_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceSyncFDDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceSyncFDDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceExportInfo -typedef struct WGPUSharedFenceSyncFDExportInfo { - WGPUChainedStructOut chain; - int handle; -} WGPUSharedFenceSyncFDExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_SYNC_FD_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceSyncFDExportInfo, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceSyncFDExportInfo} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceDescriptor -typedef struct WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor { - WGPUChainedStruct chain; - int handle; -} WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_VK_SEMAPHORE_OPAQUE_FD_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceExportInfo -typedef struct WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo { - WGPUChainedStructOut chain; - int handle; -} WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_VK_SEMAPHORE_OPAQUE_FD_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceDescriptor -typedef struct WGPUSharedFenceVkSemaphoreZirconHandleDescriptor { - WGPUChainedStruct chain; - uint32_t handle; -} WGPUSharedFenceVkSemaphoreZirconHandleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_VK_SEMAPHORE_ZIRCON_HANDLE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceVkSemaphoreZirconHandleDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedFenceExportInfo -typedef struct WGPUSharedFenceVkSemaphoreZirconHandleExportInfo { - WGPUChainedStructOut chain; - uint32_t handle; -} WGPUSharedFenceVkSemaphoreZirconHandleExportInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_VK_SEMAPHORE_ZIRCON_HANDLE_EXPORT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceVkSemaphoreZirconHandleExportInfo, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryBeginAccessDescriptor -typedef struct WGPUSharedTextureMemoryD3DSwapchainBeginState { - WGPUChainedStruct chain; - WGPUBool isSwapchain; -} WGPUSharedTextureMemoryD3DSwapchainBeginState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_D3D_SWAPCHAIN_BEGIN_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryD3DSwapchainBeginState, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryD3DSwapchainBeginState} WGPU_COMMA \ - /*.isSwapchain=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryDXGISharedHandleDescriptor { - WGPUChainedStruct chain; - void * handle; - WGPUBool useKeyedMutex; -} WGPUSharedTextureMemoryDXGISharedHandleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_DXGI_SHARED_HANDLE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryDXGISharedHandleDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ - /*.useKeyedMutex=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryEGLImageDescriptor { - WGPUChainedStruct chain; - void * image; -} WGPUSharedTextureMemoryEGLImageDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_EGL_IMAGE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryEGLImageDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryEGLImageDescriptor} WGPU_COMMA \ - /*.image=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryIOSurfaceDescriptor { - WGPUChainedStruct chain; - void * ioSurface; -} WGPUSharedTextureMemoryIOSurfaceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_IO_SURFACE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryIOSurfaceDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryIOSurfaceDescriptor} WGPU_COMMA \ - /*.ioSurface=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryAHardwareBufferDescriptor { - WGPUChainedStruct chain; - void * handle; - WGPUBool useExternalFormat; -} WGPUSharedTextureMemoryAHardwareBufferDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_A_HARDWARE_BUFFER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryAHardwareBufferDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor} WGPU_COMMA \ - /*.handle=*/{} WGPU_COMMA \ - /*.useExternalFormat=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedTextureMemoryBeginAccessDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUBool concurrentRead; - WGPUBool initialized; - size_t fenceCount; - WGPUSharedFence const * fences; - uint64_t const * signaledValues; -} WGPUSharedTextureMemoryBeginAccessDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_BEGIN_ACCESS_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryBeginAccessDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.concurrentRead=*/{} WGPU_COMMA \ - /*.initialized=*/{} WGPU_COMMA \ - /*.fenceCount=*/{} WGPU_COMMA \ - /*.fences=*/{} WGPU_COMMA \ - /*.signaledValues=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedTextureMemoryDmaBufPlane { - int fd; - uint64_t offset; - uint32_t stride; -} WGPUSharedTextureMemoryDmaBufPlane WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_DMA_BUF_PLANE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryDmaBufPlane, { \ - /*.fd=*/{} WGPU_COMMA \ - /*.offset=*/{} WGPU_COMMA \ - /*.stride=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedTextureMemoryEndAccessState { - WGPUChainedStructOut * nextInChain; - WGPUBool initialized; - size_t fenceCount; - WGPUSharedFence const * fences; - uint64_t const * signaledValues; -} WGPUSharedTextureMemoryEndAccessState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_END_ACCESS_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryEndAccessState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.initialized=*/{} WGPU_COMMA \ - /*.fenceCount=*/{} WGPU_COMMA \ - /*.fences=*/{} WGPU_COMMA \ - /*.signaledValues=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryOpaqueFDDescriptor { - WGPUChainedStruct chain; - void const * vkImageCreateInfo; - int memoryFD; - uint32_t memoryTypeIndex; - uint64_t allocationSize; - WGPUBool dedicatedAllocation; -} WGPUSharedTextureMemoryOpaqueFDDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_OPAQUE_FD_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryOpaqueFDDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryOpaqueFDDescriptor} WGPU_COMMA \ - /*.vkImageCreateInfo=*/{} WGPU_COMMA \ - /*.memoryFD=*/{} WGPU_COMMA \ - /*.memoryTypeIndex=*/{} WGPU_COMMA \ - /*.allocationSize=*/{} WGPU_COMMA \ - /*.dedicatedAllocation=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor { - WGPUChainedStruct chain; - WGPUBool dedicatedAllocation; -} WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_VK_DEDICATED_ALLOCATION_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor} WGPU_COMMA \ - /*.dedicatedAllocation=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryBeginAccessDescriptor -typedef struct WGPUSharedTextureMemoryVkImageLayoutBeginState { - WGPUChainedStruct chain; - int32_t oldLayout; - int32_t newLayout; -} WGPUSharedTextureMemoryVkImageLayoutBeginState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_VK_IMAGE_LAYOUT_BEGIN_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryVkImageLayoutBeginState, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryVkImageLayoutBeginState} WGPU_COMMA \ - /*.oldLayout=*/{} WGPU_COMMA \ - /*.newLayout=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryEndAccessState -typedef struct WGPUSharedTextureMemoryVkImageLayoutEndState { - WGPUChainedStructOut chain; - int32_t oldLayout; - int32_t newLayout; -} WGPUSharedTextureMemoryVkImageLayoutEndState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_VK_IMAGE_LAYOUT_END_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryVkImageLayoutEndState, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryVkImageLayoutEndState} WGPU_COMMA \ - /*.oldLayout=*/{} WGPU_COMMA \ - /*.newLayout=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryZirconHandleDescriptor { - WGPUChainedStruct chain; - uint32_t memoryFD; - uint64_t allocationSize; -} WGPUSharedTextureMemoryZirconHandleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_ZIRCON_HANDLE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryZirconHandleDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryZirconHandleDescriptor} WGPU_COMMA \ - /*.memoryFD=*/{} WGPU_COMMA \ - /*.allocationSize=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUBindGroupLayoutEntry -typedef struct WGPUStaticSamplerBindingLayout { - WGPUChainedStruct chain; - WGPUSampler sampler; - uint32_t sampledTextureBinding; -} WGPUStaticSamplerBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_STATIC_SAMPLER_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUStaticSamplerBindingLayout, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_StaticSamplerBindingLayout} WGPU_COMMA \ - /*.sampler=*/{} WGPU_COMMA \ - /*.sampledTextureBinding=*/WGPU_LIMIT_U32_UNDEFINED WGPU_COMMA \ -}) - -typedef struct WGPUStencilFaceState { - WGPUCompareFunction compare; - WGPUStencilOperation failOp; - WGPUStencilOperation depthFailOp; - WGPUStencilOperation passOp; -} WGPUStencilFaceState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_STENCIL_FACE_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUStencilFaceState, { \ - /*.compare=*/WGPUCompareFunction_Always WGPU_COMMA \ - /*.failOp=*/WGPUStencilOperation_Keep WGPU_COMMA \ - /*.depthFailOp=*/WGPUStencilOperation_Keep WGPU_COMMA \ - /*.passOp=*/WGPUStencilOperation_Keep WGPU_COMMA \ -}) - -typedef struct WGPUStorageTextureBindingLayout { - WGPUChainedStruct const * nextInChain; - WGPUStorageTextureAccess access; - WGPUTextureFormat format; - WGPUTextureViewDimension viewDimension; -} WGPUStorageTextureBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_STORAGE_TEXTURE_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUStorageTextureBindingLayout, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.access=*/WGPUStorageTextureAccess_BindingNotUsed WGPU_COMMA \ - /*.format=*/WGPUTextureFormat_Undefined WGPU_COMMA \ - /*.viewDimension=*/WGPUTextureViewDimension_2D WGPU_COMMA \ -}) - -typedef struct WGPUStringView { - WGPU_NULLABLE char const * data; - size_t length; -} WGPUStringView WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_STRING_VIEW_INIT WGPU_MAKE_INIT_STRUCT(WGPUStringView, { \ - /*.data=*/nullptr WGPU_COMMA \ - /*.length=*/WGPU_STRLEN WGPU_COMMA \ -}) - -typedef struct WGPUSupportedFeatures { - size_t featureCount; - WGPUFeatureName const * features; -} WGPUSupportedFeatures WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SUPPORTED_FEATURES_INIT WGPU_MAKE_INIT_STRUCT(WGPUSupportedFeatures, { \ - /*.featureCount=*/{} WGPU_COMMA \ - /*.features=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSurfaceCapabilities { - WGPUChainedStructOut * nextInChain; - WGPUTextureUsage usages; - size_t formatCount; - WGPUTextureFormat const * formats; - size_t presentModeCount; - WGPUPresentMode const * presentModes; - size_t alphaModeCount; - WGPUCompositeAlphaMode const * alphaModes; -} WGPUSurfaceCapabilities WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_CAPABILITIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceCapabilities, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.usages=*/{} WGPU_COMMA \ - /*.formatCount=*/{} WGPU_COMMA \ - /*.formats=*/{} WGPU_COMMA \ - /*.presentModeCount=*/{} WGPU_COMMA \ - /*.presentModes=*/{} WGPU_COMMA \ - /*.alphaModeCount=*/{} WGPU_COMMA \ - /*.alphaModes=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSurfaceConfiguration { - WGPUChainedStruct const * nextInChain; - WGPUDevice device; - WGPUTextureFormat format; - WGPUTextureUsage usage; - size_t viewFormatCount; - WGPUTextureFormat const * viewFormats; - WGPUCompositeAlphaMode alphaMode; - uint32_t width; - uint32_t height; - WGPUPresentMode presentMode; -} WGPUSurfaceConfiguration WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_CONFIGURATION_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceConfiguration, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.device=*/{} WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ - /*.usage=*/WGPUTextureUsage_RenderAttachment WGPU_COMMA \ - /*.viewFormatCount=*/0 WGPU_COMMA \ - /*.viewFormats=*/nullptr WGPU_COMMA \ - /*.alphaMode=*/WGPUCompositeAlphaMode_Auto WGPU_COMMA \ - /*.width=*/{} WGPU_COMMA \ - /*.height=*/{} WGPU_COMMA \ - /*.presentMode=*/WGPUPresentMode_Fifo WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceDescriptorFromWindowsCoreWindow { - WGPUChainedStruct chain; - void * coreWindow; -} WGPUSurfaceDescriptorFromWindowsCoreWindow WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_DESCRIPTOR_FROM_WINDOWS_CORE_WINDOW_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceDescriptorFromWindowsCoreWindow, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceDescriptorFromWindowsCoreWindow} WGPU_COMMA \ - /*.coreWindow=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceDescriptorFromWindowsSwapChainPanel { - WGPUChainedStruct chain; - void * swapChainPanel; -} WGPUSurfaceDescriptorFromWindowsSwapChainPanel WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_DESCRIPTOR_FROM_WINDOWS_SWAP_CHAIN_PANEL_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceDescriptorFromWindowsSwapChainPanel, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel} WGPU_COMMA \ - /*.swapChainPanel=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceXCBWindow { - WGPUChainedStruct chain; - void * connection; - uint32_t window; -} WGPUSurfaceSourceXCBWindow WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_XCB_WINDOW_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceXCBWindow, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceXCBWindow} WGPU_COMMA \ - /*.connection=*/{} WGPU_COMMA \ - /*.window=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceAndroidNativeWindow { - WGPUChainedStruct chain; - void * window; -} WGPUSurfaceSourceAndroidNativeWindow WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_ANDROID_NATIVE_WINDOW_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceAndroidNativeWindow, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceAndroidNativeWindow} WGPU_COMMA \ - /*.window=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceMetalLayer { - WGPUChainedStruct chain; - void * layer; -} WGPUSurfaceSourceMetalLayer WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_METAL_LAYER_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceMetalLayer, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceMetalLayer} WGPU_COMMA \ - /*.layer=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceWaylandSurface { - WGPUChainedStruct chain; - void * display; - void * surface; -} WGPUSurfaceSourceWaylandSurface WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_WAYLAND_SURFACE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceWaylandSurface, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceWaylandSurface} WGPU_COMMA \ - /*.display=*/{} WGPU_COMMA \ - /*.surface=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceWindowsHWND { - WGPUChainedStruct chain; - void * hinstance; - void * hwnd; -} WGPUSurfaceSourceWindowsHWND WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_WINDOWS_HWND_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceWindowsHWND, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceWindowsHWND} WGPU_COMMA \ - /*.hinstance=*/{} WGPU_COMMA \ - /*.hwnd=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceXlibWindow { - WGPUChainedStruct chain; - void * display; - uint64_t window; -} WGPUSurfaceSourceXlibWindow WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_XLIB_WINDOW_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceXlibWindow, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceXlibWindow} WGPU_COMMA \ - /*.display=*/{} WGPU_COMMA \ - /*.window=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSurfaceTexture { - WGPUTexture texture; - WGPUBool suboptimal; - WGPUSurfaceGetCurrentTextureStatus status; -} WGPUSurfaceTexture WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_TEXTURE_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceTexture, { \ - /*.texture=*/{} WGPU_COMMA \ - /*.suboptimal=*/{} WGPU_COMMA \ - /*.status=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUTextureBindingLayout { - WGPUChainedStruct const * nextInChain; - WGPUTextureSampleType sampleType; - WGPUTextureViewDimension viewDimension; - WGPUBool multisampled; -} WGPUTextureBindingLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_TEXTURE_BINDING_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUTextureBindingLayout, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.sampleType=*/WGPUTextureSampleType_BindingNotUsed WGPU_COMMA \ - /*.viewDimension=*/WGPUTextureViewDimension_2D WGPU_COMMA \ - /*.multisampled=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUTextureDescriptor -typedef struct WGPUTextureBindingViewDimensionDescriptor { - WGPUChainedStruct chain; - WGPUTextureViewDimension textureBindingViewDimension; -} WGPUTextureBindingViewDimensionDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_TEXTURE_BINDING_VIEW_DIMENSION_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUTextureBindingViewDimensionDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_TextureBindingViewDimensionDescriptor} WGPU_COMMA \ - /*.textureBindingViewDimension=*/WGPUTextureViewDimension_Undefined WGPU_COMMA \ -}) - -typedef struct WGPUTextureDataLayout { - WGPUChainedStruct const * nextInChain; - uint64_t offset; - uint32_t bytesPerRow; - uint32_t rowsPerImage; -} WGPUTextureDataLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_TEXTURE_DATA_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUTextureDataLayout, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.offset=*/0 WGPU_COMMA \ - /*.bytesPerRow=*/WGPU_COPY_STRIDE_UNDEFINED WGPU_COMMA \ - /*.rowsPerImage=*/WGPU_COPY_STRIDE_UNDEFINED WGPU_COMMA \ -}) - -typedef struct WGPUUncapturedErrorCallbackInfo { - WGPUChainedStruct const * nextInChain; - WGPUErrorCallback callback; - void * userdata; -} WGPUUncapturedErrorCallbackInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_UNCAPTURED_ERROR_CALLBACK_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUUncapturedErrorCallbackInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.callback=*/nullptr WGPU_COMMA \ - /*.userdata=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUVertexAttribute { - WGPUVertexFormat format; - uint64_t offset; - uint32_t shaderLocation; -} WGPUVertexAttribute WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_VERTEX_ATTRIBUTE_INIT WGPU_MAKE_INIT_STRUCT(WGPUVertexAttribute, { \ - /*.format=*/{} WGPU_COMMA \ - /*.offset=*/{} WGPU_COMMA \ - /*.shaderLocation=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUSamplerDescriptor -// Can be chained in WGPUTextureViewDescriptor -typedef struct WGPUYCbCrVkDescriptor { - WGPUChainedStruct chain; - uint32_t vkFormat; - uint32_t vkYCbCrModel; - uint32_t vkYCbCrRange; - uint32_t vkComponentSwizzleRed; - uint32_t vkComponentSwizzleGreen; - uint32_t vkComponentSwizzleBlue; - uint32_t vkComponentSwizzleAlpha; - uint32_t vkXChromaOffset; - uint32_t vkYChromaOffset; - WGPUFilterMode vkChromaFilter; - WGPUBool forceExplicitReconstruction; - uint64_t externalFormat; -} WGPUYCbCrVkDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_Y_CB_CR_VK_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUYCbCrVkDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_YCbCrVkDescriptor} WGPU_COMMA \ - /*.vkFormat=*/0 WGPU_COMMA \ - /*.vkYCbCrModel=*/0 WGPU_COMMA \ - /*.vkYCbCrRange=*/0 WGPU_COMMA \ - /*.vkComponentSwizzleRed=*/0 WGPU_COMMA \ - /*.vkComponentSwizzleGreen=*/0 WGPU_COMMA \ - /*.vkComponentSwizzleBlue=*/0 WGPU_COMMA \ - /*.vkComponentSwizzleAlpha=*/0 WGPU_COMMA \ - /*.vkXChromaOffset=*/0 WGPU_COMMA \ - /*.vkYChromaOffset=*/0 WGPU_COMMA \ - /*.vkChromaFilter=*/WGPUFilterMode_Nearest WGPU_COMMA \ - /*.forceExplicitReconstruction=*/false WGPU_COMMA \ - /*.externalFormat=*/0 WGPU_COMMA \ -}) - -typedef struct WGPUAHardwareBufferProperties { - WGPUYCbCrVkDescriptor yCbCrInfo; -} WGPUAHardwareBufferProperties WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_A_HARDWARE_BUFFER_PROPERTIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUAHardwareBufferProperties, { \ - /*.yCbCrInfo=*/WGPU_Y_CB_CR_VK_DESCRIPTOR_INIT WGPU_COMMA \ -}) - -typedef struct WGPUAdapterInfo { - WGPUChainedStructOut * nextInChain; - WGPUStringView vendor; - WGPUStringView architecture; - WGPUStringView device; - WGPUStringView description; - WGPUBackendType backendType; - WGPUAdapterType adapterType; - uint32_t vendorID; - uint32_t deviceID; - WGPUBool compatibilityMode; -} WGPUAdapterInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ADAPTER_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUAdapterInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.vendor=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.architecture=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.device=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.description=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.backendType=*/{} WGPU_COMMA \ - /*.adapterType=*/{} WGPU_COMMA \ - /*.vendorID=*/{} WGPU_COMMA \ - /*.deviceID=*/{} WGPU_COMMA \ - /*.compatibilityMode=*/false WGPU_COMMA \ -}) - -// Can be chained in WGPUAdapterInfo -typedef struct WGPUAdapterPropertiesMemoryHeaps { - WGPUChainedStructOut chain; - size_t heapCount; - WGPUMemoryHeapInfo const * heapInfo; -} WGPUAdapterPropertiesMemoryHeaps WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_ADAPTER_PROPERTIES_MEMORY_HEAPS_INIT WGPU_MAKE_INIT_STRUCT(WGPUAdapterPropertiesMemoryHeaps, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_AdapterPropertiesMemoryHeaps} WGPU_COMMA \ - /*.heapCount=*/{} WGPU_COMMA \ - /*.heapInfo=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUBindGroupDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUBindGroupLayout layout; - size_t entryCount; - WGPUBindGroupEntry const * entries; -} WGPUBindGroupDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BIND_GROUP_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUBindGroupDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.layout=*/{} WGPU_COMMA \ - /*.entryCount=*/{} WGPU_COMMA \ - /*.entries=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUBindGroupLayoutEntry { - WGPUChainedStruct const * nextInChain; - uint32_t binding; - WGPUShaderStage visibility; - WGPUBufferBindingLayout buffer; - WGPUSamplerBindingLayout sampler; - WGPUTextureBindingLayout texture; - WGPUStorageTextureBindingLayout storageTexture; -} WGPUBindGroupLayoutEntry WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BIND_GROUP_LAYOUT_ENTRY_INIT WGPU_MAKE_INIT_STRUCT(WGPUBindGroupLayoutEntry, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.binding=*/{} WGPU_COMMA \ - /*.visibility=*/{} WGPU_COMMA \ - /*.buffer=*/WGPU_BUFFER_BINDING_LAYOUT_INIT WGPU_COMMA \ - /*.sampler=*/WGPU_SAMPLER_BINDING_LAYOUT_INIT WGPU_COMMA \ - /*.texture=*/WGPU_TEXTURE_BINDING_LAYOUT_INIT WGPU_COMMA \ - /*.storageTexture=*/WGPU_STORAGE_TEXTURE_BINDING_LAYOUT_INIT WGPU_COMMA \ -}) - -typedef struct WGPUBlendState { - WGPUBlendComponent color; - WGPUBlendComponent alpha; -} WGPUBlendState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BLEND_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUBlendState, { \ - /*.color=*/WGPU_BLEND_COMPONENT_INIT WGPU_COMMA \ - /*.alpha=*/WGPU_BLEND_COMPONENT_INIT WGPU_COMMA \ -}) - -typedef struct WGPUBufferDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUBufferUsage usage; - uint64_t size; - WGPUBool mappedAtCreation; -} WGPUBufferDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BUFFER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUBufferDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.usage=*/{} WGPU_COMMA \ - /*.size=*/{} WGPU_COMMA \ - /*.mappedAtCreation=*/false WGPU_COMMA \ -}) - -typedef struct WGPUCommandBufferDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUCommandBufferDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMMAND_BUFFER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUCommandBufferDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPUCommandEncoderDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUCommandEncoderDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMMAND_ENCODER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUCommandEncoderDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPUCompilationMessage { - WGPUChainedStruct const * nextInChain; - WGPUStringView message; - WGPUCompilationMessageType type; - uint64_t lineNum; - uint64_t linePos; - uint64_t offset; - uint64_t length; - uint64_t utf16LinePos; - uint64_t utf16Offset; - uint64_t utf16Length; -} WGPUCompilationMessage WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPILATION_MESSAGE_INIT WGPU_MAKE_INIT_STRUCT(WGPUCompilationMessage, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.message=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.type=*/{} WGPU_COMMA \ - /*.lineNum=*/{} WGPU_COMMA \ - /*.linePos=*/{} WGPU_COMMA \ - /*.offset=*/{} WGPU_COMMA \ - /*.length=*/{} WGPU_COMMA \ - /*.utf16LinePos=*/{} WGPU_COMMA \ - /*.utf16Offset=*/{} WGPU_COMMA \ - /*.utf16Length=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUComputePassDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPU_NULLABLE WGPUComputePassTimestampWrites const * timestampWrites; -} WGPUComputePassDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPUTE_PASS_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUComputePassDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.timestampWrites=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUConstantEntry { - WGPUChainedStruct const * nextInChain; - WGPUStringView key; - double value; -} WGPUConstantEntry WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_CONSTANT_ENTRY_INIT WGPU_MAKE_INIT_STRUCT(WGPUConstantEntry, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.key=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.value=*/{} WGPU_COMMA \ -}) - -// Can be chained in WGPUDeviceDescriptor -typedef struct WGPUDawnCacheDeviceDescriptor { - WGPUChainedStruct chain; - WGPUStringView isolationKey; - WGPUDawnLoadCacheDataFunction loadDataFunction; - WGPUDawnStoreCacheDataFunction storeDataFunction; - void * functionUserdata; -} WGPUDawnCacheDeviceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DAWN_CACHE_DEVICE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDawnCacheDeviceDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DawnCacheDeviceDescriptor} WGPU_COMMA \ - /*.isolationKey=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.loadDataFunction=*/nullptr WGPU_COMMA \ - /*.storeDataFunction=*/nullptr WGPU_COMMA \ - /*.functionUserdata=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUDepthStencilState { - WGPUChainedStruct const * nextInChain; - WGPUTextureFormat format; - WGPUOptionalBool depthWriteEnabled; - WGPUCompareFunction depthCompare; - WGPUStencilFaceState stencilFront; - WGPUStencilFaceState stencilBack; - uint32_t stencilReadMask; - uint32_t stencilWriteMask; - int32_t depthBias; - float depthBiasSlopeScale; - float depthBiasClamp; -} WGPUDepthStencilState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DEPTH_STENCIL_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUDepthStencilState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ - /*.depthWriteEnabled=*/WGPUOptionalBool_Undefined WGPU_COMMA \ - /*.depthCompare=*/WGPUCompareFunction_Undefined WGPU_COMMA \ - /*.stencilFront=*/WGPU_STENCIL_FACE_STATE_INIT WGPU_COMMA \ - /*.stencilBack=*/WGPU_STENCIL_FACE_STATE_INIT WGPU_COMMA \ - /*.stencilReadMask=*/0xFFFFFFFF WGPU_COMMA \ - /*.stencilWriteMask=*/0xFFFFFFFF WGPU_COMMA \ - /*.depthBias=*/0 WGPU_COMMA \ - /*.depthBiasSlopeScale=*/0.0f WGPU_COMMA \ - /*.depthBiasClamp=*/0.0f WGPU_COMMA \ -}) - -// Can be chained in WGPUFormatCapabilities -typedef struct WGPUDrmFormatCapabilities { - WGPUChainedStructOut chain; - size_t propertiesCount; - WGPUDrmFormatProperties const * properties; -} WGPUDrmFormatCapabilities WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DRM_FORMAT_CAPABILITIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUDrmFormatCapabilities, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_DrmFormatCapabilities} WGPU_COMMA \ - /*.propertiesCount=*/{} WGPU_COMMA \ - /*.properties=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUExternalTextureDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUTextureView plane0; - WGPU_NULLABLE WGPUTextureView plane1; - WGPUOrigin2D cropOrigin; - WGPUExtent2D cropSize; - WGPUExtent2D apparentSize; - WGPUBool doYuvToRgbConversionOnly; - WGPU_NULLABLE float const * yuvToRgbConversionMatrix; - float const * srcTransferFunctionParameters; - float const * dstTransferFunctionParameters; - float const * gamutConversionMatrix; - WGPUBool mirrored; - WGPUExternalTextureRotation rotation; -} WGPUExternalTextureDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_EXTERNAL_TEXTURE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUExternalTextureDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.plane0=*/{} WGPU_COMMA \ - /*.plane1=*/nullptr WGPU_COMMA \ - /*.cropOrigin=*/WGPU_ORIGIN_2D_INIT WGPU_COMMA \ - /*.cropSize=*/WGPU_EXTENT_2D_INIT WGPU_COMMA \ - /*.apparentSize=*/WGPU_EXTENT_2D_INIT WGPU_COMMA \ - /*.doYuvToRgbConversionOnly=*/false WGPU_COMMA \ - /*.yuvToRgbConversionMatrix=*/nullptr WGPU_COMMA \ - /*.srcTransferFunctionParameters=*/{} WGPU_COMMA \ - /*.dstTransferFunctionParameters=*/{} WGPU_COMMA \ - /*.gamutConversionMatrix=*/{} WGPU_COMMA \ - /*.mirrored=*/false WGPU_COMMA \ - /*.rotation=*/WGPUExternalTextureRotation_Rotate0Degrees WGPU_COMMA \ -}) - -typedef struct WGPUFutureWaitInfo { - WGPUFuture future; - WGPUBool completed; -} WGPUFutureWaitInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_FUTURE_WAIT_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUFutureWaitInfo, { \ - /*.future=*/WGPU_FUTURE_INIT WGPU_COMMA \ - /*.completed=*/false WGPU_COMMA \ -}) - -typedef struct WGPUImageCopyBuffer { - WGPUTextureDataLayout layout; - WGPUBuffer buffer; -} WGPUImageCopyBuffer WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_IMAGE_COPY_BUFFER_INIT WGPU_MAKE_INIT_STRUCT(WGPUImageCopyBuffer, { \ - /*.layout=*/WGPU_TEXTURE_DATA_LAYOUT_INIT WGPU_COMMA \ - /*.buffer=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUImageCopyExternalTexture { - WGPUChainedStruct const * nextInChain; - WGPUExternalTexture externalTexture; - WGPUOrigin3D origin; - WGPUExtent2D naturalSize; -} WGPUImageCopyExternalTexture WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_IMAGE_COPY_EXTERNAL_TEXTURE_INIT WGPU_MAKE_INIT_STRUCT(WGPUImageCopyExternalTexture, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.externalTexture=*/{} WGPU_COMMA \ - /*.origin=*/WGPU_ORIGIN_3D_INIT WGPU_COMMA \ - /*.naturalSize=*/WGPU_EXTENT_2D_INIT WGPU_COMMA \ -}) - -typedef struct WGPUImageCopyTexture { - WGPUTexture texture; - uint32_t mipLevel; - WGPUOrigin3D origin; - WGPUTextureAspect aspect; -} WGPUImageCopyTexture WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_IMAGE_COPY_TEXTURE_INIT WGPU_MAKE_INIT_STRUCT(WGPUImageCopyTexture, { \ - /*.texture=*/{} WGPU_COMMA \ - /*.mipLevel=*/0 WGPU_COMMA \ - /*.origin=*/WGPU_ORIGIN_3D_INIT WGPU_COMMA \ - /*.aspect=*/WGPUTextureAspect_All WGPU_COMMA \ -}) - -typedef struct WGPUInstanceDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUInstanceFeatures features; -} WGPUInstanceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_INSTANCE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUInstanceDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.features=*/WGPU_INSTANCE_FEATURES_INIT WGPU_COMMA \ -}) - -typedef struct WGPUPipelineLayoutDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - size_t bindGroupLayoutCount; - WGPU_NULLABLE WGPUBindGroupLayout const * bindGroupLayouts; - uint32_t immediateDataRangeByteSize; -} WGPUPipelineLayoutDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_PIPELINE_LAYOUT_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUPipelineLayoutDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.bindGroupLayoutCount=*/{} WGPU_COMMA \ - /*.bindGroupLayouts=*/nullptr WGPU_COMMA \ - /*.immediateDataRangeByteSize=*/0 WGPU_COMMA \ -}) - -// Can be chained in WGPUPipelineLayoutDescriptor -typedef struct WGPUPipelineLayoutPixelLocalStorage { - WGPUChainedStruct chain; - uint64_t totalPixelLocalStorageSize; - size_t storageAttachmentCount; - WGPUPipelineLayoutStorageAttachment const * storageAttachments; -} WGPUPipelineLayoutPixelLocalStorage WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_PIPELINE_LAYOUT_PIXEL_LOCAL_STORAGE_INIT WGPU_MAKE_INIT_STRUCT(WGPUPipelineLayoutPixelLocalStorage, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_PipelineLayoutPixelLocalStorage} WGPU_COMMA \ - /*.totalPixelLocalStorageSize=*/{} WGPU_COMMA \ - /*.storageAttachmentCount=*/0 WGPU_COMMA \ - /*.storageAttachments=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUQuerySetDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUQueryType type; - uint32_t count; -} WGPUQuerySetDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_QUERY_SET_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUQuerySetDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.type=*/{} WGPU_COMMA \ - /*.count=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUQueueDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUQueueDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_QUEUE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUQueueDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPURenderBundleDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPURenderBundleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_BUNDLE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderBundleDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPURenderBundleEncoderDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - size_t colorFormatCount; - WGPUTextureFormat const * colorFormats; - WGPUTextureFormat depthStencilFormat; - uint32_t sampleCount; - WGPUBool depthReadOnly; - WGPUBool stencilReadOnly; -} WGPURenderBundleEncoderDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_BUNDLE_ENCODER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderBundleEncoderDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.colorFormatCount=*/{} WGPU_COMMA \ - /*.colorFormats=*/{} WGPU_COMMA \ - /*.depthStencilFormat=*/WGPUTextureFormat_Undefined WGPU_COMMA \ - /*.sampleCount=*/1 WGPU_COMMA \ - /*.depthReadOnly=*/false WGPU_COMMA \ - /*.stencilReadOnly=*/false WGPU_COMMA \ -}) - -typedef struct WGPURenderPassColorAttachment { - WGPUChainedStruct const * nextInChain; - WGPU_NULLABLE WGPUTextureView view; - uint32_t depthSlice; - WGPU_NULLABLE WGPUTextureView resolveTarget; - WGPULoadOp loadOp; - WGPUStoreOp storeOp; - WGPUColor clearValue; -} WGPURenderPassColorAttachment WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_COLOR_ATTACHMENT_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassColorAttachment, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.view=*/nullptr WGPU_COMMA \ - /*.depthSlice=*/WGPU_DEPTH_SLICE_UNDEFINED WGPU_COMMA \ - /*.resolveTarget=*/nullptr WGPU_COMMA \ - /*.loadOp=*/{} WGPU_COMMA \ - /*.storeOp=*/{} WGPU_COMMA \ - /*.clearValue=*/WGPU_COLOR_INIT WGPU_COMMA \ -}) - -typedef struct WGPURenderPassStorageAttachment { - WGPUChainedStruct const * nextInChain; - uint64_t offset; - WGPUTextureView storage; - WGPULoadOp loadOp; - WGPUStoreOp storeOp; - WGPUColor clearValue; -} WGPURenderPassStorageAttachment WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_STORAGE_ATTACHMENT_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassStorageAttachment, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.offset=*/0 WGPU_COMMA \ - /*.storage=*/{} WGPU_COMMA \ - /*.loadOp=*/{} WGPU_COMMA \ - /*.storeOp=*/{} WGPU_COMMA \ - /*.clearValue=*/WGPU_COLOR_INIT WGPU_COMMA \ -}) - -typedef struct WGPURequiredLimits { - WGPUChainedStruct const * nextInChain; - WGPULimits limits; -} WGPURequiredLimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_REQUIRED_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPURequiredLimits, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.limits=*/WGPU_LIMITS_INIT WGPU_COMMA \ -}) - -typedef struct WGPUSamplerDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUAddressMode addressModeU; - WGPUAddressMode addressModeV; - WGPUAddressMode addressModeW; - WGPUFilterMode magFilter; - WGPUFilterMode minFilter; - WGPUMipmapFilterMode mipmapFilter; - float lodMinClamp; - float lodMaxClamp; - WGPUCompareFunction compare; - uint16_t maxAnisotropy; -} WGPUSamplerDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SAMPLER_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSamplerDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.addressModeU=*/WGPUAddressMode_ClampToEdge WGPU_COMMA \ - /*.addressModeV=*/WGPUAddressMode_ClampToEdge WGPU_COMMA \ - /*.addressModeW=*/WGPUAddressMode_ClampToEdge WGPU_COMMA \ - /*.magFilter=*/WGPUFilterMode_Nearest WGPU_COMMA \ - /*.minFilter=*/WGPUFilterMode_Nearest WGPU_COMMA \ - /*.mipmapFilter=*/WGPUMipmapFilterMode_Nearest WGPU_COMMA \ - /*.lodMinClamp=*/0.0f WGPU_COMMA \ - /*.lodMaxClamp=*/32.0f WGPU_COMMA \ - /*.compare=*/WGPUCompareFunction_Undefined WGPU_COMMA \ - /*.maxAnisotropy=*/1 WGPU_COMMA \ -}) - -typedef struct WGPUShaderModuleDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUShaderModuleDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHADER_MODULE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUShaderModuleDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -// Can be chained in WGPUShaderModuleDescriptor -typedef struct WGPUShaderSourceWGSL { - WGPUChainedStruct chain; - WGPUStringView code; -} WGPUShaderSourceWGSL WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHADER_SOURCE_WGSL_INIT WGPU_MAKE_INIT_STRUCT(WGPUShaderSourceWGSL, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_ShaderSourceWGSL} WGPU_COMMA \ - /*.code=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPUSharedBufferMemoryDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUSharedBufferMemoryDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_BUFFER_MEMORY_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedBufferMemoryDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPUSharedFenceDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUSharedFenceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_FENCE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedFenceDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryProperties -typedef struct WGPUSharedTextureMemoryAHardwareBufferProperties { - WGPUChainedStructOut chain; - WGPUYCbCrVkDescriptor yCbCrInfo; -} WGPUSharedTextureMemoryAHardwareBufferProperties WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_A_HARDWARE_BUFFER_PROPERTIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryAHardwareBufferProperties, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryAHardwareBufferProperties} WGPU_COMMA \ - /*.yCbCrInfo=*/WGPU_Y_CB_CR_VK_DESCRIPTOR_INIT WGPU_COMMA \ -}) - -typedef struct WGPUSharedTextureMemoryDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUSharedTextureMemoryDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -// Can be chained in WGPUSharedTextureMemoryDescriptor -typedef struct WGPUSharedTextureMemoryDmaBufDescriptor { - WGPUChainedStruct chain; - WGPUExtent3D size; - uint32_t drmFormat; - uint64_t drmModifier; - size_t planeCount; - WGPUSharedTextureMemoryDmaBufPlane const * planes; -} WGPUSharedTextureMemoryDmaBufDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_DMA_BUF_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryDmaBufDescriptor, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SharedTextureMemoryDmaBufDescriptor} WGPU_COMMA \ - /*.size=*/WGPU_EXTENT_3D_INIT WGPU_COMMA \ - /*.drmFormat=*/{} WGPU_COMMA \ - /*.drmModifier=*/{} WGPU_COMMA \ - /*.planeCount=*/{} WGPU_COMMA \ - /*.planes=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSharedTextureMemoryProperties { - WGPUChainedStructOut * nextInChain; - WGPUTextureUsage usage; - WGPUExtent3D size; - WGPUTextureFormat format; -} WGPUSharedTextureMemoryProperties WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SHARED_TEXTURE_MEMORY_PROPERTIES_INIT WGPU_MAKE_INIT_STRUCT(WGPUSharedTextureMemoryProperties, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.usage=*/{} WGPU_COMMA \ - /*.size=*/WGPU_EXTENT_3D_INIT WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUSupportedLimits { - WGPUChainedStructOut * nextInChain; - WGPULimits limits; -} WGPUSupportedLimits WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SUPPORTED_LIMITS_INIT WGPU_MAKE_INIT_STRUCT(WGPUSupportedLimits, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.limits=*/WGPU_LIMITS_INIT WGPU_COMMA \ -}) - -typedef struct WGPUSurfaceDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; -} WGPUSurfaceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -// Can be chained in WGPUSurfaceDescriptor -typedef struct WGPUSurfaceSourceCanvasHTMLSelector_Emscripten { - WGPUChainedStruct chain; - WGPUStringView selector; -} WGPUSurfaceSourceCanvasHTMLSelector_Emscripten WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_SURFACE_SOURCE_CANVAS_HTML_SELECTOR__EMSCRIPTEN_INIT WGPU_MAKE_INIT_STRUCT(WGPUSurfaceSourceCanvasHTMLSelector_Emscripten, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten} WGPU_COMMA \ - /*.selector=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ -}) - -typedef struct WGPUTextureDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUTextureUsage usage; - WGPUTextureDimension dimension; - WGPUExtent3D size; - WGPUTextureFormat format; - uint32_t mipLevelCount; - uint32_t sampleCount; - size_t viewFormatCount; - WGPUTextureFormat const * viewFormats; -} WGPUTextureDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_TEXTURE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUTextureDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.usage=*/{} WGPU_COMMA \ - /*.dimension=*/WGPUTextureDimension_2D WGPU_COMMA \ - /*.size=*/WGPU_EXTENT_3D_INIT WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ - /*.mipLevelCount=*/1 WGPU_COMMA \ - /*.sampleCount=*/1 WGPU_COMMA \ - /*.viewFormatCount=*/0 WGPU_COMMA \ - /*.viewFormats=*/nullptr WGPU_COMMA \ -}) - -typedef struct WGPUTextureViewDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPUTextureFormat format; - WGPUTextureViewDimension dimension; - uint32_t baseMipLevel; - uint32_t mipLevelCount; - uint32_t baseArrayLayer; - uint32_t arrayLayerCount; - WGPUTextureAspect aspect; - WGPUTextureUsage usage; -} WGPUTextureViewDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_TEXTURE_VIEW_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUTextureViewDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.format=*/WGPUTextureFormat_Undefined WGPU_COMMA \ - /*.dimension=*/WGPUTextureViewDimension_Undefined WGPU_COMMA \ - /*.baseMipLevel=*/0 WGPU_COMMA \ - /*.mipLevelCount=*/WGPU_MIP_LEVEL_COUNT_UNDEFINED WGPU_COMMA \ - /*.baseArrayLayer=*/0 WGPU_COMMA \ - /*.arrayLayerCount=*/WGPU_ARRAY_LAYER_COUNT_UNDEFINED WGPU_COMMA \ - /*.aspect=*/WGPUTextureAspect_All WGPU_COMMA \ - /*.usage=*/WGPUTextureUsage_None WGPU_COMMA \ -}) - -typedef struct WGPUVertexBufferLayout { - uint64_t arrayStride; - WGPUVertexStepMode stepMode; - size_t attributeCount; - WGPUVertexAttribute const * attributes; -} WGPUVertexBufferLayout WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_VERTEX_BUFFER_LAYOUT_INIT WGPU_MAKE_INIT_STRUCT(WGPUVertexBufferLayout, { \ - /*.arrayStride=*/{} WGPU_COMMA \ - /*.stepMode=*/{} WGPU_COMMA \ - /*.attributeCount=*/{} WGPU_COMMA \ - /*.attributes=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUBindGroupLayoutDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - size_t entryCount; - WGPUBindGroupLayoutEntry const * entries; -} WGPUBindGroupLayoutDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_BIND_GROUP_LAYOUT_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUBindGroupLayoutDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.entryCount=*/{} WGPU_COMMA \ - /*.entries=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUColorTargetState { - WGPUChainedStruct const * nextInChain; - WGPUTextureFormat format; - WGPU_NULLABLE WGPUBlendState const * blend; - WGPUColorWriteMask writeMask; -} WGPUColorTargetState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COLOR_TARGET_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUColorTargetState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.format=*/{} WGPU_COMMA \ - /*.blend=*/nullptr WGPU_COMMA \ - /*.writeMask=*/WGPUColorWriteMask_All WGPU_COMMA \ -}) - -typedef struct WGPUCompilationInfo { - WGPUChainedStruct const * nextInChain; - size_t messageCount; - WGPUCompilationMessage const * messages; -} WGPUCompilationInfo WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPILATION_INFO_INIT WGPU_MAKE_INIT_STRUCT(WGPUCompilationInfo, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.messageCount=*/{} WGPU_COMMA \ - /*.messages=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUComputeState { - WGPUChainedStruct const * nextInChain; - WGPUShaderModule module; - WGPUStringView entryPoint; - size_t constantCount; - WGPUConstantEntry const * constants; -} WGPUComputeState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPUTE_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUComputeState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.module=*/{} WGPU_COMMA \ - /*.entryPoint=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.constantCount=*/0 WGPU_COMMA \ - /*.constants=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUDeviceDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - size_t requiredFeatureCount; - WGPUFeatureName const * requiredFeatures; - WGPU_NULLABLE WGPURequiredLimits const * requiredLimits; - WGPUQueueDescriptor defaultQueue; - WGPUDeviceLostCallbackInfo2 deviceLostCallbackInfo2; - WGPUUncapturedErrorCallbackInfo2 uncapturedErrorCallbackInfo2; -} WGPUDeviceDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_DEVICE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUDeviceDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.requiredFeatureCount=*/0 WGPU_COMMA \ - /*.requiredFeatures=*/nullptr WGPU_COMMA \ - /*.requiredLimits=*/nullptr WGPU_COMMA \ - /*.defaultQueue=*/WGPU_QUEUE_DESCRIPTOR_INIT WGPU_COMMA \ - /*.deviceLostCallbackInfo2=*/{} WGPU_COMMA \ - /*.uncapturedErrorCallbackInfo2=*/{} WGPU_COMMA \ -}) - -typedef struct WGPURenderPassDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - size_t colorAttachmentCount; - WGPURenderPassColorAttachment const * colorAttachments; - WGPU_NULLABLE WGPURenderPassDepthStencilAttachment const * depthStencilAttachment; - WGPU_NULLABLE WGPUQuerySet occlusionQuerySet; - WGPU_NULLABLE WGPURenderPassTimestampWrites const * timestampWrites; -} WGPURenderPassDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.colorAttachmentCount=*/{} WGPU_COMMA \ - /*.colorAttachments=*/{} WGPU_COMMA \ - /*.depthStencilAttachment=*/nullptr WGPU_COMMA \ - /*.occlusionQuerySet=*/nullptr WGPU_COMMA \ - /*.timestampWrites=*/nullptr WGPU_COMMA \ -}) - -// Can be chained in WGPURenderPassDescriptor -typedef struct WGPURenderPassPixelLocalStorage { - WGPUChainedStruct chain; - uint64_t totalPixelLocalStorageSize; - size_t storageAttachmentCount; - WGPURenderPassStorageAttachment const * storageAttachments; -} WGPURenderPassPixelLocalStorage WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PASS_PIXEL_LOCAL_STORAGE_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPassPixelLocalStorage, { \ - /*.chain=*/{/*.nextInChain*/nullptr WGPU_COMMA /*.sType*/WGPUSType_RenderPassPixelLocalStorage} WGPU_COMMA \ - /*.totalPixelLocalStorageSize=*/{} WGPU_COMMA \ - /*.storageAttachmentCount=*/0 WGPU_COMMA \ - /*.storageAttachments=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUVertexState { - WGPUChainedStruct const * nextInChain; - WGPUShaderModule module; - WGPUStringView entryPoint; - size_t constantCount; - WGPUConstantEntry const * constants; - size_t bufferCount; - WGPUVertexBufferLayout const * buffers; -} WGPUVertexState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_VERTEX_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUVertexState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.module=*/{} WGPU_COMMA \ - /*.entryPoint=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.constantCount=*/0 WGPU_COMMA \ - /*.constants=*/{} WGPU_COMMA \ - /*.bufferCount=*/0 WGPU_COMMA \ - /*.buffers=*/{} WGPU_COMMA \ -}) - -typedef struct WGPUComputePipelineDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPU_NULLABLE WGPUPipelineLayout layout; - WGPUComputeState compute; -} WGPUComputePipelineDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_COMPUTE_PIPELINE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPUComputePipelineDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.layout=*/nullptr WGPU_COMMA \ - /*.compute=*/WGPU_COMPUTE_STATE_INIT WGPU_COMMA \ -}) - -typedef struct WGPUFragmentState { - WGPUChainedStruct const * nextInChain; - WGPUShaderModule module; - WGPUStringView entryPoint; - size_t constantCount; - WGPUConstantEntry const * constants; - size_t targetCount; - WGPUColorTargetState const * targets; -} WGPUFragmentState WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_FRAGMENT_STATE_INIT WGPU_MAKE_INIT_STRUCT(WGPUFragmentState, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.module=*/{} WGPU_COMMA \ - /*.entryPoint=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.constantCount=*/0 WGPU_COMMA \ - /*.constants=*/{} WGPU_COMMA \ - /*.targetCount=*/{} WGPU_COMMA \ - /*.targets=*/{} WGPU_COMMA \ -}) - -typedef struct WGPURenderPipelineDescriptor { - WGPUChainedStruct const * nextInChain; - WGPUStringView label; - WGPU_NULLABLE WGPUPipelineLayout layout; - WGPUVertexState vertex; - WGPUPrimitiveState primitive; - WGPU_NULLABLE WGPUDepthStencilState const * depthStencil; - WGPUMultisampleState multisample; - WGPU_NULLABLE WGPUFragmentState const * fragment; -} WGPURenderPipelineDescriptor WGPU_STRUCTURE_ATTRIBUTE; - -#define WGPU_RENDER_PIPELINE_DESCRIPTOR_INIT WGPU_MAKE_INIT_STRUCT(WGPURenderPipelineDescriptor, { \ - /*.nextInChain=*/nullptr WGPU_COMMA \ - /*.label=*/WGPU_STRING_VIEW_INIT WGPU_COMMA \ - /*.layout=*/nullptr WGPU_COMMA \ - /*.vertex=*/WGPU_VERTEX_STATE_INIT WGPU_COMMA \ - /*.primitive=*/WGPU_PRIMITIVE_STATE_INIT WGPU_COMMA \ - /*.depthStencil=*/nullptr WGPU_COMMA \ - /*.multisample=*/WGPU_MULTISAMPLE_STATE_INIT WGPU_COMMA \ - /*.fragment=*/nullptr WGPU_COMMA \ -}) - -// WGPURenderPassDescriptorMaxDrawCount is deprecated. -// Use WGPURenderPassMaxDrawCount instead. -typedef WGPURenderPassMaxDrawCount WGPURenderPassDescriptorMaxDrawCount; - -// WGPUShaderModuleSPIRVDescriptor is deprecated. -// Use WGPUShaderSourceSPIRV instead. -typedef WGPUShaderSourceSPIRV WGPUShaderModuleSPIRVDescriptor; - -// WGPUShaderModuleWGSLDescriptor is deprecated. -// Use WGPUShaderSourceWGSL instead. -typedef WGPUShaderSourceWGSL WGPUShaderModuleWGSLDescriptor; - -// WGPUSurfaceDescriptorFromAndroidNativeWindow is deprecated. -// Use WGPUSurfaceSourceAndroidNativeWindow instead. -typedef WGPUSurfaceSourceAndroidNativeWindow WGPUSurfaceDescriptorFromAndroidNativeWindow; - -// WGPUSurfaceDescriptorFromCanvasHTMLSelector is deprecated. -// Use WGPUSurfaceSourceCanvasHTMLSelector_Emscripten instead. -typedef WGPUSurfaceSourceCanvasHTMLSelector_Emscripten WGPUSurfaceDescriptorFromCanvasHTMLSelector; - -// WGPUSurfaceDescriptorFromMetalLayer is deprecated. -// Use WGPUSurfaceSourceMetalLayer instead. -typedef WGPUSurfaceSourceMetalLayer WGPUSurfaceDescriptorFromMetalLayer; - -// WGPUSurfaceDescriptorFromWaylandSurface is deprecated. -// Use WGPUSurfaceSourceWaylandSurface instead. -typedef WGPUSurfaceSourceWaylandSurface WGPUSurfaceDescriptorFromWaylandSurface; - -// WGPUSurfaceDescriptorFromWindowsHWND is deprecated. -// Use WGPUSurfaceSourceWindowsHWND instead. -typedef WGPUSurfaceSourceWindowsHWND WGPUSurfaceDescriptorFromWindowsHWND; - -// WGPUSurfaceDescriptorFromXcbWindow is deprecated. -// Use WGPUSurfaceSourceXCBWindow instead. -typedef WGPUSurfaceSourceXCBWindow WGPUSurfaceDescriptorFromXcbWindow; - -// WGPUSurfaceDescriptorFromXlibWindow is deprecated. -// Use WGPUSurfaceSourceXlibWindow instead. -typedef WGPUSurfaceSourceXlibWindow WGPUSurfaceDescriptorFromXlibWindow; - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(WGPU_SKIP_PROCS) - -// TODO(374150686): Remove these Emscripten specific declarations from the -// header once they are fully deprecated. -#ifdef __EMSCRIPTEN__ -WGPU_EXPORT WGPUDevice emscripten_webgpu_get_device(void); -#endif - -typedef void (*WGPUProcAdapterInfoFreeMembers)( WGPUAdapterInfo value) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcAdapterPropertiesMemoryHeapsFreeMembers)( WGPUAdapterPropertiesMemoryHeaps value) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUInstance (*WGPUProcCreateInstance)( WGPU_NULLABLE WGPUInstanceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDrmFormatCapabilitiesFreeMembers)( WGPUDrmFormatCapabilities value) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcGetInstanceFeatures)( WGPUInstanceFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUProc (*WGPUProcGetProcAddress)( WGPUStringView procName) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedBufferMemoryEndAccessStateFreeMembers)( WGPUSharedBufferMemoryEndAccessState value) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedTextureMemoryEndAccessStateFreeMembers)( WGPUSharedTextureMemoryEndAccessState value) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSupportedFeaturesFreeMembers)( WGPUSupportedFeatures value) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceCapabilitiesFreeMembers)( WGPUSurfaceCapabilities value) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Adapter -typedef WGPUDevice (*WGPUProcAdapterCreateDevice)(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcAdapterGetFeatures)(WGPUAdapter adapter, WGPUSupportedFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcAdapterGetFormatCapabilities)(WGPUAdapter adapter, WGPUTextureFormat format, WGPUFormatCapabilities * capabilities) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcAdapterGetInfo)(WGPUAdapter adapter, WGPUAdapterInfo * info) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUInstance (*WGPUProcAdapterGetInstance)(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcAdapterGetLimits)(WGPUAdapter adapter, WGPUSupportedLimits * limits) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBool (*WGPUProcAdapterHasFeature)(WGPUAdapter adapter, WGPUFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcAdapterRequestDevice)(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * descriptor, WGPURequestDeviceCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcAdapterRequestDevice2)(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * options, WGPURequestDeviceCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcAdapterRequestDeviceF)(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * options, WGPURequestDeviceCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcAdapterAddRef)(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcAdapterRelease)(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of BindGroup -typedef void (*WGPUProcBindGroupSetLabel)(WGPUBindGroup bindGroup, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBindGroupAddRef)(WGPUBindGroup bindGroup) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBindGroupRelease)(WGPUBindGroup bindGroup) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of BindGroupLayout -typedef void (*WGPUProcBindGroupLayoutSetLabel)(WGPUBindGroupLayout bindGroupLayout, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBindGroupLayoutAddRef)(WGPUBindGroupLayout bindGroupLayout) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBindGroupLayoutRelease)(WGPUBindGroupLayout bindGroupLayout) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Buffer -typedef void (*WGPUProcBufferDestroy)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void const * (*WGPUProcBufferGetConstMappedRange)(WGPUBuffer buffer, size_t offset, size_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBufferMapState (*WGPUProcBufferGetMapState)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void * (*WGPUProcBufferGetMappedRange)(WGPUBuffer buffer, size_t offset, size_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef uint64_t (*WGPUProcBufferGetSize)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBufferUsage (*WGPUProcBufferGetUsage)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBufferMapAsync)(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcBufferMapAsync2)(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcBufferMapAsyncF)(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBufferSetLabel)(WGPUBuffer buffer, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBufferUnmap)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBufferAddRef)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcBufferRelease)(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of CommandBuffer -typedef void (*WGPUProcCommandBufferSetLabel)(WGPUCommandBuffer commandBuffer, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandBufferAddRef)(WGPUCommandBuffer commandBuffer) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandBufferRelease)(WGPUCommandBuffer commandBuffer) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of CommandEncoder -typedef WGPUComputePassEncoder (*WGPUProcCommandEncoderBeginComputePass)(WGPUCommandEncoder commandEncoder, WGPU_NULLABLE WGPUComputePassDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPURenderPassEncoder (*WGPUProcCommandEncoderBeginRenderPass)(WGPUCommandEncoder commandEncoder, WGPURenderPassDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderClearBuffer)(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderCopyBufferToBuffer)(WGPUCommandEncoder commandEncoder, WGPUBuffer source, uint64_t sourceOffset, WGPUBuffer destination, uint64_t destinationOffset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderCopyBufferToTexture)(WGPUCommandEncoder commandEncoder, WGPUImageCopyBuffer const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderCopyTextureToBuffer)(WGPUCommandEncoder commandEncoder, WGPUImageCopyTexture const * source, WGPUImageCopyBuffer const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderCopyTextureToTexture)(WGPUCommandEncoder commandEncoder, WGPUImageCopyTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUCommandBuffer (*WGPUProcCommandEncoderFinish)(WGPUCommandEncoder commandEncoder, WGPU_NULLABLE WGPUCommandBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderInjectValidationError)(WGPUCommandEncoder commandEncoder, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderInsertDebugMarker)(WGPUCommandEncoder commandEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderPopDebugGroup)(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderPushDebugGroup)(WGPUCommandEncoder commandEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderResolveQuerySet)(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t firstQuery, uint32_t queryCount, WGPUBuffer destination, uint64_t destinationOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderSetLabel)(WGPUCommandEncoder commandEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderWriteBuffer)(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t bufferOffset, uint8_t const * data, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderWriteTimestamp)(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderAddRef)(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcCommandEncoderRelease)(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of ComputePassEncoder -typedef void (*WGPUProcComputePassEncoderDispatchWorkgroups)(WGPUComputePassEncoder computePassEncoder, uint32_t workgroupCountX, uint32_t workgroupCountY, uint32_t workgroupCountZ) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderDispatchWorkgroupsIndirect)(WGPUComputePassEncoder computePassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderEnd)(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderInsertDebugMarker)(WGPUComputePassEncoder computePassEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderPopDebugGroup)(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderPushDebugGroup)(WGPUComputePassEncoder computePassEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderSetBindGroup)(WGPUComputePassEncoder computePassEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderSetLabel)(WGPUComputePassEncoder computePassEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderSetPipeline)(WGPUComputePassEncoder computePassEncoder, WGPUComputePipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderWriteTimestamp)(WGPUComputePassEncoder computePassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderAddRef)(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePassEncoderRelease)(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of ComputePipeline -typedef WGPUBindGroupLayout (*WGPUProcComputePipelineGetBindGroupLayout)(WGPUComputePipeline computePipeline, uint32_t groupIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePipelineSetLabel)(WGPUComputePipeline computePipeline, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePipelineAddRef)(WGPUComputePipeline computePipeline) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcComputePipelineRelease)(WGPUComputePipeline computePipeline) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Device -typedef WGPUBindGroup (*WGPUProcDeviceCreateBindGroup)(WGPUDevice device, WGPUBindGroupDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBindGroupLayout (*WGPUProcDeviceCreateBindGroupLayout)(WGPUDevice device, WGPUBindGroupLayoutDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBuffer (*WGPUProcDeviceCreateBuffer)(WGPUDevice device, WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUCommandEncoder (*WGPUProcDeviceCreateCommandEncoder)(WGPUDevice device, WGPU_NULLABLE WGPUCommandEncoderDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUComputePipeline (*WGPUProcDeviceCreateComputePipeline)(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceCreateComputePipelineAsync)(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDeviceCreateComputePipelineAsync2)(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDeviceCreateComputePipelineAsyncF)(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBuffer (*WGPUProcDeviceCreateErrorBuffer)(WGPUDevice device, WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUExternalTexture (*WGPUProcDeviceCreateErrorExternalTexture)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUShaderModule (*WGPUProcDeviceCreateErrorShaderModule)(WGPUDevice device, WGPUShaderModuleDescriptor const * descriptor, WGPUStringView errorMessage) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTexture (*WGPUProcDeviceCreateErrorTexture)(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUExternalTexture (*WGPUProcDeviceCreateExternalTexture)(WGPUDevice device, WGPUExternalTextureDescriptor const * externalTextureDescriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUPipelineLayout (*WGPUProcDeviceCreatePipelineLayout)(WGPUDevice device, WGPUPipelineLayoutDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUQuerySet (*WGPUProcDeviceCreateQuerySet)(WGPUDevice device, WGPUQuerySetDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPURenderBundleEncoder (*WGPUProcDeviceCreateRenderBundleEncoder)(WGPUDevice device, WGPURenderBundleEncoderDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPURenderPipeline (*WGPUProcDeviceCreateRenderPipeline)(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceCreateRenderPipelineAsync)(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDeviceCreateRenderPipelineAsync2)(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDeviceCreateRenderPipelineAsyncF)(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUSampler (*WGPUProcDeviceCreateSampler)(WGPUDevice device, WGPU_NULLABLE WGPUSamplerDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUShaderModule (*WGPUProcDeviceCreateShaderModule)(WGPUDevice device, WGPUShaderModuleDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTexture (*WGPUProcDeviceCreateTexture)(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceDestroy)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceForceLoss)(WGPUDevice device, WGPUDeviceLostReason type, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcDeviceGetAHardwareBufferProperties)(WGPUDevice device, void * handle, WGPUAHardwareBufferProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUAdapter (*WGPUProcDeviceGetAdapter)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcDeviceGetAdapterInfo)(WGPUDevice device, WGPUAdapterInfo * adapterInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceGetFeatures)(WGPUDevice device, WGPUSupportedFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcDeviceGetLimits)(WGPUDevice device, WGPUSupportedLimits * limits) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDeviceGetLostFuture)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUQueue (*WGPUProcDeviceGetQueue)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBool (*WGPUProcDeviceHasFeature)(WGPUDevice device, WGPUFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUSharedBufferMemory (*WGPUProcDeviceImportSharedBufferMemory)(WGPUDevice device, WGPUSharedBufferMemoryDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUSharedFence (*WGPUProcDeviceImportSharedFence)(WGPUDevice device, WGPUSharedFenceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUSharedTextureMemory (*WGPUProcDeviceImportSharedTextureMemory)(WGPUDevice device, WGPUSharedTextureMemoryDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceInjectError)(WGPUDevice device, WGPUErrorType type, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDevicePopErrorScope)(WGPUDevice device, WGPUErrorCallback oldCallback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDevicePopErrorScope2)(WGPUDevice device, WGPUPopErrorScopeCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcDevicePopErrorScopeF)(WGPUDevice device, WGPUPopErrorScopeCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDevicePushErrorScope)(WGPUDevice device, WGPUErrorFilter filter) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceSetLabel)(WGPUDevice device, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceSetLoggingCallback)(WGPUDevice device, WGPULoggingCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceTick)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceValidateTextureDescriptor)(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceAddRef)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcDeviceRelease)(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of ExternalTexture -typedef void (*WGPUProcExternalTextureDestroy)(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcExternalTextureExpire)(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcExternalTextureRefresh)(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcExternalTextureSetLabel)(WGPUExternalTexture externalTexture, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcExternalTextureAddRef)(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcExternalTextureRelease)(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Instance -typedef WGPUSurface (*WGPUProcInstanceCreateSurface)(WGPUInstance instance, WGPUSurfaceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef size_t (*WGPUProcInstanceEnumerateWGSLLanguageFeatures)(WGPUInstance instance, WGPUWGSLFeatureName * features) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBool (*WGPUProcInstanceHasWGSLLanguageFeature)(WGPUInstance instance, WGPUWGSLFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcInstanceProcessEvents)(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcInstanceRequestAdapter)(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcInstanceRequestAdapter2)(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcInstanceRequestAdapterF)(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUWaitStatus (*WGPUProcInstanceWaitAny)(WGPUInstance instance, size_t futureCount, WGPUFutureWaitInfo * futures, uint64_t timeoutNS) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcInstanceAddRef)(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcInstanceRelease)(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of PipelineLayout -typedef void (*WGPUProcPipelineLayoutSetLabel)(WGPUPipelineLayout pipelineLayout, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcPipelineLayoutAddRef)(WGPUPipelineLayout pipelineLayout) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcPipelineLayoutRelease)(WGPUPipelineLayout pipelineLayout) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of QuerySet -typedef void (*WGPUProcQuerySetDestroy)(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcQuerySetGetCount)(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUQueryType (*WGPUProcQuerySetGetType)(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQuerySetSetLabel)(WGPUQuerySet querySet, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQuerySetAddRef)(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQuerySetRelease)(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Queue -typedef void (*WGPUProcQueueCopyExternalTextureForBrowser)(WGPUQueue queue, WGPUImageCopyExternalTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize, WGPUCopyTextureForBrowserOptions const * options) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueCopyTextureForBrowser)(WGPUQueue queue, WGPUImageCopyTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize, WGPUCopyTextureForBrowserOptions const * options) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueOnSubmittedWorkDone)(WGPUQueue queue, WGPUQueueWorkDoneCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcQueueOnSubmittedWorkDone2)(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcQueueOnSubmittedWorkDoneF)(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueSetLabel)(WGPUQueue queue, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueSubmit)(WGPUQueue queue, size_t commandCount, WGPUCommandBuffer const * commands) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueWriteBuffer)(WGPUQueue queue, WGPUBuffer buffer, uint64_t bufferOffset, void const * data, size_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueWriteTexture)(WGPUQueue queue, WGPUImageCopyTexture const * destination, void const * data, size_t dataSize, WGPUTextureDataLayout const * dataLayout, WGPUExtent3D const * writeSize) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueAddRef)(WGPUQueue queue) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcQueueRelease)(WGPUQueue queue) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of RenderBundle -typedef void (*WGPUProcRenderBundleSetLabel)(WGPURenderBundle renderBundle, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleAddRef)(WGPURenderBundle renderBundle) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleRelease)(WGPURenderBundle renderBundle) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of RenderBundleEncoder -typedef void (*WGPUProcRenderBundleEncoderDraw)(WGPURenderBundleEncoder renderBundleEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderDrawIndexed)(WGPURenderBundleEncoder renderBundleEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderDrawIndexedIndirect)(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderDrawIndirect)(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPURenderBundle (*WGPUProcRenderBundleEncoderFinish)(WGPURenderBundleEncoder renderBundleEncoder, WGPU_NULLABLE WGPURenderBundleDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderInsertDebugMarker)(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderPopDebugGroup)(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderPushDebugGroup)(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderSetBindGroup)(WGPURenderBundleEncoder renderBundleEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderSetIndexBuffer)(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderSetLabel)(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderSetPipeline)(WGPURenderBundleEncoder renderBundleEncoder, WGPURenderPipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderSetVertexBuffer)(WGPURenderBundleEncoder renderBundleEncoder, uint32_t slot, WGPU_NULLABLE WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderAddRef)(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderBundleEncoderRelease)(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of RenderPassEncoder -typedef void (*WGPUProcRenderPassEncoderBeginOcclusionQuery)(WGPURenderPassEncoder renderPassEncoder, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderDraw)(WGPURenderPassEncoder renderPassEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderDrawIndexed)(WGPURenderPassEncoder renderPassEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderDrawIndexedIndirect)(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderDrawIndirect)(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderEnd)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderEndOcclusionQuery)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderExecuteBundles)(WGPURenderPassEncoder renderPassEncoder, size_t bundleCount, WGPURenderBundle const * bundles) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderInsertDebugMarker)(WGPURenderPassEncoder renderPassEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderMultiDrawIndexedIndirect)(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPU_NULLABLE WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderMultiDrawIndirect)(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPU_NULLABLE WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderPixelLocalStorageBarrier)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderPopDebugGroup)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderPushDebugGroup)(WGPURenderPassEncoder renderPassEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetBindGroup)(WGPURenderPassEncoder renderPassEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetBlendConstant)(WGPURenderPassEncoder renderPassEncoder, WGPUColor const * color) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetIndexBuffer)(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetLabel)(WGPURenderPassEncoder renderPassEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetPipeline)(WGPURenderPassEncoder renderPassEncoder, WGPURenderPipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetScissorRect)(WGPURenderPassEncoder renderPassEncoder, uint32_t x, uint32_t y, uint32_t width, uint32_t height) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetStencilReference)(WGPURenderPassEncoder renderPassEncoder, uint32_t reference) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetVertexBuffer)(WGPURenderPassEncoder renderPassEncoder, uint32_t slot, WGPU_NULLABLE WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderSetViewport)(WGPURenderPassEncoder renderPassEncoder, float x, float y, float width, float height, float minDepth, float maxDepth) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderWriteTimestamp)(WGPURenderPassEncoder renderPassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderAddRef)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPassEncoderRelease)(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of RenderPipeline -typedef WGPUBindGroupLayout (*WGPUProcRenderPipelineGetBindGroupLayout)(WGPURenderPipeline renderPipeline, uint32_t groupIndex) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPipelineSetLabel)(WGPURenderPipeline renderPipeline, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPipelineAddRef)(WGPURenderPipeline renderPipeline) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcRenderPipelineRelease)(WGPURenderPipeline renderPipeline) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Sampler -typedef void (*WGPUProcSamplerSetLabel)(WGPUSampler sampler, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSamplerAddRef)(WGPUSampler sampler) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSamplerRelease)(WGPUSampler sampler) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of ShaderModule -typedef void (*WGPUProcShaderModuleGetCompilationInfo)(WGPUShaderModule shaderModule, WGPUCompilationInfoCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcShaderModuleGetCompilationInfo2)(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUFuture (*WGPUProcShaderModuleGetCompilationInfoF)(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcShaderModuleSetLabel)(WGPUShaderModule shaderModule, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcShaderModuleAddRef)(WGPUShaderModule shaderModule) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcShaderModuleRelease)(WGPUShaderModule shaderModule) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of SharedBufferMemory -typedef WGPUStatus (*WGPUProcSharedBufferMemoryBeginAccess)(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, WGPUSharedBufferMemoryBeginAccessDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBuffer (*WGPUProcSharedBufferMemoryCreateBuffer)(WGPUSharedBufferMemory sharedBufferMemory, WGPU_NULLABLE WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcSharedBufferMemoryEndAccess)(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, WGPUSharedBufferMemoryEndAccessState * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcSharedBufferMemoryGetProperties)(WGPUSharedBufferMemory sharedBufferMemory, WGPUSharedBufferMemoryProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBool (*WGPUProcSharedBufferMemoryIsDeviceLost)(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedBufferMemorySetLabel)(WGPUSharedBufferMemory sharedBufferMemory, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedBufferMemoryAddRef)(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedBufferMemoryRelease)(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of SharedFence -typedef void (*WGPUProcSharedFenceExportInfo)(WGPUSharedFence sharedFence, WGPUSharedFenceExportInfo * info) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedFenceAddRef)(WGPUSharedFence sharedFence) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedFenceRelease)(WGPUSharedFence sharedFence) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of SharedTextureMemory -typedef WGPUStatus (*WGPUProcSharedTextureMemoryBeginAccess)(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, WGPUSharedTextureMemoryBeginAccessDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTexture (*WGPUProcSharedTextureMemoryCreateTexture)(WGPUSharedTextureMemory sharedTextureMemory, WGPU_NULLABLE WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcSharedTextureMemoryEndAccess)(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, WGPUSharedTextureMemoryEndAccessState * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcSharedTextureMemoryGetProperties)(WGPUSharedTextureMemory sharedTextureMemory, WGPUSharedTextureMemoryProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUBool (*WGPUProcSharedTextureMemoryIsDeviceLost)(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedTextureMemorySetLabel)(WGPUSharedTextureMemory sharedTextureMemory, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedTextureMemoryAddRef)(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSharedTextureMemoryRelease)(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Surface -typedef void (*WGPUProcSurfaceConfigure)(WGPUSurface surface, WGPUSurfaceConfiguration const * config) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUStatus (*WGPUProcSurfaceGetCapabilities)(WGPUSurface surface, WGPUAdapter adapter, WGPUSurfaceCapabilities * capabilities) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceGetCurrentTexture)(WGPUSurface surface, WGPUSurfaceTexture * surfaceTexture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfacePresent)(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceSetLabel)(WGPUSurface surface, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceUnconfigure)(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceAddRef)(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcSurfaceRelease)(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of Texture -typedef WGPUTextureView (*WGPUProcTextureCreateErrorView)(WGPUTexture texture, WGPU_NULLABLE WGPUTextureViewDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTextureView (*WGPUProcTextureCreateView)(WGPUTexture texture, WGPU_NULLABLE WGPUTextureViewDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureDestroy)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcTextureGetDepthOrArrayLayers)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTextureDimension (*WGPUProcTextureGetDimension)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTextureFormat (*WGPUProcTextureGetFormat)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcTextureGetHeight)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcTextureGetMipLevelCount)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcTextureGetSampleCount)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef WGPUTextureUsage (*WGPUProcTextureGetUsage)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef uint32_t (*WGPUProcTextureGetWidth)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureSetLabel)(WGPUTexture texture, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureAddRef)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureRelease)(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; - -// Procs of TextureView -typedef void (*WGPUProcTextureViewSetLabel)(WGPUTextureView textureView, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureViewAddRef)(WGPUTextureView textureView) WGPU_FUNCTION_ATTRIBUTE; -typedef void (*WGPUProcTextureViewRelease)(WGPUTextureView textureView) WGPU_FUNCTION_ATTRIBUTE; - - -#endif // !defined(WGPU_SKIP_PROCS) - -#if !defined(WGPU_SKIP_DECLARATIONS) - -WGPU_EXPORT void wgpuAdapterInfoFreeMembers(WGPUAdapterInfo value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuAdapterPropertiesMemoryHeapsFreeMembers(WGPUAdapterPropertiesMemoryHeaps value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUInstance wgpuCreateInstance(WGPU_NULLABLE WGPUInstanceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDrmFormatCapabilitiesFreeMembers(WGPUDrmFormatCapabilities value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuGetInstanceFeatures(WGPUInstanceFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUProc wgpuGetProcAddress(WGPUStringView procName) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedBufferMemoryEndAccessStateFreeMembers(WGPUSharedBufferMemoryEndAccessState value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedTextureMemoryEndAccessStateFreeMembers(WGPUSharedTextureMemoryEndAccessState value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSupportedFeaturesFreeMembers(WGPUSupportedFeatures value) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceCapabilitiesFreeMembers(WGPUSurfaceCapabilities value) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Adapter -WGPU_EXPORT WGPUDevice wgpuAdapterCreateDevice(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuAdapterGetFeatures(WGPUAdapter adapter, WGPUSupportedFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuAdapterGetFormatCapabilities(WGPUAdapter adapter, WGPUTextureFormat format, WGPUFormatCapabilities * capabilities) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuAdapterGetInfo(WGPUAdapter adapter, WGPUAdapterInfo * info) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUInstance wgpuAdapterGetInstance(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuAdapterGetLimits(WGPUAdapter adapter, WGPUSupportedLimits * limits) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBool wgpuAdapterHasFeature(WGPUAdapter adapter, WGPUFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuAdapterRequestDevice(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * descriptor, WGPURequestDeviceCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuAdapterRequestDevice2(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * options, WGPURequestDeviceCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuAdapterRequestDeviceF(WGPUAdapter adapter, WGPU_NULLABLE WGPUDeviceDescriptor const * options, WGPURequestDeviceCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuAdapterAddRef(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuAdapterRelease(WGPUAdapter adapter) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of BindGroup -WGPU_EXPORT void wgpuBindGroupSetLabel(WGPUBindGroup bindGroup, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBindGroupAddRef(WGPUBindGroup bindGroup) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBindGroupRelease(WGPUBindGroup bindGroup) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of BindGroupLayout -WGPU_EXPORT void wgpuBindGroupLayoutSetLabel(WGPUBindGroupLayout bindGroupLayout, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBindGroupLayoutAddRef(WGPUBindGroupLayout bindGroupLayout) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBindGroupLayoutRelease(WGPUBindGroupLayout bindGroupLayout) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Buffer -WGPU_EXPORT void wgpuBufferDestroy(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void const * wgpuBufferGetConstMappedRange(WGPUBuffer buffer, size_t offset, size_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBufferMapState wgpuBufferGetMapState(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void * wgpuBufferGetMappedRange(WGPUBuffer buffer, size_t offset, size_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint64_t wgpuBufferGetSize(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBufferUsage wgpuBufferGetUsage(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBufferMapAsync(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuBufferMapAsync2(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuBufferMapAsyncF(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBufferSetLabel(WGPUBuffer buffer, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBufferUnmap(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBufferAddRef(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuBufferRelease(WGPUBuffer buffer) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of CommandBuffer -WGPU_EXPORT void wgpuCommandBufferSetLabel(WGPUCommandBuffer commandBuffer, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandBufferAddRef(WGPUCommandBuffer commandBuffer) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandBufferRelease(WGPUCommandBuffer commandBuffer) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of CommandEncoder -WGPU_EXPORT WGPUComputePassEncoder wgpuCommandEncoderBeginComputePass(WGPUCommandEncoder commandEncoder, WGPU_NULLABLE WGPUComputePassDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPURenderPassEncoder wgpuCommandEncoderBeginRenderPass(WGPUCommandEncoder commandEncoder, WGPURenderPassDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderClearBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderCopyBufferToBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer source, uint64_t sourceOffset, WGPUBuffer destination, uint64_t destinationOffset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderCopyBufferToTexture(WGPUCommandEncoder commandEncoder, WGPUImageCopyBuffer const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderCopyTextureToBuffer(WGPUCommandEncoder commandEncoder, WGPUImageCopyTexture const * source, WGPUImageCopyBuffer const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderCopyTextureToTexture(WGPUCommandEncoder commandEncoder, WGPUImageCopyTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUCommandBuffer wgpuCommandEncoderFinish(WGPUCommandEncoder commandEncoder, WGPU_NULLABLE WGPUCommandBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderInjectValidationError(WGPUCommandEncoder commandEncoder, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderInsertDebugMarker(WGPUCommandEncoder commandEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderPopDebugGroup(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderPushDebugGroup(WGPUCommandEncoder commandEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderResolveQuerySet(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t firstQuery, uint32_t queryCount, WGPUBuffer destination, uint64_t destinationOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderSetLabel(WGPUCommandEncoder commandEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderWriteBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t bufferOffset, uint8_t const * data, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderWriteTimestamp(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderAddRef(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuCommandEncoderRelease(WGPUCommandEncoder commandEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of ComputePassEncoder -WGPU_EXPORT void wgpuComputePassEncoderDispatchWorkgroups(WGPUComputePassEncoder computePassEncoder, uint32_t workgroupCountX, uint32_t workgroupCountY, uint32_t workgroupCountZ) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderDispatchWorkgroupsIndirect(WGPUComputePassEncoder computePassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderEnd(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderInsertDebugMarker(WGPUComputePassEncoder computePassEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderPopDebugGroup(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderPushDebugGroup(WGPUComputePassEncoder computePassEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderSetBindGroup(WGPUComputePassEncoder computePassEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderSetLabel(WGPUComputePassEncoder computePassEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderSetPipeline(WGPUComputePassEncoder computePassEncoder, WGPUComputePipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderWriteTimestamp(WGPUComputePassEncoder computePassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderAddRef(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePassEncoderRelease(WGPUComputePassEncoder computePassEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of ComputePipeline -WGPU_EXPORT WGPUBindGroupLayout wgpuComputePipelineGetBindGroupLayout(WGPUComputePipeline computePipeline, uint32_t groupIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePipelineSetLabel(WGPUComputePipeline computePipeline, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePipelineAddRef(WGPUComputePipeline computePipeline) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuComputePipelineRelease(WGPUComputePipeline computePipeline) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Device -WGPU_EXPORT WGPUBindGroup wgpuDeviceCreateBindGroup(WGPUDevice device, WGPUBindGroupDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBindGroupLayout wgpuDeviceCreateBindGroupLayout(WGPUDevice device, WGPUBindGroupLayoutDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBuffer wgpuDeviceCreateBuffer(WGPUDevice device, WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUCommandEncoder wgpuDeviceCreateCommandEncoder(WGPUDevice device, WGPU_NULLABLE WGPUCommandEncoderDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUComputePipeline wgpuDeviceCreateComputePipeline(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceCreateComputePipelineAsync(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDeviceCreateComputePipelineAsync2(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDeviceCreateComputePipelineAsyncF(WGPUDevice device, WGPUComputePipelineDescriptor const * descriptor, WGPUCreateComputePipelineAsyncCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBuffer wgpuDeviceCreateErrorBuffer(WGPUDevice device, WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUExternalTexture wgpuDeviceCreateErrorExternalTexture(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUShaderModule wgpuDeviceCreateErrorShaderModule(WGPUDevice device, WGPUShaderModuleDescriptor const * descriptor, WGPUStringView errorMessage) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTexture wgpuDeviceCreateErrorTexture(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUExternalTexture wgpuDeviceCreateExternalTexture(WGPUDevice device, WGPUExternalTextureDescriptor const * externalTextureDescriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUPipelineLayout wgpuDeviceCreatePipelineLayout(WGPUDevice device, WGPUPipelineLayoutDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUQuerySet wgpuDeviceCreateQuerySet(WGPUDevice device, WGPUQuerySetDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPURenderBundleEncoder wgpuDeviceCreateRenderBundleEncoder(WGPUDevice device, WGPURenderBundleEncoderDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPURenderPipeline wgpuDeviceCreateRenderPipeline(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceCreateRenderPipelineAsync(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDeviceCreateRenderPipelineAsync2(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDeviceCreateRenderPipelineAsyncF(WGPUDevice device, WGPURenderPipelineDescriptor const * descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUSampler wgpuDeviceCreateSampler(WGPUDevice device, WGPU_NULLABLE WGPUSamplerDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUShaderModule wgpuDeviceCreateShaderModule(WGPUDevice device, WGPUShaderModuleDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTexture wgpuDeviceCreateTexture(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceDestroy(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceForceLoss(WGPUDevice device, WGPUDeviceLostReason type, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuDeviceGetAHardwareBufferProperties(WGPUDevice device, void * handle, WGPUAHardwareBufferProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUAdapter wgpuDeviceGetAdapter(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuDeviceGetAdapterInfo(WGPUDevice device, WGPUAdapterInfo * adapterInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceGetFeatures(WGPUDevice device, WGPUSupportedFeatures * features) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuDeviceGetLimits(WGPUDevice device, WGPUSupportedLimits * limits) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDeviceGetLostFuture(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUQueue wgpuDeviceGetQueue(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBool wgpuDeviceHasFeature(WGPUDevice device, WGPUFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUSharedBufferMemory wgpuDeviceImportSharedBufferMemory(WGPUDevice device, WGPUSharedBufferMemoryDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUSharedFence wgpuDeviceImportSharedFence(WGPUDevice device, WGPUSharedFenceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUSharedTextureMemory wgpuDeviceImportSharedTextureMemory(WGPUDevice device, WGPUSharedTextureMemoryDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceInjectError(WGPUDevice device, WGPUErrorType type, WGPUStringView message) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDevicePopErrorScope(WGPUDevice device, WGPUErrorCallback oldCallback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDevicePopErrorScope2(WGPUDevice device, WGPUPopErrorScopeCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuDevicePopErrorScopeF(WGPUDevice device, WGPUPopErrorScopeCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDevicePushErrorScope(WGPUDevice device, WGPUErrorFilter filter) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceSetLabel(WGPUDevice device, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceSetLoggingCallback(WGPUDevice device, WGPULoggingCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceTick(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceValidateTextureDescriptor(WGPUDevice device, WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceAddRef(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuDeviceRelease(WGPUDevice device) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of ExternalTexture -WGPU_EXPORT void wgpuExternalTextureDestroy(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuExternalTextureExpire(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuExternalTextureRefresh(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuExternalTextureSetLabel(WGPUExternalTexture externalTexture, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuExternalTextureAddRef(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuExternalTextureRelease(WGPUExternalTexture externalTexture) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Instance -WGPU_EXPORT WGPUSurface wgpuInstanceCreateSurface(WGPUInstance instance, WGPUSurfaceDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT size_t wgpuInstanceEnumerateWGSLLanguageFeatures(WGPUInstance instance, WGPUWGSLFeatureName * features) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBool wgpuInstanceHasWGSLLanguageFeature(WGPUInstance instance, WGPUWGSLFeatureName feature) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuInstanceProcessEvents(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuInstanceRequestAdapter(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuInstanceRequestAdapter2(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuInstanceRequestAdapterF(WGPUInstance instance, WGPU_NULLABLE WGPURequestAdapterOptions const * options, WGPURequestAdapterCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUWaitStatus wgpuInstanceWaitAny(WGPUInstance instance, size_t futureCount, WGPUFutureWaitInfo * futures, uint64_t timeoutNS) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuInstanceAddRef(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuInstanceRelease(WGPUInstance instance) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of PipelineLayout -WGPU_EXPORT void wgpuPipelineLayoutSetLabel(WGPUPipelineLayout pipelineLayout, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuPipelineLayoutAddRef(WGPUPipelineLayout pipelineLayout) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuPipelineLayoutRelease(WGPUPipelineLayout pipelineLayout) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of QuerySet -WGPU_EXPORT void wgpuQuerySetDestroy(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuQuerySetGetCount(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUQueryType wgpuQuerySetGetType(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQuerySetSetLabel(WGPUQuerySet querySet, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQuerySetAddRef(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQuerySetRelease(WGPUQuerySet querySet) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Queue -WGPU_EXPORT void wgpuQueueCopyExternalTextureForBrowser(WGPUQueue queue, WGPUImageCopyExternalTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize, WGPUCopyTextureForBrowserOptions const * options) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueCopyTextureForBrowser(WGPUQueue queue, WGPUImageCopyTexture const * source, WGPUImageCopyTexture const * destination, WGPUExtent3D const * copySize, WGPUCopyTextureForBrowserOptions const * options) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueOnSubmittedWorkDone(WGPUQueue queue, WGPUQueueWorkDoneCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuQueueOnSubmittedWorkDone2(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuQueueOnSubmittedWorkDoneF(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueSetLabel(WGPUQueue queue, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueSubmit(WGPUQueue queue, size_t commandCount, WGPUCommandBuffer const * commands) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueWriteBuffer(WGPUQueue queue, WGPUBuffer buffer, uint64_t bufferOffset, void const * data, size_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueWriteTexture(WGPUQueue queue, WGPUImageCopyTexture const * destination, void const * data, size_t dataSize, WGPUTextureDataLayout const * dataLayout, WGPUExtent3D const * writeSize) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueAddRef(WGPUQueue queue) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuQueueRelease(WGPUQueue queue) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of RenderBundle -WGPU_EXPORT void wgpuRenderBundleSetLabel(WGPURenderBundle renderBundle, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleAddRef(WGPURenderBundle renderBundle) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleRelease(WGPURenderBundle renderBundle) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of RenderBundleEncoder -WGPU_EXPORT void wgpuRenderBundleEncoderDraw(WGPURenderBundleEncoder renderBundleEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderDrawIndexed(WGPURenderBundleEncoder renderBundleEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderDrawIndexedIndirect(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderDrawIndirect(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPURenderBundle wgpuRenderBundleEncoderFinish(WGPURenderBundleEncoder renderBundleEncoder, WGPU_NULLABLE WGPURenderBundleDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderInsertDebugMarker(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderPopDebugGroup(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderPushDebugGroup(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderSetBindGroup(WGPURenderBundleEncoder renderBundleEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderSetIndexBuffer(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderSetLabel(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderSetPipeline(WGPURenderBundleEncoder renderBundleEncoder, WGPURenderPipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderSetVertexBuffer(WGPURenderBundleEncoder renderBundleEncoder, uint32_t slot, WGPU_NULLABLE WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderAddRef(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderBundleEncoderRelease(WGPURenderBundleEncoder renderBundleEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of RenderPassEncoder -WGPU_EXPORT void wgpuRenderPassEncoderBeginOcclusionQuery(WGPURenderPassEncoder renderPassEncoder, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderDraw(WGPURenderPassEncoder renderPassEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderDrawIndexed(WGPURenderPassEncoder renderPassEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderDrawIndexedIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderDrawIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderEnd(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderEndOcclusionQuery(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderExecuteBundles(WGPURenderPassEncoder renderPassEncoder, size_t bundleCount, WGPURenderBundle const * bundles) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderInsertDebugMarker(WGPURenderPassEncoder renderPassEncoder, WGPUStringView markerLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderMultiDrawIndexedIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPU_NULLABLE WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderMultiDrawIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPU_NULLABLE WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderPixelLocalStorageBarrier(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderPopDebugGroup(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderPushDebugGroup(WGPURenderPassEncoder renderPassEncoder, WGPUStringView groupLabel) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetBindGroup(WGPURenderPassEncoder renderPassEncoder, uint32_t groupIndex, WGPU_NULLABLE WGPUBindGroup group, size_t dynamicOffsetCount, uint32_t const * dynamicOffsets) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetBlendConstant(WGPURenderPassEncoder renderPassEncoder, WGPUColor const * color) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetIndexBuffer(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetLabel(WGPURenderPassEncoder renderPassEncoder, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetPipeline(WGPURenderPassEncoder renderPassEncoder, WGPURenderPipeline pipeline) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetScissorRect(WGPURenderPassEncoder renderPassEncoder, uint32_t x, uint32_t y, uint32_t width, uint32_t height) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetStencilReference(WGPURenderPassEncoder renderPassEncoder, uint32_t reference) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetVertexBuffer(WGPURenderPassEncoder renderPassEncoder, uint32_t slot, WGPU_NULLABLE WGPUBuffer buffer, uint64_t offset, uint64_t size) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderSetViewport(WGPURenderPassEncoder renderPassEncoder, float x, float y, float width, float height, float minDepth, float maxDepth) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderWriteTimestamp(WGPURenderPassEncoder renderPassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderAddRef(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPassEncoderRelease(WGPURenderPassEncoder renderPassEncoder) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of RenderPipeline -WGPU_EXPORT WGPUBindGroupLayout wgpuRenderPipelineGetBindGroupLayout(WGPURenderPipeline renderPipeline, uint32_t groupIndex) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPipelineSetLabel(WGPURenderPipeline renderPipeline, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPipelineAddRef(WGPURenderPipeline renderPipeline) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuRenderPipelineRelease(WGPURenderPipeline renderPipeline) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Sampler -WGPU_EXPORT void wgpuSamplerSetLabel(WGPUSampler sampler, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSamplerAddRef(WGPUSampler sampler) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSamplerRelease(WGPUSampler sampler) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of ShaderModule -WGPU_EXPORT void wgpuShaderModuleGetCompilationInfo(WGPUShaderModule shaderModule, WGPUCompilationInfoCallback callback, void * userdata) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuShaderModuleGetCompilationInfo2(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo2 callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUFuture wgpuShaderModuleGetCompilationInfoF(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo callbackInfo) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuShaderModuleSetLabel(WGPUShaderModule shaderModule, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuShaderModuleAddRef(WGPUShaderModule shaderModule) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuShaderModuleRelease(WGPUShaderModule shaderModule) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of SharedBufferMemory -WGPU_EXPORT WGPUStatus wgpuSharedBufferMemoryBeginAccess(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, WGPUSharedBufferMemoryBeginAccessDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBuffer wgpuSharedBufferMemoryCreateBuffer(WGPUSharedBufferMemory sharedBufferMemory, WGPU_NULLABLE WGPUBufferDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuSharedBufferMemoryEndAccess(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, WGPUSharedBufferMemoryEndAccessState * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuSharedBufferMemoryGetProperties(WGPUSharedBufferMemory sharedBufferMemory, WGPUSharedBufferMemoryProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBool wgpuSharedBufferMemoryIsDeviceLost(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedBufferMemorySetLabel(WGPUSharedBufferMemory sharedBufferMemory, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedBufferMemoryAddRef(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedBufferMemoryRelease(WGPUSharedBufferMemory sharedBufferMemory) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of SharedFence -WGPU_EXPORT void wgpuSharedFenceExportInfo(WGPUSharedFence sharedFence, WGPUSharedFenceExportInfo * info) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedFenceAddRef(WGPUSharedFence sharedFence) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedFenceRelease(WGPUSharedFence sharedFence) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of SharedTextureMemory -WGPU_EXPORT WGPUStatus wgpuSharedTextureMemoryBeginAccess(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, WGPUSharedTextureMemoryBeginAccessDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTexture wgpuSharedTextureMemoryCreateTexture(WGPUSharedTextureMemory sharedTextureMemory, WGPU_NULLABLE WGPUTextureDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuSharedTextureMemoryEndAccess(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, WGPUSharedTextureMemoryEndAccessState * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuSharedTextureMemoryGetProperties(WGPUSharedTextureMemory sharedTextureMemory, WGPUSharedTextureMemoryProperties * properties) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUBool wgpuSharedTextureMemoryIsDeviceLost(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedTextureMemorySetLabel(WGPUSharedTextureMemory sharedTextureMemory, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedTextureMemoryAddRef(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSharedTextureMemoryRelease(WGPUSharedTextureMemory sharedTextureMemory) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Surface -WGPU_EXPORT void wgpuSurfaceConfigure(WGPUSurface surface, WGPUSurfaceConfiguration const * config) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUStatus wgpuSurfaceGetCapabilities(WGPUSurface surface, WGPUAdapter adapter, WGPUSurfaceCapabilities * capabilities) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceGetCurrentTexture(WGPUSurface surface, WGPUSurfaceTexture * surfaceTexture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfacePresent(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceSetLabel(WGPUSurface surface, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceUnconfigure(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceAddRef(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuSurfaceRelease(WGPUSurface surface) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of Texture -WGPU_EXPORT WGPUTextureView wgpuTextureCreateErrorView(WGPUTexture texture, WGPU_NULLABLE WGPUTextureViewDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTextureView wgpuTextureCreateView(WGPUTexture texture, WGPU_NULLABLE WGPUTextureViewDescriptor const * descriptor) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureDestroy(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuTextureGetDepthOrArrayLayers(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTextureDimension wgpuTextureGetDimension(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTextureFormat wgpuTextureGetFormat(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuTextureGetHeight(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuTextureGetMipLevelCount(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuTextureGetSampleCount(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT WGPUTextureUsage wgpuTextureGetUsage(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT uint32_t wgpuTextureGetWidth(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureSetLabel(WGPUTexture texture, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureAddRef(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureRelease(WGPUTexture texture) WGPU_FUNCTION_ATTRIBUTE; - -// Methods of TextureView -WGPU_EXPORT void wgpuTextureViewSetLabel(WGPUTextureView textureView, WGPUStringView label) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureViewAddRef(WGPUTextureView textureView) WGPU_FUNCTION_ATTRIBUTE; -WGPU_EXPORT void wgpuTextureViewRelease(WGPUTextureView textureView) WGPU_FUNCTION_ATTRIBUTE; - - -#endif // !defined(WGPU_SKIP_DECLARATIONS) - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif // WEBGPU_H_ diff --git a/tinygrad/mkdocs.yml b/tinygrad/mkdocs.yml deleted file mode 100644 index d06f81c2..00000000 --- a/tinygrad/mkdocs.yml +++ /dev/null @@ -1,148 +0,0 @@ -# pip install mkdocs mkdocs-material mkdocstrings[python] -site_name: tinygrad docs -site_url: https://docs.tinygrad.org/ -repo_url: https://github.com/tinygrad/tinygrad/ -nav: -- Home: - - index.md - - Quickstart: quickstart.md - - Showcase: showcase.md - - MNIST Tutorial: mnist.md - - API Reference: - - Tensor: - - tensor/index.md - - Properties: tensor/properties.md - - Creation: tensor/creation.md - - Movement: tensor/movement.md - - Elementwise: tensor/elementwise.md - - Complex Ops: tensor/ops.md - - dtypes: dtypes.md - - nn (Neural Networks): nn.md - - Environment Variables: env_vars.md - - Runtime: runtime.md - - Developer: - - Intro: developer/developer.md - - Speed: developer/speed.md - - UOp: developer/uop.md - - Grouper: - - developer/kernelize.md - - Runtime: - - developer/runtime.md - - HCQ: developer/hcq.md - - AM Driver: developer/am.md - - tinybox: tinybox.md -#- tinygrad: reference/ - -#extra_css: -#- css/tinygrad.css - -validation: - links: - anchors: warn - -markdown_extensions: -- attr_list -- admonition -- callouts -- footnotes -- pymdownx.details -- pymdownx.emoji: - emoji_index: !!python/name:material.extensions.emoji.twemoji - emoji_generator: !!python/name:material.extensions.emoji.to_svg -- pymdownx.highlight: - pygments_lang_class: true -- pymdownx.inlinehilite: - style_plain_text: python -- pymdownx.magiclink -- pymdownx.snippets: - base_path: [!relative $config_dir] - check_paths: true -- pymdownx.superfences -- pymdownx.tabbed: - alternate_style: true - slugify: !!python/object/apply:pymdownx.slugs.slugify - kwds: - case: lower -- pymdownx.tasklist: - custom_checkbox: true -- pymdownx.tilde -- toc: - permalink: "¤" - -theme: - name: material - logo: logo_tiny_dark.svg - favicon: favicon.svg - features: - - announce.dismiss - - content.action.edit - - content.action.view - - content.code.annotate - - content.code.copy - - content.tooltips - - navigation.footer - - navigation.indexes - - navigation.sections - - navigation.expand - - navigation.top - - navigation.path - - search.highlight - - search.suggest - - toc.follow - - toc.integrate - palette: - scheme: slate - primary: black - accent: lime - palette: - - media: "(prefers-color-scheme)" - accent: lime - primary: black - toggle: - icon: material/brightness-auto - name: Switch to light mode - - media: "(prefers-color-scheme: light)" - scheme: default - accent: lime - primary: black - toggle: - icon: material/brightness-7 - name: Switch to dark mode - - media: "(prefers-color-scheme: dark)" - scheme: slate - accent: lime - primary: black - toggle: - icon: material/brightness-4 - name: Switch to system preference -plugins: -- search -- mkdocstrings: - handlers: - python: - import: - - https://docs.python.org/3/objects.inv - paths: [tinygrad] - options: - docstring_options: - ignore_init_summary: true - docstring_section_style: list - filters: ["!^_"] - heading_level: 3 - inherited_members: false - merge_init_into_class: true - separate_signature: true - show_root_heading: true - show_root_full_path: false - show_signature_annotations: true - show_symbol_type_heading: true - show_symbol_type_toc: true - show_source: true - signature_crossrefs: true - summary: true -- markdown-exec -#- gen-files: -# scripts: -# - docs/gen_ref_pages.py -#- literate-nav: -# nav_file: SUMMARY.md diff --git a/tinygrad/mypy.ini b/tinygrad/mypy.ini deleted file mode 100644 index 8a838bd2..00000000 --- a/tinygrad/mypy.ini +++ /dev/null @@ -1,10 +0,0 @@ -[mypy] -warn_unused_configs = True -files = tinygrad -ignore_missing_imports = True -check_untyped_defs = True -explicit_package_bases = True -warn_unreachable = True -warn_redundant_casts = True -# NOTE: had to comment this out to make mypy pass on both CI and OSX -#warn_unused_ignores = True diff --git a/tinygrad/ruff.toml b/tinygrad/ruff.toml deleted file mode 100644 index ac3ee495..00000000 --- a/tinygrad/ruff.toml +++ /dev/null @@ -1,44 +0,0 @@ -indent-width = 2 -preview = true -target-version = "py310" - -lint.select = [ - "F", # Pyflakes - "W6", - "E71", - "E72", - "E112", # no-indented-block - "E113", # unexpected-indentation - # "E124", - "E203", # whitespace-before-punctuation - "E272", # multiple-spaces-before-keyword - "E275", # missing-whitespace-after-keyword - "E303", # too-many-blank-lines - "E304", # blank-line-after-decorator - "E501", # line-too-long - # "E502", - "E702", # multiple-statements-on-one-line-semicolon - "E703", # useless-semicolon - "E731", # lambda-assignment - "W191", # tab-indentation - "W291", # trailing-whitespace - "W293", # blank-line-with-whitespace - "UP039", # unnecessary-class-parentheses - "C416", # unnecessary-comprehension - "RET506", # superfluous-else-raise - "RET507", # superfluous-else-continue - "A", # builtin-variable-shadowing, builtin-argument-shadowing, builtin-attribute-shadowing - "FURB110",# if-exp-instead-of-or-operator - "RUF018", # assignment-in-assert -] - -line-length = 150 - -exclude = [ - "docs/", - "examples/", - "extra/", - "tinygrad/runtime/autogen", - "test/external/mlperf_resnet", - "test/external/mlperf_unet3d", -] diff --git a/tinygrad/serve_docs.sh b/tinygrad/serve_docs.sh deleted file mode 100755 index e35dd82f..00000000 --- a/tinygrad/serve_docs.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/bash -mkdocs serve -w tinygrad/ diff --git a/tinygrad/setup.py b/tinygrad/setup.py deleted file mode 100644 index 9765ed31..00000000 --- a/tinygrad/setup.py +++ /dev/null @@ -1,89 +0,0 @@ -#!/usr/bin/env python3 - -from pathlib import Path -from setuptools import setup - -directory = Path(__file__).resolve().parent -with open(directory / 'README.md', encoding='utf-8') as f: - long_description = f.read() - -testing_minimal = [ - "numpy", - "torch", - "pytest", - "pytest-xdist", - "hypothesis", - "z3-solver", - "ml_dtypes" -] - -setup(name='tinygrad', - version='0.10.3', - description='You like pytorch? You like micrograd? You love tinygrad! <3', - author='George Hotz', - license='MIT', - long_description=long_description, - long_description_content_type='text/markdown', - packages = ['tinygrad', 'tinygrad.runtime.autogen', 'tinygrad.runtime.autogen.am', 'tinygrad.codegen', 'tinygrad.nn', - 'tinygrad.renderer', 'tinygrad.engine', 'tinygrad.viz', 'tinygrad.runtime', 'tinygrad.runtime.support', - 'tinygrad.runtime.support.am', 'tinygrad.runtime.graph', 'tinygrad.shape', 'tinygrad.uop'], - package_data = {'tinygrad': ['py.typed'], 'tinygrad.viz': ['index.html', 'perfetto.html', 'assets/**/*', 'js/*']}, - classifiers=[ - "Programming Language :: Python :: 3", - "License :: OSI Approved :: MIT License" - ], - install_requires=[], - python_requires='>=3.10', - extras_require={ - 'arm': ["unicorn"], - 'triton': ["triton-nightly>=2.1.0.dev20231014192330"], - 'linting': [ - "pylint", - "mypy==1.13.0", - "typing-extensions", - "pre-commit", - "ruff", - "numpy", - ], - #'mlperf': ["mlperf-logging @ git+https://github.com/mlperf/logging.git@5.0.0-rc3"], - 'testing_minimal': testing_minimal, - 'testing_unit': testing_minimal + [ - "tqdm", - "safetensors", - "tabulate", # for sz.py - ], - 'testing': testing_minimal + [ - "pillow", - "onnx==1.17.0", - "onnx2torch", - "onnxruntime", - "opencv-python", - "tabulate", - "tqdm", - "safetensors", - "transformers", - "sentencepiece", - "tiktoken", - "blobfile", - "librosa", - "networkx", - "nibabel", - "bottle", - "ggml-python", - "capstone", - "pycocotools", - "boto3", - "pandas", - "influxdb3-python" - ], - 'docs': [ - "mkdocs", - "mkdocs-material", - "mkdocstrings[python]", - "markdown-callouts", - "markdown-exec[ansi]", - "black", - "numpy", - ], - }, - include_package_data=True) diff --git a/tinygrad/sz.py b/tinygrad/sz.py deleted file mode 100755 index 3bd5abf5..00000000 --- a/tinygrad/sz.py +++ /dev/null @@ -1,84 +0,0 @@ -#!/usr/bin/env python3 -import os, sys -import token -import tokenize -import itertools -from tabulate import tabulate - -TOKEN_WHITELIST = [token.OP, token.NAME, token.NUMBER, token.STRING] - -def is_docstring(t): - return t.type == token.STRING and t.string.startswith('"""') and t.line.strip().startswith('"""') - -def is_js_token(s): return len(s) and not s.startswith('//') - -def gen_stats(base_path="."): - table = [] - for path, _, files in os.walk(os.path.join(base_path, "tinygrad")): - for name in files: - if not (name.endswith(".py") or name.endswith(".js")): continue - if any(s in path.replace('\\', '/') for s in ['tinygrad/runtime/autogen', 'tinygrad/viz/assets']): continue - filepath = os.path.join(path, name) - relfilepath = os.path.relpath(filepath, base_path).replace('\\', '/') - if name.endswith(".js"): - with open(filepath) as file_: lines = [line.strip() for line in file_.readlines()] - token_count, line_count = sum(len(line.split()) for line in lines if is_js_token(line)), sum(1 for line in lines if is_js_token(line)) - else: - with tokenize.open(filepath) as file_: - tokens = [t for t in tokenize.generate_tokens(file_.readline) if t.type in TOKEN_WHITELIST and not is_docstring(t)] - token_count, line_count = len(tokens), len(set([x for t in tokens for x in range(t.start[0], t.end[0]+1)])) - if line_count > 0: table.append([relfilepath, line_count, token_count/line_count]) - return table - -def gen_diff(table_old, table_new): - table = [] - files_new = set([x[0] for x in table_new]) - files_old = set([x[0] for x in table_old]) - added, deleted, unchanged = files_new - files_old, files_old - files_new, files_new & files_old - if added: - for file in added: - file_stat = [stats for stats in table_new if file in stats] - table.append([file_stat[0][0], file_stat[0][1], file_stat[0][1]-0, file_stat[0][2], file_stat[0][2]-0]) - if deleted: - for file in deleted: - file_stat = [stats for stats in table_old if file in stats] - table.append([file_stat[0][0], 0, 0 - file_stat[0][1], 0, 0-file_stat[0][2]]) - if unchanged: - for file in unchanged: - file_stat_old = [stats for stats in table_old if file in stats] - file_stat_new = [stats for stats in table_new if file in stats] - if file_stat_new[0][1]-file_stat_old[0][1] != 0 or file_stat_new[0][2]-file_stat_old[0][2] != 0: - table.append([file_stat_new[0][0], file_stat_new[0][1], file_stat_new[0][1]-file_stat_old[0][1], file_stat_new[0][2], - file_stat_new[0][2]-file_stat_old[0][2]]) - return table - -def display_diff(diff): return "+"+str(diff) if diff > 0 else str(diff) - -if __name__ == "__main__": - if len(sys.argv) == 3: - headers = ["Name", "Lines", "Diff", "Tokens/Line", "Diff"] - table = gen_diff(gen_stats(sys.argv[1]), gen_stats(sys.argv[2])) - elif len(sys.argv) == 2: - headers = ["Name", "Lines", "Tokens/Line"] - table = gen_stats(sys.argv[1]) - else: - headers = ["Name", "Lines", "Tokens/Line"] - table = gen_stats(".") - - if table: - if len(sys.argv) == 3: - print("### Changes") - print("```") - print(tabulate([headers] + sorted(table, key=lambda x: -x[1]), headers="firstrow", intfmt=(..., "d", "+d"), - floatfmt=(..., ..., ..., ".1f", "+.1f"))+"\n") - print(f"\ntotal lines changes: {display_diff(sum([x[2] for x in table]))}") - print("```") - else: - print(tabulate([headers] + sorted(table, key=lambda x: -x[1]), headers="firstrow", floatfmt=".1f")+"\n") - groups = sorted([('/'.join(x[0].rsplit("/", 1)[0].split("/")[0:2]), x[1], x[2]) for x in table]) - for dir_name, group in itertools.groupby(groups, key=lambda x:x[0]): - print(f"{dir_name:30s} : {sum([x[1] for x in group]):6d}") - total_lines = sum([x[1] for x in table]) - print(f"\ntotal line count: {total_lines}") - max_line_count = int(os.getenv("MAX_LINE_COUNT", "-1")) - assert max_line_count == -1 or total_lines <= max_line_count, f"OVER {max_line_count} LINES" diff --git a/tinygrad/test/Dockerfile b/tinygrad/test/Dockerfile deleted file mode 100644 index 260a0b0b..00000000 --- a/tinygrad/test/Dockerfile +++ /dev/null @@ -1,12 +0,0 @@ -FROM ubuntu:22.04 - -# Install python3.10, and pip3 -RUN apt-get update && apt-get install -y --no-install-recommends \ - python3.10 \ - python3-pip \ - && rm -rf /var/lib/apt/lists/* - -# Install python dependencies -COPY . ./tinygrad -WORKDIR tinygrad -RUN pip install -e . diff --git a/tinygrad/test/__init__.py b/tinygrad/test/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/test/external/external_benchmark_am.py b/tinygrad/test/external/external_benchmark_am.py deleted file mode 100644 index 6ac8bbfd..00000000 --- a/tinygrad/test/external/external_benchmark_am.py +++ /dev/null @@ -1,9 +0,0 @@ -from tinygrad.helpers import Profiling -from tinygrad import Device - -if __name__ == "__main__": - am = Device["AMD"] - - # kfd is 0.55ms! - with Profiling("allocation 127.7mb"): - am.allocator.alloc(int(127.7*1024*1024)) diff --git a/tinygrad/test/external/external_benchmark_bert_matmuls.py b/tinygrad/test/external/external_benchmark_bert_matmuls.py deleted file mode 100644 index 4f64629b..00000000 --- a/tinygrad/test/external/external_benchmark_bert_matmuls.py +++ /dev/null @@ -1,18 +0,0 @@ -from tinygrad import Tensor, dtypes -dtypes.default_float = dtypes.float16 -from tinygrad.dtype import to_dtype -from tinygrad.helpers import getenv - -if __name__ == "__main__": - # matmuls in bert layers - BS = getenv("BS", 96//6) - acc_dtype = to_dtype(getenv("ACC_DTYPE", "half")) - tensors = [ - (Tensor.empty(BS, 512, 1024), Tensor.empty(1024, 1024).T), # linear to get qkv - (Tensor.empty(BS, 512, 16, 64).permute(0,2,1,3), Tensor.empty(BS, 512, 16, 64).permute(0,2,3,1)), # q@k - (Tensor.empty(BS, 16, 512, 512), Tensor.empty(BS, 512, 16, 64).permute(0,2,1,3)), # qk@v - ] - for t0, t1 in tensors: - print(f"{t0.shape=}, {t0.uop.st.real_strides()=}, {t1.shape=}, {t1.uop.st.real_strides()=}") - for _ in range(5): - t0.dot(t1, dtype=acc_dtype).realize() diff --git a/tinygrad/test/external/external_benchmark_bert_softmax.py b/tinygrad/test/external/external_benchmark_bert_softmax.py deleted file mode 100644 index 176e2061..00000000 --- a/tinygrad/test/external/external_benchmark_bert_softmax.py +++ /dev/null @@ -1,18 +0,0 @@ -from tinygrad import Tensor, dtypes, Context, GlobalCounters -dtypes.default_float = dtypes.float16 -from tinygrad.dtype import to_dtype -from tinygrad.helpers import getenv -from test.test_softmax_fusion import single_kernel_softmax - -if __name__ == "__main__": - # softmax in bert layers - BS = getenv("BS", 96//6) - acc_dtype = to_dtype(getenv("ACC_DTYPE", "half")) - t = Tensor.empty(BS, 16, 512, 512) - t.softmax(-1, dtype="half").realize() - - # test single kernel softmax - GlobalCounters.reset() - with Context(DONT_GROUP_REDUCES=1): - single_kernel_softmax(t, -1, acc_dtype).realize() - diff --git a/tinygrad/test/external/external_benchmark_disk_raw.py b/tinygrad/test/external/external_benchmark_disk_raw.py deleted file mode 100644 index 6566ae41..00000000 --- a/tinygrad/test/external/external_benchmark_disk_raw.py +++ /dev/null @@ -1,7 +0,0 @@ -import pathlib -from tinygrad import Tensor, Device, Context - -if __name__ == "__main__": - with Context(DEBUG=2): - disk_llama = Tensor(pathlib.Path("/raid/weights/LLaMA-3/8B/consolidated.00.pth")) - device_llama = disk_llama.to(Device.DEFAULT).realize() diff --git a/tinygrad/test/external/external_benchmark_hcopt.py b/tinygrad/test/external/external_benchmark_hcopt.py deleted file mode 100644 index c2ed276e..00000000 --- a/tinygrad/test/external/external_benchmark_hcopt.py +++ /dev/null @@ -1,43 +0,0 @@ -import random -from tinygrad.helpers import getenv -from tinygrad.engine.search import beam_search, bufs_from_lin -from tinygrad.codegen.heuristic import hand_coded_optimizations -from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer - -def optimize_kernel(k): - # TODO: update this - return hand_coded_optimizations(k) - -if __name__ == '__main__': - hcopt_wins = beam_wins = tie = 0 - hcopt_total = beam_total = 0.0 - - worlds = load_worlds(filter_reduce=False, filter_noimage=True, filter_novariable=False) - random.seed(0) - random.shuffle(worlds) - - for world in worlds[:500]: - k = ast_str_to_lin(world) - rawbufs = bufs_from_lin(k) - - k_hcopt = k.copy() - k_hcopt.apply_opts(optimize_kernel(k_hcopt)) - k_beam = beam_search(k.copy(), rawbufs, getenv("BEAM", 2)) - - disable_cache = bool(getenv("NOCACHE", 0)) - t_hcopt = time_linearizer(k_hcopt, rawbufs, allow_test_size=False, cnt=10, disable_cache=disable_cache, clear_l2=True) * 1e6 - t_beam = time_linearizer(k_beam, rawbufs, allow_test_size=False, cnt=10, disable_cache=disable_cache, clear_l2=True) * 1e6 - - if t_hcopt == t_beam: tie += 1 - elif t_hcopt < t_beam: hcopt_wins += 1 - else: beam_wins += 1 - hcopt_total += t_hcopt - beam_total += t_beam - - print(f"{t_hcopt=:5.2f} {k_hcopt.applied_opts=}") - print("") - print(f"{t_beam=:5.2f} {k_beam.applied_opts=}") - print("*"*20) - - print(f"{hcopt_wins=}, {beam_wins=}, {tie=}") - print(f"{hcopt_total=:.2f}, {beam_total=:.2f}") \ No newline at end of file diff --git a/tinygrad/test/external/external_benchmark_hip_compile.py b/tinygrad/test/external/external_benchmark_hip_compile.py deleted file mode 100644 index 2b1d4803..00000000 --- a/tinygrad/test/external/external_benchmark_hip_compile.py +++ /dev/null @@ -1,31 +0,0 @@ -import random, os -from tinygrad.helpers import Timing -from tinygrad.runtime.ops_hip import compile_hip, HIPDevice -from tinygrad.runtime.ops_gpu import compile_cl, CLDevice - -# OMP_NUM_THREADS=1 strace -tt -f -e trace=file python3 test/external/external_benchmark_hip_compile.py -# AMD_COMGR_REDIRECT_LOGS=stdout AMD_COMGR_EMIT_VERBOSE_LOGS=1 python3 test/external/external_benchmark_hip_compile.py - -# issue is in https://github.com/ROCm-Developer-Tools/clr/ - -if __name__ == "__main__": - HIPDevice() - CLDevice() - - # warmup - name = "none"+str(random.randint(0, 1000000)) - compile_cl.__wrapped__(f"void {name}() {{}}") - print("compile cl warmed up") - compile_hip.__wrapped__(f"void {name}() {{}}") - print("compile hip warmed up") - - print("**** benchmark ****") - name = "none"+str(random.randint(0, 1000000)) - # this uses AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, then it links the lib on the next step - with Timing("compile cl: "): compile_cl.__wrapped__(f"void {name}() {{}}") - # this uses AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, much slower - with Timing("compile hip: "): compile_hip.__wrapped__(f"void {name}() {{}}") - os._exit(0) - - - diff --git a/tinygrad/test/external/external_benchmark_keccak.py b/tinygrad/test/external/external_benchmark_keccak.py deleted file mode 100644 index 1365ca9b..00000000 --- a/tinygrad/test/external/external_benchmark_keccak.py +++ /dev/null @@ -1,20 +0,0 @@ -from tinygrad import Tensor, dtypes -from tinygrad.engine.jit import TinyJit -from tinygrad.helpers import Timing, getenv - -if __name__ == "__main__": - BS = getenv("BS", 2**14) - BLOCKSIZE = getenv("BLOCKSIZE", 4096) - HASHFN = getenv("HASHFN", "shake_128") - NRUNS = getenv("NRUNS", 5) - - @TinyJit - def hasher(data: Tensor): return data.keccak(HASHFN) - - t = Tensor.randn(BS, BLOCKSIZE, dtype=dtypes.uint8).realize() - ds_mib = t.nbytes() / 1024**2 - - print(f"--- benchmarking (hash: {HASHFN}, data size: {ds_mib} MiB, block size: {BLOCKSIZE} B, batch size: {BS})") - for i in range(NRUNS): - with Timing(f"run: {i+1}, elapsed time: ", (lambda et: f", throughput: {ds_mib / (et*1e-9):.2f} MiB/s")): - hasher(t).realize() diff --git a/tinygrad/test/external/external_benchmark_kernel_launch.py b/tinygrad/test/external/external_benchmark_kernel_launch.py deleted file mode 100644 index 5744ba09..00000000 --- a/tinygrad/test/external/external_benchmark_kernel_launch.py +++ /dev/null @@ -1,38 +0,0 @@ -import time -from tinygrad import Tensor, TinyJit, Device, Context -from tinygrad.helpers import Profiling, Timing, GlobalCounters - -# python3 test/test_speed_v_torch.py TestSpeed.test_add_a - -@TinyJit -def plus(a:Tensor, b:Tensor): return a+b - -if __name__ == "__main__": - a = Tensor([1]).realize() - b = Tensor([1]).realize() - for i in range(5): - with Timing(prefix=f"{i}:"): - c = plus(a,b) - Device[c.device].synchronize() - assert c.item() == 2 - for i in range(5): - st = time.perf_counter() - c = plus(a,b) - et = time.perf_counter() - st - Device[c.device].synchronize() - print(f"nosync {i}: {et*1e6:.2f} us") - for i in range(5): - st = time.perf_counter() - c = plus(a,b) - Device[c.device].synchronize() - et = time.perf_counter() - st - print(f"precise {i}: {et*1e6:.2f} us") - assert GlobalCounters.time_sum_s == 0 - with Context(DEBUG=2): - st = time.perf_counter() - c = plus(a,b) - Device[c.device].synchronize() - et = time.perf_counter() - st - print(f"kernel {GlobalCounters.time_sum_s*1e3:.2f} ms / full {et*1e3:.2f} ms -- {et/(GlobalCounters.time_sum_s+1e-12):.2f} x") - with Profiling(): - c = plus(a,b) diff --git a/tinygrad/test/external/external_benchmark_load_stable_diffusion.py b/tinygrad/test/external/external_benchmark_load_stable_diffusion.py deleted file mode 100644 index 6ee0d0a3..00000000 --- a/tinygrad/test/external/external_benchmark_load_stable_diffusion.py +++ /dev/null @@ -1,13 +0,0 @@ -from tinygrad.helpers import fetch, Timing -from tinygrad.device import Device -from tinygrad.nn.state import torch_load, load_state_dict -from examples.stable_diffusion import StableDiffusion - -# run "sudo purge" before testing on OS X to avoid the memory cache - -if __name__ == "__main__": - fn = fetch('https://huggingface.co/CompVis/stable-diffusion-v-1-4-original/resolve/main/sd-v1-4.ckpt', 'sd-v1-4.ckpt') - model = StableDiffusion() - with Timing(): - load_state_dict(model, torch_load(fn)['state_dict'], strict=False) - Device[Device.DEFAULT].synchronize() diff --git a/tinygrad/test/external/external_benchmark_multitensor_allreduce.py b/tinygrad/test/external/external_benchmark_multitensor_allreduce.py deleted file mode 100644 index e2fd001a..00000000 --- a/tinygrad/test/external/external_benchmark_multitensor_allreduce.py +++ /dev/null @@ -1,55 +0,0 @@ -from tinygrad import Tensor, Device, GlobalCounters, TinyJit, dtypes -from tinygrad.helpers import getenv, Context, RING, DEBUG - -def test(devs: list[str], N: int, iters:int = 10): - @TinyJit - def f(t: Tensor) -> Tensor: t.sum(0).realize() - - secs, gflops, gbs = 0, 0, 0 - for i in range(-3, iters): - t = Tensor.empty((len(devs), N)) - t = t.shard(devs, 0).realize() - GlobalCounters.reset() - f(t) - for d in devs: Device[d].synchronize() - - if i < 0: continue # warm up jit - i_secs = GlobalCounters.time_sum_s - i_gflops = GlobalCounters.global_ops/i_secs/10**9 - i_gbs = (N*4)/i_secs/10**9 - print(f"{'ring_allreduce' if RING >= 2 else 'naive_allreduce'} iter {i+1}/{iters}: {i_secs:.6f} sec {i_gflops:.2f} GFLOP/s {i_gbs:.2f} GB/s") - secs += i_secs - gflops += i_gflops - gbs += i_gbs - - return (gflops/iters, gbs/iters, secs/iters) - -def run(sz, n_gpus=6, iters=10, use_ring=False): - devs = tuple([f"{Device.DEFAULT}:{x}" for x in range(n_gpus)]) - N = sz // dtypes.float32.itemsize - with Context(RING=(2 if use_ring else 0), DEBUG=max(DEBUG.value, 2)): return test(devs, N, iters=iters) - -def main(): - ONLY_RING = getenv("ONLY_RING", 0) - n_gpus = getenv("GPUS", 6) - iters = getenv("ITERS", 10) - - if getenv("BENCHMARK_SPLIT"): - l, r = 0, 512 - while r - l > 1: - m = (l + r) // 2 - (ring_gflops, ring_gbs, ring_secs) = run(m * 1024 * 4, n_gpus=n_gpus, iters=100, use_ring=True) - (naive_gflops, naive_gbs, naive_secs) = run(m * 1024 * 4, n_gpus=n_gpus, iters=100, use_ring=False) - if ring_secs > naive_secs: l = m - else: r = m - print("Better split", r * 1024, "elements") - else: - sz = getenv("SZ", 1000) * 10**6 # size of data on each gpu - print(f"Using {sz/10**9:.2f} GB of numbers on each of {n_gpus} GPUs, {n_gpus*sz/10**9:.2f} GB total.") - (ring_gflops, ring_gbs, ring_secs) = run(sz, use_ring=True, n_gpus=n_gpus, iters=iters) - if not ONLY_RING: (naive_gflops, naive_gbs, naive_secs) = run(sz, use_ring=False, n_gpus=n_gpus, iters=iters) - print(f"Ring:\n {ring_secs:.6f} seconds/iter\n {ring_gflops:.2f} GFLOP/s\n {ring_gbs:.2f} GB/s") - if not ONLY_RING: print(f"Naive:\n {naive_secs:.6f} seconds/iter\n {naive_gflops:.2f} GFLOP/s\n {naive_gbs:.2f} GB/s") - -if __name__ == "__main__": - main() diff --git a/tinygrad/test/external/external_benchmark_openpilot.py b/tinygrad/test/external/external_benchmark_openpilot.py deleted file mode 100644 index de856b2f..00000000 --- a/tinygrad/test/external/external_benchmark_openpilot.py +++ /dev/null @@ -1,64 +0,0 @@ -import time, sys, hashlib -from pathlib import Path -from onnx.helper import tensor_dtype_to_np_dtype -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from tinygrad import Tensor, dtypes, TinyJit -from tinygrad.helpers import IMAGE, GlobalCounters, fetch, colored, getenv, trange -from tinygrad.tensor import _from_np_dtype -import numpy as np -from extra.bench_log import BenchEvent, WallTimeEvent - -OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx" - -if __name__ == "__main__": - onnx_model = onnx_load(onnx_path := fetch(OPENPILOT_MODEL)) - run_onnx = OnnxRunner(onnx_model) - - Tensor.manual_seed(100) - input_shapes = {inp.name:tuple(x.dim_value for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input} - input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input} - new_inputs = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in input_shapes.items()} - new_inputs_junk = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in input_shapes.items()} - new_inputs_junk_numpy = {k:v.numpy() for k,v in new_inputs_junk.items()} - - # benchmark - for _ in range(5): - GlobalCounters.reset() - st = time.perf_counter_ns() - ret = next(iter(run_onnx(new_inputs_junk).values())).cast(dtypes.float32).numpy() - print(f"unjitted: {(time.perf_counter_ns() - st)*1e-6:7.4f} ms") - - # NOTE: the inputs to a JIT must be first level arguments - run_onnx_jit = TinyJit(lambda **kwargs: run_onnx(kwargs), prune=True) - for _ in range(20): - GlobalCounters.reset() - st = time.perf_counter_ns() - with WallTimeEvent(BenchEvent.STEP): - # Need to cast non-image inputs from numpy, this is only realistic way to run model - inputs = {**{k:v for k,v in new_inputs_junk.items() if 'img' in k}, - **{k:Tensor(v) for k,v in new_inputs_junk_numpy.items() if 'img' not in k}} - ret = next(iter(run_onnx_jit(**inputs).values())).cast(dtypes.float32).numpy() - print(f"jitted: {(time.perf_counter_ns() - st)*1e-6:7.4f} ms") - - suffix = "" - if IMAGE.value < 2: suffix += f"_image{IMAGE.value}" # image=2 has no suffix for compatibility - if getenv("FLOAT16") == 1: suffix += "_float16" - path = Path(__file__).parent / "openpilot" / f"{hashlib.md5(OPENPILOT_MODEL.encode()).hexdigest()}{suffix}.npy" - - # validate if we have records - tinygrad_out = next(iter(run_onnx_jit(**new_inputs).values())).cast(dtypes.float32).numpy() - if getenv("SAVE_OUTPUT"): - np.save(path, tinygrad_out) - print(f"saved output to {path}!") - elif getenv("FUZZ") and path.exists(): - known_good_out = np.load(path) - for _ in trange(1000): - ret = next(iter(run_onnx_jit(**new_inputs).values())).cast(dtypes.float32).numpy() - np.testing.assert_allclose(known_good_out, ret, atol=1e-2, rtol=1e-2) - print(colored("fuzz validated!", "green")) - elif path.exists(): - known_good_out = np.load(path) - np.testing.assert_allclose(known_good_out, tinygrad_out, atol=1e-2, rtol=1e-2) - print(colored("outputs validated!", "green")) - else: - print(colored("skipping validation", "yellow")) diff --git a/tinygrad/test/external/external_benchmark_resnet.py b/tinygrad/test/external/external_benchmark_resnet.py deleted file mode 100644 index bef7cf63..00000000 --- a/tinygrad/test/external/external_benchmark_resnet.py +++ /dev/null @@ -1,127 +0,0 @@ -import functools -import time -import unittest - -from tinygrad import Tensor, TinyJit, GlobalCounters, Device -from tinygrad.helpers import getenv, Context -from tinygrad.nn.optim import SGD -from tinygrad.nn.state import get_parameters -from tinygrad.engine.realize import run_schedule - -from extra.models import resnet -from examples.mlperf.initializers import Conv2dHeNormal, Linear -from examples.hlb_cifar10 import UnsyncedBatchNorm - -# benchmark memory or kernel count: DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# benchmark speed: BEAM=2 JITCNT=10 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# benchmark only one layer: BEAM=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py BenchmarkResnetTrain.test_layer1_2 -# inspect: DEBUG=2 BEAM=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# inspect 1x1 convs: DEBUG=2 BEAM=2 CONV=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# inspect 3x3 convs: DEBUG=2 BEAM=2 CONV=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# inspect 3x3 convs with batchnorm: DEBUG=2 BEAM=2 CONV=2 BN=1 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py -# etc - -# use ASSIGN=0 to disable batchnorm/optimizer assigns - -# memory will be slightly high with JITCNT > 1 - -bs = getenv("BS", 64) - -class BenchmarkResnetTrain(unittest.TestCase): - def _get_layer(self, layer_i, slice_i): - # isolate to conv, with or without BN - conv = getenv("CONV", 0) - bn = getenv("BN", 0) - - if not hasattr(self, 'model'): - resnet.Conv2d = Conv2dHeNormal - resnet.Linear = Linear - if not getenv("SYNCBN"): resnet.BatchNorm = functools.partial(UnsyncedBatchNorm, num_devices=1) - self.model = resnet.ResNet50() - self.layers = [self.model.layer1, self.model.layer2, self.model.layer3, self.model.layer4] - - layer = self.layers[layer_i][slice_i] - xy = 112 >> layer_i - xy >>= (1 if slice_i > 0 or layer_i == 0 else 0) # layer 1 is preceded by maxpool2d - name = f"layer{layer_i+1} slice{slice_i+1}" - - # get specific conv - if conv: - convs = [layer.conv1, layer.conv2, layer.conv3] + ([layer.downsample[0]] if layer.downsample else []) - bns = [layer.bn1, layer.bn2, layer.bn3] + ([layer.downsample[1]] if layer.downsample else []) - f = [convs[conv-1]] - if bn: f.append(bns[conv-1]) - f.append(Tensor.relu) - cin = f[0].in_channels - if conv == 3: xy //= convs[1].stride - return f"{name} conv{conv} x{str((bs, cin, xy, xy)):20s} k{str(f[0].weight.shape):20s}" + (" bn" if bn else ""), f, cin, xy - - cin = layer.conv1.in_channels - return f"{name} x{(bs, cin, xy, xy)}", [layer], cin, xy - def _test_layer(self, name, layer, cin, xy): - optim = SGD(get_parameters(layer), bs / 128 * 1.0) # need sgd for some params but not consequential for benchmarking - with Context(TRACK_MATCH_STATS=0): Tensor.realize(*[t.assign(t.detach().contiguous()) for t in get_parameters(optim)]) - - JITCNT = getenv("JITCNT", 1) - Tensor.training = True - @TinyJit - def step(x): - optim.zero_grad() - x.grad = None - - y = x.sequential(layer).contiguous().contiguous_backward() - y.sum().backward() - if getenv("ASSIGN", 1): sched, _ = Tensor.schedule_with_vars(y, x.grad, *optim.schedule_step()) - else: sched, _ = Tensor.schedule_with_vars(y, x.grad, *[t.grad for t in optim.params]) - - for _ in range(JITCNT): - run_schedule(list(sched)) - - CNT = getenv("CNT", 5) - best_tm = None - flops, mem_used, mem, kernels = None, None, None, None - for i in range(CNT): - with Context(TRACK_MATCH_STATS=0): x = Tensor.randn(bs, cin, xy, xy, requires_grad=True).realize() - GlobalCounters.reset() - - st = time.perf_counter() - step(x) - Device[Device.DEFAULT].synchronize() - et = time.perf_counter() - - flops = GlobalCounters.global_ops / JITCNT - mem_used = GlobalCounters.mem_used # a little high with JITCNT > 1 fsr - mem = GlobalCounters.global_mem / JITCNT - if kernels is None: kernels = GlobalCounters.kernel_count // JITCNT - tm = (et-st) / JITCNT - if best_tm is None or tm < best_tm: best_tm = tm - print(f"\r{name:38s}: {best_tm * 1000:>9.2f} ms, {flops / 10**12 / best_tm:>6.2f} tflops, {mem / 10**9 / best_tm:>5.0f} GB/s, " - f"{mem_used / 10**9: 6.2f} GB used, {kernels:>5d} kernels") - return best_tm, flops, mem, kernels - - def test_layer1_1(self): self._est(*self._test_layer(*self._get_layer(0, 0)), 1) - def test_layer1_2(self): self._est(*self._test_layer(*self._get_layer(0, 1)), 2) - def test_layer2_1(self): self._est(*self._test_layer(*self._get_layer(1, 0)), 1) - def test_layer2_2(self): self._est(*self._test_layer(*self._get_layer(1, 1)), 3) - def test_layer3_1(self): self._est(*self._test_layer(*self._get_layer(2, 0)), 1) - def test_layer3_2(self): self._est(*self._test_layer(*self._get_layer(2, 1)), 5) - def test_layer4_1(self): self._est(*self._test_layer(*self._get_layer(3, 0)), 1) - def test_layer4_2(self): self._est(*self._test_layer(*self._get_layer(3, 1)), 2) - - est_tm, est_flops, est_mem, est_kernels = 0, 0, 0, 0 - - @classmethod - def _est(cls, tm, flops, mem, kernels, mult): - cls.est_tm += tm * mult - cls.est_flops += flops * mult - cls.est_mem += mem * mult - cls.est_kernels += kernels * mult - - @classmethod - def tearDownClass(cls): - print(f"\restimated step tm: {cls.est_tm * 1000.0:.2f} ms, {cls.est_flops / 10 ** 12 / cls.est_tm:.3f} tflops, " - f"{cls.est_mem / 10 ** 9 / cls.est_tm:.2f} GB/s, {cls.est_kernels} kernels") - - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_benchmark_schedule.py b/tinygrad/test/external/external_benchmark_schedule.py deleted file mode 100644 index 89628ee8..00000000 --- a/tinygrad/test/external/external_benchmark_schedule.py +++ /dev/null @@ -1,59 +0,0 @@ -from typing import List -from extra.models.resnet import ResNet50 -from tinygrad import Tensor, nn -from tinygrad.helpers import Profiling, Timing, getenv, BEAM, NOOPT, DEBUG, Context, ansilen -from tinygrad.uop.ops import Ops -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.codegen import get_rewrites_for_renderer, apply_rewrites, rewrites_for_linearizer -from tinygrad.engine.search import beam_search, bufs_from_lin - -if __name__ == "__main__": - mdl = ResNet50() - for p in nn.state.get_parameters(mdl): p.replace(Tensor.empty(p.shape)) - img = Tensor.empty(64, 3, 224, 224) - - PROFILE = getenv("PYPROFILE", 0) - FORWARD_ONLY = getenv("FORWARD_ONLY", 0) - SCHEDULE_ONLY = getenv("SCHEDULE_ONLY", 0) - LINEARIZE = bool(getenv("LINEARIZE", 1)) - - with Timing("all "): - with Timing("***** model tensor in "): - out = mdl(img) - - if not FORWARD_ONLY: - with Timing("***** model schedule in "): - with Profiling(PROFILE >= 3): - sched = out.schedule() - - if not SCHEDULE_ONLY: - asts = list({x.ast.key:x.ast for x in sched if x.ast.op is Ops.SINK}.values()) - if (restrict_kernel := getenv("RESTRICT_KERNEL", -1)) != -1: asts = asts[restrict_kernel:restrict_kernel+1] - kernels: List[Kernel] = [] - with Timing(f"***** model opts({len(asts):2d}) in "): - with Profiling(PROFILE >= 3): - for ast in asts: - k = Kernel(ast) - if BEAM: - with Context(DEBUG=max(2, DEBUG.value)): k = beam_search(k, bufs_from_lin(k), BEAM.value) - elif NOOPT: pass - else: k.apply_opts(hand_coded_optimizations(k)) - kernels.append(k) - - with Timing("***** model prep in "): - kernels = [(k, k.get_optimized_ast(), get_rewrites_for_renderer(k.opts, linearizer=False)) for k in kernels] - - with Profiling(PROFILE, fn="/tmp/rewrite.prof"): - with Timing("***** model rewrite in "): - rewritten_uops = [] - for i,(k,u,rewrites) in enumerate(kernels): - with Timing(f"rewrite {i:2d} {k.name}{' '*(50-ansilen(k.name))}", enabled=getenv("VERBOSE", 0)): - rewritten_uops.append(apply_rewrites(u, rewrites)) - - if LINEARIZE: - with Timing("***** model linearize in "): - uops_line = [] - for u in rewritten_uops: - uops_line.append(apply_rewrites(u, rewrites_for_linearizer)) - print(sum(len(u.arg.lst) for u in uops_line)) diff --git a/tinygrad/test/external/external_benchmark_sdxl_softmax.py b/tinygrad/test/external/external_benchmark_sdxl_softmax.py deleted file mode 100644 index 35cf06b0..00000000 --- a/tinygrad/test/external/external_benchmark_sdxl_softmax.py +++ /dev/null @@ -1,27 +0,0 @@ -from tinygrad import Tensor, dtypes, GlobalCounters - -if __name__ == "__main__": - t = Tensor.empty(81920, 4096, dtype=dtypes.half) - GlobalCounters.reset() - t.softmax(-1, dtype="half").realize() - GlobalCounters.reset() - t.softmax(-1, dtype="half", _single_kernel=True).realize() - - from tinygrad.codegen.kernel import Kernel, Opt, OptOps - from tinygrad.helpers import get_single_element - GlobalCounters.reset() - si = get_single_element(t.softmax(-1, dtype="half", _single_kernel=True).schedule()) - k = Kernel(si.ast) - #k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) - k.apply_opt(Opt(OptOps.LOCAL, 1, 32)) - #k.apply_opt(Opt(OptOps.LOCAL, 0, 8)) - k.apply_opt(Opt(OptOps.UNROLL, 1, 4)) - k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) - #k.apply_opt(Opt(OptOps.GROUP, 1, 256)) - #k.apply_opt(Opt(OptOps.GROUP, 0, 32)) - #k.apply_opt(Opt(OptOps.GROUP, 1, 32)) - #k.apply_opt(Opt(OptOps.GROUP, 0, 32)) - from tinygrad.engine.realize import CompiledRunner, ExecItem - run = CompiledRunner(prg:=k.to_program()) - ExecItem(run, si.bufs).run() diff --git a/tinygrad/test/external/external_cl_half_max.py b/tinygrad/test/external/external_cl_half_max.py deleted file mode 100644 index 7cd6b0c5..00000000 --- a/tinygrad/test/external/external_cl_half_max.py +++ /dev/null @@ -1,13 +0,0 @@ -from tinygrad.runtime.ops_gpu import CLDevice, CLProgram, compile_cl - -if __name__ == "__main__": - dev = CLDevice() - lib = compile_cl(""" -#pragma OPENCL EXTENSION cl_khr_fp16 : enable -__kernel void test(__global half *out, __global half *a, __global half *b) { - int gid = get_global_id(0); - out[gid] = max(a[gid], b[gid]); -} -""") - prg = CLProgram(dev, "test", lib) - diff --git a/tinygrad/test/external/external_debug_metal_sd_conv.py b/tinygrad/test/external/external_debug_metal_sd_conv.py deleted file mode 100644 index cbdd93f8..00000000 --- a/tinygrad/test/external/external_debug_metal_sd_conv.py +++ /dev/null @@ -1,46 +0,0 @@ -# ruff: noqa: E501 -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad.dtype import dtypes -from tinygrad.engine.realize import CompiledRunner -from tinygrad.engine.search import bufs_from_lin -from tinygrad.uop.ops import UOp, Ops -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 1, 1, 1), strides=(81920, 0, 64, 8, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 2, 1, 2560, 4, 10, 4, 10), strides=(0, 163840, 0, 64, 0, 8, 0, 1), offset=-9, mask=((0, 1), (0, 2), (0, 1), (0, 2560), (0, 4), (1, 9), (0, 4), (1, 9)), contiguous=False), View(shape=(2, 1, 1280, 8, 8, 2560, 3, 3), strides=(4096000, 0, 0, 40, 1, 1600, 440, 11), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 2560, 3, 3), strides=(0, 0, 23040, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=3, src=()), - x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=4, src=()), - x17,)),)),)),)) -opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=2, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=8), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.LOCAL, axis=2, arg=2)] - -k = Kernel(ast) -k.apply_opts(opts) -bufs = bufs_from_lin(k) - -prg = CompiledRunner(k.to_program()) - -for i in range(10): - speed = prg(bufs, var_vals={}, wait=True) - print(f"kernel time: {speed*1e3:.2f} ms") - -# on M1 Max -# 11ms before block 9b0859d71780fef5cf3831e317f74e53f2483229 -# 15ms after block cbcc1c20eb09a1342f6581cfbb99632bade982a8 \ No newline at end of file diff --git a/tinygrad/test/external/external_fuzz_am_interrupts.py b/tinygrad/test/external/external_fuzz_am_interrupts.py deleted file mode 100644 index 2ed57242..00000000 --- a/tinygrad/test/external/external_fuzz_am_interrupts.py +++ /dev/null @@ -1,39 +0,0 @@ -import subprocess -import random -import time -from concurrent.futures import ThreadPoolExecutor, as_completed - -def run_test(i, full_run=False): - print(f"\rRunning iteration {i}...", end=" ", flush=True) - - p = subprocess.Popen(['python3', 'test/test_tiny.py', 'TestTiny.test_plus'], stdout=subprocess.PIPE, stderr=subprocess.PIPE) - - if not full_run: - time.sleep(random.uniform(0, 1200) / 1000) - p.kill() - _, stderr = p.communicate() - else: - _, stderr = p.communicate() - - if full_run: - stderr_text = stderr.decode() - print(stderr_text) - assert "Ran 1 test in" in stderr_text and "OK" in stderr_text - -max_workers = 4 -with ThreadPoolExecutor(max_workers=max_workers) as executor: - futures = [] - for i in range(1000000): - if i % 100 == 0: - for future in as_completed(futures): - try: future.result() - except Exception as e: - print(f"\nError in iteration: {e}") - futures = [] - - run_test(i, True) - else: - future = executor.submit(run_test, i, False) - futures.append(future) - - if len(futures) > max_workers * 2: futures = [f for f in futures if not f.done()] \ No newline at end of file diff --git a/tinygrad/test/external/external_fuzz_ampt.py b/tinygrad/test/external/external_fuzz_ampt.py deleted file mode 100644 index 0a280aae..00000000 --- a/tinygrad/test/external/external_fuzz_ampt.py +++ /dev/null @@ -1,108 +0,0 @@ -import random -from tinygrad.helpers import round_up -from tinygrad.runtime.support.am.amdev import AMPageTableTraverseContext -from test.external.external_test_am import helper_read_entry_components, FakeAM - -class AMPTFuzzer: - def __init__(self, total_size): - self.total_size = total_size - self.alloc_payload = 0 - self.d = FakeAM() - - self.allocations: dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) - - self.min_alloc_size = 0x1000 - self.max_alloc_size = int(total_size * 0.1) - self.alloc_probability = 0.7 - - def generate_pattern(self, ptr: int, size: int) -> int: return random.randint(0, 0xff) - - def fill_memory(self, va, size: int, pattern: int): - ctx = AMPageTableTraverseContext(self.d, self.d.mm.root_page_table, va.va_addr) - pages = list(ctx.next(size)) - - for _offset, _pt, _pte_idx, _n_ptes, _pte_covers in pages: - _vaddr = va.va_addr + _offset - - for i in range(_n_ptes): - pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) - self.d.vram[pte['paddr']] = pattern # Mark this page - assert pte['valid'] == 1 - - # If page has contigous fragment, all range should be this valid memory - frags_cnt = pte['fragment'] - contig_range = (1 << (frags_cnt + 12)) - start_vaddr = _vaddr & ~(contig_range - 1) - start_paddr = pte['paddr'] - (_vaddr - start_vaddr) - contig_ptes = contig_range // _pte_covers - assert contig_ptes > 0 - - ctx = AMPageTableTraverseContext(self.d, self.d.mm.root_page_table, start_vaddr) - frags_l = list(ctx.next(contig_range)) - for f_offset, f_pt, f_pte_idx, f_n_ptes, f_pte_covers in frags_l: - for j in range(f_n_ptes): - f_pte = helper_read_entry_components(f_pt.entries[f_pte_idx + j]) - assert f_pte['valid'] == 1 - assert f_pte['paddr'] == start_paddr+f_offset+j*f_pte_covers, f"paddr {f_pte['paddr']:#x} not {start_paddr+f_offset+j*f_pte_covers:#x}" - - _vaddr += _pte_covers - _offset += _pte_covers - - return pages - - def verify_memory(self, pages, pattern: int) -> bool: - for _offset, _pt, _pte_idx, _n_ptes, _pte_covers in pages: - for i in range(_n_ptes): - pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) - if self.d.vram[pte['paddr']] != pattern: return False - if pte['valid'] == 0: return False - - return True - - def random_alloc(self): - if self.total_size - self.alloc_payload < self.min_alloc_size: return None - - size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) - size = round_up(size, (2 << 20) if size > (4 << 20) else (4 << 10)) - - try: ptr = self.d.mm.valloc(size) - except MemoryError: - print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") - return None - - pattern = self.generate_pattern(ptr, size) - pages = self.fill_memory(ptr, size, pattern) - self.allocations[ptr.va_addr] = (size, pattern, pages, ptr) - self.alloc_payload += size - print(f"Allocated {size} bytes at {ptr.va_addr:x}, pattern: {pattern:02x}") - return ptr - - def random_free(self) -> bool: - if not self.allocations: return False - - ptr = random.choice(list(self.allocations.keys())) - size, pattern, pages, vm = self.allocations[ptr] - - # Verify pattern before freeing - if not self.verify_memory(pages, pattern): - raise RuntimeError(f"Memory corruption detected at {vm.va_addr:x}!") - - print(f"Freeing {size} bytes at {vm.va_addr:x}, pattern verified: {pattern:02x}") - self.alloc_payload -= size - self.d.mm.vfree(vm) - del self.allocations[ptr] - return True - - def run(self): - for i in range(10000000): - if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() - else: self.random_free() - - print("\nCleaning up remaining allocations...") - while self.allocations: self.random_free() - - print("Fuzzing completed successfully!") - -if __name__ == "__main__": - fuzzer = AMPTFuzzer(1 << 30) - fuzzer.run() diff --git a/tinygrad/test/external/external_fuzz_hcq_signals.py b/tinygrad/test/external/external_fuzz_hcq_signals.py deleted file mode 100644 index cc667c79..00000000 --- a/tinygrad/test/external/external_fuzz_hcq_signals.py +++ /dev/null @@ -1,31 +0,0 @@ -import random -from tinygrad import Device -from tinygrad.helpers import getenv, DEBUG - -def main(): - seed = getenv("SEED", 1337) - n_gpus = getenv("GPUS", 3) - iters = getenv("ITERS", 10000000) - only_compute = bool(getenv("ONLY_COMPUTE", 0)) - - print(f"{n_gpus} GPUs for {iters} iterations, {only_compute=}, seed {seed}") - devs = tuple([Device[f"{Device.DEFAULT}:{x}"] for x in range(n_gpus)]) - - for i in range(iters): - dev = random.choice(devs) - q_t = random.choice([dev.hw_copy_queue_t, dev.hw_compute_queue_t] if not only_compute else [dev.hw_compute_queue_t]) - - deps_sigs = random.randint(0, len(devs)) - wait_devs = random.sample(devs, deps_sigs) - - q = q_t() - for d in wait_devs: q.wait(d.timeline_signal, d.timeline_value - 1) - q.wait(dev.timeline_signal, dev.timeline_value - 1).signal(dev.timeline_signal, dev.timeline_value).submit(dev) - dev.timeline_value += 1 - - if sync:=random.randint(0, 10) < 3: dev.synchronize() - if DEBUG >= 2: print(f"{i}: {q_t} {dev.device_id} timeline {dev.timeline_value}, wait for {[d.device_id for d in wait_devs]}, {sync=}") - elif i % 100 == 0: print(f"\rCompleted {i} iterations", end='') - -if __name__ == "__main__": - main() diff --git a/tinygrad/test/external/external_fuzz_tlsf.py b/tinygrad/test/external/external_fuzz_tlsf.py deleted file mode 100644 index 512ced0b..00000000 --- a/tinygrad/test/external/external_fuzz_tlsf.py +++ /dev/null @@ -1,79 +0,0 @@ -import random -from typing import Dict, Optional -from tinygrad.helpers import getenv -from tinygrad.runtime.support.allocator import TLSFAllocator - -class AllocatorFuzzer: - def __init__(self, total_size): - self.total_size = total_size - self.alloc_payload = 0 - self.mv = memoryview(bytearray(total_size)) - self.alloctor = TLSFAllocator(total_size, block_size=16) - - self.allocations: Dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) - - self.min_alloc_size = 16 - self.max_alloc_size = int(total_size * 0.3) - self.alloc_probability = 0.7 - - def generate_pattern(self, ptr: int, size: int) -> int: return (ptr * 31 + size * 17) & 0xFF - - def fill_memory(self, ptr: int, size: int, pattern: int): - for i in range(min(size, 32)): - self.mv[ptr + i] = pattern - self.mv[ptr + (size - 1 - i)] = pattern - - def verify_memory(self, ptr: int, size: int, pattern: int) -> bool: - for i in range(min(size, 32)): - assert self.mv[ptr + i] == pattern - assert self.mv[ptr + (size - 1 - i)] == pattern - return True - - def random_alloc(self) -> Optional[int]: - size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) - - try: - ptr = self.alloctor.alloc(size) - except MemoryError: - print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") - return None - - pattern = self.generate_pattern(ptr, size) - self.fill_memory(ptr, size, pattern) - self.allocations[ptr] = (size, pattern) - self.alloc_payload += size - print(f"Allocated {size} bytes at {ptr:x}, pattern: {pattern:02x}") - return ptr - - def random_free(self) -> bool: - if not self.allocations: return False - - ptr = random.choice(list(self.allocations.keys())) - size, pattern = self.allocations[ptr] - - # Verify pattern before freeing - if not self.verify_memory(ptr, size, pattern): - raise RuntimeError(f"Memory corruption detected at {ptr:x}!") - - print(f"Freeing {size} bytes at {ptr:x}, pattern verified: {pattern:02x}") - self.alloc_payload -= size - self.alloctor.free(ptr) - del self.allocations[ptr] - return True - - def run(self): - for i in range(getenv("ITERS", 100000)): - if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() - else: self.random_free() - - print("\nCleaning up remaining allocations...") - while self.allocations: self.random_free() - - print("Fuzzing completed successfully!") - -if __name__ == "__main__": - SEED = getenv("SEED", 42) - random.seed(SEED) - - fuzzer = AllocatorFuzzer(1 << 30) - fuzzer.run() diff --git a/tinygrad/test/external/external_gpu_fail_osx.py b/tinygrad/test/external/external_gpu_fail_osx.py deleted file mode 100644 index b11b695e..00000000 --- a/tinygrad/test/external/external_gpu_fail_osx.py +++ /dev/null @@ -1,16 +0,0 @@ -# ugh, OS X OpenCL doesn't support half -from tinygrad.runtime.ops_gpu import CLDevice, CLProgram, CLCompiler - -src = """#pragma OPENCL EXTENSION cl_khr_fp16 : enable -__kernel void max_half(__global half* data0, const __global half* data1) { - int gidx0 = get_group_id(0); - data0[gidx0] = max(data1[gidx0], (half)0.0); -}""" - -if __name__ == "__main__": - dev = CLDevice() - print("created device") - lib = CLCompiler(dev, "test").compile(src) - print("created lib", len(lib)) - prg = CLProgram(dev, "max_half", lib) - print("created prg") \ No newline at end of file diff --git a/tinygrad/test/external/external_hip_compiler_bug.py b/tinygrad/test/external/external_hip_compiler_bug.py deleted file mode 100644 index 9dfcf012..00000000 --- a/tinygrad/test/external/external_hip_compiler_bug.py +++ /dev/null @@ -1,225 +0,0 @@ -# [, , ] -from tinygrad import Device, dtypes -from tinygrad.device import Buffer, CompiledRunner - -import ctypes -import gpuctypes.hip as hip -from tinygrad.helpers import to_char_p_p, init_c_var -def get_bytes(arg, get_sz, get_str, check) -> bytes: return (sz := init_c_var(ctypes.c_size_t(), lambda x: check(get_sz(arg, ctypes.byref(x)))), ctypes.string_at(init_c_var(ctypes.create_string_buffer(sz.value), lambda x: check(get_str(arg, x))), size=sz.value))[1] # noqa: E501 -def check(status): - if status != 0: raise RuntimeError(f"HIP Error {status}, {ctypes.string_at(hip.hipGetErrorString(status)).decode()}") -def compile_hip(prg:str, arch="gfx1100") -> bytes: - check(hip.hiprtcCreateProgram(ctypes.byref(prog := hip.hiprtcProgram()), prg.encode(), "".encode(), 0, None, None)) - compile_options = [f'--offload-arch={arch}', '-I/opt/rocm/include'] - status = hip.hiprtcCompileProgram(prog, len(compile_options), to_char_p_p([o.encode() for o in compile_options])) - if status != 0: raise RuntimeError(f"compile failed: {get_bytes(prog, hip.hiprtcGetProgramLogSize, hip.hiprtcGetProgramLog, check).decode()}") - return get_bytes(prog, hip.hiprtcGetCodeSize, hip.hiprtcGetCode, check) - -prefix = """ -typedef long unsigned int size_t; -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); -extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); -typedef float float2 __attribute__((ext_vector_type(2))); -static inline __attribute__((device)) float2 make_float2(float x, float y) { return {x, y}; } -""" - -code = """ -extern "C" __attribute__((global))void r_2_8_7_7_4_8_3_7_7_4_4_2_2(float* data0, const float* data1, const float* data2) { - int gidx0 = __ockl_get_group_id(2); /* 2 */ - int gidx1 = __ockl_get_group_id(1); /* 8 */ - int gidx2 = __ockl_get_group_id(0); /* 49 */ - int lidx4 = __ockl_get_local_id(1); /* 4 */ - int lidx5 = __ockl_get_local_id(0); /* 8 */ - float2 acc0 = make_float2(0.0f,0.0f); - float2 acc1 = make_float2(0.0f,0.0f); - float2 acc2 = make_float2(0.0f,0.0f); - float2 acc3 = make_float2(0.0f,0.0f); - float2 acc4 = make_float2(0.0f,0.0f); - float2 acc5 = make_float2(0.0f,0.0f); - float2 acc6 = make_float2(0.0f,0.0f); - float2 acc7 = make_float2(0.0f,0.0f); - float2 acc8 = make_float2(0.0f,0.0f); - float2 acc9 = make_float2(0.0f,0.0f); - float2 acc10 = make_float2(0.0f,0.0f); - float2 acc11 = make_float2(0.0f,0.0f); - float2 acc12 = make_float2(0.0f,0.0f); - float2 acc13 = make_float2(0.0f,0.0f); - float2 acc14 = make_float2(0.0f,0.0f); - float2 acc15 = make_float2(0.0f,0.0f); - float2 acc16 = make_float2(0.0f,0.0f); - float2 acc17 = make_float2(0.0f,0.0f); - float2 acc18 = make_float2(0.0f,0.0f); - float2 acc19 = make_float2(0.0f,0.0f); - float2 acc20 = make_float2(0.0f,0.0f); - float2 acc21 = make_float2(0.0f,0.0f); - float2 acc22 = make_float2(0.0f,0.0f); - float2 acc23 = make_float2(0.0f,0.0f); - float2 acc24 = make_float2(0.0f,0.0f); - float2 acc25 = make_float2(0.0f,0.0f); - float2 acc26 = make_float2(0.0f,0.0f); - float2 acc27 = make_float2(0.0f,0.0f); - float2 acc28 = make_float2(0.0f,0.0f); - float2 acc29 = make_float2(0.0f,0.0f); - float2 acc30 = make_float2(0.0f,0.0f); - float2 acc31 = make_float2(0.0f,0.0f); - int alu0 = (gidx2/7); - int alu1 = (gidx2%7); - int alu2 = (alu1*32); - int alu3 = (lidx5*4); - int alu4 = ((gidx0*802816)+(gidx1*100352)+(alu0*1792)+(alu1*16)+(lidx4*448)+(lidx5*2)); - for (int ridx0 = 0; ridx0 < 3; ridx0++) { - for (int ridx1 = 0; ridx1 < 7; ridx1++) { - int alu5 = ((alu0*(-32))+(lidx4*(-8))+(ridx1*(-1))); - bool alu6 = (alu5<(-2)); - bool alu7 = (alu5<0); - bool alu8 = (((alu0*32)+(lidx4*8)+ridx1)<221); - for (int ridx2 = 0; ridx2 < 7; ridx2++) { - int alu9 = ((gidx0*150528)+(ridx0*50176)+(alu0*7168)+(lidx4*1792)+(ridx1*224)+alu2+alu3+ridx2); - int alu10 = ((alu1*(-32))+(lidx5*(-4))+(ridx2*(-1))); - bool alu11 = (alu10<(-2)); - float val0 = 0.0f; - if ((alu6*alu11)) { val0 = data1[alu9+(-675)]; } - float val1 = 0.0f; - if ((alu7*alu11)) { val1 = data1[alu9+(-227)]; } - float val2 = 0.0f; - if (alu11) { val2 = data1[alu9+221]; } - float val3 = 0.0f; - if ((alu8*alu11)) { val3 = data1[alu9+669]; } - bool alu12 = (alu10<0); - bool alu13 = ((alu2+alu3+ridx2)<225); - float val4 = 0.0f; - if ((alu6*alu12*alu13)) { val4 = data1[alu9+(-673)]; } - float val5 = 0.0f; - if ((alu7*alu12*alu13)) { val5 = data1[alu9+(-225)]; } - float val6 = 0.0f; - if ((alu12*alu13)) { val6 = data1[alu9+223]; } - float val7 = 0.0f; - if ((alu8*alu12*alu13)) { val7 = data1[alu9+671]; } - int alu14 = ((gidx1*1176)+(ridx0*49)+(ridx1*7)+ridx2); - float val8 = data2[alu14]; - float val9 = data2[alu14+147]; - float val10 = data2[alu14+294]; - float val11 = data2[alu14+441]; - float val12 = data2[alu14+588]; - float val13 = data2[alu14+735]; - float val14 = data2[alu14+882]; - float val15 = data2[alu14+1029]; - (acc0).x = ((val0*val8)+(acc0).x); - (acc1).x = ((val0*val9)+(acc1).x); - (acc2).x = ((val0*val10)+(acc2).x); - (acc3).x = ((val0*val11)+(acc3).x); - (acc4).x = ((val1*val8)+(acc4).x); - (acc5).x = ((val1*val9)+(acc5).x); - (acc6).x = ((val1*val10)+(acc6).x); - (acc7).x = ((val1*val11)+(acc7).x); - (acc8).x = ((val2*val8)+(acc8).x); - (acc9).x = ((val2*val9)+(acc9).x); - (acc10).x = ((val2*val10)+(acc10).x); - (acc11).x = ((val2*val11)+(acc11).x); - (acc12).x = ((val3*val8)+(acc12).x); - (acc13).x = ((val3*val9)+(acc13).x); - (acc14).x = ((val3*val10)+(acc14).x); - (acc15).x = ((val3*val11)+(acc15).x); - (acc16).x = ((val0*val12)+(acc16).x); - (acc17).x = ((val0*val13)+(acc17).x); - (acc18).x = ((val0*val14)+(acc18).x); - (acc19).x = ((val0*val15)+(acc19).x); - (acc20).x = ((val1*val12)+(acc20).x); - (acc21).x = ((val1*val13)+(acc21).x); - (acc22).x = ((val1*val14)+(acc22).x); - (acc23).x = ((val1*val15)+(acc23).x); - (acc24).x = ((val2*val12)+(acc24).x); - (acc25).x = ((val2*val13)+(acc25).x); - (acc26).x = ((val2*val14)+(acc26).x); - (acc27).x = ((val2*val15)+(acc27).x); - (acc28).x = ((val3*val12)+(acc28).x); - (acc29).x = ((val3*val13)+(acc29).x); - (acc30).x = ((val3*val14)+(acc30).x); - (acc31).x = ((val3*val15)+(acc31).x); - (acc0).y = ((val4*val8)+(acc0).y); - (acc1).y = ((val4*val9)+(acc1).y); - (acc2).y = ((val4*val10)+(acc2).y); - (acc3).y = ((val4*val11)+(acc3).y); - (acc4).y = ((val5*val8)+(acc4).y); - (acc5).y = ((val5*val9)+(acc5).y); - (acc6).y = ((val5*val10)+(acc6).y); - (acc7).y = ((val5*val11)+(acc7).y); - (acc8).y = ((val6*val8)+(acc8).y); - (acc9).y = ((val6*val9)+(acc9).y); - (acc10).y = ((val6*val10)+(acc10).y); - (acc11).y = ((val6*val11)+(acc11).y); - (acc12).y = ((val7*val8)+(acc12).y); - (acc13).y = ((val7*val9)+(acc13).y); - (acc14).y = ((val7*val10)+(acc14).y); - (acc15).y = ((val7*val11)+(acc15).y); - (acc16).y = ((val4*val12)+(acc16).y); - (acc17).y = ((val4*val13)+(acc17).y); - (acc18).y = ((val4*val14)+(acc18).y); - (acc19).y = ((val4*val15)+(acc19).y); - (acc20).y = ((val5*val12)+(acc20).y); - (acc21).y = ((val5*val13)+(acc21).y); - (acc22).y = ((val5*val14)+(acc22).y); - (acc23).y = ((val5*val15)+(acc23).y); - (acc24).y = ((val6*val12)+(acc24).y); - (acc25).y = ((val6*val13)+(acc25).y); - (acc26).y = ((val6*val14)+(acc26).y); - (acc27).y = ((val6*val15)+(acc27).y); - (acc28).y = ((val7*val12)+(acc28).y); - (acc29).y = ((val7*val13)+(acc29).y); - (acc30).y = ((val7*val14)+(acc30).y); - (acc31).y = ((val7*val15)+(acc31).y); - } - } - } - *((float2*)(data0+alu4)) = acc0; - *((float2*)(data0+alu4+12544)) = acc1; - *((float2*)(data0+alu4+25088)) = acc2; - *((float2*)(data0+alu4+37632)) = acc3; - *((float2*)(data0+alu4+112)) = acc4; - *((float2*)(data0+alu4+12656)) = acc5; - *((float2*)(data0+alu4+25200)) = acc6; - *((float2*)(data0+alu4+37744)) = acc7; - *((float2*)(data0+alu4+224)) = acc8; - *((float2*)(data0+alu4+12768)) = acc9; - *((float2*)(data0+alu4+25312)) = acc10; - *((float2*)(data0+alu4+37856)) = acc11; - *((float2*)(data0+alu4+336)) = acc12; - *((float2*)(data0+alu4+12880)) = acc13; - *((float2*)(data0+alu4+25424)) = acc14; - *((float2*)(data0+alu4+37968)) = acc15; - *((float2*)(data0+alu4+50176)) = acc16; - *((float2*)(data0+alu4+62720)) = acc17; - *((float2*)(data0+alu4+75264)) = acc18; - *((float2*)(data0+alu4+87808)) = acc19; - *((float2*)(data0+alu4+50288)) = acc20; - *((float2*)(data0+alu4+62832)) = acc21; - *((float2*)(data0+alu4+75376)) = acc22; - *((float2*)(data0+alu4+87920)) = acc23; - *((float2*)(data0+alu4+50400)) = acc24; - *((float2*)(data0+alu4+62944)) = acc25; - *((float2*)(data0+alu4+75488)) = acc26; - *((float2*)(data0+alu4+88032)) = acc27; - *((float2*)(data0+alu4+50512)) = acc28; - *((float2*)(data0+alu4+63056)) = acc29; - *((float2*)(data0+alu4+75600)) = acc30; - *((float2*)(data0+alu4+88144)) = acc31; -} -""" - -dev = "HIP" -lib = Device[dev].compiler.compile(prefix+code) -#lib = compile_hip(code) -b0 = Buffer(dev, 1605632, dtypes.float) -b1 = Buffer(dev, 301506, dtypes.float) -b2 = Buffer(dev, 9408, dtypes.float) -print(hex(b0._buf.value), hex(b0._buf.value+1605632*4)) -print(hex(b1._buf.value)) -print(hex(b2._buf.value)) -#prg = CompiledRunner("r_2_8_7_7_4_8_3_7_7_4_4_2_2", "", dev, [7, 1, 1], [8, 4, 1], precompiled=lib) -prg = CompiledRunner("r_2_8_7_7_4_8_3_7_7_4_4_2_2", "", dev, [49, 8, 2], [8, 4, 1], precompiled=lib) -print("compiled") -prg([b0, b1, b2], {}) -print("ran") -Device[dev].synchronize() -print("sync") diff --git a/tinygrad/test/external/external_jit_failure.py b/tinygrad/test/external/external_jit_failure.py deleted file mode 100644 index 8fc9ad93..00000000 --- a/tinygrad/test/external/external_jit_failure.py +++ /dev/null @@ -1,17 +0,0 @@ -from tinygrad import Tensor, TinyJit, Device -import numpy as np - -GPUS = 4 -N = 128 -ds = tuple([Device.canonicalize(f"{Device.DEFAULT}:{i}") for i in range(GPUS)]) -t = Tensor.rand(N, N, N).shard(ds, 0) -n = t.numpy() - -@TinyJit -def allreduce(t:Tensor) -> Tensor: - return t.sum(0) #.realize() - -for i in range(10): - print(i) - tn = allreduce(t).numpy() - np.testing.assert_allclose(tn, n.sum(0), atol=1e-4, rtol=1e-4) diff --git a/tinygrad/test/external/external_llama_eval.py b/tinygrad/test/external/external_llama_eval.py deleted file mode 100644 index e7078253..00000000 --- a/tinygrad/test/external/external_llama_eval.py +++ /dev/null @@ -1,102 +0,0 @@ -from lm_eval.base import BaseLM -from lm_eval import evaluator, tasks -import torch, json, argparse - -from examples.llama import LLaMa -from tinygrad.tensor import Tensor -from tinygrad import Device - -class LLaMaAdaptor(BaseLM): - def __init__( - self, - model_size="7B", - model_gen=1, - device="", - quantize=False, - batch_size=1, - max_batch_size=1, - do_sample=False, - temperature=1.0, - checkpoint_path="", - tokenizer_path="", - ): - super().__init__() - - if batch_size is None: - batch_size = 1 - self.do_sample = do_sample - self.temperature = temperature - self._device = device - - assert isinstance(model_gen, int) - assert isinstance(model_size, str) - assert isinstance(batch_size, int) - assert isinstance(checkpoint_path, str) - assert isinstance(tokenizer_path, str) - - self.llama = LLaMa.build(checkpoint_path, tokenizer_path, model_gen, model_size, quantize) - - @classmethod - def create_from_arg_string(cls, arg_string, additional_config=None): - kwargs = {el.split("=")[0]: el.split("=")[1] for el in arg_string.split(",")} - return cls(**kwargs, **additional_config) - - @property - def eot_token_id(self): - # we use EOT because end of *text* is more accurate for what we're doing than end of *sentence* - return self.llama.tokenizer.eos_id() - - @property - def max_length(self): - return 1024 - - @property - def max_gen_toks(self): - return 256 - - @property - def batch_size(self): - return 1 - - @property - def device(self): - return self._device - - def tok_encode(self, string: str): - return [self.llama.tokenizer.bos_id()] + self.llama.tokenizer.encode(string) - - def tok_decode(self, tokens): - return self.llama.tokenizer.decode(tokens) - - def _model_call(self, inps): - return torch.Tensor(self.llama.model(Tensor(inps.numpy()), 0).numpy()) - - def greedy_until(self, requests): - continuations = [] - for request in requests: - prompt, until = request[0], request[1]['until'] - output = self.llama.greedy_until(prompt, until, max_length=128, temperature=0.0) - continuations.append(output[len(prompt):]) - return continuations - - def _model_generate(self, context, max_length, eos_token_id): - raise NotImplementedError() - -if __name__ == '__main__': - print(f"using {Device.DEFAULT} backend") - - parser = argparse.ArgumentParser(description='Run LLaMA evals in tinygrad', formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument('--size', type=str, default="7B", help="Size of model to use [7B, 13B, 30B, 65B] for Gen 1, [7B, 13B] for Gen 2") - parser.add_argument('--gen', type=int, default="1", help="Generation of the model to use [1, 2]") - parser.add_argument('--quantize', action='store_true', help="Quantize the weights to int8 in memory") - parser.add_argument('--eval', type=str, default="arc_easy", help="Run in evaluation mode") - parser.add_argument('--limit', type=int, default=None, help="Limit tests in eval") - parser.add_argument('--weights', type=str, default="./weights/LLaMa/", help="Location of the weights") - parser.add_argument('--tokenizer', type=str, default="./weights/LLaMa/tokenizer.model", help="Location of the tokenizer") - args = parser.parse_args() - - # run eval and exit - adaptor = LLaMaAdaptor(model_gen=args.gen, model_size=args.size, quantize=args.quantize, - checkpoint_path=args.weights, tokenizer_path=args.tokenizer, device="cpu") - results = evaluator.evaluate(adaptor, tasks.get_task_dict(args.eval.split(",")), False, 0, args.limit) - print(json.dumps(results, indent=2)) diff --git a/tinygrad/test/external/external_metal_compile_fail.py b/tinygrad/test/external/external_metal_compile_fail.py deleted file mode 100644 index d6e2bf98..00000000 --- a/tinygrad/test/external/external_metal_compile_fail.py +++ /dev/null @@ -1,230 +0,0 @@ -# AssertionError: Error Domain=AGXMetalG15X_B0 Code=3 "Compiler encountered an internal error" - -src = """ -#include -using namespace metal; -kernel void r_64_32_8_16_4_6_6_4(device float* data0, const device float* data1, - uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { - int gidx0 = gid.x; /* 64 */ - int lidx2 = lid.x; /* 8 */ - int gidx1 = gid.y; /* 32 */ - int lidx3 = lid.y; /* 16 */ - int alu0 = ((gidx0*4096)+(gidx1*16)+(lidx2*512)+lidx3); - int alu1 = ((gidx0*147456)+(gidx1*576)+(lidx2*18432)+(lidx3*36)); - float acc0 = 0.0f; - float acc1 = 0.0f; - float acc2 = 0.0f; - float acc3 = 0.0f; - float acc4 = 0.0f; - float acc5 = 0.0f; - float acc6 = 0.0f; - float acc7 = 0.0f; - float acc8 = 0.0f; - float acc9 = 0.0f; - float acc10 = 0.0f; - float acc11 = 0.0f; - float acc12 = 0.0f; - float acc13 = 0.0f; - float acc14 = 0.0f; - float acc15 = 0.0f; - float acc16 = 0.0f; - float acc17 = 0.0f; - float acc18 = 0.0f; - float acc19 = 0.0f; - float acc20 = 0.0f; - float acc21 = 0.0f; - float acc22 = 0.0f; - float acc23 = 0.0f; - float acc24 = 0.0f; - float acc25 = 0.0f; - float acc26 = 0.0f; - float acc27 = 0.0f; - float acc28 = 0.0f; - float acc29 = 0.0f; - float acc30 = 0.0f; - float acc31 = 0.0f; - float acc32 = 0.0f; - float acc33 = 0.0f; - float acc34 = 0.0f; - float acc35 = 0.0f; - for (int ridx0 = 0; ridx0 < 4; ridx0++) { - int alu2 = (ridx0*6); - int alu3 = (alu2+1); - int alu4 = (alu2+2); - int alu5 = (alu2+3); - int alu6 = (alu2+4); - int alu7 = (alu2+5); - int alu8 = (alu2%7); - int alu9 = ((alu8+1)%7); - int alu10 = ((alu8+2)%7); - int alu11 = ((alu8+3)%7); - int alu12 = ((alu8+4)%7); - int alu13 = ((alu8+5)%7); - int alu14 = ((((alu0+(alu3/21))%262144)*144)+(((alu3/7)%3)*3)+(alu9*36)); - int alu15 = ((((alu0+(alu4/21))%262144)*144)+(((alu4/7)%3)*3)+(alu10*36)); - int alu16 = ((((alu0+(alu5/21))%262144)*144)+(((alu5/7)%3)*3)+(alu11*36)); - int alu17 = ((((alu0+(alu6/21))%262144)*144)+(((alu6/7)%3)*3)+(alu12*36)); - int alu18 = ((((alu0+(alu7/21))%262144)*144)+(((alu7/7)%3)*3)+(alu13*36)); - int alu19 = (alu8%7); - int alu20 = ((((alu0+(alu2/21))%262144)*144)+(((alu2/7)%3)*3)+(alu19*36)); - bool alu21 = ((alu2<16)&(alu13<4)); - bool alu22 = ((alu2<17)&(alu12<4)); - bool alu23 = ((alu2<18)&(alu11<4)); - bool alu24 = ((alu2<19)&(alu10<4)); - bool alu25 = ((alu2<20)&(alu9<4)); - bool alu26 = ((alu2<21)&(alu19<4)); - float val0 = (alu25?*(data1+alu14+1):0.0f); - float val1 = (alu25?*(data1+alu14+2):0.0f); - float val2 = (alu25?*(data1+alu14+9):0.0f); - float val3 = (alu25?*(data1+alu14+10):0.0f); - float val4 = (alu25?*(data1+alu14+11):0.0f); - float val5 = (alu25?*(data1+alu14+18):0.0f); - float val6 = (alu25?*(data1+alu14+19):0.0f); - float val7 = (alu25?*(data1+alu14+20):0.0f); - float val8 = (alu25?*(data1+alu14+27):0.0f); - float val9 = (alu25?*(data1+alu14+28):0.0f); - float val10 = (alu25?*(data1+alu14+29):0.0f); - float val11 = (alu24?*(data1+alu15+1):0.0f); - float val12 = (alu24?*(data1+alu15+2):0.0f); - float val13 = (alu24?*(data1+alu15+9):0.0f); - float val14 = (alu24?*(data1+alu15+10):0.0f); - float val15 = (alu24?*(data1+alu15+11):0.0f); - float val16 = (alu24?*(data1+alu15+18):0.0f); - float val17 = (alu24?*(data1+alu15+19):0.0f); - float val18 = (alu24?*(data1+alu15+20):0.0f); - float val19 = (alu24?*(data1+alu15+27):0.0f); - float val20 = (alu24?*(data1+alu15+28):0.0f); - float val21 = (alu24?*(data1+alu15+29):0.0f); - float val22 = (alu23?*(data1+alu16+1):0.0f); - float val23 = (alu23?*(data1+alu16+2):0.0f); - float val24 = (alu23?*(data1+alu16+9):0.0f); - float val25 = (alu23?*(data1+alu16+10):0.0f); - float val26 = (alu23?*(data1+alu16+11):0.0f); - float val27 = (alu23?*(data1+alu16+18):0.0f); - float val28 = (alu23?*(data1+alu16+19):0.0f); - float val29 = (alu23?*(data1+alu16+20):0.0f); - float val30 = (alu23?*(data1+alu16+27):0.0f); - float val31 = (alu23?*(data1+alu16+28):0.0f); - float val32 = (alu23?*(data1+alu16+29):0.0f); - float val33 = (alu22?*(data1+alu17+1):0.0f); - float val34 = (alu22?*(data1+alu17+2):0.0f); - float val35 = (alu22?*(data1+alu17+9):0.0f); - float val36 = (alu22?*(data1+alu17+10):0.0f); - float val37 = (alu22?*(data1+alu17+11):0.0f); - float val38 = (alu22?*(data1+alu17+18):0.0f); - float val39 = (alu22?*(data1+alu17+19):0.0f); - float val40 = (alu22?*(data1+alu17+20):0.0f); - float val41 = (alu22?*(data1+alu17+27):0.0f); - float val42 = (alu22?*(data1+alu17+28):0.0f); - float val43 = (alu22?*(data1+alu17+29):0.0f); - float val44 = (alu21?*(data1+alu18+1):0.0f); - float val45 = (alu21?*(data1+alu18+2):0.0f); - float val46 = (alu21?*(data1+alu18+9):0.0f); - float val47 = (alu21?*(data1+alu18+10):0.0f); - float val48 = (alu21?*(data1+alu18+11):0.0f); - float val49 = (alu21?*(data1+alu18+18):0.0f); - float val50 = (alu21?*(data1+alu18+19):0.0f); - float val51 = (alu21?*(data1+alu18+20):0.0f); - float val52 = (alu21?*(data1+alu18+27):0.0f); - float val53 = (alu21?*(data1+alu18+28):0.0f); - float val54 = (alu21?*(data1+alu18+29):0.0f); - float val55 = (alu26?*(data1+alu20+1):0.0f); - float val56 = (alu26?*(data1+alu20+2):0.0f); - float val57 = (alu26?*(data1+alu20+9):0.0f); - float val58 = (alu26?*(data1+alu20+10):0.0f); - float val59 = (alu26?*(data1+alu20+11):0.0f); - float val60 = (alu26?*(data1+alu20+18):0.0f); - float val61 = (alu26?*(data1+alu20+19):0.0f); - float val62 = (alu26?*(data1+alu20+20):0.0f); - float val63 = (alu26?*(data1+alu20+27):0.0f); - float val64 = (alu26?*(data1+alu20+28):0.0f); - float val65 = (alu26?*(data1+alu20+29):0.0f); - float val66 = (alu25?*(data1+alu14):0.0f); - float val67 = (alu24?*(data1+alu15):0.0f); - float val68 = (alu23?*(data1+alu16):0.0f); - float val69 = (alu22?*(data1+alu17):0.0f); - float val70 = (alu21?*(data1+alu18):0.0f); - float val71 = (alu26?*(data1+alu20):0.0f); - acc0 = (acc0+val71); - acc1 = (acc1+val66); - acc2 = (acc2+val67); - acc3 = (acc3+val68); - acc4 = (acc4+val69); - acc5 = (acc5+val70); - acc6 = (acc6+val57+val55); - acc7 = (acc7+val2+val0); - acc8 = (acc8+val13+val11); - acc9 = (acc9+val24+val22); - acc10 = (acc10+val35+val33); - acc11 = (acc11+val46+val44); - acc12 = (acc12+val60+val58+val56); - acc13 = (acc13+val5+val3+val1); - acc14 = (acc14+val16+val14+val12); - acc15 = (acc15+val27+val25+val23); - acc16 = (acc16+val38+val36+val34); - acc17 = (acc17+val49+val47+val45); - acc18 = (acc18+val63+val61+val59); - acc19 = (acc19+val8+val6+val4); - acc20 = (acc20+val19+val17+val15); - acc21 = (acc21+val30+val28+val26); - acc22 = (acc22+val41+val39+val37); - acc23 = (acc23+val52+val50+val48); - acc24 = (acc24+val64+val62); - acc25 = (acc25+val9+val7); - acc26 = (acc26+val20+val18); - acc27 = (acc27+val31+val29); - acc28 = (acc28+val42+val40); - acc29 = (acc29+val53+val51); - acc30 = (acc30+val65); - acc31 = (acc31+val10); - acc32 = (acc32+val21); - acc33 = (acc33+val32); - acc34 = (acc34+val43); - acc35 = (acc35+val54); - } - *(data0+alu1+1) = acc6; - *(data0+alu1+2) = acc12; - *(data0+alu1+3) = acc18; - *(data0+alu1+4) = acc24; - *(data0+alu1+5) = acc30; - *(data0+alu1+6) = acc1; - *(data0+alu1+7) = acc7; - *(data0+alu1+8) = acc13; - *(data0+alu1+9) = acc19; - *(data0+alu1+10) = acc25; - *(data0+alu1+11) = acc31; - *(data0+alu1+12) = acc2; - *(data0+alu1+13) = acc8; - *(data0+alu1+14) = acc14; - *(data0+alu1+15) = acc20; - *(data0+alu1+16) = acc26; - *(data0+alu1+17) = acc32; - *(data0+alu1+18) = acc3; - *(data0+alu1+19) = acc9; - *(data0+alu1+20) = acc15; - *(data0+alu1+21) = acc21; - *(data0+alu1+22) = acc27; - *(data0+alu1+23) = acc33; - *(data0+alu1+24) = acc4; - *(data0+alu1+25) = acc10; - *(data0+alu1+26) = acc16; - *(data0+alu1+27) = acc22; - *(data0+alu1+28) = acc28; - *(data0+alu1+29) = acc34; - *(data0+alu1+30) = acc5; - *(data0+alu1+31) = acc11; - *(data0+alu1+32) = acc17; - *(data0+alu1+33) = acc23; - *(data0+alu1+34) = acc29; - *(data0+alu1+35) = acc35; - *(data0+alu1) = acc0; -} -""" - -from tinygrad.runtime.ops_metal import MetalDevice, MetalCompiler, MetalProgram - -if __name__ == "__main__": - dev = MetalDevice("METAL") - lib = MetalCompiler().compile(src) - prg = MetalProgram(dev, "r_64_32_8_16_4_6_6_4", lib) - diff --git a/tinygrad/test/external/external_model_benchmark.py b/tinygrad/test/external/external_model_benchmark.py deleted file mode 100644 index 838089ef..00000000 --- a/tinygrad/test/external/external_model_benchmark.py +++ /dev/null @@ -1,135 +0,0 @@ -import csv, pathlib, time -import numpy as np -import torch -torch.set_num_threads(1) -from onnx.helper import tensor_dtype_to_np_dtype -import onnxruntime as ort -from onnx2torch import convert -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from tinygrad.helpers import OSX, DEBUG, fetch, getenv -from tinygrad import Tensor, Device - -MODELS = { - "resnet50": "https://github.com/onnx/models/raw/main/validated/vision/classification/resnet/model/resnet50-caffe2-v1-9.onnx", - "openpilot": "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx", - "efficientnet": "https://github.com/onnx/models/raw/main/validated/vision/classification/efficientnet-lite4/model/efficientnet-lite4-11.onnx", - "shufflenet": "https://github.com/onnx/models/raw/main/validated/vision/classification/shufflenet/model/shufflenet-9.onnx", - # TODO: precision issue - # "commavq": "https://huggingface.co/commaai/commavq-gpt2m/resolve/main/gpt2m.onnx", - "dm": "https://github.com/commaai/openpilot/raw/ba7f840a06dbc8ae3c45b3b4976c88a21895aed0/selfdrive/modeld/models/dmonitoring_model.onnx", - - # broken in torch MPS - # "zfnet": "https://github.com/onnx/models/raw/main/archive/vision/classification/zfnet-512/model/zfnet512-9.onnx", - # TypeError: BatchNormalization() got an unexpected keyword argument 'is_test' - # "densenet": "https://github.com/onnx/models/raw/main/archive/vision/classification/densenet-121/model/densenet-3.onnx", - # AssertionError: only onnx version >= 10 supported for slice - # "bert": "https://github.com/onnx/models/raw/main/archive/text/machine_comprehension/bert-squad/model/bertsquad-8.onnx", - # really slow - # "resnet18": "https://github.com/onnx/models/raw/main/archive/vision/classification/resnet/model/resnet18-v2-7.onnx", -} - -CSV = {} -open_csv = None - -def benchmark(mnm, nm, fxn): - tms = [] - for _ in range(3): - st = time.perf_counter_ns() - ret = fxn() - tms.append(time.perf_counter_ns() - st) - print(f"{mnm:15s} {nm:25s} {min(tms)*1e-6:7.2f} ms") - CSV[nm] = min(tms)*1e-6 - return min(tms), ret - -#BASE = pathlib.Path(__file__).parents[2] / "weights" / "onnx" -BASE = pathlib.Path("/tmp/onnx") -def benchmark_model(m, devices, validate_outs=False): - torch.manual_seed(1) - global open_csv, CSV - CSV = {"model": m} - - fn = fetch(MODELS[m]) - onnx_model = onnx_load(fn) - output_names = [out.name for out in onnx_model.graph.output] - excluded = {inp.name for inp in onnx_model.graph.initializer} - input_shapes = {inp.name:tuple(x.dim_value if hasattr(x, "dim_value") and x.dim_value != 0 else 1 for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input if inp.name not in excluded} # noqa: E501 - input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input if inp.name not in excluded} - #input_types = {k:v if v!=np.float16 else np.float32 for k,v in input_types.items()} # cast - np_inputs = {k:torch.randn(shp).numpy().astype(input_types[k]) for k,shp in input_shapes.items()} - assert len(input_shapes) < 30, f"too many input shapes {len(input_shapes)}" - - # print input names - if DEBUG >= 2: print([inp.name for inp in onnx_model.graph.input if inp.name not in excluded]) - for device in devices: - Device.DEFAULT = device - inputs = {k:Tensor(inp) for k,inp in np_inputs.items()} - tinygrad_model = OnnxRunner(onnx_model) - benchmark(m, f"tinygrad_{device.lower()}_jitless", lambda: {k:v.numpy() for k,v in tinygrad_model(inputs).items()}) - - from tinygrad.engine.jit import TinyJit - tinygrad_jitted_model = TinyJit(lambda **kwargs: {k:v.realize() for k,v in tinygrad_model(kwargs).items()}) - for _ in range(3): {k:v.numpy() for k,v in tinygrad_jitted_model(**inputs).items()} - benchmark(m, f"tinygrad_{device.lower()}_jit", lambda: {k:v.numpy() for k,v in tinygrad_jitted_model(**inputs).items()}) # noqa: F821 - del inputs, tinygrad_model, tinygrad_jitted_model - - # convert model to torch - try: - torch_model = convert(fn) - except Exception as e: - # model conversion failed - print(f"{m:16s}onnx2torch {type(e).__name__:>25}") - else: - torch_inputs = [torch.tensor(x) for x in np_inputs.values()] - try: benchmark(m, "torch_cpu", lambda: torch_model(*torch_inputs)) - except Exception as e: print(f"{m:16s}torch_cpu {type(e).__name__:>25}") - - torch_device = "mps" if OSX else "cuda" - torch_mps_model = torch_model.to(torch_device) - torch_mps_inputs = [x.to(torch_device) for x in torch_inputs] - try: benchmark(m, f"torch_{torch_device}", lambda: torch_mps_model(*torch_mps_inputs)) - except Exception as e: print(f"{m:16s}torch_{torch_device} {type(e).__name__:>25}") - - # bench onnxruntime - ort_options = ort.SessionOptions() - ort_options.graph_optimization_level = ort.GraphOptimizationLevel.ORT_ENABLE_ALL - ort_options.log_severity_level = 3 # no warnings - for backend in ["CPU", "CUDA" if not OSX else "CoreML"]: # https://onnxruntime.ai/docs/execution-providers/ - provider = backend+"ExecutionProvider" - if provider not in ort.get_available_providers(): continue - ort_sess = ort.InferenceSession(str(fn), ort_options, [provider]) - try: - benchmark(m, f"onnxruntime_{backend.lower()}", lambda: ort_sess.run(output_names, np_inputs)) - except Exception as e: print(f"{m:16s}onnxruntime_{backend.lower()} {type(e).__name__:>25}") - del ort_sess - - if validate_outs: - for device in devices: - rtol, atol = 2e-3, 2e-3 # tolerance for fp16 models - Device.DEFAULT = device - inputs = {k:Tensor(inp) for k,inp in np_inputs.items()} - tinygrad_model = OnnxRunner(onnx_model) - tinygrad_out = tinygrad_model(inputs) - - ort_sess = ort.InferenceSession(str(fn), ort_options, ["CPUExecutionProvider"]) - onnx_out = ort_sess.run(output_names, np_inputs) - onnx_out = dict([*list(zip(output_names, onnx_out))]) - - assert_allclose(tinygrad_out, onnx_out, rtol=rtol, atol=atol) - print(f"{m:16s}outputs validated on {device=} with rtol={rtol:.1e}, atol={atol:.1e}") - - if open_csv is None: - open_csv = csv.DictWriter(open('onnx_inference_speed.csv', 'w', newline=''), fieldnames=list(CSV.keys())) - open_csv.writeheader() - open_csv.writerow(CSV) - -def assert_allclose(tiny_out:dict, onnx_out:dict, rtol, atol): - assert tiny_out.keys() == onnx_out.keys() - for k in tiny_out.keys(): - tiny_v, onnx_v = tiny_out[k], onnx_out[k] - np.testing.assert_allclose(tiny_v.numpy(), onnx_v, rtol=rtol, atol=atol, err_msg=f"For tensor '{k}' in {tiny_out.keys()}") - -if __name__ == "__main__": - devices = [Device.DEFAULT] if getenv("NOCLANG") else [Device.DEFAULT, "CPU"] - if (model:=getenv("MODEL", "")) != "": benchmark_model(model, devices, validate_outs=True) - else: - for m in MODELS: benchmark_model(m, devices, validate_outs=True) diff --git a/tinygrad/test/external/external_multi_gpu.py b/tinygrad/test/external/external_multi_gpu.py deleted file mode 100644 index 32d107df..00000000 --- a/tinygrad/test/external/external_multi_gpu.py +++ /dev/null @@ -1,79 +0,0 @@ -#!/usr/bin/env python3 -# cd extra/disassemblers/ && git clone --recursive github.com:geohot/cuda_ioctl_sniffer.git -# LD_PRELOAD=$PWD/extra/disassemblers/cuda_ioctl_sniffer/out/sniff.so GPU=1 python3 test/external/external_multi_gpu.py -import numpy as np -from tinygrad.tensor import Tensor -from tinygrad.helpers import colored, Timing, getenv -from tinygrad.device import Device - -d0, d1 = f'{Device.DEFAULT}:0', f'{Device.DEFAULT}:1' - -def sync(): - Device[d0].synchronize() - Device[d1].synchronize() - -if __name__ == "__main__": - print("GPU devices", d0, d1) - sz = getenv("N", 1024*1024*256) # 1 GB - - with Timing("GPU initial sync: "): sync() - - with Timing("CPU creation: ", on_exit=lambda x: f", {(sz*4*2)/x:.2f} GB/sec"): - c0 = (Tensor.ones(sz, device="CPU")/2).realize() - c1 = (Tensor.ones(sz, device="CPU")/4).realize() - print(c0.uop.base.realized) - print(c1.uop.base.realized) - - with Timing("CPU -> 0: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - a0 = c0.to(d0).realize() - sync() - with Timing("CPU -> 1: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - b1 = c1.to(d1).realize() - sync() - - # cross copy. this is (sometimes) going through the CPU - with Timing("0 -> 1: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - a1 = a0.to(d1).realize() - sync() - with Timing("1 -> 0: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - b0 = b1.to(d0).realize() - sync() - - # sum - with Timing("0+0 -> 0 (sum): ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - ab0 = (a0 + b0).realize() - sync() - with Timing("1+1 -> 1 (sum): ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - ab1 = (a1 + b1).realize() - sync() - - # cross device sum (does this work?) - with Timing(colored("0+1 -> 0 (sum): ", "red"), on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - abx0 = (a0 + b1.to(d0)).realize() - sync() - - with Timing(colored("1+0 -> 1 (sum): ", "red"), on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - abx1 = (b1 + a0.to(d1)).realize() - sync() - - # copy back - # NOTE: half of this slowness is caused by allocating memory on the CPU - with Timing("0 -> CPU: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - cc0 = ab0.numpy() - with Timing("1 -> CPU: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): - cc1 = ab1.numpy() - - # same - print("testing") - np.testing.assert_allclose(cc0, cc1) - - # same (cross) - print("testing (cross)") - np.testing.assert_allclose(cc0, abx0.numpy()) - np.testing.assert_allclose(cc0, abx1.numpy()) - - # devices - print(ab0) - print(ab1) - print(abx0) - print(abx1) diff --git a/tinygrad/test/external/external_osx_profiling.py b/tinygrad/test/external/external_osx_profiling.py deleted file mode 100644 index 8ac1e584..00000000 --- a/tinygrad/test/external/external_osx_profiling.py +++ /dev/null @@ -1,41 +0,0 @@ -from tinygrad.runtime.ops_gpu import CLProgram, CL, CLBuffer -from tinygrad import dtypes -import time - -N = 1000000 -a = CLBuffer(N, dtypes.float32) -b = CLBuffer(N, dtypes.float32) -c = CLBuffer(N, dtypes.float32) - -prg = CLProgram("test", """__kernel void test(__global float *a, __global float *b, __global float *c) { - int idx = get_global_id(0); - a[idx] = b[idx] + c[idx]; -}""") -prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) -t1 = time.monotonic_ns() -e1 = prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) -CL.synchronize() -t2 = time.monotonic_ns() -time.sleep(3) -t3 = time.monotonic_ns() -e2 = prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) -CL.synchronize() -t4 = time.monotonic_ns() - -print(e1.profile.queued) -print(e1.profile.submit) -print(e1.profile.start) -print(e1.profile.end) - -print(e1, e2) -print(t2-t1, e1.profile.end - e1.profile.start) -print(t4-t3, e2.profile.end - e2.profile.start) -print(t3-t2, e2.profile.queued-e1.profile.end) -print((t3-t2) / (e2.profile.start-e1.profile.end), "ratio") - -print("ratio since boot", t1/e1.profile.start) - -print(e1.profile.start) -print(e1.profile.end) -print(e2.profile.start) -print(e2.profile.end) diff --git a/tinygrad/test/external/external_test_am.py b/tinygrad/test/external/external_test_am.py deleted file mode 100644 index 46014359..00000000 --- a/tinygrad/test/external/external_test_am.py +++ /dev/null @@ -1,180 +0,0 @@ -import unittest -from tinygrad.runtime.support.am.amdev import AMMemoryManager, AMPageTableTraverseContext -from tinygrad.runtime.support.am.ip import AM_GMC -from tinygrad.runtime.support.hcq import MMIOInterface -from tinygrad.runtime.autogen.am import am -from tinygrad.helpers import mv_address - -class FakeGMC(AM_GMC): - def __init__(self, adev): - self.adev = adev - self.vm_base = 0x0 - self.address_space_mask = (1 << 44) - 1 - def init_hw(self): pass - def flush_tlb(self, *args, **kwargs): pass - -class FakePCIDev: - def __init__(self): self.regions = [(0xc12300000000, 0xc12400000000, 0x0)] - -class FakeAM: - def __init__(self): - self.is_booting, self.smi_dev = True, False - self.pcidev = FakePCIDev() - self.vram_mv = memoryview(bytearray(4 << 30)) - self.vram = MMIOInterface(mv_address(self.vram_mv), self.vram_mv.nbytes) - self.gmc = FakeGMC(self) - self.mm = AMMemoryManager(self, vram_size=4 << 30) - self.is_booting = False - self.ip_ver = {am.GC_HWIP: (11, 0, 0)} - def paddr2cpu(self, paddr:int) -> int: return paddr + mv_address(self.vram) - def paddr2mc(self, paddr:int) -> int: return paddr - -# * PTE format: -# * 63:59 reserved -# * 58:57 reserved -# * 56 F -# * 55 L -# * 54 reserved -# * 53:52 SW -# * 51 T -# * 50:48 mtype -# * 47:12 4k physical page base address -# * 11:7 fragment -# * 6 write -# * 5 read -# * 4 exe -# * 3 Z -# * 2 snooped -# * 1 system -# * 0 valid -def helper_read_entry_components(entry_val): - return {"paddr": entry_val & 0x0000FFFFFFFFF000, "fragment":(entry_val >> 7) & 0x1f, "valid": entry_val & 0x1, - "read": (entry_val >> 5) & 0x1, "write": (entry_val >> 6) & 0x1, "exec": (entry_val >> 4) & 0x1, - "mtype": (entry_val >> 48) & 0x7, "T": (entry_val >> 51) & 0x1, "L": (entry_val >> 55) & 0x1, "F": (entry_val >> 56) & 0x1} - -class TestAMPageTable(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.d = [FakeAM() for _ in range(2)] - - def test_page_table_walkers(self): - mm = self.d[0].mm - - for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000), - (0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]: - exteranl_va = va + AMMemoryManager.va_allocator.base - mm.map_range(vaddr=exteranl_va, size=sz, paddrs=[(va, sz)]) - - ctx = AMPageTableTraverseContext(self.d[0], mm.root_page_table, exteranl_va) - results = list(ctx.next(sz)) - - total_covered = 0 - for tup in results: - _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup - total_covered += _n_ptes * _pte_covers - - assert total_covered == sz, f"Expected total coverage {total_covered} to be {sz}" - - for tup in results: - _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup - for i in range(_n_ptes): - pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) - assert pte['paddr'] == va + _offset + i * _pte_covers, f"Expected paddr {pte['paddr']:#x} to be {va + _offset + i * _pte_covers:#x}" - assert pte['valid'] == 1 - - mm.unmap_range(va, sz) - - for tup in results: - _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup - for i in range(_n_ptes): - pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) - assert pte['paddr'] == 0 - assert pte['valid'] == 0 - - def test_double_map(self): - mm0 = self.d[0].mm - - for va,sz in [(0x10000, 0x3000), (0x1000000, 0x1000000), (0x12000, 0x4000)]: - exteranl_va = va + AMMemoryManager.va_allocator.base - mm0.map_range(vaddr=exteranl_va, size=sz, paddrs=[(va, sz)]) - - with self.assertRaises(AssertionError): - mm0.map_range(vaddr=exteranl_va, size=0x1000, paddrs=[(va, sz)]) - - with self.assertRaises(AssertionError): - mm0.map_range(vaddr=exteranl_va, size=0x100000, paddrs=[(va, sz)]) - - with self.assertRaises(AssertionError): - mm0.map_range(vaddr=exteranl_va + 0x1000, size=0x1000, paddrs=[(va, sz)]) - - with self.assertRaises(AssertionError): - mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddrs=[(va, sz)]) - - mm0.unmap_range(vaddr=exteranl_va, size=sz) - - # Finally can map and check paddrs - mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddrs=[(0xdead0000, 0x1000), (0xdead1000, 0xff000)]) - - ctx = AMPageTableTraverseContext(self.d[0], mm0.root_page_table, exteranl_va + 0x2000) - for tup in ctx.next(0x100000): - _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup - for i in range(_n_ptes): - pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) - assert pte['paddr'] == 0xdead0000 + _offset + i * _pte_covers, f"paddr {pte['paddr']:#x} not {0xdead0000 + _offset + i * _pte_covers:#x}" - assert pte['valid'] == 1 - - mm0.unmap_range(vaddr=exteranl_va + 0x2000, size=0x100000) - - def test_try_bad_unmap(self): - mm0 = self.d[0].mm - - with self.assertRaises(AssertionError): - mm0.unmap_range(0x10000, 0x3000) - - mm0.map_range(0x10000, 0x3000, paddrs=[(0x10000, 0x3000)]) - mm0.unmap_range(0x10000, 0x3000) - - with self.assertRaises(AssertionError): - mm0.unmap_range(0x10000, 0x3000) - - mm0.map_range(0x10000, 0x3000, paddrs=[(0x10000, 0x3000)]) - mm0.unmap_range(0x10000, 0x3000) - - with self.assertRaises(AssertionError): - mm0.unmap_range(0x10000, 0x3000) - - def test_free_pt(self): - mm0 = self.d[0].mm - - # offset from start - for off in [0, 0x3000, 0x10000]: - mm0.map_range(0x1000000 + off, (2 << 20) - off, paddrs=[(0x10000, 0x1000)] * (512 - off // 0x1000)) - mm0.unmap_range(0x1000000 + off, (2 << 20) - off) - mm0.map_range(0x1000000, 2 << 20, paddrs=[(0x10000, 2 << 20)]) - mm0.unmap_range(0x1000000, 2 << 20) - - # offset from end - for off in [0x1000, 0x20000]: - mm0.map_range(0x1000000, (2 << 20) - off, paddrs=[(0x10000, 0x1000)] * (512 - off // 0x1000)) - mm0.unmap_range(0x1000000, (2 << 20) - off) - mm0.map_range(0x1000000, 2 << 20, paddrs=[(0x10000, 2 << 20)]) - mm0.unmap_range(0x1000000, 2 << 20) - - def test_frag_size(self): - mm0 = self.d[0].mm - - def must_cover_checker(va, sz): - ans = (1 << (mm0._frag_size(va=va, sz=sz, must_cover=True) + 12)) - assert va % ans == 0 and sz % ans == 0 and (va % (2 * ans) != 0 or sz % (2 * ans) != 0), f"va {va:#x} sz {sz:#x} ans {ans:#x}" - - def not_cover_checker(va, sz): - ans = (1 << (mm0._frag_size(va=va, sz=sz, must_cover=False) + 12)) - assert va % ans == 0 and ans <= sz and (va % (2 * ans) != 0 or (2 * ans) > sz), f"va {va:#x} sz {sz:#x} ans {ans:#x}" - - for va, sz in [(0x0, 0x1000), (0x1000, 0x2000), (0x1000, 0x3000), (0x2000, 0x2000), (0x4000, 0x8000), (0x8000, 0x4000), (0x10000, 0x4000), - (0x0, 0x4000), (0x10000, 0x4000), (0x10000, 0x40000), (0x10001000, 0x40000), (0x100001000, 0x3000)]: - must_cover_checker(va, sz) - not_cover_checker(va, sz) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/external/external_test_amd.py b/tinygrad/test/external/external_test_amd.py deleted file mode 100644 index dd13353a..00000000 --- a/tinygrad/test/external/external_test_amd.py +++ /dev/null @@ -1,28 +0,0 @@ -import unittest -from tinygrad import Device, Tensor -from tinygrad.engine.schedule import create_schedule -from tinygrad.runtime.ops_amd import AMDDevice - -class TestAMD(unittest.TestCase): - @classmethod - def setUpClass(self): - TestAMD.d0: AMDDevice = Device["AMD"] - TestAMD.a = Tensor([0.,1.], device="AMD").realize() - TestAMD.b = self.a + 1 - si = create_schedule([self.b.uop])[-1] - TestAMD.d0_runner = TestAMD.d0.get_runner(*si.ast) - TestAMD.b.uop.buffer.allocate() - - def test_amd_ring_64bit_doorbell(self): - TestAMD.d0.pm4_write_pointer[0] = TestAMD.d0.pm4_write_pointer[0] + (2 << 32) - TestAMD.d0.pm4_ring.size // 4 - for _ in range(2000): - TestAMD.d0_runner.clprg(TestAMD.b.uop.buffer._buf, TestAMD.a.uop.buffer._buf, - global_size=TestAMD.d0_runner.global_size, local_size=TestAMD.d0_runner.local_size) - TestAMD.d0_runner.clprg(TestAMD.a.uop.buffer._buf, TestAMD.b.uop.buffer._buf, - global_size=TestAMD.d0_runner.global_size, local_size=TestAMD.d0_runner.local_size) - val = TestAMD.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 4000.0, f"got val {val}" - -if __name__ == "__main__": - unittest.main() - diff --git a/tinygrad/test/external/external_test_datasets.py b/tinygrad/test/external/external_test_datasets.py deleted file mode 100644 index 19e58d80..00000000 --- a/tinygrad/test/external/external_test_datasets.py +++ /dev/null @@ -1,171 +0,0 @@ -from extra.datasets.kits19 import iterate, preprocess -from examples.mlperf.dataloader import batch_load_unet3d, batch_load_retinanet -from test.external.mlperf_retinanet.coco_utils import get_openimages -from test.external.mlperf_retinanet.openimages import postprocess_targets -from test.external.mlperf_retinanet.presets import DetectionPresetTrain, DetectionPresetEval -from test.external.mlperf_retinanet.model.transform import GeneralizedRCNNTransform -from test.external.mlperf_unet3d.kits19 import PytTrain, PytVal -from tinygrad.helpers import temp -from pathlib import Path -from pycocotools.coco import COCO - -import json -import nibabel as nib -import numpy as np -import os -import PIL -import random -import tempfile -import torch -import unittest - -class ExternalTestDatasets(unittest.TestCase): - def _set_seed(self): - np.random.seed(42) - random.seed(42) - torch.manual_seed(42) - -class TestKiTS19Dataset(ExternalTestDatasets): - def _create_samples(self, val, num_samples=2): - self._set_seed() - - img, lbl = np.random.rand(190, 392, 392).astype(np.float32), np.random.randint(0, 100, size=(190, 392, 392)).astype(np.uint8) - img, lbl = nib.Nifti1Image(img, np.eye(4)), nib.Nifti1Image(lbl, np.eye(4)) - dataset = "val" if val else "train" - preproc_pth = Path(tempfile.gettempdir() + f"/{dataset}") - - for i in range(num_samples): - os.makedirs(tempfile.gettempdir() + f"/case_000{i}", exist_ok=True) - nib.save(img, temp(f"case_000{i}/imaging.nii.gz")) - nib.save(lbl, temp(f"case_000{i}/segmentation.nii.gz")) - - preproc_img, preproc_lbl = preprocess(Path(tempfile.gettempdir()) / f"case_000{i}") - preproc_img_pth, preproc_lbl_pth = temp(f"{dataset}/case_000{i}_x.npy"), temp(f"{dataset}/case_000{i}_y.npy") - - os.makedirs(preproc_pth, exist_ok=True) - np.save(preproc_img_pth, preproc_img, allow_pickle=False) - np.save(preproc_lbl_pth, preproc_lbl, allow_pickle=False) - - return preproc_pth, list(preproc_pth.glob("*_x.npy")), list(preproc_pth.glob("*_y.npy")) - - def _create_ref_dataloader(self, preproc_img_pths, preproc_lbl_pths, val): - if val: - dataset = PytVal(preproc_img_pths, preproc_lbl_pths) - else: - dataset = PytTrain(preproc_img_pths, preproc_lbl_pths, patch_size=(128, 128, 128), oversampling=0.4) - - return iter(dataset) - - def _create_tinygrad_dataloader(self, preproc_pth, val, batch_size=1, shuffle=False, seed=42, use_old_dataloader=False): - if use_old_dataloader: - dataset = iterate(list(Path(tempfile.gettempdir()).glob("case_*")), preprocessed_dir=preproc_pth, val=val, shuffle=shuffle, bs=batch_size) - else: - dataset = batch_load_unet3d(preproc_pth, batch_size=batch_size, val=val, shuffle=shuffle, seed=seed) - - return iter(dataset) - - def test_training_set(self): - preproc_pth, preproc_img_pths, preproc_lbl_pths = self._create_samples(False) - ref_dataset = self._create_ref_dataloader(preproc_img_pths, preproc_lbl_pths, False) - tinygrad_dataset = self._create_tinygrad_dataloader(preproc_pth, False) - - for ref_sample, tinygrad_sample in zip(ref_dataset, tinygrad_dataset): - self._set_seed() - - np.testing.assert_equal(tinygrad_sample[0][:, 0].numpy(), ref_sample[0]) - np.testing.assert_equal(tinygrad_sample[1][:, 0].numpy(), ref_sample[1]) - - def test_validation_set(self): - preproc_pth, preproc_img_pths, preproc_lbl_pths = self._create_samples(True) - ref_dataset = self._create_ref_dataloader(preproc_img_pths, preproc_lbl_pths, True) - tinygrad_dataset = self._create_tinygrad_dataloader(preproc_pth, True, use_old_dataloader=True) - - for ref_sample, tinygrad_sample in zip(ref_dataset, tinygrad_dataset): - np.testing.assert_equal(tinygrad_sample[0][:, 0], ref_sample[0]) - np.testing.assert_equal(tinygrad_sample[1], ref_sample[1]) - -class TestOpenImagesDataset(ExternalTestDatasets): - @classmethod - def setUpClass(cls): - cls.img_mean = [0.485, 0.456, 0.406] - cls.img_std = [0.229, 0.224, 0.225] - cls.img_size = (800, 800) - - def _create_samples(self, subset): - os.makedirs((base_dir := Path(tempfile.gettempdir() + "/openimages")) / f"{subset}/data", exist_ok=True) - os.makedirs(base_dir / Path(f"{subset}/labels"), exist_ok=True) - - lbls, img_size = ["cls_1", "cls_2"], (447, 1024) - cats = [{"id": i, "name": c, "supercategory": None} for i, c in enumerate(lbls)] - imgs = [ - { - "id": i, "file_name": f"img_{i}.jpg", - "height": img_size[0], "width": img_size[1], - "subset": subset, "license": None, "coco_url": None - } - for i in range(len(lbls)) - ] - annots = [ - { - "id": i, "image_id": i, - "category_id": 0, "bbox": [23.217183744, 31.75409775, 964.1241282560001, 326.09017434000003], - "area": 314391.4050683996, "IsOccluded": 0, - "IsInside": 0, "IsDepiction": 0, - "IsTruncated": 0, "IsGroupOf": 0, - "iscrowd": 0 - } - for i in range(len(lbls)) - ] - info = {"dataset": "openimages_mlperf", "version": "v6"} - coco_annotations = {"info": info, "licenses": [], "categories": cats, "images": imgs, "annotations": annots} - - with open(ann_file:=base_dir / Path(f"{subset}/labels/openimages-mlperf.json"), "w") as fp: - json.dump(coco_annotations, fp) - - for i in range(len(lbls)): - img = PIL.Image.new("RGB", img_size[::-1]) - img.save(base_dir / Path(f"{subset}/data/img_{i}.jpg")) - - return base_dir, ann_file - - def _create_ref_dataloader(self, base_dir, ann_file, subset): - self._set_seed() - transforms = DetectionPresetTrain("hflip") if subset == "train" else DetectionPresetEval() - return iter(get_openimages(ann_file.stem, base_dir, subset, transforms)) - - def _create_tinygrad_dataloader(self, base_dir, ann_file, subset, batch_size=1, seed=42): - return iter(batch_load_retinanet(COCO(ann_file), subset == "validation", base_dir, batch_size=batch_size, shuffle=False, seed=seed)) - - def _normalize_img(self, img): - return ((img / 255.0) - np.array(self.img_mean)) / np.array(self.img_std) - - def test_training_set(self): - base_dir, ann_file = self._create_samples((subset:="train")) - transform = GeneralizedRCNNTransform(self.img_size, self.img_mean, self.img_std) - anchors = torch.ones((120087, 4)) - - tinygrad_dataloader = self._create_tinygrad_dataloader(base_dir, ann_file, subset) - ref_dataloader = self._create_ref_dataloader(base_dir, ann_file, subset) - - for ((tinygrad_img, tinygrad_boxes, tinygrad_labels, _, _, _), (ref_img, ref_tgt)) in zip(tinygrad_dataloader, ref_dataloader): - ref_img, ref_tgt = transform(ref_img.unsqueeze(0), [ref_tgt]) - ref_tgt = postprocess_targets(ref_tgt, anchors.unsqueeze(0)) - ref_boxes, ref_labels = ref_tgt[0]["boxes"], ref_tgt[0]["labels"] - - np.testing.assert_allclose(self._normalize_img(tinygrad_img.numpy()), ref_img.tensors.transpose(1, 3).numpy(), rtol=1e-6) - np.testing.assert_equal(tinygrad_boxes[0].numpy(), ref_boxes.numpy()) - np.testing.assert_equal(tinygrad_labels[0].numpy(), ref_labels.numpy()) - - def test_validation_set(self): - base_dir, ann_file = self._create_samples((subset:="validation")) - transform = GeneralizedRCNNTransform(self.img_size, self.img_mean, self.img_std) - - tinygrad_dataloader = self._create_tinygrad_dataloader(base_dir, ann_file, subset) - ref_dataloader = self._create_ref_dataloader(base_dir, ann_file, "val") - - for ((tinygrad_img, _, _, _), (ref_img, _)) in zip(tinygrad_dataloader, ref_dataloader): - ref_img, _ = transform(ref_img.unsqueeze(0)) - np.testing.assert_allclose(self._normalize_img(tinygrad_img.numpy()), ref_img.tensors.transpose(1, 3).numpy(), rtol=1e-6) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_embedding.py b/tinygrad/test/external/external_test_embedding.py deleted file mode 100644 index 9d6bd7f2..00000000 --- a/tinygrad/test/external/external_test_embedding.py +++ /dev/null @@ -1,8 +0,0 @@ -from tinygrad.tensor import Tensor -from tinygrad.nn import Embedding - -if __name__ == "__main__": - vocab_size = 50257 - dim = 128 - test = Embedding(vocab_size, dim) - ret = test(Tensor([[1,2,3]])).numpy() diff --git a/tinygrad/test/external/external_test_example.py b/tinygrad/test/external/external_test_example.py deleted file mode 100644 index 86c3958c..00000000 --- a/tinygrad/test/external/external_test_example.py +++ /dev/null @@ -1,73 +0,0 @@ -import unittest -from tinygrad import Device -from tinygrad.tensor import Tensor -from tinygrad.helpers import getenv, CI - -def multidevice_test(fxn): - exclude_devices = getenv("EXCLUDE_DEVICES", "").split(",") - def ret(self): - for device in Device._devices: - if device in ["REMOTE", "DISK", "NPY", "FAKE", "DSP", "NULL"]: continue - if not CI: print(device) - if device in exclude_devices: - if not CI: print(f"WARNING: {device} test is excluded") - continue - with self.subTest(device=device): - try: - Device[device] - except Exception: - if not CI: print(f"WARNING: {device} test isn't running") - continue - fxn(self, device) - return ret - -class TestExample(unittest.TestCase): - @multidevice_test - def test_convert_to_cpu(self, device): - a = Tensor([[1,2],[3,4]], device=device) - assert a.numpy().shape == (2,2) - b = a.to("CPU") - assert b.numpy().shape == (2,2) - - @multidevice_test - def test_2_plus_3(self, device): - a = Tensor([2], device=device) - b = Tensor([3], device=device) - result = a + b - print(f"{a.numpy()} + {b.numpy()} = {result.numpy()}") - assert result.numpy()[0] == 5. - - @multidevice_test - def test_example_readme(self, device): - x = Tensor.eye(3, device=device, requires_grad=True) - y = Tensor([[2.0,0,-2.0]], device=device, requires_grad=True) - z = y.matmul(x).sum() - z.backward() - - x.grad.numpy() # dz/dx - y.grad.numpy() # dz/dy - - assert x.grad.device == device - assert y.grad.device == device - - @multidevice_test - def test_example_matmul(self, device): - try: - Device[device] - except Exception: - print(f"WARNING: {device} test isn't running") - return - - x = Tensor.eye(64, device=device, requires_grad=True) - y = Tensor.eye(64, device=device, requires_grad=True) - z = y.matmul(x).sum() - z.backward() - - x.grad.numpy() # dz/dx - y.grad.numpy() # dz/dy - - assert x.grad.device == device - assert y.grad.device == device - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_hcq.py b/tinygrad/test/external/external_test_hcq.py deleted file mode 100644 index 2ae0371f..00000000 --- a/tinygrad/test/external/external_test_hcq.py +++ /dev/null @@ -1,326 +0,0 @@ -import unittest, ctypes, struct, time, array -from tinygrad import Device, Tensor, dtypes -from tinygrad.helpers import to_mv, CI -from tinygrad.device import Buffer, BufferSpec -from tinygrad.engine.realize import get_runner - -def _time_queue(q, d): - st = time.perf_counter() - q.signal(d.timeline_signal, d.timeline_value) - q.submit(d) - d._wait_signal(d.timeline_signal, d.timeline_value) - d.timeline_value += 1 - return time.perf_counter() - st - -@unittest.skipUnless(Device.DEFAULT in ["NV", "AMD"], "Runs only on NV or AMD") -class TestHCQ(unittest.TestCase): - @classmethod - def setUpClass(self): - TestHCQ.d0 = Device[Device.DEFAULT] - #TestHCQ.d1: AMDDevice = Device["AMD:1"] - TestHCQ.a = Tensor([0.,1.], device=Device.DEFAULT).realize() - TestHCQ.b = self.a + 1 - si = self.b.schedule()[-1] - TestHCQ.runner = get_runner(TestHCQ.d0.device, si.ast) - TestHCQ.b.uop.buffer.allocate() - # wow that's a lot of abstraction layers - TestHCQ.addr = struct.pack("QQ", TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr) - TestHCQ.addr2 = struct.pack("QQ", TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr) - TestHCQ.kernargs_off = TestHCQ.runner._prg.kernargs_offset - TestHCQ.kernargs_size = TestHCQ.runner._prg.kernargs_alloc_size - ctypes.memmove(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_off, TestHCQ.addr, len(TestHCQ.addr)) - ctypes.memmove(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size+TestHCQ.kernargs_off, TestHCQ.addr2, len(TestHCQ.addr2)) - - if Device.DEFAULT == "AMD": - from tinygrad.runtime.ops_amd import HWQueue, HWPM4Queue - TestHCQ.compute_queue = HWPM4Queue - TestHCQ.copy_queue = HWQueue - elif Device.DEFAULT == "NV": - from tinygrad.runtime.ops_nv import HWQueue, HWQueue - # nv need to copy constbuffer there as well - to_mv(TestHCQ.d0.kernargs_ptr, 0x160).cast('I')[:] = array.array('I', TestHCQ.runner._prg.constbuffer_0) - to_mv(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, 0x160).cast('I')[:] = array.array('I', TestHCQ.runner._prg.constbuffer_0) - TestHCQ.compute_queue = HWQueue - TestHCQ.copy_queue = HWQueue - - def setUp(self): - TestHCQ.d0.synchronize() - TestHCQ.a.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - TestHCQ.b.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 0)))) - TestHCQ.d0.synchronize() # wait for copyins to complete - - def test_run_1000_times_one_submit(self): - temp_signal, temp_value = TestHCQ.d0._alloc_signal(value=0), 0 - q = TestHCQ.compute_queue() - for _ in range(1000): - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, temp_value + 1).wait(temp_signal, temp_value + 1) - temp_value += 1 - - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, temp_value + 1).wait(temp_signal, temp_value + 1) - temp_value += 1 - - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q.submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 2000.0, f"got val {val}" - - def test_run_1000_times(self): - temp_signal = TestHCQ.d0._alloc_signal(value=0) - q = TestHCQ.compute_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, 2).wait(temp_signal, 2) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, - TestHCQ.runner.p.local_size) - for _ in range(1000): - TestHCQ.d0._set_signal(temp_signal, 1) - q.submit(TestHCQ.d0) - TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 2000.0, f"got val {val}" - - def test_run_to_3(self): - temp_signal = TestHCQ.d0._alloc_signal(value=0) - q = TestHCQ.compute_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, 1).wait(temp_signal, 1) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, 2).wait(temp_signal, 2) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 3.0, f"got val {val}" - - def test_update_exec(self): - q = TestHCQ.compute_queue() - exec_cmd_idx = len(q) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.update_exec(exec_cmd_idx, (1,1,1), (1,1,1)) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 0.0, f"got val {val}, should not be updated" - - @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") - def test_bind_run(self): - temp_signal = TestHCQ.d0._alloc_signal(value=0) - q = TestHCQ.compute_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(temp_signal, 2).wait(temp_signal, 2) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, - TestHCQ.runner.p.local_size) - q.bind(TestHCQ.d0) - for _ in range(1000): - TestHCQ.d0._set_signal(temp_signal, 1) - q.submit(TestHCQ.d0) - TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 2000.0, f"got val {val}" - - @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") - def test_update_exec_binded(self): - q = TestHCQ.compute_queue() - exec_ptr = q.ptr() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q.bind(TestHCQ.d0) - - q.update_exec(exec_ptr, (1,1,1), (1,1,1)) - q.submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 0.0, f"got val {val}, should not be updated" - - @unittest.skipIf(CI, "Can't handle async update on CPU") - def test_wait_signal(self): - temp_signal = TestHCQ.d0._alloc_signal(value=0) - TestHCQ.compute_queue().wait(temp_signal, value=1).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - with self.assertRaises(RuntimeError): - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) - # clean up - TestHCQ.d0._set_signal(temp_signal, 1) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=100) - TestHCQ.d0.timeline_value += 1 - - @unittest.skipIf(CI, "Can't handle async update on CPU") - def test_wait_copy_signal(self): - temp_signal = TestHCQ.d0._alloc_signal(value=0) - TestHCQ.copy_queue().wait(temp_signal, value=1).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - with self.assertRaises(RuntimeError): - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) - # clean up - TestHCQ.d0._set_signal(temp_signal, 1) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=100) - TestHCQ.d0.timeline_value += 1 - - def test_run_normal(self): - q = TestHCQ.compute_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - - def test_submit_empty_queues(self): - TestHCQ.compute_queue().submit(TestHCQ.d0) - TestHCQ.copy_queue().submit(TestHCQ.d0) - - def test_signal_timeout(self): - with self.assertRaises(RuntimeError): - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 122, timeout=50) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1, timeout=50) - - def test_signal(self): - new_timeline_value = TestHCQ.d0.timeline_value + 0xff - TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, new_timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, new_timeline_value) - TestHCQ.d0.timeline_value = new_timeline_value + 1 # update to not break runtime - - def test_copy_signal(self): - new_timeline_value = TestHCQ.d0.timeline_value + 0xff - TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, new_timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, new_timeline_value) - TestHCQ.d0.timeline_value = new_timeline_value + 1 # update to not break runtime - - def test_run_signal(self): - q = TestHCQ.compute_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q.submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - - def test_copy_1000_times(self): - q = TestHCQ.copy_queue() - q.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) - q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) - for _ in range(1000): - q.submit(TestHCQ.d0) - TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - # confirm the signal didn't exceed the put value - with self.assertRaises(RuntimeError): - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 1, timeout=50) - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 0.0, f"got val {val}" - - def test_copy(self): - q = TestHCQ.copy_queue() - q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q.submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 1.0, f"got val {val}" - - @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") - def test_bind_copy(self): - q = TestHCQ.copy_queue() - q.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) - q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) - q.bind(TestHCQ.d0) - for _ in range(1000): - q.submit(TestHCQ.d0) - TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - # confirm the signal didn't exceed the put value - with self.assertRaises(RuntimeError): - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 1, timeout=50) - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 0.0, f"got val {val}" - - def test_copy_bandwidth(self): - # THEORY: the bandwidth is low here because it's only using one SDMA queue. I suspect it's more stable like this at least. - SZ = 2_000_000_000 - a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - b = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - q = TestHCQ.copy_queue() - q.copy(a._buf.va_addr, b._buf.va_addr, SZ) - et = _time_queue(q, TestHCQ.d0) - gb_s = (SZ/1e9)/et - print(f"same device copy: {et*1e3:.2f} ms, {gb_s:.2f} GB/s") - assert (0.3 if CI else 10) <= gb_s <= 1000 - - def test_cross_device_copy_bandwidth(self): - SZ = 2_000_000_000 - b = Buffer(f"{Device.DEFAULT}:1", SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - TestHCQ.d0._gpu_map(b._buf) - q = TestHCQ.copy_queue() - q.copy(a._buf.va_addr, b._buf.va_addr, SZ) - et = _time_queue(q, TestHCQ.d0) - gb_s = (SZ/1e9)/et - print(f"cross device copy: {et*1e3:.2f} ms, {gb_s:.2f} GB/s") - assert (0.3 if CI else 2) <= gb_s <= 50 - - def test_interleave_compute_and_copy(self): - q = TestHCQ.compute_queue() - qc = TestHCQ.copy_queue() - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) # b = [1, 2] - q.signal(sig:=TestHCQ.d0._alloc_signal(value=0), value=1) - qc.wait(sig, value=1) - qc.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) - qc.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - qc.submit(TestHCQ.d0) - time.sleep(0.02) # give it time for the wait to fail - q.submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - - def test_cross_device_signal(self): - d1 = Device[f"{Device.DEFAULT}:1"] - q1 = TestHCQ.compute_queue() - q2 = TestHCQ.compute_queue() - q1.signal(sig:=TestHCQ.d0._alloc_signal(value=0), value=0xfff) - q2.wait(sig, value=0xfff) - q2.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q2.submit(TestHCQ.d0) - q1.signal(d1.timeline_signal, d1.timeline_value) - q1.submit(d1) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - d1._wait_signal(d1.timeline_signal, d1.timeline_value) - d1.timeline_value += 1 - - def test_timeline_signal_rollover(self): - # NV 64bit, AMD 32bit - TestHCQ.d0.timeline_value = (1 << 64) - 20 if Device.DEFAULT == "NV" else (1 << 32) - 20 # close value to reset - TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) - - for _ in range(40): - q = TestHCQ.compute_queue() - q.wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) - q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) - q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/external/external_test_hcq_fuzz_failures.py b/tinygrad/test/external/external_test_hcq_fuzz_failures.py deleted file mode 100644 index 09b3633d..00000000 --- a/tinygrad/test/external/external_test_hcq_fuzz_failures.py +++ /dev/null @@ -1,61 +0,0 @@ -# ruff: noqa: E501 -import os -os.environ["VALIDATE_HCQ"]="1" - -import unittest, random -import numpy as np -from tinygrad.codegen.kernel import Kernel, KernelOptError -from tinygrad.device import is_dtype_supported -from tinygrad.uop.ops import UOp, Ops -from tinygrad.engine.search import Opt, OptOps -from tinygrad import Device, dtypes, Tensor -from test.external.fuzz_linearizer import compare_linearizer, compare_states, get_fuzz_rawbuf_like - -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -def helper_test_lin(lin: Kernel, opts, failed_platforms, validate_device, rtol=1e-2, atol=1e-2): - if any(b.dtype.base == dtypes.half for b in lin.membufs) and not is_dtype_supported(dtypes.half): return - if any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) and not is_dtype_supported(dtypes.bfloat16): return - - try: - lin.apply_opts(opts) - except KernelOptError: - # it's considered fixed if we invalidated the opts - assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" - return - - (msg, rawbufs, var_vals, ground_truth, state1) = compare_linearizer(lin, rtol=rtol, atol=atol) - if msg in ["PASS", "KernelOptError"]: - # it's considered fixed if we invalidated the opts - assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" - else: - assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {msg}" - - validate_lin = lin.copy() - validate_lin.opts = validate_device.renderer - validate_rawbufs = [get_fuzz_rawbuf_like(x, copy=True, force_device=validate_device.dname) for x in rawbufs] - (_msg, _, _, _, state2) = compare_linearizer(validate_lin, validate_rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) - - if _msg in ["PASS"] and compare_states(state1, state2): - assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" - else: - assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {msg}" - - return lin - -class TestHCQFuzzFailures(unittest.TestCase): - def setUp(self): - random.seed(42) - np.random.seed(42) - Tensor.manual_seed(42) - - @unittest.skipUnless(Device.DEFAULT in {"QCOM"}, "for QCOM") - def test_failure_1(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( UOp(Ops.STORE, dtypes.void, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=0, mask=None, contiguous=True),)), src=()), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=1, src=()), x39:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=0, mask=((0, 1), (0, 6)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()), x39,)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=3, src=()), x46:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-6, mask=((0, 1), (6, 12)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=4, src=()), x46,)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=5, src=()), x54:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (12, 13)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=6, src=()), x54,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=7, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-13, mask=((0, 1), (13, 17)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=8, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-17, mask=((0, 1), (17, 21)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=9, src=()), x68:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (21, 22)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=10, src=()), x68,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=11, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-22, mask=((0, 1), (22, 26)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=12, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-26, mask=((0, 1), (26, 30)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=13, src=()), x82:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (30, 31)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=14, src=()), x82,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=15, src=()), x90:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (31, 32)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=16, src=()), x90,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=17, src=()), x98:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (32, 33)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=18, src=()), x98,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=19, src=()), x106:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (33, 34)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=20, src=()), x106,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=21, src=()), x114:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (34, 35)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=22, src=()), x114,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=23, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-35, mask=((0, 1), (35, 39)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=24, src=()), x125:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (39, 40)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=25, src=()), x125,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=26, src=()), x133:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (40, 41)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=27, src=()), x133,)),)),)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=28, src=()), x140:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-41, mask=((0, 1), (41, 47)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=29, src=()), x140,)),)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=30, src=()), x147:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-47, mask=((0, 1), (47, 53)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=31, src=()), x147,)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=32, src=()), x155:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (53, 54)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=33, src=()), x155,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=34, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-54, mask=((0, 1), (54, 58)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=35, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-58, mask=((0, 1), (58, 62)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=36, src=()), x169:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (62, 63)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=37, src=()), x169,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=38, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-63, mask=((0, 1), (63, 67)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=39, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-67, mask=((0, 1), (67, 71)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=40, src=()), x183:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (71, 72)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=41, src=()), x183,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=42, src=()), x191:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (72, 73)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=43, src=()), x191,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=44, src=()), x199:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (73, 74)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=45, src=()), x199,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=46, src=()), x207:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (74, 75)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=47, src=()), x207,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=48, src=()), x215:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (75, 76)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=49, src=()), x215,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=50, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-76, mask=((0, 1), (76, 80)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=51, src=()), x226:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (80, 81)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=52, src=()), x226,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=53, src=()), x234:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (81, 82)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=54, src=()), x234,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=55, src=()), x243:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (82, 83)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=56, src=()), x243,)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=57, src=()), x250:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (83, 84)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=58, src=()), x250,)),)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 128, 4)), arg=59, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-84, mask=((0, 1), (84, 596)), contiguous=False),)), src=()),)),)),)),)),)) # noqa: E501 - - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[], validate_device=Device["GPU"]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_hip_compile.py b/tinygrad/test/external/external_test_hip_compile.py deleted file mode 100644 index 0edef873..00000000 --- a/tinygrad/test/external/external_test_hip_compile.py +++ /dev/null @@ -1,39 +0,0 @@ -import time, unittest -from tinygrad.runtime.support.hip_comgr import compile_hip -from tinygrad import Tensor -from tinygrad.device import Device -from tinygrad.engine.schedule import create_schedule -from tinygrad.codegen.kernel import Kernel - -class TestHIPCompileSpeed(unittest.TestCase): - @unittest.skipIf(Device.DEFAULT != "HIP", "only run on HIP") - def test_hip_compile(self): - a, b = Tensor([1,2,3,4,5]), Tensor([1,2,3,4,5]) - out = a + b - lin = Kernel(create_schedule([out.uop])[-1].ast[0]) - lin.linearize() - - reference = """ -#include - typedef long unsigned int size_t; - extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); - extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); - extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); - extern "C" __attribute__((global))void {name}(int* data0, const int* data1, const int* data2) {{ - int gidx0 = __ockl_get_group_id(0); /* 5 */ - int val0 = data1[gidx0]; - int val1 = data2[gidx0]; - data0[gidx0] = (val0+val1); - }} - """ - - def time_compile(code): - st = time.perf_counter() - compile_hip(code) - return (time.perf_counter() - st) * 1000 - - tinygrad_tm = min([time_compile(Device[Device.DEFAULT].renderer.render(f"test{i}", lin.uops)) for i in range(10)]) - ref_tm = min([time_compile(reference.format(name=f"test{i}")) for i in range(10)]) - print(f"tinygrad {tinygrad_tm:6.2f} ms") - print(f"reference {ref_tm:6.2f} ms") - assert (tinygrad_tm - ref_tm) <= 10 diff --git a/tinygrad/test/external/external_test_hsa_driver.py b/tinygrad/test/external/external_test_hsa_driver.py deleted file mode 100644 index 29ffaa23..00000000 --- a/tinygrad/test/external/external_test_hsa_driver.py +++ /dev/null @@ -1,116 +0,0 @@ -import ctypes, unittest -from tinygrad.helpers import init_c_struct_t -from tinygrad.device import Device, Buffer, BufferXfer -from tinygrad.dtype import dtypes -from tinygrad.runtime.support.hsa import AQLQueue -from tinygrad.runtime.graph.hsa import VirtAQLQueue, HSAGraph -from tinygrad.engine.realize import ExecItem - -def get_hsa_inc_prog(dev, inc=1): - prg = f""" -extern "C" __attribute__((global)) void test_inc(int* data0) {{ - data0[0] = (data0[0]+{inc}); -}} -""" - return dev.runtime("test_inc", dev.compiler.compile(prg)) - -def get_hsa_buffer_and_kernargs(dev): - test_buf = Buffer(Device.DEFAULT, 1, dtypes.int) - test_buf.copyin(memoryview(bytearray(4))) # zero mem - assert test_buf.as_buffer().cast('I')[0] == 0 # check mem is visible + sync to exec - - args_struct_t = init_c_struct_t(tuple([('f0', ctypes.c_void_p)])) - kernargs = dev.alloc_kernargs(8) - args_st = args_struct_t.from_address(kernargs) - args_st.__setattr__('f0', test_buf._buf) - dev.flush_hdp() - return test_buf, kernargs - -@unittest.skipUnless(Device.DEFAULT == "HSA", "only run on HSA") -class TestHSADriver(unittest.TestCase): - def test_hsa_simple_enqueue(self): - dev = Device[Device.DEFAULT] - queue = AQLQueue(dev, sz=256) - - clprg = get_hsa_inc_prog(dev, inc=1) - test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) - - queue.submit_kernel(clprg, [1,1,1], [1,1,1], kernargs) - queue.wait() - - assert test_buf.as_buffer().cast('I')[0] == 1, f"{test_buf.as_buffer().cast('I')[0]} != 1, all packets executed?" - del queue - - def test_hsa_ring_enqueue(self): - dev = Device[Device.DEFAULT] - - queue_size = 256 - exec_cnt = int(queue_size * 1.5) - queue = AQLQueue(dev, sz=queue_size) - - clprg_inc1 = get_hsa_inc_prog(dev, inc=1) - clprg_inc2 = get_hsa_inc_prog(dev, inc=2) - test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) - - for _ in range(exec_cnt): - queue.submit_kernel(clprg_inc1, [1,1,1], [1,1,1], kernargs) - for _ in range(exec_cnt): - queue.submit_kernel(clprg_inc2, [1,1,1], [1,1,1], kernargs) - queue.wait() - - expected = exec_cnt + exec_cnt * 2 - assert test_buf.as_buffer().cast('I')[0] == expected, f"{test_buf.as_buffer().cast('I')[0]} != {expected}, all packets executed?" - del queue - - def test_hsa_blit_enqueue(self): - dev = Device[Device.DEFAULT] - - queue_size = 256 - exec_cnt = 178 - queue = AQLQueue(dev, sz=queue_size) - - test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) - - # Using VirtAQLQueue to blit them - virt_queue_packets_cnt = 31 - virt_queue = VirtAQLQueue(dev, sz=virt_queue_packets_cnt) - - clprogs = [] - sum_per_blit = 0 - for i in range(virt_queue_packets_cnt): - sum_per_blit += i+1 - clprogs.append(get_hsa_inc_prog(dev, inc=i+1)) - - for i in range(virt_queue_packets_cnt): - virt_queue.submit_kernel(clprogs[i], [1,1,1], [1,1,1], kernargs) - - for _ in range(exec_cnt): - queue.blit_packets(virt_queue.queue_base, virt_queue.packets_count) - queue.wait() - - expected = exec_cnt * sum_per_blit - assert test_buf.as_buffer().cast('I')[0] == expected, f"{test_buf.as_buffer().cast('I')[0]} != {expected}, all packets executed?" - del queue, clprogs - - def test_hsa_copies_sync(self): - d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" - - test_buf0 = Buffer(d0, 1, dtypes.int) - test_buf1 = Buffer(d0, 1, dtypes.int) - test_buf2 = Buffer(d1, 1, dtypes.int) - test_buf0.copyin(memoryview(bytearray(1*4))) - test_buf1.copyin(memoryview(bytearray(1*4))) - test_buf2.copyin(memoryview(bytearray(1*4))) - - jit_cache = [ExecItem(BufferXfer(), [test_buf0, test_buf2]), ExecItem(BufferXfer(), [test_buf2, test_buf1])] - graph = HSAGraph(jit_cache, [], {}) - - for i in range(10000): - test_buf0.copyin(memoryview(bytearray(1*4))) - test_buf2.copyin(memoryview(bytearray(int.to_bytes(4, length=1*4, byteorder='little')))) - graph([], {}) - assert test_buf0.as_buffer().cast('I')[0] == 4 - assert test_buf2.as_buffer().cast('I')[0] == 0 - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_image.py b/tinygrad/test/external/external_test_image.py deleted file mode 100644 index 1c2cc397..00000000 --- a/tinygrad/test/external/external_test_image.py +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env python -import os -import unittest -import numpy as np -if 'IMAGE' not in os.environ: - os.environ['IMAGE'] = '2' -os.environ['GPU'] = '1' -os.environ['OPT'] = '2' -from tinygrad.tensor import Tensor -from tinygrad.nn import Conv2d - -class TestImage(unittest.TestCase): - def test_create_image(self): - t = Tensor.ones(128, 128, 1) - t = t.reshape(128, 32, 4) + 3 - t.realize() - np.testing.assert_array_equal(t.numpy(), np.ones((128,32,4))*4) - - def test_sum_image(self): - t1 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 3 - t1.realize() - t1 = t1.sum() - t1.realize() - assert t1.numpy() == 16*4*4*4, f"got {t1.numpy()}" - - def test_add_image(self): - t1 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 3 - t2 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 4 - t1.realize() - t2.realize() - t3 = t1 + t2 - t3.realize() - np.testing.assert_array_equal(t3.numpy(), np.ones((16,4,4))*9) - - def test_padded_conv(self): - bs, in_chans, out_chans = 1,12,32 - tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) - tiny_dat = Tensor.ones(bs, 12, 64, 128) - tiny_conv(tiny_dat).realize() - - def test_op_conv(self): - bs, in_chans, out_chans = 1,12,32 - tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) - tiny_dconv = Conv2d(out_chans, out_chans, 1, bias=None, padding=0) - tiny_dat = Tensor.ones(bs, 12, 64, 128) - p2 = tiny_conv(tiny_dat).relu() - p2 = tiny_dconv(p2) - p2.realize() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_jit_on_models.py b/tinygrad/test/external/external_test_jit_on_models.py deleted file mode 100644 index c04a6ed8..00000000 --- a/tinygrad/test/external/external_test_jit_on_models.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad import Tensor, dtypes -from tinygrad.engine.jit import TinyJit -from tinygrad.helpers import CI -from test.helpers import derandomize_model - -from examples.llama import Transformer - -def helper_test_jitted_correctness(gen, train, train_jit): - nojit = train(*gen()).numpy() - for _ in range(5): jit = train_jit(*gen()).numpy() - np.testing.assert_allclose(nojit, jit, rtol=1e-3, atol=1e-5) - -class TestJittedModels(unittest.TestCase): - def test_jitted_tiny_llama(self): - old_float = dtypes.default_float - dtypes.default_float = dtypes.float16 - - args_tiny = {"dim": 1024, "hidden_dim": 1024, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 1000} - model = Transformer(**args_tiny) - derandomize_model(model) - def test(t): return model(t, 0).realize() - - @TinyJit - def test_jit(t): return model(t, 0).realize() - helper_test_jitted_correctness(lambda: (Tensor([[1,]]),), test, test_jit) - dtypes.default_float = old_float - - @unittest.skipUnless(not CI, "huge for CI") - def test_jitted_stable_diffusion(self): - from examples.stable_diffusion import UNetModel, unet_params - model = UNetModel(**unet_params) - derandomize_model(model) - def test(t, t2): return model(t, 801, t2).realize() - - @TinyJit - def test_jit(t, t2): return model(t, 801, t2).realize() - helper_test_jitted_correctness(lambda: (Tensor.randn(1, 4, 16, 16),Tensor.randn(1, 77, 768)), test, test_jit) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/external/external_test_keccak.py b/tinygrad/test/external/external_test_keccak.py deleted file mode 100644 index bccffe8b..00000000 --- a/tinygrad/test/external/external_test_keccak.py +++ /dev/null @@ -1,31 +0,0 @@ -import unittest, zipfile, re -from tinygrad import Tensor -from tinygrad.helpers import fetch, tqdm - -SHA3_URL = "https://csrc.nist.gov/CSRC/media/Projects/Cryptographic-Algorithm-Validation-Program/documents/sha3/sha-3bytetestvectors.zip" -SHAKE_URL = "https://csrc.nist.gov/CSRC/media/Projects/Cryptographic-Algorithm-Validation-Program/documents/sha3/shakebytetestvectors.zip" - -class TestExternalKeccak(unittest.TestCase): - def test_sha3_224(self): self.check_nist_vectors(SHA3_URL, ["SHA3_224LongMsg.rsp", "SHA3_224ShortMsg.rsp"], "sha3_224") - def test_sha3_256(self): self.check_nist_vectors(SHA3_URL, ["SHA3_256LongMsg.rsp", "SHA3_256ShortMsg.rsp"], "sha3_256") - def test_shake_128(self): self.check_nist_vectors(SHAKE_URL, ["SHAKE128LongMsg.rsp", "SHAKE128ShortMsg.rsp"], "shake_128") - - def check_nist_vectors(self, url: str, filenames: list[str], preset: str): - pattern = r"Len\s*=\s*(?P\d+)\s+Msg\s*=\s*(?P[0-9a-fA-F\s]+)\s+(MD|Output)\s*=\s*(?P[0-9a-fA-F]+)" - vecs_zip = fetch(url) - - for filename in filenames: - vecs = zipfile.ZipFile(vecs_zip).open(filename).read().decode() - - vectors = [ (l, bytes.fromhex(match["Msg"].lower()), bytes.fromhex(match["Output"].lower())) - for match in re.finditer(pattern, vecs) if (l:=int(match["Len"])) < 8192 ] - - self.assertTrue(len(vectors) > 0) - - print("file", filename) - for data_len, data, output in tqdm(vectors): - tinyout = bytes(Tensor(data[:data_len//8]).keccak(preset).data()) - self.assertEqual(tinyout, output) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_llama3_ff.py b/tinygrad/test/external/external_test_llama3_ff.py deleted file mode 100644 index aff88c0c..00000000 --- a/tinygrad/test/external/external_test_llama3_ff.py +++ /dev/null @@ -1,12 +0,0 @@ -#!/usr/bin/env python3 -from tinygrad import Tensor, TinyJit, nn -from extra.models.llama import FeedForward - -if __name__ == "__main__": - model = FeedForward(4096, 14336) - for x in nn.state.get_parameters(model): x.replace(x.half()).realize() - jrun = TinyJit(model) - for i in range(5): - print(f"*** run {i}") - jrun(Tensor.rand(1, 4096)) - diff --git a/tinygrad/test/external/external_test_lm_head.py b/tinygrad/test/external/external_test_lm_head.py deleted file mode 100644 index 851e0aa8..00000000 --- a/tinygrad/test/external/external_test_lm_head.py +++ /dev/null @@ -1,10 +0,0 @@ -from tinygrad import Tensor, nn - -if __name__ == "__main__": - vocab_size = 50257 - n_embd = 768 - lm_head = nn.Linear(n_embd, vocab_size, bias=False) - bs = 4 - seq_len = 1024 - x = Tensor.rand(bs, seq_len, n_embd) - ret = lm_head(x).realize() diff --git a/tinygrad/test/external/external_test_losses.py b/tinygrad/test/external/external_test_losses.py deleted file mode 100644 index cd8efde2..00000000 --- a/tinygrad/test/external/external_test_losses.py +++ /dev/null @@ -1,40 +0,0 @@ -from tinygrad import Tensor -from test.external.mlperf_retinanet.focal_loss import sigmoid_focal_loss as ref_sigmoid_focal_loss -from test.external.mlperf_unet3d.dice import DiceCELoss -from examples.mlperf.losses import dice_ce_loss, sigmoid_focal_loss, l1_loss - -import numpy as np -import torch -import unittest - -class ExternalTestLosses(unittest.TestCase): - def setUp(self): - np.random.seed(42) - - def _assert_loss(self, pred, tgt, tinygrad_metrics, ref_metrics, rtol=1e-07, atol=0, **kwargs): - tinygrad_metrics_res = tinygrad_metrics(Tensor(pred), Tensor(tgt), **kwargs) - ref_metrics_res = ref_metrics(torch.from_numpy(pred), torch.from_numpy(tgt), **kwargs) - np.testing.assert_allclose(tinygrad_metrics_res.numpy(), ref_metrics_res.numpy(), rtol=rtol, atol=atol) - - def test_dice_ce_loss(self): - pred, label = np.random.rand(1, 3, 128, 128, 128).astype(np.float32), np.ones((1, 1, 128, 128, 128)).astype(np.uint8) - tinygrad_metrics_res, ref_metrics_res = dice_ce_loss, DiceCELoss(True, True, "NCDHW", False) - self._assert_loss(pred, label, tinygrad_metrics_res, ref_metrics_res, atol=1e-4) - - def test_sigmoid_focal_loss(self): - def _apply_logit(p): return np.log(p / (1 - p)) - pred, tgt = _apply_logit(np.random.rand(5,2).astype(np.float32)), np.random.randint(0, 2, (5, 2)).astype(np.float32) - for reduction in ["mean", "sum", "none"]: - for alpha, gamma in zip([-1, 0.58], [0, 2]): - self._assert_loss(pred, tgt, sigmoid_focal_loss, ref_sigmoid_focal_loss, rtol=1e-4, alpha=alpha, gamma=gamma, reduction=reduction) - - def test_l1_loss(self): - N, C, H, W = 3, 4, 5, 6 - shapes = ((N, C), (N, C, H), (N, C, H, W)) - for reduction in ["mean", "sum", "none"]: - for shape in shapes: - pred, tgt = np.random.randint(shape).astype(np.float32), np.random.randint(shape) - self._assert_loss(pred, tgt, l1_loss, torch.nn.functional.l1_loss, reduction=reduction) - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/external/external_test_mamba.py b/tinygrad/test/external/external_test_mamba.py deleted file mode 100644 index 3213b7c6..00000000 --- a/tinygrad/test/external/external_test_mamba.py +++ /dev/null @@ -1,24 +0,0 @@ -import unittest -from tinygrad.helpers import CI -from examples.mamba import Mamba, generate -from transformers import AutoTokenizer - -PROMPT = 'Why is gravity ' -TOKENIZER = AutoTokenizer.from_pretrained("EleutherAI/gpt-neox-20b") - -@unittest.skipIf(CI, "model is slow for CI") -class TestMamba(unittest.TestCase): - def test_mamba_130M(self): - OUT_130M = '''Why is gravity \nnot a good idea?\n\nA:''' - model = Mamba.from_pretrained('130m') - tinyoutput = generate(model, TOKENIZER, PROMPT, n_tokens_to_gen=10) - self.assertEqual(OUT_130M, tinyoutput) - del model - def test_mamba_370M(self): - OUT_370M = '''Why is gravity \nso important?\nBecause it's the only''' - model = Mamba.from_pretrained('370m') - tinyoutput = generate(model, TOKENIZER, PROMPT, n_tokens_to_gen=10) - self.assertEqual(OUT_370M, tinyoutput) - del model -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_metrics.py b/tinygrad/test/external/external_test_metrics.py deleted file mode 100644 index 318fc5cd..00000000 --- a/tinygrad/test/external/external_test_metrics.py +++ /dev/null @@ -1,20 +0,0 @@ -from tinygrad import Tensor -from test.external.mlperf_unet3d.dice import DiceScore -from examples.mlperf.metrics import dice_score - -import numpy as np -import torch -import unittest - -class ExternalTestMetrics(unittest.TestCase): - def _test_metrics(self, tinygrad_metrics, orig_metrics, pred, label, atol=1e-8, rtol=1e-7): - tinygrad_metrics_res = tinygrad_metrics(Tensor(pred), Tensor(label)).squeeze().numpy() - orig_metrics_res = orig_metrics(torch.from_numpy(pred), torch.from_numpy(label)).numpy() - np.testing.assert_allclose(tinygrad_metrics_res, orig_metrics_res, atol=atol, rtol=rtol) - - def test_dice(self): - pred, label = np.random.rand(1, 3, 128, 128, 128).astype(np.float32), np.ones((1, 1, 128, 128, 128)).astype(np.uint8) - self._test_metrics(dice_score, DiceScore(), pred, label) - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/external/external_test_mnist_data_select.py b/tinygrad/test/external/external_test_mnist_data_select.py deleted file mode 100644 index d4fd6c0a..00000000 --- a/tinygrad/test/external/external_test_mnist_data_select.py +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -from tinygrad import Tensor -from extra.datasets import fetch_mnist - -if __name__ == "__main__": - X_train, Y_train, X_test, Y_test = fetch_mnist(tensors=True) - samples = Tensor.randint(512, high=X_train.shape[0]) - select = X_train[samples].realize() diff --git a/tinygrad/test/external/external_test_nv.py b/tinygrad/test/external/external_test_nv.py deleted file mode 100644 index f061975e..00000000 --- a/tinygrad/test/external/external_test_nv.py +++ /dev/null @@ -1,66 +0,0 @@ -import unittest, struct, array, ctypes -from tinygrad import Device, dtypes, Tensor -from tinygrad.helpers import to_mv -from tinygrad.runtime.ops_nv import NVDevice, HWQueue -from tinygrad.engine.search import Opt, OptOps -from test.test_linearizer_failures import helper_test_lin -from tinygrad.engine.realize import get_runner, CompiledRunner -from test.external.fuzz_linearizer import get_fuzz_rawbufs - -from tinygrad.codegen.kernel import Kernel -from tinygrad.uop.ops import LazyOp, Ops, ReduceOps, BufferOps, MemBuffer -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -@unittest.skipUnless(Device.DEFAULT == "NV", "NV specific tests/fixes") -class TestNV(unittest.TestCase): - @classmethod - def setUpClass(self): - TestNV.d0: NVDevice = Device["NV"] - TestNV.a = Tensor([0.,1.], device="NV").realize() - TestNV.b = self.a + 1 - si = self.b.schedule()[-1] - TestNV.d0_runner = get_runner(TestNV.d0.device, si.ast) - TestNV.b.uop.buffer.allocate() - TestNV.addr = struct.pack("QQ", TestNV.b.uop.buffer._buf.va_addr, TestNV.a.uop.buffer._buf.va_addr) - - def test_oor_kernels(self): - ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=ReduceOps.SUM, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=Ops.MUL, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 256, 1, 512, 4, 16, 4, 16), strides=(0, 100352, 0, 196, 0, 14, 0, 1), offset=-15, mask=((0, 1), (0, 256), (0, 1), (0, 512), (0, 4), (1, 15), (0, 4), (1, 15)), contiguous=False), View(shape=(256, 1, 512, 7, 7, 512, 3, 3), strides=(2097152, 0, 0, 128, 2, 4096, 1088, 17), offset=0, mask=None, contiguous=False))))), LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=2, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(256, 1, 512, 7, 7, 512, 3, 3), strides=(25088, 0, 49, 7, 1, 0, 0, 0), offset=0, mask=None, contiguous=False),))))), arg=None),), arg=(dtypes.float, False)),), arg=((0, 3, 4), dtypes.float)),), arg=(dtypes.half, False)),), arg=MemBuffer(idx=0, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 512, 1, 1, 512, 3, 3), strides=(0, 0, 4608, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=True),)))) # noqa: E501 - opts = [Opt(op=OptOps.TC, axis=6, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=2)] # noqa: E501 - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=["NV"]) - - def test_error_on_huge_dims(self): - ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=ReduceOps.SUM, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=Ops.MUL, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 683), strides=(0, 0, 0, 1), offset=0, mask=None, contiguous=False),)))), LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=2, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 683), strides=(0, 0, 683, 1), offset=0, mask=None, contiguous=True),))))), arg=None),), arg=dtypes.float),), arg=(3,)),), arg=MemBuffer(idx=0, dtype=dtypes.float, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)))) # noqa: E501 - opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=2)] # noqa: E501 - with self.assertRaises(RuntimeError) as cm: - lin = Kernel(ast) - lin.apply_opts(opts) - rawbufs = get_fuzz_rawbufs(lin) - prg = CompiledRunner(lin.to_program()) - prg(rawbufs, {}, wait=True) - self.assertEqual(str(cm.exception), "This is a runtime error message") - - def test_buf4_usage(self): - TestNV.along = Tensor([105615], device="NV").realize() - ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=Ops.SIN, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.ulong, st=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)))),), arg=dtypes.float),), arg=None),), arg=MemBuffer(idx=0, dtype=dtypes.float, st=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)))) # noqa: E501 - temp_runner = get_runner(TestNV.d0.device, (ast,)) - temp_runner([TestNV.b.uop.buffer, TestNV.along.uop.buffer], var_vals={}) - val = TestNV.b.uop.buffer.as_buffer().cast("f")[0] - assert abs(val - 0.80647) < 0.001, f"got val {val}" - - def test_kernargs_no_oob_access(self): - kernargs_start = TestNV.d0._gpu_alloc((2 << 20), map_to_cpu=True).va_addr - kernargs = kernargs_start + ((2 << 20) - TestNV.d0_runner._prg.kernargs_alloc_size) - to_mv(kernargs, 0x160).cast('I')[:] = array.array('I', TestNV.d0_runner._prg.constbuffer_0) - ctypes.memmove(kernargs + TestNV.d0_runner._prg.kernargs_offset, TestNV.addr, len(TestNV.addr)) - - q = HWQueue() - q.exec(TestNV.d0_runner._prg, kernargs, TestNV.d0_runner.global_size, TestNV.d0_runner.local_size) - q.signal(TestNV.d0.timeline_signal, TestNV.d0.timeline_value).submit(TestNV.d0) - TestNV.d0._wait_signal(TestNV.d0.timeline_signal, TestNV.d0.timeline_value) - TestNV.d0.timeline_value += 1 - val = TestNV.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/external/external_test_onnx_backend.py b/tinygrad/test/external/external_test_onnx_backend.py deleted file mode 100644 index 2769663f..00000000 --- a/tinygrad/test/external/external_test_onnx_backend.py +++ /dev/null @@ -1,224 +0,0 @@ -import tempfile, unittest -from typing import Any, Tuple -from onnx.backend.base import Backend, BackendRep -import onnx.backend.test -import numpy as np -from tinygrad import Tensor, Device, dtypes -from tinygrad.helpers import getenv, OSX -from tinygrad.device import is_dtype_supported - -# pip3 install tabulate -pytest_plugins = 'onnx.backend.test.report', - -from tinygrad.frontend.onnx import OnnxRunner, onnx_load - -class TinygradModel(BackendRep): - def __init__(self, run_onnx, input_names): - super().__init__() - self.fxn = run_onnx - self.input_names = input_names - - def run(self, inputs: Any, **kwargs: Any) -> Tuple[Any, ...]: - real_inputs = dict(zip(self.input_names, inputs)) - ret = self.fxn(real_inputs, debug=2) - return tuple(x.numpy() if isinstance(x, Tensor) else [i.numpy() for i in x] if isinstance(x, list) else np.array(x) for x in ret.values()) - -class TinygradBackend(Backend): - @classmethod - def prepare(cls, model: onnx.ModelProto, device): - input_all = [x.name for x in model.graph.input] - input_initializer = [x.name for x in model.graph.initializer] - net_feed_input = [x for x in input_all if x not in input_initializer] - print("prepare", cls, device, net_feed_input) - with tempfile.NamedTemporaryFile(suffix='.onnx') as f: - onnx.save(model, f.name) - f.flush() - new_model = onnx_load(f.name) - run_onnx = OnnxRunner(new_model) - return TinygradModel(run_onnx, net_feed_input) - - @classmethod - def supports_device(cls, device: str) -> bool: - # NOTE: this is onnx CPU - return device == "CPU" - -backend_test = onnx.backend.test.BackendTest(TinygradBackend, __name__) - -# BUG: buggy onnx tests -backend_test.exclude('test_adam_multiple_cpu') - -# BUG: ORT fails these with runtime error -backend_test.exclude('test_PReLU_1d_multiparam_cpu') -backend_test.exclude('test_PReLU_2d_multiparam_cpu') -backend_test.exclude('test_PReLU_3d_multiparam_cpu') - -# BUG: we don't match ORT here due to some div inaccuracy with floats -backend_test.exclude('test_dynamicquantizelinear_cpu') -backend_test.exclude('test_dynamicquantizelinear_expanded_cpu') - -# BUG: ORT fails these with numerical error but we match ORT numerically -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_2D_int8_float16 -backend_test.exclude('test_qlinearmatmul_2D_int8_float16_cpu') -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_3D_int8_float16 -backend_test.exclude('test_qlinearmatmul_3D_int8_float16_cpu') -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_2D_int8_float32 -backend_test.exclude('test_qlinearmatmul_2D_int8_float32_cpu') -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_3D_int8_float32 -backend_test.exclude('test_qlinearmatmul_3D_int8_float32_cpu') -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_maxunpool_export_with_output_shape -backend_test.exclude('test_maxunpool_export_with_output_shape_cpu') -# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True -backend_test.exclude('test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True_cpu') - -# about different dtypes -if not is_dtype_supported(dtypes.float64): - backend_test.exclude('float64') - backend_test.exclude('DOUBLE') - # these have float64 inputs - backend_test.exclude('test_eyelike_with_dtype_cpu') - backend_test.exclude('test_reduce_log_sum_exp*') - backend_test.exclude('test_operator_add*') - backend_test.exclude('test_einsum_*') - backend_test.exclude('test_cumsum_*') - -if not is_dtype_supported(dtypes.float16): - backend_test.exclude('float16') - backend_test.exclude('FLOAT16') - -# dtype cast -backend_test.exclude('STRING') -backend_test.exclude('FLOAT8') -backend_test.exclude('INT4') -backend_test.exclude('UINT4') -backend_test.exclude('BFLOAT16') # not supported in numpy -# TODO: fix these with true onnx float16 -backend_test.exclude('to_FLOAT16') -backend_test.exclude('cast_no_saturate') -backend_test.exclude('test_dequantizelinear_e4m3fn_float16_cpu') -backend_test.exclude('test_max_float16_cpu') -backend_test.exclude('test_min_float16_cpu') -backend_test.exclude('test_mod_mixed_sign_float16_cpu') - -backend_test.exclude('test_dequantizelinear_int4_cpu') -backend_test.exclude('test_dequantizelinear_uint4_cpu') -backend_test.exclude('test_quantizelinear_int4_cpu') -backend_test.exclude('test_quantizelinear_uint4_cpu') - -# no support for FLOAT8 -backend_test.exclude('test_quantizelinear_e4m3fn_cpu') -backend_test.exclude('test_quantizelinear_e5m2_cpu') -backend_test.exclude('test_quantizelinear_e4m3fn_cpu') -backend_test.exclude('test_quantizelinear_e5m2_cpu') -backend_test.exclude('test_dequantizelinear_e4m3fn_cpu') -backend_test.exclude('test_dequantizelinear_e4m3fn_zero_point_cpu') -backend_test.exclude('test_dequantizelinear_e5m2_cpu') - -# we don't support indexes -backend_test.exclude('test_nonzero_*') - -# no support for int pow -backend_test.exclude('test_pow_types_int32_int32_cpu') -backend_test.exclude('test_pow_types_int64_int64_cpu') - -# no boolean ops (2d, 3d, 4d) -backend_test.exclude('test_bitshift_*') - -# no string ops -backend_test.exclude('string') -backend_test.exclude('test_strnorm_*') -backend_test.exclude('test_regex_*') - -# no rnn -backend_test.exclude('test_gru_*') -backend_test.exclude('test_rnn_*') -backend_test.exclude('test_lstm_*') -backend_test.exclude('test_simple_rnn_*') - -# no control flow -# control flow uses AttributeProto.GRAPH -backend_test.exclude('test_if_*') -backend_test.exclude('test_loop*') -backend_test.exclude('test_range_float_type_positive_delta_expanded_cpu') # requires loop -backend_test.exclude('test_affine_grid_2d_align_corners_expanded_cpu') -backend_test.exclude('test_affine_grid_2d_expanded_cpu') -backend_test.exclude('test_affine_grid_3d_align_corners_expanded_cpu') -backend_test.exclude('test_affine_grid_3d_expanded_cpu') -backend_test.exclude('test_range_int32_type_negative_delta_expanded_cpu') - -# unsupported (strange) ops -backend_test.exclude('test_blackmanwindow_*') -backend_test.exclude('test_bernoulli_*') -backend_test.exclude('test_det_*') -backend_test.exclude('test_col2im_*') -backend_test.exclude('test_hammingwindow_*') -backend_test.exclude('test_hannwindow_*') -backend_test.exclude('test_hardmax_*') -backend_test.exclude('test_gridsample_*') -backend_test.exclude('test_dft_*') -backend_test.exclude('test_einsum_batch_diagonal_cpu*') # TODO: equation = '...ii ->...i' -backend_test.exclude('test_einsum_inner_prod_cpu*') # TODO: equation = 'i,i' -backend_test.exclude('test_unique_*') -backend_test.exclude('test_sequence_*') -backend_test.exclude('test_nonmaxsuppression_*') -backend_test.exclude('test_reversesequence_*') -backend_test.exclude('test_roialign_*') -backend_test.exclude('test_tfidfvectorizer_*') -backend_test.exclude('test_stft_*') -backend_test.exclude('test_melweightmatrix_*') - -# more strange ops -backend_test.exclude('test_basic_deform_conv_*') -backend_test.exclude('test_deform_conv_*') -backend_test.exclude('test_lppool_*') -backend_test.exclude('test_scan_*') -backend_test.exclude('test_split_to_sequence_*') -backend_test.exclude('test_resize_downsample_scales_cubic_*') # unsure how to implement cubic -backend_test.exclude('test_resize_downsample_sizes_cubic_*') # unsure how to implement cubic -backend_test.exclude('test_resize_upsample_scales_cubic_*') # unsure how to implement cubic -backend_test.exclude('test_resize_upsample_sizes_cubic_*') # unsure how to implement cubic -backend_test.exclude('test_ai_onnx_ml_tree_ensemble_*') # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/aionnxml/op_tree_ensemble.py#L121 - -# rest of the failing tests -backend_test.exclude('test_resize_tf_crop_and_resize_cpu') # tf_crop_and_resize not implemented -backend_test.exclude('test_resize_tf_crop_and_resize_axes_2_3_cpu') # tf_crop_and_resize not implemented -backend_test.exclude('test_resize_tf_crop_and_resize_axes_3_2_cpu') # tf_crop_and_resize not implemented -backend_test.exclude('test_resize_tf_crop_and_resize_extrapolation_value_cpu') # tf_crop_and_resize value not implemented -backend_test.exclude('test_resize_downsample_scales_linear_antialias_cpu') # antialias not implemented -backend_test.exclude('test_resize_downsample_sizes_linear_antialias_cpu') # antialias not implemented -backend_test.exclude('test_ai_onnx_ml_label_encoder_tensor_value_only_mapping_cpu') # bad data type string -backend_test.exclude('test_ai_onnx_ml_label_encoder_tensor_mapping_cpu') # bad data type string - -backend_test.exclude('test_scatternd_min_cpu') # min not yet supported -backend_test.exclude('test_scatternd_max_cpu') # max not yet supported - -if Device.DEFAULT in ['GPU', 'METAL']: - backend_test.exclude('test_resize_upsample_sizes_nearest_axes_2_3_cpu') - backend_test.exclude('test_resize_upsample_sizes_nearest_axes_3_2_cpu') - backend_test.exclude('test_resize_upsample_sizes_nearest_cpu') - -if Device.DEFAULT == "METAL" or (OSX and Device.DEFAULT == "GPU"): - # numerical inaccuracy - backend_test.exclude('test_mish_cpu') - backend_test.exclude('test_mish_expanded_cpu') - -# disable model tests for now since they are slow -if not getenv("MODELTESTS"): - for x in backend_test.test_suite: - if 'OnnxBackendRealModelTest' in str(type(x)): - backend_test.exclude(str(x).split(" ")[0]) -else: - # model tests all pass! - backend_test.include('test_resnet50') - backend_test.include('test_inception_v1') - backend_test.include('test_inception_v2') - backend_test.include('test_densenet121') - backend_test.include('test_shufflenet') - backend_test.include('test_squeezenet') - backend_test.include('test_bvlc_alexnet') - backend_test.include('test_zfnet512') - backend_test.include('test_vgg19') - -globals().update(backend_test.enable_report().test_cases) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_onnx_ops.py b/tinygrad/test/external/external_test_onnx_ops.py deleted file mode 100644 index 8150995d..00000000 --- a/tinygrad/test/external/external_test_onnx_ops.py +++ /dev/null @@ -1,414 +0,0 @@ -# inputs, attributes, and outputs for tests are found here: -# https://github.com/onnx/onnx/blob/main/docs/Operators.md -# https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md - -from typing import Any -import unittest, onnx, tempfile -from tinygrad import dtypes -from tinygrad.frontend.onnx import OnnxRunner -import numpy as np -from extra.onnx_helpers import validate -from onnx.defs import ONNX_DOMAIN, AI_ONNX_PREVIEW_TRAINING_DOMAIN -MICROSOFT_CONTRIB_OPS_DOMAIN = "com.microsoft" - -class TestOnnxOps(unittest.TestCase): - DOMAIN = None - def helper_build_model(self, op:str, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str]): - onnx_inputs = [onnx.helper.make_tensor_value_info(name, onnx.helper.np_dtype_to_tensor_dtype(arr.dtype), arr.shape) for name, arr in inps.items()] - onnx_outputs = [onnx.helper.make_empty_tensor_value_info(name) for name in outs] - nodes = [onnx.helper.make_node(op, list(inps), list(outs), domain=self.DOMAIN, **opts)] - graph = onnx.helper.make_graph(nodes, f"test_{op.lower()}", onnx_inputs, onnx_outputs) - model = onnx.helper.make_model(graph, producer_name=f"test_{op.lower()}") - return model - - def helper_test_single_op(self, op:str, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str], rtol=1e-3, atol=1e-6): - model = self.helper_build_model(op, inps, opts, outs) - with tempfile.NamedTemporaryFile() as tmp: - onnx.save(model, tmp.name) - validate(tmp.name, inps, rtol, atol) - -class TestMainOnnxOps(TestOnnxOps): - DOMAIN = ONNX_DOMAIN - def test_reshape(self): - inputs = {"in": np.arange(6, dtype=np.float32), "shape": np.array([2,3], dtype=np.int64)} - attributes = {} - outputs = ["out"] - self.helper_test_single_op("Reshape", inputs, attributes, outputs) - - def test_squeeze(self): - # axes is None - inputs = {"data": np.random.randn(1, 3, 1, 1).astype(np.float32)} - attributes = {} - outputs = ["squeezed"] - self.helper_test_single_op("Squeeze", inputs, attributes, outputs) - - def test_conv(self): - # test VALID auto_pad - inputs = { - "x": np.random.randn(1, 3, 384, 384).astype(np.float32), - "w": np.random.randn(1152, 3, 14, 14).astype(np.float32), - "b": np.random.randn(1152).astype(np.float32) - } - attributes = {'auto_pad': 'VALID', 'dilations': (1, 1), 'group': 1, 'kernel_shape': (14, 14), 'strides': (14, 14)} - outputs = ["y"] - self.helper_test_single_op("Conv", inputs, attributes, outputs, atol=1e-4) - - def test_gather(self): - # test const negative indices - inputs = { - "input": np.random.randn(1, 3, 3).astype(np.float32), - "indices": np.array(-2, dtype=np.int64), - } - attributes = {'axis': 1} - outputs = ["y"] - self.helper_test_single_op("Gather", inputs, attributes, outputs) - - def test_maxunpool_export_with_output_shape(self): - # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-91 - xT = np.array([[[[5, 6], [7, 8]]]], dtype=np.float32) - xI = np.array([[[[5, 7], [13, 15]]]], dtype=np.int64) - output_shape = np.array((1, 1, 5, 5), dtype=np.int64) - inputs = {"x": xT, "indices": xI, "output_shape": output_shape} - attributes = {"kernel_shape": [2, 2], "strides": [2, 2]} - outputs = ["y"] - self.helper_test_single_op("MaxUnpool", inputs, attributes, outputs) - - def test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True(self): - # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-13 - inputs = {"x": np.random.randn(1, 1, 32, 32, 32).astype(np.float32)} - attributes = {"kernel_shape": (5, 5, 5), "strides": (3, 3, 3), "dilations": (2, 2, 2), "count_include_pad": 1, "ceil_mode": True} - outputs = ["y"] - self.helper_test_single_op("AveragePool", inputs, attributes, outputs) - - def test_isinf(self): - # https://github.com/onnx/onnx/blob/main/docs/Operators.md#isinf - # attributes are int but output expects bool - x = np.array([-1.2, np.nan, np.inf, 2.8, -np.inf, np.inf], dtype=np.float32) - inputs = {"x": x} - attributes = {"detect_negative":1, "detect_positive":1} - outputs = ["y"] - model = self.helper_build_model("IsInf", inputs, attributes, outputs) - outputs = OnnxRunner(model)(inputs) - assert outputs["y"].dtype is dtypes.bool - - def test_quantize_linear(self): - test_cases = [ - {"test_case": "round_half_to_even", "qdtype": np.int8, "qzero_point": 0, "x": [-1.5, -0.5, 0.5, 1.5], "scale": 1.0}, - {"test_case": "round_to_even_before_add_zero_point", "qdtype": np.uint8, "qzero_point": 1, "x": [0.5, 1.5], "scale": 1.0}, - ] - for case in test_cases: - with self.subTest(test_case=case["test_case"]): - inputs = { - "x": np.array([case["x"]], dtype=np.float32), - "y_scale": np.array(case["scale"], dtype=np.float32), - "y_zero_point": np.array(case["qzero_point"], dtype=case["qdtype"]) - } - self.helper_test_single_op("QuantizeLinear", inputs, {}, ["y"]) - - def test_dynamic_quantize_linear(self): - test_cases = [ - {"name": "round_half_to_even", "x": np.array([0, 0.5, 1.5, 255], dtype=np.float32)}, - {"name": "round_zero_point_half_down_to_even", "x": np.array([-1, 509], dtype=np.float32)}, - {"name": "round_zero_point_half_up_to_even", "x": np.array([-11, 499], dtype=np.float32)}, - # other tests from https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-45 - {"name": "max_adjusted", "x": np.array([-1.0, -2.1, -1.3, -2.5, -3.34, -4.0], dtype=np.float32)}, - {"name": "min_adjusted", "x": np.array([1, 2.1, 1.3, 2.5, 3.34, 4.0, 1.5, 2.6, 3.9, 4.0, 3.0, 2.345], dtype=np.float32).reshape((3, 4))}, - ] - for case in test_cases: - with self.subTest(test_case=case["name"]): - self.helper_test_single_op("DynamicQuantizeLinear", {"x": case["x"]}, {}, ["y", "y_scale", "y_zero_point"]) - - def test_qlinear_conv(self): - for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: - for b in (np.ones([32], dtype=np.int32), np.zeros([32], dtype=np.int32)): - with self.subTest(dtype=dtype, zero_point=zero_point): - dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max - inputs = { - "x": np.random.randint(dtype_min, dtype_max + 1, [1, 3, 224, 224], dtype=dtype), - "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "x_zero_point": np.array(zero_point, dtype=dtype), - "w": np.random.randint(dtype_min, dtype_max + 1, [32, 3, 3, 3], dtype=dtype), - "w_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "w_zero_point": np.array(zero_point, dtype=dtype), - "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "y_zero_point": np.array(zero_point, dtype=dtype), - "b": b - } - attributes = {'auto_pad': 'NOTSET', 'dilations': (1, 1), 'group': 1, 'kernel_shape': (3, 3), 'pads': (1, 1, 1, 1), 'strides': (2, 2)} - outputs = ["out"] - self.helper_test_single_op("QLinearConv", inputs, attributes, outputs, atol=1) # occasionally inaccurate - - def test_qlinear_matmul(self): - for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: - with self.subTest(dtype=dtype, zero_point=zero_point): - dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max - inputs = { - "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "A_zero_point": np.array(zero_point, dtype=dtype), - "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "B_zero_point": np.array(zero_point, dtype=dtype), - "Y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "Y_zero_point": np.array(zero_point, dtype=dtype) - } - attributes = {} - outputs = ["Y"] - self.helper_test_single_op("QLinearMatMul", inputs, attributes, outputs) - - for name,val in (("round_half_down_to_even", 1), ("round_half_up_to_even", 3)): - with self.subTest(test_case=name, val=val): - inputs = { - "A": np.array([val], dtype=np.int8), - "A_scale": np.array(0.5, dtype=np.float32), - "A_zero_point": np.array(0, dtype=np.int8), - "B": np.array([1], dtype=np.int8), - "B_scale": np.array(1, dtype=np.float32), - "B_zero_point": np.array(0, dtype=np.int8), - "Y_scale": np.array(1, dtype=np.float32), - "Y_zero_point": np.array(0, dtype=np.int8) - } - attributes = {} - outputs = ["Y"] - self.helper_test_single_op("QLinearMatMul", inputs, attributes, outputs) - - def _run_qlinearmatmul_test(self, quant_type, dtype, dims): - # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-111 - if dims == 2: - a = np.array([[208, 236, 0, 238], [3, 214, 255, 29]]) - b = np.array([[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]]) - else: - a = np.array([[[208, 236, 0, 238], [3, 214, 255, 29]], [[208, 236, 0, 238], [3, 214, 255, 29]]]) - b = np.array([[[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]], [[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]]]) - a_zero_point = np.array([113]) - b_zero_point = np.array([114]) - y_zero_point = np.array([118]) - if quant_type == np.int8: - a, b, a_zero_point, b_zero_point, y_zero_point = (x - 127 for x in (a, b, a_zero_point, b_zero_point, y_zero_point)) - a, b, a_zero_point, b_zero_point, y_zero_point = (x.astype(quant_type) for x in (a, b, a_zero_point, b_zero_point, y_zero_point)) - inputs = { - "a": a, "a_scale": np.array([0.0066], dtype=dtype), "a_zero_point": a_zero_point, - "b": b, "b_scale": np.array([0.00705], dtype=dtype), "b_zero_point": b_zero_point, - "y_scale": np.array([0.0107], dtype=dtype), "y_zero_point": y_zero_point - } - self.helper_test_single_op("QLinearMatMul", inputs, {}, ["y"],) - def test_qlinearmatmul_2D_int8_float16(self): self._run_qlinearmatmul_test(np.int8, np.float16, 2) - def test_qlinearmatmul_3D_int8_float16(self): self._run_qlinearmatmul_test(np.int8, np.float16, 3) - def test_qlinearmatmul_2D_int8_float32(self): self._run_qlinearmatmul_test(np.int8, np.float32, 2) - def test_qlinearmatmul_3D_int8_float32(self): self._run_qlinearmatmul_test(np.int8, np.float32, 3) - -class TestTrainingOnnxOps(TestOnnxOps): - # NOTE: ORT doesn't actually support training ops on cpu so we test using functions provided by onnx - DOMAIN = AI_ONNX_PREVIEW_TRAINING_DOMAIN - def _validate_training(self, op:str, onnx_fxn, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str]): - model = self.helper_build_model(op, inps, opts, outs) - if op == "Momentum": del opts['mode'] - runner = OnnxRunner(model) - tiny_out = runner(inps) - onnx_out = onnx_fxn(**inps, **opts) - for (nm, t_out), o_out in zip(tiny_out.items(), onnx_out): - np.testing.assert_allclose(t_out.numpy(), o_out, rtol=1e-3, atol=1e-6, err_msg=f"{nm} failed") - - def test_adagrad_t_greater_than_zero(self): - from onnx.backend.test.case.node.adagrad import apply_adagrad - for t in [1, 3, 100]: - inputs = { - "r": np.array(0.01, dtype=np.float32), - "t": np.array(t, dtype=np.int32), - "x": np.random.randn(3, 3).astype(np.float32), - "g": np.random.randn(3, 3).astype(np.float32), - "h": np.random.randn(3, 3).astype(np.float32), - } - attributes = {"decay_factor": 0.1, "epsilon": 1e-6, "norm_coefficient": 0.01} - outputs = ["X_out", "H_out"] - self._validate_training("Adagrad", apply_adagrad, inputs, attributes, outputs) - - def test_momentum_t_greater_than_zero(self): - from onnx.backend.test.case.node.momentum import apply_momentum, apply_nesterov - for onnx_fxn, mode in ((apply_momentum, "standard"), (apply_nesterov, "nesterov")): - for t in [1, 3, 100]: - inputs = { - "r": np.array(0.01, dtype=np.float32), - "t": np.array(t, dtype=np.int32), - "x": np.random.randn(3, 3).astype(np.float32), - "g": np.random.randn(3, 3).astype(np.float32), - "v": np.random.randn(3, 3).astype(np.float32), - } - attributes = {"alpha": 0.9, "beta": 0.1, "mode": mode, "norm_coefficient": 0.01} - outputs = ["X_out", "V_out"] - self._validate_training("Momentum", onnx_fxn, inputs, attributes, outputs) - - def test_adam_t_greater_than_zero(self): - from onnx.backend.test.case.node.adam import apply_adam - for t in [1, 3, 100]: - inputs = { - "r": np.array(0.01, dtype=np.float32), - "t": np.array(t, dtype=np.int32), - "x": np.random.randn(3, 3).astype(np.float32), - "g": np.random.randn(3, 3).astype(np.float32), - "v": np.random.randn(3, 3).astype(np.float32), - "h": np.random.randn(3, 3).astype(np.float32), - } - attributes = { "alpha": 0.9, "beta": 0.999, "epsilon": 1e-8, "norm_coefficient": 0.01, "norm_coefficient_post": 0.02 } - outputs = ["X_new", "V_new", "H_new"] - self._validate_training("Adam", apply_adam, inputs, attributes, outputs) - -class TestContribOnnxOps(TestOnnxOps): - DOMAIN = MICROSOFT_CONTRIB_OPS_DOMAIN - def test_attention(self): - batch_size, seq_len, input_hidden_size = 2, 8, 256 - num_heads, head_size = 4, 64 - hidden_size = num_heads * head_size - v_hidden_size = hidden_size - - # for mask_index - right_padding_mask = np.random.randint(1, seq_len + 1, size=(batch_size,), dtype=np.int32) - end_positions = np.random.randint(1, seq_len + 1, size=(batch_size,), dtype=np.int32) - start_positions = np.array([np.random.randint(0, end) for end in end_positions], dtype=np.int32) - left_padding_mask = np.concatenate([end_positions, start_positions]) - - base_inps = { - "input": np.random.randn(batch_size, seq_len, input_hidden_size).astype(np.float32), - "weights": np.random.randn(input_hidden_size, hidden_size * 3).astype(np.float32), - # bias is required in ORT (segfaults otherwise), eventhough docs says it's optional - "bias": np.random.randn(hidden_size * 2 + v_hidden_size).astype(np.float32), - } - base_opts = {"num_heads": num_heads} - - test_cases = [ - ({}, {}), - ({}, {"scale": 0.1}), - ({}, {"scale": 1.0}), - ({}, {"unidirectional": 1}), - ({"mask_index": right_padding_mask}, {}), - ({"mask_index": left_padding_mask}, {}), - ({"mask_index": np.random.randint(0, seq_len, size=(batch_size, seq_len), dtype=np.int32)}, {"mask_filter_value": -5000.0}), - ({"mask_index": np.random.randint(0, seq_len, size=(batch_size, seq_len, seq_len), dtype=np.int32)}, {"mask_filter_value": -np.inf}), - # BUG: when `mask_index` is used with `unidirectional`, the first value must be True - # otherwise this will trigger a different ORT behavior where start consecutive Falses will be turned True - # e.g. mask_index = [[0, 0, 1, 0, 1, 1, 1, 1], [0, 0, 1, 0, 1, 1, 1, 1]] - # will need mask[:, :, 0:1, 0:1] = True - ({"mask_index": np.array([[1, 0, 1, 0, 1, 1, 1, 1], [1, 0, 1, 0, 1, 1, 1, 1]], dtype=np.int32)}, {"unidirectional": 1}), - ({ "weights": np.random.randn(input_hidden_size, hidden_size + hidden_size + 128).astype(np.float32), - "bias": np.random.randn(hidden_size + hidden_size + 128).astype(np.float32)}, - {"qkv_hidden_sizes": [hidden_size, hidden_size, 128]}), - # TODO: past is not tested. ORT gives type error for input - ] - - for i, (extra_inps, extra_opts) in enumerate(test_cases): - with self.subTest(f"test_attention_{i}"): - inps = {**base_inps, **extra_inps} - opts = {**base_opts, **extra_opts} - outputs = ["output", "present"] if "past" in inps else ["output"] - self.helper_test_single_op("Attention", inps, opts, outputs, atol=1e-4) - - def test_skip_layer_normalization(self): - shape = (2, 8, 32) - for has_beta in [True, False]: - for has_bias in [True, False]: - with self.subTest(has_beta=has_beta, has_bias=has_bias): - hidden_size = shape[-1] - inputs = { - "input": np.random.randn(*shape).astype(np.float32), - "skip": np.random.randn(*shape).astype(np.float32), - "gamma": np.random.randn(hidden_size).astype(np.float32), - } - if has_beta: inputs["beta"] = np.random.randn(hidden_size).astype(np.float32) - if has_bias: inputs["bias"] = np.random.randn(hidden_size).astype(np.float32) - attributes = {"epsilon": 1e-12} - outputs = ["output", "mean", "inv_std_var", "input_skip_bias_sum"] - self.helper_test_single_op("SkipLayerNormalization", inputs, attributes, outputs) - - def test_bias_gelu(self): - shape = (2,3,4) - inputs = { - "A": np.random.randn(*shape).astype(np.float32), - "B": np.random.randn(shape[-1]).astype(np.float32) - } - attributes = {} - outputs = ["C"] - self.helper_test_single_op("BiasGelu", inputs, attributes, outputs) - - def test_qlinear_add(self): - for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: - with self.subTest(dtype=dtype, zero_point=zero_point): - dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max - inputs = { - "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "A_zero_point": np.array(zero_point, dtype=dtype), - "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "B_zero_point": np.array(zero_point, dtype=dtype), - "C_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "C_zero_point": np.array(zero_point, dtype=dtype) - } - attributes = {} - outputs = ["C"] - self.helper_test_single_op("QLinearAdd", inputs, attributes, outputs, atol=1) # TODO: look into why this is inaccurate - - with self.subTest(test_case="round_half_to_even"): - inputs = { - "A": np.array([1, 1, 1, 1], dtype=np.int8), - "A_scale": np.array(1, dtype=np.float32), - "A_zero_point": np.array(0, dtype=np.int8), - "B": np.array([1, 5, -3, -7], dtype=np.int8), - "B_scale": np.array(1, dtype=np.float32), - "B_zero_point": np.array(0, dtype=np.int8), - "C_scale": np.array(4, dtype=np.float32), - "C_zero_point": np.array(0, dtype=np.int8) - } - attributes = {} - outputs = ["C"] - self.helper_test_single_op("QLinearAdd", inputs, attributes, outputs) - - def test_qlinear_mul(self): - for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: - with self.subTest(dtype=dtype, zero_point=zero_point): - dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max - inputs = { - "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "A_zero_point": np.array(zero_point, dtype=dtype), - "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), - "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "B_zero_point": np.array(zero_point, dtype=dtype), - "C_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "C_zero_point": np.array(zero_point, dtype=dtype) - } - attributes = {} - outputs = ["C"] - self.helper_test_single_op("QLinearMul", inputs, attributes, outputs) - - with self.subTest(test_case="round_half_to_even"): - inputs = { - "A": np.array([1, 1, 1, 1], dtype=np.int8), - "A_scale": np.array(1, dtype=np.float32), - "A_zero_point": np.array(0, dtype=np.int8), - "B": np.array([2, 6, -2, -6], dtype=np.int8), - "B_scale": np.array(1, dtype=np.float32), - "B_zero_point": np.array(0, dtype=np.int8), - "C_scale": np.array(4, dtype=np.float32), - "C_zero_point": np.array(0, dtype=np.int8) - } - attributes = {} - outputs = ["C"] - self.helper_test_single_op("QLinearMul", inputs, attributes, outputs) - - def test_qlinear_global_average_pool(self): - for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: - with self.subTest(dtype=dtype, zero_point=zero_point): - dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max - inputs = { - "X": np.random.randint(dtype_min, dtype_max + 1, [1, 3, 32, 32], dtype=dtype), - "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "x_zero_point": np.array(zero_point, dtype=dtype), - "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), - "y_zero_point": np.array(zero_point, dtype=dtype) - } - attributes = {"channels_last": 0} - outputs = ["C"] - self.helper_test_single_op("QLinearGlobalAveragePool", inputs, attributes, outputs) - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/external/external_test_opt.py b/tinygrad/test/external/external_test_opt.py deleted file mode 100644 index 584c3af8..00000000 --- a/tinygrad/test/external/external_test_opt.py +++ /dev/null @@ -1,240 +0,0 @@ -#!/usr/bin/env python -import gc, unittest -import numpy as np -import torch - -from tinygrad import GlobalCounters, Tensor, Device -from tinygrad.helpers import getenv, Context -from tinygrad.nn.state import get_parameters -from tinygrad.engine.realize import capturing -from tinygrad.tensor import _to_np_dtype - -class CLCache: - def __init__(self, allowed=None, strict=False, preclear=True, var_vals=None): - self.allowed, self.strict, self.preclear, self.var_vals = allowed, strict, preclear, var_vals if var_vals is not None else {} - self.count = 0 - def add(self, ei): self.count += 1 - def __enter__(self): - if self.preclear: - gc.collect() - for x in [x for x in gc.get_objects() if isinstance(x, Tensor)]: - x.realize() - GlobalCounters.reset() - capturing.append(self) - print("cache: entering") - return self - def __exit__(self, _type, value, traceback): - capturing.clear() - print(f"cache: exiting with size {self.count}", f"allowed {self.allowed}" if self.allowed is not None else "") - if self.allowed is not None: - assert self.count == self.allowed, f"{self.count} != {self.allowed}" - -from extra.models.convnext import ConvNeXt -from extra.models.efficientnet import EfficientNet -from extra.models.resnet import ResNet18 -from extra.models.vit import ViT - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") -class TestInferenceMinKernels(unittest.TestCase): - def setUp(self): - self.training_old = Tensor.training - Tensor.training = False - def tearDown(self): - Tensor.training = self.training_old - - def test_convnext(self): - model = ConvNeXt() - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - img = Tensor.randn(1, 3, 224, 224) - with CLCache(143): - model(img).realize() - - def test_enet(self): - model = EfficientNet(getenv("ENET_NUM", 0), has_se=False) - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - img = Tensor.randn(1, 3, 224, 224) - with CLCache(51): - model.forward(img).realize() - - def test_enet_se(self): - model = EfficientNet(getenv("ENET_NUM", 0), has_se=True) - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - img = Tensor.randn(1, 3, 224, 224) - # TODO: this seems very high - with CLCache(115): - model.forward(img).realize() - - def test_resnet(self): - model = ResNet18() - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - img = Tensor.randn(1, 3, 224, 224) - with CLCache(23): - model.forward(img).realize() - - def test_vit(self): - model = ViT(embed_dim=192, num_heads=3) - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - img = Tensor.randn(1, 3, 224, 224) - with CLCache(209) as cache: # NOTE: this is way too high - out = model.forward(img) - assert cache.count == 0, "ViT prerealized?" - out.realize() - - @unittest.skip("llama is fp16 but CI does not have fp16") - def test_llama(self): - from examples.llama import Transformer - args_tiny = {"dim": 512, "hidden_dim": 1024, "n_heads": 8, "n_layers": 4, "norm_eps": 1e-05, "vocab_size": 1000} - model = Transformer(**args_tiny) - for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) - inp = Tensor([[1,2,3,4]]) - with CLCache(100): - model(inp, 0).realize() - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") -class TestOptBinOp(unittest.TestCase): - def _test_no_binop_rerun(self, f1, f2=None, allowed=1): - a = Tensor.randn(16, 16) - b = Tensor.randn(16, 16) - with CLCache() as cache: - c = f1(a, b) - if f2 is not None: d = f2(a, b) - c.realize() - if f2 is not None: d.realize() - assert cache.count == allowed, "binop was rerun!" - if f2 is not None: np.testing.assert_allclose(c.numpy().ravel(), d.numpy().ravel(), rtol=1e-3, atol=1e-5) - - def test_no_binop_rerun(self): return self._test_no_binop_rerun(lambda a,b: a*b, lambda a,b: (a*b).reshape(16, 16, 1)) - def test_no_binop_rerun_alt(self): return self._test_no_binop_rerun(lambda a,b: (a*b).reshape(16, 16, 1), lambda a,b: a*b) - def test_no_binop_rerun_reduce_broadcast(self): - return self._test_no_binop_rerun(lambda a,b: a.sum()+b, lambda a,b: a.sum().reshape(1,1)+b, allowed=2) - - @unittest.skip("this test started failing with the new change, based movementop issue") - def test_no_binop_rerun_transposed(self): return self._test_no_binop_rerun(lambda a,b: (a.T*b.T).T, lambda a,b: a*b) - def test_no_binop_rerun_mid_reshape(self): return self._test_no_binop_rerun(lambda a,b: (a*b).reshape(256)+a.reshape(256)) - - # currently non working tests - # def test_no_binop_rerun_preshape(self): return self._test_no_binop_rerun(lambda a,b: a.reshape(16, 16, 1)*b.reshape(16, 16, 1), lambda a,b: a*b) - #def test_no_binop_rerun_reduce(self): return self._test_no_binop_rerun(lambda a,b: (a*b).sum(), lambda a,b: (a*b).reshape(16, 16, 1).sum()) - #def test_no_binop_rerun_reduce_alt(self): return self._test_no_binop_rerun(lambda a,b: a.sum(1)+b[0], lambda a,b: a.sum(1).reshape(1,16)+b[0]) - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") -class TestOptReduceLoop(unittest.TestCase): - def test_loop_left(self): - a = Tensor.randn(16, 16) - b = Tensor.randn(16, 16) - with CLCache() as cache: - t = a.sum(0) - b = t.reshape(16,1).expand(16,16).sum(0) - c = (t+b) - c.realize() - assert cache.count == 2, "loop left fusion broken" - - def test_loop_right(self): - a = Tensor.randn(16, 16) - b = Tensor.randn(16, 16) - with CLCache() as cache: - t = a.sum(0) - b = t.reshape(16,1).expand(16,16).sum(0) - c = (b+t) - c.realize() - assert cache.count == 2, "loop right fusion broken" - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") -class TestOptWChild(unittest.TestCase): - @unittest.skip("this no longer happens, use realize") - def test_unrealized_child(self): - a = Tensor.randn(16, 16) - b = Tensor.randn(16, 16) - with CLCache() as cache: - c = (a*b).sum() - d = c+1 - e = c+2 # noqa: F841 - d.realize() - assert cache.count == 2, "don't fuse if you have children" - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") -class TestOpt(unittest.TestCase): - def test_muladd(self): - a,b,c = [Tensor.randn(2,2).realize() for _ in range(3)] - na,nb,nc = a.numpy(),b.numpy(),c.numpy() - with CLCache(allowed=1): - d = a * b + c - d.realize() - np.testing.assert_allclose(d.numpy(), na*nb+nc, rtol=1e-5, atol=1e-7) - - def test_permute_was_pushed(self): - a = Tensor.randn(16, 16, 16) - with CLCache(2): - c = a.sum(2) - d = c.permute(1,0).contiguous() - d.realize() - np.testing.assert_allclose(a.numpy().sum(2).transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) - - def test_permute_was_pushed_through_contract_reshape(self): - a = Tensor.randn(4, 4, 4, 4, 4) - with CLCache(2): - c = a.sum(-1) - d = c.reshape(16,16).permute(1,0).contiguous() - d.realize() - np.testing.assert_allclose(a.numpy().sum(-1).reshape(16,16).transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) - - def test_permute_was_pushed_through_contractw1s_reshape(self): - a = Tensor.randn(4, 4, 4, 4, 4) - with CLCache(2): - c = a.sum(-1) - d = c.reshape(16,1,16).permute(2,1,0).contiguous() - d.realize() - np.testing.assert_allclose(a.numpy().sum(-1).reshape(16,1,16).transpose(2,1,0), d.numpy(), rtol=1e-3, atol=1e-5) - - def test_permute_was_pushed_through_expand_reshape(self): - a = Tensor.randn(16, 16, 16) - with CLCache(2): - c = a.sum(2) - d = c.reshape(4,4,4,4).permute(2,3,0,1).contiguous() - d.realize() - np.testing.assert_allclose(a.numpy().sum(2).transpose(1,0).reshape(4,4,4,4), d.numpy(), rtol=1e-3, atol=1e-5) - - def test_no_reduceop_rerun(self): - a = Tensor.randn(16, 16, 16) - with CLCache() as cache: - c = a.sum(2) - d = a.sum(2).permute(1,0) - c.realize() - d.realize() - cache_len = cache.count - np.testing.assert_allclose(c.numpy().transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) - assert cache_len == 1, "reduceop was rerun!" - - def test_no_reduceop_rerun_alt(self): - a = Tensor.randn(16, 16, 16) - with CLCache() as cache: - c = a.sum(2).permute(1,0) - d = a.sum(2) - c.realize() - d.realize() - cache_len = cache.count - np.testing.assert_allclose(c.numpy(), d.numpy().transpose(1,0), rtol=1e-3, atol=1e-5) - assert cache_len == 1, "reduceop was rerun!" - - def test_expand_reduce_is_folded_on_same_axis(self): - with Context(FUSE_CONV_BW=1): - for axis in [0, 1]: - for n in [4, 8, 16]: - b = torch.ones(n, n).sum(axis).reshape(n, 1).expand(n, n).sum(axis) - with CLCache(allowed=2): - a = Tensor.ones(n, n).contiguous().sum(axis).reshape(n, 1).expand(n, n).sum(axis) - a.realize() - np.testing.assert_allclose(a.numpy(), b.numpy(), rtol=1e-3, atol=1e-5) - - def test_expand_reduce_is_folded_on_different_axes(self): - with Context(FUSE_CONV_BW=1): - axis1, axis2 = 0, 1 - for n in [4, 8, 16]: - b = torch.ones(n, n).sum(axis1).reshape(n, 1).expand(n, n).sum(axis2) - with CLCache(allowed=2): - a = Tensor.ones(n, n).contiguous().sum(axis1).reshape(n, 1).expand(n, n).sum(axis2) - a.realize() - np.testing.assert_allclose(a.numpy(), b.numpy(), rtol=1e-3, atol=1e-5) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_optim.py b/tinygrad/test/external/external_test_optim.py deleted file mode 100644 index 42abd884..00000000 --- a/tinygrad/test/external/external_test_optim.py +++ /dev/null @@ -1,175 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -import tensorflow as tf -import tensorflow_addons as tfa -from tensorflow.python.ops import math_ops -from extra.lr_scheduler import LRSchedulerGroup - -from tinygrad.tensor import Tensor -from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup - -from test.external.mlperf_resnet.lars_optimizer import LARSOptimizer - -from examples.mlperf.lr_schedulers import PolynomialDecayWithWarmup -from test.external.mlperf_resnet.lars_util import PolynomialDecayWithWarmup as PolynomialDecayWithWarmup_tf - -np.random.seed(1337) -x_init = np.random.randn(1,4).astype(np.float32) -W_init = np.random.randn(4,4).astype(np.float32) -m_init = np.random.randn(1,4).astype(np.float32) - -class TinyNet: - def __init__(self): - self.x = Tensor(x_init.copy(), requires_grad=True) - self.W = Tensor(W_init.copy(), requires_grad=True) - self.m = Tensor(m_init.copy()) - - def forward(self): - out = self.x.matmul(self.W).relu() - out = out.log_softmax(1) - out = out.mul(self.m).add(self.m).sum() - return out - -class TinyNetTF: - def __init__(self): - self.x = tf.Variable(x_init.copy(), trainable=True, name="x") - self.W = tf.Variable(W_init.copy(), trainable=True, name="W") - self.m = tf.constant(m_init.copy()) - - def forward(self): - out = tf.matmul(self.x, self.W) - out = tf.nn.relu(out) - out = tf.nn.log_softmax(out, axis=1) - out = tf.multiply(out, self.m) + self.m - out = tf.reduce_sum(out) - return out - -def step(optim, steps=1, kwargs={}, scheduler=None, schedopts=None, do_optim=True): - net = TinyNet() - optim = optim([net.x, net.W], **kwargs) - if scheduler is not None: scheduler = scheduler(optim, **schedopts) - lrs = [] - for _ in range(steps): - if do_optim: - out = net.forward() - optim.zero_grad() - out.backward() - lrs.append(optim.lr.item() if not isinstance(optim, OptimizerGroup) else optim.optimizers[0].lr.item()) - if do_optim: optim.step() - if scheduler is not None: scheduler.step() - return lrs, net.x.detach().numpy(), net.W.detach().numpy() - -def step_tf(optim, steps=1, kwargs={}, scheduler=None, schedopts=None, do_optim=True): - net = TinyNetTF() - if scheduler is not None: kwargs['lr'] = scheduler(**schedopts) - optim = optim(**kwargs) - lrs = [] - for _ in range(steps): - if do_optim: - with tf.GradientTape() as tape: - out = net.forward() - - lr_t = optim.learning_rate - # refer to test/external/mlperf_resnet/lars_optimizer.py:_prepare_local - if callable(lr_t): lr_t = lr_t(math_ops.cast(optim.iterations, tf.float32)) - lrs.append(lr_t) - - if do_optim: - grads = tape.gradient(out, [net.x, net.W]) - optim.apply_gradients(zip(grads, [net.x, net.W])) - # optim calls scheduler in tf - else: - optim._iterations.assign_add(1) - return lrs, net.x.numpy(), net.W.numpy() - -# skip list is skipping W -def create_tiny_lars(params, lr, skip_list=False): - if skip_list: return OptimizerGroup(LARS([params[0]], lr), SGD([params[1]], lr, classic=True, weight_decay=0., momentum=.9)) - return LARS(params, lr) -def create_tf_lars(lr, skip_list=False): return LARSOptimizer(lr, skip_list=["W"] if skip_list else None) - -def create_tiny_polylr(optim, initial_lr, end_lr, train_steps, warmup, power=2, skip_list=False): - assert power == 2 - if skip_list: return LRSchedulerGroup( - PolynomialDecayWithWarmup(optim[0], initial_lr, end_lr, train_steps, warmup, power), - PolynomialDecayWithWarmup(optim[1], initial_lr, end_lr, train_steps, warmup, power)) - return PolynomialDecayWithWarmup(optim, initial_lr, end_lr, train_steps, warmup, power) -def create_tf_polylr(initial_lr, end_lr, train_steps, warmup, power=2, skip_list=False): - assert power == 2 - return PolynomialDecayWithWarmup_tf(1, 1, train_steps, - initial_learning_rate=initial_lr, end_learning_rate=end_lr, warmup_epochs=warmup) - -class ExternalTestOptim(unittest.TestCase): - def setUp(self): - self.old_training = Tensor.training - Tensor.training = True - def tearDown(self): - Tensor.training = self.old_training - - def _test_optim(self, tinygrad_optim, tensorflow_optim, steps, opts, atol, rtol, tiny_sched=None, tf_sched=None, schedopts=None, do_optim=True): - for x,y in zip(step(tinygrad_optim, steps=steps, kwargs=opts, scheduler=tiny_sched, schedopts=schedopts, do_optim=do_optim), - step_tf(tensorflow_optim, steps=steps, kwargs=opts, scheduler=tf_sched, schedopts=schedopts, do_optim=do_optim)): - np.testing.assert_allclose(x, y, atol=atol, rtol=rtol) - - def _test_lamb(self, steps, opts, atol, rtol): self._test_optim(LAMB, tfa.optimizers.LAMB, steps, opts, atol, rtol) - def _test_lars(self, steps, opts, atol, rtol): self._test_optim(create_tiny_lars, create_tf_lars, steps, opts, atol, rtol) - def _test_lars_polylr(self, steps, opts, schedopts, atol, rtol, do_optim=True): - self._test_optim(create_tiny_lars, create_tf_lars, steps, opts, atol, rtol, - tiny_sched=create_tiny_polylr, tf_sched=create_tf_polylr, schedopts=schedopts, do_optim=do_optim) - - def test_lamb(self): self._test_lamb(1, {'lr': 0.001}, 1e-5, 0) - def test_lamb_high_lr(self): self._test_lamb(1, {'lr': 10}, 1e-5, 1e-5) - - def test_multistep_lamb(self): self._test_lamb(10, {'lr': 0.001}, 1e-5, 0) - def test_multistep_lamb_high_lr(self): self._test_lamb(10, {'lr': 10}, 1e-5, 3e-4) - - def test_lars(self): self._test_lars(1, {'lr': 0.01}, 1e-5, 0) - def test_lars_high_lr(self): self._test_lars(1, {'lr': 10}, 1e-5, 1e-5) - def test_multistep_lars(self): self._test_lars(10, {'lr': 0.001}, 1e-5, 0) - def test_multistep_lars_high_lr(self): self._test_lars(10, {'lr': 10}, 1e-5, 3e-4) - def test_lars_skip(self): self._test_lars(10, {'lr': 10, 'skip_list': True}, 1e-5, 3e-4) - def test_lars_skip_high_lr(self): self._test_lars(1, {'lr': 10, 'skip_list': True}, 1e-5, 1e-5) - def test_lars_skip_multistep(self): self._test_lars(10, {'lr': 0.001, 'skip_list': True}, 1e-5, 0) - def test_lars_skip_multistep_high_lr(self): self._test_lars(10, {'lr': 10, 'skip_list': True}, 1e-5, 3e-4) - - def test_lars_polylr(self): - self._test_lars_polylr(10, {'lr': 1.0}, { - 'initial_lr': 1.0, - 'end_lr': 1e-4, - 'train_steps': 10, - 'warmup': 3 - }, 1e-5, 1e-5) - def test_lars_polylr_large(self): - self._test_lars_polylr(100, {'lr': 10.0}, { - 'initial_lr': 10.0, - 'end_lr': 1e-5, - 'train_steps': 100, - 'warmup': 43 - }, 1e-5, 1e-5, do_optim=False) - def test_lars_polylr_skip(self): - self._test_lars_polylr(10, {'lr': 1.0, 'skip_list': True}, { - 'initial_lr': 1.0, - 'end_lr': 1e-4, - 'train_steps': 10, - 'warmup': 3, - 'skip_list': True - }, 1e-5, 1e-5) - - @unittest.skip("slow, but you can run this locally to check") - def test_lars_polylr_resnet(self): - train_files = 1_281_167 - BS = 624 - steps_per_epoch = train_files // BS - epochs = 45 - warmup_epochs = 5 - self._test_lars_polylr(steps_per_epoch * epochs, {'lr': 10.4}, { - 'initial_lr': 10.4, - 'end_lr': 1e-4, - # step counts for BS=624 EPOCHS=45 resnet - 'train_steps': steps_per_epoch * epochs, - 'warmup': steps_per_epoch * warmup_epochs, - }, 1e-5, 1e-5, do_optim=False) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_speed_llama.py b/tinygrad/test/external/external_test_speed_llama.py deleted file mode 100644 index 3d468e62..00000000 --- a/tinygrad/test/external/external_test_speed_llama.py +++ /dev/null @@ -1,58 +0,0 @@ -# NOTE: this only tests the speed of the LLaMA codegen, it doesn't actually run the net -import unittest, time -from examples.llama import Transformer, MODEL_PARAMS -from tinygrad.tensor import Tensor -from tinygrad import Device -from tinygrad.nn.state import get_state_dict -from tinygrad.device import Allocator, Compiled -from tinygrad.engine.realize import method_cache -from tinygrad.helpers import Profiling - -class FakeProgram: - def __init__(self, name:str, prg:bytes): pass - def __call__(self, *bufs, global_size, local_size, vals=(), wait=False): pass - -class FakeAllocator(Allocator[Compiled]): - def _alloc(self, sz, options): return None - def _copyin(self, dest, src:memoryview): pass - -class TestLLaMASpeed(unittest.TestCase): - def test_llama_compile(self): - backup_program = Device[Device.DEFAULT].runtime - backup_allocator = Device[Device.DEFAULT].allocator - backup_compiler = Device[Device.DEFAULT].compiler - Device[Device.DEFAULT].runtime = FakeProgram - Device[Device.DEFAULT].allocator = FakeAllocator(Device.default) - - print("testing llama python run time") - model = Transformer(**MODEL_PARAMS["1"]["7B"]["args"]) - print("built model") - # assign fake tensors to the values - for v in get_state_dict(model).values(): v.assign(Tensor.empty(*v.shape, dtype=v.dtype)) - print("assigned empty tensors, doing warmup") - - def run_llama(st, empty_method_cache=True): - if empty_method_cache: method_cache.clear() - tms = [time.perf_counter()] - for i in range(5): - model(Tensor([[1,2,3,4]]), i).realize() - tms.append(time.perf_counter()) - timings = [(tms[i+1]-tms[i])*1000 for i in range(len(tms)-1)] - print(f"{st:15s} mean runtime: {sum(timings)/len(timings):7.2f}ms, runs: ", ", ".join(f'{x:7.2f}' for x in timings)) - - run_llama("codegen(0)") - run_llama("codegen(1)") - - # test no compiler use for this - Device[Device.DEFAULT].compiler = None - run_llama("methodcache", False) - with Profiling(sort='time', frac=0.1, fn="/tmp/llama.prof", ts=5): - run_llama("profile", False) - - Device[Device.DEFAULT].runtime = backup_program - Device[Device.DEFAULT].allocator = backup_allocator - Device[Device.DEFAULT].compiler = backup_compiler - -if __name__ == '__main__': - TestLLaMASpeed().test_llama_compile() - #unittest.main() diff --git a/tinygrad/test/external/external_test_speed_theoretical.py b/tinygrad/test/external/external_test_speed_theoretical.py deleted file mode 100644 index ea0f2604..00000000 --- a/tinygrad/test/external/external_test_speed_theoretical.py +++ /dev/null @@ -1,48 +0,0 @@ -import time, unittest -from tinygrad import Tensor, TinyJit, Device, dtypes -from tinygrad.helpers import getenv, GlobalCounters - -SZMAX = getenv("SZMAX", 10) -SZMIN = min(SZMAX, getenv("SZMIN", 10)) -def _test(tcount, fxn, dtype=dtypes.float): - print(f"**** testing {fxn.__name__} {dtype}") - allgbs = [] - for sz in range(SZMIN, SZMAX+1): - jfxn = TinyJit(fxn) - ts = [Tensor.zeros((2**sz)*1024*1024, dtype=dtype).contiguous().realize() for _ in range(tcount)] - tms = [] - for _ in range(10): - ts = [(x+1).realize() for x in ts] - Device.default.synchronize() - GlobalCounters.global_ops = 0 - GlobalCounters.global_mem = 0 - st = time.perf_counter() - jfxn(*ts).nbytes() - Device.default.synchronize() - tms.append(time.perf_counter() - st) - ops, mem = GlobalCounters.global_ops, GlobalCounters.global_mem - gflops = ops*1e-9/min(tms) - gbs = mem*1e-9/min(tms) - print(f"{ts[0].nbytes()/(1024*1024):10.0f} MB, {min(tms)*1e3:6.2f} ms {gbs:10.2f} GB/s {gflops:10.2f} GFLOPS {str(ts[0].shape):20s}") - allgbs.append(gbs) - return max(allgbs) - -MEMBW = getenv("MEMBW", 10) -class TestRamBandwidth(unittest.TestCase): - def test_add(self): self.assertGreater(_test(2, Tensor.add), MEMBW) - def test_exp(self): self.assertGreater(_test(1, Tensor.exp), MEMBW) - def test_sum(self): self.assertGreater(_test(1, Tensor.sum), MEMBW) - -# ratio between MEM and FLOPS < 1000 -# NOTE: On AMD, (x*x)+1 gets ~30 TFLOPS, (x*x)+3 gets ~60 TFLOPS -def flopsmax(x): - for _ in range(500): x = (x*x)+3 - return x - -class TestFlops(unittest.TestCase): - def test_flops_int8(self): _test(1, flopsmax, dtypes.int8) - def test_flops_fp16(self): _test(1, flopsmax, dtypes.half) - def test_flops_fp32(self): _test(1, flopsmax) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_tlsf.py b/tinygrad/test/external/external_test_tlsf.py deleted file mode 100644 index aa780fdd..00000000 --- a/tinygrad/test/external/external_test_tlsf.py +++ /dev/null @@ -1,78 +0,0 @@ -import unittest -from tinygrad.runtime.support.allocator import TLSFAllocator - -class TestTLSFAllocator(unittest.TestCase): - def setUp(self): - self.allocator = TLSFAllocator(1024, block_size=16) - - def test_basic_alloc_free(self): - addr1 = self.allocator.alloc(32) - self.assertEqual(addr1, 0) - - addr2 = self.allocator.alloc(64) - self.assertEqual(addr2, 32) - - self.allocator.free(addr1) - addr3 = self.allocator.alloc(32) - self.assertEqual(addr3, 0) - - def test_block_size_alignment(self): - addr1 = self.allocator.alloc(20) - addr2 = self.allocator.alloc(35) - - self.assertEqual(addr1 % 16, 0) - self.assertEqual(addr2 % 16, 0) - - def test_merge_blocks(self): - addr1 = self.allocator.alloc(32) - addr2 = self.allocator.alloc(32) - self.allocator.alloc(32) - - self.allocator.free(addr1) - self.allocator.free(addr2) - addr4 = self.allocator.alloc(64) - self.assertEqual(addr4, addr1) - - def test_split_blocks(self): - addr1 = self.allocator.alloc(128) - self.allocator.free(addr1) - - addr2 = self.allocator.alloc(32) - self.assertEqual(addr2, addr1) - - addr3 = self.allocator.alloc(32) - self.assertEqual(addr3, addr1 + 32) - - def test_out_of_memory(self): - with self.assertRaises(MemoryError): - self.allocator.alloc(2048) - - def test_fragmentation_handling(self): - addrs = [] - for _ in range(5): - addrs.append(self.allocator.alloc(32)) - - # Free alternate blocks - for i in range(0, len(addrs), 2): - self.allocator.free(addrs[i]) - - def test_custom_start_address(self): - allocator = TLSFAllocator(1024, start_addr=1000) - addr1 = allocator.alloc(32) - self.assertEqual(addr1, 1000) - - addr2 = allocator.alloc(64) - self.assertEqual(addr2, 1032) - - def test_block_tracking(self): - addr1 = self.allocator.alloc(32) - addr2 = self.allocator.alloc(64) - - self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) - self.assertTrue(addr2 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) - - self.allocator.free(addr1) - self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_train_gpt2.py b/tinygrad/test/external/external_test_train_gpt2.py deleted file mode 100644 index 6d3a1cb9..00000000 --- a/tinygrad/test/external/external_test_train_gpt2.py +++ /dev/null @@ -1,55 +0,0 @@ -# ruff: noqa: E501 -import unittest - -from tinygrad.uop.ops import UOp, Ops -from tinygrad.engine.search import Opt, OptOps -from tinygrad.dtype import dtypes -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.codegen.kernel import Kernel - -from test.external.fuzz_linearizer import run_linearizer - -class TestTrainGpt2Kernel(unittest.TestCase): - def test_1(self): - # kernel 244 - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(206045184), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 1), strides=(51511296, 50304, 1, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3145728), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(786432, 768, 0, 1), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(38633472), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(0, 0, 768, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - - opts = [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=3), Opt(op=OptOps.LOCAL, axis=0, arg=2)] - kernel = Kernel(ast) - kernel.apply_opts(opts) - run_linearizer(kernel) - - def test_2(self): - # kernel 254 - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3145728), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 1, 768), strides=(786432, 768, 0, 1), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(38633472), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(0, 0, 768, 1), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(205852672), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(51463168, 50257, 1, 0), offset=0, mask=((0, 4), (0, 1024), (0, 50257), (0, 768)), contiguous=False),)), src=()),)),)),)),)),)) - - opts = [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=4)] - kernel = Kernel(ast) - kernel.apply_opts(opts) - run_linearizer(kernel) - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/external/external_test_usb_asm24.py b/tinygrad/test/external/external_test_usb_asm24.py deleted file mode 100644 index 3df81b28..00000000 --- a/tinygrad/test/external/external_test_usb_asm24.py +++ /dev/null @@ -1,73 +0,0 @@ -import unittest, time -from tinygrad.runtime.support.usb import ASM24Controller -from tinygrad.helpers import Timing -from tinygrad import Tensor, Device -import numpy as np - -class TestASMController(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.ctrl = ASM24Controller() - - def test_write_and_read(self): - base = 0xF000 - data = b"hello!" - self.ctrl.write(base, data) - out = self.ctrl.read(base, len(data)) - self.assertEqual(out, data) - - def test_scsi_write_and_read_from_f000(self): - payload = bytes([0x5B]) * 4096 - self.ctrl.scsi_write(payload, lba=0) - back = self.ctrl.read(0xF000, len(payload)) - self.assertEqual(back, payload) - - def test_scsi_write_speed_4k(self): - payload = bytes([0x5A]) * 4096 - start = time.perf_counter() - self.ctrl.scsi_write(payload, lba=0) - dur_ms = (time.perf_counter() - start) * 1000 - print(f"scsi_write 4K took {dur_ms:.3f} ms") - - def test_read_speed_4k(self): - payload = bytes([0xA5]) * 4096 - self.ctrl.write(0xF000, payload) - start = time.perf_counter() - out = self.ctrl.read(0xF000, 4096) - dur_ms = (time.perf_counter() - start) * 1000 - print(f"read 4K took {dur_ms:.3f} ms") - self.assertEqual(out, payload) - -class TestDevCopySpeeds(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.sz = 512 - cls.dev = Device["AMD"] - if not cls.dev.is_usb(): raise unittest.SkipTest("only test this on USB devices") - - def testCopyCPUtoDefault(self): - for _ in range(10): - t = Tensor.ones(self.sz, self.sz, device="CPU").contiguous().realize() - with Timing(f"copyin of {t.nbytes()/1e6:.2f} MB: ", on_exit=lambda ns: f" @ {t.nbytes()/ns * 1e3:.2f} MB/s"): # noqa: F821 - t.to(Device.DEFAULT).realize() - Device[Device.DEFAULT].synchronize() - del t - - def testCopyDefaulttoCPU(self): - t = Tensor.ones(self.sz, self.sz).contiguous().realize() - for _ in range(10): - with Timing(f"copyout of {t.nbytes()/1e6:.2f} MB: ", on_exit=lambda ns: f" @ {t.nbytes()/ns * 1e3:.2f} MB/s"): - t.to('CPU').realize() - - def testValidateCopies(self): - t = Tensor.randn(self.sz, self.sz, device="CPU").contiguous().realize() - x = t.to(Device.DEFAULT).realize() - Device[Device.DEFAULT].synchronize() - - y = x.to('CPU').realize() - - np.testing.assert_equal(t.numpy(), y.numpy()) - del x, y, t - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/external/external_test_valid_remove.py b/tinygrad/test/external/external_test_valid_remove.py deleted file mode 100644 index 65f8112e..00000000 --- a/tinygrad/test/external/external_test_valid_remove.py +++ /dev/null @@ -1,121 +0,0 @@ -# ruff: noqa: E501 -import unittest - -from tinygrad import Device -from tinygrad.uop.ops import UOp, Ops -from tinygrad.engine.search import Opt, OptOps -from tinygrad.dtype import dtypes -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.codegen.kernel import Kernel - -class TestOpenpilotValidhack(unittest.TestCase): - def test_valid_removal(self): - Device.DEFAULT = "GPU" - - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((64, 1024, 4)), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 4096, 32, 0, 0, 4, 1, 0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MAX, dtypes.float, arg=None, src=( - x5:=UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 8, 9, 10)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((128, 768, 4)), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 3, 1, 4, 4, 130, 4, 258), strides=(0, 0, 0, 0, 0, 4, 0, 1, 0, 3072, 0, 12), offset=-3084, mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 1), (0, 3), (0, 1), (0, 4), (0, 4), (1, 129), (0, 4), (1, 257)), contiguous=False), View(shape=(1, 64, 128, 1, 1, 8, 4, 3, 4, 3, 3), strides=(0, 2064, 2, 0, 0, 0, 0, 2146560, 536640, 135192, 259), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((8, 108, 4)), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 3, 4, 3, 3), strides=(0, 0, 0, 0, 0, 432, 1, 48, 4, 144, 16), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 4, 1, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - x19:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x20:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x20,)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - x5, - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - x20,)),)),)), - x29:=UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x20,)),)),)), - x19,)), - x29,)),)),)),)) - - opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.NOLOCALS, axis=None, arg=None)] - kernel = Kernel(ast) - - kernel.apply_opts(opts) - - p = kernel.to_program() - print(p.src) - - def test_const_idx(self): - Device.DEFAULT = "GPU" - - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((10, 128, 4)), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 512, 1), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((1, 128, 4)), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=0, mask=((0, 1), (0, 1), (0, 512)), contiguous=False),)), src=()),)), - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=48128, mask=((0, 1), (1, 2), (0, 512)), contiguous=False),)), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=45568, mask=((0, 1), (2, 3), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=43008, mask=((0, 1), (3, 4), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=40448, mask=((0, 1), (4, 5), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=37888, mask=((0, 1), (5, 6), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=35328, mask=((0, 1), (6, 7), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=32768, mask=((0, 1), (7, 8), (0, 512)), contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - x18, - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=30208, mask=((0, 1), (8, 9), (0, 512)), contiguous=False),)), src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((1, 128, 4)), arg=3, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=0, mask=((0, 1), (9, 10), (0, 512)), contiguous=False),)), src=()),)),)),)),)),)) - - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.NOLOCALS, axis=None, arg=None)] - kernel = Kernel(ast) - - kernel.apply_opts(opts) - - p = kernel.to_program() - # ((idx1<1)?read_imagef(data1, smp, (int2)(idx0,0)):(float4)(0.0f,0.0f,0.0f,0.0f)) - print(p.src) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_whisper_librispeech.py b/tinygrad/test/external/external_test_whisper_librispeech.py deleted file mode 100644 index 264bb3f0..00000000 --- a/tinygrad/test/external/external_test_whisper_librispeech.py +++ /dev/null @@ -1,83 +0,0 @@ -import unittest -import torch -import tqdm -import torchaudio -import pathlib -import jiwer -import os -import numpy as np -from whisper.normalizers import EnglishTextNormalizer -from examples.whisper import init_whisper, transcribe_waveform - -class TestWhisperLibriSpeech(unittest.TestCase): - # reference WERs determined by running https://github.com/openai/whisper/blob/main/notebooks/LibriSpeech.ipynb - # the values should be consistent with the paper D.1.1 https://cdn.openai.com/papers/whisper.pdf#page=22 - # tinygrad WERs do not perfectly match due to what seem to be precision differences vs torch - def test_en_tiny(self): - run_evaluation("tiny.en", 0.056629001883239174, 0.05655609406528749) - - def test_tiny(self): - run_evaluation("tiny", 0.0771121409407306, 0.07558413638335187) - - def test_en_base(self): - run_evaluation("base.en", 0.041412520064205455, 0.04271408904897505) - - def test_en_small(self): - run_evaluation("small.en", 0.03369011117172363, 0.030531615969223228) - -def run_evaluation(model_name, tinygrad_expected_wer, reference_wer): - dataset = LibriSpeech() - batch_size=16 - loader = torch.utils.data.DataLoader(dataset, batch_size=batch_size) - - model, enc = init_whisper(model_name, batch_size=batch_size) - - hypotheses = [] - references = [] - - for audio, texts in tqdm.tqdm(loader): - transcriptions = transcribe_waveform(model, enc, audio.numpy(), truncate=True) - hypotheses.extend(transcriptions) - references.extend(texts) - - normalizer = EnglishTextNormalizer() - normalized_hypotheses = [normalizer(text) for text in hypotheses] - normalized_references = [normalizer(text) for text in references] - wer = jiwer.wer(normalized_hypotheses, normalized_references) - - np.testing.assert_almost_equal(wer, tinygrad_expected_wer) - print(f'tinygrad WER {wer} vs reference WER {reference_wer}') - del model, enc - -class LibriSpeech(torch.utils.data.Dataset): - def __init__(self): - folder = pathlib.Path(__file__).parent.parent.parent / "extra" / "datasets" / "librispeech" - if not os.path.exists(folder): - os.makedirs(folder) - - self.dataset = torchaudio.datasets.LIBRISPEECH( - root=folder, - url="test-clean", - download=True, - ) - - def __len__(self): - return len(self.dataset) - - def __getitem__(self, item): - audio, sample_rate, text, _, _, _ = self.dataset[item] - assert sample_rate == 16000 - return pad_or_trim_tensor(audio[0]), text - -def pad_or_trim_tensor(tensor, target_len=480000): - curr_len = len(tensor) - if curr_len == target_len: - return tensor - elif curr_len < target_len: - return torch.cat((tensor, torch.zeros(target_len - curr_len))) - else: - return tensor[:target_len] - - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_yolo.py b/tinygrad/test/external/external_test_yolo.py deleted file mode 100644 index f28f23aa..00000000 --- a/tinygrad/test/external/external_test_yolo.py +++ /dev/null @@ -1,32 +0,0 @@ -import unittest -from pathlib import Path - -import cv2 - -from examples.yolov3 import Darknet, infer, show_labels -from tinygrad.helpers import fetch - -chicken_img = cv2.imread(str(Path(__file__).parent.parent / 'models/efficientnet/Chicken.jpg')) -car_img = cv2.imread(str(Path(__file__).parent.parent / 'models/efficientnet/car.jpg')) - -class TestYOLO(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.model = Darknet(fetch("https://raw.githubusercontent.com/pjreddie/darknet/master/cfg/yolov3.cfg").read_bytes()) - print("Loading weights file (237MB). This might take a while…") - cls.model.load_weights("https://pjreddie.com/media/files/yolov3.weights") - - @classmethod - def tearDownClass(cls): - del cls.model - - def test_chicken(self): - labels = show_labels(infer(self.model, chicken_img), confidence=0.56) - self.assertEqual(labels, ["bird"]) - - def test_car(self): - labels = show_labels(infer(self.model, car_img)) - self.assertEqual(labels, ["car"]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_test_yolov8.py b/tinygrad/test/external/external_test_yolov8.py deleted file mode 100644 index 5506fae7..00000000 --- a/tinygrad/test/external/external_test_yolov8.py +++ /dev/null @@ -1,73 +0,0 @@ -import numpy as np -from examples.yolov8 import YOLOv8, get_variant_multiples, preprocess, label_predictions, postprocess -from tinygrad import Tensor -import unittest -import io, cv2 -import onnxruntime as ort -import ultralytics -from tinygrad.nn.state import safe_load, load_state_dict -from tinygrad.helpers import fetch - -class TestYOLOv8(unittest.TestCase): - def test_all_load_weights(self): - for variant in ['n', 's', 'm', 'l', 'x']: - depth, width, ratio = get_variant_multiples(variant) - TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) - state_dict = safe_load(fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors')) - load_state_dict(TinyYolov8, state_dict) - print(f'successfully loaded weights for yolov{variant}') - - def test_predictions(self): - test_image_urls = ['https://raw.githubusercontent.com/ultralytics/yolov5/master/data/images/bus.jpg', 'https://www.aljazeera.com/wp-content/uploads/2022/10/2022-04-28T192650Z_1186456067_UP1EI4S1I0P14_RTRMADP_3_SOCCER-ENGLAND-MUN-CHE-REPORT.jpg'] - variant = 'n' - depth, width, ratio = get_variant_multiples(variant) - TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) - state_dict = safe_load(fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors')) - load_state_dict(TinyYolov8, state_dict) - - for i in range(len(test_image_urls)): - img = cv2.imdecode(np.frombuffer(fetch(test_image_urls[i]).read_bytes(), np.uint8), 1) - test_image = preprocess([img]) - predictions = TinyYolov8(test_image) - labels = label_predictions(predictions.numpy()) - assert labels == {5: 1, 0: 4, 11: 1} if i == 0 else labels == {0: 12, 29: 1, 32: 1} - - def test_forward_pass_torch_onnx(self): - variant = 'n' - weights_location = fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors') - weights_location_pt = fetch(f'https://github.com/ultralytics/assets/releases/download/v0.0.0/yolov8{variant}.pt', name=f"yolov8{variant}.pt") # it needs the pt extension # noqa: E501 - weights_location_onnx = weights_location_pt.parent / f"yolov8{variant}.onnx" - - # the ultralytics export prints a lot of unneccesary things - if not weights_location_onnx.is_file(): - model = ultralytics.YOLO(model=weights_location_pt, task='Detect') - model.export(format="onnx",imgsz=[640, 480]) - - depth, width, ratio = get_variant_multiples(variant) - TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) - state_dict = safe_load(weights_location) - load_state_dict(TinyYolov8, state_dict) - - image_location = [np.frombuffer(io.BytesIO(fetch('https://raw.githubusercontent.com/ultralytics/yolov5/master/data/images/bus.jpg').read_bytes()).read(), np.uint8)] # noqa: E501 - orig_image = [cv2.imdecode(image_location[0], 1)] - - input_image = preprocess(orig_image) - - onnx_session = ort.InferenceSession(weights_location_onnx) - onnx_input_name = onnx_session.get_inputs()[0].name - onnx_output_name = onnx_session.get_outputs()[0].name - onnx_output = onnx_session.run([onnx_output_name], {onnx_input_name: input_image.numpy()}) - - tiny_output = TinyYolov8(input_image).numpy() - onnx_output = postprocess(Tensor(onnx_output[0])).numpy() - #invalid boxes are multiplied by zero in postprocess - onnx_output = onnx_output[onnx_output[:, 4] != 0] - tiny_output = tiny_output[tiny_output[:, 4] != 0] - - # currently rtol is 0.025 because there is a 1-2% difference in our predictions - # because of the zero padding in SPPF module (line 280) maxpooling layers rather than the -infinity in torch. - # This difference does not make a difference "visually". - np.testing.assert_allclose(onnx_output, tiny_output, atol=5e-4, rtol=0.025) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/external_uop_gc.py b/tinygrad/test/external/external_uop_gc.py deleted file mode 100644 index 03f6169b..00000000 --- a/tinygrad/test/external/external_uop_gc.py +++ /dev/null @@ -1,72 +0,0 @@ -import gc -from tinygrad import Tensor, UOp, Device -from tinygrad.shape.shapetracker import views_to_indexed_uops -from tinygrad.engine.realize import method_cache, get_kernel - -def uops_allocated(): return sum([isinstance(x, UOp) for x in gc.get_objects()]) -def print_uops(): - for x in gc.get_objects(): - if isinstance(x, UOp): print(x) - -def start(): pass -def single_tensor(): Tensor([2]) -def two_plus_two(): Tensor([2])+Tensor([2]) -def two_plus_two_schedule(): (Tensor([2])+Tensor([2])).schedule() -def two_plus_two_kernel(): - si = (Tensor([2])+Tensor([2])).schedule()[-1] - get_kernel(Device.default.renderer, si.ast) -def two_plus_two_linearize(): - si = (Tensor([2])+Tensor([2])).schedule()[-1] - k = get_kernel(Device.default.renderer, si.ast) - k.get_optimized_ast() - #k.linearize() -def two_plus_two_realize(): (Tensor([2])+Tensor([2])).realize() -def two_plus_two_item(): (Tensor([2])+Tensor([2])).item() -def gradient_test(): - x = Tensor.eye(3, requires_grad=True) - y = Tensor([[2.0,0,-2.0]], requires_grad=True) - z = y.matmul(x).sum() - z.backward() -def realized_eye(): - Tensor.eye(3, requires_grad=True).realize() -def realized_list(): - Tensor([[2.0,0,-2.0]], requires_grad=True).realize() -def kernel_matmul(): - x = Tensor.eye(3, requires_grad=True) - y = Tensor([[2.0,0,-2.0]], requires_grad=True) - z = y.matmul(x) - si = z.schedule()[-1] - get_kernel(Device.default.renderer, si.ast) -def realized_matmul(): - x = Tensor.eye(3, requires_grad=True) - y = Tensor([[2.0,0,-2.0]], requires_grad=True) - z = y.matmul(x) - Tensor.realize(z) -def realized_gradient(): - x = Tensor.eye(3, requires_grad=True) - y = Tensor([[2.0,0,-2.0]], requires_grad=True) - z = y.matmul(x).sum() - z.backward() - Tensor.realize(x, y, z, x.grad, y.grad) -tests = [start, single_tensor, two_plus_two, two_plus_two_schedule, two_plus_two_kernel, - two_plus_two_linearize, two_plus_two_realize, two_plus_two_item, gradient_test, - realized_eye, realized_list, kernel_matmul, realized_matmul, realized_gradient] - -if __name__ == "__main__": - gc.disable() - start_uops = uops_allocated() - # there's a few consts created as default values - print_uops() - for t in tests: - t() - - # these caches will keep uops alive - method_cache.clear() - views_to_indexed_uops.cache_clear() - - new_uops = uops_allocated() - gc.collect() - new_uops_gc = uops_allocated() - print(f"{t.__name__:30s}: {new_uops:3d} -> {new_uops_gc:3d}") - assert new_uops == start_uops - #print_uops() diff --git a/tinygrad/test/external/fuzz_fast_idiv.py b/tinygrad/test/external/fuzz_fast_idiv.py deleted file mode 100644 index c7bf90b8..00000000 --- a/tinygrad/test/external/fuzz_fast_idiv.py +++ /dev/null @@ -1,33 +0,0 @@ -import random -from z3 import Int, Solver, sat -from tinygrad import dtypes, Device -from tinygrad.uop.ops import UOp, Ops, UPat, graph_rewrite, PatternMatcher -from tinygrad.codegen.devectorizer import fast_idiv -random.seed(42) - -z3_renderer = PatternMatcher([ - (UPat((Ops.DEFINE_VAR, Ops.SPECIAL), name="x"), lambda x: UOp(Ops.NOOP, arg=x.arg[0])), - # Because fast_idiv only works for non-negative integers we can emulate machine arithmetic with modulo operations. - (UPat(Ops.SHR, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(({x.src[0].arg}/(2**{x.src[1].arg}))%{dtypes.max(x.dtype)+1})")), - (UPat(Ops.MUL, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(({x.src[0].arg}*{x.src[1].arg})%{dtypes.max(x.dtype)+1})")), - (UPat((Ops.CONST, Ops.VCONST), name="x"), lambda x: UOp(Ops.NOOP, arg=str(x.arg))), - (UPat(Ops.CAST, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"{x.src[0].arg}")), -]) - -def render(self) -> str: - ret = graph_rewrite(self.simplify(), z3_renderer) - return ret.arg if ret.op is Ops.NOOP else str(ret) - -if __name__ == "__main__": - x = Int('x') - for _ in range(10_000): - dt = random.choice(dtypes.ints) - u = UOp(Ops.DEFINE_VAR, dt, arg=('x', 0, random.randint(1, dtypes.max(dt))), src=()) - d = random.randint(1, max(1, u.arg[2])) - - expr = fast_idiv(Device[Device.DEFAULT].renderer, u, d) - if expr is None: continue - solver = Solver() - solver.add(x>=u.arg[1], x<=u.arg[2]) - if solver.check(eval(render(expr)) != x/d) == sat: - assert False, f"Failed: {render(expr)} != x//{d} at x={solver.model()[x]}\nx={u}\nd={d}" diff --git a/tinygrad/test/external/fuzz_graph.py b/tinygrad/test/external/fuzz_graph.py deleted file mode 100644 index 4e1d492e..00000000 --- a/tinygrad/test/external/fuzz_graph.py +++ /dev/null @@ -1,128 +0,0 @@ -import random, ctypes -import numpy as np -from tinygrad.device import Buffer, Device -from tinygrad.helpers import Context, getenv, from_mv -from tinygrad.dtype import dtypes -from tinygrad.tensor import Tensor, _to_np_dtype -from tinygrad.engine.realize import ExecItem, BufferXfer, get_runner -from tinygrad.engine.jit import apply_graph_to_jit - -BUF_LEN = getenv("BUF_LEN", 128) - -cached_prgs = {} -def gen_prg(device, inputs_cnt): - if (device, inputs_cnt) in cached_prgs: return cached_prgs[(device, inputs_cnt)] - - with Context(DEBUG=0): - fst = [Tensor.randn(BUF_LEN, dtype=dtypes.int).realize() for i in range(inputs_cnt)] - s = fst[0] - for i in range(1, inputs_cnt): s = s.bitwise_xor(fst[i]) - - si = s.schedule()[-1] - prg = get_runner(device, si.ast) - cached_prgs[(device, inputs_cnt)] = prg - return prg - -def alloc_rawbuffer(device, fill=False): - rawbuf = Buffer(device, BUF_LEN, dtypes.int).ensure_allocated() - if fill: - with Context(DEBUG=0): - data = np.random.randint(-10000, 10000, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) - rawbuf.copyin(Tensor(data).realize().uop.base.realized.as_buffer()) - return rawbuf - -def gen_kernel_ji(device, deps): - assert len(deps) >= 2 - out = alloc_rawbuffer(device) - prg = gen_prg(device, len(deps)) - return ExecItem(prg, [out] + deps) - -def gen_copy_ji(device, deps): - assert len(deps) == 1 - out = alloc_rawbuffer(device) - prg = BufferXfer(deps[0].nbytes, device, deps[0].device) - return ExecItem(prg, [out] + deps) - -def gen_graph(): - input_buffers = [] - all_buffers = [] - jis = [] - - last_n_deps = getenv("LAST_N_DEPS", 0) - - kernel_count = random.randint(2, getenv("MAX_KERNELS", 128)) - for i in range(kernel_count): - target_device_id = random.randint(0, getenv("MAX_DEVICES", 6) - 1) - target_device = f"{Device.DEFAULT}:{target_device_id}" - is_copy = random.randint(0, 10) < 3 - - if is_copy: - deps_pool = [buf for buf in all_buffers[-last_n_deps:] if buf.device != target_device] - if len(deps_pool) == 0: deps = [] - else: deps = random.sample(deps_pool, 1) - else: - deps_pool = [buf for buf in all_buffers[-last_n_deps:] if buf.device == target_device] - deps_count = random.randint(0, min(getenv("MAX_DEPS_COUNT", 6), len(deps_pool))) - if deps_count == 0: deps = [] - else: deps = random.sample(deps_pool, deps_count) - - if len(deps) == 0 or (not is_copy and len(deps) < 2): - buf = alloc_rawbuffer(target_device, fill=True) - input_buffers.append(buf) - all_buffers.append(buf) - elif is_copy: - jis.append(gen_copy_ji(target_device, deps)) - all_buffers.append(jis[-1].bufs[0]) - else: - jis.append(gen_kernel_ji(target_device, deps)) - all_buffers.append(jis[-1].bufs[0]) - - return jis, all_buffers, input_buffers - -def run_jit(jis, all_buffers, input_buffers, var_vals): - with Context(DEBUG=0): - for rawbuf in all_buffers: - if rawbuf in input_buffers: continue - mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) - ctypes.memset(from_mv(mv), 0, len(mv)) - rawbuf.copyin(mv) - - for ei in jis: ei.run(var_vals, jit=True) - - with Context(DEBUG=0): - res_buffers = [] - for rawbuf in all_buffers: res_buffers.append(rawbuf.as_buffer()) - return res_buffers - -def fuzz_graph(jis, all_buffers, input_buffers): - ground_thruth_bufs = run_jit(jis, input_buffers, all_buffers, {}) - ground_truth_np = [np.frombuffer(x, _to_np_dtype(all_buffers[i].dtype)) for i,x in enumerate(ground_thruth_bufs)] - - for _ in range(getenv("FUZZ_GRAPH_SPLIT_RUNS", 64)): - max_split_points = len(jis) // 3 - split_points = random.randint(0, min(max_split_points, getenv("FUZZ_GRAPH_MAX_SPLITS", 8))) - split = [0] - for i in range(split_points - 1): - split.append(random.randint(split[-1] + 2, len(jis) - 2 * (max_split_points - i))) - split.append(len(jis)) - - graphed_jit = [] - for sp in range(len(split)-1): - graphed_jit += apply_graph_to_jit(jis[split[sp]:split[sp+1]], [], {}) - - for _ in range(getenv("FUZZ_GRAPH_SPLIT_RETRY_RUNS", 4)): - test_bufs = run_jit(graphed_jit, input_buffers, all_buffers, {}) - test_bufs_np = [np.frombuffer(x, _to_np_dtype(all_buffers[i].dtype)) for i,x in enumerate(test_bufs)] - for i in range(len(ground_thruth_bufs)): np.testing.assert_equal(ground_truth_np[i], test_bufs_np[i]) - -if __name__ == "__main__": - SEED = getenv("SEED", 42) - random.seed(SEED) - np.random.seed(SEED) - - next_graph_id = 0 - for i in range(getenv("ITERS", 1000)): - print("Running graph", next_graph_id) - jis, all_buffers, input_buffers = gen_graph() - fuzz_graph(jis, all_buffers, input_buffers) - next_graph_id += 1 diff --git a/tinygrad/test/external/fuzz_kfd.py b/tinygrad/test/external/fuzz_kfd.py deleted file mode 100644 index 29c28683..00000000 --- a/tinygrad/test/external/fuzz_kfd.py +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env python3 -import random -from tqdm import trange -from typing import List -from tinygrad import Device -from tinygrad.runtime.ops_amd import AMDDevice, HWQueue - -if __name__ == "__main__": - dev: List[AMDDevice] = [Device[f"KFD:{i}"] for i in range(6)] - print(f"got {len(dev)} devices") - - buffers = [(rd:=random.choice(dev), rd.allocator.alloc(random.randint(1, 10000))) for i in range(100)] - - for _ in trange(100000): - d1, b1 = random.choice(buffers) - d2, b2 = random.choice(buffers) - d1._gpu_map(b2) - q = HWQueue() - q.signal(sig:=AMDDevice._alloc_signal(10)) - qc = HWQueue() - qc.wait(sig) - qc.copy(b1.va_addr, b2.va_addr, min(b1.size, b2.size)) - d1.completion_signal.value = 1 - qc.signal(d1.completion_signal) - qc.submit(d1) - q.wait(d1.completion_signal) - q.submit(d1) - AMDDevice._wait_on(d1.completion_signal.event_id) diff --git a/tinygrad/test/external/fuzz_linearizer.py b/tinygrad/test/external/fuzz_linearizer.py deleted file mode 100644 index 1bf269ce..00000000 --- a/tinygrad/test/external/fuzz_linearizer.py +++ /dev/null @@ -1,338 +0,0 @@ -import random, traceback, ctypes, argparse, os -from typing import Any -import numpy as np -from collections import defaultdict -from extra.optimization.helpers import load_worlds, ast_str_to_lin, kern_str_to_lin - -# We need to insert ioctl before opening devices. -if os.getenv("VALIDATE_HCQ", 0) != 0: - try: - import extra.nv_gpu_driver.nv_ioctl - from tinygrad import Device - _, _ = Device["NV"], Device["CUDA"] - except Exception: pass - - try: - import extra.qcom_gpu_driver.opencl_ioctl - from tinygrad import Device - _, _ = Device["QCOM"], Device["GPU"] - except Exception: pass - -from tinygrad import Tensor, Device, dtypes -from tinygrad.tensor import _to_np_dtype -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.kernel import Opt, OptOps -from tinygrad.engine.search import get_kernel_actions, bufs_from_lin -from tinygrad.engine.realize import CompiledRunner -from tinygrad.helpers import getenv, from_mv, prod, colored, Context, DEBUG, Timing -from tinygrad.uop.ops import UOp, Ops -from tinygrad.device import is_dtype_supported - -def on_linearizer_will_run(): pass -def on_linearizer_did_run(): pass -def compare_states(x, y): return (True, "") - -if getenv("VALIDATE_HCQ"): - if Device.DEFAULT == "NV": - print("VALIDATE_HCQ: Comparing NV to CUDA") - import extra.nv_gpu_driver.nv_ioctl - validate_device = Device["CUDA"] - on_linearizer_will_run = extra.nv_gpu_driver.nv_ioctl.before_launch - on_linearizer_did_run = extra.nv_gpu_driver.nv_ioctl.collect_last_launch_state - compare_states = extra.nv_gpu_driver.nv_ioctl.compare_launch_state - elif Device.DEFAULT == "QCOM": - print("VALIDATE_HCQ: Comparing QCOM to GPU") - import extra.qcom_gpu_driver.opencl_ioctl - validate_device = Device["GPU"] - on_linearizer_will_run = extra.qcom_gpu_driver.opencl_ioctl.before_launch - on_linearizer_did_run = extra.qcom_gpu_driver.opencl_ioctl.collect_last_launch_state - compare_states = extra.qcom_gpu_driver.opencl_ioctl.compare_launch_state - else: - print(colored("VALIDATE_HCQ options is ignored", 'red')) - -def tuplize_uops(uops:list[UOp]) -> tuple: - return tuple([(x.op, x.dtype, tuple(uops.index(x) for x in x.src), x.arg) for x in uops]) - -def get_fuzz_rawbufs(lin): - rawbufs = bufs_from_lin(lin) - - # Reallocate output buffer with additional area to detect out-of-bounds writes. - RED_AREA_SIZE = 1024 - # setting output # TODO: multi-output kernel - rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True, size=rawbufs[0].size+RED_AREA_SIZE) - # setting inputs - with Context(DEBUG=0): - for rawbuf in rawbufs[1:]: - if dtypes.is_unsigned(rawbuf.dtype): - data = np.random.randint(0, 100, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) - elif dtypes.is_int(rawbuf.dtype): - data = np.random.randint(-100, 100, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) - elif rawbuf.dtype == dtypes.bool: - data = np.random.choice([True, False], size=rawbuf.size) - elif rawbuf.dtype == dtypes.half: - data = np.random.uniform(-1, 1, size=rawbuf.size).astype(dtype=_to_np_dtype(rawbuf.dtype)) - else: - data = np.random.uniform(-10, 10, size=rawbuf.size).astype(dtype=_to_np_dtype(rawbuf.dtype)) - rawbuf.copyin(Tensor(data, device=lin.opts.device).realize().uop.base.realized.as_buffer()) - return rawbufs - -def get_fuzz_rawbuf_like(old_rawbuf, zero=False, copy=False, size=None, force_device=None): - rawbuf = type(old_rawbuf)(force_device or old_rawbuf.device, old_rawbuf.size if size is None else size, old_rawbuf.dtype).allocate() - if copy: - with Context(DEBUG=0): rawbuf.copyin(old_rawbuf.as_buffer()) - elif zero: - with Context(DEBUG=0): - mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) - ctypes.memset(from_mv(mv), 0, len(mv)) - rawbuf.copyin(mv) - return rawbuf - -def run_linearizer(lin: Kernel, rawbufs=None, var_vals=None) -> tuple[str, Any]: # (error msg, run state) - if rawbufs is None: rawbufs = bufs_from_lin(lin) - if var_vals is None: var_vals = {v: v.min for v in lin.vars} - - # TODO: images needs required_optimization - try: - prg = CompiledRunner(lin.to_program()) - except KeyboardInterrupt: raise - except Exception: - traceback.print_exc() - return "COMPILE_ERROR", None - - if getenv("VALIDATE_HCQ"): on_linearizer_will_run() - try: - prg(rawbufs, var_vals, wait=True) - except KeyboardInterrupt: raise - except Exception: - traceback.print_exc() - return "EXEC_ERROR", None - - if getenv("VALIDATE_HCQ"): run_state = on_linearizer_did_run() - else: run_state = None - - return "PASS", run_state - -def compare_linearizer(lin: Kernel, rawbufs=None, var_vals=None, ground_truth=None, rtol=1e-2, atol=1e-2): - # TODO: for bfloat16 it compiles linearizer, but it does not run because numpy cannot generate bf16 buffer. - has_bf16 = any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) - - # TODO: raise specific fuzzing errors instead of str, and propagate the error message - try: - if rawbufs is None: - rawbufs = get_fuzz_rawbufs(lin) - else: - rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True) # get a new output buffer - except KeyboardInterrupt: raise - except BaseException: - return ("RAWBUFS_ERROR", rawbufs, var_vals, ground_truth, None) - - if var_vals is None: - # TODO: handle symbolic max case - var_vals = {v: random.randint(v.vmin, v.vmax) for v in lin.ast.variables()} - - if ground_truth is None and not has_bf16: - unoptimized = Kernel(lin.ast) - if run_linearizer(unoptimized, rawbufs, var_vals)[0] != "PASS": - return ("BASELINE_ERROR", rawbufs, var_vals, ground_truth, None) - ground_truth = np.frombuffer(rawbufs[0].as_buffer(), _to_np_dtype(rawbufs[0].dtype)).copy() - - rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True) # get a new output buffer - run_msg, run_state = run_linearizer(lin, rawbufs, var_vals) - if run_msg != "PASS": return (run_msg, rawbufs, var_vals, ground_truth, run_state) - - try: - if not has_bf16: - result = np.frombuffer(rawbufs[0].as_buffer(), _to_np_dtype(rawbufs[0].dtype)) - np.testing.assert_allclose(result, ground_truth, rtol=rtol, atol=atol) - except KeyboardInterrupt: raise - except AssertionError as e: - if DEBUG >= 2: - print(f"COMPARE_ERROR details: {e}") - if getenv("DEBUG_VALUES") > 0: - mismatch_indices = np.where(~np.isclose(result, ground_truth, rtol=rtol, atol=atol)) - mismatched_result = result[mismatch_indices] - mismatched_ground_truth = ground_truth[mismatch_indices] - for i, idx in enumerate(mismatch_indices[0]): - print(f"mismatch at {idx=}: result={mismatched_result[i]} <> ground_truth={mismatched_ground_truth[i]}") - return ("COMPARE_ERROR", rawbufs, var_vals, ground_truth, run_state) - - return ("PASS", rawbufs, var_vals, ground_truth, run_state) - -def fuzz_linearizer(lin: Kernel, rtol=1e-2, atol=1e-2, opts_list=None): - SEED = getenv("SEED", 42) - random.seed(SEED) - np.random.seed(SEED) - print(lin.ast) - print(lin.colored_shape()) - seen_uops = {} - last_lins = [lin] - failures:defaultdict[str, list[tuple[tuple[UOp, ...], list[Opt]]]] = defaultdict(list) - rawbufs, var_vals, ground_truth, validate_rawbufs = None, None, None, None - - FUZZ_ALL_ACTIONS = getenv("FUZZ_ALL_ACTIONS", 0) - FUZZ_MAX_SIZE = getenv("FUZZ_MAX_SIZE", 0) - FUZZ_IGNORE_SIMPLE_OPS = getenv("FUZZ_IGNORE_SIMPLE_OPS", 1) - - if FUZZ_MAX_SIZE > 0 and prod(lin.full_shape) > FUZZ_MAX_SIZE: - print("skipping large kernel") - return failures - if FUZZ_IGNORE_SIMPLE_OPS and _is_simple(lin): - print("skipping simple kernel") - return failures - - test_depth = 1 if opts_list is not None else getenv("DEPTH", 1 if FUZZ_ALL_ACTIONS else 10) - for depth in range(test_depth): - next_lins = [] - for lin in last_lins: - if opts_list is None: actions = get_kernel_actions(lin, include_0=False) - else: - actions = {} - for oi,opts in enumerate(opts_list): - lin2 = lin.copy() - for o in opts: lin2.apply_opt(o) - actions[oi] = lin2 - - if not actions: continue - if depth == 0 and getenv("FUZZ_REQUIRE_TC", 0): - tc_acts = {i: k for k in actions.values() if k.applied_opts[0].op == OptOps.TC} - if len(tc_acts) == 0: return failures - else: actions = tc_acts - - test_lins = list(actions.values()) - if FUZZ_ALL_ACTIONS: print(f"testing {lin.applied_opts=} with {len(actions)} actions") - elif opts_list is None: test_lins = [random.choice(test_lins)] - - for test_lin in test_lins: - if not FUZZ_ALL_ACTIONS and test_lin.applied_opts: print(f"applied opts: {test_lin.applied_opts}") - - # stop if kernel uops repeat - try: tuops = tuplize_uops(test_lin.linearize().uops) - except KeyboardInterrupt: raise - except BaseException as e: - print(test_lin.ast) - print(test_lin.applied_opts) - print(e) - failures["LINEARIZE_ERROR"].append((test_lin.ast, test_lin.applied_opts)) - continue - - if tuops in seen_uops: continue - seen_uops[tuops] = tuple(test_lin.applied_opts) - - if not FUZZ_ALL_ACTIONS: print(test_lin.colored_shape()) - - (msg, rawbufs, var_vals, ground_truth, state1) = compare_linearizer(test_lin, rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) - if state1 is not None and validate_device is not None: - validate_lin = test_lin.copy() - validate_lin.opts = validate_device.renderer - if validate_rawbufs is None: - validate_rawbufs = [get_fuzz_rawbuf_like(x, copy=True, force_device=validate_device.device) for x in rawbufs] - (_msg, _, _, _, state2) = compare_linearizer(validate_lin, validate_rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) - - if _msg != "PASS": failures[f"VALIDATE_DEV_{_msg}"].append((validate_lin.ast, validate_lin.applied_opts)) - - ok, err_msg = compare_states(state1, state2) - if not ok: failures["HCQ_COMPARE_FAILURE"].append((err_msg, test_lin.ast, test_lin.applied_opts, state1, state2)) - - if msg != "PASS": - print(test_lin.ast) - print(test_lin.applied_opts) - print(msg) - failures[msg].append((test_lin.ast, test_lin.applied_opts)) - continue - - next_lins.append(test_lin) - - last_lins = next_lins - if FUZZ_ALL_ACTIONS: print(f"depth={depth} total_lins={len(last_lins)} {failures=}") - return failures - -def _is_simple(lin: Kernel) -> bool: - if len(lin.ast.src) > 1: return False - ast:UOp = lin.ast.src[0] - if ast.src[0].op is Ops.CAST and ast.src[0].src[0].op is Ops.LOAD: return True - return False - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Run a fuzz testing on one or more kernels", formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--ast", type=str, default=None, help="the ast for the kernel to be optimized") - parser.add_argument("--file", type=str, default=None, help="a file containing asts to be optimized, one per line") - parser.add_argument("--beamreplay", type=str, default=None, help="replay asts and opts got from beam with CAPTURE_BEAM") - parser.add_argument("--logfile", type=str, default=None, help="a file containing a tuple of ast and applied_opts, one per line") - parser.add_argument("--expected-failures", type=int, default=0, help="the number of expected failed kernels") - parser.add_argument("--rtol", type=float, default=1e-2, help="relative tolerance for numerical comparison") - parser.add_argument("--atol", type=float, default=1e-2, help="absolute tolerance for numerical comparison") - args = parser.parse_args() - - opts_list = None - if args.ast is not None: - print("loaded AST from CLI") - ast_strs = [args.ast] - elif args.file is not None: - print(f"loading ASTs from file '{args.file}'") - with open(args.file, 'r') as file: - ast_strs = file.readlines() - elif args.beamreplay is not None: - print(f"loading BEAM replay from file '{args.beamreplay}'") - with open(args.beamreplay, 'r') as file: fdata = file.readlines() - ast_strs, opts_list = [x.split(' :: ')[0] for x in fdata if not x.startswith("#")], [x.split(' :: ')[1] for x in fdata if not x.startswith("#")] - - # dedup ast_strs and opts_list - dct = defaultdict(list) - for i in range(len(ast_strs)): dct[ast_strs[i]].append(eval(opts_list[i])) - ast_strs_items = list(dct.keys()) - opts_list = [dct[c] for c in ast_strs_items] - elif args.logfile is not None: - print(f"loading ASTs from LOGKERNS file '{args.file}'") - with open(args.logfile, 'r') as file: - kern_strs = file.readlines() - test_lins = [kern_str_to_lin(kern_str) for kern_str in kern_strs] - ast_strs = [f"{lin.ast}" for lin in test_lins] - else: - print("loading ASTs from world") - ast_strs = load_worlds(filter_reduce=False, filter_novariable=False) - - print(f"{len(ast_strs)=}") - tested = 0 - failed_ids = [] - failures = defaultdict(list) - seen_ast_strs = set() - - try: - for i, ast in enumerate(ast_strs[:getenv("FUZZ_N", len(ast_strs))]): - if (nth := getenv("FUZZ_NTH", -1)) != -1 and i != nth: continue - if getenv("FUZZ_IMAGEONLY") and "dtypes.image" not in ast: continue - if "dtypes.image" in ast and Device.DEFAULT not in {"GPU", "QCOM"}: continue # IMAGE is only for GPU - if ast in seen_ast_strs: continue - seen_ast_strs.add(ast) - - lin = ast_str_to_lin(ast) - if not all(is_dtype_supported(buf.dtype) for buf in lin.bufs): - print("skipping kernel due to not supported dtype") - continue - - with Timing(f"tested ast {i}: "): - tested += 1 - fuzz_failures = fuzz_linearizer(lin, rtol=args.rtol, atol=args.atol, opts_list=(opts_list[i] if opts_list else None)) - if fuzz_failures: failed_ids.append(i) - for k, v in fuzz_failures.items(): - for f in v: - failures[k].append(f) - except KeyboardInterrupt: print(colored("STOPPING...", 'red')) - - for msg, errors in failures.items(): - for i, payload in enumerate(errors): - print(f"{msg} {i} kernel: {payload}") # easier to use with output with verify_kernel.py - - print(f"{tested=}") - if failures: - print(f"{failed_ids=}") - for msg, errors in failures.items(): - print(f"{msg}: {len(errors)}") - if len(failed_ids) == args.expected_failures: - print(colored(f"{len(failed_ids)} failed as expected", "yellow")) - if len(failed_ids) != args.expected_failures: - print(colored(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}", "red")) - # TODO: fix this - # raise RuntimeError(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}") - else: - print(colored("all passed", "green")) diff --git a/tinygrad/test/external/fuzz_shape_ops.py b/tinygrad/test/external/fuzz_shape_ops.py deleted file mode 100644 index f60e58e9..00000000 --- a/tinygrad/test/external/fuzz_shape_ops.py +++ /dev/null @@ -1,87 +0,0 @@ -from __future__ import annotations -import unittest -from math import prod - -from hypothesis import assume, given, settings, strategies as st -from hypothesis.extra import numpy as stn - -import numpy as np -import torch -from tinygrad import Tensor -from tinygrad.helpers import CI, getenv - - -settings.register_profile(__file__, settings.default, - max_examples=100 if CI else 250, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) - - -# torch wraparound for large numbers -st_int32 = st.integers(-2147483648, 2147483647) - -@st.composite -def st_shape(draw) -> tuple[int, ...]: - s = draw(stn.array_shapes(min_dims=0, max_dims=6, - min_side=0, max_side=128)) - assume(prod(s) <= 1024 ** 2) - assume(prod([d for d in s if d]) <= 1024 ** 4) - return s - -def tensors_for_shape(s:tuple[int, ...]) -> tuple[torch.tensor, Tensor]: - x = np.arange(prod(s)).reshape(s) - return torch.from_numpy(x), Tensor(x) - -def apply(tor, ten, tor_fn, ten_fn=None): - ok = True - try: tor = tor_fn(tor) - except: tor, ok = None, not ok # noqa: E722 - try: ten = ten_fn(ten) if ten_fn is not None else tor_fn(ten) - except: ten, ok = None, not ok # noqa: E722 - return tor, ten, ok - -class TestShapeOps(unittest.TestCase): - @settings.get_profile(__file__) - @given(st_shape(), st_int32, st.one_of(st_int32, st.lists(st_int32))) - def test_split(self, s:tuple[int, ...], dim:int, sizes:int|list[int]): - tor, ten = tensors_for_shape(s) - tor, ten, ok = apply(tor, ten, lambda t: t.split(sizes, dim)) - assert ok - if tor is None and ten is None: return - - assert len(tor) == len(ten) - assert all([np.array_equal(tor.numpy(), ten.numpy()) for (tor, ten) in zip(tor, ten)]) - - @settings.get_profile(__file__) - @given(st_shape(), st_int32, st_int32) - def test_chunk(self, s:tuple[int, ...], dim:int, num:int): - # chunking on a 0 dim is cloning and leads to OOM if done unbounded. - assume((0 <= (actual_dim := len(s)-dim if dim < 0 else dim) < len(s) and s[actual_dim] > 0) or - (num < 16)) - - tor, ten = tensors_for_shape(s) - tor, ten, ok = apply(tor, ten, lambda t: t.chunk(num, dim)) - assert ok - if tor is None and ten is None: return - - assert len(tor) == len(ten) - assert all([np.array_equal(tor.numpy(), ten.numpy()) for (tor, ten) in zip(tor, ten)]) - - @settings.get_profile(__file__) - @given(st_shape(), st_int32) - def test_squeeze(self, s:tuple[int, ...], dim:int): - tor, ten = tensors_for_shape(s) - tor, ten, ok = apply(tor, ten, lambda t: t.squeeze(dim)) - assert ok - if tor is None and ten is None: return - assert np.array_equal(tor.numpy(), ten.numpy()) - - @settings.get_profile(__file__) - @given(st_shape(), st_int32) - def test_unsqueeze(self, s:tuple[int, ...], dim:int): - tor, ten = tensors_for_shape(s) - tor, ten, ok = apply(tor, ten, lambda t: t.unsqueeze(dim)) - assert ok - if tor is None and ten is None: return - assert np.array_equal(tor.numpy(), ten.numpy()) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/fuzz_shapetracker.py b/tinygrad/test/external/fuzz_shapetracker.py deleted file mode 100644 index ba11fa1e..00000000 --- a/tinygrad/test/external/fuzz_shapetracker.py +++ /dev/null @@ -1,61 +0,0 @@ -import random -from tinygrad.helpers import DEBUG, getenv -from test.unit.test_shapetracker import CheckingShapeTracker - -def do_permute(st): - perm = list(range(0, len(st.shape))) - random.shuffle(perm) - perm = tuple(perm) - if DEBUG >= 1: print("st.permute(", perm, ")") - st.permute(perm) - -def do_pad(st): - c = random.randint(0, len(st.shape)-1) - pad = tuple((random.randint(0,2), random.randint(0,2)) if i==c else (0,0) for i in range(len(st.shape))) - if DEBUG >= 1: print("st.pad(", pad, ")") - st.pad(pad) - -def do_reshape_split_one(st): - c = random.randint(0, len(st.shape)-1) - poss = [n for n in [1,2,3,4,5] if st.shape[c]%n == 0] - spl = random.choice(poss) - shp = st.shape[0:c] + (st.shape[c]//spl, spl) + st.shape[c+1:] - if DEBUG >= 1: print("st.reshape(", shp, ")") - st.reshape(shp) - -def do_reshape_combine_two(st): - if len(st.shape) < 2: return - c = random.randint(0, len(st.shape)-2) - shp = st.shape[:c] + (st.shape[c] * st.shape[c+1], ) + st.shape[c+2:] - if DEBUG >= 1: print("st.reshape(", shp, ")") - st.reshape(shp) - -def do_shrink(st): - c = random.randint(0, len(st.shape)-1) - while 1: - shrink = tuple((random.randint(0,s), random.randint(0,s)) if i == c else (0,s) for i,s in enumerate(st.shape)) - if all(x= 1: print("st.shrink(", shrink, ")") - st.shrink(shrink) - -def do_flip(st): - flip = tuple(random.random() < 0.5 for _ in st.shape) - if DEBUG >= 1: print("st.flip(", flip, ")") - st.flip(flip) - -def do_expand(st): - c = [i for i,s in enumerate(st.shape) if s==1] - if len(c) == 0: return - c = random.choice(c) - expand = tuple(random.choice([2,3,4]) if i==c else s for i,s in enumerate(st.shape)) - if DEBUG >= 1: print("st.expand(", expand, ")") - st.expand(expand) - -shapetracker_ops = [do_permute, do_pad, do_shrink, do_reshape_split_one, do_reshape_combine_two, do_flip, do_expand] - -if __name__ == "__main__": - random.seed(42) - for _ in range(getenv("CNT", 200)): - st = CheckingShapeTracker((random.randint(2, 10), random.randint(2, 10), random.randint(2, 10))) - for i in range(8): random.choice(shapetracker_ops)(st) - st.assert_same() diff --git a/tinygrad/test/external/fuzz_shapetracker_math.py b/tinygrad/test/external/fuzz_shapetracker_math.py deleted file mode 100644 index c7364ae3..00000000 --- a/tinygrad/test/external/fuzz_shapetracker_math.py +++ /dev/null @@ -1,46 +0,0 @@ -import random -from tinygrad.helpers import getenv, DEBUG, colored, trange -from tinygrad.shape.shapetracker import ShapeTracker -from test.external.fuzz_shapetracker import shapetracker_ops -from test.external.fuzz_shapetracker import do_permute, do_reshape_split_one, do_reshape_combine_two, do_flip, do_pad -from test.unit.test_shapetracker_math import st_equal, MultiShapeTracker - -def fuzz_plus() -> tuple[ShapeTracker, ShapeTracker]: - m = MultiShapeTracker([ShapeTracker.from_shape((random.randint(1, 10), random.randint(1, 10), random.randint(1, 10)))]) - for _ in range(4): random.choice(shapetracker_ops)(m) - backup = m.sts[0] - m.sts.append(ShapeTracker.from_shape(m.sts[0].shape)) - for _ in range(4): random.choice(shapetracker_ops)(m) - st_sum = backup + m.sts[1] - return m.sts[0], st_sum - -# shrink and expand aren't invertible, and stride is only invertible in the flip case -invertible_shapetracker_ops = [do_permute, do_reshape_split_one, do_reshape_combine_two, do_flip, do_pad] - -def fuzz_invert() -> tuple[ShapeTracker, ShapeTracker]: - start = ShapeTracker.from_shape((random.randint(1, 10), random.randint(1, 10), random.randint(1, 10))) - m = MultiShapeTracker([start]) - for _ in range(8): random.choice(invertible_shapetracker_ops)(m) - inv = m.sts[0].invert(start.shape) - st_sum = (m.sts[0] + inv) if inv else None - return start, st_sum - -if __name__ == "__main__": - if seed:=getenv("SEED"): random.seed(seed) - total = getenv("CNT", 1000) - for fuzz in [globals()[f'fuzz_{x}'] for x in getenv("FUZZ", "invert,plus").split(",")]: - same_but_neq = 0 - for _ in trange(total, desc=f"{fuzz}"): - st1, st2 = fuzz() - eq = st_equal(st1, st2) - if getenv("CHECK_NEQ") and eq and st1.simplify() != st2.simplify(): - print(colored("same but unequal", "yellow")) - print(st1.simplify()) - print(st2.simplify()) - same_but_neq += 1 - if DEBUG >= 1: - print(f"EXP: {st1}") - print(f"GOT: {st2}") - print(colored("****", "green" if eq else "red")) - if not eq: exit(0) - if getenv("CHECK_NEQ"): print(f"same but unequal {same_but_neq}/{total} = {(same_but_neq/total)*100:.2f}%") diff --git a/tinygrad/test/external/fuzz_shapetracker_size.py b/tinygrad/test/external/fuzz_shapetracker_size.py deleted file mode 100644 index dc76f3ae..00000000 --- a/tinygrad/test/external/fuzz_shapetracker_size.py +++ /dev/null @@ -1,13 +0,0 @@ -from tinygrad.shape.shapetracker import ShapeTracker -from test.external.fuzz_shapetracker import shapetracker_ops as st_ops -from test.unit.test_shapetracker_math import MultiShapeTracker -from tinygrad.helpers import getenv -import random - -random.seed(getenv("SEED", 42)) -for i in range(getenv("CNT", 2000)): - if getenv("DEBUG", 0) >= 1: print() - N = random.randint(1, 10000) - mst = MultiShapeTracker([ShapeTracker.from_shape((N,))]) # st_ops don't mutate regular shapetrackers for some reason - for j in range(20): random.choice(st_ops)(mst) - assert mst.sts[0].real_size() <= N, f"{N=}, real_size={mst.sts[0].real_size()}, st={mst.sts[0]}" diff --git a/tinygrad/test/external/fuzz_symbolic.py b/tinygrad/test/external/fuzz_symbolic.py deleted file mode 100644 index 41970a93..00000000 --- a/tinygrad/test/external/fuzz_symbolic.py +++ /dev/null @@ -1,92 +0,0 @@ -import random, operator -import z3 -from tinygrad import Variable, dtypes -from tinygrad.uop.ops import UOp, graph_rewrite -from tinygrad.uop.spec import z3_renderer -from tinygrad.helpers import DEBUG, Context - -seed = random.randint(0, 100) -print(f"Seed: {seed}") -random.seed(seed) - -unary_ops = [lambda a:a+random.randint(-4, 4), lambda a: a*random.randint(-4, 4), - lambda a: a//random.randint(1, 9), lambda a: a%random.randint(1, 9), - lambda a:a.maximum(random.randint(-10, 10)), lambda a:a.minimum(random.randint(-10, 10))] -binary_ops = [lambda a,b: a+b, lambda a,b: a*b, lambda a,b:a.maximum(b), lambda a,b:a.minimum(b)] -comp_ops = [operator.lt, operator.le, operator.gt, operator.ge] - -def random_or_sub_expression_int(depth, expr): - sub_expr = random.choice([e for e in expr.toposort() if e.dtype is not dtypes.bool]) - return random.choice([random_int_expr(depth-1), sub_expr]) - -def random_int_expr(depth=10): - if depth <= 0: return random.choice(v) - expr1 = random_int_expr(depth-1) - - # we give more weight to arithmatic ops than to minimum and maximum - ops = [ - lambda: random.choices(unary_ops, weights=[4, 4, 4, 4, 1, 1])[0](expr1), - # for the second operand its either another random exprssion or some subexpression of the first operand - lambda: random.choices(binary_ops, [8, 1, 1, 1])[0](expr1, random_or_sub_expression_int(depth-1, expr1)), - lambda: random_bool_expr(3, random_or_sub_expression_int(depth-1, expr1)).where(expr1, random_or_sub_expression_int(depth-1, expr1)), - ] - # we give weight proportional to the amount of ops in each branch - return random.choices(ops, weights=[6, 4, 1])[0]() - -def random_bool_expr(depth=10, expr1=None): - if depth == 0: return True - if expr1 is None: expr1 = random_int_expr(depth-1) - expr2 = random.choice([random_or_sub_expression_int(depth-1, expr1), UOp.const(dtypes.int, random.randint(-10, 10))]) - return random.choice(comp_ops)(expr1, expr2) - - -if __name__ == "__main__": - skipped = 0 - for i in range(10000): - if i % 1000 == 0: - print(f"Running test {i}") - upper_bounds = [*list(range(1, 10)), 16, 32, 64, 128, 256] - u1 = Variable("v1", 0, random.choice(upper_bounds)) - u2 = Variable("v2", 0, random.choice(upper_bounds)) - u3 = Variable("v3", 0, random.choice(upper_bounds)) - v = [u1,u2,u3] - expr = random_int_expr(6) - - with Context(CORRECT_DIVMOD_FOLDING=1): - simplified_expr = expr.simplify() - - solver = z3.Solver() - solver.set(timeout=5000) # some expressions take very long verify, but its very unlikely they actually return sat - z3_sink = graph_rewrite(expr.sink(simplified_expr, u1, u2, u3), z3_renderer, ctx=(solver, {})) - z3_expr, z3_simplified_expr = z3_sink.src[0].arg, z3_sink.src[1].arg - check = solver.check(z3_simplified_expr != z3_expr) - if check == z3.unknown and DEBUG>=1: - skipped += 1 - print("Skipped due to timeout or interrupt:\n" + - f"v1=Variable(\"{u1.arg[0]}\", {u1.arg[1]}, {u1.arg[2]})\n" + - f"v2=Variable(\"{u2.arg[0]}\", {u2.arg[1]}, {u2.arg[2]})\n" + - f"v3=Variable(\"{u3.arg[0]}\", {u3.arg[1]}, {u3.arg[2]})\n" + - f"expr = {expr.render(simplify=False)}\n") - elif check == z3.sat: - m = solver.model() - v1, v2, v3 = z3_sink.src[2].arg, z3_sink.src[3].arg, z3_sink.src[4].arg - n1, n2, n3 = m[v1], m[v2], m[v3] - u1_val, u2_val, u3_val = u1.const_like(n1.as_long()), u2.const_like(n2.as_long()), u3.const_like(n3.as_long()) - with Context(CORRECT_DIVMOD_FOLDING=1): - num = expr.simplify().substitute({u1:u1_val, u2:u2_val, u3:u3_val}).ssimplify() - rn = expr.substitute({u1:u1_val, u2:u2_val, u3:u3_val}).ssimplify() - if num==rn: print("z3 found a mismatch but the expressions are equal!!") - assert False, f"mismatched {expr.render()} at v1={m[v1]}; v2={m[v2]}; v3={m[v3]} = {num} != {rn}\n" +\ - "Reproduce with:\n" +\ - f"v1=Variable(\"{u1.arg[0]}\", {u1.arg[1]}, {u1.arg[2]})\n" +\ - f"v2=Variable(\"{u2.arg[0]}\", {u2.arg[1]}, {u2.arg[2]})\n" +\ - f"v3=Variable(\"{u3.arg[0]}\", {u3.arg[1]}, {u3.arg[2]})\n" +\ - f"expr = {expr}\n" +\ - f"v1_val, v2_val, v3_val = UOp.const(dtypes.int, {n1.as_long()}), UOp.const(dtypes.int, {n2.as_long()})," +\ - f"UOp.const(dtypes.int, {n3.as_long()})\n" +\ - "num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify()\n" +\ - "rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify()\n" +\ - "assert num==rn, f\"{num} != {rn}\"\n" - - if DEBUG >= 2: print(f"validated {expr.render()}") - print(f"Skipped {skipped} expressions due to timeout") diff --git a/tinygrad/test/external/graph_batchnorm.py b/tinygrad/test/external/graph_batchnorm.py deleted file mode 100644 index 59e3b796..00000000 --- a/tinygrad/test/external/graph_batchnorm.py +++ /dev/null @@ -1,61 +0,0 @@ -import unittest -from tinygrad.nn.state import get_parameters -from tinygrad.tensor import Tensor -from tinygrad.nn import Conv2d, BatchNorm2d, optim - -def model_step(lm): - with Tensor.train(): - x = Tensor.ones(8,12,128,256, requires_grad=False) - optimizer = optim.SGD(get_parameters(lm), lr=0.001) - loss = lm.forward(x).sum() - optimizer.zero_grad() - loss.backward() - del x,loss - optimizer.step() - -class TestBatchnorm(unittest.TestCase): - def test_conv(self): - class LilModel: - def __init__(self): - self.c = Conv2d(12, 32, 3, padding=1, bias=False) - def forward(self, x): - return self.c(x).relu() - lm = LilModel() - model_step(lm) - - def test_two_conv(self): - class LilModel: - def __init__(self): - self.c = Conv2d(12, 32, 3, padding=1, bias=False) - self.c2 = Conv2d(32, 32, 3, padding=1, bias=False) - def forward(self, x): - return self.c2(self.c(x)).relu() - lm = LilModel() - model_step(lm) - - def test_two_conv_bn(self): - class LilModel: - def __init__(self): - self.c = Conv2d(12, 24, 3, padding=1, bias=False) - self.bn = BatchNorm2d(24, track_running_stats=False) - self.c2 = Conv2d(24, 32, 3, padding=1, bias=False) - self.bn2 = BatchNorm2d(32, track_running_stats=False) - def forward(self, x): - x = self.bn(self.c(x)).relu() - return self.bn2(self.c2(x)).relu() - lm = LilModel() - model_step(lm) - - def test_conv_bn(self): - class LilModel: - def __init__(self): - self.c = Conv2d(12, 32, 3, padding=1, bias=False) - self.bn = BatchNorm2d(32, track_running_stats=False) - def forward(self, x): - return self.bn(self.c(x)).relu() - lm = LilModel() - model_step(lm) - - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/mlperf_bert/external_benchmark_bert.py b/tinygrad/test/external/mlperf_bert/external_benchmark_bert.py deleted file mode 100644 index b23abf5e..00000000 --- a/tinygrad/test/external/mlperf_bert/external_benchmark_bert.py +++ /dev/null @@ -1,102 +0,0 @@ -import unittest, time - -from tinygrad import Tensor, TinyJit, GlobalCounters, Device -from tinygrad.helpers import getenv, Context -from tinygrad.nn.optim import LAMB -from tinygrad.nn.state import get_parameters -from tinygrad.engine.realize import run_schedule - -from extra.models import bert - -bs = getenv("BS", 16) -seq_len = getenv("SEQ_LEN", 512) - -class BenchmarkBertTrain(unittest.TestCase): - def _get_layer(self, layer_id): - if not hasattr(self, "model"): - dropout_prob = 0.0 if getenv("DISABLE_DROPOUT") else 0.1 - self.model = bert.BertForPretraining(attention_probs_dropout_prob=dropout_prob, hidden_dropout_prob=dropout_prob) - hidden_size = self.model.bert.embeddings.word_embeddings.embed_sz - intermediate_size = self.model.bert.encoder.layer[0].intermediate.dense.weight.shape[0] - - layer_map = { - "embedding": self.model.bert.embeddings, - "attention_self": self.model.bert.encoder.layer[0].attention.self, - "attention_output": self.model.bert.encoder.layer[0].attention.output, - "intermediate": self.model.bert.encoder.layer[0].intermediate, - "output": self.model.bert.encoder.layer[0].output - } - input_shapes = { - "embedding": [(bs, seq_len), (bs, seq_len)], - "attention_self": [(bs, seq_len, hidden_size), (bs, 1, 1, seq_len)], - "attention_output": [(bs, seq_len, hidden_size), (bs, seq_len, 1)], - "intermediate": [(bs, seq_len, hidden_size)], - "output": [(bs, seq_len, intermediate_size), (bs, seq_len, 1)] - }.get(layer_id) - - return f"{layer_id}-layer, Input: {input_shapes}", layer_map.get(layer_id), input_shapes - - def _test_layer(self, name, layer, input_shapes): - optim = LAMB(get_parameters(layer)) - with Context(TRACK_MATCH_STATS=0): Tensor.realize(*[t.assign(t.detach().contiguous()) for t in get_parameters(optim)]) - - JITCNT = getenv("JITCNT", 1) - Tensor.training = True - @TinyJit - def step(inputs): - optim.zero_grad() - for i in inputs: i.grad = None - - y = layer(*inputs).contiguous().contiguous_backward() - y.sum().backward() - if getenv("ASSIGN", 1): sched, _ = Tensor.schedule_with_vars(y, *list(inputs), *optim.schedule_step()) - else: sched, _ = Tensor.schedule_with_vars(y, *list(inputs), *[t.grad for t in optim.params]) - - for _ in range(JITCNT): - run_schedule(sched) - - CNT = getenv("CNT", 5) - best_tm = None - flops, mem_used, mem, kernels = None, None, None, None - for _ in range(CNT): - with Context(TRACK_MATCH_STATS=0): inputs = [Tensor.randn(*shape, requires_grad=False).realize() for shape in input_shapes] - GlobalCounters.reset() - - st = time.perf_counter() - step(inputs) - Device[Device.DEFAULT].synchronize() - et = time.perf_counter() - - flops = GlobalCounters.global_ops / JITCNT - mem_used = GlobalCounters.mem_used - mem = GlobalCounters.global_mem / JITCNT - if kernels is None: kernels = GlobalCounters.kernel_count // JITCNT - tm = (et-st) / JITCNT - if best_tm is None or tm < best_tm: best_tm = tm - print(f"\r{name:70s}: {best_tm * 1000:>9.2f} ms, {flops / 10**12 / best_tm:>6.2f} TFLOPS, {mem / 10**9 / best_tm:>5.0f} GB/s, " - f"{mem_used / 10**9: 6.2f} GB used, {kernels:>5d} kernels") - return best_tm, flops, mem, kernels - - def test_embedding_layer(self): self._est(*self._test_layer(*self._get_layer("embedding")), 1) - def test_attention_self_layer(self): self._est(*self._test_layer(*self._get_layer("attention_self")), 24) # Assumes BERT-large - def test_attention_output_layer(self): self._est(*self._test_layer(*self._get_layer("attention_output")), 24) - def test_intermediate_layer(self): self._est(*self._test_layer(*self._get_layer("intermediate")), 24) - def test_output_layer(self): self._est(*self._test_layer(*self._get_layer("output")), 24) - - est_tm, est_flops, est_mem, est_kernels = 0, 0, 0, 0 - - @classmethod - def _est(cls, tm, flops, mem, kernels, mult): - cls.est_tm += tm * mult - cls.est_flops += flops * mult - cls.est_mem += mem * mult - cls.est_kernels += kernels * mult - - @classmethod - def tearDownClass(cls): - print(f"\restimated step tm: {cls.est_tm * 1000.0:.2f} ms, {cls.est_flops / 10 ** 12 / cls.est_tm:.3f} tflops, " - f"{cls.est_mem / 10 ** 9 / cls.est_tm:.2f} GB/s, {cls.est_kernels} kernels") - - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/external/mlperf_bert/external_test_checkpoint_loading.py b/tinygrad/test/external/mlperf_bert/external_test_checkpoint_loading.py deleted file mode 100644 index 5964d972..00000000 --- a/tinygrad/test/external/mlperf_bert/external_test_checkpoint_loading.py +++ /dev/null @@ -1,55 +0,0 @@ -# Test whether pretrained weights from first BERT pretraining phase have been loaded correctly -# Usage: -# 1. Download the BERT checkoints with `wikipedia_download.py` -# Command: BASEDIR=/path/to/wiki python3 wikipedia_download.py -# 2. Run this script. (Adjust EVAL_BS and GPUS as needed) -# Command: EVAL_BEAM=4 DEFAULT_FLOAT=half GPUS=6 BASEDIR=/path/to/wiki python3 test/external/mlperf_bert/external_test_checkpoint_loading.py -import os -from tqdm import tqdm - -from tinygrad.tensor import Tensor -from tinygrad.device import Device -from tinygrad.helpers import getenv -from tinygrad.nn.state import get_state_dict - -from examples.mlperf.helpers import get_mlperf_bert_model, get_data_bert -from examples.mlperf.dataloader import batch_load_val_bert -from examples.mlperf.model_train import eval_step_bert - -if __name__ == "__main__": - BASEDIR = os.environ["BASEDIR"] = getenv("BASEDIR", "/raid/datasets/wiki") - INIT_CKPT_DIR = getenv("INIT_CKPT_DIR", BASEDIR) - GPUS = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 1))] - EVAL_BS = getenv("EVAL_BS", 4 * len(GPUS)) - max_eval_steps = (10000 + EVAL_BS - 1) // EVAL_BS - - for i in range(10): - assert os.path.exists(os.path.join(BASEDIR, "eval", f"{i}.pkl")), \ - f"File {i}.pkl does not exist in {os.path.join(BASEDIR, 'eval')}" - - required_files = ["checkpoint", "model.ckpt-28252.data-00000-of-00001", "model.ckpt-28252.index", "model.ckpt-28252.meta"] - assert all(os.path.exists(os.path.join(INIT_CKPT_DIR, f)) for f in required_files), \ - f"Missing checkpoint files in INIT_CKPT_DIR: {required_files}" - - Tensor.training = False - - model = get_mlperf_bert_model(INIT_CKPT_DIR) - - for _, x in get_state_dict(model).items(): - x.realize().to_(GPUS) - - eval_accuracy = [] - eval_it = iter(batch_load_val_bert(EVAL_BS)) - - for _ in tqdm(range(max_eval_steps), desc="Evaluating", total=max_eval_steps): - eval_data = get_data_bert(GPUS, eval_it) - eval_result: dict[str, Tensor] = eval_step_bert(model, eval_data["input_ids"], eval_data["segment_ids"], eval_data["input_mask"], \ - eval_data["masked_lm_positions"], eval_data["masked_lm_ids"], \ - eval_data["masked_lm_weights"], eval_data["next_sentence_labels"]) - - mlm_accuracy = eval_result["masked_lm_accuracy"].numpy().item() - eval_accuracy.append(mlm_accuracy) - - total_lm_accuracy = sum(eval_accuracy) / len(eval_accuracy) - assert total_lm_accuracy >= 0.34, "Checkpoint loaded incorrectly. Accuracy should be very close to 0.34085 as per MLPerf BERT README." - print(f"Checkpoint loaded correctly. Accuracy of {total_lm_accuracy*100:.3f}% achieved. (Reference: 34.085%)") diff --git a/tinygrad/test/external/mlperf_bert/preprocessing/create_pretraining_data.py b/tinygrad/test/external/mlperf_bert/preprocessing/create_pretraining_data.py deleted file mode 100644 index 54041dfd..00000000 --- a/tinygrad/test/external/mlperf_bert/preprocessing/create_pretraining_data.py +++ /dev/null @@ -1,435 +0,0 @@ -# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/create_pretraining_data.py -# NOTE: This is a direct copy of the original script -# NOTE: With python 3.7.12, pip install tensorflow=1.15.5 -"""Create masked LM/next sentence masked_lm TF examples for BERT.""" - -from __future__ import absolute_import -from __future__ import division -from __future__ import print_function - -import os -os.environ['PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION'] = 'python' # NOTE: This is a workaround for protobuf issue - -import collections -import random -import tokenization -import tensorflow as tf - - -flags = tf.flags - -FLAGS = flags.FLAGS - -flags.DEFINE_string("input_file", None, - "Input raw text file (or comma-separated list of files).") - -flags.DEFINE_string( - "output_file", None, - "Output TF example file (or comma-separated list of files).") - -flags.DEFINE_string("vocab_file", None, - "The vocabulary file that the BERT model was trained on.") - -flags.DEFINE_bool( - "do_lower_case", True, - "Whether to lower case the input text. Should be True for uncased " - "models and False for cased models.") - -flags.DEFINE_integer("max_seq_length", 128, "Maximum sequence length.") - -flags.DEFINE_integer("max_predictions_per_seq", 20, - "Maximum number of masked LM predictions per sequence.") - -flags.DEFINE_integer("random_seed", 12345, "Random seed for data generation.") - -flags.DEFINE_integer( - "dupe_factor", 10, - "Number of times to duplicate the input data (with different masks).") - -flags.DEFINE_float("masked_lm_prob", 0.15, "Masked LM probability.") - -flags.DEFINE_float( - "short_seq_prob", 0.1, - "Probability of creating sequences which are shorter than the " - "maximum length.") - - -class TrainingInstance(object): - """A single training instance (sentence pair).""" - - def __init__(self, tokens, segment_ids, masked_lm_positions, masked_lm_labels, - is_random_next): - self.tokens = tokens - self.segment_ids = segment_ids - self.is_random_next = is_random_next - self.masked_lm_positions = masked_lm_positions - self.masked_lm_labels = masked_lm_labels - - def __str__(self): - s = "" - s += "tokens: %s\n" % (" ".join( - [tokenization.printable_text(x) for x in self.tokens])) - s += "segment_ids: %s\n" % (" ".join([str(x) for x in self.segment_ids])) - s += "is_random_next: %s\n" % self.is_random_next - s += "masked_lm_positions: %s\n" % (" ".join( - [str(x) for x in self.masked_lm_positions])) - s += "masked_lm_labels: %s\n" % (" ".join( - [tokenization.printable_text(x) for x in self.masked_lm_labels])) - s += "\n" - return s - - def __repr__(self): - return self.__str__() - - -def write_instance_to_example_files(instances, tokenizer, max_seq_length, - max_predictions_per_seq, output_files): - """Create TF example files from `TrainingInstance`s.""" - writers = [] - for output_file in output_files: - writers.append(tf.python_io.TFRecordWriter(output_file)) - - writer_index = 0 - - total_written = 0 - for (inst_index, instance) in enumerate(instances): - input_ids = tokenizer.convert_tokens_to_ids(instance.tokens) - input_mask = [1] * len(input_ids) - segment_ids = list(instance.segment_ids) - assert len(input_ids) <= max_seq_length - - while len(input_ids) < max_seq_length: - input_ids.append(0) - input_mask.append(0) - segment_ids.append(0) - - assert len(input_ids) == max_seq_length - assert len(input_mask) == max_seq_length - assert len(segment_ids) == max_seq_length - - masked_lm_positions = list(instance.masked_lm_positions) - masked_lm_ids = tokenizer.convert_tokens_to_ids(instance.masked_lm_labels) - masked_lm_weights = [1.0] * len(masked_lm_ids) - - while len(masked_lm_positions) < max_predictions_per_seq: - masked_lm_positions.append(0) - masked_lm_ids.append(0) - masked_lm_weights.append(0.0) - - next_sentence_label = 1 if instance.is_random_next else 0 - - features = collections.OrderedDict() - features["input_ids"] = create_int_feature(input_ids) - features["input_mask"] = create_int_feature(input_mask) - features["segment_ids"] = create_int_feature(segment_ids) - features["masked_lm_positions"] = create_int_feature(masked_lm_positions) - features["masked_lm_ids"] = create_int_feature(masked_lm_ids) - features["masked_lm_weights"] = create_float_feature(masked_lm_weights) - features["next_sentence_labels"] = create_int_feature([next_sentence_label]) - - tf_example = tf.train.Example(features=tf.train.Features(feature=features)) - - writers[writer_index].write(tf_example.SerializeToString()) - writer_index = (writer_index + 1) % len(writers) - - total_written += 1 - - if inst_index < 20: - tf.logging.info("*** Example ***") - tf.logging.info("tokens: %s" % " ".join( - [tokenization.printable_text(x) for x in instance.tokens])) - - for feature_name in features.keys(): - feature = features[feature_name] - values = [] - if feature.int64_list.value: - values = feature.int64_list.value - elif feature.float_list.value: - values = feature.float_list.value - tf.logging.info( - "%s: %s" % (feature_name, " ".join([str(x) for x in values]))) - - for writer in writers: - writer.close() - - tf.logging.info("Wrote %d total instances", total_written) - - -def create_int_feature(values): - feature = tf.train.Feature(int64_list=tf.train.Int64List(value=list(values))) - return feature - - -def create_float_feature(values): - feature = tf.train.Feature(float_list=tf.train.FloatList(value=list(values))) - return feature - - -def create_training_instances(input_files, tokenizer, max_seq_length, - dupe_factor, short_seq_prob, masked_lm_prob, - max_predictions_per_seq, rng): - """Create `TrainingInstance`s from raw text.""" - all_documents = [[]] - - # Input file format: - # (1) One sentence per line. These should ideally be actual sentences, not - # entire paragraphs or arbitrary spans of text. (Because we use the - # sentence boundaries for the "next sentence prediction" task). - # (2) Blank lines between documents. Document boundaries are needed so - # that the "next sentence prediction" task doesn't span between documents. - for input_file in input_files: - with tf.gfile.GFile(input_file, "r") as reader: - while True: - line = tokenization.convert_to_unicode(reader.readline()) - if not line: - break - line = line.strip() - - # Empty lines are used as document delimiters - if not line: - all_documents.append([]) - tokens = tokenizer.tokenize(line) - if tokens: - all_documents[-1].append(tokens) - - # Remove empty documents - all_documents = [x for x in all_documents if x] - rng.shuffle(all_documents) - - vocab_words = list(tokenizer.vocab.keys()) - instances = [] - for _ in range(dupe_factor): - for document_index in range(len(all_documents)): - instances.extend( - create_instances_from_document( - all_documents, document_index, max_seq_length, short_seq_prob, - masked_lm_prob, max_predictions_per_seq, vocab_words, rng)) - - rng.shuffle(instances) - return instances - - -def create_instances_from_document( - all_documents, document_index, max_seq_length, short_seq_prob, - masked_lm_prob, max_predictions_per_seq, vocab_words, rng): - """Creates `TrainingInstance`s for a single document.""" - document = all_documents[document_index] - - # Account for [CLS], [SEP], [SEP] - max_num_tokens = max_seq_length - 3 - - # We *usually* want to fill up the entire sequence since we are padding - # to `max_seq_length` anyways, so short sequences are generally wasted - # computation. However, we *sometimes* - # (i.e., short_seq_prob == 0.1 == 10% of the time) want to use shorter - # sequences to minimize the mismatch between pre-training and fine-tuning. - # The `target_seq_length` is just a rough target however, whereas - # `max_seq_length` is a hard limit. - target_seq_length = max_num_tokens - if rng.random() < short_seq_prob: - target_seq_length = rng.randint(2, max_num_tokens) - - # We DON'T just concatenate all of the tokens from a document into a long - # sequence and choose an arbitrary split point because this would make the - # next sentence prediction task too easy. Instead, we split the input into - # segments "A" and "B" based on the actual "sentences" provided by the user - # input. - instances = [] - current_chunk = [] - current_length = 0 - i = 0 - while i < len(document): - segment = document[i] - current_chunk.append(segment) - current_length += len(segment) - if i == len(document) - 1 or current_length >= target_seq_length: - if current_chunk: - # `a_end` is how many segments from `current_chunk` go into the `A` - # (first) sentence. - a_end = 1 - if len(current_chunk) >= 2: - a_end = rng.randint(1, len(current_chunk) - 1) - - tokens_a = [] - for j in range(a_end): - tokens_a.extend(current_chunk[j]) - - tokens_b = [] - # Random next - is_random_next = False - if len(current_chunk) == 1 or rng.random() < 0.5: - is_random_next = True - target_b_length = target_seq_length - len(tokens_a) - - # This should rarely go for more than one iteration for large - # corpora. However, just to be careful, we try to make sure that - # the random document is not the same as the document - # we're processing. - for _ in range(10): - random_document_index = rng.randint(0, len(all_documents) - 1) - if random_document_index != document_index: - break - - random_document = all_documents[random_document_index] - random_start = rng.randint(0, len(random_document) - 1) - for j in range(random_start, len(random_document)): - tokens_b.extend(random_document[j]) - if len(tokens_b) >= target_b_length: - break - # We didn't actually use these segments so we "put them back" so - # they don't go to waste. - num_unused_segments = len(current_chunk) - a_end - i -= num_unused_segments - # Actual next - else: - is_random_next = False - for j in range(a_end, len(current_chunk)): - tokens_b.extend(current_chunk[j]) - truncate_seq_pair(tokens_a, tokens_b, max_num_tokens, rng) - - assert len(tokens_a) >= 1 - assert len(tokens_b) >= 1 - - tokens = [] - segment_ids = [] - tokens.append("[CLS]") - segment_ids.append(0) - for token in tokens_a: - tokens.append(token) - segment_ids.append(0) - - tokens.append("[SEP]") - segment_ids.append(0) - - for token in tokens_b: - tokens.append(token) - segment_ids.append(1) - tokens.append("[SEP]") - segment_ids.append(1) - - (tokens, masked_lm_positions, - masked_lm_labels) = create_masked_lm_predictions( - tokens, masked_lm_prob, max_predictions_per_seq, vocab_words, rng) - instance = TrainingInstance( - tokens=tokens, - segment_ids=segment_ids, - is_random_next=is_random_next, - masked_lm_positions=masked_lm_positions, - masked_lm_labels=masked_lm_labels) - instances.append(instance) - current_chunk = [] - current_length = 0 - i += 1 - - return instances - - -MaskedLmInstance = collections.namedtuple("MaskedLmInstance", - ["index", "label"]) - - -def create_masked_lm_predictions(tokens, masked_lm_prob, - max_predictions_per_seq, vocab_words, rng): - """Creates the predictions for the masked LM objective.""" - - cand_indexes = [] - for (i, token) in enumerate(tokens): - if token == "[CLS]" or token == "[SEP]": - continue - cand_indexes.append(i) - - rng.shuffle(cand_indexes) - - output_tokens = list(tokens) - - num_to_predict = min(max_predictions_per_seq, - max(1, int(round(len(tokens) * masked_lm_prob)))) - - masked_lms = [] - covered_indexes = set() - for index in cand_indexes: - if len(masked_lms) >= num_to_predict: - break - if index in covered_indexes: - continue - covered_indexes.add(index) - - masked_token = None - # 80% of the time, replace with [MASK] - if rng.random() < 0.8: - masked_token = "[MASK]" - else: - # 10% of the time, keep original - if rng.random() < 0.5: - masked_token = tokens[index] - # 10% of the time, replace with random word - else: - masked_token = vocab_words[rng.randint(0, len(vocab_words) - 1)] - - output_tokens[index] = masked_token - - masked_lms.append(MaskedLmInstance(index=index, label=tokens[index])) - - masked_lms = sorted(masked_lms, key=lambda x: x.index) - - masked_lm_positions = [] - masked_lm_labels = [] - for p in masked_lms: - masked_lm_positions.append(p.index) - masked_lm_labels.append(p.label) - - return (output_tokens, masked_lm_positions, masked_lm_labels) - - -def truncate_seq_pair(tokens_a, tokens_b, max_num_tokens, rng): - """Truncates a pair of sequences to a maximum sequence length.""" - while True: - total_length = len(tokens_a) + len(tokens_b) - if total_length <= max_num_tokens: - break - - trunc_tokens = tokens_a if len(tokens_a) > len(tokens_b) else tokens_b - assert len(trunc_tokens) >= 1 - - # We want to sometimes truncate from the front and sometimes from the - # back to add more randomness and avoid biases. - if rng.random() < 0.5: - del trunc_tokens[0] - else: - trunc_tokens.pop() - - -def main(_): - tf.logging.set_verbosity(tf.logging.INFO) - - tokenizer = tokenization.FullTokenizer( - vocab_file=FLAGS.vocab_file, do_lower_case=FLAGS.do_lower_case) - - input_files = [] - for input_pattern in FLAGS.input_file.split(","): - input_files.extend(tf.gfile.Glob(input_pattern)) - - tf.logging.info("*** Reading from input files ***") - for input_file in input_files: - tf.logging.info(" %s", input_file) - - rng = random.Random(FLAGS.random_seed) - instances = create_training_instances( - input_files, tokenizer, FLAGS.max_seq_length, FLAGS.dupe_factor, - FLAGS.short_seq_prob, FLAGS.masked_lm_prob, FLAGS.max_predictions_per_seq, - rng) - - output_files = FLAGS.output_file.split(",") - tf.logging.info("*** Writing to output files ***") - for output_file in output_files: - tf.logging.info(" %s", output_file) - - write_instance_to_example_files(instances, tokenizer, FLAGS.max_seq_length, - FLAGS.max_predictions_per_seq, output_files) - - -if __name__ == "__main__": - flags.mark_flag_as_required("input_file") - flags.mark_flag_as_required("output_file") - flags.mark_flag_as_required("vocab_file") - tf.app.run() diff --git a/tinygrad/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py b/tinygrad/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py deleted file mode 100644 index 6db28412..00000000 --- a/tinygrad/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py +++ /dev/null @@ -1,79 +0,0 @@ -# USAGE: -# 1. Download raw text data with `wikipedia_download.py` - -# 2. Install python==3.7.12 and tensorflow==1.15.5 -# Run `create_pretraining_data.py` to create TFRecords on specific part (This will take some time) -# Command: python3 create_pretraining_data.py --input_file=/path/to/part-00XXX-of-00500 --vocab_file=/path/to/vocab.txt \ -# --output_file=/path/to/output.tfrecord --max_seq_length=512 --max_predictions_per_seq=76 -# -# 2.1 For eval: --input_file=/path/to/eval.txt and -# Command: python3 pick_eval_samples.py --input_tfrecord=/path/to/eval.tfrecord --output_tfrecord=/path/to/output_eval.tfrecord - -# 3. Run `wikipedia.py` to preprocess the data with tinygrad (Use python > 3.7) -# Command: BASEDIR=/path/to/basedir python3 wikipedia.py pre-train X (NOTE: part number needs to match part of step 2) -# This will output to /path/to/basedir/train/X.pkl -# -# 3.1 For eval: -# Command: BASEDIR=/path/to/basedir python3 wikipedia.py pre-eval -# This will output to /path/to/basedir/eval.pkl - -# 4. Run this script to verify the correctness of the preprocessing script for specific part -# Command: python3 external_test_preprocessing_part.py --preprocessed_part=/path/to/basedir/train/X.pkl --tf_records=/path/to/output.tfrecord -import os, argparse, pickle -from tqdm import tqdm - -# This is a workaround for protobuf issue -os.environ['PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION'] = 'python' -os.environ['TF_CPP_MIN_LOG_LEVEL'] = '2' - -import tensorflow as tf - -tf.compat.v1.enable_eager_execution() -tf.compat.v1.logging.set_verbosity(tf.compat.v1.logging.ERROR) - -def _parse_function(proto, max_seq_length, max_predictions_per_seq): - feature_description = { - 'input_ids': tf.io.FixedLenFeature([max_seq_length], tf.int64), - 'input_mask': tf.io.FixedLenFeature([max_seq_length], tf.int64), - 'segment_ids': tf.io.FixedLenFeature([max_seq_length], tf.int64), - 'masked_lm_positions': tf.io.FixedLenFeature([max_predictions_per_seq], tf.int64), - 'masked_lm_ids': tf.io.FixedLenFeature([max_predictions_per_seq], tf.int64), - 'masked_lm_weights': tf.io.FixedLenFeature([max_predictions_per_seq], tf.float32), - 'next_sentence_labels': tf.io.FixedLenFeature([1], tf.int64), - } - return tf.io.parse_single_example(proto, feature_description) - -def load_dataset(file_path, max_seq_length=512, max_predictions_per_seq=76): - dataset = tf.data.TFRecordDataset(file_path) - parse_function = lambda proto: _parse_function(proto, max_seq_length, max_predictions_per_seq) # noqa: E731 - return dataset.map(parse_function) - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Verify the correctness of the preprocessing script for specific part", - formatter_class=argparse.ArgumentDefaultsHelpFormatter) - parser.add_argument("--preprocessed_part", type=str, default=None, - help="Path to preprocessed samples file from `wikipedia.py`") - parser.add_argument("--tf_records", type=str, default=None, - help="Path to TFRecords file from `create_pretraining_data.py` (Reference implementation)") - parser.add_argument("--max_seq_length", type=int, default=512, help="Max sequence length. For MLPerf keep it at 512") - parser.add_argument("--max_predictions_per_seq", type=int, default=76, help="Max predictions per sequence. For MLPerf keep it at 76") - parser.add_argument("--is_eval", type=bool, default=False, help="Whether to run eval or train preprocessing") - args = parser.parse_args() - - assert os.path.isfile(args.preprocessed_part), f"The specified file {args.preprocessed_part} does not exist." - assert os.path.isfile(args.tf_records), f"The specified TFRecords file {args.tf_records} does not exist." - - with open(args.preprocessed_part, 'rb') as f: - preprocessed_samples = pickle.load(f) - - dataset = load_dataset(args.tf_records, args.max_seq_length, args.max_predictions_per_seq) - tf_record_count = sum(1 for _ in dataset) - assert tf_record_count == len(preprocessed_samples), f"Samples in reference: {tf_record_count} != Preprocessed samples: {len(preprocessed_samples)}" - print(f"Total samples in the part: {tf_record_count}") - - for i, (reference_example, preprocessed_sample) in tqdm(enumerate(zip(dataset, preprocessed_samples)), desc="Checking samples", total=len(preprocessed_samples)): # noqa: E501 - feature_keys = ["input_ids", "input_mask", "segment_ids", "masked_lm_positions", "masked_lm_ids", "masked_lm_weights", "next_sentence_labels"] - for key in feature_keys: - reference_example_feature = reference_example[key].numpy() - assert (reference_example_feature == preprocessed_sample[key]).all(), \ - f"{key} are not equal at index {i}\nReference: {reference_example_feature}\nPreprocessed: {preprocessed_sample[key]}" diff --git a/tinygrad/test/external/mlperf_bert/preprocessing/pick_eval_samples.py b/tinygrad/test/external/mlperf_bert/preprocessing/pick_eval_samples.py deleted file mode 100644 index d9f0b644..00000000 --- a/tinygrad/test/external/mlperf_bert/preprocessing/pick_eval_samples.py +++ /dev/null @@ -1,127 +0,0 @@ -# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/pick_eval_samples.py -# NOTE: This is a direct copy of the original script -"""Script for picking certain number of sampels. -""" - -import argparse -import time -import logging -import collections -import tensorflow as tf - -parser = argparse.ArgumentParser( - description="Eval sample picker for BERT.") -parser.add_argument( - '--input_tfrecord', - type=str, - default='', - help='Input tfrecord path') -parser.add_argument( - '--output_tfrecord', - type=str, - default='', - help='Output tfrecord path') -parser.add_argument( - '--num_examples_to_pick', - type=int, - default=10000, - help='Number of examples to pick') -parser.add_argument( - '--max_seq_length', - type=int, - default=512, - help='The maximum number of tokens within a sequence.') -parser.add_argument( - '--max_predictions_per_seq', - type=int, - default=76, - help='The maximum number of predictions within a sequence.') -args = parser.parse_args() - -max_seq_length = args.max_seq_length -max_predictions_per_seq = args.max_predictions_per_seq -logging.basicConfig(level=logging.INFO) - -def decode_record(record): - """Decodes a record to a TensorFlow example.""" - name_to_features = { - "input_ids": - tf.FixedLenFeature([max_seq_length], tf.int64), - "input_mask": - tf.FixedLenFeature([max_seq_length], tf.int64), - "segment_ids": - tf.FixedLenFeature([max_seq_length], tf.int64), - "masked_lm_positions": - tf.FixedLenFeature([max_predictions_per_seq], tf.int64), - "masked_lm_ids": - tf.FixedLenFeature([max_predictions_per_seq], tf.int64), - "masked_lm_weights": - tf.FixedLenFeature([max_predictions_per_seq], tf.float32), - "next_sentence_labels": - tf.FixedLenFeature([1], tf.int64), - } - - example = tf.parse_single_example(record, name_to_features) - - # tf.Example only supports tf.int64, but the TPU only supports tf.int32. - # So cast all int64 to int32. - for name in list(example.keys()): - t = example[name] - if t.dtype == tf.int64: - t = tf.to_int32(t) - example[name] = t - - return example - - -def create_int_feature(values): - feature = tf.train.Feature(int64_list=tf.train.Int64List(value=list(values))) - return feature - - -def create_float_feature(values): - feature = tf.train.Feature(float_list=tf.train.FloatList(value=list(values))) - return feature - - -if __name__ == '__main__': - tic = time.time() - tf.enable_eager_execution() - - d = tf.data.TFRecordDataset(args.input_tfrecord) - num_examples = 0 - records = [] - for record in d: - records.append(record) - num_examples += 1 - - writer = tf.python_io.TFRecordWriter(args.output_tfrecord) - i = 0 - pick_ratio = num_examples / args.num_examples_to_pick - num_examples_picked = 0 - for i in range(args.num_examples_to_pick): - example = decode_record(records[int(i * pick_ratio)]) - features = collections.OrderedDict() - features["input_ids"] = create_int_feature( - example["input_ids"].numpy()) - features["input_mask"] = create_int_feature( - example["input_mask"].numpy()) - features["segment_ids"] = create_int_feature( - example["segment_ids"].numpy()) - features["masked_lm_positions"] = create_int_feature( - example["masked_lm_positions"].numpy()) - features["masked_lm_ids"] = create_int_feature( - example["masked_lm_ids"].numpy()) - features["masked_lm_weights"] = create_float_feature( - example["masked_lm_weights"].numpy()) - features["next_sentence_labels"] = create_int_feature( - example["next_sentence_labels"].numpy()) - - tf_example = tf.train.Example(features=tf.train.Features(feature=features)) - writer.write(tf_example.SerializeToString()) - num_examples_picked += 1 - - writer.close() - toc = time.time() - logging.info("Picked %d examples out of %d samples in %.2f sec", - num_examples_picked, num_examples, toc - tic) diff --git a/tinygrad/test/external/mlperf_bert/preprocessing/tokenization.py b/tinygrad/test/external/mlperf_bert/preprocessing/tokenization.py deleted file mode 100644 index 2d7fc8f1..00000000 --- a/tinygrad/test/external/mlperf_bert/preprocessing/tokenization.py +++ /dev/null @@ -1,415 +0,0 @@ -# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/tokenization.py -# NOTE: This is a direct copy of the original script -"""Tokenization classes.""" - -from __future__ import absolute_import -from __future__ import division -from __future__ import print_function - -import collections -import re -import unicodedata - -from absl import flags -import six -import tensorflow.compat.v1 as tf - -FLAGS = flags.FLAGS - -flags.DEFINE_bool( - "preserve_unused_tokens", False, - "If True, Wordpiece tokenization will not be applied to words in the vocab." -) - -_UNUSED_TOKEN_RE = re.compile("^\\[unused\\d+\\]$") - - -def preserve_token(token, vocab): - """Returns True if the token should forgo tokenization and be preserved.""" - if not FLAGS.preserve_unused_tokens: - return False - if token not in vocab: - return False - return bool(_UNUSED_TOKEN_RE.search(token)) - - -def validate_case_matches_checkpoint(do_lower_case, init_checkpoint): - """Checks whether the casing config is consistent with the checkpoint name.""" - - # The casing has to be passed in by the user and there is no explicit check - # as to whether it matches the checkpoint. The casing information probably - # should have been stored in the bert_config.json file, but it's not, so - # we have to heuristically detect it to validate. - - if not init_checkpoint: - return - - m = re.match("^.*?([A-Za-z0-9_-]+)/bert_model.ckpt", init_checkpoint) - if m is None: - return - - model_name = m.group(1) - - lower_models = [ - "uncased_L-24_H-1024_A-16", "uncased_L-12_H-768_A-12", - "multilingual_L-12_H-768_A-12", "chinese_L-12_H-768_A-12" - ] - - cased_models = [ - "cased_L-12_H-768_A-12", "cased_L-24_H-1024_A-16", - "multi_cased_L-12_H-768_A-12" - ] - - is_bad_config = False - if model_name in lower_models and not do_lower_case: - is_bad_config = True - actual_flag = "False" - case_name = "lowercased" - opposite_flag = "True" - - if model_name in cased_models and do_lower_case: - is_bad_config = True - actual_flag = "True" - case_name = "cased" - opposite_flag = "False" - - if is_bad_config: - raise ValueError( - "You passed in `--do_lower_case=%s` with `--init_checkpoint=%s`. " - "However, `%s` seems to be a %s model, so you " - "should pass in `--do_lower_case=%s` so that the fine-tuning matches " - "how the model was pre-training. If this error is wrong, please " - "just comment out this check." % (actual_flag, init_checkpoint, - model_name, case_name, opposite_flag)) - - -def convert_to_unicode(text): - """Converts `text` to Unicode (if it's not already), assuming utf-8 input.""" - if six.PY3: - if isinstance(text, str): - return text - elif isinstance(text, bytes): - return text.decode("utf-8", "ignore") - else: - raise ValueError("Unsupported string type: %s" % (type(text))) - elif six.PY2: - if isinstance(text, str): - return text.decode("utf-8", "ignore") - elif isinstance(text, unicode): # noqa: F821 - return text - else: - raise ValueError("Unsupported string type: %s" % (type(text))) - else: - raise ValueError("Not running on Python2 or Python 3?") - - -def printable_text(text): - """Returns text encoded in a way suitable for print or `tf.logging`.""" - - # These functions want `str` for both Python2 and Python3, but in one case - # it's a Unicode string and in the other it's a byte string. - if six.PY3: - if isinstance(text, str): - return text - elif isinstance(text, bytes): - return text.decode("utf-8", "ignore") - else: - raise ValueError("Unsupported string type: %s" % (type(text))) - elif six.PY2: - if isinstance(text, str): - return text - elif isinstance(text, unicode): # noqa: F821 - return text.encode("utf-8") - else: - raise ValueError("Unsupported string type: %s" % (type(text))) - else: - raise ValueError("Not running on Python2 or Python 3?") - - -def load_vocab(vocab_file): - """Loads a vocabulary file into a dictionary.""" - vocab = collections.OrderedDict() - with tf.gfile.GFile(vocab_file, "r") as reader: - while True: - token = convert_to_unicode(reader.readline()) - if not token: - break - token = token.strip() - if token not in vocab: - vocab[token] = len(vocab) - return vocab - - -def convert_by_vocab(vocab, items): - """Converts a sequence of [tokens|ids] using the vocab.""" - output = [] - for item in items: - output.append(vocab[item]) - return output - - -def convert_tokens_to_ids(vocab, tokens): - return convert_by_vocab(vocab, tokens) - - -def convert_ids_to_tokens(inv_vocab, ids): - return convert_by_vocab(inv_vocab, ids) - - -def whitespace_tokenize(text): - """Runs basic whitespace cleaning and splitting on a piece of text.""" - text = text.strip() - if not text: - return [] - tokens = text.split() - return tokens - - -class FullTokenizer(object): - """Runs end-to-end tokenziation.""" - - def __init__(self, vocab_file, do_lower_case=True): - self.vocab = load_vocab(vocab_file) - self.inv_vocab = {v: k for k, v in self.vocab.items()} - self.basic_tokenizer = BasicTokenizer( - do_lower_case=do_lower_case, vocab=self.vocab) - self.wordpiece_tokenizer = WordpieceTokenizer(vocab=self.vocab) - - def tokenize(self, text): - split_tokens = [] - for token in self.basic_tokenizer.tokenize(text): - if preserve_token(token, self.vocab): - split_tokens.append(token) - continue - for sub_token in self.wordpiece_tokenizer.tokenize(token): - split_tokens.append(sub_token) - - return split_tokens - - def convert_tokens_to_ids(self, tokens): - return convert_by_vocab(self.vocab, tokens) - - def convert_ids_to_tokens(self, ids): - return convert_by_vocab(self.inv_vocab, ids) - - -class BasicTokenizer(object): - """Runs basic tokenization (punctuation splitting, lower casing, etc.).""" - - def __init__(self, do_lower_case=True, vocab=tuple()): - """Constructs a BasicTokenizer. - - Args: - do_lower_case: Whether to lower case the input. - vocab: A container of tokens to not mutate during tokenization. - """ - self.do_lower_case = do_lower_case - self.vocab = vocab - - def tokenize(self, text): - """Tokenizes a piece of text.""" - text = convert_to_unicode(text) - text = self._clean_text(text) - - # This was added on November 1st, 2018 for the multilingual and Chinese - # models. This is also applied to the English models now, but it doesn't - # matter since the English models were not trained on any Chinese data - # and generally don't have any Chinese data in them (there are Chinese - # characters in the vocabulary because Wikipedia does have some Chinese - # words in the English Wikipedia.). - text = self._tokenize_chinese_chars(text) - - orig_tokens = whitespace_tokenize(text) - split_tokens = [] - for token in orig_tokens: - if preserve_token(token, self.vocab): - split_tokens.append(token) - continue - if self.do_lower_case: - token = token.lower() - token = self._run_strip_accents(token) - split_tokens.extend(self._run_split_on_punc(token)) - - output_tokens = whitespace_tokenize(" ".join(split_tokens)) - return output_tokens - - def _run_strip_accents(self, text): - """Strips accents from a piece of text.""" - text = unicodedata.normalize("NFD", text) - output = [] - for char in text: - cat = unicodedata.category(char) - if cat == "Mn": - continue - output.append(char) - return "".join(output) - - def _run_split_on_punc(self, text): - """Splits punctuation on a piece of text.""" - chars = list(text) - i = 0 - start_new_word = True - output = [] - while i < len(chars): - char = chars[i] - if _is_punctuation(char): - output.append([char]) - start_new_word = True - else: - if start_new_word: - output.append([]) - start_new_word = False - output[-1].append(char) - i += 1 - - return ["".join(x) for x in output] - - def _tokenize_chinese_chars(self, text): - """Adds whitespace around any CJK character.""" - output = [] - for char in text: - cp = ord(char) - if self._is_chinese_char(cp): - output.append(" ") - output.append(char) - output.append(" ") - else: - output.append(char) - return "".join(output) - - def _is_chinese_char(self, cp): - """Checks whether CP is the codepoint of a CJK character.""" - # This defines a "chinese character" as anything in the CJK Unicode block: - # https://en.wikipedia.org/wiki/CJK_Unified_Ideographs_(Unicode_block) - # - # Note that the CJK Unicode block is NOT all Japanese and Korean characters, - # despite its name. The modern Korean Hangul alphabet is a different block, - # as is Japanese Hiragana and Katakana. Those alphabets are used to write - # space-separated words, so they are not treated specially and handled - # like all of the other languages. - if ((cp >= 0x4E00 and cp <= 0x9FFF) or # - (cp >= 0x3400 and cp <= 0x4DBF) or # - (cp >= 0x20000 and cp <= 0x2A6DF) or # - (cp >= 0x2A700 and cp <= 0x2B73F) or # - (cp >= 0x2B740 and cp <= 0x2B81F) or # - (cp >= 0x2B820 and cp <= 0x2CEAF) or - (cp >= 0xF900 and cp <= 0xFAFF) or # - (cp >= 0x2F800 and cp <= 0x2FA1F)): # - return True - - return False - - def _clean_text(self, text): - """Performs invalid character removal and whitespace cleanup on text.""" - output = [] - for char in text: - cp = ord(char) - if cp == 0 or cp == 0xfffd or _is_control(char): - continue - if _is_whitespace(char): - output.append(" ") - else: - output.append(char) - return "".join(output) - - -class WordpieceTokenizer(object): - """Runs WordPiece tokenziation.""" - - def __init__(self, vocab, unk_token="[UNK]", max_input_chars_per_word=200): - self.vocab = vocab - self.unk_token = unk_token - self.max_input_chars_per_word = max_input_chars_per_word - - def tokenize(self, text): - """Tokenizes a piece of text into its word pieces. - - This uses a greedy longest-match-first algorithm to perform tokenization - using the given vocabulary. - - For example: - input = "unaffable" - output = ["un", "##aff", "##able"] - - Args: - text: A single token or whitespace separated tokens. This should have - already been passed through `BasicTokenizer. - - Returns: - A list of wordpiece tokens. - """ - - text = convert_to_unicode(text) - - output_tokens = [] - for token in whitespace_tokenize(text): - chars = list(token) - if len(chars) > self.max_input_chars_per_word: - output_tokens.append(self.unk_token) - continue - - is_bad = False - start = 0 - sub_tokens = [] - while start < len(chars): - end = len(chars) - cur_substr = None - while start < end: - substr = "".join(chars[start:end]) - if start > 0: - substr = "##" + substr - if substr in self.vocab: - cur_substr = substr - break - end -= 1 - if cur_substr is None: - is_bad = True - break - sub_tokens.append(cur_substr) - start = end - - if is_bad: - output_tokens.append(self.unk_token) - else: - output_tokens.extend(sub_tokens) - return output_tokens - - -def _is_whitespace(char): - """Checks whether `chars` is a whitespace character.""" - # \t, \n, and \r are technically control characters but we treat them - # as whitespace since they are generally considered as such. - if char == " " or char == "\t" or char == "\n" or char == "\r": - return True - cat = unicodedata.category(char) - if cat == "Zs": - return True - return False - - -def _is_control(char): - """Checks whether `chars` is a control character.""" - # These are technically control characters but we count them as whitespace - # characters. - if char == "\t" or char == "\n" or char == "\r": - return False - cat = unicodedata.category(char) - if cat in ("Cc", "Cf"): - return True - return False - - -def _is_punctuation(char): - """Checks whether `chars` is a punctuation character.""" - cp = ord(char) - # We treat all non-letter/number ASCII as punctuation. - # Characters such as "^", "$", and "`" are not in the Unicode - # Punctuation class but we treat them as punctuation anyways, for - # consistency. - if ((cp >= 33 and cp <= 47) or (cp >= 58 and cp <= 64) or - (cp >= 91 and cp <= 96) or (cp >= 123 and cp <= 126)): - return True - cat = unicodedata.category(char) - if cat.startswith("P"): - return True - return False diff --git a/tinygrad/test/external/mlperf_resnet/lars_optimizer.py b/tinygrad/test/external/mlperf_resnet/lars_optimizer.py deleted file mode 100644 index 6c1a169a..00000000 --- a/tinygrad/test/external/mlperf_resnet/lars_optimizer.py +++ /dev/null @@ -1,233 +0,0 @@ -# https://github.com/mlcommons/training/blob/e3769c8dcf88cd21e1001dd2f894b40a1513ec5d/image_classification/tensorflow2/lars_optimizer.py -# changes: don't call lr_t if it's not a schedule - -# Copyright 2018 The TensorFlow Authors. All Rights Reserved. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -"""Layer-wise Adaptive Rate Scaling optimizer for large-batch training.""" - -from __future__ import absolute_import -from __future__ import division -from __future__ import print_function - -import tensorflow as tf -# from tf2_common.training import optimizer_v2modified -from tensorflow.python.framework import ops -from tensorflow.python.keras import backend_config -from tensorflow.python.keras.optimizer_v2 import optimizer_v2 -from tensorflow.python.ops import array_ops -from tensorflow.python.ops import linalg_ops -from tensorflow.python.ops import math_ops -from tensorflow.python.training import training_ops -from tensorflow.python.ops import state_ops - - -# class LARSOptimizer(optimizer_v2modified.OptimizerV2Modified): -class LARSOptimizer(optimizer_v2.OptimizerV2): - """Layer-wise Adaptive Rate Scaling for large batch training. - - Introduced by "Large Batch Training of Convolutional Networks" by Y. You, - I. Gitman, and B. Ginsburg. (https://arxiv.org/abs/1708.03888) - - Implements the LARS learning rate scheme presented in the paper above. This - optimizer is useful when scaling the batch size to up to 32K without - significant performance degradation. It is recommended to use the optimizer - in conjunction with: - - Gradual learning rate warm-up - - Linear learning rate scaling - - Poly rule learning rate decay - - Note, LARS scaling is currently only enabled for dense tensors. Sparse tensors - use the default momentum optimizer. - """ - - def __init__( - self, - learning_rate, - momentum=0.9, - weight_decay=0.0001, - # The LARS coefficient is a hyperparameter - eeta=0.001, - epsilon=0.0, - name="LARSOptimizer", - # Enable skipping variables from LARS scaling. - # TODO(sameerkm): Enable a direct mechanism to pass a - # subset of variables to the optimizer. - skip_list=None, - use_nesterov=False, - **kwargs): - """Construct a new LARS Optimizer. - - Args: - learning_rate: A `Tensor`, floating point value, or a schedule that is a - `tf.keras.optimizers.schedules.LearningRateSchedule`, or a callable - that takes no arguments and returns the actual value to use. The - learning rate. - momentum: A floating point value. Momentum hyperparameter. - weight_decay: A floating point value. Weight decay hyperparameter. - eeta: LARS coefficient as used in the paper. Dfault set to LARS - coefficient from the paper. (eeta / weight_decay) determines the highest - scaling factor in LARS. - epsilon: Optional epsilon parameter to be set in models that have very - small gradients. Default set to 0.0. - name: Optional name prefix for variables and ops created by LARSOptimizer. - skip_list: List of strings to enable skipping variables from LARS scaling. - If any of the strings in skip_list is a subset of var.name, variable - 'var' is skipped from LARS scaling. For a typical classification model - with batch normalization, the skip_list is ['batch_normalization', - 'bias'] - use_nesterov: when set to True, nesterov momentum will be enabled - **kwargs: keyword arguments. - - Raises: - ValueError: If a hyperparameter is set to a non-sensical value. - """ - if momentum < 0.0: - raise ValueError("momentum should be positive: %s" % momentum) - if weight_decay < 0.0: - raise ValueError("weight_decay should be positive: %s" % weight_decay) - super(LARSOptimizer, self).__init__(name=name, **kwargs) - - self._set_hyper("learning_rate", learning_rate) - - # When directly using class members, instead of - # _set_hyper and _get_hyper (such as learning_rate above), - # the values are fixed after __init(), and not being - # updated during the training process. - # This provides better performance but less flexibility. - self.momentum = momentum - self.weight_decay = weight_decay - self.eeta = eeta - self.epsilon = epsilon or backend_config.epsilon() - self._skip_list = skip_list - self.use_nesterov = use_nesterov - - def _prepare_local(self, var_device, var_dtype, apply_state): - lr_t = self._get_hyper("learning_rate", var_dtype) - local_step = math_ops.cast(self.iterations, var_dtype) - if callable(lr_t): lr_t = math_ops.cast(lr_t(local_step), var_dtype) - learning_rate_t = array_ops.identity(lr_t) - - apply_state[(var_device, var_dtype)].update( - dict( - learning_rate=learning_rate_t, - )) - - def _create_slots(self, var_list): - for v in var_list: - self.add_slot(v, "momentum") - - def compute_lr(self, grad, var, coefficients): - scaled_lr = coefficients["learning_rate"] - if self._skip_list is None or not any(v in var.name - for v in self._skip_list): - w_norm = linalg_ops.norm(var, ord=2) - g_norm = linalg_ops.norm(grad, ord=2) - trust_ratio = array_ops.where( - math_ops.greater(w_norm, 0), - array_ops.where( - math_ops.greater(g_norm, 0), - (self.eeta * w_norm / - (g_norm + self.weight_decay * w_norm + self.epsilon)), 1.0), 1.0) - - scaled_lr = coefficients["learning_rate"] * trust_ratio - # Add the weight regularization gradient - grad = grad + self.weight_decay * var - return scaled_lr, grad - - def _apply_dense(self, grad, var, apply_state=None): - var_device, var_dtype = var.device, var.dtype.base_dtype - coefficients = ((apply_state or {}).get((var_device, var_dtype)) - or self._fallback_apply_state(var_device, var_dtype)) - - scaled_lr, grad = self.compute_lr(grad, var, coefficients) - mom = self.get_slot(var, "momentum") - return training_ops.apply_momentum( - var, - mom, - math_ops.cast(1.0, var.dtype.base_dtype), - grad * scaled_lr, - self.momentum, - use_locking=False, - use_nesterov=self.use_nesterov) - - def _resource_apply_dense(self, grad, var, apply_state=None): - var_device, var_dtype = var.device, var.dtype.base_dtype - coefficients = ((apply_state or {}).get((var_device, var_dtype)) - or self._fallback_apply_state(var_device, var_dtype)) - - scaled_lr, grad = self.compute_lr(grad, var, coefficients) - mom = self.get_slot(var, "momentum") - # Use ApplyKerasMomentum instead of ApplyMomentum - # training_ops.resource_apply_keras_momentum( - # var.handle, - # mom.handle, - # scaled_lr, - # grad, - # coefficients["momentum"], - # use_locking=False, - # use_nesterov=self.use_nesterov) - - mom_t = mom * self.momentum - grad * scaled_lr - mom_t = state_ops.assign(mom, mom_t, use_locking=False) - if self.use_nesterov: - var_t = var + mom_t * self.momentum - grad * scaled_lr - else: - var_t = var + mom_t - return state_ops.assign(var, var_t, use_locking=False).op - - # Fallback to momentum optimizer for sparse tensors - def _apply_sparse(self, grad, var, apply_state=None): - var_device, var_dtype = var.device, var.dtype.base_dtype - coefficients = ((apply_state or {}).get((var_device, var_dtype)) - or self._fallback_apply_state(var_device, var_dtype)) - - mom = self.get_slot(var, "momentum") - return training_ops.sparse_apply_momentum( - var, - mom, - coefficients["learning_rate"], - grad.values, - grad.indices, - self.momentum, - use_locking=False, - use_nesterov=self.use_nesterov) - - def _resource_apply_sparse(self, grad, var, indices, apply_state=None): - var_device, var_dtype = var.device, var.dtype.base_dtype - coefficients = ((apply_state or {}).get((var_device, var_dtype)) - or self._fallback_apply_state(var_device, var_dtype)) - - mom = self.get_slot(var, "momentum") - return training_ops.resource_sparse_apply_keras_momentum( - var.handle, - mom.handle, - coefficients["learning_rate"], - grad, - indices, - self.momentum, - use_locking=False, - use_nesterov=self.use_nesterov) - - def get_config(self): - config = super(LARSOptimizer, self).get_config() - config.update({ - "learning_rate": self._serialize_hyperparameter("learning_rate"), - "momentum": self.momentum, - "weight_decay": self.weight_decay, - "eeta": self.eeta, - "epsilon": self.epsilon, - "use_nesterov": self.use_nesterov, - }) - return config diff --git a/tinygrad/test/external/mlperf_resnet/lars_util.py b/tinygrad/test/external/mlperf_resnet/lars_util.py deleted file mode 100644 index 5fd6337c..00000000 --- a/tinygrad/test/external/mlperf_resnet/lars_util.py +++ /dev/null @@ -1,179 +0,0 @@ -# https://github.com/mlcommons/training/blob/e237206991d10449d9675d95606459a3cb6c21ad/image_classification/tensorflow2/lars_util.py -# changes: commented out logging -# changes: convert_to_tensor_v2 -> convert_to_tensor -# changes: extend from tf.python.keras.optimizer_v2.learning_rate_schedule.LearningRateScheduler - -# Copyright 2018 The TensorFlow Authors. All Rights Reserved. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# ============================================================================== -"""Enable Layer-wise Adaptive Rate Scaling optimizer in ResNet.""" - -from __future__ import absolute_import -from __future__ import division -from __future__ import print_function - -from absl import flags -import tensorflow as tf - -#from tf2_common.utils.mlp_log import mlp_log -from tensorflow.python.eager import context -from tensorflow.python.framework import ops -from tensorflow.python.ops import math_ops -from tensorflow.python.keras.optimizer_v2 import learning_rate_schedule - -FLAGS = flags.FLAGS - - -def define_lars_flags(): - """Defines flags needed by LARS optimizer.""" - - flags.DEFINE_float( - 'end_learning_rate', default=None, - help=('Polynomial decay end learning rate.')) - - flags.DEFINE_float( - 'lars_epsilon', default=0.0, - help=('Override autoselected LARS epsilon.')) - - flags.DEFINE_float( - 'warmup_epochs', default=None, - help=('Override autoselected polynomial decay warmup epochs.')) - - flags.DEFINE_float( - 'momentum', - default=0.9, - help=('Momentum parameter used in the MomentumOptimizer.')) - - -class PolynomialDecayWithWarmup(learning_rate_schedule.LearningRateSchedule): - """A LearningRateSchedule that uses a polynomial decay with warmup.""" - - def __init__( - self, - batch_size, - steps_per_epoch, - train_steps, - initial_learning_rate=None, - end_learning_rate=None, - warmup_epochs=None, - compute_lr_on_cpu=False, - name=None): - """Applies a polynomial decay to the learning rate with warmup.""" - super(PolynomialDecayWithWarmup, self).__init__() - - self.batch_size = batch_size - self.steps_per_epoch = steps_per_epoch - self.train_steps = train_steps - self.name = name - self.learning_rate_ops_cache = {} - self.compute_lr_on_cpu = compute_lr_on_cpu - - if batch_size < 16384: - self.initial_learning_rate = 10.0 - warmup_epochs_ = 5 - elif batch_size < 32768: - self.initial_learning_rate = 25.0 - warmup_epochs_ = 5 - else: - self.initial_learning_rate = 31.2 - warmup_epochs_ = 25 - - # Override default poly learning rate and warmup epochs - if initial_learning_rate: - self.initial_learning_rate = initial_learning_rate - - if end_learning_rate: - self.end_learning_rate = end_learning_rate - else: - self.end_learning_rate = 0.0001 - - if warmup_epochs is not None: - warmup_epochs_ = warmup_epochs - self.warmup_epochs = warmup_epochs_ - - """ - opt_name = FLAGS.optimizer.lower() - mlp_log.mlperf_print('opt_name', opt_name) - if opt_name == 'lars': - mlp_log.mlperf_print('{}_epsilon'.format(opt_name), FLAGS.lars_epsilon) - mlp_log.mlperf_print('{}_opt_weight_decay'.format(opt_name), - FLAGS.weight_decay) - mlp_log.mlperf_print('{}_opt_base_learning_rate'.format(opt_name), - self.initial_learning_rate) - mlp_log.mlperf_print('{}_opt_learning_rate_warmup_epochs'.format(opt_name), - warmup_epochs_) - mlp_log.mlperf_print('{}_opt_end_learning_rate'.format(opt_name), - self.end_learning_rate) - """ - warmup_steps = warmup_epochs_ * steps_per_epoch - self.warmup_steps = tf.cast(warmup_steps, tf.float32) - self.decay_steps = train_steps - warmup_steps + 1 - """ - mlp_log.mlperf_print('{}_opt_learning_rate_decay_steps'.format(opt_name), - int(self.decay_steps)) - mlp_log.mlperf_print( - '{}_opt_learning_rate_decay_poly_power'.format(opt_name), 2.0) - mlp_log.mlperf_print('{}_opt_momentum'.format(opt_name), FLAGS.momentum) - """ - - self.poly_rate_scheduler = tf.keras.optimizers.schedules.PolynomialDecay( - initial_learning_rate=self.initial_learning_rate, - decay_steps=self.decay_steps, - end_learning_rate=self.end_learning_rate, - power=2.0) - - def __call__(self, step): - if tf.executing_eagerly(): - return self._get_learning_rate(step) - - # In an eager function or graph, the current implementation of optimizer - # repeatedly call and thus create ops for the learning rate schedule. To - # avoid this, we cache the ops if not executing eagerly. - graph = tf.compat.v1.get_default_graph() - if graph not in self.learning_rate_ops_cache: - if self.compute_lr_on_cpu: - with tf.device('/device:CPU:0'): - self.learning_rate_ops_cache[graph] = self._get_learning_rate(step) - else: - self.learning_rate_ops_cache[graph] = self._get_learning_rate(step) - return self.learning_rate_ops_cache[graph] - - def _get_learning_rate(self, step): - with ops.name_scope_v2(self.name or 'PolynomialDecayWithWarmup') as name: - - initial_learning_rate = ops.convert_to_tensor( - self.initial_learning_rate, name='initial_learning_rate') - warmup_steps = ops.convert_to_tensor( - self.warmup_steps, name='warmup_steps') - - warmup_rate = ( - initial_learning_rate * step / warmup_steps) - - poly_steps = math_ops.subtract(step, warmup_steps) - poly_rate = self.poly_rate_scheduler(poly_steps) - - decay_rate = tf.where(step <= warmup_steps, - warmup_rate, poly_rate, name=name) - return decay_rate - - def get_config(self): - return { - 'batch_size': self.batch_size, - 'steps_per_epoch': self.steps_per_epoch, - 'train_steps': self.train_steps, - 'initial_learning_rate': self.initial_learning_rate, - 'end_learning_rate': self.end_learning_rate, - 'warmup_epochs': self.warmup_epochs, - 'name': self.name, - } diff --git a/tinygrad/test/external/mlperf_retinanet/coco_utils.py b/tinygrad/test/external/mlperf_retinanet/coco_utils.py deleted file mode 100644 index 756bd695..00000000 --- a/tinygrad/test/external/mlperf_retinanet/coco_utils.py +++ /dev/null @@ -1,89 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/coco_utils.py - -import os -import torch -import torchvision - -from test.external.mlperf_retinanet import transforms as T - -class ConvertCocoPolysToMask(object): - def __init__(self, filter_iscrowd=True): - self.filter_iscrowd = filter_iscrowd - - def __call__(self, image, target): - w, h = image.size - - image_id = target["image_id"] - image_id = torch.tensor([image_id]) - - anno = target["annotations"] - - if self.filter_iscrowd: - anno = [obj for obj in anno if obj['iscrowd'] == 0] - - boxes = [obj["bbox"] for obj in anno] - # guard against no boxes via resizing - boxes = torch.as_tensor(boxes, dtype=torch.float32).reshape(-1, 4) - boxes[:, 2:] += boxes[:, :2] - boxes[:, 0::2].clamp_(min=0, max=w) - boxes[:, 1::2].clamp_(min=0, max=h) - - classes = [obj["category_id"] for obj in anno] - classes = torch.tensor(classes, dtype=torch.int64) - - keypoints = None - if anno and "keypoints" in anno[0]: - keypoints = [obj["keypoints"] for obj in anno] - keypoints = torch.as_tensor(keypoints, dtype=torch.float32) - num_keypoints = keypoints.shape[0] - if num_keypoints: - keypoints = keypoints.view(num_keypoints, -1, 3) - - keep = (boxes[:, 3] > boxes[:, 1]) & (boxes[:, 2] > boxes[:, 0]) - boxes = boxes[keep] - classes = classes[keep] - - target = {} - target["boxes"] = boxes - target["labels"] = classes - target["image_id"] = image_id - - # for conversion to coco api - area = torch.tensor([obj["area"] for obj in anno]) - iscrowd = torch.tensor([obj["iscrowd"] for obj in anno]) - target["area"] = area - target["iscrowd"] = iscrowd - - return image, target - -class CocoDetection(torchvision.datasets.CocoDetection): - def __init__(self, img_folder, ann_file, transforms): - super(CocoDetection, self).__init__(img_folder, ann_file) - self._transforms = transforms - - def __getitem__(self, idx): - img, target = super(CocoDetection, self).__getitem__(idx) - image_id = self.ids[idx] - target = dict(image_id=image_id, annotations=target) - if self._transforms is not None: - img, target = self._transforms(img, target) - return img, target - -def get_openimages(name, root, image_set, transforms): - PATHS = { - "train": os.path.join(root, "train"), - "val": os.path.join(root, "validation"), - } - - t = [ConvertCocoPolysToMask(filter_iscrowd=False)] - - if transforms is not None: - t.append(transforms) - transforms = T.Compose(t) - - img_folder = os.path.join(PATHS[image_set], "data") - ann_file = os.path.join(PATHS[image_set], "labels", f"{name}.json") - - dataset = CocoDetection(img_folder, ann_file, transforms=transforms) - - return dataset \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/focal_loss.py b/tinygrad/test/external/mlperf_retinanet/focal_loss.py deleted file mode 100644 index 7167b58a..00000000 --- a/tinygrad/test/external/mlperf_retinanet/focal_loss.py +++ /dev/null @@ -1,51 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/focal_loss.py - -import torch -import torch.nn.functional as F - - -def sigmoid_focal_loss( - inputs: torch.Tensor, - targets: torch.Tensor, - alpha: float = 0.25, - gamma: float = 2, - reduction: str = "none", -): - """ - Original implementation from https://github.com/facebookresearch/fvcore/blob/master/fvcore/nn/focal_loss.py . - Loss used in RetinaNet for dense detection: https://arxiv.org/abs/1708.02002. - - Args: - inputs: A float tensor of arbitrary shape. - The predictions for each example. - targets: A float tensor with the same shape as inputs. Stores the binary - classification label for each element in inputs - (0 for the negative class and 1 for the positive class). - alpha: (optional) Weighting factor in range (0,1) to balance - positive vs negative examples or -1 for ignore. Default = 0.25 - gamma: Exponent of the modulating factor (1 - p_t) to - balance easy vs hard examples. - reduction: 'none' | 'mean' | 'sum' - 'none': No reduction will be applied to the output. - 'mean': The output will be averaged. - 'sum': The output will be summed. - Returns: - Loss tensor with the reduction option applied. - """ - p = torch.sigmoid(inputs) - ce_loss = F.binary_cross_entropy_with_logits( - inputs, targets, reduction="none" - ) - p_t = p * targets + (1 - p) * (1 - targets) - loss = ce_loss * ((1 - p_t) ** gamma) - - if alpha >= 0: - alpha_t = alpha * targets + (1 - alpha) * (1 - targets) - loss = alpha_t * loss - - if reduction == "mean": - loss = loss.mean() - elif reduction == "sum": - loss = loss.sum() - - return loss \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/model/boxes.py b/tinygrad/test/external/mlperf_retinanet/model/boxes.py deleted file mode 100644 index 96dbceeb..00000000 --- a/tinygrad/test/external/mlperf_retinanet/model/boxes.py +++ /dev/null @@ -1,65 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/boxes.py - -import torch -from torch import Tensor -from typing import Tuple - -def _upcast(t: Tensor) -> Tensor: - # Protects from numerical overflows in multiplications by upcasting to the equivalent higher type - if t.is_floating_point(): - return t if t.dtype in (torch.float32, torch.float64) else t.float() - else: - return t if t.dtype in (torch.int32, torch.int64) else t.int() - - -def box_area(boxes: Tensor) -> Tensor: - """ - Computes the area of a set of bounding boxes, which are specified by their - (x1, y1, x2, y2) coordinates. - - Args: - boxes (Tensor[N, 4]): boxes for which the area will be computed. They - are expected to be in (x1, y1, x2, y2) format with - ``0 <= x1 < x2`` and ``0 <= y1 < y2``. - - Returns: - Tensor[N]: the area for each box - """ - boxes = _upcast(boxes) - return (boxes[:, 2] - boxes[:, 0]) * (boxes[:, 3] - boxes[:, 1]) - - -# implementation from https://github.com/kuangliu/torchcv/blob/master/torchcv/utils/box.py -# with slight modifications -def _box_inter_union(boxes1: Tensor, boxes2: Tensor) -> Tuple[Tensor, Tensor]: - area1 = box_area(boxes1) - area2 = box_area(boxes2) - - lt = torch.max(boxes1[:, None, :2], boxes2[:, :2]) # [N,M,2] - rb = torch.min(boxes1[:, None, 2:], boxes2[:, 2:]) # [N,M,2] - - wh = _upcast(rb - lt).clamp(min=0) # [N,M,2] - inter = wh[:, :, 0] * wh[:, :, 1] # [N,M] - - union = area1[:, None] + area2 - inter - - return inter, union - - -def box_iou(boxes1: Tensor, boxes2: Tensor) -> Tensor: - """ - Return intersection-over-union (Jaccard index) between two sets of boxes. - - Both sets of boxes are expected to be in ``(x1, y1, x2, y2)`` format with - ``0 <= x1 < x2`` and ``0 <= y1 < y2``. - - Args: - boxes1 (Tensor[N, 4]): first set of boxes - boxes2 (Tensor[M, 4]): second set of boxes - - Returns: - Tensor[N, M]: the NxM matrix containing the pairwise IoU values for every element in boxes1 and boxes2 - """ - inter, union = _box_inter_union(boxes1, boxes2) - iou = inter / union - return iou \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/model/image_list.py b/tinygrad/test/external/mlperf_retinanet/model/image_list.py deleted file mode 100644 index f7a4cf2e..00000000 --- a/tinygrad/test/external/mlperf_retinanet/model/image_list.py +++ /dev/null @@ -1,27 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/image_list.py - -import torch -from torch import Tensor -from typing import List, Tuple - - -class ImageList(object): - """ - Structure that holds a list of images (of possibly - varying sizes) as a single tensor. - This works by padding the images to the same size, - and storing in a field the original sizes of each image - """ - - def __init__(self, tensors: Tensor, image_sizes: List[Tuple[int, int]]): - """ - Args: - tensors (tensor) - image_sizes (list[tuple[int, int]]) - """ - self.tensors = tensors - self.image_sizes = image_sizes - - def to(self, device: torch.device) -> 'ImageList': - cast_tensor = self.tensors.to(device) - return ImageList(cast_tensor, self.image_sizes) \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/model/transform.py b/tinygrad/test/external/mlperf_retinanet/model/transform.py deleted file mode 100644 index b68e8cfb..00000000 --- a/tinygrad/test/external/mlperf_retinanet/model/transform.py +++ /dev/null @@ -1,163 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/transform.py - -import torch - -from torch import nn, Tensor -from typing import List, Tuple, Dict, Optional - -from test.external.mlperf_retinanet.model.image_list import ImageList - -@torch.jit.unused -def _get_shape_onnx(image: Tensor) -> Tensor: - from torch.onnx import operators - return operators.shape_as_tensor(image)[-2:] - -def _resize_image_and_masks(image: Tensor, - target: Optional[Dict[str, Tensor]] = None, - image_size: Optional[Tuple[int, int]] = None, - ) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: - image = torch.nn.functional.interpolate(image[None], size=image_size, scale_factor=None, mode='bilinear', - recompute_scale_factor=None, align_corners=False)[0] - - if target is None: - return image, target - - if "masks" in target: - mask = target["masks"] - mask = torch.nn.functional.interpolate(mask[:, None].float(), size=image_size, scale_factor=None, - recompute_scale_factor=None)[:, 0].byte() - target["masks"] = mask - return image, target - -class GeneralizedRCNNTransform(nn.Module): - """ - Performs input / target transformation before feeding the data to a GeneralizedRCNN - model. - - The transformations it perform are: - - input normalization (mean subtraction and std division) - - input / target resizing to match image_size - - It returns a ImageList for the inputs, and a List[Dict[Tensor]] for the targets - """ - - def __init__(self, image_size: Optional[Tuple[int, int]], - image_mean: List[float], image_std: List[float],): - super(GeneralizedRCNNTransform, self).__init__() - self.image_size = image_size - self.image_mean = image_mean - self.image_std = image_std - - def forward(self, - images: List[Tensor], - targets: Optional[List[Dict[str, Tensor]]] = None - ) -> Tuple[ImageList, Optional[List[Dict[str, Tensor]]]]: - images = list(img for img in images) - if targets is not None: - # make a copy of targets to avoid modifying it in-place - # once torchscript supports dict comprehension - # this can be simplified as follows - # targets = [{k: v for k,v in t.items()} for t in targets] - targets_copy: List[Dict[str, Tensor]] = [] - for t in targets: - data: Dict[str, Tensor] = {} - for k, v in t.items(): - data[k] = v - targets_copy.append(data) - targets = targets_copy - for i in range(len(images)): - image = images[i] - target_index = targets[i] if targets is not None else None - - if image.dim() != 3: - raise ValueError("images is expected to be a list of 3d tensors " - "of shape [C, H, W], got {}".format(image.shape)) - image = self.normalize(image) - image, target_index = self.resize(image, target_index) - images[i] = image - if targets is not None and target_index is not None: - targets[i] = target_index - - image_sizes = [img.shape[-2:] for img in images] - images = torch.stack(images) - image_sizes_list: List[Tuple[int, int]] = [] - for image_size in image_sizes: - assert len(image_size) == 2 - image_sizes_list.append((image_size[0], image_size[1])) - - image_list = ImageList(images, image_sizes_list) - return image_list, targets - - def normalize(self, image: Tensor) -> Tensor: - if not image.is_floating_point(): - raise TypeError( - f"Expected input images to be of floating type (in range [0, 1]), " - f"but found type {image.dtype} instead" - ) - dtype, device = image.dtype, image.device - mean = torch.as_tensor(self.image_mean, dtype=dtype, device=device) - std = torch.as_tensor(self.image_std, dtype=dtype, device=device) - return (image - mean[:, None, None]) / std[:, None, None] - - def torch_choice(self, k: List[int]) -> int: - """ - Implements `random.choice` via torch ops so it can be compiled with - TorchScript. Remove if https://github.com/pytorch/pytorch/issues/25803 - is fixed. - """ - index = int(torch.empty(1).uniform_(0., float(len(k))).item()) - return k[index] - - def resize(self, - image: Tensor, - target: Optional[Dict[str, Tensor]] = None, - ) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: - h, w = image.shape[-2:] - image, target = _resize_image_and_masks(image, target, self.image_size) - - if target is None: - return image, target - - bbox = target["boxes"] - bbox = resize_boxes(bbox, (h, w), image.shape[-2:]) - target["boxes"] = bbox - - return image, target - - def postprocess(self, - result: List[Dict[str, Tensor]], - image_shapes: List[Tuple[int, int]], - original_image_sizes: List[Tuple[int, int]] - ) -> List[Dict[str, Tensor]]: - if self.training: - return result - for i, (pred, im_s, o_im_s) in enumerate(zip(result, image_shapes, original_image_sizes)): - boxes = pred["boxes"] - boxes = resize_boxes(boxes, im_s, o_im_s) - result[i]["boxes"] = boxes - return result - - def __repr__(self) -> str: - format_string = self.__class__.__name__ + '(' - _indent = '\n ' - format_string += "{0}Normalize(mean={1}, std={2})".format(_indent, self.image_mean, self.image_std) - format_string += "{0}Resize(height={1}, width={2}, mode='bilinear')".format(_indent, self.image_size[0], - self.image_size[1]) - format_string += '\n)' - return format_string - -def resize_boxes(boxes: Tensor, original_size: List[int], new_size: List[int]) -> Tensor: - ratios = [ - torch.tensor(s, dtype=torch.float32, device=boxes.device) / - torch.tensor(s_orig, dtype=torch.float32, device=boxes.device) - for s, s_orig in zip(new_size, original_size) - ] - ratio_height, ratio_width = ratios - xmin, ymin, xmax, ymax = boxes.unbind(1) - - xmin = xmin * ratio_width - xmax = xmax * ratio_width - ymin = ymin * ratio_height - ymax = ymax * ratio_height - res = torch.stack((xmin, ymin, xmax, ymax), dim=1) - return res \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/model/utils.py b/tinygrad/test/external/mlperf_retinanet/model/utils.py deleted file mode 100644 index 33c64c16..00000000 --- a/tinygrad/test/external/mlperf_retinanet/model/utils.py +++ /dev/null @@ -1,123 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/utils.py - -import torch - -class Matcher(object): - """ - This class assigns to each predicted "element" (e.g., a box) a ground-truth - element. Each predicted element will have exactly zero or one matches; each - ground-truth element may be assigned to zero or more predicted elements. - - Matching is based on the MxN match_quality_matrix, that characterizes how well - each (ground-truth, predicted)-pair match. For example, if the elements are - boxes, the matrix may contain box IoU overlap values. - - The matcher returns a tensor of size N containing the index of the ground-truth - element m that matches to prediction n. If there is no match, a negative value - is returned. - """ - - BELOW_LOW_THRESHOLD = -1 - BETWEEN_THRESHOLDS = -2 - - __annotations__ = { - 'BELOW_LOW_THRESHOLD': int, - 'BETWEEN_THRESHOLDS': int, - } - - def __init__(self, high_threshold, low_threshold, allow_low_quality_matches=False): - # type: (float, float, bool) -> None - """ - Args: - high_threshold (float): quality values greater than or equal to - this value are candidate matches. - low_threshold (float): a lower quality threshold used to stratify - matches into three levels: - 1) matches >= high_threshold - 2) BETWEEN_THRESHOLDS matches in [low_threshold, high_threshold) - 3) BELOW_LOW_THRESHOLD matches in [0, low_threshold) - allow_low_quality_matches (bool): if True, produce additional matches - for predictions that have only low-quality match candidates. See - set_low_quality_matches_ for more details. - """ - self.BELOW_LOW_THRESHOLD = -1 - self.BETWEEN_THRESHOLDS = -2 - assert low_threshold <= high_threshold - self.high_threshold = high_threshold - self.low_threshold = low_threshold - self.allow_low_quality_matches = allow_low_quality_matches - - def __call__(self, match_quality_matrix): - """ - Args: - match_quality_matrix (Tensor[float]): an MxN tensor, containing the - pairwise quality between M ground-truth elements and N predicted elements. - - Returns: - matches (Tensor[int64]): an N tensor where N[i] is a matched gt in - [0, M - 1] or a negative value indicating that prediction i could not - be matched. - """ - if match_quality_matrix.numel() == 0: - # empty targets or proposals not supported during training - if match_quality_matrix.shape[0] == 0: - raise ValueError( - "No ground-truth boxes available for one of the images " - "during training") - - raise ValueError( - "No proposal boxes available for one of the images " - "during training") - - # match_quality_matrix is M (gt) x N (predicted) - # Max over gt elements (dim 0) to find best gt candidate for each prediction - matched_vals, matches = match_quality_matrix.max(dim=0) - if self.allow_low_quality_matches: - all_matches = matches.clone() - else: - all_matches = None - - # Assign candidate matches with low quality to negative (unassigned) values - below_low_threshold = matched_vals < self.low_threshold - between_thresholds = (matched_vals >= self.low_threshold) & ( - matched_vals < self.high_threshold - ) - matches[below_low_threshold] = self.BELOW_LOW_THRESHOLD - matches[between_thresholds] = self.BETWEEN_THRESHOLDS - - if self.allow_low_quality_matches: - assert all_matches is not None - self.set_low_quality_matches_(matches, all_matches, match_quality_matrix) - - return matches - - def set_low_quality_matches_(self, matches, all_matches, match_quality_matrix): - """ - Produce additional matches for predictions that have only low-quality matches. - Specifically, for each ground-truth find the set of predictions that have - maximum overlap with it (including ties); for each prediction in that set, if - it is unmatched, then match it to the ground-truth with which it has the highest - quality value. - """ - # For each gt, find the prediction with which it has highest quality - highest_quality_foreach_gt, _ = match_quality_matrix.max(dim=1) - # Find highest quality match available, even if it is low, including ties - gt_pred_pairs_of_highest_quality = torch.where( - match_quality_matrix == highest_quality_foreach_gt[:, None] - ) - # Example gt_pred_pairs_of_highest_quality: - # tensor([[ 0, 39796], - # [ 1, 32055], - # [ 1, 32070], - # [ 2, 39190], - # [ 2, 40255], - # [ 3, 40390], - # [ 3, 41455], - # [ 4, 45470], - # [ 5, 45325], - # [ 5, 46390]]) - # Each row is a (gt index, prediction index) - # Note how gt items 1, 2, 3, and 5 each have two ties - - pred_inds_to_update = gt_pred_pairs_of_highest_quality[1] - matches[pred_inds_to_update] = all_matches[pred_inds_to_update] \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/openimages.py b/tinygrad/test/external/mlperf_retinanet/openimages.py deleted file mode 100644 index d77c99d7..00000000 --- a/tinygrad/test/external/mlperf_retinanet/openimages.py +++ /dev/null @@ -1,25 +0,0 @@ -from test.external.mlperf_retinanet.model.boxes import box_iou -from test.external.mlperf_retinanet.model.utils import Matcher - -import torch - -# This applies the filtering in https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/retinanet.py#L117 -# and https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/retinanet.py#L203 -# to match with tinygrad's dataloader implementation. -def postprocess_targets(targets, anchors): - proposal_matcher, matched_idxs = Matcher(0.5, 0.4, allow_low_quality_matches=True), [] - for anchors_per_image, targets_per_image in zip(anchors, targets): - if targets_per_image['boxes'].numel() == 0: - matched_idxs.append(torch.full((anchors_per_image.size(0),), -1, dtype=torch.int64, - device=anchors_per_image.device)) - continue - - match_quality_matrix = box_iou(targets_per_image['boxes'], anchors_per_image) - matched_idxs.append(proposal_matcher(match_quality_matrix)) - - for targets_per_image, matched_idxs_per_image in zip(targets, matched_idxs): - foreground_idxs_per_image = matched_idxs_per_image >= 0 - targets_per_image["boxes"] = targets_per_image["boxes"][matched_idxs_per_image[foreground_idxs_per_image]] - targets_per_image["labels"] = targets_per_image["labels"][matched_idxs_per_image[foreground_idxs_per_image]] - - return targets diff --git a/tinygrad/test/external/mlperf_retinanet/presets.py b/tinygrad/test/external/mlperf_retinanet/presets.py deleted file mode 100644 index fb918581..00000000 --- a/tinygrad/test/external/mlperf_retinanet/presets.py +++ /dev/null @@ -1,24 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/presets.py - -from test.external.mlperf_retinanet import transforms as T - -class DetectionPresetTrain: - def __init__(self, data_augmentation, hflip_prob=0.5, mean=(123., 117., 104.)): - if data_augmentation == 'hflip': - self.transforms = T.Compose([ - T.RandomHorizontalFlip(p=hflip_prob), - T.ToTensor(), - ]) - else: - raise ValueError(f'Unknown data augmentation policy "{data_augmentation}"') - - def __call__(self, img, target): - return self.transforms(img, target) - - -class DetectionPresetEval: - def __init__(self): - self.transforms = T.ToTensor() - - def __call__(self, img, target): - return self.transforms(img, target) \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_retinanet/transforms.py b/tinygrad/test/external/mlperf_retinanet/transforms.py deleted file mode 100644 index 0a35347d..00000000 --- a/tinygrad/test/external/mlperf_retinanet/transforms.py +++ /dev/null @@ -1,77 +0,0 @@ -# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/transforms.py - -import torch -import torchvision - -from torch import nn, Tensor -from torchvision.transforms import functional as F -from torchvision.transforms import transforms as T -from typing import List, Tuple, Dict, Optional - -from PIL import Image -Image.MAX_IMAGE_PIXELS = None -from typing import Any - -try: - import accimage -except ImportError: - accimage = None - -@torch.jit.unused -def _is_pil_image(img: Any) -> bool: - if accimage is not None: - return isinstance(img, (Image.Image, accimage.Image)) - else: - return isinstance(img, Image.Image) - -def get_image_size_tensor(img: Tensor) -> List[int]: - # Returns (w, h) of tensor image - torchvision.transforms._functional_tensor._assert_image_tensor(img) - return [img.shape[-1], img.shape[-2]] - -@torch.jit.unused -def get_image_size_pil(img: Any) -> List[int]: - if _is_pil_image(img): - return list(img.size) - raise TypeError("Unexpected type {}".format(type(img))) - -def get_image_size(img: Tensor) -> List[int]: - """Returns the size of an image as [width, height]. - Args: - img (PIL Image or Tensor): The image to be checked. - Returns: - List[int]: The image size. - """ - if isinstance(img, torch.Tensor): - return get_image_size_tensor(img) - - return get_image_size_pil(img) - -class Compose(object): - def __init__(self, transforms): - self.transforms = transforms - - def __call__(self, image, target): - for t in self.transforms: - image, target = t(image, target) - return image, target - - -class RandomHorizontalFlip(T.RandomHorizontalFlip): - def forward(self, image: Tensor, - target: Optional[Dict[str, Tensor]] = None) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: - if torch.rand(1) < self.p: - image = F.hflip(image) - if target is not None: - width, _ = get_image_size(image) - target["boxes"][:, [0, 2]] = width - target["boxes"][:, [2, 0]] - if "masks" in target: - target["masks"] = target["masks"].flip(-1) - return image, target - - -class ToTensor(nn.Module): - def forward(self, image: Tensor, - target: Optional[Dict[str, Tensor]] = None) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: - image = F.to_tensor(image) - return image, target \ No newline at end of file diff --git a/tinygrad/test/external/mlperf_unet3d/dice.py b/tinygrad/test/external/mlperf_unet3d/dice.py deleted file mode 100644 index fd236d2b..00000000 --- a/tinygrad/test/external/mlperf_unet3d/dice.py +++ /dev/null @@ -1,94 +0,0 @@ -# https://github.com/mlcommons/training/blob/master/image_segmentation/pytorch/model/losses.py - -import torch -import torch.nn as nn -import torch.nn.functional as F - - -class Dice: - def __init__(self, - to_onehot_y: bool = True, - to_onehot_x: bool = False, - use_softmax: bool = True, - use_argmax: bool = False, - include_background: bool = False, - layout: str = "NCDHW"): - self.include_background = include_background - self.to_onehot_y = to_onehot_y - self.to_onehot_x = to_onehot_x - self.use_softmax = use_softmax - self.use_argmax = use_argmax - self.smooth_nr = 1e-6 - self.smooth_dr = 1e-6 - self.layout = layout - - def __call__(self, prediction, target): - if self.layout == "NCDHW": - channel_axis = 1 - reduce_axis = list(range(2, len(prediction.shape))) - else: - channel_axis = -1 - reduce_axis = list(range(1, len(prediction.shape) - 1)) - num_pred_ch = prediction.shape[channel_axis] - - if self.use_softmax: - prediction = torch.softmax(prediction, dim=channel_axis) - elif self.use_argmax: - prediction = torch.argmax(prediction, dim=channel_axis) - - if self.to_onehot_y: - target = to_one_hot(target, self.layout, channel_axis) - - if self.to_onehot_x: - prediction = to_one_hot(prediction, self.layout, channel_axis) - - if not self.include_background: - assert num_pred_ch > 1, \ - f"To exclude background the prediction needs more than one channel. Got {num_pred_ch}." - if self.layout == "NCDHW": - target = target[:, 1:] - prediction = prediction[:, 1:] - else: - target = target[..., 1:] - prediction = prediction[..., 1:] - - assert (target.shape == prediction.shape), \ - f"Target and prediction shape do not match. Target: ({target.shape}), prediction: ({prediction.shape})." - - intersection = torch.sum(target * prediction, dim=reduce_axis) - target_sum = torch.sum(target, dim=reduce_axis) - prediction_sum = torch.sum(prediction, dim=reduce_axis) - - return (2.0 * intersection + self.smooth_nr) / (target_sum + prediction_sum + self.smooth_dr) - - -def to_one_hot(array, layout, channel_axis): - if len(array.shape) >= 5: - array = torch.squeeze(array, dim=channel_axis) - array = F.one_hot(array.long(), num_classes=3) - if layout == "NCDHW": - array = array.permute(0, 4, 1, 2, 3).float() - return array - - -class DiceCELoss(nn.Module): - def __init__(self, to_onehot_y, use_softmax, layout, include_background): - super(DiceCELoss, self).__init__() - self.dice = Dice(to_onehot_y=to_onehot_y, use_softmax=use_softmax, layout=layout, - include_background=include_background) - self.cross_entropy = nn.CrossEntropyLoss() - - def forward(self, y_pred, y_true): - cross_entropy = self.cross_entropy(y_pred, torch.squeeze(y_true, dim=1).long()) - dice = torch.mean(1.0 - self.dice(y_pred, y_true)) - return (dice + cross_entropy) / 2 - - -class DiceScore: - def __init__(self, to_onehot_y: bool = True, use_argmax: bool = True, layout: str = "NCDHW", - include_background: bool = False): - self.dice = Dice(to_onehot_y=to_onehot_y, to_onehot_x=True, use_softmax=False, - use_argmax=use_argmax, layout=layout, include_background=include_background) - - def __call__(self, y_pred, y_true): - return torch.mean(self.dice(y_pred, y_true), dim=0) diff --git a/tinygrad/test/external/mlperf_unet3d/kits19.py b/tinygrad/test/external/mlperf_unet3d/kits19.py deleted file mode 100644 index ac8a918a..00000000 --- a/tinygrad/test/external/mlperf_unet3d/kits19.py +++ /dev/null @@ -1,165 +0,0 @@ -# copied from https://github.com/mlcommons/training/blob/5c08ce57e7f582cc4558035d8324a2bf4c8ca225/image_segmentation/pytorch/data_loading/pytorch_loader.py - -import random -import numpy as np -import scipy.ndimage -from torch.utils.data import Dataset -from torchvision import transforms - - -def get_train_transforms(): - rand_flip = RandFlip() - cast = Cast(types=(np.float32, np.uint8)) - rand_scale = RandomBrightnessAugmentation(factor=0.3, prob=0.1) - rand_noise = GaussianNoise(mean=0.0, std=0.1, prob=0.1) - train_transforms = transforms.Compose([rand_flip, cast, rand_scale, rand_noise]) - return train_transforms - - -class RandBalancedCrop: - def __init__(self, patch_size, oversampling): - self.patch_size = patch_size - self.oversampling = oversampling - - def __call__(self, data): - image, label = data["image"], data["label"] - if random.random() < self.oversampling: - image, label, cords = self.rand_foreg_cropd(image, label) - else: - image, label, cords = self._rand_crop(image, label) - data.update({"image": image, "label": label}) - return data - - @staticmethod - def randrange(max_range): - return 0 if max_range == 0 else random.randrange(max_range) - - def get_cords(self, cord, idx): - return cord[idx], cord[idx] + self.patch_size[idx] - - def _rand_crop(self, image, label): - ranges = [s - p for s, p in zip(image.shape[1:], self.patch_size)] - cord = [self.randrange(x) for x in ranges] - low_x, high_x = self.get_cords(cord, 0) - low_y, high_y = self.get_cords(cord, 1) - low_z, high_z = self.get_cords(cord, 2) - image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] - label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] - return image, label, [low_x, high_x, low_y, high_y, low_z, high_z] - - def rand_foreg_cropd(self, image, label): - def adjust(foreg_slice, patch_size, label, idx): - diff = patch_size[idx - 1] - (foreg_slice[idx].stop - foreg_slice[idx].start) - sign = -1 if diff < 0 else 1 - diff = abs(diff) - ladj = self.randrange(diff) - hadj = diff - ladj - low = max(0, foreg_slice[idx].start - sign * ladj) - high = min(label.shape[idx], foreg_slice[idx].stop + sign * hadj) - diff = patch_size[idx - 1] - (high - low) - if diff > 0 and low == 0: - high += diff - elif diff > 0: - low -= diff - return low, high - - cl = np.random.choice(np.unique(label[label > 0])) - foreg_slices = scipy.ndimage.find_objects(scipy.ndimage.measurements.label(label==cl)[0]) - foreg_slices = [x for x in foreg_slices if x is not None] - slice_volumes = [np.prod([s.stop - s.start for s in sl]) for sl in foreg_slices] - slice_idx = np.argsort(slice_volumes)[-2:] - foreg_slices = [foreg_slices[i] for i in slice_idx] - if not foreg_slices: - return self._rand_crop(image, label) - foreg_slice = foreg_slices[random.randrange(len(foreg_slices))] - low_x, high_x = adjust(foreg_slice, self.patch_size, label, 1) - low_y, high_y = adjust(foreg_slice, self.patch_size, label, 2) - low_z, high_z = adjust(foreg_slice, self.patch_size, label, 3) - image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] - label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] - return image, label, [low_x, high_x, low_y, high_y, low_z, high_z] - - -class RandFlip: - def __init__(self): - self.axis = [1, 2, 3] - self.prob = 1 / len(self.axis) - - def flip(self, data, axis): - data["image"] = np.flip(data["image"], axis=axis).copy() - data["label"] = np.flip(data["label"], axis=axis).copy() - return data - - def __call__(self, data): - for axis in self.axis: - if random.random() < self.prob: - data = self.flip(data, axis) - return data - - -class Cast: - def __init__(self, types): - self.types = types - - def __call__(self, data): - data["image"] = data["image"].astype(self.types[0]) - data["label"] = data["label"].astype(self.types[1]) - return data - - -class RandomBrightnessAugmentation: - def __init__(self, factor, prob): - self.prob = prob - self.factor = factor - - def __call__(self, data): - image = data["image"] - if random.random() < self.prob: - factor = np.random.uniform(low=1.0-self.factor, high=1.0+self.factor, size=1) - image = (image * (1 + factor)).astype(image.dtype) - data.update({"image": image}) - return data - - -class GaussianNoise: - def __init__(self, mean, std, prob): - self.mean = mean - self.std = std - self.prob = prob - - def __call__(self, data): - image = data["image"] - if random.random() < self.prob: - scale = np.random.uniform(low=0.0, high=self.std) - noise = np.random.normal(loc=self.mean, scale=scale, size=image.shape).astype(image.dtype) - data.update({"image": image + noise}) - return data - - -class PytTrain(Dataset): - def __init__(self, images, labels, **kwargs): - self.images, self.labels = images, labels - self.train_transforms = get_train_transforms() - patch_size, oversampling = kwargs["patch_size"], kwargs["oversampling"] - self.patch_size = patch_size - self.rand_crop = RandBalancedCrop(patch_size=patch_size, oversampling=oversampling) - - def __len__(self): - return len(self.images) - - def __getitem__(self, idx): - data = {"image": np.load(self.images[idx]), "label": np.load(self.labels[idx])} - data = self.rand_crop(data) - data = self.train_transforms(data) - return data["image"], data["label"] - - -class PytVal(Dataset): - def __init__(self, images, labels): - self.images, self.labels = images, labels - - def __len__(self): - return len(self.images) - - def __getitem__(self, idx): - return np.load(self.images[idx]), np.load(self.labels[idx]) \ No newline at end of file diff --git a/tinygrad/test/external/openpilot/b1ab7897cbfa35981e1636fe551e4ce5.npy b/tinygrad/test/external/openpilot/b1ab7897cbfa35981e1636fe551e4ce5.npy deleted file mode 100644 index 2c87c44a..00000000 Binary files a/tinygrad/test/external/openpilot/b1ab7897cbfa35981e1636fe551e4ce5.npy and /dev/null differ diff --git a/tinygrad/test/external/process_replay/README.md b/tinygrad/test/external/process_replay/README.md deleted file mode 100644 index acb3fa54..00000000 --- a/tinygrad/test/external/process_replay/README.md +++ /dev/null @@ -1,19 +0,0 @@ -# Process replay tests - -Process replay is a tool for creating a diff of generated kernels between two commits. By default, process replay doesn't assert kernel diffs. - -Refactor and speedup PRs must enable the assert by including `[pr]` in the pull request title. - -Note that process replay [early stops when over 20% of kernels change, for speed.](https://github.com/tinygrad/tinygrad/pull/5480). - -## Running locally - -To run process replay locally: - -(optional: clear previous process replay runs with `test/external/process_replay/reset.py`) - -1. Run tests with `CAPTURE_PROCESS_REPLAY=1` in your branch. This will pickle process inputs to CACHEDB. -2. Checkout master -3. Run `test/external/process_replay/process_replay.py` - -For reference, see `test/external/process_replay/local.sh`. diff --git a/tinygrad/test/external/process_replay/local.sh b/tinygrad/test/external/process_replay/local.sh deleted file mode 100755 index 0d799733..00000000 --- a/tinygrad/test/external/process_replay/local.sh +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash - -set -e -HEAD=$(git rev-parse --abbrev-ref HEAD) -python test/external/process_replay/reset.py -CAPTURE_PROCESS_REPLAY=1 python test/test_ops.py TestOps.test_add -git checkout master -git checkout $HEAD -- test/external/process_replay/process_replay.py -ASSERT_PROCESS_REPLAY=${ASSERT_PROCESS_REPLAY:-1} python test/external/process_replay/process_replay.py -git checkout $HEAD diff --git a/tinygrad/test/external/process_replay/process_replay.py b/tinygrad/test/external/process_replay/process_replay.py deleted file mode 100755 index 1ff2873f..00000000 --- a/tinygrad/test/external/process_replay/process_replay.py +++ /dev/null @@ -1,109 +0,0 @@ -#!/usr/bin/env python3 -# compare kernels created by HEAD against master -import os, multiprocessing, logging, pickle, sqlite3, difflib, warnings, itertools -from typing import Callable, Any -from tinygrad.helpers import VERSION, Context, ContextVar, colored, db_connection, getenv, tqdm, to_function_name -from tinygrad.engine.grouper import get_kernelize_map -from tinygrad.codegen.kernel import Kernel -from tinygrad.uop.ops import UOp, Ops - -# *** process replay settings - -# internal -PAGE_SIZE = getenv("PAGE_SIZE", 100) -REF = os.getenv("GITHUB_REF_NAME", "") -MAX_DIFF_PCT = getenv("PROCESS_REPLAY_MAX_DIFF_PCT", 20) -TABLE_NAME = f"process_replay_{VERSION}" -os.environ["CAPTURE_PROCESS_REPLAY"] = "0" -early_stop = multiprocessing.Event() -logging.basicConfig(level=logging.INFO, format="%(message)s") -MAX_LINES = 500 -def trunc_log(x): - if len(lines:=repr(x).splitlines()) > MAX_LINES: lines = lines[:MAX_LINES]+[f"WARN: truncated string with {len(lines)} lines"] - logging.info("\n".join(lines)) - -# user config -ASSERT_DIFF = int((flag:="[pr]") in os.getenv("COMMIT_MESSAGE", flag) or flag in os.getenv("PR_TITLE", flag)) -if not getenv("ASSERT_PROCESS_REPLAY", 1): ASSERT_DIFF = 0 -SKIP_PROCESS_REPLAY = (k:="[skip_process_replay]") in os.getenv("COMMIT_MESSAGE", "") or k in os.getenv("PR_TITLE", "") -if REF == "master": SKIP_PROCESS_REPLAY = True -class ProcessReplayWarning(Warning): pass - -# *** replay the function and convert return values to string - -def replay_kernelize(ret:dict[UOp, UOp], big_sink:UOp) -> tuple[str, str, tuple[Any, ...]]: - UOp.unique_num = itertools.count(max([u.arg for u in big_sink.toposort() if u.op is Ops.UNIQUE], default=0)+1) - new_sink = big_sink.substitute(get_kernelize_map(big_sink)) - def to_str(ret:UOp) -> str: - asts = [repr(u.arg.ast) for u in ret.toposort() if u.op is Ops.KERNEL] - return "\n".join([f"{len(asts)} kernels", *asts]) - return to_str(new_sink), to_str(ret[big_sink]), (big_sink,) - -def replay_linearize(k:Kernel, _:Kernel, name_override=None, ast_transform=None) -> tuple[str, str, tuple[Any, ...]]: - # create a copy because the Kernel class contains optimization parameters (other than applied_opts) in its state - # this should be made fully functional. It's fine for process replay since copy returns a fresh instance - k2 = k.copy() - k2.linearize(name_override=name_override or to_function_name(k.name), ast_transform=ast_transform) - def to_str(ret:Kernel) -> str: - try: return ret.opts.render(ret.uops) - except NotImplementedError: return "" # NULL backend doesn't have a renderer, this is okay - return to_str(k2), to_str(k), (k.ast, k.opts, k.applied_opts) - -replayers: dict[str, Callable[..., tuple[str, str, tuple[Any, ...]]]] = {"get_kernelize_map":replay_kernelize, "linearize":replay_linearize} - -# *** run replayers on captured rows and print diffs - -def diff(offset:int) -> None: - if ASSERT_DIFF: warnings.filterwarnings("error", category=ProcessReplayWarning) - if early_stop.is_set(): return None - conn = db_connection() - cur = conn.cursor() - cur.execute(f"SELECT val FROM '{TABLE_NAME}' LIMIT ? OFFSET ?", (PAGE_SIZE, offset)) - changed = 0 - for row in cur.fetchall(): - if changed > MAX_DIFF_PCT: - warnings.warn(f"detected changes in over {MAX_DIFF_PCT}%. skipping further diff generation.", ProcessReplayWarning) - early_stop.set() - break - try: - name, args, kwargs, ctx_vals, loc, ret = pickle.loads(row[0]) - ctx_vars = {k:v.value for k,v in ctx_vals.items() if k != "DEBUG" and (var:=ContextVar._cache.get(k)) is not None and var.value != v.value} - if (replayer:=replayers.get(name)) is None: continue - with Context(**ctx_vars): good, compare, metadata = replayer(ret, *args, **kwargs) - if good != compare: - for m in metadata: trunc_log(m) - logging.info(loc) - for line in difflib.unified_diff(good.splitlines(), compare.splitlines()): - logging.info(colored(line, "red" if line.startswith("-") else "green" if line.startswith("+") else None)) - if ctx_vars: logging.info(ctx_vars) - warnings.warn("PROCESS REPLAY DETECTED CHANGE", ProcessReplayWarning) - except Exception as e: - changed += 1 - warnings.warn(e, ProcessReplayWarning) - conn.commit() - cur.close() - -# *** main loop - -if __name__ == "__main__": - if SKIP_PROCESS_REPLAY: - logging.info("skipping process replay.") - exit(0) - - conn = db_connection() - cur = conn.cursor() - try: row_count = cur.execute(f"select count(*) from '{TABLE_NAME}'").fetchone()[0] - except sqlite3.OperationalError: - warnings.warn(f"{TABLE_NAME} isn't accessible in master, did DB_VERSION change?", ProcessReplayWarning) - exit(int(ASSERT_DIFF)) - finally: - conn.commit() - cur.close() - - logging.info(f"running process replay with {ASSERT_DIFF=}") - with multiprocessing.get_context("spawn").Pool(multiprocessing.cpu_count()) as pool: - inputs = list(range(0, row_count, PAGE_SIZE)) - list(tqdm(pool.imap_unordered(diff, inputs), total=len(inputs))) - pool.close() - pool.join() - pool.terminate() diff --git a/tinygrad/test/external/process_replay/reset.py b/tinygrad/test/external/process_replay/reset.py deleted file mode 100755 index c40b6d09..00000000 --- a/tinygrad/test/external/process_replay/reset.py +++ /dev/null @@ -1,4 +0,0 @@ -#!/usr/bin/env python3 -from tinygrad.helpers import db_connection, VERSION -cur = db_connection() -cur.execute(f"drop table if exists process_replay_{VERSION}") diff --git a/tinygrad/test/external/speed_beam_v_hcopt.py b/tinygrad/test/external/speed_beam_v_hcopt.py deleted file mode 100644 index 1bd107f6..00000000 --- a/tinygrad/test/external/speed_beam_v_hcopt.py +++ /dev/null @@ -1,41 +0,0 @@ -from tinygrad import Device -from tinygrad.helpers import getenv, DEBUG, BEAM -from tinygrad.engine.search import beam_search, bufs_from_lin -from tinygrad.codegen.heuristic import hand_coded_optimizations -from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer - -if __name__ == "__main__": - filter_reduce = bool(getenv("FILTER_REDUCE")) - ast_strs = load_worlds(filter_reduce=filter_reduce, filter_novariable=True) - dev = Device[Device.DEFAULT] - - test_n = getenv("TEST_N", 10) - single = getenv("NUM", -1) - if single != -1: ast_strs = ast_strs[single:single+1] - - beam_won, tested = 0, 0 - - for num, ast in enumerate(ast_strs[:test_n]): - def new_lin(): return ast_str_to_lin(ast, opts=dev.renderer) - - k = new_lin() - - if not (used_tensor_cores:=k.apply_tensor_cores(getenv("TC", 1))): k.apply_opts(hand_coded_optimizations(k)) - - assert BEAM > 0 - - lins = [(("tc" if used_tensor_cores else "hc"), k)] - if used_tensor_cores: - lins.append(("hc", new_lin())) - lins[-1][1].apply_opts(hand_coded_optimizations(lins[-1][1])) - kb = new_lin() - test_rawbuffers = bufs_from_lin(kb) # allocate scratch buffers for optimization - lins.append((f"beam{BEAM.value}", beam_search(kb, test_rawbuffers, BEAM.value, bool(getenv("BEAM_ESTIMATE", 1))))) - timed = sorted([(nm, tk, time_linearizer(tk, test_rawbuffers, allow_test_size=False, clear_l2=True)) for nm, tk in lins], key=lambda x: x[2]) - if DEBUG >= 1: print(" < ".join(f"{nm:6s} : {lin.colored_shape(30, dense=True)} : {tm*1e6:8.2f} us" for nm, lin, tm in timed)) - - tested += 1 - if timed[0][0].startswith("beam"): - beam_won += 1 - - print(f"{beam_won=} / {tested=} = {beam_won/tested:.3f}") \ No newline at end of file diff --git a/tinygrad/test/external/speed_compare_amd_am.py b/tinygrad/test/external/speed_compare_amd_am.py deleted file mode 100644 index 760833d4..00000000 --- a/tinygrad/test/external/speed_compare_amd_am.py +++ /dev/null @@ -1,157 +0,0 @@ -from tinygrad import Device, dtypes -from tinygrad.helpers import getenv, colorize_float, DEBUG -from extra.optimization.helpers import load_worlds, ast_str_to_lin -from test.external.fuzz_linearizer import get_fuzz_rawbufs -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.engine.search import bufs_from_lin -from tinygrad.engine.realize import CompiledRunner -from tinygrad.tensor import _to_np_dtype -from tinygrad.runtime.ops_amd import AMDDevice -from contextlib import contextmanager -import numpy as np -import os, random, statistics - -am_signal_pages, am_signal_pool, am_devices = [], [], [] -amd_signal_pages, amd_signal_pool, amd_devices = [], [], [] - -def rebind_vfio(pcibus="0000:44:00.0"): - print("rebind ", pcibus) - os.system("sudo rmmod amdgpu") - os.system("sudo modprobe vfio-pci") - - base = f"/sys/bus/pci/devices/{pcibus}" - if os.path.exists(f"{base}/driver"): - with open(f"{base}/driver/unbind", "w") as f: f.write(pcibus) - with open(f"{base}/driver_override", "w") as f: f.write("vfio-pci") - with open("/sys/bus/pci/drivers_probe", "w") as f: f.write(pcibus) - - os.system("sudo modprobe amdgpu") - os.system("rocm-smi --setprofile compute") - os.system("rocm-smi --setperflevel high") - -@contextmanager -def run_amd(): - global amd_signal_pages, amd_signal_pool, amd_devices - AMDDevice.driverless = False - AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = amd_signal_pages, amd_signal_pool, amd_devices - yield - amd_signal_pages, amd_signal_pool, amd_devices = AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices - AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = [], [], [] - -@contextmanager -def run_am(): - global am_signal_pages, am_signal_pool, am_devices - AMDDevice.driverless = True - AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = am_signal_pages, am_signal_pool, am_devices - yield - am_signal_pages, am_signal_pool, am_devices = AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices - AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = [], [], [] - -if __name__ == "__main__": - CHECK_CPU = getenv("CHECK_CPU", 0) - SEED = getenv("SEED", 42) - CNT = getenv("CNT", 7) - random.seed(SEED) - np.random.seed(SEED) - - # TODO: NUM=780 is super slow - # NUM=1907 is broken on AMD and AM have some mismatches (0 vs 1) - # kfd feels so bad when taking gpu out while it's running... Need hacks to rebind it before running. - rebind_vfio(pcibus="0000:44:00.0") - - ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) - - with run_am(): - amdev = Device["AMD:1"] - - with run_amd(): - amddev = Device["AMD"] - - if CHECK_CPU: cpudev = Device["CPU"] - - single = getenv("NUM", -1) - if single != -1: ast_strs = ast_strs[single:single+1] - - average_tm_amd, average_tm_am = 0, 0 - for num,ast in enumerate(ast_strs): - with run_amd(): - amdlin = ast_str_to_lin(ast, opts=amddev.renderer) - amdlin.apply_opts(hand_coded_optimizations(amdlin)) - has_bf16 = any(b.dtype == dtypes.bfloat16 for b in amdlin.membufs) - - amd_prg = CompiledRunner(amdlin.to_program()) - amdbufs = bufs_from_lin(amdlin) - test_amdbufs = get_fuzz_rawbufs(amdlin) if not has_bf16 else amdbufs - if not has_bf16: contents = [buf.as_buffer() for buf in test_amdbufs] - - with run_am(): - rdr = amdev.renderer - rdr.device = "AMD:1" - amlin = ast_str_to_lin(ast, opts=amdev.renderer) - amlin.apply_opts(hand_coded_optimizations(amlin)) - am_prg = CompiledRunner(amlin.to_program()) - ambufs = bufs_from_lin(amlin) - test_ambufs = get_fuzz_rawbufs(amlin) if not has_bf16 else ambufs - if not has_bf16: - for i,rawbuf in enumerate(test_ambufs): rawbuf.copyin(contents[i]) - - if CHECK_CPU: - cpu_rdr = cpudev.renderer - cpu_rdr.device = "CPU" - cpulin = ast_str_to_lin(ast, opts=cpu_rdr) - cpulin.apply_opts(hand_coded_optimizations(cpulin)) - cpu_prg = CompiledRunner(cpulin.to_program()) - cpubufs = bufs_from_lin(cpulin) - test_cpubufs = get_fuzz_rawbufs(cpulin) if not has_bf16 else ambufs - if not has_bf16: - for i,rawbuf in enumerate(test_cpubufs): rawbuf.copyin(contents[i]) - - # warmup - tm_amd, tm_am, failed = [], [], False - with run_amd(): - try: - amd_prg(test_amdbufs, {}, wait=True) - for i in range(CNT): tm_amd.append(amd_prg(amdbufs, {}, wait=True)) - except RuntimeError: - print("AMD FAILED") - tm_amd = [1e9] - failed = True - - with run_am(): - try: - am_prg(test_ambufs, {}, wait=True) - for i in range(CNT): tm_am.append(am_prg(ambufs, {}, wait=True)) - except RuntimeError: - print("AM FAILED") - tm_am = [1e9] - failed = True - - if CHECK_CPU: - cpu_prg(test_cpubufs, {}, wait=True) - for i in range(1): cpu_prg(cpubufs, {}, wait=True) - - if not failed and not has_bf16: - with run_amd(): - curesult = np.frombuffer(test_amdbufs[0].as_buffer(), _to_np_dtype(test_amdbufs[0].dtype)) - - with run_am(): - amresult = np.frombuffer(test_ambufs[0].as_buffer(), _to_np_dtype(test_ambufs[0].dtype)) - - if CHECK_CPU: - cpuresult = np.frombuffer(test_cpubufs[0].as_buffer(), _to_np_dtype(test_cpubufs[0].dtype)) - np.testing.assert_allclose(amresult, cpuresult, rtol=1e-2, atol=1e-2) - np.testing.assert_allclose(curesult, cpuresult, rtol=1e-2, atol=1e-2) - - try: - np.testing.assert_allclose(curesult, amresult, rtol=1e-2, atol=1e-2) - except AssertionError as e: - print("AM and AMD results do not match") - print(e) - - bam = statistics.median(tm_am) - bamd = statistics.median(tm_amd) - average_tm_amd += bamd - average_tm_am += bam - ratio = bam/bamd - print(f"{average_tm_am/average_tm_amd:5.2f}x -- {num:4d} {colorize_float(ratio)} {bam*1e6:7.2f} vs {bamd*1e6:7.2f} us", amlin.name) - if DEBUG > 3 and ratio > 1.04: print(f"AM slower {ratio}", amlin.ast, amlin.applied_opts) diff --git a/tinygrad/test/external/speed_compare_cuda_nv.py b/tinygrad/test/external/speed_compare_cuda_nv.py deleted file mode 100644 index 3ce1a74a..00000000 --- a/tinygrad/test/external/speed_compare_cuda_nv.py +++ /dev/null @@ -1,69 +0,0 @@ -from tinygrad import Device, dtypes -from tinygrad.helpers import getenv, colorize_float -from extra.optimization.helpers import load_worlds, ast_str_to_lin -from test.external.fuzz_linearizer import get_fuzz_rawbufs -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.engine.search import bufs_from_lin -from tinygrad.engine.realize import CompiledRunner -from tinygrad.tensor import _to_np_dtype -import numpy as np - -if __name__ == "__main__": - ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) - cudev = Device["CUDA"] - nvdev = Device["NV"] - - # NUM=112 python3 test/external/speed_compare_cuda_nv.py - - single = getenv("NUM", -1) - if single != -1: ast_strs = ast_strs[single:single+1] - - average_tm_cuda, average_tm_nv = 0, 0 - for num,ast in enumerate(ast_strs): - # cuda compile - culin = ast_str_to_lin(ast, opts=cudev.renderer) - culin.apply_opts(hand_coded_optimizations(culin)) - has_bf16 = any(b.dtype == dtypes.bfloat16 for b in culin.membufs) - - cuda_prg = CompiledRunner(culin.to_program()) - cubufs = bufs_from_lin(culin) - test_cubufs = get_fuzz_rawbufs(culin) if not has_bf16 else cubufs - - rdr = nvdev.renderer - rdr.device = "NV" - nvlin = ast_str_to_lin(ast, opts=rdr) - nvlin.apply_opts(hand_coded_optimizations(nvlin)) - nv_prg = CompiledRunner(nvlin.to_program()) - nvbufs = bufs_from_lin(nvlin) - test_nvbufs = get_fuzz_rawbufs(nvlin) if not has_bf16 else nvbufs - if not has_bf16: - for i,rawbuf in enumerate(test_nvbufs): rawbuf.copyin(test_cubufs[i].as_buffer()) - - # warmup - tm_cuda, tm_nv, failed = [], [], False - try: - cuda_prg(test_cubufs, {}, wait=True) - for i in range(5): tm_cuda.append(cuda_prg(cubufs, {}, wait=True)) - except RuntimeError: - print("CUDA FAILED") - tm_cuda = [1e9] - failed = True - - try: - nv_prg(test_nvbufs, {}, wait=True) - for i in range(5): tm_nv.append(nv_prg(nvbufs, {}, wait=True)) - except RuntimeError: - print("NV FAILED") - tm_nv = [1e9] - failed = True - - if not failed and not has_bf16: - curesult = np.frombuffer(test_cubufs[0].as_buffer(), _to_np_dtype(test_cubufs[0].dtype)) - nvresult = np.frombuffer(test_nvbufs[0].as_buffer(), _to_np_dtype(test_nvbufs[0].dtype)) - np.testing.assert_allclose(curesult, nvresult, rtol=1e-2, atol=1e-2) - - average_tm_cuda += min(tm_cuda) - average_tm_nv += min(tm_nv) - ratio = min(tm_nv)/min(tm_cuda) - print(f"{average_tm_nv/average_tm_cuda:5.2f}x -- {num:4d} {colorize_float(ratio)} {min(tm_nv)*1e6:7.2f} us", nvlin.name) - if ratio > 1.04: print(f"NV slower {ratio}", nvlin.ast, nvlin.applied_opts) diff --git a/tinygrad/test/external/speed_compare_cuda_ptx.py b/tinygrad/test/external/speed_compare_cuda_ptx.py deleted file mode 100644 index 32b586a1..00000000 --- a/tinygrad/test/external/speed_compare_cuda_ptx.py +++ /dev/null @@ -1,61 +0,0 @@ -import itertools -from tinygrad import Device -from tinygrad.engine.realize import CompiledRunner -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.helpers import getenv, colorize_float -from extra.optimization.helpers import load_worlds, ast_str_to_lin -from tinygrad.engine.search import bufs_from_lin -from tinygrad.runtime.ops_cuda import PTXCompiler, PTXRenderer, CUDACompiler - -if __name__ == "__main__": - ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) - # no bfloat16 for ptx at the moment - ast_strs = [x for x in ast_strs if "dtypes.bfloat16" not in x] - dev = Device["CUDA"] - ptx = PTXRenderer(dev.arch) - - # NUM=112 python3 test/external/speed_compare_cuda_ptx.py - - single = getenv("NUM", -1) - if single != -1: ast_strs = ast_strs[single:single+1] - - average_tm_cuda, average_tm_ptx = 0, 0 - for num,ast in enumerate(ast_strs): - # cuda compile - dev.compiler = CUDACompiler(dev.arch) - lin = ast_str_to_lin(ast, opts=dev.renderer) - lin.apply_opts(hand_coded_optimizations(lin)) - cuda_prg = CompiledRunner(lin.to_program()) - - bufs = bufs_from_lin(lin) - - # ptx compile - dev.compiler = PTXCompiler(dev.arch) - lin = ast_str_to_lin(ast, opts=ptx) - lin.apply_opts(hand_coded_optimizations(lin)) - lin.linearize() - ptx_prg = CompiledRunner(lin.to_program()) - - # warmup - try: - cuda_prg(bufs, {}, wait=True) - except RuntimeError: - print("cuda failed ast:", num) - continue - ptx_prg(bufs, {}, wait=True) - - tm_cuda, tm_ptx = [], [] - for i in range(5): - tm_cuda.append(cuda_prg(bufs, {}, wait=True)) - tm_ptx.append(ptx_prg(bufs, {}, wait=True)) - average_tm_cuda += min(tm_cuda) - average_tm_ptx += min(tm_ptx) - ratio = min(tm_ptx)/min(tm_cuda) - print(f"{average_tm_ptx/average_tm_cuda:5.2f}x -- {num:4d} {colorize_float(ratio)} {min(tm_ptx)*1e6:7.2f} us", lin.name) - if ratio > 1.5: - def fix(x): return x.replace('\t', ' ').strip() - ll1, ll2 = cuda_prg.lib.decode().split('\n'), ptx_prg.lib.decode().split('\n') - if single != -1: - for ln, (l1, l2) in enumerate(itertools.zip_longest(ll1, ll2, fillvalue='')): - print(f"{ln:5d} | {fix(l1):80s} | {fix(l2):80s}") - print(len(ll1), len(ll2), "RATIO", ratio, "us", min(tm_ptx)*1e6) diff --git a/tinygrad/test/external/speed_v_theoretical.py b/tinygrad/test/external/speed_v_theoretical.py deleted file mode 100644 index d02f87fa..00000000 --- a/tinygrad/test/external/speed_v_theoretical.py +++ /dev/null @@ -1,101 +0,0 @@ -import unittest -from tinygrad import Tensor, TinyJit, Device -from tinygrad.helpers import Context, DEBUG, GlobalCounters -from tinygrad.nn import Conv2d -from tinygrad.nn.state import get_parameters - -class TestKernelSpeed(unittest.TestCase): - def _get_tensor(self, *shape:int): - with Context(BEAM=0, DEBUG=0): - # TODO: randn is 20% faster than rand for gemv - return Tensor.randn(shape, dtype="half").realize() - - def _compare(self, tm, tflops, gbs, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): - if DEBUG >= 1: - print(f"{tm=:.6f}") - print(f"{tflops=:.6f}") - print(f"{gbs=:.3f}") - - if Device.DEFAULT == "NV": - if nv_tflops is not None: - if DEBUG >=1: print(f"tflop/s target: {nv_tflops}") - self.assertGreater(tflops, nv_tflops) - if nv_gbs is not None: - if DEBUG >=1: print(f"gb/s target: {nv_gbs}") - self.assertGreater(gbs, nv_gbs) - - if Device.DEFAULT == "AMD": - if amd_tflops is not None: - if DEBUG >=1: print(f"tflop/s target: {amd_tflops}") - self.assertGreater(tflops, amd_tflops) - if amd_gbs is not None: - if DEBUG >=1: print(f"gb/s target: {amd_gbs}") - self.assertGreater(gbs, amd_gbs) - - def _test_matmul(self, M, K=None, N=None, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): - # (MxK) @ (KxN) - @TinyJit - def f(a, b) -> Tensor: return (a @ b).realize() - - if N is None: N = M - if K is None: K = M - tms = [] - with Context(BEAM=3): - for i in range(10): - a = self._get_tensor(M, K) - b = self._get_tensor(K, N) - if i >= 3: - GlobalCounters.time_sum_s = 0 - with Context(DEBUG=max(DEBUG.value, 2)): c = f(a, b) - tms.append(GlobalCounters.time_sum_s) - else: - c = f(a, b) - - ops = 2 * M * N * K - mems = a.dtype.itemsize * M * K + b.dtype.itemsize * K * N + c.dtype.itemsize * M * N - tm = min(tms) - tflops = ops / tm / 1e12 - gbs = mems / tm / 1e9 - self._compare(tm, tflops, gbs, nv_tflops, nv_gbs, amd_tflops, amd_gbs) - - def _test_conv_3x3(self, BS, CIN, COUT, H, W, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): - @TinyJit - def f(conv, x) -> Tensor: return conv(x).realize() - tms = [] - K = 3 - with Context(BEAM=0, DEBUG=0): - conv = Conv2d(CIN, COUT, K, padding=1) - Tensor.realize(*get_parameters(conv)) - - with Context(BEAM=2): - for i in range(10): - x = self._get_tensor(BS, CIN, H, W) - if i >= 3: - GlobalCounters.time_sum_s = 0 - with Context(DEBUG=max(DEBUG.value, 2)): _c = f(conv, x) - tms.append(GlobalCounters.time_sum_s) - else: - _c = f(conv, x) - - # naive algo - ops = 2 * BS * CIN * COUT * K * K * H * W - mems = x.nbytes() + conv.weight.nbytes() + conv.bias.nbytes() + _c.nbytes() - tm = min(tms) - tflops = ops / tm / 1e12 - gbs = mems / tm / 1e9 - self._compare(tm, tflops, gbs, nv_tflops, nv_gbs, amd_tflops, amd_gbs) - - # NOTE: tiny7 was slower than tiny12 - # TODO: why are convs so slow?!? - def test_conv_3x3_256_32_32_256_256(self): self._test_conv_3x3(256, 32, 32, 256, 256, nv_tflops=27, amd_tflops=20) - - # theoretical is nv_tflops=165, amd_tflops=123 - def test_gemm_4096(self): self._test_matmul(4096, nv_tflops=115, amd_tflops=65) - def test_gemm_8192(self): self._test_matmul(8192, nv_tflops=125, amd_tflops=65) - - # theoretical is nv_gbs=1008, amd_gbs=960 - def test_gemv_16384_4096(self): self._test_matmul(16384, 4096, 1, nv_gbs=840, amd_gbs=750) - def test_gemv_4096_16384(self): self._test_matmul(4096, 16384, 1, nv_gbs=830, amd_gbs=750) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/external/verify_kernel.py b/tinygrad/test/external/verify_kernel.py deleted file mode 100644 index 55ebb684..00000000 --- a/tinygrad/test/external/verify_kernel.py +++ /dev/null @@ -1,78 +0,0 @@ -import argparse -from collections import defaultdict -from extra.optimization.helpers import kern_str_to_lin, time_linearizer -from test.external.fuzz_linearizer import compare_linearizer -from tinygrad.helpers import colored -from tinygrad.codegen.kernel import Kernel - -# Use this with the LOGKERNS options to verify that all executed kernels are valid and evaluate to the same ground truth results - -# Example for GPT2: -# 1) Run the model to log all kernels: `PYTHONPATH=. LOGKERNS=/tmp/gpt2_kerns.txt JIT=1 HALF=1 BEAM=2 CACHELEVEL=0 python3 examples/gpt2.py --count 10 --temperature 0 --timing` # noqa: E501 -# 2) Validate the kernel correctness: `PYTHONPATH=. python3 ./test/external/verify_kernel.py --file /tmp/gpt2_kerns.txt` - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Verify the correctness of one or more kernel", formatter_class=argparse.ArgumentDefaultsHelpFormatter) # noqa: E501 - parser.add_argument("--kernel", type=str, default=None, help="a string of a tuple of (ast, applied_opts,)") - parser.add_argument("--file", type=str, default=None, help="a file containing a tuple of ast and applied_opts, one per line") - parser.add_argument("--pkl", type=str, default=None, help="a pickle file containing a single tuple of ast and applied_opts") - parser.add_argument("--rtol", type=float, default=1e-2, help="relative tolerance for numerical comparison") - parser.add_argument("--atol", type=float, default=1e-2, help="absolute tolerance for numerical comparison") - parser.add_argument("--timing", action='store_true', help="show final timing for the kernel") - parser.add_argument("--expected-failures", type=int, default=0, help="the number of expected failed kernels") - args = parser.parse_args() - - if args.kernel is not None: - print("loading kernel from args") - test_lins = [kern_str_to_lin(args.kernel)] - elif args.file is not None: - print(f"loading kernel from file '{args.file}'") - with open(args.file, 'r') as file: - kern_strs = file.readlines() - test_lins = [kern_str_to_lin(kern_str) for kern_str in kern_strs] - elif args.pkl is not None: - print(f"loading kernel from pickle file '{args.file}'") - import pickle - with open(args.pkl, 'rb') as file: - (ast, applied_opts,) = pickle.load(file) - lin = Kernel(ast) - lin.apply_opts(applied_opts) - test_lins = [lin] - - else: - raise RuntimeError("no kernel specified; use --kernel, --file, or --pkl options") - - print(f"verifying {len(test_lins)} kernels") - - failed_ids = [] - failures = defaultdict(list) - for i, test_lin in enumerate(test_lins): - print(f"testing kernel {i}") - print(test_lin.ast) - print(test_lin.applied_opts) - unoptimized_lin = Kernel(test_lin.ast) - print(f"{unoptimized_lin.colored_shape()} -> {test_lin.colored_shape()}") - (msg,rb,vv,gt) = compare_linearizer(test_lin, None, None, None, rtol=args.rtol, atol=args.atol) - if msg != "PASS": - failed_ids.append(i) - failures[msg].append((test_lin.ast, test_lin.applied_opts)) - if args.timing: - tm = time_linearizer(test_lin, rb, allow_test_size=False, cnt=10) - print(f"final time {tm*1e6:9.0f} us") - - for msg, errors in failures.items(): - for i, (ast, opts) in enumerate(errors): - print(f"{msg} {i} AST: {ast}") - print(f"{msg} {i} OPTS: {opts}\n") - - print(f"tested {len(test_lins)} kernels") - if failures: - print(f"{failed_ids=}") - for msg, errors in failures.items(): - print(f"{msg}: {len(errors)}") - if len(failed_ids) == args.expected_failures: - print(colored(f"{len(failed_ids)} failed as expected", "yellow")) - if len(failed_ids) != args.expected_failures: - raise RuntimeError(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}") - else: - print(colored("all passed", "green")) diff --git a/tinygrad/test/helpers.py b/tinygrad/test/helpers.py deleted file mode 100644 index 07fe61b4..00000000 --- a/tinygrad/test/helpers.py +++ /dev/null @@ -1,72 +0,0 @@ -import time, struct -from typing import Any, Callable, Optional -import numpy as np -from tinygrad import Tensor, dtypes, Device -from tinygrad.uop.ops import UOp, Ops, sint, graph_rewrite -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.tensor import _to_np_dtype -from tinygrad.engine.realize import Runner -from tinygrad.engine.grouper import view_left -from tinygrad.dtype import ConstType, DType -from tinygrad.nn.state import get_parameters -from tinygrad.helpers import T, unwrap, CI -from tinygrad.codegen import full_rewrite -from tinygrad.runtime.ops_python import PythonProgram, PythonRenderer, PythonCompiler - -def derandomize_model(model): - for p in get_parameters(model): - p.replace(Tensor.empty(p.shape, device=p.device, dtype=p.dtype)) - p.realize() - -def assert_jit_cache_len(fxn, expected_len): - if not fxn.jit_cache: - assert expected_len == 0, expected_len - return - # until we have a better way of typing the prg in ExecItem - if issubclass(type(fxn.jit_cache[0].prg), Runner) and not type(fxn.jit_cache[0].prg).__name__.endswith('Graph'): - assert len(fxn.jit_cache) == expected_len, f"expected {expected_len}, got {len(fxn.jit_cache)}" - else: - assert len(fxn.jit_cache) == 1, len(fxn.jit_cache) - # until we have a better way of typing the prg in ExecItem - assert type(fxn.jit_cache[0].prg).__name__.endswith('Graph') - assert len(fxn.jit_cache[0].prg.jit_cache) == expected_len - -def rand_for_dtype(dt:DType, size:int): - if dtypes.is_unsigned(dt): - return np.random.randint(0, 100, size=size, dtype=_to_np_dtype(dt)) - elif dtypes.is_int(dt): - return np.random.randint(-100, 100, size=size, dtype=_to_np_dtype(dt)) - elif dt == dtypes.bool: - return np.random.choice([True, False], size=size) - return np.random.uniform(-10, 10, size=size).astype(_to_np_dtype(dt)) - -def ast_const(dtype:DType, val:ConstType, shape:tuple[sint, ...]=(), st:Optional[ShapeTracker]=None, st_src:Optional[tuple[UOp]]=None) -> UOp: - if st_src is None: - st_src = (st.to_uop() if st is not None else ShapeTracker.from_shape(()).reshape((1,)*len(shape)).expand(shape).to_uop(),) - st = unwrap(st_src[0].st) - if all(v.mask is None for v in st.views): return UOp.const(dtype, val).replace(src=(st.to_uop(),)) - return graph_rewrite(UOp.const(dtype, val).view(st).valid(), view_left) - -def timeit(fxn:Callable[..., T], *args, **kwargs) -> tuple[T, float]: - st = time.perf_counter_ns() - ret = fxn(*args, **kwargs) - return ret, (time.perf_counter_ns()-st)*1e-6 - -def eval_uop(uop:UOp, inputs:list[tuple[DType, list[Any]]]|None=None): - allocator = Device['PYTHON'].allocator - bufs = [] - for buf_dt, data in inputs or []: - bufs.append(buf:=allocator.alloc(len(data) * buf_dt.itemsize)) - allocator._copyin(buf, memoryview(struct.pack(str(len(data)) + buf_dt.fmt, *data))) - g = UOp(Ops.DEFINE_GLOBAL, uop.dtype.ptr(), arg=0, src=()) - lst = full_rewrite(UOp.store(g.index(UOp.const(dtypes.int, 0)), uop).sink(), PythonRenderer) - prog = PythonProgram("run", PythonCompiler().compile(PythonRenderer().render(lst))) - prog(out_buf:=allocator.alloc(uop.dtype.itemsize), *bufs) - return out_buf.cast(uop.dtype.fmt).tolist()[0] - -def not_support_multi_device(): - # GPU and CUDA don't support multi device if in CI - return CI and REAL_DEV in ("GPU", "CUDA") - -# NOTE: This will open REMOTE if it's the default device -REAL_DEV = (Device.DEFAULT if Device.DEFAULT != "REMOTE" else Device['REMOTE'].properties.real_device) diff --git a/tinygrad/test/mockgpu/amd/amddriver.py b/tinygrad/test/mockgpu/amd/amddriver.py deleted file mode 100644 index 2cac02e5..00000000 --- a/tinygrad/test/mockgpu/amd/amddriver.py +++ /dev/null @@ -1,172 +0,0 @@ -import pathlib, re, ctypes, mmap, collections, functools, copy, os -import tinygrad.runtime.autogen.kfd as kfd -import tinygrad.runtime.autogen.am.am as am -from tinygrad.helpers import from_mv -from test.mockgpu.driver import VirtDriver, VirtFileDesc, TextFileDesc, DirFileDesc, VirtFile -from test.mockgpu.amd.amdgpu import AMDGPU, gpu_props - -libc = ctypes.CDLL(ctypes.util.find_library("c")) -libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] -libc.mmap.restype = ctypes.c_void_p - -def ioctls_from_header(): - # hdrpy = (pathlib.Path(__file__).parent.parent.parent.parent / "tinygrad" / "runtime" / "autogen" / "kfd.py").read_text() - # pattern = r'# (AMDKFD_IOC_[A-Z0-9_]+)\s=\s_(IOW?R?).*\(( 0x[0-9a-fA-F]+) ,\s+struct\s([A-Za-z0-9_]+)\s+\)' - # matches = re.findall(pattern, hdrpy, re.MULTILINE) - hdr = (pathlib.Path(__file__).parent.parent.parent.parent / "extra" / "hip_gpu_driver" / "kfd_ioctl.h").read_text().replace("\\\n", "") - pattern = r'#define\s+(AMDKFD_IOC_[A-Z0-9_]+)\s+AMDKFD_(IOW?R?)\((0x[0-9a-fA-F]+),\s+struct\s([A-Za-z0-9_]+)\)' - matches = re.findall(pattern, hdr, re.MULTILINE) - return type("KFD_IOCTLS", (object, ), {name: int(nr, 0x10) for name, _, nr, _ in matches}), \ - {int(nr, 0x10): getattr(kfd, "struct_"+sname) for name, idir, nr, sname in matches} -kfd_ioctls, kfd_headers = ioctls_from_header() - -class KFDFileDesc(VirtFileDesc): - def __init__(self, fd, driver): - super().__init__(fd) - self.driver = driver - - def ioctl(self, fd, request, argp): return self.driver.kfd_ioctl(request, argp) - def mmap(self, start, sz, prot, flags, fd, offset): return offset - -class DRMFileDesc(VirtFileDesc): - def __init__(self, fd, driver, gpu): - super().__init__(fd) - self.driver, self.gpu = driver, gpu - - def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) - -class AMDDriver(VirtDriver): - def __init__(self, gpus=6): - super().__init__() - - # NOTE: gpu ids start from one (id 0 is skipped in KFDIface._is_usable_gpu) - self.tracked_files += [VirtFile('/dev/kfd', functools.partial(KFDFileDesc, driver=self))] + \ - [VirtFile('/sys/devices/virtual/kfd/kfd/topology/nodes', functools.partial(DirFileDesc, child_names=[str(i+1) for i in range(gpus)]))] - - self.gpus = {} - self.next_fd = (1 << 30) - self.next_handle = 1 - self.next_event = 1 - - self.object_by_handle = {} - self.doorbells = {} - self.next_doorbell = collections.defaultdict(int) - self.mmu_event_ids = [] - - for i in range(gpus): self._prepare_gpu(i+1) - - def _alloc_fd(self): - my_fd = self.next_fd - self.next_fd = self.next_fd + 1 - return my_fd - - def _alloc_handle(self): - handle = self.next_handle - self.next_handle += 1 - return handle - - def _alloc_next_event_slot(self): - ev = self.next_event - self.next_event += 1 - return ev - - def _alloc_doorbell(self, gpu_id): - x = ctypes.addressof(from_mv(self.doorbells[gpu_id])) + self.next_doorbell[gpu_id] * 8 - self.next_doorbell[gpu_id] += 1 - return x - - def _prepare_gpu(self, gpu_id): - self.doorbells[gpu_id] = memoryview(bytearray(0x2000)) - self.gpus[gpu_id] = AMDGPU(gpu_id) - self.tracked_files += [ - VirtFile('/sys/module/amdgpu', functools.partial(TextFileDesc, text="1")), - VirtFile('/sys/module/amdgpu/parameters/ppfeaturemask', functools.partial(TextFileDesc, text="0xffff3fff")), - VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}', functools.partial(DirFileDesc, child_names=['gpu_id', 'properties'])), - VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/gpu_id', functools.partial(TextFileDesc, text=f"{gpu_id}")), - VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/properties', - functools.partial(TextFileDesc, text=gpu_props.format(drm_render_minor=gpu_id))), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0', - functools.partial(DirFileDesc, child_names=[str(am.GC_HWID), str(am.SDMA0_HWID), str(am.NBIF_HWID)])), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/major', functools.partial(TextFileDesc, text='11')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/minor', functools.partial(TextFileDesc, text='0')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/base_addr', - functools.partial(TextFileDesc, text='0x00001260\n0x0000A000\n0x0001C000\n0x02402C00')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/major', functools.partial(TextFileDesc, text='6')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/minor', functools.partial(TextFileDesc, text='0')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/base_addr', - functools.partial(TextFileDesc, text='0x00001260\n0x0000A000\n0x0001C000\n0x02402C00')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/major', functools.partial(TextFileDesc, text='4')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/minor', functools.partial(TextFileDesc, text='3')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), - VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/base_addr', - functools.partial(TextFileDesc, text='0x00000000\n0x00000014\n0x00000D20\n0x00010400\n0x0241B000\n0x04040000')), - VirtFile(f'/dev/dri/renderD{gpu_id}', functools.partial(DRMFileDesc, driver=self, gpu=f"{self.gpus[gpu_id]}")), - ] - - def open(self, name, flags, mode, virtfile): return virtfile.fdcls(self._alloc_fd()) - - def kfd_ioctl(self, req, argp): - nr = req & 0xFF - struct = kfd_headers[nr].from_address(argp) - - if nr == kfd_ioctls.AMDKFD_IOC_ACQUIRE_VM: pass - elif nr == kfd_ioctls.AMDKFD_IOC_ALLOC_MEMORY_OF_GPU: - if struct.gpu_id not in self.gpus: return -1 - struct.handle = self._alloc_handle() - self.object_by_handle[struct.handle] = copy.deepcopy(struct) # save memory struct to know what mem it is - elif nr == kfd_ioctls.AMDKFD_IOC_FREE_MEMORY_OF_GPU: - self.object_by_handle.pop(struct.handle) - elif nr == kfd_ioctls.AMDKFD_IOC_MAP_MEMORY_TO_GPU: - dev_ids = (ctypes.c_int32 * struct.n_devices).from_address(struct.device_ids_array_ptr) - for i in range(struct.n_devices): - gpu = self.gpus[dev_ids[i]] - mem_obj = self.object_by_handle[struct.handle] - gpu.map_range(mem_obj.va_addr, mem_obj.size) - struct.n_success = i + 1 - elif nr == kfd_ioctls.AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU: - dev_ids = (ctypes.c_int32 * struct.n_devices).from_address(struct.device_ids_array_ptr) - for i in range(struct.n_devices): - gpu = self.gpus[dev_ids[i]] - mem_obj = self.object_by_handle[struct.handle] - gpu.unmap_range(mem_obj.va_addr, mem_obj.size) - struct.n_success = i + 1 - elif nr == kfd_ioctls.AMDKFD_IOC_CREATE_EVENT: - struct.event_slot_index = self._alloc_next_event_slot() - struct.event_id = struct.event_slot_index - - if struct.event_type == kfd.KFD_IOC_EVENT_MEMORY: self.mmu_event_ids.append(struct.event_id) - elif nr == kfd_ioctls.AMDKFD_IOC_CREATE_QUEUE: - gpu = self.gpus[struct.gpu_id] - if struct.queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: - gpu.add_sdma_queue(struct.ring_base_address, struct.ring_size, struct.read_pointer_address, struct.write_pointer_address) - elif struct.queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE: - gpu.add_pm4_queue(struct.ring_base_address, struct.ring_size, struct.read_pointer_address, struct.write_pointer_address) - else: raise RuntimeError("Unsuported, queue") - - # Track writes to doorbell, calling callback - struct.doorbell_offset = self._alloc_doorbell(struct.gpu_id) - self.track_address(struct.doorbell_offset, struct.doorbell_offset + 8, lambda mv,off: None, lambda mv, off: self._emulate_execute()) - elif nr == kfd_ioctls.AMDKFD_IOC_WAIT_EVENTS: - evs = (kfd.struct_kfd_event_data * struct.num_events).from_address(struct.events_ptr) - for ev in evs: - if ev.event_id in self.mmu_event_ids and "MOCKGPU_EMU_FAULTADDR" in os.environ: - ev.memory_exception_data.gpu_id = 1 - ev.memory_exception_data.va = int(os.environ["MOCKGPU_EMU_FAULTADDR"], 16) - ev.memory_exception_data.failure.NotPresent = 1 - else: - name = "unknown" - for k,v in kfd_ioctls.__dict__.items(): - if nr == v: name = k - assert False, f"unknown kfd ioctl, {nr} {name}" - exit(1) - return 0 - - def _emulate_execute(self): - any_progress = True - while any_progress: - any_progress = False - for gpu in self.gpus.values(): - for q in gpu.queues: - if q.executing: any_progress |= q.execute() > 0 diff --git a/tinygrad/test/mockgpu/amd/amdgpu.py b/tinygrad/test/mockgpu/amd/amdgpu.py deleted file mode 100644 index e46e894a..00000000 --- a/tinygrad/test/mockgpu/amd/amdgpu.py +++ /dev/null @@ -1,353 +0,0 @@ -import ctypes, time -from test.mockgpu.gpu import VirtGPU -from tinygrad.helpers import getbits, to_mv, init_c_struct_t -import tinygrad.runtime.autogen.amd_gpu as amd_gpu, tinygrad.runtime.autogen.am.pm4_nv as pm4, tinygrad.runtime.autogen.am.soc21 as soc21 - -SDMA_MAX_COPY_SIZE = 0x400000 - -regCOMPUTE_PGM_LO = 0x1bac + amd_gpu.GC_BASE__INST0_SEG0 -regCOMPUTE_USER_DATA_0 = 0x1be0 + amd_gpu.GC_BASE__INST0_SEG0 -regCOMPUTE_NUM_THREAD_X = 0x1ba7 + amd_gpu.GC_BASE__INST0_SEG0 -regGRBM_GFX_INDEX = 0x2200 + amd_gpu.GC_BASE__INST0_SEG1 -regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 + amd_gpu.GC_BASE__INST0_SEG1 -regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 + amd_gpu.GC_BASE__INST0_SEG1 -regSQ_THREAD_TRACE_WPTR = 0x39ef + amd_gpu.GC_BASE__INST0_SEG1 -regSQ_THREAD_TRACE_STATUS = 0x39f4 + amd_gpu.GC_BASE__INST0_SEG1 - -CACHE_FLUSH_AND_INV_TS_EVENT = 0x14 - -WAIT_REG_MEM_FUNCTION_ALWAYS = 0 -WAIT_REG_MEM_FUNCTION_EQ = 3 # == -WAIT_REG_MEM_FUNCTION_NEQ = 4 # != -WAIT_REG_MEM_FUNCTION_GEQ = 5 # >= - -REMU_PATHS = ["extra/remu/target/release/libremu.so", "libremu.so", "/usr/local/lib/libremu.so", - "extra/remu/target/release/libremu.dylib", "libremu.dylib", "/usr/local/lib/libremu.dylib", "/opt/homebrew/lib/libremu.dylib"] -def _try_dlopen_remu(): - for path in REMU_PATHS: - try: - remu = ctypes.CDLL(path) - remu.run_asm.restype = ctypes.c_int32 - remu.run_asm.argtypes = [ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, - ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_void_p] - except OSError: pass - else: return remu - print("Could not find libremu.so") - return None -remu = _try_dlopen_remu() - -def create_sdma_packets(): - # TODO: clean up this, if we want to keep it - structs = {} - for name,pkt in [(name,s) for name,s in amd_gpu.__dict__.items() if name.startswith("struct_SDMA_PKT_") and name.endswith("_TAG")]: - names = set() - fields = [] - for pkt_fields in pkt._fields_: - if not pkt_fields[0].endswith("_UNION"): fields.append(pkt_fields) - else: - assert pkt_fields[1]._fields_[0][0] == '_0' - for union_fields in pkt_fields[1]._fields_[0][1]._fields_: - fname = union_fields[0] - if fname in names: fname = pkt_fields[0]+fname - names.add(fname) - # merge together 64-bit fields, otherwise just append them - if fname.endswith("_63_32") and fields[-1][0].endswith("_31_0"): fields[-1] = tuple([fname[:-6], ctypes.c_ulong, 64]) - else: fields.append(tuple([fname, *union_fields[1:]])) - new_name = name[16:-4].lower() - structs[new_name] = init_c_struct_t(tuple(fields)) - assert ctypes.sizeof(structs[new_name]) == ctypes.sizeof(pkt), f"{ctypes.sizeof(structs[new_name])} != {ctypes.sizeof(pkt)}" - return type("SDMA_PKTS", (object, ), structs) -sdma_pkts = create_sdma_packets() - -class AMDQueue: - def __init__(self, base, size, rptr, wptr): - self.queue, self.size = to_mv(base, size).cast("I"), size - self.rptr = to_mv(rptr, 8).cast("Q") if isinstance(rptr, int) else rptr - self.wptr = to_mv(wptr, 8).cast("Q") if isinstance(wptr, int) else wptr - - @property - def executing(self): return self.rptr[0] < self.wptr[0] - -class PM4Executor(AMDQueue): - def __init__(self, gpu, base, size, rptr, wptr): - self.gpu = gpu - self.ib_executor: PM4Executor|None = None - super().__init__(base, size, rptr, wptr) - - def _next_dword(self): - x = self.queue[self.rptr[0] % (self.size // 4)] - self.rptr[0] += 1 - return x - - @property - def executing(self): return self.rptr[0] < self.wptr[0] or self.ib_executor is not None - - def execute(self): - prev_rptr, executed_in_ib, cont = self.rptr[0], 0, True - while self.executing and cont: - if self.ib_executor is not None: - executed_in_ib += self.ib_executor.execute() - if self.ib_executor.executing: break - self.ib_executor = None - continue # this continue is needed if PACKET3_INDIRECT_BUFFER is the last packet and rptr == wptr - header = self._next_dword() - packet_type = header >> 30 - op = (header >> 8) & 0xFF - n = (header >> 16) & 0x3FFF - assert packet_type == 3, "Can parse only packet3" - if op == amd_gpu.PACKET3_SET_SH_REG: self._exec_set_reg(n, pm4.PACKET3_SET_SH_REG_START) - elif op == amd_gpu.PACKET3_SET_UCONFIG_REG: self._exec_set_reg(n, pm4.PACKET3_SET_UCONFIG_REG_START) - elif op == amd_gpu.PACKET3_ACQUIRE_MEM: self._exec_acquire_mem(n) - elif op == amd_gpu.PACKET3_RELEASE_MEM: self._exec_release_mem(n) - elif op == amd_gpu.PACKET3_COPY_DATA: self._exec_copy_data(n) - elif op == amd_gpu.PACKET3_WAIT_REG_MEM: cont = self._exec_wait_reg_mem(n) - elif op == amd_gpu.PACKET3_DISPATCH_DIRECT: self._exec_dispatch_direct(n) - elif op == amd_gpu.PACKET3_INDIRECT_BUFFER: self._exec_indirect_buffer(n) - elif op == amd_gpu.PACKET3_EVENT_WRITE: self._exec_event_write(n) - else: raise RuntimeError(f"PM4: Unknown opcode: {op}") - return (self.rptr[0] - prev_rptr) + executed_in_ib - - def _exec_acquire_mem(self, n): - assert n == 6 - for _ in range(7): self._next_dword() # TODO: implement - - def _exec_release_mem(self, n): - assert n == 6 - mem_event_type = (self._next_dword() >> 0) & 0xff - selectors = self._next_dword() - mem_data_sel = (selectors >> 29) & 0b111 - # int_sel = (selectors >> 24) & 0b11 - # mem_dst_sel = (selectors >> 16) & 0b1 - addr_lo = self._next_dword() - addr_hi = self._next_dword() - val_lo = self._next_dword() - val_hi = self._next_dword() - val = val_lo + (val_hi << 32) - _ = self._next_dword() # ev - - ptr = to_mv(addr_lo + (addr_hi << 32), 8) - if mem_data_sel == 1 or mem_data_sel == 2: ptr.cast('Q')[0] = val - elif mem_data_sel == 3: - if mem_event_type == CACHE_FLUSH_AND_INV_TS_EVENT: ptr.cast('Q')[0] = int(time.perf_counter() * 1e8) - else: raise RuntimeError(f"Unknown {mem_data_sel=} {mem_event_type=}") - else: raise RuntimeError(f"Unknown {mem_data_sel=}") - - def _exec_copy_data(self, n): - assert n == 4 - copy_data_flags = self._next_dword() - src_addr_lo = self._next_dword() - _src_addr_hi = self._next_dword() - dst_addr_lo = self._next_dword() - dst_addr_hi = self._next_dword() - assert copy_data_flags == 0x100204, hex(copy_data_flags) # better fail than silently do the wrong thing - to_mv(dst_addr_hi<<32|dst_addr_lo, 4).cast('I')[0] = self.gpu.regs[src_addr_lo] - - def _exec_wait_reg_mem(self, n): - assert n == 5 - info = self._next_dword() - addr_lo = self._next_dword() - addr_hi = self._next_dword() - val = self._next_dword() - mask = self._next_dword() - _ = self._next_dword() # timeout - - mem_function = (info >> 0) & 0b111 - mem_space = (info >> 4) & 0b1 - mem_op = (info >> 6) & 0b1 - _ = (info >> 8) & 0b1 # mem_engine - - if mem_space == 0 and mem_op == 1: mval = val # hack for memory barrier, should properly handle (req_req, reg_done) - elif mem_space == 0: mval = self.gpu.regs[addr_hi<<32|addr_lo] - elif mem_space == 1: mval = to_mv(addr_lo + (addr_hi << 32), 4).cast('I')[0] - - mval &= mask - - if mem_function == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= val) - elif mem_function == WAIT_REG_MEM_FUNCTION_NEQ: can_cont = bool(mval != val) - elif mem_function == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == val) - else: raise RuntimeError(f"Do not support {mem_function=}") - - if not can_cont: self.rptr[0] = self.rptr[0] - 7 # revert this packet, need to wait again - return can_cont - - def _exec_set_reg(self, n, off): - reg = off + self._next_dword() - for i in range(n): - self.gpu.regs[reg] = self._next_dword() - reg += 1 - - def _exec_dispatch_direct(self, n): - assert n == 3 - gl = [self._next_dword() for _ in range(3)] - _ = self._next_dword() # flags - - prg_addr = (self.gpu.regs[regCOMPUTE_PGM_LO] + (self.gpu.regs[regCOMPUTE_PGM_LO + 1] << 32)) << 8 - args_addr = self.gpu.regs[regCOMPUTE_USER_DATA_0] + (self.gpu.regs[regCOMPUTE_USER_DATA_0 + 1] << 32) - lc = [self.gpu.regs[i] for i in range(regCOMPUTE_NUM_THREAD_X, regCOMPUTE_NUM_THREAD_X+3)] - - prg_sz = 0 - for st,sz in self.gpu.mapped_ranges: - if st <= prg_addr < st+sz: prg_sz = sz - (prg_addr - st) - - assert prg_sz > 0, "Invalid prg ptr (not found in mapped ranges)" - err = remu.run_asm(prg_addr, prg_sz, *gl, *lc, args_addr) - if err != 0: raise RuntimeError("remu does not support the new instruction introduced in this kernel") - - def _exec_indirect_buffer(self, n): - addr_lo = self._next_dword() - addr_hi = self._next_dword() - buf_sz = self._next_dword() & (0x7fffff) - - rptr = memoryview(bytearray(8)).cast('Q') - wptr = memoryview(bytearray(8)).cast('Q') - rptr[0] = 0 - wptr[0] = buf_sz - self.ib_executor = PM4Executor(self.gpu, (addr_hi << 32) | addr_lo, buf_sz * 4, rptr, wptr) - - def _exec_event_write(self, n): - assert n == 0 - event_dw = self._next_dword() - match (event_dw & 0xFF): # event type - case soc21.THREAD_TRACE_FINISH: - old_idx = self.gpu.regs.grbm_index - for se in range(self.gpu.regs.n_se): - self.gpu.regs.grbm_index = 0b011 << 29 | se << 16 # select se, broadcast sa and instance - self.gpu.regs[regSQ_THREAD_TRACE_STATUS] = 1 << 12 # FINISH_PENDING==0 FINISH_DONE==1 BUSY==0 - buf = ((self.gpu.regs[regSQ_THREAD_TRACE_BUF0_SIZE]&0xf)<<32|self.gpu.regs[regSQ_THREAD_TRACE_BUF0_BASE])<<12 # per page addressing - fake_used = 0x1000 # fake one page long trace - self.gpu.regs[regSQ_THREAD_TRACE_WPTR] = ((buf+fake_used)//32) & 0x1FFFFFFF - self.gpu.regs.grbm_index = old_idx - case _: pass # NOTE: for now most events aren't emulated - -class SDMAExecutor(AMDQueue): - def __init__(self, gpu, base, size, rptr, wptr): - self.gpu, self.base = gpu, base - super().__init__(base, size, rptr, wptr) - - def execute(self): - prev_rptr, cont = self.rptr[0], True - while self.executing and cont: - header = self.queue[(self.rptr[0] // 4) % (self.size // 4)] - op = (header >> 0) & 0xff - if op == 0: self.rptr[0] += 4 - elif op == amd_gpu.SDMA_OP_FENCE: self._execute_fence() - elif op == amd_gpu.SDMA_OP_TRAP: self._execute_trap() - elif op == amd_gpu.SDMA_OP_POLL_REGMEM: cont = self._execute_poll_regmem() - elif op == amd_gpu.SDMA_OP_GCR: self._execute_gcr() - elif op == amd_gpu.SDMA_OP_COPY: self._execute_copy() - elif op == amd_gpu.SDMA_OP_TIMESTAMP: self._execute_timestamp() - else: raise RuntimeError(f"Unknown SDMA op {op}") - return self.rptr[0] - prev_rptr - - def _execute_fence(self): - struct = sdma_pkts.fence.from_address(self.base + self.rptr[0] % self.size) - to_mv(struct.addr, 8).cast('Q')[0] = struct.data - self.rptr[0] += ctypes.sizeof(struct) - - def _execute_trap(self): - struct = sdma_pkts.trap.from_address(self.base + self.rptr[0] % self.size) - self.rptr[0] += ctypes.sizeof(struct) - - def _execute_poll_regmem(self): - struct = sdma_pkts.poll_regmem.from_address(self.base + self.rptr[0] % self.size) - - if struct.mem_poll == 0: mval = struct.value & struct.mask - elif struct.mem_poll == 1: mval = to_mv(struct.addr, 4).cast('I')[0] & struct.mask - - if struct.func == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= struct.value) - elif struct.func == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == struct.value) - elif struct.func == WAIT_REG_MEM_FUNCTION_ALWAYS: can_cont = True - else: raise RuntimeError(f"Do not support {struct.func=}") - - if not can_cont: return False - - self.rptr[0] += ctypes.sizeof(struct) - return True - - def _execute_timestamp(self): - struct = sdma_pkts.timestamp.from_address(self.base + self.rptr[0] % self.size) - - mem = to_mv(struct.addr, 8).cast('Q') - mem[0] = int(time.perf_counter() * 1e8) - - self.rptr[0] += ctypes.sizeof(struct) - - def _execute_gcr(self): - struct = sdma_pkts.gcr.from_address(self.base + self.rptr[0] % self.size) - self.rptr[0] += ctypes.sizeof(struct) - - def _execute_copy(self): - struct = sdma_pkts.copy_linear.from_address(self.base + self.rptr[0] % self.size) - count_cnt = to_mv(self.base + self.rptr[0] + 4, 4).cast('I')[0] & 0x3FFFFFFF - ctypes.memmove(struct.dst_addr, struct.src_addr, count_cnt + 1) - self.rptr[0] += ctypes.sizeof(struct) - -class AMDGPURegisters: - def __init__(self, n_se:int=6): - self.n_se = n_se - self.grbm_index = 0b111 << 0x1d # all broadcast. NOTE: only per-se register emulation is currently supported - self.regs: dict[tuple[int, int], int] = {} - def __getitem__(self, addr:int) -> int: - if addr == regGRBM_GFX_INDEX: return self.grbm_index - return self.regs[(addr, getbits(self.grbm_index, 16, 23))] - def __setitem__(self, addr:int, val:int): - if addr == regGRBM_GFX_INDEX: self.grbm_index = val - if getbits(self.grbm_index, 31, 31): - for se in range(self.n_se): self.regs[(addr, se)] = val - else: - self.regs[(addr, getbits(self.grbm_index, 16, 23))] = val - -class AMDGPU(VirtGPU): - def __init__(self, gpuid): - super().__init__(gpuid) - self.regs = AMDGPURegisters() - self.mapped_ranges = set() - self.queues = [] - - def map_range(self, vaddr, size): self.mapped_ranges.add((vaddr, size)) - def unmap_range(self, vaddr, size): self.mapped_ranges.remove((vaddr, size)) - def add_pm4_queue(self, base, size, rptr, wptr): - self.queues.append(PM4Executor(self, base, size, rptr, wptr)) - return len(self.queues) - 1 - def add_sdma_queue(self, base, size, rptr, wptr): - self.queues.append(SDMAExecutor(self, base, size, rptr, wptr)) - return len(self.queues) - 1 - -gpu_props = """cpu_cores_count 0 -simd_count 192 -mem_banks_count 1 -caches_count 206 -io_links_count 1 -p2p_links_count 5 -cpu_core_id_base 0 -simd_id_base 2147488032 -max_waves_per_simd 16 -lds_size_in_kb 64 -gds_size_in_kb 0 -num_gws 64 -wave_front_size 32 -array_count 12 -simd_arrays_per_engine 2 -cu_per_simd_array 8 -simd_per_cu 2 -max_slots_scratch_cu 32 -gfx_target_version 110000 -vendor_id 4098 -device_id 29772 -location_id 34304 -domain 0 -drm_render_minor {drm_render_minor} -hive_id 0 -num_sdma_engines 2 -num_sdma_xgmi_engines 0 -num_sdma_queues_per_engine 6 -num_cp_queues 8 -max_engine_clk_fcompute 2482 -local_mem_size 0 -fw_version 2140 -capability 671588992 -debug_prop 1495 -sdma_fw_version 20 -unique_id 11673270660693242239 -num_xcc 1 -max_engine_clk_ccompute 2400""" diff --git a/tinygrad/test/mockgpu/cuda/cuda.py b/tinygrad/test/mockgpu/cuda/cuda.py deleted file mode 100644 index a5dd5fe0..00000000 --- a/tinygrad/test/mockgpu/cuda/cuda.py +++ /dev/null @@ -1,170 +0,0 @@ -from __future__ import annotations -from typing import Any -import ctypes, time -from tinygrad.runtime.autogen import cuda as orig_cuda -from tinygrad.helpers import mv_address - -for attr in dir(orig_cuda): - if not attr.startswith('__'): - globals()[attr] = getattr(orig_cuda, attr) - -try: - gpuocelot_lib = ctypes.CDLL(ctypes.util.find_library("gpuocelot")) - gpuocelot_lib.ptx_run.argtypes = [ctypes.c_char_p, ctypes.c_int, ctypes.POINTER(ctypes.c_void_p), ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int] # noqa: E501 -except Exception: pass - -# Global state -class CUDAState: - def __init__(self): - self.memory: dict[int, memoryview] = {} - self.events: dict[int, float] = {} # Event ID -> timestamp - self.modules: dict[int, memoryview] = {} # Module ID -> code - self.current_context: int|None = None - self.contexts: dict[int, dict] = {} # Context ID -> context data - self.devices: dict[int, dict] = {} # Device ID -> device data - self.next_ptr = 1000 # For memory allocation - self.next_event_id = 1 - self.next_module_id = 1 - self.next_context_id = 1 - -cuda_state = CUDAState() - -# Helper functions -def check_context(): - if cuda_state.current_context is None: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - return orig_cuda.CUDA_SUCCESS - -# CUDA API simulation -def cuInit(flags: int) -> int: - return orig_cuda.CUDA_SUCCESS - -def cuDeviceGet(device, ordinal: int) -> int: - if ordinal < 0: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - device._obj.value = ordinal - cuda_state.devices[ordinal] = {"compute_capability": (3, 5)} - return orig_cuda.CUDA_SUCCESS - -def cuCtxCreate_v2(pctx, flags: int, dev: int) -> int: - ctx_id = cuda_state.next_context_id - cuda_state.next_context_id += 1 - cuda_state.contexts[ctx_id] = {"device": dev, "flags": flags} - pctx._obj.value = ctx_id - return orig_cuda.CUDA_SUCCESS - -def cuCtxSetCurrent(context) -> int: - if context.value not in cuda_state.contexts: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - cuda_state.current_context = context.value - return orig_cuda.CUDA_SUCCESS - -def cuMemAlloc_v2(dptr, bytesize: int) -> int: - x = memoryview(bytearray(bytesize)) - dptr._obj.value = mv_address(x) - cuda_state.memory[dptr._obj.value] = x - return orig_cuda.CUDA_SUCCESS - -def cuMemFree_v2(dptr) -> int: - if dptr.value in cuda_state.memory: - del cuda_state.memory[dptr.value] - return orig_cuda.CUDA_SUCCESS - return orig_cuda.CUDA_ERROR_INVALID_VALUE - -def cuMemcpyHtoDAsync_v2(dst, src: ctypes.c_void_p, bytesize: int, stream: Any) -> int: - ctypes.memmove(dst.value, src, bytesize) - return orig_cuda.CUDA_SUCCESS - -def cuMemcpyDtoH_v2(dst: ctypes.c_void_p, src, bytesize: int) -> int: - ctypes.memmove(dst, src.value, bytesize) - return orig_cuda.CUDA_SUCCESS - -def cuEventCreate(phEvent, flags: int) -> int: - event_id = cuda_state.next_event_id - cuda_state.next_event_id += 1 - cuda_state.events[event_id] = 0.0 - phEvent._obj.value = event_id - return orig_cuda.CUDA_SUCCESS - -def cuEventRecord(hEvent, hStream: Any) -> int: - if hEvent.value not in cuda_state.events: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - cuda_state.events[hEvent.value] = time.perf_counter_ns() - return orig_cuda.CUDA_SUCCESS - -def cuEventSynchronize(hEvent) -> int: - if hEvent.value not in cuda_state.events: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - return orig_cuda.CUDA_SUCCESS - -def cuEventElapsedTime(pMilliseconds, hStart, hEnd) -> int: - if hStart.value not in cuda_state.events or hEnd.value not in cuda_state.events: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - elapsed = (cuda_state.events[hEnd.value] - cuda_state.events[hStart.value]) * 1e-6 - pMilliseconds._obj.value = elapsed - return orig_cuda.CUDA_SUCCESS - -def cuEventDestroy_v2(hEvent) -> int: - if hEvent.value in cuda_state.events: - del cuda_state.events[hEvent.value] - return orig_cuda.CUDA_SUCCESS - -def cuModuleLoadData(module, image: bytes) -> int: - module_id = cuda_state.next_module_id - cuda_state.next_module_id += 1 - cuda_state.modules[module_id] = memoryview(bytearray(image)) - module._obj.value = module_id - return orig_cuda.CUDA_SUCCESS - -def cuModuleGetFunction(hfunc, hmod, name: bytes) -> int: - if hmod.value not in cuda_state.modules: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - hfunc._obj.value = mv_address(cuda_state.modules[hmod.value]) - return orig_cuda.CUDA_SUCCESS - -def cuModuleUnload(hmod) -> int: - if hmod.value in cuda_state.modules: - del cuda_state.modules[hmod.value] - return orig_cuda.CUDA_SUCCESS - -def cuLaunchKernel(f, gx: int, gy: int, gz: int, lx: int, ly: int, lz: int, sharedMemBytes: int, - hStream: Any, kernelParams: Any, extra: Any) -> int: - cargs = [ctypes.cast(getattr(extra, field[0]), ctypes.c_void_p) for field in extra._fields_] - gpuocelot_lib.ptx_run(ctypes.cast(f.value, ctypes.c_char_p), len(cargs), (ctypes.c_void_p*len(cargs))(*cargs), lx, ly, lz, gx, gy, gz, 0) - return orig_cuda.CUDA_SUCCESS - -def cuDeviceComputeCapability(major, minor, dev: int) -> int: - if dev not in cuda_state.devices: - return orig_cuda.CUDA_ERROR_INVALID_VALUE - major._obj.value = 3 - minor._obj.value = 5 - return orig_cuda.CUDA_SUCCESS - -def cuDeviceCanAccessPeer(canAccessPeer, dev: int, peerDev: int) -> int: - canAccessPeer._obj.value = 1 # Always allow peer access in simulation - return orig_cuda.CUDA_SUCCESS - -def cuCtxEnablePeerAccess(peerContext, flags: int) -> int: - return orig_cuda.CUDA_SUCCESS - -def cuMemHostAlloc(pp, bytesize: int, flags: int) -> int: - return cuMemAlloc_v2(pp, bytesize) - -def cuMemFreeHost(p: ctypes.c_void_p) -> int: return cuMemFree_v2(p) - -def cuMemcpyDtoDAsync_v2(dst, src, bytesize: int, stream: Any) -> int: - ctypes.memmove(dst.value, src.value, bytesize) - return orig_cuda.CUDA_SUCCESS - -def cuFuncSetAttribute(hfunc, attrib: int, value: int) -> int: - return orig_cuda.CUDA_SUCCESS - -def cuStreamWaitEvent(stream: Any, event, flags: int) -> int: return orig_cuda.CUDA_SUCCESS -def cuCtxSynchronize() -> int: return orig_cuda.CUDA_SUCCESS - -def cuGetErrorString(error: int, pStr) -> int: - error_str = orig_cuda.cudaError_enum__enumvalues.get(error, "Unknown CUDA error").encode() - buf = ctypes.create_string_buffer(error_str) - # Set the pointer to point to our error string buffer - pStr._obj.value = ctypes.cast(buf, ctypes.POINTER(ctypes.c_char)) - return orig_cuda.CUDA_SUCCESS diff --git a/tinygrad/test/mockgpu/driver.py b/tinygrad/test/mockgpu/driver.py deleted file mode 100644 index 7be165cb..00000000 --- a/tinygrad/test/mockgpu/driver.py +++ /dev/null @@ -1,39 +0,0 @@ -from typing import Any -from dataclasses import dataclass - -class VirtFileDesc: - def __init__(self, fd): self.fd, self.off = fd, 0 - def ioctl(self, fd, req, argp): raise NotImplementedError() - def mmap(self, st, sz, prot, flags, fd, off): raise NotImplementedError() - def close(self, fd): return 0 - -class TextFileDesc(VirtFileDesc): - def __init__(self, fd, text): - super().__init__(fd) - self.content = text - - def ioctl(self, fd, req, argp): return 0 - def read_contents(self, size=None): - ret = self.content[self.off:self.off+(size or len(self.content))] - self.off += (size or len(self.content)) - return ret - def seek(self, offset): self.off += offset -class DirFileDesc(VirtFileDesc): - def __init__(self, fd, child_names): - super().__init__(fd) - self.child_names = child_names - - def ioctl(self, fd, req, argp): return 0 - def list_contents(self): return self.child_names - -@dataclass(frozen=True) -class VirtFile: - path: str - fdcls: Any # TODO: fix this Union[VirtFileDesc, functools.partial[VirtFileDesc]] - -class VirtDriver: - def __init__(self): - self.tracked_files = [] - self.tracked_addresses = [] - def track_address(self, staddr, enaddr, rcb, wcb): self.tracked_addresses.append((staddr, enaddr, rcb, wcb)) - def open(self, name, flags, mode, fdcls): raise NotImplementedError() diff --git a/tinygrad/test/mockgpu/gpu.py b/tinygrad/test/mockgpu/gpu.py deleted file mode 100644 index 296486b9..00000000 --- a/tinygrad/test/mockgpu/gpu.py +++ /dev/null @@ -1,4 +0,0 @@ -class VirtGPU: - def __init__(self, gpuid): self.gpuid = gpuid - def map_range(self, vaddr, size): raise NotImplementedError() - def unmap_range(self, vaddr, size): raise NotImplementedError() diff --git a/tinygrad/test/mockgpu/mockgpu.py b/tinygrad/test/mockgpu/mockgpu.py deleted file mode 100644 index 9e60fa39..00000000 --- a/tinygrad/test/mockgpu/mockgpu.py +++ /dev/null @@ -1,101 +0,0 @@ -import ctypes, ctypes.util, time, os, builtins, fcntl -from tinygrad.runtime.support.hcq import FileIOInterface -from test.mockgpu.nv.nvdriver import NVDriver -from test.mockgpu.amd.amddriver import AMDDriver -start = time.perf_counter() - -# *** ioctl lib *** -libc = ctypes.CDLL(ctypes.util.find_library("c")) -libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] -libc.mmap.restype = ctypes.c_void_p - -drivers = [AMDDriver(), NVDriver()] -tracked_fds = {} - -orignal_memoryview = builtins.memoryview -class TrackedMemoryView: - def __init__(self, data, rcb, wcb): - self.mv = orignal_memoryview(data) - self.rcb, self.wcb = rcb, wcb - - def __getitem__(self, index): - self.rcb(self.mv, index) - return self.mv[index] - - def __setitem__(self, index, value): - self.mv[index] = value - self.wcb(self.mv, index) - - def cast(self, new_type, **kwargs): - self.mv = self.mv.cast('B').cast(new_type, **kwargs) - return self - - @property - def nbytes(self): return self.mv.nbytes - def __len__(self): return len(self.mv) - def __repr__(self): return repr(self.mv) - -def _memoryview(cls, mem): - if isinstance(mem, int) or isinstance(mem, ctypes.Array): - addr = ctypes.addressof(mem) if isinstance(mem, ctypes.Array) else mem - for d in drivers: - for st,en,rcb,wcb in d.tracked_addresses: - if st <= addr <= en: return TrackedMemoryView(mem, rcb, wcb) - return orignal_memoryview(mem) -builtins.memoryview = type("memoryview", (), {'__new__': _memoryview}) # type: ignore - -def _open(path, flags): - for d in drivers: - for x in d.tracked_files: - if path == x.path: - virtfd = d.open(path, flags, 0o777, x) - tracked_fds[virtfd.fd] = virtfd - return virtfd.fd - return os.open(path, flags, 0o777) if os.path.exists(path) else None - -class MockFileIOInterface(FileIOInterface): - def __init__(self, path:str="", flags:int=os.O_RDONLY, fd:int|None=None): - self.path = path - self.fd = fd or _open(path, flags) - - def __del__(self): - if self.fd in tracked_fds: - tracked_fds[self.fd].close(self.fd) - tracked_fds.pop(self.fd) - else: os.close(self.fd) - - def ioctl(self, request, arg): - if self.fd in tracked_fds: - return tracked_fds[self.fd].ioctl(self.fd, request, ctypes.addressof(arg)) - return fcntl.ioctl(self.fd, request, arg) - - def mmap(self, start, sz, prot, flags, offset): - if self.fd in tracked_fds: - return tracked_fds[self.fd].mmap(start, sz, prot, flags, self.fd, offset) - return libc.mmap(start, sz, prot, flags, self.fd, offset) - - def read(self, size=None, binary=False, offset=None): - if binary: raise NotImplementedError() - if self.fd in tracked_fds: - return tracked_fds[self.fd].read_contents(size) - with open(self.fd, "rb" if binary else "r", closefd=False) as file: - if file.tell() >= os.fstat(self.fd).st_size: file.seek(0) - return file.read(size) - - def listdir(self): - if self.fd in tracked_fds: - return tracked_fds[self.fd].list_contents() - return os.listdir(self.path) - - def write(self, content, binary=False, offset=None): raise NotImplementedError() - def seek(self, offset): - if self.fd in tracked_fds: - tracked_fds[self.fd].seek(offset) - else: - os.lseek(self.fd, offset, os.SEEK_CUR) - @staticmethod - def exists(path): return _open(path, os.O_RDONLY) is not None - @staticmethod - def readlink(path): raise NotImplementedError() - @staticmethod - def eventfd(initval, flags=None): NotImplementedError() diff --git a/tinygrad/test/mockgpu/nv/nvdriver.py b/tinygrad/test/mockgpu/nv/nvdriver.py deleted file mode 100644 index d7c330c6..00000000 --- a/tinygrad/test/mockgpu/nv/nvdriver.py +++ /dev/null @@ -1,257 +0,0 @@ -import ctypes, mmap, collections, functools, os -import tinygrad.runtime.autogen.nv_gpu as nv_gpu -from typing import Any -from tinygrad.helpers import to_mv -from test.mockgpu.driver import VirtDriver, VirtFileDesc, VirtFile -from test.mockgpu.nv.nvgpu import NVGPU - -MAP_FIXED = 0x10 -libc = ctypes.CDLL(ctypes.util.find_library("c")) -libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] -libc.mmap.restype = ctypes.c_void_p -libc.munmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t] -libc.munmap.restype = ctypes.c_int - -NVSubDevice = collections.namedtuple('NVSubDevice', ['device']) -NVUserMode = collections.namedtuple('NVUserMode', ['subdevice']) -NVVASpace = collections.namedtuple('NVVASpace', ['device']) -NVAllocation = collections.namedtuple('NVAllocation', ['device', 'size']) -NVChannelGroup = collections.namedtuple('NVChannelGroup', ['device']) -NVContextShare = collections.namedtuple('NVContextShare', ['channel_group']) -NVGPFIFO = collections.namedtuple('NVGPFIFO', ['device', 'token']) - -class NVCtlFileDesc(VirtFileDesc): - def __init__(self, fd, driver): - super().__init__(fd) - self.driver = driver - - def ioctl(self, fd, request, argp): return self.driver.ctl_ioctl(request, argp) - def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) - -class NVUVMFileDesc(VirtFileDesc): - def __init__(self, fd, driver): - super().__init__(fd) - self.driver = driver - - def ioctl(self, fd, request, argp): return self.driver.uvm_ioctl(request, argp) - def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) - -class NVDevFileDesc(VirtFileDesc): - def __init__(self, fd, driver, gpu): - super().__init__(fd) - self.driver, self.gpu = driver, gpu - self._mapping_userland = False - - def ioctl(self, fd, request, argp): return self.driver.dev_ioctl(self.gpu, request, argp) - def mmap(self, start, sz, prot, flags, fd, offset): - start = libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) - if self._mapping_userland: - self.driver.track_address(start, start+sz, lambda mv,off: None, lambda mv, off: self.driver._gpu_mmio_write(mv, off, self.gpu)) - return start - -class NVDriver(VirtDriver): - def __init__(self, gpus=6): - super().__init__() - - self.tracked_files += [VirtFile('/dev/nvidiactl', functools.partial(NVCtlFileDesc, driver=self)), - VirtFile('/dev/nvidia-uvm', functools.partial(NVUVMFileDesc, driver=self))] - - self.root_handle = None - - self.gpus = {} - self.next_fd = (1 << 29) - self.next_handle = 1 - - self.object_by_handle = {} - self.opened_fds = {} - self.next_doorbell = collections.defaultdict(int) - - for i in range(gpus): self._prepare_gpu(i) - - def _alloc_fd(self): - my_fd = self.next_fd - self.next_fd = self.next_fd + 1 - return my_fd - - def _alloc_handle(self): - handle = self.next_handle - self.next_handle += 1 - return handle - - def _prepare_gpu(self, gpu_id): - self.gpus[gpu_id] = NVGPU(gpu_id) - self.tracked_files += [VirtFile(f'/dev/nvidia{gpu_id}', functools.partial(NVDevFileDesc, driver=self, gpu=self.gpus[gpu_id]))] - - def open(self, name, flags, mode, virtfile): - cl = virtfile.fdcls(self._alloc_fd()) - self.opened_fds[cl.fd] = cl - return cl - - def rm_alloc(self, argp): - struct = nv_gpu.NVOS21_PARAMETERS.from_address(argp) - params_ptr = struct.pAllocParms - if struct.hClass == nv_gpu.NV01_ROOT_CLIENT: self.root_handle = struct.hObjectNew = self._alloc_handle() - elif struct.hClass == nv_gpu.NV01_DEVICE_0: - params:Any = nv_gpu.NV0080_ALLOC_PARAMETERS.from_address(params_ptr) - assert params.hClientShare == self.root_handle - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = self.gpus[params.deviceId] - elif struct.hClass == nv_gpu.NV20_SUBDEVICE_0: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVSubDevice(self.object_by_handle[struct.hObjectParent]) - elif struct.hClass == nv_gpu.TURING_USERMODE_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVSubDevice) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVUserMode(self.object_by_handle[struct.hObjectParent]) - elif struct.hClass == nv_gpu.FERMI_VASPACE_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVVASpace(self.object_by_handle[struct.hObjectParent]) - elif struct.hClass == nv_gpu.NV1_MEMORY_SYSTEM or struct.hClass == nv_gpu.NV1_MEMORY_USER: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) - params = nv_gpu.NV_MEMORY_ALLOCATION_PARAMS.from_address(params_ptr) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVAllocation(self.object_by_handle[struct.hObjectParent], params.size) - elif struct.hClass == nv_gpu.KEPLER_CHANNEL_GROUP_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVChannelGroup(self.object_by_handle[struct.hObjectParent]) - elif struct.hClass == nv_gpu.FERMI_CONTEXT_SHARE_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVChannelGroup) - struct.hObjectNew = self._alloc_handle() - self.object_by_handle[struct.hObjectNew] = NVContextShare(self.object_by_handle[struct.hObjectParent]) - elif struct.hClass == nv_gpu.AMPERE_CHANNEL_GPFIFO_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVChannelGroup) - struct.hObjectNew = self._alloc_handle() - params = nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.from_address(params_ptr) - gpu = self.object_by_handle[struct.hObjectParent].device - gpfifo_token = gpu.add_gpfifo(params.gpFifoOffset, params.gpFifoEntries) - self.object_by_handle[struct.hObjectNew] = NVGPFIFO(gpu, gpfifo_token) - elif struct.hClass == nv_gpu.AMPERE_DMA_COPY_B or struct.hClass == nv_gpu.ADA_COMPUTE_A: - assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPFIFO) - struct.hObjectNew = self._alloc_handle() - elif struct.hClass == nv_gpu.GT200_DEBUGGER: - struct.hObjectNew = self._alloc_handle() - else: raise RuntimeError(f"Unknown {struct.hClass} to rm_alloc") - return 0 - - def rm_control(self, argp): - struct = nv_gpu.NVOS54_PARAMETERS.from_address(argp) - params_ptr = struct.params - if struct.cmd == nv_gpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2: - params:Any = nv_gpu.NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS.from_address(params_ptr) - params.deviceInstance = params.gpuId # emulate them to be the same - elif struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 or struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: - if struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: - params = nv_gpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS.from_address(params_ptr) - else: - params = nv_gpu.NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS.from_address(params_ptr) - - classes = [50021, 51607, 51648, 50543, 51125, 51125, 51125, 51125, 50529, 36967, 36909, 37105, 33868, 36978, 37095, 37094, 36980, 37014, 49270, - 41068, 41088, 41280, 50025, 96, 112, 115, 125, 20608, 20640, 20539, 20540, 41089, 41092, 50034, 50810, 50811, 50814, 51056, 51057, - 51059, 51069, 51071, 51632, 51639, 51639, 51706, 52019, 222, 50287, 50273, 50031, 50017] # from ada102 - params.numClasses = len(classes) - if struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: - clslist = to_mv(params.classList, params.numClasses * 4).cast('I') - for i,c in enumerate(classes): clslist[i] = c - else: - for i,c in enumerate(classes): params.classList[i] = c - elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_GR_GET_INFO: - info = {nv_gpu.NV2080_CTRL_GR_INFO_INDEX_SM_VERSION: nv_gpu.NV2080_CTRL_GR_INFO_SM_VERSION_3_5, - nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS: 1, - nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC: 1, - nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC: 1, - nv_gpu.NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM: 1, - } - - params = nv_gpu.NV2080_CTRL_GR_GET_INFO_PARAMS.from_address(params_ptr) - reqlist = (nv_gpu.NV2080_CTRL_GR_INFO * params.grInfoListSize).from_address(params.grInfoList) - for i in range(params.grInfoListSize): reqlist[i].data = info[reqlist[i].index] - elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: - assert struct.hObject in self.object_by_handle and isinstance(self.object_by_handle[struct.hObject], NVSubDevice) - gpu = self.object_by_handle[struct.hObject].device - params = nv_gpu.NV2080_CTRL_GPU_GET_GID_INFO_PARAMS.from_address(params_ptr) - if params.flags != nv_gpu.NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY: raise RuntimeError("Unknown format") - bts = gpu.gpu_uuid(sz=params.length) - for i in range(params.length): params.data[i] = bts[i] - elif struct.cmd == nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: - assert struct.hObject in self.object_by_handle and isinstance(self.object_by_handle[struct.hObject], NVGPFIFO) - params = nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS.from_address(params_ptr) - gpu_fifo = self.object_by_handle[struct.hObject] - params.workSubmitToken = gpu_fifo.token - elif struct.cmd == nv_gpu.NVA06C_CTRL_CMD_GPFIFO_SCHEDULE: pass - elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_PERF_BOOST: pass - elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE: pass - elif struct.cmd == nv_gpu.NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES: - params = nv_gpu.NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS.from_address(params_ptr) - params.mmuFault.valid = bool("MOCKGPU_EMU_FAULTADDR" in os.environ) - elif struct.cmd == nv_gpu.NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO: - params = nv_gpu.struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS.from_address(params_ptr) - params.count = 1 - params.mmuFaultInfoList[0].faultAddress = int(os.environ['MOCKGPU_EMU_FAULTADDR'], base=16) - params.mmuFaultInfoList[0].faultType = 1 - params.mmuFaultInfoList[0].accessType = 1 - else: raise RuntimeError(f"Unknown {struct.cmd} to rm_control") - return 0 - - def ctl_ioctl(self, req, argp): - nr = req & 0xff - if nr == nv_gpu.NV_ESC_RM_ALLOC: return self.rm_alloc(argp) - elif nr == nv_gpu.NV_ESC_RM_ALLOC_MEMORY: pass - elif nr == nv_gpu.NV_ESC_RM_CONTROL: return self.rm_control(argp) - elif nr == nv_gpu.NV_ESC_RM_MAP_MEMORY: - st:Any = nv_gpu.nv_ioctl_nvos33_parameters_with_fd.from_address(argp) - obj = self.object_by_handle[st.params.hMemory] - if isinstance(obj, NVUserMode): - file = self.opened_fds[st.fd] - assert isinstance(file, NVDevFileDesc) - file._mapping_userland = True - elif nr == nv_gpu.NV_ESC_RM_FREE: - st = nv_gpu.NVOS00_PARAMETERS.from_address(argp) - self.object_by_handle.pop(st.hObjectOld) - elif nr == nv_gpu.NV_ESC_CARD_INFO: - for i,gpu in enumerate(self.gpus.values()): - st = nv_gpu.nv_ioctl_card_info_t.from_address(argp + i * ctypes.sizeof(nv_gpu.nv_ioctl_card_info_t)) - st.gpu_id = gpu.gpuid - st.pci_info.device_id = 0x2684 - st.valid = True - else: raise RuntimeError(f"Unknown {nr} to nvidiactl") - return 0 - def uvm_ioctl(self, nr, argp): - if nr == nv_gpu.UVM_INITIALIZE: pass - elif nr == nv_gpu.UVM_MM_INITIALIZE: pass - elif nr == nv_gpu.UVM_REGISTER_GPU: - st:Any = nv_gpu.UVM_REGISTER_GPU_PARAMS.from_address(argp) - assert any(all(st.gpu_uuid.uuid[i] == gpu.gpu_uuid()[i] for i in range(16)) for gpu in self.gpus.values()) - elif nr == nv_gpu.UVM_REGISTER_GPU_VASPACE: pass - elif nr == nv_gpu.UVM_ENABLE_PEER_ACCESS: pass # uvm and shared spaced are setup already, no emulation for now - elif nr == nv_gpu.UVM_CREATE_EXTERNAL_RANGE: - st = nv_gpu.UVM_CREATE_EXTERNAL_RANGE_PARAMS.from_address(argp) - libc.mmap(st.base, st.length, mmap.PROT_READ|mmap.PROT_WRITE, MAP_FIXED|mmap.MAP_SHARED|mmap.MAP_ANONYMOUS, -1, 0) - elif nr == nv_gpu.UVM_MAP_EXTERNAL_ALLOCATION: - st = nv_gpu.UVM_MAP_EXTERNAL_ALLOCATION_PARAMS.from_address(argp) - for gpu_attr_id in range(st.gpuAttributesCount): - gpu = None - for _gpu in self.gpus.values(): - if all(st.perGpuAttributes[gpu_attr_id].gpuUuid.uuid[i] == _gpu.gpu_uuid()[i] for i in range(16)): - gpu = _gpu - break - if gpu is None: return -1 - gpu.map_range(st.base, st.length) - elif nr == nv_gpu.UVM_REGISTER_CHANNEL: pass - elif nr == nv_gpu.UVM_FREE: - st = nv_gpu.UVM_FREE_PARAMS.from_address(argp) - libc.munmap(st.base, st.length) - else: raise RuntimeError(f"Unknown {nr} to nvidia-uvm") - return 0 - - def dev_ioctl(self, dev, req, argp): return 0 - def _gpu_mmio_write(self, mv, off, gpu): - any_progress = True - while any_progress: - any_progress = False - for gpu in self.gpus.values(): - for q in gpu.queues: - if q.ctrl.GPGet != q.ctrl.GPPut: - any_progress |= q.execute() \ No newline at end of file diff --git a/tinygrad/test/mockgpu/nv/nvgpu.py b/tinygrad/test/mockgpu/nv/nvgpu.py deleted file mode 100644 index 76239c15..00000000 --- a/tinygrad/test/mockgpu/nv/nvgpu.py +++ /dev/null @@ -1,194 +0,0 @@ -import ctypes, ctypes.util, time -import tinygrad.runtime.autogen.nv_gpu as nv_gpu -from enum import Enum, auto -from test.mockgpu.gpu import VirtGPU -from tinygrad.helpers import to_mv, init_c_struct_t - -def make_qmd_struct_type(): - fields = [] - bits = [(name,dt) for name,dt in nv_gpu.__dict__.items() if name.startswith("NVC6C0_QMDV03_00") and isinstance(dt, tuple)] - bits += [(name+f"_{i}",dt(i)) for name,dt in nv_gpu.__dict__.items() for i in range(8) if name.startswith("NVC6C0_QMDV03_00") and callable(dt)] - bits = sorted(bits, key=lambda x: x[1][1]) - for i,(name, data) in enumerate(bits): - if i > 0 and (gap:=(data[1] - bits[i-1][1][0] - 1)) != 0: fields.append((f"_reserved{i}", ctypes.c_uint32, gap)) - fields.append((name.replace("NVC6C0_QMDV03_00_", "").lower(), ctypes.c_uint32, data[0]-data[1]+1)) - return init_c_struct_t(tuple(fields)) -qmd_struct_t = make_qmd_struct_type() -assert ctypes.sizeof(qmd_struct_t) == 0x40 * 4 - -try: - gpuocelot_lib = ctypes.CDLL(ctypes.util.find_library("gpuocelot")) - gpuocelot_lib.ptx_run.argtypes = [ctypes.c_char_p, ctypes.c_int, ctypes.POINTER(ctypes.c_void_p), ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int] # noqa: E501 -except Exception: pass - -class SchedResult(Enum): CONT = auto(); YIELD = auto() # noqa: E702 - -class GPFIFO: - def __init__(self, token, base, entries_cnt): - self.token, self.base, self.entries_cnt = token, base, entries_cnt - self.gpfifo = to_mv(self.base, self.entries_cnt * 8).cast("Q") - self.ctrl = nv_gpu.AmpereAControlGPFifo.from_address(self.base + self.entries_cnt * 8) - self.state = {} - - # Buf exec state - self.buf = None - self.buf_sz = 0 - self.buf_ptr = 0 - - def _next_dword(self): - assert self.buf is not None - x = self.buf[self.buf_ptr] - self.buf_ptr += 1 - return x - - def _next_header(self): - header = self._next_dword() - typ = (header >> 28) & 0b111 - size = (header >> 16) & 0xFFF - subc = (header >> 13) & 0x7 - mthd = (header & 0x1FFF) << 2 - return typ, size, subc, mthd - - def _state(self, reg): return self.state[reg] - def _state64(self, reg): return (self.state[reg] << 32) + self.state[reg + 4] - def _state64_le(self, reg): return (self.state[reg + 4] << 32) + self.state[reg] - - def _reset_buf_state(self): self.buf, self.buf_ptr = None, 0 - def _set_buf_state(self, gpfifo_entry): - ptr = ((gpfifo_entry >> 2) & 0x3fffffffff) << 2 - sz = ((gpfifo_entry >> 42) & 0x1fffff) << 2 - self.buf = to_mv(ptr, sz).cast("I") - self.buf_sz = sz // 4 - - def execute(self) -> bool: - initial_off = self.buf_ptr - while self.ctrl.GPGet != self.ctrl.GPPut: - self._set_buf_state(self.gpfifo[self.ctrl.GPGet]) - - if not self.execute_buf(): - # Buffer isn't executed fully, check if any progress and report. - # Do not move GPGet in this case, will continue from the same state next time. - return self.buf_ptr != initial_off - - self.ctrl.GPGet = (self.ctrl.GPGet + 1) % self.entries_cnt - self._reset_buf_state() - return True - - def execute_buf(self) -> bool: - while self.buf_ptr < self.buf_sz: - init_off = self.buf_ptr - _, size, _, mthd = self._next_header() - cmd_end_off = self.buf_ptr + size - - while self.buf_ptr < cmd_end_off: - res = self.execute_cmd(mthd) - if res == SchedResult.YIELD: - self.buf_ptr = init_off # just revert to the header - return False - mthd += 4 - return True - - def execute_qmd(self, qmd_addr): - qmd = qmd_struct_t.from_address(qmd_addr) - prg_addr = qmd.program_address_lower + (qmd.program_address_upper << 32) - const0 = to_mv(qmd.constant_buffer_addr_lower_0 + (qmd.constant_buffer_addr_upper_0 << 32), 0x160).cast('I') - args_cnt, vals_cnt = const0[80], const0[81] - args_addr = qmd.constant_buffer_addr_lower_0 + (qmd.constant_buffer_addr_upper_0 << 32) + 0x160 - args = to_mv(args_addr, args_cnt*8).cast('Q') - vals = to_mv(args_addr + args_cnt*8, vals_cnt*4).cast('I') - cargs = [ctypes.cast(args[i], ctypes.c_void_p) for i in range(args_cnt)] + [ctypes.cast(vals[i], ctypes.c_void_p) for i in range(vals_cnt)] - gx, gy, gz = qmd.cta_raster_width, qmd.cta_raster_height, qmd.cta_raster_depth - lx, ly, lz = qmd.cta_thread_dimension0, qmd.cta_thread_dimension1, qmd.cta_thread_dimension2 - gpuocelot_lib.ptx_run(ctypes.cast(prg_addr, ctypes.c_char_p), args_cnt+vals_cnt, (ctypes.c_void_p*len(cargs))(*cargs), lx, ly, lz, gx, gy, gz, 0) - if qmd.release0_enable: - rel0 = to_mv(qmd.release0_address_lower + (qmd.release0_address_upper << 32), 0x10).cast('Q') - rel0[0] = qmd.release0_payload_lower + (qmd.release0_payload_upper << 32) - rel0[1] = int(time.perf_counter() * 1e9) - if qmd.release1_enable: - rel1 = to_mv(qmd.release1_address_lower + (qmd.release1_address_upper << 32), 0x10).cast('Q') - rel1[0] = qmd.release1_payload_lower + (qmd.release1_payload_upper << 32) - rel1[1] = int(time.perf_counter() * 1e9) - if qmd.dependent_qmd0_enable: - if qmd.dependent_qmd0_action == 1: self.execute_qmd(qmd.dependent_qmd0_pointer << 8) - else: raise RuntimeError("unsupported dependent qmd action") - - def execute_cmd(self, cmd) -> SchedResult: - if cmd == nv_gpu.NVC56F_SEM_EXECUTE: return self._exec_signal() - elif cmd == nv_gpu.NVC6C0_LAUNCH_DMA: return self._exec_nvc6c0_dma() - elif cmd == nv_gpu.NVC6B5_LAUNCH_DMA: return self._exec_nvc6b5_dma() - elif cmd == nv_gpu.NVC6C0_SEND_SIGNALING_PCAS2_B: return self._exec_pcas2() - elif cmd == 0x0320: return self._exec_load_inline_qmd() # NVC6C0_LOAD_INLINE_QMD_DATA - else: self.state[cmd] = self._next_dword() # just state update - return SchedResult.CONT - - def _exec_signal(self) -> SchedResult: - signal = self._state64_le(nv_gpu.NVC56F_SEM_ADDR_LO) - val = self._state64_le(nv_gpu.NVC56F_SEM_PAYLOAD_LO) - flags = self._next_dword() - typ = (flags >> 0) & 0b111 - timestamp = (flags & (1 << 25)) == (1 << 25) - if typ == 1: - to_mv(signal, 8).cast('Q')[0] = val - if timestamp: to_mv(signal + 8, 8).cast('Q')[0] = int(time.perf_counter() * 1e9) - elif typ == 3: - mval = to_mv(signal, 8).cast('Q')[0] - return SchedResult.CONT if mval >= val else SchedResult.YIELD - else: raise RuntimeError(f"Unsupported type={typ} in exec wait/signal") - return SchedResult.CONT - - def _exec_load_inline_qmd(self): - qmd_addr = self._state64(nv_gpu.NVC6C0_SET_INLINE_QMD_ADDRESS_A) << 8 - assert qmd_addr != 0x0, f"invalid qmd address {qmd_addr}" - qmd_data = [self._next_dword() for _ in range(0x40)] - cdata = (ctypes.c_uint32 * len(qmd_data))(*qmd_data) - ctypes.memmove(qmd_addr, cdata, 0x40 * 4) - self.execute_qmd(qmd_addr) - - def _exec_nvc6c0_dma(self): - addr = self._state64(nv_gpu.NVC6C0_OFFSET_OUT_UPPER) - sz = self._state(nv_gpu.NVC6C0_LINE_LENGTH_IN) - lanes = self._state(nv_gpu.NVC6C0_LINE_COUNT) - assert lanes == 1, f"unsupported lanes > 1 in _exec_nvc6c0_dma: {lanes}" - flags = self._next_dword() - assert flags == 0x41, f"unsupported flags in _exec_nvc6c0_dma: {flags}" - typ, dsize, _, mthd = self._next_header() - assert typ == 6 and mthd == nv_gpu.NVC6C0_LOAD_INLINE_DATA, f"Expected inline data not found after nvc6c0_dma, {typ=} {mthd=}" - copy_data = [self._next_dword() for _ in range(dsize)] - assert len(copy_data) * 4 == sz, f"different copy sizes in _exec_nvc6c0_dma: {len(copy_data) * 4} != {sz}" - cdata = (ctypes.c_uint32 * len(copy_data))(*copy_data) - ctypes.memmove(addr, cdata, sz) - - def _exec_nvc6b5_dma(self): - flags = self._next_dword() - if (flags & 0b11) != 0: - src = self._state64(nv_gpu.NVC6B5_OFFSET_IN_UPPER) - dst = self._state64(nv_gpu.NVC6B5_OFFSET_OUT_UPPER) - sz = self._state(nv_gpu.NVC6B5_LINE_LENGTH_IN) - assert flags == 0x182, f"unsupported flags in _exec_nvc6b5_dma: {flags}" - ctypes.memmove(dst, src, sz) - elif ((flags >> 3) & 0b11) != 0: - src = to_mv(self._state64(nv_gpu.NVC6B5_SET_SEMAPHORE_A), 0x10).cast('Q') - val = self._state(nv_gpu.NVC6B5_SET_SEMAPHORE_PAYLOAD) - src[0] = val - src[1] = int(time.perf_counter() * 1e9) - else: raise RuntimeError("unknown nvc6b5_dma flags") - - def _exec_pcas2(self): - qmd_addr = self._state(nv_gpu.NVC6C0_SEND_PCAS_A) << 8 - typ = self._next_dword() - if typ == 2 or typ == 9: # schedule - self.execute_qmd(qmd_addr) - -class NVGPU(VirtGPU): - def __init__(self, gpuid): - super().__init__(gpuid) - self.regs = {} - self.mapped_ranges = set() - self.queues = [] - - def map_range(self, vaddr, size): self.mapped_ranges.add((vaddr, size)) - def unmap_range(self, vaddr, size): self.mapped_ranges.remove((vaddr, size)) - def add_gpfifo(self, base, entries_count): - self.queues.append(GPFIFO(token:=len(self.queues), base, entries_count)) - return token - def gpu_uuid(self, sz=16): return self.gpuid.to_bytes(sz, byteorder='big', signed=False) diff --git a/tinygrad/test/mockgpu/usb.py b/tinygrad/test/mockgpu/usb.py deleted file mode 100644 index 460b4610..00000000 --- a/tinygrad/test/mockgpu/usb.py +++ /dev/null @@ -1,16 +0,0 @@ -class MockUSB: - def __init__(self, mem): - self.mem = mem - - def read(self, address, size): - return bytes(self.mem[address:address+size]) - - def write(self, address, data, ignore_cache=False): - self.mem[address:address+len(data)] = data - - def pcie_mem_req(self, address, value=None, size=1): - if value is None: return int.from_bytes(self.mem[address:address+size], "little") - else: self.mem[address:address+size] = value.to_bytes(size, "little") - - def pcie_mem_write(self, address, values, size): - for i, value in enumerate(values): self.pcie_mem_req(address + i * size, value, size) diff --git a/tinygrad/test/models/__init__.py b/tinygrad/test/models/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/test/models/efficientnet/Chicken.jpg b/tinygrad/test/models/efficientnet/Chicken.jpg deleted file mode 100644 index 9dd4815d..00000000 Binary files a/tinygrad/test/models/efficientnet/Chicken.jpg and /dev/null differ diff --git a/tinygrad/test/models/efficientnet/car.jpg b/tinygrad/test/models/efficientnet/car.jpg deleted file mode 100644 index 32154e03..00000000 Binary files a/tinygrad/test/models/efficientnet/car.jpg and /dev/null differ diff --git a/tinygrad/test/models/efficientnet/imagenet1000_clsidx_to_labels.txt b/tinygrad/test/models/efficientnet/imagenet1000_clsidx_to_labels.txt deleted file mode 100644 index 2e3ae32a..00000000 --- a/tinygrad/test/models/efficientnet/imagenet1000_clsidx_to_labels.txt +++ /dev/null @@ -1,1000 +0,0 @@ -{0: 'tench, Tinca tinca', - 1: 'goldfish, Carassius auratus', - 2: 'great white shark, white shark, man-eater, man-eating shark, Carcharodon carcharias', - 3: 'tiger shark, Galeocerdo cuvieri', - 4: 'hammerhead, hammerhead shark', - 5: 'electric ray, crampfish, numbfish, torpedo', - 6: 'stingray', - 7: 'cock', - 8: 'hen', - 9: 'ostrich, Struthio camelus', - 10: 'brambling, Fringilla montifringilla', - 11: 'goldfinch, Carduelis carduelis', - 12: 'house finch, linnet, Carpodacus mexicanus', - 13: 'junco, snowbird', - 14: 'indigo bunting, indigo finch, indigo bird, Passerina cyanea', - 15: 'robin, American robin, Turdus migratorius', - 16: 'bulbul', - 17: 'jay', - 18: 'magpie', - 19: 'chickadee', - 20: 'water ouzel, dipper', - 21: 'kite', - 22: 'bald eagle, American eagle, Haliaeetus leucocephalus', - 23: 'vulture', - 24: 'great grey owl, great gray owl, Strix nebulosa', - 25: 'European fire salamander, Salamandra salamandra', - 26: 'common newt, Triturus vulgaris', - 27: 'eft', - 28: 'spotted salamander, Ambystoma maculatum', - 29: 'axolotl, mud puppy, Ambystoma mexicanum', - 30: 'bullfrog, Rana catesbeiana', - 31: 'tree frog, tree-frog', - 32: 'tailed frog, bell toad, ribbed toad, tailed toad, Ascaphus trui', - 33: 'loggerhead, loggerhead turtle, Caretta caretta', - 34: 'leatherback turtle, leatherback, leathery turtle, Dermochelys coriacea', - 35: 'mud turtle', - 36: 'terrapin', - 37: 'box turtle, box tortoise', - 38: 'banded gecko', - 39: 'common iguana, iguana, Iguana iguana', - 40: 'American chameleon, anole, Anolis carolinensis', - 41: 'whiptail, whiptail lizard', - 42: 'agama', - 43: 'frilled lizard, Chlamydosaurus kingi', - 44: 'alligator lizard', - 45: 'Gila monster, Heloderma suspectum', - 46: 'green lizard, Lacerta viridis', - 47: 'African chameleon, Chamaeleo chamaeleon', - 48: 'Komodo dragon, Komodo lizard, dragon lizard, giant lizard, Varanus komodoensis', - 49: 'African crocodile, Nile crocodile, Crocodylus niloticus', - 50: 'American alligator, Alligator mississipiensis', - 51: 'triceratops', - 52: 'thunder snake, worm snake, Carphophis amoenus', - 53: 'ringneck snake, ring-necked snake, ring snake', - 54: 'hognose snake, puff adder, sand viper', - 55: 'green snake, grass snake', - 56: 'king snake, kingsnake', - 57: 'garter snake, grass snake', - 58: 'water snake', - 59: 'vine snake', - 60: 'night snake, Hypsiglena torquata', - 61: 'boa constrictor, Constrictor constrictor', - 62: 'rock python, rock snake, Python sebae', - 63: 'Indian cobra, Naja naja', - 64: 'green mamba', - 65: 'sea snake', - 66: 'horned viper, cerastes, sand viper, horned asp, Cerastes cornutus', - 67: 'diamondback, diamondback rattlesnake, Crotalus adamanteus', - 68: 'sidewinder, horned rattlesnake, Crotalus cerastes', - 69: 'trilobite', - 70: 'harvestman, daddy longlegs, Phalangium opilio', - 71: 'scorpion', - 72: 'black and gold garden spider, Argiope aurantia', - 73: 'barn spider, Araneus cavaticus', - 74: 'garden spider, Aranea diademata', - 75: 'black widow, Latrodectus mactans', - 76: 'tarantula', - 77: 'wolf spider, hunting spider', - 78: 'tick', - 79: 'centipede', - 80: 'black grouse', - 81: 'ptarmigan', - 82: 'ruffed grouse, partridge, Bonasa umbellus', - 83: 'prairie chicken, prairie grouse, prairie fowl', - 84: 'peacock', - 85: 'quail', - 86: 'partridge', - 87: 'African grey, African gray, Psittacus erithacus', - 88: 'macaw', - 89: 'sulphur-crested cockatoo, Kakatoe galerita, Cacatua galerita', - 90: 'lorikeet', - 91: 'coucal', - 92: 'bee eater', - 93: 'hornbill', - 94: 'hummingbird', - 95: 'jacamar', - 96: 'toucan', - 97: 'drake', - 98: 'red-breasted merganser, Mergus serrator', - 99: 'goose', - 100: 'black swan, Cygnus atratus', - 101: 'tusker', - 102: 'echidna, spiny anteater, anteater', - 103: 'platypus, duckbill, duckbilled platypus, duck-billed platypus, Ornithorhynchus anatinus', - 104: 'wallaby, brush kangaroo', - 105: 'koala, koala bear, kangaroo bear, native bear, Phascolarctos cinereus', - 106: 'wombat', - 107: 'jellyfish', - 108: 'sea anemone, anemone', - 109: 'brain coral', - 110: 'flatworm, platyhelminth', - 111: 'nematode, nematode worm, roundworm', - 112: 'conch', - 113: 'snail', - 114: 'slug', - 115: 'sea slug, nudibranch', - 116: 'chiton, coat-of-mail shell, sea cradle, polyplacophore', - 117: 'chambered nautilus, pearly nautilus, nautilus', - 118: 'Dungeness crab, Cancer magister', - 119: 'rock crab, Cancer irroratus', - 120: 'fiddler crab', - 121: 'king crab, Alaska crab, Alaskan king crab, Alaska king crab, Paralithodes camtschatica', - 122: 'American lobster, Northern lobster, Maine lobster, Homarus americanus', - 123: 'spiny lobster, langouste, rock lobster, crawfish, crayfish, sea crawfish', - 124: 'crayfish, crawfish, crawdad, crawdaddy', - 125: 'hermit crab', - 126: 'isopod', - 127: 'white stork, Ciconia ciconia', - 128: 'black stork, Ciconia nigra', - 129: 'spoonbill', - 130: 'flamingo', - 131: 'little blue heron, Egretta caerulea', - 132: 'American egret, great white heron, Egretta albus', - 133: 'bittern', - 134: 'crane', - 135: 'limpkin, Aramus pictus', - 136: 'European gallinule, Porphyrio porphyrio', - 137: 'American coot, marsh hen, mud hen, water hen, Fulica americana', - 138: 'bustard', - 139: 'ruddy turnstone, Arenaria interpres', - 140: 'red-backed sandpiper, dunlin, Erolia alpina', - 141: 'redshank, Tringa totanus', - 142: 'dowitcher', - 143: 'oystercatcher, oyster catcher', - 144: 'pelican', - 145: 'king penguin, Aptenodytes patagonica', - 146: 'albatross, mollymawk', - 147: 'grey whale, gray whale, devilfish, Eschrichtius gibbosus, Eschrichtius robustus', - 148: 'killer whale, killer, orca, grampus, sea wolf, Orcinus orca', - 149: 'dugong, Dugong dugon', - 150: 'sea lion', - 151: 'Chihuahua', - 152: 'Japanese spaniel', - 153: 'Maltese dog, Maltese terrier, Maltese', - 154: 'Pekinese, Pekingese, Peke', - 155: 'Shih-Tzu', - 156: 'Blenheim spaniel', - 157: 'papillon', - 158: 'toy terrier', - 159: 'Rhodesian ridgeback', - 160: 'Afghan hound, Afghan', - 161: 'basset, basset hound', - 162: 'beagle', - 163: 'bloodhound, sleuthhound', - 164: 'bluetick', - 165: 'black-and-tan coonhound', - 166: 'Walker hound, Walker foxhound', - 167: 'English foxhound', - 168: 'redbone', - 169: 'borzoi, Russian wolfhound', - 170: 'Irish wolfhound', - 171: 'Italian greyhound', - 172: 'whippet', - 173: 'Ibizan hound, Ibizan Podenco', - 174: 'Norwegian elkhound, elkhound', - 175: 'otterhound, otter hound', - 176: 'Saluki, gazelle hound', - 177: 'Scottish deerhound, deerhound', - 178: 'Weimaraner', - 179: 'Staffordshire bullterrier, Staffordshire bull terrier', - 180: 'American Staffordshire terrier, Staffordshire terrier, American pit bull terrier, pit bull terrier', - 181: 'Bedlington terrier', - 182: 'Border terrier', - 183: 'Kerry blue terrier', - 184: 'Irish terrier', - 185: 'Norfolk terrier', - 186: 'Norwich terrier', - 187: 'Yorkshire terrier', - 188: 'wire-haired fox terrier', - 189: 'Lakeland terrier', - 190: 'Sealyham terrier, Sealyham', - 191: 'Airedale, Airedale terrier', - 192: 'cairn, cairn terrier', - 193: 'Australian terrier', - 194: 'Dandie Dinmont, Dandie Dinmont terrier', - 195: 'Boston bull, Boston terrier', - 196: 'miniature schnauzer', - 197: 'giant schnauzer', - 198: 'standard schnauzer', - 199: 'Scotch terrier, Scottish terrier, Scottie', - 200: 'Tibetan terrier, chrysanthemum dog', - 201: 'silky terrier, Sydney silky', - 202: 'soft-coated wheaten terrier', - 203: 'West Highland white terrier', - 204: 'Lhasa, Lhasa apso', - 205: 'flat-coated retriever', - 206: 'curly-coated retriever', - 207: 'golden retriever', - 208: 'Labrador retriever', - 209: 'Chesapeake Bay retriever', - 210: 'German short-haired pointer', - 211: 'vizsla, Hungarian pointer', - 212: 'English setter', - 213: 'Irish setter, red setter', - 214: 'Gordon setter', - 215: 'Brittany spaniel', - 216: 'clumber, clumber spaniel', - 217: 'English springer, English springer spaniel', - 218: 'Welsh springer spaniel', - 219: 'cocker spaniel, English cocker spaniel, cocker', - 220: 'Sussex spaniel', - 221: 'Irish water spaniel', - 222: 'kuvasz', - 223: 'schipperke', - 224: 'groenendael', - 225: 'malinois', - 226: 'briard', - 227: 'kelpie', - 228: 'komondor', - 229: 'Old English sheepdog, bobtail', - 230: 'Shetland sheepdog, Shetland sheep dog, Shetland', - 231: 'collie', - 232: 'Border collie', - 233: 'Bouvier des Flandres, Bouviers des Flandres', - 234: 'Rottweiler', - 235: 'German shepherd, German shepherd dog, German police dog, alsatian', - 236: 'Doberman, Doberman pinscher', - 237: 'miniature pinscher', - 238: 'Greater Swiss Mountain dog', - 239: 'Bernese mountain dog', - 240: 'Appenzeller', - 241: 'EntleBucher', - 242: 'boxer', - 243: 'bull mastiff', - 244: 'Tibetan mastiff', - 245: 'French bulldog', - 246: 'Great Dane', - 247: 'Saint Bernard, St Bernard', - 248: 'Eskimo dog, husky', - 249: 'malamute, malemute, Alaskan malamute', - 250: 'Siberian husky', - 251: 'dalmatian, coach dog, carriage dog', - 252: 'affenpinscher, monkey pinscher, monkey dog', - 253: 'basenji', - 254: 'pug, pug-dog', - 255: 'Leonberg', - 256: 'Newfoundland, Newfoundland dog', - 257: 'Great Pyrenees', - 258: 'Samoyed, Samoyede', - 259: 'Pomeranian', - 260: 'chow, chow chow', - 261: 'keeshond', - 262: 'Brabancon griffon', - 263: 'Pembroke, Pembroke Welsh corgi', - 264: 'Cardigan, Cardigan Welsh corgi', - 265: 'toy poodle', - 266: 'miniature poodle', - 267: 'standard poodle', - 268: 'Mexican hairless', - 269: 'timber wolf, grey wolf, gray wolf, Canis lupus', - 270: 'white wolf, Arctic wolf, Canis lupus tundrarum', - 271: 'red wolf, maned wolf, Canis rufus, Canis niger', - 272: 'coyote, prairie wolf, brush wolf, Canis latrans', - 273: 'dingo, warrigal, warragal, Canis dingo', - 274: 'dhole, Cuon alpinus', - 275: 'African hunting dog, hyena dog, Cape hunting dog, Lycaon pictus', - 276: 'hyena, hyaena', - 277: 'red fox, Vulpes vulpes', - 278: 'kit fox, Vulpes macrotis', - 279: 'Arctic fox, white fox, Alopex lagopus', - 280: 'grey fox, gray fox, Urocyon cinereoargenteus', - 281: 'tabby, tabby cat', - 282: 'tiger cat', - 283: 'Persian cat', - 284: 'Siamese cat, Siamese', - 285: 'Egyptian cat', - 286: 'cougar, puma, catamount, mountain lion, painter, panther, Felis concolor', - 287: 'lynx, catamount', - 288: 'leopard, Panthera pardus', - 289: 'snow leopard, ounce, Panthera uncia', - 290: 'jaguar, panther, Panthera onca, Felis onca', - 291: 'lion, king of beasts, Panthera leo', - 292: 'tiger, Panthera tigris', - 293: 'cheetah, chetah, Acinonyx jubatus', - 294: 'brown bear, bruin, Ursus arctos', - 295: 'American black bear, black bear, Ursus americanus, Euarctos americanus', - 296: 'ice bear, polar bear, Ursus Maritimus, Thalarctos maritimus', - 297: 'sloth bear, Melursus ursinus, Ursus ursinus', - 298: 'mongoose', - 299: 'meerkat, mierkat', - 300: 'tiger beetle', - 301: 'ladybug, ladybeetle, lady beetle, ladybird, ladybird beetle', - 302: 'ground beetle, carabid beetle', - 303: 'long-horned beetle, longicorn, longicorn beetle', - 304: 'leaf beetle, chrysomelid', - 305: 'dung beetle', - 306: 'rhinoceros beetle', - 307: 'weevil', - 308: 'fly', - 309: 'bee', - 310: 'ant, emmet, pismire', - 311: 'grasshopper, hopper', - 312: 'cricket', - 313: 'walking stick, walkingstick, stick insect', - 314: 'cockroach, roach', - 315: 'mantis, mantid', - 316: 'cicada, cicala', - 317: 'leafhopper', - 318: 'lacewing, lacewing fly', - 319: "dragonfly, darning needle, devil's darning needle, sewing needle, snake feeder, snake doctor, mosquito hawk, skeeter hawk", - 320: 'damselfly', - 321: 'admiral', - 322: 'ringlet, ringlet butterfly', - 323: 'monarch, monarch butterfly, milkweed butterfly, Danaus plexippus', - 324: 'cabbage butterfly', - 325: 'sulphur butterfly, sulfur butterfly', - 326: 'lycaenid, lycaenid butterfly', - 327: 'starfish, sea star', - 328: 'sea urchin', - 329: 'sea cucumber, holothurian', - 330: 'wood rabbit, cottontail, cottontail rabbit', - 331: 'hare', - 332: 'Angora, Angora rabbit', - 333: 'hamster', - 334: 'porcupine, hedgehog', - 335: 'fox squirrel, eastern fox squirrel, Sciurus niger', - 336: 'marmot', - 337: 'beaver', - 338: 'guinea pig, Cavia cobaya', - 339: 'sorrel', - 340: 'zebra', - 341: 'hog, pig, grunter, squealer, Sus scrofa', - 342: 'wild boar, boar, Sus scrofa', - 343: 'warthog', - 344: 'hippopotamus, hippo, river horse, Hippopotamus amphibius', - 345: 'ox', - 346: 'water buffalo, water ox, Asiatic buffalo, Bubalus bubalis', - 347: 'bison', - 348: 'ram, tup', - 349: 'bighorn, bighorn sheep, cimarron, Rocky Mountain bighorn, Rocky Mountain sheep, Ovis canadensis', - 350: 'ibex, Capra ibex', - 351: 'hartebeest', - 352: 'impala, Aepyceros melampus', - 353: 'gazelle', - 354: 'Arabian camel, dromedary, Camelus dromedarius', - 355: 'llama', - 356: 'weasel', - 357: 'mink', - 358: 'polecat, fitch, foulmart, foumart, Mustela putorius', - 359: 'black-footed ferret, ferret, Mustela nigripes', - 360: 'otter', - 361: 'skunk, polecat, wood pussy', - 362: 'badger', - 363: 'armadillo', - 364: 'three-toed sloth, ai, Bradypus tridactylus', - 365: 'orangutan, orang, orangutang, Pongo pygmaeus', - 366: 'gorilla, Gorilla gorilla', - 367: 'chimpanzee, chimp, Pan troglodytes', - 368: 'gibbon, Hylobates lar', - 369: 'siamang, Hylobates syndactylus, Symphalangus syndactylus', - 370: 'guenon, guenon monkey', - 371: 'patas, hussar monkey, Erythrocebus patas', - 372: 'baboon', - 373: 'macaque', - 374: 'langur', - 375: 'colobus, colobus monkey', - 376: 'proboscis monkey, Nasalis larvatus', - 377: 'marmoset', - 378: 'capuchin, ringtail, Cebus capucinus', - 379: 'howler monkey, howler', - 380: 'titi, titi monkey', - 381: 'spider monkey, Ateles geoffroyi', - 382: 'squirrel monkey, Saimiri sciureus', - 383: 'Madagascar cat, ring-tailed lemur, Lemur catta', - 384: 'indri, indris, Indri indri, Indri brevicaudatus', - 385: 'Indian elephant, Elephas maximus', - 386: 'African elephant, Loxodonta africana', - 387: 'lesser panda, red panda, panda, bear cat, cat bear, Ailurus fulgens', - 388: 'giant panda, panda, panda bear, coon bear, Ailuropoda melanoleuca', - 389: 'barracouta, snoek', - 390: 'eel', - 391: 'coho, cohoe, coho salmon, blue jack, silver salmon, Oncorhynchus kisutch', - 392: 'rock beauty, Holocanthus tricolor', - 393: 'anemone fish', - 394: 'sturgeon', - 395: 'gar, garfish, garpike, billfish, Lepisosteus osseus', - 396: 'lionfish', - 397: 'puffer, pufferfish, blowfish, globefish', - 398: 'abacus', - 399: 'abaya', - 400: "academic gown, academic robe, judge's robe", - 401: 'accordion, piano accordion, squeeze box', - 402: 'acoustic guitar', - 403: 'aircraft carrier, carrier, flattop, attack aircraft carrier', - 404: 'airliner', - 405: 'airship, dirigible', - 406: 'altar', - 407: 'ambulance', - 408: 'amphibian, amphibious vehicle', - 409: 'analog clock', - 410: 'apiary, bee house', - 411: 'apron', - 412: 'ashcan, trash can, garbage can, wastebin, ash bin, ash-bin, ashbin, dustbin, trash barrel, trash bin', - 413: 'assault rifle, assault gun', - 414: 'backpack, back pack, knapsack, packsack, rucksack, haversack', - 415: 'bakery, bakeshop, bakehouse', - 416: 'balance beam, beam', - 417: 'balloon', - 418: 'ballpoint, ballpoint pen, ballpen, Biro', - 419: 'Band Aid', - 420: 'banjo', - 421: 'bannister, banister, balustrade, balusters, handrail', - 422: 'barbell', - 423: 'barber chair', - 424: 'barbershop', - 425: 'barn', - 426: 'barometer', - 427: 'barrel, cask', - 428: 'barrow, garden cart, lawn cart, wheelbarrow', - 429: 'baseball', - 430: 'basketball', - 431: 'bassinet', - 432: 'bassoon', - 433: 'bathing cap, swimming cap', - 434: 'bath towel', - 435: 'bathtub, bathing tub, bath, tub', - 436: 'beach wagon, station wagon, wagon, estate car, beach waggon, station waggon, waggon', - 437: 'beacon, lighthouse, beacon light, pharos', - 438: 'beaker', - 439: 'bearskin, busby, shako', - 440: 'beer bottle', - 441: 'beer glass', - 442: 'bell cote, bell cot', - 443: 'bib', - 444: 'bicycle-built-for-two, tandem bicycle, tandem', - 445: 'bikini, two-piece', - 446: 'binder, ring-binder', - 447: 'binoculars, field glasses, opera glasses', - 448: 'birdhouse', - 449: 'boathouse', - 450: 'bobsled, bobsleigh, bob', - 451: 'bolo tie, bolo, bola tie, bola', - 452: 'bonnet, poke bonnet', - 453: 'bookcase', - 454: 'bookshop, bookstore, bookstall', - 455: 'bottlecap', - 456: 'bow', - 457: 'bow tie, bow-tie, bowtie', - 458: 'brass, memorial tablet, plaque', - 459: 'brassiere, bra, bandeau', - 460: 'breakwater, groin, groyne, mole, bulwark, seawall, jetty', - 461: 'breastplate, aegis, egis', - 462: 'broom', - 463: 'bucket, pail', - 464: 'buckle', - 465: 'bulletproof vest', - 466: 'bullet train, bullet', - 467: 'butcher shop, meat market', - 468: 'cab, hack, taxi, taxicab', - 469: 'caldron, cauldron', - 470: 'candle, taper, wax light', - 471: 'cannon', - 472: 'canoe', - 473: 'can opener, tin opener', - 474: 'cardigan', - 475: 'car mirror', - 476: 'carousel, carrousel, merry-go-round, roundabout, whirligig', - 477: "carpenter's kit, tool kit", - 478: 'carton', - 479: 'car wheel', - 480: 'cash machine, cash dispenser, automated teller machine, automatic teller machine, automated teller, automatic teller, ATM', - 481: 'cassette', - 482: 'cassette player', - 483: 'castle', - 484: 'catamaran', - 485: 'CD player', - 486: 'cello, violoncello', - 487: 'cellular telephone, cellular phone, cellphone, cell, mobile phone', - 488: 'chain', - 489: 'chainlink fence', - 490: 'chain mail, ring mail, mail, chain armor, chain armour, ring armor, ring armour', - 491: 'chain saw, chainsaw', - 492: 'chest', - 493: 'chiffonier, commode', - 494: 'chime, bell, gong', - 495: 'china cabinet, china closet', - 496: 'Christmas stocking', - 497: 'church, church building', - 498: 'cinema, movie theater, movie theatre, movie house, picture palace', - 499: 'cleaver, meat cleaver, chopper', - 500: 'cliff dwelling', - 501: 'cloak', - 502: 'clog, geta, patten, sabot', - 503: 'cocktail shaker', - 504: 'coffee mug', - 505: 'coffeepot', - 506: 'coil, spiral, volute, whorl, helix', - 507: 'combination lock', - 508: 'computer keyboard, keypad', - 509: 'confectionery, confectionary, candy store', - 510: 'container ship, containership, container vessel', - 511: 'convertible', - 512: 'corkscrew, bottle screw', - 513: 'cornet, horn, trumpet, trump', - 514: 'cowboy boot', - 515: 'cowboy hat, ten-gallon hat', - 516: 'cradle', - 517: 'crane', - 518: 'crash helmet', - 519: 'crate', - 520: 'crib, cot', - 521: 'Crock Pot', - 522: 'croquet ball', - 523: 'crutch', - 524: 'cuirass', - 525: 'dam, dike, dyke', - 526: 'desk', - 527: 'desktop computer', - 528: 'dial telephone, dial phone', - 529: 'diaper, nappy, napkin', - 530: 'digital clock', - 531: 'digital watch', - 532: 'dining table, board', - 533: 'dishrag, dishcloth', - 534: 'dishwasher, dish washer, dishwashing machine', - 535: 'disk brake, disc brake', - 536: 'dock, dockage, docking facility', - 537: 'dogsled, dog sled, dog sleigh', - 538: 'dome', - 539: 'doormat, welcome mat', - 540: 'drilling platform, offshore rig', - 541: 'drum, membranophone, tympan', - 542: 'drumstick', - 543: 'dumbbell', - 544: 'Dutch oven', - 545: 'electric fan, blower', - 546: 'electric guitar', - 547: 'electric locomotive', - 548: 'entertainment center', - 549: 'envelope', - 550: 'espresso maker', - 551: 'face powder', - 552: 'feather boa, boa', - 553: 'file, file cabinet, filing cabinet', - 554: 'fireboat', - 555: 'fire engine, fire truck', - 556: 'fire screen, fireguard', - 557: 'flagpole, flagstaff', - 558: 'flute, transverse flute', - 559: 'folding chair', - 560: 'football helmet', - 561: 'forklift', - 562: 'fountain', - 563: 'fountain pen', - 564: 'four-poster', - 565: 'freight car', - 566: 'French horn, horn', - 567: 'frying pan, frypan, skillet', - 568: 'fur coat', - 569: 'garbage truck, dustcart', - 570: 'gasmask, respirator, gas helmet', - 571: 'gas pump, gasoline pump, petrol pump, island dispenser', - 572: 'goblet', - 573: 'go-kart', - 574: 'golf ball', - 575: 'golfcart, golf cart', - 576: 'gondola', - 577: 'gong, tam-tam', - 578: 'gown', - 579: 'grand piano, grand', - 580: 'greenhouse, nursery, glasshouse', - 581: 'grille, radiator grille', - 582: 'grocery store, grocery, food market, market', - 583: 'guillotine', - 584: 'hair slide', - 585: 'hair spray', - 586: 'half track', - 587: 'hammer', - 588: 'hamper', - 589: 'hand blower, blow dryer, blow drier, hair dryer, hair drier', - 590: 'hand-held computer, hand-held microcomputer', - 591: 'handkerchief, hankie, hanky, hankey', - 592: 'hard disc, hard disk, fixed disk', - 593: 'harmonica, mouth organ, harp, mouth harp', - 594: 'harp', - 595: 'harvester, reaper', - 596: 'hatchet', - 597: 'holster', - 598: 'home theater, home theatre', - 599: 'honeycomb', - 600: 'hook, claw', - 601: 'hoopskirt, crinoline', - 602: 'horizontal bar, high bar', - 603: 'horse cart, horse-cart', - 604: 'hourglass', - 605: 'iPod', - 606: 'iron, smoothing iron', - 607: "jack-o'-lantern", - 608: 'jean, blue jean, denim', - 609: 'jeep, landrover', - 610: 'jersey, T-shirt, tee shirt', - 611: 'jigsaw puzzle', - 612: 'jinrikisha, ricksha, rickshaw', - 613: 'joystick', - 614: 'kimono', - 615: 'knee pad', - 616: 'knot', - 617: 'lab coat, laboratory coat', - 618: 'ladle', - 619: 'lampshade, lamp shade', - 620: 'laptop, laptop computer', - 621: 'lawn mower, mower', - 622: 'lens cap, lens cover', - 623: 'letter opener, paper knife, paperknife', - 624: 'library', - 625: 'lifeboat', - 626: 'lighter, light, igniter, ignitor', - 627: 'limousine, limo', - 628: 'liner, ocean liner', - 629: 'lipstick, lip rouge', - 630: 'Loafer', - 631: 'lotion', - 632: 'loudspeaker, speaker, speaker unit, loudspeaker system, speaker system', - 633: "loupe, jeweler's loupe", - 634: 'lumbermill, sawmill', - 635: 'magnetic compass', - 636: 'mailbag, postbag', - 637: 'mailbox, letter box', - 638: 'maillot', - 639: 'maillot, tank suit', - 640: 'manhole cover', - 641: 'maraca', - 642: 'marimba, xylophone', - 643: 'mask', - 644: 'matchstick', - 645: 'maypole', - 646: 'maze, labyrinth', - 647: 'measuring cup', - 648: 'medicine chest, medicine cabinet', - 649: 'megalith, megalithic structure', - 650: 'microphone, mike', - 651: 'microwave, microwave oven', - 652: 'military uniform', - 653: 'milk can', - 654: 'minibus', - 655: 'miniskirt, mini', - 656: 'minivan', - 657: 'missile', - 658: 'mitten', - 659: 'mixing bowl', - 660: 'mobile home, manufactured home', - 661: 'Model T', - 662: 'modem', - 663: 'monastery', - 664: 'monitor', - 665: 'moped', - 666: 'mortar', - 667: 'mortarboard', - 668: 'mosque', - 669: 'mosquito net', - 670: 'motor scooter, scooter', - 671: 'mountain bike, all-terrain bike, off-roader', - 672: 'mountain tent', - 673: 'mouse, computer mouse', - 674: 'mousetrap', - 675: 'moving van', - 676: 'muzzle', - 677: 'nail', - 678: 'neck brace', - 679: 'necklace', - 680: 'nipple', - 681: 'notebook, notebook computer', - 682: 'obelisk', - 683: 'oboe, hautboy, hautbois', - 684: 'ocarina, sweet potato', - 685: 'odometer, hodometer, mileometer, milometer', - 686: 'oil filter', - 687: 'organ, pipe organ', - 688: 'oscilloscope, scope, cathode-ray oscilloscope, CRO', - 689: 'overskirt', - 690: 'oxcart', - 691: 'oxygen mask', - 692: 'packet', - 693: 'paddle, boat paddle', - 694: 'paddlewheel, paddle wheel', - 695: 'padlock', - 696: 'paintbrush', - 697: "pajama, pyjama, pj's, jammies", - 698: 'palace', - 699: 'panpipe, pandean pipe, syrinx', - 700: 'paper towel', - 701: 'parachute, chute', - 702: 'parallel bars, bars', - 703: 'park bench', - 704: 'parking meter', - 705: 'passenger car, coach, carriage', - 706: 'patio, terrace', - 707: 'pay-phone, pay-station', - 708: 'pedestal, plinth, footstall', - 709: 'pencil box, pencil case', - 710: 'pencil sharpener', - 711: 'perfume, essence', - 712: 'Petri dish', - 713: 'photocopier', - 714: 'pick, plectrum, plectron', - 715: 'pickelhaube', - 716: 'picket fence, paling', - 717: 'pickup, pickup truck', - 718: 'pier', - 719: 'piggy bank, penny bank', - 720: 'pill bottle', - 721: 'pillow', - 722: 'ping-pong ball', - 723: 'pinwheel', - 724: 'pirate, pirate ship', - 725: 'pitcher, ewer', - 726: "plane, carpenter's plane, woodworking plane", - 727: 'planetarium', - 728: 'plastic bag', - 729: 'plate rack', - 730: 'plow, plough', - 731: "plunger, plumber's helper", - 732: 'Polaroid camera, Polaroid Land camera', - 733: 'pole', - 734: 'police van, police wagon, paddy wagon, patrol wagon, wagon, black Maria', - 735: 'poncho', - 736: 'pool table, billiard table, snooker table', - 737: 'pop bottle, soda bottle', - 738: 'pot, flowerpot', - 739: "potter's wheel", - 740: 'power drill', - 741: 'prayer rug, prayer mat', - 742: 'printer', - 743: 'prison, prison house', - 744: 'projectile, missile', - 745: 'projector', - 746: 'puck, hockey puck', - 747: 'punching bag, punch bag, punching ball, punchball', - 748: 'purse', - 749: 'quill, quill pen', - 750: 'quilt, comforter, comfort, puff', - 751: 'racer, race car, racing car', - 752: 'racket, racquet', - 753: 'radiator', - 754: 'radio, wireless', - 755: 'radio telescope, radio reflector', - 756: 'rain barrel', - 757: 'recreational vehicle, RV, R.V.', - 758: 'reel', - 759: 'reflex camera', - 760: 'refrigerator, icebox', - 761: 'remote control, remote', - 762: 'restaurant, eating house, eating place, eatery', - 763: 'revolver, six-gun, six-shooter', - 764: 'rifle', - 765: 'rocking chair, rocker', - 766: 'rotisserie', - 767: 'rubber eraser, rubber, pencil eraser', - 768: 'rugby ball', - 769: 'rule, ruler', - 770: 'running shoe', - 771: 'safe', - 772: 'safety pin', - 773: 'saltshaker, salt shaker', - 774: 'sandal', - 775: 'sarong', - 776: 'sax, saxophone', - 777: 'scabbard', - 778: 'scale, weighing machine', - 779: 'school bus', - 780: 'schooner', - 781: 'scoreboard', - 782: 'screen, CRT screen', - 783: 'screw', - 784: 'screwdriver', - 785: 'seat belt, seatbelt', - 786: 'sewing machine', - 787: 'shield, buckler', - 788: 'shoe shop, shoe-shop, shoe store', - 789: 'shoji', - 790: 'shopping basket', - 791: 'shopping cart', - 792: 'shovel', - 793: 'shower cap', - 794: 'shower curtain', - 795: 'ski', - 796: 'ski mask', - 797: 'sleeping bag', - 798: 'slide rule, slipstick', - 799: 'sliding door', - 800: 'slot, one-armed bandit', - 801: 'snorkel', - 802: 'snowmobile', - 803: 'snowplow, snowplough', - 804: 'soap dispenser', - 805: 'soccer ball', - 806: 'sock', - 807: 'solar dish, solar collector, solar furnace', - 808: 'sombrero', - 809: 'soup bowl', - 810: 'space bar', - 811: 'space heater', - 812: 'space shuttle', - 813: 'spatula', - 814: 'speedboat', - 815: "spider web, spider's web", - 816: 'spindle', - 817: 'sports car, sport car', - 818: 'spotlight, spot', - 819: 'stage', - 820: 'steam locomotive', - 821: 'steel arch bridge', - 822: 'steel drum', - 823: 'stethoscope', - 824: 'stole', - 825: 'stone wall', - 826: 'stopwatch, stop watch', - 827: 'stove', - 828: 'strainer', - 829: 'streetcar, tram, tramcar, trolley, trolley car', - 830: 'stretcher', - 831: 'studio couch, day bed', - 832: 'stupa, tope', - 833: 'submarine, pigboat, sub, U-boat', - 834: 'suit, suit of clothes', - 835: 'sundial', - 836: 'sunglass', - 837: 'sunglasses, dark glasses, shades', - 838: 'sunscreen, sunblock, sun blocker', - 839: 'suspension bridge', - 840: 'swab, swob, mop', - 841: 'sweatshirt', - 842: 'swimming trunks, bathing trunks', - 843: 'swing', - 844: 'switch, electric switch, electrical switch', - 845: 'syringe', - 846: 'table lamp', - 847: 'tank, army tank, armored combat vehicle, armoured combat vehicle', - 848: 'tape player', - 849: 'teapot', - 850: 'teddy, teddy bear', - 851: 'television, television system', - 852: 'tennis ball', - 853: 'thatch, thatched roof', - 854: 'theater curtain, theatre curtain', - 855: 'thimble', - 856: 'thresher, thrasher, threshing machine', - 857: 'throne', - 858: 'tile roof', - 859: 'toaster', - 860: 'tobacco shop, tobacconist shop, tobacconist', - 861: 'toilet seat', - 862: 'torch', - 863: 'totem pole', - 864: 'tow truck, tow car, wrecker', - 865: 'toyshop', - 866: 'tractor', - 867: 'trailer truck, tractor trailer, trucking rig, rig, articulated lorry, semi', - 868: 'tray', - 869: 'trench coat', - 870: 'tricycle, trike, velocipede', - 871: 'trimaran', - 872: 'tripod', - 873: 'triumphal arch', - 874: 'trolleybus, trolley coach, trackless trolley', - 875: 'trombone', - 876: 'tub, vat', - 877: 'turnstile', - 878: 'typewriter keyboard', - 879: 'umbrella', - 880: 'unicycle, monocycle', - 881: 'upright, upright piano', - 882: 'vacuum, vacuum cleaner', - 883: 'vase', - 884: 'vault', - 885: 'velvet', - 886: 'vending machine', - 887: 'vestment', - 888: 'viaduct', - 889: 'violin, fiddle', - 890: 'volleyball', - 891: 'waffle iron', - 892: 'wall clock', - 893: 'wallet, billfold, notecase, pocketbook', - 894: 'wardrobe, closet, press', - 895: 'warplane, military plane', - 896: 'washbasin, handbasin, washbowl, lavabo, wash-hand basin', - 897: 'washer, automatic washer, washing machine', - 898: 'water bottle', - 899: 'water jug', - 900: 'water tower', - 901: 'whiskey jug', - 902: 'whistle', - 903: 'wig', - 904: 'window screen', - 905: 'window shade', - 906: 'Windsor tie', - 907: 'wine bottle', - 908: 'wing', - 909: 'wok', - 910: 'wooden spoon', - 911: 'wool, woolen, woollen', - 912: 'worm fence, snake fence, snake-rail fence, Virginia fence', - 913: 'wreck', - 914: 'yawl', - 915: 'yurt', - 916: 'web site, website, internet site, site', - 917: 'comic book', - 918: 'crossword puzzle, crossword', - 919: 'street sign', - 920: 'traffic light, traffic signal, stoplight', - 921: 'book jacket, dust cover, dust jacket, dust wrapper', - 922: 'menu', - 923: 'plate', - 924: 'guacamole', - 925: 'consomme', - 926: 'hot pot, hotpot', - 927: 'trifle', - 928: 'ice cream, icecream', - 929: 'ice lolly, lolly, lollipop, popsicle', - 930: 'French loaf', - 931: 'bagel, beigel', - 932: 'pretzel', - 933: 'cheeseburger', - 934: 'hotdog, hot dog, red hot', - 935: 'mashed potato', - 936: 'head cabbage', - 937: 'broccoli', - 938: 'cauliflower', - 939: 'zucchini, courgette', - 940: 'spaghetti squash', - 941: 'acorn squash', - 942: 'butternut squash', - 943: 'cucumber, cuke', - 944: 'artichoke, globe artichoke', - 945: 'bell pepper', - 946: 'cardoon', - 947: 'mushroom', - 948: 'Granny Smith', - 949: 'strawberry', - 950: 'orange', - 951: 'lemon', - 952: 'fig', - 953: 'pineapple, ananas', - 954: 'banana', - 955: 'jackfruit, jak, jack', - 956: 'custard apple', - 957: 'pomegranate', - 958: 'hay', - 959: 'carbonara', - 960: 'chocolate sauce, chocolate syrup', - 961: 'dough', - 962: 'meat loaf, meatloaf', - 963: 'pizza, pizza pie', - 964: 'potpie', - 965: 'burrito', - 966: 'red wine', - 967: 'espresso', - 968: 'cup', - 969: 'eggnog', - 970: 'alp', - 971: 'bubble', - 972: 'cliff, drop, drop-off', - 973: 'coral reef', - 974: 'geyser', - 975: 'lakeside, lakeshore', - 976: 'promontory, headland, head, foreland', - 977: 'sandbar, sand bar', - 978: 'seashore, coast, seacoast, sea-coast', - 979: 'valley, vale', - 980: 'volcano', - 981: 'ballplayer, baseball player', - 982: 'groom, bridegroom', - 983: 'scuba diver', - 984: 'rapeseed', - 985: 'daisy', - 986: "yellow lady's slipper, yellow lady-slipper, Cypripedium calceolus, Cypripedium parviflorum", - 987: 'corn', - 988: 'acorn', - 989: 'hip, rose hip, rosehip', - 990: 'buckeye, horse chestnut, conker', - 991: 'coral fungus', - 992: 'agaric', - 993: 'gyromitra', - 994: 'stinkhorn, carrion fungus', - 995: 'earthstar', - 996: 'hen-of-the-woods, hen of the woods, Polyporus frondosus, Grifola frondosa', - 997: 'bolete', - 998: 'ear, spike, capitulum', - 999: 'toilet tissue, toilet paper, bathroom tissue'} \ No newline at end of file diff --git a/tinygrad/test/models/test_bert.py b/tinygrad/test/models/test_bert.py deleted file mode 100644 index 0e42ff9d..00000000 --- a/tinygrad/test/models/test_bert.py +++ /dev/null @@ -1,56 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad.tensor import Tensor -import torch - -def get_question_samp(bsz, seq_len, vocab_size, seed): - np.random.seed(seed) - in_ids= np.random.randint(vocab_size, size=(bsz, seq_len)) - mask = np.random.choice([True, False], size=(bsz, seq_len)) - seg_ids = np.random.randint(1, size=(bsz, seq_len)) - return in_ids, mask, seg_ids - -def set_equal_weights(mdl, torch_mdl): - from tinygrad.nn.state import get_state_dict - state, torch_state = get_state_dict(mdl), torch_mdl.state_dict() - assert len(state) == len(torch_state) - for k, v in state.items(): - assert k in torch_state - torch_state[k].copy_(torch.from_numpy(v.numpy())) - torch_mdl.eval() - -class TestBert(unittest.TestCase): - def test_questions(self): - from extra.models.bert import BertForQuestionAnswering - from transformers import BertForQuestionAnswering as TorchBertForQuestionAnswering - from transformers import BertConfig - - # small - config = { - 'vocab_size':24, 'hidden_size':2, 'num_hidden_layers':2, 'num_attention_heads':2, - 'intermediate_size':32, 'hidden_dropout_prob':0.1, 'attention_probs_dropout_prob':0.1, - 'max_position_embeddings':512, 'type_vocab_size':2 - } - - # Create in tinygrad - Tensor.manual_seed(1337) - mdl = BertForQuestionAnswering(**config) - - # Create in torch - with torch.no_grad(): - torch_mdl = TorchBertForQuestionAnswering(BertConfig(**config)) - - set_equal_weights(mdl, torch_mdl) - - seeds = (1337, 3141) - bsz, seq_len = 1, 16 - for _, seed in enumerate(seeds): - in_ids, mask, seg_ids = get_question_samp(bsz, seq_len, config['vocab_size'], seed) - out = mdl(Tensor(in_ids), Tensor(mask), Tensor(seg_ids)) - torch_out = torch_mdl.forward(torch.from_numpy(in_ids).long(), torch.from_numpy(mask), torch.from_numpy(seg_ids).long())[:2] - torch_out = torch.cat(torch_out).unsqueeze(2) - np.testing.assert_allclose(out.numpy(), torch_out.detach().numpy(), atol=5e-4, rtol=5e-4) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_efficientnet.py b/tinygrad/test/models/test_efficientnet.py deleted file mode 100644 index 28921965..00000000 --- a/tinygrad/test/models/test_efficientnet.py +++ /dev/null @@ -1,116 +0,0 @@ -import ast -import pathlib -import unittest - -import numpy as np -from PIL import Image - -from tinygrad.helpers import getenv -from tinygrad.tensor import Tensor -from extra.models.efficientnet import EfficientNet -from extra.models.vit import ViT -from extra.models.resnet import ResNet50 - -def _load_labels(): - labels_filename = pathlib.Path(__file__).parent / 'efficientnet/imagenet1000_clsidx_to_labels.txt' - return ast.literal_eval(labels_filename.read_text()) - -_LABELS = _load_labels() - -def preprocess(img, new=False): - # preprocess image - aspect_ratio = img.size[0] / img.size[1] - img = img.resize((int(224*max(aspect_ratio,1.0)), int(224*max(1.0/aspect_ratio,1.0)))) - - img = np.array(img) - y0, x0 =(np.asarray(img.shape)[:2] - 224) // 2 - img = img[y0: y0 + 224, x0: x0 + 224] - - # low level preprocess - if new: - img = img.astype(np.float32) - img -= [127.0, 127.0, 127.0] - img /= [128.0, 128.0, 128.0] - img = img[None] - else: - img = np.moveaxis(img, [2, 0, 1], [0, 1, 2]) - img = img.astype(np.float32)[:3].reshape(1, 3, 224, 224) - img /= 255.0 - img -= np.array([0.485, 0.456, 0.406]).reshape((1, -1, 1, 1)) - img /= np.array([0.229, 0.224, 0.225]).reshape((1, -1, 1, 1)) - return img - - -def _infer(model: EfficientNet, img, bs=1): - old_training = Tensor.training - Tensor.training = False - img = preprocess(img) - # run the net - if bs > 1: img = img.repeat(bs, axis=0) - out = model.forward(Tensor(img)) - Tensor.training = old_training - return _LABELS[np.argmax(out.numpy()[0])] - -chicken_img = Image.open(pathlib.Path(__file__).parent / 'efficientnet/Chicken.jpg') -car_img = Image.open(pathlib.Path(__file__).parent / 'efficientnet/car.jpg') - -class TestEfficientNet(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.model = EfficientNet(number=getenv("NUM")) - cls.model.load_from_pretrained() - - @classmethod - def tearDownClass(cls): - del cls.model - - def test_chicken(self): - label = _infer(self.model, chicken_img) - self.assertEqual(label, "hen") - - def test_chicken_bigbatch(self): - label = _infer(self.model, chicken_img, 2) - self.assertEqual(label, "hen") - - def test_car(self): - label = _infer(self.model, car_img) - self.assertEqual(label, "sports car, sport car") - -class TestViT(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.model = ViT() - cls.model.load_from_pretrained() - - @classmethod - def tearDownClass(cls): - del cls.model - - def test_chicken(self): - label = _infer(self.model, chicken_img) - self.assertEqual(label, "cock") - - def test_car(self): - label = _infer(self.model, car_img) - self.assertEqual(label, "racer, race car, racing car") - -class TestResNet(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.model = ResNet50() - cls.model.load_from_pretrained() - - @classmethod - def tearDownClass(cls): - del cls.model - - def test_chicken(self): - label = _infer(self.model, chicken_img) - self.assertEqual(label, "hen") - - def test_car(self): - label = _infer(self.model, car_img) - self.assertEqual(label, "sports car, sport car") - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_end2end.py b/tinygrad/test/models/test_end2end.py deleted file mode 100644 index 82dc8cc7..00000000 --- a/tinygrad/test/models/test_end2end.py +++ /dev/null @@ -1,164 +0,0 @@ -import torch -from torch import nn -import unittest -import numpy as np -from tinygrad.nn.state import get_parameters, get_state_dict -from tinygrad.nn import optim, Linear, Conv2d, BatchNorm2d -from tinygrad.tensor import Tensor -from extra.datasets import fetch_mnist -from tinygrad.helpers import CI - -def compare_tiny_torch(model, model_torch, X, Y): - with Tensor.train(): - model_torch.train() - model_state_dict = get_state_dict(model) - for k,v in model_torch.named_parameters(): - if not CI: print(f"initting {k} from torch") - model_state_dict[k].assign(Tensor(v.detach().numpy())).realize() - - optimizer = optim.SGD(get_parameters(model), lr=0.001) - optimizer_torch = torch.optim.SGD(model_torch.parameters(), lr=0.001) - - Xt = torch.Tensor(X.numpy()) - np.testing.assert_allclose(X.numpy(), Xt.detach().numpy()) - - out = model(X) - loss = (out * Y).mean() - - out_torch = model_torch(torch.Tensor(X.numpy())) - loss_torch = (out_torch * torch.Tensor(Y.numpy())).mean() - - # zero and backward - optimizer.zero_grad() - loss.backward() - optimizer_torch.zero_grad() - loss_torch.backward() - - # assert losses match - if not CI: print(loss.realize().numpy()) - if not CI: print(loss_torch.detach().numpy()) - np.testing.assert_allclose(loss.realize().numpy(), loss_torch.detach().numpy(), atol=1e-4) - - for k,v in list(model_torch.named_parameters())[::-1]: - g = model_state_dict[k].grad.numpy() - gt = v.grad.detach().numpy() - if not CI: print("testing grads", k, model_state_dict[k].grad.dtype) - np.testing.assert_allclose(g, gt, atol=1e-3, err_msg=f'grad mismatch {k}') - - # take the steps - optimizer.step() - optimizer_torch.step() - - # assert weights match - for k,v in model_torch.named_parameters(): - if not CI: print("testing weight", k, model_state_dict[k].dtype) - np.testing.assert_allclose(model_state_dict[k].numpy(), v.detach().numpy(), atol=1e-3, err_msg=f'weight mismatch {k}') - -def get_mnist_data(): - _X_train, _Y_train, X_test, Y_test = fetch_mnist() - BS = 32 - num_classes = 10 - X = Tensor(X_test[0:BS].astype(np.float32)) - Y = np.zeros((BS, num_classes), np.float32) - Y[range(BS),Y_test[0:BS]] = -1.0*num_classes - return X, Tensor(Y) - -class TestEnd2End(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.X, cls.Y = get_mnist_data() - - def setUp(self): - torch.manual_seed(123) - - def test_linear_mnist(self): - class LinTiny: - def __init__(self, bias=False): - self.l1 = Linear(784, 128, bias=bias) - self.l2 = Linear(128, 10, bias=bias) - def __call__(self, x): - return self.l2(self.l1(x).relu()).log_softmax(-1) - class LinTorch(nn.Module): - def __init__(self, bias=False): - super().__init__() - self.l1 = nn.Linear(784, 128, bias=bias) - self.l2 = nn.Linear(128, 10, bias=bias) - def forward(self, x): - return self.l2(self.l1(x).relu()).log_softmax(-1) - compare_tiny_torch(LinTiny(), LinTorch(), self.X, self.Y) - - def test_bn_mnist(self): - class LinTiny: - def __init__(self): - self.l1 = Linear(784, 128) - self.l2 = Linear(128, 10) - self.bn1 = BatchNorm2d(128) - def __call__(self, x): - return self.l2(self.bn1(self.l1(x).reshape(x.shape[0], -1, 1, 1)).reshape(x.shape[0], -1).relu()).log_softmax(-1) - class LinTorch(nn.Module): - def __init__(self): - super().__init__() - self.l1 = nn.Linear(784, 128) - self.l2 = nn.Linear(128, 10) - self.bn1 = nn.BatchNorm2d(128) - def forward(self, x): - return self.l2(self.bn1(self.l1(x).reshape(x.shape[0], -1, 1, 1)).reshape(x.shape[0], -1).relu()).log_softmax(-1) - compare_tiny_torch(LinTiny(), LinTorch(), self.X, self.Y) - - def test_bn_alone(self): - np.random.seed(1337) - X = Tensor(np.random.randn(32, 10, 1, 1).astype(np.float32)) - Y = Tensor(np.random.randn(32, 10, 1, 1).astype(np.float32)) - compare_tiny_torch(BatchNorm2d(10), nn.BatchNorm2d(10), X, Y) - - def test_bn_linear(self): - BS, K = 2, 1 - eps = 0 - X = Tensor([1,0]).reshape(BS, K, 1, 1) - Y = Tensor([-1,0]).reshape(BS, K, 1, 1) - class LinTiny: - def __init__(self): - self.l1 = Conv2d(K, K, 1, bias=False) - self.bn1 = BatchNorm2d(K, affine=False, track_running_stats=False, eps=eps) - def __call__(self, x): return self.bn1(self.l1(x)) - class LinTorch(nn.Module): - def __init__(self): - super().__init__() - self.l1 = nn.Conv2d(K, K, 1, bias=False) - self.bn1 = nn.BatchNorm2d(K, affine=False, track_running_stats=False, eps=eps) - def forward(self, x): return self.bn1(self.l1(x)) - model_torch = LinTorch() - with torch.no_grad(): - model_torch.l1.weight[:] = 1. - compare_tiny_torch(LinTiny(), model_torch, X, Y) - - def test_conv_mnist(self): - class LinTiny: - def __init__(self, has_batchnorm=False): - self.c1 = Conv2d(1, 8, 3, stride=2) - self.c2 = Conv2d(8, 16, 3, stride=2) - self.l1 = Linear(16*6*6, 10) - if has_batchnorm: - self.bn1, self.bn2 = BatchNorm2d(8), BatchNorm2d(16) - else: - self.bn1, self.bn2 = lambda x: x, lambda x: x - def __call__(self, x): - return self.l1(self.bn2(self.c2(self.bn1(self.c1(x)).relu())).relu().reshape(x.shape[0], -1)).log_softmax(-1) - class LinTorch(nn.Module): - def __init__(self, has_batchnorm=False): - super().__init__() - self.c1 = nn.Conv2d(1, 8, 3, stride=2) - self.c2 = nn.Conv2d(8, 16, 3, stride=2) - self.l1 = nn.Linear(16*6*6, 10) - if has_batchnorm: - self.bn1, self.bn2 = nn.BatchNorm2d(8), nn.BatchNorm2d(16) - else: - self.bn1, self.bn2 = lambda x: x, lambda x: x - def forward(self, x): - return self.l1(self.bn2(self.c2(self.bn1(self.c1(x)).relu())).relu().reshape(x.shape[0], -1)).log_softmax(-1) - for has_batchnorm in [False, True]: - with self.subTest(has_batchnorm=has_batchnorm): - compare_tiny_torch(LinTiny(has_batchnorm), LinTorch(has_batchnorm), self.X.reshape((-1, 1, 28, 28)), self.Y) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/models/test_mnist.py b/tinygrad/test/models/test_mnist.py deleted file mode 100644 index 2f5e9398..00000000 --- a/tinygrad/test/models/test_mnist.py +++ /dev/null @@ -1,115 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad import Tensor, Device -from tinygrad.helpers import CI -from tinygrad.nn.state import get_parameters -from tinygrad.nn import optim, BatchNorm2d -from extra.training import train, evaluate -from extra.datasets import fetch_mnist - -# load the mnist dataset -X_train, Y_train, X_test, Y_test = fetch_mnist() - -# create a model -class TinyBobNet: - def __init__(self): - self.l1 = Tensor.scaled_uniform(784, 128) - self.l2 = Tensor.scaled_uniform(128, 10) - - def parameters(self): - return get_parameters(self) - - def forward(self, x): - return x.dot(self.l1).relu().dot(self.l2) - -# create a model with a conv layer -class TinyConvNet: - def __init__(self, has_batchnorm=False): - # https://keras.io/examples/vision/mnist_convnet/ - conv = 3 - #inter_chan, out_chan = 32, 64 - inter_chan, out_chan = 8, 16 # for speed - self.c1 = Tensor.scaled_uniform(inter_chan,1,conv,conv) - self.c2 = Tensor.scaled_uniform(out_chan,inter_chan,conv,conv) - self.l1 = Tensor.scaled_uniform(out_chan*5*5, 10) - if has_batchnorm: - self.bn1 = BatchNorm2d(inter_chan) - self.bn2 = BatchNorm2d(out_chan) - else: - self.bn1, self.bn2 = lambda x: x, lambda x: x - - def parameters(self): - return get_parameters(self) - - def forward(self, x:Tensor): - x = x.reshape(shape=(-1, 1, 28, 28)) # hacks - x = self.bn1(x.conv2d(self.c1)).relu().max_pool2d() - x = self.bn2(x.conv2d(self.c2)).relu().max_pool2d() - x = x.reshape(shape=[x.shape[0], -1]) - return x.dot(self.l1) - -@unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow") -class TestMNIST(unittest.TestCase): - def test_sgd_onestep(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.SGD(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=1) - for p in model.parameters(): p.realize() - - def test_sgd_threestep(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.SGD(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=3) - - def test_sgd_sixstep(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.SGD(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=6, noloss=True) - - def test_adam_onestep(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.Adam(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=1) - for p in model.parameters(): p.realize() - - def test_adam_threestep(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.Adam(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=3) - - def test_conv_onestep(self): - np.random.seed(1337) - model = TinyConvNet() - optimizer = optim.SGD(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, BS=69, steps=1, noloss=True) - for p in model.parameters(): p.realize() - - def test_conv(self): - np.random.seed(1337) - model = TinyConvNet() - optimizer = optim.Adam(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, steps=100) - assert evaluate(model, X_test, Y_test) > 0.93 # torch gets 0.9415 sometimes - - def test_conv_with_bn(self): - np.random.seed(1337) - model = TinyConvNet(has_batchnorm=True) - optimizer = optim.AdamW(model.parameters(), lr=0.003) - train(model, X_train, Y_train, optimizer, steps=200) - assert evaluate(model, X_test, Y_test) > 0.94 - - def test_sgd(self): - np.random.seed(1337) - model = TinyBobNet() - optimizer = optim.SGD(model.parameters(), lr=0.001) - train(model, X_train, Y_train, optimizer, steps=600) - assert evaluate(model, X_test, Y_test) > 0.94 # CPU gets 0.9494 sometimes - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_onnx.py b/tinygrad/test/models/test_onnx.py deleted file mode 100644 index 7bc9fb35..00000000 --- a/tinygrad/test/models/test_onnx.py +++ /dev/null @@ -1,141 +0,0 @@ -#!/usr/bin/env python -import os -import time -import unittest -import numpy as np -try: - import onnx -except ModuleNotFoundError: - raise unittest.SkipTest("onnx not installed, skipping onnx test") -from tinygrad.frontend.onnx import OnnxRunner, onnx_load -from tinygrad.tensor import Tensor -from tinygrad.helpers import CI, fetch, temp - -def run_onnx_torch(onnx_model, inputs): - import torch - from onnx2torch import convert - torch_model = convert(onnx_model).float() - with torch.no_grad(): - torch_out = torch_model(*[torch.tensor(x) for x in inputs.values()]) - return torch_out - -OPENPILOT_MODEL = "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx" - -np.random.seed(1337) - -class TestOnnxModel(unittest.TestCase): - def test_benchmark_openpilot_model(self): - onnx_model = onnx_load(fetch(OPENPILOT_MODEL)) - run_onnx = OnnxRunner(onnx_model) - def get_inputs(): - np_inputs = { - "input_imgs": np.random.randn(*(1, 12, 128, 256)), - "big_input_imgs": np.random.randn(*(1, 12, 128, 256)), - "desire": np.zeros((1, 100, 8)), - "traffic_convention": np.array([[1., 0.]]), - "nav_features": np.zeros((1, 256)), - "features_buffer": np.zeros((1, 99, 128)), - } - inputs = {k:Tensor(v.astype(np.float32), requires_grad=False) for k,v in np_inputs.items()} - return inputs - - for _ in range(7): - inputs = get_inputs() - st = time.monotonic() - tinygrad_out = run_onnx(inputs)['outputs'] - mt = time.monotonic() - tinygrad_out.realize() - mt2 = time.monotonic() - tinygrad_out = tinygrad_out.numpy() - et = time.monotonic() - if not CI: - print(f"ran openpilot model in {(et-st)*1000.0:.2f} ms, waited {(mt2-mt)*1000.0:.2f} ms for realize, {(et-mt2)*1000.0:.2f} ms for GPU queue") - - if not CI: - import cProfile - import pstats - inputs = get_inputs() - pr = cProfile.Profile(timer=time.perf_counter_ns, timeunit=1e-6) - pr.enable() - tinygrad_out = run_onnx(inputs)['outputs'] - tinygrad_out.realize() - tinygrad_out = tinygrad_out.numpy() - if not CI: - pr.disable() - stats = pstats.Stats(pr) - stats.dump_stats(temp("net.prof")) - os.system(f"flameprof {temp('net.prof')} > {temp('prof.svg')}") - ps = stats.sort_stats(pstats.SortKey.TIME) - ps.print_stats(30) - - def test_openpilot_model(self): - onnx_model = onnx_load(fetch(OPENPILOT_MODEL)) - run_onnx = OnnxRunner(onnx_model) - print("got run_onnx") - inputs = { - "input_imgs": np.random.randn(*(1, 12, 128, 256)), - "big_input_imgs": np.random.randn(*(1, 12, 128, 256)), - "desire": np.zeros((1, 100, 8)), - "traffic_convention": np.array([[1., 0.]]), - "nav_features": np.zeros((1, 256)), - "features_buffer": np.zeros((1, 99, 128)), - } - inputs = {k:v.astype(np.float32) for k,v in inputs.items()} - - st = time.monotonic() - print("****** run onnx ******") - tinygrad_out = run_onnx(inputs)['outputs'] - mt = time.monotonic() - print("****** realize ******") - tinygrad_out.realize() - mt2 = time.monotonic() - tinygrad_out = tinygrad_out.numpy() - et = time.monotonic() - print(f"ran openpilot model in {(et-st)*1000.0:.2f} ms, waited {(mt2-mt)*1000.0:.2f} ms for realize, {(et-mt2)*1000.0:.2f} ms for GPU queue") - - onnx_model = onnx.load(fetch(OPENPILOT_MODEL)) - torch_out = run_onnx_torch(onnx_model, inputs).numpy() - print(tinygrad_out, torch_out) - np.testing.assert_allclose(tinygrad_out, torch_out, atol=1e-4, rtol=1e-2) - - @unittest.skip("slow") - def test_efficientnet(self): - input_name, input_new = "images:0", True - self._test_model( - fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/efficientnet-lite4/model/efficientnet-lite4-11.onnx"), - input_name, input_new) - - def test_shufflenet(self): - input_name, input_new = "gpu_0/data_0", False - self._test_model( - fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/shufflenet/model/shufflenet-9.onnx"), - input_name, input_new) - - @unittest.skip("test is very slow") - def test_resnet(self): - # NOTE: many onnx models can't be run right now due to max pool with strides != kernel_size - input_name, input_new = "data", False - self._test_model( - fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/resnet/model/resnet18-v2-7.onnx"), - input_name, input_new) - - def _test_model(self, fn, input_name, input_new, debug=False): - onnx_model = onnx_load(fn) - print("onnx loaded") - from test.models.test_efficientnet import chicken_img, car_img, preprocess, _LABELS - run_onnx = OnnxRunner(onnx_model) - - def run(img): - inputs = {input_name: preprocess(img, new=input_new)} - tinygrad_out = list(run_onnx(inputs, debug=debug).values())[0].numpy() - return tinygrad_out.argmax() - - cls = run(chicken_img) - print(cls, _LABELS[cls]) - assert _LABELS[cls] == "hen" or _LABELS[cls] == "cock" - cls = run(car_img) - print(cls, _LABELS[cls]) - assert "car" in _LABELS[cls] or _LABELS[cls] == "convertible" - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/models/test_real_world.py b/tinygrad/test/models/test_real_world.py deleted file mode 100644 index e6facd4a..00000000 --- a/tinygrad/test/models/test_real_world.py +++ /dev/null @@ -1,175 +0,0 @@ -import unittest, time, gc -import numpy as np -from tinygrad.device import is_dtype_supported -from tinygrad.nn import optim -from tinygrad.nn.state import get_parameters -from tinygrad.engine.jit import TinyJit -from tinygrad import Tensor, Device, GlobalCounters, dtypes, Variable -from tinygrad.helpers import CI, Context -from extra.lr_scheduler import OneCycleLR -from test.helpers import derandomize_model - -from examples.gpt2 import Transformer as GPT2Transformer, MODEL_PARAMS as GPT2_MODEL_PARAMS -from examples.hlb_cifar10 import SpeedyResNet, hyp -from examples.llama import Transformer as LLaMaTransformer -from examples.stable_diffusion import UNetModel, unet_params -from extra.models.unet import ResBlock -from extra.models.bert import BertForPretraining - -global_mem_used = 0 -def helper_test(nm, gen, model, max_memory_allowed, max_kernels_allowed, all_jitted=False): - with Context(JIT=2): - tms = [] - for _ in range(4): - early_gen = [x.realize() if isinstance(x, Tensor) else x for x in gen()] - GlobalCounters.reset() - Device[Device.DEFAULT].synchronize() - st = time.perf_counter_ns() - model(*early_gen) - Device[Device.DEFAULT].synchronize() - tms.append(time.perf_counter_ns() - st) - mem_used = GlobalCounters.mem_used - global_mem_used - - # TODO: jit should expose this correctly with graph - kernels_used = len(model.jit_cache) if hasattr(model, "jit_cache") else None - print(f"{nm}: used {mem_used/1e9:.2f} GB and {kernels_used} kernels in {min(tms)/1e6:.2f} ms") - assert mem_used/1e9 < max_memory_allowed, f"{nm} used more than {max_memory_allowed:.2f} GB - {mem_used/1e9:.2} GB used" - assert not kernels_used or kernels_used <= max_kernels_allowed, f"{nm} used more than {max_kernels_allowed} kernels, it used {kernels_used}" - if all_jitted: - assert kernels_used > 0 and kernels_used == GlobalCounters.kernel_count or (kernels_used <= GlobalCounters.kernel_count and getattr(Device[Device.DEFAULT], "graph", None)), f"only {kernels_used} out of {GlobalCounters.kernel_count} were jitted" # noqa: E501 - -class TestRealWorld(unittest.TestCase): - def setUp(self): - gc.collect() - global global_mem_used - global_mem_used = GlobalCounters.mem_used - self.old_float = dtypes.default_float - np.random.seed(2002) - - def tearDown(self): - dtypes.default_float = self.old_float - - @unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow, covered by METAL") - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") - def test_stable_diffusion(self): - params = unet_params - params["model_ch"] = 16 - params["ctx_dim"] = 16 - params["num_res_blocks"] = 1 - params["n_heads"] = 2 - model = UNetModel(**params) - derandomize_model(model) - @TinyJit - def test(t, t2): return model(t, Tensor([801]), t2).realize() - helper_test("test_sd", lambda: (Tensor.randn(1, 4, 32, 32),Tensor.randn(1, 77, params["ctx_dim"])), test, 18.0, 515) - - def test_unet_resblock(self): - model = [ResBlock(16, 24, 16) for _ in range(4)] - derandomize_model(model) - @TinyJit - def test(t, t2): - for l in model: t = l(t, t2) - return t.realize() - helper_test("test_unet_resblock", lambda: (Tensor.empty(4, 16, 8, 8), Tensor.empty(1, 24)), test, 0.01, 37) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") - def test_llama(self): - dtypes.default_float = dtypes.float16 - - args_tiny = {"dim": 1024, "hidden_dim": 2048, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 1000} - model = LLaMaTransformer(**args_tiny) - derandomize_model(model) - @TinyJit - def test(t): return model(t, 0).realize() - # TODO: test first token vs rest properly - helper_test("test_llama", lambda: (Tensor([[1,2,3,4]]),), test, 0.27, 168, all_jitted=True) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") - def test_gpt2(self): - dtypes.default_float = dtypes.float16 - - args_tiny = {"dim": 1024, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-5, "vocab_size": 1000} - model = GPT2Transformer(**(args_tiny if CI else GPT2_MODEL_PARAMS["gpt2-medium"])) - derandomize_model(model) - @TinyJit - def test(t, v): - with Context(JIT=0): return model(t, v).realize() - helper_test("test_gpt2", lambda: (Tensor([[1,]]),Variable("pos", 1, 100).bind(1)), test, 0.23 if CI else 0.9, 137 if CI else 396, all_jitted=True) - - @unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow") - def test_train_mnist(self): - from examples.beautiful_mnist import Model - with Tensor.train(): - model = Model() - optimizer = optim.Adam(get_parameters(model)) - BS = 32 - - @TinyJit - def train(X): - out = model(X) - loss = out.mean() - optimizer.zero_grad() - loss.backward() - optimizer.step() - - helper_test("train_mnist", lambda: (Tensor.randn(BS, 1, 28, 28),), train, 0.07, 93) - - @unittest.skipIf(CI and Device.DEFAULT in {"CPU", "GPU", "LLVM"}, "slow") - def test_train_cifar(self): - with Tensor.train(): - model = SpeedyResNet(Tensor.ones((12,3,2,2))) - optimizer = optim.SGD(get_parameters(model), lr=0.01, momentum=0.8, nesterov=True, weight_decay=0.15) - BS = 32 - - @TinyJit - def train(X): - out = model(X) - loss = out.mean() - optimizer.zero_grad() - loss.backward() - optimizer.step() - - helper_test("train_cifar", lambda: (Tensor.randn(BS, 3, 32, 32),), train, (1.0/48)*BS, 126) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") - def test_train_cifar_hyp(self): - dtypes.default_float = dtypes.float16 - with Tensor.train(): - model = SpeedyResNet(Tensor.ones((12,3,2,2))) - optimizer = optim.SGD(get_parameters(model), lr=0.01, momentum=hyp['opt']['momentum'], nesterov=True, weight_decay=hyp['opt']['bias_decay']) - initial_div_factor = hyp['opt']['initial_div_factor'] - final_lr_ratio = hyp['opt']['final_lr_ratio'] - pct_start = hyp['opt']['percent_start'] - lr_scheduler = OneCycleLR(optimizer, max_lr=hyp['opt']['bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, - final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=4) - assert not np.isnan(lr_scheduler.min_lr), "lr too small or initial_div_facotr too big for half" - - def test_bert(self): - with Tensor.train(): - args_tiny = {"attention_probs_dropout_prob": 0.0, "hidden_dropout_prob": 0.0, "vocab_size": 30522, "type_vocab_size": 2, - "max_position_embeddings": 512, "hidden_size": 128, "intermediate_size": 512, "num_attention_heads": 2, "num_hidden_layers": 2} - model = BertForPretraining(**args_tiny) - optimizer = optim.LAMB(get_parameters(model)) - - @TinyJit - def train(input_ids:Tensor, segment_ids:Tensor, attention_mask:Tensor, - masked_positions:Tensor, masked_lm_ids:Tensor, masked_lm_weights:Tensor, next_sentence_labels:Tensor): - lm_logits, seq_relationship_logits = model(input_ids, attention_mask, masked_positions, segment_ids) - loss = model.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) - optimizer.zero_grad() - loss.backward() - optimizer.step() - - from examples.mlperf.helpers import get_fake_data_bert - data = get_fake_data_bert(BS=4) - for v in data.values(): v.to_(Device.DEFAULT) - - helper_test("train_bert", lambda: (data["input_ids"], data["segment_ids"], data["input_mask"], data["masked_lm_positions"], \ - data["masked_lm_ids"], data["masked_lm_weights"], data["next_sentence_labels"]), train, 0.25, 346) - - def test_bert_fuse_arange(self): - with Context(FUSE_ARANGE=1): - self.test_bert() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_resnet.py b/tinygrad/test/models/test_resnet.py deleted file mode 100644 index f71d6890..00000000 --- a/tinygrad/test/models/test_resnet.py +++ /dev/null @@ -1,21 +0,0 @@ -import unittest -from extra.models import resnet - -class TestResnet(unittest.TestCase): - def test_model_load(self): - model = resnet.ResNet18() - model.load_from_pretrained() - - model = resnet.ResNeXt50_32X4D() - model.load_from_pretrained() - - def test_model_load_no_fc_layer(self): - model = resnet.ResNet18(num_classes=None) - model.load_from_pretrained() - - model = resnet.ResNeXt50_32X4D(num_classes=None) - model.load_from_pretrained() - - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/models/test_rnnt.py b/tinygrad/test/models/test_rnnt.py deleted file mode 100644 index f9d5e2c9..00000000 --- a/tinygrad/test/models/test_rnnt.py +++ /dev/null @@ -1,47 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad.tensor import Tensor -from extra.models.rnnt import LSTM -import torch - -class TestRNNT(unittest.TestCase): - def test_lstm(self): - BS, SQ, IS, HS, L = 2, 20, 40, 128, 2 - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.LSTM(IS, HS, L) - - # create in tinygrad - layer = LSTM(IS, HS, L, 0.0) - - # copy weights - with torch.no_grad(): - layer.cells[0].weights_ih.assign(Tensor(torch_layer.weight_ih_l0.numpy())) - layer.cells[0].weights_hh.assign(Tensor(torch_layer.weight_hh_l0.numpy())) - layer.cells[0].bias_ih.assign(Tensor(torch_layer.bias_ih_l0.numpy())) - layer.cells[0].bias_hh.assign(Tensor(torch_layer.bias_hh_l0.numpy())) - layer.cells[1].weights_ih.assign(Tensor(torch_layer.weight_ih_l1.numpy())) - layer.cells[1].weights_hh.assign(Tensor(torch_layer.weight_hh_l1.numpy())) - layer.cells[1].bias_ih.assign(Tensor(torch_layer.bias_ih_l1.numpy())) - layer.cells[1].bias_hh.assign(Tensor(torch_layer.bias_hh_l1.numpy())) - - # test initial hidden - for _ in range(3): - x = Tensor.randn(SQ, BS, IS) - z, hc = layer(x, None) - torch_x = torch.tensor(x.numpy()) - torch_z, torch_hc = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-3, rtol=5e-3) - - # test passing hidden - for _ in range(3): - x = Tensor.randn(SQ, BS, IS) - z, hc = layer(x, hc) - torch_x = torch.tensor(x.numpy()) - torch_z, torch_hc = torch_layer(torch_x, torch_hc) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-3, rtol=5e-3) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_train.py b/tinygrad/test/models/test_train.py deleted file mode 100644 index 605e6f6d..00000000 --- a/tinygrad/test/models/test_train.py +++ /dev/null @@ -1,85 +0,0 @@ -import unittest -import time -import numpy as np -from tinygrad.nn.state import get_parameters -from tinygrad.nn import optim -from tinygrad.tensor import Device -from tinygrad.helpers import getenv, CI -from extra.training import train -from extra.models.convnext import ConvNeXt -from extra.models.efficientnet import EfficientNet -from extra.models.transformer import Transformer -from extra.models.vit import ViT -from extra.models.resnet import ResNet18 - -BS = getenv("BS", 2) - -def train_one_step(model,X,Y): - params = get_parameters(model) - pcount = 0 - for p in params: - pcount += np.prod(p.shape) - optimizer = optim.SGD(params, lr=0.001) - print("stepping %r with %.1fM params bs %d" % (type(model), pcount/1e6, BS)) - st = time.time() - train(model, X, Y, optimizer, steps=1, BS=BS) - et = time.time()-st - print("done in %.2f ms" % (et*1000.)) - -def check_gc(): - if Device.DEFAULT == "GPU": - from extra.introspection import print_objects - assert print_objects() == 0 - -class TestTrain(unittest.TestCase): - def test_convnext(self): - model = ConvNeXt(depths=[1], dims=[16]) - X = np.zeros((BS,3,224,224), dtype=np.float32) - Y = np.zeros((BS), dtype=np.int32) - train_one_step(model,X,Y) - check_gc() - - @unittest.skipIf(CI, "slow") - @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") - def test_efficientnet(self): - model = EfficientNet(0) - X = np.zeros((BS,3,224,224), dtype=np.float32) - Y = np.zeros((BS), dtype=np.int32) - train_one_step(model,X,Y) - check_gc() - - @unittest.skipIf(CI, "slow") - @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") - def test_vit(self): - model = ViT() - X = np.zeros((BS,3,224,224), dtype=np.float32) - Y = np.zeros((BS,), dtype=np.int32) - train_one_step(model,X,Y) - check_gc() - - @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") - def test_transformer(self): - # this should be small GPT-2, but the param count is wrong - # (real ff_dim is 768*4) - model = Transformer(syms=10, maxlen=6, layers=12, embed_dim=768, num_heads=12, ff_dim=768//4) - X = np.zeros((BS,6), dtype=np.float32) - Y = np.zeros((BS,6), dtype=np.int32) - train_one_step(model,X,Y) - check_gc() - - @unittest.skipIf(CI, "slow") - def test_resnet(self): - X = np.zeros((BS, 3, 224, 224), dtype=np.float32) - Y = np.zeros((BS), dtype=np.int32) - for resnet_v in [ResNet18]: - model = resnet_v() - model.load_from_pretrained() - train_one_step(model, X, Y) - check_gc() - - def test_bert(self): - # TODO: write this - pass - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_waifu2x.py b/tinygrad/test/models/test_waifu2x.py deleted file mode 100644 index 957d34fd..00000000 --- a/tinygrad/test/models/test_waifu2x.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python -import pathlib -import unittest -import numpy as np -from tinygrad.tensor import Tensor - -class TestVGG7(unittest.TestCase): - def test_vgg7(self): - from examples.vgg7_helpers.waifu2x import Vgg7, image_load - - # Create in tinygrad - Tensor.manual_seed(1337) - mdl = Vgg7() - mdl.load_from_pretrained() - - # Scale up an image - test_x = image_load(pathlib.Path(__file__).parent / 'waifu2x/input.png') - test_y = image_load(pathlib.Path(__file__).parent / 'waifu2x/output.png') - scaled = mdl.forward_tiled(test_x, 156) - scaled = np.fmax(0, np.fmin(1, scaled)) - np.testing.assert_allclose(scaled, test_y, atol=5e-3, rtol=5e-3) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/test_whisper.py b/tinygrad/test/models/test_whisper.py deleted file mode 100644 index f1696fd4..00000000 --- a/tinygrad/test/models/test_whisper.py +++ /dev/null @@ -1,71 +0,0 @@ -import unittest -import pathlib -from examples.whisper import init_whisper, load_file_waveform, transcribe_file, transcribe_waveform -from tinygrad.helpers import CI, fetch -from tinygrad import Device, dtypes -from tinygrad.device import is_dtype_supported - -# Audio generated with the command on MacOS: -# say "Could you please let me out of the box?" --file-format=WAVE --data-format=LEUI8@16000 -o test -# We use the WAVE type because it's easier to decode in CI test environments -TEST_FILE_1 = str(pathlib.Path(__file__).parent / "whisper/test.wav") -TRANSCRIPTION_1 = "Could you please let me out of the box?" -TEST_FILE_2 = str(pathlib.Path(__file__).parent / "whisper/test2.wav") -TRANSCRIPTION_2 = "a slightly longer audio file so that we can test batch transcriptions of varying length." -# TODO this file will possibly not survive long. find another 1-2 minute sound file online to transcribe -TEST_FILE_3_URL = 'https://homepage.ntu.edu.tw/~karchung/miniconversations/mc45.mp3' -TRANSCRIPTION_3 = "Just lie back and relax. Is the level of pressure about right? Yes, it's fine, and I'd like conditioner please. Sure. I'm going to start the second lathering now. Would you like some Q-tips? How'd you like it cut? I'd like my bangs and the back trimmed, and I'd like the rest thinned out a bit and layered. Where would you like the part? On the left, right about here. Here, have a look. What do you think? It's fine. Here's a thousand anti-dollars. It's 30-ant extra for the rants. Here's your change and receipt. Thank you, and please come again. So how do you like it? It could have been worse, but you'll notice that I didn't ask her for her card. Hmm, yeah. Maybe you can try that place over there next time." # noqa: E501 - -@unittest.skipIf(CI and Device.DEFAULT in ["CPU"], "slow") -@unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") -class TestWhisper(unittest.TestCase): - @classmethod - def setUpClass(cls): - model, enc = init_whisper("tiny.en", batch_size=2) - cls.model = model - cls.enc = enc - - @classmethod - def tearDownClass(cls): - del cls.model - del cls.enc - - def test_transcribe_file1(self): - self.assertEqual(transcribe_file(self.model, self.enc, TEST_FILE_1), TRANSCRIPTION_1) - - @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too many tests for CI") - def test_transcribe_file2(self): - self.assertEqual(transcribe_file(self.model, self.enc, TEST_FILE_2), TRANSCRIPTION_2) - - @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too many tests for CI") - def test_transcribe_batch12(self): - waveforms = [load_file_waveform(TEST_FILE_1), load_file_waveform(TEST_FILE_2)] - transcriptions = transcribe_waveform(self.model, self.enc, waveforms) - self.assertEqual(2, len(transcriptions)) - self.assertEqual(TRANSCRIPTION_1, transcriptions[0]) - self.assertEqual(TRANSCRIPTION_2, transcriptions[1]) - - def test_transcribe_batch21(self): - waveforms = [load_file_waveform(TEST_FILE_2), load_file_waveform(TEST_FILE_1)] - transcriptions = transcribe_waveform(self.model, self.enc, waveforms) - self.assertEqual(2, len(transcriptions)) - self.assertEqual(TRANSCRIPTION_2, transcriptions[0]) - self.assertEqual(TRANSCRIPTION_1, transcriptions[1]) - - @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too long for CI") - def test_transcribe_long(self): - waveform = [load_file_waveform(fetch(TEST_FILE_3_URL))] - transcription = transcribe_waveform(self.model, self.enc, waveform) - self.assertEqual(TRANSCRIPTION_3, transcription) - - @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too long for CI") - def test_transcribe_long_no_batch(self): - waveforms = [load_file_waveform(fetch(TEST_FILE_3_URL)), load_file_waveform(TEST_FILE_1)] - - trancriptions = transcribe_waveform(self.model, self.enc, waveforms) - self.assertEqual(2, len(trancriptions)) - self.assertEqual(TRANSCRIPTION_3, trancriptions[0]) - self.assertEqual(TRANSCRIPTION_1, trancriptions[1]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/models/waifu2x/input.png b/tinygrad/test/models/waifu2x/input.png deleted file mode 100644 index 9ae415a9..00000000 Binary files a/tinygrad/test/models/waifu2x/input.png and /dev/null differ diff --git a/tinygrad/test/models/waifu2x/output.png b/tinygrad/test/models/waifu2x/output.png deleted file mode 100644 index b105a2e2..00000000 Binary files a/tinygrad/test/models/waifu2x/output.png and /dev/null differ diff --git a/tinygrad/test/models/whisper/test.wav b/tinygrad/test/models/whisper/test.wav deleted file mode 100644 index eb938981..00000000 Binary files a/tinygrad/test/models/whisper/test.wav and /dev/null differ diff --git a/tinygrad/test/models/whisper/test2.wav b/tinygrad/test/models/whisper/test2.wav deleted file mode 100644 index e76b04fc..00000000 Binary files a/tinygrad/test/models/whisper/test2.wav and /dev/null differ diff --git a/tinygrad/test/test_amd_llvm.py b/tinygrad/test/test_amd_llvm.py deleted file mode 100644 index 9fb9fa33..00000000 --- a/tinygrad/test/test_amd_llvm.py +++ /dev/null @@ -1,52 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Device -from tinygrad.device import CompileError -from tinygrad.helpers import flat_mv -if Device.DEFAULT=="AMD": - from tinygrad.runtime.ops_amd import AMDAllocator, AMDDevice, AMDProgram - from tinygrad.runtime.support.compiler_amd import AMDLLVMCompiler - -@unittest.skipUnless(Device.DEFAULT == "AMD", "Runs only on AMD") -class TestAMDLLVM(unittest.TestCase): - def test_compiler(self): - src = ''' -; https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AMDGPU/imm.ll -define amdgpu_kernel void @i64_imm_inline_lo(ptr addrspace(1) %out) { -entry: - store i64 1311768464867721221, ptr addrspace(1) %out ; 0x1234567800000005 - ret void -} - ''' - device = AMDDevice() - compiler = AMDLLVMCompiler("gfx1100") - obj = compiler.compile(src) - allocator = AMDAllocator(device) - a = allocator.alloc(1*8) - prog = AMDProgram(device, "test", obj) - prog(a, wait=True) - na = np.empty(1, np.uint64) - allocator._copyout(flat_mv(na.data), a) - assert na == [0x1234567800000005] - - def test_compiler_diag_error(self): - src = """ -@local_temp0 = internal unnamed_addr addrspace(3) global [{N} x float*] undef, align 16 -define amdgpu_kernel void @test(float* noalias align 32 %data0, half* noalias align 32 %data1, float* noalias align 32 %data2) #0 -{{ - %local_temp0 = addrspacecast [{N} x float*] addrspace(3)* @local_temp0 to [{N} x float*]* - %v178 = getelementptr inbounds float, float* %local_temp0, i32 1 - %v133 = getelementptr inbounds float, float* %data2, i32 1 - %v134 = load float, float* %v133 - store float %v134, float* %v178 - ret void -}} -""" - compiler = AMDLLVMCompiler("gfx1100") - compiler.compile(src.format(N=65536//8)) - with self.assertRaises(CompileError): - # llvm diagnostic: :0:0: local memory (65544) exceeds limit (65536) in function 'test' - compiler.compile(src.format(N=65536//8+1)) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_arange.py b/tinygrad/test/test_arange.py deleted file mode 100644 index e9bc9983..00000000 --- a/tinygrad/test/test_arange.py +++ /dev/null @@ -1,221 +0,0 @@ -import unittest, contextlib -import numpy as np -from tinygrad import Tensor, GlobalCounters, dtypes, nn, Device, Variable -from tinygrad.helpers import CI, Context, getenv -from tinygrad.engine.realize import run_schedule -from tinygrad.codegen.kernel import Opt, OptOps, Kernel, KernelOptError -from tinygrad.engine.realize import CompiledRunner, ExecItem -from tinygrad.engine.search import get_kernel_actions -from tinygrad.uop.ops import Ops - -class TestArange(unittest.TestCase): - def _get_flops(self, N, opts=None): - GlobalCounters.reset() - tt = Tensor.arange(N) - sched = tt.schedule() - self.assertEqual(len(sched), 1) - k = Kernel(sched[-1].ast) - if opts is not None: - for o in opts: k.apply_opt(o) - p = k.to_program() - print(p.name) - #print(p.src) - ExecItem(CompiledRunner(p), [tt.uop.buffer]).run() - np.testing.assert_equal(tt.numpy(), np.arange(N)) - return p.estimates.ops - - def test_complexity(self, opts=None, limit=None): - f1 = self._get_flops(256, opts) - f2 = self._get_flops(2560, opts) - print(f"{f1=}, {f2=}") - # add 1 to avoid divide by 0. arange is 0 flops now! - assert (f1 < 6000 and f2 < 6000) or ((f2+1) / (f1+1) < 16), f"bad complexity, flops {(f2+1) / (f1+1):.1f}X while inputs 10X" - if limit is not None and not getenv("PTX"): - # PTX counts index ALU in flops - assert f1 <= limit, f"{f1=}, {limit=}" - - def test_complexity_w_upcast(self): return self.test_complexity([Opt(OptOps.UPCAST, 0, 4)], limit=0) - def test_complexity_w_unroll2(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 2)], limit=0) - def test_complexity_w_unroll4(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 4)], limit=0) - def test_complexity_w_unroll8(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 8)], limit=0) - def test_complexity_w_upcast_and_unroll(self): return self.test_complexity([Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], limit=0) - - if Device.default.renderer.has_local: - # TODO: fix limit - def test_complexity_w_group(self): return self.test_complexity([Opt(OptOps.GROUP, 0, 16)], limit=81920) - def test_complexity_w_group_top(self): return self.test_complexity([Opt(OptOps.GROUPTOP, 0, 16)], limit=106496) - - def test_complexity_w_local(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16)], limit=0) - @unittest.skip("doesn't work yet. TODO: this absolutely should work") - def test_complexity_w_local_unroll4(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.UNROLL, 0, 4)], limit=0) - @unittest.skip("doesn't work yet") - def test_complexity_w_local_and_padto(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.PADTO, axis=1, arg=32)]) - - def test_all_opts(self, opts=None, exclude=None): - k = Kernel(Tensor.arange(256).schedule()[-1].ast) - if opts is not None: - for o in opts: k.apply_opt(o) - all_opts_256 = [kk.applied_opts for kk in get_kernel_actions(k, include_0=False).values()] - k = Kernel(Tensor.arange(2560).schedule()[-1].ast) - if opts is not None: - for o in opts: k.apply_opt(o) - all_opts_2560 = [kk.applied_opts for kk in get_kernel_actions(k, include_0=False).values()] - all_opts = [x for x in all_opts_256 if x in all_opts_2560] - for opts in all_opts: - if exclude is not None and opts[-1] in exclude: continue - print(opts) - self.test_complexity(opts) - def test_all_opts_w_local(self): - with contextlib.suppress(KernelOptError): - return self.test_all_opts([Opt(OptOps.LOCAL, 0, 16)], [Opt(op=OptOps.PADTO, axis=1, arg=32)]) - def test_all_opts_w_upcast(self): return self.test_all_opts([Opt(OptOps.UPCAST, 0, 4)]) - def test_all_opts_w_unroll(self): return self.test_all_opts([Opt(OptOps.UNROLL, 0, 4)], [Opt(op=OptOps.GROUP, axis=0, arg=0)]) - def test_all_opts_w_upcast_and_unroll(self): - return self.test_all_opts([Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], [Opt(op=OptOps.GROUP, axis=0, arg=0)]) - -class TestRand(unittest.TestCase): - def test_fused_rand_less_ops(self, noopt=1): - GlobalCounters.reset() - with Context(FUSE_ARANGE=0, NOOPT=noopt): - out = Tensor.rand(16384) - out.realize() - unfused_ops = GlobalCounters.global_ops - - GlobalCounters.reset() - with Context(FUSE_ARANGE=1, NOOPT=noopt): - out = Tensor.rand(16384) - out.realize() - print(f"fused {GlobalCounters.global_ops} unfused {unfused_ops}") - self.assertLessEqual(GlobalCounters.global_ops, unfused_ops*2) - def test_fused_rand_less_ops_opt(self): self.test_fused_rand_less_ops(0) - -DSET, DDIM = 2048, 32 - -class TestIndexing(unittest.TestCase): - def test_arange_2_reduce(self): - needle = Tensor.zeros(16384, dtype=dtypes.int).contiguous() - needle[1337] = 1 - needle.realize() - with Context(NOOPT=1, FUSE_ARANGE=1): - GlobalCounters.reset() - out = ((Tensor.arange(1,16385)-1)*needle).sum() - sched = out.schedule() - self.assertEqual(len(sched), 1) - run_schedule(sched) - self.assertEqual(out.item(), 1337) - - @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") - def test_manual_index(self): - dataset = Tensor.rand(DSET, DDIM).realize() - idxs = Tensor([0,3,5,6]).realize() - real_index = dataset.numpy()[idxs.numpy()] - print("*** indexing ***") - with Context(NOOPT=1, FUSE_ARANGE=1): - GlobalCounters.reset() - rng = Tensor.ones(4, DDIM, DSET, dtype=dtypes.int)._cumalu(axis=-1, op=Ops.ADD, _include_initial=True).reshape(4, DDIM, DSET, 1) - idxs = idxs.reshape(4,1,1,1).expand(4, DDIM, DSET, 1) - reshape_dataset = dataset.T.reshape(1, DDIM, DSET, 1).expand(4, DDIM, DSET, 1) - full = (rng==idxs).where(reshape_dataset, Tensor.zeros(4, DDIM, DSET, 1)) - X = full.sum(axis=(2,3)) - sched = X.schedule() - self.assertEqual(len(sched), 1) - run_schedule(sched) - assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}" - np.testing.assert_allclose(real_index, X.numpy()) - - def test_index_variable(self): - dataset = Tensor.rand(DSET, DDIM).realize() - v = Variable("v", 0, DDIM-1) - with Context(NOOPT=1, FUSE_ARANGE=1, SPLIT_REDUCEOP=0): - GlobalCounters.reset() - vb = Tensor(v.bind(12)) - comp = dataset[vb].numpy() - # no global ops because they are all indexing - self.assertEqual(GlobalCounters.global_ops, 0) - np.testing.assert_allclose(comp, dataset.numpy()[12]) - - def test_index(self): - dataset = Tensor.rand(DSET, DDIM).realize() - idxs = Tensor([0,3,5,6]).realize() - real_index = dataset.numpy()[idxs.numpy()] - print("*** indexing ***") - with Context(NOOPT=1): - GlobalCounters.reset() - X = dataset[idxs] - assert X.shape == (4,DDIM) - sched = X.schedule() - # TODO: enable these asserts when the scheduler can handle this - #self.assertEqual(len(sched), 1) - run_schedule(sched) - #assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}" - np.testing.assert_allclose(real_index, X.numpy()) - - def test_index_fused(self, noopt=1): - dataset = Tensor.rand(DSET, DDIM).realize() - idxs = Tensor([0,3,5,6]).realize() - real_index = dataset.numpy()[idxs.numpy()] - print("*** indexing ***") - with Context(NOOPT=noopt, FUSE_ARANGE=1): - GlobalCounters.reset() - X = dataset[idxs] - assert X.shape == (4,DDIM) - sched = X.schedule() - self.assertEqual(len(sched), 2) - run_schedule(sched) - assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops} != {4*DSET}" - np.testing.assert_allclose(real_index, X.numpy()) - @unittest.skip("not ready") - def test_index_fused_opt(self): self.test_index_fused(0) - - def test_index_fused_out_of_bounds(self): - dataset = Tensor.rand(256, 256).realize() - idxs = Tensor([-19238, -257, 256, 495, 10982377]).realize() - with Context(NOOPT=1, FUSE_ARANGE=1): - X = dataset[idxs] - np.testing.assert_equal(X.numpy(), 0) - - @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") - def test_index_mnist(self, noopt=1, op_limit=512*784*13, split_reduceop=0): - # WEBGPU generates more ops due to bitpacking of < 4-byte dtypes - if Device.DEFAULT == "WEBGPU": op_limit *= 15 - from tinygrad.nn.datasets import mnist - X_train, Y_train, _, _ = mnist() - with Context(NOOPT=noopt, FUSE_ARANGE=1, SPLIT_REDUCEOP=split_reduceop): - samples = Tensor.randint(getenv("BS", 512), high=X_train.shape[0]).realize() - GlobalCounters.reset() - x = X_train[samples].numpy() - y = Y_train[samples].numpy() - assert GlobalCounters.global_ops < op_limit, f"too many ops {GlobalCounters.global_ops} != {op_limit}" - np.testing.assert_allclose(X_train.numpy()[samples.numpy()], x) - np.testing.assert_allclose(Y_train.numpy()[samples.numpy()], y) - - def test_index_mnist_opt(self): self.test_index_mnist(0) - def test_index_mnist_split(self): self.test_index_mnist(1, split_reduceop=1) - def test_index_mnist_opt_split(self): self.test_index_mnist(0, split_reduceop=1) - - @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") - def test_llama_embedding(self, noopt=1, op_limit=65536): - # llama3 is 128256 - vocab_size, embed_size = (10, 3) if CI else (32000, 4096) - emb = nn.Embedding(vocab_size, embed_size) - # TODO: why is a new realize needed here - emb_w = emb.weight.realize().numpy() - x = Tensor([1,2,3,4]) - with Context(NOOPT=noopt, FUSE_ARANGE=1): - GlobalCounters.reset() - z = emb(x).realize() - self.assertLessEqual(GlobalCounters.global_ops, op_limit) - self.assertEqual(GlobalCounters.kernel_count, 2) - if getenv("CHECK", 1): - import torch - with torch.no_grad(): - torch_emb = torch.nn.Embedding(vocab_size, embed_size).eval() - torch_emb.weight[:] = torch.tensor(emb_w, dtype=torch.float32) - torch_z = torch_emb(torch.tensor(x.numpy())) - # TODO: reshape to match torch, should we do this in nn? - np.testing.assert_allclose(z.numpy().reshape(4, embed_size), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) - # at least the arange is being fused - def test_llama_embedding_opt(self): self.test_llama_embedding(0, 1_736_704_000 if CI else 5_898_240_000) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_assign.py b/tinygrad/test/test_assign.py deleted file mode 100644 index 837e4141..00000000 --- a/tinygrad/test/test_assign.py +++ /dev/null @@ -1,398 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad import dtypes, Tensor, TinyJit, GlobalCounters, Variable -from tinygrad.device import is_dtype_supported -from tinygrad.helpers import temp - -N = 200 # has to be bigger than the cache to fail - -class TestAssign(unittest.TestCase): - def test_simple_assignment(self): - a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - a.realize() - b.realize() - ba1 = a.uop.base.realized - bb1 = b.uop.base.realized - a += b - a.realize() - ba2 = a.uop.base.realized - assert ba1 == ba2 and ba1 != bb1 - np.testing.assert_allclose(a.numpy(), (np.arange(N*N)*2).reshape((N,N))) - - def test_assign_zeros_good(self): - a = Tensor.zeros(10,10).contiguous() - a.assign(Tensor.ones(10,10)) - b = Tensor.zeros(10,10).contiguous() - a.realize() - np.testing.assert_allclose(b.numpy(), 0) - - def test_assign_zeros(self): - a = Tensor.zeros(10,10).contiguous() - b = Tensor.zeros(10,10).contiguous() - a.assign(Tensor.ones(10,10)) - a.realize() - np.testing.assert_allclose(b.numpy(), 0) - - def test_assign_add(self): - def f(x): - x += 1 - x.realize() - x = Tensor([0]) - f(x) - assert x.item() == 1 - - def test_assign_add_twice(self): - # NOTE: this has two kernels - def f(x): - x += 1 - x += 1 - x.realize() - x = Tensor([0]) - f(x) - assert x.item() == 2 - - def test_assign_add_double(self): - def f(x): - x += 1 - x.realize() - x = Tensor([0]) - f(x) - out = x.item() - assert out == 1, f"expected 1, got {out}" - x = Tensor([0]) - f(x) - out = x.item() - assert out == 1, f"expected 1, got {out}" - - def test_assign_add_jit(self): - @TinyJit - def f(x): - x += 1 - x.realize() - x = Tensor([0]) - for _ in range(5): f(x) - assert x.item() == 5 - - def test_assign_add_jit_other(self): - @TinyJit - def f(x): - x += 1 - x.realize() - x = Tensor([0]) - for _ in range(5): f(x) - assert x.item() == 5 - - y = Tensor([0]) - for _ in range(4): f(y) - assert y.item() == 4 - - def test_assign_other_jit(self): - @TinyJit - def f(x, a): - x.assign(a) - x.realize() - x = Tensor([0]) - for i in range(1, 6): - f(x, x.full_like(i).contiguous()) # const would be implicitly folded without contiguous - assert x.item() == i - - def test_assign_add_other_jit(self): - @TinyJit - def f(x, a): - x += a - x.realize() - x = Tensor([0]) - a = 0 - for i in range(1, 6): - a += i - f(x, x.full_like(i).contiguous()) - assert x.item() == a - - def test_assign_changes(self): - a = Tensor.ones(4).contiguous().realize() - old_a = a - a.assign(Tensor.full((4,), 2.).contiguous()) - # NOTE: old_a is now 2, and this would match the behavior of pytorch - new = a + old_a - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_cycle(self): - # NOTE: should *not* raise AssertionError from numpy - with self.assertRaisesRegex(RuntimeError, "cycle"): - a = Tensor.ones(4).contiguous().realize() - times_a = a*3 - a.assign(Tensor.full((4,), 2.).contiguous()) - new = a + (times_a-1) - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_contiguous_cycle(self): - with self.assertRaisesRegex(RuntimeError, "cycle"): - a = Tensor.ones(4).contiguous().realize() - times_a = a*3 - a.assign(Tensor.full((4,), 2.)) - new = a.contiguous() + times_a-1 - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_possible(self): - a = Tensor.ones(4).contiguous().realize() - times_a = a*3 - a.assign(Tensor.full((4,), 2.)) - new = a + (times_a-1).contiguous() - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_possible_contiguous(self): - a = Tensor.ones(4).contiguous().realize() - times_a = a*3 - a.assign(Tensor.full((4,), 2.).contiguous()) - new = a + (times_a-1).contiguous() - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_both_contiguous(self): - a = Tensor.ones(4).contiguous().realize() - times_a = a*3 - a.assign(Tensor.full((4,), 2.)) - new = a.contiguous() + (times_a-1).contiguous() - np.testing.assert_allclose(new.numpy(), 4) - - def test_assign_diamond_alt(self): - a = Tensor.ones(4).contiguous().realize() - a.assign(Tensor.full((4,), 2.).contiguous()) - times_a = a*3 - new = a + times_a - np.testing.assert_allclose(new.numpy(), 8) - - def test_double_assign(self): - a = Tensor.ones(4).contiguous().realize() - a += 1 - a += 1 - np.testing.assert_allclose(a.numpy(), 3) - - def test_crossover_assign(self): - a = Tensor.full((4,), 2).contiguous().realize() - b = Tensor.full((4,), 3).contiguous().realize() - a += b - b += a - Tensor.realize(a,b) - np.testing.assert_allclose(a.numpy(), 5) - np.testing.assert_allclose(b.numpy(), 8) - - def test_assign_double_diamond(self): - a = Tensor.full((4,), 2).contiguous().realize() - b = Tensor.full((4,), 3).contiguous().realize() - a_prev = a*4 - b_prev = b+3 - b += a_prev.contiguous() - a += b_prev.contiguous() - Tensor.realize(a, b) - np.testing.assert_equal(b.numpy(), 11) - np.testing.assert_equal(a.numpy(), 8) - - def test_assign_double_diamond_reduce(self): - a0 = Tensor.full((16, 16), 10).contiguous().realize() - a1 = Tensor.full((16, 16), 20).contiguous().realize() - b0 = Tensor.full((16, ), 1).contiguous().realize() - b1 = Tensor.full((16, ), 2).contiguous().realize() - - r0 = (a0 - b1.contiguous()).sum(1) - r1 = (a1 - b0.contiguous()).sum(1) - b0.assign(r0 * b0) - b1.assign(r1 * b1) - Tensor.realize(b0, b1) - np.testing.assert_equal(b0.numpy(), 128) - np.testing.assert_equal(b1.numpy(), 608) - - @unittest.skip("TODO: bring this assert back") - def test_crossunder_assign(self): - # NOTE: should *not* raise AssertionError from numpy - with self.assertRaisesRegex(RuntimeError, "cycle"): - a = Tensor.full((4,), 2).contiguous().realize() - b = Tensor.full((4,), 3).contiguous().realize() - c = a+9 - a += b - b += c - Tensor.realize(a,b) - np.testing.assert_allclose(a.numpy(), 2+3) - np.testing.assert_allclose(b.numpy(), 3+2+9) - - def test_assign_kv_cache(self): - bsz, max_context = 2, 8 - - class Attn: - @TinyJit - def __call__(self, xk:Tensor, start_pos:Variable): - seqlen = xk.shape[1] - if not hasattr(self, "cache_k"): - self.cache_k = Tensor.zeros(bsz, max_context, 1, 1).contiguous() - keys = self.cache_k.shrink((None, (0, start_pos), None, None)).cat(xk, dim=1).contiguous() if start_pos > 0 else xk - self.cache_k.assign(keys.pad((None,(0,max_context-start_pos-seqlen),None,None)).contiguous()).realize() - - attn = Attn() - xk = Tensor.ones(bsz, 3, 1, 1).contiguous() - attn(xk, 0) - for i in range(3,6): - # copied from LLaMA - start_pos = Variable("start_pos", 1, max_context).bind(i) - xk = Tensor.ones(bsz, 1, 1, 1).contiguous() - attn(xk, start_pos) - - out = attn.cache_k.flatten().numpy() - np.testing.assert_allclose(out, [1.,1.,1.,1.,1.,1.,0.,0.,1.,1.,1.,1.,1.,1.,0.,0.]) - - def test_assign_contiguous(self): - b = Tensor.rand(4,4).realize() - a = (Tensor.rand(4,4).realize() + 1) - kc = GlobalCounters.kernel_count - b.assign(a.contiguous()).realize() - assert GlobalCounters.kernel_count - kc == 2 - - def test_assign_contiguous_permute(self): - b = Tensor.rand(4,4).realize() - a = (Tensor.rand(4,4).realize() + 1).permute((1,0)) - kc = GlobalCounters.kernel_count - b.assign(a.contiguous()).realize() - assert GlobalCounters.kernel_count - kc == 2 - - def test_permuted_assignment(self): - a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - a.realize() - b.realize() - ba1 = a.uop.base.realized - bb1 = b.uop.base.realized - with self.assertRaises((RuntimeError, AssertionError)): - a = a.permute(1,0) - a += b - a.realize() - ba2 = a.uop.base.realized - assert ba1 != ba2 and ba1 != bb1 - np.testing.assert_allclose(a.numpy(), np.arange(N*N).reshape((N,N)) + np.arange(N*N).reshape((N,N)).transpose(1,0)) - - def test_post_permuted_assignment(self): - a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - a.realize() - b.realize() - #GlobalCounters.cache = [] - ba1 = a.uop.base.realized # noqa: F841 - bb1 = b.uop.base.realized # noqa: F841 - with self.assertRaisesRegex(RuntimeError, "contiguous"): - a.assign(a.permute(1,0) + b) # this should not work! - a.realize() - ba2 = a.uop.base.realized # noqa: F841 - # NOTE: don't test that it's assigned - #assert ba1 == ba2 and ba1 != bb1 - np.testing.assert_allclose(a.numpy(), np.arange(N*N).reshape((N,N)) + np.arange(N*N).reshape((N,N)).transpose(1,0)) - - @unittest.skip("multi output not supported anymore") - def test_simple_assignment_multioutput(self): - a = Tensor.randn(32, 32).realize() - b = Tensor.full((32, ), 1.).contiguous().realize() - c = Tensor.full((32, ), 2.).contiguous().realize() - d = Tensor.full((32, ), 3.).contiguous().realize() - - r = a.sum(axis=1) - b.assign(r + b) - c.assign(r + c) - d.assign(r + d) - - kc = GlobalCounters.kernel_count - Tensor.realize(b, c, d) - assert GlobalCounters.kernel_count - kc == 1 - np.testing.assert_allclose(b.numpy(), a.sum(1).numpy()+1) - np.testing.assert_allclose(c.numpy(), a.sum(1).numpy()+2) - np.testing.assert_allclose(d.numpy(), a.sum(1).numpy()+3) - - # NOTE: if the assign target is read/write in a single kernel, it should be contiguous - - def test_permuted_assignment_correct(self): - a = Tensor.arange(4 * 4).reshape(4, 4).contiguous().realize() - b = Tensor.arange(4 * 4).reshape(4, 4).contiguous().realize() - # TODO: scheduler limitation, should NOT raise AssertionError from numpy. - with self.assertRaisesRegex(RuntimeError, "contiguous"): - a = a.permute(1, 0) - new_val = a + b - a.assign(new_val) - np.testing.assert_equal(a.numpy(), np.arange(4 * 4).reshape(4, 4).transpose(1, 0) + np.arange(4 * 4).reshape(4, 4)) - - def test_permuted_reduceop_child_dual_use(self): - a = Tensor.randn(32, 32, 32).realize() - b = Tensor.full((32, 32), 1.).contiguous().realize() - with self.assertRaisesRegex(RuntimeError, "contiguous"): - r = a.sum(axis=1) - b.assign(r + b.permute(1, 0)) - b.realize() - - @unittest.skip("multi output not supported anymore") - def test_permuted_reduceop_multioutput_dual_use(self): - a = Tensor.randn(32, 32, 32).realize() - b = Tensor.full((32, 32), 1.).contiguous().realize() - c = Tensor.full((32, 32), 2.).contiguous().realize() - - with self.assertRaisesRegex(RuntimeError, "contiguous"): - r = a.sum(axis=1) - b_perm = b.permute(1, 0) - b.assign(r + b) - c.assign(r + b_perm) - Tensor.realize(b, c) - - @unittest.skip("multi output not supported anymore") - def test_permuted_reduceop_multioutput_dual_use_possible(self): - a = Tensor.randn(32, 32, 32, dtype=dtypes.int).realize() - b = Tensor.arange(32 * 32).reshape(32, 32).realize() - c = Tensor.arange(32 * 32).reshape(32, 32).realize() - - kc = GlobalCounters.kernel_count - r = a.sum(axis=1) - b_perm = b.permute(1, 0) - b.assign(r + b) - c.assign(r + b_perm.contiguous()) - Tensor.realize(b, c) - assert GlobalCounters.kernel_count - kc == 2 - np.testing.assert_equal(b.numpy(), a.numpy().sum(1) + np.arange(32 * 32).reshape(32, 32)) - np.testing.assert_equal(c.numpy(), a.numpy().sum(1) + np.arange(32 * 32).reshape(32, 32).transpose(1, 0)) - - def test_permuted_assignment_masked_view_possible(self): - a = Tensor.ones(4, 4).contiguous().realize() - b = a.shrink((None, (0, 2))).pad((None, (0, 2)), value=2) - a.assign(a + b) - kc = GlobalCounters.kernel_count - a.realize() - assert GlobalCounters.kernel_count - kc == 1 - np.testing.assert_equal(a.numpy(), np.ones((4, 4))+np.pad(np.ones((4, 4))[:, 0:2], ((0, 0), (0, 2)), constant_values=2)) - - def test_permuted_assignment_masked_view_not_contiguous(self): - a = Tensor.ones(4, 4).contiguous().realize() - with self.assertRaisesRegex(RuntimeError, "contiguous"): - b = a.shrink((None, (0, 2))).pad((None, (0, 2)), value=2).permute(1, 0) - a.assign(a + b) - a.realize() - - # TODO: is there a way to sneak in a permute such that it returns the wrong answer? - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_setitem_half(self): - a = Tensor.full((8,), 1.0, dtype=dtypes.half).contiguous().realize() - b = Tensor.full((4,), 2.0, dtype=dtypes.half).contiguous().realize() - assign = a[:4].assign(b) - assign.realize() - np.testing.assert_allclose(a.numpy(), [2., 2., 2., 2., 1., 1., 1., 1.]) - - @unittest.skip("don't use output buffer, and mismatch dtype no longer supported") - def test_cast_assignment(self): - a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) - a.realize() - oba1 = a.uop.base.output_buffer - a.assign(a.cast(dtypes.int32).realize()) - a.realize() - oba2 = a.uop.base.output_buffer - assert oba1 is None and oba2 is None - np.testing.assert_allclose(a.numpy(), np.arange(N*N,dtype=np.int32).reshape((N,N))) - - def test_disk_assignment(self): - a = Tensor.empty(5, device=f"disk:{temp('disk_assignment')}").assign(Tensor.ones(5)).numpy() - np.testing.assert_equal(a, np.ones(5)) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_compile_failures.py b/tinygrad/test/test_compile_failures.py deleted file mode 100644 index 5ab87c0b..00000000 --- a/tinygrad/test/test_compile_failures.py +++ /dev/null @@ -1,18 +0,0 @@ -import unittest -from tinygrad import Tensor, dtypes, Device -from tinygrad.engine.realize import lower_schedule -from tinygrad.device import is_dtype_supported - -class TestCompileFailures(unittest.TestCase): - def compile(self, out:Tensor): - for _ in lower_schedule(out.schedule()): pass - - @unittest.skipUnless(is_dtype_supported(dtypes.uchar, Device.DEFAULT), f"no uint8 on {Device.DEFAULT}") - def test_interpolate_atari(self): - self.compile(Tensor.empty(210, 160, dtype='uint8').interpolate((64, 64))) - - def test_add_max_uchar(self): - self.compile((Tensor.empty(1024, dtype='uint8') + Tensor.empty(1024, dtype='uint8')).max()) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_const_folding.py b/tinygrad/test/test_const_folding.py deleted file mode 100644 index 187a4b51..00000000 --- a/tinygrad/test/test_const_folding.py +++ /dev/null @@ -1,341 +0,0 @@ -import unittest, itertools, math -from typing import Any -from tinygrad import Tensor, Device, dtypes -from tinygrad.dtype import DType -from tinygrad.uop.ops import Ops, UOp -from tinygrad.codegen import full_rewrite_to_sink -import numpy as np -from tinygrad.device import is_dtype_supported -from test.helpers import not_support_multi_device - -def _check_ast_count(desired_count:int, t:Tensor): - # NOTE: this has side effect because everything can be scheduled only once - schedule = t.schedule() - asts = [s for s in schedule if s.ast.op is Ops.SINK] - assert len(asts) == desired_count, f"{len(asts)} != {desired_count}" - -class TestUnaryOpsConstFolding(unittest.TestCase): - def test_all_consts_ops(self): - _check_ast_count(0, Tensor.ones(4).exp()) - _check_ast_count(0, Tensor.ones(4).sqrt()) - _check_ast_count(0, Tensor.ones(4) + Tensor.ones(4)) - _check_ast_count(0, Tensor.ones(4) / Tensor.ones(4)) - - def test_cast(self): - _check_ast_count(0, Tensor.ones(4).cast(dtypes.int16)) - _check_ast_count(0, Tensor.full(4, fill_value=-1).cast(dtypes.uint16)) - - @unittest.expectedFailure # no two level fold at lazybuffer - def test_neg_folding(self): - _check_ast_count(0, Tensor([1, 2, 3]).mul(-1).neg()) - _check_ast_count(0, Tensor([1, 2, 3]).neg().mul(-1)) - _check_ast_count(0, Tensor([1, 2, 3]).neg().neg()) - - def test_neg_realized_no_fold(self): - x = Tensor.randn(32, 32) - x = x.clip(0, 1).realize() - _check_ast_count(1, x.neg()) - -class TestBinaryOpsConstFolding(unittest.TestCase): - def test_add_literal_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + 0) - def test_add_tensor_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(4)) - def test_literal_zero_add(self): - _check_ast_count(0, 0 + Tensor([1.0, 2, 3, 4])) - def test_tensor_zero_add(self): - _check_ast_count(0, Tensor.zeros(4) + Tensor([1.0, 2, 3, 4])) - - def test_sub_literal_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) - 0) - def test_sub_tensor_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) - Tensor.zeros(4)) - - def test_mul_literal_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * 0) - def test_mul_tensor_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.zeros(4)) - def test_literal_zero_mul(self): - _check_ast_count(0, 0 * Tensor([1.0, 2, 3, 4]) * 0) - def test_tensor_zero_mul(self): - _check_ast_count(0, Tensor.zeros(4) * Tensor([1.0, 2, 3, 4])) - - def test_mul_literal_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * 1) - def test_mul_tensor_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.ones(4)) - def test_literal_one_mul(self): - _check_ast_count(0, 1 * Tensor([1.0, 2, 3, 4])) - def test_tensor_one_mul(self): - _check_ast_count(0, Tensor.ones(4) * Tensor([1.0, 2, 3, 4])) - - def test_bool_tensor_mul_bool(self): - _check_ast_count(0, Tensor([True, False]) * True) - _check_ast_count(0, Tensor([True, False]) * False) - def test_bool_mul_bool_tensor(self): - _check_ast_count(0, True * Tensor([True, False])) - _check_ast_count(0, False * Tensor([True, False])) - - def test_div_literal_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) / 1) - def test_div_tensor_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) / Tensor.ones(4)) - - @unittest.expectedFailure # TODO: fix - def test_idiv_literal_one(self): - _check_ast_count(0, Tensor([1, 2, 3, 4]) // 1) - @unittest.expectedFailure # TODO: fix - def test_idiv_tensor_one(self): - _check_ast_count(0, Tensor([1, 2, 3, 4]) // Tensor.ones(4, dtype=dtypes.int32)) - - def test_pow_literal_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** 0) - def test_pow_tensor_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** Tensor.zeros(4)) - - def test_pow_literal_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** 1) - def test_pow_tensor_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** Tensor.ones(4)) - def test_literal_one_pow(self): - _check_ast_count(0, 1 ** Tensor([1.0, 2, 3, 4])) - def test_tensor_one_pow(self): - _check_ast_count(0, Tensor.ones(4) ** Tensor([1.0, 2, 3, 4])) - -class TestBitcastConstFolding(unittest.TestCase): - def test_scalar_bitcast(self): - def t(cases: dict[DType, Any]): - for (from_dt, from_v), (to_dt, to_v) in itertools.product(cases.items(), cases.items()): - if not math.isnan(from_v): - r = full_rewrite_to_sink(UOp.const(from_dt, from_v).bitcast(to_dt).sink()).src[0] - self.assertEqual(r.op, Ops.CONST, msg:=f"{from_dt} -> {to_dt} ({from_v} -> {to_v})") - self.assertEqual(r.dtype, to_dt, msg) - np.testing.assert_equal(r.arg, to_v, msg) - - t({dtypes.int8: 0, dtypes.uint8: 0, dtypes.bool: False}) - t({dtypes.int8: 1, dtypes.uint8: 1, dtypes.bool: True}) - - t({dtypes.int8: -1, dtypes.uint8: 2**8-1}) - t({dtypes.int16: -1, dtypes.uint16: 2**16-1, dtypes.float16: float('nan')}) - t({dtypes.int32: -1, dtypes.uint32: 2**32-1, dtypes.float32: float('nan')}) - t({dtypes.int64: -1, dtypes.uint64: 2**64-1, dtypes.float64: float('nan')}) - - t({dtypes.int8: -2**7, dtypes.uint8: 2**7}) - t({dtypes.int16: -2**15, dtypes.uint16: 2**15}) - t({dtypes.int32: -2**31, dtypes.uint32: 2**31}) - t({dtypes.int64: -2**63, dtypes.uint64: 2**63}) - - t({dtypes.int16: 13496, dtypes.uint16: 13496, dtypes.float16: 0.294921875}) - t({dtypes.int32: 1050081145, dtypes.uint32: 1050081145, dtypes.float32: 0.29485681653022766}) - t({dtypes.int64: 4598983288165178391, dtypes.uint64: 4598983288165178391, dtypes.float64: 0.29485681936461233}) - - def test_vec_bitcast(self): - r = full_rewrite_to_sink(UOp.const(dtypes.int32.vec(3), (-1, -2**31, 75)).bitcast(dtypes.uint32.vec(3)).sink()).src[0] - self.assertEqual(r.op, Ops.VECTORIZE) - self.assertEqual(r.dtype, dtypes.uint32.vec(3)) - self.assertEqual(tuple(x.arg for x in r.src), (2**32-1, 2**31, 75)) - -# folds advance indexing into basic indexing -class TestIndexingConstFolding(unittest.TestCase): - def test_scalar_index(self): - t = Tensor.arange(16).float().reshape(1,1,4,4).realize() - # TODO: fold these - _check_ast_count(2, t[:,:,Tensor(1),:]) - _check_ast_count(2, t[:,:,Tensor(1)+2,:]) - _check_ast_count(2, t[:,:,Tensor(1),Tensor(0)]) - - @unittest.expectedFailure - def test_const_tensor_index(self): - # TODO: implement const tensor folded indexing - t = Tensor.arange(16).float().reshape(1,1,4,4).realize() - _check_ast_count(0, t[:,:,Tensor.ones(2,1),:]) - _check_ast_count(0, t[:,:,Tensor.ones(1,2)+2,:]) - _check_ast_count(0, t[:,:,Tensor.ones(1,1),Tensor.zeros(2,1,2)]) - -class TestMovedConstFolding(unittest.TestCase): - def test_add_shrunk_zero(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(6).shrink(((1, 5),))) - - def test_add_padded_zero(self): - # TODO: it's 1 now, this might be possible to fold - _check_ast_count(1, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(2).pad(((1, 1),))) - - def test_mul_shrunk_one(self): - _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.ones(6).shrink(((1, 5),))) - - def test_add_padded_one(self): - _check_ast_count(1, Tensor([1.0, 2, 3, 4]) * Tensor.ones(2).pad(((1, 1),))) - - def test_cast_padded(self): - # NOTE: this is folded due to CAST_BEFORE_VIEW - if is_dtype_supported(dtypes.int16): - _check_ast_count(0, Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int16)) - np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int16).numpy(), [0, 1, 1, 1, 1, 0]) - if is_dtype_supported(dtypes.uint16): - _check_ast_count(0, Tensor.full(4, fill_value=-1).pad(((1, 1),)).cast(dtypes.uint16)) - np.testing.assert_equal(Tensor.full(4, fill_value=-1).pad(((1, 1),)).cast(dtypes.uint16).numpy(), [0, 65535, 65535, 65535, 65535, 0]) - # folded - if is_dtype_supported(dtypes.int64): - _check_ast_count(0, Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int64)) - np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int64).numpy(), [0, 1, 1, 1, 1, 0]) - -class TestReduceOpsConstFolding(unittest.TestCase): - def test_const_sum(self): - _check_ast_count(0, Tensor.ones(4, 5, 6).sum()) - np.testing.assert_equal(Tensor.ones(4, 5, 6).sum().numpy(), 4 * 5 * 6) - _check_ast_count(0, Tensor.ones(4, 5, 6).sum(axis=0)) - np.testing.assert_equal(Tensor.ones(4, 5, 6).sum(axis=0).numpy(), np.full((5, 6), 4)) - _check_ast_count(0, Tensor(4).sum()) - np.testing.assert_equal(Tensor(4).sum().numpy(), 4) - - def test_padded_const_sum(self): - _check_ast_count(1, Tensor.ones(4).pad(((1, 1),)).sum()) - np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).sum().numpy(), 4) - - # NOTE: cannot just count the non-padded area because some Ops f do not have f(0) = 0. - _check_ast_count(1, Tensor.ones(4).pad(((1, 1),)).exp().sum()) - np.testing.assert_allclose(Tensor.ones(4).pad(((1, 1),)).exp().sum().numpy(), 4 * math.e + 2) - - def test_bool_zero_max(self): - _check_ast_count(0, Tensor.full((1, 2), True).shrink(((0, 1), (0, 0))).max((1, 0))) - np.testing.assert_equal(Tensor.full((1, 2), True).shrink(((0, 1), (0, 0))).max((1, 0)).numpy(), False) - - def test_zero_size_ops(self): - for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: # lambda x:x.max() NOTE: numpy gives "reduction operation maximum which has no identity" - _check_ast_count(0, reduceop(Tensor.empty(1, 0))) - np.testing.assert_equal(reduceop(Tensor.empty(shape:=(1, 0))).numpy(), reduceop(np.empty(shape))) - - def test_zero_size_ops_view(self): - for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: - _check_ast_count(0, reduceop(Tensor.empty(1, 0, 4).permute((1, 2, 0)).contiguous())) - np.testing.assert_equal(reduceop(Tensor.empty(shape:=(1, 0))).numpy(), reduceop(np.empty((shape)))) - - def test_zero_size_ops_realized(self): - for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: - _check_ast_count(0, reduceop((Tensor.randn(0, 1)+1).realize())) - np.testing.assert_equal(reduceop((Tensor.randn(shape:=(0, 1))+1).realize()).numpy(), reduceop(np.empty(shape))) - - def test_zero_size_realize_folded(self): - # non contiguous folded output doesn't realize - _check_ast_count(0, Tensor.empty(1, 0).sum()) - # contiguous folded const can still schedule - a = Tensor.empty(1, 0).sum().contiguous() - _check_ast_count(2, a+2) - self.assertIs(a.uop.base.op, Ops.BUFFER) - np.testing.assert_equal((Tensor.empty(1, 0).sum().contiguous()+2).numpy(), 2) - # otherwise we just fuse it - _check_ast_count(1, (Tensor.empty(1, 0).sum()+2).contiguous()) - np.testing.assert_equal((Tensor.empty(1, 0).sum()+2).numpy(), 2) - - def test_const_prod(self): - _check_ast_count(0, Tensor.full((2, 3), fill_value=2).prod()) - np.testing.assert_equal(Tensor.full((2, 3), fill_value=2).prod().numpy(), 2**(2*3)) - _check_ast_count(0, Tensor.full((4, 5, 6), fill_value=2).prod(axis=0)) - np.testing.assert_equal(Tensor.full((4, 5, 6), fill_value=2).prod(axis=0).numpy(), np.full((5, 6), 2**4)) - _check_ast_count(0, Tensor(4).prod()) - np.testing.assert_equal(Tensor(4).prod().numpy(), 4) - - def test_const_max(self): - _check_ast_count(0, Tensor.ones(4, 5, 6).max()) - np.testing.assert_equal(Tensor.ones(4, 5, 6).max().numpy(), 1) - _check_ast_count(0, Tensor(4).max()) - np.testing.assert_equal(Tensor(4).max().numpy(), 4) - - def test_sum_output_dtype(self): - # sum output dtype can be different from input - for dt in dtypes.fields().values(): - if is_dtype_supported(dt): - t = Tensor.ones(16, dtype=dt).reshape(4, 4) - assert t.sum().dtype == t.contiguous().sum().dtype - -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestMultiConstFolding(unittest.TestCase): - def test_multi_const_folding_literal(self): - ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) - t = Tensor.arange(16).float().to(ds).realize() - - # non const folding case creates one ast on each shard - _check_ast_count(4, t + 1) - _check_ast_count(4, 1 + t) - _check_ast_count(4, t * 2) - _check_ast_count(4, 2 * t) - - # const folded - _check_ast_count(0, t + 0) - _check_ast_count(0, 0 + t) - _check_ast_count(0, t * 0) - _check_ast_count(0, 0 * t) - _check_ast_count(0, t * 1) - _check_ast_count(0, 1 * t) - np.testing.assert_equal((t + 0).numpy(), np.arange(16)) - np.testing.assert_equal((t * 0).numpy(), [0] * 16) - np.testing.assert_equal((t * 1).numpy(), np.arange(16)) - - _check_ast_count(0, t ** 0) - _check_ast_count(0, t ** 1) - _check_ast_count(0, 1 ** t) - - def test_multi_const_folding_tensor(self): - ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) - t = Tensor.arange(16).float().to(ds).realize() - zero = Tensor.zeros(16).to(ds).realize() - one = Tensor.ones(16).to(ds).realize() - - # const folded - _check_ast_count(0, t + zero) - _check_ast_count(0, zero + t) - _check_ast_count(0, t * zero) - _check_ast_count(0, zero * t) - _check_ast_count(0, t * one) - _check_ast_count(0, one * t) - np.testing.assert_equal((t + zero).numpy(), np.arange(16)) - np.testing.assert_equal((t * zero).numpy(), [0] * 16) - np.testing.assert_equal((t * one).numpy(), np.arange(16)) - - def test_multi_todo_pow(self): - ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) - t = Tensor.arange(16).float().to(ds).realize() - zero = Tensor.zeros(16).to(ds).realize() - one = Tensor.ones(16).to(ds).realize() - - # TODO: fix pow folding - _check_ast_count(0, t ** zero) - _check_ast_count(0, t ** one) - _check_ast_count(0, one ** t) - -class TestTautologicalCompare(unittest.TestCase): - # without const folding, these would have triggered -Wtautological-compare in clang - def test_lt_false(self): - # bool < False is always false - np.testing.assert_equal((Tensor([True, False]) < False).numpy(), [False, False]) - - def test_true_lt(self): - # True < bool is always false - np.testing.assert_equal((True < Tensor([True, False])).numpy(), [False, False]) - - def test_truth_table(self): - np.testing.assert_equal((Tensor(False) < Tensor(False)).numpy(), False) - np.testing.assert_equal((Tensor(False) < Tensor(True)).numpy(), True) - np.testing.assert_equal((Tensor(True) < Tensor(False)).numpy(), False) - np.testing.assert_equal((Tensor(True) < Tensor(True)).numpy(), False) - - def test_a_eq_a(self): - # self eq is always true for int or bool - a = Tensor([1, 2, 3]) - np.testing.assert_equal((a == a).numpy(), [True, True, True]) - - # not true for nan - a = Tensor([math.nan, 1.0, 2.0]) - np.testing.assert_equal((a == a).numpy(), [False, True, True]) - - def test_a_ne_a(self): - # self not eq is always false for int or bool - a = Tensor([1, 2, 3]) - np.testing.assert_equal((a != a).numpy(), [False, False, False]) - - # not true for nan - a = Tensor([math.nan, 1.0, 2.0]) - np.testing.assert_equal((a != a).numpy(), [True, False, False]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_conv_shapetracker.py b/tinygrad/test/test_conv_shapetracker.py deleted file mode 100644 index e812827a..00000000 --- a/tinygrad/test/test_conv_shapetracker.py +++ /dev/null @@ -1,55 +0,0 @@ -#!/usr/bin/env python -import unittest -from tinygrad.uop.ops import Ops -from tinygrad.tensor import Tensor -from tinygrad.nn import Conv2d -from tinygrad.shape.shapetracker import ShapeTracker, View -from tinygrad.helpers import prod -from test.unit.test_shapetracker import shapetracker_getitem - -class TestConvShapetracker(unittest.TestCase): - def test_conv_3x3_one_view(self): - conv = Conv2d(16, 32, (3, 3)) - # first run to init the weights, they are scheduled. - conv(Tensor.empty(1, 16, 10, 10)).schedule() - # run it again to get the kernels - sched = [si for si in conv(Tensor.empty(1, 16, 10, 10)).schedule() if si.ast.op is Ops.SINK] - assert len(sched) == 1, f"conv should only have one kernel, getting {len(sched)}" - for st in [x.st_arg for x in sched[0].ast.toposort() if x.op is Ops.LOAD]: - assert len(st.views) == 1 - - def test_conv_2x2_backward_one_view(self): - X = Tensor.rand(1, 1, 3, 3, requires_grad=True) - conv = Conv2d(1, 1, (2, 2), bias=False) - conv(X).mean().backward() - si = X.grad.schedule()[-1] - print(si) - ldb = [x for x in si.ast.toposort() if x.op is Ops.LOAD][0] - st: ShapeTracker = ldb.st_arg.simplify() - print(si.bufs[1].size) - self.assertEqual(si.bufs[1].size, st.real_size()) - for v in st.views: print(v) - - # same st - test_st = ShapeTracker(( - View(shape=(1, 1, 2, 4, 2, 4), strides=(0, 0, 2, 8, 1, 4), offset=0, mask=((0, 1), (0, 1), (0, 2), (0, 2), (0, 2), (0, 2)), contiguous=False), - View(shape=(1, 1, 1, 1, 3, 3, 3, 3), strides=(0, 0, 0, 0, 24, 8, 3, 1), offset=0, - mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 2), (0, 3), (0, 2), (0, 3)), contiguous=False))) - #test_st = ShapeTracker(( - # View(shape=(2,4), strides=(1,4), offset=0, mask=None, contiguous=False), - #)).simplify() - #View(shape=(1, 1, 2, 4, 2, 4), strides=(0, 0, 2, 8, 1, 4), offset=0, mask=((0, 1), (0, 1), (0, 2), (0, 2), (0, 2), (0, 2)), contiguous=False), - #View(shape=(1, 1, 1, 1, 3, 3, 3, 3), strides=(0, 0, 0, 0, 24, 8, 3, 1), offset=0, - # mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 2), (0, 3), (0, 2), (0, 3)), contiguous=False))).simplify() - print("*** new ***") - for v in test_st.views: print(v) - for i in range(prod(st.shape)): - i1, i2 = shapetracker_getitem(st, i), shapetracker_getitem(test_st, i) - print(i, i1, i2, si.bufs[1].size, i1==i2) - #self.assertEqual(i1, i2) - - with self.assertRaises(AssertionError): - assert len(st.views) <= 2 - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_copy_speed.py b/tinygrad/test/test_copy_speed.py deleted file mode 100644 index 5d0cc69c..00000000 --- a/tinygrad/test/test_copy_speed.py +++ /dev/null @@ -1,67 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad import Device -from tinygrad.helpers import Timing, CI, OSX -import multiprocessing.shared_memory as shared_memory - -N = 4096 -class TestCopySpeed(unittest.TestCase): - @classmethod - def setUpClass(cls): Device[Device.DEFAULT].synchronize() - - def testCopySHMtoDefault(self): - s = shared_memory.SharedMemory(name="test_X", create=True, size=N*N*4) - s.close() - if CI and not OSX: - t = Tensor.empty(N, N, device="disk:/dev/shm/test_X").realize() - else: - t = Tensor.empty(N, N, device="disk:shm:test_X").realize() - for _ in range(3): - with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): - with Timing("queue: "): - t.to(Device.DEFAULT).realize() - Device[Device.DEFAULT].synchronize() - s.unlink() - - def testCopyCPUtoDefault(self): - t = Tensor.ones(N, N, device="CPU").contiguous().realize() - print(f"buffer: {t.nbytes()*1e-9:.2f} GB") - for _ in range(3): - with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): - with Timing("queue: "): - t.to(Device.DEFAULT).realize() - Device[Device.DEFAULT].synchronize() - - def testCopyCPUtoDefaultFresh(self): - print("fresh copy") - for _ in range(3): - t = Tensor.ones(N, N, device="CPU").contiguous().realize() - with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): # noqa: F821 - with Timing("queue: "): - t.to(Device.DEFAULT).realize() - Device[Device.DEFAULT].synchronize() - del t - - def testCopyDefaulttoCPU(self): - t = Tensor.ones(N, N).contiguous().realize() - print(f"buffer: {t.nbytes()*1e-9:.2f} GB") - for _ in range(3): - with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): - t.to('CPU').realize() - - @unittest.skipIf(CI, "CI doesn't have 6 GPUs") - @unittest.skipIf(Device.DEFAULT != "GPU", "only test this on GPU") - def testCopyCPUto6GPUs(self): - from tinygrad.runtime.ops_gpu import CLDevice - if len(CLDevice.device_ids) != 6: raise unittest.SkipTest("computer doesn't have 6 GPUs") - t = Tensor.ones(N, N, device="CPU").contiguous().realize() - print(f"buffer: {t.nbytes()*1e-9:.2f} GB") - for _ in range(3): - with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s ({t.nbytes()*6/ns:.2f} GB/s total)"): - with Timing("queue: "): - for g in range(6): - t.to(f"gpu:{g}").realize() - Device["gpu"].synchronize() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_device_speed.py b/tinygrad/test/test_device_speed.py deleted file mode 100644 index efb790c9..00000000 --- a/tinygrad/test/test_device_speed.py +++ /dev/null @@ -1,37 +0,0 @@ -import unittest -from tinygrad import Device -from tinygrad.helpers import Timing, Profiling - -class TestDeviceSpeed(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.dev = Device[Device.DEFAULT] - cls.empty = Device[Device.DEFAULT].renderer.render([]) - - def test_empty_compile(self): - with Timing("compiler "): - self.dev.compiler.compile(self.empty) - - def test_empty_compile_twice(self): - self.dev.compiler.compile(self.empty) - with Timing("compiler "): - self.dev.compiler.compile(self.empty) - - def test_launch_speed(self): - prg_bin = self.dev.compiler.compile(self.empty) - prg = self.dev.runtime("test", prg_bin) - for _ in range(10): prg() # ignore first launches - with Timing("launch 1000x "): - for _ in range(1000): prg() - with Timing("launch 1000x with wait "): - for _ in range(1000): prg(wait=True) - - def test_profile_launch_speed(self): - prg_bin = self.dev.compiler.compile(self.empty) - prg = self.dev.runtime("test", prg_bin) - for _ in range(10): prg() # ignore first launches - with Profiling(): - for _ in range(1000): prg() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_dtype.py b/tinygrad/test/test_dtype.py deleted file mode 100644 index 0a7a56c1..00000000 --- a/tinygrad/test/test_dtype.py +++ /dev/null @@ -1,984 +0,0 @@ -import unittest, operator, subprocess, math -import numpy as np -import torch -from typing import Any, List -from tinygrad.device import is_dtype_supported -from tinygrad.helpers import getenv, DEBUG, CI -from tinygrad.dtype import DType, DTYPES_DICT, ImageDType, PtrDType, least_upper_float, least_upper_dtype, truncate_fp16, truncate_bf16, to_dtype -from tinygrad.dtype import truncate, fp8_to_float, float_to_fp8 -from tinygrad import Device, Tensor, dtypes -from tinygrad.tensor import _to_np_dtype -from hypothesis import assume, given, settings, strategies as strat -from test.helpers import rand_for_dtype -import ml_dtypes -import pytest -pytestmark = pytest.mark.filterwarnings("ignore") - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") - -core_dtypes = list(DTYPES_DICT.values()) -if Device.DEFAULT == "CPU": core_dtypes.remove(dtypes.bfloat16) # NOTE: this is for teenygrad, don't remove -dtype_ints = [dt for dt in core_dtypes if dtypes.is_int(dt) and is_dtype_supported(dt)] -dtype_floats = [dt for dt in core_dtypes if dtypes.is_float(dt) and is_dtype_supported(dt)] -FP8E4M3_MAX = 448.0 -FP8E5M2_MAX = 57344.0 - -def get_available_cast_dtypes(dtype: DType) -> List[DType]: - if not is_dtype_supported(dtype): return [] - # dont cast internal dtypes - return [v for k, v in DTYPES_DICT.items() if v != dtype and is_dtype_supported(v) and not k.startswith("_")] - -def _test_to_np(a:Tensor, np_dtype, target): - if DEBUG >= 2: print(a) - na = a.numpy() - if DEBUG >= 2: print(na, na.dtype, a.uop.base.realized) - try: - assert na.dtype == np_dtype - np.testing.assert_allclose(na, target) - except AssertionError as e: - raise AssertionError(f"\ntensor {a.numpy()} does not match target {target} with np_dtype {np_dtype}") from e - -def _assert_eq(tensor:Tensor, target_dtype:DType, target, tol_target_dtype:float=1e-7): - if DEBUG >= 2: print(tensor.numpy()) - try: - assert tensor.dtype == target_dtype - np.testing.assert_allclose(tensor.numpy(), target, rtol={dtypes.float16:1e-3, dtypes.bfloat16:1e-2}.get(target_dtype, tol_target_dtype)) - except AssertionError as e: - raise AssertionError(f"\ntensor {tensor.numpy()} dtype {tensor.dtype} does not match target {target} with dtype {target_dtype}") from e - -def _test_op(fxn, target_dtype:DType, target): - _assert_eq(fxn(), target_dtype, target) -def _test_cast(a:Tensor, target_dtype:DType): - if a.is_floating_point() and dtypes.is_unsigned(target_dtype): - # converting negative float to unsigned integer is undefined - a = a.abs() - if target_dtype == dtypes.half and Device.DEFAULT == "PYTHON": - # TODO: struct.pack cannot pack value > 65504 (max of half) into e format - a = (a > 65504).where(65504, a) - - _test_op(lambda: a.cast(target_dtype), target_dtype, list(a.numpy().astype(_to_np_dtype(target_dtype)))) -def _test_bitcast(a:Tensor, target_dtype:DType, target=None): - if target_dtype == dtypes.bfloat16: raise unittest.SkipTest("no test for bf16 bitcast yet") - if getenv("PTX") and a.dtype == dtypes.int8 and target_dtype.itemsize != a.dtype.itemsize: - raise unittest.SkipTest("shape changing bitcast of int8 broken on PTX") - _test_op(lambda: a.bitcast(target_dtype), target_dtype, target or a.numpy().view(_to_np_dtype(target_dtype)).tolist()) - -class TestDType(unittest.TestCase): - DTYPE: Any = None - DATA: Any = None - @classmethod - def setUpClass(cls): - if not cls.DTYPE or not is_dtype_supported(cls.DTYPE): raise unittest.SkipTest("dtype not supported") - cls.DATA = rand_for_dtype(cls.DTYPE, 10) - def setUp(self): - if self.DTYPE is None: raise unittest.SkipTest("base class") - - def test_to_np(self): - _test_to_np(Tensor(self.DATA, dtype=self.DTYPE), _to_np_dtype(self.DTYPE), np.array(self.DATA, dtype=_to_np_dtype(self.DTYPE))) - - def test_casts_to(self): list(map( - lambda dtype: _test_cast(Tensor(self.DATA, dtype=dtype), self.DTYPE), - get_available_cast_dtypes(self.DTYPE) - )) - def test_casts_from(self): list(map( - lambda dtype: _test_cast(Tensor(self.DATA, dtype=self.DTYPE), dtype), - get_available_cast_dtypes(self.DTYPE) - )) - - def test_same_size_ops(self): - list(map( - lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize == self.DTYPE.itemsize else None, - get_available_cast_dtypes(self.DTYPE) - )) - def test_upcast_ops(self): - list(map( - lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize > self.DTYPE.itemsize else None, - get_available_cast_dtypes(self.DTYPE) - )) - def test_upcast_to_ops(self): - list(map( - lambda dtype: _test_ops(a_dtype=dtype, b_dtype=self.DTYPE) if dtype.itemsize < self.DTYPE.itemsize else None, - get_available_cast_dtypes(self.DTYPE) - )) - def test_bitcast(self): - if self.DTYPE == dtypes.bool: raise unittest.SkipTest("no bools in bitcast") - list(map( - lambda dtype: - _test_bitcast(Tensor(self.DATA[:8], dtype=self.DTYPE), dtype) if dtype != dtypes.bool else None, - get_available_cast_dtypes(self.DTYPE) - )) - - def test_dtypes_fields(self): - fields = dtypes.fields() - self.assertIn("float", fields) - self.assertIn("float32", fields) - self.assertEqual(len(fields), 26) - self.assertTrue(all(isinstance(value, DType) for value in fields.values())) - self.assertTrue(all(issubclass(_to_np_dtype(value), np.generic) for value in fields.values() if _to_np_dtype(value) is not None)) - - def test_resulting_and_init_dtypes_match(self): - dtypes = list(map(np.dtype, ["bool", "uint8", "int8", "int16", "int32", "int64", "float32", "float64"])) - data = [1., 2., 0., 0.5, -1.5, 5.25] - for dt in dtypes: - arr = np.asarray(data).astype(dt) - tensor = Tensor(arr) - if not is_dtype_supported(tensor.dtype): continue - tin = tensor.numpy() - tor = torch.as_tensor(arr).detach().numpy() - assert dt == tin.dtype == tor.dtype, f"dtype mismatch: expected={dt} | tinygrad={tin.dtype} | torch={tor.dtype}" - np.testing.assert_allclose(tin, tor, atol=1e-6, rtol=1e-3) - - def test_finfo(self): - if self.DTYPE not in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: return - info = np.finfo(_to_np_dtype(self.DTYPE)) - assert info.bits == self.DTYPE.itemsize*8 - assert info.nexp == dtypes.finfo(self.DTYPE)[0] - assert info.nmant == dtypes.finfo(self.DTYPE)[1] - -def _test_ops(a_dtype:DType, b_dtype:DType, target_dtype=None): - target_dtype = target_dtype or least_upper_dtype(a_dtype, b_dtype) - if not is_dtype_supported(a_dtype) or not is_dtype_supported(b_dtype) or not is_dtype_supported(target_dtype): return - if a_dtype == dtypes.bool or b_dtype == dtypes.bool: return - _assert_eq(Tensor([1,2,3,4], dtype=a_dtype)+Tensor([1,2,3,4], dtype=b_dtype), target_dtype, [2,4,6,8]) - _assert_eq((Tensor([1], dtype=a_dtype).cast(b_dtype)+Tensor([1], dtype=a_dtype).cast(b_dtype)).cast(a_dtype), a_dtype, [2]) - _assert_eq(Tensor([1,2,3,4], dtype=a_dtype)*Tensor([1,2,3,4], dtype=b_dtype), target_dtype, [1,4,9,16]) - _assert_eq(Tensor([[1,2],[3,4]], dtype=a_dtype)@Tensor.eye(2, dtype=b_dtype), target_dtype, [[1,2],[3,4]]) - _assert_eq(Tensor([1,1,1,1], dtype=a_dtype)+Tensor.ones((4,4), dtype=b_dtype), target_dtype, 2*Tensor.ones(4,4).numpy()) - -class TestFp8s(unittest.TestCase): - def test_fp8e4m3_creation(self): assert Tensor([-1, 1, 2], dtype=dtypes.fp8e4m3).dtype == dtypes.fp8e4m3 - def test_fp8e5m2_creation(self): assert Tensor([-1, 1, 2], dtype=dtypes.fp8e5m2).dtype == dtypes.fp8e5m2 - -class TestFp8sConversions(unittest.TestCase): - @given(strat.floats(width=32, allow_subnormal=True, allow_nan=False, allow_infinity=False, min_value=-FP8E4M3_MAX, max_value=FP8E4M3_MAX)) - def test_float_to_fp8e4m3(self, x): np.testing.assert_equal(float_to_fp8(x, dtypes.fp8e4m3), ml_dtypes.float8_e4m3fn(x).tobytes()[0]) - - def test_float_to_fp8e4m3_extreme_values(self): - np.testing.assert_equal(float_to_fp8(FP8E4M3_MAX, dtypes.fp8e4m3), 126) - np.testing.assert_equal(float_to_fp8(FP8E4M3_MAX*1.01, dtypes.fp8e4m3), 126) - np.testing.assert_equal(float_to_fp8(math.inf, dtypes.fp8e4m3), 126) - np.testing.assert_equal(float_to_fp8(-FP8E4M3_MAX, dtypes.fp8e4m3), 254) - np.testing.assert_equal(float_to_fp8(-FP8E4M3_MAX*1.01, dtypes.fp8e4m3), 254) - np.testing.assert_equal(float_to_fp8(-math.inf, dtypes.fp8e4m3), 254) - np.testing.assert_equal(float_to_fp8(math.nan, dtypes.fp8e4m3), 127) - np.testing.assert_equal(float_to_fp8(-math.nan, dtypes.fp8e4m3), 255) - - @given(strat.floats(width=32, allow_subnormal=True, allow_nan=False, allow_infinity=False, min_value=-FP8E5M2_MAX, max_value=FP8E5M2_MAX)) - def test_float_to_fp8e5m2(self, x): np.testing.assert_equal(float_to_fp8(x, dtypes.fp8e5m2), ml_dtypes.float8_e5m2(x).tobytes()[0]) - - def test_float_to_fp8e5m2_extreme_values(self): - np.testing.assert_equal(float_to_fp8(FP8E5M2_MAX, dtypes.fp8e5m2), 123) - np.testing.assert_equal(float_to_fp8(FP8E5M2_MAX*1.01, dtypes.fp8e5m2), 123) - np.testing.assert_equal(float_to_fp8(math.inf, dtypes.fp8e5m2), 123) - np.testing.assert_equal(float_to_fp8(-FP8E5M2_MAX, dtypes.fp8e5m2), 251) - np.testing.assert_equal(float_to_fp8(-FP8E5M2_MAX*1.01, dtypes.fp8e5m2), 251) - np.testing.assert_equal(float_to_fp8(-math.inf, dtypes.fp8e5m2), 251) - np.testing.assert_equal(float_to_fp8(math.nan, dtypes.fp8e5m2), 126) - np.testing.assert_equal(float_to_fp8(-math.nan, dtypes.fp8e5m2), 254) - - @given(strat.integers(min_value=0, max_value=255)) - def test_fp8e4m3_to_float(self, x): np.testing.assert_equal(fp8_to_float(x, dtypes.fp8e4m3), np.uint8(x).view(ml_dtypes.float8_e4m3fn).item()) - - @given(strat.integers(min_value=0, max_value=255)) - def test_fp8e5m2_to_float(self, x): np.testing.assert_equal(fp8_to_float(x, dtypes.fp8e5m2), np.uint8(x).view(ml_dtypes.float8_e5m2).item()) - -@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") -class TestBFloat16(unittest.TestCase): - def test_bf16_creation_numpy(self): - data = [-1, 1, 2] - t = Tensor(data, dtype=dtypes.bfloat16) - assert t.dtype == dtypes.bfloat16 - tnp = t.numpy() - assert tnp.dtype == np.float32 - np.testing.assert_allclose(tnp, np.array(data)) - - def test_bf16_ones(self): - t = Tensor.ones(3, 5, dtype=dtypes.bfloat16) - assert t.dtype == dtypes.bfloat16 - np.testing.assert_allclose(t.numpy(), np.ones((3, 5))) - - def test_bf16_eye(self): - t = Tensor.eye(3, dtype=dtypes.bfloat16) - assert t.dtype == dtypes.bfloat16 - np.testing.assert_allclose(t.numpy(), np.eye(3)) - -@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") -class TestBFloat16DType(unittest.TestCase): - def test_bf16_to_float(self): - _test_cast(Tensor([100000], dtype=dtypes.bfloat16), dtypes.float32) - - def test_float_to_bf16(self): - _test_cast(Tensor([100000], dtype=dtypes.float32), dtypes.bfloat16) - - def test_bf16(self): - t = Tensor([10000, -1, -1000, -10000, 20]).cast(dtypes.bfloat16) - t.realize() - back = t.cast(dtypes.float32) - assert tuple(back.numpy().tolist()) == (9984., -1, -1000, -9984, 20) - -@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") -class TestBFloat16DTypeCast(unittest.TestCase): - def test_f16_to_bf16_conversion(self): - original_tensor = Tensor([1.0, 2.0, 3.0], dtype=dtypes.float16) - converted_tensor = original_tensor.cast(dtypes.bfloat16) - self.assertEqual(converted_tensor.dtype, dtypes.bfloat16) - back_to_float32 = converted_tensor.cast(dtypes.float32) - original_to_float32 = original_tensor.cast(dtypes.float32) - np.testing.assert_allclose(back_to_float32.numpy(), original_to_float32.numpy(), rtol=1e-2, atol=1e-3) - - def test_f16_to_bf16_edge_cases(self): - edge_cases = Tensor([0.0, -0.0, float('inf'), float('-inf'), float('nan')], dtype=dtypes.float16) - converted = edge_cases.cast(dtypes.bfloat16).cast(dtypes.float32) - np.testing.assert_equal(converted.numpy(), edge_cases.cast(dtypes.float32).numpy()) - - def test_f16_to_bf16_range_precision(self): - large_value = Tensor([65504.0], dtype=dtypes.float16) # Max representable in float16 - small_value = Tensor([6.1035e-5], dtype=dtypes.float16) # Smallest positive normal float16 - large_converted = large_value.cast(dtypes.bfloat16).cast(dtypes.float32) - small_converted = small_value.cast(dtypes.bfloat16).cast(dtypes.float32) - np.testing.assert_allclose(large_converted.numpy(), large_value.cast(dtypes.float32).numpy(), rtol=1e-2, atol=1e-3) - np.testing.assert_equal(small_converted.numpy(), small_value.cast(dtypes.float32).numpy()) - - def test_f16_to_bf16_randomized(self): - np.random.seed(42) # For reproducibility - random_values = Tensor(np.random.uniform(-65504, 65504, 1000), dtype=dtypes.float16) - converted = random_values.cast(dtypes.bfloat16).cast(dtypes.float32) - np.testing.assert_allclose(converted.numpy(), random_values.cast(dtypes.float32).numpy(), rtol=1e-2, atol=1e-3) - -class TestHalfDType(TestDType): DTYPE = dtypes.half - -class TestFloatDType(TestDType): - DTYPE = dtypes.float - - def test_float_to_uint(self): - _test_op(lambda: Tensor([-0.9, -0.3, 1.2], dtype=dtypes.float32).cast(dtypes.uint32), dtypes.uint32, - [0, 0, 1]) - -class TestDoubleDType(TestDType): - DTYPE = dtypes.double - @unittest.skipIf((CI and Device.DEFAULT in {"CUDA", "NV"}) or getenv("PTX"), "conversion not supported on CI CUDA and PTX") # TODO: why not? - def test_float64_increased_precision(self): - for func in [ - lambda t: t.exp(), - lambda t: t.exp2(), - lambda t: t.log(), - lambda t: t.log2(), - lambda t: t.sqrt(), - lambda t: t.rsqrt(), - lambda t: t.sin(), - lambda t: t.cos(), - lambda t: t.tan(), - lambda t: t.sigmoid(), - ]: - a = [2, 3, 4] - np.testing.assert_allclose(func(Tensor(a, dtype=self.DTYPE)).numpy(), func(torch.tensor(a, dtype=torch.float64)), rtol=1e-12, atol=1e-12) - - def test_float64_to_float32_cast_inf(self): - _test_op(lambda: Tensor([3.4e40, 3.4e38, 1, 0], dtype=dtypes.float64).cast(dtypes.float32), - dtypes.float32, [float('inf'), 3.4e38, 1, 0]) - - -class TestInt8DType(TestDType): - DTYPE = dtypes.int8 - @unittest.skipIf(getenv("CUDA",0)==1 or getenv("PTX", 0)==1, "cuda saturation works differently") - def test_int8_to_uint8_negative(self): - _test_op(lambda: Tensor([-1, -2, -3, -4], dtype=dtypes.int8).cast(dtypes.uint8), dtypes.uint8, [255, 254, 253, 252]) - - def test_int8_to_uint16_negative(self): - _test_op(lambda: Tensor([-1, -2, -3, -4], dtype=dtypes.int8).cast(dtypes.uint16), dtypes.uint16, [2**16-1, 2**16-2, 2**16-3, 2**16-4]) - - @unittest.skipIf(getenv("PTX"), "broken in ptx") - def test_bitcast_alt(self): - a = Tensor([72, -90, 27, 40, -53, 70, 96, 51], dtype=dtypes.int8).bitcast(dtypes.short) - self.assertListEqual(a.tolist(), [-22968, 10267, 18123, 13152]) - -class TestUint8DType(TestDType): - DTYPE = dtypes.uint8 - @unittest.skipIf(getenv("CUDA",0)==1 or getenv("PTX", 0)==1, "cuda saturation works differently") - def test_uint8_to_int8_overflow(self): - _test_op(lambda: Tensor([255, 254, 253, 252], dtype=dtypes.uint8).cast(dtypes.int8), dtypes.int8, [-1, -2, -3, -4]) - -@unittest.skipIf(Device.DEFAULT == "WEBGL", "No bitcast on WebGL") -class TestBitCast(unittest.TestCase): - @given(strat.sampled_from(dtype_ints + dtype_floats), strat.sampled_from(dtype_ints + dtype_floats)) - def test_shape_change_bitcast(self, dt1, dt2): - # NOTE: this has to be assume to prevent hypothesis from skipping all samples - assume(dt2 != dtypes.bfloat16 and dt1 != dtypes.bfloat16) # no test for bf16 bitcast yet - assume(not (getenv("PTX") and dt1 == dtypes.int8)) # TODO: bitcasting int8 fails in PTX - data = rand_for_dtype(dt1, 32).reshape(2, 2, 8) - _test_op(lambda: Tensor(data, dtype=dt1).bitcast(dt2), dt2, data.view(_to_np_dtype(dt2)).tolist()) - - def test_shape_change_bitcast_exceptions(self): - with self.assertRaises(RuntimeError): - # should fail because 3 int8 is 3 bytes but float16 is two and 3 isn't a multiple of 2 - Tensor.empty((3,), dtype=dtypes.int8).bitcast(dtypes.float16) - - with self.assertRaises(RuntimeError): - # should fail because backprop through bitcast is undefined - Tensor.empty((4,), dtype=dtypes.int8, requires_grad=True).bitcast(dtypes.float16) - - def test_bitcast_float_to_int32(self): - a = Tensor([1.,2,3]) - b = a.bitcast(dtypes.int32) - assert b.numpy()[0] == 0x3f800000 - - def test_bitcast_upcasted(self): - a = Tensor.zeros(100, 4, dtype=dtypes.int32).contiguous() + 0x3f800000 - b = a.bitcast(dtypes.float32) - assert b.numpy()[0,0] == 1. - -class TestInt16DType(TestDType): DTYPE = dtypes.int16 - -class TestUint16DType(TestDType): - DTYPE = dtypes.uint16 - - def test_uint16_to_int8_overflow(self): - _test_op(lambda: Tensor([2**16-1, 2**16-2, 1, 0], dtype=dtypes.uint16).cast(dtypes.int8), dtypes.int8, [-1, -2, 1, 0]) - -class TestInt32DType(TestDType): DTYPE = dtypes.int32 -class TestUint32DType(TestDType): DTYPE = dtypes.uint32 - -class TestInt64DType(TestDType): DTYPE = dtypes.int64 -class TestUint64DType(TestDType): - DTYPE = dtypes.uint64 - def test_uint64_load(self): - assert Tensor(2**64 - 1, dtype=dtypes.uint64).numpy() == 2**64 - 1 - -class TestBoolDType(TestDType): DTYPE = dtypes.bool - -class TestPtrDType(unittest.TestCase): - def test_vec_double(self): - dt1 = dtypes.float.vec(4).ptr().vec(4) - dt2 = dtypes.float.vec(4).ptr().vec(4) - self.assertEqual(dt1, dt2) - self.assertEqual(str(dt1), str(dt2)) - - def test_scalar(self): - dt = dtypes.float.vec(4).ptr().scalar() - self.assertEqual(dt.base, dtypes.float.vec(4)) - - dt = dtypes.float.vec(4).ptr().vec(4).scalar() - self.assertEqual(dt.base, dtypes.float.vec(4)) - - dt = dtypes.float.vec(4).scalar() - self.assertEqual(dt, dtypes.float) - - def test_serialize(self): - dt = dtypes.float.vec(4).ptr().vec(4) - self.assertEqual(dt, eval(str(dt))) - - def test_vec_ptr_sz(self): - dt = dtypes.float.ptr(1024).vec(4) - self.assertEqual(dt, eval(str(dt))) - self.assertEqual(str(dt), "dtypes.float.ptr(1024).vec(4)") - - def test_vcount(self): - dt = dtypes.float.ptr().vec(4) - self.assertEqual(dt.vcount, 4) - self.assertEqual(dt.v, 4) - self.assertEqual(dt.count, 1) - - dt = dtypes.float.vec(4).ptr() - self.assertEqual(dt.vcount, 1) - self.assertEqual(dt.v, 1) - self.assertEqual(dt.count, 4) - - dt = dtypes.float.vec(4).ptr().vec(4) - self.assertEqual(dt.vcount, 4) - self.assertEqual(dt.v, 4) - self.assertEqual(dt.count, 4) - -class TestImageDType(unittest.TestCase): - def test_image_scalar(self): - assert dtypes.imagef((10,10)).base.scalar() == dtypes.float32 - assert dtypes.imageh((10,10)).base.scalar() == dtypes.float32 - def test_image_vec(self): - assert dtypes.imagef((10,10)).base.vec(4) == dtypes.float32.vec(4) - assert dtypes.imageh((10,10)).base.vec(4) == dtypes.float32.vec(4) - -class TestEqStrDType(unittest.TestCase): - def test_image_ne(self): - if ImageDType is None: raise unittest.SkipTest("no ImageDType support") - assert dtypes.float == dtypes.float32, "float doesn't match?" - assert dtypes.imagef((1,2,4)) != dtypes.imageh((1,2,4)), "different image dtype doesn't match" - assert dtypes.imageh((1,2,4)) != dtypes.imageh((1,4,2)), "different shape doesn't match" - assert dtypes.imageh((1,2,4)) == dtypes.imageh((1,2,4)), "same shape matches" - assert isinstance(dtypes.imageh((1,2,4)), ImageDType) - def test_ptr_eq(self): - assert dtypes.float32.ptr() == dtypes.float32.ptr() - assert not (dtypes.float32.ptr() != dtypes.float32.ptr()) - def test_strs(self): - if PtrDType is None: raise unittest.SkipTest("no PtrDType support") - self.assertEqual(str(dtypes.imagef((1,2,4))), "dtypes.imagef((1, 2, 4))") - self.assertEqual(str(dtypes.float32.ptr(16)), "dtypes.float.ptr(16)") - -class TestHelpers(unittest.TestCase): - signed_ints = (dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64) - uints = (dtypes.uint8, dtypes.uint16, dtypes.uint32, dtypes.uint64) - floats = (dtypes.float16, dtypes.float32, dtypes.float64) - - @given(strat.sampled_from(signed_ints+uints), strat.integers(min_value=1, max_value=8)) - def test_is_int(self, dtype, amt): - assert dtypes.is_int(dtype.vec(amt) if amt > 1 else dtype) - assert not dtypes.is_float(dtype.vec(amt) if amt > 1 else dtype) - - @given(strat.sampled_from(uints), strat.integers(min_value=1, max_value=8)) - def test_is_unsigned_uints(self, dtype, amt): - assert dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) - - @given(strat.sampled_from(signed_ints), strat.integers(min_value=1, max_value=8)) - def test_is_unsigned_signed_ints(self, dtype, amt): - assert not dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) - - @given(strat.sampled_from(floats), strat.integers(min_value=1, max_value=8)) - def test_is_float(self, dtype, amt): - assert dtypes.is_float(dtype.vec(amt) if amt > 1 else dtype) - assert not dtypes.is_int(dtype.vec(amt) if amt > 1 else dtype) - assert not dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) - - def test_bf16_is_float(self): - assert dtypes.is_float(dtypes.bfloat16) - - def test_fp8s_are_float(self): - assert dtypes.is_float(dtypes.fp8e4m3) - assert dtypes.is_float(dtypes.fp8e5m2) - - @given(strat.sampled_from([d for d in DTYPES_DICT.values() if dtypes.is_float(d) or dtypes.is_int(d)]), strat.integers(min_value=2, max_value=8)) - def test_scalar(self, dtype, amt): - assert dtype.vec(amt).scalar() == dtype - - def test_from_py(self): - assert dtypes.from_py(True) == dtypes.bool - assert dtypes.from_py(2) == dtypes.default_int - assert dtypes.from_py(3.0) == dtypes.default_float - assert dtypes.from_py([]) == dtypes.default_float - assert dtypes.from_py(()) == dtypes.default_float - assert dtypes.from_py([True]) == dtypes.bool - assert dtypes.from_py([True, 2]) == dtypes.default_int - assert dtypes.from_py([True, 3.0]) == dtypes.default_float - assert dtypes.from_py([2, 3.0]) == dtypes.default_float - assert dtypes.from_py([True, 2, 3.0]) == dtypes.default_float - with self.assertRaises(RuntimeError): dtypes.from_py(None) - with self.assertRaises(RuntimeError): dtypes.from_py([None]) - with self.assertRaises(RuntimeError): dtypes.from_py({}) - with self.assertRaises(RuntimeError): dtypes.from_py(set()) - - def test_dtype_range(self): - for dt in core_dtypes: - if dtypes.is_float(dt): - np.testing.assert_equal(dtypes.min(dt), -math.inf) - np.testing.assert_equal(dtypes.max(dt), math.inf) - np.testing.assert_equal(dt.min, -math.inf) - np.testing.assert_equal(dt.max, math.inf) - elif dtypes.is_int(dt): - info = np.iinfo(_to_np_dtype(dt)) - np.testing.assert_equal(dtypes.min(dt), info.min) - np.testing.assert_equal(dtypes.max(dt), info.max) - np.testing.assert_equal(dt.min, info.min) - np.testing.assert_equal(dt.max, info.max) - else: - assert dt == dtypes.bool, dt - np.testing.assert_equal(dtypes.min(dt), False) - np.testing.assert_equal(dtypes.max(dt), True) - np.testing.assert_equal(dt.min, False) - np.testing.assert_equal(dt.max, True) - - def test_truncate_fp16(self): - self.assertEqual(truncate_fp16(1), 1) - self.assertEqual(truncate_fp16(65504), 65504) - self.assertEqual(truncate_fp16(65519.999), 65504) - self.assertEqual(truncate_fp16(65520), math.inf) - - def test_truncate_bf16(self): - self.assertEqual(truncate_bf16(1), 1) - self.assertAlmostEqual(truncate_bf16(1.1), 1.09375, places=7) - for a in [1234, 23456, -777.777]: - self.assertEqual(truncate_bf16(a), torch.tensor([a], dtype=torch.bfloat16).item()) - # TODO: torch bfloat 1.1 gives 1.1015625 instead of 1.09375 - max_bf16 = torch.finfo(torch.bfloat16).max - self.assertEqual(truncate_bf16(max_bf16), max_bf16) - self.assertEqual(truncate_bf16(min_bf16:=-max_bf16), min_bf16) - self.assertEqual(truncate_bf16(max_bf16 * 1.00001), math.inf) - self.assertEqual(truncate_bf16(min_bf16 * 1.00001), -math.inf) - - @given(strat.floats(width=32, allow_subnormal=True, allow_nan=True, allow_infinity=True)) - def test_truncate_fp8e4m3(self, x): - if x > FP8E4M3_MAX: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), FP8E4M3_MAX) - elif x < -FP8E4M3_MAX: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), -FP8E4M3_MAX) - else: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), ml_dtypes.float8_e4m3fn(x)) - - @given(strat.floats(width=32, allow_subnormal=True, allow_nan=True, allow_infinity=True)) - def test_truncate_fp8e5m2(self, x): - if x > FP8E5M2_MAX: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), FP8E5M2_MAX) - elif x < -FP8E5M2_MAX: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), -FP8E5M2_MAX) - else: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), ml_dtypes.float8_e5m2(x)) - -class TestTypeSpec(unittest.TestCase): - def setUp(self): - self.old_default_int, self.old_default_float = dtypes.default_int, dtypes.default_float - def tearDown(self): - dtypes.default_int, dtypes.default_float = self.old_default_int, self.old_default_float - - def test_set_dtype_default(self): - for default_int in [dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64]: - dtypes.default_int = default_int - assert dtypes.default_int == default_int - - for default_float in [*dtypes.fp8s, dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: - dtypes.default_float = default_float - assert dtypes.default_float == default_float - - @unittest.skip("this test is slow and spawning whole pythons") - def test_env_set_default_float(self): - # check default - subprocess.run(['python3 -c "from tinygrad import dtypes; assert dtypes.default_float == dtypes.float"'], - shell=True, check=True) - # check change - subprocess.run(['DEFAULT_FLOAT=HALF python3 -c "from tinygrad import dtypes; assert dtypes.default_float == dtypes.half"'], - shell=True, check=True) - # check invalid - with self.assertRaises(subprocess.CalledProcessError): - subprocess.run(['DEFAULT_FLOAT=INT32 python3 -c "from tinygrad import dtypes"'], - shell=True, check=True) - - with self.assertRaises(subprocess.CalledProcessError): - subprocess.run(['DEFAULT_FLOAT=TYPO python3 -c "from tinygrad import dtypes"'], - shell=True, check=True) - - @unittest.skipUnless(is_dtype_supported(dtypes.int8), f"no int8 on {Device.DEFAULT}") - def test_dtype_str_arg(self): - n = np.random.normal(0, 1, (10, 10)).astype(np.float32) - tested = 0 - for dtype_str, dtype in [ - ("bool", dtypes.bool), ("int8", dtypes.int8), ("int", dtypes.int), ("uint32", dtypes.uint32), ("float32", dtypes.float32)]: - np.testing.assert_equal(Tensor(n, dtype=dtype_str).numpy(), Tensor(n, dtype=dtype).numpy()) - np.testing.assert_equal(Tensor(n).cast(dtype_str).numpy(), Tensor(n).cast(dtype).numpy()) - if dtype.itemsize == 4: - np.testing.assert_equal(Tensor(n).bitcast(dtype_str).numpy(), Tensor(n).bitcast(dtype).numpy()) - tested += 1 - assert tested == 3 - - with self.assertRaises(AttributeError): Tensor([1, 2, 3], dtype="nonexistdtype") - with self.assertRaises(AttributeError): Tensor([1, 2, 3], dtype="") - - np.testing.assert_equal(Tensor(n).sum(dtype="int16").numpy(), Tensor(n).sum(dtype=dtypes.int16).numpy()) - - @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_creation(self, default_int, default_float): - dtypes.default_int, dtypes.default_float = default_int, default_float - _assert_eq(Tensor(True), dtypes.bool, True) - _assert_eq(Tensor(None), dtypes.default_float, []) - _assert_eq(Tensor(2), dtypes.default_int, 2) - _assert_eq(Tensor(2.34), dtypes.default_float, 2.34) - _assert_eq(Tensor([]), dtypes.default_float, []) - _assert_eq(Tensor([1]), dtypes.default_int, [1]) - _assert_eq(Tensor([1.1]), dtypes.default_float, [1.1]) - - _assert_eq(Tensor.eye(0), dtypes.default_float, np.eye(0)) - _assert_eq(Tensor.eye(3), dtypes.default_float, np.eye(3)) - if is_dtype_supported(dtypes.int64): - _assert_eq(Tensor.eye(3, dtype=dtypes.int64), dtypes.int64, np.eye(3)) - if is_dtype_supported(dtypes.float16): - _assert_eq(Tensor.eye(3, dtype=dtypes.float16), dtypes.float16, np.eye(3)) - - @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_full(self, default_int, default_float): - dtypes.default_int, dtypes.default_float = default_int, default_float - - _assert_eq(Tensor.zeros((2, 3)), dtypes.default_float, np.zeros((2, 3))) - if is_dtype_supported(dtypes.int64): - _assert_eq(Tensor.zeros((2, 3), dtype=dtypes.int64), dtypes.int64, np.zeros((2, 3))) - if is_dtype_supported(dtypes.float16): - _assert_eq(Tensor.zeros((2, 3), dtype=dtypes.float16), dtypes.float16, np.zeros((2, 3))) - - _assert_eq(Tensor.ones((2, 3)), dtypes.default_float, np.ones((2, 3))) - if is_dtype_supported(dtypes.int64): - _assert_eq(Tensor.ones((2, 3), dtype=dtypes.int64), dtypes.int64, np.ones((2, 3))) - if is_dtype_supported(dtypes.float16): - _assert_eq(Tensor.ones((2, 3), dtype=dtypes.float16), dtypes.float16, np.ones((2, 3))) - - _assert_eq(Tensor.full((2, 3), 3.0), dtypes.default_float, np.full((2, 3), 3.0)) - _assert_eq(Tensor.full((2, 3), 3), dtypes.default_int, np.full((2, 3), 3)) - _assert_eq(Tensor.full((2, 3), True), dtypes.bool, np.full((2, 3), True)) - if is_dtype_supported(dtypes.int64): - _assert_eq(Tensor.full((2, 3), 3, dtype=dtypes.int64), dtypes.int64, np.full((2, 3), 3)) - _assert_eq(Tensor.full((2, 3), 3.0, dtype=dtypes.int64), dtypes.int64, np.full((2, 3), 3)) - if is_dtype_supported(dtypes.float16): - _assert_eq(Tensor.full((2, 3), 3, dtype=dtypes.float16), dtypes.float16, np.full((2, 3), 3)) - _assert_eq(Tensor.full((2, 3), 3.0, dtype=dtypes.float16), dtypes.float16, np.full((2, 3), 3)) - - @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_reduce_0d_default(self, default_int, default_float): - dtypes.default_int, dtypes.default_float = default_int, default_float - _assert_eq(Tensor.ones((2,3,0)).sum(2), dtypes.default_float, np.zeros((2, 3))) - # TODO: what should this one be? - # _assert_eq(Tensor.ones((2,3,0), dtype=dtypes.default_int).sum(2), dtypes.default_int, np.zeros((2, 3))) - _assert_eq(Tensor.ones((2,3,0), dtype=dtypes.int32).sum(2), dtypes.int32, np.zeros((2, 3))) - - @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_arange(self, default_int, default_float): - dtypes.default_int, dtypes.default_float = default_int, default_float - - _assert_eq(Tensor.arange(5), dtypes.default_int, np.arange(5)) - _assert_eq(Tensor.arange(120), dtypes.default_int, np.arange(120)) - _assert_eq(Tensor.arange(5.0), dtypes.default_float, np.arange(5)) - if is_dtype_supported(dtypes.int16): - _assert_eq(Tensor.arange(5, dtype=dtypes.int16), dtypes.int16, np.arange(5)) - if is_dtype_supported(dtypes.int64): - _assert_eq(Tensor.arange(5, dtype=dtypes.int64), dtypes.int64, np.arange(5)) - if is_dtype_supported(dtypes.float16): - _assert_eq(Tensor.arange(5, dtype=dtypes.float16), dtypes.float16, np.arange(5)) - _assert_eq(Tensor.arange(3, 9, 0.7), dtypes.default_float, np.arange(3, 9, 0.7), 1e-6 if Device.DEFAULT == "WEBGPU" else 1e-7) - _assert_eq(Tensor.arange(3, 8.5, 3), dtypes.default_float, np.arange(3, 8.5, 3)) - # stop-start and step have different signs - _assert_eq(Tensor.arange(3, 5, -2), dtypes.default_int, np.arange(3, 5, -2)) - _assert_eq(Tensor.arange(5.0, 3.0), dtypes.default_float, np.arange(5.0, 3.0)) - - @given(strat.sampled_from(core_dtypes), strat.sampled_from([operator.gt, operator.ge, operator.le, operator.lt, operator.eq, operator.ne])) - def test_bool_ops(self, dtype, op): - assert op(Tensor.ones(4, 4, dtype=dtype), Tensor.ones(4, 4, dtype=dtype)).dtype == dtypes.bool - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_functions_return_index(self, dtype, default_int, default_float): - dtypes.default_int, dtypes.default_float = default_int, default_float - assert Tensor([0, 1], dtype=dtype).argmax().dtype == dtypes.int32 - assert Tensor([0, 1], dtype=dtype).argmin().dtype == dtypes.int32 - assert Tensor([0, 1], dtype=dtype).multinomial().dtype == dtypes.int32 - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints)) - def test_tensor_indexing_returns_same_dtype(self, data_dtype, indices_dtype): - X_data = Tensor.ones(60000, 1, 28, 28, dtype=data_dtype) - indices = Tensor.randint(512, high=X_data.shape[0]).cast(indices_dtype) - assert X_data[indices].dtype == X_data.dtype - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints)) - def test_gather_returns_same_dtype(self, data_dtype, indices_dtype): - X_data = Tensor([[1, 0], [0, 1]], dtype=data_dtype) - indices = Tensor([[0, 0], [1, 0]], dtype=indices_dtype) - assert X_data.gather(0, indices).dtype == X_data.dtype - assert X_data.gather(1, indices).dtype == X_data.dtype - - @given(strat.sampled_from(dtype_floats), strat.sampled_from(dtype_floats)) - def test_attention_returns_same_dtype(self, data_dtype, default_float): - dtypes.default_float = default_float - query = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) - key = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) - value = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) - mask = (Tensor.rand(32, 8, 128, 128) < 0.5) - assert query.scaled_dot_product_attention(key, value, is_causal=True).dtype == data_dtype - assert query.scaled_dot_product_attention(key, value, is_causal=True, dropout_p=0.3).dtype == data_dtype - assert query.scaled_dot_product_attention(key, value, is_causal=False).dtype == data_dtype - assert query.scaled_dot_product_attention(key, value, attn_mask=mask).dtype == data_dtype - -class TestTypePromotion(unittest.TestCase): - @given(strat.sampled_from(core_dtypes)) - def test_self_promo_to_self(self, dtype): - assert least_upper_dtype(dtype) == dtype - assert least_upper_dtype(dtype, dtype) == dtype - assert least_upper_dtype(dtype, dtype, dtype) == dtype - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) - def test_promo_resulted_higher_than_inputs(self, dtype1, dtype2): - result = least_upper_dtype(dtype1, dtype2) - assert not (result < dtype1) and not (result < dtype2) - - def test_dtype_promo(self): - assert least_upper_dtype(dtypes.bool, dtypes.int8) == dtypes.int8 - assert least_upper_dtype(dtypes.int8, dtypes.uint8) == dtypes.int16 - assert least_upper_dtype(dtypes.uint8, dtypes.int16) == dtypes.int16 - assert least_upper_dtype(dtypes.int16, dtypes.uint16) == dtypes.int32 - assert least_upper_dtype(dtypes.uint16, dtypes.int32) == dtypes.int32 - assert least_upper_dtype(dtypes.int32, dtypes.uint32) == dtypes.int64 - assert least_upper_dtype(dtypes.uint32, dtypes.int64) == dtypes.int64 - # similar to jax but we don't use weak type - assert least_upper_dtype(dtypes.int64, dtypes.uint64) == dtypes.float16 - assert least_upper_dtype(dtypes.float16, dtypes.float32) == dtypes.float32 - assert least_upper_dtype(dtypes.float32, dtypes.float64) == dtypes.float64 - - assert least_upper_dtype(dtypes.bool, dtypes.float32) == dtypes.float32 - assert least_upper_dtype(dtypes.bool, dtypes.float64) == dtypes.float64 - assert least_upper_dtype(dtypes.float16, dtypes.int64) == dtypes.float16 - assert least_upper_dtype(dtypes.float16, dtypes.uint64) == dtypes.float16 - assert least_upper_dtype(dtypes.fp8e4m3, dtypes.fp8e5m2) == dtypes.half - -class TestAutoCastType(unittest.TestCase): - def setUp(self): - self.old_default_int, self.old_default_float = dtypes.default_int, dtypes.default_float - def tearDown(self): - dtypes.default_int, dtypes.default_float = self.old_default_int, self.old_default_float - - @given(strat.sampled_from(dtype_floats), strat.sampled_from(dtype_floats)) - def test_least_upper_float_input_is_float(self, input_dtype, default_float): - dtypes.default_float = default_float - self.assertEqual(least_upper_float(input_dtype), input_dtype) - - @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) - def test_least_upper_float_input_is_int(self, input_dtype, default_float): - dtypes.default_float = default_float - self.assertEqual(least_upper_float(input_dtype), default_float) - - @given(strat.sampled_from([d for d in core_dtypes if dtypes.is_int(d) and is_dtype_supported(d)])) - def test_int_to_float_unary_func(self, dtype): - for func in [ - lambda t: t.exp(), - lambda t: t.exp2(), - lambda t: t.log(), - lambda t: t.log2(), - lambda t: t.sqrt(), - lambda t: t.rsqrt(), - lambda t: t.sin(), - lambda t: t.cos(), - lambda t: t.tan(), - lambda t: t.sigmoid(), - ]: - a = [2, 3, 4] - # float16 can have larger precision errors - np.testing.assert_allclose(func(Tensor(a, dtype=dtype)).numpy(), func(torch.tensor(a)), rtol=1e-3, atol=1e-3) - - @given(strat.sampled_from(core_dtypes)) - def test_broadcast_scalar(self, dt): - assert (Tensor.ones(4, 4, dtype=dt) + 2.3).dtype == (dt if dtypes.is_float(dt) else dtypes.default_float) - assert (Tensor.ones(4, 4, dtype=dt) + 2).dtype == (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int) - assert (Tensor.ones(4, 4, dtype=dt) + True).dtype == dt - - @given(strat.sampled_from(dtype_floats)) - def test_int_div_int(self, default_float): - dtypes.default_float = default_float - self.assertEqual(Tensor([1]).div(Tensor([2])).dtype, default_float) - - def test_sum(self): - assert (Tensor([0, 1], dtype=dtypes.bool)).sum().dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int8)).sum().dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int16)).sum().dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int32)).sum().dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int64)).sum().dtype == dtypes.int64 - assert (Tensor([0, 1], dtype=dtypes.uint8)).sum().dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint16)).sum().dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint32)).sum().dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint64)).sum().dtype == dtypes.uint64 - assert (Tensor([0, 1], dtype=dtypes.float16)).sum().dtype == dtypes.float16 - #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).sum().dtype == dtypes.bfloat16 - assert (Tensor([0, 1], dtype=dtypes.float32)).sum().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.float64)).sum().dtype == dtypes.float64 - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16") - def test_sum_dtype_arg(self): - t = Tensor([40000, 40000], dtype=dtypes.float16) - # default float16 sum returns in float16, overflowed in this case - assert t.sum().dtype == dtypes.float16 - assert math.isinf(t.sum().numpy().item()) - # specifiying dtype and it's not downcasted - assert t.sum(dtype=dtypes.float32).dtype == dtypes.float32 - np.testing.assert_allclose(t.sum(dtype=dtypes.float32).numpy(), 80000) - - def test_prod_dtype_arg(self): - t = Tensor([100, 200], dtype=dtypes.int32) - assert t.prod().dtype == dtypes.int32 - np.testing.assert_allclose(t.prod().numpy(), 20000) - assert t.prod(dtype=dtypes.float32).dtype == dtypes.float32 - np.testing.assert_allclose(t.prod(dtype=dtypes.float32).numpy(), 20000) - - def test_mean(self): - assert (Tensor([0, 1], dtype=dtypes.bool)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.int8)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.int16)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.int32)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.int64)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.uint8)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.uint16)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.uint32)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.uint64)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.float16)).mean().dtype == dtypes.float16 - #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).mean().dtype == dtypes.bfloat16 - assert (Tensor([0, 1], dtype=dtypes.float32)).mean().dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.float64)).mean().dtype == dtypes.float64 - - def test_cumsum(self): - assert (Tensor([0, 1], dtype=dtypes.bool)).cumsum(0).dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int8)).cumsum(0).dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int16)).cumsum(0).dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int32)).cumsum(0).dtype == dtypes.int32 - assert (Tensor([0, 1], dtype=dtypes.int64)).cumsum(0).dtype == dtypes.int64 - assert (Tensor([0, 1], dtype=dtypes.uint8)).cumsum(0).dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint16)).cumsum(0).dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint32)).cumsum(0).dtype == dtypes.uint32 - assert (Tensor([0, 1], dtype=dtypes.uint64)).cumsum(0).dtype == dtypes.uint64 - assert (Tensor([0, 1], dtype=dtypes.float16)).cumsum(0).dtype == dtypes.float16 - #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).cumsum(0).dtype == dtypes.bfloat16 - assert (Tensor([0, 1], dtype=dtypes.float32)).cumsum(0).dtype == dtypes.float32 - assert (Tensor([0, 1], dtype=dtypes.float64)).cumsum(0).dtype == dtypes.float64 - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) - def test_matmul(self, dt1, dt2, acc_dt): - t1 = Tensor([0, 1], dtype=dt1) - t2 = Tensor([0, 1], dtype=dt2) - self.assertEqual(t1.matmul(t2).dtype, least_upper_dtype(t1.dtype, t2.dtype)) - # if dtype is specified, return in dtype - self.assertEqual(t1.matmul(t2, dtype=acc_dt).dtype, acc_dt) - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) - def test_linear(self, dt1, dt2, dt3, acc_dt): - x = Tensor([0, 1], dtype=dt1) - w = Tensor([0, 1], dtype=dt2) - b = Tensor([0, 1], dtype=dt3) - self.assertEqual(x.linear(w).dtype, least_upper_dtype(x.dtype, w.dtype)) - self.assertEqual(x.linear(w, b).dtype, least_upper_dtype(least_upper_dtype(x.dtype, w.dtype), b.dtype)) - # if dtype is specified, return in dtype - self.assertEqual(x.linear(w, dtype=acc_dt).dtype, acc_dt) - self.assertEqual(x.linear(w, b, dtype=acc_dt).dtype, acc_dt) - - @staticmethod - def check_where_alternate_input_other(input_, other, data_type): - assert (Tensor([True, False]).where(input_, other)).dtype == data_type - assert (Tensor([True, False]).where(other, input_)).dtype == data_type - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) - def test_where_no_scalar(self, dt1, dt2): - self.check_where_alternate_input_other(Tensor(2, dtype=dt1), Tensor(3, dtype=dt2), least_upper_dtype(dt1, dt2)) - - @given(strat.sampled_from(core_dtypes)) - def test_where_one_scalar(self, dt): - t = Tensor(2, dtype=dt) - self.check_where_alternate_input_other(t, 3.2, (dt if dtypes.is_float(dt) else dtypes.default_float)) - self.check_where_alternate_input_other(t, 3, (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int)) - self.check_where_alternate_input_other(t, True, dt) - - def test_where_two_scalars(self): - self.check_where_alternate_input_other(3.1, 3.2, dtypes.default_float) - self.check_where_alternate_input_other(3.1, 3, dtypes.default_float) - self.check_where_alternate_input_other(3.1, True, dtypes.default_float) - self.check_where_alternate_input_other(3, 2, dtypes.default_int) - self.check_where_alternate_input_other(3, True, dtypes.default_int) - self.check_where_alternate_input_other(False, True, dtypes.bool) - - @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) - def test_maximum(self, dt1, dt2): - assert Tensor([0, 1, 2], dtype=dt1).maximum(Tensor([2, 0, 5], dtype=dt2)).dtype == least_upper_dtype(dt1, dt2) - - @given(strat.sampled_from(core_dtypes)) - def test_maximum_const(self, dt): - assert Tensor([1, 2], dtype=dt).maximum(3.1).dtype == (dt if dtypes.is_float(dt) else dtypes.default_float) - assert Tensor([1, 2], dtype=dt).maximum(3).dtype == (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int) - assert Tensor([1, 2], dtype=dt).maximum(True).dtype == dt - - def test_div(self): - assert (Tensor([1, 2], dtype=dtypes.int32) / Tensor([2, 2], dtype=dtypes.int32)).dtype == dtypes.default_float - assert (Tensor([1, 2], dtype=dtypes.int16) / Tensor([2, 2], dtype=dtypes.int32)).dtype == dtypes.default_float - assert (Tensor([1, 2], dtype=dtypes.float32) / Tensor([2, 2], dtype=dtypes.float16)).dtype == dtypes.float32 - assert (Tensor([1, 2], dtype=dtypes.int32) / Tensor([2, 2], dtype=dtypes.float16)).dtype == dtypes.float16 - - def test_div_const(self): - assert (Tensor([1, 2], dtype=dtypes.int32) / 2).dtype == dtypes.default_float - assert (Tensor([1, 2], dtype=dtypes.int32) / 2.0).dtype == dtypes.default_float - assert (Tensor([1, 2], dtype=dtypes.float16) / 2).dtype == dtypes.float16 - assert (Tensor([1, 2], dtype=dtypes.float16) / 2.0).dtype == dtypes.float16 - - def test_gradient_dtype(self): - old_default_float = dtypes.default_float - - for default_dtype in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: - if not is_dtype_supported(default_dtype): continue - dtypes.default_float = default_dtype - for dtype in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: - if not is_dtype_supported(dtype): continue - if DEBUG >= 2: - print(f"testing {default_dtype=}, {dtype=}") - a = Tensor([1, 2, 3], dtype=dtype, requires_grad=True) - b = (a * 5).sum() - b.backward() # if there is dtype mismatch, lazy should assert - assert a.grad.dtype == a.dtype - np.testing.assert_allclose(a.grad.numpy(), [5, 5, 5]) - - dtypes.default_float = old_default_float - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_backward_sum_acc_dtype(self): - # test acc of sum in the backward is upcasted to float - t = Tensor([5, -5], dtype=dtypes.half, requires_grad=True) - t.reshape(2, 1).expand(2, 10001).max().backward() - np.testing.assert_allclose(t.grad.numpy(), [1, 0]) - - @unittest.skipIf(Device.DEFAULT == "PYTHON", "very slow") - @unittest.skipIf(CI and Device.DEFAULT == "AMD", "very slow") - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Binding size is larger than the maximum storage buffer binding size") - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_mean_half_precision_underflow(self): - N = 10000 - x = 0.001 - t = Tensor([[x]], dtype=dtypes.half, requires_grad=True).expand(N, N).contiguous() - np.testing.assert_allclose(t.mean(axis=1).numpy(), np.array([x] * N, dtype=np.float16), rtol=1e-3) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_mean_half_precision_overflow(self): - N = 256 - t = Tensor([60000] * N*N, dtype=dtypes.half, requires_grad=True).reshape(N, N) - np.testing.assert_allclose(t.mean().numpy(), 60000) - t.square().mean().backward() - np.testing.assert_allclose(t.grad.numpy().flatten(), [60000 * 2 / (N*N)] * N*N) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Precision error") - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_softmax_dtype(self): - data = [1, 2, 3] - t = Tensor(data, dtype=dtypes.half) - tt = torch.tensor(data, dtype=torch.half) - - out = t.softmax(0) - self.assertEqual(out.dtype, dtypes.half) - np.testing.assert_allclose(out.numpy(), tt.softmax(0).numpy(), rtol=1e-3) - out = t.softmax(0, dtype=dtypes.float) - self.assertEqual(out.dtype, dtypes.float) - np.testing.assert_allclose(out.numpy(), tt.softmax(0, dtype=torch.float).numpy(), rtol=1e-3) - out = t.log_softmax(0) - self.assertEqual(out.dtype, dtypes.half) - np.testing.assert_allclose(out.numpy(), tt.log_softmax(0).numpy(), rtol=1e-3) - out = t.log_softmax(0, dtype=dtypes.float) - self.assertEqual(out.dtype, dtypes.float) - np.testing.assert_allclose(out.numpy(), tt.log_softmax(0, dtype=torch.float).numpy(), rtol=1e-3) - -class TestImplicitFunctionTypeChange(unittest.TestCase): - def test_functions(self): - result = [] - for func in [ - lambda t: t.exp(), - lambda t: t.exp2(), - lambda t: t.log(), - lambda t: t.log2(), - lambda t: t.sqrt(), - lambda t: t.sin(), - ]: - t = func(Tensor([4.0, 3.0])).max() == func(Tensor([4.0, 3.0])) - result.append(t.numpy().sum()) - assert all(result) - -class TestTensorMethod(unittest.TestCase): - @given(strat.sampled_from(core_dtypes)) - def test_abs_diff(self, dt): - if dt == dtypes.bool or not is_dtype_supported(dt): return - a, b = Tensor([2], dtype=dt), Tensor([1], dtype=dt) - ret = (a - b).abs() - np.testing.assert_allclose(ret.numpy(), np.abs(a.numpy()-b.numpy())) - -class TestDtypeUsage(unittest.TestCase): - def test_max_w_alu(self): - for d in dtypes.ints: - if is_dtype_supported(d): - t = Tensor([[1, 2], [3, 4]], dtype=d) - (t*t).max().item() - -class TestToDtype(unittest.TestCase): - def test_dtype_to_dtype(self): - dtype = dtypes.int32 - res = to_dtype(dtype) - self.assertIsInstance(res, DType) - self.assertEqual(res, dtypes.int32) - - def test_str_to_dtype(self): - dtype = "int32" - res = to_dtype(dtype) - self.assertIsInstance(res, DType) - self.assertEqual(res, dtypes.int32) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_dtype_alu.py b/tinygrad/test/test_dtype_alu.py deleted file mode 100644 index 1b0fa945..00000000 --- a/tinygrad/test/test_dtype_alu.py +++ /dev/null @@ -1,212 +0,0 @@ -import unittest - -from tinygrad import Tensor, dtypes, Device -import operator -import numpy as np -from hypothesis import given, strategies as strat, settings, HealthCheck -from tinygrad.dtype import DType -from tinygrad.helpers import CI, getenv -from tinygrad.engine.realize import run_schedule -from tinygrad.uop.ops import GroupOp -from tinygrad.tensor import _to_np_dtype -from tinygrad.device import is_dtype_supported -import pytest, math -pytestmark = pytest.mark.filterwarnings("ignore") - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") -print(settings.default) - -dtypes_float = (dtypes.float16, dtypes.float32, dtypes.float64) -dtypes_int = (dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64, dtypes.uint8, dtypes.uint16, dtypes.uint32, dtypes.uint64) -dtypes_bool = (dtypes.bool,) -binary_operations = [operator.add, operator.sub, operator.mul, operator.lt, operator.eq] - -# TODO: LLVM comparing with nan is incorrect -if Device.DEFAULT == "LLVM" or getenv("AMD_LLVM", 0): - binary_operations.remove(operator.lt) - -integer_binary_operations = binary_operations + [(Tensor.bitwise_xor, np.bitwise_xor), (Tensor.bitwise_and, np.bitwise_and), - (Tensor.bitwise_or, np.bitwise_or), operator.mod] -unary_operations = [(Tensor.exp, np.exp), (Tensor.log, np.log), (Tensor.sin, np.sin), - (Tensor.sqrt, np.sqrt), (Tensor.reciprocal, np.reciprocal)] - -# TODO: enable this (this is a dtype issue) -#binary_operations.append(operator.truediv) - -# TODO: (a+b)/2 in tensor.py's maximum can overflow. This requires a new implementation of maximum that can be backpropagated -#binary_operations += [(Tensor.maximum, np.maximum)] - -# TODO: CI CUDA segfaults on sin, WEBGPU sin is not precise enough for large numbers -if (getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}) or Device.DEFAULT == "WEBGPU": unary_operations.remove((Tensor.sin, np.sin)) - -class ht: - float64 = strat.floats(width=64, allow_subnormal=False) - float32 = strat.floats(width=32, allow_subnormal=False) - float16 = strat.floats(width=16, allow_subnormal=False) - bfloat16 = strat.floats(width=16, allow_subnormal=False) - uint8 = strat.integers(0, 255) - uint16 = strat.integers(0, 65535) - uint32 = strat.integers(0, 2**32-1) - uint64 = strat.integers(0, 2**64-1) - int8 = strat.integers(-128, 127) - int16 = strat.integers(-32768, 32767) - int32 = strat.integers(-2147483648, 2147483647) - int64 = strat.integers(-9223372036854775808, 9223372036854775807) - bool = strat.booleans() - -def universal_test(a, b, dtype, op): - # The 'nan' cases only fail with Vulkan WebGPU backend (CI) - if (math.isnan(a) or math.isnan(b)) and Device.DEFAULT == "WEBGPU" and CI: return - if not isinstance(op, tuple): op = (op, op) - if op[0] == operator.mod and b == 0: return - ta, tb = Tensor([a], dtype=dtype), Tensor([b], dtype=dtype) - tensor_value = (op[0](ta, tb)).numpy() - numpy_value = op[1](ta.numpy(), tb.numpy()) - if dtype == dtypes.bfloat16: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-3, rtol=1e-2) - elif dtype in dtypes_float: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-10) - else: np.testing.assert_equal(tensor_value, numpy_value) - -def universal_test_unary(a, dtype, op): - if not isinstance(op, tuple): op = (op, op) - ta = Tensor([a], dtype=dtype) - out: Tensor = op[0](ta) - sched = out.schedule() - ast = sched[-1].ast - run_schedule(sched) - tensor_value = out.numpy() - numpy_value = op[1](ta.numpy()) - if dtype in (dtypes.float16, dtypes.bfloat16): np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-3, rtol=1e-2) - elif dtype in dtypes_float: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-6, rtol=1e-5) - else: np.testing.assert_equal(tensor_value, numpy_value) - if op[0] != Tensor.reciprocal: # reciprocal is not supported in most backends - op = [x for x in ast.toposort() if x.op in GroupOp.Unary][0] - assert op.dtype == dtype - -def universal_test_cast(a, in_dtype, dtype): - tensor_value = Tensor([a], dtype=in_dtype).cast(dtype) - numpy_value = np.array([a], dtype=_to_np_dtype(in_dtype)).astype(_to_np_dtype(dtype)) - np.testing.assert_equal(tensor_value.numpy(), numpy_value) - -@unittest.skipIf(Device.DEFAULT == "WEBGPU", "Inf and nan cases are wrong on WebGPU") -def universal_test_midcast(a, b, c, op1, op2, d1:DType, d2:DType): - if not isinstance(op1, tuple): op1 = (op1, op1) - if not isinstance(op2, tuple): op2 = (op2, op2) - at, bt, ct = Tensor([a], dtype=d1), Tensor([b], dtype=d1), Tensor([c], dtype=d2) - an, bn, cn = np.array([a]).astype(_to_np_dtype(d1)), np.array([b]).astype(_to_np_dtype(d1)), np.array([c]).astype(_to_np_dtype(d2)) - tensor_value = op2[0](op1[0](at, bt).cast(d2), ct).numpy() - numpy_value = op2[1](op1[1](an, bn).astype(_to_np_dtype(d2)), cn) - np.testing.assert_allclose(tensor_value, numpy_value, rtol=1e-6 if getenv("PTX") else 1e-7) - -class TestDTypeALU(unittest.TestCase): - @unittest.skipUnless(is_dtype_supported(dtypes.float64, Device.DEFAULT), f"no float64 on {Device.DEFAULT}") - @given(ht.float64, ht.float64, strat.sampled_from(binary_operations)) - def test_float64(self, a, b, op): universal_test(a, b, dtypes.float64, op) - - @given(ht.float32, ht.float32, strat.sampled_from(binary_operations)) - def test_float32(self, a, b, op): universal_test(a, b, dtypes.float32, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") - @given(ht.float16, ht.float16, strat.sampled_from(binary_operations)) - def test_float16(self, a, b, op): universal_test(a, b, dtypes.float16, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16, Device.DEFAULT), f"no bfloat16 on {Device.DEFAULT}") - @given(ht.bfloat16, ht.bfloat16, strat.sampled_from(binary_operations)) - def test_bfloat16(self, a, b, op): universal_test(a, b, dtypes.bfloat16, op) - - @given(ht.float32, strat.sampled_from(unary_operations)) - def test_float32_unary(self, a, op): universal_test_unary(a, dtypes.float32, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") - @given(ht.float16, strat.sampled_from(unary_operations)) - def test_float16_unary(self, a, op): universal_test_unary(a, dtypes.float16, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16, Device.DEFAULT), f"no bfloat16 on {Device.DEFAULT}") - @given(ht.bfloat16, strat.sampled_from(unary_operations)) - @unittest.skipIf(Device.DEFAULT in ["AMD"], "broken on AMD?") - def test_bfloat16_unary(self, a, op): universal_test_unary(a, dtypes.bfloat16, op) - - @given(ht.uint8, ht.uint8, strat.sampled_from(integer_binary_operations)) - def test_uint8(self, a, b, op): universal_test(a, b, dtypes.uint8, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.uint16, Device.DEFAULT), f"no uint16 on {Device.DEFAULT}") - @given(ht.uint16, ht.uint16, strat.sampled_from(integer_binary_operations)) - def test_uint16(self, a, b, op): universal_test(a, b, dtypes.uint16, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.uint32, Device.DEFAULT), f"no uint32 on {Device.DEFAULT}") - @given(ht.uint32, ht.uint32, strat.sampled_from(integer_binary_operations)) - def test_uint32(self, a, b, op): universal_test(a, b, dtypes.uint32, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.uint64, Device.DEFAULT), f"no uint64 on {Device.DEFAULT}") - @given(ht.uint64, ht.uint64, strat.sampled_from(integer_binary_operations)) - def test_uint64(self, a, b, op): universal_test(a, b, dtypes.uint64, op) - - @given(ht.int8, ht.int8, strat.sampled_from(integer_binary_operations)) - def test_int8(self, a, b, op): universal_test(a, b, dtypes.int8, op) - - @given(ht.int16, ht.int16, strat.sampled_from(integer_binary_operations)) - def test_int16(self, a, b, op): universal_test(a, b, dtypes.int16, op) - - @given(ht.int32, ht.int32, strat.sampled_from(integer_binary_operations)) - def test_int32(self, a, b, op): universal_test(a, b, dtypes.int32, op) - - @unittest.skipUnless(is_dtype_supported(dtypes.int64, Device.DEFAULT), f"no int64 on {Device.DEFAULT}") - @given(ht.int64, ht.int64, strat.sampled_from(integer_binary_operations)) - def test_int64(self, a, b, op): universal_test(a, b, dtypes.int64, op) - - @given(ht.bool, ht.bool, strat.sampled_from(((operator.add, operator.add), (operator.mul, operator.mul)))) - def test_bool(self, a, b, op): universal_test(a, b, dtypes.bool, op) - - @unittest.skipIf(not CI and Device.DEFAULT == "METAL", "broken on local M3") - @given(ht.int32, ht.int32, ht.float32, strat.sampled_from(integer_binary_operations), strat.sampled_from(binary_operations)) - def test_int32_midcast_float(self, a, b, c, op1, op2): universal_test_midcast(a, b, c, op1, op2, dtypes.int32, dtypes.float32) - - # Metal and CUDA and HIP behave differently than numpy in CI for overflows - skip_overflow = CI and Device.DEFAULT in {"AMD", "NV", "CUDA"} - @given(strat.floats(width=32, min_value=0, max_value=10.0) if skip_overflow else ht.float32, - strat.floats(width=32, min_value=0, max_value=10.0) if skip_overflow else ht.float32, - ht.int32, strat.sampled_from(binary_operations), strat.sampled_from(integer_binary_operations)) - @unittest.skipIf(Device.DEFAULT == "PYTHON", "TODO: fix cast inf to int32 in PYTHON") - def test_float_midcast_int32(self, a, b, c, op1, op2): universal_test_midcast(a, b, c, op1, op2, dtypes.float32, dtypes.int32) - - @unittest.skip("broken. TODO: fix it") - @given(ht.float32, strat.sampled_from(dtypes_float+dtypes_int+dtypes_bool)) - def test_float_cast(self, a, dtype): universal_test_cast(a, dtypes.float32, dtype) - - @unittest.skip("broken. TODO: fix it") - @given(ht.int32, strat.sampled_from(dtypes_float+dtypes_int+dtypes_bool)) - def test_int32_cast(self, a, dtype): universal_test_cast(a, dtypes.int32, dtype) - - @settings(suppress_health_check=[HealthCheck.filter_too_much]) - @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) - def test_float_cast_to_unsigned(self, a, float_dtype, unsigned_dtype): - if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 - float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] - float_strat = float_strat.filter(lambda x: 0 < x < dtypes.max(unsigned_dtype)) - universal_test_cast(a.draw(float_strat), float_dtype, unsigned_dtype) - - @settings(suppress_health_check=[HealthCheck.filter_too_much]) - @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) - def test_float_cast_to_unsigned_overflow(self, a, float_dtype, unsigned_dtype): - if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 - float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] - overflow_strat = float_strat.filter(lambda x: x > dtypes.max(unsigned_dtype) and x <= dtypes.max(dtypes.int32)) - universal_test_cast(a.draw(overflow_strat), float_dtype, unsigned_dtype) - - @settings(suppress_health_check=[HealthCheck.filter_too_much]) - @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) - def test_float_cast_to_unsigned_underflow(self, a, float_dtype, unsigned_dtype): - if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 - float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] - underflow_strat = float_strat.filter(lambda x: x < 0 and x >= dtypes.min(dtypes.int32)) - universal_test_cast(a.draw(underflow_strat), float_dtype, unsigned_dtype) - - @unittest.expectedFailure - def test_unsafe_cast_float_to_int_failure(self): - val = float(dtypes.max(dtypes.int32) - 1) - t1 = Tensor([val], dtype=dtypes.float32).cast(dtypes.int32) - t2 = Tensor(val, dtype=dtypes.float32).cast(dtypes.int32) - np.testing.assert_equal(t1.item(), t2.item()) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_edgecases.py b/tinygrad/test/test_edgecases.py deleted file mode 100644 index 001be44e..00000000 --- a/tinygrad/test/test_edgecases.py +++ /dev/null @@ -1,301 +0,0 @@ -# end to end tests of tinygrad that you think might be edge cases. -# using the documentation, write code you think should work. -# you can compare the outputs to torch or numpy, or just tinygrad assert/raise while doing things that should be valid - -# i'm not interested in tests that currently pass, i'm only interested in tests that you think should pass but don't. -# mark them with @unittest.expectedFailure -# all the tests in here didn't pass until bugs were fixed -# get creative! think about things that failed in pytorch or tensorflow for a long time until they were fixed. -# every test should surface a unique bug. if tinygrad throws an error saying something is not supported, this is probably not a bug. -# the tests don't have to test the same parts of the code that these current ones test, more diversity is better - -# focus on making tinygrad throw runtime errors or assertions for valid things, or find clear numerical mismatches from pytorch -# confirm any bugs found are valid by doing the same thing in pytorch in the test. -# for any failing tests, explain in a comment why tinygrad is wrong and what the desired behavior should be. -# don't worry about running mypy or linters. focus on writing more of these tests and running them to confirm broken behavior. -# surface level bugs, like issues with empty tensors, input validation, or nans, are not that interesting. -# focus on bugs that would frustrate real users. - -# these are not bugs, these are desired behavior. don't add failing tests for them: -# tinygrad only accepts tinygrad dtypes or strings of the tinygrad dtype. -# boolean indexing, or anything with unknown output shape of tensor at compile time isn't supported. -# invalid indexing in things like gather and one_hot is not an error in tinygrad. nothing that depends on the value is -# repeat_interleave doesn't support a tensor as the dim. check tinygrad type signature before claiming something is a bug - -import unittest -import numpy as np -import torch -from tinygrad import Tensor, dtypes, nn - -class TestNaNEdgeCases(unittest.TestCase): - # we don't need more of these. it's unclear if torch's behavior is desired here - - @unittest.expectedFailure - def test_max_nan(self): - # Reductions with NaN should propagate NaN like PyTorch. - arr = [1.0, float('nan'), 3.0] - torch_out = torch.tensor(arr).max().item() - out = Tensor(arr).max().numpy() - if np.isnan(torch_out): - self.assertTrue(np.isnan(out)) - else: - np.testing.assert_equal(out, torch_out) - - @unittest.skip("passes on webgpu") - @unittest.expectedFailure - def test_argmax_nan(self): - # PyTorch returns the index of the NaN, tinygrad returns the index of the maximum value. - arr = [1.0, float('nan'), 3.0] - torch_idx = torch.tensor(arr).argmax().item() - idx = Tensor(arr).argmax().item() - self.assertEqual(idx, torch_idx) - - @unittest.expectedFailure - def test_sort_with_nan(self): - # Sorting a tensor containing NaN should keep NaN at the end like PyTorch. - arr = [1.0, float('nan'), 3.0] - torch_vals, torch_idxs = torch.tensor(arr).sort() - vals, idxs = Tensor(arr).sort() - np.testing.assert_equal(vals.numpy(), torch_vals.numpy()) - np.testing.assert_equal(idxs.numpy(), torch_idxs.numpy().astype(np.int32)) - -class TestEmptyTensorEdgeCases(unittest.TestCase): - # we don't need more of these - - @unittest.expectedFailure - def test_sort_empty(self): - # Sorting an empty tensor works in PyTorch and should return empty - # values and indices. tinygrad raises an error instead. - torch_vals, torch_idxs = torch.tensor([]).sort() - values, indices = Tensor([]).sort() - np.testing.assert_equal(values.numpy(), torch_vals.numpy()) - np.testing.assert_equal(indices.numpy(), torch_idxs.numpy().astype(np.int32)) - - @unittest.expectedFailure - def test_max_empty(self): - # Max on an empty tensor should also raise an error. - with self.assertRaises(RuntimeError): - torch.tensor([]).max() - with self.assertRaises(RuntimeError): - Tensor([]).max() - - @unittest.expectedFailure - def test_argmax_empty(self): - # Argmax on an empty tensor should raise an error like torch does. - with self.assertRaises(RuntimeError): - torch.tensor([]).argmax() - with self.assertRaises(RuntimeError): - Tensor([]).argmax() - - @unittest.expectedFailure - def test_masked_select_empty(self): - # Masked select on empty tensors should return an empty tensor. - torch_out = torch.tensor([], dtype=torch.float32).masked_select(torch.tensor([], dtype=torch.bool)) - out = Tensor([], dtype=dtypes.float32).masked_select(Tensor([], dtype=dtypes.bool)) - np.testing.assert_equal(out.numpy(), torch_out.numpy()) - -class TestRollEdgeCases(unittest.TestCase): - # we don't need more of these - - @unittest.expectedFailure - def test_roll_mismatched_dims(self): - with self.assertRaises(RuntimeError): - torch.roll(torch.arange(9).reshape(3, 3), 1, dims=(0, 1)) - with self.assertRaises(RuntimeError): - Tensor.arange(9).reshape(3, 3).roll(1, dims=(0, 1)) - - @unittest.expectedFailure - def test_roll_extra_shift(self): - # tinygrad ignores extra shift values instead of raising - with self.assertRaises(RuntimeError): - torch.roll(torch.arange(10), (1, 2), dims=0) - with self.assertRaises(RuntimeError): - Tensor.arange(10).roll((1, 2), dims=0) - -class TestDropoutProbabilityEdgeCases(unittest.TestCase): - # we don't need more of these - - @unittest.expectedFailure - def test_dropout_rate_one(self): - # out is full of NaNs it should be 0s - with Tensor.train(): - out = Tensor.ones(100).dropout(1.0) - np.testing.assert_allclose(out.numpy(), np.zeros(100)) - - @unittest.expectedFailure - def test_dropout_invalid_prob(self): - # negative dropout probability should raise an error - with self.assertRaises(ValueError): - torch.nn.functional.dropout(torch.ones(10), -0.1, True) - with Tensor.train(): - out = Tensor.ones(10).dropout(-0.1) - np.testing.assert_allclose(out.numpy(), np.ones(10)) - -class TestInputValidation(unittest.TestCase): - # we don't need more of these, input validation bugs are not very interesting, many are WONTFIX - - @unittest.expectedFailure - def test_repeat_negative(self): - # repeating with a negative value should error like PyTorch - with self.assertRaises(RuntimeError): - torch.tensor([1, 2, 3]).repeat(-1, 2) - with self.assertRaises(RuntimeError): - Tensor([1, 2, 3]).repeat(-1, 2) - - @unittest.expectedFailure - def test_negative_weight_decay(self): - with self.assertRaises(ValueError): - torch.optim.AdamW([torch.tensor([1.], requires_grad=True)], lr=0.1, weight_decay=-0.1) - with self.assertRaises(ValueError): - nn.optim.AdamW([Tensor([1.], requires_grad=True)], lr=0.1, weight_decay=-0.1) - - @unittest.expectedFailure - def test_negative_lr(self): - with self.assertRaises(ValueError): - torch.optim.SGD([torch.tensor([1.], requires_grad=True)], lr=-0.1) - with self.assertRaises(ValueError): - nn.optim.SGD([Tensor([1.], requires_grad=True)], lr=-0.1) - - @unittest.expectedFailure - def test_negative_momentum(self): - with self.assertRaises(ValueError): - torch.optim.SGD([torch.tensor([1.], requires_grad=True)], lr=0.1, momentum=-0.1) - with self.assertRaises(ValueError): - nn.optim.SGD([Tensor([1.], requires_grad=True)], lr=0.1, momentum=-0.1) - -class TestZeroFolding(unittest.TestCase): - # we don't need more of these - - # folding rules treat x/x, x//x and x%x as constants even when x can be zero - @unittest.expectedFailure - def test_divide_by_self_with_zero(self): - x = Tensor([0.0, 1.0]) - torch_out = torch.tensor([0.0, 1.0]) / torch.tensor([0.0, 1.0]) - out = (x / x).numpy() - np.testing.assert_allclose(out, torch_out.numpy(), equal_nan=True) - - @unittest.expectedFailure - def test_floordiv_by_self_with_zero(self): - x = Tensor([0]) - with self.assertRaises(RuntimeError): - torch.tensor([0]) // torch.tensor([0]) - with self.assertRaises(RuntimeError): - (x // x).numpy() - - @unittest.expectedFailure - def test_mod_by_self_with_zero(self): - x = Tensor([0]) - with self.assertRaises(RuntimeError): - torch.tensor([0]) % torch.tensor([0]) - with self.assertRaises(RuntimeError): - (x % x).numpy() - -class TestArangeUOpValidationIssue(unittest.TestCase): - # these fail with UOp verification error. - # we don't need more of these involving arange - - @unittest.expectedFailure - def test_large_arange_sum(self): - # Summing a huge arange should either succeed or raise a MemoryError. - n = 2**31 + 3 - expected = (n - 1) * n // 2 - out = Tensor.arange(n).sum().item() - self.assertEqual(out, expected) - - @unittest.expectedFailure - def test_large_arange_index(self): - # Indexing a huge arange should return the correct value instead of failing - # with a UOp verification error. - n = 2**31 + 3 - out = Tensor.arange(n)[0].item() - self.assertEqual(out, 0) - - @unittest.expectedFailure - def test_large_arange_permute(self): - # Permuting a huge tensor should not trigger UOp verification failures. - n = 2**31 + 3 - out = Tensor.arange(n).reshape(n, 1).permute(1, 0) - self.assertEqual(out.shape, (1, n)) - out.realize() - -class TestAssignIssues(unittest.TestCase): - # these are good failures. i'm not sure we need more, but we need to fix these. - - @unittest.expectedFailure - def test_assign_permuted_view_constant(self): - # assigning to a permuted view should modify the underlying tensor - arr = np.arange(6).reshape(2, 3).astype(np.float32) - torch_tensor = torch.tensor(arr) - torch_tensor.t().copy_(torch.tensor([[5.0, 6.0], [7.0, 8.0], [9.0, 10.0]])) - t = Tensor(arr).contiguous().realize() - t.permute(1, 0).assign(Tensor([[5.0, 6.0], [7.0, 8.0], [9.0, 10.0]])) - np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) - - @unittest.expectedFailure - def test_assign_shrink_view_constant(self): - # assigning to a shrunk view should update the base tensor - arr = np.arange(9).reshape(3, 3).astype(np.float32) - torch_tensor = torch.tensor(arr) - torch_tensor[1:3, 1:3] = torch.ones(2, 2) - t = Tensor(arr).contiguous().realize() - t.shrink(((1, 3), (1, 3))).assign(Tensor.ones(2, 2)) - np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) - - @unittest.expectedFailure - def test_assign_broadcast(self): - # broadcasting during assign should behave like PyTorch - torch_tensor = torch.zeros(3, 5) - torch_tensor[:] = torch.arange(5) - t = Tensor.zeros(3, 5) - t.assign(Tensor.arange(5)) - np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) - -class TestUOpValidationIssue(unittest.TestCase): - # these fail with UOp verification error. - # we want more of these with diverse errors! - - @unittest.expectedFailure - def test_tensor_index_overflow(self): - # Advanced indexing on tensors expanded past int32 should not error, but - # tinygrad fails with a UOp verification error. - val = Tensor([1]) - big = val.expand(2**31 + 3) - idx = Tensor([0, 2**31 + 2]) - np.testing.assert_equal(big[idx].numpy(), np.array([1, 1])) - - def test_float_floordiv_scalar(self): - (Tensor.arange(4, dtype=dtypes.float32) // 2).realize() - - def test_float_floordiv_tensor(self): - (Tensor.arange(4, dtype=dtypes.float32) // Tensor.ones(4, dtype=dtypes.float32)).realize() - -class TestEdgeCases(unittest.TestCase): - # add tests exposing new and diverse kinds of bugs that might impact real users here - - @unittest.expectedFailure - def test_circular_pad_negative(self): - # negative pads with circular mode should wrap like PyTorch - arr = np.arange(9).reshape(1, 1, 3, 3).astype(np.float32) - torch_out = torch.nn.functional.pad(torch.tensor(arr), (1, -1, 1, -1), mode='circular') - out = Tensor(arr).pad((1, -1, 1, -1), mode='circular') - np.testing.assert_equal(out.numpy(), torch_out.numpy()) - - @unittest.expectedFailure - def test_arange_float_step(self): - # float steps should match PyTorch exactly - torch_out = torch.arange(0, 2, 0.3).numpy() - out = Tensor.arange(0, 2, 0.3).numpy() - np.testing.assert_allclose(out, torch_out) - - @unittest.skip("this is flaky") - @unittest.expectedFailure - def test_topk_ties_indices(self): - # topk should match PyTorch tie-breaking behavior when values are equal - arr = [1.0, 1.0, 1.0, 1.0] - _, ti = torch.tensor(arr).topk(2) - _, i = Tensor(arr).topk(2) - np.testing.assert_equal(i.numpy(), ti.numpy().astype(np.int32)) - - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/test_fusion_op.py b/tinygrad/test/test_fusion_op.py deleted file mode 100644 index 255479cc..00000000 --- a/tinygrad/test/test_fusion_op.py +++ /dev/null @@ -1,68 +0,0 @@ -import unittest -import time -import numpy as np -from tinygrad import Tensor, dtypes -from tinygrad.engine.realize import lower_schedule_item, run_schedule - -class TestFusionOp(unittest.TestCase): - def test_contiguous_add(self): - def test(contig=False): - bt = Tensor(np.arange(16), dtype=dtypes.float32).reshape(4,4) - x = bt.permute(1,0) - if contig: x = x.contiguous() - return (x.permute(1,0) + bt).data() - assert test() == test(True) - - def test_expand_fuse(self): - bt = Tensor(np.ones((10, 1)), dtype=dtypes.float32) - out = (bt*2).expand(10,10).sum(1) - sched = out.schedule() - run_schedule(sched) - outd = out.tolist() - assert all(x == 20.0 for x in outd) - - def test_recursive_add(self): - st = time.perf_counter() - a = Tensor([1,2,3,4]) - for _ in range(24): a = a + a - sched = a.schedule() - ei = lower_schedule_item(sched[-1]) - self.assertLess(time.perf_counter()-st, 2.0) - assert len(ei.prg.p.src.splitlines()) < 250 - - def test_recursive_add_cmp(self): - st = time.perf_counter() - a = Tensor([1,2,3,4]) - for _ in range(24): a = a + a - sched1 = a.schedule() - b = Tensor([1,2,3,4]) - for _ in range(24): b = b + b - sched2 = b.schedule() - c = Tensor([1,2,3,4]) - for _ in range(23): c = c + c - sched3 = c.schedule() - self.assertEqual(sched1[-1].ast, sched2[-1].ast) - with self.assertRaises(AssertionError): self.assertEqual(sched1[-1].ast, sched3[-1].ast) - self.assertLess(time.perf_counter()-st, 2.0) - - def test_recursive_pad(self): - st = time.perf_counter() - val = 1.0 - a = Tensor(val) - for _ in range(24): a = Tensor.stack(a, a)[0] - sched = a.schedule() - self.assertEqual(len(sched), 1) - self.assertLess(time.perf_counter()-st, 2.0) - - def test_recursive_reshape(self): - st = time.perf_counter() - a = Tensor.empty(32, 32).realize() - b = Tensor.empty(16, 2).realize() - r = a.sum(1) - for _ in range(24): r = r.reshape(16, 2) + b - sched = r.schedule() - self.assertEqual(len(sched), 1) - self.assertLess(time.perf_counter()-st, 2.0) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_gc.py b/tinygrad/test/test_gc.py deleted file mode 100644 index 78827a0f..00000000 --- a/tinygrad/test/test_gc.py +++ /dev/null @@ -1,113 +0,0 @@ -#!/usr/bin/env python -import gc, inspect -import unittest -import numpy as np -from tinygrad.device import Buffer -from tinygrad.engine.realize import run_schedule -from tinygrad.uop.ops import UOp -from tinygrad.tensor import Tensor - -def tensors_allocated(): - gc.collect() - return sum([isinstance(x, Tensor) for x in gc.get_objects()]) - -def bufs_allocated(): - gc.collect() - return sum([isinstance(x, Buffer) for x in gc.get_objects()]) - -class TestGC(unittest.TestCase): - - def test_gc(self): - Tensor.manual_seed(0) - base = tensors_allocated() - a = Tensor.rand(4, 4, requires_grad=True) - b = Tensor.zeros(4, 4, requires_grad=True) - (a*b).mean().backward() - assert (tensors_allocated()-base > 0) - del a,b - assert (tensors_allocated()-base == 2) # one for Tensor._device_rng_counters, and one for Tensor._device_seeds - Tensor.manual_seed(0) - - def test_gc_complex(self): - Tensor.manual_seed(0) - base = tensors_allocated() - a = Tensor(np.zeros((4, 4), dtype=np.float32), requires_grad=True) - b = Tensor.rand(4, 4, requires_grad=True) - assert (tensors_allocated()-base == 4) - (a*b).mean().backward() - assert (tensors_allocated()-base == 6) - del b - assert (tensors_allocated()-base == 4) - b = Tensor(np.zeros((4, 4), dtype=np.float32), requires_grad=True) - print(tensors_allocated()) - (a*b).mean().backward() - print(tensors_allocated()) - assert (tensors_allocated()-base == 6) - del b - assert (tensors_allocated()-base == 4) - Tensor.manual_seed(0) - - def test_schedule_gc(self): - init = bufs_allocated() - x = Tensor.ones(256).contiguous().realize() - y = Tensor.ones(5, 5).contiguous() - y.schedule() - del x - del y - self.assertEqual(bufs_allocated()-init, 0) - - def test_schedule_gc_with_inputs(self): - init = bufs_allocated() - x = Tensor.ones(256).contiguous().realize() - y = x+Tensor.ones(256).contiguous() - ys = y.schedule() - del x - run_schedule(ys) - np.testing.assert_equal(y.numpy(), np.full((256,), 2)) - self.assertEqual(bufs_allocated()-init, 1) - del y - self.assertEqual(bufs_allocated()-init, 0) - - def test_toposort_blocks_gc(self): - init = bufs_allocated() - x = Tensor.ones(4,4).contiguous().realize()+1 - self.assertEqual(bufs_allocated()-init, 1) - # try commenting this part out, it's green! - x.uop.toposort() - del x - if bufs_allocated()-init != 0: - print(inspect.getclosurevars(UOp.toposort().fget)) - raise AssertionError(f"never gced {[x for x in gc.get_objects() if isinstance(x, Buffer)]}") - - def test_buffer_refcount(self): - init = bufs_allocated() - a = Tensor.empty(10) - self.assertEqual(bufs_allocated()-init, 0) - a.realize() - real_buf = a.uop.buffer - # after the Tensor UOp is deleted there shouldn't be any references on the Buffer - self.assertEqual(real_buf.lb_refcount, 1) - self.assertEqual(bufs_allocated()-init, 1) - del a.uop - self.assertEqual(real_buf.lb_refcount, 0) - self.assertEqual(bufs_allocated()-init, 1) # keep the buffer alive - del real_buf - self.assertEqual(bufs_allocated()-init, 0) - - def test_assign_refcount(self): - init = bufs_allocated() - a = Tensor.full((4,), 1.).contiguous() - a.realize() - real_buf = a.uop.buffer - self.assertEqual(real_buf.lb_refcount, 1) - a.assign(Tensor.full((4,), 2.)) - self.assertIs(a.uop.src[0].buffer, real_buf) - # NOTE: this is still 1, we don't count the ASSIGN - self.assertEqual(real_buf.lb_refcount, 1) - a.realize() - del a - self.assertEqual(real_buf.lb_refcount, 0) # no UOps for this Buffer - self.assertEqual(bufs_allocated()-init, 1) # Buffer is alive - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_graph.py b/tinygrad/test/test_graph.py deleted file mode 100644 index 19dd6f9f..00000000 --- a/tinygrad/test/test_graph.py +++ /dev/null @@ -1,261 +0,0 @@ -import numpy as np -import functools, unittest, ctypes - -from tinygrad.device import Device, Buffer -from tinygrad.tensor import Tensor, _to_np_dtype -from tinygrad.helpers import Context, CI, dedup, from_mv -from tinygrad.dtype import dtypes -from tinygrad.engine.jit import MultiGraphRunner -from tinygrad.engine.realize import ExecItem, BufferXfer, get_runner, CompiledRunner - -np.random.seed(1337) -Tensor.manual_seed(1337) -BUF_SIZE = 4096 if CI else 4096 * 128 -RUN_CNT = 4 if CI else 32 - -cached_prgs = {} -def helper_exec_op(device, outbuf, inbufs): - if (device, len(inbufs)) not in cached_prgs: - with Context(DEBUG=0): - fst = [Tensor.randn(BUF_SIZE, dtype=dtypes.int).realize() for i in range(len(inbufs))] - s = fst[0] - for i in range(1, len(inbufs)): s = s.bitwise_xor(fst[i]) - - si = s.schedule()[-1] - prg = get_runner(device, si.ast) - cached_prgs[(device, len(inbufs))] = prg - - return ExecItem(cached_prgs[(device, len(inbufs))], [outbuf] + inbufs) - -def helper_copy_op(device, dest, src): - prg = BufferXfer(dest.nbytes, device, src.device) - return ExecItem(prg, [dest, src]) - -def helper_alloc_rawbuffer(device, fill=False): - rawbuf = Buffer(device, BUF_SIZE, dtypes.int).ensure_allocated() - if fill: - with Context(DEBUG=0): - data = np.random.randint(-10000, 10000, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) - rawbuf.copyin(Tensor(data).realize().uop.base.realized.as_buffer()) - return rawbuf - -def helper_create_offset_rawbuffer(base, offset=0): - x = Buffer(base.device, base.size-offset, base.dtype, base=base, offset=offset) - return x.ensure_allocated() - -def helper_run_jit(jis, bufs, out_buffers): - for rawbuf in out_buffers: - mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) - ctypes.memset(from_mv(mv), 0, len(mv)) - rawbuf.copyin(mv) - - for ei in jis: ei.run({}, jit=True) - return [rawbuf.as_buffer() for rawbuf in bufs] - -def helper_test_graphs(graph_impl, graphs, runs=RUN_CNT): - reg_ji = [] - bufs = [] - out_buffers = set() - for graph in graphs: - for ji in graph: - out_buffers.update([ji.bufs[i] for i in (ji.prg.p.outs if isinstance(ji.prg, CompiledRunner) else [0])]) - bufs += ji.bufs - reg_ji.append(ji) - bufs = dedup(bufs) - - ground_thruth_bufs = helper_run_jit(reg_ji, bufs, out_buffers) - ground_truth_np = [np.frombuffer(x, _to_np_dtype(bufs[i].dtype)) for i,x in enumerate(ground_thruth_bufs)] - - # Build graphs - gr_ji = [ExecItem(graph_impl(graph, [], {}), []) for graph in graphs] - - for _ in range(runs): - test_bufs = helper_run_jit(gr_ji, bufs, out_buffers) - test_bufs_np = [np.frombuffer(x, _to_np_dtype(bufs[i].dtype)) for i,x in enumerate(test_bufs)] - for i in range(len(ground_thruth_bufs)): np.testing.assert_equal(ground_truth_np[i], test_bufs_np[i]) - -@unittest.skipUnless(Device[Device.DEFAULT].graph is not None, "graph support required") -class TestGraph(unittest.TestCase): - def test_order_2_writes_to_same_buf(self): - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] - - graphs = [ - [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[0], [b0[3], b0[4]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_order_read_write_same_buf(self): - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] - - graphs = [ - [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[1], [b0[3], b0[4]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_order_write_read_same_buf(self): - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] - - graphs = [ - [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[1], [b0[0], b0[4]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def skip_if_not_multigraph(self): - graph = g.func if isinstance(g:=Device[Device.DEFAULT].graph, functools.partial) else g - if not issubclass(graph, MultiGraphRunner): self.skipTest("graph is not supported (not MultiGraphRunner)") - - def test_order_copy_writed(self): - self.skip_if_not_multigraph() - - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(4)] - - graphs = [ - [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_copy_op(d0, b0[3], b0[0])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_order_copy_then_read(self): - self.skip_if_not_multigraph() - - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(4)] - - graphs = [ - [helper_copy_op(d0, b0[1], b0[0]), helper_exec_op(d0, b0[3], [b0[1], b0[2]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_read_write_several_graphs(self): - d0 = Device.DEFAULT - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] - - graphs = [ - [helper_exec_op(d0, b0[3], [b0[1], b0[2]])], - [helper_exec_op(d0, b0[4], [b0[1], b0[3]])], - [helper_exec_op(d0, b0[5], [b0[4], b0[2]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - graphs = [ - [helper_exec_op(d0, b0[3], [b0[1], b0[2]]), helper_exec_op(d0, b0[4], [b0[1], b0[2]]), helper_exec_op(d0, b0[5], [b0[1], b0[2]])], - [helper_exec_op(d0, b0[2], [b0[6], b0[7]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_copies_2_devs(self): - self.skip_if_not_multigraph() - - d0, d1 = Device.DEFAULT, f"{Device.DEFAULT}:1" - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(3)] - b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(1)] - - graphs = [ - [helper_copy_op(d0, b1[0], b0[0]), helper_exec_op(d0, b0[2], [b0[0], b0[1]])] - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_copies_after_graph_global(self): - self.skip_if_not_multigraph() - - d0, d1, d2, d3 = Device.DEFAULT, f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3" - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] - b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(6)] - b2 = [helper_alloc_rawbuffer(d2, fill=True) for _ in range(6)] - b3 = [helper_alloc_rawbuffer(d3, fill=True) for _ in range(6)] - - graphs = [ - [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_exec_op(d0, b0[6], [b0[1], b0[2]]), helper_exec_op(d0, b0[7], [b0[0], b0[2]])], - [helper_copy_op(d1, b0[2], b1[0])], - [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_exec_op(d0, b0[6], [b0[1], b0[2]]), helper_exec_op(d0, b0[7], [b0[0], b0[2]])], - [helper_copy_op(d3, b0[2], b3[0])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - graphs = [ - [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_copy_op(d0, b2[0], b0[2]), helper_copy_op(d0, b2[1], b0[5]), - helper_exec_op(d0, b0[7], [b0[0], b0[2]])], - [helper_copy_op(d1, b0[2], b1[0])], - [helper_exec_op(d0, b0[2], [b0[0], b0[1]])], - [helper_copy_op(d3, b0[2], b3[0])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - graphs = [ - [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_copy_op(d0, b2[0], b0[2]), helper_copy_op(d0, b2[1], b0[5]), - helper_exec_op(d0, b0[7], [b0[0], b0[2]])], - [helper_copy_op(d1, b0[5], b1[0])], - [helper_copy_op(d3, b0[5], b3[0])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - graphs = [ - [helper_copy_op(d1, b0[5], b1[0])], - [helper_copy_op(d3, b0[5], b3[0])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_graph_after_copies_devs(self): - self.skip_if_not_multigraph() - - d0, d1, d2, d3 = Device.DEFAULT, f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3" - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] - b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(1)] - b2 = [helper_alloc_rawbuffer(d2, fill=True) for _ in range(2)] - b3 = [helper_alloc_rawbuffer(d3, fill=True) for _ in range(2)] - - graphs = [ - [helper_copy_op(d1, b0[0], b1[0])], - [helper_copy_op(d2, b0[1], b2[0]), helper_copy_op(d3, b0[2], b3[0])], - [helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - graphs = [ - [helper_copy_op(d1, b0[0], b1[0])], - [helper_exec_op(d0, b0[2], [b0[0], b0[1]])], - [helper_copy_op(d2, b0[1], b2[0]), helper_copy_op(d3, b0[2], b3[0])], - [helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), - helper_exec_op(d0, b0[5], [b0[0], b0[2]])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - - def test_graph_offset_bufs(self): - self.skip_if_not_multigraph() - - d0 = Device.DEFAULT - if not hasattr(Device[d0].allocator, "_offset"): self.skipTest("device does not support _offset") - - b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(1)] - b0 += [helper_create_offset_rawbuffer(b0[0]), helper_create_offset_rawbuffer(b0[0])] - - graphs = [ - [helper_copy_op(d0, b0[0], b0[2]), helper_exec_op(d0, b0[1], [b0[0], b0[2]])], - ] - - helper_test_graphs(Device[d0].graph, graphs) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_hcq.py b/tinygrad/test/test_hcq.py deleted file mode 100644 index 884c5fc2..00000000 --- a/tinygrad/test/test_hcq.py +++ /dev/null @@ -1,539 +0,0 @@ -import unittest, ctypes, struct, os, random -from tinygrad import Device, Tensor, dtypes -from tinygrad.helpers import getenv, CI, mv_address -from tinygrad.device import Buffer, BufferSpec -from tinygrad.runtime.support.hcq import HCQCompiled, HCQBuffer -from tinygrad.runtime.autogen import libc -from tinygrad.engine.realize import get_runner, CompiledRunner -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad import Variable - -MOCKGPU = getenv("MOCKGPU") - -@unittest.skipUnless(issubclass(type(Device[Device.DEFAULT]), HCQCompiled), "HCQ device required to run") -class TestHCQ(unittest.TestCase): - @classmethod - def setUpClass(self): - TestHCQ.d0 = Device[Device.DEFAULT] - TestHCQ.a = Tensor([0.,1.], device=Device.DEFAULT).realize() - TestHCQ.b = self.a + 1 - si = self.b.schedule()[-1] - - TestHCQ.runner = get_runner(TestHCQ.d0.device, si.ast) - TestHCQ.b.uop.buffer.allocate() - - TestHCQ.kernargs_ba_ptr = TestHCQ.runner._prg.fill_kernargs([TestHCQ.b.uop.buffer._buf, TestHCQ.a.uop.buffer._buf]) - TestHCQ.kernargs_ab_ptr = TestHCQ.runner._prg.fill_kernargs([TestHCQ.a.uop.buffer._buf, TestHCQ.b.uop.buffer._buf]) - - def setUp(self): - TestHCQ.d0.synchronize() - TestHCQ.a.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - TestHCQ.b.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 0)))) - TestHCQ.d0.synchronize() # wait for copyins to complete - - # Test signals - def test_signal(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - with self.subTest(name=str(queue_type)): - queue_type().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - def test_signal_update(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) - virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) - - with self.subTest(name=str(queue_type)): - q = queue_type().signal(virt_signal, virt_val) - - var_vals = {virt_signal.base_buf.va_addr: TestHCQ.d0.timeline_signal.base_buf.va_addr, virt_val: TestHCQ.d0.timeline_value} - q.submit(TestHCQ.d0, var_vals) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - var_vals = {virt_signal.base_buf.va_addr: TestHCQ.d0.timeline_signal.base_buf.va_addr, virt_val: TestHCQ.d0.timeline_value} - q.submit(TestHCQ.d0, var_vals) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - # Test wait - def test_wait(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - with self.subTest(name=str(queue_type)): - fake_signal = TestHCQ.d0.signal_t() - fake_signal.value = 1 - queue_type().wait(fake_signal, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - @unittest.skipIf(MOCKGPU, "Can't handle async update on MOCKGPU for now") - def test_wait_late_set(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - with self.subTest(name=str(queue_type)): - fake_signal = TestHCQ.d0.signal_t() - queue_type().wait(fake_signal, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - with self.assertRaises(RuntimeError): - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value, timeout=500) - - fake_signal.value = 1 - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - - TestHCQ.d0.timeline_value += 1 - - def test_wait_update(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - with self.subTest(name=str(queue_type)): - virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) - virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) - - fake_signal = TestHCQ.d0.signal_t() - q = queue_type().wait(virt_signal, virt_val).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - - fake_signal.value = 0x30 - - q.submit(TestHCQ.d0, {virt_signal.base_buf.va_addr: fake_signal.base_buf.va_addr, virt_val: fake_signal.value}) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - # Test exec - def test_exec_one_kernel(self): - TestHCQ.d0.hw_compute_queue_t().exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - - def test_exec_2_kernels_100_times(self): - virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) - - q = TestHCQ.d0.hw_compute_queue_t() - q.wait(TestHCQ.d0.timeline_signal, virt_val - 1) \ - .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ - .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ab_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ - .signal(TestHCQ.d0.timeline_signal, virt_val) - - for _ in range(100): - q.submit(TestHCQ.d0, {virt_val: TestHCQ.d0.timeline_value}) - TestHCQ.d0.timeline_value += 1 - - val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] - assert val == 200.0, f"got val {val}" - - def test_exec_update(self): - sint_global = (Variable("sint_global", 0, 0xffffffff, dtypes.uint32),) + tuple(TestHCQ.runner.p.global_size[1:]) - sint_local = (Variable("sint_local", 0, 0xffffffff, dtypes.uint32),) + tuple(TestHCQ.runner.p.local_size[1:]) - - q = TestHCQ.d0.hw_compute_queue_t() - q.exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, sint_global, sint_local) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - - q.submit(TestHCQ.d0, {sint_global[0]: 1, sint_local[0]: 1}) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] - assert val == 1.0, f"got val {val}" - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 0.0, f"got val {val}, should not be updated" - - def test_exec_update_fuzz(self): - virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) - virt_local = [Variable(f"local_{i}", 0, 0xffffffff, dtypes.uint32) for i in range(3)] - - a = Tensor.randint((3, 3, 3), dtype=dtypes.int, device=Device.DEFAULT).realize() - b = a + 1 - si = b.schedule()[-1] - k = Kernel(si.ast, opts=TestHCQ.d0.renderer) - for i in range(3): k.apply_opt(Opt(op=OptOps.LOCAL, axis=0, arg=3)) - - runner = CompiledRunner(k.to_program()) - - zb = Buffer(Device.DEFAULT, 3 * 3 * 3, dtypes.int, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() - zt = Buffer(Device.DEFAULT, 3 * 3 * 3, dtypes.int, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() - ctypes.memset(zb._buf.va_addr, 0, zb.nbytes) - kernargs = runner._prg.fill_kernargs([zt._buf, zb._buf]) - - q = TestHCQ.d0.hw_compute_queue_t() - q.memory_barrier() \ - .exec(runner._prg, kernargs, (1,1,1), virt_local) \ - .signal(TestHCQ.d0.timeline_signal, virt_val) - - for x in range(1, 4): - for y in range(1, 4): - for z in range(1, 4): - ctypes.memset(zt._buf.va_addr, 0, zb.nbytes) - - q.submit(TestHCQ.d0, {virt_val: TestHCQ.d0.timeline_value, virt_local[0]: x, virt_local[1]: y, virt_local[2]: z}) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - res_sum = sum(x for x in zt.as_buffer().cast("I")) - assert x * y * z == res_sum, f"want {x * y * z}, got {res_sum}" - - # Test copy - def test_copy(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 1.0, f"got val {val}" - - def test_copy_long(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - sz = 64 << 20 - buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - ctypes.memset(buf2._buf.va_addr, 1, sz) - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf2._buf.va_addr, sz) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - mv_buf1 = buf1.as_buffer().cast('Q') - assert libc.memcmp(mv_address(mv_buf1), buf2._buf.va_addr, sz) == 0 - - @unittest.skipIf(CI, "skip in CI") - def test_copy_64bit(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - for sz in [(1 << 32) - 1, (1 << 32), (1 << 32) + 1, (5 << 30), (6 << 30) - 0x4642ee1]: - buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - - ctypes.memset(buf2._buf.va_addr, 0x3e, sz) - buf2_q_view = buf2._buf.cpu_view().view(fmt='Q') - for i in range(0, sz//8, 0x1000): - for j in range(32): buf2_q_view[min(max(i + j - 16, 0), (sz // 8) - 1)] = random.randint(0, 0xffffffffffffffff) - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf2._buf.va_addr, sz) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - mv_buf1 = buf1.as_buffer() - assert libc.memcmp(mv_address(mv_buf1), buf2._buf.va_addr, sz) == 0 - - def test_update_copy(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - virt_src_addr = Variable("virt_src_addr", 0, 0xffffffffffffffff, dtypes.uint64) - virt_dest_addr = Variable("virt_dest_addr", 0, 0xffffffffffffffff, dtypes.uint64) - - q = TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(virt_dest_addr, virt_src_addr, 8) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - - q.submit(TestHCQ.d0, {virt_src_addr: TestHCQ.a.uop.buffer._buf.va_addr, virt_dest_addr: TestHCQ.b.uop.buffer._buf.va_addr}) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] - assert val == 1.0, f"got val {val}" - - def test_update_copy_long(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - virt_src_addr = Variable("virt_src_addr", 0, 0xffffffffffffffff, dtypes.uint64) - virt_dest_addr = Variable("virt_dest_addr", 0, 0xffffffffffffffff, dtypes.uint64) - - sz = 64 << 20 - buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - ctypes.memset(buf2._buf.va_addr, 1, sz) - - q = TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(virt_dest_addr, virt_src_addr, sz) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - - q.submit(TestHCQ.d0, {virt_src_addr: buf2._buf.va_addr, virt_dest_addr: buf1._buf.va_addr}) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - mv_buf1 = buf1.as_buffer().cast('Q') - for i in range(sz//8): assert mv_buf1[i] == 0x0101010101010101, f"offset {i*8} differs, not all copied, got {hex(mv_buf1[i])}" - - # Test bind api - def test_bind(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) - virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) - - with self.subTest(name=str(queue_type)): - fake_signal = TestHCQ.d0.signal_t() - q = queue_type().wait(virt_signal, virt_val).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) - q.bind(TestHCQ.d0) - - fake_signal.value = 0x30 - - q.submit(TestHCQ.d0, {virt_signal.base_buf.va_addr: fake_signal.base_buf.va_addr, virt_val: fake_signal.value}) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - # Test multidevice - def test_multidevice_signal_wait(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - try: d1 = Device[f"{Device.DEFAULT}:1"] - except Exception: self.skipTest("no multidevice, test skipped") - - TestHCQ.d0.hw_copy_queue_t().signal(sig:=TestHCQ.d0.signal_t(value=0), value=0xfff) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - d1.hw_copy_queue_t().wait(sig, value=0xfff) \ - .signal(d1.timeline_signal, d1.timeline_value).submit(d1) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - d1.timeline_signal.wait(d1.timeline_value) - d1.timeline_value += 1 - - # Test profile api - def test_speed_exec_time(self): - sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() - TestHCQ.d0.hw_compute_queue_t().timestamp(sig_st) \ - .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ - .timestamp(sig_en) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - et = float(sig_en.timestamp - sig_st.timestamp) - - print(f"exec kernel time: {et:.2f} us") - assert 0.1 <= et <= (15000 if MOCKGPU else 100) - - def test_speed_copy_bandwidth(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - # THEORY: the bandwidth is low here because it's only using one SDMA queue. I suspect it's more stable like this at least. - SZ = 200_000_000 - a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - b = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - - sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() - TestHCQ.d0.hw_copy_queue_t().timestamp(sig_st) \ - .copy(a._buf.va_addr, b._buf.va_addr, SZ) \ - .timestamp(sig_en) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - et = float(sig_en.timestamp - sig_st.timestamp) - et_ms = et / 1e3 - - gb_s = ((SZ / 1e9) / et_ms) * 1e3 - print(f"same device copy: {et_ms:.2f} ms, {gb_s:.2f} GB/s") - assert (0.2 if MOCKGPU else 10) <= gb_s <= 1000 - - def test_speed_cross_device_copy_bandwidth(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - try: _ = Device[f"{Device.DEFAULT}:1"] - except Exception: self.skipTest("no multidevice, test skipped") - - SZ = 200_000_000 - b = Buffer(f"{Device.DEFAULT}:1", SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() - TestHCQ.d0.allocator.map(b._buf) - - sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() - TestHCQ.d0.hw_copy_queue_t().timestamp(sig_st) \ - .copy(a._buf.va_addr, b._buf.va_addr, SZ) \ - .timestamp(sig_en) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - et = float(sig_en.timestamp - sig_st.timestamp) - et_ms = et / 1e3 - - gb_s = ((SZ / 1e9) / et_ms) * 1e3 - print(f"cross device copy: {et_ms:.2f} ms, {gb_s:.2f} GB/s") - assert (0.2 if MOCKGPU else 2) <= gb_s <= 100 - - def test_timeline_signal_rollover(self): - for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: - if queue_type is None: continue - - with self.subTest(name=str(queue_type)): - TestHCQ.d0.timeline_value = (1 << 32) - 20 # close value to reset - queue_type().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value - 1) - - for _ in range(40): - queue_type().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_value += 1 - TestHCQ.d0.synchronize() - - def test_small_copies_from_host_buf(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - - for i in range(256): - ctypes.memset(buf2._buf.va_addr, i, 1) - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf2._buf.va_addr, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - assert buf1.as_buffer()[0] == i - - def test_small_copies_from_host_buf_intercopy(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - - for i in range(256): - ctypes.memset(buf3._buf.va_addr, i, 1) - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ - .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - assert buf2.as_buffer()[0] == i - - def test_small_copies_from_host_buf_transfer(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - try: _ = Device[f"{Device.DEFAULT}:1"] - except Exception: self.skipTest("no multidevice, test skipped") - - buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(f"{Device.DEFAULT}:1", 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() - TestHCQ.d0.allocator.map(buf2._buf) - - for i in range(256): - ctypes.memset(buf3._buf.va_addr, i, 1) - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ - .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - assert buf2.as_buffer()[0] == i - - def test_memory_barrier(self): - a = Tensor([0, 1], device=Device.DEFAULT, dtype=dtypes.int8).realize() - b = a + 1 - runner = get_runner(TestHCQ.d0.device, b.schedule()[-1].ast) - - buf1 = Buffer(Device.DEFAULT, 2, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, 2, dtypes.int8, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() - - kernargs_ptr = runner._prg.fill_kernargs([buf1._buf, buf2._buf]) - - for i in range(255): - ctypes.memset(buf2._buf.va_addr, i, 2) - - # Need memory_barrier after direct write to vram - TestHCQ.d0.hw_compute_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .memory_barrier() \ - .exec(runner._prg, kernargs_ptr, runner.p.global_size, runner.p.local_size) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - assert buf1.as_buffer()[0] == (i + 1), f"has {buf1.as_buffer()[0]}, need {i + 1}" - - def test_memory_barrier_before_copy(self): - if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") - - buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() - buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() - - for i in range(256): - ctypes.memset(buf3._buf.va_addr, i, 1) - - # Need memory_barrier after direct write to vram - TestHCQ.d0.hw_compute_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .memory_barrier() \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_value += 1 - - TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ - .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ - .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ - .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) - TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) - TestHCQ.d0.timeline_value += 1 - - assert buf2.as_buffer()[0] == i - - @unittest.skipUnless(MOCKGPU, "Emulate this on MOCKGPU to check the path in CI") - def test_on_device_hang(self): - if not hasattr(self.d0, 'on_device_hang'): self.skipTest("device does not have on_device_hang") - - os.environ["MOCKGPU_EMU_FAULTADDR"] = "0xDEADBEE1" - - # Check api calls - with self.assertRaises(RuntimeError) as ctx: - self.d0.on_device_hang() - - assert "0xDEADBEE1" in str(ctx.exception) - os.environ.pop("MOCKGPU_EMU_FAULTADDR") - - def test_multidevice(self): - try: amd_dev = Device["AMD"] - except Exception: self.skipTest("no AMD device, test skipped") - - try: nv_dev = Device["NV"] - except Exception: self.skipTest("no NV device, test skipped") - - x = amd_dev.signal_t() - y = nv_dev.signal_t() - assert type(x) is amd_dev.signal_t - assert type(y) is nv_dev.signal_t - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_hcq_iface.py b/tinygrad/test/test_hcq_iface.py deleted file mode 100644 index bf32bf63..00000000 --- a/tinygrad/test/test_hcq_iface.py +++ /dev/null @@ -1,105 +0,0 @@ -import unittest, array, time -from tinygrad.helpers import mv_address -from tinygrad.runtime.support.hcq import MMIOInterface -from tinygrad.runtime.support.usb import USBMMIOInterface -from test.mockgpu.usb import MockUSB - -class TestHCQIface(unittest.TestCase): - def setUp(self): - self.size = 4 << 10 - self.buffer = bytearray(self.size) - self.mv = memoryview(self.buffer).cast('I') - self.mmio = MMIOInterface(mv_address(self.mv), self.size, fmt='I') - - def test_getitem_setitem(self): - self.mmio[1] = 0xdeadbeef - self.assertEqual(self.mmio[1], 0xdeadbeef) - values = array.array('I', [10, 20, 30, 40]) - self.mmio[2:6] = values - read_slice = self.mmio[2:6] - # self.assertIsInstance(read_slice, array.array) - self.assertEqual(read_slice, values.tolist()) - self.assertEqual(self.mv[2:6].tolist(), values.tolist()) - - def test_view(self): - full = self.mmio.view() - self.assertEqual(len(full), len(self.mmio)) - self.mmio[0] = 0x12345678 - self.assertEqual(full[0], 0x12345678) - - # offset-only view - self.mmio[1] = 0xdeadbeef - off = self.mmio.view(offset=4) - self.assertEqual(off[0], 0xdeadbeef) - - # offset + size view: write into sub-view and confirm underlying buffer - values = array.array('I', [11, 22, 33]) - sub = self.mmio.view(offset=8, size=12) - sub[:] = values - self.assertEqual(sub[:], values.tolist()) - self.assertEqual(self.mv[2:5].tolist(), values.tolist()) - - def test_speed(self): - start = time.perf_counter() - for i in range(10000): - self.mmio[3:100] = array.array('I', [i] * 97) - _ = self.mmio[3:100] - end = time.perf_counter() - - mvstart = time.perf_counter() - for i in range(10000): - self.mv[3:100] = array.array('I', [i] * 97) - _ = self.mv[3:100].tolist() - mvend = time.perf_counter() - print(f"speed: hcq {end - start:.6f}s vs plain mv {mvend - mvstart:.6f}s") - -class TestUSBMMIOInterface(unittest.TestCase): - def setUp(self): - self.size = 256 - self.buffer = bytearray(self.size) - self.usb = MockUSB(self.buffer) - self.mmio = USBMMIOInterface(self.usb, 0, self.size, fmt='B', pcimem=False) - - def test_getitem_setitem_byte(self): - self.mmio[1] = 0xAB - self.assertEqual(self.mmio[1], 0xAB) - self.assertEqual(self.usb.mem[1], 0xAB) - - def test_slice_getitem_setitem(self): - values = [1, 2, 3, 4] - self.mmio[10:14] = values - raw = self.mmio[10:14] - self.assertIsInstance(raw, bytes) - self.assertEqual(list(raw), values) - self.assertEqual(list(self.usb.mem[10:14]), values) - - def test_view(self): - self.mmio[0] = 5 - view = self.mmio.view(offset=1, size=3) - self.assertEqual(view[0], self.usb.mem[1]) - view[:] = [7, 8, 9] - self.assertEqual(list(self.usb.mem[1:4]), [7, 8, 9]) - full_view = self.mmio.view() - self.assertEqual(len(full_view), len(self.mmio)) - self.mmio[2] = 0xFE - self.assertEqual(full_view[2], 0xFE) - - def test_pcimem_byte(self): - usb2 = MockUSB(bytearray(self.size)) - mmio_pci = USBMMIOInterface(usb2, 0, self.size, fmt='B', pcimem=True) - mmio_pci[3] = 0x11 - self.assertEqual(mmio_pci[3], 0x11) - self.assertEqual(usb2.mem[3], 0x11) - - def test_pcimem_slice(self): - usb3 = MockUSB(bytearray(self.size)) - mmio_pci = USBMMIOInterface(usb3, 0, self.size, fmt='B', pcimem=True) - values = [2, 3, 4] - mmio_pci[4:7] = values - raw = mmio_pci[4:7] - self.assertIsInstance(raw, bytes) - self.assertEqual(list(raw), values) - self.assertEqual([mmio_pci[i] for i in range(4, 7)], values) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_image_dtype.py b/tinygrad/test/test_image_dtype.py deleted file mode 100644 index 08d2c04c..00000000 --- a/tinygrad/test/test_image_dtype.py +++ /dev/null @@ -1,179 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Device, dtypes, Tensor, Context -from tinygrad.device import LRUAllocator, is_dtype_supported -from tinygrad.dtype import ImageDType -from tinygrad.engine.realize import lower_schedule -from tinygrad.helpers import prod, unwrap -from test.helpers import REAL_DEV - -IMAGE_SUPPORTED_DEVICES = ("QCOM", "GPU") - -@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") -class TestImageCopy(unittest.TestCase): - def test_image_copyout_1x1(self, img_type=dtypes.imagef): - it = Tensor.arange(4).cast(img_type((1,1,4))).realize() - buf = it.uop.buffer - out = buf.as_buffer() - np.testing.assert_equal(out.cast(it.dtype.fmt).tolist(), np.arange(4)) - - @unittest.skipUnless(is_dtype_supported(dtypes.half, device="PYTHON"), "need half") - def test_imageh_copyout_1x1(self): self.test_image_copyout_1x1(img_type=dtypes.imageh) - - def test_image_numpy_1x1(self, img_type=dtypes.imagef): - it = Tensor.arange(4).cast(img_type((1,1,4))).realize() - np.testing.assert_equal(it.numpy(), np.arange(4)) - def test_imageh_numpy_1x1(self): self.test_image_numpy_1x1(img_type=dtypes.imageh) - - def test_image_copyout_2x3(self): - it = Tensor.arange(2*3*4).cast(dtypes.imagef((2,3,4))).realize() - buf = it.uop.buffer - out = buf.as_buffer() - np.testing.assert_equal(out.cast('f').tolist(), np.arange(2*3*4)) - - def test_image_roundtrip(self): - sz = (4,2,4) - it = Tensor.rand(prod(sz)).cast(dtypes.imagef(sz)).realize() - buf = it.uop.buffer - out = buf.as_buffer() - - it2 = Tensor.rand(prod(sz)).cast(dtypes.imagef(sz)).realize() - buf2 = it2.uop.buffer - buf2.copyin(out) - - assert (it == it2).sum().item() == prod(sz) - -@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") -class TestImageDType(unittest.TestCase): - def test_image_and_back(self): - data = Tensor.randn(9*27*4).realize() - tst = data.numpy() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - assert isinstance(it.uop.base.realized.dtype, ImageDType) - np.testing.assert_equal(tst, it.numpy()) - - @unittest.expectedFailure # this isn't supported anymore, CAST to ImageDType stays ImageDType - def test_image_cast_and_back_collapses(self): - data = Tensor.randn(9*27*4).realize() - tst = data.numpy() - it = data.cast(dtypes.imagef((9,27,4))).realize() - # the underlying UOp is identical - self.assertIs(it.uop.base.realized, data.uop.base.realized) - np.testing.assert_equal(tst, it.numpy()) - - def test_image_and_back_wrong_shape(self): - data = Tensor.randn(9*27*4).realize() - tst = data.numpy() - it = data.cast(dtypes.imagef((9,12,4))).realize() - assert not isinstance(it.uop.base.realized.dtype, ImageDType) - np.testing.assert_equal(tst, it.numpy()) - - def test_shrink_load_float(self): - it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).realize() - imgv = it.numpy() - np.testing.assert_equal(imgv[0:2], it[0:2].numpy()) - - def test_mul_stays_image(self): - # NOTE: contiguous is needed otherwise this folds - it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).contiguous().realize() - out = (it*2).realize() - assert isinstance(out.uop.base.realized.dtype, ImageDType) - - def test_sum(self): - it = Tensor.rand(8).cast(dtypes.imagef((1,2,4))).realize() - itn = it.numpy() - np.testing.assert_allclose(np.sum(itn), it.sum().numpy(), rtol=1e-6) - - def test_shrink_max(self): - it = Tensor.randn(8).cast(dtypes.imagef((1,2,4))).realize() - imgv = it.numpy() - np.testing.assert_equal(np.maximum(imgv[0:3], 0), it[0:3].relu().numpy()) - - def test_shrink_to_float(self): - it = Tensor.randn(4, 4).cast(dtypes.imagef((1,4,4))).realize() - imgv = it.numpy() - np.testing.assert_equal(np.maximum(imgv[:, 0], 0), it[:, 0].relu().numpy()) - - @unittest.skipUnless(isinstance(Device.default.allocator, LRUAllocator), "Requires LRU") - def test_lru_alloc(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).realize() - b1 = it.uop.base.realized._buf - del it - it = data.cast(dtypes.imagef((9,27,4))).realize() - assert it.uop.base.realized._buf == b1 - - def test_no_lru_alloc(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - b1 = it.uop.base.realized._buf - del it - it = data.cast(dtypes.imagef((10,27,4))).contiguous().realize() - assert it.uop.base.realized._buf != b1 - - def test_no_lru_alloc_dtype(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - b1 = it.uop.base.realized._buf - del it - it = data.cast(dtypes.imageh((9,27,4))).realize() - assert it.uop.base.realized._buf != b1 - - # issue caused by: don't realize image to image casts. this is part of a larger problem - #@unittest.expectedFailure - # update: passing after tensor_map - def test_lil_model(self): - with Context(IMAGE=2): - x = Tensor.zeros(1, 1) - w1 = Tensor.zeros(1, 8, requires_grad=True) - w2 = Tensor.zeros(8, 2) - loss = x.image_dot(w1).image_dot(w2).float().max() - loss.backward() - sched = unwrap(w1.grad).schedule() - for s,(_,ei) in zip(sched, lower_schedule(sched[:])): - ei.run() - if s.bufs[0].dtype == dtypes.float: - lst = s.bufs[0].as_buffer().cast("f").tolist() - print(lst) - assert not np.any(np.isnan(lst)) - # NOTE: the w1 grad must realize to a seperate kernel - assert w1.grad.uop.is_realized, f"never realized {w1.grad}" - self.assertEqual(w1.grad.uop.base.buffer.dtype, dtypes.float32) - self.assertEqual(len(sched), 10) - -@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") -class TestImageRealization(unittest.TestCase): - def test_image_dtype_expand(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) - it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous().realize() - self.assertEqual(it_expanded.dtype, dtypes.float32) - - def test_image_dtype_expand_and_back(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) - it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)) - it2 = it_expanded.sum(3).realize() - self.assertEqual(it2.dtype, dtypes.imagef((9,27,4))) - - def test_image_alu_children(self): - data = Tensor.randn(9*27*4).realize() - it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() - self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) - it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous() - alu1 = it_expanded+1 - alu2 = it_expanded.sum(3) - it_expanded.realize() - # NOTE: the parent becomes float, but the alu child will stay image until its output cannot fit the image - self.assertEqual(alu1.dtype, dtypes.imagef((9,27,4))) - alu1.realize() - self.assertEqual(alu1.dtype, dtypes.float32) - # alu2 is back in image because it fits the dtype again - self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4))) - alu2.realize() - self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4))) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_interop.py b/tinygrad/test/test_interop.py deleted file mode 100644 index dafe5431..00000000 --- a/tinygrad/test/test_interop.py +++ /dev/null @@ -1,52 +0,0 @@ -#!/usr/bin/env python -import unittest -import torch -import numpy as np - -from tinygrad.helpers import getenv, CI -from tinygrad.tensor import Tensor -from tinygrad.device import Device -from tinygrad.dtype import _from_torch_dtype, _to_torch_dtype - -MOCKGPU = getenv("MOCKGPU") - -@unittest.skipIf(Device.DEFAULT not in ["METAL", "CUDA"] or MOCKGPU, f"no support on {Device.DEFAULT}") -class TestInterop(unittest.TestCase): - def setUp(self): - if Device.DEFAULT == "CUDA": self.torch_device = "cuda" - elif Device.DEFAULT == "METAL": self.torch_device = "mps" - - def test_torch_interop(self): - inp = torch.rand(2, 2, 3, device=torch.device(self.torch_device)) - - if self.torch_device == "mps": torch.mps.synchronize() - else: torch.cuda.synchronize() - - tg_data = Tensor.from_blob(inp.data_ptr(), inp.shape, dtype=_from_torch_dtype(inp.dtype)) - - tg_out = tg_data[:, :, 0] * 0.2989 + tg_data[:, :, 1] * 0.5870 + tg_data[:, :, 2] * 0.1140 - tg_res = tg_out.numpy() - - if self.torch_device == "mps" and CI: - # MPS backend out of memory: https://discuss.pytorch.org/t/mps-back-end-out-of-memory-on-github-action/189773 - # Calculate expected value on cpu. - inp = inp.cpu() - torch_out = inp[:, :, 0] * 0.2989 + inp[:, :, 1] * 0.5870 + inp[:, :, 2] * 0.1140 - - np.testing.assert_allclose(tg_res, torch_out.cpu().numpy(), atol=1e-5, rtol=1e-5) - - def test_torch_interop_write(self): - tg_data = Tensor.randn((4, 4), device=Device.DEFAULT) - - out = torch.empty(4, 4, device=torch.device(self.torch_device), dtype=_to_torch_dtype(tg_data.dtype)) - tg_out = Tensor.from_blob(out.data_ptr(), out.shape, dtype=_from_torch_dtype(out.dtype)) - - tg_out.assign(tg_data).realize() - Device[Device.DEFAULT].synchronize() - - torch_out_np = out.cpu().numpy() - - np.testing.assert_allclose(tg_data.numpy(), torch_out_np, atol=1e-5, rtol=1e-5) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_jit.py b/tinygrad/test/test_jit.py deleted file mode 100644 index 1b30ffc3..00000000 --- a/tinygrad/test/test_jit.py +++ /dev/null @@ -1,673 +0,0 @@ -#!/usr/bin/env python -import unittest, functools -import numpy as np - -from hypothesis import given, settings, strategies as strat -from test.helpers import assert_jit_cache_len, not_support_multi_device, REAL_DEV -from tinygrad.tensor import Tensor -from tinygrad.engine.jit import TinyJit -from tinygrad.device import Device -from tinygrad.helpers import Context, JIT, GlobalCounters -from tinygrad.dtype import dtypes -from extra.models.unet import ResBlock - -def _simple_test(add, extract=lambda x: x, N=10): - for _ in range(5): - a = Tensor.randn(N, N) - b = Tensor.randn(N, N) - c = add(a, b) - np.testing.assert_allclose(extract(c).numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(add, 1) - -class TestJit(unittest.TestCase): - - @settings(deadline=2e4) - @unittest.skipUnless(REAL_DEV in ["LLVM", "CPU"], f"no support on {REAL_DEV}") - @given(strat.sampled_from([Tensor.exp2, Tensor.log2, Tensor.sin])) - def test_approx_jit_timeout(self, op): - with Context(TRANSCENDENTAL=2): - model = [ResBlock(16, 24, 16) for _ in range(4)] - @TinyJit - def fw_approx(t, t2): - for l in model: t = l(t, t2) - return op(t).realize() - fw_approx(Tensor.empty(4, 16, 8, 8), Tensor.empty(1, 24)) - - def test_simple_jit(self): - @TinyJit - def add(a, b): return (a+b).realize() - _simple_test(add) - - def test_simple_jit_reset(self): - @TinyJit - def add(a, b): return (a+b).realize() - _simple_test(add) - add.reset() - _simple_test(add, N=20) - - def test_simple_jit_norealize(self): - @TinyJit - def add(a, b): return (a+b) - _simple_test(add) - - def test_simple_jit_norealize_list(self): - @TinyJit - def add(a, b): return [a+b] - _simple_test(add, extract=lambda x: x[0]) - - def test_simple_jit_norealize_dict(self): - @TinyJit - def add(a, b): return {"billy": a+b} - _simple_test(add, extract=lambda x: x["billy"]) - - def test_jit_multiple_outputs(self): - @TinyJit - def f(a, b): return (a+b).realize(), (a-b).realize(), (a*b).realize() - for _ in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - c, d, e = f(a, b) - np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(d.numpy(), a.numpy()-b.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(e.numpy(), a.numpy()*b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(f, 3) - - def test_nothing_jitted(self): - @TinyJit - def add(a, b): return None - with self.assertRaises(AssertionError): - for _ in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - add(a, b) - - def test_jit_zero_does_not_jit(self): - @TinyJit - def add(a, b): return (a+b).realize() - with Context(JIT=0): - for i in range(5): - a = Tensor([i]) - b = Tensor([i]) - c = add(a, b) - np.testing.assert_allclose(c.numpy(), 2*i) - assert_jit_cache_len(add, 0) - - def test_jit_not_capturing(self): - @TinyJit - def add(a, b): - Tensor.zeros(4, 4).contiguous().realize() # no-op kernel is captured - return (a+b).realize() - for i in range(5): - a = Tensor([i]) - b = Tensor([i]) - c = add(a, b) - np.testing.assert_allclose(c.numpy(), 2*i) - assert_jit_cache_len(add, 2) - - @TinyJit - def add2(a, b): - with Context(CAPTURING=0): # not captured - Tensor.zeros(4, 4).contiguous().realize() - return (a+b).realize() - for i in range(5): - a = Tensor([i]) - b = Tensor([i]) - c = add2(a, b) - np.testing.assert_allclose(c.numpy(), 2*i) - assert_jit_cache_len(add2, 1) - - def test_jit_shape_mismatch(self): - @TinyJit - def add(a, b): return (a+b).realize() - for _ in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - add(a, b) - bad = Tensor.randn(20, 20) - with self.assertRaises(AssertionError): - add(a, bad) - - def test_jit_shape_views_mismatch(self): - @TinyJit - def add(a): return (a+1).realize() - with self.assertRaises(AssertionError): - for i in range(1,5): - # a has an offset that the kernel doesn't know about - a = Tensor.randn(10, 10).realize()[:, i:i+2] - add(a) - - def test_jit_duplicate_fail(self): - # the jit doesn't support duplicate arguments - @TinyJit - def add(a, b): return (a+b).realize() - a = Tensor.randn(10, 10) - with self.assertRaises(AssertionError): - add(a, a) - - def test_jit_assign(self, dtype=dtypes.float32): - @TinyJit - def add(a): - a += 1 - a.realize() - a = Tensor.zeros(1, dtype=dtype).contiguous().realize() - for _ in range(5): add(a) - self.assertEqual(a.item(), 5) - - def test_jit_assign_int8(self): self.test_jit_assign(dtypes.int8) - - def test_kwargs_jit(self): - @TinyJit - def add_kwargs(first, second): return (first+second).realize() - for _ in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - c = add_kwargs(first=a, second=b) - np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(add_kwargs, 1) - - def test_reorder_kwargs_jit(self): - @TinyJit - def add_kwargs(first, second): return (first/second).realize() - for _ in range(2): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - c = add_kwargs(second=b, first=a) - np.testing.assert_allclose(c.numpy(), a.numpy()/b.numpy(), atol=1e-4, rtol=1e-5) - for _ in range(2): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - c = add_kwargs(first=a, second=b) - np.testing.assert_allclose(c.numpy(), a.numpy()/b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(add_kwargs, 1) - - def test_array_jit(self): - @TinyJit - def add_array(a, arr): return (a+arr[0]).realize() - for i in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - a.realize(), b.realize() - c = add_array(a, [b]) - if i >= 2: - # should fail once jitted since jit can't handle arrays - np.testing.assert_allclose(np.any(np.not_equal(c.numpy(),a.numpy()+b.numpy())), True, atol=1e-4, rtol=1e-5) - else: - np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(add_array, 1) - - def test_jit_copyin(self): - @TinyJit - def f(a): - return a + Tensor([1,2,3]) - for _ in range(5): - b = Tensor.randn(3) - c = f(b) - np.testing.assert_allclose(c.numpy(), b.numpy()+[1,2,3], atol=1e-4, rtol=1e-5) - - def test_method_jit(self): - class Fun: - def __init__(self): - self.a = Tensor.randn(10, 10) - @TinyJit - def __call__(self, b:Tensor) -> Tensor: - return (self.a+b).realize() - fun = Fun() - for _ in range(5): - b = Tensor.randn(10, 10) - c = fun(b) - np.testing.assert_allclose(c.numpy(), fun.a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(fun.__call__.func.__self__, 1) - - def test_jit_size1_input(self): - @TinyJit - def f(a, b): return (a+b).realize() - a = Tensor([1, 2, 3]) - for i in range(5): - np.testing.assert_allclose(f(a, Tensor([i])).numpy(), (a+i).numpy(), atol=1e-4, rtol=1e-5) - assert_jit_cache_len(f, 1) - - def test_jit_output_non_tensor_fail(self): - @TinyJit - def f(a, b, i): return (a+b).realize(), i - output1, output2 = [], [] - expect1, expect2 = [], [] - for i in range(5): - a = Tensor.randn(10, 10) - b = Tensor.randn(10, 10) - o1, o2 = f(a, b, i) - output1.append(o1.numpy().copy()) - output2.append(o2) - expect1.append(a.numpy().copy()+b.numpy().copy()) - expect2.append(i) - np.testing.assert_allclose(output1, expect1, atol=1e-4, rtol=1e-5) - # the jit only works with Tensor outputs - assert output2 != expect2 - assert_jit_cache_len(f, 1) - - def test_jit_random_regen(self): - def f(a, b): - rn = Tensor.randn(*a.shape) - return ((a+b)*rn).realize() - a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed - b = Tensor.randn(10, 10).realize() - - Tensor.manual_seed(1234) - jf = TinyJit(f) - res = set() - for _ in range(5): - o1 = jf(a, b) - res.add(o1.numpy()[0][0]) - assert len(res) == 5, "All values should be different, rand works in jit." - - Tensor.manual_seed(1234) - jf2 = TinyJit(f) - res2 = set() - for _ in range(5): - o1 = jf2(a, b) - res2.add(o1.numpy()[0][0]) - assert len(res2) == 5, "All values should be different, rand works in jit." - assert res == res2, "Jit rand is not reproducible with the same seed" - - Tensor.manual_seed(3421) - jf3 = TinyJit(f) - res3 = set() - for _ in range(5): - o1 = jf3(a, b) - res3.add(o1.numpy()[0][0]) - assert len(res3) == 5, "All values should be different, rand works in jit." - assert res3 != res2, "Jit rand is diff with diff seeds" - - @unittest.expectedFailure # TODO: fix - def test_jit_v_nojit_random_regen(self): - def f(a, b): - rn = Tensor.randn(*a.shape) - rn = rn * a - rn2 = Tensor.randn(*a.shape) - rn2 = rn2 * b - rn = rn + rn2 - rn2 = rn2 + Tensor.randn(*a.shape) - return ((a+b)*rn).realize(), ((a+b)*rn2).realize() - Tensor.manual_seed(0) - a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed - b = Tensor.randn(10, 10).realize() - - Tensor.manual_seed(1234) - without_jit = set() - for _ in range(5): - o1, o2 = f(a, b) - without_jit.add(o1.numpy()[0][0]) - without_jit.add(o2.numpy()[0][0]) - assert len(without_jit) == 10, "All values should be different." - - Tensor.manual_seed(1234) - jf = TinyJit(f) - with_jit = set() - for _ in range(5): - o1, o2 = jf(a, b) - with_jit.add(o1.numpy()[0][0]) - with_jit.add(o2.numpy()[0][0]) - assert len(with_jit) == 10, "All values should be different." - assert with_jit == without_jit, "Jit rand produced different values from no jit." - - def test_jit_multiple_random_regen(self): - def f(a, b): - rn = Tensor.randn(*a.shape) - rn = rn * a - rn2 = Tensor.randn(*a.shape) - rn2 = rn2 * b - rn = rn + rn2 - rn2 = rn2 + Tensor.randn(*a.shape) - return ((a+b)*rn).realize(), ((a+b)*rn2).realize() - a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed - b = Tensor.randn(10, 10).realize() - - Tensor.manual_seed(1234) - jf = TinyJit(f) - res = set() - for _ in range(5): - o1, o2 = jf(a, b) - res.add(o1.numpy()[0][0]) - res.add(o2.numpy()[0][0]) - assert len(res) == 10, "All values should be different, rand works in jit." - - Tensor.manual_seed(1234) - jf2 = TinyJit(f) - res2 = set() - for _ in range(5): - o1, o2 = jf2(a, b) - res2.add(o1.numpy()[0][0]) - res2.add(o2.numpy()[0][0]) - assert len(res2) == 10, "All values should be different, rand works in jit." - assert res == res2, "Jit rand is not reproducible with the same seed" - - Tensor.manual_seed(3421) - jf3 = TinyJit(f) - res3 = set() - for _ in range(5): - o1, o2 = jf3(a, b) - res3.add(o1.numpy()[0][0]) - res3.add(o2.numpy()[0][0]) - assert len(res3) == 10, "All values should be different, rand works in jit." - assert res3 != res2, "Jit rand is diff with diff seeds" - - #@unittest.expectedFailure # requires contiguous folding - def test_jit_random_after_unrealized_random(self): - @TinyJit - def f(): return Tensor.rand() - Tensor.manual_seed(1234) - Tensor.rand() - res = [f().numpy() for _ in range(3)] - assert res[1] != res[2] - - def test_jit_realization_and_sampling(self): - w = Tensor.eye(5) - - @TinyJit - def foo (x): return w.dot(x).realize() - - arg = [ - Tensor([1,2,3,4,5]), - Tensor([1,3,3,4,6]), - Tensor([1,2,5,4,7]), - Tensor([0,2,3,1,0]), - ] - - Y = [foo(e).numpy() for e in arg] - - foo(Tensor([7,7,7,7,7])) - want = [[1., 2., 3., 4., 5.], - [1., 3., 3., 4., 6.], - [1., 2., 5., 4., 7.], - [0., 2., 3., 1., 0.]] - np.testing.assert_allclose(want, Y) - - def test_jit_buffer_behavior(self): - @TinyJit - def foo(x) -> Tensor: return x.sum().realize() - - result_1 = foo(Tensor([1] * 2)) - result_2 = foo(Tensor([2] * 2)) - result_3 = foo(Tensor([3] * 2)) - - # expect the buffer to share underlying buffer - np.testing.assert_allclose(result_1.numpy(), [2], atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(result_2.numpy(), [6], atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(result_3.numpy(), [6], atol=1e-4, rtol=1e-5) - - def test_jit_batch_split(self): - if Device[Device.DEFAULT].graph is None or JIT >= 2: raise unittest.SkipTest("only test graphs") - - # Create long jit with 83 kernels. - def f(a, b, c, d, e): - for _ in range(80): - a = (a+b).realize() - y = (a*c).realize() - z = (y*d).realize() - w = (z*e) - return w.realize() - - a = Tensor.randn(10, 10).realize() - b = Tensor.randn(10, 10).realize() - c = Tensor.randn(10, 10).realize() - d = Tensor.randn(10, 10).realize() - e = Tensor.randn(10, 10).realize() - - jf = TinyJit(f) - prev = None - for _ in range(5): - o = jf(a, b, c, d, e).numpy() - if prev is not None: np.testing.assert_allclose(o, prev, atol=1e-4, rtol=1e-5) - prev = o - - graph_t = Device[Device.DEFAULT].graph.func if isinstance(Device[Device.DEFAULT].graph, functools.partial) else Device[Device.DEFAULT].graph - # Checking that 2 graphs are inited. - assert isinstance(jf.jit_cache[0].prg, graph_t) - assert isinstance(jf.jit_cache[1].prg, graph_t) - - def test_jit_const_inputs(self): - @TinyJit - def g(x,y,z): return (x+y+z).realize() - for i in range(5): - np.testing.assert_equal(g(Tensor([i]*3), Tensor.ones(3), Tensor.zeros(3)).numpy(), np.array([i+1]*3)) - - def test_jitted_clone(self): - def f(a): return a.clone().realize() - jf = TinyJit(f) - for _ in range(5): - a = Tensor.randn(10, 10, device=Device.DEFAULT).realize() - ja = jf(a) - np.testing.assert_allclose(a.numpy(), ja.numpy(), atol=1e-4, rtol=1e-5) - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_jitted_transfers(self): - d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" - - def f(a, b): - x = a.to(d1) - y = b.to(d1) - return x.realize(), y.realize() - - jf = TinyJit(f) - for _ in range(5): - a = Tensor.randn(10, 10, device=d0).realize() - b = Tensor.randn(10, 10, device=d0).realize() - xc, yc = jf(a, b) - np.testing.assert_allclose(a.numpy(), xc.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(b.numpy(), yc.numpy(), atol=1e-4, rtol=1e-5) - - def test_jit_several_devs(self): - d0, d1 = f"{Device.DEFAULT}:0", "CPU" - - def f(a, b): - x = a.to(d0).realize() - y = b.to(d0).realize() - return x+y.realize(), x*y.realize() - - jf = TinyJit(f) - for _ in range(5): - a = Tensor.randn(10, 10, device=d1).realize() - b = Tensor.randn(10, 10, device=d1).realize() - zc, wc = jf(a, b) - np.testing.assert_allclose((a.numpy()+b.numpy()), zc.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose((a.numpy()*b.numpy()), wc.numpy(), atol=1e-4, rtol=1e-5) - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_jitted_view(self): - d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" - - def f(a): - x1 = a.sum(axis=(1,)) - x = (x1 + 5).bitcast(dtypes.int32) - y = x.to(d1) - return y.realize() - - jf = TinyJit(f) - for _ in range(5): - a = Tensor.randn(10, 1000, device=d0).realize() - xc = jf(a) - np.testing.assert_allclose((a.numpy().sum(axis=(1,)) + 5).view(np.int32), xc.numpy(), atol=1e-4, rtol=5e-5) - - def test_jit_output_clone(self): - @TinyJit - def f(x:Tensor) -> Tensor: return (x + 1).realize() - - f(Tensor([0.0])) - f(Tensor([0.0])) - - a = f(Tensor([1.0])).clone().realize() - b = f(Tensor([2.0])) - assert abs((a - b).item()) > 0.5 - -@unittest.skip("Pending multioutput implementation #3607") -class TestMultioutputJit(unittest.TestCase): - def _test(self, f): - for _ in range(5): - a, b = Tensor.randn(10, 10), Tensor.randn(10, 10) - out0, out1, out2 = f(a, b) - np.testing.assert_allclose(out0.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(out1.numpy(), a.numpy()-b.numpy(), atol=1e-4, rtol=1e-5) - np.testing.assert_allclose(out2.numpy(), a.numpy()*b.numpy(), atol=1e-4, rtol=1e-5) - - def test_jit_multioutput_realize(self): - @TinyJit - def fxn(a, b): return (a+b).realize(), (a-b).realize(), (a*b).realize() - self._test(fxn) - assert_jit_cache_len(fxn, 3) - - def test_jit_multioutput_norealize(self): - @TinyJit - def fxn(a, b): return a+b, a-b, a*b - self._test(fxn) - assert_jit_cache_len(fxn, 1) - - def test_jit_multioutput_mix(self): - @TinyJit - def fxn(a, b): return a+b, a-b, (a*b).realize() - self._test(fxn) - assert_jit_cache_len(fxn, 2) - -class TestJitInsideJit(unittest.TestCase): - def test_jit_jit_error(self): - @TinyJit - def f(t): return t + 1 - - @TinyJit - def g(t): return f(t) * 3 - - # NOTE: first does not raise - g(Tensor([1])).realize() - with self.assertRaisesRegex(RuntimeError, "having TinyJit inside another TinyJit is not supported"): - g(Tensor([1])).realize() - -class TestCopyInsideJit(unittest.TestCase): - def test_copy_inside_jit(self): - @TinyJit - def add(x,y) -> Tensor: return x.to(Device.DEFAULT)+y - for _ in range(5): - # create a Tensor on CPU - a = Tensor.rand(16,16,device="CPU").realize() - b = Tensor.rand(16,16).realize() - out = add(a,b) - np.testing.assert_allclose(out.flatten().tolist(), [x+y for x,y in zip(a.flatten().tolist(), b.flatten().tolist())]) - -class TestJitPrune(unittest.TestCase): - def test_simple_prune(self): - weights = Tensor.rand(16).realize() - def w2(x) -> Tensor: return (weights*2).contiguous() + x - w2_noprune = TinyJit(w2) - w2_prune = TinyJit(w2, prune=True) - - for _ in range(3): - a = Tensor.rand(16).realize() - out = w2_noprune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - assert len(w2_noprune.captured.jit_cache) == 2 - - for _ in range(3): - a = Tensor.rand(16).realize() - out = w2_prune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - assert len(w2_prune.captured.jit_cache) == 1 - - def test_prune_w_copy_correct(self): - weights = Tensor.rand(16).realize() - def w2(x) -> Tensor: return (weights*2).contiguous() + x.to(Device.DEFAULT) - w2_noprune = TinyJit(w2) - w2_prune = TinyJit(w2, prune=True) - - for _ in range(3): - a = Tensor.rand(16, device="CPU").realize() - out = w2_noprune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - - for _ in range(3): - a = Tensor.rand(16, device="CPU").realize() - out = w2_prune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - - def test_prune_w_independent_copy_correct(self): - weights = Tensor.rand(16, device="CPU").realize() - def w2(x) -> Tensor: return (weights*2).contiguous().to(Device.DEFAULT) + x - w2_noprune = TinyJit(w2) - w2_prune = TinyJit(w2, prune=True) - - for _ in range(3): - a = Tensor.rand(16).realize() - out = w2_noprune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - - for _ in range(3): - a = Tensor.rand(16).realize() - out = w2_prune(a) - np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) - - assert len(w2_prune.captured.jit_cache) == 1, "prune should have removed the copy" - -class TestJitFree(unittest.TestCase): - def test_free_intermediates(self): - ext_tensor = Tensor([1,24,23,45,1]) - @TinyJit - def fxn(x:Tensor): - out = (x*2+ext_tensor).reshape(5,1).expand(5, 100).contiguous() - return out.sum() - for i in range(5): - out = fxn(Tensor([i,1,2,3,4])) - self.assertEqual(out.item(), 11400+200*i) - pre_free = GlobalCounters.mem_used - fxn.captured.free_intermediates() - savings_after_free = pre_free - GlobalCounters.mem_used - - # Different allocator implementations have different savings. - expected_savings = 8196 if hasattr(Device[Device.DEFAULT].allocator, '_offset') else 2024 - - self.assertEqual(savings_after_free, expected_savings) - out = fxn(Tensor([11,1,2,3,4])) - self.assertEqual(out.item(), 13600) - - # Try one more time... - pre_free = GlobalCounters.mem_used - fxn.captured.free_intermediates() - fxn.captured.free_intermediates() # 2nd time to validate - savings_after_free = pre_free - GlobalCounters.mem_used - - self.assertEqual(savings_after_free, expected_savings) - out = fxn(Tensor([11,1,2,3,4])) - self.assertEqual(out.item(), 13600) - - def test_updated_not_freed(self): - x = Tensor([1]).realize() - @TinyJit - def fxn(y): - nonlocal x - x += y - return x - for _ in range(5): fxn(Tensor([1])) - self.assertEqual(x.item(), 6) - pre_free = GlobalCounters.mem_used - fxn.captured.free_intermediates() - savings_after_free = pre_free - GlobalCounters.mem_used - self.assertEqual(savings_after_free, 0) - fxn(Tensor([2])) - self.assertEqual(x.item(), 8) - - def test_replan_buffers_memory_layout(self): - if not hasattr(Device[Device.DEFAULT].allocator, '_offset'): raise unittest.SkipTest("replan_buffers_memory_layout useless") - - ext_tensor = Tensor([1,24,23,45,1]) - ext_tensor_2 = Tensor([2,2,2,2,2]) - @TinyJit - def fxn(x:Tensor): - out = (x*ext_tensor_2+ext_tensor).reshape(5,1).expand(5, 100).contiguous() - return out.sum() - for i in range(5): - out = fxn(Tensor([i,1,2,3,4])) - self.assertEqual(out.item(), 11400+200*i) - assert len(set([b.base for item in fxn.captured.jit_cache for b in item.bufs if b is not None])) == 4 - fxn.captured.replan_buffers_memory_layout() - assert len(set([b.base for item in fxn.captured.jit_cache for b in item.bufs if b is not None])) == 2 - - out = fxn(Tensor([11,1,2,3,4])) - self.assertEqual(out.item(), 13600) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_jit_cases.py b/tinygrad/test/test_jit_cases.py deleted file mode 100644 index dd474e35..00000000 --- a/tinygrad/test/test_jit_cases.py +++ /dev/null @@ -1,78 +0,0 @@ -import unittest -from tinygrad import TinyJit, Tensor - -# The JIT functions as a "capturing" JIT. -# Whatever kernels ran in the JIT the second run through the function will be the kernels that will run from then on. -# Explicit inputs to the function are updated in the JIT graph to the new inputs. - -# JITs have four tensor types -# 1. Tensors that are explicit in the input, aka what's passed in. TODO: support lists/dicts/classes, anything get_state works on -# 2. Tensors that are explicit in the output, aka what's returned. TODO: same as above -# 3. Tensors that are implicit in the input as a closure. -# 4. Tensors that are implicit in the output because they were assigned to and realized. - -# explicit inputs and outputs are realized on their way in and out of the JIT -# there's a whole bunch of edge cases and weirdness here that needs to be tested and clarified. - -class TestJitCases(unittest.TestCase): - def test_explicit(self): - # this function has an explicit input and an explicit output - @TinyJit - def f(x:Tensor): - ret:Tensor = x*2 - return ret - - for i in range(5): - out = f(Tensor([i])) - self.assertEqual(out.item(), i*2) - - def test_implicit_input(self): - # x is the implicit input (like a weight) - x = Tensor([0]) - - # this function has an implicit input and an explicit output - @TinyJit - def f(): - ret:Tensor = x*2 - return ret - - for i in range(5): - # NOTE: this must be realized here, otherwise the update doesn't happen - # if we were explicitly tracking the implicit input Tensors, we might not need this realize - x.assign(Tensor([i])).realize() - out = f() - self.assertEqual(out.item(), i*2) - - def test_implicit_output(self): - # out is the implicit output (it's assigned to) - out = Tensor([0]) - - # this function has an explicit input and an implicit output - @TinyJit - def f(x:Tensor): - # NOTE: this must be realized here - # if we were explicitly tracking the implicit output Tensors, we might not need this realize - out.assign(x*2).realize() - - for i in range(5): - f(Tensor([i])) - self.assertEqual(out.item(), i*2) - - def test_implicit_io(self): - # x is the implicit input (like a weight) - # out is the implicit output (it's assigned to) - x = Tensor([0]) - out = Tensor([0]) - - # this function has an implicit input and an implicit output - @TinyJit - def f(): - out.assign(x*2).realize() # NOTE: this must be realized here - - for i in range(5): - x.assign(Tensor([i])).realize() - f() - self.assertEqual(out.item(), i*2) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_kernel_cache.py b/tinygrad/test/test_kernel_cache.py deleted file mode 100644 index 164b501a..00000000 --- a/tinygrad/test/test_kernel_cache.py +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python -import unittest -from tinygrad.tensor import Tensor -from tinygrad import Device - -class TestKernelCache(unittest.TestCase): - def test_kernel_cache_in_action(self): - if Device.DEFAULT not in ["CPU"]: - self.skipTest("No custom kernel cache is implemented") - - unique_const = 0.6765677269 - a = Tensor.rand(4,4).realize() - b = Tensor.rand(4,4).realize() - x = a + b + unique_const - x.realize() - - a1 = Tensor.rand(4,4).realize() - b1 = Tensor.rand(4,4).realize() - orig_compile_func = Device['CPU'].compiler - Device['CPU'].compiler = None # making it not callable - - try: - x1 = a1 + b1 + unique_const - x1.realize() # Same kernel should be from cache. - finally: - Device['CPU'].compiler = orig_compile_func - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_linearizer.py b/tinygrad/test/test_linearizer.py deleted file mode 100644 index 6a9dfe20..00000000 --- a/tinygrad/test/test_linearizer.py +++ /dev/null @@ -1,2215 +0,0 @@ -from typing import Union -import numpy as np -import unittest -from dataclasses import replace - -from test.helpers import ast_const -from tinygrad.codegen.kernel import Opt, OptOps, KernelOptError, Kernel -from tinygrad.codegen.lowerer import get_grouped_dims -from tinygrad.uop.ops import UOp, Ops, GroupOp -from tinygrad.device import Device, Buffer, is_dtype_supported -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.tensor import Tensor, _to_np_dtype -from tinygrad.engine.realize import run_schedule, lower_schedule, CompiledRunner -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.helpers import prod, Context, getenv, CI, flatten, dedup, AMX -from tinygrad.dtype import DType, dtypes - -def helper_realized_ast(r:Union[Tensor, list[Tensor]]) -> tuple[UOp, list[Buffer]]: - if isinstance(r, Tensor): r = [r] - s = Tensor.schedule(*r) - run_schedule(s[:-1]) # run all kernels except the last one - assert s[-1].ast.op is Ops.SINK, f"helper_realized_ast expects a SINK {s[-1]}" - # now all input buffers in s[-1] should be realized - # create fresh buffers for the outputs - bufs = [Buffer((x).device, x.size, x.dtype).allocate() if i < len(s[-1].ast.src) else x for i,x in enumerate(s[-1].bufs)] - return s[-1].ast, bufs - -def helper_tc_allclose(N:int, M:int, K:int, dtype_in:DType, dtype_out:DType, axis:int=0, tc_select:int=-1, tc_opt:int=0, use_tensor_cores:int=1): - a, b = Tensor.rand(M, K, dtype=dtype_in), Tensor.rand(K, N, dtype=dtype_in) - np_a, np_b = a.numpy(), b.numpy() - r = a.matmul(b, dtype=dtype_out) - if dtype_in == dtypes.bfloat16: r = r.float() - realized_ast, bufs = helper_realized_ast(r) - k = Kernel(realized_ast) - k.apply_tensor_cores(use_tensor_cores, axis=axis, tc_select=tc_select, tc_opt=tc_opt) - prg = CompiledRunner(replace(k.to_program(), device=Device.DEFAULT)) - if use_tensor_cores == 1: assert len([uop for uop in k.uops if uop.op is Ops.WMMA]) > 0, "wmma not triggered" - elif use_tensor_cores == 3: assert len([uop for uop in k.uops if uop.op is Ops.DEFINE_LOCAL]) == 2, "local buffers not triggered" - assert len([x for x in k.applied_opts if x.op is OptOps.TC]) == 1, "tensor core opt not included" - prg.exec(bufs) - if dtype_in == dtypes.half: tc_atol, tc_rtol = 1e-2, 1e-3 - elif dtype_in == dtypes.bfloat16: tc_atol, tc_rtol = 1e-2, 1e-2 - else: tc_atol, tc_rtol = 5e-3, 1e-4 - c = bufs[0].numpy().reshape((M,N)) - np.testing.assert_allclose(c, np_a @ np_b, atol=tc_atol, rtol=tc_rtol) - -def helper_tc_ensure_uops_and_opts_count(N: int, M:int, K:int, dtype_in:DType, dtype_out:DType, axis:int=0, tc_select:int=-1, tc_opt:int=0, - ensure_triggered:bool=True): - a, b = Tensor.rand(M, K, dtype=dtype_in), Tensor.rand(K, N, dtype=dtype_in) - r = a.matmul(b, dtype=dtype_out) - sched = r.schedule() - realized_ast = sched[-1].ast - k = Kernel(realized_ast) - k.apply_tensor_cores(1, axis=axis, tc_select=tc_select, tc_opt=tc_opt) - k.linearize() - wmmas = len([uop for uop in k.uops if uop.op is Ops.WMMA]) - tcs = len([x for x in k.applied_opts if x.op is OptOps.TC]) - if ensure_triggered: - assert wmmas > 0, "tensor core not triggered" - assert tcs == 1, "tensor core opt not included" - else: - assert wmmas == 0, "tensor core is incorrectly triggered" - assert tcs == 0, "tensor core opt is incorrectly included" - -class TestLinearizer(unittest.TestCase): - def test_arg_dedup(self): - # NOTE: this realize exists because Tensor.numpy calls .contiguous() internally - # without contiguous folding, rand.to("CPU") and rand.contiguous().to("CPU") are different UOps. - # this test asserts they are the identical Buffer - # having different buffers is fine for correctness, because the outputs match. - a, b = Tensor.randn(4).realize(), Tensor.randn(4).realize() - np_a, np_b = a.numpy(), b.numpy() - c = ((a.shrink(((0, 2),)) - a.shrink(((2, 4),))) - (b.shrink(((0, 2),)) - b.shrink(((2, 4),)))) - lowered = [x[1] for x in lower_schedule(c.schedule())] - for ei in lowered: ei.run() - rawbufs = lowered[-1].bufs - assert len(rawbufs) == 3 and set(rawbufs[1:]) == {a.uop.base.realized, b.uop.base.realized} - np_c = (np_a[:2] - np_a[2:]) - (np_b[:2] - np_b[2:]) - np.testing.assert_allclose(np_c, c.numpy(), atol=1e-4, rtol=1e-4) - - def test_load_removed(self): - a = Tensor.rand(1).realize() - b = Tensor.rand(1).realize() - ta = Tensor.where(Tensor(True), a, b).numpy() - tb = Tensor.where(Tensor(False), a, b).numpy() - np.testing.assert_equal(a.numpy(), ta) - np.testing.assert_equal(b.numpy(), tb) - - def test_multioutput(self): - dtype, st = dtypes.int, ShapeTracker.from_shape((8,)) - g0, g1, g2, g3 = [UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), arg=i) for i in range(4)] - a = UOp(Ops.LOAD, dtype, src=(g2.view(st),)) - b = UOp(Ops.LOAD, dtype, src=(g3.view(st),)) - out0 = UOp(Ops.STORE, dtypes.void, src=(g0.view(st), a + b)) - out1 = UOp(Ops.STORE, dtypes.void, src=(g1.view(st), a * b)) - sink = UOp(Ops.SINK, src=(out0, out1)) - - a_t = Tensor.full(st.shape, 2).contiguous().realize() - b_t = Tensor.full(st.shape, 3).contiguous().realize() - lin = helper_linearizer_ast(sink, [a_t, b_t], wanna_output=[a_t.numpy()+b_t.numpy(), a_t.numpy()*b_t.numpy()])[0] - - stores = [u for u in lin.uops if u.op is Ops.STORE] - mutable_bufs = dedup(flatten([[x for x in u.src[0].toposort() if x.op is Ops.DEFINE_GLOBAL] for u in stores])) - assert len(mutable_bufs) == len(stores) == 2 - self.assertSetEqual(set([u.arg for u in mutable_bufs]), set([0,1])) - - def _test_no_nested_ranges(self, lins, skip=None): - for l in lins: - range_in_acc = flatten([[x for x in u.src if x.op is Ops.RANGE] for u in l.uops if u.op is Ops.DEFINE_ACC]) - ranges = [u.op for u in l.uops if (u.op is Ops.RANGE and u in range_in_acc) or (u.op is Ops.ENDRANGE and u.src[0] in range_in_acc)] - for i,u in enumerate(ranges): - if skip and i in skip: continue - assert ranges[i-1] != u, f"multireduce nested the ranges! {ranges[i-1], {u}}" - - @unittest.expectedFailure - def test_const_alu_indexing(self): - st = ShapeTracker.from_shape((4,)).to_uop() - load = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()), st, dtype=dtypes.float) - op = load+UOp.const(dtypes.float, 1.0)*UOp.const(dtypes.float, -1) - store = UOp.store(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), st, op) - Tensor.manual_seed(0) - x = Tensor.randn(4,).realize() - helper_linearizer_ast(store.sink(), [x], wanna_output=[x.numpy()+1*-1], opts=[]) - - # shapeless CONST in AST is not supported - @unittest.expectedFailure - def test_const_alu_indexing_one_const_fine(self): - st = ShapeTracker.from_shape((4,)).to_uop() - load = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()), st, dtype=dtypes.float) - op = load+UOp.const(dtypes.float, 1.0) - store = UOp.store(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), st, op) - Tensor.manual_seed(0) - x = Tensor.randn(4,).realize() - helper_linearizer_ast(store.sink(), [x], wanna_output=[x.numpy()+1], opts=[]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(32, dtype=dtypes.float).realize() - st_x = x.uop.st - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((1, 32)).expand((32, 32))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (1,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((32, 1))),)) - diff = second_x + first_reduce*ast_const(dtypes.float, -1, (32, 1)) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (0,))) - store = UOp(Ops.STORE, dtypes.void, (g0.view(ShapeTracker.from_shape((1, 1))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [ - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # grouping - [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], - [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], - [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], # unroll reduce - [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], - [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], # can't do float8, - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], # grouping + unrolling - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], - [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 0, 8)], - ] - wanna_output = (x.numpy()-x.numpy().sum(-1, keepdims=True)).sum(-1).reshape(1,1) - lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - self._test_no_nested_ranges(lins, [0]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_mid_dim_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() - st_x = x.uop.st - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((27, 1, 32, 5)).expand((27, 32, 32, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((27, 32, 1, 5))),)) - diff = second_x + first_reduce*ast_const(dtypes.float, -1, (27, 32, 1, 5)) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [ - # locals - [Opt(OptOps.LOCAL, 0, 3)], - [Opt(OptOps.LOCAL, 0, 9)], - [Opt(OptOps.LOCAL, 0, 27)], - # grouping - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], - [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], - [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], - # # unroll - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], - [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], - [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], - # # upcasting - [Opt(OptOps.UPCAST, 0, 3)], - [Opt(OptOps.UPCAST, 0, 9)], - # locals with grouping - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - # locals with unroll - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], - # locals with upcasting - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 9)], - # grouping with unrolling - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], - # grouping with upcasting - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UPCAST, 0, 3)], - # locals with grouping with unroll - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], - # locals with grouping with upcasting - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - [Opt(OptOps.LOCAL, 0, 9), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - # grouping with unrolling and upcasting - [Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - [Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], - # locals + grouping + unrolling + upcasting - [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), - Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - ] - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - self._test_no_nested_ranges(lins, [0]) - - def test_triple_multireduce(self): - Tensor.manual_seed(0) - x0 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() - x1 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() - x2 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() - g0, g1, g2, g3 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(4)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x0.uop.st.reshape((27, 1, 1, 32, 5)).expand((27, 32, 32, 32, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x1.uop.st.reshape((27, 1, 32, 1, 5)).expand((27, 32, 32, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 32, 32, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (2,))) - third_x = UOp(Ops.LOAD, dtypes.float, (g3.view(x2.uop.st.reshape((27, 32, 1, 1, 5))),)) - mul = (third_x*second_reduce) - third_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (mul,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 1, 5))), third_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - wanna_output = (x2.numpy()*(x1.numpy()-x0.numpy().sum(axis=1, keepdims=True)).sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,1,5) - lins = helper_linearizer_ast(sink, [x0,x1,x2], wanna_output=[wanna_output]) - self._test_no_nested_ranges(lins, [0]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - @unittest.skip("this is not supported, it worked by luck") - def test_double_reduce_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(8, 32, 8, 16, dtype=dtypes.float).realize() - st = x.uop.st - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1, st.reshape((8, 1, 32, 8, 1, 16)).expand((8, 32, 32, 8, 16, 16)).to_uop())) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2, 5))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1, st.reshape((8, 32, 1, 8, 16, 1)).to_uop())) - neg_first_reduce = first_reduce * ast_const(dtypes.float, -1, (8, 32, 1, 8, 16, 1)) - squares = (second_x+neg_first_reduce) - squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (1, 4))) - store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((8, 1, 1, 8, 1, 1)).to_uop(), squares_sum,)) - sink = UOp(Ops.SINK, src=(store,)) - wanna_output = (x.numpy()-x.numpy().sum(axis=(1,3), keepdims=True)).sum(axis=(1,3)).reshape((8,1,1,8,1,1)) - opts = [ - # openCL / GPU=1 is 256 max threads - # grouping - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # first dim of both reduces - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 3, 2)], # both dims of the second reduce - [Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], # second dim of both reduces - [Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 3, 2)], # both dims of the first reduce - # group all reduce dims - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], - # checking how it works with 2 grouped reduces + unrolling - [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), - Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - # Checking how it works with 2 grouped reduces + locals. - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 0, 4), - Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], - # Checking how it works with 2 grouped reduces + locals + unroll. - [Opt(OptOps.LOCAL, 0, 2), - Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), - Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - # Checking how it works with 2 grouped reduces + locals + upcast. - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 0, 2), - Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], - # Checking how it works with 2 grouped reduces + locals + upcast + unroll. - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 0, 2), - Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), - Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], - ] - lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - self._test_no_nested_ranges(lins, [0, 1]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_partial_opt_multireduce(self): - # check how it works with one reduce optimized and one unoptimized - Tensor.manual_seed(0) - x = Tensor.randn(27, 15, 5, dtype=dtypes.float).softmax(1).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((27, 15, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [ - [Opt(OptOps.GROUPTOP, 0, 3)], # grouping - [Opt(OptOps.GROUPTOP, 1, 3)], - [Opt(OptOps.GROUPTOP, 0, 15)], - [Opt(OptOps.GROUPTOP, 1, 15)], - [Opt(OptOps.UNROLL, 0, 3)], - [Opt(OptOps.UNROLL, 1, 3)], - ] - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - self._test_no_nested_ranges(lins, [0]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_multireduce_with_parallel(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32, dtype=dtypes.float).realize() - x_p = Tensor.randn(4, 32, dtype=dtypes.float).realize() - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((4, 1, 32)).expand((4, 32, 32))),)) - first_x_p = UOp(Ops.LOAD, dtypes.float, (g2.view(x_p.uop.st.reshape((4, 1, 32)).expand((4, 32, 32))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - first_reduce_p = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x_p.alu(Ops.EXP2),), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((4, 32, 1))),)) - diff = (second_x+(first_reduce + first_reduce_p)*ast_const(dtypes.float, -1, (4, 32, 1))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((4, 1, 1))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [ - # [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # grouping - # [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], - # [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], - # [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], # unroll reduce - [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], - [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], # can't do float8, - # [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], # grouping + unrolling - # [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - # [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], - # [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 0, 8)], - ] - wanna_output = (x.numpy()-(x.numpy().sum(-1, keepdims=True)+np.exp2(x_p.numpy()).sum(-1, keepdims=True))).sum(-1).reshape(4, 1,1) - lins = helper_linearizer_ast(sink, [x,x_p], wanna_output=[wanna_output], opts=opts) - self._test_no_nested_ranges(lins, [0]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_multiout_multireduce(self): - # check how multireduce works with multioutput - Tensor.manual_seed(0) - x = Tensor.randn(27, 15, 5, dtype=dtypes.float).realize() - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - first_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x.uop.st.reshape((27, 15, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store0 = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - second_out = second_reduce * ast_const(dtypes.float, 1/15, (27, 1, 1, 5)) - store1 = UOp(Ops.STORE, src=(g1.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_out)) - sink = UOp(Ops.SINK, src=(store0, store1)) - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output, wanna_output/15]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_multiout_intermediate_multireduce(self): - # check how it outputing at different stages of the multireduce works - # TODO: Fails because the stores shapes do not match: store1.shape = (27,15,1,5) != store0.shape = (27,1,1,5) - # so the output shapes are different (FAIL!), - # if we change the shape of store1 to be contiguous, it will match store0 but not the value it's storing (FAIL!) - Tensor.manual_seed(0) - x = Tensor.randn(27, 15, 5, dtype=dtypes.float).realize() - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g2.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g2.view(x.uop.st.reshape((27, 15, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store0 = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - store1 = UOp(Ops.STORE, src=(g1.view(ShapeTracker(views=(View(shape=(27,15,1,5), strides=(5,0,1,1), offset=0, mask=None, contiguous=False),))), first_reduce)) # noqa: E501 - wanna_output0 = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - wanna_output1 = x.numpy().sum(axis=1).reshape(27,1,1,5) - - sink = UOp(Ops.SINK, src=(store0, store1)) - with self.assertRaises(RuntimeError): # AST is invalid - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output0, wanna_output1]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_complete_unroll_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(27, 3, 5, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 1, 3, 5)).expand((27, 3, 3, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 3, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 3, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [[Opt(OptOps.UNROLL, 0, 3), Opt(OptOps.UNROLL, 0, 3)]] - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_upcast_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(27, 3, 5, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 1, 3, 5)).expand((27, 3, 3, 5))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 3, 1, 5))),)) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 3, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [[Opt(OptOps.UPCAST, 0, 3)]] - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skip("can't group with multiple reduces yet") - def test_early_endif(self): - # make sure the if block of a grouped reduce can be closed early and the result loaded back in - Tensor.manual_seed(0) - x = Tensor.randn(27, 12, 5, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, (g1, x.uop.st.reshape((27, 1, 12, 5)).expand((27, 12, 12, 5)).to_uop())) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, (g1, x.uop.st.reshape((27, 12, 1, 5)).to_uop())) - diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 12, 1, 5))) - second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((27, 1, 1, 5)).to_uop(), second_reduce)) - sink = UOp(Ops.SINK, src=(store,)) - opts = [[Opt(OptOps.GROUPTOP, 0, 3), Opt(OptOps.GROUPTOP, 1, 3)]] - wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_mean_std_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 1, 35)).expand((15, 25, 35, 35))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) - neg_mean = first_reduce * ast_const(dtypes.float, -1/35, (15, 25, 35, 1)) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 35, 1))),)) - squares = (second_x+neg_mean)*(second_x+neg_mean) - squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) - variance = squares_sum * ast_const(dtypes.float, 1/35, (15, 25, 1, 1)) - std = variance.alu(Ops.SQRT) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((15, 25, 1, 1))), std)) - sink = UOp(Ops.SINK, src=(store,)) - wanna_output = x.numpy().std(axis=2, ddof=0).reshape((15,25,1,1)) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_mean_std_multireduce_mid_dim(self): - Tensor.manual_seed(0) - x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 1, 25, 35)).expand((15, 25, 25, 35))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) - neg_mean = first_reduce * ast_const(dtypes.float, -0.04, (15, 25, 1, 35)) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 1, 35))),)) - squares = (second_x+neg_mean)*(second_x+neg_mean) - squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (1,))) - variance = squares_sum * ast_const(dtypes.float, 0.04, (15, 1, 1, 35)) - std = variance.alu(Ops.SQRT) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((15, 1, 1, 35))), std)) - sink = UOp(Ops.SINK, src=(store,)) - wanna_output = x.numpy().std(axis=1, ddof=0).reshape((15,1,1,35)) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - @unittest.expectedFailure - def test_mean_std_multireduce_multiout(self): - # TODO: Similar error to test_multiout_intermediate_multireduce (implicit expand vs shape mismatch) - Tensor.manual_seed(0) - x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - first_x = UOp(Ops.LOAD, dtypes.float, (g2, x.uop.st.reshape((15, 25, 1, 35)).expand((15, 25, 35, 35)).to_uop())) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) - neg_mean = first_reduce * ast_const(dtypes.float, -1/35, (15, 25, 35, 1)) - second_x = UOp(Ops.LOAD, dtypes.float, (g2, x.uop.st.reshape((15, 25, 35, 1)).to_uop())) - squares = (second_x+neg_mean)*(second_x+neg_mean) - squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) - variance = squares_sum * ast_const(dtypes.float, 1/35, (15, 25, 1, 1)) - std = variance.alu(Ops.SQRT) - store_mean = UOp(Ops.STORE, src=(g1, ShapeTracker.from_shape((15, 25, 1, 1)).to_uop(), neg_mean)) - store_std = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((15, 25, 1, 1)).to_uop(), std)) - sink = UOp(Ops.SINK, src=(store_std, store_mean)) - wanna_output = [x.numpy().std(axis=2, ddof=0).reshape(15,25,1,1), x.numpy().mean(axis=2).reshape(15,25,1,1)] - - lins = helper_linearizer_ast(sink, [x], wanna_output=wanna_output) - for k in lins: - assert len([u for u in k.uops if u.op is Ops.DEFINE_ACC]) == 2, "got more than two accs (implies the kernel didn't reuse the mean reduce)" - - @unittest.skipIf(CI and Device.DEFAULT in {"PTX", "AMD", "NV"}, "ocelot/remu doesn't have multiple wave syncs yet") - def test_var_multireduce(self): - Tensor.manual_seed(0) - x = Tensor.randn(3, 27, 32, dtype=dtypes.float).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - # push reduce (3, 27, 32) -> (3, 27, 1) -> (3, 27, 32) expand to LOAD - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((3, 27, 1, 32)).expand((3, 27, 32, 32))),)) - first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) - neg_mean = first_reduce * ast_const(dtypes.float, -0.03125, (3, 27, 32, 1)) - # store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((3, 27, 32, 1)).to_uop(), mean)) - # verify_lazyop(store) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((3, 27, 32, 1))),)) - squares = (second_x+neg_mean)*(second_x+neg_mean) - squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) - variance = squares_sum * ast_const(dtypes.float, 0.03125, (3, 27, 1, 1)) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((3, 27, 1, 1))), variance)) - sink = UOp(Ops.SINK, src=(store,)) - wanna_output = x.numpy().var(axis=2, ddof=0).reshape((3,27,1,1)) - helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) - # tinygrad ref - y_tiny = x.var(axis=2, correction=0).reshape(3,27,1,1) - np.testing.assert_allclose(y_tiny.numpy(), wanna_output, atol=1e-4, rtol=1e-4) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_softmax_multireduce(self): - x = Tensor.rand(4, 32).realize() - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((4, 1, 32,)).expand((4, 32, 32))),)) - max_x = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.MAX, (2,))) - second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((4, 32, 1,))),)) - centered_x = second_x+max_x*ast_const(dtypes.float, -1, (4, 32, 1)) - exp_x = centered_x.alu(Ops.EXP2) - sum_exp_x = UOp(Ops.REDUCE_AXIS, dtypes.float, (exp_x,), (Ops.ADD, (1,))) - # y = exp_x * sum_exp_x.alu(Ops.RECIP) # kernels cannot do a return to full shape - recip_sum_exp_x = sum_exp_x.alu(Ops.RECIP) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((4,1,1))), recip_sum_exp_x)) - sink = UOp(Ops.SINK, src=(store,)) - expected = 1/np.exp2(x.numpy() - x.numpy().max(axis=-1, keepdims=True)).sum(axis=-1, keepdims=True).reshape(4,1,1) - helper_linearizer_ast(sink, [x], wanna_output=[expected]) - - @unittest.skipIf(CI and Device.DEFAULT in {"PTX", "AMD", "NV"}, "very slow") - def test_indexing_multireduce(self): - dataset = Tensor.rand(16384, 256).realize() - idxs = Tensor([0,3,5,6]).realize() - with Context(FUSE_ARANGE=1): - sink = dataset[idxs].contiguous().kernelize().uop.base.src[1].arg.ast - real_index = dataset.numpy()[idxs.numpy()].reshape(4, 1, 256, 1) - helper_linearizer_ast(sink, [dataset, idxs], wanna_output=[real_index]) - - # AssertionError: repeated stores in uops - def test_argmax_multireduce_axis0(self): - t = Tensor.randn(10, 20).realize() - t_max = t.max((0,)).realize() - real_argmax = np.argmax(t.numpy(), axis=0, keepdims=False).reshape(1, 20, 1) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 20, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(-1), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=10, src=( - x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 20, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x8:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x6,)), - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.MAX, (0,)), src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(200), arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(20, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(20), arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), # noqa: E501 - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(10, 20, 10), strides=(1, 0, 20), offset=0, mask=None, contiguous=False))), src=()),)), # noqa: E501 - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x28:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 20, 10), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x28,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=10, src=( - x21,)),)),)),)),)),)), - x8,)),)),)) - helper_linearizer_ast(ast, [t, t_max], wanna_output=[real_argmax]) - - def test_argmax_multireduce_flat(self): - t = Tensor.randn(10, 20).realize() - t_max = t.max().realize() - real_argmax = np.argmax(t.numpy()) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(-1), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=200, src=( - x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=()),)), # noqa: E501 - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x8:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x6,)), - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.MAX, (0,)), src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(200), arg=ShapeTracker(views=(View(shape=(200, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(200, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(200, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), # noqa: E501 - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(201, 399), strides=(0, 0), offset=0, mask=((0, 201), (199, 399)), contiguous=False), View(shape=(200, 200), strides=(1, 400), offset=0, mask=None, contiguous=False))), src=()),)), # noqa: E501 - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x28:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(200, 200), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x28,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=200, src=( - x21,)),)),)),)),)),)), - x8,)),)),)) - helper_linearizer_ast(ast, [t, t_max], wanna_output=[real_argmax]) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_padto_sum_multireduce(self): - Tensor.manual_seed(0) - N = 17 - x = Tensor.rand(N, N).realize() - opts = [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - # TODO: multireduce pads - # causes an issue because the acc won't be masked in the second reduce - # [Opt(OptOps.PADTO, 1, 32), Opt(OptOps.PADTO, 2, 32)] - ] - - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((1, N, N)).expand((N,N,N))),)) - x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N))),)) - r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.ADD, (1,))) - r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, 1, N)),),(Ops.ADD, (0,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,1,N))), r1)) - sink = UOp(Ops.SINK, src=(store,)) - helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().sum(axis=0, keepdims=True)).sum(axis=0).reshape(1,1,N)], opts=opts) - - x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N)).expand((N,N,N))),)) - x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, N, 1))),)) - r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.ADD, (2,))) - r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, N, 1)),), (Ops.ADD, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((N,1,1))), r1)) - sink = UOp(Ops.SINK, src=(store,)) - helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(N,1,1)], opts=opts) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_padto_max_multireduce(self): - Tensor.manual_seed(0) - N = 17 - x = Tensor.rand(N, N).realize() - opts = [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),] - ] - - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] - x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((1, N, N)).expand((N,N,N))),)) - x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N))),)) - r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.MAX, (1,))) - r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, 1, N)),), (Ops.MAX, (0,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,1,N))), r1)) - sink = UOp(Ops.SINK, src=(store,)) - helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().max(axis=0, keepdims=True)).max(axis=0).reshape(1,1,N)], opts=opts) - - x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N)).expand((N,N,N))),)) - x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, N, 1))),)) - r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.MAX, (2,))) - r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, N, 1)),), (Ops.MAX, (1,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((N,1,1))), r1)) - sink = UOp(Ops.SINK, src=(store,)) - helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().max(axis=1, keepdims=True)).max(axis=1).reshape(N,1,1)], opts=opts) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") - def test_padto_where_multireduce(self): - # ternary operators try to use both ridxs - - # we need to make sure the ternary operators nest properly - N = 17 - x = Tensor.rand(N, N).realize() - a = Tensor.rand(1, 1).realize() - b = Tensor.rand(1, 1).realize() - opts = [[Opt(OptOps.PADTO, 0, 32)],[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),],] - - wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(axis=1,keepdims=True), a.numpy(), b.numpy())).sum(axis=1),0.0,1.0).reshape((N,1,1)) # noqa: E501 - ld0 = x.uop.st.reshape((N, 1, N)).expand((N,N,N)) - ld1 = x.uop.st.reshape((N, N, 1)) - ast = UOp(Ops.SINK, src=( - UOp(Ops.STORE, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.5*N, (N, 1, 1)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld1, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.75*N, (N, N, 1)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld0, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3),)),)),)),)),)),)), - ast_const(dtypes.float, 0.0, (N, 1, 1)), - ast_const(dtypes.float, 1.0, (N, 1, 1)),)),)),)) - helper_linearizer_ast(ast, [x,a,b], opts=opts, wanna_output=[wanna_output]) - - ld0 = x.uop.st.reshape((1, N, N)).expand((N,N,N)) - ld1 = x.uop.st.reshape((N, 1, N)) - wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(axis=0,keepdims=True), a.numpy(), b.numpy())).sum(axis=0),0.0,1.0).reshape(1,1,N) # noqa: E501 - ast = UOp(Ops.SINK, src=( - UOp(Ops.STORE, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(1, 1, N), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.5*N, (1, 1, N)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld1, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.75*N, (N, 1, N)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld0, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, N), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, N), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3, src=()),)),)),)),)),)),)), - ast_const(dtypes.float, 0.0, (1, 1, N)), - ast_const(dtypes.float, 1.0, (1, 1, N)),)),)),)) - helper_linearizer_ast(ast, [x,a,b], opts=opts, wanna_output=[wanna_output]) - # pad reduce axis - helper_linearizer_ast(ast, [x,a,b], opts=[[Opt(OptOps.PADTO, 1, 32)],], wanna_output=[wanna_output]) - - ld0 = x.uop.st.reshape((1,1,N,N)).expand((N,N,N,N)) - ld1 = x.uop.st.reshape((N,N,1,1)) - wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(keepdims=True), a.numpy(), b.numpy())).sum(keepdims=True),0.0,1.0).reshape((1,1,1,1))# noqa: E501 - ast = UOp(Ops.SINK, src=( - UOp(Ops.STORE, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.5*N, (1, 1, 1, 1)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 1)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(N, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - ast_const(dtypes.float, 0.75*N, (N, N, 1, 1)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 3)), src=( - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, N, N), strides=(0, 0, N, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2),)),)), - UOp(Ops.LOAD, dtypes.float, src=( - UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3),)),)),)),)),)),)), - ast_const(dtypes.float, 0.0, (1, 1, 1, 1)), - ast_const(dtypes.float, 1.0, (1, 1, 1, 1)),)),)),)) - helper_linearizer_ast(ast, [x,a,b], opts=[[Opt(OptOps.PADTO, 0, 32)],], wanna_output=[wanna_output]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_end_local(self): - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=i) for i in range(2)] - load = UOp(Ops.LOAD, dtypes.int, (g1.view(ShapeTracker.from_shape((32,))),)) - reduce = UOp(Ops.REDUCE_AXIS, dtypes.int, (load,), (Ops.ADD, (0,))) - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,))), reduce)) - sink = UOp(Ops.SINK, src=(store,)) - load_t = Tensor.full(load.st_arg.shape, 1).contiguous().realize() - k = helper_linearizer_ast(sink, [load_t], wanna_output=[load_t.numpy().sum()])[1] - self.assertEqual(k.uops[-2].op, Ops.ENDIF) - self.assertEqual(k.uops[-1].op, Ops.SINK) - self.assertLess(k.uops.index([x for x in k.uops if x.op is Ops.STORE][-1]), k.uops.index(k.uops[-1])) - - def test_two_nested_range(self): - a = Tensor.randn(2, ).realize() - out = a.reshape(2, 1).expand(2, 3).sum() - lin = helper_linearizer_opt(out, wanna_output=[np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)).sum()])[0] - ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] - assert len(ranges) == 1 # NOTE: it collapses now - # RANGE -> LOAD -> RANGE -> ASSIGN - #assert any(x.op is Ops.LOAD for x in lin.uops[ranges[0]:ranges[1]]) - - def test_three_nested_range(self): - a = Tensor.randn(2, ).realize() - out = a.reshape(2, 1).expand(2, 3).expand(2, 2, 3).sum() - lin = helper_linearizer_opt(out, wanna_output=[np.broadcast_to(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)), (2, 2, 3)).sum()])[0] - ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] - assert len(ranges) == 1 # NOTE: it collapses now - # RANGE -> RANGE -> LOAD -> RANGE -> ASSIGN - # NOTE: nothing should toposort between the first two ranges - #assert ranges[0]+1 == ranges[1] - #assert any(x.op is Ops.LOAD for x in lin.uops[ranges[1]:ranges[2]]) - - def test_two_nested_range_alt_indexing(self): - a = Tensor([2, 2]).realize() - out = a.reshape(2, 1).pad(((1, 1), (1, 1)), value=2).sum() - lin = helper_linearizer_opt(out, wanna_output=[24])[0] - ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] - # RANGE -> ALU -> RANGE -> ALU + LOAD -> ASSIGN - assert any(x.op in GroupOp.ALU for x in lin.uops[ranges[0]:ranges[1]]) - assert not any(x.op is Ops.LOAD for x in lin.uops[ranges[0]:ranges[1]]) - assert any(x.op in {*GroupOp.ALU, Ops.LOAD} for x in lin.uops[ranges[1]:]) - - def test_range_outer_op_before_phi(self): - a = Tensor.randn(4, 1).realize() - b = Tensor.randn(1, 1).realize() - out = (a + b[0]).sum() + b[0] - lin = helper_linearizer_opt(out, wanna_output=[(a.numpy()+b.numpy()[0]).sum()+b.numpy()])[0] - ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] - # LOAD -> RANGE -> LOAD -> ASSIGN - assert len([x for x in lin.uops[:ranges[0]] if x.op is Ops.LOAD]) == 1 - - def test_range_outer_op_before_phi_nested_range(self): - a = Tensor.randn(2, ).realize() - b = Tensor.randn(1, 1).realize() - out = (a.reshape(2, 1).expand(2, 3) + b[0]).sum() + b[0] - lin = helper_linearizer_opt(out, wanna_output=[(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)) + b.numpy()[0]).sum() + b.numpy()])[0] - ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] - assert len(ranges) == 1 # NOTE: it collapses now - #if getenv("PTX"): - # LOAD -> RANGE -> CAST -> ALU -> ALU -> LOAD -> ALU -> RANGE -> ALU -> ASSIGN - # assert lin.uops[ranges[0]-2].op is Ops.LOAD - # assert ranges[1] == ranges[0]+6 - # assert [x.op for x in lin.uops[ranges[1]-2:ranges[1]]] == [Ops.LOAD, Ops.ALU] - # LOAD -> RANGE -> LOAD -> ALU -> RANGE -> ASSIGN - #else: - # assert lin.uops[ranges[0]-2].op is Ops.LOAD - # assert ranges[1] == ranges[0]+3 - # assert [x.op for x in lin.uops[ranges[1]-2:ranges[1]]] == [Ops.LOAD, Ops.ALU] - - def test_range_outer_op_after_phi(self): - a = Tensor.randn(4, 1).realize() - out = a.sum() * a.sum() - lin = helper_linearizer_opt(out, wanna_output=[a.numpy().sum()*a.numpy().sum()])[0] - # RANGE -> LOAD -> ASSIGN -> ALU - end = max(i for i,u in enumerate(lin.uops) if u.op is Ops.ENDRANGE) - # the INDEX can be first - assert lin.uops[end+1].op in GroupOp.ALU or lin.uops[end+2].op in GroupOp.ALU - - def test_range_outer_op_after_phi_nested_range(self): - a = Tensor.randn(2, ).realize() - out = a.reshape(2, 1).expand(2, 3).sum() + a.reshape(2, 1).expand(2, 3).sum() - lin = helper_linearizer_opt(out, wanna_output=[(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3))).sum()*2])[0] - # RANGE -> LOAD -> ASSIGN -> ALU - end = max(i for i,u in enumerate(lin.uops) if u.op is Ops.ENDRANGE) - # the INDEX can be first - assert lin.uops[end+1].op in GroupOp.ALU or lin.uops[end+2].op in GroupOp.ALU - - def test_load_dedup(self): - # for different leaves in the AST, the same loads may occur. - - a = Tensor.randn(4).realize() - # these are of size 3 to avoid float4 coalesce - r = a[:-1] + a[1:] - - k = Kernel(r.schedule()[-1].ast) - k.upcast() - k.linearize() - num_loads = len([uop for uop in k.uops if uop.op is Ops.LOAD]) - assert num_loads <= 4, "more load uops than needed" - assert num_loads >= 4, "unexpected number of uops, maybe this test needs updating?" - - @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") - def test_load_cache_const_bufs(self): - # make sure const buffers are differentiated from local and mem buffers - ST, DT = ShapeTracker(views=(View(shape=((1,)), strides=(0, 0), offset=0, mask=None, contiguous=False),)).to_uop(), dtypes.int - VAL = ast_const(DT, 2, ST.arg.shape) - g0, g1 = [UOp(Ops.DEFINE_GLOBAL, DT.ptr(), arg=i) for i in range(2)] - - # data1[0] + VAL - a = UOp(Ops.LOAD, DT, (g1.view(ST.arg),)) + VAL - # (literal const 1) + VAL - b = ast_const(DT, 1, ST.arg.shape) + VAL - - store = UOp(Ops.STORE, src=(g0.view(ST.arg), (a+b))) - sink = UOp(Ops.SINK, src=(store,)) - lin = Kernel(sink) - lin.linearize() - assert len(lin.uops) <= 10, "too many uops" - - def test_upcast_cse(self): - # when upcasting, within a subtree, there may be common expressions. - - a, b = Tensor.randn(1).realize(), Tensor.randn(1).realize() - r = a.expand([2]) + b.expand([2]) - - k = Kernel(r.schedule()[-1].ast) - k.upcast() - k.linearize() - num_ops = len([uop for uop in k.uops if uop.op in GroupOp.ALU]) - assert num_ops <= 1, "more alu uops than needed" - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_reduce_upcast(self): - x, w = Tensor.randn((1,1,3)).realize(), Tensor.randn((1,1,2)).realize() - r = Tensor.conv2d(x,w,padding=1).relu() - - k = Kernel(r.schedule()[-1].ast) - k.upcast() - k.upcast() - k.linearize() - accs = [u for u in k.uops if u.op is Ops.DEFINE_ACC] - stores = [u for u in k.uops if u.op is Ops.STORE] - assert len(accs) == 0 # it's removed now - assert len(stores) == 1 - assert stores[0].src[-1].dtype == dtypes.float.vec(4) - - # NOTE: can reenable, it does work. it just makes BEAM slow - @unittest.expectedFailure - @unittest.skipUnless(Device.DEFAULT == "CPU", "test only for CPU") - def test_upcast_with_locals_cpu(self): - out = Tensor.ones(64,64).contiguous() @ Tensor.ones(64,64).contiguous() - k = Kernel(out.schedule()[-1].ast) - k.apply_opt(Opt(OptOps.LOCAL, axis=0, arg=4)) - prg = k.to_program() - self.assertEqual(len(prg.src.split("for")), 5) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") - def test_upcast_with_locals(self): - x, y = Tensor.rand(1,128), Tensor.rand(128, 128) - r = (x@y).relu() - k = Kernel(r.schedule()[-1].ast) - k.apply_opts([Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)]) - k.linearize() - - stores = [u for u in k.uops if u.op is Ops.STORE] - - # the first store is to lds and can be upcasted - assert stores[0].src[-1].dtype == dtypes.float.vec(4) - assert any(x.op is Ops.DEFINE_LOCAL for x in stores[0].toposort()) - # the second store is to gds with no upcasts - assert stores[1].src[-1].dtype == dtypes.float - assert any(x.op is Ops.DEFINE_GLOBAL for x in stores[1].toposort()) - - def test_zero_fold(self): - a, b = Tensor.randn(1).realize(), Tensor.randn(1).realize() - r = Tensor.stack(a, b) - - k = Kernel(r.schedule()[-1].ast) - k.upcast() - k.linearize() - num_ops = len([uop for uop in k.uops if uop.op in GroupOp.ALU]) - assert num_ops == 0, "more alu uops than needed" - - def test_sum_acc_dtype(self): - for tensor_dtype, acc_dtype in ( - (dtypes.bool, dtypes.int), (dtypes.int16, dtypes.int), (dtypes.float16, dtypes.float), (dtypes.bfloat16, dtypes.float)): - if is_dtype_supported(tensor_dtype) and is_dtype_supported(acc_dtype): - a = Tensor([1, 2, 3], dtype=tensor_dtype).sum() - k = Kernel(a.schedule()[-1].ast) - k.linearize() - local = [uop for uop in k.uops if uop.op is Ops.DEFINE_ACC] - assert local[0].dtype == acc_dtype - - def test_arg_acc_dtype(self): - def helper_arg_acc_dtype(c: Tensor, expected_dtype:DType): - k = Kernel(c.schedule()[-1].ast) - k.linearize() - local = [uop for uop in k.uops if uop.op is Ops.DEFINE_ACC] - assert local[0].dtype == expected_dtype - - tests = ( - (dtypes.float16, None, dtypes.float), - (dtypes.bfloat16, None, dtypes.float), - (dtypes.float, None, dtypes.float), - (dtypes.float16, dtypes.float16, dtypes.float16), - (dtypes.bfloat16, dtypes.bfloat16, dtypes.bfloat16), - (dtypes.float, dtypes.float16, dtypes.float16), - ) - for tensor_dtype, acc_dtype, expected_dtype in tests: - if is_dtype_supported(tensor_dtype) and is_dtype_supported(acc_dtype) and is_dtype_supported(expected_dtype): - a, b = Tensor.rand(8, 8, dtype=tensor_dtype), Tensor.rand(8, 8, dtype=tensor_dtype) - helper_arg_acc_dtype(a.sum(dtype=acc_dtype), expected_dtype) - helper_arg_acc_dtype(a.matmul(b, dtype=acc_dtype), expected_dtype) - helper_arg_acc_dtype(Tensor.einsum("ki,ij->kj", a, b, dtype=acc_dtype), expected_dtype) - d, w = Tensor.rand(4, 8, 8, 8, dtype=tensor_dtype), Tensor.rand(8, 8, 2, 2, dtype=tensor_dtype) - helper_arg_acc_dtype(d.conv2d(w, dtype=acc_dtype), expected_dtype) - - # TODO: don't skip bf16 for real device (METAL, AMD) - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - # for AMX, tc.dims[2] == 1 so reduceop is None thus tensor_cores are not triggered - helper_tc_allclose(tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2], tc.dtype_in, tc.dtype_out, axis=0, tc_opt=0) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_emulation(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - # for AMX, tc.dims[2] == 1 so reduceop is None thus tensor_cores are not triggered - helper_tc_allclose(tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2], tc.dtype_in, tc.dtype_out, axis=0, tc_opt=0, use_tensor_cores=3) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_codegen(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - n, m, k = tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2] - a, b = Tensor.rand(m, k, dtype=tc.dtype_in), Tensor.rand(k, n, dtype=tc.dtype_in) - r = a.matmul(b, dtype=tc.dtype_out) - sched = r.schedule() - realized_ast = sched[-1].ast - kernel = Kernel(realized_ast) - kernel.apply_tensor_cores(1, axis=0, tc_select=-1, tc_opt=2) - kernel.linearize() - prg = kernel.to_program() - if Device.DEFAULT == "LLVM": - assert "0x201000" in prg.src - elif Device.DEFAULT == "AMD" and getenv("AMD_LLVM", 0): - assert "@llvm.amdgcn.wmma" in prg.src - elif Device[Device.DEFAULT].renderer.suffix == "PTX": - assert "mma.sync.aligned" in prg.src - else: - assert "__WMMA_" in prg.src - - @unittest.skipIf(Device.DEFAULT in ("AMD", "AMD_LLVM") or (Device.DEFAULT == "PYTHON" and getenv("EMULATE_AMD")), "broken for AMD") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_padded(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - helper_tc_allclose(tc.dims[0]+(pad:=1), tc.dims[1]+pad, tc.dims[2]+pad, tc.dtype_in, tc.dtype_out, tc_opt=2) - - # AMD compiler bug: AMD miscompiles non-zero padded tc kernels with -O3, producing wrong results, nans or hang (see #9606) - # Internal bug: zero-stride dimensions combined with a mask may produce wrong index/valid for pad == 1 on AMD - @unittest.skipUnless(Device.DEFAULT in ("AMD", "AMD_LLVM") or (Device.DEFAULT == "PYTHON" and getenv("EMULATE_AMD")), "test for AMD's tc") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - @unittest.expectedFailure - def test_tensor_cores_padded_amd(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - helper_tc_allclose(tc.dims[0]+(pad:=1), tc.dims[1]+pad, tc.dims[2]+pad, tc.dtype_in, tc.dtype_out, tc_opt=2) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_padded_uops(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - pad = 1 - - # check that TC is triggered for TC_OPT=2 - helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, - tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=True) - - # check that TC is not triggered for TC_OPT<2 - helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, - tc.dtype_in, tc.dtype_out, tc_opt=1, ensure_triggered=False) - helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, - tc.dtype_in, tc.dtype_out, tc_opt=0, ensure_triggered=False) - - # check excessive padding doesn't trigger padded TC in TC_OPT=2 - helper_tc_ensure_uops_and_opts_count(tc.dims[0]//4, tc.dims[1], tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) - helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1]//4, tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) - if not AMX: # AMX tc.dims[2] == 1 - helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1], tc.dims[2]//4, tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) - - @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI is really slow here") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_multi_reduce(self): - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue - # this will be a M=G16, N=G32, M=G16, M=G16, K=R16, K=R16, K=R16 with 9 choices of TC MNK axes - golden_result = None - for axis in range(9): - a = Tensor.rand(16, 16, 29, 29, dtype=tc.dtype_in).realize() - b = Tensor.rand(32, 16, 16, 16, dtype=tc.dtype_in).realize() - c = a.conv2d(b, padding=1, dtype=tc.dtype_out) - realized_ast, real_bufs = helper_realized_ast(c) - - k = Kernel(realized_ast) - k.apply_tensor_cores(1, axis=axis, tc_opt=2) - k.linearize() - assert len([uop for uop in k.uops if uop.op is Ops.WMMA]) > 0, "tensor core not triggered" - assert len([x for x in k.applied_opts if x.op is OptOps.TC]) == 1, "tensor core opt not included" - - prg = CompiledRunner(k.to_program()) - # TODO: support this even if numpy doesn't - if _to_np_dtype(real_bufs[0].dtype) is None: continue - real_bufs[0].copyin(np.zeros((real_bufs[0].size, ), dtype=_to_np_dtype(real_bufs[0].dtype)).data) # Zero to check that all values are filled - prg.exec(real_bufs) - result = np.frombuffer(real_bufs[0].as_buffer(), _to_np_dtype(real_bufs[0].dtype)) - - # ensure the results for each choice of axis matches - if golden_result is None: golden_result = np.frombuffer(real_bufs[0].as_buffer(), _to_np_dtype(real_bufs[0].dtype)) - np.testing.assert_allclose(result, golden_result, atol=0.1, rtol=0.2) - - # check that get_kernel_actions produces all 9 options - from tinygrad.engine.search import get_kernel_actions - tc_actions = [k for i, k in get_kernel_actions(Kernel(realized_ast), False).items() if k.applied_opts[0].op == OptOps.TC] - - available_tc = len([x for x in Device[Device.DEFAULT].renderer.tensor_cores if x.dtype_in == tc.dtype_in and x.dtype_out == tc.dtype_out]) - assert len(tc_actions) == 9 * available_tc, f"should contain 9 possible TC actions for every available TC, got {len(tc_actions)}" - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_cores_unroll_phi(self): - tc = Device[Device.DEFAULT].renderer.tensor_cores[0] - x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) - r = x.matmul(y, dtype=tc.dtype_out) - k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] - for u in k.uops: - if u.op is Ops.WMMA: - assert u.src[-1].src[0].op != Ops.ASSIGN - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"}, "CPU does not support using a different type for accumulation") - def test_tensor_cores_unroll_casted_phi(self): - tc = [tc for tc in Device[Device.DEFAULT].renderer.tensor_cores if tc.dtype_in != tc.dtype_out][0] - x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) - r = x.matmul(y, dtype=tc.dtype_out) - k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] - for u in k.uops: - if u.op is Ops.WMMA: - #assert u.src[-1].dtype == dtypes.float.vec(prod(tc.thread_local_sizes[2])) - assert u.src[-1].src[0].op != Ops.ASSIGN - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"}, "CPU does not support using a different type for accumulation") - def test_tensor_cores_unroll_casted_phi_with_children(self): - # all ASSIGN children are outside the loop - tc = [tc for tc in Device[Device.DEFAULT].renderer.tensor_cores if tc.dtype_in != tc.dtype_out][0] - x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) - r = x.matmul(y, dtype=tc.dtype_out).relu() - k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] - for u in k.uops: - if u.op is Ops.WMMA: - #assert u.src[-1].dtype == dtypes.float.vec(prod(tc.thread_local_sizes[2])) - assert u.src[-1].src[0].op != Ops.ASSIGN - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_simple_unroll_no_between_phi_dependencies(self): - x, y = Tensor.rand(128, 128), Tensor.rand(128, 128) - r = (x@y).relu() - k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4)]])[-1] - # the uops graph is RANGE -> DEFINE_ACC -> 4x ALU -> 4x ASSIGN -> ENDRANGE - for u in k.uops: - if u.op is Ops.ASSIGN: - assert u.src[1].op in GroupOp.ALU - # children of ASSIGN are placed after ENDRANGE - if any(x.op is Ops.ASSIGN for x in u.src): - end_range = [i for i, x in enumerate(k.uops) if x.op is Ops.ENDRANGE][0] - assert end_range < k.uops.index(u) - - def test_grouped_dims(self): - def _assert_grouped_dims(prefix, dims, max_sizes, reverse_dims, expected_sizes, assert_same_length = True): - idxs = get_grouped_dims(prefix, dims, max_sizes, reverse_dims) - loop_idxs = dedup(flatten([[y for y in x.toposort() if y.op is Ops.SPECIAL] for x in idxs])) - loop_idxs = sorted(loop_idxs, key=lambda uop: uop.arg[0]) - sizes = [x.arg[1] for x in loop_idxs] - assert len(idxs) == len(dims), f"expected idxs to have same length as dims {len(dims)}, got {len(idxs)}" - if assert_same_length: - assert len(loop_idxs) == min(len(sizes), len(dims)), f"expected idxs to have length {min(len(sizes), len(dims))}, got {len(loop_idxs)}" - assert sizes == expected_sizes, f"expected sizes={expected_sizes}, got {sizes=}" - # TODO: add these back after uop symbolic - # for i in range(len(dims)): - # assert idxs[i].max+1 == dims[i], f"idxs[{i}] should have max {dims[i]-1}" - # for i in range(len(loop_idxs)): - # assert loop_idxs[i].expr.startswith(prefix), f"loop_idxs[{i}] must start with {prefix}" - # assert loop_idxs[i].max+1 == sizes[i], f"loop_idxs[{i}] should have max {sizes[i]-1}" - - # no-op - _assert_grouped_dims("gidx", (2,), (16,16,16), False, [2]) - _assert_grouped_dims("gidx", (2,3), (16,16,16), False, [2,3]) - - # check reverse dims - _assert_grouped_dims("gidx", (2,3), (16,16,16), True, [3,2]) - _assert_grouped_dims("gidx", (2,3,4), (16,16,16), False, [2,3,4]) - - # test splitting globals: len(dims) == len(max) - _assert_grouped_dims("gidx", (64,3,4), (16,16,16), False, [16,12,4]) - _assert_grouped_dims("gidx", (64,3,4), (16,4,16), False, [16,3,16]) - _assert_grouped_dims("gidx", (64,3,4), (16,16,16), True, [16,3,16]) - _assert_grouped_dims("gidx", (128,3,4), (16,4,256), False, [16,3,32]) - _assert_grouped_dims("gidx", (4,4,512), (16,4,256), False, [8,4,256]) - - # prefer group_dim strategy when possible - _assert_grouped_dims("gidx", (512,4,2), (8192,2,2), False, [2048,2]) - - # test splitting globals: len(dims) < len(max) - # len(dim) -> len(limited) - # 1 -> 2 - _assert_grouped_dims("gidx", (128,), (16,16,256), False, [16,8], False) - # 1 -> 3 - _assert_grouped_dims("gidx", (65536,), (16,16,256), False, [16,16,256], False) - # 2 -> 3 - _assert_grouped_dims("gidx", (128,128), (16,16,256), False, [16,16,64], False) - # test when the only divisor is the square root of dim - _assert_grouped_dims("gidx", (121,), (12,12,12), False, [11,11], False) - - # collapse on onto the left most axis - _assert_grouped_dims("gidx", (2,3,4,5), (16,16,16), False, [6,4,5]) - _assert_grouped_dims("gidx", (2,3,4,5), (32,16,16), True, [20,3,2]) - # _assert_grouped_dims("gidx", (Variable("start_pos",1,2),3,4,5), (32,16,16), True, [20,3,Variable("start_pos",1,2)]) - - # collapse on left-most available axis (the left most is too small) - _assert_grouped_dims("gidx", (2,3,4,5), (4,16,16), False, [2,12,5]) - _assert_grouped_dims("gidx", (2,3,4,5), (16,16,16), True, [5,12,2]) - - # _assert_grouped_dims("gidx", (Variable("start_pos",1,2),3,4,5), (16,16,16), False, [Variable("start_pos",1,2)*3,4,5]) - - # dim too large and not factorable - with self.assertRaises(RuntimeError): - get_grouped_dims("gidx", (23,), (16,16,16), False,) - with self.assertRaises(RuntimeError): - get_grouped_dims("gidx", (128,3,4), (16,2,2), False,) - - # too large for sizes - with self.assertRaises(RuntimeError): - get_grouped_dims("gidx", (2,3,4,5,6), (16,16,16)) - - # # variable too large - # with self.assertRaises(AssertionError): - # get_grouped_dims("gidx", (Variable("start_pos",0,16),3,4), (16,16,16), False,) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - def test_default_global_reversed(self): - # shrink so that the dims do not collapse - t = Tensor.ones(5, 6, 7).contiguous().realize().shrink(((0, 4), (0, 5), (0, 6))) - k = helper_linearizer_opt(t+1)[0] - idxs = dedup([uop for uop in k.uops if uop.op is Ops.SPECIAL]) - idxs = sorted(idxs, key=lambda uop: uop.arg[0]) - assert idxs[0].arg == ('gidx0', 6), idxs[0].arg - assert idxs[1].arg == ('gidx1', 5), idxs[1].arg - assert idxs[2].arg == ('gidx2', 4), idxs[2].arg - - def test_sum_collapse(self): - t = Tensor([2]).reshape(1, 1).expand(256, 256).sum() - sched = [si for si in t.schedule() if si.ast.op is Ops.SINK] - # sum_collapse is a full collapse now - assert len(sched) == 1 - assert not any(u.op is Ops.REDUCE_AXIS for u in sched[0].ast.toposort()), "found reduce in sum collapse" - #lin = Kernel(sched[0].ast) - #assert not any(u.op is Ops.RANGE for u in lin.linearize().uops), "found loop in sum collapse" - - def test_assign_fold(self): - a = Tensor.ones(4, 4).contiguous().realize() - m = Tensor.ones(4, 4).shrink(((1, 2), None)).pad(((1, 2), None)) - a.assign(a+m) - a.realize() - np.testing.assert_equal(a.flatten().numpy(), [1.,1.,1.,1.,2.,2.,2.,2.,1.,1.,1.,1.,1.,1.,1.,1.]) - - def test_where_fold(self): - a = Tensor.ones(4, 4).contiguous().realize() - b = a.shrink(((1, 2), None)).pad(((1, 2), None)) - a.assign(b.where(2, a)) - sched = a.schedule() - assert len(sched) == 1 - sched_copy = sched[:] - run_schedule(sched) - np.testing.assert_equal(a.flatten().numpy(), [1.,1.,1.,1.,2.,2.,2.,2.,1.,1.,1.,1.,1.,1.,1.,1.]) - lin = Kernel(sched_copy[-1].ast) - lin.linearize() - assert not any(u.op == Ops.WHERE for u in lin.uops), "found where where where should be folded" - - def test_phi_simplification(self): - def helper(t, max_ops=0): - k = helper_linearizer_opt(t)[-1] - uops = list(k.linearize().uops) - # ignore kernel optimized IF statements for now - if if_op:=next((u for u in uops if u.op is Ops.IF), None): - uops = uops[:uops.index(if_op)] - assert len(set([u.op for u in uops if u.op in {Ops.RANGE, Ops.SPECIAL}])) == 1, "has either specials or ranges, not both" - assert len([u for u in uops if u.op is Ops.ASSIGN]) == 0, "ASSIGN should have been simplified" - # TODO: once uops track min/max this will be fixed - #assert len([u for u in uops if u.op is Ops.MAX]) <= max_ops, "no unnecessary MAX ops" - - helper(Tensor.arange(5.5, (3.5*300), 3.5), max_ops=2) - helper(Tensor.arange(-1, -100, -5), max_ops=2) - # NOTE: both of these split the reduce (this just wasn't tracked before) - #helper(Tensor.arange(-3.2, 6.7, 0.64), max_ops=2) - #helper(Tensor.arange(256), max_ops=2) - helper(Tensor.arange(255), max_ops=2) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_grouped_store_phis(self): - """ - float4 acc0 = float4(0.0,0.0,0.0,0.0); - { - acc0 = // ... - } - *((device float4*)(data0+alu2)) = float4(acc0.x,acc0.y,acc0.z,acc0.w); - simplifies to: - *((device float4*)(data0+alu2)) = acc0; - """ - x, y = Tensor.randn(64,64), Tensor.randn(64,64) - out = x.matmul(y) - k = helper_linearizer_opt(out)[-1] - # check that the float4 cast collapses - store_vals = [u.src[-1] for u in k.uops if u.op is Ops.STORE] - for val in store_vals: - assert val.dtype == dtypes.float.vec(4) # and val.op is not Ops.VECTORIZE - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_arange_opts(self): - a = Tensor.arange(128) - helper_linearizer_opt(a, [ - [Opt(OptOps.GROUP, 0, 32)], - [Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(op=OptOps.LOCAL, axis=0, arg=8)], - [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8)], - [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4)], # noqa: E501 - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_grouped_store_values(self): - x = Tensor.randn((4,3,6,6)).realize() - out = x.flip((0,1)).contiguous() - k = helper_linearizer_opt(out)[-1] - store_val = [u.src[-1] for u in k.uops if u.op is Ops.STORE][0] - assert store_val.dtype == dtypes.float.vec(4) and store_val.op is not Ops.VECTORIZE - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_grouped_store_locals_and_globals(self): - x, y = Tensor.rand(128, 128), Tensor.rand(128, 128) - out = x@y - opt = [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), - Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 2)] # upcast accs in both reduces - k = helper_linearizer_opt(out, opts=[opt])[-1] - def get_recursive(uop): return set.union(set(uop.src), [uop], *[get_recursive(v) for v in uop.src]) - local_stores = [u for u in k.uops if u.op is Ops.STORE and any(x.op is Ops.DEFINE_LOCAL for x in get_recursive(u.src[0]))] - global_stores = [u for u in k.uops if u.op is Ops.STORE and any(x.op is Ops.DEFINE_GLOBAL for x in get_recursive(u.src[0]))] - barrier = [u for u in k.uops if u.op is Ops.BARRIER][0] - # check that the float4 cast collapses for all stores - for store in local_stores+global_stores: - assert store.src[-1].dtype.count > 1 # and store.src[2].op is not Ops.VECTORIZE - # # check the children's vins - # TODO: src ALU are not the same, should it? - # assert barrier.src == tuple(local_stores) - assert len([u for u in k.uops if u.op is Ops.IF and u.src[-1] == barrier]) == 1 - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_grouped_store_local_only(self): - x, y = Tensor.rand(1,128), Tensor.rand(128, 128) - r = (x@y).relu() - k = helper_linearizer_opt(r)[-1] - stores = [u for u in k.uops if u.op is Ops.STORE] - - # the float4 value stores directly in lds and we skip upcast - self.assertEqual(stores[0].src[-1].dtype, dtypes.float.vec(4)) - #assert stores[0].src[-1].op is not Ops.VECTORIZE - - # the global store doesn't change - assert stores[1].src[-1].dtype == dtypes.float - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_skip_unmatching_upcasts(self): - Tensor.manual_seed(0) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(40, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=0, src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(1, 240, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)),)),)) - opt = [ - Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), - Opt(op=OptOps.LOCAL, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2) - ] - k = helper_linearizer_ast(ast, [Tensor.randn(240*40).realize()], opts=[opt])[-1] - out = [u for u in k.uops if u.op is Ops.STORE][0] - assert out.src[-1].op is Ops.VECTORIZE and out.src[-1].dtype == dtypes.float.vec(4) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") - def test_skip_unmatching_upcasts_with_gep(self): - Tensor.manual_seed(0) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(32, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(1, 8, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=1, src=()),)),)),)),)) - opt = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=8), - Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), - Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=2)] - k = helper_linearizer_ast(ast, [Tensor.randn(8*32).realize()], opts=[opt])[-1] - out = [u for u in k.uops if u.op is Ops.STORE][0] - assert out.src[-1].op is Ops.VECTORIZE and out.src[-1].dtype.count != 1 - -@unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need backends that support float4") -class TestFloat4(unittest.TestCase): - @staticmethod - def count_float4(k, n=4): - return (len([uop for uop in k.uops if uop.op is Ops.LOAD and uop.dtype == dtypes.float.vec(n)]), - len([uop for uop in k.uops if uop.op is Ops.STORE and uop.src[-1].dtype == dtypes.float.vec(n)])) - @staticmethod - def count_half4(k): - return (len([uop for uop in k.uops if uop.op is Ops.LOAD and uop.dtype == dtypes.half.vec(4)]), - len([uop for uop in k.uops if uop.op is Ops.STORE and uop.src[-1].dtype == dtypes.half.vec(4)])) - - def test_float4_basic(self): - a = Tensor.empty(2, 8).realize() - b = Tensor.empty(2, 8).realize() - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.apply_opts([Opt(op=OptOps.UPCAST, axis=0, arg=4)]) - k.linearize() - - assert TestFloat4.count_float4(k) == (2, 1) - - @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "CPU with AMX upcasts float up to size 16") - def test_float4_multidim(self): - a = Tensor.empty(2, 8).realize() - b = Tensor.empty(2, 8).realize() - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(0, 4) # float4 dimension - k.shift_to(0, 2, insert_before=k.shape_len-1) - k.upcast() - k.upcast() - k.local_dims += 1 - k.linearize() - - assert TestFloat4.count_float4(k) == (4, 2) - - @unittest.skipUnless(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "Only CPU with AMX upcasts float up to size 16") - def test_float4_multidim_amx(self): - def kernel_for_shape(size, shift): - a = Tensor.empty(2, size).realize() - b = Tensor.empty(2, size).realize() - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(0, 4) - k.shift_to(0, shift, insert_before=k.shape_len-1) - k.upcast() - k.upcast() - k.local_dims += 1 - k.linearize() - return k - - sizes = [12, 8, 16] - shifts = [3, 2, 4] - excepted_upcast_size = [4, 8, 16] - expected_output = [(6,3), (2,1), (2,1)] - - for i in range(len(sizes)): - assert TestFloat4.count_float4(kernel_for_shape(sizes[i], shifts[i]), excepted_upcast_size[i]) == expected_output[i] - - def test_float4_unaligned_load(self): - a = Tensor.empty(9).realize().shrink(((1, 9),)) - b = Tensor.empty(9).realize().shrink(((1, 9),)) - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.apply_opts([Opt(op=OptOps.UPCAST, axis=0, arg=4)]) - k.linearize() - - assert TestFloat4.count_float4(k) == (0, 1) - - @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "CPU with AMX upcasts float up to size 16") - def test_float4_multidim_unaligned_load(self): - a = Tensor.empty(2, 9).realize().shrink(((0, 2), (1, 9),)) - b = Tensor.empty(2, 9).realize().shrink(((0, 2), (1, 9),)) - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(len(k.full_unupcasted_shape)-1, 4) # manual trigger float4 dim - k.upcast() - k.shift_to(len(k.full_unupcasted_shape)-1, 2, insert_before=k.shape_len-1) - k.upcast() - k.local_dims += 1 - k.linearize() - - assert TestFloat4.count_float4(k) == (0, 2) - - @unittest.skipUnless(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "Only CPU with AMX upcasts float up to size 16") - def test_float4_multidim_unaligned_load_amx(self): - def kernel_for_shape(size, shift): - a = Tensor.empty(2, size).realize().shrink(((0, 2), (1, size),)) - b = Tensor.empty(2, size).realize().shrink(((0, 2), (1, size),)) - c = a + b - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(len(k.full_unupcasted_shape)-1, 4) # manual trigger float4 dim - k.upcast() - k.shift_to(len(k.full_unupcasted_shape)-1, shift, insert_before=k.shape_len-1) - k.upcast() - k.local_dims += 1 - k.linearize() - return k - - sizes = [13, 9, 17] - shifts = [3, 2, 4] - excepted_upcast_size = [4, 8, 16] - expected_output = [(0,3), (0,1), (0,1)] - - for i in range(len(sizes)): - assert TestFloat4.count_float4(kernel_for_shape(sizes[i], shifts[i]), excepted_upcast_size[i]) == expected_output[i] - - def test_float4_sometimes_unaligned(self): - a = Tensor.empty(1, 1, 8).realize() - b = Tensor.empty(1, 1, 5).realize().shrink(((0, 1), (0, 1), (1, 5))) - c = a.conv2d(b) - # only the first and last conv dot products are aligned in a, and b is never aligned, so no - # float4 should be emitted (the reduce axis of size 4 is the float4 axis here) - - s = c.schedule()[0] - k = Kernel(s.ast) - k.upcast() - k.linearize() - - assert TestFloat4.count_float4(k) == (0, 0) - - def test_float4_multidim_sometimes_unaligned(self): - a = Tensor.empty(1, 1, 7).realize() - b = Tensor.empty(1, 1, 5).realize().shrink(((0, 1), (0, 1), (1, 5))) - c = a.conv2d(b) - # the first conv dot product is aligned in a. If we upcast the output and reduce - # dimension, then we could do float4 for only that one set of loads, but we currently - # don't. - # UPDATE: now we do this fusion - - s = c.schedule()[0] - k = Kernel(s.ast) - k.upcast() - k.upcast() - k.linearize() - - assert TestFloat4.count_float4(k) in {(0,1), (1,1)} - - def test_float4_noncontiguous(self): - a = Tensor.empty(4, 2).realize() - b = Tensor.empty(4, 2).realize() - c = a + b - - # we will upcast the top axis of sz 4. they should not be coalesced into float4, - # since the top axis is not contiguous. - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(0, 4, top=True) # top axes are float4 axes - k.upcast() - k.linearize() - - assert TestFloat4.count_float4(k) == (0, 0) - - def test_float4_expand(self): - a = Tensor.empty(9).realize().shrink(((1, 9),)) - b = Tensor.empty(2).realize().reshape((2, 1)).expand((2,4)).reshape((8,)) - c = a + b - - # we will upcast the top axis of sz 4. they should not be coalesced into float4, - # since the top axis is not contiguous. - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(0, 4) # float4 axis - k.upcast() - k.linearize() - - assert TestFloat4.count_float4(k) == (0, 1) - - def test_float4_heterogeneous(self): - a = Tensor.empty(8).realize() - b = Tensor.empty(9).realize().shrink(((1, 9),)) - c = a + b - - # should float4 b but not a - - s = c.schedule()[0] - k = Kernel(s.ast) - k.shift_to(0, 4) # float4 axis - k.upcast() - k.linearize() - - assert TestFloat4.count_float4(k) == (1, 1) - - def test_half4_load_unrolled(self): - # from llama 7B shard 4 gpus - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96000), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1), strides=(0, 32000, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96000), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(9216), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1024), strides=(0, 4096, 0, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(9216), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(32768000), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1024), strides=(0, 0, 1024, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(32768000), arg=2, src=()),)),)),)),)),)),)),)) - - # TODO: fix this, expected might change but should be positive - for expected, opts in [ - ((7, 0), [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=3), Opt(op=OptOps.UNROLL, axis=0, arg=4)]), - ((5, 0), [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)]), - ((2, 0), [Opt(op=OptOps.UNROLL, axis=0, arg=4)]), - ]: - k = Kernel(ast) - k.apply_opts(opts) - k.linearize() - count = TestFloat4.count_half4(k) - assert count == expected, f"{count=}, {expected=}" - - @unittest.skip("this doesn't happen anymore") - def test_float4_acc(self): - # from float32 stable diffusion red tinybox - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(33554432), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 1, 1, 1), strides=(0, 0, 262144, 512, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(67108864), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 256, 4, 514, 4, 514), strides=(0, 0, 0, 262144, 0, 512, 0, 1), offset=-513, mask=((0, 1), (0, 1), (0, 1), (0, 256), (0, 4), (1, 513), (0, 4), (1, 513)), contiguous=False), View(shape=(1, 1, 128, 512, 512, 256, 3, 3), strides=(0, 0, 0, 2056, 1, 4227136, 1058840, 515), offset=0, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(67108864), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 256, 3, 3), strides=(0, 0, 2304, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(128), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(128), arg=3, src=()),)),)),)),)),)) - - for expected, opts in [ - (1, [Opt(op=OptOps.UPCAST, axis=2, arg=4)]), - (4, [Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)]), - ]: - k = Kernel(ast) - k.apply_opts(opts) - k.linearize() - count = len([uop for uop in k.uops if uop.op is Ops.DEFINE_ACC and uop.dtype == dtypes.float.vec(4)]) - assert count == expected, f"{count=}, {expected=}" - - @unittest.skip("this doesn't happen anymore") - def test_float2_acc(self): - # from resnet - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(212926464), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 64, 1, 114, 1, 114), strides=(0, 831744, 0, 12996, 0, 114, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(212926464), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4, 6)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(462422016), arg=ShapeTracker(views=(View(shape=(256, 64, 3, 56, 2, 3, 56, 2), strides=(1806336, 28224, 3, 504, 0, 1, 9, 0), offset=0, mask=((0, 256), (0, 64), (0, 3), (0, 56), (0, 1), (0, 3), (0, 56), (0, 1)), contiguous=False), View(shape=(256, 64, 3, 115, 3, 115), strides=(7225344, 112896, 37632, 336, 112, 1), offset=0, mask=((0, 256), (0, 64), (0, 3), (0, 112), (0, 3), (0, 112)), contiguous=False), View(shape=(256, 64, 456, 456), strides=(7617600, 119025, 345, 1), offset=0, mask=((0, 256), (0, 64), (0, 345), (0, 345)), contiguous=False), View(shape=(1, 256, 1, 64, 4, 114, 4, 114), strides=(0, 13307904, 0, 207936, 51984, 456, 114, 1), offset=0, mask=None, contiguous=True))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(462422016), arg=1, src=()),)),)),)),)),)),)),)) - for expected, opts in [ - (16, [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=3, arg=4)]), # noqa: E501 - (4, [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=2)]), - ]: - k = Kernel(ast) - k.apply_opts(opts) - k.linearize() - count = len([uop for uop in k.uops if uop.op is Ops.DEFINE_ACC and uop.dtype == dtypes.float.vec(2)]) - assert count == expected, f"{count=}, {expected=}" - -class TestHandCodedOpts(unittest.TestCase): - def test_masked_upcast(self): - layer_1 = Tensor.cat(*[Tensor.empty(5) for _ in range(4)]) - layer_2 = Tensor.cat(layer_1.unsqueeze(0), Tensor.empty(6, 20)) - - s = layer_2.schedule()[-1] - k = Kernel(s.ast) - k.apply_opts(hand_coded_optimizations(k)) - assert len(k.bufs) == 6 # make sure all ops are done in one kernel - # masked upcast should upcast masked axis of size 7 - # masked upcast should not upcast large (20) last axis - # float4/other hcopt shouldn't upcast last axis, since we already have 7 upcast, and the last axis is not very contiguous - assert k.upcasted == 1 and k.full_shape[-1] == 7 - - @unittest.skipIf(Device.DEFAULT in {"METAL", "WEBGPU"}, "METAL/WEBGPU split this kernel since it has 37 buffers") - def test_masked_upcast_wino(self): - monster = Tensor.stack(*[Tensor.stack(*[Tensor.empty(16) for _ in range(6)]) for _ in range(6)]) - - s = monster.schedule()[-1] - k = Kernel(s.ast) - k.apply_opts(hand_coded_optimizations(k)) - assert len(k.bufs) == 37 # make sure all ops are done in one kernel - # should upcast the two Tensor.stacks - assert k.upcasted >= 2 and k.full_shape[k.shape_len-k.upcasted:k.shape_len].count(6) == 2 - - def test_masked_upcast_wino_full(self): - with Context(WINO=1): - x,w = Tensor.rand(1,4,8,8, requires_grad=True).realize(), Tensor.rand(4,4,3,3, requires_grad=True).realize() - out = Tensor.conv2d(x,w, padding=1) - out.mean().backward() - - upcasts = [] - wino_schedule = out.schedule() - # collect upcasts of tile transform kernels - for i, si in enumerate(wino_schedule): - k = Kernel(si.ast) - k.apply_opts(hand_coded_optimizations(k)) - if k.reduceop is not None: continue # not a tile transform kernel (there is a gemm reduce kernel) - if len(k.bufs) < 22: continue # not a tile transform kernel (there's a permute kernel at the end) - upcasts.append(tuple(k.full_shape[k.shape_len - k.upcasted:k.shape_len])) - assert len(upcasts) == 3 # 3 transformation matrices - assert len(wino_schedule) <= 4 # 4 kernels - # this test case's inputs are too small, so one of the 4-stacks became a local, which is fine i guess - assert upcasts.count((6, 6)) == 2 #and upcasts.count((4, 4)) == 1 - - backward_schedule = Tensor.schedule(x.grad, w.grad) - for si in backward_schedule: - k = Kernel(si.ast) - k.apply_opts(hand_coded_optimizations(k)) - k.linearize() - if len(k.bufs) < 20: continue # not a tile transform kernel - # heuristic number to make sure that at least some upcasts but not too many upcasts are being done - assert 6 <= prod(k.full_shape[k.shape_len - k.upcasted:k.shape_len]) <= 216 - assert len(backward_schedule) <= 13 # just the current number, but it could be better - - def test_masked_upcast_many(self): - layer_1 = Tensor.cat(Tensor.rand(3, 4), Tensor.rand(4, 4)) - layer_2 = Tensor.cat(layer_1.unsqueeze(0), Tensor.rand(6, 7, 4)) - layer_3 = Tensor.cat(layer_2.unsqueeze(0), Tensor.rand(6, 7, 7, 4)) - - k = helper_linearizer_opt(layer_3)[-1] - assert len(k.bufs) == 5 # make sure all ops are done in one kernel - # check that we don't do too many upcasts - assert prod(k.full_shape[k.shape_len-k.upcasted:k.shape_len]) <= 49 - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - def test_matvec(self): - N = 128 - a = Tensor.rand(1, N).realize() - b = Tensor.rand(N, N).realize() - c = a @ b - - k = helper_linearizer_opt(c)[-1] - - assert k.group_for_reduces == 1 - assert k.local_dims == 1 - assert k.upcasted == 1 - -def helper_linearizer_ast(ast:UOp, inputs:list[Tensor], *args, **kwargs): - assert isinstance(ast, UOp), "ast must be UOp" - inbufs = [x.uop.base.buffer for x in inputs] - outbufs = [Buffer(inbufs[-1].device if inbufs else Device.DEFAULT, out.st_arg.size, out.src[1].dtype).allocate() \ - for out in ast.src] - return _helper_linearizer_opt_ast(ast, outbufs+inbufs, *args, **kwargs) - -def helper_linearizer_opt(r:Union[Tensor, list[Tensor]], *args, **kwargs): - realized_ast, real_bufs = helper_realized_ast(r) - return _helper_linearizer_opt_ast(realized_ast, real_bufs, *args, **kwargs) - -def copyout_outputs(lin:Kernel, outbufs:list[Buffer]) -> list[np.ndarray]: - ret = [] - for i,x in enumerate(outbufs): - shape: tuple[int, ...] = lin.ast.src[i].st_arg.shape - ret.append(np.frombuffer(x.as_buffer(), _to_np_dtype(x.dtype)).reshape(shape)) - return ret - -def reset_bufs(bufs:list[Buffer]): - for buf in bufs: buf.copyin(np.zeros((buf.size, ), dtype=_to_np_dtype(buf.dtype)).data) # Zero to check that all values are filled - -def _helper_linearizer_opt_ast(realized_ast:UOp, real_bufs:list[Buffer], opts=[], - apply_tc=False, atol=1e-4, rtol=1e-4, color_sizes=[], wanna_output=[]) -> list[Kernel]: - lins: list[Kernel] = [] - outbufs = [real_bufs[x.src[0].base.arg] for x in realized_ast.src] - device = real_bufs[0].device - - def get_prg(k:Kernel): return CompiledRunner(replace(k.to_program(), device=device)) - - def check_opt(opts, create_k, expected_color_size): - k = create_k() - lins.append(k) - if apply_tc: - assert k.apply_tensor_cores(1, extra_opts=opts), "no tensor core triggered" - else: - k.apply_opts(opts) - if expected_color_size is not None: - cs = list(zip(k.colors(), k.full_shape)) - assert cs == expected_color_size, f"expected={expected_color_size} got={cs}" - prg = get_prg(k) - reset_bufs(outbufs) - prg.exec(real_bufs) - - for x,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(x, want, atol=atol, rtol=rtol) - - # Get baseline if it is not provided, which is not optimized at all. - k = Kernel(realized_ast) - lins.append(k) - prg = get_prg(k) - prg.exec(real_bufs) - if len(wanna_output) == 0: wanna_output = copyout_outputs(k, outbufs) - else: - for buf,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(buf, want, atol=atol, rtol=rtol) - - # Check correctness of handcoded optimiztions. - k = Kernel(realized_ast) - k.apply_opts(hand_coded_optimizations(k)) - lins.append(k) - prg = get_prg(k) - reset_bufs(outbufs) - prg.exec(real_bufs) - for buf,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(buf, want, atol=atol, rtol=rtol) - for i,x in enumerate(opts): # Check custom transformations if any. - check_opt(x, lambda: Kernel(realized_ast), color_sizes[i] if i < len(color_sizes) else None) - return lins - -class TestKernelOpts(unittest.TestCase): - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_local_and_grouped_reduce(self): - N = 128 - Tensor.manual_seed(1882) - a = Tensor.rand(4, 4, N, N) - b = Tensor.rand(4, 4, N) - r = (b.sqrt() + ((a+1).sum(axis=3).exp())) - helper_linearizer_opt(r, [ - [Opt(OptOps.LOCAL, 0, 2)], - [Opt(OptOps.LOCAL, 0, 8)], - [Opt(OptOps.LOCAL, 0, 16)], # Checking how it works with locals - [Opt(OptOps.GROUPTOP, 0, 2)], - [Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.GROUPTOP, 0, 64)], # Checking how it works with grouped reduce - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 2)], - [Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.GROUPTOP, 0, 16)], - [Opt(OptOps.LOCAL, 0, 32), Opt(OptOps.GROUPTOP, 0, 2)], - # Checking how it works with locals + grouped reduce - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 64)], - # Checking how it works with locals + grouped reduce + upcasts - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.UPCAST, 0, 8), Opt(OptOps.UNROLL, 1, 4)], - # many local + many group - [Opt(OptOps.GROUP, 0, 2)] * 4, - [Opt(OptOps.LOCAL, 0, 2)] * 4, - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUP, 0, 2)] * 4, - ]) - - def test_upcasts(self): - N = 16 - Tensor.manual_seed(1772) - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - r = (a+b).sqrt() * ((a+1).exp()) - helper_linearizer_opt(r, [ - [Opt(OptOps.UPCAST, 0, 2)], - [Opt(OptOps.UPCAST, 0, 4)], - [Opt(OptOps.UPCAST, 0, 8)], # Checking how it works with upcasts - ]) - - def test_full_upcast(self): - Tensor.manual_seed(1772) - a = Tensor.rand(4) - b = Tensor.rand(4) - r = (a+b).sqrt() * ((a+1).exp()) - helper_linearizer_opt(r, [ - [Opt(OptOps.UPCAST, 0, 4)], # Checking how it works with upcasts - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_matmul(self): - N = 128 - Tensor.manual_seed(1552) - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - r = a@b - helper_linearizer_opt(r, [ - [Opt(OptOps.UPCAST, 0, 2)], - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4)], # Checking how it works with upcasts - [Opt(OptOps.LOCAL, 0, 2)], - [Opt(OptOps.LOCAL, 1, 32)], - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4)], - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 32)], - [Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.LOCAL, 1, 8)], # Checking how it works with locals - [Opt(OptOps.GROUPTOP, 0, 2)], - [Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.UNROLL, 0, 4)], # Checking how it works with grouped_reduce - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.LOCAL, 0, 8), Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 8), Opt(OptOps.GROUPTOP, 0, 4)], # Checking how it works with local+grouped_reduce - # Checking all together - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4), - Opt(OptOps.UPCAST, 1, 2)], - # Full global upcast + local - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 8)], - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_double_reduce(self): - N = 128 - Tensor.manual_seed(1552) - a = Tensor.rand(8, N, 8, N) - r = a.sum(axis=(1,3)) - helper_linearizer_opt(r, [ - # openCL / GPU=1 is 256 max threads - [Opt(OptOps.GROUPTOP, 0, 2)], [Opt(OptOps.GROUPTOP, 0, 32)], - [Opt(OptOps.GROUPTOP, 1, 2)], [Opt(OptOps.GROUPTOP, 1, 32)], # Checking how it works with 1 grouped_reduce. - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], - [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 2)], - [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 64)], # Checking how it works with 2 grouped_reduces. - [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 0, 4)], - [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 32), Opt(OptOps.UNROLL, 2, 4)], # Checking how it works with 2 grouped_reduces + upcasts. - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4)], - # Checking how it works with 2 grouped_reduces + upcasts + locals. - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 32), Opt(OptOps.UNROLL, 1, 4)], - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2)], - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2), - Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], # Checking how it works with 2 grouped_reduces + upcasts + locals. - [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2), - Opt(OptOps.UPCAST, 0, 2)], # No globals - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - def test_invalid_tensor_core_extra_opts(self): - N = 128 - Tensor.manual_seed(1552) - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - realized_ast, _ = helper_realized_ast(a@b) - invalid_opts = [ - [Opt(OptOps.LOCAL, 2, 2)], - [Opt(OptOps.UPCAST, 2, 2)], - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 2, 2)], - ] - for x in invalid_opts: - k = Kernel(realized_ast) - with self.assertRaises(AssertionError): - assert k.apply_tensor_cores(use_tensor_cores=1, extra_opts=x), "no valid tensor core" # for METAL in runners - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_buf_index_not_found_tensor_core(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(1, 256), strides=(0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(256), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(256), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1243), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1243), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1243), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1243), arg=3, src=()),)),)),)),)),)),)) - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - with self.assertRaises(KernelOptError): - k.apply_opt(Opt(OptOps.TC, 0, (-1, 1, 1))) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_tensor_core_opts(self): - N = 128 - Tensor.manual_seed(1552) - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - # bf16 buffer returns float32 numpy outputs so test would fail. testing opt with half suffices. - if tc.dtype_in != dtypes.half and tc.dtype_out != dtypes.half: continue - a, b = Tensor.rand(N, N, dtype=tc.dtype_in), Tensor.rand(N, N, dtype=tc.dtype_in) - r = a.matmul(b, dtype=tc.dtype_out) - (atol, rtol) = ((0.25, 0.01) if tc.dtype_out == dtypes.half else (3e-2, 1e-3)) if tc.dtype_in == dtypes.half else (1e-4, 1e-4) - helper_linearizer_opt(r, [ - [], - [Opt(OptOps.UPCAST, 0, 4)], - [Opt(OptOps.UPCAST, 1, 4)], - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4)], # check upcasts - [Opt(OptOps.UNROLL, 0, 2)], # check unroll - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 2)], # check combo of unroll and local - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 2)], - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 4)], - [Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UPCAST, 0, 4)], # check permutations - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 0, 4)], - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 1, 4)], - [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], - # [Opt(OptOps.GROUP, 0, 2)] # doesn't work because group_for_reduce dims become early locals (conflicting with TC) - ], apply_tc=True, atol=atol, rtol=rtol) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - def test_tensor_core_opts_locals(self): - N = 128 - Tensor.manual_seed(1552) - for tc in Device[Device.DEFAULT].renderer.tensor_cores: - # bf16 buffer returns float32 numpy outputs so test would fail. testing opt with half suffices. - if tc.dtype_in != dtypes.half and tc.dtype_out != dtypes.half: continue - a, b = Tensor.rand(N, N, dtype=tc.dtype_in), Tensor.rand(N, N, dtype=tc.dtype_in) - r = a.matmul(b, dtype=tc.dtype_out) - (atol, rtol) = ((0.25, 0.01) if tc.dtype_out == dtypes.half else (3e-2, 1e-3)) if tc.dtype_in == dtypes.half else (1e-4, 1e-4) - helper_linearizer_opt(r, [ - [Opt(OptOps.UNROLL, 0, 0)], # check full unroll of reduce with locals - [Opt(OptOps.LOCAL, 0, 4)], # check local - [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.LOCAL, 0, 2)], - [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 0, 4)], - ], apply_tc=True, atol=atol, rtol=rtol) - - def test_padto_matmul(self): - if (CI and Device.DEFAULT in ["AMD", "NV", "CUDA"]): - self.skipTest("super slow on CUDA and AMD because of the big grid dims") - N = 17 * 17 - Tensor.manual_seed(289) - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - helper_linearizer_opt(a@b, [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 1, 32)], - [Opt(OptOps.PADTO, 2, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32), Opt(OptOps.PADTO, 2, 32)], - # can optimize further post PADTO - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32), Opt(OptOps.UPCAST, 0, 2), Opt(OptOps.UPCAST, 1, 2),], - ]) - - def test_padto_upcasted_not_ok(self): - N = 4 - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - helper_linearizer_opt(a@b, [ - [Opt(OptOps.UPCAST, 0, 0)], - [Opt(OptOps.UPCAST, 1, 0)], - [Opt(OptOps.UNROLL, 0, 0)], - [Opt(OptOps.PADTO, 0, 8)], - [Opt(OptOps.PADTO, 1, 8)], - [Opt(OptOps.PADTO, 2, 8)], - ]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a@b, [[Opt(OptOps.UPCAST, 0, 0), Opt(OptOps.PADTO, 2, 8)]]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a@b, [[Opt(OptOps.UPCAST, 1, 0), Opt(OptOps.PADTO, 2, 8)]]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a@b, [[Opt(OptOps.UNROLL, 0, 0), Opt(OptOps.PADTO, 2, 8)]]) - - def test_padto_sum_ok(self): - N = 18 * 18 - # NOTE: this setup prevents 17 * 17 contiguous merged into one dimension - a = Tensor.rand(N, N).realize().shrink(((0, 17), (0, 17))) * 100 - b = (Tensor.rand(N, N) < 0.5).realize().shrink(((0, 17), (0, 17))) - - helper_linearizer_opt(a.sum(0), [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - helper_linearizer_opt(a.sum(1), [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - - # can pad sum reduce axis if there's no unsafe ops prior to sum - for axis in (0, 1): - helper_linearizer_opt(a.sum(), [[Opt(OptOps.PADTO, axis, 32)],]) - helper_linearizer_opt(a.sum(0), [[Opt(OptOps.PADTO, axis, 32)],]) - helper_linearizer_opt(b.sum(), [[Opt(OptOps.PADTO, axis, 32)],]) - helper_linearizer_opt(b.sum(0), [[Opt(OptOps.PADTO, axis, 32)],]) - helper_linearizer_opt(b.sum(dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) - # TODO: why? - if Device.DEFAULT != "WEBGPU": - helper_linearizer_opt(b.sum(0, dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) - helper_linearizer_opt(b.sum(1, dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) - - # having unsafe ops after sum is fine - helper_linearizer_opt(a.sum().exp(), [[Opt(OptOps.PADTO, 0, 32)],]) - helper_linearizer_opt(a.sum(0).exp(), [[Opt(OptOps.PADTO, 1, 32)],]) - - def test_padto_sum_not_ok(self): - N = 18 * 18 - # NOTE: this setup prevents 17 * 17 contiguous merged into one dimension - a = Tensor.rand(N, N).shrink(((0, 17), (0, 17))).exp() - # exp is not safe to pad - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a.exp().sum(), [[Opt(OptOps.PADTO, 0, 32)],]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a.exp().sum(0), [[Opt(OptOps.PADTO, 1, 32)],]) - - b = a < 1 - # lt is not safe to pad - with self.assertRaises(KernelOptError): - helper_linearizer_opt(b.sum(), [[Opt(OptOps.PADTO, 0, 32)],]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(b.sum(0), [[Opt(OptOps.PADTO, 1, 32)],]) - - def test_padto_max(self): - N = 18 * 18 - # NOTE: this setup prevents 17 * 17 contiguous merged into one axis - a = -Tensor.rand(N, N).shrink(((0, 17), (0, 17))) * 100 - - helper_linearizer_opt(a.max(0), [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - helper_linearizer_opt(a.max(1), [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - - # cannot pad max kernel on reduce - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a.max(), [[Opt(OptOps.PADTO, 0, 32)],]) - with self.assertRaises(KernelOptError): - helper_linearizer_opt(a.max(0), [[Opt(OptOps.PADTO, 1, 32)],]) - - def test_padto_where(self): - Tensor.manual_seed(0) - N = 17 * 17 - a = (Tensor.randn(N, N).realize().max(axis=0, keepdim=True) > 1).where(1, 0) - helper_linearizer_opt(a.max(0), [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - - def test_padto_where_multioutput(self): - Tensor.manual_seed(0) - N = 17 * 17 - r = Tensor.randn(N, N).realize().max(axis=0, keepdim=True) > 1 - a0 = r.where(1, 0) - a1 = r.where(2, 0) - helper_linearizer_opt([a0.max(0), a1.max(0)], [ - [Opt(OptOps.PADTO, 0, 32)], - [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_padto_group(self): - Tensor.manual_seed(0) - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),))),)) # noqa: E501 - ld1 = UOp(Ops.LOAD, dtypes.float, src=(g2.view(ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),))),)) # noqa: E501 - store = UOp(Ops.STORE, src=(g0.view(ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),))), UOp(Ops.REDUCE_AXIS, dtypes.float, (ld0*ld1,), (Ops.ADD, (0, 2, 4, 6)),))) # noqa: E501 - sink = UOp(Ops.SINK, src=(store,)) - data1 = Tensor.randn(2, 1, 4, 1, 3, 4, 2, 6, 1, 3).realize() - data2 = Tensor.randn(2, 1, 4, 1, 3, 4, 2, 6, 1, 3).realize() - helper_linearizer_ast(sink, [data1, data2], opts=[ - #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.GROUP, 0, 4)], - #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8)], - #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8), Opt(OptOps.GROUP, 0, 4)] - ]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") - def test_color_shapes_with_local(self): - N = 32 - Tensor.manual_seed(1552) - a = Tensor.rand(N, N) - b = Tensor.rand(N, N) - r = a@b - opts_shapes = [ - ([Opt(OptOps.LOCAL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("red",32)]), - ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 2)], [("blue",16),("blue",32),("cyan",2),("green",2),("red",16)]), - # check to ensure local_dims are stable for full UNROLL of first_reduce - ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), - ([Opt(OptOps.UNROLL, 0, 0),Opt(OptOps.LOCAL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), - # check behavior for full UNROLL on an existing GROUP - ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 0),Opt(OptOps.UNROLL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("green",16),("magenta",2)]), - ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 0),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), - ([Opt(OptOps.GROUP, 0, 0),Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), - ([Opt(OptOps.GROUP, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",32),("blue",32),("red",16),("magenta",2)]), - ] - helper_linearizer_opt(r, [x[0] for x in opts_shapes], color_sizes=[x[1] for x in opts_shapes]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_linearizer_dumb.py b/tinygrad/test/test_linearizer_dumb.py deleted file mode 100644 index 0c56dc9e..00000000 --- a/tinygrad/test/test_linearizer_dumb.py +++ /dev/null @@ -1,199 +0,0 @@ -# ruff: noqa: E501 -# tests where the Linearizer is doing something dumb -# like test_linearizer_failures, but they don't have to fail - -import unittest -from tinygrad import Device, dtypes -from tinygrad.device import is_dtype_supported -from tinygrad.uop.ops import UOp, Ops -from tinygrad.helpers import getenv -from tinygrad.shape.shapetracker import ShapeTracker, View -from tinygrad.engine.search import Opt, OptOps -from tinygrad.codegen.kernel import Kernel - -class TestLinearizerDumb(unittest.TestCase): - @unittest.skipUnless(Device.DEFAULT == "METAL", "only tested on METAL") - def test_unmerged_ifs(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1605632), arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 1, 1, 1), strides=(25088, 0, 49, 7, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1605632), arg=0, src=()),)), - UOp(Ops.MAX, dtypes.half, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1605632), arg=ShapeTracker(views=(View(shape=(1, 64, 1, 512, 4, 9, 4, 9), strides=(0, 25088, 0, 49, 0, 7, 0, 1), offset=-8, mask=((0, 1), (0, 64), (0, 1), (0, 512), (0, 4), (1, 8), (0, 4), (1, 8)), contiguous=False), View(shape=(64, 1, 512, 7, 7, 512, 3, 3), strides=(663552, 0, 0, 36, 1, 1296, 360, 10), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1605632), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(2359296), arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 512, 3, 3), strides=(0, 0, 4608, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2359296), arg=2, src=()),)),)),)),)),)),)), - UOp(Ops.CONST, dtypes.half, arg=0.9999950000374996, src=( - x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.CONST, dtypes.half, arg=0.0, src=( - x16,)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=0)] - k = Kernel(ast, opts=Device["METAL"].renderer) - k.apply_opts(opts) - prg = k.to_program() - print(prg.src) - Device[Device.DEFAULT].compiler.compile_cached(prg.src) - gate_count = len([x for x in prg.src.splitlines() if "if" in x]) - assert gate_count == 1, f"must have only one gate {gate_count} != 1" - assert len([u for u in k.uops if u.op is Ops.IF]) == 1, "must have a single IF" - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "need local") - def test_max_simplify_and_cancel(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1000), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1000), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1000), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1000), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x14:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1001, 1999), strides=(0, 0), offset=0, mask=((0, 1001), (999, 1999)), contiguous=False), View(shape=(1000, 1000), strides=(1, 2000), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1000, 1000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x21,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=1000, src=( - x14,)),)),)),)),)) - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8)] - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - k.apply_opts(opts) - prg = k.to_program() - print(prg.src) - assert prg.uops is not None and not any(uop.op is Ops.MAX for uop in prg.uops), "leftover MAX" - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "need local") - def test_expander_new_srcs(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)] - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - k.apply_opts(opts) - prg = k.to_program() - print(prg.src) - if_uops = [u for u in k.uops if u.op is Ops.IF] - self.assertIn(len(if_uops), {1,2,3}) - conditions = if_uops[0].src[0].toposort() - self.assertLessEqual(len(conditions), 9) - - # this was a bug in embedding, someday we should fold this anyway - @unittest.skipUnless(is_dtype_supported(dtypes.half), f"half dtype not supported on {Device.DEFAULT}") - def test_llama_embedding(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(4096), arg=ShapeTracker(views=(View(shape=(4096, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(4096), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32001, 63999), strides=(0, 0), offset=0, mask=((0, 32001), (31999, 63999)), contiguous=False), View(shape=(4096, 32000, 32000), strides=(0, 1, 64000), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4096, 32000, 32000), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x16,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x19:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x19,)),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(131072000), arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(1, 4096, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(131072000), arg=2, src=()),)),)),)),)),)),)),)),)) - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - prg = k.to_program() - print(prg.src) - - @unittest.expectedFailure - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need float4") - def test_unrolled_float4_align(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 1)), src=( - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.long, arg=None, src=( - UOp(Ops.VIEW, dtypes.long.ptr(18), arg=ShapeTracker(views=(View(shape=(3, 6), strides=(6, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.long.ptr(18), arg=1, src=()),)),)), - UOp(Ops.CONST, dtypes.long, arg=-1, src=( - x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(3, 6), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x11,)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x11,)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(18), arg=ShapeTracker(views=(View(shape=(3, 6), strides=(6, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=0)] - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - k.apply_opts(opts) - prg = k.to_program() - print(prg.src) - load_idxs = [x.src[1] for x in k.uops if x.op is Ops.LOAD and x.src[0].arg == 2] - assert load_idxs[0] < load_idxs[1], f"first loaded idx {load_idxs[0].arg} then {load_idxs[1].arg}!" - - @unittest.expectedFailure - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need float4") - @unittest.skipIf(getenv("PTX"), "this is somehow correct in PTX") - def test_upcasted_stores_out_of_order(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9360), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 1, 1, 4, 3, 3), strides=(2340, 468, 36, 0, 0, 0, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9360), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(144), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 4, 1, 4, 3, 3), strides=(0, 0, 0, 0, 0, 0, 1, 0, 4, 48, 16), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(144), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1040), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 4, 1, 4, 3, 3), strides=(260, 13, 1, 0, 0, 0, 65, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1040), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=0)] - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - k.apply_opts(opts) - prg = k.to_program() - print(prg.src) - store_idxs = [x.src[1] for x in k.uops if x.op is Ops.STORE] - for i in range(len(store_idxs) - 1): - first_bounds = store_idxs[i].vmin+store_idxs[i].vmax - next_bounds = store_idxs[i+1].vmin+store_idxs[i+1].vmax - assert first_bounds < next_bounds, f"first stored (max) idx {first_bounds} then {next_bounds}!" - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_linearizer_failures.py b/tinygrad/test/test_linearizer_failures.py deleted file mode 100644 index ec4f2ae6..00000000 --- a/tinygrad/test/test_linearizer_failures.py +++ /dev/null @@ -1,1727 +0,0 @@ -# ruff: noqa: E501 -import unittest, random -import numpy as np -from tinygrad.codegen.kernel import Kernel, KernelOptError -from tinygrad.device import is_dtype_supported -from tinygrad.uop.ops import UOp, Ops -from tinygrad.engine.search import Opt, OptOps -from tinygrad import Device, dtypes, Tensor -from tinygrad.helpers import CI, Context -from test.external.fuzz_linearizer import compare_linearizer - -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -def helper_test_lin(lin: Kernel, opts, failed_platforms, rtol=1e-2, atol=1e-2): - if any(b.dtype.base == dtypes.half for b in lin.membufs) and not is_dtype_supported(dtypes.half): return - if any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) and not is_dtype_supported(dtypes.bfloat16): return - - try: - lin.apply_opts(opts) - except KernelOptError: - # it's considered fixed if we invalidated the opts - assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" - return - - compare_result = compare_linearizer(lin, rtol=rtol, atol=atol) - if compare_result[0] in ["PASS", "KernelOptError"]: - # it's considered fixed if we invalidated the opts - assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" - else: - assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {compare_result[0]}" - return lin - -@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "failed on CUDA CI") -class TestLinearizerFailures(unittest.TestCase): - def setUp(self): - random.seed(42) - np.random.seed(42) - Tensor.manual_seed(42) - - def test_failure_1(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 16), strides=(16, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - x8:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=1, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - x8,)),)),)),)),)) - helper_test_lin(Kernel(ast), [], failed_platforms=[]) - - def test_failure_2(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(21312), arg=ShapeTracker(views=(View(shape=(32, 2, 37, 9, 1, 1), strides=(666, 333, 9, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(21312), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (4, 5)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(197119), arg=ShapeTracker(views=(View(shape=(32, 2, 111, 27), strides=(6160, 3080, 28, 1), offset=0, mask=((0, 32), (0, 2), (0, 110), (0, 27)), contiguous=False), View(shape=(32, 2, 37, 9, 2, 2), strides=(5994, 2997, 81, 3, 27, 1), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(197119), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=0, arg=32)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_3(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(32, 8, 16, 1), strides=(128, 16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(65536), arg=ShapeTracker(views=(View(shape=(32, 8, 16, 16), strides=(2048, 256, 16, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(65536), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=0, arg=32)] - # METAL: AssertionError: Error Domain=AGXMetalG13X Code=3 "Threadgroup memory size (65536) exceeds the maximum threadgroup memory allowed (32768)" UserInfo={NSLocalizedDescription=Threadgroup memory size (65536) exceeds the maximum threadgroup memory allowed (32768)} - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_5(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.CONST, dtypes.float, arg=0.1464405059814453, src=( - x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 1, 4, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x8,)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 1, 4, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=1, src=()),)),)),)), - x5,)),)),)),)) - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] - # EXEC_ERROR, it has no global_size - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_6(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(10), arg=ShapeTracker(views=(View(shape=(10, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(10), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(10, 10), strides=(1, 20), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=10, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0)] - # COMPILE FAILED, KeyError: Ops.CONST - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_7(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(18939904), arg=ShapeTracker(views=(View(shape=(512, 32, 1, 34, 1, 34), strides=(36992, 1156, 0, 34, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18939904), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 4)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(37748736), arg=ShapeTracker(views=(View(shape=(512, 32, 6, 8, 4, 6, 8, 4), strides=(2048, 64, 6291456, 8, 0, 1048576, 1, 0), offset=0, mask=((0, 512), (0, 32), (0, 6), (0, 8), (0, 1), (0, 6), (0, 8), (0, 1)), contiguous=False), View(shape=(512, 32, 6, 35, 6, 35), strides=(1179648, 36864, 6144, 192, 32, 1), offset=0, mask=((0, 512), (0, 32), (0, 6), (0, 32), (0, 6), (0, 32)), contiguous=False), View(shape=(512, 32, 238, 238), strides=(1411200, 44100, 210, 1), offset=0, mask=((0, 512), (0, 32), (0, 210), (0, 210)), contiguous=False), View(shape=(512, 32, 7, 34, 7, 34), strides=(1812608, 56644, 8092, 238, 34, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(37748736), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4)] - # test/test_linearizer_failures.py Fatal Python error: Segmentation fault - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_8(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), - UOp(Ops.SQRT, dtypes.float, arg=None, src=( - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - x9:=UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(1, 1, 4096), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(1, 1, 4096), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=2, src=()),)),)),)), - x9,)),)), - UOp(Ops.CONST, dtypes.float, arg=0.000244140625, src=( - x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1e-06, src=( - x17,)),)),)),)),)),)) - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - # fatal error: bracket nesting level exceeded maximum of 256 - # note: use -fbracket-depth=N to increase maximum nesting level - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_9(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(13500), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 0, 0, 4500, 0, 0, 0, 0, 900, 60, 12, 4, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13500), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(1, 2, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9000), arg=ShapeTracker(views=(View(shape=(1, 2, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 4500, 0, 0, 0, 0, 0, 0, 900, 60, 12, 4, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9000), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_10(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(50257), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 50257), strides=(0, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(50257), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(51463168), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 50257), strides=(0, 0, 1, 1024), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51463168), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=3, src=()),)),)),)),)),)) - helper_test_lin(Kernel(ast), [], failed_platforms=[]) - - def test_failure_11(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(1, 64, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=0, src=()),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1179648), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True),)), src=( - x12:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1179648), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - x15:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - x20:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=3, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x17,)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)), - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1179648), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - x12,)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - x15,)),)),)), - x39:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x40:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - x20,)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x40,)),)), - UOp(Ops.SQRT, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(64,), strides=(1,), offset=0, mask=None, contiguous=True), View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=4, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=5.425347222222222e-05, src=( - x53:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64,), strides=(0,), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( - x53,)),)),)),)),)),)), - x39,)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=5, src=()),)),)),)),)),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=6, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=7, src=()),)),)),)),)),)),)),)),)) - helper_test_lin(Kernel(ast), [], failed_platforms=[]) - - def test_failure_12(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=1, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), - x5,)),)),)),)) - opts = [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.GROUP, axis=0, arg=4)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - # both kernels are correct from a code standpoint, but generate different results due to precision errors (switching to float results in output matches) - def test_failure_13(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(768), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(103728), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 51864), strides=(51864, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(103728), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(19915776), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 51864), strides=(0, 0, 1, 384), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(19915776), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(19968), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(0, 0, 1, 0), offset=19584, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(19968), arg=3, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=4)] - helper_test_lin(Kernel(ast), opts, failed_platforms=["METAL", "GPU", "CUDA"]) - - def test_failure_14(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=1, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), - x5,)),)),)),)) - opts = [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)] - # COMPILE_ERROR on METAL in fuzz_linearizer: unused variables and undeclared variables - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_15(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(21952), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 196, 14, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(21952), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(94080), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 480, 1, 1), strides=(0, 0, 0, 14, 1, 196, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(94080), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(53760), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 480, 1, 1), strides=(0, 0, 480, 0, 0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(53760), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=3, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=4, src=()),)),)),)), - UOp(Ops.SQRT, dtypes.float, arg=None, src=( - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=5, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=6, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=16)] - # COMPILE_ERROR on METAL in fuzz_linearizer ast 115: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_16(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(13), arg=ShapeTracker(views=(View(shape=(1, 13, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(13312), arg=ShapeTracker(views=(View(shape=(1, 13, 1024), strides=(0, 1024, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13312), arg=1, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0009765625, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 13, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4)] - # COMPILE_ERROR on METAL/GPU (probably HIP/CUDA too) in fuzz_linearizer ast 154: bracket nesting level exceeded maximum of 256 - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_17(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(62720), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 1, 28, 28, 1, 1), strides=(31360, 0, 784, 0, 28, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(62720), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 240, 28, 28, 1, 1), strides=(0, 0, 1, 40, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(376320), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 240, 28, 28, 1, 1), strides=(188160, 0, 0, 784, 28, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(376320), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.GROUPTOP, axis=0, arg=16), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=1, arg=4)] - # COMPILE_ERROR on METAL in fuzz_linearizer ast 178: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_18(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(768), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(768), arg=1, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(3072), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1536), strides=(1536, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3072), arg=2, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(589824), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1536), strides=(0, 0, 1536, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(589824), arg=3, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(384), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(384), arg=4, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUPTOP, axis=0, arg=256), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=3)] - # COMPILE_ERROR on METAL in fuzz_linearizer ast 239: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_19(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4536), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 9, 7, 3, 3), strides=(2268, 0, 567, 0, 63, 9, 3, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4536), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(144), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 4, 9, 7, 3, 3), strides=(0, 0, 36, 9, 0, 0, -3, -1), offset=8, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(144), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(504), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 4, 9, 7, 3, 3), strides=(252, 0, 0, 63, 7, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(504), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=7), Opt(op=OptOps.UPCAST, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=3)] - # COMPILE_ERROR on METAL in fuzz_linearizer ast 379: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_20(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(4, 4), strides=(4, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4), arg=ShapeTracker(views=(View(shape=(4, 4), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4), arg=1, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 4), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_21(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(2925), arg=ShapeTracker(views=(View(shape=(45, 65), strides=(65, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(2925), arg=0, src=()),)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(45, 65), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)) - opts = [Opt(op=OptOps.PADTO, axis=0, arg=32)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - #@unittest.skipIf(Device.DEFAULT in ("LLVM", "METAL", "CPU"), "flaky") - @unittest.skip("flaky everywhere") - def test_failure_22(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - x4:=UOp(Ops.CONST, dtypes.float, arg=0.000244140625, src=( - x5:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(393216), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(393216), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=2, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=3, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=4, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=5, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=6, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=7, src=()),)),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=8, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=9, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=10, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=11, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=12, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=13, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=14, src=()),)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=15, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(544301), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 17280, 180, 18, 1), offset=19, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(544301), arg=16, src=()),)),)),)),)),)),)),)),)),)),)),)),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=17, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=2.0, src=( - x5,)),)),)),)), - x79:=UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=18, src=()),)),)), - x4,)), - UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( - x5,)),)),)),)), - x79,)),)),)),)) - opts = [] - helper_test_lin(Kernel(ast), opts, failed_platforms=["METAL", "CUDA"]) - - def test_failure_23(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(40, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=0, src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(1, 240, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.LOCAL, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_24(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(32, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(1, 8, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=1, src=()),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=8), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=2)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - # this is the cause of the GPT2 BEAM instability. bisects to PR#3530 O(n) arange attempt - def test_failure_25(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1025, 2047), strides=(0, 0), offset=0, mask=((0, 1025), (1023, 2047)), contiguous=False), View(shape=(1024, 1024), strides=(1, 2048), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1024), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - # COMPARE_ERROR from GPT2 kernel - stems from uops.py self.simplify_phi_loops - def test_failure_26(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(128), arg=ShapeTracker(views=(View(shape=(128, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(128), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(129, 255), strides=(0, 0), offset=0, mask=((0, 129), (127, 255)), contiguous=False), View(shape=(128, 128), strides=(1, 256), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 128), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - all_failing_opts = [ - [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.GROUPTOP, axis=0, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=0)], - [Opt(op=OptOps.GROUPTOP, axis=0, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4)], - [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4)], - [Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)], - [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4)], - [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=4)], - [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - [Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - ] - for opts in all_failing_opts: - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - # COMPARE_ERROR from GPT2 kernel - just the first element off - # testing ast 41 - # 0 ━┳ STORE MemBuffer(idx=0, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),))) - # 1 ┗━┳ MAX (3,) - # 2 ┗━━ LOAD MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),))) - # 208 13 - # ... - # Mismatched elements: 1 / 1232 (0.0812%) - # Max absolute difference: 0.8687 - # Max relative difference: 1. - # x: array([0. , 0.996, 0.829, ..., 0. , 0. , 0. ], dtype=float16) - # y: array([0.8687, 0.996 , 0.829 , ..., 0. , 0. , 0. ], dtype=float16) - # COMPARE FAILED!! - def test_failure_27(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(208), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.MAX, (3,)), src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(2704), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2704), arg=1, src=()),)),)),)),)),)) - all_failing_opts = [ - [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=7), Opt(op=OptOps.UPCAST, axis=0, arg=0)], - ] - for opts in all_failing_opts: - helper_test_lin(Kernel(ast), opts, failed_platforms=[]) - - def test_failure_28(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.bfloat16.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.bfloat16.ptr(1), arg=0, src=()),)), - UOp(Ops.WHERE, dtypes.bfloat16, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - x5:=UOp(Ops.CAST, dtypes.bfloat16, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()),)),)),)), - x9:=UOp(Ops.CONST, dtypes.bfloat16, arg=230.0, src=( - x10:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=()),)),)), - UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( - UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( - UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( - x5, - UOp(Ops.CONST, dtypes.bfloat16, arg=0.004347826086956522, src=( - x10,)),)), - UOp(Ops.CONST, dtypes.bfloat16, arg=0.199374800625, src=( - x10,)),)), - UOp(Ops.CONST, dtypes.bfloat16, arg=1.99375e-07, src=( - x10,)),)), - UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( - UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( - UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( - UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( - x5, - x9,)), - UOp(Ops.CONST, dtypes.bfloat16, arg=0.0012987012987012987, src=( - x10,)),)), - UOp(Ops.CONST, dtypes.bfloat16, arg=-0.19439062499999998, src=( - x10,)),)), - UOp(Ops.CONST, dtypes.bfloat16, arg=0.199375, src=( - x10,)),)),)),)),)) - helper_test_lin(Kernel(ast), opts=[], failed_platforms=[]) - - def test_failure_29(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(128, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(1, 128, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 128), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(128, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(36864), arg=ShapeTracker(views=(View(shape=(128, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(36864), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 1, 1)), Opt(op=OptOps.PADTO, axis=2, arg=32)] - helper_test_lin(Kernel(ast), opts, failed_platforms=[], atol=1.0) - - def test_failure_30(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(2952192), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 1, 1, 1), strides=(11532, 0, 961, 31, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2952192), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(786432), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 3, 2, 2), strides=(3072, 0, 0, 32, 1, 1024, 32, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(786432), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(144), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 3, 2, 2), strides=(0, 0, 12, 0, 0, 4, 2, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(144), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.PADTO, axis=3, arg=32), Opt(op=OptOps.LOCAL, axis=3, arg=32), Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - # from METAL=1 fuzz_linearizer command in test.yml - def test_failure_31(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(208), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(2704), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(2704), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(208), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - @unittest.skipIf(CI, "for real AMD GPU") - def test_failure_32(self): - # kernel from beaming resnet - # Memory access fault on tinybox red - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(12845056), arg=ShapeTracker(views=(View(shape=(256, 1, 256, 14, 14, 1, 1, 1), strides=(50176, 0, 196, 14, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12845056), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(12845056), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 256, 4, 16, 4, 16), strides=(0, 50176, 0, 196, 0, 14, 0, 1), offset=-15, mask=((0, 1), (0, 256), (0, 1), (0, 256), (0, 4), (1, 15), (0, 4), (1, 15)), contiguous=False), View(shape=(256, 1, 256, 14, 14, 256, 3, 3), strides=(1048576, 0, 0, 64, 1, 4096, 1088, 17), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12845056), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(589824), arg=ShapeTracker(views=(View(shape=(256, 1, 256, 14, 14, 256, 3, 3), strides=(0, 0, 2304, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(589824), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=7), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=16)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[], atol=0.1, rtol=0.05) - - def test_failure_33(self): - # Ops.UNMUL left after linearize - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - x5:=UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(26040), arg=ShapeTracker(views=(View(shape=(32640,), strides=(1,), offset=0, mask=((0, 26040),), contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(26040), arg=1, src=()),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - x5, - x10:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - x18:=UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=((0, 26040),), contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.float, arg=0.06788442333021306, src=( - x11,)), - x10,)), - x5,)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - x18, - UOp(Ops.CONST, dtypes.float, arg=-0.03394221166510653, src=( - x11,)), - x10,)),)), - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(6600), arg=ShapeTracker(views=(View(shape=(32640,), strides=(1,), offset=-26040, mask=((26040, 32640),), contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6600), arg=2, src=()),)),)), - UOp(Ops.WHERE, dtypes.float, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=((26040, 32640),), contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.float, arg=-0.18257418583505536, src=( - x11,)), - x10,)),)),)), - x10,)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x11,)), - UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x11,)),)), - x10,)),)),)),)),)) - opts = [Opt(op=OptOps.GROUPTOP, axis=0, arg=16)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - # from fuzzing on metal - def test_failure_34(self, unroll=False): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(720), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 1, 1), strides=(180, 0, 30, 3, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(720), arg=0, src=()),)), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(308), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 2, 5), strides=(77, 0, 0, 7, 1, 0, 7, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(308), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 2, 5), strides=(0, 0, 10, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=2, src=()),)),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UNROLL, axis=0, arg=0)] if unroll else [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1))] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - def test_failure_35(self): self.test_failure_34(True) - - # from world fuzz_linearizer: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_N=100 FUZZ_NTH=84 python3 ./test/external/fuzz_linearizer.py - def test_failure_36(self): - # Ops.UNMUL left after linearize - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(5), arg=ShapeTracker(views=(View(shape=(5, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(5), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.uchar, arg=None, src=( - UOp(Ops.ADD, dtypes.uint, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.uint, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.CAST, dtypes.uint, arg=None, src=( - UOp(Ops.WHERE, dtypes.uchar, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(6, 9), strides=(0, 0), offset=0, mask=((0, 6), (4, 9)), contiguous=False), View(shape=(5, 5), strides=(1, 10), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.uchar, arg=1, src=( - x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(5, 5), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.uchar, arg=0, src=( - x11,)),)),)),)), - UOp(Ops.CONST, dtypes.uint, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(5, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - # BEGIN METAL=1 ./examples/beautiful_mnist.py failures - # log : PYTHONPATH=. LOGKERNS=/tmp/beautiful_mnist.kernels.txt METAL=1 python3 ./examples/beautiful_mnist.py - def test_failure_37(self): - # beautiful mnist kernel number 28: 6 possible TC axis_choices (3 for axis_buf1 and 2 reduce) and all fail - # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=28 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9437184), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(18432, 0, 576, 24, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9437184), arg=0, src=()),)), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(401408), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 5, 5), strides=(784, 0, 0, 28, 1, 0, 28, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(401408), arg=1, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(800), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 5, 5), strides=(0, 0, 25, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(800), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(32), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(32), arg=3, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - for axis in [0,1,2,3,4,5]: - opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - def test_failure_38(self): - # beautiful mnist kernel number 87: 6 possible TC axis_choices (2 for axis_buf1 and 3 reduce) and first/second reduce axis fail for both axis_buf1 choices - # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=87 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(1, 1, 32, 1, 1, 1, 5, 5, 256), strides=(0, 0, 6400, 0, 0, 0, 1280, 256, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 3, 4)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(401408), arg=ShapeTracker(views=(View(shape=(2, 1, 32, 24, 24, 1, 5, 5, 256), strides=(784, 0, 0, 28, 1, 0, 28, 1, 1568), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(401408), arg=1, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(9437184), arg=ShapeTracker(views=(View(shape=(2, 1, 32, 24, 24, 1, 5, 5, 256), strides=(18432, 0, 576, 24, 1, 0, 0, 0, 36864), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9437184), arg=2, src=()),)),)),)),)),)),)) - for axis in [0,1,3,4]: - opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - @unittest.skip("very slow, similar to test_failure_37") - def test_failure_39(self): - # beautiful mnist kernel number 127: 6 possible TC axis_choices (3 for axis_buf1 and 2 reduce) and all fail - # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=127 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(184320000), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(18432, 0, 576, 24, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(184320000), arg=0, src=()),)), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(7840000), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 5, 5), strides=(784, 0, 0, 28, 1, 0, 28, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(7840000), arg=1, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(800), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 5, 5), strides=(0, 0, 25, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(800), arg=2, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(32), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(32), arg=3, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - for axis in [0,1,2,3,4,5]: - opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - def test_failure_40(self): - # beautiful mnist kernel number 3: - # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=2 DEBUG=2 FUZZ_NTH=3 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(60000), arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(60000), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60001, 119999), strides=(0, 0), offset=0, mask=((0, 60001), (59999, 119999)), contiguous=False), View(shape=(60000, 60000), strides=(1, 120000), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 60000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - for amt in [16,32]: - opts = [Opt(op=OptOps.GROUPTOP, axis=0, arg=amt), Opt(op=OptOps.UNROLL, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - # END METAL=1 ./examples/beautiful_mnist.py failures - - @unittest.skipIf(CI, "for real AMD GPU") - def test_failure_41(self): - # One more resnet crash with a page fault on AMD. Checked on rocm6.1.3, -O1 works, -O2 fails - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(256, 1, 128, 28, 28, 1, 1, 1), strides=(100352, 0, 784, 28, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(102760448), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 128, 4, 58, 4, 58), strides=(0, 401408, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 256), (0, 1), (0, 128), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(256, 1, 128, 28, 28, 128, 3, 3), strides=(6889472, 0, 0, 464, 2, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(102760448), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(147456), arg=ShapeTracker(views=(View(shape=(256, 1, 128, 28, 28, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(147456), arg=2, src=()),)),)),)),)),)),)),)),)) - opts=[Opt(op=OptOps.TC, axis=5, arg=(-1, 2, 1)), Opt(op=OptOps.UNROLL, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=["AMD", "HIP"], atol=0.02) - - # llama3 8B failure with BEAM=2 https://github.com/tinygrad/tinygrad/actions/runs/10150118124/job/28066519425#step:14:1, these don't compile - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") - def test_failure_42(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.PADTO, axis=0, arg=32)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") - def test_failure_43(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") - def test_failure_44(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)] - k = helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - assert k is not None - ifs = [u for u in k.uops if u.op is Ops.IF] - self.assertEqual(len(ifs), 3) - #for st in k.uops.sink.src: self.assertEqual(len(st.src), 4) - self.assertLessEqual(len(ifs[0].src[0].toposort()), 17) - - def test_failure_45(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 1, 1, 1), strides=(3, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 3)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 3, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=1, src=()),)),)), - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=2, src=()),)),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (4,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(3, 3), strides=(0, 0), offset=0, mask=((0, 3), (1, 3)), contiguous=False), View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 1, 0, 4), offset=0, mask=((0, 2), (0, 3), (0, 2), (0, 3), (0, 2)), contiguous=False))), src=()),)), - x20:=UOp(Ops.CONST, dtypes.int, arg=1, src=( - x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - x22:=UOp(Ops.CONST, dtypes.int, arg=0, src=( - x21,)),)),)), - x23:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x24:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - x25:=UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x24,)),)), - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(3, 1, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(6), arg=3, src=()),)),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (4,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 5), strides=(0, 0), offset=0, mask=((0, 4), (2, 5)), contiguous=False), View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 0, 1, 6), offset=0, mask=None, contiguous=False))), src=()),)), - x20, - x22,)),)), - x23,)),)), - x25,)),)),)),)),)),)),)) - # ValueError: size mismatched, can't reshape self.shape=(6, 2, 3, 3) -> new_shape=(6, 2, 3, 1, 2) - opts = [Opt(op=OptOps.UNROLL, axis=2, arg=0)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - def test_failure_46(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(10), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(10), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(512), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.bool.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(512), arg=3, src=()),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=4, src=()),)),)),)),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=5, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - def test_failure_47(self): - # upcast an arange, failed with UOP_IS_SYMBOLIC=1 (fixed!) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(60000), arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(60000), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60001, 119999), strides=(0, 0), offset=0, mask=((0, 60001), (59999, 119999)), contiguous=False), View(shape=(60000, 60000), strides=(1, 120000), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 60000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=3)] - helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) - - @unittest.skipUnless(not CI and Device.DEFAULT in ("NV", "CUDA"), "for real NV") - def test_failure_48(self): - # with UOP_IS_SYMBOLIC=1, generates the wrong IDIV (fixed!) - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(4194304), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 1, 1, 256, 1, 1, 256), strides=(0, 0, 65536, 0, 0, 256, 0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3, 4)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(205520896), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 56, 56, 256, 1, 1, 256), strides=(0, 0, 0, 56, 1, 3136, 0, 0, 802816), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(205520896), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 56, 56, 256, 1, 1, 256), strides=(0, 0, 3136, 56, 1, 0, 0, 0, 200704), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=2, src=()),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 0, 1)), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_49(self): - # with UOP_IS_SYMBOLIC=1, on METAL it breaks store fusion and has A+B and B+A being two different UOp - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(10, 6, 1), strides=(6, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(100), arg=ShapeTracker(views=(View(shape=(10, 6, 10), strides=(10, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(100), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(10, 6, 10), strides=(0, 1, 6), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=2, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=0, arg=2)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_50(self): - # from BEAM_COMPARE=2 running tinyphysics.onnx model - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.bool.ptr(400), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 1, 20), strides=(0, 0, 20, 0, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(400), arg=0, src=()),)), - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.bool, arg=(Ops.ADD, (3,)), src=( - UOp(Ops.MUL, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.bool.ptr(400), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 20, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(400), arg=1, src=()),)),)), - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(20), arg=2, src=()),)),)), - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(20), arg=3, src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 20, 1, 20), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=2)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_51(self): - # regression test for #7019, training bert on tinybox red - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(12288), arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(1024, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12288), arg=0, src=()),)), - UOp(Ops.RECIP, dtypes.half, arg=None, src=( - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.CONST, dtypes.half, arg=1.0, src=( - x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.EXP2, dtypes.half, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.CONST, dtypes.half, arg=2.0, src=( - x6,)), - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(5768192), arg=ShapeTracker(views=(View(shape=(12, 1024, 1024), strides=(524288, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(5768192), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1048576), arg=ShapeTracker(views=(View(shape=(12, 1024, 1024), strides=(0, 1024, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1048576), arg=2, src=()),)),)),)),)),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=3, src=()),)),)),)),)), - UOp(Ops.CONST, dtypes.half, arg=-1.4426950408889634, src=( - x6,)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1))] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - @unittest.skip("allocating over 200MB buffer") - @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") - def test_failure_52(self): - # resnet beam. - # NV also fails with a pf. - # CUDA Error 700, an illegal memory access was encountered - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(205520896), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(205520896), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(38535168), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, 256), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), View(shape=(256, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(38535168), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(9408), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(9408), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_53(self): - # COMPILE_ERROR, val scope issue - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(1024), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.uchar, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.MUL, dtypes.uchar, arg=None, src=( - UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(50000), arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(50000), arg=1, src=()),)),)), - UOp(Ops.CAST, dtypes.uchar, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=2, src=()),)),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(50001, 99999), strides=(0, 0), offset=0, mask=((0, 50001), (49999, 99999)), contiguous=False), View(shape=(1024, 50000, 50000), strides=(0, 1, 100000), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x20:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 50000, 50000), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x20,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x23:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x23,)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.GROUPTOP, axis=1, arg=16)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=["AMD", "GPU", "METAL", "NV", "CUDA"]) - - @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") - def test_failure_54(self): - # resnet beam - # HIP: Memory access fault by GPU node-1 (Agent handle: 0x56c21f1d1480) on address 0x730cc242e000. Reason: Page not present or supervisor privilege. - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 256), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(256, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(36864), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(36864), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=7), Opt(op=OptOps.UPCAST, axis=1, arg=2)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=["HIP", "AMD"]) - - @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") - def test_failure_55(self): - W = 2 - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(W * 200704), arg=ShapeTracker(views=(View(shape=(W, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 200704), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(W * 200704), arg=ShapeTracker(views=(View(shape=(1, W, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, W), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(W, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 200704), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(W * 18432), arg=ShapeTracker(views=(View(shape=(W, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 18432), arg=2, src=()),)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.SWAP, axis=1, arg=2)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_56(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(1, 16, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - x7:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(247808), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(1936, 121, 11, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(247808), arg=1, src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x8,)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=3, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=4, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=5, src=()),)),)),)), - x7,)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(128, 16, 5, 2, 5, 2), strides=(1600, 100, 20, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(128, 16, 11, 11), strides=(1600, 100, 10, 1), offset=0, mask=((0, 128), (0, 16), (0, 10), (0, 10)), contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=6, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=2, arg=32)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_57(self): - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(1, 16, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - x7:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(247808), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(1936, 121, 11, 1), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(247808), arg=1, src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x8,)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=3, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=4, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=5, src=()),)),)),)), - x7,)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(128, 16, 5, 2, 5, 2), strides=(1600, 100, 20, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(128, 16, 11, 11), strides=(1600, 100, 10, 1), offset=0, mask=((0, 128), (0, 16), (0, 10), (0, 10)), contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=6, src=()),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32)] - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) - - def test_failure_58(self): - # OUT OF BOUNDS ACCESS in INDEX 0 - 50271 not in 0 - 50257. idx.src[1].render()='gidx0' - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(50257), arg=ShapeTracker(views=(View(shape=(50257, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(50257), arg=0, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(50258, 100513), strides=(0, 0), offset=0, mask=((0, 50258), (50256, 100513)), contiguous=False), View(shape=(50257, 50257), strides=(1, 100514), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(50257, 50257), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(50257, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) - opts = [Opt(op=OptOps.GROUPTOP, axis=0, arg=29), Opt(op=OptOps.PADTO, axis=0, arg=32)] - with Context(IGNORE_OOB=0): - helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=["METAL", "GPU", "AMD", "NV", "CUDA"]) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") - def test_failure_59(self): - # stable diffusion with SINGLE_KERNEL_SOFTMAX=1 - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(134217728, 16777216, 4096, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(268435456), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(134217728, 16777216, 4096, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - x9:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(268435456), arg=1, src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 4096), strides=(134217728, 16777216, 4096, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x15:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - x15,)),)),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 1), strides=(134217728, 16777216, 4096, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - x9,)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 4096), strides=(134217728, 16777216, 4096, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - x9,)),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x29:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - x29,)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.LOCAL, axis=1, arg=16)] - # NOTE: this is slow to run, just confirm it can generate the program without Exception - Kernel(ast, opts=Device[Device.DEFAULT].renderer).apply_opts(opts).to_program() - - @unittest.expectedFailure - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") - def test_failure_60(self): - # TestSymbolicOps.test_attention - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x2:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), - x2,)), - UOp(Ops.CONST, dtypes.int, arg=4, src=()),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), - x1,)), 0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=0, src=()),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x2:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), - x2,)), - UOp(Ops.CONST, dtypes.int, arg=4, src=()),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), - x1,)), 0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=1, src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=0, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), 0, 1), offset=0, mask=None, contiguous=False),)), src=( - x14:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=2, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - x16,)),)),)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( - UOp(Ops.EXP2, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=0, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), 1, 0), offset=0, mask=None, contiguous=False),)), src=( - x14,)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - x0:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x0, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=0, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 1), offset=0, mask=None, contiguous=False), View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=()), - x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x2,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x2,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=0, src=()), - x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x2,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - x0:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x0, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 1), offset=0, mask=None, contiguous=False))), src=( - x14,)),)),)), - UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( - x30:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=4, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x1, - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.CONST, dtypes.int, arg=0, src=()), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), - x3,)), 1, 0), offset=0, mask=None, contiguous=False))), src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( - x30,)),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=4)] - # NOTE: this is slow to run, just confirm it can generate the program without Exception - Kernel(ast, opts=Device[Device.DEFAULT].renderer).apply_opts(opts).to_program() - - def test_failure_61(self): - # WINO=1 JITBEAM=4 python3 examples/beautiful_cifar.py - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - x7:=UOp(Ops.CONST, dtypes.half, arg=0.6931471805599453, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.CONST, dtypes.half, arg=-1.0, src=( - x14:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 10, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.ADD, dtypes.half, arg=None, src=( - UOp(Ops.CONST, dtypes.half, arg=-0.010000000000000002, src=( - x14,)), - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 10, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=1, src=()),)),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,), True), src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.VALID, dtypes.bool, arg=None, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(1024, 10, 10), strides=(0, 1, 20), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=1, src=( - x30:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 10, 10), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x30,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x14,)),)),)), - UOp(Ops.CONST, dtypes.bool, arg=True, src=( - x14,)),)),)), - UOp(Ops.CONST, dtypes.half, arg=-0.4, src=( - x14,)),)),)),)),)),)),)),)), - UOp(Ops.RECIP, dtypes.half, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=2, src=()),)),)), - x7,)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=0, arg=32), Opt(op=OptOps.GROUP, axis=1, arg=0)] - helper_test_lin(Kernel(ast), opts, failed_platforms=["AMD", "METAL", "CUDA", "NV"]) - - def test_failure_62(self): - # WINO=1 DEFAULT_FLOAT=HALF FUSE_ARANGE=1 JITBEAM=4 BS=1024 STEPS=500 python examples/hlb_cifar10.py - # RuntimeError: UOp verification failed at 4 on Ops.LOAD dtypes.half 2 [, ] None - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(11808768), arg=0, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 1, 1, 1), strides=(11532, 0, 961, 31, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.CAST, dtypes.half, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.half, arg=None, src=( - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(3145728), arg=1, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 3, 2, 2), strides=(3072, 0, 0, 32, 1, 1024, 32, 1), offset=0, mask=None, contiguous=False),)), src=()),)), - UOp(Ops.LOAD, dtypes.half, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(144), arg=2, src=()), - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 3, 2, 2), strides=(0, 0, 12, 0, 0, 4, 2, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=1, arg=3), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.PADTO, axis=2, arg=32), Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=0)] - helper_test_lin(Kernel(ast), opts, failed_platforms=["AMD", "HIP", "NV", "CUDA"]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_linearizer_overflows.py b/tinygrad/test/test_linearizer_overflows.py deleted file mode 100644 index 0bd8ef07..00000000 --- a/tinygrad/test/test_linearizer_overflows.py +++ /dev/null @@ -1,195 +0,0 @@ -# ruff: noqa: E501 -import unittest -from tinygrad import dtypes, Device -from tinygrad.helpers import CI -from tinygrad.codegen.kernel import Kernel -from tinygrad.engine.search import Opt, OptOps, bufs_from_lin -from extra.optimization.helpers import time_linearizer - -# stuff needed to unpack a kernel -from tinygrad.uop.ops import UOp, Ops -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View - -def _test_overflow(ast, opts): - lin = Kernel(ast) - lin.apply_opts(opts) - lin.linearize() - bufs = bufs_from_lin(lin) - print(bufs) - time_linearizer(lin, bufs) - -# NOTE: if you want these to trigger, set launch bounds on HIP kernels -@unittest.skip("unneeded without launch bounds") -class TestLinearizerOverflow(unittest.TestCase): - def test_overflow_1(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(51380224), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.MAX, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9633792), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 64, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, 64), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), View(shape=(64, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9408), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - x16:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( - x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=3, src=()), - x20:=UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.SQRT, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - x23:=UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - x17,)), - UOp(Ops.RECIP, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - x23, - UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( - x17,)),)),)),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=4, src=()), - x20,)),)), - x16,)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0)] - _test_overflow(ast, opts) - - # From BEAM on hlb_cifar.py - def test_overflow_2(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(512, 1, 64, 32, 32, 1, 1, 1), strides=(65536, 0, 1024, 32, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16777216), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 512, 1, 32, 4, 34, 4, 34), strides=(0, 32768, 0, 1024, 0, 32, 0, 1), offset=-33, mask=((0, 1), (0, 512), (0, 1), (0, 32), (0, 4), (1, 33), (0, 4), (1, 33)), contiguous=False), View(shape=(512, 1, 64, 32, 32, 32, 3, 3), strides=(591872, 0, 0, 136, 1, 18496, 4760, 35), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18432), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(512, 1, 64, 32, 32, 32, 3, 3), strides=(0, 0, 288, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] - _test_overflow(ast, opts) - - # from BEAM on default simple_conv.py (which is quite large): - def test_overflow_3(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(16, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 16, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 16), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(16, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(16, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=2)] - _test_overflow(ast, opts) - - # from BEAM on BS=4 simple_conv.py: - def test_overflow_4(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(8388608), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(4, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(8388608), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 4, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 4), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(4, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(4, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=4)] - _test_overflow(ast, opts) - - # from BEAM on BS=2 simple_conv.py: - def test_overflow_5(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(2, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 2, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 2), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(2, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(2, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.LOCAL, axis=2, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=2)] - _test_overflow(ast, opts) - - # from BEAM on BS=3 simple_conv.py: - def test_overflow_6(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 3, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 3), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2)] - _test_overflow(ast, opts) - - # from BEAM on BS=3 simple_conv.py: (alt) - def test_overflow_7(self): - ast = UOp(Ops.SINK, None, arg=None, src=( - UOp(Ops.STORE, None, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=0, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=1, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 3, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 3), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), - UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) - opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=4)] - _test_overflow(ast, opts) - -@unittest.skipIf(Device.DEFAULT not in {"GPU", "HSA", "CUDA", "METAL"}, "only backends with locals") -@unittest.skipIf(CI, "slow") -class TestLinearizerOverflowAlt(unittest.TestCase): - def test_overflow_1(self): - BS = 2 - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - in_st_1 = ShapeTracker(views=(View(shape=(1, BS, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, BS), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), - View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))).to_uop() - in_st_2 = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)).to_uop() - ot_st = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)).to_uop() - prod = UOp(Ops.LOAD, dtypes.float, (g1.view(in_st_1.arg),)) * UOp(Ops.LOAD, dtypes.float, (g2.view(in_st_2.arg),)) - store = UOp(Ops.STORE, src=(g0.view(ot_st.arg), UOp(Ops.REDUCE_AXIS, dtypes.float, (prod,), (Ops.ADD, (7, 6, 5))))) - ast = UOp(Ops.SINK, src=(store,)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=2)] - _test_overflow(ast, opts) - def test_overflow_2(self): - BS = 2 - g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] - in_st_1 = ShapeTracker(views=(View(shape=(1, BS, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, BS), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), - View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))).to_uop() - in_st_2 = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)).to_uop() - ot_st = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)).to_uop() - prod = UOp(Ops.LOAD, dtypes.float, (g1.view(in_st_1.arg),)) * UOp(Ops.LOAD, dtypes.float, (g2.view(in_st_2.arg),)) - store = UOp(Ops.STORE, src=(g0.view(ot_st.arg), UOp(Ops.REDUCE_AXIS, dtypes.float, (prod,), (Ops.ADD, (7, 6, 5))))) - ast = UOp(Ops.SINK, src=(store,)) - opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=16), Opt(op=OptOps.UPCAST, axis=4, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=5, arg=2)] - _test_overflow(ast, opts) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_memory_planner.py b/tinygrad/test/test_memory_planner.py deleted file mode 100644 index dcd91569..00000000 --- a/tinygrad/test/test_memory_planner.py +++ /dev/null @@ -1,124 +0,0 @@ -import unittest -from tinygrad import dtypes, Device -from tinygrad.device import Buffer -from tinygrad.engine.memory import _internal_memory_planner - -global_map = {} -def b(i, base=None, offset=0, pin=False, size=16): - global global_map - if i in global_map: return global_map[i] - global_map[i] = Buffer(Device.DEFAULT, size, dtypes.int8, base=global_map[base] if base is not None else None, offset=offset) - if pin: global_map[i].ref(1) - return global_map[i] - -def check_assign(buffers:list[list[Buffer]|tuple[Buffer, ...]]): - assigned = _internal_memory_planner(buffers, noopt_buffers=None) - - taken_parts = set() - first_appearance, last_appearance = {}, {} - for i,u in enumerate(buffers): - for buf in u: - if buf.is_allocated() or buf.base.is_allocated() or buf.lb_refcount > 0: continue - if buf.base not in first_appearance: first_appearance[buf.base] = i - last_appearance[buf.base] = i - - for i,u in enumerate(buffers): - for buf in u: - if buf.is_allocated() or buf.base.is_allocated() or buf.lb_refcount > 0: continue - cur, base = assigned.get(buf, buf), assigned.get(buf.base, buf.base) - if buf._base is not None: - assert cur.base == base.base and cur.offset == buf.offset + base.offset, f"failed: {buf} {cur} {base} {buf.offset} {base.offset}" - else: - for part in taken_parts: - assert buf.base == part[3] or part[0] != cur.base or part[1] + part[2] <= cur.offset or part[1] >= cur.offset + buf.nbytes - if first_appearance[buf.base] == i: taken_parts.add((cur.base, cur.offset, buf.nbytes, buf.base)) - if last_appearance[buf.base] == i: taken_parts.remove((cur.base, cur.offset, buf.nbytes, buf.base)) - -class TestMemoryPlanner(unittest.TestCase): - def setUp(self): - global global_map - global_map = {} - - def test_simple_buffer(self): - bs = [ - [b(0), b(1), b(2)], - [b(1), b(2), b(3)], - [b(4), b(3)], - [b(5), b(2)], - ] - check_assign(bs) - - def test_simple_pinned(self): - bs = [ - [b(0, pin=True), b(1), b(2, pin=True)], - [b(1), b(2), b(3)], - [b(4), b(3)], - [b(5), b(2)], - ] - check_assign(bs) - - def test_all_pinned(self): - bs = [ - [b(0, pin=True), b(1, pin=True)], - [b(1), b(2, pin=True)], - [b(4, pin=True), b(3, pin=True)], - ] - check_assign(bs) - - def test_simple_buffer_offset(self): - bs = [ - [b(0, pin=True), b(1, base=0, offset=1, size=8), b(2)], - [b(1), b(2), b(3, base=0, offset=1, size=8)], - [b(4), b(3)], - ] - check_assign(bs) - - def test_buffer_offset(self): - bs = [ - [b(0, pin=True), b(1, base=0, offset=1, size=8), b(2)], - [b(1), b(2), b(3, base=0, offset=1, size=8)], - [b(4), b(3)], - [b(5, base=2, offset=2, size=8), b(3)], - [b(6), b(5), b(0)], - [b(7), b(8, pin=True)], - [b(8), b(9, base=2, offset=2, size=8)], - [b(9), b(3), b(5)], - ] - check_assign(bs) - - def test_buffer_offset2(self): - bs = [ - [b(0, pin=True), b(1), b(2)], - [b(1), b(2), b(3)], - [b(4), b(3)], - [b(5), b(3)], - [b(6), b(5), b(0)], - [b(7), b(8, pin=True)], - [b(8), b(9)], - [b(9), b(3), b(5)], - [b(11), b(0)], - [b(11), b(10), b(5)], - [b(12), b(11), b(0)], - [b(6), b(12), b(7)], - [b(13), b(6), b(11)], - ] - check_assign(bs) - - def test_all_offsets_of_one(self): - bs = [ - [b(0, pin=True), b(1)], - [b(3, base=1, offset=0, size=8), b(2, base=0, offset=0, size=8)], - [b(5, base=1, offset=8, size=8), b(4, base=0, offset=8, size=8)], - [b(7, base=1, offset=4, size=8), b(6, base=0, offset=4, size=8)], - - [b(4), b(5), b(2)], - [b(3), b(7)], - [b(10), b(6), b(7)], - [b(11), b(3), b(2)], - [b(12), b(5), b(4), b(3), b(2)], - [b(13), b(6), b(12), b(7)], - ] - check_assign(bs) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_metal.py b/tinygrad/test/test_metal.py deleted file mode 100644 index 3230b7b7..00000000 --- a/tinygrad/test/test_metal.py +++ /dev/null @@ -1,75 +0,0 @@ -import unittest -from tinygrad.device import CompileError, Device, Compiler -if Device.DEFAULT=="METAL": - from tinygrad.runtime.ops_metal import MetalDevice, MetalCompiler, MetalProgram -@unittest.skipIf(Device.DEFAULT!="METAL", "Metal support required") -class TestMetal(unittest.TestCase): - def test_alloc_oom(self): - device = MetalDevice("metal") - with self.assertRaises(MemoryError): - device.allocator.alloc(10000000000000000000) - - def test_compile_error(self): - compiler = MetalCompiler() - with self.assertRaises(CompileError): - compiler.compile("this is not valid metal") - - def test_compile_success(self): - compiler = MetalCompiler() - ret = compiler.compile(""" -#include - using namespace metal; - kernel void E_4n1(device int* data0, const device int* data1, const device int* data2, - uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { - int val0 = *(data1+0); - int val1 = *(data1+1); - int val2 = *(data1+2); - int val3 = *(data1+3); - int val4 = *(data2+0); - int val5 = *(data2+1); - int val6 = *(data2+2); - int val7 = *(data2+3); - *(data0+0) = (val0+val4); - *(data0+1) = (val1+val5); - *(data0+2) = (val2+val6); - *(data0+3) = (val3+val7); - } -""") - assert ret is not None - - def test_failed_newLibraryWithData(self): - device = MetalDevice("metal") - compiler = MetalCompiler() - compiled = compiler.compile(""" -#include -kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ - data0[0] = 0; -} -""") - with self.assertRaises(RuntimeError): - compiled = compiled[:40] # corrupt the compiled program - MetalProgram(device, "r_5", compiled) - - def test_program_w_empty_compiler(self): - device = MetalDevice("metal") - compiler = Compiler(device) - compiled = compiler.compile(""" -#include -kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ - data0[0] = 0; -} -""") - MetalProgram(device, "r_5", compiled) - - def test_bad_program_w_empty_compiler(self): - device = MetalDevice("metal") - compiler = Compiler(device) - # this does not raise - compiled = compiler.compile(""" -#include -kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ - invalid codes; -} -""") - with self.assertRaises(RuntimeError): - MetalProgram(device, "r_5", compiled) \ No newline at end of file diff --git a/tinygrad/test/test_method_cache.py b/tinygrad/test/test_method_cache.py deleted file mode 100644 index 497b4069..00000000 --- a/tinygrad/test/test_method_cache.py +++ /dev/null @@ -1,48 +0,0 @@ -import unittest -from tinygrad import Tensor, Device, Variable -from examples.gpt2 import Transformer -from tinygrad.nn.state import get_state_dict - -class TestMethodCache(unittest.TestCase): - def setUp(self): - self.backup_compiler = Device[Device.DEFAULT].compiler - def tearDown(self): - Device[Device.DEFAULT].compiler = self.backup_compiler - - def test_simple_methodcache(self): - a = Tensor([1]) - b = Tensor([2]) - c = Tensor([3]) - d = Tensor([4]) - (a+b).realize() - Device[Device.DEFAULT].compiler = None - (c+d).realize() - - def test_nested_methodcache(self): - a,b,c,d = Tensor([1]), Tensor([2]), Tensor([3]), Tensor([4]) - ((a+b)+(a+b)).realize() - Device[Device.DEFAULT].compiler = None - ((c+d)+(c+d)).realize() - - def test_nested_methodcache_swap(self): - a,b,c,d = Tensor([1]), Tensor([2]), Tensor([3]), Tensor([4]) - ((a+b)+(c+d)).realize() - Device[Device.DEFAULT].compiler = None - ((c+d)+(a+b)).realize() - - @unittest.skip("incorrect use of transformer") - def test_small_transformer(self): - args_tiny = {"dim": 16, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 10} - model = Transformer(**args_tiny) - for v in get_state_dict(model).values(): v.assign(Tensor.empty(*v.shape, dtype=v.dtype).realize()) - # NOTE: you have to do this twice due to the k-v cache - for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() - for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() - Device[Device.DEFAULT].compiler = None - for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() - -if __name__ == '__main__': - unittest.main() - - - diff --git a/tinygrad/test/test_multitensor.py b/tinygrad/test/test_multitensor.py deleted file mode 100644 index 0f6f16b4..00000000 --- a/tinygrad/test/test_multitensor.py +++ /dev/null @@ -1,1268 +0,0 @@ -import unittest, functools, random, os -from tinygrad import Tensor, Device, nn, GlobalCounters, TinyJit, dtypes, Variable -from tinygrad.device import is_dtype_supported -from tinygrad.uop.ops import Ops, UOp -from tinygrad.helpers import CI, getenv, prod, Context, OSX -from tinygrad.nn.state import get_parameters, get_state_dict -from tinygrad.engine.realize import lower_schedule, BufferCopy, CompiledRunner, run_schedule -import numpy as np -from hypothesis import given, strategies as strat, settings -from test.helpers import REAL_DEV, not_support_multi_device - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") - -d0 = f"{Device.DEFAULT}:0" -d1 = f"{Device.DEFAULT}:1" -d2 = f"{Device.DEFAULT}:2" -d3 = f"{Device.DEFAULT}:3" -d4 = f"{Device.DEFAULT}:4" -d5 = f"{Device.DEFAULT}:5" -devices_2 = (d1, d2) -devices_3 = (d1, d2, d3) -devices_4 = (d1, d2, d3, d4) -N = 128 - -# shard_x is "data parallel" -# shard_w is "model parallel" - -def _test_allreduce(t:Tensor): - aa = (t[0:64] + t[64:128] + t[128:192] + t[192:256]).repeat([4,1]).realize() - ts = t.shard(devices_4, 0).realize() - b = Tensor(UOp.allreduce(ts.uop, Ops.ADD, ts.device)) - b.realize() - return aa, b - -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestMultiTensor(unittest.TestCase): - def test_to(self): - X = Tensor.ones(256).contiguous().realize() - X.to_(devices_2) - assert X.shape == (256,) - (X + X).realize() - - def test_gradient(self): - X = Tensor.ones(256).contiguous().realize() - X.to_(devices_2) - grad = X.sum().gradient(X)[0] - grad.realize() - - def test_shard(self): - X = Tensor.ones(256).contiguous().realize() - X.shard_(devices_2, 0) - for lb in X.uop.src: - assert lb.shape == (128,) - (X + X).realize() - - def test_shard_not_multiple(self): - X = Tensor.ones(256).contiguous().realize() - with self.assertRaises(RuntimeError): - X.shard_(devices_3, 0) - - def test_tensor_from_multi(self): - X = Tensor([1, 2], dtype=dtypes.int).shard_(devices_2, 0) - Y = Tensor(X.uop) - self.assertEqual(Y.device, Device.DEFAULT) - np.testing.assert_equal(X.numpy(), Y.numpy()) - - with self.assertRaises(AssertionError): - _ = Tensor(X.uop, dtype=dtypes.float) - - def test_sharded_arange(self): - sharded_arange = Tensor.arange(1000).shard(devices_2, 0) - sharded_arange.realize() - np.testing.assert_equal(sharded_arange.numpy(), np.arange(1000)) - - # TODO: fix this to not copy on the src device - @unittest.expectedFailure - def test_shard_no_recompile(self): - X = Tensor.ones(256).contiguous().realize() - X.shard_(devices_2, 0) - out = (X + X) - sched = out.schedule() - names = [] - for si, ei in lower_schedule(sched): - if isinstance(ei.prg, CompiledRunner): names.append(ei.prg.p.name) - ei.run() - self.assertEqual(len(set(names)), 1, "function was relinearized") - - @unittest.skip("this doesn't fold because shard_ calls contiguous on all lbs") - def test_sharded_memory(self): - # Buffer may be stuck in track_cross_buffer - for x in (d0, d1, d2, d3, d4): Device[x].synchronize() - mem_base = GlobalCounters.mem_used - - X = Tensor.ones(256).contiguous().realize() - assert GlobalCounters.mem_used-mem_base== X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base - X.shard_(devices_4).realize() - for x in (d0, d1, d2, d3, d4): Device[x].synchronize() - assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256 * 4, GlobalCounters.mem_used-mem_base - - X = Tensor.ones(256).contiguous().realize() - assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base - X.shard_(devices_4, axis=0).realize() - for x in (d0, d1, d2, d3, d4): Device[x].synchronize() - assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base - - X = Tensor.ones(256).realize() - assert GlobalCounters.mem_used-mem_base == 0 - X.shard_(devices_4).realize() - assert GlobalCounters.mem_used-mem_base == 0 - - X = Tensor.ones(256).realize() - assert GlobalCounters.mem_used-mem_base == 0 - X.shard_(devices_4, axis=0).realize() - assert GlobalCounters.mem_used-mem_base == 0 - - def test_shard_same_device(self): - X = Tensor.ones(256).contiguous().realize() - X.shard_((d1, X.device), 0) - (X + X).realize() - - def test_shard_plus_one_sum(self): - X = Tensor.ones(256).contiguous().realize() - X.shard_((d1, d2), 0) - (X + 1).sum().realize() - - def test_shard_plus_one_sum_d0(self): - X = Tensor.ones(256).contiguous().realize() - X.shard_((d0, d2), 0) - (X + 1).sum().realize() - - def test_numpy(self): - X = Tensor.ones(256) - X.shard_((d1, d2), 0) - np.testing.assert_allclose(X.numpy(), 1) - - def _test_simple_add_axis(self, shard_x, shard_w): - X = Tensor.ones(256).contiguous().realize() - W = Tensor.ones(256).contiguous().realize() - X.shard_((d1, d2), shard_x) - W.shard_((d1, d2), shard_w) - O = X + W - np.testing.assert_allclose(O.numpy(), 2) - - def test_simple_add(self): return self._test_simple_add_axis(None, None) - def test_simple_add_X(self): return self._test_simple_add_axis(0, None) - def test_simple_add_W(self): return self._test_simple_add_axis(None, 0) - def test_simple_add_XW(self): return self._test_simple_add_axis(0, 0) - - def test_four_add(self): - X = Tensor.ones(256, 256).contiguous().realize() - W = Tensor.ones(256, 256).contiguous().realize() - X.shard_(devices_4, 1) - W.shard_(devices_4, None) - O = X + W - np.testing.assert_allclose(O.numpy(), 2) - - def test_elementwise_dtype(self): - Tensor.manual_seed(0) - X = Tensor.randn(8, 8).realize() - W = Tensor.randn(8, 8).realize() - X.shard_(devices_4, 0) - W.shard_(devices_4, 0) - O = X.shrink(((0, 2), None)) * W.shrink(((0, 2), None)) < 2 - np.testing.assert_allclose(O.numpy(), X.numpy()[0:2]*W.numpy()[0:2] < 2) - - def test_shrink_on_shard_axis(self): - X = Tensor.arange(4*4).reshape(4,4).realize() - X_np = X.numpy() - X.shard_(devices_2, 0) - # only shrink on the device that owns the shard, this is enabled by the mselect simplifier - for i in range(2): - xt = X[i*2:i*2+2].contiguous() - sched = xt.schedule() - #kernels = [s for s in sched if s.ast.op is Ops.SINK] - #self.assertEqual(len(kernels), 1) - #self.assertEqual(kernels[0].bufs[0].device, devices_2[i]) - run_schedule(sched) - np.testing.assert_equal(xt.numpy(), X_np[i*2:i*2+2]) - - @given(strat.sampled_from((4, 5)), strat.sampled_from((devices_2, devices_3)), - strat.sampled_from((Ops.ADD, Ops.MUL, Ops.MAX)), - strat.sampled_from((None, 0, 1)), strat.sampled_from((None, 0, 1)), strat.sampled_from((1, 0, -1))) - def test_simple_reduce(self, N, devices, rop, shard_axis, reduce_axis, sign): - N = N * len(devices) - X = Tensor.rand(N*N).reshape(N, N).mul(sign) - n = X.numpy() - X.shard_(devices, shard_axis) - f = {Ops.ADD: lambda x: x.sum(reduce_axis), Ops.MUL: lambda x: x.prod(reduce_axis), - Ops.MAX: lambda x: x.max(reduce_axis)}[rop] - fX = f(X) - fn = f(n) - np.testing.assert_allclose(fX.numpy(), fn, rtol=1e-6, atol=1e-6) - - def test_allreduce_naive(self): - with Context(RING=0): - a,b = _test_allreduce(Tensor.rand(256, 256)) - np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) - - def test_allreduce_ring(self): - with Context(RING=2): - a,b = _test_allreduce(Tensor.rand(256, 256)) - np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) - - def test_copy_jit(self): - @TinyJit - def copy_tensor(x:Tensor): return (x.to(f"{x.device.split(':')[0]}:1") + 1) - for _ in range(5): - t = Tensor.rand(256).realize() - x = copy_tensor(t) - np.testing.assert_equal((t+1).numpy(), x.numpy()) - - def test_allreduce_naive_jit(self): - with Context(RING=0): - jit_allreduce = TinyJit(_test_allreduce) - for _ in range(5): - a,b = jit_allreduce(Tensor.rand(256, 256)) - np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) - - def test_allreduce_ring_jit(self): - with Context(RING=2): - jit_allreduce = TinyJit(_test_allreduce) - for _ in range(5): - a,b = jit_allreduce(Tensor.rand(256, 256)) - np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) - - def test_multitensor_jit_input(self): - @TinyJit - def f(x): return (x+1).contiguous().sum() - for _ in range(5): - tt = Tensor.arange(0, 4).contiguous().realize().shard((d1,d2), 0).realize() - out = f(tt) - assert out.item() == 1+2+3+4 - - def test_multitensor_inside_jit(self): - @TinyJit - def f(x): return (x.shard((d1,d2), 0)+1).contiguous().sum() - for _ in range(5): - tt = Tensor.arange(0, 4).contiguous().realize() - out = f(tt) - assert out.item() == 1+2+3+4 - - def test_fuzz_allreduce(self): - random.seed(41) - for it in range(2): - for n in range(2, 4+1): - shape = tuple([(n if i == 0 else 1) * random.randint(1, 10) for i in range(random.randint(1, 4))]) - t = Tensor.rand(shape).shard_(tuple([d0, d1, d2, d3][:n]), 0) - with Context(RING=0): - a = Tensor(UOp.allreduce(t.uop, Ops.ADD, t.device)) - with Context(RING=2): - b = Tensor(UOp.allreduce(t.uop, Ops.ADD, t.device)) - diff = a - b - mean_err = diff.reshape((prod(diff.shape),)).abs().mean().numpy() - max_err = diff.reshape((prod(diff.shape),)).abs().max().numpy() - assert mean_err < 1e-6, f"big mean error, iteration {it}_{n}" - assert max_err < 1e-6, f"big max error, iteration {it}_{n}" - - def _test_matmul_shard_axis(self, shard_x, shard_w, device): - X = Tensor.kaiming_uniform(N, N).realize() - W = Tensor.kaiming_uniform(N, N).realize() - Xs = X.shard(device, shard_x) - Ws = W.shard(device, shard_w) - O = (Xs@Ws) - np.testing.assert_allclose(X.numpy() @ W.numpy(), O.to(Device.DEFAULT).numpy(), atol=1e-5) - - def _test_double_matmul_shard_axis(self, shard_x, shard_w, device): - X = Tensor.kaiming_uniform(N, N).realize() - W1 = Tensor.kaiming_uniform(N, N).realize() - W2 = Tensor.kaiming_uniform(N, N).realize() - Xs = X.shard(device, shard_x) - W1s = W1.shard(device, shard_w) - W2s = W2.shard(device, shard_w) - O = (Xs@W1s)@W2s - np.testing.assert_allclose((X.numpy() @ W1.numpy()) @ W2.numpy(), O.to(Device.DEFAULT).numpy(), atol=1e-5) - - def test_matmul_shard_none(self): return self._test_matmul_shard_axis(None, None, devices_2) - def test_matmul_shard_X_0(self): return self._test_matmul_shard_axis(0, None, devices_2) - def test_matmul_shard_X_1(self): return self._test_matmul_shard_axis(1, None, devices_2) - def test_matmul_shard_W_0(self): return self._test_matmul_shard_axis(None, 0, devices_2) - def test_matmul_shard_W_1(self): return self._test_matmul_shard_axis(None, 1, devices_2) - - def test_matmul_shard_0_0(self): return self._test_matmul_shard_axis(0, 0, devices_2) - def test_matmul_shard_0_1(self): return self._test_matmul_shard_axis(0, 1, devices_2) - def test_matmul_shard_1_0(self): return self._test_matmul_shard_axis(1, 0, devices_2) - def test_matmul_shard_1_1(self): return self._test_matmul_shard_axis(1, 1, devices_2) - - def test_double_matmul_shard_X_0(self): return self._test_double_matmul_shard_axis(0, None, devices_2) - def test_double_matmul_shard_X_1(self): return self._test_double_matmul_shard_axis(1, None, devices_2) - def test_double_matmul_shard_W_0(self): return self._test_double_matmul_shard_axis(None, 0, devices_2) - def test_double_matmul_shard_W_1(self): return self._test_double_matmul_shard_axis(None, 1, devices_2) - - def test_conv_data_shard(self): - conv = nn.Conv2d(3, 16, 3, bias=False) - for p in get_parameters(conv): p.shard_(devices_2) - fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) - out = conv(fake_image) - out.numpy() - - def test_conv_bias_data_shard(self): - conv = nn.Conv2d(3, 16, 3) - for p in get_parameters(conv): p.shard_(devices_2) - fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) - out = conv(fake_image) - out.numpy() - - def test_backprop_conv(self): - with Tensor.train(): - conv = nn.Conv2d(3, 16, 3) - for p in get_parameters(conv): p.shard_(devices_2) - optim = nn.optim.Adam(get_parameters(conv)) - fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) - out = conv(fake_image) - optim.zero_grad() - out.mean().backward() - #for p in get_parameters(conv): p.grad.realize() - optim.step() - out.numpy() - - def test_backprop_conv_wino(self): - with Context(WINO=1): self.test_backprop_conv() - - def test_backward_sum(self): - x = Tensor([[1.,2,3,4], [5,6,7,8]]).shard(devices_2, axis=0) - w = Tensor([1.,2,3,4], requires_grad=True).shard(devices_2) - out = x * w - out.mean().backward() - tst = w.grad.numpy() - np.testing.assert_allclose(tst, [0.75, 1., 1.25, 1.5]) - - def test_lr_scheduler_OneCycleLR(self): - from extra.lr_scheduler import OneCycleLR - conv = nn.Conv2d(3, 16, 3) - for p in get_parameters(conv): p.shard_(devices_2) - optim = nn.optim.SGD(get_parameters(conv)) - lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) - lr_sched.step() - - def test_embedding(self): - B, T, embed_size, vocab_size = 4, 10, 20, 28 - - layer = nn.Embedding(vocab_size, embed_size) - x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) - z = layer(x) - - layer_sharded = nn.Embedding(vocab_size, embed_size) - layer_sharded.weight.replace(layer.weight.shard(devices_2, axis=1)).realize() - x_sharded = x.shard(devices_2, axis=None) - z_shard = layer_sharded(x_sharded) - - np.testing.assert_allclose(z.numpy(), z_shard.numpy(), atol=1e-6, rtol=1e-6) - - def test_rmsnorm(self): - B, T, embed_size = 4, 10, 20 - - norm = nn.RMSNorm(embed_size) - x = Tensor.rand((B, T, embed_size)).contiguous().realize() - y = norm(x) - - # for norm layers, the correct way to shard weights is duplication - norm_sharded = nn.RMSNorm(embed_size) - norm_sharded.weight.shard_(devices_2, axis=None).realize() - - # if x is being sharded, then all-reduce is involved - x_sharded = x.shard(devices_2, axis=2).realize() - y_shard = norm_sharded(x_sharded).realize() - np.testing.assert_allclose(y.numpy(), y_shard.numpy(), atol=1e-6, rtol=1e-6) - - # if x is being duplicated, then the operations remain inside each GPU - # which is the common case - x_sharded = x.shard(devices_2, axis=None).realize() - y_shard = norm_sharded(x_sharded).realize() - np.testing.assert_allclose(y.numpy(), y_shard.numpy(), atol=1e-6, rtol=1e-6) - - # NOTE: this is failing on LLVM CI, no idea why. Works locally. - @unittest.skipIf(CI and REAL_DEV in ("CUDA", "NV", "LLVM", "CPU"), "slow, and flaky on LLVM/CPU") - @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_data_parallel_resnet(self): - from extra.models.resnet import ResNet18 - - fake_image = Tensor.rand((2, 3, 224//8, 224//8)) - fake_image_sharded = fake_image.shard(devices_2, axis=0) - m = ResNet18() - m.load_from_pretrained() - real_output = m(fake_image).log_softmax().numpy() - for p in get_parameters(m): p.shard_(devices_2).realize() - GlobalCounters.reset() - shard_output = m(fake_image_sharded).log_softmax().realize() - shard_output_np = shard_output.numpy() - np.testing.assert_allclose(real_output, shard_output_np, atol=1e-6, rtol=1e-6) - - def _test_model_train_step(self, m, fake_image, labels): - from tinygrad.nn.optim import LARS - optimizer = LARS(get_parameters(m), 0.1) # set requires_grad for all params - - optimizer.zero_grad() - m.load_from_pretrained() - output = m(fake_image).sparse_categorical_crossentropy(labels, label_smoothing=0.1) - output.backward() - grad = m.conv1.weight.grad.numpy() - - fake_image_sharded = fake_image.shard(devices_2, axis=0) - labels_sharded = labels.shard(devices_2, axis=0) - for p in get_parameters(m): p.shard_(devices_2).realize() - GlobalCounters.reset() - optimizer.zero_grad() - shard_output = m(fake_image_sharded).sparse_categorical_crossentropy(labels_sharded, label_smoothing=0.1) - shard_output.backward() - shard_grad = m.conv1.weight.grad.numpy() - # sometimes there is zeros in these grads... why? - np.testing.assert_allclose(grad, shard_grad, atol=1e-5, rtol=1e-5) - - @unittest.skipIf(CI and REAL_DEV in ("CUDA", "NV", "LLVM", "CPU"), "slow, and flaky on LLVM/CPU") - @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_data_parallel_resnet_train_step(self): - from extra.models.resnet import ResNet18 - fake_image = Tensor.rand((2, 3, 224//8, 224//8)) - labels = Tensor.randint(2, low=0, high=1000) - m = ResNet18() - self._test_model_train_step(m, fake_image, labels) - - def test_data_parallel_simple_train_step(self): - class Model: - def __init__(self): self.conv1 = nn.Linear(128,128) - def __call__(self, x): return self.conv1(x) - def load_from_pretrained(self): pass - - fake_image = Tensor.rand((128,)) - labels = Tensor.randint(2, low=0, high=127) - m = Model() - self._test_model_train_step(m, fake_image, labels) - - def test_assign_kv_cache_multi(self): - bsz, max_context = 2, 8 - - class Attn: - @TinyJit - def __call__(self, xk:Tensor, start_pos:UOp): - seqlen = xk.shape[1] - if not hasattr(self, "cache_k"): - self.cache_k = Tensor.zeros(bsz, max_context, 1, 1).shard(devices_2).contiguous().realize() - keys = self.cache_k.shrink((None, (0, start_pos), None, None)).cat(xk, dim=1).contiguous() if start_pos > 0 else xk - self.cache_k.assign(keys.pad((None,(0,max_context-start_pos-seqlen),None,None)).contiguous()).realize() - - attn = Attn() - xk = Tensor.ones(bsz, 3, 1, 1).shard(devices_2).contiguous() - attn(xk, 0) - for i in range(3,6): - # copied from LLaMA - start_pos = Variable("start_pos", 1, max_context).bind(i) - xk = Tensor.ones(bsz, 1, 1, 1).shard(devices_2).contiguous() - attn(xk, start_pos) - - out = attn.cache_k.flatten().numpy() - np.testing.assert_allclose(out, [1.,1.,1.,1.,1.,1.,0.,0.,1.,1.,1.,1.,1.,1.,0.,0.]) - - def test_multi_tensor_jit_param(self): - @TinyJit - def jf(a, b) -> Tensor: - return (a + b).realize() - - for _ in range(5): - a = Tensor.ones(256).contiguous().realize() - b = Tensor.ones(256).contiguous().realize() - a.shard_(devices_2) - b.shard_(devices_2) - c = jf(a, b) - np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) - assert len(jf.jit_cache) > 0 - - def test_multi_tensor_jit_body(self): - @TinyJit - def jf() -> Tensor: - a = Tensor.ones(256).contiguous().realize() - b = Tensor.ones(256).contiguous().realize() - a.shard_(devices_2) - b.shard_(devices_2) - return (a + b).realize() - - for _ in range(5): - r = jf() - np.testing.assert_allclose(r.numpy(), np.ones(256)+np.ones(256), atol=1e-4, rtol=1e-5) - assert len(jf.jit_cache) > 0 - - @unittest.skip("test broken") - def test_multi_device_jit_graph(self): - if Device[d0].graph is None or Device[d1].graph is None: raise unittest.SkipTest("only test graphs") - - @TinyJit - def jf(a: Tensor, b: Tensor, c: Tensor, d:Tensor): - # Create 80 entries on device 0: 2 batches. - for _ in range(40): - a = ((a + b).realize() + (a * b).realize()).realize() - # Create 80 entries on device 1: 2 batches. - for _ in range(40): - c = ((c + d).realize() + (c * d).realize()).realize() - # Create a copy from device 0 to 1: 1 entry. - a = a.to(d1).realize() - # Creates one last entry on device 1: 1 batch. - return (a + c).realize() - - a = Tensor.randn(10, 10, device=d0).realize() - b = Tensor.randn(10, 10, device=d0).realize() - c = Tensor.randn(10, 10, device=d1).realize() - d = Tensor.randn(10, 10, device=d1).realize() - - ref = jf(a, b, c, d).numpy() - for _ in range(5): - o = jf(a, b, c, d).numpy() - np.testing.assert_allclose(ref, o, atol=1e-4, rtol=1e-5) - - graph_d0 = Device[d0].graph.func if isinstance(Device[d0].graph, functools.partial) else Device[d0].graph - graph_d1 = Device[d1].graph.func if isinstance(Device[d1].graph, functools.partial) else Device[d1].graph - # Checking that 2 graphs per device, 1 copy and 1 last graph on device 1 are created. - assert isinstance(jf.jit_cache[0].prg, graph_d0) - assert isinstance(jf.jit_cache[1].prg, graph_d0) - assert isinstance(jf.jit_cache[2].prg, graph_d1) - assert isinstance(jf.jit_cache[3].prg, graph_d1) - assert isinstance(jf.jit_cache[4].prg, BufferCopy) - assert isinstance(jf.jit_cache[5].prg, graph_d1) - - @unittest.skip("no longer supports uneven shard") - def test_uneven_shard(self): - for N in range(1, 6): - X = Tensor.rand(4, 1, 257).contiguous().realize() - n = X.numpy() - devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) - X.shard_(devices, 2) - np.testing.assert_equal(X.numpy(), n) - np.testing.assert_equal(X.reshape(2, 2, 257).numpy(), n.reshape((2, 2, 257))) - np.testing.assert_equal(X.shrink(((0,2), (0, 1), (0,257))).numpy(), n[0:2, 0:1, 0:257]) - np.testing.assert_equal(X.expand((4, 4, 257)).numpy(), np.tile(n, (1, 4, 1))) - np.testing.assert_equal(X.permute((0, 2, 1)).numpy(), np.transpose(n, (0, 2, 1))) - - @unittest.skip("no longer supports uneven shard") - def test_uneven_multiple_zeros(self): - for data in ([1, 2, 3, 4], [1, 2, 3], [1, 2], [1], []): - for N in (1, 2, 3, 4): - devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) - # make sure something is computed on each device - X = ((Tensor(data).shard(devices, axis=0) + 1).realize() - 1).realize() - np.testing.assert_equal(X.numpy(), data) - - @unittest.skip("no longer supports uneven shard") - def test_uneven_shard_with_empty(self): - N = 4 - X = Tensor.rand(16, 1, 3).contiguous().realize() - np_x = X.numpy() - devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) - - # test empty shard - np.testing.assert_equal(X.shard(devices, 0).numpy(), np_x) - - # test reshape with empty shard - np.testing.assert_equal(X.shard(devices, 0).reshape(8, 1, 6).numpy(), np_x.reshape(8, 1, 6)) - - @unittest.skip("no longer supports uneven shard") - def test_multiple_uneven_shard(self): - N = 4 - X = Tensor.rand(4, 1, 257).contiguous().realize() - Y = Tensor.rand(4, 1, 257).contiguous().realize() - np_x, np_y = X.numpy(), Y.numpy() - devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) - X.shard_(devices, 2) - Y.shard_(devices, 2) - np.testing.assert_equal(X.numpy(), np_x) - np.testing.assert_equal(Y.numpy(), np_y) - np.testing.assert_equal((X + Y).numpy(), np_x + np_y) - - def test_bn_ast_on_devices(self): - t = Tensor.empty((16, 64, 112, 112)).shard(devices_4, axis=0) - bn = nn.BatchNorm2d(64) - for p in get_parameters(bn): p.shard_(devices_4).realize() - - out = bn(t) - scheds = [sched for sched in out.schedule() if sched.bufs[0].device in devices_4 and sched.ast.op is not Ops.COPY] - assert set(sched.bufs[0].device for sched in scheds) == set(devices_4), "should have ast on each shard device" - asts = [sched.ast for sched in scheds] - self.assertEqual(len(asts), 4) - # ast are the same on devices - self.assertEqual(len(set(asts)), 1) - - def test_reshape_on_axis(self): - t0 = Tensor.rand((26, 15, 7)).shard(devices_3, axis=1) - - # test split and rejoin to the right - t1 = t0.reshape((26, 3, 5, 7)) - t2 = t0.reshape((26, 3, 35)) - t3 = t1.reshape((26, 15, 7)) - t4 = t2.reshape((26, 105,)) - - for t in [t0, t1, t2, t3, t4]: - assert t.uop.axis == 1 - np.testing.assert_allclose(t.numpy().flatten(), t0.numpy().flatten()) - - # test shape-one axis - t5 = t4.reshape((26, 1, 105)) - assert t5.uop.axis == 2 - np.testing.assert_allclose(t.numpy().flatten(), t5.numpy().flatten()) - - # test split and rejoin to the right and reshape to the left - t5 = t0.reshape((2, 13, 3, 5, 7)) - t6 = t0.reshape((13, 2, 3, 7, 5)) - t7 = t0.reshape((1, 13, 2, 3, 1, 7, 5)) - assert t5.uop.axis == 2 - assert t6.uop.axis == 2 - assert t7.uop.axis == 3 - np.testing.assert_allclose(t5.numpy().flatten(), t0.numpy().flatten()) - np.testing.assert_allclose(t6.numpy().flatten(), t0.numpy().flatten()) - np.testing.assert_allclose(t7.numpy().flatten(), t0.numpy().flatten()) - - # test no left join - with self.assertRaises((AssertionError, ValueError)): - t0.reshape((26*15,7)).schedule() - - @unittest.skip("no longer supports uneven shard") - def test_reshape_on_axis_uneven(self): - def reshape_helper(t0, t, t_axis): - assert t.uop.axis == t_axis - np.testing.assert_allclose(t0.reshape(t.shape).numpy(), t.numpy()) - - t0 = Tensor.rand((4, 42, 15)).shard(devices_3, axis=1, splits=[14, 7, 21]) - - # ok to reshape as long as elements remain on same device - reshape_helper(t0, t0.reshape(2, 2, 42, 3, 5), 2) - # split to the right - reshape_helper(t0, t0.reshape(2, 2, 6, 7, 15), 2) - # split off and merge to the right - reshape_helper(t0, t0.reshape(4, 6, 105), 1) - # really blend the axes together - reshape_helper(t0, t0.reshape(4, 30, 21), 1) - # split off 1-shape - reshape_helper(t0, t0.reshape(4, 1, 42, 15), 2) - reshape_helper(t0, t0.reshape(4, 6, 1, 7, 15), 1) - - # assert if cannot maintain shard axis without moving items between devices - with self.assertRaises(AssertionError): t0.reshape(4, 7, 6, 15) - # assert for degenerate reshape - with self.assertRaises(AssertionError): t0.reshape(4, 5, 7, 15) - # assert for cannot maintain axis - with self.assertRaises(AssertionError): t0.reshape(4, 3, 2, 7, 15) - - # it doesn't work like this anymore - # NOTE: this never failed in assign_multi, it failed tensor spec because MULTI was never pushed in the graph - @unittest.expectedFailure - def test_mlb_assign_change_axis(self): - t_none = Tensor.zeros((16, 16)).shard(devices_2).contiguous().realize() - t_zero = Tensor.ones((16, 16)).shard(devices_2, axis=0) - with self.assertRaises(RuntimeError): - # don't allow assigns that change axes - t_none.assign(t_zero) - t_none.schedule() - - def test_init_rand_with_multiple_devices_fail(self): - # init rand with multi device is not allowed - with self.assertRaises(ValueError): - Tensor.rand(256, device=devices_2) - - def test_rand_on_multiple_devices(self): - # different devices generate different rand - d0_rand = Tensor.rand(256, device=d0).realize() - d1_rand = Tensor.rand(256, device=d1).realize() - assert not np.allclose(d0_rand.numpy(), d1_rand.numpy()) - - def test_rand_on_multiple_devices_manual_seed(self): - Tensor.manual_seed(123) - d0_rand = Tensor.rand(2, device=d0).tolist() - d1_rand = Tensor.rand(2, device=d1).tolist() - - # manual_seed again gives the same values - Tensor.manual_seed(123) - d0_rand2 = Tensor.rand(2, device=d0).tolist() - d1_rand2 = Tensor.rand(2, device=d1).tolist() - self.assertEqual(d0_rand, d0_rand2) - self.assertEqual(d1_rand, d1_rand2) - - # device seed is only determined by init order, so flipping init order flips rands - Tensor.manual_seed(123) - d1_rand_flip = Tensor.rand(2, device=d1).tolist() - d0_rand_flip = Tensor.rand(2, device=d0).tolist() - self.assertEqual(d0_rand, d1_rand_flip) - self.assertEqual(d1_rand, d0_rand_flip) - - def test_rand_like_on_shard(self): - t = Tensor.empty((16, 16)).shard(devices_2) - t2 = Tensor.rand_like(t) - self.assertEqual(t.shape, t2.shape) - self.assertEqual(t.device, t2.device) - self.assertEqual(t.dtype, t2.dtype) - self.assertEqual(t.uop.axis, t2.uop.axis) - - def test_rand_like_from_alu(self): - a = Tensor.ones(4, 4).shard(devices_4, axis=0) - aa = a + a - self.assertEqual(aa.device, devices_4) - self.assertEqual(aa.uop.axis, 0) - raa = aa.rand_like() - self.assertEqual(raa.device, devices_4) - self.assertEqual(raa.uop.axis, 0) - - b = Tensor.empty(4, 4).shard(devices_4, axis=None) - ab = a + b - self.assertEqual(ab.device, devices_4) - self.assertEqual(ab.uop.axis, 0) - rab = ab.rand_like() - self.assertEqual(rab.device, devices_4) - self.assertEqual(rab.uop.axis, 0) - - @unittest.skip("no longer supports uneven shard") - def test_rand_like_uneven_shard(self): - t = Tensor.empty((4, 42, 15)).shard(devices_3, axis=1) - t2 = Tensor.rand_like(t) - self.assertEqual(t.shape, t2.shape) - self.assertEqual(t.device, t2.device) - self.assertEqual(t.dtype, t2.dtype) - self.assertEqual(t.uop.axis, t2.uop.axis) - assert all(tlb.shape == t2lb.shape for tlb, t2lb in zip(t.uop.src, t2.uop.src)) - - def test_rand_like_none_shard(self): - t = Tensor.empty((16, 16)).shard(devices_2) - t2 = Tensor.rand_like(t) - self.assertEqual(t.shape, t2.shape) - self.assertEqual(t.device, t2.device) - self.assertEqual(t.dtype, t2.dtype) - self.assertEqual(t.uop.axis, t2.uop.axis) - - def test_rand_like_arg_dtype(self): - t = Tensor.empty((16, 16), dtype=dtypes.int32).shard(devices_2, axis=1) - t2 = Tensor.rand_like(t, dtype=dtypes.float32) - self.assertEqual(t.dtype, dtypes.int32) - self.assertEqual(t2.dtype, dtypes.float32) - - def test_rand_like_arg_device(self): - # axis=None - t = Tensor.empty((16, 16)).shard((d1, d2), axis=None) - with self.assertRaises(RuntimeError): - Tensor.rand_like(t, device=(d3, d4)) - - # axis=1 - t = Tensor.empty((16, 16)).shard((d1, d2), axis=1) - with self.assertRaises(RuntimeError): - Tensor.rand_like(t, device=(d3, d4)) - - def test_dropout_on_shard(self): - with Tensor.train(): - X = Tensor.ones(256).to(devices_2) - output = X.dropout(0.5).numpy() - unique, counts = np.unique(output, return_counts=True) - assert set(unique) == {0, 2}, unique - assert 100 < counts[0] < 156, counts[0] - - def test_dropout_on_shard_axis(self): - with Tensor.train(): - X = Tensor.ones(512).shard(devices_2, axis=0) - output = X.dropout(0.5).numpy() - unique, counts = np.unique(output, return_counts=True) - assert set(unique) == {0, 2}, unique - assert 200 < counts[0] < 312, counts[0] - - @unittest.skip("no longer supports uneven shard") - def test_dropout_on_uneven_shard_axis(self): - with Tensor.train(): - X = Tensor.ones(256).shard(devices_3, axis=0) - output = X.dropout(0.5).numpy() - unique, counts = np.unique(output, return_counts=True) - assert set(unique) == {0, 2}, unique - assert 100 < counts[0] < 156, counts[0] - - @unittest.skip("TODO: this requires forced_realize to be deleted.") - def test_shard_memory(self): - devices = (d0, d1, d2, d3) - t = Tensor.zeros(16, 16).contiguous() - t.shard_(devices, axis=0).realize() - assert all([lb is lb.base and lb.realized.base.size == 4 * 16 for lb in t.uop.src]) - - @unittest.skip("this is unreliable on OSX") - def test_clone(self): - t = Tensor.rand(16, 16).shard(devices_2, axis=None) - np.testing.assert_allclose(t.numpy(), t.clone().numpy()) - - t = Tensor.rand(16, 16).shard(devices_2, axis=0) - np.testing.assert_allclose(t.numpy(), t.clone().numpy()) - - def test_multi_const_folding(self): - with Context(TRACK_MATCH_STATS=0): - a = Tensor.arange(3).realize() - zeros = Tensor.zeros(3).realize() - b = a.to(devices_2)*zeros.to(devices_2) - sched = b.schedule() - self.assertEqual(len(sched), 0) - self.assertListEqual(b.tolist(), [0, 0, 0]) - -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestHandleData(unittest.TestCase): - def test_copied_to_device(self): - device = (d0, d1, d2, d3) - t = Tensor([1, 2, 3, 4]).shard(device).realize() - not_covered = t.to(d5) - sched = not_covered.schedule() - assert len(sched) == 1 - # setup again because create_schedule has side effect - t = Tensor([1, 2, 3, 4]).shard(device).realize() - not_covered = t.to(d5) - assert not_covered.realize().tolist() == [1, 2, 3, 4] - - for d in device: - t = Tensor([1, 2, 3, 4]).shard(device).realize() - covered = t.to(d) - sched = covered.schedule() - # TODO: this isn't optimized out anymore - #assert len(sched) == 0 - # setup again because create_schedule has side effect - t = Tensor([1, 2, 3, 4]).shard(device).realize() - covered = t.to(d) - assert covered.realize().tolist() == [1, 2, 3, 4] - -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestShrinkMultiTensorShardedAxis(unittest.TestCase): - # shrink a multitensor on sharded axis - def test_shrink_bad_args(self): - t = Tensor.arange(64).reshape(8, 8).contiguous().realize() - t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) - - with self.assertRaises(AssertionError): - # sharded axis shrink on non-device boundry is not allowed - a = t.shrink(((0, 3), (0, 8))) - a.schedule() - with self.assertRaises(AssertionError): - # cannot shrink sharded and non-sharded axis at the same time - a = t.shrink(((0, 2), (2, 4))) - a.schedule() - - a = t.shrink(((0, 2), (0, 8))) - a.schedule() - assert a.shape == (2, 8) - - p = a.pad(((0, 6), (0, 0))) - p.schedule() - assert p.shape == (8, 8) - - @given(strat.sampled_from([dtypes.float, dtypes.int, dtypes.int64, dtypes.int16])) - def test_ops(self, dtype): - if not is_dtype_supported(dtype): return - t = Tensor.arange(64).reshape(8, 8).contiguous().realize() - t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) - for i in range(4): - print(f"{i=}") - a = t.shrink(((0+2*i,2+2*i),None)) - b = Tensor(t.numpy()[0+2*i:2+2*i]) - assert a.shape == b.shape == (2, 8) - np.testing.assert_allclose(a.numpy(), b.numpy()) - # cast - np.testing.assert_allclose(a.float().numpy(), b.float().numpy()) - - # elementwise - np.testing.assert_allclose(a.exp().numpy(), b.exp().numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.reciprocal().numpy(), b.reciprocal().numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.pow(-0.5).numpy(), b.pow(-0.5).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose((a+a).numpy(), (b+b).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_equal((a+1).numpy(), (b+1).numpy()) - np.testing.assert_equal((1+a).numpy(), (1+b).numpy()) - np.testing.assert_allclose((a.where(a+a, a)).numpy(), (b.where(b+b, b)).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose((a.where(1, 0)).numpy(), (b.where(1, 0)).numpy(), rtol=1e-7, atol=1e-3) - - # reduce - np.testing.assert_allclose(a.max().numpy(), b.max().numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.sum().numpy(), b.sum().numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.mean().numpy(), b.mean().numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.max(0).numpy(), b.max(0).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.sum(0).numpy(), b.sum(0).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.mean(0).numpy(), b.mean(0).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.max(1).numpy(), b.max(1).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.sum(1).numpy(), b.sum(1).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.mean(1).numpy(), b.mean(1).numpy(), rtol=1e-7, atol=1e-3) - - # pad it back - np.testing.assert_allclose(a.pad(((2*i, 2*(4-i-1)), None)).numpy(), b.pad(((2*i, 2*(4-i-1)), None)).numpy(), rtol=1e-7, atol=1e-3) - - # other movement - np.testing.assert_allclose(a.pad((None, (1, 1))).numpy(), b.pad((None, (1, 1))).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.shrink((None, (1, 3))).numpy(), b.shrink((None, (1, 3))).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.permute((1, 0)).numpy(), b.permute((1, 0)).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.reshape((2, 2, 4)).numpy(), b.reshape((2, 2, 4)).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.reshape((2, 1, 8)).expand((2, 5, 8)).numpy(), b.reshape((2, 1, 8)).expand((2, 5, 8)).numpy(), rtol=1e-7, atol=1e-3) - np.testing.assert_allclose(a.flip(-1).numpy(), b.flip(-1).numpy(), rtol=1e-7, atol=1e-3) - - @unittest.skip("no longer supports uneven shard") - def test_uneven(self): - t = Tensor.arange(24).reshape(3, 8).contiguous().realize() - t.shard_([f"{Device.DEFAULT}:{i}" for i in range(2)], axis=0) - - a = t.shrink(((0, 2), None)) - b = t.shrink(((2, 3), None)) - na = t.numpy()[0:2] - nb = t.numpy()[2:3] - np.testing.assert_equal(a.numpy(), na) - np.testing.assert_equal(b.numpy(), nb) - np.testing.assert_equal((a+1).numpy(), na+1) - np.testing.assert_equal((b+1).numpy(), nb+1) - np.testing.assert_equal((1+a).numpy(), 1+na) - np.testing.assert_equal((1+b).numpy(), 1+nb) - np.testing.assert_equal((a+a).numpy(), na+na) - np.testing.assert_equal((b+b).numpy(), nb+nb) - - # @unittest.skip("why didn't this work?") - def test_add_two_partitions(self): - t = Tensor.arange(64).reshape(8, 8).contiguous().realize() - t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) - - a = t.shrink(((2, 4), None)) - b = t.shrink(((6, 8), None)) - na = t.numpy()[2:4] - nb = t.numpy()[6:8] - np.testing.assert_equal(a.numpy(), na) - np.testing.assert_equal(b.numpy(), nb) - np.testing.assert_equal((a+b).numpy(), na+nb) - c = a.pad(((2, 4), None)) + b.pad(((6, 0), None)) - c.realize() - expected = np.concatenate([np.zeros_like(t.numpy()[0:2]), na, np.zeros_like(t.numpy()[4:6]), nb]) - np.testing.assert_equal(c.numpy(), expected) - - def test_add_different_tensors(self): - devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] - x = Tensor.arange(64).reshape(8, 8).contiguous().realize().shard(devices, axis=0) - - to_add = [] - for i in range(len(devices)): - to_add.append((Tensor.ones(2, 8) * i).shard(devices)) - - added:list[Tensor] = [] - for bound, a in zip(x.uop.bounds, to_add): - added.append(x[bound[0]:bound[1]] + a) - - output = added[0].cat(*added[1:]) - expected = np.arange(64).reshape((8,8)) + np.array([[0,0,1,1,2,2,3,3] for _ in range(8)]).T - np.testing.assert_allclose(output.numpy(), expected) - -@unittest.skipIf(not_support_multi_device(), "no multi") -@unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") -class TestBatchNorm(unittest.TestCase): - def test_unsynced_backprop_conv_bn(self): - with Tensor.train(): - from extra.lr_scheduler import OneCycleLR - - convs = [nn.Conv2d(3, 16, 3), nn.Conv2d(3, 16, 3)] - bns = [nn.BatchNorm2d(16), nn.BatchNorm2d(16)] - - for p in get_parameters(convs + bns): - p.shard_((d1, d2)) - optim = nn.optim.Adam(get_parameters(convs + bns)) - lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) - lr_sched.step() - - fake_image = Tensor.rand((8, 3, 32, 32)).shard((d1, d2), axis=0) - - f1 = fake_image.shrink(((0, 4), None, None, None)) - f2 = fake_image.shrink(((4, 8), None, None, None)) - - out1 = bns[0](convs[0](f1)) - out2 = bns[1](convs[1](f2)) - out = out1.cat(out2) - optim.zero_grad() - out.mean().backward() - optim.step() - out.numpy() - - @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_unsynced_backprop_standalone_bn(self): - from extra.lr_scheduler import OneCycleLR - GPUS = (d1, d2) - - class BatchNorm: - def __init__(self, num_features): - self.bns:list[nn.BatchNorm2d] = [] - for _ in GPUS: - bn = nn.BatchNorm2d(num_features, track_running_stats=False, eps=1e-12, momentum=0.85, affine=True) - self.bns.append(bn) - - def __call__(self, x:Tensor): - bn_ts = [] - each = x.shape[0]//len(self.bns) - for i, bn in enumerate(self.bns): - xi = x.shrink(((each*(i), each*(i+1)), None, None, None)) - bni = bn(xi) - bn_ts.append(bni) - return bn_ts[0].cat(*bn_ts[1:]) - - with Tensor.train(): - conv = nn.Conv2d(3, 16, 3) - bn = BatchNorm(16) - - for p in get_parameters([conv, bn]): - p.shard_(GPUS) - optim = nn.optim.Adam(get_parameters([conv, bn])) - lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) - lr_sched.step() - - fake_image = Tensor.rand((8, 3, 32, 32)).shard(GPUS, axis=0) - - out = bn(conv(fake_image)) - optim.zero_grad() - out.mean().backward() - optim.step() - - def test_unsynced_backprop_sync_weights(self): - from extra.lr_scheduler import OneCycleLR - from examples.hlb_cifar10 import UnsyncedBatchNorm - GPUS = (d1, d2) - - with Tensor.train(): - conv = nn.Conv2d(3, 16, 3) - bn = UnsyncedBatchNorm(16, num_devices=len(GPUS)) - - for k, p in get_state_dict([conv, bn]).items(): - if 'running_mean' in k or 'running_var' in k: - p.shard_(GPUS, axis=0) - else: - p.to_(GPUS) - optim = nn.optim.Adam(get_parameters([conv, bn])) - lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) - lr_sched.step() - - fake_image = Tensor.rand((8, 3, 32, 32)).shard(GPUS, axis=0) - - out = bn(conv(fake_image)) - optim.zero_grad() - out.mean().backward() - optim.step() - - @given(strat.sampled_from((False, True))) - def test_batchnorm(self, is_training): - devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] - x = Tensor.arange(4096).reshape(8, 8, 8, 8).contiguous().realize().shard(devices, axis=0) - - with Tensor.train(is_training): - bns = [] - for _ in range(len(devices)): - bn = nn.BatchNorm2d(8) - for p in get_parameters(bn): - p.shard_(devices) - bn.weight.requires_grad = True - bn.bias.requires_grad = True - bns.append(bn) - - bn_ts = [] - for bound, bn in zip(x.uop.bounds, bns): - bni = bn(x[bound[0]:bound[1]]) - bn_ts.append(bni) - - bn_ts[0].cat(*bn_ts[1:]).numpy() - - def test_synced_vs_unsynced_bn(self): - from examples.hlb_cifar10 import UnsyncedBatchNorm - from tinygrad.nn import BatchNorm2d - devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] - x = Tensor.ones(8, 8, 8, 8).contiguous().realize().shard(devices, axis=0) - - with Tensor.train(): - synced_bn = BatchNorm2d(8) - unsynced_bn = UnsyncedBatchNorm(8, num_devices=len(devices)) - - for p in get_parameters(synced_bn): - p.shard_(devices) - for k, p in get_state_dict(unsynced_bn).items(): - if 'running_mean' in k or 'running_var' in k: - p.shard_(devices, axis=0) - else: - p.to_(devices) - - synced_out = synced_bn(x) - synced_si = list(synced_out.schedule()) - unsynced_out = unsynced_bn(x) - unsynced_si = list(unsynced_out.schedule()) - - # TODO: test synced / unsynced batchnorm cross device kernel and copies - assert synced_si - assert unsynced_si - -def helper_test_shard_op(shps, fxn, atol=1e-6, rtol=1e-3): - for shp in shps: - single_in = Tensor.randn(shp) - multi_in = single_in.shard(devices_2, axis=0) - - single_out = fxn(single_in).numpy() - multi_out = fxn(multi_in).numpy() - - try: - assert single_out.shape == multi_out.shape, f"shape mismatch: single={single_out.shape} | multi={multi_out.shape}" - assert single_out.dtype == multi_out.dtype, f"dtype mismatch: single={single_out.dtype} | multi={multi_out.dtype}" - np.testing.assert_allclose(single_out, multi_out, atol=atol, rtol=rtol) - except Exception as e: - raise Exception(f"Failed shape {single_out.shape}: {e}") - -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestTensorOps(unittest.TestCase): - def test_interpolate(self): - helper_test_shard_op([(4,16,16),(4,24,24)], lambda x: Tensor.interpolate(x, (19,19))) - - def test_bitcast(self): - helper_test_shard_op([(256,), (256,)], lambda x: x.bitcast(dtypes.int)) - -# TODO: make these tests pass with VIZ=1 -@unittest.skipIf(not_support_multi_device(), "no multi") -class TestMultiRamUsage(unittest.TestCase): - def setUp(self): - self.baseline = GlobalCounters.mem_used - self.N = 100 - def assertUsed(self, amt, strict=True): - used = GlobalCounters.mem_used - self.baseline - print(f"used {used} bytes") - if strict: self.assertEqual(used, amt) - else: self.assertLessEqual(used, amt) - - def test_zeros(self): - _ = Tensor.zeros(self.N, self.N).contiguous().realize() - self.assertUsed(self.N*self.N*4) - - def test_zeros_del(self): - _ = Tensor.zeros(self.N, self.N).contiguous().realize() - del _ - self.assertUsed(0) - - def test_zeros_copy(self): - _ = Tensor.zeros(self.N, self.N).contiguous().to(devices_2).realize() - # NOTE: the first one on the DEFAULT device should be freed - self.assertUsed(self.N*self.N*4*2) - - def test_zeros_shard(self, devices=(d1, d2)): - _ = Tensor.zeros(self.N, self.N).contiguous().shard(devices, axis=0).realize() - assert int(os.getenv("VIZ", "0")) == 0 - self.assertUsed(self.N*self.N*4) # sharding should not increase total ram usage - def test_zeros_shard_self(self): self.test_zeros_shard((d0, d1)) - - def test_zeros_contiguous_shard(self): - _ = Tensor.zeros(self.N, self.N).contiguous().shard(devices_2, axis=0).contiguous().realize() - assert int(os.getenv("VIZ", "0")) == 0 - self.assertUsed(self.N*self.N*4) # sharding should not increase total ram usage - -@unittest.skipIf(not_support_multi_device(), "need multi") -class TestMultiFromUnrenderable(unittest.TestCase): - def test_from_npy(self): - t = Tensor(np.arange(100, dtype=np.uint32)) - ll = t.shard((d0, d1), axis=0) + 1 - np.testing.assert_equal(ll.numpy(), np.arange(100)+1) - -@unittest.skipIf(not_support_multi_device(), "need multi") -class TestMultiAssign(unittest.TestCase): - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) - - def test_multi_assign_realized(self): - out = Tensor.zeros(4).shard(self.device, 0).contiguous().realize() - ones = Tensor.ones(4).shard(self.device, 0).contiguous().realize() - out.assign(ones).realize() - self.assertListEqual(out.tolist(), [1,1,1,1]) - - def test_multi_assign_unrealized(self): - out = Tensor.zeros(4).contiguous().realize().shard(self.device, 0) - ones = Tensor.ones(4).shard(self.device, 0).contiguous().realize() - out.assign(ones).realize() - self.assertListEqual(out.tolist(), [1,1,1,1]) - - def test_multi_assign_both_unrealized(self): - out = Tensor.zeros(4).contiguous().realize().shard(self.device, 0) - ones = Tensor.ones(4).contiguous().realize().shard(self.device, 0) - out.assign(ones).realize() - self.assertListEqual(out.tolist(), [1,1,1,1]) - - def test_multi_assign_piece(self): - out = Tensor.zeros(4,4).shard(self.device, 0).contiguous().realize() - ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() - out[:, 2:3].assign(ones).realize() - self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) - - def test_multi_assign_piece_noncontig(self): - out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0).realize() - ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() - out[:, 2:3].assign(ones).realize() - self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) - - @unittest.expectedFailure - def test_multi_assign_piece_unrealized(self): - out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0) - ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() - out[:, 2:3].assign(ones).realize() - self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) - - def test_multi_assign_var_offset(self): - out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0).realize() - ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() - vi = Variable("i", 0, 3).bind(2) - out[:, vi:vi+1].assign(ones).realize() - self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) - - def test_multi_assign_var_offset_jit_none(self): self.test_multi_assign_var_offset_jit(None) - def test_multi_assign_var_offset_jit(self, shard_axis=0): - out = Tensor.zeros(4,6).contiguous().realize().shard(self.device, shard_axis).realize() - ones = Tensor.ones(4,1).shard(self.device, shard_axis).contiguous().realize() - - @TinyJit - def f(out:Tensor, vi): - out[:, vi:vi+1].assign(ones).realize() - ones.assign(ones+1).realize() - - vi = Variable("i", 0, 5) - for i in range(1,5): - GlobalCounters.reset() - f(out, vi.bind(i)) - self.assertListEqual(out.tolist(), [[0,1,2,3,4,0]]*4) - -@unittest.skipIf(not_support_multi_device(), "need multi") -class TestMultiTransformer(unittest.TestCase): - def test_transformer(self): - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) - - from extra.models.llama import Transformer - args = {"dim": 32, "n_heads": 1, "n_kv_heads": 1, "n_layers": 2, "norm_eps": 1e-5, "rope_theta": 500000, "vocab_size": 1024, - "hidden_dim": 32, "max_context": 12} - real_model = Transformer(**args) - shard_model = Transformer(**args) - - # copy state - nn.state.load_state_dict(shard_model, nn.state.get_state_dict(real_model)) - - # shard - for k,v in nn.state.get_state_dict(shard_model).items(): - if 'scale' in k: v.shard_(device, axis=None) # from quantized - elif '.attention.' in k: v.shard_(device, axis=-1) - elif '.feed_forward.w1.' in k: v.shard_(device, axis=0) - elif '.feed_forward.w3.' in k: v.shard_(device, axis=0) - elif '.feed_forward.' in k: v.shard_(device, axis=-1) - elif 'tok_embeddings.weight' in k: v.shard_(device, axis=0) - elif 'output.weight' in k: v.shard_(device, axis=0) - else: v.shard_(device, axis=None) - - last_tok = 0 - for i in range(10): - real_tok = real_model(Tensor([[last_tok]], device=Device.DEFAULT), i).item() - shard_tok = shard_model(Tensor([[last_tok]], device=device), i).item() - - # test kv cache - kv1 = real_model.layers[0].attention.cache_kv.numpy() - kv2 = shard_model.layers[0].attention.cache_kv.numpy() - #print(np.concatenate([kv1[:, :, :, :, 0:1], kv2[:, :, :, :, 0:1]], axis=4)) - np.testing.assert_allclose(kv1, kv2, atol=1e-5, rtol=1e-5, err_msg=f"issue at token {i}") - - # test token - self.assertEqual(real_tok, shard_tok, f"issue at token {i}") - last_tok = real_tok - - @unittest.skip("super slow") - def test_llama1b_full(self): - from tinygrad.helpers import fetch - fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir="llama3-1b-instruct") - model = fetch("https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-Q6_K.gguf", - "Llama-3.2-1B-Instruct-Q6_K.gguf", subdir="llama3-1b-instruct") - - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) - from examples.llama3 import build_transformer - real_model = build_transformer(model, model_size="1B", device=Device.DEFAULT) - shard_model = build_transformer(model, model_size="1B", device=device) - - last_tok = 0 - real_tok = real_model(Tensor([[last_tok]], device=Device.DEFAULT), 0) - shard_tok = shard_model(Tensor([[last_tok]], device=device), 0) - self.assertEqual(real_tok.item(), shard_tok.item()) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_net_speed.py b/tinygrad/test/test_net_speed.py deleted file mode 100644 index 9344ebe7..00000000 --- a/tinygrad/test/test_net_speed.py +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env python -import time -import unittest -import torch -from tinygrad import Tensor, Device -from tinygrad.helpers import Profiling, CI - -@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") -class TestConvSpeed(unittest.TestCase): - - def test_mnist(self): - # https://keras.io/examples/vision/mnist_convnet/ - conv = 3 - inter_chan, out_chan = 32, 64 - - # ****** torch baseline ******* - - torch.backends.mkldnn.enabled = False - - conv = 3 - inter_chan, out_chan = 32, 64 - c1 = torch.randn(inter_chan,1,conv,conv, requires_grad=True) - c2 = torch.randn(out_chan,inter_chan,conv,conv, requires_grad=True) - l1 = torch.randn(out_chan*5*5, 10, requires_grad=True) - - c2d = torch.nn.functional.conv2d - mp = torch.nn.MaxPool2d((2,2)) - lsm = torch.nn.LogSoftmax(dim=1) - - cnt = 5 - fpt, bpt = 0.0, 0.0 - for i in range(cnt): - et0 = time.time() - x = torch.randn(128, 1, 28, 28, requires_grad=True) - x = mp(c2d(x,c1).relu()) - x = mp(c2d(x,c2).relu()) - x = x.reshape(x.shape[0], -1) - out = lsm(x.matmul(l1)) - out = out.mean() - et1 = time.time() - out.backward() - et2 = time.time() - fpt += (et1-et0) - bpt += (et2-et1) - - fpt_baseline = (fpt*1000/cnt) - bpt_baseline = (bpt*1000/cnt) - print("torch forward pass: %.3f ms" % fpt_baseline) - print("torch backward pass: %.3f ms" % bpt_baseline) - - # ****** tinygrad compare ******* - - c1 = Tensor(c1.detach().numpy(), requires_grad=True) - c2 = Tensor(c2.detach().numpy(), requires_grad=True) - l1 = Tensor(l1.detach().numpy(), requires_grad=True) - - cnt = 5 - fpt, bpt = 0.0, 0.0 - for i in range(1+cnt): - et0 = time.time() - x = Tensor.randn(128, 1, 28, 28) - x = x.conv2d(c1).relu().avg_pool2d() - x = x.conv2d(c2).relu().max_pool2d() - x = x.reshape(shape=(x.shape[0], -1)) - out = x.dot(l1).log_softmax() - out = out.mean() - out.backward() # NOTE: we have to now compute this here, but it doesn't realize - out.realize() - et1 = time.time() - [x.grad.realize() for x in [c1, c2, l1]] - et2 = time.time() - if i == 0: - pr = Profiling(sort='time', frac=0.2) - pr.__enter__() - else: - fpt += (et1-et0) - bpt += (et2-et1) - - pr.__exit__() - fpt = (fpt*1000/cnt) - bpt = (bpt*1000/cnt) - print("forward pass: %.3f ms, %.2fx off baseline %.3f ms" % (fpt, fpt/fpt_baseline, fpt_baseline)) - print("backward pass: %.3f ms, %.2fx off baseline %.3f ms" % (bpt, bpt/bpt_baseline, bpt_baseline)) - - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_nn.py b/tinygrad/test/test_nn.py deleted file mode 100755 index 000e4591..00000000 --- a/tinygrad/test/test_nn.py +++ /dev/null @@ -1,709 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -import torch -from tinygrad import Tensor, Device, TinyJit -from tinygrad.uop.ops import Ops -from tinygrad.helpers import GlobalCounters, CI, Context, OSX -from tinygrad.nn import Conv1d, ConvTranspose1d, Conv2d, ConvTranspose2d, Linear, Embedding -from tinygrad.nn import BatchNorm, LayerNorm, LayerNorm2d, GroupNorm, InstanceNorm, RMSNorm, LSTMCell -from tinygrad.nn.state import load_state_dict -from tinygrad.engine.realize import run_schedule -from test.helpers import not_support_multi_device - -@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") -class TestNN(unittest.TestCase): - def test_sparse_cat_cross_entropy(self): - # create in tinygrad - input_tensor = Tensor.randn(6, 5) # not square to test that mean scaling uses the correct dimension - target = Tensor([0, 0, 0, 1, 2, 3]) # torch doesn't support target=-1 - torch_input = torch.tensor(input_tensor.numpy()) - torch_target = torch.tensor(target.numpy(), dtype=torch.long) - - for smoothing in [0.0, 0.1, 0.5, 1.0]: - for ignore_index in [-1, 0, 2]: - for reduction in ["none", "sum", "mean"]: - loss = input_tensor.sparse_categorical_crossentropy(target, label_smoothing=smoothing, ignore_index=ignore_index, reduction=reduction) - torch_loss = torch.nn.CrossEntropyLoss(reduction=reduction, label_smoothing=smoothing, ignore_index=ignore_index)(torch_input, torch_target) - np.testing.assert_allclose(loss.numpy(), torch_loss.detach().numpy(), atol=1e-5, rtol=1e-6) - - # also test with a batch dimension (of size 1) - loss = input_tensor.unsqueeze(0).sparse_categorical_crossentropy( - target.unsqueeze(0), label_smoothing=smoothing, ignore_index=ignore_index, reduction=reduction - ) - torch_loss = torch.nn.CrossEntropyLoss(reduction=reduction, label_smoothing=smoothing, ignore_index=ignore_index)( - torch_input.unsqueeze(0).permute(0,2,1), torch_target.unsqueeze(0) - ) - np.testing.assert_allclose(loss.numpy(), torch_loss.detach().numpy(), atol=1e-5, rtol=1e-6) - - def test_batchnorm2d(self, training=False, threed=False, track_running_stats=True): - with Tensor.train(training): - szs = [4, 8, 16, 32] - for sz in szs: - # create in tinygrad - bn = BatchNorm(sz, eps=1e-5, track_running_stats=track_running_stats) - bn.weight = Tensor.randn(sz) - bn.bias = Tensor.randn(sz) - if track_running_stats: - bn.running_mean = Tensor.randn(sz) - bn.running_var = Tensor.randn(sz) - bn.running_var.numpy()[bn.running_var.numpy() < 0] = 0 - - # create in torch - with torch.no_grad(): - if threed: - tbn = torch.nn.BatchNorm3d(sz, track_running_stats=track_running_stats).eval() - else: - tbn = torch.nn.BatchNorm2d(sz, track_running_stats=track_running_stats).eval() - tbn.training = training - tbn.weight[:] = torch.tensor(bn.weight.numpy()) - tbn.bias[:] = torch.tensor(bn.bias.numpy()) - if track_running_stats: - tbn.running_mean[:] = torch.tensor(bn.running_mean.numpy()) - tbn.running_var[:] = torch.tensor(bn.running_var.numpy()) - - if track_running_stats: - np.testing.assert_allclose(bn.running_mean.numpy(), tbn.running_mean.detach().numpy(), rtol=1e-5, atol=1e-6) - np.testing.assert_allclose(bn.running_var.numpy(), tbn.running_var.detach().numpy(), rtol=1e-5, atol=1e-6) - - # trial - if threed: - inn = Tensor.randn(2, sz, 3, 3, 3) - else: - inn = Tensor.randn(2, sz, 3, 3) - - # in tinygrad - outt = bn(inn) - - # in torch - toutt = tbn(torch.tensor(inn.numpy())) - - # close - np.testing.assert_allclose(outt.numpy(), toutt.detach().numpy(), rtol=5e-4, atol=1e-6) - if track_running_stats: - np.testing.assert_allclose(bn.running_mean.numpy(), tbn.running_mean.detach().numpy(), rtol=1e-5, atol=1e-6) - np.testing.assert_allclose(bn.running_var.numpy(), tbn.running_var.detach().numpy(), rtol=1e-5, atol=1e-6) - - def test_batchnorm2d_training(self): self.test_batchnorm2d(True, False, True) - def test_batchnorm2d_no_running_stats(self): self.test_batchnorm2d(False, False, False) - def test_batchnorm2d_training_no_running_stats(self): self.test_batchnorm2d(True, False, False) - def test_batchnorm3d(self): self.test_batchnorm2d(False, True, True) - def test_batchnorm3d_training(self): self.test_batchnorm2d(True, True, True) - def test_batchnorm3d_no_running_stats(self): self.test_batchnorm2d(False, True, False) - def test_batchnorm3d_training_no_running_stats(self): self.test_batchnorm2d(True, True, False) - - def test_batchnorm_axis(self): - sz = (2, 4, 3, 2, 2) - x = Tensor.randn(sz) - weight = Tensor.randn(2, 3) - bias = Tensor.randn(2, 3) - mean = Tensor.randn(2, 3) - invstd = Tensor.randn(2, 3) - a = (x.batchnorm(weight, bias, mean, invstd, axis=(0, 2)) - .permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2)) - b = (x.permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2) - .batchnorm(weight.flatten(), bias.flatten(), mean.flatten(), invstd.flatten())) - t_x = torch.tensor(x.permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2).numpy()) - t_weight, t_bias = torch.tensor(weight.flatten().numpy()), torch.tensor(bias.flatten().numpy()) - t_mean, t_invstd = torch.tensor(mean.flatten().numpy()), torch.tensor(invstd.flatten().numpy()) - torch.nn.functional.batch_norm(t_x, t_mean, 1.0 / t_invstd**2, t_weight, t_bias) - - np.testing.assert_allclose(a.numpy(), b.numpy()) - - def test_linear(self): - def _test_linear(x, in_dim, out_dim): - # create in tinygrad - model = Linear(in_dim, out_dim) - z = model(x) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.Linear(in_dim, out_dim).eval() - torch_layer.weight[:] = torch.tensor(model.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(model.bias.numpy(), dtype=torch.float32) - torch_x = torch.tensor(x.numpy(), dtype=torch.float32) - torch_z = torch_layer(torch_x) - - # test - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - BS, T, in_dim, out_dim = 4, 2, 8, 16 - _test_linear(Tensor.randn(BS, in_dim), in_dim, out_dim) - _test_linear(Tensor.randn(BS, T, in_dim), in_dim, out_dim) # test with more dims - - def test_conv1d(self): - BS, C1, W = 4, 16, 224//4 - C2, K, S, P = 64, 7, 2, 1 - - # create in tinygrad - layer = Conv1d(C1, C2, kernel_size=K, stride=S, padding=P) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.Conv1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - def test_conv2d(self): - BS, C1, H, W = 4, 16, 224//4, 224//4 - C2, K, S, P = 64, 7, 2, 1 - - # create in tinygrad - layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=P) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, H, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - def test_conv1d_same_padding(self): - BS, C1, W = 8, 3, 32 - C2, K, S, P = 16, 3, 1, 'same' - - # create in tinygrad - layer = Conv1d(C1, C2, kernel_size=K, stride=S, padding=P) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.Conv1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - def _run_conv2d_same_padding_test(self, BS, C1, C2, H, W, K, S, padding='same', D=1): - # create in tinygrad - layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=padding, dilation=D) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=padding, dilation=D).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, H, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - def test_conv2d_same_padding_odd_input(self): - BS, C1, H, W = 16, 16, 29, 31 - C2, K, S, P = 32, 5, 1, 'same' - self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P) - - def test_conv2d_same_padding_large_kernel(self): - BS, C1, H, W = 16, 16, 28, 33 - C2, K, S, P = 32, 9, 1, 'same' - self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P) - - def test_conv2d_same_padding_with_dilation(self): - BS, C1, H, W = 16, 3, 28, 28 - C2, K, S, P, D = 32, 3, 1, 'same', 3 - self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P, D) - - def test_conv2d_same_padding_invalid_stride(self): - C1, C2, K, S, P = 16, 32, 2, 2, 'same' - self.assertRaises(ValueError, Conv2d, C1, C2, kernel_size=K, stride=S, padding=P) - - def test_conv2d_same_padding_invalid_padding_str(self): - C1, C2, K, S, P = 16, 32, 2, 1, 'not_same' - self.assertRaises(ValueError, Conv2d, C1, C2, kernel_size=K, stride=S, padding=P) - - @unittest.skip("Takes too long to compile for Compiled backends") - def test_conv2d_winograd(self): - BS, C1, H, W = 2, 8, 16, 16 - C2, K, S, P = 8, 3, 1, 1 - - # create in tinygrad - layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=P) - layer.weight.requires_grad = True - layer.bias.requires_grad = True - - # create in torch - torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight = torch.nn.Parameter(torch.tensor(layer.weight.numpy(), dtype=torch.float32)) - torch_layer.bias = torch.nn.Parameter(torch.tensor(layer.bias.numpy(), dtype=torch.float32)) - - # test - x = Tensor.uniform(BS, C1, H, W, requires_grad=True) - - with Context(WINO=1): - z = layer(x) - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - m = z.mean() - m.backward() - gw = layer.weight.grad.realize() - gb = layer.bias.grad.realize() - gx = x.grad.realize() - - torch_z.mean().backward() - np.testing.assert_allclose(gw.numpy(), torch_layer.weight.grad.numpy(), atol=5e-4, rtol=1e-5) - np.testing.assert_allclose(gb.numpy(), torch_layer.bias.grad.numpy(), atol=5e-4, rtol=1e-5) - np.testing.assert_allclose(gx.numpy(), torch_x.grad.numpy(), atol=5e-4, rtol=1e-5) - - def test_conv_transpose1d(self): - BS, C1, W = 4, 16, 224//4 - C2, K, S, P = 64, 7, 2, 1 - - # create in tinygrad - layer = ConvTranspose1d(C1, C2, kernel_size=K, stride=S, padding=P) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.ConvTranspose1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - def test_conv_transpose2d(self): - BS, C1, H, W = 4, 16, 224//4, 224//4 - C2, K, S, P = 64, 7, 2, 1 - - # create in tinygrad - layer = ConvTranspose2d(C1, C2, kernel_size=K, stride=S, padding=P) - - # create in torch - with torch.no_grad(): - torch_layer = torch.nn.ConvTranspose2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) - - # test - x = Tensor.uniform(BS, C1, H, W) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_groupnorm(self): - BS, H, W, C, G = 20, 10, 10, 6, 3 - - # create in torch - torch_layer = torch.nn.GroupNorm(G, C).eval() - - # create in tinygrad - layer = GroupNorm(G, C) - layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) - layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) - - for _ in range(10): - # forward - x = Tensor.randn(BS, C, H, W, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_layernorm(self): - N, C, H, W = 20, 5, 10, 10 - - # create in torch - torch_layer = torch.nn.LayerNorm([H, W]).eval() - - # create in tinygrad - layer = LayerNorm([H, W]) - layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) - layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) - - for _ in range(10): - # forward - x = Tensor.randn(N, C, H, W, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_layernorm_2d(self): - N, C, H, W = 20, 5, 10, 10 - - # create in torch - torch_layer = torch.nn.LayerNorm([C]).eval() - - # create in tinygrad - layer = LayerNorm2d(C) - layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) - layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) - - for _ in range(10): - # forward - x = Tensor.randn(N, C, H, W, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x.permute(0,2,3,1)).permute(0,3,1,2) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_instancenorm_2d(self): - N, C, H, W = 20, 10, 10, 10 - - # create in torch - torch_layer = torch.nn.InstanceNorm2d(C, affine=True).eval() - - # create in tinygrad - layer = InstanceNorm(C) - layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) - layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) - - for _ in range(10): - # forward - x = Tensor.randn(N, C, H, W, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_instancenorm_3d(self): - N, C, D, H, W = 20, 10, 10, 10, 10 - - # create in torch - torch_layer = torch.nn.InstanceNorm3d(C, affine=True).eval() - - # create in tinygrad - layer = InstanceNorm(C) - layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) - layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) - - for _ in range(10): - # forward - x = Tensor.randn(N, C, D, H, W, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=2e-3, rtol=1e-3) - np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_rmsnorm(self): - class TorchRMSNorm(torch.nn.Module): - # https://github.com/meta-llama/llama/blob/be327c427cc5e89cc1d3ab3d3fec4484df771245/llama/model.py#L34C1-L77C36 - def __init__(self, dim: int, eps: float = 1e-6, elementwise_affine: bool = True): - super().__init__() - self.eps = eps - self.elementwise_affine = elementwise_affine - self.weight = torch.nn.Parameter(torch.ones(dim)) if elementwise_affine else None - - def _norm(self, x): - return x * torch.rsqrt(x.pow(2).mean(-1, keepdim=True) + self.eps) - - def forward(self, x): - output = self._norm(x.float()).type_as(x) - return output if self.weight is None else output * self.weight - - B, T, embed_size = 4, 10, 20 - torch_layer = TorchRMSNorm(embed_size) - layer = RMSNorm(embed_size) - layer.weight.requires_grad = True - - for _ in range(10): - # forward - x = Tensor.randn(B, T, embed_size, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=2e-3, rtol=1e-3) - - torch_layer = TorchRMSNorm(embed_size, elementwise_affine=False) - layer = RMSNorm(embed_size, elementwise_affine=False) - - for _ in range(10): - # forward - x = Tensor.randn(B, T, embed_size, requires_grad=True) - z = layer(x) - z.sum().backward() - - torch_x = torch.tensor(x.numpy(), requires_grad=True) - torch_z = torch_layer(torch_x) - torch_z.sum().backward() - - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) - np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) - - def test_embedding(self): - B, T, embed_size, vocab_size = 4, 10, 20, 28 - - # create in tinygrad - layer = Embedding(vocab_size, embed_size) - - with torch.no_grad(): - torch_layer = torch.nn.Embedding(vocab_size, embed_size).eval() - torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) - - # test - x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) - - # test with empty input length - x = Tensor(np.random.randint(0, vocab_size, (B, 0), dtype=np.int32)) - z = layer(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) - - # test with jit enabled - @TinyJit - def layer_jit(x): - return layer(x).realize() - - for _ in range(3): - x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) - z = layer_jit(x) - torch_x = torch.tensor(x.numpy()) - torch_z = torch_layer(torch_x) - np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) - - def test_embedding_one_kernel(self, ops=41410, kcount=3): - GlobalCounters.reset() - layer = Embedding(20, 30) - layer.weight = Tensor.zeros_like(layer.weight).contiguous() - a = Tensor([[1, 5, 9, 11], - [12, 19, 8, 1]]) - result = layer(a) - schedule = result.schedule() - self.assertEqual(kcount, len([item for item in schedule if item.ast.op is Ops.SINK]), "first run realizes weight and embedding") - run_schedule(schedule) - - b = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - result = layer(b) - schedule = result.schedule() - self.assertEqual(1, len([item for item in schedule if item.ast.op is Ops.SINK]), "second run realizes embedding only") - run_schedule(schedule) - print(f"Embedding used {GlobalCounters.global_ops} ops") - self.assertLessEqual(GlobalCounters.global_ops, ops) - - # TODO: fused with opts uses more ops - def test_embedding_one_kernel_fused(self): - with Context(FUSE_ARANGE=1, NOOPT=0): - self.test_embedding_one_kernel(ops=612_000, kcount=2) - - def test_embedding_one_kernel_fused_noopt(self): - with Context(FUSE_ARANGE=1, NOOPT=1): - self.test_embedding_one_kernel(ops=0, kcount=2) - - def test_embedding_shape(self): - vocab_size, embed_size = 10, 16 - layer = Embedding(vocab_size, embed_size) - for rank in range(5): - shp = (1,) * rank - a = Tensor([3]).reshape(shp) - result = layer(a) - self.assertEqual(result.shape, shp + (embed_size,)) - - def test_load_state_dict(self): - layer = Conv2d(3, 5, kernel_size=3) - - state_dict = { - 'weight': Tensor.randn(5, 3, 3, 3), - 'bias': Tensor.randn(5), - } - load_state_dict(layer, state_dict) - - np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) - np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_load_state_dict_sharded_model(self): - devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") - - layer = Conv2d(3, 5, kernel_size=3) - layer.weight.shard_(devices, 3) - layer.bias.shard_(devices, None) - state_dict = { - 'weight': Tensor.randn(5, 3, 3, 3).realize(), - 'bias': Tensor.randn(5).realize(), - } - load_state_dict(layer, state_dict) - - # sharded model shards the state_dict - self.assertEqual(layer.weight.device, devices) - self.assertEqual(layer.weight.uop.axis, 3) - self.assertEqual(layer.bias.device, devices) - self.assertEqual(layer.bias.uop.axis, None) - np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) - np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) - - @unittest.skipIf(not_support_multi_device, "no multi") - def test_load_state_dict_sharded_dict(self): - devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") - - layer = Conv2d(3, 5, kernel_size=3) - state_dict = { - 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, 3), - 'bias': Tensor.randn(5).shard(devices, None), - } - load_state_dict(layer, state_dict) - - # NOTE: model is not sharded, still not sharded after load_state_dict - self.assertEqual(layer.weight.device, Device.DEFAULT) - self.assertEqual(layer.bias.device, Device.DEFAULT) - np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) - np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_load_state_dict_sharded_model_dict_same_axis(self): - devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") - - layer = Conv2d(3, 5, kernel_size=3) - layer.weight.shard_(devices, 3) - layer.bias.shard_(devices, None) - - state_dict = { - 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, 3), - 'bias': Tensor.randn(5).shard(devices, None), - } - load_state_dict(layer, state_dict) - - self.assertEqual(layer.weight.device, devices) - self.assertEqual(layer.weight.uop.axis, 3) - self.assertEqual(layer.bias.device, devices) - self.assertEqual(layer.bias.uop.axis, None) - np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) - np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) - - @unittest.skipIf(not_support_multi_device, "no multi") - def test_load_state_dict_sharded_model_dict_different_axis(self): - devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") - devices5 = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3", f"{Device.DEFAULT}:4", f"{Device.DEFAULT}:5") - - layer = Conv2d(3, 5, kernel_size=3) - layer.weight.shard_(devices, 3) - layer.bias.shard_(devices, None) - - # different shard axis - state_dict = { - 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, None), - 'bias': Tensor.randn(5).shard(devices5, 0), - } - load_state_dict(layer, state_dict) - - # NOTE: model and state_dict shard differently, use the state_dict sharding # TODO: revisit this? - self.assertEqual(layer.weight.device, devices) - self.assertEqual(layer.weight.uop.axis, None) - self.assertEqual(layer.bias.device, devices5) - self.assertEqual(layer.bias.uop.axis, 0) - np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) - np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) - - def test_load_state_dict_shape_mismatch(self): - d1, d2 = 2, 4 - layer = Linear(d1, d1, bias=False) - state_dict = {'weight': Tensor.randn(d2, d2)} - with self.assertRaisesRegex(ValueError, r'Shape mismatch in layer `weight`: Expected shape \(2, 2\), but found \(4, 4\) in state dict.'): - load_state_dict(layer, state_dict) - - def test_lstm_cell(self): - layer = LSTMCell(32, 16) - with torch.no_grad(): - torch_layer = torch.nn.LSTMCell(32, 16) - layer.weight_hh.assign(torch_layer.weight_hh.numpy()) - layer.weight_ih.assign(torch_layer.weight_ih.numpy()) - layer.bias_hh.assign(torch_layer.bias_hh.numpy()) - layer.bias_ih.assign(torch_layer.bias_ih.numpy()) - - inp = Tensor.randn(1, 32) - out_h, out_c = layer(inp) - torch_out_h, torch_out_c = torch_layer(torch.tensor(inp.numpy())) - np.testing.assert_allclose(out_h.numpy(), torch_out_h.numpy(), atol=1e-6) - np.testing.assert_allclose(out_c.numpy(), torch_out_c.numpy(), atol=1e-6) - - out_h, out_c = layer(inp, (out_h, out_c)) - torch_out_h, torch_out_c = torch_layer(torch.tensor(inp.numpy()), (torch_out_h, torch_out_c)) - np.testing.assert_allclose(out_h.numpy(), torch_out_h.numpy(), atol=1e-6) - np.testing.assert_allclose(out_c.numpy(), torch_out_c.numpy(), atol=1e-6) - - def test_lstm_cell_no_bias(self): - layer = LSTMCell(32, 16, bias=False) - inp = Tensor.randn(1, 32) - out_h, out_c = layer(inp) - out_h.realize() - out_c.realize() - h = Tensor.randn(1, 16) - c = Tensor.randn(1, 16) - out_h, out_c = layer(inp, (h, c)) - out_h.realize() - out_c.realize() - assert layer.bias_hh is None - assert layer.bias_ih is None - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_ocl.py b/tinygrad/test/test_ocl.py deleted file mode 100644 index 04b8e252..00000000 --- a/tinygrad/test/test_ocl.py +++ /dev/null @@ -1,31 +0,0 @@ -import unittest -from tinygrad import Device -from tinygrad.device import Buffer -from tinygrad.dtype import dtypes -from tinygrad.helpers import CI -from tinygrad.runtime.ops_gpu import CLDevice, CLAllocator, CLCompiler, CLProgram - -@unittest.skipUnless(Device.DEFAULT == "GPU", "Runs only on OpenCL (GPU)") -class TestCLError(unittest.TestCase): - @unittest.skipIf(CI, "dangerous for CI, it allocates tons of memory") - def test_oom(self): - with self.assertRaises(RuntimeError) as err: - allocator = CLAllocator(CLDevice()) - for i in range(1_000_000): - allocator.alloc(1_000_000_000) - assert str(err.exception) == "OpenCL Error -6: CL_OUT_OF_HOST_MEMORY" - - def test_invalid_kernel_name(self): - device = Device[Device.DEFAULT] - with self.assertRaises(RuntimeError) as err: - CLProgram(device, name="", lib=CLCompiler(device, "test").compile("__kernel void test(__global int* a) { a[0] = 1; }")) - assert str(err.exception) == "OpenCL Error -46: CL_INVALID_KERNEL_NAME" - - def test_unaligned_copy(self): - data = list(range(65)) - unaligned = memoryview(bytearray(data))[1:] - buffer = Buffer("GPU", 64, dtypes.uint8).allocate() - buffer.copyin(unaligned) - result = memoryview(bytearray(len(data) - 1)) - buffer.copyout(result) - assert unaligned == result, "Unaligned data copied in must be equal to data copied out." diff --git a/tinygrad/test/test_ops.py b/tinygrad/test/test_ops.py deleted file mode 100644 index 46a89dd8..00000000 --- a/tinygrad/test/test_ops.py +++ /dev/null @@ -1,3041 +0,0 @@ -import time, math, unittest, functools -import numpy as np -from typing import List, Callable -import torch -import warnings -from tinygrad.helpers import getenv, IMAGE, DEBUG, CI, Context, TRANSCENDENTAL, DEVECTORIZE, OSX -from tinygrad import Tensor, Device, dtypes -from tinygrad.tensor import _to_np_dtype -from tinygrad.device import is_dtype_supported - -if getenv("TINY_BACKEND"): - import tinygrad.frontend.torch # noqa: F401 # pylint: disable=unused-import - torch.set_default_device("tiny") - -if CI: - warnings.filterwarnings("ignore", message="Non-empty compiler output encountered") - -FORWARD_ONLY = getenv("FORWARD_ONLY", 0) -PRINT_TENSORS = getenv("PRINT_TENSORS", 0) - -def helper_test_op(shps, torch_fxn, tinygrad_fxn=None, atol=1e-6, rtol=1e-3, grad_atol=1e-4, grad_rtol=1e-3, - forward_only=False, vals=None, low=-2, high=2): - if tinygrad_fxn is None: tinygrad_fxn = torch_fxn - ts, tst = prepare_test_op(low, high, shps, vals, forward_only) - - st = time.monotonic() - out = torch_fxn(*ts) - torch_fp = time.monotonic() - st - - # move inputs to a different device, test the device of intermediate tensors are correct - if mt:=getenv("MOVE_TENSOR", ""): - for t in tst: t.to_(mt) - - st = time.monotonic() - ret = tinygrad_fxn(*tst).realize() - tinygrad_fp = time.monotonic() - st - - def compare(s, tinygrad_output, torch_output, atol, rtol): - if PRINT_TENSORS: print(s, tinygrad_output, torch_output) - try: - assert tinygrad_output.shape == torch_output.shape, f"shape mismatch: tinygrad={tinygrad_output.shape} | torch={torch_output.shape}" - assert tinygrad_output.dtype == torch_output.dtype, f"dtype mismatch: tinygrad={tinygrad_output.dtype} | torch={torch_output.dtype}" - if np.issubdtype(tinygrad_output.dtype, np.floating): - np.testing.assert_allclose(tinygrad_output, torch_output, atol=atol, rtol=rtol) - else: - np.testing.assert_equal(tinygrad_output, torch_output) - except Exception as e: - raise Exception(f"{s} failed shape {tinygrad_output.shape}: {e}") - - if DEBUG >= 6: - np.set_printoptions(linewidth=200, suppress=True) - print(ret.numpy()) - print(out.detach().cpu().numpy()) - compare("forward pass", ret.numpy(), out.detach().cpu().numpy(), atol=atol, rtol=rtol) - - torch_fbp, tinygrad_fbp = np.nan, np.nan - if not forward_only and not FORWARD_ONLY and ts and tst: - st = time.monotonic() - torch_grads = torch.autograd.grad(torch_fxn(*ts).sum(), ts) - torch_fbp = time.monotonic() - st - - st = time.monotonic() - # NOTE: we now have to recompute the forward pass since we realized it - tiny_grads = tinygrad_fxn(*tst).sum().gradient(*tst) - Tensor.realize(*tiny_grads) - tinygrad_fbp = time.monotonic() - st - - for i, (t, torch_grad) in enumerate(zip(tiny_grads, torch_grads)): - compare(f"backward pass tensor {i}", t.numpy(), torch_grad.detach().cpu().numpy(), atol=grad_atol, rtol=grad_rtol) - - if not CI: - print("\ntesting %40r torch/tinygrad fp: %.2f / %.2f ms bp: %.2f / %.2f ms " % \ - (shps, torch_fp*1000, tinygrad_fp*1000, torch_fbp*1000, tinygrad_fbp*1000), end="") - -def prepare_test_op(low, high, shps, vals, forward_only=False): - if shps is None: - ts = [torch.tensor(x, requires_grad=(not forward_only)) for x in vals] - else: - np.random.seed(0) - np_data = [np.random.uniform(low=low, high=high, size=size).astype(_to_np_dtype(dtypes.default_float)) for size in shps] - ts = [torch.tensor(data, requires_grad=(not forward_only)) for data in np_data] - for i in range(len(ts)): - # NOTE: torch default int64 for python ints input - if ts[i].dtype == torch.int64: ts[i] = ts[i].type(torch.int32) - tst = [Tensor(x.detach().cpu().numpy(), requires_grad=(not forward_only and not FORWARD_ONLY)) for x in ts] - return ts, tst - -class TestOps(unittest.TestCase): - - def helper_test_exception(self, shps, torch_fxn, tinygrad_fxn, expected, forward_only=False, exact=False, vals=None, low=-1.5, high=1.5): - if getenv("MOCKGPU") and Device.DEFAULT == "NV": self.skipTest('helper_test_exception fails in CI CUDA') - ts, tst = prepare_test_op(low, high, shps, vals, forward_only) - with self.assertRaises(expected) as torch_cm: - torch_fxn(*ts) - with self.assertRaises(expected) as tinygrad_cm: - tinygrad_fxn(*tst) - if exact: self.assertEqual(str(torch_cm.exception), str(tinygrad_cm.exception)) - if not CI: print("\ntesting %40r torch/tinygrad exception: %s / %s" % (shps, torch_cm.exception, tinygrad_cm.exception), end="") - - def test_full_like(self): - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) - helper_test_op([], lambda: torch.full_like(b, 4), lambda: Tensor.full_like(a, 4), forward_only=True) - - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) - helper_test_op([], lambda: torch.full_like(b, 4), lambda: Tensor.full_like(a, 4), forward_only=True) - - def test_full(self): - helper_test_op([], lambda: torch.full((45,65), 4, dtype=torch.int32), lambda: Tensor.full((45,65), 4), forward_only=True) - - def test_negative_dims(self): - creation_methods: List[Callable[..., Tensor]] = [ - Tensor.empty, - Tensor.rand, - Tensor.zeros, - Tensor.ones, - Tensor.randn, - Tensor.randint, - Tensor.normal, - Tensor.uniform, - Tensor.scaled_uniform, - Tensor.glorot_uniform - ] - - for method in creation_methods: - with self.assertRaises(ValueError): method(-3, 2) - with self.assertRaises(ValueError): method((2, -3)) - with self.assertRaises(ValueError): method((2, -3, 0)) - - def test_negative_dims_full(self): - with self.assertRaises(ValueError): Tensor.full((-3,), 2) - with self.assertRaises(ValueError): Tensor.full((2, -3), 4) - with self.assertRaises(ValueError): Tensor.full((2, -3, 0), 4) - - def test_negative_dims_eye(self): - with self.assertRaises(ValueError): Tensor.eye(-3, 3) - with self.assertRaises(ValueError): Tensor.eye(3, -3) - with self.assertRaises(ValueError): Tensor.eye(-3, -3) - - def test_negative_dims_kaiming(self): - creation_methods = [Tensor.kaiming_uniform, Tensor.kaiming_normal] - for method in creation_methods: - with self.assertRaises(ValueError): method(-3, 3) - with self.assertRaises(ValueError): method((-3, 3), 3) - with self.assertRaises(ValueError): method((-3, -3), 3) - - def test_zeros(self): - helper_test_op([], lambda: torch.zeros(45,65), lambda: Tensor.zeros(45,65), forward_only=True) - helper_test_op([], lambda: torch.zeros([45,65]), lambda: Tensor.zeros([45,65]), forward_only=True) - helper_test_op([], lambda: torch.zeros([]), lambda: Tensor.zeros([]), forward_only=True) - - def test_zeros_like(self): - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) - helper_test_op([], lambda: torch.zeros_like(b), lambda: Tensor.zeros_like(a), forward_only=True) - - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) - helper_test_op([], lambda: torch.zeros_like(b), lambda: Tensor.zeros_like(a), forward_only=True) - - def test_empty_0(self): - helper_test_op([], lambda: torch.empty(45,65)*0/0, lambda: Tensor.empty(45,65)*0/0, forward_only=True) - - def test_ones(self): - helper_test_op([], lambda: torch.ones(45,65), lambda: Tensor.ones(45,65), forward_only=True) - helper_test_op([], lambda: torch.ones([45,65]), lambda: Tensor.ones([45,65]), forward_only=True) - helper_test_op([], lambda: torch.ones([]), lambda: Tensor.ones([]), forward_only=True) - - def test_ones_like(self): - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) - helper_test_op([], lambda: torch.ones_like(b), lambda: Tensor.ones_like(a), forward_only=True) - - a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) - b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) - helper_test_op([], lambda: torch.ones_like(b), lambda: Tensor.ones_like(a), forward_only=True) - - def test_eye(self): - helper_test_op([], lambda: torch.eye(10), lambda: Tensor.eye(10), forward_only=True) - helper_test_op([], lambda: torch.eye(3, 5), lambda: Tensor.eye(3, 5), forward_only=True) - helper_test_op([], lambda: torch.eye(5, 3), lambda: Tensor.eye(5, 3), forward_only=True) - helper_test_op([], lambda: torch.eye(1), lambda: Tensor.eye(1), forward_only=True) - helper_test_op([], lambda: torch.eye(0), lambda: Tensor.eye(0), forward_only=True) - - def test_split(self): - def tensor(s): return torch.arange(math.prod(s), dtype=torch.int32).reshape(s), Tensor.arange(math.prod(s)).reshape(s) - test_cases = [ - (tensor((10,)), 5, {}), - (tensor((10,)), [1,4,5], {}), - (tensor((10,)), 3, {}), - (tensor((3,4,)), 1, {}), - (tensor((3,4,)), 1, {'dim':1}), - (tensor((4,4,)), [2,2], {}), - (tensor((4,4,)), [2,2], {'dim':1}), - (tensor((10000,)), 2500, {}), - ] - - for (tor, ten), sizes, args in test_cases: - tor_splits, ten_splits = tor.split(sizes, **args), ten.split(sizes, **args) - assert len(tor_splits) == len(ten_splits) - for tor_chunk, ten_chunk in zip(tor_splits, ten_splits): - helper_test_op([], lambda: tor_chunk, lambda: ten_chunk, forward_only=True) - - def test_chunk(self): - tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(6, 1) - ten = Tensor.arange(13).repeat((8, 1)).chunk(6, 1) - assert len(tor) == len(ten) - for i in range(len(tor)): - helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) - - tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(6, 0) - ten = Tensor.arange(13).repeat((8, 1)).chunk(6, 0) - assert len(tor) == len(ten) - for i in range(len(tor)): - helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) - - tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(3, -1) - ten = Tensor.arange(13).repeat((8, 1)).chunk(3, -1) - assert len(tor) == len(ten) - for i in range(len(tor)): - helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) - - tor = torch.arange(13, dtype=torch.int32).repeat(8, 3, 3).chunk(3, -2) - ten = Tensor.arange(13).repeat((8, 3, 3)).chunk(3, -2) - assert len(tor) == len(ten) - for i in range(len(tor)): - helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) - - def test_unfold(self): - helper_test_op([(8,)], lambda x: x.unfold(0, 2, 1)) - helper_test_op([(8,)], lambda x: x.unfold(0, 2, 2)) - helper_test_op([(8,)], lambda x: x.unfold(0, 7, 3)) - helper_test_op([(3,3,3)], lambda x: x.unfold(2, 2, 8)) - helper_test_op([(3,3,3)], lambda x: x.unfold(1, 0, 8)) - helper_test_op([(3,3,3,3,3)], lambda x: x.unfold(-1, 2, 2)) - - self.helper_test_exception([(8,)], lambda x: x.unfold(0, 9, 3), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) - self.helper_test_exception([(8,)], lambda x: x.unfold(1, 8, 3), lambda x: x.unfold(1, 8, 3), expected=IndexError) - self.helper_test_exception([(8,)], lambda x: x.unfold(0, -1, 3), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) - self.helper_test_exception([(8,)], lambda x: x.unfold(0, 1, -1), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) - - def test_meshgrid(self): - x, xt = torch.tensor([0.,1.,2.], requires_grad=True), Tensor([0.,1.,2.], requires_grad=True) - y, yt = torch.tensor([3.,4.,5.,6.], requires_grad=True), Tensor([3.,4.,5.,6.], requires_grad=True) - z, zt = torch.tensor([7.,8.,9.], requires_grad=True), Tensor([7.,8.,9.], requires_grad=True) - for indexing in ("ij", "xy"): - tor = torch.meshgrid(x, indexing=indexing) - ten = xt.meshgrid(indexing=indexing) - self.assertEqual(len(tor), len(ten)) - for tor_i, ten_i in zip(tor, ten): - helper_test_op([], lambda: tor_i, lambda: ten_i) - tor = torch.meshgrid(x, y, indexing=indexing) - ten = xt.meshgrid(yt, indexing=indexing) - self.assertEqual(len(tor), len(ten)) - for tor_i, ten_i in zip(tor, ten): - helper_test_op([], lambda: tor_i, lambda: ten_i) - tor = torch.meshgrid(x, torch.tensor(10., requires_grad=True), y, z, indexing=indexing) - ten = xt.meshgrid(Tensor(10., requires_grad=True), yt, zt, indexing=indexing) - self.assertEqual(len(tor), len(ten)) - for tor_i, ten_i in zip(tor, ten): - helper_test_op([], lambda: tor_i, lambda: ten_i) - - self.helper_test_exception([], lambda: torch.meshgrid(x, indexing="bad"), lambda: xt.meshgrid(indexing="bad"), expected=RuntimeError) - - def test_arange(self): - helper_test_op([], lambda: torch.arange(10, dtype=torch.int32), lambda: Tensor.arange(10), forward_only=True) - helper_test_op([], lambda: torch.arange(36, dtype=torch.int32), lambda: Tensor.arange(36), forward_only=True) - helper_test_op([], lambda: torch.arange(5, 10, 3, dtype=torch.int32), lambda: Tensor.arange(5, 10, 3), forward_only=True) - helper_test_op([], lambda: torch.arange(10, 5, -3, dtype=torch.int32), lambda: Tensor.arange(10, 5, -3), forward_only=True) - helper_test_op([], lambda: torch.arange(11, 5, -3, dtype=torch.int32), lambda: Tensor.arange(11, 5, -3), forward_only=True) - helper_test_op([], lambda: torch.arange(1, 78, 2, dtype=torch.int32), lambda: Tensor.arange(1, 78, 2), forward_only=True) - helper_test_op([], lambda: torch.arange(5.5, 175.5, 2.5), lambda: Tensor.arange(5.5, 175.5, 2.5), forward_only=True) - helper_test_op([], lambda: torch.arange(-30.2, -0.3, 0.75), lambda: Tensor.arange(-30.2, -0.3, 0.75), forward_only=True) - helper_test_op([], lambda: torch.arange(-50.3, -380.2, -2.25), lambda: Tensor.arange(-50.3, -380.2, -2.25), forward_only=True) - - def test_arange_big(self): - helper_test_op([], lambda: torch.arange(256, dtype=torch.int32), lambda: Tensor.arange(256), forward_only=True) - - def test_arange_4096(self): - helper_test_op([], lambda: torch.arange(4096, dtype=torch.int32), lambda: Tensor.arange(4096), forward_only=True) - - def test_linspace(self): - helper_test_op([], lambda: torch.linspace(5, 10, 3), lambda: Tensor.linspace(5, 10, 3), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, 10, 1), lambda: Tensor.linspace(5, 10, 1), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, 10, 0), lambda: Tensor.linspace(5, 10, 0), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, 10, 30), lambda: Tensor.linspace(5, 10, 30), forward_only=True) - helper_test_op([], lambda: torch.linspace(-5.5, 5.5, 10), lambda: Tensor.linspace(-5.5, 5.5, 10), forward_only=True) - helper_test_op([], lambda: torch.linspace(5.5, -5.5, 10), lambda: Tensor.linspace(5.5, -5.5, 10), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, 10, 3, dtype=torch.int32), lambda: Tensor.linspace(5, 10, 3, dtype="int32"), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, 10, 20, dtype=torch.int32), lambda: Tensor.linspace(5, 10, 20, dtype="int32"), forward_only=True) - helper_test_op([], lambda: torch.linspace(5, -5, 20, dtype=torch.int32), lambda: Tensor.linspace(5, -5, 20, dtype="int32"), forward_only=True) - self.helper_test_exception([], lambda: torch.linspace(5, 10, 3, dtype=torch.bool), lambda: Tensor.linspace(5, 10, 3, dtype="bool"), - expected=(RuntimeError, ValueError)) - self.helper_test_exception([], lambda: torch.linspace(1, 2, -1), lambda: Tensor.linspace(1, 2, -1), expected=(RuntimeError, ValueError)) - - def test_sum_fake(self): - helper_test_op([(256, 1)], lambda x: x.sum(axis=1)) - - def test_sum_collapse(self): - helper_test_op([], lambda: torch.ones(256,256).sum(axis=1), lambda: Tensor.ones(256,256).sum(axis=1), forward_only=True) - - def test_sum_collapse_neg(self): - helper_test_op([], lambda: (-torch.ones(3,3)).sum(axis=1), lambda: (-Tensor.ones(3,3)).sum(axis=1), forward_only=True) - - def test_sum_pad_collapse(self): - helper_test_op([], lambda: torch.nn.functional.pad(torch.ones(256,256), pad=(0,64,0,0)).sum(axis=1), - lambda: Tensor.ones(256,256).pad(((0,0), (0,64))).sum(axis=1), forward_only=True) - - # this is more complex and won't fold for a while - def test_sum_cat_collapse(self): - helper_test_op([], lambda: torch.cat([torch.ones(256,256), torch.zeros(256,64)], dim=1).sum(axis=1), - lambda: Tensor.cat(Tensor.ones(256,256), Tensor.zeros(256,64), dim=1).sum(axis=1), forward_only=True) - - def test_max_dont_collapse(self): - helper_test_op([], lambda: torch.ones(256,256).max(1)[0], lambda: Tensor.ones(256,256).max(1), forward_only=True) - - def test_where(self): - helper_test_op( - [(100,)], - lambda x: torch.where(x > 0.5, 4, 2).type(torch.int32), - lambda x: (x > 0.5).where(4, 2), forward_only=True) - - for shps in [[(8,),(1,),(1,)], [(10,10),(10,),(10,)], [(100,)]*3, [(10,10)]*3]: - helper_test_op( - shps, - lambda x, a, b: torch.where(x > 0.5, a, b), - lambda x, a, b: (x > 0.5).where(a, b), forward_only=True) - - def test_where_permute(self): - helper_test_op( - [(5, 5)], - lambda x: torch.where(x > 0.5, 4, 2).type(torch.int32).permute((1, 0)), - lambda x: (x > 0.5).where(4, 2).permute((1, 0)), forward_only=True) - - def _test_cmp(self, fxn, reverse=True): - # test different dtypes - helper_test_op(None, fxn, fxn, forward_only=True, vals=[[0.,1,2], [2.,1,0]]) - helper_test_op(None, fxn, fxn, forward_only=True, vals=[[0,1,2], [2,1,0]]) - helper_test_op(None, fxn, fxn, forward_only=True, vals=[[True, True, False], [False,True,False]]) - # test broadcasting - for shps in [[(3, 4, 5), (3, 4, 5)], [(3, 4, 5), (5,)], [(5,), (3, 4, 5)]]: - helper_test_op(shps, fxn, fxn, forward_only=True) - # test cmp with const - helper_test_op(None, lambda x,y: fxn(x,2), lambda x,y: fxn(x,2), forward_only=True, vals=[[0.,1,2], [2.,1,0]]) - if reverse: helper_test_op(None, lambda x,y: fxn(2,y), lambda x,y: fxn(2,y), forward_only=True, vals=[[0.,1,2], [2.,1,0]]) - # test special floats # TODO: fix nan - specials = [0.0, 1.0, -1.0, math.inf, -math.inf]#, math.nan] - for s0 in specials: - for s1 in specials: - helper_test_op(None, fxn, fxn, forward_only=True, vals=[[s0], [s1]]) - - def test_cmp_eq(self): self._test_cmp(lambda x,y: x==y, reverse=False) - def test_cmp_gt(self): self._test_cmp(lambda x,y: x>y) - def test_cmp_ge(self): self._test_cmp(lambda x,y: x>=y) - def test_cmp_lt(self): self._test_cmp(lambda x,y: x 0).where(1//t, t).numpy(), [-1, 0, 1, 0]) - - def test_scalar_div(self): - helper_test_op([(45,65)], lambda x: x/255) - helper_test_op([(45,65)], lambda x: x/1) - helper_test_op([(45,65)], lambda x: 1/x) - helper_test_op([(45,65)], lambda x: x/2) - helper_test_op([(45,65)], lambda x: 2/x) - helper_test_op([()], lambda x: x/2) - helper_test_op([()], lambda x: 2/x) - - def test_mod(self): - a = [-4, 7, 5, 4, -7, 8, -9] - b = [2, -3, 8, -2, 3, 5, -5] - for float_a in [True, False]: - for float_b in [True, False]: - va = [float(ai) for ai in a] if float_a else a - vb = [float(bi) for bi in b] if float_b else b - helper_test_op(None, lambda x,y: x%y, Tensor.mod, forward_only=True, vals=[va, vb]) - helper_test_op(None, lambda x,y: x%y, forward_only=True, vals=[va, vb]) - helper_test_op(None, lambda x: x%2, forward_only=True, vals=[va]) - helper_test_op(None, lambda x: x%3, forward_only=True, vals=[va]) - helper_test_op(None, lambda x: x%3.5, forward_only=True, vals=[va]) - helper_test_op(None, lambda x: 100%x, forward_only=True, vals=[va]) - helper_test_op(None, lambda x: 100.5%x, forward_only=True, vals=[va]) - - def test_mul_naninf(self): - helper_test_op([(45,65)], lambda x: x*math.inf) - helper_test_op([(45,65)], lambda x: x*-math.inf) - helper_test_op([(45,65)], lambda x: x*math.nan) - def test_div_naninf(self): - helper_test_op([(45,65)], lambda x: x/math.inf) - helper_test_op([(45,65)], lambda x: x/-math.inf) - helper_test_op([(45,65)], lambda x: x/math.nan) - helper_test_op([(45,65)], lambda x: math.inf/x) - helper_test_op([(45,65)], lambda x: (-math.inf)/x) - helper_test_op([(45,65)], lambda x: math.nan/x) - - def test_pow_full(self): - helper_test_op([(45,65), (45,65)], lambda x,y: x**y) - helper_test_op([(45,65), (45,65)], lambda x,y: x.pow(y)) - - def test_pow(self): - helper_test_op([(45,65)], lambda x: x**0) - helper_test_op([(45,65)], lambda x: x**1) - helper_test_op([(45,65)], lambda x: x**2) - helper_test_op([(45,65)], lambda x: x**3) - helper_test_op([(45,65)], lambda x: x**-2) - helper_test_op([()], lambda x: x**2) - helper_test_op([()], lambda x: x**-2) - # Regression tests for https://github.com/tinygrad/tinygrad/issues/1151 - helper_test_op([(45,65)], lambda x: x**3, low=-30, high=-27) - helper_test_op([()], lambda x: x**3, low=-30, high=-27) - # Regression tests for https://github.com/tinygrad/tinygrad/issues/1251 - helper_test_op([(45,65)], lambda x: x**0.2, low=-30, high=-27) - helper_test_op([(45,65)], lambda x: x**1.2, low=-30, high=-27) - helper_test_op([()], lambda x: x**0.2, low=-30, high=-27) - helper_test_op([()], lambda x: x**1.2, low=-30, high=-27) - a, b = Tensor([0.0], requires_grad=True), torch.tensor([0.0], requires_grad=True) - helper_test_op([], lambda: b**1.1, lambda: a**1.1) - - def test_pow_const(self): - helper_test_op([(45,65)], lambda x: x**0.0) - helper_test_op([(45,65)], lambda x: x**1.0) - helper_test_op([(45,65)], lambda x: x**-1.0) - helper_test_op([(45,65)], lambda x: x**8.0) - helper_test_op([(45,65)], lambda x: x**5.5) - helper_test_op([(45,65)], lambda x: x**-5.5) - # helper_test_op([(45,65)], lambda x: x**-8.0) # TODO: fix this - helper_test_op([(45,65)], lambda x: 1.0**x) - helper_test_op([(45,65)], lambda x: 5.5**x) - helper_test_op([(45,65)], lambda x: (-5.5)**x) - helper_test_op([(45,65)], lambda x: 8.0**x) - helper_test_op([(45,65)], lambda x: x**2.0) - helper_test_op([(45,65)], lambda x: 2.0**x) - helper_test_op([()], lambda x: x**2.0) - helper_test_op([()], lambda x: 2.0**x) - helper_test_op(None, lambda x: 0**x, vals=[[-2.,-1,0,1,2,3]]) - helper_test_op(None, lambda x: 0.7**x, vals=[[-2.,-1,0,1,2,3]]) - helper_test_op(None, lambda x: (-2)**x, vals=[[-2.,-1,0,1,2,3]]) - # float to power of int - helper_test_op(None, lambda x: 0.7**x, vals=[[-2,-1,0,1,2,3]], forward_only=True) - - def test_pow_const_direct(self): - # x ** c - def get_tiny_gradient(x, c): - t = Tensor([x], dtype=dtypes.float) - return (t ** c)[0].gradient(t)[0].item() - def get_torch_gradient(x, c): - t = torch.tensor([x], dtype=torch.float, requires_grad=True) - return torch.autograd.grad(t ** c, t)[0].item() - for x in [-math.inf, 0, 1, math.inf]: - for c in [-1, 0, 0.3, 1, 2]: - tiny_out = get_tiny_gradient(x, c) - torch_out = get_torch_gradient(x, c) - if math.isnan(tiny_out): - assert math.isnan(torch_out) - else: - self.assertAlmostEqual(tiny_out, torch_out, msg=f"{x}, {c}") - - def test_pow_zero_tensor(self): - helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.0]]) - # TODO: fix WEBGPU - if Device.DEFAULT != "WEBGPU": - helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.3]]) - helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [-0.3]]) - def test_pow_zero_const(self): - helper_test_op(None, lambda x: x**0.3, vals=[[0.0]]) - helper_test_op(None, lambda x: x**0.0, vals=[[0.0]]) - helper_test_op(None, lambda x: x**-0.3, vals=[[0.0]]) - helper_test_op(None, lambda x: x**-1.0, vals=[[-1.0, 0.0, 1.0]]) - - @unittest.skip("not supported") - def test_pow_int(self): - def _test(base, exponent): helper_test_op(None, lambda x,y: x**y, vals=[base, exponent], forward_only=True) - - for base in ([1, 2, 3], [-1, -2, -3]): - for exponent in ([2, 3, 4], [-2, -3, -4]): - _test(base, exponent) - # NOTE: torch 0 ** -1 is 0 - _test([0, 0, 0], [0, 1, 2]) - - np.testing.assert_equal((Tensor(11) ** Tensor(7)).item(), 11 ** 7) - np.testing.assert_equal((Tensor([11]) ** Tensor(7)).item(), 11 ** 7) - # TODO: fix non-precise int pow - with self.assertRaises(AssertionError): np.testing.assert_equal((Tensor(11) ** Tensor([7])).item(), 11 ** 7) - with self.assertRaises(AssertionError): np.testing.assert_equal((Tensor([11]) ** Tensor([7])).item(), 11 ** 7) - - # pow to a const int - helper_test_op([], lambda: torch.tensor([2], dtype=torch.int) ** torch.tensor(-2, dtype=torch.int), - lambda: Tensor([2]) ** Tensor(-2), forward_only=True) - - def test_sqrt(self): - helper_test_op([(45,65)], lambda x: x.sqrt()) - helper_test_op(None, lambda x: x.sqrt(), vals=[[0.0]]) - helper_test_op([()], lambda x: x.sqrt()) - def test_rsqrt(self): - helper_test_op([(45,65)], lambda x: x.rsqrt()) - helper_test_op(None, lambda x: x.rsqrt(), vals=[[0.0]]) - helper_test_op([()], lambda x: x.rsqrt()) - - def test_xor(self): - data = [[1,-8,1],[32,1,6]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.int32) - helper_test_op([], lambda: tor^tor, lambda: ten^ten, forward_only=True) - helper_test_op([], lambda: tor^0x1337, lambda: ten^0x1337, forward_only=True) - helper_test_op([], lambda: 0x1337^tor, lambda: 0x1337^ten, forward_only=True) - - self.helper_test_exception([(4), (4)], torch.bitwise_xor, Tensor.bitwise_xor, expected=RuntimeError) - - def test_and(self): - data = [[1,-8,1],[32,1,6]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.int32) - helper_test_op([], lambda: tor&tor, lambda: ten&ten, forward_only=True) - helper_test_op([], lambda: tor&0x1337, lambda: ten&0x1337, forward_only=True) - helper_test_op([], lambda: 0x1337&tor, lambda: 0x1337&ten, forward_only=True) - - data = [[True, True, False, False], [True, False, True, False]] - tor0, tor1 = torch.tensor(data[0], dtype=torch.bool), torch.tensor(data[1], dtype=torch.bool) - ten0, ten1 = Tensor(data[0], dtype=dtypes.bool), Tensor(data[1], dtype=dtypes.bool) - helper_test_op([], lambda: tor0&tor1, lambda: ten0&ten1, forward_only=True) - - helper_test_op(None, lambda x: (1 < x) & (x < 2), forward_only=True, vals=[[1.2, 1.2, 1.2, 3.2]]) - - self.helper_test_exception([(4), (4)], torch.bitwise_and, Tensor.bitwise_and, expected=RuntimeError) - - def test_or(self): - data = [[1,-8,1],[32,1,6]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.int32) - helper_test_op([], lambda: tor|tor, lambda: ten|ten, forward_only=True) - helper_test_op([], lambda: tor|0x1337, lambda: ten|0x1337, forward_only=True) - helper_test_op([], lambda: 0x1337|tor, lambda: 0x1337|ten, forward_only=True) - - data = [[True, True, False, False], [True, False, True, False]] - tor0, tor1 = torch.tensor(data[0], dtype=torch.bool), torch.tensor(data[1], dtype=torch.bool) - ten0, ten1 = Tensor(data[0], dtype=dtypes.bool), Tensor(data[1], dtype=dtypes.bool) - helper_test_op([], lambda: tor0|tor1, lambda: ten0|ten1, forward_only=True) - - self.helper_test_exception([(4), (4)], torch.bitwise_or, Tensor.bitwise_or, expected=RuntimeError) - - def test_bitwise_not(self): - data = [[1,-8,1],[32,1,6]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.int32) - helper_test_op([], lambda: tor.bitwise_not(), lambda: ten.bitwise_not(), forward_only=True) - helper_test_op([], lambda: ~tor, lambda: ~ten, forward_only=True) - - data = [[True, False]] - tor = torch.tensor(data, dtype=torch.bool) - ten = Tensor(data, dtype=dtypes.bool) - helper_test_op([], lambda: tor.bitwise_not(), lambda: ten.bitwise_not(), forward_only=True) - helper_test_op([], lambda: ~tor, lambda: ~ten, forward_only=True) - - self.helper_test_exception([(4)], torch.bitwise_not, Tensor.bitwise_not, expected=RuntimeError) - - def test_lshift(self): - data = [[0,1,2],[1<<8,1<<16,1<<31-1]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.uint32) - # cast to int32 because torch does not support uint32 - helper_test_op([], lambda: tor << 0, lambda: (ten << 0).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor << 2, lambda: (ten << 2).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor << 31, lambda: (ten << 31).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor.__lshift__(2), lambda: ten.__lshift__(2).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor.bitwise_left_shift(2), lambda: ten.lshift(2).cast(dtypes.int32), forward_only=True) - - def test_rshift(self): - data = [[0,1,2],[1<<8,1<<16,1<<31-1]] - tor = torch.tensor(data, dtype=torch.int) - ten = Tensor(data, dtype=dtypes.uint32) - # cast to int32 because torch does not support uint32 - helper_test_op([], lambda: tor >> 0, lambda: (ten >> 0).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor >> 2, lambda: (ten >> 2).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor >> 31, lambda: (ten >> 31).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor.__rshift__(2), lambda: ten.__rshift__(2).cast(dtypes.int32), forward_only=True) - helper_test_op([], lambda: tor.bitwise_right_shift(2), lambda: ten.rshift(2).cast(dtypes.int32), forward_only=True) - - def test_idiv_shift_rewrite_negative(self): - a = Tensor(-5).idiv(2).item() - b = Tensor(-5).contiguous().idiv(2).item() - self.assertEqual(a, b) - self.assertEqual(Tensor(-1).contiguous().idiv(4).item(), 0) # NOTE this is trunc-div behaviour - - def test_sin(self): - helper_test_op([(45,65)], lambda x: x.sin()) - helper_test_op([()], lambda x: x.sin()) - # works on real CUDA but not CI - if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): - helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) - helper_test_op(None, lambda x: x.sin(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], - atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) - def test_cos(self): - helper_test_op([(45,65)], lambda x: x.cos()) - helper_test_op([()], lambda x: x.cos()) - if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): - helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) - helper_test_op(None, lambda x: x.cos(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], - atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) - def test_tan(self): - # NOTE: backward has much higher diff with input close to pi/2 and -pi/2 - helper_test_op([(45,65)], lambda x: x.tan(), low=-1.5, high=1.5) - helper_test_op([(45,65)], lambda x: x.tan(), low=-5, high=5) - helper_test_op([()], lambda x: x.tan()) - if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): - helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) - helper_test_op(None, lambda x: x.cos(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], - atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) - - def test_asin(self): - helper_test_op([(45,65)], lambda x: x.asin(), low=-1, high=1) - helper_test_op([(45,65)], lambda x: x.asin(), low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.asin(), low=300, high=303) - def test_acos(self): - # high grad atol - helper_test_op([(45,65)], lambda x: x.acos(), low=-1, high=1) - helper_test_op([(45,65)], lambda x: x.acos(), low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.acos(), low=300, high=303) - def test_atan(self): - helper_test_op([(45,65)], lambda x: x.atan()) - helper_test_op([(45,65)], lambda x: x.atan(), low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.atan(), low=300, high=303) - - def test_relu(self): - helper_test_op([(64,64)], lambda x: x.relu()) - helper_test_op([()], lambda x: x.relu()) - def test_relu_exact(self): - helper_test_op(None, lambda x: x.relu(), vals=[[-1.,0,1]]) - def test_relu_maximum_exact(self): - helper_test_op(None, lambda x: torch.maximum(x, torch.zeros_like(x, requires_grad=False)), lambda x: Tensor.maximum(x, 0), vals=[[-1.,0,1]]) - def test_leaky_relu(self): - helper_test_op([(45,65)], lambda x: torch.nn.functional.leaky_relu(x,0.01), Tensor.leaky_relu) - helper_test_op([()], lambda x: torch.nn.functional.leaky_relu(x,0.01), Tensor.leaky_relu) - def test_celu(self): - for val in range(1, 5): - helper_test_op([(45,65)], lambda x: torch.nn.functional.celu(x,val), lambda x: x.celu(val)) - helper_test_op([()], lambda x: torch.nn.functional.celu(x,val), lambda x: x.celu(val)) - def test_selu(self): - helper_test_op([(45,65)], torch.nn.functional.selu, Tensor.selu) - helper_test_op([()], torch.nn.functional.selu, Tensor.selu) - def test_silu(self): - helper_test_op([(45,65)], torch.nn.functional.silu, Tensor.silu) - helper_test_op([()], torch.nn.functional.silu, Tensor.silu) - def test_swish(self): - helper_test_op([(45,65)], torch.nn.functional.silu, Tensor.swish) - helper_test_op([()], torch.nn.functional.silu, Tensor.swish) - - def test_abs(self): - helper_test_op([(45,65)], torch.abs, Tensor.abs) - helper_test_op([()], torch.abs, Tensor.abs) - def test_abs_exact(self): - helper_test_op(None, torch.abs, Tensor.abs, vals=[[-1.,0,1]]) - - @unittest.skipIf(TRANSCENDENTAL and Device.DEFAULT=="AMD", "TODO: remu crashes") - def test_log(self): - helper_test_op([(45,65)], torch.log, Tensor.log) - helper_test_op(None, torch.log, Tensor.log, vals=[[math.inf, -math.inf, math.nan]]) - helper_test_op([()], torch.log, Tensor.log) - def test_log2(self): - helper_test_op([(45,65)], torch.log2, Tensor.log2) - helper_test_op(None, torch.log2, Tensor.log2, vals=[[math.inf, -math.inf, math.nan]]) - helper_test_op([()], torch.log2, Tensor.log2) - - @unittest.skipIf(TRANSCENDENTAL and Device.DEFAULT=="AMD", "TODO: remu crashes") - def test_exp(self): - helper_test_op([(45,65)], torch.exp, Tensor.exp) - helper_test_op(None, torch.exp, Tensor.exp, vals=[[math.inf, -math.inf, math.nan]]) - helper_test_op([()], torch.exp, Tensor.exp) - def test_exp2(self): - helper_test_op([(45,65)], torch.exp2, Tensor.exp2) - helper_test_op(None, torch.exp2, Tensor.exp2, vals=[[math.inf, -math.inf, math.nan]]) - helper_test_op([()], torch.exp2, Tensor.exp2) - - def test_sign(self): - helper_test_op([(45,65)], torch.sign, Tensor.sign) - helper_test_op([()], torch.sign, Tensor.sign) - def test_sign_exact(self): - helper_test_op(None, torch.sign, Tensor.sign, vals=[[-1.,0,1]]) - - def test_copysign(self): - helper_test_op([(45,65), (45,65)], torch.copysign, Tensor.copysign) - helper_test_op([(45,65), (45,1)], torch.copysign, Tensor.copysign) - helper_test_op([(45,1), (1,65)], torch.copysign, Tensor.copysign) - helper_test_op([(), ()], torch.copysign, Tensor.copysign) - def test_copysign_exact(self): - for i in [-1.,0.,1.]: - for j in [-1., 0., 1.]: - helper_test_op(None, torch.copysign, Tensor.copysign, vals=[[i], [j]]) - - def test_softsign(self): - helper_test_op([(45,65)], torch.nn.functional.softsign, Tensor.softsign) - helper_test_op([()], torch.nn.functional.softsign, Tensor.softsign) - def test_softsign_exact(self): - helper_test_op(None, torch.nn.functional.softsign, Tensor.softsign, vals=[[-1.,0,1]]) - - def test_sigmoid(self): - helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid) - helper_test_op([()], torch.sigmoid, Tensor.sigmoid) - def test_sigmoid_extreme(self): - helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=300, high=400) - helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=-400, high=-300) - x = Tensor([300.0]) - self.assertAlmostEqual(x.sigmoid()[0].gradient(x)[0].item(), 0.0) - x = Tensor([-300.0]) - self.assertAlmostEqual(x.sigmoid()[0].gradient(x)[0].item(), 0.0) - def test_sigmoid_alt_extreme(self): - def sigmoid(x:Tensor): return x.exp() / (1 + x.exp()) - x = Tensor([300.0]) - self.assertAlmostEqual(sigmoid(x)[0].gradient(x)[0].item(), 0.0) - x = Tensor([-300.0]) - self.assertAlmostEqual(sigmoid(x)[0].gradient(x)[0].item(), 0.0) - def test_hardsigmoid(self): - helper_test_op([(45,65)], torch.nn.functional.hardsigmoid, Tensor.hardsigmoid) - helper_test_op([()], torch.nn.functional.hardsigmoid, Tensor.hardsigmoid) - def test_hardsigmoid_extreme(self): - helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=300, high=400) - helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=-400, high=-300) - def test_softplus(self): - helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6) - helper_test_op([(45,65)], lambda t: torch.nn.functional.softplus(t, beta=3), lambda t: Tensor.softplus(t, beta=3), grad_atol=1e-6) - helper_test_op([(45,65)], lambda t: torch.nn.functional.softplus(t, beta=1/3), lambda t: Tensor.softplus(t, beta=1/3), grad_atol=1e-6) - # # TODO: support threshold and enable this - # helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6, low=300, high=400) - helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6, low=-400, high=-300) - helper_test_op([()], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6) - - def test_erf(self): - helper_test_op([(45,65)], torch.erf, Tensor.erf) - helper_test_op([(45,65)], torch.erf, Tensor.erf, low=300, high=400) - helper_test_op([(45,65)], torch.erf, Tensor.erf, low=-400, high=-300) - helper_test_op([()], torch.erf, Tensor.erf) - - def test_gelu(self): - helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu) - def test_gelu_extreme(self): - helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu, low=300, high=400) - helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu, low=-400, high=-300) - def test_quick_gelu(self): - helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu) - helper_test_op([()], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu) - def test_quick_gelu_extreme(self): - helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu, low=300, high=400) - helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu, low=-400, high=-300) - - def test_elu(self): - helper_test_op([(45,65)], torch.nn.functional.elu, Tensor.elu) - helper_test_op([(45,65)], lambda x: torch.nn.functional.elu(x, alpha=0.1), lambda x: Tensor.elu(x, alpha=0.1)) - helper_test_op([()], torch.nn.functional.elu, Tensor.elu) - def test_relu6(self): - helper_test_op([(45,65)], torch.nn.functional.relu6, Tensor.relu6) - helper_test_op([()], torch.nn.functional.relu6, Tensor.relu6) - def test_hardswish(self): - helper_test_op([(45,65)], torch.nn.functional.hardswish, Tensor.hardswish, grad_atol=1e-6) - helper_test_op([()], torch.nn.functional.hardswish, Tensor.hardswish, grad_atol=1e-6) - def test_mish(self): - helper_test_op([(45,65)], torch.nn.functional.mish, Tensor.mish) - helper_test_op([()], torch.nn.functional.mish, Tensor.mish) - - def test_small_cumsum(self): - helper_test_op([(10)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - def test_simple_cumsum(self): - helper_test_op([(512)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - helper_test_op([(1022)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - def test_cumsum(self): - helper_test_op([()], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - self.helper_test_exception([()], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1), expected=IndexError) - helper_test_op([(20,)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - self.helper_test_exception([(20,)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1), expected=IndexError) - self.helper_test_exception([(20,)], lambda x: torch.cumsum(x, dim=-2), lambda x: Tensor.cumsum(x, axis=-2), expected=IndexError) - helper_test_op([(20,30)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - helper_test_op([(20,30)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1)) - helper_test_op([(20,30,40)], lambda x: torch.cumsum(x, dim=2), lambda x: Tensor.cumsum(x, axis=2)) - helper_test_op([(20,30,40)], lambda x: torch.cumsum(x, dim=-1), lambda x: Tensor.cumsum(x, axis=-1)) - def test_cumsum_zero_axis(self): - helper_test_op([(2,0,4)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1)) - helper_test_op([(0,3)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) - helper_test_op([(2,3,0)], lambda x: torch.cumsum(x, dim=2), lambda x: Tensor.cumsum(x, axis=2)) - - def test_small_cumprod(self): - helper_test_op([(10)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - def test_simple_cumprod(self): - helper_test_op([(512)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - helper_test_op([(1022)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - def test_cumprod(self): - helper_test_op([()],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - self.helper_test_exception([()],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1),expected=IndexError) - helper_test_op([(20,)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - self.helper_test_exception([(20,)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1),expected=IndexError) - self.helper_test_exception([(20,)],lambda x: torch.cumprod(x, dim=-2),lambda x: Tensor.cumprod(x, axis=-2),expected=IndexError) - helper_test_op([(20, 30)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - helper_test_op([(20, 30)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1)) - helper_test_op([(20, 30, 40)],lambda x: torch.cumprod(x, dim=2),lambda x: Tensor.cumprod(x, axis=2)) - helper_test_op([(20, 30, 40)],lambda x: torch.cumprod(x, dim=-1),lambda x: Tensor.cumprod(x, axis=-1)) - def test_cumprod_zero_axis(self): - helper_test_op([(2, 0, 4)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1)) - helper_test_op([(0, 3)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) - helper_test_op([(2, 3, 0)],lambda x: torch.cumprod(x, dim=2),lambda x: Tensor.cumprod(x, axis=2)) - - def test_small_cummax(self): - helper_test_op([(10)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - def test_simple_cummax(self): - helper_test_op([(512)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - helper_test_op([(1022)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - def test_cummax(self): - helper_test_op([()], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - # TODO: torch allows this? - # self.helper_test_exception([()], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1), expected=IndexError) - helper_test_op([(20,)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - self.helper_test_exception([(20,)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1), expected=IndexError) - self.helper_test_exception([(20,)], lambda x: torch.cummax(x, dim=-2).values, lambda x: Tensor.cummax(x, axis=-2), expected=IndexError) - helper_test_op([(20,30)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - helper_test_op([(20,30)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1)) - helper_test_op([(20,30,40)], lambda x: torch.cummax(x, dim=2).values, lambda x: Tensor.cummax(x, axis=2)) - helper_test_op([(20,30,40)], lambda x: torch.cummax(x, dim=-1).values, lambda x: Tensor.cummax(x, axis=-1)) - def test_cummax_zero_axis(self): - helper_test_op([(2,0,4)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1)) - helper_test_op([(0,3)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) - helper_test_op([(2,3,0)], lambda x: torch.cummax(x, dim=2).values, lambda x: Tensor.cummax(x, axis=2)) - - def test_argmax(self): - # check if it returns the first index for multiple occurences - helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[2, 2]]) - helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[1, 2, 2]]) - np.testing.assert_equal(Tensor([2,2]).argmax().numpy(), 0) - np.testing.assert_equal(Tensor([1,2,2]).argmax().numpy(), 1) - helper_test_op([(10,20)], lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmax(0, False).type(torch.int32), lambda x: x.argmax(0, False), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmax(1, False).type(torch.int32), lambda x: x.argmax(1, False), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmax(1, True).type(torch.int32), lambda x: x.argmax(1, True), forward_only=True) - # regression test for bitwise_not then argmax - helper_test_op(None, lambda x: (~x).argmax().type(torch.int32), lambda x: (~x).argmax(), forward_only=True, vals=[[2, 2]]) - - helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[0, -2**31]]) - helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[-2**31, 0]]) - # NOTE: torch does not support this on bool - helper_test_op(None, lambda x: x.type(torch.int32).argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[False, True]]) - helper_test_op(None, lambda x: x.type(torch.int32).argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[True, False]]) - - def test_argmin(self): - # check if it returns the first index for multiple occurences - helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[2, 2]]) - helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[3, 2, 2]]) - np.testing.assert_equal(Tensor([2,2]).argmin().numpy(), 0) - np.testing.assert_equal(Tensor([3,2,2]).argmin().numpy(), 1) - helper_test_op([(10,20)], lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmin(0, False).type(torch.int32), lambda x: x.argmin(0, False), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmin(1, False).type(torch.int32), lambda x: x.argmin(1, False), forward_only=True) - helper_test_op([(10,20)], lambda x: x.argmin(1, True).type(torch.int32), lambda x: x.argmin(1, True), forward_only=True) - - helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[0, -2**31]]) - helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[-2**31, 0]]) - # NOTE: torch does not support this on bool - helper_test_op(None, lambda x: x.type(torch.int32).argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[False, True]]) - helper_test_op(None, lambda x: x.type(torch.int32).argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[True, False]]) - - def test_sort(self): - for dim in [-1, 0, 1]: - for descending in [True, False]: - helper_test_op([(8,45,6)], lambda x: x.sort(dim, descending).values, lambda x: x.sort(dim, descending)[0], forward_only=True) - helper_test_op([(8,45,6)], lambda x: x.sort(dim, descending).indices.type(torch.int32), lambda x: x.sort(dim, descending)[1], - forward_only=True) - # repeated values - helper_test_op(None, lambda x: x.sort(stable=True).values, lambda x: x.sort()[0], forward_only=True, vals=[[0, 1] * 9]) - helper_test_op(None, lambda x: x.sort(stable=True).indices.type(torch.int32), lambda x: x.sort()[1], forward_only=True, vals=[[0, 1] * 9]) - helper_test_op(None, lambda x: x.sort(stable=True, descending=True).values, - lambda x: x.sort(descending=True)[0], forward_only=True, vals=[[0, 1] * 9]) - helper_test_op(None, lambda x: x.sort(stable=True, descending=True).indices.type(torch.int32), - lambda x: x.sort(descending=True)[1], forward_only=True, vals=[[0, 1] * 9]) - - def test_topk(self): - helper_test_op([(10)], lambda x: x.topk(3).values, lambda x: x.topk(3)[0], forward_only=True) - helper_test_op([(10)], lambda x: x.topk(3).indices.type(torch.int32), lambda x: x.topk(3)[1], forward_only=True) - for dim in [0, 1, -1]: - for largest in [True, False]: - for sorted_ in [True]: # TODO support False - helper_test_op([(10,12,6)], - lambda x: x.topk(5, dim, largest, sorted_).values, - lambda x: x.topk(5, dim, largest, sorted_)[0], forward_only=True) - helper_test_op([(10,12,6)], - lambda x: x.topk(5, dim, largest, sorted_).indices.type(torch.int32), - lambda x: x.topk(5, dim, largest, sorted_)[1], forward_only=True) - # repeated values - value, indices = Tensor([1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0]).topk(3) - np.testing.assert_equal(value.numpy(), [1, 1, 1]) - np.testing.assert_equal(indices.numpy(), [0, 1, 3]) - value, indices = Tensor([1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0]).topk(3, largest=False) - np.testing.assert_equal(value.numpy(), [0, 0, 0]) - np.testing.assert_equal(indices.numpy(), [2, 4, 6]) - self.helper_test_exception([(4)], lambda x: x.topk(5), lambda x: x.topk(5), expected=(RuntimeError, ValueError)) - - def test_einsum(self): - # matrix transpose - helper_test_op([(150,150)], lambda a: torch.einsum('ij->ji', a), lambda a: Tensor.einsum('ij->ji', a)) - helper_test_op([(150,150)], lambda a: torch.einsum('ij -> ji', a), lambda a: Tensor.einsum('ij -> ji', a)) - helper_test_op([(150,150)], lambda a: torch.einsum('ji', a), lambda a: Tensor.einsum('ji', a)) - helper_test_op([(20,30,40)], lambda a: torch.einsum('jki', a), lambda a: Tensor.einsum('jki', a)) - helper_test_op([(20,30,40)], lambda a: torch.einsum('dog', a), lambda a: Tensor.einsum('dog', a)) - # no -> and empty rhs - helper_test_op([(20,30),(30,40)], lambda a, b: torch.einsum('ij,jk', a, b), lambda a, b: Tensor.einsum('ij,jk', a, b)) - # sum all elements - helper_test_op([(20,30,40)], lambda a: torch.einsum('ijk->', a), lambda a: Tensor.einsum('ijk->', a)) - # column sum - helper_test_op([(50,50)], lambda a: torch.einsum('ij->j', a), lambda a: Tensor.einsum('ij->j', a)) - # row sum - helper_test_op([(15,15)], lambda a: torch.einsum('ij->i', a), lambda a: Tensor.einsum('ij->i', a)) - # matrix-vector multiplication - helper_test_op([(15,20), (20,)], lambda a,b: torch.einsum('ik,k->i', a,b), lambda a,b: Tensor.einsum('ik,k->i', a, b)) - # matrix-matrix multiplication - helper_test_op([(15,20), (20,30)], lambda a,b: torch.einsum('ik,kj->ij', a,b), lambda a,b: Tensor.einsum('ik,kj->ij', a, b)) - # matrix-matrix multiplication, different letter order - helper_test_op([(15,20), (20,30)], lambda a,b: torch.einsum('jk,ki->ji', a,b), lambda a,b: Tensor.einsum('jk,ki->ji', a, b)) - # dot product - helper_test_op([(30),(30)], lambda a,b: torch.einsum('i,i->i', [a,b]), lambda a,b: Tensor.einsum('i,i->i', [a,b])) - # hadamard product - helper_test_op([(30,40),(30,40)], lambda a,b: torch.einsum('ij,ij->ij', a,b), lambda a,b: Tensor.einsum('ij,ij->ij', a,b)) - # outer product - helper_test_op([(15,), (15,)], lambda a,b: torch.einsum('i,j->ij', a,b), lambda a,b: Tensor.einsum('i,j->ij',a,b)) - # batch matrix multiplication - helper_test_op([(10,20,30),(10,30,40)], lambda a,b: torch.einsum('ijk,ikl->ijl', [a, b]), lambda a,b: Tensor.einsum('ijk,ikl->ijl', [a, b])) - # batch matrix multiplication, result permuted - helper_test_op([(10,20,25),(10,25,32)], lambda a,b: torch.einsum('ijk,ikl->jil', [a, b]), lambda a,b: Tensor.einsum('ijk,ikl->jil', [a, b])) - # batch matrix multiplication, result & input permuted - helper_test_op([(20,10,25),(10,25,32)], lambda a,b: torch.einsum('jik,ikl->jil', [a, b]), lambda a,b: Tensor.einsum('jik,ikl->jil', [a, b])) - # batch matrix multiplication, result with different letters - helper_test_op([(10,20,30),(10,30,40)], lambda a,b: torch.einsum('ijk,ika->ija', [a, b]), lambda a,b: Tensor.einsum('ijk,ika->ija', [a, b])) - # tensor contraction - helper_test_op([(3,5,8,10),(11,13,5,16,8)], lambda a,b: torch.einsum('pqrs,tuqvr->pstuv', a,b), - lambda a,b: Tensor.einsum('pqrs,tuqvr->pstuv', a,b), atol=1e-5) - # tensor contraction, input permuted - helper_test_op([(3,8,10,5),(11,5,13,16,8)], lambda a,b: torch.einsum('prsq,tquvr->pstuv', a,b), - lambda a,b: Tensor.einsum('prsq,tquvr->pstuv', a,b), atol=1e-5) - # tensor contraction, result with different letters - helper_test_op([(3,5,8,10),(11,13,5,16,8)], lambda a,b: torch.einsum('zqrs,tuqvr->zstuv', a,b), - lambda a,b: Tensor.einsum('zqrs,tuqvr->zstuv', a,b), atol=1e-5) - # bilinear transformation - helper_test_op([(2,3),(5,3,7),(2,7)], lambda a,b,c: torch.einsum('ik,jkl,il->ij', [a,b,c]), lambda a,b,c: Tensor.einsum('ik,jkl,il->ij', [a,b,c])) - - def test_einsum_ellipsis(self): - """The expected behavior for einsum is described in the PyTorch docs: https://pytorch.org/docs/stable/generated/torch.einsum.html""" - # test ellipsis - helper_test_op([(3, 8, 9), (3, 8, 9)], lambda a, b: torch.einsum('...id, ...jd -> ...ij', [a, b]), - lambda a, b: Tensor.einsum('...id, ...jd -> ...ij', [a, b])) - # ellipsis will come first in the output before the subscript labels, if rhs is not specified - helper_test_op([(3, 8, 9), (3, 8, 9)], lambda a, b: torch.einsum('...id, ...jd', [a, b]), - lambda a, b: Tensor.einsum('...id, ...jd', [a, b])) - # multiple ellipsis in different operands with different shapes are allowed - helper_test_op([(2, 3, 4, 5), (5, 2, 4)], lambda a, b: torch.einsum('i...j,ji...->...', [a, b]), - lambda a, b: Tensor.einsum('i...j,ji...->...', [a, b])) - # match torch ellipsis handling - helper_test_op([(32, 7, 24, 24, 24), (32, 7, 24, 24, 24)], lambda a, b: torch.einsum('ij...,ij...->ij', [a, b]), - lambda a, b: Tensor.einsum('ij...,ij...->ij', [a, b])) - # multiple ellipsis in one operand are not allowed. This test shall raise an exception. - with self.assertRaises(RuntimeError): - helper_test_op([(2, 3, 4), (2, 3, 4)], lambda a, b: torch.einsum('...ik..., ...jk ->', [a, b]), - lambda a, b: Tensor.einsum('...ik..., ...jk ->', [a, b])) - # multiple ellipsis must broadcast together. This test shall raise an exception. - with self.assertRaises(RuntimeError): - helper_test_op([(2, 3, 4, 5), (5, 2, 7)], lambda a, b: torch.einsum('i...j,ji...->...', [a, b]), - lambda a, b: Tensor.einsum('i...j,ji...->...', [a, b])) - - def test_einsum_shape_check(self): - a = Tensor.zeros(3,8,10,5) - b = Tensor.zeros(11,5,13,16,8) - with self.assertRaises(AssertionError): - Tensor.einsum('pqrs,tuqvr->pstuv',a,b) - - def test_einsum_arity_check1(self): - a = Tensor.zeros(10,15) - b = Tensor.zeros(15,20) - c = Tensor.zeros(20,10) - with self.assertRaises(AssertionError): - Tensor.einsum('ij,jk->ij', a,b,c) - - def test_einsum_arity_check2(self): - a = Tensor.zeros(10,10) - with self.assertRaises(AssertionError): - Tensor.einsum('ij,jk->ij', a) - - @unittest.skipIf(IMAGE>0, "no 1d dot for images") - def test_dot_1d(self): - helper_test_op([(65), (65)], lambda x,y: x.matmul(y), Tensor.dot) - helper_test_op([(65), (65,45)], lambda x,y: x.matmul(y), Tensor.dot) - helper_test_op([(45,65), (65)], lambda x,y: x.matmul(y), Tensor.dot) - helper_test_op([(8,45,65), (65)], lambda x,y: x.matmul(y), Tensor.dot) - helper_test_op([(65), (8,65,45)], lambda x,y: x.matmul(y), Tensor.dot) - self.helper_test_exception([(4), (1,2)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) - self.helper_test_exception([(2,1), (4)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) - self.helper_test_exception([(1), (4)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) - def test_dot(self): - helper_test_op([(45,65), (65,100)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-5) - helper_test_op([(8,45,65), (8,65,100)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-5) - self.helper_test_exception([(2, 4), (1, 3)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) - self.helper_test_exception([(2, 1), (4, 3)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) - with self.assertRaises(RuntimeError): - a = Tensor(3.14) - a.matmul(a) - def test_mulacc_with_zero_strides(self): - helper_test_op( - [], - lambda: torch.tensor(1.0).reshape((1,1,1)).expand(2,4,3).mul(torch.tensor(1.0).reshape((1,1,1)).expand(2,4,3)).sum(-1), - lambda: Tensor(1.0).reshape((1,1,1)).expand(2,4,3).mul(Tensor(1.0).reshape((1,1,1)).expand(2,4,3)).sum(-1), - forward_only=True - ) - a = [[1.,1.,1.,1.], [1.,1.,1.,1.]] - b = [1.,1.,1.,1.] - helper_test_op( - [], - lambda: torch.tensor(a).reshape((2,4,1)).expand(2,4,3).mul(torch.tensor(b).reshape((1,4,1)).expand(2,4,3)).sum([0,2]), - lambda: Tensor(a).reshape((2,4,1)).expand(2,4,3).mul(Tensor(b).reshape((1,4,1)).expand(2,4,3)).sum([0,2]), - forward_only=True - ) - helper_test_op( - [], - lambda: torch.ones((1,2)).matmul(torch.ones((2,3))), lambda: Tensor.ones((1,2)).dot(Tensor.ones((2,3))), - forward_only=True - ) - - def test_matmul_simple(self): - helper_test_op([(4), (4,4)], lambda x,y: x.matmul(y), Tensor.dot) - def test_matmul(self): - helper_test_op([(64), (64,99)], lambda x,y: x.matmul(y), Tensor.dot) - - @unittest.skipIf(IMAGE>0, "no batched matmul on images") - def test_matmul_batched(self): - helper_test_op([(3), (1,3,3,5)], lambda x,y: x.matmul(y), Tensor.dot) - - @unittest.skipIf(IMAGE>0, "no batched matmul on images") - def test_matmul_batched_vector(self): - helper_test_op([(4,3), (1,3,3,5)], lambda x,y: x.matmul(y), Tensor.dot) - def test_small_gemm(self): - helper_test_op([(8,8), (8,8)], lambda x,y: x.matmul(y), lambda x,y: x@y) - def test_9_gemm(self): - helper_test_op([(9,9), (9,9)], lambda x,y: x.matmul(y), lambda x,y: x@y) - def test_small_gemm_padded(self): - helper_test_op([(9,9), (9,9)], - lambda x,y: torch.nn.functional.pad(x, (0,7,0,7)).matmul(torch.nn.functional.pad(y, (0,7,0,7))), - lambda x,y: x.pad(((0,7),(0,7)))@y.pad(((0,7),(0,7)))) - def test_small_gemm_range(self): - helper_test_op(None, lambda x,y: x.matmul(y), lambda x,y: x@y, vals=[np.arange(0,64,dtype=np.float32).reshape(8,8), - np.arange(64,128,dtype=np.float32).reshape(8,8)]) - def test_small_gemm_eye(self): - helper_test_op(None, lambda x,y: x.matmul(y), lambda x,y: x@y, vals=[np.eye(8).astype(np.float32), np.eye(8).astype(np.float32)]) - @unittest.skipIf(CI and Device.DEFAULT in ["NV", "LLVM", "GPU", "CUDA"] or IMAGE, "not supported on these in CI/IMAGE") - def test_gemm_fp16(self): - helper_test_op([(64,64), (64,64)], lambda x,y: x.half().matmul(y.half()), atol=5e-3, rtol=5e-3) - def test_gemm(self): - helper_test_op([(64,64), (64,64)], lambda x,y: x.matmul(y)) - def test_big_gemm(self): - helper_test_op([(256,256), (256,256)], lambda x,y: x.matmul(y), atol=1e-4) - @unittest.skipIf(IMAGE>0, "no 0 in shape matmul on images") - def test_gemm_with_zeros_shape(self): - helper_test_op([(8,8), (8,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(0,8), (8,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(0,8), (8,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(8,0), (0,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(0,0), (0,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(0), (0,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - helper_test_op([(0), (0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) - def test_broadcastdot(self): - helper_test_op([(10,45,65), (65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) - with self.assertRaises(RuntimeError): - a = Tensor(3.14) - b = Tensor.ones(3,3) - a @ b - def test_multidot(self): - helper_test_op([(10,45,65), (10,65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) - helper_test_op([(3,3,45,65), (3,3,65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) - - def test_sum_simple(self): - helper_test_op(None, lambda x: x.sum(), vals=[[1.,1.]]) - # NOTE: simple test for locals - # FORWARD_ONLY=1 DEBUG=4 python3 test/test_ops.py TestOps.test_sum_full - def test_sum_full(self): - helper_test_op([(16384)], lambda x: x.sum()) - def test_sum_relu(self): - helper_test_op([(3,4,5)], lambda x: x.relu().sum().relu()) - def test_sum_tiny(self): - helper_test_op([(4,2,2)], lambda x: x.sum(axis=(0,2))) - def test_sum(self): - helper_test_op([(45,3)], lambda x: x.sum()) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=3)) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(1,3))) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(0,2))) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(1,2))) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=1)) - helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=1, keepdim=True)) - helper_test_op([()], lambda x: x.sum()) - helper_test_op([()], lambda x: x.sum(0)) - helper_test_op([()], lambda x: x.sum(-1)) - helper_test_op([()], lambda x: x.sum(())) - self.helper_test_exception([(3,4,5,6)], lambda x: x.sum(5), lambda x: x.sum(5), expected=IndexError) - self.helper_test_exception([()], lambda x: x.sum(1), lambda x: x.sum(1), expected=IndexError) - self.helper_test_exception([()], lambda x: x.sum((1,)), lambda x: x.sum((1,)), expected=IndexError) - - def test_sum_dtype_arg(self): - helper_test_op([(45,3)], lambda x: x.sum(), lambda x: x.sum(dtype=dtypes.float32)) - if is_dtype_supported(dtypes.float64): helper_test_op([(45,3)], lambda x: x.sum(dtype=torch.float64), lambda x: x.sum(dtype=dtypes.float64)) - - with self.assertRaises(AttributeError): Tensor([1.0, 2.0]).sum(dtype="") - - def test_sum_with_zeros_shape(self): - helper_test_op([(4, 0)], lambda x: x.sum(axis=(0,))) - helper_test_op([(4, 0)], lambda x: x.sum(axis=(1,))) - helper_test_op([(4, 0)], lambda x: x.sum(axis=(0,1))) - - def test_prod(self): - helper_test_op(None, lambda x: x.prod(), vals=[[1.0, 2.0, 3.0]]) - with Context(NOOPT=1): helper_test_op(None, lambda x: x.prod(), vals=[[1.0, 2.0, 3.0]]) - helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=3), lambda x: x.prod(axis=3)) - helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=1), lambda x: x.prod(axis=1)) - helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=1, keepdim=True), lambda x: x.prod(axis=1, keepdim=True)) - helper_test_op([()], lambda x: x.prod()) - helper_test_op([()], lambda x: x.prod(0)) - helper_test_op([()], lambda x: x.prod(-1)) - - def test_prod_dtype_arg(self): - with self.assertRaises(AttributeError): Tensor([1.0, 2.0]).prod(dtype="") - - def test_min(self): - helper_test_op([(3,3)], lambda x: x.min()) - helper_test_op([(45,3)], lambda x: x.min()) - helper_test_op([(45,3)], lambda x: x.min().mul(0.5)) - helper_test_op([()], lambda x: x.min()) - - helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[0, -2**31]]) - helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[-2**31, 0]]) - helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[False, True]]) - helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[True, False]]) - - def test_max(self): - helper_test_op([(45,3)], lambda x: x.max()) - helper_test_op([(45,3)], lambda x: x.max().mul(0.5)) - helper_test_op(None, lambda x: x.max().mul(0.5), vals=[[[1.0,1.0,0.0,1.0]],]) - helper_test_op([(3,4,5,6)], lambda x: x.max(axis=1)[0], lambda x: x.max(axis=1)) - helper_test_op([()], lambda x: x.max()) - - helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[0, -2**31]]) - helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[-2**31, 0]]) - helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[False, True]]) - helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[True, False]]) - - @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") - def test_any(self): - helper_test_op([(3,4,5,6)], lambda x: x.any(), forward_only=True) - helper_test_op(None, lambda x: x.any(), vals=[[True, True]], forward_only=True) - helper_test_op(None, lambda x: x.any(), vals=[[True, False]], forward_only=True) - helper_test_op(None, lambda x: x.any(), vals=[[False, False]], forward_only=True) - helper_test_op([()], lambda x: x.any(), forward_only=True) - def test_any_axis(self): - helper_test_op([(3,4,5,6)], lambda x: x.any(axis=(1,2)), forward_only=True) - def test_any_zero_axis(self): - helper_test_op([(1,0,3,0,5)], lambda x: x.any(axis=(1,3)), forward_only=True) - - @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") - def test_all(self): - helper_test_op([(3,4,5,6)], lambda x: x.all(), forward_only=True) - helper_test_op(None, lambda x: x.all(), vals=[[True, True]], forward_only=True) - helper_test_op(None, lambda x: x.all(), vals=[[True, False]], forward_only=True) - helper_test_op(None, lambda x: x.all(), vals=[[False, False]], forward_only=True) - helper_test_op([()], lambda x: x.all(), forward_only=True) - def test_all_axis(self): - helper_test_op([(3,4,5,6)], lambda x: x.all(axis=(1,2)), forward_only=True) - def test_all_zero_axis(self): - helper_test_op([(1,0,3,0,5)], lambda x: x.all(axis=(1,3)), forward_only=True) - - def test_isclose(self): - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x), forward_only=True) - helper_test_op([(3, 4, 5, 6), (3, 4, 5, 6)], lambda x,y: x.isclose(y), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x, equal_nan=True), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6, atol=0.0), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9, atol=0.0), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6, rtol=0.01), forward_only=True) - helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9, rtol=0.01), forward_only=True) - helper_test_op(None, lambda x,y: x.isclose(y), vals=[[1e-7, 1e-8, 1e-9], [0.0, 0.0, 0.0]], forward_only=True) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and CI, "isinf check of 'nan' fails on CI software-based vulkan") - def test_isclose_edge_cases(self): - for a in [math.inf, -math.inf, math.nan, 0.0]: - for b in [math.inf, -math.inf, math.nan, 0.0]: - helper_test_op(None, lambda x,y: x.isclose(y), vals=[[a], [b]], forward_only=True) - helper_test_op(None, lambda x,y: x.isclose(y, equal_nan=True), vals=[[a], [b]], forward_only=True) - - def test_mean(self): - helper_test_op([(3,4,5,6)], lambda x: x.mean()) - helper_test_op([()], lambda x: x.mean()) - def test_mean_axis(self): - helper_test_op([(3,4,5,6)], lambda x: x.mean(axis=(1,2))) - def test_mean_zero_axis(self): - helper_test_op([(1,0,3,0,5)], lambda x: x.mean(axis=(1,3))) - - def test_var(self): - helper_test_op([(15, 25, 35)], lambda x: x.var()) - helper_test_op([(15, 25, 35)], lambda x: x.var(correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.var(correction=5)) - # TODO: fix this - # helper_test_op([(10, 2)], lambda x: x.var(correction=50)) - def test_var_axis(self): - helper_test_op([(15, 25, 35)], lambda x: x.var(0)) - helper_test_op([(15, 25, 35)], lambda x: x.var(2)) - helper_test_op([(15, 25, 35)], lambda x: x.var([1, 2])) - helper_test_op([(15, 25, 35)], lambda x: x.var(0, correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.var(2, correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.var([1, 2], correction=0)) - def test_var_zero_in_axis(self): - with warnings.catch_warnings(): - warnings.filterwarnings("ignore", message="var\\(\\): degrees of freedom is <= 0") - helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3))) - helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3), correction=0)) - helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3), correction=5)) - def test_var_one_in_axis(self): - with warnings.catch_warnings(): - warnings.filterwarnings("ignore", message="var\\(\\): degrees of freedom is <= 0") - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3))) - # TODO: fix backward - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3), correction=5), forward_only=True) - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4), correction=5), forward_only=True) - helper_test_op([(1,)], lambda x: x.var(axis=(0,), correction=0)) - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3), correction=0)) - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4))) - helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4), correction=0)) - def test_var_keepdim(self): - helper_test_op([(15, 25, 35)], lambda x: x.var(keepdim=True)) - helper_test_op([(15, 25, 35)], lambda x: x.var(0, keepdim=True, correction=0)) - - def test_std(self): - helper_test_op([(15, 25, 35)], lambda x: x.std()) - helper_test_op([(15, 25, 35)], lambda x: x.std(correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.std(correction=5)) - def test_std_axis(self): - helper_test_op([(15, 25, 35)], lambda x: x.std(0)) - helper_test_op([(15, 25, 35)], lambda x: x.std(2)) - helper_test_op([(15, 25, 35)], lambda x: x.std([1, 2])) - helper_test_op([(15, 25, 35)], lambda x: x.std(0, correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.std(2, correction=0)) - helper_test_op([(15, 25, 35)], lambda x: x.std([1, 2], correction=0)) - def test_std_zero_in_axis(self): - with warnings.catch_warnings(): - warnings.filterwarnings("ignore", message="std\\(\\): degrees of freedom is <= 0") - helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3))) - helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3), correction=0)) - helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3), correction=5)) - def test_std_one_in_axis(self): - with warnings.catch_warnings(): - warnings.filterwarnings("ignore", message="std\\(\\): degrees of freedom is <= 0") - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3))) - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3), correction=5)) - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4), correction=5)) - # TODO: fix backward - helper_test_op([(1,)], lambda x: x.std(axis=(0,), correction=0), forward_only=True) - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3), correction=0), forward_only=True) - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4))) - helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4), correction=0)) - def test_std_keepdim(self): - helper_test_op([(15, 25, 35)], lambda x: x.std(keepdim=True)) - helper_test_op([(15, 25, 35)], lambda x: x.std(0, keepdim=True, correction=0)) - def test_std_mean(self): - helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x)), - lambda x: Tensor.stack(*x.std_mean())) - helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x, correction=5)), - lambda x: Tensor.stack(*x.std_mean(correction=5))) - helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x, keepdim=True, correction=0)), - lambda x: Tensor.stack(*x.std_mean(keepdim=True, correction=0))) - helper_test_op([(3,4,5,6)], lambda x: torch.stack(torch.std_mean(x, axis=(1,2))), - lambda x: Tensor.stack(*x.std_mean(axis=(1,2)))) - - @unittest.skip("TODO: this fails because of loaded nan in mul folding") - def test_std_mean_loaded_nan(self): - helper_test_op([(1,0,3,0,5)], lambda x: torch.stack(torch.std_mean(x, axis=(1,3))), - lambda x: Tensor.stack(*x.std_mean(axis=(1,3)))) - def test_softmax(self): - helper_test_op([(45,65)], torch.nn.Softmax(dim=1), Tensor.softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([(45)], torch.nn.Softmax(dim=0), Tensor.softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([()], torch.nn.Softmax(dim=0), Tensor.softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([()], torch.nn.Softmax(dim=-1), Tensor.softmax, atol=1e-7, grad_atol=1e-7) - def test_softmax_other_axis(self): - helper_test_op([(10,10,10)], lambda x: x.softmax(0), atol=1e-7, grad_atol=2e-7) - helper_test_op([(10,10,10)], lambda x: x.softmax(1), atol=1e-7, grad_atol=2e-7) - helper_test_op([(10,10,10)], lambda x: x.softmax(2), atol=1e-7, grad_atol=2e-7) - def test_softmax_argmax(self): - helper_test_op([(45,65)], lambda x: x.softmax(0).argmax().type(torch.int32), - lambda x: x.softmax(0).argmax(), forward_only=True, atol=1e-7, grad_atol=1e-7) - helper_test_op([(45,65)], lambda x: x.softmax(1).argmax().type(torch.int32), - lambda x: x.softmax(1).argmax(), forward_only=True, atol=1e-7, grad_atol=1e-7) - def test_log_softmax(self): - helper_test_op([(45,65)], torch.nn.LogSoftmax(dim=1), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([(45)], torch.nn.LogSoftmax(dim=0), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([()], torch.nn.LogSoftmax(dim=0), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) - helper_test_op([()], torch.nn.LogSoftmax(dim=-1), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) - def test_log_softmax_other_axis(self): - helper_test_op([(10,10,10)], lambda x: x.log_softmax(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([(10,10,10)], lambda x: x.log_softmax(1), atol=1e-7, grad_atol=1e-7) - helper_test_op([(10,10,10)], lambda x: x.log_softmax(2), atol=1e-7, grad_atol=1e-7) - - def test_logsumexp(self): - helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=0, keepdim=True), lambda x: x.logsumexp(0, True), atol=1e-7, grad_atol=1e-7) - helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=1), lambda x: x.logsumexp(1), atol=1e-7, grad_atol=1e-7) - helper_test_op([(45)], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([()], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([()], lambda x: torch.logsumexp(x, dim=-1), lambda x: x.logsumexp(-1), atol=1e-7, grad_atol=1e-7) - - def test_logcumsumexp(self): - helper_test_op([(45,65)], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([(45,65)], lambda x: torch.logcumsumexp(x, dim=1), lambda x: x.logcumsumexp(1), atol=1e-7, grad_atol=1e-7) - helper_test_op([(45)], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) - helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(), atol=1e-7, grad_atol=1e-7) - helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=-1), lambda x: x.logcumsumexp(-1), atol=1e-7, grad_atol=1e-7) - - @unittest.skipIf(not DEVECTORIZE, "broken without DEVECTORIZE. TODO: fix this") - def test_logcumsumexp_numerical(self): - helper_test_op(None, lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(), atol=1e-7, grad_atol=1e-7, vals=[[0.0, 100.0]]) - - def test_sinh(self): - helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6) - # TODO: backward nan instead of inf - helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6, low=-300, high=-297, forward_only=True) - helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6, low=300, high=303, forward_only=True) - def test_cosh(self): - helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6) - # TODO: backward nan instead of inf - helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6, low=-300, high=-297, forward_only=True) - helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6, low=300, high=303, forward_only=True) - def test_tanh(self): - helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6) - def test_tanh_extreme(self): - helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6, low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6, low=300, high=303) - def test_hardtanh(self): - for val in range(10, 30, 5): - helper_test_op([(45,65)], lambda x: torch.nn.functional.hardtanh(x, -val, val), lambda x: x.hardtanh(-val, val), grad_atol=1e-6) - helper_test_op([()], lambda x: torch.nn.functional.hardtanh(x, -val, val), lambda x: x.hardtanh(-val, val), grad_atol=1e-6) - def test_asinh(self): - helper_test_op([(45,65)], lambda x: x.asinh(), grad_atol=1e-6) - # TODO: this one has larger tol? - helper_test_op([(45,65)], lambda x: x.asinh(), atol=1e-2, rtol=2e-2, grad_rtol=2e-2, low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.asinh(), grad_atol=1e-6, low=300, high=303) - def test_acosh(self): - helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-6) - helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-3, grad_rtol=1e-2, low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-6, low=300, high=303) - def test_atanh(self): - helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6) - helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6, low=-300, high=-297) - helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6, low=300, high=303) - - def test_topo_sort(self): - helper_test_op([(45,65)], lambda x: (x+x)*x, grad_atol=1e-6) - helper_test_op([()], lambda x: (x+x)*x, grad_atol=1e-6) - - def test_flip_eye_crash(self): - helper_test_op([], lambda: (torch.eye(10)@torch.eye(10).flip(0)), - lambda: (Tensor.eye(10)@Tensor.eye(10).flip(0)), forward_only=True) - - def test_broadcast_full(self): - for torch_op, tinygrad_op in [(torch.add, Tensor.add), (torch.sub, Tensor.sub), (torch.mul, Tensor.mul), - (torch.div, Tensor.div), (torch.pow, Tensor.pow)]: - for shapes in [((5,13,24,16), (5,1,24,1)), ((1,3,1,7,1), (2,1,5,1,8))]: - with self.subTest(op=torch_op.__name__, shapes=shapes): - if tinygrad_op != Tensor.pow: - helper_test_op(shapes, torch_op, tinygrad_op) - else: - helper_test_op(shapes, torch_op, tinygrad_op, low=0, high=3) - - def test_broadcast_simple(self): - helper_test_op([(45,65), (45,1)], lambda x,y: x/y) - helper_test_op([(45,65), ()], lambda x,y: x/y) - - def test_broadcast_partial(self): - for torch_op, tinygrad_op in [(torch.add, Tensor.add), (torch.sub, Tensor.sub), (torch.mul, Tensor.mul), - (torch.div, Tensor.div), (torch.pow, Tensor.pow)]: - for shapes in [((1,32,32,32), (1,32,1,1)), ((5,13,24,16,2), (1,13,24,1,1)), - ((4,1), (4,5)), ((1,4), (5,4))]: - with self.subTest(op=torch_op.__name__, shapes=shapes): - # NOTE: ANE backwards? - if tinygrad_op != Tensor.pow: - helper_test_op(shapes, torch_op, tinygrad_op) - else: - helper_test_op(shapes, torch_op, tinygrad_op, low=0, high=3) - - def test_slice_in_bounds_1dim(self): - helper_test_op([(3)], lambda x: x[1:3]) - helper_test_op([(3)], lambda x: x[0:2]) - helper_test_op([(3)], lambda x: x[-2:2]) - - def test_slice_on_0dim_tensor(self): - helper_test_op([()], lambda x: x[None]) - - with self.assertRaises(IndexError): - a = Tensor(3.14) - a[0] - - def test_slice_int_indexing(self): - helper_test_op([(3)], lambda x: x[0]) - helper_test_op([(3)], lambda x: x[2]) - helper_test_op([(3)], lambda x: x[-1]) - helper_test_op([(3)], lambda x: x[-3]) - helper_test_op([(10,10)], lambda x: x[1]) - helper_test_op([(3,3,3)], lambda x: x[1,1,1]) - - def test_slice_in_bounds_multidim(self): - helper_test_op([(3,3,3)], lambda x: x[1:2]) - helper_test_op([(3,3,3)], lambda x: x[1:2, 2]) - helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2]) - helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2, 0:-1]) - - def test_slice_with_none(self): - helper_test_op([(3,3,3)], lambda x: x[None]) - helper_test_op([(3,3,3)], lambda x: x[1:2, None]) - helper_test_op([(3,3,3)], lambda x: x[1:2, None, 1:2]) - helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2, None, -1]) - helper_test_op([(3,3,3)], lambda x: x[None, None, 1, None, 2, 0:2]) - - def test_slice_with_const_tensor(self): - t = Tensor.zeros(1, dtype=dtypes.int) - helper_test_op([(3,3,3)], lambda x: x[:, [0], :], lambda x: x[:, t, :]) - helper_test_op([(3,3,3)], lambda x: x[:, [0], :], lambda x: x[:, t.contiguous(), :]) - - def test_slice_one_endpoint_out_of_bounds(self): - helper_test_op([(3,3,3)], lambda x: x[0:4]) - helper_test_op([(3,3,3)], lambda x: x[-6:4]) - helper_test_op([(3,3,3)], lambda x: x[1:50]) - helper_test_op([(3,3,3)], lambda x: x[1:50, 1:2, -1]) - - def test_slice_stride_gt_one(self): - helper_test_op([(7,5,10)], lambda x: x[::2, ::3, ::4]) - helper_test_op([(7,5,10)], lambda x: x[1:5:2, ::3, ::4]) - helper_test_op([(7,5,10)], lambda x: x[1:5:2, 3, ::4]) - helper_test_op([(7,5,10)], lambda x: x[1:5:2, None, None, 3, None, ::4]) - - def test_slice_negative_strides(self): - # Torch doesn't support slicing with negative steps - a = np.random.randn(10, 10, 10).astype(np.float32) - t = Tensor(a) - np.testing.assert_allclose(a[::-1], t[::-1].numpy()) - np.testing.assert_allclose(a[::-2], t[::-2].numpy()) - np.testing.assert_allclose(a[:, 2:0:-1], t[:, 2:0:-1].numpy()) - np.testing.assert_allclose(a[:, 2:0:-1, 3:1:-2], t[:, 2:0:-1, 3:1:-2].numpy()) - np.testing.assert_allclose(a[4:0:-3, 2:0:-1, -1:-5:-2], t[4:0:-3, 2:0:-1, -1:-5:-2].numpy()) - np.testing.assert_allclose(a[2:5:-1, :, :], t[2:5:-1, :, :].numpy()) # shape = (0, 10, 10) - np.testing.assert_allclose(a[:, 2:5:-1, :], t[:, 2:5:-1, :].numpy()) # shape = (0, 10, 10) - np.testing.assert_allclose(a[:, :, 2:5:-1], t[:, :, 2:5:-1].numpy()) # shape = (0, 10, 10) - - def test_slice_both_endpoints_out_of_bounds(self): - helper_test_op([(3,3,3)], lambda x: x[5:10]) - helper_test_op([(3,3,3)], lambda x: x[-15:-7]) - - def test_slice_start_gt_end(self): - helper_test_op([(3,3,3)], lambda x: x[-2:2]) - helper_test_op([(3,3,3)], lambda x: x[-2:-5]) - - def test_slice_empty(self): - helper_test_op([(10,10)], lambda x: x[1:1]) - - def test_slice_zero_in_shape(self): - helper_test_op([(10,10)], lambda x: x[1:1]) # x.shape = (0, 10) - helper_test_op([(3,3,3)], lambda x: x[-2:-5]) # x.shape = (0, 3, 3) - - def test_slice_errors(self): - a = Tensor.ones(4, 3) - b = Tensor(2) - with self.assertRaisesRegex(IndexError, "too many"): a[1, 77, 77, 77] # IndexError: (finds too many indices before the out of bounds) - with self.assertRaisesRegex(IndexError, "out of bounds"): a[1, 3] # IndexError: (out of bounds). - with self.assertRaisesRegex(IndexError, "out of bounds"): a[1, -4] - with self.assertRaisesRegex(IndexError, "single ellipsis"): a[..., ...] # IndexError: only single ellipsis - with self.assertRaises(ValueError): a[::0, 1] # no 0 strides - with self.assertRaises(TypeError): a[:Tensor([3]), 1] # Tensor can't be used as a slice parameter - with self.assertRaises(IndexError): b[:] # slice cannot be applied to a 0-dim tensor - - def test_slice_ellipsis(self): - helper_test_op([(3,3,3,3)], lambda x: x[..., 0]) - helper_test_op([(3,3,3,3)], lambda x: x[0, ...]) - helper_test_op([(3,3,3,3)], lambda x: x[0, ..., 0]) - helper_test_op([(3,3,3,3)], lambda x: x[0:3, ..., 2:3]) - helper_test_op([(3,3,3,3)], lambda x: x[None, 0:3, ..., 0, None]) - - # this was the failure in llama early realizing freqs_cis - def test_double_slice(self): - helper_test_op([(4,4)], lambda x: x[:, 1:2][1:2]) - helper_test_op([(4,4)], lambda x: x[1:3][1:2]) - helper_test_op([(4,4)], lambda x: x[:, 1:2][0:1]) - helper_test_op([(4,4)], lambda x: x[:, 1:2][:, 0:1]) - - def test_pad(self): - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4)), lambda x: x.pad(padding=(1,2,3,4))) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4)), lambda x: x.pad(padding=(-1,2,-3,4))) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=5), lambda x: x.pad(padding=(1,2,3,4),value=5)) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4), value=5), lambda x: x.pad(padding=(-1,2,-3,4),value=5)) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=math.inf), lambda x: x.pad(padding=(1,2,3,4),value=math.inf)) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4), value=-math.inf), - lambda x: x.pad(padding=(-1,2,-3,4),value=-math.inf)) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4)),lambda x: x.pad(((3,4),(1,2)))) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4)), lambda x: x.pad(((-3,4), (-1,2)))) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=5), lambda x: x.pad(((3,4), (1,2)), value=5)) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,3,4), value=1), lambda x: x.pad(((3,4), None), value=1)) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,0,0), value=1), lambda x: x.pad((None, None), value=1)) - # raise error for uneven pads - self.helper_test_exception([(3,3)], lambda x: torch.nn.functional.pad(x, (2,0,2)), lambda x: x.pad((2,0,2)), - expected=(RuntimeError, ValueError)) - # raise error for too many or too little pads - self.helper_test_exception([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,0,0,1,0,3,0)), lambda x: x.pad((0,0,0,0,1,0,3,0)), - expected=(RuntimeError, ValueError)) - # raise error for mode string typo - self.helper_test_exception([(3,3,3)], lambda x: torch.nn.functional.pad(x, (3,0), mode="typo"), lambda x: x.pad((3,0), mode="typo"), - expected=NotImplementedError) - x = Tensor.ones(3,3) - with self.assertRaises(ValueError): x.pad((None,(0,1),(3,0))) - with self.assertRaises(ValueError): x.pad(((0,1),)) - - def test_pad_reflect_mode(self): - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="reflect"), lambda x: x.pad((0,2,3,2), mode="reflect")) - helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="reflect"), lambda x: x.pad((0,2), mode="reflect")) - helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,4,1,2), mode="reflect"), - lambda x: x.pad((1,2,3,4,1,2), mode="reflect")) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,2,-1), mode="reflect"), lambda x: x.pad((-1,2,2,-1), mode="reflect")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-3,0,-3), mode="reflect"), lambda x: x.pad((3,-3,0,-3), mode="reflect")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-5,1,-5), mode="reflect"), lambda x: x.pad((3,-5,1,-5), mode="reflect")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,0,0,-5), mode="reflect"), lambda x: x.pad((0,0,0,-5), mode="reflect")) - - # max pad size for reflect is exactly once: pad < input size - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (4,4,0,4), mode="reflect"), lambda x:x.pad((4,4,0,4),mode="reflect")) - # raise error for relfection padding when: pad >= input size - self.helper_test_exception([(1,1,5,5)], - lambda x: torch.nn.functional.pad(x, (3,5,0,0),mode="reflect"), lambda x: x.pad((3,5,0,0),mode="reflect"), - expected=(RuntimeError, ValueError)) - - def test_pad_replicate_mode(self): - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="replicate"), lambda x: x.pad((0,2,3,2), mode="replicate")) - helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="replicate"), lambda x: x.pad((0,2), mode="replicate")) - helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,4,1,2),mode="replicate"),lambda x:x.pad((1,2,3,4,1,2),mode="replicate")) - helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,2,-1), mode="replicate"), lambda x: x.pad((-1,2,2,-1), mode="replicate")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-3,0,-3), mode="replicate"), lambda x: x.pad((3,-3,0,-3), mode="replicate")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-5,1,-5), mode="replicate"), lambda x: x.pad((3,-5,1,-5), mode="replicate")) - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,0,0,-5), mode="replicate"), lambda x: x.pad((0,0,0,-5), mode="replicate")) - - # no max pad sizes for replicate - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,11,0,30), mode="replicate"), lambda x: x.pad((3,11,0,30), mode="replicate")) - - def test_pad_circular_mode(self): - helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="circular"), lambda x: x.pad((0,2,3,2), mode="circular")) - helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="circular"), lambda x: x.pad((0,2), mode="circular")) - helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,5,1,2),mode="circular"),lambda x:x.pad((1,2,3,5,1,2),mode="circular")) - # circular pad cannot wrap around more than once - self.helper_test_exception([(1,1,5,5)], - lambda x: torch.nn.functional.pad(x, (3,6,0,0), mode="circular"), lambda x: x.pad((3,6,0,0), mode="circular"), - expected=(RuntimeError, ValueError)) - with self.assertRaises(NotImplementedError): - # negative pads with circular pads is not supported - Tensor.randn(1,1,5,5).pad((3,-5,1,-5), mode="circular") - - def test_pad_reshape(self): - helper_test_op([(1, 2)], - lambda x: torch.nn.functional.pad(x, (0, 1, 1, 0)).reshape((3, 2)), - lambda x: x.pad((0, 1, 1, 0)).reshape((3, 2))) - helper_test_op([(1, 2)], - lambda x: torch.nn.functional.pad(x, (0, 2, 1, 1)).reshape((4, 3)), - lambda x: x.pad((0, 2, 1, 1)).reshape((4, 3))) - helper_test_op([(1, 1, 1, 2)], - lambda x: torch.nn.functional.pad(x, (0, 4, 2, 2, 1, 2, 0, 2)).reshape((4, 3, 6, 5)), - lambda x: x.pad(((0, 2), (1, 2), (2, 2), (0, 4))).reshape((4, 3, 6, 5))) - - def test_pad_slice(self): - for value in 0., 3.456: - helper_test_op([(1)], lambda x: torch.nn.functional.pad(x,(1,0), value=value)[0], lambda x: x.pad(((1,0),), value=value)[0]) - helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(1,0), value=value)[0], lambda x: x.pad(((1,0),), value=value)[0]) - helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(3,0), value=value)[0:1], lambda x: x.pad(((3,0),), value=value)[0:1]) - helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(0,3), value=value)[6], lambda x: x.pad(((0,3),), value=value)[6]) - helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(0,3), value=value)[4:6], lambda x: x.pad(((0,3),), value=value)[4:6]) - helper_test_op([(5,5)], lambda x: torch.nn.functional.pad(x,(0,0,1,0), value=value)[0], lambda x: x.pad(((1,0),(0,0)), value=value)[0]) - helper_test_op([(2,2)], lambda x: torch.nn.functional.pad(x,(0,1,0,0), value=value)[0,2], lambda x: x.pad(((0,0),(0,1)), value=value)[0,2]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,1,0), value=value)[0,2], lambda x: x.pad(((1,0),(0,0)), value=value)[0,2]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,0,2), value=value)[5], lambda x: x.pad(((0,2),(0,0)), value=value)[5]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,0,2), value=value)[3:5], lambda x: x.pad(((0,2),(0,0)), value=value)[3:5]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,0,0,0), value=value)[1,0], lambda x: x.pad(((0,0),(3,0)), value=value)[1,0]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,0,0,0), value=value)[1,0:4], lambda x: x.pad(((0,0),(3,0)), value=value)[1,0:4]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[0], lambda x: x.pad(((1,2),(3,4)), value=value)[0]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[:,1], lambda x: x.pad(((1,2),(3,4)), value=value)[:,1]) - helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[:,4], lambda x: x.pad(((1,2),(3,4)), value=value)[:,4]) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x,(0,3,0,0), value=value)[:,4:6], lambda x: x.pad(((0,0),(0,3)), value=value)[:,4:6]) - helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x,(0,1,3,2), value=value)[0:2,:], lambda x: x.pad(((3,2),(0,1)), value=value)[0:2,:]) - helper_test_op([(3,3,3)], lambda x: torch.nn.functional.pad(x,(1,1,0,1,3,2), value=value)[0:2,:,:], - lambda x: x.pad(((3,2),(0,1),(1,1)), value=value)[0:2,:,:]) - helper_test_op([(3,3,3)], lambda x: torch.nn.functional.pad(x,(1,1,0,1,3,2), value=value)[2:4,:,:], - lambda x: x.pad(((3,2),(0,1),(1,1)), value=value)[2:4,:,:]) - - def test_stack_slice(self): - helper_test_op([(4)], lambda x: torch.stack([x for i in range(3)])[0,:], lambda x: Tensor.stack(*[x for i in range(3)])[0,:]) - helper_test_op([(5)], lambda x: torch.stack([x for i in range(3)])[0,0], lambda x: Tensor.stack(*[x for i in range(3)])[0,0]) - helper_test_op([(4,4)], lambda x: torch.stack([x for i in range(4)])[3], lambda x: Tensor.stack(*[x for i in range(4)])[3]) - - def test_transpose(self): - helper_test_op([(3,3)], lambda x: x.T) - helper_test_op([(3,3,3)], lambda x: x.transpose(1,2)) - helper_test_op([(3,3,3)], lambda x: x.transpose(0,2)) - - def test_permute(self): - helper_test_op([(1,2,3,4)], lambda x: x.permute((3,0,2,1))) - helper_test_op([(3,4,5,6)], lambda x: x.permute((3,2,1,0))) - helper_test_op([(3,4,5,6)], lambda x: x.permute((-2,-1,1,0))) - helper_test_op([()], lambda x: x.permute(())) - self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,2)), lambda x: x.permute((0,2)), expected=RuntimeError) - self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,1,2,3,3,3)), lambda x: x.permute((0,1,2,3,3,3)), expected=RuntimeError) - self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,0,1,2,3)), lambda x: x.permute((0,0,1,2,3)), expected=RuntimeError) - - def test_reshape(self): - helper_test_op([(4,3,6,6)], lambda x: x.reshape((12,6,6))) - helper_test_op([(4,3,6,6)], lambda x: x.reshape((-1,3,6,6))) - helper_test_op([(4,3,6,6)], lambda x: x.reshape((-1,1,6,6))) - helper_test_op([(4,3,6,6)], lambda x: x.reshape((4,3,6,6)), lambda x: x.reshape((None,None,6,6))) - helper_test_op([()], lambda x: x.reshape(())) - helper_test_op([(1,)], lambda x: x.reshape(())) - helper_test_op([()], lambda x: x.reshape((1,))) - helper_test_op([()], lambda x: x.reshape((1,1,1))) - self.helper_test_exception([(3,4)], lambda x: x.reshape((-1,-1,2)), lambda x: x.reshape((-1,-1,2)), expected=RuntimeError) - self.helper_test_exception([(3,4)], lambda x: x.reshape((-1,-1,-1,2)), lambda x: x.reshape((-1,-1,-1,2)), expected=RuntimeError) - - with self.assertRaises(ValueError): - x = Tensor.ones((4,3,6,6)) - x.reshape([]) - - def test_view(self): - helper_test_op([(4,3,6,6)], lambda x: x.view((12,6,6))) - helper_test_op([(4,3,6,6)], lambda x: x.view((-1,3,6,6))) - helper_test_op([(6,)], lambda x: x.view(2, 3)) - helper_test_op([(6,1)], lambda x: x.view([2, 3])) - helper_test_op([(1,6)], lambda x: x.view((3, 2))) - helper_test_op([(3,2)], lambda x: x.view((2, 3))) - helper_test_op([(3,2)], lambda x: x.view(6)) - - def test_flip(self): - helper_test_op([(4,3,6,6)], lambda x: x.flip((0,))) - helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1))) - helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1,3))) - helper_test_op([(4,3,6,6)], lambda x: x.flip((3,))) - helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1,3)).flip(0)) - helper_test_op([(4,3,6,6)], lambda x: x.flip((-1,))) - helper_test_op([()], lambda x: x.flip(())) - helper_test_op([(1,)], lambda x: x.flip(())) - helper_test_op([(4,3,6,6)], lambda x: x.flip(())) - self.helper_test_exception([(3,4)], lambda x: x.flip((0,0)), lambda x: x.flip((0,0)), expected=RuntimeError) - self.helper_test_exception([(3,4)], lambda x: x.flip((1,1)), lambda x: x.flip((1,1)), expected=RuntimeError) - self.helper_test_exception([(3,4)], lambda x: x.flip((1,-1)), lambda x: x.flip((1,-1)), expected=RuntimeError) - - def test_squeeze(self): - helper_test_op([(1,3,6,6)], lambda x: x.squeeze(0)) - helper_test_op([(4,3,1,6)], lambda x: x.squeeze(1)) - helper_test_op([(4,3,6,6)], lambda x: x.squeeze(3)) - self.helper_test_exception([(4,3,6,6)], lambda x: torch.squeeze(x, 50), lambda x: x.squeeze(dim=50), expected=IndexError) - self.helper_test_exception([(4,3,6,6)], lambda x: torch.squeeze(x, -50), lambda x: x.squeeze(dim=-50), expected=IndexError) - helper_test_op([(4,3,6,1)], lambda x: x.squeeze(-1)) - helper_test_op([(4,3,6,6)], lambda x: x.squeeze()) - helper_test_op([(1,3,6,6)], lambda x: x.squeeze()) - helper_test_op([(2,3,1)], lambda x: x.squeeze()) - helper_test_op([()], lambda x: x.squeeze(-1)) - helper_test_op([()], lambda x: x.squeeze(0)) - helper_test_op([()], lambda x: x.squeeze()) - self.helper_test_exception([()], lambda x: torch.squeeze(x, 10), lambda x: x.squeeze(dim=10), expected=IndexError) - self.helper_test_exception([()], lambda x: torch.squeeze(x, 1), lambda x: x.squeeze(dim=1), expected=IndexError) - self.helper_test_exception([()], lambda x: torch.squeeze(x, -2), lambda x: x.squeeze(dim=-2), expected=IndexError) - - def test_unsqueeze(self): - helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(0)) - helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(4)) - helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(-1)) - helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(-3)) - helper_test_op([()], lambda x: x.unsqueeze(0)) - - def test_flatten(self): - for axis in range(3): - helper_test_op([(4,3,6,6)], lambda x: x.flatten(start_dim=axis)) - for axis in range(3): - helper_test_op([(4,3,6,6)], lambda x: x.flatten(end_dim=axis)) - helper_test_op([(4,3,6,6)], lambda x: x.flatten(start_dim=1, end_dim=3)) - helper_test_op([()], lambda x: x.flatten()) - helper_test_op([(1,)], lambda x: x.flatten()) - - def test_unflatten(self): - helper_test_op([(4,3,6,6)], lambda x: x.unflatten(0, (2, 2))) - helper_test_op([(4,3,6,6)], lambda x: x.unflatten(3, (3, 2))) - helper_test_op([(4,3,6,6)], lambda x: x.unflatten(-1, (3, 2, 1))) - - def test_roll(self): - helper_test_op([(2, 4)], lambda x: torch.roll(x, 1, 0), lambda x: x.roll(1, 0)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, -1, 0), lambda x: x.roll(-1, 0)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, shifts=(2, 1), dims=(0, 1)), lambda x: x.roll(shifts=(2, 1), dims=(0, 1))) - helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, 1, 0), lambda x: x.roll(1, 0)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, 1, -1), lambda x: x.roll(1, -1)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, -1, -1), lambda x: x.roll(-1, -1)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, 5, 0), lambda x: x.roll(5, 0)) - helper_test_op([(2, 4)], lambda x: torch.roll(x, -5, 0), lambda x: x.roll(-5, 0)) - helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(2, -3), dims=(0, 2)), lambda x: x.roll(shifts=(2, -3), dims=(0, 2))) - helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(1, 2, -1), dims=(0, 1, 2)), lambda x: x.roll(shifts=(1, 2, -1), dims=(0, 1, 2))) - helper_test_op([(2, 4)], lambda x: torch.roll(x, 0, 0), lambda x: x.roll(0, 0)) - helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(0, 0), dims=(0, 1)), lambda x: x.roll(shifts=(0, 0), dims=(0, 1))) - helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(0, 2), dims=(0, 1)), lambda x: x.roll(shifts=(0, 2), dims=(0, 1))) - - def test_detach(self): - helper_test_op([(4,3,6,6)], lambda x: x.detach(), forward_only=True) - helper_test_op([()], lambda x: x.detach(), forward_only=True) - - def test_expand(self): - helper_test_op([(4,3,1,6)], lambda x: x.expand((4,3,2,6))) - helper_test_op([(1,1,1,1)], lambda x: x.expand((4,3,2,6))) - helper_test_op([(4,3,1,6)], lambda x: x.expand((6,1,4,3,2,6))) - helper_test_op([(4,3,1,6)], lambda x: x.expand((0,1,4,3,2,6))) - helper_test_op([(4,3,1,6)], lambda x: x.expand((4,3,0,6))) - helper_test_op([()], lambda x: x.expand((4,3,2,6))) - helper_test_op([()], lambda x: x.expand([])) - - with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(4,1,1,6) - with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(4,6,1,6) - with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(3,1,6) - with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,2,6).expand(4,3,0,6) - - @unittest.skip("very slow") - def test_sd_big_conv(self): - # internal shape (1, 1, 512, 62, 62, 512, 3, 3) overflows a int - helper_test_op([(1,256,64,64), (512,256,3,3)], - lambda x,w: torch.nn.functional.conv2d(x, w), - lambda x,w: x.conv2d(w), atol=1e-3) - - @unittest.skip("slow") - def test_large_bs_conv(self): - # large batch size can cause OpenCL image to exceed max image height on macOS - # (or cause the conv kernel to overflow short sampling coords) - helper_test_op([(4096,3,3,3), (1,3,3,3)], - lambda x,w: torch.nn.functional.conv2d(x, w), - lambda x,w: x.conv2d(w), atol=1e-3) - - @unittest.skip("slow") - def test_large_ic_conv(self): - # large input channel count can cause OpenCL image to exceed max image width on macOS - helper_test_op([(1,2048,3,3), (1,2048,3,3)], - lambda x,w: torch.nn.functional.conv2d(x, w), - lambda x,w: x.conv2d(w)) - - def test_biased_conv2d(self): - C = 8 - helper_test_op([(1,C,5,5), (C,C,1,1), (C,)], - lambda x,w,b: torch.nn.functional.conv2d(torch.nn.functional.conv2d(x,w,b).relu(),w,b), - lambda x,w,b: Tensor.conv2d(x,w,b).relu().conv2d(w,b)) - - def test_simple_conv2d(self): - helper_test_op([(1,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv2d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - def test_simple_conv2d_bias(self): - helper_test_op([(1,4,9,9), (4,4,3,3), (4,)], - lambda x,w,b: torch.nn.functional.conv2d(x,w,b).relu(), - lambda x,w,b: Tensor.conv2d(x,w,b).relu(), grad_rtol=1e-5) - - @unittest.skipIf(IMAGE>0, "no conv3d on images") - def test_simple_conv3d(self): - helper_test_op([(1,4,9,9,9), (4,4,3,3,3)], - lambda x,w: torch.nn.functional.conv3d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - @unittest.skipIf(IMAGE>0, "no conv3d on images") - def test_padded_conv3d(self): - helper_test_op([(1,4,5,5,5), (4,4,3,3,3)], - lambda x,w: torch.nn.functional.conv3d(x,w,padding=1).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=[1,1,1,1,1,1]).relu(), grad_rtol=1e-5) - - def test_simple_conv2d_m4(self): - helper_test_op([(1,16,18,18), (16,16,3,3)], - lambda x,w: torch.nn.functional.conv2d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - def test_simple_conv2d_1x1(self): - helper_test_op([(1,4,9,9), (4,4,1,1)], - lambda x,w: torch.nn.functional.conv2d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - def test_simple_conv2d_1x1_m4(self): - helper_test_op([(1,16,32,32), (16,16,1,1)], - lambda x,w: torch.nn.functional.conv2d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - def test_nested_conv2d(self): - helper_test_op([(1,32,9,9), (32,32,3,3), (32,32,3,3)], - lambda x,w1,w2: torch.nn.functional.conv2d(torch.nn.functional.conv2d(x,w1).relu(), w2).relu(), - lambda x,w1,w2: x.conv2d(w1).relu().conv2d(w2).relu()) - - # expect reduce nodes == 3 - def test_simple_conv2d_nhwc(self): - # weights (from tf): filter_height x filter_width x in_channels x out_channels - helper_test_op([(2,9,9,10), (3,3,10,20)], - lambda x,w: torch.nn.functional.conv2d(x.permute(0,3,1,2),w.permute(3,2,0,1)).relu(), - lambda x,w: Tensor.conv2d(x.permute(0,3,1,2),w.permute(3,2,0,1)).relu(), atol=1e-5, grad_rtol=1e-5) - - def test_simple_conv2d_batched(self): - helper_test_op([(2,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv2d(x,w).relu(), - lambda x,w: Tensor.conv2d(x,w).relu(), grad_rtol=1e-5) - - # conv transpose - - def test_simple_conv_transpose2d(self): - helper_test_op([(2,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv_transpose2d(x,w).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w).relu(), grad_rtol=1e-5) - - def test_bias_conv_transpose2d(self): - helper_test_op([(2,4,9,9), (4,4,3,3), (4,)], - lambda x,w,b: torch.nn.functional.conv_transpose2d(x,w,b).relu(), - lambda x,w,b: Tensor.conv_transpose2d(x,w,b).relu(), grad_rtol=1e-5) - - def test_grouped_conv_transpose2d(self): - helper_test_op([(2,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv_transpose2d(x,w,groups=2).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w,groups=2).relu(), grad_rtol=1e-5) - - def test_padded_conv_transpose2d(self): - for padding in [(1,2), (2,1), 2, 1, 0]: - helper_test_op([(2,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv_transpose2d(x,w,padding=padding).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w,padding=padding).relu(), grad_rtol=1e-5) - self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w: torch.nn.functional.conv_transpose2d(x,w,padding=(1,1,1)), - lambda x,w: Tensor.conv_transpose2d(x,w,padding=(1,1,1)), expected=(RuntimeError, ValueError)) - - def test_dilated_conv_transpose2d(self): - for dilation in [(1,2), (2,1), 2, 1]: - helper_test_op([(2,4,9,9), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv_transpose2d(x,w,dilation=dilation).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w,dilation=dilation).relu(), grad_rtol=1e-5) - - def test_strided_conv_transpose2d(self): - for stride in [(2,1), (1,2), 1]: - helper_test_op([(2,4,4,5), (4,4,3,3)], - lambda x,w: torch.nn.functional.conv_transpose2d(x,w, stride=stride).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w,stride=stride).relu(), atol=1e-5, grad_rtol=1e-5) - - def test_output_padded_conv_transpose2d(self): - for output_padding, stride in [((1,1), (2,3)), ((2,1), (3,2))]: - helper_test_op([(2,4,6,5), (4,4,3,3),(4,)], - lambda x,w,b: torch.nn.functional.conv_transpose2d(x,w,b,output_padding=output_padding,stride=stride).relu(), - lambda x,w,b: Tensor.conv_transpose2d(x,w,b,output_padding=output_padding,stride=stride).relu(), grad_rtol=1e-5) - - @unittest.skipIf(IMAGE>0, "no conv3d on images") - def test_simple_conv_transpose3d(self): - helper_test_op([(2,4,9,9,9), (4,4,3,3,3)], - lambda x,w: torch.nn.functional.conv_transpose3d(x,w).relu(), - lambda x,w: Tensor.conv_transpose2d(x,w).relu(), grad_rtol=1e-5) - - @unittest.skipIf((IMAGE>0), "no conv1d on images") - def test_conv1d(self): - for bs in [1,8]: - for cin in [1,3]: - for H in [1,2,5]: - for groups in [1,3] if cin == 3 and H == 5 else [1]: - with self.subTest(batch_size=bs, channels=cin, groups=groups, height=H): - helper_test_op([(bs,cin,11), (6,cin//groups,H)], - lambda x,w: torch.nn.functional.conv1d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - @unittest.skipIf(IMAGE>0, "no conv1d on images") - def test_simple_padding_conv1d(self): - bs = 6 - cin = 2 - groups = 1 - H = 5 - p = (1,1) - helper_test_op([(bs,cin,11), (6,cin//groups,H)], - lambda x,w: torch.nn.functional.conv1d(torch.nn.functional.pad(x, p),w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=p).relu()) - - @unittest.skipIf(IMAGE>0, "no conv1d on images") - def test_strided_conv1d_simple(self): - bs, H = 2, 3 - helper_test_op([(bs,1,5), (1,1,H)], - lambda x,w: torch.nn.functional.conv1d(x,w,stride=2).relu(), - lambda x,w: Tensor.conv2d(x,w,stride=2).relu()) - - @unittest.skipIf(IMAGE>0, "no conv1d on images") - def test_asymmetric_padding_conv1d(self): - for p in [(0,1), (2,1), (2,0)]: - with self.subTest(p): - for n in [3,4]: - for k in [2]: - helper_test_op([(1,1,n), (1,1,k)], - lambda x,w: torch.nn.functional.conv1d(torch.nn.functional.pad(x, p),w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=p).relu()) - - def _test_conv2d(self, bs=1, cin=1, cout=6): - for H in [2,3]: - for W in [1,3,5]: - for groups in [1,3] if cin == 3 and cout == 6 and H == 3 and W == 3 else [1]: - with self.subTest(batch_size=bs, channels=cin, groups=groups, height=H, width=W): - helper_test_op([(bs,cin,5,7), (cout,cin//groups,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - def test_conv2d(self): self._test_conv2d(bs=1, cin=3) - def test_conv2d_bs_4_cin_3(self): self._test_conv2d(bs=4, cin=3, cout=2) - def test_conv2d_bs_1_cin_1(self): self._test_conv2d(bs=1, cin=1) - def test_conv2d_bs_4_cin_1(self): self._test_conv2d(bs=4, cin=1) - - def test_conv2d_errors(self): - # kernel size cannot be larger than input size - self.helper_test_exception([(1,1,6,7), (6,1,3,3)], - lambda x,w:torch.nn.functional.conv2d(x,w,dilation=3), - lambda x,w: Tensor.conv2d(x,w,dilation=3), expected=(RuntimeError, AssertionError)) - # regression test for https://github.com/tinygrad/tinygrad/pull/7549/ - self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w:torch.nn.functional.conv2d(x,w), lambda x,w: Tensor.conv2d(x,w), - expected=(RuntimeError, AssertionError)) - self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w:torch.nn.functional.conv2d(x,w,padding=(1,1,1)), - lambda x,w: Tensor.conv2d(x,w,padding=(1,1,1)), expected=(RuntimeError, ValueError)) - - def test_large_input_conv2d(self): - bs = 4 - cin = 16 - groups = 1 - H = 5 - W = 2 - helper_test_op([(bs,cin,64,64), (6,cin//groups,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - # needed to relax tolerance on NVIDIA - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), atol=1e-4, grad_atol=1e-4, grad_rtol=1e-4) - - def test_simple_grouped_conv2d(self): - bs = 1 - groups = 2 - rcout = 1 - cin = 2 - helper_test_op([(bs,groups*cin,1,1), (groups*rcout,cin,1,1)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - def test_medium_grouped_conv2d(self): - bs = 1 - groups = 2 - rcout = 2 - cin = 2 - helper_test_op([(bs,groups*cin,1,1), (groups*rcout,cin,1,1)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - def test_depthwise_conv2d(self): - bs = 1 - groups = 32 - rcout = 1 - cin = 1 - helper_test_op([(bs,groups*cin,32,32), (groups*rcout,cin,1,1)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - def test_grouped_conv2d(self): - bs = 4 - groups = 5 - rcout = 7 - cin = 3 - helper_test_op([(bs,groups*cin,5,5), (groups*rcout,cin,3,3)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - def test_fancy_conv2d(self): - bs = 2 - cin = 3 - cout = 1 - groups = 3 - H,W = 3,3 - helper_test_op([(bs,cin,11,28), (groups*cout,cin//groups,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups).relu(), - lambda x,w: Tensor.conv2d(x,w,groups=groups).relu(), grad_rtol=1e-5) - - def test_strided_conv2d_simple(self): - bs,H,W = 2,3,1 - helper_test_op([(bs,1,5,1), (1,1,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,stride=2).relu(), - lambda x,w: Tensor.conv2d(x,w,stride=2).relu()) - - @unittest.skipIf(Device.DEFAULT != "LLVM", "DEVECTORIZE=0 only for LLVM") - def test_strided_conv2d_simple_vec(self): - with Context(DEVECTORIZE=0): self.test_strided_conv2d_simple() - - def test_strided_conv2d(self): - bs = 4 - cin = 3 - H,W = 3,3 - with self.subTest(stride := 2): - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,stride=2).relu(), - lambda x,w: Tensor.conv2d(x,w,stride=stride).relu()) - with self.subTest(stride := (2,1)): - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,stride=stride).relu(), - lambda x,w: Tensor.conv2d(x,w,stride=(2,1)).relu()) - - def test_negative_padding_conv2d(self): - n,k = 10, 3 - helper_test_op([(1,1,n,n), (1,1,k,k)], - lambda x,w: torch.nn.functional.conv2d(x[:, :, 1:-1, 1:-1],w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=-1).relu()) - helper_test_op([(1,1,n,n), (1,1,k,k)], - lambda x,w: torch.nn.functional.conv2d(x[:, :, 1:, 1:],w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=(-1,0,-1,0)).relu()) - - def test_simple_padding_conv2d(self): - p = (1,1,1,1) - helper_test_op(None, - lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=p).relu(), vals=[[[[[2.,3.]]]], [[[[1.]]]]]) - - def test_asymmetric_padding_conv2d(self): - for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: - with self.subTest(p): - for n in [3,4]: - for k in [2]: - helper_test_op([(1,1,n,n), (1,1,k,k)], - lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=p).relu()) - helper_test_op([(1,1,n,n), (1,1,k,k)], - lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=p).relu()) - - def test_padded_conv2d_p21(self): - bs,cin,H,W,padding = 4, 3, 3, 3, (2,1) - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=padding).relu()) - - def test_padded_conv2d_p22(self): - bs,cin,H,W,padding = 4, 3, 3, 3, (2,2) - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=padding).relu()) - - def test_padded_conv2d_1x1(self): - bs,cin,H,W,padding = 4, 3, 1, 1, 2 - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=padding).relu()) - - def test_padded_conv2d_bs1(self): - bs,cin,H,W,padding = 1, 3, 3, 3, 1 - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding).relu(), - lambda x,w: Tensor.conv2d(x,w,padding=padding).relu()) - - def test_padding_add(self): - helper_test_op([(64,64), (60,60)], - lambda x,w: x+torch.nn.functional.pad(w, (2,2,2,2)), - lambda x,w: x+w.pad((2,2,2,2))) - - def test_dilated_conv2d(self): - bs = 4 - cin = 3 - H,W = 3,3 - for d in [2, (2,1)]: - with self.subTest(dilation := d): - helper_test_op([(bs,cin,11,28), (4,cin,H,W)], - lambda x,w: torch.nn.functional.conv2d(x,w,dilation=dilation).relu(), - lambda x,w: Tensor.conv2d(x,w,dilation=dilation).relu()) - - def test_max_pool2d_simple(self): - ksz = (2,2) - helper_test_op([(1,1,2,3)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz), - lambda x: Tensor.max_pool2d(x, kernel_size=ksz)) - - def test_max_pool2d(self): - for ksz in [(2,2), (3,3), 2, 3, (3,2), (5,5), (5,1)]: - with self.subTest(kernel_size=ksz): - helper_test_op([(32,2,11,28)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz), - lambda x: Tensor.max_pool2d(x, kernel_size=ksz)) - - def test_max_pool2d_padding(self): - for ksz in [(2,2), (3,3), 2, 3, (3,2)]: - for p in [1, (1,0), (0,1)]: - with self.subTest(kernel_size=ksz, padding=p): - helper_test_op([(32,2,11,28)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz, padding=p), - lambda x: Tensor.max_pool2d(x, kernel_size=ksz, padding=p)) - self.helper_test_exception([(32,2,110,28)], lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), - lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), expected=(RuntimeError, ValueError)) - - def test_max_pool2d_asymmetric_padding(self): - shape = (32,2,111,28) - for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: - with self.subTest(padding=p): - helper_test_op([shape], - lambda x: torch.nn.functional.max_pool2d(torch.nn.functional.pad(x, p, value=float("-inf")), kernel_size=(5,5)), - lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), padding=p)) - - def test_max_pool2d_padding_int(self): - ksz = (2,2) - helper_test_op([(32,2,11,28)], - lambda x: torch.nn.functional.max_pool2d(x.int(), kernel_size=ksz, padding=1), - lambda x: Tensor.max_pool2d(x.int(), kernel_size=ksz, padding=1), forward_only=True) - - def test_max_pool2d_bigger_stride(self): - for stride in [(2,3), (3,2), 2, 3]: - with self.subTest(stride=stride): - helper_test_op([(32,2,11,28)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=stride), - lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=stride)) - - def test_max_pool2d_bigger_stride_dilation(self): - for stride, dilation in zip([(2,3), (3,2), 2, 3, 4], [(3,2), (2,3), 2, 3, 6]): - with self.subTest(stride=stride): - helper_test_op([(32,2,11,28)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=stride, dilation=dilation), - lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=stride, dilation=dilation)) - - @unittest.skipIf( Device.DEFAULT in {"CUDA", "NV"}, "CUDA fails on this") - def test_max_pool2d_unit_stride(self): - helper_test_op([(3, 2, 17, 14)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), stride=1), - lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), stride=1)) - - def test_max_pool2d_smaller_stride(self): - for stride in [(2,3), (3,2), 2, 3]: - with self.subTest(stride=stride): - helper_test_op([(3, 2, 17, 14)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), stride=stride), - lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), stride=stride)) - - def test_max_pool2d_dilation(self): - for dilation in [(2, 3), (3, 2), 2, 3]: - helper_test_op([(3, 2, 17, 14)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), dilation=dilation), - lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), dilation=dilation)) - - def test_max_pool2d_ceil_mode(self): - shape = (1,1,6,6) - for ksz in [(3,3), 3, (3,2), 4]: - with self.subTest(kernel_size=ksz): - helper_test_op([shape], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), - lambda x: Tensor.max_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True)) - - def test_max_pool2d_ceil_mode_output_size_reduce_by_one(self): - # sliding window ignored from end region - helper_test_op([(1,1,5,5)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True), - lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True)) - - def test_max_pool2d_return_indices(self): - # batch and multi-channel - helper_test_op([(2,3,6,6)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), return_indices=True)[1], forward_only=True) - # dilation - helper_test_op([(1,1,10,10)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,2), dilation=(2,3), return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(3,2), dilation=(2,3), return_indices=True)[1], forward_only=True) - # padding - helper_test_op([(1,1,5,5)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), padding=1, return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), padding=1, return_indices=True)[1], forward_only=True) - # ceil mode padding - helper_test_op([(1, 1, 7, 7)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2, 2), stride=(2, 2), ceil_mode=True, return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(2, 2), stride=(2, 2), ceil_mode=True, return_indices=True)[1], - forward_only=True) - # global maxpool - helper_test_op([(1,1,12,13)], - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(12, 13), return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(12, 13), return_indices=True)[1], - forward_only=True) - # multiple identical values in same window and overlapping windows - helper_test_op(None, - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), stride=1, return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=1, return_indices=True)[1], - vals=[[[[[1]*6]*6]]], forward_only=True) # Tensor.ones(1,1,6,6) - # overlapping max indices - helper_test_op(None, - lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=1, return_indices=True)[1].type(torch.int32), - lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=1, return_indices=True)[1], - vals=[[[[[1,2]*3]*6]]], forward_only=True) # Tensor([1,2,1,2,1,2]).expand(1,1,6,6) - - def test_max_unpool2d(self): - args = {"kernel_size":(5,5), "stride":(6,5)} - helper_test_op([(8,3,50,50)], - lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, return_indices=True, **args), **args), - lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, return_indices=True, **args), **args), forward_only=True) - args = {"kernel_size":(3,3), "stride":(6,7), "padding":1} - helper_test_op([(8,3,30,30)], - lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, return_indices=True, **args), **args, output_size=(30,30)), - lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, return_indices=True, **args), **args, output_size=(30,30)), forward_only=True) - # batch_size and channel_size of output_size are ignored - helper_test_op([(1,3,7,6)], - lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, kernel_size=(2,2), return_indices=True), - kernel_size=(2,2), output_size=(99,99,7,6)), - lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, kernel_size=(2,2), return_indices=True), - kernel_size=(2,2), output_size=(99,99,7,6)), forward_only=True) - - def test_avg_pool2d(self): - shape = (32,2,111,28) - for ksz in [(2,2), (3,3), (3,2), (5,5), (5,1)]: - with self.subTest(kernel_size=ksz): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz), - lambda x: Tensor.avg_pool2d(x, kernel_size=ksz), rtol=1e-5) - - # regression test for https://github.com/tinygrad/tinygrad/pull/7581 - helper_test_op([(1,1,8,8)], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(1,2), padding=(0,1), stride=(5,1)), - lambda x: Tensor.avg_pool2d(x, kernel_size=(1,2), padding=(0,1), stride=(5,1)), rtol=1e-5) - - def test_avg_pool2d_padding(self): - shape = (32,2,111,28) - for ksz in [(2,2), (3,3), 2, 3, (3,2)]: - for p in [1, (1,0), (0,1)]: - with self.subTest(kernel_size=ksz, padding=p): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=p), - lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=p), rtol=1e-5) - with self.assertRaises(ValueError): - Tensor.avg_pool2d(Tensor.randn((32,2,111,28)), kernel_size=(2,2), padding=(1,1,1)) - - def test_avg_pool2d_asymmetric_padding(self): - shape = (32,2,111,28) - for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: - with self.subTest(padding=p): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(5,5), padding=1), - lambda x: Tensor.avg_pool2d(x, kernel_size=(5,5), padding=1), rtol=1e-5) - self.helper_test_exception([shape], lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), - lambda x: Tensor.avg_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), expected=(RuntimeError, ValueError)) - - def test_avg_pool2d_padding_not_counted(self): - shape = (32,2,111,28) - for ksz in [(2,2), (3,3), 2, 3, (3,2)]: - with self.subTest(kernel_size=ksz): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, count_include_pad=False), - lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, count_include_pad=False), rtol=1e-5) - - def test_avg_pool2d_ceil_mode(self): - shape = (1,1,6,6) - for ksz in [(3,3), 3, (3,2), 4]: - with self.subTest(kernel_size=ksz): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), - lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), rtol=1e-5) - - def test_avg_pool2d_ceil_mode_padding_not_counted(self): - shape = (1,1,6,6) - for ksz in [(3,3), 3, (3,2), 4]: - with self.subTest(kernel_size=ksz): - helper_test_op([shape], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True, count_include_pad=False), - lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True, count_include_pad=False), rtol=1e-5) - - def test_avg_pool2d_ceil_mode_output_size_reduce_by_one(self): - # sliding window ignored from end region - helper_test_op([(1,1,5,5)], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True), - lambda x: Tensor.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True)) - - def test_avg_pool2d_ceil_mode_include_pad_output_size_reduce_by_one(self): - # sliding window ignored from end region - helper_test_op([(1,1,5,5)], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True, count_include_pad=True), - lambda x: Tensor.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True, count_include_pad=True)) - - def test_global_avg_pool2d(self): - helper_test_op([(32,2,111,28)], - lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(111,28)), - lambda x: Tensor.avg_pool2d(x, kernel_size=(111,28)), rtol=1e-5) - - def test_avg_pool3d_failure(self): - with Context(NOOPT=0): - helper_test_op([(1,1,16,16,16)], - lambda x: torch.nn.functional.avg_pool3d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), - lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), rtol=1e-5, forward_only=True) - - def test_avg_pool3d_noopt(self): - with Context(NOOPT=1): - helper_test_op([(1,1,16,16,16)], - lambda x: torch.nn.functional.avg_pool3d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), - lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), rtol=1e-5, forward_only=True) - - def test_interpolate_linear(self): - for in_sz, out_sz in [((52,),(29,)), ((29,),(52,))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="linear"), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear")) - - def test_interpolate_linear_corners_aligned(self): - for in_sz, out_sz in [((52,),(29,)), ((29,),(52,))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="linear", align_corners=True), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True)) - - def test_interpolate_nearest(self, mode="nearest"): - for in_sz, out_sz in [((13,),(9,)), ((9,),(13,))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), - lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) - for in_sz, out_sz in [((13,10),(9,11)), ((13,9),(11,10)), ((9,11),(10,13))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), - lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) - for in_sz, out_sz in [((5,2,8),(3,6,4))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), - lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) - - def test_interpolate_nearest_exact(self): self.test_interpolate_nearest("nearest-exact") - - def test_interpolate_bilinear(self): - for in_sz, out_sz in [((12,20),(9,31)), ((12,9),(31,20)), ((9,31),(20,12))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="bilinear"), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear"), atol=1e-4) - - def test_interpolate_bilinear_corners_aligned(self): - for in_sz, out_sz in [((12,20),(9,31)), ((12,9),(31,20)), ((9,31),(20,12))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="bilinear", align_corners=True), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True), atol=1e-4) - - def test_interpolate_trilinear(self): - for in_sz, out_sz in [((5,2,8),(3,6,4))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="trilinear"), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear"), atol=1e-4) - - def test_interpolate_trilinear_corners_aligned(self): - for in_sz, out_sz in [((5,2,8),(3,6,4))]: - helper_test_op([(2,3)+in_sz], - lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="trilinear", align_corners=True), - lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True), atol=1e-4) - - def test_cat(self): - for dim in range(-2, 3): - helper_test_op([(45,65,9), (45,65,9), (45,65,9)], lambda x,y,z: torch.cat((x,y,z), dim), lambda x,y,z: x.cat(y, z, dim=dim)) - - # zero in non-cat axis - helper_test_op([(45,0,9), (45,0,9), (45,0,9)], lambda x,y,z: torch.cat((x,y,z), 0), lambda x,y,z: x.cat(y, z, dim=0)) - - # zero in cat axis - helper_test_op([(45,0,9), (45,1,9), (45,2,9)], lambda x,y,z: torch.cat((x,y,z), 1), lambda x,y,z: x.cat(y, z, dim=1)) - helper_test_op([(45,0,9), (45,0,9), (45,0,9)], lambda x,y,z: torch.cat((x,y,z), 1), lambda x,y,z: x.cat(y, z, dim=1)) - - with self.assertRaises(IndexError): - a = Tensor(3.14) - a.cat(a) - - def test_multicat(self): - for dim in range(-1, 2): - helper_test_op([(45,65), (45,65), (45,65)], lambda x,y,z: torch.cat((x,y,z), dim), lambda x,y,z: x.cat(y, z, dim=dim)) - - def test_stack(self): - for dim in range(-1, 3): - helper_test_op([(45,65,3), (45,65,3), (45,65,3)], lambda x, y, z: torch.stack((x, y, z), dim), lambda x, y, z: Tensor.stack(x, y, z, dim=dim)) - - with self.assertRaises(IndexError): - Tensor.stack(Tensor.randn(45, 65, 3), dim=77) - - a = Tensor(3.14) - np.testing.assert_allclose(Tensor.stack(a, a).numpy(), Tensor([3.14, 3.14]).numpy()) - - def test_repeat(self): - x = Tensor.randn(4, 6, 3) - base_repeats = [2, 4, 3] - - for reps in [[], [4], [2, 1], [3, 2, 2]]: - repeats = base_repeats + reps - helper_test_op([(4, 6, 3)], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) - helper_test_op([()], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) - - with self.assertRaises(ValueError): - x.repeat((2, 4)) - - np.testing.assert_allclose(x.repeat((2, 0, 4)).numpy(), Tensor.zeros(8, 0, 12).numpy()) - - def test_repeat_interleave(self): - helper_test_op([(3, 3)], lambda x: x.repeat_interleave(6)) - helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, 1)) - helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, 0)) - helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, -1)) - helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, -2)) - - def test_simple_repeat(self): - repeats = [3, 3, 4] - helper_test_op([(3, 3)], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) - - def test_clip(self): - helper_test_op([(45,65)], lambda x: x.clip(-2.3, 1.2)) - helper_test_op([(45,65)], lambda x: x.clip(0, 0)) - helper_test_op([(45,65)], lambda x: x.clip(10, 100)) - helper_test_op([(45,65)], lambda x: x.clip(0, 0.1)) - helper_test_op([(45,65)], lambda x: x.clip(-0.3, -0.2)) - helper_test_op([(45,65)], lambda x: x.clip(3, 0)) # min > max - helper_test_op([(45,65)], lambda x: x.clip(None, 0)) - helper_test_op([(45,65)], lambda x: x.clip(0, None)) - self.helper_test_exception([(45,65)], lambda x: x.clip(None, None), lambda x: x.clip(None, None), RuntimeError) - - def test_matvecmat(self): - helper_test_op([(1,128), (128,128), (128,128)], lambda x,y,z: (x@y).relu()@z) - - def test_matvec(self): - helper_test_op([(1,128), (128,128)], lambda x,y: (x@y).relu()) - - @unittest.skip("this test is broken #862") - def test_max_nan(self): - n = Tensor([1, float("nan")]).max().numpy() - assert math.isnan(n.item()), f"{n.item()} is not nan" - - def test_inf_where(self): - x = Tensor.full((3, 3), float("inf")) - n = (x < 0).where(x, 1).numpy() - assert np.all(n == 1.) - - def _get_index_randoms(self): - # indices cannot have gradient - a = torch.randint(low=-1, high=1, size=(2,1,1,1,1,1), dtype=torch.int64, requires_grad=False) - b = torch.randint(high=1, size=(1,3,1,1,1,1), dtype=torch.int64, requires_grad=False) - c = torch.randint(low=-5, high=5, size=(1,1,4,1,1,1), dtype=torch.int64, requires_grad=False) - d = torch.randint(high=4, size=(2,1,1,5,1,1), dtype=torch.int64, requires_grad=False) - e = torch.randint(high=1, size=(1,1,1,1,6,1), dtype=torch.int64, requires_grad=False) - i, j, k, o, p = [Tensor(tor.detach().cpu().numpy().astype(np.int32), requires_grad=False) for tor in [a,b,c,d,e]] - return a,b,c,d,e,i,j,k,o,p - - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU can only run kernels with up to 10 buffers") - def test_slice_fancy_indexing_no_dim_collapse(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - # no dim collapse from int or dim injection from None - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,d,e], lambda x: x[i,j,k,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[:,b,c,d,:], lambda x: x[:,j,k,o,:]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,...], lambda x: x[i,j,...]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,...,e], lambda x: x[i,...,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[...,c,:,e], lambda x: x[...,k,:,p]) - - def test_slice_fancy_indexing_dim_collapse_int(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - # dim collapse from int - helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,c,d,e], lambda x: x[1,j,k,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,3,d,e], lambda x: x[i,j,3,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,2,d,2], lambda x: x[1,j,2,o,2]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,2,2,2,e], lambda x: x[i,2,2,2,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,:,3:11:2,d,0:2], lambda x: x[1,:,3:11:2,o,0:2]) - - def test_slice_fancy_indexing_dim_inject_none(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - # dim injection from None - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,c,d,e], lambda x: x[None,j,k,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,d,None], lambda x: x[i,j,k,o,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,None,d,e], lambda x: x[i,j,None,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,c,d,None], lambda x: x[None,j,k,o,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,:,None,d,e], lambda x: x[i,:,None,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,None,None,None], lambda x: x[None,None,None,None,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,c,d,e], lambda x: x[None,None,j,k,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,c,None,None], lambda x: x[None,None,j,k,None,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,None,None,c,d,e], lambda x: x[i,None,None,k,o,p]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,None,None,c,None,None], lambda x: x[i,None,None,k,None,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,None,d,e], lambda x: x[None,None,j,None,o,p]) - - def test_slice_fancy_indexing_dim_inject_and_collapse(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() # noqa - # dim injection and collapse - helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,None,d,1], lambda x: x[1,j,None,o,1]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,2,d,None], lambda x: x[None,j,2,o,None]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[...,1,d,None], lambda x: x[...,1,o,None]) - - def test_slice_fancy_indexing_with_tensors(self): - # indexing using idx with different dim - helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,0,0],[0,0,0]]), torch.tensor(1)], - lambda x: x[Tensor([[0,0,0],[0,0,0]]), Tensor(1)]) - helper_test_op([(2,3)], lambda x: x[torch.tensor([1]), torch.tensor([[0,0,0],[0,0,0]])], - lambda x: x[Tensor([1]), Tensor([[0,0,0],[0,0,0]])]) - helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,0,0],[0,0,0]]), torch.tensor([2,1,1])], - lambda x: x[Tensor([[0,0,0],[0,0,0]]), Tensor([2,1,1])]) - helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,1,-1],[-1,-2,0]]), torch.tensor([2,1,-1])], - lambda x: x[Tensor([[0,1,-1],[-1,-2,0]]), Tensor([2,1,-1])]) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU can only run kernels with up to 10 buffers") - def test_slice_fancy_indexing_list_indices(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[[0]]], lambda x: x[[[0]]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[0],b,c,d,:], lambda x: x[[0],j,k,o,:]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[[[0]]],b,c,d,[[1]]], lambda x: x[[[[0]]],j,k,o,[[1]]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[1,0],b,c,d,:], lambda x: x[[1,0],j,k,o,:]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,[1,2,3],...], lambda x: x[i,j,k,[1,2,3],...]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,[[1],[2],[3]],...], lambda x: x[i,j,k,[[1],[2],[3]],...]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,[2,1,0],c,[2,1,0],e], lambda x: x[i,[2,1,0],k,[2,1,0],p]) - - def test_slice_fancy_indexing_tuple_indices(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - helper_test_op([(2,5,6,5,3,4)], lambda x: x[(((0,),),)], lambda x: x[(((0,),),)]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[(0,),b,c,d,:], lambda x: x[(0,),j,k,o,:]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[(1,0),b,c,d,:], lambda x: x[(1,0),j,k,o,:]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,(1,2,3),...], lambda x: x[i,j,k,(1,2,3),...]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,((2,),(1,),(0,)),c,(2,1,0)], lambda x: x[i,((2,),(1,),(0,)),k,(2,1,0)]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,(2,1,0),None,c,(2,1,0),e], lambda x: x[1,(2,1,0),None,k,(2,1,0),p]) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") - def test_slice_fancy_indexing_list_with_tensors(self): - a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a]], lambda x: x[[i]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,1]], lambda x: x[[i,1]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,[1,1]]], lambda x: x[[i,[1,1]]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,(1,1)]], lambda x: x[[i,(1,1)]]) - helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,b,c,d,e]], lambda x: x[[i,j,k,o,p]]) - - def test_slice_fancy_indexing_errors(self): - a = Tensor.ones(10,11,12) - # tensors used as indices must be int tensors - with self.assertRaises(IndexError): a[Tensor(1.1)] - with self.assertRaises(IndexError): a[Tensor([True, True])] - # shape mismatch, cannot broadcast. either exception is okay - with self.assertRaises((IndexError, ValueError)): a[Tensor.randint(3,1,1,1), Tensor.randint(1,4,1,1), Tensor.randint(2,4,4,1)] - with self.assertRaises((IndexError, ValueError)): a[Tensor.randint(3,1,1,1), Tensor.randint(1,4,1,1,1)] - - def test_gather(self): - # indices cannot have gradient - # indices cannot be negative (torch gather) - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=0, index=b), lambda x: x.gather(dim=0, index=a)) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=1, index=b), lambda x: x.gather(dim=1, index=a)) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=2, index=b), lambda x: x.gather(dim=2, index=a)) - helper_test_op([(3,4,5)], lambda x: x.gather(dim=0, index=b), lambda x: x.gather(dim=0, index=a)) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=-1, index=b), lambda x: x.gather(dim=-1, index=a)) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=-2, index=b), lambda x: x.gather(dim=-2, index=a)) - helper_test_op([(4,5,6)], lambda x: x.gather(dim=-3, index=b), lambda x: x.gather(dim=-3, index=a)) - self.helper_test_exception([(4,5,6)], lambda x: x.gather(dim=0, index=torch.tensor([1], dtype=torch.int64)), - lambda x: x.gather(dim=0, index=Tensor([1], dtype=dtypes.int32)), expected=(RuntimeError, AssertionError)) - self.helper_test_exception([(2,1,1)], lambda x: x.gather(dim=0, index=b), - lambda x: x.gather(dim=0, index=a), expected=(RuntimeError, AssertionError)) - helper_test_op(None, lambda x: x.gather(dim=0, index=torch.tensor([2, 1, 0, 1, 2], requires_grad=False)), - lambda x: x.gather(dim=0, index=Tensor([2, 1, 0, 1, 2])), - vals=[[1., 2., 3.]]) - - @unittest.expectedFailure - @unittest.skipIf(torch._C._get_privateuse1_backend_name() == "tiny", 'results in a success instead of a failure') - def test_gather_failure(self): - # gather with inf values do not work, other values results in nan - helper_test_op(None, lambda x: x.gather(dim=0, index=torch.tensor([2, 1, 0, 1, 2], requires_grad=False)), - lambda x: x.gather(dim=0, index=Tensor([2, 1, 0, 1, 2])), - vals=[[-float("inf"), 2., 3.]]) - - def test_scatter(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - for dim in (0,1,2,-1,-2,-3): - helper_test_op([(4,5,6), (4,5,6)], lambda x,src: x.scatter(dim=dim, index=b, src=src), - lambda x,src: x.scatter(dim=dim, index=a, src=src), forward_only=True) - - helper_test_op([(3,4,5), (3,4,5)], lambda x,src: x.scatter(dim=1, index=b, src=src), - lambda x,src: x.scatter(dim=1, index=a, src=src), forward_only=True) - helper_test_op([(10,3,10), (10,10,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), - lambda x,src: x.scatter(dim=1, index=a, src=src), forward_only=True) - - self.helper_test_exception([(2,3,10), (10,10,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), - lambda x,src: x.scatter(dim=1, index=a, src=src), expected=(RuntimeError, AssertionError)) - self.helper_test_exception([(10,3,10), (10,3,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), - lambda x,src: x.scatter(dim=1, index=a, src=src), expected=(RuntimeError, AssertionError)) - self.helper_test_exception([(3,4,5), (3,4,5)], lambda x,src: x.scatter(dim=1, index=b, src=src, mode="typo"), - lambda x,src: x.scatter(dim=1, index=a, src=src, mode="typo"), expected=TypeError) - self.helper_test_exception([(3,4,5), (3,4,5)], lambda x,src: x.half().scatter(dim=1, index=b, src=src), - lambda x,src: x.half().scatter(dim=1, index=a, src=src), expected=RuntimeError) - - helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=3), lambda x: x.scatter(dim=1, index=a, src=3), forward_only=True) - helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf")), - lambda x: x.scatter(dim=1, index=a, src=float("inf")), forward_only=True) - - # overlapping indices with 0s - b = torch.tensor([0,0], requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - helper_test_op(None, - lambda x,src: x.scatter(0, b, src), - lambda x,src: x.scatter(0, a, src), forward_only=True, - vals=[[1.,2.,3.,4.], [1.,0.]]) - - def test_scatter_add(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf"), reduce="add"), - lambda x: x.scatter(dim=1, index=a, src=float("inf"), reduce="add"), forward_only=True) - - # TODO: fails for webgpu - if Device.DEFAULT != "WEBGPU": - helper_test_op([(4,5,6)], - lambda x: x.scatter(1, b, float("nan"), reduce="add"), - lambda x: x.scatter(1, a, float("nan"), reduce="add"), forward_only=True) - - def test_scatter_mul(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf"), reduce="multiply"), - lambda x: x.scatter(dim=1, index=a, src=float("inf"), reduce="multiply"), forward_only=True) - - # TODO: fails for webgpu - if Device.DEFAULT != "WEBGPU": - helper_test_op([(4,5,6)], - lambda x: x.scatter(1, b, float("nan"), reduce="multiply"), - lambda x: x.scatter(1, a, float("nan"), reduce="multiply"), forward_only=True) - - def test_scatter_no_reduce_tensor_src(self): - with self.assertRaises(TypeError): - Tensor.ones(4).scatter(dim=1, index=Tensor([0]), src=Tensor.ones(4), reduce="add") - - def test_scatter_reduce(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - for reduce in ("sum", "prod", "mean", "amin", "amax"): - for dim in (-1,1,-3): - helper_test_op([(4,5,6), (4,5,6)], - lambda x,src: x.scatter_reduce(dim=dim, index=b, src=src, reduce=reduce), - lambda x,src: x.scatter_reduce(dim=dim, index=a, src=src, reduce=reduce), forward_only=True) - helper_test_op([(4,5,6), (4,5,6)], - lambda x,src: x.scatter_reduce(dim=dim, index=b, src=src, reduce=reduce, include_self=False), - lambda x,src: x.scatter_reduce(dim=dim, index=a, src=src, reduce=reduce, include_self=False), forward_only=True) - - def test_scatter_reduce_prod_zeros(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - x = Tensor.zeros([4,5,6]).float() - y = torch.zeros([4,5,6]).float() - helper_test_op([(4,5,6)], - lambda src: y.scatter_reduce(dim=1, index=b, src=src, reduce="prod"), - lambda src: x.scatter_reduce(dim=1, index=a, src=src, reduce="prod"), forward_only=True) - - def test_scatter_reduce_errors(self): - b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) - a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) - # invalid reduce arg - self.helper_test_exception([(4,5,6), (4,5,6)], - lambda x,src: x.scatter_reduce(dim=0, index=b, src=src, reduce="INVALID"), - lambda x,src: x.scatter_reduce(dim=0, index=a, src=src, reduce="INVALID"), - RuntimeError) - # dtype mismatch - self.helper_test_exception([(4,5,6), (4,5,6)], - lambda x,src: x.half().scatter_reduce(dim=0, index=b, src=src, reduce="sum"), - lambda x,src: x.half().scatter_reduce(dim=0, index=a, src=src, reduce="sum"), - RuntimeError) - - def test_scaled_dot_product_attention(self): - helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64)], torch.nn.functional.scaled_dot_product_attention, Tensor.scaled_dot_product_attention) - helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64), (32,8,16,16)], - lambda x,y,z,m: torch.nn.functional.scaled_dot_product_attention(x,y,z,attn_mask=m), - lambda x,y,z,m: Tensor.scaled_dot_product_attention(x,y,z,attn_mask=m)) - - def test_scaled_dot_product_attention_mismatch_ls(self): - helper_test_op([(32,8,4,64), (32,8,16,64), (32,8,16,64)], torch.nn.functional.scaled_dot_product_attention, Tensor.scaled_dot_product_attention) - - def test_scaled_dot_product_attention_causal(self): - helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64)], - lambda x,y,z: torch.nn.functional.scaled_dot_product_attention(x,y,z,is_causal=True), - lambda x,y,z: Tensor.scaled_dot_product_attention(x,y,z,is_causal=True)) - - self.helper_test_exception([(32,8,16,64), (32,8,16,64), (32,8,16,64), (32,8,16,16)], - lambda x,y,z,m: torch.nn.functional.scaled_dot_product_attention(x,y,z,is_causal=True,attn_mask=m), - lambda x,y,z,m: Tensor.scaled_dot_product_attention(x,y,z,is_causal=True,attn_mask=m), - expected=RuntimeError) - - def test_binary_crossentropy(self): - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(),torch.clip(y,0,1)), - lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1))) - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x,torch.clip(y,0,1)), - lambda x,y: x.binary_crossentropy_logits(y.clip(0,1))) - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x,torch.clip(y,0,1)), - lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1))) - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(),torch.clip(y,0,1)), - lambda x,y: x.binary_crossentropy_logits(y.clip(0,1))) - def test_binary_crossentropy_reductions(self): - for r in ("mean", "sum", "none"): - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(), torch.clip(y,0,1), reduction=r), - lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1), reduction=r)) - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x, torch.clip(y,0,1), reduction=r), - lambda x,y: x.binary_crossentropy_logits(y.clip(0,1), reduction=r)) - def test_cross_entropy(self): - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y), - lambda x,y: x.cross_entropy(y)) - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, torch.argmax(y, dim=1)), - lambda x,y: x.cross_entropy(y.argmax(axis=1)), forward_only=True) - def test_cross_entropy_reductions(self): - for r in ("mean", "sum", "none"): - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, reduction=r), - lambda x,y: x.cross_entropy(y, reduction=r)) - self.helper_test_exception([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, reduction="typo"), - lambda x,y: x.cross_entropy(y, reduction="typo"), expected=ValueError) - - def test_cross_entropy_smoothing(self): - for ls in (0., 0.3, 0.7, 1.): - helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, label_smoothing=ls), - lambda x,y: x.cross_entropy(y, label_smoothing=ls)) - - def test_nll_loss(self): - helper_test_op([(32,10), (32)], - lambda x,y: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.clip(y,0).type(torch.long)), - lambda x,y: x.log_softmax(axis=1).nll_loss(y.clip(0).cast(dtypes.int32)), forward_only=True) - - def test_nll_loss_3d(self): - helper_test_op([(32,10,3,3,3), (32,3,3,3)], - lambda x,y: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.clip(y,0).type(torch.long)), - lambda x,y: x.log_softmax(axis=1).nll_loss(y.clip(0).cast(dtypes.int32)), forward_only=True) - - def test_nll_loss_reductions(self): - for r in ("mean", "sum", "none"): - helper_test_op([(32,10), (32)], - lambda x,y: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.clip(y,0).type(torch.long), reduction=r), - lambda x,y: x.log_softmax(axis=1).nll_loss(y.clip(0).cast(dtypes.int32), reduction=r), forward_only=True) - self.helper_test_exception([(32,10), (32)], - lambda x,y: torch.nn.functional.nll_loss(x, torch.clip(y,0).type(torch.long), reduction="typo"), - lambda x,y: x.nll_loss(y.clip(0).cast(dtypes.int32), reduction="typo"), expected=ValueError) - - def test_nll_loss_weight(self): - for r in ("mean", "sum", "none"): - helper_test_op([(32,10), (32), (10)], - lambda x,y,z: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.clip(y,0).type(torch.long), - weight=z, reduction=r), - lambda x,y,z: x.log_softmax(axis=1).nll_loss(y.clip(0).cast(dtypes.int32), weight=z, reduction=r), forward_only=True) - - def test_nll_loss_3d_weight(self): - for r in ("mean", "sum", "none"): - helper_test_op([(32,10,3,3,3), (32,3,3,3), (10)], - lambda x,y,z: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.clip(y,0).type(torch.long), - weight=z, reduction=r), - lambda x,y,z: x.log_softmax(axis=1).nll_loss(y.clip(0).cast(dtypes.int32), weight=z, reduction=r), forward_only=True) - - def test_nll_loss_ignore_index(self): - logits = [[2.0, 0.5, -1.0], - [1.5, 2.5, -0.5], - [0.0, -2.0, 1.0]] - targets = [0, 1, 2] - helper_test_op(None, lambda x,y: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), - torch.clip(y,0).type(torch.long), ignore_index=1), - lambda x,y: x.log_softmax().nll_loss(y.clip(0), ignore_index=1), - forward_only=True, vals=[logits, targets]) - - def test_one_hot(self): - data = [1, 2, 4] - helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data), 6).type(torch.int32), - lambda: Tensor(data).one_hot(6), forward_only=True) - helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data)).type(torch.int32), - lambda: Tensor(data).one_hot(), forward_only=True) - data = [[[1, 2, 3], [0, 3, 5]], [[1, 2, 3], [0, 3, 5]]] - helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data), 8).type(torch.int32), - lambda: Tensor(data).one_hot(8), forward_only=True) - helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data)).type(torch.int32), - lambda: Tensor(data).one_hot(), forward_only=True) - - def test_masked_fill(self): - helper_test_op([(32,10)], lambda x: x.masked_fill((x>0.1).detach(), -math.inf)) - helper_test_op([(32,10)], lambda x: x.masked_fill((x<0.1).detach(), -math.inf)) - - def test_masked_select(self): - helper_test_op([(32, 10)], lambda x: x.masked_select(x>0.5), lambda x: x.masked_select(x>0.5), forward_only=True) - helper_test_op([(32, 10)], lambda x: x.masked_select(torch.tensor(True)), lambda x: x.masked_select(Tensor(True)), forward_only=True) - - @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") - def test_cast(self): - helper_test_op([(3, 3)], lambda x: x.float()) - helper_test_op(None, lambda x: x.float(), vals=[[0, 1, 2, 3]], forward_only=True) - helper_test_op(None, lambda x: x.float(), vals=[[True, False]], forward_only=True) - helper_test_op([(3, 3)], lambda x: x.int(), forward_only=True) - helper_test_op([(3, 3)], lambda x: x.bool(), forward_only=True) - - def test_bitcast(self): - helper_test_op([(3, 3)], lambda x: x.view(torch.int32), lambda x: x.bitcast(dtypes.int32), forward_only=True) - -@unittest.skipUnless(is_dtype_supported(dtypes.uchar), f"no uint8 on {Device.DEFAULT}") -class TestOpsUint8(unittest.TestCase): - def test_cast(self): - helper_test_op([(2,3,64,64)], lambda x: x.type(torch.uint8), lambda x: x.cast('uint8'), forward_only=True) - - def test_cast_relu(self): - helper_test_op([(2,3,64,64)], lambda x: x.relu().type(torch.uint8), lambda x: x.relu().cast('uint8'), forward_only=True) - - def test_interpolate_bilinear(self): - out_sz = (10, 10) - helper_test_op([(2,3,64,64)], - lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="bilinear"), - lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="linear"), forward_only=True) - - def test_interpolate_nearest(self): - out_sz = (10, 10) - helper_test_op([(2,3,64,64)], - lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="nearest"), - lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="nearest"), forward_only=True) - - def test_interpolate_nearest_exact(self): - out_sz = (10, 10) - helper_test_op([(2,3,64,64)], - lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="nearest-exact"), - lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="nearest-exact"), forward_only=True) - - def test_min(self): - helper_test_op(None, - lambda x: x.type(torch.uint8).min(), - lambda x: x.cast(dtypes.uint8).min(), forward_only=True, vals=[[[0, 1, 2], [3, 4, 5]]]) - helper_test_op(None, - lambda x: x.type(torch.uint8).min(), - lambda x: x.cast(dtypes.uint8).min(), forward_only=True, vals=[[0, 128, 255, 64, 32, 16]]) - -@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), f"no bfloat16 on {Device.DEFAULT}") -class TestOpsBFloat16(unittest.TestCase): - def test_cast(self): - # TODO: helper_test_op breaks in unrelated part - # TODO: wrong output with GPU=1 / PYTHON=1 on mac - data = [60000.0, 70000.0, 80000.0] - np.testing.assert_allclose(Tensor(data).cast("bfloat16").numpy(), torch.tensor(data).type(torch.bfloat16).float().numpy()) - -if __name__ == '__main__': - np.random.seed(1337) - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_opt_gemm.py b/tinygrad/test/test_opt_gemm.py deleted file mode 100644 index 862d9778..00000000 --- a/tinygrad/test/test_opt_gemm.py +++ /dev/null @@ -1,45 +0,0 @@ -import numpy as np -import unittest -from tinygrad import Tensor -from tinygrad.helpers import get_single_element -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad.engine.realize import CompiledRunner, ExecItem - -class TestOptGemm(unittest.TestCase): - @classmethod - def setUpClass(cls): - N = 64 - cls.a = Tensor.randn(N, N).contiguous().realize() - cls.b = Tensor.randn(N, N).contiguous().realize() - cls.res = cls.a.T.numpy() @ cls.b.T.numpy() - - def _test_gemm_unrolled_permute_l(self, opts=[]): - t = self.a.T @ self.b.T - # TODO: this should be a generic test helper - si = get_single_element(t.schedule()) - k = Kernel(si.ast) - k.apply_opts(opts) - run = CompiledRunner(k.to_program()) - ExecItem(run, si.bufs).run() - test = si.bufs[0].numpy().reshape(self.res.shape) - np.testing.assert_allclose(self.res, test, atol=1e-4) - - def test_gemm_unrolled_permute_l_44(self): - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4)] - self._test_gemm_unrolled_permute_l(opts) - - def test_gemm_unrolled_permute_l_424(self): - # was failing with LLVM - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=4)] - self._test_gemm_unrolled_permute_l(opts) - - def test_gemm_unrolled_permute_l_42(self): - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2)] - self._test_gemm_unrolled_permute_l(opts) - - def test_gemm_unrolled_permute_l_22(self): - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2)] - self._test_gemm_unrolled_permute_l(opts) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_optim.py b/tinygrad/test/test_optim.py deleted file mode 100644 index 283378e7..00000000 --- a/tinygrad/test/test_optim.py +++ /dev/null @@ -1,136 +0,0 @@ -import numpy as np -import torch -import unittest -from tinygrad import Tensor, Device, dtypes -from tinygrad.nn.optim import Adam, SGD, AdamW -from tinygrad.helpers import CI -from tinygrad.device import is_dtype_supported - -np.random.seed(1337) -x_init = np.random.randn(1,4).astype(np.float32) -W_init = np.random.randn(4,4).astype(np.float32) -m_init = np.random.randn(1,4).astype(np.float32) - -class TeenyNet: - def __init__(self, tensor): - self.x = tensor(x_init.copy(), requires_grad=True) - self.W = tensor(W_init.copy(), requires_grad=True) - def forward(self): - return (self.x * self.W).sum() - -class TinyNet: - def __init__(self, tensor): - self.x = tensor(x_init.copy(), requires_grad=True) - self.W = tensor(W_init.copy(), requires_grad=True) - self.m = tensor(m_init.copy()) - - def forward(self): - out = self.x.matmul(self.W).relu() - # print(out.detach().numpy()) - out = out.log_softmax(1) - out = out.mul(self.m).add(self.m).sum() - return out - -def step(tensor, optim, steps=1, teeny=False, **kwargs): - net = TeenyNet(tensor) if teeny else TinyNet(tensor) - optim = optim([net.x, net.W], **kwargs) - for _ in range(steps): - out = net.forward() - optim.zero_grad() - out.backward() - optim.step() - return net.x.detach().numpy(), net.W.detach().numpy() - -@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") -class TestOptim(unittest.TestCase): - def setUp(self): - self.old_training = Tensor.training - Tensor.training = True - def tearDown(self): - Tensor.training = self.old_training - - def _test_optim(self, tinygrad_optim, torch_optim, steps, opts, atol, rtol): - for x,y in zip(step(Tensor, tinygrad_optim, steps, **opts), - step(torch.tensor, torch_optim, steps, **opts)): - np.testing.assert_allclose(x, y, atol=atol, rtol=rtol) - - def _test_sgd(self, steps, opts, atol, rtol): self._test_optim(SGD, torch.optim.SGD, steps, opts, atol, rtol) - def _test_adam(self, steps, opts, atol, rtol): self._test_optim(Adam, torch.optim.Adam, steps, opts, atol, rtol) - def _test_adamw(self, steps, opts, atol, rtol): self._test_optim(AdamW, torch.optim.AdamW, steps, opts, atol, rtol) - - def test_multistep_sgd_high_lr_teeny(self): self._test_sgd(2, {'lr': 1.1, 'teeny': True}, 1e-6, 1e-5) - def test_multistep_adam_high_lr_teeny(self): self._test_adam(2, {'lr': 1.1, 'teeny': True}, 2e-4, 5e-4) - - def test_sgd(self): self._test_sgd(1, {'lr': 0.001}, 1e-6, 0) - def test_sgd_high_lr(self): self._test_sgd(1, {'lr': 10}, 1e-6, 1e-5) - def test_sgd_wd(self): self._test_sgd(1, {'lr': 0.001, 'weight_decay': 0.1}, 1e-6, 0) - def test_sgd_high_lr_wd(self): self._test_sgd(1, {'lr': 10, 'weight_decay': 0.1}, 1e-6, 1e-5) - - def test_multistep_sgd(self): self._test_sgd(10, {'lr': 0.001}, 1e-6, 0) - def test_multistep_sgd_high_lr(self): self._test_sgd(10, {'lr': 10}, 1e-6, 3e-4) - def test_multistep_sgd_wd(self): self._test_sgd(10, {'lr': 0.001, 'weight_decay': 0.1}, 1e-6, 0) - def test_multistep_sgd_high_lr_wd(self): self._test_sgd(10, {'lr': 9, 'weight_decay': 0.1}, 1e-6, 3e-4) - - def test_multistep_sgd_momentum(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9}, 1e-6, 0) - def test_multistep_sgd_high_lr_momentum(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9}, 1e-5, 3e-4) - def test_multistep_sgd_momentum_wd(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'weight_decay': 0.1}, 1e-6, 0) - def test_multistep_sgd_high_lr_momentum_wd(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9, 'weight_decay': 0.1}, 1e-5, 3e-4) - - def test_multistep_sgd_nesterov_momentum(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'nesterov': True}, 1e-5, 0) - def test_multistep_sgd_high_lr_nesterov_momentum(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9, 'nesterov': True}, 1e-5, 3e-4) - def test_multistep_sgd_nesterov_momentum_wd(self): - self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'nesterov': True, 'weight_decay': 0.1}, 1e-5, 0) - def test_multistep_sgd_high_lr_nesterov_momentum_wd(self): - self._test_sgd(10, {'lr': 9, 'momentum': 0.9, 'nesterov': True, 'weight_decay': 0.1}, 1e-5, 3e-4) - - def test_adam(self): self._test_adam(1, {'lr': 0.001}, 1e-5, 0) - def test_adam_high_lr(self): self._test_adam(1, {'lr': 10}, 1e-4, 1e-4) - def test_adamw(self): self._test_adamw(1, {'lr': 0.001}, 1e-5, 0) - def test_adamw_high_lr(self): self._test_adamw(1, {'lr': 10}, 1e-4, 1e-4) - - def test_multistep_adam(self): self._test_adam(10, {'lr': 0.001}, 1e-5, 0) - def test_multistep_adam_high_lr(self): self._test_adam(10, {'lr': 10}, 2e-3, 5e-4) - - def test_multistep_adamw(self): self._test_adamw(10, {'lr': 0.001}, 1e-5, 0) - def test_multistep_adamw_high_lr(self): self._test_adamw(10, {'lr': 10}, 5e-4, 2e-3) - - def test_duped_weights(self): - for Opt in [Adam, AdamW, SGD]: - losses = [] - for i in range(2): - w = Tensor(x_init.copy()) - opt = Opt([w], lr=0.1) if i == 0 else Opt([w, w], lr=0.1) - - loss = None - for _ in range(3): - loss = w.sum() - opt.zero_grad() - loss.backward() - opt.step() - losses.append(loss.numpy()) - - np.testing.assert_allclose(losses[0], losses[1], atol=1e-4, rtol=0) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_mixed_precision(self): - old_default_float, dtypes.default_float = dtypes.default_float, dtypes.half - # weight update would overflow without upcasting - self._test_sgd(10, {'lr': 1e10}, 1e-6, 3e-4) - self._test_adam(1, {'lr': 1e10}, 1e-4, 1e-4) - self._test_adamw(1, {'lr': 1e10}, 1e-4, 1e-4) - dtypes.default_float = old_default_float - - def test_assert_tensor_train(self): - t = Tensor.ones((1,1), requires_grad=True) - optimizer = Adam([t]) - optimizer.zero_grad() - old_state = Tensor.training - t.sum().backward() - Tensor.training = False - self.assertRaises(RuntimeError, optimizer.step) - Tensor.training = True - optimizer.step() - Tensor.training = old_state - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_pickle.py b/tinygrad/test/test_pickle.py deleted file mode 100644 index 93758eef..00000000 --- a/tinygrad/test/test_pickle.py +++ /dev/null @@ -1,174 +0,0 @@ -import unittest, pickle, types -import numpy as np -from tinygrad import Tensor, TinyJit, Variable, dtypes -from tinygrad.helpers import GlobalCounters, ContextVar, Context -from tinygrad.uop.ops import PatternMatcher, UPat, UOp, Ops - -class TestPickle(unittest.TestCase): - def test_pickle_code_object(self): - y = lambda x: x*2 # noqa: E731 - code_str = pickle.dumps(y.__code__) - fxn = types.FunctionType(pickle.loads(code_str), globals()) - self.assertEqual(fxn(2), 4) - - def test_pickle_pattern_matcher(self): - pm = PatternMatcher([(UPat.cvar('x'), lambda x: x*2)]) - sink = UOp.const(dtypes.int, 2) - tt = pm.rewrite(sink) - pm_str = pickle.dumps(pm) - pm2 = pickle.loads(pm_str) - self.assertEqual(pm2.rewrite(sink).key, tt.key) - - def test_pickle_main_pattern_matcher(self): - from tinygrad.codegen.devectorizer import sym - ssym = pickle.dumps(sym) - dsym = pickle.loads(ssym) - self.assertEqual(dsym.patterns[0][0].location, sym.patterns[0][0].location) - - def test_pickle_realized_tensor(self): - print("** init") - t = Tensor.rand(10, 10).realize() - st = pickle.dumps(t) - t_values = t.numpy() - del t # free buffers - print("** post pickle") - init = GlobalCounters.kernel_count - t2:Tensor = pickle.loads(st) - np.testing.assert_equal(t_values, t2.numpy()) - # expect at most one COPY kernel - self.assertLessEqual(GlobalCounters.kernel_count-init, 1) - - def test_pickle_realized_tensor_alt(self): - print("** init") - t = Tensor.rand(10, 10).to("CPU").realize() - st = pickle.dumps(t) - t_values = t.numpy() - del t # free buffers - print("** post pickle") - init = GlobalCounters.kernel_count - t2:Tensor = pickle.loads(st) - np.testing.assert_equal(t_values, t2.numpy()) - self.assertEqual(GlobalCounters.kernel_count-init, 0) - - def test_pickle_realized_tensor_alt2(self): - print("** init") - t = Tensor.rand(10, 10).to("CPU").realize() - tensor_uop = t.uop - assert tensor_uop.is_realized, f"expected {tensor_uop} to be realized" - t_values = t.numpy() - # pickle - st = pickle.dumps(t) - # free buffers - del t - del tensor_uop - print("** post pickle") - t2:Tensor = pickle.loads(st) - assert t2.uop.is_realized, f"expected {t2.uop} to be realized" - np.testing.assert_equal(t_values, t2.numpy()) - - # NOTE: currently Buffer exists on the uop, not tensor - def test_pickle_buffer_uop(self): - t = Tensor.arange(4).realize() - a = t.uop - assert a.op is Ops.BUFFER - self.assertIsNotNone(buffer:=a.realized) - s = pickle.dumps(a) - # free buffers - del a - del buffer - a2:UOp = pickle.loads(s) - self.assertListEqual(a2.realized.as_buffer().cast("I").tolist(), [0, 1, 2, 3]) - - def test_pickle_unrealized_tensor(self): - t = Tensor.ones(10, 10) - st = pickle.dumps(t) - t2:Tensor = pickle.loads(st) - np.testing.assert_equal(t.numpy(), t2.numpy()) - - def test_pickle_variable(self): - v = Variable("i", 1, 20).bind(10) - t1 = Tensor.ones(10, v).contiguous() - t2 = Tensor.ones(10, v).contiguous() - ret = (t1+t2).sum(1) - st = pickle.dumps(ret) - del ret - vt2 = pickle.loads(st) - np.testing.assert_equal(vt2.numpy(), 20) - - def test_pickle_buffer_view(self): - t = Tensor.arange(10, device="CPU").contiguous().realize() - vt = t[3:5].contiguous().realize() - assert hasattr(vt.uop.buffer, 'base') - ref_value = vt.tolist() - st = pickle.dumps(vt) - del t, vt - vt2 = pickle.loads(st) - assert hasattr(vt2.uop.buffer, 'base') - assert ref_value == vt2.tolist() - - def test_pickle_numpy(self): - t = Tensor(np.array([1,2,3,4.]), dtype=dtypes.float32) - st = pickle.dumps(t) - t2:Tensor = pickle.loads(st) - np.testing.assert_equal(t.numpy(), t2.numpy()) - - def test_pickle_jit(self): - @TinyJit - def add(a, b): return a.sum()+b+1 - for _ in range(3): add(Tensor.rand(10, 10), Tensor.rand(10, 10)) - st = pickle.dumps(add) - del add - - add_fxn = pickle.loads(st) - x = Tensor.ones(10, 10).contiguous().realize() - y = Tensor.ones(10, 10).contiguous().realize() - print("post jit") - out = add_fxn(x, y) - np.testing.assert_equal(out.numpy(), 102) - - def test_pickle_context_var(self): - v = ContextVar("test_var", 0) - with Context(test_var=1): - vs = pickle.dumps(v) - v2 = pickle.loads(vs) - self.assertEqual(v2.value, 1) - - def test_pickle_schedule(self): - a = Tensor([1,2]) - out = a + 2 - sched = out.schedule() - pk = pickle.dumps(sched) - sched_pk = pickle.loads(pk) - self.assertEqual(sched_pk[-1].ast, sched[-1].ast) - - def test_pickle_renderer(self): - from tinygrad.device import Device - pk = pickle.dumps(Device.default.renderer) - pickle.loads(pk) - -class TestPickleJIT(unittest.TestCase): - @classmethod - def setUpClass(cls): - N = 10 - @TinyJit - def add(a, b): return a.sum()+b+1 - for _ in range(3): add(Tensor.rand(N, N), Tensor.rand(N, N)) - cls.st = pickle.dumps(add) - del add - - def test_inspect(self): - import io - class FakeClass: - def __init__(self, *args, **kwargs): - print(self.module, self.name) - class InspectUnpickler(pickle.Unpickler): - def find_class(self, module, name): return type("SpecializedFakeClass", (FakeClass,), {"name": name, "module": module}) - InspectUnpickler(io.BytesIO(self.st)).load() - - @unittest.skip("we are still saving intermediate buffers") - def test_size(self): - # confirm no intermediate buffers are saved - self.assertLess(len(self.st), 1_000_000) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_profiler.py b/tinygrad/test/test_profiler.py deleted file mode 100644 index c64c2711..00000000 --- a/tinygrad/test/test_profiler.py +++ /dev/null @@ -1,163 +0,0 @@ -import unittest, struct, contextlib, statistics -from tinygrad import Device, Tensor, dtypes, TinyJit -from tinygrad.helpers import CI, getenv, Context -from tinygrad.device import Buffer, BufferSpec, Compiled, ProfileRangeEvent, ProfileDeviceEvent, ProfileGraphEvent -from tinygrad.runtime.support.hcq import HCQCompiled -from tinygrad.engine.realize import get_runner - -MOCKGPU = getenv("MOCKGPU") - -@contextlib.contextmanager -def helper_collect_profile(*devs): - for dev in devs: dev.synchronize() - Compiled.profile_events = [x for x in Compiled.profile_events if isinstance(x, ProfileDeviceEvent) and x.device.startswith("METAL")] - - profile_list = [] - with Context(PROFILE=1): - yield profile_list - for dev in devs: dev.synchronize() - for dev in devs: dev._at_profile_finalize() - for x in Compiled.profile_events: profile_list.append(x) - -def helper_profile_filter_device(profile, device:str): - assert any(getattr(x, "device", None) == device and isinstance(x, ProfileDeviceEvent) for x in profile), f"device {device} is not registred" - dev_events = [x for x in profile if getattr(x, "device", None) == device and isinstance(x, ProfileDeviceEvent)] - assert len(dev_events) == 1, "only one device registration event is expected" - return [x for x in profile if getattr(x, "device", None) == device], dev_events[0] - -@unittest.skipUnless(issubclass(type(Device[Device.DEFAULT]), HCQCompiled) or Device.DEFAULT in {"METAL"}, "HCQ device required to run") -class TestProfiler(unittest.TestCase): - @classmethod - def setUpClass(self): - TestProfiler.d0 = Device[Device.DEFAULT] - - TestProfiler.a = Tensor([0.,1.], device=Device.DEFAULT).realize() - TestProfiler.b = self.a + 1 - si = self.b.schedule()[-1] - - TestProfiler.runner = get_runner(TestProfiler.d0.device, si.ast) - TestProfiler.b.uop.buffer.allocate() - - def test_profile_kernel_run(self): - runner_name = TestProfiler.runner._prg.name - with helper_collect_profile(TestProfiler.d0) as profile: - TestProfiler.runner([TestProfiler.b.uop.buffer, TestProfiler.a.uop.buffer], var_vals={}) - - profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - kernel_runs = [x for x in profile if isinstance(x, ProfileRangeEvent)] - assert len(kernel_runs) == 1, "one kernel run is expected" - assert kernel_runs[0].name == runner_name, "kernel name is not correct" - assert not kernel_runs[0].is_copy, "kernel should not be copy" - - def test_profile_copyin(self): - buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() - - with helper_collect_profile(TestProfiler.d0) as profile: - buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - - profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - kernel_runs = [x for x in profile if isinstance(x, ProfileRangeEvent)] - assert len(kernel_runs) == 1, "one kernel run is expected" - assert kernel_runs[0].is_copy, "kernel should be copy" - - def test_profile_multiops(self): - runner_name = TestProfiler.runner._prg.name - buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() - - with helper_collect_profile(TestProfiler.d0) as profile: - buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - TestProfiler.runner([buf1, TestProfiler.a.uop.buffer], var_vals={}) - buf1.copyout(memoryview(bytearray(buf1.nbytes))) - - profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - evs = [x for x in profile if isinstance(x, ProfileRangeEvent)] - - assert len(evs) == 3, "3 kernel runs are expected" - assert evs[0].is_copy, "kernel should be copy" - assert evs[1].name == runner_name, "kernel name is not correct" - assert not evs[1].is_copy, "kernel should not be copy" - assert evs[2].is_copy, "kernel should be copy" - - for i in range(1, 3): - assert evs[i].st > evs[i-1].en, "timestamp not aranged" - - def test_profile_multidev(self): - d1 = Device[f"{Device.DEFAULT}:1"] - buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() - buf2 = Buffer(f"{Device.DEFAULT}:1", 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() - - with helper_collect_profile(TestProfiler.d0, d1) as profile: - buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - buf2.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) - - profile0, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - profile1, _ = helper_profile_filter_device(profile, d1.device) - - for p in [profile0, profile1]: - evs = [x for x in p if isinstance(x, ProfileRangeEvent)] - assert len(evs) == 1, "one kernel runs are expected" - assert evs[0].is_copy, "kernel should be copy" - - def test_profile_multidev_transfer(self): - d1 = Device[f"{Device.DEFAULT}:1"] - - buf1 = Tensor.randn(10, 10, device=f"{Device.DEFAULT}:0").realize() - with helper_collect_profile(TestProfiler.d0, d1) as profile: - buf1.to(f"{Device.DEFAULT}:1").realize() - - profile0, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - kernel_runs = [x for x in profile0 if isinstance(x, ProfileRangeEvent)] - assert len(kernel_runs) == 1, "one kernel run is expected" - assert kernel_runs[0].is_copy, "kernel should be copy" - - @unittest.skipIf(Device.DEFAULT in "METAL" or (MOCKGPU and Device.DEFAULT == "AMD"), "AMD mockgpu does not support queue wait interrupts") - def test_profile_graph(self): - d1 = Device[f"{Device.DEFAULT}:1"] - - def f(a): - x = (a + 1).realize() - return x, x.to(d1.device).realize() - - a = Tensor.randn(10, 10, device=TestProfiler.d0.device).realize() - with helper_collect_profile(TestProfiler.d0, d1) as profile: - jf = TinyJit(f) - for _ in range(3): jf(a) - del jf - - graph_evs = [x for x in profile if isinstance(x, ProfileGraphEvent)] - - _, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) - _, _ = helper_profile_filter_device(profile, d1.device) - - assert len(graph_evs) == 1, "one graph event is expected" - assert len(graph_evs[0].ents) == 2, "two entities are expected" - - @unittest.skipIf(CI or not issubclass(type(Device[Device.DEFAULT]), HCQCompiled), "skip CI") - def test_dev_jitter_matrix(self): - dev_cnt = 6 - devs = [Device[f"{Device.DEFAULT}:{i}"] for i in range(dev_cnt)] - for dev in devs: dev.synchronize() - for dev in devs: dev._at_profile_finalize() - - def _sync_d2d(d1:HCQCompiled, d2:HCQCompiled): - d1.hw_compute_queue_t().signal(d1.timeline_signal, d1.timeline_value).wait(d2.timeline_signal, d2.timeline_value) \ - .timestamp(d1.timeline_signal).signal(d1.timeline_signal, d1.timeline_value+1).submit(d1) - d2.hw_compute_queue_t().signal(d2.timeline_signal, d2.timeline_value).wait(d1.timeline_signal, d1.timeline_value) \ - .timestamp(d2.timeline_signal).signal(d2.timeline_signal, d2.timeline_value+1).submit(d2) - d1.timeline_value += 2 - d2.timeline_value += 2 - d1.timeline_signal.wait(d1.timeline_value - 1) - d2.timeline_signal.wait(d2.timeline_value - 1) - return d2.timeline_signal.timestamp - d1.timeline_signal.timestamp - - # then test it by timing the GPU to GPU times - jitter_matrix = [[float('nan')] * len(devs) for _ in range(len(devs))] - pairs = [(p1, p2) for p1 in enumerate(devs) for p2 in enumerate(devs) if p1 != p2] - for (i1, d1), (i2, d2) in pairs: - cpu_diff = d1.gpu2cpu_compute_time_diff - d2.gpu2cpu_compute_time_diff - jitter_matrix[i1][i2] = statistics.median(_sync_d2d(d1, d2) - _sync_d2d(d2, d1) for _ in range(20)) / 2 - cpu_diff - assert abs(jitter_matrix[i1][i2]) < 0.5, "jitter should be less than 0.5ms" - print("pairwise clock jitter matrix (us):\n" + '\n'.join([''.join([f'{float(item):8.3f}' for item in row]) for row in jitter_matrix])) - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/test_quantize_onnx.py b/tinygrad/test/test_quantize_onnx.py deleted file mode 100644 index 7626aad8..00000000 --- a/tinygrad/test/test_quantize_onnx.py +++ /dev/null @@ -1,368 +0,0 @@ -# ruff: noqa: E501 -import numpy as np -import unittest -from dataclasses import replace -from tinygrad import Tensor, Context, Device, dtypes -from tinygrad.uop.ops import Ops, UOp # noqa: F401 # pylint: disable=unused-import -from tinygrad.codegen.kernel import Kernel, Opt, OptOps -from tinygrad.engine.realize import CompiledRunner, ExecItem, lower_schedule_item -from tinygrad.engine.search import bufs_from_lin -from tinygrad.shape.shapetracker import ShapeTracker, View # noqa: F401 # pylint: disable=unused-import - -N = 512 - -def create_gemm_model(model_path:str, batch_size=N, in_size=N, out_size=N, bias=False): - import onnx - from onnx import helper, numpy_helper, TensorProto - # Define input and output - input_tensor = helper.make_tensor_value_info("input", TensorProto.FLOAT, [batch_size, in_size]) - output_tensor = helper.make_tensor_value_info("output", TensorProto.FLOAT, [batch_size, out_size]) - - # Create random weights and bias - W_data = np.random.randn(in_size, out_size).astype(np.float32) - W_init = numpy_helper.from_array(W_data, name="W") - - if bias: - B_data = np.random.randn(out_size).astype(np.float32) - B_init = numpy_helper.from_array(B_data, name="B") - gemm_node = helper.make_node("Gemm", inputs=["input", "W", "B"], outputs=["output"], alpha=1.0, beta=1.0, transB=0) - graph_def = helper.make_graph([gemm_node], "SingleGemmGraph", [input_tensor], [output_tensor], initializer=[W_init, B_init]) - else: - gemm_node = helper.make_node("Gemm", inputs=["input", "W"], outputs=["output"], alpha=1.0, beta=1.0, transB=0) - graph_def = helper.make_graph([gemm_node], "SingleGemmGraph", [input_tensor], [output_tensor], initializer=[W_init]) - - # Create and save the model - model_def = helper.make_model(graph_def, producer_name="single_gemm_example") - onnx.save_model(model_def, model_path) - return model_path - -def sexec(out:Tensor, opts:list[Opt], replace_src=None, run_count=3): - si = out.schedule()[-1] - k = Kernel(si.ast, opts=Device[Device.DEFAULT].renderer) - #opts = [Opt(op=OptOps.UPCAST, axis=0, arg=128)] #, Opt(op=OptOps.UNROLL, axis=0, arg=4)] - k.apply_opts(opts) - prg = k.to_program() - if replace_src is not None: - old_name = prg.src.split("__attribute__((noinline)) void ")[1].split("(")[0] - prg = replace(prg, src=replace_src + "/* DSP boilerplate */" + prg.src.split("/* DSP boilerplate */")[1].replace(old_name, "fxn")) - ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) - for _ in range(run_count): ei.run(wait=True) - -def get_quantized_model(sz): - from onnxruntime.quantization import quantize_static, QuantFormat, QuantType, CalibrationDataReader - class FakeDataReader(CalibrationDataReader): - def __init__(self): self.cnt = 0 - def get_next(self) -> dict: - self.cnt += 1 - if self.cnt == 100: return None - return {"input": np.random.uniform(size=(sz, sz)).astype(np.float32)} - out_file = "/tmp/test_out.onnx" - quantize_static(create_gemm_model("/tmp/test_in.onnx", sz, sz, sz), out_file, - FakeDataReader(), quant_format=QuantFormat.QDQ, per_channel=False, reduce_range=False, - activation_type=QuantType.QUInt8, weight_type=QuantType.QInt8, - extra_options={"ActivationSymmetric": False}) - return out_file - -@unittest.skipIf(Device.DEFAULT != "CPU", "only tests for CPU") -class TestQuantizeOnnxCPU(unittest.TestCase): - def test_quant_128(self, sz=128): - try: - import onnx # noqa: F401 # pylint: disable=unused-import - except ImportError: - raise unittest.SkipTest() - from tinygrad.frontend.onnx import OnnxRunner, onnx_load - out_file = get_quantized_model(sz) - onnx_model = onnx_load(out_file) - run_onnx = OnnxRunner(onnx_model) - inp = Tensor(np.random.uniform(size=(sz, sz)).astype(np.float32)) - with Context(DONT_REALIZE_EXPAND=1, QUANTIZE=1): - sched = run_onnx({"input":inp})["output"].schedule() - ei = lower_schedule_item(sched[-2]) - daccs = [u for u in ei.prg.p.uops if u.op is Ops.DEFINE_ACC] - assert all(u.dtype.scalar() is dtypes.int for u in daccs) - -@unittest.skipIf(Device.DEFAULT != "DSP", "only tests for DSP") -class TestQuantizeOnnx(unittest.TestCase): - def test_quant_128(self): self.test_quant(128) - def test_quant(self, sz=512): - from examples.benchmark_onnx import load_onnx_model - # divide is ~1500-2000 without reduce_range, 750-900 with it - out_file = get_quantized_model(sz) - run_onnx_jit, _ = load_onnx_model(out_file) - with Context(DONT_REALIZE_EXPAND=1): - run_onnx_jit(input=Tensor(np.random.uniform(size=(sz, sz)).astype(np.float32))) - - def test_prequant_conv2d_1x1(self): - X = Tensor(np.random.uniform(0, 255, size=(1, 32, 128, 128)).astype(np.uint8)) - W = Tensor(np.random.uniform(0, 255, size=(64, 32, 1, 1)).astype(np.uint8)) - out = X.conv2d(W, dtype=X.dtype) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - sexec(out, opts) - - def test_prequant_gemm(self): - N = 512 - X = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)) - W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)) - out = X.matmul(W, dtype=X.dtype) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - sexec(out, opts) - - # TODO: this has to work - def test_prequant_gemm_intacc_early(self, xi=np.int8, wi=np.int8): - N = 512 - X = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(xi)) - W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(wi)) - with Context(DONT_REALIZE_EXPAND=1): - # this divide is interesting and forces the accumulator to actually be an int - out = (X.cast("int").matmul(W.cast("int"))//1000).cast("int8") - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - sexec(out, opts) - - def test_prequant_gemm_handcode(self): - src = """typedef int int128 __attribute__((aligned(512),vector_size(512))); - typedef int int32 __attribute__((aligned(128),vector_size(128))); - typedef int int64 __attribute__((aligned(256),vector_size(256))); - typedef unsigned char unsigned_char4 __attribute__((aligned(4),vector_size(4))); - typedef signed char signed_char128 __attribute__((aligned(128),vector_size(128))); - typedef unsigned char unsigned_char128 __attribute__((aligned(128),vector_size(128))); - typedef unsigned char unsigned_char256 __attribute__((aligned(256),vector_size(256))); - union V256 { - unsigned_char256 vec256; - struct { - unsigned_char128 lo128; - unsigned_char128 hi128; - }; - }; - __attribute__((noinline)) void fxn(unsigned char* restrict __attribute__((align_value(128))) data0, - unsigned char* restrict __attribute__((align_value(128))) data1, - signed char* restrict __attribute__((align_value(128))) data2) { - for (int ridx0 = 0; ridx0 < 512; ridx0++) { - int alu0 = (ridx0<<9); - for (int ridx1 = 0; ridx1 < 4; ridx1++) { - int alu1 = (ridx1<<7); - int32 acc0 = __builtin_HEXAGON_V6_vd0_128B(); - int32 acc1 = __builtin_HEXAGON_V6_vd0_128B(); - int32 acc2 = __builtin_HEXAGON_V6_vd0_128B(); - int32 acc3 = __builtin_HEXAGON_V6_vd0_128B(); - - for (int ridx2 = 0; ridx2 < 128; ridx2++) { - unsigned_char4 val0 = *((unsigned_char4*)((data1+(alu0+(ridx2<<2))))); - int alu2 = (alu1+(ridx2<<11)); - signed_char128 x0 = *((signed_char128*)((data2+alu2))); - signed_char128 x1 = *((signed_char128*)((data2+(alu2+512)))); - signed_char128 x2 = *((signed_char128*)((data2+(alu2+1024)))); - signed_char128 x3 = *((signed_char128*)((data2+(alu2+1536)))); - - union V256 ss01; - // ss01.lo128 = (x0[0], x1[0], x0[2], x1[2], x0[4], x1[4], ...) - // ss01.hi128 = (x0[1], x1[1], x0[3], x1[3], x0[5], x1[5], ...) - ss01.vec256 = __builtin_HEXAGON_V6_vshufoeb_128B(x1, x0); - - union V256 ss23; - // ss23.lo128 = (x2[0], x3[0], x2[2], x3[2], x2[4], x3[4], ...) - // ss23.hi128 = (x2[1], x3[1], x2[3], x3[3], x2[5], x3[5], ...) - ss23.vec256 = __builtin_HEXAGON_V6_vshufoeb_128B(x3, x2); - - union V256 sslo; - // sslo.lo128 = (x0[0], x1[0], x2[0], x3[0], x0[4], x1[4], ...) - // sslo.hi128 = (x0[2], x1[2], x2[2], x3[2], x0[6], x1[6], ...) - sslo.vec256 = __builtin_HEXAGON_V6_vdealvdd_128B(ss23.lo128, ss01.lo128, 2); - - union V256 sshi; - // sshi.lo128 = (x0[1], x1[1], x2[1], x3[1], x0[5], x1[5], ...) - // sshi.hi128 = (x0[3], x1[3], x2[3], x3[3], x0[7], x1[7], ...) - sshi.vec256 = __builtin_HEXAGON_V6_vdealvdd_128B(ss23.hi128, ss01.hi128, 2); - - //unsigned_char128 w0 = (unsigned_char128){val0[0],val0[1],val0[2],val0[3],val0[0],val0[1],val0[2],val0[3],... - unsigned_char128 w0 = __builtin_HEXAGON_V6_lvsplatw_128B(*((unsigned int*)&val0)); - - acc0 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc0, w0, sslo.lo128); - acc1 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc1, w0, sshi.lo128); - acc2 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc2, w0, sslo.hi128); - acc3 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc3, w0, sshi.hi128); - } - acc0 /= 1000; - acc1 /= 1000; - acc2 /= 1000; - acc3 /= 1000; - // ','.join([f"acc{j}[{i}]" for i in range(32) for j in range(4)]) - // acc0[0], acc0[1], acc0[2], ..... acc3[30], acc3[31] - unsigned_char128 packed = __builtin_HEXAGON_V6_vpackhub_sat_128B(__builtin_HEXAGON_V6_vpackwh_sat_128B(acc3, acc2), - __builtin_HEXAGON_V6_vpackwh_sat_128B(acc1, acc0)); - packed = __builtin_HEXAGON_V6_vshuffb_128B(packed); - packed = __builtin_HEXAGON_V6_vshuffb_128B(packed); - // acc0[0], acc1[0], acc2[0], ..... acc2[31], acc3[31] - *((unsigned_char128*)((data0+(alu0+alu1)))) = packed; - } - } - }""" - self.test_prequant_gemm_intacc(np.uint8, np.int8, src) - - def test_prequant_gemm_intacc_32(self): - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] - self.test_prequant_gemm_intacc(np.uint8, np.int8, N=32, opts=opts) - def test_prequant_gemm_intacc_128(self): self.test_prequant_gemm_intacc(np.uint8, np.int8, N=128) - def test_prequant_gemm_intacc_256(self): self.test_prequant_gemm_intacc(np.uint8, np.int8, N=256) - def test_prequant_gemm_intacc(self, xi=np.uint8, wi=np.uint8, replace_src=None, N=512, clip=True, opts=None): - X = Tensor(m1:=(np.random.uniform(0, 255, size=(N,N)).astype(xi))).realize() - W = Tensor(m2:=(np.random.uniform(0, 255, size=(N,N)).astype(wi))).realize() - # ugh, it's so broken with those casts. need DONT_REALIZE_EXPAND=1 python3 test/test_quantize_onnx.py TestQuantizeOnnx.test_prequant - tg_dtype = dtypes.int8 if xi == np.int8 else dtypes.uint8 - with Context(DONT_REALIZE_EXPAND=1): - out = (X.int().matmul(W.int())//1000) - if clip: out = out.clip(dtypes.min(tg_dtype),dtypes.max(tg_dtype)) - out = out.cast(tg_dtype) - opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] if opts is None else opts - sexec(out, opts, replace_src, run_count=1) - tout = out.numpy() - mout = ((m1.astype(np.int32) @ m2.astype(np.int32)) // 1000) - if clip: mout = mout.clip(dtypes.min(tg_dtype),dtypes.max(tg_dtype)) - mout = mout.astype(xi) - print(tout) - print(mout) - np.testing.assert_equal(tout, mout) - - def test_prequant_gemm_intacc_wi(self): self.test_prequant_gemm_intacc(wi=np.int8) - def test_prequant_gemm_intacc_xiwi(self): self.test_prequant_gemm_intacc(xi=np.int8, wi=np.int8) - def test_prequant_gemm_intacc_xiwi_noclip(self): self.test_prequant_gemm_intacc(xi=np.int8, wi=np.int8, clip=False) - - def test_prequant_gemv(self): - N = 2048 - # ugh, it's so broken with those casts. need DONT_REALIZE_EXPAND=1 python3 test/test_quantize_onnx.py TestQuantizeOnnx.test_prequant - X = Tensor(np.random.uniform(0, 255, size=(1,N)).astype(np.uint8)).realize() - W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)).realize() - #out = X.cast(dtypes.int) @ W.cast(dtypes.int) - #out = X @ W - out = X.matmul(W, dtype=X.dtype) - opts = [Opt(op=OptOps.UPCAST, axis=0, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] - sexec(out, opts) - -@unittest.skipIf(Device.DEFAULT != "DSP", "only tests for DSP") -class TestDSPCache(unittest.TestCase): - def test_cache_speed(self): - # string becuase this breaks Python language server for syntax highlight for some reason - ast = eval("""UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(25088), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 896, 32, 1, 0), offset=0, mask=None, contiguous=True),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(25088), arg=0, src=()),)), - UOp(Ops.CAST, dtypes.uchar, arg=None, src=( - UOp(Ops.XOR, dtypes.int, arg=None, src=( - UOp(Ops.MAX, dtypes.int, arg=None, src=( - UOp(Ops.XOR, dtypes.int, arg=None, src=( - UOp(Ops.MAX, dtypes.int, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( - UOp(Ops.VIEW, dtypes.uchar.ptr(150528), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 192), strides=(0, 5376, 192, 0, 1), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(150528), arg=1, src=()),)),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.012368360534310341, src=( - x22:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 192), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.int, arg=None, src=( - UOp(Ops.LOAD, dtypes.char, arg=None, src=( - UOp(Ops.VIEW, dtypes.char.ptr(6144), arg=ShapeTracker(views=(View(shape=(32, 48, 4), strides=(4, 128, 1), offset=0, mask=None, contiguous=False), View(shape=(1, 28, 28, 32, 192), strides=(0, 0, 0, 192, 1), offset=0, mask=None, contiguous=False))), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.char.ptr(6144), arg=2, src=()),)),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=0.007441135589033365, src=( - x22,)),)),)),)), - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.CAST, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.int, arg=None, src=( - UOp(Ops.VIEW, dtypes.int.ptr(32), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( - UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(32), arg=3, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=9.203465015161783e-05, src=( - x36:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=33.812857328652136, src=( - x36,)),)), - UOp(Ops.CONST, dtypes.float, arg=0.4999999, src=( - x36,)),)), - UOp(Ops.CONST, dtypes.float, arg=136.0, src=( - x36,)),)),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=( - x36,)),)), - x41:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( - x36,)),)), - UOp(Ops.CONST, dtypes.int, arg=-256, src=( - x36,)),)), - x41,)),)),)),))""") - opts = [Opt(op=OptOps.UNROLL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4)] - with Context(DEVECTORIZE=0, QUANTIZE=1): - k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) - k.apply_opts(opts) - prg = k.to_program() - #print(prg.src) - - new_src = """ -typedef int int32 __attribute__((aligned(128),vector_size(128))); -typedef signed char signed_char128 __attribute__((aligned(128),vector_size(128))); -typedef unsigned char unsigned_char8 __attribute__((aligned(8),vector_size(8))); -typedef unsigned char unsigned_char4 __attribute__((aligned(4),vector_size(4))); -typedef unsigned char unsigned_char128 __attribute__((aligned(128),vector_size(128))); -__attribute__((noinline)) void r_196_24_8_32_4(unsigned char* restrict __attribute__((align_value(128))) data0, unsigned char* restrict __attribute__((align_value(128))) data1, signed char* restrict __attribute__((align_value( -128))) data2, int* restrict __attribute__((align_value(128))) data3) { - int32 cast0 = (int32){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - int32 val0 = *((int32*)((data3+0))); - for (int ridx0 = 0; ridx0 < 196; ridx0++) { - int32 acc0 = cast0; - int32 acc1 = cast0; - int32 acc2 = cast0; - int32 acc3 = cast0; - __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768); - __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+192); - __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+384); - __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+576); - for (int ridx1 = 0; ridx1 < 24; ridx1++) { - signed_char128 val1 = *((signed_char128*)((data2+(ridx1<<8)))); - signed_char128 val2 = *((signed_char128*)((data2+((1+(ridx1<<1))<<7)))); - - int alu0 = ((ridx0*768)+(ridx1<<3)); - - unsigned_char8 val3 = *((unsigned_char8*)((data1+alu0))); - __builtin_HEXAGON_Y2_dcfetch(((data1+alu0)+16)); - unsigned_char8 val4 = *((unsigned_char8*)((data1+(alu0+192)))); - __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+192))+16)); - unsigned_char8 val5 = *((unsigned_char8*)((data1+(alu0+384)))); - __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+384))+16)); - unsigned_char8 val6 = *((unsigned_char8*)((data1+(alu0+576)))); - __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+576))+16)); - - unsigned_char4 alu5 = __builtin_shufflevector(val3, val3, 0, 1, 2, 3); - unsigned_char4 alu6 = __builtin_shufflevector(val4, val4, 0, 1, 2, 3); - unsigned_char4 alu7 = __builtin_shufflevector(val5, val5, 0, 1, 2, 3); - unsigned_char4 alu8 = __builtin_shufflevector(val6, val6, 0, 1, 2, 3); - acc0 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc0, val1, (*((unsigned int*)&alu5))); - acc1 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc1, val1, (*((unsigned int*)&alu6))); - acc2 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc2, val1, (*((unsigned int*)&alu7))); - acc3 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc3, val1, (*((unsigned int*)&alu8))); - - unsigned_char4 alu9 = __builtin_shufflevector(val3, val3, 4, 5, 6, 7); - unsigned_char4 alu10 = __builtin_shufflevector(val4, val4, 4, 5, 6, 7); - unsigned_char4 alu11 = __builtin_shufflevector(val5, val5, 4, 5, 6, 7); - unsigned_char4 alu12 = __builtin_shufflevector(val6, val6, 4, 5, 6, 7); - acc0 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc0, val2, (*((unsigned int*)&alu9))); - acc1 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc1, val2, (*((unsigned int*)&alu10))); - acc2 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc2, val2, (*((unsigned int*)&alu11))); - acc3 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc3, val2, (*((unsigned int*)&alu12))); - } - unsigned_char128 alu18 = __builtin_HEXAGON_V6_vpackhub_sat_128B(__builtin_HEXAGON_V6_vpackwh_sat_128B((((((acc3+val0)*203)+32767)/65536)+136), (((((acc2+val0)*203)+32767)/65536)+136)), __builtin_HEXAGON_V6_vpackwh_sat_128B((((((acc1+val0)*203)+32767)/65536)+136), (((((acc0+val0)*203)+32767)/65536)+136))); - *((unsigned_char128*)((data0+(ridx0<<7)))) = alu18; - } -} -""" - prg = replace(prg, src=new_src+prg.src.split("/* DSP boilerplate */ ")[1]) - rt = CompiledRunner(prg) - #Device.default.compiler.disassemble(rt.lib) - ei = ExecItem(rt, bufs_from_lin(k)) - tm = ei.run(wait=True) - print(f"final time {tm*1e6:.2f} us") - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_randomness.py b/tinygrad/test/test_randomness.py deleted file mode 100644 index 435778ef..00000000 --- a/tinygrad/test/test_randomness.py +++ /dev/null @@ -1,360 +0,0 @@ -import unittest, math -from functools import partial - -import numpy as np -import torch -from tinygrad import nn, dtypes, Tensor, Device, TinyJit -from tinygrad.helpers import getenv, CI -from tinygrad.device import is_dtype_supported -from tinygrad.engine.realize import lower_schedule, CompiledRunner -from hypothesis import given, settings, strategies as strat -from test.helpers import not_support_multi_device - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") - -# https://gist.github.com/devries/11405101 -def ksprob(a): - fac, total, termbf = 2.0, 0.0, 0.0 - a2 = -2.0 * a * a - for j in range(1, 101): - term = fac * math.exp(a2 * j * j) - total += term - if math.fabs(term) <= 0.001 * termbf or math.fabs(term) <= 1e-8 * total: - return total - fac = -fac - termbf = math.fabs(term) - return 1.0 - -def kstest(l1, l2): - n1, n2 = len(l1), len(l2) - l1.sort() - l2.sort() - j1, j2, d, fn1, fn2 = 0, 0, 0.0, 0.0, 0.0 - while j1 < n1 and j2 < n2: - d1, d2 = l1[j1], l2[j2] - if d1 <= d2: - fn1 = (float(j1) + 1.0) / float(n1) - j1 += 1 - if d2 <= d1: - fn2 = (float(j2) + 1.0) / float(n2) - j2 += 1 - dtemp = math.fabs(fn2 - fn1) - if dtemp > d: - d = dtemp - ne = float(n1 * n2) / float(n1 + n2) - nesq = math.sqrt(ne) - prob = ksprob((nesq + 0.12 + 0.11 / nesq) * d) - return prob - -def equal_distribution(tiny_func, torch_func=None, numpy_func=None, shape=(40, 43), alpha=0.04): - Tensor.manual_seed(1337) - torch.manual_seed(1337) - np.random.seed(1337) - assert not (torch_func is None and numpy_func is None), "no function to compare with" - x1 = tiny_func(*shape).numpy().flatten() - x2 = tiny_func(shape).numpy().flatten() - if numpy_func is not None: y = numpy_func(shape).flatten() - if torch_func is not None: z = torch_func(shape).numpy().flatten() - return (numpy_func is None or (kstest(x1, y) >= alpha and kstest(x2, y) >= alpha)) and \ - (torch_func is None or (kstest(x1, z) >= alpha and kstest(x2, z) >= alpha)) - -def normal_test(func, shape=(20, 23), alpha=0.05): return equal_distribution(func, numpy_func=lambda x: np.random.randn(*x), shape=shape, alpha=alpha) - -class TestRandomness(unittest.TestCase): - def test_rand(self): - self.assertFalse(normal_test(Tensor.rand)) - self.assertTrue(equal_distribution(Tensor.rand, torch.rand, lambda x: np.random.rand(*x))) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16) and is_dtype_supported(dtypes.ulong), "need float16 and ulong support") - def test_rand_float16(self): - N = 128 - x = Tensor.rand((2, N, N), dtype=dtypes.float16) - assert x.dtype == dtypes.float16 - nx = x.numpy() - # seed dependant, check output range is [0, 1) - assert nx[nx == 1].size == 0 - assert nx[nx == 0].size > 0 - equal_distribution(lambda *x: Tensor.rand(*x, dtype=dtypes.float16), torch.rand, lambda x: np.random.rand(*x), shape=(2, N, N)) - - @unittest.skipIf(CI and Device.DEFAULT in {"NV", "CUDA"}, "gpuocelot doesn't support certain ops needed for threefry") - def test_threefry_against_reference(self): - Tensor.manual_seed(1337) - - # reference generated using - """ - key0 = 1337 - key1 = 0 - values = jax.extend.random.threefry_2x32((np.uint32(key1), np.uint32(key0)), np.arange(20, dtype=np.uint32)) - print(f"[{', '.join(f'{v}' for v in values)}]") - """ - jr = np.array([2221762175, 1752107825, 653745012, 1967534793, 1395205442, 3840423848, 2159346757, - 603508235, 3319473678, 3363866483, 3544324138, 1436466838, 2169858556, 2570072943, - 2387150698, 3678370550, 2911697663, 403244401, 2560861638, 1692360114]) - - counts = Tensor.arange(20, dtype=dtypes.uint32) - counts0, counts1 = counts.chunk(2) - r = Tensor._threefry_random_bits(Tensor([0, 1337], dtype='uint32'), counts0, counts1).numpy() - - np.testing.assert_allclose(jr, r) - - @unittest.skipIf(getenv("PTX"), "fails with PTX") - def test_threefry_doesnt_use_long(self): - for (_,ei) in lower_schedule(Tensor.rand(20).schedule()): - if isinstance(ei.prg, CompiledRunner): - for u in ei.prg.p.uops: - self.assertNotIn(u.dtype, {dtypes.long, dtypes.ulong}, msg=f"long found in {ei.prg.p.name}") - - def test_threefry_against_reference_full(self): - Tensor.manual_seed(1337) - - # reference generated using - """ - key0 = 1337 - key1 = int.from_bytes(hashlib.sha256(int(0).to_bytes(4)).digest(), "big") & 0xffffffff - values = jax.extend.random.threefry_2x32((np.uint32(key1), np.uint32(key0)), np.arange(20, dtype=np.uint32)) - values = (values >> (32 - 23)) | np.array(1, dtype=np.float32).view(np.uint32) - values = values.view(np.float32) - 1 - print(f"[{', '.join(f'{v}' for v in values)}]") - """ - jr = np.array([0.9073467254638672, 0.8235964775085449, 0.6872662305831909, 0.9920015335083008, 0.4941047430038452, - 0.3108327388763428, 0.09639489650726318, 0.004686474800109863, 0.8435229063034058, 0.824237585067749, - 0.5873836278915405, 0.4232727289199829, 0.2530076503753662, 0.40300023555755615, 0.03966474533081055, - 0.27904558181762695, 0.9150195121765137, 0.48057758808135986, 0.23821306228637695, 0.7676635980606079], dtype=np.float32) - r = Tensor.rand(20).numpy() - np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) - - # next 20, np.arange(20, 40, dtype=np.uint32) - jr = np.array([0.7444133758544922, 0.7713677883148193, 0.8233780860900879, 0.43871235847473145, 0.517757773399353, - 0.6437174081802368, 0.967403769493103, 0.26167726516723633, 0.6825339794158936, 0.14966607093811035, - 0.28920769691467285, 0.017063498497009277, 0.2627382278442383, 0.9525482654571533, 0.9351049661636353, - 0.43904995918273926, 0.043945908546447754, 0.6616791486740112, 0.6667773723602295, 0.5228077173233032], dtype=np.float32) - r = Tensor.rand(20).numpy() - np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) - - # next 10, np.arange(40, 50, dtype=np.uint32) - jr = np.array([0.9614430665969849, 0.059279561042785645, 0.01909029483795166, 0.47882091999053955, 0.9677121639251709, - 0.36863112449645996, 0.3102607727050781, 0.06608951091766357, 0.35329878330230713, 0.26518797874450684], dtype=np.float32) - r = Tensor.rand(10).numpy() - np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_threefry_tensors_cnt(self): - Tensor.manual_seed(1337) - - Tensor.rand(20).realize() - - assert len(Tensor._device_rng_counters) == 1 - assert len(Tensor._device_seeds) == 1 - - Tensor.rand(20, device=f"{Device.DEFAULT}:1").realize() - - assert len(Tensor._device_rng_counters) == 2 - assert len(Tensor._device_seeds) == 2 - - Tensor.manual_seed(2) - - assert len(Tensor._device_rng_counters) == 0 - assert len(Tensor._device_seeds) == 0 - - @unittest.skipIf(not_support_multi_device(), "no multi") - def test_threefry_same_kernels(self): - Tensor.manual_seed(0) - - Tensor.rand(1).realize() - - s = Tensor.rand(20).schedule() - s2 = Tensor.rand(20).schedule() - - assert len(s) == len(s2), f"{len(s)} != {len(s2)}" - for x,y in zip(s, s2): - if not (x.ast == y.ast): - print(f"{x.ast} != {y.ast}") - - Tensor.rand(1, device=f"{Device.DEFAULT}:1").realize() - - s3 = Tensor.rand(20, device=f"{Device.DEFAULT}:1").schedule() - s4 = Tensor.rand(20, device=f"{Device.DEFAULT}:1").schedule() - - assert len(s3) == len(s4), f"{len(s3)} != {len(s4)}" - assert len(s2) == len(s4), f"{len(s)} != {len(s3)}" - for x,y in zip(s3, s4): - if not (x.ast == y.ast): - print(f"{x.ast} != {y.ast}") - - @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "need bfloat16 support") - def test_rand_bfloat16(self): - N = 128 - x = Tensor.rand((2, N, N), dtype=dtypes.bfloat16) - assert x.dtype == dtypes.bfloat16 - nx = x.numpy() - assert nx[nx == 1].size == 0 - assert nx[nx == 0].size > 0 - equal_distribution(lambda *x: Tensor.rand(*x, dtype=dtypes.bfloat16).float(), torch.rand, lambda x: np.random.rand(*x), shape=(2, N, N)) - - def test_rand_like(self): - empty = Tensor.empty((80, 44)) - rand = Tensor.rand_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - def test_randn_like(self): - empty = Tensor.empty((80, 44)) - rand = Tensor.randn_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - def test_rand_like_zero_shape(self): - empty = Tensor.empty(0, 20) - rand = Tensor.rand_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - def test_rand_like_more_dims(self): - empty = Tensor.empty((1, 2, 3, 4, 5, 6)) - rand = Tensor.rand_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - def test_rand_like_dtype(self): - empty = Tensor.empty((80, 44), dtype=dtypes.float16) - rand = Tensor.rand_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - empty = Tensor.empty((80, 44)) - rand = Tensor.rand_like(empty, dtype=dtypes.float16) - assert rand.shape == empty.shape - assert rand.dtype == dtypes.float16 - assert rand.device == empty.device - - def test_randn_like_dtype(self): - empty = Tensor.empty((80, 44), dtype=dtypes.float16) - rand = Tensor.randn_like(empty) - assert rand.shape == empty.shape - assert rand.dtype == empty.dtype - assert rand.device == empty.device - - empty = Tensor.empty((80, 44)) - rand = Tensor.randn_like(empty, dtype=dtypes.float16) - assert rand.shape == empty.shape - assert rand.dtype == dtypes.float16 - assert rand.device == empty.device - - def test_randn(self): - self.assertEqual(Tensor.randn(3,3,dtype=dtypes.half).dtype, dtypes.half) - self.assertTrue(normal_test(Tensor.randn)) - self.assertTrue(equal_distribution(Tensor.randn, torch.randn, lambda x: np.random.randn(*x))) - - @given(strat.sampled_from([dtypes.float, dtypes.float16, dtypes.bfloat16])) - @unittest.skipIf(Device.DEFAULT in ["HSA", "AMD"], "bfloat16 local buffer broken in HSA") - def test_randn_finite(self, default_float): - if not is_dtype_supported(default_float): return - old_default_float = dtypes.default_float - # low precision can result in inf from randn - dtypes.default_float = default_float - t = Tensor.randn(256, 256) - mx = t.max().numpy().item() - mn = t.min().numpy().item() - print(f"testing with {default_float=}") - assert math.isfinite(mx), mx - assert math.isfinite(mn), mn - dtypes.default_float = old_default_float - - def test_randint(self): - self.assertFalse(normal_test(Tensor.randint)) - self.assertTrue(equal_distribution(partial(Tensor.randint, low=-2, high=5), - numpy_func=lambda x: np.random.randint(low=-2, high=5, size=x))) - self.assertTrue(equal_distribution(partial(Tensor.randint, low=-2, high=5, dtype="int32"), - numpy_func=lambda x: np.random.randint(low=-2, high=5, size=x))) - self.assertTrue(Tensor.randint(1, device="CPU").device=="CPU") - # check types of args - with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0.1, high=3) - with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0, high=3.5) - with self.assertRaises(TypeError): Tensor.randint((3, 4), low=1, high=3, dtype="float") - with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0, high=3, dtype=dtypes.float32) - - def test_normal(self): - self.assertTrue(normal_test(Tensor.normal)) - self.assertTrue(equal_distribution(Tensor.normal, lambda x: torch.nn.init.normal_(torch.empty(x), mean=0, std=1), - lambda x: np.random.normal(loc=0, scale=1, size=x))) - - def test_uniform(self): - self.assertFalse(normal_test(Tensor.uniform)) - self.assertTrue(equal_distribution(Tensor.uniform, lambda x: torch.nn.init.uniform_(torch.empty(x)), lambda x: np.random.uniform(size=x))) - self.assertTrue(equal_distribution(partial(Tensor.uniform, low=-100, high=100, dtype=dtypes.int32), - numpy_func=lambda x: np.random.randint(low=-100, high=100, size=x))) - - def test_scaled_uniform(self): - self.assertFalse(normal_test(Tensor.scaled_uniform)) - self.assertTrue(equal_distribution(Tensor.scaled_uniform, lambda x: torch.nn.init.uniform_(torch.empty(x), a=-1, b=1) / math.sqrt(math.prod(x)), - lambda x: np.random.uniform(-1, 1, size=x) / math.sqrt(math.prod(x)))) - - def test_glorot_uniform(self): - self.assertFalse(normal_test(Tensor.glorot_uniform)) - self.assertTrue(equal_distribution(Tensor.glorot_uniform, lambda x: torch.nn.init.xavier_uniform_(torch.empty(x)), - lambda x: np.random.uniform(-1, 1, size=x) * math.sqrt(6 / (x[0] + math.prod(x[1:]))))) - - def test_kaiming_uniform(self): - for shape in [(32, 128, 3, 3), (80, 44), (3, 55, 35)]: - self.assertTrue(equal_distribution(Tensor.kaiming_uniform, lambda x: torch.nn.init.kaiming_uniform_(torch.empty(x)), shape=shape)) - - def test_kaiming_normal(self): - for shape in [(32, 128, 3, 3), (80, 44), (3, 55, 35)]: - self.assertTrue(equal_distribution(Tensor.kaiming_normal, lambda x: torch.nn.init.kaiming_normal_(torch.empty(x)), shape=shape)) - - def test_multinomial(self): - self.assertRaises(AssertionError, lambda: Tensor(2).multinomial(1, replacement=False)) - self.assertRaises(AssertionError, lambda: Tensor([1, 9]).multinomial(0, replacement=False)) - def _check_with_torch(w, num_samples, replacement): - tiny_res = Tensor(w).multinomial(num_samples, replacement=replacement) - torch_res = torch.tensor(w).multinomial(num_samples, replacement=replacement) - self.assertEqual(tiny_res.shape, torch_res.shape) - if torch_res.ndim == 1: - tiny_res = tiny_res.unsqueeze(0) - torch_res = torch_res.unsqueeze(0) - for i in range(torch_res.shape[0]): - self.assertTrue(equal_distribution(lambda *_: tiny_res[i], lambda _: torch_res[i])) - _check_with_torch(w=[0.231, 0., 1., 0.5], num_samples=2000, replacement=True) - _check_with_torch(w=[[0.2, 0.8]], num_samples=2000, replacement=True) # 2D but only 1 row - _check_with_torch(w=[[0.453, 0., 1., 0.81], [0.1, 0.8, 0., 0.1]], num_samples=2000, replacement=True) - # no-replacement isn't supported, unless taking only one sample - w = [0.1, 0.9] - self.assertRaises(AssertionError, lambda: Tensor(w).multinomial(100, replacement=False)) - - @TinyJit - def sample_one(): return Tensor(w).multinomial(1, replacement=False).realize() - - tiny_samples = [sample_one().item() for _ in range(1000)] - torch_samples = [torch.tensor(w).multinomial(1, replacement=False).item() for _ in range(1000)] - self.assertTrue(equal_distribution(lambda *_: Tensor(tiny_samples), lambda _: torch.tensor(torch_samples))) - - def test_multinomial_counterexample(self): - tiny_res = Tensor([0.3, 0.6, 0.1]).multinomial(4000, replacement=True) - torch_res = torch.tensor([0.3, 0.6, 0.1]).multinomial(4000, replacement=True) - self.assertTrue(equal_distribution(lambda *_: tiny_res, lambda _: torch_res)) - torch_res = torch.tensor([0.2, 0.7, 0.1]).multinomial(4000, replacement=True) - self.assertFalse(equal_distribution(lambda *_: tiny_res, lambda _: torch_res)) - - def test_conv2d_init(self): - params = (128, 256, (3,3)) - assert equal_distribution(lambda *_: nn.Conv2d(*params).weight, lambda _: torch.nn.Conv2d(*params).weight.detach()) - assert equal_distribution(lambda *_: nn.Conv2d(*params).bias, lambda _: torch.nn.Conv2d(*params).bias.detach()) - - def test_linear_init(self): - params = (64, 256) - assert equal_distribution(lambda *_: nn.Linear(*params).weight, lambda _: torch.nn.Linear(*params).weight.detach()) - assert equal_distribution(lambda *_: nn.Linear(*params).bias, lambda _: torch.nn.Linear(*params).bias.detach()) - - def test_bn_init(self): - params = (64,) - assert equal_distribution(lambda *_: nn.BatchNorm2d(*params).weight, lambda _: torch.nn.BatchNorm2d(*params).weight.detach()) - assert equal_distribution(lambda *_: nn.BatchNorm2d(*params).bias, lambda _: torch.nn.BatchNorm2d(*params).bias.detach()) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_renderer_failures.py b/tinygrad/test/test_renderer_failures.py deleted file mode 100644 index 3dd795ea..00000000 --- a/tinygrad/test/test_renderer_failures.py +++ /dev/null @@ -1,121 +0,0 @@ -import unittest -from typing import List, cast -import numpy as np -from tinygrad.device import Buffer, Device, is_dtype_supported -from tinygrad.dtype import dtypes, ConstType -from tinygrad.engine.realize import CompiledRunner -from tinygrad.helpers import dedup, flatten, prod -from tinygrad.renderer.cstyle import CStyleLanguage -from tinygrad.renderer.ptx import PTXRenderer -from tinygrad.renderer.wgsl import WGSLRenderer -from tinygrad.runtime.ops_python import PythonRenderer -from tinygrad.uop.ops import UOp, Ops, python_alu -from tinygrad.renderer import ProgramSpec -from tinygrad.tensor import Tensor, _to_np_dtype -from tinygrad.codegen import full_rewrite -from tinygrad.engine.realize import lower_schedule_item - -def _test_uop_result(inputs:List[Tensor], stores:List[UOp], local_size=None): - for x in inputs: x.realize() - # NOTE: we only toposort the stores - uops: List[UOp] = [] - def _recursive_add(uop:UOp) -> List[UOp]: return flatten([_recursive_add(x) for x in uop.src])+[uop] - uops = dedup(flatten(_recursive_add(st) for st in stores)) - outbufs = [Buffer(Device.DEFAULT, sz:=(1 if local_size is None else prod(local_size)), (dtype:=u.src[1].dtype), \ - initial_value=np.zeros(sz, dtype=_to_np_dtype(dtype)).data) for u in uops if u.op is Ops.STORE] - inbufs = [cast(UOp,x.uop).base.buffer for x in inputs] - src = Device[Device.DEFAULT].renderer.render(uops) - ei = CompiledRunner(ProgramSpec("test", src, Device.DEFAULT, uops[-1], uops=uops, local_size=local_size)) - ei.exec(outbufs+inbufs) - return [np.frombuffer(x.as_buffer(), _to_np_dtype(x.dtype)) for x in outbufs] - -def _setup_and_test_alu(alu_op:Ops, input_val:ConstType, *alu_src_uops:UOp): - dtype = alu_src_uops[0].dtype - a = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 0) - b = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 1) - idx = UOp.const(dtypes.int, 0) - ld = UOp(Ops.LOAD, dtype, (b.index(idx),)) - alu = ld.alu(alu_op, *alu_src_uops) - store = UOp.store(a.index(idx), alu) - sink = UOp(Ops.SINK, dtypes.void, (store,)) - uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) - return _test_uop_result([Tensor([input_val])], uops)[0] - -class TestRendererFailures(unittest.TestCase): - @unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, (PTXRenderer, PythonRenderer)), "test is for ptx or python renderer") - def test_gated_store_with_alu(self): - a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - gate_alu = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) - gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0, gate_alu), UOp.const(dtypes.int, 1))) - sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) - uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) - ret = _test_uop_result([], uops, local_size=[4, 1, 1])[0] - np.testing.assert_equal(ret, [0, 1, 1, 1]) - - @unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, (PTXRenderer, PythonRenderer)), "test is for ptx or python renderer") - def test_gated_store_with_alu_2d(self): - a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - gate_alu_0 = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) - gate_alu_1 = (lidx1:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx1', 2))).ne(0) - gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0+lidx1*4, gate_alu_0&gate_alu_1), UOp.const(dtypes.int, 1))) - sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) - uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) - ret = _test_uop_result([], uops, local_size=[4, 2, 1])[0] - np.testing.assert_equal(ret, [0, 0, 0, 0, 0, 1, 1, 1]) - -@unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, CStyleLanguage), "uops are for cstyle") -class TestCStyleFailures(unittest.TestCase): - def test_inline_const_alu(self): - # CPU doesn't use the max function - ret = _setup_and_test_alu(Ops.MAX, 1, UOp.const(dtypes.int, dtypes.min(dtypes.int)+1)) - self.assertEqual(ret[0], 1) - - def _test_src_strip_paren(self, op: Ops, should_strip_paren:bool=True): - dtype = "bool" if op in (Ops.OR, Ops.XOR, Ops.AND) else None - ret = Tensor.empty(1, dtype=dtype) - for _ in range(5): ret = python_alu[op](ret, Tensor.empty(1, dtype=dtype)) - schedule = ret.schedule() - assert len(schedule) == 1 - ei = lower_schedule_item(schedule[0]) - src = ei.prg.p.src - self.assertEqual("("*5 not in src, should_strip_paren) - - def test_repeat_add(self): self._test_src_strip_paren(Ops.ADD) - def test_repeat_mul(self): self._test_src_strip_paren(Ops.MUL) - def test_repeat_xor(self): self._test_src_strip_paren(Ops.XOR) - def test_repeat_or(self): self._test_src_strip_paren(Ops.OR) - def test_repeat_and(self): self._test_src_strip_paren(Ops.AND) - def test_repeat_sub(self): self._test_src_strip_paren(Ops.SUB, should_strip_paren=False) - -@unittest.skipUnless(isinstance(Device[Device.DEFAULT].renderer, WGSLRenderer), "tests for wgsl renderer") -class TestWGSLFailures(unittest.TestCase): - def test_multiply_infinity(self): - # multiplying a positive constant by infinity should return infinity - # WGSL pipelines do not handle this reliably, some of which return zero, unless infinity always comes from a read on a dynamic buffer - ret = _setup_and_test_alu(Ops.MUL, 5.0, UOp.const(dtypes.float32, float("inf"))) - self.assertEqual(ret[0], float("inf")) - -@unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, PTXRenderer), "tests for ptx renderer") -class TestPTXFailures(unittest.TestCase): - @unittest.skip("INDEX can only have a gate ALU parent, not an IF") - def test_gated_store_with_if(self): - a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - gate_alu = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) - val = UOp.const(dtypes.int, 1) - if_uop = UOp(Ops.IF, dtypes.void, (gate_alu,)) - gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0, if_uop), val)) - sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) - uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) - ret = _test_uop_result([], uops, local_size=[4, 1, 1])[0] - np.testing.assert_equal(ret, [0, 1, 1, 1]) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_gated_define_acc_with_half_dtype(self): - a = Tensor.randn(32, 32, dtype=dtypes.half).realize() - b = Tensor.randn(34, 32, dtype=dtypes.half).realize() - result = a.pad((1,1)).matmul(b, dtype=dtypes.half).numpy() - reference = a.pad((1,1)).matmul(b, dtype=dtypes.float).numpy() - np.testing.assert_allclose(result, reference, atol=1e-2, rtol=1e-2) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_sample.py b/tinygrad/test/test_sample.py deleted file mode 100644 index ae713279..00000000 --- a/tinygrad/test/test_sample.py +++ /dev/null @@ -1,21 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Tensor, Variable, Device -from tinygrad.helpers import OSX - -@unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") -class TestSample(unittest.TestCase): - def test_sample(self): - X = Tensor.rand(10000, 50).realize() - BS = 16 - idxs = np.random.randint(0, X.shape[0], size=(BS)) - # this uncovered a bug with arg sort order - batch = [Variable(f'idx{i}', 0, X.shape[0]-1).bind(s) for i,s in enumerate(idxs.tolist())] - x = Tensor.cat(*[X.shrink(((batch[i], batch[i]+1), None)) for i in range(BS)]) - print(idxs) - ret = x.numpy() - base = X.numpy()[idxs] - np.testing.assert_equal(ret, base) - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/test_schedule.py b/tinygrad/test/test_schedule.py deleted file mode 100644 index cbcb6a6c..00000000 --- a/tinygrad/test/test_schedule.py +++ /dev/null @@ -1,2712 +0,0 @@ -# this will be the new test_ops for the next level -# schedule confirms the right things are capable of fusing -# NOTE: this has overlap with external_test_opt.py - -import unittest -import numpy as np -import functools -from typing import List, Optional, Union, cast -from hypothesis import assume, given, strategies as strat - -from tinygrad import nn, dtypes, Device, Tensor -from tinygrad.device import is_dtype_supported -from tinygrad.dtype import DType, ImageDType -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.uop.ops import PatternMatcher, UOp, Ops, GroupOp, UPat, graph_rewrite, track_rewrites -from tinygrad.codegen.symbolic import symbolic_simple -from tinygrad.helpers import CI, DEBUG, FUSE_ARANGE, SPLIT_REDUCEOP, GlobalCounters, Context, getenv, all_same, temp -from tinygrad.engine.grouper import view_left, view_right, sym, get_kernelize_map, Kernel, create_ast, merge_views, create_kernels -from tinygrad.engine.schedule import ScheduleItem, create_schedule_with_vars -from tinygrad.engine.realize import CompiledRunner, run_schedule, lower_schedule - -class KernelCountException(Exception): pass -def check_schedule(t:Union[Tensor, List[Tensor], UOp], allowed:int, to_prerealize:Optional[List[Tensor]]=None, filter_sink=True): - if to_prerealize: - with Context(DEBUG=0, TRACK_MATCH_STATS=0): Tensor.realize(*to_prerealize) - if isinstance(t, Tensor): sched = t.schedule() - elif isinstance(t, List) and isinstance(t[0], Tensor): sched = Tensor.schedule(*t) - else: - assert isinstance(t, UOp), f"can't schedule {t}" - sink = UOp.sink(t) if t.op is not Ops.SINK else t - becomes_map = get_kernelize_map(sink) - sched, _ = create_schedule_with_vars(sink.substitute(becomes_map)) - # test lowering all the ScheduleItems to ExecItems - kernel_cnt = len([si for si,ei in lower_schedule(sched.copy()) if isinstance(ei.prg, CompiledRunner) or not filter_sink]) - if kernel_cnt != allowed: - print(f"SCHEDULE ISSUE, expecting {allowed} got {len(sched)}") - if DEBUG >= 3: - for i,s in enumerate(sched): - print("kernel", i+1) - print(s.ast) - raise KernelCountException(f"{kernel_cnt} != {allowed}") - return sched - -def _realize_weights(m): - for p in nn.state.get_parameters(m): p.realize() - -def _test_conv2d(allowed:int, dtype:DType=dtypes.float, **kwargs): - old_default_float, dtypes.default_float = dtypes.default_float, dtype - dtypes.default_float = dtype - Tensor.manual_seed(0) - BS, CIN = 2, 3 - img = Tensor.randn(BS, CIN, 64, 64, requires_grad=True).realize() - w = Tensor.uniform(16, CIN, 3, 3, requires_grad=True).realize() - ret = Tensor.conv2d(img, w).relu().mean().backward() - dtypes.default_float = old_default_float - with Context(**kwargs): s = Tensor.schedule(ret, img.grad, w.grad) - run_schedule(s.copy()) - cnt = len([si for si in s if si.ast.op is Ops.SINK]) - assert cnt == allowed, f"expected {allowed} kernels, got {cnt}" - if getenv("CHECK", 1): - import torch - ref_img = torch.tensor(img.numpy(), requires_grad=True) - ref_w = torch.tensor(w.numpy(), requires_grad=True) - torch.nn.functional.conv2d(ref_img, ref_w).relu().mean().backward() - assert ref_img.grad is not None and ref_w.grad is not None and img.grad is not None and w.grad is not None - np.testing.assert_allclose(img.grad.numpy(), ref_img.grad.detach().numpy(), atol=1e-6 if dtype == dtypes.float else 1e-2) - np.testing.assert_allclose(w.grad.numpy(), ref_w.grad.detach().numpy(), atol=1e-6 if dtype == dtypes.float else 1e-2) - -@track_rewrites(named=True) -def schedule_graph_rewrite(big_sink:UOp): return graph_rewrite(big_sink, merge_views+sym, {}) - -class TestSchedule(unittest.TestCase): - def test_arange_avgpool2d(self, kcount=2): - x = Tensor.arange(25).reshape(1,1,5,5).cast(dtypes.float32) - t = x.avg_pool2d(padding=1) - sched = t.schedule() - self.assertEqual(len(sched), kcount) - run_schedule(sched) - import torch - torch_out = torch.nn.functional.avg_pool2d(torch.arange(25).reshape(1,1,5,5).float(), kernel_size=(2,2), padding=1).numpy() - np.testing.assert_allclose(t.numpy(), torch_out) - - def test_arange_avgpool2d_fused_noopt(self): - with Context(FUSE_ARANGE=1, NOOPT=1): self.test_arange_avgpool2d(kcount=1) - - # linearizer error - @unittest.skip("recursion error no longer raised") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "needs supports_float4 to fail") - def test_arange_avgpool2d_fused(self): - with self.assertRaises(RecursionError): - with Context(FUSE_ARANGE=1, NOOPT=0): self.test_arange_avgpool2d(kcount=1) - - # when we're fusing a reduce, all ReduceOps must have the same N in the dimensions - # all permutes, reshapes, expands and shrinks push through the reduce - def test_arange_sum(self): - a = Tensor.arange(6).reshape(3, 2).sum(axis=1) - with Context(FUSE_ARANGE=1): - run_schedule(check_schedule(a, 1)) - self.assertListEqual(a.tolist(), [1, 5, 9]) - - def test_arange_sum_alt(self): - a = (Tensor.arange(5).reshape(1,5).expand(6,5)*Tensor(2)).reshape(1,6,5).sum(axis=2) - with Context(FUSE_ARANGE=1): - run_schedule(check_schedule(a, 1)) - np.testing.assert_equal(a.numpy(), 20) - - def test_permute_arange(self): - a = Tensor.arange(6).reshape(6, 1, 1).permute(2, 0, 1).sum(axis=1) - with Context(FUSE_ARANGE=1): - run_schedule(check_schedule(a, 1)) - self.assertListEqual(a.tolist(), [[15]]) - - @unittest.skipIf(Device.DEFAULT == "CPU", "devices must mismatch") - def test_error_on_device_mismatch(self): - a = Tensor.empty(10) - b = Tensor.empty(10, device="CPU") - c = a+b - with self.assertRaisesRegex(RuntimeError, "all buffers must be on the same device"): check_schedule(c, 1) - - @unittest.skipIf(Device.DEFAULT == "CPU", "devices must mismatch") - def test_error_on_device_mismatch_alt(self): - a = Tensor.empty(10) - b = Tensor.empty((1,), device="CPU").expand(10).contiguous() - c = a+b - with self.assertRaisesRegex(RuntimeError, "all buffers must be on the same device"): check_schedule(c, 1) - - @unittest.skipUnless(is_dtype_supported(dtypes.half) and getenv("CAST_AFTER_EXPAND"), "need half and CAST_AFTER_EXPAND=1") - @unittest.skip("CAST_AFTER_EXPAND is not supported") - def test_expand_buffer_before_cast(self): - a = Tensor.randn(4, 2, 1).realize().permute((1, 0, 2)) - b = a.cast(dtypes.half).expand((2, 4, 4))+2 - run_schedule(check_schedule(b, 1)) - np.testing.assert_allclose(b.numpy(), np.broadcast_to(a.numpy().astype(np.float16), (2, 4, 4))+2) - - def test_indexing_scalars_simple(self): - X = Tensor.randn(2, 2).realize() - xt = X[Tensor(1)][Tensor(0)] - with Context(FUSE_ARANGE=1): - run_schedule(check_schedule(xt, 2)) - np.testing.assert_equal(xt.numpy(), X.numpy()[1][0]) - - @unittest.skipIf(CI and Device.DEFAULT == "NV", "crashes on NV CI") - def test_add_chain_buffers(self): - N = 31 - with Context(TRACK_MATCH_STATS=0, DEBUG=0): - bufs = [Tensor(i).reshape((1,)).contiguous().realize() for i in range(N)] - for X in range(1,N): - root = bufs[0] - for i in range(1,N,X): - root = root + functools.reduce(lambda a,b:a+b, bufs[i:i+X]) - self.assertEqual(root.item(), sum(range(N))) - - @given(strat.sampled_from(range(2,4)), strat.sampled_from(range(2,4)), strat.sampled_from(range(0,4)), strat.sampled_from(range(0,4))) - def test_indexing_scalars(self, x, y, a, b): - assume(a1 children but should still fuse - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 3)) - np.testing.assert_allclose(out.numpy(), \ - (c.numpy()*a.numpy().sum(axis=-1,keepdims=True)).sum(-1) + (b.numpy()*a.numpy().sum(axis=-1,keepdims=True)).sum(-1), atol=1e-4, rtol=1e-4) - - def test_reduce_expand_reduce_fusion(self): - Tensor.manual_seed(0) - a = Tensor.randn(4, 32).realize() - out = (a+a.sum(-1, keepdim=True)).sum(-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), (a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) - - def test_reduce_expand_reduce_expand_fusion(self): - Tensor.manual_seed(0) - a = Tensor.randn(4, 32).realize() - out = a+(a+a.sum(-1,keepdim=True)).sum(-1, keepdim=True) - # run_schedule(check_schedule(out, 2)) - run_schedule(check_schedule(out, 3)) - np.testing.assert_allclose(out.numpy(), \ - a.numpy()+(a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1,keepdims=True), atol=1e-4, rtol=1e-4) - - def test_branching_reduces_and_expands_fusion(self): - Tensor.manual_seed(0) - a = Tensor.randn(4, 32).realize() - out0 = a+a.sum(-1, keepdim=True) - out1 = out0.sum(-1) - # run_schedule(check_schedule(out, 2)) - run_schedule(check_schedule([out0, out1], 3)) - np.testing.assert_allclose(out0.numpy(), a.numpy()+a.numpy().sum(axis=-1,keepdims=True), atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(out1.numpy(), (a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_simple_sequential(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - y = Tensor.randn(4, 32).realize() - out = (y + x.sum(axis=-1, keepdim=True)).sum(axis=-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), (y.numpy() + x.numpy().sum(axis=-1, keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_simple_parallel(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - y = Tensor.randn(4, 32).realize() - out = y.sum(axis=-1) + x.sum(axis=-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), y.numpy().sum(axis=-1) + x.numpy().sum(axis=-1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_sequential(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - out = x.std(-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), x.numpy().std(axis=-1, ddof=1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_parallel(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - y = Tensor.randn(4, 32).realize() - out = x.std(-1) + y.std(-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 4)) - np.testing.assert_allclose(out.numpy(), x.numpy().std(axis=-1, ddof=1) + y.numpy().std(axis=-1, ddof=1), atol=1e-4, rtol=1e-4) - - def test_multireduce_diffops_sequential(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - out = (x - x.max(-1, keepdim=True)).sum(-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), (x.numpy() - x.numpy().max(axis=-1, keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_diffops_parallel(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - y = Tensor.randn(4, 32).realize() - out = x.sum(-1) + y.max(-1) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), x.numpy().sum(axis=-1) + y.numpy().max(axis=-1), atol=1e-4, rtol=1e-4) - - def test_multireduce_fusion_sequential_and_parallel(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - y = Tensor.randn(4, 32).realize() - mu = (x - x.max(axis=-1, keepdim=True)).mean(axis=-1, keepdim=True) + (y - y.max(axis=-1, keepdim=True)).mean(axis=-1, keepdim=True) - out = [((x - mu).square().sum(-1)/x.shape[-1]).sqrt(), ((y - mu).square().sum(-1)/y.shape[-1]).sqrt()] - np_mu = (x.numpy() - x.numpy().max(axis=-1, keepdims=True)).mean(axis=-1, keepdims=True) + \ - (y.numpy() - y.numpy().max(axis=-1, keepdims=True)).mean(axis=-1, keepdims=True) - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 6)) - np.testing.assert_allclose(out[0].numpy(), np.sqrt(np.square(x.numpy() - np_mu).sum(-1)/x.shape[-1]), atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(out[1].numpy(), np.sqrt(np.square(y.numpy() - np_mu).sum(-1)/y.shape[-1]), atol=1e-4, rtol=1e-4) - - def test_multimatmul_fusion(self): - Tensor.manual_seed(0) - a,b = Tensor.randn(4, 64).realize(), Tensor.rand(64,8).realize() - c,d = Tensor.randn(4, 64).realize(), Tensor.rand(64,8).realize() - out = a@b + c@d - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), a.numpy()@b.numpy() + c.numpy()@d.numpy(), atol=1e-4, rtol=1e-4) - - def test_softmax_fusion(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 12, 64, 64).realize() - out = x.softmax() - run_schedule(check_schedule(out, 3)) - expected = (x_exp:=np.exp(x.numpy()-x.numpy().max(-1, keepdims=True)))/x_exp.sum(-1, keepdims=True) - np.testing.assert_allclose(out.numpy(), expected, atol=1e-4, rtol=1e-4) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_softmax_upcast(self): - # input half, softmax in float - Tensor.manual_seed(0) - x = Tensor.randn(4, 12, 64, 64, dtype=dtypes.half).realize() - out = x.softmax(dtype=dtypes.float) - sched = out.schedule() - self.assertEqual(len(sched), 3) - self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) - - # input float, softmax in float - Tensor.manual_seed(0) - x = Tensor.randn(4, 12, 64, 64, dtype=dtypes.float).realize() - out = x.softmax(dtype=dtypes.float) - sched = out.schedule() - self.assertEqual(len(sched), 3) - self.assertEqual(sched[0].bufs[0].dtype, dtypes.float) - - def test_softmax_backward(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 12, 64, 64, requires_grad=True).realize() - x.softmax().sum().backward() - run_schedule(check_schedule(x.grad, 4)) - - # changed by: multireduce spec - def test_layernorm_onelayer_fusion(self): - Tensor.manual_seed(0) - layer = nn.LayerNorm([10, 10]) - layer.weight = Tensor.randn(10,10).realize() - layer.bias = Tensor.randn(10,10).realize() - x = Tensor.randn(20, 5, 10, 10).realize() - out = layer(x) - # run_schedule(check_schedule(out, 2)) - run_schedule(check_schedule(out, 3)) - y = (x.numpy() - x.numpy().mean(layer.axis, keepdims=True)) - expected = y / np.sqrt((y*y).mean(layer.axis, keepdims=True) + layer.eps) - np.testing.assert_allclose(out.numpy(), expected * layer.weight.numpy() + layer.bias.numpy(), atol=1e-4, rtol=1e-4) - - def test_scaled_dot_product_attention_fusion(self): - x, y, z, m = (Tensor.empty(32, 8, 16, 16) for _ in range(4)) - out = Tensor.scaled_dot_product_attention(x, y, z, attn_mask=m) - check_schedule(out, 5) - - def test_scaled_dot_product_attention_causal_fusion(self): - x, y, z = (Tensor.empty(32, 8, 16, 16) for _ in range(3)) - out = Tensor.scaled_dot_product_attention(x, y, z, is_causal=True) - check_schedule(out, 5) - - def test_adam_step_fusion(self): - with Tensor.train(): - x = Tensor.empty(4, 64, 32) - layer = nn.Linear(32, 32*4) - _realize_weights(layer) - opt = nn.optim.Adam(nn.state.get_parameters(layer), lr=1e-4) - layer(x).relu().sum().backward() - check_schedule(opt.schedule_step(), 16) - - def test_adam_conv_fuse(self): - with Tensor.train(): - img = Tensor.empty(2,3,4,4) - c1 = nn.Conv2d(3,32,3) - _realize_weights(c1) - opt = nn.optim.Adam(nn.state.get_parameters(c1), lr=1e-4) - opt.zero_grad() - c1(img).relu().sum().backward() - check_schedule(opt.schedule_step(), 16) - - def test_adam_2convs_fuse(self): - with Tensor.train(): - img = Tensor.empty(2,3,4,4) - c1 = nn.Conv2d(3,16,3,bias=False) - c2 = nn.Conv2d(16,32,2,bias=False) - _realize_weights([c1, c2]) - opt = nn.optim.Adam(nn.state.get_parameters([c1, c2]), lr=1e-4) - opt.zero_grad() - c2(c1(img).relu()).relu().sum().backward() - check_schedule(opt.schedule_step(), 20) - - def test_sgd_conv_fuse(self): - with Tensor.train(): - img = Tensor.empty(2,3,4,4) - c1 = nn.Conv2d(3,32,3) - _realize_weights(c1) - opt = nn.optim.SGD(nn.state.get_parameters(c1)) - opt.zero_grad() - c1(img).relu().sum().backward() - check_schedule(opt.schedule_step(), 3) - - def test_sgd_2convs_fuse(self): - with Tensor.train(): - img = Tensor.empty(2,3,4,4) - c1 = nn.Conv2d(3,16,3,bias=False) - c2 = nn.Conv2d(16,32,2,bias=False) - _realize_weights([c1, c2]) - opt = nn.optim.SGD(nn.state.get_parameters([c1, c2])) - opt.zero_grad() - c2(c1(img).relu()).relu().sum().backward() - check_schedule(opt.schedule_step(), 7) - - @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") - def test_fold_2convs_sgd_nesterov_momentum_wd(self): - with Tensor.train(): - img = Tensor.empty(2,3,4,4) - c1 = nn.Conv2d(3,16,3,bias=False) - c2 = nn.Conv2d(16,32,2,bias=False) - _realize_weights([c1, c2]) - opt = nn.optim.SGD(nn.state.get_parameters([c1, c2]), nesterov=True, momentum=0.9, weight_decay=0.1) - opt.zero_grad() - c2(c1(img).relu()).relu().sum().backward() - check_schedule(opt.schedule_step(), 13) - - def test_sgd_4convs_fuse(self): - with Tensor.train(): - img = Tensor.empty(2,3,16,16) - c1 = nn.Conv2d(3,4,3,bias=False) - c2 = nn.Conv2d(4,8,3,bias=False) - c3 = nn.Conv2d(8,16,3,bias=False) - c4 = nn.Conv2d(16,32,3,bias=False) - _realize_weights([c1, c2, c3, c4]) - opt = nn.optim.SGD(nn.state.get_parameters([c1, c2, c3, c4])) - opt.zero_grad() - c4(c3(c2(c1(img).relu()).relu()).relu()).relu().sum().backward() - check_schedule(opt.schedule_step(), 17) - - def test_sgd_4convs_fuse_conv_bw(self): - with Tensor.train(): - img = Tensor.empty(2,3,16,16) - c1 = nn.Conv2d(3,4,3,bias=False) - c2 = nn.Conv2d(4,8,3,bias=False) - c3 = nn.Conv2d(8,16,3,bias=False) - c4 = nn.Conv2d(16,32,3,bias=False) - _realize_weights([c1, c2, c3, c4]) - opt = nn.optim.SGD(nn.state.get_parameters([c1, c2, c3, c4])) - opt.zero_grad() - c4(c3(c2(c1(img).relu()).relu()).relu()).relu().sum().backward() - with Context(FUSE_CONV_BW=1): check_schedule(opt.schedule_step(), 14) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_prefer_half_buffer(self): - x = Tensor.ones(4).contiguous().realize() - # y = Tensor.ones(4).contiguous().realize() - z = Tensor.ones(4, 4).contiguous().realize() - - # should not create extra kernel if output will be realized anyways - dummy = x.sum().half().float() - check_schedule(dummy, 1) - dummy = x.sum().half().float().contiguous() + 1 - check_schedule(dummy, 2) - - # shared between two outputs - shared = x.sum().half().float() - a = shared * 2 - b = shared * 3 - sched = check_schedule([a, b], 3) - # store reduceop in half - self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) - # fuse cast with the child kernel - self.assertEqual(sched[1].bufs[0].dtype, dtypes.float) - self.assertEqual(sched[2].bufs[0].dtype, dtypes.float) - - # reduce - a = z.sum(axis=0).half().float().sum(axis=0) - sched = check_schedule(a, 2) - self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) - self.assertEqual(sched[1].bufs[0].dtype, dtypes.float) - - # expand - # expand will realize just after the .float(), so requires change to realize-before-expand - # normal = (x.sum().half().float().reshape(1) * y).sum() - # sched = check_schedule(normal, 2) - # for si in sched[:-1]: assert all(out.dtype == dtypes.half for out in si.outputs[:-1]) - - # parallel reduce - # a = x.sum().half().float() * y.sum().half().float() - # b = a + 1 - # c = a + 2 - # sched = check_schedule([b, c], 4) - # doesn't store either in half because it doesn't chase - - def test_reduce_simple_chase(self): - a = Tensor.empty(4, 4, 4) - r = a.sum(0) + 6 - b = r.sum(0) * 4 - c = r.sum(1) * 2 - schedule = check_schedule([b, c], 3) - self.assertIs(store_val(schedule[0]).op, Ops.ADD) - - def test_multireduce_simple_chase(self): - Tensor.manual_seed(0) - a = Tensor.randn(4, 4, 4).realize() - r = (a + (a.sum(0, keepdim=True) + 6)).sum(0) * 2 - b = r.sum(0) + 8 - c = r.sum(1) + 12 - np_r = (a.numpy() + (a.numpy().sum(0) + 6)).sum(0) * 2 - # schedule = check_schedule([b,c], 3) - # self.assertIs(schedule[0].ast[0].src[0].arg, Ops.MUL) - schedule = check_schedule([b,c], 4) - run_schedule(schedule) - np.testing.assert_allclose(b.numpy(), np_r.sum(0) + 8, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(c.numpy(), np_r.sum(1) + 12, atol=1e-4, rtol=1e-4) - - def test_push_permute_chase(self): - a = Tensor.empty(4, 4, 4) - b = Tensor.empty(4, 4) - r = a.sum(2) + b - d = r.T * 4 - e = r * d - schedule = check_schedule([d, e], 3) - self.assertIs(store_val(schedule[0]).op, Ops.ADD) - - def test_multireduce_push_permute_chase(self): - Tensor.manual_seed(0) - a = Tensor.randn(4, 4, 4).realize() - b = Tensor.randn(4, 4).realize() - r = a.sum(2) + b - d = r.T * 4 - e = r * (d + a).sum(2) - schedule = check_schedule([d, e], 3) # make sure it doesn't fuse - self.assertIs(store_val(schedule[0]).op, Ops.ADD) - run_schedule(schedule) - np.testing.assert_allclose(d.numpy(), (a.numpy().sum(2) + b.numpy()).T * 4, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(e.numpy(), (a.numpy().sum(2) + b.numpy()) * (d.numpy() + a.numpy()).sum(2), atol=1e-4, rtol=1e-4) - - def test_push_shrink_chase(self): - a = Tensor.empty(16, 16) - b = Tensor.empty(4) - c = Tensor.empty(16, ) - r = a.sum(1) + c - d = r[:4] * b - schedule = check_schedule(d, 2) - self.assertIs(store_val(schedule[0]).op, Ops.ADD) - - def test_multireduce_push_shrink_chase(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = Tensor.randn(4).realize() - c = Tensor.randn(16, ).realize() - d = Tensor.randn(16, 16).realize() - r = a.sum(1) + c - out = r[:4] * b + d.sum(1)[:4] - # schedule = check_schedule(out, 2) - schedule = check_schedule(out, 3) - self.assertIs(store_val(schedule[0]).op, Ops.ADD) - run_schedule(schedule) - np.testing.assert_allclose(out.numpy(), (a.numpy().sum(1) + c.numpy())[:4] * b.numpy() + d.numpy().sum(1)[:4], atol=1e-4, rtol=1e-4) - - def test_midreduce_nochase(self): - a = Tensor.empty(16, 16) - b = (a.sum(0) + a.max(1)) + 2 - schedule = check_schedule(b, 2) - self.assertIs(store_val(schedule[0]).op, Ops.REDUCE_AXIS) - - def test_multireduce_midreduce_nochase(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = (a.sum(0)+a.max(0) + a.max(1)+a.sum(1)) + 2 - # schedule = check_schedule(b, 2) - schedule = check_schedule(b, 4) - self.assertIs(store_val(schedule[0]).op, Ops.REDUCE_AXIS) - run_schedule(schedule) - np.testing.assert_allclose(b.numpy(), a.numpy().sum(0)+a.numpy().max(0) + a.numpy().max(1)+a.numpy().sum(1)+2, atol=1e-4, rtol=1e-4) - - # changed by: multireduce spec - # pattern in test_transformer - def test_partial_fuse1(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = Tensor.randn(16, 16).realize() - c = a.sum() + 2 - d = (a.sum() - b.sum()) * 4 - # run_schedule(check_schedule([c, d], 1)) - run_schedule(check_schedule([c, d], 3)) - np.testing.assert_allclose(c.numpy(), a.numpy().sum()+2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(d.numpy(), (a.numpy().sum() - b.numpy().sum()) * 4, atol=1e-4, rtol=1e-4) - - # changed by: multireduce spec - # pattern in conv - def test_partial_fuse2(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = Tensor.randn(16, 16).realize() - c = a.sum() + 2 - d = b.sum() - c - # run_schedule(check_schedule([c, d], 1)) - run_schedule(check_schedule([c, d], 2)) - np.testing.assert_allclose(c.numpy(), a.numpy().sum()+2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(d.numpy(), b.numpy().sum()-(a.numpy().sum()+2), atol=1e-4, rtol=1e-4) - - # changed by: multireduce spec - # pattern in adam - @unittest.expectedFailure - def test_partial_fuse3(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = Tensor.randn(16, 16).realize() - c = a.sum() + 2 - d = a.sum() * 2 - e = c * d - f = b.sum() - e - # run_schedule(check_schedule([c, d, e, f], 1)) - run_schedule(check_schedule([c, d, e, f], 2)) - np.testing.assert_allclose(c.numpy(), c_np:=a.numpy().sum()+2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(d.numpy(), d_np:=a.numpy().sum()*2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(e.numpy(), e_np:=c_np*d_np, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(f.numpy(), b.numpy().sum() - e_np, atol=1e-4, rtol=1e-4) - - # changed by: multireduce spec - @unittest.expectedFailure - def test_partial_fuse4(self): - Tensor.manual_seed(0) - a = Tensor.randn(16, 16).realize() - b = Tensor.randn(16, 16).realize() - c = a.sum() + 2 - d = a.sum() * 2 - e = c * d - f = (b - d).sum() - e - # run_schedule(check_schedule([c, d, e, f], 1)) - run_schedule(check_schedule([c, d, e, f], 3)) - np.testing.assert_allclose(c.numpy(), c_np:=a.numpy().sum()+2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(d.numpy(), d_np:=a.numpy().sum()*2, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(e.numpy(), e_np:=c_np*d_np, atol=1e-4, rtol=1e-4) - np.testing.assert_allclose(f.numpy(), (b.numpy()-d_np).sum()-e_np, atol=1e-4, rtol=1e-4) - - def test_pad_reduce_safe(self): - Tensor.manual_seed(0) - a = Tensor.rand(3, 4, 5).realize() - b = Tensor.rand(3, 4, 5).realize() - out = (a + b).pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() - run_schedule(check_schedule(out, 1)) - np.testing.assert_allclose(out.numpy(), np.pad(a.numpy()+b.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-5, rtol=1e-6) - - def test_multireduce_pad_reduce_safe(self): - Tensor.manual_seed(0) - a = Tensor.randn(3, 4, 5).realize() - b = Tensor.randn(3, 4, 5).realize() - out = (a.pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum(keepdim=True)+b.pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum()).contiguous() - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), np.pad(a.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(keepdims=True) + \ - np.pad(b.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-4, rtol=1e-4) - - def test_pad_reduce_unsafe(self): - Tensor.manual_seed(0) - a = Tensor.rand(3, 4, 5).realize() - out = a.log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() - run_schedule(check_schedule(out, 2)) - np.testing.assert_allclose(out.numpy(), np.pad(np.log2(a.numpy()), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-5, rtol=1e-6) - - def test_multireduce_pad_reduce_unsafe(self): - Tensor.manual_seed(0) - a = Tensor.randn(3, 4, 5).abs().realize() - b = Tensor.randn(3, 4, 5).abs().realize() - out = (a.log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum()+b).abs().log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() - # run_schedule(check_schedule(out, 1)) - run_schedule(check_schedule(out, 4)) - np.testing.assert_allclose(out.numpy(), np.pad(np.log2(np.abs(np.pad(np.log2(a.numpy()), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum() + \ - b.numpy())), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=3e-4, rtol=1e-6) - - def test_shrink_pad_safe(self): - a = Tensor.ones((3, )).contiguous().realize() - b = Tensor.ones((3, )).contiguous().realize() - out = (a + b).shrink(((0, 1),)).pad(((0, 1),)).contiguous() - run_schedule(check_schedule(out, 1)) - np.testing.assert_equal(out.numpy(), [2, 0]) - - def test_shrink_pad_unsafe(self): - a = Tensor.ones((3, )).contiguous().realize() - out = a.exp2().shrink(((0, 1),)).pad(((0, 1),)).contiguous() - run_schedule(check_schedule(out, 2)) - np.testing.assert_equal(out.numpy(), [2, 0]) - - def test_base_change_shrink_pad(self): - a = Tensor.ones(3, 3).contiguous().realize() - b = a.exp2() - c = b[:-1, :-1] - d = c.pad(((0, 1), (0, 1))) * 2 - run_schedule(check_schedule(d, 2)) - np.testing.assert_equal(d.numpy(), np.pad(np.exp2(a.numpy())[:-1, :-1], ((0, 1), (0, 1)))*2) - - def test_base_change_expand_pad(self): - a = Tensor.ones(3, 3).contiguous().realize() - b = a.exp2() - c = b[:, None, :] - d = c.pad(((0, 0), (1, 1), (0, 0))) * 2 - run_schedule(check_schedule(d, 2)) - np.testing.assert_equal(d.numpy(), np.pad(np.exp2(a.numpy())[:, None, :], ((0, 0), (1, 1), (0, 0)))*2) - - def test_fuse_arange_pad_replicate_mode(self): - x = Tensor.empty(3,3,3,3, requires_grad=True) - y = x.pad((-1,2,2,-1), mode="replicate") - dx = y.sum().gradient(x)[0] - with Context(FUSE_ARANGE=1): - sched = check_schedule(dx, 3) - run_schedule(sched) - np.testing.assert_allclose(dx.numpy(), [[[[0.,3.,9.],[0,1.,3.],[0.,0.,0.]]]*3]*3) - - # TODO like openpilot with imagef - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_base_change_expand_expand(self): - a = Tensor.ones(4, 4).contiguous().realize() - b = a.cast(dtypes.half).expand(2, 4, 4) - c = b.cast(dtypes.int).expand(2, 2, 4, 4) - run_schedule(check_schedule(c, 2)) - np.testing.assert_equal(c.numpy(), np.ones(((2, 2, 4, 4)), dtype=np.int32)) - - def test_base_change_pad_expand(self): - a = Tensor.full((4, 4), 1.).contiguous().realize() - b = Tensor.full((4, 4), 2.).contiguous().realize() - c = (a + b).pad(((1, 1), (1, 1))) - d = c.cast(dtypes.int).expand((2, 6, 6)) * 4 - run_schedule(check_schedule(d, 2)) - c_np = np.pad((np.full((4, 4), 2., dtype=np.float32) + np.full((4, 4), 1., dtype=np.float32)), ((1, 1), (1, 1)), constant_values=0.0) - np.testing.assert_equal(d.numpy(), np.broadcast_to(c_np.astype(np.half), (2, *c_np.shape)) * 4) - - def test_pad_reduce_unsafe_multiview_st(self): - P = Tensor.ones(3, 3).contiguous() - sums = P.sum(axis=1, keepdim=True) - P /= sums - p = P[0] - p = p.pad(((1, 0), )) - p = p.repeat([2]) - run_schedule(check_schedule(p, 3)) - tiny_ret = p.numpy() - - P = np.ones((3, 3), dtype=np.float32) - sums = P.sum(axis=1, keepdims=True) - P /= sums - p = P[0] - p = np.pad(p, (1, 0), 'constant') - p = np.tile(p, 2) - np.testing.assert_allclose(tiny_ret, p) - - def test_bitcast_fuses(self): - x = Tensor.empty(1, dtype=dtypes.float32) - a = x.exp2().bitcast(dtypes.int32) - b = x.bitcast(dtypes.int32) - check_schedule(a+b, 1) # this should fuse when it makes sense - - @unittest.skip("disabling subbuffer manually isn't supported anymore") - def test_bitcast_disable_subbufer(self): - x = cast(UOp, Tensor.empty(1, dtype=dtypes.float32).realize().uop) - a = x.alu(Ops.EXP2).cast(dtypes.int32, True, allow_buffer_view=False) - b = x.cast(dtypes.int32, True, allow_buffer_view=False) - b = a.alu(Ops.ADD, b) - check_schedule(b, 1) - - def test_reduceop_reshape_dont_push(self): - Tensor.manual_seed(0) - x = Tensor.randn(10, 20).realize() - out = x.argmax(1) - run_schedule(check_schedule(out, 3)) # TODO: push a reduceop through a reshape - - def test_conv2d(self): _test_conv2d(7) - def test_conv2d_fused(self): _test_conv2d(6, FUSE_CONV_BW=1) - - @unittest.skipUnless(is_dtype_supported(dtypes.half) and is_dtype_supported(dtypes.ulong), "need half and ulong") - def test_conv2d_half(self): _test_conv2d(7, dtype=dtypes.half) - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Causes other tests to fail") - @unittest.expectedFailure - def test_conv2d_fused_half(self): _test_conv2d(5, dtype=dtypes.half) - - @unittest.skipIf(getenv("VIZ"), "TODO: VIZ blocks gc") - def test_schedule_mem_used(self): - base = GlobalCounters.mem_used - Tensor.ones(256).contiguous().realize() - Tensor.ones(5, 5).contiguous().schedule() - self.assertEqual(GlobalCounters.mem_used-base, 0) - - @unittest.skip("TODO: this is consistently creating non reproducible failures") - def test_schedule_mem_used_with_inputs(self): - base = GlobalCounters.mem_used - x = Tensor.ones(256).contiguous().realize() - (x+Tensor.ones(256).contiguous()).schedule() - self.assertEqual(GlobalCounters.mem_used-base, 1024) - - def test_const_schedule(self): - constv = Tensor.empty(2, 2).uop.const_like(10) - check_schedule(constv, 0) - - def test_const_schedule_contig(self): - constv = Tensor.empty(2, 2).uop.const_like(10).contiguous() - check_schedule(constv, 1) - - @unittest.skipIf(Device.DEFAULT != "GPU", "image only supported on GPU") - def test_image_matmul(self): - with Context(IMAGE=2): - x = Tensor.randn((9, 9)).realize() - y = Tensor.randn((9, 9)).realize() - out = x@y - run_schedule(check_schedule(out, 3)) - np.testing.assert_allclose(out.numpy(), x.numpy()@y.numpy(), atol=1e-4, rtol=1e-4) - self.assertIsInstance(out.dtype, ImageDType) - self.assertIsNotNone(out.uop.base.realized) - self.assertIsInstance(out.uop.base.realized.dtype, ImageDType) - - def _test_fusion(self, shapes, f, cnt): - with Context(DEBUG=0, TRACK_MATCH_STATS=0): args = [Tensor.randn(s).realize() for s in shapes] - run_schedule(check_schedule(compare:=f(*args), cnt)) - if getenv("COMPARE", 1): - import torch - good = f(*[torch.tensor(x.numpy()) for x in args]) - np.testing.assert_allclose(compare.numpy(), good.numpy(), atol=1e-4, rtol=1e-4) - - def test_late_fusion_simple(self): - self._test_fusion([(4, 4), (4, 1)], lambda a,b:a.sum(1, keepdim=True)+b, 1) - - def test_late_fusion_post_reshape(self): - self._test_fusion([(4, 4), (1, 4)], lambda a,b:a.sum(1).reshape(b.shape)+b, 1) - - def test_late_fusion_post_permute(self): - self._test_fusion([(4, 6, 4), (4, 4, 1)], lambda a,b:a.sum(1, keepdim=True).permute((2, 0, 1))+b, 2) - - def test_late_fusion_double_transpose(self): - self._test_fusion([(32, 16, 1)], - lambda a:(a.expand(32, 16, 16).sum((2,), keepdim=True).permute((1, 0, 2))+2).permute((1, 0, 2)).contiguous(), 1) - - def test_late_fusion_post_expand(self): - self._test_fusion([(32, 32)], lambda a:a-a.sum(1), 2) - - def test_cast_padded_view(self): - a = Tensor.arange(4).reshape(1, 4) - casted_view = a.pad(((0, 1), (0, 0))).cast(dtypes.float) - casted_view.realize() - self.assertEqual(casted_view.uop.base.realized.size, 4) - realized_view = casted_view.contiguous().realize() - self.assertEqual(realized_view.uop.base.realized.size, 8) - self.assertListEqual(realized_view.tolist(), [[0.0, 1.0, 2.0, 3.0], [0.0, 0.0, 0.0, 0.0]]) - - # NOTE: we only reorder CAST if it's an EXPAND - def test_cast_after_shrink(self): - a = Tensor.arange(4).reshape(1, 4) - casted_view = a.shrink(((0, 1), (0, 2))).cast(dtypes.float) - casted_view.realize() - self.assertEqual(casted_view.uop.base.realized.size, 2) - realized_view = casted_view.contiguous().realize() - self.assertEqual(realized_view.uop.base.realized.size, 2) - self.assertListEqual(realized_view.tolist(), [[0, 1]]) - - def test_cast_const_view(self): - a = Tensor.ones((4, 4), dtype=dtypes.float32) - casted_view = a.cast(dtypes.int32) - run_schedule(check_schedule(casted_view, 0)) - self.assertIsNone(casted_view.uop.base.realized) - realized_const_view = casted_view.contiguous() - run_schedule(check_schedule(realized_const_view, 1)) - self.assertListEqual(realized_const_view.tolist(), [[1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1]]) - - @given(strat.sampled_from(dtypes.all), strat.sampled_from(dtypes.all)) - def test_cast_padded_const(self, dt1, dt2): - assume(is_dtype_supported(dt1) and is_dtype_supported(dt2)) - a = Tensor(1, dtype=dt1).reshape(1, 1).pad(((1, 1), None)) - casted_view = a.cast(dt2) - run_schedule(check_schedule(casted_view, 0)) - realized_const_view = casted_view.contiguous() - run_schedule(check_schedule(realized_const_view, 1)) - np.testing.assert_equal(realized_const_view.numpy(), [[0], [1], [0]]) - -class TestIndexing(unittest.TestCase): - def check_schedule(self, xt:Union[Tensor,List[Tensor]], cnt:int): - with Context(FUSE_ARANGE=getenv("FUSE_ARANGE", 1)): - lst = [xt] if isinstance(xt, Tensor) else xt - s = Tensor.schedule(*lst) - lowered = [x[1] for x in lower_schedule(s.copy())] - kernels = [ei for ei in list(lowered) if isinstance(ei.prg, CompiledRunner)] - if FUSE_ARANGE: self.assertEqual(len(kernels), cnt) - for ei in lowered: ei.run(do_update_stats=True) - return s - - def test_simple_indexing(self): - X = Tensor.randn(10, 10).realize() - idxs = Tensor([0, 2]).realize() - xt = X[idxs] - self.check_schedule(xt, 2) - np.testing.assert_equal(xt.numpy(), X.numpy()[idxs.numpy()]) - - def test_simple_indexing_alt(self): - X = Tensor.arange(16).reshape(4, 4) - xt = X[[1, 2], [1, 2]] - self.check_schedule(xt, 5) - np.testing.assert_equal(xt.numpy(), (np.arange(16).reshape(4, 4))[[1, 2], [1, 2]]) - - def test_advanced_indexing(self): - X = Tensor.arange(10)+1 - xt = X[[0]] - self.check_schedule(xt, 2) - np.testing.assert_equal(xt.numpy(), (np.arange(10)+1)[[0]]) - - def test_advanced_indexing_alt(self): - X = Tensor.arange(6).reshape(3, 2)+1 - xt = X[[Tensor([2]), Tensor([1])]] - self.check_schedule(xt, 6) - np.testing.assert_equal(xt.numpy(), 6) - - def test_advanced_simple_indexing_combined(self): - X = Tensor.arange(16).reshape(4, 4) - xt = X[1:2, [1, 2]] - self.check_schedule(xt, 4) - - def test_push_through_reshape(self): - Tensor.manual_seed(0) - x = Tensor.randn(10, 20).realize() - out = x.argmax(1) - self.check_schedule(out, 2) - np.testing.assert_allclose(out.numpy(), np.argmax(x.numpy(), 1)) - - def test_arange_push_through_expand(self): - Tensor.manual_seed(0) - a = Tensor.arange(4,) - b = Tensor.randn(4, 4).realize() - out = (a+b).sum() - self.check_schedule(out, 1) - np.testing.assert_allclose(out.numpy(), (np.arange(4)+b.numpy()).sum(), atol=1e-5) - - def test_argmin(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - out = x.argmin(-1) - self.check_schedule(out, 2) - np.testing.assert_equal(out.numpy(), x.numpy().argmin(axis=-1)) - - def test_argmax(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 32).realize() - out = x.argmax(-1) - self.check_schedule(out, 2) - np.testing.assert_equal(out.numpy(), x.numpy().argmax(axis=-1)) - - def test_arange_transposed(self): - Tensor.manual_seed(0) - x = Tensor.randint(4, 1).realize() - a = ((Tensor.arange(4,)*x).T).sum() - self.check_schedule(a, 1) - np.testing.assert_equal(a.numpy(), (np.arange(4)*x.numpy()).T.sum()) - - def test_div_padded_arange(self): - x = Tensor.full((2,2), 16) - y = x.idiv(Tensor.linspace(2, 8, steps=4, dtype=dtypes.int).reshape(2,2)).pad(((1,1), (1,1))) - out = y.sum(axis=1) - with Context(FUSE_ARANGE=1): run_schedule(check_schedule(out, 2)) - self.assertListEqual(out.tolist(), [0, 12, 4, 0]) - - def test_arange_transposed_descendants(self): - Tensor.manual_seed(0) - x = Tensor.randint(4, 1).realize() - a = (Tensor.arange(4,)*x).T - b = Tensor.randint(4, 4).realize() - out = (a+b).sum() - self.check_schedule(out, 1) - np.testing.assert_equal(out.numpy(), ((np.arange(4)*x.numpy()).T+b.numpy()).sum()) - - def test_arange_index(self): - Tensor.manual_seed(0) - x = Tensor.randn(5, 2).realize() - a = Tensor.arange(10) - out = (x + a[2]).sum() - self.check_schedule(out, 1) - np.testing.assert_allclose(out.numpy(), (x.numpy()+np.arange(10)[2]).sum(), atol=1e-5, rtol=1e-6) - - def test_arange_index_shrink(self): - Tensor.manual_seed(0) - with Context(TRACK_MATCH_STATS=0): - x = Tensor.randn(11).realize() - a = Tensor.arange(22) - out = (x + a[:11]).sum() - self.check_schedule(out, 1) - - def test_arange_index_contiguous(self): - Tensor.manual_seed(0) - x = Tensor.randn(5, 2).realize() - a = Tensor.arange(10).contiguous() - out = (x + a[2]).sum() - self.check_schedule(out, 3) - np.testing.assert_allclose(out.numpy(), (x.numpy()+np.arange(10)[2]).sum(), atol=1e-5, rtol=1e-6) - - def test_arange_index_child(self): - Tensor.manual_seed(0) - x = Tensor.randn(5, 2).realize() - a = Tensor.arange(10)+1 - out = (x + a[2]).sum() - self.check_schedule(out, 1) - np.testing.assert_allclose(out.numpy(), (x.numpy()+(np.arange(10)+1)[2]).sum(), atol=1e-5, rtol=1e-6) - - def test_arange_index_contiguous_child(self): - Tensor.manual_seed(0) - x = Tensor.randn(5, 2).realize() - a = (Tensor.arange(10)+1).contiguous() - out = (x + a[2]).sum() - self.check_schedule(out, 3) - np.testing.assert_allclose(out.numpy(), (x.numpy()+(np.arange(10)+1)[2]).sum(), atol=1e-5, rtol=1e-6) - - def test_arange_childless_base(self): - a = Tensor.arange(4) - self.check_schedule(a, 1) - np.testing.assert_equal(a.numpy(), np.arange(4)) - - def test_arange_childless_view(self): - a = Tensor.arange(4).reshape(2, 2) - a[0] = 4 - np.testing.assert_equal(a.numpy(), [[4, 4], [2, 3]]) - - def test_arange_group_childless_base(self): - Tensor.manual_seed(0) - x = Tensor.randint(4).realize() - a = Tensor.arange(4)+x - self.check_schedule(a, 1) - np.testing.assert_equal(a.numpy(), np.arange(4)+x.numpy()) - - def test_arange_group_childless_view(self): - Tensor.manual_seed(0) - x = Tensor.ones(4).contiguous().realize() - a = Tensor.arange(4)+x - a[0] = 6 - np.testing.assert_equal(a.numpy(), [6., 2., 3., 4.]) - - @unittest.skip("BUFFER_VIEW no longer supported on non-disk devices") - def test_arange_view_op(self): - a = Tensor.arange(12).reshape(4, 3).shrink(((1, 2), (1, 3))).contiguous() - sched = self.check_schedule(a, 1) - self.assertIs(sched[1].ast.op, Ops.BUFFER_VIEW) - np.testing.assert_equal(a.numpy(), [[4, 5]]) - - @unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from ext device") - def test_arange_shrink_copy(self): - a = Tensor.arange(12).reshape(4, 3).shrink(((1, 2), (1, 3))).to("CPU") - sched = self.check_schedule(a, 2) # NOTE: there is a contiguous between REDUCE_AXIS and COPY - self.assertIs(sched[-1].ast.op, Ops.COPY) - np.testing.assert_equal(a.numpy(), [[4, 5]]) - - @unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from ext device") - def test_arange_expand_copy(self): - a = Tensor.arange(4).reshape(2, 2, 1).expand(2, 2, 2).contiguous().to("CPU") - sched = self.check_schedule(a, 2) # NOTE: there is a contiguous between REDUCE_AXIS and COPY - self.assertIs(sched[2].ast.op, Ops.COPY) - self.assertIs(store_val(sched[1]).op, Ops.LOAD) - self.assertIs(store_val(sched[0]).op, Ops.ADD) - np.testing.assert_equal(a.numpy(), [[[0, 0], [1, 1]], [[2, 2], [3, 3]]]) - - @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") - def test_precompute_freqs_cis(self): - from extra.models.llama import precompute_freqs_cis - args = {"dim":32 if CI else 128, "end":2048 if CI else 8192, "theta":10000} - fused = precompute_freqs_cis(**args) - with Context(FUSE_ARANGE=1): - run_schedule(check_schedule(fused, 3)) - if getenv("CHECK", 1): - ref = precompute_freqs_cis(**args) - run_schedule(check_schedule(ref, 3)) - np.testing.assert_equal(fused.numpy(), ref.numpy()) - - def test_fuse_assign_contiguous(self): - x = Tensor.zeros(4, 4, dtype=dtypes.int).contiguous().realize() - a = Tensor.arange(8).reshape(4, 2) - self.check_schedule(x.shrink((None, (0, 2))).assign(a.contiguous()), 2) - np.testing.assert_equal(x.numpy(), [[0, 1, 0, 0], [2, 3, 0, 0], [4, 5, 0, 0], [6, 7, 0, 0]]) - - def test_assign_non_contiguous(self): - x = Tensor.zeros(4, 4, dtype=dtypes.int).contiguous().realize() - y = Tensor.randint(4, 2) - a = Tensor.arange(8).reshape(4, 2)+y - x.shrink((None, (0, 2))).assign(a).realize() - xref = np.zeros((4, 4), dtype=int) - xref[:, :2] = np.arange(8).reshape(4, 2)+y.numpy() - np.testing.assert_equal(x.numpy(), xref) - - def test_sparse_categorical_crossentropy_simple(self): - X = Tensor([[0, 2, 3], [1, 2, 3]]).realize() - Y = Tensor([1, 2]).realize() - loss = X.sparse_categorical_crossentropy(Y) - self.check_schedule(loss, 4) - np.testing.assert_allclose(loss.item(), 0.878309, atol=1e-5, rtol=1e-6) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Validation error on WebGPU") - def test_mnist_val(self): - from tinygrad.nn.datasets import mnist - import torch - _, Y_train, _, _ = mnist() - samples = Tensor.randint(BS:=getenv("BS", 512), high=cast(int,Y_train.shape[-1])).realize() - yt = Tensor.randn(BS, 10).realize() - with Context(SPLIT_REDUCEOP=0): - loss = yt.sparse_categorical_crossentropy(Y_train[samples]) - self.check_schedule(loss, 6) - loss_fused = loss.numpy() - loss_ref = torch.nn.CrossEntropyLoss()(torch.tensor(yt.numpy()), torch.tensor(Y_train.numpy())[torch.tensor(samples.numpy())]) - np.testing.assert_allclose(loss_fused, loss_ref.numpy(), atol=1e-6, rtol=1e-6) - - @unittest.expectedFailure - def test_arange_fuse_grouped_children(self): - X = Tensor.randn(4, 4).realize() - r = (X+Tensor.arange(16).reshape(4, 4)).sum() - out0 = r+2 - out1 = r+3 - self.check_schedule([out0, out1], 1) - r_ref = (X.numpy()+np.arange(16).reshape(4, 4)).sum() - np.testing.assert_allclose(out0.numpy(), r_ref+2, rtol=2e-7) - np.testing.assert_allclose(out1.numpy(), r_ref+3, rtol=2e-7) - - def test_dont_fold_arange_contiguous_view(self): - X = Tensor.randn(4, 4).realize() - r = (X+Tensor.arange(16).reshape(4, 4).contiguous()).sum(1, keepdim=True) - self.check_schedule([r], 2) - np.testing.assert_allclose(r.numpy(), (X.numpy()+np.arange(16).reshape(4, 4)).sum(1, keepdims=True), atol=1e-5, rtol=1e-6) - - @unittest.skip("multi output isn't supported") - def test_multiview_arange_children(self): - X = Tensor.randn(2,3,4,4).numpy() - with Context(FUSE_ARANGE=1): - compare = Tensor(X).interpolate(size=(2, 2), mode="linear").numpy() - with Context(FUSE_ARANGE=0, TRACK_MATCH_STATS=0): - ref = Tensor(X).interpolate(size=(2, 2), mode="linear").numpy() - np.testing.assert_allclose(ref, compare, atol=1e-5, rtol=1e-6) - - def test_recursive_swizzle(self): - a = Tensor([1,2,3,4]).realize() - for _ in range(24): a = a + a - new_uop = swizzle_rewrite(a.uop.reshape((4, 1))) - self.assertEqual(new_uop.st, ShapeTracker.from_shape((4,)).reshape((4, 1))) - self.assertEqual(swizzle_cnt(new_uop), 0) - - def test_no_rewrite_elementwise(self): - a = Tensor.empty(32, 32) - b = Tensor.empty(32, 32) - sink = (a+b).schedule()[0].ast - self.assertEqual(swizzle_cnt(sink), 0) - - def test_simple_store_reshape(self): - a = Tensor.empty(32, 32).sum(axis=1)+Tensor.empty(1,32) - ast = a.schedule()[0].ast - self.assertEqual(ast.shape, (32, 1)) - self.assertEqual(a.uop.shape, (1, 32)) - - def test_no_reshape_reduceop(self): - a = Tensor.empty(32, 32).sum(axis=(1,)).contiguous() - ast = a.schedule()[0].ast - self.assertEqual(ast.shape, (32, 1)) - self.assertEqual(a.uop.shape, (32,)) - -@track_rewrites(named=True) -def swizzle_rewrite(u:UOp) -> UOp: return graph_rewrite(graph_rewrite(u, view_left), view_right) -def swizzle_cnt(u:UOp) -> int: - return len([x for x in u.toposort() if x.op is Ops.VIEW and len(x.src) != 0 and x.src[0].op not in {Ops.BUFFER, Ops.DEFINE_GLOBAL}]) - -class TestSwizzle(unittest.TestCase): - def test_swizzle_simple(self): - Tensor.manual_seed(0) - with Context(DEBUG=0, TRACK_MATCH_STATS=0): - a = Tensor.randint(32, 32).realize() - r = (a+a).sum(1).sum(0) - # double reduce collapses to a single reduce - with Context(DONT_GROUP_REDUCES=1): - run_schedule(check_schedule(r, 1)) - self.assertEqual(r.numpy(), (a.numpy()+a.numpy()).sum(1).sum(0)) - - def test_single_swizzle(self): - Tensor.manual_seed(0) - with Context(DEBUG=0, TRACK_MATCH_STATS=0): - a = Tensor.randint(4, 1).realize() - b = Tensor.ones((1, 1), dtype=a.dtype).contiguous().realize() - # ADD(REDUCE(RESHAPE(LOAD)), LOAD) to ADD(REDUCE(RESHAPE(LOAD))), RESHAPE(LOAD) - r = a.sum(0)+b - run_schedule(check_schedule(r, 1)) - self.assertEqual(r.numpy(), a.numpy().sum(0)+1) - - def test_double_swizzle_possible(self): - Tensor.manual_seed(0) - with Context(DEBUG=0, TRACK_MATCH_STATS=0): - a = Tensor.randint(4,).realize() - b = Tensor.randint(4,).realize() - # parallel reduce! - add = a.sum(0)+b.sum(0) - with Context(DONT_GROUP_REDUCES=1): - run_schedule(check_schedule(add, 1)) - self.assertEqual(add.numpy(), a.numpy().sum(0)+b.numpy().sum(0)) - - @unittest.skip("TODO: how do we express the norm") - def test_softmax_one_kernel(self): - Tensor.manual_seed(0) - with Context(DEBUG=0, TRACK_MATCH_STATS=0): - a = Tensor.randn(32, 32).realize() - t = a.softmax() - with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): - check_schedule(t, 1) - - def test_argmax_one_kernel(self): - Tensor.manual_seed(0) - with Context(DEBUG=0, TRACK_MATCH_STATS=0): - a = Tensor.randn(10, 20).realize() - t = a.argmax(0) - with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): t.realize() - - def test_swizzle_reduceop(self): - Tensor.manual_seed(0) - x = Tensor.randn(4,4).realize() - y = Tensor.randn(4,4,4).realize() - out = x.reshape(4,4,1).expand(4,4,4).sum(axis=(1,))+y - with Context(DONT_REALIZE_EXPAND=1, DONT_GROUP_REDUCES=1): - run_schedule(check_schedule(out, 1)) - np.testing.assert_allclose(out.numpy(), np.tile(x.numpy().reshape(4,4,1), (1,1,4)).sum(axis=1)+y.numpy()) - - def test_permute_rewrite(self): - x = Tensor.randn(4, 4, 16).realize() - y = Tensor.randn(4, 1, 16).realize() - z = Tensor.randn(4, 4, 1).realize() - t = (x*y).sum(axis=(0, 2)).reshape(1, 4, 1).permute(0, 2, 1)+z - with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): run_schedule(check_schedule(t, 1)) - t_np = (x.numpy()*y.numpy()).sum(axis=(0, 2)).reshape(1, 4, 1).transpose(0, 2, 1)+z.numpy() - np.testing.assert_allclose(t.numpy(), t_np, atol=1e-6, rtol=1e-3) - - @unittest.skip("TODO: this swizzle isn't resolvable when there's a mask") - def test_swizzle_failure_permute(self): - a = Tensor.empty(45,65).T.reshape(65,1,45).pad((None,None,(0,45))).expand(65,45,90) - b = Tensor.empty(45,65) - a_reduce = a.sum(axis=(2,), keepdim=True).sum(axis=(1,)) - b_reduce = b.sum(axis=(0,)) - t = a_reduce+b_reduce - with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): run_schedule(check_schedule(t, 1)) - - def test_parallel_reduce_possible(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 2, 2).realize() - y = Tensor.randn(4, 2, 2).realize() - t = x.sum(axis=1)+y.sum(axis=1) - with Context(DONT_GROUP_REDUCES=1): run_schedule(check_schedule(t, 1)) - np.testing.assert_allclose(t.numpy(), x.numpy().sum(axis=1)+y.numpy().sum(axis=1), atol=1e-6, rtol=1e-3) - - # kernels can only have 1 or n in each dim - @unittest.expectedFailure - def test_dont_parallelize_different_n(self): - Tensor.manual_seed(0) - x = Tensor.randn(4, 2, 2).realize() - y = Tensor.randn(4, 3, 2).realize() - t = x.sum(axis=1)+y.sum(axis=1) - with Context(DONT_GROUP_REDUCES=1): run_schedule(check_schedule(t, 1)) - np.testing.assert_allclose(t.numpy(), x.numpy().sum(axis=1)+y.numpy().sum(axis=1), atol=1e-6, rtol=1e-3) - - def test_unsafe_pad(self): - x = Tensor.full((2,2), 1.0).contiguous() - y = x*x.sum((1,)).reciprocal() - t = y.pad(((0,1),None)) - run_schedule(check_schedule(t, 3)) - np.testing.assert_equal(t.numpy(), [[0.5, 0.5], [0.5, 0.5], [0., 0.]]) - -def store_val(si:ScheduleItem): return si.ast.src[0].src[1] -zero_pm = UPat(Ops.CONST, arg=0) -class TestView(unittest.TestCase): - def test_all_masked_out(self): - # start with non CONST Ops - a = Tensor.rand(10, 10).realize() - # all masked out, degrades to const 0 - b = a.pad(((0, 10), None))[10:] - sched = check_schedule(b.contiguous(), 1) - assert zero_pm.match(store_val(sched[-1]), {}) - run_schedule(sched) - np.testing.assert_equal(b.numpy(), 0) - - def test_mask_dim_1(self): - # mask out dim = 1 works too - a = Tensor.rand(10, 10).realize() - b = a.pad((None, (0, 10)))[:, 10:] - assert b.shape == (10, 10) - sched = check_schedule(b.contiguous(), 1) - self.assertEqual(sched[-1].ast.full_shape, (10, 10)) - assert zero_pm.match(store_val(sched[-1]), {}) - run_schedule(sched) - np.testing.assert_equal(b.numpy(), 0) - - def test_zero_size_alt(self): - a = Tensor.empty(135, 0, 9) - b = a.pad(((0, 0), (0, 0), (18, 0))) - check_schedule(b, 0) - - def test_partial_mask(self): - # partial masked out does not degrade into CONST - a = Tensor.rand(10, 10).realize() - b = a.pad(((0, 5), None))[5:] - assert b.shape == (10, 10) - sched = check_schedule(b.contiguous(), 1) - self.assertEqual(store_val(sched[-1]).op, Ops.LOAD) - self.assertEqual(store_val(sched[-1]).st_arg, b.uop.st) - run_schedule(sched) - np.testing.assert_allclose(b.numpy(), np.pad(a.numpy(), ((0, 5), (0, 0)))[5:]) - - # a*VIEW(x), where VIEW(x) = 0 - # x collapses along with its children - def test_parent_view_collapses(self): - a = Tensor([1, 2]) - b = Tensor.arange(3).contiguous() - bv = b.pad(((0, 2),))[-2:] - # this becomes a late a*0 - late_mul = a*bv - check_schedule(late_mul, 0) - # the arange doesn't realize - self.assertIsNone(b.uop.base.realized) - # mul doesn't realize - self.assertIsNone(late_mul.uop.base.realized) - self.assertEqual(late_mul.tolist(), [0, 0]) - - # SINK has two branches: - # a*VIEW(x), where VIEW(x) = 0 - # x+2 - # as long as one child realizes, x does not collapse - def test_parent_multiple_children_no_collapse(self): - a = Tensor([1, 2]) - b = Tensor.arange(3).contiguous() - bv = b.pad(((0, 2),))[-2:] - late_mul = a*bv - other_child = b+2 - s = check_schedule([late_mul, other_child], 2) - # the arange becomes a BUFFER - self.assertIs(b.uop.base.op, Ops.BUFFER) - # mul still collapses - self.assertIs(late_mul.uop.base.op, Ops.CONST) - run_schedule(s) - self.assertEqual(other_child.tolist(), [2, 3, 4]) - -def tensor_rewrite(t) -> UOp: return graph_rewrite(t.uop.base, merge_views+symbolic_simple) -class TestSimplifier(unittest.TestCase): - def test_sink_childless_const(self): - x = Tensor(0) - check_schedule(x, 0) - - def test_sink_childless_const_alt_expanded(self): - x = Tensor.zeros(4, 4).contiguous() - check_schedule(x, 1) - - def test_all_const_uops(self): - a = Tensor(4)*Tensor(2) - sink = tensor_rewrite(a) - assert UPat.cvar().match(sink, {}) - - def test_masked_const_elementwise(self): - a = Tensor.eye(10)@Tensor.eye(10) - sink = tensor_rewrite(a) - assert UPat(Ops.REDUCE_AXIS, src=(UPat.cvar().view()*UPat.cvar().view(),)).match(sink, {}) - - def test_elementwise_ops(self): - a = Tensor.empty(4, 4, dtype=dtypes.int) - sink = tensor_rewrite(a*0) - assert UPat(Ops.CONST, arg=0).match(sink, {}) - self.assertIs(tensor_rewrite(a*1).base, a.uop.base) - self.assertIs(tensor_rewrite(a+0).base, a.uop.base) - - def test_cast_folding(self): - a = Tensor(1.0).cast(dtypes.int) - sink = tensor_rewrite(a) - assert UPat.cvar(dtype=dtypes.int).match(sink, {}) - - def test_const_folding_mul(self): - a = Tensor([1]) - sink = tensor_rewrite(a*0) - assert UPat(Ops.CONST, arg=0).match(sink, {}), f"expected {sink} to collapse to a const 0" - assert sink.shape == a.shape - - def test_const_folding_ne(self): - a = Tensor([1]) - sink = tensor_rewrite(a != a) - assert UPat(Ops.CONST, arg=False).match(sink, {}), f"expected {sink} to collapse to a const False" - assert sink.shape == a.shape - - def test_const_folding_lt(self): - a = Tensor([1]) - sink = tensor_rewrite(a < a) - assert UPat(Ops.CONST, arg=False).match(sink, {}), f"expected {sink} to collapse to a const False" - assert sink.shape == a.shape - -tensor_const_pm = PatternMatcher([ - (UPat(Ops.CONST, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),)),)), lambda: True), - (UPat(Ops.BIND, src=(UPat(Ops.DEFINE_VAR, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),)))), UPat(Ops.CONST))), lambda: True), -]) -class TestConst(unittest.TestCase): - # ** part 1: basic functionality of a tensor directly created from CONST - - def test_tensor_const(self): - a = Tensor(1) - print(a.uop) - self.assertTrue(tensor_const_pm.rewrite(a.uop)) - - def test_tensor_variable(self): - vv = UOp.variable("a", 0, 10).bind(1) - a = Tensor(vv) - print(a.uop) - self.assertTrue(tensor_const_pm.rewrite(a.uop)) - - def test_const_schedule(self): - a = Tensor.ones((4, 4)) - sched = a.schedule() - self.assertEqual(len(sched), 0) - - def test_const_contiguous_schedule(self): - # this ends up in the big graph - a = Tensor.ones((4,)).contiguous() - sched = a.schedule() - self.assertEqual(len(sched), 1) - - def test_const_ast(self): - a = Tensor.ones((4,)).pad((1, 1)).contiguous() - sched = a.schedule() - print(sched[0].ast) - const_ast_pattern = UPat(Ops.SINK, src=(UPat.store(UPat(), UPat.where(UPat(Ops.VALID), UPat.cvar("x"), UPat(Ops.CONST, arg=0))),)) - self.assertEqual(len(const_ast_pattern.match(sched[0].ast, {})), 1) - run_schedule(sched) - self.assertListEqual(a.tolist(), [0, 1, 1, 1, 1, 0]) - - def test_unmasked_const_ast(self): - a = Tensor.ones((4,)).contiguous() - sched = a.schedule() - print(sched[0].ast) - const_ast_pattern = UPat(Ops.SINK, src=(UPat.store(UPat(), UPat(Ops.CONST)),)) - self.assertEqual(len(const_ast_pattern.match(sched[0].ast, {})), 1) - run_schedule(sched) - self.assertListEqual(a.tolist(), [1, 1, 1, 1]) - - # ** part 2: scheduler behavior when const folding happens later - - def test_const_folding_no_realize(self): - a = Tensor([1, 2, 3, 4])*0 - sched = a.schedule() - self.assertEqual(len(sched), 0) - - def test_src_const_folding(self): - with Context(TRACK_MATCH_STATS=0): - a = Tensor.full((4,), 1).contiguous().realize() - b = Tensor.full((4,), 2).contiguous().realize() - mul0 = a*0 - add = b+mul0 - sched = add.schedule() - self.assertEqual(len(sched), 0) - # b+0 and b share the same underlying device memory - self.assertIs(add.uop.buffer, b.uop.buffer) - self.assertListEqual(add.tolist(), [2, 2, 2, 2]) - - def test_src_masked_const_folding(self): - with Context(TRACK_MATCH_STATS=0): - a = Tensor.full((4,), 1).contiguous().realize() - b = Tensor.full((6,), 2).contiguous().realize() - mul0 = a*0 - add = b+mul0.pad((1, 1), value=2) - sched = add.schedule() - self.assertEqual(len(sched), 1) - run_schedule(sched) - # add gets assigned to a new buffer - self.assertIsNot(add.uop.base.realized, b.uop.base.realized) - self.assertListEqual(add.tolist(), [4, 2, 2, 2, 2, 4]) - - # ** part 3: Tensor variable bindings - - #@unittest.expectedFailure # TODO: should schedule assert if you try to realize a Variable? - def test_var_schedule(self): - vv = UOp.variable("a", 0, 10).bind(1) - a = Tensor(vv) - sched = a.schedule() - self.assertEqual(len(sched), 0) - - def test_add_tvar(self): - vv = UOp.variable("a", 0, 10).bind(1) - a = Tensor(vv)+2 - sched, var_vals = a.schedule_with_vars() - self.assertEqual(len(sched), 1) - run_schedule(sched, var_vals) - self.assertEqual(a.tolist(), 3) - -@unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from another device to cpu") -class TestCopyFolding(unittest.TestCase): - def test_const_copy_is_free(self): - b = Tensor(1).to("CPU") - check_schedule(b, 0, filter_sink=False) - assert b.item() == 1 - - def test_late_const_copy_folding(self): - a = Tensor.arange(3).realize() - zeros = Tensor.zeros(3).realize() - b = (a*zeros).to("CPU") - run_schedule(check_schedule(b, 0, filter_sink=False)) - self.assertListEqual(b.tolist(), [0, 0, 0]) - - def test_alu_after_copy(self): - a = Tensor.ones((4,)).to("CPU").uop - b = Tensor.empty(4, device="CPU").uop - add = a+b - add = schedule_graph_rewrite(add) - assert all_same([x.device for x in add.src]), f"ALU has different devices! {[x.device for x in add.src]}" - - @unittest.skip("this is just clone now") - def test_copy_to_same_device(self): - a = Tensor.empty(4).uop - b = a.copy_to_device(a.device) - check_schedule(b, 0, filter_sink=False) - b = schedule_graph_rewrite(b) - # NOTE: Tensor.empty(4) always creates a VIEW(BUFFER) with ShapeTracker((4,)), we simplify this to jsut a BUFFER - # in the scheduler because buffer already has shape (4,) - self.assertIs(b, a.base) - - @unittest.skip("this is just clone now") - def test_copy_to_same_device_alt(self): - a = Tensor.empty(4, 4).uop - b = a.copy_to_device(a.device) - check_schedule(b, 0, filter_sink=False) - b = schedule_graph_rewrite(b) - self.assertIs(b.base, a.base) - - def test_clone(self): - a = Tensor.empty(4) - check_schedule(a.clone(), 1, filter_sink=False) - - # NOTE: moving copy before view might change this - def test_shrink_copy(self): - a = Tensor.arange(4) - view = a.shrink(((0, 2),)) - b = view.clone() - # NOTE: this was sort of a bug making this 2 - run_schedule(check_schedule(b, 2, filter_sink=False)) - self.assertEqual(b.uop.base.buffer.size, 2) - self.assertEqual(b.uop.size, 2) - self.assertListEqual(b.tolist(), [0, 1]) - - def test_expanded_copy(self): - a = Tensor.arange(2) - view = a.reshape(2, 1).expand(2, 2) - b = view.clone() - run_schedule(check_schedule(b, 2, filter_sink=False)) - self.assertEqual(b.uop.base.buffer.size, 4) - self.assertEqual(b.uop.size, 4) - self.assertListEqual(b.tolist(), [[0, 0], [1, 1]]) - - def test_permuted_copy(self): - a = Tensor.arange(4) - b = a.reshape(2, 2).permute(1, 0) - b.realize() - self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) - - def test_permute_on_disk(self): - with open(temp('dt_arange_4_permute'), "wb") as f: f.write(Tensor.arange(4).realize().uop.base.buffer.as_buffer()) - a = Tensor.empty(4, dtype=dtypes.int32, device=f"disk:{temp('dt_arange_4_permute')}") - b = a.reshape(2, 2).permute(1, 0).to("CPU") - b.realize() - self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) - - def test_permute_after_shrink(self): - a = Tensor.arange(5) - b = a.shrink(((0, 4),)).reshape(2, 2).permute(1, 0).to("CPU") - b.realize() - self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) - - # NOTE: disk permute must come after COPY - # TODO: this is wrong because of the permute - @unittest.expectedFailure - def test_permute_after_shrink_on_disk(self): - with open(temp('dt_arange_5_permute'), "wb") as f: f.write(Tensor.arange(5).realize().uop.base.buffer.as_buffer()) - a = Tensor.empty(5, dtype=dtypes.int32, device=f"disk:{temp('dt_arange_5_permute')}") - b = a.shrink(((0, 4),)).reshape(2, 2).permute(1, 0).to("CPU") - b.realize() - self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) - -class TestTensorUOpSpec(unittest.TestCase): - def test_const_must_be_unmasked(self): - a = Tensor.ones((4, 4)).pad((2, 2)) - unsafe_push_views = PatternMatcher([ - (UPat.cvar("root").view(name="view"), lambda root,view: root.replace(src=tuple(x.view(view.st) for x in root.src))), - ]) - a.uop = graph_rewrite(a.uop.sink(), merge_views+merge_views+unsafe_push_views) - with self.assertRaisesRegex(RuntimeError, "UOp verification failed"): - a.schedule() - - def test_expanded_const_ok(self): - a = Tensor.ones((4, 4)) - t = graph_rewrite(a.uop.sink(), merge_views+merge_views) - create_schedule_with_vars(t) - - # NOTE: changing symbolic CONST VIEWs is not allowed - @unittest.expectedFailure - def test_symbolic_shape_ok(self): - a = Tensor.ones(4) - vi = UOp.variable("i", 1, 10).bind(4) - a.uop = graph_rewrite(a.reshape(vi).sum().uop, merge_views+merge_views) - a.schedule() - -class TestBufferUOp(unittest.TestCase): - # BUFFER has a ShapeTracker of shape=(n,) and stride=(1,) - def test_buffer_has_buffer(self): - buf = Tensor.empty(10) - self.assertIsNotNone(buf.uop.buffer) - self.assertEqual(buf.uop.st, ShapeTracker.from_shape((10,))) - # the device Buffer remains unallocated until it's we run the schedule - self.assertFalse(buf.uop.buffer.is_allocated()) - add = buf+1 - sched = add.schedule() - self.assertFalse(buf.uop.buffer.is_allocated()) - run_schedule(sched) - self.assertTrue(buf.uop.buffer.is_allocated()) - - def test_buffer_has_unique_buffer(self): - buf = Tensor.empty(10) - buf1 = buf.uop.buffer - buf2 = buf.uop.buffer - self.assertIs(buf1, buf2) - - # we also allow VIEW(BUFFER) to access the underlying device Buffer, as long as it's contiguous - def test_buffer_view_allowed(self): - add = Tensor.empty(1, 1)+Tensor.empty(1, 1) - add.realize() - self.assertIsNotNone(add.uop.buffer) - self.assertEqual(add.uop.shape, (1, 1)) - - def test_buffer_view_not_allowed(self): - permuted_view = Tensor.empty(1, 2, 3).permute(0, 2, 1) - merged = graph_rewrite(permuted_view.uop, merge_views) - with self.assertRaisesRegex(AssertionError, "VIEW only works here if it's contiguous"): - merged.buffer # cannot access Buffer of a non contiguous VIEW - - def test_buffer_only_after_realize(self): - a = Tensor([1])+Tensor([2]) - # accessing realized will return None - self.assertIsNone(a.uop.realized) - # accessing Buffer will assert - with self.assertRaisesRegex(AssertionError, "must be BUFFER"): - a.uop.buffer # there is no BUFFER on an unrealized ADD - # Buffer only exists once we realize it - a.realize() - self.assertIsNotNone(a.uop.buffer) - - def test_const_does_not_realize(self): - a = Tensor(1)+Tensor(2) - run_schedule(check_schedule(a, 0)) - self.assertIsNone(a.uop.base.realized) - - def test_var_does_not_realize(self): - a = Tensor(UOp.variable("a", 0, 10).bind(1)) - run_schedule(check_schedule(a, 0)) - self.assertIsNone(a.uop.base.realized) - - def test_view_does_not_realize(self): - a = Tensor.randn(1, 4).expand(4, 4) - a.realize() - self.assertEqual(a.uop.base.realized.size, 4) - a2 = a.contiguous().realize() - self.assertEqual(a2.uop.base.realized.size, 16) - -class TestContiguous(unittest.TestCase): - def test_contiguous_buffer(self): - a = Tensor.empty(4) - b = a.contiguous() - check_schedule(b, 0) - - def test_contiguous_buffer_view(self): - a = Tensor.empty(4) - b = a.reshape((2, 2)).contiguous() - check_schedule(b, 0) - - def test_non_contiguous_buffer_view(self): - a = Tensor.empty(4, 1) - b = a.expand((4, 4)).contiguous() - check_schedule(b, 1) - - def test_size_change_buffer_view(self): - a = Tensor.empty(4) - b = a.reshape((1, 1, 4)).shrink(((0, 1), (0, 1), (0, 3))).contiguous() - check_schedule(b, 1) - - def test_double_contiguous_realizes_once(self): - a = Tensor.empty(4, 1) - b = a.expand((4, 4)).contiguous().contiguous() - check_schedule(b, 1) - - def test_view_does_not_realize(self): - a = Tensor.empty(4) - b = a.expand((4, 4)) - check_schedule(b, 0) - self.assertEqual(b.uop.base.buffer.size, 4) - - def test_contiguous_view_realizes(self): - a = Tensor.empty(4) - b = a.expand((4, 4)).contiguous() - check_schedule(b, 1) - self.assertEqual(b.uop.base.buffer.size, 16) - -class TestUOpBecome(unittest.TestCase): - # the simplest case, if we create a new BUFFER for this tensor UOp - def test_new_buffer(self): - a = Tensor.empty(4, 4) - b = Tensor.empty(4, 4) - add = a+b - check_schedule(add, 1) - # NOTE: realized base is always a flat buffer - assert UPat(Ops.BUFFER).match(add.uop.base, {}) - # the Tensor UOp can optionally stack a VIEW on top of the BUFFER, in this case to preserve the (4, 4) shape of the tensor - assert add.uop is not add.uop.base - self.assertEqual(add.uop.size, 16) - self.assertEqual(add.uop.shape, (4, 4)) - - def test_new_buffer_view(self): - a = Tensor.empty(4, 4) - b = Tensor.empty(4, 4) - add = (a+b).reshape(8, 2) - check_schedule(add, 1) - assert UPat(Ops.BUFFER).match(add.uop.base, {}) - # the shape is preserverd in the becomes_map. - self.assertEqual(add.uop.shape, (8, 2)) - assert add.uop is not add.uop.base - - def test_new_flat_buffer(self): - a = Tensor.empty(4,) - b = Tensor.empty(4,) - add = a+b - check_schedule(add, 1) - # BUFFER already has a shape (4,), this tensor just becomes a contiguous BUFFER - assert UPat(Ops.BUFFER).match(add.uop, {}) - - # sometimes we prefer to perform an op before movement ops, in this case we should stack the mops on top of the new buffer - - # NOTE: this expand is not reordered because there's before it to fuse - def test_reorder_expand(self): - a = Tensor.empty(4, 1) - b = a.expand(4, 4).reciprocal() - check_schedule(b, 1) - self.assertEqual(b.uop.base.buffer.size, 16) - self.assertEqual(b.uop.st, ShapeTracker.from_shape((4, 4))) - - def test_reorder_expand_alt(self): - x = Tensor.empty(4, 1) - y = Tensor.empty(4, 1) - img = Tensor.empty(4, 4) - z = (img*x) / y - check_schedule(z, 1) - - def test_become_existing_buffer(self): - a = Tensor.empty(4, 4) - b = a*1 - assert UPat(Ops.MUL).match(b.uop, {}) # before scheduling it's a mul - check_schedule(b, 0) - assert UPat(Ops.VIEW, src=(UPat(Ops.BUFFER))).match(b.uop, {}) # scheduling merges all MovementOps into a single VIEW - self.assertIs(a.uop.base.buffer, b.uop.base.buffer) - - def test_become_buf_with_mops(self): - a = Tensor.empty(2, 4, 2) - noop = a.shrink(((1, 2), (0, 4), (0, 2))).reshape(4, 2)*1+0 - # before realizing, this tensor is base - assert noop.uop is noop.uop.base - noop.realize() - # it becomes a realized view after realize - assert noop.uop is not noop.uop.base - assert noop.uop.base.op is Ops.BUFFER - late_add = noop+2 - late_add.realize() - - def test_become_const_in_base(self): - a = Tensor.empty(4) - b = a*0 - assert UPat(Ops.MUL).match(b.uop, {}) # before scheduling it's a mul - check_schedule(b, 0) - assert UPat(Ops.CONST, arg=0).match(b.uop.base, {}) # scheduling replaces the tensor uop with a VIEW(BUFFER) - - def test_become_const_in_view(self): - # if we shrink the base down to a size 0, only the VIEW becomes CONST, base is unchanged. - add = Tensor.empty(2, 2)+Tensor.empty(2, 2) - b = add.shrink(((0, 1), (0, 0))) - check_schedule(b, 0) - assert UPat(Ops.CONST, arg=0).match(b.uop, {}) - self.assertEqual(b.shape, (1, 0)) - # the base is untouched. - assert UPat(Ops.ADD).match(add.uop, {}) - - def test_become_const_from_const(self): - const_add = Tensor(1)+Tensor(2) - assert UPat(Ops.ADD).match(const_add.uop, {}) - check_schedule(const_add, 0) - assert UPat(Ops.CONST, arg=3).match(const_add.uop.base, {}) - - # tensors can become another realized tensor source - def test_become_existing_buf_simple(self): - a = Tensor.empty(4, 4) - b = a+0 - check_schedule(b, 0) - assert b.uop.base.op is Ops.BUFFER - self.assertIs(a.uop, b.uop) - - # they can also chain other movement ops on top of the tensor source - def test_become_existing_buf_view(self): - a = Tensor.empty(4, 4) - b = a.permute((1, 0))+0 - check_schedule(b, 0) - self.assertEqual(b.uop.st, a.uop.permute((1, 0)).st) - - def test_become_existing_buf_view_alt(self): - a = Tensor.empty(4, 4) - b = a.permute((1, 0)).reshape((8, 2))+0 - check_schedule(b, 0) - self.assertEqual(b.uop.st, a.uop.permute((1, 0)).reshape((8, 2)).st) - - # they can also have other base parents that simplified, in that case we just backtrack to the chained mops - def test_become_existing_buf_complex(self): - a = Tensor.empty(4, 4) - b = (a.permute((1, 0))+0).reshape((8, 2))+0 - check_schedule(b, 0) - self.assertEqual(b.uop.st, a.uop.permute((1, 0)).reshape((8, 2)).st) - assert b.uop.base.op is Ops.BUFFER - - def test_become_multiple_choices(self): - a = Tensor.empty(16) - b = (a.reshape(1, 1, 4, 1, 4)+0).reshape(1, 1, 4, 4).shrink(((0, 1), (0, 1), (0, 3), (0, 3)))+0 - c = (a.reshape(1, 1, 4, 4)+0).shrink(((0, 1), (0, 1), (0, 3), (0, 3)))+0 - check_schedule([b, c], 0) - assert all_same([x.uop.base.realized for x in [a,b,c]]) - # these movement ops result in the same ShapeTracker - assert b.uop.st == c.uop.st - assert b.uop is c.uop - assert UPat(Ops.VIEW, src=(UPat(Ops.BUFFER),)).match(c.uop, {}) - - def test_setitem_becomes_subbuffer(self): - a = Tensor.full((4,), 2.).contiguous().realize() - b = a.shrink(((0, 2),)).assign(Tensor.full((2,), 1.0)) - b.realize() - assert a.uop.is_realized - assert a.uop.buffer._base is None - # b is a subbuffer of a - assert b.uop.op is Ops.BUFFER_VIEW - assert b.uop.src[0] is a.uop - - def test_setitem_offset(self): - a = Tensor.full((16,), 0.).contiguous().realize() - b = Tensor.full((16,), 1.).contiguous().realize() - a_view = a[4:].reshape(3, 4).shrink(((0,2),(0,2))).reshape((4,)) - b.shrink(((0,4),)).assign(a_view).realize() - self.assertListEqual(b.tolist(), [0.0, 0.0, 0.0, 0.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_search.py b/tinygrad/test/test_search.py deleted file mode 100644 index cf430ef0..00000000 --- a/tinygrad/test/test_search.py +++ /dev/null @@ -1,180 +0,0 @@ -import unittest - -from tinygrad.codegen.kernel import Opt, OptOps -from tinygrad.codegen.kernel import Kernel -from tinygrad.uop.ops import UOp, Ops -from tinygrad.engine.search import bufs_from_lin, actions, beam_search -from tinygrad.device import Device, Buffer -from tinygrad.tensor import Tensor -from tinygrad.dtype import dtypes -from tinygrad.helpers import Context, GlobalCounters -from tinygrad.engine.realize import capturing -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from extra.optimization.helpers import time_linearizer - -class TestTimeLinearizer(unittest.TestCase): - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WebGPU timestamps are low precision, tm is 0") - def test_reasonable_time(self): - a = Tensor([1,2,3,4]).realize() - si = (a+1).schedule()[0] - # create fresh empty buffers - rawbufs = [Buffer(b.device, b.size, b.dtype).allocate() for b in si.bufs] - tm = time_linearizer(Kernel(si.ast), rawbufs, allow_test_size=False, cnt=10, disable_cache=True) - assert tm > 0 and tm != float('inf') - - def test_bufs_from_lin(self): - a = Tensor([1,2,3,4]).realize() - si = (a+1).schedule()[0] - rawbufs = bufs_from_lin(lin:=Kernel(si.ast)) - assert len(rawbufs) == len(lin.membufs) == 2 - assert all(r is not None for r in rawbufs) - assert all(isinstance(r, Buffer) for r in rawbufs) - assert all(r.size > 0 for r in rawbufs) - - def test_bufs_from_lin_alt(self): - a = Tensor.randn(4, 4).realize() - b = a+a[0] - si = b.schedule()[0] - rawbufs = bufs_from_lin(k:=Kernel(si.ast)) - assert len(rawbufs) == len(k.membufs) == 2 - assert all(r is not None for r in rawbufs) - assert all(isinstance(r, Buffer) for r in rawbufs) - assert all(r.size > 0 for r in rawbufs) - - # Ensure that the kernel count is not incremented by time_linearizer when clearing l2 - def test_kernel_count(self): - ast = Tensor.zeros(16).contiguous().kernelize().uop.src[1].arg.ast - lin = Kernel(ast) - bufs = bufs_from_lin(lin) - - kernel_count = GlobalCounters.kernel_count - time_linearizer(lin, bufs, allow_test_size=False, cnt=2, disable_cache=True, clear_l2=True) - assert GlobalCounters.kernel_count == kernel_count, "kernel count was incremented by time_linearizer" - -class TestBEAM(unittest.TestCase): - def test_dynamic_beam(self): - # TODO: make this infra globally usable - class Capture: - def __init__(self): self.captured = [] - def add(self, x): self.captured.append(x) - - capturing.append(Capture()) - kernel_count = GlobalCounters.kernel_count - with Context(BEAM=1): Tensor.zeros(16).contiguous().realize() - assert GlobalCounters.kernel_count == kernel_count + 1 - k_beam_1 = capturing[0].captured - capturing.clear() - - capturing.append(Capture()) - kernel_count = GlobalCounters.kernel_count - with Context(BEAM=0): Tensor.zeros(16).contiguous().realize() - assert GlobalCounters.kernel_count == kernel_count + 1 - k_beam_0 = capturing[0].captured - capturing.clear() - self.assertNotEqual(k_beam_0[-1].prg.p.src, k_beam_1[-1].prg.p.src) - - def test_get_kernel_actions(self): - from test.test_linearizer import helper_realized_ast - a = Tensor.rand(4, 3) - b = Tensor.rand(3) - realized_ast, _ = helper_realized_ast(a @ b) - from tinygrad.engine.search import get_kernel_actions - lins = get_kernel_actions(Kernel(realized_ast), False).values() - - # ensure amt=0 are not duplicated - if Opt(OptOps.UPCAST, 0, 0) in actions: - assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.UPCAST, axis=0, arg=4)]) == 0, "did not de-dup UPCAST" - if Opt(OptOps.LOCAL, 0, 0) in actions: - assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.LOCAL, axis=0, arg=4)]) == 0, "did not de-dup LOCAL" - if Opt(OptOps.UNROLL, 0, 0) in actions: - assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.UNROLL, axis=0, arg=3)]) == 0, "did not de-dup UNROLL" - if Opt(OptOps.GROUP, 0, 0) in actions: - assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.GROUP, axis=0, arg=3)]) == 0, "did not de-dup GROUP" - if Opt(OptOps.GROUPTOP, 0, 0) in actions: - assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.GROUPTOP, axis=0, arg=3)]) == 0, "did not de-dup GROUPTOP" - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") - def test_search_over_shape(self): - from test.test_linearizer import helper_realized_ast - from tinygrad.engine.search import get_kernel_actions - - dtype_pairs = [(tc.dtype_in, tc.dtype_out) for tc in Device[Device.DEFAULT].renderer.tensor_cores] - multi_shape_dtype_pairs = [dts for dts in dtype_pairs if dtype_pairs.count(dts) > 1] - - if len(multi_shape_dtype_pairs) == 0: raise unittest.SkipTest("only one tc available per dtype pair to search over") - - for (dtype_in, dtype_out) in multi_shape_dtype_pairs: - a = Tensor.rand(16, 16, dtype=dtype_in) - b = Tensor.rand(16, 16, dtype=dtype_in) - realized_ast, _ = helper_realized_ast(a.matmul(b, dtype=dtype_out)) - - lins = get_kernel_actions(Kernel(realized_ast)).values() - assert len(set(lin.tensor_core.dims for lin in lins if lin.tensor_core is not None)) > 1 - - def test_get_kernel_actions_preserves_actions_state(self): - from test.test_linearizer import helper_realized_ast - from tinygrad.engine.search import get_kernel_actions - a = Tensor.rand(16, 16) - b = Tensor.rand(16, 16) - realized_ast, _ = helper_realized_ast(a @ b) - actions_before = actions.copy() - get_kernel_actions(Kernel(realized_ast)) - actions_after = actions.copy() - assert actions_after == actions_before, "actions state was not preserved" - - def test_filter_global_buffer(self): - # taken from https://github.com/tinygrad/tinygrad/issues/4612 - ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( - UOp(Ops.STORE, dtypes.void, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(1, 1, 256), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), - UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (1,)), src=( - UOp(Ops.MUL, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.ADD, dtypes.float, arg=None, src=( - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=0, mask=((0, 64128),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=1, src=()),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-64128, mask=((64128, 128256),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=2, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-128256, mask=((128256, 192384),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=3, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-192384, mask=((192384, 256512),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=4, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-256512, mask=((256512, 320640),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=5, src=()),)),)),)), - UOp(Ops.LOAD, dtypes.float, arg=None, src=( - UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-320640, mask=((320640, 384768),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=6, src=()),)),)),)), - UOp(Ops.CONST, dtypes.float, arg=1.4285714285714286, src=( - UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 501, 256), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) # noqa: E501 - lin = Kernel(ast) - - bufs = bufs_from_lin(lin) - best_lin = beam_search(lin, bufs, 2) - assert best_lin - # need disable_cache to trigger. - tm = time_linearizer(best_lin, bufs, allow_test_size=False, cnt=2, disable_cache=True) - assert tm - - def test_beam_unnamed_kernels(self): - a = Tensor.rand(100) - b = Tensor.rand(100) - si = (a+b).schedule()[-1] - lin = Kernel(si.ast) - bufs = bufs_from_lin(lin) - # TODO: beam should have better instrumentation so we don't have to check this indirect thing - kcount = len(Kernel.kernel_cnt) - beam_search(lin, bufs, 3, disable_cache=True) - self.assertEqual(kcount, len(Kernel.kernel_cnt)) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_setitem.py b/tinygrad/test/test_setitem.py deleted file mode 100644 index d6de6e93..00000000 --- a/tinygrad/test/test_setitem.py +++ /dev/null @@ -1,180 +0,0 @@ -import unittest -from tinygrad import Tensor, TinyJit, Variable, dtypes -from tinygrad.helpers import Context -import numpy as np - -class TestSetitem(unittest.TestCase): - def test_simple_setitem(self): - cases = ( - ((6,6), (slice(2,4), slice(3,5)), Tensor.ones(2,2)), - ((6,6), (slice(2,4), slice(3,5)), Tensor([1.,2.])), - ((6,6), (slice(2,4), slice(3,5)), 1.0), - ((6,6), (3, 4), 1.0), - ((6,6), (3, None, 4, None), 1.0), - ((4,4,4,4), (Ellipsis, slice(1,3), slice(None)), Tensor(4)), - ((4,4,4,4), (Ellipsis, slice(1,3)), 4), - ((4,4,4,4), (2, slice(1,3), None, 1), 4), - ((4,4,4,4), (slice(1,3), slice(None), slice(0,4,2)), 4), - ((4,4,4,4), (slice(1,3), slice(None), slice(None), slice(0,3)), 4), - ((6,6), (slice(1,5,2), slice(0,5,3)), 1.0), - ((6,6), (slice(5,1,-2), slice(5,0,-3)), 1.0), - ) - for shp, slc, val in cases: - t = Tensor.zeros(shp).contiguous() - t[slc] = val - n = np.zeros(shp) - n[slc] = val.numpy() if isinstance(val, Tensor) else val - np.testing.assert_allclose(t.numpy(), n) - - def test_padded_setitem(self): - t = Tensor.arange(10) - t[4:1:-2] = 11 - self.assertListEqual(t.tolist(), [0, 1, 11, 3, 11, 5, 6, 7, 8, 9]) - - def test_setitem_inplace_mul(self): - t = Tensor.arange(10).realize() - t[:3] *= 10 - self.assertListEqual(t.tolist(), [0, 10, 20, 3, 4, 5, 6, 7, 8, 9]) - - def test_setitem_into_unrealized(self): - t = Tensor.arange(4).reshape(2, 2) - t[1] = 5 - np.testing.assert_allclose(t.numpy(), [[0, 1], [5, 5]]) - - def test_setitem_dtype(self): - for dt in (dtypes.int, dtypes.float, dtypes.bool): - for v in (5., 5, True): - t = Tensor.ones(6,6, dtype=dt).contiguous() - t[1] = v - self.assertEqual(t.dtype, dt) - - def test_setitem_into_noncontiguous(self): - t = Tensor.ones(4) - self.assertFalse(t.uop.st.contiguous) - with self.assertRaises(RuntimeError): t[1] = 5 - - @unittest.skip("TODO: flaky") - def test_setitem_inplace_operator(self): - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] += 2 - np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 5]]) - - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] -= 1 - np.testing.assert_allclose(t.numpy(), [[0, 1], [1, 2]]) - - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] *= 2 - np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 6]]) - - # NOTE: have to manually cast setitem target to least_upper_float for div - t = Tensor.arange(4, dtype=dtypes.float).reshape(2, 2).contiguous() - t[1] /= 2 - np.testing.assert_allclose(t.numpy(), [[0, 1], [1, 1.5]]) - - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] **= 2 - np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 9]]) - - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] ^= 5 - np.testing.assert_allclose(t.numpy(), [[0, 1], [7, 6]]) - - #@unittest.expectedFailure - # update: passing after delete_forced_realize - def test_setitem_consecutive_inplace_operator(self): - t = Tensor.arange(4).reshape(2, 2).contiguous() - t[1] += 2 - t = t.contiguous() - # TODO: RuntimeError: can't double realize in one schedule - t[1] -= 1 - np.testing.assert_allclose(t.numpy(), [[0, 1], [3, 4]]) - - def test_setitem_overlapping_indices(self): - t = Tensor([1,2,3,4]) - # regular overlapping indices - t[[1,1]] = Tensor([5,6]) - np.testing.assert_allclose(t.numpy(), [1,6,3,4]) - - # overlapping indices with zero value overlapped - t[[1,1]] = Tensor([0,1]) - np.testing.assert_allclose(t.numpy(), [1,1,3,4]) - - def test_setitem_overlapping_indices_with_0(self): - t = Tensor([1,2,3,4]) - t[[1,1]] = Tensor([1,0]) - np.testing.assert_allclose(t.numpy(), [1,0,3,4]) - - def test_setitem_with_1_in_shape(self): - t = Tensor([[1],[2],[3]]) - t[[0,0]] = Tensor([[1],[2]]) - np.testing.assert_allclose(t.numpy(), [[2],[2],[3]]) - - def test_fancy_setitem(self): - t = Tensor.zeros(6,6).contiguous() - t[[1,2], [3,2]] = 3 - n = np.zeros((6,6)) - n[[1,2], [3,2]] = 3 - np.testing.assert_allclose(t.numpy(), n) - - def test_simple_jit_setitem(self): - @TinyJit - def f(t:Tensor, a:Tensor): - t[2:4, 3:5] = a - - for i in range(1, 6): - t = Tensor.zeros(6, 6).contiguous().realize() - a = Tensor.full((2, 2), fill_value=i, dtype=dtypes.float).contiguous() - f(t, a) - - n = np.zeros((6, 6)) - n[2:4, 3:5] = np.full((2, 2), i) - np.testing.assert_allclose(t.numpy(), n) - - def test_jit_setitem_variable_offset(self): - with Context(IGNORE_OOB=1): - @TinyJit - def f(t:Tensor, a:Tensor, v:Variable): - t.shrink(((v,v+1), None)).assign(a).realize() - - t = Tensor.zeros(6, 6).contiguous().realize() - n = np.zeros((6, 6)) - - for i in range(6): - v = Variable("v", 0, 6).bind(i) - a = Tensor.full((1, 6), fill_value=i+1, dtype=dtypes.float).contiguous() - n[i, :] = i+1 - f(t, a, v) - np.testing.assert_allclose(t.numpy(), n) - np.testing.assert_allclose(t.numpy(), [[1,1,1,1,1,1],[2,2,2,2,2,2],[3,3,3,3,3,3],[4,4,4,4,4,4],[5,5,5,5,5,5],[6,6,6,6,6,6]]) - - def test_setitem_overlapping_inplace1(self): - t = Tensor([[3.0], [2.0], [1.0]]).contiguous() - t[1:] = t[:-1] - self.assertEqual(t.tolist(), [[3.0], [3.0], [2.0]]) - - def test_setitem_overlapping_inplace2(self): - t = Tensor([[3.0], [2.0], [1.0]]).contiguous() - t[:-1] = t[1:] - self.assertEqual(t.tolist(), [[2.0], [1.0], [1.0]]) - -class TestWithGrad(unittest.TestCase): - def test_no_requires_grad_works(self): - z = Tensor.rand(8, 8) - x = Tensor.rand(8) - z[:3] = x - - def test_set_into_requires_grad(self): - z = Tensor.rand(8, 8, requires_grad=True) - x = Tensor.rand(8) - with self.assertRaises(NotImplementedError): - z[:3] = x - - def test_set_with_requires_grad(self): - z = Tensor.rand(8, 8) - x = Tensor.rand(8, requires_grad=True) - with self.assertRaises(NotImplementedError): - z[:3] = x - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_softmax_fusion.py b/tinygrad/test/test_softmax_fusion.py deleted file mode 100644 index 23e1a4b7..00000000 --- a/tinygrad/test/test_softmax_fusion.py +++ /dev/null @@ -1,177 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Tensor, GlobalCounters, Context, Device -from tinygrad.dtype import DTypeLike, dtypes -from tinygrad.helpers import DEBUG, get_single_element -from tinygrad.engine.realize import lower_schedule_item -from tinygrad.device import is_dtype_supported - -def single_kernel_softmax(x_in:Tensor, axis=-1, dtype:DTypeLike|None=None) -> Tensor: - # only support axis =-1 - x = x_in.reshape(-1, x_in.shape[-1]) - nr_dim, r_dim = x.shape - - inp = x.reshape(nr_dim, 1, 1, r_dim).expand(nr_dim, r_dim, 1, r_dim) - imx = x.reshape(nr_dim, 1, r_dim, 1).expand(nr_dim, r_dim, r_dim, r_dim).max(axis=-2, keepdim=True) - m = inp - imx.detach() - if dtype is not None: m = m.cast(dtype) - e = m.exp() - ss = e.sum(axis=-1, keepdim=True) - - inp = x.reshape(nr_dim, r_dim, 1, 1) - imx = x.reshape(nr_dim, 1, r_dim, 1).expand(nr_dim, r_dim, r_dim, 1).max(axis=-2, keepdim=True) - m = inp - imx.detach() - if dtype is not None: m = m.cast(dtype) - e = m.exp() - - out = e.div(ss).reshape(x_in.shape) - return out - -def run_one_schedule_item(out): lower_schedule_item(get_single_element(out.schedule())).run() - -class TestFuse(unittest.TestCase): - def _test_fuse(self, fxn, *args, atol=1e-7, allow_multiple=False, **kwargs): - GlobalCounters.reset() - out_single = fxn(*args, **kwargs).fuse() - if not allow_multiple: run_one_schedule_item(out_single) - np_single = out_single.numpy() - GlobalCounters.reset() - np_multi = fxn(*args, **kwargs).numpy() - np.testing.assert_allclose(np_single, np_multi, atol=atol) - - def test_fuse_norm(self): - a = Tensor.rand(50,50).realize() - self._test_fuse(lambda a: a / a.mean(axis=1), a) - - def test_fuse_argmax(self): - a = Tensor.rand(50,50).realize() - self._test_fuse(lambda a: a.argmax(axis=-1), a) - - def test_fuse_softmax(self): - a = Tensor.rand(50,50).realize() - self._test_fuse(lambda a: a.softmax(axis=-1), a) - - def test_fuse_gemm_softmax(self): - a = Tensor.rand(50,50).realize() - b = Tensor.rand(50,50).realize() - self._test_fuse(lambda a,b: ((a@b).relu()+a).contiguous().softmax(axis=-1), a,b, allow_multiple=True) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") - def test_fuse_softmax_dtype(self): - a = Tensor.rand(50,50).realize() - self._test_fuse(lambda a: a.softmax(axis=-1, dtype='half'), a, atol=3e-4) - - def test_fuse_arange_eye(self): - self._test_fuse(lambda: Tensor.arange(10).reshape(10,1).expand(10,10) == Tensor.arange(10).reshape(1,10).expand(10,10)) - - def test_double_gemm(self): - N = 32 - with Context(TRACK_MATCH_STATS=0, DEBUG=0): - a = (Tensor.rand(N,N)-0.5).realize() - b = (Tensor.rand(N,N)-0.5).realize() - c = (Tensor.rand(N,N)-0.5).realize() - self._test_fuse(lambda a,b,c: a@b@c, a, b, c, atol=1e-5) - - def test_embedding(self): - with Context(TRACK_MATCH_STATS=0, DEBUG=0): - vocab_sz = 123 - embed_sz = 16 - weight = (Tensor.rand(vocab_sz, embed_sz)-0.5).realize() - a = Tensor([1, 1, 2, 3]).realize() - def embedding(idx:Tensor): - arange = Tensor.arange(vocab_sz).unsqueeze(-1) - big_shp = idx.shape + (vocab_sz, embed_sz) - arange, vals = arange.expand(big_shp), weight.expand(big_shp) - idx = idx.reshape(idx.shape+(1, 1)).expand(big_shp) - return (arange == idx).mul(vals).sum(-2, dtype=vals.dtype) - self._test_fuse(embedding, a, atol=1e-5) - - @unittest.skip("still broken") - def test_flash_attention(self): - BS = 4 - HEADS = 2 - MATDIM = 16 - EMB = 8 - with Context(TRACK_MATCH_STATS=0, DEBUG=0): - q = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() - k = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() - v = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() - # TODO: OPT is breaking things. NOOPT isn't linearizing - with Context(NOOPT=1): - self._test_fuse(Tensor.scaled_dot_product_attention, q, k, v) - -class TestSoftmaxFusion(unittest.TestCase): - @classmethod - def setUpClass(cls): - with Context(TRACK_MATCH_STATS=0): cls.test = Tensor.rand(32, 10).contiguous().realize() - - def setUp(self): - GlobalCounters.reset() - - def test_norm(self): - print("*** norm ***") - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - # NOTE: there's an implied expand on the mean here - sout = self.test / self.test.mean(-1, keepdim=True) - sout.realize() - - print("*** single kernel norm ***") - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - inp = self.test.reshape(32, 10, 1) - div = self.test.reshape(32, 1, 10).expand(32, 10, 10).mean(axis=-1, keepdim=True) - out = (inp / div).reshape(32, 10) - out.realize() - - np.testing.assert_allclose(sout.numpy(), out.numpy()) - - def test_softmax(self): - # this is the softmax from scaled_dot_product_attention - # it becomes 3 kernels - print("*** softmax ***") - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - sout = self.test.softmax(-1) - sout.realize() - - print("*** single kernel softmax ***") - # NOTE: DONT_GROUP_REDUCES is required here - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2), DONT_GROUP_REDUCES=1): - out = single_kernel_softmax(self.test) - out.realize() - - np.testing.assert_allclose(sout.numpy(), out.numpy()) - - def test_auto_softmax(self): - print("*** softmax ***") - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - sout = self.test.softmax(-1) - sout.realize() - - print("*** auto single kernel softmax ***") - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - out = self.test.contiguous().softmax(-1).fuse() - run_one_schedule_item(out) - - np.testing.assert_allclose(sout.numpy(), out.numpy()) - - @unittest.skip("recursion error no longer raised") - def test_softmax_bw(self): - print("*** softmax bw ***") - self.test.requires_grad_() - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): - self.test.softmax(-1).sum().backward() - sg = self.test.grad.realize() - - self.test.grad = None - - print("*** single kernel softmax bw ***") - # NOTE: DONT_GROUP_REDUCES is required here - # TODO: fix RecursionError with DONT_GROUP_REDUCES - with self.assertRaises(RecursionError): - with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2), DONT_GROUP_REDUCES=1): - single_kernel_softmax(self.test).sum().backward() - g = self.test.grad.realize() - - np.testing.assert_allclose(sg.numpy(), g.numpy(), atol=1e-7) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_specific_conv.py b/tinygrad/test/test_specific_conv.py deleted file mode 100644 index ed6492b5..00000000 --- a/tinygrad/test/test_specific_conv.py +++ /dev/null @@ -1,55 +0,0 @@ -import unittest -from tinygrad.helpers import CI -from tinygrad import Tensor, Device, dtypes -from tinygrad.device import is_dtype_supported -# similar to test/external/external_test_gpu_ast.py, but universal - -@unittest.skipIf(Device.DEFAULT in {"CUDA", "NV"} and CI, "slow on CUDA CI") -class TestSpecific(unittest.TestCase): - # from openpilot - - # 1x1 6 <- 24 - def test_1x1_6_24(self): - x = Tensor.randn(1, 24*4, 32, 64) - w = Tensor.randn(6*4, 24*4, 1, 1) - x.conv2d(w).permute(0,2,3,1).reshape(32, 384, 4).contiguous().realize() - - def test_vec_mul(self): - # this forces it to be an image... - x = Tensor.ones(1, 512, 4).contiguous().reshape(1, 2048) - w = Tensor.randn(2048, 512) - (x @ w).reshape(1, 128, 4).contiguous().realize() - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") - def test_big_vec_mul(self): - # from LLaMA - # 0 buffer<4096, dtypes.float> [View((1024, 1, 1, 4), (4, 0, 0, 1), 0, None)] - # 1 buffer<4096, dtypes.float> [View((1024, 1024, 4, 4), (0, 4, 1, 0), 0, None)] - # 2 buffer<16777216, dtypes.half> [View((1024, 1024, 4, 4), (16384, 4, 1, 4096), 0, None)] - x = Tensor.randn(4096).realize() - w = Tensor.randn(4096, 4096, dtype=dtypes.float16).realize() - (x @ w.T).realize() - - # from https://dl.acm.org/doi/pdf/10.1145/3495243.3517020 - - # ~260 GFLOPS on Adreno 640, should be 260*(720/890)*(596/710) = 176.5 on downclocked 630 - # we get 170 - def test_1x1_28_28(self): - x = Tensor.randn(1, 256, 28, 28) - w = Tensor.randn(256, 256, 1, 1) - x.conv2d(w).permute(0,2,3,1).reshape(28, 28*256//4, 4).contiguous().realize() - - # 132 GFLOPS on Adreno 640, should be 132*(720/890)*(596/710) = 90 on downclocked 630 - # gets 54 with broken opt, 74 without opt, and 146 if we pad and opt 3! - def test_3x3_28_28_stride_2(self): - x = Tensor.randn(1, 288, 36, 36) - w = Tensor.randn(384, 288, 3, 3) - x.conv2d(w, stride=2).permute(0,2,3,1).reshape(17, 17*384//4, 4).contiguous().realize() - - def test_3x3_28_28_stride_2_padded(self): - x = Tensor.randn(1, 288, 36, 36) - w = Tensor.randn(384, 288, 3, 3) - x.conv2d(w, stride=2, padding=1).permute(0,2,3,1).reshape(18, 18*384//4, 4).contiguous().realize() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_speed_v_torch.py b/tinygrad/test/test_speed_v_torch.py deleted file mode 100644 index b6c728ad..00000000 --- a/tinygrad/test/test_speed_v_torch.py +++ /dev/null @@ -1,287 +0,0 @@ -import os -os.environ["NVIDIA_TF32_OVERRIDE"] = "0" -os.environ["MKL_NUM_THREADS"] = "1" -os.environ["NUMEXPR_NUM_THREADS"] = "1" -os.environ["OMP_NUM_THREADS"] = "1" -os.environ["VECLIB_MAXIMUM_THREADS"] = "1" -import unittest -import torch -torch.set_num_threads(1) -import time -import numpy as np -np.set_printoptions(linewidth=160) -from tinygrad import Tensor, Device, GlobalCounters, TinyJit -from tinygrad.nn import Conv2d -from tinygrad.helpers import colorize_float, getenv, CI - -IN_CHANS = [int(x) for x in getenv("IN_CHANS", "4,16,64").split(",")] - -torch_dt = torch.float16 if getenv("HALF", 0) else torch.float32 -torch_device = torch.device('mps' if getenv("MPS", 0) else ('cuda' if getenv("TORCHCUDA", 0) else 'cpu')) -if str(torch_device) == "mps": - import torch.mps - def sync(): torch.mps.synchronize() -elif str(torch_device) == "cuda": - import torch.cuda - def sync(): torch.cuda.synchronize() -else: - def sync(): pass - -save_ops, save_mem = 0, 0 -CNT = getenv("CNT", 8) -def helper_test_speed(f1, *args): - global save_ops, save_mem - ets = [] - ret = None - cache_defeat = np.zeros((2048,2048)) - for i in range(CNT): - del ret - - # operation cache defeats - args = [(x+1).realize() if isinstance(x, Tensor) else (None if x is None else (x+1)) for x in args] - args = [(x-1).realize() if isinstance(x, Tensor) else (None if x is None else (x-1)) for x in args] - - # force syncing - [x.numpy() if isinstance(x, Tensor) or str(torch_device) == "cpu" else x.cpu().numpy() for x in args if x is not None] - - # clear 32MB global memory cache (CPU and global memory only) - cache_defeat += 1 - - # manual pre sync - if isinstance(args[0], Tensor): - local_device = Device[args[0].device] - local_device.synchronize() - else: sync() - - GlobalCounters.global_ops = 0 - GlobalCounters.global_mem = 0 - st = time.perf_counter() - ret = f1(*args) - if isinstance(ret, Tensor): local_device.synchronize() - else: sync() - et = (time.perf_counter() - st) * 1000 - if i >= 1: ets.append(et) - if GlobalCounters.global_ops: - save_ops, save_mem = GlobalCounters.global_ops, GlobalCounters.global_mem - return ret.numpy() if isinstance(ret, Tensor) else ret.cpu().numpy(), np.min(ets) - -def helper_test_generic_square(name, N, f1, f2, onearg=False): - torch.manual_seed(0) - torch_a = (torch.rand(N, N, dtype=torch_dt) - 0.5).to(torch_device) - torch_b = (torch.rand(N, N, dtype=torch_dt) - 0.5).to(torch_device) if not onearg else None - - tiny_a = Tensor(torch_a.cpu().numpy()) - tiny_b = Tensor(torch_b.cpu().numpy()) if not onearg else None - - helper_test_generic(f"{name:30s} {N:5d}x{N:5d}", f1, (torch_a, torch_b), TinyJit(f2), (tiny_a, tiny_b)) - -def helper_test_matvec(name, N, M): - torch.manual_seed(0) - torch_a = (torch.rand(N, dtype=torch_dt) - 0.5).to(torch_device) - torch_b = (torch.rand(N, M, dtype=torch_dt) - 0.5).to(torch_device) - - tiny_a = Tensor(torch_a.cpu().numpy()) - tiny_b = Tensor(torch_b.cpu().numpy()) - - helper_test_generic(f"{name:30s} {N:5d}x{M:5d}", lambda a,b: a@b, (torch_a, torch_b), TinyJit(lambda a,b:a@b), (tiny_a, tiny_b)) - -prefix = None -def helper_test_generic(name, f1, f1_args, f2, f2_args): - global prefix - with torch.no_grad(): - val_torch, et_torch = helper_test_speed(f1, *f1_args) - val_tinygrad, et_tinygrad = helper_test_speed(f2, *f2_args) - - desc = "faster" if et_torch > et_tinygrad else "slower" - flops = save_ops*1e-6 - mem = save_mem*1e-6 - print(("\r" if not CI else "")+f"{name:42s} {et_torch:7.2f} ms ({flops/et_torch:9.2f} GFLOPS {mem/et_torch:7.2f} GB/s) in torch, {et_tinygrad:7.2f} ms ({flops/et_tinygrad:9.2f} GFLOPS {mem/et_tinygrad:7.2f} GB/s) in tinygrad, {colorize_float(et_tinygrad/et_torch)} {desc} {flops:10.2f} MOPS {mem:8.2f} MB") # noqa: E501 - atol, rtol = (1e-2, 1e-2) if torch_dt == torch.float16 else (1e-3, 1e-3) - np.testing.assert_allclose(val_tinygrad, val_torch, atol=atol, rtol=rtol) - -def helper_test_conv(bs, in_chans, out_chans, kernel_size, img_size_y, img_size_x): - torch.manual_seed(0) - torch_dat = torch.rand(bs, in_chans, img_size_y, img_size_x, dtype=torch_dt).to(torch_device) - torch_conv = torch.nn.Conv2d(in_chans, out_chans, kernel_size, bias=None, dtype=torch_dt).to(torch_device) - - tiny_dat = Tensor(torch_dat.cpu().numpy()) - tiny_conv = Conv2d(in_chans, out_chans, kernel_size, bias=None) - tiny_conv.weight = Tensor(torch_conv.weight.detach().cpu().numpy()) - - def f1(torch_dat): return torch_conv(torch_dat) - def f2(tiny_dat): return tiny_conv(tiny_dat).realize() - helper_test_generic(f"conv bs:{bs:3d} chans:{in_chans:3d} -> {out_chans:3d} k:{kernel_size}", f1, (torch_dat,), TinyJit(f2), (tiny_dat,)) - -@unittest.skipIf(getenv("BIG") == 0, "no big tests") -@unittest.skipIf(getenv("MOCKGPU"), "no MOCKGPUs") -class TestBigSpeed(unittest.TestCase): - def test_add(self): - def f(a, b): return a+b - helper_test_generic_square('add', 8192, f, f) - def test_exp(self): - def f(a, b): return a.exp() - helper_test_generic_square('exp', 8192, f, f, onearg=True) - def test_gemm_2048(self): - def f(a, b): return a @ b - helper_test_generic_square('gemm', 2048, f, f) - def test_gemm_4096(self): - def f(a, b): return a @ b - helper_test_generic_square('gemm', 4096, f, f) - def test_large_conv_1x1(self): helper_test_conv(bs=32, in_chans=128, out_chans=128, kernel_size=1, img_size_y=128, img_size_x=128) - def test_large_conv_3x3(self): helper_test_conv(bs=4, in_chans=128, out_chans=128, kernel_size=3, img_size_y=130, img_size_x=130) - def test_large_conv_5x5(self): helper_test_conv(bs=4, in_chans=128, out_chans=128, kernel_size=5, img_size_y=132, img_size_x=132) - def test_matvec_4096_16384(self): helper_test_matvec('matvec_4096_16384', 4096, 16384) - def test_matvec_16384_4096(self): helper_test_matvec('matvec_16384_4096', 16384, 4096) - -@unittest.skipIf(getenv("BIG") == 1, "only big tests") -@unittest.skipIf(getenv("MOCKGPU"), "no MOCKGPUs") -class TestSpeed(unittest.TestCase): - def test_sub(self): - def f(a, b): return a-b - helper_test_generic_square('sub', 4096, f, f) - - def test_pow(self): - def f(a, b): return a.pow(b) - helper_test_generic_square('pow', 2048, f, f) - - def test_sum(self): - def f(a, b): return a.sum() - helper_test_generic_square('sum', 2048, f, f, onearg=True) - helper_test_generic_square('sum', 4096, f, f, onearg=True) - - def test_partial_sum(self): - R = 256 - def f(a, b): return a.reshape(int(4096//R), int(4096*R)).sum(axis=1) - helper_test_generic_square('partial_sum', 4096, f, f, onearg=True) - - @unittest.skip("not really used in models") - def test_cumsum(self): - def f0(a, b): return a.cumsum(axis=0) - def f1(a, b): return a.cumsum(axis=1) - helper_test_generic_square('cumsum_0', 256, f0, f0, onearg=True) - helper_test_generic_square('cumsum_1', 256, f1, f1, onearg=True) - - def test_cat(self): - helper_test_generic_square('cat_0', 2048, lambda x,y: torch.cat((x,y),dim=0), lambda x,y: x.cat(y,dim=0)) - helper_test_generic_square('cat_1', 2048, lambda x,y: torch.cat((x,y),dim=1), lambda x,y: x.cat(y,dim=1)) - - def test_array_packing(self): - N = 2048 - def f(a, b): return a.reshape(N, N // 32, 32).permute(1,0,2).contiguous() - helper_test_generic_square('array_packing', N, f, f, onearg=True) - - def test_permute(self): - for N in [1024, 4096]: - # this is a 64MB tensor, M1 L1 cache is 128kB - # to fit easily in L1, rotations should be 128x128 chunks. 128x128 is also the AMX size - def f(a, b): return a.permute(1,0).contiguous() - helper_test_generic_square('permute', N, f, f, onearg=True) - - def test_double_permute(self): - N = 64 - torch.manual_seed(0) - torch_a = (torch.rand(N, N, N, N, dtype=torch_dt) - 0.5).to(torch_device) - tiny_a = Tensor(torch_a.cpu().numpy()) - def f(a): return a.permute(1,0,3,2).contiguous() - helper_test_generic(f"double_permute {tiny_a.shape}", f, (torch_a,), TinyJit(lambda a: f(a).realize()), (tiny_a,)) - - def test_neg(self): - def f(a, b): return -a - helper_test_generic_square('neg', 4096, f, f, onearg=True) - - def test_exp(self): - def f(a, b): return a.exp() - helper_test_generic_square('exp', 2048, f, f, onearg=True) - - def test_sqrt(self): - def f(a, b): return a.sqrt() - helper_test_generic_square('sqrt', 2048, f, f, onearg=True) - - def test_relu(self): - def f(a, b): return a.relu() - helper_test_generic_square('relu', 4096, f, f, onearg=True) - - def test_max(self): - def f(a, b): return a.max() - helper_test_generic_square('max', 4096, f, f, onearg=True) - - def test_mul_sum(self): - def f(a, b): return (a*b).sum() - helper_test_generic_square('mul_sum', 4096, f, f) - - def test_add_a(self): - def f(a, b): return a + b - helper_test_generic_square('add', 1, f, f) - - def test_add_big(self): - for N in [1024, 4096]: - def f(a, b): return a + b - helper_test_generic_square('add', N, f, f) - - def test_add_constant(self): - def f(a, b): return a+2.0 - helper_test_generic_square('add_constant', 4096, f, f, onearg=True) - - def test_add_sq(self): - def f(a, b): return a*a + b*b - helper_test_generic_square('add_sq', 4096, f, f) - - def test_gemm(self): - def f(a, b): return a @ b - helper_test_generic_square('gemm', 1024, f, f) - - def test_gemm_small(self): - def f(a, b): return a @ b - helper_test_generic_square('gemm', 256, f, f) - - def test_gemm_unrolled(self): - N = 512 - def f1(a, b): return a@b.T - def f2(a, b): return (a.reshape(N, 1, N).expand(N, N, N) * b.reshape(1, N, N).expand(N, N, N)).sum(axis=2) - helper_test_generic_square('gemm_unrolled', N, f1, f2) - - def test_gemm_unrolled_permute_l(self): - N = 512 - def f1(a, b): return a.T@b.T - def f2(a, b): return (a.permute(1,0).reshape(N, 1, N).expand(N, N, N) * b.reshape(1, N, N).expand(N, N, N)).sum(axis=2) - helper_test_generic_square('gemm_unrolled_permute_l', N, f1, f2) - - def test_gemm_unrolled_permute_r(self): - N = 512 - def f1(a, b): return a@b - def f2(a, b): return (a.reshape(N, 1, N).expand(N, N, N) * b.permute(1,0).reshape(1, N, N).expand(N, N, N)).sum(axis=2) - helper_test_generic_square('gemm_unrolled_permute_r', N, f1, f2) - - def test_gemm_unrolled_permute_lr(self): - N = 512 - def f1(a, b): return a.T@b - def f2(a, b): return (a.permute(1,0).reshape(N, 1, N).expand(N, N, N) * b.permute(1,0).reshape(1, N, N).expand(N, N, N)).sum(axis=2) - helper_test_generic_square('gemm_unrolled_permute_lr', N, f1, f2) - - def test_matvec_1024_1024(self): helper_test_matvec('matvec_1024_1024', 1024, 1024) - def test_matvec_1024_4096(self): helper_test_matvec('matvec_1024_4096', 1024, 4096) - def test_matvec_4096_1024(self): helper_test_matvec('matvec_4096_1024', 4096, 1024) - def test_matvec_4096_4096(self): helper_test_matvec('matvec_4096_4096', 4096, 4096) - - def test_openpilot_conv2d(self): - bs, in_chans, out_chans = 1,12,32 - torch.manual_seed(0) - torch_dat = torch.rand(bs, 64, 128, 12, dtype=torch_dt).to(torch_device) - torch_conv = torch.nn.Conv2d(in_chans, out_chans, 3, bias=None, padding=1, dtype=torch_dt).to(torch_device) - - tiny_dat = Tensor(torch_dat.cpu().numpy()) - tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) - tiny_conv.weight = Tensor(torch_conv.weight.detach().cpu().numpy()) - - def f1(torch_dat): return torch_conv(torch_dat.permute(0,3,1,2)) - def f2(tiny_dat): return tiny_conv(tiny_dat.permute(0,3,1,2)).realize() - helper_test_generic(f"conv bs:{bs:3d} chans:{in_chans:3d} -> {out_chans:3d} k:3", f1, (torch_dat,), TinyJit(f2), (tiny_dat,)) - - def test_conv2d(self): - for bs in [32]: - for in_chans in IN_CHANS: - for out_chans in [32]: - helper_test_conv(bs, in_chans, out_chans, 3, 34, 34) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_stunning.py b/tinygrad/test/test_stunning.py deleted file mode 100644 index 0429a405..00000000 --- a/tinygrad/test/test_stunning.py +++ /dev/null @@ -1,59 +0,0 @@ -import unittest -from tinygrad import nn, Tensor, Variable, Context, Device -from tinygrad.helpers import trange - -class Model: - def __init__(self): self.layer = nn.Linear(28*28, 10) - def __call__(self, x:Tensor) -> Tensor: return self.layer(x.flatten(1)) - -class TestStunning(unittest.TestCase): - def test_indexing_variable(self): - a = Tensor.arange(100*10).reshape(100, 10).contiguous() - - # index without variable - nv = a[12].tolist() - - # index with variable - vi = Variable('i', 0, a.shape[0]-1) - wv = a[vi.bind(12)].tolist() - - self.assertListEqual(nv, wv) - - def test_indexing_two_bind(self): - a = Tensor.arange(100*10).reshape(100, 10).contiguous() - - nv = a[12].cat(a[76]).tolist() - - vi = Variable('i', 0, a.shape[0]-1) - with self.assertRaisesRegex(AssertionError, "different values for the same key"): - wv = a[vi.bind(12)].cat(a[vi.bind(76)]).tolist() - self.assertListEqual(nv, wv) - - @unittest.skipIf(Device.DEFAULT in {"WEBGPU", "NV", "CUDA"}, "Too many buffers / too slow") - @unittest.skip("This is binding a Variable to two different values") - def test_simple_train(self, steps=6, bs=4, adam=True): - X_train, Y_train, _, _ = nn.datasets.mnist() - model = Model() - if adam: opt = nn.optim.Adam(nn.state.get_parameters(model)) - else: opt = nn.optim.SGD(nn.state.get_parameters(model), momentum=0.1) - samples = Tensor.randint(steps, bs, high=X_train.shape[0]) - Y_train = Y_train.one_hot(10) - X_samp, Y_samp = X_train[samples], Y_train[samples] - vi = Variable('i', 0, samples.shape[0]-1) - with Context(FUSE_ARANGE=1, SPLIT_REDUCEOP=0): - with Tensor.train(): - losses = [] - for i in range(samples.shape[0]): - vib = vi.bind(i) - opt.zero_grad() - pred = model(X_samp[vib].realize()) - loss = (pred - Y_samp[vib]).square().mean() - losses.append(loss.backward()) - opt.schedule_step() - #losses = Tensor.stack(*losses) - - # run - for i in (t:=trange(len(losses))): t.set_description(f"loss: {losses[i].item():6.2f}") - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_subbuffer.py b/tinygrad/test/test_subbuffer.py deleted file mode 100644 index 9c9a34d5..00000000 --- a/tinygrad/test/test_subbuffer.py +++ /dev/null @@ -1,68 +0,0 @@ -import unittest -from tinygrad import Device, dtypes, Tensor -from tinygrad.device import Buffer -from tinygrad.helpers import Context -from test.helpers import REAL_DEV - -@unittest.skipUnless(hasattr(Device[Device.DEFAULT].allocator, "_offset"), "subbuffer not supported") -class TestSubBuffer(unittest.TestCase): - def setUp(self): - self.buf = Buffer(Device.DEFAULT, 10, dtypes.uint8).ensure_allocated() - self.buf.copyin(memoryview(bytearray(range(10)))) - - def test_subbuffer(self): - vbuf = self.buf.view(2, dtypes.uint8, offset=3).ensure_allocated() - tst = vbuf.as_buffer().tolist() - assert tst == [3, 4] - - def test_subbuffer_cast(self): - # NOTE: bitcast depends on endianness - vbuf = self.buf.view(2, dtypes.uint16, offset=3).ensure_allocated() - tst = vbuf.as_buffer().cast("H").tolist() - assert tst == [3|(4<<8), 5|(6<<8)] - - def test_subbuffer_double(self): - vbuf = self.buf.view(4, dtypes.uint8, offset=3).ensure_allocated() - vvbuf = vbuf.view(2, dtypes.uint8, offset=1).ensure_allocated() - tst = vvbuf.as_buffer().tolist() - assert tst == [4, 5] - - def test_subbuffer_len(self): - vbuf = self.buf.view(5, dtypes.uint8, 2).ensure_allocated() - mv = vbuf.as_buffer() - assert len(mv) == 5 - mv = vbuf.as_buffer(allow_zero_copy=True) - assert len(mv) == 5 - - def test_subbuffer_used(self): - t = Tensor.arange(0, 10, dtype=dtypes.uint8).realize() - vt = t[2:4].realize() - out = (vt + 100).tolist() - assert out == [102, 103] - - @unittest.skipIf(REAL_DEV not in {"CUDA", "NV", "AMD"}, "only NV, AMD, CUDA") - def test_subbuffer_transfer(self): - t = Tensor.arange(0, 10, dtype=dtypes.uint8).realize() - vt = t[2:5].contiguous().realize() - out = vt.to(f"{Device.DEFAULT}:1").realize().tolist() - assert out == [2, 3, 4] - - def test_subbuffer_deallocate(self): - with Context(LRU=0): - vbuf = self.buf.view(2, dtypes.uint8, offset=3).ensure_allocated() - self.buf.deallocate() - vbuf.deallocate() - - # Allocate a fake one on the same place - _ = Buffer(Device.DEFAULT, 10, dtypes.uint8).ensure_allocated() - - self.buf.ensure_allocated() - self.buf.copyin(memoryview(bytearray(range(10, 20)))) - - vbuf.ensure_allocated() - - tst = vbuf.as_buffer().tolist() - assert tst == [13, 14] - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_symbolic_jit.py b/tinygrad/test/test_symbolic_jit.py deleted file mode 100644 index 881ce334..00000000 --- a/tinygrad/test/test_symbolic_jit.py +++ /dev/null @@ -1,327 +0,0 @@ -import unittest - -from test.helpers import assert_jit_cache_len -from tinygrad import Variable, Tensor, TinyJit -from tinygrad.helpers import Context -import numpy as np - -class TestSymbolicJit(unittest.TestCase): - def setUp(self): - # A lot of these test are out of bounds, so we ignore the bounds check - self.context = Context(IGNORE_OOB=1) - self.context.__enter__() - - def tearDown(self): - self.context.__exit__(None, None, None) - - def test_plus1(self): - def f(a): return (a+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - symbolic = jf(a.reshape(3, vi)).reshape(3, i).numpy() - expected = f(a).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_add(self): - def f(a, b): return (a+b).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(3, i) - symbolic = jf(a.reshape(3, vi), b.reshape(3, vi)).reshape(3, i).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_matmul(self): - def f(a, b): return (a@b).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(i, 5) - symbolic = jf(a.reshape(3, vi), b.reshape(vi, 5)).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_mixed_with_no_symbol_kernel(self): - def f(a, b): - s = (a@b).realize() - s = (s+s).realize() # this one does not have symbols in input - return s - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(i, 5) - symbolic = jf(a.reshape(3, vi), b.reshape(vi, 5)).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 2) - - def test_attention(self): - def f(q, k, v): return Tensor.scaled_dot_product_attention(q.transpose(1, 2), k.transpose(1, 2), v.transpose(1, 2)).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - q = Tensor.rand(2, 1, 4, 8) - k = Tensor.rand(2, i, 4, 8) - v = Tensor.rand(2, i, 4, 8) - symbolic = jf(q, k.reshape(2, vi, 4, 8), v.reshape(2, vi, 4, 8)).reshape(2, 4, 1, 8).numpy() - expected = f(q, k, v).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 5) - - def test_cat_dim0(self): - def f(a, b): return a.cat(b, dim=0).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(i, 3) - b = Tensor.rand(2, 3) - symbolic = jf(a.reshape(vi, 3), b).reshape(i+2, 3).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_cat_dim1(self): - def f(a, b): return a.cat(b, dim=1).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(3, 2) - symbolic = jf(a.reshape(3, vi), b).reshape(3, i+2).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_cat_dim0_two_vars(self): - def f(a, b): return a.cat(b, dim=0).realize() - jf = TinyJit(f) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(i, 3) - b = Tensor.rand(j, 3) - symbolic = jf(a.reshape(vi, 3), b.reshape(vj, 3)).reshape(i+j, 3).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_cat_dim1_two_vars(self): - def f(a, b): return a.cat(b, dim=1).realize() - jf = TinyJit(f) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(3, i) - b = Tensor.rand(3, j) - symbolic = jf(a.reshape(3, vi), b.reshape(3, vj)).reshape(3, i+j).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_two_vars_plus1_ij(self): - def f(a, b): return (a@b+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(i, 3) - b = Tensor.rand(3, j) - symbolic = jf(a.reshape(vi, 3), b.reshape(3, vj)).reshape(i, j).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_two_vars_plus1_ji(self): - def f(a, b): return (a@b+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(j, 3) - b = Tensor.rand(3, i) - symbolic = jf(a.reshape(vj, 3), b.reshape(3, vi)).reshape(j, i).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_jit_symbolic_shape_mismatch(self): - @TinyJit - def add(a, b): return (a+b).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i).reshape(3, vi) - b = Tensor.rand(3, i).reshape(3, vi) - add(a, b) - vi2 = Variable("i", 1, 10).bind(7) - a = Tensor.rand(3, 7).reshape(3, vi2) - bad = Tensor.rand(4, 7).reshape(4, vi2) - with self.assertRaises(AssertionError): - add(a, bad) - - def test_shrink(self): - # shrink is a movement, so we pair it with a simple function to test the JIT interaction - def f(a): return (a+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(7, 11) - symbolic = a.shrink(((3,5),(vi,vi+2))) - symbolic = jf(symbolic).numpy() - expected = f(a.shrink(((3,5),(i,i+2)))).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_slice(self): - # slice is a movement, so we pair it with a simple function to test the JIT interaction - def f(a): return (a+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(7, 11) - symbolic = a[3:5, vi:vi+2] - symbolic = jf(symbolic).numpy() - expected = f(a[3:5, i:i+2]).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_slice_var_shape(self): - def f(a): return (a+1).realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.ones(vi, 11).contiguous() - symbolic = a[:, 1:2] - symbolic = jf(symbolic).reshape(i, 1).numpy() - expected = f(a.reshape(i, 11)[:, 1:2]).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - assert_jit_cache_len(jf, 1) - - def test_ones_sum(self): - def f(a): return a.sum().realize() - jf = TinyJit(f) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - t = Tensor.ones(i) - symbolic = jf(t.reshape(vi)).item() - expected = f(t).item() - np.testing.assert_equal(symbolic, expected) - - def test_mean(self): - def f(a): return a.mean().realize() - def f0(a): return a.mean(0).realize() - def f1(a): return a.mean(1).realize() - jf = TinyJit(f) - jf0 = TinyJit(f0) - jf1 = TinyJit(f1) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - # aixs = None - a = Tensor.rand(i, 3) - symbolic = jf(a.reshape(vi, 3)).numpy() - expected = a.mean().numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 0 - a = Tensor.rand(i, 3) - symbolic = jf0(a.reshape(vi, 3)).numpy() - expected = a.mean(0).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 1 - a = Tensor.rand(i, 3) - symbolic = jf1(a.reshape(vi, 3)).reshape(i).numpy() - expected = a.mean(1).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_mean_2d(self): - def f(a): return a.mean().realize() - def f0(a): return a.mean(0).realize() - def f1(a): return a.mean(1).realize() - jf = TinyJit(f) - jf0 = TinyJit(f0) - jf1 = TinyJit(f1) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - # aixs = None - a = Tensor.rand(i, j) - symbolic = jf(a.reshape(vi, vj)).numpy() - expected = a.mean().numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 0 - a = Tensor.rand(i, j) - symbolic = jf0(a.reshape(vi, vj)).reshape(j).numpy() - expected = a.mean(0).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 1 - a = Tensor.rand(i, j) - symbolic = jf1(a.reshape(vi, vj)).reshape(i).numpy() - expected = a.mean(1).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_var(self): - def f(a): return a.var().realize() - def f0(a): return a.var(0).realize() - def f1(a): return a.var(1).realize() - jf = TinyJit(f) - jf0 = TinyJit(f0) - jf1 = TinyJit(f1) - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - # aixs = None - a = Tensor.rand(i, 3) - symbolic = jf(a.reshape(vi, 3)).numpy() - expected = a.var().numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 0 - a = Tensor.rand(i, 3) - symbolic = jf0(a.reshape(vi, 3)).numpy() - expected = a.var(0).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 1 - a = Tensor.rand(i, 3) - symbolic = jf1(a.reshape(vi, 3)).reshape(i).numpy() - expected = a.var(1).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_var_2d(self): - def f(a): return a.var().realize() - def f0(a): return a.var(0).realize() - def f1(a): return a.var(1).realize() - jf = TinyJit(f) - jf0 = TinyJit(f0) - jf1 = TinyJit(f1) - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - # aixs = None - a = Tensor.rand(i, j) - symbolic = jf(a.reshape(vi, vj)).numpy() - expected = a.var().numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 0 - a = Tensor.rand(i, j) - symbolic = jf0(a.reshape(vi, vj)).reshape(j).numpy() - expected = a.var(0).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - # aixs = 1 - a = Tensor.rand(i, j) - symbolic = jf1(a.reshape(vi, vj)).reshape(i).numpy() - expected = a.var(1).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_symbolic_ops.py b/tinygrad/test/test_symbolic_ops.py deleted file mode 100644 index ab9a0387..00000000 --- a/tinygrad/test/test_symbolic_ops.py +++ /dev/null @@ -1,273 +0,0 @@ -import unittest -from tinygrad import Tensor, Variable -from tinygrad.shape.shapetracker import View -from tinygrad.helpers import Context, GlobalCounters -from tinygrad.uop.ops import sym_infer -from tinygrad.dtype import dtypes -from tinygrad.device import Device -from examples.gpt2 import Attention -import numpy as np - -class TestSymbolicOps(unittest.TestCase): - def setUp(self): - # A lot of these test are out of bounds, so we ignore the bounds check - self.context = Context(IGNORE_OOB=1) - self.context.__enter__() - - def tearDown(self): - self.context.__exit__(None, None, None) - - def test_plus1(self): - def f(a): return (a+1).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - symbolic = f(a.reshape(3, vi)).reshape(3, i).numpy() - expected = f(a).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_add(self): - def f(a, b): return (a+b).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(3, i) - symbolic = f(a.reshape(3, vi), b.reshape(3, vi)).reshape(3, i).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_matmul(self): - def f(a, b): return (a@b).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(i, 5) - symbolic = f(a.reshape(3, vi), b.reshape(vi, 5)).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_attention(self, dropout_p=0.0, imin=1, imax=5, use_symbolic=True): - def f(q, k, v): return Tensor.scaled_dot_product_attention(q.transpose(1, 2), k.transpose(1, 2), v.transpose(1, 2), dropout_p=dropout_p).realize() - for i in range(imin, imax): - vi = Variable("i", 1, 10).bind(i) if use_symbolic else i - q = Tensor.rand(2, 1, 4, 8) - k = Tensor.rand(2, i, 4, 8) - v = Tensor.rand(2, i, 4, 8) - Tensor.realize(q, k, v) - GlobalCounters.reset() - symbolic = f(q, k.reshape(2, vi, 4, 8), v.reshape(2, vi, 4, 8)).reshape(2, 4, 1, 8).numpy() - expected = f(q, k, v).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_attention_cmp_symbolic(self): - # symbolic isn't seeing if i == i, so it's not putting them on the same axis - self.test_attention(imin=4, imax=5, use_symbolic=False) - self.test_attention(imin=4, imax=5, use_symbolic=True) - - # until this works, symbolic single kernel softmax won't - @unittest.expectedFailure - def test_attention_simple_view(self): - i = Variable("i", 2, 10) - v1 = View.create((2,4,1,i,i), ((i*4),i,0,0,1)) - v2 = View.create((2,4,1,i,i,i), (((i*i)*4),(i*i),0,0,i,1)) - self.assertIsNotNone(v1+v2) - - def test_attention_training(self): - with Tensor.train(): - self.test_attention(dropout_p=0.0) - with self.assertRaises(ValueError): - # symbolic shape dropout is not supported - self.test_attention(dropout_p=0.5) - - def test_attention_pos_0_sz_0(self): - Attention(128, 8)(Tensor.ones(1, 0, 128), Variable("start_pos", 0, 128).bind(0), None) - - def test_attention_pos_0_sz_1(self): - Attention(128, 8)(Tensor.ones(1, 1, 128), Variable("start_pos", 0, 128).bind(0), None) - - def test_attention_pos_0_sz_2(self): - Attention(128, 8)(Tensor.ones(1, 2, 128), Variable("start_pos", 0, 128).bind(0), None) - - def test_cat_dim0(self): - def f(a, b): return a.cat(b, dim=0).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(i, 3) - b = Tensor.rand(2, 3) - symbolic = f(a.reshape(vi, 3), b).reshape(i+2, 3).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_cat_dim1(self): - def f(a, b): return a.cat(b, dim=1).realize() - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(3, i) - b = Tensor.rand(3, 2) - symbolic = f(a.reshape(3, vi), b).reshape(3, i+2).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_cat_dim0_two_vars(self): - def f(a, b): return a.cat(b, dim=0).realize() - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(i, 3) - b = Tensor.rand(j, 3) - symbolic = f(a.reshape(vi, 3), b.reshape(vj, 3)).reshape(i+j, 3).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_cat_dim1_two_vars(self): - def f(a, b): return a.cat(b, dim=1).realize() - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(3, i) - b = Tensor.rand(3, j) - symbolic = f(a.reshape(3, vi), b.reshape(3, vj)).reshape(3, i+j).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_two_vars_plus1_ij(self): - def f(a, b): return (a@b+1).realize() - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(i, 3) - b = Tensor.rand(3, j) - symbolic = f(a.reshape(vi, 3), b.reshape(3, vj)).reshape(i, j).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_two_vars_plus1_ji(self): - # reverse the order of variables - def f(a, b): return (a@b+1).realize() - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - a = Tensor.rand(j, 3) - b = Tensor.rand(3, i) - symbolic = f(a.reshape(vj, 3), b.reshape(3, vi)).reshape(j, i).numpy() - expected = f(a, b).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_shrink(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(7, 11) - symbolic = a.shrink(((3,5),(vi,vi+2))) - symbolic = symbolic.numpy() - expected = a.shrink(((3,5),(i,i+2))).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_slice(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(7, 11) - symbolic = a[3:5, vi:vi+2] - symbolic = symbolic.numpy() - expected = a[3:5, i:i+2].numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_expand_padded(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor(1).unsqueeze(0).pad((0, 1)).unsqueeze(0) - symbolic = a.expand(vi, 2).reshape(i, 2).numpy() - expected = a.expand(i, 2).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_slice_var_shape(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.ones(vi, 11).contiguous() - symbolic = a[:, 1:2].reshape(i, 1).numpy() - expected = a.reshape(i, 11)[:, 1:2].numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_ones_sum(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - t = Tensor.ones(i) - symbolic = t.reshape(vi).sum().item() - expected = t.sum().item() - np.testing.assert_equal(symbolic, expected) - - def test_mean(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - for axis in [None, 0, 1]: - a = Tensor.rand(i, 3) - expected = a.mean(axis).numpy() - symbolic = a.reshape(vi, 3).mean(axis).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_mean_2d(self): - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - for axis in [None, 0, 1]: - a = Tensor.rand(i, j) - expected = a.mean(axis).numpy() - symbolic = a.reshape(vi, vj).mean(axis).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_var(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - for axis in [None, 0, 1]: - a = Tensor.rand(i, 3) - expected = a.var(axis).numpy() - symbolic = a.reshape(vi, 3).var(axis).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_var_2d(self): - for i in range(1, 5): - for j in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - vj = Variable("j", 1, 10).bind(j) - for axis in [None, 0, 1]: - a = Tensor.rand(i, j) - expected = a.var(axis).numpy() - symbolic = a.reshape(vi, vj).var(axis).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) - - def test_bitcast_down(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(i, 3) - expected = a.bitcast(dtypes.uint8).numpy() - symbolic = a.reshape(vi, 3).bitcast(dtypes.uint8).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=0) - - @unittest.skipIf(Device.DEFAULT == "WEBGPU", "no uint64") - def test_bitcast_up(self): - for i in range(1, 5): - vi = Variable("i", 1, 10).bind(i) - a = Tensor.rand(i, 4) - expected = a.bitcast(dtypes.uint64).numpy() - symbolic = a.reshape(vi, 4).bitcast(dtypes.uint64).reshape(expected.shape).numpy() - np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=0) - - @unittest.expectedFailure - def test_conv2d_ceildiv_edge_case(self): - v = Variable('v', 11, 50_000) - val = 39601 - x = Tensor.randn(1, 22, 39601).reshape(1, 22, v.bind(val)) - weight = Tensor.randn(256, 22, 12) - - result = x.conv2d(weight=weight, groups=1, stride=6, dilation=1, padding=(3, 3)) - var_val = {v: val} - shape = tuple(sym_infer(s, var_val) for s in result.shape) - self.assertEqual(shape, (1, 256, 6600)) # TODO: fails if ceildiv is incorrect - # TODO: test output is correct - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_tensor.py b/tinygrad/test/test_tensor.py deleted file mode 100644 index 704f6974..00000000 --- a/tinygrad/test/test_tensor.py +++ /dev/null @@ -1,910 +0,0 @@ -import subprocess -import numpy as np -import torch -import unittest, copy, mmap, random, math, array -from tinygrad import Tensor, Device, dtypes -from tinygrad.tensor import _METADATA -from tinygrad.helpers import getenv, temp, mv_address -from extra.gradcheck import numerical_jacobian, jacobian, gradcheck -from hypothesis import given, settings, strategies as strat -from tinygrad.device import is_dtype_supported -from tinygrad.uop.ops import Ops, UOp -from tinygrad.runtime.support.compiler_cuda import PTX -from tinygrad.codegen import full_rewrite -from tinygrad.dtype import DType - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") - -x_init = np.random.randn(1,3).astype(np.float32) -U_init = np.random.randn(3,3).astype(np.float32) -V_init = np.random.randn(3,3).astype(np.float32) -W_init = np.random.randn(3,3).astype(np.float32) -m_init = np.random.randn(1,3).astype(np.float32) -gradient = np.random.randn(1,3).astype(np.float32) - -class TestTinygrad(unittest.TestCase): - def test_zerodim_initialization(self): - self.assertEqual(Tensor(55).shape, ()) - self.assertEqual(Tensor(3.14).shape, ()) - - def test_plus_equals(self): - a = Tensor.randn(10,10) - b = Tensor.randn(10,10) - c = a + b - val1 = c.numpy() - a += b - val2 = a.numpy() - np.testing.assert_allclose(val1, val2) - - def test_backward_pass(self): - def test_tinygrad(): - x = Tensor(x_init, requires_grad=True) - W = Tensor(W_init, requires_grad=True) - m = Tensor(m_init) - out = x.dot(W).relu() - out = out.log_softmax() - out = out.mul(m).add(m).sum() - out.backward() - return out.numpy(), x.grad.numpy(), W.grad.numpy() - - def test_pytorch(): - x = torch.tensor(x_init, requires_grad=True) - W = torch.tensor(W_init, requires_grad=True) - m = torch.tensor(m_init) - out = x.matmul(W).relu() - out = torch.nn.functional.log_softmax(out, dim=1) - out = out.mul(m).add(m).sum() - out.backward() - return out.detach().numpy(), x.grad, W.grad - - for x,y in zip(test_tinygrad(), test_pytorch()): - np.testing.assert_allclose(x, y, atol=1e-5) - - # A simple test is to check that we can accumulate gradients (run backward twice or more times) - def test_accumulate_gradients(self): - x = Tensor(x_init, requires_grad=True) - W = Tensor(W_init, requires_grad=True) - m = Tensor(m_init) - out = x.dot(W).relu() - out = out.log_softmax() - out = out.mul(m).add(m).sum() - out.backward() - xgrad,wgrad = x.grad, W.grad - out.backward() - xgrad2,wgrad2 = x.grad, W.grad - out.backward() # no need to retain again since we will not re-run backward - xgrad3,wgrad3 = x.grad, W.grad - np.testing.assert_allclose(xgrad3.numpy(), xgrad.numpy() * 3., atol=1e-6) - np.testing.assert_allclose(wgrad3.numpy(), wgrad.numpy() * 3., atol=1e-6) - np.testing.assert_allclose(xgrad2.numpy(), xgrad.numpy() * 2., atol=1e-6) - np.testing.assert_allclose(wgrad2.numpy(), wgrad.numpy() * 2., atol=1e-6) - - def test_second_order_backward_pass(self): - def test_pytorch(): - x_val = torch.tensor([2.0], requires_grad=True) - f = x_val**3 - first_derivative = torch.autograd.grad(outputs=f, inputs=x_val, create_graph=True)[0] - second_derivative = torch.autograd.grad(outputs=first_derivative, inputs=x_val)[0] - # d^2f/dx^2 = 6x = 6*2 = 12 - return second_derivative.numpy() - - def test_tinygrad(): - x_val = Tensor(2.0) - f = x_val**3 - first_derivative = f.gradient(x_val)[0] - second_derivative = first_derivative.gradient(x_val)[0] - return second_derivative.numpy() - - np.testing.assert_allclose(test_tinygrad(), test_pytorch(), atol=1e-5) - - # passing `gradient` to backward - def test_backward_pass_vjp(self): - def test_tinygrad(): - x = Tensor(x_init, requires_grad=True) - W = Tensor(W_init, requires_grad=True) - m = Tensor(m_init) - out = x.dot(W).relu() - out = out.log_softmax() - out = out.mul(m).add(m) - out.backward(Tensor(gradient)) - return out.numpy(), x.grad.numpy(), W.grad.numpy() - - def test_pytorch(): - x = torch.tensor(x_init, requires_grad=True) - W = torch.tensor(W_init, requires_grad=True) - m = torch.tensor(m_init) - out = x.matmul(W).relu() - out = torch.nn.functional.log_softmax(out, dim=1) - out = out.mul(m).add(m) - out.backward(torch.tensor(gradient)) - return out.detach().numpy(), x.grad, W.grad - - for x,y in zip(test_tinygrad(), test_pytorch()): - np.testing.assert_allclose(x, y, atol=1e-5) - - def test_backward_pass_diamond_model(self): - def test_tinygrad(): - u = Tensor(U_init, requires_grad=True) - v = Tensor(V_init, requires_grad=True) - w = Tensor(W_init, requires_grad=True) - x = u.mul(v).relu() - y = u.mul(w).relu() - out = x.add(y).mul(y).relu() - out = out.log_softmax() - out = out.sum() - out.backward() - return out.numpy(), u.grad.numpy(), v.grad.numpy(), w.grad.numpy() - - def test_pytorch(): - u = torch.tensor(U_init, requires_grad=True) - v = torch.tensor(V_init, requires_grad=True) - w = torch.tensor(W_init, requires_grad=True) - x = u.mul(v).relu() - y = u.mul(w).relu() - out = x.add(y).mul(y).relu() - out = torch.nn.functional.log_softmax(out, dim=1) - out = out.sum() - out.backward() - return out.detach().numpy(), u.grad, v.grad, w.grad - - for x,y in zip(test_tinygrad(), test_pytorch()): - np.testing.assert_allclose(x, y, atol=1e-5, rtol=1e-6) - - @unittest.expectedFailure - def test_const_backward_pass(self): - init = 3.5 - - def test_pytorch(): - w1 = torch.tensor(init, requires_grad=True) - w2 = torch.tensor(init, requires_grad=True) - out = w1.add(w2) - out.backward() - return w1.grad, w2.grad - - def test_tinygrad(): - w1 = Tensor(init, requires_grad=True) - w2 = Tensor(init, requires_grad=True) - out = w1.add(w2) - out.backward() - return w1.grad.numpy(), w2.grad.numpy() - - for x, y in zip(test_tinygrad(), test_pytorch()): - np.testing.assert_allclose(x, y, atol=1e-5) - - def test_nograd(self): - x = Tensor(x_init, requires_grad=False) - m = Tensor(m_init, requires_grad=False) - W = Tensor(W_init, requires_grad=True) - tmp = x.mul(m) - mm = tmp.matmul(W) - out = mm.relu() - out = out.sum() - out.backward() - assert x.grad is None - assert m.grad is None - assert tmp.grad is None - assert mm.grad is not None - assert W.grad is not None - - def test_dropout(self): - with Tensor.train(): - n, rate = 1_000_000, 0.1 - w = Tensor.ones(n).dropout(rate) - non_zeros = np.count_nonzero(w.numpy()) - expected = n * (1 - rate) - np.testing.assert_allclose(non_zeros, expected, rtol=2e-3) - - def test_jacobian(self): - W = np.random.RandomState(42069).random((10, 5)).astype(np.float32) - x = np.random.RandomState(69420).random((1, 10)).astype(np.float32) - - torch_x = torch.tensor(x, requires_grad=True) - torch_W = torch.tensor(W, requires_grad=True) - def torch_func(x): return torch.nn.functional.log_softmax(x.matmul(torch_W).relu(), dim=1) - PJ = torch.autograd.functional.jacobian(torch_func, torch_x).squeeze().numpy() - - tiny_x = Tensor(x, requires_grad=True) - tiny_W = Tensor(W, requires_grad=True) - def tiny_func(x): return x.dot(tiny_W).relu().log_softmax() - J = jacobian(tiny_func, tiny_x) - NJ = numerical_jacobian(tiny_func, tiny_x) - - np.testing.assert_allclose(PJ, J, atol = 1e-5) - np.testing.assert_allclose(PJ, NJ, atol = 1e-3) - - def test_gradcheck(self): - W = np.random.RandomState(1337).random((10, 5)).astype(np.float32) - x = np.random.RandomState(7331).random((1, 10)).astype(np.float32) - - tiny_x = Tensor(x, requires_grad=True) - tiny_W = Tensor(W, requires_grad=True) - def tiny_func(x): return x.dot(tiny_W).relu().log_softmax() - - self.assertTrue(gradcheck(tiny_func, tiny_x, eps = 1e-3)) - - # coarse approx. since a "big" eps and the non-linearities of the model - self.assertFalse(gradcheck(tiny_func, tiny_x, eps = 1e-5)) - - def test_random_fns_are_deterministic_with_seed(self): - for random_fn in [Tensor.randn, Tensor.normal, Tensor.uniform, Tensor.scaled_uniform, Tensor.glorot_uniform, Tensor.kaiming_normal]: - with self.subTest(msg=f"Tensor.{random_fn.__name__}"): - Tensor.manual_seed(1337) - a = random_fn(10,10).realize() - Tensor.manual_seed(1337) - b = random_fn(10,10).realize() - np.testing.assert_allclose(a.numpy(), b.numpy()) - - def test_randperm(self): - Tensor.manual_seed(0) - a = Tensor.randperm(10).realize() - np.testing.assert_equal(a.numpy(), [5, 2, 8, 1, 3, 7, 9, 6, 0, 4]) - b = Tensor.randperm(1000).realize() - np.testing.assert_equal(set(b.numpy()), set(range(1000))) - - def test_randn_isnt_inf_on_zero(self): - # simulate failure case of rand handing a zero to randn - original_rand, Tensor.rand = Tensor.rand, Tensor.zeros - try: self.assertNotIn(np.inf, Tensor.randn(16).numpy()) - except: raise - finally: Tensor.rand = original_rand - - def test_zeros_like_has_same_dtype_and_shape(self): - for datatype in [dtypes.float16, dtypes.float32, dtypes.int8, dtypes.int32, dtypes.int64, dtypes.uint8]: - a = Tensor([1, 2, 3], dtype=datatype) - b = Tensor.zeros_like(a) - assert a.dtype == b.dtype, f"dtype mismatch {a.dtype=} != {b.dtype}" - assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" - - a = Tensor([1, 2, 3]) - b = Tensor.zeros_like(a, dtype=dtypes.int8) - assert a.dtype == dtypes.default_int and b.dtype == dtypes.int8, "a.dtype should be int and b.dtype should be char" - assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" - - def test_ones_like_has_same_dtype_and_shape(self): - for datatype in [dtypes.float16, dtypes.float32, dtypes.int8, dtypes.int32, dtypes.int64, dtypes.uint8]: - a = Tensor([1, 2, 3], dtype=datatype) - b = Tensor.ones_like(a) - assert a.dtype == b.dtype, f"dtype mismatch {a.dtype=} != {b.dtype}" - assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" - - a = Tensor([1, 2, 3]) - b = Tensor.ones_like(a, dtype=dtypes.int8) - assert a.dtype == dtypes.default_int and b.dtype == dtypes.int8, "a.dtype should be int and b.dtype should be char" - assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" - - def test_rand_like_device(self): - a = Tensor.ones(3, 3, device="CPU") - b = Tensor.rand_like(a) - self.assertEqual(b.device, a.device) - - def test_ndim(self): - assert Tensor(1).ndim == 0 - assert Tensor.randn(1).ndim == 1 - assert Tensor.randn(2,2,2).ndim == 3 - assert Tensor.randn(1,1,1,1,1,1).ndim == 6 - - def test_argfix(self): - for f in [Tensor.zeros, Tensor.ones, Tensor.rand, Tensor.randn, Tensor.empty]: - self.assertEqual(f().shape, ()) - self.assertEqual(f(1).shape, (1,)) - self.assertEqual(f(10,20,40).shape, (10,20,40)) - self.assertEqual(f([]).shape, ()) - self.assertEqual(f([1]).shape, (1,)) - self.assertEqual(f([10,20,40]).shape, (10,20,40)) - self.assertEqual(f(()).shape, ()) - self.assertEqual(f((1,)).shape, (1,)) - self.assertEqual(f((10,20,40)).shape, (10,20,40)) - - with self.assertRaises(ValueError): f((2, 2), 2, 2) - with self.assertRaises(ValueError): f((2, 2), (2, 2)) - with self.assertRaises(ValueError): f((128, 128), 0.0, 0.01) - - def test_numel(self): - assert Tensor.randn(10, 10).numel() == 100 - assert Tensor.randn(1,2,5).numel() == 10 - assert Tensor.randn(1,1,1,1,1,1).numel() == 1 - assert Tensor([]).numel() == 0 - assert Tensor.randn(1,0,2,5).numel() == 0 - assert Tensor(3).numel() == 1 - - def test_len(self): - assert len(torch.zeros(7)) == len(Tensor.zeros(7)) - assert len(torch.zeros(10,20)) == len(Tensor.zeros(10,20)) - assert len(torch.zeros(10,20)) == len(Tensor.zeros(10,20,30)) - assert len(torch.zeros(1).flatten()) == len(Tensor.zeros(1).flatten()) - with self.assertRaises(TypeError): len(Tensor(3)) - - def test_size(self): - t1, t2 = torch.zeros(10,20), Tensor.zeros(10,20) - assert t1.size() == t2.size() - assert t1.size(0) == t2.size(0) - assert t1.size(1) == t2.size(1) - assert t1.size(-1) == t2.size(-1) - assert t1.size(-2) == t2.size(-2) - with self.assertRaises(IndexError): t2.size(2) - - def test_tolist(self): - # NOTE: float16 Tensor.tolist() requires python 3.12 - for arr in [[1,2,3], [1.5,2,3], [[1,2,3], [4,5,6]], 3]: - assert Tensor(arr).tolist() == torch.tensor(arr).tolist() == arr - - def test_element_size(self): - for _, dtype in dtypes.fields().items(): - assert dtype.itemsize == Tensor.randn(3, dtype=dtype).element_size(), f"Tensor.element_size() not matching Tensor.dtype.itemsize for {dtype}" - - def test_deepwalk_ctx_check(self): - layer = Tensor.uniform(1, 1, requires_grad=True) - x = Tensor.randn(1, 1, 1) - x.dot(layer).mean().backward() - x = Tensor.randn(1, 1, 1) - x.dot(layer).mean().backward() - - def test_zerosized_tensors(self): - np.testing.assert_equal(Tensor([]).numpy(), np.array([])) - np.testing.assert_equal(Tensor(None).numpy(), np.array([])) - - def test_tensor_ndarray_dtype(self): - arr = np.array([1]) # where dtype is implicitly int64 - assert Tensor(arr).dtype == dtypes.int64 - assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 # check if ndarray correctly casts to Tensor dtype - assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 # check that it works for something else - - def test_tensor_from_blob(self): - x = memoryview(bytearray(16)).cast('I') - - t = Tensor.from_blob(mv_address(x), (4,), dtype=dtypes.int, device="CPU") - z = (t+1) - np.testing.assert_equal(z.numpy(), [1, 1, 1, 1]) - - x[:] = array.array('I', [0, 1, 2, 3]) - z = (t+1) - np.testing.assert_equal(z.numpy(), [1, 2, 3, 4]) - - def test_tensor_list_dtype(self): - for arr in ([1], [[[1]]], [[1,1],[1,1]], [[[1,1],[1,1]],[[1,1],[1,1]]]): - assert Tensor(arr).dtype == dtypes.default_int - assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 - assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 - - for arr in ([True], [[[False]]], [[True,False],[True,False]], [[[False,True],[False,False]],[[True,True],[False,True]]]): - assert Tensor(arr).dtype == dtypes.bool - assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 - assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 - - # empty tensor defaults - for arr in ([], [[[]]], [[],[]]): - t = Tensor(arr) - assert t.dtype == dtypes.default_float - np.testing.assert_allclose(t.numpy(), np.array(arr)) - - # mixture of bool and int - for arr in ([True, 3], [[True],[3]], [[[True]], [[3]]], [[True, 3], [3, True]]): - t = Tensor(arr) - assert t.dtype == dtypes.default_int - np.testing.assert_allclose(t.numpy(), np.array(arr)) - - # mixture of bool, int and float - for arr in ([[True,True],[3.,True]], [[0,1],[3.,4]], [[[0],[1]],[[3.],[4]]], [[[True],[1]],[[3.],[4]]]): - t = Tensor(arr) - assert t.dtype == dtypes.default_float - np.testing.assert_allclose(t.numpy(), np.array(arr)) - - def test_tensor_list_shapes(self): - self.assertEqual(Tensor([[[]]]).shape, (1,1,0)) - self.assertEqual(Tensor([[],[]]).shape, (2,0)) - self.assertEqual(Tensor([[[[]],[[]]], [[[]],[[]]], [[[]],[[]]]]).shape, (3,2,1,0)) - - def test_tensor_list_errors(self): - # inhomogeneous shape - with self.assertRaises(ValueError): Tensor([[],[[]]]) - with self.assertRaises(ValueError): Tensor([[1],[]]) - with self.assertRaises(ValueError): Tensor([[1],[1],1]) - with self.assertRaises(ValueError): Tensor([[[1,1,1],[1,1]]]) - with self.assertRaises(ValueError): Tensor([[1,1,1],[[1,1,1]]]) - - def test_tensor_mixed_list_tuple(self): - def _list_or_tuple(): return list if random.random() < 0.5 else tuple - def _generate_data(depth): - if depth == 0: return _list_or_tuple()() - if depth == 1: return _list_or_tuple()([random.random(), random.random()]) - return _list_or_tuple()([_generate_data(depth-1), _generate_data(depth-1)]) - - for depth in range(7): - for _ in range(20): - data = _generate_data(depth) - np.testing.assert_allclose(Tensor(data).numpy(), np.array(data)) - - def test_tensor_list_special_values(self): - if is_dtype_supported(dtypes.float16): - data = [math.nan, -math.inf, 65504, 65519, 65519.999, 65520, 65520.1] - data = data + [-x for x in data] - with np.errstate(over='ignore'): np.testing.assert_allclose(Tensor(data, dtype=dtypes.float16).numpy(), np.array(data).astype(np.float16)) - - # uint32 - data = [1 << 33, 1 << 32, 1 << 32 - 1, 1] - data = data + [-x for x in data] - np.testing.assert_allclose(Tensor(data, dtype=dtypes.uint32).numpy(), np.array(data).astype(np.uint32)) - - # int32 - data = [1 << 33, 1 << 32, 1 << 32 - 1, 1] - data = data + [-x for x in data] - np.testing.assert_allclose(Tensor(data, dtype=dtypes.int32).numpy(), np.array(data).astype(np.int32)) - - def test_tensor_list_ndarray(self): - data = [np.array([1, 2, 3]), np.array([1, 2, 3]), np.array([1, 2, 3])] - np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) - data = [np.array([1.0, 2.0, 3.0]), np.array([1, 2, 3]), np.array([1, 2, 3])] - np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) - data = [np.array(1.0), np.array(2.0), np.array(3.0)] - np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) - - def test_tensor_dtype_errors(self): - with self.assertRaises(AttributeError): Tensor([3], dtype="typo") - with self.assertRaises(AttributeError): Tensor([3], dtype=(dtypes.int,)) - - def test_tensor_bytes(self): - data = b"abc123" - t = Tensor(data) - assert t.dtype == dtypes.uint8 - assert t.shape == (6,) - np.testing.assert_equal(t.numpy(), list(data)) - - def test_tensor_copy(self): - x = copy.deepcopy(Tensor.ones((3,3,3))) - np.testing.assert_allclose(x.numpy(), np.ones((3,3,3))) - - def test_copy_from_disk(self): - t = Tensor.randn(30).to(f"disk:{temp('test_copy_from_disk')}") - a = t[10:20] - dev = a.to(Device.DEFAULT) - np.testing.assert_allclose(a.numpy(), dev.numpy()) - - # Regression test for https://github.com/tinygrad/tinygrad/issues/1751 - def test_copy_from_numpy_unaligned(self): - # 2**15 is the minimum for repro - arr = np.random.randn(2**15).astype(np.float32) - fn = temp('test_copy_from_numpy_unaligned') - with open(fn, 'wb') as f: f.write(b't' + arr.tobytes()) - with open(fn, "a+b") as f: memview = memoryview(mmap.mmap(f.fileno(), arr.nbytes + 1)) - ua_arr = np.frombuffer(memview[1:], dtype=arr.dtype, count=arr.shape[0]) - np.testing.assert_allclose(arr, ua_arr) - assert not ua_arr.flags.aligned - # force device copy - to() is opt'd away - Tensor(dev)/1 is ignored - np.testing.assert_allclose(ua_arr, (Tensor(ua_arr)/Tensor(1)).numpy()) - - def test_item_to_tensor_to_item(self): - for a in [0, 1, 2, 3, -1, -100, 100, -101.1, 2.345, 100.1, True, False]: - item = Tensor(a).item() - assert type(item) is type(a), a - np.testing.assert_allclose(item, a), a - buffered_item = Tensor([a]).item() - assert type(buffered_item) is type(a), a - np.testing.assert_allclose(buffered_item, a), a - reshaped_item = Tensor([a]).reshape((1, 1, 1, 1, 1)).item() - assert type(reshaped_item) is type(a), a - np.testing.assert_allclose(reshaped_item, a), a - - def test_no_bool(self): - with self.assertRaises(TypeError): - if Tensor(3): - print("hi") - - with self.assertRaises(TypeError): - _a = Tensor([3]) in [Tensor([3]), Tensor([4]), Tensor([5])] - - def test_repr_with_grad(self): - a = Tensor([1.0], requires_grad=True) - b = Tensor([1]) - c = (a + b).sum().backward() - print(a) - print(c) - - def test_env_overwrite_default_device(self): - subprocess.run(['DISK=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT != \\"DISK\\""'], - shell=True, check=True) - subprocess.run(['NPY=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT != \\"NPY\\""'], - shell=True, check=True) - subprocess.run([f'{Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], - shell=True, check=True) - subprocess.run([f'DISK=1 {Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], - shell=True, check=True) - subprocess.run([f'NPY=1 {Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], - shell=True, check=True) - - def test_no_attributeerror_after_apply_uop_exception(self): - try: - Tensor.arange(4).reshape(3,2) - except ValueError: - Tensor.zeros(2, 2).realize() - - def test_shrink(self): - t = Tensor.arange(32).contiguous().realize() - self.assertListEqual(t[16:20].tolist(), [16,17,18,19]) - -@unittest.skip("this test is just flaky, sync issue") -class TestMoveTensor(unittest.TestCase): - d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" - @given(strat.sampled_from([d0, d1]), strat.sampled_from([d0, d1]), - strat.sampled_from([dtypes.float16, dtypes.float32]), strat.sampled_from([True, False, None])) - def test_to_preserves(self, src, dest, dtype, requires_grad): - if not is_dtype_supported(dtype): - return - s = Tensor([1, 2, 3], device=src, dtype=dtype, requires_grad=requires_grad) - if requires_grad: s.sum().backward() - t = s.to(dest) - np.testing.assert_equal(s.numpy(), t.numpy()) - assert s.dtype == t.dtype - assert s.requires_grad == t.requires_grad - if requires_grad: - np.testing.assert_equal(s.grad.numpy(), t.grad.numpy()) - - @given(strat.sampled_from([dtypes.float16, dtypes.float32]), strat.sampled_from([True, False, None])) - def test_shard_preserves(self, dtype, requires_grad): - s = Tensor([1, 2, 3], dtype=dtype, requires_grad=requires_grad) - t = s.shard((f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1")) - np.testing.assert_equal(s.numpy(), t.numpy()) - assert s.dtype == t.dtype - assert s.requires_grad == t.requires_grad - - @given(strat.sampled_from([d0, d1])) - def test_same_dev(self, dev): - x = Tensor([1,2,3], device=dev) - y = x.to(dev) - assert x is y - - def test_to_grad(self): - x = Tensor.eye(3, requires_grad=True, device=self.d0) - y = Tensor([[2.0,0,-2.0]], requires_grad=True, device=self.d0) - z = y.matmul(x).to(self.d1).sum() - z.backward() - np.testing.assert_equal(x.grad.numpy(), [[2,2,2],[0,0,0],[-2,-2,-2]]) - -class TestZeroShapeTensor(unittest.TestCase): - def test_shape_stride(self): - t = Tensor.empty(3, 2, 0) - assert t.shape == (3, 2, 0) - # numpy has stride 0, 0, 0; torch has stride 2, 1, 1 - assert t.uop.st.real_strides() == (0, 0, 0) - - t = Tensor.empty(3, 0, 2) - assert t.shape == (3, 0, 2) - # numpy has stride 0, 0, 0; torch has stride 2, 2, 1 - assert t.uop.st.real_strides() == (0, 0, 0) - - t = Tensor.empty(0, 0, 0) - assert t.shape == (0, 0, 0) - # numpy has stride 0, 0, 0; torch has stride 1, 1, 1 - assert t.uop.st.real_strides() == (0, 0, 0) - - def test_rand(self): - t = Tensor.rand(3, 2, 0) - assert t.shape == (3, 2, 0) - np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) - t = Tensor.rand(0) - assert t.shape == (0,) - np.testing.assert_equal(t.numpy(), np.zeros((0,))) - t = Tensor.rand(0, 0, 0) - assert t.shape == (0, 0, 0) - np.testing.assert_equal(t.numpy(), np.zeros((0, 0, 0))) - - def test_full(self): - t = Tensor.zeros(3, 2, 0) - assert t.shape == (3, 2, 0) - np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) - t = Tensor.full((3, 2, 0), 12) - assert t.shape == (3, 2, 0) - np.testing.assert_equal(t.numpy(), np.full((3, 2, 0), 12)) - - def test_reshape(self): - t = Tensor.zeros(3, 2, 0) - a = t.reshape(7, 0) - assert a.shape == (7, 0) - np.testing.assert_equal(a.numpy(), np.zeros((7, 0))) - a = t.reshape(0) - assert a.shape == (0,) - np.testing.assert_equal(a.numpy(), np.zeros((0,))) - with self.assertRaises(ValueError): - # cannot reshape from size 0 to size 1 - a = t.reshape(()) - - def test_expand(self): - t = Tensor.full((1, 2, 0), 12).expand((6, 2, 0)) - assert t.shape == (6, 2, 0) - np.testing.assert_equal(t.numpy(), np.full((6, 2, 0), 12)) - - def test_pad(self): - t = Tensor.rand(3, 2, 0).pad((None, None, (1, 1)), value=1) - assert t.shape == (3, 2, 2) - np.testing.assert_equal(t.numpy(), np.ones((3, 2, 2))) - - t = Tensor.rand(3, 2, 0).pad((None, (1, 1), None), value=1) - assert t.shape == (3, 4, 0) - np.testing.assert_equal(t.numpy(), np.ones((3, 4, 0))) - - t = Tensor.rand(3, 2, 0).pad(((1, 1), None, None), value=1) - assert t.shape == (5, 2, 0) - np.testing.assert_equal(t.numpy(), np.ones((5, 2, 0))) - - def test_shrink_into_zero(self): - t = Tensor.rand(3, 4).realize() - assert t.shrink((None, (2, 2))).realize().shape == (3, 0) - assert t.shrink(((2, 2), None)).realize().shape == (0, 4) - assert t.shrink(((2, 2), (2, 2))).realize().shape == (0, 0) - - def test_cat(self): - a = Tensor.rand(3, 2, 2) - b = Tensor.rand(3, 2, 0) - - t = a.cat(b, dim=2) - assert t.shape == (3, 2, 2) - np.testing.assert_equal(t.numpy(), a.numpy()) - - t = b.cat(a, dim=2) - assert t.shape == (3, 2, 2) - np.testing.assert_equal(t.numpy(), a.numpy()) - - t = b.cat(b, dim=0) - assert t.shape == (6, 2, 0) - np.testing.assert_equal(t.numpy(), np.zeros((6, 2, 0))) - t = b.cat(b, dim=1) - assert t.shape == (3, 4, 0) - np.testing.assert_equal(t.numpy(), np.zeros((3, 4, 0))) - t = b.cat(b, dim=2) - assert t.shape == (3, 2, 0) - np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) - - def test_elementwise(self): - a = Tensor.rand(3, 2, 0) - a_exp = a.exp() - assert a_exp.shape == (3, 2, 0) - np.testing.assert_equal(a_exp.numpy(), np.exp(a.numpy())) - - b = Tensor.rand(3, 2, 0) - assert b.shape == (3, 2, 0) - ab = a * b - assert ab.shape == (3, 2, 0) - np.testing.assert_equal(ab.numpy(), a.numpy() * b.numpy()) - - mask = (Tensor.rand(3, 2, 0) > 0.5) - assert mask.shape == (3, 2, 0) - c = mask.where(a, b) - assert c.shape == (3, 2, 0) - np.testing.assert_equal(c.numpy(), np.where(mask.numpy(), a.numpy(), b.numpy())) - - def test_reduce_over_non_zero(self): - a = Tensor.ones(3, 2, 0).sum(axis=1) - assert a.shape == (3, 0) - np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=1)) - - def test_reduce_over_zero(self): - a = Tensor.ones(3, 2, 0).sum(axis=2) - assert a.shape == (3, 2) - np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=2)) - - a = Tensor.ones(3, 2, 0).sum(axis=2, keepdim=True) - assert a.shape == (3, 2, 1) - np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=2, keepdims=True)) - - def test_clone(self): - a = Tensor.rand(16, 16).realize() - b = a.clone() - np.testing.assert_allclose(a.numpy(), b.numpy()) - self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) - - a = Tensor.rand(16, 16).mul(5.0).add(5.0).realize() - b = a.clone() - np.testing.assert_allclose(a.numpy(), b.numpy()) - self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) - - def test_clone_with_shrink(self): - a = Tensor.rand(16, 16) - b = a.shrink(((2, 10), None)).clone() - b.realize() - self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) - - def test_clone_with_shrink_realized(self): - a = Tensor.rand(16, 16).realize() - b = a.shrink(((2, 10), None)).clone() - b.realize() - self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) - - def test_clone_with_grad(self): - a = Tensor.rand(16, 16, requires_grad=True) - a.mul(5.0).add(5.0).mean().backward() - b = a.clone() - assert a.grad is not None - assert b.grad is not None - np.testing.assert_allclose(a.grad.numpy(), b.grad.numpy()) - - def test_reduce_default(self): - np.testing.assert_equal(Tensor([]).max().numpy(), -float("inf")) - np.testing.assert_equal(Tensor([]).min().numpy(), float("inf")) - np.testing.assert_equal(Tensor([]).sum().numpy(), 0) - np.testing.assert_equal(Tensor([]).mean().numpy(), float("nan")) - -class TestTensorCreationDevice(unittest.TestCase): - # test auxiliary tensors are created on the same device - def test_one_hot(self): - y = Tensor([1, 2, 3]).to("CPU") - x = y.one_hot(10) - x.realize() - -class TestTrainMode(unittest.TestCase): - def test_train_mode(self): - assert not Tensor.training - @Tensor.train() - def f(): - assert Tensor.training - f() - assert not Tensor.training - -class TestInferenceMode(unittest.TestCase): - def test_inference(self): - x = Tensor(x_init, requires_grad=True) - m = Tensor(m_init, requires_grad=True) - W = Tensor(W_init, requires_grad=True) - tmp = x.mul(m) - mm = tmp.matmul(W) - out = mm.relu() - out = out.sum() - #out.backward() - assert x.grad is None - assert m.grad is None - assert tmp.grad is None - assert mm.grad is None - assert W.grad is None - assert W.requires_grad - - def test_no_grad_mode_context_manager(self): - x = Tensor(x_init, requires_grad=True) - m = Tensor(m_init, requires_grad=True) - W = Tensor(W_init, requires_grad=True) - def f(x, m, W): - tmp = x.mul(m) - mm = tmp.matmul(W) - out = mm.relu() - out = out.sum() - #out.backward() - assert x.grad is None - assert m.grad is None - assert tmp.grad is None - assert mm.grad is None - assert W.grad is None - f(x, m, W) - -class TestTensorMetadata(unittest.TestCase): - def setUp(self) -> None: _METADATA.set(None) - - # NOOPs are not included in kernel metadata - @unittest.skip("why would this be true?") - def test_exclude_noop_metadata(self): - a = Tensor.rand(4, 4)*1 - self.assertEqual(a.uop.metadata[0].name, "__mul__") - k = a.schedule()[-1] - self.assertEqual([m.name for m in k.metadata], ["rand"]) - - # we exclude const from kernel metadata because tensor methods can share the same CONST UOp - @unittest.skip("TODO: flaky") - def test_exclude_const_metadata(self): - a = Tensor.arange(4) - b = Tensor.full((4,), -1, dtype=dtypes.int).contiguous() - sched = Tensor.schedule(a, b) - self.assertEqual([m.name for m in sched[0].metadata], ["arange"]) - self.assertEqual([m.name for m in sched[1].metadata], ["contiguous"]) - - def test_matmul(self): - x = Tensor.rand(3, requires_grad=True) - W = Tensor.rand(3, 3, requires_grad=True) - out = x.matmul(W) - self.assertEqual(out.uop.metadata[0].name, "matmul") - si = out.schedule()[-1] - self.assertEqual(len(si.metadata), 1) - self.assertEqual(si.metadata[0].name, "matmul") - - def test_relu(self): - x = Tensor.rand(3, requires_grad=True) - out = x.relu() - self.assertEqual(out.uop.metadata[0].name, "relu") - si = out.schedule()[-1] - self.assertEqual(len(si.metadata), 1) - self.assertEqual(si.metadata[0].name, "relu") - - def test_complex(self): - x = Tensor.rand(3, requires_grad=True) - y = Tensor.rand(3, requires_grad=True) - out = x.relu() * y.sigmoid() - self.assertEqual(out.uop.metadata[0].name, "__mul__") - self.assertEqual(out.uop.src[0].metadata[0].name, "relu") - self.assertEqual(out.uop.src[1].metadata[0].name, "sigmoid") - si = out.schedule()[-1] - self.assertEqual(len(si.metadata), 3) - self.assertEqual(set(m.name for m in si.metadata), {"relu", "sigmoid", "__mul__"}) - - def test_complex_backward(self): - x = Tensor.rand(3, requires_grad=True).realize() - y = Tensor.rand(3, requires_grad=True).realize() - out = (x.relu() * y.sigmoid()).sum() - self.assertEqual(out.uop.metadata[0].name, "sum") - out.backward() - self.assertEqual(x.grad.uop.metadata[0].name, "relu") - self.assertTrue(x.grad.uop.metadata[0].backward) - self.assertEqual(y.grad.uop.metadata[0].name, "sigmoid") - self.assertTrue(y.grad.uop.metadata[0].backward) - si = Tensor.schedule(out, x.grad, y.grad)[-1] - self.assertEqual(len(si.metadata), 4, f"failed with {si.metadata}") - self.assertSetEqual(set(m.name for m in si.metadata), {"sigmoid", "__mul__", "relu"}) - bw = [m for m in si.metadata if m.backward] - self.assertEqual(len(bw), 2) - self.assertEqual(bw[0].name, "sigmoid") - -class TestIdxUpcast(unittest.TestCase): - def _find_op(self, ast: UOp, op: Ops): - if ast.op is op: return ast - for src in ast.src: - if (ret:=self._find_op(src, op)) is not None: return ret - def _schedule_render(self, a: Tensor): - schedule, _ = a.schedule_with_vars() - for s in schedule: - if s.ast.op is Ops.SINK: - renderer = Device[s.bufs[0].device].renderer - uops = full_rewrite(s.ast, renderer) - renderer.render(uops) - return uops - - def _assert(self, dtype: DType, a: Tensor): - uops = self._schedule_render(a) - # Assert the dtype of the INDEX value, This will need be updated if UOp spec changes - store = next(uop for uop in uops if uop.op is Ops.STORE) - assert store.op is Ops.STORE - idx = self._find_op(store, Ops.INDEX) - if idx is not None: # PTX turns Ops.INDEX into pointer arithmetic earlier than cstyle, plus it's already cast to int64 - assert idx.op is Ops.INDEX - idx_val = idx.src[1] - assert idx_val.dtype is dtype - - # use expand to generate kernel that uses large idx - def do_op_then_assert(self, dtype: DType, dim1, dim2, dim3): - self._assert(dtype, Tensor.empty(dim1, dim2, 1).expand(-1, -1, dim3).contiguous()) - - @unittest.skipUnless(is_dtype_supported(dtypes.long), "int64 is supported") - def test_overflow(self): - # 2**11, 2**11, 2**11 -> 2**33 will overflow when indexed - self.do_op_then_assert(dtypes.long, 2048, 2048, 2048) - - @unittest.skipUnless(is_dtype_supported(dtypes.long), "int64 is supported") - def test_overflow_sym(self): - self.do_op_then_assert(dtypes.long, 2048, 2048, UOp.variable("dim3", 0, 2048).bind(32)) - - def test_regular(self): - self.do_op_then_assert(dtypes.int, 64, 64, 64) - - def test_regular_sym(self): - self.do_op_then_assert(dtypes.int, 2048, 2048, UOp.variable("dim3", 0, 64).bind(32)) - - @unittest.skipIf(PTX, "PTX always convert Ops.INDEX to int64") - def test_symfold(self): - # This would cause an overflow, but after sym fold it's within int32 - a = Tensor.arange(65535) - uops = self._schedule_render(a) - assert all(uop.dtype is not dtypes.long for uop in uops) - - @unittest.skipIf(is_dtype_supported(dtypes.long), "int64 is supported") - def test_int64_unsupported_overflow_sym(self): - with self.assertRaises(KeyError): - self.do_op_then_assert(dtypes.long, 2048, 2048, UOp.variable("dim3", 0, 2048).bind(32)) - - @unittest.skipIf(is_dtype_supported(dtypes.long), "int64 is supported") - def test_int64_unsupported_overflow(self): - with self.assertRaises(KeyError): - self.do_op_then_assert(dtypes.long, 2048, 2048, 2048) - - @unittest.skip("This is kept for reference, it requires large memory to run") - def test_overflow_kernel_run(self): - # This creates a total of 2**31+10 elements, requiring at least 2147 MB memory to run - # Modified example from issue 3271 - a = Tensor.empty(2**11, 2**11, 1, dtype=dtypes.int8).permute((2, 0, 1)).expand((2**9+10, -1, -1)).contiguous() - a.realize() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_tensor_data.py b/tinygrad/test/test_tensor_data.py deleted file mode 100644 index 214a89d5..00000000 --- a/tinygrad/test/test_tensor_data.py +++ /dev/null @@ -1,82 +0,0 @@ -import unittest, struct -from tinygrad import Tensor, dtypes - -# format types: https://docs.python.org/3/library/struct.html - -class TestTensorBytes(unittest.TestCase): - def test_bytes(self): - lst = Tensor(bytes(b"\xaa\xbb\xcc\xdd")) - assert lst.tolist() == [170, 187, 204, 221] - - def test_float_bytes(self): - lst = Tensor(bytes(struct.pack("ff", 0.234, 0.8585)), dtype=dtypes.float32) - assert lst.shape == (2,) - assert abs(lst.tolist()[0] - 0.234) < 1e-6 - assert abs(lst.tolist()[1] - 0.8585) < 1e-6 - -class TestTensorData(unittest.TestCase): - def test_data(self): - a = Tensor([1,2,3,4], dtype=dtypes.int32) - dat = a.data() - assert dat.itemsize == 4 - assert list(dat) == [1,2,3,4] - assert dat.shape == (4,) - assert dat[0] == 1 - assert dat[1] == 2 - - def test_data_empty(self): - a = Tensor([], dtype=dtypes.int32) - dat = a.data() - assert dat.itemsize == 4 - assert list(dat) == [] - assert dat.shape == (0,) - - def test_data_empty_multi_dim(self): - a = Tensor([], dtype=dtypes.int32).reshape(0, 2) - dat = a.data() - assert dat.itemsize == 4 - assert list(dat) == [] - assert dat.shape == (0,) - - def test_data_uint8(self): - a = Tensor([1,2,3,4], dtype=dtypes.uint8) - dat = a.data() - assert dat.format == "B" - assert dat.itemsize == 1 - assert dat[0] == 1 - assert dat[1] == 2 - - def test_data_nested(self): - a = Tensor([[1,2],[3,4]], dtype=dtypes.int32) - dat = a.data() - assert dat.format == "i" - assert dat.itemsize == 4 - assert dat.tolist() == [[1, 2], [3, 4]] - assert dat.shape == (2,2) - assert dat[0, 0] == 1 - assert dat[1, 1] == 4 - - def test_data_const(self): - a = Tensor(3, dtype=dtypes.int32) - dat = a.data() - assert dat.format == "i" - assert dat.itemsize == 4 - assert dat.tolist() == 3 - assert dat.shape == () - - def test_data_float32(self): - a = Tensor([[1,2.5],[3,4]], dtype=dtypes.float32) - dat = a.data() - assert dat.format == "f" - assert dat[0, 1] == 2.5 - - @unittest.skip("requires python 3.12") - def test_data_float16(self): - a = Tensor([[1,2.5],[3,4]], dtype=dtypes.float16) - dat = a.data() - assert dat.format == "e" - assert dat.shape == (2,2) - # NOTE: python can't deref float16 - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/test_tensor_uop.py b/tinygrad/test/test_tensor_uop.py deleted file mode 100644 index 19541ead..00000000 --- a/tinygrad/test/test_tensor_uop.py +++ /dev/null @@ -1,121 +0,0 @@ -#!/usr/bin/env python -import numpy as np -import unittest -from tinygrad import Tensor, Device, dtypes -from tinygrad.engine.realize import run_schedule -from tinygrad.uop.ops import Ops, UOp, UPat - -class TestTensorUOp(unittest.TestCase): - def test_fromcpu_shape_tracker(self): - def helper(a: np.ndarray): - print(a.shape, a.strides, a.flags.c_contiguous) - b = Tensor(a).uop - #assert b.st.contiguous == a.flags.c_contiguous - assert b.st.shape == a.shape - np.testing.assert_equal(a, Tensor(b).numpy()) - - for ndims in range(1, 4): - a = np.random.randn(*(4,)*ndims).astype(np.float32) - for stride in [-2, 1, 2]: - for start in [0, 1]: - helper(a[(slice(start, None, stride),)*ndims]) - - def test_shuffle_pad_ops_cmpeq(self): - y = Tensor([1]).cat(Tensor([1]) == 0).numpy() - z = Tensor([1, 0]).numpy() - np.testing.assert_allclose(y, z) - - def test_shuffle_pad_ops_div(self): - y = Tensor([1]).cat(Tensor([1]).div(Tensor([2.0]))).numpy() - z = Tensor([1, 0.5]).numpy() - np.testing.assert_allclose(y, z) - - def test_shuffle_pad_ops_log(self): - y = Tensor([1]).cat(Tensor([1]).log()).numpy() - z = Tensor([1, 0]).numpy() - np.testing.assert_allclose(y, z) - - def test_shuffle_pad_ops_exp(self): - y = Tensor([1]).cat(Tensor([1]).exp()).numpy() - z = Tensor([1, np.e]).numpy() - np.testing.assert_allclose(y, z) - - def test_device_0_is_the_same_device(self): - a = Tensor([1, 2, 3], f"{Device.DEFAULT}") - b = Tensor([1, 2, 3], f"{Device.DEFAULT}:0") - assert a.device == b.device - - def test_shrink_const_into_zero(self): - # regression test to make sure the shapetracker is preserved - a = Tensor.zeros(4,4,4).shrink((None, (0,0), None)) - b = Tensor.zeros(4,1,4) - c = a.cat(b, dim=1) - np.testing.assert_allclose(c.numpy(), np.concatenate((a.numpy(), b.numpy()), axis=1)) - - def test_shrink_const_then_cast(self): - # regression test to make sure the shapetracker is preserved - a = Tensor.zeros(4,4,4).shrink((None, (0,0), None)).cast(dtypes.int32) - b = Tensor.zeros(4,1,4) - c = a.cat(b, dim=1) - np.testing.assert_allclose(c.numpy(), np.concatenate((a.numpy(), b.numpy()), axis=1)) - - def test_const_dtype(self): - lb: UOp = Tensor([1], dtype=dtypes.int).uop - assert lb.const_like(1).base.arg == 1 - assert type(lb.const_like(1).base.arg) is int - - lb: UOp = Tensor([1], dtype=dtypes.float).uop - assert lb.const_like(1).base.arg == 1.0 - assert type(lb.const_like(1).base.arg) is float - - def test_contiguous_alu(self): - a = Tensor.randn(2, 2).realize() - b = Tensor.randn(2, 2).realize() - add = (a+b).contiguous() - out = add+2 - sched = out.schedule() - self.assertEqual(len(sched), 2) - run_schedule(sched) - np.testing.assert_allclose(out.numpy(), a.numpy()+b.numpy()+2) - - # NOTE: contiguous on a buffer collapses - def test_contiguous_empty(self): - empty = Tensor.empty(1).contiguous() - sched = empty.schedule() - self.assertEqual(len(sched), 0) - - def test_contiguous_folded_alu(self): - a = Tensor.empty(8, 8) - # NOTE: the buffer for mul_0 late folds to just a CONST - mul_0 = a*0 - out = mul_0.shrink(((4, 8), (0, 8))).contiguous() - out.realize() - self.assertEqual(out.tolist(), Tensor.zeros(4, 8).tolist()) - -reduce_kernel = UPat(Ops.SINK, src=(UPat(Ops.STORE, src=(UPat(), UPat(Ops.REDUCE_AXIS))))) -class TestReduceOp(unittest.TestCase): - def test_no_split_reduce_kernel(self): - a = Tensor.rand(4, 4).realize() - a = a.sum() - sched = a.schedule() - assert len(sched) == 1 - assert reduce_kernel.match(sched[0].ast, {}) - - def test_split_reduce_kernel_dim0(self): - a = Tensor.rand(256, 255).realize() - a = a.sum() - sched = a.schedule() - assert len(sched) == 2 - for s in sched: - assert reduce_kernel.match(s.ast, {}) - - def test_split_reduce_kernel_dim1(self): - a = Tensor.rand(255, 256).realize() - a = a.sum() - sched = a.schedule() - assert len(sched) == 2 - for s in sched: - assert reduce_kernel.match(s.ast, {}) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/test_tensor_variable.py b/tinygrad/test/test_tensor_variable.py deleted file mode 100644 index a680cf9a..00000000 --- a/tinygrad/test/test_tensor_variable.py +++ /dev/null @@ -1,96 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Tensor, Variable -from tinygrad.helpers import Context - -class TestTensorVariable(unittest.TestCase): - def test_add_tvar(self): - vv = Variable("a", 0, 10).bind(1) - ret = (Tensor(vv) + 3).item() - assert ret == 4 - - def test_inner_tvar_node(self): - vv = Variable("w", 0, 10).bind(2) - ret = Tensor.from_uop(vv * 4).item() - assert ret == 8 - - def test_inner_tvar_mul(self): - vv = Variable("w", 0, 10).bind(2) - assert (Tensor(3) * vv).item() == 6 - - def test_inner_tvar_mul_node(self): - vv = Variable("w", 0, 10).bind(2) - assert (Tensor(3) * (vv * 4)).item() == 24 - - def test_symbolic_mean(self): - with Context(IGNORE_OOB=1): - vv = Variable("a", 1, 10).bind(2) - t = Tensor.ones(2, 2).contiguous().reshape(2, vv) - ret = t.mean().item() - assert ret == 1 - - def test_symbolic_mean_2d(self): - with Context(IGNORE_OOB=1): - vv = Variable("a", 1, 10).bind(2) - vv2 = Variable("b", 1, 10).bind(2) - t = Tensor.ones(2, 2).contiguous().reshape(vv2, vv) - ret = t.mean().item() - assert ret == 1 - - def test_symbolic_mean_2d_axis_1(self): - with Context(IGNORE_OOB=1): - vv = Variable("a", 1, 10).bind(2) - vv2 = Variable("b", 1, 10).bind(2) - t = Tensor.ones(2, 2).contiguous().reshape(vv2, vv) - ret = t.mean(axis=1).reshape(2, 1).numpy() - assert np.all(ret == 1) - - def test_symbolic_mean_2d_add(self): - with Context(IGNORE_OOB=1): - add_term = Variable("c", 0, 10).bind(1) - vv = Variable("a", 1, 10).bind(1) - vv2 = Variable("b", 1, 10).bind(1) - t = Tensor.ones(2, 2).contiguous().reshape(vv2+add_term, vv+add_term) - ret = t.mean().item() - assert ret == 1 - - def test_symbolic_var(self): - with Context(IGNORE_OOB=1): - vv = Variable("a", 1, 10).bind(2) - t = Tensor.ones(2, 2).contiguous().reshape(2, vv) - ret = t.var().item() - assert ret == 0 - - def test_symbolic_pad(self): - vv = Variable("a", 1, 10).bind(2) - t = Tensor.ones(2, 2).contiguous() - t = t.pad([vv, vv, vv, vv]).mean() - ones = 4 - zeros = 6+6+4+4+6+6 - self.assertAlmostEqual(t.item(), ones/(ones+zeros)) - - def test_symbolic_arange(self): - vv = Variable("a", 1, 10) - ret = Tensor.arange(0, vv.bind(4)) - self.assertListEqual(ret.reshape(4).tolist(), [0,1,2,3]) - - def test_symbolic_arange_sym_start(self): - vv = Variable("a", 1, 6) - ret = Tensor.arange(vv.bind(4), 7) - self.assertListEqual(ret.reshape(3).tolist(), [4,5,6]) - - # TODO: add vmin/vmax pattern for symbolic denominator - @unittest.expectedFailure - def test_symbolic_arange_sym_step(self): - vv = Variable("step", 1, 3) - ret = Tensor.arange(0, 10, vv.bind(2)) - self.assertListEqual(ret.reshape(5).tolist(), [0,2,4,6,8]) - - def test_symbolic_arange_two_vars(self): - begin = Variable("b", 1, 5) - end = Variable("e", 6, 10) - ret = Tensor.arange(begin.bind(4), end.bind(7)) - self.assertListEqual(ret.reshape(3).tolist(), [4,5,6]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_tiny.py b/tinygrad/test/test_tiny.py deleted file mode 100644 index 0d6798fb..00000000 --- a/tinygrad/test/test_tiny.py +++ /dev/null @@ -1,119 +0,0 @@ -# basic self-contained tests of the external functionality of tinygrad -import unittest, random -from tinygrad import Tensor, Context, Variable, TinyJit, dtypes, Device, nn -from tinygrad.helpers import IMAGE, CI - -class TestTiny(unittest.TestCase): - - # *** basic functionality *** - - def test_plus(self): - out = Tensor([1.,2,3]) + Tensor([4.,5,6]) - self.assertListEqual(out.tolist(), [5.0, 7.0, 9.0]) - - def test_plus_int(self): - out = Tensor([1,2,3], dtype=dtypes.int) + Tensor([4,5,6], dtype=dtypes.int) - self.assertListEqual(out.tolist(), [5, 7, 9]) - - def test_plus_big(self): - out = Tensor.ones(16).contiguous() + Tensor.ones(16).contiguous() - self.assertListEqual(out.tolist(), [2]*16) - - def test_cat(self): - out = Tensor.cat(Tensor.ones(8).contiguous(), Tensor.ones(8).contiguous()) - self.assertListEqual(out.tolist(), [1]*16) - - def test_sum(self): - out = Tensor.ones(256).contiguous().sum() - self.assertEqual(out.item(), 256) - - def test_gemm(self, N=64, out_dtype=dtypes.float): - a = Tensor.ones(N,N).contiguous() - b = Tensor.eye(N).contiguous() - self.assertListEqual((out:=a@b).flatten().tolist(), [1.0]*(N*N)) - if IMAGE < 2: self.assertEqual(out.dtype, out_dtype) - - # *** randomness *** - - def test_random(self): - out = Tensor.rand(10) - for x in out.tolist(): - self.assertGreaterEqual(x, 0.0) - self.assertLessEqual(x, 1.0) - - # *** JIT (for Python speed) *** - - def test_jit(self): - cnt = 0 - random.seed(0) - def new_rand_list(ln=10): return [random.randint(0, 100000) for _ in range(ln)] - - @TinyJit - def fxn(a,b) -> Tensor: - nonlocal cnt - cnt += 1 - return a+b - - for _ in range(3): - la,lb = new_rand_list(), new_rand_list() - fa,fb = Tensor(la), Tensor(lb) - ret = fxn(fa, fb) - # math is correct - self.assertListEqual(ret.tolist(), [a+b for a,b in zip(la, lb)]) - - # function is only called twice - self.assertEqual(cnt, 2) - - # *** BEAM (for Kernel speed) *** - - def test_beam(self): - with Context(BEAM=1, IGNORE_BEAM_CACHE=1): self.test_plus() - - # *** symbolic (to allow less recompilation) *** - - def test_symbolic(self): - i = Variable('i', 1, 10) - with Context(IGNORE_OOB=1): - for s in [2,5]: - ret = Tensor.ones(s).contiguous().reshape(i.bind(s)) + 1 - self.assertListEqual(ret.reshape(s).tolist(), [2.0]*s) - - def test_symbolic_reduce(self): - i = Variable('i', 1, 10) - with Context(IGNORE_OOB=1): - for s in [2,5]: - ret = Tensor.ones(s).contiguous().reshape(i.bind(s)).sum() - self.assertEqual(ret.item(), s) - - # *** a model *** - - # TODO: this is failing because of how swizzling rewrites the ShapeTracker of the final STORE - @unittest.skipIf(IMAGE>0 or (CI and Device.DEFAULT == "DSP"), "failing because of make things that can't be images not images") - def test_mnist(self): - layers = [ - nn.Conv2d(1, 32, 5), Tensor.relu, - nn.Conv2d(32, 32, 5), Tensor.relu, - nn.BatchNorm(32), Tensor.max_pool2d, - nn.Conv2d(32, 64, 3), Tensor.relu, - nn.Conv2d(64, 64, 3), Tensor.relu, - nn.BatchNorm(64), Tensor.max_pool2d, - lambda x: x.flatten(1), nn.Linear(576, 10)] - - # replace random weights with ones - for p in nn.state.get_parameters(layers): p.replace(Tensor.ones_like(p).contiguous()).realize() - - # run model inference - probs = Tensor.rand(1, 1, 28, 28).sequential(layers).tolist() - self.assertEqual(len(probs[0]), 10) - - # *** image *** - - @unittest.skipIf(Device.DEFAULT != "GPU", "image only supported on GPU") - def test_image(self): - with Context(IMAGE=2): self.test_gemm(N=4, out_dtype=dtypes.imagef((4, 1, 4))) - - def test_beam_image(self): - with Context(BEAM=1, IGNORE_BEAM_CACHE=1): self.test_image() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_to_numpy.py b/tinygrad/test/test_to_numpy.py deleted file mode 100644 index deaa9fc9..00000000 --- a/tinygrad/test/test_to_numpy.py +++ /dev/null @@ -1,17 +0,0 @@ -from tinygrad.tensor import Tensor -import numpy as np -import pickle -import unittest - -class TestToNumpy(unittest.TestCase): - def test_numpy_is_numpy(self): - output = Tensor.ones((1, 3, 4096)).realize().numpy() - new = np.copy(output) - print(type(new)) - serialized = pickle.dumps(new) - out = pickle.loads(serialized) - assert out.shape == (1,3,4096) - assert (out==1).all() - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/test_transcendental.py b/tinygrad/test/test_transcendental.py deleted file mode 100644 index 932cfa29..00000000 --- a/tinygrad/test/test_transcendental.py +++ /dev/null @@ -1,163 +0,0 @@ -import unittest -from tinygrad import Tensor, Device, dtypes -from tinygrad.tensor import _to_np_dtype -from tinygrad.helpers import Context, getenv, CI, OSX -from test.test_schedule import check_schedule -from test.test_dtype_alu import ht, dtypes_float -from tinygrad.device import is_dtype_supported -import numpy as np -import math -from hypothesis import given, settings, strategies as strat - -settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) -settings.load_profile("my_profile") - -class TestTranscendentalMath(unittest.TestCase): - @unittest.skipUnless(is_dtype_supported(dtypes.float64, Device.DEFAULT), f"no float64 on {Device.DEFAULT}") - @unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}, "crashed") - @given(ht.float64, strat.sampled_from([(Tensor.exp, np.exp), (Tensor.log, np.log), (Tensor.sin, np.sin)])) - def test_float64(self, x, op): - if op[0] == Tensor.sin: - # TODO: reduction does not work # 536870912.125 # 2914593.01171875 # 134217728.03125 # 230581075.65625 # 139216373.71875 - if abs(x) > 100_000_000: return - with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): - np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float64)).numpy(), - op[1](np.array([x], dtype=_to_np_dtype(dtypes.float64))), - atol=3e-2, rtol=1e-5) # sin can have bigger atol for very big x - - @unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}, "crashed") - @given(ht.float32, strat.sampled_from([(Tensor.exp, np.exp),(Tensor.log, np.log)] + - ([(Tensor.sin, np.sin)] if is_dtype_supported(dtypes.ulong) else []))) - def test_float32(self, x, op): - # wrong nan behavior on Vulkan - if (math.isnan(x) or (x < 0 and op[0] == Tensor.log)) and CI and Device.DEFAULT == "WEBGPU" and not OSX: return - with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): - np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float32)).numpy(), - op[1](np.array([x], dtype=_to_np_dtype(dtypes.float32))), - atol=2e-5, rtol=1e-5) - - @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") - @given(ht.float16, strat.sampled_from([(Tensor.exp, np.exp),(Tensor.log, np.log)] + - ([(Tensor.sin, np.sin)] if is_dtype_supported(dtypes.ulong) else []))) - def test_float16(self, x, op): - # wrong nan behavior on Vulkan - if (math.isnan(x) or (x < 0 and op[0] == Tensor.log)) and CI and Device.DEFAULT == "WEBGPU" and not OSX: return - with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): - np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float16)).numpy(), - op[1](np.array([x], dtype=_to_np_dtype(dtypes.float16))), - atol=1e-2, rtol=5e-3) # exp can have bigger rtol - - @given(strat.sampled_from([(dtypes.float64, 709.5), (dtypes.float32, 88.7), (dtypes.float16, 11)])) - def test_exp_near_inf(self, dtype_x): - # reordering compute might return inf - dtype, x = dtype_x - if not is_dtype_supported(dtype): return - with Context(TRANSCENDENTAL=2): - y = Tensor([x], dtype=dtype).exp().numpy() - expected = np.exp(np.array([x], dtype=_to_np_dtype(dtype))) - np.testing.assert_allclose(y, expected, rtol=5e-3) - -class TestFromFuzzer(unittest.TestCase): - @given(strat.sampled_from(dtypes_float)) - @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") - def test_sin(self, dtype): - if not is_dtype_supported(dtype): return - if dtype == dtypes.float64: - # crashes in CI CUDA - if getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}: return - def _test_value(n: float, unit: float=1.0): - next_float = np.nextafter(1.0, 2.0, dtype=_to_np_dtype(dtype)) - ulp = next_float - 1.0 - ulp = unit * ulp - with Context(TRANSCENDENTAL=2): - np.testing.assert_allclose(Tensor([n], dtype=dtype).sin().numpy(), np.sin(np.array([n], dtype=_to_np_dtype(dtype))), atol=ulp, rtol=1e-5) - _test_value(-35.0) - _test_value(-25.0) - _test_value(25.0) - _test_value(30.0) # 30.0 == switch_over - _test_value(35.0) - _test_value(0.0) - _test_value(np.pi / 2) - # worst case of ulp 1.5 - _test_value(np.pi * 2, unit=1.5) - - @given(strat.sampled_from(dtypes_float)) - @unittest.skipIf(Device.DEFAULT == "WEBGPU" and CI, "Nan location mismatch on Vulkan, Metal works") - def test_log2(self, dtype): - if not is_dtype_supported(dtype): return - if dtype == dtypes.float64: - # crashes in CI CUDA - if getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}: return - def _test_value(n: float, unit: float=1.0): - next_float = np.nextafter(1.0, 2.0, dtype=_to_np_dtype(dtype)) - ulp = next_float - 1.0 - ulp = unit * ulp - with Context(TRANSCENDENTAL=2): - np.testing.assert_allclose(Tensor([n], dtype=dtype).log2().numpy(), np.log2(np.array([n], dtype=_to_np_dtype(dtype))), atol=ulp, rtol=1e-5) - fmin = np.finfo(_to_np_dtype(dtype)).tiny - for scale in [1.0, 1e10, 1e20, 1e30]: - _test_value(fmin * scale) - _test_value(-fmin * scale) - _test_value(0) - _test_value(0.0000009) - -class TestTranscendentalSchedule(unittest.TestCase): - @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") - def test_transcendental_sin_fusion(self): - with Context(TRANSCENDENTAL=2): - a = Tensor.empty(10) - b = Tensor.empty(10) - c = a.sin() + b.sin() - c = c.sin() - check_schedule(c, 1) - - def test_transcendental_log2_fusion(self): - with Context(TRANSCENDENTAL=2): - a = Tensor.empty(10) - b = Tensor.empty(10) - c = a.log2() + b.log2() - c = c.log2() - check_schedule(c, 1) - - def test_transcendental_exp2_fusion(self): - with Context(TRANSCENDENTAL=2): - a = Tensor.empty(10) - b = Tensor.empty(10) - c = a.exp2() + b.exp2() - c = c.exp2() - check_schedule(c, 1) - -class TestTranscendentalVectorized(unittest.TestCase): - def _vectorized_data(self, low, high, vec_size): - np_data = np.linspace(low, high, num=(128 // vec_size) * vec_size, dtype=np.float32).reshape(-1, vec_size) - data = Tensor(np_data, dtype=dtypes.float32.vec(vec_size)) - return data, np_data - - def _test_vectorized_op(self, fxn, np_fxn, data_range, vec_size, param_range=None): - data, np_data = self._vectorized_data(data_range[0], data_range[1], vec_size) - if param_range: - param, np_param = self._vectorized_data(param_range[0], param_range[1], vec_size) - out, np_out = fxn(data, param), np_fxn(np_data, np_param) - else: - out, np_out = fxn(data), np_fxn(np_data) - np.testing.assert_allclose(out.numpy(), np_out, rtol=1e-4) - - def test_exp2_vectorized(self): - for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.exp2, np.exp2, (-100, 100), vec_size) - - def test_log2_vectorized(self): - for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.log2, np.log2, (0.001, 200), vec_size) - - @unittest.skipIf(getenv("DSP"), "requires int division") - def test_sin_vectorized(self): - for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.sin, np.sin, (-100, 100), vec_size) - - def test_pow_vectorized(self): - # np.pow returns nan for negative values raised to a non-integral power - for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.pow, np.pow, (0.001, 200), vec_size, param_range=(-10, 10)) - - def test_sqrt_vectorized(self): - for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.sqrt, np.sqrt, (0, 100), vec_size) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/test_uop_graph.py b/tinygrad/test/test_uop_graph.py deleted file mode 100644 index 0ad6f072..00000000 --- a/tinygrad/test/test_uop_graph.py +++ /dev/null @@ -1,746 +0,0 @@ -from typing import List -import unittest, pytest -from tinygrad import dtypes, Variable -from tinygrad.helpers import DEBUG, Context -from tinygrad.uop.ops import Ops, UOp, UPat, PatternMatcher, track_rewrites, graph_rewrite, GroupOp -from tinygrad.codegen.symbolic import sym -from tinygrad.codegen import full_rewrite, full_rewrite_to_sink -from tinygrad.codegen.expander import expander - -simple_pm = PatternMatcher([ - (UPat.cvar('x', dtypes.int), lambda x: UOp.const(dtypes.float, 1.0) + UOp.const(dtypes.float, 2.0)), - (UPat.cvar('x') + UPat.cvar('y'), lambda x,y: UOp.const(dtypes.float, x.arg+y.arg)), - (UPat.cvar('x') * UPat.cvar('y') * UPat.cvar('z'), lambda x,y,z: UOp.const(dtypes.float, x.arg*y.arg*z.arg)), - ((UPat.var('x') + UPat.cvar('c1')) + UPat.cvar('c2'), lambda x,c1,c2: x + (c1.arg+c2.arg)), -]) - -def to_uops_list(u:List[UOp]) -> List[UOp]: - # we strip the SINK here for legacy reasons - ret = full_rewrite(UOp.sink(*u)) - assert ret[-1].op is Ops.SINK - return ret[:-1] - -class TestGraphRewriteConst(unittest.TestCase): - def test_gep_const(self): - v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) - v2 = v1.gep(1) - ret = graph_rewrite(v2, sym) - self.assertEqual(ret.dtype, dtypes.int) - self.assertEqual(ret.arg, 1) - - def test_gep_const_single(self): - v1 = UOp.const(dtypes.int.vec(3), 4) - v2 = v1.gep(1) - ret = graph_rewrite(v2, sym) - self.assertEqual(ret.dtype, dtypes.int) - self.assertEqual(ret.arg, 4) - - def test_add_const(self): - v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) - v2 = UOp.const(dtypes.int.vec(3), (5,6,7)) - ret = graph_rewrite(v1+v2, sym) - self.assertEqual(ret.op, Ops.VCONST) - self.assertEqual(ret.dtype, dtypes.int.vec(3)) - self.assertEqual(ret.arg, (5,7,9)) - - def test_add_const_lose_v(self): - v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) - v2 = UOp.const(dtypes.int.vec(3), (2,1,0)) - ret = graph_rewrite(v1+v2, sym) - self.assertEqual(ret.op, Ops.CONST) - self.assertEqual(ret.dtype, dtypes.int.vec(3)) - self.assertEqual(ret.arg, 2) - -xfail_broken_const_wraparound = pytest.mark.xfail(reason="const folding does not properly implement modular arithmetic") -class TestModularWraparound(unittest.TestCase): - def _test(self, uop:UOp, expected:int): - results = to_uops_list([uop]) - self.assertEqual(len(results), 1) - self.assertEqual(results[0].op, Ops.CONST) - self.assertEqual(results[0].dtype, uop.dtype) - self.assertEqual(results[0].arg, expected) - - @xfail_broken_const_wraparound - def test_cast(self): - t = self._test - t(UOp.const(dtypes.uint, 0xABCD17D6).cast(dtypes.uint8), 0xD6) - t(UOp.const(dtypes.uint, 0xABCD17D6).cast(dtypes.uint8).cast(dtypes.uint), 0xD6) - - @xfail_broken_const_wraparound - def test_mul(self): - t = self._test - t(UOp.const(dtypes.uint, 0xABCD17D6) * 0xAABBCCDD, 1147018174) - t(UOp.const(dtypes.int, 0xABCD17D6) * 10, -1241321892) - - @xfail_broken_const_wraparound - def test_div(self): - t = self._test - t(UOp.const(dtypes.uint, 0xABCD17D6) * 0xAABBCCDD // 11, 104274379) - t(UOp.const(dtypes.int, 0xABCD17D6) * 10 // 11, -112847444) - - @xfail_broken_const_wraparound - def test_neg(self): - t = self._test - t(-UOp.const(dtypes.uint8, 1), 0xFF) - t(-UOp.const(dtypes.uint16, 1), 0xFFFF) - t(-UOp.const(dtypes.uint32, 1), 0xFFFFFFFF) - t(-UOp.const(dtypes.uint64, 1), 0xFFFFFFFFFFFFFFFF) - - @xfail_broken_const_wraparound - def test_neg_min_int(self): - t = self._test - t(-UOp.const(dtypes.int8, -2**7), -2**7) - t(-UOp.const(dtypes.int16, -2**15), -2**15) - t(-UOp.const(dtypes.int32, -2**31), -2**31) - t(-UOp.const(dtypes.int64, -2**63), -2**63) - - @xfail_broken_const_wraparound - def test_payne_hanek_reduction_bug(self): - t = self._test - a = (UOp.const(dtypes.uint, 43748177600).cast(dtypes.uint) | 36).cast(dtypes.ulong) - b = 2536655455 * a + 4294967296 * UOp.const(dtypes.ulong, 25366554550) - c = (b + 2261737165) // 4611686018427387904 - t(c, 0) - -class TestGraphRewrite(unittest.TestCase): - def test_dedup(self): - v1 = UOp(Ops.DEFINE_VAR, dtypes.float) - v2 = UOp(Ops.DEFINE_VAR, dtypes.float) - nout = graph_rewrite(v1+v2, PatternMatcher([])) - self.assertIs(nout.src[0], nout.src[1]) - - # NOTE: this shows why we can't have a UOp in arg - @unittest.expectedFailure - def test_no_dedup_args(self): - a1 = UOp(Ops.DEFINE_VAR, dtypes.int, (), ("a1", UOp.const(dtypes.int, 0), UOp.const(dtypes.int, 11))) - a2 = UOp(Ops.DEFINE_VAR, dtypes.int, (), ("a2", UOp.const(dtypes.int, 0), UOp.const(dtypes.int, 11))) - sink = a1.sink(a2) - define_vars = [x for x in graph_rewrite(sink, PatternMatcher([])).toposort() if x.op is Ops.DEFINE_VAR] - self.assertEqual(len(define_vars), 1) - - def test_simple(self): - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - nout = graph_rewrite(c1+c2, simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 3.0) - - def test_depth_2_late(self): - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - c3 = UOp.const(dtypes.float, 3.0) - nout = graph_rewrite(c1*c2*(c3+c3), simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 12.0) - - def test_double(self): - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - c3 = UOp.const(dtypes.float, 3.0) - nout = graph_rewrite(c1+c2+c3, simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 6.0) - - def test_triple(self): - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - c3 = UOp.const(dtypes.float, 3.0) - c4 = UOp.const(dtypes.float, 4.0) - nout = graph_rewrite(c1+c2+c3+c4, simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 10.0) - - def test_diamond(self): - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - c3 = UOp.const(dtypes.float, 3.0) - nout = graph_rewrite((c1+c2)+(c1+c3), simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 7.0) - - def test_magic_4(self): - c1 = UOp.const(dtypes.int, 4.0) - nout = graph_rewrite(c1, simple_pm) - self.assertEqual(nout.op, Ops.CONST) - self.assertEqual(nout.arg, 3.0) - - def test_depth_2_fold(self): - v = UOp(Ops.DEFINE_VAR, dtypes.float) - c1 = UOp.const(dtypes.float, 1.0) - c2 = UOp.const(dtypes.float, 2.0) - nout = graph_rewrite(v+c1+c2, simple_pm) - self.assertEqual(nout.op, Ops.ADD) - self.assertEqual(nout.src[0].op, Ops.DEFINE_VAR) - self.assertEqual(nout.src[1].op, Ops.CONST) - self.assertEqual(nout.src[1].arg, 3.0) - - def test_commutative_work(self): - a = UOp.variable('a', 0, 1) - b = UOp.variable('b', 0, 1) - self.assertIs((a+b).simplify(), (b+a).simplify()) - - def test_consts_go_last_right_away(self): - a = UOp.variable('a', 0, 1) - tst = (2+a).simplify() - self.assertIs(tst.src[0], a) - self.assertIs(tst.src[1], a.const_like(2)) - - def test_consts_go_last(self): - a = UOp.variable('a', 0, 1) - b = UOp.variable('b', 0, 1) - c = UOp.variable('c', 0, 1) - d = UOp.variable('d', 0, 1) - outs = [2+a, 2+a+d+3+b+c+4, UOp(Ops.ADD, a.dtype, src=(a.const_like(2), a)), (4+d)+c+(2+a)+b] - for out in outs: - sink = graph_rewrite(out, sym) - print(sink.render()) - self.assertEqual(sink.op, Ops.ADD) - self.assertEqual(sink.src[1].op, Ops.CONST) - self.assertEqual(len([x for x in sink.toposort() if x.op is Ops.CONST]), 1) - -class TestUOpGraph(unittest.TestCase): - def test_add_constant_fold(self): - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - out = UOp(Ops.ADD, dtypes.float, (c1, c2)) - uops = to_uops_list([out]) - self.assertEqual(len(uops), 1) - out = uops[-1] - self.assertEqual(out.op, Ops.CONST) - self.assertEqual(out.arg, 3.0) - - def test_where_same_fold(self): - v = UOp.variable('tmp', 0, 1) - c0 = UOp(Ops.CONST, dtypes.int, arg=0) - vc = UOp(Ops.CMPNE, dtypes.bool, (v, c0)) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - out = UOp(Ops.WHERE, dtypes.float, (vc, c1, c1)) - uops = to_uops_list([out]) - self.assertEqual(len(uops), 1) - out = uops[-1] - self.assertEqual(out.op, Ops.CONST) - self.assertEqual(out.arg, 1.0) - - def test_where_const_fold(self): - bf = UOp(Ops.CONST, dtypes.bool, arg=False) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - out = UOp(Ops.WHERE, dtypes.float, (bf, c1, c2)) - uops = to_uops_list([out]) - self.assertEqual(len(uops), 1) - out = uops[-1] - self.assertEqual(out.op, Ops.CONST) - self.assertEqual(out.arg, 2.0) - - def test_const_cast(self): - bf = UOp(Ops.CONST, dtypes.bool, arg=False) - out = UOp(Ops.CAST, dtypes.int, (bf,)) - uops = to_uops_list([out]) - self.assertEqual(len(uops), 1) - out = uops[-1] - self.assertEqual(out.op, Ops.CONST) - self.assertEqual(out.arg, 0) - - @unittest.skip("this test isn't valid uops") - def test_noop_vectorize_fold(self): - d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0) - idx = UOp.const(dtypes.int, 0) - ld = UOp(Ops.LOAD, dtypes.float.vec(2), (d0, idx)) - vec = UOp(Ops.VECTORIZE, dtypes.float.vec(2), (ld,)) - x = UOp(Ops.GEP, dtypes.float, (vec, ), arg=0) - alu = UOp(Ops.SQRT, dtypes.float, (x, )) - out = UOp(Ops.STORE, dtypes.void, (d0, idx, alu)) - uops = to_uops_list([out]) - self.assertEqual(len([x for x in uops if x.op is Ops.VECTORIZE]), 0) - - def test_gep_vec_fold(self): - d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) - d2 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 2) - idx = UOp.const(dtypes.int, 0) - def _test_vec(geps, count=4): - vec = UOp(Ops.VECTORIZE, dtypes.float.vec(count), geps) - out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), vec)) - uops = to_uops_list([out]) - if DEBUG >= 4: - from tinygrad import Device - print(Device[Device.DEFAULT].renderer.render(uops)) - return uops[-1].src[-1] - - # possible - val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) - xyzw = tuple(UOp(Ops.GEP, dtypes.float, (val,), (i,)) for i in range(4)) - self.assertIs(_test_vec(xyzw).op, Ops.LOAD) - - # unaligned - val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) - wzyx = tuple(UOp(Ops.GEP, dtypes.float, (val,), (i,)) for i in reversed(range(4))) - self.assertIs(_test_vec(wzyx).op, Ops.VECTORIZE) - - # different_size - val = UOp(Ops.LOAD, dtypes.float.vec(2), (d1.index(idx),)) - xy = tuple(UOp(Ops.GEP, dtypes.float, (val, ), (i,)) for i in range(2)) - self.assertIs(_test_vec(xy+xy).op, Ops.VECTORIZE) - val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) - xy = tuple(UOp(Ops.GEP, dtypes.float, (val, ), (i,)) for i in range(2)) - self.assertIs(_test_vec(xy, count=2).op, Ops.VECTORIZE) - - # different vals - val1 = UOp(Ops.LOAD, dtypes.float.vec(2), (d1.index(idx),)) - val2 = UOp(Ops.LOAD, dtypes.float.vec(2), (d2.index(idx),)) - xy1 = tuple(UOp(Ops.GEP, dtypes.float, (val1, ), (i,)) for i in range(2)) - xy2 = tuple(UOp(Ops.GEP, dtypes.float, (val2, ), (i,)) for i in range(2)) - self.assertIs(_test_vec(xy1+xy2).op, Ops.VECTORIZE) - - def test_gep_vec_const_fold(self): - for vec_size in [2, 4, 8]: - consts = [UOp.const(dtypes.float, float(i)) for i in range(vec_size)] - vec = UOp(Ops.VECTORIZE, dtypes.float.vec(vec_size), tuple(consts)) - uops = to_uops_list([UOp(Ops.GEP, dtypes.float, (vec,), (i,)) for i in range(vec_size)]) - for uop, const in zip(uops, consts): - self.assertEqual(uop, const) - - def test_wmma_vectorize_fold(self): - for i in [2, 4, 8]: - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), tuple(UOp.const(dtypes.half, 0.0) for _ in range(i))) - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i)) - acc = UOp.variable('acc', 0, 1, dtypes.half.vec(i)) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[0], acc) - self.assertEqual(len(uops), 1) - - for i in [2, 4, 8]: - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i)) - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), tuple(UOp.const(dtypes.half, 0.0) for _ in range(i))) - acc = UOp.variable('acc', 0, 1, dtypes.half.vec(i)) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[0], acc) - self.assertEqual(len(uops), 1) - - @unittest.skip("wmma is wrong here, it needs an arg") - def test_wmma_vectorize_no_fold(self): - for i in [4, 8]: - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), - tuple(UOp.const(dtypes.half, 0.0) for _ in range(i//2)) + - tuple(UOp(Ops.DEFINE_VAR, dtypes.half, arg=(f'tmp{j}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) for j in range(i//2))) - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[-1], wmma) - - for i in [4, 8]: - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), - tuple(UOp.const(dtypes.half, 0.0) for _ in range(i//2)) + - tuple(UOp(Ops.DEFINE_VAR, dtypes.half, arg=(f'tmp{j}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) for j in range(i//2))) - acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[-1], wmma) - - for i in [2, 4, 8]: - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), - tuple(UOp.const(dtypes.half, 1.0 if j == 0 else 0.0) for j in range(i))) - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[-1], wmma) - - for i in [2, 4, 8]: - var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), - tuple(UOp.const(dtypes.half, 1.0 if j == 0 else 0.0) for j in range(i))) - acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) - wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) - uops = to_uops_list([wmma]) - self.assertEqual(uops[-1], wmma) - - def test_cast_alu_fold(self): - d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(), arg=0) - d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=1) - idx = UOp.const(dtypes.int, 0) - ld = UOp(Ops.LOAD, dtypes.int, (d1.index(idx),)) - alu = (ld<1).cast(dtypes.bool) - out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), alu)) - uops = to_uops_list([out]) - self.assertEqual(len([x for x in uops if x.op is Ops.CAST]), 0) - - def test_double_cast_fold(self): - d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0) - d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=1) - idx = UOp.const(dtypes.int, 0) - ld = UOp(Ops.LOAD, dtypes.int, (d1.index(idx),)) - alu = ld.cast(dtypes.float).cast(dtypes.float) - out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), alu)) - uops = to_uops_list([out]) - self.assertEqual(len([x for x in uops if x.op is Ops.CAST]), 1) - - def test_depth_2_const_fold(self): - v = UOp.variable("tmp", 0, 1) - c2 = UOp(Ops.CONST, dtypes.int, arg=2) - c4 = UOp(Ops.CONST, dtypes.int, arg=4) - vc = UOp(Ops.ADD, dtypes.int, (v, c2)) - out = UOp(Ops.ADD, dtypes.int, (vc, c4)) - uops = to_uops_list([out]) - self.assertEqual(len(uops), 3) - out = uops[-1] - self.assertEqual(out.op, Ops.ADD) - self.assertEqual(out.src[1].op, Ops.CONST) - self.assertEqual(out.src[1].arg, 6) - - def test_bitcast_to_same_dtype_fold(self): - for dt in dtypes.ints + dtypes.floats + (dtypes.bool,): - d0 = UOp(Ops.DEFINE_GLOBAL, dt.ptr(), arg=0) - v = UOp(Ops.LOAD, dt, (d0.index(UOp.const(dtypes.int, 0)),)) - uops = to_uops_list([v.bitcast(dt)]) - self.assertEqual(len([x for x in uops if x.op is Ops.BITCAST]), 0, f"dtype = {dt}") - - def test_in_out_of_bounds_access(self): - with Context(IGNORE_OOB=0): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 0)),)) - to_uops_list([ld0]) - ld1 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 15)),)) - to_uops_list([ld1]) - ld1 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 7)),)) - to_uops_list([ld1]) - - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 42)),)) - with self.assertRaises(RuntimeError): to_uops_list([ld0]) - - def test_in_out_of_bounds_access_symbolic(self): - with Context(IGNORE_OOB=0): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 1, 10)),)) - to_uops_list([ld0]) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 0, 15)),)) - to_uops_list([ld0]) - - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 0, 20)),)) - with self.assertRaises(RuntimeError): to_uops_list([ld0]) - - def test_out_of_bounds_off_by_one_access(self): - with Context(IGNORE_OOB=0): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 16)),)) - with self.assertRaises(RuntimeError): to_uops_list([ld0]) - - def test_in_out_bounds_access_with_mask(self): - with Context(IGNORE_OOB=0): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) - gidx0 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx0", 42)) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(gidx0, (5=0)&(ld0<32)),)) - to_uops_list([ld1]) - - ld1 = UOp(Ops.LOAD, dtypes.int, (glbl1.index(ld0*2, (ld0>=0)&(ld0<64)),)) - with self.assertRaises(RuntimeError): to_uops_list([ld1]) - - def test_fold_gated_load(self): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - glbl1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 1) - glbl2 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 2) - idx = UOp.const(dtypes.int, 0) - ld0 = UOp(Ops.LOAD, dtypes.int, (glbl1.index(idx, UOp.const(dtypes.bool, False)),)) - ld1 = UOp(Ops.LOAD, dtypes.int, (glbl2.index(idx, UOp.const(dtypes.bool, True)),)) - uops = to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0.index(idx), ld1+ld0))]) - ld0 = uops[-1].src[-1] - # the gate and invalid value are deleted from ld1 - self.assertEqual(ld0, UOp.load(glbl2.index(idx), dtype=dtypes.int)) - - def test_fold_gated_load_local(self): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - smem = UOp(Ops.DEFINE_LOCAL, dtypes.int.ptr(size=18, local=True), (), "temp") - lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 16)) - st = UOp(Ops.STORE, dtypes.void, (smem.index(lidx), UOp.load(glbl0.index(lidx), dtype=dtypes.int))) - barrier = UOp(Ops.BARRIER, dtypes.void, (st, )) - ld0 = UOp(Ops.LOAD, dtypes.int, (smem.index(lidx+1, UOp.const(dtypes.bool, False)), barrier)) - ld1 = UOp(Ops.LOAD, dtypes.int, (smem.index(lidx+2, UOp.const(dtypes.bool, True)), barrier)) - uops = to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0.index(lidx), ld1+ld0))]) - - ld0 = uops[-1].src[-1] - # the gate and invalid value are deleted from ld1 - self.assertEqual(ld0.src[0], smem.index(lidx+2)) - - def test_fold_gated_store(self): - glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - idx0 = UOp.const(dtypes.int, 0) - idx1 = UOp.const(dtypes.int, 0) - val = UOp.const(dtypes.int, 42) - st0 = UOp(Ops.STORE, dtypes.void, (glbl.index(idx0, UOp.const(dtypes.bool, False)), val)) - st1 = UOp(Ops.STORE, dtypes.void, (glbl.index(idx1, UOp.const(dtypes.bool, True)), val)) - uops = to_uops_list([st0, st1]) - # only the second store happens - self.assertEqual(len(uops), 5) - self.assertEqual(uops[-1], UOp.store(glbl.index(idx1), val)) - - @unittest.skip("this is a uop type error") - def test_asserts_bad_gate(self): - glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - idx = UOp.const(dtypes.int, 0) - bad_gate = UOp.const(dtypes.int, 1) - with self.assertRaises(AssertionError): to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0, idx, UOp.const(dtypes.int, 42), bad_gate))]) - - def test_switched_range_order(self): - glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - c2 = UOp.const(dtypes.int, 2) - cf = UOp.const(dtypes.float, 0.0) - r1 = UOp(Ops.RANGE, dtypes.int, (c2,), 0) - r2 = UOp(Ops.RANGE, dtypes.int, (c2,), 1) - alu = UOp(Ops.MUL, dtypes.int, (r2, r1)) - store = UOp(Ops.STORE, dtypes.void, (glbl.index(alu), cf)) - uops = to_uops_list([store]) - ranges = [x for x in uops if x.op is Ops.RANGE] - endranges = [x for x in uops if x.op is Ops.ENDRANGE] - # ranges are closed in the right order - self.assertEqual(endranges[-1].src[0], ranges[0]) - -@track_rewrites() -def expander_rewrite(sink): return graph_rewrite(sink, sym + expander) - -class TestExpander(unittest.TestCase): - def test_expand_add_broadcast(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) - sink = expander_rewrite(e1+3) - assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 4 - self.assertTupleEqual(sink.src[0].arg, (3,4,5,6)) - - def test_contract_simple(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) - con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((1,4),)) - sink = expander_rewrite(con) - self.assertEqual(sink.op, Ops.VCONST) - self.assertTupleEqual(sink.arg, (0,1,2,3)) - - def test_contract_axis_1(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,4),(2,4))) - con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((1,4),)) - sink = expander_rewrite(con) - assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 and sink.arg == ((2,4),) - assert sink.src[0].op is Ops.VCONST - self.assertTupleEqual(sink.src[0].arg[0:4], (0,4,8,12)) - self.assertTupleEqual(sink.src[0].arg[12:], (3,7,11,15)) - - def test_contract_axis_2(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,4),(2,4))) - con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((2,4),)) - sink = expander_rewrite(con) - assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 and sink.arg == ((1,4),) - assert sink.src[0].op is Ops.VCONST - self.assertTupleEqual(sink.src[0].arg[0:4], (0,1,2,3)) - self.assertTupleEqual(sink.src[0].arg[12:], (12,13,14,15)) - - def test_contract_axis_2_big(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,2),(2,2),(3,2),(4,2))) - con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) - sink = expander_rewrite(con) - assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (3, 2), (4, 2)) - self.assertTupleEqual(sink.src[0].arg[0:2], (0,4)) - self.assertTupleEqual(sink.src[0].arg[12:14], (10,14)) - - def test_contract_multi_axis(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,2),(2,2),(3,2),(4,2))) - sink = expander_rewrite(UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((3, 2), (2, 2)))) - assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (4, 2)) - self.assertTupleEqual(sink.src[0].arg[0:4], (0, 4, 2, 6)) - sink = expander_rewrite(UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((2, 2), (3, 2)))) - assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (4, 2)) - self.assertTupleEqual(sink.src[0].arg[0:4], (0, 2, 4, 6)) - - def test_contract_mid(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(8), tuple(x for x in range(8))),), ((1,2),(2,2),(3,2))) - con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) - sink = expander_rewrite(con) - assert sink.op is Ops.UNROLL and sink.arg == ((1,2),(3,2)) - assert sink.src[0].op is Ops.VCONST and len(sink.src[0].arg) == 8 - self.assertTupleEqual(sink.src[0].arg, (0,2,1,3,4,6,5,7)) - - def test_contract_no_expand(self): - e1 = UOp(Ops.DEFINE_VAR, dtypes.int) - con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) - sink = expander_rewrite(con) - assert sink.op is Ops.VECTORIZE and len(sink.src) == 2 - assert sink.src[0] == sink.src[1] - - def test_contract_half_expand(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) - con = UOp(Ops.CONTRACT, dtypes.int.vec(8), (e1,), ((1,4), (2,2))) - sink = expander_rewrite(con) - assert sink.op is Ops.VCONST and len(sink.arg) == 8 - assert sink.arg[0] == sink.arg[1] - assert sink.arg[0] != sink.arg[2] - assert sink.arg[6] == sink.arg[7] - - def test_expand_same_axis(self): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) - e2 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(4*x for x in range(4))),), ((1,4),)) - sink = expander_rewrite(e1+e2) - self.assertEqual(sink.op, Ops.UNROLL) - self.assertEqual(sink.src[0].op, Ops.VCONST) - self.assertTupleEqual(sink.src[0].arg, (0,5,10,15)) - - def test_expand_different_axis(self, flip=False): - e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(4*x for x in range(4))),), ((1,4),)) - e2 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((2,4),)) - sink = expander_rewrite((e2+e1) if flip else (e1+e2)) - assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 - assert sink.arg == ((1, 4), (2, 4)) - self.assertTupleEqual(sink.src[0].arg, (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)) - - def test_expand_different_axis_flip(self): self.test_expand_different_axis(True) - - @unittest.skip("no longer supported") - def test_reduce_known_axis(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) - sink = UOp(Ops.REDUCE, dtypes.int, (3*e1,e1), Ops.ADD) - sink = expander_rewrite(sink) - assert sink.op is Ops.CONST - self.assertEqual(sink.arg, 3*(0+1+2+3)) - - @unittest.skip("no longer supported") - def test_reduce_const(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) - sink = UOp(Ops.REDUCE, dtypes.int, (UOp.const(dtypes.int, 3), e1), Ops.ADD) - sink = expander_rewrite(sink) - assert sink.op is Ops.CONST - self.assertEqual(sink.arg, 3*4) - - @unittest.skip("no longer supported") - def test_double_expand(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((2,4),)) - e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((2,4),)) - e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((1,2),)) - sink = expander_rewrite(e) - assert sink.op is Ops.UNROLL and len(sink.src) == 8 - assert sink.arg == ((1, 2), (2, 4)) - self.assertListEqual([x.arg for x in sink.src], [0,1,2,3,4,5,6,7]) - - @unittest.skip("no longer supported") - def test_double_expand_reverse(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) - e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((1,4),)) - e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((2,2),)) - sink = expander_rewrite(e) - assert sink.op is Ops.UNROLL and len(sink.src) == 8 - assert sink.arg == ((1, 4), (2, 2)) - self.assertListEqual([x.arg for x in sink.src], [0, 4, 1, 5, 2, 6, 3, 7]) - - @unittest.skip("no longer supported") - def test_double_expand_middle(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,2),(3,2))) - e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((1,2),(3,2))) - e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((2,2),)) - sink = expander_rewrite(e) - assert sink.op is Ops.UNROLL and len(sink.src) == 8 - assert sink.arg == ((1, 2), (2, 2), (3, 2)) - self.assertListEqual([x.arg for x in sink.src], [0, 1, 4, 5, 2, 3, 6, 7]) - - # does this need to work? - @unittest.expectedFailure - @unittest.skip - def test_reduce_different_axis(self): - e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) - e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((2,4),)) - sink = UOp(Ops.REDUCE, dtypes.int, (e1,e2), Ops.ADD) - sink = expander_rewrite(sink) - print(sink) - -class TestIFUOps(unittest.TestCase): - def test_create_ifs(self): - gbuf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - sbuf = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(size=4, local=True), (), "smem") - valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 10))<5 - lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 4)) - gate = valid&(lidx.ne(2)) - idx = UOp.const(dtypes.int, 0) - st = UOp(Ops.STORE, dtypes.void, (sbuf.index(idx), UOp.const(dtypes.float, 42))) - barrier = UOp(Ops.BARRIER, dtypes.void, (st,)) - lbuf = UOp(Ops.LOAD, dtypes.float, (sbuf.index(UOp.const(dtypes.int, 0)), barrier)) - store = UOp(Ops.STORE, dtypes.void, (gbuf.index(UOp.const(dtypes.int, 0), gate), lbuf)) - sink = UOp(Ops.SINK, dtypes.void, (store,)) - sink = full_rewrite_to_sink(sink) - if_uops = [u for u in sink.toposort() if u.op is Ops.IF] - self.assertEqual(len(if_uops), 1) - self.assertEqual(if_uops[0].src[0], gate) - for st in sink.src: - self.assertEqual(len(st.src), 2) - - def test_expand_ifs_one_gate(self): - gbuf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - sbuf = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(size=16, local=True), (), "smem") - valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 4))<1 - lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 16)) - gate = valid&(lidx.ne(2)) - st = UOp(Ops.STORE, dtypes.void, (sbuf, lidx, UOp.const(dtypes.float, 42))) - barrier = UOp(Ops.BARRIER, dtypes.void, (st,)) - lbufs = [UOp(Ops.LOAD, dtypes.float, (sbuf.index(UOp.const(dtypes.int, i)), barrier)) for i in range(4)] - stores = [UOp(Ops.STORE, dtypes.void, (gbuf.index(UOp.const(dtypes.int, i), gate), lbufs[i])) for i in range(4)] - sink = UOp(Ops.SINK, dtypes.void, tuple(stores)) - sink = full_rewrite_to_sink(sink) - if_uops = [u for u in sink.toposort() if u.op is Ops.IF] - self.assertEqual(len(if_uops), 1) - self.assertEqual(if_uops[0].src[0], gate) - for st in sink.src: - self.assertEqual(len(st.src), 2) - - # this will be fixed with the merge gated stores bounty - @unittest.expectedFailure - def test_expand_ifs_dumb(self): - buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 10))<5 - lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 4)) - gate = valid&(lidx.ne(2)) - stores = [UOp(Ops.STORE, dtypes.void, (buf, UOp.const(dtypes.int, i), UOp.const(dtypes.float, i), gate)) for i in range(4)] - sink = UOp(Ops.SINK, dtypes.void, tuple(stores)) - sink = full_rewrite_to_sink(sink) - if_uops = [u for u in sink.toposort() if u.op is Ops.IF] - self.assertEqual(len(if_uops), 1) - self.assertEqual(if_uops[0].src[0], gate) - for st in sink.src: - self.assertEqual(len(st.src), 2) - -class TestUOpTags(unittest.TestCase): - def test_inc_by_one(self): - g = UOp.const(dtypes.int, 1) + UOp.const(dtypes.int, 1) - assert g.ssimplify() == 2 - pm_plus_1 = PatternMatcher([(UPat(Ops.CONST, name="x"), lambda x: x.replace(arg=x.arg+1, tag=1) if x.tag is None else None)]) - pm_strip_tags = PatternMatcher([(UPat(GroupOp.All, name="x"), lambda x: x.replace(tag=None) if x.tag is not None else None)]) - g = graph_rewrite(g, pm_plus_1) - assert g.ssimplify() == 4 - g = graph_rewrite(g, pm_plus_1) - assert g.ssimplify() == 4 - g = graph_rewrite(g, pm_strip_tags) - assert g.ssimplify() == 4 - g = graph_rewrite(g, pm_plus_1) - assert g.ssimplify() == 6 - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_uops.py b/tinygrad/test/test_uops.py deleted file mode 100644 index 779cac71..00000000 --- a/tinygrad/test/test_uops.py +++ /dev/null @@ -1,665 +0,0 @@ -from typing import Optional, Any -import unittest, math -import numpy as np -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View # noqa F401 -from tinygrad.tensor import Tensor, _to_np_dtype -from tinygrad.helpers import CI, DEBUG, getenv, Context, Timing -from tinygrad.dtype import dtypes, DType -from tinygrad.device import Buffer, Device -from tinygrad.uop.ops import Ops, UOp, UPat, KernelInfo, exec_alu # noqa F401 -from tinygrad.uop.spec import spec -from tinygrad.renderer import ProgramSpec -from tinygrad.engine.grouper import fix_kernel_ops -from tinygrad.engine.realize import CompiledRunner, get_kernel -from tinygrad.codegen import full_rewrite -from tinygrad.codegen.symbolic import sym -from tinygrad.device import is_dtype_supported -from tinygrad.codegen.kernel import Kernel, Opt, OptOps - -def to_uops_list(u:list[UOp], opts=None, skip_check=False) -> list[UOp]: return full_rewrite(UOp.sink(*u), opts) - -def _uops_to_prg(uops_list): - uops = full_rewrite(ast:=UOp.sink(*uops_list), opts=Device[Device.DEFAULT].renderer) - src = Device[Device.DEFAULT].renderer.render(uops) - has_local = Device[Device.DEFAULT].renderer.has_local - return CompiledRunner(ProgramSpec("test", src, Device.DEFAULT, ast, uops=uops, - global_size=[1,1,1] if has_local else None, local_size=[1,1,1] if has_local else None)) - -def uop(uops:list[UOp], uop:Ops, dtype:Optional[DType], src:tuple[UOp, ...], arg:Any=None) -> UOp: - uops.append(UOp(uop, dtype, tuple(src), arg)) - return uops[-1] - -def _test_single_value(vals, op, dts): - uops = [] - output_dtype = dtypes.bool if op in (Ops.CMPLT, Ops.CMPNE) else dts[-1] - buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) - buf_loads = [uop(uops, Ops.DEFINE_GLOBAL, dtype.ptr(), (), i+1) for i,dtype in enumerate(dts)] - loads = (uop(uops, Ops.LOAD, dtype, [buf_loads[i].index(uop(uops, Ops.CONST, dtypes.int32, (), 0))]) for i, dtype in enumerate(dts)) - alu = uop(uops, op, output_dtype, loads) - out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), alu)) - buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() - buf2 = [Buffer(Device.DEFAULT, 1, dtype).allocate().copyin(np.array([a], dtype=_to_np_dtype(dtype)).data) for a,dtype in zip(vals, dts)] - prg = _uops_to_prg([out]) - prg.exec([buf]+buf2) - ret = np.empty(1, _to_np_dtype(output_dtype)) - buf.copyout(ret.data) - return ret[0] - -def _test_single_value_const(vals, op, dts): - uops = [] - output_dtype = dtypes.bool if op in (Ops.CMPLT, Ops.CMPNE) else dts[-1] - buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) - loads = (uop(uops, Ops.CONST, dtype, [], a) for a,dtype in zip(vals, dts)) - alu = uop(uops, op, output_dtype, loads) - out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), alu)) - buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() - prg = _uops_to_prg([out]) - prg.exec([buf]) - ret = np.empty(1, _to_np_dtype(output_dtype)) - buf.copyout(ret.data) - return ret[0] - -def _test_uops_result(output_dtype, uops, res): - # uops = [] - buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) - # res = output_fn(uops) - out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), res)) - buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() - prg = _uops_to_prg([out]) - prg.exec([buf]) - ret = np.empty(1, _to_np_dtype(output_dtype)) - buf.copyout(ret.data) - return ret[0] - -class TestUOps(unittest.TestCase): - def _equal(self, v1, v2): - assert isinstance(v2, (float, int, bool)) - if isinstance(v2, float): - np.testing.assert_allclose(v1, v2, rtol=2e-7) - else: - np.testing.assert_equal(v1, v2) - - def _test_uop_fxn(self, op, fxn, dts=(dtypes.float32, )): - for f in [_test_single_value, _test_single_value_const]: - for a in [-2.0, 0.0, 1.0]: - a = dtypes.as_const(a, dts[0]) - self._equal(f([a], op, dts), fxn(a)) - - def _test_bop_fxn(self, op, fxn, dts=(dtypes.float32, )*2, no_b_zero=False, no_b_neg=False): - for f in [_test_single_value, _test_single_value_const]: - for a in [-2.0, 0.0, 1.0]: - for b in [-3.0, 1.0] + ([] if no_b_zero else [0.0]): - a = dtypes.as_const(a, dts[0]) - b = dtypes.as_const(abs(b) if no_b_neg else b, dts[1]) - self._equal(f([a,b], op, dts), fxn(a,b)) - - def _test_top_fxn(self, op, fxn, dts=(dtypes.float32, )*3): - for f in [_test_single_value, _test_single_value_const]: - for a in [-2.0, 0, 1]: - for b in [-3.0, 3.0]: - for c in [-4.0, 4.0]: - a = dtypes.as_const(a, dts[0]) - b = dtypes.as_const(b, dts[1]) - c = dtypes.as_const(c, dts[2]) - self._equal(f([a,b,c], op, dts), fxn(a,b,c)) - -class TestFloatUOps(TestUOps): - @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') - def test_exp2(self): self._test_uop_fxn(Ops.EXP2, lambda a: np.exp2(a)) - @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') - def test_log2(self): self._test_uop_fxn(Ops.LOG2, lambda a: math.log2(a) if a > 0 else float('-inf' if a==0 else 'nan')) - @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') - def test_sin(self): self._test_uop_fxn(Ops.SIN, lambda a: math.sin(a)) - def test_recip(self): self._test_uop_fxn(Ops.RECIP, lambda a: 1/a if a != 0 else float('inf')) - def test_sqrt(self): self._test_uop_fxn(Ops.SQRT, lambda a: math.sqrt(a) if a >= 0 else float('nan')) - - def test_add(self): self._test_bop_fxn(Ops.ADD, lambda a,b: a+b) - def test_mul(self): self._test_bop_fxn(Ops.MUL, lambda a,b: a*b) - def test_max(self): self._test_bop_fxn(Ops.MAX, lambda a,b: max(a,b)) - def test_cmplt(self): self._test_bop_fxn(Ops.CMPLT, lambda a,b: a>int(b), (dtypes.int32, dtypes.int32), no_b_neg=True) - @unittest.skipUnless(getenv("PTX"), "only ptx uses bitshifts") - def test_shl_int32(self): self._test_bop_fxn(Ops.SHL, lambda a,b: int(a)<= 4: print(Device[Device.DEFAULT].renderer.render(uops)) - if_uop = next(u for u in uops if u.op is Ops.IF) - endif = next(u for u in uops if u.op is Ops.ENDIF) - assert endif.src[0] is if_uop - gated_uops = tuple(uops[uops.index(if_uop)+1:uops.index(endif)]) - self.assertEqual(len(gated_uops), 1) - self.assertIs(gated_uops[-1].op, Ops.STORE) - - def test_gate_some_stores(self): - gmem0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - gmem1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) - gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) - idx = gidx0 * UOp.const(dtypes.int, 2) - idx0 = UOp(Ops.INDEX, dtypes.float.ptr(), (gmem0, idx, gidx0= 4: print(Device[Device.DEFAULT].renderer.render(uops)) - if_uop = next(u for u in uops if u.op is Ops.IF) - endif = next(u for u in uops if u.op is Ops.ENDIF) - assert endif.src[0] is if_uop - gated_uops = tuple(uops[uops.index(if_uop)+1:uops.index(endif)]) - self.assertEqual(len(gated_uops), 1) - self.assertIs(gated_uops[-1].op, Ops.STORE) - - # scaled down version of TestLinearizerDumb.test_unmerged_ifs - def test_merge_ifs_alt(self): - gmem0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - gmem1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) - gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) - idx = gidx0*UOp.const(dtypes.int, 2) - gate = gidx0= 4: print(Device[Device.DEFAULT].renderer.render(uops)) - ifs = [u for u in uops if u.op is Ops.IF] - endifs = [u for u in uops if u.op is Ops.ENDIF] - self.assertEqual(len(ifs), 1) - self.assertEqual(len(endifs), 1) - gated_uops = tuple(uops[uops.index(ifs[0])+1:uops.index(endifs[0])]) - self.assertEqual(len(gated_uops), 2) - for x in gated_uops: self.assertIs(x.op, Ops.STORE) - -class TestLocalAccess(unittest.TestCase): - # NOTE: this is failing on METAL CI, no idea why. Works locally. - @unittest.skipIf(Device.DEFAULT == "METAL" and CI, "failing only in CI") - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared memory") - def test_local_basic(self): - uops = [] - smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.float32.ptr(size=16, local=True), (), 'smem') - st = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), uop(uops, Ops.CONST, dtypes.float32, (), 42.0))) - barr = uop(uops, Ops.BARRIER, dtypes.void, (st,)) - sres = uop(uops, Ops.LOAD, dtypes.float32, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), barr)) - self.assertEqual(_test_uops_result(dtypes.float32, uops, sres), 42) - - # NOTE: webgpu specific, since only webgpu performs bitpacking - @unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Test local access with packed data type") - def test_local_packed(self): - uops = [] - smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.uint8.ptr(size=16, local=True), (), 'smem') - st = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), uop(uops, Ops.CONST, dtypes.uint8, (), 42))) - barr = uop(uops, Ops.BARRIER, dtypes.void, (st,)) - sres = uop(uops, Ops.LOAD, dtypes.uint8, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), barr)) - self.assertEqual(_test_uops_result(dtypes.uint8, uops, sres), 42) - - # NOTE: webgpu specific, since only webgpu performs bitpacking - @unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Test local memory size for packed data types") - def test_packed_smem_size(self): - _dtypes = [dtypes.char, dtypes.uchar, dtypes.short, dtypes.ushort, dtypes.half] - size = 16 - for dtype in _dtypes: - temp = UOp(Ops.DEFINE_LOCAL, dtype.ptr(size=size, local=True), (), 'smem') - uops = to_uops_list([temp], opts=Device[Device.DEFAULT].renderer) - out = Device[Device.DEFAULT].renderer.render(uops) - # half is supported in wgsl, so it doesn't have to be packed - corrected_size = size//(4//dtype.itemsize) if dtype != dtypes.half else size - self.assertIn(f"temp0: array<{Device[Device.DEFAULT].renderer.buf_map(dtype)},{corrected_size}>;", out) - - @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared memory") - @unittest.skip("tinygrad doesn't support this behavior") - def test_local_indirect(self): - uops = [] - smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.int32.ptr(size=16, local=True), (), 'smem') - st1 = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 1)), uop(uops, Ops.CONST, dtypes.int32, (), 2))) - st2 = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 2)), uop(uops, Ops.CONST, dtypes.int32, (), 42))) - barr = uop(uops, Ops.BARRIER, dtypes.void, (st1,st2)) - ofs = uop(uops, Ops.LOAD, dtypes.int32, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 1)), barr)) - sres = uop(uops, Ops.LOAD, dtypes.int32, (smem.index(ofs),)) - self.assertEqual(_test_uops_result(dtypes.int32, uops, sres), 42) - -@unittest.skipUnless(getenv("PTX"), "This only tests assembly backends") -class TestAssembly(unittest.TestCase): - def test_bitshift_left(self): - g1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 0) - c1 = UOp(Ops.CONST, dtypes.int, (), 2) - c2 = UOp(Ops.CONST, dtypes.int, (), 3) - l1 = UOp(Ops.LOAD, dtypes.int, (g1.index(c1),)) - a1 = UOp(Ops.MUL, dtypes.int, (l1, c1)) - a2 = UOp(Ops.MUL, dtypes.int, (l1, c2)) - uops = to_uops_list([a1,a2], opts=Device[Device.DEFAULT].renderer) - Device[Device.DEFAULT].renderer.render(uops) - ops = [x.op for x in uops] - self.assertIn(Ops.SHL, ops) - self.assertIn(Ops.MUL, ops) - - def test_division_power_of_two(self): - g = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(), (), 0) - c = UOp(Ops.CONST, dtypes.uint, (), 2) - l = UOp(Ops.LOAD, dtypes.uint, (g.index(c),)) - a = UOp(Ops.IDIV, dtypes.uint, (l, c)) - uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) - Device[Device.DEFAULT].renderer.render(uops) - ops = [x.op for x in uops] - self.assertIn(Ops.SHR, ops) - self.assertNotIn(Ops.IDIV, ops) - - def test_fast_idiv_and_mod(self): - g = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(), (), 0) - c = UOp(Ops.CONST, dtypes.uint, (), 3) - l = UOp(Ops.LOAD, dtypes.uint, (g.index(c),)) - a = UOp(Ops.IDIV, dtypes.uint, (l, c)) - uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) - Device[Device.DEFAULT].renderer.render(uops) - ops = [x.op for x in uops] - self.assertIn(Ops.SHR, ops) - self.assertNotIn(Ops.IDIV, ops) - - b = UOp(Ops.MOD, dtypes.uint, (l, c)) - uops = to_uops_list([b], opts=Device[Device.DEFAULT].renderer) - Device[Device.DEFAULT].renderer.render(uops) - ops = [x.op for x in uops] - self.assertIn(Ops.SHR, ops) - self.assertNotIn(Ops.MOD, ops) - - @unittest.expectedFailure - def test_fast_idiv_overflow(self): - # This will be possible with a slightly different method for fast_idiv - g = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(), (), 0) - c = UOp(Ops.CONST, dtypes.uint, (), 7) - l = UOp(Ops.LOAD, dtypes.uint, (g.index(c),)) - a = UOp(Ops.IDIV, dtypes.uint, (l, c)) - uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) - Device[Device.DEFAULT].renderer.render(uops) - ops = [x.op for x in uops] - self.assertIn(Ops.SHR, ops) - self.assertNotIn(Ops.IDIV, ops) - - def test_mulacc_unrolled(self): - # test that acc = acc + a0*b0 + a1*b1 + a2*b2 + a3*b3 - # is not acc = acc + (a0*b0 + a1*b1 + a2*b2 + a3*b3) - a = Tensor.empty(1024) - b = Tensor.empty(1024) - c = (a*b).sum() - k = Kernel(c.schedule()[-1].ast) - k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) - uops = k.linearize().uops - self.assertEqual(len([x.op for x in uops if x.op is Ops.MULACC]), 4) - -class TestUOpMethod(unittest.TestCase): - @unittest.skip("uops lt no longer ordered") - def test_compare_alu_same_src_different_arg(self): - a = UOp(Ops.CONST, dtypes.float, (), 2.0) - b = UOp(Ops.CONST, dtypes.float, (), 3.0) - - add = UOp(Ops.ADD, dtypes.float, (a, b)) - mul = UOp(Ops.MUL, dtypes.float, (a, b)) - assert (add < mul) or (mul < add), "add and mul with same src should have an order" - - def test_uop_variables(self): - a = UOp.variable("a", 1, 10) - uop_var = Tensor(a.bind(1)) - st_var = Tensor.empty((2, 1)).reshape((2, a.bind(1))) - _, var_vals = (uop_var+st_var).schedule_with_vars() - self.assertEqual(len(var_vals), 1) - self.assertEqual(list(var_vals)[0], a) - - def test_const_factor(self): - gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 8)) - self.assertEqual(UOp(Ops.CONST, dtypes.int, (), 17).const_factor(), 17) - self.assertEqual(gidx0.const_factor(), 1) - self.assertEqual((gidx0*3).const_factor(), 3) - self.assertEqual((gidx0*3+6).const_factor(), 3) - self.assertEqual((gidx0*3+1).const_factor(), 1) - - def test_replace(self): - x = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) - self.assertIs(x.replace(arg=None).arg, None) - with self.assertRaises(AssertionError): x.replace(field="a") - - def test_device(self): - x = UOp(Ops.VIEW, dtypes.int, (UOp.new_buffer(Device.DEFAULT, 1, dtypes.int), UOp.const(dtypes.int, 1)), ShapeTracker.from_shape(())) - self.assertEqual(x.device, Device.DEFAULT) - # NOTE: CONST doesn't have device - buffer, const = x.src - self.assertEqual(buffer.device, Device.DEFAULT) - self.assertEqual(const._device, None) - with self.assertRaises(AssertionError): const.device - -class TestUOpStr(unittest.TestCase): - def test_uop_str(self): - a = UOp(Ops.CONST, dtypes.float, (), 2.0) + UOp(Ops.CONST, dtypes.float, (), 3.0) - for _ in range(20): a = a + a - assert len(str(a)) < 10_000, "exponential string growth" - assert str(eval(str(a))) == str(a) - - t = Tensor.arange(10) - t = t + t * Tensor.rand(10) - # nice big complicated uop - with Context(NOOPT=1): - sink = UOp(Ops.SINK, dtypes.void, (get_kernel(Device[Device.DEFAULT].renderer, t.schedule()[-1].ast).linearize().uops[-1],)) - self.assertEqual(sink, eval(str(sink))) - - def test_vectorized_str(self): - vec = UOp(Ops.VECTORIZE, dtypes.int.vec(4), tuple(UOp.const(dtypes.int, x) for x in range(4))) - assert str(eval(str(vec))) == str(vec) - - def test_device_arg(self): - device = UOp(Ops.DEVICE, arg="GPU") - assert str(eval(str(device))) == str(device) - - def test_reduceop_arg(self): - sum_uop = Tensor.empty(32, 32).sum().uop - assert str(eval(str(sum_uop))) == str(sum_uop) - -@unittest.skip("uop no longer has order like this") -class TestIndexingOrdering(unittest.TestCase): - # NOTE: these tests skip type_verify since they add dtype to STORE - @unittest.expectedFailure - def test_simple_order(self): - buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - st0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) - st1 = UOp(Ops.STORE, dtypes.float, (buf, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) - uops = to_uops_list([st1, st0], skip_check=True) - stores = [st for st in uops if st.op is Ops.STORE] - assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" - - @unittest.expectedFailure - def test_ordering_multi_output(self): - buf0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - buf1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) - st0_0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf0, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) - st1_0 = UOp(Ops.STORE, dtypes.float, (buf0, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) - st0_1 = UOp(Ops.STORE, dtypes.float.vec(4), (buf1, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) - st1_1 = UOp(Ops.STORE, dtypes.float, (buf1, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) - uops = to_uops_list([st0_0, st1_0, st0_1, st1_1], skip_check=True) - stores = [st for st in uops if st.op is Ops.STORE] - print("\n".join(map(str, stores))) - # buf0 stores come first - self.assertEqual(stores[0].src[0].arg, stores[1].src[0].arg) - # buf1 stores come next - self.assertEqual(stores[2].src[0].arg, stores[3].src[0].arg) - # both stores are aligned based on idx - assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" - assert stores[2].src[1] < stores[3].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" - - def test_simple_order_with_special(self): - buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) - st0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf, gidx0+UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) - st1 = UOp(Ops.STORE, dtypes.float, (buf, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) - uops = full_rewrite(UOp.sink(st1, st0)) - stores = [st for st in uops if st.op is Ops.STORE] - assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" - -class TestUPatHelpers(unittest.TestCase): - def test_location(self): - self.assertEqual(sym.patterns[-1][0].location[0].replace("\\", "/").split("/")[-1], "symbolic.py") - self.assertEqual(fix_kernel_ops.patterns[0][0].location[0].replace("\\", "/").split("/")[-1], "grouper.py") - self.assertEqual(spec.patterns[0][0].location[0].replace("\\", "/").split("/")[-1], "spec.py") - test_upat = UPat(Ops.CONST, dtypes.bool) - self.assertEqual(test_upat.location[0].split("/")[-1], __file__.replace("\\", "/").split("/")[-1]) - test_upat_named = test_upat.named("test_name") - self.assertEqual(test_upat.location[0], test_upat_named.location[0]) - self.assertNotEqual(test_upat.location[1], test_upat_named.location[1]) - -class TestUopsObject(unittest.TestCase): - # LOL, running this test breaks all instances of "4" - """ - @unittest.expectedFailure - def test_immutable(self): - const_4 = UOp.const(dtypes.int, 4) - with self.assertRaises(Exception): - const_4.arg = 5 - """ - - def test_timing(self): - with Timing("create 10k uops:"): ret = [UOp(Ops.CONST, dtypes.int, arg=10000000+i) for i in range(10000)] - assert len(ret) == 10000 - - -class TestShapeSpec(unittest.TestCase): - # ** CONST is CONST(VIEW(DEVICE)) -> RESHPAE -> EXPAND - - def test_expanded_const(self): - a = Tensor(1).uop - self.assertEqual(a.st, ShapeTracker.from_shape(())) - a = Tensor.ones((4, 4)).uop - self.assertEqual(a.st, ShapeTracker.from_shape(()).reshape((1,1)).expand((4,4))) - - def test_padded_const(self): - a = Tensor.ones((1, 1)).pad(((1, 1), (1, 1))) - ast = a.contiguous().schedule()[0].ast - valid_pattern = UPat(Ops.WHERE, src=(UPat(Ops.VALID), UPat.cvar(), UPat.cvar())) - valid_ternary = [x for x in ast.toposort() if valid_pattern.match(x, {})][0] - # the WHERE outputs a contiguous (3, 3) - self.assertEqual(valid_ternary.st, ShapeTracker.from_shape((3, 3))) - valid, x, y = valid_ternary.src - # very notably, only the first source is padded - self.assertIsNotNone(valid.st.views[-1].mask) - assert x.st.views[-1].mask is y.st.views[-1].mask is None - assert all(s.shape == (3, 3) for s in valid_ternary.src) - - # NOTE: CONST ShapeTracker comes from its source - def test_scalar_const(self): - a = Tensor(0).uop - self.assertEqual(a.st, ShapeTracker.from_shape(())) - - def test_scalar_var(self): - vv = UOp.variable("a", 1, 4).bind(2) - t = Tensor(vv).uop - self.assertEqual(t.st, ShapeTracker.from_shape(())) - - # ** ASSIGN is ASSIGN(VIEW(BUFFER), new_val) - - def test_assign_flat(self): - buffer = Tensor.arange(4).realize() - a = buffer.assign(Tensor.zeros((4,), dtype=dtypes.int)) - assign_pattern = UPat(Ops.ASSIGN, src=(UPat(Ops.BUFFER), UPat())) - assert assign_pattern.match(a.uop, {}) - a.realize() - self.assertEqual(buffer.tolist(), [0, 0, 0, 0]) - - def test_assign_permuted(self): - buffer = Tensor.arange(4).reshape(2, 1, 2).contiguous().realize() - a = buffer.permute((1, 2, 0)).assign(Tensor.arange(4).reshape(1, 2, 2).contiguous()) - a.realize() - self.assertEqual(buffer.tolist(), [[[0, 2]], [[1, 3]]]) - - def test_assign_reshaped(self): - buffer = Tensor.ones((4,)).contiguous().realize() - a = buffer.reshape((2, 2)).assign(Tensor.zeros((2, 2))) - assign_pattern = UPat(Ops.ASSIGN, src=(UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER))), UPat())) - assert assign_pattern.match(a.uop, {}) - a.realize() - self.assertEqual(buffer.tolist(), [0, 0, 0, 0]) - - # setitem is a partial assign - def test_setitem(self): - a = Tensor.ones((4,)).contiguous().realize() - assign = a.shrink(((1, 2),)).assign(Tensor.zeros((1,))) - # the ASSIGN UOp has size=1 - self.assertEqual(assign.uop.size, 1) - # the ASSIGN views the buffer with a shrunk st - self.assertEqual(assign.uop.src[0].st, ShapeTracker.from_shape((4,)).shrink(((1, 2),))) - # the underlying BUFFER has a size=4 - self.assertEqual(assign.uop.buf_uop.size, 4) - # NOTE: output shape is different from the BUFFER shape - self.assertNotEqual(assign.uop.shape, a.uop.shape) - assign.realize() - self.assertEqual(a.tolist(), [1, 0, 1, 1]) - - def test_buffer_st(self): - a = UOp.new_buffer(Device.DEFAULT, 10, dtypes.float) - self.assertEqual(a.st, ShapeTracker.from_shape((10,))) - - def test_ops_st(self): - # view / mop - a = Tensor.empty(4, 2, 1).permute((1, 2, 0)).uop - self.assertEqual(a.st, ShapeTracker.from_shape((4, 2, 1)).permute((1, 2, 0))) - # alu / reduce - alu = a*2 - self.assertEqual(alu.st, ShapeTracker.from_shape((2, 1, 4))) - r = Tensor.empty(4, 4).sum(axis=1) - self.assertEqual(r.uop.st, ShapeTracker.from_shape((4,))) - - def test_st_wmma_none(self): - A = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('a', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 1))) - B = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('b', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 2))) - C = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('c', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 3))) - wmma = UOp(Ops.WMMA, dtypes.float.vec(16), (A, B, C)) - assert wmma.st is None - -class TestUOpChildren(unittest.TestCase): - def test_children_exist(self): - a = UOp.variable("weird_name_234", 0, 10) - b = a*a - self.assertEqual(len(a.children), 1) - self.assertIs(list(a.children)[0](), b) - - def test_children_cleaned_up(self): - a = UOp.variable("weird_name_235", 0, 10) - b = a*a - self.assertEqual(len(a.children), 1) - del b - self.assertEqual(len(a.children), 0) - - def test_children_cleaned_up_two(self): - a = UOp.variable("weird_name_236", 0, 10) - b = a*a - c = a*2 - self.assertEqual(len(a.children), 2) - del b - self.assertEqual(len(a.children), 1) - del c - self.assertEqual(len(a.children), 0) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_uops_stats.py b/tinygrad/test/test_uops_stats.py deleted file mode 100644 index fdaf21c4..00000000 --- a/tinygrad/test/test_uops_stats.py +++ /dev/null @@ -1,249 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad.helpers import getenv, GlobalCounters -from tinygrad.engine.realize import lower_schedule_item, ProgramSpec -from tinygrad.renderer import Estimates -from tinygrad.codegen import full_rewrite -from tinygrad.uop.ops import Ops, UOp -from tinygrad.dtype import dtypes -from tinygrad.codegen.kernel import Kernel, Opt, OptOps, KernelOptError -from tinygrad.device import Device - -def flops_mem(uops, ignore_indexing=False): - est = Estimates.from_uops(uops, ignore_indexing) - return est.ops, est.lds - -# **************** new FlopCounter **************** - -def get_stats(x:Tensor): - si = x.schedule()[-1] - ei = lower_schedule_item(si) - return ei.prg.estimates.ops, ei.prg.estimates.mem - -class TestMemoryCount(unittest.TestCase): - def test_add(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - b = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - _, mem = get_stats(a+b) - self.assertEqual(mem, 1024*1024*3) # 2 reads + 1 write - - def test_add_const(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - _, mem = get_stats(a+3) - self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write - - @unittest.skip("depends on subbuffer working") - def test_add_slice(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8)[:512] - _, mem = get_stats(a+3) - self.assertEqual(mem, 512*1024*2) # 1 read + 1 write - - def test_expanded(self): - a = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) - b = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - _, mem = get_stats(a+b) - self.assertEqual(mem, 1024*1024*2 + 1024) # 1 full read + 1 lil read + 1 write - - def test_both_expanded(self): - # TODO: this probably should be a full write - a = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) - b = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) - _, mem = get_stats(a+b) - self.assertEqual(mem, 1024*1024 + 2*1024) # 2 lil reads + 1 write - - def test_self_add(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - _, mem = get_stats(a+a) - self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write - - def test_self_add_transposed(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) - _, mem = get_stats(a+a.T) - self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write - - def test_self_add_assign(self): - a = Tensor.empty(1024, 1024, dtype=dtypes.uint8).realize() - _, mem = get_stats(a.assign(a+a)) - self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write - - @unittest.skipIf(Device.DEFAULT == "CPU", "test copy to CPU from other device") - def test_copyout(self): - a = Tensor.empty(32, dtype=dtypes.uint8).to("CPU") - _, mem = get_stats(a) - self.assertEqual(mem, 32*1) - a = Tensor.empty(32, dtype=dtypes.uint32).to("CPU") - _, mem = get_stats(a) - self.assertEqual(mem, 32*4) - -# NOTE: this still isn't testing unroll using the acc -@unittest.skipUnless(getenv("PYTHON"), "only run test on emulated tensor cores") -class TestUOpsStatsMatmulHalf(unittest.TestCase): - def test_simple_matmul_half(self, N=16): - GlobalCounters.reset() - a, b = Tensor.empty(N, N, dtype=dtypes.half), Tensor.empty(N, N, dtype=dtypes.half) - c = a.matmul(b) - c.realize() - expected_ops = N ** 3 * 2 - self.assertEqual(expected_ops, GlobalCounters.global_ops) - - def test_bigger_matmul_half(self): self.test_simple_matmul_half(64) - - def test_batched_matmul_half(self, N=16): - GlobalCounters.reset() - a, b = Tensor.empty(4, N, N, dtype=dtypes.half), Tensor.empty(1, N, N, dtype=dtypes.half) - c = a.matmul(b) - c.realize() - expected_ops = 4 * N ** 3 * 2 - self.assertEqual(expected_ops, GlobalCounters.global_ops) - -class TestUOpsStats(unittest.TestCase): - @unittest.skipIf(getenv("PTX"), "wrong in PTX") - def test_simple_add(self): - a = Tensor.empty(100,100) - b = Tensor.empty(100,100) - c = a+b - ops, mem = get_stats(c) - expected_ops = c.numel() - expected_mem = a.nbytes() + b.nbytes() + c.nbytes() - self.assertEqual(mem, expected_mem) - # NOTE; ops also include indexing ops - assert expected_ops <= ops and ops <= expected_ops * 2 - - @unittest.skipIf(getenv("PTX"), "wrong in PTX") - def test_simple_add_sq(self): - a = Tensor.empty(100,100) - b = Tensor.empty(100,100) - c = (a+b)*(a+b) - ops, mem = get_stats(c) - expected_ops = c.numel()*2 - expected_mem = a.nbytes() + b.nbytes() + c.nbytes() - self.assertEqual(mem, expected_mem) - # NOTE; ops also include indexing ops - assert expected_ops <= ops and ops <= expected_ops * 2 - - def test_simple_matmul(self, M=1024, N=1024, K=1024): - a = Tensor.empty(M,N) - b = Tensor.empty(N,K) - c = a@b - ops, mem = get_stats(c) - expected_ops = c.numel() * N * 2 - required_mem = a.nbytes() + b.nbytes() + c.nbytes() - assert expected_ops <= ops and ops <= expected_ops * 1.2 - # NOTE: it's hard to assert on the memory here, all depends on caching - assert required_mem <= mem - - def test_simple_matmul_8192(self): self.test_simple_matmul(8192, 8192, 8192) - - #MULACC should have the same stats as MUL + ADD - def test_mulacc(self): - globl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), tuple()) - o1 = UOp(Ops.CONST, dtypes.int, tuple(), 1) - o2 = UOp(Ops.CONST, dtypes.int, tuple(), 2) - u1 = UOp(Ops.LOAD, dtypes.int, (globl.index(o1),)) - u2 = UOp(Ops.LOAD, dtypes.int, (globl.index(o2),)) - u3 = UOp(Ops.CONST, dtypes.int, tuple(), 3) - u4 = UOp(Ops.MUL, dtypes.int, (u1,u2)) - u5 = UOp(Ops.ADD, dtypes.int, (u4,u3)) - uops = full_rewrite(u5.sink()) - - globl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), tuple()) - o1 = UOp(Ops.CONST, dtypes.int, tuple(), 1) - o2 = UOp(Ops.CONST, dtypes.int, tuple(), 2) - u1 = UOp(Ops.LOAD, dtypes.int, (globl.index(o1),)) - u2 = UOp(Ops.LOAD, dtypes.int, (globl.index(o2),)) - u3 = UOp(Ops.CONST, dtypes.int, tuple(), 3) - u4 = UOp(Ops.MULACC, dtypes.int, (u1,u2,u3)) - uops_fma = full_rewrite(u4.sink()) - - self.assertEqual(flops_mem(uops), flops_mem(uops_fma)) - -N = 64 -@unittest.skipIf(getenv("PTX"), "wrong in PTX") # maybe? -class TestStatsOptimized(unittest.TestCase): - @classmethod - def setUpClass(cls): - cls.ast_gemm = (Tensor.empty(N, N) @ Tensor.empty(N, N)).schedule()[-1].ast - cls.ast_reduce = (Tensor.empty(N*N).sum()).schedule()[-1].ast - - def check_gemm(self, p:ProgramSpec, extra_flops=0): - #p.uops.print() - #print(p.src) - print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) - self.assertEqual(p.estimates.ops, 2*N*N*N + extra_flops) # N**3 mulaccs - self.assertEqual(p.estimates.mem, 3*N*N*4) # 3 NxN mats with floats - - def test_gemm(self): - p = Kernel(self.ast_gemm).to_program() - self.check_gemm(p) - self.assertEqual(p.estimates.lds, 2*N*N*N*4 + 4*N*N) - - def test_gemm_tc_unroll(self): - k = Kernel(self.ast_gemm) - if not k.apply_tensor_cores(): self.skipTest("no tensor cores") - k.apply_opt(Opt(OptOps.UNROLL, 0, 2)) - p = k.to_program() - print(p.src) - self.check_gemm(p) - - # this is a good lesson about why UPCASTing is a good idea - - def test_gemm_one_upcasted(self): - k = Kernel(self.ast_gemm) - k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - p = k.to_program() - self.check_gemm(p) - self.assertEqual(p.estimates.lds, N*N*N*4 + N*N*N*4//4 + 4*N*N) - - def test_gemm_upcasted(self): - k = Kernel(self.ast_gemm) - k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) - k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) - p = k.to_program() - self.check_gemm(p) - self.assertEqual(p.estimates.lds, 2*N*N*N*4//4 + 4*N*N) - - def test_gemm_upcasted_locals(self): - k = Kernel(self.ast_gemm) - k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) - try: - k.apply_opt(Opt(OptOps.LOCAL, 0, 5)) - k.apply_opt(Opt(OptOps.LOCAL, 1, 5)) - except KernelOptError: - raise unittest.SkipTest("no locals") - p = k.to_program() - self.check_gemm(p) - self.assertEqual(p.estimates.lds, 2*N*N*N*4//4 + 4*N*N) - - def test_gemm_group(self): - k = Kernel(self.ast_gemm) - try: - k.apply_opt(Opt(OptOps.GROUP, 0, 4)) - except KernelOptError: - raise unittest.SkipTest("no locals") - SZ = N*N*4 - p = k.to_program() - # NOTE: these are sort of wrong. they aren't honoring the IF statement - self.check_gemm(p, extra_flops=SZ*4) - self.assertEqual(p.estimates.lds, 2*N*N*N*4 + SZ*4 + (SZ*4 + 4*N*N)*4) - - def test_reduce(self): - k = Kernel(self.ast_reduce) - p = k.to_program() - print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) - self.assertEqual(p.estimates.ops, N*N) - self.assertEqual(p.estimates.mem, N*N*4 + 4) - - def test_reduce_group(self): - k = Kernel(self.ast_reduce) - try: - k.apply_opt(Opt(OptOps.GROUP, 0, 50)) - except KernelOptError: - raise unittest.SkipTest("no locals") - p = k.to_program() - # NOTE: these are wrong, they don't respect the if statement - print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_winograd.py b/tinygrad/test/test_winograd.py deleted file mode 100644 index e4ef3caa..00000000 --- a/tinygrad/test/test_winograd.py +++ /dev/null @@ -1,97 +0,0 @@ -import unittest -import numpy as np -from tinygrad import Tensor, GlobalCounters, dtypes, Context, nn -from tinygrad.uop.ops import Ops -from tinygrad.helpers import Timing, CI, Profiling, WINO, DEBUG, getenv -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.heuristic import hand_coded_optimizations - -class TestWinogradClose(unittest.TestCase): - def test_close(self): - inp = Tensor.rand(1, 16, 16, 16) - conv = nn.Conv2d(16, 16, 3) - conv(inp).realize() # warmup - GlobalCounters.reset() - print("non winograd") - with Context(WINO=0): - cmp = conv(inp).realize() # warmup - GlobalCounters.reset() - print("winograd") - with Context(WINO=1): - test = conv(inp).realize() - np.testing.assert_allclose(cmp.numpy(), test.numpy(), atol=1e-5) - -class TestWinograd(unittest.TestCase): - def setUp(self): - self.old = WINO.value - WINO.value = 1 - def tearDown(self): - WINO.value = self.old - - def test_speed(self): - x = Tensor.empty(1,4,9,9) - w = Tensor.empty(4,4,3,3) - - with Timing("running conv: "): - out = Tensor.conv2d(x, w) - - with Timing("scheduling: "): - sched = out.schedule() - - for i,s in enumerate(sched): - if s.ast.op is not Ops.SINK: continue - ops = s.ast.toposort() - with Timing(f"linearize {i} with {len(ops):4d} ops: "): - l = Kernel(s.ast) - l.apply_opts(hand_coded_optimizations(l)) - l.linearize() - assert len(l.sts) <= 256 # just the current value to prevent regression - if DEBUG >= 2: print(f"{len(l.sts):4d} shapetrackers with max {max(len(x.views) for x in l.sts)} views") - for st in l.sts: - assert len(st.views) <= 2, "too many views in winograd" - if DEBUG >= 3: - print(f"{len(st.views):3d} views") - for v in st.views: print(v) - - def test_profile(self): - x,w = Tensor.rand(1,4,9,9).realize(), Tensor.rand(4,4,3,3).realize() - with Profiling(enabled=not CI, sort='time'): - out = Tensor.conv2d(x,w).realize() - out.numpy() - - def test_four_kernels(self): - x,w = Tensor.rand(1,4,9,9).realize(), Tensor.rand(4,4,3,3).realize() - GlobalCounters.reset() - out = Tensor.conv2d(x,w).realize() - assert GlobalCounters.kernel_count == 4 - out.numpy() - - @unittest.skipIf(getenv("PTX"), "winograd uses too much in PTX") - def test_counters(self): - IC, OC, X, Y = 4,4,9,9 - #OC, IC, X, Y = 512, 256, 8, 8 - x,w = Tensor.rand(1,IC,Y,X).realize(), Tensor.rand(OC,IC,3,3).realize() - GlobalCounters.reset() - Tensor.conv2d(x,w).realize() - ops_wino, mem_wino = GlobalCounters.global_ops, GlobalCounters.global_mem - WINO.value = 0 - GlobalCounters.reset() - Tensor.conv2d(x,w).realize() - ops_normal, mem_normal = GlobalCounters.global_ops, GlobalCounters.global_mem - - ops_ratio, mem_ratio = ops_wino/ops_normal, mem_wino/mem_normal - print(f"ops: normal {ops_normal:9d} wino {ops_wino:9d} ratio {ops_ratio:.2f}") - print(f"mem: normal {mem_normal:9d} wino {mem_wino:9d} ratio {mem_ratio:.2f}") - self.assertLess(ops_ratio, 2.6) # TODO: there's issues with factorization now - self.assertLess(mem_ratio, 10) - - def test_dtype(self): - IC, OC, X, Y = 4,4,9,9 - x,w = Tensor.empty(1,IC,Y,X), Tensor.empty(OC,IC,3,3) - self.assertEqual(Tensor.conv2d(x,w).dtype, dtypes.default_float) - - x,w = Tensor.empty(1,IC,Y,X,dtype=dtypes.half), Tensor.empty(OC,IC,3,3,dtype=dtypes.half) - self.assertEqual(Tensor.conv2d(x,w).dtype, dtypes.half) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/test_zero_copy.py b/tinygrad/test/test_zero_copy.py deleted file mode 100644 index c8625780..00000000 --- a/tinygrad/test/test_zero_copy.py +++ /dev/null @@ -1,27 +0,0 @@ -import unittest -from tinygrad import Tensor, Device -import time - -def time_tensor_numpy(out:Tensor): - times = [] - for _ in range(5): - st = time.perf_counter() - out.uop.base.realized.as_buffer(allow_zero_copy=True) - et = time.perf_counter() - st - times.append(et) - return min(times) - -N = 4096 -class TestZeroCopy(unittest.TestCase): - @unittest.skipIf(Device.DEFAULT not in {"CPU", "LLVM", "METAL"}, "device isn't zero copy") - def test_zero_copy_from_default_to_cpu(self): - demo = Tensor.rand(1).realize() - t1 = time_tensor_numpy(demo) - out = Tensor.rand(N, N).realize() - t2 = time_tensor_numpy(out) - gbps = out.nbytes()*1e-9/max(t2-t1, 1e-10) - print(f"time(base): {t1*1e3:.2f} ms, time(copy): {t2*1e3:.2f} ms : copy speed {gbps:.2f} GB/s") - self.assertGreater(gbps, 600) # more than 600 GB/s = no copy - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/testextra/__init__.py b/tinygrad/test/testextra/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/test/testextra/test_bench_log.py b/tinygrad/test/testextra/test_bench_log.py deleted file mode 100644 index dd63f916..00000000 --- a/tinygrad/test/testextra/test_bench_log.py +++ /dev/null @@ -1,108 +0,0 @@ -import unittest, time -from unittest.case import skipIf - -from extra.bench_log import BenchEvent, InstantBenchEvent, WallTimeEvent, KernelTimeEvent, log_event_instant, _events, clear_events -from tinygrad.helpers import Context, CI -from tinygrad.tensor import Tensor -from tinygrad.device import Device - -class TestBenchLog(unittest.TestCase): - def setUp(self): - clear_events() - - def test_log_single_wall_time(self): - for event in BenchEvent: - with WallTimeEvent(event): - time.sleep(0.1) - - # check event list - for event in BenchEvent: - self.assertEqual(len(_events[event]["wall"]), 1) - self.assertGreater(_events[event]["wall"][0], 0) - - def test_log_double_wall_time(self): - for event in BenchEvent: - with WallTimeEvent(event): - time.sleep(0.1) - - for event in reversed(BenchEvent): - with WallTimeEvent(event): - time.sleep(0.2) - - # check event list - for event in BenchEvent: - self.assertEqual(len(_events[event]["wall"]), 2) - self.assertGreater(_events[event]["wall"][0], 0) - self.assertGreater(_events[event]["wall"][1], 0) - - @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") - def test_log_single_kernel_time(self): - wall_times = [] - - with Context(DEBUG=2): - for event in BenchEvent: - with KernelTimeEvent(event): - st = time.perf_counter() - Tensor.rand(32, 32).sum().realize().item() - wall_times.append(time.perf_counter() - st) - - # check event list - for event in BenchEvent: - self.assertEqual(len(_events[event]["kernel"]), 1) - self.assertLess(_events[event]["kernel"][0], wall_times[0]) - self.assertGreater(_events[event]["kernel"][0], 0) - - @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") - def test_interleaved_wall_kernel_time(self): - wall_times = [] - with Context(DEBUG=2): - for event in BenchEvent: - with KernelTimeEvent(event): - st = time.perf_counter() - Tensor.rand(32, 32).sum().realize().item() - wall_times.append(time.perf_counter() - st) - - with WallTimeEvent(event): - st = time.perf_counter() - Tensor.rand(32, 32).sum().realize().item() - wall_times.append(time.perf_counter() - st) - - # check event list - for event in BenchEvent: - self.assertEqual(len(_events[event]["wall"]), 1) - self.assertEqual(len(_events[event]["kernel"]), 1) - self.assertLess(_events[event]["kernel"][0], wall_times[0]) - self.assertGreater(_events[event]["kernel"][0], 0) - - @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") - def test_stacked_wall_kernel_time(self): - with Context(DEBUG=2): - for event in BenchEvent: - with KernelTimeEvent(event): - with WallTimeEvent(event): - Tensor.rand(32, 32).sum().realize().item() - - for event in BenchEvent: - with WallTimeEvent(event): - with KernelTimeEvent(event): - Tensor.rand(32, 32).sum().realize().item() - - for event in BenchEvent: - self.assertEqual(len(_events[event]["wall"]), 2) - self.assertEqual(len(_events[event]["kernel"]), 2) - self.assertLess(_events[event]["kernel"][0], _events[event]["wall"][0]) - self.assertGreater(_events[event]["kernel"][0], 0) - self.assertLess(_events[event]["kernel"][1], _events[event]["wall"][1]) - self.assertGreater(_events[event]["kernel"][1], 0) - - def test_log_instant_event(self): - for event in InstantBenchEvent: - log_event_instant(event, 1000) - - # check event list - for event in InstantBenchEvent: - self.assertEqual(len(_events[event]), 1) - self.assertEqual(_events[event][0], 1000) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/testextra/test_export_model.py b/tinygrad/test/testextra/test_export_model.py deleted file mode 100644 index 2b84e71f..00000000 --- a/tinygrad/test/testextra/test_export_model.py +++ /dev/null @@ -1,69 +0,0 @@ -import unittest -from extra.export_model import export_model, EXPORT_SUPPORTED_DEVICE -from tinygrad.tensor import Tensor, Device -from tinygrad import dtypes -import json - -class MockMultiInputModel: - def forward(self, x1, x2, x3): - return x1 + x2 + x3 - -class MockMultiOutputModel: - def __call__(self, x1): - return x1 + 2.0, x1.pad(((0, 0), (0, 1))) + 1.0 - -# TODO: move compile_efficientnet tests here -@unittest.skipUnless(Device.DEFAULT in EXPORT_SUPPORTED_DEVICE, f"Model export is not supported on {Device.DEFAULT}") -class TextModelExport(unittest.TestCase): - def test_multi_input_model_export(self): - model = MockMultiInputModel() - inputs = [Tensor.rand(2,2), Tensor.rand(2,2), Tensor.rand(2,2)] - prg, inp_sizes, _, _ = export_model(model, "", *inputs) - prg = json.loads(prg) - - assert len(inputs) == len(prg["inputs"]) == len(inp_sizes), f"Model and exported inputs don't match: mdl={len(inputs)}, prg={len(prg['inputs'])}, inp_sizes={len(inp_sizes)}" # noqa: E501 - - for i in range(len(inputs)): - assert f"input{i}" in inp_sizes, f"input{i} not captured in inp_sizes" - assert f"input{i}" in prg["buffers"], f"input{i} not captured in exported buffers" - - for i, exported_input in enumerate(prg["inputs"]): - assert inputs[i].dtype.name == exported_input["dtype"], f"Model and exported input dtype don't match: mdl={inputs[i].dtype.name}, prg={exported_input['dtype']}" # noqa: E501 - - def test_multi_output_model_export(self): - model = MockMultiOutputModel() - input_tensor = Tensor.rand(2,2) - outputs = model(input_tensor) - prg, _, out_sizes, _ = export_model(model, "", input_tensor) - prg = json.loads(prg) - - assert len(outputs) == len(prg["outputs"]) == len(out_sizes), f"Model and exported outputs don't match: mdl={len(outputs)}, prg={len(prg['outputs'])}, inp_sizes={len(out_sizes)}" # noqa: E501 - - for i in range(len(outputs)): - assert f"output{i}" in out_sizes, f"output{i} not captured in out_sizes" - assert f"output{i}" in prg["buffers"], f"output{i} not captured in exported buffers" - - for i, exported_output in enumerate(prg["outputs"]): - assert outputs[i].dtype.name == exported_output["dtype"], f"Model and exported output dtype don't match: mdl={outputs[i].dtype.name}, prg={exported_output['dtype']}" # noqa: E501 - -@unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Testing WebGPU specific model export behavior") -class TextModelExportWebGPU(unittest.TestCase): - def test_exported_input_output_dtypes(self): - class MyModel: - def forward(self, *inputs): return tuple([(inp+2).cast(inp.dtype) for inp in inputs]) - model = MyModel() - # [:-1] because "ulong" and "long" is not supported - inputs = [Tensor.randn(2, dtype=dt) for dt in dtypes.uints[:-1] + dtypes.sints[:-1] + (dtypes.bool, dtypes.float)] - prg, _, _, _ = export_model(model, "webgpu", *inputs) - expected_buffer_types = ["Uint"]*len(dtypes.uints[:-1]) + ["Int"]*len(dtypes.sints[:-1]) + ["Int", "Float"] - for i, expected_buffer_type in enumerate(expected_buffer_types): - dt = inputs[i].dtype - expected_arr_prefix = f"{expected_buffer_type}{dt.itemsize*8}" - # test input buffers - self.assertIn(f"new {expected_arr_prefix}Array(gpuWriteBuffer{i}.getMappedRange()).set(_input{i});", prg) - # test output buffers - self.assertIn(f"const resultBuffer{i} = new {expected_arr_prefix}Array(gpuReadBuffer{i}.size/{dt.itemsize});", prg) - self.assertIn(f"resultBuffer{i}.set(new {expected_arr_prefix}Array(gpuReadBuffer{i}.getMappedRange()));", prg) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/testextra/test_f16_decompress.py b/tinygrad/test/testextra/test_f16_decompress.py deleted file mode 100644 index 68068770..00000000 --- a/tinygrad/test/testextra/test_f16_decompress.py +++ /dev/null @@ -1,16 +0,0 @@ -import unittest -from extra.f16_decompress import u32_to_f16 -from tinygrad.tensor import Tensor -from tinygrad.device import is_dtype_supported -from tinygrad import dtypes -import numpy as np - -class TestF16Decompression(unittest.TestCase): - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16") - def test_u32_to_f16(self): - a = Tensor.randn(50, dtype=dtypes.float16) - f16_as_u32 = a.bitcast(dtypes.uint32) - f16 = u32_to_f16(f16_as_u32) - ref = a.numpy() - out = f16.numpy().astype(np.float16) - np.testing.assert_allclose(out, ref) diff --git a/tinygrad/test/testextra/test_lr_scheduler.py b/tinygrad/test/testextra/test_lr_scheduler.py deleted file mode 100644 index ce7464ec..00000000 --- a/tinygrad/test/testextra/test_lr_scheduler.py +++ /dev/null @@ -1,125 +0,0 @@ -import numpy as np -import torch -import unittest -from tinygrad.tensor import Tensor -from tinygrad.nn.state import get_parameters -from tinygrad.nn.optim import Adam, SGD -from tinygrad.helpers import DEBUG -from extra.lr_scheduler import MultiStepLR, ReduceLROnPlateau, CosineAnnealingLR, OneCycleLR -from extra.training import train, evaluate -from extra.datasets import fetch_mnist - -np.random.seed(1337) -Tensor.manual_seed(1337) - -X_train, Y_train, X_test, Y_test = fetch_mnist() - -class TinyBobNet: - def __init__(self): - self.l1 = Tensor.scaled_uniform(784, 128) - self.l2 = Tensor.scaled_uniform(128, 10) - - def parameters(self): - return get_parameters(self) - - def forward(self, x): - return x.dot(self.l1).relu().dot(self.l2).log_softmax() - -def lr_scheduler_training(sched_fn=None, args=None): - model = TinyBobNet() - optim = Adam(model.parameters(), lr=0.01) - if sched_fn is not None: sched = sched_fn(optim, **args) - for _ in range(25): - train(model, X_train, Y_train, optim, 100) - if sched_fn is not None: - if isinstance(sched, ReduceLROnPlateau): - sched.step(evaluate(model, X_test, Y_test)) - else: - sched.step() - return evaluate(model, X_test, Y_test) - -def current_lr(optim): return optim.param_groups[0]['lr'] if hasattr(optim, 'param_groups') else optim.lr -def get_lrs(optim, sched, epochs, steps=1, accs=None): - lr = current_lr(optim) - if not isinstance(lr, float): lr = lr.numpy()[0] - lrs = [lr] - for e in range(epochs): - for _ in range(steps): - optim.step() - sched.step() if accs is None else sched.step(accs[e]) - lr = current_lr(optim) - if not isinstance(lr, float): lr = lr.numpy()[0] - lrs.append(lr) - return lrs - -class TestLrScheduler(unittest.TestCase): - def setUp(self): - self.old_training = Tensor.training - Tensor.training = True - def tearDown(self): - Tensor.training = self.old_training - - def _test_lr_scheduler(self, tinygrad_sched, torch_sched, epochs, opts, atol, rtol, adam=True): - accs = opts.pop('accs', None) - test_tensor = Tensor([0.], requires_grad=True) # NOTE: optimizers are broken on 0-dim tensors because it broadcasts to [lr] - test_tensor.mean().backward() - if adam: - tinygrad_optim, torch_optim = Adam([test_tensor], lr=0.01), torch.optim.Adam([torch.tensor([0.], requires_grad=True)], lr=0.01) - else: - tinygrad_optim, torch_optim = SGD([test_tensor], lr=0.01), torch.optim.SGD([torch.tensor([0.], requires_grad=True)], lr=0.01) - tinygrad_sched, torch_sched = tinygrad_sched(tinygrad_optim, **opts), torch_sched(torch_optim, **opts) - - tinygrad_lrs = get_lrs(tinygrad_optim, tinygrad_sched, epochs, accs=accs) - torch_lrs = get_lrs(torch_optim, torch_sched, epochs, accs=accs) - - np.testing.assert_allclose(tinygrad_lrs, torch_lrs, atol=atol, rtol=rtol) - - def _test_multisteplr(self, epochs, opts, atol, rtol, adam=True): - self._test_lr_scheduler(MultiStepLR, torch.optim.lr_scheduler.MultiStepLR, epochs, opts, atol, rtol, adam=adam) - def _test_reducelronplateau(self, epochs, opts, atol, rtol): - opts['accs'] = np.random.randn(epochs) - self._test_lr_scheduler(ReduceLROnPlateau, torch.optim.lr_scheduler.ReduceLROnPlateau, epochs, opts, atol, rtol) - def _test_cosineannealinglr(self, epochs, opts, atol, rtol): - opts['T_max'] = epochs - self._test_lr_scheduler(CosineAnnealingLR, torch.optim.lr_scheduler.CosineAnnealingLR, epochs, opts, atol, rtol) - def _test_onecyclelr(self, epochs, opts, atol, rtol): - opts['total_steps'] = epochs - self._test_lr_scheduler(OneCycleLR, torch.optim.lr_scheduler.OneCycleLR, epochs, opts, atol, rtol) - - def test_multisteplr(self): self._test_multisteplr(10, {'milestones': [1, 2, 7]}, 1e-6, 1e-6) - def test_multisteplr_gamma(self): self._test_multisteplr(10, {'milestones': [1, 2, 7], 'gamma': 0.1337}, 1e-6, 1e-6) - - def test_reducelronplateau(self): self._test_reducelronplateau(100, {}, 1e-6, 1e-6) - def test_reducelronplateau_max(self): self._test_reducelronplateau(100, {'mode': 'max'}, 1e-6, 1e-6) - def test_reducelronplateau_factor(self): self._test_reducelronplateau(100, {'factor': 0.1337}, 1e-6, 1e-6) - def test_reducelronplateau_patience(self): self._test_reducelronplateau(100, {'patience': 3}, 1e-6, 1e-6) - def test_reducelronplateau_threshold(self): self._test_reducelronplateau(100, {'threshold': 1e-6}, 1e-6, 1e-6) - def test_reducelronplateau_threshold_mode(self): self._test_reducelronplateau(100, {'threshold_mode': 'abs'}, 1e-6, 1e-6) - - def test_cosineannealinglr(self): self._test_cosineannealinglr(100, {}, 1e-6, 1e-6) - def test_cosineannealinglr_eta_min(self): self._test_cosineannealinglr(100, {'eta_min': 0.001}, 1e-6, 1e-6) - - def test_multistep_2step(self): - # was making this fail with LRU=1, some issue with epoch_counter - if DEBUG>=2: print("first") - self._test_multisteplr(1, {'milestones': [1]}, 1e-6, 1e-6, adam=False) - if DEBUG>=2: print("second") - self._test_multisteplr(1, {'milestones': [1], 'gamma': 0.133}, 1e-6, 1e-6, adam=False) - if DEBUG>=2: print("third") - - def test_onecyclelr(self): self._test_onecyclelr(100, {'pct_start': 0.3, 'anneal_strategy': 'linear', - 'cycle_momentum': False, 'div_factor': 25.0, - 'final_div_factor': 10000.0, 'max_lr':1e-5}, 1e-6, 1e-6) - @unittest.skip("slow") - def test_training(self): - without = lr_scheduler_training() - sched_fns = [MultiStepLR, ReduceLROnPlateau, CosineAnnealingLR, OneCycleLR] - argss = [{'milestones': [5, 7, 10, 15], 'gamma': 0.5}, {'factor': 0.5, 'patience': 2}, {'T_max': 25, 'eta_min': 0.001}, - {'pct_start': 0.3, 'anneal_strategy': 'linear', 'cycle_momentum': False, 'div_factor': 25.0, 'final_div_factor': 10000.0, - 'max_lr':1e-5, 'total_steps': 25}] - for sched_fn, args in zip(sched_fns, argss): - with_sched = lr_scheduler_training(sched_fn, args) - assert with_sched > without - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/testextra/test_mockgpu.py b/tinygrad/test/testextra/test_mockgpu.py deleted file mode 100644 index 0f1d6164..00000000 --- a/tinygrad/test/testextra/test_mockgpu.py +++ /dev/null @@ -1,13 +0,0 @@ -from tinygrad.helpers import getenv -import unittest, importlib - -@unittest.skipUnless(getenv("MOCKGPU"), 'Testing mockgpu') -class TestMockGPU(unittest.TestCase): - # https://github.com/tinygrad/tinygrad/pull/7627 - def test_import_typing_extensions(self): - import test.mockgpu.mockgpu # noqa: F401 # pylint: disable=unused-import - import typing_extensions - importlib.reload(typing_extensions) # pytest imports typing_extension before mockgpu - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/unit/__init__.py b/tinygrad/test/unit/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/test/unit/test_allreduce.py b/tinygrad/test/unit/test_allreduce.py deleted file mode 100644 index a3030966..00000000 --- a/tinygrad/test/unit/test_allreduce.py +++ /dev/null @@ -1,29 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad.helpers import Context -from tinygrad.uop.ops import Ops - -class TestRingAllReduce(unittest.TestCase): - def test_schedule_ring(self): - with Context(RING=2): - N = 4 - ds = tuple(f"CPU:{i}" for i in range(N)) - t = Tensor.empty(N, N*100).shard(ds, axis=0).realize() - schedules = t.sum(0).schedule_with_vars()[0] - copies = [si for si in schedules if si.ast.op is Ops.COPY] - pairs = [(c.bufs[0].device, c.bufs[1].device) for c in copies] - # N*(N-1) scatter reduce, and N*(N-1) allgather - self.assertEqual(len(pairs), N*(N-1)*2) - # copy topology forms a ring - self.assertEqual(len(set(pairs)), N) - - def test_correct_ring(self): - with Context(RING=2): - N = 4 - ds = tuple(f"CPU:{i}" for i in range(N)) - t = Tensor.ones(N, N*100).contiguous().shard(ds, axis=0).realize() - out = t.sum(0) - self.assertListEqual(out.tolist(), [4]*N*100) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_attention.py b/tinygrad/test/unit/test_attention.py deleted file mode 100644 index 9929dbc3..00000000 --- a/tinygrad/test/unit/test_attention.py +++ /dev/null @@ -1,20 +0,0 @@ -import unittest -from tinygrad import Tensor, dtypes - -# TODO: test_scheduler, but just in uint -class TestAttention(unittest.TestCase): - def test_half_qkv_buffers(self): - BS, seqlen, dim = 10, 4, 100 - q = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() - k = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() - v = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() - attn = q.scaled_dot_product_attention(k, v) - sched = attn.schedule() - # attention has 5 kernels now - self.assertEqual(len(sched), 5) - softmax_inputs = sched[1:4] - for si in softmax_inputs: - assert all(b.dtype == dtypes.half for b in si.bufs), f"non half {si.bufs=}" - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/unit/test_block_reorder.py b/tinygrad/test/unit/test_block_reorder.py deleted file mode 100644 index 24488d23..00000000 --- a/tinygrad/test/unit/test_block_reorder.py +++ /dev/null @@ -1,76 +0,0 @@ -import unittest, random -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import print_uops, UOp, Ops -from tinygrad.codegen.linearize import block_reorder -from tinygrad.renderer.cstyle import OpenCLRenderer - -def is_toposorted(lst:list[UOp]): - seen = set() - for u in lst: - if any(p not in seen for p in u.src): return False - seen.add(u) - return True - -class TestBlockReorder(unittest.TestCase): - def _test_randomize(self, golden:list[UOp]): - # test random order is always same - for _ in range(50): - # shuffle and form a valid toposort - lst = golden[:] - random.shuffle(lst) - topolst = [] - for u in lst: - for p in u.toposort(): - if p not in topolst: topolst.append(p) - assert is_toposorted(topolst) - - for x,y in zip(golden, this_order:=block_reorder(topolst)): - if x is not y: - print_uops(golden) - print_uops(this_order) - self.assertIs(x, y) - - def _test_render(self, golden:list[UOp]): - return OpenCLRenderer().render(golden) - - def test_loads(self): - a = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=0) - b = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=1) - c = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=2) - v1 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx0", 4)) - v2 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx1", 4)) - v1 = v1*27 - v2 = v2*4 - loads = [ - a.index(v1).load(dtype=dtypes.float), - a.index(v1+1).load(dtype=dtypes.float), - a.index(v1+2).load(dtype=dtypes.float), - a.index(v1+3).load(dtype=dtypes.float), - b.index(v2).load(dtype=dtypes.float), - b.index(v2+1).load(dtype=dtypes.float), - b.index(v2+2).load(dtype=dtypes.float), - b.index(v2+3).load(dtype=dtypes.float)] - #random.shuffle(loads) - sink = c.store(sum(loads)).sink() - - # determine golden order - golden = block_reorder(sink.toposort()) - - # render for test - print(self._test_render(golden)) - #print_uops(golden) - - # assert the loads are in this order - self.assertListEqual([g.src[0].src[1].render() for g in golden if g.op is Ops.LOAD], - ['(gidx1*4)', '((gidx1*4)+1)', '((gidx1*4)+2)', '((gidx1*4)+3)', - '(gidx0*27)', '((gidx0*27)+1)', '((gidx0*27)+2)', '((gidx0*27)+3)']) - - # assert math is after loads - first_math = [i for i,g in enumerate(golden) if g.op is Ops.ADD and g.dtype == dtypes.float][0] - assert not any(x.op is Ops.LOAD for x in golden[first_math:]) - - # confirm the sort is stable - self._test_randomize(golden) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_conv.py b/tinygrad/test/unit/test_conv.py deleted file mode 100644 index 6091a9c4..00000000 --- a/tinygrad/test/unit/test_conv.py +++ /dev/null @@ -1,132 +0,0 @@ -import unittest -import numpy as np -from tinygrad.tensor import Tensor -from tinygrad.helpers import Context - -class TestConv(unittest.TestCase): - def test_simple(self): - x = Tensor.ones(1,12,16,32).contiguous().realize() - w = Tensor.ones(32,12,3,3).contiguous().realize() - ret = x.conv2d(w, stride=(2,2), padding=(1,1)).numpy() - # it's not 108 around the padding - assert (ret[:, :, 1:-1, 1:-1] == 108).all() - assert ret[0,0,0,0] == 48 - assert ret[0,0,0,1] == 72 - - def test_simple_rand(self): - x = Tensor.rand(1,12,16,32) - w = Tensor.rand(32,12,3,3) - x.conv2d(w, stride=(2,2), padding=(1,1)).numpy() - - def test_many_simple(self): - x = Tensor(np.arange(8*2*8).reshape(1,8,2,8).astype(np.float32)) - #w = Tensor(np.arange(8*8*1*1).reshape(8,8,1,1).astype(np.float32)) - w = Tensor.eye(8).reshape((8,8,1,1)) - ret = x.conv2d(w, stride=(1,2), padding=(0,0)).numpy() - print(ret) - - def test_lazycache(self): - x = Tensor.rand(1, 32) - y = Tensor.rand(32) - out = x + y.reshape((1,32,1)).reshape((1,32)) + y.reshape((1,32,1)).reshape((1,32)) - out.numpy() - - def test_simple_biased(self): - C = 8 - x = Tensor.rand(1,C,5,5) - w = Tensor.eye(C).reshape((C,C,1,1)) - b = Tensor(np.arange(C).astype(np.float32)) - ret = Tensor.conv2d(x,w,b).relu().conv2d(w,b) - - print(ret.numpy()) - - def test_two_binops_no_rerun_small(self): - x = Tensor.rand(1,1,32,32) - w = Tensor.rand(1,1,3,3) - out = x.conv2d(w, padding=(1,1)) - np.testing.assert_allclose(out.relu().numpy(), np.maximum(out.numpy(), 0)) - - def test_two_binops_no_rerun(self): - x = Tensor.randn(1,12,16,32) - w = Tensor.randn(32,12,3,3) - out = x.conv2d(w, stride=(2,2), padding=(1,1)) - r1, r2 = out.relu(), (out-1) - np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) - np.testing.assert_allclose(r2.numpy(), out.numpy() - 1) - - def test_two_overlapping_binops_no_rerun(self): - x = Tensor.randn(1,12,16,32) - w = Tensor.randn(32,12,3,3) - out = x.conv2d(w, stride=(2,2), padding=(1,1)) - r1, r2 = out.relu(), out.elu() - np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) - np.testing.assert_allclose(r2.numpy(), np.where(out.numpy() > 0, out.numpy(), (np.exp(out.numpy()) - 1)), atol=1e-5) - - def test_two_overlapping_binops_no_rerun_wino(self): - with Context(WINO=1): - x = Tensor.randn(1,4,16,16) - w = Tensor.randn(6,4,3,3) - out = x.conv2d(w, padding=(1,1)) - r1, r2 = out.relu(), out.elu() - np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) - np.testing.assert_allclose(r2.numpy(), np.where(out.numpy() > 0, out.numpy(), (np.exp(out.numpy()) - 1)), atol=1e-5) - - def test_first_three(self): - x = Tensor.rand(1,12,16,32) - - w = Tensor.rand(32,12,3,3) - x = x.conv2d(w, stride=(2,2), padding=(1,1)).elu() - - w = Tensor.rand(32,1,3,3) - x = x.conv2d(w, padding=(1,1), groups=32).elu() - - w = Tensor.rand(16,32,1,1) - x = x.conv2d(w).elu() - - x = x.numpy() - print(x.shape) - - def test_elu(self): - x = Tensor.rand(1,12,16,32) - - w = Tensor.rand(32,12,3,3) - x = x.conv2d(w, stride=(2,2), padding=(1,1)) - - x = x.elu() - - w = Tensor.rand(32,1,3,3) - x = x.conv2d(w, padding=(1,1), groups=32) - x.numpy() - - def test_reduce_relu(self): - x = Tensor.rand(1,12,16,32) - x = x.sum(keepdim=True).relu() - x.numpy() - - def test_bias(self): - from tinygrad.nn import Conv2d - x = Tensor.rand(1,12,16,32) - c = Conv2d(12, 32, 3) - x = c(x).relu() - w = Tensor.uniform(32, 1, 3, 3) - x = x.conv2d(w, groups=32) - x.numpy() - - def test_multiadd(self): - w = Tensor.rand(32) - x = Tensor.rand(32).relu() - (w+x).numpy() - - def test_reorder(self): - x = Tensor.rand(1,12,16,32) - w = Tensor.rand(12,12,3,3) - x = x.conv2d(w, padding=(1,1)) - print(x.shape) - x = x.reshape((1, 12, 32, 16)) - x += 1 - x += 1 - x = x.reshape((1, 12, 16, 32)) - x.numpy() - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_device.py b/tinygrad/test/unit/test_device.py deleted file mode 100644 index 1f20cebd..00000000 --- a/tinygrad/test/unit/test_device.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env python -import unittest -from tinygrad import Tensor -from tinygrad.device import Device, Compiler -from tinygrad.helpers import diskcache_get, diskcache_put, getenv, Context - -class TestDevice(unittest.TestCase): - def test_canonicalize(self): - self.assertEqual(Device.canonicalize(None), Device.DEFAULT) - self.assertEqual(Device.canonicalize("CPU"), "CPU") - self.assertEqual(Device.canonicalize("cpu"), "CPU") - self.assertEqual(Device.canonicalize("GPU"), "GPU") - self.assertEqual(Device.canonicalize("GPU:0"), "GPU") - self.assertEqual(Device.canonicalize("gpu:0"), "GPU") - self.assertEqual(Device.canonicalize("GPU:1"), "GPU:1") - self.assertEqual(Device.canonicalize("gpu:1"), "GPU:1") - self.assertEqual(Device.canonicalize("GPU:2"), "GPU:2") - self.assertEqual(Device.canonicalize("disk:/dev/shm/test"), "DISK:/dev/shm/test") - self.assertEqual(Device.canonicalize("disk:000.txt"), "DISK:000.txt") - - def test_getitem_not_exist(self): - with self.assertRaises(ModuleNotFoundError): - Device["TYPO"] - - def test_lowercase_canonicalizes(self): - device = Device.DEFAULT - Device.DEFAULT = device.lower() - self.assertEqual(Device.canonicalize(None), device) - Device.DEFAULT = device - -class MockCompiler(Compiler): - def __init__(self, key): super().__init__(key) - def compile(self, src) -> bytes: return src.encode() - -class TestCompiler(unittest.TestCase): - def test_compile_cached(self): - diskcache_put("key", "123", None) # clear cache - getenv.cache_clear() - with Context(DISABLE_COMPILER_CACHE=0): - self.assertEqual(MockCompiler("key").compile_cached("123"), str.encode("123")) - self.assertEqual(diskcache_get("key", "123"), str.encode("123")) - - def test_compile_cached_disabled(self): - diskcache_put("disabled_key", "123", None) # clear cache - getenv.cache_clear() - with Context(DISABLE_COMPILER_CACHE=1): - self.assertEqual(MockCompiler("disabled_key").compile_cached("123"), str.encode("123")) - self.assertIsNone(diskcache_get("disabled_key", "123")) - - def test_device_compile(self): - getenv.cache_clear() - with Context(DISABLE_COMPILER_CACHE=1): - a = Tensor([0.,1.], device=Device.DEFAULT).realize() - (a + 1).realize() - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_disk_cache.py b/tinygrad/test/unit/test_disk_cache.py deleted file mode 100644 index 6ddf1abe..00000000 --- a/tinygrad/test/unit/test_disk_cache.py +++ /dev/null @@ -1,108 +0,0 @@ -import unittest -import pickle -from tinygrad.helpers import diskcache_get, diskcache_put, diskcache, diskcache_clear - -def remote_get(table,q,k): q.put(diskcache_get(table, k)) -def remote_put(table,k,v): diskcache_put(table, k, v) - -class DiskCache(unittest.TestCase): - def test_putget(self): - table = "test_putget" - diskcache_put(table, "hello", "world") - self.assertEqual(diskcache_get(table, "hello"), "world") - diskcache_put(table, "hello", "world2") - self.assertEqual(diskcache_get(table, "hello"), "world2") - - def test_putcomplex(self): - table = "test_putcomplex" - diskcache_put(table, "k", ("complex", 123, "object")) - ret = diskcache_get(table, "k") - self.assertEqual(ret, ("complex", 123, "object")) - - def test_getotherprocess(self): - table = "test_getotherprocess" - from multiprocessing import Process, Queue - diskcache_put(table, "k", "getme") - q = Queue() - p = Process(target=remote_get, args=(table,q,"k")) - p.start() - p.join() - self.assertEqual(q.get(), "getme") - - def test_putotherprocess(self): - table = "test_putotherprocess" - from multiprocessing import Process - p = Process(target=remote_put, args=(table,"k", "remote")) - p.start() - p.join() - self.assertEqual(diskcache_get(table, "k"), "remote") - - def test_no_table(self): - self.assertIsNone(diskcache_get("faketable", "k")) - - def test_ret(self): - table = "test_ret" - self.assertEqual(diskcache_put(table, "key", ("vvs",)), ("vvs",)) - - def test_non_str_key(self): - table = "test_non_str_key" - diskcache_put(table, 4, 5) - self.assertEqual(diskcache_get(table, 4), 5) - self.assertEqual(diskcache_get(table, "4"), 5) - - def test_decorator(self): - calls = 0 - @diskcache - def hello(x): - nonlocal calls - calls += 1 - return "world"+x - self.assertEqual(hello("bob"), "worldbob") - self.assertEqual(hello("billy"), "worldbilly") - kcalls = calls - self.assertEqual(hello("bob"), "worldbob") - self.assertEqual(hello("billy"), "worldbilly") - self.assertEqual(kcalls, calls) - - def test_dict_key(self): - table = "test_dict_key" - fancy_key = {"hello": "world", "goodbye": 7, "good": True, "pkl": pickle.dumps("cat")} - fancy_key2 = {"hello": "world", "goodbye": 8, "good": True, "pkl": pickle.dumps("cat")} - fancy_key3 = {"hello": "world", "goodbye": 8, "good": True, "pkl": pickle.dumps("dog")} - diskcache_put(table, fancy_key, 5) - self.assertEqual(diskcache_get(table, fancy_key), 5) - diskcache_put(table, fancy_key2, 8) - self.assertEqual(diskcache_get(table, fancy_key2), 8) - self.assertEqual(diskcache_get(table, fancy_key), 5) - self.assertEqual(diskcache_get(table, fancy_key3), None) - - def test_table_name(self): - table = "test_gfx1010:xnack-" - diskcache_put(table, "key", "test") - self.assertEqual(diskcache_get(table, "key"), "test") - - @unittest.skip("disabled by default because this drops cache table") - def test_clear_cache(self): - # clear cache to start - diskcache_clear() - tables = [f"test_clear_cache:{i}" for i in range(3)] - for table in tables: - # check no entries - self.assertIsNone(diskcache_get(table, "k")) - for table in tables: - diskcache_put(table, "k", "test") - # check insertion - self.assertEqual(diskcache_get(table, "k"), "test") - - diskcache_clear() - for table in tables: - # check no entries again - self.assertIsNone(diskcache_get(table, "k")) - - # calling multiple times is fine - diskcache_clear() - diskcache_clear() - diskcache_clear() - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_disk_tensor.py b/tinygrad/test/unit/test_disk_tensor.py deleted file mode 100644 index 74a8fee8..00000000 --- a/tinygrad/test/unit/test_disk_tensor.py +++ /dev/null @@ -1,414 +0,0 @@ -import pathlib, tempfile, unittest -import numpy as np -from tinygrad import Tensor, Device, dtypes -from tinygrad.dtype import DType -from tinygrad.nn.state import safe_load, safe_save, get_state_dict, torch_load -from tinygrad.helpers import Timing, fetch, temp, CI, OSX -from tinygrad.device import is_dtype_supported - -def compare_weights_both(url): - import torch - fn = fetch(url) - tg_weights = get_state_dict(torch_load(fn)) - torch_weights = get_state_dict(torch.load(fn, map_location=torch.device('cpu'), weights_only=False), tensor_type=torch.Tensor) - assert list(tg_weights.keys()) == list(torch_weights.keys()) - for k in tg_weights: - if tg_weights[k].dtype == dtypes.bfloat16: tg_weights[k] = torch_weights[k].float() # numpy doesn't support bfloat16 - if torch_weights[k].dtype == torch.bfloat16: torch_weights[k] = torch_weights[k].float() # numpy doesn't support bfloat16 - if torch_weights[k].requires_grad: torch_weights[k] = torch_weights[k].detach() - np.testing.assert_equal(tg_weights[k].numpy(), torch_weights[k].numpy(), err_msg=f"mismatch at {k}, {tg_weights[k].shape}") - print(f"compared {len(tg_weights)} weights") - -class TestTorchLoad(unittest.TestCase): - # pytorch pkl format - def test_load_enet(self): compare_weights_both("https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b0-355c32eb.pth") - # pytorch zip format - def test_load_enet_alt(self): compare_weights_both("https://download.pytorch.org/models/efficientnet_b0_rwightman-3dd342df.pth") - # pytorch zip format - def test_load_convnext(self): compare_weights_both('https://dl.fbaipublicfiles.com/convnext/convnext_tiny_1k_224_ema.pth') - - @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") - def test_load_llama2bfloat(self): compare_weights_both("https://huggingface.co/qazalin/bf16-lightweight/resolve/main/consolidated.00.pth?download=true") - - # pytorch tar format - def test_load_resnet(self): compare_weights_both('https://download.pytorch.org/models/resnet50-19c8e357.pth') - -test_fn = pathlib.Path(__file__).parents[2] / "weights/LLaMA/7B/consolidated.00.pth" -#test_size = test_fn.stat().st_size -test_size = 1024*1024*1024*2 - -def _test_bitcasted(t: Tensor, dt: DType, expected): - np.testing.assert_allclose(t.bitcast(dt).numpy(), expected) - -# sudo su -c 'sync; echo 1 > /proc/sys/vm/drop_caches' && python3 test/unit/test_disk_tensor.py TestRawDiskBuffer.test_readinto_read_speed -class TestRawDiskBuffer(unittest.TestCase): - @unittest.skipIf(not test_fn.exists(), "download LLaMA weights for read in speed tests") - def test_readinto_read_speed(self): - tst = np.empty(test_size, np.uint8) - with open(test_fn, "rb") as f: - with Timing("copy in ", lambda et_ns: f" {test_size/et_ns:.2f} GB/s"): - f.readinto(tst) - def test_bitcasts_on_disk(self): - _, tmp = tempfile.mkstemp() - # ground truth = https://evanw.github.io/float-toy/ - t = Tensor.empty((128, 128), dtype=dtypes.uint8, device=f"disk:{tmp}") # uint8 - # all zeroes - _test_bitcasted(t, dtypes.float16, 0.0) - _test_bitcasted(t, dtypes.uint16, 0) - _test_bitcasted(t, dtypes.float32, 0.0) - _test_bitcasted(t, dtypes.uint32, 0) - # pi in float16 stored via int16 - t.bitcast(dtypes.uint16).assign(Tensor.full((128, 64), 0x4248, dtype=dtypes.uint16)).realize() - _test_bitcasted(t, dtypes.float16, 3.140625) - _test_bitcasted(t, dtypes.float32, 50.064727) - _test_bitcasted(t, dtypes.uint16, 0x4248) - _test_bitcasted(t, dtypes.uint32, 0x42484248) - # pi in float32 stored via float32 - t.bitcast(dtypes.float32).assign(Tensor.full((128, 32), 3.1415927, dtype=dtypes.float32)).realize() - _test_bitcasted(t, dtypes.float32, 3.1415927) - _test_bitcasted(t, dtypes.uint32, 0x40490FDB) - # doesn't suport normal cast - with self.assertRaises(NotImplementedError): - Tensor.empty((4,), dtype=dtypes.int16, device=f"disk:{tmp}").cast(dtypes.float16).realize() - - # Those two should be moved to test_dtype.py:test_shape_change_bitcast after bitcast works on non-disk - with self.assertRaises(RuntimeError): - # should fail because 3 int8 is 3 bytes but float16 is two and 3 isn't a multiple of 2 - Tensor.empty((3,), dtype=dtypes.int8, device=f"DISK:{tmp}").bitcast(dtypes.float16) - - with self.assertRaises(RuntimeError): - # should fail because backprop through bitcast is undefined - Tensor.empty((4,), dtype=dtypes.int8, requires_grad=True, device=f"DISK:{tmp}").bitcast(dtypes.float16) - - pathlib.Path(tmp).unlink() - -@unittest.skipUnless(is_dtype_supported(dtypes.uint8), "need uint8") -class TestSafetensors(unittest.TestCase): - def test_real_safetensors(self): - import torch - from safetensors.torch import save_file - torch.manual_seed(1337) - tensors = { - "weight1": torch.randn((16, 16)), - "weight2": torch.arange(0, 17, dtype=torch.uint8), - "weight3": torch.arange(0, 17, dtype=torch.int32).reshape(17,1,1), - "weight4": torch.arange(0, 2, dtype=torch.uint8), - } - save_file(tensors, temp("real.safetensors")) - - ret = safe_load(temp("real.safetensors")) - for k,v in tensors.items(): np.testing.assert_array_equal(ret[k].numpy(), v.numpy()) - safe_save(ret, temp("real.safetensors_alt")) - with open(temp("real.safetensors"), "rb") as f: - with open(temp("real.safetensors_alt"), "rb") as g: - assert f.read() == g.read() - ret2 = safe_load(temp("real.safetensors_alt")) - for k,v in tensors.items(): np.testing.assert_array_equal(ret2[k].numpy(), v.numpy()) - - def test_real_safetensors_open(self): - fn = temp("real_safe") - state_dict = {"tmp": Tensor.rand(10,10)} - safe_save(state_dict, fn) - import os - assert os.path.getsize(fn) == 8+0x40+(10*10*4) - from safetensors import safe_open - with safe_open(fn, framework="pt", device="cpu") as f: - assert sorted(f.keys()) == sorted(state_dict.keys()) - for k in f.keys(): - np.testing.assert_array_equal(f.get_tensor(k).numpy(), state_dict[k].numpy()) - - @unittest.skip("this test takes 7 seconds. TODO: make disk assign lazy") - def test_efficientnet_safetensors(self): - from extra.models.efficientnet import EfficientNet - model = EfficientNet(0) - state_dict = get_state_dict(model) - safe_save(state_dict, temp("eff0")) - state_dict_loaded = safe_load(temp("eff0")) - assert sorted(state_dict_loaded.keys()) == sorted(state_dict.keys()) - for k,v in state_dict.items(): - np.testing.assert_array_equal(v.numpy(), state_dict_loaded[k].numpy()) - - # load with the real safetensors - from safetensors import safe_open - with safe_open(temp("eff0"), framework="pt", device="cpu") as f: - assert sorted(f.keys()) == sorted(state_dict.keys()) - for k in f.keys(): - np.testing.assert_array_equal(f.get_tensor(k).numpy(), state_dict[k].numpy()) - - def _test_huggingface_enet_safetensors(self, fn): - state_dict = safe_load(fn) - assert len(state_dict.keys()) == 244 - assert 'blocks.2.2.se.conv_reduce.weight' in state_dict - assert state_dict['blocks.0.0.bn1.num_batches_tracked'].numpy() == 276570 - assert state_dict['blocks.2.0.bn2.num_batches_tracked'].numpy() == 276570 - - def test_huggingface_enet_safetensors(self): - # test a real file - fn = fetch("https://huggingface.co/timm/mobilenetv3_small_075.lamb_in1k/resolve/main/model.safetensors") - self._test_huggingface_enet_safetensors(fn) - - def test_huggingface_enet_safetensors_fromurl(self): - # test tensor input - t = Tensor.from_url("https://huggingface.co/timm/mobilenetv3_small_075.lamb_in1k/resolve/main/model.safetensors") - self._test_huggingface_enet_safetensors(t) - - def test_metadata(self): - metadata = {"hello": "world"} - safe_save({}, temp('metadata.safetensors'), metadata) - import struct - with open(temp('metadata.safetensors'), 'rb') as f: - dat = f.read() - sz = struct.unpack(">Q", dat[0:8])[0] - import json - assert json.loads(dat[8:8+sz])['__metadata__']['hello'] == 'world' - - def test_save_all_dtypes(self): - for dtype in dtypes.fields().values(): - if dtype in [dtypes.bfloat16]: continue # not supported in numpy - if dtype in [dtypes.double, *dtypes.fp8s] and Device.DEFAULT == "METAL": continue # not supported on METAL - path = temp(f"ones.{dtype}.safetensors") - ones = Tensor(np.random.rand(10,10), dtype=dtype) - safe_save(get_state_dict(ones), path) - np.testing.assert_equal(ones.numpy(), list(safe_load(path).values())[0].numpy()) - - def test_load_supported_types(self): - import torch - from safetensors.torch import save_file - from safetensors.numpy import save_file as np_save_file - torch.manual_seed(1337) - tensors = { - "weight_F16": torch.randn((2, 2), dtype=torch.float16), - "weight_F32": torch.randn((2, 2), dtype=torch.float32), - "weight_U8": torch.tensor([1, 2, 3], dtype=torch.uint8), - "weight_I8": torch.tensor([-1, 2, 3], dtype=torch.int8), - "weight_I32": torch.tensor([-1, 2, 3], dtype=torch.int32), - "weight_I64": torch.tensor([-1, 2, 3], dtype=torch.int64), - "weight_F64": torch.randn((2, 2), dtype=torch.double), - "weight_BOOL": torch.tensor([True, False], dtype=torch.bool), - "weight_I16": torch.tensor([127, 64], dtype=torch.short), - "weight_BF16": torch.randn((2, 2), dtype=torch.bfloat16), - } - save_file(tensors, temp("dtypes.safetensors")) - - loaded = safe_load(temp("dtypes.safetensors")) - for k,v in loaded.items(): - if v.dtype != dtypes.bfloat16: - assert v.numpy().dtype == tensors[k].numpy().dtype - np.testing.assert_allclose(v.numpy(), tensors[k].numpy()) - - # pytorch does not support U16, U32, and U64 dtypes. - tensors = { - "weight_U16": np.array([1, 2, 3], dtype=np.uint16), - "weight_U32": np.array([1, 2, 3], dtype=np.uint32), - "weight_U64": np.array([1, 2, 3], dtype=np.uint64), - } - np_save_file(tensors, temp("dtypes.safetensors")) - - loaded = safe_load(temp("dtypes.safetensors")) - for k,v in loaded.items(): - assert v.numpy().dtype == tensors[k].dtype - np.testing.assert_allclose(v.numpy(), tensors[k]) - -def helper_test_disk_tensor(fn, data, np_fxn, tinygrad_fxn=None): - if tinygrad_fxn is None: tinygrad_fxn = np_fxn - pathlib.Path(temp(fn)).unlink(missing_ok=True) - tinygrad_tensor = Tensor(data, device="CPU").to(f"disk:{temp(fn)}") - numpy_arr = np.array(data) - tinygrad_fxn(tinygrad_tensor) - np_fxn(numpy_arr) - np.testing.assert_allclose(tinygrad_tensor.numpy(), numpy_arr) - -class TestDiskTensor(unittest.TestCase): - def test_empty(self): - pathlib.Path(temp("dt_empty")).unlink(missing_ok=True) - Tensor.empty(100, 100, device=f"disk:{temp('dt_empty')}") - - def test_simple_read(self): - fn = pathlib.Path(temp("dt_simple_read")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))) - t = Tensor.empty(16, 16, device=f"disk:{temp('dt_simple_read')}", dtype=dtypes.uint8) - out = t[1].to(Device.DEFAULT).tolist() - assert out == list(range(16, 32)) - - def test_simple_read_bitcast(self): - fn = pathlib.Path(temp("dt_simple_read_bitcast")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))*2) - t = Tensor.empty(16, 16*2, device=f"disk:{temp('dt_simple_read_bitcast')}", dtype=dtypes.uint8) - out = t[1].bitcast(dtypes.uint16).to(Device.DEFAULT).tolist() - tout = [(x//256, x%256) for x in out] - assert tout == list([(x+1,x) for x in range(32,64,2)]) - - def test_simple_read_bitcast_alt(self): - fn = pathlib.Path(temp("dt_simple_read_bitcast_alt")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))*2) - t = Tensor.empty(16, 16*2, device=f"disk:{temp('dt_simple_read_bitcast_alt')}", dtype=dtypes.uint8) - out = t.bitcast(dtypes.uint16)[1].to(Device.DEFAULT).tolist() - tout = [(x//256, x%256) for x in out] - assert tout == list([(x+1,x) for x in range(32,64,2)]) - - def test_write_ones(self): - pathlib.Path(temp("dt_write_ones")).unlink(missing_ok=True) - - out = Tensor.ones(10, 10, device="CPU").contiguous() - outdisk = out.to(f"disk:{temp('dt_write_ones')}") - print(outdisk) - outdisk.realize() - del out, outdisk - - import struct - # test file - with open(temp("dt_write_ones"), "rb") as f: - assert f.read() == struct.pack(' bf16 - with open(temp('dt_bf16_disk_write_read_f32'), "rb") as f: dat = f.read() - adat = b''.join([dat[i+2:i+4] for i in range(0, len(dat), 4)]) - with open(temp('dt_bf16_disk_write_read_bf16'), "wb") as f: f.write(adat) - - t = Tensor.empty(5, dtype=dtypes.bfloat16, device=f"disk:{temp('dt_bf16_disk_write_read_bf16')}") - ct = t.llvm_bf16_cast(dtypes.float) - assert ct.numpy().tolist() == [9984., -1, -1000, -9984, 20] - - def test_copy_from_disk(self): - fn = pathlib.Path(temp("dt_copy_from_disk")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))*1024) - - t = Tensor.empty(256*1024, device=f"disk:{temp('dt_copy_from_disk')}", dtype=dtypes.uint8) - on_dev = t.to(Device.DEFAULT).realize() - np.testing.assert_equal(on_dev.numpy(), t.numpy()) - - def test_copy_from_disk_offset(self): - fn = pathlib.Path(temp("dt_copy_from_disk_offset")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))*1024) - - for off in [314, 991, 2048, 4096]: - t = Tensor.empty(256*1024, device=f"disk:{temp('dt_copy_from_disk_offset')}", dtype=dtypes.uint8)[off:] - on_dev = t.to(Device.DEFAULT).realize() - np.testing.assert_equal(on_dev.numpy(), t.numpy()) - - def test_copy_from_disk_huge(self): - if CI and not hasattr(Device["DISK"], 'io_uring'): self.skipTest("slow on ci without iouring") - - fn = pathlib.Path(temp("dt_copy_from_disk_huge")) - fn.unlink(missing_ok=True) - fn.write_bytes(bytes(range(256))*1024*256) - - for off in [0, 551]: - t = Tensor.empty(256*1024*256, device=f"disk:{temp('dt_copy_from_disk_huge')}", dtype=dtypes.uint8)[off:] - on_dev = t.to(Device.DEFAULT).realize() - np.testing.assert_equal(on_dev.numpy(), t.numpy()) - - @unittest.skip("this allocates a lot of RAM") - @unittest.skipUnless(OSX, "seems to only be an issue on macOS with file size >2 GiB") - def test_copy_to_cpu_not_truncated(self): - with open((fn:=temp("dt_copy_to_cpu_not_truncated")), "wb") as f: f.write(b'\x01' * (size := int(2 * 1024**3)) + (test := b"test")) - x = Tensor.empty(size + len(test), dtype=dtypes.uint8, device=f"disk:{fn}").to("CPU").realize() - assert x[size:].data().tobytes() == test - -class TestPathTensor(unittest.TestCase): - def setUp(self): - self.temp_dir = tempfile.TemporaryDirectory() - self.test_file = pathlib.Path(self.temp_dir.name) / "test_file.bin" - self.test_data = np.arange(100, dtype=np.uint8).tobytes() - with open(self.test_file, "wb") as f: - f.write(self.test_data) - - def tearDown(self): - self.temp_dir.cleanup() - - def test_path_tensor_no_device(self): - t = Tensor(self.test_file) - self.assertEqual(t.shape, (100,)) - self.assertEqual(t.dtype, dtypes.uint8) - self.assertTrue(t.device.startswith("DISK:")) - np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) - - def test_path_tensor_with_device(self): - t = Tensor(self.test_file, device="CPU") - self.assertEqual(t.shape, (100,)) - self.assertEqual(t.dtype, dtypes.uint8) - self.assertEqual(t.device, "CPU") - np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) - - def test_path_tensor_empty_file(self): - empty_file = pathlib.Path(self.temp_dir.name) / "empty_file.bin" - empty_file.touch() - t = Tensor(empty_file) - self.assertEqual(t.shape, (0,)) - self.assertEqual(t.dtype, dtypes.uint8) - self.assertTrue(t.device.startswith("DISK:")) - - def test_path_tensor_non_existent_file(self): - non_existent_file = pathlib.Path(self.temp_dir.name) / "non_existent.bin" - with self.assertRaises(FileNotFoundError): - Tensor(non_existent_file) - - def test_path_tensor_with_dtype(self): - t = Tensor(self.test_file, dtype=dtypes.int16) - self.assertEqual(t.shape, (50,)) - self.assertEqual(t.dtype, dtypes.int16) - self.assertTrue(t.device.startswith("DISK:")) - np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.int16)) - - def test_path_tensor_copy_to_device(self): - t = Tensor(self.test_file) - t_cpu = t.to("CPU") - self.assertEqual(t_cpu.device, "CPU") - np.testing.assert_array_equal(t_cpu.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_elf.py b/tinygrad/test/unit/test_elf.py deleted file mode 100644 index cdf02b77..00000000 --- a/tinygrad/test/unit/test_elf.py +++ /dev/null @@ -1,29 +0,0 @@ -import unittest, subprocess, platform -from tinygrad.runtime.ops_cpu import ClangJITCompiler -from tinygrad.runtime.support.elf import elf_loader - -class TestElfLoader(unittest.TestCase): - def test_load_clang_jit_strtab(self): - src = ''' - int something; // will be a load from a relocation (needed for .rela.text to exist) - int test(int x) { - return something + x; - } - ''' - args = ('-x', 'c', '-c', '-target', f'{platform.machine()}-none-unknown-elf', '-march=native', '-fPIC', '-O2', '-ffreestanding', '-nostdlib') - obj = subprocess.check_output(('clang',) + args + ('-', '-o', '-'), input=src.encode('utf-8')) - _, sections, _ = elf_loader(obj) - section_names = [sh.name for sh in sections] - assert '.text' in section_names and '.rela.text' in section_names, str(section_names) - def test_clang_jit_compiler_external_raise(self): - src = ''' - int evil_external_function(int); - int test(int x) { - return evil_external_function(x+2)*2; - } - ''' - with self.assertRaisesRegex(RuntimeError, 'evil_external_function'): - ClangJITCompiler().compile(src) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_gguf.py b/tinygrad/test/unit/test_gguf.py deleted file mode 100644 index b36ad14f..00000000 --- a/tinygrad/test/unit/test_gguf.py +++ /dev/null @@ -1,107 +0,0 @@ -import os, unittest, ctypes -from tinygrad import dtypes, Tensor, fetch, Device -import numpy as np -from tinygrad.nn.state import ggml_data_to_tensor, gguf_load -from tinygrad.device import is_dtype_supported -try: - import ggml -except ModuleNotFoundError: - raise unittest.SkipTest("ggml not installed, skipping gguf test") - -ggml_test_block_count = 4 -ggml_type_to_np_dtype = { - ggml.GGML_TYPE_F16: np.float16, ggml.GGML_TYPE_F32:np.float32, ggml.GGML_TYPE_F64:np.float64, - ggml.GGML_TYPE_I8:np.int8, ggml.GGML_TYPE_I16: np.int16, ggml.GGML_TYPE_I32: np.int32, ggml.GGML_TYPE_I64: np.int64, -} -np_dtype_to_ctype = { np.float16: ctypes.c_uint16 } -gguf_val_getters = [ - ggml.gguf_get_val_u8, ggml.gguf_get_val_i8, ggml.gguf_get_val_u16, ggml.gguf_get_val_i16, - ggml.gguf_get_val_u32, ggml.gguf_get_val_i32, ggml.gguf_get_val_f32, ggml.gguf_get_val_bool, - lambda *args: ggml.gguf_get_val_str(*args).decode("utf-8"), None, - ggml.gguf_get_val_u64, ggml.gguf_get_val_i64, ggml.gguf_get_val_f64, -] - -def ggml_tensor_to_numpy(tensor: ggml.ggml_tensor_p): - ctx: ggml.ggml_context_p | None = None - ggml_type, n_dims, n_els = tensor.contents.type, ggml.ggml_n_dims(tensor), ggml.ggml_nelements(tensor) - shape = tuple(reversed(tensor.contents.ne[:n_dims])) - if ggml_type not in ggml_type_to_np_dtype: - ctx = ggml.ggml_init(ggml.ggml_init_params(mem_size=n_els * 5 + 500, mem_buffer=None)) - ntensor = ggml.ggml_new_tensor(ctx, ggml.GGML_TYPE_F32, n_dims, tensor.contents.ne) - type_traits = ggml.ggml_internal_get_type_traits(ggml_type) - type_traits.to_float(ggml.ggml_get_data(tensor), ggml.ggml_get_data_f32(ntensor), n_els) - tensor, ggml_type = ntensor, ggml.GGML_TYPE_F32 - - np_type = ggml_type_to_np_dtype[ggml_type] - ctypes_type = np_dtype_to_ctype.get(np_type, None) or np.ctypeslib.as_ctypes_type(np_type) - data = ggml.ggml_get_data(tensor) - if data is None: raise ValueError("tensor data is None") - arr = (ctypes_type * ggml.ggml_nelements(tensor)).from_address(data) - strides = tuple(reversed(tensor.contents.nb[:n_dims])) - output = np.ctypeslib.as_array(arr) - output.dtype = np_type - return np.lib.stride_tricks.as_strided(output, shape=shape, strides=strides), ctx - -@unittest.skipIf(any(not is_dtype_supported(t) for t in [ dtypes.uint8, dtypes.half ]), "Backend must support uint8 and half") -class TestGGUF(unittest.TestCase): - def setUp(self) -> None: - params = ggml.ggml_init_params(mem_size=0, mem_buffer=None, no_alloc=False) - self.ctx = ctypes.cast(ggml.ggml_init(params), ctypes.POINTER(ctypes.c_void_p)) - def tearDown(self) -> None: ggml.ggml_free(self.ctx) - - def test_load_tinyllama_q8_0(self): self._test_gguf_load("https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories15M-q8_0.gguf?download=true") - def test_load_tinyllama_q4_0(self): self._test_gguf_load("https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories15M-q4_0.gguf?download=true") - def test_load_gpt2_q4_1(self): self._test_gguf_load("https://huggingface.co/PrunaAI/gpt2-GGUF-smashed/resolve/main/gpt2.Q4_1.gguf?download=true") - def test_load_sample_q6_k(self): self._test_gguf_load("https://huggingface.co/Isotr0py/test-gguf-sample/resolve/main/Quant_Q6_K_1024.gguf?download=true") - - def test_dequantization_q4_0(self): self._test_dequantization(ggml.GGML_TYPE_Q4_0) - def test_dequantization_q4_1(self): self._test_dequantization(ggml.GGML_TYPE_Q4_1) - def test_dequantization_q8_0(self): self._test_dequantization(ggml.GGML_TYPE_Q8_0) - def test_dequantization_q6_k(self): self._test_dequantization(ggml.GGML_TYPE_Q6_K) - - def test_expected_failure_unknown_type(self): - with self.assertRaises(ValueError): - ggml_data_to_tensor(Tensor.empty(512, dtype=dtypes.uint8), 256, 1337) - - def _test_dequantization(self, ttype: int): - type_traits = ggml.ggml_internal_get_type_traits(ttype) - n_el, n_bytes = ggml_test_block_count * type_traits.blck_size, ggml_test_block_count * type_traits.type_size - - data_in = (np.random.random((n_el,)).astype(np.float32) * 100 - 50).ctypes.data_as(ctypes.POINTER(ctypes.c_float)) - - c_q_data, c_dq_data = (ctypes.c_char * n_bytes)(0), (ctypes.c_float * n_el)(0) - type_traits.from_float(data_in, c_q_data, n_el) - type_traits.to_float(c_q_data, c_dq_data, n_el) - - q_tensor = Tensor(np.frombuffer(c_q_data, dtype=np.uint8, count=n_bytes)) - dq_tensor = ggml_data_to_tensor(q_tensor, n_el, ttype).reshape(n_el) - - np.testing.assert_equal(dq_tensor.numpy(), np.frombuffer(c_dq_data, dtype=np.float32)) - - def _test_gguf_load(self, url: str): - fp = fetch(url) - model_size = os.stat(fp).st_size - gguf_tensor = Tensor.empty(model_size, dtype=dtypes.uint8, device=f"disk:{fp}").to(Device.DEFAULT) - kv_data, tensors = gguf_load(gguf_tensor) - - gguf_params = ggml.gguf_init_params(ctx=self.ctx, no_alloc=False) - gguf_ctx = ggml.gguf_init_from_file(str(fp).encode("utf8"), gguf_params) - param_ctx = gguf_params.ctx.contents.value - - for ggml_tensor_idx in range(ggml.gguf_get_n_tensors(gguf_ctx)): - tensor_name = ggml.gguf_get_tensor_name(gguf_ctx, ggml_tensor_idx) - ggml_tensor = ggml.ggml_get_tensor(param_ctx, tensor_name) - ggml_tensor_numpy, temp_ctx = ggml_tensor_to_numpy(ggml_tensor) - tensor = tensors.get(tensor_name.decode("utf-8")) - np.testing.assert_equal(tensor.numpy(), ggml_tensor_numpy) - if temp_ctx is not None: ggml.ggml_free(temp_ctx) - - for gguf_key_id in range(ggml.gguf_get_n_kv(gguf_ctx)): - v = kv_data[ggml.gguf_get_key(gguf_ctx, gguf_key_id).decode("utf-8")] - v_type = ggml.gguf_get_kv_type(gguf_ctx, gguf_key_id) - if (get_fn := gguf_val_getters[v_type]) is not None: self.assertEqual(get_fn(gguf_ctx, gguf_key_id), v) - - ggml.gguf_free(gguf_ctx) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_gradient.py b/tinygrad/test/unit/test_gradient.py deleted file mode 100644 index 2739fe90..00000000 --- a/tinygrad/test/unit/test_gradient.py +++ /dev/null @@ -1,147 +0,0 @@ -from typing import Callable -import unittest, math -import torch -import numpy as np -from tinygrad import Tensor -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UOp -from tinygrad.gradient import compute_gradient - -class TestGradient(unittest.TestCase): - def _cmp_nan_okay(self, x, y): - if math.isnan(x) and math.isnan(y): return - self.assertAlmostEqual(x, y, places=5) - - def _test_one_input_function(self, f:Callable, jf:Callable|None=None): - if jf is None: jf = f - x = UOp.variable('x', -math.inf, math.inf, dtype=dtypes.float) - gx = compute_gradient(f(x), UOp.const(dtypes.float, 1.0), set([x]))[x] - - for val in [-5., -2.0, 0.0, 2.0, 5.]: - tg_out = gx.substitute({x: x.const_like(val)}).ssimplify() - tx = torch.tensor([val], dtype=torch.float, requires_grad=True) - torch_out = torch.autograd.grad(jf(tx), tx)[0].item() - self._cmp_nan_okay(tg_out, torch_out) - - def _test_two_input_function(self, f:Callable, jf:Callable|None=None): - if jf is None: jf = f - x = UOp.variable('x', -math.inf, math.inf, dtype=dtypes.float) - y = UOp.variable('y', -math.inf, math.inf, dtype=dtypes.float) - grads = compute_gradient(f(x, y), UOp.const(dtypes.float, 1.0), set([x, y])) - gx, gy = grads[x], grads[y] - - for valx in [-5., -2.0, 0.0, 2.0, 5.]: - for valy in [-5., -2.0, 0.0, 2.0, 5.]: - # Substitute the values into the gradient expressions - substitutions = {x: x.const_like(valx), y: y.const_like(valy)} - tg_out_x = gx.substitute(substitutions).ssimplify() - tg_out_y = gy.substitute(substitutions).ssimplify() - - tx = torch.tensor([valx], dtype=torch.float, requires_grad=True) - ty = torch.tensor([valy], dtype=torch.float, requires_grad=True) - torch_grad = torch.autograd.grad(jf(tx, ty), [tx, ty]) - torch_out_x, torch_out_y = [x.item() for x in torch_grad] - - self._cmp_nan_okay(tg_out_x, torch_out_x) - self._cmp_nan_okay(tg_out_y, torch_out_y) - - # unary ops unit - def test_recip(self): self._test_one_input_function(lambda x: 1.0/x) - def test_sin(self): self._test_one_input_function(lambda x: x.sin()) - def test_sqrt(self): self._test_one_input_function(lambda x: x.sqrt()) - def test_log2(self): self._test_one_input_function(lambda x: x.log2()) - def test_exp2(self): self._test_one_input_function(lambda x: x.exp2()) - - # binary ops unit - def test_add(self): self._test_two_input_function(lambda x,y: x+y) - def test_mul(self): self._test_two_input_function(lambda x,y: x*y) - - # chain rule - def test_chain(self): self._test_one_input_function(lambda x: x.sin().sqrt()) - def test_chain_binop(self): self._test_two_input_function(lambda x,y: (x*y)+x*y) - def test_big_add_sin(self): self._test_two_input_function(lambda x,y: x.sin()+3.0/y) - def test_big_chain(self): self._test_two_input_function(lambda x,y: (1.0/x*y)+x*y) - def test_where(self): self._test_two_input_function(lambda x,y: (x 0, - f"Expected +inf for reciprocal(0.0), got {optimized_recip_zero.arg}") - - @unittest.skip("broken") - def test_full_graph_rewrite_modulo_negative_dividend(self): - x_var_uop = UOp.variable('x', -5, -1) - optimized_sink = full_rewrite_to_sink((x_var_uop % 3).sink()) - for x_value in range(-5, 0): - self.assertEqual(x_value % 3, evaluate_uop(optimized_sink.src[0], {'x': x_value})) - - @unittest.skip("broken") - def test_full_graph_rewrite_division_negative_divisor(self): - x_var_uop = UOp.variable('x', 1, 5) - optimized_sink = full_rewrite_to_sink((x_var_uop // -2).sink()) - for x_value in range(1, 6): - self.assertEqual(x_value // -2, evaluate_uop(optimized_sink.src[0], {'x': x_value})) - -class TestGEPAndVectorizeRewrite(unittest.TestCase): - def test_gep_single_element_extraction(self): - # GEP on a vector dtype to extract a single element - base_vector = UOp.const(dtypes.float32.vec(4), (1.0, 2.0, 3.0, 4.0)) - self.assertEqual(apply_rewrite(base_vector.gep(2)).arg, 3.0) - - def test_gep_tuple_extraction(self): - # GEP on a vector dtype to extract multiple elements as a vector - base_vector = UOp.const(dtypes.float32.vec(4), (1.0, 2.0, 3.0, 4.0)) - optimized_uop = apply_rewrite(base_vector.gep((2, 3))) - self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [3.0, 4.0]) - - def test_gep_on_vconst(self): - # GEP on a VCONST to extract a single element - vconst = UOp(Ops.VCONST, dtypes.float32.vec(4), arg=(1.0, 2.0, 3.0, 4.0)) - self.assertEqual(apply_rewrite(vconst.gep(2)).arg, 3.0) - - def test_gep_tuple_on_vconst(self): - # GEP on a VCONST using a tuple to extract multiple elements - vconst = UOp(Ops.VCONST, dtypes.float32.vec(4), arg=(7.0, 8.0, 9.0, 10.0)) - optimized_uop = apply_rewrite(vconst.gep((1, 3))) - self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [8.0, 10.0]) - - def test_gep_gep_simplification(self): - # Nested GEP simplification on a vector dtype - base_vector = UOp.const(dtypes.float32.vec(4), (10.0, 20.0, 30.0, 40.0)) - gep_inner = base_vector.gep(1) # Extract 2nd element (20.0) - self.assertEqual(apply_rewrite(gep_inner.gep(0)).arg, 20.0) - - def test_vectorize_multiple_elements(self): - # Vectorizing multiple elements using GEP - base_vector = UOp.const(dtypes.float32.vec(4), (5.0, 10.0, 15.0, 20.0)) - vectorized_uop = UOp(Ops.VECTORIZE, dtypes.float32.vec(4), src=(base_vector.gep(0), base_vector.gep(1), base_vector.gep(2), base_vector.gep(3))) - optimized_uop = apply_rewrite(vectorized_uop) - self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [5.0, 10.0, 15.0, 20.0]) - - -import inspect -from tinygrad.uop.ops import graph_rewrite, _substitute, track_rewrites -from tinygrad.codegen.symbolic import symbolic_simple - -class TestBottomUpRewrite(unittest.TestCase): - def test_const_folding(self): - a = UOp.const(dtypes.int, 5) - ret = (a*3) + (a*7) - gt = graph_rewrite(ret, symbolic_simple) - ret = graph_rewrite(ret, symbolic_simple, bottom_up=True) - self.assertIs(gt, ret) - -# normally .substitute would be fine, but it's not tracked -@track_rewrites() -def named_substitute(name:str, uop:UOp, rel:dict[UOp, UOp]): return graph_rewrite(uop, _substitute, rel, bottom_up=True) -def substitute(uop:UOp, rel:dict[UOp, UOp]): return named_substitute(inspect.stack()[1].function, uop, rel) - -class TestSubstitute(unittest.TestCase): - # these work because the substituted things don't have parents - def test_simple(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - ret = a + 4 - ret = substitute(ret, {a:b}) - self.assertIs(ret, b+4) - - def test_double(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - c = UOp.variable('c', 0, 10) - ret = (a + 4) + b - ret = substitute(ret, {a:c, b:c}) - self.assertIs(ret, (c + 4) + c) - - def test_diamond(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - ret = (a + 4) + (a + 5) - ret = substitute(ret, {a:b}) - self.assertIs(ret, (b + 4) + (b + 5)) - - # this works because there's nothing above the substituted node - def test_sin(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - ret = a.sin().sin() - ret = substitute(ret, {a.sin():b}) - self.assertIs(ret, b.sin()) - - # broken due to infinite recursion - # NOTE: VIZ hangs and doesn't recover if you click this one - @unittest.skip("recursion error no longer raised") - def test_assert_inf_recurse(self): - a = UOp.variable('a', 0, 10) - n1 = a.sin() - ret = n1 - with self.assertRaises(RecursionError): - ret = substitute(ret, {n1:n1.sqrt()}) - - def test_sin_to_sqrt(self): - a = UOp.variable('a', 0, 10) - n1 = a.sin() - ret = n1.sin() - ret = substitute(ret, {a.sin():a.sqrt()}) - self.assertIs(ret, a.sqrt().sin()) - - def test_double_sin_to_sqrt(self): - a = UOp.variable('a', 0, 10) - n1 = a.sin() - ret = n1.sin() - # NOTE: this would work if it had gone in the opposite order - ret = substitute(ret, {a.sin():a.sqrt(), n1.sin():n1.sqrt()}) - self.assertIs(ret, a.sqrt().sqrt()) - - def test_tagged_replace(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - ret = (a+4).replace(tag=1) - ret = substitute(ret, {a:b}) - # the srcs are rewritten but we keep tag - self.assertIs(ret, (b+4).replace(tag=1)) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_helpers.py b/tinygrad/test/unit/test_helpers.py deleted file mode 100644 index b9c06167..00000000 --- a/tinygrad/test/unit/test_helpers.py +++ /dev/null @@ -1,367 +0,0 @@ -import gzip, unittest -from tinygrad import Variable -from tinygrad.helpers import Context, ContextVar, argfix -from tinygrad.helpers import merge_dicts, strip_parens, prod, round_up, fetch, fully_flatten, from_mv, to_mv, polyN, time_to_str, cdiv, cmod, getbits -from tinygrad.tensor import get_shape -from tinygrad.codegen.lowerer import get_contraction, get_contraction_with_reduce -import numpy as np - -VARIABLE = ContextVar("VARIABLE", 0) - -class TestContextVars(unittest.TestCase): - # Ensuring that the test does not modify variables outside the tests. - ctx = Context() - def setUp(self): TestContextVars.ctx.__enter__() - def tearDown(self): TestContextVars.ctx.__exit__() - - def test_initial_value_is_set(self): - _TMP = ContextVar("_TMP", 5) - self.assertEqual(_TMP.value, 5) - - def test_cannot_recreate(self): - _TMP2 = ContextVar("_TMP2", 1) - with self.assertRaises(RuntimeError): - _TMP2 = ContextVar("_TMP2", 2) - - def test_new_var_inside_context(self): - with Context(VARIABLE=1): - _TMP3 = ContextVar("_TMP3", 1) - with self.assertRaises(RuntimeError): - _TMP3 = ContextVar("_TMP3", 2) - - def test_value_across_modules(self): - # Mocking module import by invoking the code but not in our globals(). - exec('from tinygrad.helpers import ContextVar;C = ContextVar("C", 13)', {}) # pylint:disable=exec-used - # It should not matter that the first creation was in another module. - with self.assertRaises(RuntimeError): - _C = ContextVar("C", 0) - - def test_assignment_across_modules(self): - B = ContextVar("B", 1) - # local assignment - B.value = 2 - self.assertEqual(B.value, 2) - with self.assertRaises(RuntimeError): - # Assignment in another module. - exec('from tinygrad.helpers import ContextVar;B = ContextVar("B", 0);B.value = 3;', {}) # pylint:disable=exec-used - - def test_context_assignment(self): - with Context(VARIABLE=1): - self.assertEqual(VARIABLE.value, 1) - self.assertEqual(VARIABLE.value, 0) - - def test_unknown_param_to_context(self): - with self.assertRaises(KeyError): - with Context(SOMETHING_ELSE=1): - pass - - def test_nested_context(self): - with Context(VARIABLE=1): - with Context(VARIABLE=2): - MORE = ContextVar("MORE", 2) - with Context(VARIABLE=3, MORE=3): - self.assertEqual(VARIABLE.value, 3) - self.assertEqual(MORE.value, 3) - self.assertEqual(VARIABLE.value, 2) - self.assertEqual(MORE.value, 2) - self.assertEqual(VARIABLE.value, 1) - self.assertEqual(MORE.value, 2) # TODO: should this raise? - self.assertEqual(VARIABLE.value, 0) - - def test_decorator(self): - @Context(VARIABLE=1, DEBUG=4) - def test(): - self.assertEqual(VARIABLE.value, 1) - - self.assertEqual(VARIABLE.value, 0) - test() - self.assertEqual(VARIABLE.value, 0) - - def test_context_exit_reverts_updated_values(self): - D = ContextVar("D", 1) - D.value = 2 - with Context(D=3): - ... - assert D.value == 2, f"Expected D to be 2, but was {D.value}. Indicates that Context.__exit__ did not restore to the correct value." - -class TestMergeDicts(unittest.TestCase): - def test_merge_dicts(self): - a = {"a": 1, "b": 2} - b = {"a": 1, "c": 3} - c = {} - d = {"a": 2, "b": 2} - assert merge_dicts([a, b]) == {"a": 1, "b": 2, "c": 3} - assert merge_dicts([a, c]) == a - assert merge_dicts([a, b, c]) == {"a": 1, "b": 2, "c": 3} - with self.assertRaises(AssertionError): - merge_dicts([a, d]) - -class TestStripParens(unittest.TestCase): - def test_simple(self): self.assertEqual("1+2", strip_parens("(1+2)")) - def test_nested(self): self.assertEqual("1+(2+3)", strip_parens("(1+(2+3))")) - def test_casted_no_strip(self): self.assertEqual("(int)(1+2)", strip_parens("(int)(1+2)")) - -class TestProd(unittest.TestCase): - def test_empty(self): self.assertEqual(1, prod(tuple())) - def test_ints(self): self.assertEqual(30, prod((2, 3, 5))) - def test_variable(self): self.assertEqual("(a*12)", prod((Variable("a", 1, 5), 3, 4)).render()) - def test_variable_order(self): self.assertEqual("(a*12)", prod((3, 4, Variable("a", 1, 5))).render()) - -class TestRoundUp(unittest.TestCase): - def test_round_up(self): - self.assertEqual(round_up(-3,4), 0) - self.assertEqual(round_up(-4,4), -4) - self.assertEqual(round_up(6,4), 8) - self.assertEqual(round_up(8,4), 8) - self.assertEqual(round_up(232, 24984), 24984) - self.assertEqual(round_up(24984, 232), 25056) - -@unittest.skip("no fetch tests because they need internet") -class TestFetch(unittest.TestCase): - def test_fetch_bad_http(self): - self.assertRaises(Exception, fetch, 'http://www.google.com/404', allow_caching=False) - - def test_fetch_small(self): - assert (len(fetch('https://google.com', allow_caching=False).read_bytes())>0) - - def test_fetch_img(self): - from PIL import Image - img = fetch("https://avatars.githubusercontent.com/u/132956020", allow_caching=False) - with Image.open(img) as pimg: - assert pimg.size == (77, 77), pimg.size - - def test_fetch_subdir(self): - from PIL import Image - img = fetch("https://avatars.githubusercontent.com/u/132956020", allow_caching=False, subdir="images") - with Image.open(img) as pimg: - assert pimg.size == (77, 77), pimg.size - assert img.parent.name == "images" - - def test_fetch_gunzip_valid(self): - # compare fetch(gunzip=True) to fetch(gunzip=False) plus decompressing afterwards - gzip_url: str = 'https://ftp.gnu.org/gnu/gzip/gzip-1.13.tar.gz' - fp_gz = fetch(gzip_url, gunzip=True) - fp_no_gz = fetch(gzip_url, gunzip=False) - with open(fp_gz, 'rb') as f: content_gz = f.read() - with open(fp_no_gz, 'rb') as f: content_no_gz = gzip.decompress(f.read()) - assert fp_gz.stat().st_size > fp_no_gz.stat().st_size - assert isinstance(content_gz, bytes) and isinstance(content_no_gz, bytes) - assert len(content_gz) == len(content_no_gz) - assert content_gz == content_no_gz - - def test_fetch_gunzip_invalid(self): - # given a non-gzipped file, fetch(gunzip=True) fails - no_gzip_url: str = 'https://ftp.gnu.org/gnu/gzip/gzip-1.13.zip' - with self.assertRaises(gzip.BadGzipFile): - fetch(no_gzip_url, gunzip=True) - - def test_fetch_user_agent(self): - fetch("https://csrc.nist.gov/CSRC/media/Projects/lightweight-cryptography/documents/finalist-round/updated-submissions/sparkle.zip", - allow_caching=False) - -class TestFullyFlatten(unittest.TestCase): - def test_fully_flatten(self): - self.assertEqual(fully_flatten([[1, 3], [1, 2]]), [1, 3, 1, 2]) - self.assertEqual(fully_flatten(((1, 3), (1, 2))), [1, 3, 1, 2]) - self.assertEqual(fully_flatten([[[1], [3]], [[1], [2]]]), [1, 3, 1, 2]) - self.assertEqual(fully_flatten([[[[1], 2], 3], 4]), [1, 2, 3, 4]) - self.assertEqual(fully_flatten([[1, 2, [3, 4]], [5, 6], 7]), [1, 2, 3, 4, 5, 6, 7]) - self.assertEqual(fully_flatten([[1, "ab"], [True, None], [3.14, [5, "b"]]]), [1, "ab", True, None, 3.14, 5, "b"]) - - def test_fully_flatten_numpy(self): - self.assertEqual(fully_flatten([np.array([])]), []) - self.assertEqual(fully_flatten([np.array(3)]), [3]) - self.assertEqual(fully_flatten([np.array([3])]), [3]) - self.assertEqual(fully_flatten([np.array([[3]])]), [3]) - self.assertEqual(fully_flatten([np.array([1, 3]), np.array([1, 2])]), [1, 3, 1, 2]) - self.assertEqual(fully_flatten((np.array([1, 3]), np.array([1, 2]))), [1, 3, 1, 2]) - self.assertEqual(fully_flatten([np.array([[1], [3]]), np.array([[1], [2]])]), [1, 3, 1, 2]) - self.assertEqual(fully_flatten([[1, "ab"], [True, None], np.array([[3.14], [6.28]])]), [1, "ab", True, None, 3.14, 6.28]) - -class TestMemoryview(unittest.TestCase): - def test_from_mv_to_mv(self): - base = memoryview(bytearray(b"\x11\x22\x33"*40)) - ct = from_mv(base) - mv = to_mv(ct, len(base)) - mv[0] = 2 - assert base[0] == 2 - -class TestGetContraction(unittest.TestCase): - def test_contraction_with_reduce(self): - r = get_contraction((16, 1, 1, 1), (16, 1, 1)) - self.assertEqual(r, [[0], [], [1, 2, 3]]) - r = get_contraction_with_reduce((16, 1, 1, 1), (16, 1, 1), (1,)) - self.assertEqual(r, [[0], [1, 2], [3]]) - - r = get_contraction((16, 1, 1, 1, 1), (16, 1, 1, 1)) - self.assertEqual(r, [[0], [], [], [1, 2, 3, 4]]) - r = get_contraction_with_reduce((16, 1, 1, 1, 1), (16, 1, 1, 1), (1,)) - self.assertEqual(r, [[0], [1, 2], [3], [4]]) - - r = get_contraction_with_reduce((2, 512, 1, 1), (2, 1, 512), (1,)) - self.assertIsNone(r) - - def test_contraction(self): - r = get_contraction((1,2,3,4), (2,3,4)) - self.assertEqual(r, [[0, 1], [2], [3]]) - - r = get_contraction((2,1,3,4), (2,3,4)) - self.assertEqual(r, [[0], [1, 2], [3]]) - - r = get_contraction((1,2,3,1,4), (1,2,3,4)) - self.assertEqual(r, [[], [0, 1], [2], [3, 4]]) - - r = get_contraction((1,2,3,1,4,1,1), (2,3,4)) - self.assertEqual(r, [[0, 1], [2], [3, 4, 5, 6]]) - - r = get_contraction((1,2,3,4), (1,2,3*4)) - self.assertEqual(r, [[], [0, 1], [2, 3]]) - - r = get_contraction((1,2,3,4), (2,1,3,4)) - self.assertEqual(r, [[0, 1], [], [2], [3]]) - - r = get_contraction((1,2,3,4), (1,1,2*3*4,1)) - self.assertEqual(r, [[], [], [0,1,2,3], []]) - - r = get_contraction((2,1,3,4), (1,2,3,4)) - self.assertEqual(r, [[], [0], [1, 2], [3]]) - - r = get_contraction((1,2,3,4), (2*3*4,1,1,1)) - self.assertEqual(r, [[0, 1, 2, 3], [], [], []]) - - r = get_contraction((4,4,4,4), (16,1,16)) - self.assertEqual(r, [[0, 1], [], [2, 3]]) - - r = get_contraction((1,2,3,4,1,1,1), (2,3,4)) - self.assertEqual(r, [[0, 1], [2], [3, 4, 5, 6]]) - - r = get_contraction((1,2,3,4), (1,2,3,4,1)) - self.assertEqual(r, [[], [0, 1], [2], [3], []]) - - r = get_contraction((14,1,384,14,1,1,1,1), (1,14,384,14)) - self.assertEqual(r, [[], [0], [1,2], [3,4,5,6,7]]) - - r = get_contraction((14,1,384,1,14,1,1,1,1), (1,14,384,14)) - self.assertEqual(r, [[], [0], [1,2], [3,4,5,6,7,8]]) - - r = get_contraction((512, 512), (1, 1, 512, 1, 1, 1, 1, 512)) - self.assertEqual(r, [[], [], [0], [], [], [], [], [1]]) - - r = get_contraction((1,2,3,4), (1,2,6,2)) - self.assertEqual(r, None) - - def test_contraction_ones(self): - r = get_contraction((1,), (1,1,1)) - self.assertEqual(r, [[], [], [0]]) - - r = get_contraction((1,1), (1,1,1)) - self.assertEqual(r, [[], [], [0, 1]]) - - r = get_contraction((1,1,1,1), (1,)) - self.assertEqual(r, [[0,1,2,3]]) - - r = get_contraction((1,1,1,1), (1,1)) - self.assertEqual(r, [[], [0,1,2,3]]) - - r = get_contraction((1,1,1,1), (1,1,1)) - self.assertEqual(r, [[], [], [0,1,2,3]]) - - r = get_contraction((1,1,1,1), (1,1,1,1)) - self.assertEqual(r, [[], [], [], [0,1,2,3]]) - -class TestGetShape(unittest.TestCase): - def test_get_shape(self): - assert get_shape(2) == () - assert get_shape([]) == (0,) - assert get_shape([[]]) == (1, 0) - assert get_shape([[1, 2]]) == (1, 2) - assert get_shape([[1, 2], (3, 4)]) == (2, 2) - - def test_inhomogeneous_shape(self): - with self.assertRaises(ValueError): get_shape([[], [1]]) - with self.assertRaises(ValueError): get_shape([[1, [2]], [1]]) - -class TestPolyN(unittest.TestCase): - def test_float(self): - np.testing.assert_allclose(polyN(1.0, [1.0, -2.0, 1.0]), 0.0) - np.testing.assert_allclose(polyN(2.0, [1.0, -2.0, 1.0]), 1.0) - np.testing.assert_allclose(polyN(3.0, [1.0, -2.0, 1.0]), 4.0) - np.testing.assert_allclose(polyN(4.0, [1.0, -2.0, 1.0]), 9.0) - - def test_tensor(self): - from tinygrad.tensor import Tensor - np.testing.assert_allclose(polyN(Tensor([1.0, 2.0, 3.0, 4.0]), [1.0, -2.0, 1.0]).numpy(), [0.0, 1.0, 4.0, 9.0]) - - def test_uop(self): - from tinygrad.dtype import dtypes - from tinygrad.uop.ops import UOp - from test.helpers import eval_uop - np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 1.0), [1.0, -2.0, 1.0])), 0.0) - np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 2.0), [1.0, -2.0, 1.0])), 1.0) - np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 3.0), [1.0, -2.0, 1.0])), 4.0) - np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 4.0), [1.0, -2.0, 1.0])), 9.0) - -class TestTimeToStr(unittest.TestCase): - def test_seconds(self): self.assertEqual(" 10.01s ", time_to_str(10.01)) - def test_boundary_sec_ms(self): self.assertEqual("10000.00ms", time_to_str(10)) - def test_milliseconds(self): self.assertEqual(" 500.00ms", time_to_str(0.5)) - def test_boundary_ms_us(self): self.assertEqual("10000.00us", time_to_str(0.01)) - def test_microseconds(self): self.assertEqual(" 100.00us", time_to_str(0.0001)) - def test_zero(self): self.assertEqual(" 0.00us", time_to_str(0)) - def test_width_formatting(self): self.assertEqual(" 10.01s ", time_to_str(10.01, w=6)) - -class TestCStyleDivMod(unittest.TestCase): - def test_div_pos(self): - self.assertEqual(cdiv(-9, 5), -1) - self.assertEqual(cdiv(-4, 5), 0) - self.assertEqual(cdiv(0, 5), 0) - self.assertEqual(cdiv(4, 5), 0) - self.assertEqual(cdiv(9, 5), 1) - def test_div_neg(self): - self.assertEqual(cdiv(-9, -5), 1) - self.assertEqual(cdiv(-4, -5), 0) - self.assertEqual(cdiv(0, -5), 0) - self.assertEqual(cdiv(4, -5), 0) - self.assertEqual(cdiv(9, -5), -1) - def test_mod_pos(self): - self.assertEqual(cmod(-9, 5), -4) - self.assertEqual(cmod(-4, 5), -4) - self.assertEqual(cmod(0, 5), 0) - self.assertEqual(cmod(4, 5), 4) - self.assertEqual(cmod(9, 5), 4) - def test_mod_neg(self): - self.assertEqual(cmod(-9, -5), -4) - self.assertEqual(cmod(-4, -5), -4) - self.assertEqual(cmod(0, -5), 0) - self.assertEqual(cmod(4, -5), 4) - self.assertEqual(cmod(9, -5), 4) - -class TestGetBits(unittest.TestCase): - def test_low_bits(self): - self.assertEqual(getbits(0b11010110, 0, 3), 0b0110) - - def test_high_bits(self): - self.assertEqual(getbits(0b11010110, 4, 7), 0b1101) - - def test_middle_bits(self): - self.assertEqual(getbits(0b11010110, 3, 5), 0b010) - - def test_full_range(self): - self.assertEqual(getbits(0b11010110, 0, 7), 0b11010110) - - def test_single_bit(self): - self.assertEqual(getbits(0b100000000, 8, 8), 1) - -class TestArgFix(unittest.TestCase): - def test_none(self): - self.assertEqual(argfix(None), (None, )) - self.assertEqual(argfix(None, None), (None, None)) - def test_positional_arguments(self): - self.assertEqual(argfix(1, 2, 3), (1, 2, 3)) - def test_tuple(self): - self.assertEqual(argfix((1., 2., 3.)), (1., 2., 3.)) - def test_list(self): - self.assertEqual(argfix([True, False]), (True, False)) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_indexing.py b/tinygrad/test/unit/test_indexing.py deleted file mode 100644 index da5d6194..00000000 --- a/tinygrad/test/unit/test_indexing.py +++ /dev/null @@ -1,1573 +0,0 @@ -# test cases are modified from pytorch test_indexing.py https://github.com/pytorch/pytorch/blob/597d3fb86a2f3b8d6d8ee067e769624dcca31cdb/test/test_indexing.py - -import unittest, random, warnings -import numpy as np - -from tinygrad import Tensor, dtypes, Device, TinyJit -from tinygrad.device import is_dtype_supported -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View -from tinygrad.helpers import CI, all_same, prod - -random.seed(42) - -def numpy_testing_assert_equal_helper(a, b): - if isinstance(a, Tensor): a = a.numpy() - if isinstance(b, Tensor): b = b.numpy() - np.testing.assert_equal(a, b) - -def consec(shape, start=1): - return Tensor.arange(prod(shape)).reshape(shape)+start - -# creates strided tensor with base set to reference tensor's base, equivalent to torch.set_() -def set_(reference: Tensor, shape, strides, offset): - raise NotImplementedError("need to implement without calling uop.view") - if reference.uop.base.realized is None: reference.realize() - assert reference.uop.base.realized, "base has to be realized before setting it to strided's base" - strided = Tensor(reference.uop.view(ShapeTracker((View.create(shape=shape, strides=strides, offset=offset),)))) - assert strided.uop.st.real_strides() == strides, "real_strides should equal strides for strided" - return strided - -def clone(original:Tensor): return original.clone() -def copy_(src:Tensor, other:Tensor) -> Tensor: return src.clone() -# this is fine for tested usecases since as geohotstan understands, -# data_ptr is used to compare if operations needed between tensors is the same -def data_ptr(tensor:Tensor): return tensor.uop - -# https://pytorch.org/docs/stable/generated/torch.Tensor.index_put_.html -def index_put_(tensor:Tensor, indices, values, accumulate) -> Tensor: - if accumulate: tensor[indices] += values - else: tensor[indices] = values - -# https://pytorch.org/docs/stable/generated/torch.argsort.html -def argsort(tensor:Tensor) -> Tensor: - pass - -# https://pytorch.org/docs/stable/generated/torch.all.html -def all_(tensor:Tensor) -> Tensor: - return tensor != 0 - -# https://pytorch.org/docs/stable/generated/torch.diagonal.html -def diagonal(tensor:Tensor) -> Tensor: - assert tensor.ndim == 2 and all_same(tensor.shape), 'only support 2 ndim square tensors' - return (Tensor.eye(tensor.shape[0]) * tensor).sum(0) - -# https://numpy.org/doc/stable/reference/generated/numpy.unravel_index.html -def unravel_index(tensor, shape): - pass - -# https://github.com/pytorch/pytorch/blob/79811e765c23242210ebdc623539d2103a166463/torch/testing/_creation.py#L38 -def make_tensor(shape, dtype:dtypes, noncontiguous) -> Tensor: - r"""Creates a tensor with the given :attr:`shape`, :attr:`device`, and :attr:`dtype`, and filled with - values uniformly drawn from ``[low, high)``. - - If :attr:`low` or :attr:`high` are specified and are outside the range of the :attr:`dtype`'s representable - finite values then they are clamped to the lowest or highest representable finite value, respectively. - If ``None``, then the following table describes the default values for :attr:`low` and :attr:`high`, - which depend on :attr:`dtype`. - - +---------------------------+------------+----------+ - | ``dtype`` | ``low`` | ``high`` | - +===========================+============+==========+ - | boolean type | ``0`` | ``2`` | - +---------------------------+------------+----------+ - | unsigned integral type | ``0`` | ``10`` | - +---------------------------+------------+----------+ - | signed integral types | ``-9`` | ``10`` | - +---------------------------+------------+----------+ - | floating types | ``-9`` | ``9`` | - +---------------------------+------------+----------+ - | complex types | ``-9`` | ``9`` | - +---------------------------+------------+----------+ - """ - contiguous = not noncontiguous - if dtype == dtypes.bool: return Tensor.randint(shape=shape, low=0, high=2, contiguous=contiguous).cast(dtypes.bool) - elif dtype.is_unsigned(): return Tensor.randint(shape=shape, low=0, high=10, contiguous=contiguous).cast(dtype) - elif dtype.is_int(): return Tensor.randint(shape=shape, low=-9, high=10, contiguous=contiguous).cast(dtype) # signed int - elif dtype.is_float(): return Tensor.rand(shape=shape, low=-9, high=9, dtype=dtype, contiguous=contiguous) - else: raise NotImplementedError(f"{dtype} not implemented") - -class TestIndexing(unittest.TestCase): - def test_index(self): - - reference = consec((3, 3, 3)) - - numpy_testing_assert_equal_helper(reference[0], consec((3, 3))) - numpy_testing_assert_equal_helper(reference[1], consec((3, 3), 10)) - numpy_testing_assert_equal_helper(reference[2], consec((3, 3), 19)) - numpy_testing_assert_equal_helper(reference[0, 1], consec((3,), 4)) - numpy_testing_assert_equal_helper(reference[0:2], consec((2, 3, 3))) - numpy_testing_assert_equal_helper(reference[2, 2, 2], 27) - numpy_testing_assert_equal_helper(reference[:], consec((3, 3, 3))) - - # indexing with Ellipsis - numpy_testing_assert_equal_helper(reference[..., 2], np.array([[3., 6., 9.],[12., 15., 18.],[21., 24., 27.]])) - numpy_testing_assert_equal_helper(reference[0, ..., 2], np.array([3., 6., 9.])) - numpy_testing_assert_equal_helper(reference[..., 2], reference[:, :, 2]) - numpy_testing_assert_equal_helper(reference[0, ..., 2], reference[0, :, 2]) - numpy_testing_assert_equal_helper(reference[0, 2, ...], reference[0, 2]) - numpy_testing_assert_equal_helper(reference[..., 2, 2, 2], 27) - numpy_testing_assert_equal_helper(reference[2, ..., 2, 2], 27) - numpy_testing_assert_equal_helper(reference[2, 2, ..., 2], 27) - numpy_testing_assert_equal_helper(reference[2, 2, 2, ...], 27) - numpy_testing_assert_equal_helper(reference[...], reference) - - reference_5d = consec((3, 3, 3, 3, 3)) - numpy_testing_assert_equal_helper(reference_5d[..., 1, 0], reference_5d[:, :, :, 1, 0]) - numpy_testing_assert_equal_helper(reference_5d[2, ..., 1, 0], reference_5d[2, :, :, 1, 0]) - numpy_testing_assert_equal_helper(reference_5d[2, 1, 0, ..., 1], reference_5d[2, 1, 0, :, 1]) - numpy_testing_assert_equal_helper(reference_5d[...], reference_5d) - - # None indexing - numpy_testing_assert_equal_helper(reference[2, None], reference[2].unsqueeze(0)) - numpy_testing_assert_equal_helper(reference[2, None, None], reference[2].unsqueeze(0).unsqueeze(0)) - numpy_testing_assert_equal_helper(reference[2:4, None], reference[2:4].unsqueeze(1)) - numpy_testing_assert_equal_helper(reference[None, 2, None, None], reference.unsqueeze(0)[:, 2].unsqueeze(0).unsqueeze(0)) - numpy_testing_assert_equal_helper(reference[None, 2:5, None, None], reference.unsqueeze(0)[:, 2:5].unsqueeze(2).unsqueeze(2)) - - # indexing 0-length slice - numpy_testing_assert_equal_helper(np.empty((0, 3, 3)), reference[slice(0)]) - numpy_testing_assert_equal_helper(np.empty((0, 3)), reference[slice(0), 2]) - numpy_testing_assert_equal_helper(np.empty((0, 3)), reference[2, slice(0)]) - numpy_testing_assert_equal_helper(np.empty([]), reference[2, 1:1, 2]) - - # indexing with step - reference = consec((10, 10, 10)) - numpy_testing_assert_equal_helper(reference[1:5:2], Tensor.stack(reference[1], reference[3], dim=0)) - numpy_testing_assert_equal_helper(reference[1:6:2], Tensor.stack(reference[1], reference[3], reference[5], dim=0)) - numpy_testing_assert_equal_helper(reference[1:9:4], Tensor.stack(reference[1], reference[5], dim=0)) - numpy_testing_assert_equal_helper(reference[2:4, 1:5:2], Tensor.stack(reference[2:4, 1], reference[2:4, 3], dim=1)) - numpy_testing_assert_equal_helper(reference[3, 1:6:2], Tensor.stack(reference[3, 1], reference[3, 3], reference[3, 5], dim=0)) - numpy_testing_assert_equal_helper(reference[None, 2, 1:9:4], Tensor.stack(reference[2, 1], reference[2, 5], dim=0).unsqueeze(0)) - numpy_testing_assert_equal_helper(reference[:, 2, 1:6:2], Tensor.stack(reference[:, 2, 1], reference[:, 2, 3], reference[:, 2, 5], dim=1)) - - lst = [list(range(i, i+10)) for i in range(0, 100, 10)] - tensor = Tensor(lst) - for _ in range(100): - idx1_start = random.randrange(10) - idx1_end = idx1_start + random.randrange(1, 10 - idx1_start + 1) - idx1_step = random.randrange(1, 8) - idx1 = slice(idx1_start, idx1_end, idx1_step) - if random.randrange(2) == 0: - idx2_start = random.randrange(10) - idx2_end = idx2_start + random.randrange(1, 10 - idx2_start + 1) - idx2_step = random.randrange(1, 8) - idx2 = slice(idx2_start, idx2_end, idx2_step) - lst_indexed = [l[idx2] for l in lst[idx1]] - tensor_indexed = tensor[idx1, idx2] - else: - lst_indexed = lst[idx1] - tensor_indexed = tensor[idx1] - numpy_testing_assert_equal_helper(tensor_indexed, np.array(lst_indexed)) - - self.assertRaises(ValueError, lambda: reference[1:9:0]) - # NOTE torch doesn't support this but numpy does so we should too. Torch raises ValueError - # see test_slice_negative_strides in test_ops.py - # self.assertRaises(ValueError, lambda: reference[1:9:-1]) - - self.assertRaises(IndexError, lambda: reference[1, 1, 1, 1]) - self.assertRaises(IndexError, lambda: reference[1, 1, 1, 1:1]) - self.assertRaises(IndexError, lambda: reference[3, 3, 3, 3, 3, 3, 3, 3]) - - self.assertRaises(IndexError, lambda: reference[0.0]) - self.assertRaises(TypeError, lambda: reference[0.0:2.0]) - self.assertRaises(IndexError, lambda: reference[0.0, 0.0:2.0]) - self.assertRaises(IndexError, lambda: reference[0.0, :, 0.0:2.0]) - self.assertRaises(IndexError, lambda: reference[0.0, ..., 0.0:2.0]) - self.assertRaises(IndexError, lambda: reference[0.0, :, 0.0]) - - # TODO: delitem - # def delitem(): del reference[0] - # self.assertRaises(TypeError, delitem) - - # TODO: LLVM is quite fast, why are other compiled backends slow? - @unittest.skipIf(CI and Device.DEFAULT in ["CPU", "GPU", "METAL", "NV", "AMD"], "slow") - def test_advancedindex(self): - # integer array indexing - - # pick a random valid indexer type - def ri(indices): - choice = random.randint(0, 2) - if choice == 0: return Tensor(indices) - if choice == 1: return list(indices) - return tuple(indices) - - def validate_indexing(x): - numpy_testing_assert_equal_helper(x[[0]], consec((1,))) - numpy_testing_assert_equal_helper(x[ri([0]),], consec((1,))) - numpy_testing_assert_equal_helper(x[ri([3]),], consec((1,), 4)) - numpy_testing_assert_equal_helper(x[[2, 3, 4]], consec((3,), 3)) - numpy_testing_assert_equal_helper(x[ri([2, 3, 4]),], consec((3,), 3)) - numpy_testing_assert_equal_helper(x[ri([0, 2, 4]),], np.array([1, 3, 5])) - - def validate_setting(x): - x[[0]] = -2 - numpy_testing_assert_equal_helper(x[[0]], np.array([-2])) - x[[0]] = -1 - numpy_testing_assert_equal_helper(x[ri([0]), ], np.array([-1])) - x[[2, 3, 4]] = 4 - numpy_testing_assert_equal_helper(x[[2, 3, 4]], np.array([4, 4, 4])) - x[ri([2, 3, 4]), ] = 3 - numpy_testing_assert_equal_helper(x[ri([2, 3, 4]), ], np.array([3, 3, 3])) - x[ri([0, 2, 4]), ] = Tensor([5, 4, 3]) - numpy_testing_assert_equal_helper(x[ri([0, 2, 4]), ], np.array([5, 4, 3])) - - # Case 1: Purely Integer Array Indexing - reference = consec((10,)) - validate_indexing(reference) - # setting values - validate_setting(reference) - - # Tensor with stride != 1 - # strided is [1, 3, 5, 7] - - # # TODO: set stride - # reference = consec((10,)) - # strided = set_(reference, (4,), (2,), 0) - - # numpy_testing_assert_equal_helper(strided[[0]], np.array([1])) - # numpy_testing_assert_equal_helper(strided[ri([0]), ], np.array([1])) - # numpy_testing_assert_equal_helper(strided[ri([3]), ], np.array([7])) - # numpy_testing_assert_equal_helper(strided[[1, 2]], np.array([3, 5])) - # numpy_testing_assert_equal_helper(strided[ri([1, 2]), ], np.array([3, 5])) - # numpy_testing_assert_equal_helper(strided[ri([[2, 1], [0, 3]]), ], - # np.array([[5, 3], [1, 7]])) - - # stride is [4, 8] - - # strided = set_(reference, (2,), (4,), offset=4) - - # numpy_testing_assert_equal_helper(strided[[0]], np.array([5])) - # numpy_testing_assert_equal_helper(strided[ri([0]), ], np.array([5])) - # numpy_testing_assert_equal_helper(strided[ri([1]), ], np.array([9])) - # numpy_testing_assert_equal_helper(strided[[0, 1]], np.array([5, 9])) - # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ], np.array([5, 9])) - # numpy_testing_assert_equal_helper(strided[ri([[0, 1], [1, 0]]), ], - # np.array([[5, 9], [9, 5]])) - - # reference is 1 2 - # 3 4 - # 5 6 - reference = consec((3, 2)) - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], np.array([1, 3, 5])) - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([1])], np.array([2, 4, 6])) - numpy_testing_assert_equal_helper(reference[ri([0]), ri([0])], consec((1,))) - numpy_testing_assert_equal_helper(reference[ri([2]), ri([1])], consec((1,), 6)) - numpy_testing_assert_equal_helper(reference[[ri([0, 0]), ri([0, 1])]], np.array([1, 2])) - numpy_testing_assert_equal_helper(reference[[ri([0, 1, 1, 0, 2]), ri([1])]], np.array([2, 4, 4, 2, 6])) - numpy_testing_assert_equal_helper(reference[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([1, 2, 3, 3])) - - rows = ri([[0, 0], - [1, 2]]) - columns = [0], - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[1, 1], - [3, 5]])) - - rows = ri([[0, 0], - [1, 2]]) - columns = ri([1, 0]) - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[2, 1], - [4, 5]])) - rows = ri([[0, 0], - [1, 2]]) - columns = ri([[0, 1], - [1, 0]]) - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[1, 2], - [4, 5]])) - - # setting values - reference[ri([0]), ri([1])] = -1 - numpy_testing_assert_equal_helper(reference[ri([0]), ri([1])], np.array([-1])) - reference[ri([0, 1, 2]), ri([0])] = Tensor([-1, 2, -4]) - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], - np.array([-1, 2, -4])) - reference[rows, columns] = Tensor([[4, 6], [2, 3]]) - numpy_testing_assert_equal_helper(reference[rows, columns], - np.array([[4, 6], [2, 3]])) - - # Verify still works with Transposed (i.e. non-contiguous) Tensors - reference = Tensor([[0, 1, 2, 3], - [4, 5, 6, 7], - [8, 9, 10, 11]]).T - - # Transposed: [[0, 4, 8], - # [1, 5, 9], - # [2, 6, 10], - # [3, 7, 11]] - - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], np.array([0, 1, 2])) - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([1])], np.array([4, 5, 6])) - numpy_testing_assert_equal_helper(reference[ri([0]), ri([0])], np.array([0])) - numpy_testing_assert_equal_helper(reference[ri([2]), ri([1])], np.array([6])) - numpy_testing_assert_equal_helper(reference[[ri([0, 0]), ri([0, 1])]], np.array([0, 4])) - numpy_testing_assert_equal_helper(reference[[ri([0, 1, 1, 0, 3]), ri([1])]], np.array([4, 5, 5, 4, 7])) - numpy_testing_assert_equal_helper(reference[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([0, 4, 1, 1])) - - rows = ri([[0, 0], - [1, 2]]) - columns = [0], - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[0, 0], [1, 2]])) - - rows = ri([[0, 0], - [1, 2]]) - columns = ri([1, 0]) - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[4, 0], [5, 2]])) - rows = ri([[0, 0], - [1, 3]]) - columns = ri([[0, 1], - [1, 2]]) - numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[0, 4], [5, 11]])) - - # TODO: non contiguous setitem - ''' - # setting values - reference[ri([0]), ri([1])] = -1 - numpy_testing_assert_equal_helper(reference[ri([0]), ri([1])], - np.array([-1])) - reference[ri([0, 1, 2]), ri([0])] = np.array([-1, 2, -4]) - numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], - np.array([-1, 2, -4])) - reference[rows, columns] = np.array([[4, 6], [2, 3]]) - numpy_testing_assert_equal_helper(reference[rows, columns], - np.array([[4, 6], [2, 3]])) - ''' - - # stride != 1 - - # strided is [[1 3 5 7], - # [9 11 13 15]] - - # # TODO: set stride - # reference = Tensor.arange(0., 24).reshape(3, 8) - # strided = set_(reference, (2,4), (8,2), 1) - - # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([0])], np.array([1, 9])) - # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1])], np.array([3, 11])) - # numpy_testing_assert_equal_helper(strided[ri([0]), ri([0])], np.array([1])) - # numpy_testing_assert_equal_helper(strided[ri([1]), ri([3])], np.array([15])) - # numpy_testing_assert_equal_helper(strided[[ri([0, 0]), ri([0, 3])]], np.array([1, 7])) - # numpy_testing_assert_equal_helper(strided[[ri([1]), ri([0, 1, 1, 0, 3])]], np.array([9, 11, 11, 9, 15])) - # numpy_testing_assert_equal_helper(strided[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([1, 3, 9, 9])) - - # rows = ri([[0, 0], - # [1, 1]]) - # columns = [0], - # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[1, 1], [9, 9]])) - - # rows = ri([[0, 1], - # [1, 0]]) - # columns = ri([1, 2]) - # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[3, 13], [11, 5]])) - # rows = ri([[0, 0], - # [1, 1]]) - # columns = ri([[0, 1], - # [1, 2]]) - # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[1, 3], [11, 13]])) - - # setting values - - # strided is [[10, 11], - # [17, 18]] - - # # TODO: set stride - # reference = Tensor.arange(0., 24).reshape(3, 8) - # strided = set_(reference, (2,2), (7,1), 10) - - # numpy_testing_assert_equal_helper(strided[ri([0]), ri([1])], np.array([11])) - - # TODO non contiguous setitem - ''' - strided[ri([0]), ri([1])] = -1 - numpy_testing_assert_equal_helper(strided[ri([0]), ri([1])], - Tensor([-1])) - ''' - # # TODO: set stride - # reference = Tensor.arange(0., 24).reshape(3, 8) - # strided = set_(reference, (2,2), (7,1), 10) - - # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1, 0])], np.array([11, 17])) - - # TODO non contiguous setitem - ''' - strided[ri([0, 1]), ri([1, 0])] = Tensor([-1, 2]) - numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1, 0])], - Tensor([-1, 2])) - ''' - - # # TODO: set stride - # reference = Tensor.arange(0., 24).realize().reshape(3, 8) - # strided = set_(reference, (2,2), (7,1), 10) - - # rows = ri([[0], - # [1]]) - # columns = ri([[0, 1], - # [0, 1]]) - # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[10, 11], [17, 18]])) - - # TODO non contiguous setitem - ''' - strided[rows, columns] = Tensor([[4, 6], [2, 3]]) - numpy_testing_assert_equal_helper(strided[rows, columns], - Tensor([[4, 6], [2, 3]])) - ''' - - # Tests using less than the number of dims, and ellipsis - - # reference is 1 2 - # 3 4 - # 5 6 - reference = consec((3, 2)) - numpy_testing_assert_equal_helper(reference[ri([0, 2]),], np.array([[1, 2], [5, 6]])) - numpy_testing_assert_equal_helper(reference[ri([1]), ...], np.array([[3, 4]])) - numpy_testing_assert_equal_helper(reference[..., ri([1])], np.array([[2], [4], [6]])) - - # verify too many indices fails - with self.assertRaises(IndexError): reference[ri([1]), ri([0, 2]), ri([3])] - - # test invalid index fails - reference = Tensor.empty(10) - for err_idx in (10, -11): - with self.assertRaises(IndexError): - reference[err_idx] - # NOTE cannot check for out of bounds with Tensor indexing - # see tensor.py: __getitem__ (Tiny Things) - ''' - with self.assertRaises(IndexError): - reference[Tensor([err_idx], dtype=dtypes.int64)] - with self.assertRaises(IndexError): - reference[[err_idx]] - ''' - - def tensor_indices_to_np(tensor: Tensor, indices): - npt = tensor.numpy() - idxs = tuple(i.numpy().tolist() if isinstance(i, Tensor) and i.dtype == dtypes.int64 else - i for i in indices) - return npt, idxs - - def get_numpy(tensor, indices): - npt, idxs = tensor_indices_to_np(tensor, indices) - return Tensor(npt[idxs]) - - def set_numpy(tensor:Tensor, indices, value): - if not isinstance(value, int): - value = value.numpy() - npt, idxs = tensor_indices_to_np(tensor, indices) - npt[idxs] = value - return npt - - def assert_get_eq(tensor, indexer): - numpy_testing_assert_equal_helper(tensor[indexer], get_numpy(tensor, indexer)) - - def assert_set_eq(tensor: Tensor, indexer, val): - pyt = clone(tensor) - numt = clone(tensor) - pyt[indexer] = val - numt = set_numpy(numt, indexer, val) - numpy_testing_assert_equal_helper(pyt, numt) - - # NOTE: torch initiates the gradients using g0cpu (rand as gradients) - def assert_backward_eq(tensor: Tensor, indexer): - cpu = clone(tensor.float()) - cpu.requires_grad = True - outcpu = cpu[indexer].sum() - outcpu.backward() - dev = cpu.detach() - dev.requires_grad = True - outdev = dev[indexer].sum() - outdev.backward() - numpy_testing_assert_equal_helper(cpu.grad, dev.grad) - - def get_set_tensor(indexed: Tensor, indexer): - set_size = indexed[indexer].shape - set_count = indexed[indexer].numel() - set_tensor = Tensor.randint(set_count, high=set_count).reshape(set_size) #.cast(dtypes.float64) - return set_tensor - - # Tensor is 0 1 2 3 4 - # 5 6 7 8 9 - # 10 11 12 13 14 - # 15 16 17 18 19 - reference = Tensor.arange(0., 20).reshape(4, 5) - - indices_to_test = [ - # grab the second, fourth columns - [slice(None), [1, 3]], - - # first, third rows, - [[0, 2], slice(None)], - - # weird shape - [slice(None), [[0, 1], - [2, 3]]], - # negatives - [[-1], [0]], - [[0, 2], [-1]], - [slice(None), [-1]], - ] - - # only test dupes on gets - get_indices_to_test = indices_to_test + [[slice(None), [0, 1, 1, 2, 2]]] - - for indexer in get_indices_to_test: - assert_get_eq(reference, indexer) - assert_backward_eq(reference, indexer) - - for indexer in indices_to_test: - assert_set_eq(reference, indexer, 44) - assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) - - reference = Tensor.arange(0., 160).reshape(4, 8, 5) - - indices_to_test = [ - [slice(None), slice(None), [0, 3, 4]], - [slice(None), [2, 4, 5, 7], slice(None)], - [[2, 3], slice(None), slice(None)], - [slice(None), [0, 2, 3], [1, 3, 4]], - [slice(None), [0], [1, 2, 4]], - [slice(None), [0, 1, 3], [4]], - [slice(None), [[0, 1], [1, 0]], [[2, 3]]], - [slice(None), [[0, 1], [2, 3]], [[0]]], - [slice(None), [[5, 6]], [[0, 3], [4, 4]]], - [[0, 2, 3], [1, 3, 4], slice(None)], - [[0], [1, 2, 4], slice(None)], - [[0, 1, 3], [4], slice(None)], - [[[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None)], - [[[0, 1], [1, 0]], [[2, 3]], slice(None)], - [[[0, 1], [2, 3]], [[0]], slice(None)], - [[[2, 1]], [[0, 3], [4, 4]], slice(None)], - [[[2]], [[0, 3], [4, 1]], slice(None)], - # non-contiguous indexing subspace - [[0, 2, 3], slice(None), [1, 3, 4]], - - # less dim, ellipsis - [[0, 2], ], - [[0, 2], slice(None)], - [[0, 2], Ellipsis], - [[0, 2], slice(None), Ellipsis], - [[0, 2], Ellipsis, slice(None)], - [[0, 2], [1, 3]], - [[0, 2], [1, 3], Ellipsis], - [Ellipsis, [1, 3], [2, 3]], - [Ellipsis, [2, 3, 4]], - [Ellipsis, slice(None), [2, 3, 4]], - [slice(None), Ellipsis, [2, 3, 4]], - - # ellipsis counts for nothing - [Ellipsis, slice(None), slice(None), [0, 3, 4]], - [slice(None), Ellipsis, slice(None), [0, 3, 4]], - [slice(None), slice(None), Ellipsis, [0, 3, 4]], - [slice(None), slice(None), [0, 3, 4], Ellipsis], - [Ellipsis, [[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None)], - [[[0, 1], [1, 0]], [[2, 1], [3, 5]], Ellipsis, slice(None)], - [[[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None), Ellipsis], - ] - - for indexer in indices_to_test: - assert_get_eq(reference, indexer) - - assert_set_eq(reference, indexer, 212) - assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) - assert_backward_eq(reference, indexer) - - reference = Tensor.arange(0., 1296).reshape(3, 9, 8, 6) - - indices_to_test = [ - [slice(None), slice(None), slice(None), [0, 3, 4]], - [slice(None), slice(None), [2, 4, 5, 7], slice(None)], - [slice(None), [2, 3], slice(None), slice(None)], - [[1, 2], slice(None), slice(None), slice(None)], - [slice(None), slice(None), [0, 2, 3], [1, 3, 4]], - [slice(None), slice(None), [0], [1, 2, 4]], - [slice(None), slice(None), [0, 1, 3], [4]], - [slice(None), slice(None), [[0, 1], [1, 0]], [[2, 3]]], - [slice(None), slice(None), [[0, 1], [2, 3]], [[0]]], - [slice(None), slice(None), [[5, 6]], [[0, 3], [4, 4]]], - [slice(None), [0, 2, 3], [1, 3, 4], slice(None)], - [slice(None), [0], [1, 2, 4], slice(None)], - [slice(None), [0, 1, 3], [4], slice(None)], - [slice(None), [[0, 1], [3, 4]], [[2, 3], [0, 1]], slice(None)], - [slice(None), [[0, 1], [3, 4]], [[2, 3]], slice(None)], - [slice(None), [[0, 1], [3, 2]], [[0]], slice(None)], - [slice(None), [[2, 1]], [[0, 3], [6, 4]], slice(None)], - [slice(None), [[2]], [[0, 3], [4, 2]], slice(None)], - [[0, 1, 2], [1, 3, 4], slice(None), slice(None)], - [[0], [1, 2, 4], slice(None), slice(None)], - [[0, 1, 2], [4], slice(None), slice(None)], - [[[0, 1], [0, 2]], [[2, 4], [1, 5]], slice(None), slice(None)], - [[[0, 1], [1, 2]], [[2, 0]], slice(None), slice(None)], - [[[2, 2]], [[0, 3], [4, 5]], slice(None), slice(None)], - [[[2]], [[0, 3], [4, 5]], slice(None), slice(None)], - [slice(None), [3, 4, 6], [0, 2, 3], [1, 3, 4]], - [slice(None), [2, 3, 4], [1, 3, 4], [4]], - [slice(None), [0, 1, 3], [4], [1, 3, 4]], - [slice(None), [6], [0, 2, 3], [1, 3, 4]], - [slice(None), [2, 3, 5], [3], [4]], - [slice(None), [0], [4], [1, 3, 4]], - [slice(None), [6], [0, 2, 3], [1]], - [slice(None), [[0, 3], [3, 6]], [[0, 1], [1, 3]], [[5, 3], [1, 2]]], - [[2, 2, 1], [0, 2, 3], [1, 3, 4], slice(None)], - [[2, 0, 1], [1, 2, 3], [4], slice(None)], - [[0, 1, 2], [4], [1, 3, 4], slice(None)], - [[0], [0, 2, 3], [1, 3, 4], slice(None)], - [[0, 2, 1], [3], [4], slice(None)], - [[0], [4], [1, 3, 4], slice(None)], - [[1], [0, 2, 3], [1], slice(None)], - [[[1, 2], [1, 2]], [[0, 1], [2, 3]], [[2, 3], [3, 5]], slice(None)], - - # less dim, ellipsis - [Ellipsis, [0, 3, 4]], - [Ellipsis, slice(None), [0, 3, 4]], - [Ellipsis, slice(None), slice(None), [0, 3, 4]], - [slice(None), Ellipsis, [0, 3, 4]], - [slice(None), slice(None), Ellipsis, [0, 3, 4]], - [slice(None), [0, 2, 3], [1, 3, 4]], - [slice(None), [0, 2, 3], [1, 3, 4], Ellipsis], - [Ellipsis, [0, 2, 3], [1, 3, 4], slice(None)], - [[0], [1, 2, 4]], - [[0], [1, 2, 4], slice(None)], - [[0], [1, 2, 4], Ellipsis], - [[0], [1, 2, 4], Ellipsis, slice(None)], - [[1], ], - [[0, 2, 1], [3], [4]], - [[0, 2, 1], [3], [4], slice(None)], - [[0, 2, 1], [3], [4], Ellipsis], - [Ellipsis, [0, 2, 1], [3], [4]], - ] - - for indexer in indices_to_test: - assert_get_eq(reference, indexer) - assert_set_eq(reference, indexer, 1333) - assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) - - indices_to_test += [ - [slice(None), slice(None), [[0, 1], [1, 0]], [[2, 3], [3, 0]]], - [slice(None), slice(None), [[2]], [[0, 3], [4, 4]]], - ] - for indexer in indices_to_test: - assert_get_eq(reference, indexer) - assert_set_eq(reference, indexer, 1333) - assert_backward_eq(reference, indexer) - - # TODO setitem backward - ''' - def test_set_item_to_scalar_tensor(self): - m = random.randint(1, 10) - n = random.randint(1, 10) - z = Tensor.randn([m, n]) - a = 1.0 - w = Tensor(a, requires_grad=True) - z[:, 0] = w - z.sum().backward() - numpy_testing_assert_equal_helper(w.grad, m * a) - ''' - - def test_single_int(self): - v = Tensor.randn(5, 7, 3) - numpy_testing_assert_equal_helper(v[4].shape, (7, 3)) - - def test_multiple_int(self): - v = Tensor.randn(5, 7, 3) - numpy_testing_assert_equal_helper(v[4].shape, (7, 3)) - numpy_testing_assert_equal_helper(v[4, :, 1].shape, (7,)) - - def test_none(self): - v = Tensor.randn(5, 7, 3) - numpy_testing_assert_equal_helper(v[None].shape, (1, 5, 7, 3)) - numpy_testing_assert_equal_helper(v[:, None].shape, (5, 1, 7, 3)) - numpy_testing_assert_equal_helper(v[:, None, None].shape, (5, 1, 1, 7, 3)) - numpy_testing_assert_equal_helper(v[..., None].shape, (5, 7, 3, 1)) - - def test_step(self): - v = Tensor.arange(10) - numpy_testing_assert_equal_helper(v[::1], v) - numpy_testing_assert_equal_helper(v[::2], [0, 2, 4, 6, 8]) - numpy_testing_assert_equal_helper(v[::3], [0, 3, 6, 9]) - numpy_testing_assert_equal_helper(v[::11], [0]) - numpy_testing_assert_equal_helper(v[1:6:2], [1, 3, 5]) - - def test_step_assignment(self): - v = Tensor.zeros(4, 4).contiguous() - v[0, 1::2] = Tensor([3., 4.]) - numpy_testing_assert_equal_helper(v[0].numpy().tolist(), [0, 3, 0, 4]) - numpy_testing_assert_equal_helper(v[1:].sum(), 0) - - @unittest.skip("bool indexing not supported") - def test_bool_indices(self): - v = Tensor.randn(5, 7, 3) - boolIndices = Tensor([True, False, True, True, False], dtype=dtypes.bool) - numpy_testing_assert_equal_helper(v[boolIndices].shape, (3, 7, 3)) - numpy_testing_assert_equal_helper(v[boolIndices], Tensor.stack([v[0], v[2], v[3]])) - - v = Tensor([True, False, True], dtype=dtypes.bool) - boolIndices = Tensor([True, False, False], dtype=dtypes.bool) - uint8Indices = Tensor([1, 0, 0], dtype=dtypes.uint8) - with warnings.catch_warnings(record=True) as w: - numpy_testing_assert_equal_helper(v[boolIndices].shape, v[uint8Indices].shape) - numpy_testing_assert_equal_helper(v[boolIndices], v[uint8Indices]) - numpy_testing_assert_equal_helper(v[boolIndices], Tensor([True])) - numpy_testing_assert_equal_helper(len(w), 2) - - @unittest.skip("bool indexing not supported") - def test_bool_indices_accumulate(self): - mask = Tensor.zeros(size=(10, ), dtype=dtypes.bool) - y = Tensor.ones(size=(10, 10)) - index_put_(y, (mask, ), y[mask], accumulate=True) - numpy_testing_assert_equal_helper(y, Tensor.ones(size=(10, 10))) - - @unittest.skip("bool indexing not supported") - def test_multiple_bool_indices(self): - v = Tensor.randn(5, 7, 3) - # note: these broadcast together and are transposed to the first dim - mask1 = Tensor([1, 0, 1, 1, 0], dtype=dtypes.bool) - mask2 = Tensor([1, 1, 1], dtype=dtypes.bool) - numpy_testing_assert_equal_helper(v[mask1, :, mask2].shape, (3, 7)) - - @unittest.skip("bool indexing not supported") - def test_byte_mask(self): - v = Tensor.randn(5, 7, 3) - mask = Tensor([1, 0, 1, 1, 0], dtype=dtypes.uint8) - with warnings.catch_warnings(record=True) as w: - numpy_testing_assert_equal_helper(v[mask].shape, (3, 7, 3)) - numpy_testing_assert_equal_helper(v[mask], Tensor.stack([v[0], v[2], v[3]])) - numpy_testing_assert_equal_helper(len(w), 2) - - v = Tensor([1.]) - numpy_testing_assert_equal_helper(v[v == 0], Tensor([])) - - @unittest.skip("bool indexing not supported") - def test_byte_mask_accumulate(self): - mask = Tensor.zeros(size=(10, ), dtype=dtypes.uint8) - y = Tensor.ones(size=(10, 10)) - with warnings.catch_warnings(record=True) as w: - warnings.simplefilter("always") - index_put_(y, (mask, ), y[mask], accumulate=True) - numpy_testing_assert_equal_helper(y, Tensor.ones(size=(10, 10))) - numpy_testing_assert_equal_helper(len(w), 2) - - # TODO setitem - # NOTE: tinygrad doesn't support idx.max that big - ''' - def test_index_put_accumulate_large_tensor(self): - # This test is for tensors with number of elements >= INT_MAX (2^31 - 1). - N = (1 << 31) + 5 - dt = dtypes.int8 - a = Tensor.ones(N, dtype=dt).contiguous() - indices = Tensor([-2, 0, -2, -1, 0, -1, 1], dtype=dtypes.int64) - values = Tensor([6, 5, 6, 6, 5, 7, 11], dtype=dt) - - index_put_(a, (indices, ), values, accumulate=True) - - numpy_testing_assert_equal_helper(a[0], 11) - numpy_testing_assert_equal_helper(a[1], 12) - numpy_testing_assert_equal_helper(a[2], 1) - numpy_testing_assert_equal_helper(a[-3], 1) - numpy_testing_assert_equal_helper(a[-2], 13) - numpy_testing_assert_equal_helper(a[-1], 14) - - a = Tensor.ones((2, N), dtype=dt).contiguous() - indices0 = np.array([0, -1, 0, 1], dtype=dtypes.int64) - indices1 = np.array([-2, -1, 0, 1], dtype=dtypes.int64) - values = np.array([12, 13, 10, 11], dtype=dt) - - index_put_(a, (indices0, indices1), values, accumulate=True) - - numpy_testing_assert_equal_helper(a[0, 0], 11) - numpy_testing_assert_equal_helper(a[0, 1], 1) - numpy_testing_assert_equal_helper(a[1, 0], 1) - numpy_testing_assert_equal_helper(a[1, 1], 12) - numpy_testing_assert_equal_helper(a[:, 2], Tensor.ones(2, dtype=dtypes.int8)) - numpy_testing_assert_equal_helper(a[:, -3], Tensor.ones(2, dtype=dtypes.int8)) - numpy_testing_assert_equal_helper(a[0, -2], 13) - numpy_testing_assert_equal_helper(a[1, -2], 1) - numpy_testing_assert_equal_helper(a[-1, -1], 14) - numpy_testing_assert_equal_helper(a[0, -1], 1) - ''' - - # TODO fancy setitem - ''' - def test_index_put_accumulate_duplicate_indices(self): - for i in range(1, 512): - # generate indices by random walk, this will create indices with - # lots of duplicates interleaved with each other - delta = Tensor.uniform(low=-1, high=1, dtype=dtypes.double) - indices = delta.cumsum(0).cast(dtypes.int64) - - # input = torch.randn(indices.abs().max() + 1) - input = Tensor.randn(indices.abs().max().item() + 1) - # values = torch.randn(indices.size(0)) - values = Tensor.randn(indices.shape(0)) - output = index_put_(input, (indices,), values, accumulate=True) - - input_list = input.numpy().tolist() - indices_list = indices.numpy().tolist() - values_list = values.numpy().tolist() - for i, v in zip(indices_list, values_list): - input_list[i] += v - - numpy_testing_assert_equal_helper(output, input_list) - ''' - - @unittest.skipUnless(is_dtype_supported(dtypes.long), f"long dtype not supported on {Device.DEFAULT}") - def test_index_ind_dtype(self): - x = Tensor.randn(4, 4) - # ind_long = torch.randint(4, (4,), dtype=torch.long) - # TODO should we spend an extra line to allow for randint other dtypes? - # copied from randint - ind_long = (Tensor.rand((4,),)*(4-0)+0).cast(dtypes.int64) - # ind_int = ind_long.int() - ind_int = (ind_long).cast(dtypes.int32) - ref = x[ind_long, ind_long] - res = x[ind_int, ind_int] - numpy_testing_assert_equal_helper(ref, res) - ref = x[ind_long, :] - res = x[ind_int, :] - numpy_testing_assert_equal_helper(ref, res) - ref = x[:, ind_long] - res = x[:, ind_int] - numpy_testing_assert_equal_helper(ref, res) - # no repeating indices for index_put - # TODO fancy setitem - ''' - src = Tensor.randn(4) - ind_long = Tensor.arange(4, dtype=dtypes.int64) - ind_int = ind_long.cast(dtypes.int32) - for accum in (True, False): - inp_ref = clone(x) - inp_res = clone(x) - index_put_(inp_ref, (ind_long, ind_long), src, accum) - index_put_(inp_res, (ind_int, ind_int), src, accum) - numpy_testing_assert_equal_helper(inp_ref, inp_res) - ''' - - # TODO empty setitem - ''' - def test_index_put_accumulate_empty(self): - # Regression test for https://github.com/pytorch/pytorch/issues/94667 - input = Tensor.rand([], dtype=dtypes.float32) - with self.assertRaises(RuntimeError): - index_put_(input, [], np.array([1.0]), True) - ''' - - @unittest.skip("bool indexing not supported") - def test_multiple_byte_mask(self): - v = Tensor.randn(5, 7, 3) - # note: these broadcast together and are transposed to the first dim - mask1 = Tensor([1, 0, 1, 1, 0], dtype=dtypes.uint8) - mask2 = Tensor([1, 1, 1], dtype=dtypes.uint8) - with warnings.catch_warnings(record=True) as w: - warnings.simplefilter("always") - numpy_testing_assert_equal_helper(v[mask1, :, mask2].shape, (3, 7)) - numpy_testing_assert_equal_helper(len(w), 2) - - @unittest.skip("bool indexing not supported") - def test_byte_mask2d(self): - v = Tensor.randn(5, 7, 3) - c = Tensor.randn(5, 7) - num_ones = (c > 0).sum() - r = v[c > 0] - numpy_testing_assert_equal_helper(r.shape, (num_ones, 3)) - - @unittest.skip("bool indexing not supported") - def test_jit_indexing(self): - def fn1(x): - x[x < 50] = 1.0 - return x - - def fn2(x): - x[0:50] = 1.0 - return x - - scripted_fn1 = TinyJit(fn1) - scripted_fn2 = TinyJit(fn2) - data = Tensor.arange(100, dtype=dtypes.float) - out = scripted_fn1(clone(data)) - ref = Tensor(np.concatenate((np.ones(50), np.arange(50, 100))), dtype=dtypes.float) - numpy_testing_assert_equal_helper(out, ref) - out = scripted_fn2(clone(data)) - numpy_testing_assert_equal_helper(out, ref) - - def test_int_indices(self): - v = Tensor.randn(5, 7, 3) - numpy_testing_assert_equal_helper(v[[0, 4, 2]].shape, (3, 7, 3)) - numpy_testing_assert_equal_helper(v[:, [0, 4, 2]].shape, (5, 3, 3)) - numpy_testing_assert_equal_helper(v[:, [[0, 1], [4, 3]]].shape, (5, 2, 2, 3)) - - # TODO fancy setitem - ''' - def test_index_put_src_datatype(self, dtype): - src = Tensor.ones(3, 2, 4, dtype=dtype) - vals = Tensor.ones(3, 2, 4, dtype=dtype) - indices = (np.array([0, 2, 1]),) - res = index_put_(src, indices, vals, accumulate=True) - numpy_testing_assert_equal_helper(res.shape, src.shape) - ''' - - def test_index_src_datatype(self): - src = Tensor.ones(3, 2, 4) - # test index - res = src[[0, 2, 1], :, :] - numpy_testing_assert_equal_helper(res.shape, src.shape) - # test index_put, no accum - # TODO fancy setitem - ''' - src[[0, 2, 1], :, :] = res - numpy_testing_assert_equal_helper(res.shape, src.shape) - ''' - - def test_int_indices2d(self): - # From the NumPy indexing example - x = Tensor.arange(0, 12).reshape(4, 3) - rows = Tensor([[0, 0], [3, 3]]) - columns = Tensor([[0, 2], [0, 2]]) - numpy_testing_assert_equal_helper(x[rows, columns].numpy().tolist(), [[0, 2], [9, 11]]) - - def test_int_indices_broadcast(self): - # From the NumPy indexing example - x = Tensor.arange(0, 12).reshape(4, 3) - rows = Tensor([0, 3]) - columns = Tensor([0, 2]) - result = x[rows[:, None], columns] - numpy_testing_assert_equal_helper(result.numpy().tolist(), [[0, 2], [9, 11]]) - - # TODO jax supports empty tensor indexing - @unittest.skip("empty tensor indexing not supported") - def test_empty_index(self): - x = Tensor.arange(0, 12).reshape(4, 3) - idx = Tensor([], dtype=dtypes.int64) - numpy_testing_assert_equal_helper(x[idx].numel(), 0) - - # TODO empty setitem - ''' - # empty assignment should have no effect but not throw an exception - y = clone(x) - y[idx] = -1 - numpy_testing_assert_equal_helper(x, y) - - mask = Tensor.zeros(4, 3).cast(dtypes.bool) - y[mask] = -1 - numpy_testing_assert_equal_helper(x, y) - ''' - - # TODO jax supports empty tensor indexing - @unittest.skip("empty tensor indexing not supported") - def test_empty_ndim_index(self): - x = Tensor.randn(5) - numpy_testing_assert_equal_helper(Tensor.empty(0, 2), x[Tensor.empty(0, 2, dtype=dtypes.int64)]) - - x = Tensor.randn(2, 3, 4, 5) - numpy_testing_assert_equal_helper(Tensor.empty(2, 0, 6, 4, 5), - x[:, Tensor.empty(0, 6, dtype=dtypes.int64)]) - - x = Tensor.empty(10, 0) - numpy_testing_assert_equal_helper(x[[1, 2]].shape, (2, 0)) - numpy_testing_assert_equal_helper(x[[], []].shape, (0,)) - with self.assertRaises(IndexError): - x[:, [0, 1]] - - def test_empty_slice(self): - x = Tensor.randn(2, 3, 4, 5) - y = x[:, :, :, 1] - z = y[:, 1:1, :] - numpy_testing_assert_equal_helper((2, 0, 4), z.shape) - # this isn't technically necessary, but matches NumPy stride calculations. - # NOTE: this is empty and shouldn't have strides - #numpy_testing_assert_equal_helper((60, 20, 5), z.uop.st.real_strides()) - # NOTE tinygrad's int slicing implementation makes this not contiguous - # self.assertTrue(z.uop.st.contiguous) - - @unittest.skip("bool indexing not supported") - def test_index_getitem_copy_bools_slices(self): - true = Tensor(1, dtype=dtypes.uint8) - false = Tensor(0, dtype=dtypes.uint8) - - tensors = [Tensor.randn(2, 3), Tensor(3.)] - - for a in tensors: - self.assertNotEqual(data_ptr(a), data_ptr(a[True])) - numpy_testing_assert_equal_helper(Tensor.empty(0, *a.shape), a[False]) - self.assertNotEqual(data_ptr(a), data_ptr(a[true])) - numpy_testing_assert_equal_helper(Tensor.empty(0, *a.shape), a[false]) - self.assertEqual(data_ptr(a), data_ptr(a[None])) - self.assertEqual(data_ptr(a), data_ptr(a[...])) - - @unittest.skip("bool indexing not supported") - def test_index_setitem_bools_slices(self): - true = Tensor(1, dtype=dtypes.uint8) - false = Tensor(0, dtype=dtypes.uint8) - - tensors = [Tensor.randn(2, 3), Tensor(3)] - - for a in tensors: - # prefix with a 1,1, to ensure we are compatible with numpy which cuts off prefix 1s - # (some of these ops already prefix a 1 to the size) - neg_ones = Tensor.ones_like(a) * -1 - neg_ones_expanded = neg_ones.unsqueeze(0).unsqueeze(0) - a[True] = neg_ones_expanded - numpy_testing_assert_equal_helper(a, neg_ones) - a[False] = 5 - numpy_testing_assert_equal_helper(a, neg_ones) - a[true] = neg_ones_expanded * 2 - numpy_testing_assert_equal_helper(a, neg_ones * 2) - a[false] = 5 - numpy_testing_assert_equal_helper(a, neg_ones * 2) - a[None] = neg_ones_expanded * 3 - numpy_testing_assert_equal_helper(a, neg_ones * 3) - a[...] = neg_ones_expanded * 4 - numpy_testing_assert_equal_helper(a, neg_ones * 4) - if a.dim() == 0: - with self.assertRaises(IndexError): - a[:] = neg_ones_expanded * 5 - - @unittest.skip("bool indexing not supported") - def test_index_scalar_with_bool_mask(self): - a = Tensor(1) - uintMask = Tensor(True, dtype=dtypes.uint8) - boolMask = Tensor(True, dtype=dtypes.bool) - numpy_testing_assert_equal_helper(a[uintMask], a[boolMask]) - numpy_testing_assert_equal_helper(a[uintMask].dtype, a[boolMask].dtype) - - a = Tensor(True, dtype=dtypes.bool) - numpy_testing_assert_equal_helper(a[uintMask], a[boolMask]) - numpy_testing_assert_equal_helper(a[uintMask].dtype, a[boolMask].dtype) - - @unittest.skip("bool indexing not supported") - def test_setitem_expansion_error(self): - true = Tensor(True) - a = Tensor.randn(2, 3) - # check prefix with non-1s doesn't work - # a_expanded = a.expand(torch.Size([5, 1]) + a.size()) - a_expanded = a.expand((5, 1) + a.shape) - # NumPy: ValueError - with self.assertRaises(RuntimeError): - a[True] = a_expanded - with self.assertRaises(RuntimeError): - a[true] = a_expanded - - def test_getitem_scalars_simple(self): - src = Tensor([[[1.,2.],[3.,4.]], [[1,1],[1,1]]]) - a = src[0].mul(src[1]) - self.assertEqual(a[0,1].item(), 2) - - @unittest.skipUnless(is_dtype_supported(dtypes.int64), "need dtypes.int64") - def test_getitem_scalars(self): - zero = Tensor(0, dtype=dtypes.int64) - one = Tensor(1, dtype=dtypes.int64) - - # non-scalar indexed with scalars - a = Tensor.randn(2, 3).realize() - numpy_testing_assert_equal_helper(a[0], a[zero]) - numpy_testing_assert_equal_helper(a[0][1], a[zero][one]) - numpy_testing_assert_equal_helper(a[0, 1], a[zero, one]) - numpy_testing_assert_equal_helper(a[0, one], a[zero, 1]) - - # indexing by a scalar should slice (not copy) - numpy_testing_assert_equal_helper(a[0, 1], a[zero, one]) - numpy_testing_assert_equal_helper(a[1], a[one.cast(dtypes.int32)]) - numpy_testing_assert_equal_helper(a[1], a[one.cast(dtypes.int16)]) - - # scalar indexed with scalar - r = Tensor.randn().realize() - with self.assertRaises(IndexError): - r[:] - with self.assertRaises(IndexError): - r[zero] - numpy_testing_assert_equal_helper(r, r[...]) - - # TODO fancy setitem - ''' - def test_setitem_scalars(self): - zero = Tensor(0, dtype=dtypes.int64) - - # non-scalar indexed with scalars - a = Tensor.randn(2, 3).contiguous() - a_set_with_number = clone(a).contiguous() - a_set_with_scalar = clone(a).contiguous() - b = Tensor.randn(3) - - a_set_with_number[0] = b - a_set_with_scalar[zero] = b - numpy_testing_assert_equal_helper(a_set_with_number, a_set_with_scalar) - a[1, zero] = 7.7 - # TODO: weird inaccuracy Max relative difference: 2.47707621e-08 - # numpy_testing_assert_equal_helper(7.7, a[1, 0]) - np.testing.assert_allclose(7.7, a[1, 0].numpy(), rtol=1e-7) - - # scalar indexed with scalars - r = Tensor.randn().contiguous() - with self.assertRaises(IndexError): - r[:] = 8.8 - with self.assertRaises(IndexError): - r[zero] = 8.8 - r[...] = 9.9 - # TODO: weird inaccuracy Max relative difference: 3.85322971e-08 - # numpy_testing_assert_equal_helper(9.9, r) - np.testing.assert_allclose(9.9, r, rtol=1e-7) - ''' - - @unittest.skip("getitem expects elementwise ops folding to be instant, but it happens late in the scheduler") - def test_getitem_casted_scalars_folding(self): - Tensor.manual_seed(0) - # cast of const is just another const, don't need extra kernels for this - a = Tensor.randn(2, 3) - one = Tensor(1, dtype=dtypes.int64) - self.assertEqual(data_ptr(a[1]), data_ptr(a[one.cast(dtypes.int32)])) - self.assertEqual(data_ptr(a[1]), data_ptr(a[one.cast(dtypes.int16)])) - - @unittest.skip("does not fold now") - def test_getitem_scalars_simple_folding(self): - a = Tensor.randn(2, 3) - zero = Tensor(0, dtype=dtypes.int64) - one = Tensor(1, dtype=dtypes.int64) - self.assertEqual(data_ptr(a[0, 1]), data_ptr(a[zero, one])) - - def test_basic_advanced_combined(self): - # From the NumPy indexing example - x = Tensor.arange(0, 12).reshape(4, 3) - numpy_testing_assert_equal_helper(x[1:2, 1:3], x[1:2, [1, 2]]) - numpy_testing_assert_equal_helper(x[1:2, 1:3].numpy().tolist(), [[4, 5]]) - - # Check that it is a copy - unmodified = clone(x) - x[1:2, [1, 2]].zeros_like() - numpy_testing_assert_equal_helper(x, unmodified) - - # But assignment should modify the original - # TODO fancy setitem - ''' - unmodified = clone(x) - x[1:2, [1, 2]] = 0 - self.assertNotEqual(x, unmodified) - ''' - - def test_int_assignment(self): - x = Tensor.arange(0, 4).reshape(2, 2) - x[1] = 5 - numpy_testing_assert_equal_helper(x.numpy().tolist(), [[0, 1], [5, 5]]) - - x = Tensor.arange(0, 4).reshape(2, 2) - x[1] = Tensor.arange(5, 7) - numpy_testing_assert_equal_helper(x.numpy().tolist(), [[0, 1], [5, 6]]) - - # TODO fancy setitem - ''' - def test_byte_tensor_assignment(self): - x = Tensor.arange(0., 16).reshape(4, 4) - b = Tensor([True, False, True, False], dtype=dtypes.uint8) - value = Tensor([3., 4., 5., 6.]) - - with warnings.catch_warnings(record=True) as w: - x[b] = value - numpy_testing_assert_equal_helper(len(w), 1) - - numpy_testing_assert_equal_helper(x[0], value) - numpy_testing_assert_equal_helper(x[1], Tensor.arange(4., 8)) - numpy_testing_assert_equal_helper(x[2], value) - numpy_testing_assert_equal_helper(x[3], Tensor.arange(12., 16)) - ''' - - @unittest.skip("Tensor unpacking not supported") - def test_variable_slicing(self): - x = Tensor.arange(0, 16).reshape(4, 4) - indices = Tensor([0, 1], dtype=dtypes.int32) - i, j = indices - numpy_testing_assert_equal_helper(x[i:j], x[0:1]) - - def test_ellipsis_tensor(self): - x = Tensor.arange(0, 9).reshape(3, 3) - idx = Tensor([0, 2]) - numpy_testing_assert_equal_helper(x[..., idx].numpy().tolist(), [[0, 2], - [3, 5], - [6, 8]]) - numpy_testing_assert_equal_helper(x[idx, ...].numpy().tolist(), [[0, 1, 2], - [6, 7, 8]]) - - # TODO unravel_index - ''' - def test_unravel_index_errors(self): - with self.assertRaises(TypeError): - unravel_index( - Tensor(0.5), - (2, 2)) - - with self.assertRaises(TypeError): - unravel_index( - Tensor([]), - (10, 3, 5)) - - with self.assertRaises(TypeError): - unravel_index( - Tensor([1], dtype=dtypes.int64), - Tensor([1, 2, 3])) - - with self.assertRaises(TypeError): - unravel_index( - Tensor([1], dtype=dtypes.int64), - (1, 2, 2.0)) - - with self.assertRaises(ValueError): - unravel_index( - Tensor(0), - (2, -3)) - ''' - - def test_invalid_index(self): - x = Tensor.arange(0, 16).reshape(4, 4) - self.assertRaises(TypeError, lambda: x["0":"1"]) - - def test_out_of_bound_index(self): - x = Tensor.arange(0, 100).reshape(2, 5, 10) - self.assertRaises(IndexError, lambda: x[0, 5]) - self.assertRaises(IndexError, lambda: x[4, 5]) - self.assertRaises(IndexError, lambda: x[0, 1, 15]) - self.assertRaises(IndexError, lambda: x[:, :, 12]) - - def test_zero_dim_index(self): - x = Tensor(10) - numpy_testing_assert_equal_helper(x, x.item()) - - def runner(): - print(x[0]) - return x[0] - - self.assertRaises(IndexError, runner) - - # TODO fancy setitem - ''' - def test_cpu_indices(self): - idx = Tensor([0, 1]) - b = Tensor.zeros(2) - x = Tensor.ones(10).contiguous() - x[idx] = b # index_put_ - ref = Tensor.ones(10).contiguous() - ref[:2] = 0 - numpy_testing_assert_equal_helper(x, ref) - out = x[idx] # index - numpy_testing_assert_equal_helper(out, Tensor.zeros(2)) - ''' - - def test_take_along_dim(self): - def _test_against_numpy(t: Tensor, indices: Tensor, dim): - actual = t.gather(dim, indices) - t_np = t.numpy() - indices_np = indices.numpy() - expected = np.take_along_axis(t_np, indices_np, axis=dim) - numpy_testing_assert_equal_helper(actual, expected) - - # TODO argsort - ''' - for shape in [(3, 2), (2, 3, 5), (2, 4, 0), (2, 3, 1, 4)]: - for noncontiguous in [True, False]: - for dtype in (dtypes.float32, dtypes.int64): - t = make_tensor(shape, dtype=dtype, noncontiguous=noncontiguous) - for dim in list(range(t.ndim)) + [None]: - if dim is None: - indices = argsort(t.reshape(-1)) - else: - indices = argsort(t, dim=dim) - - _test_against_numpy(t, indices, dim) - ''' - - # test broadcasting - t = Tensor.ones((3, 4, 1)) - indices = Tensor.ones((1, 2, 5), dtype=dtypes.int64) - - _test_against_numpy(t, indices, 1) - - # test empty indices - t = Tensor.ones((3, 4, 5)) - indices = Tensor.ones((3, 0, 5), dtype=dtypes.int64) - - _test_against_numpy(t, indices, 1) - - # TODO argsort - ''' - def test_take_along_dim_invalid(self): - for dtype in (dtypes.int64, dtypes.float32): - shape = (2, 3, 1, 4) - dim = 0 - t = make_tensor(shape, dtype=dtype) - indices = argsort(t, dim=dim) - - # dim of `t` and `indices` does not match - with self.assertRaises(RuntimeError, "input and indices should have the same number of dimensions"): - t.gather(0, indices[0]) - - # invalid `indices` dtype - with self.assertRaises(RuntimeError): - t.gather(0, indices.cast(dtypes.bool)) - - with self.assertRaises(RuntimeError): - t.gather(0, indices.cast(dtypes.float32)) - - with self.assertRaises(RuntimeError): - t.gather(0, indices.cast(dtypes.int32)) - - # invalid axis - with self.assertRaises(IndexError): - t.gather(-7, indices) - - with self.assertRaises(IndexError): - t.gather(7, indices) - ''' - -class TestNumpy(unittest.TestCase): - def test_index_no_floats(self): - a = Tensor([[[5.]]]) - - self.assertRaises(IndexError, lambda: a[0.0]) - self.assertRaises(IndexError, lambda: a[0, 0.0]) - self.assertRaises(IndexError, lambda: a[0.0, 0]) - self.assertRaises(IndexError, lambda: a[0.0, :]) - self.assertRaises(IndexError, lambda: a[:, 0.0]) - self.assertRaises(IndexError, lambda: a[:, 0.0, :]) - self.assertRaises(IndexError, lambda: a[0.0, :, :]) - self.assertRaises(IndexError, lambda: a[0, 0, 0.0]) - self.assertRaises(IndexError, lambda: a[0.0, 0, 0]) - self.assertRaises(IndexError, lambda: a[0, 0.0, 0]) - self.assertRaises(IndexError, lambda: a[-1.4]) - self.assertRaises(IndexError, lambda: a[0, -1.4]) - self.assertRaises(IndexError, lambda: a[-1.4, 0]) - self.assertRaises(IndexError, lambda: a[-1.4, :]) - self.assertRaises(IndexError, lambda: a[:, -1.4]) - self.assertRaises(IndexError, lambda: a[:, -1.4, :]) - self.assertRaises(IndexError, lambda: a[-1.4, :, :]) - self.assertRaises(IndexError, lambda: a[0, 0, -1.4]) - self.assertRaises(IndexError, lambda: a[-1.4, 0, 0]) - self.assertRaises(IndexError, lambda: a[0, -1.4, 0]) - # these two trigger slice internal type verification first - self.assertRaises(TypeError, lambda: a[0.0:, 0.0]) - self.assertRaises(TypeError, lambda: a[0.0:, 0.0,:]) - - def test_none_index(self): - # `None` index adds newaxis - a = Tensor([1, 2, 3]) - numpy_testing_assert_equal_helper(a[None].ndim, a.ndim+1) - - def test_empty_tuple_index(self): - # Empty tuple index creates a view - a = Tensor([1, 2, 3]) - numpy_testing_assert_equal_helper(a[()], a) - #self.assertEqual(data_ptr(a[()]), data_ptr(a)) - - # TODO jax supports empty tensor indexing - @unittest.skip("empty tensor indexing not supported") - def test_empty_fancy_index(self): - # Empty list index creates an empty array - a = Tensor([1, 2, 3]) - numpy_testing_assert_equal_helper(a[[]], np.array([])) - - b = Tensor([]).cast(dtypes.int64) - numpy_testing_assert_equal_helper(a[[]], np.array([])) - - b = Tensor([]).float() - self.assertRaises(IndexError, lambda: a[b]) - - def test_ellipsis_index(self): - a = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - self.assertIsNot(a[...], a) - numpy_testing_assert_equal_helper(a[...], a) - # `a[...]` was `a` in numpy <1.9. - #numpy_testing_assert_equal_helper(data_ptr(a[...]), data_ptr(a)) - - # Slicing with ellipsis can skip an - # arbitrary number of dimensions - numpy_testing_assert_equal_helper(a[0, ...], a[0]) - numpy_testing_assert_equal_helper(a[0, ...], a[0, :]) - numpy_testing_assert_equal_helper(a[..., 0], a[:, 0]) - - # In NumPy, slicing with ellipsis results in a 0-dim array. In PyTorch - # we don't have separate 0-dim arrays and scalars. - numpy_testing_assert_equal_helper(a[0, ..., 1], np.array(2)) - - # Assignment with `(Ellipsis,)` on 0-d arrays - b = np.array(1) - b[(Ellipsis,)] = 2 - numpy_testing_assert_equal_helper(b, 2) - - def test_single_int_index(self): - # Single integer index selects one row - a = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - - numpy_testing_assert_equal_helper(a[0], [1, 2, 3]) - numpy_testing_assert_equal_helper(a[-1], [7, 8, 9]) - - self.assertRaises(IndexError, a.__getitem__, 1 << 30) - self.assertRaises(IndexError, a.__getitem__, 1 << 64) - - @unittest.skip("bool indexing not supported") - def test_single_bool_index(self): - # Single boolean index - a = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - - numpy_testing_assert_equal_helper(a[True], a[None]) - numpy_testing_assert_equal_helper(a[False], a[None][0:0]) - - @unittest.skip("bool indexing not supported") - def test_boolean_shape_mismatch(self): - arr = Tensor.ones((5, 4, 3)) - - index = Tensor([True]) - self.assertRaises(IndexError, lambda: arr[index]) - - index = Tensor([False] * 6) - self.assertRaises(IndexError, lambda: arr[index]) - - index = Tensor.zeros(4, 4, dtype=dtypes.uint8) - self.assertRaises(IndexError, lambda: arr[index]) - self.assertRaises(IndexError, lambda: arr[(slice(None), index)]) - - @unittest.skip("bool indexing not supported") - def test_boolean_indexing_onedim(self): - # Indexing a 2-dimensional array with - # boolean array of length one - a = Tensor([[0., 0., 0.]]) - b = Tensor([True]) - numpy_testing_assert_equal_helper(a[b], a) - # boolean assignment - a[b] = 1. - numpy_testing_assert_equal_helper(a, Tensor([[1., 1., 1.]])) - - @unittest.skip("bool indexing not supported") - def test_boolean_assignment_value_mismatch(self): - # A boolean assignment should fail when the shape of the values - # cannot be broadcast to the subscription. (see also gh-3458) - a = Tensor.arange(0, 4) - - def f(a, v): - a[a > -1] = Tensor(v) - - self.assertRaises(Exception, f, a, []) - self.assertRaises(Exception, f, a, [1, 2, 3]) - self.assertRaises(Exception, f, a[:1], [1, 2, 3]) - - @unittest.skip("bool indexing not supported") - def test_boolean_indexing_twodim(self): - # Indexing a 2-dimensional array with - # 2-dimensional boolean array - a = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - b = Tensor([[True, False, True], - [False, True, False], - [True, False, True]]) - numpy_testing_assert_equal_helper(a[b], Tensor([1, 3, 5, 7, 9])) - numpy_testing_assert_equal_helper(a[b[1]], Tensor([[4, 5, 6]])) - numpy_testing_assert_equal_helper(a[b[0]], a[b[2]]) - - # boolean assignment - a[b] = 0 - numpy_testing_assert_equal_helper(a, Tensor([[0, 2, 0], - [4, 0, 6], - [0, 8, 0]])) - - @unittest.skip("bool indexing not supported") - def test_boolean_indexing_weirdness(self): - # Weird boolean indexing things - a = Tensor.ones((2, 3, 4)) - numpy_testing_assert_equal_helper((0, 2, 3, 4), a[False, True, ...].shape) - numpy_testing_assert_equal_helper(Tensor.ones(1, 2), a[True, [0, 1], True, True, [1], [[2]]]) - self.assertRaises(IndexError, lambda: a[False, [0, 1], ...]) - - @unittest.skip("bool indexing not supported") - def test_boolean_indexing_weirdness_tensors(self): - # Weird boolean indexing things - false = Tensor(False) - true = Tensor(True) - a = Tensor.ones((2, 3, 4)) - numpy_testing_assert_equal_helper((0, 2, 3, 4), a[False, True, ...].shape) - numpy_testing_assert_equal_helper(Tensor.ones(1, 2), a[true, [0, 1], true, true, [1], [[2]]]) - self.assertRaises(IndexError, lambda: a[false, [0, 1], ...]) - - @unittest.skip("bool indexing not supported") - def test_boolean_indexing_alldims(self): - true = Tensor(True) - a = Tensor.ones((2, 3)) - numpy_testing_assert_equal_helper((1, 2, 3), a[True, True].shape) - numpy_testing_assert_equal_helper((1, 2, 3), a[true, true].shape) - - @unittest.skip("bool indexing not supported") - def test_boolean_list_indexing(self): - # Indexing a 2-dimensional array with - # boolean lists - a = Tensor([[1, 2, 3], - [4, 5, 6], - [7, 8, 9]]) - b = [True, False, False] - c = [True, True, False] - numpy_testing_assert_equal_helper(a[b], Tensor([[1, 2, 3]])) - numpy_testing_assert_equal_helper(a[b, b], Tensor([1])) - numpy_testing_assert_equal_helper(a[c], Tensor([[1, 2, 3], [4, 5, 6]])) - numpy_testing_assert_equal_helper(a[c, c], Tensor([1, 5])) - - def test_everything_returns_views(self): - # Before `...` would return a itself. - a = Tensor([5]) - - self.assertIsNot(a, a[()]) - self.assertIsNot(a, a[...]) - self.assertIsNot(a, a[:]) - - def test_broaderrors_indexing(self): - a = Tensor.zeros(5, 5) - self.assertRaises(IndexError, a.__getitem__, ([0, 1], [0, 1, 2])) - self.assertRaises(IndexError, a.contiguous().__setitem__, ([0, 1], [0, 1, 2]), 0) - - # TODO out of bound getitem does not raise error - ''' - def test_trivial_fancy_out_of_bounds(self): - a = Tensor.zeros(5) - ind = Tensor.ones(20, dtype=dtypes.int64) - ind[-1] = 10 - self.assertRaises(IndexError, a.__getitem__, ind) - self.assertRaises(IndexError, a.__setitem__, ind, 0) - ind = Tensor.ones(20, dtype=dtypes.int64) - ind[0] = 11 - self.assertRaises(IndexError, a.__getitem__, ind) - self.assertRaises(IndexError, a.__setitem__, ind, 0) - ''' - - # TODO fancy setitem - ''' - def test_index_is_larger(self): - # Simple case of fancy index broadcasting of the index. - a = Tensor.zeros((5, 5)) - a[[[0], [1], [2]], [0, 1, 2]] = Tensor([2., 3., 4.]) - - self.assertTrue((a[:3, :3] == all_(Tensor([2., 3., 4.])))) - ''' - - # TODO fancy setitem - ''' - def test_broadcast_subspace(self): - a = Tensor.zeros((100, 100)) - v = Tensor.arange(0., 100)[:, None] - b = Tensor.arange(99, -1, -1).cast(dtypes.int64) - a[b] = v - expected = b.float().unsqueeze(1).expand(100, 100) - numpy_testing_assert_equal_helper(a, expected) - ''' - - # TODO fancy setitem - ''' - def test_truncate_leading_1s(self): - col_max = Tensor.randn(1, 4) - kernel = col_max.T * col_max # [4, 4] tensor - kernel2 = clone(kernel) - # Set the diagonal - # len(torch.tensor) is just tensor.shape[0] - kernel[range(kernel.shape[0]), range(kernel.shape[0])] = col_max.square() - kernel2 = diagonal(kernel2) - # torch.diagonal(kernel2).copy_(torch.square(col_max.view(4))) - kernel2 = copy_(kernel2, col_max.reshape(4).square()) - numpy_testing_assert_equal_helper(kernel, kernel2) - ''' - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_keccak.py b/tinygrad/test/unit/test_keccak.py deleted file mode 100644 index c32a74f8..00000000 --- a/tinygrad/test/unit/test_keccak.py +++ /dev/null @@ -1,42 +0,0 @@ -from typing_extensions import Callable -import hashlib, random, unittest -from tinygrad import Tensor, Device, getenv, dtypes -from tinygrad.device import is_dtype_supported - -@unittest.skipUnless(is_dtype_supported(dtypes.uint8) and is_dtype_supported(dtypes.uint64), "Device must support uint8 and uint64") -@unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT == "NV", "crashes in NV CI") -class TestKeccak(unittest.TestCase): - def setUp(self) -> None: random.seed(1337) - - def test_shape_keeping(self): - s = (1, 2, 3, 4) - for i in range(len(s)): - out_shape = Tensor.randint(*s[i:], high=255, dtype=dtypes.uint8).keccak().shape - self.assertTupleEqual(s[i:-1], out_shape[:-1]) - - def test_sha3_224(self): self._test_preset("sha3_224", [143, 144]) - def test_sha3_256(self): self._test_preset("sha3_256", [135, 136]) - def test_shake_128(self): self._test_preset("shake_128", [167, 168], lambda d: hashlib.shake_128(d).digest(16)) - - def _test_preset(self, name: str, special_sizes: list[int], hasher: Callable[[bytes], bytes] | None = None): - def default_hasher(d: bytes) -> bytes: return getattr(hashlib, name)(d).digest() - if hasher is None: hasher = default_hasher - - for n in (special_sizes + [special_sizes[0] - 1]): - a, b = random.randbytes(n), random.randbytes(n) - - ha_ref, hb_ref = hasher(a), hasher(b) - tres = Tensor.stack(*(Tensor(d) for d in (a, b))).keccak(name) - ha, hb = tres[0].data(), tres[1].data() - - self.assertEqual(ha_ref, ha) - self.assertEqual(ha_ref, Tensor(a).keccak(name).data()) - self.assertEqual(hb_ref, hb) - - def test_abc(self): - # https://www.di-mgt.com.au/sha_testvectors.html - out = Tensor(b"abc").keccak() - self.assertEqual(bytes(out.tolist()), bytearray.fromhex("3a985da74fe225b2 045c172d6bd390bd 855f086e3e9d525b 46bfe24511431532")) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_kernelize.py b/tinygrad/test/unit/test_kernelize.py deleted file mode 100644 index 2b0bcee5..00000000 --- a/tinygrad/test/unit/test_kernelize.py +++ /dev/null @@ -1,33 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad.uop import Ops - -class TestKernelize(unittest.TestCase): - def test_add_reshaped(self): - a = Tensor.ones(16,16).contiguous() - b = Tensor.zeros(16,16).contiguous() - ret = (a+b).sum(axis=1) - ret_reshaped_1 = ret.reshape(4,4) - ret_reshaped_2 = ret.reshape(2,8) - ret.kernelize() - self.assertIs(ret_reshaped_1.uop.src[0], ret_reshaped_2.uop.src[0]) - - def test_two_reduce(self): - a = Tensor.ones(16,16).contiguous() - a1 = a.sum(axis=1) - a0 = a1.sum(axis=0) - a0.kernelize() - self.assertIs(a1.uop.base.op, Ops.ASSIGN) - - def test_two_reduce_w_add(self): - a = Tensor.ones(16,16).contiguous() - a1 = a.sum(axis=1) - a0 = (a1+1).sum(axis=0) - a0.kernelize() - # NOTE: the +1 is fused with a1, so a1 is not kernelized - self.assertIs(a1.uop.base.op, Ops.REDUCE_AXIS) - # the input to the REDUCE_AXIS is an ASSIGN though - self.assertIs(a1.uop.base.src[0].base.op, Ops.ASSIGN) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_linearizer_rewrite.py b/tinygrad/test/unit/test_linearizer_rewrite.py deleted file mode 100644 index 358c43ce..00000000 --- a/tinygrad/test/unit/test_linearizer_rewrite.py +++ /dev/null @@ -1,28 +0,0 @@ -import unittest -from tinygrad import Tensor, Context, Device -from tinygrad.codegen.kernel import Kernel, Opt, OptOps - -class TestLinearizerRewrite(unittest.TestCase): - def test_reduction(self): - t = Tensor.ones((64,64), device="NULL").contiguous().realize() - out = (t*2).sum(axis=1) - with Context(SPLIT_REDUCEOP=0, DEVECTORIZE=0): - si = out.schedule()[-1] - k = Kernel(si.ast, Device["CPU"].renderer) - k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) - prg = k.to_program() - print(prg.src) - - def test_arange(self): - out = Tensor.arange(32, device="NULL") - with Context(SPLIT_REDUCEOP=0, DEVECTORIZE=0): - si = out.schedule()[-1] - k = Kernel(si.ast, Device["CPU"].renderer) - k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) - k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) - prg = k.to_program() - print(prg.src) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_masked_st.py b/tinygrad/test/unit/test_masked_st.py deleted file mode 100644 index ce88a710..00000000 --- a/tinygrad/test/unit/test_masked_st.py +++ /dev/null @@ -1,32 +0,0 @@ -import unittest -from tinygrad.tensor import Tensor - -class TestMaskedShapeTracker(unittest.TestCase): - def test_mul_masked(self): - a = Tensor([1,1,1,1,1]) - b = Tensor([1,1]).pad(((0,3),)) - c = a*b - assert c.shape == a.shape - #assert c.uop.st.views[0].mask is not None - ret = c.data() - assert ret.tolist() == [1.0, 1.0, 0.0, 0.0, 0.0] - - def test_mul_both_masked(self): - a = Tensor([1,1]).pad(((0,3),)) - b = Tensor([1,1]).pad(((0,3),)) - c = a*b - assert c.shape == a.shape - #assert c.uop.st.views[0].mask is not None - ret = c.data() - assert ret.tolist() == [1.0, 1.0, 0.0, 0.0, 0.0] - - def test_add_masked(self): - a = Tensor([1,1]).pad(((0,2),)) - b = Tensor([1,1]).pad(((0,2),)) - c = a+b - #assert c.uop.st.views[0].mask is not None - ret = c.data() - assert ret.tolist() == [2.0, 2.0, 0.0, 0.0] - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_microbenchmarks.py b/tinygrad/test/unit/test_microbenchmarks.py deleted file mode 100644 index 71b43c88..00000000 --- a/tinygrad/test/unit/test_microbenchmarks.py +++ /dev/null @@ -1,43 +0,0 @@ -import unittest, time -from tinygrad.uop.ops import UOp -from tinygrad.dtype import dtypes - -# it's about 1 ms per 1k UOps on M3 -N = 10000 - -class TestMicrobenchmarks(unittest.TestCase): - def setUp(self): - self.st = time.perf_counter() - def tearDown(self): - et = (time.perf_counter() - self.st) - print(f"{self._testMethodName} {et*1e3:.2f} ms") - - def test_uop_instant_creation(self): - for i in range(N): UOp.const(dtypes.int, 100+i) - - def test_uop_list_creation(self): - [UOp.const(dtypes.int, 100+i) for i in range(N)] - - def test_uop_add_2n(self): - a = UOp.const(dtypes.int, 2) - for _ in range(N): a = a + a - - def test_uop_toposort(self): - a = UOp.const(dtypes.int, 0) - for i in range(N): a = a + UOp.const(dtypes.int, 100+i) - self.setUp() - self.assertEqual(len(a.toposort()), 2*N+1) - - def test_uop_toposort_2n(self): - a = UOp.const(dtypes.int, 0) - for i in range(N): a = a + a - self.setUp() - self.assertEqual(len(a.toposort()), N+1) - - def test_uop_simplify(self): - a = UOp.const(dtypes.int, 2) - for _ in range(N): (a+a).simplify() - -if __name__ == '__main__': - unittest.main() - diff --git a/tinygrad/test/unit/test_mnist_dataset.py b/tinygrad/test/unit/test_mnist_dataset.py deleted file mode 100644 index 9db9a9e3..00000000 --- a/tinygrad/test/unit/test_mnist_dataset.py +++ /dev/null @@ -1,14 +0,0 @@ -import unittest -from tinygrad.helpers import GlobalCounters -from tinygrad.nn.datasets import mnist - -class TestDataset(unittest.TestCase): - def test_dataset_is_realized(self): - X_train, _, _, _ = mnist() - X_train[0].contiguous().realize() - start = GlobalCounters.kernel_count - X_train[0].contiguous().realize() - self.assertEqual(GlobalCounters.kernel_count-start, 1) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_pattern_matcher.py b/tinygrad/test/unit/test_pattern_matcher.py deleted file mode 100644 index d1dfffaa..00000000 --- a/tinygrad/test/unit/test_pattern_matcher.py +++ /dev/null @@ -1,215 +0,0 @@ -import unittest, itertools -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import Ops, UOp, GroupOp # noqa: F401 -from tinygrad.uop.ops import PatternMatcher, UPat - -class TestPatternMatcher(unittest.TestCase): - def test_simple_match(self): - matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype=dtypes.float), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.int, arg=1) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), None) - - def test_upat_any(self): - def test(a, x=None, y=None, z=None): - #print(x,y,z) - if y is not None: return a+y - matcher = PatternMatcher([ - (UPat.var("a")+UPat.any(UPat.var("x"), UPat.var("y"), UPat.var("z")), test), - ]) - v1 = UOp.variable("a", 0, 10) - v2 = UOp.variable("b", 0, 10) - c1 = v1+v2 - self.assertEqual(matcher.rewrite(c1), c1) - - def test_minimum_len(self): - matcher = PatternMatcher([ - (UPat(Ops.NOOP, src=(UPat(Ops.NOOP), UPat(Ops.NOOP)), allow_any_len=True), lambda: True), - ]) - self.assertTrue(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP), UOp(Ops.NOOP), UOp(Ops.NOOP),)))) - self.assertTrue(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP), UOp(Ops.NOOP))))) - self.assertIsNone(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP),)))) - - @unittest.skip("closures aren't supported on pattern matchers") - def test_match_sz_0(self): - match_cnt = 0 - def fxn(x): - nonlocal match_cnt - match_cnt += 1 - assert len(x.src) == 0 - return UOp(Ops.CONST, src=(UOp(Ops.CONST),)) - matcher = PatternMatcher([(UPat(Ops.CONST, src=(), name="x"), fxn)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - # second rewrite shouldn't match anything - c1 = matcher.rewrite(c1) - c1 = matcher.rewrite(c1) - self.assertEqual(match_cnt, 1) - - def test_match_sz_0_ctx(self): - def fxn(ctx, x): - ctx.append(True) - assert len(x.src) == 0 - return UOp(Ops.CONST, src=(UOp(Ops.CONST),)) - matcher = PatternMatcher([(UPat(Ops.CONST, src=(), name="x"), fxn)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - # second rewrite shouldn't match anything - ctx = [] - c1 = matcher.rewrite(c1, ctx) - c1 = matcher.rewrite(c1, ctx) - self.assertEqual(len(ctx), 1) - - def test_uop(self): - matcher = PatternMatcher([(UPat(Ops.CONST, name="x"), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.ADD, dtypes.float, (c1, c1)) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), None) - - def test_uop_set(self): - matcher = PatternMatcher([(UPat((Ops.CONST, Ops.CAST), name="x"), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.bool, arg=False) - c2 = UOp(Ops.CAST, dtypes.int, (c1,)) - c3 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c4 = UOp(Ops.ADD, dtypes.float, (c3, c3)) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), c2) - self.assertEqual(matcher.rewrite(c4), None) - - def test_arg(self): - matcher = PatternMatcher([ - (UPat(Ops.CONST, arg=0, name="x"), lambda x: x), - (UPat(Ops.CONST, arg=False, name="x"), lambda x: x), - (UPat(Ops.MAX, name="x"), lambda x: x), - ]) - c1 = UOp(Ops.CONST, dtypes.float, arg=0.0) - c2 = UOp(Ops.CONST, dtypes.bool, arg=False) - c3 = UOp(Ops.MAX, dtypes.float, (c1, c1)) - c4 = UOp(Ops.MUL, dtypes.float, (c1, c1)) - c5 = UOp(Ops.CONST, dtypes.int, arg=-1) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), c2) - self.assertEqual(matcher.rewrite(c3), c3) - self.assertEqual(matcher.rewrite(c4), None) - self.assertEqual(matcher.rewrite(c5), None) - - def test_filter_arg(self): - matcher = PatternMatcher([ - (UPat(Ops.MUL, src=[UPat(Ops.CONST, name="c"), UPat(Ops.CONST, arg=2)], name="x"), - lambda x,c: x if c.arg in {1, -1} else None) - ]) - y1 = UOp(Ops.CONST, dtypes.int, arg=1) - y2 = UOp(Ops.CONST, dtypes.int, arg=2) - y3 = UOp(Ops.CONST, dtypes.int, arg=-1) - c1 = UOp(Ops.MUL, dtypes.int, (y1, y2)) - c2 = UOp(Ops.MUL, dtypes.int, (y2, y2)) - c3 = UOp(Ops.MUL, dtypes.int, (y3, y2)) - c4 = UOp(Ops.MUL, dtypes.int, (y2, y1)) - c5 = UOp(Ops.MUL, dtypes.int, (y2, y3)) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), None) - self.assertEqual(matcher.rewrite(c3), c3) - self.assertEqual(matcher.rewrite(c4), c4) - self.assertEqual(matcher.rewrite(c5), c5) - - def test_dup_name(self): - matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST, name="y"), UPat(Ops.CONST, name="y"))), lambda x, y: x)]) - y1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - y2 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c1 = UOp(Ops.ADD, dtypes.float, (y1, y1)) - c2 = UOp(Ops.ADD, dtypes.float, (y1, y2)) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), c1) - - def test_dtype(self): - matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype=dtypes.float32), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float64, arg=1.0) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), None) - - def test_dtype_set(self): - matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype={dtypes.float32, dtypes.float64}), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float64, arg=1.0) - c3 = UOp(Ops.CONST, dtypes.float16, arg=1.0) - c4 = UOp(Ops.CONST, dtypes.int, arg=1) - self.assertEqual(matcher.rewrite(c1), c1) - self.assertEqual(matcher.rewrite(c2), c2) - self.assertEqual(matcher.rewrite(c3), None) - self.assertEqual(matcher.rewrite(c4), None) - - def test_src_one(self): - matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST), UPat(Ops.CONST))), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) - self.assertEqual(matcher.rewrite(c3), c3) - self.assertEqual(matcher.rewrite(c2), None) - # that CONST/ALU -> ALU/CONST rewrite is now instant - """ - matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST), UPat(GroupOp.ALU))), lambda x: x)]) - c4 = UOp(Ops.ADD, dtypes.float, (c1,c3)) - c5 = UOp(Ops.ADD, dtypes.float, (c3,c1)) - self.assertEqual(matcher.rewrite(c3), None) - self.assertEqual(matcher.rewrite(c4), c4) - self.assertEqual(matcher.rewrite(c5), None) - """ - - def test_src_permutations(self): - matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=[UPat(Ops.CONST), UPat(GroupOp.ALU)]), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) - c4 = UOp(Ops.ADD, dtypes.float, (c3,c2)) - c5 = UOp(Ops.ADD, dtypes.float, (c2,c3)) - c6 = UOp(Ops.ADD, dtypes.float, (c3,c4)) - self.assertEqual(matcher.rewrite(c3), None) - self.assertEqual(matcher.rewrite(c4), c4) - self.assertEqual(matcher.rewrite(c5), c5) - self.assertEqual(matcher.rewrite(c6), None) - - def test_src_repeat(self): - matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=UPat(Ops.CONST)), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) - c4 = UOp(Ops.ADD, dtypes.float, (c2,c3)) - self.assertEqual(matcher.rewrite(c3), c3) - self.assertEqual(matcher.rewrite(c4), None) - - def test_allow_len(self): - matcher = PatternMatcher([(UPat(Ops.MULACC, name="x", src=(UPat(Ops.CONST),), allow_any_len=True), lambda x: x)]) - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - c3 = UOp(Ops.CONST, dtypes.float, arg=3.0) - c4 = UOp(Ops.EXP2, dtypes.float, (c1,)) - c5 = UOp(Ops.ADD, dtypes.float, (c1,c2)) - c6 = UOp(Ops.MULACC, dtypes.float, (c1,c2,c3)) - self.assertEqual(matcher.rewrite(c4), None) - self.assertEqual(matcher.rewrite(c5), None) - self.assertEqual(matcher.rewrite(c6), c6) - - def test_deep_src_permutations(self): - c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) - c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) - u1 = (c1 + c2) + c1 - u2 = (c2 + c1) + c1 - matcher = PatternMatcher([ - (UPat(GroupOp.ALU, src=[UPat(GroupOp.ALU, src=[UPat(name='a'), UPat(name='b')]), UPat(name='b')]), lambda a,b: b) - ]) - self.assertIsNotNone(matcher.rewrite(u1)) - self.assertIsNotNone(matcher.rewrite(u2)) - - def _assert_eq_upat(self, a:UPat, b:UPat): - assert (sorted(map(str,a.op)) if a.op else [] == (sorted(map(str,b.op)) if b.op else [])) - assert (sorted(a.dtype) if a.dtype else [] == (sorted(b.dtype) if b.dtype else [])) - assert (a.name, type(a.src)) == (b.name, type(b.src)) - def simple_src(u:UPat): - if u.src is None: return [] - if isinstance(u.src, itertools.repeat): return next(u.src[0]) - return u.src[0] - for a,b in zip(simple_src(a), simple_src(b)): self._assert_eq_upat(a, b) - -if __name__ == '__main__': - unittest.main(verbosity=2) diff --git a/tinygrad/test/unit/test_qcom.py b/tinygrad/test/unit/test_qcom.py deleted file mode 100644 index 4794cdb1..00000000 --- a/tinygrad/test/unit/test_qcom.py +++ /dev/null @@ -1,73 +0,0 @@ -#!/usr/bin/env python -import unittest -from tinygrad.device import Device, BufferSpec -from tinygrad.dtype import dtypes - -@unittest.skipUnless(Device.DEFAULT == "QCOM", "QCOM device required to run") -class TestQcom(unittest.TestCase): - def test_image_pitch(self): - dev = Device["QCOM"] - - def __validate(imgdt, expected_pitch): - img = dev.allocator.alloc(imgdt.shape[0] * imgdt.shape[1] * 16, options:=BufferSpec(image=imgdt)) - pitch = (img.descriptor[2] & 0x1fffff80) >> 7 - assert pitch == expected_pitch, f"Failed pitch for image: {imgdt}. Got 0x{pitch:X}, expected 0x{expected_pitch:X}" - dev.allocator.free(img, imgdt.shape[0] * imgdt.shape[1] * 16, options) - - __validate(dtypes.imageh((1, 201)), 0x680) - __validate(dtypes.imageh((16, 216)), 0x700) - __validate(dtypes.imageh((16, 9)), 0x80) - __validate(dtypes.imageh((48, 64)), 0x200) - __validate(dtypes.imageh((32, 128)), 0x400) - __validate(dtypes.imageh((96, 128)), 0x400) - __validate(dtypes.imageh((64, 256)), 0x840) - __validate(dtypes.imageh((64, 9)), 0x80) - __validate(dtypes.imageh((192, 256)), 0x840) - __validate(dtypes.imageh((64, 768)), 0x1840) - __validate(dtypes.imageh((256, 49)), 0x1C0) - __validate(dtypes.imageh((128, 9)), 0x80) - __validate(dtypes.imageh((16, 1024)), 0x2080) - __validate(dtypes.imageh((64, 512)), 0x1040) - __validate(dtypes.imageh((16, 512)), 0x1080) - __validate(dtypes.imageh((132, 64)), 0x200) - __validate(dtypes.imageh((4, 512)), 0x1200) - __validate(dtypes.imageh((8, 512)), 0x1100) - __validate(dtypes.imageh((128, 128)), 0x400) - __validate(dtypes.imageh((32, 512)), 0x1040) - __validate(dtypes.imageh((26, 64)), 0x200) - __validate(dtypes.imageh((32, 516)), 0x1040) - __validate(dtypes.imageh((32, 1024)), 0x2040) - __validate(dtypes.imageh((16, 2048)), 0x4080) - __validate(dtypes.imageh((8, 2048)), 0x4100) - __validate(dtypes.imageh((4, 4096)), 0x8200) - - __validate(dtypes.imagef((16, 49)), 0x380) - __validate(dtypes.imagef((16, 1024)), 0x4080) - __validate(dtypes.imagef((256, 64)), 0x400) - __validate(dtypes.imagef((64, 512)), 0x2040) - __validate(dtypes.imagef((16, 512)), 0x2080) - __validate(dtypes.imagef((132, 64)), 0x400) - __validate(dtypes.imagef((4, 512)), 0x2200) - __validate(dtypes.imagef((4, 16)), 0x200) - __validate(dtypes.imagef((2, 16)), 0x400) - __validate(dtypes.imagef((8, 512)), 0x2100) - __validate(dtypes.imagef((12, 64)), 0x400) - __validate(dtypes.imagef((3, 32)), 0x400) - __validate(dtypes.imagef((128, 128)), 0x840) - __validate(dtypes.imagef((32, 512)), 0x2040) - __validate(dtypes.imagef((8, 3072)), 0xC100) - __validate(dtypes.imagef((4, 2048)), 0x8200) - __validate(dtypes.imagef((4, 1024)), 0x4200) - __validate(dtypes.imagef((4, 4096)), 0x10200) - __validate(dtypes.imagef((10, 384)), 0x1900) - __validate(dtypes.imagef((24, 64)), 0x400) - __validate(dtypes.imagef((128, 12)), 0xC0) - __validate(dtypes.imagef((10, 24)), 0x200) - __validate(dtypes.imagef((1, 129)), 0x840) - __validate(dtypes.imagef((1, 32)), 0x200) - __validate(dtypes.imagef((1, 64)), 0x400) - __validate(dtypes.imagef((1, 1239)), 0x4D80) - __validate(dtypes.imagef((1, 1)), 0x40) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_rearrange_einops.py b/tinygrad/test/unit/test_rearrange_einops.py deleted file mode 100644 index faf159b9..00000000 --- a/tinygrad/test/unit/test_rearrange_einops.py +++ /dev/null @@ -1,321 +0,0 @@ -# modified from -# https://github.com/arogozhnikov/einops/blob/master/tests/test_examples.py -# https://github.com/arogozhnikov/einops/blob/master/tests/test_ops.py -# https://github.com/arogozhnikov/einops/blob/master/tests/test_parsing.py - -import numpy as np -import unittest -from tinygrad import Tensor - - -class test_rearrange_examples(unittest.TestCase): - def test1(self): - # transpose - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - y = x.rearrange("b c h w -> b h w c") - assert tuple(y.shape) == (10, 30, 40, 20) - - def test2(self): - # view / reshape - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - y = x.rearrange("b c h w -> b (c h w)") - assert tuple(y.shape) == (10, 20 * 30 * 40) - - def test3(self): - # depth-to-space - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - y = x.rearrange("b (c h1 w1) h w -> b c (h h1) (w w1)", h1=2, w1=2) - assert tuple(y.shape) == (10, 5, 30 * 2, 40 * 2) - - def test4(self): - # space-to-depth - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - y = x.rearrange("b c (h h1) (w w1) -> b (h1 w1 c) h w", h1=2, w1=2) - assert tuple(y.shape) == (10, 20 * 4, 30 // 2, 40 // 2) - - def test5(self): - # simple transposition - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - y = x.rearrange("b1 sound b2 letter -> b1 b2 sound letter") - assert tuple(y.shape) == (10, 30, 20, 40) - - def test6(self): - # parsing parameters - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - t = x.rearrange("b c h w -> (b h w) c") - t = t[:, ::2] # replacement for dot-product, just changes size of second axis - assert tuple(t.shape) == (10 * 30 * 40, 10) - - def test7(self): - x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) - # split of embedding into groups - y1, y2 = x.rearrange("b (c g) h w -> g b c h w", g=2) - assert tuple(y1.shape) == (10, 10, 30, 40) - assert tuple(y2.shape) == (10, 10, 30, 40) - - def test8(self): - x = Tensor(np.arange(10 * 20 * 1 * 1).reshape([10, 20, 1, 1])) - # squeeze - unsqueeze - y = x.rearrange("b c () () -> b c") - assert tuple(y.shape) == (10, 20) - y = y.rearrange("b c -> c b () ()") - assert tuple(y.shape) == (20, 10, 1, 1) - - def test9(self): - x = Tensor(np.arange(10 * 20 * 1 * 1).reshape([10, 20, 1, 1])) - # squeeze - unsqueeze - y = x.rearrange("b c 1 1 -> b c") - assert tuple(y.shape) == (10, 20) - y = y.rearrange("b1 c -> c b1 1 1") - assert tuple(y.shape) == (20, 10, 1, 1) - - def test_tensor_train_example_numpy(self): - # kept here just for a collection, only tested for numpy - # https://arxiv.org/pdf/1509.06569.pdf, (5) - x = Tensor.ones([3, 4, 5, 6]) - rank = 4 - - # creating appropriate Gs - Gs = [Tensor.ones([d, d, rank, rank]) for d in x.shape] - Gs[0] = Gs[0][:, :, :1, :] - Gs[-1] = Gs[-1][:, :, :, :1] - - # einsum way - y = x.reshape((1,) + x.shape) - for G in Gs: - # taking partial results left-to-right - # y = numpy.einsum('i j alpha beta, alpha i ... -> beta ... j', G, y) - y = Tensor(np.einsum("i j a b, a i ... -> b ... j", G.numpy(), y.numpy())) - y1 = y.reshape(-1) - - # alternative way - y = x.reshape(-1) - for G in Gs: - i, j, alpha, beta = G.shape - y = y.rearrange("(i rest alpha) -> rest (alpha i)", alpha=alpha, i=i) - y = y @ G.rearrange("i j alpha beta -> (alpha i) (j beta)") - y = y.rearrange("rest (beta j) -> (beta rest j)", beta=beta, j=j) - y2 = y - assert np.allclose(y1.numpy(), y2.numpy()) - - # yet another way - y = x - for G in Gs: - i, j, alpha, beta = G.shape - y = y.rearrange("i ... (j alpha) -> ... j (alpha i)", alpha=alpha, i=i) - y = y @ G.rearrange("i j alpha beta -> (alpha i) (j beta)") - y3 = y.reshape(-1) - assert np.allclose(y1.numpy(), y3.numpy()) - - -class test_rearrange_ops(unittest.TestCase): - def test_rearrange_errors(self): - x = Tensor.zeros([1, 1, 1, 1, 1]) - x.rearrange("a b c d ... -> a b c ... d") - bad_patterns = [ - "a b c d (...) -> a b c ... d", # collapsed ellipsis on input - "a b (c d ... -> a b c ... d", # unbalanced brackets - "a b* c d ... -> a b c ... d", # not alphanumeric - "a b c d -> a b c d -> a b c d", # two "->" - "a ... c ... -> ... a ... c", # two "..." - "a b c d e -> f b c d e", # name mismatch - ] - for pattern in bad_patterns: - with self.assertRaises(AssertionError): - x.rearrange(pattern) - - x.rearrange("... -> (...)") - with self.assertRaises(AssertionError): - x.rearrange("(...) -> (...)") - - y = Tensor.zeros([8, 1]) - y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2, a2=2) - with self.assertRaises(RuntimeError): - ## should fail as not enough dimensions specified - y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2) - with self.assertRaises(ValueError): - ## should fail as 6 does not divide 8 - y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=3, a2=2) - with self.assertRaises(AssertionError): - ## incorrect dimension provided for an axis that is only permuted - y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2, a2=2, b=2) - with self.assertRaises(AssertionError): - ## unused axis provided - y.rearrange("(a b c) d -> a b c d", b=2, c=2, e=2) - - def test_rearrange_ellipsis_ops(self): - identity_patterns = [ - "...->...", - "a b c d e-> a b c d e", - "a b c d e ...-> ... a b c d e", - "a b c d e ...-> a ... b c d e", - "... a b c d e -> ... a b c d e", - "a ... e-> a ... e", - "a ... -> a ... ", - "a ... c d e -> a (...) c d e", - ] - - equivalent_rearrange_patterns = [ - ("a b c d e -> (a b) c d e", "a b ... -> (a b) ... "), - ("a b c d e -> a b (c d) e", "... c d e -> ... (c d) e"), - ("a b c d e -> a b c d e", "... -> ... "), - ("a b c d e -> (a b c d e)", "... -> (...)"), - ("a b c d e -> b (c d e) a", "a b ... -> b (...) a"), - ("a b c d e -> b (a c d) e", "a b ... e -> b (a ...) e"), - ] - - xnp = np.arange(2 * 3 * 4 * 5 * 6).reshape([2, 3, 4, 5, 6]) - x = Tensor(xnp) - for pattern in identity_patterns: - assert np.array_equal(xnp, x.rearrange(pattern).numpy()), pattern - - for pattern1, pattern2 in equivalent_rearrange_patterns: - assert np.array_equal(x.rearrange(pattern1).numpy(), x.rearrange(pattern2).numpy()) - - def test_rearrange_consistency(self): - shape = [1, 2, 3, 5, 7, 11] - xnp = np.arange(np.prod(shape)).reshape(shape) - x = Tensor(xnp) - for pattern in [ - "a b c d e f -> a b c d e f", - "b a c d e f -> a b d e f c", - "a b c d e f -> f e d c b a", - "a b c d e f -> (f e) d (c b a)", - "a b c d e f -> (f e d c b a)", - ]: - result = x.rearrange(pattern).numpy() - assert len(np.setdiff1d(xnp, result)) == 0 - assert result.dtype == xnp.dtype - - result = x.rearrange("a b c d e f -> a (b) (c d e) f").numpy() - assert np.array_equal(xnp.flatten(), result.flatten()) - - result = x.rearrange("a aa aa1 a1a1 aaaa a11 -> a aa aa1 a1a1 aaaa a11").numpy() - assert np.array_equal(xnp, result) - - result1 = x.rearrange("a b c d e f -> f e d c b a").numpy() - result2 = x.rearrange("f e d c b a -> a b c d e f").numpy() - assert np.array_equal(result1, result2) - - result = x.rearrange("a b c d e f -> (f d) c (e b) a").rearrange("(f d) c (e b) a -> a b c d e f", b=2, d=5).numpy() - assert np.array_equal(xnp, result) - - sizes = dict(zip("abcdef", shape)) - temp = x.rearrange("a b c d e f -> (f d) c (e b) a", **sizes) - result = temp.rearrange("(f d) c (e b) a -> a b c d e f", **sizes).numpy() - assert np.array_equal(xnp, result) - - x2 = np.arange(2 * 3 * 4).reshape([2, 3, 4]) - result = Tensor(x2).rearrange("a b c -> b c a").numpy() - assert x2[1, 2, 3] == result[2, 3, 1] - assert x2[0, 1, 2] == result[1, 2, 0] - - def test_rearrange_permutations(self): - # tests random permutation of axes against two independent numpy ways - for n_axes in range(1, 10): - x = np.arange(2**n_axes).reshape([2] * n_axes) - permutation = np.random.permutation(n_axes) - left_expression = " ".join("i" + str(axis) for axis in range(n_axes)) - right_expression = " ".join("i" + str(axis) for axis in permutation) - expression = left_expression + " -> " + right_expression - result = Tensor(x).rearrange(expression).numpy() - - for pick in np.random.randint(0, 2, [10, n_axes]): - assert x[tuple(pick)] == result[tuple(pick[permutation])] - - for n_axes in range(1, 10): - x = np.arange(2**n_axes).reshape([2] * n_axes) - permutation = np.random.permutation(n_axes) - left_expression = " ".join("i" + str(axis) for axis in range(n_axes)[::-1]) - right_expression = " ".join("i" + str(axis) for axis in permutation[::-1]) - expression = left_expression + " -> " + right_expression - result = Tensor(x).rearrange(expression).numpy() - assert result.shape == x.shape - expected_result = np.zeros_like(x) - for original_axis, result_axis in enumerate(permutation): - expected_result |= ((x >> original_axis) & 1) << result_axis - - assert np.array_equal(result, expected_result) - -def check_expression_helper(expression: str): - Tensor.ones((1, 2, 3, 4, 5, 6, 7)) - -class test_rearrange_parsing(unittest.TestCase): - def test_elementary_axis_name(self): - for name in [ - "a", - "b", - "h", - "dx", - "h1", - "zz", - "i9123", - "somelongname", - "Alex", - "camelCase", - "u_n_d_e_r_score", - "unreasonablyLongAxisName", - ]: - Tensor.ones((1,)).rearrange(f"{name} -> {name}") - - for name in ["2b", "12", "_startWithUnderscore", "endWithUnderscore_", "_"]: - with self.assertRaises(AssertionError): - Tensor.ones((1,)).rearrange(f"{name} -> {name}") - - with self.assertRaises(RuntimeError): - Tensor.ones((1,)).rearrange(" -> ") - - def test_invalid_expressions(self): - # double ellipsis should raise an error - def _test_expression(expression: str): - Tensor.ones((2, 3, 4, 5, 6)).rearrange(f"{expression} -> {expression}") - - _test_expression("... a b c d") - with self.assertRaises(AssertionError): - _test_expression("... a b c d ...") - with self.assertRaises(AssertionError): - _test_expression("... a b c (d ...)") - with self.assertRaises(AssertionError): - _test_expression("(... a) b c (d ...)") - - # double/missing/enclosed parenthesis - Tensor.ones((2, 3, 4, 5, 6)).rearrange("a b c d ... -> (a) b c (d ...)") - with self.assertRaises(AssertionError): - _test_expression("(a)) b c (d ...)") - with self.assertRaises(AssertionError): - _test_expression("(a b c (d ...)") - with self.assertRaises(AssertionError): - _test_expression("(a) (()) b c (d ...)") - with self.assertRaises(AssertionError): - _test_expression("(a) ((b c) (d ...))") - - # invalid identifiers - _test_expression("camelCase under_scored cApiTaLs ß ...") - with self.assertRaises(AssertionError): - _test_expression("1a") - with self.assertRaises(AssertionError): - _test_expression("_pre") - with self.assertRaises(AssertionError): - _test_expression("...pre") - with self.assertRaises(AssertionError): - _test_expression("pre...") - - def test_unicode_ellipsis(self): - equivalent_rearrange_patterns = [ - ("a b … -> (a b) … ", "a b ... -> (a b) ... "), - ("… c d e -> … (c d) e", "... c d e -> ... (c d) e"), - ("… -> … ", "... -> ... "), - ("… -> (…)", "... -> (...)"), - ("a b … -> b (…) a", "a b ... -> b (...) a"), - ("a b … e -> b (a …) e", "a b ... e -> b (a ...) e"), - ] - - xnp = np.arange(2 * 3 * 4 * 5 * 6).reshape([2, 3, 4, 5, 6]) - x = Tensor(xnp) - - for pattern1, pattern2 in equivalent_rearrange_patterns: - assert np.array_equal(x.rearrange(pattern1).numpy(), x.rearrange(pattern2).numpy()) - - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_rewrite_map.py b/tinygrad/test/unit/test_rewrite_map.py deleted file mode 100644 index 0eed9477..00000000 --- a/tinygrad/test/unit/test_rewrite_map.py +++ /dev/null @@ -1,202 +0,0 @@ -import unittest -from tinygrad import dtypes -from tinygrad.uop.ops import UOp, graph_rewrite_map, _substitute -from tinygrad.codegen.symbolic import symbolic - -class TestRewriteMap(unittest.TestCase): - def test_substitute(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - c = UOp.variable('c', 0, 10) - e = UOp.variable('e', 0, 10) - ret = (a+b)*c - sub = {a+b: e} - sub_map = graph_rewrite_map(ret, _substitute, sub, bottom_up=True) - self.assertIs(sub_map[a+b], e) - self.assertIs(sub_map[(a+b)*c], e*c) - - def test_substitute_depth_2(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - c = UOp.variable('c', 0, 10) - d = UOp.variable('d', 0, 10) - e = UOp.variable('e', 0, 10) - f = UOp.variable('f', 0, 10) - ret = (a+b)*c+d - sub = {a+b: e, (a+b)*c: f} - sub_map = graph_rewrite_map(ret, _substitute, sub, bottom_up=True) - self.assertIs(sub_map[a+b], e) - self.assertIs(sub_map[(a+b)*c], f) - - def test_multistage_substitute(self): - a = UOp.variable('a', 0, 10) - b = UOp.variable('b', 0, 10) - c = UOp.variable('c', 0, 10) - d = UOp.variable('d', 0, 10) - sub1 = {a+b:c} - start = (a+b)*c - # stage 1: (a+b)*c -> c*c - sub_map1 = graph_rewrite_map(start, _substitute, sub1, bottom_up=True) - self.assertIs(sub_map1[(a+b)*c], c*c) - # stage 2: c*c -> d - sub2 = {c*c:d} - sub_map2 = graph_rewrite_map(sub_map1[start], _substitute, sub2, input_map=sub_map1, bottom_up=True) - # (a+b)*c -> c*c -> d - self.assertIs(sub_map2[(a+b)*c], d) - - def test_add_zero(self): - # Build a small graph: add(0, add(const=0, const=5)) - zero_node = UOp.const(dtypes.int, 0) - five_node = UOp.const(dtypes.int, 5) - inner_add = zero_node + five_node - root_add = zero_node + inner_add - - # Perform top-down rewrite - node_map = graph_rewrite_map(root_add, symbolic) - - # We expect that add(0, add(0, 5)) -> add(0, 5) -> 5 - # Check the mapping - assert node_map[root_add] == five_node - assert node_map[inner_add] == five_node - # zero_node and five_node map to themselves - assert node_map[zero_node] == zero_node - assert node_map[five_node] == five_node - - def test_double_neg(self): - """ - Test rewriting neg(neg(5)) => 5 using symbolic. - """ - # In some versions of TinyGrad, you might do: (-(-five_node)) - five_node = UOp.const(dtypes.int, 5) - # If your code allows UOp(...), do that; else you might do something like: - # double_neg_five = -(-five_node) - # But let's be explicit: - neg_five = -five_node - double_neg_five = -neg_five - - node_map = graph_rewrite_map(double_neg_five, symbolic) - - # node_map should map double_neg_five -> five_node - self.assertEqual(node_map[double_neg_five], five_node) - # five_node maps to itself - self.assertEqual(node_map[five_node], five_node) - - def test_add_zero_and_double_neg(self): - """ - Combine both rewrites: add(0, neg(neg(5))) => add(0, 5) => 5 - """ - zero_node = UOp.const(dtypes.int, 0) - five_node = UOp.const(dtypes.int, 5) - neg_five = -five_node - double_neg_five = -neg_five - root_add = zero_node + double_neg_five - - node_map = graph_rewrite_map(root_add, symbolic) - - # node_map: root_add -> five_node, double_neg_five -> five_node - self.assertEqual(node_map[root_add], five_node) - self.assertEqual(node_map[double_neg_five], five_node) - # zero_node, five_node map to themselves - self.assertEqual(node_map[zero_node], zero_node) - self.assertEqual(node_map[five_node], five_node) - - def test_multi_var_rewrites(self): - x_var = UOp.variable('x', 0, 10) - y_var = UOp.variable('y', -5, 5) - zero_node = UOp.const(dtypes.int, 0) - - sum_with_zero = y_var + zero_node # (y + 0) - combined = x_var + sum_with_zero # x + (y + 0) - double_neg = -(-combined) # neg(neg(x + y)) - final_expr = zero_node + double_neg # 0 + (x + y) - - node_map = graph_rewrite_map(final_expr, symbolic) - - # The final root should be (x_var + y_var). - expected = x_var + y_var - - # Each sub-expression has its own "final" result. - # (y + 0) -> y_var - self.assertEqual(node_map[sum_with_zero], y_var) - # (x + (y+0)) -> (x + y) - self.assertEqual(node_map[combined], expected) - # neg(neg(x+y)) -> (x + y) - self.assertEqual(node_map[double_neg], expected) - # 0 + (x+y) -> (x + y) - self.assertEqual(node_map[final_expr], expected) - - # x_var, y_var, zero_node remain unchanged - self.assertEqual(node_map[x_var], x_var) - self.assertEqual(node_map[y_var], y_var) - self.assertEqual(node_map[zero_node], zero_node) - - def test_complex_multi_var_edges(self): - """ - Build a multi-variable expression with multiple intermediates: - - x_var = UOp.variable('x', 1, 10) - y_var = UOp.variable('y', -5, 5) - z_var = UOp.variable('z', 0, 5) - zero_node = UOp.const(dtypes.int, 0) - one_node = UOp.const(dtypes.int, 1) - - yz_sum = y_var + z_var - yz_sum_zero = yz_sum + zero_node -> rewrites to yz_sum - yz_neg = -yz_sum_zero -> -(y+z) - yz_dneg = -yz_neg -> y+z (double neg gone) - x_plus_yz = x_var + yz_dneg -> x + (y+z) - double_neg_x = -(-x_plus_yz) -> x + (y+z) - final_expr = double_neg_x * one_node -> x + (y+z) - - We expect the final result to be (x + (y+z)). - Each original node should map to the final node that replaces it, - which might be structurally equivalent but not the same reference. - """ - x_var = UOp.variable('x', 1, 10) - y_var = UOp.variable('y', -5, 5) - z_var = UOp.variable('z', 0, 5) - zero_node = UOp.const(dtypes.int, 0) - one_node = UOp.const(dtypes.int, 1) - - # Build sub-expressions - yz_sum = y_var + z_var # (y + z) - yz_sum_zero = yz_sum + zero_node # (y + z) + 0 - yz_neg = -yz_sum_zero # -(y+z) - yz_dneg = -yz_neg # -(-(y+z)) -> (y+z) - x_plus_yz = x_var + yz_dneg # x + (y+z) - double_neg_x = -(-x_plus_yz) # neg(neg(x+(y+z))) -> x+(y+z) - final_expr = double_neg_x * one_node # (x+(y+z)) * 1 -> x+(y+z) - - node_map = graph_rewrite_map(final_expr, symbolic) - - # (y + z) is unchanged - self.assertEqual(node_map[yz_sum], yz_sum) - - # (y+z) + 0 => (y+z) - self.assertEqual(node_map[yz_sum_zero], yz_sum) - - # -(y+z) remains -(y+z), but might be a new UOp with updated children - # Compare structurally to -(y_var + z_var). - self.assertEqual(node_map[yz_neg], -yz_sum) - - # -(-(y+z)) => (y+z) - self.assertEqual(node_map[yz_dneg], yz_sum) - - # x + (y+z) => might get recreated if yz_dneg was changed, so compare to x + yz_sum - self.assertEqual(node_map[x_plus_yz], x_var + yz_sum) - - # -(-(x+(y+z))) => x + (y+z) - self.assertEqual(node_map[double_neg_x], x_var + yz_sum) - - # (x+(y+z)) * 1 => x+(y+z) - self.assertEqual(node_map[final_expr], x_var + yz_sum) - - # Unchanged atomic nodes map to themselves - self.assertEqual(node_map[x_var], x_var) - self.assertEqual(node_map[y_var], y_var) - self.assertEqual(node_map[z_var], z_var) - self.assertEqual(node_map[zero_node], zero_node) - self.assertEqual(node_map[one_node], one_node) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_rewrite_tracked_childen.py b/tinygrad/test/unit/test_rewrite_tracked_childen.py deleted file mode 100644 index 688e2efa..00000000 --- a/tinygrad/test/unit/test_rewrite_tracked_childen.py +++ /dev/null @@ -1,63 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad.uop.ops import PatternMatcher, Ops, UPat, graph_rewrite, RewriteContext, UOp -from tinygrad.engine.grouper import sym, merge_views - -class TestRewriteTrackedChildren(unittest.TestCase): - @unittest.skip("track_children no longer supported") - def test_children_in_context(self): - def print_children(ctx:RewriteContext, sink:UOp): - view_w_child = sink.src[0].src[0].src[0] - assert view_w_child.op is Ops.VIEW - assert set([x.arg for x in ctx.children[view_w_child]]) == set((2,3)) - ctx.update_children() - assert set([x.arg for x in ctx.children[view_w_child]]) == set((3,4)) - # this is the 3 - assert len(ctx.children[sink.src[0].src[1]]) == 1 - assert next(iter(ctx.children[sink.src[0].src[1]])).op is Ops.ADD - # this is the 4 - assert len(ctx.children[sink.src[0].src[0]]) == 1 - assert next(iter(ctx.children[sink.src[0].src[0]])).op is Ops.ADD - rewrite = PatternMatcher([ - (UPat(Ops.CONST, arg=2, name="x"), lambda x: x.replace(arg=4)), - (UPat(Ops.SINK, name="sink"), print_children) - ]) - a = Tensor(2) - b = Tensor(3) - c = a + b - sink = c.uop.sink() - sink = graph_rewrite(sink, rewrite, track_children=True) - - def test_simple_child(self): - rewrite = PatternMatcher([ - (UPat(Ops.CONST, arg=2, name="x"), lambda x: x.replace(arg=4)), - ]) - a = Tensor(2) - b = Tensor(3) - c = a + b - sink = c.uop - view_w_child = a.uop.src[0] - print([x().arg for x in view_w_child.children]) - print([x.arg for x in sink.get_children_map()[view_w_child]]) - self.assertSetEqual(set([x.arg for x in sink.get_children_map()[view_w_child]]), set((2,3))) - # children can either be added to or removed from the map with graph_rewrite - # added to is easy to detect, just hook the UOp constructor - # when are children removed? - # * if a rewrite rule returns a UOp, the matched node is removed from the graph - sink = graph_rewrite(sink, rewrite) - print([x().arg for x in view_w_child.children]) - print([x.arg for x in sink.get_children_map()[view_w_child]]) - self.assertSetEqual(set([x.arg for x in sink.get_children_map()[view_w_child]]), set((3,4))) - - @unittest.skip("track_children no longer supported") - def test_child_after_parent_update(self): - def print_children(ctx, r): - ctx.update_children() - print(ctx.children[r]) - extra = PatternMatcher([(UPat(Ops.REDUCE_AXIS, name="r"), print_children)]) - a = Tensor.empty(3, 3) - r = (a+0).sum() - graph_rewrite(r.uop, merge_views+sym+extra, track_children=True) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_search.py b/tinygrad/test/unit/test_search.py deleted file mode 100644 index d6d4e4be..00000000 --- a/tinygrad/test/unit/test_search.py +++ /dev/null @@ -1,11 +0,0 @@ -import unittest -from tinygrad.engine.search import get_test_global_size - -class TestSearchUtil(unittest.TestCase): - def test_get_test_global_size(self): - self.assertEqual(get_test_global_size([256, 256, 256], 65536, {}), ([256, 16, 16], 256.0)) - self.assertEqual(get_test_global_size([65536, 1, 1], 256, {}), ([256, 1, 1], 256.0)) - self.assertEqual(get_test_global_size([77, 1, 1], 16, {}), ([9, 1, 1], 77/9)) - -if __name__ == "__main__": - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/unit/test_shapetracker.py b/tinygrad/test/unit/test_shapetracker.py deleted file mode 100644 index 23fda925..00000000 --- a/tinygrad/test/unit/test_shapetracker.py +++ /dev/null @@ -1,917 +0,0 @@ -#!/usr/bin/env python -import unittest -import numpy as np -from tinygrad.dtype import dtypes -from tinygrad.helpers import prod -from tinygrad.shape.shapetracker import ShapeTracker, View -from tinygrad import Variable -from tinygrad.uop.ops import UOp, Ops, graph_rewrite -from tinygrad.codegen.devectorizer import sym -from itertools import product - -def shapetracker_getitem(st:ShapeTracker, val:int): - idx, valid = st.reshape((st.size,)).to_indexed_uops([UOp.const(dtypes.int, val)]) - idx, valid = graph_rewrite(idx, sym), graph_rewrite(valid, sym) - assert idx.op is Ops.CONST and valid.op is Ops.CONST - return idx.arg, valid.arg - -class CheckingShapeTracker: - def __init__(self, shape): - self.st = ShapeTracker.from_shape(shape) - self.t = np.arange(prod(shape), dtype=np.int32).reshape(shape) - - @property - def shape(self): - return self.t.shape - - def simplify(self): - self.st = self.st.simplify() - return self - - def reshape(self, new_shape): - self.st = self.st.reshape(new_shape) - self.t = self.t.reshape(new_shape) - return self - - def permute(self, axis): - self.st = self.st.permute(axis) - self.t = np.transpose(self.t, axis) - return self - - def expand(self, new_shape): - self.st = self.st.expand(new_shape) - self.t = np.broadcast_to(self.t, new_shape) - return self - - def flip(self, arg): - self.st = self.st.flip(arg) - self.t = np.flip(self.t, tuple(i for i in range(len(arg)) if arg[i])) - return self - - def shrink(self, arg): - self.st = self.st.shrink(arg) - self.t = self.t[tuple([slice(x[0], x[1]) for x in arg])] - return self - - def pad(self, arg): - self.st = self.st.pad(arg) - self.t = np.pad(self.t, arg, constant_values=-1) - return self - - def __getitem__(self, val): - return self.t.flatten()[val] - - @property - def views(self): return self.st.views - - @property - def contiguous(self): return self.st.contiguous - - def assert_same(self): - x = [(v[0] if (v:=shapetracker_getitem(self.st, i))[1] else -1) for i in range(prod(self.st.shape))] - y = [self[i] for i in range(prod(self.shape))] - assert self.st.shape == self.shape - assert x == y, f"mismatch shapetracker:{x} real:{y}" - -@unittest.skip("don't create shapetrackers with views") -class TestRealIssues(unittest.TestCase): - def test_reshape_doesnt_multiview(self): - self.st = ShapeTracker((View.create((256, 256, 2, 2, 2, 2, 2, 256, 8, 2), (0, 8, 0, 4, 0, 0, 2, 16384, 2048, 1), 0, None),)) - self.st.reshape((128, 2, 256, 2, 2, 2, 2, 2, 256, 8, 2)) - assert len(self.st.views) == 1 - - def test_reshape_stable_diffusion(self): - # regression test for https://github.com/tinygrad/tinygrad/pull/2616 - st = ShapeTracker((View((2, 1920, 32, 32), (1310720, 1024, 32, 1), 0, ((0, 2), (0, 1280), (0, 32), (0, 32)), False),)) - st = st.reshape((2, 32, 240, 256)) - assert len(st.views) == 2 - - def test_reshape_trailing_invalid_ones(self): - st = ShapeTracker((View(shape=(1, 1, 5), strides=(0, 0, 1), offset=-5, mask=((1, 1), (0, 1), (0, 5)), contiguous=False),)) - st = st.reshape((5,)) - assert len(st.views) == 1 - assert st.views[0].mask == ((0,0),) - -class TestRealDoesntSimplify(unittest.TestCase): - def tearDown(self): - st = self.st.real_strides() - print(st) - self.st = self.st.simplify() - assert len(self.st.views) != 1 - assert None in st - - def test_1(self): - self.st = ShapeTracker(( - View.create((8, 3, 1, 2, 11, 1), (33, 11, 0, 0, 1, 0), 0, None), - View.create((8, 6, 11), (66, 11, 1), 0, None))) - self.assertEqual(self.st.real_strides(), (33, None, 1)) - - def test_2(self): - self.st = ShapeTracker(( - View.create((2, 2, 4, 3, 3), (72, 9, 18, -3, -1), 8, None), - View.create((4, 4, 3, 3), (36, 9, 3, 1), 0, None))) - self.assertEqual(self.st.real_strides(), (None, 18, -3, -1)) - -class TestRealStrides(unittest.TestCase): - def test_1(self): - st = ShapeTracker(( - View.create((2048,), (1,), 0, ((0, 512),)), - View.create((16, 32, 4), (128, 4, 1), 0, None), - )) - self.assertEqual(st.real_strides(), (None, 4, 1)) - - def test_2(self): - # test/test_ops.py::TestOps::test_simple_padding_conv1d - st = ShapeTracker(( - View.create((6, 2, 5, 14), (90, 45, 1, 5), 0, ((0, 6), (0, 2), (0, 5), (0, 9))), - View.create((6, 2, 78), (140, 70, 1), 0, ((0, 6), (0, 2), (0, 70))), - View.create((6, 2, 13, 6), (156, 78, 1, 13), 0, None), - )) - self.assertEqual(st.real_strides(), (90, 45, None, None)) - - def test_3(self): - # test/test_ops.py::TestOps::test_simple_cumsum - st = ShapeTracker(( - View.create((4, 256, 512), (256, 0, 1), 0, ((0, 4), (0, 256), (0, 256))), - View.create((4, 131327), (131072, 1), 0, ((0, 4), (0, 131072))), - View.create((4, 511, 257), (131327, 1, 511), 0, None), - )) - self.assertEqual(st.real_strides(), (256, None, None)) - - def test_4(self): - # test/test_nn.py::TestNN::test_conv_transpose1d - st = ShapeTracker(( - View.create((4, 16, 56, 2), (896, 56, 1, 0), 0, ((0, 4), (0, 16), (0, 56), (0, 1))), - View.create((1, 4, 1, 16, 8, 121), (0, 1792, 0, 112, 0, 1), -5, ((0, 1), (0, 4), (0, 1), (0, 16), (0, 8), (5, 116))), - View.create((4, 64, 115, 16, 7), (15488, 0, 1, 968, 122), 0, None), - )) - self.assertEqual(st.real_strides(), (896, 0, None, 56, None)) - - def test_5(self): - # test/test_ops.py::TestOps::test_conv2d - st = ShapeTracker(( - View.create((1, 3, 1, 12, 2, 8), (0, 132, 0, 12, 1, 2), 0, ((0, 1), (0, 3), (0, 1), (0, 11), (0, 2), (0, 6))), - View.create((1, 3, 22, 21), (0, 192, 16, 1), 0, ((0, 1), (0, 3), (0, 12), (0, 16))), - View.create((3, 11, 7, 2, 3), (462, 21, 1, 231, 7), 0, None), - )) - self.assertEqual(st.real_strides(), (132, None, None, None, None)) - -class TestRealSimplifies(unittest.TestCase): - def tearDown(self): - st = self.st.real_strides() - self.st = self.st.simplify() - assert len(self.st.views) == 1 - print(self.st.views[-1].strides, st) - self.assertEqual(self.st.views[-1].strides, st) - - def test_1(self): - self.st = ShapeTracker(( - View.create((1, 3, 2, 11, 4, 28), (0, 308, 0, 28, 0, 1), 0, None), - View.create((1, 3, 2, 11, 26, 1, 1, 3), (0, 2464, 0, 112, 1, 0, 0, 29), 0, None))) - - def test_2(self): - self.st = ShapeTracker(( - View.create((8, 3, 3, 11, 2, 28), (924, 308, 0, 28, 0, 1), 0, None), - View.create((8, 1, 6, 10, 28, 3, 2, 1), (5544, 0, 0, 56, 1, 1848, 672, 0), 0, None))) - -class TestViewMinify(unittest.TestCase): - def test_minifies(self): - assert len(View.create((10,10)).minify().shape) == 1 - assert len(View.create((10,10)).permute((1,0)).minify().shape) == 2 - assert len(View.create((10,10,10,10)).permute((1,0,2,3)).minify().shape) == 3 - -class TestIndexExpressions2d(unittest.TestCase): - def setUp(self): - shapes = [(30, 5), (15, 10), (15, 1), (5, 10), (5, 1)] # Make sure dim0 is a multiple of 5, one of the tests divides this dimension by 5 - offsets = [0, 1, 15, 28, 10000] - self.sts = [ShapeTracker.from_shape((prod(base_shape)+offset,)).shrink(((offset, offset+prod(base_shape)),)).\ - reshape(base_shape) for base_shape in shapes for offset in offsets] - self.offset = [offset for base_shape in shapes for offset in offsets] - self.shapes = [shape for shape in shapes for offset in offsets] - self.idxs_exprs = [] - - def tearDown(self): - for st, offset, shape, idxs_expr in zip(self.sts, self.offset, self.shapes, self.idxs_exprs): - numel = prod(shape) - self.check_bounds(idxs_expr(self.default_idxs(st.shape)), offset, numel) - idx0s = [(0,0), (0, min(1, st.shape[0]-1)), (0, st.shape[0]-1), (min(3, st.shape[0]-1), min(6, st.shape[0]-1)), (st.shape[0]-1, st.shape[0]-1)] - idx1s = [(0,0), (0, min(1, st.shape[1]-1)), (0, st.shape[1]-1), (min(3, st.shape[1]-1), min(6, st.shape[1]-1)), (st.shape[1]-1, st.shape[1]-1)] - idx2s = [(0,0), (0, min(1, st.shape[2]-1)), (0, st.shape[2]-1), (min(3, st.shape[2]-1), min(6, st.shape[2]-1)), - (st.shape[2]-1, st.shape[2]-1)] if len(st.shape) == 3 else [None for _ in idx0s] - for idx0, idx1, idx2 in product(idx0s, idx1s, idx2s): - idxs = [Variable(f"idx{i}", idx[0], idx[1]) for i, idx in enumerate((idx0, idx1, idx2)) if idx is not None] - self.check_bounds(idxs_expr(idxs), offset, numel) - - def default_idx(self, shape): - return Variable("idx", 0, prod(shape)-1) - - def default_idxs(self, shape): - return [Variable(f"idx{i}", 0, d-1) for i,d in enumerate(shape)] - - def check_bounds(self, expr, offset, numel): - assert expr.vmin >= offset - assert expr.vmax <= offset + numel - 1 - - def test_noop(self): - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[1] + offset) - - def test_permute(self): - new_st = [] - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - st = st.permute((1, 0)) - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0] + idxs[1]*base_shape[1] + offset) - new_st.append(st) - self.sts = new_st - - def test_reshape(self): - new_st = [] - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - st = st.reshape((base_shape[0], 1, base_shape[1])) - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[2] + offset) - new_st.append(st) - self.sts = new_st - - def test_reshape_expand(self): - new_st = [] - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - st = st.reshape((base_shape[0], 1, base_shape[1])) - st = st.expand((base_shape[0], base_shape[1], base_shape[1])) - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[2] + offset) - new_st.append(st) - self.sts = new_st - - def test_permute_reshape_1(self): # This tests multiple views - new_st = [] - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - st = st.permute((1, 0)) - st = st.reshape((base_shape[0]//5, 1, base_shape[1]*5)) - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: (idxs[0]*(base_shape[1]*5)+idxs[2])%base_shape[0]*base_shape[1] + \ - (idxs[0]*(base_shape[1]*5)+idxs[2])//base_shape[0] + offset) - new_st.append(st) - self.sts = new_st - - def test_permute_reshape_2(self): - new_st = [] - for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): - st = st.permute((1, 0)) - st = st.reshape((1, base_shape[0]//5, base_shape[1]*5)) - self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: (idxs[1]*(base_shape[1]*5)+idxs[2])%base_shape[0]*base_shape[1] + \ - (idxs[1]*(base_shape[1]*5)+idxs[2])//base_shape[0] + offset) - new_st.append(st) - self.sts = new_st - - def test_reshaping_splitting(self): - self.st = CheckingShapeTracker((5,10,5,10)) - self.st.permute((1, 0, 3, 2)) - self.st.pad(((0,0), (0,5), (0,0), (0,5))) - self.st.reshape((10,2,5,10,2,5)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_splitting_1(self): - self.st = CheckingShapeTracker((1,10,1)) - self.st.pad(((0,4),(0,0),(1,0))) - self.st.reshape((5,5,2,2)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_combining_1(self): - self.st = CheckingShapeTracker((2,1,10)) - self.st.pad(((2,6), (0,0), (0,0))) - self.st.reshape((100,)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_combining_2(self): - self.st = CheckingShapeTracker((1,1,5)) - self.st.pad(((3,6), (0,0), (0,5))) - self.st.reshape((100,)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_combining_3(self): - self.st = CheckingShapeTracker((1,1,4)) - self.st.pad(((3,6), (0,0), (1,5))) - self.st.reshape((100,)) - assert len(self.st.views) == 1 - assert self.st.views[0].mask[0] == (31, 35) - self.st.assert_same() - - def test_reshape_combining_4(self): - # interestingly this one is quite slow - self.st = CheckingShapeTracker((1,1,5,5,1,1,5)) - self.st.pad(((2,1), (0,0), (0,2), (0,0), (2,1), (0,0), (0,2))) - self.st.reshape((28,5,28)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_splitting_combining(self): - self.st = CheckingShapeTracker((1,5,5)) - self.st.pad(((0,4), (0,5), (0,0))) - self.st.reshape((10,25)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_reshape_only_1s(self): - self.st = CheckingShapeTracker((1, 1, 1, 4, 1, 3, 5, 1)) - self.st.pad(((0,4), (0,0), (0,0), (1,1), (0,0), (0,0), (0,0), (0,0))) - self.st.reshape((5, 6, 3, 5)) - assert len(self.st.views) == 1 - self.st.assert_same() - self.st.reshape((1, 1, 5, 6, 3, 5, 1, 1)) - assert len(self.st.views) == 1 - self.st.assert_same() - self.st.reshape((1, 5, 6, 1, 3, 1, 5, 1)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_zero_mask_1(self): - self.st = CheckingShapeTracker((1, 3, 2)) - self.st.pad(((0,0), (0,3), (0,0))) - self.st.shrink(((0,1), (3,6), (0,2))) - self.st.reshape((3,2)) - assert len(self.st.views) == 1 - self.st.assert_same() - self.st.reshape((1, 3, 1, 2, 1)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_zero_mask_2(self): - self.st = CheckingShapeTracker((1, 3, 2)) - self.st.pad(((0,2), (0,3), (0,0))) - self.st.shrink(((2,3), (3,6), (0,2))) - self.st.reshape((3,2)) - assert len(self.st.views) == 1 - self.st.assert_same() - self.st.reshape((1, 3, 1, 2, 1)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_expanded_reshaped(self): - self.st = CheckingShapeTracker((1, 3, 2, 1)) - self.st.expand((5, 3, 2, 2)) - self.st.pad(((0,0), (0,3), (0,0), (0, 0))) - self.st.reshape((5, 2, 3, 2, 2)) - assert len(self.st.views) == 1 - self.st.assert_same() - - def test_splitting_big(self): - self.st = CheckingShapeTracker((1, 5, 1, 15, 1)) - self.st.pad(((0,0), (0,5), (0,0), (0,15), (0,0))) - self.st.reshape((10, 1, 30)) - self.st.permute((2,1,0)) - self.st.reshape((2,3,5,2,5)) - assert len(self.st.views) == 1 - v = self.st.views[-1] - assert v.strides == (0, 5, 1, 0, 15) and v.mask == ((0, 1), (0, 3), (0, 5), (0, 1), (0, 5)) - self.st.assert_same() - - def test_combining_big(self): - self.st = CheckingShapeTracker((1,3,1,5,3,1)) - self.st.pad(((0,0),(2,2),(0,0),(0,0),(0,0),(0,0))) - self.st.reshape((1,1,1,105,1,1)) - assert len(self.st.views) == 1 - v = self.st.views[-1] - assert v.strides == (0, 0, 0, 1, 0, 0) and v.mask == ((0, 1), (0, 1), (0, 1), (30, 75), (0, 1), (0, 1)) and v.offset == -30 - self.st.assert_same() - - def test_pad_reshape(self): - self.st = CheckingShapeTracker((4,)) - self.st.pad(((2,2),)) - self.st.reshape((4,2)) - assert len(self.st.views) == 1 - self.st.assert_same() - -class TestSimplifyingShapeTracker(unittest.TestCase): - def setUp(self): - self.st = CheckingShapeTracker((1, 10)) - - def tearDown(self): - self.st.assert_same() - - # multiview simplify - def test_expand_contract_simple(self): - self.st = self.st.expand((10, 10)) - self.st = self.st.reshape((100,)) - print(self.st.views) - assert (len(self.st.views) == 2) - self.st = self.st.reshape((10, 10)) - print(self.st.views) - - self.st = self.st.simplify() - print(self.st.views) - assert (len(self.st.views) == 1) - - # multiview simplify - def test_expand_contract_different_shape(self): - self.st.expand((10, 10)) - self.st.reshape((100,)) - print(self.st.views) - assert (len(self.st.views) == 2) - self.st.reshape((2, 5, 2, 5)) - print(self.st.views) - - self.st = self.st.simplify() - print(self.st.views) - assert (len(self.st.views) == 1) - - # multiview simplify - def test_expand_contract_still_complex(self): - self.st.expand((10, 10)) - self.st.reshape((100,)) - print(self.st.views) - assert (len(self.st.views) == 2) - self.st.reshape((5, 20)) - - self.st = self.st.simplify() - print(self.st.views) - assert (len(self.st.views) == 2) - -# Tensor.zeros(2, 4).permute(1,0).reshape(2, 4) -# (d1*4 + d0%4), d1=x//4, d0=x%4 = ((x//4)*4) + (x%4)%4 - -class TestComplexShapeTracker(unittest.TestCase): - def test_add_1s(self): - self.st = CheckingShapeTracker((4, 4)) - self.st.permute((1,0)) - self.st.reshape((1,4,1,4,1)) - assert not self.st.contiguous - self.st.permute((0,3,2,1,4)) - assert self.st.contiguous - - def test_permute_1s_simple(self): - self.st = CheckingShapeTracker((1, 16, 9,9)) - self.st.permute((1,0,2,3)) - assert self.st.contiguous - self.st = CheckingShapeTracker((2, 16, 9,9)) - self.st.permute((1,0,2,3)) - assert not self.st.contiguous - - def test_remove_1s_simple(self): - self.st = CheckingShapeTracker((1, 16, 1, 1)) - self.st.reshape((16,)) - assert self.st.contiguous - - def test_remove_1s(self): - self.st = CheckingShapeTracker((1, 4, 1, 4, 1)) - self.st.permute((0,3,2,1,4)) - self.st.reshape((4,4)) - assert not self.st.contiguous - self.st.permute((1,0)) - assert self.st.contiguous - - def test_permute_reshape(self): - self.st = CheckingShapeTracker((4, 4)) - self.st.permute((1,0)) - self.st.reshape((2, 2, 2, 2)) - # TODO: should also be tested by test_super_complex - assert len(self.st.views) == 1 - - def test_factorize_split(self): - self.st = CheckingShapeTracker((4, 4)) - self.st.permute((1,0)) - self.st.reshape((2, 2, 2, 2)) - self.st.permute((2,3,0,1)) - assert self.st.contiguous - - def test_factorize_combine(self): - self.st = CheckingShapeTracker((4, 4, 4)) - self.st.permute((2, 0, 1)) - self.st.reshape((4, 16)) - self.st.permute((1, 0)) - assert self.st.contiguous - - def test_factorize_combine_add_ones(self): - self.st = CheckingShapeTracker((4, 4, 4)) - self.st.permute((2, 0, 1)) - self.st.reshape((4, 16, 1, 1)) - self.st.permute((1, 0, 2, 3)) - assert self.st.contiguous - - def test_fancy_factorize(self): - self.st = CheckingShapeTracker((32, 3, 3, 1)) - self.st.reshape((8, 4, 3, 3)) - assert len(self.st.views) == 1 - - def test_super_complex_2_fail(self): - self.st = CheckingShapeTracker((4, 4, 4)) - self.st.permute((2, 0, 1)) - self.st.reshape((16, 4)) - assert len(self.st.views) != 1 - - def test_work(self): - self.st = CheckingShapeTracker((64, 1024, 4)) - self.st.reshape((1, 64, 128, 32)) - self.st.permute((0, 3, 1, 2)) - self.st.reshape((1, 32, 1, 64, 128)) - self.st.permute((0, 3, 4, 1, 2)) - assert self.st.contiguous - - def test_work2(self): - self.st = CheckingShapeTracker((64, 1024, 4)) - self.st.reshape((1, 64, 128, 32)) - self.st.permute((0, 3, 1, 2)) - self.st.reshape((1, 1, 32, 64, 128)) - self.st.permute((0, 3, 4, 1, 2)) - self.st.reshape((64, 1024, 4)) - print(self.st.views) - assert self.st.contiguous - -class TestShapeTrackerEquality(unittest.TestCase): - def test_simple_equals(self): - self.assertEqual(ShapeTracker.from_shape((10,10)), ShapeTracker.from_shape((10,10))) - def test_other_equals(self): - st1 = ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True))) - st2 = ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True))) - self.assertEqual(st1, st2) - -class TestSingleShapeTracker(unittest.TestCase): - def setUp(self): - self.st = CheckingShapeTracker((7,4)) - - def tearDown(self): - self.st.assert_same() - - def test_reshape(self): - self.st.reshape((7,1,4)) - assert self.st.contiguous - - def test_permute(self): - self.st.permute((1,0)) - assert not self.st.contiguous - - def test_shrink(self): - self.st.shrink(((1,2), (0,4))) - assert not self.st.contiguous - - def test_double_permute(self): - self.st.permute((1,0)) - self.st.permute((1,0)) - assert self.st.contiguous - - def test_reshape_permute(self): - self.st.reshape((7,1,4)) - self.st.permute((0,1,2)) - assert self.st.contiguous - - def test_reshape_permute_yes(self): - self.st.reshape((7,1,4)) - self.st.permute((0,2,1)) - assert self.st.contiguous - - def test_reshape_permute_no(self): - self.st.reshape((4,7)) - self.st.permute((1,0)) - assert not self.st.contiguous - -class TestShapeTrackerFuzzFailures(unittest.TestCase): - def setUp(self): - self.st = CheckingShapeTracker((3,3,3)) - def tearDown(self): - self.st.assert_same() - def test_case_1(self): - self.st.shrink(((1, 2), (1, 3), (1, 3))) - self.st.reshape((1, 4)) - self.st.shrink(((0, 1), (1, 3))) - self.st = self.st.simplify() - def test_case_2(self): - self.st.flip( (True, False, True) ) - self.st.reshape( (3, 9) ) - self.st.shrink( ((1, 2), (1, 5)) ) - self.st.flip( (True, True) ) - def test_case_3(self): - self.st.shrink( ((0, 2), (0, 2), (0, 1)) ) - self.st.permute( (1, 0, 2) ) - self.st.reshape( (4,) ) - self.st.shrink( ((0, 3),) ) - self.st.flip( (True, False) ) - def test_case_4(self): - self.st.reshape( (3, 3, 3, 1) ) - self.st.pad( ((0, 0), (0, 0), (0, 0), (1, 1)) ) - self.st.shrink( ((0, 2), (1, 2), (0, 2), (0, 1)) ) - self.st.expand( (2, 1, 2, 3) ) - -class TestMaskedShapeTracker(unittest.TestCase): - def test_pad_1x1(self): - self.st = CheckingShapeTracker((1,1)) - self.st.pad(((1,1), (1,1))) - self.st.assert_same() - - def test_pad_2x2(self): - self.st = CheckingShapeTracker((2,2)) - self.st.pad(((1,1), (1,1))) - self.st.assert_same() - - def test_pad_reshape(self): - st1 = CheckingShapeTracker((1, 2)) - st1.pad(((1, 0), (0, 1))) - st1.reshape((3, 2)) - st1.assert_same() - - st2 = CheckingShapeTracker((1, 2)) - st2.pad(((1, 1), (0, 2))) - st2.reshape((4, 3)) - st2.assert_same() - - st3 = CheckingShapeTracker((1, 1, 1, 2)) - st3.pad(((0, 2), (1, 2), (2, 2), (0, 4))) - st3.reshape((4, 3, 6, 5)) - st3.assert_same() - - def test_axis_is_masked(self): - st = ShapeTracker.from_shape((100, 100, 100, 100)).pad(((0,1),(0,0),(2,0), (0,0))) - assert st.axis_is_masked(0) - assert not st.axis_is_masked(1) - assert st.axis_is_masked(2) - assert not st.axis_is_masked(3) - - def test_axis_is_masked_rw1(self): - st = ShapeTracker(views=(View(shape=(1, 2, 1, 4, 4, 13, 4, 13), strides=(0, 324, 0, 81, 0, 9, 0, 1), offset=-20, - mask=((0, 1), (0, 2), (0, 1), (0, 4), (0, 4), (2, 11), (0, 4), (2, 11)), contiguous=False), - View(shape=(2, 4, 11, 11, 4, 3, 3), strides=(10816, 0, 52, 1, 2704, 728, 14), offset=0, - mask=None, contiguous=False))) - assert not st.axis_is_masked(0) - -class TestShapeTracker(unittest.TestCase): - def setUp(self): - self.st = CheckingShapeTracker((7,4)) - self.apply = lambda fxn: [fxn(x) for x in [self.st]] - - def tearDown(self): - self.st.assert_same() - - def test_noop(self): - pass - - def test_simple_split(self): - self.test_permute() - self.apply(lambda x: x.reshape((prod(self.st.shape), ))) - - def test_simple_pad(self): - self.st.pad(((1,1), (1,1))) - - def test_pad_shrink(self): - self.st.pad(((1,1), (1,1))) - self.st.shrink(((0,4), (0,4))) - - def test_pad_one_sided(self): - self.st.pad(((0,1), (0,0))) - - def test_pad_reshape(self): - self.st.pad(((0,1), (0,0))) - self.st.reshape((8*4,)) - - def test_pad_pad(self): - self.st.pad(((1,1), (1,1))) - self.st.pad(((1,1), (1,1))) - - def test_pad_permute(self): - self.st.pad(((1,1), (2,2))) - self.st.permute((1,0)) - - def test_pad_expand(self): - self.st.reshape((7,4,1)) - self.st.pad(((1,1), (1,1), (0,0))) - self.st.expand((9,6,4)) - - def test_pad_expand_alt(self): - self.st.pad(((1,1), (1,1))) - self.st.reshape((9,6,1)) - self.st.expand((9,6,4)) - - def test_pad_flip(self): - self.st.pad(((1,4), (1,3))) - self.st.flip((True, False)) - - def test_pad_flip_int(self): - self.st.pad(((1,4), (1,3))) - self.st.flip((0, 1)) - - def test_reshape(self): - new_shape = self.st.shape[::-1] - self.apply(lambda x: x.reshape(new_shape)) - - def test_permute(self): - if len(self.st.shape) == 2: self.apply(lambda x: x.permute((1,0))) - elif len(self.st.shape) == 3: self.apply(lambda x: x.permute((2,0,1))) - - def test_reshape_with_1(self): - new_shape = (self.st.shape[0], 1, self.st.shape[1]) - self.apply(lambda x: x.reshape(new_shape)) - - def test_expand(self): - self.test_reshape_with_1() - new_shape = list(self.st.shape) - new_shape[1] = 2 - self.apply(lambda x: x.expand(tuple(new_shape))) - - def test_flip_0(self): - self.apply(lambda x: x.flip((True, False))) - - def test_flip_1(self): - self.apply(lambda x: x.flip((False, True))) - - def test_flip_01(self): - self.apply(lambda x: x.flip((True, True))) - - def test_slice_0(self): - self.apply(lambda x: x.shrink(((1, x.shape[0]), (0, x.shape[1])))) - - def test_slice_1(self): - self.apply(lambda x: x.shrink(((0, x.shape[0]), (1, x.shape[1])))) - - def test_slice_1c1(self): - self.apply(lambda x: x.shrink(((0, 1), (0, 1)))) - - def test_slice_1c2(self): - self.apply(lambda x: x.shrink(((1, 2), (1, 2)))) - - def test_double_permute(self): - self.apply(lambda x: x.permute((1, 0))) - self.apply(lambda x: x.permute((1, 0))) - - def test_slice_permute(self): - self.apply(lambda x: x.shrink(((0, 2), (2, 4)))) - self.apply(lambda x: x.permute((1, 0))) - - def test_slice_expand(self): - self.apply(lambda x: x.shrink(((0, 2), (3, 4)))) - self.apply(lambda x: x.expand((2, 10))) - - def test_double_flip(self): - self.apply(lambda x: x.flip((True, False))) - self.apply(lambda x: x.flip((True, False))) - - def test_flip(self): self.apply(lambda x: x.flip((True, False))) - def test_flip2(self): self.apply(lambda x: x.flip((False, True))) - def test_flip3(self): self.apply(lambda x: x.flip((True, True))) - - def test_reshape_then_permute(self): - self.test_reshape() - self.test_permute() - - def test_reshape_then_expand(self): - self.test_reshape() - self.test_expand() - - def test_permute_then_reshape(self): - self.test_permute() - self.test_reshape() - - def test_expand_then_reshape(self): - self.test_expand() - self.test_reshape() - - def test_combo(self): - self.test_permute() - self.test_reshape() - self.test_slice_1() - self.test_expand() - self.test_permute() - -class TestShapeTrackerSize(unittest.TestCase): - def test_simple_size(self): - st = ShapeTracker.from_shape((100, 100)) - self.assertEqual(st.real_size(), 100*100) - - def test_0_in_shape_size(self): - st = ShapeTracker.from_shape((0, 100)) - self.assertEqual(st.real_size(), 0) - st = ShapeTracker.from_shape((100, 0)) - self.assertEqual(st.real_size(), 0) - - def test_expand_size(self): - st = ShapeTracker.from_shape((100, 100)) - st = st.reshape((100, 100, 1)) - st = st.expand((100, 100, 100)) - self.assertEqual(st.real_size(), 100*100) - - def test_expand_size_flatten(self): - st = ShapeTracker.from_shape((100, 100)) - st = st.reshape((100, 100, 1)) - st = st.expand((100, 100, 100)) - st = st.reshape((100*100*100,)) - self.assertEqual(st.real_size(), 100*100) - - def test_shrink_size_axis_0(self): - st = ShapeTracker.from_shape((100, 100)) - st = st.shrink(((0, 50), (0, 100))) - self.assertEqual(st.real_size(), 50*100) - - def test_shrink_size_axis_0_variable(self): - st = ShapeTracker.from_shape((100, 100)) - st = st.shrink(((0, Variable("a", 0, 50)), (0, 100))) - self.assertEqual(st.real_size(), 50*100) - - def test_shrink_size_axis_1(self): - st = ShapeTracker.from_shape((100, 100)) - st = st.shrink(((0, 100), (0, 50))) - self.assertEqual(st.real_size(), 9950) # careful here - - def test_size_variable(self): - st = ShapeTracker(views=(View(shape=(1, 1, 1, (Variable('start_pos', 0, 8192)+1), 1, 8, 4, 128), strides=(0, 0, 0, 1024, 0, 128, 0, 1), - offset=0, mask=None, contiguous=False), View(shape=(1, 32, 1, (Variable('start_pos', 0, 8192)+1), 128), - strides=(0, 128, 0, 4096, 1), offset=0, mask=None, contiguous=False))) - self.assertEqual(st.real_size(), 8389632) - - def test_pad_size_simple(self): - st = ShapeTracker.from_shape((10,)).pad(((2,4),)) - self.assertEqual(st.real_size(), 10) - - def test_pad_size_multiview(self): - st = ShapeTracker.from_shape((10,10)).pad(((2,4), (3,1))).reshape((16*14,)) - self.assertEqual(st.real_size(), 100) - - def test_flip_size(self): - st = ShapeTracker.from_shape((10,10)).pad(((2,4), (3,1))).flip((True, True)) - self.assertEqual(st.real_size(), 100) - -class TestConsecutive(unittest.TestCase): - @classmethod - def setUpClass(self): - from tinygrad.tensor import Tensor # easier test setup - self.t = Tensor([[1, 2, 3, 4], [5, 6, 7, 8]]) - self.const = Tensor(2) - self.ones = Tensor.ones(2, 4) - - def test_unmodified(self): - assert self.t.uop.st.consecutive - assert self.t.reshape(4, 2).uop.st.consecutive - assert self.t.reshape(1, 8).uop.st.consecutive - - def test_sliced(self): - assert self.t[0].uop.st.consecutive - assert self.t[0, 1:2].uop.st.consecutive - assert self.t[1].uop.st.consecutive - assert not self.t[:, 0].uop.st.consecutive - assert not self.t[:, 1].uop.st.consecutive - - def test_padded(self): - assert not self.t.pad(((1, 1), None)).uop.st.consecutive - assert not self.t.pad((None, (1, 1))).uop.st.consecutive - - def test_const(self): - assert self.const.uop.st.consecutive - - def test_ones(self): - assert not self.ones.uop.st.consecutive - assert not self.ones[0, :].uop.st.consecutive - # consecutive if sliced into size 1 - assert self.ones[0, 0].uop.st.consecutive - -class TestRender(unittest.TestCase): - def test_render(self): - st = ShapeTracker.from_shape((2, 3)) - idx, valid = st.to_indexed_uops() - self.assertEqual(idx.render(), "((ridx0*3)+ridx1)") - self.assertEqual(valid.render(), "True") - - st = st.pad(((0, 1), (0, 0))) - idx, valid = st.to_indexed_uops() - self.assertEqual(idx.render(), "((ridx0*3)+ridx1)") - self.assertEqual(valid.render(), "(ridx0<2)") - -class TestVariableReshape(unittest.TestCase): - def test_reshape(self): - st = ShapeTracker.from_shape((3,)) - st = st.reshape((Variable("i", 1, 10),)) - assert len(st.views) == 1 - - def test_reshape_stride_0(self): - st = ShapeTracker.from_shape((3,), (0,)) - st = st.reshape((Variable("i", 1, 10).bind(3),)) - assert len(st.views) == 1, f"multiview {st}" - - def test_reshape_bound(self): - st = ShapeTracker.from_shape((3,)) - st = st.reshape((Variable("i", 1, 10).bind(3),)) - assert len(st.views) == 1 - - def test_add(self): - st1 = ShapeTracker.from_shape((3,)) - st2 = ShapeTracker.from_shape((Variable("i", 1, 10),)) - st = st1+st2 - assert len(st.views) == 1 - - def test_add_stride_0(self): - st1 = ShapeTracker.from_shape((3,), (0,)) - st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),), (0,)) - st = st1+st2 - assert len(st.views) == 1, f"multiview {st}" - - def test_add_bound(self): - st1 = ShapeTracker.from_shape((3,)) - st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),)) - st = st1+st2 - assert len(st.views) == 1 - - def test_simplify(self): - st1 = ShapeTracker.from_shape((3,)) - st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),)) - st = ShapeTracker((st1.views[0], st2.views[0])) - st = st.simplify() - assert len(st.views) == 1 - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_shapetracker_math.py b/tinygrad/test/unit/test_shapetracker_math.py deleted file mode 100644 index efd017f5..00000000 --- a/tinygrad/test/unit/test_shapetracker_math.py +++ /dev/null @@ -1,178 +0,0 @@ -import unittest -from tinygrad.helpers import prod -from tinygrad.shape.view import View -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad import Variable -from test.unit.test_shapetracker import shapetracker_getitem - -class MultiShapeTracker: - def __init__(self, sts:list[ShapeTracker]): self.sts = sts - @property - def shape(self): return self.sts[0].shape - def reshape(self, arg): self.sts = [x.reshape(arg) for x in self.sts] - def permute(self, arg): self.sts = [x.permute(arg) for x in self.sts] - def expand(self, arg): self.sts = [x.expand(arg) for x in self.sts] - def shrink(self, arg): self.sts = [x.shrink(arg) for x in self.sts] - def flip(self, arg): self.sts = [x.flip(arg) for x in self.sts] - def pad(self, arg): self.sts = [x.pad(arg) for x in self.sts] - -def st_equal(st1:ShapeTracker, st2:ShapeTracker) -> bool: - if st1.shape != st2.shape: return False - if st1 == st2: return True - for i in range(0, prod(st1.shape)): - st1_off, st1_v = shapetracker_getitem(st1, i) - st2_off, st2_v = shapetracker_getitem(st2, i) - if st1_v != st2_v or (st1_off != st2_off and st1_v): - print(f"ST MISMATCH @ {i}, {st1_v=} != {st2_v=}, {st1_off=} != {st2_off=}") - print(st1) - print(st2) - return False - return True - -class TestShapeTrackerBasics(unittest.TestCase): - def test_pad_shrink_removes_mask(self): - a = ShapeTracker.from_shape((10, 10)) - a = a.pad(((0,2), (0,2))) - a = a.shrink(((0,10), (0,10))) - assert len(a.views) == 1 and a.views[-1].mask is None - - def test_pad_shrink_leaves_mask(self): - a = ShapeTracker.from_shape((10, 10)) - a = a.pad(((0,2), (0,2))) - a = a.shrink(((0,10), (0,11))) - assert len(a.views) == 1 and a.views[-1].mask is not None - - def test_reshape_makes_same(self): - a = ShapeTracker.from_shape((2, 5)) - x = a.pad( ((2, 0), (0, 0)) ) - x = x.reshape( (2, 2, 5) ) - x1 = x.reshape( (4, 5) ) - x1 = x1.reshape( (2, 2, 5) ) - assert x == x1.simplify() - - def test_simplify_is_correct(self): - multiv = ShapeTracker(views=(View(shape=(15, 3), strides=(9, 1), offset=6, mask=None, contiguous=False), - View(shape=(4, 3), strides=(12, 4), offset=0, mask=None, contiguous=False))) - assert st_equal(multiv, multiv.simplify()) - -class TestShapeTrackerAdd(unittest.TestCase): - def test_simple_add_reshape(self): - a = ShapeTracker.from_shape((10, 10)) - a = a.reshape((100,)) - b = ShapeTracker.from_shape((100,)) - assert a+b == b - - def test_simple_add_permute(self): - a = ShapeTracker.from_shape((10, 10)) - a = a.permute((1,0)) - b = ShapeTracker.from_shape((10, 10)) - b = b.permute((1,0)) - assert a+b == ShapeTracker.from_shape((10, 10)) - - def test_plus_real1(self): - st = MultiShapeTracker([ShapeTracker.from_shape((15, 9))]) - st.shrink( ((0, 15), (6, 9)) ) - backup = st.sts[0] - st.sts.append(ShapeTracker.from_shape(backup.shape)) - st.reshape( (45,) ) - st.flip( (True,) ) - st.reshape( (15, 3) ) - assert st_equal(backup + st.sts[1], st.sts[0]) - - def test_off_by_one(self): - st1 = ShapeTracker(views=(View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True), - View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True))) - st2 = ShapeTracker(views=(View(shape=(4,), strides=(1,), offset=0, mask=None, contiguous=True), - View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True))) - assert not (st_equal(st1, st2)) - -class TestShapeTrackerAddVariable(unittest.TestCase): - def test_self_add(self): - j = Variable("j", 0, 20).bind(10) - a = ShapeTracker.from_shape((10,10)) - x = a.reshape((10, j)) - out = x + x - assert out == x - - def test_self_add_reshape(self): - j = Variable("j", 0, 20).bind(10) - a = ShapeTracker.from_shape((10,10)) - x = a.reshape((10, j)) - out = x.reshape((5, 2, j)) + x - assert out == x - - def test_merge_symbolic_views(self): - var_i = Variable('i', 1, 10) - var_j = Variable('i', 1, 10) - vm1 = View(shape=(var_i, var_j, 3), strides=(3, 0, 1), offset=0, mask=None, contiguous=False) - vm2 = View(shape=(var_i, var_j, 3), strides=(var_j*3, 3, 1), offset=0, mask=None, contiguous=True) - ShapeTracker((vm1,)) + ShapeTracker((vm2,)) - - def test_merge_symbolic_views_2(self): - var_i = Variable('i', 1, 10) - var_j = Variable('j', 1, 10) - vm1 = View(shape=(var_i, var_j), strides=(0, 0), offset=0, mask=None, contiguous=False) - vm2 = View(shape=(var_i, var_j), strides=(var_j, 1), offset=0, mask=None, contiguous=True) - ret = (ShapeTracker((vm1,)) + ShapeTracker((vm2,))).reshape((var_i, var_j, 1)) - ret_2 = ShapeTracker((vm1,)) + ShapeTracker((vm2,)).reshape((var_i, var_j, 1)) - assert ret == ret_2 - -class TestShapeTrackerInvert(unittest.TestCase): - def test_invert_reshape(self): - a = ShapeTracker.from_shape((10, 10)) - x = a.reshape((5, 20)) - ap = ShapeTracker.from_shape(x.shape) + x.invert(a.shape) - assert ap == a, f"{ap} != {a}" - - def test_invert_permute(self): - a = ShapeTracker.from_shape((5, 20)) - x = a.permute((1,0)) - ap = x + x.invert(a.shape) - assert ap == a, f"{ap} != {a}" - - def test_invert_permute_3(self): - a = ShapeTracker.from_shape((8, 4, 5)) - x = a.permute((1,2,0)) - ap = x + x.invert(a.shape) - assert ap == a, f"{ap} != {a}" - - def test_invert_real1(self): - a = ShapeTracker.from_shape((3, 6, 10)) - x = a.reshape( (3, 3, 2, 10) ) - x = x.permute( (2, 1, 3, 0) ) - ap = x + x.invert(a.shape) - assert ap == a, f"{ap} != {a}" - - def test_cant_invert_expand(self): - a = ShapeTracker.from_shape((10, 1)) - x = a.expand((10,10)) - assert x.invert(a.shape) is None - - def test_cant_invert_shrink(self): - a = ShapeTracker.from_shape((10, 10)) - x = a.shrink(((0,10),(2,8))) - assert x.invert(a.shape) is None - - def test_can_invert_flip(self): - a = ShapeTracker.from_shape((20, 10)) - x = a.flip((True,False)) - ap = x + x.invert(a.shape) - assert st_equal(ap, a) - - def test_can_invert_flip_permute(self): - a = ShapeTracker.from_shape((20, 10)) - x = a.permute((1,0)) - x = x.flip((True,False)) - ap = x + x.invert(a.shape) - assert st_equal(ap, a) - - def test_invert_failure(self): - a = ShapeTracker.from_shape((2, 5)) - x = a.pad( ((2, 0), (0, 0)) ) - x = x.reshape( (2, 2, 5) ) - x = x.reshape( (4, 5) ) - ap = x + x.invert(a.shape) - assert st_equal(ap, a) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_shm_tensor.py b/tinygrad/test/unit/test_shm_tensor.py deleted file mode 100644 index 6c9ab248..00000000 --- a/tinygrad/test/unit/test_shm_tensor.py +++ /dev/null @@ -1,38 +0,0 @@ -import unittest -import multiprocessing.shared_memory as shared_memory -from tinygrad.helpers import CI -from tinygrad.tensor import Tensor, Device -import numpy as np - -class TestRawShmBuffer(unittest.TestCase): - def test_e2e(self): - t = Tensor.randn(2, 2, 2).realize() - - # copy to shm - shm_name = (s := shared_memory.SharedMemory(create=True, size=t.nbytes())).name - s.close() - t_shm = t.to(f"disk:shm:{shm_name}").realize() - - # copy from shm - t2 = t_shm.to(Device.DEFAULT).realize() - - assert np.allclose(t.numpy(), t2.numpy()) - s.unlink() - - @unittest.skipIf(CI, "CI doesn't like big shared memory") - def test_e2e_big(self): - t = Tensor.randn(2048, 2048, 8).realize() - - # copy to shm - shm_name = (s := shared_memory.SharedMemory(create=True, size=t.nbytes())).name - s.close() - t_shm = t.to(f"disk:shm:{shm_name}").realize() - - # copy from shm - t2 = t_shm.to(Device.DEFAULT).realize() - - assert np.allclose(t.numpy(), t2.numpy()) - s.unlink() - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_simplify_valid_idx.py b/tinygrad/test/unit/test_simplify_valid_idx.py deleted file mode 100644 index 656821ba..00000000 --- a/tinygrad/test/unit/test_simplify_valid_idx.py +++ /dev/null @@ -1,416 +0,0 @@ -import unittest, itertools - -from tinygrad.codegen import full_rewrite_to_sink -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UOp, Ops -from tinygrad.codegen.symbolic import simplify_valid - -def get_gated_load_uop(valid:UOp, idx:UOp): - return UOp(Ops.LOAD, dtypes.float, ( - UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0).index(idx, valid), - UOp.const(dtypes.float, 0.0) - )) - -def get_load_image_uop(image_shape:tuple[int, ...], valid:UOp, idx:tuple[UOp, UOp]): - return UOp(Ops.LOAD, dtypes.float.vec(4), ( - UOp(Ops.DEFINE_GLOBAL, dtypes.imagef(image_shape), arg=0).index(UOp(Ops.VECTORIZE, dtypes.int.vec(2), idx), valid), - UOp(Ops.VECTORIZE, dtypes.float.vec(4), src=(UOp.const(dtypes.float, 0.0),) * 4) - )) - -def Special(expr, nmax): return UOp(Ops.SPECIAL, dtypes.int, (), (expr, nmax)) -def Variable(expr, nmin, nmax): return UOp.variable(expr, nmin, nmax) -def Range(n, nmax): return UOp(Ops.RANGE, dtypes.int, arg=n, src=(UOp.const(dtypes.int, nmax),)) - -class TestHelpers(unittest.TestCase): - def test_is_increasing(self): - idx1 = Special("idx1", 32) - idx2 = Special("idx2", 64) - ridx0 = Variable("ridx0", 0, 5) - ridx1 = Variable("ridx1", 0, 2) - ridx2 = Variable("ridx2", 0, 2) - # (ridx0+(idx1*48)+(ridx2*6)+(-6)),((idx2*2)+ridx1+(-1))) - f0 = ((idx1*24)+(ridx2*3)+ridx0+765)%768 - f1 = ridx0+(idx1*48)+(ridx2*6)+(-6) - f2 = (idx2*2)+ridx1+((idx1+((ridx2+7)//8)+31)//32)+(-2) - f3 = (idx2*2)+ridx1+(-1) - - self.assertFalse(f0.is_increasing()) - self.assertTrue(f1.is_increasing()) - self.assertTrue(f2.is_increasing()) - self.assertTrue(f3.is_increasing()) - - rng = UOp(Ops.RANGE, dtypes.int, arg=(2, True), src=(UOp(Ops.CONST, dtypes.int, arg=5, src=()),)) - self.assertTrue(rng.is_increasing()) - self.assertTrue((rng+2).is_increasing()) - -class TestValidIdxSimplification(unittest.TestCase): - def check(self, load, sidx, svalid): - load = full_rewrite_to_sink(load.sink()).src[0] - idx, valid = load.src[0].src[1], load.src[0].src[2] - self.assertEqual(idx.render(simplify=False), sidx) - self.assertEqual(valid.render(simplify=False), svalid) - - def test_cumsum(self): - gidx0 = Special("gidx0", 5) - lidx0 = Special("lidx0", 4) - gate = (gidx0*4+lidx0<19).ne(True) - idx = gidx0*4+lidx0-19 - load = get_gated_load_uop(gate, idx) - self.check(load, - "0", - "(((lidx0+(gidx0*4))<19)!=True)") - - def test_simplify_within_valid1(self): - ridx0 = Range(0, 4) - ridx1 = Range(1, 4) - ridx2 = Range(2, 4) - ridx3 = Range(3, 4) - valid = ((ridx0*3+ridx1)<8) & ((((ridx0*3+ridx1)//8+ridx2*3+ridx3)%4)<2) - idx = ridx0+ridx1+ridx2+ridx3 - load = get_gated_load_uop(valid, idx) - self.check(load, - "(((ridx0+ridx1)+ridx2)+ridx3)", - "((((ridx0*3)+ridx1)<8)&((((ridx2*3)+ridx3)%4)<2))") - - def test_simplify_within_valid2(self): - gidx0 = Special("gidx0", 56) - ridx0 = Range(0, 3) - alu0 = gidx0+ridx0 - valid = (alu0 < 57) & (alu0 >= 1) - self.assertIsNone(simplify_valid(valid)) - - def test_valid_order_matters1(self): - ridx0 = Range(0, 2) - v0 = ridx0<1 - v1 = ((ridx0*5+1)%6)<5 - self.assertEqual(simplify_valid(v0&v1).render(), "(ridx0<1)") - self.assertEqual(simplify_valid(v1&v0).render(), "(ridx0<1)") - - def test_valid_order_matters2(self): - gidx0 = Special("gidx0", 13) - gidx1 = Special("gidx1", 13) - ridx0 = Range(0, 4) - alu0 = (gidx1+(ridx0*13)) - v0 = (gidx0+11)%14<11 - v1 = (alu0+((gidx0+39)//42))%14<11 - v2 = gidx0<3 - v3 = alu0<42 - - for v in itertools.permutations([v0,v1,v2,v3]): - self.assertEqual(simplify_valid(v[0]&v[1]&v[2]&v[3]).render(), "False") - - def test_simplify_valid_from_div(self): - x = Variable("x", -100, 100) - valid = ((x<0)&((100%x).cast(dtypes.bool))) - self.assertIsNone(simplify_valid(valid)) - - @unittest.expectedFailure # TODO: fix - def test_from_merge_views(self): - # taken from test_merges_from_fuzzer1 - # generated by - # v0 = View(shape=(2, 4), strides=(2, 1), offset=-2, mask=((0, 2), (2, 4)), contiguous=False) - # v1 = View(shape=(2, 4, 2, 2), strides=(4, 0, -2, -1), offset=3, mask=None, contiguous=False) - # s = ShapeTracker((v0, v1)) - # idx, valid = s.to_indexed_uops() - # print(f"{idx.render()=}") - # print(f"{valid.render()=}") - - # s = ShapeTracker((View(shape=(2, 4, 2, 2), strides=(2, 0, 0, -1), offset=1, mask=((0, 2), (0, 4), (0, 1), (0, 2)), contiguous=False),)) - # idx, valid = s.to_indexed_uops() - # print(f"{idx.render()=}") - # print(f"{valid.render()=}") - ridx0 = Range(0, 2) - ridx2 = Range(2, 2) - ridx3 = Range(3, 2) - idx = (((ridx0*2)+((((ridx2*2)+(ridx3*3))+3)%4))+-2) - valid = ((((((ridx2*2)+(ridx3*3))+3)%4)<2)!=True) # noqa: E712 - load = get_gated_load_uop(valid, idx) - self.check(load, - "(((ridx0*2)+(ridx3*-1))+1)", - "(ridx2<1)") - - def test_load_in_valid(self): - # from FUSE_ARANGE=1 python test/test_ops.py TestOps.test_scatter_add - # can lead to OOB - ridx2 = Range(2, 4) - lidx0 = Special("lidx0", 3) - gidx0 = Special("gidx0", 2) - idx=(((lidx0+(gidx0*3))+(ridx2*5))+40) - valid = (lidx0+(gidx0*3)) < 5 - val7 = get_gated_load_uop(valid, idx) - valid2 = valid & val7.cast(dtypes.bool).logical_not() - self.assertIsNone(simplify_valid(valid2)) - - def test_valid_becomes_const1(self): - # from DSP mobilenetv2 - ridx0 = Range(0, 30) - ridx1 = Range(1, 7) - ridx2 = Range(2, 2) - alu11 = (ridx1+ridx2) - alu15 = ((alu11+1)//7) - idx = (alu15*-31)+(((((alu11+218)//224)+ridx0)%30)*1568) - valid = (ridx2<1)&(ridx1<6) - load = get_gated_load_uop(valid, idx) - self.check(load, - "(ridx0*1568)", - "((ridx2<1)&(ridx1<6))") - - def test_valid_becomes_const1_z3(self): - from z3 import Ints, Solver, And, If, Not, unsat - ridx0, ridx1, ridx2, alu11, alu15 = Ints('ridx0 ridx1 ridx2 alu11 alu15') - alu11 = (ridx1+ridx2) - alu15 = ((alu11+1)/7) - idx = (alu15*-31)+(((((alu11+218)/224)+ridx0)%30)*1568) - valid = (ridx2<1)&(ridx1<6) - load = If(valid, idx, 0) - - # correct simplification - s = Solver() - s.add(And(0<=ridx0, ridx0<30, 0<=ridx1, ridx1<7, 0<=ridx2, ridx2<2)) - simplifed_idx = (ridx0*1568) - simplifed_load = If(valid, simplifed_idx, 0) - s.add(Not(load == simplifed_load)) # Check if they are NOT equivalent - assert s.check() == unsat, f"The expressions are not equivalent. {s.model()=}" - - # new solver for a wrong simplified expression - s = Solver() - s.add(And(0<=ridx0, ridx0<30, 0<=ridx1, ridx1<7, 0<=ridx2, ridx2<2)) - wrong_simplifed_idx = (ridx0*1567)+ridx1 - wrong_simplifed_load = If(valid, wrong_simplifed_idx, 0) - s.add(Not(load == wrong_simplifed_load)) # Check if they are NOT equivalent - assert s.check() != unsat, "The expressions are equivalent??" - print("The expressions are not equivalent.") - print(s.model()) - - @unittest.expectedFailure # TODO: improve uop_given_valid - def test_valid_becomes_const2(self): - ridx0 = Range(0, 4) - ridx1 = Range(1, 4) - ridx2 = Range(2, 4) - ridx3 = Range(3, 4) - idx= ((ridx0+ridx1+ridx2+ridx3+28)//30) - valid = ((ridx0+ridx1)<1).ne(True) & ((ridx2+ridx3)<1).ne(True) - load = get_gated_load_uop(valid, idx) - self.check(load, - "1", - "((((ridx0+ridx1)<1)!=True)&(((ridx2+ridx3)<1)!=True))") - -class TestImageSimplification(unittest.TestCase): - def check(self, load, svalid, sidx0, sidx1): - load = full_rewrite_to_sink(load.sink()).src[0] - idx = load.src[0].src[1] - self.assertEqual(idx.op, Ops.VECTORIZE) - self.assertEqual(len(idx.src), 2) - idx0, idx1 = idx.src[0], idx.src[1] - self.assertEqual(idx0.render(simplify=False), sidx0) - self.assertEqual(idx1.render(simplify=False), sidx1) - if svalid is not None: - self.assertEqual(load.src[0].src[2].render(simplify=False), svalid) - else: - self.assertEqual(len(load.src[0].src), 2, "svalid is None but load still has a valid") - - def test_idx_gt_c(self): - # (idx1 < c+1).ne(True) ? (..., idx1-1+c) : 0 can drop the valid - # (idx1 < c+1).ne(True) -> idx > c - gidx0 = Special("gidx0", 32) - gidx1 = Special("gidx1", 32) - shape = (10, 10, 4) - load = get_load_image_uop(shape, (gidx1<1).ne(True), (gidx0, gidx1-1)) - self.check(load, None, "gidx0", "(gidx1+-1)") - load = get_load_image_uop(shape, (gidx1<1).ne(True), (gidx0, gidx1-2)) - self.check(load, None, "gidx0", "(gidx1+-2)") - - # should match any one of the AND clause and drop the matched statement from valid - valid = (gidx0<1).ne(True) & (gidx1<1).ne(True) - load = get_load_image_uop(shape, valid, (gidx0+1, gidx1-1)) - self.check(load, "((gidx0<1)!=True)", "(gidx0+1)", "(gidx1+-1)") - - valid = (gidx0<1).ne(True) & (gidx1<1).ne(True) - load = get_load_image_uop(shape, valid, (gidx0, gidx1-1)) - self.check(load, "((gidx0<1)!=True)", "gidx0", "(gidx1+-1)") - - def test_idx_lt_bound(self): - # (idx1 < image_bound) ? (..., idx1) : 0 can drop the valid - gidx0 = Special("gidx0", 32) - gidx1 = Special("gidx1", 32) - load = get_load_image_uop((10, 10, 4), gidx1<10, (gidx0, gidx1)) - self.check(load, None, "gidx0", "gidx1") - - # same thing, valid has a div - load = get_load_image_uop((10, 10, 4), gidx1//2<5, (gidx0, gidx1)) - self.check(load, None, "gidx0", "gidx1") - - # 10x20 image, not out of bound - load = get_load_image_uop((20, 10, 4), gidx1<10, (gidx0, gidx1)) - self.check(load, "(gidx1<10)", "gidx0", "gidx1") - - def test_generic_idx_lt_bound(self): - # (idx1 < image_bound - c) ? (..., idx1 + c) : 0 can drop the valid - gidx0 = Special("gidx0", 32) - gidx1 = Special("gidx1", 32) - shape = (10, 10, 4) - load = get_load_image_uop(shape, (gidx1<8), (gidx0, gidx1+2)) - self.check(load, None, "gidx0", "(gidx1+2)") - - load = get_load_image_uop(shape, (gidx1<5), (gidx0, gidx1+5)) - self.check(load, None, "gidx0", "(gidx1+5)") - - def test_valid_empty_set(self): - gidx0 = Special("gidx0", 32) - gidx1 = Special("gidx1", 32) - shape = (32, 32, 4) - idx = (gidx0%2, gidx1+2) - # not empty - load = get_load_image_uop(shape, gidx0<8, idx) - self.check(load, "(gidx0<8)", "(gidx0%2)", "(gidx1+2)") - - # empty -> invalid - load = get_load_image_uop(shape, (gidx0<8) & (gidx0<8).ne(True), idx) - load = full_rewrite_to_sink(load.sink()).src[0] - self.assertEqual(load.op, Ops.VECTORIZE) - self.assertEqual(load.dtype.count, 4) - - def test_openpilot_conv1(self): - # first conv in openpilot - # kernel in tinygrad ae5d1407ee844a97a52ad3756835d38e7e2b9e1b https://gist.github.com/chenyuxyz/39c2d4e9a076b46731c67d345ff066b6 - idx1 = Special("idx1", 32) - idx2 = Special("idx2", 64) - # ridx0 = Variable("ridx0", 0, 5) - # ridx1 = Variable("ridx1", 0, 2) - # ridx2 = Variable("ridx2", 0, 2) - ridx0 = Range(0, 6) - ridx1 = Range(1, 3) - ridx2 = Range(2, 3) - - alu1 = ((idx2*2)+ridx1) - alu4 = ((idx1*48)+(ridx2*6)+ridx0) - - valid = ((((idx2*2)+(ridx1))<1).ne(True))&((((idx1*8)+(ridx2))<1).ne(True)) - shape = (128, 1536, 4) - idx = ((alu4+1530)%1536, alu1+((idx1+((ridx2+7)//8)+31)//32)+(-2)) - - load = get_load_image_uop(shape, valid, idx) - self.check(load, None, "((((idx1*48)+(ridx2*6))+ridx0)+-6)", "(((idx2*2)+ridx1)+-1)") - - def test_openpilot_conv2(self): - # conv in test/external/external_test_valid_remove.py - idx1 = Special("idx1", 32) - idx2 = Special("idx2", 64) - # ridx0 = Variable("ridx0", 0, 2) - # ridx1 = Variable("ridx1", 0, 2) - # ridx2 = Variable("ridx2", 0, 2) - ridx0 = Range(0, 3) - ridx1 = Range(1, 3) - ridx2 = Range(2, 3) - - alu1 = ((idx2*2)+ridx1) - alu3 = ((idx1*24)+(ridx2*3)+ridx0) - - valid = ((((idx2*2)+ridx1)<1).ne(True))&((((idx1*8)+ridx2)<1).ne(True)) - shape = (128, 768, 4) - idx = ((alu3+765)%768, alu1+((idx1+((ridx2+7)//8)+31)//32)+(-2)) - load = get_load_image_uop(shape, valid, idx) - - self.check(load, None, "((((idx1*24)+(ridx2*3))+ridx0)+-3)", "(((idx2*2)+ridx1)+-1)") - - def test_openpilot_conv3(self): - # in openpilot 0.9.7 - idx0 = Special("idx0", 64) - idx1 = Special("idx1", 2) - idx2 = Special("idx2", 4) - ridx0 = Range(0, 7) - ridx1 = Range(1, 7) - - alu2 = ((idx2*2)+ridx0) - alu4 = ((idx1*8)+ridx1) - alu6 = ((idx1*512)+(ridx1*64)+idx0) - - valid = (alu2<11)&(alu4<3).ne(True) - shape = (8, 1024, 4) - idx = (((alu6+832)%1024),(alu2+((idx1+((ridx1+5)//8)+1)//2)+(-4))) - - load = get_load_image_uop(shape, valid, idx) - - self.check(load, - "((((idx2*2)+ridx0)<11)&((((idx1*8)+ridx1)<3)!=True))", - "(((idx0+((idx1*512)+(ridx1*64)))+832)%1024)", - "((((idx2*2)+ridx0)+(((idx1+((ridx1+5)//8))+1)//2))+-4)") - - def test_simplify1(self): - # idx has the form (A % m, A // m + k) and valid has (c0 < A) and (A < c1) - gidx = Special("gidx", 512) - valid = (gidx<488) & (gidx<480).ne(True) - idx = ((gidx*3+18)%26, (gidx*3+18)//26-56) - load = get_load_image_uop((1, 26, 4), valid, idx) - self.check(load, None, "((gidx*3)+-1438)", "0") - - def test_simplify2(self): - # from GPU=1 DEBUG=4 FORWARD_ONLY=1 IMAGE=2 python3 test/test_ops.py TestOps.test_simple_padding_conv2d - lidx = Special("lidx", 4) - valid = (lidx<3) & (lidx<1).ne(True) - idx = ((lidx+1)%2, (lidx+1)//2-1) - load = get_load_image_uop((1, 2, 4), valid, idx) - self.check(load, None, "(lidx+-1)", "0") - - def test_simplify3(self): - # from openpilot - idx0 = Special("idx0", 265) - valid = (idx0<201).ne(True) - idx = ((idx0+55)%64, (idx0+55)//64-4) - load = get_load_image_uop((1, 64, 4), valid, idx) - self.check(load, None, "(idx0+-201)", "0") - - def test_simplify4(self): - idx0 = Special("idx0", 512) - shape = (4, 64, 4) - alu2 = ((idx0*4+1)%32) - alu3 = ((idx0*4+2)%32) - alu4 = ((idx0*4+3)%32) - alu5 = (idx0*4%32) - alu8 = (idx0//8%32//4) - alu9 = idx0<256 - - # TODO: can this be simplified further? - load = get_load_image_uop(shape, alu9, (((alu8+(alu2*8))%64),(alu2//8))) - self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+8)%64)", "((idx0%8)//2)") - - load = get_load_image_uop(shape, alu9, (((alu8+(alu3*8))%64),(alu3//8))) - self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+16)%64)", "((idx0%8)//2)") - - load = get_load_image_uop(shape, alu9, (((alu8+(alu4*8))%64),(alu4//8))) - self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+24)%64)", "((idx0%8)//2)") - - load = get_load_image_uop(shape, alu9, (((alu8+(alu5*8))%64),(alu5//8))) - self.check(load, "(idx0<256)", "((((idx0%8)*32)+(idx0//32))%64)", "((idx0%8)//2)") - - def test_simplify5(self): - # openpilot 0.9.7, chunk replacement to simplify - shape = (10, 384, 4) - idx0 = Special("idx0", 16) - idx1 = Special("idx1", 24) - alu0 = idx0*4 - alu1 = (idx1*256)+alu0 - alu2 = idx1//3 - alu3 = ((alu1+1)%768) - idx = ((idx0+((((alu3//640)+alu2)%8)*16)+128),((alu3//64)%10)) - valid = alu3<640 - - load = get_load_image_uop(shape, valid, idx) - self.check(load, "(((idx0+(idx1*64))%192)<160)", "((idx0+((idx1//3)*16))+128)", "(((idx0+(idx1*64))%192)//16)") - - def test_simplify6(self): - # from openpilot - # the valid implies the numerator of the div/mod is positive and can be simplified with floordiv rules - idx1 = Special("idx1", 16) - idx2 = Special("idx2", 64) - ridx3 = Range(3, 3) - ridx4 = Range(4, 3) - ridx5 = Range(5, 3) - alu0 = ((idx2*1536)+(ridx4*768)+ridx3+(idx1*24)+(ridx5*3)+-771)%768 - alu1 = ((idx2*1536)+(ridx4*768)+ridx3+(idx1*24)+(ridx5*3)+-771)//768 - valid = (((idx2+ridx4)<1)!=1)&(((idx1+ridx5)<1)!=1) - load = get_load_image_uop((128, 768, 4), valid, (alu0, alu1)) - self.check(load, None, "((((idx1*24)+ridx3)+(ridx5*3))+-3)", "(((idx2*2)+ridx4)+-1)") - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_symbolic_failures.py b/tinygrad/test/unit/test_symbolic_failures.py deleted file mode 100644 index 0fc5ee24..00000000 --- a/tinygrad/test/unit/test_symbolic_failures.py +++ /dev/null @@ -1,161 +0,0 @@ -import unittest -from tinygrad import Variable, dtypes -from tinygrad.helpers import Context -from tinygrad.uop.ops import Ops, UOp - - -class TestFuzzFailure(unittest.TestCase): - def setUp(self): - self.context = Context(CORRECT_DIVMOD_FOLDING=1) - self.context.__enter__() - - def tearDown(self): - self.context.__exit__(None, None, None) - - def test_fuzz_failure1(self): - v1=Variable('v1', 0, 8) - v2=Variable('v2', 0, 2) - v3=Variable('v3', 0, 1) - expr = (((((((((((((((((((((((0//4)%2)//8)+-2)+-4)+-3)+v1)+-4)+v2)+-2)+v3)+v2)//3)%7)*1)//2)+v2)*-1)+2)+1)+0)+-3)+v3) - v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure2(self): - v1=Variable('v1', 0, 16) - v2=Variable('v2', 0, 5) - v3=Variable('v3', 0, 3) - expr = (((((((((((((((((((((((((0*4)//5)*2)*-1)*-2)+-4)*4)*2)*3)*4)+-4)*4)+v2)+v2)+v3)//3)+v2)+v1)//9)+3)+1)//1)+-4)//4)*2) - expr = (((((v1+(v2+(((v3+(v2*2))+1)//3)))+4)//9)+-57)//(9*4)) - v1_val, v2_val, v3_val = v1.const_like(6), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure3(self): - v1=Variable('v1', 0, 2) - v2=Variable('v2', 0, 1) - v3=Variable('v3', 0, 2) - expr = (((((((((((((((((((0//2)//3)+v3)+0)+-4)*-2)*-2)+-1)+2)+3)+v3)+0)//8)*-3)+0)*-2)*-4)*-2)//5) - v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure4(self): - v1=Variable('v1', 0, 2) - v2=Variable('v2', 0, 3) - v3=Variable('v3', 0, 4) - expr = (((((((((((((((((((((((((((((0*-2)+0)*-1)//9)//6)//8)+v1)*-4)+v2)//4)//8)+4)*3)+v1)+v3)//8)//7)+4)+v3)*-4)+1)+v1)*3)+4)*2)//5)//2)//3)*-4) - v1_val, v2_val, v3_val = v1.const_like(2), v2.const_like(0), v3.const_like(2) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure5(self): - v1=Variable('v1', 0, 1) - v2=Variable('v2', 0, 1) - v3=Variable('v3', 0, 3) - expr = ((((((((((((((0+v2)+v1)*0)+v2)//1)//7)+-2)+v2)+v1)*4)+-3)//5)+v2)+1) - v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure6(self): - v1=Variable('v1', 0, 8) - v2=Variable('v2', 0, 64) - v3=Variable('v3', 0, 128) - expr = (((((((((((((((((((((((((((((0//3)+4)+v1)//2)+-1)//1)*1)*-1)*4)//5)+v1)//6)+v1)*-1)+-4)+v2)+-2)*-3)+v3)+-4)+-2)*-1)//8)//4)*-4)+3)+v3)* - -2)+v2) - v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(3), v3.const_like(2) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure7(self): - v1=Variable('v1', 0, 64) - v2=Variable('v2', 0, 5) - v3=Variable('v3', 0, 128) - expr = (((((((((((((((((((((((((((((0+v2)*-4)+0)//9)+-4)*-2)*3)*4)//9)+v3)+v1)//4)+v1)+v3)+-1)*4)//4)+v2)//7)//3)+v1)+v2)+v3)+1)*2)//4)*3)+-1)*1) - v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(2), v3.const_like(65) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure8(self): - v1=Variable('v1', 0, 2) - v2=Variable('v2', 0, 8) - v3=Variable('v3', 0, 9) - expr = (((((((0+-1)+2)+v1)*-2)//3)+v1)*-4) - v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure9(self): - v1=Variable('v1', 0, 256) - v2=Variable('v2', 0, 1) - v3=Variable('v3', 0, 8) - expr = (((((((((((((((((((((((((((((0*-2)//1)+3)*-2)+-3)*-4)*1)+v1)+0)%2)%8)%9)+v2)%9)+-4)//4)+-1)*-2)+0)+v1)+v1)+3)+v1)+4)+-4)+0)*2)+-3)%6) - v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(1), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) - - def test_fuzz_failure10(self): - v1=Variable("v1", 0, 256) - v2=Variable("v2", 0, 32) - v3=Variable("v3", 0, 32) - expr = UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.MAX, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - x5:=UOp(Ops.IDIV, dtypes.int, arg=None, src=( - UOp(Ops.WHERE, dtypes.int, arg=None, src=( - UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( - UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( - x9:=UOp(Ops.CONST, dtypes.int, arg=9, src=()), - x10:=UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v1', 0, 256), src=()),)), - x11:=UOp(Ops.CONST, dtypes.bool, arg=True, src=()),)), - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x10, - x14:=UOp(Ops.CONST, dtypes.int, arg=-4, src=()),)), - x14,)), - UOp(Ops.IDIV, dtypes.int, arg=None, src=( - x10, - x9,)),)), - x9,)), - x14,)), - x11,)), - x5, - UOp(Ops.IDIV, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.MOD, dtypes.int, arg=None, src=( - x19:=UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v2', 0, 32), src=()), - UOp(Ops.CONST, dtypes.int, arg=3, src=()),)), - x19,)), - UOp(Ops.CONST, dtypes.int, arg=5, src=()),)),)), - x22:=UOp(Ops.CONST, dtypes.int, arg=-1, src=()),)), - UOp(Ops.MUL, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.ADD, dtypes.int, arg=None, src=( - UOp(Ops.MOD, dtypes.int, arg=None, src=( - UOp(Ops.MUL, dtypes.int, arg=None, src=( - x10, - UOp(Ops.CONST, dtypes.int, arg=-2, src=()),)), - UOp(Ops.CONST, dtypes.int, arg=6, src=()),)), - UOp(Ops.MOD, dtypes.int, arg=None, src=( - UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v3', 0, 32), src=()), - UOp(Ops.CONST, dtypes.int, arg=1, src=()),)),)), - UOp(Ops.CONST, dtypes.int, arg=0, src=()),)), - x22,)),)), - x22,)) - v1_val, v2_val, v3_val = UOp.const(dtypes.int, 9), UOp.const(dtypes.int, 0),UOp.const(dtypes.int, 0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - self.assertEqual(num, rn) diff --git a/tinygrad/test/unit/test_symbolic_shapetracker.py b/tinygrad/test/unit/test_symbolic_shapetracker.py deleted file mode 100644 index ed065d05..00000000 --- a/tinygrad/test/unit/test_symbolic_shapetracker.py +++ /dev/null @@ -1,251 +0,0 @@ -import unittest -from tinygrad.shape.shapetracker import ShapeTracker, View -from tinygrad import Variable -from tinygrad.tensor import Tensor - -class TestSymbolic(unittest.TestCase): - def assert_tuple_equal(self, x, y): - for a,b in zip(x,y): self.assertFalse(a != b) - - def test_symbolic_st(self): - x = Variable("x", 1, 100) - st = ShapeTracker.from_shape((x, 3)) - assert st.shape == (x, 3) - assert st.real_strides() == (3, 1) - - @unittest.expectedFailure - def test_real_strides_0(self): - st = ShapeTracker(views=(View(shape=(2, (Variable('start_pos', 1, 8)+1), 1, 1), strides=(8, 1, 0, 0), offset=0, mask=((0, 2), (0, Variable('start_pos', 1, 8)), (0, 1), (0, 1)), contiguous=False), View(shape=(2, (Variable('start_pos', 1, 8)+1)), strides=((Variable('start_pos', 1, 8)+1), 1), offset=0, mask=None, contiguous=True))) # noqa: E501 - self.assertEqual(st.real_strides(), (8, None)) - - @unittest.expectedFailure - def test_real_strides_1(self): - st = ShapeTracker(views=(View(shape=(3, (Variable('i', 1, 10)+2)), strides=(Variable('i', 1, 10), 1), offset=0, mask=((0, 3), (0, Variable('i', 1, 10))), contiguous=False),)) # noqa: E501 - self.assertEqual(st.real_strides(), (Variable('i', 1, 10), None)) - - @unittest.expectedFailure - def test_real_strides_2(self): - st = ShapeTracker(views=(View(shape=(3, (Variable('i', 1, 10)+Variable('j', 1, 10))), strides=(Variable('i', 1, 10), 1), offset=0, mask=((0, 3), (0, Variable('i', 1, 10))), contiguous=False),)) # noqa: E501 - self.assertEqual(st.real_strides(), (Variable('i', 1, 10), None)) - - def test_merge_view_recursion_err(self): - vm2 = View(shape=(Variable('j', 1, 10),), strides=(0,), offset=0, mask=None, contiguous=False) - vm1 = View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True) - self.assertEqual(vm2+vm1, vm1) - - def test_merge_view_recursion_err2(self): - vm2 = View(shape=(Variable('a', 1, 10).bind(4),), strides=(0,), offset=0, mask=None, contiguous=False) - # NOTE: vm1 is different from what create function would give, and this test vm2+vm1 halts - vm1 = View(shape=(Variable('a', 1, 10).bind(4),), strides=(1,), offset=0, mask=((0, Variable('a', 1, 10).bind(4)),), contiguous=False) - self.assertEqual(vm2+vm1, None) - - vm3 = View.create(shape=(Variable('a', 1, 10).bind(4),)) - self.assertEqual(vm3.shape, vm1.shape) - self.assertEqual(vm3.strides, vm1.strides) - self.assertEqual(vm2+vm3, vm2) - - def test_cat_dim0_strides(self): - i = Variable("i", 1, 5).bind(3) - j = Variable("j", 1, 5).bind(3) - k = Variable("k", 1, 5).bind(3) - t = Tensor.rand(3, 4).reshape(i, 4).cat(Tensor.rand(3, 4).reshape(j, 4), dim=0).cat(Tensor.rand(3, 4).reshape(k, 4), dim=0) - st = t.uop.st - self.assert_tuple_equal(st.shape, (i+j+k, 4)) - assert st.real_strides() == (4, 1) - t = Tensor.rand(3, 3).reshape(i, 3).cat(Tensor.rand(3, 3).reshape(i, 3), dim=0).cat(Tensor.rand(3, 3), dim=0) - st = t.uop.st - self.assert_tuple_equal(st.shape, (2*i+3, 3)) - assert st.real_strides() == (3, 1) - - def test_cat_dim1_strides(self): - i = Variable("i", 1, 5).bind(4) - j = Variable("j", 1, 5).bind(4) - k = Variable("k", 1, 5).bind(4) - t = Tensor.rand(3, 4).reshape(3, i).cat(Tensor.rand(3, 4).reshape(3, j), dim=1).cat(Tensor.rand(3, 4).reshape(3, k), dim=1) - st = t.uop.st - self.assert_tuple_equal(st.shape, (3, i+j+k)) - self.assert_tuple_equal(st.real_strides(), (i+j+k, 1)) - -class TestSymbolicVarVals(unittest.TestCase): - def assert_equal(self, x, y): self.assertFalse(x != y) - def test_var_vals_empty(self): - assert ShapeTracker.from_shape((3, 4, 5)).var_vals == {} - - def test_var_vals_shape(self): - x = Variable("x", 1, 100).bind(3) - assert ShapeTracker.from_shape((x, 3)).var_vals == {Variable("x", 1, 100): 3} - - def test_var_vals_offset(self): - x = Variable("x", 1, 100).bind(3) - st = ShapeTracker.from_shape((4, 3)).shrink(((x, x+1), (0, 3))) - self.assert_equal(st.views[-1].offset, x * 3) - assert st.var_vals == {Variable("x", 1, 100): 3} - - def test_var_vals_mask(self): - x = Variable("x", 1, 100).bind(3) - view = View.create(shape=(3,4), strides=(4,1), offset=0, mask=((0, x), (0, 4))) - st = ShapeTracker(views=(view,)) - assert st.var_vals == {Variable("x", 1, 100): 3} - - def test_var_vals_complex(self): - x = Variable("x", 1, 100).bind(3) - y = Variable("y", 1, 100).bind(4) - z = Variable("z", 1, 100).bind(5) - st = ShapeTracker.from_shape((x, 5, y)).shrink(((0, x), (z, z+1), (0, 3))) - self.assert_equal(st.views[-1].offset, y * z) - assert st.var_vals == {Variable("x", 1, 100): 3, Variable("y", 1, 100):4, Variable("z", 1, 100): 5} - - def test_shrink_reshape(self): - x = Variable("x", 1, 100).bind(3) - st = ShapeTracker.from_shape((10, 10, 10)).shrink(((x, x+3), (3, 7), (2, 5))) - st = st.reshape((3*4*3,)) - assert st.var_vals == {Variable("x", 1, 100): 3} - -class TestShapeTrackerUnbind(unittest.TestCase): - def test_view_unbind(self): - v = Variable("v", 1, 100) - bv = Variable("v", 1, 100).bind(3) - unbound_view, var_val = View.create(shape=(bv, 4)).unbind() - assert unbound_view == View.create(shape=(v, 4)) - assert var_val == {v: 3} - - def test_reshape_unbind(self): - v = Variable("v", 1, 100) - bv = Variable("v", 1, 100).bind(3) - t = Tensor.rand(3, 4).reshape(bv, 4) - unbound_st, var_val = t.uop.st.unbind() - assert unbound_st == ShapeTracker((View.create(shape=(v, 4)),)) - assert var_val == {v: 3} - - def test_shrink_unbind(self): - v = Variable("v", 1, 100) - bv = Variable("v", 1, 100).bind(2) - t = Tensor.rand(3, 4).shrink(((bv, bv+1), (0, 4))) - unbound_st, var_val = t.uop.st.unbind() - assert unbound_st == ShapeTracker((View.create(shape=(1, 4), offset=4*v),)) - assert var_val == {v: 2} - -class TestSymbolicReshapeFromContiguous(unittest.TestCase): - def test_reshape_into_symbols_simple(self): - for i in range(1, 6): - vi = Variable("i", 1, 5).bind(i) - t = Tensor.rand(i, 4).reshape(vi, 4) - assert t.shape == (vi, 4) - t = Tensor.rand(i, 6).reshape(vi, 2, 3) - assert t.shape == (vi, 2, 3) - - def test_reshape_symbols_reshape_ints(self): - for i in range(1, 6): - vi = Variable("i", 1, 5).bind(i) - t = Tensor.rand(i, 4).reshape(vi, 4) - assert t.shape == (vi, 4) - t = t.reshape(i, 4) - assert t.shape == (i, 4) - - @unittest.skip("works now") - def test_reshape_into_symbols_bad_shape(self): - vi = Variable("i", 1, 10).bind(4) - # TODO: this never actually worked, it relied on lazy - #with self.assertRaises(ValueError): - # Tensor.rand(4, 6).reshape(vi, 6).reshape(1, 77) # reshape to a different size new shape through symbolic shape - with self.assertRaises(AssertionError): - Tensor.rand(3, 4).reshape(3, (vi+1)) # reshape into non-Variable Node - - def test_two_symbol_reshape(self): - for i in range(1, 6): - for j in range(1, 6): - vi = Variable("i", 1, 5).bind(i) - vj = Variable("j", 1, 5).bind(j) - t = Tensor.rand(i, j).reshape(vi, vj) - assert t.shape == (vi, vj) - # NOTE: this is currently not allowed - # t = t.reshape(1, vi*vj) - # assert t.shape == (1, vi*vj) - t = t.reshape(vj, vi) - assert t.shape == (vj, vi) - - def test_symbolic_mask(self): - # taken from gpt2 single kvcache - # these two caused problems in gpt2 if reshape merged views - view = View(shape=(1, (Variable('start_pos', 1, 128).bind(2)+1), 16, 64), strides=(0, 0, 64, 1), offset=1024, mask=((0, 1), (Variable('start_pos', 1, 128).bind(2), (Variable('start_pos', 1, 128).bind(2)+1)), (0, 16), (0, 64)), contiguous=False) # noqa: E501 - new_shape = (1, 1, (Variable('start_pos', 1, 128).bind(2)+1), 16, 64) - assert view.reshape(new_shape) is None - - view = View(shape=(2, 1, (Variable('start_pos', 1, 128)+1), 16, 64), strides=(0, 0, 1024, 64, 1), offset=131072, mask=((1, 2), (0, 1), (0, (Variable('start_pos', 1, 128)+1)), (0, 16), (0, 64)), contiguous=False) # noqa: E501 - new_shape = (2, (Variable('start_pos', 1, 128)+1), 16, 64) - assert view.reshape(new_shape) is None - -class TestSymbolicReshapeFromNonContiguous(unittest.TestCase): - def test_reshape_from_const(self): - vi = Variable("i", 1, 5).bind(4) - t = Tensor.ones(3, 4).reshape(3, vi) - assert t.shape == (3, vi) - assert not t.uop.st.contiguous - assert len(t.uop.st.views) == 1 - - def test_reshape_not_allowed(self): - vi = Variable("i", 1, 5).bind(4) - with self.assertRaises(ValueError): - # different shape length # TODO: cases where contractions matched might be fine - Tensor.ones(3, 4, 1).reshape(3, vi) - with self.assertRaises(ValueError): - # size matched, but dimensions do not match - Tensor.ones(4, 3).reshape(3, vi) - - def test_reshape_from_padded(self): - vi = Variable("i", 1, 5).bind(4) - t = Tensor.ones(3, 4).contiguous().expand(2, 3, 4).pad(((1, 1), None, None)).shrink((None, None, (1, 3))) - st = t.uop.st - assert len(st.views) == 1 - view = st.views[0] - assert view.shape == (4, 3, 2) - t = t.reshape(vi, 3, 2) - st2 = t.uop.st - assert len(st2.views) == 1 - view2 = st2.views[0] - # check only shape changed. strides, offset, mask, contiguous remained the same - assert view2.shape == (vi, 3, 2) - assert view.strides == view2.strides == (0, 4, 1) - assert view.offset == view2.offset == 1 - assert view.mask == view2.mask == ((1, 3), (0, 3), (0, 2)) - assert not view.contiguous and not view2.contiguous - -class TestSymbolicExpand(unittest.TestCase): - def test_expand_into_symbols(self): - vi = Variable("i", 1, 5).bind(3) - vj = Variable("j", 1, 5).bind(3) - a = Tensor([[1], [2], [3]]).expand((3, vi)) - assert a.shape == (3, vi) - a = a.reshape(3, vi, 1).expand((3, vi, vj)) - assert a.shape == (3, vi, vj) - - def test_plus_expands_constant(self): - for i in range(1, 6): - vi = Variable("i", 1, 5).bind(i) - a = Tensor.rand(3, i).reshape(3, vi) - a = a + 1 - self.assertTupleEqual(a.shape, (3, vi)) - - def test_pad_then_expand_into_symbols(self): - vi = Variable("i", 1, 10).bind(3) - a = Tensor(1).unsqueeze(0).pad((0, 24)).unsqueeze(0).expand((vi, 25)) - self.assertEqual(a.shape, (vi, 25)) - self.assertEqual(a.reshape(25*vi).shape, (vi*25,)) - self.assertEqual(a.reshape(vi*25).shape, (vi*25,)) - -class TestSymbolicShrink(unittest.TestCase): - def test_shrink_symbols(self): - vi = Variable("i", 1, 5) - t = Tensor.rand(3, 5).shrink(((0, 2), (vi, vi+1))) - assert t.shape == (2, 1) - -class TestSymbolicPad(unittest.TestCase): - def test_pad(self): - v = Variable("v", 1, 100).bind(5) - t = Tensor.ones(5).reshape(v).pad(((4, 0),)).reshape(9) - assert t.shape == (9,) - st = t.uop.st - print(st) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_tar.py b/tinygrad/test/unit/test_tar.py deleted file mode 100644 index 42f00d16..00000000 --- a/tinygrad/test/unit/test_tar.py +++ /dev/null @@ -1,141 +0,0 @@ -import unittest, tarfile, io, os, pathlib, tempfile -import numpy as np -from tinygrad import Tensor -from tinygrad.nn.state import tar_extract - -class TestTarExtractFile(unittest.TestCase): - def setUp(self): - self.test_dir = tempfile.mkdtemp() - self.test_files = { - 'file1.txt': b'Hello, World!', - 'file2.bin': b'\x00\x01\x02\x03\x04', - 'empty_file.txt': b'' - } - self.tar_path = os.path.join(self.test_dir, 'test.tar') - with tarfile.open(self.tar_path, 'w') as tar: - for filename, content in self.test_files.items(): - file_path = os.path.join(self.test_dir, filename) - with open(file_path, 'wb') as f: - f.write(content) - tar.add(file_path, arcname=filename) - - # Create invalid tar file - self.invalid_tar_path = os.path.join(self.test_dir, 'invalid.tar') - with open(self.invalid_tar_path, 'wb') as f: - f.write(b'This is not a valid tar file') - - def tearDown(self): - for filename in self.test_files: - os.remove(os.path.join(self.test_dir, filename)) - os.remove(self.tar_path) - os.remove(self.invalid_tar_path) - os.rmdir(self.test_dir) - - def test_tar_extract_returns_dict(self): - result = tar_extract(self.tar_path) - self.assertIsInstance(result, dict) - - def test_tar_extract_correct_keys(self): - result = tar_extract(self.tar_path) - self.assertEqual(set(result.keys()), set(self.test_files.keys())) - - def test_tar_extract_content_size(self): - result = tar_extract(self.tar_path) - for filename, content in self.test_files.items(): - self.assertEqual(len(result[filename]), len(content)) - - def test_tar_extract_content_values(self): - result = tar_extract(self.tar_path) - for filename, content in self.test_files.items(): - np.testing.assert_array_equal(result[filename].numpy(), np.frombuffer(content, dtype=np.uint8)) - - def test_tar_extract_empty_file(self): - result = tar_extract(self.tar_path) - self.assertEqual(len(result['empty_file.txt']), 0) - - def test_tar_extract_non_existent_file(self): - with self.assertRaises(FileNotFoundError): - tar_extract('non_existent_file.tar') - - def test_tar_extract_invalid_file(self): - with self.assertRaises(tarfile.ReadError): - tar_extract(self.invalid_tar_path) - -class TestTarExtractPAX(unittest.TestCase): - tar_format = tarfile.PAX_FORMAT - max_link_len = 1000_000 - test_files = { - 'a/file1.txt': b'Hello, World!', - 'a/b/file2.bin': b'\x00\x01\x02\x03\x04', - 'empty_file.txt': b'', - '512file': b'a' * 512, - 'long_file': b'some data' * 100, - 'very' * 15 + '/' + 'very' * 15 + '_long_filename.txt': b'Hello, World!!', - 'very' * 200 + '_long_filename.txt': b'Hello, World!!!', - } - - def create_tar_tensor(self): - fobj = io.BytesIO() - test_dirs = set(os.path.dirname(k) for k in self.test_files.keys()).difference({ '' }) - with tarfile.open(fileobj=fobj, mode='w', format=self.tar_format) as tar: - for dirname in test_dirs: - dir_info = tarfile.TarInfo(name=dirname) - dir_info.type = tarfile.DIRTYPE - tar.addfile(dir_info) - - for filename, content in self.test_files.items(): - file_info = tarfile.TarInfo(name=filename) - file_info.size = len(content) - tar.addfile(file_info, io.BytesIO(content)) - - if len(filename) < self.max_link_len: - link_info = tarfile.TarInfo(name=filename + '.lnk') - link_info.type = tarfile.SYMTYPE - link_info.linkname = filename - tar.addfile(link_info) - return Tensor(fobj.getvalue()) - - def test_tar_extract_returns_dict(self): - result = tar_extract(self.create_tar_tensor()) - self.assertIsInstance(result, dict) - - def test_tar_extract_correct_keys(self): - result = tar_extract(self.create_tar_tensor()) - self.assertEqual(set(result.keys()), set(self.test_files.keys())) - - def test_tar_extract_content_size(self): - result = tar_extract(self.create_tar_tensor()) - for filename, content in self.test_files.items(): - self.assertEqual(len(result[filename]), len(content)) - - def test_tar_extract_content_values(self): - result = tar_extract(self.create_tar_tensor()) - for filename, content in self.test_files.items(): - np.testing.assert_array_equal(result[filename].numpy(), np.frombuffer(content, dtype=np.uint8)) - - def test_tar_extract_empty_file(self): - result = tar_extract(self.create_tar_tensor()) - self.assertEqual(len(result['empty_file.txt']), 0) - - def test_tar_extract_non_existent_file(self): - with self.assertRaises(FileNotFoundError): - tar_extract(Tensor(pathlib.Path('non_existent_file.tar'))) - - def test_tar_extract_invalid_file(self): - with self.assertRaises(tarfile.ReadError): - tar_extract(Tensor(b'This is not a valid tar file')) - - def test_tar_extract_invalid_file_long(self): - with self.assertRaises(tarfile.ReadError): - tar_extract(Tensor(b'This is not a valid tar file'*100)) - -class TestTarExtractUSTAR(TestTarExtractPAX): - tar_format = tarfile.USTAR_FORMAT - max_link_len = 100 - test_files = {k: v for k, v in TestTarExtractPAX.test_files.items() if len(k) < 256} - -class TestTarExtractGNU(TestTarExtractPAX): - tar_format = tarfile.GNU_FORMAT - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_tensor_io.py b/tinygrad/test/unit/test_tensor_io.py deleted file mode 100644 index a8392572..00000000 --- a/tinygrad/test/unit/test_tensor_io.py +++ /dev/null @@ -1,38 +0,0 @@ -import unittest -from tinygrad import Tensor, dtypes -from tinygrad.nn.state import TensorIO - -class TestTensorIO(unittest.TestCase): - def test_create(self): - with self.assertRaises(ValueError): - TensorIO(Tensor(b"Hello World").reshape(1, -1)) - with self.assertRaises(ValueError): - TensorIO(Tensor([], dtype=dtypes.int64).reshape(1, -1)) - - def test_seek(self): - t = Tensor(b"Hello World!") - fobj = TensorIO(t) - self.assertEqual(fobj.tell(), 0) - self.assertEqual(fobj.seek(1), 1) - self.assertEqual(fobj.seek(-2, 2), len(t) - 2) - self.assertEqual(fobj.seek(1, 1), len(t) - 1) - self.assertEqual(fobj.seek(10, 1), len(t)) - self.assertEqual(fobj.seek(10, 2), len(t)) - self.assertEqual(fobj.seek(-10, 0), 0) - - def test_read(self): - data = b"Hello World!" - fobj = TensorIO(Tensor(data)) - self.assertEqual(fobj.read(1), data[:1]) - self.assertEqual(fobj.read(5), data[1:6]) - self.assertEqual(fobj.read(100), data[6:]) - self.assertEqual(fobj.read(100), b"") - - def test_read_nolen(self): - data = b"Hello World!" - fobj = TensorIO(Tensor(data)) - fobj.seek(2) - self.assertEqual(fobj.read(), data[2:]) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_tensor_uop_representation.py b/tinygrad/test/unit/test_tensor_uop_representation.py deleted file mode 100644 index a2dacee1..00000000 --- a/tinygrad/test/unit/test_tensor_uop_representation.py +++ /dev/null @@ -1,127 +0,0 @@ -import unittest -from tinygrad import Tensor -from tinygrad.uop.ops import UPat, Ops, UOp - -# NOTE: unlike before base for a realized tensor is always a BUFFER -realized_pattern = UPat(Ops.BUFFER) -# after realization, base tensor uops become RESHAPE(BUFFER) -buffer_view_pattern = UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),)) -const_pattern = UPat(Ops.CONST, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),),))) -def is_pattern_uop(u:UOp, pat:UPat): assert pat.match(u, {}), f"{u}\nis not\n{pat}" -def is_pattern(ten:Tensor, pat:UPat): is_pattern_uop(ten.uop, pat) - -class TestTensorMutates(unittest.TestCase): - def test_mutate_add(self): - a = Tensor([1,2,3]) - b = Tensor([4,5,6]) - ret = a+b - pa = a.uop - pb = b.uop - pr = ret.uop - ret.schedule() - self.assertIsNot(pa, a.uop) - self.assertIsNot(pb, b.uop) - self.assertIsNot(pr, ret.uop) - for t in [a,b,ret]: is_pattern_uop(t.uop.base, realized_pattern) - - def test_reshape_is_same_parent(self): - a = Tensor([1,2,3]) - b = Tensor([4,5,6]) - c = a+b - d = (a+b).reshape(3,1) - d.realize() - is_pattern_uop(d.uop.base, realized_pattern) - is_pattern_uop(c.uop.base, realized_pattern) - # NOTE: we keep movement ops on top of the buffer view - is_pattern_uop(c.uop, UPat(Ops.BUFFER)) - is_pattern_uop(d.uop, UPat(Ops.VIEW, src=(realized_pattern,))) - - def test_reshape_is_same_child(self): - a = Tensor([1,2,3]) - b = Tensor([4,5,6]) - c = a+b - d = (a+b).reshape(3,1) - c.realize() - is_pattern_uop(c.uop.base, realized_pattern) - is_pattern_uop(d.uop.base, realized_pattern) - -class TestTensorUopRepresentation(unittest.TestCase): - def test_realized(self): - a = Tensor([1.,2,3]).realize() - print(a.uop) - is_pattern_uop(a.uop.base, realized_pattern) - - def test_add_realized(self): - a = Tensor([1.,2,3]).realize() - b = Tensor([4.,5,6]).realize() - c = a+b - print(c.uop) - is_pattern(c, UPat(Ops.ADD, src=(realized_pattern, realized_pattern))) - - def test_const_pattern(self): - a = Tensor(1) - print(a.uop) - is_pattern(a, const_pattern) # const in tensor has a DEVICE and VIEW src - is_pattern(a, UPat.cvar("x")) # even cvar works! - - def test_consts_do_not_realize(self): - a = Tensor(1) - print(a.uop) - pre_realize = a.uop - a.realize() - assert a.uop is pre_realize - - def test_viewed_consts_do_not_realize(self): - a = Tensor.ones(10, 10) - print(a.uop) - a.realize() - is_pattern(a, const_pattern) - self.assertEqual(a.uop.shape, (10, 10)) - - # currently, CONSTs have a "fake" BUFFER. this should be fixed - # current: - # UOp(Ops.EXPAND, dtypes.float, arg=(10, 10), src=( - # UOp(Ops.RESHAPE, dtypes.float, arg=(1, 1), src=( - # UOp(Ops.VIEW, dtypes.float, arg=ShapeTracker(views=(View(shape=(), strides=(), offset=0, mask=None, contiguous=True),)), src=( - # UOp(Ops.BUFFER, dtypes.float, arg=(-1, 'METAL', 1), src=()), - # UOp(Ops.CONST, dtypes.float, arg=1.0, src=()),)),)),)) - # expected: - # UOp(Ops.EXPAND, dtypes.float, arg=(10, 10), src=( - # UOp(Ops.RESHAPE, dtypes.float, arg=(1, 1), src=( - # UOp(Ops.VIEW, dtypes.float, arg=ShapeTracker(views=(View(shape=(), strides=(), offset=0, mask=None, contiguous=True),)), src=( - # UOp(Ops.CONST, dtypes.float, arg=1.0, src=( - # UOp(Ops.DEVICE, dtypes.void, arg="METAL", src=()),)),)),)) - def test_consts_dont_have_buffers(self): - a = Tensor.ones(10, 10) - print(a.uop) - buffers_in_parents = [x.op for x in a.uop.toposort() if x.op is Ops.BUFFER] - self.assertEqual(len(buffers_in_parents), 0) - - # currently, COPY has an extra BUFFER on the output - # current: - # UOp(Ops.VIEW, dtypes.float, arg=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)), src=( - # UOp(Ops.BUFFER, dtypes.float, arg=(2, 'TEST', 3), src=()), - # UOp(Ops.COPY, dtypes.float, arg=('TEST', False), src=( - # UOp(Ops.VIEW, dtypes.float, arg=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)), src=( - # UOp(Ops.BUFFER, dtypes.float, arg=(1, 'METAL', 3), src=()),)),)),)) - # expected: - # UOp(Ops.COPY, dtypes.float, arg=('TEST', False), src=( - # UOp(Ops.VIEW, dtypes.float, arg=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)), src=( - # UOp(Ops.BUFFER, dtypes.float, arg=(1, 'METAL', 3), src=()),)) - # update: now the arg is just a single bool, the first source is a device. - def test_copyin(self): - a = Tensor([1.,2,3]).realize() - c = a.to("TEST") # NOTE: this isn't checked - print(c.uop) - is_pattern(c, UPat(Ops.COPY, src=(realized_pattern, UPat(Ops.DEVICE)))) - - def test_empty_buf(self): - a = Tensor.empty(3, 3) - is_pattern(a, UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),))) - vi = UOp.variable("i", 1, 3).bind(1) - a = Tensor.empty(3, vi) - is_pattern(a, UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),))) - self.assertEqual(a.uop.base.buffer.size, 9) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_tqdm.py b/tinygrad/test/unit/test_tqdm.py deleted file mode 100644 index 9d7b3756..00000000 --- a/tinygrad/test/unit/test_tqdm.py +++ /dev/null @@ -1,310 +0,0 @@ -import time, random, unittest, itertools -from unittest.mock import patch -from io import StringIO -from collections import namedtuple -from tqdm import tqdm -from tinygrad.helpers import tqdm as tinytqdm, trange as tinytrange -import numpy as np - -def _get_iter_per_second(raw:str) -> float: - # raw might have unit scale - if raw.endswith("k"): return float(raw[:-1])*1e3 - if raw.endswith("M"): return float(raw[:-1])*1e6 - return float(raw) - -# TODO: _get_iter_per_second in test_unit_scale might fail if lower bound is too small -NCOLS_RANGE = [80, 240] - -class TestProgressBar(unittest.TestCase): - def _compare_bars(self, bar1, bar2): - prefix1, prog1, suffix1 = bar1.split("|") - prefix2, prog2, suffix2 = bar2.split("|") - - self.assertEqual(len(bar1), len(bar2)) - self.assertEqual(prefix1, prefix2) - - def parse_timer(timer): return sum(int(x) * y for x, y in zip(timer.split(':')[::-1], (1, 60, 3600))) - - if "?" not in suffix1 and "?" not in suffix2: - # allow for few sec diff in timers (removes flakiness) - timer1, rm1 = [parse_timer(timer) for timer in suffix1.split("[")[-1].split(",")[0].split("<")] - timer2, rm2 = [parse_timer(timer) for timer in suffix2.split("[")[-1].split(",")[0].split("<")] - np.testing.assert_allclose(timer1, timer2, atol=5, rtol=1e-2) - np.testing.assert_allclose(rm1, rm2, atol=5, rtol=1e-2) - - # get suffix without timers - suffix1 = suffix1.split("[")[0] + suffix1.split(",")[1] - suffix2 = suffix2.split("[")[0] + suffix2.split(",")[1] - self.assertEqual(suffix1, suffix2) - else: - self.assertEqual(suffix1, suffix2) - - diff = sum([c1 != c2 for c1, c2 in zip(prog1, prog2)]) # allow 1 char diff to be less flaky, but it should match - assert diff <= 1, f"{diff=}\n{prog1=}\n{prog2=}" - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_output_iter(self, mock_terminal_size, mock_stderr): - for _ in range(10): - total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - for n in (bar := tinytqdm(range(total), desc="Test")): - if bar.i % bar.skip != 0: continue - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = n/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tinytqdm_output, tqdm_output) - - # compare final bars - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = total/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tinytqdm_output, tqdm_output) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_unit_scale(self, mock_terminal_size, mock_stderr): - for unit_scale in [True, False]: - # NOTE: numpy comparison raises TypeError if exponent > 22 - for exponent in range(1, 22, 3): - low, high = 10 ** exponent, 10 ** (exponent+1) - for _ in range(5): - total, ncols = random.randint(low, high), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - # setting high rate to make sure it does not skip - for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=1e9): - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - - if n: - iters_per_sec = _get_iter_per_second(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) - elapsed = n/iters_per_sec - else: - elapsed = 0 - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) - self._compare_bars(tinytqdm_output, tqdm_output) - if n > 3: break - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_unit_scale_exact(self, mock_terminal_size, mock_stderr): - unit_scale = True - ncols = 80 - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - total = 10 - with patch('time.perf_counter', side_effect=[0]+list(range(100))): # one more 0 for the init call - # compare bars at each iteration (only when tinytqdm bar has been updated) - for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=1e9): - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - elapsed = n - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) - self._compare_bars(tinytqdm_output, tqdm_output) - if n > 5: break - - total = 10 - k=0.001000001 - # regression test for - # E AssertionError: ' 1.00/10.0 1000it/s]' != ' 1.00/10.0 1.00kit/s]' - # E - 1.00/10.0 1000it/s] - # E ? ^ - # E + 1.00/10.0 1.00kit/s] - # E ? + ^ - with patch('time.perf_counter', side_effect=[0, *[i*k for i in range(100)]]): # one more 0 for the init call - # compare bars at each iteration (only when tinytqdm bar has been updated) - for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=1e9): - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - elapsed = n*k - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) - self._compare_bars(tinytqdm_output, tqdm_output) - if n > 5: break - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_set_description(self, mock_terminal_size, mock_stderr): - for _ in range(10): - total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - expected_prefix = "Test" - # compare bars at each iteration (only when tinytqdm bar has been updated) - for i,n in enumerate(bar := tinytqdm(range(total), desc="Test")): - if bar.i % bar.skip != 0: continue - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = n/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix=expected_prefix) - expected_prefix = desc = f"Test {i}" if i % 2 == 0 else "" - bar.set_description(desc) - self._compare_bars(tinytqdm_output, tqdm_output) - - # compare final bars - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = total/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix=expected_prefix) - self._compare_bars(tinytqdm_output, tqdm_output) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_trange_output_iter(self, mock_terminal_size, mock_stderr): - for _ in range(5): - total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - for n in (bar := tinytrange(total, desc="Test")): - if bar.i % bar.skip != 0: continue - tiny_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tiny_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = n/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tiny_output, tqdm_output) - - # compare final bars - tiny_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tiny_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = total/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tiny_output, tqdm_output) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_output_custom(self, mock_terminal_size, mock_stderr): - for _ in range(10): - total, ncols = random.randint(10000, 1000000), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - bar = tinytqdm(total=total, desc="Test") - n = 0 - while n < total: - incr = (total // 100) + random.randint(0, 1000) - if n + incr > total: incr = total - n - bar.update(incr, close=n+incr==total) - n += incr - if bar.i % bar.skip != 0: continue - - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = n/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tinytqdm_output, tqdm_output) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_output_custom_0_total(self, mock_terminal_size, mock_stderr): - for _ in range(10): - total, ncols = random.randint(10000, 100000), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - bar = tinytqdm(total=0, desc="Test") - n = 0 - while n < total: - incr = (total // 10) + random.randint(0, 100) - if n + incr > total: incr = total - n - bar.update(incr, close=n+incr==total) - n += incr - if bar.i % bar.skip != 0: continue - - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 - elapsed = n/iters_per_sec if n>0 else 0 - tqdm_output = tqdm.format_meter(n=n, total=0, elapsed=elapsed, ncols=ncols, prefix="Test") - self.assertEqual(tinytqdm_output, tqdm_output) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_output_custom_nolen_total(self, mock_terminal_size, mock_stderr): - for unit_scale in [True, False]: - for _ in range(5): - gen = itertools.count(0) - ncols = random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - # compare bars at each iteration (only when tinytqdm bar has been updated) - # setting high rate to make sure it does not skip - for n,g in enumerate(tinytqdm(gen, desc="Test", unit_scale=unit_scale, rate=1e9)): - assert g == n - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - if n: - iters_per_sec = _get_iter_per_second(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) - elapsed = n/iters_per_sec - else: - elapsed = 0 - tqdm_output = tqdm.format_meter(n=n, total=0, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) - self.assertEqual(tinytqdm_output, tqdm_output) - if n > 5: break - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_write(self, mock_terminal_size, mock_stderr): - for _ in range(5): - ncols, tqdm_fp = random.randint(*NCOLS_RANGE), StringIO() - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - tqdm_fp.truncate(0) - for i in tinytqdm(range(10)): - time.sleep(0.01) - tinytqdm.write(str(i)) - tqdm.write(str(i), file=tqdm_fp) - tinytqdm_out, tqdm_out = mock_stderr.getvalue(), tqdm_fp.getvalue() - self.assertEqual(tinytqdm_out.split("\r\033[K")[-1], tqdm_out.split(f"{i-1}\n")[-1]) - self.assertEqual(tinytqdm_out, tinytqdm_out) - - @patch('sys.stderr', new_callable=StringIO) - @patch('shutil.get_terminal_size') - def test_tqdm_context_manager(self, mock_terminal_size, mock_stderr): - for _ in range(10): - total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) - mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) - mock_stderr.truncate(0) - - with tinytqdm(desc="Test", total=total) as bar: - for _ in range(total): - bar.update(1) - - tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() - iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) - elapsed = total/iters_per_sec - tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") - self._compare_bars(tinytqdm_output, tqdm_output) - - def test_tqdm_perf(self): - st = time.perf_counter() - for _ in tqdm(range(100)): pass - tqdm_time = time.perf_counter() - st - - st = time.perf_counter() - for _ in tinytqdm(range(100)): pass - tinytqdm_time = time.perf_counter() - st - - assert tinytqdm_time < 2 * tqdm_time - - def test_tqdm_perf_high_iter(self): - st = time.perf_counter() - for _ in tqdm(range(10^7)): pass - tqdm_time = time.perf_counter() - st - - st = time.perf_counter() - for _ in tinytqdm(range(10^7)): pass - tinytqdm_time = time.perf_counter() - st - - assert tinytqdm_time < 5 * tqdm_time - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_transcendental_helpers.py b/tinygrad/test/unit/test_transcendental_helpers.py deleted file mode 100644 index 16a97ad4..00000000 --- a/tinygrad/test/unit/test_transcendental_helpers.py +++ /dev/null @@ -1,109 +0,0 @@ -import unittest, math -import numpy as np -from tinygrad import dtypes -from tinygrad.uop.ops import UOp, Ops -from tinygrad.codegen.transcendental import TRANSCENDENTAL_SUPPORTED_DTYPES, payne_hanek_reduction, cody_waite_reduction -from tinygrad.codegen.transcendental import frexp, rintk, xpow, xexp2, xlog2, trig_poly, pow2if -from test.helpers import eval_uop - -class TestTranscendentalFunctions(unittest.TestCase): - def test_payne_hanek_reduction(self): - # TODO: Test constant input when constant folding is fixed (or maybe test both variants) - # Load input value from a buffer to prevent constant folding - input_buf = UOp(Ops.DEFINE_GLOBAL, dtypes.double.ptr(), arg=1, src=()) - loaded_value = UOp.load(input_buf.index(UOp.const(dtypes.int, 0)), dtype=dtypes.double) - def eval_payne_hanek_reduction(v:float) -> tuple[float, int]: - return tuple(eval_uop(u, [(dtypes.float64, [v])]) for u in payne_hanek_reduction(loaded_value)) - - r, q = eval_payne_hanek_reduction(12 * math.pi + 0.1) - np.testing.assert_allclose(r, 0.1 - math.pi / 2) - np.testing.assert_equal(q, 1) - - r, q = eval_payne_hanek_reduction(12 * math.pi) - np.testing.assert_allclose(r, 0.0, atol=1e-8) - np.testing.assert_equal(q, 4) - - r, q = eval_payne_hanek_reduction(12 * math.pi - 0.1) - np.testing.assert_allclose(r, -0.1) - np.testing.assert_equal(q, 4) - - def test_cody_waite_reduction(self): - r, q = (eval_uop(u) for u in cody_waite_reduction(UOp.const(dtypes.float64, 12 * math.pi + 0.1))) - np.testing.assert_allclose(r, 0.1) - np.testing.assert_equal(q, 12) - - def test_frexp(self): - for x in (1, -1): - mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, x))) - np.testing.assert_equal(mantissa, 0.5) - np.testing.assert_equal(exponent, 1) - - for x in (2, -2): - mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 2.0))) - np.testing.assert_equal(mantissa, 0.5) - np.testing.assert_equal(exponent, 2) - - mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 5.0))) - np.testing.assert_equal(mantissa, 0.625) - np.testing.assert_equal(exponent, 3) - - mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 1000.0))) - np.testing.assert_allclose(mantissa, 0.9765625) - np.testing.assert_equal(exponent, 10) - - def test_rintk(self): - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 0.0))), 0) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.0))), 5) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.5))), 6) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.999))), 6) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.0))), -5) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.5))), -6) - np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.999))), -6) - - def test_pow2if(self): - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 0), dtypes.float)), 1.0) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 1), dtypes.float)), 2.0) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 2), dtypes.float)), 4.0) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 10), dtypes.float)), 1024.0) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 63), dtypes.float)), 2**63) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -1), dtypes.float)), 0.5) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -2), dtypes.float)), 0.25) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -10), dtypes.float)), 2**-10) - np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -63), dtypes.float)), 2**-63) - -class TestTranscendentalVectorizedFunctions(unittest.TestCase): - # given a scalar and vectorized input, check that the fxn outputs have the same - # scalar_dtypes, args, ops, and vcount (only for vectorized input) - - def _check_uop_vcount(self, u:tuple|UOp, vcount:int): - # check all UOps in u are vectorized with vcount - if isinstance(u, UOp): - assert u.dtype.vcount == vcount, f'expected {vcount=} but got {u.dtype.vcount=} for UOp\n{u=}' - [self._check_uop_vcount(x, vcount) for x in (u if isinstance(u, tuple) else u.src)] - - def _check_uops_match(self, u1:tuple|UOp, u2:tuple|UOp): - # check all UOps in u1, u2 have the same scalar_dtype, args, ops - if isinstance(u1, UOp) and isinstance(u2, UOp): - assert u1.dtype.scalar() == u2.dtype.scalar(), f'expected {u1.dtype.scalar()=} but got {u2.dtype.scalar()=} for UOps\n{u1=}\n{u2}' - assert u1.arg == u2.arg or (math.isnan(u1.arg) and math.isnan(u2.arg)), f'expected {u1.arg=} but got {u2.arg=} for UOps\n{u1=}\n{u2}' - assert u1.op == u2.op, f'expected {u1.op=} but got {u2.op=} for UOps\n{u1=}\n{u2}' - [self._check_uops_match(x1, x2) for x1, x2 in zip((u1 if isinstance(u1, tuple) else u1.src), (u2 if isinstance(u2, tuple) else u2.src))] - - def _test_vectorized(self, fxn, scalar_dtypes=TRANSCENDENTAL_SUPPORTED_DTYPES, vals=[-2,1.3,194], vcounts=[1,4,19]): - for scalar_dtype in scalar_dtypes: - for val in vals: - for vcount in vcounts: - in_scalar, in_vec = UOp.const(scalar_dtype, val), UOp.const(scalar_dtype.vec(vcount), val) - out_scalar, out_vec = fxn(in_scalar), fxn(in_vec) - self._check_uops_match(out_scalar, out_vec) - self._check_uop_vcount(out_vec, vcount) - - def test_xpow(self): return self._test_vectorized(lambda x: xpow(x, x)) - def test_xexp2(self): return self._test_vectorized(xexp2) - def test_xlog2(self): return self._test_vectorized(xlog2) - def test_payne_hanek_reduction(self): return self._test_vectorized(payne_hanek_reduction) - def test_cody_waite_reduction(self): return self._test_vectorized(cody_waite_reduction) - def test_trig_poly(self): return self._test_vectorized(lambda x: trig_poly(x, [0.0], [1.0])) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_uop_resolve.py b/tinygrad/test/unit/test_uop_resolve.py deleted file mode 100644 index 83db0331..00000000 --- a/tinygrad/test/unit/test_uop_resolve.py +++ /dev/null @@ -1,125 +0,0 @@ -import unittest -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UOp, resolve - -class TestUOpResolve(unittest.TestCase): - def test_simple_int(self): - u = UOp.const(dtypes.int, 4) - self.assertEqual(int(u), 4) - - def test_int_add(self): - u = UOp.const(dtypes.int, 4) + 7 - self.assertEqual(int(u), 11) - - def test_lt(self): - u = UOp.const(dtypes.int, 4) < 7 - self.assertTrue(u) - - def test_rfloordiv(self): - u = 8 // UOp.const(dtypes.int, 4) - self.assertEqual(int(u), 2) - - def test_rtruediv(self): - u = 9 / UOp.const(dtypes.float, 4) - self.assertEqual(float(u), 2.25) - - def test_leq(self): - u = UOp.const(dtypes.int, 4) <= 4 - self.assertTrue(u) - - def test_ne(self): - u = UOp.const(dtypes.int, 4) != 7 - self.assertTrue(u) - - def test_ne_f(self): - u = UOp.const(dtypes.int, 4) != 4 - self.assertFalse(u) - - def test_ngt(self): - u = UOp.const(dtypes.int, 4) > 7 - self.assertFalse(u) - - def test_ssimplify(self): - self.assertEqual((8 % UOp.const(dtypes.int, 4)).ssimplify(), 0) - self.assertEqual((8 * UOp.const(dtypes.int, 4)).ssimplify(), 32) - - def test_ambiguous_less_than(self): - u = UOp.variable("i", 1, 10) - self.assertTrue(resolve(u < 4)) - self.assertFalse(resolve(u < 4, False)) - self.assertTrue(resolve(u < 11, False)) - self.assertFalse(resolve(u < -1, False)) - self.assertFalse(resolve(u < -1, True)) - - def test_float_direct(self): - u = UOp.const(dtypes.float, 4.5) + 7 - self.assertEqual(float(u), 11.5) - - def test_var_cmp_t(self): - u = UOp.variable("i", 1, 10) < 20 - self.assertTrue(u) - - def test_var_cmp_t2(self): - u = UOp.variable("i", 1, 10)//2 < 20 - self.assertTrue(u) - - def test_var_cmp_f(self): - u = UOp.variable("i", 1, 10) < 1 - self.assertFalse(u) - - def test_var_cmp_f2(self): - u = UOp.variable("i", 1, 10) > 11 - self.assertFalse(u) - - def test_or_true(self): - u = UOp.variable("b", False, True, dtypes.bool) | True - self.assertTrue(u) - - def test_or_false(self): - with self.assertRaises(ValueError): - u = UOp.variable("b", False, True, dtypes.bool) | False - self.assertTrue(u) - - def test_and_false(self): - u = UOp.variable("b", False, True, dtypes.bool) & False - self.assertFalse(u) - - def test_max(self): - x = UOp.variable("x", 1, 10) - y = UOp.variable("y", 5, 10) - u = x.maximum(y) - self.assertTrue(u < 20) - self.assertFalse(u < 3) - - def test_x_lt_x(self): - x = UOp.variable("i", 1, 10) - self.assertFalse(x < x) - - @unittest.expectedFailure - def test_x_lt_xp1(self): - x = UOp.variable("i", 1, 10) - self.assertTrue(x < (x+1)) - - def test_and_true(self): - with self.assertRaises(ValueError): - u = UOp.variable("b", False, True, dtypes.bool) & True - self.assertFalse(u) - - @unittest.expectedFailure - def test_var_cmp_range(self): - v = UOp.variable("i", 1, 10) - u = (v > 4) | (v < 6) - self.assertTrue(u) - - def test_var_cmp_assert(self): - with self.assertRaises(ValueError): - u = UOp.variable("i", 1, 10) < 5 - self.assertFalse(u) - - def test_plus_ordering_lt(self): - i = UOp.variable("i", 1, 10) - j = UOp.variable("j", 1, 10) - self.assertFalse((i+j) < (j+i)) - -if __name__ == '__main__': - unittest.main() \ No newline at end of file diff --git a/tinygrad/test/unit/test_uop_symbolic.py b/tinygrad/test/unit/test_uop_symbolic.py deleted file mode 100644 index 53b1d5f1..00000000 --- a/tinygrad/test/unit/test_uop_symbolic.py +++ /dev/null @@ -1,872 +0,0 @@ -#!/usr/bin/env python -import unittest, pickle, functools -import z3 - -from tinygrad.dtype import dtypes, ConstType -from tinygrad.codegen import full_rewrite -from tinygrad.codegen.devectorizer import sym -from tinygrad.helpers import Context -from tinygrad.uop.ops import UOp, Ops, graph_rewrite, sym_infer -from tinygrad import Variable -from tinygrad.uop.spec import z3_renderer - -def render(self) -> tuple[str, ConstType, ConstType]: - # NOTE: we need STORE so the ALU op has children - glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=0) - uops = full_rewrite(UOp(Ops.STORE, dtypes.void, (glbl.index(UOp.const(dtypes.int, 0)), self)).sink()) - rewritten_uop = [uop for uop in uops if uop.op is Ops.STORE][0].src[-1] - return rewritten_uop.render(simplify=False), rewritten_uop.vmin, rewritten_uop.vmax - -def uconst(val): return UOp.const(dtypes.int, val) -def usum(ops): return functools.reduce(lambda x,y: x+y, ops) -def uand(ops): return functools.reduce(lambda x,y: x*y, ops) - -# *** leave tests the same - -class TestSymbolicPickle(unittest.TestCase): - def _test_pickle_unpickle(self, x): self.assertEqual(x, pickle.loads(pickle.dumps(x))) - def test_pickle_variable(self): self._test_pickle_unpickle(Variable("a", 3, 8)) - def test_pickle_variable_times_2(self): self._test_pickle_unpickle(Variable("a", 3, 8)*2) - -class TestSymbolic(unittest.TestCase): - def helper_test_variable(self, v, n, m, s): - rendered, nmin, nmax = render(v) - if isinstance(s, tuple): self.assertIn(rendered, s) - else: self.assertEqual(rendered, s) - self.assertEqual(nmin, n) - self.assertEqual(nmax, m) - solver = z3.Solver() - z3_sink = graph_rewrite(v.sink(v.simplify()), z3_renderer, ctx=(solver, {})) - expr, epxr_simplified = z3_sink.src[0].arg, z3_sink.src[1].arg - self.assertEqual(solver.check(expr != epxr_simplified), z3.unsat, "simplified expression not equal to original") - - def test_cmp_simple(self): - self.helper_test_variable(Variable("a", 3, 8) < 4, 0, 1, "(a<4)") - self.helper_test_variable(Variable("a", 3, 8) >= 8, 0, 1, "((a<8)!=True)") - - def test_ge(self): - self.helper_test_variable(Variable("a", 3, 8) >= 77, 0, 0, "False") - self.helper_test_variable(Variable("a", 3, 8) >= 9, 0, 0, "False") - self.helper_test_variable(Variable("a", 3, 8) >= 8, 0, 1, "((a<8)!=True)") - self.helper_test_variable(Variable("a", 3, 8) >= 4, 0, 1, "((a<4)!=True)") - self.helper_test_variable(Variable("a", 3, 8) >= 3, 1, 1, "True") - self.helper_test_variable(Variable("a", 3, 8) >= 2, 1, 1, "True") - - def test_lt(self): - self.helper_test_variable(Variable("a", 3, 8) < 77, 1, 1, "True") - self.helper_test_variable(Variable("a", 3, 8) < 9, 1, 1, "True") - self.helper_test_variable(Variable("a", 3, 8) < 8, 0, 1, "(a<8)") - self.helper_test_variable(Variable("a", 3, 8) < 4, 0, 1, "(a<4)") - self.helper_test_variable(Variable("a", 3, 8) < 3, 0, 0, "False") - self.helper_test_variable(Variable("a", 3, 8) < 2, 0, 0, "False") - self.helper_test_variable(Variable("a", 3, 4) < Variable("b", 5, 6), 1, 1, "True") - self.helper_test_variable(Variable("a", 3, 5) < Variable("b", 5, 6), 0, 1, "(a= 12, 0, 1, "((a<3)!=True)") - self.helper_test_variable(Variable("a", 0, 5)*4 >= 13, 0, 1, "((a<4)!=True)") - - def test_div_div(self): - self.helper_test_variable((Variable("a", 0, 1800)//10)//9, 0, 20, "(a//90)") - - def test_div_const_div(self): - a = Variable("a", 0, 124) - self.helper_test_variable((a//2+1)//2, 0, 31, "((a+2)//4)") - self.helper_test_variable(((-a)//2-1)//2, -31, 0, "(((a+2)//4)*-1)") - self.helper_test_variable(((-a)//2+10)//2, -26, 5, "((((a//2)*-1)+10)//2)") - - def test_div_const_div_wrong_sign(self): - a = Variable("a", 0, 124) - self.helper_test_variable(((a-10)//2+10)//2, 2, 33, "((((a+-10)//2)+10)//2)") - - def test_distribute_mul(self): - self.helper_test_variable(usum([Variable("a", 0, 3), Variable("b", 0, 5)])*3, 0, 24, "((a*3)+(b*3))") - self.helper_test_variable((1+Variable("a", 0, 3))*(-2)+12, 4, 10, "((a*-2)+10)") - - def test_mod_mul_sum(self): - self.helper_test_variable(usum([Variable("b", 0, 2), Variable("a", 0, 5)*10])%9, 0, 7, ("(b+a)", "(a+b)")) - - def test_sum_0(self): - self.helper_test_variable(usum([Variable("a", 0, 7)]), 0, 7, "a") - - def test_mod_remove(self): - self.helper_test_variable(Variable("a", 0, 6)%100, 0, 6, "a") - - def test_big_mod(self): - self.helper_test_variable(Variable("a", -20, 20)%10, -9, 9, "(a%10)") - self.helper_test_variable(Variable("a", -20, 0)%10, -9, 0, "(((a*-1)%10)*-1)") - self.helper_test_variable(Variable("a", -20, 1)%10, -9, 9, "(a%10)") # TODO: tighter max - self.helper_test_variable(Variable("a", 0, 20)%10, 0, 9, "(a%10)") - self.helper_test_variable(Variable("a", -1, 20)%10, -9, 9, "(a%10)") # TODO: tighter min - - def test_ge_remove(self): - self.helper_test_variable(Variable("a", 0, 6) >= 25, 0, 0, "False") - - def test_lt_remove(self): - self.helper_test_variable(Variable("a", 0, 6) < -3, 0, 0, "False") - self.helper_test_variable(Variable("a", 0, 6) < 3, 0, 1, "(a<3)") - self.helper_test_variable(Variable("a", 0, 6) < 8, 1, 1, "True") - - def test_lt_sum_remove(self): - self.helper_test_variable(Variable("a", 0, 6) + 2 < 3, 0, 1, "(a<1)") - - def test_lt_simple_factor(self): - self.helper_test_variable((Variable("a", 0, 6)*6+Variable("b", 0, 6)*6) < 8, 0, 1, "(((a*3)+(b*3))<4)") - - def test_lt_sum_factor_rhs_partial(self): - self.helper_test_variable((Variable("a", 0, 6)*6 + Variable("b", 0, 6)*4 + Variable("c", 0, 6)*8) < 4, 0, 1, - ("((((a*3)+(b*2))+(c*4))<2)", "(((b*2)+((a*3)+(c*4)))<2)")) - - def test_lt_sum_factor_rhs_all(self): - self.helper_test_variable((Variable("a", 0, 6)*6 + Variable("b", 0, 6)*4 + Variable("c", 0, 6)*8) < 2, 0, 1, - ("((((a*3)+(b*2))+(c*4))<1)", "(((b*2)+((a*3)+(c*4)))<1)")) - - def test_and_fold(self): - self.helper_test_variable(uand([uconst(0), Variable("a", 0, 1)]), 0, 0, "0") - - def test_and_remove(self): - self.helper_test_variable(uand([uconst(1), Variable("a", 0, 1)]), 0, 1, "a") - - def test_mod_factor_negative(self): - self.helper_test_variable(usum([uconst(-29), Variable("a", 0, 10), Variable("b", 0, 10)*28]) % 28, -27, 27, "(((a+(b*28))+-29)%28)") - self.helper_test_variable(usum([uconst(-29), Variable("a", 0, 100), Variable("b", 0, 10)*28]) % 28, -27, 27, "(((a+(b*28))+-29)%28)") - - def test_sum_combine_num(self): - self.helper_test_variable(usum([uconst(29), Variable("a", 0, 10), uconst(-23)]), 6, 16, "(a+6)") - - def test_sum_num_hoisted_and_factors_cancel_out(self): - self.helper_test_variable(usum([Variable("a", 0, 1) * -4 + 1, Variable("a", 0, 1) * 4]), 1, 1, "1") - - @unittest.expectedFailure # only correct for floordiv, not truncdiv - def test_div_cancel(self): - self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40])//40, -1, 9, "(b+-1)") - - def test_div_cancel_correct(self): - with Context(CORRECT_DIVMOD_FOLDING=1): - self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40])//40, -1, 9, "(((a+(b*20))+-20)//20)") - - @unittest.expectedFailure # only correct for floordiv, not truncdiv - def test_mod_cancel(self): - self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40]) % 40, 0, 20, "(a*2)") - - def test_mod_cancel_correct(self): - with Context(CORRECT_DIVMOD_FOLDING=1): - self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40]) % 40, -38, 38, "((((a+(b*20))+-20)%20)*2)") - - def test_mul_div(self): - self.helper_test_variable((Variable("a", 0, 10)*4)//4, 0, 10, "a") - - def test_add_div(self): - # careful about the lower bounds and upper bounds - self.helper_test_variable((Variable("a", 0, 5)-2)//4, 0, 0, "0") - self.helper_test_variable((Variable("a", 0, 5)-1)//4, 0, 1, "((a+-1)//4)") - self.helper_test_variable((Variable("a", 0, 5))//4, 0, 1, "(a//4)") - self.helper_test_variable((Variable("a", 0, 5)+1)//4, 0, 1, "((a+1)//4)") - self.helper_test_variable((Variable("a", 0, 5)+2)//4, 0, 1, "((a+2)//4)") - self.helper_test_variable((Variable("a", 0, 5)+3)//4, 0, 2, "((a+3)//4)") - self.helper_test_variable((Variable("a", 0, 5)+4)//4, 1, 2, "((a//4)+1)") - self.helper_test_variable((Variable("a", 0, 5)+5)//4, 1, 2, "(((a+1)//4)+1)") - - def test_div_neg_rem(self): - self.helper_test_variable((-Variable("a", 0, 255)+256)//2, 0, 128, "((((a+1)//2)*-1)+128)") - - def test_mul_div_factor_mul(self): - self.helper_test_variable((Variable("a", 0, 10)*8)//4, 0, 20, "(a*2)") - - def test_mul_div_factor_mul_neg(self): - self.helper_test_variable((Variable("a", 0, 10)*-8+16)//4, -16, 4, "((a*-2)+4)") - - def test_mul_div_factor_div(self): - self.helper_test_variable((Variable("a", 0, 10)*4)//8, 0, 5, "(a//2)") - - def test_mul_div_factor_div_neg(self): - self.helper_test_variable((Variable("a", 0, 10)*-4+4)//8, -4, 0, "(((a*-1)+1)//2)") - - def test_mod_gcd_factor_neg(self): - self.helper_test_variable((Variable("a", 0, 10)*-4+4)%8, -4, 4, "((((a*-1)+1)%2)*4)") - - def test_mod_gcd_fold_neg(self): - self.helper_test_variable((Variable("a", 0, 10)*-8+20)%4, 0, 0, "0") - - def test_sum_div_partial_remove(self): - self.helper_test_variable(usum([Variable("idx0", 0, 127)*4, Variable("idx2", 0, 3)])//4, 0, 127, "idx0") - - def test_cdiv_const_evaluation(self): - self.helper_test_variable((Variable("a", 0, 2)-12)//8, -1, -1, "-1") - self.helper_test_variable((-Variable("a", 0, 2))//7, 0, 0, "0") - - def test_cmod_const_evaluation(self): - self.helper_test_variable((Variable("a", 1, 1)*-3)%8, -3, -3, "-3") - self.helper_test_variable((-Variable("a", 10, 10))%7, -3, -3, "-3") - - def test_div_numerator_negative(self): - self.helper_test_variable((Variable("idx", 0, 9)*-10)//11, -8, 0, "(((idx*10)//11)*-1)") - - def test_div_into_mod(self): - self.helper_test_variable((Variable("idx", 0, 16)*4)%8//4, 0, 1, "(idx%2)") - - def test_div_neg_cancel(self): - self.helper_test_variable((-Variable("idx", 0, 100)+199)//-4 + 50, 1, 26, "((idx//4)+1)") - self.helper_test_variable((-Variable("idx", 0, 100)+200)//-4 + 50, 0, 25, "((idx+3)//4)") - self.helper_test_variable((-Variable("idx", 0, 100)+201)//-4 + 50, 0, 25, "((idx+2)//4)") - - def test_sum_div_big_const(self): - gidx0 = Variable("gidx0", 0, 24) - self.helper_test_variable((gidx0+19)//20, 0, 2, "((gidx0+19)//20)") - self.helper_test_variable((gidx0+20)//20, 1, 2, "((gidx0//20)+1)") - self.helper_test_variable((gidx0+21)//20, 1, 2, "(((gidx0+1)//20)+1)") - - def test_sum_div_complex1(self): - gidx0 = Variable("gidx0", 0, 24) - gidx1 = Variable("gidx1", 0, 1) - gidx2 = Variable("gidx2", 0, 255) - lidx0 = Variable("lidx0", 0, 1) - lidx1 = Variable("lidx1", 0, 15) - lidx2 = Variable("lidx2", 0, 3) - alu0 = gidx2*640+gidx1*160+(gidx0//5)*2+lidx0*320+lidx1*10 - self.helper_test_variable((alu0+lidx2*2+1)//20, 0, 8192, - ("((((((gidx0//5)+lidx2)//5)+lidx1)//2)+(((gidx2*32)+(gidx1*8))+(lidx0*16)))", - "(((lidx1+((lidx2+(gidx0//5))//5))//2)+((gidx2*32)+((gidx1*8)+(lidx0*16))))", - "((((gidx1*8)+(gidx2*32))+(lidx0*16))+((lidx1+((lidx2+(gidx0//5))//5))//2))")) - - def test_sum_div_complex2(self): - gidx0 = Variable("gidx0", 0, 7) - lidx2 = Variable("lidx2", 0, 1) - lidx3 = Variable("lidx3", 0, 1) - self.helper_test_variable((gidx0*4+lidx2*2+1)//10, 0, 3, ("(((gidx0*2)+lidx2)//5)", "((lidx2+(gidx0*2))//5)")) - self.helper_test_variable((gidx0*4+lidx2*2+lidx3)//10, 0, 3, ("(((gidx0*2)+lidx2)//5)", "((lidx2+(gidx0*2))//5)")) - self.helper_test_variable((gidx0*2+lidx2)//10, 0, 1, "(gidx0//5)") - - def test_sum_div_complex3(self): - gidx0 = Variable("gidx0", 0, 7) - lidx2 = Variable("lidx2", 0, 12) - lidx3 = Variable("lidx3", 0, 1) - self.helper_test_variable((gidx0*4+lidx2*2+lidx3)//12, 0, 4, ("(((lidx2//2)+gidx0)//3)", "((gidx0+(lidx2//2))//3)")) - self.helper_test_variable((lidx2*2+gidx0*4+lidx3)//12, 0, 4, ("(((lidx2//2)+gidx0)//3)", "((gidx0+(lidx2//2))//3)")) - - def test_sum_mul_distribute(self): - gidx0 = Variable("gidx0", 0, 7) - lidx2 = Variable("lidx2", 0, 12) - lidx3 = Variable("lidx3", 0, 1) - self.helper_test_variable((gidx0+lidx2+lidx3)*4, 0, 80, - ("(((gidx0*4)+(lidx2*4))+(lidx3*4))","((lidx3*4)+((gidx0*4)+(lidx2*4)))")) - - @unittest.expectedFailure - def test_variable_divmod(self): - start_pos = Variable("start_pos", 0, 127) - v = start_pos + 1 - idx0 = Variable("idx0", 0, 2) - idx1 = Variable("idx1", 0, start_pos) - self.helper_test_variable((idx0*v+idx1)//v, 0, 2, "(idx0)") - self.helper_test_variable((idx0*v+idx1)%v, 0, start_pos, "idx1") - - def test_divmod_variable_denom_fold_to_const(self): - x = Variable("x", 20, 23) - y = Variable("y", 8, 10) - self.helper_test_variable(x//y, 2, 2, "2") - self.helper_test_variable(x%y, 0, 7, "(x+(y*-2))") - # ensure all 4 corners are checked - x = Variable("x", -10, 10) - y = Variable("y", -8, 9) - self.helper_test_variable(x//y, -2147483648, 2147483647, "(x//y)") - self.helper_test_variable(x%y, -2147483648, 2147483647, "(x%y)") - - def test_div_neg_all_range(self): - gidx = Variable("gidx", 0, 124) - lidx = Variable("lidx", 0, 7) - self.helper_test_variable((-gidx*8-lidx+999)//-4 + 250, 1, 250, "(((gidx*2)+(lidx//4))+1)") - self.helper_test_variable((-gidx*8-lidx+1000)//-4 + 250, 0, 250, "((gidx*2)+((lidx+3)//4))") - self.helper_test_variable((-gidx*8-lidx+1001)//-4 + 250, 0, 250, "((gidx*2)+((lidx+2)//4))") - self.helper_test_variable((-gidx*8-lidx+1002)//-4 + 250, 0, 250, "((gidx*2)+((lidx+1)//4))") - - def test_div_neg_then_neg(self): - # taken from arange opts - lidx0 = Variable("lidx0", 0, 7) - lidx1 = Variable("lidx1", 0, 7) - alu2 = -lidx0-lidx1 - self.helper_test_variable((((alu2+14)//(-32))+4), 4, 4, "4") - self.helper_test_variable(-(((alu2+14)//(-32))+4), -4, -4, "-4") - self.helper_test_variable((((alu2+134)//(-32))+4), 0, 1, "(((lidx0+lidx1)+25)//32)") - self.helper_test_variable((((alu2+142)//(-32))+4), 0, 0, "0") - self.helper_test_variable((((alu2+150)//(-32))+4), 0, 0, "0") - self.helper_test_variable((((alu2+158)//(-32))+4), 0, 0, "0") - - def test_div_mod_recombine(self): - gidx = Variable("gidx", 0, 124) - self.helper_test_variable(gidx%4+(gidx//4)*4, 0, 124, "gidx") - self.helper_test_variable((gidx//4)*4+gidx%4, 0, 124, "gidx") - - def test_div_mod_recombine_folded_mod(self): - a = Variable("a", 0, 2) - b = Variable("b", 0, 100) - self.helper_test_variable((31 * a + 1) % 30 + ((31 * a + 1) // 30) * 30, 1, 63, "((a*31)+1)") - with self.assertRaises(AssertionError): - self.helper_test_variable((31 * b + 1) % 18 + ((31 * b + 1) // 18) * 18, 1, 3101, "((b*31)+1)") - - def test_div_mod_recombine_with_gcd(self): - b = Variable("b", 0, 100) - exp = (16 * b + 2) % 18 + ((16 * b + 2) // 18) * 18 - self.helper_test_variable(exp, 2, 1602, "((b*16)+2)") - with self.assertRaises(AssertionError): - self.helper_test_variable((30 * b + 1) % 18 + ((30 * b + 1) // 18) * 18, 1, 3001, "((b*30)+1)") - - def test_arange_unrolled4(self): - gidx = Variable("gidx", 0, 2559) - unrolled_div = (gidx+2561)//4+(gidx+2562)//4+(gidx+2560)//4+(gidx+2559)//4 - self.helper_test_variable(unrolled_div, 2559, 5118, "(gidx+2559)") - - def test_arange_unrolled4_mul(self): - gidx = Variable("gidx", 0, 2559) - unrolled_div = 2*((gidx+2561)//4)+2*((gidx+2562)//4)+2*((gidx+2560)//4)+2*((gidx+2559)//4) - self.helper_test_variable(unrolled_div, 5118, 10236, "((gidx*2)+5118)") - - def test_arange_unrolled4_small(self): - gidx = Variable("gidx", 0, 3) - unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 - self.helper_test_variable(unrolled_div, 0, 3, "gidx") - - gidx = Variable("gidx", 0, 2) - unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 - self.helper_test_variable(unrolled_div, 0, 2, "gidx") - - gidx = Variable("gidx", 0, 1) - unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 - self.helper_test_variable(unrolled_div, 0, 1, "gidx") - - def test_arange_unrolled2(self): - gidx = Variable("gidx", 0, 2559) - unrolled_div = (gidx+2559)//2+(gidx+2560)//2+3 - self.helper_test_variable(unrolled_div, 2562, 5121, "(gidx+2562)") - - def test_arange_unrolled2_neg(self): - ridx = Variable("ridx", 0, 255) - unrolled_div = -((255-ridx)//2) - ((256-ridx)//2) - self.helper_test_variable(unrolled_div, -255, 0, "(ridx+-255)") - - def test_gated_load(self): - idx = Variable("idx", 0, 24) - self.helper_test_variable(idx//4, 0, 6, "(idx//4)") - # TODO: simplify the true branch - self.helper_test_variable((idx<4).where(idx//4, idx.const_like(-1)), -1, 6, "((idx//4) if (idx<4) else -1)") - - def test_idiv_lt(self): - idx = Variable("idx", 0, 24) - self.helper_test_variable((idx//4<3), 0, 1, "(idx<12)") - self.helper_test_variable(((idx-20)//4<-3), 0, 1, "(idx<5)") - self.helper_test_variable(((idx-10)//4<0), 0, 1, "(idx<7)") - self.helper_test_variable((idx//-4<-3), 0, 1, "(((idx//4)*-1)<-3)") - - def test_simplex_lt(self): - a = Variable("a", 0, 3) - b = Variable("b", 0, 3) - c = Variable("c", 0, 3) - d = Variable("d", -3, 3) - self.helper_test_variable((a<1).ne(True), 0, 1, "((a<1)!=True)") - self.helper_test_variable((a+b<1).ne(True), 0, 1, "(((a+b)<1)!=True)") - self.helper_test_variable((a*3+b*4<1).ne(True), 0, 1, "(((a+b)<1)!=True)") - self.helper_test_variable((a*(-3)+b*4<1).ne(True), 0, 1, "((((a*-3)+(b*4))<1)!=True)") # negative coeff, should not be simplified - self.helper_test_variable((a*3+d*4<1).ne(True), 0, 1, "((((a*3)+(d*4))<1)!=True)") # var can be negative, should not be simplified - self.helper_test_variable((a+b+c*2<1).ne(True), 0, 1, ("((((a+b)+c)<1)!=True)", "(((c+(a+b))<1)!=True)", '(((b+(a+c))<1)!=True)')) - self.helper_test_variable((a+b*2+c*4<1).ne(True), 0, 1, ("((((a+b)+c)<1)!=True)", "(((c+(a+b))<1)!=True)", '(((b+(a+c))<1)!=True)')) - - def test_where_removal(self): - cond = Variable("a", 0, 3) < 2 - u1, u0 = cond.ufix(1), cond.ufix(0) - self.helper_test_variable(cond, 0, 1, "(a<2)") - self.helper_test_variable(cond.where(u1, u0), 0, 1, "(a<2)") - self.helper_test_variable(cond.where(u1, u0).where(u1, u0), 0, 1, "(a<2)") - - def test_where_combine(self): - cond = Variable("x", 0, 3) < 2 - a = Variable("a", 0, 3) - b = Variable("b", 0, 3) - aa = cond.where(a, a.ufix(0)) - bb = cond.where(b, b.ufix(1)) - self.helper_test_variable(aa, 0, 3, "(a if (x<2) else 0)") - self.helper_test_variable(bb, 0, 3, "(b if (x<2) else 1)") - self.helper_test_variable(aa+bb, 0, 6, "((a+b) if (x<2) else 1)") - self.helper_test_variable(aa.maximum(bb), 0, 3, "(max(a, b) if (x<2) else 1)") - - # not combining because it increased total ALU - c = Variable("c", 0, 3) - cc = cond.where(c, c+1) - self.helper_test_variable(bb+cc, 0, 7, "((b if (x<2) else 1)+(c if (x<2) else (c+1)))") - - # not combining # TODO: can combine if it can further simplify? - ab = cond.where(a, b) - ba = cond.where(b, a) - self.helper_test_variable(ab+ba, 0, 6, "((a if (x<2) else b)+(b if (x<2) else a))") - - # not combining # TODO: can combine if one is identity element const - self.helper_test_variable(aa+ab, 0, 6, "((a if (x<2) else b)+(a if (x<2) else 0))") - - def test_negation_in_where(self): - cond = Variable("x", 0, 3) < 2 - a = Variable("a", 0, 3) - b = Variable("b", 0, 3) - w = cond.logical_not().where(a, b) - self.helper_test_variable(w, 0, 3, "(b if (x<2) else a)") - - def test_neg_in_comp(self): - a = Variable("a", 0, 3) - b = Variable("b", 0, 3) - self.helper_test_variable(-a<-b, False, True, "(b 2 - a = Variable("a", 0, 3) - b = Variable("b", 0, 3) - expr = cond1.where(cond2.where(a, b), b) - self.helper_test_variable(expr, 0, 3, "(a if ((s<6)&(2 (a if (s<5) else b) - self.helper_test_variable(expr, 0, 3, "(a if (s<5) else b)") - - def test_symbolic_div(self): - # from symbolic arange - a = Variable("a", 1, 10) - denominator = ((a*-2)+1) - numerator = (((((a*2)+-1)*2)+1)*a) - self.helper_test_variable(denominator, -19, -1, "((a*-2)+1)") - self.helper_test_variable(numerator, 3, 390, "(a*((a*4)+-1))") - self.helper_test_variable((numerator//denominator)<=0, 1, 1, "True") - -class TestSymbolicNumeric(unittest.TestCase): - def helper_test_numeric(self, f): - MIN, MAX = 0, 10 - # one number - for i in range(MIN, MAX): - v = graph_rewrite(f(uconst(i)), sym) - self.assertEqual(v.vmin, v.vmax) - self.assertEqual(v.vmin, f(i)) - for kmin in range(MIN, MAX): - for kmax in range(MIN, MAX): - if kmin > kmax: continue - v = f(Variable("tmp", kmin, kmax)) - values = [f(rv) for rv in range(kmin, kmax+1)] - # the min and max may not be exact - self.assertLessEqual(v.vmin, min(values)) - self.assertGreaterEqual(v.vmax, max(values)) - - def test_mod_4(self): self.helper_test_numeric(lambda x: (x%4)) - def test_div_4(self): self.helper_test_numeric(lambda x: (x//4)) - def test_plus_1_div_2(self): self.helper_test_numeric(lambda x: (x+1)//2) - def test_plus_1_mod_2(self): self.helper_test_numeric(lambda x: (x+1)%2) - def test_times_2(self): self.helper_test_numeric(lambda x: x*2) - def test_times_2_plus_3(self): self.helper_test_numeric(lambda x: x*2 + 3) - def test_times_2_plus_3_mod_4(self): self.helper_test_numeric(lambda x: (x*2 + 3)%4) - def test_times_2_plus_3_div_4(self): self.helper_test_numeric(lambda x: (x*2 + 3)//4) - def test_times_2_plus_3_div_4_mod_4(self): self.helper_test_numeric(lambda x: ((x*2 + 3)//4)%4) - -class TestSymbolicVars(unittest.TestCase): - def test_simple(self): - z = uconst(0) - a = Variable("a", 0, 10) - b = Variable("b", 0, 10) - c = Variable("c", 0, 10) - assert z.vars() == z.vars() == set() - print(a.vars()) - assert a.vars() == a.vars() == {a} - m = a * 3 - assert m.vars() == {a} - s = usum([a, b, c]) - assert s.vars() == {a, b, c} - - def test_compound(self): - a = Variable("a", 0, 10) - b = Variable("b", 0, 10) - c = Variable("c", 0, 10) - assert (a + b * c).vars() == {a, b, c} - assert (a % 3 + b // 5).vars() == {a, b} - # TODO: fix me - with self.assertRaises(AssertionError): - assert (a + b + c - a).vars() == {b, c} - - def test_dedup(self): - a = Variable("a", 0, 10) - assert (a * a).vars() == {a} - assert (a//4 + a//6).vars() == {a} - -class TestSymInfer(unittest.TestCase): - def test_sym_infer(self): - a = Variable("a", 0, 10) - b = Variable("b", 0, 10) - c = Variable("c", 0, 10) - var_vals = {a: 2, b: 3, c: 4} - assert sym_infer(5, var_vals) == 5 - assert sym_infer(4.2, var_vals) == 4.2 - assert sym_infer(a, var_vals) == 2 - assert sym_infer(b, var_vals) == 3 - assert sym_infer(a+b, var_vals) == 5 - assert sym_infer(a-b, var_vals) == -1 - assert sym_infer(a+b+c, var_vals) == 9 - assert sym_infer(a*b, var_vals) == 6 - assert sym_infer(a*b+c, var_vals) == 10 - def test_sym_infer_cdiv_cmod(self): - a = Variable("a", -1000, 1) - b = Variable("b", -1000, 1) - var_vals = {a: 1, b: -1000} - assert sym_infer(a%b, var_vals) == 1 - assert sym_infer(a//b, var_vals) == 0 - -""" -@unittest.skip("not supported on uops yet") -class TestSymbolicSymbolicOps(unittest.TestCase): - def test_node_divmod_node(self): - i = Variable("i", 1, 10) - idx0 = Variable("idx0", 0, i*3-1) - assert uconst(0) // (Variable("i", 1, 10)*128) == 0 - assert uconst(0) % (Variable("i", 1, 10)*128) == 0 - assert uconst(127) // (Variable("i", 1, 10)*128) == 0 - assert uconst(127) % (Variable("i", 1, 10)*128) == 127 - assert 127 // (Variable("i", 1, 10)*128) == 0 - assert 127 % (Variable("i", 1, 10)*128) == 127 - assert uconst(128) // (Variable("i", 1, 10)*128 + 128) == 0 - assert uconst(128) % (Variable("i", 1, 10)*128 + 128) == 128 - assert 128 // (Variable("i", 1, 10)*128 + 128) == 0 - assert 128 % (Variable("i", 1, 10)*128 + 128) == 128 - assert 0 // (Variable("i", 1, 10)*128) == 0 - assert 0 % (Variable("i", 1, 10)*128) == 0 - assert idx0 // (i*3) == 0 - assert idx0 % (i*3) == idx0 - assert i // i == 1 - assert i % i == 0 - assert 128 // uconst(4) == 32 - assert 128 % uconst(4) == 0 - assert uconst(128) // uconst(4) == 32 - assert uconst(128) % uconst(4) == 0 - - def test_mulnode_divmod_node(self): - i = Variable("i", 1, 10) - idx0 = Variable("idx0", 0, 31) - # assert (idx0*(i*4+4)) // (i+1) == (idx0*4) - # assert (idx0*(i*4+4)) % (i+1) == 0 - assert (idx0*i) % i == 0 - - def test_sumnode_divmod_sumnode(self): - i = Variable("i", 1, 10) - # idx0 = Variable("idx0", 0, 7) - # idx1 = Variable("idx1", 0, 3) - # idx2 = Variable("idx2", 0, i) - # assert (idx0*(i*4+4)+idx1*(i+1)+idx2) // (i+1) == idx0*4+idx1 - # assert (idx0*(i*4+4)+idx1*(i+1)+idx2) % (i+1) == idx2 - assert (i+1) // (i*128+128) == 0 - assert (i+1) % (i*128+128) == (i+1) - # assert (i+1+idx2) // (i+1) == 1 - # assert (i+1+idx2) % (i+1) == idx2 - # assert (idx0*(i*4+4)+i+1+idx2) // (i+1) == idx0*4+1 - # assert (idx0*(i*4+4)+i+1+idx2) % (i+1) == idx2 - # assert (i*128+128)*2 // (i*128+128) == 2 - # assert (i*128+128)*2 % (i*128+128) == 0 - - def test_sumnode_div_uconst_no_factoring(self): - gid = Variable("gid", 0, 1023) - lid = Variable("lid", 0, 3) - expr_before_div = uconst(-1019)-4*lid-gid - unfactored_expr = Node.__floordiv__(expr_before_div, uconst(-16), False) - factored_expr = Node.__floordiv__(expr_before_div, uconst(-16), True) - self.assertEqual(unfactored_expr.render(), "(((lid*4)+1019+gid)//16)") - self.assertEqual(factored_expr.render(), "(((((3+gid)//4)+2+lid)//4)+63)") - - def test_mod_node_max(self): - i = Variable("i", 1, 128) - gidx0 = Variable("gidx0", 0, i) - mod = gidx0 % 8 - assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 8 - mod = gidx0 % 2 - assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 2 - - gidx0 = Variable("gidx0", 0, i*8+7) - mod = gidx0 % 8 - assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 8 - mod = gidx0 % 2 - assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 2 - - def test_nested_variable_mod(self): - i = Variable("i", 1, 5) - idx0 = Variable("idx0", 0, i) - with self.assertRaises(AssertionError): - assert idx0 % 2 == idx0 - - def test_num_node_mul_node(self): - a = Variable("a", 1, 5) - b = uconst(2) * a - assert b == a * 2 - assert isinstance(b, MulNode) - b = uconst(1) * a - assert b == a - assert isinstance(b, Variable) - b = uconst(0) * a - assert b == 0 - assert isinstance(b, uconst) - - def test_substitute(self): - a = Variable("idx0", 1, 3) - b = a + 1 - c = b.substitute({a: uconst(1)}) - assert c == uconst(2) -""" - -class TestSymbolicRealWorld(unittest.TestCase): - def test_resnet_half(self): - gidx0 = Variable("gidx0", 0, 3) - gidx1 = Variable("gidx1", 0, 127) - gidx2 = Variable("gidx2", 0, 7) - lidx3 = Variable("lidx3", 0, 7) - lidx4 = Variable("lidx4", 0, 1) - lidx5 = Variable("lidx5", 0, 15) - - idx:UOp = ((((1+lidx5)%16)*49)+(((262145+lidx5)//16)*802816)+(gidx0*3211264)+(gidx1*784)+(gidx2*8)+(lidx4*100352)+-13151129600+lidx3) - idx = graph_rewrite(idx, sym) - #print(idx.render()) - # NOTE: this used to have 13,151,129,600 in the output which is out of int32 range. - self.assertIn(idx.render(), - ("((((((((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49))+(gidx0*3211264))+(gidx1*784))+(gidx2*8))+(lidx4*100352))+lidx3)+2207744)", - '((lidx3+((((((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49))+(gidx0*3211264))+(gidx1*784))+(gidx2*8))+(lidx4*100352)))+2207744)', - '((lidx3+((lidx4*100352)+((gidx2*8)+((gidx1*784)+((gidx0*3211264)+((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49)))))))+2207744)', - )) - -class TestBounds(unittest.TestCase): - def test_unrolled_arange(self): - # #include - # using namespace metal; - # kernel void r_2560_640_4(device int* data0, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { - # int gidx0 = gid.x; /* 2560 */ - # int alu0 = (gidx0*(-1)); - # int alu1 = max((int)((-640)),((((alu0+2559)/(-4))*(-1))+(-640))); - # int alu2 = max((int)((-640)),((((alu0+2560)/(-4))*(-1))+(-640))); - # int alu3 = max((int)((-640)),((((alu0+2561)/(-4))*(-1))+(-640))); - # int alu4 = max((int)((-640)),((((alu0+2562)/(-4))*(-1))+(-640))); - # *(data0+gidx0) = ((alu1*(-1))+(alu2*(-1))+(alu4*(-1))+(alu3*(-1))+(-1)); - # } - gidx0 = Variable("gidx0", 0, 2559) - assert gidx0.vmin == 0 and gidx0.vmax == 2559 - alu0 = gidx0 * -1 - assert alu0.vmin == -2559 and alu0.vmax == 0 - assert (alu0+2559).vmin == 0 and (alu0+2559).vmax == 2559 - assert ((alu0+2559)//-4).vmin == -639 and ((alu0+2559)//-4).vmax == 0 - assert (((alu0+2559)//-4)*(-1)).vmin == 0 and (((alu0+2559)//-4)*(-1)).vmax == 639 - -class TestFuzzFailure(unittest.TestCase): - def test_fuzz_failure1(self): - v1=Variable('v1', 0, 8) - v2=Variable('v2', 0, 2) - v3=Variable('v3', 0, 1) - expr = (((((((((((((((((((((((0//4)%2)//8)+-2)+-4)+-3)+v1)+-4)+v2)+-2)+v3)+v2)//3)%7)*1)//2)+v2)*-1)+2)+1)+0)+-3)+v3) - v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(0), v3.const_like(0) - num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() - assert num==rn, f"{num} != {rn}" - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_uop_vmin_vmax.py b/tinygrad/test/unit/test_uop_vmin_vmax.py deleted file mode 100644 index cc1ca49d..00000000 --- a/tinygrad/test/unit/test_uop_vmin_vmax.py +++ /dev/null @@ -1,322 +0,0 @@ -import unittest, math -from tinygrad.uop.ops import UOp, Ops -from tinygrad.dtype import dtypes - -class TestVminVmaxProperties(unittest.TestCase): - def test_vmin_vmax_constant(self): - # vmin and vmax for a constant - uop = UOp.const(dtypes.int32, 42) - self.assertEqual(uop.vmin, 42) - self.assertEqual(uop.vmax, 42) - - def test_vmin_vmax_cmpne(self): - uop = UOp.const(dtypes.int32, 42) - def test_bool(u, x): - self.assertEqual(u.vmin, x) - self.assertEqual(u.vmax, x) - test_bool(uop != 42, False) - test_bool(uop != 43, True) - test_bool(uop != 41, True) - - def test_vmin_vmax_addition_with_variable(self): - # vmin and vmax for addition with a variable - x = UOp.variable('x', 10, 20) - uop = x + 5 - self.assertEqual(uop.vmin, 15) - self.assertEqual(uop.vmax, 25) - - def test_vmin_vmax_subtraction_with_variable(self): - x = UOp.variable('x', 10, 20) - uop = x - 5 - self.assertEqual(uop.vmin, 5) - self.assertEqual(uop.vmax, 15) - uop = 5 - x - self.assertEqual(uop.vmin, -15) - self.assertEqual(uop.vmax, -5) - - def test_vmin_vmax_and_with_variable(self): - x = UOp.variable('x', 10, 20) - uop = x & 5 - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 5) - - # this can be improved - uop = x & 15 - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 15) - - # this can be improved - uop = x & 32 - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 20) - - def test_vmin_vmax_multiplication_with_variable(self): - # vmin and vmax for multiplication with a variable - x = UOp.variable('x', -3, 4) - uop = x * 2 - self.assertEqual(uop.vmin, -6) - self.assertEqual(uop.vmax, 8) - - def test_vmin_vmax_variable_inside_special(self): - uop = UOp(Ops.SPECIAL, dtypes.int, arg=('gidx0', UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10)))) - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 10) - - def test_vmin_vmax_multiplication_0_inf(self): - # vmin and vmax for multiplication with a variable - x = UOp.const(dtypes.float, 0.0) - y = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0), UOp.const(dtypes.int, 0), dtype=dtypes.float) - uop = x * y - # TODO: these should be 0, but definitely should not be nan - self.assertEqual(uop.vmin, -math.inf) - self.assertEqual(uop.vmax, math.inf) - - def test_vmin_vmax_with_negative_multiplication(self): - # vmin and vmax when multiplying by a negative number - x = UOp.variable('x', 2, 5) - uop = x * -3 - self.assertEqual(uop.vmin, -15) - self.assertEqual(uop.vmax, -6) - - def test_vmin_vmax_with_negative_multiplication2(self): - # vmin and vmax when multiplying by a negative number - x = UOp.variable('x', -2, 5) - uop = x * -3 - self.assertEqual(uop.vmin, -15) - self.assertEqual(uop.vmax, 6) - - def test_vmin_vmax_nested_min_max(self): - # vmin and vmax with nested min/max operations - x = UOp.variable('x', 0, 10) - uop = x.maximum(5).minimum(8) - self.assertEqual(uop.vmin, 5) - self.assertEqual(uop.vmax, 8) - - def test_vmin_vmax_where(self): - x = UOp.variable('x', 0, 10) - y = UOp.variable('y', 1, 11) - z = UOp.variable('z', 2, 12) - uop = (x<5).where(y, z) - self.assertEqual(uop.vmin, 1) - self.assertEqual(uop.vmax, 12) - - def test_vmin_vmax_shl(self): - x = UOp.variable('x', 0, 10) << 5 - self.assertEqual(x.vmin, 0) - self.assertEqual(x.vmax, 10 << 5) - - def test_vmin_vmax_shr(self): - x = UOp.variable('x', 0, 10) >> 2 - self.assertEqual(x.vmin, 0) - self.assertEqual(x.vmax, 10 >> 2) - -class TestVminVmaxDivMod(unittest.TestCase): - def test_vmin_vmax_division_positive(self): - # vmin and vmax for division of a variable by a positive constant - x = UOp.variable('x', 10, 20) - uop = x // 2 - self.assertEqual(uop.vmin, 5) - self.assertEqual(uop.vmax, 10) - - def test_vmin_vmax_division_negative(self): - # vmin and vmax for division of a variable by a negative constant - # always positive - x = UOp.variable('x', 10, 20) - uop = x // -2 - self.assertEqual(uop.vmin, -10) - self.assertEqual(uop.vmax, -5) - uop = x // -3 - self.assertEqual(uop.vmin, -6) - self.assertEqual(uop.vmax, -3) - - # always negative - x = UOp.variable('x', -20, -10) - uop = x // -2 - self.assertEqual(uop.vmin, 5) - self.assertEqual(uop.vmax, 10) - uop = x // -3 - self.assertEqual(uop.vmin, 3) - self.assertEqual(uop.vmax, 6) - - # cross 0 - x = UOp.variable('x', -10, 10) - uop = x // -2 - self.assertEqual(uop.vmin, -5) - self.assertEqual(uop.vmax, 5) - uop = x // -3 - self.assertEqual(uop.vmin, -3) - self.assertEqual(uop.vmax, 3) - - def test_vmin_vmax_div_symbolic(self): - x = UOp.variable('x', 1, 10) - y = UOp.variable('y', 3, 5) - self.assertEqual((x//y).vmin, 0) - self.assertEqual((x//y).vmax, 3) - self.assertEqual(((-x)//y).vmin, -3) - self.assertEqual(((-x)//y).vmax, 0) - self.assertEqual((x//(-y)).vmin, -3) - self.assertEqual((x//(-y)).vmax, 0) - self.assertEqual(((-x)//(-y)).vmin, 0) - self.assertEqual(((-x)//(-y)).vmax, 3) - - self.assertEqual((100//y).vmin, 20) - self.assertEqual((100//y).vmax, 33) - self.assertEqual(((-100)//y).vmin, -33) - self.assertEqual(((-100)//y).vmax, -20) - self.assertEqual((100//(-y)).vmin, -33) - self.assertEqual((100//(-y)).vmax, -20) - self.assertEqual(((-100)//(-y)).vmin, 20) - self.assertEqual(((-100)//(-y)).vmax, 33) - - def test_vmin_vmax_mod_positive(self): - # vmin and vmax for modulo of a variable by a positive constant - positive = UOp.variable('positive', 10, 20) - uop = positive % 3 - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 2) - - negative = UOp.variable('negative', -20, -10) - uop = negative % 3 - self.assertEqual(uop.vmin, -2) - self.assertEqual(uop.vmax, 0) - - mixed = UOp.variable('mixed', -20, 20) - uop = mixed % 3 - self.assertEqual(uop.vmin, -2) - self.assertEqual(uop.vmax, 2) - - def test_vmin_vmax_mod_negative(self): - # vmin and vmax for modulo of a variable by a negative constant - positive = UOp.variable('positive', 10, 20) - uop = positive % -3 - self.assertEqual(uop.vmin, 0) - self.assertEqual(uop.vmax, 2) - - negative = UOp.variable('negative', -20, -10) - uop = negative % -3 - self.assertEqual(uop.vmin, -2) - self.assertEqual(uop.vmax, 0) - - mixed = UOp.variable('mixed', -20, 20) - uop = mixed % -3 - self.assertEqual(uop.vmin, -2) - self.assertEqual(uop.vmax, 2) - -class TestVminVmaxVConst(unittest.TestCase): - def test_vmin_vmax_vconst_single_element(self): - # vmin and vmax for a single-element vector constant - uop = UOp.const(dtypes.int32.vec(1), (42,)) - self.assertEqual(uop.vmin, 42) - self.assertEqual(uop.vmax, 42) - - def test_vmin_vmax_vconst_multiple_elements(self): - # vmin and vmax for a multi-element vector constant - uop = UOp.const(dtypes.int32.vec(4), (10, 20, -5, 7)) - self.assertEqual(uop.vmin, -5) - self.assertEqual(uop.vmax, 20) - - def test_vmin_vmax_vconst_all_equal(self): - # vmin and vmax for a vector where all elements are equal - uop = UOp.const(dtypes.int32.vec(3), (7, 7, 7)) - self.assertEqual(uop.vmin, 7) - self.assertEqual(uop.vmax, 7) - - def test_vmin_vmax_vconst_with_negative_values(self): - # vmin and vmax for a vector constant containing negative values - uop = UOp.const(dtypes.int32.vec(4), (-10, -20, -5, -15)) - self.assertEqual(uop.vmin, -20) - self.assertEqual(uop.vmax, -5) - - def test_vmin_vmax_vconst_with_floats(self): - # vmin and vmax for a vector constant of float values - uop = UOp.const(dtypes.float32.vec(3), (1.5, -3.2, 0.0)) - self.assertEqual(uop.vmin, -3.2) - self.assertEqual(uop.vmax, 1.5) - - def test_vmin_vmax_vconst_with_bools(self): - # vmin and vmax for a vector constant of bool values - uop = UOp.const(dtypes.bool.vec(3), (True, False, False)) - self.assertIs(uop.vmin, False) - self.assertIs(uop.vmax, True) - -class TestConstFactor(unittest.TestCase): - def test_const_factor_constant(self): - # const_factor for a constant - uop = UOp.const(dtypes.int32, 42) - self.assertEqual(uop.const_factor(), 42) - - def test_const_factor_addition(self): - # const_factor for an addition of constants - uop = UOp.const(dtypes.int32, 30) + UOp.const(dtypes.int32, 12) - self.assertEqual(uop.const_factor(), 6) # GCD(30, 12) = 6 - - def test_const_factor_multiplication(self): - # const_factor for a multiplication of constants - uop = UOp.const(dtypes.int32, 5) * UOp.const(dtypes.int32, 7) - self.assertEqual(uop.const_factor(), 5) # For multiplication, it's one of the factors - - def test_const_factor_with_variable(self): - # const_factor for an expression involving a variable - x = UOp.variable('x', 10, 20) - uop = x * 3 - self.assertEqual(uop.const_factor(), 3) - - def test_const_factor_division(self): - # const_factor for an expression with division - x = UOp.variable('x', 10, 20) - uop = x // 4 - self.assertEqual(uop.const_factor(), 1) # Division reduces the const_factor to 1 - - def test_const_factor_multiplication_of_var_and_const(self): - # const_factor for multiplication of a variable and a constant - x = UOp.variable('x', 6, 18) - uop = x * 4 - self.assertEqual(uop.const_factor(), 4) # Constant factor 4 - - @unittest.skip("broken") - def test_const_factor_multiplication_of_consts_and_vars(self): - # Multiplying constants and variables - x = UOp.variable('x', 10, 20) - uop = (x * 3) * 5 - self.assertEqual(uop.const_factor(), 15) # Constant multipliers are combined (3 * 5 = 15) - -class TestDivides(unittest.TestCase): - def test_divides_constant_exact(self): - # Divides a constant by an exact divisor - uop = UOp.const(dtypes.int32, 42) - result = uop.divides(7) - self.assertIsNotNone(result) - self.assertEqual(result.const_factor(), 6) # 42 / 7 = 6 - - def test_divides_constant_inexact(self): - # Try to divide a constant by a non-exact divisor - uop = UOp.const(dtypes.int32, 42) - result = uop.divides(5) - self.assertIsNone(result) # 42 is not divisible by 5 - - @unittest.skip("broken") - def test_divides_variable_and_constant(self): - # Multiplying a variable by a constant, then dividing by the same constant - x = UOp.variable('x', 10, 20) - uop = x * 6 - result = uop.divides(6) - self.assertIsNotNone(result) - self.assertEqual(result, x) # (x * 6) / 6 = x - - def test_divides_complex_expression(self): - # Dividing a more complex expression - x = UOp.variable('x', 10, 20) - uop = (x * 6) + 18 - result = uop.divides(6) - self.assertIsNotNone(result) - self.assertEqual(result.const_factor(), 1) # (x + 3), const_factor is 1 - - def test_divides_with_inexact_factors(self): - # Multiplying by a constant but dividing by a non-exact divisor - x = UOp.variable('x', 15, 45) - uop = x * 4 - result = uop.divides(3) - self.assertIsNone(result) # Cannot divide by 3, since 4 is not divisible by 3 - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_upat_compile.py b/tinygrad/test/unit/test_upat_compile.py deleted file mode 100644 index 1f68a883..00000000 --- a/tinygrad/test/unit/test_upat_compile.py +++ /dev/null @@ -1,53 +0,0 @@ -import unittest -from tinygrad.helpers import DEBUG -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UPat, track_rewrites, GroupOp, Ops -from tinygrad.uop.upat import _get_code, upat_compile -import dis - -@track_rewrites() -def do_compile(up): - print("\n***** COMPILE", up) - match_code = _get_code(up, False) - match = upat_compile(up, lambda **kwargs: None) - print(match_code[0]) - if DEBUG >= 2: dis.dis(match) - return match_code[0] - -class TestUPatCompile(unittest.TestCase): - def test_double(self): - up = UPat.var("x") * UPat.cvar("c0") + UPat.var("x") * UPat.cvar("c1") - do_compile(up) - - def test_single(self): - up = UPat.var("x") + UPat.var("y") - do_compile(up) - - def test_xpx(self): - up = UPat.var("x") + UPat.var("x") - do_compile(up) - - def test_xp0(self): - up = UPat.var("x") + 0 - do_compile(up) - - def test_bool(self): - up = UPat.var('x', dtype=dtypes.bool) * UPat.var('y', dtype=dtypes.bool) - do_compile(up) - - def test_single_c(self): - up = (UPat.var("x") + UPat.var("y")) * UPat.var("c") - do_compile(up) - - def test_const_folding(self): - up = UPat(GroupOp.ALU-{Ops.THREEFRY}, name="a", src=UPat((Ops.VCONST, Ops.CONST))) - do_compile(up) - - @unittest.skip("fix this") - def test_range_named(self): - # this should be one src, but this should also still work - up = UPat(Ops.CAST, dtypes.float, UPat.var("x", dtypes.bfloat16)) - do_compile(up) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/unit/test_verify_ast.py b/tinygrad/test/unit/test_verify_ast.py deleted file mode 100644 index fd8a9212..00000000 --- a/tinygrad/test/unit/test_verify_ast.py +++ /dev/null @@ -1,98 +0,0 @@ -from __future__ import annotations -import unittest - -from tinygrad import Tensor -from tinygrad.codegen.kernel import Kernel -from tinygrad.helpers import DEBUG -from tinygrad.uop.ops import UOp, Ops, print_uops -from tinygrad.uop.spec import type_verify, ast_spec -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad import dtypes -from tinygrad.shape.view import View - -class InvalidASTException(Exception): pass -def helper_test_verify_ast(*stores:UOp) -> Kernel: - sink = UOp(Ops.SINK, dtypes.void, stores) - if DEBUG >= 3: - for op in stores: print(op) - try: type_verify(list(sink.toposort()), ast_spec) - except RuntimeError as e: raise InvalidASTException(e.args) - k = Kernel(sink) - k.linearize() - if DEBUG >= 6: print_uops(k.uops) - if DEBUG >= 4: print(k.to_program().src) - return k - -class TestVerifyAST(unittest.TestCase): - def test_tiny_add(self): - dtype = dtypes.int - buf_0 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 0) - buf_1 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 1) - buf_2 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 2) - a = UOp(Ops.LOAD, dtype, (buf_1.view(ShapeTracker.from_shape((32, 1))),)) - b = UOp(Ops.LOAD, dtype, (buf_2.view(ShapeTracker.from_shape((32, 1))),)) - store = UOp(Ops.STORE, dtypes.void, (buf_0.view(ShapeTracker.from_shape((32, 1))), a+b)) - helper_test_verify_ast(store) - - def test_exactly_one_full_shape(self): - dtype = dtypes.int - bufs = [UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), i) for i in range(6)] - a = UOp(Ops.LOAD, dtype, (bufs[2].view(ShapeTracker.from_shape((32, 1))),)) - b = UOp(Ops.LOAD, dtype, (bufs[3].view(ShapeTracker.from_shape((32, 1))),)) - st0 = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), a+b) - a = UOp(Ops.LOAD, dtype, (bufs[4].view(ShapeTracker.from_shape((32, 32))),)) - b = UOp(Ops.LOAD, dtype, (bufs[5].view(ShapeTracker.from_shape((32, 32))),)) - st1 = UOp.store(bufs[1], ShapeTracker.from_shape((32, 32)).to_uop(), a+b) - with self.assertRaises(InvalidASTException): helper_test_verify_ast(st0, st1) - - def test_no_implicit_broadcasting(self): - bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] - a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((4, 32))),)) - b = a + UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.MAX, (1,))) - st = UOp(Ops.STORE, dtypes.void, (bufs[0].view(ShapeTracker.from_shape((4, 32))), b)) - with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) - - def test_shrink_ok(self): - bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] - a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker((View((32, 32), strides=(32, 1), offset=0, mask=None, contiguous=True),))),)) - b = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker((View((32, 32), strides=(0, 1), offset=0, mask=None, contiguous=False),))),)) - st = UOp.store(bufs[0].view(ShapeTracker.from_shape((32, 32))), a+b) - helper_test_verify_ast(st) - - def test_reduce_store(self): - bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] - a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((32, 1))),)) - r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) - st = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), r) - with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) - - def test_reduce_add_store(self): - bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] - a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((32, 1))),)) - r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) - st = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), r+a) - with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) - - def test_buffer_uops_st(self): - a = Tensor.randn(4, 4)+2 - helper_test_verify_ast(ast:=a.schedule()[-1].ast) - store_st = [u.st for u in ast.toposort() if u.op is Ops.STORE][0] - self.assertEqual(store_st, ShapeTracker.from_shape((4, 4))) - const_st = [u.st for u in ast.toposort() if u.op is Ops.CONST][0] - self.assertEqual(const_st, ShapeTracker.from_shape((1, 1)).expand((4, 4))) - - def test_assert_swizzle(self): - buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - a = UOp(Ops.LOAD, dtypes.float, (buf.view(ShapeTracker.from_shape((32, 1))),)) - r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) - st = UOp.store(buf, ShapeTracker.from_shape((32, 1)).to_uop(), r.view(r.st.expand((32, 1)))+a) - with self.assertRaisesRegex(InvalidASTException, "UOp verification failed"): helper_test_verify_ast(st) - - def test_const_view_always_valid(self): - buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) - a = UOp.const(dtypes.int, 0).replace(src=(UOp(Ops.VIEW, dtypes.void, (), ShapeTracker.from_shape(())),)) - st = UOp.store(buf.view(ShapeTracker.from_shape(())), a.cast(dtypes.float)) - helper_test_verify_ast(st) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_view.py b/tinygrad/test/unit/test_view.py deleted file mode 100644 index 45f7b594..00000000 --- a/tinygrad/test/unit/test_view.py +++ /dev/null @@ -1,227 +0,0 @@ -#!/usr/bin/env python -import unittest -from tinygrad.shape.view import View, merge_dims -# from tinygrad.shape.shapetracker import ShapeTracker - -class TestView(unittest.TestCase): - def test_canonicalize_empty_mask(self): - v = View.create(shape=(2,2,2), strides=(4,2,1), mask=((0,2),(0,2),(0,2))) - self.assertIsNone(v.mask) - v = View.create(shape=(4,3,2), strides=(1,4,10), mask=((0,4),(0,3),(0,2))) - self.assertIsNone(v.mask) - - def test_minify_zero_strided_dims(self): - target = View.create(shape=(2,2), strides=(30,2), offset=7, mask=None) - v = View.create(shape=(2,1,2), strides=(30,0,2), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(1,2,2), strides=(0,30,2), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(2,2,1), strides=(30,2,0), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(2,1,1,2), strides=(30,0,0,2), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(1,1,2,2), strides=(0,0,30,2), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(2,2,1,1), strides=(30,2,0,0), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(1,2,2,1), strides=(0,30,2,0), offset=7, mask=None) - self.assertEqual(v.minify(), target) - v = View.create(shape=(1,2,1,2), strides=(0,30,0,2), offset=7, mask=None) - self.assertEqual(v.minify(), target) - - def test_empty_mask_contiguous(self): - v1 = View.create(shape=(2,2,2), strides=(4,2,1), mask=None) - v2 = View.create(shape=(2,2,2), strides=(4,2,1), mask=((0,2),(0,2),(0,2))) - self.assertEqual(v1.contiguous, v2.contiguous) - v1 = View.create(shape=(1,1,1,4), strides=(0,0,0,1), offset=0, mask=None) - v2 = View.create(shape=(1,1,1,4), strides=(0,0,0,1), offset=0, mask=((0,1),(0,1),(0,1),(0,4))) - self.assertEqual(v1.contiguous, v2.contiguous) - v = View.create(shape=(2,3,4), mask=((0,2),(0,3),(0,4))) - self.assertTrue(v.contiguous) - - def test_reshape_all_invalid(self): - v = View.create((4,5), mask=((0,0), (0,0))).reshape((20,)) - self.assertIsNotNone(v) - self.assertEqual(v, View.create((20,), mask=((0,0),))) - -class TestMergeDims(unittest.TestCase): - def test_contiguous(self): - shape = (2, 3, 4) - strides = (12, 4, 1) #=strides_for_shape(shape) - m = merge_dims(shape, strides) - self.assertEqual(m, ((24, 1, 24),)) - - def test_0_in_strides(self): - shape = (2, 3, 4) - self.assertEqual(merge_dims(shape, (0, 4, 1)), ((2, 0, 0), (12, 1, 12))) - self.assertEqual(merge_dims(shape, (0, 0, 1)), ((6, 0, 0), (4, 1, 4))) - self.assertEqual(merge_dims(shape, (3, 1, 0)), ((6, 1, 6), (4, 0, 4))) - self.assertEqual(merge_dims(shape, (0, 0, 0)), ((24, 0, 0),)) - - def test_pad(self): - # print(ShapeTracker.from_shape((1, 2)).pad(((1, 0), (0, 1))).views[-1]) - self.assertEqual(merge_dims((2, 3), (0, 1), ((1, 2), (0, 2))), ((6, 1, 3),)) - - # print(f"{ShapeTracker.from_shape((1, 1, 2)).pad(((1, 0), (1, 0), (0, 1))).views[-1]}") - self.assertEqual(merge_dims((2, 2, 3), (0, 0, 1), ((1, 2), (1, 2), (0, 2))), ((12, 1, 3),)) - - # print(f"{ShapeTracker.from_shape((1, 1, 2, 2)).pad(((1, 0), (1, 0), (0, 1), (0, 1))).views[-1]}") - self.assertEqual(merge_dims((2, 2, 3, 3), (0, 0, 2, 1), ((1, 2), (1, 2), (0, 2), (0, 2))), ((12, 2, 3), (3, 1, 3))) - - # print(f"{ShapeTracker.from_shape((2, 1, 2)).pad(((0, 0), (1, 0), (0, 1))).views[-1]}") - self.assertEqual(merge_dims((2, 2, 3), (2, 0, 1), ((0, 2), (1, 2), (0, 2))), ((2, 2, 2), (6, 1, 3))) - - def test_different_1_pad(self): - # print(f"{ShapeTracker.from_shape((2, 2, 1)).pad(((0, 0), (0, 0), (0, 1))).views[-1]}") - self.assertEqual(merge_dims((2, 2, 2), (2, 1, 0), ((0, 2), (0, 2), (0, 1))), ((4, 1, 4), (2, 0, 2))) - - # print(f"{ShapeTracker.from_shape((2, 1, 1)).pad(((0, 0), (0, 1), (0, 1))).views[-1]}") - self.assertEqual(merge_dims((2, 2, 2), (1, 0, 0), ((0, 2), (0, 2), (0, 1))), ((2, 1, 2), (4, 0, 4))) - -class TestMergeViews(unittest.TestCase): - def test_with_mask_0(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - v0 = View(shape=(1, 1, 5, 8), strides=(0, 0, 5, 1), offset=-3, mask=((0, 1), (0, 1), (0, 5), (3, 8)), contiguous=False) - v1 = View(shape=(1, 1, 2, 2), strides=(0, 0, 8, 1), offset=3, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(1, 1, 2, 2), strides=(0, 0, 5, 1), offset=0, mask=None, contiguous=False)) - - def test_with_mask_1(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, 3, 1), offset=-6, mask=((0, 3), (0, 3), (2, 4), (1, 3)), contiguous=False) - v1 = View(shape=(3, 3, 2, 2), strides=(45, 15, 3, 1), offset=7, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(3, 3, 2, 2), strides=(27, 9, 3, 1), offset=1, mask=None, contiguous=False)) - - def test_with_mask_2(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, -3, 1), offset=6, mask=((0, 3), (0, 3), (0, 2), (0, 2)), contiguous=False) - v1 = View(shape=(3, 3, 2, 2), strides=(45, 15, -3, 1), offset=3, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(3, 3, 2, 2), strides=(27, 9, 3, 1), offset=3, mask=None, contiguous=False)) - - def test_with_mask_3(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - # has a mask in the final view - v0 = View(shape=(3, 3, 4, 4), strides=(27, 9, 3, 1), offset=-5, mask=((0, 3), (0, 3), (2, 4), (0, 2)), contiguous=False) - v1 = View(shape=(3, 3, 4, 2), strides=(48, 16, 4, 1), offset=0, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(3, 3, 4, 2), strides=(27, 9, 3, 1), offset=-5, mask=((0, 3), (0, 3), (2, 4), (0, 2)), contiguous=False)) - - def test_with_mask_4(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - # has a mask in the final view - v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, -3, 1), offset=6, mask=((0, 3), (0, 3), (0, 2), (1, 3)), contiguous=False) - v1 = View(shape=(3, 3, 3, 3), strides=(45, 15, 3, 1), offset=6, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(3, 3, 3, 3), strides=(0, 0, 0, 0), offset=0, mask=((0, 0), (0, 0), (0, 0), (0, 0)), contiguous=False)) - - def test_with_mask_5(self): - # from test/test_ops.py::TestOps::test_pad_reflect_mode - # has a mask in the final view - v0 = View(shape=(1, 1, 6, 5), strides=(0, 0, 5, 1), offset=-5, mask=((0, 1), (0, 1), (1, 6), (0, 5)), contiguous=False) - v1 = View(shape=(1, 1, 6, 3), strides=(0, 0, 5, -1), offset=3, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(1, 1, 6, 3), strides=(0, 0, 5, -1), offset=-2, mask=((0, 1), (0, 1), (1, 6), (0, 3)), contiguous=False)) - - @unittest.expectedFailure # TODO: fix these - def test_merges_from_fuzzer1(self): - v0 = View(shape=(2, 4), strides=(2, 1), offset=-2, mask=((0, 2), (2, 4)), contiguous=False) - v1 = View(shape=(2, 4, 2, 2), strides=(4, 0, -2, -1), offset=3, mask=None, contiguous=False) - target = View(shape=(2, 4, 2, 2), strides=(2, 0, 0, -1), offset=1, mask=((0, 2), (0, 4), (0, 1), (0, 2)), contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, target) - - @unittest.expectedFailure # TODO: fix these - def test_merges_from_fuzzer2(self): - v0 = View(shape=(5, 10, 12), strides=(100, 1, 10), offset=-20, mask=((0, 5), (0, 10), (2, 12)), contiguous=False) - v1 = View(shape=(10, 6, 5, 2, 2), strides=(12, 2, 120, 1, 0), offset=0, mask=None, contiguous=False) - target = View(shape=(10, 6, 5, 2, 2), strides=(1, 20, 100, 10, 0), offset=-20, mask=((0, 10), (1, 6), (0, 5), (0, 2), (0, 2)), contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, target) - - @unittest.expectedFailure # TODO: fix these - def test_merges_from_fuzzer3(self): - v0 = View(shape=(8, 7, 3), strides=(1, 12, -4), offset=6, mask=((2, 6), (0, 7), (0, 3)), contiguous=False) - v1 = View(shape=(4, 2, 6, 2, 1), strides=(42, 21, 3, 1, 0), offset=4, mask=None, contiguous=False) - target = View(shape=(4, 2, 6, 2, 1), strides=(2, 1, 12, -4, 0), offset=14, mask=((1, 3), (0, 2), (0, 6), (0, 2), (0, 1)), contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, target) - - @unittest.expectedFailure # TODO: fix these - def test_merges_from_fuzzer4(self): - v0 = View(shape=(7, 21, 3), strides=(54, 3, 1), offset=-9, mask=((0, 6), (3, 21), (0, 3)), contiguous=False) - v1 = View(shape=(5, 3, 3, 7), strides=(63, 1, 3, 9), offset=63, mask=None, contiguous=False) - target = View(shape=(5, 3, 3, 7), strides=(54, 1, 3, 9), offset=45, mask=((0, 5), (0, 3), (0, 3), (1, 7)), contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, target) - - @unittest.expectedFailure # TODO: fix these - def test_merges_from_fuzzer5(self): - v0 = View(shape=(5, 1, 24), strides=(20, 0, 1), offset=-2, mask=((0, 5), (0, 1), (2, 22)), contiguous=False) - v1 = View(shape=(12, 2, 5, 2, 1), strides=(2, 1, 24, 0, 0), offset=0, mask=None, contiguous=False) - target = View(shape=(12, 2, 5, 2, 1), strides=(2, 1, 20, 0, 0), offset=-2, mask=((1, 11), (0, 2), (0, 5), (0, 2), (0, 1)), contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, target) - - def test_view_padded_area1(self): - # test_multinomial - v0 = View(shape=(2,), strides=(0,), offset=0, mask=((1, 2),), contiguous=False) - v1 = View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(1,), strides=(0,), offset=0, mask=((0, 0),), contiguous=False)) - - def test_view_padded_area2(self): - # test_pad_reflect_mode - v0 = View(shape=(1, 1, 10, 7), strides=(0, 0, 5, 1), offset=-15, mask=((0, 1), (0, 1), (3, 8), (0, 5)), contiguous=False) - v1 = View(shape=(0, 0, 0, 0), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(0, 0, 0, 0), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True)) - - def test_view_padded_area3(self): - # test_roll - v0 = View(shape=(2, 4), strides=(0, 1), offset=4, mask=((0, 1), (0, 4)), contiguous=False) - v1 = View(shape=(1, 4), strides=(0, 1), offset=4, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(1, 4), strides=(0, 0), offset=0, mask=((0, 0), (0, 0)), contiguous=False)) - - def test_view_padded_area4(self): - # test_std_mean - v0 = View(shape=(2,), strides=(0,), offset=0, mask=((0, 1),), contiguous=False) - v1 = View(shape=(1, 1, 1), strides=(0, 0, 0), offset=1, mask=None, contiguous=False) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=((0, 0), (0, 0), (0, 0)), contiguous=False)) - - def test_empty_shape_view1(self): - # test_stack_slice - v0 = View(shape=(3, 5), strides=(0, 1), offset=0, mask=((0, 1), (0, 5)), contiguous=False) - v1 = View(shape=(), strides=(), offset=0, mask=None, contiguous=True) - v = v0 + v1 - self.assertIsNotNone(v) - self.assertEqual(v, View(shape=(), strides=(), offset=0, mask=None, contiguous=True)) - - def test_empty_shape_view2(self): - # test_std_mean - v0 = View(shape=(2,), strides=(0,), offset=0, mask=((1, 2),), contiguous=False) - v1 = View(shape=(), strides=(), offset=0, mask=None, contiguous=True) - v = v0 + v1 - # TODO: why is this different? - self.assertIsNone(v) - -if __name__ == '__main__': - unittest.main() diff --git a/tinygrad/test/unit/test_viz.py b/tinygrad/test/unit/test_viz.py deleted file mode 100644 index 90e79248..00000000 --- a/tinygrad/test/unit/test_viz.py +++ /dev/null @@ -1,295 +0,0 @@ -import unittest, decimal, json -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import TRACK_MATCH_STATS, TrackedPatternMatcher, UOp, graph_rewrite, track_rewrites, UPat, Ops -from tinygrad.codegen.symbolic import symbolic -from tinygrad.uop.ops import tracked_ctxs as contexts, tracked_keys as keys, _name_cnt, _substitute -from tinygrad.device import ProfileDeviceEvent, ProfileRangeEvent, ProfileGraphEvent, ProfileGraphEntry -from tinygrad.viz.serve import get_metadata, get_details, uop_to_json, to_perfetto - -# NOTE: VIZ tests always use the tracked PatternMatcher instance -symbolic = TrackedPatternMatcher(symbolic.patterns) -substitute = TrackedPatternMatcher(_substitute.patterns) - -inner_rewrite = TrackedPatternMatcher([ - (UPat.cvar("x"), lambda x: None if x.dtype == dtypes.float32 else UOp.const(dtypes.float32, x.arg)), -]) - -l2 = TrackedPatternMatcher([(UPat(Ops.CUSTOM, arg=2, name="x"), lambda x: x.replace(arg=3))]) -l1 = TrackedPatternMatcher([(UPat(Ops.CUSTOM, arg=1, name="x"), lambda x: graph_rewrite(x.replace(arg=2), l2))]) -l0 = TrackedPatternMatcher([(UPat(Ops.CUSTOM, arg=0, name="x"), lambda x: graph_rewrite(x.replace(arg=1), l1))]) - -class TestViz(unittest.TestCase): - def setUp(self): - # clear the global context - contexts.clear() - keys.clear() - _name_cnt.clear() - self.tms = TRACK_MATCH_STATS.value - TRACK_MATCH_STATS.value = 2 - def tearDown(self): TRACK_MATCH_STATS.value = self.tms - - def test_viz_simple(self): - a = UOp.variable("a", 0, 10) - @track_rewrites(named=True) - def test(sink): return graph_rewrite(sink, symbolic) - test(a*1) - ret = get_metadata(keys, contexts) - self.assertEqual(len(ret), 1) - key, val = ret[0]["name"], ret[0]["steps"] - self.assertEqual(key, "test_1") - self.assertEqual(val[0]["match_count"], 1) - - def test_track_two_rewrites(self): - a = UOp.variable("a", 0, 10) - @track_rewrites(named=True) - def test(sink): return graph_rewrite(sink, symbolic) - test((a+a)*1) - ret = get_metadata(keys, contexts) - key, val = ret[0]["name"], ret[0]["steps"] - self.assertEqual(len(ret), 1) # one context - self.assertEqual(len(val), 1) # one graph_rewrite call in context - self.assertEqual(key, "test_1") - self.assertEqual(val[0]["match_count"], 2) # two upats applied - - def test_track_multiple_calls_one_ctx(self): - a = UOp.variable("a", 0, 10) - @track_rewrites(named=True) - def test(a, b): - a = graph_rewrite(a, symbolic) - b = graph_rewrite(b, symbolic) - test(a*1, a*5) - ret = get_metadata(keys, contexts) - key, val = ret[0]["name"], ret[0]["steps"] - self.assertEqual(len(ret), 1) # one context - self.assertEqual(len(val), 2) # two graph_rewrite calls in context - self.assertEqual(key, "test_1") - self.assertEqual(val[0]["match_count"], 1) # one rewrite for a*0 - self.assertEqual(val[1]["match_count"], 0) # no rewrites for a*5 - - def test_track_rewrites(self): - @track_rewrites(named=True) - def do_rewrite(x:UOp): return graph_rewrite(x, symbolic) - a = UOp.variable("a", 0, 10) - b = UOp.variable("b", 0, 4) - do_rewrite(a*1) - do_rewrite(a*b) - ret = get_metadata(keys, contexts) - self.assertEqual(len(ret), 2) - key, m = ret[0]["name"], ret[0]["steps"] - self.assertEqual(key, "do_rewrite_1") - self.assertEqual(m[0]["match_count"], 1) - key, m = ret[1]["name"], ret[1]["steps"] - self.assertEqual(key, "do_rewrite_2") - self.assertEqual(m[0]["match_count"], 0) - - def test_track_rewrites_with_exception(self): - @track_rewrites() - def do_rewrite(x:UOp): - x = graph_rewrite(x, symbolic) # NOTE: viz tracks this - raise Exception("test") - a = UOp.variable("a", 0, 10) - with self.assertRaises(Exception): do_rewrite(a*1) - ret = get_metadata(keys, contexts) - self.assertEqual(len(ret), 1) - - def test_track_rewrites_name_fxn(self): - @track_rewrites(name_fxn=lambda _,ret: f"output_{ret}") - def do_rewrite(x:UOp): - x = graph_rewrite(x, symbolic) - return x.render() - expr = UOp.variable("a",0,10)*UOp.variable("b",0,10) - do_rewrite(expr) - key = get_metadata(keys, contexts)[0]["name"] - self.assertEqual(key, "output_(a*b) n1") - - expr2 = UOp.variable("a",0,10)+UOp.variable("b",0,10) - do_rewrite(expr2) - key = get_metadata(keys, contexts)[1]["name"] - self.assertEqual(key, "output_(a+b) n2") - - @unittest.expectedFailure - def test_name_in_positional_arg(self): - @track_rewrites(named=True) - def test(sink): return graph_rewrite(sink, symbolic, None, False, "name") - test(UOp.variable("a", 0, 1)) - self.assertEqual(contexts[0].pop().name, "name") - - # NOTE: CONST UOps do not get nodes in the graph - def test_dont_create_const_nodes(self): - a = UOp.variable("a", 0, 10) - b = UOp.variable("b", 0, 4) - self.assertEqual(len(uop_to_json(a*1)), 2) - self.assertEqual(len(uop_to_json(a*b)), 3) - - def test_bottom_up_rewrite(self): - a = UOp.variable("a", 0, 10) - b = UOp.variable("b", 0, 10) - c = UOp.variable("c", 0, 10) - @track_rewrites(named=True) - def fxn(sink): return graph_rewrite(sink, substitute, ctx={a+b:c}, bottom_up=True) - fxn(a+b) - #UOp.substitute(a+b, {a+b:c}) - ret = get_metadata(keys, contexts) - self.assertEqual(len(ret), 1) - m = ret[0]["steps"] - self.assertEqual(m[0]["match_count"], 1) - - # NOTE: calling graph_rewrite when the function isn't decorated with track_rewrites should not VIZ - def test_rewrite_without_context(self): - def untracked_graph_rewrite(sink): return graph_rewrite(sink, symbolic) - @track_rewrites(named=True) - def tracked_graph_rewrite(sink): return graph_rewrite(sink, symbolic) - # test - add = UOp.const(dtypes.int, 2) + UOp.const(dtypes.int, 1) - untracked_graph_rewrite(add) - self.assertEqual(len(contexts), 0) - tracked_graph_rewrite(add) - self.assertEqual(len(contexts), 1) - - def test_inner_rewrite_location(self): - # inner rewrite gets tracked in another context - def inner_rewrite(sink): return graph_rewrite(sink, symbolic) - @track_rewrites(named=True) - def tracked_graph_rewrite(sink): return inner_rewrite(sink) - # test - add = UOp.const(dtypes.int, 2) + UOp.const(dtypes.int, 1) - tracked_graph_rewrite(add) - self.assertEqual(len(contexts), 1) - # location of context is inner_rewrite - fp, lineno = contexts[0][0].loc - self.assertEqual(lineno, inner_rewrite.__code__.co_firstlineno) - self.assertEqual(fp, inner_rewrite.__code__.co_filename) - - def test_nested_rewrite(self): - def make_float(x:UOp, y:UOp): - if x.dtype == dtypes.float: return None - x2 = graph_rewrite(x, inner_rewrite, name="inner_x") - y2 = graph_rewrite(y, inner_rewrite, name="inner_y") - return None if (x2 is x and y2 is y) else x2+y2 - outer_rewrite = TrackedPatternMatcher([(UPat.cvar("x")+UPat.cvar("y"), make_float),]) - @track_rewrites(named=True) - def rewrite(u:UOp): return graph_rewrite(u, outer_rewrite, name="outer") - a = UOp.const(dtypes.int, 1)+UOp.const(dtypes.int, 2) - rewrite(a) - self.assertEqual(len(contexts), 1) - tracked = contexts[0] - self.assertEqual(len(tracked), 3) - self.assertEqual(tracked[0].depth, 0) - self.assertEqual(tracked[1].depth, 1) - self.assertEqual(tracked[2].depth, 1) - # NOTE: this is sorted by the time called, maybe it should be by depth - self.assertEqual([x.name for x in tracked], ["outer", "inner_x", "inner_y"]) - self.assertEqual([len(x.matches) for x in tracked], [1, 1, 1]) - - def test_depth_level(self): - @track_rewrites(named=True) - def fxn(u:UOp): return graph_rewrite(u, l0) - ret = fxn(UOp(Ops.CUSTOM, arg=0)) - assert ret is UOp(Ops.CUSTOM, arg=3) - self.assertEqual(len(contexts), 1) - tracked = contexts[0] - self.assertEqual(tracked[0].depth, 0) - self.assertEqual(tracked[1].depth, 1) - self.assertEqual(tracked[2].depth, 2) - - def test_shape_label(self): - a = UOp.new_buffer("CPU", 1, dtypes.uint8).expand((4,)) - b = UOp.new_buffer("CPU", 1, dtypes.uint8).expand((8,)) - n = a+b - ser = uop_to_json(n) - self.assertIn("(4,)", ser[id(a)]["label"]) - self.assertIn("(8,)", ser[id(b)]["label"]) - with self.assertRaises(AssertionError): n.st - _ = ser[id(n)]["label"] # VIZ should not crash - - def test_default_named(self): - test = UOp(Ops.NOOP) - @track_rewrites() - def test_fxn(): return graph_rewrite(test, l0) - assert test_fxn() is test - self.assertEqual(keys[0], "test_fxn_1") - - @unittest.skip("TODO: doesn't work") - def test_recursion_err(self): - inf = TrackedPatternMatcher([ - (UPat.const(dtypes.int, 0).named("a"), lambda a: a.const_like(1)), - (UPat.const(dtypes.int, 1).named("b"), lambda b: b.const_like(0)), - ]) - @track_rewrites(named=True) - def func(u): return graph_rewrite(u, inf) - with self.assertRaises(RecursionError): func(UOp.const(dtypes.int, 0)) - _ = list(get_details(keys[0], contexts[0][0])) - -class TextVizProfiler(unittest.TestCase): - def test_perfetto_node(self): - prof = [ProfileRangeEvent(device='NV', name='E_2', st=decimal.Decimal(1000), en=decimal.Decimal(1010), is_copy=False), - ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100))] - - j = json.loads(to_perfetto(prof)) - - # Device regs always first - self.assertEqual(j['traceEvents'][0]['name'], 'process_name') - self.assertEqual(j['traceEvents'][0]['ph'], 'M') - self.assertEqual(j['traceEvents'][0]['args']['name'], 'NV') - - self.assertEqual(j['traceEvents'][1]['name'], 'thread_name') - self.assertEqual(j['traceEvents'][1]['ph'], 'M') - self.assertEqual(j['traceEvents'][1]['pid'], j['traceEvents'][0]['pid']) - self.assertEqual(j['traceEvents'][1]['tid'], 0) - self.assertEqual(j['traceEvents'][1]['args']['name'], 'COMPUTE') - - self.assertEqual(j['traceEvents'][2]['name'], 'thread_name') - self.assertEqual(j['traceEvents'][2]['ph'], 'M') - self.assertEqual(j['traceEvents'][2]['pid'], j['traceEvents'][0]['pid']) - self.assertEqual(j['traceEvents'][2]['tid'], 1) - self.assertEqual(j['traceEvents'][2]['args']['name'], 'COPY') - - self.assertEqual(j['traceEvents'][3]['name'], 'E_2') - self.assertEqual(j['traceEvents'][3]['ts'], 0) - self.assertEqual(j['traceEvents'][3]['dur'], 10) - self.assertEqual(j['traceEvents'][3]['ph'], 'X') - self.assertEqual(j['traceEvents'][3]['pid'], j['traceEvents'][0]['pid']) - self.assertEqual(j['traceEvents'][3]['tid'], 0) - - def test_perfetto_copy_node(self): - prof = [ProfileRangeEvent(device='NV', name='COPYxx', st=decimal.Decimal(1000), en=decimal.Decimal(1010), is_copy=True), - ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100))] - - j = json.loads(to_perfetto(prof)) - - self.assertEqual(j['traceEvents'][3]['name'], 'COPYxx') - self.assertEqual(j['traceEvents'][3]['ts'], 900) # diff clock - self.assertEqual(j['traceEvents'][3]['dur'], 10) - self.assertEqual(j['traceEvents'][3]['ph'], 'X') - self.assertEqual(j['traceEvents'][3]['tid'], 1) - - def test_perfetto_graph(self): - prof = [ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100)), - ProfileDeviceEvent(device='NV:1', comp_tdiff=decimal.Decimal(-500), copy_tdiff=decimal.Decimal(-50)), - ProfileGraphEvent(ents=[ProfileGraphEntry(device='NV', name='E_25_4n2', st_id=0, en_id=1, is_copy=False), - ProfileGraphEntry(device='NV:1', name='NV -> NV:1', st_id=2, en_id=3, is_copy=True)], - deps=[[], [0]], - sigs=[decimal.Decimal(1000), decimal.Decimal(1002), decimal.Decimal(1004), decimal.Decimal(1008)])] - - j = json.loads(to_perfetto(prof)) - - # Device regs always first - self.assertEqual(j['traceEvents'][0]['args']['name'], 'NV') - self.assertEqual(j['traceEvents'][1]['args']['name'], 'COMPUTE') - self.assertEqual(j['traceEvents'][2]['args']['name'], 'COPY') - self.assertEqual(j['traceEvents'][3]['args']['name'], 'NV:1') - self.assertEqual(j['traceEvents'][4]['args']['name'], 'COMPUTE') - self.assertEqual(j['traceEvents'][5]['args']['name'], 'COPY') - - self.assertEqual(j['traceEvents'][6]['name'], 'E_25_4n2') - self.assertEqual(j['traceEvents'][6]['ts'], 0) - self.assertEqual(j['traceEvents'][6]['dur'], 2) - self.assertEqual(j['traceEvents'][6]['pid'], j['traceEvents'][0]['pid']) - - self.assertEqual(j['traceEvents'][7]['name'], 'NV -> NV:1') - self.assertEqual(j['traceEvents'][7]['ts'], 954) - self.assertEqual(j['traceEvents'][7]['dur'], 4) - self.assertEqual(j['traceEvents'][7]['pid'], j['traceEvents'][3]['pid']) - -if __name__ == "__main__": - unittest.main() diff --git a/tinygrad/test/web/test_viz.js b/tinygrad/test/web/test_viz.js deleted file mode 100644 index 80475734..00000000 --- a/tinygrad/test/web/test_viz.js +++ /dev/null @@ -1,34 +0,0 @@ -const { spawn } = require("child_process"); -const puppeteer = require("puppeteer"); - -async function main() { - // ** start viz server - const proc = spawn("python", ["-u", "-c", "from tinygrad import Tensor; Tensor.arange(4).realize()"], { env: { ...process.env, VIZ:"1" }, - stdio: ["inherit", "pipe", "inherit"]}); - await new Promise(resolve => proc.stdout.on("data", r => { - if (r.includes("ready")) resolve(); - })); - - // ** run browser tests - let browser; - try { - browser = await puppeteer.launch({ headless: true }); - const page = await browser.newPage(); - const res = await page.goto("http://localhost:8000", { waitUntil:"domcontentloaded" }); - if (res.status() !== 200) throw new Error("Failed to load page"); - const scheduleSelector = await page.waitForSelector("ul"); - scheduleSelector.click(); - await page.waitForSelector("rect"); - const nodes = await page.evaluate(() => document.querySelectorAll("#nodes > g").length); - const edges = await page.evaluate(() => document.querySelectorAll("#edges > path").length); - if (!nodes || !edges) { - throw new Error("VIZ didn't render a graph") - } - } finally { - // ** cleanups - if (browser) await browser.close(); - proc.kill(); - } -} - -main(); diff --git a/tinygrad/test/web/test_webgpu.js b/tinygrad/test/web/test_webgpu.js deleted file mode 100644 index 1c953da8..00000000 --- a/tinygrad/test/web/test_webgpu.js +++ /dev/null @@ -1,65 +0,0 @@ -const puppeteer = require("puppeteer"); -const { spawn } = require("child_process"); -const res = spawn("python", ["-m", "http.server", "8000"], { shell: true }); - -async function timeout(time) { - return new Promise((resolve) => setTimeout(resolve, time)); -} - -function cleanup(err) { - console.log("cleaning up"); - res.kill(); - if (err != null) { - console.error(err); - process.exit(1); - } - process.exit(0); -} - -async function waitForText(selector, text) { - let n = 0; - let ready = false; - while (n < 30) { - const res = await (await selector.getProperty("textContent")).jsonValue(); - console.log(`waiting for text ${text} got ${res}`); - if (res == text) { - ready = true; - break; - } - await timeout(1000); - n += 1; - } - return ready; -} - -async function runTest() { - const browser = await puppeteer.launch({ - headless: false, - args: ["--enable-unsafe-webgpu"], - }); - const page = await browser.newPage(); - - page - .on("console", (message) => - console.log(`message from console ${message.text()}`), - ) - .on("pageerror", ({ message }) => - console.log(`error from page ${message}`), - ); - - const res = await page.goto("http://localhost:8000/examples/webgpu/efficientnet/index.html"); - if (res.status() !== 200) throw new Error("Failed to load page"); - - const textSelector = await page.waitForSelector("#result"); - const buttonSelector = await page.waitForSelector("input[type=button]"); - const ready = await waitForText(textSelector, "ready"); - if (!ready) throw new Error("Failed to load page"); - - await buttonSelector.evaluate((e) => e.click()); - const done = await waitForText(textSelector, "hen"); - if (!done) throw new Error("failed to get hen"); - - cleanup(null); -} - -runTest().catch((err) => cleanup(err)); diff --git a/tinygrad/test_driven_development.sh b/tinygrad/test_driven_development.sh deleted file mode 100755 index e868497e..00000000 --- a/tinygrad/test_driven_development.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -python3 test/external/process_replay/reset.py -CAPTURE_PROCESS_REPLAY=1 pytest -n auto test/test_tiny.py test/test_uop_graph.py test/test_ops.py test/test_linearizer.py -while true; do - if python3 test/test_tiny.py; then - PYTHONPATH="." python3 test/external/process_replay/process_replay.py - fi -done diff --git a/tinygrad/tinygrad/__init__.py b/tinygrad/tinygrad/__init__.py deleted file mode 100644 index 5bc12f91..00000000 --- a/tinygrad/tinygrad/__init__.py +++ /dev/null @@ -1,11 +0,0 @@ -import os -if int(os.getenv("TYPED", "0")): - from typeguard import install_import_hook - install_import_hook(__name__) -from tinygrad.tensor import Tensor # noqa: F401 -from tinygrad.engine.jit import TinyJit # noqa: F401 -from tinygrad.uop.ops import UOp -Variable = UOp.variable -from tinygrad.dtype import dtypes # noqa: F401 -from tinygrad.helpers import GlobalCounters, fetch, Context, getenv # noqa: F401 -from tinygrad.device import Device # noqa: F401 diff --git a/tinygrad/tinygrad/codegen/__init__.py b/tinygrad/tinygrad/codegen/__init__.py deleted file mode 100644 index fc3eb412..00000000 --- a/tinygrad/tinygrad/codegen/__init__.py +++ /dev/null @@ -1,79 +0,0 @@ -from typing import Any, Callable -import functools -from dataclasses import dataclass -from tinygrad.helpers import QUANTIZE, DEVECTORIZE, TRANSCENDENTAL -from tinygrad.uop.ops import PatternMatcher, graph_rewrite, UOp -from tinygrad.renderer import Renderer - -# import all pattern matchers here -from tinygrad.codegen.lowerer import pm_quant, pm_lowerer, get_index -from tinygrad.codegen.symbolic import sym, symbolic_simple, gep_pushing -from tinygrad.codegen.expander import migrate_indexing, pm_store_ignore, pm_move_ignore, pm_delete_ignore, expander -from tinygrad.codegen.devectorizer import load_store_folding, load_store_indexing, devectorize, \ - pm_reduce, ReduceContext, correct_load_store, pm_render, get_late_rewrite_patterns -from tinygrad.codegen.linearize import block_create, pm_blockend_merge, block_merge, pm_finalize, BlockContext - -@dataclass -class RewriteStep: - pm: PatternMatcher - ctx: Callable[[UOp], Any]|None = None - name: str|None = None - bottom_up: bool = False - def __call__(self, sink:UOp): - return graph_rewrite(sink, self.pm, ctx=self.ctx(sink) if self.ctx is not None else None, name=self.name, bottom_up=self.bottom_up) - -def apply_rewrites(sink:UOp, rewrites:list[RewriteStep]): return functools.reduce(lambda x,f: f(x), rewrites, sink) - -rewrites_for_linearizer = [ - RewriteStep(block_create, ctx=BlockContext.from_sink, name="Linearizer: Create Blocks", bottom_up=True), - RewriteStep(pm_blockend_merge, name="Linearizer: Merge Blockends"), - RewriteStep(block_merge, name="Linearizer: Merge Blocks"), - RewriteStep(pm_finalize, name="Linearizer: Finalize")] - -def get_rewrites_for_renderer(opts:Renderer, linearizer:bool=True) -> list[RewriteStep]: - # cache with the values of the context vars - return _get_rewrites_for_renderer(opts, linearizer, QUANTIZE.value, DEVECTORIZE.value, TRANSCENDENTAL.value) - -@functools.cache -def _get_rewrites_for_renderer(opts:Renderer, linearizer:bool, _QUANTIZE, _DEVECTORIZE, _TRANSCENDENTAL) -> list[RewriteStep]: - # ** lowerer (rewrite_shapetracker_with_index) ** - ret: list[RewriteStep] = [] - if _QUANTIZE and opts.device in {"CPU", "DSP"}: ret.append(RewriteStep(pm_quant, name="quantize")) - ret.append(RewriteStep(pm_lowerer, lambda ast: get_index(ast, opts), name="lowerer")) - - # ** expander (expand_rewrite) ** - ret.append(RewriteStep(sym+migrate_indexing, name="initial symbolic")) - - # ignore (for masked stores) - ret.append(RewriteStep(pm_store_ignore, name="store_ignore")) - ret.append(RewriteStep(pm_move_ignore, name="move_ignore")) - - # expand + remove surviving ignores - ret.append(RewriteStep(pm_delete_ignore+sym+expander, name="expander")) - - # ** devectorizer (full_graph_rewrite) ** - # remove reduce - ret.append(RewriteStep(pm_reduce+gep_pushing, lambda _: ReduceContext(), name="remove_reduce")) - - # devectorize (TODO: does this need opts?) - if _DEVECTORIZE >= 2: pm_devectorize = sym+load_store_folding+load_store_indexing - elif _DEVECTORIZE: pm_devectorize = sym+devectorize+load_store_folding+correct_load_store+load_store_indexing - else: pm_devectorize = sym+load_store_folding+correct_load_store+load_store_indexing - ret.append(RewriteStep(pm_devectorize, lambda _: opts, name="devectorize")) - - supported_ops = tuple(opts.code_for_op.keys()) - extra_matcher = opts.extra_matcher if opts.extra_matcher is not None else PatternMatcher([]) - - # optional pre matcher - if opts.pre_matcher is not None: ret.append(RewriteStep(opts.pre_matcher, name="pre_matcher")) - - # final rules for the renderer (without sym) - pm_final_rewrite = symbolic_simple+get_late_rewrite_patterns(supported_ops, _TRANSCENDENTAL>=2)+pm_render+extra_matcher - ret.append(RewriteStep(pm_final_rewrite, lambda _: opts, name="final rewrite")) - - # return the list (with optional linearizer) - return ret + (rewrites_for_linearizer if linearizer else []) - -def full_rewrite_to_sink(sink:UOp, opts:Renderer|None=None, linearizer:bool=False) -> UOp: - return apply_rewrites(sink, get_rewrites_for_renderer(opts if opts is not None else Renderer(), linearizer)) -def full_rewrite(sink:UOp, opts:Renderer|None=None) -> list[UOp]: return list(full_rewrite_to_sink(sink, opts, linearizer=True).arg.lst) diff --git a/tinygrad/tinygrad/codegen/devectorizer.py b/tinygrad/tinygrad/codegen/devectorizer.py deleted file mode 100644 index c3a4911e..00000000 --- a/tinygrad/tinygrad/codegen/devectorizer.py +++ /dev/null @@ -1,431 +0,0 @@ -from typing import Any, Callable, cast -import functools, operator, itertools -from collections import defaultdict -from dataclasses import dataclass -from tinygrad.device import is_dtype_supported -from tinygrad.dtype import dtypes, ImageDType, PtrDType, promo_lattice, DType -from tinygrad.uop.ops import UOp, Ops, UPat, PatternMatcher, resolve, graph_rewrite, GroupOp, identity_element -from tinygrad.codegen.symbolic import split_uop, uop_given_valid, parse_valid, simplify_valid, sym, symbolic_flat -from tinygrad.helpers import getenv, flatten, AMX, prod, partition -from tinygrad.codegen.transcendental import xexp2, xlog2, xsin, xpow, TRANSCENDENTAL_SUPPORTED_DTYPES -from tinygrad.renderer import Renderer - -# ***** image load valid simplification ***** - -def simplify_valid_load(buf:UOp, start_idx:UOp, valid:UOp) -> UOp|None: - if (idx:=uop_given_valid(valid, start_idx)) is None: return buf.const_like(0) - if not isinstance(buf.dtype, ImageDType): return None if idx is start_idx else buf.index(idx, valid) - - # wait for it to be image indexed before running simplification - if start_idx.dtype.count != 2: return None - - # can drop valid if idx is out of bound when valid is False - drop_stmt = [] - for stmt in split_uop(valid, Ops.AND): - try: X, is_upper_bound, c = parse_valid(stmt) - except ValueError: return None - - # for X0 + X1 + ... >= 1, check if it's out of bound when Xi = 0 for all i - if not is_upper_bound and c == 1 and all(u.op in GroupOp.Irreducible and u.vmin == 0 for u in split_uop(X, Ops.ADD)): - testidx = functools.reduce(lambda nowidx,u: nowidx.substitute({u:u.const_like(0)}), split_uop(X, Ops.ADD), idx) - testidx = testidx.simplify() - if testidx.gep(0).vmax < 0 or testidx.gep(1).vmax < 0: - drop_stmt.append(stmt) - continue - - # if X <= c, check if it's out of bound when X = c+1 - # if X >= c, check if it's out of bound when X = c-1 - test_value = c + 1 if is_upper_bound else c - 1 - for i,b in zip(idx.src, (buf.dtype.shape[1], buf.dtype.shape[0])): - if i.is_increasing(): - rw = i.substitute({X:X.const_like(test_value)}).simplify() - if rw.vmin >= b or rw.vmax < 0: - drop_stmt.append(stmt) - break - - if not drop_stmt and idx is start_idx: return None - new_valid = functools.reduce(operator.and_, ss) if (ss:=[s for s in split_uop(valid, Ops.AND) if s not in drop_stmt]) else None - return buf.index(idx, new_valid) - -def delete_redundant_gates(buf:UOp, idx:UOp, val:UOp, store_gate:UOp, cast:UOp|None=None) -> UOp|None: - if store_gate not in [gate.src[0] for gate in val.toposort() if gate.op is Ops.IF]: return None - # remove the gate from the index - return UOp.store(buf.index(idx).cast(cast.dtype) if cast is not None else buf.index(idx), val) - -load_store_indexing = PatternMatcher([ - # simplify valid - (UPat(Ops.AND, name="valid"), simplify_valid), - # image load valid idx simplification - (UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("start_idx"), UPat.var("valid"))), simplify_valid_load), - # index True is just Index - (UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("start_idx"), UPat(Ops.CONST, arg=True))), lambda buf,start_idx: buf.index(start_idx)), - # delete_redundant_gates (after expand) - (UPat(Ops.STORE, src=(UPat.any(stidx:=UPat.var("buf").index(UPat.var("idx"), UPat.var("store_gate")), stidx.cast().named("cast")), - UPat.var("val"))), delete_redundant_gates), -]) - -# ***** load/store grouping ***** - -def expand_index(buf:UOp, vec:UOp, mask:UOp|None=None): - if getenv("UNSAFE_DISABLE_MASK", 0): mask = None - # generate the individual indexes - midx = graph_rewrite(UOp.sink(*[buf.index(vec.gep(i), mask.gep(i) if mask is not None else None) for i in range(vec.dtype.count)]), - symbolic_flat+load_store_indexing, name=f"index_buf_{buf.arg}") - # extract all the relevant offsets - offsets_rootsrc: defaultdict[Any, dict[int, list[int]]] = defaultdict(dict) - for i in range(vec.dtype.count): - idx: Any = midx.src[i].src[1] - if idx.op is Ops.ADD and idx.src[1].op is Ops.CONST: root_src, arg = idx.src[0], idx.src[1].arg - elif idx.op is Ops.ADD and idx.src[0].op is Ops.CONST: root_src, arg = idx.src[1], idx.src[0].arg - elif idx.op is Ops.CONST: root_src, arg = "CONST", idx.arg - else: root_src, arg = idx, 0 - if len(midx.src[i].src) == 3: root_src = (midx.src[i].src[2], root_src) - offsets_rootsrc[root_src].setdefault(arg, []).append(i) - - # the buf.dtype is always a pointer - ptrdtype = cast(PtrDType, buf.dtype) - - # then rewrite everything we can into groups - ret = [] - idxs: list[int|None] = [None]*vec.dtype.count - global_offset = 0 - for offsets in offsets_rootsrc.values(): - grouped_offsets = [[x for _,x in group] for _,group in itertools.groupby(enumerate(sorted(offsets.keys())), lambda x: x[1]-x[0])] - for grp in grouped_offsets: - # get the index offset for this element. using [0] is okay, because they are the same - lidx = midx.src[offsets[grp[0]][0]] - if len(grp) > 1: lidx = lidx.cast(ptrdtype.base.vec(len(grp)).ptr(size=ptrdtype.size, local=ptrdtype.local)) - # set the idxs of the output - for i,g in enumerate(grp): - for oo in offsets[g]: idxs[oo] = global_offset+i - # add this lidx to the CAT - ret.append(lidx) - global_offset += len(grp) - assert None not in idxs, f"some idxs are missing {idxs}" - # this base thing is for image, we want the CAT to be a normal pointer - post_cat = UOp(Ops.PTRCAT, ptrdtype.base.ptr(size=ptrdtype.size, local=ptrdtype.local).vec(vec.dtype.count), tuple(ret)) - return post_cat.gep(tuple(cast(list[int], idxs))) - -def cat_after_store(cat:UOp, data:UOp): - # TODO: this is written in many places - offset = 0 - ret = [] - for s in cat.src: - ret.append(s.store(data.gep(tuple(range(offset, offset+s.dtype.count))))) - offset += s.dtype.count - return UOp.sink(ret[0], *ret[1:]) - -def gep_on_store(gep:UOp, st:UOp): - # NOTE: we need to invert the gep here, but it may be an expanding gep - # fake argsort. TODO: handle duplicates - a = {} - for i,x in enumerate(gep.arg): a[x] = i - new_arg = tuple(x[1] for x in sorted(a.items())) - return UOp(Ops.STORE, src=(gep.src[0], st.gep(new_arg))) - -load_store_folding = PatternMatcher([ - (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL), name="buf")), UPat.var("vec"))), expand_index), - (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL), name="buf")), UPat.var("vec"), - UPat.var("mask"))), expand_index), - # GEP after LOAD - (UPat(Ops.LOAD, src=(UPat(Ops.GEP, name="gep"),), name="ld", allow_any_len=True), - lambda gep, ld: ld.replace(dtype=ld.dtype.scalar().vec(gep.dtype.count), src=(gep.src[0],)+ld.src[1:]).gep(gep.arg)), - # GEP on data of STORE - (UPat(Ops.STORE, src=(UPat(Ops.GEP, name="gep"), UPat.var("st"))), gep_on_store), - # put PTRCAT after LOAD - (UPat(Ops.LOAD, src=(UPat(Ops.PTRCAT, name="cat"),), name="ld", allow_any_len=True), - lambda cat,ld: UOp(Ops.CAT, ld.dtype, tuple(ld.replace(dtype=x.dtype.base, src=(x,)+ld.src[1:]) for x in cat.src))), - # put PTRCAT after STORE - (UPat(Ops.STORE, src=(UPat(Ops.PTRCAT, name="cat"), UPat(name="data"))), cat_after_store), -]) - -# ***** optional patterns ***** - -@functools.lru_cache(None) -def magicgu(vmax:int, d:int) -> tuple[int,int]: - # calculate m,s such that x//d == (x*m) >> s for all 0 <= x <= vmax, d>0; adapted from Hacker's Delight, Chapter 10 - nc = (vmax+1)//(d) * d - 1 - nbits = vmax.bit_length() - for s in range(0, 2*nbits + 1): - if 2**s > nc*(d - 1 - (2**s - 1) % d): - m = (2**s + d - 1 - (2**s - 1) % d)//d - return m, s - assert False - -def fast_idiv(ctx: Renderer|None, x: UOp, d: int) -> UOp|None: - # idiv is truncated division, but arithmatic shift is floored division, so can only do non-negative numbers! - if x.vmin<0: return None - sign = 1 if d > 0 else -1 - m,s = magicgu(vmax := min(x.vmax, dtypes.max(x.dtype)), abs(d)) - if m * vmax <= dtypes.max(x.dtype): return sign * ((x*m) >> s) - # promo_lattice needs to return an unsigned type - if ctx is not None and dtypes.is_int(next_dtype := promo_lattice[x.dtype][-1]) and is_dtype_supported(next_dtype, ctx.device): - if m * vmax <= dtypes.max(next_dtype): return sign * ((x.cast(next_dtype)*m) >> s).cast(x.dtype) - return None - -powers_of_two = {2**i:i for i in range(64)} -@functools.cache -def get_late_rewrite_patterns(ops, force_transcendental=False): - pat: list[tuple[UPat, Callable]] = [(UPat(op, dtype=TRANSCENDENTAL_SUPPORTED_DTYPES, src=(UPat.var("d"),)), f) for op,f in \ - ((Ops.EXP2, xexp2), (Ops.LOG2, xlog2), (Ops.SIN, xsin)) if op not in ops or force_transcendental] - # rewrite SQRT to xpow 0.5 - if Ops.SQRT not in ops: pat.append((UPat(Ops.SQRT, src=UPat.var("d")), lambda d: xpow(d, d.const_like(0.5)))) - # rewrite MOD to AND (which should always be supported, but not for generic in tests): x % (2**y) -> x & (2**y-1) - if Ops.AND in ops: pat += [(UPat.var("x", dtypes.ints)%UPat.cvar("c"), lambda x,c: x & (c.arg-1) if c.arg in powers_of_two else None)] - # rewrite MUL/IDIV to SHL+SHR: x*(2**y) -> shl(x,y) and x//(2**y) -> shr(x,y) - if Ops.SHL in ops: pat += [(UPat.var("x", dtypes.ints)*UPat.cvar("c"), lambda c,x: x << v if (v:=powers_of_two.get(c.arg, 0)) else None)] - if Ops.SHR in ops: - # no reason to check x>=0 for uints - pat += [(UPat.var("x", dtypes.uints)//UPat.cvar("c"), lambda x,c: x >> v if (v:=powers_of_two.get(c.arg, 0)) else None)] - pat += [(UPat.var("x", dtypes.sints)//UPat.cvar("c"), lambda x,c: x >> v if (v:=powers_of_two.get(c.arg, 0)) and resolve(x>=0,False) else None)] - if not getenv("DISABLE_FAST_IDIV"): - pat += [(UPat.var("x", dtypes.ints)//UPat.cvar("d"), lambda ctx, x, d: fast_idiv(ctx, x, d.arg))] - pat += [(UPat.var("x", dtypes.ints)%UPat.cvar("d"), lambda ctx, x, d: x - d*f if (f:=fast_idiv(ctx, x, d.arg)) is not None else None)] - if Ops.NEG in ops: - pat += [(UPat.var('x')*-1, lambda x: x.alu(Ops.NEG))] - if Ops.SUB in ops: pat += [(UPat.var('x')+UPat.var('y').alu(Ops.NEG), lambda x,y: x.alu(Ops.SUB, y))] - if Ops.MULACC in ops: pat += [(UPat.var('a')*UPat.var('b')+UPat.var('c'), lambda a,b,c: a.alu(Ops.MULACC, b, c))] - return PatternMatcher(pat) - -# *** correct load/store *** - -def split_load_store(ctx:Renderer|None, ls:UOp, idx:UOp): - # this splits loads and stores into multiple chunks - - # if there's only one element to load/store, no splitting needed - if (sz:=ls.src[0].dtype.count) == 1: return None - buf = idx.src[0] - - # determine fold lengths - lengths = [] - must_divide = True - if ctx is not None and ctx.device == "DSP": - lengths = [128,64,32,16,8,4] - must_divide = False - elif buf.dtype.base != dtypes.float and buf.dtype.base != dtypes.half and not isinstance(buf.dtype, ImageDType): - pass - elif isinstance(buf.dtype, ImageDType): - lengths = [4] - elif ctx is not None and ctx.supports_float4: - # TODO: a better way to get this than ctx - lengths = [8,4,2] if buf.dtype.base == dtypes.half and getenv("ALLOW_HALF8") else ([16,8,4,2] if AMX else [4,2]) - lengths.append(1) # worst case, it's not folded - - # filter fold lengths that don't divide - if must_divide: lengths = [x for x in lengths if idx.src[1].divides(x) is not None] - - # split based on the fold lengths - global_offset = 0 - ret = [] - ptrdtype = cast(PtrDType, buf.dtype) - while global_offset < sz: - # with 1 at the end of the lengths list, this will always hit - for fold_length in lengths: - if global_offset+fold_length > sz: continue - lidx = buf.index(idx.src[1] + global_offset, idx.src[2] if len(idx.src) > 2 else None) - if fold_length > 1: lidx = lidx.cast(ptrdtype.base.vec(fold_length).ptr(size=ptrdtype.size, local=ptrdtype.local)) - if ls.op is Ops.STORE: ret.append(ls.replace(src=(lidx,ls.src[1].gep(tuple(range(global_offset, global_offset+fold_length))))+ls.src[2:])) - else: ret.append(ls.replace(src=(lidx,)+ls.src[1:], dtype=ls.dtype.scalar().vec(fold_length))) - global_offset += fold_length - break - - # if it wasn't split, we return None. otherwise we CAT them - return UOp(Ops.CAT, ls.dtype, tuple(ret)) if len(ret) > 1 else None - -def image_fixup(ls:UOp): - # normal image load or store, with the CAST from expand_index - if ls.src[0].op is Ops.CAST and isinstance(image_dtype:=ls.src[0].src[0].dtype, ImageDType): - assert ls.src[0].dtype.count == 4, "image must be casted to 4" - idx = ls.src[0].src[0] - oidx = UOp(Ops.VECTORIZE, dtypes.int.vec(2), ((idx.src[1] // 4) % image_dtype.shape[1], (idx.src[1] // (4*image_dtype.shape[1])))) - idx = idx.replace(src=(idx.src[0], oidx)+idx.src[2:]) - return ls.replace(src=(idx,)+ls.src[1:]) - - # this is an unprocessed image without a cast, aka unfoldable image load. this doesn't work for stores - if isinstance(image_dtype:=ls.src[0].dtype, ImageDType) and ls.src[0].src[1].dtype != dtypes.int.vec(2): - assert ls.op is Ops.LOAD, "if an image store isn't upcasted to 4, we can't store it" - idx = ls.src[0] - id4 = idx.src[1] % 4 - oidx = UOp(Ops.VECTORIZE, dtypes.int.vec(2), ((idx.src[1] // 4) % image_dtype.shape[1], (idx.src[1] // (4*image_dtype.shape[1])))) - idx = idx.replace(src=(idx.src[0], oidx)+idx.src[2:]) - vec_load = ls.replace(dtype=ls.dtype.vec(4), src=(idx,)+ls.src[1:]) - return functools.reduce(lambda ret, i: id4.ne(i).where(ret, vec_load.gep(i)), range(4), ls.const_like(float('nan'))) - - return None - -correct_load_store = PatternMatcher([ - # split LOAD/STORE - (UPat((Ops.LOAD, Ops.STORE), src=(UPat(Ops.INDEX, name="idx").cast(),), name="ls", allow_any_len=True), split_load_store), - # image indexing, including unfoldable images - (UPat((Ops.LOAD, Ops.STORE), name="ls"), image_fixup), -]) - -# *** uop expander *** - -# TODO: there's a lot shared with gep_through_wmma here -def no_vectorized_wmma(wmma:UOp): - out_sz = prod(x[1] for x in wmma.arg[6][-1]) - if wmma.dtype.count == out_sz: return None - tsrcs = [] - for s,sz in zip(wmma.src, wmma.arg[6]): - ssz = prod(x[1] for x in sz) - tsrcs.append([s.gep(tuple(range(grp, grp+ssz))) for grp in range(0, s.dtype.count, ssz)]) - wmmas = [UOp(Ops.WMMA, wmma.dtype.scalar().vec(out_sz), tsrc, wmma.arg) for tsrc in zip(*tsrcs)] - wmma_ex = flatten([[e.gep(i) for i in range(out_sz)] for e in wmmas]) - return UOp(Ops.VECTORIZE, wmma.dtype, tuple(wmma_ex)) - -def no_vectorized_alu(alu:UOp): - if alu.dtype.vcount == 1: return None - alus = tuple(UOp(alu.op, alu.dtype.scalar(), tuple(s.gep(i) for s in alu.src), alu.arg) for i in range(alu.dtype.vcount)) - return UOp(Ops.VECTORIZE, alu.dtype, alus) - -def no_vectorized_acc(acc:UOp): - if acc.dtype.count == 1: return None - alus = tuple(UOp(acc.op, acc.dtype.scalar(), - tuple(s.gep(i) if j == 0 else s for j,s in enumerate(acc.src)), acc.arg+(i,)) for i in range(acc.dtype.count)) - return UOp(Ops.VECTORIZE, acc.dtype, alus) - -devectorize = PatternMatcher([ - # no ALU on vectorized dtypes - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.ASSIGN), name="alu"), no_vectorized_alu), - (UPat(Ops.WMMA, name="wmma"), no_vectorized_wmma), - (UPat(Ops.DEFINE_ACC, name="acc"), no_vectorized_acc), -]) - -pm_render = PatternMatcher([ - # for rendering, we use explicit VECTORIZE - (UPat(Ops.CONST, name='c'), - lambda c: UOp(Ops.VECTORIZE, c.dtype, (UOp.const(c.dtype.scalar(), c.arg),)*c.dtype.vcount) if c.dtype.vcount > 1 else None), - (UPat(Ops.VCONST, name='c'), lambda c: UOp(Ops.VECTORIZE, c.dtype, tuple(UOp.const(c.dtype.scalar(), x) for x in c.arg))), - (UPat(Ops.GEP, name='gep'), lambda gep: UOp(Ops.VECTORIZE, gep.dtype, tuple(gep.src[0].gep(x) for x in gep.arg)) if len(gep.arg) > 1 else None), - (UPat(Ops.GEP, name='gep'), lambda gep: gep.src[0] if gep.src[0].dtype.vcount == 1 and gep.arg == (0,) else None), - (UPat(Ops.VECTORIZE, src=(UPat(name='x'),)), lambda x: x), - # give any loads that are masked an alt value - (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat(), UPat(), UPat())).or_casted(),), allow_any_len=True, name="x"), - lambda x: x.replace(src=(x.src[0], x.const_like(0))+x.src[1:]) if len(x.src) == 1 or x.src[1].op is Ops.CUSTOM else None), - # gate any stores that aren't gated with ifs - (UPat(Ops.STORE, dtype=dtypes.void, src=(UPat(src=(UPat(), UPat(), UPat(dtype=dtypes.bool)), name="idx").or_casted(), UPat()), name="store"), - lambda store,idx: UOp(Ops.STORE, src=store.src+(UOp(Ops.IF, src=(idx.src[2],)),))), -]) - -# *** Ops.REDUCE -> Ops.DEFINE_ACC+Ops.ASSIGN *** - -@dataclass -class ReduceContext: - acc_num: int = 0 - -def horizontal_reduce(inp:UOp, out_dtype:DType) -> list[UOp]: - # if this has a horizontal reduction component, do that first - if inp.dtype != out_dtype: - # NOTE: [0 1 2 3 4 5 6 7] -> [0+4, 1+5, 2+6, 3+7] - horizontal_amount = inp.dtype.count//out_dtype.count - return [inp.gep(tuple(range(i, inp.dtype.count, horizontal_amount))) for i in range(0, horizontal_amount)] - return [inp] - -def reduce_to_acc(ctx:ReduceContext, red:UOp): - inp, reduce_range = red.src[0], red.src[1:] - lst = horizontal_reduce(inp, red.dtype) - assert all(x.dtype == red.dtype for x in lst), f"horizontal reduction mismatch {lst[0].dtype} != {red.dtype}" - # if we have a range - if len(reduce_range) != 0: - acc = UOp(Ops.DEFINE_ACC, red.dtype, (red.const_like(identity_element(red.arg, red.dtype.scalar())),) + tuple(reduce_range), (ctx.acc_num,)) - lst = [acc] + lst # put acc as the first element - ctx.acc_num += 1 - ret = functools.reduce(lambda x,y: x.alu(red.arg, y), lst) - return acc.assign(ret) if len(reduce_range) != 0 else ret - -def no_vectorized_reduce(inp:UOp, red:UOp): - if inp.dtype != red.dtype: - red = red.replace(src=(functools.reduce(lambda x,y: x.alu(red.arg, y), horizontal_reduce(inp, red.dtype)),)+red.src[1:]) - if red.dtype.vcount == 1: return red - # no_vectorize_alu ignoring ranges - if red.dtype.vcount == 1: return None - alus = tuple(UOp(red.op, red.dtype.scalar(), (red.src[0].gep(i),)+red.src[1:], red.arg) for i in range(red.dtype.vcount)) - return UOp(Ops.VECTORIZE, red.dtype, alus) - -def reduce_rangeless(red:UOp): - # TODO: share code with reduce_unparented - if red.arg not in {Ops.ADD, Ops.MAX}: return None - if red.src[0].dtype != red.dtype: return None - if any(x.op in {Ops.RANGE} for x in red.src[0].toposort()): return None - ret = red.src[0] - if red.arg is Ops.ADD: - for r in red.src[1:]: - ret = ret * r.src[0].cast(ret.dtype.scalar()).broadcast(ret.dtype.count) - return ret - -def no_range(u:UOp) -> bool: return not any(x.op is Ops.RANGE for x in u.sparents) - -pm_reduce_collapse = PatternMatcher([ - # lift x+y out of reduce on lt - ((UPat.var("x")+UPat.var("y")) < UPat.var("c"), lambda x,y,c: (x < (c-y)) if no_range(y) and no_range(c) else None), - # lift x*y out of reduce - ((UPat.var("x")*UPat.var("y")) < UPat.var("c"), - lambda x,y,c: (x < ((c+y-1) // y)) if no_range(y) and no_range(c) and y.vmin > 0 else None), - # lift x+y out of reduce on ne - ((UPat.var("x")+UPat.var("y")) != UPat.var("c"), lambda x,y,c: (x != (c-y)) if no_range(y) and no_range(c) else None), - # fold the range - ((UPat(Ops.RANGE, name="r") < UPat.var("cut")).where(0, UPat.cvar("val")).reduce(arg=Ops.ADD, allow_any_len=True), - lambda r,cut,val: (r.src[0]-cut).maximum(0).minimum(r.src[0]).cast(val.dtype) * val), - ((UPat(Ops.RANGE, name="r") < UPat.var("cut")).where(UPat.cvar("val"), 0).reduce(arg=Ops.ADD, allow_any_len=True), - lambda r,cut,val: cut.maximum(0).minimum(r.src[0]).cast(val.dtype) * val), - # REDUCE on ADD - ((UPat.var("x")+UPat.var("y")).reduce(arg=Ops.ADD, allow_any_len=True, name="r"), - lambda x,y,r: x.reduce(*r.src[1:], arg=Ops.ADD) + y.reduce(*r.src[1:],arg=Ops.ADD)), - # MUL casted bool - ((UPat.var("x") * UPat.var("gate", dtype=dtypes.bool).cast().or_broadcasted(name="b")), - lambda x,gate,b=None: gate.broadcast(x.dtype.count).where(x, 0) if b is not None else gate.where(x, 0)), - # WHERE on LOAD (works on max too) - (UPat.var("gate").where(UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("idx"))).load(), 0).reduce(arg=Ops.ADD, allow_any_len=True), - lambda buf,idx,gate: buf.index(idx, gate).load()), - (UPat.var("gate").where(0, UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("idx"))).load()).reduce(arg=Ops.ADD, allow_any_len=True), - lambda buf,idx,gate: buf.index(idx, gate.logical_not()).load()), - # INDEX on RANGE / gated RANGE - (UPat.var("buf").index(UPat.var("expr"), UPat.var("idx").eq(UPat(Ops.RANGE, name="r").or_casted())), - lambda buf,r,idx,expr: buf.index(expr.substitute({r:idx.cast(r.dtype)}), (idx.cast(r.dtype) >= 0) & (idx.cast(r.dtype) < r.src[0]))), - # AND on WHERE - ((UPat.any(UPat(Ops.DEFINE_VAR, name="x"), UPat(Ops.DEFINE_VAR).gep(name="x")) & UPat.var("y")) \ - .where(UPat.cvar("c"), 0).reduce(arg=Ops.ADD, allow_any_len=True, name="r"), - lambda x,y,c,r: y.where(c, 0).reduce(*r.src[1:], arg=Ops.ADD)*x.cast(c.dtype)), - # remove REDUCEs that no longer have a RANGE in the src - (UPat(Ops.REDUCE, name="red"), reduce_rangeless), - # devectorize REDUCE - (UPat(Ops.VECTORIZE, name="inp").reduce(name="red", allow_any_len=True), no_vectorized_reduce), - # index/load/where. TODO: this is more aggressive than needed - (UPat((Ops.INDEX, Ops.LOAD, Ops.WHERE), name="alu"), no_vectorized_alu), -])+sym - -def reduce_collapse(red:UOp): - included, not_included = partition(red.parents, lambda x: any(y in x.sparents for y in red.src[1:])) - if any(x.op in {Ops.STORE, Ops.REDUCE} for x in included): return None - replaces: dict[UOp, UOp] = {} - for u in included: - for s in u.src: - if s in not_included and s not in replaces and s.op not in {Ops.CONST, Ops.VCONST, Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_VAR}: - replaces[s] = UOp(Ops.DEFINE_VAR, dtype=s.dtype, arg=(f'in{len(replaces)}', s.vmin, s.vmax)) - collapse_fxn = red.substitute(replaces) - sink = graph_rewrite(collapse_fxn, pm_reduce_collapse, name="reduce_collapse") - # TODO: why is REDUCE needed here and just RANGE isn't enough? - if any(x.op in {Ops.REDUCE, Ops.RANGE} for x in sink.toposort()): return None - return sink.substitute({v:k for k,v in replaces.items()}) - -def reduce_unparented(red:UOp): - if red.arg not in {Ops.ADD, Ops.MAX}: return None - reduce_parented, reduce_unparented = partition(red.src[1:], lambda x: x in red.src[0].sparents) - if len(reduce_unparented) == 0: return None - ret = red.replace(src=(red.src[0],)+tuple(reduce_parented)) if len(reduce_parented) or red.dtype != red.src[0].dtype else red.src[0] - if red.arg is Ops.ADD: - for r in reduce_unparented: ret = ret * r.src[0].cast(ret.dtype.scalar()).broadcast(ret.dtype.count) - return ret - -pm_reduce = PatternMatcher([ - # remove any ranges from a REDUCE that aren't referenced in the reduce source - (UPat(Ops.REDUCE, name="red"), reduce_unparented), - # remove REDUCE without loads (generic arange opt / indexing). TODO: support multi range - (UPat(Ops.REDUCE, src=(UPat(), UPat()), name="red"), reduce_collapse), - # REDUCE -> DEFINE_ACC+ASSIGN - (UPat(Ops.REDUCE, name="red"), reduce_to_acc), - # tensor core built in accumulate - (UPat(Ops.WMMA, name="wmma") + UPat.var("add"), - lambda add, wmma: UOp(wmma.op, wmma.dtype, (wmma.src[0], wmma.src[1], wmma.src[2]+add), wmma.arg)), -])+sym diff --git a/tinygrad/tinygrad/codegen/expander.py b/tinygrad/tinygrad/codegen/expander.py deleted file mode 100644 index be59b4cd..00000000 --- a/tinygrad/tinygrad/codegen/expander.py +++ /dev/null @@ -1,138 +0,0 @@ -# this converts a lowerer program into a vectorized program - -import functools, itertools, operator -from tinygrad.helpers import AMX, dedup, flatten, all_same, prod -from tinygrad.uop.ops import UOp, Ops, UPat, PatternMatcher, GroupOp - -def _expand_arg_to_idx(args:tuple[tuple[int, int], ...], rpk:dict[int, int]) -> int: - idx, mul = 0, 1 - for axis,m in args[::-1]: - idx += rpk[axis] * mul - mul *= m - return idx - -def _choices_from_args(args:tuple[tuple[int, int], ...]) -> list[dict[int, int]]: - return [dict(x) for x in itertools.product(*[zip(itertools.repeat(axis), range(m)) for axis,m in args])] - -@functools.cache -def _swizzle_args(cargs:tuple[tuple[int, int], ...], eargs:tuple[tuple[int, int], ...], exclude_args:tuple[int, ...]) -> list[int]: - return [_expand_arg_to_idx(eargs, {**rpk, **{x:0 for x in exclude_args}} if exclude_args else rpk) for rpk in _choices_from_args(cargs)] - -def do_expand(root:UOp): - expands = [x for x in root.src if x.op is Ops.UNROLL] - if len(expands) == 0: return None - # NOTE: we 0 out the reduce axis for WMMA. in theory they should all be the same, but is this always correct? - exclude_args = tuple(dedup(root.arg[-1] + tuple(y[0] for y in flatten(root.arg[-2])))) if root.op is Ops.WMMA else () - if all_same(expands_args:=[x.arg for x in expands]) and len(exclude_args) == 0: - # if there's only one expand arg, it's okay to use it (optimization) - expand_args = expands[0].arg - else: - # otherwise, we sort them and GEP - expand_args = tuple(x for x in sorted(dedup(flatten(expands_args))) if x[0] not in exclude_args) - expand_sz = prod([x[1] for x in expand_args]) - new_srcs = [] - for i,src in enumerate(root.src): - if src.op is Ops.UNROLL: - if root.op is Ops.IF and i == 0: - # IF means OR on first arg to IF - new_srcs.append(functools.reduce(operator.__or__, [src.src[0].gep(i) for i in range(expand_sz)])) - elif expand_args == src.arg: - # just remove the expand - new_srcs.append(src.src[0]) - else: - lst = _swizzle_args(expand_args, src.arg, exclude_args) - # if the base dtype is > 1, put those at the end - if src.dtype.count > 1: lst = flatten([[i*src.dtype.count+j for j in range(src.dtype.count)] for i in lst]) - new_srcs.append(src.src[0].gep(tuple(lst))) - else: - # non-UNROLL input - if root.op is Ops.IF: - # for the first arg of IF, just pass them through ignoring UNROLLS - new_srcs.append(src) - elif root.op is Ops.REDUCE and src.op is Ops.RANGE: - # for any range args of REDUCE, pass them through - new_srcs.append(src) - elif src.dtype.count > 1: - # put any input dtype > 1 grouped together - new_srcs.append(UOp(Ops.CAT, src.dtype.scalar().vec(expand_sz*src.dtype.count), (src,)*expand_sz)) - else: - # repeat the arg - new_srcs.append(src.broadcast(expand_sz)) - - new_arg = root.arg - if root.op is Ops.GEP: - assert root.dtype.count == 1 - # is this right? - new_arg = tuple(range(root.arg[0], new_srcs[0].dtype.count, new_srcs[0].dtype.count // expand_sz)) - nsrc = UOp(root.op, root.dtype.scalar().vec(root.dtype.count*expand_sz), tuple(new_srcs), new_arg) - return UOp(Ops.UNROLL, root.dtype, (nsrc,), expand_args) - -def do_contract(con:UOp): - ex = con.src[0] - # CONTRACT without UNROLL repeats the element VECTORIZED - if ex.op is not Ops.UNROLL: return UOp(Ops.VECTORIZE, con.dtype, con.src*con.dtype.count) - # CONTRACT may remove several axes from UNROLL - assert con.dtype.count == prod([x[1] for x in con.arg]), "dtype is wrong" - idxs = [] - for rpk in _choices_from_args(new_ex_args:=tuple(x for x in ex.arg if x not in con.arg)): - idxs += [_expand_arg_to_idx(ex.arg, {**rpk, **lrpk}) for lrpk in _choices_from_args(con.arg)] - return UOp(Ops.UNROLL, con.dtype, (ex.src[0].gep(tuple(idxs)),), new_ex_args) - -expander = PatternMatcher([ - # double expand - (UPat(Ops.UNROLL, name="outer", src=(UPat(Ops.UNROLL, name="inner"),)), - lambda outer, inner: UOp(Ops.UNROLL, outer.dtype, (inner.src[0],), inner.arg+outer.arg)), - # do expansion - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.GEP, Ops.WMMA, Ops.LOAD, Ops.STORE, Ops.INDEX, Ops.ASSIGN, - Ops.VECTORIZE, Ops.IF, Ops.REDUCE), name="root", custom_early_reject=set([Ops.UNROLL])), do_expand), - (UPat(Ops.CONTRACT, name="con"), do_contract), - # vectorize DEFINE_ACC - (UPat(Ops.VECTORIZE, src=UPat(Ops.DEFINE_ACC, name="acc"), name="v"), - lambda acc,v: acc.replace(dtype=v.dtype, src=(acc.src[0].broadcast(v.dtype.count),)+acc.src[1:])), - # BARRIERs aren't actually expanded - (UPat(Ops.BARRIER, src=(UPat(Ops.UNROLL, name="ex"),)), - lambda ex: UOp(Ops.UNROLL, src=(UOp(Ops.BARRIER, src=ex.src),)*len(ex.src), arg=ex.arg)), - # empty UNROLL is NOOP - (UPat(Ops.UNROLL, src=(UPat.var('x'),), arg=()), lambda x: x), - # UNROLL GEP (needed for WMMA, generalize this) -> vectorized ALU - (UPat(Ops.UNROLL, name="ex", src=tuple(UPat.var('x').gep(i)+UPat.var('y').gep(i) for i in range(256 if AMX else 8))), - lambda ex,x,y: UOp(Ops.UNROLL, ex.dtype, tuple((x+y).gep(i) for i in range(256 if AMX else 8)), ex.arg)), -]) - -def create_gate(root:UOp) -> UOp|None: - @functools.cache - def _gate_srcs(u:UOp, gate:UOp) -> UOp: - if u.op is Ops.BARRIER: return u - if u.op is Ops.LOAD and u.src[-1].op is Ops.BARRIER: - return UOp(u.op, u.dtype, u.src[:-1]+(UOp(Ops.IF, src=(gate, u.src[-1])),), arg=u.arg) - return u if (replace_source:=tuple(_gate_srcs(x, gate) for x in u.src)) == u.src else UOp(u.op, u.dtype, replace_source, u.arg) - idx = root.src[0] - if idx.op is Ops.CAST: idx = idx.src[0] - return None if idx.op is not Ops.INDEX or len(idx.src) == 2 or (ret:=_gate_srcs(root, idx.src[2])) is root else ret - -migrate_indexing = PatternMatcher([ - # create gate MUST BE BEFORE expander - (UPat(Ops.STORE, name="root"), create_gate), -]) - -# **** IGNORE support **** - -pm_store_ignore = PatternMatcher([ - (UPat().index(UPat(), UPat(name="mask")).store(UPat()).named("store"), - lambda store,mask: store.replace(src=(store.src[0], UOp(Ops.IGNORE, src=(store.src[1], mask)))) if store.src[1].op is not Ops.IGNORE else None), -]) - -pm_move_ignore = PatternMatcher([ - # IGNORE on SELF is nothing - (UPat(Ops.IGNORE, src=(UPat(name="x"), UPat(name="x"))), lambda x: x.const_like(True)), - # IGNORE on a CONST is nothing - (UPat(Ops.IGNORE, src=(UPat((Ops.CONST, Ops.VCONST), name="c"), UPat())), lambda c: c), - # move the IGNOREs - (UPat(Ops.IGNORE, src=(UPat((*GroupOp.ALU, Ops.CAST, Ops.VECTORIZE), name="alu"), UPat.var("mask")), name="ig"), - lambda ig,alu,mask: alu.replace(src=tuple(UOp(Ops.IGNORE, x.dtype, (x, mask)) for x in alu.src))), -]) - -pm_delete_ignore = PatternMatcher([ - # IGNORE on SELF is nothing - (UPat(Ops.IGNORE, src=(UPat(name="x"), UPat())), lambda x: x), -]) diff --git a/tinygrad/tinygrad/codegen/heuristic.py b/tinygrad/tinygrad/codegen/heuristic.py deleted file mode 100644 index 1f773390..00000000 --- a/tinygrad/tinygrad/codegen/heuristic.py +++ /dev/null @@ -1,133 +0,0 @@ -import itertools -from tinygrad.codegen.kernel import Kernel, Opt, OptOps, KernelOptError -from tinygrad.helpers import getenv, DEBUG, all_int, prod -from tinygrad.dtype import ImageDType -from tinygrad.uop.ops import Ops, resolve - -def hand_coded_optimizations(k:Kernel) -> list[Opt]: - # make a copy so it does not mutate the input - k = k.copy() - - # should use matvec - TODO: adjust/tune based on the wide vs tall/large vs small mat - MV_BLOCKSIZE, MV_THREADS_PER_ROW, MV_ROWS_PER_THREAD = getenv("MV_BLOCKSIZE", 4), getenv("MV_THREADS_PER_ROW", 8), getenv("MV_ROWS_PER_THREAD", 4) - if k.opts.has_local and getenv("MV",1) != 0 and (MV_BLOCKSIZE > 1 or MV_THREADS_PER_ROW > 1 or MV_ROWS_PER_THREAD > 1) and \ - k.reduceop is not None and k.reduceop.arg[0] is Ops.ADD and len(k.full_shape) >= 2 and k.opts.has_shared and \ - (mulop:=k.reduceop.src[0]).op is Ops.MUL and mulop.src[0].op is Ops.LOAD and mulop.src[1].op is Ops.LOAD: - st0, st1 = k.sts[k.bufs.index(mulop.src[0])], k.sts[k.bufs.index(mulop.src[1])] - strides0, strides1 = st0.real_strides(), st1.real_strides() - def has_expanded_axis(shape, strides): return any(resolve(s > 1) and not resolve(st != 0) for s,st in zip(shape,strides)) - if strides0[k.first_reduce] == 1 and not (has_expanded_axis(st0.shape, strides0) and has_expanded_axis(st1.shape, strides1)): - for global_idx in range(k.global_dims): - if k.full_shape[k.first_reduce]%MV_THREADS_PER_ROW == 0 and k.full_shape[global_idx]%(MV_BLOCKSIZE*MV_ROWS_PER_THREAD) == 0: - if DEBUG >= 3: - print(f"MATVEC: {k.full_shape=} {k.first_reduce=} {strides0=} {MV_BLOCKSIZE=} {MV_THREADS_PER_ROW=} {MV_ROWS_PER_THREAD=}") - if MV_THREADS_PER_ROW > 1: k.apply_opt(Opt(OptOps.GROUP, 0, MV_THREADS_PER_ROW)) - if MV_BLOCKSIZE > 1: k.apply_opt(Opt(OptOps.LOCAL, global_idx, MV_BLOCKSIZE)) - if MV_ROWS_PER_THREAD > 1: k.apply_opt(Opt(OptOps.UPCAST, global_idx, MV_ROWS_PER_THREAD)) - return k.applied_opts - - if k.opts.has_local and k.opts.has_shared and all_int(k.sts[0].shape[:k.first_reduce]): - # are we grouping? (requires local shape support) - if not [x for x in k.sts[0].unit_stride_axes() if x >= k.first_upcast and k.sts[0].shape[x]%4 == 0] and \ - k.first_reduce <= 2 and k.first_reduce < k.shape_len and prod(k.sts[0].shape[:k.first_reduce]) <= 2048: - # TODO: use 1024 if it's allowed in a smarter way - for sz in ([256, 16] if prod(k.sts[0].shape[:k.first_reduce]) <= 32 else [16]): - if all(st.shape[k.first_reduce] % sz == 0 or st.shape[k.first_reduce] == 1 for st in k.sts): - try: # may fail due to excessive smem usage - k.apply_opt(Opt(OptOps.GROUPTOP, 0, sz)) - break - except KernelOptError: pass - - # upcast float4 images - for buf_index,buf in enumerate(k.bufs): - unit_stride_axes_mul_4 = [i for i in k.sts[buf_index].unit_stride_axes(ignore_valid=True) if k.sts[buf_index].shape[i]%4 == 0] - if buf.src[0].dtype.__class__ is ImageDType: - #assert len(unit_stride_axes_mul_4) >= 1, f"needs a unit stride axis in {k.bufs[buf_index]}" - if len(unit_stride_axes_mul_4) and all(x < k.first_upcast for x in unit_stride_axes_mul_4): - if unit_stride_axes_mul_4[0] < k.first_reduce: - k.apply_opt(Opt(OptOps.UPCAST, unit_stride_axes_mul_4[0], 4)) - else: - k.apply_opt(Opt(OptOps.UNROLL, unit_stride_axes_mul_4[0]-k.first_reduce, 4)) - - # no more opt if we are grouping - if k.group_for_reduces: return k.applied_opts - - # **** below this line need to be optional and benchmarked **** - - # TODO: doing extra upcasts with images doesn't work for some reason (maybe has to do with to_image_idx) - # to trigger the above bug, remove prod(k.full_shape[k.first_upcast:]) from the below - # expression and run test/test_ops.py with IMAGE=2 - # if there are small dims with lots of valid masks, upcast them (they might be from Tensor.stack) - # this can be made much smarter - to_upcast: list[int] = [] - # upcast leading axes first (hack-ish for winograd; we actually want to upcast masked axes with low stride first) - for axis in range(k.first_reduce): - # we might want to be able to split axes that are masked, or refuse to merge them in simplify_merge_adjacent - # for now skip upcasting here if there is a symbolic axis - if isinstance(k.full_shape[axis], int) and k.full_shape[axis] <= 7 and any(st.axis_is_masked(axis) for st in k.sts) and \ - prod(k.full_shape[k.first_upcast:]) * prod(k.full_shape[j] for j in to_upcast) * k.full_shape[axis] <= 7 * 7: - if DEBUG >= 4: print(f"upcasting masked axis : {axis}") - to_upcast.append(axis) - for axis in to_upcast[::-1]: k.apply_opt(Opt(OptOps.UPCAST, axis, 0)) - - # potentially do more upcasts of non reduce axes based on a heuristic - is_dsp = k.opts is not None and k.opts.device == "DSP" - upcasted_axis: set[int] = set() - while resolve(prod(k.sts[0].shape[:k.first_reduce]) >= 1024): - xb_choices = [] - # consider all the non reduce axes, and a 3 or 4 reduce. (128 on the DSP) - for axis, upcast_amount in itertools.product(range(k.first_reduce), ([128] if not len(upcasted_axis) else []) if is_dsp else [3,4]): - # if we haven't upcasted it, it's not symbolic, it mods, and buffer has stride 0 on axis while having no stride 0 in the upcasted axis already - if axis not in upcasted_axis and isinstance(k.full_shape[axis], int) and k.full_shape[axis]%upcast_amount == 0 and \ - any(st.views[-1].strides[axis] == 0 and not any(x[1] == 0 for x in k.upcasted_axis(buf_index)) for buf_index, st in enumerate(k.sts)): - xb_choices.append((sum(st.views[-1].strides[axis]>0 for st in k.sts), - sum(st.views[-1].strides[axis] for st in k.sts), axis, upcast_amount)) - if xb_choices: - xb_choices = sorted(xb_choices) - if DEBUG >= 4: print(f"float4 merging axis : {xb_choices}") - k.apply_opt(Opt(OptOps.UPCAST, xb_choices[0][2], xb_choices[0][3])) - upcasted_axis.add(xb_choices[0][2]) - else: break - - # if last dim is small(ish) and it's a reduce dim, upcast the reduce (loop unrolling). no simplify needed since it's just an upcast. - if k.first_reduce < k.first_upcast and (prod(k.full_shape[k.first_upcast:]) <= 4 or \ - not any(x!=y for x,y in zip(k.sts[0].shape[k.first_upcast:], k.full_shape[k.first_upcast:]))) and \ - (k.upcasted == 0 or prod(k.full_shape[-k.upcasted:]) < 64): - if isinstance(s:=k.full_unupcasted_shape[-1], int) and s <= 32: # NOTE: cannot loop unroll symbolic axis - k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, 0)) - # if it's small, upcast a second reduce dimension too - if k.first_reduce < k.first_upcast and s <= 3 and isinstance(s2:=k.full_unupcasted_shape[-1], int) and s2 <= 3: - k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, 0)) - else: - for splits in [4]: - if k.full_unupcasted_shape[-1]%splits == 0: - k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, splits)) - break - - # if nothing at all is upcasted and it's easy to, do an upcast - for splits in [4]: - if k.upcasted == 0 and k.full_unupcasted_shape and k.full_unupcasted_shape[-1] % splits == 0: - k.apply_opt(Opt(OptOps.UPCAST, len(k.full_unupcasted_shape)-1, splits)) - - # **** local groups **** - - if k.opts.has_local: - if getenv("NOLOCALS") and k.local_dims == 0 and not k.group_for_reduces: - k.apply_opt(Opt(OptOps.NOLOCALS)) - else: - # prioritize making expand axes local - local_axis_ranking = [(any(k.sts[buf_index].views[-1].strides[axis] == 0 for buf_index in range(len(k.sts))), axis) \ - for axis in range(len(k.full_shape[:k.first_reduce]))] - to_local: list[tuple[int, int]] = [] - for _, axis in sorted(local_axis_ranking, key=lambda x: (-x[0], -x[1])): - local_size = prod(sz for _, sz in to_local) - local_sz: int|None = next((x for x in ([32] * (axis == 0) + [16,8,4,3,2]) if k.full_shape[axis] % x == 0 and local_size * x <= 128), None) - if local_sz is not None: to_local.append((axis, local_sz)) - deleted_shape = 0 - for axis, local_sz in sorted(to_local[:3]): - axis = axis - deleted_shape - will_delete_shape = local_sz == k.full_shape[axis] - k.apply_opt(Opt(OptOps.LOCAL, axis, local_sz)) - if will_delete_shape: deleted_shape += 1 - - return k.applied_opts \ No newline at end of file diff --git a/tinygrad/tinygrad/codegen/kernel.py b/tinygrad/tinygrad/codegen/kernel.py deleted file mode 100644 index 44457950..00000000 --- a/tinygrad/tinygrad/codegen/kernel.py +++ /dev/null @@ -1,575 +0,0 @@ -from __future__ import annotations -import itertools, functools, math -from dataclasses import dataclass -from collections import defaultdict -from typing import Optional, cast, Final, Callable, Sequence - -from tinygrad.uop.ops import GroupOp, KernelInfo, UOp, Ops, can_pad, resolve, Variable, sint, graph_rewrite, track_rewrites, print_uops -from tinygrad.uop.ops import PatternMatcher, smax -from tinygrad.uop.spec import type_verify, ast_spec -from tinygrad.device import Device -from tinygrad.renderer import Renderer, TensorCore, ProgramSpec, Opt, OptOps -from tinygrad.dtype import ImageDType -from tinygrad.helpers import all_same, colored, ansilen, dedup, getenv, prod, round_up, all_int, to_function_name, unwrap -from tinygrad.helpers import DEBUG, TC_SELECT, TC_OPT, AMX -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import strides_for_shape -from tinygrad.codegen.lowerer import get_contraction -from tinygrad.engine.grouper import view_left -from tinygrad.codegen import full_rewrite - -class KernelOptError(Exception): pass - -def check(cond:bool, msg:str=""): - if not cond: raise KernelOptError(msg) - -@dataclass -class TensorCoreOptions: - axes: tuple[int, ...] # the location of the original N and M axes if still in the shape - axes_exist: tuple[bool, ...] # true if the original N and M axes are still in the shape - axis_pads: tuple[tuple[int, int], ...] - def fix_axes(self, removed_axis:int): # adjust the TC axes if necessary when a dimension is removed - axes, axes_exist = list(self.axes), list(self.axes_exist) - for tc_dim in [i for i in range(2) if axes_exist[i]]: - if removed_axis < axes[tc_dim]: axes[tc_dim] -= 1 - elif removed_axis == axes[tc_dim]: axes_exist[tc_dim] = False - self.axes, self.axes_exist = tuple(axes), tuple(axes_exist) - -class Kernel: - def __init__(self, ast:UOp, opts:Optional[Renderer]=None): - assert ast.op is Ops.SINK, ast.op - self.ast = ast - - self.opts = opts if opts is not None else Device[Device.DEFAULT].renderer - # verify AST matches the spec - if __debug__: type_verify(list(self.ast.toposort()), ast_spec) - - self.reduceops = [x for x in self.ast.toposort() if x.op is Ops.REDUCE_AXIS] - - self.vars: list[Variable] = self.ast.variables() - # NOTE: this requires a specific order with the [::-1], this is likely a bug - self.bufs: list[UOp] = [x for x in self.ast.toposort() if x.op in GroupOp.Buffer][::-1] - - # create new shapetrackers inside this kernel, we will permute them - self.sts: list[ShapeTracker] = [x.st_arg for x in self.bufs] - - # add the shapetrackers for each reduce - # we use this to track which axes are reduced in each reduce - for x in self.reduceops: - self.sts.append(unwrap(x.st)) - self.sts.append(unwrap(x.src[0].st)) - - # add a shapetracker to the end to track the full shape, with 0 strides so it can merge - self.sts.append(ShapeTracker.from_shape(tuple([smax(*s) for s in zip(*[x.shape for x in self.sts])]), (0,)*self.shape_len)) - - # move all reduce axes to the end - reduce = list(enumerate(zip(self.full_shape, self.output_shape))) - permute = tuple([i for i,(s,n) in reduce if not resolve(s != n)] + [i for i,(s,n) in reduce if resolve(s != n)]) - self.reshape_and_permute(None, permute) - - # parameters for optimization - self.applied_opts: list[Opt] = [] - self.group_for_reduces: int = 0 - self.upcasted: int = 0 - self.local_dims: int = 0 - self.tensor_core: Optional[TensorCore] = None - self.tensor_core_opts: Optional[TensorCoreOptions] = None - self.use_tensor_cores: int = 0 - self.dont_use_locals: bool = False - - # group simplifies - self.simplify_ones() - self.simplify_merge_adjacent() - - def copy(self): - ret = type(self).__new__(type(self)) - - # base linearizer params - ret.opts, ret.ast = self.opts, self.ast - - # things downstream of the AST - ret.reduceops, ret.vars, ret.bufs = self.reduceops, self.vars, self.bufs - ret.sts = self.sts[:] - - # parameters for optimizations - ret.applied_opts, ret.group_for_reduces, ret.upcasted, ret.local_dims, ret.dont_use_locals = \ - self.applied_opts[:], self.group_for_reduces, self.upcasted, self.local_dims, self.dont_use_locals - ret.tensor_core, ret.tensor_core_opts, ret.use_tensor_cores = self.tensor_core, self.tensor_core_opts, self.use_tensor_cores - - return ret - - @property - def membufs(self) -> list[UOp]: return dedup([x.src[0].base for x in self.bufs if x.op in {Ops.LOAD, Ops.STORE}]) - - def upcasted_axis(self, i:int) -> list[tuple[int, Optional[sint], bool]]: - upcasted_shape, upcasted_stride = self.sts[i].shape[self.first_upcast:], self.sts[i].real_strides()[self.first_upcast:] - assert all_int(upcasted_shape), f"cannot upcast a symbolic amount {upcasted_shape=}" - return list(zip(upcasted_shape, upcasted_stride, - [x!=y for x,y in zip(self.sts[0].shape[self.first_upcast:], self.full_shape[self.first_upcast:])])) - - @property - def first_reduce(self) -> int: - return [resolve(x!=y) for x,y in zip(self.sts[0].shape[:self.first_upcast]+(0,), self.full_shape[:self.first_upcast]+(1,))].index(True) - - @property - def first_upcast(self) -> int: return self.shape_len-self.upcasted - - @property - def reduceop(self) -> UOp|None: return self.reduceops[0] if len(self.reduceops) > 0 else None - - @property - def output_shape(self) -> tuple[sint, ...]: return self.sts[0].shape - - @property - def full_shape(self) -> tuple[sint, ...]: return self.sts[-1].shape - - @property - def full_unupcasted_shape(self) -> tuple[sint, ...]: return self.full_shape[:self.first_upcast] - - @property - def shape_len(self) -> int: return len(self.sts[0].shape) - - @property - def global_dims(self) -> int: return self.first_reduce-self.local_dims - - # there's eight chunks of the shape - # blue -- global dims - # cyan -- local dims (warp ones first) - # *** self.first_reduce - # green -- reduce-local dims - # red -- reduce loops - # *** self.upcasted - # purple -- reduce upcasted - # yellow -- normal upcasted dimensions - def colors(self) -> list[str]: - # first non local non reduce dims are global (blue) - colors = ["blue"] * self.global_dims if not self.dont_use_locals else ["BLUE"] * self.global_dims - # after global are local_dims; warp ones used in tensor cores must be closest to first_reduce (cyan) - colors += ["cyan"] * self.local_dims - # between first_reduce and first_reduce + group_for_reduces, they are late upcasted (green) - colors += ["green"] * self.group_for_reduces - # between first_reduce + group_for_reduces and upcasted, they are reduce (red) - colors += ["red"] * (self.first_upcast - (self.first_reduce + self.group_for_reduces)) - # upcasted dimensions are reduce (magenta) or normal (yellow) - colors += ["magenta" if self.full_shape[i] != self.sts[0].shape[i] else "yellow" for i in range(self.first_upcast, self.shape_len)] - assert len(colors) == self.shape_len, "colors size mismatch" - return colors - - def colored_shape(self, pad:Optional[int]=None, dense=False) -> str: - shape_strs = [(s if dense else f"{s:4d}") if isinstance(s, int) else s.render() for s in self.full_shape] - ret = ' '.join(colored(s, color) for s,color in zip(shape_strs, self.colors())) - if pad: ret += ' '*(pad-ansilen(ret)) - return ret - - # ******************** base simplifiers ******************** - - # apply reshape and permute to all shapetrackers - def reshape_and_permute(self, new_shape_fxn:Optional[Callable[[tuple[sint, ...]], Sequence[sint]]], axis:Optional[Sequence[int]]): - def reshape(st:ShapeTracker): return st.reshape(tuple(new_shape_fxn(st.shape))) if new_shape_fxn is not None else st - def permute(st:ShapeTracker): return st.permute(tuple(axis)) if axis is not None else st - self.sts = [permute(reshape(st)) for st in self.sts] - - # drops the final dimension - def upcast(self): - check(self.full_shape[-1] != 1, "can't upcast a dimension with size 1") - self.upcasted += 1 - - # axis : the axis to pull from - # amount : the amount to take - # top : if you want to pull that amount from the top - # insert_before : place to insert the new stuff - def shift_to(self, axis, amount, top=False, insert_before=None): - if insert_before is None: insert_before = self.shape_len - move_axis = axis if top else axis+1 - if move_axis < insert_before: insert_before += 1 - self.reshape_and_permute( - lambda x: x[0:axis] + (((amount, x[axis]//amount) if top else (x[axis]//amount, amount)) if x[axis] > 1 else (1,1)) + x[axis+1:], - [i for i in range(insert_before) if i != move_axis] + [move_axis] + [i for i in range(insert_before, self.shape_len+1) if i != move_axis]) - - # ******************** complex simplifiers ******************** - - def simplify_ones(self) -> bool: - # remove places where the shape is all ones - # TODO: this should be factored in to multi shape stride - if self.shape_len == 0: return False - all_ones = [s==1 for s in self.full_shape] - self.local_dims -= sum(all_ones[self.first_reduce-self.local_dims:self.first_reduce]) - self.upcasted -= sum(all_ones[self.first_upcast:]) # TODO: no necessary since upcasted axis can't be un-upcasted - self.reshape_and_permute(lambda shape: [x for i,x in enumerate(shape) if not all_ones[i]], None) - return any(all_ones) - - def simplify_merge_adjacent(self): - if self.shape_len == 0: return - shapes, strides = [x.shape for x in self.sts], [x.real_strides() for x in self.sts] - - # if it's an image, insert fake strides such that this fusion doesn't happen across image axes - if isinstance(self.membufs[0].dtype, ImageDType): - base_shape = self.membufs[0].dtype.shape - if shape_idx_groups := get_contraction(self.output_shape, base_shape): - special_strides: tuple[sint, ...] = tuple() - for i,g in enumerate(shape_idx_groups): - shape_piece = tuple(self.output_shape[x] for x in g) - assert prod(shape_piece) == base_shape[i], f"get_contraction was wrong? {shape_piece} != {base_shape[i]}" - special_strides += strides_for_shape(shape_piece) - # adding the fake image shape - shapes.append(self.output_shape) - strides.append(special_strides) - - # merge dimensions if we can, multi _merge_dims - # NOTE: this does not always preserve the reduce dimension - # TODO: move this into shapetracker, with tests! - # TODO: how does this work with multi-reduce? - rets = [[(s[0], st[0])] for s,st in zip(shapes, strides)] - for i in range(1, len(shapes[0])): - can_merge = [] - for s,st,ret in zip(shapes, strides, rets): - # TODO: added the always mergeability of 1s, is this right? if so, add to shapetracker in the 1 case - si, sti, last_st = s[i], st[i], ret[-1][1] - can_merge.append((sti is not None) and ((sti != 0 and last_st == si*sti) or (sti == 0 and last_st == 0))) - # more can merge than this - mergeable = all(can_merge) and i != self.first_reduce - for j,(s,st) in enumerate(zip(shapes, strides)): - if mergeable: rets[j][-1] = (rets[j][-1][0] * s[i], st[i]) - else: rets[j].append((s[i], st[i])) - - # do the reshapes - for i,x in enumerate(rets[:len(self.sts)]): self.sts[i] = self.sts[i].reshape(tuple([y[0] for y in x])) - - # ******************** high level optimizers ******************** - - def _create_tc_opts(self, reduceop:UOp, tc:TensorCore, axis:int, opt_level:int) -> Optional[TensorCoreOptions]: - has_cast = tc.dtype_in != tc.dtype_out - if has_cast and not (reduceop.src[0].op is Ops.CAST and reduceop.src[0].dtype == tc.dtype_out): return None - - mul_op = reduceop.src[0].src[0] if has_cast else reduceop.src[0] - if mul_op.op is not Ops.MUL: return None - - def buf_index(src:UOp) -> Optional[int]: - # TODO: apply tc even if the sources are not from LOAD - if src.op is Ops.LOAD and src.dtype == tc.dtype_in: return self.bufs.index(src) - try: - if opt_level >= 1 and src.op is Ops.CAST and src.dtype == tc.dtype_in: return self.bufs.index(src.src[0]) - except ValueError: return None - return None - if (buf0:=buf_index(mul_op.src[0])) is None or (buf1:=buf_index(mul_op.src[1])) is None: return None - - buf0_strides, buf1_strides = self.sts[buf0].real_strides(), self.sts[buf1].real_strides() - axis_buf0 = [(i,self.full_shape[i],buf1_strides[i]) for i,s in enumerate(buf0_strides[:self.first_reduce]) if s == 0] - axis_buf1 = [(i,self.full_shape[i],buf0_strides[i]) for i,s in enumerate(buf1_strides[:self.first_reduce]) if s == 0] - if not (axis_buf0 and axis_buf1 and ((self.shape_len-self.first_reduce) == 1 or (opt_level >= 1))): return None - - axis_choices = list(itertools.product(axis_buf0, axis_buf1, range(self.first_reduce, self.shape_len))) - if not (axis < len(axis_choices)): return None - - s0, s1, s2 = axis_choices[-(axis+1)][0][0], axis_choices[-(axis+1)][1][0], axis_choices[-(axis+1)][2] # s0 is n, s1 is m, s2 is k - axis_pads = tuple((x, tc.dims[i]) for i, x in enumerate([s0, s1, s2]) if resolve(self.full_shape[x]%tc.dims[i] != 0)) - if axis_pads and (opt_level < 2): return None - if DEBUG >= 3: print("TENSOR CORES", axis_buf0, axis_buf1, tc) - return TensorCoreOptions(axes=(s0, s1, s2), axes_exist=(True, True), axis_pads=axis_pads) - - def _apply_tc_opt(self, use_tensor_cores:int, axis:int, tc_select:int, opt_level:int) -> bool: - if use_tensor_cores and self.reduceop is not None and self.reduceop.arg[0] is Ops.ADD: - tensor_cores = self.opts.tensor_cores if tc_select == -1 else [self.opts.tensor_cores[tc_select]] - for tc in tensor_cores: - tensor_core_opts = [self._create_tc_opts(reduceop, tc, axis, opt_level) for reduceop in self.reduceops] - # can only fuse reduces with the same tc options - assert all_same(tensor_core_opts) - if tensor_core_opts[0] is None: continue - self.tensor_core_opts = tc_opts = tensor_core_opts[0] - - # attempt to pad the tensor axes that require it - try: - for axis, dim in tc_opts.axis_pads: self.apply_opt(Opt(OptOps.PADTO, axis, dim), append_opt=False) # PADTO might fail - except KernelOptError: continue - # tensor core -- unroll the reduce dim (K), upcast and local the inner and outer dims (N, M) - for dim, amt in tc.get_reduce_axes(): self.apply_opt(Opt(OptOps.UNROLL, tc_opts.axes[2]-self.first_reduce, amt), append_opt=False) - for opt in tc.opts: self.apply_opt(Opt({"u":OptOps.UPCAST, "l":OptOps.LOCAL}[opt[0]], tc_opts.axes[int(opt[1])], 2), append_opt=False) - self.tensor_core = tc - self.use_tensor_cores = use_tensor_cores # TC=2 will do the shape ops without the WMMA - return True - return False - - def apply_tensor_cores(self, use_tensor_cores=1, extra_opts:Optional[list[Opt]]=None, axis:int=0, tc_select:Optional[int]=None, - tc_opt:Optional[int]=None) -> bool: - """ Attempts to apply a tensor core optimization to the kernel. If one exists and applies properly, return true, otherwise return false. - Tensor cores are optimized instructions that matrix multiply-accumulate across a wave of threads: D(M, N) = A(M, K) * B(K, N) + C(M, N). - - Keyword arguments: - use_tensor_cores -- controls how tensor cores are applied (default 1) - 0: will disable any tensor core matching - 1: enable tensor cores - 2: apply tensor core shape but don't use UOp.WMMA - 3: emulate tensor cores with local memory - extra_opts -- additional Opt's to apply after the tensor core instead of the hand-coded additional Opt's (default None) - tc_select -- specifies which tensor core(s) to use for optimization (default -1) - -1: iterates through all available tensor cores in order and uses the first one that matches the requirements (dims and dtypes) - [0-N]: uses only the n'th tensor core available; useful for search - tc_opt -- controls which kinds of kernels may be eligible for tensor cores application (default 2 during BEAM, 0 otherwise) - 0: applies to only kernels with a single reduce axis and direct Ops.LOAD into Ops.MUL - 1: allows kernels with multiple reduce axes and also multiplication of Ops.CAST'd buffers - 2: allows kernels with M, N, K axes that are not multiples of the tensor core dimensions by applying padding those axes as needed - """ - if tc_select is None: tc_select = TC_SELECT.value - if tc_opt is None: tc_opt = TC_OPT.value - if not self.opts.tensor_cores: return False - try: # check TC first and apply hand-coded opts if successful - self.apply_opt(Opt(OptOps.TC, axis, (tc_select, tc_opt, use_tensor_cores))) - - if (tc_opts:=self.tensor_core_opts) is not None: - if extra_opts is not None: self.apply_opts(extra_opts) - else: - if AMX: return True # skip hand-coded TC opts if AMX, upcasting will make kernel slower - # hand-coded TC opts - for tc_dim in [tc_dim for tc_dim in [1,0] if tc_opts.axes_exist[tc_dim]]: # attempt to upcast M and N - szs = [sz for sz in [5,4,3,2] if self.full_shape[tc_opts.axes[tc_dim]] % sz == 0] - if szs: self.apply_opt(Opt(OptOps.UPCAST, tc_opts.axes[tc_dim], szs[0])) - - if tc_opts.axes_exist[0] and (szs := [sz for sz in [4,2] if self.full_shape[tc_opts.axes[0]] % sz == 0]): # attempt to local N - self.apply_opt(Opt(OptOps.LOCAL, tc_opts.axes[0], szs[0])) - return True - except KernelOptError: - return False - - def real_axis(self, opt:Opt): - if opt.axis is None: return -1 - if opt.op is OptOps.UNROLL: return self.first_reduce+opt.axis - if opt.op in {OptOps.GROUP, OptOps.GROUPTOP}: return self.first_reduce+self.group_for_reduces+opt.axis - return opt.axis - - def apply_opt(self, opt:Opt, append_opt:bool=True): - if self.dont_use_locals: check(opt.op not in {OptOps.LOCAL, OptOps.GROUP, OptOps.GROUPTOP}, "not using locals") - - if opt.op is OptOps.TC: - check(len(self.applied_opts) == 0, "tensor core opts must be first") # TODO: things like PADTO might be fine - check(len(self.opts.tensor_cores) > 0, "must have tensor cores") - check(opt.axis is not None, "tensor core opts must have an axis") - check(opt.arg is not None and isinstance(opt.arg, tuple) and len(opt.arg) == 3, "tensor core opts must have valid arg") - check(-1 <= (tc_select:=cast(tuple, opt.arg)[0]) < len(self.opts.tensor_cores), "tensor core opts must have valid tc_select") - check(0 <= (tc_opt:=cast(tuple, opt.arg)[1]) <= 2, "tensor core opts must have valid tc_opt") - check(0 < (use_tensor_cores:=cast(tuple, opt.arg)[2]) <= 3, "use_tensor_cores value is not valid") - check(self._apply_tc_opt(use_tensor_cores, cast(int, opt.axis), tc_select, tc_opt), "no tensor core available") - self.applied_opts.append(opt) - return - - axis = self.real_axis(opt) - check(axis < len(self.full_shape), "invalid axis") - - if opt.op is OptOps.SWAP: amt = cast(int, opt.arg) # arg is an axis in the SWAPs - elif opt.arg is not None: - check(isinstance(opt.arg, int), "arg should be int") - amt = arg if (arg:=cast(int, opt.arg)) != 0 else self.full_shape[axis] - check(isinstance(amt, int) and amt != 1, f"shift/padto of {amt=}, 1 or symbolic amount is meaningless") - if opt.op is not OptOps.PADTO: check(self.full_shape[axis] % amt == 0, f"no longer valid shift {self.full_shape[axis]=}, {amt=}") - else: amt = -1 - - if self.reduceop is not None and (opt.op in {OptOps.GROUP, OptOps.GROUPTOP} or \ - (self.group_for_reduces and opt.op not in {OptOps.NOLOCALS, OptOps.PADTO})): - acc_sz = self.reduceop.dtype.itemsize - upcast_sz = prod([a for a,b in zip(self.full_shape[self.first_upcast:], self.sts[0].shape[self.first_upcast:]) if a == b]) - local_sz = prod(self.full_shape[self.first_reduce-self.local_dims:self.first_reduce+self.group_for_reduces]) - smem_sz = amt*acc_sz*upcast_sz*local_sz - check(smem_sz <= self.opts.shared_max, f"exceeds maximum shared memory size: needs {smem_sz}, max {self.opts.shared_max}") - - if opt.op is OptOps.LOCAL: # cyan - # NOTE: LLVM/CPU can use locals too, but they are treated the same as globals (still helpful for L1 cache) - # it's disabled for now since it makes BEAM slow for little gain - check(self.opts.has_local, "target does not support local") - check(axis < self.global_dims, "local is for globals") - self.shift_to(axis, amt, insert_before=self.first_reduce) - self.local_dims += 1 - elif opt.op in {OptOps.GROUP, OptOps.GROUPTOP}: # green - check(self.opts.has_local and self.opts.has_shared, "target does not support local or shared mem") - check(self.first_reduce + self.group_for_reduces <= axis < self.first_upcast, "must be reduce axis to group") - check(not self.tensor_core, "can't group with tensor cores") - check(len(reduce_axes:=[i for r in self.reduceops for i in r.axis_arg]) == len(set(reduce_axes)), "can't group with parallel reduces") - self.shift_to(axis, amt, top=(opt.op is OptOps.GROUPTOP), insert_before=self.first_reduce + self.group_for_reduces) - self.group_for_reduces += 1 - elif opt.op is OptOps.UNROLL: # purple - check(axis < self.first_upcast, "can't upcasted already upcasted") - check(amt <= 32, "don't unroll more than 32") - # TODO: fix upcast_count to put purples before yellows. broken because of METAL tensor cores - #upcast_count = sum(x == y for x,y in zip(self.full_shape[-self.upcasted:], self.output_shape[-self.upcasted:])) if self.upcasted else 0 - #self.shift_to(axis, amt, insert_before=None if upcast_count == 0 else self.shape_len-upcast_count) - if self.full_shape[axis] == amt and axis == self.first_reduce: self.local_dims += 1 # first_reduce will ++, so offset loss in simplify_ones - if self.full_shape[axis] == amt and axis < self.first_reduce+self.group_for_reduces: self.group_for_reduces -= 1 # fully unrolling a GROUP - self.shift_to(axis, amt, insert_before=None) - self.upcast() - elif opt.op is OptOps.UPCAST: # yellow - check(axis < self.first_reduce, "upcast is for non-reduce") - check(not (self.tensor_core and self.global_dims <= axis < self.global_dims+len(self.tensor_core.get_local_axes())), "can't upcast TC locals") - check((self.opts is not None and self.opts.device == "DSP") or amt <= 16, "don't upcast more than 16") - self.shift_to(axis, amt, insert_before=None) - self.upcast() - elif opt.op is OptOps.NOLOCALS: - check(self.opts.has_local and not self.dont_use_locals, "NOLOCALS is meaningless if target does not support local or already not using locals") - check(self.local_dims == 0 and self.group_for_reduces == 0, "can't have no locals with locals") - self.dont_use_locals = True - elif opt.op is OptOps.SWAP: - check(axis < amt < self.global_dims, f"swap is only for globals with axis < amt, getting {amt=}, {axis=}, {self.global_dims=}") - permute = list(range(self.shape_len)) - permute[axis], permute[amt] = permute[amt], permute[axis] - self.reshape_and_permute(None, tuple(permute)) - elif opt.op is OptOps.PADTO: - check(not self.vars, "does not work with symbolic shape") - check(axis < self.first_upcast, "cannot pad upcasted") - # ok to pad SUM if all parent ALU ops have f(0) = 0 - if (r:=self.reduceop) is not None and self.first_reduce <= axis: check(r.arg[0] is Ops.ADD and can_pad(r, {}), f"cannot pad {r}") - padded = False - for i,st in enumerate(self.sts): - if (s:=st.shape[axis]) == 1: continue # reduced - check(s > amt//4, f"pad adds more than quadruple the work {st.shape[axis]=} > {amt//4=}") - if (ru := round_up(cast(int, s), amt) - s): - # pad right seems to be faster - self.sts[i] = st.pad(((0,0),) * axis + ((0,ru),) + ((0,0),) * (len(st.shape)-axis-1)) - padded = True - check(padded, "nothing was padded") - - if append_opt: self.applied_opts.append(opt) - if self.simplify_ones() and self.tensor_core_opts: - self.tensor_core_opts.fix_axes(axis) # fix up axes in TC opts if required after simplify_ones() - - def apply_opts(self, opts:Sequence[Opt]) -> Kernel: - for opt in opts: self.apply_opt(opt) - return self - - # **** kernel outputs **** - - kernel_cnt: Final[defaultdict[str, int]] = defaultdict(int) - @functools.cached_property - def name(self) -> str: - # kernel name (before late upcast) - kernel_type = "r" if self.reduceop is not None else ("C" if all(x.op is Ops.SINK or x.op in GroupOp.Buffer for x in self.ast.toposort()) else "E") - suffix = colored('_', 'BLACK').join([colored(x.render() if isinstance(x, UOp) else str(x), c) for x,c in zip(self.full_shape, self.colors())]) - name = kernel_type + (f"{len(self.ast.src)}" if len(self.ast.src) > 1 else "") + "_" + suffix - - # name the function something unique - Kernel.kernel_cnt[(function_name := to_function_name(name))] += 1 - num = f"n{Kernel.kernel_cnt[function_name]-1}" if Kernel.kernel_cnt[function_name] > 1 else "" - return name + colored(num, 'BLACK') - - def get_optimized_ast(self, name_override:Optional[str]=None) -> UOp: - @functools.cache - def fixup_ast(op:UOp) -> UOp: - ret = op.replace(src=tuple(fixup_ast(x) for x in op.src)) # noqa: F821 - if op.op in GroupOp.Buffer and op in self.bufs: - st = self.sts[self.bufs.index(op)] - # NOTE: if CONST got masked after applying opts, we create a new VALID - if op.op is Ops.CONST and any(v.mask is not None for v in st.views): return op.view(st).valid() - # otherwise we just replace the VIEW source - return ret.replace(src=(ret.src[0].replace(arg=st),)+ret.src[1:]) - if op.op is Ops.SINK: - return ret.replace(arg = KernelInfo(to_function_name(self.name) if name_override is None else name_override, - self.local_dims, self.upcasted, self.dont_use_locals)) - if op.op is Ops.REDUCE_AXIS: - reduce_idx = len(self.bufs) + self.reduceops.index(op) * 2 - - def reduced_axes(start, stop): - return tuple(i for i in range(start, stop) if resolve(self.sts[reduce_idx].shape[i] != self.sts[reduce_idx + 1].shape[i])) - axes = reduced_axes(self.first_reduce + self.group_for_reduces, self.shape_len) - grouped_axes = reduced_axes(self.first_reduce, self.first_reduce + self.group_for_reduces) - - if (tc := self.tensor_core) and (self.use_tensor_cores == 1 or self.use_tensor_cores == 3): - wd, tcd = self.global_dims, self.first_upcast - def get_upcast_axes(buf): # upcast along non-zero dimensions of (tc_reduce + tc_upcast) - upcast_axes = int(math.log2(tc.elements_per_thread[buf])) - return tuple((tcd + len(tc.get_reduce_axes()) + len(tc.get_upcast_axes()) - (i+1), 2) for i in range(upcast_axes)) - def get_tc_swizzle_st(shape, local_perm, upcast_perm): - offset = (tcd - (wd + len(local_perm))) - permaxis = list(range(wd)) \ - + [wd + x + (offset if x >= len(local_perm) else 0) for x in local_perm] + list(range(wd + len(local_perm), tcd)) \ - + [wd + x + (offset if x >= len(local_perm) else 0) for x in upcast_perm] + list(range(tcd + len(upcast_perm), len(shape))) - return ShapeTracker.from_shape(shape).permute(tuple(permaxis)) - - srcs = list((ret.src[0] if ret.src[0].op is not Ops.CAST else ret.src[0].src[0]).src) - for i, (src, swizzle) in enumerate(zip(srcs, tc.swizzle)): - src_st = (src if src.op is Ops.LOAD else src.src[0]).st_arg - if swizzle: srcs[i] = src.view(get_tc_swizzle_st(src_st.shape, *swizzle)) - - if self.use_tensor_cores == 3: # for TC=3, emulate the warp addressing with locals - local_shape = tuple(1 if st == 0 or i < wd or (i >= self.first_reduce and i < tcd) else src_st.shape[i] \ - for i,st in enumerate(src_st.real_strides())) - st = store_st = ShapeTracker.from_shape(local_shape) - local_buffer = UOp(Ops.DEFINE_LOCAL, tc.dtype_in.ptr(size=st.real_size(), local=True), (), f"temp{i}") - if swizzle: store_st = get_tc_swizzle_st(store_st.shape, *swizzle) - local_store = UOp.store(local_buffer.view(store_st), srcs[i]) - srcs[i] = UOp(Ops.LOAD, tc.dtype_in, (local_buffer.view(st), local_store)) - - tc_reduce_axes = tuple(tcd + ax for ax, _ in tc.get_reduce_axes()) - if self.use_tensor_cores == 1: # real WMMA, use CONTRACT/UNROLL to get the vectorization right - tc_upcast_axes = (get_upcast_axes(0), get_upcast_axes(1), get_upcast_axes(2)) - wmma_arg = (str(tc), tc.dims, tc.dtype_in, tc.dtype_out, self.opts.device, tc.threads, tc_upcast_axes, tc_reduce_axes) - wmma = UOp(Ops.WMMA, dtype=tc.dtype_out.vec(tc.elements_per_thread[2]), src=( - UOp(Ops.CONTRACT, dtype=srcs[0].dtype.vec(tc.elements_per_thread[0]), src=(srcs[0],), arg=tc_upcast_axes[0]), - UOp(Ops.CONTRACT, dtype=srcs[1].dtype.vec(tc.elements_per_thread[1]), src=(srcs[1],), arg=tc_upcast_axes[1]), - UOp.const(tc.dtype_out.vec(tc.elements_per_thread[2]), 0.0)), arg=wmma_arg) - tc_uop = UOp(Ops.UNROLL, tc.dtype_out, (wmma,), arg=tc_upcast_axes[2]) - - else: # for TC=3 MUL/SUM instead of WMMA - tc_uop = UOp(Ops.REDUCE_AXIS, tc.dtype_out, ((srcs[0] * srcs[1]).cast(tc.dtype_out),), (Ops.ADD, tc_reduce_axes)) - - return ret.replace(src=(tc_uop,), arg=(Ops.ADD, new_axes)) if (new_axes := tuple(i for i in axes if i not in tc_reduce_axes)) else tc_uop - - ret = ret.replace(arg = (op.arg[0], axes)) - if self.group_for_reduces and grouped_axes: - local_shape = (1,) * self.global_dims + self.full_shape[self.global_dims:self.global_dims+self.local_dims] + \ - tuple([self.full_shape[i] if self.sts[reduce_idx].shape[i] != self.sts[reduce_idx+1].shape[i] else 1 \ - for i in range(self.first_reduce, self.first_reduce+self.group_for_reduces)]) + \ - (1,) * (self.shape_len - self.upcasted - self.group_for_reduces - self.first_reduce) + tuple([x[0] for x in self.upcasted_axis(0)]) - st = ShapeTracker.from_shape(local_shape) - local_size = st.real_size() - local_buffer = UOp(Ops.DEFINE_LOCAL, op.dtype.ptr(local_size, local=True), (), f"temp{self.reduceops.index(op)}") - local_load = UOp(Ops.LOAD, op.dtype, (local_buffer.view(st), UOp.store(local_buffer.view(st), ret))) - grouped_reduce = UOp(Ops.REDUCE_AXIS, op.dtype, (local_load,), arg=(op.arg[0], grouped_axes)) - if op is self.reduceops[-1]: return grouped_reduce - st = ShapeTracker.from_shape(tuple([1 if i in grouped_axes else a for i,a in enumerate(local_shape)])) - return UOp(Ops.LOAD, op.dtype, (local_buffer.view(st), UOp.store(local_buffer.view(st), grouped_reduce))) - - return ret - fixed_ast = fixup_ast(self.ast) - del fixup_ast - return graph_rewrite(fixed_ast, view_left, name="fixup optimized AST") - - # **** this is the lowerer **** - - @track_rewrites() - def linearize(self, name_override:Optional[str]=None, ast_transform:Optional[Callable]=None) -> Kernel: - # display the AST - if getenv("VIZ"): graph_rewrite(self.ast, PatternMatcher([]), name="View Base AST") - - modified_ast = self.get_optimized_ast(name_override) - if ast_transform is not None: modified_ast = ast_transform(self, modified_ast) - - if DEBUG >= 3: - print(self.name) - if DEBUG >= 5: print(self.ast) - for i,(buf,st) in enumerate([(buf,st) for buf,st in zip(self.bufs, self.sts) if buf.op not in {Ops.CONST, Ops.VALID}]): - print(f"{i:2d}: {str(st.shape):25s} {str(buf.src[0].dtype).replace('dtypes.',''):20s} {str(st.real_strides()):30s}", - str(st) if DEBUG >= 4 else "") - print(self.applied_opts) - if DEBUG >= 5: print(modified_ast) - # verify AST matches the spec after applying opts - if __debug__: type_verify(list(modified_ast.toposort())) - # TODO: sadly modified_ast doesn't pass the shape spec because of how group_for_reduces constructs UOps, there's probably a way to fix this - #if __debug__: type_verify(list(modified_ast.toposort()), ast_spec) - - try: - self.uops:list[UOp] = full_rewrite(modified_ast, self.opts) - except RuntimeError: - print("***** LINEARIZE FAILURE *****") - print(f"ast = {self.ast}") - print(f"opts = {self.applied_opts}") - raise - if DEBUG >= 6: print_uops(self.uops) - return self - - def to_program(self, name_override:Optional[str]=None, ast_transform:Optional[Callable]=None) -> ProgramSpec: - self.linearize(name_override, ast_transform) - assert self.uops[-1].op is Ops.SINK, "last uop must be sink" - src = self.opts.render(self.uops) - # group non-local bufs by the op type (LOAD or STORE) and the buffer arg. take the max access of that buffer in bytes - # TODO: these max and min don't work on symbolic, and results are very wrong. - mem_bytes = sum(max(x.src[0].dtype.nbytes() for x in group) - for _, group in itertools.groupby([x for x in self.ast.toposort() if x.op in GroupOp.Buffer and x.src[0].base.op is Ops.DEFINE_GLOBAL], - key=lambda x: (x.op, x.src[0].base.arg))) - return ProgramSpec(self.name if not name_override else name_override, src, self.opts.device, self.ast, self.uops, self.applied_opts, mem_bytes, - global_size=[1,1,1] if self.opts.has_local else None, local_size=[1,1,1] if self.opts.has_local else None) diff --git a/tinygrad/tinygrad/codegen/linearize.py b/tinygrad/tinygrad/codegen/linearize.py deleted file mode 100644 index 23dfc791..00000000 --- a/tinygrad/tinygrad/codegen/linearize.py +++ /dev/null @@ -1,245 +0,0 @@ -from __future__ import annotations -import heapq -from collections import defaultdict -from dataclasses import dataclass, replace -from tinygrad.uop.ops import UOp, Ops, PatternMatcher, UPat, GroupOp -from tinygrad.helpers import dedup, partition, all_same, flatten, getenv -from tinygrad.uop.spec import type_verify - -# NOTE: any toposort should be valid here, unlike last time this isn't required, it's just for speed -def block_reorder(lst:list[UOp]) -> list[UOp]: - in_this_block = set(lst) - local_children: defaultdict[UOp, list[UOp]] = defaultdict(list) - in_degree:dict[UOp, int] = {} - priorities:dict[UOp, int] = {} - - # get local children and assign priorities - # NOTE: this requires the lst be locally toposorted - for u in reversed(lst): - in_degree[u] = 0 - for s in u.src: - if s in in_this_block: - local_children[s].append(u) - in_degree[u] += 1 - # put loads in the beginning of the block and prevent priority inversion. hack for BARRIER grouping too - priority = [0] + [priorities[x] for x in local_children[u]] - if u.op is Ops.LOAD: priority.append(-1000) - if u.op is Ops.BARRIER: priority.append(-1500) - priorities[u] = min(priority) - - # number the uops in "ideal" order - nkey = {u:i for i,u in enumerate(sorted(lst, key=lambda x: (priorities[x],)+x.tuplize))} - - # then force then to be toposorted in as close to the ideal order as possible - heapq.heapify(heap:=[(nkey[u],u) for u in lst if in_degree[u] == 0]) - newlst = [] - while heap: - newlst.append(u:=heapq.heappop(heap)[1]) - for v in local_children[u]: - in_degree[v] -= 1 - if in_degree[v] == 0: heapq.heappush(heap, (nkey[v],v)) - - assert len(newlst) == len(lst), f"len mismatch {len(newlst)} != {len(lst)}" - return newlst - -# ***** basic block ***** - -def disp(y:UOp) -> str: - if y.op is Ops.IF: return f'IF{id(y)}' - if y.op is Ops.RANGE: return str(y.arg) - return "" - -@dataclass(frozen=True, eq=False) -class BasicBlock: - lst: tuple[UOp, ...] - ctx: tuple[UOp, ...] = () - end: UOp|None = None - cnt: int = 0 - child_ctx: tuple[UOp, ...]|None = None - def __lt__(self, _:BasicBlock): raise RuntimeError("no comparing basic blocks") - def __repr__(self): - return f"{(str(disp(self.end))+' ') if self.end is not None else ''}"+f'f{self.cnt} '+\ - f"{[disp(y) for y in self.ctx]} {[disp(y) for y in self.child_ctx] if self.child_ctx is not None else '-'} "+\ - f"{len(self.lst)}" + "\n" + '\n'.join([str(x.op) for x in self.lst]) - def last_ctx(self): return self.child_ctx if self.child_ctx is not None else self.ctx - -def _sort_ctx(inp): return tuple(sorted(dedup(inp), key=lambda x: x.tuplize)) - -# ***** block context ***** - -@dataclass -class BlockContext: - child_count: dict[UOp, int] - block_ctxs: dict[UOp, tuple[UOp, ...]] - child_ctxs: dict[UOp, tuple[UOp, ...]] - def last_ctx(self, u): return self.child_ctxs.get(u, self.block_ctxs[u]) - @staticmethod - def from_sink(sink:UOp) -> BlockContext: - # get children and all block contexts - ctx = BlockContext({}, {}, {}) - for u in sink.toposort(): - this_block_ctx: list[UOp] = [] - ctx.child_count[u] = 0 - - # get children and accumulate the last_ctx - for s in u.src: - # NOTE: if a parent appears multiple times in the src, it counts multiple times as a child - ctx.child_count[s] += 1 - this_block_ctx += ctx.last_ctx(s) - - # save the block ctx - ctx.block_ctxs[u] = _sort_ctx(this_block_ctx) - - # RANGE/IF add to the next ctx - # STORE/ASSIGN subtract from the next ctx - if u.op in {Ops.RANGE, Ops.IF}: ctx.child_ctxs[u] = _sort_ctx(ctx.block_ctxs[u] + (u,)) - elif u.op is Ops.STORE: - # ugh, deal with non-reduce locals. probably wrong - if any(x.op is Ops.DEFINE_LOCAL for x in u.src[0].toposort()): - idx_context, store_context = ctx.last_ctx(u.src[0]), ctx.last_ctx(u.src[1]) - ctx.child_ctxs[u] = tuple([y for y in store_context if y not in idx_context and y.op is Ops.RANGE]) - else: ctx.child_ctxs[u] = () - elif u.op is Ops.ASSIGN: - assert u.src[0].op is Ops.DEFINE_ACC - ctx.child_ctxs[u] = tuple([y for y in ctx.last_ctx(u.src[1]) if y not in u.src[0].src[1:]]) - return ctx - -# ***** make blocks ***** - -DONT_PLACE_IN_BLOCK = {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_VAR, Ops.SPECIAL, Ops.CONST} - -def add_blockends(base_block:UOp, new_ctx:tuple[UOp, ...], current_ctx:tuple[UOp, ...], cnt:int=1) -> UOp: - ends_to_add = [z for z in new_ctx if z not in current_ctx] - while len(ends_to_add): - r:UOp = ends_to_add.pop(-1) - new_ctx = tuple([z for z in new_ctx if z is not r]) - end_uop = UOp(Ops.ENDIF if r.op is Ops.IF else Ops.ENDRANGE, src=(r,)) - base_block = UOp(Ops.BLOCKEND, src=(base_block,)*cnt, arg=BasicBlock((end_uop,), tuple(new_ctx), end=r, cnt=cnt)) - return base_block - -def make_block_bottom_up(ctx:BlockContext, x:UOp): - if x.op is Ops.BLOCKSTART: - current_ctx, child_ctx = x.arg - lst = list(x.src) - child_count = 1 - else: - current_ctx, child_count, child_ctx = ctx.block_ctxs[x], ctx.child_count[x], ctx.child_ctxs.get(x, None) - lst = [x] - - # count of times we've seen this block, or a seed for a new block if we can't merge it - unmergable: defaultdict[UOp, int] = defaultdict(int) - blockseeds = defaultdict(list) - - # add the srcs of this to the frontier - # NOTE: things may be in here multiple times, that's okay - frontier_nodes = list(flatten(y.src[::-1] for y in lst)) - while len(frontier_nodes): - u = frontier_nodes.pop(0) - if u.op not in DONT_PLACE_IN_BLOCK and ctx.child_count[u] == unmergable[u]+1: - # count is correct - if (newctx:=ctx.block_ctxs[u]) == current_ctx: - # block has same context, merge it, and put the srcs on the frontier - lst.append(u) - frontier_nodes.extend(u.src[::-1]) - else: - # block has different context, add it to blockseeds - blockseeds[(newctx, ctx.child_ctxs.get(u, None))].append(u) - del unmergable[u] - else: - # count is incorrect (or it's DONT_PLACE_IN_BLOCK), add it to unmergable - unmergable[u] += 1 - - # add unmergables to sources - srcs = [] - for u,cnt in unmergable.items(): srcs += [add_blockends(u, ctx.block_ctxs[u], current_ctx, cnt=cnt)]*cnt - - # add blockseeds, with blockends as needed - for (new_ctx, new_child_ctx), v in blockseeds.items(): - base_block = UOp(Ops.BLOCKSTART, src=tuple(v), arg=(new_ctx, new_child_ctx)) - srcs.append(add_blockends(base_block, new_ctx, current_ctx)) - - lst = lst[::-1] - if getenv("BLOCK_REORDER", 1): lst = block_reorder(lst) - bb = BasicBlock(tuple(lst), ctx=current_ctx, cnt=child_count, child_ctx=child_ctx) - return UOp(Ops.BLOCK, src=tuple(srcs), arg=bb) - -block_create = PatternMatcher([ - (UPat(GroupOp.All-DONT_PLACE_IN_BLOCK.union({Ops.BLOCK, Ops.BLOCKEND}), name="x"), make_block_bottom_up), -]) - -# ***** blockend merging **** - -def merge_blockends(sink:UOp) -> UOp|None: - # only run on the final BLOCK with the SINK in it - if sink.arg.lst[-1].op is not Ops.SINK: return None - # combine matching BLOCKENDS, the keys of this dictionary are the RANGE UOps, values are the BLOCKENDs - blockends_to_arg: dict[UOp, list[UOp]] = {} - for be in sink.toposort(): - if be.op is Ops.BLOCKEND: blockends_to_arg.setdefault(be.arg.end, []).append(be) - new_forks = {} - for k,v in blockends_to_arg.items(): - # NOTE: if any BLOCKEND is the parent of any other with the same arg, this algo fails - if len(v) > 1: - bb = BasicBlock(v[0].arg.lst, _sort_ctx(flatten([y.arg.ctx for y in v])), k, cnt=sum(y.arg.cnt for y in v)) - out = UOp(Ops.BLOCKEND, src=tuple(flatten([x.src for x in v])), arg=bb) - # NOTE: bb.ctx != u.arg.ctx can cause problems here - for u in v: new_forks[u] = out - if len(new_forks) == 0: return None - return sink.substitute(new_forks) - -pm_blockend_merge = PatternMatcher([(UPat(Ops.BLOCK, name="sink"), merge_blockends)]) - -# ***** block merging **** - -def merge_block(x:UOp): - unmergable_blocks, mergable_blocks = [], [] - mergable_dict: defaultdict[UOp, int] = defaultdict(int) - for y in x.src: - if y.op is Ops.BLOCK and x.op is Ops.BLOCK and x.arg.ctx == y.arg.ctx: mergable_dict[y] += 1 - elif y.op is Ops.BLOCK and x.op is Ops.BLOCKEND and x.arg.end in y.arg.ctx: mergable_dict[y] += 1 - else: unmergable_blocks.append(y) - for k,v in mergable_dict.items(): - if v == k.arg.cnt: mergable_blocks.append(k) - else: unmergable_blocks.extend([k]*v) - if len(mergable_blocks) == 0: return None - del mergable_dict - - # create the block - arg = replace(x.arg, lst=tuple(flatten([y.arg.lst for y in mergable_blocks]))+x.arg.lst) - return UOp(x.op, src=tuple(flatten([y.src for y in mergable_blocks])+unmergable_blocks), arg=arg) - -def remove_blockend(x:UOp): - # if there's any remaining blocks that need to go in this BLOCKEND, we don't remove it - if any(x.arg.end in y.arg.ctx for y in x.src if y.op in {Ops.BLOCK, Ops.BLOCKEND}): return None - - if (parent_blocks := [y for y in x.src if y.op is Ops.BLOCK and y.arg.child_ctx is not None and x.arg.end in y.arg.child_ctx]): - assert all_same(parent_blocks), f"should never have two parent blocks (has {len(parent_blocks)})" - parent_block = parent_blocks[0] - assert len(parent_blocks) == parent_block.arg.cnt - # range needs DEFINE_ACC to be before the range (never in DEFINE_ACC for if) - early_ops, late_ops = partition(x.arg.lst, lambda y: y.op is Ops.DEFINE_ACC and x.arg.end in y.src) - # NOTE: we have to add a barrier at the start if barrier is used in the range - if x.op is Ops.BLOCKEND and any(y.op is Ops.BARRIER for y in late_ops) and late_ops[-1].op is Ops.ENDRANGE: - late_ops = [UOp(Ops.BARRIER)] + late_ops - arg = BasicBlock(tuple(early_ops)+parent_block.arg.lst+tuple(late_ops), tuple([y for y in x.arg.ctx if y is not x.arg.end]), cnt=x.arg.cnt) - return UOp(Ops.BLOCK, src=tuple(y for y in x.src if y is not parent_block)+parent_block.src, arg=arg) - -block_merge = PatternMatcher([ - (UPat((Ops.BLOCK, Ops.BLOCKEND), name="x"), merge_block), - (UPat(Ops.BLOCKEND, name="x"), remove_blockend), -]) - -# ****** finalize ****** - -def finalize(sink:UOp) -> UOp: - if sink.op is not Ops.BLOCK or not all(x.op in DONT_PLACE_IN_BLOCK for x in sink.src): - raise RuntimeError("linearize failure") - - # place the early things - lst = sorted(dedup(sink.src), key=lambda x: x.tuplize) + list(sink.arg.lst) - - if __debug__: type_verify(lst) - - return UOp(Ops.BLOCKFINAL, arg=BasicBlock(tuple(lst))) - -pm_finalize = PatternMatcher([(UPat(Ops.BLOCK, name="sink"), finalize)]) diff --git a/tinygrad/tinygrad/codegen/lowerer.py b/tinygrad/tinygrad/codegen/lowerer.py deleted file mode 100644 index 79223300..00000000 --- a/tinygrad/tinygrad/codegen/lowerer.py +++ /dev/null @@ -1,232 +0,0 @@ -# the job of the lowerer is to do indexing -import itertools, operator, math -from dataclasses import dataclass -from typing import cast -from tinygrad.dtype import dtypes, PtrDType, least_upper_dtype -from tinygrad.uop.ops import KernelInfo, UOp, Ops, PatternMatcher, UPat, sint, sint_to_uop -from tinygrad.renderer import Renderer -from tinygrad.helpers import all_int, prod, partition, flatten, unwrap -from tinygrad.codegen.symbolic import symbolic - -# returns the axes to create new_shape if new_shape can be created by combining axis from old_shape -def get_contraction(old_shape:tuple[sint, ...], new_shape:tuple[sint, ...]) -> list[list[int]]|None: - acc_old, acc_new = list(itertools.accumulate(old_shape, operator.mul)), list(itertools.accumulate(new_shape, operator.mul)) - try: split = [acc_old.index(acc)+1 if acc != 1 else 0 for acc in acc_new] - except ValueError: return None - return [list(range(st,ed)) for st,ed in zip([0]+split[:-1], split[:-1]+[len(old_shape)])] - -def get_contraction_with_reduce(old_shape:tuple[sint, ...], new_shape:tuple[sint, ...], reduce_axis:tuple[int, ...]) -> list[list[int]]|None: - if (contraction:=get_contraction(old_shape, new_shape)) is None: return None - # contraction returns the 1s as right justified as possible - # normally this contraction is good, but sometimes the reduce dim is empty. borrow from the next one, leaving one - # this ensures there's always ones available in the reduce dimension. this is also a valid contraction - for i in range(len(contraction)): - if i in reduce_axis and len(contraction[i]) == 0: - take_from = i+1 - while take_from < len(contraction) and len(contraction[take_from]) == 0: - assert new_shape[take_from] == 1 - take_from += 1 - if take_from == len(contraction) or new_shape[take_from] != 1: return None # nothing to take - for j in range(take_from, i, -1): - assert len(contraction[j]) > 0 - contraction[j-1] = contraction[j][:-1] - contraction[j] = contraction[j][-1:] - return contraction - -# ***** indexing ***** -def _group_dims(dims:tuple[sint, ...], max_sizes:tuple[int, ...]): - # TODO: symbolic shape - if not all_int(dims): return dims - while len(dims) > len(max_sizes) or any(d > m for d,m in zip(dims, max_sizes)): - for i,m in enumerate(max_sizes): - if i < (len(dims)-1) and dims[i] * dims[i+1] <= m: - dims = dims[:i] + (dims[i]*dims[i+1],) + dims[i+2:] - break - else: return None - return dims - -def _split_dims(dims, max_sizes): - if all(d <= m for d,m in zip(dims, max_sizes)): return dims - _dims = list(dims) + [1]*(3-len(dims)) - for i in range(len(_dims)): - while _dims[i] > max_sizes[i]: - div = next((d for d in range(2, math.ceil(math.sqrt(_dims[i])) + 1) if (_dims[i] % d) == 0), 1) - if div == 1: raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") - _dims[i], _dims[(i+1)%len(_dims)] = _dims[i]//div, _dims[(i+1)%len(_dims)]*div - return tuple(_dims[:2] if _dims[2] == 1 else _dims[0] if _dims[1:3] == [1,1] else _dims) - -def get_grouped_dims(prefix, dims:tuple[sint, ...], max_sizes:tuple[int, ...]|None, reverse=False) -> list[UOp]: - if reverse: dims = dims[::-1] - # try to group first: (a, b, c, d) -> (ab, c, d) - limited = (grouped if (grouped := _group_dims(dims, max_sizes)) else dims) if max_sizes is not None else dims - # check if grouping failed - if max_sizes is not None and len(limited) > len(max_sizes): raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") - # try to split up dims: (a,) -> (b, c) - if limited == dims: limited = _split_dims(dims, max_sizes) if max_sizes is not None else dims - ret = raw_idxs = [UOp(Ops.SPECIAL, dtypes.int, (), (f"{prefix}{i}", s)) for i,s in enumerate(limited)] - if len(limited) < len(dims): - ret = [] - if (contraction:=get_contraction(dims, limited)) is None: raise AssertionError(f"get_contraction should not be None {dims=} {limited=}") - for idx, contraction_group in zip(raw_idxs, contraction): - for c in contraction_group[:-1]: - ret.append(idx % dims[c]) - idx //= dims[c] - ret.append(idx) - elif len(limited) > len(dims): - a, b = len(limited), len(dims) - if a == 2 and b == 1: ret = [raw_idxs[0] * limited[1] + raw_idxs[1]] - if a == 3 and b == 1: ret = [raw_idxs[0] * (limited[1] * limited[2]) + raw_idxs[1] * limited[2] + raw_idxs[2]] - if a == 3 and b == 2: ret = [raw_idxs[0] * limited[1] + raw_idxs[1], raw_idxs[2]] - return ret[::-1] if reverse else ret - -@dataclass -class IndexContext: - idxs: list[UOp] - ridxs: list[UOp] - -def get_index(ast:UOp, opts:Renderer) -> IndexContext: - ki = ast.arg if isinstance(ast.arg, KernelInfo) else KernelInfo() - # NOTE: assumes the shape is - full_shape = ast.full_shape - first_upcasted = len(full_shape)-ki.upcasted - # if there's no reduce, this is first_upcasted. assumes reduces are at the end - first_reduce = min([first_upcasted]+flatten(x.axis_arg for x in ast.toposort() if x.op is Ops.REDUCE_AXIS)) - local_loads = [x for x in ast.toposort() if x.op is Ops.LOAD and x.src[0].base.op is Ops.DEFINE_LOCAL] - # NOTE: sum up the reduced axes looking across all local loads, yields the number of grouped reduces - group_for_reduces = sum([any(l.st_arg.shape[i]!=ast.src[0].st_arg.shape[i] for l in local_loads) for i in range(first_reduce,first_upcasted)]) - global_dims = first_reduce-ki.local_dims - - if opts.has_local: - if ki.dont_use_locals: - assert ki.local_dims == 0, "can't use locals if there's no local dims" - idxs = get_grouped_dims("idx", full_shape[:global_dims], opts.global_max, reverse=True) - else: - # define indexes for GPU-like execution - idxs = get_grouped_dims("gidx", full_shape[:global_dims], opts.global_max, reverse=True) + \ - get_grouped_dims("lidx", full_shape[global_dims:first_reduce+group_for_reduces], opts.local_max) - else: - # all loops are RANGES - idxs = [UOp(Ops.RANGE, dtypes.int, (sint_to_uop(g),), i) for i,g in enumerate(full_shape[:first_reduce])] - - # reduce loops - idxs += [UOp(Ops.RANGE, dtypes.int, (sint_to_uop(g),), i) - for i,g in enumerate(full_shape[first_reduce+group_for_reduces:first_upcasted], start=first_reduce+group_for_reduces)] - - # upcast loops - for i,g in enumerate(full_shape[first_upcasted:], start=first_upcasted): - assert isinstance(g, int), "needs to be int to upcast/unroll" - idxs.append(UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(g), tuple(range(g))),), ((i,g),))) - - # late indexes (group for reduce) - ridxs = idxs[:] - for a in range(first_reduce, first_reduce+group_for_reduces): - ridxs[a] = UOp(Ops.RANGE, dtypes.int, (sint_to_uop(full_shape[a]),), 1000+a) - - return IndexContext(idxs, ridxs) - -# ***** lowering (given index) ***** - -def lower_reduce_axis(ctx: IndexContext, x: UOp): - # NOTE: always using ridxs is fine here - reduce_range, reduce_expand = partition([ctx.ridxs[i] for i in x.axis_arg], lambda y: y.op is Ops.RANGE) - assert all(x.op is Ops.UNROLL for x in reduce_expand), f"not all UNROLLS in {reduce_expand} for {x.axis_arg}" - alu_op: Ops = x.arg[0] - ret = x.src[0] - if len(contract_axis:=flatten(x.arg for x in reduce_expand)): - ret = UOp(Ops.CONTRACT, x.dtype.vec(prod(x[1] for x in contract_axis)), (ret,), tuple(contract_axis)) - # REDUCE supports both "horizonal" reduction and range reduction. the horizonal elements are taken in the nearest group - return UOp(Ops.REDUCE, x.dtype, (ret,)+tuple(reduce_range), alu_op) - -def lower_load_store(ctx: IndexContext, x: UOp, buf: UOp): - idx, valid = x.st_arg.to_indexed_uops(ctx.ridxs if x.op is Ops.LOAD and buf.op is Ops.DEFINE_LOCAL else ctx.idxs) - if x.op is Ops.LOAD: - barrier = (UOp(Ops.BARRIER, dtypes.void, (x.src[1],)),) if buf.op is Ops.DEFINE_LOCAL else () - return UOp(Ops.LOAD, x.dtype, (buf.index(idx, valid),) + barrier) - # NOTE: only store the local reduceop in the threads that are actually doing the reduce - if cast(PtrDType, buf.dtype).local and x.src[1].op is Ops.REDUCE: - reduce_input = x.src[1].src[0] - store_back = reduce_input.op is Ops.LOAD and cast(PtrDType, reduce_input.src[0].dtype).local - else: store_back = False - # NOTE: If we're storing the reduced value back into each thread, need to zero-out the reduced axes - if store_back: idx, _ = x.st_arg.to_indexed_uops([u.const_like(0) if u in x.src[1].src else u for u in ctx.idxs]) - if (not cast(PtrDType, buf.dtype).local) or store_back: - for oidx, ridx in zip(ctx.idxs, ctx.ridxs): - if oidx is not ridx: valid = valid * oidx.eq(0) - return UOp(Ops.STORE, dtypes.void, (buf.index(idx, valid), x.src[1])) - -def lower_const(x:UOp): - assert all(v.mask is None for v in unwrap(x.st).views), f"VIEW in CONST/DEFINE_VAR source must be unmasked, got {x.st}" - return x.replace(src=()) - -pm_lowerer = PatternMatcher([ - (UPat(Ops.REDUCE_AXIS, name="x"), lower_reduce_axis), - (UPat((Ops.CONST, Ops.DEFINE_VAR), src=(UPat(Ops.VIEW),), name="x"), lower_const), - (UPat(Ops.VALID, src=(UPat(Ops.VIEW),), name="x"), lambda ctx,x: x.st_arg.to_indexed_uops(ctx.idxs)[1]), - # rewrite LOAD/STORE VIEW to LOAD/STORE with indexed - (UPat((Ops.LOAD, Ops.STORE), src=(UPat.var("buf").view(),), allow_any_len=True, name="x"), lower_load_store), - (UPat(Ops.INDEX, src=(UPat.var("b"), UPat.var("idx"), UPat.const(dtypes.bool, True))), lambda b, idx: b.index(idx)), - (UPat(Ops.IGNORE, name="x"), lambda x: x.src[0]), -]) - -# **** this is the "quantization preprocessor", it makes ONNX quantized models, and probably also others, actually use ints **** - -FP = (1 << 15) -pm_quant = symbolic+PatternMatcher([ - # cast after add/mul - (UPat.var("x").cast(dtypes.float32) + UPat.var("y").cast(dtypes.float32), - lambda x,y: (x.cast(least_upper_dtype(x.dtype, y.dtype))+y.cast(least_upper_dtype(x.dtype, y.dtype))).cast(dtypes.float32)), - (UPat.var("x").cast(dtypes.float32) * UPat.var("y").cast(dtypes.float32), - lambda x,y: (x.cast(least_upper_dtype(x.dtype, y.dtype))*y.cast(least_upper_dtype(x.dtype, y.dtype))).cast(dtypes.float32)), - - # masked MUL after masked ADD - ((UPat.var("x") + UPat.var("v").where(UPat.var('cadd'), UPat(Ops.CONST, arg=0))) * UPat.var("v").where(UPat.var('cmul'), UPat(Ops.CONST, arg=0)), - lambda x,v,cadd,cmul: x*v.where(cmul, 0)+v.where(cadd*cmul, 0)), - - # MUL after reduce - (UPat(Ops.REDUCE_AXIS, src=(UPat.var("x") * UPat.cvar("c"),), name="r"), lambda x,c,r: r.replace(src=(x,))*c.arg), - # CAST after reduce (doesn't work if it's a size change) - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.CAST, src=(UPat.var("x"),)),), name="r"), - lambda x,r: r.replace(dtype=x.dtype, src=(x,)).cast(r.dtype) if dtypes.is_float(r.dtype) else None), - - # x*c1 + y*c2 -> (x+y)*c1 (if c1 and c2 are close floats) - (UPat.var("x")*UPat.cvar("c1", dtype=dtypes.floats) + UPat.var("y")*UPat.cvar("c2", dtype=dtypes.floats), - lambda x,y,c1,c2: (x+y)*c1 if abs(c1.arg-c2.arg) < 1e-9 else None), - # mul 0 * c1 is 0 - (UPat(Ops.VALID, src=(UPat(Ops.VIEW, name="v"),)).where(UPat.cvar("c1"), UPat(Ops.CONST, arg=0)) * - UPat(Ops.LOAD, src=(UPat().view(name="v"),)).cast(dtypes.int).cast(dtypes.float).named("ld"), lambda ld,v,c1: ld*c1), - # mul (with plus) 0 * c1 is 0 - (UPat(Ops.VALID, src=(UPat(Ops.VIEW, name="v"),)).where(UPat.cvar("c1"), UPat(Ops.CONST, arg=0)) * - (UPat(Ops.LOAD, src=(UPat().view(name="v"),)).cast(dtypes.int) + \ - UPat(Ops.VALID, src=(UPat(Ops.VIEW, name="v"),)).where(UPat.cvar(), UPat(Ops.CONST, arg=0))).cast(dtypes.float).named("ld"), - lambda ld,v,c1: ld*c1), - - # const push through add - ((UPat.var("x")*UPat.cvar("c1") + UPat.var("y")*UPat.cvar("c2")) * UPat.cvar("c3"), lambda x,y,c1,c2,c3: (x*c1*c3) + (y*c2*c3)), - - # fixed point mult, replace (x.float()*c1+c2).int() with an int expression - ((UPat.var("x").cast(dtypes.float)*UPat.var("c1")+UPat.var("cc")).cast(dtypes.int), - lambda x,c1,cc: ((x*(c1*FP).cast(x.dtype) + (cc*FP).cast(x.dtype)) // FP).cast(dtypes.int)), - # fixed point mult, replace (x.float()*c1 + y.float()*c2)*cc.int() with an int expression - ((UPat.var("x").cast(dtypes.float)*UPat.var("c1")+UPat.var("y").cast(dtypes.float)*UPat.var("c2")+UPat.var("cc")).cast(dtypes.int), - lambda x,c1,y,c2,cc: ((x*(c1*FP).cast(x.dtype) + y.cast(x.dtype)*(c2*FP).cast(x.dtype) + (cc*FP).cast(x.dtype)) // FP).cast(dtypes.int)), - - # where move - (UPat.var("valid").where(UPat.var("yes"), UPat(Ops.CONST, arg=0))*UPat.var("mul"), lambda valid, yes, mul: - (yes*mul*valid.where(UOp.const(mul.dtype, 1), UOp.const(mul.dtype, 0))) if yes.op is not Ops.CONST or yes.arg != 1 else None), - ((UPat.var("x")*UPat.cvar("c"))*(UPat.var().where(UPat(Ops.CONST, arg=1), UPat(Ops.CONST, arg=0)).named("v")), lambda x,c,v: (x*v)*c), - (UPat.var("x").cast().named('c') * UPat.var('valid').where(UPat(Ops.CONST, arg=1), UPat(Ops.CONST, arg=0)), lambda x,c,valid: - (x*valid.where(UOp.const(x.dtype, 1), UOp.const(x.dtype, 0))).cast(c.dtype)), - ((UPat.var('x') * UPat.var('v1').where(UPat(Ops.CONST, arg=1), UPat(Ops.CONST, arg=0)) * - UPat.var('v2').where(UPat(Ops.CONST, arg=1), UPat(Ops.CONST, arg=0))).named("mul"), lambda x, mul, v1, v2: - x * (v1&v2).where(UOp.const(mul.dtype, 1), UOp.const(mul.dtype, 0))), - - # where on two adds - (UPat.var("x") + UPat.var("v").where(UPat.var("a0"), UPat.var("a1")) + UPat.var("v").where(UPat.var("b0"), UPat.var("b1")), - lambda x,v,a0,a1,b0,b1: x + v.where(a0+b0, a1+b1)), - - # split REDUCE into multiple reduces (who remembers FOIL?) - (UPat(Ops.REDUCE_AXIS, src=((UPat(Ops.CAST, name="v1")+UPat.var("c1")) * UPat(Ops.CAST, name="v2"),), name="r"), - lambda v1,v2,c1,r: r.replace(src=(v1*v2,)) + r.replace(src=(c1*v2,))), - (UPat(Ops.REDUCE_AXIS, src=((UPat(Ops.CAST, name="v1")+UPat.var("c1")) * (UPat(Ops.CAST, name="v2",)+UPat.var("c2")),), name="r"), - lambda v1,v2,c1,c2,r: r.replace(src=(v1*v2,)) + r.replace(src=(c2*v1,)) + r.replace(src=(c1*v2,)) + r.replace(src=(c1*c2,))), -]) diff --git a/tinygrad/tinygrad/codegen/symbolic.py b/tinygrad/tinygrad/codegen/symbolic.py deleted file mode 100644 index f293e66b..00000000 --- a/tinygrad/tinygrad/codegen/symbolic.py +++ /dev/null @@ -1,472 +0,0 @@ -# all of symbolic lives here now -from typing import Any, Literal, cast -import math, operator, struct, functools -from collections import defaultdict -from tinygrad.uop.ops import Ops, PatternMatcher, UPat, UOp, GroupOp, exec_alu -from tinygrad.dtype import ConstType, dtypes, PtrDType -from tinygrad.helpers import partition, all_same, prod, flatten, get_single_element, cdiv, cmod, CORRECT_DIVMOD_FOLDING -from tinygrad.codegen.transcendental import xpow - -# ******** phase 1 of symbolic used to live in ops, it's the most generic folding rules ******** - -def simplify_pow(x:UOp, c:UOp) -> UOp|None: - if c.arg < 0: return x.reciprocal().pow(-c) - if c.arg == 0: return x.const_like(1) - if int(c.arg-0.5)+0.5 == c.arg: return x.pow(c.const_like(c.arg-0.5)) * x.sqrt() - if int(c.arg) == c.arg: return (y := x.pow(c.const_like(c.arg//2))) * y * (x if c.arg%2 == 1 else 1) - return None - -def fold_bitcast(root:UOp, c:UOp) -> UOp|None: - if (from_fmt:=c.dtype.scalar().fmt) is None or (to_fmt:=root.dtype.scalar().fmt) is None: return None - def convert(v:Any): return struct.unpack(to_fmt, struct.pack(from_fmt, v))[0] - return root.const_like(convert(c.arg) if root.dtype.count == 1 else tuple(map(convert, c.arg))) - -symbolic_simple = PatternMatcher([ - # ** self folding ** - (UPat.var("x") + 0, lambda x: x), # x+0 -> x - (UPat.var("x") * 1, lambda x: x), # x*1 -> x - (UPat.var("x") // UPat.var("x"), lambda x: x.const_like(1)), # x//x -> 1 - (UPat.var("x") // 1, lambda x: x), # x//1 -> x - (UPat.var("x") // -1, lambda x: -x), # x//-1 -> -x - (UPat.var("x") / UPat.var("x"), lambda x: x.const_like(1)), # x/x -> 1 - ((UPat.var("x") * UPat.var("x2")) / UPat.var("x2"), lambda x,x2: x), # (x*x2)/x2 -> x - ((UPat.var() % UPat.var("y")).named("base") % UPat.var("y"), lambda base,y: base), # (x%y)%y = -> x%y (rewritten with base for speed) - (UPat.var("x")%UPat.cvar("c")+(UPat.var("x")//UPat.cvar("c"))*UPat.cvar("c"), lambda x,c: x), # (x%c)+(x//c)*c = x - ((UPat.var("x")//UPat.cvar("c1"))*UPat.cvar("c3")+UPat.var("x")%UPat.cvar("c1")*UPat.cvar("c2"), - lambda x,c1,c2,c3: x*c2 if c1.arg*c2.arg==c3.arg else None), # (x%c1)*c2+(x//c1)*c3 = x*c2 if c1*c2==c3 - (UPat.var("x", dtype=dtypes.bool) & UPat.cvar("c", vec=False), lambda x,c: x if c.arg else c), - (UPat.var("x", dtype=dtypes.bool) | UPat.cvar("c", vec=False), lambda x,c: c if c.arg else x), - (UPat(GroupOp.Idempotent, src=(UPat.var("x"), UPat.var("x"))), lambda x: x), - (UPat.var("x", dtype=dtypes.bool).logical_not().logical_not(), lambda x: x), - (UPat.var("x", dtype=dtypes.bool).where(UPat.const(dtypes.bool, True), UPat.const(dtypes.bool, False)), lambda x: x), - # ** zero folding ** - (UPat.var("x") < UPat.var("x"), lambda x: x.const_like(False).cast(dtypes.bool.vec(x.dtype.count))), # x < x -> False - (UPat.var("x") % UPat.var("x"), lambda x: x.const_like(0)), # x%x -> 0 - (UPat.var("x", dtype=dtypes.ints) != UPat.var("x", dtype=dtypes.ints), - lambda x: x.const_like(False).cast(dtypes.bool.vec(x.dtype.count))), # x != x -> False (only ints) - # x*0 -> 0 or 0*x -> 0 - # if x is nan or inf it should render the nan value. - # NOTE: this can be wrong for loaded NaN - (UPat.var("x") * 0, lambda x: x.const_like(float("nan") if isinstance(x.arg, float) and (math.isnan(x.arg) or math.isinf(x.arg)) else 0)), - # ** constant folding ** - # TODO: add const folding for Ops.THREEFRY - (UPat(GroupOp.Unary, src=(UPat((Ops.VCONST, Ops.CONST)),), name="a"), lambda a: a.const_like(exec_alu(a.op, a.dtype, [a.src[0].arg], False))), - (UPat(GroupOp.Binary-{Ops.THREEFRY}, src=(UPat((Ops.VCONST, Ops.CONST)),)*2, name="a"), - lambda a: a.const_like(exec_alu(a.op, a.dtype, [a.src[0].arg, a.src[1].arg], False))), - (UPat(GroupOp.Ternary, src=(UPat((Ops.VCONST, Ops.CONST)),)*3, name="a"), - lambda a: a.const_like(exec_alu(a.op, a.dtype, [a.src[0].arg, a.src[1].arg, a.src[2].arg], False))), - # bool MUL is AND, ADD/MAX is OR. prevents other rules to rewrite bool ADD/MUL incorrectly - (UPat.var('x', dtype=dtypes.bool) * UPat.var('y', dtype=dtypes.bool), lambda x,y: x&y), - (UPat.var('x', dtype=dtypes.bool) + UPat.var('y', dtype=dtypes.bool), lambda x,y: x|y), - (UPat.var('x', dtype=dtypes.bool).maximum(UPat.var('y', dtype=dtypes.bool)), lambda x,y: x|y), - # *** cast/bitcast *** - (UPat(Ops.CAST, name="root", src=(UPat.cvar("c"),)), lambda root, c: root.const_like(c.arg)), - (UPat((Ops.CAST, Ops.BITCAST), name="root"), lambda root: root.src[0] if root.dtype == root.src[0].dtype else None), - (UPat(Ops.BITCAST, name="root", src=(UPat.cvar("c"),)), fold_bitcast), - # ** pow ** - (UPat.var("x").alu(Ops.POW, UPat.cvar("c", vec=False)), simplify_pow), - # positive const ** x - (UPat.cvar("c", vec=False).alu(Ops.POW, UPat.var("x")), lambda c,x: c if c.arg == 1 else (x*math.log2(c.arg)).exp2() if c.arg > 0 else None), -]) - -# ******** phase 2 builds on phase 1, it includes the old "symbolic", rules that match deeper ******** - -def split_uop(x:UOp, sep:Ops): - if x.op is sep: - for s in x.src: yield from split_uop(s, sep) - else: yield x - -def fold_unrolled_divs(divs:UOp, denominator: int, fac=1) -> UOp|None: - # div pattern in unrolled arange - # example: (x//4+(x+1)//4+(x+2)//4+(x+3)//4 -> x - seen_const, ans = [], None - for u in split_uop(divs, Ops.ADD): - if fac!=1: - if u.op is not Ops.MUL or u.src[1].op is not Ops.CONST or u.src[1].arg != fac: return None - u = u.src[0] - if not (u.op is Ops.IDIV and u.src[1].op is Ops.CONST): return None - if denominator != u.src[1].arg: return None - if (s0:=u.src[0]).vmin < 0: return None - # assumed CONST is the last of an ADD - if s0.op is Ops.ADD and s0.src[1].op is Ops.CONST and s0.src[1].op is Ops.CONST: - seen_const.append(s0.src[1].arg) - s0 = s0.src[0] - else: seen_const.append(0) - if ans is None: ans = s0 - if ans is not s0: return None - if ans is None: return None - # the first (denominator-len(seen_const)) terms may have been folded to 0 already - for i in range(denominator-len(seen_const)): - if ans is not None and 0 <= ans.vmin and ans.vmax + i < denominator: seen_const.append(i) - if sorted(seen_const)==list(range(denominator)): - return fac*ans - return None - -def lt_folding(x:UOp, c:int) -> UOp|None: - p, np = partition(split_uop(x, Ops.ADD), lambda u: u.const_factor() == 1) - if np and (d:=math.gcd(*[u.const_factor() for u in np], c)) > 1 and 0 <= sum(u.vmin for u in p) and sum(u.vmax for u in p) < d: - return cast(UOp, functools.reduce(operator.add, np).divides(d))<(c//d) - return None - -def canonicalize_simplex(X:UOp) -> UOp|None: - # (X := a0*x0 + a1*x1 + ...) > 0 is equivalent to x0 + x1 + ... > 0 if xi >= 0 and ai > 0 for ints. - # returns x0 + x1 + ... in such case, or None if not - changed, ret = False, [] - for u in split_uop(X, Ops.ADD): - # assumed the const is the last src of MUL - if u.op is Ops.MUL and u.src[1].op is Ops.CONST and u.src[1].arg > 0: - changed = True - u = u.src[0] - if not (u.op in GroupOp.Irreducible and u.vmin >= 0): return None - ret.append(u) - return functools.reduce(operator.add, ret) if changed else None - -def div_and_mod_folding(x: UOp, y: UOp, which: Literal[Ops.MOD, Ops.IDIV], split_rem: bool=False) -> UOp|None: - # simplify x // y or x % y, None means no change - # simple cancel div/mod case - x_min, x_max, y_min, y_max = x.vmin, x.vmax, y.vmin, y.vmax - assert isinstance(x_min, int) and isinstance(x_max, int) and isinstance(y_min, int) and isinstance(y_max, int) - - if y_min*y_max > 0 and (q:=cdiv(x_min,y_min)) == cdiv(x_min,y_max) == cdiv(x_max,y_min) == cdiv(x_max,y_max): - return x - q*y if which is Ops.MOD else x.const_like(q) - - if (y.op is not Ops.CONST) or ((c := y.arg) <= 0) or (x.dtype.count > 1): return None - - svars, factors, quotients, remainders, gcd, div, const, something_changed = [], [], [], [], c, 1, 0, False - for u in split_uop(x, Ops.ADD): - if u.op is Ops.MOD and which is Ops.MOD and u.src[1].op is Ops.CONST and u.src[1].arg%c == 0: - u = u.src[0] - something_changed = True - v: UOp = u.divides(f:=u.const_factor()) - q, r = divmod(f, c) - if r==0 or ((which is Ops.MOD or split_rem or u.op is Ops.CONST) and r!=f): something_changed = True - if u.op is Ops.CONST: const += f - else: # div is the smallest common divisor of all terms - if f > 1 and c % f == 0 and (div == 1 or div > f): div = f - gcd = math.gcd(r, gcd) - factors.append(f); svars.append(v); quotients.append(q); remainders.append(r) # noqa: E702 - - # we can fold if the expression has only one non-constant term and this term can only take on two values - if len(svars)==1 and (v:=svars[0]).vmax-v.vmin == 1: - y1 = cmod(factors[0]*v.vmin+const, c) if which is Ops.MOD else cdiv(factors[0]*v.vmin+const, c) - y2 = cmod(factors[0]*v.vmax+const, c) if which is Ops.MOD else cdiv(factors[0]*v.vmax+const, c) - return (y2-y1)*(v-v.vmin) + y1 - - if not CORRECT_DIVMOD_FOLDING or x_min>=0: - # a//c = (a-a%c)/c, if we can fold a%c, we can fold a//c - # within a mod we can freely subtract multiples of c, we use this to see if a is congruent to an expression whose vmin/vmax are between 0 and c - rems = [min(r, r-c, key=abs) for r in remainders] - if (rem:=sum(r*v for r,v in zip(rems,svars))+const%c).vmin//c==rem.vmax//c and all(f > 0 for f in factors): - if which is Ops.MOD: return rem - rem.vmin//c*c - return sum((f-r)//c * v for f,r,v in zip(factors,rems,svars)) + (const-const%c+rem.vmin//c*c)//c - - if (g:=math.gcd(gcd, const))!=1: - ret = UOp(which, x.dtype, src=(sum(f//g * v for f,v in zip(factors, svars)) + const//g, x.const_like(c//g))) - return ret*g if which is Ops.MOD else ret - - if gcd != 1: something_changed = True - if not something_changed: - if which is Ops.IDIV and (1 < div < c) and (newx:=div_and_mod_folding(x, x.const_like(div), Ops.IDIV)) is not None: return newx//(c//div) - return None - quo, rem = x.const_like(const//c), x.const_like((const%c)//gcd) - for q,r,f,v in zip(quotients, remainders, factors, svars): - if which is Ops.IDIV and (not split_rem) and r!=0: - rem += f//gcd * v - else: - rem += r//gcd * v - quo += q * v - - # if numerator before/after is negative, and it has remainder, don't simplify because C divmod is different from python divmod. - if (x_min < 0 or rem.vmin < 0) and remainders: return None - if which is Ops.MOD: return gcd*(rem % (c//gcd)) + const%gcd - return rem//(c//gcd)+quo - -def gep_through_wmma(gep:UOp, wmma:UOp): - out_sz = prod(x[1] for x in wmma.arg[6][-1]) - wmma_idxs = gep.arg[::out_sz] - for i in range(out_sz): - if tuple(x-i for x in gep.arg[i::out_sz]) != wmma_idxs: return None - tsrcs = [] - for s,sz in zip(wmma.src, wmma.arg[6]): - src_args = [] - ssz = prod(x[1] for x in sz) - for w in wmma_idxs: src_args += list(range((w//out_sz)*ssz, (w//out_sz)*ssz + ssz)) - tsrcs.append(s.gep(tuple(src_args))) - return UOp(Ops.WMMA, gep.dtype, tuple(tsrcs), wmma.arg) - -gep_pushing = PatternMatcher([ - # GEP/VECTORIZE, GEP/GEP, GEP/CONST, GEP/VCONST - (UPat(Ops.GEP, src=(UPat(Ops.GEP, name='g2'),), name='g1'), - lambda g1, g2: g2.src[0].gep(tuple(g2.arg[g1.arg[i]] for i in range(len(g1.arg))))), - (UPat(Ops.GEP, src=(UPat(Ops.VECTORIZE, name="vec"),), name="gep"), - lambda gep, vec: UOp(Ops.VECTORIZE, gep.dtype, tuple(vec.src[i] for i in gep.arg)) if len(gep.arg) > 1 else vec.src[gep.arg[0]]), - (UPat(Ops.GEP, src=(UPat.cvar("c", vec=False),), name="gep"), lambda gep, c: gep.const_like(c.arg)), - (UPat(Ops.GEP, src=(UPat(Ops.VCONST, name="c"),), name="gep"), lambda gep, c: gep.const_like(tuple(c.arg[x] for x in gep.arg))), - # GEP on void is skipped - (UPat(Ops.GEP, src=(UPat(dtype=dtypes.void, name="x"),)), lambda x: x), - # GEP in order is removed - (UPat(Ops.GEP, name="g"), lambda g: g.src[0] if not isinstance(g.dtype, PtrDType) and g.arg == tuple(range(g.src[0].dtype.count)) else None), - # push all GEPs through ALUs (fix arange stuff) - (UPat(Ops.GEP, src=(UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST), name='alu'),), name='gep'), - lambda gep,alu: UOp(alu.op, alu.dtype.scalar().vec(gep.dtype.count), tuple(x.gep(gep.arg) for x in alu.src), alu.arg) \ - if not isinstance(gep.dtype, PtrDType) else None), - # CAT can't be rendered. it's a VECTORIZE on vectors, we expand to a single VECTORIZEs with GEPs (TODO: move this later) - (UPat(Ops.CAT, name="x"), lambda x: UOp(Ops.VECTORIZE, x.dtype, tuple(y.gep(i) for y in x.src for i in range(y.dtype.count))) \ - if not isinstance(x.dtype, PtrDType) else None), - # VECTORIZE on same GEP - (UPat(Ops.VECTORIZE, name="v", src=UPat(Ops.GEP, src=(UPat.var("x"),))), lambda v,x: x.gep(tuple(get_single_element(i.arg) for i in v.src))), - # push some GEPs through WMMAs - (UPat(Ops.GEP, src=(UPat(Ops.WMMA, name="wmma"),), name="gep"), gep_through_wmma), -]) - -commutative = PatternMatcher([ - # ** COMMUTATIVE flipping (only for ints) ** - # NOTE: this can break merging vector math by only flipping some of them - (UPat(GroupOp.Commutative, dtype=dtypes.int, name='x'), lambda x: x.replace(src=x.src[::-1]) if x.src[1].tuplize < x.src[0].tuplize else None), -]) - -symbolic = symbolic_simple+commutative+PatternMatcher([ - # ** boolean algebra ** - (UPat.var("x") | (UPat.var("x") & UPat.var()), lambda x: x), # x|(x&y) -> x - # ** combine terms ** - (UPat.var("x") * UPat.cvar("c0") + UPat.var("x") * UPat.cvar("c1"), lambda x,c0,c1: x*(c0+c1)), # (x*c0)+(x*c1) -> x*(c0+c1) - ((UPat.var("y") + UPat.var("x") * UPat.cvar("c0")) + UPat.var("x") * UPat.cvar("c1"), lambda x,y,c0,c1: y+x*(c0+c1)), - (UPat.var("x") + UPat.var("x") * UPat.cvar("c"), lambda x,c: x*(c+1)), # (x+x*c)-> x*(c+1) - ((UPat.var("y") + UPat.var("x")) + UPat.var("x") * UPat.cvar("c"), lambda x,y,c: y+x*(c+1)), - (UPat.var("x") + UPat.var("x"), lambda x: x*2), # (x+x)-> x*2 - ((UPat.var("y") + UPat.var("x")) + UPat.var("x"), lambda y,x: y+x*2), - ((UPat.var("x") / UPat.var("x2")) / UPat.var("x3"), lambda x,x2,x3: x/(x2*x3) if x2 is not x3 else None), # (x/x2)/x3 -> x/(x2*x3) - (-1 * (UPat.var("x") + UPat.cvar("c")), lambda x,c: (-x)+(-c)), # -(x+c) -> -x + -c - # a conditional with the same results either way is a noop, also fold const conditionals - (UPat.var().where(UPat.var("val"), UPat.var("val")), lambda val: val), - (UPat.cvar("gate", vec=False).where(UPat.var("c0"), UPat.var("c1")), lambda gate, c0, c1: c0 if gate.arg else c1), - (UPat.var("cond", dtype=dtypes.bool).logical_not().where(UPat.var("t"), UPat.var("f")), lambda cond, t, f: cond.where(f,t)), - # alu of two where with same conds can combine, only do if true branch or false branch is const - (UPat(GroupOp.Binary, name="alu", src=(UPat.var("c").where(UPat.var("t"), UPat.var("f")), UPat.var("c").where(UPat.var("tt"), UPat.var("ff")))), \ - lambda alu,c,t,tt,f,ff: c.where(t.alu(alu.op, tt), f.alu(alu.op, ff)) if t.op == tt.op == Ops.CONST or f.op == ff.op == Ops.CONST else None), - # ALU/variable min==max -> CONST (slow!) - (UPat(GroupOp.ALU|{Ops.DEFINE_VAR, Ops.SPECIAL, Ops.RANGE}, name="x"), lambda x: x.const_like(x.vmin) if x.vmin == x.vmax else None), - # max folding - (UPat.maximum(UPat.var("x"), UPat.var("y")), lambda x,y: x if x.vmin >= y.vmax else y if x.vmax <= y.vmin else None), - # TODO: why does this rule break beautiful_mnist? - #((UPat.var("x")+UPat.var("z")).maximum(UPat.var("y")+UPat.var("z")), lambda x,y,z: x.maximum(y) + z), - #((UPat.var("x")*UPat.cvar("c1")).maximum(UPat.var("x")*UPat.cvar("c2")), max_var_const), - # ** two stage ALU folding ** - *((UPat.var("x").alu(op, UPat.cvar("c1")).alu(op, UPat.cvar("c2")).named("f"), - lambda f,x,c1,c2: x.alu(f.op,c1.alu(f.op,c2))) for op in GroupOp.Associative), - ((UPat.cvar("c0") + UPat.var("x")) < UPat.cvar("c1"), lambda x,c0,c1: x<(c1-c0)), # c0 + x < c1 -> x < c1 - c0 - ((UPat.var("x") // UPat.cvar("c1")) // UPat.cvar("c2"), lambda x,c1,c2: x//(c1*c2)), # (x//c1)//c2 -> x//(c1*c2) - # ** lt ** - # c0*x 0 and c1.arg > 0 else None), - # c0*x 0 else x<(c.arg*d.arg-(d.arg-1))) if d.arg > 0 else None), - # ** move add/mul consts to end (NOTE: this is still happening before constant folding) ** - ((UPat.var("x") + UPat.cvar("c1")) + UPat.var("y"), lambda x,c1,y: (x+y)+c1), - ((UPat.var("x") * UPat.cvar("c1")) * UPat.var("y"), lambda x,c1,y: (x*y)*c1), - # *** rules from symbolic *** - # unrolled arange div folding - ((UPat() + UPat()//UPat.cvar("d", vec=False)).named("divs"), lambda divs,d: fold_unrolled_divs(divs, d.arg)), - ((UPat() + (UPat()//UPat.cvar("d", vec=False))*UPat.cvar("c")).named("divs"), lambda divs,d,c: fold_unrolled_divs(divs, d.arg, c.arg)), - # generic lt folding - (UPat.var("x", dtypes.sints) 0 - # not x < 1 -> X > 0 - ((UPat.var("x", dtypes.ints)<1).ne(True), lambda x: (newx<1).ne(True) if (newx:=canonicalize_simplex(x)) is not None else None), - # ** div ** - # div folding - ((UPat.var("x")//UPat.cvar("c") + UPat.cvar("a"))//UPat.cvar("d"), lambda x,c,a,d: (x+a*c)//(c*d) - if (x.vmin>=0 and a.vmin>=0) or (x.vmax<=0 and a.vmax<=0) else None), # (x//c+a)//d -> (x+a*c)//(c*d) - (UPat.var("x", dtypes.sints) // UPat.var("y"), lambda x,y: div_and_mod_folding(x,y,Ops.IDIV)), - (UPat.var("x") // UPat.var("d"), lambda x,d: -(x//(-d)) if d.vmax <=0 else None), - (UPat.var("x") // UPat.var("d"), lambda x,d: -((-x)//d) if x.vmax <=0 else None), - ((UPat.var("x", dtypes.sints)+UPat.cvar("c", vec=False)).named("n")//UPat.cvar("d", vec=False), - lambda x,c,n,d: (-(-(c.arg%d.arg + x - (d.arg-1))//d) + c.arg//d.arg) if x.vmax<=0 and n.vmin>=0 and d.arg>0 else None), - # ** mod ** - # mod folding - (UPat.var("x") % UPat.var("y"), lambda x,y: div_and_mod_folding(x,y,Ops.MOD)), - (UPat.var("x") % UPat.var("d"), lambda x,d: -(x%(-d)) if d.vmax <=0 else None), - (UPat.var("x") % UPat.var("d"), lambda x,d: -((-x)%d) if x.vmax <=0 else None), -])+gep_pushing - -symbolic_flat = symbolic+PatternMatcher([ - # ** combine terms (opinionated) ** - (-1 * (UPat.var("x") + UPat.var("y")), lambda x,y: (-x)+(-y)), # -(x+y) -> -x + -y - # (x+y)*c -> x*c+y*c. only for int, float has inf*0=nan issue - ((UPat.var("x", dtypes.ints) + UPat.var("y")) * UPat.cvar("c"), lambda x,y,c: x*c+y*c), -]) - -# ******** we take a small aside to "simplify_valid" to rewrite valids ******** - -def parse_valid(valid:UOp) -> tuple[UOp, bool, int]: - # if it's X <= c, returns X, True, c - # if it's X >= c, returns X, False, c - - # (X < c).ne(True) -> X >= c - if valid.op is Ops.CMPNE and valid.src[1].op is Ops.CONST and valid.src[1].arg == 1 and \ - (s0:=valid.src[0]).op is Ops.CMPLT and s0.src[1].op is Ops.CONST: return s0.src[0], False, s0.src[1].arg - # X < c -> X <= c-1 - if valid.op is Ops.CMPLT and valid.src[1].op is Ops.CONST and dtypes.is_int(valid.src[0].dtype): return valid.src[0], True, valid.src[1].arg-1 - raise ValueError(f"not able to parse {valid=}") - -def uop_given_valid(valid:UOp, uop:UOp) -> UOp|None: - # return None if valid is always False, otherwise the simplified uop (might be the same as input) - - # first, parse valid into {expr: (lower_bound, upper_bound)} - bounds:defaultdict[UOp, list[ConstType|None]] = defaultdict(lambda: [None, None]) - for stmt in split_uop(valid, Ops.AND): - try: expr, is_upper, c = parse_valid(stmt) - except ValueError: return uop # give up if we cannot parse the valid - bounds[expr][int(is_upper)] = c - - # don't simplify any other gates, can lead to OOB, we substitute them back later - uop = uop.substitute((load_subs:={u: UOp(Ops.NOOP, arg=u) for u in uop.toposort() if u.op is Ops.INDEX})) - - # simplify uop given that valid is True - for expr,v in bounds.items(): - v0, v1 = (expr.vmin if v[0] is None else v[0], expr.vmax if v[1] is None else v[1]) - # some expr has lower bound > upper bound -> valid is an empty set and we return None - if v0 > v1: return None - # whole node became a const - if v0 == v1: - uop = uop.substitute({expr:expr.const_like(v0)}).simplify() - continue - # every candidate is a set of contrained UOp based on valid, and if every item in a set simplifies the uop into a same output, we rewrite uop - candidates = [] - if expr.op is Ops.ADD and v0 == 1 and all(u.op in GroupOp.Irreducible for u in split_uop(expr, Ops.ADD)): - # if the constraint is a simplex: X0 + X1 + ... > 0, we can check if all Xi > 0 simplify into the same output - candidates.append([(Xi, UOp.variable("fake", 1, Xi.vmax, Xi.dtype)) for Xi in split_uop(expr, Ops.ADD)]) - # try checking the whole clause - if expr in uop.toposort(): candidates.append([(expr, UOp.variable("fake", v0, v1, expr.dtype))]) - - for candidate in candidates: - # if every branch in candidate gives the same simplified uop, we can rewrite the uop - newuops = [uop.substitute({X:newX}).simplify().substitute({newX:X}).simplify() for X,newX in candidate] - if uop.op is Ops.VECTORIZE and len(uop.src) == 2: - if all_same([uops.src[0] for uops in newuops]): uop = uop.replace(src=(newuops[0].src[0], uop.src[1])) - if all_same([uops.src[1] for uops in newuops]): uop = uop.replace(src=(uop.src[0], newuops[0].src[1])) - elif all_same(newuops): uop = newuops[0] - - # put the loads back in - uop = uop.substitute({v:k for k,v in load_subs.items()}) - return uop - -def _valid_priority(v: UOp, valids:list[UOp]): - # we want valid that's in other valids' parents to be first, so it's more likely the other valids get simplified - try: return sum(-1 if parse_valid(v)[0] in other.toposort() else 0 for other in valids) - except ValueError: return 0 - -def simplify_valid(valid:UOp) -> UOp|None: - ret:list[UOp] = [] - something_changed = False - valids = list(split_uop(valid, Ops.AND)) - for stmt in sorted(valids, key=lambda v: _valid_priority(v, valids)): - # TODO: root cause this and test_simplify_valid_from_div - if stmt.op is Ops.CAST: return None - ret.append(newstmt if ret and (newstmt:=uop_given_valid(functools.reduce(operator.and_, ret), stmt)) is not None else stmt) - if ret[-1] is not stmt: something_changed = True - return functools.reduce(operator.and_, ret) if something_changed else None - -# ***** threefry ***** - -def threefry2x32(x: UOp, key: UOp): - # split x and key from uint64 to two uint32 - x0, x1 = (x & 0xffffffff).cast(dtypes.uint32), ((x // 2**32) & 0xffffffff).cast(dtypes.uint32) - key0, key1 = (key & 0xffffffff).cast(dtypes.uint32), ((key // 2**32) & 0xffffffff).cast(dtypes.uint32) - - rotations = [[13, 15, 26, 6], [17, 29, 16, 24]] - ks = [key1, key0 ^ key1 ^ 0x1BD11BDA, key0] - xr = [x0 + ks[-1], x1 + ks[0]] - for i in range(5): - for r in rotations[i % 2]: xr[0], xr[1] = (x0 := xr[0] + xr[1]), x0 ^ ((xr[1] * 2**r) + (xr[1] // 2**(32 - r))) - xr = [(xr[0] + ks[i % 3]), (xr[1] + ks[(i + 1) % 3] + i + 1)] - - return xr[1].cast(dtypes.uint64) * 2**32 | xr[0].cast(dtypes.uint64) - -# ******** phase 3 is the complete symbolic, and deals with very complex things like loop rewriting and threefry transform ******** - -def reduce_mul_chain(r:UOp): - if r.arg not in {Ops.ADD, Ops.MAX}: return None - if r.dtype != r.src[0].dtype: return None - inside, outside = [], [] - for m in split_uop(r.src[0], Ops.MUL): - m_parents = m.toposort() - if all(r not in m_parents for r in r.src[1:]) and (r.arg != Ops.MAX or m.vmin >= 0): outside.append(m) - else: inside.append(m) - if len(outside) == 0: return None - return r.replace(src=(prod(inside) if len(inside) else r.src[0].const_like(1),)+r.src[1:])*prod(outside) - -# this is symbolic 2.0 -sym = symbolic_flat+PatternMatcher([ - # self ASSIGN is just self - (UPat(Ops.ASSIGN, src=(UPat.var('x'), UPat.var('x'))), lambda x: x), - # VECTORIZE/CONST, VECTORIZE/GEP - (UPat(Ops.VECTORIZE, src=UPat(Ops.CONST), name="vec"), lambda vec: UOp.const(vec.dtype, tuple(x.arg for x in vec.src))), - (UPat(Ops.VECTORIZE, src=UPat(Ops.GEP, src=(UPat.var("x"),)), name="vec"), lambda vec,x: x.gep(tuple(y.arg[0] for y in vec.src))), - # reorder ALU/VECTORIZE - (UPat(GroupOp.ALU, src=(UPat(Ops.VECTORIZE, src=UPat(name='x')), UPat(Ops.VECTORIZE, src=UPat(name='y'))), name='alu'), - lambda x,y,alu: UOp(Ops.VECTORIZE, alu.dtype, (UOp(alu.op, alu.dtype.scalar(), (x,y)),)*alu.dtype.count)), - # VECTORIZE of a single element is just that element - (UPat(Ops.VECTORIZE, src=(UPat(name='x'),)), lambda x: x), - # VECTORIZE void is SINK - (UPat(Ops.VECTORIZE, dtype=dtypes.void, src=UPat(Ops.BARRIER, name='b')), lambda b: b), - (UPat(Ops.VECTORIZE, dtype=dtypes.void, name='x'), lambda x: UOp(Ops.SINK, dtypes.void, x.src)), - # tensor core with a 0 input is acc - (UPat(Ops.WMMA, src=(UPat.const(None, 0.0), UPat.var(), UPat.var("acc"))), lambda acc: acc), - (UPat(Ops.WMMA, src=(UPat.var(), UPat.const(None, 0.0), UPat.var("acc"))), lambda acc: acc), - # threefry + remove longs - (UPat(Ops.THREEFRY, dtype=dtypes.uint64, src=(UPat.var("x"), UPat.var("key"))), threefry2x32), - (UPat.var('x', dtypes.uint32).cast(dtypes.uint64).cast(dtypes.uint32), lambda x: x), # cast there and back is noop (TODO: genericize) - ((UPat.var('x', dtypes.uint64)&0xFFFFFFFF).cast(dtypes.uint32), lambda x: x.cast(dtypes.uint32)), # cast does truncation - (((UPat.var(None, dtypes.uint64)*(1<<32)) | UPat.var('y', dtypes.uint32).cast(dtypes.uint64)).cast(dtypes.uint32), lambda y: y), - (((UPat.var('x', dtypes.uint64)*(1<<32)) | UPat.var(None, dtypes.uint32).cast(dtypes.uint64))//(1<<32), lambda x: x), - # hacks for threefry long removal when padded (TODO: genericize) - (UPat.var('x', dtypes.uint32).cast(dtypes.uint64) * UPat.var('y').where(UPat.const(dtypes.uint64, 1<<32), UPat.const(dtypes.uint64, 0)), - lambda x,y: y.where(x, UOp.const(dtypes.uint32, 0)).cast(dtypes.uint64) * (1<<32)), - ((UPat.var('x', dtypes.uint64)&(UPat.var('y').where(UPat.const(dtypes.uint64, 0xFFFFFFFF), UPat.const(dtypes.uint64, 0)))).cast(dtypes.uint32), - lambda x,y: y.where(x.cast(dtypes.uint32), UOp.const(dtypes.uint32, 0))), - # ** self folding ** - (UPat(Ops.DEFINE_ACC, src=(UPat.var("x"),)), lambda x: x), # a DEFINE_ACC without ranges is a CONST - (UPat(Ops.ASSIGN, src=(UPat.cvar(),UPat.var("x"))), lambda x: x), # an ASSIGN to a const is a NOOP - # x!=0 -> (bool)x - (UPat.var("x")!=0, lambda x: x.cast(dtypes.bool.vec(x.dtype.count))), - # ** where ** - # push cast to branches - (UPat.var("s").where(UPat.var("a"), UPat.var("b")).cast().named("cast"), lambda s,a,b,cast: s.where(a.cast(cast.dtype), b.cast(cast.dtype))), - # a.where(b.where(c, d), d) -> (a & b).where(c, d) - (UPat.var("a").where(UPat.var("b").where(UPat.var("c"), UPat.var("d")), UPat.var("d")), lambda a,b,c,d: (a&b).where(c,d)), - # ** pow ** - ((UPat(Ops.POW, name="p"), lambda p: xpow(*p.src))), - # ** load/store folding ** - (UPat.store(UPat(Ops.INDEX, name="index"), UPat.load(UPat(Ops.INDEX, name="index"))), lambda index: UOp(Ops.NOOP)), - (UPat.store(UPat(Ops.INDEX, name="index"), UPat.var("gate").where(UPat.var("alt"), UPat.load(UPat(Ops.INDEX, name="index")))), - lambda index, gate, alt: UOp.store(index.src[0].index(index.src[1], gate), alt)), - # fold gated LOAD/STORE - (UPat().index(UPat(), UPat.const(dtypes.bool, True)).named("idx"), lambda idx: idx.replace(src=idx.src[0:2])), # remove True - (UPat().index(UPat(), UPat.const(dtypes.bool, False)).named("idx"), lambda idx: idx.const_like(0)), # False -> NULL pointer - (UPat(Ops.LOAD, src=(UPat.const(None, 0),), allow_any_len=True, name="x"), lambda x: x.const_like(0)), # NULL pointer load loads 0 - (UPat(Ops.STORE, src=(UPat.const(None, 0),), allow_any_len=True), lambda: UOp(Ops.NOOP)), # NULL pointer store does nothing - # remove NOOPs from SINK - (UPat(Ops.SINK, name="root"), - lambda root: UOp(Ops.SINK, root.dtype, a, root.arg) if len(a:=tuple(x for x in root.src if x.op is not Ops.NOOP)) != len(root.src) else None), - # remove VECTORIZE from SINK/BARRIER - (UPat(Ops.BARRIER, src=(UPat((Ops.VECTORIZE, Ops.SINK), name='sink'),)), lambda sink: UOp(Ops.BARRIER, dtypes.void, sink.src)), - (UPat(Ops.SINK, name="root"), - lambda root: UOp(Ops.SINK, root.dtype, tuple(flatten(x.src if x.op in {Ops.SINK, Ops.UNROLL} else (x,) for x in root.src)), root.arg) - if any(x.op in {Ops.SINK, Ops.UNROLL} for x in root.src) else None), - ((UPat.var("x") * UPat.var("x")).reciprocal(), lambda x: x.reciprocal()*x.reciprocal()), # 1/(x^c) -> (1/x)^c - ((UPat.var("x") * UPat.var("x") * UPat.var("x")).reciprocal(), lambda x: x.reciprocal()*x.reciprocal()*x.reciprocal()), - (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")), lambda x,d: 1-d), # x*/(1+x) -> 1-1/(1+x) - (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")*UPat.var("y")), lambda x,y,d: y*(1-d)), - (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")+UPat.var("y")), lambda x,y,d: (1-d)+x*y), - # move const multiply after REDUCE (NOTE: the mul chain can do this, but only if it's a same dtype reduce) - ((UPat.var("x")*UPat.cvar("c", vec=False)).reduce(arg=Ops.ADD, name="r", allow_any_len=True), lambda x,c,r: r.replace(src=(x,)+r.src[1:])*c.arg), - # reduce mul chain, move muls after the reduce - (UPat(Ops.MUL).reduce(name="r", allow_any_len=True), reduce_mul_chain), -]) diff --git a/tinygrad/tinygrad/codegen/transcendental.py b/tinygrad/tinygrad/codegen/transcendental.py deleted file mode 100644 index 3fff6e09..00000000 --- a/tinygrad/tinygrad/codegen/transcendental.py +++ /dev/null @@ -1,266 +0,0 @@ -import math -from tinygrad.dtype import dtypes, DType -from tinygrad.helpers import polyN -from tinygrad.uop.ops import UOp - -TRANSCENDENTAL_SUPPORTED_DTYPES = (dtypes.float16, dtypes.float32, dtypes.float64) - -def _lazy_map_numbers(x:UOp, inf:UOp, _inf:UOp, nan:UOp, ratio:UOp): - """replace inf -> inf, -inf -> _inf, nan -> nan, otherwise -> ratio""" - return x.ne(math.inf).where(x.ne(x).where(nan, x.ne(-math.inf).where(ratio, _inf)), inf) - -# *** helper functions for bit manipulation *** -def mantissa_bits(d:DType) -> int: return dtypes.finfo(d.scalar())[1] -def exponent_bias(d:DType) -> int: return {dtypes.float64: 1023, dtypes.float32: 127, dtypes.float16: 15}[d.scalar()] -def exponent_mask(d:DType) -> int: return {dtypes.float64: 2047, dtypes.float32: 255, dtypes.float16: 31}[d.scalar()] - -# **** utils **** -def shr(x:UOp, y:int) -> UOp: return x // (2**y) -def shl(x:UOp, y:int) -> UOp: return x * (2**y) - -def rintk(d:UOp) -> UOp: - """round d:float to int away from 0""" - out_dtype = {dtypes.float64: dtypes.int64, dtypes.float32: dtypes.int32, dtypes.float16: dtypes.int16}[d.dtype.scalar()].vec(d.dtype.vcount) - return (d + (d<0.0).where(d.const_like(-0.5), d.const_like(0.5))).cast(out_dtype) - -def pow2if(q:UOp, float_dtype:DType): - """cast(2^q, float_dtype) where q is any integer in the range of [-126, 127]""" - out_dtype = {dtypes.int64: dtypes.float64, dtypes.int32: dtypes.float32, dtypes.int16: float_dtype.scalar()}[q.dtype.scalar()].vec(q.dtype.vcount) - return shl(q + exponent_bias(out_dtype), mantissa_bits(out_dtype)).bitcast(out_dtype) - -def ilogb2k(d:UOp) -> UOp: - """calculate the integer part of log2(d), where d is normalized fp value in the range of [0, +inf).""" - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - dint = d.bitcast({dtypes.float64: dtypes.int64, dtypes.float32: dtypes.int32, dtypes.float16: dtypes.int16}[d.dtype.scalar()].vec(d.dtype.vcount)) - # -1 <= ilog2bk(d) <= 128 - return (shr(dint, mantissa_bits(d.dtype)) & exponent_mask(d.dtype)) - exponent_bias(d.dtype) - -def ldexp3k(d:UOp, e:UOp) -> UOp: - """d*2^e. e is a number obtained by casting an integer in the range [-127, 127] to a float. d is any float number.""" - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES and e.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - dtype = {dtypes.float64: dtypes.int64, dtypes.float32: dtypes.int32, dtypes.float16: dtypes.int16}[d.dtype.scalar()].vec(d.dtype.count) - m1 = d.bitcast(dtype) - m2 = shl(e.cast(dtype), mantissa_bits(d.dtype)) - return (m1 + m2).bitcast(d.dtype).cast(d.dtype) - -def ldexp2k(d:UOp, e:UOp) -> UOp: - """d*2^e. much faster than ldexp3k but risky. d > 0 and d is not denormal.""" - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES and e.dtype.scalar() in (dtypes.int16, dtypes.int32, dtypes.int64) - return (d * pow2if(shr(e, 1), d.dtype)) * pow2if(e - shr(e, 1), d.dtype) - -def frexp(v:UOp) -> tuple[UOp, UOp]: - """frexp(v) -> (mantissa, exponent) assuming v != 0""" - assert v.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - # m1 = masks for mantissa, m2 = masks to normalize the mantissa. - m1 = {dtypes.float64: 0x000FFFFFFFFFFFFF, dtypes.float32: 0x807FFFFF, dtypes.float16: 0x83FF}[v.dtype.scalar()] - m2 = {dtypes.float64: 0x3FE0000000000000, dtypes.float32: 0x3F000000, dtypes.float16: 0x3800}[v.dtype.scalar()] - bits = v.bitcast({dtypes.float64: dtypes.uint64, dtypes.float32: dtypes.uint32, dtypes.float16: dtypes.uint16}[v.dtype.scalar()].vec(v.dtype.count)) - exponent = shr(bits, mantissa_bits(v.dtype)) & exponent_mask(v.dtype) - # Set the exponent bits appropriately to normalize the mantissa into the range of [0.5, 1.0). - mantissa = ((bits & m1) | m2).bitcast(v.dtype) - exp = exponent - exponent_bias(v.dtype) + 1 - return mantissa, exp - -# *** reduction algorithms for sine *** -def payne_hanek_reduction(d:UOp) -> tuple[UOp, UOp]: - """ - Performs Payne-Hanek Reduction: computes the remainder of `d` modulo pi/2 for the values `d` where - 39800.0 <= d <= +Inf - Returns a tuple of `(r, q)`: - - `r`[d.dtype] is the reminder value corresponding to `round_to_nearest(x % pi/2)`. - - `q`[int32] is an integer, and q % 4 is corresponding to the quadrant of the original angle `d`. - """ - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - # https://stackoverflow.com/questions/30463616/payne-hanek-algorithm-implementation-in-c/30465751#30465751 - # 190 bits of 2/pi for Payne-Hanek style argument reduction - two_over_pi_f = [0x00000000, 0x28be60db, 0x9391054a, 0x7f09d5f4, 0x7d4d3770, 0x36d8a566, 0x4f10e410] - - intermediate_dtype = dtypes.float32.vec(d.dtype.count) if d.dtype.base.scalar() == dtypes.float16 else d.dtype - - f, e = frexp(d) - ia = (f.cast(intermediate_dtype) * 4.294967296e9).cast_vec(dtypes.uint64) - # extract 96 relevant bits of 2/pi based on magnitude of argument - i = shr(e.cast_vec(dtypes.uint64), 5) - e = e.cast_vec(dtypes.int32) & 31 - offset = 32 - e - - def _take(an:UOp, offset:int, count:int=0) -> UOp: - """an = two_over_pi_f[i+offset]""" - if count+offset < len(two_over_pi_f) - 1: - an = i.ne(count).where(_take(an, offset, count=count+1), an.const_like(two_over_pi_f[count+offset])) - return an - def _shl_lazy(x, y): return (x.cast_vec(dtypes.uint64) * pow2if(y, d.dtype).cast_vec(dtypes.uint64)).cast_vec(dtypes.uint32) - def _shr_lazy(x, y): return (x.cast_vec(dtypes.uint64) // pow2if(y, d.dtype).cast_vec(dtypes.uint64)).cast_vec(dtypes.uint32) - - a = [_take(UOp.const(dtypes.uint32.vec(d.dtype.count), 0), i) for i in range(4)] - # (two_over_pi_f[Int(i) + n] << e) | (two_over_pi_f[Int(i) + n+1] >> (nbits - e)) - # Note: e >= 1 for all numbers d >= 1.0. assume e != 0 - hi = _shl_lazy(a[0], e) | _shr_lazy(a[1], offset) - mi = _shl_lazy(a[1], e) | _shr_lazy(a[2], offset) - lo = _shl_lazy(a[2], e) | _shr_lazy(a[3], offset) - - def _hp_mul(x:UOp, y:UOp) -> UOp: return x.cast_vec(dtypes.uint64) * y.cast_vec(dtypes.uint64) - # compute x * 2/pi - p = shl(_hp_mul(ia, hi), 32) + _hp_mul(ia, mi) + shr(_hp_mul(ia, lo), 32) - - # round quotient to nearest - q = shr(p, 62).cast_vec(dtypes.int32) - p = p & 0x3fffffffffffffff - r = (p.cast(intermediate_dtype) * (3.4061215800865545e-19)).cast(d.dtype) - - # if fraction >= 0.5, r -= pi/2, q += 1 - return (f<0.5).where(r, r - math.pi/2), (f<0.5).where(q, q + 1) - -def cody_waite_reduction(d:UOp) -> tuple[UOp, UOp]: - """ - Performs Cody-Waite Reduction: computes the reminder of `d` modulo pi/2 for the values `d` where - 0 <= abs(d) <= 39800.0 - Returns a tuple of `(r, q)`, where the output format is the same as that of `payne_hanek_reduction`. - """ - def _reduce_d(x:UOp, q:UOp): - # https://github.com/shibatch/sleef/blob/4e08851f59fc2b545f9c393c6a23dfd311a26308/src/libm/sleefdp.c#L789-L823 - if x.dtype.scalar() == dtypes.float64: - # https://github.com/shibatch/sleef/blob/f6d8a841fbfddd26ce712834d4da220cd76048fb/src/common/misc.h#L77 - PI_A, PI_B, PI_C, PI_D = 3.1415926218032836914, 3.1786509424591713469e-08, 1.2246467864107188502e-16, 1.2736634327021899816e-24 - d = qdh * -PI_A + x - d = q * -PI_A + d - d = qdh * -PI_B + d - d = q * -PI_B + d - d = qdh * -PI_C + d - d = q * -PI_C + d - d = (qdh + q) * -PI_D + d - elif x.dtype.scalar() == dtypes.float16: - # [FIXME] when reducing `d`, FP16 needs FP32 precision to achieve 1.0 ULP precision. - d = _reduce_d(x.cast_vec(dtypes.float32), q.cast_vec(dtypes.float32)).cast_vec(dtypes.float16) - else: - # https://github.com/shibatch/sleef/blob/4e08851f59fc2b545f9c393c6a23dfd311a26308/src/libm/sleefsp.c#L464-L503 - d = q * -3.1414794921875 + x - d = q * -0.00011315941810607910156 + d - d = q * -1.9841872589410058936e-09 + d - d = q * -1.2154201256553420762e-10 + d - return d - - m_1_pi = 0.318309886183790671537767526745028724 - qdh = (d * (m_1_pi / 2.0**24)).cast_vec(dtypes.int64).cast(d.dtype) * (2.0**24) - quadrant = rintk(d * m_1_pi -qdh) if d.dtype.base.scalar() == dtypes.float64 else rintk(d * m_1_pi) - return _reduce_d(d, quadrant.cast(d.dtype)), quadrant.cast_vec(dtypes.int32) - -# *** approximate sine on small angle. *** -def trig_poly(d:UOp, coeff32, coeff64): return d * (polyN(d*d, coeff64) if d.dtype.scalar() == dtypes.float64 else polyN(d*d, coeff32)) -# approximate sine on [-pi/2, pi/2] -def sin_poly(d:UOp) -> UOp: - return trig_poly(d, [2.6083159809786593541503e-06, -0.0001981069071916863322258, 0.00833307858556509017944336, -0.166666597127914428710938, 1.0], - [-7.97255955009037868891952e-18, 2.81009972710863200091251e-15, -7.64712219118158833288484e-13, 1.60590430605664501629054e-10, - -2.50521083763502045810755e-08, 2.75573192239198747630416e-06, -0.000198412698412696162806809, 0.00833333333333332974823815, - -0.166666666666666657414808, 1.0]) - -def _ifand(q:UOp, n:int): return (q & n).ne(0) - -def sin_poly_small(d:UOp, q:UOp) -> UOp: - r = sin_poly(d) - return r * _ifand(q, 1).where(r.const_like(-1), r.const_like(1)) - -def sin_poly_large(d:UOp, q:UOp) -> UOp: - r = sin_poly(d + _ifand(q, 1).where(d.const_like(math.pi / 2), d.const_like(0))) - return r * _ifand(q, 2).where(r.const_like(-1), r.const_like(1)) - -# *** toplevel functions for xsin/xlog2/xexp2 *** - -def xsin(d:UOp, fast:bool=False, switch_over:float=30.0) -> UOp: - """ - Implements a 1.0 ULP approximation for Ops.SIN. - - fast=True assumes x <= switch_over. - - switch_over is the threshold for switching to payne_hanek_reduction. - """ - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - # mask +-inf/nan as zero - x = _lazy_map_numbers(d, d.const_like(0.0), d.const_like(0.0), d.const_like(0.0), d) - # x_sign = sign(x) - x_sign = x.ne(0).where((x<0).where(x.const_like(-1), x.const_like(1)), x.const_like(0)) - x_abs = x * x_sign - r, q = (cody_waite_reduction if fast else payne_hanek_reduction)(x_abs) - if fast: result = sin_poly_small(r, q) - else: - # Payne Hanek Reduction assumes abs(x) >= pi/4, so for smaller values, use cody_waite_reduction. - r_small, q_small = cody_waite_reduction(x_abs) - result = (x_abs UOp: - """ - Implements a 1.0 ULP approximation for Ops.EXP2 - - Paper: https://arxiv.org/pdf/2001.09258 - """ - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - # mask +=inf/nan as zero. - x = _lazy_map_numbers(d, d.const_like(0.0), d.const_like(0.0), d.const_like(0.0), d) - q = rintk(x) - # s = d - round(d) - s = x - q.cast(x.dtype) - # a polynomial approximation with 13 non-zero terms in the range of [−(log 2)/2,(log 2)/2]. - if d.dtype.scalar() == dtypes.float64: - u = polyN(s, [0.4434359082926529454e-9, 0.7073164598085707425e-8, 0.1017819260921760451e-6, 0.1321543872511327615e-5, 0.1525273353517584730e-4, - 0.1540353045101147808e-3, 0.1333355814670499073e-2, 0.9618129107597600536e-2, 0.5550410866482046596e-1, 0.2402265069591012214e+0, - 0.6931471805599452862e+0, 0.1000000000000000000e+1]) - else: u = polyN(s, [0.1535920892e-3, 0.1339262701e-2, 0.9618384764e-2, 0.5550347269e-1, 0.2402264476e+0, 0.6931471825e+0, 1.0]) - u = ldexp2k(u, q) # u*2^q - upper, lower = {dtypes.float64: (1024, -2000), dtypes.float32: (128, -150), dtypes.float16: (23, -22)}[d.dtype.scalar()] - # Replace x >= upper with +inf - u = (d >= upper).where(d.const_like(math.inf), u) - # Replace x < lower with zero. - u = (d UOp: - """ - Implements a 1.0 ULP approximation for Ops.LOG2 - Paper: https://arxiv.org/pdf/2001.09258 5.5 - """ - assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES - # TODO: float16 denormal need float32 to achieve precision - if d.dtype.scalar() == dtypes.float16: return xlog2(d.cast_vec(dtypes.float32)).cast_vec(dtypes.float16) - FLT_MIN = d.const_like(1e-6 if d.dtype.scalar() == dtypes.float16 else 1e-4) - is_denormal = d UOp: - # start with b ** e = exp2(e * log2(b)) - ret = (base < 0).where(-base, base).log2().mul(exponent).exp2() - # negative base adjustment: nan for non-integer exponent and -1 for odd exponent - non_int = exponent != exponent.cast_vec(dtypes.int32).cast(exponent.dtype) - adj = non_int.where(ret.const_like(math.nan), - (exponent < 0).where(-exponent, exponent).cast_vec(dtypes.int32).mod(2).cast_vec(dtypes.bool).where(ret.const_like(-1), ret.const_like(1))) - # fix 0 ** 0 = 1 - return (base.eq(0) & exponent.eq(0)).where(ret.const_like(1), ret * (base < 0).where(adj, ret.const_like(1))) diff --git a/tinygrad/tinygrad/device.py b/tinygrad/tinygrad/device.py deleted file mode 100644 index e84e803c..00000000 --- a/tinygrad/tinygrad/device.py +++ /dev/null @@ -1,407 +0,0 @@ -from __future__ import annotations -from dataclasses import dataclass, replace -from collections import defaultdict -from typing import Optional, Any, Generic, TypeVar, Iterator, Generator -import importlib, inspect, functools, pathlib, os, ctypes, ctypes.util, platform, contextlib, sys, re, atexit, pickle, decimal, time -from tinygrad.helpers import CI, OSX, LRU, getenv, diskcache_get, diskcache_put, DEBUG, GlobalCounters, flat_mv, from_mv, PROFILE, temp, mv_address, \ - cpu_time_execution, colored, Context, round_up, DISABLE_COMPILER_CACHE, ALLOW_DEVICE_USAGE -from tinygrad.dtype import DType, ImageDType, PtrDType, dtypes, _to_np_dtype -from tinygrad.renderer import Renderer - -# **************** Device **************** - -ALL_DEVICES = ["METAL", "AMD", "NV", "CUDA", "QCOM", "GPU", "CPU", "LLVM", "DSP", "WEBGPU"] -class _Device: - def __init__(self) -> None: - self._devices = [x.stem[len("ops_"):].upper() for x in (pathlib.Path(__file__).parent/"runtime").iterdir() if x.stem.startswith("ops_")] - self._opened_devices:set[str] = set() - @functools.cache # this class is a singleton, pylint: disable=method-cache-max-size-none - def _canonicalize(self, device:str) -> str: return re.sub(r":0$", "", (d:=device.split(":", 1)[0].upper()) + device[len(d):]) - # NOTE: you can't cache canonicalize in case Device.DEFAULT changes - def canonicalize(self, device:Optional[str]) -> str: return self._canonicalize(device if device is not None else Device.DEFAULT) - def __getitem__(self, ix:str) -> Compiled: return self.__get_canonicalized_item(self.canonicalize(ix)) - @functools.cache # this class is a singleton, pylint: disable=method-cache-max-size-none - def __get_canonicalized_item(self, ix:str) -> Compiled: - assert ALLOW_DEVICE_USAGE or ix.split(":")[0] in ["DISK", "NPY", "PYTHON"], f"usage of device {ix} disallowed" - x = ix.split(":")[0].lower() - ret = [cls for cname, cls in inspect.getmembers(importlib.import_module(f'tinygrad.runtime.ops_{x}')) \ - if (cname.lower() == x + "device")][0](ix) - if DEBUG >= 1: print(f"opened device {ix} from pid:{os.getpid()}") - self._opened_devices.add(ix) - return ret - @property - def default(self) -> Compiled: return self[self.DEFAULT] - def get_available_devices(self) -> Iterator[str]: - for device in ALL_DEVICES: - with contextlib.suppress(Exception): yield self[device].device - @functools.cached_property - def DEFAULT(self) -> str: - from_env = [d for d in self._devices if d not in ["DISK", "NPY"] and getenv(d) == 1] - assert len(from_env) < 2, f"multiple devices set in env: {from_env}" - if len(from_env) == 1: return from_env[0] - try: - device = next(self.get_available_devices()) - os.environ[device] = "1" # we set this in environment for spawned children - return device - except StopIteration as exc: raise RuntimeError("no usable devices") from exc -Device = _Device() -atexit.register(lambda: [Device[dn].finalize() for dn in Device._opened_devices]) - -# **************** Profile **************** - -class ProfileEvent: pass - -@dataclass(frozen=True) -class ProfileDeviceEvent(ProfileEvent): - device:str; comp_tdiff:decimal.Decimal=decimal.Decimal(0); copy_tdiff:decimal.Decimal=decimal.Decimal(0) # noqa: E702 - -@dataclass(frozen=True) -class ProfileRangeEvent(ProfileEvent): device:str; name:str; st:decimal.Decimal; en:decimal.Decimal; is_copy:bool # noqa: E702 - -@dataclass(frozen=True) -class ProfileProgramEvent(ProfileEvent): device:str; name:str; lib:bytes|None; base:int|None # noqa: E702 - -@dataclass(frozen=True) -class ProfileGraphEntry: device:str; name:str; st_id:int; en_id:int; is_copy:bool # noqa: E702 - -@dataclass(frozen=True) -class ProfileGraphEvent(ProfileEvent): ents:list[ProfileGraphEntry]; deps:list[list[int]]; sigs:list[decimal.Decimal] # noqa: E702 - -@dataclass -class ProfileResult: st:Optional[int]=None; en:Optional[int]=None # noqa: E702 - -@contextlib.contextmanager -def cpu_profile(name, device="CPU", is_copy=False, display=True) -> Generator[ProfileResult, None, None]: - yield (res:=ProfileResult(st:=time.perf_counter_ns())) - res.en = en = time.perf_counter_ns() - if PROFILE and display: - Compiled.profile_events += [ProfileRangeEvent(device, name, decimal.Decimal(st) / 1000, decimal.Decimal(en) / 1000, is_copy=is_copy)] - -# **************** Buffer + Allocators **************** - - -@dataclass(frozen=True, eq=True) -class BufferSpec: - # TODO: move device, size, dtype here? - image: Optional[ImageDType] = None - uncached: bool = False - cpu_access: bool = False - host: bool = False - nolru: bool = False - external_ptr: Optional[int] = None - -class MultiBuffer: - def __init__(self, device:tuple[str, ...], size:int, dtype:DType): - self.bufs = [Buffer(d, size, dtype) for d in device] - @property - def size(self): return self.bufs[0].size - @property - def dtype(self): return self.bufs[0].dtype - def ref(self, cnt): - for b in self.bufs: b.ref(cnt) - return self - def is_allocated(self): return all(x.is_allocated() for x in self.bufs) - def __repr__(self): return f"" - -class Buffer: - def __init__(self, device:str, size:int, dtype:DType, opaque:Any=None, options:Optional[BufferSpec]=None, initial_value:Optional[bytes]=None, - lb_refcount=0, base:Optional[Buffer]=None, offset:int=0, preallocate=False): - if isinstance(dtype, ImageDType): options = BufferSpec(image=dtype) # TODO: image hack shouldn't be here. where should it be? - else: assert isinstance(dtype, DType) and not isinstance(dtype, PtrDType) - self.device, self.size, self.dtype, self.options, self.offset, self.allocated_views = device, size, dtype, options, offset, 0 - if base is None: - assert offset == 0, "base buffers can't have offset" - self._base = None - self._lb_refcount = lb_refcount - if opaque is not None: self.allocate(opaque) - if initial_value is not None: - self.allocate() - self.copyin(memoryview(initial_value)) - else: - assert base._base is None, "base can't have a base" - assert device == base.device, "base must have the same device" - self._base = base - if preallocate: self.allocate() - @property - def base(self) -> Buffer: return self._base if self._base is not None else self - @property - def lb_refcount(self): return self.base._lb_refcount - def ref(self, cnt): - self.base._lb_refcount += cnt - return self - def is_allocated(self) -> bool: return hasattr(self, '_buf') - def ensure_allocated(self) -> Buffer: return self.allocate() if not self.is_allocated() else self - def allocate(self, opaque=None, external_ptr=None) -> Buffer: - assert not self.is_allocated(), "can't allocate already allocated buffer" - if DEBUG >= 7: print(f"buffer: allocate {self.nbytes} bytes on {self.device}") - if (mbs:=getenv("MAX_BUFFER_SIZE", 0)) > 0 and self.size > mbs: raise RuntimeError(f"buffer of size {self.size/1e6:.2f}M is too large") - self.allocator:Allocator = Device[self.device].allocator - if external_ptr is not None: - self.options = replace(self.options, external_ptr=external_ptr) if self.options else BufferSpec(external_ptr=external_ptr) - if self._base is not None: - self._base.ensure_allocated() - self._base.allocated_views += 1 - assert hasattr(self.allocator, "_offset"), "offset function required for view" - self._buf: Any = self.allocator._offset(self.base._buf, self.nbytes, self.offset) - else: - self._buf = opaque if opaque is not None else self.allocator.alloc(self.nbytes, self.options) - if not self.device.startswith("DISK"): GlobalCounters.mem_used += self.nbytes - return self - def deallocate(self): - assert self.is_allocated(), "buffer must be allocated to deallocate" - if DEBUG is not None and DEBUG >= 7: print(f"buffer: deallocate {self.nbytes} bytes on {self.device}") - if self._base is None and (self.options is None or self.options.external_ptr is None): - if GlobalCounters is not None and not self.device.startswith("DISK"): GlobalCounters.mem_used -= self.nbytes - self.allocator.free(self._buf, self.nbytes, self.options) - elif self._base is not None: self._base.allocated_views -= 1 - del self._buf - def __reduce__(self): - buf = None - if self._base is not None: - return self.__class__, (self.device, self.size, self.dtype, None, None, None, 0, self.base, self.offset, self.is_allocated()) - if self.device == "NPY": return self.__class__, (self.device, self.size, self.dtype, self._buf, self.options, None, self.lb_refcount) - if self.is_allocated(): - buf = bytearray(self.nbytes) - self.copyout(memoryview(buf)) - return self.__class__, (self.device, self.size, self.dtype, None, self.options, buf, self.lb_refcount) - @property - def nbytes(self): return self.size*self.dtype.itemsize - def __del__(self): (not self.is_allocated()) or self.deallocate() - def __repr__(self): - return f"" - def as_buffer(self, allow_zero_copy=False, force_zero_copy=False) -> memoryview: - # zero copy with as_buffer (disabled by default due to use after free) - if (force_zero_copy or allow_zero_copy) and hasattr(self.allocator, '_as_buffer') and (self.options is None or self.options.image is None): - return self.allocator._as_buffer(self._buf) - assert not force_zero_copy, "force zero copy was passed, but copy is required" - return self.copyout(memoryview(bytearray(self.nbytes))) - def as_typed_buffer(self, shape=None, allow_zero_copy=False, force_zero_copy=False) -> memoryview: - assert self.dtype.base.fmt is not None, f"no fmt dtype for {self.dtype.base}" - assert self.dtype.base.fmt != "e" or sys.version_info >= (3, 12) - return self.as_buffer(allow_zero_copy, force_zero_copy).cast(self.dtype.base.fmt, shape if shape is not None else (self.size,)) - def numpy(self) -> 'np.ndarray': # type: ignore [name-defined] # noqa: F821 - import numpy as np - assert _to_np_dtype(self.dtype.base) is not None, f"no np dtype for {self.dtype.base}" - return np.frombuffer(self.as_buffer(), dtype=_to_np_dtype(self.dtype.base)) - def copyin(self, mv:memoryview): - mv = flat_mv(mv) - assert len(mv) == self.nbytes, f"size mismatch, {len(mv)=} != {self.dtype=} {self.size=}" - assert self.is_allocated(), "can't copyin to unallocated buffer" - self.allocator._copyin(self._buf, mv) - return self - def copyout(self, mv:memoryview) -> memoryview: - mv = flat_mv(mv) - assert len(mv) == self.nbytes, f"size mismatch, {len(mv)=} != {self.dtype=} {self.size=}" - assert self.is_allocated(), "can't copyout unallocated buffer" - self.allocator._copyout(mv, self._buf) - return mv - def view(self, size:int, dtype:DType, offset:int) -> Buffer: - assert offset < self.nbytes, "offset must be less than nbytes" - if self._base is not None: return Buffer(self.device, size, dtype, base=self._base, offset=self.offset+offset) - return Buffer(self.device, size, dtype, base=self, offset=offset) - -DeviceType = TypeVar('DeviceType', bound='Compiled') - -# TODO: size, dest, src are the same type. can we enforce this? -class Allocator(Generic[DeviceType]): - def __init__(self, dev:DeviceType): - self.dev: DeviceType = dev - self.default_buffer_spec: BufferSpec = BufferSpec() - # overridden in LRUAllocator - def alloc(self, size:int, options:Optional[BufferSpec]=None): - assert size > 0, f"alloc size must be positive, getting {size}" - return self._alloc(size, options if options is not None else self.default_buffer_spec) - def free(self, opaque, size:int, options:Optional[BufferSpec]=None): - self._free(opaque, options if options is not None else self.default_buffer_spec) - - # implemented by the runtime - def _alloc(self, size:int, options:BufferSpec): raise NotImplementedError("need alloc") - def _free(self, opaque, options:BufferSpec): pass # if opaque is a Python object, you don't need a free - def _copyin(self, dest, src:memoryview): raise NotImplementedError("need copyin") - def _copyout(self, dest:memoryview, src): raise NotImplementedError("need copyout") - # def _as_buffer(self, src) -> memoryview: - # def _offset(self, buf, size:int, offset:int): - # def _transfer(self, dest, src, sz:int, src_dev, dest_dev): - -class LRUAllocator(Allocator, Generic[DeviceType]): - """ - The LRU Allocator is responsible for caching buffers. - It ensures that buffers are not freed until it is absolutely necessary, optimizing performance. - """ - def __init__(self, dev:DeviceType): - self.cache: dict[tuple[int, Optional[BufferSpec]], Any] = defaultdict(list) - super().__init__(dev) - def alloc(self, size:int, options:Optional[BufferSpec]=None): - if len(c := self.cache[(size, options)]): return c.pop() - try: return super().alloc(size, options) - except (RuntimeError, MemoryError): - self.free_cache() - return super().alloc(size, options) - def free_cache(self): - for (sz,options),opaques in self.cache.items(): - for opaque in opaques: super().free(opaque, sz, options) - opaques.clear() - def free(self, opaque:Any, size:int, options:Optional[BufferSpec]=None): - if LRU and (options is None or not options.nolru): self.cache[(size, options)].append(opaque) - else: super().free(opaque, size, options) - -class _MallocAllocator(LRUAllocator['Compiled']): - def _alloc(self, size:int, options:BufferSpec): - # must be aligned to 0x20 for 256-bit ymm registers - # TODO: investigate if this is the cause of nondeterminism in speed - alignment = 0x1000 if size >= 0x1000 else 0x20 - return (ctypes.c_uint8 * size).from_address(options.external_ptr) if options.external_ptr else self._alloc_aligned(size, alignment) - def _alloc_aligned(self, size:int, alignment:int): - buffer = (ctypes.c_uint8 * (size + alignment))() - offset = round_up(ctypes.addressof(buffer), alignment) - ctypes.addressof(buffer) - return (ctypes.c_uint8 * size).from_buffer(buffer, offset) - def _as_buffer(self, src) -> memoryview: return flat_mv(memoryview(src)) - def _copyin(self, dest, src:memoryview): ctypes.memmove(dest, from_mv(src), len(src)) - def _copyout(self, dest:memoryview, src): ctypes.memmove(from_mv(dest), src, len(dest)) - def _offset(self, buf, size:int, offset:int): return from_mv(self._as_buffer(buf)[offset:offset+size]) - -MallocAllocator = _MallocAllocator(None) # type: ignore - -# NOTE: MAP_JIT is added to mmap module in python 3.13 -MAP_JIT = 0x0800 - -# CPUProgram is a jit/shellcode program that can be just mmapped and jumped to -class CPUProgram: - rt_lib = ctypes.CDLL(ctypes.util.find_library('System' if OSX else 'kernel32') if OSX or sys.platform == "win32" else 'libgcc_s.so.1') - atomic_lib = ctypes.CDLL(ctypes.util.find_library('atomic')) if sys.platform == "linux" else None - - def __init__(self, name:str, lib:bytes): - if sys.platform == "win32": - PAGE_EXECUTE_READWRITE = 0x40 - MEM_COMMIT = 0x1000 - MEM_RESERVE = 0x2000 - ctypes.windll.kernel32.VirtualAlloc.restype = ctypes.c_void_p - self.mem = ctypes.windll.kernel32.VirtualAlloc(ctypes.c_void_p(0), ctypes.c_size_t(len(lib)), MEM_COMMIT | MEM_RESERVE, PAGE_EXECUTE_READWRITE) - ctypes.memmove(self.mem, lib, len(lib)) - ctypes.windll.kernel32.GetCurrentProcess.restype = ctypes.c_void_p - proc = ctypes.windll.kernel32.GetCurrentProcess() - ctypes.windll.kernel32.FlushInstructionCache(ctypes.c_void_p(proc), ctypes.c_void_p(self.mem), ctypes.c_size_t(len(lib))) - self.fxn = ctypes.CFUNCTYPE(None)(self.mem) - else: - from mmap import mmap, PROT_READ, PROT_WRITE, PROT_EXEC, MAP_ANON, MAP_PRIVATE - # On apple silicon with SPRR enabled (it always is in macos) RWX pages are unrepresentable: https://blog.svenpeter.dev/posts/m1_sprr_gxf/ - # MAP_JIT allows us to easily flip pages from RW- to R-X and vice versa. It is a noop on intel cpus. (man pthread_jit_write_protect_np) - self.mem = mmap(-1, len(lib), MAP_ANON | MAP_PRIVATE | (MAP_JIT if OSX else 0), PROT_READ | PROT_WRITE | PROT_EXEC) - - if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(False) - self.mem.write(lib) - if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(True) - - # __clear_cache isn't a normal libc function, but a compiler support routine found in libgcc_s for gcc and compiler-rt for clang. - # libgcc_s comes as shared library but compiler-rt is only a bunch of static library archives which we can't directly load, but fortunately - # it somehow found its way into libSystem on macos (likely because it used __builtin_clear_cache) and libgcc_s is ~always present on linux - # Using ["name"] instead of .name because otherwise name is getting mangled: https://docs.python.org/3.12/reference/expressions.html#index-5 - CPUProgram.rt_lib["__clear_cache"](ctypes.c_void_p(mv_address(self.mem)), ctypes.c_void_p(mv_address(self.mem) + len(lib))) - - self.fxn = ctypes.CFUNCTYPE(None)(mv_address(self.mem)) - - def __call__(self, *bufs, vals=(), wait=False): - args = list(bufs) + list(vals) - # NOTE: replace this by --target={host's triple}-elf in clang args once we only support macos sequoia and later. - # Apple relaxes abi requirement for stack arguments to always be at least 8 byte aligned on arm64 - # https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms - # This hack is required because clang/llvm bug doesn't allow us to just use {host's triple}+'-elf' (relocation failures) - # The bug was fixed in https://github.com/llvm/llvm-project/commit/454cc36630296262cdb6360b60f90a64a97f7f1a but was only backported to xcode 16+ - if platform.machine() == "arm64" and OSX: args = args[:8] + [ctypes.c_int64(a) if isinstance(a, int) else a for a in args[8:]] - return cpu_time_execution(lambda: self.fxn(*args), enable=wait) - - def __del__(self): - if sys.platform == 'win32': ctypes.windll.kernel32.VirtualFree(ctypes.c_void_p(self.mem), ctypes.c_size_t(0), 0x8000) #0x8000 - MEM_RELEASE - -# **************** for Compiled Devices **************** - -class CompileError(Exception): pass - -class Compiler: - def __init__(self, cachekey:Optional[str]=None): self.cachekey = None if DISABLE_COMPILER_CACHE else cachekey - def compile(self, src:str) -> bytes: return src.encode() # NOTE: empty compiler is the default - def compile_cached(self, src:str) -> bytes: - if self.cachekey is None or (lib := diskcache_get(self.cachekey, src)) is None: - assert not getenv("ASSERT_COMPILE"), f"tried to compile with ASSERT_COMPILE set\n{src}" - lib = self.compile(src) - if self.cachekey is not None: diskcache_put(self.cachekey, src, lib) - return lib - def disassemble(self, lib:bytes): pass - -class Compiled: - profile_events:list[ProfileEvent] = [ProfileDeviceEvent("CPU")] # NOTE: CPU is the default device. - - def __init__(self, device:str, allocator:Allocator, renderer:Optional[Renderer], compiler:Optional[Compiler], runtime, graph=None): - self.device, self.allocator, self.compiler, self.runtime, self.graph = device, allocator, compiler or Compiler(), runtime, graph - self.renderer = renderer or Renderer() - def synchronize(self): - """ - Synchronize all pending operations on the device. - - This method ensures that all previously queued operations on the device have been completed before proceeding. - """ - # override this in your device implementation - def _at_profile_finalize(self): - """ - Called at the end of profiling to allow the device to finalize any profiling. - """ - # override this in your device implementation - def finalize(self): - """ - Called at the end of process lifetime to allow the device to finalize. - """ - # override this in your device implementation - -# TODO: move this to each Device -def is_dtype_supported(dtype:DType, device:Optional[str]=None) -> bool: - if device is None: device = Device.DEFAULT - if dtype == dtypes.bfloat16: - if device == "METAL": return not CI - if device in {"CUDA", "NV"}: return not CI and not getenv("PTX") - if device in {"CPU", "LLVM"}: return not CI and platform.machine() in {"arm", "arm64", "aarch64", "x86_64", "amd64"} - return device == "AMD" - if dtype in dtypes.fp8s: - # not supported yet - in progress - return False - if device == "WEBGPU": return dtype in [dtypes.bool, dtypes.char, dtypes.uchar, dtypes.short, - dtypes.ushort, dtypes.float, dtypes.int32, dtypes.uint32, dtypes.half] - # for CI GPU and OSX, cl_khr_fp16 isn't supported - # for CI LLVM, it segfaults because it can't link to the casting function - # CI CUDA architecture is sm_35 but we need at least sm_70 to run fp16 ALUs - # PYTHON supports half memoryview in 3.12+ https://github.com/python/cpython/issues/90751 - if dtype == dtypes.half: - if device == "GPU": return not CI and not OSX - if device in ["CUDA", "NV"]: return not CI - if device == "LLVM": return OSX - if device == "PYTHON": return sys.version_info >= (3, 12) - if dtype == dtypes.float64: return device != "METAL" and not (OSX and device == "GPU") - return True - -if PROFILE: - @atexit.register - def finalize_profile(): - devs = [Device[d] for d in Device._opened_devices] - for dev in devs: dev.synchronize() - for dev in devs: dev._at_profile_finalize() - - with open(fn:=temp("profile.pkl", append_user=True), "wb") as f: pickle.dump(Compiled.profile_events, f) - - if not getenv("SQTT", 0): - from tinygrad.uop.ops import launch_viz - launch_viz("PROFILE", fn) - -if __name__ == "__main__": - for device in ALL_DEVICES: - try: - _ = Device[device].device - try: - from tinygrad import Tensor - with Context(CACHELEVEL=0): test = (Tensor([1,2,3], device=device) * 2).tolist() - if test != [2,4,6]: raise ValueError(f"got {test} instead of [2, 4, 6]") - result = colored("PASS", "green") - except Exception as e: - result = f"{colored('FAIL', 'yellow')} {e}" - except Exception as e: - result = f"{colored('FAIL', 'red')} {e}" - print(f"{'*' if device == Device.DEFAULT else ' '} {device:10s}: {result}") diff --git a/tinygrad/tinygrad/dtype.py b/tinygrad/tinygrad/dtype.py deleted file mode 100644 index d7fe21aa..00000000 --- a/tinygrad/tinygrad/dtype.py +++ /dev/null @@ -1,297 +0,0 @@ -from __future__ import annotations -from typing import Final, Optional, ClassVar, Union, Callable, Literal -import math, struct, ctypes, functools -from dataclasses import dataclass, fields -from tinygrad.helpers import getenv, prod - -ConstType = Union[float, int, bool] - -FmtStr = Literal['?', 'b', 'B', 'h', 'H', 'i', 'I', 'q', 'Q', 'e', 'f', 'd'] - -# all DTypes should only be created once -class DTypeMetaClass(type): - dcache: dict[tuple, DType] = {} - def __call__(cls, *args, **kwargs): - if (ret:=DTypeMetaClass.dcache.get(args, None)) is not None: return ret - DTypeMetaClass.dcache[args] = ret = super().__call__(*args) - return ret - -@dataclass(frozen=True, eq=False) -class DType(metaclass=DTypeMetaClass): - priority: int # this determines when things get upcasted - itemsize: int - name: str - fmt: Optional[FmtStr] - count: int - _scalar: Optional[DType] - @staticmethod - def new(priority:int, itemsize:int, name:str, fmt:Optional[FmtStr]): return DType(priority, itemsize, name, fmt, 1, None) - def __reduce__(self): return type(self), tuple(getattr(self, f.name) for f in fields(self)) - def __repr__(self): return f"dtypes.{INVERSE_DTYPES_DICT[self.scalar().name]}"+(f".vec({self.count})" if self.count > 1 else "") - def __lt__(self, o:DType): return (self.priority, self.itemsize, self.name, self.fmt, self.count) < (o.priority, o.itemsize, o.name, o.fmt, o.count) - @property - def base(self): return self - @property - def vcount(self): return self.count - @functools.cache # pylint: disable=method-cache-max-size-none - def vec(self, sz:int) -> DType: - assert self.count == 1, f"can't vectorize {self} with size {sz}" - if sz == 1 or self == dtypes.void: return self # void doesn't vectorize, and sz=1 is scalar - return DType(self.priority, self.itemsize*sz, f"{INVERSE_DTYPES_DICT[self.name]}{sz}", None, sz, self) - def ptr(self, size=-1, local=False) -> PtrDType: - return PtrDType(self.priority, self.itemsize, self.name, self.fmt, self.count, None, self, local, 1, size) - def scalar(self) -> DType: return self._scalar if self._scalar is not None else self - def nbytes(self): raise RuntimeError("only ptr types have nbytes") - @property - def min(self): return dtypes.min(self) - @property - def max(self): return dtypes.max(self) - -@dataclass(frozen=True, eq=False) -class PtrDType(DType): - _base: DType - local: bool - v: int - size: int = -1 # -1 is unlimited size - @property - def base(self): return self._base - @functools.cache # pylint: disable=method-cache-max-size-none - def vec(self, sz:int) -> DType: - assert self.v == 1, f"can't vectorize ptr {self} with size {sz}" - if sz == 1: return self # sz=1 is a scalar - if isinstance(self, ImageDType): - return ImageDType(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.local, sz, self.size, self.shape) - return type(self)(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.local, sz, self.size) - def ptr(self, size=-1, local=False): raise RuntimeError("can't make a pointer from a pointer") - def nbytes(self) -> int: - if self.size == -1: return 0 # TODO: this should be an exception - return self.size*self.itemsize - @property - def vcount(self): return self.v - def __repr__(self): - return f"{self.base.__repr__()}.ptr({self.size}{', local=True' if self.local else ''})" + (f'.vec({self.v})' if self.v != 1 else '') - -@dataclass(frozen=True, eq=False) -class ImageDType(PtrDType): - shape: tuple[int, ...] = () # shape of the Image - def ptr(self, size=-1, local=False) -> PtrDType: - assert not local, "images can't be local" - return self - def __repr__(self): return f"dtypes.{self.name}({self.shape})" + (f'.vec({self.v})' if self.v != 1 else '') - -class dtypes: - @staticmethod - @functools.cache - def is_float(x: DType) -> bool: return x.scalar() in dtypes.floats or isinstance(x, ImageDType) - @staticmethod # static methods on top, or bool in the type info will refer to dtypes.bool - @functools.cache - def is_int(x: DType) -> bool: return x.scalar() in dtypes.ints - @staticmethod - @functools.cache - def is_unsigned(x: DType) -> bool: return x.scalar() in dtypes.uints - @staticmethod - def is_bool(x: DType) -> bool: return x.scalar() == dtypes.bool - @staticmethod - def from_py(x) -> DType: - if x.__class__ is float: return dtypes.default_float - if x.__class__ is int: return dtypes.default_int - if x.__class__ is bool: return dtypes.bool - # put this in the last is faster because there are more items than lists/tuples to check - if x.__class__ is list or x.__class__ is tuple: return max(dtypes.from_py(xi) for xi in x) if x else dtypes.default_float - raise RuntimeError(f"Could not infer dtype of {x} with type {type(x)}") - @staticmethod - def as_const(val: tuple[ConstType, ...]|ConstType, dtype:DType): - if isinstance(val, tuple): - assert len(val) == dtype.count, f"mismatch {val} {dtype}" - return tuple(dtypes.as_const(x, dtype) for x in val) - # TODO: should truncate here - return int(val) if dtypes.is_int(dtype) else float(val) if dtypes.is_float(dtype) else bool(val) - @staticmethod - @functools.cache - def min(dtype:DType): - if dtypes.is_int(dtype): return 0 if dtypes.is_unsigned(dtype) else -2**(dtype.itemsize*8-1) - return -float("inf") if dtypes.is_float(dtype) else False - @staticmethod - @functools.cache - def max(dtype:DType): - if dtypes.is_int(dtype): return 2**(dtype.itemsize*8)-1+dtypes.min(dtype) - return float("inf") if dtypes.is_float(dtype) else True - @staticmethod - def finfo(dtype:DType) -> tuple[int, int]: - """(exponent, mantissa)""" - if not dtypes.is_float(dtype): raise ValueError(f"{dtype} is not a floating point type") - return {dtypes.float16: (5, 10), dtypes.bfloat16: (8, 7), dtypes.float32: (8, 23), dtypes.float64: (11, 52), - dtypes.fp8e5m2: (5, 2), dtypes.fp8e4m3: (4, 3)}[dtype] - @staticmethod - def fields() -> dict[str, DType]: return DTYPES_DICT - void: Final[DType] = DType.new(-1, 0, "void", None) - bool: Final[DType] = DType.new(0, 1, "bool", '?') - int8: Final[DType] = DType.new(1, 1, "signed char", 'b') - uint8: Final[DType] = DType.new(2, 1, "unsigned char", 'B') - int16: Final[DType] = DType.new(3, 2, "short", 'h') - uint16: Final[DType] = DType.new(4, 2, "unsigned short", 'H') - int32: Final[DType] = DType.new(5, 4, "int", 'i') - uint32: Final[DType] = DType.new(6, 4, "unsigned int", 'I') - int64: Final[DType] = DType.new(7, 8, "long", 'q') - uint64: Final[DType] = DType.new(8, 8, "unsigned long", 'Q') - fp8e4m3: Final[DType] = DType.new(9, 1, "float8_e4m3", None) - fp8e5m2: Final[DType] = DType.new(10, 1, "float8_e5m2", None) - float16: Final[DType] = DType.new(11, 2, "half", 'e') - # bfloat16 has higher priority than float16, so least_upper_dtype(dtypes.int64, dtypes.uint64) = dtypes.float16 - bfloat16: Final[DType] = DType.new(12, 2, "__bf16", None) - float32: Final[DType] = DType.new(13, 4, "float", 'f') - float64: Final[DType] = DType.new(14, 8, "double", 'd') - - # dtype aliases - half = float16; float = float32; double = float64 # noqa: E702 - uchar = uint8; ushort = uint16; uint = uint32; ulong = uint64 # noqa: E702 - char = int8; short = int16; int = int32; long = int64 # noqa: E702 - - # NOTE: these are image dtypes - @staticmethod - def imageh(shp): return ImageDType(100, 2, "imageh", 'e', 1, None, dtypes.float32, False, 1, prod(shp), shp) - @staticmethod - def imagef(shp): return ImageDType(100, 4, "imagef", 'f', 1, None, dtypes.float32, False, 1, prod(shp), shp) - - default_float: ClassVar[DType] = float32 - default_int: ClassVar[DType] = int32 - - fp8s = (fp8e4m3, fp8e5m2) - floats = fp8s + (float16, bfloat16, float32, float64) - uints = (uint8, uint16, uint32, uint64) - sints = (int8, int16, int32, int64) - ints = uints + sints - all = floats + ints + (bool,) - -if (env_default_float := getenv("DEFAULT_FLOAT", "")): - dtypes.default_float = getattr(dtypes, env_default_float.lower()) - assert dtypes.is_float(dtypes.default_float), f"{env_default_float} is not a float dtype" - -DTypeLike = Union[str, DType] -def to_dtype(dtype:DTypeLike) -> DType: return dtype if isinstance(dtype, DType) else getattr(dtypes, dtype.lower()) - -# https://jax.readthedocs.io/en/latest/jep/9407-type-promotion.html -# we don't support weak type and complex type -promo_lattice = { dtypes.bool: [dtypes.int8, dtypes.uint8], dtypes.int8: [dtypes.int16], dtypes.int16: [dtypes.int32], dtypes.int32: [dtypes.int64], - dtypes.int64: [dtypes.float16, dtypes.bfloat16], dtypes.uint8: [dtypes.int16, dtypes.uint16], dtypes.uint16: [dtypes.int32, dtypes.uint32], - dtypes.uint32: [dtypes.int64, dtypes.uint64], dtypes.uint64: [dtypes.float16, dtypes.bfloat16], - dtypes.fp8e5m2: [dtypes.float16, dtypes.bfloat16], dtypes.fp8e4m3: [dtypes.float16, dtypes.bfloat16], - dtypes.float16: [dtypes.float32], dtypes.bfloat16: [dtypes.float32], dtypes.float32: [dtypes.float64], } - -@functools.cache -def _get_recursive_parents(dtype:DType) -> set[DType]: - return set.union(*[_get_recursive_parents(d) for d in promo_lattice[dtype]], {dtype}) if dtype != dtypes.float64 else {dtypes.float64} -@functools.cache -def least_upper_dtype(*ds:DType) -> DType: - return min(set.intersection(*[_get_recursive_parents(d) for d in ds])) if not (images:=[d for d in ds if isinstance(d, ImageDType)]) else images[0] -def least_upper_float(dt:DType) -> DType: return dt if dtypes.is_float(dt) else least_upper_dtype(dt, dtypes.default_float) - -DTYPES_DICT = {k: v for k, v in dtypes.__dict__.items() if isinstance(v, DType) and not k.startswith(("default", "void"))} -INVERSE_DTYPES_DICT = {**{v.name:k for k,v in DTYPES_DICT.items()}, "void": "void"} - -def sum_acc_dtype(dt:DType): - # default acc dtype for sum - if dtypes.is_unsigned(dt): return least_upper_dtype(dt, dtypes.uint) - if dtypes.is_int(dt) or dt == dtypes.bool: return least_upper_dtype(dt, dtypes.int) - return least_upper_dtype(dt, to_dtype(getenv("SUM_DTYPE", "float32"))) - -def truncate_fp16(x): - try: return struct.unpack("@e", struct.pack("@e", float(x)))[0] - except OverflowError: return math.copysign(math.inf, x) - -def truncate_bf16(x): - max_bf16 = struct.unpack('f', struct.pack('I', 0x7f7f0000))[0] - if abs(x) > max_bf16: return math.copysign(math.inf, x) - f32_int = struct.unpack('I', struct.pack('f', x))[0] - bf = struct.unpack('f', struct.pack('I', f32_int & 0xFFFF0000))[0] - return bf - -# fp8-float conversions based on https://gitlab.com/nvidia/headers/cuda-individual/cudart/-/blob/main/cuda_fp8.hpp -def float_to_fp8(x: float, dtype: DType) -> int: - assert dtype in dtypes.fp8s, "Only for fp8s" - config = { - dtypes.fp8e4m3: {"EXP_BIAS": 7, "SIGNIFICAND_BITS": 4, "MANTISSA_MASK": 0x7, "MINDENORM_O2": 0x3F50000000000000, - "OVERFLOW_THRESHOLD": 0x407D000000000000, "MAXNORM": 0x7E, "MINNORM": 0x3F90000000000000, "INF_VALUE": 0x7F}, - dtypes.fp8e5m2: {"EXP_BIAS": 15, "SIGNIFICAND_BITS": 3, "MANTISSA_MASK": 0x3, "MINDENORM_O2": 0x3EE0000000000000, - "OVERFLOW_THRESHOLD": 0x40EE000000000000 - 1, "MAXNORM": 0x7B, "MINNORM": 0x3F10000000000000, "INF_VALUE": 0x7E} - }[dtype] - xbits, = struct.unpack('Q', struct.pack('d', x)) - FP8_DP_HALF_ULP = 1 << (53 - config["SIGNIFICAND_BITS"] - 1) - sign = ((xbits >> 63) & 1) << 7 - exp = (((xbits >> 52) & 0x7FF) - 1023 + config["EXP_BIAS"]) - mantissa = (xbits >> (53 - config["SIGNIFICAND_BITS"])) & config["MANTISSA_MASK"] - absx = xbits & 0x7FFFFFFFFFFFFFFF - - if absx <= config["MINDENORM_O2"]: res = 0 - elif absx > 0x7FF0000000000000: res = 0x7F if dtype == dtypes.fp8e4m3 else 0x7E | mantissa - elif absx > config["OVERFLOW_THRESHOLD"]: res = config["MAXNORM"] - elif absx >= config["MINNORM"]: - res = ((exp << (config["SIGNIFICAND_BITS"] - 1)) | mantissa) - round_bits = xbits & ((FP8_DP_HALF_ULP << 1) - 1) - if (round_bits > FP8_DP_HALF_ULP) or (round_bits == FP8_DP_HALF_ULP and (mantissa & 1)): res = res + 1 - else: - shift = 1 - exp - mantissa |= 1 << (config["SIGNIFICAND_BITS"] - 1) - res = (mantissa >> shift) - round_bits = (xbits | (1 << (53 - 1))) & ((FP8_DP_HALF_ULP << (shift + 1)) - 1) - if (round_bits > (FP8_DP_HALF_ULP << shift)) or (round_bits == (FP8_DP_HALF_ULP << shift) and (res & 1)): - res = res + 1 - - res |= sign - return int(res) - -def fp8_to_float(x: int, dtype: DType) -> float: - assert dtype in dtypes.fp8s, "Only for fp8s" - ur = x << 8 - - if dtype == dtypes.fp8e5m2 and (ur & 0x7FFF) > 0x7C00: ur = 0x7FFF - elif dtype == dtypes.fp8e4m3: - sign = ur & 0x8000 - exponent = ((ur & 0x7800) >> 1) + 0x2000 - mantissa = (ur & 0x0700) >> 1 - absx = x & 0x7F - if absx == 0x7F: ur = 0x7FFF - elif exponent == 0x2000: - if mantissa != 0: - mantissa <<= 1 - while (mantissa & 0x0400) == 0: - mantissa <<= 1 - exponent -= 0x0400 - mantissa &= 0x03FF - else: - exponent = 0 - ur = (sign | exponent) | mantissa - else: - ur = (sign | exponent) | mantissa - - half_bytes = struct.pack(' Optional[type]: - import numpy as np - return np.dtype(dtype.fmt).type if dtype.fmt is not None else None -def _from_np_dtype(npdtype:'np.dtype') -> DType: # type: ignore [name-defined] # noqa: F821 - import numpy as np - return dtypes.fields()[np.dtype(npdtype).name] - -@functools.cache -def _to_torch_dtype(dtype:DType) -> Optional['torch.dtype']: # type: ignore [name-defined] # noqa: F821 - import numpy as np, torch - # NOTE: torch doesn't expose this mapping with a stable API - try: return torch.from_numpy(np.array([], dtype=_to_np_dtype(dtype))).dtype - except TypeError: return None -@functools.cache -def _from_torch_dtype(torchdtype:'torch.dtype') -> DType: # type: ignore [name-defined] # noqa: F821 - return {v:k for k in dtypes.all if (v:=_to_torch_dtype(k)) is not None}[torchdtype] \ No newline at end of file diff --git a/tinygrad/tinygrad/engine/__init__.py b/tinygrad/tinygrad/engine/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/engine/grouper.py b/tinygrad/tinygrad/engine/grouper.py deleted file mode 100644 index d04669db..00000000 --- a/tinygrad/tinygrad/engine/grouper.py +++ /dev/null @@ -1,584 +0,0 @@ -from dataclasses import dataclass -from tinygrad.uop.ops import UOp, Ops, GroupOp, PatternMatcher, UPat, graph_rewrite, graph_rewrite_map, identity_element, resolve, can_pad, sint -from tinygrad.uop.ops import track_rewrites, _substitute -from tinygrad.uop.spec import type_verify, tensor_uop_spec -from tinygrad.codegen.lowerer import get_contraction_with_reduce -from tinygrad.codegen.symbolic import symbolic_simple -from tinygrad.helpers import Metadata, all_int, all_same, colored, prod, dedup, unwrap, getenv, pluralize -from tinygrad.helpers import FUSE_CONV_BW, FUSE_ARANGE, DEBUG, DONT_REALIZE_EXPAND, DONT_GROUP_REDUCES, SPLIT_REDUCEOP -from tinygrad.dtype import ImageDType -from tinygrad.engine.multi import multi_pm, replace_allreduce -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View, strides_for_shape - -# creation can recurse a lot -import sys -sys.setrecursionlimit(10000) - -# **** schedule simplifier - -def simplify_stride0_reduce(reduce:UOp, x:UOp): - # must be unmasked (NOTE: can be relaxed if not masked on stride 0 axis) - if any(v.mask is not None for v in unwrap(x.st).views): return None - # must have all stride 0 in the relevant axis (NOTE: can do partial) - if not all(unwrap(x.st).views[-1].strides[axis] == 0 for axis in reduce.arg[1]) or not all_int(x.shape): return None - prshape = prod(x.shape[i] for i in reduce.arg[1]) - ret = x.shrink(tuple((0,s) if i not in reduce.arg[1] else (0,1) for i,s in enumerate(x.shape))) - match reduce.arg[0]: - case Ops.ADD: return ret*prshape - case Ops.MUL: return ret.pow(prshape) - case Ops.MAX: return ret # NOTE: Ops.MAX is passthrough - -def split_reduceop(reduce:UOp, x:UOp): - if not SPLIT_REDUCEOP or not all_int(x.shape) or (prod(x.shape)//prod(reduce.shape))= 3: print(f"split {divisor}: {x.shape} -> {splitted.shape} -> {reduce.shape}") - # reduce original axes, then split - return splitted.r(*reduce.arg).r(reduce.arg[0], (len(reduce.shape),)).reshape(reduce.shape) - -def copy_reorder_view(copy:UOp, view:UOp, base:UOp): - if prod(view.shape) < prod(base.shape): return view.contiguous().copy_to_device(copy.device) - return base.copy_to_device(copy.device).view(view.arg) - -ALWAYS_CONTIGUOUS = {Ops.CONTIGUOUS, Ops.ASSIGN, Ops.COPY, Ops.BUFFER, Ops.BUFFER_VIEW, - Ops.CONST, Ops.BIND, Ops.DEVICE, Ops.MSELECT, Ops.MSTACK, Ops.GBARRIER} - -sym = symbolic_simple+PatternMatcher([ - # UOp with size 0 is zero - (UPat(GroupOp.All-{Ops.SINK}, name="root"), lambda root: root.const_like(0) if root.base.st is not None and root.size == 0 \ - and not (root.base.op is Ops.CONST and root.base.arg == 0) else None), - # DETACH and CONTIGUOUS_BACKWARD are NOOPs here - (UPat((Ops.DETACH, Ops.CONTIGUOUS_BACKWARD), name="x"), lambda x: x.src[0]), - # reduce of size 0 is the identity element - (UPat(Ops.REDUCE_AXIS, name="reduce", src=(UPat.var("x"),)), - lambda reduce,x: reduce.const_like(identity_element(reduce.arg[0], reduce.dtype)) if x.size == 0 and reduce.size != 0 else None), - # reduce on stride 0 is collapsed - (UPat(Ops.REDUCE_AXIS, name="reduce", src=(UPat.var("x"),)), simplify_stride0_reduce), - # split_reduceop - (UPat(Ops.REDUCE_AXIS, name="reduce", src=(UPat.var("x"),)), split_reduceop), - # COPY(CONST) creates a new CONST on the destination device - (UPat(Ops.COPY, name="root", src=(UPat.cvar("x"), UPat(Ops.DEVICE))), lambda root,x: root.const_like(x.arg)), - # non device changing COPY is a NOOP - (UPat(Ops.COPY, name="c", src=(UPat.var("x"), UPat(Ops.DEVICE))), lambda c,x: x if c.device == x.device else None), - # store a shrink before COPY, otherwise view after the COPY - (UPat(Ops.COPY, src=(UPat(Ops.VIEW, src=(UPat.var("base"),), name="view"), UPat(Ops.DEVICE)), name="copy"), copy_reorder_view), - # remove cast to image when it's already a contiguous image - (UPat(Ops.CAST, name="cast", src=(UPat(Ops.VIEW, name="vm", src=(UPat(Ops.CONTIGUOUS, name="base"),)),)), - lambda cast,base,vm: base.view(vm.st) if isinstance(cast.dtype, ImageDType) and isinstance(base.dtype, ImageDType) else None), - # CAST before masking constants - (UPat.cvar("x").view().cast(name="c"), lambda x,c: x.cast(c.dtype).view(c.src[0].arg)), - # make things that can't be images not images - (UPat(GroupOp.All-{Ops.BUFFER, Ops.VIEW, Ops.CONST, Ops.DEVICE}, name="u"), lambda u: u.replace(dtype=dt.base) if isinstance(dt:=u.dtype,ImageDType) - and (prod(u.shape) != prod(dt.shape) or not any(u.shape[x]%4 == 0 for x in u.st.unit_stride_axes())) else None), - # remove contiguous if we can just view the buffer - (UPat(Ops.CONTIGUOUS, name="root", src=(UPat(Ops.VIEW, name="view", src=(UPat(Ops.BUFFER, name="buf"),)),)), - lambda root,view,buf: view if view.st.contiguous and view.size == buf.size else None), - # contiguous/buffer/copy/assign is already contiguous - (UPat(Ops.CONTIGUOUS, name="root", src=(UPat((Ops.CONTIGUOUS, Ops.BUFFER, Ops.COPY, Ops.ASSIGN)),)), lambda root: root.src[0]), - # substitute BITCAST/CONTIGUOUS with BUFFER_VIEW on DISK - (UPat((Ops.BITCAST, Ops.CONTIGUOUS), src=(UPat.var("x"),), name="t"), lambda x,t: UOp(Ops.BUFFER_VIEW, t.dtype, (x.base,), - (t.size, x.st.views[0].offset)).reshape(t.shape) if isinstance(x.device, str) and x.device.startswith("DISK") else None), - # double ASSIGN to same target is one ASSIGN - (UPat(Ops.ASSIGN, src=(UPat.var("t"), UPat(Ops.ASSIGN, src=(UPat.var("t"), UPat.var("x"))))), lambda x,t: t.assign(x.contiguous())), - # ASSIGN to unrealized replaces the UOp - (UPat(Ops.ASSIGN, src=(UPat.var("t"), UPat.var("x"))), lambda x,t: x.contiguous() if t.base.op not in {Ops.BUFFER, Ops.BUFFER_VIEW} and - not (t.base.op is Ops.MSTACK and all(x.op is Ops.BUFFER for x in t.base.src)) else None), - # put CAST to smaller dtype before EXPAND - (UPat(Ops.CAST, name="cast", src=(UPat(Ops.VIEW, name="vm"),)), lambda cast,vm: vm.base.cast(cast.dtype).view(vm.st) - if cast.dtype.itemsize <= vm.dtype.itemsize and resolve(prod(vm.shape) > vm.st.real_size()) else None), - # put UnaryOps before EXPANDs, if it can fuse with the input - (UPat(GroupOp.Unary, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="inp"),), name="v"),), name="alu"), - lambda inp,v,alu: inp.alu(alu.op).view(v.st) if resolve(prod(alu.shape) > v.st.real_size()) else None), -]) - -# support for using a contiguous permuted view instead of the parent view if one exists - -def found_contiguous(ctx:dict[UOp, UOp], contig:UOp, src:UOp): - if (sti:=unwrap(src.st).invert(src.base.shape)) is not None: ctx[src.base] = contig.view(sti) - -replace_contiguous = PatternMatcher([ - (UPat(Ops.CONTIGUOUS, src=(UPat(Ops.VIEW, name="src"),), name="contig"), found_contiguous), - (UPat(GroupOp.ALU, name="alu"), lambda ctx,alu: alu.replace(src=new_src) if (new_src:=tuple(ctx.get(s, s) for s in alu.src)) != alu.src else None), -]) - -# **** Grouper decides which of the UOps realize - -def realize(ctx:dict[UOp, None], tr:UOp) -> None: ctx[tr] = None - -def realize_parents(ctx:dict[UOp, None], rb:UOp) -> None: - for s in rb.src: - if s.op not in ALWAYS_CONTIGUOUS: ctx[s] = None - -def realize_before_view(ctx:dict[UOp, None], view:UOp, tr:UOp) -> None: - st = unwrap(view.st) - # always realize unsafe pad ops before masked view - if any(v.mask is not None for v in st.views) and not can_pad(tr, ctx): return realize(ctx, tr) - # fold simple pads - if len(st.views) == 1 and (m:=st.views[-1].mask) is not None and all_int(tr.shape) and resolve(prod(tr.shape) >= prod([y-x for x,y in m])): return - # realize before expand - if resolve(prod(tr.shape) < prod(st.shape)) and not DONT_REALIZE_EXPAND: return realize(ctx, tr) - -do_realize = PatternMatcher([ - # always realize SINK parents - (UPat(Ops.SINK, name="s"), lambda ctx,s: ctx.update((x.base, None) for x in s.src if x.base.op not in ALWAYS_CONTIGUOUS)), - # always realize ASSIGN/CONTIGUOUS/GroupOp.Meta - (UPat({Ops.ASSIGN, Ops.CONTIGUOUS, *GroupOp.Meta}, name="tr"), realize), - # realize before expand or unsafe pad ops - (UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="tr"),), name="view"), realize_before_view), - # realize parents of COPY, MSELECT, MSTACK - (UPat((Ops.COPY, Ops.MSELECT, Ops.MSTACK), name="rb"), realize_parents), -]) - -def recursive_group(tr:UOp, st:ShapeTracker, r:UOp, children:dict[UOp, dict[UOp, None]], realizes:dict[UOp, None], - reduce_for_op:dict[UOp, UOp], group:dict[UOp, None], cache:dict[tuple[UOp, ShapeTracker], None]) -> None: - if (tr, st) in cache: return - cache.setdefault((tr, st)) - rsize = unwrap(r.st).size - if tr in realizes and tr is not r: - # can only fuse contiguous - # max one reduceop per kernel - if not st.contiguous or st.size != rsize or tr in reduce_for_op: group.setdefault(r) - return group.setdefault(tr) - for tr_next in children.get(tr, {}): - # max one reduceop per kernel - if tr_next.op is Ops.REDUCE_AXIS: return group.setdefault(r) - # can only fuse contiguous - if len(st_childs:=dedup(unwrap(x.st) for x in tr_next.src if x.base == tr)) > 1: return group.setdefault(r) - recursive_group(tr_next, st+st_childs[0], r, children, realizes, reduce_for_op, group, cache) - -def group_realizes(sink:UOp) -> dict[UOp, None]: - # start by adding uops that always realize - realizes: dict[UOp, None] = {} - sink = graph_rewrite(sink, do_realize, ctx=realizes, name="do_realize") - if DONT_GROUP_REDUCES: return realizes - - # construct children graph (only for bases) - children: dict[UOp, dict[UOp, None]] = {} - assigns: dict[UOp, None] = {} - for u in (toposort:=sink.toposort()): - if u.op in {Ops.VIEW, Ops.SINK}: continue - if u.op is Ops.ASSIGN: assigns[u.buf_uop] = None - for s in u.src: children.setdefault(s.base, {})[u] = None - - # find all reduces, and pair them to a elementwise op. if they can't be cleanly paired, force realize the reduce (or a contig child) - reduce_for_op: dict[UOp, UOp] = {} - double_reduces: list[UOp] = [] - for r in toposort: - if r.op is not Ops.REDUCE_AXIS: continue - if len(r.arg) == 3 and r.arg[2] is True: continue - if FUSE_CONV_BW and r.src[0].base.op is Ops.REDUCE_AXIS and r.src[0] is not r.src[0].base: double_reduces.append(r) - if r in realizes: continue - group: dict[UOp, None] = {} - recursive_group(r, unwrap(r.st), r, children, realizes, reduce_for_op, group, cache={}) - # max one reduceop per kernel - can_chase = all(tr not in reduce_for_op for tr in group) - for u in r.toposort(gate=lambda u: u not in realizes): - if u.op is Ops.REDUCE_AXIS and u.src[0].base.op is Ops.CONST: - can_chase = False - break - # TODO: forced_realize exists because the scheduler is incapable of checking for self-contained DAGs - forced_realize = r in group - # can only have one output - if not forced_realize and len(group) > 1: forced_realize = True - # can only fuse assign if no other assign_target is used in the kernel - if not forced_realize and (assign_targets:={x.buf_uop for x in group if x.op is Ops.ASSIGN}): - parents = [r, *group] - while parents and not forced_realize: - p = parents.pop().base - if p.op is Ops.BUFFER and p in assigns and p not in assign_targets: forced_realize, can_chase = True, False - if p in realizes: continue - parents.extend(p.src) - if forced_realize or not group: - tr = r - if can_chase: - # can chase this down to contiguous children - st = unwrap(tr.st) - while len(lst:=children.get(tr, {})) == 1: - tr_next = next(iter(lst)) - st_childs = dedup(unwrap(s.st) for s in tr_next.src if s.base is tr) - if len(st_childs) > 1: break - if st.size != st_childs[0].size: break - st = st + st_childs[0] - if not st.contiguous or tr_next.op is Ops.REDUCE_AXIS: break - tr = tr_next - # don't cast to higher size before store (tr cannot be realized if forced_realize) - if tr.op is Ops.CAST and tr.dtype.itemsize > tr.src[0].dtype.itemsize: - tr = tr.src[0].base - group = {tr: None} - realizes[tr] = None - reduce_for_op.update((tr, r) for tr in group) - # fuse double reduces with no other child - for reduceop in double_reduces: - top_reduce = reduceop.src[0].base - if len(children.get(top_reduce, {})) == 1: del realizes[top_reduce] - return realizes - -# **** create kernels - -@dataclass(frozen=True) -class Kernel: - ast: UOp - metadata: tuple[Metadata, ...] = () - def __repr__(self): - ast_rep = f"SINK{tuple(s.op for s in self.ast.src)}" if self.ast.op is Ops.SINK else repr(self.ast.op) - return f"" - -def create_kernel(x:UOp, b:UOp|None=None): - if b is None: b = UOp.new_buffer(x.device, x.size, x.dtype) - kernel = UOp(Ops.KERNEL, src=(b,)+x.src, arg=Kernel(x.sink(), m if (m:=x.metadata) else ())) - buffer = b.base if b.size == b.base.size else UOp(Ops.BUFFER_VIEW, b.dtype, (b.base,), (b.size, b.arg.views[0].offset)) - return buffer.assign(kernel).reshape(x.shape) - -DONT_PLACE_IN_KERNEL = {Ops.KERNEL, Ops.ASSIGN, Ops.BUFFER, Ops.MSELECT, Ops.MSTACK, Ops.MULTI} -def append_to_kernel(x:UOp): - new_srcs: list[UOp] = [] - metadata = x.arg.metadata - for s in x.src: - if s.op in DONT_PLACE_IN_KERNEL: new_srcs.append(s) - else: - new_srcs.extend(s.src) - # NOTE: because const and device are shared UOps they don't change metadata - # NOTE: if it's a reshape after ASSIGN we're not fusing that parent kernel - if s.base.op not in {Ops.CONST, Ops.DEVICE} and (not (s.op is Ops.RESHAPE and s.base.op is Ops.ASSIGN)) and (m:=s.metadata): metadata += m - if (new_src:=tuple(dedup(new_srcs))) != x.src: return x.replace(src=new_src, arg=Kernel(x.arg.ast, tuple(dedup(metadata)))) - -create_kernels = PatternMatcher([ - # always give assign/gbarrier a kernel - (UPat.assign(UPat.var("b"), UPat(GroupOp.All-{Ops.KERNEL}), name="x"), create_kernel), - (UPat(Ops.GBARRIER, src=(UPat.var("x"),)), create_kernel), - # walk back the local graph until we reach a realized source - (UPat(Ops.KERNEL, name="x"), append_to_kernel), - # push RESHAPE through MSELECT - (UPat(Ops.MSELECT, src=(UPat(Ops.RESHAPE, name="r"),), name="ms"), lambda ms,r: r.src[0].mselect(ms.arg).reshape(r.arg)), - # push RESHAPE through MSTACK - (UPat(Ops.MSTACK, src=UPat(Ops.RESHAPE), name="ms"), - lambda ms: UOp(Ops.MSTACK, ms.dtype, tuple(x.src[0] for x in ms.src)).reshape(ms.src[0].arg)), -]) - -# **** swizzler - -merge_views = PatternMatcher([ - # merge adjacent views - (UPat(Ops.VIEW, src=(UPat(Ops.VIEW, name="v1"),), name="v2"), lambda v1,v2: v1.replace(arg=v1.arg+v2.arg)), - # replace MovementOps with VIEW - (UPat(GroupOp.Movement, src=(UPat.var("x"),), name="mop"), lambda mop,x: x.base.view(mop.st)), - # remove NOOP views - (UPat.var("x").view(name="view"), lambda x,view: x if x.st is not None and view.st.contiguous and view.shape == x.shape else None), - (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL}).view(name="view"), - lambda view: view.const_like(0) if (mask:=view.st.views[-1].mask) is not None and any((x[1]-x[0]) == 0 for x in mask) else None), - # only unmaksed VIEW on CONST replaces the ShapeTracker - (UPat(Ops.VIEW, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="x"),), name="view"), - lambda x,view: x.replace(src=(x.src[0].replace(arg=x.st+view.st),)) if all(v.mask is None for v in (x.st+view.st).views) else None), -]) - -def reduce_push_add_ones(src:UOp, r:UOp, view:UOp): - # contiguous, expand, and the same with ones removed - if unwrap(view.st).contiguous and len(r.shape) < len(view.shape) and \ - tuple(x for x in r.shape if resolve(x != 1)) == tuple(x for x in view.shape if resolve(x != 1)): - new_shape: list[sint] = [] - new_reduce_axis = [] - if (contraction:=get_contraction_with_reduce(view.shape, r.shape, r.arg[1])) is None: return None - for i,pairs in enumerate(contraction): - new_shape_chunk = [view.shape[p] for p in pairs] - if i in r.arg[1]: - # if this is a reduce axis, we need a 1 in the view here to put it - assert len(new_shape_chunk) > 0 - new_shape += [1]*(len(pairs)-1) + [src.shape[i]] - new_reduce_axis.append(len(new_shape)-1) - else: - # otherwise, pass through the new_shape_chunk - new_shape += new_shape_chunk - ret = r.replace(src=(src.reshape(tuple(new_shape)),), arg=(r.arg[0], tuple(new_reduce_axis))+r.arg[2:]) - assert ret.shape == view.shape, f"shape mismatch on reduce_push_add_ones, {ret.shape} != {view.shape}" - return ret - return None - -view_left = merge_views+PatternMatcher([ - # view before elementwise and buffer ops - (UPat(Ops.VIEW, src=(UPat({*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.BIND, Ops.LOAD, Ops.STORE, Ops.VALID}, name="e"),), name="view"), - lambda e,view: e.replace(src=tuple(s.view(view.st) for s in e.src))), - # if there's ones added after reduce, put this before the reduce - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), reduce_push_add_ones), -]) - -def apply_swizzle(u:UOp) -> UOp: return graph_rewrite(u, view_left, name="Sub View Left") - -# change reduceop axes and input ShapeTrackers, view gets replaced with a reshape. -def swizzle_reduceop(r:UOp, src:UOp, view:UOp, fuse=False): - # contiguous and same size can push to children - # if there's a reduce child, shapes match with ones removed - if unwrap(view.st).contiguous and view.size == r.size and \ - (not (len(r.arg) == 3 and r.arg[2]) or # arg[2] = True is fuse marker - tuple((i,x) for i,x in enumerate(r.shape) if resolve(x != 1)) == tuple((i,x) for i,x in enumerate(view.shape) if resolve(x != 1))): - return None - # swizzle the input - input_st = ShapeTracker.from_shape(src.shape) - tmp = input_st.permute(tuple(i for i in range(len(input_st.shape)) if i not in r.axis_arg)+r.axis_arg) - prshape = prod(rshape:=tmp.shape[-len(r.axis_arg):]) - strides = strides_for_shape(rshape) - nv = [View.create(v.shape+rshape, tuple(x*prshape for x in v.strides)+strides, - v.offset*prshape, v.mask+tuple((0,s) for s in rshape) if v.mask is not None else None) for v in unwrap(view.st).views] - new_view = tmp + ShapeTracker(tuple(nv)) - swizzled_input = apply_swizzle(src.view(new_view)) - # create a new reduceop - new_axis = tuple(range(len(view.shape), len(view.shape) + len(r.axis_arg))) - if fuse: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input.fuse(),), (r.arg[0], new_axis, True)) - else: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input,), (r.arg[0], new_axis)) - return red.reshape(view.shape) - -def reduceop_view_right(src:UOp, v:UOp, r:UOp): - assert unwrap(v.st).contiguous and v.size == src.size, f"can't compute new axis for {src.shape} -> {r.shape}" - new_axis = [i for i,(s,u) in enumerate(zip(src.shape, r.shape)) if s != u] - return src.r(r.arg[0], tuple(new_axis)).reshape(r.shape) - -def elementwise_view_right(root:UOp): - if not (swizzles:=[x for x in root.src if x.op is Ops.VIEW and x.base.op not in ALWAYS_CONTIGUOUS]): return None - assert all_same([x.base.size for x in swizzles]), f"swizzle inputs must have the same size {swizzles}" - # place view after applying the elementwise op - new_st = ShapeTracker.from_shape(swizzles[0].base.shape) - new_src = [x.base if x.base.shape==new_st.shape else apply_swizzle(x.view(new_st)) for x in root.src] - # reshape to match downstream shapes - return root.replace(src=tuple(new_src)).reshape(root.shape) - -# push VIEW to children -view_right = merge_views+PatternMatcher([ - # push a non contiguous ShapeTracker through reduceop - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), swizzle_reduceop), - # apply view after reduceops - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="src"),), name="v"),), name="r"), reduceop_view_right), - # apply view after elementwise ops - (UPat(GroupOp.All-{Ops.SINK, Ops.GBARRIER}, name="root"), elementwise_view_right), - # merge axes for double reduce (invert of SPLIT_REDUCEOP=1) - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.REDUCE_AXIS, name="r1"),), name="r2"), - lambda r1,r2: r1.replace(arg=(r1.arg[0], r2.arg[1]+r1.arg[1])) if r1.arg[0] is r2.arg[0] else None), -]) - -# **** fix kernel AST - -add_buffer_ops = PatternMatcher([ - # LOAD - (UPat(Ops.BUFFER, name="x"), lambda ctx,x: UOp.load(UOp(Ops.DEFINE_GLOBAL, x.dtype.ptr(x.size), (), ctx.index(x)).view(x.st),)), - # STORE (except for meta ops) - (UPat(Ops.SINK, src=(UPat(GroupOp.Meta, name="x"),)), lambda x:x), - (UPat(Ops.SINK, src=UPat(GroupOp.All-{Ops.STORE}), name="sink"), lambda ctx,sink: - UOp.sink(*[UOp.store(UOp(Ops.DEFINE_GLOBAL, (s:=x.base).dtype.ptr(ctx[i].size), (), i).view(s.st), s) for i,x in enumerate(sink.src)])), - # passthrough ASSIGN - (UPat(Ops.ASSIGN, name="x"), lambda x: x.src[1]), - # VALID - (UPat(Ops.VIEW, src=(UPat.cvar(),), name="self"), UOp.valid), -]) - -def check_load_st(glbl:UOp, view:UOp): - if glbl.arg != 0 or (st:=unwrap(view.st)).contiguous: return - # if it has a single view and it becomes contiguous when you shrink expanded axes, it's fine - if len(st.views) == 1 and st.shrink(tuple((0,1) if st == 0 else (0,s) for s,st in zip(st.shape, st.views[0].strides))).contiguous: return - # if it has a single view and it's equal when you shrink a contig, it's fine - if len(st.views) == 1 and (mask:=st.views[0].mask) is not None and ShapeTracker.from_shape(st.shape).shrink(mask) == st.shrink(mask): return - # otherwise, it's not fine - raise RuntimeError("self operand of augmented assign must be contiguous.\nhelp: consider using .contiguous():\n" - +colored(" - a += a.T\n", "red")+colored(" + a += a.T.contiguous()", "green")) - -fix_kernel_ops = PatternMatcher([ - # remove CONTIGUOUS/DEVICE from kernel AST - (UPat((Ops.CONTIGUOUS, Ops.MSELECT), src=(UPat.var("x"),)), lambda x: x), - (UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),), name="view"), lambda view: view.replace(src=())), - # no ImageDType after index - (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL, Ops.VIEW}, name="x"), lambda x: x.replace(dtype=x.dtype.base) if isinstance(x.dtype, ImageDType) else None), - # if this kernel also assigns to the loaded buffer, ensure we can index it correctly - (UPat(Ops.LOAD, src=(UPat.var("glbl").view(name="view"),)), check_load_st), -]) - -replace_globals = PatternMatcher([ - # replace ASSIGN with the target BUFFER - (UPat(Ops.ASSIGN, src=(UPat(Ops.BUFFER), UPat(Ops.KERNEL)), name="assign", allow_any_len=True), lambda assign: assign.src[0]), - # HACK: select the 0 branch of MSTACK (the device is wrong after this, is that okay?) - (UPat(Ops.MSTACK, name="x"), lambda x: x.src[0]), -]) - -def fix_kernel_ast(k:UOp) -> UOp|None: - if k.arg.ast.op in GroupOp.Meta or all(s.op is Ops.STORE for s in k.arg.ast.src): return None - # replace global memory ops with the BUFFER they write to - ast = graph_rewrite(k.arg.ast, replace_globals, bottom_up=True, name="replace globals") - # push views to edges - ast = graph_rewrite(graph_rewrite(ast, view_left, name="Main View Left"), view_right, name="Main View Right") - # replace buffer with define_global + add load/store last - bufs = [] - for s in k.src: - s = s.buf_uop - # traverse back through MSELECT and MSTACK. HACK: 0 branch of MSTACK only - while s.op in {Ops.MSELECT, Ops.MSTACK}: s = s.src[0] - bufs.append(s) - ast = graph_rewrite(ast, view_left+add_buffer_ops+fix_kernel_ops, bufs, bottom_up=True, name="replace buffer") - if ast.op is Ops.SINK and not all_same([x.device for x in k.src]): - raise RuntimeError(f"all buffers must be on the same device: {tuple(b.buf_uop.buffer for b in k.src)}") - return k.replace(arg=Kernel(ast, k.arg.metadata)) - -create_ast = PatternMatcher([(UPat(Ops.KERNEL, name="k"), fix_kernel_ast),]) - -# ** add metadata of KERNEL outputs - -def append_metadata(root:UOp, k:UOp): - if not root.metadata or (new_metadata:=tuple(dedup(k.arg.metadata+root.metadata))) == k.arg.metadata: return None - return root.replace(src=(root.src[0], k.replace(arg=Kernel(k.arg.ast, new_metadata)))+root.src[2:]) - -replace_metadata = PatternMatcher([(UPat(Ops.ASSIGN, src=(UPat(), UPat(Ops.KERNEL, name="k")), name="root", allow_any_len=True), append_metadata),]) - -pm_fuse = PatternMatcher([ - # FUSE on CONTIGUOUS removes FUSE - (UPat(Ops.CONTIGUOUS, name="c").fuse(), lambda c: c), - - # FUSE triggers swizzle on reduceop - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r").or_casted(),), name="view").fuse(), - lambda r,src,view: ret.cast(view.dtype) if (ret:=swizzle_reduceop(r, src, view, fuse=True)) is not None else None), - - # FUSE on reduce (without view) adds fuse marker to grouper - (UPat(Ops.REDUCE_AXIS, name="r").fuse(), - lambda r: r.replace(src=(r.src[0].fuse(),), arg=r.arg+(True,)) if len(r.arg) == 2 else None), - - # remove FUSE and insert CONTIGUOUS if it's an unsafe pad - (UPat(Ops.VIEW, src=(UPat(GroupOp.UnsafePad, name="alu"),), name="view").fuse(), - lambda alu, view: alu.contiguous().view(view.st) if any(v.mask is not None for v in view.st.views) else None), - - # FUSE elementwise. - (UPat(Ops.VIEW, src=(UPat({*GroupOp.ALU, Ops.CAST}, name="alu"),), name="view").fuse(), - lambda alu, view: alu.replace(src=tuple(apply_swizzle(x.view(view.arg)).fuse() for x in alu.src))), - - # push FUSE through to srcs - (UPat(Ops.FUSE, name="x"), lambda x: x.src[0].replace(src=tuple(y.fuse() for y in x.src[0].src))), -]) - -def do_fusion(x:UOp): - found_contiguous = {} - def gate_contiguous(x): - if is_contiguous:=(x.op is Ops.CONTIGUOUS): found_contiguous[x] = x.replace(src=(UOp(Ops.VIEW, arg=x.st),)) - return not is_contiguous - x.toposort(gate=gate_contiguous) - del gate_contiguous - return graph_rewrite(x.substitute(found_contiguous), pm_fuse, name="local fusion").substitute({v:k for k,v in found_contiguous.items()}) - -def fuse_arange(root:UOp): - # skip if root is arange - if not FUSE_ARANGE or root.src[0].base.op is Ops.CONST: return None - # gather all local aranges (including any fused ones) - local_arange: list[UOp] = [] - def gate_reduce(u): - if u.op is Ops.REDUCE_AXIS and u.src[0].base.op is Ops.CONST: local_arange.append(u) - return u.op not in {*ALWAYS_CONTIGUOUS, Ops.REDUCE_AXIS} or u is root - toposort = root.toposort(gate=gate_reduce) - if not local_arange: return None - # fuse the nearest expand child of arange - local_children: dict[UOp, list[UOp]] = {} - for u in toposort: - for s in u.src: local_children.setdefault(s, []).append(u) - fuse_rep: dict[UOp, UOp] = {} - # skip if root depends on aranges with different ndims. This can be improved - if any(len(set(dims)) > 1 for dims in zip(*[r.src[0].shape for r in local_arange])): return - for r in local_arange: - # skip if already fused - if len(r.arg) > 2: continue - q = list(local_children[r]) - while q: - u = q.pop() - if not (curr_children:=local_children.get(u, [])): continue - for child in curr_children: - other_paths = {s for s in child.toposort() if s.op in {Ops.REDUCE_AXIS, Ops.BUFFER} and s not in {root, r}} - fuse_rep[child] = child.replace(src=tuple(s.fuse() if s is u else s for s in child.src)) - if other_paths: break - else: q.extend(curr_children) - return root.substitute(fuse_rep, name="fuse_arange") if fuse_rep else None - -do_fuse = PatternMatcher([ - (UPat(Ops.FUSE, name="x"), do_fusion), - (UPat(Ops.REDUCE_AXIS, name="root"), fuse_arange), -]) - -add_gbarrier = PatternMatcher([(UPat(GroupOp.All-{Ops.GBARRIER, Ops.ASSIGN}, name="x"), - lambda ctx,x: x.replace(tag=1).gbarrier() if x in ctx and x.tag is None else None)]) - -# TODO: get this from the device through GrouperOpts -DEVICE_MAX_BUFS = {"METAL":32, "WEBGPU":8} - -def limit_bufs(root:UOp): - # check if backend has a buffer limit - device = root.device if isinstance(root.device, str) else root.device[0].split(":")[0] - if not (MAX_BUFS:=getenv("MAX_KERNEL_BUFFERS", DEVICE_MAX_BUFS.get(device, 0))): return None - # count number of unique buffers flowing into this op - bufs: set[UOp] = set() - def gate_input(u:UOp): - if (is_load:=(u.op in {Ops.BUFFER, Ops.GBARRIER, Ops.ASSIGN, Ops.MSTACK})): bufs.add(u) - return not is_load - root.toposort(gate=gate_input) - # NOTE: this -1 is for the output buffer - if len(bufs)>=MAX_BUFS-1: - return root.replace(src=tuple(s if s.base in bufs else s.replace(tag=1).gbarrier() for s in root.src)) - -finalize_gbarrier = PatternMatcher([ - # if an op takes more than one input, check combined LOADs don't exceed device limits - (UPat(set.union(GroupOp.Binary, GroupOp.Ternary), name="root"), limit_bufs), - # merge gbarrier - (UPat((Ops.GBARRIER, Ops.CONTIGUOUS), src=(UPat(Ops.GBARRIER),), name="x"), lambda x: x.src[0]), - # add contiguous to VIEW before GBARRIER - (UPat(Ops.GBARRIER, src=(UPat(Ops.VIEW,),), name="x"), lambda x: x.src[0].contiguous().gbarrier()), - # remove gbarrier on constants without a contiguous - (UPat(Ops.GBARRIER, src=(UPat(Ops.CONST),), name="x"), lambda x: x.src[0]), -]) - -remove_tags = PatternMatcher([(UPat(GroupOp.All, name="x"), lambda x: x.replace(tag=None) if x.tag is not None else None)]) - -@track_rewrites(name_fxn=lambda big_sink,ret: f"Schedule {pluralize('Kernel',len([u for u in ret[big_sink].toposort() if u.op is Ops.KERNEL]))}") -def get_kernelize_map(big_sink:UOp) -> dict[UOp, UOp]: - # multi + merge_views + simplify - tensor_map = graph_rewrite_map(big_sink, multi_pm+replace_allreduce+do_fuse+merge_views+sym+replace_contiguous, ctx={}, name="merge_views") - - # display the cleaned up tensor graph - if getenv("VIZ"): graph_rewrite(tensor_map[big_sink], PatternMatcher([]), name="View Tensor Graph") - - # insert gbarriers in places determined by the realize map - realize_map = group_realizes(tensor_map[big_sink]) - tensor_map = graph_rewrite_map(tensor_map[big_sink], add_gbarrier, realize_map, bottom_up=True, input_map=tensor_map, name="insert_gbarrier") - # optionally reorder gbarriers or insert more (top down) - tensor_map = graph_rewrite_map(tensor_map[big_sink], finalize_gbarrier, input_map=tensor_map, name="finalize_gbarrier") - tensor_map = graph_rewrite_map(tensor_map[big_sink], remove_tags, input_map=tensor_map, name="remove_tags") - - # TODO: move view_left/view_right here - - # group into kernels (this is context-free) - tensor_map = graph_rewrite_map(tensor_map[big_sink], create_kernels, input_map=tensor_map, name="create_kernels") - - # if a kernel depends on a buffer, and that buffer is later assigned to, make the assign depend on the kernel's assign - kernel_assign: dict[UOp, UOp] = {} - assign_rep: dict[UOp, UOp] = {} - for u in tensor_map[big_sink].toposort(): - if u.op is not Ops.ASSIGN: continue - kernel_assign[u.buf_uop] = u - for s in u.src[1].src: - # TODO: this is probably broken for MSELECT/MSTACK - if s.op is not Ops.BUFFER or s is u.buf_uop or (a:=kernel_assign.get(s)) is None: continue - if any(x.op is Ops.ASSIGN and x.buf_uop is s for x in u.toposort()): - raise RuntimeError(f"cycle detected in graph, kernel for {u.buf_uop} must either depend on ASSIGN or BUFFER") - assign_rep[a] = kernel_assign[s] = a.replace(src=a.src+(u,)) - if assign_rep: - tensor_map = graph_rewrite_map(tensor_map[big_sink], _substitute, ctx=assign_rep, bottom_up=True, input_map=tensor_map, name="fix_assign") - - # finally, create the AST for kernels - tensor_map = graph_rewrite_map(tensor_map[big_sink], create_ast+replace_metadata, bottom_up=True, input_map=tensor_map, name="create_ast") - - # display the final graph - sched_sink = tensor_map[big_sink] - if getenv("VIZ"): graph_rewrite(sched_sink, PatternMatcher([]), name="View Kernel Graph") - if getenv("VIZ"): graph_rewrite(sched_sink, PatternMatcher([]), name="View Memory Graph") - - # verify Kernels match the spec - if __debug__: type_verify(list(sched_sink.toposort()), tensor_uop_spec) - - return tensor_map diff --git a/tinygrad/tinygrad/engine/jit.py b/tinygrad/tinygrad/engine/jit.py deleted file mode 100644 index c63810f1..00000000 --- a/tinygrad/tinygrad/engine/jit.py +++ /dev/null @@ -1,332 +0,0 @@ -from typing import TypeVar, Generic, Callable, Union, cast, Optional, Any -import functools, collections -from tinygrad.tensor import Tensor -from tinygrad.helpers import flatten, merge_dicts, DEBUG, Context, BEAM, getenv, colored, JIT, dedup, partition, unwrap -from tinygrad.device import Buffer, Compiled, Device, MultiBuffer -from tinygrad.dtype import DType -from tinygrad.uop.ops import UOp, Variable, sym_infer, Ops -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.engine.realize import ExecItem, capturing, ViewOp, BufferCopy, BufferXfer, CompiledRunner, Runner, Estimates -from tinygrad.engine.memory import _internal_memory_planner -from tinygrad.nn.state import get_parameters -from dataclasses import dataclass -from weakref import WeakKeyDictionary - -class GraphException(Exception): pass - -def graph_class(dev): return dev.graph.func if isinstance(dev.graph, functools.partial) else dev.graph - -def apply_graph_to_jit(jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int], max_batch_size=0) -> list[ExecItem]: - # Split JIT cache into batches for faster graph execution. - # This allows the accelerator to run some batches while subsequent graphs are still being updated. - graphed_jit_cache: list[ExecItem] = [] - current_batch: list[ExecItem] = [] - current_device: Optional[Compiled] = None - - def flush_batch(): - nonlocal current_batch, current_device, max_batch_size - try: - if current_device is None: raise GraphException("no device for graph") - if len(current_batch) <= 1 and not getenv("GRAPH_ONE_KERNEL"): raise GraphException("only one kernel doesn't graph") - graph_runner = current_device.graph(current_batch, input_rawbuffers, var_vals) - # clear jit inputs to allow their memory to be freed/reused - for (j,i) in graph_runner.input_replace.keys(): graph_runner.jit_cache[j].bufs[i] = None - graphed_jit_cache.append(ExecItem(graph_runner, cast(list[Optional[Buffer]], input_rawbuffers))) - max_batch_size *= 2 - if DEBUG >= 2: print(f"JIT GRAPHing batch with {len(current_batch)} kernels on device {current_device}") - except GraphException as e: - graphed_jit_cache.extend(current_batch) - if DEBUG >= 2: print(f"JIT GRAPHing failed batch with {len(current_batch)} kernels on device {current_device}: {e}") - current_batch = [] - current_device = None - - for ji in jit_cache: - match ji.prg: - case CompiledRunner(): - ji_graph_dev = ji.prg.dev - # All GraphRunners can graph CompiledRunners - can_be_graphed = ji_graph_dev.graph is not None - case BufferXfer(): - ji_graph_dev = Device[unwrap(ji.bufs[0]).device] - # All *Multi*GraphRunner support graphing BufferXfers - can_be_graphed = ji_graph_dev.graph is not None and issubclass(graph_class(ji_graph_dev), MultiGraphRunner) - case ViewOp(): continue # ViewOps are just ignored - case _: can_be_graphed = False # Everything else is not graphed and flushes existing graph if it's being constructed - - is_multigraph = can_be_graphed and issubclass(graph_class(ji_graph_dev), MultiGraphRunner) - can_share_graph = can_be_graphed and (type(ji_graph_dev) is type(current_device) if is_multigraph else ji_graph_dev == current_device) - can_extend_graph_batch = can_share_graph and (max_batch_size == 0 or len(current_batch) < max_batch_size) - if not can_extend_graph_batch and len(current_batch) > 0: flush_batch() - (current_batch if can_be_graphed else graphed_jit_cache).append(ji) - current_device = ji_graph_dev if can_be_graphed else None - - if len(current_batch) > 0: flush_batch() - return graphed_jit_cache - -def get_input_replace(jit_cache: list[ExecItem], input_rawbuffers:list[Buffer]) -> dict[tuple[int, int], int]: - input_replace: dict[tuple[int, int], int] = {} - for j,ji in enumerate(jit_cache): - for i,a in enumerate(ji.bufs): - if a in input_rawbuffers: - input_replace[(j,i)] = input_rawbuffers.index(a) - return input_replace - -class GraphRunner(Runner): - def __init__(self, jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int]): - self.jit_cache = jit_cache # NOTE: this is not used, but you have to keep these objects alive for the Graph - self.input_replace:dict[tuple[int, int], int] = get_input_replace(jit_cache, input_rawbuffers) - self.var_vals_replace:dict[int, list[tuple[int, int]]] = {} - self.launch_dims_replace:dict[int, tuple[Optional[int], Optional[int]]] = {} - self.launch_dims_base:dict[int, tuple[tuple[int, ...], tuple[int, ...]]] = {} - - def is_sym_dim(dim) -> bool: return not all(isinstance(d, (int, float)) for d in dim) - - self.vars = sorted(var_vals.keys(), key=lambda v: v.expr) - self.symbolic_dims = dedup([tuple(d) for ji in jit_cache if isinstance(ji.prg, CompiledRunner) and (d:=ji.prg.p.local_size) and is_sym_dim(d)] + - [tuple(d) for ji in jit_cache if isinstance(ji.prg, CompiledRunner) and (d:=ji.prg.p.global_size) and is_sym_dim(d)]) - def find_symbolic_dim(dim): return self.symbolic_dims.index(tuple(dim)) if dim is not None and tuple(dim) in self.symbolic_dims else None - - estimates = Estimates() - for j,ji in enumerate(jit_cache): - estimates += ji.prg.estimates - if isinstance(ji.prg, CompiledRunner): - if ji.prg.p.vars: self.var_vals_replace[j] = [(i, self.vars.index(v)) for i, v in enumerate(ji.prg.p.vars) if v not in ji.fixedvars] - - global_dim_idx, local_dim_idx = find_symbolic_dim(ji.prg.p.global_size), find_symbolic_dim(ji.prg.p.local_size) - if global_dim_idx is not None or local_dim_idx is not None: - self.launch_dims_replace[j] = (global_dim_idx, local_dim_idx) - assert ji.prg.p.global_size is not None and ji.prg.p.local_size is not None - self.launch_dims_base[j] = (tuple(ji.prg.p.global_size), tuple(ji.prg.p.local_size)) - - # used in MultiGraphRunner. the ints are id() of _bufs - self.w_dependency_map: dict[int, Any] = {} - self.r_dependency_map: dict[int, list[Any]] = collections.defaultdict(list) - - super().__init__(colored(f"", "cyan"), jit_cache[0].prg.device.split(":")[0], estimates.simplify()) - - def updated_vars(self, var_vals: dict[Variable, int]): - vals = [var_vals[v] for v in self.vars] - for j, vidxs in self.var_vals_replace.items(): - for i, v in vidxs: yield j, i, vals[v] - - def updated_launch_dims(self, var_vals: dict[Variable, int]): - dims = [tuple(sym_infer(s, var_vals) for s in dim) for dim in self.symbolic_dims] - for j, (gl, lc) in self.launch_dims_replace.items(): - yield j, (dims[gl] if gl is not None else self.launch_dims_base[j][0]), (dims[lc] if lc is not None else self.launch_dims_base[j][1]) - - def _access_resources(self, rawbufs:list[Buffer], write:list[int], new_dependency:Any): - # To synchronize access to resources, we monitor the necessary prerequisites for accessing each resource, - # whether for write or read operations. A resource can be accessed by either a single writer or multiple readers. - wait_nodes = [] - - for i,rawbuf in enumerate(rawbufs): - if id(rawbuf.base._buf) in self.w_dependency_map: wait_nodes.append(self.w_dependency_map[id(rawbuf.base._buf)]) - if i in write: - if id(rawbuf.base._buf) in self.r_dependency_map: wait_nodes.extend(self.r_dependency_map.pop(id(rawbuf.base._buf))) - - for i,rawbuf in enumerate(rawbufs): - if i in write: self.w_dependency_map[id(rawbuf.base._buf)] = new_dependency - else: self.r_dependency_map[id(rawbuf.base._buf)].append(new_dependency) - - return list({id(x):x for x in wait_nodes}.values()) - -# a marker for your graph supporting multiple devices of the same type -class MultiGraphRunner(GraphRunner): pass - -def get_out_buffers_for_ei(ei:ExecItem) -> list[Buffer]: - if isinstance(ei.prg, CompiledRunner): return [cast(Buffer, ei.bufs[out]) for out in ei.prg.p.outs if out not in ei.prg.p.ins] - if isinstance(ei.prg, (BufferCopy, BufferXfer)): return [cast(Buffer, ei.bufs[0])] - return [] - -def update_depends(depends:set[Buffer|None], jit_cache:list[ExecItem]): - for ei in jit_cache: - if any(b in depends for b in ei.bufs): depends.update(get_out_buffers_for_ei(ei)) - -ReturnType = TypeVar('ReturnType') -@dataclass -class CapturedJit(Generic[ReturnType]): - ret: Any # includes the Tensors or any other returned object - jit_cache: list[ExecItem] - input_replace: dict[tuple[int, int], int] - extra_view_inputs: list[tuple[int, int, str, int, DType]] - expected_names: list[Union[int, str]] - expected_st_vars_dtype_device: list[tuple[ShapeTracker, tuple[Variable, ...], DType, str]] - - def __reduce__(self): - # TODO: free_intermediates here? replan_buffers_memory_layout here? - return self.__class__, (self.ret, self.jit_cache, self.input_replace, self.extra_view_inputs, - self.expected_names, self.expected_st_vars_dtype_device) - - def __post_init__(self): - self._jit_cache: list[ExecItem] = self.jit_cache - self._input_replace: dict[tuple[int, int], int] = self.input_replace - self._first_run = True - self._clear_inputs() - - def _clear_inputs(self): - for (j,i) in self._input_replace.keys(): self._jit_cache[j].bufs[i] = None - - def free_intermediates(self): - depends: set[Buffer|None] = set([None]) - update_depends(depends, self.jit_cache) - for b in depends: - if b is not None: - if b.is_allocated(): b.deallocate() - if b._base is not None and b._base.allocated_views == 0 and b._base.is_allocated(): b._base.deallocate() - self.__post_init__() # reset the graph state - - def replan_buffers_memory_layout(self): - blacklist = [t.uop.buffer for t in get_parameters(self.ret)] - asgn = _internal_memory_planner([[b for item in self.jit_cache for b in item.bufs if b is not None and b not in blacklist]], ignore_checks=True) - self.jit_cache = [ExecItem(item.prg, [asgn.get(b,b) if b is not None else None for b in item.bufs]) for item in self.jit_cache] - for old, new in asgn.items(): - if old.is_allocated(): new.ensure_allocated().copyin(old.as_buffer()) - self.__post_init__() - - # jit exec - def __call__(self, input_buffers:list[Buffer], var_vals:dict[Variable, int]) -> ReturnType: - # assign inputs - for idx, offset, device, size, dtype in self.extra_view_inputs: - input_buffers.append(Buffer(device, size, dtype, base=input_buffers[idx], offset=offset).ensure_allocated()) - for (j,i),input_idx in self._input_replace.items(): self._jit_cache[j].bufs[i] = input_buffers[input_idx] - - # Condense the items into a graph executor. - if self._first_run: - # allocate intermediates if freed - for ji in self.jit_cache: - for b in ji.bufs: - if b is not None: b.ensure_allocated() - # create graph if needed - if JIT < 2: - self._jit_cache = apply_graph_to_jit(self.jit_cache, input_buffers, var_vals, max_batch_size=getenv("JIT_BATCH_SIZE", 32)) - self._input_replace = get_input_replace(self._jit_cache, input_buffers) - self._first_run = False - - if DEBUG >= 1 and len(self._jit_cache) >= 10: print(f"jit execs {len(self._jit_cache)} kernels") - for ei in self._jit_cache: ei.run(var_vals, jit=True) - self._clear_inputs() - return self.ret - -def _prepare_jit_inputs(args, kwargs): - input_tensors: list[tuple[int|str, Tensor]] = [(name,t) for name,t in list(enumerate(args))+sorted(kwargs.items()) if t.__class__ is Tensor] - names, tensors = [name for name,_ in input_tensors], [t for _,t in input_tensors] - if len(unrealized_tensors := [x for x in tensors if not x.uop.is_realized]): Tensor.realize(*unrealized_tensors) - # TODO: this multi unpack stuff is not well tested. - lbs: list[UOp] = flatten([t.uop.src if t.uop.op is Ops.MULTI else [t.uop] for t in tensors]) - input_buffers: list[Buffer] = flatten([rb.bufs if isinstance(rb:=lb.base.realized, MultiBuffer) else [rb] - for lb in lbs if lb.base.realized is not None]) - assert len(set(input_buffers)) == len(input_buffers), "duplicate inputs to JIT" - st_varval_dtype_device = [(*unwrap(lb.st).unbind(), lb.dtype, lb.device) for lb in lbs] - var_vals = merge_dicts([x[1] for x in st_varval_dtype_device] + [dict(v.unbind() for v in (args + tuple(kwargs.values())) if isinstance(v, UOp))]) - st_vars_dtype_device = [(x[0], tuple(sorted(x[1].keys(), key=lambda v: v.expr)), x[2], x[3]) for x in st_varval_dtype_device] - return input_buffers, var_vals, names, st_vars_dtype_device - -class TinyJit(Generic[ReturnType]): - def __init__(self, fxn:Optional[Callable[..., ReturnType]], captured:Optional[CapturedJit]=None, prune=False, optimize=False): - assert fxn or captured, "need either a function or a CapturedJit" - self.fxn = fxn - self.captured: Optional[CapturedJit] = captured - self.cnt: int = 2 if self.fxn is None else 0 - self.prune = prune - self.optimize = optimize - - def add_buffer(self, b:Buffer) -> Buffer: - if found:=self._buffer_replace.get(b, None): return found - if b.is_allocated() or b.lb_refcount > 0: return b - if b._base is not None: - self._buffer_replace[b] = ret = Buffer(b.device, b.size, b.dtype, base=self.add_buffer(b._base), offset=b.offset) - else: - self._buffer_replace[b] = ret = Buffer(b.device, b.size, b.dtype, options=b.options) - return ret - - def add(self, ei:ExecItem): - self._jit_cache.append(ExecItem(ei.prg, [self.add_buffer(buf) for buf in ei.bufs if buf is not None], ei.metadata, ei.fixedvars)) - - def reset(self): - assert self.fxn is not None, "can't reset without function" - self.cnt = 0 - self.captured = None - - def __reduce__(self): - assert self.captured is not None, "can't pickle an uncaptured JIT" - return self.__class__, (None, self.captured) - - # keep legacy code working - @property - def jit_cache(self) -> list[ExecItem]: return self.captured._jit_cache if self.captured is not None else [] - @property - def input_replace(self) -> dict[tuple[int, int], int]: return self.captured._input_replace if self.captured is not None else {} - - def __get__(self, obj, objtype): return functools.partial(self.__call__, obj) # add support for instance methods - - def __call__(self, *args, **kwargs) -> ReturnType: - input_buffers, var_vals, names, st_vars_dtype_device = _prepare_jit_inputs(args, kwargs) - if not JIT or self.cnt == 0: - # jit ignore - assert self.fxn is not None - with Context(BEAM=0 if getenv("IGNORE_JIT_FIRST_BEAM") else BEAM.value): - ret = self.fxn(*args, **kwargs) - if len(params:=get_parameters(ret)): Tensor.realize(params[0], *params[1:]) - elif self.cnt == 1: - # jit capture - assert self.fxn is not None - if capturing: raise RuntimeError(f"having TinyJit inside another TinyJit is not supported {len(capturing)=} {capturing=}") - self._jit_cache: list[ExecItem] = [] - self._buffer_replace: WeakKeyDictionary[Buffer, Buffer] = WeakKeyDictionary() - # TODO: should we always disable the memory planner here? it must be off for prune - with Context(BEAM=getenv("JITBEAM", BEAM.value), NO_MEMORY_PLANNER=int(self.prune)): - capturing.append(self) - try: - ret = self.fxn(*args, **kwargs) - if len(params:=get_parameters(ret)): Tensor.realize(params[0], *params[1:]) - except Exception as e: raise e - finally: capturing.clear() - jit_cache = self._jit_cache - del self._buffer_replace, self._jit_cache - assert len(jit_cache), "didn't JIT anything!" - if DEBUG >= 1: print(f"JIT captured {len(jit_cache)} kernels with {len(input_buffers)} inputs") - - # track inputs that are views of buffers - # TODO: eventually expected_buffers should live in ExecItem - extra_view_inputs: list[tuple[int, int, str, int, DType]] = [] - for item in jit_cache: - for b in item.bufs: - if b is not None and b._base is not None and b._base in input_buffers: - input_buffers.append(b) - extra_view_inputs.append((input_buffers.index(b.base), b.offset, b.device, b.size, b.dtype)) - - # prune independent kernels (optional) - if self.prune: - depends = set(input_buffers) - update_depends(depends, jit_cache) - pruned, onetime = partition(jit_cache, lambda ei: any(b in depends for b in get_out_buffers_for_ei(ei))) - if DEBUG >= 1: print(f"pruned from {len(jit_cache)} -> {len(pruned)} kernels") - # run the onetime kernels here - for ei in onetime: - for b in ei.bufs: cast(Buffer, b).ensure_allocated() - ei.run(var_vals, jit=True) - jit_cache = pruned - - # memory planning (optional) - # Exclude buffers involved in transfer ops to preserve parallelism. - noopt_buffers = {b for ji in jit_cache if isinstance(ji.prg, BufferXfer) for b in ji.bufs} - assigned = _internal_memory_planner([cast(list[Buffer], item.bufs) for item in jit_cache], noopt_buffers, debug_prefix="JIT ") - jit_cache = [ExecItem(item.prg, [assigned.get(b,b).ensure_allocated() for b in item.bufs if b is not None], - item.metadata, item.fixedvars) for item in jit_cache] - - input_replace = get_input_replace(jit_cache, input_buffers) - if DEBUG >= 1 and len(set(input_replace.values())) != len(input_buffers): print("WARNING: some input tensors not found") - - # set this for next run - self.captured = CapturedJit(ret, jit_cache, input_replace, extra_view_inputs, names, st_vars_dtype_device) - if self.optimize: self.captured.replan_buffers_memory_layout() - elif self.cnt >= 2: - # jit exec - assert self.captured is not None - assert self.captured.expected_names == names, f"args mismatch in JIT: {self.captured.expected_names=} != {names}" - assert self.captured.expected_st_vars_dtype_device == st_vars_dtype_device, \ - f"args mismatch in JIT: {self.captured.expected_st_vars_dtype_device=} != {st_vars_dtype_device=}" - ret = self.captured(input_buffers, var_vals) - - self.cnt += 1 - return ret diff --git a/tinygrad/tinygrad/engine/memory.py b/tinygrad/tinygrad/engine/memory.py deleted file mode 100644 index e925972d..00000000 --- a/tinygrad/tinygrad/engine/memory.py +++ /dev/null @@ -1,69 +0,0 @@ -from typing import cast -from collections import defaultdict -from tinygrad.engine.schedule import ScheduleItem -from tinygrad.device import Device, Buffer -from tinygrad.helpers import NO_MEMORY_PLANNER, dedup, DEBUG, round_up -from tinygrad.uop.ops import Ops -from tinygrad.dtype import dtypes, ImageDType -from tinygrad.runtime.support.allocator import TLSFAllocator - -# **************** memory planning **************** - -def _internal_memory_planner(buffers:list[list[Buffer]], noopt_buffers=None, ignore_checks=False, debug_prefix="") -> dict[Buffer, Buffer]: - if NO_MEMORY_PLANNER: return {} - first_appearance, last_appearance, buf_to_opt = {}, {}, set() - for i,u in enumerate(buffers): - for buf in u: - should_skip = buf.is_allocated() or buf.base.is_allocated() or buf.lb_refcount > 0 or (noopt_buffers is not None and buf.base in noopt_buffers) - if not ignore_checks and should_skip: continue - if buf.base not in first_appearance: first_appearance[buf.base] = i - last_appearance[buf.base] = i - buf_to_opt.add(buf) - - # Sort buffer operations in timeline order. Two events: buffer is allocated or buffer is freed. - buffer_requests = sorted([((first_appearance[buf], True), buf) for buf in first_appearance.keys()] + \ - [((last_appearance[buf] + 1, False), buf) for buf in first_appearance.keys()], key=lambda x: x[0]) - - # Try to suballocate from a shared buffer managed by global_planner using TLSFAllocator. - # Also track buffer replacements for buffers that do not support suballocation. - buffer_replace:dict[Buffer, tuple[Buffer|None, int|None]] = {} - reuse_buffers:dict[tuple, list[Buffer]] = defaultdict(list) - global_planner:dict[str, tuple[int, TLSFAllocator]] = defaultdict(lambda: (0, TLSFAllocator(1 << 44, block_size=0x1000, lv2_cnt=32))) - for (_, is_open_ev), buf in buffer_requests: - # Check if suballocation is possible for the given buffer and device. - if hasattr(Device[buf.device].allocator, "_offset") and not isinstance(buf.dtype, ImageDType): - if is_open_ev: buffer_replace[buf] = (None, global_planner[buf.device][1].alloc(round_up(buf.nbytes, 0x1000))) - else: global_planner[buf.device][1].free(cast(int, buffer_replace[buf][1])) - global_planner[buf.device] = (max(global_planner[buf.device][0], buffer_replace[buf][1] + buf.nbytes), global_planner[buf.device][1]) - else: - key = (buf.device, buf.dtype, buf.options, buf.nbytes) - if is_open_ev: buffer_replace[buf] = (reuse_buffers[key].pop(), None) if key in reuse_buffers and len(reuse_buffers[key]) > 0 else (buf, None) - else: reuse_buffers[key].append(cast(Buffer, buffer_replace[buf][0])) - - # Allocate global buffers based on the memory planner. - global_buffers = {dev: Buffer(dev, round_up(sz, 0x1000), dtypes.int8) for dev, (sz, _) in global_planner.items()} - buffer_resolve:dict[Buffer, tuple[Buffer, int|None]] = {buf: (base or global_buffers[buf.device], off) for buf,(base,off) in buffer_replace.items()} - - # Assign buffers. First, assign full buffers (not sub-buffers). - assigned:dict[Buffer, Buffer] = {} - for buf, (base, off) in buffer_resolve.items(): - if buf != base: - assigned[buf] = base if off is None else Buffer(buf.device, buf.size, buf.dtype, base=base, offset=off) - - # Now assign sub-buffers. - for buf in buf_to_opt: - if buf._base is not None: - assigned[buf] = Buffer(buf.device, buf.size, buf.dtype, base=(pbuf:=assigned.get(buf.base, buf.base)).base, offset=pbuf.offset+buf.offset) - - if DEBUG >= 1: - ak, av = dedup(x for x in assigned.keys() if x._base is None),dedup(x for x in assigned.values() if x._base is None)+list(global_buffers.values()) - omem, nmem = sum([x.nbytes for x in ak])/1e6, sum([x.nbytes for x in av])/1e6 - if omem != nmem: print(f"{debug_prefix}memory reduced from {omem:.2f} MB -> {nmem:.2f} MB,", f"{len(ak)} -> {len(av)} bufs") - - return assigned - -def memory_planner(schedule:list[ScheduleItem]) -> list[ScheduleItem]: - # Exclude buffers involved in load ops (e.g transfers) to preserve parallelism in graphs. - assigned = _internal_memory_planner([list(si.bufs) for si in schedule], - noopt_buffers={b for si in schedule if si.ast.op is not Ops.SINK for b in si.bufs}) - return [ScheduleItem(si.ast, tuple(assigned.get(x, x) for x in si.bufs), si.metadata, si.fixedvars) for si in schedule] diff --git a/tinygrad/tinygrad/engine/multi.py b/tinygrad/tinygrad/engine/multi.py deleted file mode 100644 index 0f544e0f..00000000 --- a/tinygrad/tinygrad/engine/multi.py +++ /dev/null @@ -1,204 +0,0 @@ -from typing import cast -import functools, itertools, operator -from tinygrad.helpers import all_same, all_int, prod, DEBUG, RING, getenv, unwrap -from tinygrad.uop.ops import Ops, UOp, sint, PatternMatcher, UPat, GroupOp, resolve - -# *** allreduce implementation *** - -def handle_allreduce(buf:UOp, red:UOp) -> UOp|None: - if not isinstance(buf.device, tuple): return None - assert all_int(buf.shape), f"does not support symbolic shape {buf.shape}" - n_lbs, shape, numel = len(buf.device), buf.shape, prod(buf.shape) - # ring allreduce doesn't provide a benefit with only 2 nodes or where number of elements is less than 256k (empirically) - # fallback to naive allreduce to save on kernel dispatch, chunking and reassembling chunks. - use_ring = (RING >= 2 or (n_lbs > 2 and numel > getenv("RING_ALLREDUCE_THRESHOLD", 256_000) and RING >= 1)) - if DEBUG >= 2: print(f"{'RING ALLREDUCE' if use_ring else 'NAIVE ALLREDUCE'} {n_lbs}x{numel} | {buf.dtype}") - - # contiguous before we copy it - buf = buf.contiguous() - - # copy to all devices. if you shrink later, that'll be handled - if not use_ring: return functools.reduce(lambda x,y: x.alu(red.arg, y), - [UOp(Ops.COPY, buf.dtype, (buf.mselect(i), red.src[1])) for i in range(len(buf.device))]) - - # new ring reduce - factor = next((f for f in [32, 16, 8, 4, 2] if numel % f == 0), 1) - base, left = (numel // factor) // n_lbs, (numel // factor) % n_lbs - chunk_sizes = [(base + 1) * factor] * left + [base * factor] * (n_lbs - left) - chunks = list(itertools.pairwise(itertools.accumulate(chunk_sizes, initial=0))) - - # extract chunks and scatter-reduce - reduced_chunks = [] - for i,(s,e) in enumerate(chunks): - chunk = buf.reshape((numel,)).shrink(((s,e),)) - reduced_chunk = chunk - for step in range(n_lbs-1): - src, dest = (i+step)%n_lbs, (i+step+1)%n_lbs - # copy the chunk from the src device to the dest (operating device), and select the chunk on the dest device - reduced_chunk = reduced_chunk.copy_to_device(buf.device[dest], src if isinstance(reduced_chunk.device, tuple) else None) \ - .alu(red.arg, chunk.copy_to_device(buf.device[dest], dest)) - reduced_chunks.append(reduced_chunk) - - # allgather - copied_chunks = [] - for i,c in enumerate(reduced_chunks): - this_chunk = [None] * len(buf.device) - this_chunk[(i+len(buf.device)-1)%n_lbs] = c - for step in range(n_lbs-1): - dest = (i+step)%n_lbs - this_chunk[dest] = c = c.copy_to_device(buf.device[dest]) - copied_chunks.append(UOp(Ops.MSTACK, buf.dtype, tuple(cast(list[UOp], this_chunk)))) - - # reassemble - pads = [((s,numel-e),) for s,e in chunks] - return functools.reduce(operator.add, [c.pad(pad) for pad,c in zip(pads, copied_chunks)]).reshape(shape) - -# ***** multi rewrite MSELECT/MSTACK ***** - -def _replace_dnum(st, val): - # replace dnum in ShapeTracker with literal const for this mselect - if (dnums:=[x for x in st.vars() if x.op is Ops.DEFINE_VAR and x.arg[0] == '_device_num']): - assert len(dnums) == 1, f"view must have exactly 0 or 1 dnum, got {dnums}" - st = st.substitute({dnums[0]:dnums[0].const_like(val)}) - return st - -def mstack_reorder_view(ms:UOp): - args = [x.arg for x in ms.src] - if not all_same(args) or len([x for x in args[0].vars() if x.arg[0] == '_device_num']) != 0: return None - return UOp(Ops.MSTACK, ms.dtype, tuple(x.src[0] for x in ms.src)).view(args[0]) - -def mstack_early_shrink(view:UOp, ms:UOp): - if resolve(prod(view.shape) >= prod(ms.shape)) or _replace_dnum(view.st, 0) == view.st: return None - ret = [] - for i, x in enumerate(ms.src): - new_view = _replace_dnum(view.st, i) - if x.op is Ops.COPY: - # if src device doesn't have a renderer, we have to view after the copy - # TODO: a way to understand this - if x.src[0].device in {"DISK", "NPY"}: - ret.append(x.view(new_view)) - else: - ret.append(x.src[0].view(new_view).copy_to_device(x.device)) - else: - ret.append(x.view(new_view).contiguous()) - return ms.replace(src=tuple(ret)) - -replace_allreduce = PatternMatcher([ - (UPat(Ops.ALLREDUCE, src=(UPat.var("buf"), UPat()), name="red"), handle_allreduce), - # BROADCAST: explicitly expand broadcast copies and combine with MSTACK - (UPat(Ops.COPY, name="c", src=(UPat(GroupOp.All-{Ops.CONST}, name="x"), UPat(Ops.DEVICE))), lambda c,x: - UOp(Ops.MSTACK, c.dtype, tuple(x.copy_to_device(d) for d in c.device)) if isinstance(c.device, tuple) and isinstance(x.device, str) else None), - # COPY_TO_ONE: if copying from multidevice to one, MSELECT the first (TODO: a little from each?) - (UPat(Ops.COPY, name="c", src=(UPat(GroupOp.All-{Ops.CONST}, name="x"), UPat(Ops.DEVICE))), lambda c,x: - x.mselect(0).copy_to_device(c.device) if isinstance(c.device, str) and isinstance(x.device, tuple) else None), - # MSELECT on MSTACK is replaced with nothing - (UPat(Ops.MSELECT, src=(UPat(Ops.MSTACK, name="mstack"),), name="ms"), lambda mstack, ms: mstack.src[ms.arg]), - # MSELECT must select a base, if there are views apply them after selecting the base - (UPat(Ops.MSELECT, src=(UPat(Ops.VIEW, src=(UPat.var("base"),), name="view"),), name="ms"), lambda ms, view, base: - base.mselect(ms.arg).view(_replace_dnum(unwrap(view.st), ms.arg))), - # move view through MSTACK - (UPat(Ops.MSTACK, src=UPat(Ops.VIEW), name="ms"), mstack_reorder_view), - # move shrink before MSTACK - (UPat(Ops.VIEW, src=(UPat(Ops.MSTACK, name="ms"),), name="view"), mstack_early_shrink), -]) - -# ***** multi functions ***** - -def alu_multi(root:UOp): - msrcs = root.src - assert all_same([x.device for x in msrcs]), f"all buffers must have the same device {[x.device for x in msrcs]}" - axis = root.axis - assert axis is not None - - srcs = [] - for mlb in msrcs: - if mlb.axis == axis: - # same axis, just copy through - assert mlb.op is Ops.MULTI - srcs.append(mlb.src[0]) - elif mlb.axis is None: - # no axis, shard it - assert mlb.op is not Ops.MULTI - srcs.append(mlb._shard(axis)) - else: - # axis mismatch, unshard it, send it to all devices, and shard it correctly - assert mlb.op is Ops.MULTI - srcs.append(mlb.src[0]._unshard(mlb.axis).allreduce(Ops.ADD, mlb.device)._shard(axis)) - return srcs[0].alu(root.op, *srcs[1:]).multi(axis) - -def reduce_multi(root:UOp, multi:UOp): - op, axis = root.arg - if multi.axis is not None and multi.axis in axis: - # all-reduce on sharded axes - return multi.src[0].r(op, axis).allreduce(op, multi.device) - # reduce on non sharded axes, piecewise is fine. if axis is None this is also correct - return multi.src[0].r(op, axis).multi(axis=multi.axis) - -def _shape_to_single_shard(axis, shape:tuple[sint, ...], lb:UOp) -> tuple[sint, ...]: - return tuple(lb.shape[axis] if a == axis else s for a,s in enumerate(shape)) - -def reshape_multi(root:UOp, multi:UOp): - arg = root.arg - if (new_axis:=root.axis) is None: return multi.src[0].reshape(arg).multi(new_axis) - assert prod(multi.shape) == prod(arg), "reshape must maintain prod(shape)" - assert prod(multi.src[0].shape[multi.axis:])%prod(arg[new_axis+1:]) == 0, f"reshape cannot move items between shards {multi.shape} -> {root.arg=}" - new_shape_axis = prod(multi.src[0].shape[multi.axis:]) // prod(arg[new_axis+1:]) - return multi.src[0].reshape(tuple(s if a!=new_axis else new_shape_axis for a,s in enumerate(arg))).multi(new_axis) - -def expand_multi(root:UOp, multi:UOp): - # NOTE: this assert isn't needed, sharded axis can have dim 1 - assert multi.axis is None or root.arg[multi.axis] == multi.shape[multi.axis], f"expand not supported on sharded axis {root.arg=}" - return multi.src[0].expand(_shape_to_single_shard(multi.axis, root.arg, multi.src[0])).multi(multi.axis) - -def pad_multi(root:UOp, multi:UOp): - assert multi.axis is None or root.arg[multi.axis] == (0,0), f"padding not supported for {root.arg=}" - return multi.src[0].pad(root.arg).multi(multi.axis) - -def permute_multi(root:UOp, multi:UOp): - # all permutes supported! - return multi.src[0].permute(root.arg).multi(root.axis) - -def shrink_multi(root:UOp, multi:UOp): - assert multi.axis is None or root.arg[multi.axis] == (0, multi.shape[multi.axis]) or root.arg[multi.axis] in multi.bounds, \ - f"shrinking not supported for {root.arg=}" - if multi.axis is not None and root.arg[multi.axis] in multi.bounds and root.arg[multi.axis] != (0, multi.shape[multi.axis]): - assert all(root.arg[i] == (0, s) or i == multi.axis for i,s in enumerate(multi.shape)), \ - "cannot shrink sharded and non-sharded axis at the same time" - # NOTE: shrink on the shard axis is only allowed when result is a single partition, denoted by the new real - # we just copy it to all the devices, no real. this will be optimized out later - return multi.src[0].copy_to_device(multi.device, arg=multi.bounds.index(root.arg[multi.axis])) - return multi.src[0].shrink(tuple((0, multi.src[0].shape[multi.axis]) if a == multi.axis else s for a,s in enumerate(root.arg))).multi(multi.axis) - -def flip_multi(root:UOp, multi:UOp): - assert multi.axis is None or not root.arg[multi.axis], "flipping not supported on sharded axis" - return multi.src[0].flip(root.arg).multi(multi.axis) - -# from multiple devices -> one -def copy_multi(multi:UOp, device:UOp): - assert multi.axis is not None, "all multi ops have axis" - return multi.src[0]._unshard(multi.axis).allreduce(Ops.ADD, device) - -def assign_multi(dest:UOp, src:UOp): - if dest.axis != src.axis: raise RuntimeError(f"axis must match in assign {dest.axis} != {src.axis}") - return dest.src[0].assign(src.src[0]).multi(src.axis) - -def passthrough_multi(root:UOp, multi:UOp): - return root.replace(src=(multi.src[0],)).multi(multi.axis) - -# NOTE: this is the same pattern as Ops.UNROLL -multi_pm = PatternMatcher([ - (UPat(GroupOp.ALU, name="root", custom_early_reject=set([Ops.MULTI])), alu_multi), - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), reduce_multi), - (UPat(Ops.RESHAPE, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), reshape_multi), - (UPat(Ops.EXPAND, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), expand_multi), - (UPat(Ops.PAD, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), pad_multi), - (UPat(Ops.PERMUTE, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), permute_multi), - (UPat(Ops.SHRINK, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), shrink_multi), - (UPat(Ops.FLIP, src=(UPat(Ops.MULTI, name="multi"), ), name="root"), flip_multi), - (UPat(Ops.ASSIGN, src=(UPat(Ops.MULTI, name="dest"), UPat(Ops.MULTI, name="src"))), assign_multi), - (UPat(Ops.COPY, src=(UPat(Ops.MULTI, name="multi"), UPat(Ops.DEVICE, name="device"))), copy_multi), - (UPat(Ops.ALLREDUCE, src=(UPat(Ops.MULTI, name="multi"), UPat(Ops.DEVICE, name="device")), name="red"), - lambda multi,device,red: multi.src[0].allreduce(red.arg, device).multi(axis=multi.axis)), - (UPat((Ops.CAST, Ops.BITCAST, Ops.CONTIGUOUS, Ops.DETACH, Ops.CONTIGUOUS_BACKWARD, Ops.FUSE), - src=(UPat(Ops.MULTI, name="multi"), ), name="root"), passthrough_multi), -]) diff --git a/tinygrad/tinygrad/engine/realize.py b/tinygrad/tinygrad/engine/realize.py deleted file mode 100644 index fc4352d1..00000000 --- a/tinygrad/tinygrad/engine/realize.py +++ /dev/null @@ -1,187 +0,0 @@ -from typing import Optional, cast, Generator -import time, pprint -from dataclasses import dataclass, replace, field -from tinygrad.helpers import all_same, colored, getenv, DEBUG, GlobalCounters, ansilen, BEAM, NOOPT, all_int, CAPTURING, Metadata, TRACEMETA -from tinygrad.helpers import DEVECTORIZE, time_to_str, VALIDATE_WITH_CPU -from tinygrad.uop.ops import Ops, PatternMatcher, UOp, UPat, Variable, sym_infer -from tinygrad.device import Device, Buffer -from tinygrad.renderer import Renderer, ProgramSpec, Estimates -from tinygrad.codegen.kernel import Kernel -from tinygrad.codegen.heuristic import hand_coded_optimizations -from tinygrad.engine.schedule import ScheduleItem - -# **************** Program Creation **************** - -logkerns, logkerns_level = open(getenv("LOGKERNS", ""), "a") if getenv("LOGKERNS", "") else None, getenv("LOGKERNS_LEVEL", 1) -def get_kernel(renderer:Renderer, ast:UOp) -> Kernel: - k = Kernel(ast, opts=renderer) - if not NOOPT: - if not k.apply_tensor_cores(getenv("TC", 1)): k.apply_opts(hand_coded_optimizations(k)) - if BEAM >= 1: - from tinygrad.engine.search import beam_search, bufs_from_lin - kb = Kernel(ast, opts=renderer) - rawbufs = bufs_from_lin(kb, allocate=False) - k = beam_search(kb, rawbufs, BEAM.value, bool(getenv("BEAM_ESTIMATE", 1))) - if logkerns is not None: logkerns.writelines([f"{(k.ast, k.applied_opts)}\n"]) - return k - -# **************** Runners **************** - -class Runner: - def __init__(self, display_name:str, device:str, estimates=Estimates()): - self.first_run, self.display_name, self.device, self.estimates = True, display_name, device, estimates - @property - def dev(self): return Device[self.device] - def exec(self, rawbufs:list[Buffer], var_vals:Optional[dict[Variable, int]]=None) -> Optional[float]: - return self(rawbufs, {} if var_vals is None else var_vals) - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> Optional[float]: - raise NotImplementedError("override this") - -class CompiledRunner(Runner): - def __init__(self, p:ProgramSpec, precompiled:Optional[bytes]=None, prg=None): - if DEBUG >= 4: print(p.src) - self.p:ProgramSpec = p - self.lib:bytes = precompiled if precompiled is not None else Device[p.device].compiler.compile_cached(p.src) - if DEBUG >= 7: Device[p.device].compiler.disassemble(self.lib) - self._prg = Device[p.device].runtime(p.function_name, self.lib) if prg is None else prg - super().__init__(p.name, p.device, p.estimates) - - def __reduce__(self): return self.__class__, (self.p, self.lib) - - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> Optional[float]: - global_size, local_size = self.p.launch_dims(var_vals) - if global_size is not None and local_size is None and all_int(self.p.global_size): # type: ignore[arg-type] - # TODO: this is copied from get_program - from tinygrad.engine.search import optimize_local_size - local_size = optimize_local_size(self._prg, global_size, rawbufs) - global_size = [g//l if g%l == 0 else g/l for g,l in zip(global_size, local_size)] - self.p = replace(self.p, global_size=global_size, local_size=local_size) - lra = {} - if global_size: - lra['global_size'] = tuple(global_size) - assert len(global_size) == 3, "global size must have len 3" - if local_size: - lra['local_size'] = tuple(local_size) - assert len(local_size) == 3, "local size must have len 3" - return self._prg(*[x._buf for x in rawbufs], **lra, vals=tuple(var_vals[k] for k in self.p.vars), wait=wait) - -class ViewOp(Runner): - def __init__(self, buf:Buffer): super().__init__(colored(f"view {buf.nbytes:8d} @ {buf.offset:<10d}", "yellow"), buf.device) - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False): - assert rawbufs[0]._base is not None and rawbufs[0]._base == rawbufs[1].base, f"must be base {rawbufs}" - -class BufferCopy(Runner): - def __init__(self, total_sz, dest_device, src_device): - if total_sz >= 1e6: name = f"{type(self).__name__[6:].lower()} {total_sz/1e6:7.2f}M, {dest_device[:7]:>7s} <- {src_device[:7]:7s}" - else: name = f"{type(self).__name__[6:].lower()} {total_sz:8d}, {dest_device[:7]:>7s} <- {src_device[:7]:7s}" - super().__init__(colored(name, "yellow"), dest_device, Estimates(lds=total_sz, mem=total_sz)) - def copy(self, dest, src): - disk_supports_fast_copyout = src.device.startswith("DISK") and hasattr(src.allocator.dev, 'io_uring') and \ - getattr(src.allocator.dev, 'fd', None) is not None - if src.device.startswith("DISK") and hasattr(dest.allocator, 'copy_from_disk') and disk_supports_fast_copyout and src.nbytes >= 4096: - dest.allocator.copy_from_disk(dest._buf, src._buf, src.nbytes) - elif src.device.startswith("DISK") and hasattr(dest.allocator, '_as_buffer'): - # fast(ish) path, uses readinto in diskbuffers - src.allocator._copyout(dest.allocator._as_buffer(dest._buf), src._buf) - else: - dest.copyin(src.as_buffer(allow_zero_copy=True)) # may allocate a CPU buffer depending on allow_zero_copy - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False): - dest, src = rawbufs[0:2] - assert dest.size == src.size and dest.dtype == src.dtype, f"buffer copy mismatch, {dest.size} != {src.size}, {dest.dtype} != {src.dtype}" - st = time.perf_counter() - self.copy(dest, src) - if wait: - Device[dest.device].synchronize() - return time.perf_counter() - st - -class BufferXfer(BufferCopy): - def copy(self, dest, src): dest.allocator._transfer(dest._buf, src._buf, dest.nbytes, src_dev=src.allocator.dev, dest_dev=dest.allocator.dev) - -# **************** method cache **************** - -method_cache: dict[tuple[str, bytes, tuple[int, ...], bool], CompiledRunner] = {} -def get_runner(device:str, ast:UOp) -> CompiledRunner: - # TODO: this should be all context relevant to rendering - context = (BEAM.value, NOOPT.value, DEVECTORIZE.value) - ckey = (device, ast.key, context, False) - if cret:=method_cache.get(ckey): return cret - bkey = (device.split(":")[0], ast.key, context, True) - if bret:=method_cache.get(bkey): - method_cache[ckey] = ret = CompiledRunner(replace(bret.p, device=device), bret.lib) - else: - prg: ProgramSpec = get_kernel(Device[device].renderer, ast).to_program() - method_cache[ckey] = method_cache[bkey] = ret = CompiledRunner(replace(prg, device=device)) - return ret - -# **************** lowering functions **************** - -@dataclass(frozen=True) -class ExecItem: - prg: Runner - bufs: list[Optional[Buffer]] - metadata: Optional[tuple[Metadata, ...]] = None - fixedvars: dict[Variable, int] = field(default_factory=dict) - def run(self, _var_vals:Optional[dict[Variable, int]]=None, wait=False, jit=False, do_update_stats=True) -> Optional[float]: - var_vals = self.fixedvars if _var_vals is None else (_var_vals|self.fixedvars) - bufs = [cast(Buffer, x) for x in self.bufs] if jit else [cast(Buffer, x).ensure_allocated() for x in self.bufs] - et = self.prg(bufs, var_vals, wait=wait or DEBUG >= 2) - if do_update_stats: - GlobalCounters.kernel_count += 1 - GlobalCounters.global_ops += (op_est:=sym_infer(self.prg.estimates.ops, var_vals)) - GlobalCounters.global_mem += (mem_est:=sym_infer(self.prg.estimates.mem, var_vals)) - if et is not None: GlobalCounters.time_sum_s += et - if DEBUG >= 2: - lds_est = sym_infer(self.prg.estimates.lds, var_vals) - mem_est = min(mem_est, lds_est) # there can't be more memory accessed than loads/stores. remove this when symbolic is fixed - ptm = colored(time_to_str(et, w=9), "yellow" if et > 0.01 else None) if et is not None else "" - print(f"{colored(f'*** {self.prg.device[:7]:7s} {GlobalCounters.kernel_count:4d}', 'magenta' if jit else ('green' if self.prg.first_run else None))} {self.prg.display_name+' '*(41-ansilen(self.prg.display_name))} arg {len(bufs):2d} mem {GlobalCounters.mem_used/1e9:5.2f} GB " + # noqa: E501 - (str() if et is None else f"tm {ptm}/{GlobalCounters.time_sum_s*1e3:9.2f}ms ({op_est/((et or 1e-20)*1e9):9.2f} GFLOPS {mem_est/((et or 1e-20)*1e9):6.1f}|{lds_est/((et or 1e-20)*1e9):<7.1f} GB/s)" + # noqa: E501 - f" {[repr(m) if TRACEMETA >= 2 else str(m) for m in self.metadata] if self.metadata else ''}")) - self.prg.first_run = False - return et - -# NOTE: ctx is the buffers -si_lowerer = PatternMatcher([ - (UPat(Ops.SINK, name="sink"), lambda ctx,sink: (runner:=get_runner(ctx[0].device, sink), [ctx[x] for x in runner.p.globals])), - (UPat(Ops.BUFFER_VIEW), lambda ctx: (ViewOp(ctx[0]), list(ctx))), - (UPat(Ops.COPY, name="copy"), lambda ctx,copy: ((BufferXfer(ctx[0].nbytes, ctx[0].device, ctx[1].device) \ - if hasattr(Device[ctx[0].device].allocator, '_transfer') and all_same([x.device.split(":")[0] for x in ctx]) \ - else BufferCopy(ctx[0].nbytes, ctx[0].device, ctx[1].device)), list(ctx))), -]) -def lower_schedule_item(si:ScheduleItem) -> ExecItem: - return ExecItem(*cast(tuple[Runner,list], si_lowerer.rewrite(si.ast, si.bufs)), si.metadata, si.fixedvars) - -def lower_schedule(schedule:list[ScheduleItem]) -> Generator[tuple[ScheduleItem, ExecItem], None, None]: - while len(schedule): - si = schedule.pop(0) - try: yield (si, lower_schedule_item(si)) - except Exception as e: - if DEBUG >= 2: - print(f"error lowering {si.ast.op}") - print("tensor operations:") - pprint.pprint(si.metadata, indent=2) - raise e - -# **************** main run function **************** - -capturing: list = [] # put classes with an add method in here - -def run_schedule(schedule:list[ScheduleItem], var_vals:Optional[dict[Variable, int]]=None, do_update_stats=True): - for si, ei in lower_schedule(schedule): - if len(capturing) and CAPTURING: capturing[0].add(ei) - if VALIDATE_WITH_CPU and si.ast.op is Ops.SINK: - # copy in allocated buffers from the GPU - nb: tuple[Buffer, ...] = tuple(Buffer("CPU", b.size, b.dtype) for b in si.bufs) - for cpu_b, gpu_b in zip(nb, si.bufs): - if gpu_b.is_allocated(): cpu_b.ensure_allocated().copyin(gpu_b.as_buffer()) - - # run on GPU - ei.run(var_vals, do_update_stats=do_update_stats) - - # validate the output buffers match (NOTE: this is assuming the output is buffer 0) - lower_schedule_item(ScheduleItem(si.ast, nb, si.metadata, si.fixedvars)).run(var_vals, do_update_stats=do_update_stats) - import numpy as np - np.testing.assert_allclose(si.bufs[0].numpy(), nb[0].numpy(), rtol=1e-3, atol=1e-3) - else: - ei.run(var_vals, do_update_stats=do_update_stats) - diff --git a/tinygrad/tinygrad/engine/schedule.py b/tinygrad/tinygrad/engine/schedule.py deleted file mode 100644 index 9a64639b..00000000 --- a/tinygrad/tinygrad/engine/schedule.py +++ /dev/null @@ -1,91 +0,0 @@ -from typing import cast -from dataclasses import dataclass, field -from collections import deque, defaultdict -from tinygrad.uop.ops import UOp, Variable, Ops, UPat, PatternMatcher, graph_rewrite, buffers -from tinygrad.device import Buffer, MultiBuffer -from tinygrad.helpers import Metadata, unwrap, merge_dicts - -# **** ScheduleItem return type - -@dataclass(frozen=True) -class ScheduleItem: - ast: UOp - bufs: tuple[Buffer, ...] - metadata: tuple[Metadata, ...] = () - fixedvars: dict[Variable, int] = field(default_factory=dict) - -# **** unbind Variables - -def unbind_view(ctx:list[dict[Variable, int]], x:UOp): - st = unwrap(x.st).simplify() - if any(x.op is Ops.BIND for x in st.vars()): - st, var_vals = st.unbind() - ctx.append(var_vals) - return x.replace(arg=st) - return None - -def unbind_bind(ctx:list[dict[Variable, int]], x:UOp): - var, val = x.unbind() - ctx.append({var.replace(src=()):val}) - return var - -pm_unbind = PatternMatcher([ - (UPat(Ops.VIEW, name="x"), unbind_view), - (UPat(Ops.BIND, name="x"), unbind_bind), -]) - -# **** schedule linearizer - -def create_schedule_with_vars(sched_sink:UOp) -> tuple[list[ScheduleItem], dict[Variable, int]]: - # construct the KERNEL children graph based on assigns - children: defaultdict[UOp, list[UOp]] = defaultdict(list) - in_degree: dict[UOp, int] = {} - for u in sched_sink.toposort(): - if u.op is not Ops.ASSIGN: continue # anything that's not an ASSIGN doesn't write a kernel, so we can skip - k = u.src[1] - in_degree.setdefault(k, 0) - for s in k.src: - if s.op is Ops.ASSIGN: - children[s.src[1]].append(k) - in_degree[k] += 1 - elif s.op in {Ops.MSELECT, Ops.MSTACK}: - for ss in s.src: - if ss.op is Ops.MSELECT: ss = ss.src[0] - if ss.op is not Ops.BUFFER: - assert ss.op is Ops.ASSIGN - children[ss.src[1]].append(k) - in_degree[k] += 1 - elif s.op is Ops.BUFFER: - pass # a BUFFER is already realized, nothing to do here - else: - raise RuntimeError(f"input to kernel must be ASSIGN or BUFFER, not {s.op}") - - # linearize KERNEL UOps into ScheduleItems in BFS order - queue = deque(k for k,v in in_degree.items() if v == 0) - schedule: list[ScheduleItem] = [] - var_vals: dict[Variable, int] = {} - while queue: - k = queue.popleft() - # unbind var_vals from the kernel - local_var_vals: list[dict[Variable, int]] = [] - ast = graph_rewrite(k.arg.ast, pm_unbind, ctx=local_var_vals, name="unbind vars") - var_vals = merge_dicts([var_vals, *local_var_vals]) - # create subbuffers if needed - if ast.op is Ops.BUFFER_VIEW: - base = k.src[1].buf_uop.buffer - assert isinstance(base, Buffer), "base can't be MultiBuffer" - buffers[k.src[0]] = base.view(k.size, ast.dtype, ast.arg[1]*base.dtype.itemsize) - ubufs = tuple(s.buf_uop.buffer for s in k.src) - if any(isinstance(x, MultiBuffer) for x in ubufs): - assert all(isinstance(x, MultiBuffer) for x in ubufs), "kernel must all be multibuffer" - dnums = [x for x in ast.variables() if x.arg[0] == '_device_num'] - for i,bufs in enumerate(zip(*[x.bufs for x in cast(tuple[MultiBuffer, ...], ubufs)])): - schedule.append(ScheduleItem(ast, bufs, k.arg.metadata, {dnums[0]:i} if len(dnums) else {})) - else: - # ONE -> ONE - schedule.append(ScheduleItem(ast, cast(tuple[Buffer, ...], ubufs), k.arg.metadata)) - for x in children[k]: - in_degree[x] -= 1 - if in_degree[x] == 0: queue.append(x) - - return schedule, var_vals diff --git a/tinygrad/tinygrad/engine/search.py b/tinygrad/tinygrad/engine/search.py deleted file mode 100644 index 9e92df35..00000000 --- a/tinygrad/tinygrad/engine/search.py +++ /dev/null @@ -1,210 +0,0 @@ -from typing import cast, Optional, Callable -import itertools, functools, random, math, time, multiprocessing, traceback, signal, atexit -from collections import defaultdict -from dataclasses import replace -from tinygrad.uop.ops import UOp, Ops, Variable, sym_infer -from tinygrad.device import Device, Buffer, Compiler -from tinygrad.helpers import prod, flatten, DEBUG, CACHELEVEL, diskcache_get, diskcache_put, getenv, Context, colored, time_to_str -from tinygrad.helpers import IGNORE_BEAM_CACHE, TC_SEARCH_OVER_SHAPE -from tinygrad.dtype import ImageDType, PtrDType -from tinygrad.codegen.kernel import Kernel, Opt, OptOps, KernelOptError -from tinygrad.tensor import Tensor -from tinygrad.engine.realize import CompiledRunner -from tinygrad.renderer import ProgramSpec - -actions = [Opt(op=OptOps.UPCAST, axis=axis, arg=amt) for amt in [0,2,3,4,5,7] for axis in range(6)] -actions += [Opt(op=OptOps.UNROLL, axis=axis, arg=amt) for amt in [0,4,7] for axis in range(5)] -actions += [Opt(op=OptOps.LOCAL, axis=axis, arg=amt) for amt in [2,3,4,8,13,16,29] for axis in range(6)] -actions += [Opt(op=OptOps.GROUPTOP, axis=axis, arg=amt) for amt in [13,16,28,29,32,49,64,256] for axis in range(3)] -actions += [Opt(op=OptOps.GROUP, axis=axis, arg=amt) for amt in [0,4,8,16] for axis in range(3)] -if getenv("BEAM_PADTO", 1): actions += [Opt(op=OptOps.PADTO, axis=axis, arg=amt) for amt in [32] for axis in range(7)] -actions += [Opt(op=OptOps.LOCAL, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=6, arg=2)] -actions += [Opt(op=OptOps.TC, axis=0, arg=(-1, 0, getenv("TC", 1)))] -# covers resnet kernels (3 global * 3 reduce) -actions += [Opt(op=OptOps.TC, axis=axis, arg=(-1, getenv("TC_OPT", 2), getenv("TC", 1))) for axis in range(9)] -actions += [Opt(op=OptOps.SWAP, axis=axis_0, arg=axis_1) for axis_0 in range(5) for axis_1 in range(axis_0+1, 5)] -if getenv("NOLOCALS"): actions += [Opt(op=OptOps.NOLOCALS)] - -def get_test_global_size(global_size, max_global_size, var_vals): - test_global_size = [sym_infer(sz, var_vals) for sz in global_size] - input_size = prod(test_global_size) - while prod(test_global_size) > max_global_size: - for j in range(len(global_size)-1,-1,-1): - if test_global_size[j] > 16: - test_global_size[j] //= 2 - break - return test_global_size, input_size / prod(test_global_size) - -def _time_program(p:ProgramSpec, lib:bytes, var_vals:dict[Variable, int], rawbufs:list[Buffer], early_stop:Optional[float]=None, - allow_test_size:int=True, max_global_size:Optional[int]=65536, clear_l2=False, cnt=3, name="test") -> list[float]: - factor = 1 - if allow_test_size and p.global_size is not None and max_global_size is not None: - global_size, factor = get_test_global_size(p.global_size, max_global_size, var_vals) - p = replace(p, global_size=global_size) - try: car = CompiledRunner(p, precompiled=lib) - except AssertionError: return [math.inf] * cnt - tms = [] - input_bufs = [rawbufs[i] for i in car.p.globals] - for _ in range(cnt): - if clear_l2: - if hasattr(dev:=Device[p.device], 'invalidate_caches'): dev.invalidate_caches() - else: - with Context(DEBUG=0, BEAM=0, CAPTURING=0, TRACK_MATCH_STATS=0): Tensor.ones(1024,1024).contiguous().realize(do_update_stats=False) - tms.append(cast(float, car(input_bufs, var_vals, wait=True))*factor) - if early_stop is not None and early_stop < min(tms): break - return tms - -class TimeoutException(Exception): pass -def timeout_handler(signum, frame): raise TimeoutException() - -def _try_compile_linearized_w_idx(x:tuple[int,Kernel], compiler:Compiler) -> tuple[int, Optional[tuple[ProgramSpec, bytes, float]]]: - if hasattr(signal, "alarm"): - signal.signal(getattr(signal, 'SIGALRM'), timeout_handler) - # set timeout - signal.alarm(getenv("BEAM_TIMEOUT_SEC", 10)) - ret = None - try: - p = x[1].to_program(name_override="test") - assert p.uops is not None, "uop list wasn't generated?" - if len(p.uops) >= (uops_max:=getenv("BEAM_UOPS_MAX", 3000)) > 0: - if getenv("BEAM_LOG_SURPASS_MAX"): print(f"too many uops. {len(p.uops)=}, {uops_max=}") - raise RuntimeError("too many uops") - st = time.perf_counter() - prog = compiler.compile(p.src) - et = time.perf_counter() - st - ret = (p, prog, et) - except RuntimeError: - if DEBUG >= 4: traceback.print_exc() - except Exception as e: - if getenv("BEAM_STRICT_MODE"): raise e - finally: - if hasattr(signal, "alarm"): signal.alarm(0) - return x[0], ret - -# workers should not open devices and should ignore ctrl c -def _init_worker(): - Context(ALLOW_DEVICE_USAGE=0).__enter__() - signal.signal(signal.SIGINT, signal.SIG_IGN) - -def _ensure_buffer_alloc(bufs:list[Buffer]) -> list[Buffer]: return [buf.ensure_allocated() if buf is not None else buf for buf in bufs] - -# *** external API *** - -# get (scrap) buffers for timing the linearizer -def bufs_from_lin(lin:Kernel, allocate:bool=True) -> list[Buffer]: - bufsts: defaultdict[int, list[UOp]] = defaultdict(list) - for x in lin.bufs: - if x.src[0].base.op is Ops.DEFINE_GLOBAL: bufsts[x.src[0].base.arg].append(x) - # TODO: Nones are staying in here if buffers are optimized out! - # TODO: add a test for this - rawbufs: list[Optional[Buffer]] = [None]*(max(bufsts)+1) - for k,lx in bufsts.items(): - buf_size = prod(dtype.shape) if isinstance(dtype:=lx[0].src[0].dtype, ImageDType) else max(y.st_arg.real_size() for y in lx) - assert isinstance(dtype, (PtrDType, ImageDType)) - if buf_size == 0: buf_size = 1 # create a size 1 buffer if no cell is accessed in kernel. # TODO: remove from kernel input in this case. - buf_dtype = dtype if isinstance(dtype, ImageDType) else dtype.base - rawbufs[k] = Buffer(lin.opts.device, buf_size, buf_dtype).allocate() if allocate else Buffer(lin.opts.device, buf_size, buf_dtype) - #assert all(r is not None for r in rawbufs) - return cast(list[Buffer], rawbufs) - -# get dictionary of all possible actions -def get_kernel_actions(lin:Kernel, include_0=True) -> dict[int, Kernel]: - acted_lins, max_up, max_lcl = {0:lin} if include_0 else {}, getenv("BEAM_UPCAST_MAX", 256), getenv("BEAM_LOCAL_MAX", 1024) - kernel_actions = actions.copy() - - if TC_SEARCH_OVER_SHAPE and len(lin.applied_opts) == 0: # tensor core opts must be first - for i, action in enumerate(kernel_actions): - if action.op == OptOps.TC and (tc_arg := cast(tuple, action.arg))[0] == -1: - # replace every tc_action with default tc with one tc_action for each available tc - kernel_actions[i:i+1] = \ - [Opt(op=OptOps.TC, axis=action.axis, arg=(tc_select, tc_arg[1], tc_arg[2])) for tc_select,_ in enumerate(lin.opts.tensor_cores)] - - for i,a in enumerate(kernel_actions): - if a.axis is not None and a.op is not OptOps.TC: - if ((ax:=lin.real_axis(a)) >= lin.shape_len) or (lin.full_shape[ax] == a.arg and Opt(a.op, ax, 0) in kernel_actions): continue - lin2 = lin.copy() - try: - lin2.apply_opt(a) - up, lcl, tc_up = 1, 1, prod(tc.dims)//tc.threads if (tc:=lin2.tensor_core) else 1 - for s,c in zip(lin2.full_shape, lin2.colors()): - if c in {"magenta", "yellow"}: up *= s - elif c in {"cyan", "green", "white"}: lcl *= s - if up//tc_up > max_up or lcl > max_lcl: - if getenv("BEAM_LOG_SURPASS_MAX"): print(f"too many upcast/local. {up//tc_up=}, {max_up=}, {lcl=}, {max_lcl=}") - continue - acted_lins[i+1] = lin2 - except KernelOptError: pass - return acted_lins - -beam_pool, BEAM_DEBUG = None, getenv("BEAM_DEBUG") -def beam_search(lin:Kernel, rawbufs:list[Buffer], amt:int, allow_test_size=True, disable_cache=IGNORE_BEAM_CACHE.value) -> Kernel: - global beam_pool - key = {"ast": lin.ast.key, "amt": amt, "allow_test_size": allow_test_size, "device": lin.opts.device, "suffix": lin.opts.suffix} - if not disable_cache and CACHELEVEL >= 1 and (val:=diskcache_get("beam_search", key)) is not None: - ret = lin.copy() - for o in val[len(lin.applied_opts):]: ret.apply_opt(o) - return ret - - beam: list[tuple[Kernel, float]] = [(lin, float("inf"))] - seen_libs = set() - - default_parallel = multiprocessing.cpu_count() if lin.opts.device in {"CUDA", "AMD", "NV", "METAL", "HIP"} else 0 - if beam_pool is None and (workers := getenv("PARALLEL", default_parallel)): - beam_pool = multiprocessing.get_context("spawn").Pool(workers, _init_worker, (), getenv("BEAM_MAX_TASKS_PER_CHILD", 16)) - @atexit.register - def close_pool(): beam_pool.close() - - min_progress = getenv("BEAM_MIN_PROGRESS", 0.01)/1e6 - if BEAM_DEBUG: print(f"BEAM_SEARCH:\n{lin.ast}") - if DEBUG >= 2: print(f" 0.00s: from 1 -> 1 actions {lin.colored_shape()}") - - try: - rawbufs = _ensure_buffer_alloc(rawbufs) - var_vals: dict[Variable, int] = {k:int(k.vmax+k.vmin)//2 for k in lin.ast.variables()} - exiting, st = False, time.perf_counter() - dev = Device[lin.opts.device] - while not exiting: - acted_lins: list[Kernel] = flatten([get_kernel_actions(lin, include_0=False).values() for lin,_ in beam]) - timed_lins: list[tuple[Kernel, float]] = [] - _compile_fn = functools.partial(_try_compile_linearized_w_idx, compiler=dev.compiler) - least_compute_ops = math.inf - for i,proc in (map(_compile_fn, enumerate(acted_lins)) if beam_pool is None else beam_pool.imap_unordered(_compile_fn, enumerate(acted_lins))): - if proc is None: continue - p, lib, compile_et = proc - if lib in seen_libs: continue - # filter out kernels that use 1000x more compute than the smallest - least_compute_ops = min(this_compute_ops:=sym_infer(p.estimates.ops, var_vals), least_compute_ops) - if least_compute_ops*1000 < this_compute_ops: continue - seen_libs.add(lib) - try: tms = _time_program(p, lib, var_vals, rawbufs, early_stop=beam[0][1]*3 if len(beam) else 1.0, - allow_test_size=allow_test_size, clear_l2=hasattr(dev, 'invalidate_caches')) - except RuntimeError: continue # for runtime issues - timed_lins.append((acted_lins[i], min(tms))) - if BEAM_DEBUG > 1: print(f"{time.perf_counter() - st:7.2f}s: {i:5d} {len(cast(list, p.uops)):5d} uops {time_to_str(compile_et, w=12)} compile/{time_to_str(timed_lins[-1][1], w=12)} run {len(timed_lins):4d}/{len(acted_lins):4d} {timed_lins[-1][0].colored_shape()}") # noqa: E501 - elif DEBUG >= 2: print(f"\r{time.perf_counter() - st:7.2f}s: {time_to_str(timed_lins[-1][1], w=12)} {len(timed_lins):4d}/{len(acted_lins):4d} {timed_lins[-1][0].colored_shape()}\033[K", end="") # noqa: E501 - - # done - opts = sorted(timed_lins, key=lambda x: x[1]) - exiting = len(opts) == 0 or (opts[0][1] < min_progress) or (len(beam) > 0 and ((beam[0][1]-opts[0][1]) < min_progress)) - if not exiting: beam = opts[:amt] - elif len(opts) > 0 and opts[0][1] < beam[0][1]: beam = opts[:1] - if DEBUG >= 2: print(f"\r{time.perf_counter() - st:7.2f}s:", colored(time_to_str(beam[0][1], w=12), "green" if exiting else None), f"from {len(acted_lins):3d} -> {len(opts):3d} actions\033[K", beam[0][0].colored_shape()) # noqa: E501 - except KeyboardInterrupt as e: - if beam_pool is not None: beam_pool.terminate() - raise e - - if CACHELEVEL >= 1: diskcache_put("beam_search", key, beam[0][0].applied_opts) - if BEAM_DEBUG: print(f"BEAM_SEARCH: final tm={time_to_str(beam[0][1], w=0)}, applied_opts={beam[0][0].applied_opts}") - return beam[0][0] - -def optimize_local_size(_prg:Callable, global_size:list[int], rawbufs:list[Buffer]) -> list[int]: - test_rawbuffers = [Buffer(rawbufs[0].device, rawbufs[0].size, rawbufs[0].dtype).allocate(), *rawbufs[1:]] if rawbufs[0] in rawbufs[1:] else rawbufs - MAX_WORKGROUP = 1024 - local_dims = [[x for x in set([sz, 1, 2, 4, 8, 16, 32, 64, 128, 256, MAX_WORKGROUP]) if x<=sz] for sz in global_size] - local_sizes = [list(x) for x in itertools.product(*local_dims) if prod(x) <= MAX_WORKGROUP] * 2 # try each valid size twice - def try_exec(local_size): - try: return _prg(*[x._buf for x in test_rawbuffers], global_size=[g//l if g%l == 0 else g/l for g,l in zip(global_size, local_size)], local_size=local_size, wait=True) # noqa: E501 - except Exception: return float('inf') - ret = min([(try_exec(local_size), local_size) for local_size in random.sample(local_sizes, len(local_sizes))]) - assert not math.isinf(ret[0]), "all optimize_local_size exec failed" - return ret[1] diff --git a/tinygrad/tinygrad/frontend/__init__.py b/tinygrad/tinygrad/frontend/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/frontend/onnx.py b/tinygrad/tinygrad/frontend/onnx.py deleted file mode 100644 index db34a70b..00000000 --- a/tinygrad/tinygrad/frontend/onnx.py +++ /dev/null @@ -1,7 +0,0 @@ -# type: ignore -import sys, pathlib -sys.path.append(pathlib.Path(__file__).parent.parent.as_posix()) -try: - from extra.onnx import OnnxRunner # noqa: F401 # pylint: disable=unused-import - from extra.onnx_parser import onnx_load # noqa: F401 # pylint: disable=unused-import -except ImportError as e: raise ImportError("onnx frontend not in release\nTo fix, install tinygrad from a git checkout with pip install -e .") from e \ No newline at end of file diff --git a/tinygrad/tinygrad/frontend/torch.py b/tinygrad/tinygrad/frontend/torch.py deleted file mode 100644 index 079256f6..00000000 --- a/tinygrad/tinygrad/frontend/torch.py +++ /dev/null @@ -1,5 +0,0 @@ -# type: ignore -import sys, pathlib -sys.path.append(pathlib.Path(__file__).parent.parent.as_posix()) -try: import extra.torch_backend.backend # noqa: F401 # pylint: disable=unused-import -except ImportError as e: raise ImportError("torch frontend not in release\nTo fix, install tinygrad from a git checkout with pip install -e .") from e \ No newline at end of file diff --git a/tinygrad/tinygrad/gradient.py b/tinygrad/tinygrad/gradient.py deleted file mode 100644 index 6936ebdc..00000000 --- a/tinygrad/tinygrad/gradient.py +++ /dev/null @@ -1,67 +0,0 @@ -from typing import cast -import math, dataclasses -from tinygrad.dtype import dtypes, sum_acc_dtype -from tinygrad.uop.ops import UOp, PatternMatcher, UPat, Ops, all_metadata -from tinygrad.helpers import argsort - -def reduce_gradient(ctx:UOp, ret:UOp): - if ret.arg[0] == Ops.ADD: return (ctx.expand(ret.src[0].shape),) - if ret.arg[0] == Ops.MAX: - max_is_1s = ret.src[0].ne(ret.expand(ret.src[0].shape)).ne(ret.src[0].const_like(1).cast(dtypes.bool)).cast(ctx.dtype) - div = max_is_1s.r(Ops.ADD, ret.arg[1]).expand(ret.src[0].shape) - return ((max_is_1s/div) * ctx.expand(ret.src[0].shape),) - if ret.arg[0] == Ops.MUL: return ((ctx * ret).expand(ret.src[0].shape) / ret.src[0],) - -# ctx is grad_output -pm_gradient = PatternMatcher([ - (UPat(Ops.CAST, name="ret"), lambda ctx, ret: (ctx.cast(ret.src[0].dtype),)), - (UPat(Ops.RECIP, name="ret"), lambda ctx, ret: (-ctx * ret * ret,)), - (UPat(Ops.SIN, name="ret"), lambda ctx, ret: ((math.pi/2 - ret.src[0]).sin() * ctx,)), - (UPat(Ops.LOG2, name="ret"), lambda ctx, ret: (ctx / (ret.src[0] * math.log(2)),)), - (UPat(Ops.EXP2, name="ret"), lambda ctx, ret: (ret * ctx * math.log(2),)), - (UPat(Ops.SQRT, name="ret"), lambda ctx, ret: (ctx / (ret*2),)), - (UPat((Ops.CMPLT, Ops.CMPNE)), lambda: (None, None)), - (UPat(Ops.ADD), lambda ctx: (ctx, ctx)), - (UPat(Ops.POW, name="ret"), lambda ctx, ret: - (ctx*(ret.src[0].eq(0) & ret.src[1].eq(0)).where(ret.src[1], ret.src[1]*ret.src[0].pow(ret.src[1]-1)), - ctx*ret.src[0].eq(0).where((ret.src[1]<0).where(ret.const_like(-math.inf), ret.const_like(0)), ret*ret.src[0].log2()*math.log(2.0)))), - (UPat(Ops.MAX, name="ret"), lambda ctx, ret: ((ret.src[0]>ret.src[1]).where(ctx, (ret.src[0]!=ret.src[1]).where(ctx.const_like(0), ctx * 0.5)), - (ret.src[0] list[UOp]: - # compute the target path (top down) - in_target_path: dict[UOp, bool] = {} - for u in root.toposort(): in_target_path[u] = any(x in targets or in_target_path[x] for x in u.src) - # don't flow through DETACH/ASSIGN or anything not in target path - return list(root.toposort(lambda node: node.op not in {Ops.DETACH, Ops.ASSIGN} and in_target_path[node])) - -def compute_gradient(root:UOp, root_grad:UOp, targets:set[UOp]) -> dict[UOp, UOp]: - grads = {root: root_grad} - for t0 in reversed(_deepwalk(root, targets)): - if t0 not in grads: continue - lgrads: tuple[UOp|None, ...]|None = cast(tuple[UOp, ...]|None, pm_gradient.rewrite(t0, ctx=grads[t0])) - if lgrads is None: raise RuntimeError(f"failed to compute gradient for {t0.op}\n\nin {str(t0)[0:1000]}...") - assert len(lgrads) == len(t0.src), f"got {len(lgrads)} gradient, expected {len(t0.src)}" - for k,v in zip(t0.src, lgrads): - if v is None: continue - if k in grads: grads[k] = grads[k] + v - else: grads[k] = v - if len(forward_metadata:=all_metadata.get(t0, ())): all_metadata[v] = tuple(dataclasses.replace(x, backward=True) for x in forward_metadata) - return grads diff --git a/tinygrad/tinygrad/helpers.py b/tinygrad/tinygrad/helpers.py deleted file mode 100644 index 1c2f7ff3..00000000 --- a/tinygrad/tinygrad/helpers.py +++ /dev/null @@ -1,352 +0,0 @@ -from __future__ import annotations -import os, functools, platform, time, re, contextlib, operator, hashlib, pickle, sqlite3, tempfile, pathlib, string, ctypes, sys, gzip, getpass -import urllib.request, subprocess, shutil, math, types, copyreg, inspect, importlib -from dataclasses import dataclass -from typing import Union, ClassVar, Optional, Iterable, Any, TypeVar, Callable, Sequence, TypeGuard, Iterator, Generic - -T = TypeVar("T") -U = TypeVar("U") -# NOTE: it returns int 1 if x is empty regardless of the type of x -def prod(x:Iterable[T]) -> Union[T,int]: return functools.reduce(operator.mul, x, 1) - -# NOTE: helpers is not allowed to import from anything else in tinygrad -OSX = platform.system() == "Darwin" -CI = os.getenv("CI", "") != "" - -# fix colors on Windows, https://stackoverflow.com/questions/12492810/python-how-can-i-make-the-ansi-escape-codes-to-work-also-in-windows -if sys.platform == "win32": os.system("") - -def dedup(x:Iterable[T]): return list(dict.fromkeys(x)) # retains list order -def argfix(*x): - if x and x[0].__class__ in (tuple, list): - if len(x) != 1: raise ValueError(f"bad arg {x}") - return tuple(x[0]) - return x -def argsort(x): return type(x)(sorted(range(len(x)), key=x.__getitem__)) # https://stackoverflow.com/questions/3382352/equivalent-of-numpy-argsort-in-basic-python -def all_same(items:Union[tuple[T, ...], list[T]]): return all(x == items[0] for x in items) -def all_int(t: Sequence[Any]) -> TypeGuard[tuple[int, ...]]: return all(isinstance(s, int) for s in t) -def colored(st, color:Optional[str], background=False): return f"\u001b[{10*background+60*(color.upper() == color)+30+['black', 'red', 'green', 'yellow', 'blue', 'magenta', 'cyan', 'white'].index(color.lower())}m{st}\u001b[0m" if color is not None else st # replace the termcolor library with one line # noqa: E501 -def colorize_float(x: float): return colored(f"{x:7.2f}x", 'green' if x < 0.75 else 'red' if x > 1.15 else 'yellow') -def time_to_str(t:float, w=8) -> str: return next((f"{t * d:{w}.2f}{pr}" for d,pr in [(1, "s "),(1e3, "ms")] if t > 10/d), f"{t * 1e6:{w}.2f}us") -def ansistrip(s:str): return re.sub('\x1b\\[(K|.*?m)', '', s) -def ansilen(s:str): return len(ansistrip(s)) -def make_tuple(x:Union[int, Sequence[int]], cnt:int) -> tuple[int, ...]: return (x,)*cnt if isinstance(x, int) else tuple(x) -def flatten(l:Iterable[Iterable[T]]): return [item for sublist in l for item in sublist] -def fully_flatten(l): - if hasattr(l, "__len__") and hasattr(l, "__getitem__") and not isinstance(l, str): - if hasattr(l, "shape") and l.shape == (): return [l[()]] - flattened = [] - for li in l: flattened.extend(fully_flatten(li)) - return flattened - return [l] -def fromimport(mod, frm): return getattr(__import__(mod, fromlist=[frm]), frm) -def strip_parens(fst:str): return fst[1:-1] if fst[0] == '(' and fst[-1] == ')' and fst[1:-1].find('(') <= fst[1:-1].find(')') else fst -def ceildiv(num, amt): return int(ret) if isinstance((ret:=-(num//-amt)), float) else ret -def round_up(num:int, amt:int) -> int: return (num+amt-1)//amt * amt -# cstyle div and mod -def cdiv(x:int, y:int) -> int: return abs(x)//abs(y)*(1,-1)[x*y<0] if y != 0 else 0 -def cmod(x:int, y:int) -> int: return x-cdiv(x,y)*y -def lo32(x:Any) -> Any: return x & 0xFFFFFFFF # Any is sint -def hi32(x:Any) -> Any: return x >> 32 # Any is sint -def data64(data:Any) -> tuple[Any, Any]: return (data >> 32, data & 0xFFFFFFFF) # Any is sint -def data64_le(data:Any) -> tuple[Any, Any]: return (data & 0xFFFFFFFF, data >> 32) # Any is sint -def getbits(value: int, start: int, end: int): return (value >> start) & ((1 << (end - start + 1)) - 1) -def i2u(bits: int, value: int): return value if value >= 0 else (1< dict[T,U]: - kvs = set([(k,v) for d in ds for k,v in d.items()]) - assert len(kvs) == len(set(kv[0] for kv in kvs)), f"cannot merge, {kvs} contains different values for the same key" - return {k:v for d in ds for k,v in d.items()} -def partition(itr:Iterable[T], fxn:Callable[[T],bool]) -> tuple[list[T], list[T]]: - ret:tuple[list[T], list[T]] = ([], []) - for s in itr: (ret[0] if fxn(s) else ret[1]).append(s) - return ret -def unwrap(x:Optional[T]) -> T: - assert x is not None - return x -def get_single_element(x:list[T]) -> T: - assert len(x) == 1, f"list {x} must only have 1 element" - return x[0] -def get_child(obj, key): - for k in key.split('.'): - if k.isnumeric(): obj = obj[int(k)] - elif isinstance(obj, dict): obj = obj[k] - else: obj = getattr(obj, k) - return obj -def word_wrap(x, wrap=80): return x if len(x) <= wrap or '\n' in x[0:wrap] else (x[0:wrap] + "\n" + word_wrap(x[wrap:], wrap)) -def pluralize(st:str, cnt:int): return f"{cnt} {st}"+('' if cnt == 1 else 's') - -# for length N coefficients `p`, returns p[0] * x**(N-1) + p[1] * x**(N-2) + ... + p[-2] * x + p[-1] -def polyN(x:T, p:list[float]) -> T: return functools.reduce(lambda acc,c: acc*x+c, p, 0.0) # type: ignore - -@functools.cache -def to_function_name(s:str): return ''.join([c if c in (string.ascii_letters+string.digits+'_') else f'{ord(c):02X}' for c in ansistrip(s)]) -@functools.cache -def getenv(key:str, default=0): return type(default)(os.getenv(key, default)) -def temp(x:str, append_user:bool=False) -> str: - return (pathlib.Path(tempfile.gettempdir()) / (f"{x}.{getpass.getuser()}" if append_user else x)).as_posix() - -class Context(contextlib.ContextDecorator): - def __init__(self, **kwargs): self.kwargs = kwargs - def __enter__(self): - self.old_context:dict[str, int] = {k:v.value for k,v in ContextVar._cache.items()} - for k,v in self.kwargs.items(): ContextVar._cache[k].value = v - def __exit__(self, *args): - for k,v in self.old_context.items(): ContextVar._cache[k].value = v - -class ContextVar: - _cache: ClassVar[dict[str, ContextVar]] = {} - value: int - key: str - def __init__(self, key, default_value): - if key in ContextVar._cache: raise RuntimeError(f"attempt to recreate ContextVar {key}") - ContextVar._cache[key] = self - self.value, self.key = getenv(key, default_value), key - def __bool__(self): return bool(self.value) - def __ge__(self, x): return self.value >= x - def __gt__(self, x): return self.value > x - def __lt__(self, x): return self.value < x - -DEBUG, IMAGE, BEAM, NOOPT = ContextVar("DEBUG", 0), ContextVar("IMAGE", 0), ContextVar("BEAM", 0), ContextVar("NOOPT", 0) -JIT = ContextVar("JIT", 2 if platform.system() == 'Darwin' and ('Intel' in platform.processor() or 'i386' in platform.processor()) else 1) -WINO, CAPTURING, TRACEMETA = ContextVar("WINO", 0), ContextVar("CAPTURING", 1), ContextVar("TRACEMETA", 1) -USE_TC, TC_SELECT, TC_OPT, AMX = ContextVar("TC", 1), ContextVar("TC_SELECT", -1), ContextVar("TC_OPT", 0), ContextVar("AMX", 0) -TRANSCENDENTAL, TC_SEARCH_OVER_SHAPE = ContextVar("TRANSCENDENTAL", 1), ContextVar("TC_SEARCH_OVER_SHAPE", 1) -FUSE_ARANGE, FUSE_CONV_BW = ContextVar("FUSE_ARANGE", 0), ContextVar("FUSE_CONV_BW", 0) -SPLIT_REDUCEOP, NO_MEMORY_PLANNER, RING = ContextVar("SPLIT_REDUCEOP", 1), ContextVar("NO_MEMORY_PLANNER", 0), ContextVar("RING", 1) -PICKLE_BUFFERS, PROFILE, LRU = ContextVar("PICKLE_BUFFERS", 1), ContextVar("PROFILE", getenv("VIZ")), ContextVar("LRU", 1) -CACHELEVEL, IGNORE_BEAM_CACHE, DEVECTORIZE = ContextVar("CACHELEVEL", 2), ContextVar("IGNORE_BEAM_CACHE", 0), ContextVar("DEVECTORIZE", 1) -DISABLE_COMPILER_CACHE = ContextVar("DISABLE_COMPILER_CACHE", 0) -DONT_REALIZE_EXPAND, DONT_GROUP_REDUCES = ContextVar("DONT_REALIZE_EXPAND", 0), ContextVar("DONT_GROUP_REDUCES", 0) -QUANTIZE, VALIDATE_WITH_CPU = ContextVar("QUANTIZE", 0), ContextVar("VALIDATE_WITH_CPU", 0) -CORRECT_DIVMOD_FOLDING, FUSE_OPTIM = ContextVar("CORRECT_DIVMOD_FOLDING", 0), ContextVar("FUSE_OPTIM", 0) -ALLOW_DEVICE_USAGE = ContextVar("ALLOW_DEVICE_USAGE", 1) - -@dataclass(frozen=True) -class Metadata: - name: str - caller: str - backward: bool = False - def __hash__(self): return hash(self.name) - def __repr__(self): return str(self) + (f" - {self.caller}" if self.caller else "") - def __str__(self): return self.name + (" bw" if self.backward else "") - -# **************** global state Counters **************** - -class GlobalCounters: - global_ops: ClassVar[int] = 0 - global_mem: ClassVar[int] = 0 - time_sum_s: ClassVar[float] = 0.0 - kernel_count: ClassVar[int] = 0 - mem_used: ClassVar[int] = 0 # NOTE: this is not reset - @staticmethod - def reset(): GlobalCounters.global_ops, GlobalCounters.global_mem, GlobalCounters.time_sum_s, GlobalCounters.kernel_count = 0,0,0.0,0 - -# **************** timer and profiler **************** - -class Timing(contextlib.ContextDecorator): - def __init__(self, prefix="", on_exit=None, enabled=True): self.prefix, self.on_exit, self.enabled = prefix, on_exit, enabled - def __enter__(self): self.st = time.perf_counter_ns() - def __exit__(self, *exc): - self.et = time.perf_counter_ns() - self.st - if self.enabled: print(f"{self.prefix}{self.et*1e-6:6.2f} ms"+(self.on_exit(self.et) if self.on_exit else "")) - -def _format_fcn(fcn): return f"{fcn[0]}:{fcn[1]}:{fcn[2]}" -class Profiling(contextlib.ContextDecorator): - def __init__(self, enabled=True, sort='cumtime', frac=0.2, fn=None, ts=1): - self.enabled, self.sort, self.frac, self.fn, self.time_scale = enabled, sort, frac, fn, 1e3/ts - def __enter__(self): - import cProfile - self.pr = cProfile.Profile() - if self.enabled: self.pr.enable() - def __exit__(self, *exc): - if self.enabled: - self.pr.disable() - if self.fn: self.pr.dump_stats(self.fn) - import pstats - stats = pstats.Stats(self.pr).strip_dirs().sort_stats(self.sort) - for fcn in stats.fcn_list[0:int(len(stats.fcn_list)*self.frac)]: # type: ignore[attr-defined] - (_primitive_calls, num_calls, tottime, cumtime, callers) = stats.stats[fcn] # type: ignore[attr-defined] - scallers = sorted(callers.items(), key=lambda x: -x[1][2]) - print(f"n:{num_calls:8d} tm:{tottime*self.time_scale:7.2f}ms tot:{cumtime*self.time_scale:7.2f}ms", - colored(_format_fcn(fcn).ljust(50), "yellow"), - colored(f"<- {(scallers[0][1][2]/tottime)*100:3.0f}% {_format_fcn(scallers[0][0])}", "BLACK") if scallers else '') - -# *** universal database cache *** - -cache_dir: str = os.path.join(getenv("XDG_CACHE_HOME", os.path.expanduser("~/Library/Caches" if OSX else "~/.cache")), "tinygrad") -CACHEDB: str = getenv("CACHEDB", os.path.abspath(os.path.join(cache_dir, "cache.db"))) - -VERSION = 20 -_db_connection = None -def db_connection(): - global _db_connection - if _db_connection is None: - os.makedirs(CACHEDB.rsplit(os.sep, 1)[0], exist_ok=True) - _db_connection = sqlite3.connect(CACHEDB, timeout=60, isolation_level="IMMEDIATE") - # another connection has set it already or is in the process of setting it - # that connection will lock the database - with contextlib.suppress(sqlite3.OperationalError): _db_connection.execute("PRAGMA journal_mode=WAL").fetchone() - if DEBUG >= 8: _db_connection.set_trace_callback(print) - return _db_connection - -def diskcache_clear(): - cur = db_connection().cursor() - drop_tables = cur.execute("SELECT 'DROP TABLE IF EXISTS ' || quote(name) || ';' FROM sqlite_master WHERE type = 'table';").fetchall() - cur.executescript("\n".join([s[0] for s in drop_tables] + ["VACUUM;"])) - -def diskcache_get(table:str, key:Union[dict, str, int]) -> Any: - if CACHELEVEL < 1: return None - if isinstance(key, (str,int)): key = {"key": key} - cur = db_connection().cursor() - try: - res = cur.execute(f"SELECT val FROM '{table}_{VERSION}' WHERE {' AND '.join([f'{x}=?' for x in key.keys()])}", tuple(key.values())) - except sqlite3.OperationalError: - return None # table doesn't exist - if (val:=res.fetchone()) is not None: return pickle.loads(val[0]) - return None - -_db_tables = set() -def diskcache_put(table:str, key:Union[dict, str, int], val:Any, prepickled=False): - if CACHELEVEL < 1: return val - if isinstance(key, (str,int)): key = {"key": key} - conn = db_connection() - cur = conn.cursor() - if table not in _db_tables: - TYPES = {str: "text", bool: "integer", int: "integer", float: "numeric", bytes: "blob"} - ltypes = ', '.join(f"{k} {TYPES[type(key[k])]}" for k in key.keys()) - cur.execute(f"CREATE TABLE IF NOT EXISTS '{table}_{VERSION}' ({ltypes}, val blob, PRIMARY KEY ({', '.join(key.keys())}))") - _db_tables.add(table) - cur.execute(f"REPLACE INTO '{table}_{VERSION}' ({', '.join(key.keys())}, val) VALUES ({', '.join(['?']*len(key))}, ?)", tuple(key.values()) + (val if prepickled else pickle.dumps(val), )) # noqa: E501 - conn.commit() - cur.close() - return val - -def diskcache(func:Callable[..., T]): - def wrapper(*args, **kwargs) -> T: - table, key = f"cache_{func.__name__}", hashlib.sha256(pickle.dumps((args, kwargs))).hexdigest() - if (ret:=diskcache_get(table, key)) is not None: return ret - return diskcache_put(table, key, func(*args, **kwargs)) - return wrapper - -# *** http support *** - -def _ensure_downloads_dir() -> pathlib.Path: - # if we are on a tinybox, use the raid array - if pathlib.Path("/etc/tinybox-release").is_file(): - # try creating dir with sudo - if not (downloads_dir := pathlib.Path("/raid/downloads")).exists(): - subprocess.run(["sudo", "mkdir", "-p", downloads_dir], check=True) - subprocess.run(["sudo", "chown", "tiny:root", downloads_dir], check=True) - subprocess.run(["sudo", "chmod", "775", downloads_dir], check=True) - return downloads_dir - return pathlib.Path(cache_dir) / "downloads" - -def fetch(url:str, name:Optional[Union[pathlib.Path, str]]=None, subdir:Optional[str]=None, gunzip:bool=False, - allow_caching=not getenv("DISABLE_HTTP_CACHE")) -> pathlib.Path: - if url.startswith(("/", ".")): return pathlib.Path(url) - if name is not None and (isinstance(name, pathlib.Path) or '/' in name): fp = pathlib.Path(name) - else: fp = _ensure_downloads_dir() / (subdir or "") / ((name or hashlib.md5(url.encode('utf-8')).hexdigest()) + (".gunzip" if gunzip else "")) - if not fp.is_file() or not allow_caching: - (_dir := fp.parent).mkdir(parents=True, exist_ok=True) - with urllib.request.urlopen(urllib.request.Request(url, headers={"User-Agent": "tinygrad 0.10.3"}), timeout=10) as r: - assert r.status == 200, r.status - length = int(r.headers.get('content-length', 0)) if not gunzip else None - readfile = gzip.GzipFile(fileobj=r) if gunzip else r - progress_bar:tqdm = tqdm(total=length, unit='B', unit_scale=True, desc=f"{url}", disable=CI) - with tempfile.NamedTemporaryFile(dir=_dir, delete=False) as f: - while chunk := readfile.read(16384): progress_bar.update(f.write(chunk)) - f.close() - pathlib.Path(f.name).rename(fp) - progress_bar.update(close=True) - if length and (file_size:=os.stat(fp).st_size) < length: raise RuntimeError(f"fetch size incomplete, {file_size} < {length}") - return fp - -# *** Exec helpers - -def cpu_time_execution(cb, enable): - if enable: st = time.perf_counter() - cb() - if enable: return time.perf_counter()-st - -def cpu_objdump(lib, objdump_tool='objdump'): - with tempfile.NamedTemporaryFile(delete=True) as f: - pathlib.Path(f.name).write_bytes(lib) - print(subprocess.check_output([objdump_tool, '-d', f.name]).decode('utf-8')) - -def capstone_flatdump(lib: bytes): - import capstone - match platform.machine(): - case 'x86_64' | 'AMD64': cs = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_64) - case 'aarch64' | 'arm64': cs = capstone.Cs(capstone.CS_ARCH_ARM64, capstone.CS_MODE_ARM) - case machine: raise NotImplementedError(f"Capstone disassembly isn't supported for {machine}") - cs.skipdata = True - for instr in cs.disasm(lib, 0): - print(f"{instr.address:#08x}: {instr.mnemonic}\t{instr.op_str}") - sys.stdout.flush() - -# *** ctypes helpers - -# TODO: make this work with read only memoryviews (if possible) -def from_mv(mv:memoryview, to_type=ctypes.c_char): - return ctypes.cast(ctypes.addressof(to_type.from_buffer(mv)), ctypes.POINTER(to_type * len(mv))).contents -def to_mv(ptr:int, sz:int) -> memoryview: return memoryview(ctypes.cast(ptr, ctypes.POINTER(ctypes.c_uint8 * sz)).contents).cast("B") -def mv_address(mv): return ctypes.addressof(ctypes.c_char.from_buffer(mv)) -def to_char_p_p(options: list[bytes], to_type=ctypes.c_char): - return (ctypes.POINTER(to_type) * len(options))(*[ctypes.cast(ctypes.create_string_buffer(o), ctypes.POINTER(to_type)) for o in options]) -@functools.cache -def init_c_struct_t(fields: tuple[tuple[str, ctypes._SimpleCData], ...]): - class CStruct(ctypes.Structure): - _pack_, _fields_ = 1, fields - return CStruct -def init_c_var(ctypes_var, creat_cb): return (creat_cb(ctypes_var), ctypes_var)[1] -def flat_mv(mv:memoryview): return mv if len(mv) == 0 else mv.cast("B", shape=(mv.nbytes,)) - -# *** tqdm - -class tqdm(Generic[T]): - def __init__(self, iterable:Iterable[T]|None=None, desc:str='', disable:bool=False, - unit:str='it', unit_scale=False, total:Optional[int]=None, rate:int=100): - self.iterable, self.disable, self.unit, self.unit_scale, self.rate = iterable, disable, unit, unit_scale, rate - self.st, self.i, self.n, self.skip, self.t = time.perf_counter(), -1, 0, 1, getattr(iterable, "__len__", lambda:0)() if total is None else total - self.set_description(desc) - self.update(0) - def __iter__(self) -> Iterator[T]: - assert self.iterable is not None, "need an iterable to iterate" - for item in self.iterable: - yield item - self.update(1) - self.update(close=True) - def __enter__(self): return self - def __exit__(self, *_): self.update(close=True) - def set_description(self, desc:str): self.desc = f"{desc}: " if desc else "" - def update(self, n:int=0, close:bool=False): - self.n, self.i = self.n+n, self.i+1 - if self.disable or (not close and self.i % self.skip != 0): return - prog, elapsed, ncols = self.n/self.t if self.t else 0, time.perf_counter()-self.st, shutil.get_terminal_size().columns - if elapsed and self.i/elapsed > self.rate and self.i: self.skip = max(int(self.i/elapsed)//self.rate,1) - def HMS(t): return ':'.join(f'{x:02d}' if i else str(x) for i,x in enumerate([int(t)//3600,int(t)%3600//60,int(t)%60]) if i or x) - def SI(x): - return (f"{x/1000**int(g:=round(math.log(x,1000),6)):.{int(3-3*math.fmod(g,1))}f}"[:4].rstrip('.')+' kMGTPEZY'[int(g)].strip()) if x else '0.00' - prog_text = f'{SI(self.n)}{f"/{SI(self.t)}" if self.t else self.unit}' if self.unit_scale else f'{self.n}{f"/{self.t}" if self.t else self.unit}' - est_text = f'<{HMS(elapsed/prog-elapsed) if self.n else "?"}' if self.t else '' - it_text = (SI(self.n/elapsed) if self.unit_scale else f"{self.n/elapsed:5.2f}") if self.n else "?" - suf = f'{prog_text} [{HMS(elapsed)}{est_text}, {it_text}{self.unit}/s]' - sz = max(ncols-len(self.desc)-3-2-2-len(suf), 1) - bar = '\r' + self.desc + (f'{100*prog:3.0f}%|{("█"*int(num:=sz*prog)+" ▏▎▍▌▋▊▉"[int(8*num)%8].strip()).ljust(sz," ")}| ' if self.t else '') + suf - print(bar[:ncols+1], flush=True, end='\n'*close, file=sys.stderr) - @classmethod - def write(cls, s:str): print(f"\r\033[K{s}", flush=True, file=sys.stderr) - -class trange(tqdm): - def __init__(self, n:int, **kwargs): super().__init__(iterable=range(n), total=n, **kwargs) - -# *** universal support for code object pickling - -def _reconstruct_code(*args): return types.CodeType(*args) -def _serialize_code(code:types.CodeType): - args = inspect.signature(types.CodeType).parameters # NOTE: this works in Python 3.10 and up - return _reconstruct_code, tuple(code.__getattribute__('co_'+x.replace('codestring', 'code').replace('constants', 'consts')) for x in args) -copyreg.pickle(types.CodeType, _serialize_code) - -def _serialize_module(module:types.ModuleType): return importlib.import_module, (module.__name__,) -copyreg.pickle(types.ModuleType, _serialize_module) diff --git a/tinygrad/tinygrad/nn/__init__.py b/tinygrad/tinygrad/nn/__init__.py deleted file mode 100644 index b8139950..00000000 --- a/tinygrad/tinygrad/nn/__init__.py +++ /dev/null @@ -1,355 +0,0 @@ -from __future__ import annotations -import math -from tinygrad.tensor import Tensor -from tinygrad.dtype import dtypes -from tinygrad.device import is_dtype_supported -from tinygrad.helpers import prod, make_tuple, flatten -from tinygrad.nn import optim, state, datasets # noqa: F401 - -class BatchNorm: - """ - Applies Batch Normalization over a 2D or 3D input. - - - Described: https://paperswithcode.com/method/batch-normalization - - Paper: https://arxiv.org/abs/1502.03167v3 - - See: `Tensor.batchnorm` - - ```python exec="true" session="tensor" - from tinygrad import Tensor, dtypes, nn - import numpy as np - np.set_printoptions(precision=4) - ``` - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.BatchNorm(3) - t = Tensor.rand(2, 3, 4, 4) - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = norm(t) - print(t.mean().item(), t.std().item()) - ``` - """ - def __init__(self, sz:int, eps=1e-5, affine=True, track_running_stats=True, momentum=0.1): - self.eps, self.track_running_stats, self.momentum = eps, track_running_stats, momentum - - self.weight: Tensor|None = Tensor.ones(sz) if affine else None - self.bias: Tensor|None = Tensor.zeros(sz) if affine else None - - self.num_batches_tracked = Tensor.zeros(1, dtype='long' if is_dtype_supported(dtypes.long) else 'int', requires_grad=False) - if track_running_stats: self.running_mean, self.running_var = Tensor.zeros(sz, requires_grad=False), Tensor.ones(sz, requires_grad=False) - - def calc_stats(self, x:Tensor) -> tuple[Tensor, Tensor]: - shape_mask: list[int] = [1, -1, *([1]*(x.ndim-2))] - if self.track_running_stats and not Tensor.training: return self.running_mean, self.running_var.reshape(shape=shape_mask).expand(x.shape) - # This requires two full memory accesses to x - # https://github.com/pytorch/pytorch/blob/c618dc13d2aa23625cb0d7ada694137532a4fa33/aten/src/ATen/native/cuda/Normalization.cuh - # There's "online" algorithms that fix this, like https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance#Welford's_Online_algorithm - batch_mean = x.mean(axis=(reduce_axes:=tuple(x for x in range(x.ndim) if x != 1))) - y = (x - batch_mean.detach().reshape(shape=shape_mask)) # d(var)/d(mean) = 0 - batch_var = (y*y).mean(axis=reduce_axes) - return batch_mean, batch_var - - def __call__(self, x:Tensor) -> Tensor: - batch_mean, batch_var = self.calc_stats(x) - # NOTE: wow, this is done all throughout training in most PyTorch models - if self.track_running_stats and Tensor.training: - self.running_mean.assign((1-self.momentum) * self.running_mean + self.momentum * batch_mean.detach()) - self.running_var.assign((1-self.momentum) * self.running_var + self.momentum * x.numel()/(x.numel()-x.shape[1]) * batch_var.detach()) - self.num_batches_tracked += 1 - return x.batchnorm(self.weight, self.bias, batch_mean, batch_var.add(self.eps).rsqrt()) -BatchNorm2d = BatchNorm3d = BatchNorm - -def Conv1d(in_channels:int, out_channels:int, kernel_size:int, stride=1, padding:int|str=0, dilation=1, groups=1, bias=True) -> Conv2d: - """ - Applies a 1D convolution over an input signal composed of several input planes. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Conv1d - - ```python exec="true" source="above" session="tensor" result="python" - conv = nn.Conv1d(1, 1, 3) - t = Tensor.rand(1, 1, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = conv(t) - print(t.numpy()) - ``` - """ - return Conv2d(in_channels, out_channels, (kernel_size,), stride, padding, dilation, groups, bias) - -class Conv2d: - """ - Applies a 2D convolution over an input signal composed of several input planes. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Conv2d - - ```python exec="true" source="above" session="tensor" result="python" - conv = nn.Conv2d(1, 1, 3) - t = Tensor.rand(1, 1, 4, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = conv(t) - print(t.numpy()) - ``` - """ - def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...], stride=1, padding:int|tuple[int, ...]|str=0, - dilation=1, groups=1, bias=True): - self.kernel_size = make_tuple(kernel_size, 2) - if isinstance(padding, str): - if padding.lower() != 'same': raise ValueError(f"Invalid padding string {padding!r}, only 'same' is supported") - if stride != 1: raise ValueError("padding='same' is not supported for strided convolutions") - pad = [(d*(k-1)//2, d*(k-1) - d*(k-1)//2) for d,k in zip(make_tuple(dilation, len(self.kernel_size)), self.kernel_size[::-1])] - padding = tuple(flatten(pad)) - self.stride, self.dilation, self.groups, self.padding = stride, dilation, groups, padding - scale = 1 / math.sqrt(in_channels * prod(self.kernel_size)) - self.weight = Tensor.uniform(out_channels, in_channels//groups, *self.kernel_size, low=-scale, high=scale) - self.bias: Tensor|None = Tensor.uniform(out_channels, low=-scale, high=scale) if bias else None - - def __call__(self, x:Tensor) -> Tensor: return x.conv2d(self.weight, self.bias, self.groups, self.stride, self.dilation, self.padding) - -def ConvTranspose1d(in_channels:int, out_channels:int, kernel_size:int, stride=1, padding=0, output_padding=0, dilation=1, - groups=1, bias=True) -> ConvTranspose2d: - """ - Applies a 1D transposed convolution operator over an input signal composed of several input planes. - - See: https://pytorch.org/docs/stable/generated/torch.nn.ConvTranspose1d - - ```python exec="true" source="above" session="tensor" result="python" - conv = nn.ConvTranspose1d(1, 1, 3) - t = Tensor.rand(1, 1, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = conv(t) - print(t.numpy()) - ``` - """ - return ConvTranspose2d(in_channels, out_channels, (kernel_size,), stride, padding, output_padding, dilation, groups, bias) - -class ConvTranspose2d(Conv2d): - """ - Applies a 2D transposed convolution operator over an input image. - - See: https://pytorch.org/docs/stable/generated/torch.nn.ConvTranspose2d - - ```python exec="true" source="above" session="tensor" result="python" - conv = nn.ConvTranspose2d(1, 1, 3) - t = Tensor.rand(1, 1, 4, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = conv(t) - print(t.numpy()) - ``` - """ - def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...], stride=1, padding=0, output_padding=0, - dilation=1, groups=1, bias=True): - super().__init__(in_channels, out_channels, kernel_size, stride, padding, dilation, groups, bias) - scale = 1 / math.sqrt(in_channels * prod(self.kernel_size)) - self.weight = Tensor.uniform(in_channels, out_channels//groups, *self.kernel_size, low=-scale, high=scale) - self.output_padding = output_padding - - def __call__(self, x:Tensor) -> Tensor: - return x.conv_transpose2d(self.weight, self.bias, self.groups, self.stride, self.dilation, self.padding, self.output_padding) - -class Linear: - """ - Applies a linear transformation to the incoming data. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Linear - - ```python exec="true" source="above" session="tensor" result="python" - lin = nn.Linear(3, 4) - t = Tensor.rand(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = lin(t) - print(t.numpy()) - ``` - """ - def __init__(self, in_features:int, out_features:int, bias=True): - bound = 1 / math.sqrt(in_features) - self.weight = Tensor.uniform(out_features, in_features, low=-bound, high=bound) - self.bias = Tensor.uniform(out_features, low=-bound, high=bound) if bias else None - - def __call__(self, x:Tensor) -> Tensor: return x.linear(self.weight.transpose(), self.bias) - -class GroupNorm: - """ - Applies Group Normalization over a mini-batch of inputs. - - - Described: https://paperswithcode.com/method/group-normalization - - Paper: https://arxiv.org/abs/1803.08494v3 - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.GroupNorm(2, 12) - t = Tensor.rand(2, 12, 4, 4) * 2 + 1 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = norm(t) - print(t.mean().item(), t.std().item()) - ``` - """ - def __init__(self, num_groups:int, num_channels:int, eps=1e-5, affine=True): - self.num_groups, self.num_channels, self.eps = num_groups, num_channels, eps - self.weight: Tensor|None = Tensor.ones(num_channels) if affine else None - self.bias: Tensor|None = Tensor.zeros(num_channels) if affine else None - - def __call__(self, x:Tensor) -> Tensor: - # reshape for layernorm to work as group norm - # subtract mean and divide stddev - x = x.reshape(x.shape[0], self.num_groups, -1).layernorm(eps=self.eps).reshape(x.shape) - - if self.weight is None or self.bias is None: return x - # elementwise_affine on channels - return x * self.weight.reshape(1, -1, *[1] * (x.ndim-2)) + self.bias.reshape(1, -1, *[1] * (x.ndim-2)) - -class InstanceNorm: - """ - Applies Instance Normalization over a mini-batch of inputs. - - - Described: https://paperswithcode.com/method/instance-normalization - - Paper: https://arxiv.org/abs/1607.08022v3 - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.InstanceNorm(3) - t = Tensor.rand(2, 3, 4, 4) * 2 + 1 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = norm(t) - print(t.mean().item(), t.std().item()) - ``` - """ - def __init__(self, num_features:int, eps=1e-5, affine=True): - self.num_features, self.eps = num_features, eps - self.weight: Tensor|None = Tensor.ones(num_features) if affine else None - self.bias: Tensor|None = Tensor.zeros(num_features) if affine else None - - def __call__(self, x:Tensor) -> Tensor: - x = x.reshape(x.shape[0], self.num_features, -1).layernorm(eps=self.eps).reshape(x.shape) - if self.weight is None or self.bias is None: return x - return x * self.weight.reshape(1, -1, *[1] * (x.ndim-2)) + self.bias.reshape(1, -1, *[1] * (x.ndim-2)) - -class LayerNorm: - """ - Applies Layer Normalization over a mini-batch of inputs. - - - Described: https://paperswithcode.com/method/layer-normalization - - Paper: https://arxiv.org/abs/1607.06450v1 - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.LayerNorm(3) - t = Tensor.rand(2, 5, 3) * 2 + 1 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = norm(t) - print(t.mean().item(), t.std().item()) - ``` - """ - def __init__(self, normalized_shape:int|tuple[int, ...], eps=1e-5, elementwise_affine=True): - self.normalized_shape: tuple[int, ...] = make_tuple(normalized_shape, 1) - self.axis, self.eps, self.elementwise_affine = tuple(-1-i for i in range(len(self.normalized_shape))), eps, elementwise_affine - self.weight: Tensor|None = Tensor.ones(*self.normalized_shape) if elementwise_affine else None - self.bias: Tensor|None = Tensor.zeros(*self.normalized_shape) if elementwise_affine else None - - def __call__(self, x:Tensor) -> Tensor: - assert self.normalized_shape == x.shape[-len(self.normalized_shape):], f"last dimensions of {x.shape} must match {self.normalized_shape}" - x = x.layernorm(eps=self.eps, axis=self.axis) - if not self.elementwise_affine: return x - return x * self.weight + self.bias - -class LayerNorm2d(LayerNorm): - """ - Applies Layer Normalization over a mini-batch of 2D inputs. - - See: `LayerNorm` - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.LayerNorm2d(3) - t = Tensor.rand(2, 3, 4, 4) * 2 + 1 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = norm(t) - print(t.mean().item(), t.std().item()) - ``` - """ - def __call__(self, x: Tensor) -> Tensor: return super().__call__(x.permute(0, 2, 3, 1)).permute(0, 3, 1, 2) - -class RMSNorm: - """ - Applies Root Mean Square Normalization to input. - - - Described: https://paperswithcode.com/method/rmsnorm - - Paper: https://arxiv.org/abs/1910.07467 - - ```python exec="true" source="above" session="tensor" result="python" - norm = nn.RMSNorm(4) - t = Tensor.arange(12, dtype=dtypes.float).reshape(3, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(norm(t).numpy()) - ``` - """ - def __init__(self, dim:int, eps=1e-6, elementwise_affine=True): - self.eps = eps - self.weight = Tensor.ones(dim) if elementwise_affine else None - - def _norm(self, x:Tensor) -> Tensor: return x * (x.square().mean(-1, keepdim=True) + self.eps).rsqrt() - - def __call__(self, x:Tensor) -> Tensor: - x = self._norm(x.float()).cast(x.dtype) - return x if self.weight is None else x * self.weight - -class Embedding: - """ - A simple lookup table that stores embeddings of a fixed dictionary and size. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Embedding - - ```python exec="true" source="above" session="tensor" result="python" - emb = nn.Embedding(10, 3) - print(emb(Tensor([1, 2, 3, 1])).numpy()) - ``` - """ - def __init__(self, vocab_size:int, embed_size:int): - self.vocab_sz, self.embed_sz, self.weight = vocab_size, embed_size, Tensor.glorot_uniform(vocab_size, embed_size) - - def __call__(self, idx:Tensor) -> Tensor: - if not hasattr(self, 'arange'): self.arange = Tensor.arange(self.vocab_sz, requires_grad=False, device=self.weight.device).unsqueeze(-1) - big_shp = idx.shape+(self.vocab_sz, self.embed_sz) - arange, idx, vals = self.arange.expand(big_shp), idx.reshape(idx.shape+(1, 1)).expand(big_shp), self.weight.expand(big_shp) - return (arange == idx).mul(vals).sum(-2, dtype=vals.dtype) - -class LSTMCell: - """ - A long short-term memory (LSTM) cell. - - Args: - input_size: The number of expected features in the input `x` - hidden_size: The number of features in the hidden state `h` - bias: If ``False``, then the layer does not use bias weights `b_ih` and `b_hh` - """ - def __init__(self, input_size:int, hidden_size:int, bias:bool=True): - stdv = 1.0 / math.sqrt(hidden_size) - self.weight_ih = Tensor.uniform(hidden_size*4, input_size, low=-stdv, high=stdv) - self.weight_hh = Tensor.uniform(hidden_size*4, hidden_size, low=-stdv, high=stdv) - self.bias_ih: Tensor|None = Tensor.zeros(hidden_size*4) if bias else None - self.bias_hh: Tensor|None = Tensor.zeros(hidden_size*4) if bias else None - - def __call__(self, x:Tensor, hc:tuple[Tensor, Tensor]|None=None) -> tuple[Tensor, Tensor]: - if hc is None: hc = (Tensor.zeros(x.size(0), self.weight_hh.size(1), dtype=x.dtype, device=x.device),)*2 - gates = x.linear(self.weight_ih.T, self.bias_ih) + hc[0].linear(self.weight_hh.T, self.bias_hh) - i, f, g, o = gates.chunk(4, dim=1) - i, f, g, o = i.sigmoid(), f.sigmoid(), g.tanh(), o.sigmoid() - new_c = f * hc[1] + i * g - new_h = o * new_c.tanh() - return (new_h.contiguous(), new_c.contiguous()) diff --git a/tinygrad/tinygrad/nn/datasets.py b/tinygrad/tinygrad/nn/datasets.py deleted file mode 100644 index 30439fb4..00000000 --- a/tinygrad/tinygrad/nn/datasets.py +++ /dev/null @@ -1,14 +0,0 @@ -from tinygrad.tensor import Tensor -from tinygrad.nn.state import tar_extract - -def mnist(device=None, fashion=False): - base_url = "http://fashion-mnist.s3-website.eu-central-1.amazonaws.com/" if fashion else "https://storage.googleapis.com/cvdf-datasets/mnist/" - def _mnist(file): return Tensor.from_url(base_url+file, gunzip=True) - return _mnist("train-images-idx3-ubyte.gz")[0x10:].reshape(-1,1,28,28).to(device), _mnist("train-labels-idx1-ubyte.gz")[8:].to(device), \ - _mnist("t10k-images-idx3-ubyte.gz")[0x10:].reshape(-1,1,28,28).to(device), _mnist("t10k-labels-idx1-ubyte.gz")[8:].to(device) - -def cifar(device=None): - tt = tar_extract(Tensor.from_url('https://www.cs.toronto.edu/~kriz/cifar-10-binary.tar.gz', gunzip=True)) - train = Tensor.cat(*[tt[f"cifar-10-batches-bin/data_batch_{i}.bin"].reshape(-1, 3073).to(device) for i in range(1,6)]) - test = tt["cifar-10-batches-bin/test_batch.bin"].reshape(-1, 3073).to(device) - return train[:, 1:].reshape(-1,3,32,32), train[:, 0], test[:, 1:].reshape(-1,3,32,32), test[:, 0] diff --git a/tinygrad/tinygrad/nn/optim.py b/tinygrad/tinygrad/nn/optim.py deleted file mode 100644 index 9b469feb..00000000 --- a/tinygrad/tinygrad/nn/optim.py +++ /dev/null @@ -1,165 +0,0 @@ -# sorted in order of increasing complexity -import itertools -from tinygrad.helpers import dedup, flatten, getenv, unwrap, FUSE_OPTIM -from tinygrad.tensor import Tensor -from tinygrad.dtype import dtypes, least_upper_dtype - -class Optimizer: - """ - Base class for all optimizers. - """ - def __init__(self, params: list[Tensor], lr: float, fused=FUSE_OPTIM): - # if it's None, but being put into an optimizer, set it to True - for x in params: - if x.requires_grad is None: x.requires_grad = True - - self.params: list[Tensor] = dedup([x for x in params if x.requires_grad]) - assert len(self.params) != 0, "optimizer must have at least one param" - self.device = self.params[0].device - self.buffers: list[Tensor] = dedup([x for x in params if not x.requires_grad]) # buffers are still realized - self.fused = fused - # store lr in at least float32 precision - self.lr = Tensor(lr if getenv("CONST_LR") else [lr], requires_grad=False, device=self.device, - dtype=least_upper_dtype(dtypes.default_float, dtypes.float32)) - if self.fused: self.pos_params = list(itertools.accumulate(self.params, lambda x,y: x+y.flatten().shape[0], initial=0)) - - def _new_optim_param(self) -> list[Tensor]: - if self.fused: return [Tensor.zeros(self.pos_params[-1], dtype=dtypes.float32, device=self.device, requires_grad=False).contiguous()] - return [Tensor.zeros(*t.shape, dtype=dtypes.float32, device=t.device, requires_grad=False).contiguous() for t in self.params] - - def zero_grad(self): - """ - Zeroes the gradients of all the parameters. - """ - for param in self.params: param.grad = None - - def step(self): - """ - Performs a single optimization step. - """ - Tensor.realize(*self.schedule_step()) - - def schedule_step(self) -> list[Tensor]: - """ - Returns the tensors that need to be realized to perform a single optimization step. - """ - if not Tensor.training: raise RuntimeError( - f"""Tensor.training={Tensor.training}, Tensor.training must be enabled to use the optimizer. - - help: Consider setting Tensor.training=True before calling Optimizer.step().""") - if self.fused: - # optimizer fusion just concatentates all the buffers, runs the _step, then splits them back up - out, extra = self._step([Tensor.cat(*[t.flatten() for t in self.params], dim=0)], - [Tensor.cat(*[unwrap(t.grad).flatten() for t in self.params], dim=0)]) - updated_params = [out[0][self.pos_params[i]:self.pos_params[i+1]].reshape(tt.shape) for i, tt in enumerate(self.params)] - else: - updated_params, extra = self._step(self.params, [unwrap(t.grad) for t in self.params]) - for i, tt in enumerate(self.params): tt.assign(updated_params[i]) - return extra+self.params+self.buffers - - def _step(self, params:list[Tensor], grads:list[Tensor]) -> tuple[list[Tensor], list[Tensor]]: raise NotImplementedError - -class OptimizerGroup(Optimizer): - """ - Combines multiple optimizers into one. - """ - def __init__(self, *optimizers: Optimizer): # pylint: disable=super-init-not-called - self.optimizers = optimizers - self.params, self.buffers = flatten([o.params for o in self.optimizers]), flatten([o.buffers for o in self.optimizers]) - def __getitem__(self, i): return self.optimizers[i] - def zero_grad(self): [o.zero_grad() for o in self.optimizers] - def schedule_step(self) -> list[Tensor]: return [x for o in self.optimizers for x in o.schedule_step()] - -# LARS is essentially just trust ratio to SGD so if we just set the trust coeff 0.0 it's just standard SGD. -def SGD(params: list[Tensor], lr=0.001, momentum=0.0, weight_decay=0.0, nesterov=False, classic=False, fused=FUSE_OPTIM): - """ - Stochastic Gradient Descent (SGD) optimizer with optional momentum and weight decay. - - `classic` is a boolean flag that determines whether to use the popular momentum update rule or the classic momentum update rule. - - - Described: https://paperswithcode.com/method/sgd - """ - return LARS(params, lr, momentum, weight_decay, nesterov, classic, tcoef=0.0, fused=fused) - -class LARS(Optimizer): - """ - Layer-wise Adaptive Rate Scaling (LARS) optimizer with optional momentum and weight decay. - - - Described: https://paperswithcode.com/method/lars - - Paper: https://arxiv.org/abs/1708.03888v3 - """ - def __init__(self, params:list[Tensor], lr=0.001, momentum=0.9, weight_decay=1e-4, nesterov=False, classic=True, tcoef=0.001, fused=FUSE_OPTIM): - super().__init__(params, lr, fused) - self.momentum, self.wd, self.nesterov, self.classic, self.tcoef = momentum, weight_decay, nesterov, classic, tcoef - self.b = self._new_optim_param() if self.momentum else [] - - def _step(self, params:list[Tensor], grads:list[Tensor]) -> tuple[list[Tensor], list[Tensor]]: - ret = [] - for i, (t, g) in enumerate(zip(params, grads)): - if self.tcoef != 0: - r1 = t.detach().square().sum().sqrt() - r2 = g.square().sum().sqrt() - r:Tensor|float = (r1 > 0).where((r2 > 0).where(self.tcoef * r1 / (r2 + self.wd * r1), 1.0), 1.0) - else: r = 1.0 - g = g + self.wd * t.detach() - # classic momentum does post learning rate update - if self.classic: g = g * r * self.lr - if self.momentum: - # TODO: this contiguous is required for correctness because self.b[i] becomes a non contiguous view - # the scheduler should detect this and just insert contiguous - self.b[i].assign(self.momentum * self.b[i].contiguous() + g) # NOTE: self.b[i] is zero on the first run, no if required - g = (g + self.momentum * self.b[i]) if self.nesterov else self.b[i] - # popular momentum does pre learning rate update - if not self.classic: g = g * r * self.lr - ret.append((t.detach() - g).cast(t.dtype)) - return ret, self.b - -# LAMB is essentially just the trust ratio part of LARS applied to Adam/W so if we just set the trust ratio to 1.0 it's just Adam/W. -def AdamW(params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-8, weight_decay=0.01, fused=FUSE_OPTIM): - """ - AdamW optimizer with optional weight decay. - - - Described: https://paperswithcode.com/method/adamw - - Paper: https://arxiv.org/abs/1711.05101v3 - """ - return LAMB(params, lr, b1, b2, eps, weight_decay, adam=True, fused=fused) -def Adam(params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-8, fused=FUSE_OPTIM): - """ - Adam optimizer. - - - Described: https://paperswithcode.com/method/adam - - Paper: https://arxiv.org/abs/1412.6980 - """ - return LAMB(params, lr, b1, b2, eps, 0.0, adam=True, fused=fused) - -class LAMB(Optimizer): - """ - LAMB optimizer with optional weight decay. - - - Described: https://paperswithcode.com/method/lamb - - Paper: https://arxiv.org/abs/1904.00962 - """ - def __init__(self, params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-6, weight_decay=0.0, adam=False, fused=FUSE_OPTIM): - super().__init__(params, lr, fused) - self.b1, self.b2, self.eps, self.wd, self.adam = b1, b2, eps, weight_decay, adam - self.b1_t, self.b2_t = (Tensor.ones((1,), dtype=dtypes.float32, device=self.device, requires_grad=False).contiguous() for _ in [b1, b2]) - self.m = self._new_optim_param() - self.v = self._new_optim_param() - - def _step(self, params:list[Tensor], grads:list[Tensor]) -> tuple[list[Tensor], list[Tensor]]: - ret = [] - self.b1_t *= self.b1 - self.b2_t *= self.b2 - for i, (t, g) in enumerate(zip(params, grads)): - self.m[i].assign(self.b1 * self.m[i] + (1.0 - self.b1) * g) - self.v[i].assign(self.b2 * self.v[i] + (1.0 - self.b2) * (g * g)) - m_hat = self.m[i] / (1.0 - self.b1_t) - v_hat = self.v[i] / (1.0 - self.b2_t) - up = (m_hat / (v_hat.sqrt() + self.eps)) + self.wd * t.detach() - if not self.adam: - r1 = t.detach().square().sum().sqrt() - r2 = up.square().sum().sqrt() - r: Tensor|float = Tensor.where(r1 > 0, Tensor.where(r2 > 0, r1 / r2, 1.0), 1.0) - else: - r = 1.0 - ret.append((t.detach() - self.lr * r * up).cast(t.dtype)) - return ret, [self.b1_t, self.b2_t] + self.m + self.v diff --git a/tinygrad/tinygrad/nn/state.py b/tinygrad/tinygrad/nn/state.py deleted file mode 100644 index 6b56a45b..00000000 --- a/tinygrad/tinygrad/nn/state.py +++ /dev/null @@ -1,340 +0,0 @@ -import json, pathlib, zipfile, pickle, tarfile, struct, functools, io -from collections import OrderedDict -from typing import Union, Optional, Any, Callable, BinaryIO, Iterable -from tinygrad.tensor import Tensor -from tinygrad.dtype import dtypes -from tinygrad.helpers import prod, argsort, DEBUG, Timing, CI, unwrap, GlobalCounters, tqdm, round_up, T -from tinygrad.shape.view import strides_for_shape - -class TensorIO(io.RawIOBase, BinaryIO): - def __init__(self, t: Tensor): - if t.ndim != 1 or t.dtype != dtypes.uint8: raise ValueError("Tensor must be 1d and of dtype uint8!") - self._position, self._tensor = 0, t - - def readable(self) -> bool: return True - def read(self, size: int = -1) -> bytes: - if (buf:=super().read(size)) is None: raise ValueError("io.RawIOBase.read returned None") # only happens if readinto returns None (never) - return buf - def readinto(self, buffer: Any) -> int: - data = self._tensor[self._position:self._position+len(buffer)].data() - buffer[:len(data)] = data - self._position += len(data) - return len(data) - - def seekable(self) -> bool: return True - def seek(self, offset: int, whence: int = 0) -> int: - self._position = min(len(self._tensor), max(0, [offset, self._position+offset, len(self._tensor)+offset][whence])) - return self._position - - # required to correctly implement BinaryIO - def __enter__(self): return self - def write(self, s: Any): raise io.UnsupportedOperation("TensorIO.write not supported") - def writelines(self, lines: Iterable[Any]): raise io.UnsupportedOperation("TensorIO.writelines not supported") - -safe_dtypes = {"BOOL":dtypes.bool, "I8":dtypes.int8, "U8":dtypes.uint8, "I16":dtypes.int16, "U16":dtypes.uint16, "I32":dtypes.int, "U32":dtypes.uint, - "I64":dtypes.int64, "U64":dtypes.uint64, "F16":dtypes.float16, "BF16":dtypes.bfloat16, "F32":dtypes.float32, "F64":dtypes.float64} -inverse_safe_dtypes = {v:k for k,v in safe_dtypes.items()} - -def accept_filename(func: Callable[[Tensor], T]) -> Callable[[Union[Tensor, str, pathlib.Path]], T]: - @functools.wraps(func) - def wrapper(fn: Union[Tensor, str, pathlib.Path]) -> T: return func(Tensor(pathlib.Path(fn)) if not isinstance(fn, Tensor) else fn) - return wrapper - -@accept_filename -def safe_load_metadata(t:Tensor) -> tuple[Tensor, int, dict[str, Any]]: - """ - Loads a .safetensor file, returning the source tensor, data start position, and metadata. - """ - data_start = int.from_bytes(t[0:8].data(), "little") + 8 - return t, data_start, json.loads(t[8:data_start].data().tobytes()) - -def safe_load(fn:Union[Tensor, str, pathlib.Path]) -> dict[str, Tensor]: - """ - Loads a .safetensor file, returning the `state_dict`. - - ```python - state_dict = nn.state.safe_load("test.safetensor") - ``` - """ - t, data_start, metadata = safe_load_metadata(fn) - data = t[data_start:] - return { k: data[v['data_offsets'][0]:v['data_offsets'][1]].bitcast(safe_dtypes[v['dtype']]).reshape(v['shape']) - for k, v in metadata.items() if k != "__metadata__" } - -def safe_save(tensors:dict[str, Tensor], fn:str, metadata:Optional[dict[str, Any]]=None): - """ - Saves a `state_dict` to disk in a .safetensor file with optional metadata. - - ```python - t = Tensor([1, 2, 3]) - nn.state.safe_save({'t':t}, "test.safetensor") - ``` - """ - headers, offset = {}, 0 - if metadata: headers['__metadata__'] = metadata - for k,v in tensors.items(): - headers[k] = {'dtype': inverse_safe_dtypes[v.dtype], 'shape': list(v.shape), 'data_offsets':[offset, offset+v.nbytes()]} - offset += v.nbytes() - j = json.dumps(headers, separators=(',', ':')) - j += "\x20"*(round_up(len(j),8)-len(j)) - pathlib.Path(fn).unlink(missing_ok=True) - t = Tensor.empty(8+len(j)+offset, dtype=dtypes.uint8, device=f"disk:{fn}") - t[0:8].bitcast(dtypes.int64).assign([len(j)]) - t[8:8+len(j)].assign(list(j.encode('utf-8'))) - for k,v in safe_load(t).items(): v.assign(tensors[k]) - -# state dict - -def get_state_dict(obj, prefix:str='', tensor_type=Tensor) -> dict[str, Tensor]: - """ - Returns a `state_dict` of the object, with optional prefix. - - ```python exec="true" source="above" session="tensor" result="python" - class Net: - def __init__(self): - self.l1 = nn.Linear(4, 5) - self.l2 = nn.Linear(5, 6) - - net = Net() - print(nn.state.get_state_dict(net).keys()) - ``` - """ - if isinstance(obj, tensor_type): return {prefix.strip('.'):obj} - if hasattr(obj, '_asdict'): return get_state_dict(obj._asdict(), prefix, tensor_type) # namedtuple - if isinstance(obj, OrderedDict): return get_state_dict(dict(obj), prefix, tensor_type) - if hasattr(obj, '__dict__'): return get_state_dict(obj.__dict__, prefix, tensor_type) - state_dict = {} - if isinstance(obj, (list, tuple)): - for i,x in enumerate(obj): state_dict.update(get_state_dict(x, f"{prefix}{str(i)}.", tensor_type)) - elif isinstance(obj, dict): - for k,v in obj.items(): state_dict.update(get_state_dict(v, f"{prefix}{str(k)}.", tensor_type)) - return state_dict - -def get_parameters(obj) -> list[Tensor]: - """ - ```python exec="true" source="above" session="tensor" result="python" - class Net: - def __init__(self): - self.l1 = nn.Linear(4, 5) - self.l2 = nn.Linear(5, 6) - - net = Net() - print(len(nn.state.get_parameters(net))) - ``` - """ - return list(get_state_dict(obj).values()) - -def load_state_dict(model, state_dict:dict[str, Tensor], strict=True, verbose=True, consume=False, realize=True) -> list[Tensor]: - """ - Loads a `state_dict` into a model. Return the loaded Tensors. - - ```python - class Net: - def __init__(self): - self.l1 = nn.Linear(4, 5) - self.l2 = nn.Linear(5, 6) - - net = Net() - state_dict = nn.state.get_state_dict(net) - nn.state.load_state_dict(net, state_dict) - ``` - """ - start_mem_used = GlobalCounters.mem_used - ret = [] - with Timing("loaded weights in ", - lambda et_ns: f", {(B:=(GlobalCounters.mem_used-start_mem_used))/1e9:.2f} GB loaded at {B/et_ns:.2f} GB/s", enabled=verbose): - model_state_dict = get_state_dict(model) - if DEBUG >= 1 and len(state_dict) > len(model_state_dict): - print("WARNING: unused weights in state_dict", sorted(list(state_dict.keys() - model_state_dict.keys()))) - for k,v in (t := tqdm(model_state_dict.items(), disable=CI or not verbose)): - t.desc = f"ram used: {GlobalCounters.mem_used/1e9:5.2f} GB, {k:50s}: " - if k not in state_dict and not strict: - if DEBUG >= 1: print(f"WARNING: not loading {k}") - continue - if v.shape != state_dict[k].shape: - raise ValueError(f'Shape mismatch in layer `{k}`: Expected shape {v.shape}, but found {state_dict[k].shape} in state dict.') - if isinstance(v.device, tuple): - if isinstance(state_dict[k].device, tuple): v.replace(state_dict[k]) - else: v.replace(state_dict[k].shard(v.device, v.uop.axis)) - else: v.replace(state_dict[k].to(v.device)) - if realize: v.realize() - if consume: del state_dict[k] - ret.append(v) - return ret - -@accept_filename -def tar_extract(t: Tensor) -> dict[str, Tensor]: - """ - ```python - tar_extract(fn: Tensor | str | Path) -> dict[str, Tensor] - ``` - - Extracts files from a tar archive and returns them as a dictionary of names (keys) and tensors (values). - - ```python - tensors = nn.state.tar_extract(Tensor(pathlib.Path("archive.tar"))) - ``` - """ - with tarfile.open(fileobj=TensorIO(t), mode="r") as tar: - return {member.name:t[member.offset_data:member.offset_data+member.size] for member in tar if member.type == tarfile.REGTYPE} - -# torch support! - -@accept_filename -def torch_load(t:Tensor) -> dict[str, Tensor]: - """ - ```python - torch_load(fn: Tensor | str | Path) -> dict[str, Tensor] - ``` - - Loads a torch .pth file, returning the `state_dict`. - - ```python - state_dict = nn.state.torch_load("test.pth") - ``` - """ - offsets: dict[Union[str, int], int] = {} - lens: dict[Union[str, int], int] = {} - def _rebuild_tensor_v2(storage, storage_offset, size, stride, requires_grad=None, backward_hooks=None, metadata=None): - #print(storage, storage_offset, size, stride, requires_grad, backward_hooks, metadata) - lens[storage[2]] = storage[4] * storage[1].itemsize - if storage[2] not in offsets: return None - byte_offset = offsets[storage[2]]+storage_offset*storage[1].itemsize - ret = t[byte_offset:byte_offset+prod(size)*storage[1].itemsize].bitcast(storage[1]) - - # 7 lines to deal with permuted tensors. NOTE: this currently requires reading off the disk - shape_strides = [(s, st) for s,st in zip(size, stride) if s != 1] - permute_indexes = [len(shape_strides)-1-y for y in argsort([x[1] for x in shape_strides])] - if tuple(permute_indexes) != tuple(range(len(permute_indexes))): - intermediate_shape = tuple([shape_strides[x][0] for x in argsort(permute_indexes)]) - assert tuple([shape_strides[i][1] for i in argsort(permute_indexes)]) == strides_for_shape(intermediate_shape), "nonpermutable strides" - if DEBUG >= 3: print(f"WARNING: this torch load is slow. to permute {intermediate_shape} with {permute_indexes}") - assert storage[1] != dtypes.bfloat16, "can't permute BF16" - # TODO: find a nice way to support all shapetracker on disktensors - ret = ret.to(None).reshape(intermediate_shape).permute(permute_indexes) - - return ret.reshape(size) - - class Parameter: - def __setstate__(self, state): self.tensor = state[0] - - deserialized_objects: dict[str, Any] = {} - intercept = {"HalfStorage": dtypes.float16, "FloatStorage": dtypes.float32, "BFloat16Storage": dtypes.bfloat16, - "IntStorage": dtypes.int32, "BoolStorage": dtypes.bool, - "LongStorage": dtypes.int64, "_rebuild_tensor_v2": _rebuild_tensor_v2, "FloatTensor": None, "Parameter": Parameter} - whitelist = {"torch", "collections", "numpy", "_codecs"} # NOTE: this is not for security, only speed - class Dummy: pass - class TorchPickle(pickle.Unpickler): - def find_class(self, module, name): - module_root = module.split(".")[0] - if module_root not in whitelist: - if DEBUG >= 2: print(f"WARNING: returning Dummy for {module} {name}") - return Dummy - return intercept[name] if module_root == "torch" else super().find_class(module, name) - def persistent_load(self, pid): return deserialized_objects.get(pid, pid) - - fobj = io.BufferedReader(TensorIO(t)) - def passthrough_reset(v: bool): return fobj.seek(0, 0) or v - - if passthrough_reset(zipfile.is_zipfile(fobj)): # NOTE: passthrough_reset required to support python < 3.14 - myzip = zipfile.ZipFile(fobj, 'r') - base_name = myzip.namelist()[0].split('/', 1)[0] - for n in myzip.namelist(): - if n.startswith(f'{base_name}/data/'): - with myzip.open(n) as myfile: - offsets[n.split("/")[-1]] = myfile._orig_compress_start # type: ignore - with myzip.open(f'{base_name}/data.pkl') as myfile: - return TorchPickle(myfile).load() - elif passthrough_reset(tarfile.is_tarfile(fobj)): # NOTE: passthrough_reset required to support python < 3.11 - with tarfile.open(fileobj=fobj, mode="r") as tar: - storages_offset = tar.getmember('storages').offset_data - f = unwrap(tar.extractfile('storages')) - for i in range(TorchPickle(f).load()): # num_storages - (key, _, storage_type), sz = TorchPickle(f).load(), struct.unpack(' Tensor: - """ - Converts ggml tensor data to a tinygrad tensor. - - Supported native types: float32 (id: 0), float16 (id: 1), int8 (id: 16), int16 (id: 17), int32 (id: 18) - Supported quantized types: Q4_0 (id: 2), Q4_1 (id: 3), Q8_0 (id: 8), Q6_K (id: 14) - """ - # https://github.com/ggerganov/ggml/blob/6dccc647264f5429df2624f36138f601e7ce23e5/include/ggml.h#L356 - - # native types - if (dtype := { 0: dtypes.float32, 1: dtypes.float16, 16: dtypes.int8, 17: dtypes.int16, 18: dtypes.int32 }.get(ggml_type)) is not None: - return t[:dtype.itemsize * n].bitcast(dtype) - - def q_to_uint8(t: Tensor, b: int) -> Tensor: - # TODO: rewrite with arange? - shift_tensor, bitmask = Tensor.stack(*[ Tensor(2**(i*b), device=t.device, dtype=t.dtype) for i in range(8//b) ]), 0xff >> (8 - b) - return t.unsqueeze(-1).expand((*t.shape,8//b)).idiv(shift_tensor).bitwise_and(bitmask).transpose(-1, -2).flatten(-2) - - # map to (number of elements, number of bytes) - if (nelements_nbytes := { 2: (32, 18), 3: (32, 20), 14: (256, 210), 8: (32, 34) }.get(ggml_type)) is not None: - blocks = t[:(n//nelements_nbytes[0])*nelements_nbytes[1]].reshape((-1, nelements_nbytes[1])) - if ggml_type == 2: return (q_to_uint8(blocks[:,2:], 4).bitcast(dtypes.int8) - 8) * blocks[:,:2].bitcast(dtypes.float16).cast(dtypes.float32) - if ggml_type == 3: - d, m = (blocks[:,s:s+2].bitcast(dtypes.float16).cast(dtypes.float32) for s in [ 0, 2 ]) - return q_to_uint8(blocks[:,4:], 4).bitcast(dtypes.int8) * d + m - if ggml_type == 8: return blocks[:,:2].bitcast(dtypes.float16).cast(dtypes.float32) * blocks[:,2:].bitcast(dtypes.int8) - if ggml_type == 14: - xl, xh = q_to_uint8(blocks[:,:128].reshape((-1, 2, 64)), 4), q_to_uint8(blocks[:,128:192].reshape((-1, 2, 32)), 2).lshift(4) - scales = blocks[:,192:208].bitcast(dtypes.int8).unsqueeze(-1).expand((-1, 16, 16)).reshape((-1, 256)) - d = blocks[:,-2:].bitcast(dtypes.float16).cast(dtypes.float32).expand((-1, 256)) - return d * (xl.bitwise_or(xh).bitcast(dtypes.int8) - 32).flatten(-2) * scales - raise ValueError(f"GGML type '{ggml_type}' is not supported!") - -@accept_filename -def gguf_load(tensor: Tensor) -> tuple[dict, dict[str, Tensor]]: - """ - Loads a .gguf file, returning the `kv_data` and `state_dict`. - - ```python - gguf_tensor = Tensor(pathlib.Path("Meta-Llama-3-8B-Instruct.Q4_0.gguf")).to(Device.DEFAULT) - kv_data, state_dict = nn.state.gguf_load(gguf_tensor) - ``` - - NOTE: The provided tensor must be on a device that supports execution. - """ - reader, kv_data, state_dict = io.BufferedReader(TensorIO(tensor), 1_000_000), {}, {} - def read_unpack(fmt: str, n: int): return struct.unpack(fmt, reader.read(n))[0] - def read_str(): return str(reader.read(read_uint64()), "utf-8") - def read_arr(): - reader, n = readers[read_int32()], read_uint64() - return [ reader() for _ in range(n) ] - - readers: dict[int, Callable[[], Any]] = { 8: read_str, 9: read_arr, **{ t: functools.partial(read_unpack, "<"+f, nb) for t,f,nb in \ - [ (0,"c",1), (1,"b",1), (2,"H",2), (3,"h",2), (4,"I",4), (5,"i",4), (6,"f",4), (7,"?",1), (10,"Q",8), (11,"q",8), (12,"d",8) ] } } - read_uint32, read_int32, read_uint64, read_int64 = readers[4], readers[5], readers[10], readers[11] - - magic, version, n_tensors, n_kv = reader.read(4), read_int32(), read_int64(), read_int64() - if magic != b"GGUF" or version not in [2, 3]: raise ValueError("Invalid GGUF format!") - for _ in range(n_kv): - k, typ = read_str(), read_int32() - kv_data[k] = readers[typ]() - - t_infos = [ (read_str(), tuple(read_uint64() for _ in range(read_uint32())), read_int32(), read_uint64()) for _ in range(n_tensors) ] - alignment, pos = kv_data.get("general.alignment", 32), reader.tell() - data_start = round_up(pos, alignment) - - for name, dims, typ, off in t_infos: state_dict[name] = ggml_data_to_tensor(tensor[data_start + off:], prod(dims), typ).reshape(*reversed(dims)) - - return kv_data, state_dict diff --git a/tinygrad/tinygrad/py.typed b/tinygrad/tinygrad/py.typed deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/renderer/__init__.py b/tinygrad/tinygrad/renderer/__init__.py deleted file mode 100644 index 24b536ff..00000000 --- a/tinygrad/tinygrad/renderer/__init__.py +++ /dev/null @@ -1,149 +0,0 @@ -from __future__ import annotations -from typing import Optional, Callable, cast -import functools, math -from enum import Enum, auto -from dataclasses import dataclass, field, replace -from tinygrad.helpers import to_function_name, dedup, prod -from tinygrad.uop.ops import Ops, UOp, sym_infer, sint, Variable, ssimplify, GroupOp, PatternMatcher -from tinygrad.dtype import DType - -class OptOps(Enum): - TC = auto(); UPCAST = auto(); UNROLL = auto(); LOCAL = auto() # noqa: E702 - GROUP = auto(); GROUPTOP = auto(); NOLOCALS = auto(); PADTO = auto(); SWAP = auto() # noqa: E702 - def __lt__(self, x:OptOps): return self.value < x.value - -@dataclass(frozen=True, order=True) -class Opt: - op: OptOps - axis: Optional[int] = None - arg: Optional[int | tuple] = None - def __repr__(self): return f"Opt(op={self.op}, axis={self.axis}, arg={self.arg})" - -@dataclass(frozen=True) -class TensorCore: # D = A * B + C, A is (M x K), B is (K x N), C and D are (M x N) - dims: tuple[int,int,int] # N, M, K - threads: int # number of threads that construct the warp - elements_per_thread: tuple[int, int, int] # elements per-thread to load/store from A/B/C - dtype_in: DType # dtype for A and B - dtype_out: DType # dtype for C and D - opts: tuple[str, ...] # ordered tuple of "ux" or "lx" specifing kernel opts to perform. "ux" upcasts dim x and "lx" localizes dim x - swizzle: tuple[Optional[tuple[tuple[int, ...], tuple[int, ...]]], Optional[tuple[tuple[int, ...], tuple[int, ...]]]] = (None, None) - def get_reduce_axes(self): return [(i, 2) for i in range(int(math.log2(self.dims[2])))] - def get_upcast_axes(self): return [opt for opt in self.opts if opt[0] == "u"] - def get_local_axes(self): return [opt for opt in self.opts if opt[0] == "l"] - def __str__(self): return "_".join(["WMMA"] + list(map(str, self.dims)) + [self.dtype_in.name, self.dtype_out.name]) - def __post_init__(self): - local_axes, upcast_axes, reduce_axes = len(self.get_local_axes()), len(self.get_upcast_axes()), len(self.get_reduce_axes()) - assert self.dims[0] * self.dims[1] == 2**(local_axes + upcast_axes), ( - f"N({self.dims[0]}) x M({self.dims[1]}) != local({2**local_axes}) x upcast({2**upcast_axes}) with opts({self.opts})") - assert 2**local_axes == self.threads, f"{self.threads} threads construct the warp but found {2**local_axes} in {self.opts}" - assert 2**upcast_axes == self.elements_per_thread[2], ( - f"{self.elements_per_thread[2]} elements from C are processed per thread but found {2**upcast_axes} in {self.opts}") - assert all(len(perm[0]) == local_axes and len(perm[1]) == reduce_axes + upcast_axes for perm in self.swizzle if perm), ( - f"swizzle perm should be of len (({local_axes})({reduce_axes + upcast_axes}))") - -@dataclass(frozen=True) -class Estimates: - # number of FLOPS used in the Kernel - ops:sint = 0 - # bytes accessed in loads and stores - lds:sint = 0 - # total bytes accessed, counting only once for bytes that are accessed multiple times - mem:sint = 0 - def __add__(self, o:Estimates): return Estimates(self.ops + o.ops, self.lds + o.lds, self.mem + o.mem) - def simplify(self): return Estimates(ssimplify(self.ops), ssimplify(self.lds), ssimplify(self.mem)) - @staticmethod - def from_uops(uops:list[UOp], ignore_indexing=False) -> Estimates: - flops: sint = 0 - lds: sint = 0 - mults: sint = 1 - mult_stack: list[sint] = [] - dont_count: set[UOp] = set() - if ignore_indexing: - for u in uops: - if u.op in {Ops.LOAD, Ops.STORE}: - dont_count = dont_count.union(u.src[0].toposort()) - if len(u.src) > 2: dont_count = dont_count.union(u.src[2].toposort()) - elif u.op is Ops.IF: - dont_count = dont_count.union(u.src[0].toposort()) - for u in uops: - if u.op is Ops.RANGE: - mult_stack.append(mults) - mults *= cast(sint, u.src[0].ssimplify()) - # SPECIAL are already counted in mults - mults = mults.substitute({x:x.const_like(0) for x in mults.toposort() if x.op is Ops.SPECIAL}) if isinstance(mults, UOp) else mults - elif u.op is Ops.ENDRANGE: mults = mult_stack.pop(-1) - elif u.op is Ops.SPECIAL: mults *= u.arg[1] # NOTE: we don't push to the mult_stack here, you can't end these - elif u.op is Ops.LOAD: lds += u.dtype.itemsize * mults - elif u.op is Ops.STORE: lds += u.src[1].dtype.itemsize * mults - elif u.op in GroupOp.ALU and u not in dont_count: flops += (mults * (2 if u.op is Ops.MULACC else 1)) * u.dtype.count - elif u.op is Ops.WMMA and u not in dont_count: flops += 2 * prod(u.arg[1]) // u.arg[5] * mults - return Estimates(flops, lds, lds) # TODO: properly track memory, lds is always a high estimate - -@dataclass -class ProgramSpec: - name:str - src:str - device:str - ast:UOp # save the base ast (this is method cache key) - uops:Optional[list[UOp]]=None - applied_opts:Optional[list[Opt]]=None - mem_estimate:sint=0 # TODO: get this from the load/store uops once min/max are good - - # filled in from uops (if we have uops) - global_size:Optional[list[int]]=None - local_size:Optional[list[int]]=None - vars:list[Variable]=field(default_factory=list) - globals:list[int]=field(default_factory=list) - outs:list[int]=field(default_factory=list) - ins:list[int]=field(default_factory=list) - _ran_post_init:bool=False # NOTE: this is needed if you call replace on the Program - - def __post_init__(self): - if not self._ran_post_init and self.uops is not None: - # single pass through the uops - for u in self.uops: - if u.op is Ops.DEFINE_VAR: self.vars.append(u) - if u.op is Ops.DEFINE_GLOBAL: self.globals.append(u.arg) - if u.op is Ops.STORE: self.outs.extend([x.arg for x in u.src[0].toposort() if x.op is Ops.DEFINE_GLOBAL]) - if u.op is Ops.LOAD: self.ins.extend([x.arg for x in u.src[0].toposort() if x.op is Ops.DEFINE_GLOBAL]) - if u.op is Ops.SPECIAL: - # NOTE: you have to set local_size and global_size to the base [1,1,1] outside this - if u.arg[0][0] == 'i': self.local_size = None - special_size = self.local_size if u.arg[0][0] == 'l' else self.global_size - if special_size is not None: special_size[int(u.arg[0][-1])] = u.arg[1] - self.vars = sorted(self.vars, key=lambda v: v.arg) - self.outs = sorted(dedup(self.outs)) - self.ins = sorted(dedup(self.ins)) - self._ran_post_init = True - - @functools.cached_property - def estimates(self) -> Estimates: - return replace(Estimates() if self.uops is None else Estimates.from_uops(self.uops, ignore_indexing=True), mem=self.mem_estimate) - - @functools.cached_property - def function_name(self) -> str: return to_function_name(self.name) - - def launch_dims(self, var_vals:dict[Variable, int]): - global_size = [sym_infer(sz, var_vals) for sz in self.global_size] if self.global_size is not None else None - local_size = [sym_infer(sz, var_vals) for sz in self.local_size] if self.local_size is not None else None - return global_size, local_size - -class Renderer: - device: str = "" - suffix: str = "" - # TODO: make this generic with a list of supported types - supports_float4: bool = True - has_local: bool = True - has_shared: bool = True - # NOTE: these two should be in (x,y,z) order to match the max_sizes argument in get_grouped_dims - global_max: Optional[tuple[int, ...]] = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now - local_max: Optional[tuple[int, ...]] = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now - shared_max: int = 32768 - tensor_cores: list[TensorCore] = [] - pre_matcher: Optional[PatternMatcher] = None - extra_matcher: Optional[PatternMatcher] = None - code_for_op: dict[Ops, Callable] = {} - - def __reduce__(self): return self.__class__, () - def render(self, uops:list[UOp]) -> str: raise NotImplementedError("needs a renderer") diff --git a/tinygrad/tinygrad/renderer/cstyle.py b/tinygrad/tinygrad/renderer/cstyle.py deleted file mode 100644 index 0d6bb112..00000000 --- a/tinygrad/tinygrad/renderer/cstyle.py +++ /dev/null @@ -1,504 +0,0 @@ -from typing import Literal, Callable, cast -import os, math, sys -from collections import defaultdict, Counter -from tinygrad.uop.ops import GroupOp, Ops, UOp, PatternMatcher, UPat -from tinygrad.helpers import strip_parens, getenv, prod, dedup, AMX -from tinygrad.dtype import ImageDType, dtypes, DType, PtrDType -from tinygrad.renderer import Renderer, TensorCore -from tinygrad.codegen.devectorizer import no_vectorized_alu - -base_rewrite = PatternMatcher([ - (UPat(Ops.DEFINE_ACC, name="x"), lambda ctx,x: ctx[x.src[0]]), - (UPat(Ops.ASSIGN, name="x"), lambda ctx,x: f"{ctx[x.src[0]]} = {ctx[x.src[1]]};"), - (UPat(Ops.IF, name="x"), lambda ctx,x: f"if ({ctx[x.src[0]]}) {{"), - (UPat((Ops.ENDIF, Ops.ENDRANGE)), lambda ctx: "}"), - (UPat(Ops.WMMA, name="x"), lambda ctx,x: f"__{x.arg[0]}({ctx[x.src[0]]}, {ctx[x.src[1]]}, {ctx[x.src[2]]})"), - # r method accesses - (UPat(Ops.RANGE, name="x"), - lambda ctx,x: f"for ({ctx.render_dtype(x.dtype)} {ctx[x]} = 0; {ctx[x]} < {ctx[x.src[0]]}; {ctx[x]}++) {{"), - (UPat(Ops.VECTORIZE, name="x"), - lambda ctx,x: f"{ctx.float4.replace('float4', ctx.render_dtype(x.dtype))}" + \ - f"{ctx.float4_style[0]}{','.join([ctx[y] for y in x.src])}{ctx.float4_style[1]}"), - (UPat(Ops.CAST, name="x"), lambda ctx,x: - f"__builtin_convertvector({ctx[x.src[0]]}, {ctx.render_dtype(x.dtype)})" if x.dtype.count > 1 and not isinstance(x.dtype, PtrDType) else None), - (UPat(Ops.CAST, name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, ctx[x.src[0]])})"), - (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f"(*(({ctx.buffer_prefix}{ctx.render_dtype(x.dtype)}*)&{ctx[x.src[0]]}))"), - (UPat(Ops.DEFINE_LOCAL, name="x"), lambda ctx,x: f"{ctx.smem_align}{ctx.smem_prefix}{ctx.render_dtype(x.dtype.base)} {ctx[x]}[{x.dtype.size}];"), - (UPat(Ops.BARRIER), lambda ctx: ctx.barrier), - (UPat(Ops.NOOP, name="x"), lambda ctx,x: ctx[x.src[0]]), - (UPat(Ops.SPECIAL, name="x"), lambda ctx,x: f"{ctx.code_for_workitem[x.arg[0][0]](x.arg[0][-1])}; /* {x.arg[1]} */"), - # const - (UPat(Ops.CONST, arg=math.inf, name="x"), lambda ctx, x: f"({ctx.render_cast(x.dtype, ctx.infinity)})"), - (UPat(Ops.CONST, arg=-math.inf, name="x"), lambda ctx, x: f"({ctx.render_cast(x.dtype, f'-{ctx.infinity}')})"), - (UPat(Ops.CONST, dtype=dtypes.floats, name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, ctx.nan)})" if math.isnan(x.arg) else None), - (UPat(Ops.CONST, dtype=dtypes.float, name="x"), lambda ctx,x: f"{x.arg}f"), - (UPat(Ops.CONST, dtype=dtypes.int64, name="x"), lambda ctx,x: f"{x.arg}ll"), - (UPat(Ops.CONST, dtype=dtypes.uint64, name="x"), lambda ctx,x: f"{x.arg}ull"), - (UPat(Ops.CONST, dtype=dtypes.uint32, name="x"), lambda ctx,x: f"{x.arg}u"), - (UPat(Ops.CONST, dtype=dtypes.bool, name="x"), lambda ctx,x: "1" if x.arg else "0"), - # consts are rendered to larger type and casted - (UPat(Ops.CONST, (dtypes.bfloat16, dtypes.half), name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, f'{x.arg}f')})"), - (UPat(Ops.CONST, (dtypes.uint8, dtypes.uint16), name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, f'{x.arg}u')})"), - (UPat(Ops.CONST, (dtypes.int8, dtypes.int16), name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, x.arg)})"), - # default const render - (UPat(Ops.CONST, name="x"), lambda ctx,x: str(x.arg)), - # new load/store - (UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var('idx')), allow_any_len=True), - lambda ctx,buf,idx: f"({ctx[buf]}+{strip_parens(ctx[idx]) if idx.arg == Ops.ADD else ctx[idx]})"), - (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat(), UPat(), UPat.var("gate"))).or_casted("bidx"), UPat.var("var")), allow_any_len=True), - lambda ctx,bidx,var,gate: f"({ctx[gate]}?*{ctx[bidx]}:{ctx[var]})"), - (UPat(Ops.LOAD, src=(UPat.var('bidx'),), allow_any_len=True), lambda ctx,bidx: f"*{ctx[bidx]}"), - (UPat(Ops.STORE, src=(UPat.var('bidx'), UPat.var("var")), allow_any_len=True), lambda ctx,bidx,var: f"*{ctx[bidx]} = {ctx[var]};"), - # alu/gep - # TODO: look for left-associative - (UPat(GroupOp.ALU, name="x"), lambda ctx,x: ctx.code_for_op[x.op]( - *([strip_parens(ctx[v]) if v.op == x.op and x.op in {Ops.ADD, Ops.MUL, Ops.XOR, Ops.OR, Ops.AND} else ctx[v] for v in x.src]), x.dtype)), - (UPat(Ops.GEP, name="x"), lambda ctx,x: ctx[x.src[0]] + \ - (f"[{x.arg[0]}]" if x.src[0].dtype.count > ctx.gep_arr_threshold else f".{'xyzwabcd'[x.arg[0]]}")), - # custom passes through with format - (UPat((Ops.CUSTOM, Ops.CUSTOMI), name="x"), lambda ctx,x: x.arg.format(*[ctx[y] for y in x.src])), -]) - -extra_pm = PatternMatcher([ - # insert a NOOP before BITCAST to force it to be rendered. not needed on all backends? - (UPat(Ops.BITCAST, name="x"), - lambda x: UOp(Ops.BITCAST, x.dtype, (UOp(Ops.NOOP, x.src[0].dtype, x.src),)) if x.src[0].op not in {Ops.NOOP, Ops.LOAD, Ops.CUSTOM} else None), - # rewrite MAX to CMPLT + WHERE (max function is annoying on many cstyle backends) - (UPat(Ops.MAX, name="m"), lambda m: (m.src[0] < m.src[1]).where(m.src[1], m.src[0])), - # devectorize any bools - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.ASSIGN, Ops.INDEX), dtype=dtypes.bool, name="alu"), no_vectorized_alu), - # CAST (from bool) can't be vectorized - (UPat(Ops.CAST, src=(UPat(dtype=dtypes.bool),), name="alu"), no_vectorized_alu), - # WHERE can't be vectorized - (UPat(Ops.WHERE, name="alu"), no_vectorized_alu), -]) - -def uops_to_dtypes(uops:list[UOp]) -> list[DType]: return dedup(u.dtype for u in uops if not isinstance(u.dtype, (ImageDType, PtrDType))) - -class CStyleLanguage(Renderer): - kernel_typedef: str = "void" - buffer_prefix: str = "" - buffer_suffix: str = "" - smem_align: str = "" - smem_prefix: str = "" - smem_prefix_for_cast: bool = True - arg_int_prefix: str = "const int" - barrier: str = "" - code_for_workitem: dict[Literal["g", "l", "i"], Callable] = {} - extra_args: list[str] = [] - float4: str|None = None - float4_style: tuple[str, str] = ('(', ')') - gep_arr_threshold: int = 4 - type_map: dict[DType, str] = {} - infinity: str = "INFINITY" - nan: str = "NAN" - code_for_op: dict = { - Ops.SQRT: lambda x,dtype: f"sqrt({x})", Ops.RECIP: lambda x,dtype: f"(1/{x})", Ops.NEG: lambda x,dtype: f"-{x}", - Ops.EXP2: lambda x,dtype: f"exp2({x})", Ops.LOG2: lambda x,dtype: f"log2({x})", Ops.SIN: lambda x,dtype: f"sin({x})", - Ops.AND: lambda a,b,dtype: f"({a}&{b})", Ops.XOR: lambda a,b,dtype: f"({a}^{b})", Ops.OR: lambda a,b,dtype: f"({a}|{b})", - Ops.ADD: lambda a,b,dtype: f"({a}+{b})", Ops.SUB: lambda a,b,dtype: f"({a}-{b})", Ops.MUL: lambda a,b,dtype: f"({a}*{b})", - Ops.MOD: lambda a,b,dtype: f"({a}%{b})", Ops.IDIV: lambda a,b,dtype: f"({a}/{b})", Ops.CMPNE: lambda a,b,dtype: f"({a}!={b})", - Ops.SHR: lambda a,b,dtype: f"({a}>>{b})", Ops.SHL: lambda a,b,dtype: f"({a}<<{b})", Ops.CMPLT: lambda a,b,dtype: f"({a}<{b})", - Ops.WHERE: lambda a,b,c,dtype: f"({a}?{b}:{c})" } - - string_rewrite = base_rewrite - extra_matcher = extra_pm - - def render_kernel(self, function_name:str, kernel:list[str], bufs:list[tuple[str,tuple[DType,bool]]], uops:list[UOp], prefix=None) -> str: - tmp = "const sampler_t smp = CLK_NORMALIZED_COORDS_FALSE | CLK_ADDRESS_CLAMP | CLK_FILTER_NEAREST;\n" if any(isinstance(dtype, ImageDType) for _,(dtype,_) in bufs) else "" # noqa: E501 - buftypes = [(name, self.render_dtype(dtype, mutable)+self.buffer_suffix if isinstance(dtype, (ImageDType, PtrDType)) else - self.arg_int_prefix if dtype == dtypes.int else None) for name,(dtype,mutable) in bufs] - launch_bounds = prod(u.arg[1] for u in uops if u.op is Ops.SPECIAL and u.arg[0][0] == "l") - prg = ''.join([f"{self.kernel_typedef.format(launch_bounds=launch_bounds)} {function_name}(",] + - [', '.join([f'{t} {name}' for name,t in buftypes] + self.extra_args)] + - [") {\n" + tmp] + ['\n'.join(kernel), "\n}"]) - return prg if prefix is None else "\n".join(prefix)+f"\n{prg}" - - def render_cast(self, dt:DType, val: str) -> str: return f"({self.render_dtype(dt)})({val})" - def render_dtype(self, dt:DType, mutable=True) -> str: - if isinstance(dt, ImageDType): return f"{'write_only' if mutable else 'read_only'} image2d_t" - if isinstance(dt, PtrDType): - return (self.smem_prefix if dt.local and self.smem_prefix_for_cast else self.buffer_prefix) + self.render_dtype(dt.base) + "*" - if dt.count > 1: return self.type_map.get(scalar:=dt.scalar(), scalar.name).replace(" ", "_") + str(dt.count) - return self.type_map.get(scalar:=dt.scalar(), scalar.name) - - def __getitem__(self, key): return self.r[key] # hacky helper - def _render(self, uops:list[UOp]) -> tuple[str, list[str], list[tuple[str,tuple[DType,bool]]]]: - r: dict[UOp, str] = {} - self.r = r - - child_count = Counter(v for ru in uops for v in ru.src) - bufs: dict[UOp, tuple[str, tuple[DType, bool]]] = {} - kernel = [] - depth = 1 - c: defaultdict[str, int] = defaultdict(int) - name = "test" - for u in uops: - if u.op is Ops.SINK: - if u.arg is not None: name = u.arg.name - continue - if u.op in (Ops.DEFINE_GLOBAL, Ops.DEFINE_VAR): - r[u] = f"data{u.arg}" if u.op is Ops.DEFINE_GLOBAL else u.arg[0] - bufs[u] = (r[u], (u.dtype, False)) - continue - - # mark buffers that we store to writable - if u.op is Ops.STORE: - for up in u.src[0].toposort(): - if up.op is Ops.DEFINE_GLOBAL: bufs[up] = (bufs[up][0], (bufs[up][1][0], True)) - - # naming - prefix = None - if u.op is Ops.SPECIAL: r[u] = u.arg[0] - elif u.op is Ops.RANGE: r[u] = f"ridx{u.arg}" - else: - prefix = {Ops.WMMA: "wmma", Ops.DEFINE_LOCAL: "temp", Ops.CONST: "const", - Ops.CAST: "cast", Ops.BITCAST: "cast", Ops.GEP: "gep", Ops.VECTORIZE: "cast", Ops.NOOP: "precast", - Ops.INDEX: "bidx", Ops.DEFINE_ACC: "acc", Ops.LOAD: "val"}.get(u.op, "alu") - r[u] = f"{prefix}{c[prefix]}" - - l = cast(str, self.string_rewrite.rewrite(u, ctx=self)) - assert l is not None, f"failed to render {u.op} {u.dtype} {[(x.op,x.dtype) for x in u.src]} {u.arg}" - - if u.op in {Ops.ENDIF, Ops.ENDRANGE}: depth -= 1 - if (u.op is not Ops.CAST or u.dtype.vcount == 1) and (u.op in {Ops.CONST, Ops.GEP, Ops.INDEX, Ops.CUSTOMI} or \ - (u.op in {Ops.VECTORIZE, *(GroupOp.ALU-{Ops.WHERE}), Ops.CAST, Ops.BITCAST} and child_count[u] == 1 and not getenv("EXPAND_SSA"))): - r[u] = l - else: - if u.op in {Ops.RANGE, Ops.ASSIGN, Ops.DEFINE_LOCAL} or u.dtype == dtypes.void: - if u.op is Ops.ASSIGN: r[u] = r[u.src[0]] - else: - l = f"{self.render_dtype(u.dtype)} {r[u]} = {l}" + (";" if u.op is not Ops.SPECIAL else "") - kernel.append(" "*depth + l) - if prefix: c[prefix] += 1 # if it was used, increment - if u.op in {Ops.IF, Ops.RANGE}: depth += 1 - del self.r - - # NOTE: this relies on bufs dict preserving order - return (name, kernel, list(bufs.values())) - def render(self, uops:list[UOp]) -> str: return self.render_kernel(*self._render(uops), uops) - -class ClangRenderer(CStyleLanguage): - device = "CPU" - float4 = "(float4)" - float4_style = ('{', '}') - gep_arr_threshold = 0 - has_local = False - global_max = None - infinity = "__builtin_inff()" - nan = '__builtin_nanf("")' - amx_tc = [TensorCore(dims=(sz,sz,1), threads=1, elements_per_thread=(sz,sz,sz*sz), dtype_in=dt, dtype_out=dt, swizzle=(None,((),(4,5,6,7,0,1,2,3))), - opts=("u0","u0","u0","u0","u1","u1","u1","u1")) for dt,sz in [(dt, 64 // dt.itemsize) for dt in [dtypes.float]]] - if AMX: tensor_cores = amx_tc - - # language options - buffer_suffix = " restrict" - type_map = {dtypes.bool:"_Bool", dtypes.half:"__fp16"} - code_for_op = {**({k:v for k,v in CStyleLanguage.code_for_op.items() if k not in [Ops.EXP2, Ops.SIN, Ops.LOG2]}), - Ops.SQRT: lambda x,dtype: f"__builtin_sqrt({x})" if dtype == dtypes.float64 else f"__builtin_sqrtf({x})"} - # LLVM legalizes double => half cast on systems that don't support it natively (like x86 cpus without AVX512-FP16) into a compiler-rt libcall. - extra_matcher = PatternMatcher([(UPat.var("x", dtypes.float64).cast(dtypes.float16), lambda x: x.cast(dtypes.float32).cast(dtypes.float16)), - (UPat(Ops.SQRT, name="alu"), no_vectorized_alu),]) + CStyleLanguage.extra_matcher - - if sys.platform == 'win32': - kernel_typedef = "__attribute__((ms_abi)) void" - def render_vector_prefix(self, dt:DType) -> str: - # round (down) to power of two (this is actually the default clang behavior) - alignment = 2**int(math.log2(dt.itemsize)) if getenv("ALIGNED", 1) else 1 - return f"typedef {self.render_dtype(dt.scalar())} {self.render_dtype(dt)} __attribute__((aligned({alignment}),vector_size({dt.itemsize})));" - - def _render_defines(self, uops) -> list[str]: - prefix = [self.render_vector_prefix(dt) for dt in uops_to_dtypes(uops) if dt.count > 1] - # https://github.com/corsix/amx - for name, (N, M, _), dtype_in, _, _, _, _, _ in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): - prefix += [ - '#define AMX_SET(imm5) __asm("nop\\nnop\\nnop\\n.word (0x201000+(%0<<5)+%1)" : : "i"(17), "i"(imm5) : "memory")', - '#define AMX(op, gpr, btf) __asm(".word (0x201000+(%0 << 5)+0%1-((0%1>>4)*6))" : : "i"(op), "r"((unsigned long long)(gpr)+(btf)) : "memory")', - ] - # 'static' in C roughly means that function symbol isn't exported. LLVM puts those symbols at the end of object file which allows Clang JIT - # to just jump at the start of a shellcode whithout having to deal with symbols or trampolines at all. This is better than having to inline - # wmma function every time it is called or wasting complexity on a symbol parsing and a memory page on trampoline. - prefix += [f"""static {(out := self.render_dtype(dtype_in.vec(N*N)))} __{name}({self.render_dtype(dtype_in.vec(N))} data1, {self.render_dtype(dtype_in.vec(M))} data2, {out} data0){{ - AMX_SET(0);\n for(int ridx0 = 0; ridx0 < 16; ridx0++){{ AMX(4, (int *)(&data0), 0ull<<62 | (ridx0*4ull)<<56 | ridx0*64ull); }} - AMX(0, (int *)(&data2), 0ull<<62); AMX(1, (int *)(&data1), 0ull<<62); AMX(12, 0, 0ull); - for(int ridx0 = 0; ridx0 < 16; ridx0++){{ AMX(5, (int *)(&data0), 0ull<<62 | (ridx0*4ull)<<56 | ridx0*64ull); }}\n AMX_SET(1);\n return data0;\n}}"""] # noqa: E501 - return prefix - def _render_body(self, function_name, kernel, bufs, uops, pref=None) -> str: return super().render_kernel(function_name, kernel, bufs, uops, pref) - def _render_entry(self, function_name:str, bufs:list[tuple[str,tuple[DType,bool]]]) -> str: return "" - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None) -> str: - defines = '\n'.join(self._render_defines(uops)) - return defines + "\n" + self._render_body(function_name, kernel, bufs, uops, prefix) + "\n" + self._render_entry(function_name, bufs) - -class OpenCLRenderer(CStyleLanguage): - device = "GPU" - - # language options - kernel_typedef = "__kernel void" - buffer_prefix = "__global " - smem_align = "__attribute__ ((aligned (16))) " - smem_prefix = "__local " - barrier = "barrier(CLK_LOCAL_MEM_FENCE);" - float4 = "(float4)" - code_for_workitem = {"g": lambda x: f"get_group_id({x})", "l": lambda x: f"get_local_id({x})", "i": lambda x: f"get_global_id({x})"} - type_map = { dtypes.int8: "char", dtypes.uint8: "uchar", dtypes.uint32: "uint", dtypes.uint16: "ushort", dtypes.uint64: "ulong", - dtypes.bfloat16: "ushort" } - - string_rewrite = PatternMatcher([ - (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f"as_{ctx.render_dtype(x.dtype)}({ctx[x.src[0]]})"), - # load/store image (OpenCL) - (UPat(Ops.LOAD, dtype=dtypes.float.vec(4), src=(UPat.var('buf').index(UPat.var('idx', dtypes.int.vec(2)), UPat.var("gate")), UPat.var("var"))), - lambda ctx,buf,idx,var,gate: f"({ctx[gate]}?read_imagef({ctx[buf]}, smp, {ctx[idx]}):{ctx[var]})"), - (UPat(Ops.LOAD, dtype=dtypes.float.vec(4), src=(UPat.var('buf').index(UPat.var('idx', dtypes.int.vec(2))),)), - lambda ctx,buf,idx: f"read_imagef({ctx[buf]}, smp, {ctx[idx]})"), - (UPat(Ops.STORE, src=(UPat.var('buf').index(UPat.var('idx', dtypes.int.vec(2))), UPat.var("var", dtypes.float.vec(4))), allow_any_len=True), - lambda ctx,buf,idx,var: f"write_imagef({ctx[buf]}, {ctx[idx]}, {ctx[var]});"), - ]) + base_rewrite - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None) -> str: - if any(uop.dtype.base == dtypes.half for uop in uops): prefix = (["#pragma OPENCL EXTENSION cl_khr_fp16 : enable"] + (prefix or [])) - return super().render_kernel(function_name, kernel, bufs, uops, prefix) - -class IntelRenderer(OpenCLRenderer): - device, suffix, kernel_typedef = "GPU", "INTEL", "__attribute__((intel_reqd_sub_group_size(8)))\n" + "__kernel void" - tensor_cores = [TensorCore(dims=(8,8,16), threads=8, elements_per_thread=(16,16,8), dtype_in=dtypes.half, dtype_out=dtypes.float, - opts=("l0","l0","l0","u1","u1","u1"), swizzle=(((4,5,6),(0,1,2,3,7,8,9)), ((0,1,2),(7,8,9,3,4,5,6))))] - - string_rewrite = PatternMatcher([ - (UPat(Ops.CAST, dtype=dtypes.bfloat16, src=(UPat.var('x', dtype=dtypes.float),)), lambda ctx,x: f"intel_convert_bfloat16_as_ushort({ctx[x]})"), - (UPat(Ops.CAST, dtype=dtypes.float, src=(UPat.var('x', dtype=dtypes.bfloat16),)), lambda ctx,x: f"intel_convert_as_bfloat16_float({ctx[x]})"), - ]) + OpenCLRenderer.string_rewrite - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None) -> str: - prefix = [] - for arg in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): - dt_in = ("ushort", "bf16") if arg[2] == dtypes.bfloat16 else (arg[2].name, "f16") - prefix.append(f"""{arg[3].name}8 __{arg[0]}({dt_in[0]}16 a, {dt_in[0]}16 b, {arg[3].name}8 c) {{ - return intel_sub_group_{dt_in[1]}_{dt_in[1]}_matrix_mad_k16(as_int8(a), as_int8(b), c);\n}}""") - return super().render_kernel(function_name, kernel, bufs, uops, prefix or None) - -class MetalRenderer(CStyleLanguage): - device = "METAL" - shared_max = 32768 - tensor_cores = [TensorCore(dims=(8,8,8), threads=32, elements_per_thread=(2,2,2), dtype_in=di, dtype_out=do, opts=("u0","l0","l1","l1","l0","l1"), - swizzle=(((6,1,2,7,4),(8,0,3,5)), ((0,5,6,3,7),(1,2,4,8)))) for di,do in [(dtypes.float,dtypes.float),(dtypes.half,dtypes.float), - (dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] - def __init__(self): self.tensor_cores = MetalRenderer.tensor_cores if hasattr(os, 'uname') and os.uname().machine == "arm64" else [] - - # language options - kernel_typedef = "kernel void" - buffer_prefix = "device " - smem_prefix = "threadgroup __attribute__((aligned(16))) " - arg_int_prefix = "constant int&" - barrier = "threadgroup_barrier(mem_flags::mem_threadgroup);" - float4 = "float4" - code_for_workitem = {"g": lambda x: f"gid.{chr(120+int(x))}", "l": lambda x: f"lid.{chr(120+int(x))}"} - # uint3 used for gid/lid - TODO: this should probably be `ushort3 lid [[thread_position_in_threadgroup]]` - extra_args = ['uint3 gid [[threadgroup_position_in_grid]]', 'uint3 lid [[thread_position_in_threadgroup]]'] - type_map = {dtypes.bfloat16: "bfloat"} - - # precise::sin - code_for_op = {**CStyleLanguage.code_for_op, Ops.SIN: lambda x,dtype: f"precise::sin({x})"} - - # upcast to float32 all the ops that don't support bfloat16 - extra_matcher = PatternMatcher([ - # NOTE: this is copied from PTX - (UPat((Ops.SQRT, Ops.EXP2, Ops.LOG2, Ops.SIN), dtype=dtypes.bfloat16, name="x"), - lambda x: (UOp(x.op, dtypes.float, tuple(vv.cast(dtypes.float) for vv in x.src), x.arg).cast(dtypes.bfloat16))), - ]) + extra_pm - - string_rewrite = PatternMatcher([ - (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f"as_type<{ctx.render_dtype(x.dtype)}>({ctx[x.src[0]]})"), - ]) + base_rewrite - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None): - prefix, wmma_args = ["#include ","using namespace metal;"], set([uop.arg for uop in uops if uop.op is Ops.WMMA]) - for arg in wmma_args: prefix.append( - f"""{(dtype_out:=self.render_dtype(arg[3].vec(2)))} __{arg[0]}({(dtype_in:=self.render_dtype(arg[2].vec(2)))} a, {dtype_in} b, {dtype_out} c){{ - simdgroup_{self.render_dtype(arg[2])}8x8 mat_a, mat_b; simdgroup_{self.render_dtype(arg[3])}8x8 mat_c; - mat_a.thread_elements()[0] = a[0]; mat_b.thread_elements()[0] = b[0]; mat_c.thread_elements()[0] = c[0]; - mat_a.thread_elements()[1] = a[1]; mat_b.thread_elements()[1] = b[1]; mat_c.thread_elements()[1] = c[1]; - simdgroup_multiply_accumulate(mat_c, mat_a, mat_b, mat_c);\n return {dtype_out}(mat_c.thread_elements()[0], mat_c.thread_elements()[1]);\n}}""") - return super().render_kernel(function_name, kernel, bufs, uops, prefix) - -_nms = "xyzwabcdefghijkl" -cuda_tc_opts = ("u0","l0","l0","l1","l1","l1","u1") # shared by all shapes with M=16 N=8 - -class CUDARenderer(CStyleLanguage): - device = "CUDA" - global_max = (2147483647, 65535, 65535) - local_max = (1024, 1024, 64) - shared_max = 49152 - # https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-multiply-accumulate-instructions - tc_81616 = [TensorCore(dims=(8,16,16), threads=32, elements_per_thread=(8,4,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, - swizzle=(((6,7,2,3,4),(0,1,9,5,10,8)), ((6,7,9,0,1),(2,3,4,10,5,8)))) for di,do in [(dtypes.half,dtypes.float), (dtypes.bfloat16,dtypes.float), - (dtypes.half,dtypes.half)]] - tc_8168_f16 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, - swizzle=(((6,7,2,3,4),(0,1,8,5,9)), ((6,7,8,0,1),(2,3,4,9,5)))) for di,do in [(dtypes.half,dtypes.float), (dtypes.half,dtypes.half)]] - tc_8168_tf32 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=dtypes.float, dtype_out=dtypes.float, opts=cuda_tc_opts, - swizzle=(((5,6,2,3,4),(0,1,8,9,7)), ((5,6,8,0,1),(2,3,4,9,7))))] - - tc_sm80 = tc_81616 + tc_8168_f16 - if getenv("ALLOW_TF32", 0): tc_sm80 += tc_8168_tf32 - tc_sm75 = tc_8168_f16 - def __init__(self, arch:str): - self.tensor_cores, self.arch = CUDARenderer.tc_sm80 if int(arch[3:]) >= 80 else CUDARenderer.tc_sm75 if int(arch[3:]) >= 75 else [], arch - def __reduce__(self): return self.__class__, (self.arch,) - - # language options - # https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html - kernel_typedef = "extern \"C\" __global__ void __launch_bounds__({launch_bounds})" - smem_prefix = "__shared__ __align__(16) " - smem_prefix_for_cast = False - barrier = "__syncthreads();" - float4 = "make_float4" - gep_arr_threshold = 8 - code_for_workitem = {"g": lambda x: f"blockIdx.{chr(120+int(x))}", "l": lambda x: f"threadIdx.{chr(120+int(x))}", - "i": lambda x: f"(blockIdx.{chr(120+int(x))}*blockDim.{chr(120+int(x))}+threadIdx.{chr(120+int(x))})"} - code_for_op = { **CStyleLanguage.code_for_op, - Ops.SIN: lambda x,dtype: f"hsin({x})" if dtype in (dtypes.half, dtypes.bfloat16) else f"sin({x})", - Ops.LOG2: lambda x,dtype: f"hlog2({x})" if dtype in (dtypes.half, dtypes.bfloat16) else f"log2({x})", - Ops.EXP2: lambda x,dtype: f"hexp2({x})" if dtype in (dtypes.half, dtypes.bfloat16) else f"exp2({x})", - Ops.SQRT: lambda x,dtype: f"hsqrt({x})" if dtype in (dtypes.half, dtypes.bfloat16) else f"sqrt({x})", - Ops.RECIP: lambda x,dtype: f"hrcp({x})" if dtype in (dtypes.half, dtypes.bfloat16) else f"(1/{x})" } - type_map = {dtypes.bfloat16: "nv_bfloat16"} - - def render_vector_prefix(self, dt:DType) -> str: - vec, scal = self.render_dtype(dt), self.render_dtype(dt.scalar()), - elems, header = ', '.join(_nms[:dt.count]), ', '.join([f"{scal} {x}" for x in _nms[:dt.count]]) - return f"struct __align__({dt.itemsize}) {vec} {{ {scal} {elems}; }}; __device__ {vec} make_{vec}({header}) {{ {vec} r={{{elems}}}; return r; }}" - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None): - # TODO: why is dtypes.bfloat16.name == "__bf16"? would be easier not override dtypes.name - prefix = ["#define INFINITY (__int_as_float(0x7f800000))","#define NAN (__int_as_float(0x7fffffff))"] - - used_dtypes = uops_to_dtypes(uops) - if any(dt.scalar() == dtypes.half for dt in used_dtypes): prefix.append("#include ") - if any(dt.scalar() == dtypes.bfloat16 for dt in used_dtypes): prefix.append("#include ") - prefix += [self.render_vector_prefix(dt) for dt in used_dtypes if dt.count in (4,8) and dt.scalar() in {dtypes.half, dtypes.bfloat16}] - - dt_map_in = { dtypes.float: "tf32", dtypes.half: "f16", dtypes.bfloat16: "bf16" } - dt_map_out = { dtypes.float: "f32", dtypes.half: "f16" } - for name, (N, M, K), dtype_in, dtype_out, _, _, upcast_axes, _ in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): - upcast_sizes = [prod(size for _, size in upcast) for upcast in upcast_axes] - wmma_dtypes = [self.render_dtype(dtype.vec(size)) for dtype, size in zip([dtype_in, dtype_in, dtype_out], upcast_sizes)] - n_operands = [size*dtype.itemsize//4 for dtype, size in zip([dtype_in, dtype_in, dtype_out], upcast_sizes)] # 4 => CUDA reg size in bytes - operands = [f"%{i}" for i in range(sum(n_operands))] - - # mma operands => {c}, {a}, {b}, {c} - prefix.append(f"""__device__ {wmma_dtypes[2]} __{name}({wmma_dtypes[0]} a, {wmma_dtypes[1]} b, {wmma_dtypes[2]} c){{ - int *a_pk = (int *)(&a), *b_pk = (int *)(&b), *c_pk = (int *)(&c); - asm("mma.sync.aligned.m{M}n{N}k{K}.row.col.{dt_map_out[dtype_out]}.{dt_map_in[dtype_in]}.{dt_map_in[dtype_in]}.{dt_map_out[dtype_out]}" - "{{{", ".join(operands[:n_operands[2]])}}}, {{{", ".join(operands[n_operands[2]:n_operands[2]+n_operands[0]])}}}," - "{{{", ".join(operands[-n_operands[1]:])}}}, {{{", ".join(operands[:n_operands[2]])}}};" - : {", ".join([f'"+r"(c_pk[{i}])' for i in range(n_operands[2])])} - : {", ".join([f'"r"(a_pk[{i}])' for i in range(n_operands[0])])}, {", ".join([f'"r"(b_pk[{i}])' for i in range(n_operands[1])])}); - return c;\n}}""") - - return super().render_kernel(function_name, kernel, bufs, uops, prefix=prefix) - -def cast_float_to_bf16(x: UOp) -> UOp: - assert x.dtype == dtypes.float, "cast float -> bf16 must start with float" - x = x.bitcast(dtypes.uint) - x = (-x & 0x7f800000).where(x + ((x >> 16) & 1) + 0x7fff, (x & 0xffff).where((x | 0x10000), x)) - return (x >> 16).cast(dtypes.ushort).bitcast(dtypes.bfloat16) - -class AMDRenderer(CStyleLanguage): - device = "AMD" - shared_max = 65536 - # NOTE: this is only really needed on gfx12, even though gfx11 reports the same limitation - global_max = (2147483647, 65535, 65535) - # https://gpuopen.com/learn/wmma_on_rdna3/ - tensor_cores = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(16,16,8), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","l1","u1","u1","u1"), swizzle=(((4,9,10,11,0),(1,2,3,5,6,7,8)), ((0,1,2,3,4),(9,10,11,5,6,7,8)))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float)]] - tensor_cores_rdna4 = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(8,8,8), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","u1","u1","u1","l1"), swizzle=(((9,10,11,4,7),(0,1,2,3,5,6,8)),((0,1,2,3,7),(4,9,10,11,5,6,8)))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] - # https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme - tensor_cores_mfma = [TensorCore(dims=(16,16,16), threads=64, elements_per_thread=(4,4,4), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","u1","u1","l1","l1"), swizzle=(((10,11,4,5,8,9),(0,1,2,3,6,7)),((0,1,2,3,8,9),(4,5,10,11,6,7)))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.bfloat16,dtypes.float)]] - - @staticmethod - def get_tensor_cores(arch): - return {"gfx942": AMDRenderer.tensor_cores_mfma, "gfx1201": AMDRenderer.tensor_cores_rdna4}.get(arch.split(":")[0], AMDRenderer.tensor_cores) - def __init__(self, arch:str): # gfx942 => MI300, gfx1100 => RX 7900, gfx1201 => RX 9700 - self.arch = arch - self.tensor_cores = self.get_tensor_cores(arch) - if self.arch.split(":")[0] == "gfx942": - self.string_rewrite = PatternMatcher([ - (UPat(Ops.WMMA, name="x"), lambda ctx,x: f"__{x.arg[0]}({ctx[x.src[0]]}, {ctx[x.src[1]]}, {ctx[x.src[2]]}, 0, 0, 0)")]) + base_rewrite - def __reduce__(self): return self.__class__, (self.arch,) - - # language options - ockl = [(f"__ockl_get_{name}", "unsigned int", "size_t", "const") for name in ["local_id", "group_id", "local_size"]] - ocml = [(f"__ocml_{name}_f{n}", f"{dt}, {dt}" if "fmax" == name else dt, dt, atr) - for dt, n in [(dtype.name, dtype.itemsize * 8) for dtype in [dtypes.float, dtypes.double, dtypes.half]] - for name, atr in [("fmax", "const"), ("exp2", "pure"), ("log2", "pure"), ("sqrt", "const"), ("sin", "")]] - - kernel_typedef = "\n".join(f'extern "C" __attribute__((device{f", {atr}" if atr else ""})) {dto} {meth}({dti});' for meth,dti,dto,atr in ockl+ocml) - # https://clang.llvm.org/docs/AttributeReference.html#amdgpu-flat-work-group-size - # NOTE: this makes hlb_cifar10 twice as fast, there may be more gains in tweaking these parameters - kernel_typedef += '\nextern "C" __attribute__((global)) void __attribute__((amdgpu_flat_work_group_size(1, {launch_bounds})))' - code_for_workitem = {"g": lambda x: f"__ockl_get_group_id({x})", "l": lambda x: f"__ockl_get_local_id({x})", - "i": lambda x: f"(__ockl_get_group_id({x})*__ockl_get_local_size({x})+__ockl_get_local_id({x}))"} - code_for_op = { **CStyleLanguage.code_for_op, - Ops.SIN: lambda x,dtype: f"__ocml_sin_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", - Ops.LOG2: lambda x,dtype: f"__ocml_log2_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", - Ops.EXP2: lambda x,dtype: f"__ocml_exp2_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", - Ops.SQRT: lambda x,dtype: f"__ocml_sqrt_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})" } - smem_prefix = "__attribute__((shared, aligned(16)))" - smem_prefix_for_cast: bool = False - barrier = '__builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup");' + '__builtin_amdgcn_s_barrier();' + \ - '__builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup");' - float4 = "make_float4" - type_map = {dtypes.bfloat16: "hip_bfloat16"} - extra_matcher = PatternMatcher([ - # cast bfloat16 alus to float - (UPat(Ops.WHERE, src=(UPat.var("b"), UPat.var("x", dtype=dtypes.bfloat16), UPat.var("y", dtype=dtypes.bfloat16))), - lambda b,x,y: UOp(Ops.WHERE, dtype=dtypes.float, src=(b,x.cast(dtypes.float),y.cast(dtypes.float))).cast(dtypes.bfloat16)), - (UPat(GroupOp.ALU, dtype=dtypes.bfloat16, name="x"), - lambda x: UOp(x.op, dtypes.float, tuple(vv.cast(dtypes.float) for vv in x.src), x.arg).cast(dtypes.bfloat16)), - (UPat(GroupOp.ALU, dtypes.bool, name="alu", src=(UPat.var("x", dtype=dtypes.bfloat16), UPat.var("y", dtype=dtypes.bfloat16))), - lambda alu,x,y: UOp(alu.op, dtypes.bool, (x.cast(dtypes.float), y.cast(dtypes.float)), alu.arg)), - # add float intermediate casting for bfloat16 - (UPat(Ops.CAST, name="x", src=(UPat.var("y", dtypes.bfloat16),)), - lambda x,y: y.cast(dtypes.float).cast(x.dtype) if x.dtype!=dtypes.float else None), - (UPat(Ops.CAST, dtypes.bfloat16, (UPat.var("x"),)), - lambda x: x.cast(dtypes.float).cast(dtypes.bfloat16) if x.dtype!=dtypes.float else None), - # bfloat16 casting - (UPat.cvar('x', dtypes.bfloat16), lambda x: cast_float_to_bf16(UOp.const(dtypes.float, x.arg))), - (UPat(Ops.CAST, dtypes.float, (UPat.var("x", dtypes.bfloat16),)), - lambda x: (x.bitcast(dtypes.ushort).cast(dtypes.uint)<<16).bitcast(dtypes.float)), - (UPat(Ops.CAST, dtype=dtypes.bfloat16, src=(UPat.var("x", dtype=dtypes.float),)), cast_float_to_bf16)]) + extra_pm - - def render_vector_prefix(self, dtype:DType) -> str: - vec, scal = self.render_dtype(dtype), self.render_dtype(dtype.scalar()) - return f"typedef {scal} {vec} __attribute__((ext_vector_type({dtype.count})));\nstatic inline __attribute__((device)) "+ \ - f"{vec} make_{vec}({', '.join([f'{scal} {x}' for x in _nms[:dtype.count]])}) {{ return {{ {', '.join(_nms[:dtype.count])} }}; }}" - - def render_kernel(self, function_name, kernel, bufs, uops, prefix=None) -> str: - prefix = ["#define INFINITY (__builtin_inff())","#define NAN (__builtin_nanf(\"\"))","typedef long unsigned int size_t;","#define half _Float16"] - type_map = { dtypes.bfloat16: "bf16", dtypes.float: "f32", dtypes.half: "f16" } - used_dtypes = uops_to_dtypes(uops) - if any(dt.scalar() == dtypes.bfloat16 for dt in used_dtypes): prefix.append("typedef unsigned short hip_bfloat16;") - prefix += [self.render_vector_prefix(dt) for dt in used_dtypes if dt.count > 1] - - for arg in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): # TODO: handle TCs f32_bf16 and bf16_bf16 w/ wrapper - if self.arch.split(":")[0] == "gfx942": - prefix.append(f"#define __{arg[0]} __builtin_amdgcn_mfma_f32_16x16x16{'f16' if arg[2] == dtypes.half else 'bf16_1k'}") - # #define __WMMA_16_16_16_half_half __builtin_amdgcn_wmma_f16_16x16x16_f16_w32_gfx12 - elif self.arch.split(":")[0] == "gfx1201": - prefix.append(f"#define __{arg[0]} __builtin_amdgcn_wmma_{type_map[arg[3]]}_16x16x16_{type_map[arg[2]]}_w32_gfx12") - elif arg[3] == dtypes.float: - prefix.append(f"#define __{arg[0]} __builtin_amdgcn_wmma_f32_16x16x16_{'f16' if arg[2] == dtypes.half else 'bf16'}_w32") - else: prefix.append(f"static inline __attribute__((device)) half8 __{arg[0]}"+"""(half16 a, half16 b, half8 c) { - half16 c_frag = {}; half8 d; for (int n = 0; n < 8; n++) { c_frag[n*2] = c[n]; } - c_frag = __builtin_amdgcn_wmma_f16_16x16x16_f16_w32(a, b, c_frag, false); - for (int n = 0; n < 8; n++) { d[n] = c_frag[n*2]; } return d;\n}""") - return super().render_kernel(function_name, kernel, bufs, uops, prefix) - -class NVRenderer(CUDARenderer): device = "NV" -class HIPRenderer(AMDRenderer): device = "HIP" -class QCOMRenderer(OpenCLRenderer): device = "QCOM" diff --git a/tinygrad/tinygrad/renderer/llvmir.py b/tinygrad/tinygrad/renderer/llvmir.py deleted file mode 100644 index 9be32fd2..00000000 --- a/tinygrad/tinygrad/renderer/llvmir.py +++ /dev/null @@ -1,250 +0,0 @@ -from typing import cast -import math, struct, sys -from tinygrad.renderer import Renderer -from tinygrad.renderer.cstyle import ClangRenderer, AMDRenderer -from tinygrad.uop.ops import UOp, PatternMatcher, UPat, Ops, GroupOp -from tinygrad.dtype import dtypes, DType, PtrDType, truncate -from tinygrad.helpers import prod, AMX - -def ldt(dt:DType): - if dt.vcount > 1: return f"<{dt.vcount} x {ldt(dt.scalar())}>" - if isinstance(dt, PtrDType): return ldt(dt.base) + "*" - return {dtypes.void: "void", dtypes.bool: "i1", dtypes.int8: "i8", dtypes.int16: "i16", dtypes.int32: "i32", dtypes.int64: "i64", - dtypes.uint8: "i8", dtypes.uint16: "i16", dtypes.uint32: "i32", dtypes.uint64: "i64", - dtypes.float16: "half", dtypes.bfloat16: "bfloat", dtypes.float32: "float", dtypes.float64: "double"}[dt] - -def lconst(x, dtype:DType): - if dtype in dtypes.floats: - if math.isinf(x) or math.isnan(x): return "0x%02X%02X%02X%02X%02X%02X%02X%02X" % tuple(struct.pack("d",x)[::-1]) - return truncate[dtype](x) - return int(x) - -def lcast(input_type:DType, output_type:DType): - if dtypes.is_float(input_type): - if dtypes.is_float(output_type): return 'fpext' if output_type.itemsize > input_type.itemsize else 'fptrunc' - if dtypes.is_int(output_type): return 'fptoui' if dtypes.is_unsigned(output_type) else 'fptosi' - if dtypes.is_unsigned(input_type) or dtypes.is_bool(input_type): - if dtypes.is_float(output_type): return 'uitofp' - if dtypes.is_int(output_type): return 'trunc' if output_type.itemsize < input_type.itemsize else 'zext' - if dtypes.is_int(input_type): - if dtypes.is_float(output_type): return 'sitofp' - if dtypes.is_int(output_type): return 'trunc' if output_type.itemsize < input_type.itemsize else 'sext' - raise NotImplementedError(f"cast from {input_type} -> {output_type} not implemented") - -# https://github.com/corsix/amx -def render_wmma_amx(ctx, wmma: UOp) -> str: - def AMX(op, gpr): return f'call void asm sideeffect ".word (0x201000+($0<<5)+0$1-((0$1>>4)*6))", "i,r,~{{memory}}"(i32 {op}, i64 {gpr}) #0; AMX' - - return "\n".join([ - *[f' store {ldt(src.dtype)} {ctx[src]}, {ldt(src.dtype.ptr())} {ctx[wmma]}_amx{i}, align {src.dtype.itemsize}' for i,src in enumerate(wmma.src)], - f' call void asm sideeffect "nop\\0Anop\\0Anop\\0A.word ({0x201000 + (17 << 5) + 0})", "~{{memory}}"() #0; AMX set', # set - *[f' {ctx[wmma]}_ld{i} = add i64 {ctx[wmma]}_ptr_amx2, {i*4<<56 | i*64}\n {AMX(4,f"{ctx[wmma]}_ld{i}")} ldz' for i in range(16)], # ldz - f' {AMX(0, f"{ctx[wmma]}_ptr_amx1")} ldx\n {AMX(1, f"{ctx[wmma]}_ptr_amx0")} ldy\n {AMX(12, 0)} fma32', # ldx ldy fma - *[f' {ctx[wmma]}_st{i} = add i64 {ctx[wmma]}_ptr_amx2, {i*4<<56 | i*64}\n {AMX(5,f"{ctx[wmma]}_st{i}")} stz' for i in range(16)], # stz - f' call void asm sideeffect "nop\\0Anop\\0Anop\\0A.word ({0x201000 + (17 << 5) + 1})", "~{{memory}}"() #0; AMX clr', # clr - f' {ctx[wmma]} = load {ldt(wmma.dtype)}, ptr {ctx[wmma]}_amx2, align {wmma.dtype.itemsize}']) - -def render_wmma_amd(ctx, wmma: UOp, arch: str) -> str: - dt_map = {dtypes.half: "f16", dtypes.float: "f32", dtypes.bfloat16: "bf16", dtypes.ushort: "bf16"} - # https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl - if arch.split(":")[0] == "gfx942": return f" {ctx[wmma]} = call {ldt(wmma.dtype)} @llvm.amdgcn.mfma.{dt_map[wmma.src[-1].dtype.scalar()]}" + \ - f".16x16x16{dt_map[wmma.src[0].dtype.scalar()]}(" + ", ".join([f"{ldt(w.dtype)} {ctx[w]}" for w in wmma.src]) + ", i32 0, i32 0, i32 0)" - # https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll - # example: %wmma0 = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16(<16 x half> %v99,<16 x half> %v100,<8 x float> %v101) - return f" {ctx[wmma]} = call {ldt(wmma.dtype)} @llvm.amdgcn.wmma.{dt_map[wmma.src[-1].dtype.scalar()]}.16x16x16." + \ - f"{dt_map[wmma.src[0].dtype.scalar()]}(" + ", ".join([f"{ldt(w.dtype)} {ctx[w]}" for w in wmma.src]) + (", i1 false)" \ - if wmma.dtype.scalar() != dtypes.float else ")") - -# llvm ops, lop[][] -unsigned_lop = { Ops.ADD: "add", Ops.MUL: "mul", Ops.IDIV: "udiv", Ops.MOD: "urem", - Ops.CMPLT: "icmp ult", Ops.CMPNE: "icmp ne", Ops.OR: "or", Ops.AND: "and", Ops.XOR: "xor", } -signed_lop = {**unsigned_lop, Ops.ADD: "add nsw", Ops.CMPLT: "icmp slt", Ops.IDIV: "sdiv", Ops.MOD: "srem"} -flags = " nsz arcp contract afn" -float_lop = {Ops.ADD: "fadd"+flags, Ops.MUL: "fmul"+flags, Ops.CMPLT: f"fcmp{flags} ult", Ops.CMPNE: f"fcmp{flags} une", Ops.FDIV: "fdiv"+flags} -lop = {**{x:unsigned_lop for x in (dtypes.bool,)+dtypes.uints}, **{x:signed_lop for x in dtypes.sints}, **{x:float_lop for x in dtypes.floats}} - -base_rewrite = PatternMatcher([ - # memory load/store - (UPat(Ops.INDEX, name="x"), lambda ctx,x: - f" {ctx[x]} = getelementptr inbounds {ldt(x.dtype.base)}, {ldt(x.src[0].dtype)} {ctx[x.src[0]]}, {ldt(x.src[1].dtype)} {ctx[x.src[1]]}"), - (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat(), UPat(), UPat.var("mask"))).or_casted("idx"), UPat.var("alt")), name="x"), - lambda ctx,x,idx,alt,mask: - f" br label {ctx[x]}_entry\n{ctx[x][1:]}_entry:\n" - f" br i1 {ctx[mask]}, label {ctx[x]}_load, label {ctx[x]}_exit\n{ctx[x][1:]}_load:\n" - f" {ctx[x]}_yes = load {ldt(x.dtype)}, {ldt(idx.dtype)} {ctx[idx]}\n" - f" br label {ctx[x]}_exit\n{ctx[x][1:]}_exit:\n" - f" {ctx[x]} = phi {ldt(x.dtype)} [{ctx[x]}_yes, {ctx[x]}_load], [{ctx[alt]}, {ctx[x]}_entry]"), - (UPat(Ops.LOAD, src=(UPat.var('idx'),), allow_any_len=True, name="x"), - lambda ctx,x,idx: f" {ctx[x]} = load {ldt(x.dtype)}, {ldt(idx.dtype)} {ctx[idx]}"), - (UPat(Ops.STORE, name="x"), lambda ctx,x: f" store {ldt(x.src[1].dtype)} {ctx[x.src[1]]}, {ldt(x.src[0].dtype)} {ctx[x.src[0]]}"), - - # GEP/VECTORIZE/CAST for float4 support - (UPat(Ops.GEP, name="x"), lambda ctx,x: f" {ctx[x]} = extractelement {ldt(x.src[0].dtype)} {ctx[x.src[0]]}, i32 {x.arg[0]}"), - (UPat(Ops.VECTORIZE, src=UPat.var('y'), name="x"), lambda ctx,x,y: - f" {ctx[x]}_z = insertelement <1 x {ldt(y.dtype)}> poison, {ldt(y.dtype)} {ctx[y]}, i32 0\n" - f" {ctx[x]} = shufflevector <1 x {ldt(y.dtype)}> {ctx[x]}_z, <1 x {ldt(y.dtype)}> poison, <{x.dtype.count} x i32> zeroinitializer"), - (UPat(Ops.VECTORIZE, name="x"), lambda ctx,x: "\n".join([(f" {ctx[x]}_{i}" if i+1 != len(x.src) else f" {ctx[x]}")+ - f" = insertelement {ldt(x.dtype)} "+(f"{ctx[x]}_{i-1}" if i != 0 else "poison")+ - f", {ldt(u.dtype)} {ctx[u]}, i32 {i}" for i,u in enumerate(x.src)])), - # unary/binary/ternary ops - (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f" {ctx[x]} = bitcast {ldt(x.src[0].dtype)} {ctx[x.src[0]]} to {ldt(x.dtype)}"), - (UPat(Ops.CAST, name="x"), lambda ctx,x: f" {ctx[x]} = {lcast(x.src[0].dtype, x.dtype)} {ldt(x.src[0].dtype)} {ctx[x.src[0]]} to {ldt(x.dtype)}"), - (UPat(GroupOp.Binary, name="x"), lambda ctx,x: - f" {ctx[x]} = {lop[x.src[0].dtype.scalar()][x.op]} {ldt(x.src[0].dtype)} {ctx[x.src[0]]}, {ctx[x.src[1]]}"), - (UPat(Ops.WHERE, name="x"), lambda ctx,x: - f" {ctx[x]} = select {ldt(x.src[0].dtype)} {ctx[x.src[0]]}, {ldt(x.src[1].dtype)} {ctx[x.src[1]]}, {ldt(x.src[2].dtype)} {ctx[x.src[2]]}"), - - # range - (UPat(Ops.RANGE, name="x"), lambda ctx,x: - f" br label %loop_entry_{x.arg}\nloop_entry_{x.arg}:\n" - f" br label %loop_body_{x.arg}\nloop_body_{x.arg}:\n" - f" {ctx[x]} = phi {ldt(x.dtype)} [ 0, %loop_entry_{x.arg} ], [ {ctx[x]}phi, %loop_latch_{x.arg} ]"), - (UPat(Ops.ENDRANGE, name="x"), lambda ctx,x: - f" br label %loop_latch_{x.src[0].arg}\nloop_latch_{x.src[0].arg}:\n" - f" {ctx[x.src[0]]}phi = add i32 {ctx[x.src[0]]}, 1\n {ctx[x]} = icmp ult i32 {ctx[x.src[0]]}phi, {ctx[x.src[0].src[0]]}\n" - f" br i1 {ctx[x]}, label %loop_body_{x.src[0].arg}, label %loop_exit_{x.src[0].arg}\nloop_exit_{x.src[0].arg}:"), - - # if - (UPat(Ops.IF, name="x"), lambda ctx,x: f" br i1 {ctx[x.src[0]]}, label %ifbody_{ctx[x][1:]}, label %ifskip_{ctx[x][1:]}\nifbody_{ctx[x][1:]}:"), - (UPat(Ops.ENDIF, name="x"), lambda ctx,x: f" br label %ifskip_{ctx[x.src[0]][1:]}\nifskip_{ctx[x.src[0]][1:]}:"), - - (UPat(Ops.BARRIER), lambda ctx: "") -]) - -class LLVMRenderer(Renderer): - device = "LLVM" - abi = 'win64cc' if sys.platform == 'win32' else None - supports_float4 = True - has_local = False - global_max: tuple[int, ...] | None = None - string_rewrite = base_rewrite + PatternMatcher([(UPat(Ops.WMMA, name="wmma"), render_wmma_amx)]) - if AMX: tensor_cores = ClangRenderer.amx_tc - - extra_matcher = PatternMatcher([ - # rewrite RECIP with FDIV - (UPat(Ops.RECIP, name="x"), lambda x: UOp(Ops.FDIV, x.dtype, (x.const_like(1), x.src[0]))), - # rewrite cast to bool to CMPNE 0 - (UPat(Ops.CAST, dtype=dtypes.bool, name="x"), lambda x: x.src[0] != x.src[0].const_like(0)), - # rewrite MAX to CMPLT + WHERE - (UPat(Ops.MAX, name="m"), lambda m: (m.src[0] < m.src[1]).where(m.src[1], m.src[0])), - # copied from cstyle.py, upcast to float32 all the ops that don't support bfloat16 - (UPat((Ops.SQRT, Ops.EXP2, Ops.LOG2, Ops.SIN), dtype=dtypes.bfloat16, name="x"), - lambda x: (UOp(x.op, dtypes.float, tuple(vv.cast(dtypes.float) for vv in x.src), x.arg).cast(dtypes.bfloat16))), - # copied from cstyle.py, add float intermediate casting - (UPat(Ops.CAST, name="x", src=UPat.var("y", dtypes.bfloat16)),lambda x,y: y.cast(dtypes.float).cast(x.dtype) if x.dtype!=dtypes.float else None), - (UPat(Ops.CAST, dtypes.bfloat16, UPat.var("x")),lambda x: x.cast(dtypes.float).cast(dtypes.bfloat16) if x.dtype!=dtypes.float else None), - ]) - - def render(self, uops: list[UOp]) -> str: return "\n".join((k:=self._render_kernel(uops))[0] + (k[1], self._render_footer(uops))) - def _render_footer(self, uops: list[UOp]) -> str: return 'attributes #0 = { alwaysinline nounwind "no-builtins" "no-trapping-math"="true" }' - def _render_fn(self, name:str, args:list[tuple[str,DType]], kernel:list[str], prefix:list[str]|None=None) -> str: - # NOTE: MallocAllocator promises 0x20 alignment - sargs = ", ".join([f"{ldt(dt)}{' noalias align 32' if isinstance(dt, PtrDType) else ''} {name}" for name,dt in args]) - sprefix = "".join([f" {x}" for x in (prefix or []) + [self.abi] if x is not None]) - return "\n".join([f"define{sprefix} void @{name}({sargs}) #0", "{"] + kernel + [" ret void\n}"]) - def _render_kernel(self, uops: list[UOp], prefix:list[str]|None=None) -> tuple[tuple[str, ...], str]: - r: dict[UOp, str] = {} - args: list[tuple[str, DType]] = [] - kernel: list[str] = [] - vc = -1 - - local_args: list[str] = [] - acc_to_assign: dict[UOp, UOp] = {} - for u in uops: - if u.op is Ops.ASSIGN: # prealloc all assigns - vc += 1 - r[u] = r[u.src[1]] = f"%assign{vc}" - assert u.src[0] not in acc_to_assign, "can't assign to DEFINE_ACC twice" - acc_to_assign[u.src[0]] = u.src[1] - if AMX and u.op is Ops.WMMA: # prealloc aux buffers as AMX can only load from memory - vc += 1 - r[u] = f"%wmma{vc}" - for i, dtype in enumerate(u.arg[2].vec(sz) for sz in [prod(size for _, size in upcast) for upcast in u.arg[6]]): - kernel += [f" {r[u]}_amx{i} = alloca {ldt(dtype)}, align {dtype.itemsize}", - f" {r[u]}_ptr_amx{i} = ptrtoint {ldt(dtype.ptr())} {r[u]}_amx{i} to i64"] - - name = "test" - for u in uops: - if u.op is Ops.SINK: - if u.arg is not None: name = u.arg.name - continue - if u.op in (Ops.DEFINE_GLOBAL, Ops.DEFINE_VAR): - r[u] = f"%data{u.arg}" if u.op is Ops.DEFINE_GLOBAL else f"%{u.arg[0]}" - args.append((r[u], u.dtype)) - elif u.op == Ops.DEFINE_LOCAL: - r[u] = f"%local_{u.arg}" - assert isinstance(u.dtype, PtrDType) - if self.device == "LLVM": kernel.append(f" {r[u]} = alloca [{u.dtype.size} x {ldt(u.dtype)}], align 16") - else: - local_args.append(f"@{r[u][1:]} = internal unnamed_addr addrspace(3) global [{u.dtype.size} x {ldt(u.dtype)}] undef, align 16") - kernel.append(f" {r[u]} = addrspacecast [{u.dtype.size} x {ldt(u.dtype)}] addrspace(3)* @{r[u][1:]} to [{u.dtype.size} x {ldt(u.dtype)}]*") - elif u.op is Ops.ASSIGN: pass # assign is already handled by the first pass - elif u.op is Ops.DEFINE_ACC: r[u] = r[u.src[0]] # a define acc can be used and never be assigned to - elif u.op is Ops.CONST: r[u] = lconst(u.arg, u.dtype) - elif u.op is Ops.CAST and (ldt(u.dtype) == ldt(u.src[0].dtype) or isinstance(u.dtype, PtrDType)): - r[u] = r[u.src[0]] # cast from signed to unsigned of the same size is a noop, or pointer cast - else: - # if it's an assign target, it's already preallocated - if u not in r: - vc += 1 - r[u] = f"%v{vc}" - - # do the rendering of the llvm ir code - if (l:=self.string_rewrite.rewrite(u, ctx=r)) is None: - raise RuntimeError(f"failed to render {u.op} with {u.dtype} srcs {[x.dtype for x in u.src]}") - kernel.append(cast(str, l)) - - # generate the phi nodes for the assigns - if u.op is Ops.RANGE: - for x in acc_to_assign: - if u in x.src: # if this range is relevant for this acc - vc += 1 - kernel.append(f" %acc{vc} = phi {ldt(x.dtype)} [ {r[x]}, %loop_entry_{u.arg} ], [ {r[acc_to_assign[x]]}, %loop_latch_{u.arg} ]") - r[x] = f"%acc{vc}" - return tuple(local_args), self._render_fn(name, args, kernel, prefix) - -barrier = 'fence syncscope("workgroup") release\ntail call void @llvm.amdgcn.s.barrier()\nfence syncscope("workgroup") acquire\n' -code_for_workitem = {"g": lambda x: f"tail call i32 @llvm.amdgcn.workgroup.id.{chr(120+int(x))}()", - "l": lambda x: f"tail call i32 @llvm.amdgcn.workitem.id.{chr(120+int(x))}()"} -class AMDLLVMRenderer(LLVMRenderer): - device = "AMD" - has_local = True - shared_max = AMDRenderer.shared_max - global_max = AMDRenderer.global_max - abi = "amdgpu_kernel" - string_rewrite = PatternMatcher([ - (UPat(Ops.SPECIAL, name="x"), lambda ctx, x: f" {ctx[x]} = " + f"{ code_for_workitem[x.arg[0][0]](x.arg[0][-1])}; "), - (UPat(Ops.BARRIER), lambda ctx: barrier), - (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(16), src=UPat.var("y", dtypes.half.vec(8))), lambda ctx, x, y: f" {ctx[x]} = shufflevector "\ - f"<8 x half> {ctx[y]}, <8 x half> zeroinitializer, <16 x i32> <{', '.join([f'i32 {i}, i32 {j}' for i, j in zip(range(0, 8), range(8, 16))])}>"), - (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(8), src=UPat.var("y", dtypes.half.vec(16))), lambda ctx, x, y: - f" {ctx[x]}= shufflevector <16 x half> {ctx[y]}, <16 x half> undef, <8 x i32> <{', '.join([f'i32 {x}' for x in range(0, 16, 2)])}>"), - ]) + base_rewrite - extra_matcher = LLVMRenderer.extra_matcher - def _render_footer(self, uops: list[UOp]) -> str: - # TODO: this is copied from cstyle - requiredMaxThreadsPerBlock = prod(u.arg[1] for u in uops if u.op is Ops.SPECIAL and u.arg[0][0] == "l") - attributes = ["alwaysinline", "nounwind", '"no-builtins"', - f'"amdgpu-flat-work-group-size"="1,{requiredMaxThreadsPerBlock}"', '"no-trapping-math"="true"'] - return 'attributes #0 = { ' + ' '.join(attributes) + ' }' - def __init__(self, arch:str): - self.arch = arch - self.tensor_cores = AMDRenderer.get_tensor_cores(arch) - self.string_rewrite += PatternMatcher([(UPat(Ops.WMMA, name="wmma"), lambda ctx, wmma, arch=arch: render_wmma_amd(ctx, wmma, arch))]) - if self.arch.split(":")[0] == "gfx1100": - self.extra_matcher += PatternMatcher([ - (UPat(Ops.WMMA, name="x", dtype=dtypes.half.vec(8)), - lambda x: UOp(Ops.WMMA, dtypes.half.vec(16), (x.src[0], x.src[1], x.src[2].cast(dtypes.half.vec(16))), (*x.arg,)).cast(dtypes.half.vec(8))), - (UPat(Ops.WMMA, name="x"), lambda x: UOp(Ops.WMMA, x.dtype, (x.src[0].bitcast(dtypes.uint16.vec(16)), x.src[1].bitcast(dtypes.uint16.vec(16)), - x.src[2]), x.arg) if x.src[0].dtype == dtypes.bfloat16.vec(16) else None), - ]) - if self.arch.split(":")[0] == "gfx1201": - self.extra_matcher += PatternMatcher([ - (UPat(Ops.WMMA, name="x", dtype=dtypes.bfloat16.vec(8)), lambda x: UOp(Ops.WMMA, dtypes.uint16.vec(8), - (x.src[0].bitcast(dtypes.uint16.vec(8)), x.src[1].bitcast(dtypes.uint16.vec(8)), x.src[2].bitcast(dtypes.uint16.vec(8))), (*x.arg,)) - .bitcast(dtypes.bfloat16.vec(8)) if x.src[0].dtype == dtypes.bfloat16.vec(8) else None), - (UPat(Ops.WMMA, name="x", dtype=dtypes.float.vec(8)), - lambda x: UOp(Ops.WMMA, dtypes.float.vec(8), (x.src[0].bitcast(dtypes.uint16.vec(8)), x.src[1].bitcast(dtypes.uint16.vec(8)), - x.src[2]), (*x.arg,)) if x.src[0].dtype == dtypes.bfloat16.vec(8) else None) - ]) - def __reduce__(self): return self.__class__, (self.arch,) diff --git a/tinygrad/tinygrad/renderer/ptx.py b/tinygrad/tinygrad/renderer/ptx.py deleted file mode 100644 index 76e878ee..00000000 --- a/tinygrad/tinygrad/renderer/ptx.py +++ /dev/null @@ -1,214 +0,0 @@ -from typing import cast, Callable -import struct -from collections import defaultdict -from tinygrad.uop.ops import Ops, UOp, PatternMatcher, UPat, GroupOp -from tinygrad.dtype import dtypes, DType, PtrDType -from tinygrad.renderer import Renderer -from tinygrad.renderer.cstyle import CUDARenderer -from tinygrad.helpers import flatten, get_single_element - -def render_val(x, dtype): - if dtypes.is_float(dtype): - if dtype == dtypes.double: return "0d%02X%02X%02X%02X%02X%02X%02X%02X" % tuple(struct.pack("d",x)[::-1]) - if dtype == dtypes.half: return "0x%02X%02X" % tuple(struct.pack("e",x)[::-1]) - return "0f%02X%02X%02X%02X" % tuple(struct.pack("f",x)[::-1]) - return str(int(x)) + ("U" if dtypes.is_unsigned(dtype) else "") - -asm_for_op: dict[Ops, Callable] = { - Ops.RECIP: lambda d,a,dt,name: f"rcp{'.approx' if dtypes.is_float(dt) else ''}.{name} {d}, {a};", - Ops.EXP2: lambda d,a,dt,name: f"ex2.approx.{name} {d}, {a};", Ops.LOG2: lambda d,a,dt,name: f"lg2.approx.{name} {d}, {a};", - Ops.SIN: lambda d,a,dt,name: f"sin.approx.{name} {d}, {a};", Ops.SQRT: lambda d,a,dt,name: f"sqrt.approx.{name} {d}, {a};", - Ops.SHR: lambda d,a,b,dt,name: f"shr.{name} {d}, {a}, {b};", Ops.SHL: lambda d,a,b,dt,name: f"shl.b{name[1:]} {d}, {a}, {b};", - Ops.ADD: lambda d,a,b,dt,name: f"{'or' if dt == dtypes.bool else 'add'}.{name} {d}, {a}, {b};", - Ops.MUL: lambda d,a,b,dt,name: f"{'and' if dt == dtypes.bool else 'mul'}{'.lo' if dtypes.is_int(dt) else ''}.{name} {d}, {a}, {b};", - Ops.XOR: lambda d,a,b,dt,name: f"xor.pred {d}, {a}, {b};" if dt == dtypes.bool else f"xor.b{name[1:]} {d}, {a}, {b};", - Ops.AND: lambda d,a,b,dt, name: f"and.pred {d}, {a}, {b};" if dt == dtypes.bool else f"and.b{name[1:]} {d}, {a}, {b};", - Ops.OR: lambda d,a,b,dt, name: f"or.pred {d}, {a}, {b};" if dt == dtypes.bool else f"or.b{name[1:]} {d}, {a}, {b};", - Ops.IDIV: lambda d,a,b,dt,name: f"div.{name} {d}, {a}, {b};", Ops.MOD: lambda d,a,b,dt,name: f"rem.{name} {d}, {a}, {b};", - Ops.MAX: lambda d,a,b,dt,name: f"max.{name} {d}, {a}, {b};", - Ops.CMPLT: lambda d,a,b,dt,name: f"setp.lt.{name} {d}, {a}, {b};", Ops.CMPNE: lambda d,a,b,dt,name: f"setp.ne.{name} {d}, {a}, {b};", - Ops.MULACC: lambda d,a,b,c,dt,name: f"{'fma.rn' if dtypes.is_float(dt) else 'mad.lo'}.{name} {d}, {a}, {b}, {c};", - Ops.WHERE: lambda d,a,b,c,dt,name: [f"@{a} mov.{name} {d}, {b};", f"@!{a} mov.{name} {d}, {c};"] if dt == dtypes.bool else \ - f"selp.{'b16' if name == 'f16' else name} {d}, {b}, {c}, {a};" -} - -supports_half = (Ops.EXP2, Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPLT, Ops.WHERE) -doesnt_support_half: tuple[Ops, ...] = tuple(op for op in asm_for_op.keys() if op not in supports_half) -ptx_matcher = PatternMatcher([ - # bool CMPNE is XOR, bool CMPLT is XOR+AND (universal makes this slow, this is for renderer only) - (UPat.var('x', dtype=dtypes.bool).ne(UPat.var('y')), lambda x,y: x^y), - (UPat.var('x', dtype=dtypes.bool) uint8 - (UPat(Ops.LOAD, dtypes.bool, src=(UPat(dtype=dtypes.int64),), name="x", allow_any_len=True), - lambda x: UOp(x.op, dtypes.uint8, x.src[0:1] + ((x.src[1].cast(dtypes.uint8),) if len(x.src) >= 2 else ()) + x.src[2:]).cast(dtypes.bool)), - (UPat(Ops.STORE, src=(UPat(dtype=dtypes.int64), UPat(dtype=dtypes.bool)), name="x", allow_any_len=True), - lambda x: UOp(x.op, dtypes.void, x.src[0:1] + (x.src[1].cast(dtypes.uint8),) + x.src[2:])), - # load/store use pointer arithmetic, and the cast does nothing - (UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("idx"))), lambda buf,idx: buf.cast(dtypes.int64) + idx.cast(dtypes.int64)*buf.dtype.itemsize), - (UPat(Ops.CAST, name="x"), lambda x: x.src[0] if isinstance(x.dtype, PtrDType) or x.src[0].dtype == dtypes.void else None), - # move mask from INDEX to the load/store to enable pointer arithmetic - (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("idx"), UPat.var("gate"))), UPat.var("alt"))), - lambda buf,idx,gate,alt: UOp(Ops.LOAD, alt.dtype, (buf.index(idx), alt, gate))), - (UPat(Ops.STORE, src=(UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("idx"), UPat())), UPat.var("val"), UPat.var("gate"))), - lambda buf,idx,val,gate: UOp.store(buf.index(idx), val, gate)), - # ptx shr and shl instructions require y to be uint - (UPat.var("x") << UPat.var("y"), lambda x,y: UOp(Ops.SHL, x.dtype, (x,y.cast(dtypes.uint))) if y.dtype != dtypes.uint else None), - (UPat.var("x") >> UPat.var("y"), lambda x,y: UOp(Ops.SHR, x.dtype, (x,y.cast(dtypes.uint))) if y.dtype != dtypes.uint else None), -]) - -def mem_type(x: UOp): return 'shared' if any(_x.op is Ops.DEFINE_LOCAL for _x in x.src[0].toposort()) else 'global' - -def render_wmma(ctx: "PTXRenderer", wmma: UOp): - assert ctx.wmma_r, "registry values for wmma must be populated" - (N, M, K), dtype_in, dtype_out = wmma.arg[1], wmma.arg[2], wmma.arg[3] - - for src, regs in zip(wmma.src, ctx.wmma_r): - for i, reg in enumerate(regs): # pack input and acc registers - if (elems_per_reg := 4 // src.dtype.scalar().itemsize) == 1: yield f"mov.b32 {reg}, {ctx.r[src][i]};" - else: yield f"mov.b32 {reg}, {{{', '.join(ctx.r[src][i * elems_per_reg : (i+1) * elems_per_reg])}}};" - - dt_map_in, dt_map_out = {dtypes.float: "tf32", dtypes.half: "f16"}, {dtypes.float: "f32", dtypes.half: "f16"} - yield f'mma.sync.aligned.m{M}n{N}k{K}.row.col.{dt_map_out[dtype_out]}.{dt_map_in[dtype_in]}.{dt_map_in[dtype_in]}.{dt_map_out[dtype_out]}{" "*12}'+\ - f'{{{", ".join(ctx.wmma_r[2])}}}, {{{", ".join(ctx.wmma_r[0])}}}, {{{", ".join(ctx.wmma_r[1])}}}, {{{", ".join(ctx.wmma_r[2])}}};' - - for i, reg in enumerate(ctx.wmma_r[2]): # unpack acc registers - if (elems_per_reg := 4 // dtype_out.itemsize) == 1: yield f"mov.b32 {ctx.r[wmma][i]}, {reg};" - else: yield f"mov.b32 {{{', '.join(ctx.r[wmma][i * elems_per_reg : (i+1) * elems_per_reg])}}}, {reg};" - -def modifier(a: DType, b: DType): return '.rzi' if dtypes.is_int(a) and dtypes.is_float(b) else '.rn' if dtypes.is_float(a) and \ - (a.itemsize < b.itemsize or dtypes.is_int(b) or b == dtypes.bool) else '' - -string_rewrite = PatternMatcher([ - (UPat.cvar("x", dtypes.bool), lambda ctx, x: f"setp.ne.s16 {ctx.r[x]}, {render_val(x.arg, x.dtype)}, 0;"), - (UPat.cvar("x"), lambda ctx, x: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {render_val(x.arg, x.dtype)};"), - (UPat(Ops.STORE, name="x", src=(UPat.var('bidx'), UPat.var("var")), allow_any_len=True), lambda ctx, x, bidx, var: f"st.{mem_type(bidx)}" + \ - f"{f'.v{cnt}' if ((cnt:=var.dtype.count)>1) else ''}.{ctx.mem_types[var.dtype.scalar()]} " + \ - f"[{ctx.r[bidx]}+0], {('{' + ', '.join(ctx.r[var]) + '}') if var.dtype.count > 1 else ctx.r[var]};"), - (UPat(Ops.SPECIAL, name="x"), lambda ctx,x: f"mov.u32 %{x.arg[0]}, %{'ctaid' if x.arg[0][0] == 'g' else 'tid'}.{chr(120+int(x.arg[0][-1]))};"), - (UPat(Ops.DEFINE_GLOBAL, name="x"), lambda ctx, x: f"ld.param.{ctx.types[dtypes.ulong]} {ctx.r[x]}, [data{x.arg}+0];"), - (UPat((Ops.CMPLT, Ops.CMPNE), name="x", allow_any_len=True, src=(UPat.var("src0"),)), - lambda ctx, x, src0: ctx.code_for_op[x.op](ctx.r[x], *[ctx.r[v] for v in x.src], src0.dtype, ctx.types[src0.dtype])), - (UPat(GroupOp.ALU, name="x"), lambda ctx, x: ctx.code_for_op[x.op](ctx.r[x], *[ctx.r[v] for v in x.src], x.dtype, ctx.types[x.dtype])), - (UPat(Ops.BITCAST, name="x", src=(UPat.var("a"),), allow_any_len=True), lambda ctx, x, a: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {ctx.r[a]};"), - (UPat(Ops.CAST, name="x", src=(UPat(dtype=dtypes.bool, name="a"),)), - lambda ctx, x, a: f"selp.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {render_val(1, x.dtype)}, {render_val(0, x.dtype)}, {ctx.r[a]};"), - (UPat(Ops.CAST, name="x", dtype=dtypes.bool, src=(UPat.var("a"),)), - lambda ctx, x, a: f"setp.ne.b{ctx.types[a.dtype][1:]} {ctx.r[x]}, {ctx.r[a]}, {render_val(0, a.dtype)};"), - (UPat(Ops.CAST, name="x", src=(UPat.var("a"),)), - lambda ctx, x, a: f"cvt{modifier(x.dtype, a.dtype)}.{ctx.types[x.dtype]}.{ctx.types[a.dtype]} {ctx.r[x]}, {ctx.r[a]};"), - (UPat(Ops.LOAD, name="x", src=(UPat.var('loc'), UPat(name='alt'), UPat(name="gate", op=GroupOp.ALU))), lambda ctx, x, loc, alt, gate: flatten([ - [f"mov.{ctx.mem_types[x.dtype.scalar()]} {v}, {render_val(0, x.dtype.scalar())};" for v in ctx.r[x]], - [f"@{ctx.r[gate]} ld.{mem_type(x)}.v{x.dtype.count}.{ctx.mem_types[x.dtype.scalar()]} {{{', '.join(ctx.r[x])}}}, [{ctx.r[loc]}+0];"] - ]) if alt.dtype.count > 1 else [ - f"@{ctx.r[gate]} ld.{mem_type(x)}.{ctx.mem_types[x.dtype.scalar()]} {ctx.r[x]}, [{ctx.r[loc]}+0];", - f"@!{ctx.r[gate]} mov.b{ctx.types[x.dtype.scalar()][1:]} {ctx.r[x]}, {ctx.r[alt]};"]), - (UPat(Ops.LOAD, name="x", src=(UPat.var('loc'),), allow_any_len=True), - lambda ctx, x, loc: f"ld.{mem_type(x)}.v{x.dtype.count}.{ctx.mem_types[x.dtype.scalar()]} {{{', '.join(ctx.r[x])}}}, [{ctx.r[loc]}+0];" \ - if x.dtype.count > 1 else f"ld.{mem_type(x)}.{ctx.mem_types[x.dtype]} {ctx.r[x]}, [{ctx.r[loc]}+0];"), - (UPat(Ops.DEFINE_ACC, name="x", src=(UPat.cvar("pred", dtype=dtypes.bool),), allow_any_len=True), lambda ctx, x, pred: [ - f"setp.ne.s16 {ctx.r[pred]}, {render_val(pred.arg, pred.dtype)}, 0;", f"mov.pred {ctx.r[x]}, {ctx.r[pred]};"]), - (UPat(Ops.DEFINE_ACC, name="x", src=(UPat.cvar("pred"),), allow_any_len=True), - lambda ctx, x, pred: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {render_val(pred.arg, x.dtype)};"), - (UPat(Ops.RANGE, name="x"), lambda ctx, x: [f"mov.u32 {ctx.r[x]}, 0;", "LOOP_" + f"{ctx.r[x][1:]}:"]), - (UPat(Ops.ASSIGN, name="x", dtype=dtypes.bool), lambda ctx, x: [f"mov.pred {ctx.r[x.src[0]]}, {ctx.r[x.src[1]]};"]), - (UPat(Ops.ASSIGN, name="x"), lambda ctx, x: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x.src[0]]}, {ctx.r[x.src[1]]};"), - (UPat(Ops.ENDRANGE, name="x", src=(UPat.var("src0"),)), lambda ctx, x, src0: [ - ctx.code_for_op[Ops.ADD](ctx.r[src0], ctx.r[src0], "1", dtypes.int, ctx.types[dtypes.int]), - ctx.code_for_op[Ops.CMPLT](ctx.r[x], ctx.r[x.src[0]], ctx.r[src0.src[0]], dtypes.int, ctx.types[dtypes.int]), - f"@{ctx.r[x]} bra LOOP_{ctx.r[src0][1:]};"]), - (UPat(Ops.DEFINE_LOCAL, name="x"), - lambda ctx, x: [f".shared .align 16 .b8 {x.arg}[{x.dtype.size*x.dtype.itemsize}];", f"mov.u64 {ctx.r[x]}, {x.arg}[0];"]), - (UPat(Ops.IF, name="x"), lambda ctx, x: f"@!{ctx.r[x.src[0]]} bra IF_{ctx.r[x.src[0]][1:]}_{ctx.uops.index(x)};"), - (UPat(Ops.ENDIF, name="x"), lambda ctx, x: f"IF_{ctx.r[x.src[0].src[0]][1:]}_{ctx.uops.index(x.src[0])}:"), - (UPat(Ops.WMMA, name="x"), lambda ctx, x: list(render_wmma(ctx, x))), - (UPat(Ops.BARRIER, name="x"), lambda ctx, x: ctx.barrier), - (UPat(Ops.DEFINE_VAR, name="x"), lambda ctx, x: f"ld.param.{ctx.mem_types[x.dtype]} {ctx.r[x]}, [{x.arg[0]}+0];"), -]) - -class PTXRenderer(Renderer): - device = "CUDA" - suffix = "PTX" - global_max, local_max, shared_max = CUDARenderer.global_max, CUDARenderer.local_max, CUDARenderer.shared_max - tc_sm80 = [tc for tc in CUDARenderer.tc_sm80 if tc.dtype_in in [dtypes.half, dtypes.float]] - code_for_op = asm_for_op - extra_matcher = ptx_matcher - def __init__(self, arch:str, device="CUDA"): - self.device, self.arch = device, arch - self.tensor_cores = PTXRenderer.tc_sm80 if int(arch[3:]) >= 80 else CUDARenderer.tc_sm75 if int(arch[3:]) >= 75 else [] - def __reduce__(self): return self.__class__, (self.arch, self.device) - - # language options - kernel_prefix = """.version VERSION -.target TARGET -.address_size 64 -.visible .entry""" - barrier = "bar.sync\t0;" - # HACK: Use s16 and u16 for int8 and uint8 buffers. This can be wrong in cast. - types: dict[DType, str] = { dtypes.int8: "s16", dtypes.int16: "s16", dtypes.int32: "s32", dtypes.int64: "s64", - dtypes.uint8: "u16", dtypes.uint16: "u16", dtypes.uint32: "u32", dtypes.uint64: "u64", - dtypes.float16: "f16", dtypes.float32: "f32", dtypes.float64: "f64", dtypes.bool: "pred" } - - mem_types: dict[DType, str] = {**types, dtypes.int8: "s8", dtypes.uint8: "u8", dtypes.bool: "u8", dtypes.float16: "b16"} - - def render_kernel(self, kernel, function_name, bufs, regs) -> str: - def fmt(line): return line if line[0]=="$" else "\t" + line.replace(" ", "\t" if len(line.split(" ")[0]) > 7 else "\t\t", 1) - kernel = '\n'.join(map(fmt, [f".reg .{reg.split('_')[-2]} %{reg}<{cnt}>;" for reg,cnt in regs] + kernel + ["ret;"])) - params = ',\n\t'.join([f".param .{'u64' if dtype.__class__ == PtrDType else self.types[dtype]} {name}" for name,dtype in bufs]) - return f"{self.kernel_prefix} {function_name}(\n\t{params}\n)\n{{\n{kernel}\n}}" - - def render(self, uops:list[UOp]) -> str: - kernel:list[str] = [] - bufs = [] - - c: defaultdict[str, int] = defaultdict(int) - r: dict[UOp, list[str]|str] = {} - self.r = r - self.uops = uops - - def ssa(prefix:str, u:UOp|None=None, dtype:str|None=None) -> str: - nonlocal c, r - prefix += f"_{dtype if dtype is not None else self.types[cast(UOp, u).dtype]}_" - c[prefix] += 1 - return f"%{prefix}{c[prefix]-1}" - - name = "test" - for u in uops: - if u.op is Ops.SINK: - if u.arg is not None: name = u.arg.name - continue - if u.op is Ops.VECTORIZE: - r[u] = [cast(str,r[x]) for x in u.src] - continue - if u.op is Ops.GEP: - r[u] = r[u.src[0]][get_single_element(u.arg)] - continue - if u.op in {Ops.CAST, Ops.BITCAST} and (u.src[0].dtype == u.dtype or isinstance(u.src[0].dtype, PtrDType)): - r[u] = r[u.src[0]] - continue - if u.op is Ops.SPECIAL: r[u] = "%" + u.arg[0] - elif u.op is Ops.DEFINE_VAR: bufs.append((u.arg[0], u.dtype)) - elif u.op is Ops.LOAD: - assert u.src[0].dtype == dtypes.int64, "load isn't int64" - r[u] = [ssa('val', dtype=self.types[u.dtype.scalar()]) for _ in range(u.dtype.count)] if u.dtype.count > 1 else ssa('val', u) - elif u.op is Ops.DEFINE_GLOBAL: bufs.append((f"data{u.arg}", u.dtype)) - elif u.op is Ops.WMMA: - # registers for packing/unpacking input and acc - self.wmma_r = [[ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[0]]), 4 // u.arg[2].itemsize)], - [ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[1]]), 4 // u.arg[2].itemsize)], - [ssa("wmma_acc", dtype="b32") for _ in range(0, len(r[u.src[2]]), 4 // u.arg[3].itemsize)]] - r[u] = [ssa("wmma", dtype=self.types[u.dtype.scalar()]) for _ in range(u.dtype.count)] - prefix, dtype = {Ops.CAST: ("cast", None), Ops.BITCAST: ("cast", None), Ops.ENDRANGE: ("pred", "pred"), Ops.RANGE: ("ridx", None), - Ops.DEFINE_ACC: ("acc", None), Ops.DEFINE_VAR: ("dat", None), Ops.CONST: ("const", None), Ops.DEFINE_LOCAL:("local",self.types[dtypes.ulong]), - Ops.DEFINE_GLOBAL: ("dat", self.types[dtypes.ulong]), **{op: ("alu", None) for op in GroupOp.ALU}}.get(u.op, (None, None)) - if prefix: r[u] = ssa(prefix, u, dtype) - - if (l:=cast(str|list[str], string_rewrite.rewrite(u, ctx=self))) is None: - raise RuntimeError(f"failed to render {u.op} with {u.dtype} srcs {[x.dtype for x in u.src]}") - kernel.extend([l] if isinstance(l, str) else l) - - if u.op is Ops.ASSIGN: r[u] = r[u.src[0]] - elif u.op is Ops.SPECIAL: kernel = [f".reg .u32 %{u.arg[0]};"] + kernel - return self.render_kernel(kernel, name, bufs, c.items()) diff --git a/tinygrad/tinygrad/renderer/wgsl.py b/tinygrad/tinygrad/renderer/wgsl.py deleted file mode 100644 index 1d3147d0..00000000 --- a/tinygrad/tinygrad/renderer/wgsl.py +++ /dev/null @@ -1,92 +0,0 @@ -from tinygrad.dtype import DType, PtrDType, dtypes -from tinygrad.uop.ops import UOp, Ops, PatternMatcher, UPat -from tinygrad.renderer.cstyle import CStyleLanguage, base_rewrite, extra_pm -from tinygrad.helpers import strip_parens - -def sign_extend(val:UOp, sext_am:int): - return (UOp.where((val >> (sext_am - 1)) > 0, UOp.const(dtypes.uint32, 0xffffffff) << sext_am, UOp.const(dtypes.uint32, 0)) \ - | val.bitcast(dtypes.uint32)).bitcast(dtypes.int) - -# store for char: buf[idx/4] <- (var << (idx%4)*8)) -def packed_store(bidx:UOp, var:UOp): - shift_am = (bidx.src[1].cast(dtypes.uint32)%UOp.const(dtypes.uint32, 4//var.dtype.itemsize))*UOp.const(dtypes.uint32, 8*var.dtype.itemsize) - new_v = (var & (0xFF if var.dtype.itemsize == 1 else 0xFFFF)).cast(dtypes.uint32) << shift_am - mask = (((0xFF if var.dtype.itemsize == 1 else 0xFFFF) << shift_am) ^ 0xFFFFFFFF).cast(dtypes.uint32) - buf = UOp.load(UOp(Ops.INDEX, bidx.dtype, (bidx.src[0], bidx.src[1]//(4//var.dtype.itemsize))), dtype=dtypes.uint32) - return UOp.store(UOp(Ops.INDEX, bidx.dtype, (bidx.src[0], bidx.src[1]//(4//var.dtype.itemsize))), ((buf & mask) | new_v.cast(dtypes.uint32))) - -# load for char: sign_extend(buf[idx/4] >> ((idx%4)*8)) -def packed_load(root:UOp, bidx:UOp, dtype:DType, var:UOp|None=None): - div_idx = bidx.src[1]//(4//dtype.itemsize) - shift_am = (bidx.src[1].cast(dtypes.uint32)%UOp.const(dtypes.uint32, 4//dtype.itemsize))*UOp.const(dtypes.uint32, 8*dtype.itemsize) - if var is not None: load = UOp.load(UOp(Ops.INDEX, bidx.dtype, (bidx.src[0], div_idx, bidx.src[2])), var, dtype=dtypes.uint32, arg=root.arg) - else: load = UOp.load(UOp(Ops.INDEX, bidx.dtype, (bidx.src[0], div_idx)), *root.src[1:], dtype=dtypes.uint32, arg=root.arg) - val = (load.cast(dtypes.uint32) >> shift_am) & (0xFF if dtype.itemsize == 1 else 0xFFFF) - return sign_extend(val, 8*dtype.itemsize).cast(dtype) if dtype in [dtypes.char, dtypes.short] else val.cast(dtype) - -def is_packed(dt:DType) -> bool: return dt.itemsize < 4 and dt.base != dtypes.half - -wgsl_matcher = PatternMatcher([ - (UPat((Ops.CMPLT, Ops.XOR), src=(UPat(name="a", dtype=dtypes.bool), UPat.var("b")), name="c"), - lambda a,b,c: a.cast(dtypes.int).alu(c.op, b.cast(dtypes.int)).cast(dtypes.bool)), - (UPat.load(UPat.var("b"), UPat.cvar("c"), name="l"),lambda l,b,c: packed_load(l,b,l.dtype,c.cast(dtypes.uint32)) if is_packed(l.dtype) else None), - (UPat.load(UPat.var("b"), name='l', allow_any_len=True), lambda l,b: packed_load(l, b, l.dtype) if is_packed(l.dtype) else None), - (UPat.store(UPat.var("bidx"), UPat.var("var"), allow_any_len=True), lambda bidx,var: packed_store(bidx,var) if is_packed(var.dtype) else None), - (UPat.var("a") << UPat.var("b"),lambda a,b:(a.bitcast(dtypes.uint32)<({x.arg})" if x.arg < 0 else f"{x.arg&0xFFFFFFFF}u"), - (UPat(Ops.DEFINE_LOCAL, name="x"), lambda ctx,x: - f"var {ctx[x]}: array<{ctx.buf_map(x.dtype.base)},{x.dtype.size//(4//x.dtype.itemsize) if is_packed(x.dtype) else x.dtype.size}>;"), - (UPat(Ops.BITCAST, dtype=dtypes.half, name="x", src=(UPat(dtype=(dtypes.short, dtypes.ushort, dtypes.uint32),),)), - lambda ctx,x: f"bitcast>({ctx[x.src[0]]})[0]"), - (UPat(Ops.BITCAST, dtype=(dtypes.char, dtypes.uchar), name="x"), lambda ctx,x: f"bitcast<{ctx.type_map[x.dtype]}>({ctx[x.src[0]]}&0xFF)"), - (UPat(Ops.BITCAST, dtype=(dtypes.short, dtypes.ushort), name="x"),lambda ctx,x:f"bitcast<{ctx.type_map[x.dtype]}>(vec2({ctx[x.src[0]]},0))" \ - if x.src[0].dtype == dtypes.half else f"bitcast<{ctx.type_map[x.dtype]}>({ctx[x.src[0]]}&0xFFFF)"), - (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f"bitcast<{ctx.type_map[x.dtype]}>({ctx[x.src[0]]})"), - (UPat.load(UPat.var("b"), UPat.cvar("v")),lambda ctx,b,v: f"select({ctx[v]}, {ctx.render_load(ctx[b],b.src[0].dtype)}, {ctx[b.src[2]]})"), - (UPat.load(UPat.var("b"), allow_any_len=True), lambda ctx, b: ctx.render_load(ctx[b], b.dtype)), - (UPat.store(UPat.var("b"), UPat.var("v"), allow_any_len=True),lambda ctx,b,v:\ - # (load & mask) | var -> mask = v.src[0].src[1], var = v.src[1] - f"atomicAnd(&{ctx[b]},{ctx[v.src[0].src[1]]});\n atomicAdd(&{ctx[b]},{ctx[v.src[1]]});" if is_packed(b.src[0].dtype) \ - else f"{ctx[b]} = {ctx[v]};"), - (UPat(Ops.INDEX, src=(UPat.var("b"), UPat.var("idx")), allow_any_len=True), - lambda ctx,b,idx: f"{ctx[b]}[{strip_parens(ctx[idx]) if idx.arg is Ops.ADD else ctx[idx]}]"), - # fix nan check: 'a != a -> is_nan()' - (UPat.var("a") != UPat.var("a"), lambda ctx,a: f"(min({ctx[a]}, 1.0) == 1.0 && max({ctx[a]}, -1.0) == -1.0)"), - ]) + base_rewrite - - def render_cast(self, dt:DType, val: str) -> str: return f"{self.type_map[dt]}({val})" - def render_dtype(self, dt:DType, mutable=True) -> str: return "var" - def render_load(self, x:str, dt:DType) -> str: return f"atomicLoad(&{x})" if is_packed(dt) else x - def buf_map(self, dt:DType) -> str: return "atomic" if is_packed(dt) else self.type_map[dt.base] - def render_kernel(self, function_name:str, kernel:list[str], bufs:list[tuple[str,tuple[DType,bool]]], uops:list[UOp], prefix=None) -> str: - local_size = [num for _, num in sorted([u.arg for u in uops if u.op is Ops.SPECIAL and u.arg[0][0] == 'l'], key=lambda x: x[0])] - if not local_size: local_size = [1] - bind_it = iter(range(len(bufs))) - external_local_bufs = [line.lstrip() for line in kernel if "var" in line] - kernel[:] = [line for line in kernel if "var" not in line] - prg = "enable f16;\n" if any(uop.dtype.base == dtypes.half for uop in uops) else "" - prg += "fn nan() -> f32 { let bits = 0xffffffffu; return bitcast(bits); }\n" - prg += "@group(0) @binding(0)\nvar INFINITY : f32;\n" - prg += "\n".join((external_local_bufs or [])+[f"@group(0) @binding({next(bind_it)+1})" + - f"{'var' if isinstance(dtype, PtrDType) else 'var'}" + - f"{name}:{f'array<{self.buf_map(dtype.base)}>' if isinstance(dtype,PtrDType) else self.buf_map(dtype)};" for name,(dtype,_) in bufs]) - prg += f"\n@compute @workgroup_size({','.join([str(x) for x in local_size])}) fn {function_name}(@builtin(workgroup_id) gindex: vec3," - return prg + "@builtin(local_invocation_id) lindex: vec3) {\n" + "\n".join(kernel) + "\n}" diff --git a/tinygrad/tinygrad/runtime/__init__.py b/tinygrad/tinygrad/runtime/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/runtime/autogen/adreno.py b/tinygrad/tinygrad/runtime/autogen/adreno.py deleted file mode 100644 index 4228e021..00000000 --- a/tinygrad/tinygrad/runtime/autogen/adreno.py +++ /dev/null @@ -1,17904 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - - - -A6XX_XML = True # macro -# def __struct_cast(X): # macro -# return (structX) -REG_CP_LOAD_STATE_0 = 0x00000000 # macro -CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff # macro -CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 # macro -CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 # macro -CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 # macro -CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE_1 = 0x00000001 # macro -CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 # macro -CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 # macro -CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE4_0 = 0x00000000 # macro -CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff # macro -CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 # macro -CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 # macro -CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 # macro -CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE4_1 = 0x00000001 # macro -CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 # macro -CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 # macro -CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE4_2 = 0x00000002 # macro -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro -REG_CP_LOAD_STATE6_0 = 0x00000000 # macro -CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff # macro -CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 # macro -CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 # macro -CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 # macro -CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 # macro -CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 # macro -CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE6_1 = 0x00000001 # macro -CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE6_2 = 0x00000002 # macro -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro -REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 # macro -REG_CP_DRAW_INDX_0 = 0x00000000 # macro -CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff # macro -CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 # macro -REG_CP_DRAW_INDX_1 = 0x00000001 # macro -CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 # macro -CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 # macro -CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 # macro -CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 # macro -CP_DRAW_INDX_1_NOT_EOP = 0x00001000 # macro -CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 # macro -CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro -CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 # macro -CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 # macro -REG_CP_DRAW_INDX_2 = 0x00000002 # macro -CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_3 = 0x00000003 # macro -CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff # macro -CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_4 = 0x00000004 # macro -CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff # macro -CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_2_0 = 0x00000000 # macro -CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 # macro -REG_CP_DRAW_INDX_2_1 = 0x00000001 # macro -CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 # macro -CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 # macro -CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 # macro -CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 # macro -CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 # macro -CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 # macro -CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro -CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 # macro -CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 # macro -REG_CP_DRAW_INDX_2_2 = 0x00000002 # macro -CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 # macro -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 # macro -CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 # macro -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 # macro -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 # macro -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 # macro -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 # macro -CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 # macro -CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 # macro -REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 # macro -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 # macro -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 # macro -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 # macro -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro -CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 # macro -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro -A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 # macro -A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro -REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 # macro -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 # macro -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 # macro -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a # macro -REG_CP_DRAW_AUTO_0 = 0x00000000 # macro -CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 # macro -CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 # macro -CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 # macro -CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 # macro -CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 # macro -CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 # macro -CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 # macro -CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 # macro -REG_CP_DRAW_AUTO_1 = 0x00000001 # macro -CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff # macro -CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 # macro -REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 # macro -REG_CP_DRAW_AUTO_4 = 0x00000004 # macro -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff # macro -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 # macro -REG_CP_DRAW_AUTO_5 = 0x00000005 # macro -CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff # macro -CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 # macro -REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 # macro -CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 # macro -REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 # macro -CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 # macro -REG_CP_DRAW_PRED_SET_0 = 0x00000000 # macro -CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 # macro -CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 # macro -CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 # macro -CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 # macro -REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 # macro -# def REG_CP_SET_DRAW_STATE_(i0): # macro -# return (0x00000000+0x3*i0) -CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff # macro -CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 # macro -CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 # macro -CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 # macro -CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 # macro -CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 # macro -CP_SET_DRAW_STATE__0_BINNING = 0x00100000 # macro -CP_SET_DRAW_STATE__0_GMEM = 0x00200000 # macro -CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 # macro -CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 # macro -CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 # macro -CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 # macro -CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_0 = 0x00000000 # macro -REG_CP_SET_BIN_1 = 0x00000001 # macro -CP_SET_BIN_1_X1__MASK = 0x0000ffff # macro -CP_SET_BIN_1_X1__SHIFT = 0 # macro -CP_SET_BIN_1_Y1__MASK = 0xffff0000 # macro -CP_SET_BIN_1_Y1__SHIFT = 16 # macro -REG_CP_SET_BIN_2 = 0x00000002 # macro -CP_SET_BIN_2_X2__MASK = 0x0000ffff # macro -CP_SET_BIN_2_X2__SHIFT = 0 # macro -CP_SET_BIN_2_Y2__MASK = 0xffff0000 # macro -CP_SET_BIN_2_Y2__SHIFT = 16 # macro -REG_CP_SET_BIN_DATA_0 = 0x00000000 # macro -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff # macro -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA_1 = 0x00000001 # macro -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff # macro -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_0 = 0x00000000 # macro -CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 # macro -CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 # macro -CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 # macro -CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 # macro -REG_CP_SET_BIN_DATA5_1 = 0x00000001 # macro -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_2 = 0x00000002 # macro -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_3 = 0x00000003 # macro -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_4 = 0x00000004 # macro -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_5 = 0x00000005 # macro -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_6 = 0x00000006 # macro -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_7 = 0x00000007 # macro -REG_CP_SET_BIN_DATA5_9 = 0x00000009 # macro -REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 # macro -REG_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 # macro -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 # macro -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 # macro -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 # macro -REG_CP_REG_RMW_0 = 0x00000000 # macro -CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff # macro -CP_REG_RMW_0_DST_REG__SHIFT = 0 # macro -CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 # macro -CP_REG_RMW_0_ROTATE__SHIFT = 24 # macro -CP_REG_RMW_0_SRC1_ADD = 0x20000000 # macro -CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 # macro -CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 # macro -REG_CP_REG_RMW_1 = 0x00000001 # macro -CP_REG_RMW_1_SRC0__MASK = 0xffffffff # macro -CP_REG_RMW_1_SRC0__SHIFT = 0 # macro -REG_CP_REG_RMW_2 = 0x00000002 # macro -CP_REG_RMW_2_SRC1__MASK = 0xffffffff # macro -CP_REG_RMW_2_SRC1__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_0 = 0x00000000 # macro -CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_1 = 0x00000001 # macro -CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_2 = 0x00000002 # macro -CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 # macro -CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 # macro -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 # macro -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 # macro -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 # macro -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 # macro -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 # macro -REG_CP_MEM_TO_REG_0 = 0x00000000 # macro -CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff # macro -CP_MEM_TO_REG_0_REG__SHIFT = 0 # macro -CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 # macro -CP_MEM_TO_REG_0_CNT__SHIFT = 19 # macro -CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 # macro -CP_MEM_TO_REG_0_UNK31 = 0x80000000 # macro -REG_CP_MEM_TO_REG_1 = 0x00000001 # macro -CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff # macro -CP_MEM_TO_REG_1_SRC__SHIFT = 0 # macro -REG_CP_MEM_TO_REG_2 = 0x00000002 # macro -CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff # macro -CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 # macro -REG_CP_MEM_TO_MEM_0 = 0x00000000 # macro -CP_MEM_TO_MEM_0_NEG_A = 0x00000001 # macro -CP_MEM_TO_MEM_0_NEG_B = 0x00000002 # macro -CP_MEM_TO_MEM_0_NEG_C = 0x00000004 # macro -CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 # macro -CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 # macro -CP_MEM_TO_MEM_0_UNK31 = 0x80000000 # macro -REG_CP_MEMCPY_0 = 0x00000000 # macro -CP_MEMCPY_0_DWORDS__MASK = 0xffffffff # macro -CP_MEMCPY_0_DWORDS__SHIFT = 0 # macro -REG_CP_MEMCPY_1 = 0x00000001 # macro -CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff # macro -CP_MEMCPY_1_SRC_LO__SHIFT = 0 # macro -REG_CP_MEMCPY_2 = 0x00000002 # macro -CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff # macro -CP_MEMCPY_2_SRC_HI__SHIFT = 0 # macro -REG_CP_MEMCPY_3 = 0x00000003 # macro -CP_MEMCPY_3_DST_LO__MASK = 0xffffffff # macro -CP_MEMCPY_3_DST_LO__SHIFT = 0 # macro -REG_CP_MEMCPY_4 = 0x00000004 # macro -CP_MEMCPY_4_DST_HI__MASK = 0xffffffff # macro -CP_MEMCPY_4_DST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_SCRATCH_0 = 0x00000000 # macro -CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 # macro -CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 # macro -CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 # macro -CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 # macro -CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 # macro -REG_CP_SCRATCH_TO_REG_0 = 0x00000000 # macro -CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff # macro -CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 # macro -CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 # macro -CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 # macro -CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 # macro -CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 # macro -CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 # macro -REG_CP_SCRATCH_WRITE_0 = 0x00000000 # macro -CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 # macro -CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 # macro -REG_CP_MEM_WRITE_0 = 0x00000000 # macro -CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff # macro -CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 # macro -REG_CP_MEM_WRITE_1 = 0x00000001 # macro -CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff # macro -CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE_0 = 0x00000000 # macro -CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 # macro -CP_COND_WRITE_0_FUNCTION__SHIFT = 0 # macro -CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 # macro -CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_COND_WRITE_1 = 0x00000001 # macro -CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff # macro -CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 # macro -REG_CP_COND_WRITE_2 = 0x00000002 # macro -CP_COND_WRITE_2_REF__MASK = 0xffffffff # macro -CP_COND_WRITE_2_REF__SHIFT = 0 # macro -REG_CP_COND_WRITE_3 = 0x00000003 # macro -CP_COND_WRITE_3_MASK__MASK = 0xffffffff # macro -CP_COND_WRITE_3_MASK__SHIFT = 0 # macro -REG_CP_COND_WRITE_4 = 0x00000004 # macro -CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff # macro -CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 # macro -REG_CP_COND_WRITE_5 = 0x00000005 # macro -CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff # macro -CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 # macro -REG_CP_COND_WRITE5_0 = 0x00000000 # macro -CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 # macro -CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 # macro -CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 # macro -CP_COND_WRITE5_0_POLL__MASK = 0x00000030 # macro -CP_COND_WRITE5_0_POLL__SHIFT = 4 # macro -CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_COND_WRITE5_1 = 0x00000001 # macro -CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_COND_WRITE5_2 = 0x00000002 # macro -CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE5_3 = 0x00000003 # macro -CP_COND_WRITE5_3_REF__MASK = 0xffffffff # macro -CP_COND_WRITE5_3_REF__SHIFT = 0 # macro -REG_CP_COND_WRITE5_4 = 0x00000004 # macro -CP_COND_WRITE5_4_MASK__MASK = 0xffffffff # macro -CP_COND_WRITE5_4_MASK__SHIFT = 0 # macro -REG_CP_COND_WRITE5_5 = 0x00000005 # macro -CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff # macro -CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 # macro -REG_CP_COND_WRITE5_6 = 0x00000006 # macro -CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff # macro -CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE5_7 = 0x00000007 # macro -CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff # macro -CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_0 = 0x00000000 # macro -CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_1 = 0x00000001 # macro -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_2 = 0x00000002 # macro -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_3 = 0x00000003 # macro -CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_0 = 0x00000000 # macro -CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 # macro -CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 # macro -CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 # macro -CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 # macro -CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 # macro -CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_WAIT_REG_MEM_1 = 0x00000001 # macro -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_2 = 0x00000002 # macro -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_3 = 0x00000003 # macro -CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_3_REF__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_4 = 0x00000004 # macro -CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_5 = 0x00000005 # macro -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_0 = 0x00000000 # macro -CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff # macro -CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_1 = 0x00000001 # macro -CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff # macro -CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_2 = 0x00000002 # macro -CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff # macro -CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 # macro -REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 # macro -CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 # macro -CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 # macro -CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_0 = 0x00000000 # macro -CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff # macro -CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_1 = 0x00000001 # macro -CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_2 = 0x00000002 # macro -CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_3 = 0x00000003 # macro -CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 # macro -CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 # macro -REG_CP_SET_RENDER_MODE_4 = 0x00000004 # macro -REG_CP_SET_RENDER_MODE_5 = 0x00000005 # macro -CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_6 = 0x00000006 # macro -CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_7 = 0x00000007 # macro -CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 # macro -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 # macro -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 # macro -REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 # macro -REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 # macro -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 # macro -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 # macro -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 # macro -REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 # macro -REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 # macro -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 # macro -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_0 = 0x00000000 # macro -CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff # macro -CP_EVENT_WRITE_0_EVENT__SHIFT = 0 # macro -CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 # macro -CP_EVENT_WRITE_0_IRQ = 0x80000000 # macro -REG_CP_EVENT_WRITE_1 = 0x00000001 # macro -CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_2 = 0x00000002 # macro -CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_3 = 0x00000003 # macro -REG_CP_EVENT_WRITE7_0 = 0x00000000 # macro -CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff # macro -CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 # macro -CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 # macro -CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 # macro -CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 # macro -CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 # macro -CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 # macro -CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 # macro -CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 # macro -CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 # macro -CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 # macro -CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 # macro -CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 # macro -CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 # macro -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_2 = 0x00000002 # macro -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 # macro -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 # macro -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro -REG_CP_BLIT_0 = 0x00000000 # macro -CP_BLIT_0_OP__MASK = 0x0000000f # macro -CP_BLIT_0_OP__SHIFT = 0 # macro -REG_CP_BLIT_1 = 0x00000001 # macro -CP_BLIT_1_SRC_X1__MASK = 0x00003fff # macro -CP_BLIT_1_SRC_X1__SHIFT = 0 # macro -CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 # macro -CP_BLIT_1_SRC_Y1__SHIFT = 16 # macro -REG_CP_BLIT_2 = 0x00000002 # macro -CP_BLIT_2_SRC_X2__MASK = 0x00003fff # macro -CP_BLIT_2_SRC_X2__SHIFT = 0 # macro -CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 # macro -CP_BLIT_2_SRC_Y2__SHIFT = 16 # macro -REG_CP_BLIT_3 = 0x00000003 # macro -CP_BLIT_3_DST_X1__MASK = 0x00003fff # macro -CP_BLIT_3_DST_X1__SHIFT = 0 # macro -CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 # macro -CP_BLIT_3_DST_Y1__SHIFT = 16 # macro -REG_CP_BLIT_4 = 0x00000004 # macro -CP_BLIT_4_DST_X2__MASK = 0x00003fff # macro -CP_BLIT_4_DST_X2__SHIFT = 0 # macro -CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 # macro -CP_BLIT_4_DST_Y2__SHIFT = 16 # macro -REG_CP_EXEC_CS_0 = 0x00000000 # macro -REG_CP_EXEC_CS_1 = 0x00000001 # macro -CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff # macro -CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 # macro -REG_CP_EXEC_CS_2 = 0x00000002 # macro -CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff # macro -CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 # macro -REG_CP_EXEC_CS_3 = 0x00000003 # macro -CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff # macro -CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff # macro -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff # macro -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff # macro -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_CP_SET_MARKER_0 = 0x00000000 # macro -A6XX_CP_SET_MARKER_0_MODE__MASK = 0x000001ff # macro -A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 # macro -A6XX_CP_SET_MARKER_0_MARKER__MASK = 0x0000000f # macro -A6XX_CP_SET_MARKER_0_MARKER__SHIFT = 0 # macro -# def REG_A6XX_CP_SET_PSEUDO_REG_(i0): # macro -# return (0x00000000+0x3*i0) -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff # macro -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 # macro -A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff # macro -A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 # macro -A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff # macro -A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 # macro -REG_A6XX_CP_REG_TEST_0 = 0x00000000 # macro -A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff # macro -A6XX_CP_REG_TEST_0_REG__SHIFT = 0 # macro -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff # macro -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 # macro -A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 # macro -A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 # macro -A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 # macro -A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 # macro -A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 # macro -A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 # macro -A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 # macro -A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 # macro -REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 # macro -REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 # macro -REG_CP_COND_REG_EXEC_0 = 0x00000000 # macro -CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff # macro -CP_COND_REG_EXEC_0_REG0__SHIFT = 0 # macro -CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 # macro -CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 # macro -CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 # macro -CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 # macro -CP_COND_REG_EXEC_0_BINNING = 0x02000000 # macro -CP_COND_REG_EXEC_0_GMEM = 0x04000000 # macro -CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 # macro -CP_COND_REG_EXEC_0_BV = 0x02000000 # macro -CP_COND_REG_EXEC_0_BR = 0x04000000 # macro -CP_COND_REG_EXEC_0_LPAC = 0x08000000 # macro -CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 # macro -CP_COND_REG_EXEC_0_MODE__SHIFT = 28 # macro -REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 # macro -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff # macro -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 # macro -REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 # macro -REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 # macro -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff # macro -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 # macro -REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_CP_COND_REG_EXEC_2 = 0x00000002 # macro -CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff # macro -CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 # macro -REG_CP_COND_EXEC_0 = 0x00000000 # macro -CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff # macro -CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 # macro -REG_CP_COND_EXEC_1 = 0x00000001 # macro -CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff # macro -CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 # macro -REG_CP_COND_EXEC_2 = 0x00000002 # macro -CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff # macro -CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 # macro -REG_CP_COND_EXEC_3 = 0x00000003 # macro -CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff # macro -CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 # macro -REG_CP_COND_EXEC_4 = 0x00000004 # macro -CP_COND_EXEC_4_REF__MASK = 0xffffffff # macro -CP_COND_EXEC_4_REF__SHIFT = 0 # macro -REG_CP_COND_EXEC_5 = 0x00000005 # macro -CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff # macro -CP_COND_EXEC_5_DWORDS__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_0 = 0x00000000 # macro -CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_1 = 0x00000001 # macro -CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_2 = 0x00000002 # macro -CP_SET_CTXSWITCH_IB_2_DWORDS__MASK = 0x000fffff # macro -CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT = 0 # macro -CP_SET_CTXSWITCH_IB_2_TYPE__MASK = 0x00300000 # macro -CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT = 20 # macro -REG_CP_REG_WRITE_0 = 0x00000000 # macro -CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f # macro -CP_REG_WRITE_0_TRACKER__SHIFT = 0 # macro -REG_CP_REG_WRITE_1 = 0x00000001 # macro -REG_CP_REG_WRITE_2 = 0x00000002 # macro -REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 # macro -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 # macro -REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 # macro -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff # macro -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 # macro -CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 # macro -CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 # macro -REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 # macro -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 # macro -REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 # macro -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 # macro -REG_CP_START_BIN_BIN_COUNT = 0x00000000 # macro -REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 # macro -REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 # macro -REG_CP_START_BIN_BODY_DWORDS = 0x00000004 # macro -REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 # macro -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 # macro -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 # macro -CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 # macro -CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 # macro -REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 # macro -REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 # macro -REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 # macro -REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 # macro -REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 # macro -CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f # macro -CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 # macro -REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 # macro -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff # macro -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 # macro -REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 # macro -CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff # macro -CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 # macro -CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 # macro -CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 # macro -REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 # macro -CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f # macro -CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 # macro -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f # macro -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 # macro -CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff # macro -CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 # macro -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff # macro -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 # macro -REG_CP_THREAD_CONTROL_0 = 0x00000000 # macro -CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 # macro -CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 # macro -CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 # macro -CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 # macro -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff # macro -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 # macro -REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS = 0x00000004 # macro -REG_AXXX_CP_RB_BASE = 0x000001c0 # macro -REG_AXXX_CP_RB_CNTL = 0x000001c1 # macro -AXXX_CP_RB_CNTL_BUFSZ__MASK = 0x0000003f # macro -AXXX_CP_RB_CNTL_BUFSZ__SHIFT = 0 # macro -AXXX_CP_RB_CNTL_BLKSZ__MASK = 0x00003f00 # macro -AXXX_CP_RB_CNTL_BLKSZ__SHIFT = 8 # macro -AXXX_CP_RB_CNTL_BUF_SWAP__MASK = 0x00030000 # macro -AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT = 16 # macro -AXXX_CP_RB_CNTL_POLL_EN = 0x00100000 # macro -AXXX_CP_RB_CNTL_NO_UPDATE = 0x08000000 # macro -AXXX_CP_RB_CNTL_RPTR_WR_EN = 0x80000000 # macro -REG_AXXX_CP_RB_RPTR_ADDR = 0x000001c3 # macro -AXXX_CP_RB_RPTR_ADDR_SWAP__MASK = 0x00000003 # macro -AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT = 0 # macro -AXXX_CP_RB_RPTR_ADDR_ADDR__MASK = 0xfffffffc # macro -AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT = 2 # macro -REG_AXXX_CP_RB_RPTR = 0x000001c4 # macro -REG_AXXX_CP_RB_WPTR = 0x000001c5 # macro -REG_AXXX_CP_RB_WPTR_DELAY = 0x000001c6 # macro -REG_AXXX_CP_RB_RPTR_WR = 0x000001c7 # macro -REG_AXXX_CP_RB_WPTR_BASE = 0x000001c8 # macro -REG_AXXX_CP_QUEUE_THRESHOLDS = 0x000001d5 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK = 0x0000000f # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT = 0 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK = 0x00000f00 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT = 8 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK = 0x000f0000 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT = 16 # macro -REG_AXXX_CP_MEQ_THRESHOLDS = 0x000001d6 # macro -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK = 0x001f0000 # macro -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT = 16 # macro -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK = 0x1f000000 # macro -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT = 24 # macro -REG_AXXX_CP_CSQ_AVAIL = 0x000001d7 # macro -AXXX_CP_CSQ_AVAIL_RING__MASK = 0x0000007f # macro -AXXX_CP_CSQ_AVAIL_RING__SHIFT = 0 # macro -AXXX_CP_CSQ_AVAIL_IB1__MASK = 0x00007f00 # macro -AXXX_CP_CSQ_AVAIL_IB1__SHIFT = 8 # macro -AXXX_CP_CSQ_AVAIL_IB2__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_AVAIL_IB2__SHIFT = 16 # macro -REG_AXXX_CP_STQ_AVAIL = 0x000001d8 # macro -AXXX_CP_STQ_AVAIL_ST__MASK = 0x0000007f # macro -AXXX_CP_STQ_AVAIL_ST__SHIFT = 0 # macro -REG_AXXX_CP_MEQ_AVAIL = 0x000001d9 # macro -AXXX_CP_MEQ_AVAIL_MEQ__MASK = 0x0000001f # macro -AXXX_CP_MEQ_AVAIL_MEQ__SHIFT = 0 # macro -REG_AXXX_SCRATCH_UMSK = 0x000001dc # macro -AXXX_SCRATCH_UMSK_UMSK__MASK = 0x000000ff # macro -AXXX_SCRATCH_UMSK_UMSK__SHIFT = 0 # macro -AXXX_SCRATCH_UMSK_SWAP__MASK = 0x00030000 # macro -AXXX_SCRATCH_UMSK_SWAP__SHIFT = 16 # macro -REG_AXXX_SCRATCH_ADDR = 0x000001dd # macro -REG_AXXX_CP_ME_RDADDR = 0x000001ea # macro -REG_AXXX_CP_STATE_DEBUG_INDEX = 0x000001ec # macro -REG_AXXX_CP_STATE_DEBUG_DATA = 0x000001ed # macro -REG_AXXX_CP_INT_CNTL = 0x000001f2 # macro -AXXX_CP_INT_CNTL_SW_INT_MASK = 0x00080000 # macro -AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK = 0x00800000 # macro -AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK = 0x01000000 # macro -AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK = 0x02000000 # macro -AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK = 0x04000000 # macro -AXXX_CP_INT_CNTL_IB_ERROR_MASK = 0x08000000 # macro -AXXX_CP_INT_CNTL_IB2_INT_MASK = 0x20000000 # macro -AXXX_CP_INT_CNTL_IB1_INT_MASK = 0x40000000 # macro -AXXX_CP_INT_CNTL_RB_INT_MASK = 0x80000000 # macro -REG_AXXX_CP_INT_STATUS = 0x000001f3 # macro -REG_AXXX_CP_INT_ACK = 0x000001f4 # macro -REG_AXXX_CP_ME_CNTL = 0x000001f6 # macro -AXXX_CP_ME_CNTL_BUSY = 0x20000000 # macro -AXXX_CP_ME_CNTL_HALT = 0x10000000 # macro -REG_AXXX_CP_ME_STATUS = 0x000001f7 # macro -REG_AXXX_CP_ME_RAM_WADDR = 0x000001f8 # macro -REG_AXXX_CP_ME_RAM_RADDR = 0x000001f9 # macro -REG_AXXX_CP_ME_RAM_DATA = 0x000001fa # macro -REG_AXXX_CP_DEBUG = 0x000001fc # macro -AXXX_CP_DEBUG_PREDICATE_DISABLE = 0x00800000 # macro -AXXX_CP_DEBUG_PROG_END_PTR_ENABLE = 0x01000000 # macro -AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE = 0x02000000 # macro -AXXX_CP_DEBUG_PREFETCH_PASS_NOPS = 0x04000000 # macro -AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE = 0x08000000 # macro -AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE = 0x10000000 # macro -AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL = 0x40000000 # macro -AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE = 0x80000000 # macro -REG_AXXX_CP_CSQ_RB_STAT = 0x000001fd # macro -AXXX_CP_CSQ_RB_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_RB_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_CSQ_IB1_STAT = 0x000001fe # macro -AXXX_CP_CSQ_IB1_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_IB1_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_CSQ_IB2_STAT = 0x000001ff # macro -AXXX_CP_CSQ_IB2_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_IB2_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_NON_PREFETCH_CNTRS = 0x00000440 # macro -REG_AXXX_CP_STQ_ST_STAT = 0x00000443 # macro -REG_AXXX_CP_ST_BASE = 0x0000044d # macro -REG_AXXX_CP_ST_BUFSZ = 0x0000044e # macro -REG_AXXX_CP_MEQ_STAT = 0x0000044f # macro -REG_AXXX_CP_MIU_TAG_STAT = 0x00000452 # macro -REG_AXXX_CP_BIN_MASK_LO = 0x00000454 # macro -REG_AXXX_CP_BIN_MASK_HI = 0x00000455 # macro -REG_AXXX_CP_BIN_SELECT_LO = 0x00000456 # macro -REG_AXXX_CP_BIN_SELECT_HI = 0x00000457 # macro -REG_AXXX_CP_IB1_BASE = 0x00000458 # macro -REG_AXXX_CP_IB1_BUFSZ = 0x00000459 # macro -REG_AXXX_CP_IB2_BASE = 0x0000045a # macro -REG_AXXX_CP_IB2_BUFSZ = 0x0000045b # macro -REG_AXXX_CP_STAT = 0x0000047f # macro -AXXX_CP_STAT_CP_BUSY = 0x80000000 # macro -AXXX_CP_STAT_VS_EVENT_FIFO_BUSY = 0x40000000 # macro -AXXX_CP_STAT_PS_EVENT_FIFO_BUSY = 0x20000000 # macro -AXXX_CP_STAT_CF_EVENT_FIFO_BUSY = 0x10000000 # macro -AXXX_CP_STAT_RB_EVENT_FIFO_BUSY = 0x08000000 # macro -AXXX_CP_STAT_ME_BUSY = 0x04000000 # macro -AXXX_CP_STAT_MIU_WR_C_BUSY = 0x02000000 # macro -AXXX_CP_STAT_CP_3D_BUSY = 0x00800000 # macro -AXXX_CP_STAT_CP_NRT_BUSY = 0x00400000 # macro -AXXX_CP_STAT_RBIU_SCRATCH_BUSY = 0x00200000 # macro -AXXX_CP_STAT_RCIU_ME_BUSY = 0x00100000 # macro -AXXX_CP_STAT_RCIU_PFP_BUSY = 0x00080000 # macro -AXXX_CP_STAT_MEQ_RING_BUSY = 0x00040000 # macro -AXXX_CP_STAT_PFP_BUSY = 0x00020000 # macro -AXXX_CP_STAT_ST_QUEUE_BUSY = 0x00010000 # macro -AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY = 0x00002000 # macro -AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY = 0x00001000 # macro -AXXX_CP_STAT_RING_QUEUE_BUSY = 0x00000800 # macro -AXXX_CP_STAT_CSF_BUSY = 0x00000400 # macro -AXXX_CP_STAT_CSF_ST_BUSY = 0x00000200 # macro -AXXX_CP_STAT_EVENT_BUSY = 0x00000100 # macro -AXXX_CP_STAT_CSF_INDIRECT2_BUSY = 0x00000080 # macro -AXXX_CP_STAT_CSF_INDIRECTS_BUSY = 0x00000040 # macro -AXXX_CP_STAT_CSF_RING_BUSY = 0x00000020 # macro -AXXX_CP_STAT_RCIU_BUSY = 0x00000010 # macro -AXXX_CP_STAT_RBIU_BUSY = 0x00000008 # macro -AXXX_CP_STAT_MIU_RD_RETURN_BUSY = 0x00000004 # macro -AXXX_CP_STAT_MIU_RD_REQ_BUSY = 0x00000002 # macro -AXXX_CP_STAT_MIU_WR_BUSY = 0x00000001 # macro -REG_AXXX_CP_SCRATCH_REG0 = 0x00000578 # macro -REG_AXXX_CP_SCRATCH_REG1 = 0x00000579 # macro -REG_AXXX_CP_SCRATCH_REG2 = 0x0000057a # macro -REG_AXXX_CP_SCRATCH_REG3 = 0x0000057b # macro -REG_AXXX_CP_SCRATCH_REG4 = 0x0000057c # macro -REG_AXXX_CP_SCRATCH_REG5 = 0x0000057d # macro -REG_AXXX_CP_SCRATCH_REG6 = 0x0000057e # macro -REG_AXXX_CP_SCRATCH_REG7 = 0x0000057f # macro -REG_AXXX_CP_ME_VS_EVENT_SRC = 0x00000600 # macro -REG_AXXX_CP_ME_VS_EVENT_ADDR = 0x00000601 # macro -REG_AXXX_CP_ME_VS_EVENT_DATA = 0x00000602 # macro -REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM = 0x00000603 # macro -REG_AXXX_CP_ME_VS_EVENT_DATA_SWM = 0x00000604 # macro -REG_AXXX_CP_ME_PS_EVENT_SRC = 0x00000605 # macro -REG_AXXX_CP_ME_PS_EVENT_ADDR = 0x00000606 # macro -REG_AXXX_CP_ME_PS_EVENT_DATA = 0x00000607 # macro -REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM = 0x00000608 # macro -REG_AXXX_CP_ME_PS_EVENT_DATA_SWM = 0x00000609 # macro -REG_AXXX_CP_ME_CF_EVENT_SRC = 0x0000060a # macro -REG_AXXX_CP_ME_CF_EVENT_ADDR = 0x0000060b # macro -REG_AXXX_CP_ME_CF_EVENT_DATA = 0x0000060c # macro -REG_AXXX_CP_ME_NRT_ADDR = 0x0000060d # macro -REG_AXXX_CP_ME_NRT_DATA = 0x0000060e # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_SRC = 0x00000612 # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR = 0x00000613 # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_DATA = 0x00000614 # macro -A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 # macro -A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 # macro -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 # macro -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 # macro -A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 # macro -A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 # macro -A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 # macro -A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 # macro -A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 # macro -A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 # macro -A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 # macro -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 # macro -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 # macro -A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 # macro -A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 # macro -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 # macro -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 # macro -A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 # macro -A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 # macro -A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 # macro -A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 # macro -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 # macro -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 # macro -A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 # macro -A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 # macro -A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 # macro -A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 # macro -A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 # macro -A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 # macro -A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 # macro -A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 # macro -A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 # macro -A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 # macro -A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 # macro -A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 # macro -REG_A6XX_CP_RB_BASE = 0x00000800 # macro -REG_A6XX_CP_RB_CNTL = 0x00000802 # macro -REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 # macro -REG_A6XX_CP_RB_RPTR = 0x00000806 # macro -REG_A6XX_CP_RB_WPTR = 0x00000807 # macro -REG_A6XX_CP_SQE_CNTL = 0x00000808 # macro -REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 # macro -A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 # macro -REG_A6XX_CP_HW_FAULT = 0x00000821 # macro -REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 # macro -REG_A6XX_CP_PROTECT_STATUS = 0x00000824 # macro -REG_A6XX_CP_STATUS_1 = 0x00000825 # macro -REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 # macro -REG_A6XX_CP_MISC_CNTL = 0x00000840 # macro -REG_A6XX_CP_APRIV_CNTL = 0x00000844 # macro -A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 # macro -A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 # macro -A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 # macro -A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 # macro -A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 # macro -A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 # macro -REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 # macro -REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 # macro -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff # macro -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 # macro -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 # macro -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 # macro -REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 # macro -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff # macro -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 # macro -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 # macro -REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 # macro -REG_A6XX_CP_CHICKEN_DBG = 0x00000841 # macro -REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 # macro -REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 # macro -REG_A6XX_CP_PROTECT_CNTL = 0x0000084f # macro -A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 # macro -A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 # macro -A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 # macro -# def REG_A6XX_CP_SCRATCH(i0): # macro -# return (0x00000883+0x1*i0) -# def REG_A6XX_CP_PROTECT(i0): # macro -# return (0x00000850+0x1*i0) -A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff # macro -A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 # macro -A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 # macro -A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 # macro -A6XX_CP_PROTECT_REG_READ = 0x80000000 # macro -REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 # macro -REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 # macro -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 # macro -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 # macro -REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 # macro -REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab # macro -# def REG_A6XX_CP_PERFCTR_CP_SEL(i0): # macro -# return (0x000008d0+0x1*i0) -# def REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0): # macro -# return (0x000008e0+0x1*i0) -REG_A6XX_CP_CRASH_SCRIPT_BASE = 0x00000900 # macro -REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 # macro -REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 # macro -REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 # macro -REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 # macro -REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a # macro -REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b # macro -REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c # macro -REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d # macro -REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e # macro -REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f # macro -REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 # macro -REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 # macro -REG_A6XX_CP_IB1_BASE = 0x00000928 # macro -REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a # macro -REG_A6XX_CP_IB2_BASE = 0x0000092b # macro -REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d # macro -REG_A6XX_CP_SDS_BASE = 0x0000092e # macro -REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 # macro -REG_A6XX_CP_MRB_BASE = 0x00000931 # macro -REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 # macro -REG_A6XX_CP_VSD_BASE = 0x00000934 # macro -REG_A6XX_CP_ROQ_RB_STAT = 0x00000939 # macro -A6XX_CP_ROQ_RB_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_RB_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_IB1_STAT = 0x0000093a # macro -A6XX_CP_ROQ_IB1_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_IB1_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_IB2_STAT = 0x0000093b # macro -A6XX_CP_ROQ_IB2_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_IB2_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_SDS_STAT = 0x0000093c # macro -A6XX_CP_ROQ_SDS_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_SDS_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_MRB_STAT = 0x0000093d # macro -A6XX_CP_ROQ_MRB_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_MRB_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_VSD_STAT = 0x0000093e # macro -A6XX_CP_ROQ_VSD_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_VSD_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_IB1_DWORDS = 0x00000943 # macro -REG_A6XX_CP_IB2_DWORDS = 0x00000944 # macro -REG_A6XX_CP_SDS_DWORDS = 0x00000945 # macro -REG_A6XX_CP_MRB_DWORDS = 0x00000946 # macro -REG_A6XX_CP_VSD_DWORDS = 0x00000947 # macro -REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 # macro -A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 # macro -A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a # macro -A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b # macro -A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c # macro -A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d # macro -A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 # macro -REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 # macro -REG_A6XX_CP_AHB_CNTL = 0x0000098d # macro -REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro -REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro -A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 # macro -A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 # macro -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 # macro -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 # macro -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 # macro -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 # macro -REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro -REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro -A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 # macro -A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 # macro -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 # macro -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 # macro -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 # macro -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 # macro -REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 # macro -REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 # macro -REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 # macro -REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 # macro -REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 # macro -REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 # macro -REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 # macro -REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 # macro -REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 # macro -REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 # macro -REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 # macro -REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 # macro -REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 # macro -REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR = 0x00000a9a # macro -REG_A7XX_CP_RESOURCE_TBL_DBG_DATA = 0x00000a9b # macro -REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 # macro -REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada # macro -REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a # macro -REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b # macro -REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c # macro -REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 # macro -REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 # macro -REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 # macro -REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a # macro -REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 # macro -REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 # macro -REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 # macro -REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 # macro -REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 # macro -REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 # macro -REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 # macro -REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 # macro -REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 # macro -REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 # macro -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 # macro -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 # macro -REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac # macro -REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad # macro -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 # macro -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 # macro -REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 # macro -REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 # macro -REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 # macro -REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 # macro -REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc # macro -REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd # macro -REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 # macro -REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 # macro -REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 # macro -REG_A6XX_RBBM_STATUS = 0x00000210 # macro -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 # macro -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 # macro -A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 # macro -A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 # macro -A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 # macro -A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 # macro -A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 # macro -A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 # macro -A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 # macro -A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 # macro -A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 # macro -A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 # macro -A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 # macro -A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 # macro -A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 # macro -A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 # macro -A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 # macro -A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 # macro -A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 # macro -A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 # macro -A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 # macro -A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 # macro -A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 # macro -A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 # macro -REG_A6XX_RBBM_STATUS1 = 0x00000211 # macro -REG_A6XX_RBBM_STATUS2 = 0x00000212 # macro -REG_A6XX_RBBM_STATUS3 = 0x00000213 # macro -A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 # macro -REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 # macro -REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 # macro -REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 # macro -REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 # macro -REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 # macro -# def REG_A6XX_RBBM_PERFCTR_CP(i0): # macro -# return (0x00000400+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RBBM(i0): # macro -# return (0x0000041c+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_PC(i0): # macro -# return (0x00000424+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VFD(i0): # macro -# return (0x00000434+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_HLSQ(i0): # macro -# return (0x00000444+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VPC(i0): # macro -# return (0x00000450+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_CCU(i0): # macro -# return (0x0000045c+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_TSE(i0): # macro -# return (0x00000466+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RAS(i0): # macro -# return (0x0000046e+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_UCHE(i0): # macro -# return (0x00000476+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_TP(i0): # macro -# return (0x0000048e+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_SP(i0): # macro -# return (0x000004a6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RB(i0): # macro -# return (0x000004d6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VSC(i0): # macro -# return (0x000004e6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_LRZ(i0): # macro -# return (0x000004ea+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_CMP(i0): # macro -# return (0x000004f2+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CP(i0): # macro -# return (0x00000300+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RBBM(i0): # macro -# return (0x0000031c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_PC(i0): # macro -# return (0x00000324+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VFD(i0): # macro -# return (0x00000334+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_HLSQ(i0): # macro -# return (0x00000344+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VPC(i0): # macro -# return (0x00000350+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CCU(i0): # macro -# return (0x0000035c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_TSE(i0): # macro -# return (0x00000366+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RAS(i0): # macro -# return (0x0000036e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_UCHE(i0): # macro -# return (0x00000376+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_TP(i0): # macro -# return (0x0000038e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_SP(i0): # macro -# return (0x000003a6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RB(i0): # macro -# return (0x000003d6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VSC(i0): # macro -# return (0x000003e6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_LRZ(i0): # macro -# return (0x000003ea+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CMP(i0): # macro -# return (0x000003f2+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_UFC(i0): # macro -# return (0x000003fa+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_HLSQ(i0): # macro -# return (0x00000410+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_CP(i0): # macro -# return (0x0000041c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_SP(i0): # macro -# return (0x0000042a+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_TP(i0): # macro -# return (0x00000442+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_UFC(i0): # macro -# return (0x0000044e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_PC(i0): # macro -# return (0x00000460+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_VFD(i0): # macro -# return (0x00000470+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_VPC(i0): # macro -# return (0x00000480+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_TSE(i0): # macro -# return (0x0000048c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_RAS(i0): # macro -# return (0x00000494+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0): # macro -# return (0x0000049c+0x2*i0) -REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 # macro -# def REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0): # macro -# return (0x00000507+0x1*i0) -REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b # macro -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e # macro -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f # macro -REG_A6XX_RBBM_ISDB_CNT = 0x00000533 # macro -REG_A7XX_RBBM_NC_MODE_CNTL = 0x00000534 # macro -REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 # macro -REG_A6XX_RBBM_PRIMCTR_0_LO = 0x00000540 # macro -REG_A6XX_RBBM_PRIMCTR_0_HI = 0x00000541 # macro -REG_A6XX_RBBM_PRIMCTR_1_LO = 0x00000542 # macro -REG_A6XX_RBBM_PRIMCTR_1_HI = 0x00000543 # macro -REG_A6XX_RBBM_PRIMCTR_2_LO = 0x00000544 # macro -REG_A6XX_RBBM_PRIMCTR_2_HI = 0x00000545 # macro -REG_A6XX_RBBM_PRIMCTR_3_LO = 0x00000546 # macro -REG_A6XX_RBBM_PRIMCTR_3_HI = 0x00000547 # macro -REG_A6XX_RBBM_PRIMCTR_4_LO = 0x00000548 # macro -REG_A6XX_RBBM_PRIMCTR_4_HI = 0x00000549 # macro -REG_A6XX_RBBM_PRIMCTR_5_LO = 0x0000054a # macro -REG_A6XX_RBBM_PRIMCTR_5_HI = 0x0000054b # macro -REG_A6XX_RBBM_PRIMCTR_6_LO = 0x0000054c # macro -REG_A6XX_RBBM_PRIMCTR_6_HI = 0x0000054d # macro -REG_A6XX_RBBM_PRIMCTR_7_LO = 0x0000054e # macro -REG_A6XX_RBBM_PRIMCTR_7_HI = 0x0000054f # macro -REG_A6XX_RBBM_PRIMCTR_8_LO = 0x00000550 # macro -REG_A6XX_RBBM_PRIMCTR_8_HI = 0x00000551 # macro -REG_A6XX_RBBM_PRIMCTR_9_LO = 0x00000552 # macro -REG_A6XX_RBBM_PRIMCTR_9_HI = 0x00000553 # macro -REG_A6XX_RBBM_PRIMCTR_10_LO = 0x00000554 # macro -REG_A6XX_RBBM_PRIMCTR_10_HI = 0x00000555 # macro -REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 # macro -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 # macro -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 # macro -REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 # macro -REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 # macro -REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 # macro -REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 # macro -REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 # macro -REG_A6XX_RBBM_GBIF_HALT = 0x00000016 # macro -REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro -REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c # macro -A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 # macro -REG_A7XX_RBBM_GBIF_HALT = 0x00000016 # macro -REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro -REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f # macro -REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 # macro -REG_A6XX_RBBM_INT_0_MASK = 0x00000038 # macro -REG_A7XX_RBBM_INT_2_MASK = 0x0000003a # macro -REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 # macro -REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 # macro -REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 # macro -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 # macro -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 # macro -REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad # macro -REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb # macro -REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc # macro -REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd # macro -REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be # macro -REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df # macro -REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 # macro -REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 # macro -REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 # macro -REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a # macro -REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b # macro -REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c # macro -REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d # macro -REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e # macro -REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f # macro -REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 # macro -REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 # macro -REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 # macro -REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 # macro -REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 # macro -REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 # macro -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 # macro -REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 # macro -REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a # macro -REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b # macro -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c # macro -REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d # macro -REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e # macro -REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f # macro -REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 # macro -REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 # macro -REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 # macro -A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 # macro -REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 # macro -REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 # macro -REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 # macro -REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 # macro -REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 # macro -REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 # macro -REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a # macro -REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b # macro -REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f # macro -REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 # macro -REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f # macro -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f # macro -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 # macro -# def REG_A6XX_VSC_PERFCTR_VSC_SEL(i0): # macro -# return (0x00000cd8+0x1*i0) -REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 # macro -A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 # macro -REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 # macro -REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 # macro -REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 # macro -REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 # macro -REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 # macro -REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 # macro -REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 # macro -REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b # macro -REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d # macro -REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 # macro -REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 # macro -REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 # macro -A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff # macro -A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 # macro -# def REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0): # macro -# return (0x00000e1c+0x1*i0) -REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a # macro -REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c # macro -REG_A6XX_VBIF_VERSION = 0x00003000 # macro -REG_A6XX_VBIF_CLKON = 0x00003001 # macro -A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 # macro -REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a # macro -REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 # macro -REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 # macro -REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 # macro -REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 # macro -REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 # macro -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f # macro -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 # macro -REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 # macro -REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 # macro -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff # macro -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 # macro -REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c # macro -REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 # macro -REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 # macro -REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 # macro -REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 # macro -REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 # macro -REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 # macro -REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da # macro -REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db # macro -REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a # macro -REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 # macro -REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 # macro -REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 # macro -REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 # macro -REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 # macro -REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 # macro -REG_A6XX_GBIF_HALT = 0x00003c45 # macro -REG_A6XX_GBIF_HALT_ACK = 0x00003c46 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 # macro -REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 # macro -REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 # macro -REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 # macro -REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 # macro -REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca # macro -REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb # macro -REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc # macro -REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd # macro -REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce # macro -REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf # macro -REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 # macro -REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 # macro -REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 # macro -REG_A6XX_VSC_BIN_SIZE = 0x00000c02 # macro -A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff # macro -A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 # macro -A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 # macro -A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 # macro -REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS = 0x00000c03 # macro -REG_A6XX_VSC_BIN_COUNT = 0x00000c06 # macro -A6XX_VSC_BIN_COUNT_NX__MASK = 0x000007fe # macro -A6XX_VSC_BIN_COUNT_NX__SHIFT = 1 # macro -A6XX_VSC_BIN_COUNT_NY__MASK = 0x001ff800 # macro -A6XX_VSC_BIN_COUNT_NY__SHIFT = 11 # macro -# def REG_A6XX_VSC_PIPE_CONFIG(i0): # macro -# return (0x00000c10+0x1*i0) -A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff # macro -A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 # macro -A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 # macro -A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 # macro -A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 # macro -A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 # macro -A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 # macro -A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 # macro -REG_A6XX_VSC_PRIM_STRM_ADDRESS = 0x00000c30 # macro -REG_A6XX_VSC_PRIM_STRM_PITCH = 0x00000c32 # macro -REG_A6XX_VSC_PRIM_STRM_LIMIT = 0x00000c33 # macro -REG_A6XX_VSC_DRAW_STRM_ADDRESS = 0x00000c34 # macro -REG_A6XX_VSC_DRAW_STRM_PITCH = 0x00000c36 # macro -REG_A6XX_VSC_DRAW_STRM_LIMIT = 0x00000c37 # macro -# def REG_A6XX_VSC_STATE(i0): # macro -# return (0x00000c38+0x1*i0) -# def REG_A6XX_VSC_PRIM_STRM_SIZE(i0): # macro -# return (0x00000c58+0x1*i0) -# def REG_A6XX_VSC_DRAW_STRM_SIZE(i0): # macro -# return (0x00000c78+0x1*i0) -REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 # macro -REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 # macro -REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 # macro -REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 # macro -REG_A6XX_GRAS_CL_CNTL = 0x00008000 # macro -A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 # macro -A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 # macro -A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 # macro -A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro -A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 # macro -A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 # macro -A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 # macro -A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 # macro -REG_A6XX_GRAS_VS_CL_CNTL = 0x00008001 # macro -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_DS_CL_CNTL = 0x00008002 # macro -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_GS_CL_CNTL = 0x00008003 # macro -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_MAX_LAYER_INDEX = 0x00008004 # macro -REG_A6XX_GRAS_CNTL = 0x00008005 # macro -A6XX_GRAS_CNTL_IJ_PERSP_PIXEL = 0x00000001 # macro -A6XX_GRAS_CNTL_IJ_PERSP_CENTROID = 0x00000002 # macro -A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE = 0x00000004 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL = 0x00000008 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID = 0x00000010 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 # macro -A6XX_GRAS_CNTL_COORD_MASK__MASK = 0x000003c0 # macro -A6XX_GRAS_CNTL_COORD_MASK__SHIFT = 6 # macro -A6XX_GRAS_CNTL_UNK10 = 0x00000400 # macro -A6XX_GRAS_CNTL_UNK11 = 0x00000800 # macro -REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 # macro -REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 # macro -REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 # macro -REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 # macro -REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a # macro -REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b # macro -REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c # macro -# def REG_A6XX_GRAS_CL_VPORT(i0): # macro -# return (0x00008010+0x6*i0) -A6XX_GRAS_CL_VPORT_XOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_XSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_XSCALE__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_YOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_YSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_YSCALE__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_ZOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_ZSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT = 0 # macro -# def REG_A6XX_GRAS_CL_Z_CLAMP(i0): # macro -# return (0x00008070+0x2*i0) -A6XX_GRAS_CL_Z_CLAMP_MIN__MASK = 0xffffffff # macro -A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT = 0 # macro -A6XX_GRAS_CL_Z_CLAMP_MAX__MASK = 0xffffffff # macro -A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_CNTL = 0x00008090 # macro -A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 # macro -A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 # macro -A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 # macro -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 # macro -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 # macro -A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 # macro -A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 # macro -A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 # macro -A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 # macro -A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 # macro -A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 # macro -A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 # macro -A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 # macro -A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 # macro -A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 # macro -A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 # macro -REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 # macro -A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff # macro -A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 # macro -A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 # macro -A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 # macro -REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 # macro -A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff # macro -A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 # macro -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 # macro -A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro -REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 # macro -REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a # macro -A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 # macro -A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 # macro -REG_A6XX_GRAS_VS_LAYER_CNTL = 0x0000809b # macro -A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_GS_LAYER_CNTL = 0x0000809c # macro -A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_DS_LAYER_CNTL = 0x0000809d # macro -A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_SC_CNTL = 0x000080a0 # macro -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 # macro -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 # macro -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 # macro -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 # macro -A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 # macro -A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 # macro -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 # macro -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 # macro -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 # macro -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 # macro -A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 # macro -A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 # macro -A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 # macro -A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 # macro -REG_A6XX_GRAS_BIN_CONTROL = 0x000080a1 # macro -A6XX_GRAS_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A6XX_GRAS_BIN_CONTROL_BINW__SHIFT = 0 # macro -A6XX_GRAS_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A6XX_GRAS_BIN_CONTROL_BINH__SHIFT = 8 # macro -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -A6XX_GRAS_BIN_CONTROL_UNK27 = 0x08000000 # macro -REG_A6XX_GRAS_RAS_MSAA_CNTL = 0x000080a2 # macro -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_GRAS_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro -A6XX_GRAS_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro -REG_A6XX_GRAS_DEST_MSAA_CNTL = 0x000080a3 # macro -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_GRAS_SAMPLE_CONFIG = 0x000080a4 # macro -A6XX_GRAS_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_GRAS_SAMPLE_LOCATION_0 = 0x000080a5 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_GRAS_SAMPLE_LOCATION_1 = 0x000080a6 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 # macro -REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af # macro -# def REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0): # macro -# return (0x000080b0+0x2*i0) -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 # macro -# def REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0): # macro -# return (0x000080d0+0x2*i0) -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A7XX_GRAS_UNKNOWN_80F4 = 0x000080f4 # macro -REG_A7XX_GRAS_UNKNOWN_80F5 = 0x000080f5 # macro -REG_A7XX_GRAS_UNKNOWN_80F6 = 0x000080f6 # macro -REG_A7XX_GRAS_UNKNOWN_80F8 = 0x000080f8 # macro -REG_A7XX_GRAS_UNKNOWN_80F9 = 0x000080f9 # macro -REG_A7XX_GRAS_UNKNOWN_80FA = 0x000080fa # macro -REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 # macro -A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 # macro -A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 # macro -A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 # macro -A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 # macro -A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE = 0x00000010 # macro -A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 # macro -A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 # macro -A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 # macro -A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 # macro -A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 # macro -A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 # macro -A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 # macro -REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 # macro -REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 = 0x00008102 # macro -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT = 0 # macro -REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 # macro -REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 # macro -REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 # macro -REG_A6XX_GRAS_SAMPLE_CNTL = 0x00008109 # macro -A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro -REG_A6XX_GRAS_LRZ_DEPTH_VIEW = 0x0000810a # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK = 0x000007ff # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT = 0 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK = 0x07ff0000 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT = 16 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK = 0xf0000000 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT = 28 # macro -REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b # macro -A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 # macro -A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 # macro -REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 # macro -REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 = 0x00008111 # macro -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK = 0xffffffff # macro -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT = 0 # macro -REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro -REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 # macro -REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 # macro -REG_A6XX_GRAS_2D_BLIT_CNTL = 0x00008400 # macro -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro -A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro -A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro -A6XX_GRAS_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro -A6XX_GRAS_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro -A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro -A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro -A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro -A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro -REG_A6XX_GRAS_2D_SRC_TL_X = 0x00008401 # macro -A6XX_GRAS_2D_SRC_TL_X__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_TL_X__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_BR_X = 0x00008402 # macro -A6XX_GRAS_2D_SRC_BR_X__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_BR_X__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_TL_Y = 0x00008403 # macro -A6XX_GRAS_2D_SRC_TL_Y__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_TL_Y__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_BR_Y = 0x00008404 # macro -A6XX_GRAS_2D_SRC_BR_Y__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_BR_Y__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_DST_TL = 0x00008405 # macro -A6XX_GRAS_2D_DST_TL_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_DST_TL_X__SHIFT = 0 # macro -A6XX_GRAS_2D_DST_TL_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_DST_TL_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_DST_BR = 0x00008406 # macro -A6XX_GRAS_2D_DST_BR_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_DST_BR_X__SHIFT = 0 # macro -A6XX_GRAS_2D_DST_BR_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_DST_BR_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 # macro -REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 = 0x0000840a # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT = 0 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 = 0x0000840b # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT = 0 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 # macro -A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 # macro -A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 # macro -REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 # macro -REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 # macro -# def REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0): # macro -# return (0x00008610+0x1*i0) -# def REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0): # macro -# return (0x00008614+0x1*i0) -# def REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0): # macro -# return (0x00008618+0x1*i0) -REG_A6XX_RB_BIN_CONTROL = 0x00008800 # macro -A6XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A6XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro -A6XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A6XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro -A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -REG_A7XX_RB_BIN_CONTROL = 0x00008800 # macro -A7XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A7XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro -A7XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A7XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro -A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -REG_A6XX_RB_RENDER_CNTL = 0x00008801 # macro -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 # macro -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 # macro -A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro -A6XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro -A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 # macro -A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 # macro -A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro -A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro -A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro -A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro -A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 # macro -A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 # macro -A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 # macro -REG_A7XX_RB_RENDER_CNTL = 0x00008801 # macro -A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro -A7XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro -A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro -A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro -A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro -A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro -REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 # macro -A7XX_GRAS_SU_RENDER_CNTL_BINNING = 0x00000080 # macro -REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 # macro -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro -A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro -REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 # macro -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_RB_SAMPLE_CONFIG = 0x00008804 # macro -A6XX_RB_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_RB_SAMPLE_LOCATION_0 = 0x00008805 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_RB_SAMPLE_LOCATION_1 = 0x00008806 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_RB_RENDER_CONTROL0 = 0x00008809 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL = 0x00000001 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID = 0x00000002 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE = 0x00000004 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL = 0x00000008 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID = 0x00000010 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE = 0x00000020 # macro -A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK = 0x000003c0 # macro -A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT = 6 # macro -A6XX_RB_RENDER_CONTROL0_UNK10 = 0x00000400 # macro -REG_A6XX_RB_RENDER_CONTROL1 = 0x0000880a # macro -A6XX_RB_RENDER_CONTROL1_SAMPLEMASK = 0x00000001 # macro -A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE = 0x00000002 # macro -A6XX_RB_RENDER_CONTROL1_FACENESS = 0x00000004 # macro -A6XX_RB_RENDER_CONTROL1_SAMPLEID = 0x00000008 # macro -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 # macro -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT = 4 # macro -A6XX_RB_RENDER_CONTROL1_CENTERRHW = 0x00000040 # macro -A6XX_RB_RENDER_CONTROL1_LINELENGTHEN = 0x00000080 # macro -A6XX_RB_RENDER_CONTROL1_FOVEATION = 0x00000100 # macro -REG_A6XX_RB_FS_OUTPUT_CNTL0 = 0x0000880b # macro -A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z = 0x00000002 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK = 0x00000004 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF = 0x00000008 # macro -REG_A6XX_RB_FS_OUTPUT_CNTL1 = 0x0000880c # macro -A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro -A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro -REG_A6XX_RB_RENDER_COMPONENTS = 0x0000880d # macro -A6XX_RB_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro -A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro -A6XX_RB_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro -A6XX_RB_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro -A6XX_RB_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro -A6XX_RB_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro -A6XX_RB_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro -A6XX_RB_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro -A6XX_RB_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_RB_DITHER_CNTL = 0x0000880e # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 # macro -REG_A6XX_RB_SRGB_CNTL = 0x0000880f # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro -REG_A6XX_RB_SAMPLE_CNTL = 0x00008810 # macro -A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro -REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 # macro -REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 # macro -REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 # macro -REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 # macro -REG_A6XX_RB_UNKNOWN_881A = 0x0000881a # macro -REG_A6XX_RB_UNKNOWN_881B = 0x0000881b # macro -REG_A6XX_RB_UNKNOWN_881C = 0x0000881c # macro -REG_A6XX_RB_UNKNOWN_881D = 0x0000881d # macro -REG_A6XX_RB_UNKNOWN_881E = 0x0000881e # macro -# def REG_A6XX_RB_MRT(i0): # macro -# return (0x00008820+0x8*i0) -A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 # macro -A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 # macro -A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 # macro -A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 # macro -A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 # macro -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 # macro -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro -A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro -A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro -A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro -A6XX_RB_MRT_PITCH__MASK = 0xffffffff # macro -A6XX_RB_MRT_PITCH__SHIFT = 0 # macro -A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff # macro -A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_RED_F32 = 0x00008860 # macro -A6XX_RB_BLEND_RED_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_RED_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_GREEN_F32 = 0x00008861 # macro -A6XX_RB_BLEND_GREEN_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_GREEN_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_BLUE_F32 = 0x00008862 # macro -A6XX_RB_BLEND_BLUE_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_BLUE_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_ALPHA_F32 = 0x00008863 # macro -A6XX_RB_BLEND_ALPHA_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_ALPHA_F32__SHIFT = 0 # macro -REG_A6XX_RB_ALPHA_CONTROL = 0x00008864 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK = 0x000000ff # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT = 0 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST = 0x00000100 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK = 0x00000e00 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT = 9 # macro -REG_A6XX_RB_BLEND_CNTL = 0x00008865 # macro -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro -A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 # macro -A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro -A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro -A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 # macro -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 # macro -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 # macro -REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 # macro -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_CNTL = 0x00008871 # macro -A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro -A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 # macro -A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c # macro -A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 # macro -A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro -A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 # macro -A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 # macro -REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 # macro -A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro -REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro -REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 # macro -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 # macro -A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 # macro -REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 # macro -A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff # macro -A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 # macro -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff # macro -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 # macro -REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM = 0x00008877 # macro -REG_A6XX_RB_Z_BOUNDS_MIN = 0x00008878 # macro -A6XX_RB_Z_BOUNDS_MIN__MASK = 0xffffffff # macro -A6XX_RB_Z_BOUNDS_MIN__SHIFT = 0 # macro -REG_A6XX_RB_Z_BOUNDS_MAX = 0x00008879 # macro -A6XX_RB_Z_BOUNDS_MAX__MASK = 0xffffffff # macro -A6XX_RB_Z_BOUNDS_MAX__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_CONTROL = 0x00008880 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE = 0x00000001 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF = 0x00000002 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_READ = 0x00000004 # macro -A6XX_RB_STENCIL_CONTROL_FUNC__MASK = 0x00000700 # macro -A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT = 8 # macro -A6XX_RB_STENCIL_CONTROL_FAIL__MASK = 0x00003800 # macro -A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT = 11 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS__MASK = 0x0001c000 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT = 14 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK = 0x000e0000 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT = 17 # macro -A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK = 0x00700000 # macro -A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT = 20 # macro -A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK = 0x03800000 # macro -A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT = 23 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK = 0x1c000000 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT = 26 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK = 0xe0000000 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT = 29 # macro -REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 # macro -A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 # macro -REG_A6XX_RB_STENCIL_INFO = 0x00008881 # macro -A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro -A6XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro -REG_A7XX_RB_STENCIL_INFO = 0x00008881 # macro -A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro -A7XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro -A7XX_RB_STENCIL_INFO_TILEMODE__MASK = 0x0000000c # macro -A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT = 2 # macro -REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 # macro -A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff # macro -A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 # macro -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff # macro -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 # macro -REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM = 0x00008886 # macro -REG_A6XX_RB_STENCILREF = 0x00008887 # macro -A6XX_RB_STENCILREF_REF__MASK = 0x000000ff # macro -A6XX_RB_STENCILREF_REF__SHIFT = 0 # macro -A6XX_RB_STENCILREF_BFREF__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILREF_BFREF__SHIFT = 8 # macro -REG_A6XX_RB_STENCILMASK = 0x00008888 # macro -A6XX_RB_STENCILMASK_MASK__MASK = 0x000000ff # macro -A6XX_RB_STENCILMASK_MASK__SHIFT = 0 # macro -A6XX_RB_STENCILMASK_BFMASK__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILMASK_BFMASK__SHIFT = 8 # macro -REG_A6XX_RB_STENCILWRMASK = 0x00008889 # macro -A6XX_RB_STENCILWRMASK_WRMASK__MASK = 0x000000ff # macro -A6XX_RB_STENCILWRMASK_WRMASK__SHIFT = 0 # macro -A6XX_RB_STENCILWRMASK_BFWRMASK__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT = 8 # macro -REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 # macro -A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_RB_SAMPLE_COUNT_CONTROL = 0x00008891 # macro -A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE = 0x00000001 # macro -A6XX_RB_SAMPLE_COUNT_CONTROL_COPY = 0x00000002 # macro -REG_A6XX_RB_LRZ_CNTL = 0x00008898 # macro -A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 # macro -REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 # macro -REG_A6XX_RB_Z_CLAMP_MIN = 0x000088c0 # macro -A6XX_RB_Z_CLAMP_MIN__MASK = 0xffffffff # macro -A6XX_RB_Z_CLAMP_MIN__SHIFT = 0 # macro -REG_A6XX_RB_Z_CLAMP_MAX = 0x000088c1 # macro -A6XX_RB_Z_CLAMP_MAX__MASK = 0xffffffff # macro -A6XX_RB_Z_CLAMP_MAX__SHIFT = 0 # macro -REG_A6XX_RB_UNKNOWN_88D0 = 0x000088d0 # macro -A6XX_RB_UNKNOWN_88D0_UNK0__MASK = 0x00001fff # macro -A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT = 0 # macro -A6XX_RB_UNKNOWN_88D0_UNK16__MASK = 0x07ff0000 # macro -A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_SCISSOR_TL = 0x000088d1 # macro -A6XX_RB_BLIT_SCISSOR_TL_X__MASK = 0x00003fff # macro -A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_RB_BLIT_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro -A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_SCISSOR_BR = 0x000088d2 # macro -A6XX_RB_BLIT_SCISSOR_BR_X__MASK = 0x00003fff # macro -A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_RB_BLIT_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro -A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A6XX_RB_BIN_CONTROL2 = 0x000088d3 # macro -A6XX_RB_BIN_CONTROL2_BINW__MASK = 0x0000003f # macro -A6XX_RB_BIN_CONTROL2_BINW__SHIFT = 0 # macro -A6XX_RB_BIN_CONTROL2_BINH__MASK = 0x00007f00 # macro -A6XX_RB_BIN_CONTROL2_BINH__SHIFT = 8 # macro -REG_A6XX_RB_WINDOW_OFFSET2 = 0x000088d4 # macro -A6XX_RB_WINDOW_OFFSET2_X__MASK = 0x00003fff # macro -A6XX_RB_WINDOW_OFFSET2_X__SHIFT = 0 # macro -A6XX_RB_WINDOW_OFFSET2_Y__MASK = 0x3fff0000 # macro -A6XX_RB_WINDOW_OFFSET2_Y__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL = 0x000088d5 # macro -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK = 0x00000018 # macro -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT = 3 # macro -REG_A6XX_RB_BLIT_BASE_GMEM = 0x000088d6 # macro -REG_A6XX_RB_BLIT_DST_INFO = 0x000088d7 # macro -A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK = 0x00000003 # macro -A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT = 0 # macro -A6XX_RB_BLIT_DST_INFO_FLAGS = 0x00000004 # macro -A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK = 0x00000018 # macro -A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT = 3 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK = 0x00000060 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT = 5 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK = 0x00007f80 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT = 7 # macro -A6XX_RB_BLIT_DST_INFO_UNK15 = 0x00008000 # macro -REG_A6XX_RB_BLIT_DST = 0x000088d8 # macro -REG_A6XX_RB_BLIT_DST_PITCH = 0x000088da # macro -A6XX_RB_BLIT_DST_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_BLIT_DST_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLIT_DST_ARRAY_PITCH = 0x000088db # macro -A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK = 0x1fffffff # macro -A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLIT_FLAG_DST = 0x000088dc # macro -REG_A6XX_RB_BLIT_FLAG_DST_PITCH = 0x000088de # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 = 0x000088df # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 = 0x000088e0 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 = 0x000088e1 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 = 0x000088e2 # macro -REG_A6XX_RB_BLIT_INFO = 0x000088e3 # macro -A6XX_RB_BLIT_INFO_UNK0 = 0x00000001 # macro -A6XX_RB_BLIT_INFO_GMEM = 0x00000002 # macro -A6XX_RB_BLIT_INFO_SAMPLE_0 = 0x00000004 # macro -A6XX_RB_BLIT_INFO_DEPTH = 0x00000008 # macro -A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK = 0x000000f0 # macro -A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT = 4 # macro -A6XX_RB_BLIT_INFO_LAST__MASK = 0x00000300 # macro -A6XX_RB_BLIT_INFO_LAST__SHIFT = 8 # macro -A6XX_RB_BLIT_INFO_BUFFER_ID__MASK = 0x0000f000 # macro -A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT = 12 # macro -REG_A7XX_RB_UNKNOWN_88E4 = 0x000088e4 # macro -A7XX_RB_UNKNOWN_88E4_UNK0 = 0x00000001 # macro -REG_A7XX_RB_CCU_CNTL2 = 0x000088e5 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK = 0x00000001 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT = 0 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK = 0x00000004 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT = 2 # macro -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT = 10 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK = 0x001ff000 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT = 12 # macro -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT = 21 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK = 0xff800000 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT = 23 # macro -REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 # macro -REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 # macro -REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_UNKNOWN_88F4 = 0x000088f4 # macro -REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 # macro -REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 # macro -REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -# def REG_A6XX_RB_MRT_FLAG_BUFFER(i0): # macro -# return (0x00008903+0x3*i0) -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_SAMPLE_COUNT_ADDR = 0x00008927 # macro -REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 # macro -REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 # macro -REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 # macro -REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 # macro -REG_A6XX_RB_2D_BLIT_CNTL = 0x00008c00 # macro -A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro -A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro -A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro -A6XX_RB_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro -A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro -A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro -A6XX_RB_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro -A6XX_RB_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro -A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro -A6XX_RB_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro -A6XX_RB_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro -A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro -A6XX_RB_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro -A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro -A6XX_RB_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro -REG_A6XX_RB_2D_UNKNOWN_8C01 = 0x00008c01 # macro -REG_A6XX_RB_2D_DST_INFO = 0x00008c17 # macro -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_RB_2D_DST_INFO_TILE_MODE__MASK = 0x00000300 # macro -A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT = 8 # macro -A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT = 10 # macro -A6XX_RB_2D_DST_INFO_FLAGS = 0x00001000 # macro -A6XX_RB_2D_DST_INFO_SRGB = 0x00002000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES__MASK = 0x0000c000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT = 14 # macro -A6XX_RB_2D_DST_INFO_FILTER = 0x00010000 # macro -A6XX_RB_2D_DST_INFO_UNK17 = 0x00020000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A6XX_RB_2D_DST_INFO_UNK19 = 0x00080000 # macro -A6XX_RB_2D_DST_INFO_UNK20 = 0x00100000 # macro -A6XX_RB_2D_DST_INFO_UNK21 = 0x00200000 # macro -A6XX_RB_2D_DST_INFO_UNK22 = 0x00400000 # macro -A6XX_RB_2D_DST_INFO_UNK23__MASK = 0x07800000 # macro -A6XX_RB_2D_DST_INFO_UNK23__SHIFT = 23 # macro -A6XX_RB_2D_DST_INFO_UNK28 = 0x10000000 # macro -REG_A6XX_RB_2D_DST = 0x00008c18 # macro -REG_A6XX_RB_2D_DST_PITCH = 0x00008c1a # macro -A6XX_RB_2D_DST_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_2D_DST_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_PLANE1 = 0x00008c1b # macro -REG_A6XX_RB_2D_DST_PLANE_PITCH = 0x00008c1d # macro -A6XX_RB_2D_DST_PLANE_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_2D_DST_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_PLANE2 = 0x00008c1e # macro -REG_A6XX_RB_2D_DST_FLAGS = 0x00008c20 # macro -REG_A6XX_RB_2D_DST_FLAGS_PITCH = 0x00008c22 # macro -A6XX_RB_2D_DST_FLAGS_PITCH__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_FLAGS_PLANE = 0x00008c23 # macro -REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH = 0x00008c25 # macro -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_SRC_SOLID_C0 = 0x00008c2c # macro -REG_A6XX_RB_2D_SRC_SOLID_C1 = 0x00008c2d # macro -REG_A6XX_RB_2D_SRC_SOLID_C2 = 0x00008c2e # macro -REG_A6XX_RB_2D_SRC_SOLID_C3 = 0x00008c2f # macro -REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 # macro -REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 # macro -REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 # macro -REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 # macro -REG_A7XX_RB_UNKNOWN_8E06 = 0x00008e06 # macro -REG_A6XX_RB_CCU_CNTL = 0x00008e07 # macro -A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro -A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 # macro -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 # macro -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 # macro -REG_A7XX_RB_CCU_CNTL = 0x00008e07 # macro -A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro -A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro -REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 # macro -A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 # macro -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro -A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro -A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 # macro -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 # macro -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 # macro -A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 # macro -A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 # macro -A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 # macro -REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 # macro -# def REG_A6XX_RB_PERFCTR_RB_SEL(i0): # macro -# return (0x00008e10+0x1*i0) -# def REG_A6XX_RB_PERFCTR_CCU_SEL(i0): # macro -# return (0x00008e18+0x1*i0) -REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 # macro -# def REG_A6XX_RB_PERFCTR_CMP_SEL(i0): # macro -# return (0x00008e2c+0x1*i0) -# def REG_A7XX_RB_PERFCTR_UFC_SEL(i0): # macro -# return (0x00008e30+0x1*i0) -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b # macro -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d # macro -REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE = 0x00008e50 # macro -REG_A6XX_RB_UNKNOWN_8E51 = 0x00008e51 # macro -REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 # macro -REG_A6XX_VPC_GS_PARAM = 0x00009100 # macro -A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 # macro -REG_A6XX_VPC_VS_CLIP_CNTL = 0x00009101 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_CLIP_CNTL = 0x00009102 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_CLIP_CNTL = 0x00009103 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_CLIP_CNTL_V2 = 0x00009311 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_CLIP_CNTL_V2 = 0x00009312 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_CLIP_CNTL_V2 = 0x00009313 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_LAYER_CNTL = 0x00009104 # macro -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_LAYER_CNTL = 0x00009105 # macro -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_LAYER_CNTL = 0x00009106 # macro -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_LAYER_CNTL_V2 = 0x00009314 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_LAYER_CNTL_V2 = 0x00009315 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_LAYER_CNTL_V2 = 0x00009316 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 # macro -A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 # macro -A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 # macro -REG_A6XX_VPC_POLYGON_MODE = 0x00009108 # macro -A6XX_VPC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A6XX_VPC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A7XX_VPC_PRIMITIVE_CNTL_0 = 0x00009109 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro -REG_A7XX_VPC_PRIMITIVE_CNTL_5 = 0x0000910a # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro -REG_A7XX_VPC_MULTIVIEW_MASK = 0x0000910b # macro -REG_A7XX_VPC_MULTIVIEW_CNTL = 0x0000910c # macro -A7XX_VPC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -# def REG_A6XX_VPC_VARYING_INTERP(i0): # macro -# return (0x00009200+0x1*i0) -# def REG_A6XX_VPC_VARYING_PS_REPL(i0): # macro -# return (0x00009208+0x1*i0) -REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 # macro -REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 # macro -# def REG_A6XX_VPC_VAR(i0): # macro -# return (0x00009212+0x1*i0) -REG_A6XX_VPC_SO_CNTL = 0x00009216 # macro -A6XX_VPC_SO_CNTL_ADDR__MASK = 0x000000ff # macro -A6XX_VPC_SO_CNTL_ADDR__SHIFT = 0 # macro -A6XX_VPC_SO_CNTL_RESET = 0x00010000 # macro -REG_A6XX_VPC_SO_PROG = 0x00009217 # macro -A6XX_VPC_SO_PROG_A_BUF__MASK = 0x00000003 # macro -A6XX_VPC_SO_PROG_A_BUF__SHIFT = 0 # macro -A6XX_VPC_SO_PROG_A_OFF__MASK = 0x000007fc # macro -A6XX_VPC_SO_PROG_A_OFF__SHIFT = 2 # macro -A6XX_VPC_SO_PROG_A_EN = 0x00000800 # macro -A6XX_VPC_SO_PROG_B_BUF__MASK = 0x00003000 # macro -A6XX_VPC_SO_PROG_B_BUF__SHIFT = 12 # macro -A6XX_VPC_SO_PROG_B_OFF__MASK = 0x007fc000 # macro -A6XX_VPC_SO_PROG_B_OFF__SHIFT = 14 # macro -A6XX_VPC_SO_PROG_B_EN = 0x00800000 # macro -REG_A6XX_VPC_SO_STREAM_COUNTS = 0x00009218 # macro -# def REG_A6XX_VPC_SO(i0): # macro -# return (0x0000921a+0x7*i0) -REG_A6XX_VPC_POINT_COORD_INVERT = 0x00009236 # macro -A6XX_VPC_POINT_COORD_INVERT_INVERT = 0x00000001 # macro -REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 # macro -REG_A6XX_VPC_VS_PACK = 0x00009301 # macro -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_VS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_VS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_VS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_GS_PACK = 0x00009302 # macro -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_GS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_GS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_GS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_DS_PACK = 0x00009303 # macro -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_DS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_DS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_DS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_CNTL_0 = 0x00009304 # macro -A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK = 0x000000ff # macro -A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT = 0 # macro -A6XX_VPC_CNTL_0_PRIMIDLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT = 8 # macro -A6XX_VPC_CNTL_0_VARYING = 0x00010000 # macro -A6XX_VPC_CNTL_0_VIEWIDLOC__MASK = 0xff000000 # macro -A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT = 24 # macro -REG_A6XX_VPC_SO_STREAM_CNTL = 0x00009305 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK = 0x00000007 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT = 0 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK = 0x00000038 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT = 3 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK = 0x000001c0 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT = 6 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK = 0x00000e00 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT = 9 # macro -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro -REG_A6XX_VPC_SO_DISABLE = 0x00009306 # macro -A6XX_VPC_SO_DISABLE_DISABLE = 0x00000001 # macro -REG_A7XX_VPC_POLYGON_MODE2 = 0x00009307 # macro -A7XX_VPC_POLYGON_MODE2_MODE__MASK = 0x00000003 # macro -A7XX_VPC_POLYGON_MODE2_MODE__SHIFT = 0 # macro -REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM = 0x00009308 # macro -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro -REG_A7XX_VPC_ATTR_BUF_BASE_GMEM = 0x00009309 # macro -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK = 0xffffffff # macro -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT = 0 # macro -REG_A7XX_PC_ATTR_BUF_SIZE_GMEM = 0x00009b09 # macro -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro -REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 # macro -REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 # macro -REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 # macro -REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 # macro -# def REG_A6XX_VPC_PERFCTR_VPC_SEL(i0): # macro -# return (0x00009604+0x1*i0) -# def REG_A7XX_VPC_PERFCTR_VPC_SEL(i0): # macro -# return (0x0000960b+0x1*i0) -REG_A6XX_PC_TESS_NUM_VERTEX = 0x00009800 # macro -REG_A6XX_PC_HS_INPUT_SIZE = 0x00009801 # macro -A6XX_PC_HS_INPUT_SIZE_SIZE__MASK = 0x000007ff # macro -A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT = 0 # macro -A6XX_PC_HS_INPUT_SIZE_UNK13 = 0x00002000 # macro -REG_A6XX_PC_TESS_CNTL = 0x00009802 # macro -A6XX_PC_TESS_CNTL_SPACING__MASK = 0x00000003 # macro -A6XX_PC_TESS_CNTL_SPACING__SHIFT = 0 # macro -A6XX_PC_TESS_CNTL_OUTPUT__MASK = 0x0000000c # macro -A6XX_PC_TESS_CNTL_OUTPUT__SHIFT = 2 # macro -REG_A6XX_PC_RESTART_INDEX = 0x00009803 # macro -REG_A6XX_PC_MODE_CNTL = 0x00009804 # macro -REG_A6XX_PC_POWER_CNTL = 0x00009805 # macro -REG_A6XX_PC_PS_CNTL = 0x00009806 # macro -A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 # macro -REG_A6XX_PC_SO_STREAM_CNTL = 0x00009808 # macro -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro -REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a # macro -A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro -REG_A6XX_PC_DRAW_CMD = 0x00009840 # macro -A6XX_PC_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_PC_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_PC_DISPATCH_CMD = 0x00009841 # macro -A6XX_PC_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_PC_EVENT_CMD = 0x00009842 # macro -A6XX_PC_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A6XX_PC_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A6XX_PC_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_PC_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_PC_MARKER = 0x00009880 # macro -REG_A6XX_PC_POLYGON_MODE = 0x00009981 # macro -A6XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A6XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A7XX_PC_POLYGON_MODE = 0x00009809 # macro -A7XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A7XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A6XX_PC_RASTER_CNTL = 0x00009980 # macro -A6XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro -A6XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro -A6XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro -REG_A7XX_PC_RASTER_CNTL = 0x00009107 # macro -A7XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro -A7XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro -A7XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro -REG_A7XX_PC_RASTER_CNTL_V2 = 0x00009317 # macro -A7XX_PC_RASTER_CNTL_V2_STREAM__MASK = 0x00000003 # macro -A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT = 0 # macro -A7XX_PC_RASTER_CNTL_V2_DISCARD = 0x00000004 # macro -REG_A7XX_PC_TESS_PARAM_SIZE = 0x00009885 # macro -REG_A7XX_PC_TESS_FACTOR_SIZE = 0x00009886 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_0 = 0x00009b00 # macro -A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro -A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro -A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro -A6XX_PC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro -REG_A6XX_PC_VS_OUT_CNTL = 0x00009b01 # macro -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_VS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_VS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_VS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_VS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_GS_OUT_CNTL = 0x00009b02 # macro -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_GS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_GS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_GS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_GS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_HS_OUT_CNTL = 0x00009b03 # macro -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_HS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_HS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_HS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_HS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_DS_OUT_CNTL = 0x00009b04 # macro -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_DS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_DS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_DS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_DS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_5 = 0x00009b05 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro -A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro -A6XX_PC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 # macro -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff # macro -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 # macro -REG_A6XX_PC_MULTIVIEW_CNTL = 0x00009b07 # macro -A6XX_PC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -REG_A6XX_PC_MULTIVIEW_MASK = 0x00009b08 # macro -REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 # macro -A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro -A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro -A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro -REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 # macro -REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 # macro -REG_A6XX_PC_DRAW_INDX_BASE = 0x00009e04 # macro -REG_A6XX_PC_DRAW_FIRST_INDX = 0x00009e06 # macro -REG_A6XX_PC_DRAW_MAX_INDICES = 0x00009e07 # macro -REG_A6XX_PC_TESSFACTOR_ADDR = 0x00009e08 # macro -REG_A7XX_PC_TESSFACTOR_ADDR = 0x00009810 # macro -REG_A6XX_PC_DRAW_INITIATOR = 0x00009e0b # macro -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK = 0x0000003f # macro -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT = 0 # macro -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK = 0x000000c0 # macro -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT = 6 # macro -A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK = 0x00000300 # macro -A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT = 8 # macro -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK = 0x00000c00 # macro -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT = 10 # macro -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK = 0x00003000 # macro -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT = 12 # macro -A6XX_PC_DRAW_INITIATOR_GS_ENABLE = 0x00010000 # macro -A6XX_PC_DRAW_INITIATOR_TESS_ENABLE = 0x00020000 # macro -REG_A6XX_PC_DRAW_NUM_INSTANCES = 0x00009e0c # macro -REG_A6XX_PC_DRAW_NUM_INDICES = 0x00009e0d # macro -REG_A6XX_PC_VSTREAM_CONTROL = 0x00009e11 # macro -A6XX_PC_VSTREAM_CONTROL_UNK0__MASK = 0x0000ffff # macro -A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT = 0 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK = 0x003f0000 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT = 16 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK = 0x07c00000 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT = 22 # macro -REG_A6XX_PC_BIN_PRIM_STRM = 0x00009e12 # macro -REG_A6XX_PC_BIN_DRAW_STRM = 0x00009e14 # macro -REG_A6XX_PC_VISIBILITY_OVERRIDE = 0x00009e1c # macro -A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE = 0x00000001 # macro -REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 # macro -# def REG_A6XX_PC_PERFCTR_PC_SEL(i0): # macro -# return (0x00009e34+0x1*i0) -# def REG_A7XX_PC_PERFCTR_PC_SEL(i0): # macro -# return (0x00009e42+0x1*i0) -REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 # macro -REG_A6XX_VFD_CONTROL_0 = 0x0000a000 # macro -A6XX_VFD_CONTROL_0_FETCH_CNT__MASK = 0x0000003f # macro -A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT = 0 # macro -A6XX_VFD_CONTROL_0_DECODE_CNT__MASK = 0x00003f00 # macro -A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_1 = 0x0000a001 # macro -A6XX_VFD_CONTROL_1_REGID4VTX__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT = 0 # macro -A6XX_VFD_CONTROL_1_REGID4INST__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_1_REGID4INST__SHIFT = 8 # macro -A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK = 0x00ff0000 # macro -A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT = 16 # macro -A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK = 0xff000000 # macro -A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT = 24 # macro -REG_A6XX_VFD_CONTROL_2 = 0x0000a002 # macro -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT = 0 # macro -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_3 = 0x0000a003 # macro -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT = 0 # macro -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT = 8 # macro -A6XX_VFD_CONTROL_3_REGID_TESSX__MASK = 0x00ff0000 # macro -A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT = 16 # macro -A6XX_VFD_CONTROL_3_REGID_TESSY__MASK = 0xff000000 # macro -A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT = 24 # macro -REG_A6XX_VFD_CONTROL_4 = 0x0000a004 # macro -A6XX_VFD_CONTROL_4_UNK0__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_4_UNK0__SHIFT = 0 # macro -REG_A6XX_VFD_CONTROL_5 = 0x0000a005 # macro -A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT = 0 # macro -A6XX_VFD_CONTROL_5_UNK8__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_5_UNK8__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_6 = 0x0000a006 # macro -A6XX_VFD_CONTROL_6_PRIMID4PSEN = 0x00000001 # macro -REG_A6XX_VFD_MODE_CNTL = 0x0000a007 # macro -A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK = 0x00000007 # macro -A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT = 0 # macro -REG_A6XX_VFD_MULTIVIEW_CNTL = 0x0000a008 # macro -A6XX_VFD_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -REG_A6XX_VFD_ADD_OFFSET = 0x0000a009 # macro -A6XX_VFD_ADD_OFFSET_VERTEX = 0x00000001 # macro -A6XX_VFD_ADD_OFFSET_INSTANCE = 0x00000002 # macro -REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e # macro -REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f # macro -# def REG_A6XX_VFD_FETCH(i0): # macro -# return (0x0000a010+0x4*i0) -# def REG_A6XX_VFD_DECODE(i0): # macro -# return (0x0000a090+0x2*i0) -A6XX_VFD_DECODE_INSTR_IDX__MASK = 0x0000001f # macro -A6XX_VFD_DECODE_INSTR_IDX__SHIFT = 0 # macro -A6XX_VFD_DECODE_INSTR_OFFSET__MASK = 0x0001ffe0 # macro -A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT = 5 # macro -A6XX_VFD_DECODE_INSTR_INSTANCED = 0x00020000 # macro -A6XX_VFD_DECODE_INSTR_FORMAT__MASK = 0x0ff00000 # macro -A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT = 20 # macro -A6XX_VFD_DECODE_INSTR_SWAP__MASK = 0x30000000 # macro -A6XX_VFD_DECODE_INSTR_SWAP__SHIFT = 28 # macro -A6XX_VFD_DECODE_INSTR_UNK30 = 0x40000000 # macro -A6XX_VFD_DECODE_INSTR_FLOAT = 0x80000000 # macro -# def REG_A6XX_VFD_DEST_CNTL(i0): # macro -# return (0x0000a0d0+0x1*i0) -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f # macro -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 # macro -A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 # macro -A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 # macro -REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 # macro -REG_A7XX_VFD_UNKNOWN_A600 = 0x0000a600 # macro -REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 # macro -# def REG_A6XX_VFD_PERFCTR_VFD_SEL(i0): # macro -# return (0x0000a610+0x1*i0) -# def REG_A7XX_VFD_PERFCTR_VFD_SEL(i0): # macro -# return (0x0000a610+0x1*i0) -REG_A6XX_SP_VS_CTRL_REG0 = 0x0000a800 # macro -A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_VS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_VS_CTRL_REG0_MERGEDREGS = 0x00100000 # macro -A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE = 0x00200000 # macro -REG_A6XX_SP_VS_BRANCH_COND = 0x0000a801 # macro -REG_A6XX_SP_VS_PRIMITIVE_CNTL = 0x0000a802 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_VS_OUT(i0): # macro -# return (0x0000a803+0x1*i0) -A6XX_SP_VS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_VS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_VS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_VS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_VS_VPC_DST(i0): # macro -# return (0x0000a813+0x1*i0) -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET = 0x0000a81b # macro -REG_A6XX_SP_VS_OBJ_START = 0x0000a81c # macro -REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e # macro -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_VS_PVT_MEM_ADDR = 0x0000a81f # macro -REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 # macro -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_VS_TEX_COUNT = 0x0000a822 # macro -REG_A6XX_SP_VS_CONFIG = 0x0000a823 # macro -A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_VS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_VS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_VS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_VS_INSTRLEN = 0x0000a824 # macro -REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET = 0x0000a825 # macro -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_VS_VGPR_CONFIG = 0x0000a82d # macro -REG_A6XX_SP_HS_CTRL_REG0 = 0x0000a830 # macro -A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_HS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_HS_WAVE_INPUT_SIZE = 0x0000a831 # macro -REG_A6XX_SP_HS_BRANCH_COND = 0x0000a832 # macro -REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET = 0x0000a833 # macro -REG_A6XX_SP_HS_OBJ_START = 0x0000a834 # macro -REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 # macro -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_HS_PVT_MEM_ADDR = 0x0000a837 # macro -REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 # macro -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_HS_TEX_COUNT = 0x0000a83a # macro -REG_A6XX_SP_HS_CONFIG = 0x0000a83b # macro -A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_HS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_HS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_HS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_HS_INSTRLEN = 0x0000a83c # macro -REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET = 0x0000a83d # macro -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_HS_VGPR_CONFIG = 0x0000a82f # macro -REG_A6XX_SP_DS_CTRL_REG0 = 0x0000a840 # macro -A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_DS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_DS_BRANCH_COND = 0x0000a841 # macro -REG_A6XX_SP_DS_PRIMITIVE_CNTL = 0x0000a842 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_DS_OUT(i0): # macro -# return (0x0000a843+0x1*i0) -A6XX_SP_DS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_DS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_DS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_DS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_DS_VPC_DST(i0): # macro -# return (0x0000a853+0x1*i0) -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET = 0x0000a85b # macro -REG_A6XX_SP_DS_OBJ_START = 0x0000a85c # macro -REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e # macro -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_DS_PVT_MEM_ADDR = 0x0000a85f # macro -REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 # macro -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_DS_TEX_COUNT = 0x0000a862 # macro -REG_A6XX_SP_DS_CONFIG = 0x0000a863 # macro -A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_DS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_DS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_DS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_DS_INSTRLEN = 0x0000a864 # macro -REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET = 0x0000a865 # macro -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_DS_VGPR_CONFIG = 0x0000a868 # macro -REG_A6XX_SP_GS_CTRL_REG0 = 0x0000a870 # macro -A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_GS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_GS_PRIM_SIZE = 0x0000a871 # macro -REG_A6XX_SP_GS_BRANCH_COND = 0x0000a872 # macro -REG_A6XX_SP_GS_PRIMITIVE_CNTL = 0x0000a873 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_GS_OUT(i0): # macro -# return (0x0000a874+0x1*i0) -A6XX_SP_GS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_GS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_GS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_GS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_GS_VPC_DST(i0): # macro -# return (0x0000a884+0x1*i0) -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET = 0x0000a88c # macro -REG_A6XX_SP_GS_OBJ_START = 0x0000a88d # macro -REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f # macro -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_GS_PVT_MEM_ADDR = 0x0000a890 # macro -REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 # macro -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_GS_TEX_COUNT = 0x0000a893 # macro -REG_A6XX_SP_GS_CONFIG = 0x0000a894 # macro -A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_GS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_GS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_GS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_GS_INSTRLEN = 0x0000a895 # macro -REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET = 0x0000a896 # macro -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_GS_VGPR_CONFIG = 0x0000a899 # macro -REG_A6XX_SP_VS_TEX_SAMP = 0x0000a8a0 # macro -REG_A6XX_SP_HS_TEX_SAMP = 0x0000a8a2 # macro -REG_A6XX_SP_DS_TEX_SAMP = 0x0000a8a4 # macro -REG_A6XX_SP_GS_TEX_SAMP = 0x0000a8a6 # macro -REG_A6XX_SP_VS_TEX_CONST = 0x0000a8a8 # macro -REG_A6XX_SP_HS_TEX_CONST = 0x0000a8aa # macro -REG_A6XX_SP_DS_TEX_CONST = 0x0000a8ac # macro -REG_A6XX_SP_GS_TEX_CONST = 0x0000a8ae # macro -REG_A6XX_SP_FS_CTRL_REG0 = 0x0000a980 # macro -A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_FS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro -A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro -A6XX_SP_FS_CTRL_REG0_UNK21 = 0x00200000 # macro -A6XX_SP_FS_CTRL_REG0_VARYING = 0x00400000 # macro -A6XX_SP_FS_CTRL_REG0_LODPIXMASK = 0x00800000 # macro -A6XX_SP_FS_CTRL_REG0_UNK24 = 0x01000000 # macro -A6XX_SP_FS_CTRL_REG0_UNK25 = 0x02000000 # macro -A6XX_SP_FS_CTRL_REG0_PIXLODENABLE = 0x04000000 # macro -A6XX_SP_FS_CTRL_REG0_UNK27 = 0x08000000 # macro -A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE = 0x10000000 # macro -A6XX_SP_FS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro -REG_A6XX_SP_FS_BRANCH_COND = 0x0000a981 # macro -REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET = 0x0000a982 # macro -REG_A6XX_SP_FS_OBJ_START = 0x0000a983 # macro -REG_A6XX_SP_FS_PVT_MEM_PARAM = 0x0000a985 # macro -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_FS_PVT_MEM_ADDR = 0x0000a986 # macro -REG_A6XX_SP_FS_PVT_MEM_SIZE = 0x0000a988 # macro -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_BLEND_CNTL = 0x0000a989 # macro -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro -A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 # macro -A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro -A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro -REG_A6XX_SP_SRGB_CNTL = 0x0000a98a # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro -REG_A6XX_SP_FS_RENDER_COMPONENTS = 0x0000a98b # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_SP_FS_OUTPUT_CNTL0 = 0x0000a98c # macro -A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK = 0x0000ff00 # macro -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT = 8 # macro -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT = 16 # macro -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK = 0xff000000 # macro -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT = 24 # macro -REG_A6XX_SP_FS_OUTPUT_CNTL1 = 0x0000a98d # macro -A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro -A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro -# def REG_A6XX_SP_FS_OUTPUT(i0): # macro -# return (0x0000a98e+0x1*i0) -A6XX_SP_FS_OUTPUT_REG_REGID__MASK = 0x000000ff # macro -A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT = 0 # macro -A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION = 0x00000100 # macro -# def REG_A6XX_SP_FS_MRT(i0): # macro -# return (0x0000a996+0x1*i0) -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_SP_FS_MRT_REG_COLOR_SINT = 0x00000100 # macro -A6XX_SP_FS_MRT_REG_COLOR_UINT = 0x00000200 # macro -A6XX_SP_FS_MRT_REG_UNK10 = 0x00000400 # macro -REG_A6XX_SP_FS_PREFETCH_CNTL = 0x0000a99e # macro -A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK = 0x00000007 # macro -A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT = 0 # macro -A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE = 0x00000008 # macro -A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD = 0x00000010 # macro -A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK = 0x00007fc0 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT = 6 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT = 16 # macro -# def REG_A6XX_SP_FS_PREFETCH(i0): # macro -# return (0x0000a99f+0x1*i0) -A6XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro -A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000780 # macro -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x0000f800 # macro -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 11 # macro -A6XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x003f0000 # macro -A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 16 # macro -A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x03c00000 # macro -A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 22 # macro -A6XX_SP_FS_PREFETCH_CMD_HALF = 0x04000000 # macro -A6XX_SP_FS_PREFETCH_CMD_UNK27 = 0x08000000 # macro -A6XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x10000000 # macro -A6XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0xe0000000 # macro -A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 29 # macro -# def REG_A7XX_SP_FS_PREFETCH(i0): # macro -# return (0x0000a99f+0x1*i0) -A7XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro -A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000380 # macro -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x00001c00 # macro -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 10 # macro -A7XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x0007e000 # macro -A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 13 # macro -A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x00780000 # macro -A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 19 # macro -A7XX_SP_FS_PREFETCH_CMD_HALF = 0x00800000 # macro -A7XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x02000000 # macro -A7XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0x3c000000 # macro -A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 26 # macro -# def REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0): # macro -# return (0x0000a9a3+0x1*i0) -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK = 0x0000ffff # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT = 0 # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK = 0xffff0000 # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT = 16 # macro -REG_A6XX_SP_FS_TEX_COUNT = 0x0000a9a7 # macro -REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 # macro -REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9a9 # macro -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A6XX_SP_CS_CTRL_REG0 = 0x0000a9b0 # macro -A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_CS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro -A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro -A6XX_SP_CS_CTRL_REG0_UNK21 = 0x00200000 # macro -A6XX_SP_CS_CTRL_REG0_UNK22 = 0x00400000 # macro -A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE = 0x00800000 # macro -A6XX_SP_CS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro -REG_A6XX_SP_CS_UNKNOWN_A9B1 = 0x0000a9b1 # macro -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK = 0x0000001f # macro -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT = 0 # macro -A6XX_SP_CS_UNKNOWN_A9B1_UNK5 = 0x00000020 # macro -A6XX_SP_CS_UNKNOWN_A9B1_UNK6 = 0x00000040 # macro -REG_A6XX_SP_CS_BRANCH_COND = 0x0000a9b2 # macro -REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET = 0x0000a9b3 # macro -REG_A6XX_SP_CS_OBJ_START = 0x0000a9b4 # macro -REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 # macro -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_CS_PVT_MEM_ADDR = 0x0000a9b7 # macro -REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 # macro -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_CS_TEX_COUNT = 0x0000a9ba # macro -REG_A6XX_SP_CS_CONFIG = 0x0000a9bb # macro -A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_CS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_CS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_CS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_CS_INSTRLEN = 0x0000a9bc # macro -REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9bd # macro -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be # macro -REG_A7XX_SP_CS_VGPR_CONFIG = 0x0000a9c5 # macro -REG_A6XX_SP_CS_CNTL_0 = 0x0000a9c2 # macro -A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro -A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro -A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro -A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro -REG_A6XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro -REG_A7XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000100 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 8 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000200 # macro -A7XX_SP_CS_CNTL_1_UNK15 = 0x00008000 # macro -REG_A6XX_SP_FS_TEX_SAMP = 0x0000a9e0 # macro -REG_A6XX_SP_CS_TEX_SAMP = 0x0000a9e2 # macro -REG_A6XX_SP_FS_TEX_CONST = 0x0000a9e4 # macro -REG_A6XX_SP_CS_TEX_CONST = 0x0000a9e6 # macro -# def REG_A6XX_SP_CS_BINDLESS_BASE(i0): # macro -# return (0x0000a9e8+0x2*i0) -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -# def REG_A7XX_SP_CS_BINDLESS_BASE(i0): # macro -# return (0x0000a9e8+0x2*i0) -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_SP_CS_IBO = 0x0000a9f2 # macro -REG_A6XX_SP_CS_IBO_COUNT = 0x0000aa00 # macro -REG_A7XX_SP_FS_VGPR_CONFIG = 0x0000aa01 # macro -REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL = 0x0000aa02 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED = 0x00000001 # macro -REG_A7XX_SP_PS_ALIASED_COMPONENTS = 0x0000aa03 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK = 0x0000000f # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT = 0 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT = 4 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT = 8 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT = 12 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT = 16 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT = 20 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT = 24 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 # macro -REG_A6XX_SP_MODE_CONTROL = 0x0000ab00 # macro -A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE = 0x00000001 # macro -A6XX_SP_MODE_CONTROL_ISAMMODE__MASK = 0x00000006 # macro -A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT = 1 # macro -A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE = 0x00000008 # macro -REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 # macro -REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 # macro -REG_A6XX_SP_FS_CONFIG = 0x0000ab04 # macro -A6XX_SP_FS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_FS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_FS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_FS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_FS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_FS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_FS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_FS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_FS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_FS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_FS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_FS_INSTRLEN = 0x0000ab05 # macro -# def REG_A6XX_SP_BINDLESS_BASE(i0): # macro -# return (0x0000ab10+0x2*i0) -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -# def REG_A7XX_SP_BINDLESS_BASE(i0): # macro -# return (0x0000ab0a+0x2*i0) -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_SP_IBO = 0x0000ab1a # macro -REG_A6XX_SP_IBO_COUNT = 0x0000ab20 # macro -REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 # macro -REG_A6XX_SP_2D_DST_FORMAT = 0x0000acc0 # macro -A6XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro -A6XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro -A6XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro -A6XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro -A6XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro -A6XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro -REG_A7XX_SP_2D_DST_FORMAT = 0x0000a9bf # macro -A7XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro -A7XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro -A7XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro -A7XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro -A7XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro -A7XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro -REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 # macro -REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 # macro -REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 # macro -REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 # macro -REG_A6XX_SP_FLOAT_CNTL = 0x0000ae04 # macro -A6XX_SP_FLOAT_CNTL_F16_NO_INF = 0x00000008 # macro -REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 # macro -REG_A7XX_SP_UNKNOWN_AE08 = 0x0000ae08 # macro -REG_A7XX_SP_UNKNOWN_AE09 = 0x0000ae09 # macro -REG_A7XX_SP_UNKNOWN_AE0A = 0x0000ae0a # macro -REG_A6XX_SP_PERFCTR_ENABLE = 0x0000ae0f # macro -A6XX_SP_PERFCTR_ENABLE_VS = 0x00000001 # macro -A6XX_SP_PERFCTR_ENABLE_HS = 0x00000002 # macro -A6XX_SP_PERFCTR_ENABLE_DS = 0x00000004 # macro -A6XX_SP_PERFCTR_ENABLE_GS = 0x00000008 # macro -A6XX_SP_PERFCTR_ENABLE_FS = 0x00000010 # macro -A6XX_SP_PERFCTR_ENABLE_CS = 0x00000020 # macro -# def REG_A6XX_SP_PERFCTR_SP_SEL(i0): # macro -# return (0x0000ae10+0x1*i0) -# def REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0): # macro -# return (0x0000ae60+0x1*i0) -REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a # macro -REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b # macro -REG_A7XX_SP_UNKNOWN_AE6C = 0x0000ae6c # macro -REG_A7XX_SP_READ_SEL = 0x0000ae6d # macro -A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 # macro -A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 # macro -A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 # macro -A7XX_SP_READ_SEL_PIPE__SHIFT = 16 # macro -A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 # macro -A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 # macro -A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 # macro -A7XX_SP_READ_SEL_USPTP__SHIFT = 4 # macro -A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f # macro -A7XX_SP_READ_SEL_SPTP__SHIFT = 0 # macro -REG_A7XX_SP_DBG_CNTL = 0x0000ae71 # macro -REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 # macro -# def REG_A7XX_SP_PERFCTR_SP_SEL(i0): # macro -# return (0x0000ae80+0x1*i0) -REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro -REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR = 0x0000b180 # macro -REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 # macro -REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 # macro -REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 # macro -REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 # macro -REG_A6XX_SP_TP_RAS_MSAA_CNTL = 0x0000b300 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c # macro -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT = 2 # macro -REG_A6XX_SP_TP_DEST_MSAA_CNTL = 0x0000b301 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR = 0x0000b302 # macro -REG_A6XX_SP_TP_SAMPLE_CONFIG = 0x0000b304 # macro -A6XX_SP_TP_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_SP_TP_SAMPLE_LOCATION_0 = 0x0000b305 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_SP_TP_SAMPLE_LOCATION_1 = 0x0000b306 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_SP_TP_WINDOW_OFFSET = 0x0000b307 # macro -A6XX_SP_TP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_SP_TP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_SP_TP_MODE_CNTL = 0x0000b309 # macro -A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK = 0x00000003 # macro -A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT = 0 # macro -A6XX_SP_TP_MODE_CNTL_UNK3__MASK = 0x000000fc # macro -A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT = 2 # macro -REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 # macro -REG_A6XX_SP_PS_2D_SRC_INFO = 0x0000b4c0 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro -A6XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro -A6XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro -A6XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro -REG_A6XX_SP_PS_2D_SRC_SIZE = 0x0000b4c1 # macro -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro -REG_A6XX_SP_PS_2D_SRC = 0x0000b4c2 # macro -REG_A6XX_SP_PS_2D_SRC_PITCH = 0x0000b4c4 # macro -A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro -A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro -A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro -REG_A7XX_SP_PS_2D_SRC_INFO = 0x0000b2c0 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro -A7XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro -A7XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro -A7XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro -REG_A7XX_SP_PS_2D_SRC_SIZE = 0x0000b2c1 # macro -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro -REG_A7XX_SP_PS_2D_SRC = 0x0000b2c2 # macro -REG_A7XX_SP_PS_2D_SRC_PITCH = 0x0000b2c4 # macro -A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro -A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro -A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE1 = 0x0000b4c5 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b4c7 # macro -A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro -A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE2 = 0x0000b4c8 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE1 = 0x0000b2c5 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b2c7 # macro -A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro -A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE2 = 0x0000b2c8 # macro -REG_A6XX_SP_PS_2D_SRC_FLAGS = 0x0000b4ca # macro -REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b4cc # macro -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro -REG_A7XX_SP_PS_2D_SRC_FLAGS = 0x0000b2ca # macro -REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b2cc # macro -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro -REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd # macro -REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce # macro -REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf # macro -REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 # macro -REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 # macro -A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd # macro -REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce # macro -REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf # macro -REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 # macro -REG_A7XX_SP_PS_2D_WINDOW_OFFSET = 0x0000b2d1 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT = 0 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A7XX_SP_PS_UNKNOWN_B2D2 = 0x0000b2d2 # macro -REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 # macro -A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 # macro -REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 # macro -REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 # macro -A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND = 0x00040000 # macro -REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 # macro -A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 # macro -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro -A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 # macro -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 # macro -A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 # macro -A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 # macro -REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro -# def REG_A6XX_TPL1_PERFCTR_TP_SEL(i0): # macro -# return (0x0000b610+0x1*i0) -# def REG_A7XX_TPL1_PERFCTR_TP_SEL(i0): # macro -# return (0x0000b610+0x1*i0) -REG_A6XX_HLSQ_VS_CNTL = 0x0000b800 # macro -A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_HS_CNTL = 0x0000b801 # macro -A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_DS_CNTL = 0x0000b802 # macro -A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_GS_CNTL = 0x0000b803 # macro -A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_VS_CNTL = 0x0000a827 # macro -A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_HS_CNTL = 0x0000a83f # macro -A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_DS_CNTL = 0x0000a867 # macro -A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_GS_CNTL = 0x0000a898 # macro -A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_UNKNOWN_A9AA = 0x0000a9aa # macro -A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE = 0x00000001 # macro -REG_A7XX_HLSQ_UNKNOWN_A9AC = 0x0000a9ac # macro -REG_A7XX_HLSQ_UNKNOWN_A9AD = 0x0000a9ad # macro -REG_A7XX_HLSQ_UNKNOWN_A9AE = 0x0000a9ae # macro -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK = 0x000000ff # macro -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT = 0 # macro -A7XX_HLSQ_UNKNOWN_A9AE_UNK8 = 0x00000100 # macro -A7XX_HLSQ_UNKNOWN_A9AE_UNK9 = 0x00000200 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 # macro -REG_A6XX_HLSQ_FS_CNTL_0 = 0x0000b980 # macro -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro -A6XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro -A6XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro -A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro -REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 # macro -REG_A6XX_HLSQ_CONTROL_1_REG = 0x0000b982 # macro -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro -REG_A6XX_HLSQ_CONTROL_2_REG = 0x0000b983 # macro -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_3_REG = 0x0000b984 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_4_REG = 0x0000b985 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_5_REG = 0x0000b986 # macro -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro -REG_A6XX_HLSQ_CS_CNTL = 0x0000b987 # macro -A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_CNTL_0 = 0x0000a9c6 # macro -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro -A7XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro -A7XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro -A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro -REG_A7XX_HLSQ_CONTROL_1_REG = 0x0000a9c7 # macro -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro -REG_A7XX_HLSQ_CONTROL_2_REG = 0x0000a9c8 # macro -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_3_REG = 0x0000a9c9 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_4_REG = 0x0000a9ca # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_5_REG = 0x0000a9cb # macro -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro -REG_A7XX_HLSQ_CS_CNTL = 0x0000a9cd # macro -A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_CS_NDRANGE_0 = 0x0000b990 # macro -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_HLSQ_CS_NDRANGE_1 = 0x0000b991 # macro -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_2 = 0x0000b992 # macro -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_3 = 0x0000b993 # macro -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_4 = 0x0000b994 # macro -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_5 = 0x0000b995 # macro -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_6 = 0x0000b996 # macro -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_CNTL_0 = 0x0000b997 # macro -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CS_CNTL_1 = 0x0000b998 # macro -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000b999 # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000b99a # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000b99b # macro -REG_A7XX_HLSQ_CS_NDRANGE_0 = 0x0000a9d4 # macro -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro -REG_A7XX_HLSQ_CS_NDRANGE_1 = 0x0000a9d5 # macro -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_2 = 0x0000a9d6 # macro -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_3 = 0x0000a9d7 # macro -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_4 = 0x0000a9d8 # macro -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_5 = 0x0000a9d9 # macro -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_6 = 0x0000a9da # macro -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000a9dc # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000a9dd # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000a9de # macro -REG_A7XX_HLSQ_CS_CNTL_1 = 0x0000a9db # macro -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A7XX_HLSQ_CS_CNTL_1_UNK11 = 0x00000800 # macro -A7XX_HLSQ_CS_CNTL_1_UNK22 = 0x00400000 # macro -A7XX_HLSQ_CS_CNTL_1_UNK26 = 0x04000000 # macro -A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK = 0x78000000 # macro -A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT = 27 # macro -REG_A7XX_HLSQ_CS_LOCAL_SIZE = 0x0000a9df # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK = 0x00000ffc # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT = 2 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK = 0x003ff000 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT = 12 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK = 0xffc00000 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 # macro -# def REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0): # macro -# return (0x0000b9c0+0x2*i0) -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 = 0x0000b9d0 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK = 0x0000001f # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 = 0x00000020 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 = 0x00000040 # macro -REG_A6XX_HLSQ_DRAW_CMD = 0x0000bb00 # macro -A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_HLSQ_DISPATCH_CMD = 0x0000bb01 # macro -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_HLSQ_EVENT_CMD = 0x0000bb02 # macro -A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A6XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_HLSQ_INVALIDATE_CMD = 0x0000bb08 # macro -A6XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro -A6XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro -A6XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro -A6XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro -A6XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST = 0x00080000 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST = 0x00000100 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x00003e00 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x0007c000 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 14 # macro -REG_A7XX_HLSQ_DRAW_CMD = 0x0000ab1c # macro -A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A7XX_HLSQ_DISPATCH_CMD = 0x0000ab1d # macro -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A7XX_HLSQ_EVENT_CMD = 0x0000ab1e # macro -A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A7XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A7XX_HLSQ_INVALIDATE_CMD = 0x0000ab1f # macro -A7XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro -A7XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro -A7XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro -A7XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro -A7XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x0001fe00 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x01fe0000 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 17 # macro -REG_A6XX_HLSQ_FS_CNTL = 0x0000bb10 # macro -A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_CNTL = 0x0000ab03 # macro -A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -# def REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0): # macro -# return (0x0000ab40+0x1*i0) -REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 # macro -A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 # macro -# def REG_A6XX_HLSQ_BINDLESS_BASE(i0): # macro -# return (0x0000bb20+0x2*i0) -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 # macro -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro -A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 # macro -REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 # macro -REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 # macro -REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 # macro -REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 # macro -# def REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0): # macro -# return (0x0000be10+0x1*i0) -REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro -REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 # macro -REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 # macro -REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 # macro -REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 # macro -REG_A6XX_CP_EVENT_START = 0x0000d600 # macro -A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_EVENT_END = 0x0000d601 # macro -A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_2D_EVENT_START = 0x0000d700 # macro -A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_2D_EVENT_END = 0x0000d701 # macro -A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 # macro -REG_A6XX_TEX_SAMP_0 = 0x00000000 # macro -A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 # macro -A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 # macro -A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 # macro -A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 # macro -A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 # macro -A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 # macro -A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 # macro -A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 # macro -A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 # macro -A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 # macro -A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 # macro -A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 # macro -A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 # macro -A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 # macro -A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 # macro -REG_A6XX_TEX_SAMP_1 = 0x00000001 # macro -A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 # macro -A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e # macro -A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 # macro -A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 # macro -A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 # macro -A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 # macro -A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 # macro -A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 # macro -A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 # macro -A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 # macro -REG_A6XX_TEX_SAMP_2 = 0x00000002 # macro -A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 # macro -A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 # macro -A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 # macro -A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 # macro -A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 # macro -REG_A6XX_TEX_SAMP_3 = 0x00000003 # macro -REG_A6XX_TEX_CONST_0 = 0x00000000 # macro -A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 # macro -A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 # macro -A6XX_TEX_CONST_0_SRGB = 0x00000004 # macro -A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 # macro -A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 # macro -A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 # macro -A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 # macro -A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 # macro -A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 # macro -A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 # macro -A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 # macro -A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 # macro -A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 # macro -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 # macro -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 # macro -A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 # macro -A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 # macro -A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 # macro -A6XX_TEX_CONST_0_FMT__SHIFT = 22 # macro -A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 # macro -A6XX_TEX_CONST_0_SWAP__SHIFT = 30 # macro -REG_A6XX_TEX_CONST_1 = 0x00000001 # macro -A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff # macro -A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 # macro -A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 # macro -A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 # macro -REG_A6XX_TEX_CONST_2 = 0x00000002 # macro -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 # macro -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 # macro -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 # macro -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 # macro -A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f # macro -A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 # macro -A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 # macro -A6XX_TEX_CONST_2_PITCH__SHIFT = 7 # macro -A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 # macro -A6XX_TEX_CONST_2_TYPE__SHIFT = 29 # macro -REG_A6XX_TEX_CONST_3 = 0x00000003 # macro -A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff # macro -A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 # macro -A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 # macro -A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 # macro -A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 # macro -A6XX_TEX_CONST_3_FLAG = 0x10000000 # macro -REG_A6XX_TEX_CONST_4 = 0x00000004 # macro -A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 # macro -A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 # macro -REG_A6XX_TEX_CONST_5 = 0x00000005 # macro -A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 # macro -A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 # macro -A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 # macro -REG_A6XX_TEX_CONST_6 = 0x00000006 # macro -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff # macro -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 # macro -A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 # macro -A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 # macro -REG_A6XX_TEX_CONST_7 = 0x00000007 # macro -A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 # macro -A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 # macro -REG_A6XX_TEX_CONST_8 = 0x00000008 # macro -A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 # macro -REG_A6XX_TEX_CONST_9 = 0x00000009 # macro -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_TEX_CONST_10 = 0x0000000a # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 # macro -REG_A6XX_TEX_CONST_11 = 0x0000000b # macro -REG_A6XX_TEX_CONST_12 = 0x0000000c # macro -REG_A6XX_TEX_CONST_13 = 0x0000000d # macro -REG_A6XX_TEX_CONST_14 = 0x0000000e # macro -REG_A6XX_TEX_CONST_15 = 0x0000000f # macro -REG_A6XX_UBO_0 = 0x00000000 # macro -A6XX_UBO_0_BASE_LO__MASK = 0xffffffff # macro -A6XX_UBO_0_BASE_LO__SHIFT = 0 # macro -REG_A6XX_UBO_1 = 0x00000001 # macro -A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff # macro -A6XX_UBO_1_BASE_HI__SHIFT = 0 # macro -A6XX_UBO_1_SIZE__MASK = 0xfffe0000 # macro -A6XX_UBO_1_SIZE__SHIFT = 17 # macro -REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 # macro -REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 # macro -REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 # macro -REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 # macro -REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 # macro -REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 # macro -REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 # macro -REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 # macro -REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 # macro -REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 # macro -REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 # macro -REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 # macro -REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 # macro -REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db # macro -REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 # macro -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 # macro -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 # macro -REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 # macro -REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 # macro - -# values for enumeration 'vgt_event_type' -vgt_event_type__enumvalues = { - 0: 'VS_DEALLOC', - 1: 'PS_DEALLOC', - 2: 'VS_DONE_TS', - 3: 'PS_DONE_TS', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'VIZQUERY_START', - 7: 'HLSQ_FLUSH', - 8: 'VIZQUERY_END', - 9: 'SC_WAIT_WC', - 9: 'WRITE_PRIMITIVE_COUNTS', - 11: 'START_PRIMITIVE_CTRS', - 12: 'STOP_PRIMITIVE_CTRS', - 13: 'RST_PIX_CNT', - 14: 'RST_VTX_CNT', - 15: 'TILE_FLUSH', - 16: 'STAT_EVENT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'ZPASS_DONE', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 22: 'RB_DONE_TS', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 27: 'VS_FETCH_DONE', - 28: 'FACENESS_FLUSH', - 8: 'WT_DONE_TS', - 13: 'START_FRAGMENT_CTRS', - 14: 'STOP_FRAGMENT_CTRS', - 15: 'START_COMPUTE_CTRS', - 16: 'STOP_COMPUTE_CTRS', - 17: 'FLUSH_SO_0', - 18: 'FLUSH_SO_1', - 19: 'FLUSH_SO_2', - 20: 'FLUSH_SO_3', - 24: 'PC_CCU_INVALIDATE_DEPTH', - 25: 'PC_CCU_INVALIDATE_COLOR', - 26: 'PC_CCU_RESOLVE_TS', - 28: 'PC_CCU_FLUSH_DEPTH_TS', - 29: 'PC_CCU_FLUSH_COLOR_TS', - 30: 'BLIT', - 36: 'LRZ_FLIP_BUFFER', - 37: 'LRZ_CLEAR', - 38: 'LRZ_FLUSH', - 39: 'BLIT_OP_FILL_2D', - 40: 'BLIT_OP_COPY_2D', - 40: 'UNK_40', - 42: 'BLIT_OP_SCALE_2D', - 43: 'CONTEXT_DONE_2D', - 44: 'UNK_2C', - 45: 'UNK_2D', - 49: 'CACHE_INVALIDATE', - 63: 'LABEL', - 1: 'DUMMY_EVENT', - 24: 'CCU_INVALIDATE_DEPTH', - 25: 'CCU_INVALIDATE_COLOR', - 26: 'CCU_RESOLVE_CLEAN', - 28: 'CCU_FLUSH_DEPTH', - 29: 'CCU_FLUSH_COLOR', - 30: 'CCU_RESOLVE', - 31: 'CCU_END_RESOLVE_GROUP', - 32: 'CCU_CLEAN_DEPTH', - 33: 'CCU_CLEAN_COLOR', - 48: 'CACHE_RESET', - 49: 'CACHE_CLEAN', - 50: 'CACHE_FLUSH7', - 51: 'CACHE_INVALIDATE7', -} -VS_DEALLOC = 0 -PS_DEALLOC = 1 -VS_DONE_TS = 2 -PS_DONE_TS = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -VIZQUERY_START = 7 -HLSQ_FLUSH = 7 -VIZQUERY_END = 8 -SC_WAIT_WC = 9 -WRITE_PRIMITIVE_COUNTS = 9 -START_PRIMITIVE_CTRS = 11 -STOP_PRIMITIVE_CTRS = 12 -RST_PIX_CNT = 13 -RST_VTX_CNT = 14 -TILE_FLUSH = 15 -STAT_EVENT = 16 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -ZPASS_DONE = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -RB_DONE_TS = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -VS_FETCH_DONE = 27 -FACENESS_FLUSH = 28 -WT_DONE_TS = 8 -START_FRAGMENT_CTRS = 13 -STOP_FRAGMENT_CTRS = 14 -START_COMPUTE_CTRS = 15 -STOP_COMPUTE_CTRS = 16 -FLUSH_SO_0 = 17 -FLUSH_SO_1 = 18 -FLUSH_SO_2 = 19 -FLUSH_SO_3 = 20 -PC_CCU_INVALIDATE_DEPTH = 24 -PC_CCU_INVALIDATE_COLOR = 25 -PC_CCU_RESOLVE_TS = 26 -PC_CCU_FLUSH_DEPTH_TS = 28 -PC_CCU_FLUSH_COLOR_TS = 29 -BLIT = 30 -LRZ_FLIP_BUFFER = 36 -LRZ_CLEAR = 37 -LRZ_FLUSH = 38 -BLIT_OP_FILL_2D = 39 -BLIT_OP_COPY_2D = 40 -UNK_40 = 40 -BLIT_OP_SCALE_2D = 42 -CONTEXT_DONE_2D = 43 -UNK_2C = 44 -UNK_2D = 45 -CACHE_INVALIDATE = 49 -LABEL = 63 -DUMMY_EVENT = 1 -CCU_INVALIDATE_DEPTH = 24 -CCU_INVALIDATE_COLOR = 25 -CCU_RESOLVE_CLEAN = 26 -CCU_FLUSH_DEPTH = 28 -CCU_FLUSH_COLOR = 29 -CCU_RESOLVE = 30 -CCU_END_RESOLVE_GROUP = 31 -CCU_CLEAN_DEPTH = 32 -CCU_CLEAN_COLOR = 33 -CACHE_RESET = 48 -CACHE_CLEAN = 49 -CACHE_FLUSH7 = 50 -CACHE_INVALIDATE7 = 51 -vgt_event_type = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_primtype' -pc_di_primtype__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST_PSIZE', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_LINELOOP', - 8: 'DI_PT_RECTLIST', - 9: 'DI_PT_POINTLIST', - 10: 'DI_PT_LINE_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRI_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 31: 'DI_PT_PATCHES0', - 32: 'DI_PT_PATCHES1', - 33: 'DI_PT_PATCHES2', - 34: 'DI_PT_PATCHES3', - 35: 'DI_PT_PATCHES4', - 36: 'DI_PT_PATCHES5', - 37: 'DI_PT_PATCHES6', - 38: 'DI_PT_PATCHES7', - 39: 'DI_PT_PATCHES8', - 40: 'DI_PT_PATCHES9', - 41: 'DI_PT_PATCHES10', - 42: 'DI_PT_PATCHES11', - 43: 'DI_PT_PATCHES12', - 44: 'DI_PT_PATCHES13', - 45: 'DI_PT_PATCHES14', - 46: 'DI_PT_PATCHES15', - 47: 'DI_PT_PATCHES16', - 48: 'DI_PT_PATCHES17', - 49: 'DI_PT_PATCHES18', - 50: 'DI_PT_PATCHES19', - 51: 'DI_PT_PATCHES20', - 52: 'DI_PT_PATCHES21', - 53: 'DI_PT_PATCHES22', - 54: 'DI_PT_PATCHES23', - 55: 'DI_PT_PATCHES24', - 56: 'DI_PT_PATCHES25', - 57: 'DI_PT_PATCHES26', - 58: 'DI_PT_PATCHES27', - 59: 'DI_PT_PATCHES28', - 60: 'DI_PT_PATCHES29', - 61: 'DI_PT_PATCHES30', - 62: 'DI_PT_PATCHES31', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST_PSIZE = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_LINELOOP = 7 -DI_PT_RECTLIST = 8 -DI_PT_POINTLIST = 9 -DI_PT_LINE_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRI_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_PATCHES0 = 31 -DI_PT_PATCHES1 = 32 -DI_PT_PATCHES2 = 33 -DI_PT_PATCHES3 = 34 -DI_PT_PATCHES4 = 35 -DI_PT_PATCHES5 = 36 -DI_PT_PATCHES6 = 37 -DI_PT_PATCHES7 = 38 -DI_PT_PATCHES8 = 39 -DI_PT_PATCHES9 = 40 -DI_PT_PATCHES10 = 41 -DI_PT_PATCHES11 = 42 -DI_PT_PATCHES12 = 43 -DI_PT_PATCHES13 = 44 -DI_PT_PATCHES14 = 45 -DI_PT_PATCHES15 = 46 -DI_PT_PATCHES16 = 47 -DI_PT_PATCHES17 = 48 -DI_PT_PATCHES18 = 49 -DI_PT_PATCHES19 = 50 -DI_PT_PATCHES20 = 51 -DI_PT_PATCHES21 = 52 -DI_PT_PATCHES22 = 53 -DI_PT_PATCHES23 = 54 -DI_PT_PATCHES24 = 55 -DI_PT_PATCHES25 = 56 -DI_PT_PATCHES26 = 57 -DI_PT_PATCHES27 = 58 -DI_PT_PATCHES28 = 59 -DI_PT_PATCHES29 = 60 -DI_PT_PATCHES30 = 61 -DI_PT_PATCHES31 = 62 -pc_di_primtype = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_src_sel' -pc_di_src_sel__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_AUTO_XFB', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_AUTO_XFB = 3 -pc_di_src_sel = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_face_cull_sel' -pc_di_face_cull_sel__enumvalues = { - 0: 'DI_FACE_CULL_NONE', - 1: 'DI_FACE_CULL_FETCH', - 2: 'DI_FACE_BACKFACE_CULL', - 3: 'DI_FACE_FRONTFACE_CULL', -} -DI_FACE_CULL_NONE = 0 -DI_FACE_CULL_FETCH = 1 -DI_FACE_BACKFACE_CULL = 2 -DI_FACE_FRONTFACE_CULL = 3 -pc_di_face_cull_sel = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_index_size' -pc_di_index_size__enumvalues = { - 0: 'INDEX_SIZE_IGN', - 0: 'INDEX_SIZE_16_BIT', - 1: 'INDEX_SIZE_32_BIT', - 2: 'INDEX_SIZE_8_BIT', - 0: 'INDEX_SIZE_INVALID', -} -INDEX_SIZE_IGN = 0 -INDEX_SIZE_16_BIT = 0 -INDEX_SIZE_32_BIT = 1 -INDEX_SIZE_8_BIT = 2 -INDEX_SIZE_INVALID = 0 -pc_di_index_size = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_vis_cull_mode' -pc_di_vis_cull_mode__enumvalues = { - 0: 'IGNORE_VISIBILITY', - 1: 'USE_VISIBILITY', -} -IGNORE_VISIBILITY = 0 -USE_VISIBILITY = 1 -pc_di_vis_cull_mode = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pm4_packet_type' -adreno_pm4_packet_type__enumvalues = { - 0: 'CP_TYPE0_PKT', - 1073741824: 'CP_TYPE1_PKT', - 2147483648: 'CP_TYPE2_PKT', - 3221225472: 'CP_TYPE3_PKT', - 1073741824: 'CP_TYPE4_PKT', - 1879048192: 'CP_TYPE7_PKT', -} -CP_TYPE0_PKT = 0 -CP_TYPE1_PKT = 1073741824 -CP_TYPE2_PKT = 2147483648 -CP_TYPE3_PKT = 3221225472 -CP_TYPE4_PKT = 1073741824 -CP_TYPE7_PKT = 1879048192 -adreno_pm4_packet_type = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pm4_type3_packets' -adreno_pm4_type3_packets__enumvalues = { - 72: 'CP_ME_INIT', - 16: 'CP_NOP', - 28: 'CP_PREEMPT_ENABLE', - 30: 'CP_PREEMPT_TOKEN', - 63: 'CP_INDIRECT_BUFFER', - 87: 'CP_INDIRECT_BUFFER_CHAIN', - 55: 'CP_INDIRECT_BUFFER_PFD', - 38: 'CP_WAIT_FOR_IDLE', - 60: 'CP_WAIT_REG_MEM', - 82: 'CP_WAIT_REG_EQ', - 83: 'CP_WAIT_REG_GTE', - 92: 'CP_WAIT_UNTIL_READ', - 93: 'CP_WAIT_IB_PFD_COMPLETE', - 33: 'CP_REG_RMW', - 47: 'CP_SET_BIN_DATA', - 47: 'CP_SET_BIN_DATA5', - 62: 'CP_REG_TO_MEM', - 61: 'CP_MEM_WRITE', - 79: 'CP_MEM_WRITE_CNTR', - 68: 'CP_COND_EXEC', - 69: 'CP_COND_WRITE', - 69: 'CP_COND_WRITE5', - 70: 'CP_EVENT_WRITE', - 70: 'CP_EVENT_WRITE7', - 88: 'CP_EVENT_WRITE_SHD', - 89: 'CP_EVENT_WRITE_CFL', - 91: 'CP_EVENT_WRITE_ZPD', - 49: 'CP_RUN_OPENCL', - 34: 'CP_DRAW_INDX', - 54: 'CP_DRAW_INDX_2', - 52: 'CP_DRAW_INDX_BIN', - 53: 'CP_DRAW_INDX_2_BIN', - 35: 'CP_VIZ_QUERY', - 37: 'CP_SET_STATE', - 45: 'CP_SET_CONSTANT', - 39: 'CP_IM_LOAD', - 43: 'CP_IM_LOAD_IMMEDIATE', - 46: 'CP_LOAD_CONSTANT_CONTEXT', - 59: 'CP_INVALIDATE_STATE', - 74: 'CP_SET_SHADER_BASES', - 80: 'CP_SET_BIN_MASK', - 81: 'CP_SET_BIN_SELECT', - 94: 'CP_CONTEXT_UPDATE', - 64: 'CP_INTERRUPT', - 44: 'CP_IM_STORE', - 75: 'CP_SET_DRAW_INIT_FLAGS', - 95: 'CP_SET_PROTECTED_MODE', - 111: 'CP_BOOTSTRAP_UCODE', - 48: 'CP_LOAD_STATE', - 48: 'CP_LOAD_STATE4', - 58: 'CP_COND_INDIRECT_BUFFER_PFE', - 50: 'CP_COND_INDIRECT_BUFFER_PFD', - 63: 'CP_INDIRECT_BUFFER_PFE', - 76: 'CP_SET_BIN', - 113: 'CP_TEST_TWO_MEMS', - 120: 'CP_REG_WR_NO_CTXT', - 17: 'CP_RECORD_PFP_TIMESTAMP', - 102: 'CP_SET_SECURE_MODE', - 19: 'CP_WAIT_FOR_ME', - 67: 'CP_SET_DRAW_STATE', - 56: 'CP_DRAW_INDX_OFFSET', - 40: 'CP_DRAW_INDIRECT', - 41: 'CP_DRAW_INDX_INDIRECT', - 42: 'CP_DRAW_INDIRECT_MULTI', - 36: 'CP_DRAW_AUTO', - 25: 'CP_DRAW_PRED_ENABLE_GLOBAL', - 26: 'CP_DRAW_PRED_ENABLE_LOCAL', - 78: 'CP_DRAW_PRED_SET', - 116: 'CP_WIDE_REG_WRITE', - 77: 'CP_SCRATCH_TO_REG', - 74: 'CP_REG_TO_SCRATCH', - 18: 'CP_WAIT_MEM_WRITES', - 71: 'CP_COND_REG_EXEC', - 66: 'CP_MEM_TO_REG', - 65: 'CP_EXEC_CS_INDIRECT', - 51: 'CP_EXEC_CS', - 80: 'CP_PERFCOUNTER_ACTION', - 83: 'CP_SMMU_TABLE_UPDATE', - 101: 'CP_SET_MARKER', - 86: 'CP_SET_PSEUDO_REG', - 92: 'CP_CONTEXT_REG_BUNCH', - 28: 'CP_YIELD_ENABLE', - 29: 'CP_SKIP_IB2_ENABLE_GLOBAL', - 35: 'CP_SKIP_IB2_ENABLE_LOCAL', - 53: 'CP_SET_SUBDRAW_SIZE', - 98: 'CP_WHERE_AM_I', - 100: 'CP_SET_VISIBILITY_OVERRIDE', - 105: 'CP_PREEMPT_ENABLE_GLOBAL', - 106: 'CP_PREEMPT_ENABLE_LOCAL', - 107: 'CP_CONTEXT_SWITCH_YIELD', - 108: 'CP_SET_RENDER_MODE', - 110: 'CP_COMPUTE_CHECKPOINT', - 115: 'CP_MEM_TO_MEM', - 44: 'CP_BLIT', - 57: 'CP_REG_TEST', - 99: 'CP_SET_MODE', - 50: 'CP_LOAD_STATE6_GEOM', - 52: 'CP_LOAD_STATE6_FRAG', - 54: 'CP_LOAD_STATE6', - 23: 'IN_IB_PREFETCH_END', - 31: 'IN_SUBBLK_PREFETCH', - 32: 'IN_INSTR_PREFETCH', - 71: 'IN_INSTR_MATCH', - 73: 'IN_CONST_PREFETCH', - 85: 'IN_INCR_UPDT_STATE', - 86: 'IN_INCR_UPDT_CONST', - 87: 'IN_INCR_UPDT_INSTR', - 4: 'PKT4', - 10: 'IN_IB_END', - 11: 'IN_GMU_INTERRUPT', - 15: 'IN_PREEMPT', - 76: 'CP_SCRATCH_WRITE', - 116: 'CP_REG_TO_MEM_OFFSET_MEM', - 114: 'CP_REG_TO_MEM_OFFSET_REG', - 20: 'CP_WAIT_MEM_GTE', - 112: 'CP_WAIT_TWO_REGS', - 117: 'CP_MEMCPY', - 46: 'CP_SET_BIN_DATA5_OFFSET', - 45: 'CP_SET_UNK_BIN_DATA', - 84: 'CP_CONTEXT_SWITCH', - 85: 'CP_SET_CTXSWITCH_IB', - 109: 'CP_REG_WRITE', - 80: 'CP_START_BIN', - 81: 'CP_END_BIN', - 108: 'CP_PREEMPT_DISABLE', - 20: 'CP_WAIT_TIMESTAMP', - 21: 'CP_GLOBAL_TIMESTAMP', - 22: 'CP_LOCAL_TIMESTAMP', - 23: 'CP_THREAD_CONTROL', - 24: 'CP_RESOURCE_LIST', - 27: 'CP_BV_BR_COUNT_OPS', - 28: 'CP_MODIFY_TIMESTAMP', - 93: 'CP_CONTEXT_REG_BUNCH2', - 73: 'CP_MEM_TO_SCRATCH_MEM', - 127: 'CP_FIXED_STRIDE_DRAW_TABLE', - 31: 'CP_RESET_CONTEXT_STATE', - 58: 'CP_CCHE_INVALIDATE', -} -CP_ME_INIT = 72 -CP_NOP = 16 -CP_PREEMPT_ENABLE = 28 -CP_PREEMPT_TOKEN = 30 -CP_INDIRECT_BUFFER = 63 -CP_INDIRECT_BUFFER_CHAIN = 87 -CP_INDIRECT_BUFFER_PFD = 55 -CP_WAIT_FOR_IDLE = 38 -CP_WAIT_REG_MEM = 60 -CP_WAIT_REG_EQ = 82 -CP_WAIT_REG_GTE = 83 -CP_WAIT_UNTIL_READ = 92 -CP_WAIT_IB_PFD_COMPLETE = 93 -CP_REG_RMW = 33 -CP_SET_BIN_DATA = 47 -CP_SET_BIN_DATA5 = 47 -CP_REG_TO_MEM = 62 -CP_MEM_WRITE = 61 -CP_MEM_WRITE_CNTR = 79 -CP_COND_EXEC = 68 -CP_COND_WRITE = 69 -CP_COND_WRITE5 = 69 -CP_EVENT_WRITE = 70 -CP_EVENT_WRITE7 = 70 -CP_EVENT_WRITE_SHD = 88 -CP_EVENT_WRITE_CFL = 89 -CP_EVENT_WRITE_ZPD = 91 -CP_RUN_OPENCL = 49 -CP_DRAW_INDX = 34 -CP_DRAW_INDX_2 = 54 -CP_DRAW_INDX_BIN = 52 -CP_DRAW_INDX_2_BIN = 53 -CP_VIZ_QUERY = 35 -CP_SET_STATE = 37 -CP_SET_CONSTANT = 45 -CP_IM_LOAD = 39 -CP_IM_LOAD_IMMEDIATE = 43 -CP_LOAD_CONSTANT_CONTEXT = 46 -CP_INVALIDATE_STATE = 59 -CP_SET_SHADER_BASES = 74 -CP_SET_BIN_MASK = 80 -CP_SET_BIN_SELECT = 81 -CP_CONTEXT_UPDATE = 94 -CP_INTERRUPT = 64 -CP_IM_STORE = 44 -CP_SET_DRAW_INIT_FLAGS = 75 -CP_SET_PROTECTED_MODE = 95 -CP_BOOTSTRAP_UCODE = 111 -CP_LOAD_STATE = 48 -CP_LOAD_STATE4 = 48 -CP_COND_INDIRECT_BUFFER_PFE = 58 -CP_COND_INDIRECT_BUFFER_PFD = 50 -CP_INDIRECT_BUFFER_PFE = 63 -CP_SET_BIN = 76 -CP_TEST_TWO_MEMS = 113 -CP_REG_WR_NO_CTXT = 120 -CP_RECORD_PFP_TIMESTAMP = 17 -CP_SET_SECURE_MODE = 102 -CP_WAIT_FOR_ME = 19 -CP_SET_DRAW_STATE = 67 -CP_DRAW_INDX_OFFSET = 56 -CP_DRAW_INDIRECT = 40 -CP_DRAW_INDX_INDIRECT = 41 -CP_DRAW_INDIRECT_MULTI = 42 -CP_DRAW_AUTO = 36 -CP_DRAW_PRED_ENABLE_GLOBAL = 25 -CP_DRAW_PRED_ENABLE_LOCAL = 26 -CP_DRAW_PRED_SET = 78 -CP_WIDE_REG_WRITE = 116 -CP_SCRATCH_TO_REG = 77 -CP_REG_TO_SCRATCH = 74 -CP_WAIT_MEM_WRITES = 18 -CP_COND_REG_EXEC = 71 -CP_MEM_TO_REG = 66 -CP_EXEC_CS_INDIRECT = 65 -CP_EXEC_CS = 51 -CP_PERFCOUNTER_ACTION = 80 -CP_SMMU_TABLE_UPDATE = 83 -CP_SET_MARKER = 101 -CP_SET_PSEUDO_REG = 86 -CP_CONTEXT_REG_BUNCH = 92 -CP_YIELD_ENABLE = 28 -CP_SKIP_IB2_ENABLE_GLOBAL = 29 -CP_SKIP_IB2_ENABLE_LOCAL = 35 -CP_SET_SUBDRAW_SIZE = 53 -CP_WHERE_AM_I = 98 -CP_SET_VISIBILITY_OVERRIDE = 100 -CP_PREEMPT_ENABLE_GLOBAL = 105 -CP_PREEMPT_ENABLE_LOCAL = 106 -CP_CONTEXT_SWITCH_YIELD = 107 -CP_SET_RENDER_MODE = 108 -CP_COMPUTE_CHECKPOINT = 110 -CP_MEM_TO_MEM = 115 -CP_BLIT = 44 -CP_REG_TEST = 57 -CP_SET_MODE = 99 -CP_LOAD_STATE6_GEOM = 50 -CP_LOAD_STATE6_FRAG = 52 -CP_LOAD_STATE6 = 54 -IN_IB_PREFETCH_END = 23 -IN_SUBBLK_PREFETCH = 31 -IN_INSTR_PREFETCH = 32 -IN_INSTR_MATCH = 71 -IN_CONST_PREFETCH = 73 -IN_INCR_UPDT_STATE = 85 -IN_INCR_UPDT_CONST = 86 -IN_INCR_UPDT_INSTR = 87 -PKT4 = 4 -IN_IB_END = 10 -IN_GMU_INTERRUPT = 11 -IN_PREEMPT = 15 -CP_SCRATCH_WRITE = 76 -CP_REG_TO_MEM_OFFSET_MEM = 116 -CP_REG_TO_MEM_OFFSET_REG = 114 -CP_WAIT_MEM_GTE = 20 -CP_WAIT_TWO_REGS = 112 -CP_MEMCPY = 117 -CP_SET_BIN_DATA5_OFFSET = 46 -CP_SET_UNK_BIN_DATA = 45 -CP_CONTEXT_SWITCH = 84 -CP_SET_CTXSWITCH_IB = 85 -CP_REG_WRITE = 109 -CP_START_BIN = 80 -CP_END_BIN = 81 -CP_PREEMPT_DISABLE = 108 -CP_WAIT_TIMESTAMP = 20 -CP_GLOBAL_TIMESTAMP = 21 -CP_LOCAL_TIMESTAMP = 22 -CP_THREAD_CONTROL = 23 -CP_RESOURCE_LIST = 24 -CP_BV_BR_COUNT_OPS = 27 -CP_MODIFY_TIMESTAMP = 28 -CP_CONTEXT_REG_BUNCH2 = 93 -CP_MEM_TO_SCRATCH_MEM = 73 -CP_FIXED_STRIDE_DRAW_TABLE = 127 -CP_RESET_CONTEXT_STATE = 31 -CP_CCHE_INVALIDATE = 58 -adreno_pm4_type3_packets = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_block' -adreno_state_block__enumvalues = { - 0: 'SB_VERT_TEX', - 1: 'SB_VERT_MIPADDR', - 2: 'SB_FRAG_TEX', - 3: 'SB_FRAG_MIPADDR', - 4: 'SB_VERT_SHADER', - 5: 'SB_GEOM_SHADER', - 6: 'SB_FRAG_SHADER', - 7: 'SB_COMPUTE_SHADER', -} -SB_VERT_TEX = 0 -SB_VERT_MIPADDR = 1 -SB_FRAG_TEX = 2 -SB_FRAG_MIPADDR = 3 -SB_VERT_SHADER = 4 -SB_GEOM_SHADER = 5 -SB_FRAG_SHADER = 6 -SB_COMPUTE_SHADER = 7 -adreno_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_type' -adreno_state_type__enumvalues = { - 0: 'ST_SHADER', - 1: 'ST_CONSTANTS', -} -ST_SHADER = 0 -ST_CONSTANTS = 1 -adreno_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_src' -adreno_state_src__enumvalues = { - 0: 'SS_DIRECT', - 2: 'SS_INVALID_ALL_IC', - 3: 'SS_INVALID_PART_IC', - 4: 'SS_INDIRECT', - 5: 'SS_INDIRECT_TCM', - 6: 'SS_INDIRECT_STM', -} -SS_DIRECT = 0 -SS_INVALID_ALL_IC = 2 -SS_INVALID_PART_IC = 3 -SS_INDIRECT = 4 -SS_INDIRECT_TCM = 5 -SS_INDIRECT_STM = 6 -adreno_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_block' -a4xx_state_block__enumvalues = { - 0: 'SB4_VS_TEX', - 1: 'SB4_HS_TEX', - 2: 'SB4_DS_TEX', - 3: 'SB4_GS_TEX', - 4: 'SB4_FS_TEX', - 5: 'SB4_CS_TEX', - 8: 'SB4_VS_SHADER', - 9: 'SB4_HS_SHADER', - 10: 'SB4_DS_SHADER', - 11: 'SB4_GS_SHADER', - 12: 'SB4_FS_SHADER', - 13: 'SB4_CS_SHADER', - 14: 'SB4_SSBO', - 15: 'SB4_CS_SSBO', -} -SB4_VS_TEX = 0 -SB4_HS_TEX = 1 -SB4_DS_TEX = 2 -SB4_GS_TEX = 3 -SB4_FS_TEX = 4 -SB4_CS_TEX = 5 -SB4_VS_SHADER = 8 -SB4_HS_SHADER = 9 -SB4_DS_SHADER = 10 -SB4_GS_SHADER = 11 -SB4_FS_SHADER = 12 -SB4_CS_SHADER = 13 -SB4_SSBO = 14 -SB4_CS_SSBO = 15 -a4xx_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_type' -a4xx_state_type__enumvalues = { - 0: 'ST4_SHADER', - 1: 'ST4_CONSTANTS', - 2: 'ST4_UBO', -} -ST4_SHADER = 0 -ST4_CONSTANTS = 1 -ST4_UBO = 2 -a4xx_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_src' -a4xx_state_src__enumvalues = { - 0: 'SS4_DIRECT', - 2: 'SS4_INDIRECT', -} -SS4_DIRECT = 0 -SS4_INDIRECT = 2 -a4xx_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_block' -a6xx_state_block__enumvalues = { - 0: 'SB6_VS_TEX', - 1: 'SB6_HS_TEX', - 2: 'SB6_DS_TEX', - 3: 'SB6_GS_TEX', - 4: 'SB6_FS_TEX', - 5: 'SB6_CS_TEX', - 8: 'SB6_VS_SHADER', - 9: 'SB6_HS_SHADER', - 10: 'SB6_DS_SHADER', - 11: 'SB6_GS_SHADER', - 12: 'SB6_FS_SHADER', - 13: 'SB6_CS_SHADER', - 14: 'SB6_IBO', - 15: 'SB6_CS_IBO', -} -SB6_VS_TEX = 0 -SB6_HS_TEX = 1 -SB6_DS_TEX = 2 -SB6_GS_TEX = 3 -SB6_FS_TEX = 4 -SB6_CS_TEX = 5 -SB6_VS_SHADER = 8 -SB6_HS_SHADER = 9 -SB6_DS_SHADER = 10 -SB6_GS_SHADER = 11 -SB6_FS_SHADER = 12 -SB6_CS_SHADER = 13 -SB6_IBO = 14 -SB6_CS_IBO = 15 -a6xx_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_type' -a6xx_state_type__enumvalues = { - 0: 'ST6_SHADER', - 1: 'ST6_CONSTANTS', - 2: 'ST6_UBO', - 3: 'ST6_IBO', -} -ST6_SHADER = 0 -ST6_CONSTANTS = 1 -ST6_UBO = 2 -ST6_IBO = 3 -a6xx_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_src' -a6xx_state_src__enumvalues = { - 0: 'SS6_DIRECT', - 1: 'SS6_BINDLESS', - 2: 'SS6_INDIRECT', - 3: 'SS6_UBO', -} -SS6_DIRECT = 0 -SS6_BINDLESS = 1 -SS6_INDIRECT = 2 -SS6_UBO = 3 -a6xx_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_index_size' -a4xx_index_size__enumvalues = { - 0: 'INDEX4_SIZE_8_BIT', - 1: 'INDEX4_SIZE_16_BIT', - 2: 'INDEX4_SIZE_32_BIT', -} -INDEX4_SIZE_8_BIT = 0 -INDEX4_SIZE_16_BIT = 1 -INDEX4_SIZE_32_BIT = 2 -a4xx_index_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_patch_type' -a6xx_patch_type__enumvalues = { - 0: 'TESS_QUADS', - 1: 'TESS_TRIANGLES', - 2: 'TESS_ISOLINES', -} -TESS_QUADS = 0 -TESS_TRIANGLES = 1 -TESS_ISOLINES = 2 -a6xx_patch_type = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_draw_indirect_opcode' -a6xx_draw_indirect_opcode__enumvalues = { - 2: 'INDIRECT_OP_NORMAL', - 4: 'INDIRECT_OP_INDEXED', - 6: 'INDIRECT_OP_INDIRECT_COUNT', - 7: 'INDIRECT_OP_INDIRECT_COUNT_INDEXED', -} -INDIRECT_OP_NORMAL = 2 -INDIRECT_OP_INDEXED = 4 -INDIRECT_OP_INDIRECT_COUNT = 6 -INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7 -a6xx_draw_indirect_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'cp_draw_pred_src' -cp_draw_pred_src__enumvalues = { - 5: 'PRED_SRC_MEM', -} -PRED_SRC_MEM = 5 -cp_draw_pred_src = ctypes.c_uint32 # enum - -# values for enumeration 'cp_draw_pred_test' -cp_draw_pred_test__enumvalues = { - 0: 'NE_0_PASS', - 1: 'EQ_0_PASS', -} -NE_0_PASS = 0 -EQ_0_PASS = 1 -cp_draw_pred_test = ctypes.c_uint32 # enum - -# values for enumeration 'cp_cond_function' -cp_cond_function__enumvalues = { - 0: 'WRITE_ALWAYS', - 1: 'WRITE_LT', - 2: 'WRITE_LE', - 3: 'WRITE_EQ', - 4: 'WRITE_NE', - 5: 'WRITE_GE', - 6: 'WRITE_GT', -} -WRITE_ALWAYS = 0 -WRITE_LT = 1 -WRITE_LE = 2 -WRITE_EQ = 3 -WRITE_NE = 4 -WRITE_GE = 5 -WRITE_GT = 6 -cp_cond_function = ctypes.c_uint32 # enum - -# values for enumeration 'poll_memory_type' -poll_memory_type__enumvalues = { - 0: 'POLL_REGISTER', - 1: 'POLL_MEMORY', - 2: 'POLL_SCRATCH', - 3: 'POLL_ON_CHIP', -} -POLL_REGISTER = 0 -POLL_MEMORY = 1 -POLL_SCRATCH = 2 -POLL_ON_CHIP = 3 -poll_memory_type = ctypes.c_uint32 # enum - -# values for enumeration 'render_mode_cmd' -render_mode_cmd__enumvalues = { - 1: 'BYPASS', - 2: 'BINNING', - 3: 'GMEM', - 5: 'BLIT2D', - 7: 'BLIT2DSCALE', - 8: 'END2D', -} -BYPASS = 1 -BINNING = 2 -GMEM = 3 -BLIT2D = 5 -BLIT2DSCALE = 7 -END2D = 8 -render_mode_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'event_write_src' -event_write_src__enumvalues = { - 0: 'EV_WRITE_USER_32B', - 1: 'EV_WRITE_USER_64B', - 2: 'EV_WRITE_TIMESTAMP_SUM', - 3: 'EV_WRITE_ALWAYSON', - 4: 'EV_WRITE_REGS_CONTENT', -} -EV_WRITE_USER_32B = 0 -EV_WRITE_USER_64B = 1 -EV_WRITE_TIMESTAMP_SUM = 2 -EV_WRITE_ALWAYSON = 3 -EV_WRITE_REGS_CONTENT = 4 -event_write_src = ctypes.c_uint32 # enum - -# values for enumeration 'event_write_dst' -event_write_dst__enumvalues = { - 0: 'EV_DST_RAM', - 1: 'EV_DST_ONCHIP', -} -EV_DST_RAM = 0 -EV_DST_ONCHIP = 1 -event_write_dst = ctypes.c_uint32 # enum - -# values for enumeration 'cp_blit_cmd' -cp_blit_cmd__enumvalues = { - 0: 'BLIT_OP_FILL', - 1: 'BLIT_OP_COPY', - 3: 'BLIT_OP_SCALE', -} -BLIT_OP_FILL = 0 -BLIT_OP_COPY = 1 -BLIT_OP_SCALE = 3 -cp_blit_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_marker' -a6xx_marker__enumvalues = { - 1: 'RM6_BYPASS', - 2: 'RM6_BINNING', - 4: 'RM6_GMEM', - 5: 'RM6_ENDVIS', - 6: 'RM6_RESOLVE', - 7: 'RM6_YIELD', - 8: 'RM6_COMPUTE', - 12: 'RM6_BLIT2DSCALE', - 13: 'RM6_IB1LIST_START', - 14: 'RM6_IB1LIST_END', - 256: 'RM6_IFPC_ENABLE', - 257: 'RM6_IFPC_DISABLE', -} -RM6_BYPASS = 1 -RM6_BINNING = 2 -RM6_GMEM = 4 -RM6_ENDVIS = 5 -RM6_RESOLVE = 6 -RM6_YIELD = 7 -RM6_COMPUTE = 8 -RM6_BLIT2DSCALE = 12 -RM6_IB1LIST_START = 13 -RM6_IB1LIST_END = 14 -RM6_IFPC_ENABLE = 256 -RM6_IFPC_DISABLE = 257 -a6xx_marker = ctypes.c_uint32 # enum - -# values for enumeration 'pseudo_reg' -pseudo_reg__enumvalues = { - 0: 'SMMU_INFO', - 1: 'NON_SECURE_SAVE_ADDR', - 2: 'SECURE_SAVE_ADDR', - 3: 'NON_PRIV_SAVE_ADDR', - 4: 'COUNTER', - 8: 'DRAW_STRM_ADDRESS', - 9: 'DRAW_STRM_SIZE_ADDRESS', - 10: 'PRIM_STRM_ADDRESS', - 11: 'UNK_STRM_ADDRESS', - 12: 'UNK_STRM_SIZE_ADDRESS', - 16: 'BINDLESS_BASE_0_ADDR', - 17: 'BINDLESS_BASE_1_ADDR', - 18: 'BINDLESS_BASE_2_ADDR', - 19: 'BINDLESS_BASE_3_ADDR', - 20: 'BINDLESS_BASE_4_ADDR', - 21: 'BINDLESS_BASE_5_ADDR', - 22: 'BINDLESS_BASE_6_ADDR', -} -SMMU_INFO = 0 -NON_SECURE_SAVE_ADDR = 1 -SECURE_SAVE_ADDR = 2 -NON_PRIV_SAVE_ADDR = 3 -COUNTER = 4 -DRAW_STRM_ADDRESS = 8 -DRAW_STRM_SIZE_ADDRESS = 9 -PRIM_STRM_ADDRESS = 10 -UNK_STRM_ADDRESS = 11 -UNK_STRM_SIZE_ADDRESS = 12 -BINDLESS_BASE_0_ADDR = 16 -BINDLESS_BASE_1_ADDR = 17 -BINDLESS_BASE_2_ADDR = 18 -BINDLESS_BASE_3_ADDR = 19 -BINDLESS_BASE_4_ADDR = 20 -BINDLESS_BASE_5_ADDR = 21 -BINDLESS_BASE_6_ADDR = 22 -pseudo_reg = ctypes.c_uint32 # enum - -# values for enumeration 'source_type' -source_type__enumvalues = { - 0: 'SOURCE_REG', - 1: 'SOURCE_SCRATCH_MEM', -} -SOURCE_REG = 0 -SOURCE_SCRATCH_MEM = 1 -source_type = ctypes.c_uint32 # enum - -# values for enumeration 'compare_mode' -compare_mode__enumvalues = { - 1: 'PRED_TEST', - 2: 'REG_COMPARE', - 3: 'RENDER_MODE', - 4: 'REG_COMPARE_IMM', - 5: 'THREAD_MODE', -} -PRED_TEST = 1 -REG_COMPARE = 2 -RENDER_MODE = 3 -REG_COMPARE_IMM = 4 -THREAD_MODE = 5 -compare_mode = ctypes.c_uint32 # enum - -# values for enumeration 'ctxswitch_ib' -ctxswitch_ib__enumvalues = { - 0: 'RESTORE_IB', - 1: 'YIELD_RESTORE_IB', - 2: 'SAVE_IB', - 3: 'RB_SAVE_IB', -} -RESTORE_IB = 0 -YIELD_RESTORE_IB = 1 -SAVE_IB = 2 -RB_SAVE_IB = 3 -ctxswitch_ib = ctypes.c_uint32 # enum - -# values for enumeration 'reg_tracker' -reg_tracker__enumvalues = { - 1: 'TRACK_CNTL_REG', - 2: 'TRACK_RENDER_CNTL', - 4: 'UNK_EVENT_WRITE', - 8: 'TRACK_LRZ', -} -TRACK_CNTL_REG = 1 -TRACK_RENDER_CNTL = 2 -UNK_EVENT_WRITE = 4 -TRACK_LRZ = 8 -reg_tracker = ctypes.c_uint32 # enum - -# values for enumeration 'ts_wait_value_src' -ts_wait_value_src__enumvalues = { - 0: 'TS_WAIT_GE_32B', - 1: 'TS_WAIT_GE_64B', - 2: 'TS_WAIT_GE_TIMESTAMP_SUM', -} -TS_WAIT_GE_32B = 0 -TS_WAIT_GE_64B = 1 -TS_WAIT_GE_TIMESTAMP_SUM = 2 -ts_wait_value_src = ctypes.c_uint32 # enum - -# values for enumeration 'ts_wait_type' -ts_wait_type__enumvalues = { - 0: 'TS_WAIT_RAM', - 1: 'TS_WAIT_ONCHIP', -} -TS_WAIT_RAM = 0 -TS_WAIT_ONCHIP = 1 -ts_wait_type = ctypes.c_uint32 # enum - -# values for enumeration 'pipe_count_op' -pipe_count_op__enumvalues = { - 1: 'PIPE_CLEAR_BV_BR', - 2: 'PIPE_SET_BR_OFFSET', - 3: 'PIPE_BR_WAIT_FOR_BV', - 4: 'PIPE_BV_WAIT_FOR_BR', -} -PIPE_CLEAR_BV_BR = 1 -PIPE_SET_BR_OFFSET = 2 -PIPE_BR_WAIT_FOR_BV = 3 -PIPE_BV_WAIT_FOR_BR = 4 -pipe_count_op = ctypes.c_uint32 # enum - -# values for enumeration 'timestamp_op' -timestamp_op__enumvalues = { - 0: 'MODIFY_TIMESTAMP_CLEAR', - 1: 'MODIFY_TIMESTAMP_ADD_GLOBAL', - 2: 'MODIFY_TIMESTAMP_ADD_LOCAL', -} -MODIFY_TIMESTAMP_CLEAR = 0 -MODIFY_TIMESTAMP_ADD_GLOBAL = 1 -MODIFY_TIMESTAMP_ADD_LOCAL = 2 -timestamp_op = ctypes.c_uint32 # enum - -# values for enumeration 'cp_thread' -cp_thread__enumvalues = { - 1: 'CP_SET_THREAD_BR', - 2: 'CP_SET_THREAD_BV', - 3: 'CP_SET_THREAD_BOTH', -} -CP_SET_THREAD_BR = 1 -CP_SET_THREAD_BV = 2 -CP_SET_THREAD_BOTH = 3 -cp_thread = ctypes.c_uint32 # enum - -# values for enumeration 'chip' -chip__enumvalues = { - 2: 'A2XX', - 3: 'A3XX', - 4: 'A4XX', - 5: 'A5XX', - 6: 'A6XX', - 7: 'A7XX', -} -A2XX = 2 -A3XX = 3 -A4XX = 4 -A5XX = 5 -A6XX = 6 -A7XX = 7 -chip = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pa_su_sc_draw' -adreno_pa_su_sc_draw__enumvalues = { - 0: 'PC_DRAW_POINTS', - 1: 'PC_DRAW_LINES', - 2: 'PC_DRAW_TRIANGLES', -} -PC_DRAW_POINTS = 0 -PC_DRAW_LINES = 1 -PC_DRAW_TRIANGLES = 2 -adreno_pa_su_sc_draw = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_compare_func' -adreno_compare_func__enumvalues = { - 0: 'FUNC_NEVER', - 1: 'FUNC_LESS', - 2: 'FUNC_EQUAL', - 3: 'FUNC_LEQUAL', - 4: 'FUNC_GREATER', - 5: 'FUNC_NOTEQUAL', - 6: 'FUNC_GEQUAL', - 7: 'FUNC_ALWAYS', -} -FUNC_NEVER = 0 -FUNC_LESS = 1 -FUNC_EQUAL = 2 -FUNC_LEQUAL = 3 -FUNC_GREATER = 4 -FUNC_NOTEQUAL = 5 -FUNC_GEQUAL = 6 -FUNC_ALWAYS = 7 -adreno_compare_func = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_stencil_op' -adreno_stencil_op__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_REPLACE', - 3: 'STENCIL_INCR_CLAMP', - 4: 'STENCIL_DECR_CLAMP', - 5: 'STENCIL_INVERT', - 6: 'STENCIL_INCR_WRAP', - 7: 'STENCIL_DECR_WRAP', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_REPLACE = 2 -STENCIL_INCR_CLAMP = 3 -STENCIL_DECR_CLAMP = 4 -STENCIL_INVERT = 5 -STENCIL_INCR_WRAP = 6 -STENCIL_DECR_WRAP = 7 -adreno_stencil_op = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_blend_factor' -adreno_rb_blend_factor__enumvalues = { - 0: 'FACTOR_ZERO', - 1: 'FACTOR_ONE', - 4: 'FACTOR_SRC_COLOR', - 5: 'FACTOR_ONE_MINUS_SRC_COLOR', - 6: 'FACTOR_SRC_ALPHA', - 7: 'FACTOR_ONE_MINUS_SRC_ALPHA', - 8: 'FACTOR_DST_COLOR', - 9: 'FACTOR_ONE_MINUS_DST_COLOR', - 10: 'FACTOR_DST_ALPHA', - 11: 'FACTOR_ONE_MINUS_DST_ALPHA', - 12: 'FACTOR_CONSTANT_COLOR', - 13: 'FACTOR_ONE_MINUS_CONSTANT_COLOR', - 14: 'FACTOR_CONSTANT_ALPHA', - 15: 'FACTOR_ONE_MINUS_CONSTANT_ALPHA', - 16: 'FACTOR_SRC_ALPHA_SATURATE', - 20: 'FACTOR_SRC1_COLOR', - 21: 'FACTOR_ONE_MINUS_SRC1_COLOR', - 22: 'FACTOR_SRC1_ALPHA', - 23: 'FACTOR_ONE_MINUS_SRC1_ALPHA', -} -FACTOR_ZERO = 0 -FACTOR_ONE = 1 -FACTOR_SRC_COLOR = 4 -FACTOR_ONE_MINUS_SRC_COLOR = 5 -FACTOR_SRC_ALPHA = 6 -FACTOR_ONE_MINUS_SRC_ALPHA = 7 -FACTOR_DST_COLOR = 8 -FACTOR_ONE_MINUS_DST_COLOR = 9 -FACTOR_DST_ALPHA = 10 -FACTOR_ONE_MINUS_DST_ALPHA = 11 -FACTOR_CONSTANT_COLOR = 12 -FACTOR_ONE_MINUS_CONSTANT_COLOR = 13 -FACTOR_CONSTANT_ALPHA = 14 -FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15 -FACTOR_SRC_ALPHA_SATURATE = 16 -FACTOR_SRC1_COLOR = 20 -FACTOR_ONE_MINUS_SRC1_COLOR = 21 -FACTOR_SRC1_ALPHA = 22 -FACTOR_ONE_MINUS_SRC1_ALPHA = 23 -adreno_rb_blend_factor = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_surface_endian' -adreno_rb_surface_endian__enumvalues = { - 0: 'ENDIAN_NONE', - 1: 'ENDIAN_8IN16', - 2: 'ENDIAN_8IN32', - 3: 'ENDIAN_16IN32', - 4: 'ENDIAN_8IN64', - 5: 'ENDIAN_8IN128', -} -ENDIAN_NONE = 0 -ENDIAN_8IN16 = 1 -ENDIAN_8IN32 = 2 -ENDIAN_16IN32 = 3 -ENDIAN_8IN64 = 4 -ENDIAN_8IN128 = 5 -adreno_rb_surface_endian = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_dither_mode' -adreno_rb_dither_mode__enumvalues = { - 0: 'DITHER_DISABLE', - 1: 'DITHER_ALWAYS', - 2: 'DITHER_IF_ALPHA_OFF', -} -DITHER_DISABLE = 0 -DITHER_ALWAYS = 1 -DITHER_IF_ALPHA_OFF = 2 -adreno_rb_dither_mode = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_depth_format' -adreno_rb_depth_format__enumvalues = { - 0: 'DEPTHX_16', - 1: 'DEPTHX_24_8', - 2: 'DEPTHX_32', -} -DEPTHX_16 = 0 -DEPTHX_24_8 = 1 -DEPTHX_32 = 2 -adreno_rb_depth_format = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_copy_control_mode' -adreno_rb_copy_control_mode__enumvalues = { - 1: 'RB_COPY_RESOLVE', - 2: 'RB_COPY_CLEAR', - 5: 'RB_COPY_DEPTH_STENCIL', -} -RB_COPY_RESOLVE = 1 -RB_COPY_CLEAR = 2 -RB_COPY_DEPTH_STENCIL = 5 -adreno_rb_copy_control_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_rop_code' -a3xx_rop_code__enumvalues = { - 0: 'ROP_CLEAR', - 1: 'ROP_NOR', - 2: 'ROP_AND_INVERTED', - 3: 'ROP_COPY_INVERTED', - 4: 'ROP_AND_REVERSE', - 5: 'ROP_INVERT', - 6: 'ROP_XOR', - 7: 'ROP_NAND', - 8: 'ROP_AND', - 9: 'ROP_EQUIV', - 10: 'ROP_NOOP', - 11: 'ROP_OR_INVERTED', - 12: 'ROP_COPY', - 13: 'ROP_OR_REVERSE', - 14: 'ROP_OR', - 15: 'ROP_SET', -} -ROP_CLEAR = 0 -ROP_NOR = 1 -ROP_AND_INVERTED = 2 -ROP_COPY_INVERTED = 3 -ROP_AND_REVERSE = 4 -ROP_INVERT = 5 -ROP_XOR = 6 -ROP_NAND = 7 -ROP_AND = 8 -ROP_EQUIV = 9 -ROP_NOOP = 10 -ROP_OR_INVERTED = 11 -ROP_COPY = 12 -ROP_OR_REVERSE = 13 -ROP_OR = 14 -ROP_SET = 15 -a3xx_rop_code = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_render_mode' -a3xx_render_mode__enumvalues = { - 0: 'RB_RENDERING_PASS', - 1: 'RB_TILING_PASS', - 2: 'RB_RESOLVE_PASS', - 3: 'RB_COMPUTE_PASS', -} -RB_RENDERING_PASS = 0 -RB_TILING_PASS = 1 -RB_RESOLVE_PASS = 2 -RB_COMPUTE_PASS = 3 -a3xx_render_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_msaa_samples' -a3xx_msaa_samples__enumvalues = { - 0: 'MSAA_ONE', - 1: 'MSAA_TWO', - 2: 'MSAA_FOUR', - 3: 'MSAA_EIGHT', -} -MSAA_ONE = 0 -MSAA_TWO = 1 -MSAA_FOUR = 2 -MSAA_EIGHT = 3 -a3xx_msaa_samples = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_threadmode' -a3xx_threadmode__enumvalues = { - 0: 'MULTI', - 1: 'SINGLE', -} -MULTI = 0 -SINGLE = 1 -a3xx_threadmode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_instrbuffermode' -a3xx_instrbuffermode__enumvalues = { - 0: 'CACHE', - 1: 'BUFFER', -} -CACHE = 0 -BUFFER = 1 -a3xx_instrbuffermode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_threadsize' -a3xx_threadsize__enumvalues = { - 0: 'TWO_QUADS', - 1: 'FOUR_QUADS', -} -TWO_QUADS = 0 -FOUR_QUADS = 1 -a3xx_threadsize = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_color_swap' -a3xx_color_swap__enumvalues = { - 0: 'WZYX', - 1: 'WXYZ', - 2: 'ZYXW', - 3: 'XYZW', -} -WZYX = 0 -WXYZ = 1 -ZYXW = 2 -XYZW = 3 -a3xx_color_swap = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_rb_blend_opcode' -a3xx_rb_blend_opcode__enumvalues = { - 0: 'BLEND_DST_PLUS_SRC', - 1: 'BLEND_SRC_MINUS_DST', - 2: 'BLEND_DST_MINUS_SRC', - 3: 'BLEND_MIN_DST_SRC', - 4: 'BLEND_MAX_DST_SRC', -} -BLEND_DST_PLUS_SRC = 0 -BLEND_SRC_MINUS_DST = 1 -BLEND_DST_MINUS_SRC = 2 -BLEND_MIN_DST_SRC = 3 -BLEND_MAX_DST_SRC = 4 -a3xx_rb_blend_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_tess_spacing' -a4xx_tess_spacing__enumvalues = { - 0: 'EQUAL_SPACING', - 2: 'ODD_SPACING', - 3: 'EVEN_SPACING', -} -EQUAL_SPACING = 0 -ODD_SPACING = 2 -EVEN_SPACING = 3 -a4xx_tess_spacing = ctypes.c_uint32 # enum - -# values for enumeration 'a5xx_address_mode' -a5xx_address_mode__enumvalues = { - 0: 'ADDR_32B', - 1: 'ADDR_64B', -} -ADDR_32B = 0 -ADDR_64B = 1 -a5xx_address_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a5xx_line_mode' -a5xx_line_mode__enumvalues = { - 0: 'BRESENHAM', - 1: 'RECTANGULAR', -} -BRESENHAM = 0 -RECTANGULAR = 1 -a5xx_line_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_prefetch_cmd' -a6xx_tex_prefetch_cmd__enumvalues = { - 0: 'TEX_PREFETCH_UNK0', - 1: 'TEX_PREFETCH_SAM', - 2: 'TEX_PREFETCH_GATHER4R', - 3: 'TEX_PREFETCH_GATHER4G', - 4: 'TEX_PREFETCH_GATHER4B', - 5: 'TEX_PREFETCH_GATHER4A', - 6: 'TEX_PREFETCH_UNK6', - 7: 'TEX_PREFETCH_UNK7', -} -TEX_PREFETCH_UNK0 = 0 -TEX_PREFETCH_SAM = 1 -TEX_PREFETCH_GATHER4R = 2 -TEX_PREFETCH_GATHER4G = 3 -TEX_PREFETCH_GATHER4B = 4 -TEX_PREFETCH_GATHER4A = 5 -TEX_PREFETCH_UNK6 = 6 -TEX_PREFETCH_UNK7 = 7 -a6xx_tex_prefetch_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tile_mode' -a6xx_tile_mode__enumvalues = { - 0: 'TILE6_LINEAR', - 2: 'TILE6_2', - 3: 'TILE6_3', -} -TILE6_LINEAR = 0 -TILE6_2 = 2 -TILE6_3 = 3 -a6xx_tile_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_format' -a6xx_format__enumvalues = { - 2: 'FMT6_A8_UNORM', - 3: 'FMT6_8_UNORM', - 4: 'FMT6_8_SNORM', - 5: 'FMT6_8_UINT', - 6: 'FMT6_8_SINT', - 8: 'FMT6_4_4_4_4_UNORM', - 10: 'FMT6_5_5_5_1_UNORM', - 12: 'FMT6_1_5_5_5_UNORM', - 14: 'FMT6_5_6_5_UNORM', - 15: 'FMT6_8_8_UNORM', - 16: 'FMT6_8_8_SNORM', - 17: 'FMT6_8_8_UINT', - 18: 'FMT6_8_8_SINT', - 19: 'FMT6_L8_A8_UNORM', - 21: 'FMT6_16_UNORM', - 22: 'FMT6_16_SNORM', - 23: 'FMT6_16_FLOAT', - 24: 'FMT6_16_UINT', - 25: 'FMT6_16_SINT', - 33: 'FMT6_8_8_8_UNORM', - 34: 'FMT6_8_8_8_SNORM', - 35: 'FMT6_8_8_8_UINT', - 36: 'FMT6_8_8_8_SINT', - 48: 'FMT6_8_8_8_8_UNORM', - 49: 'FMT6_8_8_8_X8_UNORM', - 50: 'FMT6_8_8_8_8_SNORM', - 51: 'FMT6_8_8_8_8_UINT', - 52: 'FMT6_8_8_8_8_SINT', - 53: 'FMT6_9_9_9_E5_FLOAT', - 54: 'FMT6_10_10_10_2_UNORM', - 55: 'FMT6_10_10_10_2_UNORM_DEST', - 57: 'FMT6_10_10_10_2_SNORM', - 58: 'FMT6_10_10_10_2_UINT', - 59: 'FMT6_10_10_10_2_SINT', - 66: 'FMT6_11_11_10_FLOAT', - 67: 'FMT6_16_16_UNORM', - 68: 'FMT6_16_16_SNORM', - 69: 'FMT6_16_16_FLOAT', - 70: 'FMT6_16_16_UINT', - 71: 'FMT6_16_16_SINT', - 72: 'FMT6_32_UNORM', - 73: 'FMT6_32_SNORM', - 74: 'FMT6_32_FLOAT', - 75: 'FMT6_32_UINT', - 76: 'FMT6_32_SINT', - 77: 'FMT6_32_FIXED', - 88: 'FMT6_16_16_16_UNORM', - 89: 'FMT6_16_16_16_SNORM', - 90: 'FMT6_16_16_16_FLOAT', - 91: 'FMT6_16_16_16_UINT', - 92: 'FMT6_16_16_16_SINT', - 96: 'FMT6_16_16_16_16_UNORM', - 97: 'FMT6_16_16_16_16_SNORM', - 98: 'FMT6_16_16_16_16_FLOAT', - 99: 'FMT6_16_16_16_16_UINT', - 100: 'FMT6_16_16_16_16_SINT', - 101: 'FMT6_32_32_UNORM', - 102: 'FMT6_32_32_SNORM', - 103: 'FMT6_32_32_FLOAT', - 104: 'FMT6_32_32_UINT', - 105: 'FMT6_32_32_SINT', - 106: 'FMT6_32_32_FIXED', - 112: 'FMT6_32_32_32_UNORM', - 113: 'FMT6_32_32_32_SNORM', - 114: 'FMT6_32_32_32_UINT', - 115: 'FMT6_32_32_32_SINT', - 116: 'FMT6_32_32_32_FLOAT', - 117: 'FMT6_32_32_32_FIXED', - 128: 'FMT6_32_32_32_32_UNORM', - 129: 'FMT6_32_32_32_32_SNORM', - 130: 'FMT6_32_32_32_32_FLOAT', - 131: 'FMT6_32_32_32_32_UINT', - 132: 'FMT6_32_32_32_32_SINT', - 133: 'FMT6_32_32_32_32_FIXED', - 140: 'FMT6_G8R8B8R8_422_UNORM', - 141: 'FMT6_R8G8R8B8_422_UNORM', - 142: 'FMT6_R8_G8B8_2PLANE_420_UNORM', - 143: 'FMT6_NV21', - 144: 'FMT6_R8_G8_B8_3PLANE_420_UNORM', - 145: 'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', - 148: 'FMT6_NV12_Y', - 149: 'FMT6_NV12_UV', - 150: 'FMT6_NV12_VU', - 151: 'FMT6_NV12_4R', - 152: 'FMT6_NV12_4R_Y', - 153: 'FMT6_NV12_4R_UV', - 154: 'FMT6_P010', - 155: 'FMT6_P010_Y', - 156: 'FMT6_P010_UV', - 157: 'FMT6_TP10', - 158: 'FMT6_TP10_Y', - 159: 'FMT6_TP10_UV', - 160: 'FMT6_Z24_UNORM_S8_UINT', - 171: 'FMT6_ETC2_RG11_UNORM', - 172: 'FMT6_ETC2_RG11_SNORM', - 173: 'FMT6_ETC2_R11_UNORM', - 174: 'FMT6_ETC2_R11_SNORM', - 175: 'FMT6_ETC1', - 176: 'FMT6_ETC2_RGB8', - 177: 'FMT6_ETC2_RGBA8', - 178: 'FMT6_ETC2_RGB8A1', - 179: 'FMT6_DXT1', - 180: 'FMT6_DXT3', - 181: 'FMT6_DXT5', - 183: 'FMT6_RGTC1_UNORM', - 184: 'FMT6_RGTC1_SNORM', - 187: 'FMT6_RGTC2_UNORM', - 188: 'FMT6_RGTC2_SNORM', - 190: 'FMT6_BPTC_UFLOAT', - 191: 'FMT6_BPTC_FLOAT', - 192: 'FMT6_BPTC', - 193: 'FMT6_ASTC_4x4', - 194: 'FMT6_ASTC_5x4', - 195: 'FMT6_ASTC_5x5', - 196: 'FMT6_ASTC_6x5', - 197: 'FMT6_ASTC_6x6', - 198: 'FMT6_ASTC_8x5', - 199: 'FMT6_ASTC_8x6', - 200: 'FMT6_ASTC_8x8', - 201: 'FMT6_ASTC_10x5', - 202: 'FMT6_ASTC_10x6', - 203: 'FMT6_ASTC_10x8', - 204: 'FMT6_ASTC_10x10', - 205: 'FMT6_ASTC_12x10', - 206: 'FMT6_ASTC_12x12', - 234: 'FMT6_Z24_UINT_S8_UINT', - 255: 'FMT6_NONE', -} -FMT6_A8_UNORM = 2 -FMT6_8_UNORM = 3 -FMT6_8_SNORM = 4 -FMT6_8_UINT = 5 -FMT6_8_SINT = 6 -FMT6_4_4_4_4_UNORM = 8 -FMT6_5_5_5_1_UNORM = 10 -FMT6_1_5_5_5_UNORM = 12 -FMT6_5_6_5_UNORM = 14 -FMT6_8_8_UNORM = 15 -FMT6_8_8_SNORM = 16 -FMT6_8_8_UINT = 17 -FMT6_8_8_SINT = 18 -FMT6_L8_A8_UNORM = 19 -FMT6_16_UNORM = 21 -FMT6_16_SNORM = 22 -FMT6_16_FLOAT = 23 -FMT6_16_UINT = 24 -FMT6_16_SINT = 25 -FMT6_8_8_8_UNORM = 33 -FMT6_8_8_8_SNORM = 34 -FMT6_8_8_8_UINT = 35 -FMT6_8_8_8_SINT = 36 -FMT6_8_8_8_8_UNORM = 48 -FMT6_8_8_8_X8_UNORM = 49 -FMT6_8_8_8_8_SNORM = 50 -FMT6_8_8_8_8_UINT = 51 -FMT6_8_8_8_8_SINT = 52 -FMT6_9_9_9_E5_FLOAT = 53 -FMT6_10_10_10_2_UNORM = 54 -FMT6_10_10_10_2_UNORM_DEST = 55 -FMT6_10_10_10_2_SNORM = 57 -FMT6_10_10_10_2_UINT = 58 -FMT6_10_10_10_2_SINT = 59 -FMT6_11_11_10_FLOAT = 66 -FMT6_16_16_UNORM = 67 -FMT6_16_16_SNORM = 68 -FMT6_16_16_FLOAT = 69 -FMT6_16_16_UINT = 70 -FMT6_16_16_SINT = 71 -FMT6_32_UNORM = 72 -FMT6_32_SNORM = 73 -FMT6_32_FLOAT = 74 -FMT6_32_UINT = 75 -FMT6_32_SINT = 76 -FMT6_32_FIXED = 77 -FMT6_16_16_16_UNORM = 88 -FMT6_16_16_16_SNORM = 89 -FMT6_16_16_16_FLOAT = 90 -FMT6_16_16_16_UINT = 91 -FMT6_16_16_16_SINT = 92 -FMT6_16_16_16_16_UNORM = 96 -FMT6_16_16_16_16_SNORM = 97 -FMT6_16_16_16_16_FLOAT = 98 -FMT6_16_16_16_16_UINT = 99 -FMT6_16_16_16_16_SINT = 100 -FMT6_32_32_UNORM = 101 -FMT6_32_32_SNORM = 102 -FMT6_32_32_FLOAT = 103 -FMT6_32_32_UINT = 104 -FMT6_32_32_SINT = 105 -FMT6_32_32_FIXED = 106 -FMT6_32_32_32_UNORM = 112 -FMT6_32_32_32_SNORM = 113 -FMT6_32_32_32_UINT = 114 -FMT6_32_32_32_SINT = 115 -FMT6_32_32_32_FLOAT = 116 -FMT6_32_32_32_FIXED = 117 -FMT6_32_32_32_32_UNORM = 128 -FMT6_32_32_32_32_SNORM = 129 -FMT6_32_32_32_32_FLOAT = 130 -FMT6_32_32_32_32_UINT = 131 -FMT6_32_32_32_32_SINT = 132 -FMT6_32_32_32_32_FIXED = 133 -FMT6_G8R8B8R8_422_UNORM = 140 -FMT6_R8G8R8B8_422_UNORM = 141 -FMT6_R8_G8B8_2PLANE_420_UNORM = 142 -FMT6_NV21 = 143 -FMT6_R8_G8_B8_3PLANE_420_UNORM = 144 -FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145 -FMT6_NV12_Y = 148 -FMT6_NV12_UV = 149 -FMT6_NV12_VU = 150 -FMT6_NV12_4R = 151 -FMT6_NV12_4R_Y = 152 -FMT6_NV12_4R_UV = 153 -FMT6_P010 = 154 -FMT6_P010_Y = 155 -FMT6_P010_UV = 156 -FMT6_TP10 = 157 -FMT6_TP10_Y = 158 -FMT6_TP10_UV = 159 -FMT6_Z24_UNORM_S8_UINT = 160 -FMT6_ETC2_RG11_UNORM = 171 -FMT6_ETC2_RG11_SNORM = 172 -FMT6_ETC2_R11_UNORM = 173 -FMT6_ETC2_R11_SNORM = 174 -FMT6_ETC1 = 175 -FMT6_ETC2_RGB8 = 176 -FMT6_ETC2_RGBA8 = 177 -FMT6_ETC2_RGB8A1 = 178 -FMT6_DXT1 = 179 -FMT6_DXT3 = 180 -FMT6_DXT5 = 181 -FMT6_RGTC1_UNORM = 183 -FMT6_RGTC1_SNORM = 184 -FMT6_RGTC2_UNORM = 187 -FMT6_RGTC2_SNORM = 188 -FMT6_BPTC_UFLOAT = 190 -FMT6_BPTC_FLOAT = 191 -FMT6_BPTC = 192 -FMT6_ASTC_4x4 = 193 -FMT6_ASTC_5x4 = 194 -FMT6_ASTC_5x5 = 195 -FMT6_ASTC_6x5 = 196 -FMT6_ASTC_6x6 = 197 -FMT6_ASTC_8x5 = 198 -FMT6_ASTC_8x6 = 199 -FMT6_ASTC_8x8 = 200 -FMT6_ASTC_10x5 = 201 -FMT6_ASTC_10x6 = 202 -FMT6_ASTC_10x8 = 203 -FMT6_ASTC_10x10 = 204 -FMT6_ASTC_12x10 = 205 -FMT6_ASTC_12x12 = 206 -FMT6_Z24_UINT_S8_UINT = 234 -FMT6_NONE = 255 -a6xx_format = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_polygon_mode' -a6xx_polygon_mode__enumvalues = { - 1: 'POLYMODE6_POINTS', - 2: 'POLYMODE6_LINES', - 3: 'POLYMODE6_TRIANGLES', -} -POLYMODE6_POINTS = 1 -POLYMODE6_LINES = 2 -POLYMODE6_TRIANGLES = 3 -a6xx_polygon_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_depth_format' -a6xx_depth_format__enumvalues = { - 0: 'DEPTH6_NONE', - 1: 'DEPTH6_16', - 2: 'DEPTH6_24_8', - 4: 'DEPTH6_32', -} -DEPTH6_NONE = 0 -DEPTH6_16 = 1 -DEPTH6_24_8 = 2 -DEPTH6_32 = 4 -a6xx_depth_format = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_shader_id' -a6xx_shader_id__enumvalues = { - 9: 'A6XX_TP0_TMO_DATA', - 10: 'A6XX_TP0_SMO_DATA', - 11: 'A6XX_TP0_MIPMAP_BASE_DATA', - 25: 'A6XX_TP1_TMO_DATA', - 26: 'A6XX_TP1_SMO_DATA', - 27: 'A6XX_TP1_MIPMAP_BASE_DATA', - 41: 'A6XX_SP_INST_DATA', - 42: 'A6XX_SP_LB_0_DATA', - 43: 'A6XX_SP_LB_1_DATA', - 44: 'A6XX_SP_LB_2_DATA', - 45: 'A6XX_SP_LB_3_DATA', - 46: 'A6XX_SP_LB_4_DATA', - 47: 'A6XX_SP_LB_5_DATA', - 48: 'A6XX_SP_CB_BINDLESS_DATA', - 49: 'A6XX_SP_CB_LEGACY_DATA', - 50: 'A6XX_SP_UAV_DATA', - 51: 'A6XX_SP_INST_TAG', - 52: 'A6XX_SP_CB_BINDLESS_TAG', - 53: 'A6XX_SP_TMO_UMO_TAG', - 54: 'A6XX_SP_SMO_TAG', - 55: 'A6XX_SP_STATE_DATA', - 73: 'A6XX_HLSQ_CHUNK_CVS_RAM', - 74: 'A6XX_HLSQ_CHUNK_CPS_RAM', - 75: 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG', - 76: 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG', - 77: 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 78: 'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', - 80: 'A6XX_HLSQ_CVS_MISC_RAM', - 81: 'A6XX_HLSQ_CPS_MISC_RAM', - 82: 'A6XX_HLSQ_INST_RAM', - 83: 'A6XX_HLSQ_GFX_CVS_CONST_RAM', - 84: 'A6XX_HLSQ_GFX_CPS_CONST_RAM', - 85: 'A6XX_HLSQ_CVS_MISC_RAM_TAG', - 86: 'A6XX_HLSQ_CPS_MISC_RAM_TAG', - 87: 'A6XX_HLSQ_INST_RAM_TAG', - 88: 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 89: 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 90: 'A6XX_HLSQ_PWR_REST_RAM', - 91: 'A6XX_HLSQ_PWR_REST_TAG', - 96: 'A6XX_HLSQ_DATAPATH_META', - 97: 'A6XX_HLSQ_FRONTEND_META', - 98: 'A6XX_HLSQ_INDIRECT_META', - 99: 'A6XX_HLSQ_BACKEND_META', - 112: 'A6XX_SP_LB_6_DATA', - 113: 'A6XX_SP_LB_7_DATA', - 115: 'A6XX_HLSQ_INST_RAM_1', -} -A6XX_TP0_TMO_DATA = 9 -A6XX_TP0_SMO_DATA = 10 -A6XX_TP0_MIPMAP_BASE_DATA = 11 -A6XX_TP1_TMO_DATA = 25 -A6XX_TP1_SMO_DATA = 26 -A6XX_TP1_MIPMAP_BASE_DATA = 27 -A6XX_SP_INST_DATA = 41 -A6XX_SP_LB_0_DATA = 42 -A6XX_SP_LB_1_DATA = 43 -A6XX_SP_LB_2_DATA = 44 -A6XX_SP_LB_3_DATA = 45 -A6XX_SP_LB_4_DATA = 46 -A6XX_SP_LB_5_DATA = 47 -A6XX_SP_CB_BINDLESS_DATA = 48 -A6XX_SP_CB_LEGACY_DATA = 49 -A6XX_SP_UAV_DATA = 50 -A6XX_SP_INST_TAG = 51 -A6XX_SP_CB_BINDLESS_TAG = 52 -A6XX_SP_TMO_UMO_TAG = 53 -A6XX_SP_SMO_TAG = 54 -A6XX_SP_STATE_DATA = 55 -A6XX_HLSQ_CHUNK_CVS_RAM = 73 -A6XX_HLSQ_CHUNK_CPS_RAM = 74 -A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75 -A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76 -A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77 -A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78 -A6XX_HLSQ_CVS_MISC_RAM = 80 -A6XX_HLSQ_CPS_MISC_RAM = 81 -A6XX_HLSQ_INST_RAM = 82 -A6XX_HLSQ_GFX_CVS_CONST_RAM = 83 -A6XX_HLSQ_GFX_CPS_CONST_RAM = 84 -A6XX_HLSQ_CVS_MISC_RAM_TAG = 85 -A6XX_HLSQ_CPS_MISC_RAM_TAG = 86 -A6XX_HLSQ_INST_RAM_TAG = 87 -A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88 -A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89 -A6XX_HLSQ_PWR_REST_RAM = 90 -A6XX_HLSQ_PWR_REST_TAG = 91 -A6XX_HLSQ_DATAPATH_META = 96 -A6XX_HLSQ_FRONTEND_META = 97 -A6XX_HLSQ_INDIRECT_META = 98 -A6XX_HLSQ_BACKEND_META = 99 -A6XX_SP_LB_6_DATA = 112 -A6XX_SP_LB_7_DATA = 113 -A6XX_HLSQ_INST_RAM_1 = 115 -a6xx_shader_id = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_statetype_id' -a7xx_statetype_id__enumvalues = { - 0: 'A7XX_TP0_NCTX_REG', - 1: 'A7XX_TP0_CTX0_3D_CVS_REG', - 2: 'A7XX_TP0_CTX0_3D_CPS_REG', - 3: 'A7XX_TP0_CTX1_3D_CVS_REG', - 4: 'A7XX_TP0_CTX1_3D_CPS_REG', - 5: 'A7XX_TP0_CTX2_3D_CPS_REG', - 6: 'A7XX_TP0_CTX3_3D_CPS_REG', - 9: 'A7XX_TP0_TMO_DATA', - 10: 'A7XX_TP0_SMO_DATA', - 11: 'A7XX_TP0_MIPMAP_BASE_DATA', - 32: 'A7XX_SP_NCTX_REG', - 33: 'A7XX_SP_CTX0_3D_CVS_REG', - 34: 'A7XX_SP_CTX0_3D_CPS_REG', - 35: 'A7XX_SP_CTX1_3D_CVS_REG', - 36: 'A7XX_SP_CTX1_3D_CPS_REG', - 37: 'A7XX_SP_CTX2_3D_CPS_REG', - 38: 'A7XX_SP_CTX3_3D_CPS_REG', - 39: 'A7XX_SP_INST_DATA', - 40: 'A7XX_SP_INST_DATA_1', - 41: 'A7XX_SP_LB_0_DATA', - 42: 'A7XX_SP_LB_1_DATA', - 43: 'A7XX_SP_LB_2_DATA', - 44: 'A7XX_SP_LB_3_DATA', - 45: 'A7XX_SP_LB_4_DATA', - 46: 'A7XX_SP_LB_5_DATA', - 47: 'A7XX_SP_LB_6_DATA', - 48: 'A7XX_SP_LB_7_DATA', - 49: 'A7XX_SP_CB_RAM', - 50: 'A7XX_SP_LB_13_DATA', - 51: 'A7XX_SP_LB_14_DATA', - 52: 'A7XX_SP_INST_TAG', - 53: 'A7XX_SP_INST_DATA_2', - 54: 'A7XX_SP_TMO_TAG', - 55: 'A7XX_SP_SMO_TAG', - 56: 'A7XX_SP_STATE_DATA', - 57: 'A7XX_SP_HWAVE_RAM', - 58: 'A7XX_SP_L0_INST_BUF', - 59: 'A7XX_SP_LB_8_DATA', - 60: 'A7XX_SP_LB_9_DATA', - 61: 'A7XX_SP_LB_10_DATA', - 62: 'A7XX_SP_LB_11_DATA', - 63: 'A7XX_SP_LB_12_DATA', - 64: 'A7XX_HLSQ_DATAPATH_DSTR_META', - 67: 'A7XX_HLSQ_L2STC_TAG_RAM', - 68: 'A7XX_HLSQ_L2STC_INFO_CMD', - 69: 'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', - 70: 'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', - 71: 'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', - 72: 'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', - 73: 'A7XX_HLSQ_CHUNK_CVS_RAM', - 74: 'A7XX_HLSQ_CHUNK_CPS_RAM', - 75: 'A7XX_HLSQ_CHUNK_CVS_RAM_TAG', - 76: 'A7XX_HLSQ_CHUNK_CPS_RAM_TAG', - 77: 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 78: 'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', - 79: 'A7XX_HLSQ_CVS_MISC_RAM', - 80: 'A7XX_HLSQ_CPS_MISC_RAM', - 81: 'A7XX_HLSQ_CPS_MISC_RAM_1', - 82: 'A7XX_HLSQ_INST_RAM', - 83: 'A7XX_HLSQ_GFX_CVS_CONST_RAM', - 84: 'A7XX_HLSQ_GFX_CPS_CONST_RAM', - 85: 'A7XX_HLSQ_CVS_MISC_RAM_TAG', - 86: 'A7XX_HLSQ_CPS_MISC_RAM_TAG', - 87: 'A7XX_HLSQ_INST_RAM_TAG', - 88: 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 89: 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 90: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM', - 91: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', - 92: 'A7XX_HLSQ_INST_RAM_1', - 93: 'A7XX_HLSQ_STPROC_META', - 94: 'A7XX_HLSQ_BV_BE_META', - 95: 'A7XX_HLSQ_INST_RAM_2', - 96: 'A7XX_HLSQ_DATAPATH_META', - 97: 'A7XX_HLSQ_FRONTEND_META', - 98: 'A7XX_HLSQ_INDIRECT_META', - 99: 'A7XX_HLSQ_BACKEND_META', -} -A7XX_TP0_NCTX_REG = 0 -A7XX_TP0_CTX0_3D_CVS_REG = 1 -A7XX_TP0_CTX0_3D_CPS_REG = 2 -A7XX_TP0_CTX1_3D_CVS_REG = 3 -A7XX_TP0_CTX1_3D_CPS_REG = 4 -A7XX_TP0_CTX2_3D_CPS_REG = 5 -A7XX_TP0_CTX3_3D_CPS_REG = 6 -A7XX_TP0_TMO_DATA = 9 -A7XX_TP0_SMO_DATA = 10 -A7XX_TP0_MIPMAP_BASE_DATA = 11 -A7XX_SP_NCTX_REG = 32 -A7XX_SP_CTX0_3D_CVS_REG = 33 -A7XX_SP_CTX0_3D_CPS_REG = 34 -A7XX_SP_CTX1_3D_CVS_REG = 35 -A7XX_SP_CTX1_3D_CPS_REG = 36 -A7XX_SP_CTX2_3D_CPS_REG = 37 -A7XX_SP_CTX3_3D_CPS_REG = 38 -A7XX_SP_INST_DATA = 39 -A7XX_SP_INST_DATA_1 = 40 -A7XX_SP_LB_0_DATA = 41 -A7XX_SP_LB_1_DATA = 42 -A7XX_SP_LB_2_DATA = 43 -A7XX_SP_LB_3_DATA = 44 -A7XX_SP_LB_4_DATA = 45 -A7XX_SP_LB_5_DATA = 46 -A7XX_SP_LB_6_DATA = 47 -A7XX_SP_LB_7_DATA = 48 -A7XX_SP_CB_RAM = 49 -A7XX_SP_LB_13_DATA = 50 -A7XX_SP_LB_14_DATA = 51 -A7XX_SP_INST_TAG = 52 -A7XX_SP_INST_DATA_2 = 53 -A7XX_SP_TMO_TAG = 54 -A7XX_SP_SMO_TAG = 55 -A7XX_SP_STATE_DATA = 56 -A7XX_SP_HWAVE_RAM = 57 -A7XX_SP_L0_INST_BUF = 58 -A7XX_SP_LB_8_DATA = 59 -A7XX_SP_LB_9_DATA = 60 -A7XX_SP_LB_10_DATA = 61 -A7XX_SP_LB_11_DATA = 62 -A7XX_SP_LB_12_DATA = 63 -A7XX_HLSQ_DATAPATH_DSTR_META = 64 -A7XX_HLSQ_L2STC_TAG_RAM = 67 -A7XX_HLSQ_L2STC_INFO_CMD = 68 -A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69 -A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70 -A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71 -A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72 -A7XX_HLSQ_CHUNK_CVS_RAM = 73 -A7XX_HLSQ_CHUNK_CPS_RAM = 74 -A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75 -A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76 -A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77 -A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78 -A7XX_HLSQ_CVS_MISC_RAM = 79 -A7XX_HLSQ_CPS_MISC_RAM = 80 -A7XX_HLSQ_CPS_MISC_RAM_1 = 81 -A7XX_HLSQ_INST_RAM = 82 -A7XX_HLSQ_GFX_CVS_CONST_RAM = 83 -A7XX_HLSQ_GFX_CPS_CONST_RAM = 84 -A7XX_HLSQ_CVS_MISC_RAM_TAG = 85 -A7XX_HLSQ_CPS_MISC_RAM_TAG = 86 -A7XX_HLSQ_INST_RAM_TAG = 87 -A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88 -A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89 -A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90 -A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91 -A7XX_HLSQ_INST_RAM_1 = 92 -A7XX_HLSQ_STPROC_META = 93 -A7XX_HLSQ_BV_BE_META = 94 -A7XX_HLSQ_INST_RAM_2 = 95 -A7XX_HLSQ_DATAPATH_META = 96 -A7XX_HLSQ_FRONTEND_META = 97 -A7XX_HLSQ_INDIRECT_META = 98 -A7XX_HLSQ_BACKEND_META = 99 -a7xx_statetype_id = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_debugbus_id' -a6xx_debugbus_id__enumvalues = { - 1: 'A6XX_DBGBUS_CP', - 2: 'A6XX_DBGBUS_RBBM', - 3: 'A6XX_DBGBUS_VBIF', - 4: 'A6XX_DBGBUS_HLSQ', - 5: 'A6XX_DBGBUS_UCHE', - 6: 'A6XX_DBGBUS_DPM', - 7: 'A6XX_DBGBUS_TESS', - 8: 'A6XX_DBGBUS_PC', - 9: 'A6XX_DBGBUS_VFDP', - 10: 'A6XX_DBGBUS_VPC', - 11: 'A6XX_DBGBUS_TSE', - 12: 'A6XX_DBGBUS_RAS', - 13: 'A6XX_DBGBUS_VSC', - 14: 'A6XX_DBGBUS_COM', - 16: 'A6XX_DBGBUS_LRZ', - 17: 'A6XX_DBGBUS_A2D', - 18: 'A6XX_DBGBUS_CCUFCHE', - 19: 'A6XX_DBGBUS_GMU_CX', - 20: 'A6XX_DBGBUS_RBP', - 21: 'A6XX_DBGBUS_DCS', - 22: 'A6XX_DBGBUS_DBGC', - 23: 'A6XX_DBGBUS_CX', - 24: 'A6XX_DBGBUS_GMU_GX', - 25: 'A6XX_DBGBUS_TPFCHE', - 26: 'A6XX_DBGBUS_GBIF_GX', - 29: 'A6XX_DBGBUS_GPC', - 30: 'A6XX_DBGBUS_LARC', - 31: 'A6XX_DBGBUS_HLSQ_SPTP', - 32: 'A6XX_DBGBUS_RB_0', - 33: 'A6XX_DBGBUS_RB_1', - 34: 'A6XX_DBGBUS_RB_2', - 36: 'A6XX_DBGBUS_UCHE_WRAPPER', - 40: 'A6XX_DBGBUS_CCU_0', - 41: 'A6XX_DBGBUS_CCU_1', - 42: 'A6XX_DBGBUS_CCU_2', - 56: 'A6XX_DBGBUS_VFD_0', - 57: 'A6XX_DBGBUS_VFD_1', - 58: 'A6XX_DBGBUS_VFD_2', - 59: 'A6XX_DBGBUS_VFD_3', - 60: 'A6XX_DBGBUS_VFD_4', - 61: 'A6XX_DBGBUS_VFD_5', - 64: 'A6XX_DBGBUS_SP_0', - 65: 'A6XX_DBGBUS_SP_1', - 66: 'A6XX_DBGBUS_SP_2', - 72: 'A6XX_DBGBUS_TPL1_0', - 73: 'A6XX_DBGBUS_TPL1_1', - 74: 'A6XX_DBGBUS_TPL1_2', - 75: 'A6XX_DBGBUS_TPL1_3', - 76: 'A6XX_DBGBUS_TPL1_4', - 77: 'A6XX_DBGBUS_TPL1_5', - 88: 'A6XX_DBGBUS_SPTP_0', - 89: 'A6XX_DBGBUS_SPTP_1', - 90: 'A6XX_DBGBUS_SPTP_2', - 91: 'A6XX_DBGBUS_SPTP_3', - 92: 'A6XX_DBGBUS_SPTP_4', - 93: 'A6XX_DBGBUS_SPTP_5', -} -A6XX_DBGBUS_CP = 1 -A6XX_DBGBUS_RBBM = 2 -A6XX_DBGBUS_VBIF = 3 -A6XX_DBGBUS_HLSQ = 4 -A6XX_DBGBUS_UCHE = 5 -A6XX_DBGBUS_DPM = 6 -A6XX_DBGBUS_TESS = 7 -A6XX_DBGBUS_PC = 8 -A6XX_DBGBUS_VFDP = 9 -A6XX_DBGBUS_VPC = 10 -A6XX_DBGBUS_TSE = 11 -A6XX_DBGBUS_RAS = 12 -A6XX_DBGBUS_VSC = 13 -A6XX_DBGBUS_COM = 14 -A6XX_DBGBUS_LRZ = 16 -A6XX_DBGBUS_A2D = 17 -A6XX_DBGBUS_CCUFCHE = 18 -A6XX_DBGBUS_GMU_CX = 19 -A6XX_DBGBUS_RBP = 20 -A6XX_DBGBUS_DCS = 21 -A6XX_DBGBUS_DBGC = 22 -A6XX_DBGBUS_CX = 23 -A6XX_DBGBUS_GMU_GX = 24 -A6XX_DBGBUS_TPFCHE = 25 -A6XX_DBGBUS_GBIF_GX = 26 -A6XX_DBGBUS_GPC = 29 -A6XX_DBGBUS_LARC = 30 -A6XX_DBGBUS_HLSQ_SPTP = 31 -A6XX_DBGBUS_RB_0 = 32 -A6XX_DBGBUS_RB_1 = 33 -A6XX_DBGBUS_RB_2 = 34 -A6XX_DBGBUS_UCHE_WRAPPER = 36 -A6XX_DBGBUS_CCU_0 = 40 -A6XX_DBGBUS_CCU_1 = 41 -A6XX_DBGBUS_CCU_2 = 42 -A6XX_DBGBUS_VFD_0 = 56 -A6XX_DBGBUS_VFD_1 = 57 -A6XX_DBGBUS_VFD_2 = 58 -A6XX_DBGBUS_VFD_3 = 59 -A6XX_DBGBUS_VFD_4 = 60 -A6XX_DBGBUS_VFD_5 = 61 -A6XX_DBGBUS_SP_0 = 64 -A6XX_DBGBUS_SP_1 = 65 -A6XX_DBGBUS_SP_2 = 66 -A6XX_DBGBUS_TPL1_0 = 72 -A6XX_DBGBUS_TPL1_1 = 73 -A6XX_DBGBUS_TPL1_2 = 74 -A6XX_DBGBUS_TPL1_3 = 75 -A6XX_DBGBUS_TPL1_4 = 76 -A6XX_DBGBUS_TPL1_5 = 77 -A6XX_DBGBUS_SPTP_0 = 88 -A6XX_DBGBUS_SPTP_1 = 89 -A6XX_DBGBUS_SPTP_2 = 90 -A6XX_DBGBUS_SPTP_3 = 91 -A6XX_DBGBUS_SPTP_4 = 92 -A6XX_DBGBUS_SPTP_5 = 93 -a6xx_debugbus_id = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_state_location' -a7xx_state_location__enumvalues = { - 0: 'A7XX_HLSQ_STATE', - 1: 'A7XX_HLSQ_DP', - 2: 'A7XX_SP_TOP', - 3: 'A7XX_USPTP', - 4: 'A7XX_HLSQ_DP_STR', -} -A7XX_HLSQ_STATE = 0 -A7XX_HLSQ_DP = 1 -A7XX_SP_TOP = 2 -A7XX_USPTP = 3 -A7XX_HLSQ_DP_STR = 4 -a7xx_state_location = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_pipe' -a7xx_pipe__enumvalues = { - 0: 'A7XX_PIPE_NONE', - 1: 'A7XX_PIPE_BR', - 2: 'A7XX_PIPE_BV', - 3: 'A7XX_PIPE_LPAC', -} -A7XX_PIPE_NONE = 0 -A7XX_PIPE_BR = 1 -A7XX_PIPE_BV = 2 -A7XX_PIPE_LPAC = 3 -a7xx_pipe = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cluster' -a7xx_cluster__enumvalues = { - 0: 'A7XX_CLUSTER_NONE', - 1: 'A7XX_CLUSTER_FE', - 2: 'A7XX_CLUSTER_SP_VS', - 3: 'A7XX_CLUSTER_PC_VS', - 4: 'A7XX_CLUSTER_GRAS', - 5: 'A7XX_CLUSTER_SP_PS', - 6: 'A7XX_CLUSTER_VPC_PS', - 7: 'A7XX_CLUSTER_PS', -} -A7XX_CLUSTER_NONE = 0 -A7XX_CLUSTER_FE = 1 -A7XX_CLUSTER_SP_VS = 2 -A7XX_CLUSTER_PC_VS = 3 -A7XX_CLUSTER_GRAS = 4 -A7XX_CLUSTER_SP_PS = 5 -A7XX_CLUSTER_VPC_PS = 6 -A7XX_CLUSTER_PS = 7 -a7xx_cluster = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_debugbus_id' -a7xx_debugbus_id__enumvalues = { - 1: 'A7XX_DBGBUS_CP_0_0', - 2: 'A7XX_DBGBUS_CP_0_1', - 3: 'A7XX_DBGBUS_RBBM', - 5: 'A7XX_DBGBUS_GBIF_GX', - 6: 'A7XX_DBGBUS_GBIF_CX', - 7: 'A7XX_DBGBUS_HLSQ', - 9: 'A7XX_DBGBUS_UCHE_0', - 10: 'A7XX_DBGBUS_UCHE_1', - 13: 'A7XX_DBGBUS_TESS_BR', - 14: 'A7XX_DBGBUS_TESS_BV', - 17: 'A7XX_DBGBUS_PC_BR', - 18: 'A7XX_DBGBUS_PC_BV', - 21: 'A7XX_DBGBUS_VFDP_BR', - 22: 'A7XX_DBGBUS_VFDP_BV', - 25: 'A7XX_DBGBUS_VPC_BR', - 26: 'A7XX_DBGBUS_VPC_BV', - 29: 'A7XX_DBGBUS_TSE_BR', - 30: 'A7XX_DBGBUS_TSE_BV', - 33: 'A7XX_DBGBUS_RAS_BR', - 34: 'A7XX_DBGBUS_RAS_BV', - 37: 'A7XX_DBGBUS_VSC', - 39: 'A7XX_DBGBUS_COM_0', - 43: 'A7XX_DBGBUS_LRZ_BR', - 44: 'A7XX_DBGBUS_LRZ_BV', - 47: 'A7XX_DBGBUS_UFC_0', - 48: 'A7XX_DBGBUS_UFC_1', - 55: 'A7XX_DBGBUS_GMU_GX', - 59: 'A7XX_DBGBUS_DBGC', - 60: 'A7XX_DBGBUS_CX', - 61: 'A7XX_DBGBUS_GMU_CX', - 62: 'A7XX_DBGBUS_GPC_BR', - 63: 'A7XX_DBGBUS_GPC_BV', - 66: 'A7XX_DBGBUS_LARC', - 68: 'A7XX_DBGBUS_HLSQ_SPTP', - 70: 'A7XX_DBGBUS_RB_0', - 71: 'A7XX_DBGBUS_RB_1', - 72: 'A7XX_DBGBUS_RB_2', - 73: 'A7XX_DBGBUS_RB_3', - 74: 'A7XX_DBGBUS_RB_4', - 75: 'A7XX_DBGBUS_RB_5', - 102: 'A7XX_DBGBUS_UCHE_WRAPPER', - 106: 'A7XX_DBGBUS_CCU_0', - 107: 'A7XX_DBGBUS_CCU_1', - 108: 'A7XX_DBGBUS_CCU_2', - 109: 'A7XX_DBGBUS_CCU_3', - 110: 'A7XX_DBGBUS_CCU_4', - 111: 'A7XX_DBGBUS_CCU_5', - 138: 'A7XX_DBGBUS_VFD_BR_0', - 139: 'A7XX_DBGBUS_VFD_BR_1', - 140: 'A7XX_DBGBUS_VFD_BR_2', - 141: 'A7XX_DBGBUS_VFD_BR_3', - 142: 'A7XX_DBGBUS_VFD_BR_4', - 143: 'A7XX_DBGBUS_VFD_BR_5', - 144: 'A7XX_DBGBUS_VFD_BR_6', - 145: 'A7XX_DBGBUS_VFD_BR_7', - 202: 'A7XX_DBGBUS_VFD_BV_0', - 203: 'A7XX_DBGBUS_VFD_BV_1', - 204: 'A7XX_DBGBUS_VFD_BV_2', - 205: 'A7XX_DBGBUS_VFD_BV_3', - 234: 'A7XX_DBGBUS_USP_0', - 235: 'A7XX_DBGBUS_USP_1', - 236: 'A7XX_DBGBUS_USP_2', - 237: 'A7XX_DBGBUS_USP_3', - 238: 'A7XX_DBGBUS_USP_4', - 239: 'A7XX_DBGBUS_USP_5', - 266: 'A7XX_DBGBUS_TP_0', - 267: 'A7XX_DBGBUS_TP_1', - 268: 'A7XX_DBGBUS_TP_2', - 269: 'A7XX_DBGBUS_TP_3', - 270: 'A7XX_DBGBUS_TP_4', - 271: 'A7XX_DBGBUS_TP_5', - 272: 'A7XX_DBGBUS_TP_6', - 273: 'A7XX_DBGBUS_TP_7', - 274: 'A7XX_DBGBUS_TP_8', - 275: 'A7XX_DBGBUS_TP_9', - 276: 'A7XX_DBGBUS_TP_10', - 277: 'A7XX_DBGBUS_TP_11', - 330: 'A7XX_DBGBUS_USPTP_0', - 331: 'A7XX_DBGBUS_USPTP_1', - 332: 'A7XX_DBGBUS_USPTP_2', - 333: 'A7XX_DBGBUS_USPTP_3', - 334: 'A7XX_DBGBUS_USPTP_4', - 335: 'A7XX_DBGBUS_USPTP_5', - 336: 'A7XX_DBGBUS_USPTP_6', - 337: 'A7XX_DBGBUS_USPTP_7', - 338: 'A7XX_DBGBUS_USPTP_8', - 339: 'A7XX_DBGBUS_USPTP_9', - 340: 'A7XX_DBGBUS_USPTP_10', - 341: 'A7XX_DBGBUS_USPTP_11', - 396: 'A7XX_DBGBUS_CCHE_0', - 397: 'A7XX_DBGBUS_CCHE_1', - 398: 'A7XX_DBGBUS_CCHE_2', - 408: 'A7XX_DBGBUS_VPC_DSTR_0', - 409: 'A7XX_DBGBUS_VPC_DSTR_1', - 410: 'A7XX_DBGBUS_VPC_DSTR_2', - 411: 'A7XX_DBGBUS_HLSQ_DP_STR_0', - 412: 'A7XX_DBGBUS_HLSQ_DP_STR_1', - 413: 'A7XX_DBGBUS_HLSQ_DP_STR_2', - 414: 'A7XX_DBGBUS_HLSQ_DP_STR_3', - 415: 'A7XX_DBGBUS_HLSQ_DP_STR_4', - 416: 'A7XX_DBGBUS_HLSQ_DP_STR_5', - 443: 'A7XX_DBGBUS_UFC_DSTR_0', - 444: 'A7XX_DBGBUS_UFC_DSTR_1', - 445: 'A7XX_DBGBUS_UFC_DSTR_2', - 446: 'A7XX_DBGBUS_CGC_SUBCORE', - 447: 'A7XX_DBGBUS_CGC_CORE', -} -A7XX_DBGBUS_CP_0_0 = 1 -A7XX_DBGBUS_CP_0_1 = 2 -A7XX_DBGBUS_RBBM = 3 -A7XX_DBGBUS_GBIF_GX = 5 -A7XX_DBGBUS_GBIF_CX = 6 -A7XX_DBGBUS_HLSQ = 7 -A7XX_DBGBUS_UCHE_0 = 9 -A7XX_DBGBUS_UCHE_1 = 10 -A7XX_DBGBUS_TESS_BR = 13 -A7XX_DBGBUS_TESS_BV = 14 -A7XX_DBGBUS_PC_BR = 17 -A7XX_DBGBUS_PC_BV = 18 -A7XX_DBGBUS_VFDP_BR = 21 -A7XX_DBGBUS_VFDP_BV = 22 -A7XX_DBGBUS_VPC_BR = 25 -A7XX_DBGBUS_VPC_BV = 26 -A7XX_DBGBUS_TSE_BR = 29 -A7XX_DBGBUS_TSE_BV = 30 -A7XX_DBGBUS_RAS_BR = 33 -A7XX_DBGBUS_RAS_BV = 34 -A7XX_DBGBUS_VSC = 37 -A7XX_DBGBUS_COM_0 = 39 -A7XX_DBGBUS_LRZ_BR = 43 -A7XX_DBGBUS_LRZ_BV = 44 -A7XX_DBGBUS_UFC_0 = 47 -A7XX_DBGBUS_UFC_1 = 48 -A7XX_DBGBUS_GMU_GX = 55 -A7XX_DBGBUS_DBGC = 59 -A7XX_DBGBUS_CX = 60 -A7XX_DBGBUS_GMU_CX = 61 -A7XX_DBGBUS_GPC_BR = 62 -A7XX_DBGBUS_GPC_BV = 63 -A7XX_DBGBUS_LARC = 66 -A7XX_DBGBUS_HLSQ_SPTP = 68 -A7XX_DBGBUS_RB_0 = 70 -A7XX_DBGBUS_RB_1 = 71 -A7XX_DBGBUS_RB_2 = 72 -A7XX_DBGBUS_RB_3 = 73 -A7XX_DBGBUS_RB_4 = 74 -A7XX_DBGBUS_RB_5 = 75 -A7XX_DBGBUS_UCHE_WRAPPER = 102 -A7XX_DBGBUS_CCU_0 = 106 -A7XX_DBGBUS_CCU_1 = 107 -A7XX_DBGBUS_CCU_2 = 108 -A7XX_DBGBUS_CCU_3 = 109 -A7XX_DBGBUS_CCU_4 = 110 -A7XX_DBGBUS_CCU_5 = 111 -A7XX_DBGBUS_VFD_BR_0 = 138 -A7XX_DBGBUS_VFD_BR_1 = 139 -A7XX_DBGBUS_VFD_BR_2 = 140 -A7XX_DBGBUS_VFD_BR_3 = 141 -A7XX_DBGBUS_VFD_BR_4 = 142 -A7XX_DBGBUS_VFD_BR_5 = 143 -A7XX_DBGBUS_VFD_BR_6 = 144 -A7XX_DBGBUS_VFD_BR_7 = 145 -A7XX_DBGBUS_VFD_BV_0 = 202 -A7XX_DBGBUS_VFD_BV_1 = 203 -A7XX_DBGBUS_VFD_BV_2 = 204 -A7XX_DBGBUS_VFD_BV_3 = 205 -A7XX_DBGBUS_USP_0 = 234 -A7XX_DBGBUS_USP_1 = 235 -A7XX_DBGBUS_USP_2 = 236 -A7XX_DBGBUS_USP_3 = 237 -A7XX_DBGBUS_USP_4 = 238 -A7XX_DBGBUS_USP_5 = 239 -A7XX_DBGBUS_TP_0 = 266 -A7XX_DBGBUS_TP_1 = 267 -A7XX_DBGBUS_TP_2 = 268 -A7XX_DBGBUS_TP_3 = 269 -A7XX_DBGBUS_TP_4 = 270 -A7XX_DBGBUS_TP_5 = 271 -A7XX_DBGBUS_TP_6 = 272 -A7XX_DBGBUS_TP_7 = 273 -A7XX_DBGBUS_TP_8 = 274 -A7XX_DBGBUS_TP_9 = 275 -A7XX_DBGBUS_TP_10 = 276 -A7XX_DBGBUS_TP_11 = 277 -A7XX_DBGBUS_USPTP_0 = 330 -A7XX_DBGBUS_USPTP_1 = 331 -A7XX_DBGBUS_USPTP_2 = 332 -A7XX_DBGBUS_USPTP_3 = 333 -A7XX_DBGBUS_USPTP_4 = 334 -A7XX_DBGBUS_USPTP_5 = 335 -A7XX_DBGBUS_USPTP_6 = 336 -A7XX_DBGBUS_USPTP_7 = 337 -A7XX_DBGBUS_USPTP_8 = 338 -A7XX_DBGBUS_USPTP_9 = 339 -A7XX_DBGBUS_USPTP_10 = 340 -A7XX_DBGBUS_USPTP_11 = 341 -A7XX_DBGBUS_CCHE_0 = 396 -A7XX_DBGBUS_CCHE_1 = 397 -A7XX_DBGBUS_CCHE_2 = 398 -A7XX_DBGBUS_VPC_DSTR_0 = 408 -A7XX_DBGBUS_VPC_DSTR_1 = 409 -A7XX_DBGBUS_VPC_DSTR_2 = 410 -A7XX_DBGBUS_HLSQ_DP_STR_0 = 411 -A7XX_DBGBUS_HLSQ_DP_STR_1 = 412 -A7XX_DBGBUS_HLSQ_DP_STR_2 = 413 -A7XX_DBGBUS_HLSQ_DP_STR_3 = 414 -A7XX_DBGBUS_HLSQ_DP_STR_4 = 415 -A7XX_DBGBUS_HLSQ_DP_STR_5 = 416 -A7XX_DBGBUS_UFC_DSTR_0 = 443 -A7XX_DBGBUS_UFC_DSTR_1 = 444 -A7XX_DBGBUS_UFC_DSTR_2 = 445 -A7XX_DBGBUS_CGC_SUBCORE = 446 -A7XX_DBGBUS_CGC_CORE = 447 -a7xx_debugbus_id = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_cp_perfcounter_select' -a6xx_cp_perfcounter_select__enumvalues = { - 0: 'PERF_CP_ALWAYS_COUNT', - 1: 'PERF_CP_BUSY_GFX_CORE_IDLE', - 2: 'PERF_CP_BUSY_CYCLES', - 3: 'PERF_CP_NUM_PREEMPTIONS', - 4: 'PERF_CP_PREEMPTION_REACTION_DELAY', - 5: 'PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 6: 'PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 7: 'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 8: 'PERF_CP_PREDICATED_DRAWS_KILLED', - 9: 'PERF_CP_MODE_SWITCH', - 10: 'PERF_CP_ZPASS_DONE', - 11: 'PERF_CP_CONTEXT_DONE', - 12: 'PERF_CP_CACHE_FLUSH', - 13: 'PERF_CP_LONG_PREEMPTIONS', - 14: 'PERF_CP_SQE_I_CACHE_STARVE', - 15: 'PERF_CP_SQE_IDLE', - 16: 'PERF_CP_SQE_PM4_STARVE_RB_IB', - 17: 'PERF_CP_SQE_PM4_STARVE_SDS', - 18: 'PERF_CP_SQE_MRB_STARVE', - 19: 'PERF_CP_SQE_RRB_STARVE', - 20: 'PERF_CP_SQE_VSD_STARVE', - 21: 'PERF_CP_VSD_DECODE_STARVE', - 22: 'PERF_CP_SQE_PIPE_OUT_STALL', - 23: 'PERF_CP_SQE_SYNC_STALL', - 24: 'PERF_CP_SQE_PM4_WFI_STALL', - 25: 'PERF_CP_SQE_SYS_WFI_STALL', - 26: 'PERF_CP_SQE_T4_EXEC', - 27: 'PERF_CP_SQE_LOAD_STATE_EXEC', - 28: 'PERF_CP_SQE_SAVE_SDS_STATE', - 29: 'PERF_CP_SQE_DRAW_EXEC', - 30: 'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 31: 'PERF_CP_SQE_EXEC_PROFILED', - 32: 'PERF_CP_MEMORY_POOL_EMPTY', - 33: 'PERF_CP_MEMORY_POOL_SYNC_STALL', - 34: 'PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 35: 'PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 36: 'PERF_CP_AHB_STALL_SQE_GMU', - 37: 'PERF_CP_AHB_STALL_SQE_WR_OTHER', - 38: 'PERF_CP_AHB_STALL_SQE_RD_OTHER', - 39: 'PERF_CP_CLUSTER0_EMPTY', - 40: 'PERF_CP_CLUSTER1_EMPTY', - 41: 'PERF_CP_CLUSTER2_EMPTY', - 42: 'PERF_CP_CLUSTER3_EMPTY', - 43: 'PERF_CP_CLUSTER4_EMPTY', - 44: 'PERF_CP_CLUSTER5_EMPTY', - 45: 'PERF_CP_PM4_DATA', - 46: 'PERF_CP_PM4_HEADERS', - 47: 'PERF_CP_VBIF_READ_BEATS', - 48: 'PERF_CP_VBIF_WRITE_BEATS', - 49: 'PERF_CP_SQE_INSTR_COUNTER', -} -PERF_CP_ALWAYS_COUNT = 0 -PERF_CP_BUSY_GFX_CORE_IDLE = 1 -PERF_CP_BUSY_CYCLES = 2 -PERF_CP_NUM_PREEMPTIONS = 3 -PERF_CP_PREEMPTION_REACTION_DELAY = 4 -PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5 -PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6 -PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7 -PERF_CP_PREDICATED_DRAWS_KILLED = 8 -PERF_CP_MODE_SWITCH = 9 -PERF_CP_ZPASS_DONE = 10 -PERF_CP_CONTEXT_DONE = 11 -PERF_CP_CACHE_FLUSH = 12 -PERF_CP_LONG_PREEMPTIONS = 13 -PERF_CP_SQE_I_CACHE_STARVE = 14 -PERF_CP_SQE_IDLE = 15 -PERF_CP_SQE_PM4_STARVE_RB_IB = 16 -PERF_CP_SQE_PM4_STARVE_SDS = 17 -PERF_CP_SQE_MRB_STARVE = 18 -PERF_CP_SQE_RRB_STARVE = 19 -PERF_CP_SQE_VSD_STARVE = 20 -PERF_CP_VSD_DECODE_STARVE = 21 -PERF_CP_SQE_PIPE_OUT_STALL = 22 -PERF_CP_SQE_SYNC_STALL = 23 -PERF_CP_SQE_PM4_WFI_STALL = 24 -PERF_CP_SQE_SYS_WFI_STALL = 25 -PERF_CP_SQE_T4_EXEC = 26 -PERF_CP_SQE_LOAD_STATE_EXEC = 27 -PERF_CP_SQE_SAVE_SDS_STATE = 28 -PERF_CP_SQE_DRAW_EXEC = 29 -PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30 -PERF_CP_SQE_EXEC_PROFILED = 31 -PERF_CP_MEMORY_POOL_EMPTY = 32 -PERF_CP_MEMORY_POOL_SYNC_STALL = 33 -PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34 -PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35 -PERF_CP_AHB_STALL_SQE_GMU = 36 -PERF_CP_AHB_STALL_SQE_WR_OTHER = 37 -PERF_CP_AHB_STALL_SQE_RD_OTHER = 38 -PERF_CP_CLUSTER0_EMPTY = 39 -PERF_CP_CLUSTER1_EMPTY = 40 -PERF_CP_CLUSTER2_EMPTY = 41 -PERF_CP_CLUSTER3_EMPTY = 42 -PERF_CP_CLUSTER4_EMPTY = 43 -PERF_CP_CLUSTER5_EMPTY = 44 -PERF_CP_PM4_DATA = 45 -PERF_CP_PM4_HEADERS = 46 -PERF_CP_VBIF_READ_BEATS = 47 -PERF_CP_VBIF_WRITE_BEATS = 48 -PERF_CP_SQE_INSTR_COUNTER = 49 -a6xx_cp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rbbm_perfcounter_select' -a6xx_rbbm_perfcounter_select__enumvalues = { - 0: 'PERF_RBBM_ALWAYS_COUNT', - 1: 'PERF_RBBM_ALWAYS_ON', - 2: 'PERF_RBBM_TSE_BUSY', - 3: 'PERF_RBBM_RAS_BUSY', - 4: 'PERF_RBBM_PC_DCALL_BUSY', - 5: 'PERF_RBBM_PC_VSD_BUSY', - 6: 'PERF_RBBM_STATUS_MASKED', - 7: 'PERF_RBBM_COM_BUSY', - 8: 'PERF_RBBM_DCOM_BUSY', - 9: 'PERF_RBBM_VBIF_BUSY', - 10: 'PERF_RBBM_VSC_BUSY', - 11: 'PERF_RBBM_TESS_BUSY', - 12: 'PERF_RBBM_UCHE_BUSY', - 13: 'PERF_RBBM_HLSQ_BUSY', -} -PERF_RBBM_ALWAYS_COUNT = 0 -PERF_RBBM_ALWAYS_ON = 1 -PERF_RBBM_TSE_BUSY = 2 -PERF_RBBM_RAS_BUSY = 3 -PERF_RBBM_PC_DCALL_BUSY = 4 -PERF_RBBM_PC_VSD_BUSY = 5 -PERF_RBBM_STATUS_MASKED = 6 -PERF_RBBM_COM_BUSY = 7 -PERF_RBBM_DCOM_BUSY = 8 -PERF_RBBM_VBIF_BUSY = 9 -PERF_RBBM_VSC_BUSY = 10 -PERF_RBBM_TESS_BUSY = 11 -PERF_RBBM_UCHE_BUSY = 12 -PERF_RBBM_HLSQ_BUSY = 13 -a6xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_pc_perfcounter_select' -a6xx_pc_perfcounter_select__enumvalues = { - 0: 'PERF_PC_BUSY_CYCLES', - 1: 'PERF_PC_WORKING_CYCLES', - 2: 'PERF_PC_STALL_CYCLES_VFD', - 3: 'PERF_PC_STALL_CYCLES_TSE', - 4: 'PERF_PC_STALL_CYCLES_VPC', - 5: 'PERF_PC_STALL_CYCLES_UCHE', - 6: 'PERF_PC_STALL_CYCLES_TESS', - 7: 'PERF_PC_STALL_CYCLES_TSE_ONLY', - 8: 'PERF_PC_STALL_CYCLES_VPC_ONLY', - 9: 'PERF_PC_PASS1_TF_STALL_CYCLES', - 10: 'PERF_PC_STARVE_CYCLES_FOR_INDEX', - 11: 'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', - 12: 'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', - 13: 'PERF_PC_STARVE_CYCLES_FOR_POSITION', - 14: 'PERF_PC_STARVE_CYCLES_DI', - 15: 'PERF_PC_VIS_STREAMS_LOADED', - 16: 'PERF_PC_INSTANCES', - 17: 'PERF_PC_VPC_PRIMITIVES', - 18: 'PERF_PC_DEAD_PRIM', - 19: 'PERF_PC_LIVE_PRIM', - 20: 'PERF_PC_VERTEX_HITS', - 21: 'PERF_PC_IA_VERTICES', - 22: 'PERF_PC_IA_PRIMITIVES', - 23: 'PERF_PC_GS_PRIMITIVES', - 24: 'PERF_PC_HS_INVOCATIONS', - 25: 'PERF_PC_DS_INVOCATIONS', - 26: 'PERF_PC_VS_INVOCATIONS', - 27: 'PERF_PC_GS_INVOCATIONS', - 28: 'PERF_PC_DS_PRIMITIVES', - 29: 'PERF_PC_VPC_POS_DATA_TRANSACTION', - 30: 'PERF_PC_3D_DRAWCALLS', - 31: 'PERF_PC_2D_DRAWCALLS', - 32: 'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', - 33: 'PERF_TESS_BUSY_CYCLES', - 34: 'PERF_TESS_WORKING_CYCLES', - 35: 'PERF_TESS_STALL_CYCLES_PC', - 36: 'PERF_TESS_STARVE_CYCLES_PC', - 37: 'PERF_PC_TSE_TRANSACTION', - 38: 'PERF_PC_TSE_VERTEX', - 39: 'PERF_PC_TESS_PC_UV_TRANS', - 40: 'PERF_PC_TESS_PC_UV_PATCHES', - 41: 'PERF_PC_TESS_FACTOR_TRANS', -} -PERF_PC_BUSY_CYCLES = 0 -PERF_PC_WORKING_CYCLES = 1 -PERF_PC_STALL_CYCLES_VFD = 2 -PERF_PC_STALL_CYCLES_TSE = 3 -PERF_PC_STALL_CYCLES_VPC = 4 -PERF_PC_STALL_CYCLES_UCHE = 5 -PERF_PC_STALL_CYCLES_TESS = 6 -PERF_PC_STALL_CYCLES_TSE_ONLY = 7 -PERF_PC_STALL_CYCLES_VPC_ONLY = 8 -PERF_PC_PASS1_TF_STALL_CYCLES = 9 -PERF_PC_STARVE_CYCLES_FOR_INDEX = 10 -PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11 -PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12 -PERF_PC_STARVE_CYCLES_FOR_POSITION = 13 -PERF_PC_STARVE_CYCLES_DI = 14 -PERF_PC_VIS_STREAMS_LOADED = 15 -PERF_PC_INSTANCES = 16 -PERF_PC_VPC_PRIMITIVES = 17 -PERF_PC_DEAD_PRIM = 18 -PERF_PC_LIVE_PRIM = 19 -PERF_PC_VERTEX_HITS = 20 -PERF_PC_IA_VERTICES = 21 -PERF_PC_IA_PRIMITIVES = 22 -PERF_PC_GS_PRIMITIVES = 23 -PERF_PC_HS_INVOCATIONS = 24 -PERF_PC_DS_INVOCATIONS = 25 -PERF_PC_VS_INVOCATIONS = 26 -PERF_PC_GS_INVOCATIONS = 27 -PERF_PC_DS_PRIMITIVES = 28 -PERF_PC_VPC_POS_DATA_TRANSACTION = 29 -PERF_PC_3D_DRAWCALLS = 30 -PERF_PC_2D_DRAWCALLS = 31 -PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32 -PERF_TESS_BUSY_CYCLES = 33 -PERF_TESS_WORKING_CYCLES = 34 -PERF_TESS_STALL_CYCLES_PC = 35 -PERF_TESS_STARVE_CYCLES_PC = 36 -PERF_PC_TSE_TRANSACTION = 37 -PERF_PC_TSE_VERTEX = 38 -PERF_PC_TESS_PC_UV_TRANS = 39 -PERF_PC_TESS_PC_UV_PATCHES = 40 -PERF_PC_TESS_FACTOR_TRANS = 41 -a6xx_pc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vfd_perfcounter_select' -a6xx_vfd_perfcounter_select__enumvalues = { - 0: 'PERF_VFD_BUSY_CYCLES', - 1: 'PERF_VFD_STALL_CYCLES_UCHE', - 2: 'PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 3: 'PERF_VFD_STALL_CYCLES_SP_INFO', - 4: 'PERF_VFD_STALL_CYCLES_SP_ATTR', - 5: 'PERF_VFD_STARVE_CYCLES_UCHE', - 6: 'PERF_VFD_RBUFFER_FULL', - 7: 'PERF_VFD_ATTR_INFO_FIFO_FULL', - 8: 'PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 9: 'PERF_VFD_NUM_ATTRIBUTES', - 10: 'PERF_VFD_UPPER_SHADER_FIBERS', - 11: 'PERF_VFD_LOWER_SHADER_FIBERS', - 12: 'PERF_VFD_MODE_0_FIBERS', - 13: 'PERF_VFD_MODE_1_FIBERS', - 14: 'PERF_VFD_MODE_2_FIBERS', - 15: 'PERF_VFD_MODE_3_FIBERS', - 16: 'PERF_VFD_MODE_4_FIBERS', - 17: 'PERF_VFD_TOTAL_VERTICES', - 18: 'PERF_VFDP_STALL_CYCLES_VFD', - 19: 'PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 20: 'PERF_VFDP_STALL_CYCLES_VFD_PROG', - 21: 'PERF_VFDP_STARVE_CYCLES_PC', - 22: 'PERF_VFDP_VS_STAGE_WAVES', -} -PERF_VFD_BUSY_CYCLES = 0 -PERF_VFD_STALL_CYCLES_UCHE = 1 -PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2 -PERF_VFD_STALL_CYCLES_SP_INFO = 3 -PERF_VFD_STALL_CYCLES_SP_ATTR = 4 -PERF_VFD_STARVE_CYCLES_UCHE = 5 -PERF_VFD_RBUFFER_FULL = 6 -PERF_VFD_ATTR_INFO_FIFO_FULL = 7 -PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8 -PERF_VFD_NUM_ATTRIBUTES = 9 -PERF_VFD_UPPER_SHADER_FIBERS = 10 -PERF_VFD_LOWER_SHADER_FIBERS = 11 -PERF_VFD_MODE_0_FIBERS = 12 -PERF_VFD_MODE_1_FIBERS = 13 -PERF_VFD_MODE_2_FIBERS = 14 -PERF_VFD_MODE_3_FIBERS = 15 -PERF_VFD_MODE_4_FIBERS = 16 -PERF_VFD_TOTAL_VERTICES = 17 -PERF_VFDP_STALL_CYCLES_VFD = 18 -PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19 -PERF_VFDP_STALL_CYCLES_VFD_PROG = 20 -PERF_VFDP_STARVE_CYCLES_PC = 21 -PERF_VFDP_VS_STAGE_WAVES = 22 -a6xx_vfd_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_hlsq_perfcounter_select' -a6xx_hlsq_perfcounter_select__enumvalues = { - 0: 'PERF_HLSQ_BUSY_CYCLES', - 1: 'PERF_HLSQ_STALL_CYCLES_UCHE', - 2: 'PERF_HLSQ_STALL_CYCLES_SP_STATE', - 3: 'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 4: 'PERF_HLSQ_UCHE_LATENCY_CYCLES', - 5: 'PERF_HLSQ_UCHE_LATENCY_COUNT', - 6: 'PERF_HLSQ_FS_STAGE_1X_WAVES', - 7: 'PERF_HLSQ_FS_STAGE_2X_WAVES', - 8: 'PERF_HLSQ_QUADS', - 9: 'PERF_HLSQ_CS_INVOCATIONS', - 10: 'PERF_HLSQ_COMPUTE_DRAWCALLS', - 11: 'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 12: 'PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 13: 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 14: 'PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 15: 'PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 16: 'PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 17: 'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 18: 'PERF_HLSQ_STALL_CYCLES_VPC', - 19: 'PERF_HLSQ_PIXELS', - 20: 'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', -} -PERF_HLSQ_BUSY_CYCLES = 0 -PERF_HLSQ_STALL_CYCLES_UCHE = 1 -PERF_HLSQ_STALL_CYCLES_SP_STATE = 2 -PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3 -PERF_HLSQ_UCHE_LATENCY_CYCLES = 4 -PERF_HLSQ_UCHE_LATENCY_COUNT = 5 -PERF_HLSQ_FS_STAGE_1X_WAVES = 6 -PERF_HLSQ_FS_STAGE_2X_WAVES = 7 -PERF_HLSQ_QUADS = 8 -PERF_HLSQ_CS_INVOCATIONS = 9 -PERF_HLSQ_COMPUTE_DRAWCALLS = 10 -PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11 -PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12 -PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13 -PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14 -PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15 -PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16 -PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17 -PERF_HLSQ_STALL_CYCLES_VPC = 18 -PERF_HLSQ_PIXELS = 19 -PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20 -a6xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vpc_perfcounter_select' -a6xx_vpc_perfcounter_select__enumvalues = { - 0: 'PERF_VPC_BUSY_CYCLES', - 1: 'PERF_VPC_WORKING_CYCLES', - 2: 'PERF_VPC_STALL_CYCLES_UCHE', - 3: 'PERF_VPC_STALL_CYCLES_VFD_WACK', - 4: 'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 5: 'PERF_VPC_STALL_CYCLES_PC', - 6: 'PERF_VPC_STALL_CYCLES_SP_LM', - 7: 'PERF_VPC_STARVE_CYCLES_SP', - 8: 'PERF_VPC_STARVE_CYCLES_LRZ', - 9: 'PERF_VPC_PC_PRIMITIVES', - 10: 'PERF_VPC_SP_COMPONENTS', - 11: 'PERF_VPC_STALL_CYCLES_VPCRAM_POS', - 12: 'PERF_VPC_LRZ_ASSIGN_PRIMITIVES', - 13: 'PERF_VPC_RB_VISIBLE_PRIMITIVES', - 14: 'PERF_VPC_LM_TRANSACTION', - 15: 'PERF_VPC_STREAMOUT_TRANSACTION', - 16: 'PERF_VPC_VS_BUSY_CYCLES', - 17: 'PERF_VPC_PS_BUSY_CYCLES', - 18: 'PERF_VPC_VS_WORKING_CYCLES', - 19: 'PERF_VPC_PS_WORKING_CYCLES', - 20: 'PERF_VPC_STARVE_CYCLES_RB', - 21: 'PERF_VPC_NUM_VPCRAM_READ_POS', - 22: 'PERF_VPC_WIT_FULL_CYCLES', - 23: 'PERF_VPC_VPCRAM_FULL_CYCLES', - 24: 'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', - 25: 'PERF_VPC_NUM_VPCRAM_WRITE', - 26: 'PERF_VPC_NUM_VPCRAM_READ_SO', - 27: 'PERF_VPC_NUM_ATTR_REQ_LM', -} -PERF_VPC_BUSY_CYCLES = 0 -PERF_VPC_WORKING_CYCLES = 1 -PERF_VPC_STALL_CYCLES_UCHE = 2 -PERF_VPC_STALL_CYCLES_VFD_WACK = 3 -PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4 -PERF_VPC_STALL_CYCLES_PC = 5 -PERF_VPC_STALL_CYCLES_SP_LM = 6 -PERF_VPC_STARVE_CYCLES_SP = 7 -PERF_VPC_STARVE_CYCLES_LRZ = 8 -PERF_VPC_PC_PRIMITIVES = 9 -PERF_VPC_SP_COMPONENTS = 10 -PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11 -PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12 -PERF_VPC_RB_VISIBLE_PRIMITIVES = 13 -PERF_VPC_LM_TRANSACTION = 14 -PERF_VPC_STREAMOUT_TRANSACTION = 15 -PERF_VPC_VS_BUSY_CYCLES = 16 -PERF_VPC_PS_BUSY_CYCLES = 17 -PERF_VPC_VS_WORKING_CYCLES = 18 -PERF_VPC_PS_WORKING_CYCLES = 19 -PERF_VPC_STARVE_CYCLES_RB = 20 -PERF_VPC_NUM_VPCRAM_READ_POS = 21 -PERF_VPC_WIT_FULL_CYCLES = 22 -PERF_VPC_VPCRAM_FULL_CYCLES = 23 -PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24 -PERF_VPC_NUM_VPCRAM_WRITE = 25 -PERF_VPC_NUM_VPCRAM_READ_SO = 26 -PERF_VPC_NUM_ATTR_REQ_LM = 27 -a6xx_vpc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tse_perfcounter_select' -a6xx_tse_perfcounter_select__enumvalues = { - 0: 'PERF_TSE_BUSY_CYCLES', - 1: 'PERF_TSE_CLIPPING_CYCLES', - 2: 'PERF_TSE_STALL_CYCLES_RAS', - 3: 'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', - 4: 'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', - 5: 'PERF_TSE_STARVE_CYCLES_PC', - 6: 'PERF_TSE_INPUT_PRIM', - 7: 'PERF_TSE_INPUT_NULL_PRIM', - 8: 'PERF_TSE_TRIVAL_REJ_PRIM', - 9: 'PERF_TSE_CLIPPED_PRIM', - 10: 'PERF_TSE_ZERO_AREA_PRIM', - 11: 'PERF_TSE_FACENESS_CULLED_PRIM', - 12: 'PERF_TSE_ZERO_PIXEL_PRIM', - 13: 'PERF_TSE_OUTPUT_NULL_PRIM', - 14: 'PERF_TSE_OUTPUT_VISIBLE_PRIM', - 15: 'PERF_TSE_CINVOCATION', - 16: 'PERF_TSE_CPRIMITIVES', - 17: 'PERF_TSE_2D_INPUT_PRIM', - 18: 'PERF_TSE_2D_ALIVE_CYCLES', - 19: 'PERF_TSE_CLIP_PLANES', -} -PERF_TSE_BUSY_CYCLES = 0 -PERF_TSE_CLIPPING_CYCLES = 1 -PERF_TSE_STALL_CYCLES_RAS = 2 -PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3 -PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4 -PERF_TSE_STARVE_CYCLES_PC = 5 -PERF_TSE_INPUT_PRIM = 6 -PERF_TSE_INPUT_NULL_PRIM = 7 -PERF_TSE_TRIVAL_REJ_PRIM = 8 -PERF_TSE_CLIPPED_PRIM = 9 -PERF_TSE_ZERO_AREA_PRIM = 10 -PERF_TSE_FACENESS_CULLED_PRIM = 11 -PERF_TSE_ZERO_PIXEL_PRIM = 12 -PERF_TSE_OUTPUT_NULL_PRIM = 13 -PERF_TSE_OUTPUT_VISIBLE_PRIM = 14 -PERF_TSE_CINVOCATION = 15 -PERF_TSE_CPRIMITIVES = 16 -PERF_TSE_2D_INPUT_PRIM = 17 -PERF_TSE_2D_ALIVE_CYCLES = 18 -PERF_TSE_CLIP_PLANES = 19 -a6xx_tse_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ras_perfcounter_select' -a6xx_ras_perfcounter_select__enumvalues = { - 0: 'PERF_RAS_BUSY_CYCLES', - 1: 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 2: 'PERF_RAS_STALL_CYCLES_LRZ', - 3: 'PERF_RAS_STARVE_CYCLES_TSE', - 4: 'PERF_RAS_SUPER_TILES', - 5: 'PERF_RAS_8X4_TILES', - 6: 'PERF_RAS_MASKGEN_ACTIVE', - 7: 'PERF_RAS_FULLY_COVERED_SUPER_TILES', - 8: 'PERF_RAS_FULLY_COVERED_8X4_TILES', - 9: 'PERF_RAS_PRIM_KILLED_INVISILBE', - 10: 'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 11: 'PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 12: 'PERF_RAS_BLOCKS', -} -PERF_RAS_BUSY_CYCLES = 0 -PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1 -PERF_RAS_STALL_CYCLES_LRZ = 2 -PERF_RAS_STARVE_CYCLES_TSE = 3 -PERF_RAS_SUPER_TILES = 4 -PERF_RAS_8X4_TILES = 5 -PERF_RAS_MASKGEN_ACTIVE = 6 -PERF_RAS_FULLY_COVERED_SUPER_TILES = 7 -PERF_RAS_FULLY_COVERED_8X4_TILES = 8 -PERF_RAS_PRIM_KILLED_INVISILBE = 9 -PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10 -PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11 -PERF_RAS_BLOCKS = 12 -a6xx_ras_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_uche_perfcounter_select' -a6xx_uche_perfcounter_select__enumvalues = { - 0: 'PERF_UCHE_BUSY_CYCLES', - 1: 'PERF_UCHE_STALL_CYCLES_ARBITER', - 2: 'PERF_UCHE_VBIF_LATENCY_CYCLES', - 3: 'PERF_UCHE_VBIF_LATENCY_SAMPLES', - 4: 'PERF_UCHE_VBIF_READ_BEATS_TP', - 5: 'PERF_UCHE_VBIF_READ_BEATS_VFD', - 6: 'PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 7: 'PERF_UCHE_VBIF_READ_BEATS_LRZ', - 8: 'PERF_UCHE_VBIF_READ_BEATS_SP', - 9: 'PERF_UCHE_READ_REQUESTS_TP', - 10: 'PERF_UCHE_READ_REQUESTS_VFD', - 11: 'PERF_UCHE_READ_REQUESTS_HLSQ', - 12: 'PERF_UCHE_READ_REQUESTS_LRZ', - 13: 'PERF_UCHE_READ_REQUESTS_SP', - 14: 'PERF_UCHE_WRITE_REQUESTS_LRZ', - 15: 'PERF_UCHE_WRITE_REQUESTS_SP', - 16: 'PERF_UCHE_WRITE_REQUESTS_VPC', - 17: 'PERF_UCHE_WRITE_REQUESTS_VSC', - 18: 'PERF_UCHE_EVICTS', - 19: 'PERF_UCHE_BANK_REQ0', - 20: 'PERF_UCHE_BANK_REQ1', - 21: 'PERF_UCHE_BANK_REQ2', - 22: 'PERF_UCHE_BANK_REQ3', - 23: 'PERF_UCHE_BANK_REQ4', - 24: 'PERF_UCHE_BANK_REQ5', - 25: 'PERF_UCHE_BANK_REQ6', - 26: 'PERF_UCHE_BANK_REQ7', - 27: 'PERF_UCHE_VBIF_READ_BEATS_CH0', - 28: 'PERF_UCHE_VBIF_READ_BEATS_CH1', - 29: 'PERF_UCHE_GMEM_READ_BEATS', - 30: 'PERF_UCHE_TPH_REF_FULL', - 31: 'PERF_UCHE_TPH_VICTIM_FULL', - 32: 'PERF_UCHE_TPH_EXT_FULL', - 33: 'PERF_UCHE_VBIF_STALL_WRITE_DATA', - 34: 'PERF_UCHE_DCMP_LATENCY_SAMPLES', - 35: 'PERF_UCHE_DCMP_LATENCY_CYCLES', - 36: 'PERF_UCHE_VBIF_READ_BEATS_PC', - 37: 'PERF_UCHE_READ_REQUESTS_PC', - 38: 'PERF_UCHE_RAM_READ_REQ', - 39: 'PERF_UCHE_RAM_WRITE_REQ', -} -PERF_UCHE_BUSY_CYCLES = 0 -PERF_UCHE_STALL_CYCLES_ARBITER = 1 -PERF_UCHE_VBIF_LATENCY_CYCLES = 2 -PERF_UCHE_VBIF_LATENCY_SAMPLES = 3 -PERF_UCHE_VBIF_READ_BEATS_TP = 4 -PERF_UCHE_VBIF_READ_BEATS_VFD = 5 -PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6 -PERF_UCHE_VBIF_READ_BEATS_LRZ = 7 -PERF_UCHE_VBIF_READ_BEATS_SP = 8 -PERF_UCHE_READ_REQUESTS_TP = 9 -PERF_UCHE_READ_REQUESTS_VFD = 10 -PERF_UCHE_READ_REQUESTS_HLSQ = 11 -PERF_UCHE_READ_REQUESTS_LRZ = 12 -PERF_UCHE_READ_REQUESTS_SP = 13 -PERF_UCHE_WRITE_REQUESTS_LRZ = 14 -PERF_UCHE_WRITE_REQUESTS_SP = 15 -PERF_UCHE_WRITE_REQUESTS_VPC = 16 -PERF_UCHE_WRITE_REQUESTS_VSC = 17 -PERF_UCHE_EVICTS = 18 -PERF_UCHE_BANK_REQ0 = 19 -PERF_UCHE_BANK_REQ1 = 20 -PERF_UCHE_BANK_REQ2 = 21 -PERF_UCHE_BANK_REQ3 = 22 -PERF_UCHE_BANK_REQ4 = 23 -PERF_UCHE_BANK_REQ5 = 24 -PERF_UCHE_BANK_REQ6 = 25 -PERF_UCHE_BANK_REQ7 = 26 -PERF_UCHE_VBIF_READ_BEATS_CH0 = 27 -PERF_UCHE_VBIF_READ_BEATS_CH1 = 28 -PERF_UCHE_GMEM_READ_BEATS = 29 -PERF_UCHE_TPH_REF_FULL = 30 -PERF_UCHE_TPH_VICTIM_FULL = 31 -PERF_UCHE_TPH_EXT_FULL = 32 -PERF_UCHE_VBIF_STALL_WRITE_DATA = 33 -PERF_UCHE_DCMP_LATENCY_SAMPLES = 34 -PERF_UCHE_DCMP_LATENCY_CYCLES = 35 -PERF_UCHE_VBIF_READ_BEATS_PC = 36 -PERF_UCHE_READ_REQUESTS_PC = 37 -PERF_UCHE_RAM_READ_REQ = 38 -PERF_UCHE_RAM_WRITE_REQ = 39 -a6xx_uche_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tp_perfcounter_select' -a6xx_tp_perfcounter_select__enumvalues = { - 0: 'PERF_TP_BUSY_CYCLES', - 1: 'PERF_TP_STALL_CYCLES_UCHE', - 2: 'PERF_TP_LATENCY_CYCLES', - 3: 'PERF_TP_LATENCY_TRANS', - 4: 'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', - 5: 'PERF_TP_FLAG_CACHE_REQUEST_LATENCY', - 6: 'PERF_TP_L1_CACHELINE_REQUESTS', - 7: 'PERF_TP_L1_CACHELINE_MISSES', - 8: 'PERF_TP_SP_TP_TRANS', - 9: 'PERF_TP_TP_SP_TRANS', - 10: 'PERF_TP_OUTPUT_PIXELS', - 11: 'PERF_TP_FILTER_WORKLOAD_16BIT', - 12: 'PERF_TP_FILTER_WORKLOAD_32BIT', - 13: 'PERF_TP_QUADS_RECEIVED', - 14: 'PERF_TP_QUADS_OFFSET', - 15: 'PERF_TP_QUADS_SHADOW', - 16: 'PERF_TP_QUADS_ARRAY', - 17: 'PERF_TP_QUADS_GRADIENT', - 18: 'PERF_TP_QUADS_1D', - 19: 'PERF_TP_QUADS_2D', - 20: 'PERF_TP_QUADS_BUFFER', - 21: 'PERF_TP_QUADS_3D', - 22: 'PERF_TP_QUADS_CUBE', - 23: 'PERF_TP_DIVERGENT_QUADS_RECEIVED', - 24: 'PERF_TP_PRT_NON_RESIDENT_EVENTS', - 25: 'PERF_TP_OUTPUT_PIXELS_POINT', - 26: 'PERF_TP_OUTPUT_PIXELS_BILINEAR', - 27: 'PERF_TP_OUTPUT_PIXELS_MIP', - 28: 'PERF_TP_OUTPUT_PIXELS_ANISO', - 29: 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 30: 'PERF_TP_FLAG_CACHE_REQUESTS', - 31: 'PERF_TP_FLAG_CACHE_MISSES', - 32: 'PERF_TP_L1_5_L2_REQUESTS', - 33: 'PERF_TP_2D_OUTPUT_PIXELS', - 34: 'PERF_TP_2D_OUTPUT_PIXELS_POINT', - 35: 'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 36: 'PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 37: 'PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 38: 'PERF_TP_TPA2TPC_TRANS', - 39: 'PERF_TP_L1_MISSES_ASTC_1TILE', - 40: 'PERF_TP_L1_MISSES_ASTC_2TILE', - 41: 'PERF_TP_L1_MISSES_ASTC_4TILE', - 42: 'PERF_TP_L1_5_L2_COMPRESS_REQS', - 43: 'PERF_TP_L1_5_L2_COMPRESS_MISS', - 44: 'PERF_TP_L1_BANK_CONFLICT', - 45: 'PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 46: 'PERF_TP_L1_5_MISS_LATENCY_TRANS', - 47: 'PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 48: 'PERF_TP_FRONTEND_WORKING_CYCLES', - 49: 'PERF_TP_L1_TAG_WORKING_CYCLES', - 50: 'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 51: 'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 52: 'PERF_TP_BACKEND_WORKING_CYCLES', - 53: 'PERF_TP_FLAG_CACHE_WORKING_CYCLES', - 54: 'PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 55: 'PERF_TP_STARVE_CYCLES_SP', - 56: 'PERF_TP_STARVE_CYCLES_UCHE', -} -PERF_TP_BUSY_CYCLES = 0 -PERF_TP_STALL_CYCLES_UCHE = 1 -PERF_TP_LATENCY_CYCLES = 2 -PERF_TP_LATENCY_TRANS = 3 -PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4 -PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5 -PERF_TP_L1_CACHELINE_REQUESTS = 6 -PERF_TP_L1_CACHELINE_MISSES = 7 -PERF_TP_SP_TP_TRANS = 8 -PERF_TP_TP_SP_TRANS = 9 -PERF_TP_OUTPUT_PIXELS = 10 -PERF_TP_FILTER_WORKLOAD_16BIT = 11 -PERF_TP_FILTER_WORKLOAD_32BIT = 12 -PERF_TP_QUADS_RECEIVED = 13 -PERF_TP_QUADS_OFFSET = 14 -PERF_TP_QUADS_SHADOW = 15 -PERF_TP_QUADS_ARRAY = 16 -PERF_TP_QUADS_GRADIENT = 17 -PERF_TP_QUADS_1D = 18 -PERF_TP_QUADS_2D = 19 -PERF_TP_QUADS_BUFFER = 20 -PERF_TP_QUADS_3D = 21 -PERF_TP_QUADS_CUBE = 22 -PERF_TP_DIVERGENT_QUADS_RECEIVED = 23 -PERF_TP_PRT_NON_RESIDENT_EVENTS = 24 -PERF_TP_OUTPUT_PIXELS_POINT = 25 -PERF_TP_OUTPUT_PIXELS_BILINEAR = 26 -PERF_TP_OUTPUT_PIXELS_MIP = 27 -PERF_TP_OUTPUT_PIXELS_ANISO = 28 -PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29 -PERF_TP_FLAG_CACHE_REQUESTS = 30 -PERF_TP_FLAG_CACHE_MISSES = 31 -PERF_TP_L1_5_L2_REQUESTS = 32 -PERF_TP_2D_OUTPUT_PIXELS = 33 -PERF_TP_2D_OUTPUT_PIXELS_POINT = 34 -PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35 -PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36 -PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37 -PERF_TP_TPA2TPC_TRANS = 38 -PERF_TP_L1_MISSES_ASTC_1TILE = 39 -PERF_TP_L1_MISSES_ASTC_2TILE = 40 -PERF_TP_L1_MISSES_ASTC_4TILE = 41 -PERF_TP_L1_5_L2_COMPRESS_REQS = 42 -PERF_TP_L1_5_L2_COMPRESS_MISS = 43 -PERF_TP_L1_BANK_CONFLICT = 44 -PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45 -PERF_TP_L1_5_MISS_LATENCY_TRANS = 46 -PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47 -PERF_TP_FRONTEND_WORKING_CYCLES = 48 -PERF_TP_L1_TAG_WORKING_CYCLES = 49 -PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50 -PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51 -PERF_TP_BACKEND_WORKING_CYCLES = 52 -PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53 -PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54 -PERF_TP_STARVE_CYCLES_SP = 55 -PERF_TP_STARVE_CYCLES_UCHE = 56 -a6xx_tp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_sp_perfcounter_select' -a6xx_sp_perfcounter_select__enumvalues = { - 0: 'PERF_SP_BUSY_CYCLES', - 1: 'PERF_SP_ALU_WORKING_CYCLES', - 2: 'PERF_SP_EFU_WORKING_CYCLES', - 3: 'PERF_SP_STALL_CYCLES_VPC', - 4: 'PERF_SP_STALL_CYCLES_TP', - 5: 'PERF_SP_STALL_CYCLES_UCHE', - 6: 'PERF_SP_STALL_CYCLES_RB', - 7: 'PERF_SP_NON_EXECUTION_CYCLES', - 8: 'PERF_SP_WAVE_CONTEXTS', - 9: 'PERF_SP_WAVE_CONTEXT_CYCLES', - 10: 'PERF_SP_FS_STAGE_WAVE_CYCLES', - 11: 'PERF_SP_FS_STAGE_WAVE_SAMPLES', - 12: 'PERF_SP_VS_STAGE_WAVE_CYCLES', - 13: 'PERF_SP_VS_STAGE_WAVE_SAMPLES', - 14: 'PERF_SP_FS_STAGE_DURATION_CYCLES', - 15: 'PERF_SP_VS_STAGE_DURATION_CYCLES', - 16: 'PERF_SP_WAVE_CTRL_CYCLES', - 17: 'PERF_SP_WAVE_LOAD_CYCLES', - 18: 'PERF_SP_WAVE_EMIT_CYCLES', - 19: 'PERF_SP_WAVE_NOP_CYCLES', - 20: 'PERF_SP_WAVE_WAIT_CYCLES', - 21: 'PERF_SP_WAVE_FETCH_CYCLES', - 22: 'PERF_SP_WAVE_IDLE_CYCLES', - 23: 'PERF_SP_WAVE_END_CYCLES', - 24: 'PERF_SP_WAVE_LONG_SYNC_CYCLES', - 25: 'PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 26: 'PERF_SP_WAVE_JOIN_CYCLES', - 27: 'PERF_SP_LM_LOAD_INSTRUCTIONS', - 28: 'PERF_SP_LM_STORE_INSTRUCTIONS', - 29: 'PERF_SP_LM_ATOMICS', - 30: 'PERF_SP_GM_LOAD_INSTRUCTIONS', - 31: 'PERF_SP_GM_STORE_INSTRUCTIONS', - 32: 'PERF_SP_GM_ATOMICS', - 33: 'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 34: 'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 35: 'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 36: 'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 37: 'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 38: 'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 39: 'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 40: 'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 41: 'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 42: 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 43: 'PERF_SP_VS_INSTRUCTIONS', - 44: 'PERF_SP_FS_INSTRUCTIONS', - 45: 'PERF_SP_ADDR_LOCK_COUNT', - 46: 'PERF_SP_UCHE_READ_TRANS', - 47: 'PERF_SP_UCHE_WRITE_TRANS', - 48: 'PERF_SP_EXPORT_VPC_TRANS', - 49: 'PERF_SP_EXPORT_RB_TRANS', - 50: 'PERF_SP_PIXELS_KILLED', - 51: 'PERF_SP_ICL1_REQUESTS', - 52: 'PERF_SP_ICL1_MISSES', - 53: 'PERF_SP_HS_INSTRUCTIONS', - 54: 'PERF_SP_DS_INSTRUCTIONS', - 55: 'PERF_SP_GS_INSTRUCTIONS', - 56: 'PERF_SP_CS_INSTRUCTIONS', - 57: 'PERF_SP_GPR_READ', - 58: 'PERF_SP_GPR_WRITE', - 59: 'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 60: 'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 61: 'PERF_SP_LM_BANK_CONFLICTS', - 62: 'PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 63: 'PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 64: 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 65: 'PERF_SP_LM_WORKING_CYCLES', - 66: 'PERF_SP_DISPATCHER_WORKING_CYCLES', - 67: 'PERF_SP_SEQUENCER_WORKING_CYCLES', - 68: 'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 69: 'PERF_SP_STARVE_CYCLES_HLSQ', - 70: 'PERF_SP_NON_EXECUTION_LS_CYCLES', - 71: 'PERF_SP_WORKING_EU', - 72: 'PERF_SP_ANY_EU_WORKING', - 73: 'PERF_SP_WORKING_EU_FS_STAGE', - 74: 'PERF_SP_ANY_EU_WORKING_FS_STAGE', - 75: 'PERF_SP_WORKING_EU_VS_STAGE', - 76: 'PERF_SP_ANY_EU_WORKING_VS_STAGE', - 77: 'PERF_SP_WORKING_EU_CS_STAGE', - 78: 'PERF_SP_ANY_EU_WORKING_CS_STAGE', - 79: 'PERF_SP_GPR_READ_PREFETCH', - 80: 'PERF_SP_GPR_READ_CONFLICT', - 81: 'PERF_SP_GPR_WRITE_CONFLICT', - 82: 'PERF_SP_GM_LOAD_LATENCY_CYCLES', - 83: 'PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 84: 'PERF_SP_EXECUTABLE_WAVES', -} -PERF_SP_BUSY_CYCLES = 0 -PERF_SP_ALU_WORKING_CYCLES = 1 -PERF_SP_EFU_WORKING_CYCLES = 2 -PERF_SP_STALL_CYCLES_VPC = 3 -PERF_SP_STALL_CYCLES_TP = 4 -PERF_SP_STALL_CYCLES_UCHE = 5 -PERF_SP_STALL_CYCLES_RB = 6 -PERF_SP_NON_EXECUTION_CYCLES = 7 -PERF_SP_WAVE_CONTEXTS = 8 -PERF_SP_WAVE_CONTEXT_CYCLES = 9 -PERF_SP_FS_STAGE_WAVE_CYCLES = 10 -PERF_SP_FS_STAGE_WAVE_SAMPLES = 11 -PERF_SP_VS_STAGE_WAVE_CYCLES = 12 -PERF_SP_VS_STAGE_WAVE_SAMPLES = 13 -PERF_SP_FS_STAGE_DURATION_CYCLES = 14 -PERF_SP_VS_STAGE_DURATION_CYCLES = 15 -PERF_SP_WAVE_CTRL_CYCLES = 16 -PERF_SP_WAVE_LOAD_CYCLES = 17 -PERF_SP_WAVE_EMIT_CYCLES = 18 -PERF_SP_WAVE_NOP_CYCLES = 19 -PERF_SP_WAVE_WAIT_CYCLES = 20 -PERF_SP_WAVE_FETCH_CYCLES = 21 -PERF_SP_WAVE_IDLE_CYCLES = 22 -PERF_SP_WAVE_END_CYCLES = 23 -PERF_SP_WAVE_LONG_SYNC_CYCLES = 24 -PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25 -PERF_SP_WAVE_JOIN_CYCLES = 26 -PERF_SP_LM_LOAD_INSTRUCTIONS = 27 -PERF_SP_LM_STORE_INSTRUCTIONS = 28 -PERF_SP_LM_ATOMICS = 29 -PERF_SP_GM_LOAD_INSTRUCTIONS = 30 -PERF_SP_GM_STORE_INSTRUCTIONS = 31 -PERF_SP_GM_ATOMICS = 32 -PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33 -PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34 -PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35 -PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36 -PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37 -PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38 -PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39 -PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40 -PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41 -PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42 -PERF_SP_VS_INSTRUCTIONS = 43 -PERF_SP_FS_INSTRUCTIONS = 44 -PERF_SP_ADDR_LOCK_COUNT = 45 -PERF_SP_UCHE_READ_TRANS = 46 -PERF_SP_UCHE_WRITE_TRANS = 47 -PERF_SP_EXPORT_VPC_TRANS = 48 -PERF_SP_EXPORT_RB_TRANS = 49 -PERF_SP_PIXELS_KILLED = 50 -PERF_SP_ICL1_REQUESTS = 51 -PERF_SP_ICL1_MISSES = 52 -PERF_SP_HS_INSTRUCTIONS = 53 -PERF_SP_DS_INSTRUCTIONS = 54 -PERF_SP_GS_INSTRUCTIONS = 55 -PERF_SP_CS_INSTRUCTIONS = 56 -PERF_SP_GPR_READ = 57 -PERF_SP_GPR_WRITE = 58 -PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59 -PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60 -PERF_SP_LM_BANK_CONFLICTS = 61 -PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62 -PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63 -PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64 -PERF_SP_LM_WORKING_CYCLES = 65 -PERF_SP_DISPATCHER_WORKING_CYCLES = 66 -PERF_SP_SEQUENCER_WORKING_CYCLES = 67 -PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68 -PERF_SP_STARVE_CYCLES_HLSQ = 69 -PERF_SP_NON_EXECUTION_LS_CYCLES = 70 -PERF_SP_WORKING_EU = 71 -PERF_SP_ANY_EU_WORKING = 72 -PERF_SP_WORKING_EU_FS_STAGE = 73 -PERF_SP_ANY_EU_WORKING_FS_STAGE = 74 -PERF_SP_WORKING_EU_VS_STAGE = 75 -PERF_SP_ANY_EU_WORKING_VS_STAGE = 76 -PERF_SP_WORKING_EU_CS_STAGE = 77 -PERF_SP_ANY_EU_WORKING_CS_STAGE = 78 -PERF_SP_GPR_READ_PREFETCH = 79 -PERF_SP_GPR_READ_CONFLICT = 80 -PERF_SP_GPR_WRITE_CONFLICT = 81 -PERF_SP_GM_LOAD_LATENCY_CYCLES = 82 -PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83 -PERF_SP_EXECUTABLE_WAVES = 84 -a6xx_sp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rb_perfcounter_select' -a6xx_rb_perfcounter_select__enumvalues = { - 0: 'PERF_RB_BUSY_CYCLES', - 1: 'PERF_RB_STALL_CYCLES_HLSQ', - 2: 'PERF_RB_STALL_CYCLES_FIFO0_FULL', - 3: 'PERF_RB_STALL_CYCLES_FIFO1_FULL', - 4: 'PERF_RB_STALL_CYCLES_FIFO2_FULL', - 5: 'PERF_RB_STARVE_CYCLES_SP', - 6: 'PERF_RB_STARVE_CYCLES_LRZ_TILE', - 7: 'PERF_RB_STARVE_CYCLES_CCU', - 8: 'PERF_RB_STARVE_CYCLES_Z_PLANE', - 9: 'PERF_RB_STARVE_CYCLES_BARY_PLANE', - 10: 'PERF_RB_Z_WORKLOAD', - 11: 'PERF_RB_HLSQ_ACTIVE', - 12: 'PERF_RB_Z_READ', - 13: 'PERF_RB_Z_WRITE', - 14: 'PERF_RB_C_READ', - 15: 'PERF_RB_C_WRITE', - 16: 'PERF_RB_TOTAL_PASS', - 17: 'PERF_RB_Z_PASS', - 18: 'PERF_RB_Z_FAIL', - 19: 'PERF_RB_S_FAIL', - 20: 'PERF_RB_BLENDED_FXP_COMPONENTS', - 21: 'PERF_RB_BLENDED_FP16_COMPONENTS', - 22: 'PERF_RB_PS_INVOCATIONS', - 23: 'PERF_RB_2D_ALIVE_CYCLES', - 24: 'PERF_RB_2D_STALL_CYCLES_A2D', - 25: 'PERF_RB_2D_STARVE_CYCLES_SRC', - 26: 'PERF_RB_2D_STARVE_CYCLES_SP', - 27: 'PERF_RB_2D_STARVE_CYCLES_DST', - 28: 'PERF_RB_2D_VALID_PIXELS', - 29: 'PERF_RB_3D_PIXELS', - 30: 'PERF_RB_BLENDER_WORKING_CYCLES', - 31: 'PERF_RB_ZPROC_WORKING_CYCLES', - 32: 'PERF_RB_CPROC_WORKING_CYCLES', - 33: 'PERF_RB_SAMPLER_WORKING_CYCLES', - 34: 'PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 35: 'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 36: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 37: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 38: 'PERF_RB_STALL_CYCLES_VPC', - 39: 'PERF_RB_2D_INPUT_TRANS', - 40: 'PERF_RB_2D_OUTPUT_RB_DST_TRANS', - 41: 'PERF_RB_2D_OUTPUT_RB_SRC_TRANS', - 42: 'PERF_RB_BLENDED_FP32_COMPONENTS', - 43: 'PERF_RB_COLOR_PIX_TILES', - 44: 'PERF_RB_STALL_CYCLES_CCU', - 45: 'PERF_RB_EARLY_Z_ARB3_GRANT', - 46: 'PERF_RB_LATE_Z_ARB3_GRANT', - 47: 'PERF_RB_EARLY_Z_SKIP_GRANT', -} -PERF_RB_BUSY_CYCLES = 0 -PERF_RB_STALL_CYCLES_HLSQ = 1 -PERF_RB_STALL_CYCLES_FIFO0_FULL = 2 -PERF_RB_STALL_CYCLES_FIFO1_FULL = 3 -PERF_RB_STALL_CYCLES_FIFO2_FULL = 4 -PERF_RB_STARVE_CYCLES_SP = 5 -PERF_RB_STARVE_CYCLES_LRZ_TILE = 6 -PERF_RB_STARVE_CYCLES_CCU = 7 -PERF_RB_STARVE_CYCLES_Z_PLANE = 8 -PERF_RB_STARVE_CYCLES_BARY_PLANE = 9 -PERF_RB_Z_WORKLOAD = 10 -PERF_RB_HLSQ_ACTIVE = 11 -PERF_RB_Z_READ = 12 -PERF_RB_Z_WRITE = 13 -PERF_RB_C_READ = 14 -PERF_RB_C_WRITE = 15 -PERF_RB_TOTAL_PASS = 16 -PERF_RB_Z_PASS = 17 -PERF_RB_Z_FAIL = 18 -PERF_RB_S_FAIL = 19 -PERF_RB_BLENDED_FXP_COMPONENTS = 20 -PERF_RB_BLENDED_FP16_COMPONENTS = 21 -PERF_RB_PS_INVOCATIONS = 22 -PERF_RB_2D_ALIVE_CYCLES = 23 -PERF_RB_2D_STALL_CYCLES_A2D = 24 -PERF_RB_2D_STARVE_CYCLES_SRC = 25 -PERF_RB_2D_STARVE_CYCLES_SP = 26 -PERF_RB_2D_STARVE_CYCLES_DST = 27 -PERF_RB_2D_VALID_PIXELS = 28 -PERF_RB_3D_PIXELS = 29 -PERF_RB_BLENDER_WORKING_CYCLES = 30 -PERF_RB_ZPROC_WORKING_CYCLES = 31 -PERF_RB_CPROC_WORKING_CYCLES = 32 -PERF_RB_SAMPLER_WORKING_CYCLES = 33 -PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34 -PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35 -PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36 -PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37 -PERF_RB_STALL_CYCLES_VPC = 38 -PERF_RB_2D_INPUT_TRANS = 39 -PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40 -PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41 -PERF_RB_BLENDED_FP32_COMPONENTS = 42 -PERF_RB_COLOR_PIX_TILES = 43 -PERF_RB_STALL_CYCLES_CCU = 44 -PERF_RB_EARLY_Z_ARB3_GRANT = 45 -PERF_RB_LATE_Z_ARB3_GRANT = 46 -PERF_RB_EARLY_Z_SKIP_GRANT = 47 -a6xx_rb_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vsc_perfcounter_select' -a6xx_vsc_perfcounter_select__enumvalues = { - 0: 'PERF_VSC_BUSY_CYCLES', - 1: 'PERF_VSC_WORKING_CYCLES', - 2: 'PERF_VSC_STALL_CYCLES_UCHE', - 3: 'PERF_VSC_EOT_NUM', - 4: 'PERF_VSC_INPUT_TILES', -} -PERF_VSC_BUSY_CYCLES = 0 -PERF_VSC_WORKING_CYCLES = 1 -PERF_VSC_STALL_CYCLES_UCHE = 2 -PERF_VSC_EOT_NUM = 3 -PERF_VSC_INPUT_TILES = 4 -a6xx_vsc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ccu_perfcounter_select' -a6xx_ccu_perfcounter_select__enumvalues = { - 0: 'PERF_CCU_BUSY_CYCLES', - 1: 'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 2: 'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 3: 'PERF_CCU_STARVE_CYCLES_FLAG_RETURN', - 4: 'PERF_CCU_DEPTH_BLOCKS', - 5: 'PERF_CCU_COLOR_BLOCKS', - 6: 'PERF_CCU_DEPTH_BLOCK_HIT', - 7: 'PERF_CCU_COLOR_BLOCK_HIT', - 8: 'PERF_CCU_PARTIAL_BLOCK_READ', - 9: 'PERF_CCU_GMEM_READ', - 10: 'PERF_CCU_GMEM_WRITE', - 11: 'PERF_CCU_DEPTH_READ_FLAG0_COUNT', - 12: 'PERF_CCU_DEPTH_READ_FLAG1_COUNT', - 13: 'PERF_CCU_DEPTH_READ_FLAG2_COUNT', - 14: 'PERF_CCU_DEPTH_READ_FLAG3_COUNT', - 15: 'PERF_CCU_DEPTH_READ_FLAG4_COUNT', - 16: 'PERF_CCU_DEPTH_READ_FLAG5_COUNT', - 17: 'PERF_CCU_DEPTH_READ_FLAG6_COUNT', - 18: 'PERF_CCU_DEPTH_READ_FLAG8_COUNT', - 19: 'PERF_CCU_COLOR_READ_FLAG0_COUNT', - 20: 'PERF_CCU_COLOR_READ_FLAG1_COUNT', - 21: 'PERF_CCU_COLOR_READ_FLAG2_COUNT', - 22: 'PERF_CCU_COLOR_READ_FLAG3_COUNT', - 23: 'PERF_CCU_COLOR_READ_FLAG4_COUNT', - 24: 'PERF_CCU_COLOR_READ_FLAG5_COUNT', - 25: 'PERF_CCU_COLOR_READ_FLAG6_COUNT', - 26: 'PERF_CCU_COLOR_READ_FLAG8_COUNT', - 27: 'PERF_CCU_2D_RD_REQ', - 28: 'PERF_CCU_2D_WR_REQ', -} -PERF_CCU_BUSY_CYCLES = 0 -PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1 -PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2 -PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3 -PERF_CCU_DEPTH_BLOCKS = 4 -PERF_CCU_COLOR_BLOCKS = 5 -PERF_CCU_DEPTH_BLOCK_HIT = 6 -PERF_CCU_COLOR_BLOCK_HIT = 7 -PERF_CCU_PARTIAL_BLOCK_READ = 8 -PERF_CCU_GMEM_READ = 9 -PERF_CCU_GMEM_WRITE = 10 -PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11 -PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12 -PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13 -PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14 -PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15 -PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16 -PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17 -PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18 -PERF_CCU_COLOR_READ_FLAG0_COUNT = 19 -PERF_CCU_COLOR_READ_FLAG1_COUNT = 20 -PERF_CCU_COLOR_READ_FLAG2_COUNT = 21 -PERF_CCU_COLOR_READ_FLAG3_COUNT = 22 -PERF_CCU_COLOR_READ_FLAG4_COUNT = 23 -PERF_CCU_COLOR_READ_FLAG5_COUNT = 24 -PERF_CCU_COLOR_READ_FLAG6_COUNT = 25 -PERF_CCU_COLOR_READ_FLAG8_COUNT = 26 -PERF_CCU_2D_RD_REQ = 27 -PERF_CCU_2D_WR_REQ = 28 -a6xx_ccu_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_lrz_perfcounter_select' -a6xx_lrz_perfcounter_select__enumvalues = { - 0: 'PERF_LRZ_BUSY_CYCLES', - 1: 'PERF_LRZ_STARVE_CYCLES_RAS', - 2: 'PERF_LRZ_STALL_CYCLES_RB', - 3: 'PERF_LRZ_STALL_CYCLES_VSC', - 4: 'PERF_LRZ_STALL_CYCLES_VPC', - 5: 'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', - 6: 'PERF_LRZ_STALL_CYCLES_UCHE', - 7: 'PERF_LRZ_LRZ_READ', - 8: 'PERF_LRZ_LRZ_WRITE', - 9: 'PERF_LRZ_READ_LATENCY', - 10: 'PERF_LRZ_MERGE_CACHE_UPDATING', - 11: 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 12: 'PERF_LRZ_PRIM_KILLED_BY_LRZ', - 13: 'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 14: 'PERF_LRZ_FULL_8X8_TILES', - 15: 'PERF_LRZ_PARTIAL_8X8_TILES', - 16: 'PERF_LRZ_TILE_KILLED', - 17: 'PERF_LRZ_TOTAL_PIXEL', - 18: 'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 19: 'PERF_LRZ_FULLY_COVERED_TILES', - 20: 'PERF_LRZ_PARTIAL_COVERED_TILES', - 21: 'PERF_LRZ_FEEDBACK_ACCEPT', - 22: 'PERF_LRZ_FEEDBACK_DISCARD', - 23: 'PERF_LRZ_FEEDBACK_STALL', - 24: 'PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 25: 'PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 26: 'PERF_LRZ_STALL_CYCLES_VC', - 27: 'PERF_LRZ_RAS_MASK_TRANS', -} -PERF_LRZ_BUSY_CYCLES = 0 -PERF_LRZ_STARVE_CYCLES_RAS = 1 -PERF_LRZ_STALL_CYCLES_RB = 2 -PERF_LRZ_STALL_CYCLES_VSC = 3 -PERF_LRZ_STALL_CYCLES_VPC = 4 -PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5 -PERF_LRZ_STALL_CYCLES_UCHE = 6 -PERF_LRZ_LRZ_READ = 7 -PERF_LRZ_LRZ_WRITE = 8 -PERF_LRZ_READ_LATENCY = 9 -PERF_LRZ_MERGE_CACHE_UPDATING = 10 -PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11 -PERF_LRZ_PRIM_KILLED_BY_LRZ = 12 -PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13 -PERF_LRZ_FULL_8X8_TILES = 14 -PERF_LRZ_PARTIAL_8X8_TILES = 15 -PERF_LRZ_TILE_KILLED = 16 -PERF_LRZ_TOTAL_PIXEL = 17 -PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18 -PERF_LRZ_FULLY_COVERED_TILES = 19 -PERF_LRZ_PARTIAL_COVERED_TILES = 20 -PERF_LRZ_FEEDBACK_ACCEPT = 21 -PERF_LRZ_FEEDBACK_DISCARD = 22 -PERF_LRZ_FEEDBACK_STALL = 23 -PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24 -PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25 -PERF_LRZ_STALL_CYCLES_VC = 26 -PERF_LRZ_RAS_MASK_TRANS = 27 -a6xx_lrz_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_cmp_perfcounter_select' -a6xx_cmp_perfcounter_select__enumvalues = { - 0: 'PERF_CMPDECMP_STALL_CYCLES_ARB', - 1: 'PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 2: 'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 3: 'PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 4: 'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 5: 'PERF_CMPDECMP_VBIF_READ_REQUEST', - 6: 'PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 7: 'PERF_CMPDECMP_VBIF_READ_DATA', - 8: 'PERF_CMPDECMP_VBIF_WRITE_DATA', - 9: 'PERF_CMPDECMP_FLAG_FETCH_CYCLES', - 10: 'PERF_CMPDECMP_FLAG_FETCH_SAMPLES', - 11: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 12: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 13: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 14: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 15: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 16: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 17: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 18: 'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 19: 'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 20: 'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 21: 'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 22: 'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 23: 'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 24: 'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 25: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', - 26: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', - 27: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', - 28: 'PERF_CMPDECMP_2D_RD_DATA', - 29: 'PERF_CMPDECMP_2D_WR_DATA', - 30: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 31: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 32: 'PERF_CMPDECMP_2D_OUTPUT_TRANS', - 33: 'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 34: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 35: 'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 36: 'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 37: 'PERF_CMPDECMP_2D_BUSY_CYCLES', - 38: 'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', - 39: 'PERF_CMPDECMP_2D_PIXELS', -} -PERF_CMPDECMP_STALL_CYCLES_ARB = 0 -PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1 -PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2 -PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3 -PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4 -PERF_CMPDECMP_VBIF_READ_REQUEST = 5 -PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6 -PERF_CMPDECMP_VBIF_READ_DATA = 7 -PERF_CMPDECMP_VBIF_WRITE_DATA = 8 -PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9 -PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10 -PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11 -PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12 -PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13 -PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14 -PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15 -PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16 -PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17 -PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18 -PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19 -PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20 -PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21 -PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22 -PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23 -PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27 -PERF_CMPDECMP_2D_RD_DATA = 28 -PERF_CMPDECMP_2D_WR_DATA = 29 -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30 -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31 -PERF_CMPDECMP_2D_OUTPUT_TRANS = 32 -PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33 -PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34 -PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35 -PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36 -PERF_CMPDECMP_2D_BUSY_CYCLES = 37 -PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38 -PERF_CMPDECMP_2D_PIXELS = 39 -a6xx_cmp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_2d_ifmt' -a6xx_2d_ifmt__enumvalues = { - 16: 'R2D_UNORM8', - 7: 'R2D_INT32', - 6: 'R2D_INT16', - 5: 'R2D_INT8', - 4: 'R2D_FLOAT32', - 3: 'R2D_FLOAT16', - 1: 'R2D_UNORM8_SRGB', - 0: 'R2D_RAW', -} -R2D_UNORM8 = 16 -R2D_INT32 = 7 -R2D_INT16 = 6 -R2D_INT8 = 5 -R2D_FLOAT32 = 4 -R2D_FLOAT16 = 3 -R2D_UNORM8_SRGB = 1 -R2D_RAW = 0 -a6xx_2d_ifmt = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ztest_mode' -a6xx_ztest_mode__enumvalues = { - 0: 'A6XX_EARLY_Z', - 1: 'A6XX_LATE_Z', - 2: 'A6XX_EARLY_LRZ_LATE_Z', - 3: 'A6XX_INVALID_ZTEST', -} -A6XX_EARLY_Z = 0 -A6XX_LATE_Z = 1 -A6XX_EARLY_LRZ_LATE_Z = 2 -A6XX_INVALID_ZTEST = 3 -a6xx_ztest_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tess_spacing' -a6xx_tess_spacing__enumvalues = { - 0: 'TESS_EQUAL', - 2: 'TESS_FRACTIONAL_ODD', - 3: 'TESS_FRACTIONAL_EVEN', -} -TESS_EQUAL = 0 -TESS_FRACTIONAL_ODD = 2 -TESS_FRACTIONAL_EVEN = 3 -a6xx_tess_spacing = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tess_output' -a6xx_tess_output__enumvalues = { - 0: 'TESS_POINTS', - 1: 'TESS_LINES', - 2: 'TESS_CW_TRIS', - 3: 'TESS_CCW_TRIS', -} -TESS_POINTS = 0 -TESS_LINES = 1 -TESS_CW_TRIS = 2 -TESS_CCW_TRIS = 3 -a6xx_tess_output = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cp_perfcounter_select' -a7xx_cp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CP_NEVER_COUNT', - 1: 'A7XX_PERF_CP_ALWAYS_COUNT', - 2: 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', - 3: 'A7XX_PERF_CP_BUSY_CYCLES', - 4: 'A7XX_PERF_CP_NUM_PREEMPTIONS', - 5: 'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', - 6: 'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 7: 'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 8: 'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 9: 'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', - 10: 'A7XX_PERF_CP_MODE_SWITCH', - 11: 'A7XX_PERF_CP_ZPASS_DONE', - 12: 'A7XX_PERF_CP_CONTEXT_DONE', - 13: 'A7XX_PERF_CP_CACHE_FLUSH', - 14: 'A7XX_PERF_CP_LONG_PREEMPTIONS', - 15: 'A7XX_PERF_CP_SQE_I_CACHE_STARVE', - 16: 'A7XX_PERF_CP_SQE_IDLE', - 17: 'A7XX_PERF_CP_SQE_PM4_STARVE_RB', - 18: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB1', - 19: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB2', - 20: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB3', - 21: 'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', - 22: 'A7XX_PERF_CP_SQE_PM4_STARVE_SDS', - 23: 'A7XX_PERF_CP_SQE_MRB_STARVE', - 24: 'A7XX_PERF_CP_SQE_RRB_STARVE', - 25: 'A7XX_PERF_CP_SQE_VSD_STARVE', - 26: 'A7XX_PERF_CP_VSD_DECODE_STARVE', - 27: 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL', - 28: 'A7XX_PERF_CP_SQE_SYNC_STALL', - 29: 'A7XX_PERF_CP_SQE_PM4_WFI_STALL', - 30: 'A7XX_PERF_CP_SQE_SYS_WFI_STALL', - 31: 'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', - 32: 'A7XX_PERF_CP_OUTPUT_BLOCKED', - 33: 'A7XX_PERF_CP_SQE_T4_EXEC', - 34: 'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', - 35: 'A7XX_PERF_CP_SQE_SAVE_SDS_STATE', - 36: 'A7XX_PERF_CP_SQE_DRAW_EXEC', - 37: 'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 38: 'A7XX_PERF_CP_SQE_EXEC_PROFILED', - 39: 'A7XX_PERF_CP_MEMORY_POOL_EMPTY', - 40: 'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', - 41: 'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 42: 'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', - 43: 'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 44: 'A7XX_PERF_CP_AHB_STALL_SQE_GMU', - 45: 'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', - 46: 'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', - 47: 'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', - 48: 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', - 49: 'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', - 50: 'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', - 51: 'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', - 52: 'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', - 53: 'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', - 54: 'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', - 55: 'A7XX_PERF_CP_CLUSTER_PS_EMPTY', - 56: 'A7XX_PERF_CP_PM4_DATA', - 57: 'A7XX_PERF_CP_PM4_HEADERS', - 58: 'A7XX_PERF_CP_VBIF_READ_BEATS', - 59: 'A7XX_PERF_CP_VBIF_WRITE_BEATS', - 60: 'A7XX_PERF_CP_SQE_INSTR_COUNTER', - 61: 'A7XX_PERF_CP_CLUSTER_FE_US_FULL', - 62: 'A7XX_PERF_CP_CLUSTER_FE_S_FULL', - 63: 'A7XX_PERF_CP_CLUSTER_SP_VS_FULL', - 64: 'A7XX_PERF_CP_CLUSTER_VPC_US_FULL', - 65: 'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', - 66: 'A7XX_PERF_CP_CLUSTER_GRAS_FULL', - 67: 'A7XX_PERF_CP_CLUSTER_SP_PS_FULL', - 68: 'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', - 69: 'A7XX_PERF_CP_CLUSTER_PS_FULL', - 70: 'A7XX_PERF_CP_ICACHE_MISSES', - 71: 'A7XX_PERF_CP_ICACHE_HITS', - 72: 'A7XX_PERF_CP_ICACHE_STALL', - 73: 'A7XX_PERF_CP_DCACHE_MISSES', - 74: 'A7XX_PERF_CP_DCACHE_HITS', - 75: 'A7XX_PERF_CP_DCACHE_STALLS', - 76: 'A7XX_PERF_CP_AQE_SQE_STALL', - 77: 'A7XX_PERF_CP_SQE_AQE_STARVE', - 78: 'A7XX_PERF_CP_ISR_CYCLES', - 79: 'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', - 80: 'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', - 81: 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', - 82: 'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', - 83: 'A7XX_PERF_CP_S_SKEW_BUFFER_FULL', - 84: 'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', -} -A7XX_PERF_CP_NEVER_COUNT = 0 -A7XX_PERF_CP_ALWAYS_COUNT = 1 -A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = 2 -A7XX_PERF_CP_BUSY_CYCLES = 3 -A7XX_PERF_CP_NUM_PREEMPTIONS = 4 -A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = 5 -A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 6 -A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = 7 -A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 8 -A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = 9 -A7XX_PERF_CP_MODE_SWITCH = 10 -A7XX_PERF_CP_ZPASS_DONE = 11 -A7XX_PERF_CP_CONTEXT_DONE = 12 -A7XX_PERF_CP_CACHE_FLUSH = 13 -A7XX_PERF_CP_LONG_PREEMPTIONS = 14 -A7XX_PERF_CP_SQE_I_CACHE_STARVE = 15 -A7XX_PERF_CP_SQE_IDLE = 16 -A7XX_PERF_CP_SQE_PM4_STARVE_RB = 17 -A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = 18 -A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = 19 -A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = 20 -A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = 21 -A7XX_PERF_CP_SQE_PM4_STARVE_SDS = 22 -A7XX_PERF_CP_SQE_MRB_STARVE = 23 -A7XX_PERF_CP_SQE_RRB_STARVE = 24 -A7XX_PERF_CP_SQE_VSD_STARVE = 25 -A7XX_PERF_CP_VSD_DECODE_STARVE = 26 -A7XX_PERF_CP_SQE_PIPE_OUT_STALL = 27 -A7XX_PERF_CP_SQE_SYNC_STALL = 28 -A7XX_PERF_CP_SQE_PM4_WFI_STALL = 29 -A7XX_PERF_CP_SQE_SYS_WFI_STALL = 30 -A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = 31 -A7XX_PERF_CP_OUTPUT_BLOCKED = 32 -A7XX_PERF_CP_SQE_T4_EXEC = 33 -A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = 34 -A7XX_PERF_CP_SQE_SAVE_SDS_STATE = 35 -A7XX_PERF_CP_SQE_DRAW_EXEC = 36 -A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 37 -A7XX_PERF_CP_SQE_EXEC_PROFILED = 38 -A7XX_PERF_CP_MEMORY_POOL_EMPTY = 39 -A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = 40 -A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = 41 -A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = 42 -A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = 43 -A7XX_PERF_CP_AHB_STALL_SQE_GMU = 44 -A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = 45 -A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = 46 -A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = 47 -A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = 48 -A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = 49 -A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = 50 -A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = 51 -A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = 52 -A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = 53 -A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = 54 -A7XX_PERF_CP_CLUSTER_PS_EMPTY = 55 -A7XX_PERF_CP_PM4_DATA = 56 -A7XX_PERF_CP_PM4_HEADERS = 57 -A7XX_PERF_CP_VBIF_READ_BEATS = 58 -A7XX_PERF_CP_VBIF_WRITE_BEATS = 59 -A7XX_PERF_CP_SQE_INSTR_COUNTER = 60 -A7XX_PERF_CP_CLUSTER_FE_US_FULL = 61 -A7XX_PERF_CP_CLUSTER_FE_S_FULL = 62 -A7XX_PERF_CP_CLUSTER_SP_VS_FULL = 63 -A7XX_PERF_CP_CLUSTER_VPC_US_FULL = 64 -A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = 65 -A7XX_PERF_CP_CLUSTER_GRAS_FULL = 66 -A7XX_PERF_CP_CLUSTER_SP_PS_FULL = 67 -A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = 68 -A7XX_PERF_CP_CLUSTER_PS_FULL = 69 -A7XX_PERF_CP_ICACHE_MISSES = 70 -A7XX_PERF_CP_ICACHE_HITS = 71 -A7XX_PERF_CP_ICACHE_STALL = 72 -A7XX_PERF_CP_DCACHE_MISSES = 73 -A7XX_PERF_CP_DCACHE_HITS = 74 -A7XX_PERF_CP_DCACHE_STALLS = 75 -A7XX_PERF_CP_AQE_SQE_STALL = 76 -A7XX_PERF_CP_SQE_AQE_STARVE = 77 -A7XX_PERF_CP_ISR_CYCLES = 78 -A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = 79 -A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = 80 -A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = 81 -A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = 82 -A7XX_PERF_CP_S_SKEW_BUFFER_FULL = 83 -A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = 84 -a7xx_cp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_rbbm_perfcounter_select' -a7xx_rbbm_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RBBM_NEVER_COUNT', - 1: 'A7XX_PERF_RBBM_US_ALWAYS_COUNT', - 2: 'A7XX_PERF_RBBM_US_ALWAYS_ON', - 3: 'A7XX_PERF_RBBM_US_STATUS_MASKED', - 4: 'A7XX_PERF_RBBM_US_PC_BUSY', - 5: 'A7XX_PERF_RBBM_US_COM_BUSY', - 6: 'A7XX_PERF_RBBM_US_DCOM_BUSY', - 7: 'A7XX_PERF_RBBM_US_VBIF_BUSY', - 8: 'A7XX_PERF_RBBM_US_VSC_BUSY', - 9: 'A7XX_PERF_RBBM_US_UCHE_BUSY', - 10: 'A7XX_PERF_RBBM_US_HLSQ_BUSY', - 11: 'A7XX_PERF_RBBM_S_HLSQ_BUSY', - 12: 'A7XX_PERF_RBBM_S_PC_BUSY', - 13: 'A7XX_PERF_RBBM_S_TESS_BUSY', - 14: 'A7XX_PERF_RBBM_S_TSEFE_BUSY', - 15: 'A7XX_PERF_RBBM_S_TSEBE_BUSY', - 16: 'A7XX_PERF_RBBM_S_RAS_BUSY', -} -A7XX_PERF_RBBM_NEVER_COUNT = 0 -A7XX_PERF_RBBM_US_ALWAYS_COUNT = 1 -A7XX_PERF_RBBM_US_ALWAYS_ON = 2 -A7XX_PERF_RBBM_US_STATUS_MASKED = 3 -A7XX_PERF_RBBM_US_PC_BUSY = 4 -A7XX_PERF_RBBM_US_COM_BUSY = 5 -A7XX_PERF_RBBM_US_DCOM_BUSY = 6 -A7XX_PERF_RBBM_US_VBIF_BUSY = 7 -A7XX_PERF_RBBM_US_VSC_BUSY = 8 -A7XX_PERF_RBBM_US_UCHE_BUSY = 9 -A7XX_PERF_RBBM_US_HLSQ_BUSY = 10 -A7XX_PERF_RBBM_S_HLSQ_BUSY = 11 -A7XX_PERF_RBBM_S_PC_BUSY = 12 -A7XX_PERF_RBBM_S_TESS_BUSY = 13 -A7XX_PERF_RBBM_S_TSEFE_BUSY = 14 -A7XX_PERF_RBBM_S_TSEBE_BUSY = 15 -A7XX_PERF_RBBM_S_RAS_BUSY = 16 -a7xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_pc_perfcounter_select' -a7xx_pc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_PC_NEVER_COUNT', - 1: 'A7XX_PERF_PC_US_BUSY_CYCLES', - 2: 'A7XX_PERF_PC_US_WORKING_CYCLES', - 3: 'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', - 4: 'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', - 5: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', - 6: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', - 7: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', - 8: 'A7XX_PERF_PC_US_STARVE_CYCLES_DI', - 9: 'A7XX_PERF_PC_US_VIS_STREAMS_LOADED', - 10: 'A7XX_PERF_PC_US_INSTANCES', - 11: 'A7XX_PERF_PC_US_DEAD_PRIM', - 12: 'A7XX_PERF_PC_US_SLICE_LIVE_PRIM', - 13: 'A7XX_PERF_PC_US_3D_DRAWCALLS', - 14: 'A7XX_PERF_PC_US_2D_DRAWCALLS', - 15: 'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', - 16: 'A7XX_PERF_PC_US_MESH_DRAWS', - 17: 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS', - 18: 'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', - 19: 'A7XX_PERF_PC_US_MESH_DEAD_PRIM', - 20: 'A7XX_PERF_PC_US_MESH_LIVE_PRIM', - 21: 'A7XX_PERF_PC_US_MESH_PA_EN_PRIM', - 22: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', - 23: 'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', - 24: 'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', - 25: 'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', - 26: 'A7XX_PERF_PC_US_PREDRAW_STALLS', - 27: 'A7XX_PERF_PC_US_DP0_INPUT_STALLS', - 28: 'A7XX_PERF_PC_US_DP1_INPUT_STALLS', - 29: 'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', - 30: 'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', - 31: 'A7XX_PERF_PC_US_PASSPAIR_STALL', - 32: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', - 33: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', - 34: 'A7XX_PERF_PC_US_UCHE_0_TRANS', - 35: 'A7XX_PERF_PC_US_UCHE_1_TRANS', - 36: 'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', - 37: 'A7XX_PERF_PC_US_BV_STARVED_BY_RARB', - 38: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', - 39: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', - 40: 'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', - 41: 'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', - 42: 'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', - 43: 'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', - 44: 'A7XX_PERF_PC_US_DP0_RARB_FULL', - 45: 'A7XX_PERF_PC_US_DP1_RARB_FULL', - 46: 'A7XX_PERF_PC_US_DP0_LIVE_PRIM', - 47: 'A7XX_PERF_PC_US_DP1_LIVE_PRIM', - 48: 'A7XX_PERF_PC_US_BV2BR_SWITCH', - 49: 'A7XX_PERF_PC_US_BR2BV_SWITCH', - 50: 'A7XX_PERF_PC_US_STALL_CYCLES_PC_S', - 51: 'A7XX_PERF_PC_RESERVED_51', - 52: 'A7XX_PERF_PC_RESERVED_52', - 53: 'A7XX_PERF_PC_RESERVED_53', - 54: 'A7XX_PERF_PC_RESERVED_54', - 55: 'A7XX_PERF_PC_RESERVED_55', - 56: 'A7XX_PERF_PC_RESERVED_56', - 57: 'A7XX_PERF_PC_RESERVED_57', - 58: 'A7XX_PERF_PC_RESERVED_58', - 59: 'A7XX_PERF_PC_RESERVED_59', - 60: 'A7XX_PERF_PC_S_BUSY_CYCLES', - 61: 'A7XX_PERF_PC_S_WORKING_CYCLES', - 62: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD', - 63: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', - 64: 'A7XX_PERF_PC_S_STALL_CYCLES_TESS', - 65: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', - 66: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', - 67: 'A7XX_PERF_PC_S_VPC_PRIMITIVES', - 68: 'A7XX_PERF_PC_S_VERTEX_HITS', - 69: 'A7XX_PERF_PC_S_IA_VERTICES', - 70: 'A7XX_PERF_PC_S_IA_PRIMITIVES', - 71: 'A7XX_PERF_PC_S_HS_INVOCATIONS', - 72: 'A7XX_PERF_PC_S_DS_INVOCATIONS', - 73: 'A7XX_PERF_PC_S_VS_INVOCATIONS', - 74: 'A7XX_PERF_PC_S_GS_INVOCATIONS', - 75: 'A7XX_PERF_PC_S_DS_PRIMITIVES', - 76: 'A7XX_PERF_PC_S_TESS_BUSY_CYCLES', - 77: 'A7XX_PERF_PC_S_TESS_WORKING_CYCLES', - 78: 'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', - 79: 'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', - 80: 'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', - 81: 'A7XX_PERF_PC_S_TESS_PID_ACTIVE', - 82: 'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', - 83: 'A7XX_PERF_PC_S_TESS_FACTOR_TRANS', - 84: 'A7XX_PERF_PC_S_TESS_PC_UV_TRANS', - 85: 'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', - 86: 'A7XX_PERF_PC_S_MESH_VS_WAVES', -} -A7XX_PERF_PC_NEVER_COUNT = 0 -A7XX_PERF_PC_US_BUSY_CYCLES = 1 -A7XX_PERF_PC_US_WORKING_CYCLES = 2 -A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = 3 -A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = 4 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = 5 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = 6 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = 7 -A7XX_PERF_PC_US_STARVE_CYCLES_DI = 8 -A7XX_PERF_PC_US_VIS_STREAMS_LOADED = 9 -A7XX_PERF_PC_US_INSTANCES = 10 -A7XX_PERF_PC_US_DEAD_PRIM = 11 -A7XX_PERF_PC_US_SLICE_LIVE_PRIM = 12 -A7XX_PERF_PC_US_3D_DRAWCALLS = 13 -A7XX_PERF_PC_US_2D_DRAWCALLS = 14 -A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = 15 -A7XX_PERF_PC_US_MESH_DRAWS = 16 -A7XX_PERF_PC_US_MESH_DEAD_DRAWS = 17 -A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = 18 -A7XX_PERF_PC_US_MESH_DEAD_PRIM = 19 -A7XX_PERF_PC_US_MESH_LIVE_PRIM = 20 -A7XX_PERF_PC_US_MESH_PA_EN_PRIM = 21 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = 22 -A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = 23 -A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = 24 -A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = 25 -A7XX_PERF_PC_US_PREDRAW_STALLS = 26 -A7XX_PERF_PC_US_DP0_INPUT_STALLS = 27 -A7XX_PERF_PC_US_DP1_INPUT_STALLS = 28 -A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = 29 -A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = 30 -A7XX_PERF_PC_US_PASSPAIR_STALL = 31 -A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = 32 -A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = 33 -A7XX_PERF_PC_US_UCHE_0_TRANS = 34 -A7XX_PERF_PC_US_UCHE_1_TRANS = 35 -A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = 36 -A7XX_PERF_PC_US_BV_STARVED_BY_RARB = 37 -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = 38 -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = 39 -A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = 40 -A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = 41 -A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = 42 -A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = 43 -A7XX_PERF_PC_US_DP0_RARB_FULL = 44 -A7XX_PERF_PC_US_DP1_RARB_FULL = 45 -A7XX_PERF_PC_US_DP0_LIVE_PRIM = 46 -A7XX_PERF_PC_US_DP1_LIVE_PRIM = 47 -A7XX_PERF_PC_US_BV2BR_SWITCH = 48 -A7XX_PERF_PC_US_BR2BV_SWITCH = 49 -A7XX_PERF_PC_US_STALL_CYCLES_PC_S = 50 -A7XX_PERF_PC_RESERVED_51 = 51 -A7XX_PERF_PC_RESERVED_52 = 52 -A7XX_PERF_PC_RESERVED_53 = 53 -A7XX_PERF_PC_RESERVED_54 = 54 -A7XX_PERF_PC_RESERVED_55 = 55 -A7XX_PERF_PC_RESERVED_56 = 56 -A7XX_PERF_PC_RESERVED_57 = 57 -A7XX_PERF_PC_RESERVED_58 = 58 -A7XX_PERF_PC_RESERVED_59 = 59 -A7XX_PERF_PC_S_BUSY_CYCLES = 60 -A7XX_PERF_PC_S_WORKING_CYCLES = 61 -A7XX_PERF_PC_S_STALL_CYCLES_VFD = 62 -A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = 63 -A7XX_PERF_PC_S_STALL_CYCLES_TESS = 64 -A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = 65 -A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = 66 -A7XX_PERF_PC_S_VPC_PRIMITIVES = 67 -A7XX_PERF_PC_S_VERTEX_HITS = 68 -A7XX_PERF_PC_S_IA_VERTICES = 69 -A7XX_PERF_PC_S_IA_PRIMITIVES = 70 -A7XX_PERF_PC_S_HS_INVOCATIONS = 71 -A7XX_PERF_PC_S_DS_INVOCATIONS = 72 -A7XX_PERF_PC_S_VS_INVOCATIONS = 73 -A7XX_PERF_PC_S_GS_INVOCATIONS = 74 -A7XX_PERF_PC_S_DS_PRIMITIVES = 75 -A7XX_PERF_PC_S_TESS_BUSY_CYCLES = 76 -A7XX_PERF_PC_S_TESS_WORKING_CYCLES = 77 -A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = 78 -A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = 79 -A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = 80 -A7XX_PERF_PC_S_TESS_PID_ACTIVE = 81 -A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = 82 -A7XX_PERF_PC_S_TESS_FACTOR_TRANS = 83 -A7XX_PERF_PC_S_TESS_PC_UV_TRANS = 84 -A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = 85 -A7XX_PERF_PC_S_MESH_VS_WAVES = 86 -a7xx_pc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vfd_perfcounter_select' -a7xx_vfd_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VFD_NEVER_COUNT', - 1: 'A7XX_PERF_VFD_BUSY_CYCLES', - 2: 'A7XX_PERF_VFD_STALL_CYCLES_UCHE', - 3: 'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 4: 'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', - 5: 'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', - 6: 'A7XX_PERF_VFD_STARVE_CYCLES_UCHE', - 7: 'A7XX_PERF_VFD_RBUFFER_FULL', - 8: 'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', - 9: 'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 10: 'A7XX_PERF_VFD_NUM_ATTRIBUTES', - 11: 'A7XX_PERF_VFD_UPPER_SHADER_FIBERS', - 12: 'A7XX_PERF_VFD_LOWER_SHADER_FIBERS', - 13: 'A7XX_PERF_VFD_MODE_0_FIBERS', - 14: 'A7XX_PERF_VFD_MODE_1_FIBERS', - 15: 'A7XX_PERF_VFD_MODE_2_FIBERS', - 16: 'A7XX_PERF_VFD_MODE_3_FIBERS', - 17: 'A7XX_PERF_VFD_MODE_4_FIBERS', - 18: 'A7XX_PERF_VFD_TOTAL_VERTICES', - 19: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD', - 20: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 21: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', - 22: 'A7XX_PERF_VFDP_STARVE_CYCLES_PC', - 23: 'A7XX_PERF_VFDP_VS_STAGE_WAVES', - 24: 'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', - 25: 'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', -} -A7XX_PERF_VFD_NEVER_COUNT = 0 -A7XX_PERF_VFD_BUSY_CYCLES = 1 -A7XX_PERF_VFD_STALL_CYCLES_UCHE = 2 -A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = 3 -A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = 4 -A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = 5 -A7XX_PERF_VFD_STARVE_CYCLES_UCHE = 6 -A7XX_PERF_VFD_RBUFFER_FULL = 7 -A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = 8 -A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = 9 -A7XX_PERF_VFD_NUM_ATTRIBUTES = 10 -A7XX_PERF_VFD_UPPER_SHADER_FIBERS = 11 -A7XX_PERF_VFD_LOWER_SHADER_FIBERS = 12 -A7XX_PERF_VFD_MODE_0_FIBERS = 13 -A7XX_PERF_VFD_MODE_1_FIBERS = 14 -A7XX_PERF_VFD_MODE_2_FIBERS = 15 -A7XX_PERF_VFD_MODE_3_FIBERS = 16 -A7XX_PERF_VFD_MODE_4_FIBERS = 17 -A7XX_PERF_VFD_TOTAL_VERTICES = 18 -A7XX_PERF_VFDP_STALL_CYCLES_VFD = 19 -A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = 20 -A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = 21 -A7XX_PERF_VFDP_STARVE_CYCLES_PC = 22 -A7XX_PERF_VFDP_VS_STAGE_WAVES = 23 -A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = 24 -A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = 25 -a7xx_vfd_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_hlsq_perfcounter_select' -a7xx_hlsq_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_HLSQ_NEVER_COUNT', - 1: 'A7XX_PERF_HLSQ_BUSY_CYCLES', - 2: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', - 3: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 4: 'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', - 5: 'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', - 6: 'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', - 7: 'A7XX_PERF_HLSQ_RESERVED_7', - 8: 'A7XX_PERF_HLSQ_RESERVED_8', - 9: 'A7XX_PERF_HLSQ_RESERVED_9', - 10: 'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', - 11: 'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 12: 'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 13: 'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 14: 'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 15: 'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 16: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 17: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 18: 'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', - 19: 'A7XX_PERF_HLSQ_RESERVED_19', - 20: 'A7XX_PERF_HLSQ_RESERVED_20', - 21: 'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', - 22: 'A7XX_PERF_HLSQ_FS_STALL_CYCLES', - 23: 'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', - 24: 'A7XX_PERF_HLSQ_BV_STALL_CYCLES', - 25: 'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', - 26: 'A7XX_PERF_HLSQ_FS_DEREF_CYCLES', - 27: 'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', - 28: 'A7XX_PERF_HLSQ_BV_DEREF_CYCLES', - 29: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', - 30: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES', - 31: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', - 32: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES', - 33: 'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', - 34: 'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', - 35: 'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', - 36: 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', - 37: 'A7XX_PERF_HLSQ_RESERVED_37', - 38: 'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', - 39: 'A7XX_PERF_HLSQ_FS_STARVING_SP', - 40: 'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', - 41: 'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', - 42: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', - 43: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', - 44: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', - 45: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', - 46: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', - 47: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', - 48: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', - 49: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', - 50: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', - 51: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', - 52: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', - 53: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', - 54: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', - 55: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', - 56: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', - 57: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', - 58: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', - 59: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', - 60: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', - 61: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', - 62: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', - 63: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', - 64: 'A7XX_PERF_HLSQ_L2STC_REQ_SP', - 65: 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', - 66: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', - 67: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', - 68: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', - 69: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', - 70: 'A7XX_PERF_HLSQ_L2STC_REQ_UCHE', - 71: 'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', - 72: 'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', - 73: 'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', - 74: 'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', - 75: 'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', - 76: 'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', - 77: 'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', - 78: 'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', - 79: 'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', - 80: 'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', - 81: 'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', - 82: 'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', - 83: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', - 84: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', - 85: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', - 86: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', - 87: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', - 88: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', - 89: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', - 90: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', - 91: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', - 92: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', - 93: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', - 94: 'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', - 95: 'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', - 96: 'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', - 97: 'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', - 98: 'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', - 99: 'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', - 100: 'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', - 101: 'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', - 102: 'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', - 103: 'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', - 104: 'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', - 105: 'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', - 106: 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT', - 107: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', - 108: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', - 109: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', - 110: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', - 111: 'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', -} -A7XX_PERF_HLSQ_NEVER_COUNT = 0 -A7XX_PERF_HLSQ_BUSY_CYCLES = 1 -A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = 2 -A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3 -A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = 4 -A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = 5 -A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = 6 -A7XX_PERF_HLSQ_RESERVED_7 = 7 -A7XX_PERF_HLSQ_RESERVED_8 = 8 -A7XX_PERF_HLSQ_RESERVED_9 = 9 -A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = 10 -A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11 -A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12 -A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13 -A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14 -A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15 -A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16 -A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17 -A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = 18 -A7XX_PERF_HLSQ_RESERVED_19 = 19 -A7XX_PERF_HLSQ_RESERVED_20 = 20 -A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = 21 -A7XX_PERF_HLSQ_FS_STALL_CYCLES = 22 -A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = 23 -A7XX_PERF_HLSQ_BV_STALL_CYCLES = 24 -A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = 25 -A7XX_PERF_HLSQ_FS_DEREF_CYCLES = 26 -A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = 27 -A7XX_PERF_HLSQ_BV_DEREF_CYCLES = 28 -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = 29 -A7XX_PERF_HLSQ_FS_S2W_CYCLES = 30 -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = 31 -A7XX_PERF_HLSQ_BV_S2W_CYCLES = 32 -A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = 33 -A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = 34 -A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = 35 -A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = 36 -A7XX_PERF_HLSQ_RESERVED_37 = 37 -A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = 38 -A7XX_PERF_HLSQ_FS_STARVING_SP = 39 -A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = 40 -A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = 41 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = 42 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = 43 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = 44 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = 45 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = 46 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = 47 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = 48 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = 49 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = 50 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = 51 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = 52 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = 53 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = 54 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = 55 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = 56 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = 57 -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = 58 -A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = 59 -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = 60 -A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = 61 -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = 62 -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = 63 -A7XX_PERF_HLSQ_L2STC_REQ_SP = 64 -A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = 65 -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = 66 -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = 67 -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = 68 -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = 69 -A7XX_PERF_HLSQ_L2STC_REQ_UCHE = 70 -A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = 71 -A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = 72 -A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = 73 -A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = 74 -A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = 75 -A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = 76 -A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = 77 -A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = 78 -A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = 79 -A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = 80 -A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = 81 -A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = 82 -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = 83 -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = 84 -A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = 85 -A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = 86 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = 87 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = 88 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = 89 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = 90 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = 91 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = 92 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = 93 -A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = 94 -A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = 95 -A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = 96 -A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = 97 -A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = 98 -A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = 99 -A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = 100 -A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = 101 -A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = 102 -A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = 103 -A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = 104 -A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = 105 -A7XX_PERF_HLSQ_PRIMITIVE_COUNT = 106 -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = 107 -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = 108 -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = 109 -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = 110 -A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = 111 -a7xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vpc_perfcounter_select' -a7xx_vpc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VPC_NEVER_COUNT', - 1: 'A7XX_PERF_VPC_FE_BUSY_CYCLES', - 2: 'A7XX_PERF_VPC_FE_WORKING_CYCLES', - 3: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', - 4: 'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', - 5: 'A7XX_PERF_VPC_FE_PC_PRIMITIVES', - 6: 'A7XX_PERF_VPC_FE_SP_COMPONENTS', - 7: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', - 8: 'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', - 9: 'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', - 10: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', - 11: 'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', - 12: 'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', - 13: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', - 14: 'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', - 15: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', - 16: 'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', - 17: 'A7XX_PERF_VPC_FE_GS_PRIMITIVES', - 18: 'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', - 19: 'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', - 20: 'A7XX_PERF_VPC_FE_NUM_WM_HIT', - 21: 'A7XX_PERF_VPC_FE_STALL_DQ_WACK', - 22: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', - 23: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', - 24: 'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', - 25: 'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', - 26: 'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', - 27: 'A7XX_PERF_VPC_FE_BOTTLENECK', - 28: 'A7XX_PERF_VPC_US_BUSY_CYCLES', - 29: 'A7XX_PERF_VPC_US_WORKING_CYCLES', - 30: 'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', - 31: 'A7XX_PERF_VPC_US_PTUS_FULL', - 32: 'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', - 33: 'A7XX_PERF_VPC_US_STALL_CYCLES_VSC', - 34: 'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', - 35: 'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', - 36: 'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', - 37: 'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', - 38: 'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', - 39: 'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', - 40: 'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', - 41: 'A7XX_PERF_VPC_US_BOTTLENECK', - 42: 'A7XX_PERF_VPC_RESERVED_42', - 43: 'A7XX_PERF_VPC_RESERVED_43', - 44: 'A7XX_PERF_VPC_RESERVED_44', - 45: 'A7XX_PERF_VPC_BE_BUSY_CYCLES', - 46: 'A7XX_PERF_VPC_BE_WORKING_CYCLES', - 47: 'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', - 48: 'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', - 49: 'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', - 50: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', - 51: 'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', - 52: 'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', - 53: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', - 54: 'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 55: 'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', - 56: 'A7XX_PERF_VPC_BE_NUM_PA_REQ', - 57: 'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', - 58: 'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', - 59: 'A7XX_PERF_VPC_BE_LM_TRANSACTION', - 60: 'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', - 61: 'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', - 62: 'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', - 63: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', - 64: 'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', - 65: 'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', - 66: 'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', - 67: 'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', - 68: 'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', - 69: 'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', - 70: 'A7XX_PERF_VPC_BE_BOTTLENECK', -} -A7XX_PERF_VPC_NEVER_COUNT = 0 -A7XX_PERF_VPC_FE_BUSY_CYCLES = 1 -A7XX_PERF_VPC_FE_WORKING_CYCLES = 2 -A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = 3 -A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = 4 -A7XX_PERF_VPC_FE_PC_PRIMITIVES = 5 -A7XX_PERF_VPC_FE_SP_COMPONENTS = 6 -A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = 7 -A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = 8 -A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = 9 -A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = 10 -A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = 11 -A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = 12 -A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = 13 -A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = 14 -A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = 15 -A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = 16 -A7XX_PERF_VPC_FE_GS_PRIMITIVES = 17 -A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = 18 -A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = 19 -A7XX_PERF_VPC_FE_NUM_WM_HIT = 20 -A7XX_PERF_VPC_FE_STALL_DQ_WACK = 21 -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = 22 -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = 23 -A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = 24 -A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = 25 -A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = 26 -A7XX_PERF_VPC_FE_BOTTLENECK = 27 -A7XX_PERF_VPC_US_BUSY_CYCLES = 28 -A7XX_PERF_VPC_US_WORKING_CYCLES = 29 -A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = 30 -A7XX_PERF_VPC_US_PTUS_FULL = 31 -A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = 32 -A7XX_PERF_VPC_US_STALL_CYCLES_VSC = 33 -A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = 34 -A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = 35 -A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = 36 -A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = 37 -A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = 38 -A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = 39 -A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = 40 -A7XX_PERF_VPC_US_BOTTLENECK = 41 -A7XX_PERF_VPC_RESERVED_42 = 42 -A7XX_PERF_VPC_RESERVED_43 = 43 -A7XX_PERF_VPC_RESERVED_44 = 44 -A7XX_PERF_VPC_BE_BUSY_CYCLES = 45 -A7XX_PERF_VPC_BE_WORKING_CYCLES = 46 -A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = 47 -A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = 48 -A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = 49 -A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = 50 -A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = 51 -A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = 52 -A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = 53 -A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = 54 -A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = 55 -A7XX_PERF_VPC_BE_NUM_PA_REQ = 56 -A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = 57 -A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = 58 -A7XX_PERF_VPC_BE_LM_TRANSACTION = 59 -A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = 60 -A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = 61 -A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = 62 -A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = 63 -A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = 64 -A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = 65 -A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = 66 -A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = 67 -A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = 68 -A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = 69 -A7XX_PERF_VPC_BE_BOTTLENECK = 70 -a7xx_vpc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_tse_perfcounter_select' -a7xx_tse_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_TSE_NEVER_COUNT', - 1: 'A7XX_PERF_TSE_BE_BUSY_CYCLES', - 2: 'A7XX_PERF_TSE_BE_CLIPPING_CYCLES', - 3: 'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', - 4: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', - 5: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', - 6: 'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', - 7: 'A7XX_PERF_TSE_BE_INPUT_PRIM', - 8: 'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', - 9: 'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', - 10: 'A7XX_PERF_TSE_BE_CLIPPED_PRIM', - 11: 'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', - 12: 'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', - 13: 'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', - 14: 'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', - 15: 'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', - 16: 'A7XX_PERF_TSE_BE_CINVOCATION', - 17: 'A7XX_PERF_TSE_BE_CPRIMITIVES', - 18: 'A7XX_PERF_TSE_BE_2D_INPUT_PRIM', - 19: 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', - 20: 'A7XX_PERF_TSE_BE_CLIP_PLANES', - 21: 'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', - 22: 'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', - 23: 'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 24: 'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 25: 'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', - 26: 'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', - 27: 'A7XX_PERF_TSE_BE_EXCLUDED_PRIM', - 28: 'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', - 29: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', - 30: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', - 31: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', - 32: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', - 33: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', - 34: 'A7XX_PERF_TSE_FE_BUSY_CYCLES', - 35: 'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', - 36: 'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', - 37: 'A7XX_PERF_TSE_FE_INPUT_PRIM', - 38: 'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', - 39: 'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', - 40: 'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', - 41: 'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', - 42: 'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', - 43: 'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', - 44: 'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', - 45: 'A7XX_PERF_TSE_FE_CINVOCATION', - 46: 'A7XX_PERF_TSE_FE_CPRIMITIVES', - 47: 'A7XX_PERF_TSE_FE_CLIP_PLANES', - 48: 'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', - 49: 'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', - 50: 'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 51: 'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 52: 'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', - 53: 'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', - 54: 'A7XX_PERF_TSE_FE_EXCLUDED_PRIM', - 55: 'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', - 56: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', - 57: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', - 58: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', - 59: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', - 60: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', - 61: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', -} -A7XX_PERF_TSE_NEVER_COUNT = 0 -A7XX_PERF_TSE_BE_BUSY_CYCLES = 1 -A7XX_PERF_TSE_BE_CLIPPING_CYCLES = 2 -A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = 3 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = 4 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = 5 -A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = 6 -A7XX_PERF_TSE_BE_INPUT_PRIM = 7 -A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = 8 -A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = 9 -A7XX_PERF_TSE_BE_CLIPPED_PRIM = 10 -A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = 11 -A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = 12 -A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = 13 -A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = 14 -A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = 15 -A7XX_PERF_TSE_BE_CINVOCATION = 16 -A7XX_PERF_TSE_BE_CPRIMITIVES = 17 -A7XX_PERF_TSE_BE_2D_INPUT_PRIM = 18 -A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = 19 -A7XX_PERF_TSE_BE_CLIP_PLANES = 20 -A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = 21 -A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = 22 -A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 23 -A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 24 -A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = 25 -A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = 26 -A7XX_PERF_TSE_BE_EXCLUDED_PRIM = 27 -A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = 28 -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = 29 -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = 30 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = 31 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = 32 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = 33 -A7XX_PERF_TSE_FE_BUSY_CYCLES = 34 -A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = 35 -A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = 36 -A7XX_PERF_TSE_FE_INPUT_PRIM = 37 -A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = 38 -A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = 39 -A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = 40 -A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = 41 -A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = 42 -A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = 43 -A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = 44 -A7XX_PERF_TSE_FE_CINVOCATION = 45 -A7XX_PERF_TSE_FE_CPRIMITIVES = 46 -A7XX_PERF_TSE_FE_CLIP_PLANES = 47 -A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = 48 -A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = 49 -A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 50 -A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 51 -A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = 52 -A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = 53 -A7XX_PERF_TSE_FE_EXCLUDED_PRIM = 54 -A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = 55 -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = 56 -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = 57 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = 58 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = 59 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = 60 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = 61 -a7xx_tse_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ras_perfcounter_select' -a7xx_ras_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RAS_NEVER_COUNT', - 1: 'A7XX_PERF_RAS_BUSY_CYCLES', - 2: 'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 3: 'A7XX_PERF_RAS_STALL_CYCLES_LRZ', - 4: 'A7XX_PERF_RAS_STARVE_CYCLES_TSE', - 5: 'A7XX_PERF_RAS_SUPER_TILES', - 6: 'A7XX_PERF_RAS_8X4_TILES', - 7: 'A7XX_PERF_RAS_MASKGEN_ACTIVE', - 8: 'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', - 9: 'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', - 10: 'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', - 11: 'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 12: 'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 13: 'A7XX_PERF_RAS_BLOCKS', - 14: 'A7XX_PERF_RAS_FALSE_PARTIAL_STILE', - 15: 'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', - 16: 'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', - 17: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', - 18: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', - 19: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', - 20: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', - 21: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', - 22: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', - 23: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', - 24: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', - 25: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', - 26: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', - 27: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', - 28: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', - 29: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', - 30: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', - 31: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', - 32: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', -} -A7XX_PERF_RAS_NEVER_COUNT = 0 -A7XX_PERF_RAS_BUSY_CYCLES = 1 -A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 2 -A7XX_PERF_RAS_STALL_CYCLES_LRZ = 3 -A7XX_PERF_RAS_STARVE_CYCLES_TSE = 4 -A7XX_PERF_RAS_SUPER_TILES = 5 -A7XX_PERF_RAS_8X4_TILES = 6 -A7XX_PERF_RAS_MASKGEN_ACTIVE = 7 -A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = 8 -A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = 9 -A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = 10 -A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 11 -A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = 12 -A7XX_PERF_RAS_BLOCKS = 13 -A7XX_PERF_RAS_FALSE_PARTIAL_STILE = 14 -A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = 15 -A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = 16 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = 17 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = 18 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = 19 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = 20 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = 21 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = 22 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = 23 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = 24 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = 25 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = 26 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = 27 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = 28 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = 29 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = 30 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = 31 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = 32 -a7xx_ras_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_uche_perfcounter_select' -a7xx_uche_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_UCHE_NEVER_COUNT', - 1: 'A7XX_PERF_UCHE_BUSY_CYCLES', - 2: 'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', - 3: 'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', - 4: 'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', - 5: 'A7XX_PERF_UCHE_STALL_CYCLES_DECMP', - 6: 'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', - 7: 'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', - 8: 'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', - 9: 'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', - 10: 'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', - 11: 'A7XX_PERF_UCHE_READ_REQUESTS_SP', - 12: 'A7XX_PERF_UCHE_READ_REQUESTS_TP', - 13: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', - 14: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', - 15: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', - 16: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD', - 17: 'A7XX_PERF_UCHE_READ_REQUESTS_VPC', - 18: 'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', - 19: 'A7XX_PERF_UCHE_READ_REQUESTS_LRZ', - 20: 'A7XX_PERF_UCHE_READ_REQUESTS_PC', - 21: 'A7XX_PERF_UCHE_WRITE_REQUESTS_SP', - 22: 'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', - 23: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', - 24: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', - 25: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', - 26: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', - 27: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', - 28: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', - 29: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 30: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', - 31: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', - 32: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', - 33: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', - 34: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', - 35: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', - 36: 'A7XX_PERF_UCHE_GMEM_READ_BEATS', - 37: 'A7XX_PERF_UCHE_GMEM_WRITE_BEATS', - 38: 'A7XX_PERF_UCHE_UBWC_READ_BEATS', - 39: 'A7XX_PERF_UCHE_UBWC_WRITE_BEATS', - 40: 'A7XX_PERF_UCHE_EVICTS', - 41: 'A7XX_PERF_UCHE_BANK_REQ0', - 42: 'A7XX_PERF_UCHE_BANK_REQ1', - 43: 'A7XX_PERF_UCHE_BANK_REQ2', - 44: 'A7XX_PERF_UCHE_BANK_REQ3', - 45: 'A7XX_PERF_UCHE_BANK_REQ4', - 46: 'A7XX_PERF_UCHE_BANK_REQ5', - 47: 'A7XX_PERF_UCHE_BANK_REQ6', - 48: 'A7XX_PERF_UCHE_BANK_REQ7', - 49: 'A7XX_PERF_UCHE_TPH_REF_FULL', - 50: 'A7XX_PERF_UCHE_TPH_VICTIM_FULL', - 51: 'A7XX_PERF_UCHE_TPH_EXT_FULL', - 52: 'A7XX_PERF_UCHE_RAM_READ_REQ', - 53: 'A7XX_PERF_UCHE_RAM_WRITE_REQ', - 54: 'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', - 55: 'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', - 56: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', - 57: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', - 58: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', - 59: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', - 60: 'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', - 61: 'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', - 62: 'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', - 63: 'A7XX_PERF_UCHE_EVICTS_SP', - 64: 'A7XX_PERF_UCHE_EVICTS_LRZ', - 65: 'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', - 66: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', - 67: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', - 68: 'A7XX_PERF_BYPC_FULL', - 69: 'A7XX_PERF_BYPC_FULL_CCHE_STALL', - 70: 'A7XX_PERF_BYPC_VHUB_STALL', - 71: 'A7XX_PERF_BYPD_FULL', - 72: 'A7XX_PERF_BYPD_FULL_GBIF_STALL', - 73: 'A7XX_PERF_VHUB_PTABLE_FULL', - 74: 'A7XX_PERF_DHUB_PTABLE_FULL', - 75: 'A7XX_PERF_UCHE_RESERVED_75', - 76: 'A7XX_PERF_UCHE_RESERVED_76', - 77: 'A7XX_PERF_UCHE_RESERVED_77', - 78: 'A7XX_PERF_UCHE_RESERVED_78', - 79: 'A7XX_PERF_UCHE_RESERVED_79', - 80: 'A7XX_PERF_UCHE_RESERVED_80', - 81: 'A7XX_PERF_UCHE_RESERVED_81', - 82: 'A7XX_PERF_UCHE_RESERVED_82', - 83: 'A7XX_PERF_UCHE_RESERVED_83', - 84: 'A7XX_PERF_UCHE_RESERVED_84', - 85: 'A7XX_PERF_UCHE_RESERVED_85', - 86: 'A7XX_PERF_UCHE_RESERVED_86', - 87: 'A7XX_PERF_UCHE_RESERVED_87', - 88: 'A7XX_PERF_UCHE_RESERVED_88', - 89: 'A7XX_PERF_UCHE_RESERVED_89', - 90: 'A7XX_PERF_UCHE_RESERVED_90', - 91: 'A7XX_PERF_UCHE_RESERVED_91', - 92: 'A7XX_PERF_UCHE_RESERVED_92', - 93: 'A7XX_PERF_UCHE_RESERVED_93', - 94: 'A7XX_PERF_UCHE_RESERVED_94', - 95: 'A7XX_PERF_UCHE_RESERVED_95', - 96: 'A7XX_PERF_UCHE_RESERVED_96', - 97: 'A7XX_PERF_UCHE_RESERVED_97', - 98: 'A7XX_PERF_UCHE_RESERVED_98', - 99: 'A7XX_PERF_UCHE_RESERVED_99', - 100: 'A7XX_PERF_UCHE_RESERVED_100', - 101: 'A7XX_PERF_UCHE_RESERVED_101', - 102: 'A7XX_PERF_UCHE_RESERVED_102', - 103: 'A7XX_PERF_UCHE_RESERVED_103', - 104: 'A7XX_PERF_UCHE_RESERVED_104', - 105: 'A7XX_PERF_UCHE_RESERVED_105', - 106: 'A7XX_PERF_UCHE_RESERVED_106', - 107: 'A7XX_PERF_UCHE_RESERVED_107', - 108: 'A7XX_PERF_UCHE_RESERVED_108', - 109: 'A7XX_PERF_UCHE_RESERVED_109', - 110: 'A7XX_PERF_UCHE_RESERVED_110', - 111: 'A7XX_PERF_UCHE_RESERVED_111', - 112: 'A7XX_PERF_UCHE_RESERVED_112', - 113: 'A7XX_PERF_UCHE_RESERVED_113', - 114: 'A7XX_PERF_UCHE_RESERVED_114', - 115: 'A7XX_PERF_UCHE_RESERVED_115', - 116: 'A7XX_PERF_UCHE_RESERVED_116', - 117: 'A7XX_PERF_UCHE_RESERVED_117', - 118: 'A7XX_PERF_UCHE_RESERVED_118', - 119: 'A7XX_PERF_UCHE_RESERVED_119', - 120: 'A7XX_PERF_UCHE_RESERVED_120', - 121: 'A7XX_PERF_UCHE_RESERVED_121', - 122: 'A7XX_PERF_UCHE_RESERVED_122', - 123: 'A7XX_PERF_UCHE_RESERVED_123', - 124: 'A7XX_PERF_UCHE_RESERVED_124', - 125: 'A7XX_PERF_UCHE_RESERVED_125', - 126: 'A7XX_PERF_UCHE_RESERVED_126', - 127: 'A7XX_PERF_UCHE_RESERVED_127', - 128: 'A7XX_PERF_CCHE_BUSY_CYCLES', - 129: 'A7XX_PERF_CCHE_STALL_CYCLES_UCHE', - 130: 'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', - 131: 'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', - 132: 'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', - 133: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', - 134: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', - 135: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', - 136: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', - 137: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', - 138: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', - 139: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', - 140: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', - 141: 'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', - 142: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', - 143: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', - 144: 'A7XX_PERF_CCHE_READ_REQUESTS_LRZ', - 145: 'A7XX_PERF_CCHE_READ_REQUESTS_VPC', - 146: 'A7XX_PERF_CCHE_WRITE_REQUESTS_SP', - 147: 'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', - 148: 'A7XX_PERF_CCHE_READ_REQUESTS_GMEM', - 149: 'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', - 150: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', - 151: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', - 152: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', - 153: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', - 154: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', - 155: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', - 156: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', - 157: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', - 158: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', - 159: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', - 160: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', - 161: 'A7XX_PERF_CCHE_BANK_REQ0', - 162: 'A7XX_PERF_CCHE_BANK_REQ1', - 163: 'A7XX_PERF_CCHE_BANK_REQ2', - 164: 'A7XX_PERF_CCHE_BANK_REQ3', - 165: 'A7XX_PERF_CCHE_BANK_REQ4', - 166: 'A7XX_PERF_CCHE_BANK_REQ5', - 167: 'A7XX_PERF_CCHE_BANK_REQ6', - 168: 'A7XX_PERF_CCHE_BANK_REQ7', - 169: 'A7XX_PERF_CCHE_BANK_REQ8', - 170: 'A7XX_PERF_CCHE_BANK_REQ9', - 171: 'A7XX_PERF_CCHE_BANK_REQ10', - 172: 'A7XX_PERF_CCHE_BANK_REQ11', - 173: 'A7XX_PERF_CCHE_BANK_REQ12', - 174: 'A7XX_PERF_CCHE_BANK_REQ13', - 175: 'A7XX_PERF_CCHE_BANK_REQ14', - 176: 'A7XX_PERF_CCHE_BANK_REQ15', - 177: 'A7XX_PERF_CCHE_GBANK_REQ0', - 178: 'A7XX_PERF_CCHE_GBANK_REQ1', - 179: 'A7XX_PERF_CCHE_GBANK_REQ2', - 180: 'A7XX_PERF_CCHE_GBANK_REQ3', - 181: 'A7XX_PERF_CCHE_TPH_REF_FULL', - 182: 'A7XX_PERF_CCHE_TPH_VICTIM_FULL', - 183: 'A7XX_PERF_CCHE_TPH_EXT_FULL', - 184: 'A7XX_PERF_CCHE_RAM_READ_REQ', - 185: 'A7XX_PERF_CCHE_RAM_WRITE_REQ', - 186: 'A7XX_PERF_CCHE_TPH_CONFLICT_CL', - 187: 'A7XX_PERF_CCHE_DBANK_CONFLICT', - 188: 'A7XX_PERF_CCHE_TPH_QUEUE_FULL', - 189: 'A7XX_PERF_CCHE_DPH_QUEUE_FULL', - 190: 'A7XX_PERF_CCHE_OPH_QUEUE_FULL', - 191: 'A7XX_PERF_CCHE_WACK_QUEUE_FULL', - 192: 'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', - 193: 'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', - 194: 'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', - 195: 'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', - 196: 'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', - 197: 'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', - 198: 'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', - 199: 'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', - 200: 'A7XX_PERF_CCHE_STALL_CYCLES_TP', -} -A7XX_PERF_UCHE_NEVER_COUNT = 0 -A7XX_PERF_UCHE_BUSY_CYCLES = 1 -A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = 2 -A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = 3 -A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = 4 -A7XX_PERF_UCHE_STALL_CYCLES_DECMP = 5 -A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = 6 -A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = 7 -A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = 8 -A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = 9 -A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = 10 -A7XX_PERF_UCHE_READ_REQUESTS_SP = 11 -A7XX_PERF_UCHE_READ_REQUESTS_TP = 12 -A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = 13 -A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = 14 -A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = 15 -A7XX_PERF_UCHE_READ_REQUESTS_VFD = 16 -A7XX_PERF_UCHE_READ_REQUESTS_VPC = 17 -A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = 18 -A7XX_PERF_UCHE_READ_REQUESTS_LRZ = 19 -A7XX_PERF_UCHE_READ_REQUESTS_PC = 20 -A7XX_PERF_UCHE_WRITE_REQUESTS_SP = 21 -A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = 22 -A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = 23 -A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = 24 -A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = 25 -A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = 26 -A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = 27 -A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = 28 -A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = 29 -A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = 30 -A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = 31 -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = 32 -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = 33 -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = 34 -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = 35 -A7XX_PERF_UCHE_GMEM_READ_BEATS = 36 -A7XX_PERF_UCHE_GMEM_WRITE_BEATS = 37 -A7XX_PERF_UCHE_UBWC_READ_BEATS = 38 -A7XX_PERF_UCHE_UBWC_WRITE_BEATS = 39 -A7XX_PERF_UCHE_EVICTS = 40 -A7XX_PERF_UCHE_BANK_REQ0 = 41 -A7XX_PERF_UCHE_BANK_REQ1 = 42 -A7XX_PERF_UCHE_BANK_REQ2 = 43 -A7XX_PERF_UCHE_BANK_REQ3 = 44 -A7XX_PERF_UCHE_BANK_REQ4 = 45 -A7XX_PERF_UCHE_BANK_REQ5 = 46 -A7XX_PERF_UCHE_BANK_REQ6 = 47 -A7XX_PERF_UCHE_BANK_REQ7 = 48 -A7XX_PERF_UCHE_TPH_REF_FULL = 49 -A7XX_PERF_UCHE_TPH_VICTIM_FULL = 50 -A7XX_PERF_UCHE_TPH_EXT_FULL = 51 -A7XX_PERF_UCHE_RAM_READ_REQ = 52 -A7XX_PERF_UCHE_RAM_WRITE_REQ = 53 -A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = 54 -A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = 55 -A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = 56 -A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = 57 -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = 58 -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = 59 -A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = 60 -A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = 61 -A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = 62 -A7XX_PERF_UCHE_EVICTS_SP = 63 -A7XX_PERF_UCHE_EVICTS_LRZ = 64 -A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = 65 -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = 66 -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = 67 -A7XX_PERF_BYPC_FULL = 68 -A7XX_PERF_BYPC_FULL_CCHE_STALL = 69 -A7XX_PERF_BYPC_VHUB_STALL = 70 -A7XX_PERF_BYPD_FULL = 71 -A7XX_PERF_BYPD_FULL_GBIF_STALL = 72 -A7XX_PERF_VHUB_PTABLE_FULL = 73 -A7XX_PERF_DHUB_PTABLE_FULL = 74 -A7XX_PERF_UCHE_RESERVED_75 = 75 -A7XX_PERF_UCHE_RESERVED_76 = 76 -A7XX_PERF_UCHE_RESERVED_77 = 77 -A7XX_PERF_UCHE_RESERVED_78 = 78 -A7XX_PERF_UCHE_RESERVED_79 = 79 -A7XX_PERF_UCHE_RESERVED_80 = 80 -A7XX_PERF_UCHE_RESERVED_81 = 81 -A7XX_PERF_UCHE_RESERVED_82 = 82 -A7XX_PERF_UCHE_RESERVED_83 = 83 -A7XX_PERF_UCHE_RESERVED_84 = 84 -A7XX_PERF_UCHE_RESERVED_85 = 85 -A7XX_PERF_UCHE_RESERVED_86 = 86 -A7XX_PERF_UCHE_RESERVED_87 = 87 -A7XX_PERF_UCHE_RESERVED_88 = 88 -A7XX_PERF_UCHE_RESERVED_89 = 89 -A7XX_PERF_UCHE_RESERVED_90 = 90 -A7XX_PERF_UCHE_RESERVED_91 = 91 -A7XX_PERF_UCHE_RESERVED_92 = 92 -A7XX_PERF_UCHE_RESERVED_93 = 93 -A7XX_PERF_UCHE_RESERVED_94 = 94 -A7XX_PERF_UCHE_RESERVED_95 = 95 -A7XX_PERF_UCHE_RESERVED_96 = 96 -A7XX_PERF_UCHE_RESERVED_97 = 97 -A7XX_PERF_UCHE_RESERVED_98 = 98 -A7XX_PERF_UCHE_RESERVED_99 = 99 -A7XX_PERF_UCHE_RESERVED_100 = 100 -A7XX_PERF_UCHE_RESERVED_101 = 101 -A7XX_PERF_UCHE_RESERVED_102 = 102 -A7XX_PERF_UCHE_RESERVED_103 = 103 -A7XX_PERF_UCHE_RESERVED_104 = 104 -A7XX_PERF_UCHE_RESERVED_105 = 105 -A7XX_PERF_UCHE_RESERVED_106 = 106 -A7XX_PERF_UCHE_RESERVED_107 = 107 -A7XX_PERF_UCHE_RESERVED_108 = 108 -A7XX_PERF_UCHE_RESERVED_109 = 109 -A7XX_PERF_UCHE_RESERVED_110 = 110 -A7XX_PERF_UCHE_RESERVED_111 = 111 -A7XX_PERF_UCHE_RESERVED_112 = 112 -A7XX_PERF_UCHE_RESERVED_113 = 113 -A7XX_PERF_UCHE_RESERVED_114 = 114 -A7XX_PERF_UCHE_RESERVED_115 = 115 -A7XX_PERF_UCHE_RESERVED_116 = 116 -A7XX_PERF_UCHE_RESERVED_117 = 117 -A7XX_PERF_UCHE_RESERVED_118 = 118 -A7XX_PERF_UCHE_RESERVED_119 = 119 -A7XX_PERF_UCHE_RESERVED_120 = 120 -A7XX_PERF_UCHE_RESERVED_121 = 121 -A7XX_PERF_UCHE_RESERVED_122 = 122 -A7XX_PERF_UCHE_RESERVED_123 = 123 -A7XX_PERF_UCHE_RESERVED_124 = 124 -A7XX_PERF_UCHE_RESERVED_125 = 125 -A7XX_PERF_UCHE_RESERVED_126 = 126 -A7XX_PERF_UCHE_RESERVED_127 = 127 -A7XX_PERF_CCHE_BUSY_CYCLES = 128 -A7XX_PERF_CCHE_STALL_CYCLES_UCHE = 129 -A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = 130 -A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = 131 -A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = 132 -A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = 133 -A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = 134 -A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = 135 -A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = 136 -A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = 137 -A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = 138 -A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = 139 -A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = 140 -A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = 141 -A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = 142 -A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = 143 -A7XX_PERF_CCHE_READ_REQUESTS_LRZ = 144 -A7XX_PERF_CCHE_READ_REQUESTS_VPC = 145 -A7XX_PERF_CCHE_WRITE_REQUESTS_SP = 146 -A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = 147 -A7XX_PERF_CCHE_READ_REQUESTS_GMEM = 148 -A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = 149 -A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = 150 -A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = 151 -A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = 152 -A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = 153 -A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = 154 -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = 155 -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = 156 -A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = 157 -A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = 158 -A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = 159 -A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = 160 -A7XX_PERF_CCHE_BANK_REQ0 = 161 -A7XX_PERF_CCHE_BANK_REQ1 = 162 -A7XX_PERF_CCHE_BANK_REQ2 = 163 -A7XX_PERF_CCHE_BANK_REQ3 = 164 -A7XX_PERF_CCHE_BANK_REQ4 = 165 -A7XX_PERF_CCHE_BANK_REQ5 = 166 -A7XX_PERF_CCHE_BANK_REQ6 = 167 -A7XX_PERF_CCHE_BANK_REQ7 = 168 -A7XX_PERF_CCHE_BANK_REQ8 = 169 -A7XX_PERF_CCHE_BANK_REQ9 = 170 -A7XX_PERF_CCHE_BANK_REQ10 = 171 -A7XX_PERF_CCHE_BANK_REQ11 = 172 -A7XX_PERF_CCHE_BANK_REQ12 = 173 -A7XX_PERF_CCHE_BANK_REQ13 = 174 -A7XX_PERF_CCHE_BANK_REQ14 = 175 -A7XX_PERF_CCHE_BANK_REQ15 = 176 -A7XX_PERF_CCHE_GBANK_REQ0 = 177 -A7XX_PERF_CCHE_GBANK_REQ1 = 178 -A7XX_PERF_CCHE_GBANK_REQ2 = 179 -A7XX_PERF_CCHE_GBANK_REQ3 = 180 -A7XX_PERF_CCHE_TPH_REF_FULL = 181 -A7XX_PERF_CCHE_TPH_VICTIM_FULL = 182 -A7XX_PERF_CCHE_TPH_EXT_FULL = 183 -A7XX_PERF_CCHE_RAM_READ_REQ = 184 -A7XX_PERF_CCHE_RAM_WRITE_REQ = 185 -A7XX_PERF_CCHE_TPH_CONFLICT_CL = 186 -A7XX_PERF_CCHE_DBANK_CONFLICT = 187 -A7XX_PERF_CCHE_TPH_QUEUE_FULL = 188 -A7XX_PERF_CCHE_DPH_QUEUE_FULL = 189 -A7XX_PERF_CCHE_OPH_QUEUE_FULL = 190 -A7XX_PERF_CCHE_WACK_QUEUE_FULL = 191 -A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = 192 -A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = 193 -A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = 194 -A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = 195 -A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = 196 -A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = 197 -A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = 198 -A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = 199 -A7XX_PERF_CCHE_STALL_CYCLES_TP = 200 -a7xx_uche_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_tp_perfcounter_select' -a7xx_tp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_TP_NEVER_COUNT', - 1: 'A7XX_PERF_TP_BUSY_CYCLES', - 2: 'A7XX_PERF_TP_STALL_CYCLES_UCHE', - 3: 'A7XX_PERF_TP_LATENCY_CYCLES', - 4: 'A7XX_PERF_TP_LATENCY_TRANS', - 5: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', - 6: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', - 7: 'A7XX_PERF_TP_L1_CACHELINE_REQUESTS', - 8: 'A7XX_PERF_TP_L1_CACHELINE_MISSES', - 9: 'A7XX_PERF_TP_SP_TP_TRANS', - 10: 'A7XX_PERF_TP_TP_SP_TRANS', - 11: 'A7XX_PERF_TP_OUTPUT_PIXELS', - 12: 'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', - 13: 'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', - 14: 'A7XX_PERF_TP_QUADS_RECEIVED', - 15: 'A7XX_PERF_TP_QUADS_OFFSET', - 16: 'A7XX_PERF_TP_QUADS_SHADOW', - 17: 'A7XX_PERF_TP_QUADS_ARRAY', - 18: 'A7XX_PERF_TP_QUADS_GRADIENT', - 19: 'A7XX_PERF_TP_QUADS_1D', - 20: 'A7XX_PERF_TP_QUADS_2D', - 21: 'A7XX_PERF_TP_QUADS_BUFFER', - 22: 'A7XX_PERF_TP_QUADS_3D', - 23: 'A7XX_PERF_TP_QUADS_CUBE', - 24: 'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', - 25: 'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', - 26: 'A7XX_PERF_TP_OUTPUT_PIXELS_POINT', - 27: 'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', - 28: 'A7XX_PERF_TP_OUTPUT_PIXELS_MIP', - 29: 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', - 30: 'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 31: 'A7XX_PERF_TP_FLAG_CACHE_REQUESTS', - 32: 'A7XX_PERF_TP_FLAG_CACHE_MISSES', - 33: 'A7XX_PERF_TP_L1_5_L2_REQUESTS', - 34: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS', - 35: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', - 36: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 37: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 38: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 39: 'A7XX_PERF_TP_TPA2TPC_TRANS', - 40: 'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', - 41: 'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', - 42: 'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', - 43: 'A7XX_PERF_TP_L1_5_COMPRESS_REQS', - 44: 'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', - 45: 'A7XX_PERF_TP_L1_BANK_CONFLICT', - 46: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 47: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', - 48: 'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 49: 'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', - 50: 'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', - 51: 'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 52: 'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 53: 'A7XX_PERF_TP_BACKEND_WORKING_CYCLES', - 54: 'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 55: 'A7XX_PERF_TP_STARVE_CYCLES_SP', - 56: 'A7XX_PERF_TP_STARVE_CYCLES_UCHE', - 57: 'A7XX_PERF_TP_STALL_CYCLES_UFC', - 58: 'A7XX_PERF_TP_FORMAT_DECOMP_POINT', - 59: 'A7XX_PERF_TP_FILTER_POINT_FP16', - 60: 'A7XX_PERF_TP_FILTER_POINT_FP32', - 61: 'A7XX_PERF_TP_LATENCY_FIFO_FULL', - 62: 'A7XX_PERF_TP_RESERVED_62', - 63: 'A7XX_PERF_TP_RESERVED_63', - 64: 'A7XX_PERF_TP_RESERVED_64', - 65: 'A7XX_PERF_TP_RESERVED_65', - 66: 'A7XX_PERF_TP_RESERVED_66', - 67: 'A7XX_PERF_TP_RESERVED_67', - 68: 'A7XX_PERF_TP_RESERVED_68', - 69: 'A7XX_PERF_TP_RESERVED_69', - 70: 'A7XX_PERF_TP_RESERVED_70', - 71: 'A7XX_PERF_TP_RESERVED_71', - 72: 'A7XX_PERF_TP_RESERVED_72', - 73: 'A7XX_PERF_TP_RESERVED_73', - 74: 'A7XX_PERF_TP_RESERVED_74', - 75: 'A7XX_PERF_TP_RESERVED_75', - 76: 'A7XX_PERF_TP_RESERVED_76', - 77: 'A7XX_PERF_TP_RESERVED_77', - 78: 'A7XX_PERF_TP_RESERVED_78', - 79: 'A7XX_PERF_TP_RESERVED_79', - 80: 'A7XX_PERF_TP_RESERVED_80', - 81: 'A7XX_PERF_TP_RESERVED_81', - 82: 'A7XX_PERF_TP_RESERVED_82', - 83: 'A7XX_PERF_TP_RESERVED_83', - 84: 'A7XX_PERF_TP_RESERVED_84', - 85: 'A7XX_PERF_TP_RESERVED_85', - 86: 'A7XX_PERF_TP_RESERVED_86', - 87: 'A7XX_PERF_TP_RESERVED_87', - 88: 'A7XX_PERF_TP_RESERVED_88', - 89: 'A7XX_PERF_TP_RESERVED_89', - 90: 'A7XX_PERF_TP_RESERVED_90', - 91: 'A7XX_PERF_TP_RESERVED_91', - 92: 'A7XX_PERF_TP_RESERVED_92', - 93: 'A7XX_PERF_TP_RESERVED_93', - 94: 'A7XX_PERF_TP_RESERVED_94', - 95: 'A7XX_PERF_TP_RESERVED_95', - 96: 'A7XX_PERF_TP_RESERVED_96', - 97: 'A7XX_PERF_TP_RESERVED_97', - 98: 'A7XX_PERF_TP_RESERVED_98', - 99: 'A7XX_PERF_TP_RESERVED_99', - 100: 'A7XX_PERF_TP_RESERVED_100', - 101: 'A7XX_PERF_TP_RESERVED_101', - 102: 'A7XX_PERF_TP_RESERVED_102', - 103: 'A7XX_PERF_TP_RESERVED_103', - 104: 'A7XX_PERF_TP_RESERVED_104', - 105: 'A7XX_PERF_TP_RESERVED_105', - 106: 'A7XX_PERF_TP_RESERVED_106', - 107: 'A7XX_PERF_TP_RESERVED_107', - 108: 'A7XX_PERF_TP_RESERVED_108', - 109: 'A7XX_PERF_TP_RESERVED_109', - 110: 'A7XX_PERF_TP_RESERVED_110', - 111: 'A7XX_PERF_TP_RESERVED_111', - 112: 'A7XX_PERF_TP_RESERVED_112', - 113: 'A7XX_PERF_TP_RESERVED_113', - 114: 'A7XX_PERF_TP_RESERVED_114', - 115: 'A7XX_PERF_TP_RESERVED_115', - 116: 'A7XX_PERF_TP_RESERVED_116', - 117: 'A7XX_PERF_TP_RESERVED_117', - 118: 'A7XX_PERF_TP_RESERVED_118', - 119: 'A7XX_PERF_TP_RESERVED_119', - 120: 'A7XX_PERF_TP_RESERVED_120', - 121: 'A7XX_PERF_TP_RESERVED_121', - 122: 'A7XX_PERF_TP_RESERVED_122', - 123: 'A7XX_PERF_TP_RESERVED_123', - 124: 'A7XX_PERF_TP_RESERVED_124', - 125: 'A7XX_PERF_TP_RESERVED_125', - 126: 'A7XX_PERF_TP_RESERVED_126', - 127: 'A7XX_PERF_TP_RESERVED_127', - 128: 'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', - 129: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', - 130: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', - 131: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', - 132: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', -} -A7XX_PERF_TP_NEVER_COUNT = 0 -A7XX_PERF_TP_BUSY_CYCLES = 1 -A7XX_PERF_TP_STALL_CYCLES_UCHE = 2 -A7XX_PERF_TP_LATENCY_CYCLES = 3 -A7XX_PERF_TP_LATENCY_TRANS = 4 -A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = 5 -A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = 6 -A7XX_PERF_TP_L1_CACHELINE_REQUESTS = 7 -A7XX_PERF_TP_L1_CACHELINE_MISSES = 8 -A7XX_PERF_TP_SP_TP_TRANS = 9 -A7XX_PERF_TP_TP_SP_TRANS = 10 -A7XX_PERF_TP_OUTPUT_PIXELS = 11 -A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = 12 -A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = 13 -A7XX_PERF_TP_QUADS_RECEIVED = 14 -A7XX_PERF_TP_QUADS_OFFSET = 15 -A7XX_PERF_TP_QUADS_SHADOW = 16 -A7XX_PERF_TP_QUADS_ARRAY = 17 -A7XX_PERF_TP_QUADS_GRADIENT = 18 -A7XX_PERF_TP_QUADS_1D = 19 -A7XX_PERF_TP_QUADS_2D = 20 -A7XX_PERF_TP_QUADS_BUFFER = 21 -A7XX_PERF_TP_QUADS_3D = 22 -A7XX_PERF_TP_QUADS_CUBE = 23 -A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = 24 -A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = 25 -A7XX_PERF_TP_OUTPUT_PIXELS_POINT = 26 -A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = 27 -A7XX_PERF_TP_OUTPUT_PIXELS_MIP = 28 -A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = 29 -A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 30 -A7XX_PERF_TP_FLAG_CACHE_REQUESTS = 31 -A7XX_PERF_TP_FLAG_CACHE_MISSES = 32 -A7XX_PERF_TP_L1_5_L2_REQUESTS = 33 -A7XX_PERF_TP_2D_OUTPUT_PIXELS = 34 -A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = 35 -A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 36 -A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = 37 -A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = 38 -A7XX_PERF_TP_TPA2TPC_TRANS = 39 -A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = 40 -A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = 41 -A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = 42 -A7XX_PERF_TP_L1_5_COMPRESS_REQS = 43 -A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = 44 -A7XX_PERF_TP_L1_BANK_CONFLICT = 45 -A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = 46 -A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = 47 -A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = 48 -A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = 49 -A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = 50 -A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 51 -A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 52 -A7XX_PERF_TP_BACKEND_WORKING_CYCLES = 53 -A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54 -A7XX_PERF_TP_STARVE_CYCLES_SP = 55 -A7XX_PERF_TP_STARVE_CYCLES_UCHE = 56 -A7XX_PERF_TP_STALL_CYCLES_UFC = 57 -A7XX_PERF_TP_FORMAT_DECOMP_POINT = 58 -A7XX_PERF_TP_FILTER_POINT_FP16 = 59 -A7XX_PERF_TP_FILTER_POINT_FP32 = 60 -A7XX_PERF_TP_LATENCY_FIFO_FULL = 61 -A7XX_PERF_TP_RESERVED_62 = 62 -A7XX_PERF_TP_RESERVED_63 = 63 -A7XX_PERF_TP_RESERVED_64 = 64 -A7XX_PERF_TP_RESERVED_65 = 65 -A7XX_PERF_TP_RESERVED_66 = 66 -A7XX_PERF_TP_RESERVED_67 = 67 -A7XX_PERF_TP_RESERVED_68 = 68 -A7XX_PERF_TP_RESERVED_69 = 69 -A7XX_PERF_TP_RESERVED_70 = 70 -A7XX_PERF_TP_RESERVED_71 = 71 -A7XX_PERF_TP_RESERVED_72 = 72 -A7XX_PERF_TP_RESERVED_73 = 73 -A7XX_PERF_TP_RESERVED_74 = 74 -A7XX_PERF_TP_RESERVED_75 = 75 -A7XX_PERF_TP_RESERVED_76 = 76 -A7XX_PERF_TP_RESERVED_77 = 77 -A7XX_PERF_TP_RESERVED_78 = 78 -A7XX_PERF_TP_RESERVED_79 = 79 -A7XX_PERF_TP_RESERVED_80 = 80 -A7XX_PERF_TP_RESERVED_81 = 81 -A7XX_PERF_TP_RESERVED_82 = 82 -A7XX_PERF_TP_RESERVED_83 = 83 -A7XX_PERF_TP_RESERVED_84 = 84 -A7XX_PERF_TP_RESERVED_85 = 85 -A7XX_PERF_TP_RESERVED_86 = 86 -A7XX_PERF_TP_RESERVED_87 = 87 -A7XX_PERF_TP_RESERVED_88 = 88 -A7XX_PERF_TP_RESERVED_89 = 89 -A7XX_PERF_TP_RESERVED_90 = 90 -A7XX_PERF_TP_RESERVED_91 = 91 -A7XX_PERF_TP_RESERVED_92 = 92 -A7XX_PERF_TP_RESERVED_93 = 93 -A7XX_PERF_TP_RESERVED_94 = 94 -A7XX_PERF_TP_RESERVED_95 = 95 -A7XX_PERF_TP_RESERVED_96 = 96 -A7XX_PERF_TP_RESERVED_97 = 97 -A7XX_PERF_TP_RESERVED_98 = 98 -A7XX_PERF_TP_RESERVED_99 = 99 -A7XX_PERF_TP_RESERVED_100 = 100 -A7XX_PERF_TP_RESERVED_101 = 101 -A7XX_PERF_TP_RESERVED_102 = 102 -A7XX_PERF_TP_RESERVED_103 = 103 -A7XX_PERF_TP_RESERVED_104 = 104 -A7XX_PERF_TP_RESERVED_105 = 105 -A7XX_PERF_TP_RESERVED_106 = 106 -A7XX_PERF_TP_RESERVED_107 = 107 -A7XX_PERF_TP_RESERVED_108 = 108 -A7XX_PERF_TP_RESERVED_109 = 109 -A7XX_PERF_TP_RESERVED_110 = 110 -A7XX_PERF_TP_RESERVED_111 = 111 -A7XX_PERF_TP_RESERVED_112 = 112 -A7XX_PERF_TP_RESERVED_113 = 113 -A7XX_PERF_TP_RESERVED_114 = 114 -A7XX_PERF_TP_RESERVED_115 = 115 -A7XX_PERF_TP_RESERVED_116 = 116 -A7XX_PERF_TP_RESERVED_117 = 117 -A7XX_PERF_TP_RESERVED_118 = 118 -A7XX_PERF_TP_RESERVED_119 = 119 -A7XX_PERF_TP_RESERVED_120 = 120 -A7XX_PERF_TP_RESERVED_121 = 121 -A7XX_PERF_TP_RESERVED_122 = 122 -A7XX_PERF_TP_RESERVED_123 = 123 -A7XX_PERF_TP_RESERVED_124 = 124 -A7XX_PERF_TP_RESERVED_125 = 125 -A7XX_PERF_TP_RESERVED_126 = 126 -A7XX_PERF_TP_RESERVED_127 = 127 -A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = 128 -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = 129 -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = 130 -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = 131 -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = 132 -a7xx_tp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_sp_perfcounter_select' -a7xx_sp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_SP_NEVER_COUNT', - 1: 'A7XX_PERF_SP_BUSY_CYCLES', - 2: 'A7XX_PERF_SP_ALU_WORKING_CYCLES', - 3: 'A7XX_PERF_SP_STALL_CYCLES_VPC_BE', - 4: 'A7XX_PERF_SP_STALL_CYCLES_TP', - 5: 'A7XX_PERF_SP_STALL_CYCLES_UCHE', - 6: 'A7XX_PERF_SP_STALL_CYCLES_RB', - 7: 'A7XX_PERF_SP_NON_EXECUTION_CYCLES', - 8: 'A7XX_PERF_SP_WAVE_CONTEXTS', - 9: 'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', - 10: 'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', - 11: 'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', - 12: 'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', - 13: 'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', - 14: 'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', - 15: 'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', - 16: 'A7XX_PERF_SP_WAVE_CTRL_CYCLES', - 17: 'A7XX_PERF_SP_WAVE_LOAD_CYCLES', - 18: 'A7XX_PERF_SP_WAVE_EMIT_CYCLES', - 19: 'A7XX_PERF_SP_WAVE_NOP_CYCLES', - 20: 'A7XX_PERF_SP_WAVE_WAIT_CYCLES', - 21: 'A7XX_PERF_SP_WAVE_FETCH_CYCLES', - 22: 'A7XX_PERF_SP_WAVE_IDLE_CYCLES', - 23: 'A7XX_PERF_SP_WAVE_END_CYCLES', - 24: 'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', - 25: 'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 26: 'A7XX_PERF_SP_WAVE_JOIN_CYCLES', - 27: 'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', - 28: 'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', - 29: 'A7XX_PERF_SP_LM_ATOMICS', - 30: 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', - 31: 'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', - 32: 'A7XX_PERF_SP_GM_ATOMICS', - 33: 'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 34: 'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 35: 'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 36: 'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 37: 'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 38: 'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 39: 'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 40: 'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 41: 'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 42: 'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 43: 'A7XX_PERF_SP_VS_INSTRUCTIONS', - 44: 'A7XX_PERF_SP_FS_INSTRUCTIONS', - 45: 'A7XX_PERF_SP_ADDR_LOCK_COUNT', - 46: 'A7XX_PERF_SP_UCHE_READ_TRANS', - 47: 'A7XX_PERF_SP_UCHE_WRITE_TRANS', - 48: 'A7XX_PERF_SP_EXPORT_VPC_TRANS', - 49: 'A7XX_PERF_SP_EXPORT_RB_TRANS', - 50: 'A7XX_PERF_SP_PIXELS_KILLED', - 51: 'A7XX_PERF_SP_ICL1_REQUESTS', - 52: 'A7XX_PERF_SP_ICL1_MISSES', - 53: 'A7XX_PERF_SP_HS_INSTRUCTIONS', - 54: 'A7XX_PERF_SP_DS_INSTRUCTIONS', - 55: 'A7XX_PERF_SP_GS_INSTRUCTIONS', - 56: 'A7XX_PERF_SP_CS_INSTRUCTIONS', - 57: 'A7XX_PERF_SP_GPR_READ', - 58: 'A7XX_PERF_SP_GPR_WRITE', - 59: 'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 60: 'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 61: 'A7XX_PERF_SP_LM_BANK_CONFLICTS', - 62: 'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 63: 'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 64: 'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 65: 'A7XX_PERF_SP_LM_WORKING_CYCLES', - 66: 'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', - 67: 'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', - 68: 'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 69: 'A7XX_PERF_SP_STARVE_CYCLES_HLSQ', - 70: 'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', - 71: 'A7XX_PERF_SP_WORKING_EU', - 72: 'A7XX_PERF_SP_ANY_EU_WORKING', - 73: 'A7XX_PERF_SP_WORKING_EU_FS_STAGE', - 74: 'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', - 75: 'A7XX_PERF_SP_WORKING_EU_VS_STAGE', - 76: 'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', - 77: 'A7XX_PERF_SP_WORKING_EU_CS_STAGE', - 78: 'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', - 79: 'A7XX_PERF_SP_GPR_READ_PREFETCH', - 80: 'A7XX_PERF_SP_GPR_READ_CONFLICT', - 81: 'A7XX_PERF_SP_GPR_WRITE_CONFLICT', - 82: 'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', - 83: 'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 84: 'A7XX_PERF_SP_EXECUTABLE_WAVES', - 85: 'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', - 86: 'A7XX_PERF_SP_RESERVED_86', - 87: 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES', - 88: 'A7XX_PERF_SP_ANY_EU_WORKING_LPAC', - 89: 'A7XX_PERF_SP_WAVE_ALU_CYCLES', - 90: 'A7XX_PERF_SP_WAVE_EFU_CYCLES', - 91: 'A7XX_PERF_SP_WAVE_INT_CYCLES', - 92: 'A7XX_PERF_SP_WAVE_CSP_CYCLES', - 93: 'A7XX_PERF_SP_EWAVE_CONTEXTS', - 94: 'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', - 95: 'A7XX_PERF_SP_LPAC_BUSY_CYCLES', - 96: 'A7XX_PERF_SP_LPAC_INSTRUCTIONS', - 97: 'A7XX_PERF_SP_FS_STAGE_1X_WAVES', - 98: 'A7XX_PERF_SP_FS_STAGE_2X_WAVES', - 99: 'A7XX_PERF_SP_QUADS', - 100: 'A7XX_PERF_SP_CS_INVOCATIONS', - 101: 'A7XX_PERF_SP_PIXELS', - 102: 'A7XX_PERF_SP_LPAC_DRAWCALLS', - 103: 'A7XX_PERF_SP_PI_WORKING_CYCLES', - 104: 'A7XX_PERF_SP_WAVE_INPUT_CYCLES', - 105: 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', - 106: 'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', - 107: 'A7XX_PERF_SP_WAVE_HWAVE_SYNC', - 108: 'A7XX_PERF_SP_OUTPUT_3D_PIXELS', - 109: 'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', - 110: 'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', - 111: 'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', - 112: 'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', - 113: 'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', - 114: 'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', - 115: 'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', - 116: 'A7XX_PERF_SP_ALU_GPR_READ_CYCLES', - 117: 'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', - 118: 'A7XX_PERF_SP_LM_FULL_CYCLES', - 119: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', - 120: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', - 121: 'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', - 122: 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', - 123: 'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', - 124: 'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', - 125: 'A7XX_PERF_SP_RTU_BUSY_CYCLES', - 126: 'A7XX_PERF_SP_RTU_L0_HITS', - 127: 'A7XX_PERF_SP_RTU_L0_MISSES', - 128: 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', - 129: 'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', - 130: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', - 131: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', - 132: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', - 133: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', - 134: 'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', - 135: 'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', - 136: 'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', - 137: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', - 138: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', - 139: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', - 140: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', - 141: 'A7XX_PERF_SP_STCHE_MISS_INC_VS', - 142: 'A7XX_PERF_SP_STCHE_MISS_INC_FS', - 143: 'A7XX_PERF_SP_STCHE_MISS_INC_BV', - 144: 'A7XX_PERF_SP_STCHE_MISS_INC_LPAC', - 145: 'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', - 146: 'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', - 147: 'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', - 148: 'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', - 149: 'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', - 150: 'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', - 151: 'A7XX_PERF_SP_EFU_WORKING_CYCLES', - 152: 'A7XX_PERF_SP_BRANCH_TAKEN', - 153: 'A7XX_PERF_SP_BRANCH_NOT_TAKEN', - 154: 'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', - 155: 'A7XX_PERF_SP_BRANCH_INS_COUNT', - 156: 'A7XX_PERF_SP_PREDICT_TAKEN', - 157: 'A7XX_PERF_SP_PREDICT_NOT_TAKEN', - 158: 'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', - 159: 'A7XX_PERF_SP_PREDICT_INS_COUNT', - 160: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', - 161: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', - 162: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', - 163: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', - 164: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', - 165: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', - 166: 'A7XX_PERF_SP_LB_READ_XFER_ALU', - 167: 'A7XX_PERF_SP_LB_ALU_READ_CONS', - 168: 'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', - 169: 'A7XX_PERF_SP_LB_WRITE_XFER_VPC', - 170: 'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', - 171: 'A7XX_PERF_SP_LB_LDST_RW_LM', - 172: 'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', - 173: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS', - 174: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', - 175: 'A7XX_PERF_SP_GPR_READ_BANK', - 176: 'A7XX_PERF_SP_GPR_WRITE_BANK', - 177: 'A7XX_PERF_SP_VS_WAVE_REQ_PENDING', - 178: 'A7XX_PERF_SP_FS_WAVE_REQ_PENDING', - 179: 'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', - 180: 'A7XX_PERF_SP_WAVE_SPLIT_CNT', - 181: 'A7XX_PERF_SP_FS_OOO_WAVE_ACC', -} -A7XX_PERF_SP_NEVER_COUNT = 0 -A7XX_PERF_SP_BUSY_CYCLES = 1 -A7XX_PERF_SP_ALU_WORKING_CYCLES = 2 -A7XX_PERF_SP_STALL_CYCLES_VPC_BE = 3 -A7XX_PERF_SP_STALL_CYCLES_TP = 4 -A7XX_PERF_SP_STALL_CYCLES_UCHE = 5 -A7XX_PERF_SP_STALL_CYCLES_RB = 6 -A7XX_PERF_SP_NON_EXECUTION_CYCLES = 7 -A7XX_PERF_SP_WAVE_CONTEXTS = 8 -A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = 9 -A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = 10 -A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = 11 -A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = 12 -A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = 13 -A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = 14 -A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = 15 -A7XX_PERF_SP_WAVE_CTRL_CYCLES = 16 -A7XX_PERF_SP_WAVE_LOAD_CYCLES = 17 -A7XX_PERF_SP_WAVE_EMIT_CYCLES = 18 -A7XX_PERF_SP_WAVE_NOP_CYCLES = 19 -A7XX_PERF_SP_WAVE_WAIT_CYCLES = 20 -A7XX_PERF_SP_WAVE_FETCH_CYCLES = 21 -A7XX_PERF_SP_WAVE_IDLE_CYCLES = 22 -A7XX_PERF_SP_WAVE_END_CYCLES = 23 -A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = 24 -A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25 -A7XX_PERF_SP_WAVE_JOIN_CYCLES = 26 -A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = 27 -A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = 28 -A7XX_PERF_SP_LM_ATOMICS = 29 -A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = 30 -A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = 31 -A7XX_PERF_SP_GM_ATOMICS = 32 -A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33 -A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34 -A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35 -A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36 -A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37 -A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38 -A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39 -A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40 -A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41 -A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42 -A7XX_PERF_SP_VS_INSTRUCTIONS = 43 -A7XX_PERF_SP_FS_INSTRUCTIONS = 44 -A7XX_PERF_SP_ADDR_LOCK_COUNT = 45 -A7XX_PERF_SP_UCHE_READ_TRANS = 46 -A7XX_PERF_SP_UCHE_WRITE_TRANS = 47 -A7XX_PERF_SP_EXPORT_VPC_TRANS = 48 -A7XX_PERF_SP_EXPORT_RB_TRANS = 49 -A7XX_PERF_SP_PIXELS_KILLED = 50 -A7XX_PERF_SP_ICL1_REQUESTS = 51 -A7XX_PERF_SP_ICL1_MISSES = 52 -A7XX_PERF_SP_HS_INSTRUCTIONS = 53 -A7XX_PERF_SP_DS_INSTRUCTIONS = 54 -A7XX_PERF_SP_GS_INSTRUCTIONS = 55 -A7XX_PERF_SP_CS_INSTRUCTIONS = 56 -A7XX_PERF_SP_GPR_READ = 57 -A7XX_PERF_SP_GPR_WRITE = 58 -A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59 -A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60 -A7XX_PERF_SP_LM_BANK_CONFLICTS = 61 -A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62 -A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63 -A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64 -A7XX_PERF_SP_LM_WORKING_CYCLES = 65 -A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = 66 -A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = 67 -A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68 -A7XX_PERF_SP_STARVE_CYCLES_HLSQ = 69 -A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = 70 -A7XX_PERF_SP_WORKING_EU = 71 -A7XX_PERF_SP_ANY_EU_WORKING = 72 -A7XX_PERF_SP_WORKING_EU_FS_STAGE = 73 -A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = 74 -A7XX_PERF_SP_WORKING_EU_VS_STAGE = 75 -A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = 76 -A7XX_PERF_SP_WORKING_EU_CS_STAGE = 77 -A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = 78 -A7XX_PERF_SP_GPR_READ_PREFETCH = 79 -A7XX_PERF_SP_GPR_READ_CONFLICT = 80 -A7XX_PERF_SP_GPR_WRITE_CONFLICT = 81 -A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = 82 -A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83 -A7XX_PERF_SP_EXECUTABLE_WAVES = 84 -A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = 85 -A7XX_PERF_SP_RESERVED_86 = 86 -A7XX_PERF_SP_BYPASS_BUSY_CYCLES = 87 -A7XX_PERF_SP_ANY_EU_WORKING_LPAC = 88 -A7XX_PERF_SP_WAVE_ALU_CYCLES = 89 -A7XX_PERF_SP_WAVE_EFU_CYCLES = 90 -A7XX_PERF_SP_WAVE_INT_CYCLES = 91 -A7XX_PERF_SP_WAVE_CSP_CYCLES = 92 -A7XX_PERF_SP_EWAVE_CONTEXTS = 93 -A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = 94 -A7XX_PERF_SP_LPAC_BUSY_CYCLES = 95 -A7XX_PERF_SP_LPAC_INSTRUCTIONS = 96 -A7XX_PERF_SP_FS_STAGE_1X_WAVES = 97 -A7XX_PERF_SP_FS_STAGE_2X_WAVES = 98 -A7XX_PERF_SP_QUADS = 99 -A7XX_PERF_SP_CS_INVOCATIONS = 100 -A7XX_PERF_SP_PIXELS = 101 -A7XX_PERF_SP_LPAC_DRAWCALLS = 102 -A7XX_PERF_SP_PI_WORKING_CYCLES = 103 -A7XX_PERF_SP_WAVE_INPUT_CYCLES = 104 -A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = 105 -A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = 106 -A7XX_PERF_SP_WAVE_HWAVE_SYNC = 107 -A7XX_PERF_SP_OUTPUT_3D_PIXELS = 108 -A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = 109 -A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = 110 -A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = 111 -A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = 112 -A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = 113 -A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = 114 -A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = 115 -A7XX_PERF_SP_ALU_GPR_READ_CYCLES = 116 -A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = 117 -A7XX_PERF_SP_LM_FULL_CYCLES = 118 -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = 119 -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = 120 -A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = 121 -A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = 122 -A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = 123 -A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = 124 -A7XX_PERF_SP_RTU_BUSY_CYCLES = 125 -A7XX_PERF_SP_RTU_L0_HITS = 126 -A7XX_PERF_SP_RTU_L0_MISSES = 127 -A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = 128 -A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = 129 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = 130 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = 131 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = 132 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = 133 -A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = 134 -A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = 135 -A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = 136 -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = 137 -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = 138 -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = 139 -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = 140 -A7XX_PERF_SP_STCHE_MISS_INC_VS = 141 -A7XX_PERF_SP_STCHE_MISS_INC_FS = 142 -A7XX_PERF_SP_STCHE_MISS_INC_BV = 143 -A7XX_PERF_SP_STCHE_MISS_INC_LPAC = 144 -A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = 145 -A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = 146 -A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = 147 -A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = 148 -A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = 149 -A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = 150 -A7XX_PERF_SP_EFU_WORKING_CYCLES = 151 -A7XX_PERF_SP_BRANCH_TAKEN = 152 -A7XX_PERF_SP_BRANCH_NOT_TAKEN = 153 -A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = 154 -A7XX_PERF_SP_BRANCH_INS_COUNT = 155 -A7XX_PERF_SP_PREDICT_TAKEN = 156 -A7XX_PERF_SP_PREDICT_NOT_TAKEN = 157 -A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = 158 -A7XX_PERF_SP_PREDICT_INS_COUNT = 159 -A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = 160 -A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = 161 -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = 162 -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = 163 -A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = 164 -A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = 165 -A7XX_PERF_SP_LB_READ_XFER_ALU = 166 -A7XX_PERF_SP_LB_ALU_READ_CONS = 167 -A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = 168 -A7XX_PERF_SP_LB_WRITE_XFER_VPC = 169 -A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = 170 -A7XX_PERF_SP_LB_LDST_RW_LM = 171 -A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = 172 -A7XX_PERF_SP_LB_LDST_WRITE_CONS = 173 -A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = 174 -A7XX_PERF_SP_GPR_READ_BANK = 175 -A7XX_PERF_SP_GPR_WRITE_BANK = 176 -A7XX_PERF_SP_VS_WAVE_REQ_PENDING = 177 -A7XX_PERF_SP_FS_WAVE_REQ_PENDING = 178 -A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = 179 -A7XX_PERF_SP_WAVE_SPLIT_CNT = 180 -A7XX_PERF_SP_FS_OOO_WAVE_ACC = 181 -a7xx_sp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_rb_perfcounter_select' -a7xx_rb_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RB_NEVER_COUNT', - 1: 'A7XX_PERF_RB_BUSY_CYCLES', - 2: 'A7XX_PERF_RB_STALL_CYCLES_HLSQ', - 3: 'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', - 4: 'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', - 5: 'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', - 6: 'A7XX_PERF_RB_STARVE_CYCLES_SP', - 7: 'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', - 8: 'A7XX_PERF_RB_STARVE_CYCLES_CCU', - 9: 'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', - 10: 'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', - 11: 'A7XX_PERF_RB_Z_WORKLOAD', - 12: 'A7XX_PERF_RB_HLSQ_ACTIVE', - 13: 'A7XX_PERF_RB_Z_READ', - 14: 'A7XX_PERF_RB_Z_WRITE', - 15: 'A7XX_PERF_RB_C_READ', - 16: 'A7XX_PERF_RB_C_WRITE', - 17: 'A7XX_PERF_RB_TOTAL_PASS', - 18: 'A7XX_PERF_RB_Z_PASS', - 19: 'A7XX_PERF_RB_Z_FAIL', - 20: 'A7XX_PERF_RB_S_FAIL', - 21: 'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', - 22: 'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', - 23: 'A7XX_PERF_RB_PS_INVOCATIONS', - 24: 'A7XX_PERF_RB_2D_ALIVE_CYCLES', - 25: 'A7XX_PERF_RB_2D_STARVE_CYCLES_SP', - 26: 'A7XX_PERF_RB_2D_VALID_PIXELS', - 27: 'A7XX_PERF_RB_3D_PIXELS', - 28: 'A7XX_PERF_RB_BLENDER_WORKING_CYCLES', - 29: 'A7XX_PERF_RB_ZPROC_WORKING_CYCLES', - 30: 'A7XX_PERF_RB_CPROC_WORKING_CYCLES', - 31: 'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', - 32: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 33: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 34: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 35: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 36: 'A7XX_PERF_RB_STALL_CYCLES_VPC_BE', - 37: 'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', - 38: 'A7XX_PERF_RB_COLOR_PIX_TILES', - 39: 'A7XX_PERF_RB_STALL_CYCLES_CCU', - 40: 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', - 41: 'A7XX_PERF_RB_LATE_Z_ARB3_GRANT', - 42: 'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', - 43: 'A7XX_PERF_RB_VRS_1X1_QUADS', - 44: 'A7XX_PERF_RB_VRS_2X1_QUADS', - 45: 'A7XX_PERF_RB_VRS_1X2_QUADS', - 46: 'A7XX_PERF_RB_VRS_2X2_QUADS', - 47: 'A7XX_PERF_RB_VRS_2X4_QUADS', - 48: 'A7XX_PERF_RB_VRS_4X2_QUADS', - 49: 'A7XX_PERF_RB_VRS_4X4_QUADS', -} -A7XX_PERF_RB_NEVER_COUNT = 0 -A7XX_PERF_RB_BUSY_CYCLES = 1 -A7XX_PERF_RB_STALL_CYCLES_HLSQ = 2 -A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = 3 -A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = 4 -A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = 5 -A7XX_PERF_RB_STARVE_CYCLES_SP = 6 -A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = 7 -A7XX_PERF_RB_STARVE_CYCLES_CCU = 8 -A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = 9 -A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = 10 -A7XX_PERF_RB_Z_WORKLOAD = 11 -A7XX_PERF_RB_HLSQ_ACTIVE = 12 -A7XX_PERF_RB_Z_READ = 13 -A7XX_PERF_RB_Z_WRITE = 14 -A7XX_PERF_RB_C_READ = 15 -A7XX_PERF_RB_C_WRITE = 16 -A7XX_PERF_RB_TOTAL_PASS = 17 -A7XX_PERF_RB_Z_PASS = 18 -A7XX_PERF_RB_Z_FAIL = 19 -A7XX_PERF_RB_S_FAIL = 20 -A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = 21 -A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = 22 -A7XX_PERF_RB_PS_INVOCATIONS = 23 -A7XX_PERF_RB_2D_ALIVE_CYCLES = 24 -A7XX_PERF_RB_2D_STARVE_CYCLES_SP = 25 -A7XX_PERF_RB_2D_VALID_PIXELS = 26 -A7XX_PERF_RB_3D_PIXELS = 27 -A7XX_PERF_RB_BLENDER_WORKING_CYCLES = 28 -A7XX_PERF_RB_ZPROC_WORKING_CYCLES = 29 -A7XX_PERF_RB_CPROC_WORKING_CYCLES = 30 -A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = 31 -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 32 -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 33 -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 34 -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 35 -A7XX_PERF_RB_STALL_CYCLES_VPC_BE = 36 -A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = 37 -A7XX_PERF_RB_COLOR_PIX_TILES = 38 -A7XX_PERF_RB_STALL_CYCLES_CCU = 39 -A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = 40 -A7XX_PERF_RB_LATE_Z_ARB3_GRANT = 41 -A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = 42 -A7XX_PERF_RB_VRS_1X1_QUADS = 43 -A7XX_PERF_RB_VRS_2X1_QUADS = 44 -A7XX_PERF_RB_VRS_1X2_QUADS = 45 -A7XX_PERF_RB_VRS_2X2_QUADS = 46 -A7XX_PERF_RB_VRS_2X4_QUADS = 47 -A7XX_PERF_RB_VRS_4X2_QUADS = 48 -A7XX_PERF_RB_VRS_4X4_QUADS = 49 -a7xx_rb_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vsc_perfcounter_select' -a7xx_vsc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VSC_NEVER_COUNT', - 1: 'A7XX_PERF_VSC_BUSY_CYCLES', - 2: 'A7XX_PERF_VSC_WORKING_CYCLES', - 3: 'A7XX_PERF_VSC_STALL_CYCLES_UCHE', - 4: 'A7XX_PERF_VSC_EOT_NUM', - 5: 'A7XX_PERF_VSC_INPUT_TILES', - 6: 'A7XX_PERF_VSC_TILE_COMP_TRAN', - 7: 'A7XX_PERF_VSC_TILE_BYPASS_TRAN', -} -A7XX_PERF_VSC_NEVER_COUNT = 0 -A7XX_PERF_VSC_BUSY_CYCLES = 1 -A7XX_PERF_VSC_WORKING_CYCLES = 2 -A7XX_PERF_VSC_STALL_CYCLES_UCHE = 3 -A7XX_PERF_VSC_EOT_NUM = 4 -A7XX_PERF_VSC_INPUT_TILES = 5 -A7XX_PERF_VSC_TILE_COMP_TRAN = 6 -A7XX_PERF_VSC_TILE_BYPASS_TRAN = 7 -a7xx_vsc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ccu_perfcounter_select' -a7xx_ccu_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CCU_NEVER_COUNT', - 1: 'A7XX_PERF_CCU_BUSY_CYCLES', - 2: 'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 3: 'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 4: 'A7XX_PERF_CCU_DEPTH_BLOCKS', - 5: 'A7XX_PERF_CCU_COLOR_BLOCKS', - 6: 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT', - 7: 'A7XX_PERF_CCU_COLOR_BLOCK_HIT', - 8: 'A7XX_PERF_CCU_PARTIAL_BLOCK_READ', - 9: 'A7XX_PERF_CCU_GMEM_READ', - 10: 'A7XX_PERF_CCU_GMEM_WRITE', - 11: 'A7XX_PERF_CCU_2D_RD_REQ', - 12: 'A7XX_PERF_CCU_2D_WR_REQ', - 13: 'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', - 14: 'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', - 15: 'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', - 16: 'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', - 17: 'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', - 18: 'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', - 19: 'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', - 20: 'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', - 21: 'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', - 22: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', - 23: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', - 24: 'A7XX_PERF_CCU_COLOR_EVB_STALL', - 25: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', - 26: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', - 27: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', - 28: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', - 29: 'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', - 30: 'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', - 31: 'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', - 32: 'A7XX_PERF_CCU_RESERVED_32', - 33: 'A7XX_PERF_CCU_RESERVED_33', - 34: 'A7XX_PERF_CCU_RESERVED_34', - 35: 'A7XX_PERF_CCU_RESERVED_35', - 36: 'A7XX_PERF_CCU_RESERVED_36', - 37: 'A7XX_PERF_CCU_RESERVED_37', - 38: 'A7XX_PERF_CCU_RESERVED_38', - 39: 'A7XX_PERF_CCU_RESERVED_39', - 40: 'A7XX_PERF_CCU_RESERVED_40', - 41: 'A7XX_PERF_CCU_RESERVED_41', - 42: 'A7XX_PERF_CCU_RESERVED_42', - 43: 'A7XX_PERF_CCU_RESERVED_43', - 44: 'A7XX_PERF_CCU_RESERVED_44', - 45: 'A7XX_PERF_CCU_RESERVED_45', - 46: 'A7XX_PERF_CCU_RESERVED_46', - 47: 'A7XX_PERF_CCU_RESERVED_47', - 48: 'A7XX_PERF_CCU_RESERVED_48', - 49: 'A7XX_PERF_CCU_RESERVED_49', - 50: 'A7XX_PERF_CCU_RESERVED_50', - 51: 'A7XX_PERF_CCU_RESERVED_51', - 52: 'A7XX_PERF_CCU_RESERVED_52', - 53: 'A7XX_PERF_CCU_RESERVED_53', - 54: 'A7XX_PERF_CCU_RESERVED_54', - 55: 'A7XX_PERF_CCU_RESERVED_55', - 56: 'A7XX_PERF_CCU_RESERVED_56', - 57: 'A7XX_PERF_CCU_RESERVED_57', - 58: 'A7XX_PERF_CCU_RESERVED_58', - 59: 'A7XX_PERF_CCU_RESERVED_59', - 60: 'A7XX_PERF_CCU_RESERVED_60', - 61: 'A7XX_PERF_CCU_RESERVED_61', - 62: 'A7XX_PERF_CCU_RESERVED_62', - 63: 'A7XX_PERF_CCU_RESERVED_63', - 64: 'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', - 65: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', - 66: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', - 67: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', - 68: 'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', - 69: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', - 70: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', - 71: 'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', - 72: 'A7XX_PERF_UFC_L0_SP_REQUESTS', - 73: 'A7XX_PERF_UFC_L0_SP_FILTER_HIT', - 74: 'A7XX_PERF_UFC_L0_SP_FILTER_MISS', - 75: 'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', - 76: 'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', - 77: 'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', - 78: 'A7XX_PERF_CCU_RESERVED_78', - 79: 'A7XX_PERF_CCU_RESERVED_79', - 80: 'A7XX_PERF_CCU_RESERVED_80', - 81: 'A7XX_PERF_CCU_RESERVED_81', - 82: 'A7XX_PERF_CCU_RESERVED_82', - 83: 'A7XX_PERF_CCU_RESERVED_83', - 84: 'A7XX_PERF_CCU_RESERVED_84', - 85: 'A7XX_PERF_CCU_RESERVED_85', - 86: 'A7XX_PERF_CCU_RESERVED_86', - 87: 'A7XX_PERF_CCU_RESERVED_87', - 88: 'A7XX_PERF_CCU_RESERVED_88', - 89: 'A7XX_PERF_CCU_RESERVED_89', - 90: 'A7XX_PERF_CCU_RESERVED_90', - 91: 'A7XX_PERF_CCU_RESERVED_91', - 92: 'A7XX_PERF_CCU_RESERVED_92', - 93: 'A7XX_PERF_CCU_RESERVED_93', - 94: 'A7XX_PERF_CCU_RESERVED_94', - 95: 'A7XX_PERF_CCU_RESERVED_95', - 96: 'A7XX_PERF_CCU_RESERVED_96', - 97: 'A7XX_PERF_CCU_RESERVED_97', - 98: 'A7XX_PERF_CCU_RESERVED_98', - 99: 'A7XX_PERF_CCU_RESERVED_99', - 100: 'A7XX_PERF_CCU_RESERVED_100', - 101: 'A7XX_PERF_CCU_RESERVED_101', - 102: 'A7XX_PERF_CCU_RESERVED_102', - 103: 'A7XX_PERF_CCU_RESERVED_103', - 104: 'A7XX_PERF_CCU_RESERVED_104', - 105: 'A7XX_PERF_CCU_RESERVED_105', - 106: 'A7XX_PERF_CCU_RESERVED_106', - 107: 'A7XX_PERF_CCU_RESERVED_107', - 108: 'A7XX_PERF_CCU_RESERVED_108', - 109: 'A7XX_PERF_CCU_RESERVED_109', - 110: 'A7XX_PERF_CCU_RESERVED_110', - 111: 'A7XX_PERF_CCU_RESERVED_111', - 112: 'A7XX_PERF_CCU_RESERVED_112', - 113: 'A7XX_PERF_CCU_RESERVED_113', - 114: 'A7XX_PERF_CCU_RESERVED_114', - 115: 'A7XX_PERF_CCU_RESERVED_115', - 116: 'A7XX_PERF_CCU_RESERVED_116', - 117: 'A7XX_PERF_CCU_RESERVED_117', - 118: 'A7XX_PERF_CCU_RESERVED_118', - 119: 'A7XX_PERF_CCU_RESERVED_119', - 120: 'A7XX_PERF_CCU_RESERVED_120', - 121: 'A7XX_PERF_CCU_RESERVED_121', - 122: 'A7XX_PERF_CCU_RESERVED_122', - 123: 'A7XX_PERF_CCU_RESERVED_123', - 124: 'A7XX_PERF_CCU_RESERVED_124', - 125: 'A7XX_PERF_CCU_RESERVED_125', - 126: 'A7XX_PERF_CCU_RESERVED_126', - 127: 'A7XX_PERF_CCU_RESERVED_127', - 128: 'A7XX_PERF_CRE_RESOLVE_EVENTS', - 129: 'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', - 130: 'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', - 131: 'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', - 132: 'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', - 133: 'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', - 134: 'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', - 135: 'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', - 136: 'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', -} -A7XX_PERF_CCU_NEVER_COUNT = 0 -A7XX_PERF_CCU_BUSY_CYCLES = 1 -A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 2 -A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 3 -A7XX_PERF_CCU_DEPTH_BLOCKS = 4 -A7XX_PERF_CCU_COLOR_BLOCKS = 5 -A7XX_PERF_CCU_DEPTH_BLOCK_HIT = 6 -A7XX_PERF_CCU_COLOR_BLOCK_HIT = 7 -A7XX_PERF_CCU_PARTIAL_BLOCK_READ = 8 -A7XX_PERF_CCU_GMEM_READ = 9 -A7XX_PERF_CCU_GMEM_WRITE = 10 -A7XX_PERF_CCU_2D_RD_REQ = 11 -A7XX_PERF_CCU_2D_WR_REQ = 12 -A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = 13 -A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = 14 -A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = 15 -A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = 16 -A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = 17 -A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = 18 -A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = 19 -A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = 20 -A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = 21 -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = 22 -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = 23 -A7XX_PERF_CCU_COLOR_EVB_STALL = 24 -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = 25 -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = 26 -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = 27 -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = 28 -A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = 29 -A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = 30 -A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = 31 -A7XX_PERF_CCU_RESERVED_32 = 32 -A7XX_PERF_CCU_RESERVED_33 = 33 -A7XX_PERF_CCU_RESERVED_34 = 34 -A7XX_PERF_CCU_RESERVED_35 = 35 -A7XX_PERF_CCU_RESERVED_36 = 36 -A7XX_PERF_CCU_RESERVED_37 = 37 -A7XX_PERF_CCU_RESERVED_38 = 38 -A7XX_PERF_CCU_RESERVED_39 = 39 -A7XX_PERF_CCU_RESERVED_40 = 40 -A7XX_PERF_CCU_RESERVED_41 = 41 -A7XX_PERF_CCU_RESERVED_42 = 42 -A7XX_PERF_CCU_RESERVED_43 = 43 -A7XX_PERF_CCU_RESERVED_44 = 44 -A7XX_PERF_CCU_RESERVED_45 = 45 -A7XX_PERF_CCU_RESERVED_46 = 46 -A7XX_PERF_CCU_RESERVED_47 = 47 -A7XX_PERF_CCU_RESERVED_48 = 48 -A7XX_PERF_CCU_RESERVED_49 = 49 -A7XX_PERF_CCU_RESERVED_50 = 50 -A7XX_PERF_CCU_RESERVED_51 = 51 -A7XX_PERF_CCU_RESERVED_52 = 52 -A7XX_PERF_CCU_RESERVED_53 = 53 -A7XX_PERF_CCU_RESERVED_54 = 54 -A7XX_PERF_CCU_RESERVED_55 = 55 -A7XX_PERF_CCU_RESERVED_56 = 56 -A7XX_PERF_CCU_RESERVED_57 = 57 -A7XX_PERF_CCU_RESERVED_58 = 58 -A7XX_PERF_CCU_RESERVED_59 = 59 -A7XX_PERF_CCU_RESERVED_60 = 60 -A7XX_PERF_CCU_RESERVED_61 = 61 -A7XX_PERF_CCU_RESERVED_62 = 62 -A7XX_PERF_CCU_RESERVED_63 = 63 -A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = 64 -A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = 65 -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = 66 -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = 67 -A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = 68 -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = 69 -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = 70 -A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = 71 -A7XX_PERF_UFC_L0_SP_REQUESTS = 72 -A7XX_PERF_UFC_L0_SP_FILTER_HIT = 73 -A7XX_PERF_UFC_L0_SP_FILTER_MISS = 74 -A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = 75 -A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = 76 -A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = 77 -A7XX_PERF_CCU_RESERVED_78 = 78 -A7XX_PERF_CCU_RESERVED_79 = 79 -A7XX_PERF_CCU_RESERVED_80 = 80 -A7XX_PERF_CCU_RESERVED_81 = 81 -A7XX_PERF_CCU_RESERVED_82 = 82 -A7XX_PERF_CCU_RESERVED_83 = 83 -A7XX_PERF_CCU_RESERVED_84 = 84 -A7XX_PERF_CCU_RESERVED_85 = 85 -A7XX_PERF_CCU_RESERVED_86 = 86 -A7XX_PERF_CCU_RESERVED_87 = 87 -A7XX_PERF_CCU_RESERVED_88 = 88 -A7XX_PERF_CCU_RESERVED_89 = 89 -A7XX_PERF_CCU_RESERVED_90 = 90 -A7XX_PERF_CCU_RESERVED_91 = 91 -A7XX_PERF_CCU_RESERVED_92 = 92 -A7XX_PERF_CCU_RESERVED_93 = 93 -A7XX_PERF_CCU_RESERVED_94 = 94 -A7XX_PERF_CCU_RESERVED_95 = 95 -A7XX_PERF_CCU_RESERVED_96 = 96 -A7XX_PERF_CCU_RESERVED_97 = 97 -A7XX_PERF_CCU_RESERVED_98 = 98 -A7XX_PERF_CCU_RESERVED_99 = 99 -A7XX_PERF_CCU_RESERVED_100 = 100 -A7XX_PERF_CCU_RESERVED_101 = 101 -A7XX_PERF_CCU_RESERVED_102 = 102 -A7XX_PERF_CCU_RESERVED_103 = 103 -A7XX_PERF_CCU_RESERVED_104 = 104 -A7XX_PERF_CCU_RESERVED_105 = 105 -A7XX_PERF_CCU_RESERVED_106 = 106 -A7XX_PERF_CCU_RESERVED_107 = 107 -A7XX_PERF_CCU_RESERVED_108 = 108 -A7XX_PERF_CCU_RESERVED_109 = 109 -A7XX_PERF_CCU_RESERVED_110 = 110 -A7XX_PERF_CCU_RESERVED_111 = 111 -A7XX_PERF_CCU_RESERVED_112 = 112 -A7XX_PERF_CCU_RESERVED_113 = 113 -A7XX_PERF_CCU_RESERVED_114 = 114 -A7XX_PERF_CCU_RESERVED_115 = 115 -A7XX_PERF_CCU_RESERVED_116 = 116 -A7XX_PERF_CCU_RESERVED_117 = 117 -A7XX_PERF_CCU_RESERVED_118 = 118 -A7XX_PERF_CCU_RESERVED_119 = 119 -A7XX_PERF_CCU_RESERVED_120 = 120 -A7XX_PERF_CCU_RESERVED_121 = 121 -A7XX_PERF_CCU_RESERVED_122 = 122 -A7XX_PERF_CCU_RESERVED_123 = 123 -A7XX_PERF_CCU_RESERVED_124 = 124 -A7XX_PERF_CCU_RESERVED_125 = 125 -A7XX_PERF_CCU_RESERVED_126 = 126 -A7XX_PERF_CCU_RESERVED_127 = 127 -A7XX_PERF_CRE_RESOLVE_EVENTS = 128 -A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = 129 -A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = 130 -A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = 131 -A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = 132 -A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = 133 -A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = 134 -A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = 135 -A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = 136 -a7xx_ccu_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_lrz_perfcounter_select' -a7xx_lrz_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_LRZ_NEVER_COUNT', - 1: 'A7XX_PERF_LRZ_BUSY_CYCLES', - 2: 'A7XX_PERF_LRZ_STARVE_CYCLES_RAS', - 3: 'A7XX_PERF_LRZ_STALL_CYCLES_RB', - 4: 'A7XX_PERF_LRZ_STALL_CYCLES_VSC', - 5: 'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', - 6: 'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', - 7: 'A7XX_PERF_LRZ_STALL_CYCLES_UCHE', - 8: 'A7XX_PERF_LRZ_LRZ_READ', - 9: 'A7XX_PERF_LRZ_LRZ_WRITE', - 10: 'A7XX_PERF_LRZ_READ_LATENCY', - 11: 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', - 12: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 13: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', - 14: 'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 15: 'A7XX_PERF_LRZ_FULL_8X8_TILES', - 16: 'A7XX_PERF_LRZ_PARTIAL_8X8_TILES', - 17: 'A7XX_PERF_LRZ_TILE_KILLED', - 18: 'A7XX_PERF_LRZ_TOTAL_PIXEL', - 19: 'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 20: 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT', - 21: 'A7XX_PERF_LRZ_FEEDBACK_DISCARD', - 22: 'A7XX_PERF_LRZ_FEEDBACK_STALL', - 23: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 24: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 25: 'A7XX_PERF_LRZ_RAS_MASK_TRANS', - 26: 'A7XX_PERF_LRZ_STALL_CYCLES_MVC', - 27: 'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', - 28: 'A7XX_PERF_LRZ_TILE_KILLED_BY_Z', - 29: 'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', - 30: 'A7XX_PERF_LRZ_NUM_FLOCK', -} -A7XX_PERF_LRZ_NEVER_COUNT = 0 -A7XX_PERF_LRZ_BUSY_CYCLES = 1 -A7XX_PERF_LRZ_STARVE_CYCLES_RAS = 2 -A7XX_PERF_LRZ_STALL_CYCLES_RB = 3 -A7XX_PERF_LRZ_STALL_CYCLES_VSC = 4 -A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = 5 -A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = 6 -A7XX_PERF_LRZ_STALL_CYCLES_UCHE = 7 -A7XX_PERF_LRZ_LRZ_READ = 8 -A7XX_PERF_LRZ_LRZ_WRITE = 9 -A7XX_PERF_LRZ_READ_LATENCY = 10 -A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = 11 -A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 12 -A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = 13 -A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 14 -A7XX_PERF_LRZ_FULL_8X8_TILES = 15 -A7XX_PERF_LRZ_PARTIAL_8X8_TILES = 16 -A7XX_PERF_LRZ_TILE_KILLED = 17 -A7XX_PERF_LRZ_TOTAL_PIXEL = 18 -A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 19 -A7XX_PERF_LRZ_FEEDBACK_ACCEPT = 20 -A7XX_PERF_LRZ_FEEDBACK_DISCARD = 21 -A7XX_PERF_LRZ_FEEDBACK_STALL = 22 -A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 23 -A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = 24 -A7XX_PERF_LRZ_RAS_MASK_TRANS = 25 -A7XX_PERF_LRZ_STALL_CYCLES_MVC = 26 -A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = 27 -A7XX_PERF_LRZ_TILE_KILLED_BY_Z = 28 -A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = 29 -A7XX_PERF_LRZ_NUM_FLOCK = 30 -a7xx_lrz_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cmp_perfcounter_select' -a7xx_cmp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CMPDECMP_NEVER_COUNT', - 1: 'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', - 2: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 3: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 4: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 5: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 6: 'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', - 7: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 8: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA', - 9: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', - 10: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 11: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 12: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 13: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 14: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 15: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 16: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 17: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 18: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 19: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 20: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 21: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 22: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 23: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 24: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 25: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 26: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 27: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 28: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 29: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 30: 'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', - 31: 'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', - 32: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', - 33: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', - 34: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', - 35: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', - 36: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', - 37: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', - 38: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', - 39: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', - 40: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', - 41: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', - 42: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', - 43: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', - 44: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', - 45: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', - 46: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', - 47: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', -} -A7XX_PERF_CMPDECMP_NEVER_COUNT = 0 -A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = 1 -A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 2 -A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 3 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = 4 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 5 -A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = 6 -A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = 7 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA = 8 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = 9 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 10 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 11 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 12 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 13 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 14 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 15 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 16 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 17 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 18 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 19 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 20 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 21 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 22 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 23 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 24 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 25 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 26 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 27 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 28 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 29 -A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = 30 -A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = 31 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = 32 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = 33 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = 34 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = 35 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = 36 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = 37 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = 38 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = 39 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = 40 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = 41 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = 42 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = 43 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = 44 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = 45 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = 46 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = 47 -a7xx_cmp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_gbif_perfcounter_select' -a7xx_gbif_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_GBIF_NEVER_COUNT', - 1: 'A7XX_PERF_GBIF_RESERVED_1', - 2: 'A7XX_PERF_GBIF_RESERVED_2', - 3: 'A7XX_PERF_GBIF_RESERVED_3', - 4: 'A7XX_PERF_GBIF_RESERVED_4', - 5: 'A7XX_PERF_GBIF_RESERVED_5', - 6: 'A7XX_PERF_GBIF_RESERVED_6', - 7: 'A7XX_PERF_GBIF_RESERVED_7', - 8: 'A7XX_PERF_GBIF_RESERVED_8', - 9: 'A7XX_PERF_GBIF_RESERVED_9', - 10: 'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', - 11: 'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', - 12: 'A7XX_PERF_GBIF_RESERVED_12', - 13: 'A7XX_PERF_GBIF_RESERVED_13', - 14: 'A7XX_PERF_GBIF_RESERVED_14', - 15: 'A7XX_PERF_GBIF_RESERVED_15', - 16: 'A7XX_PERF_GBIF_RESERVED_16', - 17: 'A7XX_PERF_GBIF_RESERVED_17', - 18: 'A7XX_PERF_GBIF_RESERVED_18', - 19: 'A7XX_PERF_GBIF_RESERVED_19', - 20: 'A7XX_PERF_GBIF_RESERVED_20', - 21: 'A7XX_PERF_GBIF_RESERVED_21', - 22: 'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', - 23: 'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', - 24: 'A7XX_PERF_GBIF_RESERVED_24', - 25: 'A7XX_PERF_GBIF_RESERVED_25', - 26: 'A7XX_PERF_GBIF_RESERVED_26', - 27: 'A7XX_PERF_GBIF_RESERVED_27', - 28: 'A7XX_PERF_GBIF_RESERVED_28', - 29: 'A7XX_PERF_GBIF_RESERVED_29', - 30: 'A7XX_PERF_GBIF_RESERVED_30', - 31: 'A7XX_PERF_GBIF_RESERVED_31', - 32: 'A7XX_PERF_GBIF_RESERVED_32', - 33: 'A7XX_PERF_GBIF_RESERVED_33', - 34: 'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', - 35: 'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', - 36: 'A7XX_PERF_GBIF_RESERVED_36', - 37: 'A7XX_PERF_GBIF_RESERVED_37', - 38: 'A7XX_PERF_GBIF_RESERVED_38', - 39: 'A7XX_PERF_GBIF_RESERVED_39', - 40: 'A7XX_PERF_GBIF_RESERVED_40', - 41: 'A7XX_PERF_GBIF_RESERVED_41', - 42: 'A7XX_PERF_GBIF_RESERVED_42', - 43: 'A7XX_PERF_GBIF_RESERVED_43', - 44: 'A7XX_PERF_GBIF_RESERVED_44', - 45: 'A7XX_PERF_GBIF_RESERVED_45', - 46: 'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', - 47: 'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', - 48: 'A7XX_PERF_GBIF_RESERVED_48', - 49: 'A7XX_PERF_GBIF_RESERVED_49', - 50: 'A7XX_PERF_GBIF_RESERVED_50', - 51: 'A7XX_PERF_GBIF_RESERVED_51', - 52: 'A7XX_PERF_GBIF_RESERVED_52', - 53: 'A7XX_PERF_GBIF_RESERVED_53', - 54: 'A7XX_PERF_GBIF_RESERVED_54', - 55: 'A7XX_PERF_GBIF_RESERVED_55', - 56: 'A7XX_PERF_GBIF_RESERVED_56', - 57: 'A7XX_PERF_GBIF_RESERVED_57', - 58: 'A7XX_PERF_GBIF_RESERVED_58', - 59: 'A7XX_PERF_GBIF_RESERVED_59', - 60: 'A7XX_PERF_GBIF_RESERVED_60', - 61: 'A7XX_PERF_GBIF_RESERVED_61', - 62: 'A7XX_PERF_GBIF_RESERVED_62', - 63: 'A7XX_PERF_GBIF_RESERVED_63', - 64: 'A7XX_PERF_GBIF_RESERVED_64', - 65: 'A7XX_PERF_GBIF_RESERVED_65', - 66: 'A7XX_PERF_GBIF_RESERVED_66', - 67: 'A7XX_PERF_GBIF_RESERVED_67', - 68: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', - 69: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', - 70: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', - 71: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', - 72: 'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', - 73: 'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', - 74: 'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', - 75: 'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', - 76: 'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', - 77: 'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', - 78: 'A7XX_PERF_GBIF_RESERVED_78', - 79: 'A7XX_PERF_GBIF_RESERVED_79', - 80: 'A7XX_PERF_GBIF_RESERVED_80', - 81: 'A7XX_PERF_GBIF_RESERVED_81', - 82: 'A7XX_PERF_GBIF_RESERVED_82', - 83: 'A7XX_PERF_GBIF_RESERVED_83', - 84: 'A7XX_PERF_GBIF_RESERVED_84', - 85: 'A7XX_PERF_GBIF_RESERVED_85', - 86: 'A7XX_PERF_GBIF_RESERVED_86', - 87: 'A7XX_PERF_GBIF_RESERVED_87', - 88: 'A7XX_PERF_GBIF_RESERVED_88', - 89: 'A7XX_PERF_GBIF_RESERVED_89', - 90: 'A7XX_PERF_GBIF_RESERVED_90', - 91: 'A7XX_PERF_GBIF_RESERVED_91', - 92: 'A7XX_PERF_GBIF_RESERVED_92', - 93: 'A7XX_PERF_GBIF_RESERVED_93', - 94: 'A7XX_PERF_GBIF_RESERVED_94', - 95: 'A7XX_PERF_GBIF_RESERVED_95', - 96: 'A7XX_PERF_GBIF_RESERVED_96', - 97: 'A7XX_PERF_GBIF_RESERVED_97', - 98: 'A7XX_PERF_GBIF_RESERVED_98', - 99: 'A7XX_PERF_GBIF_RESERVED_99', - 100: 'A7XX_PERF_GBIF_RESERVED_100', - 101: 'A7XX_PERF_GBIF_RESERVED_101', - 102: 'A7XX_PERF_GBIF_RESERVED_102', - 103: 'A7XX_PERF_GBIF_RESERVED_103', - 104: 'A7XX_PERF_GBIF_RESERVED_104', - 105: 'A7XX_PERF_GBIF_RESERVED_105', - 106: 'A7XX_PERF_GBIF_RESERVED_106', - 107: 'A7XX_PERF_GBIF_RESERVED_107', - 108: 'A7XX_PERF_GBIF_RESERVED_108', - 109: 'A7XX_PERF_GBIF_RESERVED_109', - 110: 'A7XX_PERF_GBIF_RESERVED_110', - 111: 'A7XX_PERF_GBIF_RESERVED_111', - 112: 'A7XX_PERF_GBIF_RESERVED_112', - 113: 'A7XX_PERF_GBIF_RESERVED_113', - 114: 'A7XX_PERF_GBIF_RESERVED_114', - 115: 'A7XX_PERF_GBIF_RESERVED_115', - 116: 'A7XX_PERF_GBIF_RESERVED_116', - 117: 'A7XX_PERF_GBIF_RESERVED_117', - 118: 'A7XX_PERF_GBIF_RESERVED_118', - 119: 'A7XX_PERF_GBIF_RESERVED_119', - 120: 'A7XX_PERF_GBIF_RESERVED_120', - 121: 'A7XX_PERF_GBIF_RESERVED_121', - 122: 'A7XX_PERF_GBIF_RESERVED_122', - 123: 'A7XX_PERF_GBIF_RESERVED_123', - 124: 'A7XX_PERF_GBIF_RESERVED_124', - 125: 'A7XX_PERF_GBIF_RESERVED_125', - 126: 'A7XX_PERF_GBIF_RESERVED_126', - 127: 'A7XX_PERF_GBIF_RESERVED_127', - 128: 'A7XX_PERF_GBIF_RESERVED_128', - 129: 'A7XX_PERF_GBIF_RESERVED_129', - 130: 'A7XX_PERF_GBIF_RESERVED_130', - 131: 'A7XX_PERF_GBIF_RESERVED_131', - 132: 'A7XX_PERF_GBIF_RESERVED_132', - 133: 'A7XX_PERF_GBIF_RESERVED_133', - 134: 'A7XX_PERF_GBIF_RESERVED_134', - 135: 'A7XX_PERF_GBIF_RESERVED_135', - 136: 'A7XX_PERF_GBIF_RESERVED_136', - 137: 'A7XX_PERF_GBIF_RESERVED_137', - 138: 'A7XX_PERF_GBIF_RESERVED_138', - 139: 'A7XX_PERF_GBIF_RESERVED_139', - 140: 'A7XX_PERF_GBIF_RESERVED_140', - 141: 'A7XX_PERF_GBIF_RESERVED_141', - 142: 'A7XX_PERF_GBIF_RESERVED_142', - 143: 'A7XX_PERF_GBIF_RESERVED_143', - 144: 'A7XX_PERF_GBIF_RESERVED_144', - 145: 'A7XX_PERF_GBIF_RESERVED_145', - 146: 'A7XX_PERF_GBIF_RESERVED_146', - 147: 'A7XX_PERF_GBIF_RESERVED_147', - 148: 'A7XX_PERF_GBIF_RESERVED_148', - 149: 'A7XX_PERF_GBIF_RESERVED_149', - 150: 'A7XX_PERF_GBIF_RESERVED_150', - 151: 'A7XX_PERF_GBIF_RESERVED_151', - 152: 'A7XX_PERF_GBIF_RESERVED_152', - 153: 'A7XX_PERF_GBIF_RESERVED_153', - 154: 'A7XX_PERF_GBIF_RESERVED_154', - 155: 'A7XX_PERF_GBIF_RESERVED_155', - 156: 'A7XX_PERF_GBIF_RESERVED_156', - 157: 'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', - 158: 'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', - 159: 'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', - 160: 'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', - 161: 'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', -} -A7XX_PERF_GBIF_NEVER_COUNT = 0 -A7XX_PERF_GBIF_RESERVED_1 = 1 -A7XX_PERF_GBIF_RESERVED_2 = 2 -A7XX_PERF_GBIF_RESERVED_3 = 3 -A7XX_PERF_GBIF_RESERVED_4 = 4 -A7XX_PERF_GBIF_RESERVED_5 = 5 -A7XX_PERF_GBIF_RESERVED_6 = 6 -A7XX_PERF_GBIF_RESERVED_7 = 7 -A7XX_PERF_GBIF_RESERVED_8 = 8 -A7XX_PERF_GBIF_RESERVED_9 = 9 -A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = 10 -A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = 11 -A7XX_PERF_GBIF_RESERVED_12 = 12 -A7XX_PERF_GBIF_RESERVED_13 = 13 -A7XX_PERF_GBIF_RESERVED_14 = 14 -A7XX_PERF_GBIF_RESERVED_15 = 15 -A7XX_PERF_GBIF_RESERVED_16 = 16 -A7XX_PERF_GBIF_RESERVED_17 = 17 -A7XX_PERF_GBIF_RESERVED_18 = 18 -A7XX_PERF_GBIF_RESERVED_19 = 19 -A7XX_PERF_GBIF_RESERVED_20 = 20 -A7XX_PERF_GBIF_RESERVED_21 = 21 -A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = 22 -A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = 23 -A7XX_PERF_GBIF_RESERVED_24 = 24 -A7XX_PERF_GBIF_RESERVED_25 = 25 -A7XX_PERF_GBIF_RESERVED_26 = 26 -A7XX_PERF_GBIF_RESERVED_27 = 27 -A7XX_PERF_GBIF_RESERVED_28 = 28 -A7XX_PERF_GBIF_RESERVED_29 = 29 -A7XX_PERF_GBIF_RESERVED_30 = 30 -A7XX_PERF_GBIF_RESERVED_31 = 31 -A7XX_PERF_GBIF_RESERVED_32 = 32 -A7XX_PERF_GBIF_RESERVED_33 = 33 -A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = 34 -A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = 35 -A7XX_PERF_GBIF_RESERVED_36 = 36 -A7XX_PERF_GBIF_RESERVED_37 = 37 -A7XX_PERF_GBIF_RESERVED_38 = 38 -A7XX_PERF_GBIF_RESERVED_39 = 39 -A7XX_PERF_GBIF_RESERVED_40 = 40 -A7XX_PERF_GBIF_RESERVED_41 = 41 -A7XX_PERF_GBIF_RESERVED_42 = 42 -A7XX_PERF_GBIF_RESERVED_43 = 43 -A7XX_PERF_GBIF_RESERVED_44 = 44 -A7XX_PERF_GBIF_RESERVED_45 = 45 -A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = 46 -A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = 47 -A7XX_PERF_GBIF_RESERVED_48 = 48 -A7XX_PERF_GBIF_RESERVED_49 = 49 -A7XX_PERF_GBIF_RESERVED_50 = 50 -A7XX_PERF_GBIF_RESERVED_51 = 51 -A7XX_PERF_GBIF_RESERVED_52 = 52 -A7XX_PERF_GBIF_RESERVED_53 = 53 -A7XX_PERF_GBIF_RESERVED_54 = 54 -A7XX_PERF_GBIF_RESERVED_55 = 55 -A7XX_PERF_GBIF_RESERVED_56 = 56 -A7XX_PERF_GBIF_RESERVED_57 = 57 -A7XX_PERF_GBIF_RESERVED_58 = 58 -A7XX_PERF_GBIF_RESERVED_59 = 59 -A7XX_PERF_GBIF_RESERVED_60 = 60 -A7XX_PERF_GBIF_RESERVED_61 = 61 -A7XX_PERF_GBIF_RESERVED_62 = 62 -A7XX_PERF_GBIF_RESERVED_63 = 63 -A7XX_PERF_GBIF_RESERVED_64 = 64 -A7XX_PERF_GBIF_RESERVED_65 = 65 -A7XX_PERF_GBIF_RESERVED_66 = 66 -A7XX_PERF_GBIF_RESERVED_67 = 67 -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = 68 -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = 69 -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = 70 -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = 71 -A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = 72 -A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = 73 -A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = 74 -A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = 75 -A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = 76 -A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = 77 -A7XX_PERF_GBIF_RESERVED_78 = 78 -A7XX_PERF_GBIF_RESERVED_79 = 79 -A7XX_PERF_GBIF_RESERVED_80 = 80 -A7XX_PERF_GBIF_RESERVED_81 = 81 -A7XX_PERF_GBIF_RESERVED_82 = 82 -A7XX_PERF_GBIF_RESERVED_83 = 83 -A7XX_PERF_GBIF_RESERVED_84 = 84 -A7XX_PERF_GBIF_RESERVED_85 = 85 -A7XX_PERF_GBIF_RESERVED_86 = 86 -A7XX_PERF_GBIF_RESERVED_87 = 87 -A7XX_PERF_GBIF_RESERVED_88 = 88 -A7XX_PERF_GBIF_RESERVED_89 = 89 -A7XX_PERF_GBIF_RESERVED_90 = 90 -A7XX_PERF_GBIF_RESERVED_91 = 91 -A7XX_PERF_GBIF_RESERVED_92 = 92 -A7XX_PERF_GBIF_RESERVED_93 = 93 -A7XX_PERF_GBIF_RESERVED_94 = 94 -A7XX_PERF_GBIF_RESERVED_95 = 95 -A7XX_PERF_GBIF_RESERVED_96 = 96 -A7XX_PERF_GBIF_RESERVED_97 = 97 -A7XX_PERF_GBIF_RESERVED_98 = 98 -A7XX_PERF_GBIF_RESERVED_99 = 99 -A7XX_PERF_GBIF_RESERVED_100 = 100 -A7XX_PERF_GBIF_RESERVED_101 = 101 -A7XX_PERF_GBIF_RESERVED_102 = 102 -A7XX_PERF_GBIF_RESERVED_103 = 103 -A7XX_PERF_GBIF_RESERVED_104 = 104 -A7XX_PERF_GBIF_RESERVED_105 = 105 -A7XX_PERF_GBIF_RESERVED_106 = 106 -A7XX_PERF_GBIF_RESERVED_107 = 107 -A7XX_PERF_GBIF_RESERVED_108 = 108 -A7XX_PERF_GBIF_RESERVED_109 = 109 -A7XX_PERF_GBIF_RESERVED_110 = 110 -A7XX_PERF_GBIF_RESERVED_111 = 111 -A7XX_PERF_GBIF_RESERVED_112 = 112 -A7XX_PERF_GBIF_RESERVED_113 = 113 -A7XX_PERF_GBIF_RESERVED_114 = 114 -A7XX_PERF_GBIF_RESERVED_115 = 115 -A7XX_PERF_GBIF_RESERVED_116 = 116 -A7XX_PERF_GBIF_RESERVED_117 = 117 -A7XX_PERF_GBIF_RESERVED_118 = 118 -A7XX_PERF_GBIF_RESERVED_119 = 119 -A7XX_PERF_GBIF_RESERVED_120 = 120 -A7XX_PERF_GBIF_RESERVED_121 = 121 -A7XX_PERF_GBIF_RESERVED_122 = 122 -A7XX_PERF_GBIF_RESERVED_123 = 123 -A7XX_PERF_GBIF_RESERVED_124 = 124 -A7XX_PERF_GBIF_RESERVED_125 = 125 -A7XX_PERF_GBIF_RESERVED_126 = 126 -A7XX_PERF_GBIF_RESERVED_127 = 127 -A7XX_PERF_GBIF_RESERVED_128 = 128 -A7XX_PERF_GBIF_RESERVED_129 = 129 -A7XX_PERF_GBIF_RESERVED_130 = 130 -A7XX_PERF_GBIF_RESERVED_131 = 131 -A7XX_PERF_GBIF_RESERVED_132 = 132 -A7XX_PERF_GBIF_RESERVED_133 = 133 -A7XX_PERF_GBIF_RESERVED_134 = 134 -A7XX_PERF_GBIF_RESERVED_135 = 135 -A7XX_PERF_GBIF_RESERVED_136 = 136 -A7XX_PERF_GBIF_RESERVED_137 = 137 -A7XX_PERF_GBIF_RESERVED_138 = 138 -A7XX_PERF_GBIF_RESERVED_139 = 139 -A7XX_PERF_GBIF_RESERVED_140 = 140 -A7XX_PERF_GBIF_RESERVED_141 = 141 -A7XX_PERF_GBIF_RESERVED_142 = 142 -A7XX_PERF_GBIF_RESERVED_143 = 143 -A7XX_PERF_GBIF_RESERVED_144 = 144 -A7XX_PERF_GBIF_RESERVED_145 = 145 -A7XX_PERF_GBIF_RESERVED_146 = 146 -A7XX_PERF_GBIF_RESERVED_147 = 147 -A7XX_PERF_GBIF_RESERVED_148 = 148 -A7XX_PERF_GBIF_RESERVED_149 = 149 -A7XX_PERF_GBIF_RESERVED_150 = 150 -A7XX_PERF_GBIF_RESERVED_151 = 151 -A7XX_PERF_GBIF_RESERVED_152 = 152 -A7XX_PERF_GBIF_RESERVED_153 = 153 -A7XX_PERF_GBIF_RESERVED_154 = 154 -A7XX_PERF_GBIF_RESERVED_155 = 155 -A7XX_PERF_GBIF_RESERVED_156 = 156 -A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = 157 -A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = 158 -A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = 159 -A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = 160 -A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = 161 -a7xx_gbif_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ufc_perfcounter_select' -a7xx_ufc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_UFC_NEVER_COUNT', - 1: 'A7XX_PERF_UFC_BUSY_CYCLES', - 2: 'A7XX_PERF_UFC_READ_DATA_VBIF', - 3: 'A7XX_PERF_UFC_WRITE_DATA_VBIF', - 4: 'A7XX_PERF_UFC_READ_REQUEST_VBIF', - 5: 'A7XX_PERF_UFC_WRITE_REQUEST_VBIF', - 6: 'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', - 7: 'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', - 8: 'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', - 9: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', - 10: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', - 11: 'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', - 12: 'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', - 13: 'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', - 14: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', - 15: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', - 16: 'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', - 17: 'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', - 18: 'A7XX_PERF_UFC_MAIN_TP_RD_NRDY', - 19: 'A7XX_PERF_UFC_MAIN_TP_RD_RDY', - 20: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', - 21: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', - 22: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', - 23: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', - 24: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', - 25: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', - 26: 'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', - 27: 'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', - 28: 'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', - 29: 'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', - 30: 'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', - 31: 'A7XX_PERF_UFC_LOCK_STALLED_CYCLES', - 32: 'A7XX_PERF_UFC_MISS_LATENCY_CYCLES', - 33: 'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', - 34: 'A7XX_PERF_UFC_L1_CRE_REQUESTS', - 35: 'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', - 36: 'A7XX_PERF_UFC_L1_CRE_FILTER_HIT', - 37: 'A7XX_PERF_UFC_L1_CRE_FILTER_MISS', - 38: 'A7XX_PERF_UFC_L1_SP_REQUESTS', - 39: 'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', - 40: 'A7XX_PERF_UFC_L1_SP_FILTER_HIT', - 41: 'A7XX_PERF_UFC_L1_SP_FILTER_MISS', - 42: 'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', - 43: 'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', - 44: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', - 45: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', - 46: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', -} -A7XX_PERF_UFC_NEVER_COUNT = 0 -A7XX_PERF_UFC_BUSY_CYCLES = 1 -A7XX_PERF_UFC_READ_DATA_VBIF = 2 -A7XX_PERF_UFC_WRITE_DATA_VBIF = 3 -A7XX_PERF_UFC_READ_REQUEST_VBIF = 4 -A7XX_PERF_UFC_WRITE_REQUEST_VBIF = 5 -A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = 6 -A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = 7 -A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = 8 -A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = 9 -A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = 10 -A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = 11 -A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = 12 -A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = 13 -A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = 14 -A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = 15 -A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = 16 -A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = 17 -A7XX_PERF_UFC_MAIN_TP_RD_NRDY = 18 -A7XX_PERF_UFC_MAIN_TP_RD_RDY = 19 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = 20 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = 21 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = 22 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = 23 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = 24 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = 25 -A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = 26 -A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = 27 -A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = 28 -A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = 29 -A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = 30 -A7XX_PERF_UFC_LOCK_STALLED_CYCLES = 31 -A7XX_PERF_UFC_MISS_LATENCY_CYCLES = 32 -A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = 33 -A7XX_PERF_UFC_L1_CRE_REQUESTS = 34 -A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = 35 -A7XX_PERF_UFC_L1_CRE_FILTER_HIT = 36 -A7XX_PERF_UFC_L1_CRE_FILTER_MISS = 37 -A7XX_PERF_UFC_L1_SP_REQUESTS = 38 -A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = 39 -A7XX_PERF_UFC_L1_SP_FILTER_HIT = 40 -A7XX_PERF_UFC_L1_SP_FILTER_MISS = 41 -A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = 42 -A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = 43 -A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = 44 -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = 45 -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = 46 -a7xx_ufc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_sequenced_thread_dist' -a6xx_sequenced_thread_dist__enumvalues = { - 0: 'DIST_SCREEN_COORD', - 1: 'DIST_ALL_TO_RB0', -} -DIST_SCREEN_COORD = 0 -DIST_ALL_TO_RB0 = 1 -a6xx_sequenced_thread_dist = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_single_prim_mode' -a6xx_single_prim_mode__enumvalues = { - 0: 'NO_FLUSH', - 1: 'FLUSH_PER_OVERLAP_AND_OVERWRITE', - 3: 'FLUSH_PER_OVERLAP', -} -NO_FLUSH = 0 -FLUSH_PER_OVERLAP_AND_OVERWRITE = 1 -FLUSH_PER_OVERLAP = 3 -a6xx_single_prim_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_raster_mode' -a6xx_raster_mode__enumvalues = { - 0: 'TYPE_TILED', - 1: 'TYPE_WRITER', -} -TYPE_TILED = 0 -TYPE_WRITER = 1 -a6xx_raster_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_raster_direction' -a6xx_raster_direction__enumvalues = { - 0: 'LR_TB', - 1: 'RL_TB', - 2: 'LR_BT', - 3: 'RB_BT', -} -LR_TB = 0 -RL_TB = 1 -LR_BT = 2 -RB_BT = 3 -a6xx_raster_direction = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_render_mode' -a6xx_render_mode__enumvalues = { - 0: 'RENDERING_PASS', - 1: 'BINNING_PASS', -} -RENDERING_PASS = 0 -BINNING_PASS = 1 -a6xx_render_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_buffers_location' -a6xx_buffers_location__enumvalues = { - 0: 'BUFFERS_IN_GMEM', - 3: 'BUFFERS_IN_SYSMEM', -} -BUFFERS_IN_GMEM = 0 -BUFFERS_IN_SYSMEM = 3 -a6xx_buffers_location = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_lrz_dir_status' -a6xx_lrz_dir_status__enumvalues = { - 1: 'LRZ_DIR_LE', - 2: 'LRZ_DIR_GE', - 3: 'LRZ_DIR_INVALID', -} -LRZ_DIR_LE = 1 -LRZ_DIR_GE = 2 -LRZ_DIR_INVALID = 3 -a6xx_lrz_dir_status = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_fragcoord_sample_mode' -a6xx_fragcoord_sample_mode__enumvalues = { - 0: 'FRAGCOORD_CENTER', - 3: 'FRAGCOORD_SAMPLE', -} -FRAGCOORD_CENTER = 0 -FRAGCOORD_SAMPLE = 3 -a6xx_fragcoord_sample_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rotation' -a6xx_rotation__enumvalues = { - 0: 'ROTATE_0', - 1: 'ROTATE_90', - 2: 'ROTATE_180', - 3: 'ROTATE_270', - 4: 'ROTATE_HFLIP', - 5: 'ROTATE_VFLIP', -} -ROTATE_0 = 0 -ROTATE_90 = 1 -ROTATE_180 = 2 -ROTATE_270 = 3 -ROTATE_HFLIP = 4 -ROTATE_VFLIP = 5 -a6xx_rotation = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ccu_cache_size' -a6xx_ccu_cache_size__enumvalues = { - 0: 'CCU_CACHE_SIZE_FULL', - 1: 'CCU_CACHE_SIZE_HALF', - 2: 'CCU_CACHE_SIZE_QUARTER', - 3: 'CCU_CACHE_SIZE_EIGHTH', -} -CCU_CACHE_SIZE_FULL = 0 -CCU_CACHE_SIZE_HALF = 1 -CCU_CACHE_SIZE_QUARTER = 2 -CCU_CACHE_SIZE_EIGHTH = 3 -a6xx_ccu_cache_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_varying_interp_mode' -a6xx_varying_interp_mode__enumvalues = { - 0: 'INTERP_SMOOTH', - 1: 'INTERP_FLAT', - 2: 'INTERP_ZERO', - 3: 'INTERP_ONE', -} -INTERP_SMOOTH = 0 -INTERP_FLAT = 1 -INTERP_ZERO = 2 -INTERP_ONE = 3 -a6xx_varying_interp_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_varying_ps_repl_mode' -a6xx_varying_ps_repl_mode__enumvalues = { - 0: 'PS_REPL_NONE', - 1: 'PS_REPL_S', - 2: 'PS_REPL_T', - 3: 'PS_REPL_ONE_MINUS_T', -} -PS_REPL_NONE = 0 -PS_REPL_S = 1 -PS_REPL_T = 2 -PS_REPL_ONE_MINUS_T = 3 -a6xx_varying_ps_repl_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_threadsize' -a6xx_threadsize__enumvalues = { - 0: 'THREAD64', - 1: 'THREAD128', -} -THREAD64 = 0 -THREAD128 = 1 -a6xx_threadsize = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_bindless_descriptor_size' -a6xx_bindless_descriptor_size__enumvalues = { - 1: 'BINDLESS_DESCRIPTOR_16B', - 3: 'BINDLESS_DESCRIPTOR_64B', -} -BINDLESS_DESCRIPTOR_16B = 1 -BINDLESS_DESCRIPTOR_64B = 3 -a6xx_bindless_descriptor_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_isam_mode' -a6xx_isam_mode__enumvalues = { - 1: 'ISAMMODE_CL', - 2: 'ISAMMODE_GL', -} -ISAMMODE_CL = 1 -ISAMMODE_GL = 2 -a6xx_isam_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cs_yalign' -a7xx_cs_yalign__enumvalues = { - 8: 'CS_YALIGN_1', - 4: 'CS_YALIGN_2', - 2: 'CS_YALIGN_4', - 1: 'CS_YALIGN_8', -} -CS_YALIGN_1 = 8 -CS_YALIGN_2 = 4 -CS_YALIGN_4 = 2 -CS_YALIGN_8 = 1 -a7xx_cs_yalign = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_filter' -a6xx_tex_filter__enumvalues = { - 0: 'A6XX_TEX_NEAREST', - 1: 'A6XX_TEX_LINEAR', - 2: 'A6XX_TEX_ANISO', - 3: 'A6XX_TEX_CUBIC', -} -A6XX_TEX_NEAREST = 0 -A6XX_TEX_LINEAR = 1 -A6XX_TEX_ANISO = 2 -A6XX_TEX_CUBIC = 3 -a6xx_tex_filter = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_clamp' -a6xx_tex_clamp__enumvalues = { - 0: 'A6XX_TEX_REPEAT', - 1: 'A6XX_TEX_CLAMP_TO_EDGE', - 2: 'A6XX_TEX_MIRROR_REPEAT', - 3: 'A6XX_TEX_CLAMP_TO_BORDER', - 4: 'A6XX_TEX_MIRROR_CLAMP', -} -A6XX_TEX_REPEAT = 0 -A6XX_TEX_CLAMP_TO_EDGE = 1 -A6XX_TEX_MIRROR_REPEAT = 2 -A6XX_TEX_CLAMP_TO_BORDER = 3 -A6XX_TEX_MIRROR_CLAMP = 4 -a6xx_tex_clamp = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_aniso' -a6xx_tex_aniso__enumvalues = { - 0: 'A6XX_TEX_ANISO_1', - 1: 'A6XX_TEX_ANISO_2', - 2: 'A6XX_TEX_ANISO_4', - 3: 'A6XX_TEX_ANISO_8', - 4: 'A6XX_TEX_ANISO_16', -} -A6XX_TEX_ANISO_1 = 0 -A6XX_TEX_ANISO_2 = 1 -A6XX_TEX_ANISO_4 = 2 -A6XX_TEX_ANISO_8 = 3 -A6XX_TEX_ANISO_16 = 4 -a6xx_tex_aniso = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_reduction_mode' -a6xx_reduction_mode__enumvalues = { - 0: 'A6XX_REDUCTION_MODE_AVERAGE', - 1: 'A6XX_REDUCTION_MODE_MIN', - 2: 'A6XX_REDUCTION_MODE_MAX', -} -A6XX_REDUCTION_MODE_AVERAGE = 0 -A6XX_REDUCTION_MODE_MIN = 1 -A6XX_REDUCTION_MODE_MAX = 2 -a6xx_reduction_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_swiz' -a6xx_tex_swiz__enumvalues = { - 0: 'A6XX_TEX_X', - 1: 'A6XX_TEX_Y', - 2: 'A6XX_TEX_Z', - 3: 'A6XX_TEX_W', - 4: 'A6XX_TEX_ZERO', - 5: 'A6XX_TEX_ONE', -} -A6XX_TEX_X = 0 -A6XX_TEX_Y = 1 -A6XX_TEX_Z = 2 -A6XX_TEX_W = 3 -A6XX_TEX_ZERO = 4 -A6XX_TEX_ONE = 5 -a6xx_tex_swiz = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_type' -a6xx_tex_type__enumvalues = { - 0: 'A6XX_TEX_1D', - 1: 'A6XX_TEX_2D', - 2: 'A6XX_TEX_CUBE', - 3: 'A6XX_TEX_3D', - 4: 'A6XX_TEX_BUFFER', -} -A6XX_TEX_1D = 0 -A6XX_TEX_2D = 1 -A6XX_TEX_CUBE = 2 -A6XX_TEX_3D = 3 -A6XX_TEX_BUFFER = 4 -a6xx_tex_type = ctypes.c_uint32 # enum -__all__ = \ - ['A2XX', 'A3XX', 'A4XX', 'A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE', - 'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE', - 'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK', - 'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT', 'A5XX', - 'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK', - 'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT', - 'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK', - 'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT', 'A6XX', - 'A6XX_CP_2D_EVENT_END_STATE_ID__MASK', - 'A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT', - 'A6XX_CP_2D_EVENT_START_STATE_ID__MASK', - 'A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT', - 'A6XX_CP_APRIV_CNTL_CDREAD', 'A6XX_CP_APRIV_CNTL_CDWRITE', - 'A6XX_CP_APRIV_CNTL_ICACHE', 'A6XX_CP_APRIV_CNTL_RBFETCH', - 'A6XX_CP_APRIV_CNTL_RBPRIVLEVEL', 'A6XX_CP_APRIV_CNTL_RBRPWB', - 'A6XX_CP_CP2GMU_STATUS_IFPC', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT', - 'A6XX_CP_EVENT_END_STATE_ID__MASK', - 'A6XX_CP_EVENT_END_STATE_ID__SHIFT', - 'A6XX_CP_EVENT_START_STATE_ID__MASK', - 'A6XX_CP_EVENT_START_STATE_ID__SHIFT', 'A6XX_CP_INT_CP_AHB_ERROR', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR_BV', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC', - 'A6XX_CP_INT_CP_OPCODE_ERROR', 'A6XX_CP_INT_CP_OPCODE_ERROR_BV', - 'A6XX_CP_INT_CP_OPCODE_ERROR_LPAC', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC', - 'A6XX_CP_INT_CP_UCODE_ERROR', 'A6XX_CP_INT_CP_UCODE_ERROR_BV', - 'A6XX_CP_INT_CP_UCODE_ERROR_LPAC', - 'A6XX_CP_INT_CP_VSD_PARITY_ERROR', - 'A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN', - 'A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN', - 'A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE', - 'A6XX_CP_PROTECT_REG_BASE_ADDR__MASK', - 'A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT', - 'A6XX_CP_PROTECT_REG_MASK_LEN__MASK', - 'A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT', 'A6XX_CP_PROTECT_REG_READ', - 'A6XX_CP_REG_TEST_0_BIT__MASK', 'A6XX_CP_REG_TEST_0_BIT__SHIFT', - 'A6XX_CP_REG_TEST_0_PRED_BIT__MASK', - 'A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT', - 'A6XX_CP_REG_TEST_0_PRED_UPDATE', 'A6XX_CP_REG_TEST_0_REG__MASK', - 'A6XX_CP_REG_TEST_0_REG__SHIFT', - 'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK', - 'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT', - 'A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME', - 'A6XX_CP_REG_TEST_0_SOURCE__MASK', - 'A6XX_CP_REG_TEST_0_SOURCE__SHIFT', - 'A6XX_CP_ROQ_AVAIL_IB1_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_IB2_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_MRB_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_RB_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_SDS_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_VSD_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT', - 'A6XX_CP_ROQ_IB1_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_IB1_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_IB2_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_IB2_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_MRB_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_MRB_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_RB_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_RB_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_SDS_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_SDS_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT', - 'A6XX_CP_ROQ_VSD_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_VSD_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT', - 'A6XX_CP_SET_MARKER_0_MARKER__MASK', - 'A6XX_CP_SET_MARKER_0_MARKER__SHIFT', - 'A6XX_CP_SET_MARKER_0_MODE__MASK', - 'A6XX_CP_SET_MARKER_0_MODE__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK', - 'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__1_LO__MASK', - 'A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__2_HI__MASK', - 'A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT', - 'A6XX_DBGBUS_A2D', 'A6XX_DBGBUS_CCUFCHE', 'A6XX_DBGBUS_CCU_0', - 'A6XX_DBGBUS_CCU_1', 'A6XX_DBGBUS_CCU_2', 'A6XX_DBGBUS_COM', - 'A6XX_DBGBUS_CP', 'A6XX_DBGBUS_CX', 'A6XX_DBGBUS_DBGC', - 'A6XX_DBGBUS_DCS', 'A6XX_DBGBUS_DPM', 'A6XX_DBGBUS_GBIF_GX', - 'A6XX_DBGBUS_GMU_CX', 'A6XX_DBGBUS_GMU_GX', 'A6XX_DBGBUS_GPC', - 'A6XX_DBGBUS_HLSQ', 'A6XX_DBGBUS_HLSQ_SPTP', 'A6XX_DBGBUS_LARC', - 'A6XX_DBGBUS_LRZ', 'A6XX_DBGBUS_PC', 'A6XX_DBGBUS_RAS', - 'A6XX_DBGBUS_RBBM', 'A6XX_DBGBUS_RBP', 'A6XX_DBGBUS_RB_0', - 'A6XX_DBGBUS_RB_1', 'A6XX_DBGBUS_RB_2', 'A6XX_DBGBUS_SPTP_0', - 'A6XX_DBGBUS_SPTP_1', 'A6XX_DBGBUS_SPTP_2', 'A6XX_DBGBUS_SPTP_3', - 'A6XX_DBGBUS_SPTP_4', 'A6XX_DBGBUS_SPTP_5', 'A6XX_DBGBUS_SP_0', - 'A6XX_DBGBUS_SP_1', 'A6XX_DBGBUS_SP_2', 'A6XX_DBGBUS_TESS', - 'A6XX_DBGBUS_TPFCHE', 'A6XX_DBGBUS_TPL1_0', 'A6XX_DBGBUS_TPL1_1', - 'A6XX_DBGBUS_TPL1_2', 'A6XX_DBGBUS_TPL1_3', 'A6XX_DBGBUS_TPL1_4', - 'A6XX_DBGBUS_TPL1_5', 'A6XX_DBGBUS_TSE', 'A6XX_DBGBUS_UCHE', - 'A6XX_DBGBUS_UCHE_WRAPPER', 'A6XX_DBGBUS_VBIF', - 'A6XX_DBGBUS_VFDP', 'A6XX_DBGBUS_VFD_0', 'A6XX_DBGBUS_VFD_1', - 'A6XX_DBGBUS_VFD_2', 'A6XX_DBGBUS_VFD_3', 'A6XX_DBGBUS_VFD_4', - 'A6XX_DBGBUS_VFD_5', 'A6XX_DBGBUS_VPC', 'A6XX_DBGBUS_VSC', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT', - 'A6XX_EARLY_LRZ_LATE_Z', 'A6XX_EARLY_Z', - 'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_D24S8', - 'A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN', - 'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_SCISSOR', - 'A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK30', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT', - 'A6XX_GRAS_2D_DST_BR_X__MASK', 'A6XX_GRAS_2D_DST_BR_X__SHIFT', - 'A6XX_GRAS_2D_DST_BR_Y__MASK', 'A6XX_GRAS_2D_DST_BR_Y__SHIFT', - 'A6XX_GRAS_2D_DST_TL_X__MASK', 'A6XX_GRAS_2D_DST_TL_X__SHIFT', - 'A6XX_GRAS_2D_DST_TL_Y__MASK', 'A6XX_GRAS_2D_DST_TL_Y__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT', - 'A6XX_GRAS_2D_SRC_BR_X__MASK', 'A6XX_GRAS_2D_SRC_BR_X__SHIFT', - 'A6XX_GRAS_2D_SRC_BR_Y__MASK', 'A6XX_GRAS_2D_SRC_BR_Y__SHIFT', - 'A6XX_GRAS_2D_SRC_TL_X__MASK', 'A6XX_GRAS_2D_SRC_TL_X__SHIFT', - 'A6XX_GRAS_2D_SRC_TL_Y__MASK', 'A6XX_GRAS_2D_SRC_TL_Y__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BINH__MASK', - 'A6XX_GRAS_BIN_CONTROL_BINH__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BINW__MASK', - 'A6XX_GRAS_BIN_CONTROL_BINW__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK', - 'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK', - 'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_UNK27', 'A6XX_GRAS_CL_CNTL_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE', - 'A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE', - 'A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE', - 'A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z', - 'A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT', - 'A6XX_GRAS_CL_VPORT_XOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_XSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_XSCALE__SHIFT', - 'A6XX_GRAS_CL_VPORT_YOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_YSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_YSCALE__SHIFT', - 'A6XX_GRAS_CL_VPORT_ZOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_ZSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT', - 'A6XX_GRAS_CL_Z_CLAMP_MAX__MASK', - 'A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT', - 'A6XX_GRAS_CL_Z_CLAMP_MIN__MASK', - 'A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT', - 'A6XX_GRAS_CNTL_COORD_MASK__MASK', - 'A6XX_GRAS_CNTL_COORD_MASK__SHIFT', - 'A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID', - 'A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL', - 'A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE', - 'A6XX_GRAS_CNTL_IJ_PERSP_CENTROID', - 'A6XX_GRAS_CNTL_IJ_PERSP_PIXEL', 'A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE', - 'A6XX_GRAS_CNTL_UNK10', 'A6XX_GRAS_CNTL_UNK11', - 'A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS', - 'A6XX_GRAS_DBG_ECO_CNTL_UNK7', - 'A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_DIR_WRITE', 'A6XX_GRAS_LRZ_CNTL_DIR__MASK', - 'A6XX_GRAS_LRZ_CNTL_DIR__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR', - 'A6XX_GRAS_LRZ_CNTL_ENABLE', 'A6XX_GRAS_LRZ_CNTL_FC_ENABLE', - 'A6XX_GRAS_LRZ_CNTL_GREATER', 'A6XX_GRAS_LRZ_CNTL_LRZ_WRITE', - 'A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE', - 'A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK', - 'A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT', - 'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK', - 'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID', - 'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_GRAS_RAS_MSAA_CNTL_UNK2', 'A6XX_GRAS_RAS_MSAA_CNTL_UNK3', - 'A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE', - 'A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_GRAS_SAMPLE_CONFIG_UNK0', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK', - 'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT', - 'A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN', - 'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK', - 'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT', - 'A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK', - 'A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT', - 'A6XX_GRAS_SC_CNTL_ROTATION__MASK', - 'A6XX_GRAS_SC_CNTL_ROTATION__SHIFT', - 'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK', - 'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT', - 'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK', - 'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT', - 'A6XX_GRAS_SC_CNTL_UNK9', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SU_CNTL_CULL_BACK', 'A6XX_GRAS_SU_CNTL_CULL_FRONT', - 'A6XX_GRAS_SU_CNTL_FRONT_CW', - 'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK', - 'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT', - 'A6XX_GRAS_SU_CNTL_LINE_MODE__MASK', - 'A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT', - 'A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE', - 'A6XX_GRAS_SU_CNTL_POLY_OFFSET', - 'A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR', - 'A6XX_GRAS_SU_CNTL_UNK12', 'A6XX_GRAS_SU_CNTL_UNK15__MASK', - 'A6XX_GRAS_SU_CNTL_UNK15__SHIFT', 'A6XX_GRAS_SU_CNTL_UNK20__MASK', - 'A6XX_GRAS_SU_CNTL_UNK20__SHIFT', - 'A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3', - 'A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE', - 'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK', - 'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT', - 'A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN', - 'A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0', - 'A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK', - 'A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT', - 'A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK', - 'A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT', - 'A6XX_GRAS_SU_POINT_SIZE__MASK', 'A6XX_GRAS_SU_POINT_SIZE__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT', - 'A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE', - 'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK', - 'A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT', - 'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_BACKEND_META', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_HLSQ_CHUNK_CPS_RAM', 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG', - 'A6XX_HLSQ_CHUNK_CVS_RAM', 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG', - 'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK', - 'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK', - 'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK', - 'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT', - 'A6XX_HLSQ_CPS_MISC_RAM', 'A6XX_HLSQ_CPS_MISC_RAM_TAG', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT', - 'A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_CS_CNTL_ENABLED', - 'A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK', - 'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK', - 'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK', - 'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK', - 'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK', - 'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK', - 'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6', 'A6XX_HLSQ_CVS_MISC_RAM', - 'A6XX_HLSQ_CVS_MISC_RAM_TAG', 'A6XX_HLSQ_DATAPATH_META', - 'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_DS_CNTL_ENABLED', - 'A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_EVENT_CMD_EVENT__MASK', - 'A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT', - 'A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A6XX_HLSQ_FRONTEND_META', - 'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK', - 'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT', - 'A6XX_HLSQ_FS_CNTL_0_UNK2__MASK', - 'A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A6XX_HLSQ_FS_CNTL_0_VARYINGS', - 'A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_FS_CNTL_ENABLED', - 'A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_GFX_CPS_CONST_RAM', 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 'A6XX_HLSQ_GFX_CVS_CONST_RAM', 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 'A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_GS_CNTL_ENABLED', - 'A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_HS_CNTL_ENABLED', - 'A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 'A6XX_HLSQ_INDIRECT_META', 'A6XX_HLSQ_INST_RAM', - 'A6XX_HLSQ_INST_RAM_1', 'A6XX_HLSQ_INST_RAM_TAG', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_IBO', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_DS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_FS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST', - 'A6XX_HLSQ_INVALIDATE_CMD_GS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_HS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A6XX_HLSQ_PWR_REST_RAM', - 'A6XX_HLSQ_PWR_REST_TAG', 'A6XX_HLSQ_SHARED_CONSTS_ENABLE', - 'A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_VS_CNTL_ENABLED', - 'A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS', 'A6XX_INVALID_ZTEST', - 'A6XX_LATE_Z', 'A6XX_PC_2D_EVENT_CMD_EVENT__MASK', - 'A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT', - 'A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK', - 'A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN', - 'A6XX_PC_DISPATCH_CMD_STATE_ID__MASK', - 'A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DRAW_CMD_STATE_ID__MASK', - 'A6XX_PC_DRAW_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_GS_ENABLE', - 'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK', - 'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK', - 'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK', - 'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK', - 'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_TESS_ENABLE', - 'A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK', - 'A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_LAYER', 'A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_DS_OUT_CNTL_PSIZE', 'A6XX_PC_DS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_VIEW', 'A6XX_PC_EVENT_CMD_EVENT__MASK', - 'A6XX_PC_EVENT_CMD_EVENT__SHIFT', - 'A6XX_PC_EVENT_CMD_STATE_ID__MASK', - 'A6XX_PC_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_LAYER', 'A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_GS_OUT_CNTL_PSIZE', 'A6XX_PC_GS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_VIEW', 'A6XX_PC_HS_INPUT_SIZE_SIZE__MASK', - 'A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT', - 'A6XX_PC_HS_INPUT_SIZE_UNK13', - 'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_HS_OUT_CNTL_LAYER', 'A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_HS_OUT_CNTL_PSIZE', 'A6XX_PC_HS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_HS_OUT_CNTL_VIEW', - 'A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A6XX_PC_MULTIVIEW_CNTL_ENABLE', - 'A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK', - 'A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A6XX_PC_POLYGON_MODE_MODE__MASK', - 'A6XX_PC_POLYGON_MODE_MODE__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING', - 'A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART', - 'A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST', - 'A6XX_PC_PRIMITIVE_CNTL_0_UNK3', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN', - 'A6XX_PC_PRIMITIVE_CNTL_5_UNK18', - 'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_PS_CNTL_PRIMITIVEIDEN', 'A6XX_PC_RASTER_CNTL_DISCARD', - 'A6XX_PC_RASTER_CNTL_STREAM__MASK', - 'A6XX_PC_RASTER_CNTL_STREAM__SHIFT', - 'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK', - 'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT', - 'A6XX_PC_TESS_CNTL_OUTPUT__MASK', - 'A6XX_PC_TESS_CNTL_OUTPUT__SHIFT', - 'A6XX_PC_TESS_CNTL_SPACING__MASK', - 'A6XX_PC_TESS_CNTL_SPACING__SHIFT', - 'A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE', - 'A6XX_PC_VSTREAM_CONTROL_UNK0__MASK', - 'A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT', - 'A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK', - 'A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT', - 'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK', - 'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_LAYER', 'A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_VS_OUT_CNTL_PSIZE', 'A6XX_PC_VS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_VIEW', 'A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR', - 'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS', - 'A6XX_RBBM_INT_0_MASK_CP_HW_ERROR', 'A6XX_RBBM_INT_0_MASK_CP_IB1', - 'A6XX_RBBM_INT_0_MASK_CP_IB2', - 'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0', - 'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1', - 'A6XX_RBBM_INT_0_MASK_CP_RB', - 'A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS', - 'A6XX_RBBM_INT_0_MASK_CP_SW', - 'A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS', - 'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0', - 'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1', - 'A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ', - 'A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG', - 'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT', - 'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC', - 'A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW', - 'A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW', - 'A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR', - 'A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE', - 'A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT', - 'A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION', - 'A6XX_RBBM_INT_0_MASK_TSBWRITEERROR', - 'A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS', - 'A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR', - 'A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT', - 'A6XX_RBBM_STATUS_A2D_BUSY', 'A6XX_RBBM_STATUS_CCU_BUSY', - 'A6XX_RBBM_STATUS_COM_DCOM_BUSY', - 'A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER', - 'A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER', - 'A6XX_RBBM_STATUS_CP_BUSY', 'A6XX_RBBM_STATUS_GFX_DBGC_BUSY', - 'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB', - 'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP', - 'A6XX_RBBM_STATUS_HLSQ_BUSY', 'A6XX_RBBM_STATUS_LRZ_BUSY', - 'A6XX_RBBM_STATUS_PC_DCALL_BUSY', 'A6XX_RBBM_STATUS_PC_VSD_BUSY', - 'A6XX_RBBM_STATUS_RAS_BUSY', 'A6XX_RBBM_STATUS_RB_BUSY', - 'A6XX_RBBM_STATUS_SP_BUSY', 'A6XX_RBBM_STATUS_TESS_BUSY', - 'A6XX_RBBM_STATUS_TPL1_BUSY', 'A6XX_RBBM_STATUS_TSE_BUSY', - 'A6XX_RBBM_STATUS_UCHE_BUSY', 'A6XX_RBBM_STATUS_VBIF_BUSY', - 'A6XX_RBBM_STATUS_VFD_BUSY', 'A6XX_RBBM_STATUS_VPC_BUSY', - 'A6XX_RBBM_STATUS_VSC_BUSY', - 'A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE', - 'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK', - 'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_D24S8', 'A6XX_RB_2D_BLIT_CNTL_IFMT__MASK', - 'A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_MASK__MASK', - 'A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN', - 'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK', - 'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK', - 'A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_SCISSOR', - 'A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR', - 'A6XX_RB_2D_BLIT_CNTL_UNK17__MASK', - 'A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT', 'A6XX_RB_2D_BLIT_CNTL_UNK30', - 'A6XX_RB_2D_BLIT_CNTL_UNK4__MASK', - 'A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT', - 'A6XX_RB_2D_DST_FLAGS_PITCH__MASK', - 'A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT', - 'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK', - 'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT', - 'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_2D_DST_INFO_FILTER', 'A6XX_RB_2D_DST_INFO_FLAGS', - 'A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE', - 'A6XX_RB_2D_DST_INFO_SAMPLES__MASK', - 'A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT', 'A6XX_RB_2D_DST_INFO_SRGB', - 'A6XX_RB_2D_DST_INFO_TILE_MODE__MASK', - 'A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT', - 'A6XX_RB_2D_DST_INFO_UNK17', 'A6XX_RB_2D_DST_INFO_UNK19', - 'A6XX_RB_2D_DST_INFO_UNK20', 'A6XX_RB_2D_DST_INFO_UNK21', - 'A6XX_RB_2D_DST_INFO_UNK22', 'A6XX_RB_2D_DST_INFO_UNK23__MASK', - 'A6XX_RB_2D_DST_INFO_UNK23__SHIFT', 'A6XX_RB_2D_DST_INFO_UNK28', - 'A6XX_RB_2D_DST_PITCH__MASK', 'A6XX_RB_2D_DST_PITCH__SHIFT', - 'A6XX_RB_2D_DST_PLANE_PITCH__MASK', - 'A6XX_RB_2D_DST_PLANE_PITCH__SHIFT', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT', - 'A6XX_RB_BIN_CONTROL2_BINH__MASK', - 'A6XX_RB_BIN_CONTROL2_BINH__SHIFT', - 'A6XX_RB_BIN_CONTROL2_BINW__MASK', - 'A6XX_RB_BIN_CONTROL2_BINW__SHIFT', - 'A6XX_RB_BIN_CONTROL_BINH__MASK', - 'A6XX_RB_BIN_CONTROL_BINH__SHIFT', - 'A6XX_RB_BIN_CONTROL_BINW__MASK', - 'A6XX_RB_BIN_CONTROL_BINW__SHIFT', - 'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK', - 'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT', - 'A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK', - 'A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A6XX_RB_BLEND_ALPHA_F32__MASK', 'A6XX_RB_BLEND_ALPHA_F32__SHIFT', - 'A6XX_RB_BLEND_BLUE_F32__MASK', 'A6XX_RB_BLEND_BLUE_F32__SHIFT', - 'A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE', - 'A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE', - 'A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE', - 'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK', - 'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT', - 'A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND', - 'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK', - 'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT', - 'A6XX_RB_BLEND_GREEN_F32__MASK', 'A6XX_RB_BLEND_GREEN_F32__SHIFT', - 'A6XX_RB_BLEND_RED_F32__MASK', 'A6XX_RB_BLEND_RED_F32__SHIFT', - 'A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK', - 'A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_FLAGS', - 'A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK', - 'A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK', - 'A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_UNK15', 'A6XX_RB_BLIT_DST_PITCH__MASK', - 'A6XX_RB_BLIT_DST_PITCH__SHIFT', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT', - 'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_BLIT_INFO_BUFFER_ID__MASK', - 'A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT', - 'A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK', - 'A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT', 'A6XX_RB_BLIT_INFO_DEPTH', - 'A6XX_RB_BLIT_INFO_GMEM', 'A6XX_RB_BLIT_INFO_LAST__MASK', - 'A6XX_RB_BLIT_INFO_LAST__SHIFT', 'A6XX_RB_BLIT_INFO_SAMPLE_0', - 'A6XX_RB_BLIT_INFO_UNK0', 'A6XX_RB_BLIT_SCISSOR_BR_X__MASK', - 'A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_BR_Y__MASK', - 'A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_TL_X__MASK', - 'A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_TL_Y__MASK', - 'A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT', - 'A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE', - 'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT', - 'A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE', - 'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK', - 'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_PITCH__MASK', - 'A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT', - 'A6XX_RB_DEPTH_CNTL_ZFUNC__MASK', - 'A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT', - 'A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT', - 'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK', - 'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT', - 'A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT', - 'A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z', - 'A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK', - 'A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT', 'A6XX_RB_LRZ_CNTL_ENABLE', - 'A6XX_RB_MRT_ARRAY_PITCH__MASK', 'A6XX_RB_MRT_ARRAY_PITCH__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_UNK10', 'A6XX_RB_MRT_CONTROL_BLEND', - 'A6XX_RB_MRT_CONTROL_BLEND2', - 'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK', - 'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT', - 'A6XX_RB_MRT_CONTROL_ROP_CODE__MASK', - 'A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT', - 'A6XX_RB_MRT_CONTROL_ROP_ENABLE', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_MRT_PITCH__MASK', 'A6XX_RB_MRT_PITCH__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_AMSBC', - 'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK', - 'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH', - 'A6XX_RB_NC_MODE_CNTL_MODE', - 'A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR', - 'A6XX_RB_NC_MODE_CNTL_UNK12__MASK', - 'A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK', - 'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT', - 'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_RAS_MSAA_CNTL_UNK2', 'A6XX_RB_RAS_MSAA_CNTL_UNK3', - 'A6XX_RB_RENDER_CNTL_BINNING', - 'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK', - 'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT', - 'A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN', - 'A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN', - 'A6XX_RB_RENDER_CNTL_FLAG_DEPTH', - 'A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK', - 'A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT', - 'A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN', - 'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK', - 'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT', - 'A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK', - 'A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT', - 'A6XX_RB_RENDER_CNTL_UNK8__MASK', - 'A6XX_RB_RENDER_CNTL_UNK8__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT0__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT1__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT2__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT3__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT4__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT5__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT6__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT7__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT', - 'A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK', - 'A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE', - 'A6XX_RB_RENDER_CONTROL0_UNK10', - 'A6XX_RB_RENDER_CONTROL1_CENTERRHW', - 'A6XX_RB_RENDER_CONTROL1_FACENESS', - 'A6XX_RB_RENDER_CONTROL1_FOVEATION', - 'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK', - 'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT', - 'A6XX_RB_RENDER_CONTROL1_LINELENGTHEN', - 'A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE', - 'A6XX_RB_RENDER_CONTROL1_SAMPLEID', - 'A6XX_RB_RENDER_CONTROL1_SAMPLEMASK', - 'A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE', - 'A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_RB_SAMPLE_CONFIG_UNK0', 'A6XX_RB_SAMPLE_COUNT_CONTROL_COPY', - 'A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT0', 'A6XX_RB_SRGB_CNTL_SRGB_MRT1', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT2', 'A6XX_RB_SRGB_CNTL_SRGB_MRT3', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT4', 'A6XX_RB_SRGB_CNTL_SRGB_MRT5', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT6', 'A6XX_RB_SRGB_CNTL_SRGB_MRT7', - 'A6XX_RB_STENCILMASK_BFMASK__MASK', - 'A6XX_RB_STENCILMASK_BFMASK__SHIFT', - 'A6XX_RB_STENCILMASK_MASK__MASK', - 'A6XX_RB_STENCILMASK_MASK__SHIFT', - 'A6XX_RB_STENCILREF_BFREF__MASK', - 'A6XX_RB_STENCILREF_BFREF__SHIFT', 'A6XX_RB_STENCILREF_REF__MASK', - 'A6XX_RB_STENCILREF_REF__SHIFT', - 'A6XX_RB_STENCILWRMASK_BFWRMASK__MASK', - 'A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT', - 'A6XX_RB_STENCILWRMASK_WRMASK__MASK', - 'A6XX_RB_STENCILWRMASK_WRMASK__SHIFT', - 'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_RB_STENCIL_BUFFER_PITCH__MASK', - 'A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FAIL__MASK', - 'A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FUNC__MASK', - 'A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_READ', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZPASS__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT', - 'A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL', - 'A6XX_RB_STENCIL_INFO_UNK1', 'A6XX_RB_UNKNOWN_88D0_UNK0__MASK', - 'A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT', - 'A6XX_RB_UNKNOWN_88D0_UNK16__MASK', - 'A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_WINDOW_OFFSET2_X__MASK', - 'A6XX_RB_WINDOW_OFFSET2_X__SHIFT', - 'A6XX_RB_WINDOW_OFFSET2_Y__MASK', - 'A6XX_RB_WINDOW_OFFSET2_Y__SHIFT', - 'A6XX_RB_WINDOW_OFFSET_X__MASK', 'A6XX_RB_WINDOW_OFFSET_X__SHIFT', - 'A6XX_RB_WINDOW_OFFSET_Y__MASK', 'A6XX_RB_WINDOW_OFFSET_Y__SHIFT', - 'A6XX_RB_Z_BOUNDS_MAX__MASK', 'A6XX_RB_Z_BOUNDS_MAX__SHIFT', - 'A6XX_RB_Z_BOUNDS_MIN__MASK', 'A6XX_RB_Z_BOUNDS_MIN__SHIFT', - 'A6XX_RB_Z_CLAMP_MAX__MASK', 'A6XX_RB_Z_CLAMP_MAX__SHIFT', - 'A6XX_RB_Z_CLAMP_MIN__MASK', 'A6XX_RB_Z_CLAMP_MIN__SHIFT', - 'A6XX_REDUCTION_MODE_AVERAGE', 'A6XX_REDUCTION_MODE_MAX', - 'A6XX_REDUCTION_MODE_MIN', - 'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK', - 'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT', - 'A6XX_SP_2D_DST_FORMAT_MASK__MASK', - 'A6XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A6XX_SP_2D_DST_FORMAT_NORM', - 'A6XX_SP_2D_DST_FORMAT_SINT', 'A6XX_SP_2D_DST_FORMAT_SRGB', - 'A6XX_SP_2D_DST_FORMAT_UINT', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE', - 'A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE', - 'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK', - 'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT', - 'A6XX_SP_BLEND_CNTL_UNK8', 'A6XX_SP_CB_BINDLESS_DATA', - 'A6XX_SP_CB_BINDLESS_TAG', 'A6XX_SP_CB_LEGACY_DATA', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK', - 'A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE', - 'A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR', - 'A6XX_SP_CS_CNTL_1_THREADSIZE__MASK', - 'A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT', - 'A6XX_SP_CS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_CS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_CS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_CS_CONFIG_BINDLESS_UBO', 'A6XX_SP_CS_CONFIG_ENABLED', - 'A6XX_SP_CS_CONFIG_NIBO__MASK', 'A6XX_SP_CS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_CS_CONFIG_NSAMP__MASK', 'A6XX_SP_CS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_CS_CONFIG_NTEX__MASK', 'A6XX_SP_CS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK', - 'A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_UNK13', 'A6XX_SP_CS_CTRL_REG0_UNK21', - 'A6XX_SP_CS_CTRL_REG0_UNK22', - 'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK', - 'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT', - 'A6XX_SP_CS_UNKNOWN_A9B1_UNK5', 'A6XX_SP_CS_UNKNOWN_A9B1_UNK6', - 'A6XX_SP_DS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_DS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_DS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_DS_CONFIG_BINDLESS_UBO', 'A6XX_SP_DS_CONFIG_ENABLED', - 'A6XX_SP_DS_CONFIG_NIBO__MASK', 'A6XX_SP_DS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_DS_CONFIG_NSAMP__MASK', 'A6XX_SP_DS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_DS_CONFIG_NTEX__MASK', 'A6XX_SP_DS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_UNK13', - 'A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_DS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_DS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_DS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_DS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_FLOAT_CNTL_F16_NO_INF', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A6XX_SP_FS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_FS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_FS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_FS_CONFIG_BINDLESS_UBO', 'A6XX_SP_FS_CONFIG_ENABLED', - 'A6XX_SP_FS_CONFIG_NIBO__MASK', 'A6XX_SP_FS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_FS_CONFIG_NSAMP__MASK', 'A6XX_SP_FS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_FS_CONFIG_NTEX__MASK', 'A6XX_SP_FS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_LODPIXMASK', - 'A6XX_SP_FS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_FS_CTRL_REG0_PIXLODENABLE', - 'A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK', - 'A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_UNK13', 'A6XX_SP_FS_CTRL_REG0_UNK21', - 'A6XX_SP_FS_CTRL_REG0_UNK24', 'A6XX_SP_FS_CTRL_REG0_UNK25', - 'A6XX_SP_FS_CTRL_REG0_UNK27', 'A6XX_SP_FS_CTRL_REG0_VARYING', - 'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK', - 'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT', - 'A6XX_SP_FS_MRT_REG_COLOR_SINT', 'A6XX_SP_FS_MRT_REG_COLOR_UINT', - 'A6XX_SP_FS_MRT_REG_UNK10', - 'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE', - 'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT', - 'A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION', - 'A6XX_SP_FS_OUTPUT_REG_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_BINDLESS', - 'A6XX_SP_FS_PREFETCH_CMD_CMD__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_DST__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_HALF', - 'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_SRC__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_UNK27', - 'A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD', - 'A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE', - 'A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT', - 'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT', - 'A6XX_SP_GS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_GS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_GS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_GS_CONFIG_BINDLESS_UBO', 'A6XX_SP_GS_CONFIG_ENABLED', - 'A6XX_SP_GS_CONFIG_NIBO__MASK', 'A6XX_SP_GS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_GS_CONFIG_NSAMP__MASK', 'A6XX_SP_GS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_GS_CONFIG_NTEX__MASK', 'A6XX_SP_GS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_UNK13', - 'A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_GS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_GS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_GS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_GS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_HS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_HS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_HS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_HS_CONFIG_BINDLESS_UBO', 'A6XX_SP_HS_CONFIG_ENABLED', - 'A6XX_SP_HS_CONFIG_NIBO__MASK', 'A6XX_SP_HS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_HS_CONFIG_NSAMP__MASK', 'A6XX_SP_HS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_HS_CONFIG_NTEX__MASK', 'A6XX_SP_HS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_UNK13', - 'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_INST_DATA', 'A6XX_SP_INST_TAG', 'A6XX_SP_LB_0_DATA', - 'A6XX_SP_LB_1_DATA', 'A6XX_SP_LB_2_DATA', 'A6XX_SP_LB_3_DATA', - 'A6XX_SP_LB_4_DATA', 'A6XX_SP_LB_5_DATA', 'A6XX_SP_LB_6_DATA', - 'A6XX_SP_LB_7_DATA', - 'A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE', - 'A6XX_SP_MODE_CONTROL_ISAMMODE__MASK', - 'A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT', - 'A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE', - 'A6XX_SP_PERFCTR_ENABLE_CS', 'A6XX_SP_PERFCTR_ENABLE_DS', - 'A6XX_SP_PERFCTR_ENABLE_FS', 'A6XX_SP_PERFCTR_ENABLE_GS', - 'A6XX_SP_PERFCTR_ENABLE_HS', 'A6XX_SP_PERFCTR_ENABLE_VS', - 'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_FILTER', 'A6XX_SP_PS_2D_SRC_INFO_FLAGS', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_SRGB', - 'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_UNK17', 'A6XX_SP_PS_2D_SRC_INFO_UNK19', - 'A6XX_SP_PS_2D_SRC_INFO_UNK20', 'A6XX_SP_PS_2D_SRC_INFO_UNK21', - 'A6XX_SP_PS_2D_SRC_INFO_UNK22', - 'A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_UNK28', - 'A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK', - 'A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT', - 'A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK', - 'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT', - 'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK', - 'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT', 'A6XX_SP_SMO_TAG', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT0', 'A6XX_SP_SRGB_CNTL_SRGB_MRT1', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT2', 'A6XX_SP_SRGB_CNTL_SRGB_MRT3', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT4', 'A6XX_SP_SRGB_CNTL_SRGB_MRT5', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT6', 'A6XX_SP_SRGB_CNTL_SRGB_MRT7', - 'A6XX_SP_STATE_DATA', 'A6XX_SP_TMO_UMO_TAG', - 'A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK', - 'A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT', - 'A6XX_SP_TP_MODE_CNTL_UNK3__MASK', - 'A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT', - 'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK', - 'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT', - 'A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_SP_TP_SAMPLE_CONFIG_UNK0', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_SP_TP_WINDOW_OFFSET_X__MASK', - 'A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT', - 'A6XX_SP_TP_WINDOW_OFFSET_Y__MASK', - 'A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT', 'A6XX_SP_UAV_DATA', - 'A6XX_SP_VS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_VS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_VS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_VS_CONFIG_BINDLESS_UBO', 'A6XX_SP_VS_CONFIG_ENABLED', - 'A6XX_SP_VS_CONFIG_NIBO__MASK', 'A6XX_SP_VS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_VS_CONFIG_NSAMP__MASK', 'A6XX_SP_VS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_VS_CONFIG_NTEX__MASK', 'A6XX_SP_VS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_UNK13', - 'A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_VS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_VS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_VS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_VS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_WINDOW_OFFSET_X__MASK', 'A6XX_SP_WINDOW_OFFSET_X__SHIFT', - 'A6XX_SP_WINDOW_OFFSET_Y__MASK', 'A6XX_SP_WINDOW_OFFSET_Y__SHIFT', - 'A6XX_TEX_1D', 'A6XX_TEX_2D', 'A6XX_TEX_3D', 'A6XX_TEX_ANISO', - 'A6XX_TEX_ANISO_1', 'A6XX_TEX_ANISO_16', 'A6XX_TEX_ANISO_2', - 'A6XX_TEX_ANISO_4', 'A6XX_TEX_ANISO_8', 'A6XX_TEX_BUFFER', - 'A6XX_TEX_CLAMP_TO_BORDER', 'A6XX_TEX_CLAMP_TO_EDGE', - 'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X', - 'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y', - 'A6XX_TEX_CONST_0_FMT__MASK', 'A6XX_TEX_CONST_0_FMT__SHIFT', - 'A6XX_TEX_CONST_0_MIPLVLS__MASK', - 'A6XX_TEX_CONST_0_MIPLVLS__SHIFT', - 'A6XX_TEX_CONST_0_SAMPLES__MASK', - 'A6XX_TEX_CONST_0_SAMPLES__SHIFT', 'A6XX_TEX_CONST_0_SRGB', - 'A6XX_TEX_CONST_0_SWAP__MASK', 'A6XX_TEX_CONST_0_SWAP__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_W__MASK', 'A6XX_TEX_CONST_0_SWIZ_W__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_X__MASK', 'A6XX_TEX_CONST_0_SWIZ_X__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_Y__MASK', 'A6XX_TEX_CONST_0_SWIZ_Y__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_Z__MASK', 'A6XX_TEX_CONST_0_SWIZ_Z__SHIFT', - 'A6XX_TEX_CONST_0_TILE_MODE__MASK', - 'A6XX_TEX_CONST_0_TILE_MODE__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT', - 'A6XX_TEX_CONST_1_HEIGHT__MASK', 'A6XX_TEX_CONST_1_HEIGHT__SHIFT', - 'A6XX_TEX_CONST_1_WIDTH__MASK', 'A6XX_TEX_CONST_1_WIDTH__SHIFT', - 'A6XX_TEX_CONST_2_PITCHALIGN__MASK', - 'A6XX_TEX_CONST_2_PITCHALIGN__SHIFT', - 'A6XX_TEX_CONST_2_PITCH__MASK', 'A6XX_TEX_CONST_2_PITCH__SHIFT', - 'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK', - 'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT', - 'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK', - 'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT', - 'A6XX_TEX_CONST_2_TYPE__MASK', 'A6XX_TEX_CONST_2_TYPE__SHIFT', - 'A6XX_TEX_CONST_3_ARRAY_PITCH__MASK', - 'A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT', 'A6XX_TEX_CONST_3_FLAG', - 'A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK', - 'A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT', - 'A6XX_TEX_CONST_3_TILE_ALL', 'A6XX_TEX_CONST_4_BASE_LO__MASK', - 'A6XX_TEX_CONST_4_BASE_LO__SHIFT', - 'A6XX_TEX_CONST_5_BASE_HI__MASK', - 'A6XX_TEX_CONST_5_BASE_HI__SHIFT', 'A6XX_TEX_CONST_5_DEPTH__MASK', - 'A6XX_TEX_CONST_5_DEPTH__SHIFT', - 'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK', - 'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT', - 'A6XX_TEX_CONST_6_PLANE_PITCH__MASK', - 'A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT', - 'A6XX_TEX_CONST_7_FLAG_LO__MASK', - 'A6XX_TEX_CONST_7_FLAG_LO__SHIFT', - 'A6XX_TEX_CONST_8_FLAG_HI__MASK', - 'A6XX_TEX_CONST_8_FLAG_HI__SHIFT', - 'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_TEX_CUBE', 'A6XX_TEX_CUBIC', 'A6XX_TEX_LINEAR', - 'A6XX_TEX_MIRROR_CLAMP', 'A6XX_TEX_MIRROR_REPEAT', - 'A6XX_TEX_NEAREST', 'A6XX_TEX_ONE', 'A6XX_TEX_REPEAT', - 'A6XX_TEX_SAMP_0_ANISO__MASK', 'A6XX_TEX_SAMP_0_ANISO__SHIFT', - 'A6XX_TEX_SAMP_0_LOD_BIAS__MASK', - 'A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT', - 'A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR', - 'A6XX_TEX_SAMP_0_WRAP_R__MASK', 'A6XX_TEX_SAMP_0_WRAP_R__SHIFT', - 'A6XX_TEX_SAMP_0_WRAP_S__MASK', 'A6XX_TEX_SAMP_0_WRAP_S__SHIFT', - 'A6XX_TEX_SAMP_0_WRAP_T__MASK', 'A6XX_TEX_SAMP_0_WRAP_T__SHIFT', - 'A6XX_TEX_SAMP_0_XY_MAG__MASK', 'A6XX_TEX_SAMP_0_XY_MAG__SHIFT', - 'A6XX_TEX_SAMP_0_XY_MIN__MASK', 'A6XX_TEX_SAMP_0_XY_MIN__SHIFT', - 'A6XX_TEX_SAMP_1_CLAMPENABLE', - 'A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK', - 'A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT', - 'A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF', - 'A6XX_TEX_SAMP_1_MAX_LOD__MASK', 'A6XX_TEX_SAMP_1_MAX_LOD__SHIFT', - 'A6XX_TEX_SAMP_1_MIN_LOD__MASK', 'A6XX_TEX_SAMP_1_MIN_LOD__SHIFT', - 'A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR', - 'A6XX_TEX_SAMP_1_UNNORM_COORDS', 'A6XX_TEX_SAMP_2_BCOLOR__MASK', - 'A6XX_TEX_SAMP_2_BCOLOR__SHIFT', 'A6XX_TEX_SAMP_2_CHROMA_LINEAR', - 'A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK', - 'A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT', 'A6XX_TEX_W', - 'A6XX_TEX_X', 'A6XX_TEX_Y', 'A6XX_TEX_Z', 'A6XX_TEX_ZERO', - 'A6XX_TP0_MIPMAP_BASE_DATA', 'A6XX_TP0_SMO_DATA', - 'A6XX_TP0_TMO_DATA', 'A6XX_TP1_MIPMAP_BASE_DATA', - 'A6XX_TP1_SMO_DATA', 'A6XX_TP1_TMO_DATA', - 'A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND', - 'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT', - 'A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH', - 'A6XX_TPL1_NC_MODE_CNTL_MODE', - 'A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT', - 'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT', - 'A6XX_UBO_0_BASE_LO__MASK', 'A6XX_UBO_0_BASE_LO__SHIFT', - 'A6XX_UBO_1_BASE_HI__MASK', 'A6XX_UBO_1_BASE_HI__SHIFT', - 'A6XX_UBO_1_SIZE__MASK', 'A6XX_UBO_1_SIZE__SHIFT', - 'A6XX_UCHE_CLIENT_PF_PERFSEL__MASK', - 'A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT', - 'A6XX_VBIF_CLKON_FORCE_ON_TESTBUS', - 'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK', - 'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT', - 'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK', - 'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT', - 'A6XX_VFD_ADD_OFFSET_INSTANCE', 'A6XX_VFD_ADD_OFFSET_VERTEX', - 'A6XX_VFD_CONTROL_0_DECODE_CNT__MASK', - 'A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT', - 'A6XX_VFD_CONTROL_0_FETCH_CNT__MASK', - 'A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4INST__MASK', - 'A6XX_VFD_CONTROL_1_REGID4INST__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK', - 'A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK', - 'A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4VTX__MASK', - 'A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT', - 'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK', - 'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT', - 'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK', - 'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK', - 'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK', - 'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_TESSX__MASK', - 'A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_TESSY__MASK', - 'A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT', - 'A6XX_VFD_CONTROL_4_UNK0__MASK', 'A6XX_VFD_CONTROL_4_UNK0__SHIFT', - 'A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK', - 'A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT', - 'A6XX_VFD_CONTROL_5_UNK8__MASK', 'A6XX_VFD_CONTROL_5_UNK8__SHIFT', - 'A6XX_VFD_CONTROL_6_PRIMID4PSEN', 'A6XX_VFD_DECODE_INSTR_FLOAT', - 'A6XX_VFD_DECODE_INSTR_FORMAT__MASK', - 'A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT', - 'A6XX_VFD_DECODE_INSTR_IDX__MASK', - 'A6XX_VFD_DECODE_INSTR_IDX__SHIFT', - 'A6XX_VFD_DECODE_INSTR_INSTANCED', - 'A6XX_VFD_DECODE_INSTR_OFFSET__MASK', - 'A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT', - 'A6XX_VFD_DECODE_INSTR_SWAP__MASK', - 'A6XX_VFD_DECODE_INSTR_SWAP__SHIFT', - 'A6XX_VFD_DECODE_INSTR_UNK30', - 'A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK', - 'A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT', - 'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK', - 'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT', - 'A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK', - 'A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT', - 'A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A6XX_VFD_MULTIVIEW_CNTL_ENABLE', - 'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK', - 'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK', - 'A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT', - 'A6XX_VPC_CNTL_0_PRIMIDLOC__MASK', - 'A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT', 'A6XX_VPC_CNTL_0_VARYING', - 'A6XX_VPC_CNTL_0_VIEWIDLOC__MASK', - 'A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_DS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_DS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_DS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_DS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_GS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_GS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_GS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_GS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK', - 'A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT', - 'A6XX_VPC_POINT_COORD_INVERT_INVERT', - 'A6XX_VPC_POLYGON_MODE_MODE__MASK', - 'A6XX_VPC_POLYGON_MODE_MODE__SHIFT', - 'A6XX_VPC_SO_CNTL_ADDR__MASK', 'A6XX_VPC_SO_CNTL_ADDR__SHIFT', - 'A6XX_VPC_SO_CNTL_RESET', 'A6XX_VPC_SO_DISABLE_DISABLE', - 'A6XX_VPC_SO_PROG_A_BUF__MASK', 'A6XX_VPC_SO_PROG_A_BUF__SHIFT', - 'A6XX_VPC_SO_PROG_A_EN', 'A6XX_VPC_SO_PROG_A_OFF__MASK', - 'A6XX_VPC_SO_PROG_A_OFF__SHIFT', 'A6XX_VPC_SO_PROG_B_BUF__MASK', - 'A6XX_VPC_SO_PROG_B_BUF__SHIFT', 'A6XX_VPC_SO_PROG_B_EN', - 'A6XX_VPC_SO_PROG_B_OFF__MASK', 'A6XX_VPC_SO_PROG_B_OFF__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT', - 'A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD', - 'A6XX_VPC_UNKNOWN_9107_UNK2', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_VS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_VS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_VS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_VS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VSC_BIN_COUNT_NX__MASK', 'A6XX_VSC_BIN_COUNT_NX__SHIFT', - 'A6XX_VSC_BIN_COUNT_NY__MASK', 'A6XX_VSC_BIN_COUNT_NY__SHIFT', - 'A6XX_VSC_BIN_SIZE_HEIGHT__MASK', - 'A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT', - 'A6XX_VSC_BIN_SIZE_WIDTH__MASK', 'A6XX_VSC_BIN_SIZE_WIDTH__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_H__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_W__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_X__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_Y__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT', 'A6XX_XML', 'A7XX', - 'A7XX_CLUSTER_FE', 'A7XX_CLUSTER_GRAS', 'A7XX_CLUSTER_NONE', - 'A7XX_CLUSTER_PC_VS', 'A7XX_CLUSTER_PS', 'A7XX_CLUSTER_SP_PS', - 'A7XX_CLUSTER_SP_VS', 'A7XX_CLUSTER_VPC_PS', - 'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT', - 'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT', - 'A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT', - 'A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND', - 'A7XX_CX_MISC_SW_FUSE_VALUE_LPAC', - 'A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING', 'A7XX_DBGBUS_CCHE_0', - 'A7XX_DBGBUS_CCHE_1', 'A7XX_DBGBUS_CCHE_2', 'A7XX_DBGBUS_CCU_0', - 'A7XX_DBGBUS_CCU_1', 'A7XX_DBGBUS_CCU_2', 'A7XX_DBGBUS_CCU_3', - 'A7XX_DBGBUS_CCU_4', 'A7XX_DBGBUS_CCU_5', 'A7XX_DBGBUS_CGC_CORE', - 'A7XX_DBGBUS_CGC_SUBCORE', 'A7XX_DBGBUS_COM_0', - 'A7XX_DBGBUS_CP_0_0', 'A7XX_DBGBUS_CP_0_1', 'A7XX_DBGBUS_CX', - 'A7XX_DBGBUS_DBGC', 'A7XX_DBGBUS_GBIF_CX', 'A7XX_DBGBUS_GBIF_GX', - 'A7XX_DBGBUS_GMU_CX', 'A7XX_DBGBUS_GMU_GX', 'A7XX_DBGBUS_GPC_BR', - 'A7XX_DBGBUS_GPC_BV', 'A7XX_DBGBUS_HLSQ', - 'A7XX_DBGBUS_HLSQ_DP_STR_0', 'A7XX_DBGBUS_HLSQ_DP_STR_1', - 'A7XX_DBGBUS_HLSQ_DP_STR_2', 'A7XX_DBGBUS_HLSQ_DP_STR_3', - 'A7XX_DBGBUS_HLSQ_DP_STR_4', 'A7XX_DBGBUS_HLSQ_DP_STR_5', - 'A7XX_DBGBUS_HLSQ_SPTP', 'A7XX_DBGBUS_LARC', 'A7XX_DBGBUS_LRZ_BR', - 'A7XX_DBGBUS_LRZ_BV', 'A7XX_DBGBUS_PC_BR', 'A7XX_DBGBUS_PC_BV', - 'A7XX_DBGBUS_RAS_BR', 'A7XX_DBGBUS_RAS_BV', 'A7XX_DBGBUS_RBBM', - 'A7XX_DBGBUS_RB_0', 'A7XX_DBGBUS_RB_1', 'A7XX_DBGBUS_RB_2', - 'A7XX_DBGBUS_RB_3', 'A7XX_DBGBUS_RB_4', 'A7XX_DBGBUS_RB_5', - 'A7XX_DBGBUS_TESS_BR', 'A7XX_DBGBUS_TESS_BV', 'A7XX_DBGBUS_TP_0', - 'A7XX_DBGBUS_TP_1', 'A7XX_DBGBUS_TP_10', 'A7XX_DBGBUS_TP_11', - 'A7XX_DBGBUS_TP_2', 'A7XX_DBGBUS_TP_3', 'A7XX_DBGBUS_TP_4', - 'A7XX_DBGBUS_TP_5', 'A7XX_DBGBUS_TP_6', 'A7XX_DBGBUS_TP_7', - 'A7XX_DBGBUS_TP_8', 'A7XX_DBGBUS_TP_9', 'A7XX_DBGBUS_TSE_BR', - 'A7XX_DBGBUS_TSE_BV', 'A7XX_DBGBUS_UCHE_0', 'A7XX_DBGBUS_UCHE_1', - 'A7XX_DBGBUS_UCHE_WRAPPER', 'A7XX_DBGBUS_UFC_0', - 'A7XX_DBGBUS_UFC_1', 'A7XX_DBGBUS_UFC_DSTR_0', - 'A7XX_DBGBUS_UFC_DSTR_1', 'A7XX_DBGBUS_UFC_DSTR_2', - 'A7XX_DBGBUS_USPTP_0', 'A7XX_DBGBUS_USPTP_1', - 'A7XX_DBGBUS_USPTP_10', 'A7XX_DBGBUS_USPTP_11', - 'A7XX_DBGBUS_USPTP_2', 'A7XX_DBGBUS_USPTP_3', - 'A7XX_DBGBUS_USPTP_4', 'A7XX_DBGBUS_USPTP_5', - 'A7XX_DBGBUS_USPTP_6', 'A7XX_DBGBUS_USPTP_7', - 'A7XX_DBGBUS_USPTP_8', 'A7XX_DBGBUS_USPTP_9', 'A7XX_DBGBUS_USP_0', - 'A7XX_DBGBUS_USP_1', 'A7XX_DBGBUS_USP_2', 'A7XX_DBGBUS_USP_3', - 'A7XX_DBGBUS_USP_4', 'A7XX_DBGBUS_USP_5', 'A7XX_DBGBUS_VFDP_BR', - 'A7XX_DBGBUS_VFDP_BV', 'A7XX_DBGBUS_VFD_BR_0', - 'A7XX_DBGBUS_VFD_BR_1', 'A7XX_DBGBUS_VFD_BR_2', - 'A7XX_DBGBUS_VFD_BR_3', 'A7XX_DBGBUS_VFD_BR_4', - 'A7XX_DBGBUS_VFD_BR_5', 'A7XX_DBGBUS_VFD_BR_6', - 'A7XX_DBGBUS_VFD_BR_7', 'A7XX_DBGBUS_VFD_BV_0', - 'A7XX_DBGBUS_VFD_BV_1', 'A7XX_DBGBUS_VFD_BV_2', - 'A7XX_DBGBUS_VFD_BV_3', 'A7XX_DBGBUS_VPC_BR', - 'A7XX_DBGBUS_VPC_BV', 'A7XX_DBGBUS_VPC_DSTR_0', - 'A7XX_DBGBUS_VPC_DSTR_1', 'A7XX_DBGBUS_VPC_DSTR_2', - 'A7XX_DBGBUS_VSC', 'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK', - 'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT', - 'A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR', - 'A7XX_GRAS_LRZ_CNTL2_FC_ENABLE', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3', - 'A7XX_GRAS_SU_RENDER_CNTL_BINNING', 'A7XX_HLSQ_BACKEND_META', - 'A7XX_HLSQ_BV_BE_META', 'A7XX_HLSQ_CHUNK_CPS_RAM', - 'A7XX_HLSQ_CHUNK_CPS_RAM_TAG', 'A7XX_HLSQ_CHUNK_CVS_RAM', - 'A7XX_HLSQ_CHUNK_CVS_RAM_TAG', - 'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK', - 'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK', - 'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK', - 'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT', - 'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CPS_MISC_RAM', - 'A7XX_HLSQ_CPS_MISC_RAM_1', 'A7XX_HLSQ_CPS_MISC_RAM_TAG', - 'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK', - 'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT', - 'A7XX_HLSQ_CS_CNTL_1_UNK11', 'A7XX_HLSQ_CS_CNTL_1_UNK22', - 'A7XX_HLSQ_CS_CNTL_1_UNK26', 'A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK', - 'A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT', - 'A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_CS_CNTL_ENABLED', - 'A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK', - 'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK', - 'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK', - 'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK', - 'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK', - 'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK', - 'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT', - 'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CVS_MISC_RAM', - 'A7XX_HLSQ_CVS_MISC_RAM_TAG', 'A7XX_HLSQ_DATAPATH_DSTR_META', - 'A7XX_HLSQ_DATAPATH_META', - 'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_DP', - 'A7XX_HLSQ_DP_STR', 'A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT', - 'A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_DS_CNTL_ENABLED', - 'A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_EVENT_CMD_EVENT__MASK', - 'A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT', - 'A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_FRONTEND_META', - 'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK', - 'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT', - 'A7XX_HLSQ_FS_CNTL_0_UNK2__MASK', - 'A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A7XX_HLSQ_FS_CNTL_0_VARYINGS', - 'A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_FS_CNTL_ENABLED', - 'A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE', - 'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', - 'A7XX_HLSQ_GFX_CPS_CONST_RAM', 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', - 'A7XX_HLSQ_GFX_CVS_CONST_RAM', 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM', - 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', - 'A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_GS_CNTL_ENABLED', - 'A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_HS_CNTL_ENABLED', - 'A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 'A7XX_HLSQ_INDIRECT_META', 'A7XX_HLSQ_INST_RAM', - 'A7XX_HLSQ_INST_RAM_1', 'A7XX_HLSQ_INST_RAM_2', - 'A7XX_HLSQ_INST_RAM_TAG', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_IBO', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_DS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_FS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO', - 'A7XX_HLSQ_INVALIDATE_CMD_GS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_HS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A7XX_HLSQ_L2STC_INFO_CMD', - 'A7XX_HLSQ_L2STC_TAG_RAM', 'A7XX_HLSQ_STATE', - 'A7XX_HLSQ_STPROC_META', - 'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK', - 'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT', - 'A7XX_HLSQ_UNKNOWN_A9AE_UNK8', 'A7XX_HLSQ_UNKNOWN_A9AE_UNK9', - 'A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_VS_CNTL_ENABLED', - 'A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK', - 'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT', - 'A7XX_PC_POLYGON_MODE_MODE__MASK', - 'A7XX_PC_POLYGON_MODE_MODE__SHIFT', 'A7XX_PC_RASTER_CNTL_DISCARD', - 'A7XX_PC_RASTER_CNTL_STREAM__MASK', - 'A7XX_PC_RASTER_CNTL_STREAM__SHIFT', - 'A7XX_PC_RASTER_CNTL_V2_DISCARD', - 'A7XX_PC_RASTER_CNTL_V2_STREAM__MASK', - 'A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT', 'A7XX_PERF_BYPC_FULL', - 'A7XX_PERF_BYPC_FULL_CCHE_STALL', 'A7XX_PERF_BYPC_VHUB_STALL', - 'A7XX_PERF_BYPD_FULL', 'A7XX_PERF_BYPD_FULL_GBIF_STALL', - 'A7XX_PERF_CCHE_BANK_REQ0', 'A7XX_PERF_CCHE_BANK_REQ1', - 'A7XX_PERF_CCHE_BANK_REQ10', 'A7XX_PERF_CCHE_BANK_REQ11', - 'A7XX_PERF_CCHE_BANK_REQ12', 'A7XX_PERF_CCHE_BANK_REQ13', - 'A7XX_PERF_CCHE_BANK_REQ14', 'A7XX_PERF_CCHE_BANK_REQ15', - 'A7XX_PERF_CCHE_BANK_REQ2', 'A7XX_PERF_CCHE_BANK_REQ3', - 'A7XX_PERF_CCHE_BANK_REQ4', 'A7XX_PERF_CCHE_BANK_REQ5', - 'A7XX_PERF_CCHE_BANK_REQ6', 'A7XX_PERF_CCHE_BANK_REQ7', - 'A7XX_PERF_CCHE_BANK_REQ8', 'A7XX_PERF_CCHE_BANK_REQ9', - 'A7XX_PERF_CCHE_BUSY_CYCLES', 'A7XX_PERF_CCHE_DBANK_CONFLICT', - 'A7XX_PERF_CCHE_DPH_QUEUE_FULL', 'A7XX_PERF_CCHE_GBANK_REQ0', - 'A7XX_PERF_CCHE_GBANK_REQ1', 'A7XX_PERF_CCHE_GBANK_REQ2', - 'A7XX_PERF_CCHE_GBANK_REQ3', - 'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', - 'A7XX_PERF_CCHE_OPH_QUEUE_FULL', 'A7XX_PERF_CCHE_RAM_READ_REQ', - 'A7XX_PERF_CCHE_RAM_WRITE_REQ', - 'A7XX_PERF_CCHE_READ_REQUESTS_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_LRZ', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', - 'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_VPC', - 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', - 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', - 'A7XX_PERF_CCHE_STALL_CYCLES_TP', - 'A7XX_PERF_CCHE_STALL_CYCLES_UCHE', - 'A7XX_PERF_CCHE_TPH_CONFLICT_CL', 'A7XX_PERF_CCHE_TPH_EXT_FULL', - 'A7XX_PERF_CCHE_TPH_QUEUE_FULL', 'A7XX_PERF_CCHE_TPH_REF_FULL', - 'A7XX_PERF_CCHE_TPH_VICTIM_FULL', - 'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', - 'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', - 'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', - 'A7XX_PERF_CCHE_WACK_QUEUE_FULL', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_SP', 'A7XX_PERF_CCU_2D_RD_REQ', - 'A7XX_PERF_CCU_2D_WR_REQ', 'A7XX_PERF_CCU_BUSY_CYCLES', - 'A7XX_PERF_CCU_COLOR_BLOCKS', 'A7XX_PERF_CCU_COLOR_BLOCK_HIT', - 'A7XX_PERF_CCU_COLOR_EVB_STALL', - 'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', - 'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', - 'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', - 'A7XX_PERF_CCU_DEPTH_BLOCKS', 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT', - 'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', - 'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', - 'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', - 'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', - 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', - 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', - 'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', 'A7XX_PERF_CCU_GMEM_READ', - 'A7XX_PERF_CCU_GMEM_WRITE', 'A7XX_PERF_CCU_NEVER_COUNT', - 'A7XX_PERF_CCU_PARTIAL_BLOCK_READ', - 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', - 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', - 'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', - 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', - 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', - 'A7XX_PERF_CCU_RESERVED_100', 'A7XX_PERF_CCU_RESERVED_101', - 'A7XX_PERF_CCU_RESERVED_102', 'A7XX_PERF_CCU_RESERVED_103', - 'A7XX_PERF_CCU_RESERVED_104', 'A7XX_PERF_CCU_RESERVED_105', - 'A7XX_PERF_CCU_RESERVED_106', 'A7XX_PERF_CCU_RESERVED_107', - 'A7XX_PERF_CCU_RESERVED_108', 'A7XX_PERF_CCU_RESERVED_109', - 'A7XX_PERF_CCU_RESERVED_110', 'A7XX_PERF_CCU_RESERVED_111', - 'A7XX_PERF_CCU_RESERVED_112', 'A7XX_PERF_CCU_RESERVED_113', - 'A7XX_PERF_CCU_RESERVED_114', 'A7XX_PERF_CCU_RESERVED_115', - 'A7XX_PERF_CCU_RESERVED_116', 'A7XX_PERF_CCU_RESERVED_117', - 'A7XX_PERF_CCU_RESERVED_118', 'A7XX_PERF_CCU_RESERVED_119', - 'A7XX_PERF_CCU_RESERVED_120', 'A7XX_PERF_CCU_RESERVED_121', - 'A7XX_PERF_CCU_RESERVED_122', 'A7XX_PERF_CCU_RESERVED_123', - 'A7XX_PERF_CCU_RESERVED_124', 'A7XX_PERF_CCU_RESERVED_125', - 'A7XX_PERF_CCU_RESERVED_126', 'A7XX_PERF_CCU_RESERVED_127', - 'A7XX_PERF_CCU_RESERVED_32', 'A7XX_PERF_CCU_RESERVED_33', - 'A7XX_PERF_CCU_RESERVED_34', 'A7XX_PERF_CCU_RESERVED_35', - 'A7XX_PERF_CCU_RESERVED_36', 'A7XX_PERF_CCU_RESERVED_37', - 'A7XX_PERF_CCU_RESERVED_38', 'A7XX_PERF_CCU_RESERVED_39', - 'A7XX_PERF_CCU_RESERVED_40', 'A7XX_PERF_CCU_RESERVED_41', - 'A7XX_PERF_CCU_RESERVED_42', 'A7XX_PERF_CCU_RESERVED_43', - 'A7XX_PERF_CCU_RESERVED_44', 'A7XX_PERF_CCU_RESERVED_45', - 'A7XX_PERF_CCU_RESERVED_46', 'A7XX_PERF_CCU_RESERVED_47', - 'A7XX_PERF_CCU_RESERVED_48', 'A7XX_PERF_CCU_RESERVED_49', - 'A7XX_PERF_CCU_RESERVED_50', 'A7XX_PERF_CCU_RESERVED_51', - 'A7XX_PERF_CCU_RESERVED_52', 'A7XX_PERF_CCU_RESERVED_53', - 'A7XX_PERF_CCU_RESERVED_54', 'A7XX_PERF_CCU_RESERVED_55', - 'A7XX_PERF_CCU_RESERVED_56', 'A7XX_PERF_CCU_RESERVED_57', - 'A7XX_PERF_CCU_RESERVED_58', 'A7XX_PERF_CCU_RESERVED_59', - 'A7XX_PERF_CCU_RESERVED_60', 'A7XX_PERF_CCU_RESERVED_61', - 'A7XX_PERF_CCU_RESERVED_62', 'A7XX_PERF_CCU_RESERVED_63', - 'A7XX_PERF_CCU_RESERVED_78', 'A7XX_PERF_CCU_RESERVED_79', - 'A7XX_PERF_CCU_RESERVED_80', 'A7XX_PERF_CCU_RESERVED_81', - 'A7XX_PERF_CCU_RESERVED_82', 'A7XX_PERF_CCU_RESERVED_83', - 'A7XX_PERF_CCU_RESERVED_84', 'A7XX_PERF_CCU_RESERVED_85', - 'A7XX_PERF_CCU_RESERVED_86', 'A7XX_PERF_CCU_RESERVED_87', - 'A7XX_PERF_CCU_RESERVED_88', 'A7XX_PERF_CCU_RESERVED_89', - 'A7XX_PERF_CCU_RESERVED_90', 'A7XX_PERF_CCU_RESERVED_91', - 'A7XX_PERF_CCU_RESERVED_92', 'A7XX_PERF_CCU_RESERVED_93', - 'A7XX_PERF_CCU_RESERVED_94', 'A7XX_PERF_CCU_RESERVED_95', - 'A7XX_PERF_CCU_RESERVED_96', 'A7XX_PERF_CCU_RESERVED_97', - 'A7XX_PERF_CCU_RESERVED_98', 'A7XX_PERF_CCU_RESERVED_99', - 'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', - 'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', - 'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', - 'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', - 'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_NEVER_COUNT', - 'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', - 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 'A7XX_PERF_CP_AHB_STALL_SQE_GMU', - 'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', - 'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', - 'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 'A7XX_PERF_CP_ALWAYS_COUNT', 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', - 'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', 'A7XX_PERF_CP_AQE_SQE_STALL', - 'A7XX_PERF_CP_BUSY_CYCLES', 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', - 'A7XX_PERF_CP_CACHE_FLUSH', 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', - 'A7XX_PERF_CP_CLUSTER_FE_S_FULL', - 'A7XX_PERF_CP_CLUSTER_FE_US_FULL', - 'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', - 'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_GRAS_FULL', 'A7XX_PERF_CP_CLUSTER_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_SP_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_SP_VS_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_US_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', 'A7XX_PERF_CP_CONTEXT_DONE', - 'A7XX_PERF_CP_DCACHE_HITS', 'A7XX_PERF_CP_DCACHE_MISSES', - 'A7XX_PERF_CP_DCACHE_STALLS', - 'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 'A7XX_PERF_CP_ICACHE_HITS', 'A7XX_PERF_CP_ICACHE_MISSES', - 'A7XX_PERF_CP_ICACHE_STALL', 'A7XX_PERF_CP_ISR_CYCLES', - 'A7XX_PERF_CP_LONG_PREEMPTIONS', - 'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', - 'A7XX_PERF_CP_MEMORY_POOL_EMPTY', - 'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', 'A7XX_PERF_CP_MODE_SWITCH', - 'A7XX_PERF_CP_NEVER_COUNT', 'A7XX_PERF_CP_NUM_PREEMPTIONS', - 'A7XX_PERF_CP_OUTPUT_BLOCKED', 'A7XX_PERF_CP_PM4_DATA', - 'A7XX_PERF_CP_PM4_HEADERS', - 'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', - 'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', - 'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 'A7XX_PERF_CP_SQE_AQE_STARVE', - 'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 'A7XX_PERF_CP_SQE_DRAW_EXEC', 'A7XX_PERF_CP_SQE_EXEC_PROFILED', - 'A7XX_PERF_CP_SQE_IDLE', 'A7XX_PERF_CP_SQE_INSTR_COUNTER', - 'A7XX_PERF_CP_SQE_I_CACHE_STARVE', - 'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', - 'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', - 'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', - 'A7XX_PERF_CP_SQE_MRB_STARVE', 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL', - 'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB1', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB2', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB3', - 'A7XX_PERF_CP_SQE_PM4_STARVE_RB', - 'A7XX_PERF_CP_SQE_PM4_STARVE_SDS', - 'A7XX_PERF_CP_SQE_PM4_WFI_STALL', 'A7XX_PERF_CP_SQE_RRB_STARVE', - 'A7XX_PERF_CP_SQE_SAVE_SDS_STATE', 'A7XX_PERF_CP_SQE_SYNC_STALL', - 'A7XX_PERF_CP_SQE_SYS_WFI_STALL', 'A7XX_PERF_CP_SQE_T4_EXEC', - 'A7XX_PERF_CP_SQE_VSD_STARVE', - 'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', - 'A7XX_PERF_CP_S_SKEW_BUFFER_FULL', 'A7XX_PERF_CP_VBIF_READ_BEATS', - 'A7XX_PERF_CP_VBIF_WRITE_BEATS', 'A7XX_PERF_CP_VSD_DECODE_STARVE', - 'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', 'A7XX_PERF_CP_ZPASS_DONE', - 'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', - 'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', - 'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', - 'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', - 'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_RESOLVE_EVENTS', - 'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', - 'A7XX_PERF_DHUB_PTABLE_FULL', - 'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', - 'A7XX_PERF_GBIF_NEVER_COUNT', - 'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', - 'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', - 'A7XX_PERF_GBIF_RESERVED_1', 'A7XX_PERF_GBIF_RESERVED_100', - 'A7XX_PERF_GBIF_RESERVED_101', 'A7XX_PERF_GBIF_RESERVED_102', - 'A7XX_PERF_GBIF_RESERVED_103', 'A7XX_PERF_GBIF_RESERVED_104', - 'A7XX_PERF_GBIF_RESERVED_105', 'A7XX_PERF_GBIF_RESERVED_106', - 'A7XX_PERF_GBIF_RESERVED_107', 'A7XX_PERF_GBIF_RESERVED_108', - 'A7XX_PERF_GBIF_RESERVED_109', 'A7XX_PERF_GBIF_RESERVED_110', - 'A7XX_PERF_GBIF_RESERVED_111', 'A7XX_PERF_GBIF_RESERVED_112', - 'A7XX_PERF_GBIF_RESERVED_113', 'A7XX_PERF_GBIF_RESERVED_114', - 'A7XX_PERF_GBIF_RESERVED_115', 'A7XX_PERF_GBIF_RESERVED_116', - 'A7XX_PERF_GBIF_RESERVED_117', 'A7XX_PERF_GBIF_RESERVED_118', - 'A7XX_PERF_GBIF_RESERVED_119', 'A7XX_PERF_GBIF_RESERVED_12', - 'A7XX_PERF_GBIF_RESERVED_120', 'A7XX_PERF_GBIF_RESERVED_121', - 'A7XX_PERF_GBIF_RESERVED_122', 'A7XX_PERF_GBIF_RESERVED_123', - 'A7XX_PERF_GBIF_RESERVED_124', 'A7XX_PERF_GBIF_RESERVED_125', - 'A7XX_PERF_GBIF_RESERVED_126', 'A7XX_PERF_GBIF_RESERVED_127', - 'A7XX_PERF_GBIF_RESERVED_128', 'A7XX_PERF_GBIF_RESERVED_129', - 'A7XX_PERF_GBIF_RESERVED_13', 'A7XX_PERF_GBIF_RESERVED_130', - 'A7XX_PERF_GBIF_RESERVED_131', 'A7XX_PERF_GBIF_RESERVED_132', - 'A7XX_PERF_GBIF_RESERVED_133', 'A7XX_PERF_GBIF_RESERVED_134', - 'A7XX_PERF_GBIF_RESERVED_135', 'A7XX_PERF_GBIF_RESERVED_136', - 'A7XX_PERF_GBIF_RESERVED_137', 'A7XX_PERF_GBIF_RESERVED_138', - 'A7XX_PERF_GBIF_RESERVED_139', 'A7XX_PERF_GBIF_RESERVED_14', - 'A7XX_PERF_GBIF_RESERVED_140', 'A7XX_PERF_GBIF_RESERVED_141', - 'A7XX_PERF_GBIF_RESERVED_142', 'A7XX_PERF_GBIF_RESERVED_143', - 'A7XX_PERF_GBIF_RESERVED_144', 'A7XX_PERF_GBIF_RESERVED_145', - 'A7XX_PERF_GBIF_RESERVED_146', 'A7XX_PERF_GBIF_RESERVED_147', - 'A7XX_PERF_GBIF_RESERVED_148', 'A7XX_PERF_GBIF_RESERVED_149', - 'A7XX_PERF_GBIF_RESERVED_15', 'A7XX_PERF_GBIF_RESERVED_150', - 'A7XX_PERF_GBIF_RESERVED_151', 'A7XX_PERF_GBIF_RESERVED_152', - 'A7XX_PERF_GBIF_RESERVED_153', 'A7XX_PERF_GBIF_RESERVED_154', - 'A7XX_PERF_GBIF_RESERVED_155', 'A7XX_PERF_GBIF_RESERVED_156', - 'A7XX_PERF_GBIF_RESERVED_16', 'A7XX_PERF_GBIF_RESERVED_17', - 'A7XX_PERF_GBIF_RESERVED_18', 'A7XX_PERF_GBIF_RESERVED_19', - 'A7XX_PERF_GBIF_RESERVED_2', 'A7XX_PERF_GBIF_RESERVED_20', - 'A7XX_PERF_GBIF_RESERVED_21', 'A7XX_PERF_GBIF_RESERVED_24', - 'A7XX_PERF_GBIF_RESERVED_25', 'A7XX_PERF_GBIF_RESERVED_26', - 'A7XX_PERF_GBIF_RESERVED_27', 'A7XX_PERF_GBIF_RESERVED_28', - 'A7XX_PERF_GBIF_RESERVED_29', 'A7XX_PERF_GBIF_RESERVED_3', - 'A7XX_PERF_GBIF_RESERVED_30', 'A7XX_PERF_GBIF_RESERVED_31', - 'A7XX_PERF_GBIF_RESERVED_32', 'A7XX_PERF_GBIF_RESERVED_33', - 'A7XX_PERF_GBIF_RESERVED_36', 'A7XX_PERF_GBIF_RESERVED_37', - 'A7XX_PERF_GBIF_RESERVED_38', 'A7XX_PERF_GBIF_RESERVED_39', - 'A7XX_PERF_GBIF_RESERVED_4', 'A7XX_PERF_GBIF_RESERVED_40', - 'A7XX_PERF_GBIF_RESERVED_41', 'A7XX_PERF_GBIF_RESERVED_42', - 'A7XX_PERF_GBIF_RESERVED_43', 'A7XX_PERF_GBIF_RESERVED_44', - 'A7XX_PERF_GBIF_RESERVED_45', 'A7XX_PERF_GBIF_RESERVED_48', - 'A7XX_PERF_GBIF_RESERVED_49', 'A7XX_PERF_GBIF_RESERVED_5', - 'A7XX_PERF_GBIF_RESERVED_50', 'A7XX_PERF_GBIF_RESERVED_51', - 'A7XX_PERF_GBIF_RESERVED_52', 'A7XX_PERF_GBIF_RESERVED_53', - 'A7XX_PERF_GBIF_RESERVED_54', 'A7XX_PERF_GBIF_RESERVED_55', - 'A7XX_PERF_GBIF_RESERVED_56', 'A7XX_PERF_GBIF_RESERVED_57', - 'A7XX_PERF_GBIF_RESERVED_58', 'A7XX_PERF_GBIF_RESERVED_59', - 'A7XX_PERF_GBIF_RESERVED_6', 'A7XX_PERF_GBIF_RESERVED_60', - 'A7XX_PERF_GBIF_RESERVED_61', 'A7XX_PERF_GBIF_RESERVED_62', - 'A7XX_PERF_GBIF_RESERVED_63', 'A7XX_PERF_GBIF_RESERVED_64', - 'A7XX_PERF_GBIF_RESERVED_65', 'A7XX_PERF_GBIF_RESERVED_66', - 'A7XX_PERF_GBIF_RESERVED_67', 'A7XX_PERF_GBIF_RESERVED_7', - 'A7XX_PERF_GBIF_RESERVED_78', 'A7XX_PERF_GBIF_RESERVED_79', - 'A7XX_PERF_GBIF_RESERVED_8', 'A7XX_PERF_GBIF_RESERVED_80', - 'A7XX_PERF_GBIF_RESERVED_81', 'A7XX_PERF_GBIF_RESERVED_82', - 'A7XX_PERF_GBIF_RESERVED_83', 'A7XX_PERF_GBIF_RESERVED_84', - 'A7XX_PERF_GBIF_RESERVED_85', 'A7XX_PERF_GBIF_RESERVED_86', - 'A7XX_PERF_GBIF_RESERVED_87', 'A7XX_PERF_GBIF_RESERVED_88', - 'A7XX_PERF_GBIF_RESERVED_89', 'A7XX_PERF_GBIF_RESERVED_9', - 'A7XX_PERF_GBIF_RESERVED_90', 'A7XX_PERF_GBIF_RESERVED_91', - 'A7XX_PERF_GBIF_RESERVED_92', 'A7XX_PERF_GBIF_RESERVED_93', - 'A7XX_PERF_GBIF_RESERVED_94', 'A7XX_PERF_GBIF_RESERVED_95', - 'A7XX_PERF_GBIF_RESERVED_96', 'A7XX_PERF_GBIF_RESERVED_97', - 'A7XX_PERF_GBIF_RESERVED_98', 'A7XX_PERF_GBIF_RESERVED_99', - 'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', - 'A7XX_PERF_HLSQ_BUSY_CYCLES', 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', - 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', - 'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_BV_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_S2W_CYCLES', 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_BV_STALL_CYCLES', 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', - 'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', - 'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_FS_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_S2W_CYCLES', 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_FS_STALL_CYCLES', 'A7XX_PERF_HLSQ_FS_STARVING_SP', - 'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', - 'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', - 'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', - 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', - 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_SP', 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_UCHE', - 'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', - 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', - 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', - 'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', - 'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', - 'A7XX_PERF_HLSQ_NEVER_COUNT', 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT', - 'A7XX_PERF_HLSQ_RESERVED_19', 'A7XX_PERF_HLSQ_RESERVED_20', - 'A7XX_PERF_HLSQ_RESERVED_37', 'A7XX_PERF_HLSQ_RESERVED_7', - 'A7XX_PERF_HLSQ_RESERVED_8', 'A7XX_PERF_HLSQ_RESERVED_9', - 'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', - 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', - 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', - 'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', - 'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', - 'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', - 'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 'A7XX_PERF_LRZ_BUSY_CYCLES', 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT', - 'A7XX_PERF_LRZ_FEEDBACK_DISCARD', 'A7XX_PERF_LRZ_FEEDBACK_STALL', - 'A7XX_PERF_LRZ_FULL_8X8_TILES', 'A7XX_PERF_LRZ_LRZ_READ', - 'A7XX_PERF_LRZ_LRZ_WRITE', 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', - 'A7XX_PERF_LRZ_NEVER_COUNT', 'A7XX_PERF_LRZ_NUM_FLOCK', - 'A7XX_PERF_LRZ_PARTIAL_8X8_TILES', - 'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', - 'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 'A7XX_PERF_LRZ_RAS_MASK_TRANS', 'A7XX_PERF_LRZ_READ_LATENCY', - 'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', - 'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', - 'A7XX_PERF_LRZ_STALL_CYCLES_MVC', 'A7XX_PERF_LRZ_STALL_CYCLES_RB', - 'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 'A7XX_PERF_LRZ_STALL_CYCLES_UCHE', - 'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_LRZ_STALL_CYCLES_VSC', - 'A7XX_PERF_LRZ_STARVE_CYCLES_RAS', 'A7XX_PERF_LRZ_TILE_KILLED', - 'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', - 'A7XX_PERF_LRZ_TILE_KILLED_BY_Z', 'A7XX_PERF_LRZ_TOTAL_PIXEL', - 'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 'A7XX_PERF_PC_NEVER_COUNT', 'A7XX_PERF_PC_RESERVED_51', - 'A7XX_PERF_PC_RESERVED_52', 'A7XX_PERF_PC_RESERVED_53', - 'A7XX_PERF_PC_RESERVED_54', 'A7XX_PERF_PC_RESERVED_55', - 'A7XX_PERF_PC_RESERVED_56', 'A7XX_PERF_PC_RESERVED_57', - 'A7XX_PERF_PC_RESERVED_58', 'A7XX_PERF_PC_RESERVED_59', - 'A7XX_PERF_PC_S_BUSY_CYCLES', 'A7XX_PERF_PC_S_DS_INVOCATIONS', - 'A7XX_PERF_PC_S_DS_PRIMITIVES', 'A7XX_PERF_PC_S_GS_INVOCATIONS', - 'A7XX_PERF_PC_S_HS_INVOCATIONS', 'A7XX_PERF_PC_S_IA_PRIMITIVES', - 'A7XX_PERF_PC_S_IA_VERTICES', 'A7XX_PERF_PC_S_MESH_VS_WAVES', - 'A7XX_PERF_PC_S_STALL_CYCLES_TESS', - 'A7XX_PERF_PC_S_STALL_CYCLES_VFD', - 'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', - 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', - 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', - 'A7XX_PERF_PC_S_TESS_BUSY_CYCLES', - 'A7XX_PERF_PC_S_TESS_FACTOR_TRANS', - 'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', - 'A7XX_PERF_PC_S_TESS_PC_UV_TRANS', - 'A7XX_PERF_PC_S_TESS_PID_ACTIVE', - 'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', - 'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', - 'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', - 'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', - 'A7XX_PERF_PC_S_TESS_WORKING_CYCLES', - 'A7XX_PERF_PC_S_VERTEX_HITS', 'A7XX_PERF_PC_S_VPC_PRIMITIVES', - 'A7XX_PERF_PC_S_VS_INVOCATIONS', 'A7XX_PERF_PC_S_WORKING_CYCLES', - 'A7XX_PERF_PC_US_2D_DRAWCALLS', 'A7XX_PERF_PC_US_3D_DRAWCALLS', - 'A7XX_PERF_PC_US_BR2BV_SWITCH', - 'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', - 'A7XX_PERF_PC_US_BUSY_CYCLES', 'A7XX_PERF_PC_US_BV2BR_SWITCH', - 'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', - 'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', - 'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', - 'A7XX_PERF_PC_US_BV_STARVED_BY_RARB', 'A7XX_PERF_PC_US_DEAD_PRIM', - 'A7XX_PERF_PC_US_DP0_INPUT_STALLS', - 'A7XX_PERF_PC_US_DP0_LIVE_PRIM', 'A7XX_PERF_PC_US_DP0_RARB_FULL', - 'A7XX_PERF_PC_US_DP1_INPUT_STALLS', - 'A7XX_PERF_PC_US_DP1_LIVE_PRIM', 'A7XX_PERF_PC_US_DP1_RARB_FULL', - 'A7XX_PERF_PC_US_INSTANCES', 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS', - 'A7XX_PERF_PC_US_MESH_DEAD_PRIM', 'A7XX_PERF_PC_US_MESH_DRAWS', - 'A7XX_PERF_PC_US_MESH_LIVE_PRIM', - 'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', - 'A7XX_PERF_PC_US_MESH_PA_EN_PRIM', - 'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', - 'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', - 'A7XX_PERF_PC_US_PASSPAIR_STALL', - 'A7XX_PERF_PC_US_PREDRAW_STALLS', - 'A7XX_PERF_PC_US_SLICE_LIVE_PRIM', - 'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', - 'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', - 'A7XX_PERF_PC_US_STALL_CYCLES_PC_S', - 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', - 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', - 'A7XX_PERF_PC_US_STARVE_CYCLES_DI', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', - 'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', - 'A7XX_PERF_PC_US_UCHE_0_TRANS', 'A7XX_PERF_PC_US_UCHE_1_TRANS', - 'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', - 'A7XX_PERF_PC_US_VIS_STREAMS_LOADED', - 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', - 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', - 'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', - 'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', - 'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', - 'A7XX_PERF_PC_US_WORKING_CYCLES', 'A7XX_PERF_RAS_8X4_TILES', - 'A7XX_PERF_RAS_BLOCKS', 'A7XX_PERF_RAS_BUSY_CYCLES', - 'A7XX_PERF_RAS_FALSE_PARTIAL_STILE', - 'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', - 'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', - 'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 'A7XX_PERF_RAS_MASKGEN_ACTIVE', 'A7XX_PERF_RAS_NEVER_COUNT', - 'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', - 'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', - 'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', - 'A7XX_PERF_RAS_STALL_CYCLES_LRZ', - 'A7XX_PERF_RAS_STARVE_CYCLES_TSE', - 'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 'A7XX_PERF_RAS_SUPER_TILES', 'A7XX_PERF_RBBM_NEVER_COUNT', - 'A7XX_PERF_RBBM_S_HLSQ_BUSY', 'A7XX_PERF_RBBM_S_PC_BUSY', - 'A7XX_PERF_RBBM_S_RAS_BUSY', 'A7XX_PERF_RBBM_S_TESS_BUSY', - 'A7XX_PERF_RBBM_S_TSEBE_BUSY', 'A7XX_PERF_RBBM_S_TSEFE_BUSY', - 'A7XX_PERF_RBBM_US_ALWAYS_COUNT', 'A7XX_PERF_RBBM_US_ALWAYS_ON', - 'A7XX_PERF_RBBM_US_COM_BUSY', 'A7XX_PERF_RBBM_US_DCOM_BUSY', - 'A7XX_PERF_RBBM_US_HLSQ_BUSY', 'A7XX_PERF_RBBM_US_PC_BUSY', - 'A7XX_PERF_RBBM_US_STATUS_MASKED', 'A7XX_PERF_RBBM_US_UCHE_BUSY', - 'A7XX_PERF_RBBM_US_VBIF_BUSY', 'A7XX_PERF_RBBM_US_VSC_BUSY', - 'A7XX_PERF_RB_2D_ALIVE_CYCLES', - 'A7XX_PERF_RB_2D_STARVE_CYCLES_SP', - 'A7XX_PERF_RB_2D_VALID_PIXELS', 'A7XX_PERF_RB_3D_PIXELS', - 'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', - 'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', - 'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', - 'A7XX_PERF_RB_BLENDER_WORKING_CYCLES', 'A7XX_PERF_RB_BUSY_CYCLES', - 'A7XX_PERF_RB_COLOR_PIX_TILES', - 'A7XX_PERF_RB_CPROC_WORKING_CYCLES', 'A7XX_PERF_RB_C_READ', - 'A7XX_PERF_RB_C_WRITE', 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', - 'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', 'A7XX_PERF_RB_HLSQ_ACTIVE', - 'A7XX_PERF_RB_LATE_Z_ARB3_GRANT', 'A7XX_PERF_RB_NEVER_COUNT', - 'A7XX_PERF_RB_PS_INVOCATIONS', - 'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', - 'A7XX_PERF_RB_STALL_CYCLES_CCU', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_HLSQ', - 'A7XX_PERF_RB_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', - 'A7XX_PERF_RB_STARVE_CYCLES_CCU', - 'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', - 'A7XX_PERF_RB_STARVE_CYCLES_SP', - 'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', 'A7XX_PERF_RB_S_FAIL', - 'A7XX_PERF_RB_TOTAL_PASS', 'A7XX_PERF_RB_VRS_1X1_QUADS', - 'A7XX_PERF_RB_VRS_1X2_QUADS', 'A7XX_PERF_RB_VRS_2X1_QUADS', - 'A7XX_PERF_RB_VRS_2X2_QUADS', 'A7XX_PERF_RB_VRS_2X4_QUADS', - 'A7XX_PERF_RB_VRS_4X2_QUADS', 'A7XX_PERF_RB_VRS_4X4_QUADS', - 'A7XX_PERF_RB_ZPROC_WORKING_CYCLES', 'A7XX_PERF_RB_Z_FAIL', - 'A7XX_PERF_RB_Z_PASS', 'A7XX_PERF_RB_Z_READ', - 'A7XX_PERF_RB_Z_WORKLOAD', 'A7XX_PERF_RB_Z_WRITE', - 'A7XX_PERF_SP_ADDR_LOCK_COUNT', - 'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', - 'A7XX_PERF_SP_ALU_GPR_READ_CYCLES', - 'A7XX_PERF_SP_ALU_WORKING_CYCLES', 'A7XX_PERF_SP_ANY_EU_WORKING', - 'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', - 'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', - 'A7XX_PERF_SP_ANY_EU_WORKING_LPAC', - 'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', - 'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', - 'A7XX_PERF_SP_BRANCH_INS_COUNT', - 'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', - 'A7XX_PERF_SP_BRANCH_NOT_TAKEN', 'A7XX_PERF_SP_BRANCH_TAKEN', - 'A7XX_PERF_SP_BUSY_CYCLES', 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES', - 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', - 'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', 'A7XX_PERF_SP_CS_INSTRUCTIONS', - 'A7XX_PERF_SP_CS_INVOCATIONS', - 'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', - 'A7XX_PERF_SP_DS_INSTRUCTIONS', 'A7XX_PERF_SP_EFU_WORKING_CYCLES', - 'A7XX_PERF_SP_EWAVE_CONTEXTS', - 'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', - 'A7XX_PERF_SP_EXECUTABLE_WAVES', 'A7XX_PERF_SP_EXPORT_RB_TRANS', - 'A7XX_PERF_SP_EXPORT_VPC_TRANS', - 'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_FS_INSTRUCTIONS', 'A7XX_PERF_SP_FS_OOO_WAVE_ACC', - 'A7XX_PERF_SP_FS_STAGE_1X_WAVES', - 'A7XX_PERF_SP_FS_STAGE_2X_WAVES', - 'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', - 'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', - 'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', - 'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', - 'A7XX_PERF_SP_FS_WAVE_REQ_PENDING', - 'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', - 'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', - 'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', - 'A7XX_PERF_SP_GM_ATOMICS', 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', - 'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', - 'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', 'A7XX_PERF_SP_GPR_READ', - 'A7XX_PERF_SP_GPR_READ_BANK', 'A7XX_PERF_SP_GPR_READ_CONFLICT', - 'A7XX_PERF_SP_GPR_READ_PREFETCH', 'A7XX_PERF_SP_GPR_WRITE', - 'A7XX_PERF_SP_GPR_WRITE_BANK', 'A7XX_PERF_SP_GPR_WRITE_CONFLICT', - 'A7XX_PERF_SP_GS_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', - 'A7XX_PERF_SP_HS_INSTRUCTIONS', 'A7XX_PERF_SP_ICL1_MISSES', - 'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', - 'A7XX_PERF_SP_ICL1_REQUESTS', 'A7XX_PERF_SP_LB_ALU_READ_CONS', - 'A7XX_PERF_SP_LB_LDST_RW_LM', - 'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', - 'A7XX_PERF_SP_LB_LDST_WRITE_CONS', - 'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', - 'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', - 'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', - 'A7XX_PERF_SP_LB_READ_XFER_ALU', - 'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', - 'A7XX_PERF_SP_LB_WRITE_XFER_VPC', 'A7XX_PERF_SP_LM_ATOMICS', - 'A7XX_PERF_SP_LM_BANK_CONFLICTS', 'A7XX_PERF_SP_LM_FULL_CYCLES', - 'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', - 'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', - 'A7XX_PERF_SP_LM_WORKING_CYCLES', - 'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 'A7XX_PERF_SP_LPAC_BUSY_CYCLES', 'A7XX_PERF_SP_LPAC_DRAWCALLS', - 'A7XX_PERF_SP_LPAC_INSTRUCTIONS', - 'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', 'A7XX_PERF_SP_NEVER_COUNT', - 'A7XX_PERF_SP_NON_EXECUTION_CYCLES', - 'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', - 'A7XX_PERF_SP_OUTPUT_3D_PIXELS', - 'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', 'A7XX_PERF_SP_PIXELS', - 'A7XX_PERF_SP_PIXELS_KILLED', 'A7XX_PERF_SP_PI_WORKING_CYCLES', - 'A7XX_PERF_SP_PREDICT_INS_COUNT', - 'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', - 'A7XX_PERF_SP_PREDICT_NOT_TAKEN', 'A7XX_PERF_SP_PREDICT_TAKEN', - 'A7XX_PERF_SP_QUADS', 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', - 'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', - 'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', 'A7XX_PERF_SP_RESERVED_86', - 'A7XX_PERF_SP_RTU_BUSY_CYCLES', - 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', - 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', - 'A7XX_PERF_SP_RTU_L0_HITS', 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', - 'A7XX_PERF_SP_RTU_L0_MISSES', - 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', - 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', - 'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', - 'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', - 'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', - 'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', - 'A7XX_PERF_SP_STALL_CYCLES_RB', 'A7XX_PERF_SP_STALL_CYCLES_TP', - 'A7XX_PERF_SP_STALL_CYCLES_UCHE', - 'A7XX_PERF_SP_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_SP_STARVE_CYCLES_HLSQ', - 'A7XX_PERF_SP_STCHE_MISS_INC_BV', - 'A7XX_PERF_SP_STCHE_MISS_INC_FS', - 'A7XX_PERF_SP_STCHE_MISS_INC_LPAC', - 'A7XX_PERF_SP_STCHE_MISS_INC_VS', - 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', - 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', - 'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_UCHE_READ_TRANS', 'A7XX_PERF_SP_UCHE_WRITE_TRANS', - 'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', - 'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', - 'A7XX_PERF_SP_VS_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', - 'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', - 'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', - 'A7XX_PERF_SP_VS_WAVE_REQ_PENDING', - 'A7XX_PERF_SP_WAVE_ALU_CYCLES', 'A7XX_PERF_SP_WAVE_CONTEXTS', - 'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', - 'A7XX_PERF_SP_WAVE_CSP_CYCLES', 'A7XX_PERF_SP_WAVE_CTRL_CYCLES', - 'A7XX_PERF_SP_WAVE_EFU_CYCLES', 'A7XX_PERF_SP_WAVE_EMIT_CYCLES', - 'A7XX_PERF_SP_WAVE_END_CYCLES', 'A7XX_PERF_SP_WAVE_FETCH_CYCLES', - 'A7XX_PERF_SP_WAVE_HWAVE_SYNC', - 'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', - 'A7XX_PERF_SP_WAVE_IDLE_CYCLES', 'A7XX_PERF_SP_WAVE_INPUT_CYCLES', - 'A7XX_PERF_SP_WAVE_INT_CYCLES', 'A7XX_PERF_SP_WAVE_JOIN_CYCLES', - 'A7XX_PERF_SP_WAVE_LOAD_CYCLES', - 'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', - 'A7XX_PERF_SP_WAVE_NOP_CYCLES', 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', - 'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 'A7XX_PERF_SP_WAVE_SPLIT_CNT', 'A7XX_PERF_SP_WAVE_WAIT_CYCLES', - 'A7XX_PERF_SP_WORKING_EU', 'A7XX_PERF_SP_WORKING_EU_CS_STAGE', - 'A7XX_PERF_SP_WORKING_EU_FS_STAGE', - 'A7XX_PERF_SP_WORKING_EU_VS_STAGE', - 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', - 'A7XX_PERF_TP_BACKEND_WORKING_CYCLES', 'A7XX_PERF_TP_BUSY_CYCLES', - 'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', - 'A7XX_PERF_TP_FILTER_POINT_FP16', - 'A7XX_PERF_TP_FILTER_POINT_FP32', - 'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', - 'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', - 'A7XX_PERF_TP_FLAG_CACHE_MISSES', - 'A7XX_PERF_TP_FLAG_CACHE_REQUESTS', - 'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', - 'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', - 'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', - 'A7XX_PERF_TP_FORMAT_DECOMP_POINT', - 'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_5_COMPRESS_REQS', - 'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', - 'A7XX_PERF_TP_L1_5_L2_REQUESTS', - 'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', - 'A7XX_PERF_TP_L1_BANK_CONFLICT', - 'A7XX_PERF_TP_L1_CACHELINE_MISSES', - 'A7XX_PERF_TP_L1_CACHELINE_REQUESTS', - 'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', - 'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', - 'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', - 'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', - 'A7XX_PERF_TP_LATENCY_CYCLES', 'A7XX_PERF_TP_LATENCY_FIFO_FULL', - 'A7XX_PERF_TP_LATENCY_TRANS', 'A7XX_PERF_TP_NEVER_COUNT', - 'A7XX_PERF_TP_OUTPUT_PIXELS', 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', - 'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', - 'A7XX_PERF_TP_OUTPUT_PIXELS_MIP', - 'A7XX_PERF_TP_OUTPUT_PIXELS_POINT', - 'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', - 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', - 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', - 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', - 'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', 'A7XX_PERF_TP_QUADS_1D', - 'A7XX_PERF_TP_QUADS_2D', 'A7XX_PERF_TP_QUADS_3D', - 'A7XX_PERF_TP_QUADS_ARRAY', 'A7XX_PERF_TP_QUADS_BUFFER', - 'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 'A7XX_PERF_TP_QUADS_CUBE', 'A7XX_PERF_TP_QUADS_GRADIENT', - 'A7XX_PERF_TP_QUADS_OFFSET', 'A7XX_PERF_TP_QUADS_RECEIVED', - 'A7XX_PERF_TP_QUADS_SHADOW', 'A7XX_PERF_TP_RESERVED_100', - 'A7XX_PERF_TP_RESERVED_101', 'A7XX_PERF_TP_RESERVED_102', - 'A7XX_PERF_TP_RESERVED_103', 'A7XX_PERF_TP_RESERVED_104', - 'A7XX_PERF_TP_RESERVED_105', 'A7XX_PERF_TP_RESERVED_106', - 'A7XX_PERF_TP_RESERVED_107', 'A7XX_PERF_TP_RESERVED_108', - 'A7XX_PERF_TP_RESERVED_109', 'A7XX_PERF_TP_RESERVED_110', - 'A7XX_PERF_TP_RESERVED_111', 'A7XX_PERF_TP_RESERVED_112', - 'A7XX_PERF_TP_RESERVED_113', 'A7XX_PERF_TP_RESERVED_114', - 'A7XX_PERF_TP_RESERVED_115', 'A7XX_PERF_TP_RESERVED_116', - 'A7XX_PERF_TP_RESERVED_117', 'A7XX_PERF_TP_RESERVED_118', - 'A7XX_PERF_TP_RESERVED_119', 'A7XX_PERF_TP_RESERVED_120', - 'A7XX_PERF_TP_RESERVED_121', 'A7XX_PERF_TP_RESERVED_122', - 'A7XX_PERF_TP_RESERVED_123', 'A7XX_PERF_TP_RESERVED_124', - 'A7XX_PERF_TP_RESERVED_125', 'A7XX_PERF_TP_RESERVED_126', - 'A7XX_PERF_TP_RESERVED_127', 'A7XX_PERF_TP_RESERVED_62', - 'A7XX_PERF_TP_RESERVED_63', 'A7XX_PERF_TP_RESERVED_64', - 'A7XX_PERF_TP_RESERVED_65', 'A7XX_PERF_TP_RESERVED_66', - 'A7XX_PERF_TP_RESERVED_67', 'A7XX_PERF_TP_RESERVED_68', - 'A7XX_PERF_TP_RESERVED_69', 'A7XX_PERF_TP_RESERVED_70', - 'A7XX_PERF_TP_RESERVED_71', 'A7XX_PERF_TP_RESERVED_72', - 'A7XX_PERF_TP_RESERVED_73', 'A7XX_PERF_TP_RESERVED_74', - 'A7XX_PERF_TP_RESERVED_75', 'A7XX_PERF_TP_RESERVED_76', - 'A7XX_PERF_TP_RESERVED_77', 'A7XX_PERF_TP_RESERVED_78', - 'A7XX_PERF_TP_RESERVED_79', 'A7XX_PERF_TP_RESERVED_80', - 'A7XX_PERF_TP_RESERVED_81', 'A7XX_PERF_TP_RESERVED_82', - 'A7XX_PERF_TP_RESERVED_83', 'A7XX_PERF_TP_RESERVED_84', - 'A7XX_PERF_TP_RESERVED_85', 'A7XX_PERF_TP_RESERVED_86', - 'A7XX_PERF_TP_RESERVED_87', 'A7XX_PERF_TP_RESERVED_88', - 'A7XX_PERF_TP_RESERVED_89', 'A7XX_PERF_TP_RESERVED_90', - 'A7XX_PERF_TP_RESERVED_91', 'A7XX_PERF_TP_RESERVED_92', - 'A7XX_PERF_TP_RESERVED_93', 'A7XX_PERF_TP_RESERVED_94', - 'A7XX_PERF_TP_RESERVED_95', 'A7XX_PERF_TP_RESERVED_96', - 'A7XX_PERF_TP_RESERVED_97', 'A7XX_PERF_TP_RESERVED_98', - 'A7XX_PERF_TP_RESERVED_99', 'A7XX_PERF_TP_SP_TP_TRANS', - 'A7XX_PERF_TP_STALL_CYCLES_UCHE', 'A7XX_PERF_TP_STALL_CYCLES_UFC', - 'A7XX_PERF_TP_STARVE_CYCLES_SP', - 'A7XX_PERF_TP_STARVE_CYCLES_UCHE', 'A7XX_PERF_TP_TPA2TPC_TRANS', - 'A7XX_PERF_TP_TP_SP_TRANS', 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', - 'A7XX_PERF_TSE_BE_2D_INPUT_PRIM', - 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', - 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', - 'A7XX_PERF_TSE_BE_BUSY_CYCLES', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', - 'A7XX_PERF_TSE_BE_CINVOCATION', 'A7XX_PERF_TSE_BE_CLIPPED_PRIM', - 'A7XX_PERF_TSE_BE_CLIPPING_CYCLES', - 'A7XX_PERF_TSE_BE_CLIP_PLANES', 'A7XX_PERF_TSE_BE_CPRIMITIVES', - 'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', - 'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', - 'A7XX_PERF_TSE_BE_EXCLUDED_PRIM', - 'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', - 'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', - 'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_BE_INPUT_PRIM', - 'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', - 'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', - 'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', - 'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', - 'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', - 'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', - 'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', - 'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', - 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', - 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', - 'A7XX_PERF_TSE_FE_BUSY_CYCLES', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', - 'A7XX_PERF_TSE_FE_CINVOCATION', 'A7XX_PERF_TSE_FE_CLIP_PLANES', - 'A7XX_PERF_TSE_FE_CPRIMITIVES', - 'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', - 'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', - 'A7XX_PERF_TSE_FE_EXCLUDED_PRIM', - 'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', - 'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', - 'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_FE_INPUT_PRIM', - 'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', - 'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', - 'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', - 'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', - 'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', - 'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', - 'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', - 'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', 'A7XX_PERF_TSE_NEVER_COUNT', - 'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', - 'A7XX_PERF_UCHE_BANK_REQ0', 'A7XX_PERF_UCHE_BANK_REQ1', - 'A7XX_PERF_UCHE_BANK_REQ2', 'A7XX_PERF_UCHE_BANK_REQ3', - 'A7XX_PERF_UCHE_BANK_REQ4', 'A7XX_PERF_UCHE_BANK_REQ5', - 'A7XX_PERF_UCHE_BANK_REQ6', 'A7XX_PERF_UCHE_BANK_REQ7', - 'A7XX_PERF_UCHE_BUSY_CYCLES', - 'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', - 'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', - 'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', - 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', - 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', - 'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', - 'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', 'A7XX_PERF_UCHE_EVICTS', - 'A7XX_PERF_UCHE_EVICTS_LRZ', 'A7XX_PERF_UCHE_EVICTS_SP', - 'A7XX_PERF_UCHE_GMEM_READ_BEATS', - 'A7XX_PERF_UCHE_GMEM_WRITE_BEATS', - 'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', - 'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', - 'A7XX_PERF_UCHE_NEVER_COUNT', 'A7XX_PERF_UCHE_RAM_READ_REQ', - 'A7XX_PERF_UCHE_RAM_WRITE_REQ', - 'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', - 'A7XX_PERF_UCHE_READ_REQUESTS_LRZ', - 'A7XX_PERF_UCHE_READ_REQUESTS_PC', - 'A7XX_PERF_UCHE_READ_REQUESTS_SP', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', - 'A7XX_PERF_UCHE_READ_REQUESTS_VPC', - 'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', - 'A7XX_PERF_UCHE_RESERVED_100', 'A7XX_PERF_UCHE_RESERVED_101', - 'A7XX_PERF_UCHE_RESERVED_102', 'A7XX_PERF_UCHE_RESERVED_103', - 'A7XX_PERF_UCHE_RESERVED_104', 'A7XX_PERF_UCHE_RESERVED_105', - 'A7XX_PERF_UCHE_RESERVED_106', 'A7XX_PERF_UCHE_RESERVED_107', - 'A7XX_PERF_UCHE_RESERVED_108', 'A7XX_PERF_UCHE_RESERVED_109', - 'A7XX_PERF_UCHE_RESERVED_110', 'A7XX_PERF_UCHE_RESERVED_111', - 'A7XX_PERF_UCHE_RESERVED_112', 'A7XX_PERF_UCHE_RESERVED_113', - 'A7XX_PERF_UCHE_RESERVED_114', 'A7XX_PERF_UCHE_RESERVED_115', - 'A7XX_PERF_UCHE_RESERVED_116', 'A7XX_PERF_UCHE_RESERVED_117', - 'A7XX_PERF_UCHE_RESERVED_118', 'A7XX_PERF_UCHE_RESERVED_119', - 'A7XX_PERF_UCHE_RESERVED_120', 'A7XX_PERF_UCHE_RESERVED_121', - 'A7XX_PERF_UCHE_RESERVED_122', 'A7XX_PERF_UCHE_RESERVED_123', - 'A7XX_PERF_UCHE_RESERVED_124', 'A7XX_PERF_UCHE_RESERVED_125', - 'A7XX_PERF_UCHE_RESERVED_126', 'A7XX_PERF_UCHE_RESERVED_127', - 'A7XX_PERF_UCHE_RESERVED_75', 'A7XX_PERF_UCHE_RESERVED_76', - 'A7XX_PERF_UCHE_RESERVED_77', 'A7XX_PERF_UCHE_RESERVED_78', - 'A7XX_PERF_UCHE_RESERVED_79', 'A7XX_PERF_UCHE_RESERVED_80', - 'A7XX_PERF_UCHE_RESERVED_81', 'A7XX_PERF_UCHE_RESERVED_82', - 'A7XX_PERF_UCHE_RESERVED_83', 'A7XX_PERF_UCHE_RESERVED_84', - 'A7XX_PERF_UCHE_RESERVED_85', 'A7XX_PERF_UCHE_RESERVED_86', - 'A7XX_PERF_UCHE_RESERVED_87', 'A7XX_PERF_UCHE_RESERVED_88', - 'A7XX_PERF_UCHE_RESERVED_89', 'A7XX_PERF_UCHE_RESERVED_90', - 'A7XX_PERF_UCHE_RESERVED_91', 'A7XX_PERF_UCHE_RESERVED_92', - 'A7XX_PERF_UCHE_RESERVED_93', 'A7XX_PERF_UCHE_RESERVED_94', - 'A7XX_PERF_UCHE_RESERVED_95', 'A7XX_PERF_UCHE_RESERVED_96', - 'A7XX_PERF_UCHE_RESERVED_97', 'A7XX_PERF_UCHE_RESERVED_98', - 'A7XX_PERF_UCHE_RESERVED_99', - 'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', - 'A7XX_PERF_UCHE_STALL_CYCLES_DECMP', - 'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', - 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', - 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', - 'A7XX_PERF_UCHE_TPH_EXT_FULL', 'A7XX_PERF_UCHE_TPH_REF_FULL', - 'A7XX_PERF_UCHE_TPH_VICTIM_FULL', - 'A7XX_PERF_UCHE_UBWC_READ_BEATS', - 'A7XX_PERF_UCHE_UBWC_WRITE_BEATS', - 'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', - 'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', - 'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', - 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', - 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_SP', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', 'A7XX_PERF_UFC_BUSY_CYCLES', - 'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_SP_FILTER_HIT', - 'A7XX_PERF_UFC_L0_SP_FILTER_MISS', 'A7XX_PERF_UFC_L0_SP_REQUESTS', - 'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', - 'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', - 'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_CRE_FILTER_HIT', - 'A7XX_PERF_UFC_L1_CRE_FILTER_MISS', - 'A7XX_PERF_UFC_L1_CRE_REQUESTS', - 'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_SP_FILTER_HIT', - 'A7XX_PERF_UFC_L1_SP_FILTER_MISS', 'A7XX_PERF_UFC_L1_SP_REQUESTS', - 'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', - 'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', - 'A7XX_PERF_UFC_LOCK_STALLED_CYCLES', - 'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', - 'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', - 'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', - 'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', - 'A7XX_PERF_UFC_MAIN_TP_RD_NRDY', 'A7XX_PERF_UFC_MAIN_TP_RD_RDY', - 'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', - 'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', - 'A7XX_PERF_UFC_MISS_LATENCY_CYCLES', - 'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', 'A7XX_PERF_UFC_NEVER_COUNT', - 'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', - 'A7XX_PERF_UFC_READ_DATA_VBIF', 'A7XX_PERF_UFC_READ_REQUEST_VBIF', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', - 'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', - 'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', - 'A7XX_PERF_UFC_WRITE_DATA_VBIF', - 'A7XX_PERF_UFC_WRITE_REQUEST_VBIF', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', - 'A7XX_PERF_VFDP_STARVE_CYCLES_PC', - 'A7XX_PERF_VFDP_VS_STAGE_WAVES', - 'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', 'A7XX_PERF_VFD_BUSY_CYCLES', - 'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 'A7XX_PERF_VFD_LOWER_SHADER_FIBERS', - 'A7XX_PERF_VFD_MODE_0_FIBERS', 'A7XX_PERF_VFD_MODE_1_FIBERS', - 'A7XX_PERF_VFD_MODE_2_FIBERS', 'A7XX_PERF_VFD_MODE_3_FIBERS', - 'A7XX_PERF_VFD_MODE_4_FIBERS', 'A7XX_PERF_VFD_NEVER_COUNT', - 'A7XX_PERF_VFD_NUM_ATTRIBUTES', 'A7XX_PERF_VFD_RBUFFER_FULL', - 'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', - 'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', - 'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', - 'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', - 'A7XX_PERF_VFD_STALL_CYCLES_UCHE', - 'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 'A7XX_PERF_VFD_STARVE_CYCLES_UCHE', - 'A7XX_PERF_VFD_TOTAL_VERTICES', - 'A7XX_PERF_VFD_UPPER_SHADER_FIBERS', 'A7XX_PERF_VHUB_PTABLE_FULL', - 'A7XX_PERF_VPC_BE_BOTTLENECK', 'A7XX_PERF_VPC_BE_BUSY_CYCLES', - 'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', - 'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', - 'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', - 'A7XX_PERF_VPC_BE_LM_TRANSACTION', - 'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', - 'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', - 'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', 'A7XX_PERF_VPC_BE_NUM_PA_REQ', - 'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', - 'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', - 'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', - 'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', - 'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', - 'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', - 'A7XX_PERF_VPC_BE_WORKING_CYCLES', 'A7XX_PERF_VPC_FE_BOTTLENECK', - 'A7XX_PERF_VPC_FE_BUSY_CYCLES', - 'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_GS_PRIMITIVES', - 'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', - 'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', - 'A7XX_PERF_VPC_FE_NUM_WM_HIT', 'A7XX_PERF_VPC_FE_PC_PRIMITIVES', - 'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_SP_COMPONENTS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', - 'A7XX_PERF_VPC_FE_STALL_DQ_WACK', - 'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', - 'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', - 'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', - 'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', - 'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', - 'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_WORKING_CYCLES', 'A7XX_PERF_VPC_NEVER_COUNT', - 'A7XX_PERF_VPC_RESERVED_42', 'A7XX_PERF_VPC_RESERVED_43', - 'A7XX_PERF_VPC_RESERVED_44', 'A7XX_PERF_VPC_US_BOTTLENECK', - 'A7XX_PERF_VPC_US_BUSY_CYCLES', - 'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', - 'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', 'A7XX_PERF_VPC_US_PTUS_FULL', - 'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', - 'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', - 'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_VPC_US_STALL_CYCLES_VSC', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', - 'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', - 'A7XX_PERF_VPC_US_WORKING_CYCLES', 'A7XX_PERF_VSC_BUSY_CYCLES', - 'A7XX_PERF_VSC_EOT_NUM', 'A7XX_PERF_VSC_INPUT_TILES', - 'A7XX_PERF_VSC_NEVER_COUNT', 'A7XX_PERF_VSC_STALL_CYCLES_UCHE', - 'A7XX_PERF_VSC_TILE_BYPASS_TRAN', 'A7XX_PERF_VSC_TILE_COMP_TRAN', - 'A7XX_PERF_VSC_WORKING_CYCLES', 'A7XX_PIPE_BR', 'A7XX_PIPE_BV', - 'A7XX_PIPE_LPAC', 'A7XX_PIPE_NONE', - 'A7XX_RBBM_CGC_P2S_STATUS_TXDONE', - 'A7XX_RB_BIN_CONTROL_BINH__MASK', - 'A7XX_RB_BIN_CONTROL_BINH__SHIFT', - 'A7XX_RB_BIN_CONTROL_BINW__MASK', - 'A7XX_RB_BIN_CONTROL_BINW__SHIFT', - 'A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK', - 'A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT', - 'A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE', - 'A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE', - 'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN', - 'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT', - 'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN', - 'A7XX_RB_MRT_BUF_INFO_UNK10', 'A7XX_RB_RENDER_CNTL_BINNING', - 'A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN', - 'A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN', - 'A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN', - 'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK', - 'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT', - 'A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK', - 'A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT', - 'A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL', - 'A7XX_RB_STENCIL_INFO_TILEMODE__MASK', - 'A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT', - 'A7XX_RB_STENCIL_INFO_UNK1', 'A7XX_RB_UNKNOWN_88E4_UNK0', - 'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK', - 'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT', - 'A7XX_SP_2D_DST_FORMAT_MASK__MASK', - 'A7XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A7XX_SP_2D_DST_FORMAT_NORM', - 'A7XX_SP_2D_DST_FORMAT_SINT', 'A7XX_SP_2D_DST_FORMAT_SRGB', - 'A7XX_SP_2D_DST_FORMAT_UINT', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A7XX_SP_CB_RAM', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR', - 'A7XX_SP_CS_CNTL_1_THREADSIZE__MASK', - 'A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT', 'A7XX_SP_CS_CNTL_1_UNK15', - 'A7XX_SP_CTX0_3D_CPS_REG', 'A7XX_SP_CTX0_3D_CVS_REG', - 'A7XX_SP_CTX1_3D_CPS_REG', 'A7XX_SP_CTX1_3D_CVS_REG', - 'A7XX_SP_CTX2_3D_CPS_REG', 'A7XX_SP_CTX3_3D_CPS_REG', - 'A7XX_SP_FS_PREFETCH_CMD_BINDLESS', - 'A7XX_SP_FS_PREFETCH_CMD_CMD__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_DST__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_HALF', - 'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_SRC__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT', 'A7XX_SP_HWAVE_RAM', - 'A7XX_SP_INST_DATA', 'A7XX_SP_INST_DATA_1', 'A7XX_SP_INST_DATA_2', - 'A7XX_SP_INST_TAG', 'A7XX_SP_L0_INST_BUF', 'A7XX_SP_LB_0_DATA', - 'A7XX_SP_LB_10_DATA', 'A7XX_SP_LB_11_DATA', 'A7XX_SP_LB_12_DATA', - 'A7XX_SP_LB_13_DATA', 'A7XX_SP_LB_14_DATA', 'A7XX_SP_LB_1_DATA', - 'A7XX_SP_LB_2_DATA', 'A7XX_SP_LB_3_DATA', 'A7XX_SP_LB_4_DATA', - 'A7XX_SP_LB_5_DATA', 'A7XX_SP_LB_6_DATA', 'A7XX_SP_LB_7_DATA', - 'A7XX_SP_LB_8_DATA', 'A7XX_SP_LB_9_DATA', 'A7XX_SP_NCTX_REG', - 'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_FILTER', 'A7XX_SP_PS_2D_SRC_INFO_FLAGS', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_SRGB', - 'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_UNK17', 'A7XX_SP_PS_2D_SRC_INFO_UNK19', - 'A7XX_SP_PS_2D_SRC_INFO_UNK20', 'A7XX_SP_PS_2D_SRC_INFO_UNK21', - 'A7XX_SP_PS_2D_SRC_INFO_UNK22', - 'A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_UNK28', - 'A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK', - 'A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT', - 'A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK', - 'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT', - 'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK', - 'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT', - 'A7XX_SP_READ_SEL_LOCATION__MASK', - 'A7XX_SP_READ_SEL_LOCATION__SHIFT', 'A7XX_SP_READ_SEL_PIPE__MASK', - 'A7XX_SP_READ_SEL_PIPE__SHIFT', 'A7XX_SP_READ_SEL_SPTP__MASK', - 'A7XX_SP_READ_SEL_SPTP__SHIFT', - 'A7XX_SP_READ_SEL_STATETYPE__MASK', - 'A7XX_SP_READ_SEL_STATETYPE__SHIFT', - 'A7XX_SP_READ_SEL_USPTP__MASK', 'A7XX_SP_READ_SEL_USPTP__SHIFT', - 'A7XX_SP_SMO_TAG', 'A7XX_SP_STATE_DATA', 'A7XX_SP_TMO_TAG', - 'A7XX_SP_TOP', 'A7XX_SP_WINDOW_OFFSET_X__MASK', - 'A7XX_SP_WINDOW_OFFSET_X__SHIFT', 'A7XX_SP_WINDOW_OFFSET_Y__MASK', - 'A7XX_SP_WINDOW_OFFSET_Y__SHIFT', 'A7XX_TP0_CTX0_3D_CPS_REG', - 'A7XX_TP0_CTX0_3D_CVS_REG', 'A7XX_TP0_CTX1_3D_CPS_REG', - 'A7XX_TP0_CTX1_3D_CVS_REG', 'A7XX_TP0_CTX2_3D_CPS_REG', - 'A7XX_TP0_CTX3_3D_CPS_REG', 'A7XX_TP0_MIPMAP_BASE_DATA', - 'A7XX_TP0_NCTX_REG', 'A7XX_TP0_SMO_DATA', 'A7XX_TP0_TMO_DATA', - 'A7XX_USPTP', 'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK', - 'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT', - 'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK', - 'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT', - 'A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A7XX_VPC_MULTIVIEW_CNTL_ENABLE', - 'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK', - 'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A7XX_VPC_POLYGON_MODE2_MODE__MASK', - 'A7XX_VPC_POLYGON_MODE2_MODE__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING', - 'A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART', - 'A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST', - 'A7XX_VPC_PRIMITIVE_CNTL_0_UNK3', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN', - 'A7XX_VPC_PRIMITIVE_CNTL_5_UNK18', - 'A7XX_VSC_UNKNOWN_0CD8_BINNING', 'ADDR_32B', 'ADDR_64B', - 'AXXX_CP_CSQ_AVAIL_IB1__MASK', 'AXXX_CP_CSQ_AVAIL_IB1__SHIFT', - 'AXXX_CP_CSQ_AVAIL_IB2__MASK', 'AXXX_CP_CSQ_AVAIL_IB2__SHIFT', - 'AXXX_CP_CSQ_AVAIL_RING__MASK', 'AXXX_CP_CSQ_AVAIL_RING__SHIFT', - 'AXXX_CP_CSQ_IB1_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_IB1_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT', - 'AXXX_CP_CSQ_IB2_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_IB2_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT', - 'AXXX_CP_CSQ_RB_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_RB_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT', - 'AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE', - 'AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE', - 'AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE', - 'AXXX_CP_DEBUG_PREDICATE_DISABLE', - 'AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE', - 'AXXX_CP_DEBUG_PREFETCH_PASS_NOPS', - 'AXXX_CP_DEBUG_PROG_END_PTR_ENABLE', - 'AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL', - 'AXXX_CP_INT_CNTL_IB1_INT_MASK', 'AXXX_CP_INT_CNTL_IB2_INT_MASK', - 'AXXX_CP_INT_CNTL_IB_ERROR_MASK', - 'AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK', - 'AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK', - 'AXXX_CP_INT_CNTL_RB_INT_MASK', - 'AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK', - 'AXXX_CP_INT_CNTL_SW_INT_MASK', - 'AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK', - 'AXXX_CP_MEQ_AVAIL_MEQ__MASK', 'AXXX_CP_MEQ_AVAIL_MEQ__SHIFT', - 'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK', - 'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT', - 'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK', - 'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT', 'AXXX_CP_ME_CNTL_BUSY', - 'AXXX_CP_ME_CNTL_HALT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT', - 'AXXX_CP_RB_CNTL_BLKSZ__MASK', 'AXXX_CP_RB_CNTL_BLKSZ__SHIFT', - 'AXXX_CP_RB_CNTL_BUFSZ__MASK', 'AXXX_CP_RB_CNTL_BUFSZ__SHIFT', - 'AXXX_CP_RB_CNTL_BUF_SWAP__MASK', - 'AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT', 'AXXX_CP_RB_CNTL_NO_UPDATE', - 'AXXX_CP_RB_CNTL_POLL_EN', 'AXXX_CP_RB_CNTL_RPTR_WR_EN', - 'AXXX_CP_RB_RPTR_ADDR_ADDR__MASK', - 'AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT', - 'AXXX_CP_RB_RPTR_ADDR_SWAP__MASK', - 'AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT', - 'AXXX_CP_STAT_CF_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_CP_3D_BUSY', - 'AXXX_CP_STAT_CP_BUSY', 'AXXX_CP_STAT_CP_NRT_BUSY', - 'AXXX_CP_STAT_CSF_BUSY', 'AXXX_CP_STAT_CSF_INDIRECT2_BUSY', - 'AXXX_CP_STAT_CSF_INDIRECTS_BUSY', 'AXXX_CP_STAT_CSF_RING_BUSY', - 'AXXX_CP_STAT_CSF_ST_BUSY', 'AXXX_CP_STAT_EVENT_BUSY', - 'AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY', - 'AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY', 'AXXX_CP_STAT_MEQ_RING_BUSY', - 'AXXX_CP_STAT_ME_BUSY', 'AXXX_CP_STAT_MIU_RD_REQ_BUSY', - 'AXXX_CP_STAT_MIU_RD_RETURN_BUSY', 'AXXX_CP_STAT_MIU_WR_BUSY', - 'AXXX_CP_STAT_MIU_WR_C_BUSY', 'AXXX_CP_STAT_PFP_BUSY', - 'AXXX_CP_STAT_PS_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RBIU_BUSY', - 'AXXX_CP_STAT_RBIU_SCRATCH_BUSY', - 'AXXX_CP_STAT_RB_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RCIU_BUSY', - 'AXXX_CP_STAT_RCIU_ME_BUSY', 'AXXX_CP_STAT_RCIU_PFP_BUSY', - 'AXXX_CP_STAT_RING_QUEUE_BUSY', 'AXXX_CP_STAT_ST_QUEUE_BUSY', - 'AXXX_CP_STAT_VS_EVENT_FIFO_BUSY', 'AXXX_CP_STQ_AVAIL_ST__MASK', - 'AXXX_CP_STQ_AVAIL_ST__SHIFT', 'AXXX_SCRATCH_UMSK_SWAP__MASK', - 'AXXX_SCRATCH_UMSK_SWAP__SHIFT', 'AXXX_SCRATCH_UMSK_UMSK__MASK', - 'AXXX_SCRATCH_UMSK_UMSK__SHIFT', 'BINDLESS_BASE_0_ADDR', - 'BINDLESS_BASE_1_ADDR', 'BINDLESS_BASE_2_ADDR', - 'BINDLESS_BASE_3_ADDR', 'BINDLESS_BASE_4_ADDR', - 'BINDLESS_BASE_5_ADDR', 'BINDLESS_BASE_6_ADDR', - 'BINDLESS_DESCRIPTOR_16B', 'BINDLESS_DESCRIPTOR_64B', 'BINNING', - 'BINNING_PASS', 'BLEND_DST_MINUS_SRC', 'BLEND_DST_PLUS_SRC', - 'BLEND_MAX_DST_SRC', 'BLEND_MIN_DST_SRC', 'BLEND_SRC_MINUS_DST', - 'BLIT', 'BLIT2D', 'BLIT2DSCALE', 'BLIT_OP_COPY', - 'BLIT_OP_COPY_2D', 'BLIT_OP_FILL', 'BLIT_OP_FILL_2D', - 'BLIT_OP_SCALE', 'BLIT_OP_SCALE_2D', 'BRESENHAM', 'BUFFER', - 'BUFFERS_IN_GMEM', 'BUFFERS_IN_SYSMEM', 'BYPASS', 'CACHE', - 'CACHE_CLEAN', 'CACHE_FLUSH', 'CACHE_FLUSH7', - 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', - 'CACHE_FLUSH_TS', 'CACHE_INVALIDATE', 'CACHE_INVALIDATE7', - 'CACHE_RESET', 'CCU_CACHE_SIZE_EIGHTH', 'CCU_CACHE_SIZE_FULL', - 'CCU_CACHE_SIZE_HALF', 'CCU_CACHE_SIZE_QUARTER', - 'CCU_CLEAN_COLOR', 'CCU_CLEAN_DEPTH', 'CCU_END_RESOLVE_GROUP', - 'CCU_FLUSH_COLOR', 'CCU_FLUSH_DEPTH', 'CCU_INVALIDATE_COLOR', - 'CCU_INVALIDATE_DEPTH', 'CCU_RESOLVE', 'CCU_RESOLVE_CLEAN', - 'CONTEXT_DONE', 'CONTEXT_DONE_2D', 'COUNTER', 'CP_BLIT', - 'CP_BLIT_0_OP__MASK', 'CP_BLIT_0_OP__SHIFT', - 'CP_BLIT_1_SRC_X1__MASK', 'CP_BLIT_1_SRC_X1__SHIFT', - 'CP_BLIT_1_SRC_Y1__MASK', 'CP_BLIT_1_SRC_Y1__SHIFT', - 'CP_BLIT_2_SRC_X2__MASK', 'CP_BLIT_2_SRC_X2__SHIFT', - 'CP_BLIT_2_SRC_Y2__MASK', 'CP_BLIT_2_SRC_Y2__SHIFT', - 'CP_BLIT_3_DST_X1__MASK', 'CP_BLIT_3_DST_X1__SHIFT', - 'CP_BLIT_3_DST_Y1__MASK', 'CP_BLIT_3_DST_Y1__SHIFT', - 'CP_BLIT_4_DST_X2__MASK', 'CP_BLIT_4_DST_X2__SHIFT', - 'CP_BLIT_4_DST_Y2__MASK', 'CP_BLIT_4_DST_Y2__SHIFT', - 'CP_BOOTSTRAP_UCODE', 'CP_BV_BR_COUNT_OPS', - 'CP_BV_BR_COUNT_OPS_0_OP__MASK', 'CP_BV_BR_COUNT_OPS_0_OP__SHIFT', - 'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK', - 'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT', 'CP_CCHE_INVALIDATE', - 'CP_COMPUTE_CHECKPOINT', - 'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK', - 'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT', - 'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK', - 'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT', - 'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK', - 'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT', - 'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK', - 'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT', - 'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK', - 'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT', 'CP_COND_EXEC', - 'CP_COND_EXEC_0_ADDR0_LO__MASK', 'CP_COND_EXEC_0_ADDR0_LO__SHIFT', - 'CP_COND_EXEC_1_ADDR0_HI__MASK', 'CP_COND_EXEC_1_ADDR0_HI__SHIFT', - 'CP_COND_EXEC_2_ADDR1_LO__MASK', 'CP_COND_EXEC_2_ADDR1_LO__SHIFT', - 'CP_COND_EXEC_3_ADDR1_HI__MASK', 'CP_COND_EXEC_3_ADDR1_HI__SHIFT', - 'CP_COND_EXEC_4_REF__MASK', 'CP_COND_EXEC_4_REF__SHIFT', - 'CP_COND_EXEC_5_DWORDS__MASK', 'CP_COND_EXEC_5_DWORDS__SHIFT', - 'CP_COND_INDIRECT_BUFFER_PFD', 'CP_COND_INDIRECT_BUFFER_PFE', - 'CP_COND_REG_EXEC', 'CP_COND_REG_EXEC_0_BINNING', - 'CP_COND_REG_EXEC_0_BR', 'CP_COND_REG_EXEC_0_BV', - 'CP_COND_REG_EXEC_0_GMEM', 'CP_COND_REG_EXEC_0_LPAC', - 'CP_COND_REG_EXEC_0_MODE__MASK', 'CP_COND_REG_EXEC_0_MODE__SHIFT', - 'CP_COND_REG_EXEC_0_ONCHIP_MEM', - 'CP_COND_REG_EXEC_0_PRED_BIT__MASK', - 'CP_COND_REG_EXEC_0_PRED_BIT__SHIFT', - 'CP_COND_REG_EXEC_0_REG0__MASK', 'CP_COND_REG_EXEC_0_REG0__SHIFT', - 'CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME', - 'CP_COND_REG_EXEC_0_SYSMEM', 'CP_COND_REG_EXEC_2_DWORDS__MASK', - 'CP_COND_REG_EXEC_2_DWORDS__SHIFT', 'CP_COND_WRITE', - 'CP_COND_WRITE5', 'CP_COND_WRITE5_0_FUNCTION__MASK', - 'CP_COND_WRITE5_0_FUNCTION__SHIFT', 'CP_COND_WRITE5_0_POLL__MASK', - 'CP_COND_WRITE5_0_POLL__SHIFT', 'CP_COND_WRITE5_0_SIGNED_COMPARE', - 'CP_COND_WRITE5_0_WRITE_MEMORY', - 'CP_COND_WRITE5_1_POLL_ADDR_LO__MASK', - 'CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT', - 'CP_COND_WRITE5_2_POLL_ADDR_HI__MASK', - 'CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT', - 'CP_COND_WRITE5_3_REF__MASK', 'CP_COND_WRITE5_3_REF__SHIFT', - 'CP_COND_WRITE5_4_MASK__MASK', 'CP_COND_WRITE5_4_MASK__SHIFT', - 'CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK', - 'CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT', - 'CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK', - 'CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT', - 'CP_COND_WRITE5_7_WRITE_DATA__MASK', - 'CP_COND_WRITE5_7_WRITE_DATA__SHIFT', - 'CP_COND_WRITE_0_FUNCTION__MASK', - 'CP_COND_WRITE_0_FUNCTION__SHIFT', 'CP_COND_WRITE_0_POLL_MEMORY', - 'CP_COND_WRITE_0_WRITE_MEMORY', 'CP_COND_WRITE_1_POLL_ADDR__MASK', - 'CP_COND_WRITE_1_POLL_ADDR__SHIFT', 'CP_COND_WRITE_2_REF__MASK', - 'CP_COND_WRITE_2_REF__SHIFT', 'CP_COND_WRITE_3_MASK__MASK', - 'CP_COND_WRITE_3_MASK__SHIFT', 'CP_COND_WRITE_4_WRITE_ADDR__MASK', - 'CP_COND_WRITE_4_WRITE_ADDR__SHIFT', - 'CP_COND_WRITE_5_WRITE_DATA__MASK', - 'CP_COND_WRITE_5_WRITE_DATA__SHIFT', 'CP_CONTEXT_REG_BUNCH', - 'CP_CONTEXT_REG_BUNCH2', 'CP_CONTEXT_SWITCH', - 'CP_CONTEXT_SWITCH_YIELD', 'CP_CONTEXT_UPDATE', - 'CP_DISPATCH_COMPUTE_1_X__MASK', 'CP_DISPATCH_COMPUTE_1_X__SHIFT', - 'CP_DISPATCH_COMPUTE_2_Y__MASK', 'CP_DISPATCH_COMPUTE_2_Y__SHIFT', - 'CP_DISPATCH_COMPUTE_3_Z__MASK', 'CP_DISPATCH_COMPUTE_3_Z__SHIFT', - 'CP_DRAW_AUTO', 'CP_DRAW_AUTO_0_GS_ENABLE', - 'CP_DRAW_AUTO_0_INDEX_SIZE__MASK', - 'CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT', - 'CP_DRAW_AUTO_0_PATCH_TYPE__MASK', - 'CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT', - 'CP_DRAW_AUTO_0_PRIM_TYPE__MASK', - 'CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT', - 'CP_DRAW_AUTO_0_SOURCE_SELECT__MASK', - 'CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT', - 'CP_DRAW_AUTO_0_TESS_ENABLE', 'CP_DRAW_AUTO_0_VIS_CULL__MASK', - 'CP_DRAW_AUTO_0_VIS_CULL__SHIFT', - 'CP_DRAW_AUTO_1_NUM_INSTANCES__MASK', - 'CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK', - 'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT', - 'CP_DRAW_AUTO_5_STRIDE__MASK', 'CP_DRAW_AUTO_5_STRIDE__SHIFT', - 'CP_DRAW_INDIRECT', 'CP_DRAW_INDIRECT_MULTI', 'CP_DRAW_INDX', - 'CP_DRAW_INDX_0_VIZ_QUERY__MASK', - 'CP_DRAW_INDX_0_VIZ_QUERY__SHIFT', - 'CP_DRAW_INDX_1_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_1_NOT_EOP', - 'CP_DRAW_INDX_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE', - 'CP_DRAW_INDX_1_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_1_PRIM_TYPE__SHIFT', 'CP_DRAW_INDX_1_SMALL_INDEX', - 'CP_DRAW_INDX_1_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_1_VIS_CULL__MASK', 'CP_DRAW_INDX_1_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_2', 'CP_DRAW_INDX_2_0_VIZ_QUERY__MASK', - 'CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT', - 'CP_DRAW_INDX_2_1_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_2_1_NOT_EOP', - 'CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE', - 'CP_DRAW_INDX_2_1_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT', - 'CP_DRAW_INDX_2_1_SMALL_INDEX', - 'CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_2_1_VIS_CULL__MASK', - 'CP_DRAW_INDX_2_1_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_2_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT', 'CP_DRAW_INDX_2_BIN', - 'CP_DRAW_INDX_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_2_NUM_INDICES__SHIFT', - 'CP_DRAW_INDX_3_INDX_BASE__MASK', - 'CP_DRAW_INDX_3_INDX_BASE__SHIFT', - 'CP_DRAW_INDX_4_INDX_SIZE__MASK', - 'CP_DRAW_INDX_4_INDX_SIZE__SHIFT', 'CP_DRAW_INDX_BIN', - 'CP_DRAW_INDX_INDIRECT', 'CP_DRAW_INDX_OFFSET', - 'CP_DRAW_INDX_OFFSET_0_GS_ENABLE', - 'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK', - 'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_TESS_ENABLE', - 'CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK', - 'CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT', - 'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK', - 'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT', - 'CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK', - 'CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT', - 'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK', - 'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT', - 'CP_DRAW_PRED_ENABLE_GLOBAL', - 'CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE', - 'CP_DRAW_PRED_ENABLE_LOCAL', 'CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE', - 'CP_DRAW_PRED_SET', 'CP_DRAW_PRED_SET_0_SRC__MASK', - 'CP_DRAW_PRED_SET_0_SRC__SHIFT', 'CP_DRAW_PRED_SET_0_TEST__MASK', - 'CP_DRAW_PRED_SET_0_TEST__SHIFT', 'CP_END_BIN', 'CP_EVENT_WRITE', - 'CP_EVENT_WRITE7', 'CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE', - 'CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE', - 'CP_EVENT_WRITE7_0_EVENT__MASK', 'CP_EVENT_WRITE7_0_EVENT__SHIFT', - 'CP_EVENT_WRITE7_0_INC_BR_COUNT', - 'CP_EVENT_WRITE7_0_INC_BV_COUNT', - 'CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET', - 'CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF', - 'CP_EVENT_WRITE7_0_WRITE_DST__MASK', - 'CP_EVENT_WRITE7_0_WRITE_DST__SHIFT', - 'CP_EVENT_WRITE7_0_WRITE_ENABLED', - 'CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT', - 'CP_EVENT_WRITE7_0_WRITE_SRC__MASK', - 'CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT', - 'CP_EVENT_WRITE_0_EVENT__MASK', 'CP_EVENT_WRITE_0_EVENT__SHIFT', - 'CP_EVENT_WRITE_0_IRQ', 'CP_EVENT_WRITE_0_TIMESTAMP', - 'CP_EVENT_WRITE_1_ADDR_0_LO__MASK', - 'CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT', - 'CP_EVENT_WRITE_2_ADDR_0_HI__MASK', - 'CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT', 'CP_EVENT_WRITE_CFL', - 'CP_EVENT_WRITE_SHD', 'CP_EVENT_WRITE_ZPD', 'CP_EXEC_CS', - 'CP_EXEC_CS_1_NGROUPS_X__MASK', 'CP_EXEC_CS_1_NGROUPS_X__SHIFT', - 'CP_EXEC_CS_2_NGROUPS_Y__MASK', 'CP_EXEC_CS_2_NGROUPS_Y__SHIFT', - 'CP_EXEC_CS_3_NGROUPS_Z__MASK', 'CP_EXEC_CS_3_NGROUPS_Z__SHIFT', - 'CP_EXEC_CS_INDIRECT', 'CP_FIXED_STRIDE_DRAW_TABLE', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT', - 'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT', - 'CP_GLOBAL_TIMESTAMP', 'CP_IM_LOAD', 'CP_IM_LOAD_IMMEDIATE', - 'CP_IM_STORE', 'CP_INDIRECT_BUFFER', 'CP_INDIRECT_BUFFER_CHAIN', - 'CP_INDIRECT_BUFFER_PFD', 'CP_INDIRECT_BUFFER_PFE', - 'CP_INTERRUPT', 'CP_INVALIDATE_STATE', 'CP_LOAD_CONSTANT_CONTEXT', - 'CP_LOAD_STATE', 'CP_LOAD_STATE4', - 'CP_LOAD_STATE4_0_DST_OFF__MASK', - 'CP_LOAD_STATE4_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE4_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE4_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE4_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE4_0_STATE_SRC__MASK', - 'CP_LOAD_STATE4_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE4_1_STATE_TYPE__MASK', - 'CP_LOAD_STATE4_1_STATE_TYPE__SHIFT', - 'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK', - 'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6', - 'CP_LOAD_STATE6_0_DST_OFF__MASK', - 'CP_LOAD_STATE6_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE6_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE6_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE6_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE6_0_STATE_SRC__MASK', - 'CP_LOAD_STATE6_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE6_0_STATE_TYPE__MASK', - 'CP_LOAD_STATE6_0_STATE_TYPE__SHIFT', - 'CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK', - 'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6_FRAG', - 'CP_LOAD_STATE6_GEOM', 'CP_LOAD_STATE_0_DST_OFF__MASK', - 'CP_LOAD_STATE_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE_0_STATE_SRC__MASK', - 'CP_LOAD_STATE_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE_1_STATE_TYPE__MASK', - 'CP_LOAD_STATE_1_STATE_TYPE__SHIFT', 'CP_LOCAL_TIMESTAMP', - 'CP_MEMCPY', 'CP_MEMCPY_0_DWORDS__MASK', - 'CP_MEMCPY_0_DWORDS__SHIFT', 'CP_MEMCPY_1_SRC_LO__MASK', - 'CP_MEMCPY_1_SRC_LO__SHIFT', 'CP_MEMCPY_2_SRC_HI__MASK', - 'CP_MEMCPY_2_SRC_HI__SHIFT', 'CP_MEMCPY_3_DST_LO__MASK', - 'CP_MEMCPY_3_DST_LO__SHIFT', 'CP_MEMCPY_4_DST_HI__MASK', - 'CP_MEMCPY_4_DST_HI__SHIFT', 'CP_MEM_TO_MEM', - 'CP_MEM_TO_MEM_0_DOUBLE', 'CP_MEM_TO_MEM_0_NEG_A', - 'CP_MEM_TO_MEM_0_NEG_B', 'CP_MEM_TO_MEM_0_NEG_C', - 'CP_MEM_TO_MEM_0_UNK31', 'CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES', - 'CP_MEM_TO_REG', 'CP_MEM_TO_REG_0_CNT__MASK', - 'CP_MEM_TO_REG_0_CNT__SHIFT', 'CP_MEM_TO_REG_0_REG__MASK', - 'CP_MEM_TO_REG_0_REG__SHIFT', 'CP_MEM_TO_REG_0_SHIFT_BY_2', - 'CP_MEM_TO_REG_0_UNK31', 'CP_MEM_TO_REG_1_SRC__MASK', - 'CP_MEM_TO_REG_1_SRC__SHIFT', 'CP_MEM_TO_REG_2_SRC_HI__MASK', - 'CP_MEM_TO_REG_2_SRC_HI__SHIFT', 'CP_MEM_TO_SCRATCH_MEM', - 'CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK', - 'CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK', - 'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK', - 'CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK', - 'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT', 'CP_MEM_WRITE', - 'CP_MEM_WRITE_0_ADDR_LO__MASK', 'CP_MEM_WRITE_0_ADDR_LO__SHIFT', - 'CP_MEM_WRITE_1_ADDR_HI__MASK', 'CP_MEM_WRITE_1_ADDR_HI__SHIFT', - 'CP_MEM_WRITE_CNTR', 'CP_ME_INIT', 'CP_MODIFY_TIMESTAMP', - 'CP_MODIFY_TIMESTAMP_0_ADD__MASK', - 'CP_MODIFY_TIMESTAMP_0_ADD__SHIFT', - 'CP_MODIFY_TIMESTAMP_0_OP__MASK', - 'CP_MODIFY_TIMESTAMP_0_OP__SHIFT', 'CP_NOP', - 'CP_PERFCOUNTER_ACTION', - 'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK', - 'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT', - 'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK', - 'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT', 'CP_PREEMPT_DISABLE', - 'CP_PREEMPT_ENABLE', 'CP_PREEMPT_ENABLE_GLOBAL', - 'CP_PREEMPT_ENABLE_LOCAL', 'CP_PREEMPT_TOKEN', - 'CP_RECORD_PFP_TIMESTAMP', 'CP_REG_RMW', - 'CP_REG_RMW_0_DST_REG__MASK', 'CP_REG_RMW_0_DST_REG__SHIFT', - 'CP_REG_RMW_0_ROTATE__MASK', 'CP_REG_RMW_0_ROTATE__SHIFT', - 'CP_REG_RMW_0_SRC0_IS_REG', 'CP_REG_RMW_0_SRC1_ADD', - 'CP_REG_RMW_0_SRC1_IS_REG', 'CP_REG_RMW_1_SRC0__MASK', - 'CP_REG_RMW_1_SRC0__SHIFT', 'CP_REG_RMW_2_SRC1__MASK', - 'CP_REG_RMW_2_SRC1__SHIFT', 'CP_REG_TEST', 'CP_REG_TO_MEM', - 'CP_REG_TO_MEM_0_64B', 'CP_REG_TO_MEM_0_ACCUMULATE', - 'CP_REG_TO_MEM_0_CNT__MASK', 'CP_REG_TO_MEM_0_CNT__SHIFT', - 'CP_REG_TO_MEM_0_REG__MASK', 'CP_REG_TO_MEM_0_REG__SHIFT', - 'CP_REG_TO_MEM_1_DEST__MASK', 'CP_REG_TO_MEM_1_DEST__SHIFT', - 'CP_REG_TO_MEM_2_DEST_HI__MASK', 'CP_REG_TO_MEM_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM', 'CP_REG_TO_MEM_OFFSET_MEM_0_64B', - 'CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE', - 'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG', 'CP_REG_TO_MEM_OFFSET_REG_0_64B', - 'CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE', - 'CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT', 'CP_REG_TO_SCRATCH', - 'CP_REG_TO_SCRATCH_0_CNT__MASK', 'CP_REG_TO_SCRATCH_0_CNT__SHIFT', - 'CP_REG_TO_SCRATCH_0_REG__MASK', 'CP_REG_TO_SCRATCH_0_REG__SHIFT', - 'CP_REG_TO_SCRATCH_0_SCRATCH__MASK', - 'CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT', 'CP_REG_WRITE', - 'CP_REG_WRITE_0_TRACKER__MASK', 'CP_REG_WRITE_0_TRACKER__SHIFT', - 'CP_REG_WR_NO_CTXT', 'CP_RESET_CONTEXT_STATE', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE', - 'CP_RESOURCE_LIST', 'CP_RUN_OPENCL', 'CP_SCRATCH_TO_REG', - 'CP_SCRATCH_TO_REG_0_CNT__MASK', 'CP_SCRATCH_TO_REG_0_CNT__SHIFT', - 'CP_SCRATCH_TO_REG_0_REG__MASK', 'CP_SCRATCH_TO_REG_0_REG__SHIFT', - 'CP_SCRATCH_TO_REG_0_SCRATCH__MASK', - 'CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT', 'CP_SCRATCH_TO_REG_0_UNK18', - 'CP_SCRATCH_WRITE', 'CP_SCRATCH_WRITE_0_SCRATCH__MASK', - 'CP_SCRATCH_WRITE_0_SCRATCH__SHIFT', 'CP_SET_BIN', - 'CP_SET_BIN_1_X1__MASK', 'CP_SET_BIN_1_X1__SHIFT', - 'CP_SET_BIN_1_Y1__MASK', 'CP_SET_BIN_1_Y1__SHIFT', - 'CP_SET_BIN_2_X2__MASK', 'CP_SET_BIN_2_X2__SHIFT', - 'CP_SET_BIN_2_Y2__MASK', 'CP_SET_BIN_2_Y2__SHIFT', - 'CP_SET_BIN_DATA', 'CP_SET_BIN_DATA5', - 'CP_SET_BIN_DATA5_0_VSC_N__MASK', - 'CP_SET_BIN_DATA5_0_VSC_N__SHIFT', - 'CP_SET_BIN_DATA5_0_VSC_SIZE__MASK', - 'CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT', - 'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK', - 'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT', - 'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK', - 'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT', - 'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK', - 'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT', - 'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK', - 'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT', - 'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK', - 'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT', - 'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK', - 'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT', - 'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK', - 'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT', - 'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK', - 'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT', 'CP_SET_BIN_MASK', - 'CP_SET_BIN_SELECT', 'CP_SET_CONSTANT', 'CP_SET_CTXSWITCH_IB', - 'CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK', - 'CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT', - 'CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK', - 'CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT', - 'CP_SET_CTXSWITCH_IB_2_DWORDS__MASK', - 'CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT', - 'CP_SET_CTXSWITCH_IB_2_TYPE__MASK', - 'CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT', 'CP_SET_DRAW_INIT_FLAGS', - 'CP_SET_DRAW_STATE', 'CP_SET_DRAW_STATE__0_BINNING', - 'CP_SET_DRAW_STATE__0_COUNT__MASK', - 'CP_SET_DRAW_STATE__0_COUNT__SHIFT', 'CP_SET_DRAW_STATE__0_DIRTY', - 'CP_SET_DRAW_STATE__0_DISABLE', - 'CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS', - 'CP_SET_DRAW_STATE__0_GMEM', - 'CP_SET_DRAW_STATE__0_GROUP_ID__MASK', - 'CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT', - 'CP_SET_DRAW_STATE__0_LOAD_IMMED', 'CP_SET_DRAW_STATE__0_SYSMEM', - 'CP_SET_DRAW_STATE__1_ADDR_LO__MASK', - 'CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT', - 'CP_SET_DRAW_STATE__2_ADDR_HI__MASK', - 'CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT', 'CP_SET_MARKER', - 'CP_SET_MODE', 'CP_SET_PROTECTED_MODE', 'CP_SET_PSEUDO_REG', - 'CP_SET_RENDER_MODE', 'CP_SET_RENDER_MODE_0_MODE__MASK', - 'CP_SET_RENDER_MODE_0_MODE__SHIFT', - 'CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK', - 'CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT', - 'CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK', - 'CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT', - 'CP_SET_RENDER_MODE_3_GMEM_ENABLE', - 'CP_SET_RENDER_MODE_3_VSC_ENABLE', - 'CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK', - 'CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT', - 'CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK', - 'CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT', - 'CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK', - 'CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT', 'CP_SET_SECURE_MODE', - 'CP_SET_SHADER_BASES', 'CP_SET_STATE', 'CP_SET_SUBDRAW_SIZE', - 'CP_SET_THREAD_BOTH', 'CP_SET_THREAD_BR', 'CP_SET_THREAD_BV', - 'CP_SET_UNK_BIN_DATA', 'CP_SET_VISIBILITY_OVERRIDE', - 'CP_SKIP_IB2_ENABLE_GLOBAL', 'CP_SKIP_IB2_ENABLE_LOCAL', - 'CP_SMMU_TABLE_UPDATE', 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK', - 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT', - 'CP_SMMU_TABLE_UPDATE_1_ASID__MASK', - 'CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT', - 'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK', - 'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT', - 'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK', - 'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT', - 'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK', - 'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT', 'CP_START_BIN', - 'CP_TEST_TWO_MEMS', 'CP_THREAD_CONTROL', - 'CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE', - 'CP_THREAD_CONTROL_0_SYNC_THREADS', - 'CP_THREAD_CONTROL_0_THREAD__MASK', - 'CP_THREAD_CONTROL_0_THREAD__SHIFT', 'CP_TYPE0_PKT', - 'CP_TYPE1_PKT', 'CP_TYPE2_PKT', 'CP_TYPE3_PKT', 'CP_TYPE4_PKT', - 'CP_TYPE7_PKT', 'CP_VIZ_QUERY', 'CP_WAIT_FOR_IDLE', - 'CP_WAIT_FOR_ME', 'CP_WAIT_IB_PFD_COMPLETE', 'CP_WAIT_MEM_GTE', - 'CP_WAIT_MEM_GTE_0_RESERVED__MASK', - 'CP_WAIT_MEM_GTE_0_RESERVED__SHIFT', - 'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK', - 'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT', - 'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK', - 'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT', - 'CP_WAIT_MEM_GTE_3_REF__MASK', 'CP_WAIT_MEM_GTE_3_REF__SHIFT', - 'CP_WAIT_MEM_WRITES', 'CP_WAIT_REG_EQ', 'CP_WAIT_REG_GTE', - 'CP_WAIT_REG_MEM', 'CP_WAIT_REG_MEM_0_FUNCTION__MASK', - 'CP_WAIT_REG_MEM_0_FUNCTION__SHIFT', - 'CP_WAIT_REG_MEM_0_POLL__MASK', 'CP_WAIT_REG_MEM_0_POLL__SHIFT', - 'CP_WAIT_REG_MEM_0_SIGNED_COMPARE', - 'CP_WAIT_REG_MEM_0_WRITE_MEMORY', - 'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK', - 'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT', - 'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK', - 'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT', - 'CP_WAIT_REG_MEM_3_REF__MASK', 'CP_WAIT_REG_MEM_3_REF__SHIFT', - 'CP_WAIT_REG_MEM_4_MASK__MASK', 'CP_WAIT_REG_MEM_4_MASK__SHIFT', - 'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK', - 'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT', 'CP_WAIT_TIMESTAMP', - 'CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK', - 'CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT', - 'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK', - 'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT', 'CP_WAIT_TWO_REGS', - 'CP_WAIT_TWO_REGS_0_REG0__MASK', 'CP_WAIT_TWO_REGS_0_REG0__SHIFT', - 'CP_WAIT_TWO_REGS_1_REG1__MASK', 'CP_WAIT_TWO_REGS_1_REG1__SHIFT', - 'CP_WAIT_TWO_REGS_2_REF__MASK', 'CP_WAIT_TWO_REGS_2_REF__SHIFT', - 'CP_WAIT_UNTIL_READ', 'CP_WHERE_AM_I', 'CP_WIDE_REG_WRITE', - 'CP_YIELD_ENABLE', 'CS_YALIGN_1', 'CS_YALIGN_2', 'CS_YALIGN_4', - 'CS_YALIGN_8', 'DEPTH6_16', 'DEPTH6_24_8', 'DEPTH6_32', - 'DEPTH6_NONE', 'DEPTHX_16', 'DEPTHX_24_8', 'DEPTHX_32', - 'DIST_ALL_TO_RB0', 'DIST_SCREEN_COORD', 'DITHER_ALWAYS', - 'DITHER_DISABLE', 'DITHER_IF_ALPHA_OFF', 'DI_FACE_BACKFACE_CULL', - 'DI_FACE_CULL_FETCH', 'DI_FACE_CULL_NONE', - 'DI_FACE_FRONTFACE_CULL', 'DI_PT_LINELIST', 'DI_PT_LINELOOP', - 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', 'DI_PT_LINE_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCHES0', 'DI_PT_PATCHES1', - 'DI_PT_PATCHES10', 'DI_PT_PATCHES11', 'DI_PT_PATCHES12', - 'DI_PT_PATCHES13', 'DI_PT_PATCHES14', 'DI_PT_PATCHES15', - 'DI_PT_PATCHES16', 'DI_PT_PATCHES17', 'DI_PT_PATCHES18', - 'DI_PT_PATCHES19', 'DI_PT_PATCHES2', 'DI_PT_PATCHES20', - 'DI_PT_PATCHES21', 'DI_PT_PATCHES22', 'DI_PT_PATCHES23', - 'DI_PT_PATCHES24', 'DI_PT_PATCHES25', 'DI_PT_PATCHES26', - 'DI_PT_PATCHES27', 'DI_PT_PATCHES28', 'DI_PT_PATCHES29', - 'DI_PT_PATCHES3', 'DI_PT_PATCHES30', 'DI_PT_PATCHES31', - 'DI_PT_PATCHES4', 'DI_PT_PATCHES5', 'DI_PT_PATCHES6', - 'DI_PT_PATCHES7', 'DI_PT_PATCHES8', 'DI_PT_PATCHES9', - 'DI_PT_POINTLIST', 'DI_PT_POINTLIST_PSIZE', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRISTRIP', - 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_ADJ', 'DI_SRC_SEL_AUTO_INDEX', - 'DI_SRC_SEL_AUTO_XFB', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DRAW_STRM_ADDRESS', 'DRAW_STRM_SIZE_ADDRESS', 'DUMMY_EVENT', - 'END2D', 'ENDIAN_16IN32', 'ENDIAN_8IN128', 'ENDIAN_8IN16', - 'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', 'EQUAL_SPACING', - 'EQ_0_PASS', 'EVEN_SPACING', 'EV_DST_ONCHIP', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT', 'EV_DST_RAM', - 'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT', - 'EV_WRITE_ALWAYSON', 'EV_WRITE_REGS_CONTENT', - 'EV_WRITE_TIMESTAMP_SUM', 'EV_WRITE_USER_32B', - 'EV_WRITE_USER_64B', 'FACENESS_FLUSH', 'FACTOR_CONSTANT_ALPHA', - 'FACTOR_CONSTANT_COLOR', 'FACTOR_DST_ALPHA', 'FACTOR_DST_COLOR', - 'FACTOR_ONE', 'FACTOR_ONE_MINUS_CONSTANT_ALPHA', - 'FACTOR_ONE_MINUS_CONSTANT_COLOR', 'FACTOR_ONE_MINUS_DST_ALPHA', - 'FACTOR_ONE_MINUS_DST_COLOR', 'FACTOR_ONE_MINUS_SRC1_ALPHA', - 'FACTOR_ONE_MINUS_SRC1_COLOR', 'FACTOR_ONE_MINUS_SRC_ALPHA', - 'FACTOR_ONE_MINUS_SRC_COLOR', 'FACTOR_SRC1_ALPHA', - 'FACTOR_SRC1_COLOR', 'FACTOR_SRC_ALPHA', - 'FACTOR_SRC_ALPHA_SATURATE', 'FACTOR_SRC_COLOR', 'FACTOR_ZERO', - 'FLUSH_PER_OVERLAP', 'FLUSH_PER_OVERLAP_AND_OVERWRITE', - 'FLUSH_SO_0', 'FLUSH_SO_1', 'FLUSH_SO_2', 'FLUSH_SO_3', - 'FMT6_10_10_10_2_SINT', 'FMT6_10_10_10_2_SNORM', - 'FMT6_10_10_10_2_UINT', 'FMT6_10_10_10_2_UNORM', - 'FMT6_10_10_10_2_UNORM_DEST', 'FMT6_11_11_10_FLOAT', - 'FMT6_16_16_16_16_FLOAT', 'FMT6_16_16_16_16_SINT', - 'FMT6_16_16_16_16_SNORM', 'FMT6_16_16_16_16_UINT', - 'FMT6_16_16_16_16_UNORM', 'FMT6_16_16_16_FLOAT', - 'FMT6_16_16_16_SINT', 'FMT6_16_16_16_SNORM', 'FMT6_16_16_16_UINT', - 'FMT6_16_16_16_UNORM', 'FMT6_16_16_FLOAT', 'FMT6_16_16_SINT', - 'FMT6_16_16_SNORM', 'FMT6_16_16_UINT', 'FMT6_16_16_UNORM', - 'FMT6_16_FLOAT', 'FMT6_16_SINT', 'FMT6_16_SNORM', 'FMT6_16_UINT', - 'FMT6_16_UNORM', 'FMT6_1_5_5_5_UNORM', 'FMT6_32_32_32_32_FIXED', - 'FMT6_32_32_32_32_FLOAT', 'FMT6_32_32_32_32_SINT', - 'FMT6_32_32_32_32_SNORM', 'FMT6_32_32_32_32_UINT', - 'FMT6_32_32_32_32_UNORM', 'FMT6_32_32_32_FIXED', - 'FMT6_32_32_32_FLOAT', 'FMT6_32_32_32_SINT', - 'FMT6_32_32_32_SNORM', 'FMT6_32_32_32_UINT', - 'FMT6_32_32_32_UNORM', 'FMT6_32_32_FIXED', 'FMT6_32_32_FLOAT', - 'FMT6_32_32_SINT', 'FMT6_32_32_SNORM', 'FMT6_32_32_UINT', - 'FMT6_32_32_UNORM', 'FMT6_32_FIXED', 'FMT6_32_FLOAT', - 'FMT6_32_SINT', 'FMT6_32_SNORM', 'FMT6_32_UINT', 'FMT6_32_UNORM', - 'FMT6_4_4_4_4_UNORM', 'FMT6_5_5_5_1_UNORM', 'FMT6_5_6_5_UNORM', - 'FMT6_8_8_8_8_SINT', 'FMT6_8_8_8_8_SNORM', 'FMT6_8_8_8_8_UINT', - 'FMT6_8_8_8_8_UNORM', 'FMT6_8_8_8_SINT', 'FMT6_8_8_8_SNORM', - 'FMT6_8_8_8_UINT', 'FMT6_8_8_8_UNORM', 'FMT6_8_8_8_X8_UNORM', - 'FMT6_8_8_SINT', 'FMT6_8_8_SNORM', 'FMT6_8_8_UINT', - 'FMT6_8_8_UNORM', 'FMT6_8_SINT', 'FMT6_8_SNORM', 'FMT6_8_UINT', - 'FMT6_8_UNORM', 'FMT6_9_9_9_E5_FLOAT', 'FMT6_A8_UNORM', - 'FMT6_ASTC_10x10', 'FMT6_ASTC_10x5', 'FMT6_ASTC_10x6', - 'FMT6_ASTC_10x8', 'FMT6_ASTC_12x10', 'FMT6_ASTC_12x12', - 'FMT6_ASTC_4x4', 'FMT6_ASTC_5x4', 'FMT6_ASTC_5x5', - 'FMT6_ASTC_6x5', 'FMT6_ASTC_6x6', 'FMT6_ASTC_8x5', - 'FMT6_ASTC_8x6', 'FMT6_ASTC_8x8', 'FMT6_BPTC', 'FMT6_BPTC_FLOAT', - 'FMT6_BPTC_UFLOAT', 'FMT6_DXT1', 'FMT6_DXT3', 'FMT6_DXT5', - 'FMT6_ETC1', 'FMT6_ETC2_R11_SNORM', 'FMT6_ETC2_R11_UNORM', - 'FMT6_ETC2_RG11_SNORM', 'FMT6_ETC2_RG11_UNORM', 'FMT6_ETC2_RGB8', - 'FMT6_ETC2_RGB8A1', 'FMT6_ETC2_RGBA8', 'FMT6_G8R8B8R8_422_UNORM', - 'FMT6_L8_A8_UNORM', 'FMT6_NONE', 'FMT6_NV12_4R', - 'FMT6_NV12_4R_UV', 'FMT6_NV12_4R_Y', 'FMT6_NV12_UV', - 'FMT6_NV12_VU', 'FMT6_NV12_Y', 'FMT6_NV21', 'FMT6_P010', - 'FMT6_P010_UV', 'FMT6_P010_Y', 'FMT6_R8G8R8B8_422_UNORM', - 'FMT6_R8_G8B8_2PLANE_420_UNORM', 'FMT6_R8_G8_B8_3PLANE_420_UNORM', - 'FMT6_RGTC1_SNORM', 'FMT6_RGTC1_UNORM', 'FMT6_RGTC2_SNORM', - 'FMT6_RGTC2_UNORM', 'FMT6_TP10', 'FMT6_TP10_UV', 'FMT6_TP10_Y', - 'FMT6_Z24_UINT_S8_UINT', 'FMT6_Z24_UNORM_S8_UINT', - 'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 'FOUR_QUADS', - 'FRAGCOORD_CENTER', 'FRAGCOORD_SAMPLE', 'FUNC_ALWAYS', - 'FUNC_EQUAL', 'FUNC_GEQUAL', 'FUNC_GREATER', 'FUNC_LEQUAL', - 'FUNC_LESS', 'FUNC_NEVER', 'FUNC_NOTEQUAL', 'GMEM', 'HLSQ_FLUSH', - 'IGNORE_VISIBILITY', 'INDEX4_SIZE_16_BIT', 'INDEX4_SIZE_32_BIT', - 'INDEX4_SIZE_8_BIT', 'INDEX_SIZE_16_BIT', 'INDEX_SIZE_32_BIT', - 'INDEX_SIZE_8_BIT', 'INDEX_SIZE_IGN', 'INDEX_SIZE_INVALID', - 'INDIRECT_OP_INDEXED', 'INDIRECT_OP_INDIRECT_COUNT', - 'INDIRECT_OP_INDIRECT_COUNT_INDEXED', 'INDIRECT_OP_NORMAL', - 'INTERP_FLAT', 'INTERP_ONE', 'INTERP_SMOOTH', 'INTERP_ZERO', - 'IN_CONST_PREFETCH', 'IN_GMU_INTERRUPT', 'IN_IB_END', - 'IN_IB_PREFETCH_END', 'IN_INCR_UPDT_CONST', 'IN_INCR_UPDT_INSTR', - 'IN_INCR_UPDT_STATE', 'IN_INSTR_MATCH', 'IN_INSTR_PREFETCH', - 'IN_PREEMPT', 'IN_SUBBLK_PREFETCH', 'ISAMMODE_CL', 'ISAMMODE_GL', - 'LABEL', 'LRZ_CLEAR', 'LRZ_DIR_GE', 'LRZ_DIR_INVALID', - 'LRZ_DIR_LE', 'LRZ_FLIP_BUFFER', 'LRZ_FLUSH', 'LR_BT', 'LR_TB', - 'MODIFY_TIMESTAMP_ADD_GLOBAL', 'MODIFY_TIMESTAMP_ADD_LOCAL', - 'MODIFY_TIMESTAMP_CLEAR', 'MSAA_EIGHT', 'MSAA_FOUR', 'MSAA_ONE', - 'MSAA_TWO', 'MULTI', 'NE_0_PASS', 'NON_PRIV_SAVE_ADDR', - 'NON_SECURE_SAVE_ADDR', 'NO_FLUSH', 'ODD_SPACING', - 'PC_CCU_FLUSH_COLOR_TS', 'PC_CCU_FLUSH_DEPTH_TS', - 'PC_CCU_INVALIDATE_COLOR', 'PC_CCU_INVALIDATE_DEPTH', - 'PC_CCU_RESOLVE_TS', 'PC_DRAW_LINES', 'PC_DRAW_POINTS', - 'PC_DRAW_TRIANGLES', 'PERFCOUNTER_START', 'PERFCOUNTER_STOP', - 'PERF_CCU_2D_RD_REQ', 'PERF_CCU_2D_WR_REQ', - 'PERF_CCU_BUSY_CYCLES', 'PERF_CCU_COLOR_BLOCKS', - 'PERF_CCU_COLOR_BLOCK_HIT', 'PERF_CCU_COLOR_READ_FLAG0_COUNT', - 'PERF_CCU_COLOR_READ_FLAG1_COUNT', - 'PERF_CCU_COLOR_READ_FLAG2_COUNT', - 'PERF_CCU_COLOR_READ_FLAG3_COUNT', - 'PERF_CCU_COLOR_READ_FLAG4_COUNT', - 'PERF_CCU_COLOR_READ_FLAG5_COUNT', - 'PERF_CCU_COLOR_READ_FLAG6_COUNT', - 'PERF_CCU_COLOR_READ_FLAG8_COUNT', 'PERF_CCU_DEPTH_BLOCKS', - 'PERF_CCU_DEPTH_BLOCK_HIT', 'PERF_CCU_DEPTH_READ_FLAG0_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG1_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG2_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG3_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG4_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG5_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG6_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG8_COUNT', 'PERF_CCU_GMEM_READ', - 'PERF_CCU_GMEM_WRITE', 'PERF_CCU_PARTIAL_BLOCK_READ', - 'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 'PERF_CCU_STARVE_CYCLES_FLAG_RETURN', - 'PERF_CMPDECMP_2D_BUSY_CYCLES', 'PERF_CMPDECMP_2D_OUTPUT_TRANS', - 'PERF_CMPDECMP_2D_PIXELS', 'PERF_CMPDECMP_2D_RD_DATA', - 'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', - 'PERF_CMPDECMP_2D_WR_DATA', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 'PERF_CMPDECMP_FLAG_FETCH_CYCLES', - 'PERF_CMPDECMP_FLAG_FETCH_SAMPLES', - 'PERF_CMPDECMP_STALL_CYCLES_ARB', - 'PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 'PERF_CMPDECMP_VBIF_READ_DATA', - 'PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 'PERF_CMPDECMP_VBIF_READ_REQUEST', - 'PERF_CMPDECMP_VBIF_WRITE_DATA', - 'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 'PERF_CMPDECMP_VBIF_WRITE_REQUEST', 'PERF_CP_AHB_STALL_SQE_GMU', - 'PERF_CP_AHB_STALL_SQE_RD_OTHER', - 'PERF_CP_AHB_STALL_SQE_WR_OTHER', - 'PERF_CP_AHB_WR_STALL_PRE_DRAWS', 'PERF_CP_ALWAYS_COUNT', - 'PERF_CP_BUSY_CYCLES', 'PERF_CP_BUSY_GFX_CORE_IDLE', - 'PERF_CP_CACHE_FLUSH', 'PERF_CP_CLUSTER0_EMPTY', - 'PERF_CP_CLUSTER1_EMPTY', 'PERF_CP_CLUSTER2_EMPTY', - 'PERF_CP_CLUSTER3_EMPTY', 'PERF_CP_CLUSTER4_EMPTY', - 'PERF_CP_CLUSTER5_EMPTY', 'PERF_CP_CONTEXT_DONE', - 'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 'PERF_CP_LONG_PREEMPTIONS', - 'PERF_CP_MEMORY_POOL_ABOVE_THRESH', 'PERF_CP_MEMORY_POOL_EMPTY', - 'PERF_CP_MEMORY_POOL_SYNC_STALL', 'PERF_CP_MODE_SWITCH', - 'PERF_CP_NUM_PREEMPTIONS', 'PERF_CP_PM4_DATA', - 'PERF_CP_PM4_HEADERS', 'PERF_CP_PREDICATED_DRAWS_KILLED', - 'PERF_CP_PREEMPTION_REACTION_DELAY', - 'PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 'PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 'PERF_CP_SQE_DRAW_EXEC', - 'PERF_CP_SQE_EXEC_PROFILED', 'PERF_CP_SQE_IDLE', - 'PERF_CP_SQE_INSTR_COUNTER', 'PERF_CP_SQE_I_CACHE_STARVE', - 'PERF_CP_SQE_LOAD_STATE_EXEC', 'PERF_CP_SQE_MRB_STARVE', - 'PERF_CP_SQE_PIPE_OUT_STALL', 'PERF_CP_SQE_PM4_STARVE_RB_IB', - 'PERF_CP_SQE_PM4_STARVE_SDS', 'PERF_CP_SQE_PM4_WFI_STALL', - 'PERF_CP_SQE_RRB_STARVE', 'PERF_CP_SQE_SAVE_SDS_STATE', - 'PERF_CP_SQE_SYNC_STALL', 'PERF_CP_SQE_SYS_WFI_STALL', - 'PERF_CP_SQE_T4_EXEC', 'PERF_CP_SQE_VSD_STARVE', - 'PERF_CP_VBIF_READ_BEATS', 'PERF_CP_VBIF_WRITE_BEATS', - 'PERF_CP_VSD_DECODE_STARVE', 'PERF_CP_ZPASS_DONE', - 'PERF_HLSQ_BUSY_CYCLES', 'PERF_HLSQ_COMPUTE_DRAWCALLS', - 'PERF_HLSQ_CS_INVOCATIONS', - 'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', - 'PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 'PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 'PERF_HLSQ_FS_STAGE_1X_WAVES', 'PERF_HLSQ_FS_STAGE_2X_WAVES', - 'PERF_HLSQ_PIXELS', 'PERF_HLSQ_QUADS', - 'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 'PERF_HLSQ_STALL_CYCLES_SP_STATE', 'PERF_HLSQ_STALL_CYCLES_UCHE', - 'PERF_HLSQ_STALL_CYCLES_VPC', 'PERF_HLSQ_UCHE_LATENCY_COUNT', - 'PERF_HLSQ_UCHE_LATENCY_CYCLES', 'PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 'PERF_HLSQ_WAVE_PENDING_NO_QUAD', 'PERF_LRZ_BUSY_CYCLES', - 'PERF_LRZ_FEEDBACK_ACCEPT', 'PERF_LRZ_FEEDBACK_DISCARD', - 'PERF_LRZ_FEEDBACK_STALL', 'PERF_LRZ_FULLY_COVERED_TILES', - 'PERF_LRZ_FULL_8X8_TILES', 'PERF_LRZ_LRZ_READ', - 'PERF_LRZ_LRZ_WRITE', 'PERF_LRZ_MERGE_CACHE_UPDATING', - 'PERF_LRZ_PARTIAL_8X8_TILES', 'PERF_LRZ_PARTIAL_COVERED_TILES', - 'PERF_LRZ_PRIM_KILLED_BY_LRZ', 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 'PERF_LRZ_RAS_MASK_TRANS', 'PERF_LRZ_READ_LATENCY', - 'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', 'PERF_LRZ_STALL_CYCLES_RB', - 'PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 'PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 'PERF_LRZ_STALL_CYCLES_UCHE', - 'PERF_LRZ_STALL_CYCLES_VC', 'PERF_LRZ_STALL_CYCLES_VPC', - 'PERF_LRZ_STALL_CYCLES_VSC', 'PERF_LRZ_STARVE_CYCLES_RAS', - 'PERF_LRZ_TILE_KILLED', 'PERF_LRZ_TOTAL_PIXEL', - 'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 'PERF_PC_2D_DRAWCALLS', - 'PERF_PC_3D_DRAWCALLS', 'PERF_PC_BUSY_CYCLES', - 'PERF_PC_DEAD_PRIM', 'PERF_PC_DS_INVOCATIONS', - 'PERF_PC_DS_PRIMITIVES', 'PERF_PC_GS_INVOCATIONS', - 'PERF_PC_GS_PRIMITIVES', 'PERF_PC_HS_INVOCATIONS', - 'PERF_PC_IA_PRIMITIVES', 'PERF_PC_IA_VERTICES', - 'PERF_PC_INSTANCES', 'PERF_PC_LIVE_PRIM', - 'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', - 'PERF_PC_PASS1_TF_STALL_CYCLES', 'PERF_PC_STALL_CYCLES_TESS', - 'PERF_PC_STALL_CYCLES_TSE', 'PERF_PC_STALL_CYCLES_TSE_ONLY', - 'PERF_PC_STALL_CYCLES_UCHE', 'PERF_PC_STALL_CYCLES_VFD', - 'PERF_PC_STALL_CYCLES_VPC', 'PERF_PC_STALL_CYCLES_VPC_ONLY', - 'PERF_PC_STARVE_CYCLES_DI', 'PERF_PC_STARVE_CYCLES_FOR_INDEX', - 'PERF_PC_STARVE_CYCLES_FOR_POSITION', - 'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', - 'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', - 'PERF_PC_TESS_FACTOR_TRANS', 'PERF_PC_TESS_PC_UV_PATCHES', - 'PERF_PC_TESS_PC_UV_TRANS', 'PERF_PC_TSE_TRANSACTION', - 'PERF_PC_TSE_VERTEX', 'PERF_PC_VERTEX_HITS', - 'PERF_PC_VIS_STREAMS_LOADED', 'PERF_PC_VPC_POS_DATA_TRANSACTION', - 'PERF_PC_VPC_PRIMITIVES', 'PERF_PC_VS_INVOCATIONS', - 'PERF_PC_WORKING_CYCLES', 'PERF_RAS_8X4_TILES', 'PERF_RAS_BLOCKS', - 'PERF_RAS_BUSY_CYCLES', 'PERF_RAS_FULLY_COVERED_8X4_TILES', - 'PERF_RAS_FULLY_COVERED_SUPER_TILES', - 'PERF_RAS_LRZ_INTF_WORKING_CYCLES', 'PERF_RAS_MASKGEN_ACTIVE', - 'PERF_RAS_PRIM_KILLED_INVISILBE', 'PERF_RAS_STALL_CYCLES_LRZ', - 'PERF_RAS_STARVE_CYCLES_TSE', 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 'PERF_RAS_SUPER_TILES', - 'PERF_RBBM_ALWAYS_COUNT', 'PERF_RBBM_ALWAYS_ON', - 'PERF_RBBM_COM_BUSY', 'PERF_RBBM_DCOM_BUSY', - 'PERF_RBBM_HLSQ_BUSY', 'PERF_RBBM_PC_DCALL_BUSY', - 'PERF_RBBM_PC_VSD_BUSY', 'PERF_RBBM_RAS_BUSY', - 'PERF_RBBM_STATUS_MASKED', 'PERF_RBBM_TESS_BUSY', - 'PERF_RBBM_TSE_BUSY', 'PERF_RBBM_UCHE_BUSY', - 'PERF_RBBM_VBIF_BUSY', 'PERF_RBBM_VSC_BUSY', - 'PERF_RB_2D_ALIVE_CYCLES', 'PERF_RB_2D_INPUT_TRANS', - 'PERF_RB_2D_OUTPUT_RB_DST_TRANS', - 'PERF_RB_2D_OUTPUT_RB_SRC_TRANS', 'PERF_RB_2D_STALL_CYCLES_A2D', - 'PERF_RB_2D_STARVE_CYCLES_DST', 'PERF_RB_2D_STARVE_CYCLES_SP', - 'PERF_RB_2D_STARVE_CYCLES_SRC', 'PERF_RB_2D_VALID_PIXELS', - 'PERF_RB_3D_PIXELS', 'PERF_RB_BLENDED_FP16_COMPONENTS', - 'PERF_RB_BLENDED_FP32_COMPONENTS', - 'PERF_RB_BLENDED_FXP_COMPONENTS', - 'PERF_RB_BLENDER_WORKING_CYCLES', 'PERF_RB_BUSY_CYCLES', - 'PERF_RB_COLOR_PIX_TILES', 'PERF_RB_CPROC_WORKING_CYCLES', - 'PERF_RB_C_READ', 'PERF_RB_C_WRITE', 'PERF_RB_EARLY_Z_ARB3_GRANT', - 'PERF_RB_EARLY_Z_SKIP_GRANT', 'PERF_RB_HLSQ_ACTIVE', - 'PERF_RB_LATE_Z_ARB3_GRANT', 'PERF_RB_PS_INVOCATIONS', - 'PERF_RB_SAMPLER_WORKING_CYCLES', 'PERF_RB_STALL_CYCLES_CCU', - 'PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 'PERF_RB_STALL_CYCLES_FIFO0_FULL', - 'PERF_RB_STALL_CYCLES_FIFO1_FULL', - 'PERF_RB_STALL_CYCLES_FIFO2_FULL', 'PERF_RB_STALL_CYCLES_HLSQ', - 'PERF_RB_STALL_CYCLES_VPC', 'PERF_RB_STARVE_CYCLES_BARY_PLANE', - 'PERF_RB_STARVE_CYCLES_CCU', 'PERF_RB_STARVE_CYCLES_LRZ_TILE', - 'PERF_RB_STARVE_CYCLES_SP', 'PERF_RB_STARVE_CYCLES_Z_PLANE', - 'PERF_RB_S_FAIL', 'PERF_RB_TOTAL_PASS', - 'PERF_RB_ZPROC_WORKING_CYCLES', 'PERF_RB_Z_FAIL', - 'PERF_RB_Z_PASS', 'PERF_RB_Z_READ', 'PERF_RB_Z_WORKLOAD', - 'PERF_RB_Z_WRITE', 'PERF_SP_ADDR_LOCK_COUNT', - 'PERF_SP_ALU_WORKING_CYCLES', 'PERF_SP_ANY_EU_WORKING', - 'PERF_SP_ANY_EU_WORKING_CS_STAGE', - 'PERF_SP_ANY_EU_WORKING_FS_STAGE', - 'PERF_SP_ANY_EU_WORKING_VS_STAGE', 'PERF_SP_BUSY_CYCLES', - 'PERF_SP_CS_INSTRUCTIONS', 'PERF_SP_DISPATCHER_WORKING_CYCLES', - 'PERF_SP_DS_INSTRUCTIONS', 'PERF_SP_EFU_WORKING_CYCLES', - 'PERF_SP_EXECUTABLE_WAVES', 'PERF_SP_EXPORT_RB_TRANS', - 'PERF_SP_EXPORT_VPC_TRANS', 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 'PERF_SP_FS_INSTRUCTIONS', 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_DURATION_CYCLES', - 'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_WAVE_CYCLES', 'PERF_SP_FS_STAGE_WAVE_SAMPLES', - 'PERF_SP_GM_ATOMICS', 'PERF_SP_GM_LOAD_INSTRUCTIONS', - 'PERF_SP_GM_LOAD_LATENCY_CYCLES', - 'PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 'PERF_SP_GM_STORE_INSTRUCTIONS', 'PERF_SP_GPR_READ', - 'PERF_SP_GPR_READ_CONFLICT', 'PERF_SP_GPR_READ_PREFETCH', - 'PERF_SP_GPR_WRITE', 'PERF_SP_GPR_WRITE_CONFLICT', - 'PERF_SP_GS_INSTRUCTIONS', 'PERF_SP_HS_INSTRUCTIONS', - 'PERF_SP_ICL1_MISSES', 'PERF_SP_ICL1_REQUESTS', - 'PERF_SP_LM_ATOMICS', 'PERF_SP_LM_BANK_CONFLICTS', - 'PERF_SP_LM_LOAD_INSTRUCTIONS', 'PERF_SP_LM_STORE_INSTRUCTIONS', - 'PERF_SP_LM_WORKING_CYCLES', - 'PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 'PERF_SP_NON_EXECUTION_CYCLES', 'PERF_SP_NON_EXECUTION_LS_CYCLES', - 'PERF_SP_PIXELS_KILLED', 'PERF_SP_SEQUENCER_WORKING_CYCLES', - 'PERF_SP_STALL_CYCLES_RB', 'PERF_SP_STALL_CYCLES_TP', - 'PERF_SP_STALL_CYCLES_UCHE', 'PERF_SP_STALL_CYCLES_VPC', - 'PERF_SP_STARVE_CYCLES_HLSQ', - 'PERF_SP_TEX_CONTROL_WORKING_CYCLES', 'PERF_SP_UCHE_READ_TRANS', - 'PERF_SP_UCHE_WRITE_TRANS', 'PERF_SP_VS_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_DURATION_CYCLES', - 'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_WAVE_CYCLES', 'PERF_SP_VS_STAGE_WAVE_SAMPLES', - 'PERF_SP_WAVE_CONTEXTS', 'PERF_SP_WAVE_CONTEXT_CYCLES', - 'PERF_SP_WAVE_CTRL_CYCLES', 'PERF_SP_WAVE_EMIT_CYCLES', - 'PERF_SP_WAVE_END_CYCLES', 'PERF_SP_WAVE_FETCH_CYCLES', - 'PERF_SP_WAVE_IDLE_CYCLES', 'PERF_SP_WAVE_JOIN_CYCLES', - 'PERF_SP_WAVE_LOAD_CYCLES', 'PERF_SP_WAVE_LONG_SYNC_CYCLES', - 'PERF_SP_WAVE_NOP_CYCLES', 'PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 'PERF_SP_WAVE_WAIT_CYCLES', 'PERF_SP_WORKING_EU', - 'PERF_SP_WORKING_EU_CS_STAGE', 'PERF_SP_WORKING_EU_FS_STAGE', - 'PERF_SP_WORKING_EU_VS_STAGE', 'PERF_TESS_BUSY_CYCLES', - 'PERF_TESS_STALL_CYCLES_PC', 'PERF_TESS_STARVE_CYCLES_PC', - 'PERF_TESS_WORKING_CYCLES', 'PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 'PERF_TP_2D_FILTER_WORKLOAD_32BIT', 'PERF_TP_2D_OUTPUT_PIXELS', - 'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 'PERF_TP_2D_OUTPUT_PIXELS_POINT', - 'PERF_TP_BACKEND_WORKING_CYCLES', 'PERF_TP_BUSY_CYCLES', - 'PERF_TP_DIVERGENT_QUADS_RECEIVED', - 'PERF_TP_FILTER_WORKLOAD_16BIT', 'PERF_TP_FILTER_WORKLOAD_32BIT', - 'PERF_TP_FLAG_CACHE_MISSES', 'PERF_TP_FLAG_CACHE_REQUESTS', - 'PERF_TP_FLAG_CACHE_REQUEST_LATENCY', - 'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', - 'PERF_TP_FLAG_CACHE_WORKING_CYCLES', - 'PERF_TP_FRONTEND_WORKING_CYCLES', - 'PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 'PERF_TP_L1_5_L2_COMPRESS_MISS', 'PERF_TP_L1_5_L2_COMPRESS_REQS', - 'PERF_TP_L1_5_L2_REQUESTS', 'PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 'PERF_TP_L1_5_MISS_LATENCY_TRANS', 'PERF_TP_L1_BANK_CONFLICT', - 'PERF_TP_L1_CACHELINE_MISSES', 'PERF_TP_L1_CACHELINE_REQUESTS', - 'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 'PERF_TP_L1_MISSES_ASTC_1TILE', 'PERF_TP_L1_MISSES_ASTC_2TILE', - 'PERF_TP_L1_MISSES_ASTC_4TILE', 'PERF_TP_L1_TAG_WORKING_CYCLES', - 'PERF_TP_LATENCY_CYCLES', 'PERF_TP_LATENCY_TRANS', - 'PERF_TP_OUTPUT_PIXELS', 'PERF_TP_OUTPUT_PIXELS_ANISO', - 'PERF_TP_OUTPUT_PIXELS_BILINEAR', 'PERF_TP_OUTPUT_PIXELS_MIP', - 'PERF_TP_OUTPUT_PIXELS_POINT', 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 'PERF_TP_PRT_NON_RESIDENT_EVENTS', 'PERF_TP_QUADS_1D', - 'PERF_TP_QUADS_2D', 'PERF_TP_QUADS_3D', 'PERF_TP_QUADS_ARRAY', - 'PERF_TP_QUADS_BUFFER', 'PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 'PERF_TP_QUADS_CUBE', 'PERF_TP_QUADS_GRADIENT', - 'PERF_TP_QUADS_OFFSET', 'PERF_TP_QUADS_RECEIVED', - 'PERF_TP_QUADS_SHADOW', 'PERF_TP_SP_TP_TRANS', - 'PERF_TP_STALL_CYCLES_UCHE', 'PERF_TP_STARVE_CYCLES_SP', - 'PERF_TP_STARVE_CYCLES_UCHE', 'PERF_TP_TPA2TPC_TRANS', - 'PERF_TP_TP_SP_TRANS', 'PERF_TSE_2D_ALIVE_CYCLES', - 'PERF_TSE_2D_INPUT_PRIM', 'PERF_TSE_BUSY_CYCLES', - 'PERF_TSE_CINVOCATION', 'PERF_TSE_CLIPPED_PRIM', - 'PERF_TSE_CLIPPING_CYCLES', 'PERF_TSE_CLIP_PLANES', - 'PERF_TSE_CPRIMITIVES', 'PERF_TSE_FACENESS_CULLED_PRIM', - 'PERF_TSE_INPUT_NULL_PRIM', 'PERF_TSE_INPUT_PRIM', - 'PERF_TSE_OUTPUT_NULL_PRIM', 'PERF_TSE_OUTPUT_VISIBLE_PRIM', - 'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', - 'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', 'PERF_TSE_STALL_CYCLES_RAS', - 'PERF_TSE_STARVE_CYCLES_PC', 'PERF_TSE_TRIVAL_REJ_PRIM', - 'PERF_TSE_ZERO_AREA_PRIM', 'PERF_TSE_ZERO_PIXEL_PRIM', - 'PERF_UCHE_BANK_REQ0', 'PERF_UCHE_BANK_REQ1', - 'PERF_UCHE_BANK_REQ2', 'PERF_UCHE_BANK_REQ3', - 'PERF_UCHE_BANK_REQ4', 'PERF_UCHE_BANK_REQ5', - 'PERF_UCHE_BANK_REQ6', 'PERF_UCHE_BANK_REQ7', - 'PERF_UCHE_BUSY_CYCLES', 'PERF_UCHE_DCMP_LATENCY_CYCLES', - 'PERF_UCHE_DCMP_LATENCY_SAMPLES', 'PERF_UCHE_EVICTS', - 'PERF_UCHE_GMEM_READ_BEATS', 'PERF_UCHE_RAM_READ_REQ', - 'PERF_UCHE_RAM_WRITE_REQ', 'PERF_UCHE_READ_REQUESTS_HLSQ', - 'PERF_UCHE_READ_REQUESTS_LRZ', 'PERF_UCHE_READ_REQUESTS_PC', - 'PERF_UCHE_READ_REQUESTS_SP', 'PERF_UCHE_READ_REQUESTS_TP', - 'PERF_UCHE_READ_REQUESTS_VFD', 'PERF_UCHE_STALL_CYCLES_ARBITER', - 'PERF_UCHE_TPH_EXT_FULL', 'PERF_UCHE_TPH_REF_FULL', - 'PERF_UCHE_TPH_VICTIM_FULL', 'PERF_UCHE_VBIF_LATENCY_CYCLES', - 'PERF_UCHE_VBIF_LATENCY_SAMPLES', 'PERF_UCHE_VBIF_READ_BEATS_CH0', - 'PERF_UCHE_VBIF_READ_BEATS_CH1', 'PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 'PERF_UCHE_VBIF_READ_BEATS_LRZ', 'PERF_UCHE_VBIF_READ_BEATS_PC', - 'PERF_UCHE_VBIF_READ_BEATS_SP', 'PERF_UCHE_VBIF_READ_BEATS_TP', - 'PERF_UCHE_VBIF_READ_BEATS_VFD', - 'PERF_UCHE_VBIF_STALL_WRITE_DATA', 'PERF_UCHE_WRITE_REQUESTS_LRZ', - 'PERF_UCHE_WRITE_REQUESTS_SP', 'PERF_UCHE_WRITE_REQUESTS_VPC', - 'PERF_UCHE_WRITE_REQUESTS_VSC', 'PERF_VFDP_STALL_CYCLES_VFD', - 'PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 'PERF_VFDP_STALL_CYCLES_VFD_PROG', 'PERF_VFDP_STARVE_CYCLES_PC', - 'PERF_VFDP_VS_STAGE_WAVES', 'PERF_VFD_ATTR_INFO_FIFO_FULL', - 'PERF_VFD_BUSY_CYCLES', 'PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 'PERF_VFD_LOWER_SHADER_FIBERS', 'PERF_VFD_MODE_0_FIBERS', - 'PERF_VFD_MODE_1_FIBERS', 'PERF_VFD_MODE_2_FIBERS', - 'PERF_VFD_MODE_3_FIBERS', 'PERF_VFD_MODE_4_FIBERS', - 'PERF_VFD_NUM_ATTRIBUTES', 'PERF_VFD_RBUFFER_FULL', - 'PERF_VFD_STALL_CYCLES_SP_ATTR', 'PERF_VFD_STALL_CYCLES_SP_INFO', - 'PERF_VFD_STALL_CYCLES_UCHE', 'PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 'PERF_VFD_STARVE_CYCLES_UCHE', 'PERF_VFD_TOTAL_VERTICES', - 'PERF_VFD_UPPER_SHADER_FIBERS', 'PERF_VPC_BUSY_CYCLES', - 'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', 'PERF_VPC_LM_TRANSACTION', - 'PERF_VPC_LRZ_ASSIGN_PRIMITIVES', 'PERF_VPC_NUM_ATTR_REQ_LM', - 'PERF_VPC_NUM_VPCRAM_READ_POS', 'PERF_VPC_NUM_VPCRAM_READ_SO', - 'PERF_VPC_NUM_VPCRAM_WRITE', 'PERF_VPC_PC_PRIMITIVES', - 'PERF_VPC_PS_BUSY_CYCLES', 'PERF_VPC_PS_WORKING_CYCLES', - 'PERF_VPC_RB_VISIBLE_PRIMITIVES', 'PERF_VPC_SP_COMPONENTS', - 'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 'PERF_VPC_STALL_CYCLES_PC', 'PERF_VPC_STALL_CYCLES_SP_LM', - 'PERF_VPC_STALL_CYCLES_UCHE', 'PERF_VPC_STALL_CYCLES_VFD_WACK', - 'PERF_VPC_STALL_CYCLES_VPCRAM_POS', 'PERF_VPC_STARVE_CYCLES_LRZ', - 'PERF_VPC_STARVE_CYCLES_RB', 'PERF_VPC_STARVE_CYCLES_SP', - 'PERF_VPC_STREAMOUT_TRANSACTION', 'PERF_VPC_VPCRAM_FULL_CYCLES', - 'PERF_VPC_VS_BUSY_CYCLES', 'PERF_VPC_VS_WORKING_CYCLES', - 'PERF_VPC_WIT_FULL_CYCLES', 'PERF_VPC_WORKING_CYCLES', - 'PERF_VSC_BUSY_CYCLES', 'PERF_VSC_EOT_NUM', - 'PERF_VSC_INPUT_TILES', 'PERF_VSC_STALL_CYCLES_UCHE', - 'PERF_VSC_WORKING_CYCLES', 'PIPE_BR_WAIT_FOR_BV', - 'PIPE_BV_WAIT_FOR_BR', 'PIPE_CLEAR_BV_BR', 'PIPE_SET_BR_OFFSET', - 'PKT4', 'POLL_MEMORY', 'POLL_ON_CHIP', 'POLL_REGISTER', - 'POLL_SCRATCH', 'POLYMODE6_LINES', 'POLYMODE6_POINTS', - 'POLYMODE6_TRIANGLES', 'PRED_SRC_MEM', 'PRED_TEST', - 'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'PRIM_STRM_ADDRESS', - 'PS_DEALLOC', 'PS_DONE_TS', 'PS_REPL_NONE', 'PS_REPL_ONE_MINUS_T', - 'PS_REPL_S', 'PS_REPL_T', 'R2D_FLOAT16', 'R2D_FLOAT32', - 'R2D_INT16', 'R2D_INT32', 'R2D_INT8', 'R2D_RAW', 'R2D_UNORM8', - 'R2D_UNORM8_SRGB', 'RB_BT', 'RB_COMPUTE_PASS', 'RB_COPY_CLEAR', - 'RB_COPY_DEPTH_STENCIL', 'RB_COPY_RESOLVE', 'RB_DONE_TS', - 'RB_RENDERING_PASS', 'RB_RESOLVE_PASS', 'RB_SAVE_IB', - 'RB_TILING_PASS', 'RECTANGULAR', 'REG_A4XX_CP_DRAW_INDIRECT_0', - 'REG_A4XX_CP_DRAW_INDIRECT_1', 'REG_A4XX_CP_DRAW_INDX_INDIRECT_0', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_1', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_2', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_3', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_0', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_1', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_2', 'REG_A5XX_CP_DRAW_INDIRECT_1', - 'REG_A5XX_CP_DRAW_INDIRECT_2', - 'REG_A5XX_CP_DRAW_INDIRECT_INDIRECT', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_1', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_2', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_3', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_4', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_5', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_4', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_5', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_6', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_1', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_2', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_3', 'REG_A6XX_CP_2D_EVENT_END', - 'REG_A6XX_CP_2D_EVENT_START', 'REG_A6XX_CP_ADDR_MODE_CNTL', - 'REG_A6XX_CP_AHB_CNTL', 'REG_A6XX_CP_ALWAYS_ON_COUNTER', - 'REG_A6XX_CP_APERTURE_CNTL_CD', 'REG_A6XX_CP_APERTURE_CNTL_HOST', - 'REG_A6XX_CP_APRIV_CNTL', 'REG_A6XX_CP_CHICKEN_DBG', - 'REG_A6XX_CP_CONTEXT_SWITCH_CNTL', - 'REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO', - 'REG_A6XX_CP_CP2GMU_STATUS', 'REG_A6XX_CP_CRASH_DUMP_CNTL', - 'REG_A6XX_CP_CRASH_DUMP_STATUS', 'REG_A6XX_CP_CRASH_SCRIPT_BASE', - 'REG_A6XX_CP_DBG_ECO_CNTL', 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_0', - 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_1', - 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT', - 'REG_A6XX_CP_DRAW_STATE_ADDR', 'REG_A6XX_CP_DRAW_STATE_DATA', - 'REG_A6XX_CP_EVENT_END', 'REG_A6XX_CP_EVENT_START', - 'REG_A6XX_CP_HW_FAULT', 'REG_A6XX_CP_IB1_BASE', - 'REG_A6XX_CP_IB1_DWORDS', 'REG_A6XX_CP_IB1_REM_SIZE', - 'REG_A6XX_CP_IB2_BASE', 'REG_A6XX_CP_IB2_DWORDS', - 'REG_A6XX_CP_IB2_REM_SIZE', 'REG_A6XX_CP_INTERRUPT_STATUS', - 'REG_A6XX_CP_LPAC_PROG_FIFO_SIZE', 'REG_A6XX_CP_LPAC_SQE_CNTL', - 'REG_A6XX_CP_LPAC_SQE_INSTR_BASE', - 'REG_A6XX_CP_MEM_POOL_DBG_ADDR', 'REG_A6XX_CP_MEM_POOL_DBG_DATA', - 'REG_A6XX_CP_MEM_POOL_SIZE', 'REG_A6XX_CP_MISC_CNTL', - 'REG_A6XX_CP_MRB_BASE', 'REG_A6XX_CP_MRB_DWORDS', - 'REG_A6XX_CP_MRB_REM_SIZE', 'REG_A6XX_CP_PREEMPT_THRESHOLD', - 'REG_A6XX_CP_PROTECT_CNTL', 'REG_A6XX_CP_PROTECT_STATUS', - 'REG_A6XX_CP_RB_BASE', 'REG_A6XX_CP_RB_CNTL', - 'REG_A6XX_CP_RB_RPTR', 'REG_A6XX_CP_RB_RPTR_ADDR', - 'REG_A6XX_CP_RB_WPTR', 'REG_A6XX_CP_REG_TEST_0', - 'REG_A6XX_CP_REG_TEST_PRED_MASK', 'REG_A6XX_CP_REG_TEST_PRED_VAL', - 'REG_A6XX_CP_ROQ_AVAIL_IB1', 'REG_A6XX_CP_ROQ_AVAIL_IB2', - 'REG_A6XX_CP_ROQ_AVAIL_MRB', 'REG_A6XX_CP_ROQ_AVAIL_RB', - 'REG_A6XX_CP_ROQ_AVAIL_SDS', 'REG_A6XX_CP_ROQ_AVAIL_VSD', - 'REG_A6XX_CP_ROQ_DBG_ADDR', 'REG_A6XX_CP_ROQ_DBG_DATA', - 'REG_A6XX_CP_ROQ_IB1_STAT', 'REG_A6XX_CP_ROQ_IB2_STAT', - 'REG_A6XX_CP_ROQ_MRB_STAT', 'REG_A6XX_CP_ROQ_RB_STAT', - 'REG_A6XX_CP_ROQ_SDS_STAT', 'REG_A6XX_CP_ROQ_THRESHOLDS_1', - 'REG_A6XX_CP_ROQ_THRESHOLDS_2', 'REG_A6XX_CP_ROQ_VSD_STAT', - 'REG_A6XX_CP_SDS_BASE', 'REG_A6XX_CP_SDS_DWORDS', - 'REG_A6XX_CP_SDS_REM_SIZE', 'REG_A6XX_CP_SET_MARKER_0', - 'REG_A6XX_CP_SQE_CNTL', 'REG_A6XX_CP_SQE_INSTR_BASE', - 'REG_A6XX_CP_SQE_STAT_ADDR', 'REG_A6XX_CP_SQE_STAT_DATA', - 'REG_A6XX_CP_SQE_UCODE_DBG_ADDR', - 'REG_A6XX_CP_SQE_UCODE_DBG_DATA', 'REG_A6XX_CP_STATUS_1', - 'REG_A6XX_CP_VSD_BASE', 'REG_A6XX_CP_VSD_DWORDS', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2', - 'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0', - 'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_CNTLM', - 'REG_A6XX_DBGC_CFG_DBGBUS_CNTLT', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_A', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_B', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_C', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_D', - 'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1', - 'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2', 'REG_A6XX_GBIF_HALT', - 'REG_A6XX_GBIF_HALT_ACK', 'REG_A6XX_GBIF_PERF_CNT_HIGH0', - 'REG_A6XX_GBIF_PERF_CNT_HIGH1', 'REG_A6XX_GBIF_PERF_CNT_HIGH2', - 'REG_A6XX_GBIF_PERF_CNT_HIGH3', 'REG_A6XX_GBIF_PERF_CNT_LOW0', - 'REG_A6XX_GBIF_PERF_CNT_LOW1', 'REG_A6XX_GBIF_PERF_CNT_LOW2', - 'REG_A6XX_GBIF_PERF_CNT_LOW3', 'REG_A6XX_GBIF_PERF_CNT_SEL', - 'REG_A6XX_GBIF_PERF_PWR_CNT_CLR', 'REG_A6XX_GBIF_PERF_PWR_CNT_EN', - 'REG_A6XX_GBIF_PERF_PWR_CNT_SEL', 'REG_A6XX_GBIF_PWR_CNT_HIGH0', - 'REG_A6XX_GBIF_PWR_CNT_HIGH1', 'REG_A6XX_GBIF_PWR_CNT_HIGH2', - 'REG_A6XX_GBIF_PWR_CNT_LOW0', 'REG_A6XX_GBIF_PWR_CNT_LOW1', - 'REG_A6XX_GBIF_PWR_CNT_LOW2', 'REG_A6XX_GBIF_QSB_SIDE0', - 'REG_A6XX_GBIF_QSB_SIDE1', 'REG_A6XX_GBIF_QSB_SIDE2', - 'REG_A6XX_GBIF_QSB_SIDE3', 'REG_A6XX_GBIF_SCACHE_CNTL0', - 'REG_A6XX_GBIF_SCACHE_CNTL1', 'REG_A6XX_GRAS_2D_BLIT_CNTL', - 'REG_A6XX_GRAS_2D_DST_BR', 'REG_A6XX_GRAS_2D_DST_TL', - 'REG_A6XX_GRAS_2D_RESOLVE_CNTL_1', - 'REG_A6XX_GRAS_2D_RESOLVE_CNTL_2', 'REG_A6XX_GRAS_2D_SRC_BR_X', - 'REG_A6XX_GRAS_2D_SRC_BR_Y', 'REG_A6XX_GRAS_2D_SRC_TL_X', - 'REG_A6XX_GRAS_2D_SRC_TL_Y', 'REG_A6XX_GRAS_2D_UNKNOWN_8407', - 'REG_A6XX_GRAS_2D_UNKNOWN_8408', 'REG_A6XX_GRAS_2D_UNKNOWN_8409', - 'REG_A6XX_GRAS_ADDR_MODE_CNTL', 'REG_A6XX_GRAS_BIN_CONTROL', - 'REG_A6XX_GRAS_CL_CNTL', 'REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ', - 'REG_A6XX_GRAS_CNTL', 'REG_A6XX_GRAS_DBG_ECO_CNTL', - 'REG_A6XX_GRAS_DEST_MSAA_CNTL', 'REG_A6XX_GRAS_DS_CL_CNTL', - 'REG_A6XX_GRAS_DS_LAYER_CNTL', 'REG_A6XX_GRAS_GS_CL_CNTL', - 'REG_A6XX_GRAS_GS_LAYER_CNTL', 'REG_A6XX_GRAS_LRZ_BUFFER_BASE', - 'REG_A6XX_GRAS_LRZ_BUFFER_PITCH', 'REG_A6XX_GRAS_LRZ_CNTL', - 'REG_A6XX_GRAS_LRZ_DEPTH_VIEW', - 'REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE', - 'REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0', - 'REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL', - 'REG_A6XX_GRAS_MAX_LAYER_INDEX', 'REG_A6XX_GRAS_RAS_MSAA_CNTL', - 'REG_A6XX_GRAS_SAMPLE_CNTL', 'REG_A6XX_GRAS_SAMPLE_CONFIG', - 'REG_A6XX_GRAS_SAMPLE_LOCATION_0', - 'REG_A6XX_GRAS_SAMPLE_LOCATION_1', 'REG_A6XX_GRAS_SC_CNTL', - 'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR', - 'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL', 'REG_A6XX_GRAS_SU_CNTL', - 'REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL', - 'REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO', - 'REG_A6XX_GRAS_SU_DEPTH_CNTL', - 'REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL', - 'REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL', - 'REG_A6XX_GRAS_SU_POINT_MINMAX', 'REG_A6XX_GRAS_SU_POINT_SIZE', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE', - 'REG_A6XX_GRAS_SU_STENCIL_CNTL', 'REG_A6XX_GRAS_UNKNOWN_80AF', - 'REG_A6XX_GRAS_UNKNOWN_8110', 'REG_A6XX_GRAS_VS_CL_CNTL', - 'REG_A6XX_GRAS_VS_LAYER_CNTL', 'REG_A6XX_HLSQ_2D_EVENT_CMD', - 'REG_A6XX_HLSQ_ADDR_MODE_CNTL', - 'REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE', - 'REG_A6XX_HLSQ_CONTROL_1_REG', 'REG_A6XX_HLSQ_CONTROL_2_REG', - 'REG_A6XX_HLSQ_CONTROL_3_REG', 'REG_A6XX_HLSQ_CONTROL_4_REG', - 'REG_A6XX_HLSQ_CONTROL_5_REG', 'REG_A6XX_HLSQ_CS_CNTL', - 'REG_A6XX_HLSQ_CS_CNTL_0', 'REG_A6XX_HLSQ_CS_CNTL_1', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_X', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A6XX_HLSQ_CS_NDRANGE_0', - 'REG_A6XX_HLSQ_CS_NDRANGE_1', 'REG_A6XX_HLSQ_CS_NDRANGE_2', - 'REG_A6XX_HLSQ_CS_NDRANGE_3', 'REG_A6XX_HLSQ_CS_NDRANGE_4', - 'REG_A6XX_HLSQ_CS_NDRANGE_5', 'REG_A6XX_HLSQ_CS_NDRANGE_6', - 'REG_A6XX_HLSQ_CS_UNKNOWN_B9D0', - 'REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE', - 'REG_A6XX_HLSQ_DBG_ECO_CNTL', 'REG_A6XX_HLSQ_DBG_READ_SEL', - 'REG_A6XX_HLSQ_DISPATCH_CMD', 'REG_A6XX_HLSQ_DRAW_CMD', - 'REG_A6XX_HLSQ_DS_CNTL', 'REG_A6XX_HLSQ_EVENT_CMD', - 'REG_A6XX_HLSQ_FS_CNTL', 'REG_A6XX_HLSQ_FS_CNTL_0', - 'REG_A6XX_HLSQ_GS_CNTL', 'REG_A6XX_HLSQ_HS_CNTL', - 'REG_A6XX_HLSQ_INVALIDATE_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR', - 'REG_A6XX_HLSQ_SHARED_CONSTS', 'REG_A6XX_HLSQ_UNKNOWN_B981', - 'REG_A6XX_HLSQ_UNKNOWN_BE00', 'REG_A6XX_HLSQ_UNKNOWN_BE01', - 'REG_A6XX_HLSQ_UNKNOWN_BE08', 'REG_A6XX_HLSQ_VS_CNTL', - 'REG_A6XX_PC_2D_EVENT_CMD', 'REG_A6XX_PC_ADDR_MODE_CNTL', - 'REG_A6XX_PC_BIN_DRAW_STRM', 'REG_A6XX_PC_BIN_PRIM_STRM', - 'REG_A6XX_PC_DBG_ECO_CNTL', - 'REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL', - 'REG_A6XX_PC_DISPATCH_CMD', 'REG_A6XX_PC_DRAW_CMD', - 'REG_A6XX_PC_DRAW_FIRST_INDX', 'REG_A6XX_PC_DRAW_INDX_BASE', - 'REG_A6XX_PC_DRAW_INITIATOR', 'REG_A6XX_PC_DRAW_MAX_INDICES', - 'REG_A6XX_PC_DRAW_NUM_INDICES', 'REG_A6XX_PC_DRAW_NUM_INSTANCES', - 'REG_A6XX_PC_DS_OUT_CNTL', 'REG_A6XX_PC_EVENT_CMD', - 'REG_A6XX_PC_GS_OUT_CNTL', 'REG_A6XX_PC_HS_INPUT_SIZE', - 'REG_A6XX_PC_HS_OUT_CNTL', 'REG_A6XX_PC_MARKER', - 'REG_A6XX_PC_MODE_CNTL', 'REG_A6XX_PC_MULTIVIEW_CNTL', - 'REG_A6XX_PC_MULTIVIEW_MASK', 'REG_A6XX_PC_POLYGON_MODE', - 'REG_A6XX_PC_POWER_CNTL', 'REG_A6XX_PC_PRIMITIVE_CNTL_0', - 'REG_A6XX_PC_PRIMITIVE_CNTL_5', 'REG_A6XX_PC_PRIMITIVE_CNTL_6', - 'REG_A6XX_PC_PS_CNTL', 'REG_A6XX_PC_RASTER_CNTL', - 'REG_A6XX_PC_RESTART_INDEX', 'REG_A6XX_PC_SO_STREAM_CNTL', - 'REG_A6XX_PC_TESSFACTOR_ADDR', 'REG_A6XX_PC_TESS_CNTL', - 'REG_A6XX_PC_TESS_NUM_VERTEX', 'REG_A6XX_PC_UNKNOWN_9E72', - 'REG_A6XX_PC_VISIBILITY_OVERRIDE', 'REG_A6XX_PC_VSTREAM_CONTROL', - 'REG_A6XX_PC_VS_OUT_CNTL', 'REG_A6XX_PDC_GPU_ENABLE_PDC', - 'REG_A6XX_PDC_GPU_SEQ_MEM_0', 'REG_A6XX_PDC_GPU_SEQ_START_ADDR', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS0_CONTROL', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS1_CONTROL', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS2_CONTROL', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS3_CONTROL', - 'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD', - 'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2', 'REG_A6XX_RBBM_CLOCK_CNTL', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RAC', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RB1', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RB3', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_SP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_SP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_UCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL3_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP1', - 'REG_A6XX_RBBM_CLOCK_CNTL3_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP3', - 'REG_A6XX_RBBM_CLOCK_CNTL3_UCHE', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP0', - 'REG_A6XX_RBBM_CLOCK_CNTL4_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP2', - 'REG_A6XX_RBBM_CLOCK_CNTL4_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL4_UCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL_CCU0', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU1', - 'REG_A6XX_RBBM_CLOCK_CNTL_CCU2', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU3', - 'REG_A6XX_RBBM_CLOCK_CNTL_FCHE', 'REG_A6XX_RBBM_CLOCK_CNTL_GLC', - 'REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX', - 'REG_A6XX_RBBM_CLOCK_CNTL_MHUB', 'REG_A6XX_RBBM_CLOCK_CNTL_RAC', - 'REG_A6XX_RBBM_CLOCK_CNTL_RB0', 'REG_A6XX_RBBM_CLOCK_CNTL_RB1', - 'REG_A6XX_RBBM_CLOCK_CNTL_RB2', 'REG_A6XX_RBBM_CLOCK_CNTL_RB3', - 'REG_A6XX_RBBM_CLOCK_CNTL_SP0', 'REG_A6XX_RBBM_CLOCK_CNTL_SP1', - 'REG_A6XX_RBBM_CLOCK_CNTL_SP2', 'REG_A6XX_RBBM_CLOCK_CNTL_SP3', - 'REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL_TP1', - 'REG_A6XX_RBBM_CLOCK_CNTL_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL_TP3', - 'REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_CNTL_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY2_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_FCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_GLC', - 'REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX', - 'REG_A6XX_RBBM_CLOCK_DELAY_GPC', 'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ', - 'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2', - 'REG_A6XX_RBBM_CLOCK_DELAY_MHUB', 'REG_A6XX_RBBM_CLOCK_DELAY_RAC', - 'REG_A6XX_RBBM_CLOCK_DELAY_SP0', 'REG_A6XX_RBBM_CLOCK_DELAY_SP1', - 'REG_A6XX_RBBM_CLOCK_DELAY_SP2', 'REG_A6XX_RBBM_CLOCK_DELAY_SP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_DELAY_TP0', 'REG_A6XX_RBBM_CLOCK_DELAY_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY_TP2', 'REG_A6XX_RBBM_CLOCK_DELAY_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_DELAY_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_VFD', - 'REG_A6XX_RBBM_CLOCK_HYST2_TP0', 'REG_A6XX_RBBM_CLOCK_HYST2_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST2_TP2', 'REG_A6XX_RBBM_CLOCK_HYST2_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST3_TP0', 'REG_A6XX_RBBM_CLOCK_HYST3_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST3_TP2', 'REG_A6XX_RBBM_CLOCK_HYST3_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST4_TP0', 'REG_A6XX_RBBM_CLOCK_HYST4_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST4_TP2', 'REG_A6XX_RBBM_CLOCK_HYST4_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST_FCHE', 'REG_A6XX_RBBM_CLOCK_HYST_GLC', - 'REG_A6XX_RBBM_CLOCK_HYST_GMU_GX', 'REG_A6XX_RBBM_CLOCK_HYST_GPC', - 'REG_A6XX_RBBM_CLOCK_HYST_HLSQ', 'REG_A6XX_RBBM_CLOCK_HYST_MHUB', - 'REG_A6XX_RBBM_CLOCK_HYST_RAC', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3', - 'REG_A6XX_RBBM_CLOCK_HYST_SP0', 'REG_A6XX_RBBM_CLOCK_HYST_SP1', - 'REG_A6XX_RBBM_CLOCK_HYST_SP2', 'REG_A6XX_RBBM_CLOCK_HYST_SP3', - 'REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_HYST_TP0', 'REG_A6XX_RBBM_CLOCK_HYST_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST_TP2', 'REG_A6XX_RBBM_CLOCK_HYST_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_HYST_UCHE', 'REG_A6XX_RBBM_CLOCK_HYST_VFD', - 'REG_A6XX_RBBM_CLOCK_MODE_GPC', 'REG_A6XX_RBBM_CLOCK_MODE_HLSQ', - 'REG_A6XX_RBBM_CLOCK_MODE_VFD', - 'REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL', 'REG_A6XX_RBBM_GBIF_HALT', - 'REG_A6XX_RBBM_GBIF_HALT_ACK', 'REG_A6XX_RBBM_GPR0_CNTL', - 'REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL', - 'REG_A6XX_RBBM_INT_0_MASK', 'REG_A6XX_RBBM_INT_0_STATUS', - 'REG_A6XX_RBBM_INT_CLEAR_CMD', 'REG_A6XX_RBBM_ISDB_CNT', - 'REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL', - 'REG_A6XX_RBBM_PERFCTR_CNTL', - 'REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD0', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD1', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD2', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD3', - 'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI', - 'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO', - 'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD', - 'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS', - 'REG_A6XX_RBBM_PRIMCTR_0_HI', 'REG_A6XX_RBBM_PRIMCTR_0_LO', - 'REG_A6XX_RBBM_PRIMCTR_10_HI', 'REG_A6XX_RBBM_PRIMCTR_10_LO', - 'REG_A6XX_RBBM_PRIMCTR_1_HI', 'REG_A6XX_RBBM_PRIMCTR_1_LO', - 'REG_A6XX_RBBM_PRIMCTR_2_HI', 'REG_A6XX_RBBM_PRIMCTR_2_LO', - 'REG_A6XX_RBBM_PRIMCTR_3_HI', 'REG_A6XX_RBBM_PRIMCTR_3_LO', - 'REG_A6XX_RBBM_PRIMCTR_4_HI', 'REG_A6XX_RBBM_PRIMCTR_4_LO', - 'REG_A6XX_RBBM_PRIMCTR_5_HI', 'REG_A6XX_RBBM_PRIMCTR_5_LO', - 'REG_A6XX_RBBM_PRIMCTR_6_HI', 'REG_A6XX_RBBM_PRIMCTR_6_LO', - 'REG_A6XX_RBBM_PRIMCTR_7_HI', 'REG_A6XX_RBBM_PRIMCTR_7_LO', - 'REG_A6XX_RBBM_PRIMCTR_8_HI', 'REG_A6XX_RBBM_PRIMCTR_8_LO', - 'REG_A6XX_RBBM_PRIMCTR_9_HI', 'REG_A6XX_RBBM_PRIMCTR_9_LO', - 'REG_A6XX_RBBM_RAC_THRESHOLD_CNT', - 'REG_A6XX_RBBM_SECVID_TRUST_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE', - 'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE', - 'REG_A6XX_RBBM_SP_HYST_CNT', 'REG_A6XX_RBBM_STATUS', - 'REG_A6XX_RBBM_STATUS1', 'REG_A6XX_RBBM_STATUS2', - 'REG_A6XX_RBBM_STATUS3', 'REG_A6XX_RBBM_SW_RESET_CMD', - 'REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL', - 'REG_A6XX_RBBM_VBIF_GX_RESET_STATUS', - 'REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD', 'REG_A6XX_RB_2D_BLIT_CNTL', - 'REG_A6XX_RB_2D_DST', 'REG_A6XX_RB_2D_DST_FLAGS', - 'REG_A6XX_RB_2D_DST_FLAGS_PITCH', - 'REG_A6XX_RB_2D_DST_FLAGS_PLANE', - 'REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH', 'REG_A6XX_RB_2D_DST_INFO', - 'REG_A6XX_RB_2D_DST_PITCH', 'REG_A6XX_RB_2D_DST_PLANE1', - 'REG_A6XX_RB_2D_DST_PLANE2', 'REG_A6XX_RB_2D_DST_PLANE_PITCH', - 'REG_A6XX_RB_2D_SRC_SOLID_C0', 'REG_A6XX_RB_2D_SRC_SOLID_C1', - 'REG_A6XX_RB_2D_SRC_SOLID_C2', 'REG_A6XX_RB_2D_SRC_SOLID_C3', - 'REG_A6XX_RB_2D_UNKNOWN_8C01', 'REG_A6XX_RB_ADDR_MODE_CNTL', - 'REG_A6XX_RB_ALPHA_CONTROL', 'REG_A6XX_RB_BIN_CONTROL', - 'REG_A6XX_RB_BIN_CONTROL2', 'REG_A6XX_RB_BLEND_ALPHA_F32', - 'REG_A6XX_RB_BLEND_BLUE_F32', 'REG_A6XX_RB_BLEND_CNTL', - 'REG_A6XX_RB_BLEND_GREEN_F32', 'REG_A6XX_RB_BLEND_RED_F32', - 'REG_A6XX_RB_BLIT_BASE_GMEM', 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3', 'REG_A6XX_RB_BLIT_DST', - 'REG_A6XX_RB_BLIT_DST_ARRAY_PITCH', 'REG_A6XX_RB_BLIT_DST_INFO', - 'REG_A6XX_RB_BLIT_DST_PITCH', 'REG_A6XX_RB_BLIT_FLAG_DST', - 'REG_A6XX_RB_BLIT_FLAG_DST_PITCH', - 'REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL', 'REG_A6XX_RB_BLIT_INFO', - 'REG_A6XX_RB_BLIT_SCISSOR_BR', 'REG_A6XX_RB_BLIT_SCISSOR_TL', - 'REG_A6XX_RB_CCU_CNTL', 'REG_A6XX_RB_CMP_DBG_ECO_CNTL', - 'REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE', - 'REG_A6XX_RB_DBG_ECO_CNTL', - 'REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH', - 'REG_A6XX_RB_DEPTH_BUFFER_BASE', - 'REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM', - 'REG_A6XX_RB_DEPTH_BUFFER_INFO', 'REG_A6XX_RB_DEPTH_BUFFER_PITCH', - 'REG_A6XX_RB_DEPTH_CNTL', 'REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE', - 'REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH', - 'REG_A6XX_RB_DEPTH_PLANE_CNTL', 'REG_A6XX_RB_DEST_MSAA_CNTL', - 'REG_A6XX_RB_DITHER_CNTL', 'REG_A6XX_RB_FS_OUTPUT_CNTL0', - 'REG_A6XX_RB_FS_OUTPUT_CNTL1', 'REG_A6XX_RB_LRZ_CNTL', - 'REG_A6XX_RB_NC_MODE_CNTL', 'REG_A6XX_RB_RAS_MSAA_CNTL', - 'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD', - 'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST', - 'REG_A6XX_RB_RENDER_CNTL', 'REG_A6XX_RB_RENDER_COMPONENTS', - 'REG_A6XX_RB_RENDER_CONTROL0', 'REG_A6XX_RB_RENDER_CONTROL1', - 'REG_A6XX_RB_SAMPLE_CNTL', 'REG_A6XX_RB_SAMPLE_CONFIG', - 'REG_A6XX_RB_SAMPLE_COUNT_ADDR', - 'REG_A6XX_RB_SAMPLE_COUNT_CONTROL', - 'REG_A6XX_RB_SAMPLE_LOCATION_0', 'REG_A6XX_RB_SAMPLE_LOCATION_1', - 'REG_A6XX_RB_SRGB_CNTL', 'REG_A6XX_RB_STENCILMASK', - 'REG_A6XX_RB_STENCILREF', 'REG_A6XX_RB_STENCILWRMASK', - 'REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH', - 'REG_A6XX_RB_STENCIL_BUFFER_BASE', - 'REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM', - 'REG_A6XX_RB_STENCIL_BUFFER_PITCH', 'REG_A6XX_RB_STENCIL_CONTROL', - 'REG_A6XX_RB_STENCIL_INFO', 'REG_A6XX_RB_UNKNOWN_8811', - 'REG_A6XX_RB_UNKNOWN_8818', 'REG_A6XX_RB_UNKNOWN_8819', - 'REG_A6XX_RB_UNKNOWN_881A', 'REG_A6XX_RB_UNKNOWN_881B', - 'REG_A6XX_RB_UNKNOWN_881C', 'REG_A6XX_RB_UNKNOWN_881D', - 'REG_A6XX_RB_UNKNOWN_881E', 'REG_A6XX_RB_UNKNOWN_88D0', - 'REG_A6XX_RB_UNKNOWN_88F0', 'REG_A6XX_RB_UNKNOWN_88F4', - 'REG_A6XX_RB_UNKNOWN_8A00', 'REG_A6XX_RB_UNKNOWN_8A10', - 'REG_A6XX_RB_UNKNOWN_8A20', 'REG_A6XX_RB_UNKNOWN_8A30', - 'REG_A6XX_RB_UNKNOWN_8E01', 'REG_A6XX_RB_UNKNOWN_8E51', - 'REG_A6XX_RB_UNK_FLAG_BUFFER_BASE', - 'REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH', 'REG_A6XX_RB_WINDOW_OFFSET', - 'REG_A6XX_RB_WINDOW_OFFSET2', 'REG_A6XX_RB_Z_BOUNDS_MAX', - 'REG_A6XX_RB_Z_BOUNDS_MIN', 'REG_A6XX_RB_Z_CLAMP_MAX', - 'REG_A6XX_RB_Z_CLAMP_MIN', 'REG_A6XX_SP_2D_DST_FORMAT', - 'REG_A6XX_SP_ADDR_MODE_CNTL', 'REG_A6XX_SP_BLEND_CNTL', - 'REG_A6XX_SP_CHICKEN_BITS', - 'REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE', - 'REG_A6XX_SP_CS_BRANCH_COND', 'REG_A6XX_SP_CS_CNTL_0', - 'REG_A6XX_SP_CS_CNTL_1', 'REG_A6XX_SP_CS_CONFIG', - 'REG_A6XX_SP_CS_CTRL_REG0', 'REG_A6XX_SP_CS_IBO', - 'REG_A6XX_SP_CS_IBO_COUNT', 'REG_A6XX_SP_CS_INSTRLEN', - 'REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_CS_OBJ_START', 'REG_A6XX_SP_CS_PVT_MEM_ADDR', - 'REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_CS_PVT_MEM_PARAM', 'REG_A6XX_SP_CS_PVT_MEM_SIZE', - 'REG_A6XX_SP_CS_TEX_CONST', 'REG_A6XX_SP_CS_TEX_COUNT', - 'REG_A6XX_SP_CS_TEX_SAMP', 'REG_A6XX_SP_CS_UNKNOWN_A9B1', - 'REG_A6XX_SP_DBG_ECO_CNTL', 'REG_A6XX_SP_DS_BRANCH_COND', - 'REG_A6XX_SP_DS_CONFIG', 'REG_A6XX_SP_DS_CTRL_REG0', - 'REG_A6XX_SP_DS_INSTRLEN', 'REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_DS_OBJ_START', 'REG_A6XX_SP_DS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_DS_PVT_MEM_ADDR', - 'REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_DS_PVT_MEM_PARAM', 'REG_A6XX_SP_DS_PVT_MEM_SIZE', - 'REG_A6XX_SP_DS_TEX_CONST', 'REG_A6XX_SP_DS_TEX_COUNT', - 'REG_A6XX_SP_DS_TEX_SAMP', 'REG_A6XX_SP_FLOAT_CNTL', - 'REG_A6XX_SP_FS_BRANCH_COND', 'REG_A6XX_SP_FS_CONFIG', - 'REG_A6XX_SP_FS_CTRL_REG0', 'REG_A6XX_SP_FS_INSTRLEN', - 'REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_FS_OBJ_START', 'REG_A6XX_SP_FS_OUTPUT_CNTL0', - 'REG_A6XX_SP_FS_OUTPUT_CNTL1', 'REG_A6XX_SP_FS_PREFETCH_CNTL', - 'REG_A6XX_SP_FS_PVT_MEM_ADDR', - 'REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_FS_PVT_MEM_PARAM', 'REG_A6XX_SP_FS_PVT_MEM_SIZE', - 'REG_A6XX_SP_FS_RENDER_COMPONENTS', 'REG_A6XX_SP_FS_TEX_CONST', - 'REG_A6XX_SP_FS_TEX_COUNT', 'REG_A6XX_SP_FS_TEX_SAMP', - 'REG_A6XX_SP_GS_BRANCH_COND', 'REG_A6XX_SP_GS_CONFIG', - 'REG_A6XX_SP_GS_CTRL_REG0', 'REG_A6XX_SP_GS_INSTRLEN', - 'REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_GS_OBJ_START', 'REG_A6XX_SP_GS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_GS_PRIM_SIZE', 'REG_A6XX_SP_GS_PVT_MEM_ADDR', - 'REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_GS_PVT_MEM_PARAM', 'REG_A6XX_SP_GS_PVT_MEM_SIZE', - 'REG_A6XX_SP_GS_TEX_CONST', 'REG_A6XX_SP_GS_TEX_COUNT', - 'REG_A6XX_SP_GS_TEX_SAMP', 'REG_A6XX_SP_HS_BRANCH_COND', - 'REG_A6XX_SP_HS_CONFIG', 'REG_A6XX_SP_HS_CTRL_REG0', - 'REG_A6XX_SP_HS_INSTRLEN', 'REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_HS_OBJ_START', 'REG_A6XX_SP_HS_PVT_MEM_ADDR', - 'REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_HS_PVT_MEM_PARAM', 'REG_A6XX_SP_HS_PVT_MEM_SIZE', - 'REG_A6XX_SP_HS_TEX_CONST', 'REG_A6XX_SP_HS_TEX_COUNT', - 'REG_A6XX_SP_HS_TEX_SAMP', 'REG_A6XX_SP_HS_WAVE_INPUT_SIZE', - 'REG_A6XX_SP_IBO', 'REG_A6XX_SP_IBO_COUNT', - 'REG_A6XX_SP_MODE_CONTROL', 'REG_A6XX_SP_NC_MODE_CNTL', - 'REG_A6XX_SP_PERFCTR_ENABLE', 'REG_A6XX_SP_PS_2D_SRC', - 'REG_A6XX_SP_PS_2D_SRC_FLAGS', - 'REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A6XX_SP_PS_2D_SRC_INFO', - 'REG_A6XX_SP_PS_2D_SRC_PITCH', 'REG_A6XX_SP_PS_2D_SRC_PLANE1', - 'REG_A6XX_SP_PS_2D_SRC_PLANE2', - 'REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A6XX_SP_PS_2D_SRC_SIZE', - 'REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR', - 'REG_A6XX_SP_PS_UNKNOWN_B4CD', 'REG_A6XX_SP_PS_UNKNOWN_B4CE', - 'REG_A6XX_SP_PS_UNKNOWN_B4CF', 'REG_A6XX_SP_PS_UNKNOWN_B4D0', - 'REG_A6XX_SP_SRGB_CNTL', 'REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR', - 'REG_A6XX_SP_TP_DEST_MSAA_CNTL', 'REG_A6XX_SP_TP_MODE_CNTL', - 'REG_A6XX_SP_TP_RAS_MSAA_CNTL', 'REG_A6XX_SP_TP_SAMPLE_CONFIG', - 'REG_A6XX_SP_TP_SAMPLE_LOCATION_0', - 'REG_A6XX_SP_TP_SAMPLE_LOCATION_1', - 'REG_A6XX_SP_TP_WINDOW_OFFSET', 'REG_A6XX_SP_UNKNOWN_A9A8', - 'REG_A6XX_SP_UNKNOWN_AAF2', 'REG_A6XX_SP_UNKNOWN_B182', - 'REG_A6XX_SP_UNKNOWN_B183', 'REG_A6XX_SP_UNKNOWN_B190', - 'REG_A6XX_SP_UNKNOWN_B191', 'REG_A6XX_SP_VS_BRANCH_COND', - 'REG_A6XX_SP_VS_CONFIG', 'REG_A6XX_SP_VS_CTRL_REG0', - 'REG_A6XX_SP_VS_INSTRLEN', 'REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_VS_OBJ_START', 'REG_A6XX_SP_VS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_VS_PVT_MEM_ADDR', - 'REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_VS_PVT_MEM_PARAM', 'REG_A6XX_SP_VS_PVT_MEM_SIZE', - 'REG_A6XX_SP_VS_TEX_CONST', 'REG_A6XX_SP_VS_TEX_COUNT', - 'REG_A6XX_SP_VS_TEX_SAMP', 'REG_A6XX_SP_WINDOW_OFFSET', - 'REG_A6XX_TEX_CONST_0', 'REG_A6XX_TEX_CONST_1', - 'REG_A6XX_TEX_CONST_10', 'REG_A6XX_TEX_CONST_11', - 'REG_A6XX_TEX_CONST_12', 'REG_A6XX_TEX_CONST_13', - 'REG_A6XX_TEX_CONST_14', 'REG_A6XX_TEX_CONST_15', - 'REG_A6XX_TEX_CONST_2', 'REG_A6XX_TEX_CONST_3', - 'REG_A6XX_TEX_CONST_4', 'REG_A6XX_TEX_CONST_5', - 'REG_A6XX_TEX_CONST_6', 'REG_A6XX_TEX_CONST_7', - 'REG_A6XX_TEX_CONST_8', 'REG_A6XX_TEX_CONST_9', - 'REG_A6XX_TEX_SAMP_0', 'REG_A6XX_TEX_SAMP_1', - 'REG_A6XX_TEX_SAMP_2', 'REG_A6XX_TEX_SAMP_3', - 'REG_A6XX_TPL1_ADDR_MODE_CNTL', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4', - 'REG_A6XX_TPL1_DBG_ECO_CNTL', 'REG_A6XX_TPL1_DBG_ECO_CNTL1', - 'REG_A6XX_TPL1_NC_MODE_CNTL', 'REG_A6XX_TPL1_UNKNOWN_B605', - 'REG_A6XX_UBO_0', 'REG_A6XX_UBO_1', - 'REG_A6XX_UCHE_ADDR_MODE_CNTL', 'REG_A6XX_UCHE_CACHE_WAYS', - 'REG_A6XX_UCHE_CLIENT_PF', 'REG_A6XX_UCHE_CMDQ_CONFIG', - 'REG_A6XX_UCHE_FILTER_CNTL', 'REG_A6XX_UCHE_GBIF_GX_CONFIG', - 'REG_A6XX_UCHE_GMEM_RANGE_MAX', 'REG_A6XX_UCHE_GMEM_RANGE_MIN', - 'REG_A6XX_UCHE_MODE_CNTL', 'REG_A6XX_UCHE_TRAP_BASE', - 'REG_A6XX_UCHE_UNKNOWN_0E12', 'REG_A6XX_UCHE_WRITE_RANGE_MAX', - 'REG_A6XX_UCHE_WRITE_THRU_BASE', 'REG_A6XX_VBIF_CLKON', - 'REG_A6XX_VBIF_GATE_OFF_WRREQ_EN', 'REG_A6XX_VBIF_PERF_CNT_HIGH0', - 'REG_A6XX_VBIF_PERF_CNT_HIGH1', 'REG_A6XX_VBIF_PERF_CNT_HIGH2', - 'REG_A6XX_VBIF_PERF_CNT_HIGH3', 'REG_A6XX_VBIF_PERF_CNT_LOW0', - 'REG_A6XX_VBIF_PERF_CNT_LOW1', 'REG_A6XX_VBIF_PERF_CNT_LOW2', - 'REG_A6XX_VBIF_PERF_CNT_LOW3', 'REG_A6XX_VBIF_PERF_CNT_SEL0', - 'REG_A6XX_VBIF_PERF_CNT_SEL1', 'REG_A6XX_VBIF_PERF_CNT_SEL2', - 'REG_A6XX_VBIF_PERF_CNT_SEL3', 'REG_A6XX_VBIF_PERF_PWR_CNT_EN0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_EN1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_EN2', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW2', - 'REG_A6XX_VBIF_TEST_BUS1_CTRL0', 'REG_A6XX_VBIF_TEST_BUS1_CTRL1', - 'REG_A6XX_VBIF_TEST_BUS2_CTRL0', 'REG_A6XX_VBIF_TEST_BUS2_CTRL1', - 'REG_A6XX_VBIF_TEST_BUS_OUT', 'REG_A6XX_VBIF_TEST_BUS_OUT_CTRL', - 'REG_A6XX_VBIF_VERSION', 'REG_A6XX_VBIF_XIN_HALT_CTRL0', - 'REG_A6XX_VBIF_XIN_HALT_CTRL1', 'REG_A6XX_VFD_ADDR_MODE_CNTL', - 'REG_A6XX_VFD_ADD_OFFSET', 'REG_A6XX_VFD_CONTROL_0', - 'REG_A6XX_VFD_CONTROL_1', 'REG_A6XX_VFD_CONTROL_2', - 'REG_A6XX_VFD_CONTROL_3', 'REG_A6XX_VFD_CONTROL_4', - 'REG_A6XX_VFD_CONTROL_5', 'REG_A6XX_VFD_CONTROL_6', - 'REG_A6XX_VFD_INDEX_OFFSET', 'REG_A6XX_VFD_INSTANCE_START_OFFSET', - 'REG_A6XX_VFD_MODE_CNTL', 'REG_A6XX_VFD_MULTIVIEW_CNTL', - 'REG_A6XX_VFD_POWER_CNTL', 'REG_A6XX_VPC_ADDR_MODE_CNTL', - 'REG_A6XX_VPC_CNTL_0', 'REG_A6XX_VPC_DBG_ECO_CNTL', - 'REG_A6XX_VPC_DS_CLIP_CNTL', 'REG_A6XX_VPC_DS_CLIP_CNTL_V2', - 'REG_A6XX_VPC_DS_LAYER_CNTL', 'REG_A6XX_VPC_DS_LAYER_CNTL_V2', - 'REG_A6XX_VPC_DS_PACK', 'REG_A6XX_VPC_GS_CLIP_CNTL', - 'REG_A6XX_VPC_GS_CLIP_CNTL_V2', 'REG_A6XX_VPC_GS_LAYER_CNTL', - 'REG_A6XX_VPC_GS_LAYER_CNTL_V2', 'REG_A6XX_VPC_GS_PACK', - 'REG_A6XX_VPC_GS_PARAM', 'REG_A6XX_VPC_POINT_COORD_INVERT', - 'REG_A6XX_VPC_POLYGON_MODE', 'REG_A6XX_VPC_SO_CNTL', - 'REG_A6XX_VPC_SO_DISABLE', 'REG_A6XX_VPC_SO_PROG', - 'REG_A6XX_VPC_SO_STREAM_CNTL', 'REG_A6XX_VPC_SO_STREAM_COUNTS', - 'REG_A6XX_VPC_UNKNOWN_9107', 'REG_A6XX_VPC_UNKNOWN_9210', - 'REG_A6XX_VPC_UNKNOWN_9211', 'REG_A6XX_VPC_UNKNOWN_9300', - 'REG_A6XX_VPC_UNKNOWN_9602', 'REG_A6XX_VPC_UNKNOWN_9603', - 'REG_A6XX_VPC_VS_CLIP_CNTL', 'REG_A6XX_VPC_VS_CLIP_CNTL_V2', - 'REG_A6XX_VPC_VS_LAYER_CNTL', 'REG_A6XX_VPC_VS_LAYER_CNTL_V2', - 'REG_A6XX_VPC_VS_PACK', 'REG_A6XX_VSC_ADDR_MODE_CNTL', - 'REG_A6XX_VSC_BIN_COUNT', 'REG_A6XX_VSC_BIN_SIZE', - 'REG_A6XX_VSC_DBG_ECO_CNTL', 'REG_A6XX_VSC_DRAW_STRM_ADDRESS', - 'REG_A6XX_VSC_DRAW_STRM_LIMIT', 'REG_A6XX_VSC_DRAW_STRM_PITCH', - 'REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS', - 'REG_A6XX_VSC_PRIM_STRM_ADDRESS', 'REG_A6XX_VSC_PRIM_STRM_LIMIT', - 'REG_A6XX_VSC_PRIM_STRM_PITCH', 'REG_A7XX_CP_APERTURE_CNTL_CD', - 'REG_A7XX_CP_APERTURE_CNTL_HOST', 'REG_A7XX_CP_AQE_APRIV_CNTL', - 'REG_A7XX_CP_AQE_INSTR_BASE_0', 'REG_A7XX_CP_AQE_INSTR_BASE_1', - 'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0', - 'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1', - 'REG_A7XX_CP_AQE_ROQ_DBG_DATA_0', - 'REG_A7XX_CP_AQE_ROQ_DBG_DATA_1', 'REG_A7XX_CP_AQE_STAT_ADDR_0', - 'REG_A7XX_CP_AQE_STAT_ADDR_1', 'REG_A7XX_CP_AQE_STAT_DATA_0', - 'REG_A7XX_CP_AQE_STAT_DATA_1', 'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0', - 'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1', - 'REG_A7XX_CP_AQE_UCODE_DBG_DATA_0', - 'REG_A7XX_CP_AQE_UCODE_DBG_DATA_1', 'REG_A7XX_CP_BV_APRIV_CNTL', - 'REG_A7XX_CP_BV_CHICKEN_DBG', 'REG_A7XX_CP_BV_DRAW_STATE_ADDR', - 'REG_A7XX_CP_BV_DRAW_STATE_DATA', 'REG_A7XX_CP_BV_HW_FAULT', - 'REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR', - 'REG_A7XX_CP_BV_MEM_POOL_DBG_DATA', - 'REG_A7XX_CP_BV_PROTECT_STATUS', 'REG_A7XX_CP_BV_RB_RPTR_ADDR', - 'REG_A7XX_CP_BV_ROQ_DBG_ADDR', 'REG_A7XX_CP_BV_ROQ_DBG_DATA', - 'REG_A7XX_CP_BV_SQE_STAT_ADDR', 'REG_A7XX_CP_BV_SQE_STAT_DATA', - 'REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR', - 'REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA', - 'REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS', - 'REG_A7XX_CP_LPAC_APRIV_CNTL', 'REG_A7XX_CP_LPAC_DRAW_STATE_ADDR', - 'REG_A7XX_CP_LPAC_DRAW_STATE_DATA', - 'REG_A7XX_CP_LPAC_FIFO_DBG_ADDR', - 'REG_A7XX_CP_LPAC_FIFO_DBG_DATA', 'REG_A7XX_CP_LPAC_ROQ_DBG_ADDR', - 'REG_A7XX_CP_LPAC_ROQ_DBG_DATA', - 'REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR', - 'REG_A7XX_CP_RESOURCE_TBL_DBG_DATA', - 'REG_A7XX_CP_SQE_AC_STAT_ADDR', 'REG_A7XX_CP_SQE_AC_STAT_DATA', - 'REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR', - 'REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA', - 'REG_A7XX_CX_MISC_SW_FUSE_VALUE', 'REG_A7XX_CX_MISC_TCM_RET_CNTL', - 'REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32', 'REG_A7XX_GRAS_LRZ_CNTL2', - 'REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO', - 'REG_A7XX_GRAS_NC_MODE_CNTL', 'REG_A7XX_GRAS_SU_RENDER_CNTL', - 'REG_A7XX_GRAS_UNKNOWN_8007', 'REG_A7XX_GRAS_UNKNOWN_8008', - 'REG_A7XX_GRAS_UNKNOWN_8009', 'REG_A7XX_GRAS_UNKNOWN_800A', - 'REG_A7XX_GRAS_UNKNOWN_800B', 'REG_A7XX_GRAS_UNKNOWN_800C', - 'REG_A7XX_GRAS_UNKNOWN_80A7', 'REG_A7XX_GRAS_UNKNOWN_80F4', - 'REG_A7XX_GRAS_UNKNOWN_80F5', 'REG_A7XX_GRAS_UNKNOWN_80F6', - 'REG_A7XX_GRAS_UNKNOWN_80F8', 'REG_A7XX_GRAS_UNKNOWN_80F9', - 'REG_A7XX_GRAS_UNKNOWN_80FA', 'REG_A7XX_GRAS_UNKNOWN_8120', - 'REG_A7XX_GRAS_UNKNOWN_8121', 'REG_A7XX_HLSQ_CONTROL_1_REG', - 'REG_A7XX_HLSQ_CONTROL_2_REG', 'REG_A7XX_HLSQ_CONTROL_3_REG', - 'REG_A7XX_HLSQ_CONTROL_4_REG', 'REG_A7XX_HLSQ_CONTROL_5_REG', - 'REG_A7XX_HLSQ_CS_CNTL', 'REG_A7XX_HLSQ_CS_CNTL_1', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_X', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A7XX_HLSQ_CS_LOCAL_SIZE', - 'REG_A7XX_HLSQ_CS_NDRANGE_0', 'REG_A7XX_HLSQ_CS_NDRANGE_1', - 'REG_A7XX_HLSQ_CS_NDRANGE_2', 'REG_A7XX_HLSQ_CS_NDRANGE_3', - 'REG_A7XX_HLSQ_CS_NDRANGE_4', 'REG_A7XX_HLSQ_CS_NDRANGE_5', - 'REG_A7XX_HLSQ_CS_NDRANGE_6', 'REG_A7XX_HLSQ_DISPATCH_CMD', - 'REG_A7XX_HLSQ_DRAW_CMD', 'REG_A7XX_HLSQ_DS_CNTL', - 'REG_A7XX_HLSQ_EVENT_CMD', 'REG_A7XX_HLSQ_FS_CNTL', - 'REG_A7XX_HLSQ_FS_CNTL_0', 'REG_A7XX_HLSQ_FS_UNKNOWN_A9AA', - 'REG_A7XX_HLSQ_GS_CNTL', 'REG_A7XX_HLSQ_HS_CNTL', - 'REG_A7XX_HLSQ_INVALIDATE_CMD', 'REG_A7XX_HLSQ_UNKNOWN_A9AC', - 'REG_A7XX_HLSQ_UNKNOWN_A9AD', 'REG_A7XX_HLSQ_UNKNOWN_A9AE', - 'REG_A7XX_HLSQ_VS_CNTL', 'REG_A7XX_PC_ATTR_BUF_SIZE_GMEM', - 'REG_A7XX_PC_POLYGON_MODE', 'REG_A7XX_PC_RASTER_CNTL', - 'REG_A7XX_PC_RASTER_CNTL_V2', 'REG_A7XX_PC_TESSFACTOR_ADDR', - 'REG_A7XX_PC_TESS_FACTOR_SIZE', 'REG_A7XX_PC_TESS_PARAM_SIZE', - 'REG_A7XX_PC_UNKNOWN_9E24', 'REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD', - 'REG_A7XX_RBBM_CGC_P2S_STATUS', 'REG_A7XX_RBBM_CGC_P2S_TRIG_CMD', - 'REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL', - 'REG_A7XX_RBBM_CLOCK_HYST2_VFD', 'REG_A7XX_RBBM_CLOCK_MODE2_GRAS', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_GPC', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_VFD', 'REG_A7XX_RBBM_CLOCK_MODE_CP', - 'REG_A7XX_RBBM_GBIF_HALT', 'REG_A7XX_RBBM_GBIF_HALT_ACK', - 'REG_A7XX_RBBM_INT_2_MASK', 'REG_A7XX_RBBM_NC_MODE_CNTL', - 'REG_A7XX_RBBM_SECVID_TSB_STATUS', - 'REG_A7XX_RBBM_SNAPSHOT_STATUS', 'REG_A7XX_RBBM_SW_FUSE_INT_MASK', - 'REG_A7XX_RBBM_SW_FUSE_INT_STATUS', 'REG_A7XX_RB_BIN_CONTROL', - 'REG_A7XX_RB_CCU_CNTL', 'REG_A7XX_RB_CCU_CNTL2', - 'REG_A7XX_RB_DEPTH_BUFFER_INFO', 'REG_A7XX_RB_RENDER_CNTL', - 'REG_A7XX_RB_STENCIL_INFO', 'REG_A7XX_RB_UNKNOWN_8812', - 'REG_A7XX_RB_UNKNOWN_8899', 'REG_A7XX_RB_UNKNOWN_88E4', - 'REG_A7XX_RB_UNKNOWN_88F5', 'REG_A7XX_RB_UNKNOWN_8C34', - 'REG_A7XX_RB_UNKNOWN_8E06', 'REG_A7XX_RB_UNKNOWN_8E09', - 'REG_A7XX_RB_UNKNOWN_8E79', 'REG_A7XX_SP_2D_DST_FORMAT', - 'REG_A7XX_SP_AHB_READ_APERTURE', 'REG_A7XX_SP_CS_CNTL_1', - 'REG_A7XX_SP_CS_UNKNOWN_A9BE', 'REG_A7XX_SP_CS_VGPR_CONFIG', - 'REG_A7XX_SP_DBG_CNTL', 'REG_A7XX_SP_DS_VGPR_CONFIG', - 'REG_A7XX_SP_FS_VGPR_CONFIG', 'REG_A7XX_SP_GS_VGPR_CONFIG', - 'REG_A7XX_SP_HS_VGPR_CONFIG', 'REG_A7XX_SP_PS_2D_SRC', - 'REG_A7XX_SP_PS_2D_SRC_FLAGS', - 'REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A7XX_SP_PS_2D_SRC_INFO', - 'REG_A7XX_SP_PS_2D_SRC_PITCH', 'REG_A7XX_SP_PS_2D_SRC_PLANE1', - 'REG_A7XX_SP_PS_2D_SRC_PLANE2', - 'REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A7XX_SP_PS_2D_SRC_SIZE', - 'REG_A7XX_SP_PS_2D_WINDOW_OFFSET', - 'REG_A7XX_SP_PS_ALIASED_COMPONENTS', - 'REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL', - 'REG_A7XX_SP_PS_UNKNOWN_B2D2', 'REG_A7XX_SP_PS_UNKNOWN_B4CD', - 'REG_A7XX_SP_PS_UNKNOWN_B4CE', 'REG_A7XX_SP_PS_UNKNOWN_B4CF', - 'REG_A7XX_SP_PS_UNKNOWN_B4D0', 'REG_A7XX_SP_READ_SEL', - 'REG_A7XX_SP_UNKNOWN_0CE2', 'REG_A7XX_SP_UNKNOWN_0CE4', - 'REG_A7XX_SP_UNKNOWN_0CE6', 'REG_A7XX_SP_UNKNOWN_AB01', - 'REG_A7XX_SP_UNKNOWN_AB02', 'REG_A7XX_SP_UNKNOWN_AB22', - 'REG_A7XX_SP_UNKNOWN_AE06', 'REG_A7XX_SP_UNKNOWN_AE08', - 'REG_A7XX_SP_UNKNOWN_AE09', 'REG_A7XX_SP_UNKNOWN_AE0A', - 'REG_A7XX_SP_UNKNOWN_AE6A', 'REG_A7XX_SP_UNKNOWN_AE6B', - 'REG_A7XX_SP_UNKNOWN_AE6C', 'REG_A7XX_SP_UNKNOWN_AE73', - 'REG_A7XX_SP_UNKNOWN_B310', 'REG_A7XX_SP_VS_VGPR_CONFIG', - 'REG_A7XX_SP_WINDOW_OFFSET', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4', - 'REG_A7XX_UCHE_UNKNOWN_0E10', 'REG_A7XX_UCHE_UNKNOWN_0E11', - 'REG_A7XX_VFD_UNKNOWN_A600', 'REG_A7XX_VPC_ATTR_BUF_BASE_GMEM', - 'REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM', 'REG_A7XX_VPC_MULTIVIEW_CNTL', - 'REG_A7XX_VPC_MULTIVIEW_MASK', 'REG_A7XX_VPC_POLYGON_MODE2', - 'REG_A7XX_VPC_PRIMITIVE_CNTL_0', 'REG_A7XX_VPC_PRIMITIVE_CNTL_5', - 'REG_A7XX_VSC_UNKNOWN_0CD8', 'REG_A7XX_VSC_UNKNOWN_0D08', - 'REG_AXXX_CP_BIN_MASK_HI', 'REG_AXXX_CP_BIN_MASK_LO', - 'REG_AXXX_CP_BIN_SELECT_HI', 'REG_AXXX_CP_BIN_SELECT_LO', - 'REG_AXXX_CP_CSQ_AVAIL', 'REG_AXXX_CP_CSQ_IB1_STAT', - 'REG_AXXX_CP_CSQ_IB2_STAT', 'REG_AXXX_CP_CSQ_RB_STAT', - 'REG_AXXX_CP_DEBUG', 'REG_AXXX_CP_IB1_BASE', - 'REG_AXXX_CP_IB1_BUFSZ', 'REG_AXXX_CP_IB2_BASE', - 'REG_AXXX_CP_IB2_BUFSZ', 'REG_AXXX_CP_INT_ACK', - 'REG_AXXX_CP_INT_CNTL', 'REG_AXXX_CP_INT_STATUS', - 'REG_AXXX_CP_MEQ_AVAIL', 'REG_AXXX_CP_MEQ_STAT', - 'REG_AXXX_CP_MEQ_THRESHOLDS', 'REG_AXXX_CP_ME_CF_EVENT_ADDR', - 'REG_AXXX_CP_ME_CF_EVENT_DATA', 'REG_AXXX_CP_ME_CF_EVENT_SRC', - 'REG_AXXX_CP_ME_CNTL', 'REG_AXXX_CP_ME_NRT_ADDR', - 'REG_AXXX_CP_ME_NRT_DATA', 'REG_AXXX_CP_ME_PS_EVENT_ADDR', - 'REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM', - 'REG_AXXX_CP_ME_PS_EVENT_DATA', - 'REG_AXXX_CP_ME_PS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_PS_EVENT_SRC', - 'REG_AXXX_CP_ME_RAM_DATA', 'REG_AXXX_CP_ME_RAM_RADDR', - 'REG_AXXX_CP_ME_RAM_WADDR', 'REG_AXXX_CP_ME_RDADDR', - 'REG_AXXX_CP_ME_STATUS', 'REG_AXXX_CP_ME_VS_EVENT_ADDR', - 'REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM', - 'REG_AXXX_CP_ME_VS_EVENT_DATA', - 'REG_AXXX_CP_ME_VS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_VS_EVENT_SRC', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_DATA', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_SRC', 'REG_AXXX_CP_MIU_TAG_STAT', - 'REG_AXXX_CP_NON_PREFETCH_CNTRS', 'REG_AXXX_CP_QUEUE_THRESHOLDS', - 'REG_AXXX_CP_RB_BASE', 'REG_AXXX_CP_RB_CNTL', - 'REG_AXXX_CP_RB_RPTR', 'REG_AXXX_CP_RB_RPTR_ADDR', - 'REG_AXXX_CP_RB_RPTR_WR', 'REG_AXXX_CP_RB_WPTR', - 'REG_AXXX_CP_RB_WPTR_BASE', 'REG_AXXX_CP_RB_WPTR_DELAY', - 'REG_AXXX_CP_SCRATCH_REG0', 'REG_AXXX_CP_SCRATCH_REG1', - 'REG_AXXX_CP_SCRATCH_REG2', 'REG_AXXX_CP_SCRATCH_REG3', - 'REG_AXXX_CP_SCRATCH_REG4', 'REG_AXXX_CP_SCRATCH_REG5', - 'REG_AXXX_CP_SCRATCH_REG6', 'REG_AXXX_CP_SCRATCH_REG7', - 'REG_AXXX_CP_STAT', 'REG_AXXX_CP_STATE_DEBUG_DATA', - 'REG_AXXX_CP_STATE_DEBUG_INDEX', 'REG_AXXX_CP_STQ_AVAIL', - 'REG_AXXX_CP_STQ_ST_STAT', 'REG_AXXX_CP_ST_BASE', - 'REG_AXXX_CP_ST_BUFSZ', 'REG_AXXX_SCRATCH_ADDR', - 'REG_AXXX_SCRATCH_UMSK', 'REG_COMPARE', - 'REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM', - 'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK', - 'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT', 'REG_COMPARE_IMM', - 'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK', - 'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT', 'REG_CP_BLIT_0', - 'REG_CP_BLIT_1', 'REG_CP_BLIT_2', 'REG_CP_BLIT_3', - 'REG_CP_BLIT_4', 'REG_CP_BV_BR_COUNT_OPS_0', - 'REG_CP_BV_BR_COUNT_OPS_1', 'REG_CP_COMPUTE_CHECKPOINT_0', - 'REG_CP_COMPUTE_CHECKPOINT_1', 'REG_CP_COMPUTE_CHECKPOINT_2', - 'REG_CP_COMPUTE_CHECKPOINT_3', 'REG_CP_COMPUTE_CHECKPOINT_4', - 'REG_CP_COMPUTE_CHECKPOINT_5', 'REG_CP_COMPUTE_CHECKPOINT_6', - 'REG_CP_COMPUTE_CHECKPOINT_7', 'REG_CP_COND_EXEC_0', - 'REG_CP_COND_EXEC_1', 'REG_CP_COND_EXEC_2', 'REG_CP_COND_EXEC_3', - 'REG_CP_COND_EXEC_4', 'REG_CP_COND_EXEC_5', - 'REG_CP_COND_REG_EXEC_0', 'REG_CP_COND_REG_EXEC_2', - 'REG_CP_COND_WRITE5_0', 'REG_CP_COND_WRITE5_1', - 'REG_CP_COND_WRITE5_2', 'REG_CP_COND_WRITE5_3', - 'REG_CP_COND_WRITE5_4', 'REG_CP_COND_WRITE5_5', - 'REG_CP_COND_WRITE5_6', 'REG_CP_COND_WRITE5_7', - 'REG_CP_COND_WRITE_0', 'REG_CP_COND_WRITE_1', - 'REG_CP_COND_WRITE_2', 'REG_CP_COND_WRITE_3', - 'REG_CP_COND_WRITE_4', 'REG_CP_COND_WRITE_5', - 'REG_CP_DISPATCH_COMPUTE_0', 'REG_CP_DISPATCH_COMPUTE_1', - 'REG_CP_DISPATCH_COMPUTE_2', 'REG_CP_DISPATCH_COMPUTE_3', - 'REG_CP_DRAW_AUTO_0', 'REG_CP_DRAW_AUTO_1', 'REG_CP_DRAW_AUTO_4', - 'REG_CP_DRAW_AUTO_5', 'REG_CP_DRAW_AUTO_NUM_VERTICES_BASE', - 'REG_CP_DRAW_INDX_0', 'REG_CP_DRAW_INDX_1', 'REG_CP_DRAW_INDX_2', - 'REG_CP_DRAW_INDX_2_0', 'REG_CP_DRAW_INDX_2_1', - 'REG_CP_DRAW_INDX_2_2', 'REG_CP_DRAW_INDX_3', - 'REG_CP_DRAW_INDX_4', 'REG_CP_DRAW_INDX_OFFSET_0', - 'REG_CP_DRAW_INDX_OFFSET_1', 'REG_CP_DRAW_INDX_OFFSET_2', - 'REG_CP_DRAW_INDX_OFFSET_3', 'REG_CP_DRAW_INDX_OFFSET_4', - 'REG_CP_DRAW_INDX_OFFSET_5', 'REG_CP_DRAW_PRED_ENABLE_GLOBAL_0', - 'REG_CP_DRAW_PRED_ENABLE_LOCAL_0', 'REG_CP_DRAW_PRED_SET_0', - 'REG_CP_DRAW_PRED_SET_MEM_ADDR', 'REG_CP_EVENT_WRITE7_0', - 'REG_CP_EVENT_WRITE_0', 'REG_CP_EVENT_WRITE_1', - 'REG_CP_EVENT_WRITE_2', 'REG_CP_EVENT_WRITE_3', - 'REG_CP_EXEC_CS_0', 'REG_CP_EXEC_CS_1', 'REG_CP_EXEC_CS_2', - 'REG_CP_EXEC_CS_3', 'REG_CP_FIXED_STRIDE_DRAW_TABLE_2', - 'REG_CP_FIXED_STRIDE_DRAW_TABLE_3', - 'REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE', 'REG_CP_LOAD_STATE4_0', - 'REG_CP_LOAD_STATE4_1', 'REG_CP_LOAD_STATE4_2', - 'REG_CP_LOAD_STATE6_0', 'REG_CP_LOAD_STATE6_1', - 'REG_CP_LOAD_STATE6_2', 'REG_CP_LOAD_STATE6_EXT_SRC_ADDR', - 'REG_CP_LOAD_STATE_0', 'REG_CP_LOAD_STATE_1', 'REG_CP_MEMCPY_0', - 'REG_CP_MEMCPY_1', 'REG_CP_MEMCPY_2', 'REG_CP_MEMCPY_3', - 'REG_CP_MEMCPY_4', 'REG_CP_MEM_TO_MEM_0', 'REG_CP_MEM_TO_REG_0', - 'REG_CP_MEM_TO_REG_1', 'REG_CP_MEM_TO_REG_2', - 'REG_CP_MEM_TO_SCRATCH_MEM_0', 'REG_CP_MEM_TO_SCRATCH_MEM_1', - 'REG_CP_MEM_TO_SCRATCH_MEM_2', 'REG_CP_MEM_TO_SCRATCH_MEM_3', - 'REG_CP_MEM_WRITE_0', 'REG_CP_MEM_WRITE_1', - 'REG_CP_MODIFY_TIMESTAMP_0', 'REG_CP_PERFCOUNTER_ACTION_0', - 'REG_CP_PERFCOUNTER_ACTION_1', 'REG_CP_PERFCOUNTER_ACTION_2', - 'REG_CP_REG_RMW_0', 'REG_CP_REG_RMW_1', 'REG_CP_REG_RMW_2', - 'REG_CP_REG_TO_MEM_0', 'REG_CP_REG_TO_MEM_1', - 'REG_CP_REG_TO_MEM_2', 'REG_CP_REG_TO_MEM_OFFSET_MEM_0', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_1', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_2', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_3', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_4', - 'REG_CP_REG_TO_MEM_OFFSET_REG_0', - 'REG_CP_REG_TO_MEM_OFFSET_REG_1', - 'REG_CP_REG_TO_MEM_OFFSET_REG_2', - 'REG_CP_REG_TO_MEM_OFFSET_REG_3', 'REG_CP_REG_TO_SCRATCH_0', - 'REG_CP_REG_WRITE_0', 'REG_CP_REG_WRITE_1', 'REG_CP_REG_WRITE_2', - 'REG_CP_RESET_CONTEXT_STATE_0', 'REG_CP_SCRATCH_TO_REG_0', - 'REG_CP_SCRATCH_WRITE_0', 'REG_CP_SET_BIN_0', 'REG_CP_SET_BIN_1', - 'REG_CP_SET_BIN_2', 'REG_CP_SET_BIN_DATA5_0', - 'REG_CP_SET_BIN_DATA5_1', 'REG_CP_SET_BIN_DATA5_2', - 'REG_CP_SET_BIN_DATA5_3', 'REG_CP_SET_BIN_DATA5_4', - 'REG_CP_SET_BIN_DATA5_5', 'REG_CP_SET_BIN_DATA5_6', - 'REG_CP_SET_BIN_DATA5_7', 'REG_CP_SET_BIN_DATA5_9', - 'REG_CP_SET_BIN_DATA5_OFFSET_0', 'REG_CP_SET_BIN_DATA5_OFFSET_1', - 'REG_CP_SET_BIN_DATA5_OFFSET_2', 'REG_CP_SET_BIN_DATA5_OFFSET_3', - 'REG_CP_SET_BIN_DATA_0', 'REG_CP_SET_BIN_DATA_1', - 'REG_CP_SET_CTXSWITCH_IB_0', 'REG_CP_SET_CTXSWITCH_IB_1', - 'REG_CP_SET_CTXSWITCH_IB_2', 'REG_CP_SET_RENDER_MODE_0', - 'REG_CP_SET_RENDER_MODE_1', 'REG_CP_SET_RENDER_MODE_2', - 'REG_CP_SET_RENDER_MODE_3', 'REG_CP_SET_RENDER_MODE_4', - 'REG_CP_SET_RENDER_MODE_5', 'REG_CP_SET_RENDER_MODE_6', - 'REG_CP_SET_RENDER_MODE_7', 'REG_CP_SMMU_TABLE_UPDATE_0', - 'REG_CP_SMMU_TABLE_UPDATE_1', 'REG_CP_SMMU_TABLE_UPDATE_2', - 'REG_CP_SMMU_TABLE_UPDATE_3', 'REG_CP_START_BIN_BIN_COUNT', - 'REG_CP_START_BIN_BODY_DWORDS', 'REG_CP_START_BIN_PREFIX_ADDR', - 'REG_CP_START_BIN_PREFIX_DWORDS', 'REG_CP_THREAD_CONTROL_0', - 'REG_CP_WAIT_MEM_GTE_0', 'REG_CP_WAIT_MEM_GTE_1', - 'REG_CP_WAIT_MEM_GTE_2', 'REG_CP_WAIT_MEM_GTE_3', - 'REG_CP_WAIT_REG_MEM_0', 'REG_CP_WAIT_REG_MEM_1', - 'REG_CP_WAIT_REG_MEM_2', 'REG_CP_WAIT_REG_MEM_3', - 'REG_CP_WAIT_REG_MEM_4', 'REG_CP_WAIT_REG_MEM_5', - 'REG_CP_WAIT_TIMESTAMP_0', 'REG_CP_WAIT_TIMESTAMP_SRC_0', - 'REG_CP_WAIT_TIMESTAMP_SRC_1', 'REG_CP_WAIT_TWO_REGS_0', - 'REG_CP_WAIT_TWO_REGS_1', 'REG_CP_WAIT_TWO_REGS_2', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_1', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_2', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_3', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_4', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_PRED_TEST_CP_COND_REG_EXEC_1', - 'REG_REG_COMPARE_CP_COND_REG_EXEC_1', - 'REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1', - 'REG_RENDER_MODE_CP_COND_REG_EXEC_1', - 'REG_THREAD_MODE_CP_COND_REG_EXEC_1', - 'REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0', - 'REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR', 'RENDERING_PASS', - 'RENDER_MODE', 'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'RESTORE_IB', - 'RL_TB', 'RM6_BINNING', 'RM6_BLIT2DSCALE', 'RM6_BYPASS', - 'RM6_COMPUTE', 'RM6_ENDVIS', 'RM6_GMEM', 'RM6_IB1LIST_END', - 'RM6_IB1LIST_START', 'RM6_IFPC_DISABLE', 'RM6_IFPC_ENABLE', - 'RM6_RESOLVE', 'RM6_YIELD', 'ROP_AND', 'ROP_AND_INVERTED', - 'ROP_AND_REVERSE', 'ROP_CLEAR', 'ROP_COPY', 'ROP_COPY_INVERTED', - 'ROP_EQUIV', 'ROP_INVERT', 'ROP_NAND', 'ROP_NOOP', 'ROP_NOR', - 'ROP_OR', 'ROP_OR_INVERTED', 'ROP_OR_REVERSE', 'ROP_SET', - 'ROP_XOR', 'ROTATE_0', 'ROTATE_180', 'ROTATE_270', 'ROTATE_90', - 'ROTATE_HFLIP', 'ROTATE_VFLIP', 'RST_PIX_CNT', 'RST_VTX_CNT', - 'SAVE_IB', 'SB4_CS_SHADER', 'SB4_CS_SSBO', 'SB4_CS_TEX', - 'SB4_DS_SHADER', 'SB4_DS_TEX', 'SB4_FS_SHADER', 'SB4_FS_TEX', - 'SB4_GS_SHADER', 'SB4_GS_TEX', 'SB4_HS_SHADER', 'SB4_HS_TEX', - 'SB4_SSBO', 'SB4_VS_SHADER', 'SB4_VS_TEX', 'SB6_CS_IBO', - 'SB6_CS_SHADER', 'SB6_CS_TEX', 'SB6_DS_SHADER', 'SB6_DS_TEX', - 'SB6_FS_SHADER', 'SB6_FS_TEX', 'SB6_GS_SHADER', 'SB6_GS_TEX', - 'SB6_HS_SHADER', 'SB6_HS_TEX', 'SB6_IBO', 'SB6_VS_SHADER', - 'SB6_VS_TEX', 'SB_COMPUTE_SHADER', 'SB_FRAG_MIPADDR', - 'SB_FRAG_SHADER', 'SB_FRAG_TEX', 'SB_GEOM_SHADER', - 'SB_VERT_MIPADDR', 'SB_VERT_SHADER', 'SB_VERT_TEX', 'SC_WAIT_WC', - 'SECURE_SAVE_ADDR', 'SINGLE', 'SMMU_INFO', 'SOURCE_REG', - 'SOURCE_SCRATCH_MEM', 'SS4_DIRECT', 'SS4_INDIRECT', - 'SS6_BINDLESS', 'SS6_DIRECT', 'SS6_INDIRECT', 'SS6_UBO', - 'SS_DIRECT', 'SS_INDIRECT', 'SS_INDIRECT_STM', 'SS_INDIRECT_TCM', - 'SS_INVALID_ALL_IC', 'SS_INVALID_PART_IC', 'ST4_CONSTANTS', - 'ST4_SHADER', 'ST4_UBO', 'ST6_CONSTANTS', 'ST6_IBO', 'ST6_SHADER', - 'ST6_UBO', 'START_COMPUTE_CTRS', 'START_FRAGMENT_CTRS', - 'START_PRIMITIVE_CTRS', 'STAT_EVENT', 'STENCIL_DECR_CLAMP', - 'STENCIL_DECR_WRAP', 'STENCIL_INCR_CLAMP', 'STENCIL_INCR_WRAP', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_REPLACE', - 'STENCIL_ZERO', 'STOP_COMPUTE_CTRS', 'STOP_FRAGMENT_CTRS', - 'STOP_PRIMITIVE_CTRS', 'ST_CONSTANTS', 'ST_SHADER', - 'TESS_CCW_TRIS', 'TESS_CW_TRIS', 'TESS_EQUAL', - 'TESS_FRACTIONAL_EVEN', 'TESS_FRACTIONAL_ODD', 'TESS_ISOLINES', - 'TESS_LINES', 'TESS_POINTS', 'TESS_QUADS', 'TESS_TRIANGLES', - 'TEX_PREFETCH_GATHER4A', 'TEX_PREFETCH_GATHER4B', - 'TEX_PREFETCH_GATHER4G', 'TEX_PREFETCH_GATHER4R', - 'TEX_PREFETCH_SAM', 'TEX_PREFETCH_UNK0', 'TEX_PREFETCH_UNK6', - 'TEX_PREFETCH_UNK7', 'THREAD128', 'THREAD64', 'THREAD_MODE', - 'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'TILE6_2', - 'TILE6_3', 'TILE6_LINEAR', 'TILE_FLUSH', 'TRACK_CNTL_REG', - 'TRACK_LRZ', 'TRACK_RENDER_CNTL', 'TS_WAIT_GE_32B', - 'TS_WAIT_GE_64B', 'TS_WAIT_GE_TIMESTAMP_SUM', 'TS_WAIT_ONCHIP', - 'TS_WAIT_RAM', 'TWO_QUADS', 'TYPE_TILED', 'TYPE_WRITER', 'UNK_2C', - 'UNK_2D', 'UNK_40', 'UNK_EVENT_WRITE', 'UNK_STRM_ADDRESS', - 'UNK_STRM_SIZE_ADDRESS', 'USE_VISIBILITY', 'VIZQUERY_END', - 'VIZQUERY_START', 'VS_DEALLOC', 'VS_DONE_TS', 'VS_FETCH_DONE', - 'WRITE_ALWAYS', 'WRITE_EQ', 'WRITE_GE', 'WRITE_GT', 'WRITE_LE', - 'WRITE_LT', 'WRITE_NE', 'WRITE_PRIMITIVE_COUNTS', 'WT_DONE_TS', - 'WXYZ', 'WZYX', 'XYZW', 'YIELD_RESTORE_IB', 'ZPASS_DONE', 'ZYXW', - 'a3xx_color_swap', 'a3xx_instrbuffermode', 'a3xx_msaa_samples', - 'a3xx_rb_blend_opcode', 'a3xx_render_mode', 'a3xx_rop_code', - 'a3xx_threadmode', 'a3xx_threadsize', 'a4xx_index_size', - 'a4xx_state_block', 'a4xx_state_src', 'a4xx_state_type', - 'a4xx_tess_spacing', 'a5xx_address_mode', 'a5xx_line_mode', - 'a6xx_2d_ifmt', 'a6xx_bindless_descriptor_size', - 'a6xx_buffers_location', 'a6xx_ccu_cache_size', - 'a6xx_ccu_perfcounter_select', 'a6xx_cmp_perfcounter_select', - 'a6xx_cp_perfcounter_select', 'a6xx_debugbus_id', - 'a6xx_depth_format', 'a6xx_draw_indirect_opcode', 'a6xx_format', - 'a6xx_fragcoord_sample_mode', 'a6xx_hlsq_perfcounter_select', - 'a6xx_isam_mode', 'a6xx_lrz_dir_status', - 'a6xx_lrz_perfcounter_select', 'a6xx_marker', 'a6xx_patch_type', - 'a6xx_pc_perfcounter_select', 'a6xx_polygon_mode', - 'a6xx_ras_perfcounter_select', 'a6xx_raster_direction', - 'a6xx_raster_mode', 'a6xx_rb_perfcounter_select', - 'a6xx_rbbm_perfcounter_select', 'a6xx_reduction_mode', - 'a6xx_render_mode', 'a6xx_rotation', 'a6xx_sequenced_thread_dist', - 'a6xx_shader_id', 'a6xx_single_prim_mode', - 'a6xx_sp_perfcounter_select', 'a6xx_state_block', - 'a6xx_state_src', 'a6xx_state_type', 'a6xx_tess_output', - 'a6xx_tess_spacing', 'a6xx_tex_aniso', 'a6xx_tex_clamp', - 'a6xx_tex_filter', 'a6xx_tex_prefetch_cmd', 'a6xx_tex_swiz', - 'a6xx_tex_type', 'a6xx_threadsize', 'a6xx_tile_mode', - 'a6xx_tp_perfcounter_select', 'a6xx_tse_perfcounter_select', - 'a6xx_uche_perfcounter_select', 'a6xx_varying_interp_mode', - 'a6xx_varying_ps_repl_mode', 'a6xx_vfd_perfcounter_select', - 'a6xx_vpc_perfcounter_select', 'a6xx_vsc_perfcounter_select', - 'a6xx_ztest_mode', 'a7xx_ccu_perfcounter_select', 'a7xx_cluster', - 'a7xx_cmp_perfcounter_select', 'a7xx_cp_perfcounter_select', - 'a7xx_cs_yalign', 'a7xx_debugbus_id', - 'a7xx_gbif_perfcounter_select', 'a7xx_hlsq_perfcounter_select', - 'a7xx_lrz_perfcounter_select', 'a7xx_pc_perfcounter_select', - 'a7xx_pipe', 'a7xx_ras_perfcounter_select', - 'a7xx_rb_perfcounter_select', 'a7xx_rbbm_perfcounter_select', - 'a7xx_sp_perfcounter_select', 'a7xx_state_location', - 'a7xx_statetype_id', 'a7xx_tp_perfcounter_select', - 'a7xx_tse_perfcounter_select', 'a7xx_uche_perfcounter_select', - 'a7xx_ufc_perfcounter_select', 'a7xx_vfd_perfcounter_select', - 'a7xx_vpc_perfcounter_select', 'a7xx_vsc_perfcounter_select', - 'adreno_compare_func', 'adreno_pa_su_sc_draw', - 'adreno_pm4_packet_type', 'adreno_pm4_type3_packets', - 'adreno_rb_blend_factor', 'adreno_rb_copy_control_mode', - 'adreno_rb_depth_format', 'adreno_rb_dither_mode', - 'adreno_rb_surface_endian', 'adreno_state_block', - 'adreno_state_src', 'adreno_state_type', 'adreno_stencil_op', - 'chip', 'compare_mode', 'cp_blit_cmd', 'cp_cond_function', - 'cp_draw_pred_src', 'cp_draw_pred_test', 'cp_thread', - 'ctxswitch_ib', 'event_write_dst', 'event_write_src', - 'pc_di_face_cull_sel', 'pc_di_index_size', 'pc_di_primtype', - 'pc_di_src_sel', 'pc_di_vis_cull_mode', 'pipe_count_op', - 'poll_memory_type', 'pseudo_reg', 'reg_tracker', - 'render_mode_cmd', 'source_type', 'timestamp_op', 'ts_wait_type', - 'ts_wait_value_src', 'vgt_event_type'] -def CP_LOAD_STATE_0_DST_OFF(val): return (val << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK -def CP_LOAD_STATE_0_STATE_SRC(val): return (val << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK -def CP_LOAD_STATE_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK -def CP_LOAD_STATE_0_NUM_UNIT(val): return (val << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK -def CP_LOAD_STATE_1_STATE_TYPE(val): return (val << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK -def CP_LOAD_STATE_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE4_0_DST_OFF(val): return (val << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK -def CP_LOAD_STATE4_0_STATE_SRC(val): return (val << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK -def CP_LOAD_STATE4_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK -def CP_LOAD_STATE4_0_NUM_UNIT(val): return (val << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK -def CP_LOAD_STATE4_1_STATE_TYPE(val): return (val << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK -def CP_LOAD_STATE4_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK -def CP_LOAD_STATE6_0_DST_OFF(val): return (val << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK -def CP_LOAD_STATE6_0_STATE_TYPE(val): return (val << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK -def CP_LOAD_STATE6_0_STATE_SRC(val): return (val << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK -def CP_LOAD_STATE6_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK -def CP_LOAD_STATE6_0_NUM_UNIT(val): return (val << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK -def CP_LOAD_STATE6_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK -def CP_DRAW_INDX_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK -def CP_DRAW_INDX_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK -def CP_DRAW_INDX_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK -def CP_DRAW_INDX_1_VIS_CULL(val): return (val << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK -def CP_DRAW_INDX_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK -def CP_DRAW_INDX_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK -def CP_DRAW_INDX_3_INDX_BASE(val): return (val << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK -def CP_DRAW_INDX_4_INDX_SIZE(val): return (val << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK -def CP_DRAW_INDX_2_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK -def CP_DRAW_INDX_2_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK -def CP_DRAW_INDX_2_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK -def CP_DRAW_INDX_2_1_VIS_CULL(val): return (val << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK -def CP_DRAW_INDX_2_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK -def CP_DRAW_INDX_2_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_2_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK -def CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK -def CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK -def CP_DRAW_INDX_OFFSET_0_VIS_CULL(val): return (val << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK -def CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK -def CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK -def CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_OFFSET_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK -def CP_DRAW_INDX_OFFSET_3_FIRST_INDX(val): return (val << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK -def A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK -def A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK -def A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK -def CP_DRAW_INDX_OFFSET_4_INDX_BASE(val): return (val << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK -def CP_DRAW_INDX_OFFSET_5_INDX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK -def A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK -def A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK -def A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK -def A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK -def A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK -def A4XX_CP_DRAW_INDIRECT_1_INDIRECT(val): return (val << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK -def A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK -def A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK -def CP_DRAW_AUTO_0_PRIM_TYPE(val): return (val << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK -def CP_DRAW_AUTO_0_SOURCE_SELECT(val): return (val << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK -def CP_DRAW_AUTO_0_VIS_CULL(val): return (val << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK -def CP_DRAW_AUTO_0_INDEX_SIZE(val): return (val << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK -def CP_DRAW_AUTO_0_PATCH_TYPE(val): return (val << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK -def CP_DRAW_AUTO_1_NUM_INSTANCES(val): return (val << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK -def CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(val): return (val << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK -def CP_DRAW_AUTO_5_STRIDE(val): return (val << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK -def CP_DRAW_PRED_SET_0_SRC(val): return (val << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK -def CP_DRAW_PRED_SET_0_TEST(val): return (val << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK -def CP_SET_DRAW_STATE__0_COUNT(val): return (val << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK -def CP_SET_DRAW_STATE__0_GROUP_ID(val): return (val << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK -def CP_SET_DRAW_STATE__1_ADDR_LO(val): return (val << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK -def CP_SET_DRAW_STATE__2_ADDR_HI(val): return (val << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK -def CP_SET_BIN_1_X1(val): return (val << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK -def CP_SET_BIN_1_Y1(val): return (val << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK -def CP_SET_BIN_2_X2(val): return (val << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK -def CP_SET_BIN_2_Y2(val): return (val << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK -def CP_SET_BIN_DATA_0_BIN_DATA_ADDR(val): return (val << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK -def CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(val): return (val << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK -def CP_SET_BIN_DATA5_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK -def CP_SET_BIN_DATA5_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK -def CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(val): return (val << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK -def CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(val): return (val << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK -def CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(val): return (val << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK -def CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(val): return (val << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK -def CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(val): return (val << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK -def CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(val): return (val << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK -def CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK -def CP_SET_BIN_DATA5_OFFSET_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK -def CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK -def CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK -def CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK -def CP_REG_RMW_0_DST_REG(val): return (val << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK -def CP_REG_RMW_0_ROTATE(val): return (val << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK -def CP_REG_RMW_1_SRC0(val): return (val << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK -def CP_REG_RMW_2_SRC1(val): return (val << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK -def CP_REG_TO_MEM_0_REG(val): return (val << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK -def CP_REG_TO_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK -def CP_REG_TO_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK -def CP_REG_TO_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_REG_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK -def CP_REG_TO_MEM_OFFSET_REG_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK -def CP_REG_TO_MEM_OFFSET_REG_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK -def CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(val): return (val << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK -def CP_REG_TO_MEM_OFFSET_MEM_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK -def CP_REG_TO_MEM_OFFSET_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK -def CP_REG_TO_MEM_OFFSET_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK -def CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK -def CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK -def CP_MEM_TO_REG_0_REG(val): return (val << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK -def CP_MEM_TO_REG_0_CNT(val): return (val << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK -def CP_MEM_TO_REG_1_SRC(val): return (val << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK -def CP_MEM_TO_REG_2_SRC_HI(val): return (val << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK -def CP_MEMCPY_0_DWORDS(val): return (val << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK -def CP_MEMCPY_1_SRC_LO(val): return (val << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK -def CP_MEMCPY_2_SRC_HI(val): return (val << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK -def CP_MEMCPY_3_DST_LO(val): return (val << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK -def CP_MEMCPY_4_DST_HI(val): return (val << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK -def CP_REG_TO_SCRATCH_0_REG(val): return (val << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK -def CP_REG_TO_SCRATCH_0_SCRATCH(val): return (val << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK -def CP_REG_TO_SCRATCH_0_CNT(val): return (val << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK -def CP_SCRATCH_TO_REG_0_REG(val): return (val << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK -def CP_SCRATCH_TO_REG_0_SCRATCH(val): return (val << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK -def CP_SCRATCH_TO_REG_0_CNT(val): return (val << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK -def CP_SCRATCH_WRITE_0_SCRATCH(val): return (val << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK -def CP_MEM_WRITE_0_ADDR_LO(val): return (val << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK -def CP_MEM_WRITE_1_ADDR_HI(val): return (val << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK -def CP_COND_WRITE_0_FUNCTION(val): return (val << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK -def CP_COND_WRITE_1_POLL_ADDR(val): return (val << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK -def CP_COND_WRITE_2_REF(val): return (val << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK -def CP_COND_WRITE_3_MASK(val): return (val << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK -def CP_COND_WRITE_4_WRITE_ADDR(val): return (val << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK -def CP_COND_WRITE_5_WRITE_DATA(val): return (val << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK -def CP_COND_WRITE5_0_FUNCTION(val): return (val << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK -def CP_COND_WRITE5_0_POLL(val): return (val << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK -def CP_COND_WRITE5_1_POLL_ADDR_LO(val): return (val << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK -def CP_COND_WRITE5_2_POLL_ADDR_HI(val): return (val << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK -def CP_COND_WRITE5_3_REF(val): return (val << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK -def CP_COND_WRITE5_4_MASK(val): return (val << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK -def CP_COND_WRITE5_5_WRITE_ADDR_LO(val): return (val << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK -def CP_COND_WRITE5_6_WRITE_ADDR_HI(val): return (val << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK -def CP_COND_WRITE5_7_WRITE_DATA(val): return (val << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK -def CP_WAIT_MEM_GTE_0_RESERVED(val): return (val << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK -def CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(val): return (val << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK -def CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(val): return (val << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK -def CP_WAIT_MEM_GTE_3_REF(val): return (val << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK -def CP_WAIT_REG_MEM_0_FUNCTION(val): return (val << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK -def CP_WAIT_REG_MEM_0_POLL(val): return (val << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK -def CP_WAIT_REG_MEM_1_POLL_ADDR_LO(val): return (val << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK -def CP_WAIT_REG_MEM_2_POLL_ADDR_HI(val): return (val << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK -def CP_WAIT_REG_MEM_3_REF(val): return (val << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK -def CP_WAIT_REG_MEM_4_MASK(val): return (val << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK -def CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(val): return (val << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK -def CP_WAIT_TWO_REGS_0_REG0(val): return (val << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK -def CP_WAIT_TWO_REGS_1_REG1(val): return (val << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK -def CP_WAIT_TWO_REGS_2_REF(val): return (val << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK -def CP_DISPATCH_COMPUTE_1_X(val): return (val << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK -def CP_DISPATCH_COMPUTE_2_Y(val): return (val << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK -def CP_DISPATCH_COMPUTE_3_Z(val): return (val << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK -def CP_SET_RENDER_MODE_0_MODE(val): return (val << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK -def CP_SET_RENDER_MODE_1_ADDR_0_LO(val): return (val << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK -def CP_SET_RENDER_MODE_2_ADDR_0_HI(val): return (val << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK -def CP_SET_RENDER_MODE_5_ADDR_1_LEN(val): return (val << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK -def CP_SET_RENDER_MODE_6_ADDR_1_LO(val): return (val << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK -def CP_SET_RENDER_MODE_7_ADDR_1_HI(val): return (val << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK -def CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(val): return (val << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK -def CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(val): return (val << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK -def CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(val): return (val << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK -def CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(val): return (val << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK -def CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(val): return (val << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK -def CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(val): return (val << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK -def CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(val): return (val << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK -def CP_EVENT_WRITE_0_EVENT(val): return (val << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK -def CP_EVENT_WRITE_1_ADDR_0_LO(val): return (val << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK -def CP_EVENT_WRITE_2_ADDR_0_HI(val): return (val << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK -def CP_EVENT_WRITE7_0_EVENT(val): return (val << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK -def CP_EVENT_WRITE7_0_WRITE_SRC(val): return (val << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK -def CP_EVENT_WRITE7_0_WRITE_DST(val): return (val << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK -def CP_BLIT_0_OP(val): return (val << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK -def CP_BLIT_1_SRC_X1(val): return (val << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK -def CP_BLIT_1_SRC_Y1(val): return (val << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK -def CP_BLIT_2_SRC_X2(val): return (val << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK -def CP_BLIT_2_SRC_Y2(val): return (val << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK -def CP_BLIT_3_DST_X1(val): return (val << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK -def CP_BLIT_3_DST_Y1(val): return (val << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK -def CP_BLIT_4_DST_X2(val): return (val << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK -def CP_BLIT_4_DST_Y2(val): return (val << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK -def CP_EXEC_CS_1_NGROUPS_X(val): return (val << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK -def CP_EXEC_CS_2_NGROUPS_Y(val): return (val << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK -def CP_EXEC_CS_3_NGROUPS_Z(val): return (val << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK -def A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK -def A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK -def A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK -def A6XX_CP_SET_MARKER_0_MODE(val): return (val << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK -def A6XX_CP_SET_MARKER_0_MARKER(val): return (val << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK -def A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(val): return (val << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK -def A6XX_CP_SET_PSEUDO_REG__1_LO(val): return (val << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK -def A6XX_CP_SET_PSEUDO_REG__2_HI(val): return (val << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK -def A6XX_CP_REG_TEST_0_REG(val): return (val << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK -def A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(val): return (val << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK -def A6XX_CP_REG_TEST_0_SOURCE(val): return (val << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK -def A6XX_CP_REG_TEST_0_BIT(val): return (val << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK -def A6XX_CP_REG_TEST_0_PRED_BIT(val): return (val << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK -def CP_COND_REG_EXEC_0_REG0(val): return (val << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK -def CP_COND_REG_EXEC_0_PRED_BIT(val): return (val << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK -def CP_COND_REG_EXEC_0_MODE(val): return (val << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK -def PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(val): return (val << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK -def REG_COMPARE_CP_COND_REG_EXEC_1_REG1(val): return (val << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK -def RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK -def REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(val): return (val << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK -def THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK -def CP_COND_REG_EXEC_2_DWORDS(val): return (val << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK -def CP_COND_EXEC_0_ADDR0_LO(val): return (val << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK -def CP_COND_EXEC_1_ADDR0_HI(val): return (val << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK -def CP_COND_EXEC_2_ADDR1_LO(val): return (val << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK -def CP_COND_EXEC_3_ADDR1_HI(val): return (val << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK -def CP_COND_EXEC_4_REF(val): return (val << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK -def CP_COND_EXEC_5_DWORDS(val): return (val << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK -def CP_SET_CTXSWITCH_IB_0_ADDR_LO(val): return (val << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK -def CP_SET_CTXSWITCH_IB_1_ADDR_HI(val): return (val << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK -def CP_SET_CTXSWITCH_IB_2_DWORDS(val): return (val << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK -def CP_SET_CTXSWITCH_IB_2_TYPE(val): return (val << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK -def CP_REG_WRITE_0_TRACKER(val): return (val << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK -def CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(val): return (val << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK -def CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(val): return (val << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK -def CP_SMMU_TABLE_UPDATE_1_ASID(val): return (val << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK -def CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(val): return (val << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK -def CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(val): return (val << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK -def CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK -def CP_WAIT_TIMESTAMP_0_WAIT_DST(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK -def CP_BV_BR_COUNT_OPS_0_OP(val): return (val << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK -def CP_BV_BR_COUNT_OPS_1_BR_OFFSET(val): return (val << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK -def CP_MODIFY_TIMESTAMP_0_ADD(val): return (val << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK -def CP_MODIFY_TIMESTAMP_0_OP(val): return (val << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK -def CP_MEM_TO_SCRATCH_MEM_0_CNT(val): return (val << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK -def CP_MEM_TO_SCRATCH_MEM_1_OFFSET(val): return (val << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK -def CP_MEM_TO_SCRATCH_MEM_2_SRC(val): return (val << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK -def CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(val): return (val << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK -def CP_THREAD_CONTROL_0_THREAD(val): return (val << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK -def AXXX_CP_RB_CNTL_BUFSZ(val): return (val << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK -def AXXX_CP_RB_CNTL_BLKSZ(val): return (val << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK -def AXXX_CP_RB_CNTL_BUF_SWAP(val): return (val << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK -def AXXX_CP_RB_RPTR_ADDR_SWAP(val): return (val << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK -def AXXX_CP_RB_RPTR_ADDR_ADDR(val): return (val << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK -def AXXX_CP_MEQ_THRESHOLDS_MEQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK -def AXXX_CP_MEQ_THRESHOLDS_ROQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK -def AXXX_CP_CSQ_AVAIL_RING(val): return (val << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK -def AXXX_CP_CSQ_AVAIL_IB1(val): return (val << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK -def AXXX_CP_CSQ_AVAIL_IB2(val): return (val << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK -def AXXX_CP_STQ_AVAIL_ST(val): return (val << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK -def AXXX_CP_MEQ_AVAIL_MEQ(val): return (val << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK -def AXXX_SCRATCH_UMSK_UMSK(val): return (val << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK -def AXXX_SCRATCH_UMSK_SWAP(val): return (val << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK -def AXXX_CP_CSQ_RB_STAT_RPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK -def AXXX_CP_CSQ_RB_STAT_WPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK -def AXXX_CP_CSQ_IB1_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK -def AXXX_CP_CSQ_IB1_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK -def AXXX_CP_CSQ_IB2_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK -def AXXX_CP_CSQ_IB2_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK -def A6XX_CP_PROTECT_REG_BASE_ADDR(val): return (val << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK -def A6XX_CP_PROTECT_REG_MASK_LEN(val): return (val << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK -def A6XX_CP_ROQ_RB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK -def A6XX_CP_ROQ_RB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK -def A6XX_CP_ROQ_IB1_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK -def A6XX_CP_ROQ_IB1_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK -def A6XX_CP_ROQ_IB2_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK -def A6XX_CP_ROQ_IB2_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK -def A6XX_CP_ROQ_SDS_STAT_RPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK -def A6XX_CP_ROQ_SDS_STAT_WPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK -def A6XX_CP_ROQ_MRB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK -def A6XX_CP_ROQ_MRB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK -def A6XX_CP_ROQ_VSD_STAT_RPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK -def A6XX_CP_ROQ_VSD_STAT_WPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK -def A6XX_CP_ROQ_AVAIL_RB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK -def A6XX_CP_ROQ_AVAIL_IB1_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK -def A6XX_CP_ROQ_AVAIL_IB2_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK -def A6XX_CP_ROQ_AVAIL_SDS_REM(val): return (val << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK -def A6XX_CP_ROQ_AVAIL_MRB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK -def A6XX_CP_ROQ_AVAIL_VSD_REM(val): return (val << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK -def A7XX_CP_APERTURE_CNTL_HOST_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK -def A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK -def A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK -def A7XX_CP_APERTURE_CNTL_CD_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK -def A7XX_CP_APERTURE_CNTL_CD_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK -def A7XX_CP_APERTURE_CNTL_CD_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK -def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK -def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK -def A6XX_UCHE_CLIENT_PF_PERFSEL(val): return (val << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK -def A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK -def A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK -def A6XX_VSC_BIN_SIZE_WIDTH(val): return (val << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK -def A6XX_VSC_BIN_SIZE_HEIGHT(val): return (val << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK -def A6XX_VSC_BIN_COUNT_NX(val): return (val << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK -def A6XX_VSC_BIN_COUNT_NY(val): return (val << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK -def A6XX_VSC_PIPE_CONFIG_REG_X(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK -def A6XX_VSC_PIPE_CONFIG_REG_Y(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK -def A6XX_VSC_PIPE_CONFIG_REG_W(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK -def A6XX_VSC_PIPE_CONFIG_REG_H(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK -def A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_VS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_DS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_GS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_CNTL_COORD_MASK(val): return (val << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK -def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK -def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK -def A6XX_GRAS_CL_VPORT_XOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK -def A6XX_GRAS_CL_VPORT_XSCALE(val): return (val << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK -def A6XX_GRAS_CL_VPORT_YOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK -def A6XX_GRAS_CL_VPORT_YSCALE(val): return (val << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK -def A6XX_GRAS_CL_VPORT_ZOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK -def A6XX_GRAS_CL_VPORT_ZSCALE(val): return (val << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK -def A6XX_GRAS_CL_Z_CLAMP_MIN(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK -def A6XX_GRAS_CL_Z_CLAMP_MAX(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK -def A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(val): return (val << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK -def A6XX_GRAS_SU_CNTL_LINE_MODE(val): return (val << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK -def A6XX_GRAS_SU_CNTL_UNK15(val): return (val << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK -def A6XX_GRAS_SU_CNTL_UNK20(val): return (val << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK -def A6XX_GRAS_SU_POINT_MINMAX_MIN(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK -def A6XX_GRAS_SU_POINT_MINMAX_MAX(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK -def A6XX_GRAS_SU_POINT_SIZE(val): return (val << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK -def A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK -def A6XX_GRAS_SU_POLY_OFFSET_SCALE(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK -def A6XX_GRAS_SU_POLY_OFFSET_OFFSET(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK -def A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK -def A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK -def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK -def A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK -def A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(val): return (val << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK -def A6XX_GRAS_SC_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK -def A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK -def A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(val): return (val << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK -def A6XX_GRAS_SC_CNTL_ROTATION(val): return (val << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK -def A6XX_GRAS_BIN_CONTROL_BINW(val): return (val << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK -def A6XX_GRAS_BIN_CONTROL_BINH(val): return (val << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK -def A6XX_GRAS_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK -def A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK -def A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK -def A6XX_GRAS_LRZ_CNTL_DIR(val): return (val << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK -def A6XX_GRAS_LRZ_CNTL_Z_FUNC(val): return (val << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK -def A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK -def A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(val): return (val << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK -def A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK -def A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK -def A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(val): return (val << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK -def A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK -def A6XX_GRAS_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK -def A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK -def A6XX_GRAS_2D_BLIT_CNTL_MASK(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK -def A6XX_GRAS_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK -def A6XX_GRAS_2D_SRC_TL_X(val): return (val << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK -def A6XX_GRAS_2D_SRC_BR_X(val): return (val << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK -def A6XX_GRAS_2D_SRC_TL_Y(val): return (val << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK -def A6XX_GRAS_2D_SRC_BR_Y(val): return (val << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK -def A6XX_GRAS_2D_DST_TL_X(val): return (val << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK -def A6XX_GRAS_2D_DST_TL_Y(val): return (val << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK -def A6XX_GRAS_2D_DST_BR_X(val): return (val << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK -def A6XX_GRAS_2D_DST_BR_Y(val): return (val << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_1_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_2_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK -def A6XX_RB_BIN_CONTROL_BINW(val): return (val << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK -def A6XX_RB_BIN_CONTROL_BINH(val): return (val << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK -def A6XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK -def A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK -def A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A7XX_RB_BIN_CONTROL_BINW(val): return (val << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK -def A7XX_RB_BIN_CONTROL_BINH(val): return (val << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK -def A7XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK -def A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK -def A6XX_RB_RENDER_CNTL_UNK8(val): return (val << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK -def A6XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK -def A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK -def A6XX_RB_RENDER_CNTL_FLAG_MRTS(val): return (val << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK -def A7XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK -def A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK -def A6XX_RB_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_RB_RENDER_CONTROL0_COORD_MASK(val): return (val << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK -def A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK -def A6XX_RB_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK -def A6XX_RB_RENDER_COMPONENTS_RT0(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK -def A6XX_RB_RENDER_COMPONENTS_RT1(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK -def A6XX_RB_RENDER_COMPONENTS_RT2(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK -def A6XX_RB_RENDER_COMPONENTS_RT3(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK -def A6XX_RB_RENDER_COMPONENTS_RT4(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK -def A6XX_RB_RENDER_COMPONENTS_RT5(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK -def A6XX_RB_RENDER_COMPONENTS_RT6(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK -def A6XX_RB_RENDER_COMPONENTS_RT7(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK -def A6XX_RB_MRT_CONTROL_ROP_CODE(val): return (val << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK -def A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(val): return (val << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK -def A6XX_RB_MRT_PITCH(val): return (val << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK -def A6XX_RB_MRT_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK -def A6XX_RB_BLEND_RED_F32(val): return (val << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK -def A6XX_RB_BLEND_GREEN_F32(val): return (val << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK -def A6XX_RB_BLEND_BLUE_F32(val): return (val << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK -def A6XX_RB_BLEND_ALPHA_F32(val): return (val << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK -def A6XX_RB_ALPHA_CONTROL_ALPHA_REF(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK -def A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK -def A6XX_RB_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK -def A6XX_RB_BLEND_CNTL_SAMPLE_MASK(val): return (val << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK -def A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK -def A6XX_RB_DEPTH_CNTL_ZFUNC(val): return (val << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK -def A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK -def A6XX_RB_DEPTH_BUFFER_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK -def A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK -def A6XX_RB_Z_BOUNDS_MIN(val): return (val << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK -def A6XX_RB_Z_BOUNDS_MAX(val): return (val << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK -def A6XX_RB_STENCIL_CONTROL_FUNC(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK -def A6XX_RB_STENCIL_CONTROL_FAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK -def A6XX_RB_STENCIL_CONTROL_ZPASS(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK -def A6XX_RB_STENCIL_CONTROL_ZFAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK -def A6XX_RB_STENCIL_CONTROL_FUNC_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK -def A6XX_RB_STENCIL_CONTROL_FAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK -def A6XX_RB_STENCIL_CONTROL_ZPASS_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK -def A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK -def A7XX_RB_STENCIL_INFO_TILEMODE(val): return (val << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK -def A6XX_RB_STENCIL_BUFFER_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK -def A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK -def A6XX_RB_STENCILREF_REF(val): return (val << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK -def A6XX_RB_STENCILREF_BFREF(val): return (val << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK -def A6XX_RB_STENCILMASK_MASK(val): return (val << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK -def A6XX_RB_STENCILMASK_BFMASK(val): return (val << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK -def A6XX_RB_STENCILWRMASK_WRMASK(val): return (val << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK -def A6XX_RB_STENCILWRMASK_BFWRMASK(val): return (val << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK -def A6XX_RB_WINDOW_OFFSET_X(val): return (val << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK -def A6XX_RB_WINDOW_OFFSET_Y(val): return (val << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK -def A6XX_RB_Z_CLAMP_MIN(val): return (val << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK -def A6XX_RB_Z_CLAMP_MAX(val): return (val << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK -def A6XX_RB_UNKNOWN_88D0_UNK0(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK -def A6XX_RB_UNKNOWN_88D0_UNK16(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK -def A6XX_RB_BLIT_SCISSOR_TL_X(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK -def A6XX_RB_BLIT_SCISSOR_TL_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK -def A6XX_RB_BLIT_SCISSOR_BR_X(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK -def A6XX_RB_BLIT_SCISSOR_BR_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK -def A6XX_RB_BIN_CONTROL2_BINW(val): return (val << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK -def A6XX_RB_BIN_CONTROL2_BINH(val): return (val << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK -def A6XX_RB_WINDOW_OFFSET2_X(val): return (val << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK -def A6XX_RB_WINDOW_OFFSET2_Y(val): return (val << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK -def A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_BLIT_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK -def A6XX_RB_BLIT_DST_INFO_SAMPLES(val): return (val << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK -def A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK -def A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK -def A6XX_RB_BLIT_DST_PITCH(val): return (val << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK -def A6XX_RB_BLIT_DST_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK -def A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK -def A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_BLIT_INFO_CLEAR_MASK(val): return (val << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK -def A6XX_RB_BLIT_INFO_LAST(val): return (val << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK -def A6XX_RB_BLIT_INFO_BUFFER_ID(val): return (val << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK -def A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK -def A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK -def A7XX_RB_CCU_CNTL2_COLOR_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK -def A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK -def A6XX_RB_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK -def A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK -def A6XX_RB_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK -def A6XX_RB_2D_BLIT_CNTL_MASK(val): return (val << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK -def A6XX_RB_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK -def A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK -def A6XX_RB_2D_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK -def A6XX_RB_2D_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK -def A6XX_RB_2D_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK -def A6XX_RB_2D_DST_INFO_SAMPLES(val): return (val << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK -def A6XX_RB_2D_DST_INFO_UNK23(val): return (val << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK -def A6XX_RB_2D_DST_PITCH(val): return (val << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK -def A6XX_RB_2D_DST_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK -def A6XX_RB_2D_DST_FLAGS_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK -def A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK -def A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK -def A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK -def A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK -def A6XX_RB_CCU_CNTL_DEPTH_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK -def A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK -def A6XX_RB_CCU_CNTL_COLOR_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK -def A6XX_RB_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK -def A6XX_RB_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK -def A6XX_RB_NC_MODE_CNTL_UNK12(val): return (val << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK -def A6XX_VPC_GS_PARAM_LINELENGTHLOC(val): return (val << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_POLYGON_MODE_MODE(val): return (val << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK -def A7XX_VPC_MULTIVIEW_CNTL_VIEWS(val): return (val << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_VPC_SO_CNTL_ADDR(val): return (val << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK -def A6XX_VPC_SO_PROG_A_BUF(val): return (val << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK -def A6XX_VPC_SO_PROG_A_OFF(val): return (val << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK -def A6XX_VPC_SO_PROG_B_BUF(val): return (val << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK -def A6XX_VPC_SO_PROG_B_OFF(val): return (val << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK -def A6XX_VPC_VS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_VS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK -def A6XX_VPC_VS_PACK_PSIZELOC(val): return (val << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK -def A6XX_VPC_VS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK -def A6XX_VPC_GS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_GS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK -def A6XX_VPC_GS_PACK_PSIZELOC(val): return (val << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK -def A6XX_VPC_GS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK -def A6XX_VPC_DS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_DS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK -def A6XX_VPC_DS_PACK_PSIZELOC(val): return (val << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK -def A6XX_VPC_DS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK -def A6XX_VPC_CNTL_0_NUMNONPOSVAR(val): return (val << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK -def A6XX_VPC_CNTL_0_PRIMIDLOC(val): return (val << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK -def A6XX_VPC_CNTL_0_VIEWIDLOC(val): return (val << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK -def A7XX_VPC_POLYGON_MODE2_MODE(val): return (val << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK -def A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK -def A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK -def A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK -def A6XX_PC_HS_INPUT_SIZE_SIZE(val): return (val << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK -def A6XX_PC_TESS_CNTL_SPACING(val): return (val << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK -def A6XX_PC_TESS_CNTL_OUTPUT(val): return (val << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK -def A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK -def A6XX_PC_DRAW_CMD_STATE_ID(val): return (val << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK -def A6XX_PC_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK -def A6XX_PC_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK -def A6XX_PC_EVENT_CMD_EVENT(val): return (val << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK -def A6XX_PC_POLYGON_MODE_MODE(val): return (val << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK -def A7XX_PC_POLYGON_MODE_MODE(val): return (val << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK -def A6XX_PC_RASTER_CNTL_STREAM(val): return (val << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK -def A7XX_PC_RASTER_CNTL_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK -def A7XX_PC_RASTER_CNTL_V2_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK -def A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_VS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_GS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_HS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_DS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK -def A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(val): return (val << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK -def A6XX_PC_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_PC_2D_EVENT_CMD_EVENT(val): return (val << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK -def A6XX_PC_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK -def A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK -def A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(val): return (val << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK -def A6XX_PC_DRAW_INITIATOR_VIS_CULL(val): return (val << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK -def A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(val): return (val << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK -def A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK -def A6XX_PC_VSTREAM_CONTROL_UNK0(val): return (val << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK -def A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK -def A6XX_PC_VSTREAM_CONTROL_VSC_N(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK -def A6XX_VFD_CONTROL_0_FETCH_CNT(val): return (val << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK -def A6XX_VFD_CONTROL_0_DECODE_CNT(val): return (val << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK -def A6XX_VFD_CONTROL_1_REGID4VTX(val): return (val << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK -def A6XX_VFD_CONTROL_1_REGID4INST(val): return (val << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK -def A6XX_VFD_CONTROL_1_REGID4PRIMID(val): return (val << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK -def A6XX_VFD_CONTROL_1_REGID4VIEWID(val): return (val << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK -def A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK -def A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(val): return (val << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK -def A6XX_VFD_CONTROL_3_REGID_DSPRIMID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK -def A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK -def A6XX_VFD_CONTROL_3_REGID_TESSX(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK -def A6XX_VFD_CONTROL_3_REGID_TESSY(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK -def A6XX_VFD_CONTROL_4_UNK0(val): return (val << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK -def A6XX_VFD_CONTROL_5_REGID_GSHEADER(val): return (val << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK -def A6XX_VFD_CONTROL_5_UNK8(val): return (val << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK -def A6XX_VFD_MODE_CNTL_RENDER_MODE(val): return (val << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK -def A6XX_VFD_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_VFD_DECODE_INSTR_IDX(val): return (val << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK -def A6XX_VFD_DECODE_INSTR_OFFSET(val): return (val << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK -def A6XX_VFD_DECODE_INSTR_FORMAT(val): return (val << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK -def A6XX_VFD_DECODE_INSTR_SWAP(val): return (val << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK -def A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK -def A6XX_VFD_DEST_CNTL_INSTR_REGID(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK -def A6XX_SP_VS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_VS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_VS_OUT_REG_A_REGID(val): return (val << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK -def A6XX_SP_VS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_VS_OUT_REG_B_REGID(val): return (val << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK -def A6XX_SP_VS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_VS_CONFIG_NTEX(val): return (val << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK -def A6XX_SP_VS_CONFIG_NSAMP(val): return (val << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK -def A6XX_SP_VS_CONFIG_NIBO(val): return (val << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK -def A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_HS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_HS_CONFIG_NTEX(val): return (val << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK -def A6XX_SP_HS_CONFIG_NSAMP(val): return (val << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK -def A6XX_SP_HS_CONFIG_NIBO(val): return (val << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK -def A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_DS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_DS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_DS_OUT_REG_A_REGID(val): return (val << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK -def A6XX_SP_DS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_DS_OUT_REG_B_REGID(val): return (val << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK -def A6XX_SP_DS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_DS_CONFIG_NTEX(val): return (val << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK -def A6XX_SP_DS_CONFIG_NSAMP(val): return (val << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK -def A6XX_SP_DS_CONFIG_NIBO(val): return (val << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK -def A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_GS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_GS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_GS_OUT_REG_A_REGID(val): return (val << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK -def A6XX_SP_GS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_GS_OUT_REG_B_REGID(val): return (val << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK -def A6XX_SP_GS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_GS_CONFIG_NTEX(val): return (val << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK -def A6XX_SP_GS_CONFIG_NSAMP(val): return (val << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK -def A6XX_SP_GS_CONFIG_NIBO(val): return (val << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK -def A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_FS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_FS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK -def A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT0(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT1(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT2(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT3(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT4(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT5(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT6(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT7(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK -def A6XX_SP_FS_OUTPUT_REG_REGID(val): return (val << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK -def A6XX_SP_FS_MRT_REG_COLOR_FORMAT(val): return (val << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK -def A6XX_SP_FS_PREFETCH_CNTL_COUNT(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK -def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK -def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK -def A6XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK -def A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK -def A6XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK -def A6XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK -def A6XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK -def A6XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK -def A7XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK -def A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK -def A7XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK -def A7XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK -def A7XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK -def A7XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK -def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK -def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK -def A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_CS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_CS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK -def A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(val): return (val << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK -def A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_CS_CONFIG_NTEX(val): return (val << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK -def A6XX_SP_CS_CONFIG_NSAMP(val): return (val << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK -def A6XX_SP_CS_CONFIG_NIBO(val): return (val << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK -def A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK -def A6XX_SP_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK -def A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK -def A6XX_SP_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK -def A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A6XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK -def A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A7XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK -def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT0(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT1(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT2(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT3(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT4(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT5(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT6(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT7(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK -def A6XX_SP_MODE_CONTROL_ISAMMODE(val): return (val << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK -def A6XX_SP_FS_CONFIG_NTEX(val): return (val << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK -def A6XX_SP_FS_CONFIG_NSAMP(val): return (val << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK -def A6XX_SP_FS_CONFIG_NIBO(val): return (val << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK -def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK -def A6XX_SP_2D_DST_FORMAT_MASK(val): return (val << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK -def A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK -def A7XX_SP_2D_DST_FORMAT_MASK(val): return (val << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK -def A7XX_SP_READ_SEL_LOCATION(val): return (val << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK -def A7XX_SP_READ_SEL_PIPE(val): return (val << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK -def A7XX_SP_READ_SEL_STATETYPE(val): return (val << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK -def A7XX_SP_READ_SEL_USPTP(val): return (val << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK -def A7XX_SP_READ_SEL_SPTP(val): return (val << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK -def A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK -def A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_SP_TP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK -def A6XX_SP_TP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK -def A6XX_SP_TP_MODE_CNTL_ISAMMODE(val): return (val << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK -def A6XX_SP_TP_MODE_CNTL_UNK3(val): return (val << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK -def A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK -def A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK -def A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK -def A6XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK -def A6XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK -def A6XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK -def A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK -def A6XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK -def A6XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK -def A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK -def A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK -def A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK -def A7XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK -def A7XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK -def A7XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK -def A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK -def A7XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK -def A7XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK -def A6XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK -def A7XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK -def A6XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK -def A7XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK -def A6XX_SP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK -def A6XX_SP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK -def A7XX_SP_PS_2D_WINDOW_OFFSET_X(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK -def A7XX_SP_PS_2D_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK -def A7XX_SP_WINDOW_OFFSET_X(val): return (val << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK -def A7XX_SP_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK -def A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK -def A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK -def A6XX_TPL1_NC_MODE_CNTL_UNK6(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK -def A6XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(val): return (val << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK -def A6XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK -def A6XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK -def A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK -def A6XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK -def A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK -def A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK -def A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK -def A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK -def A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK -def A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK -def A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK -def A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK -def A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK -def A6XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK -def A7XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK -def A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK -def A7XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK -def A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK -def A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK -def A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK -def A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK -def A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK -def A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK -def A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK -def A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK -def A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK -def A7XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK -def A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK -def A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK -def A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK -def A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK -def A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK -def A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK -def A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK -def A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A6XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK -def A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK -def A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK -def A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK -def A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK -def A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK -def A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK -def A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK -def A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A7XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK -def A7XX_HLSQ_CS_CNTL_1_YALIGN(val): return (val << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK -def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(val): return (val << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK -def A6XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK -def A6XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK -def A6XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK -def A6XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK -def A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK -def A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK -def A7XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK -def A7XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK -def A7XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK -def A7XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A7XX_HLSQ_EVENT_CMD_EVENT__MASK -def A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK -def A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK -def A6XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK -def A6XX_HLSQ_2D_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK -def A6XX_CP_EVENT_START_STATE_ID(val): return (val << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK -def A6XX_CP_EVENT_END_STATE_ID(val): return (val << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK -def A6XX_CP_2D_EVENT_START_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK -def A6XX_CP_2D_EVENT_END_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK -def A6XX_TEX_SAMP_0_XY_MAG(val): return (val << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK -def A6XX_TEX_SAMP_0_XY_MIN(val): return (val << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK -def A6XX_TEX_SAMP_0_WRAP_S(val): return (val << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK -def A6XX_TEX_SAMP_0_WRAP_T(val): return (val << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK -def A6XX_TEX_SAMP_0_WRAP_R(val): return (val << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK -def A6XX_TEX_SAMP_0_ANISO(val): return (val << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK -def A6XX_TEX_SAMP_0_LOD_BIAS(val): return (val << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK -def A6XX_TEX_SAMP_1_COMPARE_FUNC(val): return (val << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK -def A6XX_TEX_SAMP_1_MAX_LOD(val): return (val << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK -def A6XX_TEX_SAMP_1_MIN_LOD(val): return (val << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK -def A6XX_TEX_SAMP_2_REDUCTION_MODE(val): return (val << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK -def A6XX_TEX_SAMP_2_BCOLOR(val): return (val << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK -def A6XX_TEX_CONST_0_TILE_MODE(val): return (val << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK -def A6XX_TEX_CONST_0_SWIZ_X(val): return (val << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK -def A6XX_TEX_CONST_0_SWIZ_Y(val): return (val << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK -def A6XX_TEX_CONST_0_SWIZ_Z(val): return (val << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK -def A6XX_TEX_CONST_0_SWIZ_W(val): return (val << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK -def A6XX_TEX_CONST_0_MIPLVLS(val): return (val << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK -def A6XX_TEX_CONST_0_SAMPLES(val): return (val << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK -def A6XX_TEX_CONST_0_FMT(val): return (val << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK -def A6XX_TEX_CONST_0_SWAP(val): return (val << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK -def A6XX_TEX_CONST_1_WIDTH(val): return (val << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK -def A6XX_TEX_CONST_1_HEIGHT(val): return (val << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK -def A6XX_TEX_CONST_2_STRUCTSIZETEXELS(val): return (val << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK -def A6XX_TEX_CONST_2_STARTOFFSETTEXELS(val): return (val << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK -def A6XX_TEX_CONST_2_PITCHALIGN(val): return (val << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK -def A6XX_TEX_CONST_2_PITCH(val): return (val << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK -def A6XX_TEX_CONST_2_TYPE(val): return (val << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK -def A6XX_TEX_CONST_3_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK -def A6XX_TEX_CONST_3_MIN_LAYERSZ(val): return (val << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK -def A6XX_TEX_CONST_4_BASE_LO(val): return (val << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK -def A6XX_TEX_CONST_5_BASE_HI(val): return (val << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK -def A6XX_TEX_CONST_5_DEPTH(val): return (val << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK -def A6XX_TEX_CONST_6_MIN_LOD_CLAMP(val): return (val << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK -def A6XX_TEX_CONST_6_PLANE_PITCH(val): return (val << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK -def A6XX_TEX_CONST_7_FLAG_LO(val): return (val << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK -def A6XX_TEX_CONST_8_FLAG_HI(val): return (val << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK -def A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK -def A6XX_UBO_0_BASE_LO(val): return (val << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK -def A6XX_UBO_1_BASE_HI(val): return (val << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK -def A6XX_UBO_1_SIZE(val): return (val << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK diff --git a/tinygrad/tinygrad/runtime/autogen/am/am.py b/tinygrad/tinygrad/runtime/autogen/am/am.py deleted file mode 100644 index 0bbfe1b8..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/am.py +++ /dev/null @@ -1,5861 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', 'stdint.h'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -V11_STRUCTS_H_ = True # macro -uint32_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -uint64_t = True # macro -class struct_v11_gfx_mqd(Structure): - pass - -struct_v11_gfx_mqd._pack_ = 1 # source:False -struct_v11_gfx_mqd._fields_ = [ - ('shadow_base_lo', ctypes.c_uint32), - ('shadow_base_hi', ctypes.c_uint32), - ('gds_bkup_base_lo', ctypes.c_uint32), - ('gds_bkup_base_hi', ctypes.c_uint32), - ('fw_work_area_base_lo', ctypes.c_uint32), - ('fw_work_area_base_hi', ctypes.c_uint32), - ('shadow_initialized', ctypes.c_uint32), - ('ib_vmid', ctypes.c_uint32), - ('reserved_8', ctypes.c_uint32), - ('reserved_9', ctypes.c_uint32), - ('reserved_10', ctypes.c_uint32), - ('reserved_11', ctypes.c_uint32), - ('reserved_12', ctypes.c_uint32), - ('reserved_13', ctypes.c_uint32), - ('reserved_14', ctypes.c_uint32), - ('reserved_15', ctypes.c_uint32), - ('reserved_16', ctypes.c_uint32), - ('reserved_17', ctypes.c_uint32), - ('reserved_18', ctypes.c_uint32), - ('reserved_19', ctypes.c_uint32), - ('reserved_20', ctypes.c_uint32), - ('reserved_21', ctypes.c_uint32), - ('reserved_22', ctypes.c_uint32), - ('reserved_23', ctypes.c_uint32), - ('reserved_24', ctypes.c_uint32), - ('reserved_25', ctypes.c_uint32), - ('reserved_26', ctypes.c_uint32), - ('reserved_27', ctypes.c_uint32), - ('reserved_28', ctypes.c_uint32), - ('reserved_29', ctypes.c_uint32), - ('reserved_30', ctypes.c_uint32), - ('reserved_31', ctypes.c_uint32), - ('reserved_32', ctypes.c_uint32), - ('reserved_33', ctypes.c_uint32), - ('reserved_34', ctypes.c_uint32), - ('reserved_35', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('reserved_37', ctypes.c_uint32), - ('reserved_38', ctypes.c_uint32), - ('reserved_39', ctypes.c_uint32), - ('reserved_40', ctypes.c_uint32), - ('reserved_41', ctypes.c_uint32), - ('reserved_42', ctypes.c_uint32), - ('reserved_43', ctypes.c_uint32), - ('reserved_44', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('checksum_lo', ctypes.c_uint32), - ('checksum_hi', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('cp_mqd_query_wave_count', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_gfx_hqd_active', ctypes.c_uint32), - ('cp_gfx_hqd_vmid', ctypes.c_uint32), - ('reserved_131', ctypes.c_uint32), - ('reserved_132', ctypes.c_uint32), - ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), - ('cp_gfx_hqd_quantum', ctypes.c_uint32), - ('cp_gfx_hqd_base', ctypes.c_uint32), - ('cp_gfx_hqd_base_hi', ctypes.c_uint32), - ('cp_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_rb_doorbell_control', ctypes.c_uint32), - ('cp_gfx_hqd_offset', ctypes.c_uint32), - ('cp_gfx_hqd_cntl', ctypes.c_uint32), - ('reserved_146', ctypes.c_uint32), - ('reserved_147', ctypes.c_uint32), - ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), - ('reserved_151', ctypes.c_uint32), - ('reserved_152', ctypes.c_uint32), - ('reserved_153', ctypes.c_uint32), - ('reserved_154', ctypes.c_uint32), - ('reserved_155', ctypes.c_uint32), - ('cp_gfx_hqd_mapped', ctypes.c_uint32), - ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), - ('reserved_158', ctypes.c_uint32), - ('reserved_159', ctypes.c_uint32), - ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), - ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), - ('cp_gfx_mqd_control', ctypes.c_uint32), - ('reserved_163', ctypes.c_uint32), - ('reserved_164', ctypes.c_uint32), - ('reserved_165', ctypes.c_uint32), - ('reserved_166', ctypes.c_uint32), - ('reserved_167', ctypes.c_uint32), - ('reserved_168', ctypes.c_uint32), - ('reserved_169', ctypes.c_uint32), - ('cp_num_prim_needed_count0_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count0_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count1_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count1_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count2_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count2_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count3_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count3_hi', ctypes.c_uint32), - ('cp_num_prim_written_count0_lo', ctypes.c_uint32), - ('cp_num_prim_written_count0_hi', ctypes.c_uint32), - ('cp_num_prim_written_count1_lo', ctypes.c_uint32), - ('cp_num_prim_written_count1_hi', ctypes.c_uint32), - ('cp_num_prim_written_count2_lo', ctypes.c_uint32), - ('cp_num_prim_written_count2_hi', ctypes.c_uint32), - ('cp_num_prim_written_count3_lo', ctypes.c_uint32), - ('cp_num_prim_written_count3_hi', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('mp1_smn_fps_cnt', ctypes.c_uint32), - ('sq_thread_trace_buf0_base', ctypes.c_uint32), - ('sq_thread_trace_buf0_size', ctypes.c_uint32), - ('sq_thread_trace_buf1_base', ctypes.c_uint32), - ('sq_thread_trace_buf1_size', ctypes.c_uint32), - ('sq_thread_trace_wptr', ctypes.c_uint32), - ('sq_thread_trace_mask', ctypes.c_uint32), - ('sq_thread_trace_token_mask', ctypes.c_uint32), - ('sq_thread_trace_ctrl', ctypes.c_uint32), - ('sq_thread_trace_status', ctypes.c_uint32), - ('sq_thread_trace_dropped_cntr', ctypes.c_uint32), - ('sq_thread_trace_finish_done_debug', ctypes.c_uint32), - ('sq_thread_trace_gfx_draw_cntr', ctypes.c_uint32), - ('sq_thread_trace_gfx_marker_cntr', ctypes.c_uint32), - ('sq_thread_trace_hp3d_draw_cntr', ctypes.c_uint32), - ('sq_thread_trace_hp3d_marker_cntr', ctypes.c_uint32), - ('reserved_206', ctypes.c_uint32), - ('reserved_207', ctypes.c_uint32), - ('cp_sc_psinvoc_count0_lo', ctypes.c_uint32), - ('cp_sc_psinvoc_count0_hi', ctypes.c_uint32), - ('cp_pa_cprim_count_lo', ctypes.c_uint32), - ('cp_pa_cprim_count_hi', ctypes.c_uint32), - ('cp_pa_cinvoc_count_lo', ctypes.c_uint32), - ('cp_pa_cinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_vsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_vsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_gsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_gsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_gsprim_count_lo', ctypes.c_uint32), - ('cp_vgt_gsprim_count_hi', ctypes.c_uint32), - ('cp_vgt_iaprim_count_lo', ctypes.c_uint32), - ('cp_vgt_iaprim_count_hi', ctypes.c_uint32), - ('cp_vgt_iavert_count_lo', ctypes.c_uint32), - ('cp_vgt_iavert_count_hi', ctypes.c_uint32), - ('cp_vgt_hsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_hsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_dsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_dsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_csinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_230', ctypes.c_uint32), - ('reserved_231', ctypes.c_uint32), - ('reserved_232', ctypes.c_uint32), - ('reserved_233', ctypes.c_uint32), - ('reserved_234', ctypes.c_uint32), - ('reserved_235', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('reserved_240', ctypes.c_uint32), - ('reserved_241', ctypes.c_uint32), - ('reserved_242', ctypes.c_uint32), - ('reserved_243', ctypes.c_uint32), - ('reserved_244', ctypes.c_uint32), - ('reserved_245', ctypes.c_uint32), - ('reserved_246', ctypes.c_uint32), - ('reserved_247', ctypes.c_uint32), - ('reserved_248', ctypes.c_uint32), - ('reserved_249', ctypes.c_uint32), - ('reserved_250', ctypes.c_uint32), - ('reserved_251', ctypes.c_uint32), - ('reserved_252', ctypes.c_uint32), - ('reserved_253', ctypes.c_uint32), - ('reserved_254', ctypes.c_uint32), - ('reserved_255', ctypes.c_uint32), - ('reserved_256', ctypes.c_uint32), - ('reserved_257', ctypes.c_uint32), - ('reserved_258', ctypes.c_uint32), - ('reserved_259', ctypes.c_uint32), - ('reserved_260', ctypes.c_uint32), - ('reserved_261', ctypes.c_uint32), - ('reserved_262', ctypes.c_uint32), - ('reserved_263', ctypes.c_uint32), - ('reserved_264', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_0', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_1', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_2', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_3', ctypes.c_uint32), - ('reserved_272', ctypes.c_uint32), - ('reserved_273', ctypes.c_uint32), - ('reserved_274', ctypes.c_uint32), - ('reserved_275', ctypes.c_uint32), - ('vgt_dma_max_size', ctypes.c_uint32), - ('vgt_dma_num_instances', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('it_set_base_ib_addr_lo', ctypes.c_uint32), - ('it_set_base_ib_addr_hi', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', ctypes.c_uint32), - ('reserved_354', ctypes.c_uint32), - ('reserved_355', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_ps', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_vs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_gs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_hs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_ps', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_vs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_gs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_hs', ctypes.c_uint32), - ('db_occlusion_count0_low_00', ctypes.c_uint32), - ('db_occlusion_count0_hi_00', ctypes.c_uint32), - ('db_occlusion_count1_low_00', ctypes.c_uint32), - ('db_occlusion_count1_hi_00', ctypes.c_uint32), - ('db_occlusion_count2_low_00', ctypes.c_uint32), - ('db_occlusion_count2_hi_00', ctypes.c_uint32), - ('db_occlusion_count3_low_00', ctypes.c_uint32), - ('db_occlusion_count3_hi_00', ctypes.c_uint32), - ('db_occlusion_count0_low_01', ctypes.c_uint32), - ('db_occlusion_count0_hi_01', ctypes.c_uint32), - ('db_occlusion_count1_low_01', ctypes.c_uint32), - ('db_occlusion_count1_hi_01', ctypes.c_uint32), - ('db_occlusion_count2_low_01', ctypes.c_uint32), - ('db_occlusion_count2_hi_01', ctypes.c_uint32), - ('db_occlusion_count3_low_01', ctypes.c_uint32), - ('db_occlusion_count3_hi_01', ctypes.c_uint32), - ('db_occlusion_count0_low_02', ctypes.c_uint32), - ('db_occlusion_count0_hi_02', ctypes.c_uint32), - ('db_occlusion_count1_low_02', ctypes.c_uint32), - ('db_occlusion_count1_hi_02', ctypes.c_uint32), - ('db_occlusion_count2_low_02', ctypes.c_uint32), - ('db_occlusion_count2_hi_02', ctypes.c_uint32), - ('db_occlusion_count3_low_02', ctypes.c_uint32), - ('db_occlusion_count3_hi_02', ctypes.c_uint32), - ('db_occlusion_count0_low_03', ctypes.c_uint32), - ('db_occlusion_count0_hi_03', ctypes.c_uint32), - ('db_occlusion_count1_low_03', ctypes.c_uint32), - ('db_occlusion_count1_hi_03', ctypes.c_uint32), - ('db_occlusion_count2_low_03', ctypes.c_uint32), - ('db_occlusion_count2_hi_03', ctypes.c_uint32), - ('db_occlusion_count3_low_03', ctypes.c_uint32), - ('db_occlusion_count3_hi_03', ctypes.c_uint32), - ('db_occlusion_count0_low_04', ctypes.c_uint32), - ('db_occlusion_count0_hi_04', ctypes.c_uint32), - ('db_occlusion_count1_low_04', ctypes.c_uint32), - ('db_occlusion_count1_hi_04', ctypes.c_uint32), - ('db_occlusion_count2_low_04', ctypes.c_uint32), - ('db_occlusion_count2_hi_04', ctypes.c_uint32), - ('db_occlusion_count3_low_04', ctypes.c_uint32), - ('db_occlusion_count3_hi_04', ctypes.c_uint32), - ('db_occlusion_count0_low_05', ctypes.c_uint32), - ('db_occlusion_count0_hi_05', ctypes.c_uint32), - ('db_occlusion_count1_low_05', ctypes.c_uint32), - ('db_occlusion_count1_hi_05', ctypes.c_uint32), - ('db_occlusion_count2_low_05', ctypes.c_uint32), - ('db_occlusion_count2_hi_05', ctypes.c_uint32), - ('db_occlusion_count3_low_05', ctypes.c_uint32), - ('db_occlusion_count3_hi_05', ctypes.c_uint32), - ('db_occlusion_count0_low_06', ctypes.c_uint32), - ('db_occlusion_count0_hi_06', ctypes.c_uint32), - ('db_occlusion_count1_low_06', ctypes.c_uint32), - ('db_occlusion_count1_hi_06', ctypes.c_uint32), - ('db_occlusion_count2_low_06', ctypes.c_uint32), - ('db_occlusion_count2_hi_06', ctypes.c_uint32), - ('db_occlusion_count3_low_06', ctypes.c_uint32), - ('db_occlusion_count3_hi_06', ctypes.c_uint32), - ('db_occlusion_count0_low_07', ctypes.c_uint32), - ('db_occlusion_count0_hi_07', ctypes.c_uint32), - ('db_occlusion_count1_low_07', ctypes.c_uint32), - ('db_occlusion_count1_hi_07', ctypes.c_uint32), - ('db_occlusion_count2_low_07', ctypes.c_uint32), - ('db_occlusion_count2_hi_07', ctypes.c_uint32), - ('db_occlusion_count3_low_07', ctypes.c_uint32), - ('db_occlusion_count3_hi_07', ctypes.c_uint32), - ('db_occlusion_count0_low_10', ctypes.c_uint32), - ('db_occlusion_count0_hi_10', ctypes.c_uint32), - ('db_occlusion_count1_low_10', ctypes.c_uint32), - ('db_occlusion_count1_hi_10', ctypes.c_uint32), - ('db_occlusion_count2_low_10', ctypes.c_uint32), - ('db_occlusion_count2_hi_10', ctypes.c_uint32), - ('db_occlusion_count3_low_10', ctypes.c_uint32), - ('db_occlusion_count3_hi_10', ctypes.c_uint32), - ('db_occlusion_count0_low_11', ctypes.c_uint32), - ('db_occlusion_count0_hi_11', ctypes.c_uint32), - ('db_occlusion_count1_low_11', ctypes.c_uint32), - ('db_occlusion_count1_hi_11', ctypes.c_uint32), - ('db_occlusion_count2_low_11', ctypes.c_uint32), - ('db_occlusion_count2_hi_11', ctypes.c_uint32), - ('db_occlusion_count3_low_11', ctypes.c_uint32), - ('db_occlusion_count3_hi_11', ctypes.c_uint32), - ('db_occlusion_count0_low_12', ctypes.c_uint32), - ('db_occlusion_count0_hi_12', ctypes.c_uint32), - ('db_occlusion_count1_low_12', ctypes.c_uint32), - ('db_occlusion_count1_hi_12', ctypes.c_uint32), - ('db_occlusion_count2_low_12', ctypes.c_uint32), - ('db_occlusion_count2_hi_12', ctypes.c_uint32), - ('db_occlusion_count3_low_12', ctypes.c_uint32), - ('db_occlusion_count3_hi_12', ctypes.c_uint32), - ('db_occlusion_count0_low_13', ctypes.c_uint32), - ('db_occlusion_count0_hi_13', ctypes.c_uint32), - ('db_occlusion_count1_low_13', ctypes.c_uint32), - ('db_occlusion_count1_hi_13', ctypes.c_uint32), - ('db_occlusion_count2_low_13', ctypes.c_uint32), - ('db_occlusion_count2_hi_13', ctypes.c_uint32), - ('db_occlusion_count3_low_13', ctypes.c_uint32), - ('db_occlusion_count3_hi_13', ctypes.c_uint32), - ('db_occlusion_count0_low_14', ctypes.c_uint32), - ('db_occlusion_count0_hi_14', ctypes.c_uint32), - ('db_occlusion_count1_low_14', ctypes.c_uint32), - ('db_occlusion_count1_hi_14', ctypes.c_uint32), - ('db_occlusion_count2_low_14', ctypes.c_uint32), - ('db_occlusion_count2_hi_14', ctypes.c_uint32), - ('db_occlusion_count3_low_14', ctypes.c_uint32), - ('db_occlusion_count3_hi_14', ctypes.c_uint32), - ('db_occlusion_count0_low_15', ctypes.c_uint32), - ('db_occlusion_count0_hi_15', ctypes.c_uint32), - ('db_occlusion_count1_low_15', ctypes.c_uint32), - ('db_occlusion_count1_hi_15', ctypes.c_uint32), - ('db_occlusion_count2_low_15', ctypes.c_uint32), - ('db_occlusion_count2_hi_15', ctypes.c_uint32), - ('db_occlusion_count3_low_15', ctypes.c_uint32), - ('db_occlusion_count3_hi_15', ctypes.c_uint32), - ('db_occlusion_count0_low_16', ctypes.c_uint32), - ('db_occlusion_count0_hi_16', ctypes.c_uint32), - ('db_occlusion_count1_low_16', ctypes.c_uint32), - ('db_occlusion_count1_hi_16', ctypes.c_uint32), - ('db_occlusion_count2_low_16', ctypes.c_uint32), - ('db_occlusion_count2_hi_16', ctypes.c_uint32), - ('db_occlusion_count3_low_16', ctypes.c_uint32), - ('db_occlusion_count3_hi_16', ctypes.c_uint32), - ('db_occlusion_count0_low_17', ctypes.c_uint32), - ('db_occlusion_count0_hi_17', ctypes.c_uint32), - ('db_occlusion_count1_low_17', ctypes.c_uint32), - ('db_occlusion_count1_hi_17', ctypes.c_uint32), - ('db_occlusion_count2_low_17', ctypes.c_uint32), - ('db_occlusion_count2_hi_17', ctypes.c_uint32), - ('db_occlusion_count3_low_17', ctypes.c_uint32), - ('db_occlusion_count3_hi_17', ctypes.c_uint32), - ('reserved_492', ctypes.c_uint32), - ('reserved_493', ctypes.c_uint32), - ('reserved_494', ctypes.c_uint32), - ('reserved_495', ctypes.c_uint32), - ('reserved_496', ctypes.c_uint32), - ('reserved_497', ctypes.c_uint32), - ('reserved_498', ctypes.c_uint32), - ('reserved_499', ctypes.c_uint32), - ('reserved_500', ctypes.c_uint32), - ('reserved_501', ctypes.c_uint32), - ('reserved_502', ctypes.c_uint32), - ('reserved_503', ctypes.c_uint32), - ('reserved_504', ctypes.c_uint32), - ('reserved_505', ctypes.c_uint32), - ('reserved_506', ctypes.c_uint32), - ('reserved_507', ctypes.c_uint32), - ('reserved_508', ctypes.c_uint32), - ('reserved_509', ctypes.c_uint32), - ('reserved_510', ctypes.c_uint32), - ('reserved_511', ctypes.c_uint32), -] - -class struct_v11_sdma_mqd(Structure): - pass - -struct_v11_sdma_mqd._pack_ = 1 # source:False -struct_v11_sdma_mqd._fields_ = [ - ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), - ('sdmax_rlcx_rb_base', ctypes.c_uint32), - ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), - ('sdmax_rlcx_ib_offset', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_size', ctypes.c_uint32), - ('sdmax_rlcx_skip_cntl', ctypes.c_uint32), - ('sdmax_rlcx_context_status', ctypes.c_uint32), - ('sdmax_rlcx_doorbell', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), - ('sdmax_rlcx_preempt', ctypes.c_uint32), - ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), - ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), - ('sdmax_rlcx_rb_preempt', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), - ('sdmax_rlcx_f32_dbg0', ctypes.c_uint32), - ('sdmax_rlcx_f32_dbg1', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('reserved_86', ctypes.c_uint32), - ('reserved_87', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('reserved_92', ctypes.c_uint32), - ('reserved_93', ctypes.c_uint32), - ('reserved_94', ctypes.c_uint32), - ('reserved_95', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('reserved_104', ctypes.c_uint32), - ('reserved_105', ctypes.c_uint32), - ('reserved_106', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('sdma_engine_id', ctypes.c_uint32), - ('sdma_queue_id', ctypes.c_uint32), -] - -class struct_v11_compute_mqd(Structure): - pass - -struct_v11_compute_mqd._pack_ = 1 # source:False -struct_v11_compute_mqd._fields_ = [ - ('header', ctypes.c_uint32), - ('compute_dispatch_initiator', ctypes.c_uint32), - ('compute_dim_x', ctypes.c_uint32), - ('compute_dim_y', ctypes.c_uint32), - ('compute_dim_z', ctypes.c_uint32), - ('compute_start_x', ctypes.c_uint32), - ('compute_start_y', ctypes.c_uint32), - ('compute_start_z', ctypes.c_uint32), - ('compute_num_thread_x', ctypes.c_uint32), - ('compute_num_thread_y', ctypes.c_uint32), - ('compute_num_thread_z', ctypes.c_uint32), - ('compute_pipelinestat_enable', ctypes.c_uint32), - ('compute_perfcount_enable', ctypes.c_uint32), - ('compute_pgm_lo', ctypes.c_uint32), - ('compute_pgm_hi', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_lo', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_hi', ctypes.c_uint32), - ('compute_dispatch_scratch_base_lo', ctypes.c_uint32), - ('compute_dispatch_scratch_base_hi', ctypes.c_uint32), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('compute_vmid', ctypes.c_uint32), - ('compute_resource_limits', ctypes.c_uint32), - ('compute_static_thread_mgmt_se0', ctypes.c_uint32), - ('compute_static_thread_mgmt_se1', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('compute_static_thread_mgmt_se2', ctypes.c_uint32), - ('compute_static_thread_mgmt_se3', ctypes.c_uint32), - ('compute_restart_x', ctypes.c_uint32), - ('compute_restart_y', ctypes.c_uint32), - ('compute_restart_z', ctypes.c_uint32), - ('compute_thread_trace_enable', ctypes.c_uint32), - ('compute_misc_reserved', ctypes.c_uint32), - ('compute_dispatch_id', ctypes.c_uint32), - ('compute_threadgroup_id', ctypes.c_uint32), - ('compute_req_ctrl', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('compute_user_accum_0', ctypes.c_uint32), - ('compute_user_accum_1', ctypes.c_uint32), - ('compute_user_accum_2', ctypes.c_uint32), - ('compute_user_accum_3', ctypes.c_uint32), - ('compute_pgm_rsrc3', ctypes.c_uint32), - ('compute_ddid_index', ctypes.c_uint32), - ('compute_shader_chksum', ctypes.c_uint32), - ('compute_static_thread_mgmt_se4', ctypes.c_uint32), - ('compute_static_thread_mgmt_se5', ctypes.c_uint32), - ('compute_static_thread_mgmt_se6', ctypes.c_uint32), - ('compute_static_thread_mgmt_se7', ctypes.c_uint32), - ('compute_dispatch_interleave', ctypes.c_uint32), - ('compute_relaunch', ctypes.c_uint32), - ('compute_wave_restore_addr_lo', ctypes.c_uint32), - ('compute_wave_restore_addr_hi', ctypes.c_uint32), - ('compute_wave_restore_control', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('compute_user_data_0', ctypes.c_uint32), - ('compute_user_data_1', ctypes.c_uint32), - ('compute_user_data_2', ctypes.c_uint32), - ('compute_user_data_3', ctypes.c_uint32), - ('compute_user_data_4', ctypes.c_uint32), - ('compute_user_data_5', ctypes.c_uint32), - ('compute_user_data_6', ctypes.c_uint32), - ('compute_user_data_7', ctypes.c_uint32), - ('compute_user_data_8', ctypes.c_uint32), - ('compute_user_data_9', ctypes.c_uint32), - ('compute_user_data_10', ctypes.c_uint32), - ('compute_user_data_11', ctypes.c_uint32), - ('compute_user_data_12', ctypes.c_uint32), - ('compute_user_data_13', ctypes.c_uint32), - ('compute_user_data_14', ctypes.c_uint32), - ('compute_user_data_15', ctypes.c_uint32), - ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), - ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), - ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), - ('cp_mqd_readindex_lo', ctypes.c_uint32), - ('cp_mqd_readindex_hi', ctypes.c_uint32), - ('cp_mqd_save_start_time_lo', ctypes.c_uint32), - ('cp_mqd_save_start_time_hi', ctypes.c_uint32), - ('cp_mqd_save_end_time_lo', ctypes.c_uint32), - ('cp_mqd_save_end_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt0', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt1', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt2', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt3', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('cp_pq_exe_status_lo', ctypes.c_uint32), - ('cp_pq_exe_status_hi', ctypes.c_uint32), - ('cp_packet_id_lo', ctypes.c_uint32), - ('cp_packet_id_hi', ctypes.c_uint32), - ('cp_packet_exe_status_lo', ctypes.c_uint32), - ('cp_packet_exe_status_hi', ctypes.c_uint32), - ('gds_save_base_addr_lo', ctypes.c_uint32), - ('gds_save_base_addr_hi', ctypes.c_uint32), - ('gds_save_mask_lo', ctypes.c_uint32), - ('gds_save_mask_hi', ctypes.c_uint32), - ('ctx_save_base_addr_lo', ctypes.c_uint32), - ('ctx_save_base_addr_hi', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr_lo', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_active', ctypes.c_uint32), - ('cp_hqd_vmid', ctypes.c_uint32), - ('cp_hqd_persistent_state', ctypes.c_uint32), - ('cp_hqd_pipe_priority', ctypes.c_uint32), - ('cp_hqd_queue_priority', ctypes.c_uint32), - ('cp_hqd_quantum', ctypes.c_uint32), - ('cp_hqd_pq_base_lo', ctypes.c_uint32), - ('cp_hqd_pq_base_hi', ctypes.c_uint32), - ('cp_hqd_pq_rptr', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), - ('reserved_144', ctypes.c_uint32), - ('cp_hqd_pq_control', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ib_rptr', ctypes.c_uint32), - ('cp_hqd_ib_control', ctypes.c_uint32), - ('cp_hqd_iq_timer', ctypes.c_uint32), - ('cp_hqd_iq_rptr', ctypes.c_uint32), - ('cp_hqd_dequeue_request', ctypes.c_uint32), - ('cp_hqd_dma_offload', ctypes.c_uint32), - ('cp_hqd_sema_cmd', ctypes.c_uint32), - ('cp_hqd_msg_type', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), - ('cp_hqd_hq_status0', ctypes.c_uint32), - ('cp_hqd_hq_control0', ctypes.c_uint32), - ('cp_mqd_control', ctypes.c_uint32), - ('cp_hqd_hq_status1', ctypes.c_uint32), - ('cp_hqd_hq_control1', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_eop_control', ctypes.c_uint32), - ('cp_hqd_eop_rptr', ctypes.c_uint32), - ('cp_hqd_eop_wptr', ctypes.c_uint32), - ('cp_hqd_eop_done_events', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ctx_save_control', ctypes.c_uint32), - ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), - ('cp_hqd_cntl_stack_size', ctypes.c_uint32), - ('cp_hqd_wg_state_offset', ctypes.c_uint32), - ('cp_hqd_ctx_save_size', ctypes.c_uint32), - ('cp_hqd_gds_resource_state', ctypes.c_uint32), - ('cp_hqd_error', ctypes.c_uint32), - ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), - ('cp_hqd_aql_control', ctypes.c_uint32), - ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), - ('reserved_184', ctypes.c_uint32), - ('reserved_185', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('reserved_190', ctypes.c_uint32), - ('reserved_191', ctypes.c_uint32), - ('iqtimer_pkt_header', ctypes.c_uint32), - ('iqtimer_pkt_dw0', ctypes.c_uint32), - ('iqtimer_pkt_dw1', ctypes.c_uint32), - ('iqtimer_pkt_dw2', ctypes.c_uint32), - ('iqtimer_pkt_dw3', ctypes.c_uint32), - ('iqtimer_pkt_dw4', ctypes.c_uint32), - ('iqtimer_pkt_dw5', ctypes.c_uint32), - ('iqtimer_pkt_dw6', ctypes.c_uint32), - ('iqtimer_pkt_dw7', ctypes.c_uint32), - ('iqtimer_pkt_dw8', ctypes.c_uint32), - ('iqtimer_pkt_dw9', ctypes.c_uint32), - ('iqtimer_pkt_dw10', ctypes.c_uint32), - ('iqtimer_pkt_dw11', ctypes.c_uint32), - ('iqtimer_pkt_dw12', ctypes.c_uint32), - ('iqtimer_pkt_dw13', ctypes.c_uint32), - ('iqtimer_pkt_dw14', ctypes.c_uint32), - ('iqtimer_pkt_dw15', ctypes.c_uint32), - ('iqtimer_pkt_dw16', ctypes.c_uint32), - ('iqtimer_pkt_dw17', ctypes.c_uint32), - ('iqtimer_pkt_dw18', ctypes.c_uint32), - ('iqtimer_pkt_dw19', ctypes.c_uint32), - ('iqtimer_pkt_dw20', ctypes.c_uint32), - ('iqtimer_pkt_dw21', ctypes.c_uint32), - ('iqtimer_pkt_dw22', ctypes.c_uint32), - ('iqtimer_pkt_dw23', ctypes.c_uint32), - ('iqtimer_pkt_dw24', ctypes.c_uint32), - ('iqtimer_pkt_dw25', ctypes.c_uint32), - ('iqtimer_pkt_dw26', ctypes.c_uint32), - ('iqtimer_pkt_dw27', ctypes.c_uint32), - ('iqtimer_pkt_dw28', ctypes.c_uint32), - ('iqtimer_pkt_dw29', ctypes.c_uint32), - ('iqtimer_pkt_dw30', ctypes.c_uint32), - ('iqtimer_pkt_dw31', ctypes.c_uint32), - ('reserved_225', ctypes.c_uint32), - ('reserved_226', ctypes.c_uint32), - ('reserved_227', ctypes.c_uint32), - ('set_resources_header', ctypes.c_uint32), - ('set_resources_dw1', ctypes.c_uint32), - ('set_resources_dw2', ctypes.c_uint32), - ('set_resources_dw3', ctypes.c_uint32), - ('set_resources_dw4', ctypes.c_uint32), - ('set_resources_dw5', ctypes.c_uint32), - ('set_resources_dw6', ctypes.c_uint32), - ('set_resources_dw7', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('queue_doorbell_id0', ctypes.c_uint32), - ('queue_doorbell_id1', ctypes.c_uint32), - ('queue_doorbell_id2', ctypes.c_uint32), - ('queue_doorbell_id3', ctypes.c_uint32), - ('queue_doorbell_id4', ctypes.c_uint32), - ('queue_doorbell_id5', ctypes.c_uint32), - ('queue_doorbell_id6', ctypes.c_uint32), - ('queue_doorbell_id7', ctypes.c_uint32), - ('queue_doorbell_id8', ctypes.c_uint32), - ('queue_doorbell_id9', ctypes.c_uint32), - ('queue_doorbell_id10', ctypes.c_uint32), - ('queue_doorbell_id11', ctypes.c_uint32), - ('queue_doorbell_id12', ctypes.c_uint32), - ('queue_doorbell_id13', ctypes.c_uint32), - ('queue_doorbell_id14', ctypes.c_uint32), - ('queue_doorbell_id15', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('control_buf_wptr_lo', ctypes.c_uint32), - ('control_buf_wptr_hi', ctypes.c_uint32), - ('control_buf_dptr_lo', ctypes.c_uint32), - ('control_buf_dptr_hi', ctypes.c_uint32), - ('control_buf_num_entries', ctypes.c_uint32), - ('draw_ring_addr_lo', ctypes.c_uint32), - ('draw_ring_addr_hi', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('reserved_268', ctypes.c_uint32), - ('reserved_269', ctypes.c_uint32), - ('reserved_270', ctypes.c_uint32), - ('reserved_271', ctypes.c_uint32), - ('reserved_272', ctypes.c_uint32), - ('reserved_273', ctypes.c_uint32), - ('reserved_274', ctypes.c_uint32), - ('reserved_275', ctypes.c_uint32), - ('reserved_276', ctypes.c_uint32), - ('reserved_277', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('reserved_288', ctypes.c_uint32), - ('reserved_289', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', ctypes.c_uint32), - ('reserved_354', ctypes.c_uint32), - ('reserved_355', ctypes.c_uint32), - ('reserved_356', ctypes.c_uint32), - ('reserved_357', ctypes.c_uint32), - ('reserved_358', ctypes.c_uint32), - ('reserved_359', ctypes.c_uint32), - ('reserved_360', ctypes.c_uint32), - ('reserved_361', ctypes.c_uint32), - ('reserved_362', ctypes.c_uint32), - ('reserved_363', ctypes.c_uint32), - ('reserved_364', ctypes.c_uint32), - ('reserved_365', ctypes.c_uint32), - ('reserved_366', ctypes.c_uint32), - ('reserved_367', ctypes.c_uint32), - ('reserved_368', ctypes.c_uint32), - ('reserved_369', ctypes.c_uint32), - ('reserved_370', ctypes.c_uint32), - ('reserved_371', ctypes.c_uint32), - ('reserved_372', ctypes.c_uint32), - ('reserved_373', ctypes.c_uint32), - ('reserved_374', ctypes.c_uint32), - ('reserved_375', ctypes.c_uint32), - ('reserved_376', ctypes.c_uint32), - ('reserved_377', ctypes.c_uint32), - ('reserved_378', ctypes.c_uint32), - ('reserved_379', ctypes.c_uint32), - ('reserved_380', ctypes.c_uint32), - ('reserved_381', ctypes.c_uint32), - ('reserved_382', ctypes.c_uint32), - ('reserved_383', ctypes.c_uint32), - ('reserved_384', ctypes.c_uint32), - ('reserved_385', ctypes.c_uint32), - ('reserved_386', ctypes.c_uint32), - ('reserved_387', ctypes.c_uint32), - ('reserved_388', ctypes.c_uint32), - ('reserved_389', ctypes.c_uint32), - ('reserved_390', ctypes.c_uint32), - ('reserved_391', ctypes.c_uint32), - ('reserved_392', ctypes.c_uint32), - ('reserved_393', ctypes.c_uint32), - ('reserved_394', ctypes.c_uint32), - ('reserved_395', ctypes.c_uint32), - ('reserved_396', ctypes.c_uint32), - ('reserved_397', ctypes.c_uint32), - ('reserved_398', ctypes.c_uint32), - ('reserved_399', ctypes.c_uint32), - ('reserved_400', ctypes.c_uint32), - ('reserved_401', ctypes.c_uint32), - ('reserved_402', ctypes.c_uint32), - ('reserved_403', ctypes.c_uint32), - ('reserved_404', ctypes.c_uint32), - ('reserved_405', ctypes.c_uint32), - ('reserved_406', ctypes.c_uint32), - ('reserved_407', ctypes.c_uint32), - ('reserved_408', ctypes.c_uint32), - ('reserved_409', ctypes.c_uint32), - ('reserved_410', ctypes.c_uint32), - ('reserved_411', ctypes.c_uint32), - ('reserved_412', ctypes.c_uint32), - ('reserved_413', ctypes.c_uint32), - ('reserved_414', ctypes.c_uint32), - ('reserved_415', ctypes.c_uint32), - ('reserved_416', ctypes.c_uint32), - ('reserved_417', ctypes.c_uint32), - ('reserved_418', ctypes.c_uint32), - ('reserved_419', ctypes.c_uint32), - ('reserved_420', ctypes.c_uint32), - ('reserved_421', ctypes.c_uint32), - ('reserved_422', ctypes.c_uint32), - ('reserved_423', ctypes.c_uint32), - ('reserved_424', ctypes.c_uint32), - ('reserved_425', ctypes.c_uint32), - ('reserved_426', ctypes.c_uint32), - ('reserved_427', ctypes.c_uint32), - ('reserved_428', ctypes.c_uint32), - ('reserved_429', ctypes.c_uint32), - ('reserved_430', ctypes.c_uint32), - ('reserved_431', ctypes.c_uint32), - ('reserved_432', ctypes.c_uint32), - ('reserved_433', ctypes.c_uint32), - ('reserved_434', ctypes.c_uint32), - ('reserved_435', ctypes.c_uint32), - ('reserved_436', ctypes.c_uint32), - ('reserved_437', ctypes.c_uint32), - ('reserved_438', ctypes.c_uint32), - ('reserved_439', ctypes.c_uint32), - ('reserved_440', ctypes.c_uint32), - ('reserved_441', ctypes.c_uint32), - ('reserved_442', ctypes.c_uint32), - ('reserved_443', ctypes.c_uint32), - ('reserved_444', ctypes.c_uint32), - ('reserved_445', ctypes.c_uint32), - ('reserved_446', ctypes.c_uint32), - ('reserved_447', ctypes.c_uint32), - ('gws_0_val', ctypes.c_uint32), - ('gws_1_val', ctypes.c_uint32), - ('gws_2_val', ctypes.c_uint32), - ('gws_3_val', ctypes.c_uint32), - ('gws_4_val', ctypes.c_uint32), - ('gws_5_val', ctypes.c_uint32), - ('gws_6_val', ctypes.c_uint32), - ('gws_7_val', ctypes.c_uint32), - ('gws_8_val', ctypes.c_uint32), - ('gws_9_val', ctypes.c_uint32), - ('gws_10_val', ctypes.c_uint32), - ('gws_11_val', ctypes.c_uint32), - ('gws_12_val', ctypes.c_uint32), - ('gws_13_val', ctypes.c_uint32), - ('gws_14_val', ctypes.c_uint32), - ('gws_15_val', ctypes.c_uint32), - ('gws_16_val', ctypes.c_uint32), - ('gws_17_val', ctypes.c_uint32), - ('gws_18_val', ctypes.c_uint32), - ('gws_19_val', ctypes.c_uint32), - ('gws_20_val', ctypes.c_uint32), - ('gws_21_val', ctypes.c_uint32), - ('gws_22_val', ctypes.c_uint32), - ('gws_23_val', ctypes.c_uint32), - ('gws_24_val', ctypes.c_uint32), - ('gws_25_val', ctypes.c_uint32), - ('gws_26_val', ctypes.c_uint32), - ('gws_27_val', ctypes.c_uint32), - ('gws_28_val', ctypes.c_uint32), - ('gws_29_val', ctypes.c_uint32), - ('gws_30_val', ctypes.c_uint32), - ('gws_31_val', ctypes.c_uint32), - ('gws_32_val', ctypes.c_uint32), - ('gws_33_val', ctypes.c_uint32), - ('gws_34_val', ctypes.c_uint32), - ('gws_35_val', ctypes.c_uint32), - ('gws_36_val', ctypes.c_uint32), - ('gws_37_val', ctypes.c_uint32), - ('gws_38_val', ctypes.c_uint32), - ('gws_39_val', ctypes.c_uint32), - ('gws_40_val', ctypes.c_uint32), - ('gws_41_val', ctypes.c_uint32), - ('gws_42_val', ctypes.c_uint32), - ('gws_43_val', ctypes.c_uint32), - ('gws_44_val', ctypes.c_uint32), - ('gws_45_val', ctypes.c_uint32), - ('gws_46_val', ctypes.c_uint32), - ('gws_47_val', ctypes.c_uint32), - ('gws_48_val', ctypes.c_uint32), - ('gws_49_val', ctypes.c_uint32), - ('gws_50_val', ctypes.c_uint32), - ('gws_51_val', ctypes.c_uint32), - ('gws_52_val', ctypes.c_uint32), - ('gws_53_val', ctypes.c_uint32), - ('gws_54_val', ctypes.c_uint32), - ('gws_55_val', ctypes.c_uint32), - ('gws_56_val', ctypes.c_uint32), - ('gws_57_val', ctypes.c_uint32), - ('gws_58_val', ctypes.c_uint32), - ('gws_59_val', ctypes.c_uint32), - ('gws_60_val', ctypes.c_uint32), - ('gws_61_val', ctypes.c_uint32), - ('gws_62_val', ctypes.c_uint32), - ('gws_63_val', ctypes.c_uint32), -] - -V12_STRUCTS_H_ = True # macro -class struct_v12_gfx_mqd(Structure): - pass - -struct_v12_gfx_mqd._pack_ = 1 # source:False -struct_v12_gfx_mqd._fields_ = [ - ('shadow_base_lo', ctypes.c_uint32), - ('shadow_base_hi', ctypes.c_uint32), - ('reserved_2', ctypes.c_uint32), - ('reserved_3', ctypes.c_uint32), - ('fw_work_area_base_lo', ctypes.c_uint32), - ('fw_work_area_base_hi', ctypes.c_uint32), - ('shadow_initialized', ctypes.c_uint32), - ('ib_vmid', ctypes.c_uint32), - ('reserved_8', ctypes.c_uint32), - ('reserved_9', ctypes.c_uint32), - ('reserved_10', ctypes.c_uint32), - ('reserved_11', ctypes.c_uint32), - ('reserved_12', ctypes.c_uint32), - ('reserved_13', ctypes.c_uint32), - ('reserved_14', ctypes.c_uint32), - ('reserved_15', ctypes.c_uint32), - ('reserved_16', ctypes.c_uint32), - ('reserved_17', ctypes.c_uint32), - ('reserved_18', ctypes.c_uint32), - ('reserved_19', ctypes.c_uint32), - ('reserved_20', ctypes.c_uint32), - ('reserved_21', ctypes.c_uint32), - ('reserved_22', ctypes.c_uint32), - ('reserved_23', ctypes.c_uint32), - ('reserved_24', ctypes.c_uint32), - ('reserved_25', ctypes.c_uint32), - ('reserved_26', ctypes.c_uint32), - ('reserved_27', ctypes.c_uint32), - ('reserved_28', ctypes.c_uint32), - ('reserved_29', ctypes.c_uint32), - ('reserved_30', ctypes.c_uint32), - ('reserved_31', ctypes.c_uint32), - ('reserved_32', ctypes.c_uint32), - ('reserved_33', ctypes.c_uint32), - ('reserved_34', ctypes.c_uint32), - ('reserved_35', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('reserved_37', ctypes.c_uint32), - ('reserved_38', ctypes.c_uint32), - ('reserved_39', ctypes.c_uint32), - ('reserved_40', ctypes.c_uint32), - ('reserved_41', ctypes.c_uint32), - ('reserved_42', ctypes.c_uint32), - ('reserved_43', ctypes.c_uint32), - ('reserved_44', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('checksum_lo', ctypes.c_uint32), - ('checksum_hi', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('cp_mqd_query_wave_count', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('task_shader_control_buf_addr_lo', ctypes.c_uint32), - ('task_shader_control_buf_addr_hi', ctypes.c_uint32), - ('task_shader_read_rptr_lo', ctypes.c_uint32), - ('task_shader_read_rptr_hi', ctypes.c_uint32), - ('task_shader_num_entries', ctypes.c_uint32), - ('task_shader_num_entries_bits', ctypes.c_uint32), - ('task_shader_ring_buffer_addr_lo', ctypes.c_uint32), - ('task_shader_ring_buffer_addr_hi', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_gfx_hqd_active', ctypes.c_uint32), - ('cp_gfx_hqd_vmid', ctypes.c_uint32), - ('reserved_132', ctypes.c_uint32), - ('reserved_133', ctypes.c_uint32), - ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), - ('cp_gfx_hqd_quantum', ctypes.c_uint32), - ('cp_gfx_hqd_base', ctypes.c_uint32), - ('cp_gfx_hqd_base_hi', ctypes.c_uint32), - ('cp_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_rb_doorbell_control', ctypes.c_uint32), - ('cp_gfx_hqd_offset', ctypes.c_uint32), - ('cp_gfx_hqd_cntl', ctypes.c_uint32), - ('reserved_146', ctypes.c_uint32), - ('reserved_147', ctypes.c_uint32), - ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), - ('reserved_151', ctypes.c_uint32), - ('reserved_152', ctypes.c_uint32), - ('reserved_153', ctypes.c_uint32), - ('reserved_154', ctypes.c_uint32), - ('reserved_155', ctypes.c_uint32), - ('cp_gfx_hqd_mapped', ctypes.c_uint32), - ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), - ('reserved_158', ctypes.c_uint32), - ('reserved_159', ctypes.c_uint32), - ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), - ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), - ('cp_gfx_mqd_control', ctypes.c_uint32), - ('reserved_163', ctypes.c_uint32), - ('reserved_164', ctypes.c_uint32), - ('reserved_165', ctypes.c_uint32), - ('reserved_166', ctypes.c_uint32), - ('reserved_167', ctypes.c_uint32), - ('reserved_168', ctypes.c_uint32), - ('reserved_169', ctypes.c_uint32), - ('reserved_170', ctypes.c_uint32), - ('reserved_171', ctypes.c_uint32), - ('reserved_172', ctypes.c_uint32), - ('reserved_173', ctypes.c_uint32), - ('reserved_174', ctypes.c_uint32), - ('reserved_175', ctypes.c_uint32), - ('reserved_176', ctypes.c_uint32), - ('reserved_177', ctypes.c_uint32), - ('reserved_178', ctypes.c_uint32), - ('reserved_179', ctypes.c_uint32), - ('reserved_180', ctypes.c_uint32), - ('reserved_181', ctypes.c_uint32), - ('reserved_182', ctypes.c_uint32), - ('reserved_183', ctypes.c_uint32), - ('reserved_184', ctypes.c_uint32), - ('reserved_185', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('reserved_190', ctypes.c_uint32), - ('reserved_191', ctypes.c_uint32), - ('reserved_192', ctypes.c_uint32), - ('reserved_193', ctypes.c_uint32), - ('reserved_194', ctypes.c_uint32), - ('reserved_195', ctypes.c_uint32), - ('reserved_196', ctypes.c_uint32), - ('reserved_197', ctypes.c_uint32), - ('reserved_198', ctypes.c_uint32), - ('reserved_199', ctypes.c_uint32), - ('reserved_200', ctypes.c_uint32), - ('reserved_201', ctypes.c_uint32), - ('reserved_202', ctypes.c_uint32), - ('reserved_203', ctypes.c_uint32), - ('reserved_204', ctypes.c_uint32), - ('reserved_205', ctypes.c_uint32), - ('reserved_206', ctypes.c_uint32), - ('reserved_207', ctypes.c_uint32), - ('reserved_208', ctypes.c_uint32), - ('reserved_209', ctypes.c_uint32), - ('reserved_210', ctypes.c_uint32), - ('reserved_211', ctypes.c_uint32), - ('reserved_212', ctypes.c_uint32), - ('reserved_213', ctypes.c_uint32), - ('reserved_214', ctypes.c_uint32), - ('reserved_215', ctypes.c_uint32), - ('reserved_216', ctypes.c_uint32), - ('reserved_217', ctypes.c_uint32), - ('reserved_218', ctypes.c_uint32), - ('reserved_219', ctypes.c_uint32), - ('reserved_220', ctypes.c_uint32), - ('reserved_221', ctypes.c_uint32), - ('reserved_222', ctypes.c_uint32), - ('reserved_223', ctypes.c_uint32), - ('reserved_224', ctypes.c_uint32), - ('reserved_225', ctypes.c_uint32), - ('reserved_226', ctypes.c_uint32), - ('reserved_227', ctypes.c_uint32), - ('reserved_228', ctypes.c_uint32), - ('reserved_229', ctypes.c_uint32), - ('reserved_230', ctypes.c_uint32), - ('reserved_231', ctypes.c_uint32), - ('reserved_232', ctypes.c_uint32), - ('reserved_233', ctypes.c_uint32), - ('reserved_234', ctypes.c_uint32), - ('reserved_235', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('reserved_240', ctypes.c_uint32), - ('reserved_241', ctypes.c_uint32), - ('reserved_242', ctypes.c_uint32), - ('reserved_243', ctypes.c_uint32), - ('reserved_244', ctypes.c_uint32), - ('reserved_245', ctypes.c_uint32), - ('reserved_246', ctypes.c_uint32), - ('reserved_247', ctypes.c_uint32), - ('reserved_248', ctypes.c_uint32), - ('reserved_249', ctypes.c_uint32), - ('reserved_250', ctypes.c_uint32), - ('reserved_251', ctypes.c_uint32), - ('reserved_252', ctypes.c_uint32), - ('reserved_253', ctypes.c_uint32), - ('reserved_254', ctypes.c_uint32), - ('reserved_255', ctypes.c_uint32), - ('reserved_256', ctypes.c_uint32), - ('reserved_257', ctypes.c_uint32), - ('reserved_258', ctypes.c_uint32), - ('reserved_259', ctypes.c_uint32), - ('reserved_260', ctypes.c_uint32), - ('reserved_261', ctypes.c_uint32), - ('reserved_262', ctypes.c_uint32), - ('reserved_263', ctypes.c_uint32), - ('reserved_264', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('reserved_268', ctypes.c_uint32), - ('reserved_269', ctypes.c_uint32), - ('reserved_270', ctypes.c_uint32), - ('reserved_271', ctypes.c_uint32), - ('dfwx_flags', ctypes.c_uint32), - ('dfwx_slot', ctypes.c_uint32), - ('dfwx_client_data_addr_lo', ctypes.c_uint32), - ('dfwx_client_data_addr_hi', ctypes.c_uint32), - ('reserved_276', ctypes.c_uint32), - ('reserved_277', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('reserved_288', ctypes.c_uint32), - ('reserved_289', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', ctypes.c_uint32), - ('reserved_354', ctypes.c_uint32), - ('reserved_355', ctypes.c_uint32), - ('reserved_356', ctypes.c_uint32), - ('reserved_357', ctypes.c_uint32), - ('reserved_358', ctypes.c_uint32), - ('reserved_359', ctypes.c_uint32), - ('reserved_360', ctypes.c_uint32), - ('reserved_361', ctypes.c_uint32), - ('reserved_362', ctypes.c_uint32), - ('reserved_363', ctypes.c_uint32), - ('reserved_364', ctypes.c_uint32), - ('reserved_365', ctypes.c_uint32), - ('reserved_366', ctypes.c_uint32), - ('reserved_367', ctypes.c_uint32), - ('reserved_368', ctypes.c_uint32), - ('reserved_369', ctypes.c_uint32), - ('reserved_370', ctypes.c_uint32), - ('reserved_371', ctypes.c_uint32), - ('reserved_372', ctypes.c_uint32), - ('reserved_373', ctypes.c_uint32), - ('reserved_374', ctypes.c_uint32), - ('reserved_375', ctypes.c_uint32), - ('reserved_376', ctypes.c_uint32), - ('reserved_377', ctypes.c_uint32), - ('reserved_378', ctypes.c_uint32), - ('reserved_379', ctypes.c_uint32), - ('reserved_380', ctypes.c_uint32), - ('reserved_381', ctypes.c_uint32), - ('reserved_382', ctypes.c_uint32), - ('reserved_383', ctypes.c_uint32), - ('reserved_384', ctypes.c_uint32), - ('reserved_385', ctypes.c_uint32), - ('reserved_386', ctypes.c_uint32), - ('reserved_387', ctypes.c_uint32), - ('reserved_388', ctypes.c_uint32), - ('reserved_389', ctypes.c_uint32), - ('reserved_390', ctypes.c_uint32), - ('reserved_391', ctypes.c_uint32), - ('reserved_392', ctypes.c_uint32), - ('reserved_393', ctypes.c_uint32), - ('reserved_394', ctypes.c_uint32), - ('reserved_395', ctypes.c_uint32), - ('reserved_396', ctypes.c_uint32), - ('reserved_397', ctypes.c_uint32), - ('reserved_398', ctypes.c_uint32), - ('reserved_399', ctypes.c_uint32), - ('reserved_400', ctypes.c_uint32), - ('reserved_401', ctypes.c_uint32), - ('reserved_402', ctypes.c_uint32), - ('reserved_403', ctypes.c_uint32), - ('reserved_404', ctypes.c_uint32), - ('reserved_405', ctypes.c_uint32), - ('reserved_406', ctypes.c_uint32), - ('reserved_407', ctypes.c_uint32), - ('reserved_408', ctypes.c_uint32), - ('reserved_409', ctypes.c_uint32), - ('reserved_410', ctypes.c_uint32), - ('reserved_411', ctypes.c_uint32), - ('reserved_412', ctypes.c_uint32), - ('reserved_413', ctypes.c_uint32), - ('reserved_414', ctypes.c_uint32), - ('reserved_415', ctypes.c_uint32), - ('reserved_416', ctypes.c_uint32), - ('reserved_417', ctypes.c_uint32), - ('reserved_418', ctypes.c_uint32), - ('reserved_419', ctypes.c_uint32), - ('reserved_420', ctypes.c_uint32), - ('reserved_421', ctypes.c_uint32), - ('reserved_422', ctypes.c_uint32), - ('reserved_423', ctypes.c_uint32), - ('reserved_424', ctypes.c_uint32), - ('reserved_425', ctypes.c_uint32), - ('reserved_426', ctypes.c_uint32), - ('reserved_427', ctypes.c_uint32), - ('reserved_428', ctypes.c_uint32), - ('reserved_429', ctypes.c_uint32), - ('reserved_430', ctypes.c_uint32), - ('reserved_431', ctypes.c_uint32), - ('reserved_432', ctypes.c_uint32), - ('reserved_433', ctypes.c_uint32), - ('reserved_434', ctypes.c_uint32), - ('reserved_435', ctypes.c_uint32), - ('reserved_436', ctypes.c_uint32), - ('reserved_437', ctypes.c_uint32), - ('reserved_438', ctypes.c_uint32), - ('reserved_439', ctypes.c_uint32), - ('reserved_440', ctypes.c_uint32), - ('reserved_441', ctypes.c_uint32), - ('reserved_442', ctypes.c_uint32), - ('reserved_443', ctypes.c_uint32), - ('reserved_444', ctypes.c_uint32), - ('reserved_445', ctypes.c_uint32), - ('reserved_446', ctypes.c_uint32), - ('reserved_447', ctypes.c_uint32), - ('reserved_448', ctypes.c_uint32), - ('reserved_449', ctypes.c_uint32), - ('reserved_450', ctypes.c_uint32), - ('reserved_451', ctypes.c_uint32), - ('reserved_452', ctypes.c_uint32), - ('reserved_453', ctypes.c_uint32), - ('reserved_454', ctypes.c_uint32), - ('reserved_455', ctypes.c_uint32), - ('reserved_456', ctypes.c_uint32), - ('reserved_457', ctypes.c_uint32), - ('reserved_458', ctypes.c_uint32), - ('reserved_459', ctypes.c_uint32), - ('reserved_460', ctypes.c_uint32), - ('reserved_461', ctypes.c_uint32), - ('reserved_462', ctypes.c_uint32), - ('reserved_463', ctypes.c_uint32), - ('reserved_464', ctypes.c_uint32), - ('reserved_465', ctypes.c_uint32), - ('reserved_466', ctypes.c_uint32), - ('reserved_467', ctypes.c_uint32), - ('reserved_468', ctypes.c_uint32), - ('reserved_469', ctypes.c_uint32), - ('reserved_470', ctypes.c_uint32), - ('reserved_471', ctypes.c_uint32), - ('reserved_472', ctypes.c_uint32), - ('reserved_473', ctypes.c_uint32), - ('reserved_474', ctypes.c_uint32), - ('reserved_475', ctypes.c_uint32), - ('reserved_476', ctypes.c_uint32), - ('reserved_477', ctypes.c_uint32), - ('reserved_478', ctypes.c_uint32), - ('reserved_479', ctypes.c_uint32), - ('reserved_480', ctypes.c_uint32), - ('reserved_481', ctypes.c_uint32), - ('reserved_482', ctypes.c_uint32), - ('reserved_483', ctypes.c_uint32), - ('reserved_484', ctypes.c_uint32), - ('reserved_485', ctypes.c_uint32), - ('reserved_486', ctypes.c_uint32), - ('reserved_487', ctypes.c_uint32), - ('reserved_488', ctypes.c_uint32), - ('reserved_489', ctypes.c_uint32), - ('reserved_490', ctypes.c_uint32), - ('reserved_491', ctypes.c_uint32), - ('reserved_492', ctypes.c_uint32), - ('reserved_493', ctypes.c_uint32), - ('reserved_494', ctypes.c_uint32), - ('reserved_495', ctypes.c_uint32), - ('reserved_496', ctypes.c_uint32), - ('reserved_497', ctypes.c_uint32), - ('reserved_498', ctypes.c_uint32), - ('reserved_499', ctypes.c_uint32), - ('reserved_500', ctypes.c_uint32), - ('reserved_501', ctypes.c_uint32), - ('reserved_502', ctypes.c_uint32), - ('reserved_503', ctypes.c_uint32), - ('reserved_504', ctypes.c_uint32), - ('reserved_505', ctypes.c_uint32), - ('reserved_506', ctypes.c_uint32), - ('reserved_507', ctypes.c_uint32), - ('reserved_508', ctypes.c_uint32), - ('reserved_509', ctypes.c_uint32), - ('reserved_510', ctypes.c_uint32), - ('reserved_511', ctypes.c_uint32), -] - -class struct_v12_sdma_mqd(Structure): - pass - -struct_v12_sdma_mqd._pack_ = 1 # source:False -struct_v12_sdma_mqd._fields_ = [ - ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), - ('sdmax_rlcx_rb_base', ctypes.c_uint32), - ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), - ('sdmax_rlcx_ib_offset', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_size', ctypes.c_uint32), - ('sdmax_rlcx_doorbell', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), - ('sdmax_rlcx_preempt', ctypes.c_uint32), - ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), - ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), - ('sdmax_rlcx_mcu_dbg0', ctypes.c_uint32), - ('sdmax_rlcx_mcu_dbg1', ctypes.c_uint32), - ('sdmax_rlcx_context_switch_status', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), - ('sdmax_rlcx_wait_unsatisfied_thd', ctypes.c_uint32), - ('sdmax_rlcx_mqd_base_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_mqd_base_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_mqd_control', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('reserved_86', ctypes.c_uint32), - ('reserved_87', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('reserved_92', ctypes.c_uint32), - ('reserved_93', ctypes.c_uint32), - ('reserved_94', ctypes.c_uint32), - ('reserved_95', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('reserved_104', ctypes.c_uint32), - ('reserved_105', ctypes.c_uint32), - ('reserved_106', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('sdma_engine_id', ctypes.c_uint32), - ('sdma_queue_id', ctypes.c_uint32), -] - -class struct_v12_compute_mqd(Structure): - pass - -struct_v12_compute_mqd._pack_ = 1 # source:False -struct_v12_compute_mqd._fields_ = [ - ('header', ctypes.c_uint32), - ('compute_dispatch_initiator', ctypes.c_uint32), - ('compute_dim_x', ctypes.c_uint32), - ('compute_dim_y', ctypes.c_uint32), - ('compute_dim_z', ctypes.c_uint32), - ('compute_start_x', ctypes.c_uint32), - ('compute_start_y', ctypes.c_uint32), - ('compute_start_z', ctypes.c_uint32), - ('compute_num_thread_x', ctypes.c_uint32), - ('compute_num_thread_y', ctypes.c_uint32), - ('compute_num_thread_z', ctypes.c_uint32), - ('compute_pipelinestat_enable', ctypes.c_uint32), - ('compute_perfcount_enable', ctypes.c_uint32), - ('compute_pgm_lo', ctypes.c_uint32), - ('compute_pgm_hi', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_lo', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_hi', ctypes.c_uint32), - ('compute_dispatch_scratch_base_lo', ctypes.c_uint32), - ('compute_dispatch_scratch_base_hi', ctypes.c_uint32), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('compute_vmid', ctypes.c_uint32), - ('compute_resource_limits', ctypes.c_uint32), - ('compute_static_thread_mgmt_se0', ctypes.c_uint32), - ('compute_static_thread_mgmt_se1', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('compute_static_thread_mgmt_se2', ctypes.c_uint32), - ('compute_static_thread_mgmt_se3', ctypes.c_uint32), - ('compute_restart_x', ctypes.c_uint32), - ('compute_restart_y', ctypes.c_uint32), - ('compute_restart_z', ctypes.c_uint32), - ('compute_thread_trace_enable', ctypes.c_uint32), - ('compute_misc_reserved', ctypes.c_uint32), - ('compute_dispatch_id', ctypes.c_uint32), - ('compute_threadgroup_id', ctypes.c_uint32), - ('compute_req_ctrl', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('compute_user_accum_0', ctypes.c_uint32), - ('compute_user_accum_1', ctypes.c_uint32), - ('compute_user_accum_2', ctypes.c_uint32), - ('compute_user_accum_3', ctypes.c_uint32), - ('compute_pgm_rsrc3', ctypes.c_uint32), - ('compute_ddid_index', ctypes.c_uint32), - ('compute_shader_chksum', ctypes.c_uint32), - ('compute_static_thread_mgmt_se4', ctypes.c_uint32), - ('compute_static_thread_mgmt_se5', ctypes.c_uint32), - ('compute_static_thread_mgmt_se6', ctypes.c_uint32), - ('compute_static_thread_mgmt_se7', ctypes.c_uint32), - ('compute_dispatch_interleave', ctypes.c_uint32), - ('compute_relaunch', ctypes.c_uint32), - ('compute_wave_restore_addr_lo', ctypes.c_uint32), - ('compute_wave_restore_addr_hi', ctypes.c_uint32), - ('compute_wave_restore_control', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('compute_static_thread_mgmt_se8', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('compute_user_data_0', ctypes.c_uint32), - ('compute_user_data_1', ctypes.c_uint32), - ('compute_user_data_2', ctypes.c_uint32), - ('compute_user_data_3', ctypes.c_uint32), - ('compute_user_data_4', ctypes.c_uint32), - ('compute_user_data_5', ctypes.c_uint32), - ('compute_user_data_6', ctypes.c_uint32), - ('compute_user_data_7', ctypes.c_uint32), - ('compute_user_data_8', ctypes.c_uint32), - ('compute_user_data_9', ctypes.c_uint32), - ('compute_user_data_10', ctypes.c_uint32), - ('compute_user_data_11', ctypes.c_uint32), - ('compute_user_data_12', ctypes.c_uint32), - ('compute_user_data_13', ctypes.c_uint32), - ('compute_user_data_14', ctypes.c_uint32), - ('compute_user_data_15', ctypes.c_uint32), - ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), - ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), - ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), - ('cp_mqd_readindex_lo', ctypes.c_uint32), - ('cp_mqd_readindex_hi', ctypes.c_uint32), - ('cp_mqd_save_start_time_lo', ctypes.c_uint32), - ('cp_mqd_save_start_time_hi', ctypes.c_uint32), - ('cp_mqd_save_end_time_lo', ctypes.c_uint32), - ('cp_mqd_save_end_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('cp_pq_exe_status_lo', ctypes.c_uint32), - ('cp_pq_exe_status_hi', ctypes.c_uint32), - ('cp_packet_id_lo', ctypes.c_uint32), - ('cp_packet_id_hi', ctypes.c_uint32), - ('cp_packet_exe_status_lo', ctypes.c_uint32), - ('cp_packet_exe_status_hi', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('ctx_save_base_addr_lo', ctypes.c_uint32), - ('ctx_save_base_addr_hi', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr_lo', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_active', ctypes.c_uint32), - ('cp_hqd_vmid', ctypes.c_uint32), - ('cp_hqd_persistent_state', ctypes.c_uint32), - ('cp_hqd_pipe_priority', ctypes.c_uint32), - ('cp_hqd_queue_priority', ctypes.c_uint32), - ('cp_hqd_quantum', ctypes.c_uint32), - ('cp_hqd_pq_base_lo', ctypes.c_uint32), - ('cp_hqd_pq_base_hi', ctypes.c_uint32), - ('cp_hqd_pq_rptr', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), - ('reserved_144', ctypes.c_uint32), - ('cp_hqd_pq_control', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ib_rptr', ctypes.c_uint32), - ('cp_hqd_ib_control', ctypes.c_uint32), - ('cp_hqd_iq_timer', ctypes.c_uint32), - ('cp_hqd_iq_rptr', ctypes.c_uint32), - ('cp_hqd_dequeue_request', ctypes.c_uint32), - ('cp_hqd_dma_offload', ctypes.c_uint32), - ('cp_hqd_sema_cmd', ctypes.c_uint32), - ('cp_hqd_msg_type', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), - ('cp_hqd_hq_status0', ctypes.c_uint32), - ('cp_hqd_hq_control0', ctypes.c_uint32), - ('cp_mqd_control', ctypes.c_uint32), - ('cp_hqd_hq_status1', ctypes.c_uint32), - ('cp_hqd_hq_control1', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_eop_control', ctypes.c_uint32), - ('cp_hqd_eop_rptr', ctypes.c_uint32), - ('cp_hqd_eop_wptr', ctypes.c_uint32), - ('cp_hqd_eop_done_events', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ctx_save_control', ctypes.c_uint32), - ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), - ('cp_hqd_cntl_stack_size', ctypes.c_uint32), - ('cp_hqd_wg_state_offset', ctypes.c_uint32), - ('cp_hqd_ctx_save_size', ctypes.c_uint32), - ('reserved_178', ctypes.c_uint32), - ('cp_hqd_error', ctypes.c_uint32), - ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), - ('cp_hqd_aql_control', ctypes.c_uint32), - ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), - ('reserved_184', ctypes.c_uint32), - ('reserved_185', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('reserved_190', ctypes.c_uint32), - ('reserved_191', ctypes.c_uint32), - ('iqtimer_pkt_header', ctypes.c_uint32), - ('iqtimer_pkt_dw0', ctypes.c_uint32), - ('iqtimer_pkt_dw1', ctypes.c_uint32), - ('iqtimer_pkt_dw2', ctypes.c_uint32), - ('iqtimer_pkt_dw3', ctypes.c_uint32), - ('iqtimer_pkt_dw4', ctypes.c_uint32), - ('iqtimer_pkt_dw5', ctypes.c_uint32), - ('iqtimer_pkt_dw6', ctypes.c_uint32), - ('iqtimer_pkt_dw7', ctypes.c_uint32), - ('iqtimer_pkt_dw8', ctypes.c_uint32), - ('iqtimer_pkt_dw9', ctypes.c_uint32), - ('iqtimer_pkt_dw10', ctypes.c_uint32), - ('iqtimer_pkt_dw11', ctypes.c_uint32), - ('iqtimer_pkt_dw12', ctypes.c_uint32), - ('iqtimer_pkt_dw13', ctypes.c_uint32), - ('iqtimer_pkt_dw14', ctypes.c_uint32), - ('iqtimer_pkt_dw15', ctypes.c_uint32), - ('iqtimer_pkt_dw16', ctypes.c_uint32), - ('iqtimer_pkt_dw17', ctypes.c_uint32), - ('iqtimer_pkt_dw18', ctypes.c_uint32), - ('iqtimer_pkt_dw19', ctypes.c_uint32), - ('iqtimer_pkt_dw20', ctypes.c_uint32), - ('iqtimer_pkt_dw21', ctypes.c_uint32), - ('iqtimer_pkt_dw22', ctypes.c_uint32), - ('iqtimer_pkt_dw23', ctypes.c_uint32), - ('iqtimer_pkt_dw24', ctypes.c_uint32), - ('iqtimer_pkt_dw25', ctypes.c_uint32), - ('iqtimer_pkt_dw26', ctypes.c_uint32), - ('iqtimer_pkt_dw27', ctypes.c_uint32), - ('iqtimer_pkt_dw28', ctypes.c_uint32), - ('iqtimer_pkt_dw29', ctypes.c_uint32), - ('iqtimer_pkt_dw30', ctypes.c_uint32), - ('iqtimer_pkt_dw31', ctypes.c_uint32), - ('reserved_225', ctypes.c_uint32), - ('reserved_226', ctypes.c_uint32), - ('reserved_227', ctypes.c_uint32), - ('set_resources_header', ctypes.c_uint32), - ('set_resources_dw1', ctypes.c_uint32), - ('set_resources_dw2', ctypes.c_uint32), - ('set_resources_dw3', ctypes.c_uint32), - ('set_resources_dw4', ctypes.c_uint32), - ('set_resources_dw5', ctypes.c_uint32), - ('set_resources_dw6', ctypes.c_uint32), - ('set_resources_dw7', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('queue_doorbell_id0', ctypes.c_uint32), - ('queue_doorbell_id1', ctypes.c_uint32), - ('queue_doorbell_id2', ctypes.c_uint32), - ('queue_doorbell_id3', ctypes.c_uint32), - ('queue_doorbell_id4', ctypes.c_uint32), - ('queue_doorbell_id5', ctypes.c_uint32), - ('queue_doorbell_id6', ctypes.c_uint32), - ('queue_doorbell_id7', ctypes.c_uint32), - ('queue_doorbell_id8', ctypes.c_uint32), - ('queue_doorbell_id9', ctypes.c_uint32), - ('queue_doorbell_id10', ctypes.c_uint32), - ('queue_doorbell_id11', ctypes.c_uint32), - ('queue_doorbell_id12', ctypes.c_uint32), - ('queue_doorbell_id13', ctypes.c_uint32), - ('queue_doorbell_id14', ctypes.c_uint32), - ('queue_doorbell_id15', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('control_buf_wptr_lo', ctypes.c_uint32), - ('control_buf_wptr_hi', ctypes.c_uint32), - ('control_buf_dptr_lo', ctypes.c_uint32), - ('control_buf_dptr_hi', ctypes.c_uint32), - ('control_buf_num_entries', ctypes.c_uint32), - ('draw_ring_addr_lo', ctypes.c_uint32), - ('draw_ring_addr_hi', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('reserved_268', ctypes.c_uint32), - ('reserved_269', ctypes.c_uint32), - ('reserved_270', ctypes.c_uint32), - ('reserved_271', ctypes.c_uint32), - ('dfwx_flags', ctypes.c_uint32), - ('dfwx_slot', ctypes.c_uint32), - ('dfwx_client_data_addr_lo', ctypes.c_uint32), - ('dfwx_client_data_addr_hi', ctypes.c_uint32), - ('reserved_276', ctypes.c_uint32), - ('reserved_277', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('reserved_288', ctypes.c_uint32), - ('reserved_289', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', ctypes.c_uint32), - ('reserved_354', ctypes.c_uint32), - ('reserved_355', ctypes.c_uint32), - ('reserved_356', ctypes.c_uint32), - ('reserved_357', ctypes.c_uint32), - ('reserved_358', ctypes.c_uint32), - ('reserved_359', ctypes.c_uint32), - ('reserved_360', ctypes.c_uint32), - ('reserved_361', ctypes.c_uint32), - ('reserved_362', ctypes.c_uint32), - ('reserved_363', ctypes.c_uint32), - ('reserved_364', ctypes.c_uint32), - ('reserved_365', ctypes.c_uint32), - ('reserved_366', ctypes.c_uint32), - ('reserved_367', ctypes.c_uint32), - ('reserved_368', ctypes.c_uint32), - ('reserved_369', ctypes.c_uint32), - ('reserved_370', ctypes.c_uint32), - ('reserved_371', ctypes.c_uint32), - ('reserved_372', ctypes.c_uint32), - ('reserved_373', ctypes.c_uint32), - ('reserved_374', ctypes.c_uint32), - ('reserved_375', ctypes.c_uint32), - ('reserved_376', ctypes.c_uint32), - ('reserved_377', ctypes.c_uint32), - ('reserved_378', ctypes.c_uint32), - ('reserved_379', ctypes.c_uint32), - ('reserved_380', ctypes.c_uint32), - ('reserved_381', ctypes.c_uint32), - ('reserved_382', ctypes.c_uint32), - ('reserved_383', ctypes.c_uint32), - ('reserved_384', ctypes.c_uint32), - ('reserved_385', ctypes.c_uint32), - ('reserved_386', ctypes.c_uint32), - ('reserved_387', ctypes.c_uint32), - ('reserved_388', ctypes.c_uint32), - ('reserved_389', ctypes.c_uint32), - ('reserved_390', ctypes.c_uint32), - ('reserved_391', ctypes.c_uint32), - ('reserved_392', ctypes.c_uint32), - ('reserved_393', ctypes.c_uint32), - ('reserved_394', ctypes.c_uint32), - ('reserved_395', ctypes.c_uint32), - ('reserved_396', ctypes.c_uint32), - ('reserved_397', ctypes.c_uint32), - ('reserved_398', ctypes.c_uint32), - ('reserved_399', ctypes.c_uint32), - ('reserved_400', ctypes.c_uint32), - ('reserved_401', ctypes.c_uint32), - ('reserved_402', ctypes.c_uint32), - ('reserved_403', ctypes.c_uint32), - ('reserved_404', ctypes.c_uint32), - ('reserved_405', ctypes.c_uint32), - ('reserved_406', ctypes.c_uint32), - ('reserved_407', ctypes.c_uint32), - ('reserved_408', ctypes.c_uint32), - ('reserved_409', ctypes.c_uint32), - ('reserved_410', ctypes.c_uint32), - ('reserved_411', ctypes.c_uint32), - ('reserved_412', ctypes.c_uint32), - ('reserved_413', ctypes.c_uint32), - ('reserved_414', ctypes.c_uint32), - ('reserved_415', ctypes.c_uint32), - ('reserved_416', ctypes.c_uint32), - ('reserved_417', ctypes.c_uint32), - ('reserved_418', ctypes.c_uint32), - ('reserved_419', ctypes.c_uint32), - ('reserved_420', ctypes.c_uint32), - ('reserved_421', ctypes.c_uint32), - ('reserved_422', ctypes.c_uint32), - ('reserved_423', ctypes.c_uint32), - ('reserved_424', ctypes.c_uint32), - ('reserved_425', ctypes.c_uint32), - ('reserved_426', ctypes.c_uint32), - ('reserved_427', ctypes.c_uint32), - ('reserved_428', ctypes.c_uint32), - ('reserved_429', ctypes.c_uint32), - ('reserved_430', ctypes.c_uint32), - ('reserved_431', ctypes.c_uint32), - ('reserved_432', ctypes.c_uint32), - ('reserved_433', ctypes.c_uint32), - ('reserved_434', ctypes.c_uint32), - ('reserved_435', ctypes.c_uint32), - ('reserved_436', ctypes.c_uint32), - ('reserved_437', ctypes.c_uint32), - ('reserved_438', ctypes.c_uint32), - ('reserved_439', ctypes.c_uint32), - ('reserved_440', ctypes.c_uint32), - ('reserved_441', ctypes.c_uint32), - ('reserved_442', ctypes.c_uint32), - ('reserved_443', ctypes.c_uint32), - ('reserved_444', ctypes.c_uint32), - ('reserved_445', ctypes.c_uint32), - ('reserved_446', ctypes.c_uint32), - ('reserved_447', ctypes.c_uint32), - ('gws_0_val', ctypes.c_uint32), - ('gws_1_val', ctypes.c_uint32), - ('gws_2_val', ctypes.c_uint32), - ('gws_3_val', ctypes.c_uint32), - ('gws_4_val', ctypes.c_uint32), - ('gws_5_val', ctypes.c_uint32), - ('gws_6_val', ctypes.c_uint32), - ('gws_7_val', ctypes.c_uint32), - ('gws_8_val', ctypes.c_uint32), - ('gws_9_val', ctypes.c_uint32), - ('gws_10_val', ctypes.c_uint32), - ('gws_11_val', ctypes.c_uint32), - ('gws_12_val', ctypes.c_uint32), - ('gws_13_val', ctypes.c_uint32), - ('gws_14_val', ctypes.c_uint32), - ('gws_15_val', ctypes.c_uint32), - ('gws_16_val', ctypes.c_uint32), - ('gws_17_val', ctypes.c_uint32), - ('gws_18_val', ctypes.c_uint32), - ('gws_19_val', ctypes.c_uint32), - ('gws_20_val', ctypes.c_uint32), - ('gws_21_val', ctypes.c_uint32), - ('gws_22_val', ctypes.c_uint32), - ('gws_23_val', ctypes.c_uint32), - ('gws_24_val', ctypes.c_uint32), - ('gws_25_val', ctypes.c_uint32), - ('gws_26_val', ctypes.c_uint32), - ('gws_27_val', ctypes.c_uint32), - ('gws_28_val', ctypes.c_uint32), - ('gws_29_val', ctypes.c_uint32), - ('gws_30_val', ctypes.c_uint32), - ('gws_31_val', ctypes.c_uint32), - ('gws_32_val', ctypes.c_uint32), - ('gws_33_val', ctypes.c_uint32), - ('gws_34_val', ctypes.c_uint32), - ('gws_35_val', ctypes.c_uint32), - ('gws_36_val', ctypes.c_uint32), - ('gws_37_val', ctypes.c_uint32), - ('gws_38_val', ctypes.c_uint32), - ('gws_39_val', ctypes.c_uint32), - ('gws_40_val', ctypes.c_uint32), - ('gws_41_val', ctypes.c_uint32), - ('gws_42_val', ctypes.c_uint32), - ('gws_43_val', ctypes.c_uint32), - ('gws_44_val', ctypes.c_uint32), - ('gws_45_val', ctypes.c_uint32), - ('gws_46_val', ctypes.c_uint32), - ('gws_47_val', ctypes.c_uint32), - ('gws_48_val', ctypes.c_uint32), - ('gws_49_val', ctypes.c_uint32), - ('gws_50_val', ctypes.c_uint32), - ('gws_51_val', ctypes.c_uint32), - ('gws_52_val', ctypes.c_uint32), - ('gws_53_val', ctypes.c_uint32), - ('gws_54_val', ctypes.c_uint32), - ('gws_55_val', ctypes.c_uint32), - ('gws_56_val', ctypes.c_uint32), - ('gws_57_val', ctypes.c_uint32), - ('gws_58_val', ctypes.c_uint32), - ('gws_59_val', ctypes.c_uint32), - ('gws_60_val', ctypes.c_uint32), - ('gws_61_val', ctypes.c_uint32), - ('gws_62_val', ctypes.c_uint32), - ('gws_63_val', ctypes.c_uint32), -] - -__AMDGPU_VM_H__ = True # macro -AMDGPU_VM_MAX_UPDATE_SIZE = 0x3FFFF # macro -# def AMDGPU_VM_PTE_COUNT(adev): # macro -# return (1<<(adev)->vm_manager.block_size) -AMDGPU_PTE_VALID = (1<<0) # macro -AMDGPU_PTE_SYSTEM = (1<<1) # macro -AMDGPU_PTE_SNOOPED = (1<<2) # macro -AMDGPU_PTE_TMZ = (1<<3) # macro -AMDGPU_PTE_EXECUTABLE = (1<<4) # macro -AMDGPU_PTE_READABLE = (1<<5) # macro -AMDGPU_PTE_WRITEABLE = (1<<6) # macro -def AMDGPU_PTE_FRAG(x): # macro - return ((x&0x1f)<<7) -AMDGPU_PTE_PRT = (1<<51) # macro -AMDGPU_PDE_PTE = (1<<54) # macro -AMDGPU_PTE_LOG = (1<<55) # macro -AMDGPU_PTE_TF = (1<<56) # macro -AMDGPU_PTE_NOALLOC = (1<<58) # macro -def AMDGPU_PDE_BFS(a): # macro - return ( a<<59) -AMDGPU_VM_NORETRY_FLAGS = ((1<<4)|(1<<54)|(1<<56)) # macro -AMDGPU_VM_NORETRY_FLAGS_TF = ((1<<0)|(1<<1)|(1<<51)) # macro -def AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype): # macro - return ( (mtype)<<57) -AMDGPU_PTE_MTYPE_VG10_MASK = AMDGPU_PTE_MTYPE_VG10_SHIFT ( 3 ) # macro -def AMDGPU_PTE_MTYPE_VG10(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_VG10_SHIFT(3)))|AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) -AMDGPU_MTYPE_NC = 0 # macro -AMDGPU_MTYPE_CC = 2 # macro -AMDGPU_PTE_DEFAULT_ATC = ((1<<1)|(1<<2)|(1<<4)|(1<<5)|(1<<6)|AMDGPU_PTE_MTYPE_VG10(0, 2)) # macro -def AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype): # macro - return ( (mtype)<<48) -AMDGPU_PTE_MTYPE_NV10_MASK = AMDGPU_PTE_MTYPE_NV10_SHIFT ( 7 ) # macro -def AMDGPU_PTE_MTYPE_NV10(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_NV10_SHIFT(7)))|AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) -AMDGPU_PTE_PRT_GFX12 = (1<<56) # macro -def AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype): # macro - return ( (mtype)<<54) -AMDGPU_PTE_MTYPE_GFX12_MASK = AMDGPU_PTE_MTYPE_GFX12_SHIFT ( 3 ) # macro -def AMDGPU_PTE_MTYPE_GFX12(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_GFX12_SHIFT(3)))|AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) -AMDGPU_PTE_IS_PTE = (1<<63) # macro -def AMDGPU_PDE_BFS_GFX12(a): # macro - return ( ((a)&0x1f)<<58) -AMDGPU_PDE_PTE_GFX12 = (1<<63) # macro -AMDGPU_VM_FAULT_STOP_NEVER = 0 # macro -AMDGPU_VM_FAULT_STOP_FIRST = 1 # macro -AMDGPU_VM_FAULT_STOP_ALWAYS = 2 # macro -AMDGPU_VM_RESERVED_VRAM = (8<<20) # macro -AMDGPU_MAX_VMHUBS = 13 # macro -AMDGPU_GFXHUB_START = 0 # macro -AMDGPU_MMHUB0_START = 8 # macro -AMDGPU_MMHUB1_START = 12 # macro -def AMDGPU_GFXHUB(x): # macro - return (0+(x)) -def AMDGPU_MMHUB0(x): # macro - return (8+(x)) -def AMDGPU_MMHUB1(x): # macro - return (12+(x)) -def AMDGPU_IS_GFXHUB(x): # macro - return ((x)>=0 and (x)<8) -def AMDGPU_IS_MMHUB0(x): # macro - return ((x)>=8 and (x)<12) -def AMDGPU_IS_MMHUB1(x): # macro - return ((x)>=12 and (x)<13) -AMDGPU_VA_RESERVED_CSA_SIZE = (2<<20) # macro -# def AMDGPU_VA_RESERVED_CSA_START(adev): # macro -# return (((adev)->vm_manager.max_pfn<=IP_VERSION(12,0,0))?(1<<56):(1<<51)) -# def AMDGPU_PDE_BFS_FLAG(adev, a): # macro -# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?AMDGPU_PDE_BFS_GFX12(a):AMDGPU_PDE_BFS(a)) -# def AMDGPU_PDE_PTE_FLAG(adev): # macro -# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?(1<<63):(1<<54)) -hw_id_map = [['GC_HWIP', '11'],['HDP_HWIP', '41'],['SDMA0_HWIP', '42'],['SDMA1_HWIP', '43'],['SDMA2_HWIP', '68'],['SDMA3_HWIP', '69'],['LSDMA_HWIP', '91'],['MMHUB_HWIP', '34'],['ATHUB_HWIP', '35'],['NBIO_HWIP', '108'],['MP0_HWIP', '255'],['MP1_HWIP', '1'],['UVD_HWIP', '12'],['VCE_HWIP', '32'],['DF_HWIP', '46'],['DCE_HWIP', '271'],['OSSSYS_HWIP', '40'],['SMUIO_HWIP', '4'],['PWR_HWIP', '10'],['NBIF_HWIP', '108'],['THM_HWIP', '3'],['CLK_HWIP', '6'],['UMC_HWIP', '150'],['XGMI_HWIP', '200'],['DCI_HWIP', '15'],['PCIE_HWIP', '70'],['VPE_HWIP', '21'],['ISP_HWIP', '44']] # Variable ctypes.c_int32 * 35 -__AMDGPU_UCODE_H__ = True # macro -int32_t = True # macro -int8_t = True # macro -int16_t = True # macro -bool = True # macro -u32 = True # macro -AMDGPU_SDMA0_UCODE_LOADED = 0x00000001 # macro -AMDGPU_SDMA1_UCODE_LOADED = 0x00000002 # macro -AMDGPU_CPCE_UCODE_LOADED = 0x00000004 # macro -AMDGPU_CPPFP_UCODE_LOADED = 0x00000008 # macro -AMDGPU_CPME_UCODE_LOADED = 0x00000010 # macro -AMDGPU_CPMEC1_UCODE_LOADED = 0x00000020 # macro -AMDGPU_CPMEC2_UCODE_LOADED = 0x00000040 # macro -AMDGPU_CPRLC_UCODE_LOADED = 0x00000100 # macro -class struct_common_firmware_header(Structure): - pass - -struct_common_firmware_header._pack_ = 1 # source:False -struct_common_firmware_header._fields_ = [ - ('size_bytes', ctypes.c_uint32), - ('header_size_bytes', ctypes.c_uint32), - ('header_version_major', ctypes.c_uint16), - ('header_version_minor', ctypes.c_uint16), - ('ip_version_major', ctypes.c_uint16), - ('ip_version_minor', ctypes.c_uint16), - ('ucode_version', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), - ('ucode_array_offset_bytes', ctypes.c_uint32), - ('crc32', ctypes.c_uint32), -] - -class struct_mc_firmware_header_v1_0(Structure): - pass - -struct_mc_firmware_header_v1_0._pack_ = 1 # source:False -struct_mc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('io_debug_size_bytes', ctypes.c_uint32), - ('io_debug_array_offset_bytes', ctypes.c_uint32), -] - -class struct_smc_firmware_header_v1_0(Structure): - pass - -struct_smc_firmware_header_v1_0._pack_ = 1 # source:False -struct_smc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_start_addr', ctypes.c_uint32), -] - -class struct_smc_firmware_header_v2_0(Structure): - pass - -struct_smc_firmware_header_v2_0._pack_ = 1 # source:False -struct_smc_firmware_header_v2_0._fields_ = [ - ('v1_0', struct_smc_firmware_header_v1_0), - ('ppt_offset_bytes', ctypes.c_uint32), - ('ppt_size_bytes', ctypes.c_uint32), -] - -class struct_smc_soft_pptable_entry(Structure): - pass - -struct_smc_soft_pptable_entry._pack_ = 1 # source:False -struct_smc_soft_pptable_entry._fields_ = [ - ('id', ctypes.c_uint32), - ('ppt_offset_bytes', ctypes.c_uint32), - ('ppt_size_bytes', ctypes.c_uint32), -] - -class struct_smc_firmware_header_v2_1(Structure): - pass - -struct_smc_firmware_header_v2_1._pack_ = 1 # source:False -struct_smc_firmware_header_v2_1._fields_ = [ - ('v1_0', struct_smc_firmware_header_v1_0), - ('pptable_count', ctypes.c_uint32), - ('pptable_entry_offset', ctypes.c_uint32), -] - -class struct_psp_fw_legacy_bin_desc(Structure): - pass - -struct_psp_fw_legacy_bin_desc._pack_ = 1 # source:False -struct_psp_fw_legacy_bin_desc._fields_ = [ - ('fw_version', ctypes.c_uint32), - ('offset_bytes', ctypes.c_uint32), - ('size_bytes', ctypes.c_uint32), -] - -class struct_psp_firmware_header_v1_0(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_common_firmware_header), - ('sos', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_1(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_0', struct_psp_firmware_header_v1_0), - ('toc', struct_psp_fw_legacy_bin_desc), - ('kdb', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_2(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_0', struct_psp_firmware_header_v1_0), - ('res', struct_psp_fw_legacy_bin_desc), - ('kdb', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_3(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_1', struct_psp_firmware_header_v1_1), - ('spl', struct_psp_fw_legacy_bin_desc), - ('rl', struct_psp_fw_legacy_bin_desc), - ('sys_drv_aux', struct_psp_fw_legacy_bin_desc), - ('sos_aux', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_fw_bin_desc(Structure): - pass - -struct_psp_fw_bin_desc._pack_ = 1 # source:False -struct_psp_fw_bin_desc._fields_ = [ - ('fw_type', ctypes.c_uint32), - ('fw_version', ctypes.c_uint32), - ('offset_bytes', ctypes.c_uint32), - ('size_bytes', ctypes.c_uint32), -] - -# UCODE_MAX_PSP_PACKAGING = (((ctypes.sizeof(amdgpu_firmware_header)-ctypes.sizeof(struct_common_firmware_header)-4)/ctypes.sizeof(struct_psp_fw_bin_desc))*2) # macro - -# values for enumeration 'psp_fw_type' -psp_fw_type__enumvalues = { - 0: 'PSP_FW_TYPE_UNKOWN', - 1: 'PSP_FW_TYPE_PSP_SOS', - 2: 'PSP_FW_TYPE_PSP_SYS_DRV', - 3: 'PSP_FW_TYPE_PSP_KDB', - 4: 'PSP_FW_TYPE_PSP_TOC', - 5: 'PSP_FW_TYPE_PSP_SPL', - 6: 'PSP_FW_TYPE_PSP_RL', - 7: 'PSP_FW_TYPE_PSP_SOC_DRV', - 8: 'PSP_FW_TYPE_PSP_INTF_DRV', - 9: 'PSP_FW_TYPE_PSP_DBG_DRV', - 10: 'PSP_FW_TYPE_PSP_RAS_DRV', - 11: 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', - 12: 'PSP_FW_TYPE_MAX_INDEX', -} -PSP_FW_TYPE_UNKOWN = 0 -PSP_FW_TYPE_PSP_SOS = 1 -PSP_FW_TYPE_PSP_SYS_DRV = 2 -PSP_FW_TYPE_PSP_KDB = 3 -PSP_FW_TYPE_PSP_TOC = 4 -PSP_FW_TYPE_PSP_SPL = 5 -PSP_FW_TYPE_PSP_RL = 6 -PSP_FW_TYPE_PSP_SOC_DRV = 7 -PSP_FW_TYPE_PSP_INTF_DRV = 8 -PSP_FW_TYPE_PSP_DBG_DRV = 9 -PSP_FW_TYPE_PSP_RAS_DRV = 10 -PSP_FW_TYPE_PSP_IPKEYMGR_DRV = 11 -PSP_FW_TYPE_MAX_INDEX = 12 -psp_fw_type = ctypes.c_uint32 # enum -class struct_psp_firmware_header_v2_0(Structure): - pass - -struct_psp_firmware_header_v2_0._pack_ = 1 # source:False -struct_psp_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('psp_fw_bin_count', ctypes.c_uint32), - ('psp_fw_bin', struct_psp_fw_bin_desc * 1), -] - -class struct_psp_firmware_header_v2_1(Structure): - pass - -struct_psp_firmware_header_v2_1._pack_ = 1 # source:False -struct_psp_firmware_header_v2_1._fields_ = [ - ('header', struct_common_firmware_header), - ('psp_fw_bin_count', ctypes.c_uint32), - ('psp_aux_fw_bin_index', ctypes.c_uint32), - ('psp_fw_bin', struct_psp_fw_bin_desc * 1), -] - -class struct_ta_firmware_header_v1_0(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_common_firmware_header), - ('xgmi', struct_psp_fw_legacy_bin_desc), - ('ras', struct_psp_fw_legacy_bin_desc), - ('hdcp', struct_psp_fw_legacy_bin_desc), - ('dtm', struct_psp_fw_legacy_bin_desc), - ('securedisplay', struct_psp_fw_legacy_bin_desc), - ] - - -# values for enumeration 'ta_fw_type' -ta_fw_type__enumvalues = { - 0: 'TA_FW_TYPE_UNKOWN', - 1: 'TA_FW_TYPE_PSP_ASD', - 2: 'TA_FW_TYPE_PSP_XGMI', - 3: 'TA_FW_TYPE_PSP_RAS', - 4: 'TA_FW_TYPE_PSP_HDCP', - 5: 'TA_FW_TYPE_PSP_DTM', - 6: 'TA_FW_TYPE_PSP_RAP', - 7: 'TA_FW_TYPE_PSP_SECUREDISPLAY', - 8: 'TA_FW_TYPE_MAX_INDEX', -} -TA_FW_TYPE_UNKOWN = 0 -TA_FW_TYPE_PSP_ASD = 1 -TA_FW_TYPE_PSP_XGMI = 2 -TA_FW_TYPE_PSP_RAS = 3 -TA_FW_TYPE_PSP_HDCP = 4 -TA_FW_TYPE_PSP_DTM = 5 -TA_FW_TYPE_PSP_RAP = 6 -TA_FW_TYPE_PSP_SECUREDISPLAY = 7 -TA_FW_TYPE_MAX_INDEX = 8 -ta_fw_type = ctypes.c_uint32 # enum -class struct_ta_firmware_header_v2_0(Structure): - pass - -struct_ta_firmware_header_v2_0._pack_ = 1 # source:False -struct_ta_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ta_fw_bin_count', ctypes.c_uint32), - ('ta_fw_bin', struct_psp_fw_bin_desc * 1), -] - -class struct_gfx_firmware_header_v1_0(Structure): - pass - -struct_gfx_firmware_header_v1_0._pack_ = 1 # source:False -struct_gfx_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), -] - -class struct_gfx_firmware_header_v2_0(Structure): - pass - -struct_gfx_firmware_header_v2_0._pack_ = 1 # source:False -struct_gfx_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), - ('ucode_offset_bytes', ctypes.c_uint32), - ('data_size_bytes', ctypes.c_uint32), - ('data_offset_bytes', ctypes.c_uint32), - ('ucode_start_addr_lo', ctypes.c_uint32), - ('ucode_start_addr_hi', ctypes.c_uint32), -] - -class struct_mes_firmware_header_v1_0(Structure): - pass - -struct_mes_firmware_header_v1_0._pack_ = 1 # source:False -struct_mes_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('mes_ucode_version', ctypes.c_uint32), - ('mes_ucode_size_bytes', ctypes.c_uint32), - ('mes_ucode_offset_bytes', ctypes.c_uint32), - ('mes_ucode_data_version', ctypes.c_uint32), - ('mes_ucode_data_size_bytes', ctypes.c_uint32), - ('mes_ucode_data_offset_bytes', ctypes.c_uint32), - ('mes_uc_start_addr_lo', ctypes.c_uint32), - ('mes_uc_start_addr_hi', ctypes.c_uint32), - ('mes_data_start_addr_lo', ctypes.c_uint32), - ('mes_data_start_addr_hi', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v1_0(Structure): - pass - -struct_rlc_firmware_header_v1_0._pack_ = 1 # source:False -struct_rlc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('save_and_restore_offset', ctypes.c_uint32), - ('clear_state_descriptor_offset', ctypes.c_uint32), - ('avail_scratch_ram_locations', ctypes.c_uint32), - ('master_pkt_description_offset', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v2_0(Structure): - pass - -struct_rlc_firmware_header_v2_0._pack_ = 1 # source:False -struct_rlc_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), - ('save_and_restore_offset', ctypes.c_uint32), - ('clear_state_descriptor_offset', ctypes.c_uint32), - ('avail_scratch_ram_locations', ctypes.c_uint32), - ('reg_restore_list_size', ctypes.c_uint32), - ('reg_list_format_start', ctypes.c_uint32), - ('reg_list_format_separate_start', ctypes.c_uint32), - ('starting_offsets_start', ctypes.c_uint32), - ('reg_list_format_size_bytes', ctypes.c_uint32), - ('reg_list_format_array_offset_bytes', ctypes.c_uint32), - ('reg_list_size_bytes', ctypes.c_uint32), - ('reg_list_array_offset_bytes', ctypes.c_uint32), - ('reg_list_format_separate_size_bytes', ctypes.c_uint32), - ('reg_list_format_separate_array_offset_bytes', ctypes.c_uint32), - ('reg_list_separate_size_bytes', ctypes.c_uint32), - ('reg_list_separate_array_offset_bytes', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v2_1(Structure): - pass - -struct_rlc_firmware_header_v2_1._pack_ = 1 # source:False -struct_rlc_firmware_header_v2_1._fields_ = [ - ('v2_0', struct_rlc_firmware_header_v2_0), - ('reg_list_format_direct_reg_list_length', ctypes.c_uint32), - ('save_restore_list_cntl_ucode_ver', ctypes.c_uint32), - ('save_restore_list_cntl_feature_ver', ctypes.c_uint32), - ('save_restore_list_cntl_size_bytes', ctypes.c_uint32), - ('save_restore_list_cntl_offset_bytes', ctypes.c_uint32), - ('save_restore_list_gpm_ucode_ver', ctypes.c_uint32), - ('save_restore_list_gpm_feature_ver', ctypes.c_uint32), - ('save_restore_list_gpm_size_bytes', ctypes.c_uint32), - ('save_restore_list_gpm_offset_bytes', ctypes.c_uint32), - ('save_restore_list_srm_ucode_ver', ctypes.c_uint32), - ('save_restore_list_srm_feature_ver', ctypes.c_uint32), - ('save_restore_list_srm_size_bytes', ctypes.c_uint32), - ('save_restore_list_srm_offset_bytes', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v2_2(Structure): - pass - -struct_rlc_firmware_header_v2_2._pack_ = 1 # source:False -struct_rlc_firmware_header_v2_2._fields_ = [ - ('v2_1', struct_rlc_firmware_header_v2_1), - ('rlc_iram_ucode_size_bytes', ctypes.c_uint32), - ('rlc_iram_ucode_offset_bytes', ctypes.c_uint32), - ('rlc_dram_ucode_size_bytes', ctypes.c_uint32), - ('rlc_dram_ucode_offset_bytes', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v2_3(Structure): - pass - -struct_rlc_firmware_header_v2_3._pack_ = 1 # source:False -struct_rlc_firmware_header_v2_3._fields_ = [ - ('v2_2', struct_rlc_firmware_header_v2_2), - ('rlcp_ucode_version', ctypes.c_uint32), - ('rlcp_ucode_feature_version', ctypes.c_uint32), - ('rlcp_ucode_size_bytes', ctypes.c_uint32), - ('rlcp_ucode_offset_bytes', ctypes.c_uint32), - ('rlcv_ucode_version', ctypes.c_uint32), - ('rlcv_ucode_feature_version', ctypes.c_uint32), - ('rlcv_ucode_size_bytes', ctypes.c_uint32), - ('rlcv_ucode_offset_bytes', ctypes.c_uint32), -] - -class struct_rlc_firmware_header_v2_4(Structure): - pass - -struct_rlc_firmware_header_v2_4._pack_ = 1 # source:False -struct_rlc_firmware_header_v2_4._fields_ = [ - ('v2_3', struct_rlc_firmware_header_v2_3), - ('global_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('global_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se0_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se0_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se1_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se1_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se2_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se2_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se3_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se3_tap_delays_ucode_offset_bytes', ctypes.c_uint32), -] - -class struct_sdma_firmware_header_v1_0(Structure): - pass - -struct_sdma_firmware_header_v1_0._pack_ = 1 # source:False -struct_sdma_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_change_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), -] - -class struct_sdma_firmware_header_v1_1(Structure): - pass - -struct_sdma_firmware_header_v1_1._pack_ = 1 # source:False -struct_sdma_firmware_header_v1_1._fields_ = [ - ('v1_0', struct_sdma_firmware_header_v1_0), - ('digest_size', ctypes.c_uint32), -] - -class struct_sdma_firmware_header_v2_0(Structure): - pass - -struct_sdma_firmware_header_v2_0._pack_ = 1 # source:False -struct_sdma_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ctx_ucode_size_bytes', ctypes.c_uint32), - ('ctx_jt_offset', ctypes.c_uint32), - ('ctx_jt_size', ctypes.c_uint32), - ('ctl_ucode_offset', ctypes.c_uint32), - ('ctl_ucode_size_bytes', ctypes.c_uint32), - ('ctl_jt_offset', ctypes.c_uint32), - ('ctl_jt_size', ctypes.c_uint32), -] - -class struct_vpe_firmware_header_v1_0(Structure): - pass - -struct_vpe_firmware_header_v1_0._pack_ = 1 # source:False -struct_vpe_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ctx_ucode_size_bytes', ctypes.c_uint32), - ('ctx_jt_offset', ctypes.c_uint32), - ('ctx_jt_size', ctypes.c_uint32), - ('ctl_ucode_offset', ctypes.c_uint32), - ('ctl_ucode_size_bytes', ctypes.c_uint32), - ('ctl_jt_offset', ctypes.c_uint32), - ('ctl_jt_size', ctypes.c_uint32), -] - -class struct_umsch_mm_firmware_header_v1_0(Structure): - pass - -struct_umsch_mm_firmware_header_v1_0._pack_ = 1 # source:False -struct_umsch_mm_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('umsch_mm_ucode_version', ctypes.c_uint32), - ('umsch_mm_ucode_size_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_offset_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_data_version', ctypes.c_uint32), - ('umsch_mm_ucode_data_size_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_data_offset_bytes', ctypes.c_uint32), - ('umsch_mm_irq_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_irq_start_addr_hi', ctypes.c_uint32), - ('umsch_mm_uc_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_uc_start_addr_hi', ctypes.c_uint32), - ('umsch_mm_data_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_data_start_addr_hi', ctypes.c_uint32), -] - -class struct_sdma_firmware_header_v3_0(Structure): - pass - -struct_sdma_firmware_header_v3_0._pack_ = 1 # source:False -struct_sdma_firmware_header_v3_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_offset_bytes', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), -] - -class struct_gpu_info_firmware_v1_0(Structure): - pass - -struct_gpu_info_firmware_v1_0._pack_ = 1 # source:False -struct_gpu_info_firmware_v1_0._fields_ = [ - ('gc_num_se', ctypes.c_uint32), - ('gc_num_cu_per_sh', ctypes.c_uint32), - ('gc_num_sh_per_se', ctypes.c_uint32), - ('gc_num_rb_per_se', ctypes.c_uint32), - ('gc_num_tccs', ctypes.c_uint32), - ('gc_num_gprs', ctypes.c_uint32), - ('gc_num_max_gs_thds', ctypes.c_uint32), - ('gc_gs_table_depth', ctypes.c_uint32), - ('gc_gsprim_buff_depth', ctypes.c_uint32), - ('gc_parameter_cache_depth', ctypes.c_uint32), - ('gc_double_offchip_lds_buffer', ctypes.c_uint32), - ('gc_wave_size', ctypes.c_uint32), - ('gc_max_waves_per_simd', ctypes.c_uint32), - ('gc_max_scratch_slots_per_cu', ctypes.c_uint32), - ('gc_lds_size', ctypes.c_uint32), -] - -class struct_gpu_info_firmware_v1_1(Structure): - pass - -struct_gpu_info_firmware_v1_1._pack_ = 1 # source:False -struct_gpu_info_firmware_v1_1._fields_ = [ - ('v1_0', struct_gpu_info_firmware_v1_0), - ('num_sc_per_sh', ctypes.c_uint32), - ('num_packer_per_sc', ctypes.c_uint32), -] - -class struct_gpu_info_firmware_header_v1_0(Structure): - pass - -struct_gpu_info_firmware_header_v1_0._pack_ = 1 # source:False -struct_gpu_info_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('version_major', ctypes.c_uint16), - ('version_minor', ctypes.c_uint16), -] - -class struct_dmcu_firmware_header_v1_0(Structure): - pass - -struct_dmcu_firmware_header_v1_0._pack_ = 1 # source:False -struct_dmcu_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('intv_offset_bytes', ctypes.c_uint32), - ('intv_size_bytes', ctypes.c_uint32), -] - -class struct_dmcub_firmware_header_v1_0(Structure): - pass - -struct_dmcub_firmware_header_v1_0._pack_ = 1 # source:False -struct_dmcub_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('inst_const_bytes', ctypes.c_uint32), - ('bss_data_bytes', ctypes.c_uint32), -] - -class struct_imu_firmware_header_v1_0(Structure): - pass - -struct_imu_firmware_header_v1_0._pack_ = 1 # source:False -struct_imu_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('imu_iram_ucode_size_bytes', ctypes.c_uint32), - ('imu_iram_ucode_offset_bytes', ctypes.c_uint32), - ('imu_dram_ucode_size_bytes', ctypes.c_uint32), - ('imu_dram_ucode_offset_bytes', ctypes.c_uint32), -] - -class union_amdgpu_firmware_header(Union): - pass - -union_amdgpu_firmware_header._pack_ = 1 # source:False -union_amdgpu_firmware_header._fields_ = [ - ('common', struct_common_firmware_header), - ('mc', struct_mc_firmware_header_v1_0), - ('smc', struct_smc_firmware_header_v1_0), - ('smc_v2_0', struct_smc_firmware_header_v2_0), - ('psp', struct_psp_firmware_header_v1_0), - ('psp_v1_1', struct_psp_firmware_header_v1_1), - ('psp_v1_3', struct_psp_firmware_header_v1_3), - ('psp_v2_0', struct_psp_firmware_header_v2_0), - ('psp_v2_1', struct_psp_firmware_header_v2_0), - ('ta', struct_ta_firmware_header_v1_0), - ('ta_v2_0', struct_ta_firmware_header_v2_0), - ('gfx', struct_gfx_firmware_header_v1_0), - ('gfx_v2_0', struct_gfx_firmware_header_v2_0), - ('rlc', struct_rlc_firmware_header_v1_0), - ('rlc_v2_0', struct_rlc_firmware_header_v2_0), - ('rlc_v2_1', struct_rlc_firmware_header_v2_1), - ('rlc_v2_2', struct_rlc_firmware_header_v2_2), - ('rlc_v2_3', struct_rlc_firmware_header_v2_3), - ('rlc_v2_4', struct_rlc_firmware_header_v2_4), - ('sdma', struct_sdma_firmware_header_v1_0), - ('sdma_v1_1', struct_sdma_firmware_header_v1_1), - ('sdma_v2_0', struct_sdma_firmware_header_v2_0), - ('sdma_v3_0', struct_sdma_firmware_header_v3_0), - ('gpu_info', struct_gpu_info_firmware_header_v1_0), - ('dmcu', struct_dmcu_firmware_header_v1_0), - ('dmcub', struct_dmcub_firmware_header_v1_0), - ('imu', struct_imu_firmware_header_v1_0), - ('raw', ctypes.c_ubyte * 256), -] - - -# values for enumeration 'AMDGPU_UCODE_ID' -AMDGPU_UCODE_ID__enumvalues = { - 0: 'AMDGPU_UCODE_ID_CAP', - 1: 'AMDGPU_UCODE_ID_SDMA0', - 2: 'AMDGPU_UCODE_ID_SDMA1', - 3: 'AMDGPU_UCODE_ID_SDMA2', - 4: 'AMDGPU_UCODE_ID_SDMA3', - 5: 'AMDGPU_UCODE_ID_SDMA4', - 6: 'AMDGPU_UCODE_ID_SDMA5', - 7: 'AMDGPU_UCODE_ID_SDMA6', - 8: 'AMDGPU_UCODE_ID_SDMA7', - 9: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', - 10: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', - 11: 'AMDGPU_UCODE_ID_SDMA_RS64', - 12: 'AMDGPU_UCODE_ID_CP_CE', - 13: 'AMDGPU_UCODE_ID_CP_PFP', - 14: 'AMDGPU_UCODE_ID_CP_ME', - 15: 'AMDGPU_UCODE_ID_CP_RS64_PFP', - 16: 'AMDGPU_UCODE_ID_CP_RS64_ME', - 17: 'AMDGPU_UCODE_ID_CP_RS64_MEC', - 18: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', - 19: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', - 20: 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', - 21: 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', - 22: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', - 23: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', - 24: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', - 25: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', - 26: 'AMDGPU_UCODE_ID_CP_MEC1', - 27: 'AMDGPU_UCODE_ID_CP_MEC1_JT', - 28: 'AMDGPU_UCODE_ID_CP_MEC2', - 29: 'AMDGPU_UCODE_ID_CP_MEC2_JT', - 30: 'AMDGPU_UCODE_ID_CP_MES', - 31: 'AMDGPU_UCODE_ID_CP_MES_DATA', - 32: 'AMDGPU_UCODE_ID_CP_MES1', - 33: 'AMDGPU_UCODE_ID_CP_MES1_DATA', - 34: 'AMDGPU_UCODE_ID_IMU_I', - 35: 'AMDGPU_UCODE_ID_IMU_D', - 36: 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', - 37: 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', - 38: 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', - 39: 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', - 40: 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', - 41: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', - 42: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', - 43: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', - 44: 'AMDGPU_UCODE_ID_RLC_IRAM', - 45: 'AMDGPU_UCODE_ID_RLC_DRAM', - 46: 'AMDGPU_UCODE_ID_RLC_P', - 47: 'AMDGPU_UCODE_ID_RLC_V', - 48: 'AMDGPU_UCODE_ID_RLC_G', - 49: 'AMDGPU_UCODE_ID_STORAGE', - 50: 'AMDGPU_UCODE_ID_SMC', - 51: 'AMDGPU_UCODE_ID_PPTABLE', - 52: 'AMDGPU_UCODE_ID_UVD', - 53: 'AMDGPU_UCODE_ID_UVD1', - 54: 'AMDGPU_UCODE_ID_VCE', - 55: 'AMDGPU_UCODE_ID_VCN', - 56: 'AMDGPU_UCODE_ID_VCN1', - 57: 'AMDGPU_UCODE_ID_DMCU_ERAM', - 58: 'AMDGPU_UCODE_ID_DMCU_INTV', - 59: 'AMDGPU_UCODE_ID_VCN0_RAM', - 60: 'AMDGPU_UCODE_ID_VCN1_RAM', - 61: 'AMDGPU_UCODE_ID_DMCUB', - 62: 'AMDGPU_UCODE_ID_VPE_CTX', - 63: 'AMDGPU_UCODE_ID_VPE_CTL', - 64: 'AMDGPU_UCODE_ID_VPE', - 65: 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', - 66: 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', - 67: 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', - 68: 'AMDGPU_UCODE_ID_P2S_TABLE', - 69: 'AMDGPU_UCODE_ID_JPEG_RAM', - 70: 'AMDGPU_UCODE_ID_ISP', - 71: 'AMDGPU_UCODE_ID_MAXIMUM', -} -AMDGPU_UCODE_ID_CAP = 0 -AMDGPU_UCODE_ID_SDMA0 = 1 -AMDGPU_UCODE_ID_SDMA1 = 2 -AMDGPU_UCODE_ID_SDMA2 = 3 -AMDGPU_UCODE_ID_SDMA3 = 4 -AMDGPU_UCODE_ID_SDMA4 = 5 -AMDGPU_UCODE_ID_SDMA5 = 6 -AMDGPU_UCODE_ID_SDMA6 = 7 -AMDGPU_UCODE_ID_SDMA7 = 8 -AMDGPU_UCODE_ID_SDMA_UCODE_TH0 = 9 -AMDGPU_UCODE_ID_SDMA_UCODE_TH1 = 10 -AMDGPU_UCODE_ID_SDMA_RS64 = 11 -AMDGPU_UCODE_ID_CP_CE = 12 -AMDGPU_UCODE_ID_CP_PFP = 13 -AMDGPU_UCODE_ID_CP_ME = 14 -AMDGPU_UCODE_ID_CP_RS64_PFP = 15 -AMDGPU_UCODE_ID_CP_RS64_ME = 16 -AMDGPU_UCODE_ID_CP_RS64_MEC = 17 -AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK = 18 -AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK = 19 -AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK = 20 -AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK = 21 -AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK = 22 -AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK = 23 -AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK = 24 -AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK = 25 -AMDGPU_UCODE_ID_CP_MEC1 = 26 -AMDGPU_UCODE_ID_CP_MEC1_JT = 27 -AMDGPU_UCODE_ID_CP_MEC2 = 28 -AMDGPU_UCODE_ID_CP_MEC2_JT = 29 -AMDGPU_UCODE_ID_CP_MES = 30 -AMDGPU_UCODE_ID_CP_MES_DATA = 31 -AMDGPU_UCODE_ID_CP_MES1 = 32 -AMDGPU_UCODE_ID_CP_MES1_DATA = 33 -AMDGPU_UCODE_ID_IMU_I = 34 -AMDGPU_UCODE_ID_IMU_D = 35 -AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS = 36 -AMDGPU_UCODE_ID_SE0_TAP_DELAYS = 37 -AMDGPU_UCODE_ID_SE1_TAP_DELAYS = 38 -AMDGPU_UCODE_ID_SE2_TAP_DELAYS = 39 -AMDGPU_UCODE_ID_SE3_TAP_DELAYS = 40 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL = 41 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM = 42 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM = 43 -AMDGPU_UCODE_ID_RLC_IRAM = 44 -AMDGPU_UCODE_ID_RLC_DRAM = 45 -AMDGPU_UCODE_ID_RLC_P = 46 -AMDGPU_UCODE_ID_RLC_V = 47 -AMDGPU_UCODE_ID_RLC_G = 48 -AMDGPU_UCODE_ID_STORAGE = 49 -AMDGPU_UCODE_ID_SMC = 50 -AMDGPU_UCODE_ID_PPTABLE = 51 -AMDGPU_UCODE_ID_UVD = 52 -AMDGPU_UCODE_ID_UVD1 = 53 -AMDGPU_UCODE_ID_VCE = 54 -AMDGPU_UCODE_ID_VCN = 55 -AMDGPU_UCODE_ID_VCN1 = 56 -AMDGPU_UCODE_ID_DMCU_ERAM = 57 -AMDGPU_UCODE_ID_DMCU_INTV = 58 -AMDGPU_UCODE_ID_VCN0_RAM = 59 -AMDGPU_UCODE_ID_VCN1_RAM = 60 -AMDGPU_UCODE_ID_DMCUB = 61 -AMDGPU_UCODE_ID_VPE_CTX = 62 -AMDGPU_UCODE_ID_VPE_CTL = 63 -AMDGPU_UCODE_ID_VPE = 64 -AMDGPU_UCODE_ID_UMSCH_MM_UCODE = 65 -AMDGPU_UCODE_ID_UMSCH_MM_DATA = 66 -AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER = 67 -AMDGPU_UCODE_ID_P2S_TABLE = 68 -AMDGPU_UCODE_ID_JPEG_RAM = 69 -AMDGPU_UCODE_ID_ISP = 70 -AMDGPU_UCODE_ID_MAXIMUM = 71 -AMDGPU_UCODE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'AMDGPU_UCODE_STATUS' -AMDGPU_UCODE_STATUS__enumvalues = { - 0: 'AMDGPU_UCODE_STATUS_INVALID', - 1: 'AMDGPU_UCODE_STATUS_NOT_LOADED', - 2: 'AMDGPU_UCODE_STATUS_LOADED', -} -AMDGPU_UCODE_STATUS_INVALID = 0 -AMDGPU_UCODE_STATUS_NOT_LOADED = 1 -AMDGPU_UCODE_STATUS_LOADED = 2 -AMDGPU_UCODE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'amdgpu_firmware_load_type' -amdgpu_firmware_load_type__enumvalues = { - 0: 'AMDGPU_FW_LOAD_DIRECT', - 1: 'AMDGPU_FW_LOAD_PSP', - 2: 'AMDGPU_FW_LOAD_SMU', - 3: 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', -} -AMDGPU_FW_LOAD_DIRECT = 0 -AMDGPU_FW_LOAD_PSP = 1 -AMDGPU_FW_LOAD_SMU = 2 -AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO = 3 -amdgpu_firmware_load_type = ctypes.c_uint32 # enum -class struct_amdgpu_firmware_info(Structure): - pass - -class struct_firmware(Structure): - pass - -struct_amdgpu_firmware_info._pack_ = 1 # source:False -struct_amdgpu_firmware_info._fields_ = [ - ('ucode_id', AMDGPU_UCODE_ID), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fw', ctypes.POINTER(struct_firmware)), - ('mc_addr', ctypes.c_uint64), - ('kaddr', ctypes.POINTER(None)), - ('ucode_size', ctypes.c_uint32), - ('tmr_mc_addr_lo', ctypes.c_uint32), - ('tmr_mc_addr_hi', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -_PSP_TEE_GFX_IF_H_ = True # macro -PSP_GFX_CMD_BUF_VERSION = 0x00000001 # macro -GFX_CMD_STATUS_MASK = 0x0000FFFF # macro -GFX_CMD_ID_MASK = 0x000F0000 # macro -GFX_CMD_RESERVED_MASK = 0x7FF00000 # macro -GFX_CMD_RESPONSE_MASK = 0x80000000 # macro -C2PMSG_CMD_GFX_USB_PD_FW_VER = 0x2000000 # macro -GFX_FLAG_RESPONSE = 0x80000000 # macro -GFX_BUF_MAX_DESC = 64 # macro -FRAME_TYPE_DESTROY = 1 # macro -PSP_ERR_UNKNOWN_COMMAND = 0x00000100 # macro - -# values for enumeration 'psp_gfx_crtl_cmd_id' -psp_gfx_crtl_cmd_id__enumvalues = { - 65536: 'GFX_CTRL_CMD_ID_INIT_RBI_RING', - 131072: 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', - 196608: 'GFX_CTRL_CMD_ID_DESTROY_RINGS', - 262144: 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', - 327680: 'GFX_CTRL_CMD_ID_ENABLE_INT', - 393216: 'GFX_CTRL_CMD_ID_DISABLE_INT', - 458752: 'GFX_CTRL_CMD_ID_MODE1_RST', - 524288: 'GFX_CTRL_CMD_ID_GBR_IH_SET', - 589824: 'GFX_CTRL_CMD_ID_CONSUME_CMD', - 786432: 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', - 983040: 'GFX_CTRL_CMD_ID_MAX', -} -GFX_CTRL_CMD_ID_INIT_RBI_RING = 65536 -GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 131072 -GFX_CTRL_CMD_ID_DESTROY_RINGS = 196608 -GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 262144 -GFX_CTRL_CMD_ID_ENABLE_INT = 327680 -GFX_CTRL_CMD_ID_DISABLE_INT = 393216 -GFX_CTRL_CMD_ID_MODE1_RST = 458752 -GFX_CTRL_CMD_ID_GBR_IH_SET = 524288 -GFX_CTRL_CMD_ID_CONSUME_CMD = 589824 -GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 786432 -GFX_CTRL_CMD_ID_MAX = 983040 -psp_gfx_crtl_cmd_id = ctypes.c_uint32 # enum -class struct_psp_gfx_ctrl(Structure): - pass - -struct_psp_gfx_ctrl._pack_ = 1 # source:False -struct_psp_gfx_ctrl._fields_ = [ - ('cmd_resp', ctypes.c_uint32), - ('rbi_wptr', ctypes.c_uint32), - ('rbi_rptr', ctypes.c_uint32), - ('gpcom_wptr', ctypes.c_uint32), - ('gpcom_rptr', ctypes.c_uint32), - ('ring_addr_lo', ctypes.c_uint32), - ('ring_addr_hi', ctypes.c_uint32), - ('ring_buf_size', ctypes.c_uint32), -] - - -# values for enumeration 'psp_gfx_cmd_id' -psp_gfx_cmd_id__enumvalues = { - 1: 'GFX_CMD_ID_LOAD_TA', - 2: 'GFX_CMD_ID_UNLOAD_TA', - 3: 'GFX_CMD_ID_INVOKE_CMD', - 4: 'GFX_CMD_ID_LOAD_ASD', - 5: 'GFX_CMD_ID_SETUP_TMR', - 6: 'GFX_CMD_ID_LOAD_IP_FW', - 7: 'GFX_CMD_ID_DESTROY_TMR', - 8: 'GFX_CMD_ID_SAVE_RESTORE', - 9: 'GFX_CMD_ID_SETUP_VMR', - 10: 'GFX_CMD_ID_DESTROY_VMR', - 11: 'GFX_CMD_ID_PROG_REG', - 15: 'GFX_CMD_ID_GET_FW_ATTESTATION', - 32: 'GFX_CMD_ID_LOAD_TOC', - 33: 'GFX_CMD_ID_AUTOLOAD_RLC', - 34: 'GFX_CMD_ID_BOOT_CFG', - 39: 'GFX_CMD_ID_SRIOV_SPATIAL_PART', -} -GFX_CMD_ID_LOAD_TA = 1 -GFX_CMD_ID_UNLOAD_TA = 2 -GFX_CMD_ID_INVOKE_CMD = 3 -GFX_CMD_ID_LOAD_ASD = 4 -GFX_CMD_ID_SETUP_TMR = 5 -GFX_CMD_ID_LOAD_IP_FW = 6 -GFX_CMD_ID_DESTROY_TMR = 7 -GFX_CMD_ID_SAVE_RESTORE = 8 -GFX_CMD_ID_SETUP_VMR = 9 -GFX_CMD_ID_DESTROY_VMR = 10 -GFX_CMD_ID_PROG_REG = 11 -GFX_CMD_ID_GET_FW_ATTESTATION = 15 -GFX_CMD_ID_LOAD_TOC = 32 -GFX_CMD_ID_AUTOLOAD_RLC = 33 -GFX_CMD_ID_BOOT_CFG = 34 -GFX_CMD_ID_SRIOV_SPATIAL_PART = 39 -psp_gfx_cmd_id = ctypes.c_uint32 # enum - -# values for enumeration 'psp_gfx_boot_config_cmd' -psp_gfx_boot_config_cmd__enumvalues = { - 1: 'BOOTCFG_CMD_SET', - 2: 'BOOTCFG_CMD_GET', - 3: 'BOOTCFG_CMD_INVALIDATE', -} -BOOTCFG_CMD_SET = 1 -BOOTCFG_CMD_GET = 2 -BOOTCFG_CMD_INVALIDATE = 3 -psp_gfx_boot_config_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'psp_gfx_boot_config' -psp_gfx_boot_config__enumvalues = { - 1: 'BOOT_CONFIG_GECC', -} -BOOT_CONFIG_GECC = 1 -psp_gfx_boot_config = ctypes.c_uint32 # enum -class struct_psp_gfx_cmd_load_ta(Structure): - pass - -struct_psp_gfx_cmd_load_ta._pack_ = 1 # source:False -struct_psp_gfx_cmd_load_ta._fields_ = [ - ('app_phy_addr_lo', ctypes.c_uint32), - ('app_phy_addr_hi', ctypes.c_uint32), - ('app_len', ctypes.c_uint32), - ('cmd_buf_phy_addr_lo', ctypes.c_uint32), - ('cmd_buf_phy_addr_hi', ctypes.c_uint32), - ('cmd_buf_len', ctypes.c_uint32), -] - -class struct_psp_gfx_cmd_unload_ta(Structure): - pass - -struct_psp_gfx_cmd_unload_ta._pack_ = 1 # source:False -struct_psp_gfx_cmd_unload_ta._fields_ = [ - ('session_id', ctypes.c_uint32), -] - -class struct_psp_gfx_buf_desc(Structure): - pass - -struct_psp_gfx_buf_desc._pack_ = 1 # source:False -struct_psp_gfx_buf_desc._fields_ = [ - ('buf_phy_addr_lo', ctypes.c_uint32), - ('buf_phy_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), -] - -class struct_psp_gfx_buf_list(Structure): - pass - -struct_psp_gfx_buf_list._pack_ = 1 # source:False -struct_psp_gfx_buf_list._fields_ = [ - ('num_desc', ctypes.c_uint32), - ('total_size', ctypes.c_uint32), - ('buf_desc', struct_psp_gfx_buf_desc * 64), -] - -class struct_psp_gfx_cmd_invoke_cmd(Structure): - pass - -struct_psp_gfx_cmd_invoke_cmd._pack_ = 1 # source:False -struct_psp_gfx_cmd_invoke_cmd._fields_ = [ - ('session_id', ctypes.c_uint32), - ('ta_cmd_id', ctypes.c_uint32), - ('buf', struct_psp_gfx_buf_list), -] - -class struct_psp_gfx_cmd_setup_tmr(Structure): - pass - -class union_psp_gfx_cmd_setup_tmr_0(Union): - pass - -class struct_psp_gfx_cmd_setup_tmr_0_bitfield(Structure): - pass - -struct_psp_gfx_cmd_setup_tmr_0_bitfield._pack_ = 1 # source:False -struct_psp_gfx_cmd_setup_tmr_0_bitfield._fields_ = [ - ('sriov_enabled', ctypes.c_uint32, 1), - ('virt_phy_addr', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 30), -] - -union_psp_gfx_cmd_setup_tmr_0._pack_ = 1 # source:False -union_psp_gfx_cmd_setup_tmr_0._fields_ = [ - ('bitfield', struct_psp_gfx_cmd_setup_tmr_0_bitfield), - ('tmr_flags', ctypes.c_uint32), -] - -struct_psp_gfx_cmd_setup_tmr._pack_ = 1 # source:False -struct_psp_gfx_cmd_setup_tmr._anonymous_ = ('_0',) -struct_psp_gfx_cmd_setup_tmr._fields_ = [ - ('buf_phy_addr_lo', ctypes.c_uint32), - ('buf_phy_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), - ('_0', union_psp_gfx_cmd_setup_tmr_0), - ('system_phy_addr_lo', ctypes.c_uint32), - ('system_phy_addr_hi', ctypes.c_uint32), -] - - -# values for enumeration 'psp_gfx_fw_type' -psp_gfx_fw_type__enumvalues = { - 0: 'GFX_FW_TYPE_NONE', - 1: 'GFX_FW_TYPE_CP_ME', - 2: 'GFX_FW_TYPE_CP_PFP', - 3: 'GFX_FW_TYPE_CP_CE', - 4: 'GFX_FW_TYPE_CP_MEC', - 5: 'GFX_FW_TYPE_CP_MEC_ME1', - 6: 'GFX_FW_TYPE_CP_MEC_ME2', - 7: 'GFX_FW_TYPE_RLC_V', - 8: 'GFX_FW_TYPE_RLC_G', - 9: 'GFX_FW_TYPE_SDMA0', - 10: 'GFX_FW_TYPE_SDMA1', - 11: 'GFX_FW_TYPE_DMCU_ERAM', - 12: 'GFX_FW_TYPE_DMCU_ISR', - 13: 'GFX_FW_TYPE_VCN', - 14: 'GFX_FW_TYPE_UVD', - 15: 'GFX_FW_TYPE_VCE', - 16: 'GFX_FW_TYPE_ISP', - 17: 'GFX_FW_TYPE_ACP', - 18: 'GFX_FW_TYPE_SMU', - 19: 'GFX_FW_TYPE_MMSCH', - 20: 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', - 21: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', - 22: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', - 23: 'GFX_FW_TYPE_UVD1', - 24: 'GFX_FW_TYPE_TOC', - 25: 'GFX_FW_TYPE_RLC_P', - 26: 'GFX_FW_TYPE_RLC_IRAM', - 27: 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', - 28: 'GFX_FW_TYPE_SE0_TAP_DELAYS', - 29: 'GFX_FW_TYPE_SE1_TAP_DELAYS', - 30: 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', - 31: 'GFX_FW_TYPE_SDMA0_JT', - 32: 'GFX_FW_TYPE_SDMA1_JT', - 33: 'GFX_FW_TYPE_CP_MES', - 34: 'GFX_FW_TYPE_MES_STACK', - 35: 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', - 36: 'GFX_FW_TYPE_RLCG_SCRATCH_SR', - 37: 'GFX_FW_TYPE_RLCP_SCRATCH_SR', - 38: 'GFX_FW_TYPE_RLCV_SCRATCH_SR', - 39: 'GFX_FW_TYPE_RLX6_DRAM_SR', - 40: 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', - 41: 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', - 42: 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', - 43: 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', - 44: 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', - 45: 'GFX_FW_TYPE_ACCUM_CTRL_RAM', - 46: 'GFX_FW_TYPE_RLCP_CAM', - 47: 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', - 48: 'GFX_FW_TYPE_RLC_DRAM_BOOT', - 49: 'GFX_FW_TYPE_VCN0_RAM', - 50: 'GFX_FW_TYPE_VCN1_RAM', - 51: 'GFX_FW_TYPE_DMUB', - 52: 'GFX_FW_TYPE_SDMA2', - 53: 'GFX_FW_TYPE_SDMA3', - 54: 'GFX_FW_TYPE_SDMA4', - 55: 'GFX_FW_TYPE_SDMA5', - 56: 'GFX_FW_TYPE_SDMA6', - 57: 'GFX_FW_TYPE_SDMA7', - 58: 'GFX_FW_TYPE_VCN1', - 62: 'GFX_FW_TYPE_CAP', - 65: 'GFX_FW_TYPE_SE2_TAP_DELAYS', - 66: 'GFX_FW_TYPE_SE3_TAP_DELAYS', - 67: 'GFX_FW_TYPE_REG_LIST', - 68: 'GFX_FW_TYPE_IMU_I', - 69: 'GFX_FW_TYPE_IMU_D', - 70: 'GFX_FW_TYPE_LSDMA', - 71: 'GFX_FW_TYPE_SDMA_UCODE_TH0', - 72: 'GFX_FW_TYPE_SDMA_UCODE_TH1', - 73: 'GFX_FW_TYPE_PPTABLE', - 74: 'GFX_FW_TYPE_DISCRETE_USB4', - 75: 'GFX_FW_TYPE_TA', - 76: 'GFX_FW_TYPE_RS64_MES', - 77: 'GFX_FW_TYPE_RS64_MES_STACK', - 78: 'GFX_FW_TYPE_RS64_KIQ', - 79: 'GFX_FW_TYPE_RS64_KIQ_STACK', - 80: 'GFX_FW_TYPE_ISP_DATA', - 81: 'GFX_FW_TYPE_CP_MES_KIQ', - 82: 'GFX_FW_TYPE_MES_KIQ_STACK', - 83: 'GFX_FW_TYPE_UMSCH_DATA', - 84: 'GFX_FW_TYPE_UMSCH_UCODE', - 85: 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', - 86: 'GFX_FW_TYPE_USB_DP_COMBO_PHY', - 87: 'GFX_FW_TYPE_RS64_PFP', - 88: 'GFX_FW_TYPE_RS64_ME', - 89: 'GFX_FW_TYPE_RS64_MEC', - 90: 'GFX_FW_TYPE_RS64_PFP_P0_STACK', - 91: 'GFX_FW_TYPE_RS64_PFP_P1_STACK', - 92: 'GFX_FW_TYPE_RS64_ME_P0_STACK', - 93: 'GFX_FW_TYPE_RS64_ME_P1_STACK', - 94: 'GFX_FW_TYPE_RS64_MEC_P0_STACK', - 95: 'GFX_FW_TYPE_RS64_MEC_P1_STACK', - 96: 'GFX_FW_TYPE_RS64_MEC_P2_STACK', - 97: 'GFX_FW_TYPE_RS64_MEC_P3_STACK', - 100: 'GFX_FW_TYPE_VPEC_FW1', - 101: 'GFX_FW_TYPE_VPEC_FW2', - 102: 'GFX_FW_TYPE_VPE', - 128: 'GFX_FW_TYPE_JPEG_RAM', - 129: 'GFX_FW_TYPE_P2S_TABLE', - 130: 'GFX_FW_TYPE_MAX', -} -GFX_FW_TYPE_NONE = 0 -GFX_FW_TYPE_CP_ME = 1 -GFX_FW_TYPE_CP_PFP = 2 -GFX_FW_TYPE_CP_CE = 3 -GFX_FW_TYPE_CP_MEC = 4 -GFX_FW_TYPE_CP_MEC_ME1 = 5 -GFX_FW_TYPE_CP_MEC_ME2 = 6 -GFX_FW_TYPE_RLC_V = 7 -GFX_FW_TYPE_RLC_G = 8 -GFX_FW_TYPE_SDMA0 = 9 -GFX_FW_TYPE_SDMA1 = 10 -GFX_FW_TYPE_DMCU_ERAM = 11 -GFX_FW_TYPE_DMCU_ISR = 12 -GFX_FW_TYPE_VCN = 13 -GFX_FW_TYPE_UVD = 14 -GFX_FW_TYPE_VCE = 15 -GFX_FW_TYPE_ISP = 16 -GFX_FW_TYPE_ACP = 17 -GFX_FW_TYPE_SMU = 18 -GFX_FW_TYPE_MMSCH = 19 -GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20 -GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21 -GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22 -GFX_FW_TYPE_UVD1 = 23 -GFX_FW_TYPE_TOC = 24 -GFX_FW_TYPE_RLC_P = 25 -GFX_FW_TYPE_RLC_IRAM = 26 -GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27 -GFX_FW_TYPE_SE0_TAP_DELAYS = 28 -GFX_FW_TYPE_SE1_TAP_DELAYS = 29 -GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30 -GFX_FW_TYPE_SDMA0_JT = 31 -GFX_FW_TYPE_SDMA1_JT = 32 -GFX_FW_TYPE_CP_MES = 33 -GFX_FW_TYPE_MES_STACK = 34 -GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35 -GFX_FW_TYPE_RLCG_SCRATCH_SR = 36 -GFX_FW_TYPE_RLCP_SCRATCH_SR = 37 -GFX_FW_TYPE_RLCV_SCRATCH_SR = 38 -GFX_FW_TYPE_RLX6_DRAM_SR = 39 -GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40 -GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41 -GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42 -GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43 -GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44 -GFX_FW_TYPE_ACCUM_CTRL_RAM = 45 -GFX_FW_TYPE_RLCP_CAM = 46 -GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47 -GFX_FW_TYPE_RLC_DRAM_BOOT = 48 -GFX_FW_TYPE_VCN0_RAM = 49 -GFX_FW_TYPE_VCN1_RAM = 50 -GFX_FW_TYPE_DMUB = 51 -GFX_FW_TYPE_SDMA2 = 52 -GFX_FW_TYPE_SDMA3 = 53 -GFX_FW_TYPE_SDMA4 = 54 -GFX_FW_TYPE_SDMA5 = 55 -GFX_FW_TYPE_SDMA6 = 56 -GFX_FW_TYPE_SDMA7 = 57 -GFX_FW_TYPE_VCN1 = 58 -GFX_FW_TYPE_CAP = 62 -GFX_FW_TYPE_SE2_TAP_DELAYS = 65 -GFX_FW_TYPE_SE3_TAP_DELAYS = 66 -GFX_FW_TYPE_REG_LIST = 67 -GFX_FW_TYPE_IMU_I = 68 -GFX_FW_TYPE_IMU_D = 69 -GFX_FW_TYPE_LSDMA = 70 -GFX_FW_TYPE_SDMA_UCODE_TH0 = 71 -GFX_FW_TYPE_SDMA_UCODE_TH1 = 72 -GFX_FW_TYPE_PPTABLE = 73 -GFX_FW_TYPE_DISCRETE_USB4 = 74 -GFX_FW_TYPE_TA = 75 -GFX_FW_TYPE_RS64_MES = 76 -GFX_FW_TYPE_RS64_MES_STACK = 77 -GFX_FW_TYPE_RS64_KIQ = 78 -GFX_FW_TYPE_RS64_KIQ_STACK = 79 -GFX_FW_TYPE_ISP_DATA = 80 -GFX_FW_TYPE_CP_MES_KIQ = 81 -GFX_FW_TYPE_MES_KIQ_STACK = 82 -GFX_FW_TYPE_UMSCH_DATA = 83 -GFX_FW_TYPE_UMSCH_UCODE = 84 -GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85 -GFX_FW_TYPE_USB_DP_COMBO_PHY = 86 -GFX_FW_TYPE_RS64_PFP = 87 -GFX_FW_TYPE_RS64_ME = 88 -GFX_FW_TYPE_RS64_MEC = 89 -GFX_FW_TYPE_RS64_PFP_P0_STACK = 90 -GFX_FW_TYPE_RS64_PFP_P1_STACK = 91 -GFX_FW_TYPE_RS64_ME_P0_STACK = 92 -GFX_FW_TYPE_RS64_ME_P1_STACK = 93 -GFX_FW_TYPE_RS64_MEC_P0_STACK = 94 -GFX_FW_TYPE_RS64_MEC_P1_STACK = 95 -GFX_FW_TYPE_RS64_MEC_P2_STACK = 96 -GFX_FW_TYPE_RS64_MEC_P3_STACK = 97 -GFX_FW_TYPE_VPEC_FW1 = 100 -GFX_FW_TYPE_VPEC_FW2 = 101 -GFX_FW_TYPE_VPE = 102 -GFX_FW_TYPE_JPEG_RAM = 128 -GFX_FW_TYPE_P2S_TABLE = 129 -GFX_FW_TYPE_MAX = 130 -psp_gfx_fw_type = ctypes.c_uint32 # enum -class struct_psp_gfx_cmd_load_ip_fw(Structure): - pass - -struct_psp_gfx_cmd_load_ip_fw._pack_ = 1 # source:False -struct_psp_gfx_cmd_load_ip_fw._fields_ = [ - ('fw_phy_addr_lo', ctypes.c_uint32), - ('fw_phy_addr_hi', ctypes.c_uint32), - ('fw_size', ctypes.c_uint32), - ('fw_type', psp_gfx_fw_type), -] - -class struct_psp_gfx_cmd_save_restore_ip_fw(Structure): - pass - -struct_psp_gfx_cmd_save_restore_ip_fw._pack_ = 1 # source:False -struct_psp_gfx_cmd_save_restore_ip_fw._fields_ = [ - ('save_fw', ctypes.c_uint32), - ('save_restore_addr_lo', ctypes.c_uint32), - ('save_restore_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), - ('fw_type', psp_gfx_fw_type), -] - -class struct_psp_gfx_cmd_reg_prog(Structure): - pass - -struct_psp_gfx_cmd_reg_prog._pack_ = 1 # source:False -struct_psp_gfx_cmd_reg_prog._fields_ = [ - ('reg_value', ctypes.c_uint32), - ('reg_id', ctypes.c_uint32), -] - -class struct_psp_gfx_cmd_load_toc(Structure): - pass - -struct_psp_gfx_cmd_load_toc._pack_ = 1 # source:False -struct_psp_gfx_cmd_load_toc._fields_ = [ - ('toc_phy_addr_lo', ctypes.c_uint32), - ('toc_phy_addr_hi', ctypes.c_uint32), - ('toc_size', ctypes.c_uint32), -] - -class struct_psp_gfx_cmd_boot_cfg(Structure): - pass - -struct_psp_gfx_cmd_boot_cfg._pack_ = 1 # source:False -struct_psp_gfx_cmd_boot_cfg._fields_ = [ - ('timestamp', ctypes.c_uint32), - ('sub_cmd', psp_gfx_boot_config_cmd), - ('boot_config', ctypes.c_uint32), - ('boot_config_valid', ctypes.c_uint32), -] - -class struct_psp_gfx_cmd_sriov_spatial_part(Structure): - pass - -struct_psp_gfx_cmd_sriov_spatial_part._pack_ = 1 # source:False -struct_psp_gfx_cmd_sriov_spatial_part._fields_ = [ - ('mode', ctypes.c_uint32), - ('override_ips', ctypes.c_uint32), - ('override_xcds_avail', ctypes.c_uint32), - ('override_this_aid', ctypes.c_uint32), -] - -class union_psp_gfx_commands(Union): - pass - -union_psp_gfx_commands._pack_ = 1 # source:False -union_psp_gfx_commands._fields_ = [ - ('cmd_load_ta', struct_psp_gfx_cmd_load_ta), - ('cmd_unload_ta', struct_psp_gfx_cmd_unload_ta), - ('cmd_invoke_cmd', struct_psp_gfx_cmd_invoke_cmd), - ('cmd_setup_tmr', struct_psp_gfx_cmd_setup_tmr), - ('cmd_load_ip_fw', struct_psp_gfx_cmd_load_ip_fw), - ('cmd_save_restore_ip_fw', struct_psp_gfx_cmd_save_restore_ip_fw), - ('cmd_setup_reg_prog', struct_psp_gfx_cmd_reg_prog), - ('cmd_setup_vmr', struct_psp_gfx_cmd_setup_tmr), - ('cmd_load_toc', struct_psp_gfx_cmd_load_toc), - ('boot_cfg', struct_psp_gfx_cmd_boot_cfg), - ('cmd_spatial_part', struct_psp_gfx_cmd_sriov_spatial_part), - ('PADDING_0', ctypes.c_ubyte * 768), -] - -class struct_psp_gfx_uresp_reserved(Structure): - pass - -struct_psp_gfx_uresp_reserved._pack_ = 1 # source:False -struct_psp_gfx_uresp_reserved._fields_ = [ - ('reserved', ctypes.c_uint32 * 8), -] - -class struct_psp_gfx_uresp_fwar_db_info(Structure): - pass - -struct_psp_gfx_uresp_fwar_db_info._pack_ = 1 # source:False -struct_psp_gfx_uresp_fwar_db_info._fields_ = [ - ('fwar_db_addr_lo', ctypes.c_uint32), - ('fwar_db_addr_hi', ctypes.c_uint32), -] - -class struct_psp_gfx_uresp_bootcfg(Structure): - pass - -struct_psp_gfx_uresp_bootcfg._pack_ = 1 # source:False -struct_psp_gfx_uresp_bootcfg._fields_ = [ - ('boot_cfg', ctypes.c_uint32), -] - -class union_psp_gfx_uresp(Union): - pass - -union_psp_gfx_uresp._pack_ = 1 # source:False -union_psp_gfx_uresp._fields_ = [ - ('reserved', struct_psp_gfx_uresp_reserved), - ('boot_cfg', struct_psp_gfx_uresp_bootcfg), - ('fwar_db_info', struct_psp_gfx_uresp_fwar_db_info), - ('PADDING_0', ctypes.c_ubyte * 24), -] - -class struct_psp_gfx_resp(Structure): - pass - -struct_psp_gfx_resp._pack_ = 1 # source:False -struct_psp_gfx_resp._fields_ = [ - ('status', ctypes.c_uint32), - ('session_id', ctypes.c_uint32), - ('fw_addr_lo', ctypes.c_uint32), - ('fw_addr_hi', ctypes.c_uint32), - ('tmr_size', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 11), - ('uresp', union_psp_gfx_uresp), -] - -class struct_psp_gfx_cmd_resp(Structure): - pass - -struct_psp_gfx_cmd_resp._pack_ = 1 # source:False -struct_psp_gfx_cmd_resp._fields_ = [ - ('buf_size', ctypes.c_uint32), - ('buf_version', ctypes.c_uint32), - ('cmd_id', ctypes.c_uint32), - ('resp_buf_addr_lo', ctypes.c_uint32), - ('resp_buf_addr_hi', ctypes.c_uint32), - ('resp_offset', ctypes.c_uint32), - ('resp_buf_size', ctypes.c_uint32), - ('cmd', union_psp_gfx_commands), - ('reserved_1', ctypes.c_ubyte * 52), - ('resp', struct_psp_gfx_resp), - ('reserved_2', ctypes.c_ubyte * 64), -] - -class struct_psp_gfx_rb_frame(Structure): - pass - -struct_psp_gfx_rb_frame._pack_ = 1 # source:False -struct_psp_gfx_rb_frame._fields_ = [ - ('cmd_buf_addr_lo', ctypes.c_uint32), - ('cmd_buf_addr_hi', ctypes.c_uint32), - ('cmd_buf_size', ctypes.c_uint32), - ('fence_addr_lo', ctypes.c_uint32), - ('fence_addr_hi', ctypes.c_uint32), - ('fence_value', ctypes.c_uint32), - ('sid_lo', ctypes.c_uint32), - ('sid_hi', ctypes.c_uint32), - ('vmid', ctypes.c_ubyte), - ('frame_type', ctypes.c_ubyte), - ('reserved1', ctypes.c_ubyte * 2), - ('reserved2', ctypes.c_uint32 * 7), -] - - -# values for enumeration 'tee_error_code' -tee_error_code__enumvalues = { - 0: 'TEE_SUCCESS', - 4294901770: 'TEE_ERROR_NOT_SUPPORTED', -} -TEE_SUCCESS = 0 -TEE_ERROR_NOT_SUPPORTED = 4294901770 -tee_error_code = ctypes.c_uint32 # enum -__AMDGPU_PSP_H__ = True # macro -PSP_FENCE_BUFFER_SIZE = 0x1000 # macro -PSP_CMD_BUFFER_SIZE = 0x1000 # macro -PSP_1_MEG = 0x100000 # macro -# def PSP_TMR_SIZE(adev): # macro -# return ((adev)->asic_type==CHIP_ALDEBARAN?0x800000:0x400000) -PSP_TMR_ALIGNMENT = 0x100000 # macro -PSP_FW_NAME_LEN = 0x24 # macro -AMDGPU_XGMI_MAX_CONNECTED_NODES = 64 # macro -MEM_TRAIN_SYSTEM_SIGNATURE = 0x54534942 # macro -GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES = 0x1000 # macro -GDDR6_MEM_TRAINING_OFFSET = 0x8000 # macro -BIST_MEM_TRAINING_ENCROACHED_SIZE = 0x2000000 # macro -PSP_RUNTIME_DB_SIZE_IN_BYTES = 0x10000 # macro -PSP_RUNTIME_DB_OFFSET = 0x100000 # macro -PSP_RUNTIME_DB_COOKIE_ID = 0x0ed5 # macro -PSP_RUNTIME_DB_VER_1 = 0x0100 # macro -PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT = 0x40 # macro - -# values for enumeration 'psp_shared_mem_size' -psp_shared_mem_size__enumvalues = { - 0: 'PSP_ASD_SHARED_MEM_SIZE', - 16384: 'PSP_XGMI_SHARED_MEM_SIZE', - 16384: 'PSP_RAS_SHARED_MEM_SIZE', - 16384: 'PSP_HDCP_SHARED_MEM_SIZE', - 16384: 'PSP_DTM_SHARED_MEM_SIZE', - 16384: 'PSP_RAP_SHARED_MEM_SIZE', - 16384: 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', -} -PSP_ASD_SHARED_MEM_SIZE = 0 -PSP_XGMI_SHARED_MEM_SIZE = 16384 -PSP_RAS_SHARED_MEM_SIZE = 16384 -PSP_HDCP_SHARED_MEM_SIZE = 16384 -PSP_DTM_SHARED_MEM_SIZE = 16384 -PSP_RAP_SHARED_MEM_SIZE = 16384 -PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 16384 -psp_shared_mem_size = ctypes.c_uint32 # enum - -# values for enumeration 'ta_type_id' -ta_type_id__enumvalues = { - 1: 'TA_TYPE_XGMI', - 2: 'TA_TYPE_RAS', - 3: 'TA_TYPE_HDCP', - 4: 'TA_TYPE_DTM', - 5: 'TA_TYPE_RAP', - 6: 'TA_TYPE_SECUREDISPLAY', - 7: 'TA_TYPE_MAX_INDEX', -} -TA_TYPE_XGMI = 1 -TA_TYPE_RAS = 2 -TA_TYPE_HDCP = 3 -TA_TYPE_DTM = 4 -TA_TYPE_RAP = 5 -TA_TYPE_SECUREDISPLAY = 6 -TA_TYPE_MAX_INDEX = 7 -ta_type_id = ctypes.c_uint32 # enum -class struct_psp_context(Structure): - pass - -class struct_psp_xgmi_node_info(Structure): - pass - -class struct_psp_xgmi_topology_info(Structure): - pass - -class struct_psp_bin_desc(Structure): - pass - - -# values for enumeration 'psp_bootloader_cmd' -psp_bootloader_cmd__enumvalues = { - 65536: 'PSP_BL__LOAD_SYSDRV', - 131072: 'PSP_BL__LOAD_SOSDRV', - 524288: 'PSP_BL__LOAD_KEY_DATABASE', - 720896: 'PSP_BL__LOAD_SOCDRV', - 786432: 'PSP_BL__LOAD_DBGDRV', - 786432: 'PSP_BL__LOAD_HADDRV', - 851968: 'PSP_BL__LOAD_INTFDRV', - 917504: 'PSP_BL__LOAD_RASDRV', - 983040: 'PSP_BL__LOAD_IPKEYMGRDRV', - 1048576: 'PSP_BL__DRAM_LONG_TRAIN', - 2097152: 'PSP_BL__DRAM_SHORT_TRAIN', - 268435456: 'PSP_BL__LOAD_TOS_SPL_TABLE', -} -PSP_BL__LOAD_SYSDRV = 65536 -PSP_BL__LOAD_SOSDRV = 131072 -PSP_BL__LOAD_KEY_DATABASE = 524288 -PSP_BL__LOAD_SOCDRV = 720896 -PSP_BL__LOAD_DBGDRV = 786432 -PSP_BL__LOAD_HADDRV = 786432 -PSP_BL__LOAD_INTFDRV = 851968 -PSP_BL__LOAD_RASDRV = 917504 -PSP_BL__LOAD_IPKEYMGRDRV = 983040 -PSP_BL__DRAM_LONG_TRAIN = 1048576 -PSP_BL__DRAM_SHORT_TRAIN = 2097152 -PSP_BL__LOAD_TOS_SPL_TABLE = 268435456 -psp_bootloader_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'psp_ring_type' -psp_ring_type__enumvalues = { - 0: 'PSP_RING_TYPE__INVALID', - 1: 'PSP_RING_TYPE__UM', - 2: 'PSP_RING_TYPE__KM', -} -PSP_RING_TYPE__INVALID = 0 -PSP_RING_TYPE__UM = 1 -PSP_RING_TYPE__KM = 2 -psp_ring_type = ctypes.c_uint32 # enum - -# values for enumeration 'psp_reg_prog_id' -psp_reg_prog_id__enumvalues = { - 0: 'PSP_REG_IH_RB_CNTL', - 1: 'PSP_REG_IH_RB_CNTL_RING1', - 2: 'PSP_REG_IH_RB_CNTL_RING2', - 3: 'PSP_REG_LAST', -} -PSP_REG_IH_RB_CNTL = 0 -PSP_REG_IH_RB_CNTL_RING1 = 1 -PSP_REG_IH_RB_CNTL_RING2 = 2 -PSP_REG_LAST = 3 -psp_reg_prog_id = ctypes.c_uint32 # enum - -# values for enumeration 'psp_memory_training_init_flag' -psp_memory_training_init_flag__enumvalues = { - 0: 'PSP_MEM_TRAIN_NOT_SUPPORT', - 1: 'PSP_MEM_TRAIN_SUPPORT', - 2: 'PSP_MEM_TRAIN_INIT_FAILED', - 4: 'PSP_MEM_TRAIN_RESERVE_SUCCESS', - 8: 'PSP_MEM_TRAIN_INIT_SUCCESS', -} -PSP_MEM_TRAIN_NOT_SUPPORT = 0 -PSP_MEM_TRAIN_SUPPORT = 1 -PSP_MEM_TRAIN_INIT_FAILED = 2 -PSP_MEM_TRAIN_RESERVE_SUCCESS = 4 -PSP_MEM_TRAIN_INIT_SUCCESS = 8 -psp_memory_training_init_flag = ctypes.c_uint32 # enum - -# values for enumeration 'psp_memory_training_ops' -psp_memory_training_ops__enumvalues = { - 1: 'PSP_MEM_TRAIN_SEND_LONG_MSG', - 2: 'PSP_MEM_TRAIN_SAVE', - 4: 'PSP_MEM_TRAIN_RESTORE', - 8: 'PSP_MEM_TRAIN_SEND_SHORT_MSG', - 1: 'PSP_MEM_TRAIN_COLD_BOOT', - 8: 'PSP_MEM_TRAIN_RESUME', -} -PSP_MEM_TRAIN_SEND_LONG_MSG = 1 -PSP_MEM_TRAIN_SAVE = 2 -PSP_MEM_TRAIN_RESTORE = 4 -PSP_MEM_TRAIN_SEND_SHORT_MSG = 8 -PSP_MEM_TRAIN_COLD_BOOT = 1 -PSP_MEM_TRAIN_RESUME = 8 -psp_memory_training_ops = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_entry_type' -psp_runtime_entry_type__enumvalues = { - 0: 'PSP_RUNTIME_ENTRY_TYPE_INVALID', - 1: 'PSP_RUNTIME_ENTRY_TYPE_TEST', - 2: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', - 3: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', - 4: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', - 5: 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', - 6: 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', -} -PSP_RUNTIME_ENTRY_TYPE_INVALID = 0 -PSP_RUNTIME_ENTRY_TYPE_TEST = 1 -PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 2 -PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 3 -PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 4 -PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 5 -PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 6 -psp_runtime_entry_type = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_boot_cfg_feature' -psp_runtime_boot_cfg_feature__enumvalues = { - 1: 'BOOT_CFG_FEATURE_GECC', - 2: 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', -} -BOOT_CFG_FEATURE_GECC = 1 -BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 2 -psp_runtime_boot_cfg_feature = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_scpm_authentication' -psp_runtime_scpm_authentication__enumvalues = { - 0: 'SCPM_DISABLE', - 1: 'SCPM_ENABLE', - 2: 'SCPM_ENABLE_WITH_SCPM_ERR', -} -SCPM_DISABLE = 0 -SCPM_ENABLE = 1 -SCPM_ENABLE_WITH_SCPM_ERR = 2 -psp_runtime_scpm_authentication = ctypes.c_uint32 # enum -__AMDGPU_IRQ_H__ = True # macro -AMDGPU_MAX_IRQ_SRC_ID = 0x100 # macro -AMDGPU_MAX_IRQ_CLIENT_ID = 0x100 # macro -AMDGPU_IRQ_CLIENTID_LEGACY = 0 # macro -AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW = 4 # macro -class struct_amdgpu_device(Structure): - pass - - -# values for enumeration 'amdgpu_interrupt_state' -amdgpu_interrupt_state__enumvalues = { - 0: 'AMDGPU_IRQ_STATE_DISABLE', - 1: 'AMDGPU_IRQ_STATE_ENABLE', -} -AMDGPU_IRQ_STATE_DISABLE = 0 -AMDGPU_IRQ_STATE_ENABLE = 1 -amdgpu_interrupt_state = ctypes.c_uint32 # enum -class struct_amdgpu_iv_entry(Structure): - pass - -struct_amdgpu_iv_entry._pack_ = 1 # source:False -struct_amdgpu_iv_entry._fields_ = [ - ('client_id', ctypes.c_uint32), - ('src_id', ctypes.c_uint32), - ('ring_id', ctypes.c_uint32), - ('vmid', ctypes.c_uint32), - ('vmid_src', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timestamp', ctypes.c_uint64), - ('timestamp_src', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), - ('node_id', ctypes.c_uint32), - ('src_data', ctypes.c_uint32 * 4), - ('PADDING_1', ctypes.c_ubyte * 4), - ('iv_entry', ctypes.POINTER(ctypes.c_uint32)), -] - - -# values for enumeration 'interrupt_node_id_per_aid' -interrupt_node_id_per_aid__enumvalues = { - 0: 'AID0_NODEID', - 1: 'XCD0_NODEID', - 2: 'XCD1_NODEID', - 4: 'AID1_NODEID', - 5: 'XCD2_NODEID', - 6: 'XCD3_NODEID', - 8: 'AID2_NODEID', - 9: 'XCD4_NODEID', - 10: 'XCD5_NODEID', - 12: 'AID3_NODEID', - 13: 'XCD6_NODEID', - 14: 'XCD7_NODEID', - 15: 'NODEID_MAX', -} -AID0_NODEID = 0 -XCD0_NODEID = 1 -XCD1_NODEID = 2 -AID1_NODEID = 4 -XCD2_NODEID = 5 -XCD3_NODEID = 6 -AID2_NODEID = 8 -XCD4_NODEID = 9 -XCD5_NODEID = 10 -AID3_NODEID = 12 -XCD6_NODEID = 13 -XCD7_NODEID = 14 -NODEID_MAX = 15 -interrupt_node_id_per_aid = ctypes.c_uint32 # enum -AMDGPU_DOORBELL_H = True # macro - -# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT' -AMDGPU_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_DOORBELL_KIQ', - 1: 'AMDGPU_DOORBELL_HIQ', - 2: 'AMDGPU_DOORBELL_DIQ', - 16: 'AMDGPU_DOORBELL_MEC_RING0', - 17: 'AMDGPU_DOORBELL_MEC_RING1', - 18: 'AMDGPU_DOORBELL_MEC_RING2', - 19: 'AMDGPU_DOORBELL_MEC_RING3', - 20: 'AMDGPU_DOORBELL_MEC_RING4', - 21: 'AMDGPU_DOORBELL_MEC_RING5', - 22: 'AMDGPU_DOORBELL_MEC_RING6', - 23: 'AMDGPU_DOORBELL_MEC_RING7', - 32: 'AMDGPU_DOORBELL_GFX_RING0', - 480: 'AMDGPU_DOORBELL_sDMA_ENGINE0', - 481: 'AMDGPU_DOORBELL_sDMA_ENGINE1', - 488: 'AMDGPU_DOORBELL_IH', - 1023: 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL_INVALID', -} -AMDGPU_DOORBELL_KIQ = 0 -AMDGPU_DOORBELL_HIQ = 1 -AMDGPU_DOORBELL_DIQ = 2 -AMDGPU_DOORBELL_MEC_RING0 = 16 -AMDGPU_DOORBELL_MEC_RING1 = 17 -AMDGPU_DOORBELL_MEC_RING2 = 18 -AMDGPU_DOORBELL_MEC_RING3 = 19 -AMDGPU_DOORBELL_MEC_RING4 = 20 -AMDGPU_DOORBELL_MEC_RING5 = 21 -AMDGPU_DOORBELL_MEC_RING6 = 22 -AMDGPU_DOORBELL_MEC_RING7 = 23 -AMDGPU_DOORBELL_GFX_RING0 = 32 -AMDGPU_DOORBELL_sDMA_ENGINE0 = 480 -AMDGPU_DOORBELL_sDMA_ENGINE1 = 481 -AMDGPU_DOORBELL_IH = 488 -AMDGPU_DOORBELL_MAX_ASSIGNMENT = 1023 -AMDGPU_DOORBELL_INVALID = 65535 -AMDGPU_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT' -AMDGPU_VEGA20_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_VEGA20_DOORBELL_KIQ', - 1: 'AMDGPU_VEGA20_DOORBELL_HIQ', - 2: 'AMDGPU_VEGA20_DOORBELL_DIQ', - 3: 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', - 4: 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', - 5: 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', - 6: 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', - 7: 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', - 8: 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', - 9: 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', - 10: 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', - 11: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', - 138: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', - 139: 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', - 256: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', - 266: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', - 276: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', - 286: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', - 296: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', - 306: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', - 316: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', - 326: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', - 376: 'AMDGPU_VEGA20_DOORBELL_IH', - 392: 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', - 393: 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', - 394: 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', - 395: 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', - 396: 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', - 397: 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', - 398: 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', - 399: 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', - 392: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', - 393: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', - 394: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', - 395: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', - 396: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', - 397: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', - 398: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', - 399: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', - 256: 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', - 399: 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', - 400: 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', - 407: 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', - 464: 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', - 503: 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_VEGA20_DOORBELL_INVALID', -} -AMDGPU_VEGA20_DOORBELL_KIQ = 0 -AMDGPU_VEGA20_DOORBELL_HIQ = 1 -AMDGPU_VEGA20_DOORBELL_DIQ = 2 -AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 3 -AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 4 -AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 5 -AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 6 -AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 7 -AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 8 -AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 9 -AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 10 -AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 11 -AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 138 -AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 139 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 256 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 266 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 276 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 286 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 296 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 306 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 316 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 326 -AMDGPU_VEGA20_DOORBELL_IH = 376 -AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 392 -AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 393 -AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 394 -AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 395 -AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 396 -AMDGPU_VEGA20_DOORBELL64_VCNa_b = 397 -AMDGPU_VEGA20_DOORBELL64_VCNc_d = 398 -AMDGPU_VEGA20_DOORBELL64_VCNe_f = 399 -AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 392 -AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 393 -AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 394 -AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 395 -AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 396 -AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 397 -AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 398 -AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 399 -AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = 256 -AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = 399 -AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 400 -AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 407 -AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 464 -AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 503 -AMDGPU_VEGA20_DOORBELL_INVALID = 65535 -AMDGPU_VEGA20_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT' -AMDGPU_NAVI10_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_NAVI10_DOORBELL_KIQ', - 1: 'AMDGPU_NAVI10_DOORBELL_HIQ', - 2: 'AMDGPU_NAVI10_DOORBELL_DIQ', - 3: 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', - 4: 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', - 5: 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', - 6: 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', - 7: 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', - 8: 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', - 9: 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', - 10: 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', - 11: 'AMDGPU_NAVI10_DOORBELL_MES_RING0', - 12: 'AMDGPU_NAVI10_DOORBELL_MES_RING1', - 13: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', - 138: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', - 139: 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', - 140: 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', - 141: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', - 255: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', - 256: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', - 266: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', - 276: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', - 286: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', - 376: 'AMDGPU_NAVI10_DOORBELL_IH', - 392: 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', - 393: 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', - 394: 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', - 395: 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', - 396: 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', - 397: 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', - 398: 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', - 399: 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', - 400: 'AMDGPU_NAVI10_DOORBELL64_VPE', - 256: 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', - 400: 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', - 400: 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_NAVI10_DOORBELL_INVALID', -} -AMDGPU_NAVI10_DOORBELL_KIQ = 0 -AMDGPU_NAVI10_DOORBELL_HIQ = 1 -AMDGPU_NAVI10_DOORBELL_DIQ = 2 -AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 3 -AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 4 -AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 5 -AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 6 -AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 7 -AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 8 -AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 9 -AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 10 -AMDGPU_NAVI10_DOORBELL_MES_RING0 = 11 -AMDGPU_NAVI10_DOORBELL_MES_RING1 = 12 -AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 13 -AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 138 -AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 139 -AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 140 -AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 141 -AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 255 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 256 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 266 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 276 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 286 -AMDGPU_NAVI10_DOORBELL_IH = 376 -AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 392 -AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 393 -AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 394 -AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 395 -AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 396 -AMDGPU_NAVI10_DOORBELL64_VCNa_b = 397 -AMDGPU_NAVI10_DOORBELL64_VCNc_d = 398 -AMDGPU_NAVI10_DOORBELL64_VCNe_f = 399 -AMDGPU_NAVI10_DOORBELL64_VPE = 400 -AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = 256 -AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = 400 -AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 400 -AMDGPU_NAVI10_DOORBELL_INVALID = 65535 -AMDGPU_NAVI10_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'AMDGPU_DOORBELL64_ASSIGNMENT' -AMDGPU_DOORBELL64_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_DOORBELL64_KIQ', - 1: 'AMDGPU_DOORBELL64_HIQ', - 2: 'AMDGPU_DOORBELL64_DIQ', - 3: 'AMDGPU_DOORBELL64_MEC_RING0', - 4: 'AMDGPU_DOORBELL64_MEC_RING1', - 5: 'AMDGPU_DOORBELL64_MEC_RING2', - 6: 'AMDGPU_DOORBELL64_MEC_RING3', - 7: 'AMDGPU_DOORBELL64_MEC_RING4', - 8: 'AMDGPU_DOORBELL64_MEC_RING5', - 9: 'AMDGPU_DOORBELL64_MEC_RING6', - 10: 'AMDGPU_DOORBELL64_MEC_RING7', - 11: 'AMDGPU_DOORBELL64_USERQUEUE_START', - 138: 'AMDGPU_DOORBELL64_USERQUEUE_END', - 139: 'AMDGPU_DOORBELL64_GFX_RING0', - 240: 'AMDGPU_DOORBELL64_sDMA_ENGINE0', - 241: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', - 242: 'AMDGPU_DOORBELL64_sDMA_ENGINE1', - 243: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', - 244: 'AMDGPU_DOORBELL64_IH', - 245: 'AMDGPU_DOORBELL64_IH_RING1', - 246: 'AMDGPU_DOORBELL64_IH_RING2', - 248: 'AMDGPU_DOORBELL64_VCN0_1', - 249: 'AMDGPU_DOORBELL64_VCN2_3', - 250: 'AMDGPU_DOORBELL64_VCN4_5', - 251: 'AMDGPU_DOORBELL64_VCN6_7', - 248: 'AMDGPU_DOORBELL64_UVD_RING0_1', - 249: 'AMDGPU_DOORBELL64_UVD_RING2_3', - 250: 'AMDGPU_DOORBELL64_UVD_RING4_5', - 251: 'AMDGPU_DOORBELL64_UVD_RING6_7', - 252: 'AMDGPU_DOORBELL64_VCE_RING0_1', - 253: 'AMDGPU_DOORBELL64_VCE_RING2_3', - 254: 'AMDGPU_DOORBELL64_VCE_RING4_5', - 255: 'AMDGPU_DOORBELL64_VCE_RING6_7', - 240: 'AMDGPU_DOORBELL64_FIRST_NON_CP', - 255: 'AMDGPU_DOORBELL64_LAST_NON_CP', - 255: 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL64_INVALID', -} -AMDGPU_DOORBELL64_KIQ = 0 -AMDGPU_DOORBELL64_HIQ = 1 -AMDGPU_DOORBELL64_DIQ = 2 -AMDGPU_DOORBELL64_MEC_RING0 = 3 -AMDGPU_DOORBELL64_MEC_RING1 = 4 -AMDGPU_DOORBELL64_MEC_RING2 = 5 -AMDGPU_DOORBELL64_MEC_RING3 = 6 -AMDGPU_DOORBELL64_MEC_RING4 = 7 -AMDGPU_DOORBELL64_MEC_RING5 = 8 -AMDGPU_DOORBELL64_MEC_RING6 = 9 -AMDGPU_DOORBELL64_MEC_RING7 = 10 -AMDGPU_DOORBELL64_USERQUEUE_START = 11 -AMDGPU_DOORBELL64_USERQUEUE_END = 138 -AMDGPU_DOORBELL64_GFX_RING0 = 139 -AMDGPU_DOORBELL64_sDMA_ENGINE0 = 240 -AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 241 -AMDGPU_DOORBELL64_sDMA_ENGINE1 = 242 -AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 243 -AMDGPU_DOORBELL64_IH = 244 -AMDGPU_DOORBELL64_IH_RING1 = 245 -AMDGPU_DOORBELL64_IH_RING2 = 246 -AMDGPU_DOORBELL64_VCN0_1 = 248 -AMDGPU_DOORBELL64_VCN2_3 = 249 -AMDGPU_DOORBELL64_VCN4_5 = 250 -AMDGPU_DOORBELL64_VCN6_7 = 251 -AMDGPU_DOORBELL64_UVD_RING0_1 = 248 -AMDGPU_DOORBELL64_UVD_RING2_3 = 249 -AMDGPU_DOORBELL64_UVD_RING4_5 = 250 -AMDGPU_DOORBELL64_UVD_RING6_7 = 251 -AMDGPU_DOORBELL64_VCE_RING0_1 = 252 -AMDGPU_DOORBELL64_VCE_RING2_3 = 253 -AMDGPU_DOORBELL64_VCE_RING4_5 = 254 -AMDGPU_DOORBELL64_VCE_RING6_7 = 255 -AMDGPU_DOORBELL64_FIRST_NON_CP = 240 -AMDGPU_DOORBELL64_LAST_NON_CP = 255 -AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 255 -AMDGPU_DOORBELL64_INVALID = 65535 -AMDGPU_DOORBELL64_ASSIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1' -AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1__enumvalues = { - 0: 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', - 1: 'AMDGPU_DOORBELL_LAYOUT1_HIQ', - 2: 'AMDGPU_DOORBELL_LAYOUT1_DIQ', - 8: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', - 15: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', - 16: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', - 31: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', - 32: 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', - 256: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', - 415: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', - 416: 'AMDGPU_DOORBELL_LAYOUT1_IH', - 432: 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', - 488: 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', - 256: 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', - 488: 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', - 488: 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL_LAYOUT1_INVALID', -} -AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0 -AMDGPU_DOORBELL_LAYOUT1_HIQ = 1 -AMDGPU_DOORBELL_LAYOUT1_DIQ = 2 -AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 8 -AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 15 -AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 16 -AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 31 -AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 32 -AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 256 -AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 415 -AMDGPU_DOORBELL_LAYOUT1_IH = 416 -AMDGPU_DOORBELL_LAYOUT1_VCN_START = 432 -AMDGPU_DOORBELL_LAYOUT1_VCN_END = 488 -AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = 256 -AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = 488 -AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 488 -AMDGPU_DOORBELL_LAYOUT1_INVALID = 65535 -AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 = ctypes.c_uint32 # enum -__SOC15_IH_CLIENTID_H__ = True # macro - -# values for enumeration 'soc15_ih_clientid' -soc15_ih_clientid__enumvalues = { - 0: 'SOC15_IH_CLIENTID_IH', - 1: 'SOC15_IH_CLIENTID_ACP', - 2: 'SOC15_IH_CLIENTID_ATHUB', - 3: 'SOC15_IH_CLIENTID_BIF', - 4: 'SOC15_IH_CLIENTID_DCE', - 5: 'SOC15_IH_CLIENTID_ISP', - 6: 'SOC15_IH_CLIENTID_PCIE0', - 7: 'SOC15_IH_CLIENTID_RLC', - 8: 'SOC15_IH_CLIENTID_SDMA0', - 9: 'SOC15_IH_CLIENTID_SDMA1', - 10: 'SOC15_IH_CLIENTID_SE0SH', - 11: 'SOC15_IH_CLIENTID_SE1SH', - 12: 'SOC15_IH_CLIENTID_SE2SH', - 13: 'SOC15_IH_CLIENTID_SE3SH', - 14: 'SOC15_IH_CLIENTID_UVD1', - 15: 'SOC15_IH_CLIENTID_THM', - 16: 'SOC15_IH_CLIENTID_UVD', - 17: 'SOC15_IH_CLIENTID_VCE0', - 18: 'SOC15_IH_CLIENTID_VMC', - 19: 'SOC15_IH_CLIENTID_XDMA', - 20: 'SOC15_IH_CLIENTID_GRBM_CP', - 21: 'SOC15_IH_CLIENTID_ATS', - 22: 'SOC15_IH_CLIENTID_ROM_SMUIO', - 23: 'SOC15_IH_CLIENTID_DF', - 24: 'SOC15_IH_CLIENTID_VCE1', - 25: 'SOC15_IH_CLIENTID_PWR', - 26: 'SOC15_IH_CLIENTID_RESERVED', - 27: 'SOC15_IH_CLIENTID_UTCL2', - 28: 'SOC15_IH_CLIENTID_EA', - 29: 'SOC15_IH_CLIENTID_UTCL2LOG', - 30: 'SOC15_IH_CLIENTID_MP0', - 31: 'SOC15_IH_CLIENTID_MP1', - 32: 'SOC15_IH_CLIENTID_MAX', - 16: 'SOC15_IH_CLIENTID_VCN', - 14: 'SOC15_IH_CLIENTID_VCN1', - 1: 'SOC15_IH_CLIENTID_SDMA2', - 4: 'SOC15_IH_CLIENTID_SDMA3', - 5: 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', - 5: 'SOC15_IH_CLIENTID_SDMA4', - 17: 'SOC15_IH_CLIENTID_SDMA5', - 19: 'SOC15_IH_CLIENTID_SDMA6', - 24: 'SOC15_IH_CLIENTID_SDMA7', - 6: 'SOC15_IH_CLIENTID_VMC1', -} -SOC15_IH_CLIENTID_IH = 0 -SOC15_IH_CLIENTID_ACP = 1 -SOC15_IH_CLIENTID_ATHUB = 2 -SOC15_IH_CLIENTID_BIF = 3 -SOC15_IH_CLIENTID_DCE = 4 -SOC15_IH_CLIENTID_ISP = 5 -SOC15_IH_CLIENTID_PCIE0 = 6 -SOC15_IH_CLIENTID_RLC = 7 -SOC15_IH_CLIENTID_SDMA0 = 8 -SOC15_IH_CLIENTID_SDMA1 = 9 -SOC15_IH_CLIENTID_SE0SH = 10 -SOC15_IH_CLIENTID_SE1SH = 11 -SOC15_IH_CLIENTID_SE2SH = 12 -SOC15_IH_CLIENTID_SE3SH = 13 -SOC15_IH_CLIENTID_UVD1 = 14 -SOC15_IH_CLIENTID_THM = 15 -SOC15_IH_CLIENTID_UVD = 16 -SOC15_IH_CLIENTID_VCE0 = 17 -SOC15_IH_CLIENTID_VMC = 18 -SOC15_IH_CLIENTID_XDMA = 19 -SOC15_IH_CLIENTID_GRBM_CP = 20 -SOC15_IH_CLIENTID_ATS = 21 -SOC15_IH_CLIENTID_ROM_SMUIO = 22 -SOC15_IH_CLIENTID_DF = 23 -SOC15_IH_CLIENTID_VCE1 = 24 -SOC15_IH_CLIENTID_PWR = 25 -SOC15_IH_CLIENTID_RESERVED = 26 -SOC15_IH_CLIENTID_UTCL2 = 27 -SOC15_IH_CLIENTID_EA = 28 -SOC15_IH_CLIENTID_UTCL2LOG = 29 -SOC15_IH_CLIENTID_MP0 = 30 -SOC15_IH_CLIENTID_MP1 = 31 -SOC15_IH_CLIENTID_MAX = 32 -SOC15_IH_CLIENTID_VCN = 16 -SOC15_IH_CLIENTID_VCN1 = 14 -SOC15_IH_CLIENTID_SDMA2 = 1 -SOC15_IH_CLIENTID_SDMA3 = 4 -SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = 5 -SOC15_IH_CLIENTID_SDMA4 = 5 -SOC15_IH_CLIENTID_SDMA5 = 17 -SOC15_IH_CLIENTID_SDMA6 = 19 -SOC15_IH_CLIENTID_SDMA7 = 24 -SOC15_IH_CLIENTID_VMC1 = 6 -soc15_ih_clientid = ctypes.c_uint32 # enum -AMDGPU_IRQ_CLIENTID_MAX = SOC15_IH_CLIENTID_MAX # macro -soc15_ih_clientid_name = [] # Variable ctypes.POINTER(ctypes.c_char) * 0 - -# values for enumeration 'soc21_ih_clientid' -soc21_ih_clientid__enumvalues = { - 0: 'SOC21_IH_CLIENTID_IH', - 2: 'SOC21_IH_CLIENTID_ATHUB', - 3: 'SOC21_IH_CLIENTID_BIF', - 4: 'SOC21_IH_CLIENTID_DCN', - 5: 'SOC21_IH_CLIENTID_ISP', - 6: 'SOC21_IH_CLIENTID_MP3', - 7: 'SOC21_IH_CLIENTID_RLC', - 10: 'SOC21_IH_CLIENTID_GFX', - 11: 'SOC21_IH_CLIENTID_IMU', - 14: 'SOC21_IH_CLIENTID_VCN1', - 15: 'SOC21_IH_CLIENTID_THM', - 16: 'SOC21_IH_CLIENTID_VCN', - 17: 'SOC21_IH_CLIENTID_VPE1', - 18: 'SOC21_IH_CLIENTID_VMC', - 20: 'SOC21_IH_CLIENTID_GRBM_CP', - 22: 'SOC21_IH_CLIENTID_ROM_SMUIO', - 23: 'SOC21_IH_CLIENTID_DF', - 24: 'SOC21_IH_CLIENTID_VPE', - 25: 'SOC21_IH_CLIENTID_PWR', - 26: 'SOC21_IH_CLIENTID_LSDMA', - 30: 'SOC21_IH_CLIENTID_MP0', - 31: 'SOC21_IH_CLIENTID_MP1', - 32: 'SOC21_IH_CLIENTID_MAX', -} -SOC21_IH_CLIENTID_IH = 0 -SOC21_IH_CLIENTID_ATHUB = 2 -SOC21_IH_CLIENTID_BIF = 3 -SOC21_IH_CLIENTID_DCN = 4 -SOC21_IH_CLIENTID_ISP = 5 -SOC21_IH_CLIENTID_MP3 = 6 -SOC21_IH_CLIENTID_RLC = 7 -SOC21_IH_CLIENTID_GFX = 10 -SOC21_IH_CLIENTID_IMU = 11 -SOC21_IH_CLIENTID_VCN1 = 14 -SOC21_IH_CLIENTID_THM = 15 -SOC21_IH_CLIENTID_VCN = 16 -SOC21_IH_CLIENTID_VPE1 = 17 -SOC21_IH_CLIENTID_VMC = 18 -SOC21_IH_CLIENTID_GRBM_CP = 20 -SOC21_IH_CLIENTID_ROM_SMUIO = 22 -SOC21_IH_CLIENTID_DF = 23 -SOC21_IH_CLIENTID_VPE = 24 -SOC21_IH_CLIENTID_PWR = 25 -SOC21_IH_CLIENTID_LSDMA = 26 -SOC21_IH_CLIENTID_MP0 = 30 -SOC21_IH_CLIENTID_MP1 = 31 -SOC21_IH_CLIENTID_MAX = 32 -soc21_ih_clientid = ctypes.c_uint32 # enum -__all__ = \ - ['ACP_HWID', 'AID0_NODEID', 'AID1_NODEID', 'AID2_NODEID', - 'AID3_NODEID', 'AMDGPU_CPCE_UCODE_LOADED', - 'AMDGPU_CPMEC1_UCODE_LOADED', 'AMDGPU_CPMEC2_UCODE_LOADED', - 'AMDGPU_CPME_UCODE_LOADED', 'AMDGPU_CPPFP_UCODE_LOADED', - 'AMDGPU_CPRLC_UCODE_LOADED', 'AMDGPU_DOORBELL64_ASSIGNMENT', - 'AMDGPU_DOORBELL64_DIQ', 'AMDGPU_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_DOORBELL64_GFX_RING0', 'AMDGPU_DOORBELL64_HIQ', - 'AMDGPU_DOORBELL64_IH', 'AMDGPU_DOORBELL64_IH_RING1', - 'AMDGPU_DOORBELL64_IH_RING2', 'AMDGPU_DOORBELL64_INVALID', - 'AMDGPU_DOORBELL64_KIQ', 'AMDGPU_DOORBELL64_LAST_NON_CP', - 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL64_MEC_RING0', - 'AMDGPU_DOORBELL64_MEC_RING1', 'AMDGPU_DOORBELL64_MEC_RING2', - 'AMDGPU_DOORBELL64_MEC_RING3', 'AMDGPU_DOORBELL64_MEC_RING4', - 'AMDGPU_DOORBELL64_MEC_RING5', 'AMDGPU_DOORBELL64_MEC_RING6', - 'AMDGPU_DOORBELL64_MEC_RING7', 'AMDGPU_DOORBELL64_USERQUEUE_END', - 'AMDGPU_DOORBELL64_USERQUEUE_START', - 'AMDGPU_DOORBELL64_UVD_RING0_1', 'AMDGPU_DOORBELL64_UVD_RING2_3', - 'AMDGPU_DOORBELL64_UVD_RING4_5', 'AMDGPU_DOORBELL64_UVD_RING6_7', - 'AMDGPU_DOORBELL64_VCE_RING0_1', 'AMDGPU_DOORBELL64_VCE_RING2_3', - 'AMDGPU_DOORBELL64_VCE_RING4_5', 'AMDGPU_DOORBELL64_VCE_RING6_7', - 'AMDGPU_DOORBELL64_VCN0_1', 'AMDGPU_DOORBELL64_VCN2_3', - 'AMDGPU_DOORBELL64_VCN4_5', 'AMDGPU_DOORBELL64_VCN6_7', - 'AMDGPU_DOORBELL64_sDMA_ENGINE0', - 'AMDGPU_DOORBELL64_sDMA_ENGINE1', - 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', - 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', - 'AMDGPU_DOORBELL_ASSIGNMENT', - 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1', 'AMDGPU_DOORBELL_DIQ', - 'AMDGPU_DOORBELL_GFX_RING0', 'AMDGPU_DOORBELL_H', - 'AMDGPU_DOORBELL_HIQ', 'AMDGPU_DOORBELL_IH', - 'AMDGPU_DOORBELL_INVALID', 'AMDGPU_DOORBELL_KIQ', - 'AMDGPU_DOORBELL_LAYOUT1_DIQ', - 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', - 'AMDGPU_DOORBELL_LAYOUT1_HIQ', 'AMDGPU_DOORBELL_LAYOUT1_IH', - 'AMDGPU_DOORBELL_LAYOUT1_INVALID', - 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', - 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', - 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', - 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', - 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', - 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', - 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', - 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', - 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', - 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', - 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', - 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', - 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL_MEC_RING0', - 'AMDGPU_DOORBELL_MEC_RING1', 'AMDGPU_DOORBELL_MEC_RING2', - 'AMDGPU_DOORBELL_MEC_RING3', 'AMDGPU_DOORBELL_MEC_RING4', - 'AMDGPU_DOORBELL_MEC_RING5', 'AMDGPU_DOORBELL_MEC_RING6', - 'AMDGPU_DOORBELL_MEC_RING7', 'AMDGPU_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_DOORBELL_sDMA_ENGINE1', 'AMDGPU_FW_LOAD_DIRECT', - 'AMDGPU_FW_LOAD_PSP', 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', - 'AMDGPU_FW_LOAD_SMU', 'AMDGPU_GFXHUB_START', - 'AMDGPU_IRQ_CLIENTID_LEGACY', 'AMDGPU_IRQ_CLIENTID_MAX', - 'AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW', 'AMDGPU_IRQ_STATE_DISABLE', - 'AMDGPU_IRQ_STATE_ENABLE', 'AMDGPU_MAX_IRQ_CLIENT_ID', - 'AMDGPU_MAX_IRQ_SRC_ID', 'AMDGPU_MAX_VMHUBS', - 'AMDGPU_MMHUB0_START', 'AMDGPU_MMHUB1_START', 'AMDGPU_MTYPE_CC', - 'AMDGPU_MTYPE_NC', 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', - 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', - 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', - 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', - 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', - 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', - 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', - 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', - 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', 'AMDGPU_NAVI10_DOORBELL64_VPE', - 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT', 'AMDGPU_NAVI10_DOORBELL_DIQ', - 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', - 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', - 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', - 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', - 'AMDGPU_NAVI10_DOORBELL_HIQ', 'AMDGPU_NAVI10_DOORBELL_IH', - 'AMDGPU_NAVI10_DOORBELL_INVALID', 'AMDGPU_NAVI10_DOORBELL_KIQ', - 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', - 'AMDGPU_NAVI10_DOORBELL_MES_RING0', - 'AMDGPU_NAVI10_DOORBELL_MES_RING1', - 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', - 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', 'AMDGPU_PDE_PTE', - 'AMDGPU_PDE_PTE_GFX12', 'AMDGPU_PTE_DEFAULT_ATC', - 'AMDGPU_PTE_EXECUTABLE', 'AMDGPU_PTE_IS_PTE', 'AMDGPU_PTE_LOG', - 'AMDGPU_PTE_MTYPE_GFX12_MASK', 'AMDGPU_PTE_MTYPE_NV10_MASK', - 'AMDGPU_PTE_MTYPE_VG10_MASK', 'AMDGPU_PTE_NOALLOC', - 'AMDGPU_PTE_PRT', 'AMDGPU_PTE_PRT_GFX12', 'AMDGPU_PTE_READABLE', - 'AMDGPU_PTE_SNOOPED', 'AMDGPU_PTE_SYSTEM', 'AMDGPU_PTE_TF', - 'AMDGPU_PTE_TMZ', 'AMDGPU_PTE_VALID', 'AMDGPU_PTE_WRITEABLE', - 'AMDGPU_SDMA0_UCODE_LOADED', 'AMDGPU_SDMA1_UCODE_LOADED', - 'AMDGPU_UCODE_ID', 'AMDGPU_UCODE_ID_CAP', 'AMDGPU_UCODE_ID_CP_CE', - 'AMDGPU_UCODE_ID_CP_ME', 'AMDGPU_UCODE_ID_CP_MEC1', - 'AMDGPU_UCODE_ID_CP_MEC1_JT', 'AMDGPU_UCODE_ID_CP_MEC2', - 'AMDGPU_UCODE_ID_CP_MEC2_JT', 'AMDGPU_UCODE_ID_CP_MES', - 'AMDGPU_UCODE_ID_CP_MES1', 'AMDGPU_UCODE_ID_CP_MES1_DATA', - 'AMDGPU_UCODE_ID_CP_MES_DATA', 'AMDGPU_UCODE_ID_CP_PFP', - 'AMDGPU_UCODE_ID_CP_RS64_ME', 'AMDGPU_UCODE_ID_CP_RS64_MEC', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_PFP', - 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', 'AMDGPU_UCODE_ID_DMCUB', - 'AMDGPU_UCODE_ID_DMCU_ERAM', 'AMDGPU_UCODE_ID_DMCU_INTV', - 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', 'AMDGPU_UCODE_ID_IMU_D', - 'AMDGPU_UCODE_ID_IMU_I', 'AMDGPU_UCODE_ID_ISP', - 'AMDGPU_UCODE_ID_JPEG_RAM', 'AMDGPU_UCODE_ID_MAXIMUM', - 'AMDGPU_UCODE_ID_P2S_TABLE', 'AMDGPU_UCODE_ID_PPTABLE', - 'AMDGPU_UCODE_ID_RLC_DRAM', 'AMDGPU_UCODE_ID_RLC_G', - 'AMDGPU_UCODE_ID_RLC_IRAM', 'AMDGPU_UCODE_ID_RLC_P', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', - 'AMDGPU_UCODE_ID_RLC_V', 'AMDGPU_UCODE_ID_SDMA0', - 'AMDGPU_UCODE_ID_SDMA1', 'AMDGPU_UCODE_ID_SDMA2', - 'AMDGPU_UCODE_ID_SDMA3', 'AMDGPU_UCODE_ID_SDMA4', - 'AMDGPU_UCODE_ID_SDMA5', 'AMDGPU_UCODE_ID_SDMA6', - 'AMDGPU_UCODE_ID_SDMA7', 'AMDGPU_UCODE_ID_SDMA_RS64', - 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', - 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', - 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', 'AMDGPU_UCODE_ID_SMC', - 'AMDGPU_UCODE_ID_STORAGE', 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', - 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', - 'AMDGPU_UCODE_ID_UVD', 'AMDGPU_UCODE_ID_UVD1', - 'AMDGPU_UCODE_ID_VCE', 'AMDGPU_UCODE_ID_VCN', - 'AMDGPU_UCODE_ID_VCN0_RAM', 'AMDGPU_UCODE_ID_VCN1', - 'AMDGPU_UCODE_ID_VCN1_RAM', 'AMDGPU_UCODE_ID_VPE', - 'AMDGPU_UCODE_ID_VPE_CTL', 'AMDGPU_UCODE_ID_VPE_CTX', - 'AMDGPU_UCODE_STATUS', 'AMDGPU_UCODE_STATUS_INVALID', - 'AMDGPU_UCODE_STATUS_LOADED', 'AMDGPU_UCODE_STATUS_NOT_LOADED', - 'AMDGPU_VA_RESERVED_BOTTOM', 'AMDGPU_VA_RESERVED_CSA_SIZE', - 'AMDGPU_VA_RESERVED_SEQ64_SIZE', 'AMDGPU_VA_RESERVED_TOP', - 'AMDGPU_VA_RESERVED_TRAP_SIZE', - 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', - 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', - 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', - 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', - 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', - 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', - 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', - 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', - 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT', 'AMDGPU_VEGA20_DOORBELL_DIQ', - 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', 'AMDGPU_VEGA20_DOORBELL_HIQ', - 'AMDGPU_VEGA20_DOORBELL_IH', 'AMDGPU_VEGA20_DOORBELL_INVALID', - 'AMDGPU_VEGA20_DOORBELL_KIQ', - 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', - 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', - 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', - 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', - 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', - 'AMDGPU_VM_FAULT_STOP_ALWAYS', 'AMDGPU_VM_FAULT_STOP_FIRST', - 'AMDGPU_VM_FAULT_STOP_NEVER', 'AMDGPU_VM_MAX_UPDATE_SIZE', - 'AMDGPU_VM_NORETRY_FLAGS', 'AMDGPU_VM_NORETRY_FLAGS_TF', - 'AMDGPU_VM_PDB0', 'AMDGPU_VM_PDB1', 'AMDGPU_VM_PDB2', - 'AMDGPU_VM_PTB', 'AMDGPU_VM_RESERVED_VRAM', - 'AMDGPU_VM_USE_CPU_FOR_COMPUTE', 'AMDGPU_VM_USE_CPU_FOR_GFX', - 'AMDGPU_XGMI_MAX_CONNECTED_NODES', 'ATHUB_HWID', 'ATHUB_HWIP', - 'AUDIO_AZ_HWID', 'BINARY_SIGNATURE', - 'BIST_MEM_TRAINING_ENCROACHED_SIZE', 'BOOTCFG_CMD_GET', - 'BOOTCFG_CMD_INVALIDATE', 'BOOTCFG_CMD_SET', - 'BOOT_CFG_FEATURE_GECC', - 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', 'BOOT_CONFIG_GECC', - 'C2PMSG_CMD_GFX_USB_PD_FW_VER', 'CCXSEC_HWID', 'CLKA_HWID', - 'CLKB_HWID', 'CLK_HWIP', 'DAZ_HWID', 'DBGU0_HWID', 'DBGU1_HWID', - 'DBGU_IO_HWID', 'DBGU_NBIO_HWID', 'DCEAZ_HWID', 'DCE_HWIP', - 'DCI_HWID', 'DCI_HWIP', 'DCO_HWID', 'DDCL_HWID', 'DFX_DAP_HWID', - 'DFX_HWID', 'DF_HWID', 'DF_HWIP', 'DIO_HWID', - 'DISCOVERY_TABLE_SIGNATURE', 'DMU_HWID', 'FCH_HWID', - 'FCH_USB_PD_HWID', 'FRAME_TYPE_DESTROY', 'FUSE_HWID', 'GC', - 'GC_HWID', 'GC_HWIP', 'GC_TABLE_ID', - 'GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES', - 'GDDR6_MEM_TRAINING_OFFSET', 'GFX_BUF_MAX_DESC', - 'GFX_CMD_ID_AUTOLOAD_RLC', 'GFX_CMD_ID_BOOT_CFG', - 'GFX_CMD_ID_DESTROY_TMR', 'GFX_CMD_ID_DESTROY_VMR', - 'GFX_CMD_ID_GET_FW_ATTESTATION', 'GFX_CMD_ID_INVOKE_CMD', - 'GFX_CMD_ID_LOAD_ASD', 'GFX_CMD_ID_LOAD_IP_FW', - 'GFX_CMD_ID_LOAD_TA', 'GFX_CMD_ID_LOAD_TOC', 'GFX_CMD_ID_MASK', - 'GFX_CMD_ID_PROG_REG', 'GFX_CMD_ID_SAVE_RESTORE', - 'GFX_CMD_ID_SETUP_TMR', 'GFX_CMD_ID_SETUP_VMR', - 'GFX_CMD_ID_SRIOV_SPATIAL_PART', 'GFX_CMD_ID_UNLOAD_TA', - 'GFX_CMD_RESERVED_MASK', 'GFX_CMD_RESPONSE_MASK', - 'GFX_CMD_STATUS_MASK', 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', - 'GFX_CTRL_CMD_ID_CONSUME_CMD', - 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', - 'GFX_CTRL_CMD_ID_DESTROY_RINGS', 'GFX_CTRL_CMD_ID_DISABLE_INT', - 'GFX_CTRL_CMD_ID_ENABLE_INT', 'GFX_CTRL_CMD_ID_GBR_IH_SET', - 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', - 'GFX_CTRL_CMD_ID_INIT_RBI_RING', 'GFX_CTRL_CMD_ID_MAX', - 'GFX_CTRL_CMD_ID_MODE1_RST', 'GFX_FLAG_RESPONSE', - 'GFX_FW_TYPE_ACCUM_CTRL_RAM', 'GFX_FW_TYPE_ACP', - 'GFX_FW_TYPE_CAP', 'GFX_FW_TYPE_CP_CE', 'GFX_FW_TYPE_CP_ME', - 'GFX_FW_TYPE_CP_MEC', 'GFX_FW_TYPE_CP_MEC_ME1', - 'GFX_FW_TYPE_CP_MEC_ME2', 'GFX_FW_TYPE_CP_MES', - 'GFX_FW_TYPE_CP_MES_KIQ', 'GFX_FW_TYPE_CP_PFP', - 'GFX_FW_TYPE_DISCRETE_USB4', 'GFX_FW_TYPE_DMCU_ERAM', - 'GFX_FW_TYPE_DMCU_ISR', 'GFX_FW_TYPE_DMUB', - 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', - 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', - 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', 'GFX_FW_TYPE_IMU_D', - 'GFX_FW_TYPE_IMU_I', 'GFX_FW_TYPE_ISP', 'GFX_FW_TYPE_ISP_DATA', - 'GFX_FW_TYPE_JPEG_RAM', 'GFX_FW_TYPE_LSDMA', 'GFX_FW_TYPE_MAX', - 'GFX_FW_TYPE_MES_KIQ_STACK', 'GFX_FW_TYPE_MES_STACK', - 'GFX_FW_TYPE_MMSCH', 'GFX_FW_TYPE_NONE', 'GFX_FW_TYPE_P2S_TABLE', - 'GFX_FW_TYPE_PPTABLE', 'GFX_FW_TYPE_REG_LIST', - 'GFX_FW_TYPE_RLCG_SCRATCH_SR', 'GFX_FW_TYPE_RLCP_CAM', - 'GFX_FW_TYPE_RLCP_SCRATCH_SR', 'GFX_FW_TYPE_RLCV_SCRATCH_SR', - 'GFX_FW_TYPE_RLC_DRAM_BOOT', 'GFX_FW_TYPE_RLC_G', - 'GFX_FW_TYPE_RLC_IRAM', 'GFX_FW_TYPE_RLC_P', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', - 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', - 'GFX_FW_TYPE_RLC_V', 'GFX_FW_TYPE_RLX6_DRAM_SR', - 'GFX_FW_TYPE_RS64_KIQ', 'GFX_FW_TYPE_RS64_KIQ_STACK', - 'GFX_FW_TYPE_RS64_ME', 'GFX_FW_TYPE_RS64_MEC', - 'GFX_FW_TYPE_RS64_MEC_P0_STACK', 'GFX_FW_TYPE_RS64_MEC_P1_STACK', - 'GFX_FW_TYPE_RS64_MEC_P2_STACK', 'GFX_FW_TYPE_RS64_MEC_P3_STACK', - 'GFX_FW_TYPE_RS64_MES', 'GFX_FW_TYPE_RS64_MES_STACK', - 'GFX_FW_TYPE_RS64_ME_P0_STACK', 'GFX_FW_TYPE_RS64_ME_P1_STACK', - 'GFX_FW_TYPE_RS64_PFP', 'GFX_FW_TYPE_RS64_PFP_P0_STACK', - 'GFX_FW_TYPE_RS64_PFP_P1_STACK', 'GFX_FW_TYPE_SDMA0', - 'GFX_FW_TYPE_SDMA0_JT', 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', - 'GFX_FW_TYPE_SDMA1', 'GFX_FW_TYPE_SDMA1_JT', - 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', 'GFX_FW_TYPE_SDMA2', - 'GFX_FW_TYPE_SDMA3', 'GFX_FW_TYPE_SDMA4', 'GFX_FW_TYPE_SDMA5', - 'GFX_FW_TYPE_SDMA6', 'GFX_FW_TYPE_SDMA7', - 'GFX_FW_TYPE_SDMA_UCODE_TH0', 'GFX_FW_TYPE_SDMA_UCODE_TH1', - 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE0_TAP_DELAYS', - 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE1_TAP_DELAYS', - 'GFX_FW_TYPE_SE2_TAP_DELAYS', 'GFX_FW_TYPE_SE3_TAP_DELAYS', - 'GFX_FW_TYPE_SMU', 'GFX_FW_TYPE_TA', 'GFX_FW_TYPE_TOC', - 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', 'GFX_FW_TYPE_UMSCH_DATA', - 'GFX_FW_TYPE_UMSCH_UCODE', 'GFX_FW_TYPE_USB_DP_COMBO_PHY', - 'GFX_FW_TYPE_UVD', 'GFX_FW_TYPE_UVD1', 'GFX_FW_TYPE_VCE', - 'GFX_FW_TYPE_VCN', 'GFX_FW_TYPE_VCN0_RAM', 'GFX_FW_TYPE_VCN1', - 'GFX_FW_TYPE_VCN1_RAM', 'GFX_FW_TYPE_VPE', 'GFX_FW_TYPE_VPEC_FW1', - 'GFX_FW_TYPE_VPEC_FW2', 'HARVEST_INFO', 'HARVEST_TABLE_SIGNATURE', - 'HDP_HWID', 'HDP_HWIP', 'HWIP_MAX_INSTANCE', 'HW_ID_MAX', - 'IOAGR_HWID', 'IOAPIC_HWID', 'IOHC_HWID', 'IP_DISCOVERY', - 'ISP_HWID', 'ISP_HWIP', 'JPEG_HWIP', 'L1IMU10_HWID', - 'L1IMU11_HWID', 'L1IMU12_HWID', 'L1IMU13_HWID', 'L1IMU14_HWID', - 'L1IMU15_HWID', 'L1IMU3_HWID', 'L1IMU4_HWID', 'L1IMU5_HWID', - 'L1IMU6_HWID', 'L1IMU7_HWID', 'L1IMU8_HWID', 'L1IMU9_HWID', - 'L1IMU_IOAGR_HWID', 'L1IMU_NBIF_HWID', 'L1IMU_PCIE_HWID', - 'L2IMU_HWID', 'LSDMA_HWID', 'LSDMA_HWIP', 'MALL_INFO', - 'MALL_INFO_TABLE_ID', 'MAX_HWIP', 'MEM_TRAIN_SYSTEM_SIGNATURE', - 'MMHUB_HWID', 'MMHUB_HWIP', 'MP0_HWID', 'MP0_HWIP', 'MP1_HWID', - 'MP1_HWIP', 'MP2_HWID', 'NBIF_HWID', 'NBIF_HWIP', 'NBIO_HWIP', - 'NODEID_MAX', 'NPS_INFO', 'NPS_INFO_TABLE_ID', - 'NPS_INFO_TABLE_MAX_NUM_INSTANCES', 'NTBCCP_HWID', 'NTB_HWID', - 'OSSSYS_HWID', 'OSSSYS_HWIP', 'PCIE_HWID', 'PCIE_HWIP', - 'PCS_HWID', 'PSP_1_MEG', 'PSP_ASD_SHARED_MEM_SIZE', - 'PSP_BL__DRAM_LONG_TRAIN', 'PSP_BL__DRAM_SHORT_TRAIN', - 'PSP_BL__LOAD_DBGDRV', 'PSP_BL__LOAD_HADDRV', - 'PSP_BL__LOAD_INTFDRV', 'PSP_BL__LOAD_IPKEYMGRDRV', - 'PSP_BL__LOAD_KEY_DATABASE', 'PSP_BL__LOAD_RASDRV', - 'PSP_BL__LOAD_SOCDRV', 'PSP_BL__LOAD_SOSDRV', - 'PSP_BL__LOAD_SYSDRV', 'PSP_BL__LOAD_TOS_SPL_TABLE', - 'PSP_CMD_BUFFER_SIZE', 'PSP_DTM_SHARED_MEM_SIZE', - 'PSP_ERR_UNKNOWN_COMMAND', 'PSP_FENCE_BUFFER_SIZE', - 'PSP_FW_NAME_LEN', 'PSP_FW_TYPE_MAX_INDEX', - 'PSP_FW_TYPE_PSP_DBG_DRV', 'PSP_FW_TYPE_PSP_INTF_DRV', - 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', 'PSP_FW_TYPE_PSP_KDB', - 'PSP_FW_TYPE_PSP_RAS_DRV', 'PSP_FW_TYPE_PSP_RL', - 'PSP_FW_TYPE_PSP_SOC_DRV', 'PSP_FW_TYPE_PSP_SOS', - 'PSP_FW_TYPE_PSP_SPL', 'PSP_FW_TYPE_PSP_SYS_DRV', - 'PSP_FW_TYPE_PSP_TOC', 'PSP_FW_TYPE_UNKOWN', - 'PSP_GFX_CMD_BUF_VERSION', 'PSP_HDCP_SHARED_MEM_SIZE', - 'PSP_HEADER_SIZE', 'PSP_MEM_TRAIN_COLD_BOOT', - 'PSP_MEM_TRAIN_INIT_FAILED', 'PSP_MEM_TRAIN_INIT_SUCCESS', - 'PSP_MEM_TRAIN_NOT_SUPPORT', 'PSP_MEM_TRAIN_RESERVE_SUCCESS', - 'PSP_MEM_TRAIN_RESTORE', 'PSP_MEM_TRAIN_RESUME', - 'PSP_MEM_TRAIN_SAVE', 'PSP_MEM_TRAIN_SEND_LONG_MSG', - 'PSP_MEM_TRAIN_SEND_SHORT_MSG', 'PSP_MEM_TRAIN_SUPPORT', - 'PSP_RAP_SHARED_MEM_SIZE', 'PSP_RAS_SHARED_MEM_SIZE', - 'PSP_REG_IH_RB_CNTL', 'PSP_REG_IH_RB_CNTL_RING1', - 'PSP_REG_IH_RB_CNTL_RING2', 'PSP_REG_LAST', - 'PSP_RING_TYPE__INVALID', 'PSP_RING_TYPE__KM', - 'PSP_RING_TYPE__UM', 'PSP_RUNTIME_DB_COOKIE_ID', - 'PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT', 'PSP_RUNTIME_DB_OFFSET', - 'PSP_RUNTIME_DB_SIZE_IN_BYTES', 'PSP_RUNTIME_DB_VER_1', - 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', - 'PSP_RUNTIME_ENTRY_TYPE_INVALID', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', - 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', - 'PSP_RUNTIME_ENTRY_TYPE_TEST', - 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', 'PSP_TMR_ALIGNMENT', - 'PSP_XGMI_SHARED_MEM_SIZE', 'PWR_HWID', 'PWR_HWIP', 'RSMU_HWIP', - 'SATA_HWID', 'SCPM_DISABLE', 'SCPM_ENABLE', - 'SCPM_ENABLE_WITH_SCPM_ERR', 'SDMA0_HWID', 'SDMA0_HWIP', - 'SDMA1_HWID', 'SDMA1_HWIP', 'SDMA2_HWID', 'SDMA2_HWIP', - 'SDMA3_HWID', 'SDMA3_HWIP', 'SDMA4_HWIP', 'SDMA5_HWIP', - 'SDMA6_HWIP', 'SDMA7_HWIP', 'SDPMUX_HWID', 'SMUIO_HWID', - 'SMUIO_HWIP', 'SOC15_IH_CLIENTID_ACP', 'SOC15_IH_CLIENTID_ATHUB', - 'SOC15_IH_CLIENTID_ATS', 'SOC15_IH_CLIENTID_BIF', - 'SOC15_IH_CLIENTID_DCE', 'SOC15_IH_CLIENTID_DF', - 'SOC15_IH_CLIENTID_EA', 'SOC15_IH_CLIENTID_GRBM_CP', - 'SOC15_IH_CLIENTID_IH', 'SOC15_IH_CLIENTID_ISP', - 'SOC15_IH_CLIENTID_MAX', 'SOC15_IH_CLIENTID_MP0', - 'SOC15_IH_CLIENTID_MP1', 'SOC15_IH_CLIENTID_PCIE0', - 'SOC15_IH_CLIENTID_PWR', 'SOC15_IH_CLIENTID_RESERVED', - 'SOC15_IH_CLIENTID_RLC', 'SOC15_IH_CLIENTID_ROM_SMUIO', - 'SOC15_IH_CLIENTID_SDMA0', 'SOC15_IH_CLIENTID_SDMA1', - 'SOC15_IH_CLIENTID_SDMA2', 'SOC15_IH_CLIENTID_SDMA3', - 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', - 'SOC15_IH_CLIENTID_SDMA4', 'SOC15_IH_CLIENTID_SDMA5', - 'SOC15_IH_CLIENTID_SDMA6', 'SOC15_IH_CLIENTID_SDMA7', - 'SOC15_IH_CLIENTID_SE0SH', 'SOC15_IH_CLIENTID_SE1SH', - 'SOC15_IH_CLIENTID_SE2SH', 'SOC15_IH_CLIENTID_SE3SH', - 'SOC15_IH_CLIENTID_THM', 'SOC15_IH_CLIENTID_UTCL2', - 'SOC15_IH_CLIENTID_UTCL2LOG', 'SOC15_IH_CLIENTID_UVD', - 'SOC15_IH_CLIENTID_UVD1', 'SOC15_IH_CLIENTID_VCE0', - 'SOC15_IH_CLIENTID_VCE1', 'SOC15_IH_CLIENTID_VCN', - 'SOC15_IH_CLIENTID_VCN1', 'SOC15_IH_CLIENTID_VMC', - 'SOC15_IH_CLIENTID_VMC1', 'SOC15_IH_CLIENTID_XDMA', - 'SOC21_IH_CLIENTID_ATHUB', 'SOC21_IH_CLIENTID_BIF', - 'SOC21_IH_CLIENTID_DCN', 'SOC21_IH_CLIENTID_DF', - 'SOC21_IH_CLIENTID_GFX', 'SOC21_IH_CLIENTID_GRBM_CP', - 'SOC21_IH_CLIENTID_IH', 'SOC21_IH_CLIENTID_IMU', - 'SOC21_IH_CLIENTID_ISP', 'SOC21_IH_CLIENTID_LSDMA', - 'SOC21_IH_CLIENTID_MAX', 'SOC21_IH_CLIENTID_MP0', - 'SOC21_IH_CLIENTID_MP1', 'SOC21_IH_CLIENTID_MP3', - 'SOC21_IH_CLIENTID_PWR', 'SOC21_IH_CLIENTID_RLC', - 'SOC21_IH_CLIENTID_ROM_SMUIO', 'SOC21_IH_CLIENTID_THM', - 'SOC21_IH_CLIENTID_VCN', 'SOC21_IH_CLIENTID_VCN1', - 'SOC21_IH_CLIENTID_VMC', 'SOC21_IH_CLIENTID_VPE', - 'SOC21_IH_CLIENTID_VPE1', 'SST_HWID', 'SYSTEMHUB_HWID', - 'TA_FW_TYPE_MAX_INDEX', 'TA_FW_TYPE_PSP_ASD', - 'TA_FW_TYPE_PSP_DTM', 'TA_FW_TYPE_PSP_HDCP', 'TA_FW_TYPE_PSP_RAP', - 'TA_FW_TYPE_PSP_RAS', 'TA_FW_TYPE_PSP_SECUREDISPLAY', - 'TA_FW_TYPE_PSP_XGMI', 'TA_FW_TYPE_UNKOWN', 'TA_TYPE_DTM', - 'TA_TYPE_HDCP', 'TA_TYPE_MAX_INDEX', 'TA_TYPE_RAP', 'TA_TYPE_RAS', - 'TA_TYPE_SECUREDISPLAY', 'TA_TYPE_XGMI', - 'TEE_ERROR_NOT_SUPPORTED', 'TEE_SUCCESS', 'THM_HWID', 'THM_HWIP', - 'TOTAL_TABLES', 'UMC_HWID', 'UMC_HWIP', 'USB_HWID', 'UVD_HWID', - 'UVD_HWIP', 'V11_STRUCTS_H_', 'V12_STRUCTS_H_', 'VCE_HWID', - 'VCE_HWIP', 'VCN1_HWIP', 'VCN_HWID', 'VCN_HWIP', 'VCN_INFO', - 'VCN_INFO_TABLE_ID', 'VCN_INFO_TABLE_MAX_NUM_INSTANCES', - 'VPE_HWID', 'VPE_HWIP', 'WAFLC_HWID', 'XCD0_NODEID', - 'XCD1_NODEID', 'XCD2_NODEID', 'XCD3_NODEID', 'XCD4_NODEID', - 'XCD5_NODEID', 'XCD6_NODEID', 'XCD7_NODEID', 'XDMA_HWID', - 'XGBE_HWID', 'XGMI_HWID', 'XGMI_HWIP', '_DISCOVERY_H_', - '_PSP_TEE_GFX_IF_H_', '__AMDGPU_IRQ_H__', '__AMDGPU_PSP_H__', - '__AMDGPU_UCODE_H__', '__AMDGPU_VM_H__', - '__SOC15_IH_CLIENTID_H__', 'amd_hw_ip_block_type', - 'amdgpu_firmware_load_type', 'amdgpu_interrupt_state', - 'amdgpu_vm_level', 'binary_header', 'bool', 'c__EA_table', - 'die_header', 'die_info', 'harvest_info', 'harvest_info_header', - 'harvest_table', 'hw_id_map', 'int16_t', 'int32_t', 'int8_t', - 'interrupt_node_id_per_aid', 'ip', 'ip_discovery_header', - 'ip_structure', 'ip_v3', 'ip_v4', 'psp_bootloader_cmd', - 'psp_fw_type', 'psp_gfx_boot_config', 'psp_gfx_boot_config_cmd', - 'psp_gfx_cmd_id', 'psp_gfx_crtl_cmd_id', 'psp_gfx_fw_type', - 'psp_memory_training_init_flag', 'psp_memory_training_ops', - 'psp_reg_prog_id', 'psp_ring_type', - 'psp_runtime_boot_cfg_feature', 'psp_runtime_entry_type', - 'psp_runtime_scpm_authentication', 'psp_shared_mem_size', - 'soc15_ih_clientid', 'soc15_ih_clientid_name', - 'soc21_ih_clientid', 'struct__fuse_data_bits', - 'struct_amdgpu_device', 'struct_amdgpu_firmware_info', - 'struct_amdgpu_iv_entry', 'struct_binary_header', - 'struct_common_firmware_header', 'struct_die', - 'struct_die_header', 'struct_die_info', - 'struct_dmcu_firmware_header_v1_0', - 'struct_dmcub_firmware_header_v1_0', 'struct_firmware', - 'struct_gc_info_v1_0', 'struct_gc_info_v1_1', - 'struct_gc_info_v1_2', 'struct_gc_info_v1_3', - 'struct_gc_info_v2_0', 'struct_gc_info_v2_1', - 'struct_gfx_firmware_header_v1_0', - 'struct_gfx_firmware_header_v2_0', - 'struct_gpu_info_firmware_header_v1_0', - 'struct_gpu_info_firmware_v1_0', 'struct_gpu_info_firmware_v1_1', - 'struct_gpu_info_header', 'struct_harvest_info', - 'struct_harvest_info_header', 'struct_harvest_table', - 'struct_imu_firmware_header_v1_0', 'struct_ip', - 'struct_ip_discovery_header', 'struct_ip_discovery_header_0_0', - 'struct_ip_structure', 'struct_ip_v3', 'struct_ip_v4', - 'struct_mall_info_header', 'struct_mall_info_v1_0', - 'struct_mall_info_v2_0', 'struct_mc_firmware_header_v1_0', - 'struct_mes_firmware_header_v1_0', 'struct_nps_info_header', - 'struct_nps_info_v1_0', 'struct_nps_instance_info_v1_0', - 'struct_psp_bin_desc', 'struct_psp_context', - 'struct_psp_firmware_header_v1_0', - 'struct_psp_firmware_header_v1_1', - 'struct_psp_firmware_header_v1_2', - 'struct_psp_firmware_header_v1_3', - 'struct_psp_firmware_header_v2_0', - 'struct_psp_firmware_header_v2_1', 'struct_psp_fw_bin_desc', - 'struct_psp_fw_legacy_bin_desc', 'struct_psp_gfx_buf_desc', - 'struct_psp_gfx_buf_list', 'struct_psp_gfx_cmd_boot_cfg', - 'struct_psp_gfx_cmd_invoke_cmd', 'struct_psp_gfx_cmd_load_ip_fw', - 'struct_psp_gfx_cmd_load_ta', 'struct_psp_gfx_cmd_load_toc', - 'struct_psp_gfx_cmd_reg_prog', 'struct_psp_gfx_cmd_resp', - 'struct_psp_gfx_cmd_save_restore_ip_fw', - 'struct_psp_gfx_cmd_setup_tmr', - 'struct_psp_gfx_cmd_setup_tmr_0_bitfield', - 'struct_psp_gfx_cmd_sriov_spatial_part', - 'struct_psp_gfx_cmd_unload_ta', 'struct_psp_gfx_ctrl', - 'struct_psp_gfx_rb_frame', 'struct_psp_gfx_resp', - 'struct_psp_gfx_uresp_bootcfg', - 'struct_psp_gfx_uresp_fwar_db_info', - 'struct_psp_gfx_uresp_reserved', 'struct_psp_xgmi_node_info', - 'struct_psp_xgmi_topology_info', - 'struct_rlc_firmware_header_v1_0', - 'struct_rlc_firmware_header_v2_0', - 'struct_rlc_firmware_header_v2_1', - 'struct_rlc_firmware_header_v2_2', - 'struct_rlc_firmware_header_v2_3', - 'struct_rlc_firmware_header_v2_4', - 'struct_sdma_firmware_header_v1_0', - 'struct_sdma_firmware_header_v1_1', - 'struct_sdma_firmware_header_v2_0', - 'struct_sdma_firmware_header_v3_0', - 'struct_smc_firmware_header_v1_0', - 'struct_smc_firmware_header_v2_0', - 'struct_smc_firmware_header_v2_1', - 'struct_smc_soft_pptable_entry', 'struct_ta_firmware_header_v1_0', - 'struct_ta_firmware_header_v2_0', 'struct_table_info', - 'struct_umsch_mm_firmware_header_v1_0', 'struct_v11_compute_mqd', - 'struct_v11_gfx_mqd', 'struct_v11_sdma_mqd', - 'struct_v12_compute_mqd', 'struct_v12_gfx_mqd', - 'struct_v12_sdma_mqd', 'struct_vcn_info_header', - 'struct_vcn_info_v1_0', 'struct_vcn_instance_info_v1_0', - 'struct_vpe_firmware_header_v1_0', 'ta_fw_type', 'ta_type_id', - 'table', 'table__enumvalues', 'table_info', 'tee_error_code', - 'u32', 'uint16_t', 'uint32_t', 'uint64_t', 'uint8_t', - 'union__fuse_data', 'union_amdgpu_firmware_header', 'union_die_0', - 'union_ip_discovery_header_0', 'union_psp_gfx_cmd_setup_tmr_0', - 'union_psp_gfx_commands', 'union_psp_gfx_uresp'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/navi10.py b/tinygrad/tinygrad/runtime/autogen/am/navi10.py deleted file mode 100644 index 1960cec8..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/navi10.py +++ /dev/null @@ -1,40774 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - - - -_navi10_ENUM_HEADER = True # macro -ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro -SQ_WAVE_TYPE_PS0 = 0x00000000 # macro -SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro -SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro -SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro -SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro -SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro -SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro -SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro -SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro -SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro -SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro -SQ_GFXDEC_BEGIN = 0x0000a000 # macro -SQ_GFXDEC_END = 0x0000c000 # macro -SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro -SQDEC_BEGIN = 0x00002300 # macro -SQDEC_END = 0x000023ff # macro -SQPERFSDEC_BEGIN = 0x0000d9c0 # macro -SQPERFSDEC_END = 0x0000da40 # macro -SQPERFDDEC_BEGIN = 0x0000d1c0 # macro -SQPERFDDEC_END = 0x0000d240 # macro -SQGFXUDEC_BEGIN = 0x0000c330 # macro -SQGFXUDEC_END = 0x0000c380 # macro -SQPWRDEC_BEGIN = 0x0000f08c # macro -SQPWRDEC_END = 0x0000f094 # macro -SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro -SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro -SQ_MAX_PGM_SGPRS = 0x00000068 # macro -SQ_MAX_PGM_VGPRS = 0x00000100 # macro -SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro -SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro -SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro -SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro -SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro -SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro -SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro -SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro -SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro -SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro -SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro -INST_ID_PRIV_START = 0x80000000 # macro -INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro -INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro -INST_ID_HW_TRAP = 0xfffffff2 # macro -INST_ID_KILL_SEQ = 0xfffffff3 # macro -INST_ID_SPI_WREXEC = 0xfffffff4 # macro -INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro -SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro -SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro -SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro -SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro -SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro -SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro -SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro -SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro -SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro -SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro -SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro -SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro -SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro -SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro -SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro -CSDATA_TYPE_WIDTH = 0x00000002 # macro -CSDATA_ADDR_WIDTH = 0x00000007 # macro -CSDATA_DATA_WIDTH = 0x00000020 # macro -CSCNTL_TYPE_WIDTH = 0x00000002 # macro -CSCNTL_ADDR_WIDTH = 0x00000007 # macro -CSCNTL_DATA_WIDTH = 0x00000020 # macro -GSTHREADID_SIZE = 0x00000002 # macro -SEM_ECC_ERROR = 0x00000000 # macro -SEM_TRANS_ERROR = 0x00000001 # macro -SEM_RESP_FAILED = 0x00000002 # macro -SEM_RESP_PASSED = 0x00000003 # macro -IQ_QUEUE_SLEEP = 0x00000000 # macro -IQ_OFFLOAD_RETRY = 0x00000001 # macro -IQ_SCH_WAVE_MSG = 0x00000002 # macro -IQ_SEM_REARM = 0x00000003 # macro -IQ_DEQUEUE_RETRY = 0x00000004 # macro -IQ_INTR_TYPE_PQ = 0x00000000 # macro -IQ_INTR_TYPE_IB = 0x00000001 # macro -IQ_INTR_TYPE_MQD = 0x00000002 # macro -VMID_SZ = 0x00000004 # macro -CONFIG_SPACE_START = 0x00002000 # macro -CONFIG_SPACE_END = 0x00009fff # macro -CONFIG_SPACE1_START = 0x00002000 # macro -CONFIG_SPACE1_END = 0x00002bff # macro -CONFIG_SPACE2_START = 0x00003000 # macro -CONFIG_SPACE2_END = 0x00009fff # macro -UCONFIG_SPACE_START = 0x0000c000 # macro -UCONFIG_SPACE_END = 0x0000ffff # macro -PERSISTENT_SPACE_START = 0x00002c00 # macro -PERSISTENT_SPACE_END = 0x00002fff # macro -CONTEXT_SPACE_START = 0x0000a000 # macro -CONTEXT_SPACE_END = 0x0000bfff # macro -ROM_SIGNATURE = 0x0000aa55 # macro -IP_USB_PD_REVISION_ID = 0x00000000 # macro - -# values for enumeration 'GDS_PERFCOUNT_SELECT' -GDS_PERFCOUNT_SELECT__enumvalues = { - 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', - 1: 'GDS_PERF_SEL_DS_BANK_CONFL', - 2: 'GDS_PERF_SEL_WBUF_FLUSH', - 3: 'GDS_PERF_SEL_WR_COMP', - 4: 'GDS_PERF_SEL_WBUF_WR', - 5: 'GDS_PERF_SEL_RBUF_HIT', - 6: 'GDS_PERF_SEL_RBUF_MISS', - 7: 'GDS_PERF_SEL_SE0_SH0_NORET', - 8: 'GDS_PERF_SEL_SE0_SH0_RET', - 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', - 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', - 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', - 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', - 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', - 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', - 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', - 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', - 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', - 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', - 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', - 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', - 21: 'GDS_PERF_SEL_SE0_SH1_NORET', - 22: 'GDS_PERF_SEL_SE0_SH1_RET', - 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', - 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', - 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', - 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', - 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', - 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', - 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', - 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', - 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', - 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', - 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', - 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', - 35: 'GDS_PERF_SEL_SE1_SH0_NORET', - 36: 'GDS_PERF_SEL_SE1_SH0_RET', - 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', - 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', - 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', - 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', - 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', - 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', - 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', - 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', - 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', - 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', - 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', - 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', - 49: 'GDS_PERF_SEL_SE1_SH1_NORET', - 50: 'GDS_PERF_SEL_SE1_SH1_RET', - 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', - 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', - 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', - 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', - 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', - 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', - 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', - 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', - 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', - 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', - 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', - 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', - 63: 'GDS_PERF_SEL_SE2_SH0_NORET', - 64: 'GDS_PERF_SEL_SE2_SH0_RET', - 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', - 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', - 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', - 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', - 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', - 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', - 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', - 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', - 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', - 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', - 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', - 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', - 77: 'GDS_PERF_SEL_SE2_SH1_NORET', - 78: 'GDS_PERF_SEL_SE2_SH1_RET', - 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', - 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', - 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', - 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', - 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', - 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', - 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', - 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', - 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', - 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', - 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', - 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', - 91: 'GDS_PERF_SEL_SE3_SH0_NORET', - 92: 'GDS_PERF_SEL_SE3_SH0_RET', - 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', - 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', - 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', - 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', - 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', - 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', - 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', - 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', - 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', - 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', - 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', - 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', - 105: 'GDS_PERF_SEL_SE3_SH1_NORET', - 106: 'GDS_PERF_SEL_SE3_SH1_RET', - 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', - 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', - 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', - 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', - 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', - 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', - 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', - 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', - 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', - 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', - 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', - 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', - 119: 'GDS_PERF_SEL_GWS_RELEASED', - 120: 'GDS_PERF_SEL_GWS_BYPASS', -} -GDS_PERF_SEL_DS_ADDR_CONFL = 0 -GDS_PERF_SEL_DS_BANK_CONFL = 1 -GDS_PERF_SEL_WBUF_FLUSH = 2 -GDS_PERF_SEL_WR_COMP = 3 -GDS_PERF_SEL_WBUF_WR = 4 -GDS_PERF_SEL_RBUF_HIT = 5 -GDS_PERF_SEL_RBUF_MISS = 6 -GDS_PERF_SEL_SE0_SH0_NORET = 7 -GDS_PERF_SEL_SE0_SH0_RET = 8 -GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 -GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 -GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 -GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 -GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 -GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 -GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 -GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 -GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 -GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 -GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 -GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 -GDS_PERF_SEL_SE0_SH1_NORET = 21 -GDS_PERF_SEL_SE0_SH1_RET = 22 -GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 -GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 -GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 -GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 -GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 -GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 -GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 -GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 -GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 -GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 -GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 -GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 -GDS_PERF_SEL_SE1_SH0_NORET = 35 -GDS_PERF_SEL_SE1_SH0_RET = 36 -GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 -GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 -GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 -GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 -GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 -GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 -GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 -GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 -GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 -GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 -GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 -GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 -GDS_PERF_SEL_SE1_SH1_NORET = 49 -GDS_PERF_SEL_SE1_SH1_RET = 50 -GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 -GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 -GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 -GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 -GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 -GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 -GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 -GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 -GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 -GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 -GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 -GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 -GDS_PERF_SEL_SE2_SH0_NORET = 63 -GDS_PERF_SEL_SE2_SH0_RET = 64 -GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 -GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 -GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 -GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 -GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 -GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 -GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 -GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 -GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 -GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 -GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 -GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 -GDS_PERF_SEL_SE2_SH1_NORET = 77 -GDS_PERF_SEL_SE2_SH1_RET = 78 -GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 -GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 -GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 -GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 -GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 -GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 -GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 -GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 -GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 -GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 -GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 -GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 -GDS_PERF_SEL_SE3_SH0_NORET = 91 -GDS_PERF_SEL_SE3_SH0_RET = 92 -GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 -GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 -GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 -GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 -GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 -GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 -GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 -GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 -GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 -GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 -GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 -GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 -GDS_PERF_SEL_SE3_SH1_NORET = 105 -GDS_PERF_SEL_SE3_SH1_RET = 106 -GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 -GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 -GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 -GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 -GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 -GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 -GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 -GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 -GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 -GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 -GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 -GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 -GDS_PERF_SEL_GWS_RELEASED = 119 -GDS_PERF_SEL_GWS_BYPASS = 120 -GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GATCL1RequestType' -GATCL1RequestType__enumvalues = { - 0: 'GATCL1_TYPE_NORMAL', - 1: 'GATCL1_TYPE_SHOOTDOWN', - 2: 'GATCL1_TYPE_BYPASS', -} -GATCL1_TYPE_NORMAL = 0 -GATCL1_TYPE_SHOOTDOWN = 1 -GATCL1_TYPE_BYPASS = 2 -GATCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1RequestType' -UTCL1RequestType__enumvalues = { - 0: 'UTCL1_TYPE_NORMAL', - 1: 'UTCL1_TYPE_SHOOTDOWN', - 2: 'UTCL1_TYPE_BYPASS', -} -UTCL1_TYPE_NORMAL = 0 -UTCL1_TYPE_SHOOTDOWN = 1 -UTCL1_TYPE_BYPASS = 2 -UTCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1FaultType' -UTCL1FaultType__enumvalues = { - 0: 'UTCL1_XNACK_SUCCESS', - 1: 'UTCL1_XNACK_RETRY', - 2: 'UTCL1_XNACK_PRT', - 3: 'UTCL1_XNACK_NO_RETRY', -} -UTCL1_XNACK_SUCCESS = 0 -UTCL1_XNACK_RETRY = 1 -UTCL1_XNACK_PRT = 2 -UTCL1_XNACK_NO_RETRY = 3 -UTCL1FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0RequestType' -UTCL0RequestType__enumvalues = { - 0: 'UTCL0_TYPE_NORMAL', - 1: 'UTCL0_TYPE_SHOOTDOWN', - 2: 'UTCL0_TYPE_BYPASS', -} -UTCL0_TYPE_NORMAL = 0 -UTCL0_TYPE_SHOOTDOWN = 1 -UTCL0_TYPE_BYPASS = 2 -UTCL0RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0FaultType' -UTCL0FaultType__enumvalues = { - 0: 'UTCL0_XNACK_SUCCESS', - 1: 'UTCL0_XNACK_RETRY', - 2: 'UTCL0_XNACK_PRT', - 3: 'UTCL0_XNACK_NO_RETRY', -} -UTCL0_XNACK_SUCCESS = 0 -UTCL0_XNACK_RETRY = 1 -UTCL0_XNACK_PRT = 2 -UTCL0_XNACK_NO_RETRY = 3 -UTCL0FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'VMEMCMD_RETURN_ORDER' -VMEMCMD_RETURN_ORDER__enumvalues = { - 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', - 1: 'VMEMCMD_RETURN_IN_ORDER', - 2: 'VMEMCMD_RETURN_IN_ORDER_READ', -} -VMEMCMD_RETURN_OUT_OF_ORDER = 0 -VMEMCMD_RETURN_IN_ORDER = 1 -VMEMCMD_RETURN_IN_ORDER_READ = 2 -VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'GL0V_CACHE_POLICIES' -GL0V_CACHE_POLICIES__enumvalues = { - 0: 'GL0V_CACHE_POLICY_MISS_LRU', - 1: 'GL0V_CACHE_POLICY_MISS_EVICT', - 2: 'GL0V_CACHE_POLICY_HIT_LRU', - 3: 'GL0V_CACHE_POLICY_HIT_EVICT', -} -GL0V_CACHE_POLICY_MISS_LRU = 0 -GL0V_CACHE_POLICY_MISS_EVICT = 1 -GL0V_CACHE_POLICY_HIT_LRU = 2 -GL0V_CACHE_POLICY_HIT_EVICT = 3 -GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_POLICIES' -GL1_CACHE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_POLICY_MISS_LRU', - 1: 'GL1_CACHE_POLICY_MISS_EVICT', - 2: 'GL1_CACHE_POLICY_HIT_LRU', - 3: 'GL1_CACHE_POLICY_HIT_EVICT', -} -GL1_CACHE_POLICY_MISS_LRU = 0 -GL1_CACHE_POLICY_MISS_EVICT = 1 -GL1_CACHE_POLICY_HIT_LRU = 2 -GL1_CACHE_POLICY_HIT_EVICT = 3 -GL1_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_STORE_POLICIES' -GL1_CACHE_STORE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_STORE_POLICY_BYPASS', -} -GL1_CACHE_STORE_POLICY_BYPASS = 0 -GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_CACHE_POLICIES' -TCC_CACHE_POLICIES__enumvalues = { - 0: 'TCC_CACHE_POLICY_LRU', - 1: 'TCC_CACHE_POLICY_STREAM', -} -TCC_CACHE_POLICY_LRU = 0 -TCC_CACHE_POLICY_STREAM = 1 -TCC_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_MTYPE' -TCC_MTYPE__enumvalues = { - 0: 'MTYPE_NC', - 1: 'MTYPE_WC', - 2: 'MTYPE_CC', -} -MTYPE_NC = 0 -MTYPE_WC = 1 -MTYPE_CC = 2 -TCC_MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_CACHE_POLICIES' -GL2_CACHE_POLICIES__enumvalues = { - 0: 'GL2_CACHE_POLICY_LRU', - 1: 'GL2_CACHE_POLICY_STREAM', - 2: 'GL2_CACHE_POLICY_NOA', - 3: 'GL2_CACHE_POLICY_BYPASS', -} -GL2_CACHE_POLICY_LRU = 0 -GL2_CACHE_POLICY_STREAM = 1 -GL2_CACHE_POLICY_NOA = 2 -GL2_CACHE_POLICY_BYPASS = 3 -GL2_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'MTYPE' -MTYPE__enumvalues = { - 0: 'MTYPE_C_RW_US', - 1: 'MTYPE_RESERVED_1', - 2: 'MTYPE_C_RO_S', - 3: 'MTYPE_UC', - 4: 'MTYPE_C_RW_S', - 5: 'MTYPE_RESERVED_5', - 6: 'MTYPE_C_RO_US', - 7: 'MTYPE_RESERVED_7', -} -MTYPE_C_RW_US = 0 -MTYPE_RESERVED_1 = 1 -MTYPE_C_RO_S = 2 -MTYPE_UC = 3 -MTYPE_C_RW_S = 4 -MTYPE_RESERVED_5 = 5 -MTYPE_C_RO_US = 6 -MTYPE_RESERVED_7 = 7 -MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'RMI_CID' -RMI_CID__enumvalues = { - 0: 'RMI_CID_CC', - 1: 'RMI_CID_FC', - 2: 'RMI_CID_CM', - 3: 'RMI_CID_DC', - 4: 'RMI_CID_Z', - 5: 'RMI_CID_S', - 6: 'RMI_CID_TILE', - 7: 'RMI_CID_ZPCPSD', -} -RMI_CID_CC = 0 -RMI_CID_FC = 1 -RMI_CID_CM = 2 -RMI_CID_DC = 3 -RMI_CID_Z = 4 -RMI_CID_S = 5 -RMI_CID_TILE = 6 -RMI_CID_ZPCPSD = 7 -RMI_CID = ctypes.c_uint32 # enum - -# values for enumeration 'WritePolicy' -WritePolicy__enumvalues = { - 0: 'CACHE_LRU_WR', - 1: 'CACHE_STREAM', - 2: 'CACHE_BYPASS', - 3: 'UNCACHED_WR', -} -CACHE_LRU_WR = 0 -CACHE_STREAM = 1 -CACHE_BYPASS = 2 -UNCACHED_WR = 3 -WritePolicy = ctypes.c_uint32 # enum - -# values for enumeration 'ReadPolicy' -ReadPolicy__enumvalues = { - 0: 'CACHE_LRU_RD', - 1: 'CACHE_NOA', - 2: 'UNCACHED_RD', - 3: 'RESERVED_RDPOLICY', -} -CACHE_LRU_RD = 0 -CACHE_NOA = 1 -UNCACHED_RD = 2 -RESERVED_RDPOLICY = 3 -ReadPolicy = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_COUNTER_MODE' -PERFMON_COUNTER_MODE__enumvalues = { - 0: 'PERFMON_COUNTER_MODE_ACCUM', - 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 2: 'PERFMON_COUNTER_MODE_MAX', - 3: 'PERFMON_COUNTER_MODE_DIRTY', - 4: 'PERFMON_COUNTER_MODE_SAMPLE', - 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 15: 'PERFMON_COUNTER_MODE_RESERVED', -} -PERFMON_COUNTER_MODE_ACCUM = 0 -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 -PERFMON_COUNTER_MODE_MAX = 2 -PERFMON_COUNTER_MODE_DIRTY = 3 -PERFMON_COUNTER_MODE_SAMPLE = 4 -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 -PERFMON_COUNTER_MODE_RESERVED = 15 -PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_SPM_MODE' -PERFMON_SPM_MODE__enumvalues = { - 0: 'PERFMON_SPM_MODE_OFF', - 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', - 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', - 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 5: 'PERFMON_SPM_MODE_RESERVED_5', - 6: 'PERFMON_SPM_MODE_RESERVED_6', - 7: 'PERFMON_SPM_MODE_RESERVED_7', - 8: 'PERFMON_SPM_MODE_TEST_MODE_0', - 9: 'PERFMON_SPM_MODE_TEST_MODE_1', - 10: 'PERFMON_SPM_MODE_TEST_MODE_2', -} -PERFMON_SPM_MODE_OFF = 0 -PERFMON_SPM_MODE_16BIT_CLAMP = 1 -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 -PERFMON_SPM_MODE_32BIT_CLAMP = 3 -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 -PERFMON_SPM_MODE_RESERVED_5 = 5 -PERFMON_SPM_MODE_RESERVED_6 = 6 -PERFMON_SPM_MODE_RESERVED_7 = 7 -PERFMON_SPM_MODE_TEST_MODE_0 = 8 -PERFMON_SPM_MODE_TEST_MODE_1 = 9 -PERFMON_SPM_MODE_TEST_MODE_2 = 10 -PERFMON_SPM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceTiling' -SurfaceTiling__enumvalues = { - 0: 'ARRAY_LINEAR', - 1: 'ARRAY_TILED', -} -ARRAY_LINEAR = 0 -ARRAY_TILED = 1 -SurfaceTiling = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceArray' -SurfaceArray__enumvalues = { - 0: 'ARRAY_1D', - 1: 'ARRAY_2D', - 2: 'ARRAY_3D', - 3: 'ARRAY_3D_SLICE', -} -ARRAY_1D = 0 -ARRAY_2D = 1 -ARRAY_3D = 2 -ARRAY_3D_SLICE = 3 -SurfaceArray = ctypes.c_uint32 # enum - -# values for enumeration 'ColorArray' -ColorArray__enumvalues = { - 0: 'ARRAY_2D_ALT_COLOR', - 1: 'ARRAY_2D_COLOR', - 3: 'ARRAY_3D_SLICE_COLOR', -} -ARRAY_2D_ALT_COLOR = 0 -ARRAY_2D_COLOR = 1 -ARRAY_3D_SLICE_COLOR = 3 -ColorArray = ctypes.c_uint32 # enum - -# values for enumeration 'DepthArray' -DepthArray__enumvalues = { - 0: 'ARRAY_2D_ALT_DEPTH', - 1: 'ARRAY_2D_DEPTH', -} -ARRAY_2D_ALT_DEPTH = 0 -ARRAY_2D_DEPTH = 1 -DepthArray = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_NUM_SIMD_PER_CU' -ENUM_NUM_SIMD_PER_CU__enumvalues = { - 2: 'NUM_SIMD_PER_CU', -} -NUM_SIMD_PER_CU = 2 -ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_ENABLE_ERROR_INJECT' -DSM_ENABLE_ERROR_INJECT__enumvalues = { - 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', -} -DSM_ENABLE_ERROR_INJECT_FED_IN = 0 -DSM_ENABLE_ERROR_INJECT_SINGLE = 1 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 -DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SELECT_INJECT_DELAY' -DSM_SELECT_INJECT_DELAY__enumvalues = { - 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', - 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', -} -DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 -DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 -DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_DATA_SEL' -DSM_DATA_SEL__enumvalues = { - 0: 'DSM_DATA_SEL_DISABLE', - 1: 'DSM_DATA_SEL_0', - 2: 'DSM_DATA_SEL_1', - 3: 'DSM_DATA_SEL_BOTH', -} -DSM_DATA_SEL_DISABLE = 0 -DSM_DATA_SEL_0 = 1 -DSM_DATA_SEL_1 = 2 -DSM_DATA_SEL_BOTH = 3 -DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SINGLE_WRITE' -DSM_SINGLE_WRITE__enumvalues = { - 0: 'DSM_SINGLE_WRITE_DIS', - 1: 'DSM_SINGLE_WRITE_EN', -} -DSM_SINGLE_WRITE_DIS = 0 -DSM_SINGLE_WRITE_EN = 1 -DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'Hdp_SurfaceEndian' -Hdp_SurfaceEndian__enumvalues = { - 0: 'HDP_ENDIAN_NONE', - 1: 'HDP_ENDIAN_8IN16', - 2: 'HDP_ENDIAN_8IN32', - 3: 'HDP_ENDIAN_8IN64', -} -HDP_ENDIAN_NONE = 0 -HDP_ENDIAN_8IN16 = 1 -HDP_ENDIAN_8IN32 = 2 -HDP_ENDIAN_8IN64 = 3 -Hdp_SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_ENABLE' -CNVC_ENABLE__enumvalues = { - 0: 'CNVC_DIS', - 1: 'CNVC_EN', -} -CNVC_DIS = 0 -CNVC_EN = 1 -CNVC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_BYPASS' -CNVC_BYPASS__enumvalues = { - 0: 'CNVC_BYPASS_DISABLE', - 1: 'CNVC_BYPASS_EN', -} -CNVC_BYPASS_DISABLE = 0 -CNVC_BYPASS_EN = 1 -CNVC_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_PENDING' -CNVC_PENDING__enumvalues = { - 0: 'CNVC_NOT_PENDING', - 1: 'CNVC_YES_PENDING', -} -CNVC_NOT_PENDING = 0 -CNVC_YES_PENDING = 1 -CNVC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'DENORM_TRUNCATE' -DENORM_TRUNCATE__enumvalues = { - 0: 'CNVC_ROUND', - 1: 'CNVC_TRUNCATE', -} -CNVC_ROUND = 0 -CNVC_TRUNCATE = 1 -DENORM_TRUNCATE = ctypes.c_uint32 # enum - -# values for enumeration 'PIX_EXPAND_MODE' -PIX_EXPAND_MODE__enumvalues = { - 0: 'PIX_DYNAMIC_EXPANSION', - 1: 'PIX_ZERO_EXPANSION', -} -PIX_DYNAMIC_EXPANSION = 0 -PIX_ZERO_EXPANSION = 1 -PIX_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_PIXEL_FORMAT' -SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'ARGB1555', - 2: 'RGBA5551', - 3: 'RGB565', - 4: 'BGR565', - 5: 'ARGB4444', - 6: 'RGBA4444', - 8: 'ARGB8888', - 9: 'RGBA8888', - 10: 'ARGB2101010', - 11: 'RGBA1010102', - 12: 'AYCrCb8888', - 13: 'YCrCbA8888', - 14: 'ACrYCb8888', - 15: 'CrYCbA8888', - 16: 'ARGB16161616_10MSB', - 17: 'RGBA16161616_10MSB', - 18: 'ARGB16161616_10LSB', - 19: 'RGBA16161616_10LSB', - 20: 'ARGB16161616_12MSB', - 21: 'RGBA16161616_12MSB', - 22: 'ARGB16161616_12LSB', - 23: 'RGBA16161616_12LSB', - 24: 'ARGB16161616_FLOAT', - 25: 'RGBA16161616_FLOAT', - 26: 'ARGB16161616_UNORM', - 27: 'RGBA16161616_UNORM', - 28: 'ARGB16161616_SNORM', - 29: 'RGBA16161616_SNORM', - 32: 'AYCrCb16161616_10MSB', - 33: 'AYCrCb16161616_10LSB', - 34: 'YCrCbA16161616_10MSB', - 35: 'YCrCbA16161616_10LSB', - 36: 'ACrYCb16161616_10MSB', - 37: 'ACrYCb16161616_10LSB', - 38: 'CrYCbA16161616_10MSB', - 39: 'CrYCbA16161616_10LSB', - 40: 'AYCrCb16161616_12MSB', - 41: 'AYCrCb16161616_12LSB', - 42: 'YCrCbA16161616_12MSB', - 43: 'YCrCbA16161616_12LSB', - 44: 'ACrYCb16161616_12MSB', - 45: 'ACrYCb16161616_12LSB', - 46: 'CrYCbA16161616_12MSB', - 47: 'CrYCbA16161616_12LSB', - 64: 'Y8_CrCb88_420_PLANAR', - 65: 'Y8_CbCr88_420_PLANAR', - 66: 'Y10_CrCb1010_420_PLANAR', - 67: 'Y10_CbCr1010_420_PLANAR', - 68: 'Y12_CrCb1212_420_PLANAR', - 69: 'Y12_CbCr1212_420_PLANAR', - 72: 'YCrYCb8888_422_PACKED', - 73: 'YCbYCr8888_422_PACKED', - 74: 'CrYCbY8888_422_PACKED', - 75: 'CbYCrY8888_422_PACKED', - 76: 'YCrYCb10101010_422_PACKED', - 77: 'YCbYCr10101010_422_PACKED', - 78: 'CrYCbY10101010_422_PACKED', - 79: 'CbYCrY10101010_422_PACKED', - 80: 'YCrYCb12121212_422_PACKED', - 81: 'YCbYCr12121212_422_PACKED', - 82: 'CrYCbY12121212_422_PACKED', - 83: 'CbYCrY12121212_422_PACKED', - 112: 'RGB111110_FIX', - 113: 'BGR101111_FIX', - 114: 'ACrYCb2101010', - 115: 'CrYCbA1010102', - 118: 'RGB111110_FLOAT', - 119: 'BGR101111_FLOAT', - 120: 'MONO_8', - 121: 'MONO_10MSB', - 122: 'MONO_10LSB', - 123: 'MONO_12MSB', - 124: 'MONO_12LSB', - 125: 'MONO_16', -} -ARGB1555 = 1 -RGBA5551 = 2 -RGB565 = 3 -BGR565 = 4 -ARGB4444 = 5 -RGBA4444 = 6 -ARGB8888 = 8 -RGBA8888 = 9 -ARGB2101010 = 10 -RGBA1010102 = 11 -AYCrCb8888 = 12 -YCrCbA8888 = 13 -ACrYCb8888 = 14 -CrYCbA8888 = 15 -ARGB16161616_10MSB = 16 -RGBA16161616_10MSB = 17 -ARGB16161616_10LSB = 18 -RGBA16161616_10LSB = 19 -ARGB16161616_12MSB = 20 -RGBA16161616_12MSB = 21 -ARGB16161616_12LSB = 22 -RGBA16161616_12LSB = 23 -ARGB16161616_FLOAT = 24 -RGBA16161616_FLOAT = 25 -ARGB16161616_UNORM = 26 -RGBA16161616_UNORM = 27 -ARGB16161616_SNORM = 28 -RGBA16161616_SNORM = 29 -AYCrCb16161616_10MSB = 32 -AYCrCb16161616_10LSB = 33 -YCrCbA16161616_10MSB = 34 -YCrCbA16161616_10LSB = 35 -ACrYCb16161616_10MSB = 36 -ACrYCb16161616_10LSB = 37 -CrYCbA16161616_10MSB = 38 -CrYCbA16161616_10LSB = 39 -AYCrCb16161616_12MSB = 40 -AYCrCb16161616_12LSB = 41 -YCrCbA16161616_12MSB = 42 -YCrCbA16161616_12LSB = 43 -ACrYCb16161616_12MSB = 44 -ACrYCb16161616_12LSB = 45 -CrYCbA16161616_12MSB = 46 -CrYCbA16161616_12LSB = 47 -Y8_CrCb88_420_PLANAR = 64 -Y8_CbCr88_420_PLANAR = 65 -Y10_CrCb1010_420_PLANAR = 66 -Y10_CbCr1010_420_PLANAR = 67 -Y12_CrCb1212_420_PLANAR = 68 -Y12_CbCr1212_420_PLANAR = 69 -YCrYCb8888_422_PACKED = 72 -YCbYCr8888_422_PACKED = 73 -CrYCbY8888_422_PACKED = 74 -CbYCrY8888_422_PACKED = 75 -YCrYCb10101010_422_PACKED = 76 -YCbYCr10101010_422_PACKED = 77 -CrYCbY10101010_422_PACKED = 78 -CbYCrY10101010_422_PACKED = 79 -YCrYCb12121212_422_PACKED = 80 -YCbYCr12121212_422_PACKED = 81 -CrYCbY12121212_422_PACKED = 82 -CbYCrY12121212_422_PACKED = 83 -RGB111110_FIX = 112 -BGR101111_FIX = 113 -ACrYCb2101010 = 114 -CrYCbA1010102 = 115 -RGB111110_FLOAT = 118 -BGR101111_FLOAT = 119 -MONO_8 = 120 -MONO_10MSB = 121 -MONO_10LSB = 122 -MONO_12MSB = 123 -MONO_12LSB = 124 -MONO_16 = 125 -SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'XNORM' -XNORM__enumvalues = { - 0: 'XNORM_A', - 1: 'XNORM_B', -} -XNORM_A = 0 -XNORM_B = 1 -XNORM = ctypes.c_uint32 # enum - -# values for enumeration 'COLOR_KEYER_MODE' -COLOR_KEYER_MODE__enumvalues = { - 0: 'FORCE_00', - 1: 'FORCE_FF', - 2: 'RANGE_00', - 3: 'RANGE_FF', -} -FORCE_00 = 0 -FORCE_FF = 1 -RANGE_00 = 2 -RANGE_FF = 3 -COLOR_KEYER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ENABLE' -CUR_ENABLE__enumvalues = { - 0: 'CUR_DIS', - 1: 'CUR_EN', -} -CUR_DIS = 0 -CUR_EN = 1 -CUR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_PENDING' -CUR_PENDING__enumvalues = { - 0: 'CUR_NOT_PENDING', - 1: 'CUR_YES_PENDING', -} -CUR_NOT_PENDING = 0 -CUR_YES_PENDING = 1 -CUR_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_EXPAND_MODE' -CUR_EXPAND_MODE__enumvalues = { - 0: 'CUR_DYNAMIC_EXPANSION', - 1: 'CUR_ZERO_EXPANSION', -} -CUR_DYNAMIC_EXPANSION = 0 -CUR_ZERO_EXPANSION = 1 -CUR_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ROM_EN' -CUR_ROM_EN__enumvalues = { - 0: 'CUR_FP_NO_ROM', - 1: 'CUR_FP_USE_ROM', -} -CUR_FP_NO_ROM = 0 -CUR_FP_USE_ROM = 1 -CUR_ROM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_MODE' -CUR_MODE__enumvalues = { - 0: 'MONO_2BIT', - 1: 'COLOR_24BIT_1BIT_AND', - 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'COLOR_64BIT_FP_PREMULT', - 5: 'COLOR_64BIT_FP_UNPREMULT', -} -MONO_2BIT = 0 -COLOR_24BIT_1BIT_AND = 1 -COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -COLOR_64BIT_FP_PREMULT = 4 -COLOR_64BIT_FP_UNPREMULT = 5 -CUR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_INV_CLAMP' -CUR_INV_CLAMP__enumvalues = { - 0: 'CUR_CLAMP_DIS', - 1: 'CUR_CLAMP_EN', -} -CUR_CLAMP_DIS = 0 -CUR_CLAMP_EN = 1 -CUR_INV_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' -SCL_COEF_FILTER_TYPE_SEL__enumvalues = { - 0: 'SCL_COEF_LUMA_VERT_FILTER', - 1: 'SCL_COEF_LUMA_HORZ_FILTER', - 2: 'SCL_COEF_CHROMA_VERT_FILTER', - 3: 'SCL_COEF_CHROMA_HORZ_FILTER', - 4: 'SCL_COEF_ALPHA_VERT_FILTER', - 5: 'SCL_COEF_ALPHA_HORZ_FILTER', -} -SCL_COEF_LUMA_VERT_FILTER = 0 -SCL_COEF_LUMA_HORZ_FILTER = 1 -SCL_COEF_CHROMA_VERT_FILTER = 2 -SCL_COEF_CHROMA_HORZ_FILTER = 3 -SCL_COEF_ALPHA_VERT_FILTER = 4 -SCL_COEF_ALPHA_HORZ_FILTER = 5 -SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSCL_MODE_SEL' -DSCL_MODE_SEL__enumvalues = { - 0: 'DSCL_MODE_SCALING_444_BYPASS', - 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', - 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', - 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', - 6: 'DSCL_MODE_DSCL_BYPASS', -} -DSCL_MODE_SCALING_444_BYPASS = 0 -DSCL_MODE_SCALING_444_RGB_ENABLE = 1 -DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 -DSCL_MODE_SCALING_YCBCR_ENABLE = 3 -DSCL_MODE_LUMA_SCALING_BYPASS = 4 -DSCL_MODE_CHROMA_SCALING_BYPASS = 5 -DSCL_MODE_DSCL_BYPASS = 6 -DSCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_AUTOCAL_MODE' -SCL_AUTOCAL_MODE__enumvalues = { - 0: 'AUTOCAL_MODE_OFF', - 1: 'AUTOCAL_MODE_AUTOSCALE', - 2: 'AUTOCAL_MODE_AUTOCENTER', - 3: 'AUTOCAL_MODE_AUTOREPLICATE', -} -AUTOCAL_MODE_OFF = 0 -AUTOCAL_MODE_AUTOSCALE = 1 -AUTOCAL_MODE_AUTOCENTER = 2 -AUTOCAL_MODE_AUTOREPLICATE = 3 -SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_RAM_SEL' -SCL_COEF_RAM_SEL__enumvalues = { - 0: 'SCL_COEF_RAM_SEL_0', - 1: 'SCL_COEF_RAM_SEL_1', -} -SCL_COEF_RAM_SEL_0 = 0 -SCL_COEF_RAM_SEL_1 = 1 -SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_CHROMA_COEF' -SCL_CHROMA_COEF__enumvalues = { - 0: 'SCL_CHROMA_COEF_LUMA', - 1: 'SCL_CHROMA_COEF_CHROMA', -} -SCL_CHROMA_COEF_LUMA = 0 -SCL_CHROMA_COEF_CHROMA = 1 -SCL_CHROMA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_ALPHA_COEF' -SCL_ALPHA_COEF__enumvalues = { - 0: 'SCL_ALPHA_COEF_LUMA', - 1: 'SCL_ALPHA_COEF_ALPHA', -} -SCL_ALPHA_COEF_LUMA = 0 -SCL_ALPHA_COEF_ALPHA = 1 -SCL_ALPHA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'COEF_RAM_SELECT_RD' -COEF_RAM_SELECT_RD__enumvalues = { - 0: 'COEF_RAM_SELECT_BACK', - 1: 'COEF_RAM_SELECT_CURRENT', -} -COEF_RAM_SELECT_BACK = 0 -COEF_RAM_SELECT_CURRENT = 1 -COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_2TAP_HARDCODE' -SCL_2TAP_HARDCODE__enumvalues = { - 0: 'SCL_COEF_2TAP_HARDCODE_OFF', - 1: 'SCL_COEF_2TAP_HARDCODE_ON', -} -SCL_COEF_2TAP_HARDCODE_OFF = 0 -SCL_COEF_2TAP_HARDCODE_ON = 1 -SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_SHARP_EN' -SCL_SHARP_EN__enumvalues = { - 0: 'SCL_SHARP_DISABLE', - 1: 'SCL_SHARP_ENABLE', -} -SCL_SHARP_DISABLE = 0 -SCL_SHARP_ENABLE = 1 -SCL_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BOUNDARY' -SCL_BOUNDARY__enumvalues = { - 0: 'SCL_BOUNDARY_EDGE', - 1: 'SCL_BOUNDARY_BLACK', -} -SCL_BOUNDARY_EDGE = 0 -SCL_BOUNDARY_BLACK = 1 -SCL_BOUNDARY = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERLEAVE_EN' -LB_INTERLEAVE_EN__enumvalues = { - 0: 'LB_INTERLEAVE_DISABLE', - 1: 'LB_INTERLEAVE_ENABLE', -} -LB_INTERLEAVE_DISABLE = 0 -LB_INTERLEAVE_ENABLE = 1 -LB_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_ALPHA_EN' -LB_ALPHA_EN__enumvalues = { - 0: 'LB_ALPHA_DISABLE', - 1: 'LB_ALPHA_ENABLE', -} -LB_ALPHA_DISABLE = 0 -LB_ALPHA_ENABLE = 1 -LB_ALPHA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_BYPASS_SEL' -OBUF_BYPASS_SEL__enumvalues = { - 0: 'OBUF_BYPASS_DIS', - 1: 'OBUF_BYPASS_EN', -} -OBUF_BYPASS_DIS = 0 -OBUF_BYPASS_EN = 1 -OBUF_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' -OBUF_USE_FULL_BUFFER_SEL__enumvalues = { - 0: 'OBUF_RECOUT', - 1: 'OBUF_FULL', -} -OBUF_RECOUT = 0 -OBUF_FULL = 1 -OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' -OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { - 0: 'OBUF_FULL_RECOUT', - 1: 'OBUF_HALF_RECOUT', -} -OBUF_FULL_RECOUT = 0 -OBUF_HALF_RECOUT = 1 -OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_BYPASS' -CM_BYPASS__enumvalues = { - 0: 'NON_BYPASS', - 1: 'BYPASS_EN', -} -NON_BYPASS = 0 -BYPASS_EN = 1 -CM_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CM_EN' -CM_EN__enumvalues = { - 0: 'CM_DISABLE', - 1: 'CM_ENABLE', -} -CM_DISABLE = 0 -CM_ENABLE = 1 -CM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CM_PENDING' -CM_PENDING__enumvalues = { - 0: 'CM_NOT_PENDING', - 1: 'CM_YES_PENDING', -} -CM_NOT_PENDING = 0 -CM_YES_PENDING = 1 -CM_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CM_DATA_SIGNED' -CM_DATA_SIGNED__enumvalues = { - 0: 'UNSIGNED', - 1: 'SIGNED', -} -UNSIGNED = 0 -SIGNED = 1 -CM_DATA_SIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'CM_WRITE_BASE_ONLY' -CM_WRITE_BASE_ONLY__enumvalues = { - 0: 'WRITE_BOTH', - 1: 'WRITE_BASE_ONLY', -} -WRITE_BOTH = 0 -WRITE_BASE_ONLY = 1 -CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_CONFIG_ENUM' -CM_LUT_4_CONFIG_ENUM__enumvalues = { - 0: 'LUT_4CFG_NO_MEMORY', - 1: 'LUT_4CFG_ROM_A', - 2: 'LUT_4CFG_ROM_B', - 3: 'LUT_4CFG_MEMORY_A', - 4: 'LUT_4CFG_MEMORY_B', -} -LUT_4CFG_NO_MEMORY = 0 -LUT_4CFG_ROM_A = 1 -LUT_4CFG_ROM_B = 2 -LUT_4CFG_MEMORY_A = 3 -LUT_4CFG_MEMORY_B = 4 -CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_CONFIG_ENUM' -CM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'LUT_2CFG_NO_MEMORY', - 1: 'LUT_2CFG_MEMORY_A', - 2: 'LUT_2CFG_MEMORY_B', -} -LUT_2CFG_NO_MEMORY = 0 -LUT_2CFG_MEMORY_A = 1 -LUT_2CFG_MEMORY_B = 2 -CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_MODE_ENUM' -CM_LUT_4_MODE_ENUM__enumvalues = { - 0: 'LUT_4_MODE_BYPASS', - 1: 'LUT_4_MODE_ROMA_LUT', - 2: 'LUT_4_MODE_ROMB_LUT', - 3: 'LUT_4_MODE_RAMA_LUT', - 4: 'LUT_4_MODE_RAMB_LUT', -} -LUT_4_MODE_BYPASS = 0 -LUT_4_MODE_ROMA_LUT = 1 -LUT_4_MODE_ROMB_LUT = 2 -LUT_4_MODE_RAMA_LUT = 3 -LUT_4_MODE_RAMB_LUT = 4 -CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_MODE_ENUM' -CM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'LUT_2_MODE_BYPASS', - 1: 'LUT_2_MODE_RAMA_LUT', - 2: 'LUT_2_MODE_RAMB_LUT', -} -LUT_2_MODE_BYPASS = 0 -LUT_2_MODE_RAMA_LUT = 1 -LUT_2_MODE_RAMB_LUT = 2 -CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_RAM_SEL' -CM_LUT_RAM_SEL__enumvalues = { - 0: 'RAMA_ACCESS', - 1: 'RAMB_ACCESS', -} -RAMA_ACCESS = 0 -RAMB_ACCESS = 1 -CM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_NUM_SEG' -CM_LUT_NUM_SEG__enumvalues = { - 0: 'SEGMENTS_1', - 1: 'SEGMENTS_2', - 2: 'SEGMENTS_4', - 3: 'SEGMENTS_8', - 4: 'SEGMENTS_16', - 5: 'SEGMENTS_32', - 6: 'SEGMENTS_64', - 7: 'SEGMENTS_128', -} -SEGMENTS_1 = 0 -SEGMENTS_2 = 1 -SEGMENTS_4 = 2 -SEGMENTS_8 = 3 -SEGMENTS_16 = 4 -SEGMENTS_32 = 5 -SEGMENTS_64 = 6 -SEGMENTS_128 = 7 -CM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_ICSC_MODE_ENUM' -CM_ICSC_MODE_ENUM__enumvalues = { - 0: 'BYPASS_ICSC', - 1: 'COEF_ICSC', - 2: 'COEF_ICSC_B', -} -BYPASS_ICSC = 0 -COEF_ICSC = 1 -COEF_ICSC_B = 2 -CM_ICSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' -CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'BYPASS_GAMUT', - 1: 'GAMUT_COEF', - 2: 'GAMUT_COEF_B', -} -BYPASS_GAMUT = 0 -GAMUT_COEF = 1 -GAMUT_COEF_B = 2 -CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_COEF_FORMAT_ENUM' -CM_COEF_FORMAT_ENUM__enumvalues = { - 0: 'FIX_S2_13', - 1: 'FIX_S3_12', -} -FIX_S2_13 = 0 -FIX_S3_12 = 1 -CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' -CMC_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'CMC_LUT_2CFG_NO_MEMORY', - 1: 'CMC_LUT_2CFG_MEMORY_A', - 2: 'CMC_LUT_2CFG_MEMORY_B', -} -CMC_LUT_2CFG_NO_MEMORY = 0 -CMC_LUT_2CFG_MEMORY_A = 1 -CMC_LUT_2CFG_MEMORY_B = 2 -CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_MODE_ENUM' -CMC_LUT_2_MODE_ENUM__enumvalues = { - 0: 'CMC_LUT_2_MODE_BYPASS', - 1: 'CMC_LUT_2_MODE_RAMA_LUT', - 2: 'CMC_LUT_2_MODE_RAMB_LUT', -} -CMC_LUT_2_MODE_BYPASS = 0 -CMC_LUT_2_MODE_RAMA_LUT = 1 -CMC_LUT_2_MODE_RAMB_LUT = 2 -CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_RAM_SEL' -CMC_LUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAMA_ACCESS', - 1: 'CMC_RAMB_ACCESS', -} -CMC_RAMA_ACCESS = 0 -CMC_RAMB_ACCESS = 1 -CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_RAM_SEL' -CMC_3DLUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAM0_ACCESS', - 1: 'CMC_RAM1_ACCESS', - 2: 'CMC_RAM2_ACCESS', - 3: 'CMC_RAM3_ACCESS', -} -CMC_RAM0_ACCESS = 0 -CMC_RAM1_ACCESS = 1 -CMC_RAM2_ACCESS = 2 -CMC_RAM3_ACCESS = 3 -CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_NUM_SEG' -CMC_LUT_NUM_SEG__enumvalues = { - 0: 'CMC_SEGMENTS_1', - 1: 'CMC_SEGMENTS_2', - 2: 'CMC_SEGMENTS_4', - 3: 'CMC_SEGMENTS_8', - 4: 'CMC_SEGMENTS_16', - 5: 'CMC_SEGMENTS_32', - 6: 'CMC_SEGMENTS_64', - 7: 'CMC_SEGMENTS_128', -} -CMC_SEGMENTS_1 = 0 -CMC_SEGMENTS_2 = 1 -CMC_SEGMENTS_4 = 2 -CMC_SEGMENTS_8 = 3 -CMC_SEGMENTS_16 = 4 -CMC_SEGMENTS_32 = 5 -CMC_SEGMENTS_64 = 6 -CMC_SEGMENTS_128 = 7 -CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_30BIT_ENUM' -CMC_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'CMC_3DLUT_36BIT', - 1: 'CMC_3DLUT_30BIT', -} -CMC_3DLUT_36BIT = 0 -CMC_3DLUT_30BIT = 1 -CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_SIZE_ENUM' -CMC_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'CMC_3DLUT_17CUBE', - 1: 'CMC_3DLUT_9CUBE', -} -CMC_3DLUT_17CUBE = 0 -CMC_3DLUT_9CUBE = 1 -CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_SEL' -TEST_CLK_SEL__enumvalues = { - 0: 'TEST_CLK_SEL_0', - 1: 'TEST_CLK_SEL_1', - 2: 'TEST_CLK_SEL_2', - 3: 'TEST_CLK_SEL_3', - 4: 'TEST_CLK_SEL_4', - 5: 'TEST_CLK_SEL_5', - 6: 'TEST_CLK_SEL_6', - 7: 'TEST_CLK_SEL_7', - 8: 'TEST_CLK_SEL_8', -} -TEST_CLK_SEL_0 = 0 -TEST_CLK_SEL_1 = 1 -TEST_CLK_SEL_2 = 2 -TEST_CLK_SEL_3 = 3 -TEST_CLK_SEL_4 = 4 -TEST_CLK_SEL_5 = 5 -TEST_CLK_SEL_6 = 6 -TEST_CLK_SEL_7 = 7 -TEST_CLK_SEL_8 = 8 -TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_SRC_SEL' -CRC_SRC_SEL__enumvalues = { - 0: 'CRC_SRC_0', - 1: 'CRC_SRC_1', - 2: 'CRC_SRC_2', - 3: 'CRC_SRC_3', -} -CRC_SRC_0 = 0 -CRC_SRC_1 = 1 -CRC_SRC_2 = 2 -CRC_SRC_3 = 3 -CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_PIX_SEL' -CRC_IN_PIX_SEL__enumvalues = { - 0: 'CRC_IN_PIX_0', - 1: 'CRC_IN_PIX_1', - 2: 'CRC_IN_PIX_2', - 3: 'CRC_IN_PIX_3', - 4: 'CRC_IN_PIX_4', - 5: 'CRC_IN_PIX_5', - 6: 'CRC_IN_PIX_6', - 7: 'CRC_IN_PIX_7', -} -CRC_IN_PIX_0 = 0 -CRC_IN_PIX_1 = 1 -CRC_IN_PIX_2 = 2 -CRC_IN_PIX_3 = 3 -CRC_IN_PIX_4 = 4 -CRC_IN_PIX_5 = 5 -CRC_IN_PIX_6 = 6 -CRC_IN_PIX_7 = 7 -CRC_IN_PIX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_CUR_BITS_SEL' -CRC_CUR_BITS_SEL__enumvalues = { - 0: 'CRC_CUR_BITS_0', - 1: 'CRC_CUR_BITS_1', -} -CRC_CUR_BITS_0 = 0 -CRC_CUR_BITS_1 = 1 -CRC_CUR_BITS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_CUR_SEL' -CRC_IN_CUR_SEL__enumvalues = { - 0: 'CRC_IN_CUR_0', - 1: 'CRC_IN_CUR_1', -} -CRC_IN_CUR_0 = 0 -CRC_IN_CUR_1 = 1 -CRC_IN_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_CUR_SEL' -CRC_CUR_SEL__enumvalues = { - 0: 'CRC_CUR_0', - 1: 'CRC_CUR_1', -} -CRC_CUR_0 = 0 -CRC_CUR_1 = 1 -CRC_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_STEREO_SEL' -CRC_STEREO_SEL__enumvalues = { - 0: 'CRC_STEREO_0', - 1: 'CRC_STEREO_1', - 2: 'CRC_STEREO_2', - 3: 'CRC_STEREO_3', -} -CRC_STEREO_0 = 0 -CRC_STEREO_1 = 1 -CRC_STEREO_2 = 2 -CRC_STEREO_3 = 3 -CRC_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_INTERLACE_SEL' -CRC_INTERLACE_SEL__enumvalues = { - 0: 'CRC_INTERLACE_0', - 1: 'CRC_INTERLACE_1', - 2: 'CRC_INTERLACE_2', - 3: 'CRC_INTERLACE_3', -} -CRC_INTERLACE_0 = 0 -CRC_INTERLACE_1 = 1 -CRC_INTERLACE_2 = 2 -CRC_INTERLACE_3 = 3 -CRC_INTERLACE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CVALUE_SEL' -PERFCOUNTER_CVALUE_SEL__enumvalues = { - 0: 'PERFCOUNTER_CVALUE_SEL_47_0', - 1: 'PERFCOUNTER_CVALUE_SEL_15_0', - 2: 'PERFCOUNTER_CVALUE_SEL_31_16', - 3: 'PERFCOUNTER_CVALUE_SEL_47_32', - 4: 'PERFCOUNTER_CVALUE_SEL_11_0', - 5: 'PERFCOUNTER_CVALUE_SEL_23_12', - 6: 'PERFCOUNTER_CVALUE_SEL_35_24', - 7: 'PERFCOUNTER_CVALUE_SEL_47_36', -} -PERFCOUNTER_CVALUE_SEL_47_0 = 0 -PERFCOUNTER_CVALUE_SEL_15_0 = 1 -PERFCOUNTER_CVALUE_SEL_31_16 = 2 -PERFCOUNTER_CVALUE_SEL_47_32 = 3 -PERFCOUNTER_CVALUE_SEL_11_0 = 4 -PERFCOUNTER_CVALUE_SEL_23_12 = 5 -PERFCOUNTER_CVALUE_SEL_35_24 = 6 -PERFCOUNTER_CVALUE_SEL_47_36 = 7 -PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INC_MODE' -PERFCOUNTER_INC_MODE__enumvalues = { - 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', - 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', - 2: 'PERFCOUNTER_INC_MODE_LSB', - 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', - 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', -} -PERFCOUNTER_INC_MODE_MULTI_BIT = 0 -PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 -PERFCOUNTER_INC_MODE_LSB = 2 -PERFCOUNTER_INC_MODE_POS_EDGE = 3 -PERFCOUNTER_INC_MODE_NEG_EDGE = 4 -PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' -PERFCOUNTER_HW_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', - 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', -} -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 -PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RUNEN_MODE' -PERFCOUNTER_RUNEN_MODE__enumvalues = { - 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', -} -PERFCOUNTER_RUNEN_MODE_LEVEL = 0 -PERFCOUNTER_RUNEN_MODE_EDGE = 1 -PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' -PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { - 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', - 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', -} -PERFCOUNTER_CNTOFF_START_ENABLE = 0 -PERFCOUNTER_CNTOFF_START_DISABLE = 1 -PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RESTART_EN' -PERFCOUNTER_RESTART_EN__enumvalues = { - 0: 'PERFCOUNTER_RESTART_DISABLE', - 1: 'PERFCOUNTER_RESTART_ENABLE', -} -PERFCOUNTER_RESTART_DISABLE = 0 -PERFCOUNTER_RESTART_ENABLE = 1 -PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_EN' -PERFCOUNTER_INT_EN__enumvalues = { - 0: 'PERFCOUNTER_INT_DISABLE', - 1: 'PERFCOUNTER_INT_ENABLE', -} -PERFCOUNTER_INT_DISABLE = 0 -PERFCOUNTER_INT_ENABLE = 1 -PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_OFF_MASK' -PERFCOUNTER_OFF_MASK__enumvalues = { - 0: 'PERFCOUNTER_OFF_MASK_DISABLE', - 1: 'PERFCOUNTER_OFF_MASK_ENABLE', -} -PERFCOUNTER_OFF_MASK_DISABLE = 0 -PERFCOUNTER_OFF_MASK_ENABLE = 1 -PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_ACTIVE' -PERFCOUNTER_ACTIVE__enumvalues = { - 0: 'PERFCOUNTER_IS_IDLE', - 1: 'PERFCOUNTER_IS_ACTIVE', -} -PERFCOUNTER_IS_IDLE = 0 -PERFCOUNTER_IS_ACTIVE = 1 -PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_TYPE' -PERFCOUNTER_INT_TYPE__enumvalues = { - 0: 'PERFCOUNTER_INT_TYPE_LEVEL', - 1: 'PERFCOUNTER_INT_TYPE_PULSE', -} -PERFCOUNTER_INT_TYPE_LEVEL = 0 -PERFCOUNTER_INT_TYPE_PULSE = 1 -PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' -PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { - 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', -} -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 -PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' -PERFCOUNTER_HW_STOP1_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP1_0', - 1: 'PERFCOUNTER_HW_STOP1_1', -} -PERFCOUNTER_HW_STOP1_0 = 0 -PERFCOUNTER_HW_STOP1_1 = 1 -PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' -PERFCOUNTER_HW_STOP2_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP2_0', - 1: 'PERFCOUNTER_HW_STOP2_1', -} -PERFCOUNTER_HW_STOP2_0 = 0 -PERFCOUNTER_HW_STOP2_1 = 1 -PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTL_SEL' -PERFCOUNTER_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_CNTL_SEL_0', - 1: 'PERFCOUNTER_CNTL_SEL_1', - 2: 'PERFCOUNTER_CNTL_SEL_2', - 3: 'PERFCOUNTER_CNTL_SEL_3', - 4: 'PERFCOUNTER_CNTL_SEL_4', - 5: 'PERFCOUNTER_CNTL_SEL_5', - 6: 'PERFCOUNTER_CNTL_SEL_6', - 7: 'PERFCOUNTER_CNTL_SEL_7', -} -PERFCOUNTER_CNTL_SEL_0 = 0 -PERFCOUNTER_CNTL_SEL_1 = 1 -PERFCOUNTER_CNTL_SEL_2 = 2 -PERFCOUNTER_CNTL_SEL_3 = 3 -PERFCOUNTER_CNTL_SEL_4 = 4 -PERFCOUNTER_CNTL_SEL_5 = 5 -PERFCOUNTER_CNTL_SEL_6 = 6 -PERFCOUNTER_CNTL_SEL_7 = 7 -PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT0_STATE' -PERFCOUNTER_CNT0_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT0_STATE_RESET', - 1: 'PERFCOUNTER_CNT0_STATE_START', - 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT0_STATE_HW', -} -PERFCOUNTER_CNT0_STATE_RESET = 0 -PERFCOUNTER_CNT0_STATE_START = 1 -PERFCOUNTER_CNT0_STATE_FREEZE = 2 -PERFCOUNTER_CNT0_STATE_HW = 3 -PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL0' -PERFCOUNTER_STATE_SEL0__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', -} -PERFCOUNTER_STATE_SEL0_GLOBAL = 0 -PERFCOUNTER_STATE_SEL0_LOCAL = 1 -PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT1_STATE' -PERFCOUNTER_CNT1_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT1_STATE_RESET', - 1: 'PERFCOUNTER_CNT1_STATE_START', - 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT1_STATE_HW', -} -PERFCOUNTER_CNT1_STATE_RESET = 0 -PERFCOUNTER_CNT1_STATE_START = 1 -PERFCOUNTER_CNT1_STATE_FREEZE = 2 -PERFCOUNTER_CNT1_STATE_HW = 3 -PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL1' -PERFCOUNTER_STATE_SEL1__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', -} -PERFCOUNTER_STATE_SEL1_GLOBAL = 0 -PERFCOUNTER_STATE_SEL1_LOCAL = 1 -PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT2_STATE' -PERFCOUNTER_CNT2_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT2_STATE_RESET', - 1: 'PERFCOUNTER_CNT2_STATE_START', - 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT2_STATE_HW', -} -PERFCOUNTER_CNT2_STATE_RESET = 0 -PERFCOUNTER_CNT2_STATE_START = 1 -PERFCOUNTER_CNT2_STATE_FREEZE = 2 -PERFCOUNTER_CNT2_STATE_HW = 3 -PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL2' -PERFCOUNTER_STATE_SEL2__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', -} -PERFCOUNTER_STATE_SEL2_GLOBAL = 0 -PERFCOUNTER_STATE_SEL2_LOCAL = 1 -PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT3_STATE' -PERFCOUNTER_CNT3_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT3_STATE_RESET', - 1: 'PERFCOUNTER_CNT3_STATE_START', - 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT3_STATE_HW', -} -PERFCOUNTER_CNT3_STATE_RESET = 0 -PERFCOUNTER_CNT3_STATE_START = 1 -PERFCOUNTER_CNT3_STATE_FREEZE = 2 -PERFCOUNTER_CNT3_STATE_HW = 3 -PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL3' -PERFCOUNTER_STATE_SEL3__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', -} -PERFCOUNTER_STATE_SEL3_GLOBAL = 0 -PERFCOUNTER_STATE_SEL3_LOCAL = 1 -PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT4_STATE' -PERFCOUNTER_CNT4_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT4_STATE_RESET', - 1: 'PERFCOUNTER_CNT4_STATE_START', - 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT4_STATE_HW', -} -PERFCOUNTER_CNT4_STATE_RESET = 0 -PERFCOUNTER_CNT4_STATE_START = 1 -PERFCOUNTER_CNT4_STATE_FREEZE = 2 -PERFCOUNTER_CNT4_STATE_HW = 3 -PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL4' -PERFCOUNTER_STATE_SEL4__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', -} -PERFCOUNTER_STATE_SEL4_GLOBAL = 0 -PERFCOUNTER_STATE_SEL4_LOCAL = 1 -PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT5_STATE' -PERFCOUNTER_CNT5_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT5_STATE_RESET', - 1: 'PERFCOUNTER_CNT5_STATE_START', - 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT5_STATE_HW', -} -PERFCOUNTER_CNT5_STATE_RESET = 0 -PERFCOUNTER_CNT5_STATE_START = 1 -PERFCOUNTER_CNT5_STATE_FREEZE = 2 -PERFCOUNTER_CNT5_STATE_HW = 3 -PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL5' -PERFCOUNTER_STATE_SEL5__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', -} -PERFCOUNTER_STATE_SEL5_GLOBAL = 0 -PERFCOUNTER_STATE_SEL5_LOCAL = 1 -PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT6_STATE' -PERFCOUNTER_CNT6_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT6_STATE_RESET', - 1: 'PERFCOUNTER_CNT6_STATE_START', - 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT6_STATE_HW', -} -PERFCOUNTER_CNT6_STATE_RESET = 0 -PERFCOUNTER_CNT6_STATE_START = 1 -PERFCOUNTER_CNT6_STATE_FREEZE = 2 -PERFCOUNTER_CNT6_STATE_HW = 3 -PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL6' -PERFCOUNTER_STATE_SEL6__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', -} -PERFCOUNTER_STATE_SEL6_GLOBAL = 0 -PERFCOUNTER_STATE_SEL6_LOCAL = 1 -PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT7_STATE' -PERFCOUNTER_CNT7_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT7_STATE_RESET', - 1: 'PERFCOUNTER_CNT7_STATE_START', - 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT7_STATE_HW', -} -PERFCOUNTER_CNT7_STATE_RESET = 0 -PERFCOUNTER_CNT7_STATE_START = 1 -PERFCOUNTER_CNT7_STATE_FREEZE = 2 -PERFCOUNTER_CNT7_STATE_HW = 3 -PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL7' -PERFCOUNTER_STATE_SEL7__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', -} -PERFCOUNTER_STATE_SEL7_GLOBAL = 0 -PERFCOUNTER_STATE_SEL7_LOCAL = 1 -PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_STATE' -PERFMON_STATE__enumvalues = { - 0: 'PERFMON_STATE_RESET', - 1: 'PERFMON_STATE_START', - 2: 'PERFMON_STATE_FREEZE', - 3: 'PERFMON_STATE_HW', -} -PERFMON_STATE_RESET = 0 -PERFMON_STATE_START = 1 -PERFMON_STATE_FREEZE = 2 -PERFMON_STATE_HW = 3 -PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_AND_OR' -PERFMON_CNTOFF_AND_OR__enumvalues = { - 0: 'PERFMON_CNTOFF_OR', - 1: 'PERFMON_CNTOFF_AND', -} -PERFMON_CNTOFF_OR = 0 -PERFMON_CNTOFF_AND = 1 -PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_EN' -PERFMON_CNTOFF_INT_EN__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_DISABLE', - 1: 'PERFMON_CNTOFF_INT_ENABLE', -} -PERFMON_CNTOFF_INT_DISABLE = 0 -PERFMON_CNTOFF_INT_ENABLE = 1 -PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' -PERFMON_CNTOFF_INT_TYPE__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', - 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', -} -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 -PERFMON_CNTOFF_INT_TYPE_PULSE = 1 -PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ROTATION_ANGLE' -ROTATION_ANGLE__enumvalues = { - 0: 'ROTATE_0_DEGREES', - 1: 'ROTATE_90_DEGREES', - 2: 'ROTATE_180_DEGREES', - 3: 'ROTATE_270_DEGREES', -} -ROTATE_0_DEGREES = 0 -ROTATE_90_DEGREES = 1 -ROTATE_180_DEGREES = 2 -ROTATE_270_DEGREES = 3 -ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'H_MIRROR_EN' -H_MIRROR_EN__enumvalues = { - 0: 'HW_MIRRORING_DISABLE', - 1: 'HW_MIRRORING_ENABLE', -} -HW_MIRRORING_DISABLE = 0 -HW_MIRRORING_ENABLE = 1 -H_MIRROR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_PIPES' -NUM_PIPES__enumvalues = { - 0: 'ONE_PIPE', - 1: 'TWO_PIPES', - 2: 'FOUR_PIPES', - 3: 'EIGHT_PIPES', - 4: 'SIXTEEN_PIPES', - 5: 'THIRTY_TWO_PIPES', - 6: 'SIXTY_FOUR_PIPES', -} -ONE_PIPE = 0 -TWO_PIPES = 1 -FOUR_PIPES = 2 -EIGHT_PIPES = 3 -SIXTEEN_PIPES = 4 -THIRTY_TWO_PIPES = 5 -SIXTY_FOUR_PIPES = 6 -NUM_PIPES = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_BANKS' -NUM_BANKS__enumvalues = { - 0: 'ONE_BANK', - 1: 'TWO_BANKS', - 2: 'FOUR_BANKS', - 3: 'EIGHT_BANKS', - 4: 'SIXTEEN_BANKS', -} -ONE_BANK = 0 -TWO_BANKS = 1 -FOUR_BANKS = 2 -EIGHT_BANKS = 3 -SIXTEEN_BANKS = 4 -NUM_BANKS = ctypes.c_uint32 # enum - -# values for enumeration 'SW_MODE' -SW_MODE__enumvalues = { - 0: 'SWIZZLE_LINEAR', - 5: 'SWIZZLE_4KB_S', - 6: 'SWIZZLE_4KB_D', - 9: 'SWIZZLE_64KB_S', - 10: 'SWIZZLE_64KB_D', - 13: 'SWIZZLE_VAR_S', - 14: 'SWIZZLE_VAR_D', - 17: 'SWIZZLE_64KB_S_T', - 18: 'SWIZZLE_64KB_D_T', - 21: 'SWIZZLE_4KB_S_X', - 22: 'SWIZZLE_4KB_D_X', - 25: 'SWIZZLE_64KB_S_X', - 26: 'SWIZZLE_64KB_D_X', - 27: 'SWIZZLE_64KB_R_X', - 29: 'SWIZZLE_VAR_S_X', - 30: 'SWIZZLE_VAR_D_X', -} -SWIZZLE_LINEAR = 0 -SWIZZLE_4KB_S = 5 -SWIZZLE_4KB_D = 6 -SWIZZLE_64KB_S = 9 -SWIZZLE_64KB_D = 10 -SWIZZLE_VAR_S = 13 -SWIZZLE_VAR_D = 14 -SWIZZLE_64KB_S_T = 17 -SWIZZLE_64KB_D_T = 18 -SWIZZLE_4KB_S_X = 21 -SWIZZLE_4KB_D_X = 22 -SWIZZLE_64KB_S_X = 25 -SWIZZLE_64KB_D_X = 26 -SWIZZLE_64KB_R_X = 27 -SWIZZLE_VAR_S_X = 29 -SWIZZLE_VAR_D_X = 30 -SW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INTERLEAVE' -PIPE_INTERLEAVE__enumvalues = { - 0: 'PIPE_INTERLEAVE_256B', - 1: 'PIPE_INTERLEAVE_512B', - 2: 'PIPE_INTERLEAVE_1KB', -} -PIPE_INTERLEAVE_256B = 0 -PIPE_INTERLEAVE_512B = 1 -PIPE_INTERLEAVE_1KB = 2 -PIPE_INTERLEAVE = ctypes.c_uint32 # enum - -# values for enumeration 'LEGACY_PIPE_INTERLEAVE' -LEGACY_PIPE_INTERLEAVE__enumvalues = { - 0: 'LEGACY_PIPE_INTERLEAVE_256B', - 1: 'LEGACY_PIPE_INTERLEAVE_512B', -} -LEGACY_PIPE_INTERLEAVE_256B = 0 -LEGACY_PIPE_INTERLEAVE_512B = 1 -LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_SE' -NUM_SE__enumvalues = { - 0: 'ONE_SHADER_ENGIN', - 1: 'TWO_SHADER_ENGINS', - 2: 'FOUR_SHADER_ENGINS', - 3: 'EIGHT_SHADER_ENGINS', -} -ONE_SHADER_ENGIN = 0 -TWO_SHADER_ENGINS = 1 -FOUR_SHADER_ENGINS = 2 -EIGHT_SHADER_ENGINS = 3 -NUM_SE = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_RB_PER_SE' -NUM_RB_PER_SE__enumvalues = { - 0: 'ONE_RB_PER_SE', - 1: 'TWO_RB_PER_SE', - 2: 'FOUR_RB_PER_SE', -} -ONE_RB_PER_SE = 0 -TWO_RB_PER_SE = 1 -FOUR_RB_PER_SE = 2 -NUM_RB_PER_SE = ctypes.c_uint32 # enum - -# values for enumeration 'MAX_COMPRESSED_FRAGS' -MAX_COMPRESSED_FRAGS__enumvalues = { - 0: 'ONE_FRAGMENT', - 1: 'TWO_FRAGMENTS', - 2: 'FOUR_FRAGMENTS', - 3: 'EIGHT_FRAGMENTS', -} -ONE_FRAGMENT = 0 -TWO_FRAGMENTS = 1 -FOUR_FRAGMENTS = 2 -EIGHT_FRAGMENTS = 3 -MAX_COMPRESSED_FRAGS = ctypes.c_uint32 # enum - -# values for enumeration 'DIM_TYPE' -DIM_TYPE__enumvalues = { - 0: 'DIM_TYPE_1D', - 1: 'DIM_TYPE_2D', - 2: 'DIM_TYPE_3D', - 3: 'DIM_TYPE_RESERVED', -} -DIM_TYPE_1D = 0 -DIM_TYPE_2D = 1 -DIM_TYPE_3D = 2 -DIM_TYPE_RESERVED = 3 -DIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'META_LINEAR' -META_LINEAR__enumvalues = { - 0: 'META_SURF_TILED', - 1: 'META_SURF_LINEAR', -} -META_SURF_TILED = 0 -META_SURF_LINEAR = 1 -META_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'RB_ALIGNED' -RB_ALIGNED__enumvalues = { - 0: 'RB_UNALIGNED_META_SURF', - 1: 'RB_ALIGNED_META_SURF', -} -RB_UNALIGNED_META_SURF = 0 -RB_ALIGNED_META_SURF = 1 -RB_ALIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_ALIGNED' -PIPE_ALIGNED__enumvalues = { - 0: 'PIPE_UNALIGNED_SURF', - 1: 'PIPE_ALIGNED_SURF', -} -PIPE_UNALIGNED_SURF = 0 -PIPE_ALIGNED_SURF = 1 -PIPE_ALIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'ARRAY_MODE' -ARRAY_MODE__enumvalues = { - 0: 'AM_LINEAR_GENERAL', - 1: 'AM_LINEAR_ALIGNED', - 2: 'AM_1D_TILED_THIN1', - 3: 'AM_1D_TILED_THICK', - 4: 'AM_2D_TILED_THIN1', - 5: 'AM_PRT_TILED_THIN1', - 6: 'AM_PRT_2D_TILED_THIN1', - 7: 'AM_2D_TILED_THICK', - 8: 'AM_2D_TILED_XTHICK', - 9: 'AM_PRT_TILED_THICK', - 10: 'AM_PRT_2D_TILED_THICK', - 11: 'AM_PRT_3D_TILED_THIN1', - 12: 'AM_3D_TILED_THIN1', - 13: 'AM_3D_TILED_THICK', - 14: 'AM_3D_TILED_XTHICK', - 15: 'AM_PRT_3D_TILED_THICK', -} -AM_LINEAR_GENERAL = 0 -AM_LINEAR_ALIGNED = 1 -AM_1D_TILED_THIN1 = 2 -AM_1D_TILED_THICK = 3 -AM_2D_TILED_THIN1 = 4 -AM_PRT_TILED_THIN1 = 5 -AM_PRT_2D_TILED_THIN1 = 6 -AM_2D_TILED_THICK = 7 -AM_2D_TILED_XTHICK = 8 -AM_PRT_TILED_THICK = 9 -AM_PRT_2D_TILED_THICK = 10 -AM_PRT_3D_TILED_THIN1 = 11 -AM_3D_TILED_THIN1 = 12 -AM_3D_TILED_THICK = 13 -AM_3D_TILED_XTHICK = 14 -AM_PRT_3D_TILED_THICK = 15 -ARRAY_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_CONFIG' -PIPE_CONFIG__enumvalues = { - 0: 'P2', - 4: 'P4_8x16', - 5: 'P4_16x16', - 6: 'P4_16x32', - 7: 'P4_32x32', - 8: 'P8_16x16_8x16', - 9: 'P8_16x32_8x16', - 10: 'P8_32x32_8x16', - 11: 'P8_16x32_16x16', - 12: 'P8_32x32_16x16', - 13: 'P8_32x32_16x32', - 14: 'P8_32x64_32x32', - 16: 'P16_32x32_8x16', - 17: 'P16_32x32_16x16', - 18: 'P16_ADDR_SURF', -} -P2 = 0 -P4_8x16 = 4 -P4_16x16 = 5 -P4_16x32 = 6 -P4_32x32 = 7 -P8_16x16_8x16 = 8 -P8_16x32_8x16 = 9 -P8_32x32_8x16 = 10 -P8_16x32_16x16 = 11 -P8_32x32_16x16 = 12 -P8_32x32_16x32 = 13 -P8_32x64_32x32 = 14 -P16_32x32_8x16 = 16 -P16_32x32_16x16 = 17 -P16_ADDR_SURF = 18 -PIPE_CONFIG = ctypes.c_uint32 # enum - -# values for enumeration 'MICRO_TILE_MODE_NEW' -MICRO_TILE_MODE_NEW__enumvalues = { - 0: 'DISPLAY_MICRO_TILING', - 1: 'THIN_MICRO_TILING', - 2: 'DEPTH_MICRO_TILING', - 3: 'ROTATED_MICRO_TILING', - 4: 'THICK_MICRO_TILING', -} -DISPLAY_MICRO_TILING = 0 -THIN_MICRO_TILING = 1 -DEPTH_MICRO_TILING = 2 -ROTATED_MICRO_TILING = 3 -THICK_MICRO_TILING = 4 -MICRO_TILE_MODE_NEW = ctypes.c_uint32 # enum - -# values for enumeration 'TILE_SPLIT' -TILE_SPLIT__enumvalues = { - 0: 'SURF_TILE_SPLIT_64B', - 1: 'SURF_TILE_SPLIT_128B', - 2: 'SURF_TILE_SPLIT_256B', - 3: 'SURF_TILE_SPLIT_512B', - 4: 'SURF_TILE_SPLIT_1KB', - 5: 'SURF_TILE_SPLIT_2KB', - 6: 'SURF_TILE_SPLIT_4KB', -} -SURF_TILE_SPLIT_64B = 0 -SURF_TILE_SPLIT_128B = 1 -SURF_TILE_SPLIT_256B = 2 -SURF_TILE_SPLIT_512B = 3 -SURF_TILE_SPLIT_1KB = 4 -SURF_TILE_SPLIT_2KB = 5 -SURF_TILE_SPLIT_4KB = 6 -TILE_SPLIT = ctypes.c_uint32 # enum - -# values for enumeration 'BANK_WIDTH' -BANK_WIDTH__enumvalues = { - 0: 'SURF_BANK_WIDTH_1', - 1: 'SURF_BANK_WIDTH_2', - 2: 'SURF_BANK_WIDTH_4', - 3: 'SURF_BANK_WIDTH_8', -} -SURF_BANK_WIDTH_1 = 0 -SURF_BANK_WIDTH_2 = 1 -SURF_BANK_WIDTH_4 = 2 -SURF_BANK_WIDTH_8 = 3 -BANK_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'BANK_HEIGHT' -BANK_HEIGHT__enumvalues = { - 0: 'SURF_BANK_HEIGHT_1', - 1: 'SURF_BANK_HEIGHT_2', - 2: 'SURF_BANK_HEIGHT_4', - 3: 'SURF_BANK_HEIGHT_8', -} -SURF_BANK_HEIGHT_1 = 0 -SURF_BANK_HEIGHT_2 = 1 -SURF_BANK_HEIGHT_4 = 2 -SURF_BANK_HEIGHT_8 = 3 -BANK_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'MACRO_TILE_ASPECT' -MACRO_TILE_ASPECT__enumvalues = { - 0: 'SURF_MACRO_ASPECT_1', - 1: 'SURF_MACRO_ASPECT_2', - 2: 'SURF_MACRO_ASPECT_4', - 3: 'SURF_MACRO_ASPECT_8', -} -SURF_MACRO_ASPECT_1 = 0 -SURF_MACRO_ASPECT_2 = 1 -SURF_MACRO_ASPECT_4 = 2 -SURF_MACRO_ASPECT_8 = 3 -MACRO_TILE_ASPECT = ctypes.c_uint32 # enum - -# values for enumeration 'LEGACY_NUM_BANKS' -LEGACY_NUM_BANKS__enumvalues = { - 0: 'SURF_2_BANK', - 1: 'SURF_4_BANK', - 2: 'SURF_8_BANK', - 3: 'SURF_16_BANK', -} -SURF_2_BANK = 0 -SURF_4_BANK = 1 -SURF_8_BANK = 2 -SURF_16_BANK = 3 -LEGACY_NUM_BANKS = ctypes.c_uint32 # enum - -# values for enumeration 'SWATH_HEIGHT' -SWATH_HEIGHT__enumvalues = { - 0: 'SWATH_HEIGHT_1L', - 1: 'SWATH_HEIGHT_2L', - 2: 'SWATH_HEIGHT_4L', - 3: 'SWATH_HEIGHT_8L', - 4: 'SWATH_HEIGHT_16L', -} -SWATH_HEIGHT_1L = 0 -SWATH_HEIGHT_2L = 1 -SWATH_HEIGHT_4L = 2 -SWATH_HEIGHT_8L = 3 -SWATH_HEIGHT_16L = 4 -SWATH_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' -PTE_ROW_HEIGHT_LINEAR__enumvalues = { - 0: 'PTE_ROW_HEIGHT_LINEAR_8L', - 1: 'PTE_ROW_HEIGHT_LINEAR_16L', - 2: 'PTE_ROW_HEIGHT_LINEAR_32L', - 3: 'PTE_ROW_HEIGHT_LINEAR_64L', - 4: 'PTE_ROW_HEIGHT_LINEAR_128L', - 5: 'PTE_ROW_HEIGHT_LINEAR_256L', - 6: 'PTE_ROW_HEIGHT_LINEAR_512L', - 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', -} -PTE_ROW_HEIGHT_LINEAR_8L = 0 -PTE_ROW_HEIGHT_LINEAR_16L = 1 -PTE_ROW_HEIGHT_LINEAR_32L = 2 -PTE_ROW_HEIGHT_LINEAR_64L = 3 -PTE_ROW_HEIGHT_LINEAR_128L = 4 -PTE_ROW_HEIGHT_LINEAR_256L = 5 -PTE_ROW_HEIGHT_LINEAR_512L = 6 -PTE_ROW_HEIGHT_LINEAR_1024L = 7 -PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CHUNK_SIZE' -CHUNK_SIZE__enumvalues = { - 0: 'CHUNK_SIZE_1KB', - 1: 'CHUNK_SIZE_2KB', - 2: 'CHUNK_SIZE_4KB', - 3: 'CHUNK_SIZE_8KB', - 4: 'CHUNK_SIZE_16KB', - 5: 'CHUNK_SIZE_32KB', - 6: 'CHUNK_SIZE_64KB', -} -CHUNK_SIZE_1KB = 0 -CHUNK_SIZE_2KB = 1 -CHUNK_SIZE_4KB = 2 -CHUNK_SIZE_8KB = 3 -CHUNK_SIZE_16KB = 4 -CHUNK_SIZE_32KB = 5 -CHUNK_SIZE_64KB = 6 -CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_CHUNK_SIZE' -MIN_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_CHUNK_SIZE', - 1: 'MIN_CHUNK_SIZE_256B', - 2: 'MIN_CHUNK_SIZE_512B', - 3: 'MIN_CHUNK_SIZE_1024B', -} -NO_MIN_CHUNK_SIZE = 0 -MIN_CHUNK_SIZE_256B = 1 -MIN_CHUNK_SIZE_512B = 2 -MIN_CHUNK_SIZE_1024B = 3 -MIN_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'META_CHUNK_SIZE' -META_CHUNK_SIZE__enumvalues = { - 0: 'META_CHUNK_SIZE_1KB', - 1: 'META_CHUNK_SIZE_2KB', - 2: 'META_CHUNK_SIZE_4KB', - 3: 'META_CHUNK_SIZE_8KB', -} -META_CHUNK_SIZE_1KB = 0 -META_CHUNK_SIZE_2KB = 1 -META_CHUNK_SIZE_4KB = 2 -META_CHUNK_SIZE_8KB = 3 -META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_META_CHUNK_SIZE' -MIN_META_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_META_CHUNK_SIZE', - 1: 'MIN_META_CHUNK_SIZE_64B', - 2: 'MIN_META_CHUNK_SIZE_128B', - 3: 'MIN_META_CHUNK_SIZE_256B', -} -NO_MIN_META_CHUNK_SIZE = 0 -MIN_META_CHUNK_SIZE_64B = 1 -MIN_META_CHUNK_SIZE_128B = 2 -MIN_META_CHUNK_SIZE_256B = 3 -MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DPTE_GROUP_SIZE' -DPTE_GROUP_SIZE__enumvalues = { - 0: 'DPTE_GROUP_SIZE_64B', - 1: 'DPTE_GROUP_SIZE_128B', - 2: 'DPTE_GROUP_SIZE_256B', - 3: 'DPTE_GROUP_SIZE_512B', - 4: 'DPTE_GROUP_SIZE_1024B', - 5: 'DPTE_GROUP_SIZE_2048B', - 6: 'DPTE_GROUP_SIZE_4096B', - 7: 'DPTE_GROUP_SIZE_8192B', -} -DPTE_GROUP_SIZE_64B = 0 -DPTE_GROUP_SIZE_128B = 1 -DPTE_GROUP_SIZE_256B = 2 -DPTE_GROUP_SIZE_512B = 3 -DPTE_GROUP_SIZE_1024B = 4 -DPTE_GROUP_SIZE_2048B = 5 -DPTE_GROUP_SIZE_4096B = 6 -DPTE_GROUP_SIZE_8192B = 7 -DPTE_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MPTE_GROUP_SIZE' -MPTE_GROUP_SIZE__enumvalues = { - 0: 'MPTE_GROUP_SIZE_64B', - 1: 'MPTE_GROUP_SIZE_128B', - 2: 'MPTE_GROUP_SIZE_256B', - 3: 'MPTE_GROUP_SIZE_512B', - 4: 'MPTE_GROUP_SIZE_1024B', - 5: 'MPTE_GROUP_SIZE_2048B', - 6: 'MPTE_GROUP_SIZE_4096B', - 7: 'MPTE_GROUP_SIZE_8192B', -} -MPTE_GROUP_SIZE_64B = 0 -MPTE_GROUP_SIZE_128B = 1 -MPTE_GROUP_SIZE_256B = 2 -MPTE_GROUP_SIZE_512B = 3 -MPTE_GROUP_SIZE_1024B = 4 -MPTE_GROUP_SIZE_2048B = 5 -MPTE_GROUP_SIZE_4096B = 6 -MPTE_GROUP_SIZE_8192B = 7 -MPTE_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_BLANK_EN' -HUBP_BLANK_EN__enumvalues = { - 0: 'HUBP_BLANK_SW_DEASSERT', - 1: 'HUBP_BLANK_SW_ASSERT', -} -HUBP_BLANK_SW_DEASSERT = 0 -HUBP_BLANK_SW_ASSERT = 1 -HUBP_BLANK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_DISABLE' -HUBP_DISABLE__enumvalues = { - 0: 'HUBP_ENABLED', - 1: 'HUBP_DISABLED', -} -HUBP_ENABLED = 0 -HUBP_DISABLED = 1 -HUBP_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_TTU_DISABLE' -HUBP_TTU_DISABLE__enumvalues = { - 0: 'HUBP_TTU_ENABLED', - 1: 'HUBP_TTU_DISABLED', -} -HUBP_TTU_ENABLED = 0 -HUBP_TTU_DISABLED = 1 -HUBP_TTU_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' -HUBP_NO_OUTSTANDING_REQ__enumvalues = { - 0: 'OUTSTANDING_REQ', - 1: 'NO_OUTSTANDING_REQ', -} -OUTSTANDING_REQ = 0 -NO_OUTSTANDING_REQ = 1 -HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_IN_BLANK' -HUBP_IN_BLANK__enumvalues = { - 0: 'HUBP_IN_ACTIVE', - 1: 'HUBP_IN_VBLANK', -} -HUBP_IN_ACTIVE = 0 -HUBP_IN_VBLANK = 1 -HUBP_IN_BLANK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VTG_SEL' -HUBP_VTG_SEL__enumvalues = { - 0: 'VTG_SEL_0', - 1: 'VTG_SEL_1', - 2: 'VTG_SEL_2', - 3: 'VTG_SEL_3', - 4: 'VTG_SEL_4', - 5: 'VTG_SEL_5', -} -VTG_SEL_0 = 0 -VTG_SEL_1 = 1 -VTG_SEL_2 = 2 -VTG_SEL_3 = 3 -VTG_SEL_4 = 4 -VTG_SEL_5 = 5 -HUBP_VTG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' -HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { - 0: 'VREADY_BEFORE_VSYNC', - 1: 'VREADY_AT_OR_AFTER_VSYNC', -} -VREADY_BEFORE_VSYNC = 0 -VREADY_AT_OR_AFTER_VSYNC = 1 -HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'VMPG_SIZE' -VMPG_SIZE__enumvalues = { - 0: 'VMPG_SIZE_4KB', - 1: 'VMPG_SIZE_64KB', -} -VMPG_SIZE_4KB = 0 -VMPG_SIZE_64KB = 1 -VMPG_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' -HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { - 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', -} -HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 -HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 -HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 -HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 -HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_TMZ' -SURFACE_TMZ__enumvalues = { - 0: 'SURFACE_IS_NOT_TMZ', - 1: 'SURFACE_IS_TMZ', -} -SURFACE_IS_NOT_TMZ = 0 -SURFACE_IS_TMZ = 1 -SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC' -SURFACE_DCC__enumvalues = { - 0: 'SURFACE_IS_NOT_DCC', - 1: 'SURFACE_IS_DCC', -} -SURFACE_IS_NOT_DCC = 0 -SURFACE_IS_DCC = 1 -SURFACE_DCC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_64B' -SURFACE_DCC_IND_64B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_64B', - 1: 'SURFACE_DCC_IS_IND_64B', -} -SURFACE_DCC_IS_NOT_IND_64B = 0 -SURFACE_DCC_IS_IND_64B = 1 -SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_TYPE' -SURFACE_FLIP_TYPE__enumvalues = { - 0: 'SURFACE_V_FLIP', - 1: 'SURFACE_I_FLIP', -} -SURFACE_V_FLIP = 0 -SURFACE_I_FLIP = 1 -SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' -SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { - 0: 'FLIP_ANY_FRAME', - 1: 'FLIP_LEFT_EYE', - 2: 'FLIP_RIGHT_EYE', - 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', -} -FLIP_ANY_FRAME = 0 -FLIP_LEFT_EYE = 1 -FLIP_RIGHT_EYE = 2 -SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 -SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_UPDATE_LOCK' -SURFACE_UPDATE_LOCK__enumvalues = { - 0: 'SURFACE_UPDATE_IS_UNLOCKED', - 1: 'SURFACE_UPDATE_IS_LOCKED', -} -SURFACE_UPDATE_IS_UNLOCKED = 0 -SURFACE_UPDATE_IS_LOCKED = 1 -SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' -SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { - 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', -} -SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 -SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 -SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' -SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', -} -SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 -SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 -SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' -SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', -} -SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 -SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 -SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' -SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { - 0: 'SURFACE_INUSE_IS_LATCHED', - 1: 'SURFACE_INUSE_IS_NOT_LATCHED', -} -SURFACE_INUSE_IS_LATCHED = 0 -SURFACE_INUSE_IS_NOT_LATCHED = 1 -SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum - -# values for enumeration 'INT_MASK' -INT_MASK__enumvalues = { - 0: 'INT_DISABLED', - 1: 'INT_ENABLED', -} -INT_DISABLED = 0 -INT_ENABLED = 1 -INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_INT_TYPE' -SURFACE_FLIP_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_INT_LEVEL', - 1: 'SURFACE_FLIP_INT_PULSE', -} -SURFACE_FLIP_INT_LEVEL = 0 -SURFACE_FLIP_INT_PULSE = 1 -SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' -SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', - 1: 'SURFACE_FLIP_AWAY_INT_PULSE', -} -SURFACE_FLIP_AWAY_INT_LEVEL = 0 -SURFACE_FLIP_AWAY_INT_PULSE = 1 -SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' -SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { - 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', - 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', -} -SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 -SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 -SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 -SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 -SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 -SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 -SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 -SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 -SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 -SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 -SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 -SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 -SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 -SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 -SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 -SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 -SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_SIZE' -DFQ_SIZE__enumvalues = { - 0: 'DFQ_SIZE_0', - 1: 'DFQ_SIZE_1', - 2: 'DFQ_SIZE_2', - 3: 'DFQ_SIZE_3', - 4: 'DFQ_SIZE_4', - 5: 'DFQ_SIZE_5', - 6: 'DFQ_SIZE_6', - 7: 'DFQ_SIZE_7', -} -DFQ_SIZE_0 = 0 -DFQ_SIZE_1 = 1 -DFQ_SIZE_2 = 2 -DFQ_SIZE_3 = 3 -DFQ_SIZE_4 = 4 -DFQ_SIZE_5 = 5 -DFQ_SIZE_6 = 6 -DFQ_SIZE_7 = 7 -DFQ_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_MIN_FREE_ENTRIES' -DFQ_MIN_FREE_ENTRIES__enumvalues = { - 0: 'DFQ_MIN_FREE_ENTRIES_0', - 1: 'DFQ_MIN_FREE_ENTRIES_1', - 2: 'DFQ_MIN_FREE_ENTRIES_2', - 3: 'DFQ_MIN_FREE_ENTRIES_3', - 4: 'DFQ_MIN_FREE_ENTRIES_4', - 5: 'DFQ_MIN_FREE_ENTRIES_5', - 6: 'DFQ_MIN_FREE_ENTRIES_6', - 7: 'DFQ_MIN_FREE_ENTRIES_7', -} -DFQ_MIN_FREE_ENTRIES_0 = 0 -DFQ_MIN_FREE_ENTRIES_1 = 1 -DFQ_MIN_FREE_ENTRIES_2 = 2 -DFQ_MIN_FREE_ENTRIES_3 = 3 -DFQ_MIN_FREE_ENTRIES_4 = 4 -DFQ_MIN_FREE_ENTRIES_5 = 5 -DFQ_MIN_FREE_ENTRIES_6 = 6 -DFQ_MIN_FREE_ENTRIES_7 = 7 -DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_NUM_ENTRIES' -DFQ_NUM_ENTRIES__enumvalues = { - 0: 'DFQ_NUM_ENTRIES_0', - 1: 'DFQ_NUM_ENTRIES_1', - 2: 'DFQ_NUM_ENTRIES_2', - 3: 'DFQ_NUM_ENTRIES_3', - 4: 'DFQ_NUM_ENTRIES_4', - 5: 'DFQ_NUM_ENTRIES_5', - 6: 'DFQ_NUM_ENTRIES_6', - 7: 'DFQ_NUM_ENTRIES_7', - 8: 'DFQ_NUM_ENTRIES_8', -} -DFQ_NUM_ENTRIES_0 = 0 -DFQ_NUM_ENTRIES_1 = 1 -DFQ_NUM_ENTRIES_2 = 2 -DFQ_NUM_ENTRIES_3 = 3 -DFQ_NUM_ENTRIES_4 = 4 -DFQ_NUM_ENTRIES_5 = 5 -DFQ_NUM_ENTRIES_6 = 6 -DFQ_NUM_ENTRIES_7 = 7 -DFQ_NUM_ENTRIES_8 = 8 -DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'FLIP_RATE' -FLIP_RATE__enumvalues = { - 0: 'FLIP_RATE_0', - 1: 'FLIP_RATE_1', - 2: 'FLIP_RATE_2', - 3: 'FLIP_RATE_3', - 4: 'FLIP_RATE_4', - 5: 'FLIP_RATE_5', - 6: 'FLIP_RATE_6', - 7: 'FLIP_RATE_7', -} -FLIP_RATE_0 = 0 -FLIP_RATE_1 = 1 -FLIP_RATE_2 = 2 -FLIP_RATE_3 = 3 -FLIP_RATE_4 = 4 -FLIP_RATE_5 = 5 -FLIP_RATE_6 = 6 -FLIP_RATE_7 = 7 -FLIP_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' -DETILE_BUFFER_PACKER_ENABLE__enumvalues = { - 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', - 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', -} -DETILE_BUFFER_PACKER_IS_DISABLE = 0 -DETILE_BUFFER_PACKER_IS_ENABLE = 1 -DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_ALPHA' -CROSSBAR_FOR_ALPHA__enumvalues = { - 0: 'ALPHA_DATA_ON_ALPHA_PORT', - 1: 'ALPHA_DATA_ON_Y_G_PORT', - 2: 'ALPHA_DATA_ON_CB_B_PORT', - 3: 'ALPHA_DATA_ON_CR_R_PORT', -} -ALPHA_DATA_ON_ALPHA_PORT = 0 -ALPHA_DATA_ON_Y_G_PORT = 1 -ALPHA_DATA_ON_CB_B_PORT = 2 -ALPHA_DATA_ON_CR_R_PORT = 3 -CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_Y_G' -CROSSBAR_FOR_Y_G__enumvalues = { - 0: 'Y_G_DATA_ON_ALPHA_PORT', - 1: 'Y_G_DATA_ON_Y_G_PORT', - 2: 'Y_G_DATA_ON_CB_B_PORT', - 3: 'Y_G_DATA_ON_CR_R_PORT', -} -Y_G_DATA_ON_ALPHA_PORT = 0 -Y_G_DATA_ON_Y_G_PORT = 1 -Y_G_DATA_ON_CB_B_PORT = 2 -Y_G_DATA_ON_CR_R_PORT = 3 -CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CB_B' -CROSSBAR_FOR_CB_B__enumvalues = { - 0: 'CB_B_DATA_ON_ALPHA_PORT', - 1: 'CB_B_DATA_ON_Y_G_PORT', - 2: 'CB_B_DATA_ON_CB_B_PORT', - 3: 'CB_B_DATA_ON_CR_R_PORT', -} -CB_B_DATA_ON_ALPHA_PORT = 0 -CB_B_DATA_ON_Y_G_PORT = 1 -CB_B_DATA_ON_CB_B_PORT = 2 -CB_B_DATA_ON_CR_R_PORT = 3 -CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CR_R' -CROSSBAR_FOR_CR_R__enumvalues = { - 0: 'CR_R_DATA_ON_ALPHA_PORT', - 1: 'CR_R_DATA_ON_Y_G_PORT', - 2: 'CR_R_DATA_ON_CB_B_PORT', - 3: 'CR_R_DATA_ON_CR_R_PORT', -} -CR_R_DATA_ON_ALPHA_PORT = 0 -CR_R_DATA_ON_Y_G_PORT = 1 -CR_R_DATA_ON_CB_B_PORT = 2 -CR_R_DATA_ON_CR_R_PORT = 3 -CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum - -# values for enumeration 'DET_MEM_PWR_LIGHT_SLEEP_MODE' -DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', -} -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_ENABLE' -CURSOR_ENABLE__enumvalues = { - 0: 'CURSOR_IS_DISABLE', - 1: 'CURSOR_IS_ENABLE', -} -CURSOR_IS_DISABLE = 0 -CURSOR_IS_ENABLE = 1 -CURSOR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_2X_MAGNIFY' -CURSOR_2X_MAGNIFY__enumvalues = { - 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', - 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', -} -CURSOR_2X_MAGNIFY_IS_DISABLE = 0 -CURSOR_2X_MAGNIFY_IS_ENABLE = 1 -CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_MODE' -CURSOR_MODE__enumvalues = { - 0: 'CURSOR_MONO_2BIT', - 1: 'CURSOR_COLOR_24BIT_1BIT_AND', - 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', - 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', -} -CURSOR_MONO_2BIT = 0 -CURSOR_COLOR_24BIT_1BIT_AND = 1 -CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -CURSOR_COLOR_64BIT_FP_PREMULT = 4 -CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 -CURSOR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SURFACE_TMZ' -CURSOR_SURFACE_TMZ__enumvalues = { - 0: 'CURSOR_SURFACE_IS_NOT_TMZ', - 1: 'CURSOR_SURFACE_IS_TMZ', -} -CURSOR_SURFACE_IS_NOT_TMZ = 0 -CURSOR_SURFACE_IS_TMZ = 1 -CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SNOOP' -CURSOR_SNOOP__enumvalues = { - 0: 'CURSOR_IS_NOT_SNOOP', - 1: 'CURSOR_IS_SNOOP', -} -CURSOR_IS_NOT_SNOOP = 0 -CURSOR_IS_SNOOP = 1 -CURSOR_SNOOP = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SYSTEM' -CURSOR_SYSTEM__enumvalues = { - 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', - 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', -} -CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 -CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 -CURSOR_SYSTEM = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PITCH' -CURSOR_PITCH__enumvalues = { - 0: 'CURSOR_PITCH_64_PIXELS', - 1: 'CURSOR_PITCH_128_PIXELS', - 2: 'CURSOR_PITCH_256_PIXELS', -} -CURSOR_PITCH_64_PIXELS = 0 -CURSOR_PITCH_128_PIXELS = 1 -CURSOR_PITCH_256_PIXELS = 2 -CURSOR_PITCH = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_LINES_PER_CHUNK' -CURSOR_LINES_PER_CHUNK__enumvalues = { - 0: 'CURSOR_LINE_PER_CHUNK_1', - 1: 'CURSOR_LINE_PER_CHUNK_2', - 2: 'CURSOR_LINE_PER_CHUNK_4', - 3: 'CURSOR_LINE_PER_CHUNK_8', - 4: 'CURSOR_LINE_PER_CHUNK_16', -} -CURSOR_LINE_PER_CHUNK_1 = 0 -CURSOR_LINE_PER_CHUNK_2 = 1 -CURSOR_LINE_PER_CHUNK_4 = 2 -CURSOR_LINE_PER_CHUNK_8 = 3 -CURSOR_LINE_PER_CHUNK_16 = 4 -CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' -CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', -} -CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 -CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 -CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' -CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', -} -CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 -CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 -CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_STEREO_EN' -CURSOR_STEREO_EN__enumvalues = { - 0: 'CURSOR_STEREO_IS_DISABLED', - 1: 'CURSOR_STEREO_IS_ENABLED', -} -CURSOR_STEREO_IS_DISABLED = 0 -CURSOR_STEREO_IS_ENABLED = 1 -CURSOR_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { - 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', -} -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' -CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UPDATED' -DMDATA_UPDATED__enumvalues = { - 0: 'DMDATA_NOT_UPDATED', - 1: 'DMDATA_WAS_UPDATED', -} -DMDATA_NOT_UPDATED = 0 -DMDATA_WAS_UPDATED = 1 -DMDATA_UPDATED = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_REPEAT' -DMDATA_REPEAT__enumvalues = { - 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', - 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', -} -DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 -DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 -DMDATA_REPEAT = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_MODE' -DMDATA_MODE__enumvalues = { - 0: 'DMDATA_SOFTWARE_UPDATE_MODE', - 1: 'DMDATA_HARDWARE_UPDATE_MODE', -} -DMDATA_SOFTWARE_UPDATE_MODE = 0 -DMDATA_HARDWARE_UPDATE_MODE = 1 -DMDATA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_QOS_MODE' -DMDATA_QOS_MODE__enumvalues = { - 0: 'DMDATA_QOS_LEVEL_FROM_TTU', - 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', -} -DMDATA_QOS_LEVEL_FROM_TTU = 0 -DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 -DMDATA_QOS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_DONE' -DMDATA_DONE__enumvalues = { - 0: 'DMDATA_NOT_SENT_TO_DIG', - 1: 'DMDATA_SENT_TO_DIG', -} -DMDATA_NOT_SENT_TO_DIG = 0 -DMDATA_SENT_TO_DIG = 1 -DMDATA_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW' -DMDATA_UNDERFLOW__enumvalues = { - 0: 'DMDATA_NOT_UNDERFLOW', - 1: 'DMDATA_UNDERFLOWED', -} -DMDATA_NOT_UNDERFLOW = 0 -DMDATA_UNDERFLOWED = 1 -DMDATA_UNDERFLOW = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' -DMDATA_UNDERFLOW_CLEAR__enumvalues = { - 0: 'DMDATA_DONT_CLEAR', - 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', -} -DMDATA_DONT_CLEAR = 0 -DMDATA_CLEAR_UNDERFLOW_STATUS = 1 -DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_XFC_PIXEL_FORMAT_ENUM' -HUBP_XFC_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'HUBP_XFC_PIXEL_IS_32BPP', - 1: 'HUBP_XFC_PIXEL_IS_64BPP', -} -HUBP_XFC_PIXEL_IS_32BPP = 0 -HUBP_XFC_PIXEL_IS_64BPP = 1 -HUBP_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_XFC_FRAME_MODE_ENUM' -HUBP_XFC_FRAME_MODE_ENUM__enumvalues = { - 0: 'HUBP_XFC_PARTIAL_FRAME_MODE', - 1: 'HUBP_XFC_FULL_FRAME_MODE', -} -HUBP_XFC_PARTIAL_FRAME_MODE = 0 -HUBP_XFC_FULL_FRAME_MODE = 1 -HUBP_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_XFC_CHUNK_SIZE_ENUM' -HUBP_XFC_CHUNK_SIZE_ENUM__enumvalues = { - 0: 'HUBP_XFC_CHUNK_SIZE_256B', - 1: 'HUBP_XFC_CHUNK_SIZE_512B', - 2: 'HUBP_XFC_CHUNK_SIZE_1KB', - 3: 'HUBP_XFC_CHUNK_SIZE_2KB', - 4: 'HUBP_XFC_CHUNK_SIZE_4KB', - 5: 'HUBP_XFC_CHUNK_SIZE_8KB', - 6: 'HUBP_XFC_CHUNK_SIZE_16KB', - 7: 'HUBP_XFC_CHUNK_SIZE_32KB', -} -HUBP_XFC_CHUNK_SIZE_256B = 0 -HUBP_XFC_CHUNK_SIZE_512B = 1 -HUBP_XFC_CHUNK_SIZE_1KB = 2 -HUBP_XFC_CHUNK_SIZE_2KB = 3 -HUBP_XFC_CHUNK_SIZE_4KB = 4 -HUBP_XFC_CHUNK_SIZE_8KB = 5 -HUBP_XFC_CHUNK_SIZE_16KB = 6 -HUBP_XFC_CHUNK_SIZE_32KB = 7 -HUBP_XFC_CHUNK_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MMHUBBUB_XFC_XFCMON_MODE_ENUM' -MMHUBBUB_XFC_XFCMON_MODE_ENUM__enumvalues = { - 0: 'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT', - 1: 'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS', - 2: 'MMHUBBUB_XFC_XFCMON_MODE_PERIODS', -} -MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0 -MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 1 -MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 2 -MMHUBBUB_XFC_XFCMON_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM' -MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM__enumvalues = { - 0: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB', - 1: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB', -} -MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0 -MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 1 -MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM' -MMHUBBUB_XFC_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'MMHUBBUB_XFC_PIXEL_IS_32BPP', - 1: 'MMHUBBUB_XFC_PIXEL_IS_64BPP', -} -MMHUBBUB_XFC_PIXEL_IS_32BPP = 0 -MMHUBBUB_XFC_PIXEL_IS_64BPP = 1 -MMHUBBUB_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MMHUBBUB_XFC_FRAME_MODE_ENUM' -MMHUBBUB_XFC_FRAME_MODE_ENUM__enumvalues = { - 0: 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE', - 1: 'MMHUBBUB_XFC_FULL_FRAME_MODE', -} -MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0 -MMHUBBUB_XFC_FULL_FRAME_MODE = 1 -MMHUBBUB_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' -MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { - 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', - 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', - 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', -} -MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 -MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 -MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 -MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 -MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_MODE' -MPC_CRC_CALC_MODE__enumvalues = { - 0: 'MPC_CRC_ONE_SHOT_MODE', - 1: 'MPC_CRC_CONTINUOUS_MODE', -} -MPC_CRC_ONE_SHOT_MODE = 0 -MPC_CRC_CONTINUOUS_MODE = 1 -MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' -MPC_CRC_CALC_STEREO_MODE__enumvalues = { - 0: 'MPC_CRC_STEREO_MODE_LEFT', - 1: 'MPC_CRC_STEREO_MODE_RIGHT', - 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', -} -MPC_CRC_STEREO_MODE_LEFT = 0 -MPC_CRC_STEREO_MODE_RIGHT = 1 -MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 -MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' -MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { - 0: 'MPC_CRC_INTERLACE_MODE_TOP', - 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', - 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', -} -MPC_CRC_INTERLACE_MODE_TOP = 0 -MPC_CRC_INTERLACE_MODE_BOTTOM = 1 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_SOURCE_SELECT' -MPC_CRC_SOURCE_SELECT__enumvalues = { - 0: 'MPC_CRC_SOURCE_SEL_DPP', - 1: 'MPC_CRC_SOURCE_SEL_OPP', - 2: 'MPC_CRC_SOURCE_SEL_DWB', - 3: 'MPC_CRC_SOURCE_SEL_OTHER', -} -MPC_CRC_SOURCE_SEL_DPP = 0 -MPC_CRC_SOURCE_SEL_OPP = 1 -MPC_CRC_SOURCE_SEL_DWB = 2 -MPC_CRC_SOURCE_SEL_OTHER = 3 -MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' -MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' -MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { - 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', -} -MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 -MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 -MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { - 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', -} -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_COEF_FORMAT' -MPC_OCSC_COEF_FORMAT__enumvalues = { - 0: 'MPC_OCSC_COEF_FORMAT_S2_13', - 1: 'MPC_OCSC_COEF_FORMAT_S3_12', -} -MPC_OCSC_COEF_FORMAT_S2_13 = 0 -MPC_OCSC_COEF_FORMAT_S3_12 = 1 -MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_CSC_MODE' -MPC_OUT_CSC_MODE__enumvalues = { - 0: 'MPC_OUT_CSC_MODE_0', - 1: 'MPC_OUT_CSC_MODE_1', - 2: 'MPC_OUT_CSC_MODE_2', - 3: 'MPC_OUT_CSC_MODE_RSV', -} -MPC_OUT_CSC_MODE_0 = 0 -MPC_OUT_CSC_MODE_1 = 1 -MPC_OUT_CSC_MODE_2 = 2 -MPC_OUT_CSC_MODE_RSV = 3 -MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_MODE' -MPCC_CONTROL_MPCC_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', -} -MPCC_CONTROL_MPCC_MODE_BYPASS = 0 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 -MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 -MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', -} -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', -} -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', -} -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' -MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' -MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 -MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 -MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 -MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK' -MPCC_STALL_STATUS_MPCC_STALL_INT_ACK__enumvalues = { - 0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE', - 1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE', -} -MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0 -MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 1 -MPCC_STALL_STATUS_MPCC_STALL_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK' -MPCC_STALL_STATUS_MPCC_STALL_INT_MASK__enumvalues = { - 0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE', - 1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE', -} -MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0 -MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 1 -MPCC_STALL_STATUS_MPCC_STALL_INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_BG_COLOR_BPC' -MPCC_BG_COLOR_BPC__enumvalues = { - 0: 'MPCC_BG_COLOR_BPC_8bit', - 1: 'MPCC_BG_COLOR_BPC_9bit', - 2: 'MPCC_BG_COLOR_BPC_10bit', - 3: 'MPCC_BG_COLOR_BPC_11bit', - 4: 'MPCC_BG_COLOR_BPC_12bit', -} -MPCC_BG_COLOR_BPC_8bit = 0 -MPCC_BG_COLOR_BPC_9bit = 1 -MPCC_BG_COLOR_BPC_10bit = 2 -MPCC_BG_COLOR_BPC_11bit = 3 -MPCC_BG_COLOR_BPC_12bit = 4 -MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' -MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', -} -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', -} -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE' -MPCC_OGAM_MODE_MPCC_OGAM_MODE__enumvalues = { - 0: 'MPCC_OGAM_MODE_0', - 1: 'MPCC_OGAM_MODE_1', - 2: 'MPCC_OGAM_MODE_2', - 3: 'MPCC_OGAM_MODE_RSV', -} -MPCC_OGAM_MODE_0 = 0 -MPCC_OGAM_MODE_1 = 1 -MPCC_OGAM_MODE_2 = 2 -MPCC_OGAM_MODE_RSV = 3 -MPCC_OGAM_MODE_MPCC_OGAM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_EN' -ENUM_DPG_EN__enumvalues = { - 0: 'ENUM_DPG_DISABLE', - 1: 'ENUM_DPG_ENABLE', -} -ENUM_DPG_DISABLE = 0 -ENUM_DPG_ENABLE = 1 -ENUM_DPG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_MODE' -ENUM_DPG_MODE__enumvalues = { - 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 3: 'ENUM_DPG_MODE_VERTICAL_BAR', - 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', - 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', - 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', -} -ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 -ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 -ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 -ENUM_DPG_MODE_VERTICAL_BAR = 3 -ENUM_DPG_MODE_HORIZONTAL_BAR = 4 -ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 -ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 -ENUM_DPG_MODE_RGB_XR_BIAS = 7 -ENUM_DPG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' -ENUM_DPG_DYNAMIC_RANGE__enumvalues = { - 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', - 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', -} -ENUM_DPG_DYNAMIC_RANGE_VESA = 0 -ENUM_DPG_DYNAMIC_RANGE_CEA = 1 -ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_BIT_DEPTH' -ENUM_DPG_BIT_DEPTH__enumvalues = { - 0: 'ENUM_DPG_BIT_DEPTH_6BPC', - 1: 'ENUM_DPG_BIT_DEPTH_8BPC', - 2: 'ENUM_DPG_BIT_DEPTH_10BPC', - 3: 'ENUM_DPG_BIT_DEPTH_12BPC', -} -ENUM_DPG_BIT_DEPTH_6BPC = 0 -ENUM_DPG_BIT_DEPTH_8BPC = 1 -ENUM_DPG_BIT_DEPTH_10BPC = 2 -ENUM_DPG_BIT_DEPTH_12BPC = 3 -ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_FIELD_POLARITY' -ENUM_DPG_FIELD_POLARITY__enumvalues = { - 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', -} -ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 -ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 -ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' -FMT_CONTROL_PIXEL_ENCODING__enumvalues = { - 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', -} -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 -FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' -FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', -} -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 -FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' -FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', -} -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 -FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { - 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', -} -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' -FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' -FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', -} -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' -FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' -FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { - 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', -} -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 -FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_MODE' -FMT_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_MODE_0', - 1: 'FMT_SPATIAL_DITHER_MODE_1', - 2: 'FMT_SPATIAL_DITHER_MODE_2', - 3: 'FMT_SPATIAL_DITHER_MODE_3', -} -FMT_SPATIAL_DITHER_MODE_0 = 0 -FMT_SPATIAL_DITHER_MODE_1 = 1 -FMT_SPATIAL_DITHER_MODE_2 = 2 -FMT_SPATIAL_DITHER_MODE_3 = 3 -FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DYNAMIC_EXP_MODE' -FMT_DYNAMIC_EXP_MODE__enumvalues = { - 0: 'FMT_DYNAMIC_EXP_MODE_10to12', - 1: 'FMT_DYNAMIC_EXP_MODE_8to12', -} -FMT_DYNAMIC_EXP_MODE_10to12 = 0 -FMT_DYNAMIC_EXP_MODE_8to12 = 1 -FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' -FMTMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'FMTMEM_NO_FORCE_REQUEST', - 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', -} -FMTMEM_NO_FORCE_REQUEST = 0 -FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 -FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_DIS_CTRL' -FMTMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', -} -FMTMEM_ENABLE_MEM_PWR_CTRL = 0 -FMTMEM_DISABLE_MEM_PWR_CTRL = 1 -FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_POWER_STATE_ENUM' -FMT_POWER_STATE_ENUM__enumvalues = { - 0: 'FMT_POWER_STATE_ENUM_ON', - 1: 'FMT_POWER_STATE_ENUM_LS', - 2: 'FMT_POWER_STATE_ENUM_DS', - 3: 'FMT_POWER_STATE_ENUM_SD', -} -FMT_POWER_STATE_ENUM_ON = 0 -FMT_POWER_STATE_ENUM_LS = 1 -FMT_POWER_STATE_ENUM_DS = 2 -FMT_POWER_STATE_ENUM_SD = 3 -FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' -FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { - 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', -} -FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 -FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 -FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', -} -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' -FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', -} -FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 -FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 -FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' -FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', -} -FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 -FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 -FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_FMT_PTI_FIELD_POLARITY' -ENUM_FMT_PTI_FIELD_POLARITY__enumvalues = { - 0: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 1: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', -} -ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 -ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 -ENUM_FMT_PTI_FIELD_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' -OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { - 0: 'OPP_PIPE_CLOCK_DISABLE', - 1: 'OPP_PIPE_CLOCK_ENABLE', -} -OPP_PIPE_CLOCK_DISABLE = 0 -OPP_PIPE_CLOCK_ENABLE = 1 -OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' -OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { - 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', -} -OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 -OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 -OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_EN' -OPP_PIPE_CRC_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_DISABLE', - 1: 'OPP_PIPE_CRC_ENABLE', -} -OPP_PIPE_CRC_DISABLE = 0 -OPP_PIPE_CRC_ENABLE = 1 -OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_CONT_EN' -OPP_PIPE_CRC_CONT_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', - 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', -} -OPP_PIPE_CRC_MODE_ONE_SHOT = 0 -OPP_PIPE_CRC_MODE_CONTINUOUS = 1 -OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' -OPP_PIPE_CRC_STEREO_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', - 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', -} -OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 -OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 -OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' -OPP_PIPE_CRC_STEREO_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', -} -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 -OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' -OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', - 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', -} -OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 -OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 -OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' -OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', -} -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 -OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' -OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', -} -OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 -OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 -OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 -OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 -OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' -OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', -} -OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 -OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 -OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' -OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { - 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', -} -OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 -OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 -OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' -OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { - 0: 'OPP_TOP_CLOCK_GATING_ENABLED', - 1: 'OPP_TOP_CLOCK_GATING_DISABLED', -} -OPP_TOP_CLOCK_GATING_ENABLED = 0 -OPP_TOP_CLOCK_GATING_DISABLED = 1 -OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' -OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { - 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', - 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', -} -OPP_TOP_CLOCK_DISABLED_STATUS = 0 -OPP_TOP_CLOCK_ENABLED_STATUS = 1 -OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' -OPP_TEST_CLK_SEL_CONTROL__enumvalues = { - 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', - 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', - 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', - 3: 'OPP_TEST_CLK_SEL_RESERVED0', - 4: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', - 5: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 6: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', - 7: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP4', - 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP5', -} -OPP_TEST_CLK_SEL_DISPCLK_P = 0 -OPP_TEST_CLK_SEL_DISPCLK_R = 1 -OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 -OPP_TEST_CLK_SEL_RESERVED0 = 3 -OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 4 -OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 5 -OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 6 -OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 7 -OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 8 -OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 9 -OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' -OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', -} -OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 -OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', -} -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' -OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED', - 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', -} -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 2 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', -} -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE' -OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE__enumvalues = { - 0: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE', - 1: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE', -} -OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0 -OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 1 -OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_SOF_PULL_EN' -OTG_CONTROL_OTG_SOF_PULL_EN__enumvalues = { - 0: 'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE', - 1: 'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE', -} -OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0 -OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 1 -OTG_CONTROL_OTG_SOF_PULL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN' -OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', -} -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { - 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', - 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', -} -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { - 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', -} -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { - 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', -} -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL', - 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 14 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', -} -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL', - 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 14 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', -} -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE', - 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 15 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { - 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', -} -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' -OTG_CONTROL_OTG_MASTER_EN__enumvalues = { - 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', -} -OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 -OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 -OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN' -OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN__enumvalues = { - 0: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE', - 1: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE', -} -OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0 -OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 1 -OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE' -OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE__enumvalues = { - 0: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE', - 1: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE', -} -OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0 -OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 1 -OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY' -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', - 1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', -} -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT' -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT__enumvalues = { - 0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE', - 1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE', -} -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0 -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 1 -OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { - 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', -} -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { - 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', -} -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', -} -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', -} -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' -OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { - 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', -} -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { - 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', -} -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY' -OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY__enumvalues = { - 0: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE', - 1: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE', -} -OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 -OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 -OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY' -OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY__enumvalues = { - 0: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE', - 1: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE', -} -OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0 -OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 1 -OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN' -OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN__enumvalues = { - 0: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE', - 1: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE', -} -OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0 -OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 1 -OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN' -OTG_START_LINE_CONTROL_OTG_PREFETCH_EN__enumvalues = { - 0: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE', - 1: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE', -} -OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0 -OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 1 -OTG_START_LINE_CONTROL_OTG_PREFETCH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { - 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', -} -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN' -OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE' -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1', - 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2', - 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 2 -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 3 -OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE' -OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { - 0: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE', - 1: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE', -} -OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 -OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 -OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { - 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', -} -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE' -OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE__enumvalues = { - 0: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE', - 1: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG', - 2: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL', -} -OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0 -OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 1 -OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 2 -OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR' -OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR__enumvalues = { - 0: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE', - 1: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE', -} -OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0 -OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 1 -OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR' -OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { - 0: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', - 1: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', -} -OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 -OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 -OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR' -OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR__enumvalues = { - 0: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE', - 1: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE', -} -OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0 -OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 1 -OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' -OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' -OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', -} -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', -} -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE' -OTG_CRC_CNTL2_OTG_CRC_DSC_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE', - 1: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE', -} -OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0 -OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 1 -OTG_CRC_CNTL2_OTG_CRC_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE' -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE', - 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE', -} -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 1 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE' -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE', - 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1', - 2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2', - 3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3', -} -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 1 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 2 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 3 -OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT' -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT__enumvalues = { - 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0', - 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1', - 2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2', - 3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3', -} -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0 -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 1 -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 2 -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 3 -OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT', - 2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', - 3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', - 2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', - 3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE' -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', -} -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 -OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE' -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR' -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', -} -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE' -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', -} -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', - 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', - 2: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', - 3: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', - 4: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', - 5: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', - 6: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', - 7: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', -} -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 -OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE' -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR' -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE', -} -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 1 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE' -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE', -} -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 -OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', -} -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR' -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', -} -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { - 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', - 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', -} -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 -OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_A_POL' -OTG_V_SYNC_A_POL__enumvalues = { - 0: 'OTG_V_SYNC_A_POL_HIGH', - 1: 'OTG_V_SYNC_A_POL_LOW', -} -OTG_V_SYNC_A_POL_HIGH = 0 -OTG_V_SYNC_A_POL_LOW = 1 -OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_SYNC_A_POL' -OTG_H_SYNC_A_POL__enumvalues = { - 0: 'OTG_H_SYNC_A_POL_HIGH', - 1: 'OTG_H_SYNC_A_POL_LOW', -} -OTG_H_SYNC_A_POL_HIGH = 0 -OTG_H_SYNC_A_POL_LOW = 1 -OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_HORZ_REPETITION_COUNT' -OTG_HORZ_REPETITION_COUNT__enumvalues = { - 0: 'OTG_HORZ_REPETITION_COUNT_0', - 1: 'OTG_HORZ_REPETITION_COUNT_1', - 2: 'OTG_HORZ_REPETITION_COUNT_2', - 3: 'OTG_HORZ_REPETITION_COUNT_3', - 4: 'OTG_HORZ_REPETITION_COUNT_4', - 5: 'OTG_HORZ_REPETITION_COUNT_5', - 6: 'OTG_HORZ_REPETITION_COUNT_6', - 7: 'OTG_HORZ_REPETITION_COUNT_7', - 8: 'OTG_HORZ_REPETITION_COUNT_8', - 9: 'OTG_HORZ_REPETITION_COUNT_9', - 10: 'OTG_HORZ_REPETITION_COUNT_10', - 11: 'OTG_HORZ_REPETITION_COUNT_11', - 12: 'OTG_HORZ_REPETITION_COUNT_12', - 13: 'OTG_HORZ_REPETITION_COUNT_13', - 14: 'OTG_HORZ_REPETITION_COUNT_14', - 15: 'OTG_HORZ_REPETITION_COUNT_15', -} -OTG_HORZ_REPETITION_COUNT_0 = 0 -OTG_HORZ_REPETITION_COUNT_1 = 1 -OTG_HORZ_REPETITION_COUNT_2 = 2 -OTG_HORZ_REPETITION_COUNT_3 = 3 -OTG_HORZ_REPETITION_COUNT_4 = 4 -OTG_HORZ_REPETITION_COUNT_5 = 5 -OTG_HORZ_REPETITION_COUNT_6 = 6 -OTG_HORZ_REPETITION_COUNT_7 = 7 -OTG_HORZ_REPETITION_COUNT_8 = 8 -OTG_HORZ_REPETITION_COUNT_9 = 9 -OTG_HORZ_REPETITION_COUNT_10 = 10 -OTG_HORZ_REPETITION_COUNT_11 = 11 -OTG_HORZ_REPETITION_COUNT_12 = 12 -OTG_HORZ_REPETITION_COUNT_13 = 13 -OTG_HORZ_REPETITION_COUNT_14 = 14 -OTG_HORZ_REPETITION_COUNT_15 = 15 -OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_SEL' -MASTER_UPDATE_LOCK_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_SEL_0', - 1: 'MASTER_UPDATE_LOCK_SEL_1', - 2: 'MASTER_UPDATE_LOCK_SEL_2', - 3: 'MASTER_UPDATE_LOCK_SEL_3', - 4: 'MASTER_UPDATE_LOCK_SEL_4', - 5: 'MASTER_UPDATE_LOCK_SEL_5', -} -MASTER_UPDATE_LOCK_SEL_0 = 0 -MASTER_UPDATE_LOCK_SEL_1 = 1 -MASTER_UPDATE_LOCK_SEL_2 = 2 -MASTER_UPDATE_LOCK_SEL_3 = 3 -MASTER_UPDATE_LOCK_SEL_4 = 4 -MASTER_UPDATE_LOCK_SEL_5 = 5 -MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DRR_UPDATE_LOCK_SEL' -DRR_UPDATE_LOCK_SEL__enumvalues = { - 0: 'DRR_UPDATE_LOCK_SEL_0', - 1: 'DRR_UPDATE_LOCK_SEL_1', - 2: 'DRR_UPDATE_LOCK_SEL_2', - 3: 'DRR_UPDATE_LOCK_SEL_3', - 4: 'DRR_UPDATE_LOCK_SEL_4', - 5: 'DRR_UPDATE_LOCK_SEL_5', -} -DRR_UPDATE_LOCK_SEL_0 = 0 -DRR_UPDATE_LOCK_SEL_1 = 1 -DRR_UPDATE_LOCK_SEL_2 = 2 -DRR_UPDATE_LOCK_SEL_3 = 3 -DRR_UPDATE_LOCK_SEL_4 = 4 -DRR_UPDATE_LOCK_SEL_5 = 5 -DRR_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { - 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4', - 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5', -} -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 4 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 5 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 2: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', -} -MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 -MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 -MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 2 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', -} -MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_BY2' -OTG_H_TIMING_DIV_BY2__enumvalues = { - 0: 'OTG_H_TIMING_DIV_BY2_FALSE', - 1: 'OTG_H_TIMING_DIV_BY2_TRUE', -} -OTG_H_TIMING_DIV_BY2_FALSE = 0 -OTG_H_TIMING_DIV_BY2_TRUE = 1 -OTG_H_TIMING_DIV_BY2 = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE' -OTG_H_TIMING_DIV_BY2_UPDATE_MODE__enumvalues = { - 0: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0', - 1: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1', -} -OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0 -OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 1 -OTG_H_TIMING_DIV_BY2_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' -OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' -OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', -} -OTG_TRIGA_FREQUENCY_SELECT_0 = 0 -OTG_TRIGA_FREQUENCY_SELECT_1 = 1 -OTG_TRIGA_FREQUENCY_SELECT_2 = 2 -OTG_TRIGA_FREQUENCY_SELECT_3 = 3 -OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' -OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' -OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', -} -OTG_TRIGB_FREQUENCY_SELECT_0 = 0 -OTG_TRIGB_FREQUENCY_SELECT_1 = 1 -OTG_TRIGB_FREQUENCY_SELECT_2 = 2 -OTG_TRIGB_FREQUENCY_SELECT_3 = 3 -OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_PIPE_ABORT' -OTG_PIPE_ABORT__enumvalues = { - 0: 'OTG_PIPE_ABORT_0', - 1: 'OTG_PIPE_ABORT_1', -} -OTG_PIPE_ABORT_0 = 0 -OTG_PIPE_ABORT_1 = 1 -OTG_PIPE_ABORT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' -OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', -} -OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 -OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 -OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_PTI_CONTROL_OTG_PIT_EN' -OTG_PTI_CONTROL_OTG_PIT_EN__enumvalues = { - 0: 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE', - 1: 'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE', -} -OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0 -OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 1 -OTG_PTI_CONTROL_OTG_PIT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GSL_MASTER_MODE' -OTG_GSL_MASTER_MODE__enumvalues = { - 0: 'OTG_GSL_MASTER_MODE_0', - 1: 'OTG_GSL_MASTER_MODE_1', - 2: 'OTG_GSL_MASTER_MODE_2', - 3: 'OTG_GSL_MASTER_MODE_3', -} -OTG_GSL_MASTER_MODE_0 = 0 -OTG_GSL_MASTER_MODE_1 = 1 -OTG_GSL_MASTER_MODE_2 = 2 -OTG_GSL_MASTER_MODE_3 = 3 -OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_TIMER_WINDOW' -DC_DMCUB_TIMER_WINDOW__enumvalues = { - 0: 'BITS_31_0', - 1: 'BITS_32_1', - 2: 'BITS_33_2', - 3: 'BITS_34_3', - 4: 'BITS_35_4', - 5: 'BITS_36_5', - 6: 'BITS_37_6', - 7: 'BITS_38_7', -} -BITS_31_0 = 0 -BITS_32_1 = 1 -BITS_33_2 = 2 -BITS_34_3 = 3 -BITS_35_4 = 4 -BITS_36_5 = 5 -BITS_37_6 = 6 -BITS_38_7 = 7 -DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_INT_TYPE' -DC_DMCUB_INT_TYPE__enumvalues = { - 0: 'INT_LEVEL', - 1: 'INT_PULSE', -} -INT_LEVEL = 0 -INT_PULSE = 1 -DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'INVALID_REG_ACCESS_TYPE' -INVALID_REG_ACCESS_TYPE__enumvalues = { - 0: 'REG_UNALLOCATED_ADDR_WRITE', - 1: 'REG_UNALLOCATED_ADDR_READ', - 2: 'REG_VIRTUAL_WRITE', - 3: 'REG_VIRTUAL_READ', -} -REG_UNALLOCATED_ADDR_WRITE = 0 -REG_UNALLOCATED_ADDR_READ = 1 -REG_VIRTUAL_WRITE = 2 -REG_VIRTUAL_READ = 3 -INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' -DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DMU_GPU_TIMER_START_0_END_27', - 1: 'DMU_GPU_TIMER_START_1_END_28', - 2: 'DMU_GPU_TIMER_START_2_END_29', - 3: 'DMU_GPU_TIMER_START_3_END_30', - 4: 'DMU_GPU_TIMER_START_4_END_31', - 5: 'DMU_GPU_TIMER_START_6_END_33', - 6: 'DMU_GPU_TIMER_START_8_END_35', - 7: 'DMU_GPU_TIMER_START_10_END_37', -} -DMU_GPU_TIMER_START_0_END_27 = 0 -DMU_GPU_TIMER_START_1_END_28 = 1 -DMU_GPU_TIMER_START_2_END_29 = 2 -DMU_GPU_TIMER_START_3_END_30 = 3 -DMU_GPU_TIMER_START_4_END_31 = 4 -DMU_GPU_TIMER_START_6_END_33 = 5 -DMU_GPU_TIMER_START_8_END_35 = 6 -DMU_GPU_TIMER_START_10_END_37 = 7 -DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' -DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 8: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8', - 9: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9', - 10: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10', - 11: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11', - 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 20: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20', - 21: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21', - 22: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22', - 23: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23', - 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 32: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32', - 33: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33', - 34: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34', - 35: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35', - 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 44: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44', - 45: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45', - 46: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46', - 47: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47', - 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 56: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56', - 57: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57', - 58: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58', - 59: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59', - 60: 'RESERVED_60', - 61: 'RESERVED_61', - 62: 'RESERVED_62', - 63: 'RESERVED_63', - 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 72: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72', - 73: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73', - 74: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74', - 75: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75', - 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 84: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84', - 85: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85', - 86: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86', - 87: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87', - 88: 'RESERVED_88', - 89: 'RESERVED_89', - 90: 'RESERVED_90', - 91: 'RESERVED_91', -} -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 8 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 9 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 10 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 11 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 20 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 21 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 22 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 23 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 32 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 33 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 34 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 35 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 44 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 45 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 46 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 47 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 56 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 57 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 58 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 59 -RESERVED_60 = 60 -RESERVED_61 = 61 -RESERVED_62 = 62 -RESERVED_63 = 63 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 72 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 73 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 74 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 75 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 -DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 84 -DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 85 -DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 86 -DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 87 -RESERVED_88 = 88 -RESERVED_89 = 89 -RESERVED_90 = 90 -RESERVED_91 = 91 -DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' -IHC_INTERRUPT_LINE_STATUS__enumvalues = { - 0: 'INTERRUPT_LINE_NOT_ASSERTED', - 1: 'INTERRUPT_LINE_ASSERTED', -} -INTERRUPT_LINE_NOT_ASSERTED = 0 -INTERRUPT_LINE_ASSERTED = 1 -IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_CLOCK_GATING_DISABLE' -DMU_CLOCK_GATING_DISABLE__enumvalues = { - 0: 'DMU_ENABLE_CLOCK_GATING', - 1: 'DMU_DISABLE_CLOCK_GATING', -} -DMU_ENABLE_CLOCK_GATING = 0 -DMU_DISABLE_CLOCK_GATING = 1 -DMU_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_CLOCK_ON' -DMU_CLOCK_ON__enumvalues = { - 0: 'DMU_CLOCK_STATUS_ON', - 1: 'DMU_CLOCK_STATUS_OFF', -} -DMU_CLOCK_STATUS_ON = 0 -DMU_CLOCK_STATUS_OFF = 1 -DMU_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' -DC_SMU_INTERRUPT_ENABLE__enumvalues = { - 0: 'DISABLE_THE_INTERRUPT', - 1: 'ENABLE_THE_INTERRUPT', -} -DISABLE_THE_INTERRUPT = 0 -ENABLE_THE_INTERRUPT = 1 -DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'STATIC_SCREEN_SMU_INTR' -STATIC_SCREEN_SMU_INTR__enumvalues = { - 0: 'STATIC_SCREEN_SMU_INTR_NOOP', - 1: 'SET_STATIC_SCREEN_SMU_INTR', -} -STATIC_SCREEN_SMU_INTR_NOOP = 0 -SET_STATIC_SCREEN_SMU_INTR = 1 -STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE' -ENABLE__enumvalues = { - 0: 'DISABLE_THE_FEATURE', - 1: 'ENABLE_THE_FEATURE', -} -DISABLE_THE_FEATURE = 0 -ENABLE_THE_FEATURE = 1 -ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_HW_CAL_ENABLE' -DS_HW_CAL_ENABLE__enumvalues = { - 0: 'DS_HW_CAL_DIS', - 1: 'DS_HW_CAL_EN', -} -DS_HW_CAL_DIS = 0 -DS_HW_CAL_EN = 1 -DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_CLOCK' -ENABLE_CLOCK__enumvalues = { - 0: 'DISABLE_THE_CLOCK', - 1: 'ENABLE_THE_CLOCK', -} -DISABLE_THE_CLOCK = 0 -ENABLE_THE_CLOCK = 1 -ENABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'CLEAR_SMU_INTR' -CLEAR_SMU_INTR__enumvalues = { - 0: 'SMU_INTR_STATUS_NOOP', - 1: 'SMU_INTR_STATUS_CLEAR', -} -SMU_INTR_STATUS_NOOP = 0 -SMU_INTR_STATUS_CLEAR = 1 -CLEAR_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'JITTER_REMOVE_DISABLE' -JITTER_REMOVE_DISABLE__enumvalues = { - 0: 'ENABLE_JITTER_REMOVAL', - 1: 'DISABLE_JITTER_REMOVAL', -} -ENABLE_JITTER_REMOVAL = 0 -DISABLE_JITTER_REMOVAL = 1 -JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_REF_SRC' -DS_REF_SRC__enumvalues = { - 0: 'DS_REF_IS_XTALIN', - 1: 'DS_REF_IS_EXT_GENLOCK', - 2: 'DS_REF_IS_PCIE', -} -DS_REF_IS_XTALIN = 0 -DS_REF_IS_EXT_GENLOCK = 1 -DS_REF_IS_PCIE = 2 -DS_REF_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING' -DISABLE_CLOCK_GATING__enumvalues = { - 0: 'CLOCK_GATING_ENABLED', - 1: 'CLOCK_GATING_DISABLED', -} -CLOCK_GATING_ENABLED = 0 -CLOCK_GATING_DISABLED = 1 -DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' -DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { - 0: 'CLOCK_GATING_ENABLED_IN_DCO', - 1: 'CLOCK_GATING_DISABLED_IN_DCO', -} -CLOCK_GATING_ENABLED_IN_DCO = 0 -CLOCK_GATING_DISABLED_IN_DCO = 1 -DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DEEP_COLOR_CNTL' -DCCG_DEEP_COLOR_CNTL__enumvalues = { - 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', - 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', - 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', -} -DCCG_DEEP_COLOR_DTO_DISABLE = 0 -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 -DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'REFCLK_CLOCK_EN' -REFCLK_CLOCK_EN__enumvalues = { - 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', - 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', -} -REFCLK_CLOCK_EN_XTALIN_CLK = 0 -REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 -REFCLK_CLOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'REFCLK_SRC_SEL' -REFCLK_SRC_SEL__enumvalues = { - 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', - 1: 'REFCLK_SRC_SEL_CPL_REFCLK', -} -REFCLK_SRC_SEL_PCIE_REFCLK = 0 -REFCLK_SRC_SEL_CPL_REFCLK = 1 -REFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPREFCLK_SRC_SEL' -DPREFCLK_SRC_SEL__enumvalues = { - 0: 'DPREFCLK_SRC_SEL_CK', - 1: 'DPREFCLK_SRC_SEL_P0PLL', - 2: 'DPREFCLK_SRC_SEL_P1PLL', - 3: 'DPREFCLK_SRC_SEL_P2PLL', -} -DPREFCLK_SRC_SEL_CK = 0 -DPREFCLK_SRC_SEL_P0PLL = 1 -DPREFCLK_SRC_SEL_P1PLL = 2 -DPREFCLK_SRC_SEL_P2PLL = 3 -DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_SEL' -XTAL_REF_SEL__enumvalues = { - 0: 'XTAL_REF_SEL_1X', - 1: 'XTAL_REF_SEL_2X', -} -XTAL_REF_SEL_1X = 0 -XTAL_REF_SEL_2X = 1 -XTAL_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' -XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', - 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', -} -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 -XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 -XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' -ALLOW_SR_ON_TRANS_REQ__enumvalues = { - 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', -} -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 -ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 -ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' -PIPE_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', - 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', -} -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 -PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 -PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 -PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_DIV_SEL' -TEST_CLK_DIV_SEL__enumvalues = { - 0: 'NO_DIV', - 1: 'DIV_2', - 2: 'DIV_4', - 3: 'DIV_8', -} -NO_DIV = 0 -DIV_2 = 1 -DIV_4 = 2 -DIV_8 = 3 -TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' -PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', - 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', - 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', -} -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 6 -PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' -PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', - 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', -} -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 -PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DTO_DS_DISABLE' -DP_DTO_DS_DISABLE__enumvalues = { - 0: 'DP_DTO_DESPREAD_DISABLE', - 1: 'DP_DTO_DESPREAD_ENABLE', -} -DP_DTO_DESPREAD_DISABLE = 0 -DP_DTO_DESPREAD_ENABLE = 1 -DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_ADD_PIXEL' -OTG_ADD_PIXEL__enumvalues = { - 0: 'OTG_ADD_PIXEL_NOOP', - 1: 'OTG_ADD_PIXEL_FORCE', -} -OTG_ADD_PIXEL_NOOP = 0 -OTG_ADD_PIXEL_FORCE = 1 -OTG_ADD_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DROP_PIXEL' -OTG_DROP_PIXEL__enumvalues = { - 0: 'OTG_DROP_PIXEL_NOOP', - 1: 'OTG_DROP_PIXEL_FORCE', -} -OTG_DROP_PIXEL_NOOP = 0 -OTG_DROP_PIXEL_FORCE = 1 -OTG_DROP_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_EN' -SYMCLK_FE_FORCE_EN__enumvalues = { - 0: 'SYMCLK_FE_FORCE_EN_DISABLE', - 1: 'SYMCLK_FE_FORCE_EN_ENABLE', -} -SYMCLK_FE_FORCE_EN_DISABLE = 0 -SYMCLK_FE_FORCE_EN_ENABLE = 1 -SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_SRC' -SYMCLK_FE_FORCE_SRC__enumvalues = { - 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', - 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', - 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', - 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', - 6: 'SYMCLK_FE_FORCE_SRC_RESERVED', -} -SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 -SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 -SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 -SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 -SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 -SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 -SYMCLK_FE_FORCE_SRC_RESERVED = 6 -SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' -DVOACLK_COARSE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', -} -DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 -DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 -DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 -DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 -DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 -DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 -DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 -DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 -DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 -DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 -DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 -DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 -DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 -DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 -DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 -DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 -DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 -DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 -DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 -DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 -DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 -DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 -DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 -DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 -DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 -DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 -DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 -DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' -DVOACLK_FINE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', -} -DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 -DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 -DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 -DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 -DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKD_IN_PHASE' -DVOACLKD_IN_PHASE__enumvalues = { - 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_IN_PHASE' -DVOACLKC_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_IN_PHASE' -DVOACLKC_MVP_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { - 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', -} -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' -DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4', - 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5', - 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', -} -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 4 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 5 -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 -DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_SEL' -DCCG_AUDIO_DTO_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', - 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', -} -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 -DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' -DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', -} -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 -DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' -DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { - 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', -} -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 -DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' -DISPCLK_FREQ_RAMP_DONE__enumvalues = { - 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', - 1: 'DISPCLK_FREQ_RAMP_COMPLETED', -} -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 -DISPCLK_FREQ_RAMP_COMPLETED = 1 -DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_RESET' -DCCG_FIFO_ERRDET_RESET__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', - 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', -} -DCCG_FIFO_ERRDET_RESET_NOOP = 0 -DCCG_FIFO_ERRDET_RESET_FORCE = 1 -DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_STATE' -DCCG_FIFO_ERRDET_STATE__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', -} -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 -DCCG_FIFO_ERRDET_STATE_DETECTION = 1 -DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' -DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', - 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', -} -DCCG_FIFO_ERRDET_OVR_DISABLE = 0 -DCCG_FIFO_ERRDET_OVR_ENABLE = 1 -DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' -DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { - 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', -} -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 -DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' -DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { - 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', -} -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 -DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_RUN' -DCCG_PERF_RUN__enumvalues = { - 0: 'DCCG_PERF_RUN_NOOP', - 1: 'DCCG_PERF_RUN_START', -} -DCCG_PERF_RUN_NOOP = 0 -DCCG_PERF_RUN_START = 1 -DCCG_PERF_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_VSYNC' -DCCG_PERF_MODE_VSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_VSYNC_NOOP', - 1: 'DCCG_PERF_MODE_VSYNC_START', -} -DCCG_PERF_MODE_VSYNC_NOOP = 0 -DCCG_PERF_MODE_VSYNC_START = 1 -DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_HSYNC' -DCCG_PERF_MODE_HSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_HSYNC_NOOP', - 1: 'DCCG_PERF_MODE_HSYNC_START', -} -DCCG_PERF_MODE_HSYNC_NOOP = 0 -DCCG_PERF_MODE_HSYNC_START = 1 -DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_OTG_SELECT' -DCCG_PERF_OTG_SELECT__enumvalues = { - 0: 'DCCG_PERF_SEL_OTG0', - 1: 'DCCG_PERF_SEL_OTG1', - 2: 'DCCG_PERF_SEL_OTG2', - 3: 'DCCG_PERF_SEL_OTG3', - 4: 'DCCG_PERF_SEL_OTG4', - 5: 'DCCG_PERF_SEL_OTG5', - 6: 'DCCG_PERF_SEL_RESERVED', -} -DCCG_PERF_SEL_OTG0 = 0 -DCCG_PERF_SEL_OTG1 = 1 -DCCG_PERF_SEL_OTG2 = 2 -DCCG_PERF_SEL_OTG3 = 3 -DCCG_PERF_SEL_OTG4 = 4 -DCCG_PERF_SEL_OTG5 = 5 -DCCG_PERF_SEL_RESERVED = 6 -DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' -CLOCK_BRANCH_SOFT_RESET__enumvalues = { - 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', -} -CLOCK_BRANCH_SOFT_RESET_NOOP = 0 -CLOCK_BRANCH_SOFT_RESET_FORCE = 1 -CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'PLL_CFG_IF_SOFT_RESET' -PLL_CFG_IF_SOFT_RESET__enumvalues = { - 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', - 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', -} -PLL_CFG_IF_SOFT_RESET_NOOP = 0 -PLL_CFG_IF_SOFT_RESET_FORCE = 1 -PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_ENABLE_RST' -DVO_ENABLE_RST__enumvalues = { - 0: 'DVO_ENABLE_RST_DISABLE', - 1: 'DVO_ENABLE_RST_ENABLE', -} -DVO_ENABLE_RST_DISABLE = 0 -DVO_ENABLE_RST_ENABLE = 1 -DVO_ENABLE_RST = ctypes.c_uint32 # enum - -# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' -DS_JITTER_COUNT_SRC_SEL__enumvalues = { - 0: 'DS_JITTER_COUNT_SRC_SEL0', - 1: 'DS_JITTER_COUNT_SRC_SEL1', -} -DS_JITTER_COUNT_SRC_SEL0 = 0 -DS_JITTER_COUNT_SRC_SEL1 = 1 -DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_FIFO_ERROR' -DIO_FIFO_ERROR__enumvalues = { - 0: 'DIO_FIFO_ERROR_00', - 1: 'DIO_FIFO_ERROR_01', - 2: 'DIO_FIFO_ERROR_10', - 3: 'DIO_FIFO_ERROR_11', -} -DIO_FIFO_ERROR_00 = 0 -DIO_FIFO_ERROR_01 = 1 -DIO_FIFO_ERROR_10 = 2 -DIO_FIFO_ERROR_11 = 3 -DIO_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_REFCLK_SEL' -VSYNC_CNT_REFCLK_SEL__enumvalues = { - 0: 'VSYNC_CNT_REFCLK_SEL_0', - 1: 'VSYNC_CNT_REFCLK_SEL_1', -} -VSYNC_CNT_REFCLK_SEL_0 = 0 -VSYNC_CNT_REFCLK_SEL_1 = 1 -VSYNC_CNT_REFCLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_RESET_SEL' -VSYNC_CNT_RESET_SEL__enumvalues = { - 0: 'VSYNC_CNT_RESET_SEL_0', - 1: 'VSYNC_CNT_RESET_SEL_1', -} -VSYNC_CNT_RESET_SEL_0 = 0 -VSYNC_CNT_RESET_SEL_1 = 1 -VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_LATCH_MASK' -VSYNC_CNT_LATCH_MASK__enumvalues = { - 0: 'VSYNC_CNT_LATCH_MASK_0', - 1: 'VSYNC_CNT_LATCH_MASK_1', -} -VSYNC_CNT_LATCH_MASK_0 = 0 -VSYNC_CNT_LATCH_MASK_1 = 1 -VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_ACK' -HPD_INT_CONTROL_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_ACK_0', - 1: 'HPD_INT_CONTROL_ACK_1', -} -HPD_INT_CONTROL_ACK_0 = 0 -HPD_INT_CONTROL_ACK_1 = 1 -HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_POLARITY' -HPD_INT_CONTROL_POLARITY__enumvalues = { - 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', - 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', -} -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 -HPD_INT_CONTROL_GEN_INT_ON_CON = 1 -HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' -HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', - 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', -} -HPD_INT_CONTROL_RX_INT_ACK_0 = 0 -HPD_INT_CONTROL_RX_INT_ACK_1 = 1 -HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' -DP_MSO_NUM_OF_SST_LINKS__enumvalues = { - 0: 'DP_MSO_ONE_SSTLINK', - 1: 'DP_MSO_TWO_SSTLINK', - 2: 'DP_MSO_FOUR_SSTLINK', -} -DP_MSO_ONE_SSTLINK = 0 -DP_MSO_TWO_SSTLINK = 1 -DP_MSO_FOUR_SSTLINK = 2 -DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SYNC_POLARITY' -DP_SYNC_POLARITY__enumvalues = { - 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', - 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', -} -DP_SYNC_POLARITY_ACTIVE_HIGH = 0 -DP_SYNC_POLARITY_ACTIVE_LOW = 1 -DP_SYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMBINE_PIXEL_NUM' -DP_COMBINE_PIXEL_NUM__enumvalues = { - 0: 'DP_COMBINE_ONE_PIXEL', - 1: 'DP_COMBINE_TWO_PIXEL', - 2: 'DP_COMBINE_FOUR_PIXEL', -} -DP_COMBINE_ONE_PIXEL = 0 -DP_COMBINE_TWO_PIXEL = 1 -DP_COMBINE_FOUR_PIXEL = 2 -DP_COMBINE_PIXEL_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_COMPLETE' -DP_LINK_TRAINING_COMPLETE__enumvalues = { - 0: 'DP_LINK_TRAINING_NOT_COMPLETE', - 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', -} -DP_LINK_TRAINING_NOT_COMPLETE = 0 -DP_LINK_TRAINING_ALREADY_COMPLETE = 1 -DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_EMBEDDED_PANEL_MODE' -DP_EMBEDDED_PANEL_MODE__enumvalues = { - 0: 'DP_EXTERNAL_PANEL', - 1: 'DP_EMBEDDED_PANEL', -} -DP_EXTERNAL_PANEL = 0 -DP_EMBEDDED_PANEL = 1 -DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING' -DP_PIXEL_ENCODING__enumvalues = { - 0: 'DP_PIXEL_ENCODING_RGB444', - 1: 'DP_PIXEL_ENCODING_YCBCR422', - 2: 'DP_PIXEL_ENCODING_YCBCR444', - 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 4: 'DP_PIXEL_ENCODING_Y_ONLY', - 5: 'DP_PIXEL_ENCODING_YCBCR420', - 6: 'DP_PIXEL_ENCODING_RESERVED', -} -DP_PIXEL_ENCODING_RGB444 = 0 -DP_PIXEL_ENCODING_YCBCR422 = 1 -DP_PIXEL_ENCODING_YCBCR444 = 2 -DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 -DP_PIXEL_ENCODING_Y_ONLY = 4 -DP_PIXEL_ENCODING_YCBCR420 = 5 -DP_PIXEL_ENCODING_RESERVED = 6 -DP_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPONENT_DEPTH' -DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_COMPONENT_DEPTH_6BPC', - 1: 'DP_COMPONENT_DEPTH_8BPC', - 2: 'DP_COMPONENT_DEPTH_10BPC', - 3: 'DP_COMPONENT_DEPTH_12BPC', - 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', - 5: 'DP_COMPONENT_DEPTH_RESERVED', -} -DP_COMPONENT_DEPTH_6BPC = 0 -DP_COMPONENT_DEPTH_8BPC = 1 -DP_COMPONENT_DEPTH_10BPC = 2 -DP_COMPONENT_DEPTH_12BPC = 3 -DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 -DP_COMPONENT_DEPTH_RESERVED = 5 -DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DP_UDI_LANES' -DP_UDI_LANES__enumvalues = { - 0: 'DP_UDI_1_LANE', - 1: 'DP_UDI_2_LANES', - 2: 'DP_UDI_LANES_RESERVED', - 3: 'DP_UDI_4_LANES', -} -DP_UDI_1_LANE = 0 -DP_UDI_2_LANES = 1 -DP_UDI_LANES_RESERVED = 2 -DP_UDI_4_LANES = 3 -DP_UDI_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DIS_DEFER' -DP_VID_STREAM_DIS_DEFER__enumvalues = { - 0: 'DP_VID_STREAM_DIS_NO_DEFER', - 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', -} -DP_VID_STREAM_DIS_NO_DEFER = 0 -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 -DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_ACK' -DP_STEER_OVERFLOW_ACK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_MASK' -DP_STEER_OVERFLOW_MASK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_MASKED', - 1: 'DP_STEER_OVERFLOW_UNMASK', -} -DP_STEER_OVERFLOW_MASKED = 0 -DP_STEER_OVERFLOW_UNMASK = 1 -DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_TU_OVERFLOW_ACK' -DP_TU_OVERFLOW_ACK__enumvalues = { - 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' -DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { - 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', -} -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 -DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_GEN_EN' -DP_VID_M_N_GEN_EN__enumvalues = { - 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', - 1: 'DP_VID_M_N_CALC_AUTO', -} -DP_VID_M_N_PROGRAMMED_VIA_REG = 0 -DP_VID_M_N_CALC_AUTO = 1 -DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_N_MUL' -DP_VID_N_MUL__enumvalues = { - 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', - 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', -} -DP_VID_M_1X_INPUT_PIXEL_RATE = 0 -DP_VID_M_2X_INPUT_PIXEL_RATE = 1 -DP_VID_M_4X_INPUT_PIXEL_RATE = 2 -DP_VID_M_8X_INPUT_PIXEL_RATE = 3 -DP_VID_N_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' -DP_VID_ENHANCED_FRAME_MODE__enumvalues = { - 0: 'VID_NORMAL_FRAME_MODE', - 1: 'VID_ENHANCED_MODE', -} -VID_NORMAL_FRAME_MODE = 0 -VID_ENHANCED_MODE = 1 -DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_VBID_FIELD_POL' -DP_VID_VBID_FIELD_POL__enumvalues = { - 0: 'DP_VID_VBID_FIELD_POL_NORMAL', - 1: 'DP_VID_VBID_FIELD_POL_INV', -} -DP_VID_VBID_FIELD_POL_NORMAL = 0 -DP_VID_VBID_FIELD_POL_INV = 1 -DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' -DP_VID_STREAM_DISABLE_ACK__enumvalues = { - 0: 'ID_STREAM_DISABLE_NO_ACK', - 1: 'ID_STREAM_DISABLE_ACKED', -} -ID_STREAM_DISABLE_NO_ACK = 0 -ID_STREAM_DISABLE_ACKED = 1 -DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' -DP_VID_STREAM_DISABLE_MASK__enumvalues = { - 0: 'VID_STREAM_DISABLE_MASKED', - 1: 'VID_STREAM_DISABLE_UNMASK', -} -VID_STREAM_DISABLE_MASKED = 0 -VID_STREAM_DISABLE_UNMASK = 1 -DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE0' -DPHY_ATEST_SEL_LANE0__enumvalues = { - 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE0_REG_PATTERN', -} -DPHY_ATEST_LANE0_PRBS_PATTERN = 0 -DPHY_ATEST_LANE0_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE1' -DPHY_ATEST_SEL_LANE1__enumvalues = { - 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE1_REG_PATTERN', -} -DPHY_ATEST_LANE1_PRBS_PATTERN = 0 -DPHY_ATEST_LANE1_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE2' -DPHY_ATEST_SEL_LANE2__enumvalues = { - 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE2_REG_PATTERN', -} -DPHY_ATEST_LANE2_PRBS_PATTERN = 0 -DPHY_ATEST_LANE2_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE3' -DPHY_ATEST_SEL_LANE3__enumvalues = { - 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE3_REG_PATTERN', -} -DPHY_ATEST_LANE3_PRBS_PATTERN = 0 -DPHY_ATEST_LANE3_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_BYPASS' -DPHY_BYPASS__enumvalues = { - 0: 'DPHY_8B10B_OUTPUT', - 1: 'DPHY_DBG_OUTPUT', -} -DPHY_8B10B_OUTPUT = 0 -DPHY_DBG_OUTPUT = 1 -DPHY_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SKEW_BYPASS' -DPHY_SKEW_BYPASS__enumvalues = { - 0: 'DPHY_WITH_SKEW', - 1: 'DPHY_NO_SKEW', -} -DPHY_WITH_SKEW = 0 -DPHY_NO_SKEW = 1 -DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' -DPHY_TRAINING_PATTERN_SEL__enumvalues = { - 0: 'DPHY_TRAINING_PATTERN_1', - 1: 'DPHY_TRAINING_PATTERN_2', - 2: 'DPHY_TRAINING_PATTERN_3', - 3: 'DPHY_TRAINING_PATTERN_4', -} -DPHY_TRAINING_PATTERN_1 = 0 -DPHY_TRAINING_PATTERN_2 = 1 -DPHY_TRAINING_PATTERN_3 = 2 -DPHY_TRAINING_PATTERN_4 = 3 -DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_RESET' -DPHY_8B10B_RESET__enumvalues = { - 0: 'DPHY_8B10B_NOT_RESET', - 1: 'DPHY_8B10B_RESETET', -} -DPHY_8B10B_NOT_RESET = 0 -DPHY_8B10B_RESETET = 1 -DPHY_8B10B_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' -DP_DPHY_8B10B_EXT_DISP__enumvalues = { - 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', -} -DP_DPHY_8B10B_EXT_DISP_ZERO = 0 -DP_DPHY_8B10B_EXT_DISP_ONE = 1 -DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_CUR_DISP' -DPHY_8B10B_CUR_DISP__enumvalues = { - 0: 'DPHY_8B10B_CUR_DISP_ZERO', - 1: 'DPHY_8B10B_CUR_DISP_ONE', -} -DPHY_8B10B_CUR_DISP_ZERO = 0 -DPHY_8B10B_CUR_DISP_ONE = 1 -DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_EN' -DPHY_PRBS_EN__enumvalues = { - 0: 'DPHY_PRBS_DISABLE', - 1: 'DPHY_PRBS_ENABLE', -} -DPHY_PRBS_DISABLE = 0 -DPHY_PRBS_ENABLE = 1 -DPHY_PRBS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_SEL' -DPHY_PRBS_SEL__enumvalues = { - 0: 'DPHY_PRBS7_SELECTED', - 1: 'DPHY_PRBS23_SELECTED', - 2: 'DPHY_PRBS11_SELECTED', -} -DPHY_PRBS7_SELECTED = 0 -DPHY_PRBS23_SELECTED = 1 -DPHY_PRBS11_SELECTED = 2 -DPHY_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_ENABLE' -DPHY_FEC_ENABLE__enumvalues = { - 0: 'DPHY_FEC_DISABLED', - 1: 'DPHY_FEC_ENABLED', -} -DPHY_FEC_DISABLED = 0 -DPHY_FEC_ENABLED = 1 -DPHY_FEC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'FEC_ACTIVE_STATUS' -FEC_ACTIVE_STATUS__enumvalues = { - 0: 'DPHY_FEC_NOT_ACTIVE', - 1: 'DPHY_FEC_ACTIVE', -} -DPHY_FEC_NOT_ACTIVE = 0 -DPHY_FEC_ACTIVE = 1 -FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_READY' -DPHY_FEC_READY__enumvalues = { - 0: 'DPHY_FEC_READY_EN', - 1: 'DPHY_FEC_READY_DIS', -} -DPHY_FEC_READY_EN = 0 -DPHY_FEC_READY_DIS = 1 -DPHY_FEC_READY = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_LOAD_BS_COUNT_START' -DPHY_LOAD_BS_COUNT_START__enumvalues = { - 0: 'DPHY_LOAD_BS_COUNT_STARTED', - 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', -} -DPHY_LOAD_BS_COUNT_STARTED = 0 -DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 -DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_EN' -DPHY_CRC_EN__enumvalues = { - 0: 'DPHY_CRC_DISABLED', - 1: 'DPHY_CRC_ENABLED', -} -DPHY_CRC_DISABLED = 0 -DPHY_CRC_ENABLED = 1 -DPHY_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_CONT_EN' -DPHY_CRC_CONT_EN__enumvalues = { - 0: 'DPHY_CRC_ONE_SHOT', - 1: 'DPHY_CRC_CONTINUOUS', -} -DPHY_CRC_ONE_SHOT = 0 -DPHY_CRC_CONTINUOUS = 1 -DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_FIELD' -DPHY_CRC_FIELD__enumvalues = { - 0: 'DPHY_CRC_START_FROM_TOP_FIELD', - 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', -} -DPHY_CRC_START_FROM_TOP_FIELD = 0 -DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 -DPHY_CRC_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_SEL' -DPHY_CRC_SEL__enumvalues = { - 0: 'DPHY_CRC_LANE0_SELECTED', - 1: 'DPHY_CRC_LANE1_SELECTED', - 2: 'DPHY_CRC_LANE2_SELECTED', - 3: 'DPHY_CRC_LANE3_SELECTED', -} -DPHY_CRC_LANE0_SELECTED = 0 -DPHY_CRC_LANE1_SELECTED = 1 -DPHY_CRC_LANE2_SELECTED = 2 -DPHY_CRC_LANE3_SELECTED = 3 -DPHY_CRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' -DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { - 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 1: 'DPHY_FAST_TRAINING_CAPABLE', -} -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 -DPHY_FAST_TRAINING_CAPABLE = 1 -DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_COLLISION_ACK' -DP_SEC_COLLISION_ACK__enumvalues = { - 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', - 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', -} -DP_SEC_COLLISION_ACK_NO_EFFECT = 0 -DP_SEC_COLLISION_ACK_CLR_FLAG = 1 -DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_AUDIO_MUTE' -DP_SEC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', - 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', -} -DP_SEC_AUDIO_MUTE_HW_CTRL = 0 -DP_SEC_AUDIO_MUTE_SW_CTRL = 1 -DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_TIMESTAMP_MODE' -DP_SEC_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', -} -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 -DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_PRIORITY' -DP_SEC_ASP_PRIORITY__enumvalues = { - 0: 'DP_SEC_ASP_LOW_PRIORITY', - 1: 'DP_SEC_ASP_HIGH_PRIORITY', -} -DP_SEC_ASP_LOW_PRIORITY = 0 -DP_SEC_ASP_HIGH_PRIORITY = 1 -DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' -DP_MSE_SAT_UPDATE_ACT__enumvalues = { - 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', - 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', -} -DP_MSE_SAT_UPDATE_NO_ACTION = 0 -DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 -DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 -DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_LINK_LINE' -DP_MSE_LINK_LINE__enumvalues = { - 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', - 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', - 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', - 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', -} -DP_MSE_LINK_LINE_32_MTP_LONG = 0 -DP_MSE_LINK_LINE_64_MTP_LONG = 1 -DP_MSE_LINK_LINE_128_MTP_LONG = 2 -DP_MSE_LINK_LINE_256_MTP_LONG = 3 -DP_MSE_LINK_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_BLANK_CODE' -DP_MSE_BLANK_CODE__enumvalues = { - 0: 'DP_MSE_BLANK_CODE_SF_FILLED', - 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', -} -DP_MSE_BLANK_CODE_SF_FILLED = 0 -DP_MSE_BLANK_CODE_ZERO_FILLED = 1 -DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_TIMESTAMP_MODE' -DP_MSE_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', -} -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 -DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_ZERO_ENCODER' -DP_MSE_ZERO_ENCODER__enumvalues = { - 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', - 1: 'DP_MSE_ZERO_FE_ENCODER', -} -DP_MSE_NOT_ZERO_FE_ENCODER = 0 -DP_MSE_ZERO_FE_ENCODER = 1 -DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' -DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { - 0: 'DP_DPHY_HBR2_PASS_THROUGH', - 1: 'DP_DPHY_HBR2_PATTERN_1', - 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', - 3: 'DP_DPHY_HBR2_PATTERN_3', - 6: 'DP_DPHY_HBR2_PATTERN_2_POS', -} -DP_DPHY_HBR2_PASS_THROUGH = 0 -DP_DPHY_HBR2_PATTERN_1 = 1 -DP_DPHY_HBR2_PATTERN_2_NEG = 2 -DP_DPHY_HBR2_PATTERN_3 = 3 -DP_DPHY_HBR2_PATTERN_2_POS = 6 -DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' -DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { - 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', - 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', -} -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 -DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 -DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SW_FAST_TRAINING_START' -DPHY_SW_FAST_TRAINING_START__enumvalues = { - 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 1: 'DPHY_SW_FAST_TRAINING_STARTED', -} -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 -DPHY_SW_FAST_TRAINING_STARTED = 1 -DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', -} -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' -DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' -DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' -DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { - 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', - 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', -} -MSA_V_TIMING_OVERRIDE_DISABLED = 0 -MSA_V_TIMING_OVERRIDE_ENABLED = 1 -DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_PRIORITY' -DP_SEC_GSP0_PRIORITY__enumvalues = { - 0: 'SEC_GSP0_PRIORITY_LOW', - 1: 'SEC_GSP0_PRIORITY_HIGH', -} -SEC_GSP0_PRIORITY_LOW = 0 -SEC_GSP0_PRIORITY_HIGH = 1 -DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND' -DP_SEC_GSP_SEND__enumvalues = { - 0: 'NOT_SENT', - 1: 'FORCE_SENT', -} -NOT_SENT = 0 -FORCE_SENT = 1 -DP_SEC_GSP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' -DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { - 0: 'SEND_AT_LINK_NUMBER', - 1: 'SEND_AT_EARLIEST_TIME', -} -SEND_AT_LINK_NUMBER = 0 -SEND_AT_EARLIEST_TIME = 1 -DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_LINE_REFERENCE' -DP_SEC_LINE_REFERENCE__enumvalues = { - 0: 'REFER_TO_DP_SOF', - 1: 'REFER_TO_OTG_SOF', -} -REFER_TO_DP_SOF = 0 -REFER_TO_OTG_SOF = 1 -DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_PPS' -DP_SEC_GSP_SEND_PPS__enumvalues = { - 0: 'SEND_NORMAL_PACKET', - 1: 'SEND_PPS_PACKET', -} -SEND_NORMAL_PACKET = 0 -SEND_PPS_PACKET = 1 -DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_ML_PHY_SEQ_MODE' -DP_ML_PHY_SEQ_MODE__enumvalues = { - 0: 'DP_ML_PHY_SEQ_LINE_NUM', - 1: 'DP_ML_PHY_SEQ_IMMEDIATE', -} -DP_ML_PHY_SEQ_LINE_NUM = 0 -DP_ML_PHY_SEQ_IMMEDIATE = 1 -DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' -DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { - 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', -} -DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 -DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 -DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DSC_MODE' -DP_DSC_MODE__enumvalues = { - 0: 'DP_DSC_DISABLE', - 1: 'DP_DSC_444_SIMPLE_422', - 2: 'DP_DSC_NATIVE_422_420', -} -DP_DSC_DISABLE = 0 -DP_DSC_444_SIMPLE_422 = 1 -DP_DSC_NATIVE_422_420 = 2 -DP_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_KEEPOUT_MODE' -HDMI_KEEPOUT_MODE__enumvalues = { - 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', -} -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 -HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' -HDMI_CLOCK_CHANNEL_RATE__enumvalues = { - 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', -} -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 -HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' -HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { - 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', - 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', -} -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 -HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_GEN_VERSION' -HDMI_PACKET_GEN_VERSION__enumvalues = { - 0: 'HDMI_PACKET_GEN_VERSION_OLD', - 1: 'HDMI_PACKET_GEN_VERSION_NEW', -} -HDMI_PACKET_GEN_VERSION_OLD = 0 -HDMI_PACKET_GEN_VERSION_NEW = 1 -HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_ACK' -HDMI_ERROR_ACK__enumvalues = { - 0: 'HDMI_ERROR_ACK_INT', - 1: 'HDMI_ERROR_NOT_ACK', -} -HDMI_ERROR_ACK_INT = 0 -HDMI_ERROR_NOT_ACK = 1 -HDMI_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_MASK' -HDMI_ERROR_MASK__enumvalues = { - 0: 'HDMI_ERROR_MASK_INT', - 1: 'HDMI_ERROR_NOT_MASK', -} -HDMI_ERROR_MASK_INT = 0 -HDMI_ERROR_NOT_MASK = 1 -HDMI_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' -HDMI_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', -} -HDMI_DEEP_COLOR_DEPTH_24BPP = 0 -HDMI_DEEP_COLOR_DEPTH_30BPP = 1 -HDMI_DEEP_COLOR_DEPTH_36BPP = 2 -HDMI_DEEP_COLOR_DEPTH_48BPP = 3 -HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_DELAY_EN' -HDMI_AUDIO_DELAY_EN__enumvalues = { - 0: 'HDMI_AUDIO_DELAY_DISABLE', - 1: 'HDMI_AUDIO_DELAY_58CLK', - 2: 'HDMI_AUDIO_DELAY_56CLK', - 3: 'HDMI_AUDIO_DELAY_RESERVED', -} -HDMI_AUDIO_DELAY_DISABLE = 0 -HDMI_AUDIO_DELAY_58CLK = 1 -HDMI_AUDIO_DELAY_56CLK = 2 -HDMI_AUDIO_DELAY_RESERVED = 3 -HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' -HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { - 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', -} -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 -HDMI_SEND_MAX_AUDIO_PACKETS = 1 -HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SEND' -HDMI_ACR_SEND__enumvalues = { - 0: 'HDMI_ACR_NOT_SEND', - 1: 'HDMI_ACR_PKT_SEND', -} -HDMI_ACR_NOT_SEND = 0 -HDMI_ACR_PKT_SEND = 1 -HDMI_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_CONT' -HDMI_ACR_CONT__enumvalues = { - 0: 'HDMI_ACR_CONT_DISABLE', - 1: 'HDMI_ACR_CONT_ENABLE', -} -HDMI_ACR_CONT_DISABLE = 0 -HDMI_ACR_CONT_ENABLE = 1 -HDMI_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SELECT' -HDMI_ACR_SELECT__enumvalues = { - 0: 'HDMI_ACR_SELECT_HW', - 1: 'HDMI_ACR_SELECT_32K', - 2: 'HDMI_ACR_SELECT_44K', - 3: 'HDMI_ACR_SELECT_48K', -} -HDMI_ACR_SELECT_HW = 0 -HDMI_ACR_SELECT_32K = 1 -HDMI_ACR_SELECT_44K = 2 -HDMI_ACR_SELECT_48K = 3 -HDMI_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SOURCE' -HDMI_ACR_SOURCE__enumvalues = { - 0: 'HDMI_ACR_SOURCE_HW', - 1: 'HDMI_ACR_SOURCE_SW', -} -HDMI_ACR_SOURCE_HW = 0 -HDMI_ACR_SOURCE_SW = 1 -HDMI_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_N_MULTIPLE' -HDMI_ACR_N_MULTIPLE__enumvalues = { - 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', - 1: 'HDMI_ACR_1_MULTIPLE', - 2: 'HDMI_ACR_2_MULTIPLE', - 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', - 4: 'HDMI_ACR_4_MULTIPLE', - 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', - 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', - 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', -} -HDMI_ACR_0_MULTIPLE_RESERVED = 0 -HDMI_ACR_1_MULTIPLE = 1 -HDMI_ACR_2_MULTIPLE = 2 -HDMI_ACR_3_MULTIPLE_RESERVED = 3 -HDMI_ACR_4_MULTIPLE = 4 -HDMI_ACR_5_MULTIPLE_RESERVED = 5 -HDMI_ACR_6_MULTIPLE_RESERVED = 6 -HDMI_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' -HDMI_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NULL_SEND' -HDMI_NULL_SEND__enumvalues = { - 0: 'HDMI_NULL_NOT_SEND', - 1: 'HDMI_NULL_PKT_SEND', -} -HDMI_NULL_NOT_SEND = 0 -HDMI_NULL_PKT_SEND = 1 -HDMI_NULL_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_SEND' -HDMI_GC_SEND__enumvalues = { - 0: 'HDMI_GC_NOT_SEND', - 1: 'HDMI_GC_PKT_SEND', -} -HDMI_GC_NOT_SEND = 0 -HDMI_GC_PKT_SEND = 1 -HDMI_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_CONT' -HDMI_GC_CONT__enumvalues = { - 0: 'HDMI_GC_CONT_DISABLE', - 1: 'HDMI_GC_CONT_ENABLE', -} -HDMI_GC_CONT_DISABLE = 0 -HDMI_GC_CONT_ENABLE = 1 -HDMI_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_SEND' -HDMI_ISRC_SEND__enumvalues = { - 0: 'HDMI_ISRC_NOT_SEND', - 1: 'HDMI_ISRC_PKT_SEND', -} -HDMI_ISRC_NOT_SEND = 0 -HDMI_ISRC_PKT_SEND = 1 -HDMI_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_CONT' -HDMI_ISRC_CONT__enumvalues = { - 0: 'HDMI_ISRC_CONT_DISABLE', - 1: 'HDMI_ISRC_CONT_ENABLE', -} -HDMI_ISRC_CONT_DISABLE = 0 -HDMI_ISRC_CONT_ENABLE = 1 -HDMI_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_SEND' -HDMI_AUDIO_INFO_SEND__enumvalues = { - 0: 'HDMI_AUDIO_INFO_NOT_SEND', - 1: 'HDMI_AUDIO_INFO_PKT_SEND', -} -HDMI_AUDIO_INFO_NOT_SEND = 0 -HDMI_AUDIO_INFO_PKT_SEND = 1 -HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_CONT' -HDMI_AUDIO_INFO_CONT__enumvalues = { - 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', - 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', -} -HDMI_AUDIO_INFO_CONT_DISABLE = 0 -HDMI_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_SEND' -HDMI_MPEG_INFO_SEND__enumvalues = { - 0: 'HDMI_MPEG_INFO_NOT_SEND', - 1: 'HDMI_MPEG_INFO_PKT_SEND', -} -HDMI_MPEG_INFO_NOT_SEND = 0 -HDMI_MPEG_INFO_PKT_SEND = 1 -HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_CONT' -HDMI_MPEG_INFO_CONT__enumvalues = { - 0: 'HDMI_MPEG_INFO_CONT_DISABLE', - 1: 'HDMI_MPEG_INFO_CONT_ENABLE', -} -HDMI_MPEG_INFO_CONT_DISABLE = 0 -HDMI_MPEG_INFO_CONT_ENABLE = 1 -HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_SEND' -HDMI_GENERIC_SEND__enumvalues = { - 0: 'HDMI_GENERIC_NOT_SEND', - 1: 'HDMI_GENERIC_PKT_SEND', -} -HDMI_GENERIC_NOT_SEND = 0 -HDMI_GENERIC_PKT_SEND = 1 -HDMI_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_CONT' -HDMI_GENERIC_CONT__enumvalues = { - 0: 'HDMI_GENERIC_CONT_DISABLE', - 1: 'HDMI_GENERIC_CONT_ENABLE', -} -HDMI_GENERIC_CONT_DISABLE = 0 -HDMI_GENERIC_CONT_ENABLE = 1 -HDMI_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE_CONT' -HDMI_GC_AVMUTE_CONT__enumvalues = { - 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', - 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', -} -HDMI_GC_AVMUTE_CONT_DISABLE = 0 -HDMI_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' -HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { - 0: 'HDMI_PACKING_PHASE_SET_BY_HW', - 1: 'HDMI_PACKING_PHASE_SET_BY_SW', -} -HDMI_PACKING_PHASE_SET_BY_HW = 0 -HDMI_PACKING_PHASE_SET_BY_SW = 1 -HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_PIXEL_ENCODING' -TMDS_PIXEL_ENCODING__enumvalues = { - 0: 'TMDS_PIXEL_ENCODING_444_OR_420', - 1: 'TMDS_PIXEL_ENCODING_422', -} -TMDS_PIXEL_ENCODING_444_OR_420 = 0 -TMDS_PIXEL_ENCODING_422 = 1 -TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_COLOR_FORMAT' -TMDS_COLOR_FORMAT__enumvalues = { - 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', - 3: 'TMDS_COLOR_FORMAT_RESERVED', -} -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 -TMDS_COLOR_FORMAT_DUAL30BPP = 2 -TMDS_COLOR_FORMAT_RESERVED = 3 -TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' -TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { - 0: 'TMDS_STEREOSYNC_CTL0', - 1: 'TMDS_STEREOSYNC_CTL1', - 2: 'TMDS_STEREOSYNC_CTL2', - 3: 'TMDS_STEREOSYNC_CTL3', -} -TMDS_STEREOSYNC_CTL0 = 0 -TMDS_STEREOSYNC_CTL1 = 1 -TMDS_STEREOSYNC_CTL2 = 2 -TMDS_STEREOSYNC_CTL3 = 3 -TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_SEL' -TMDS_CTL0_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', -} -TMDS_CTL0_DATA_SEL0_RESERVED = 0 -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL0_DATA_SEL2_VSYNC = 2 -TMDS_CTL0_DATA_SEL3_RESERVED = 3 -TMDS_CTL0_DATA_SEL4_HSYNC = 4 -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 -TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_INVERT' -TMDS_CTL0_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL0_DATA_NORMAL', - 1: 'TMDS_CTL0_DATA_INVERT_EN', -} -TMDS_CTL0_DATA_NORMAL = 0 -TMDS_CTL0_DATA_INVERT_EN = 1 -TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_MODULATION' -TMDS_CTL0_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', -} -TMDS_CTL0_DATA_MODULATION_DISABLE = 0 -TMDS_CTL0_DATA_MODULATION_BIT0 = 1 -TMDS_CTL0_DATA_MODULATION_BIT1 = 2 -TMDS_CTL0_DATA_MODULATION_BIT2 = 3 -TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' -TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', -} -TMDS_CTL0_PATTERN_OUT_DISABLE = 0 -TMDS_CTL0_PATTERN_OUT_ENABLE = 1 -TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_SEL' -TMDS_CTL1_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL1_DATA_SEL0_RESERVED = 0 -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL1_DATA_SEL2_VSYNC = 2 -TMDS_CTL1_DATA_SEL3_RESERVED = 3 -TMDS_CTL1_DATA_SEL4_HSYNC = 4 -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_INVERT' -TMDS_CTL1_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL1_DATA_NORMAL', - 1: 'TMDS_CTL1_DATA_INVERT_EN', -} -TMDS_CTL1_DATA_NORMAL = 0 -TMDS_CTL1_DATA_INVERT_EN = 1 -TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_MODULATION' -TMDS_CTL1_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', -} -TMDS_CTL1_DATA_MODULATION_DISABLE = 0 -TMDS_CTL1_DATA_MODULATION_BIT0 = 1 -TMDS_CTL1_DATA_MODULATION_BIT1 = 2 -TMDS_CTL1_DATA_MODULATION_BIT2 = 3 -TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' -TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', -} -TMDS_CTL1_PATTERN_OUT_DISABLE = 0 -TMDS_CTL1_PATTERN_OUT_ENABLE = 1 -TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_SEL' -TMDS_CTL2_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL2_DATA_SEL0_RESERVED = 0 -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL2_DATA_SEL2_VSYNC = 2 -TMDS_CTL2_DATA_SEL3_RESERVED = 3 -TMDS_CTL2_DATA_SEL4_HSYNC = 4 -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_INVERT' -TMDS_CTL2_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL2_DATA_NORMAL', - 1: 'TMDS_CTL2_DATA_INVERT_EN', -} -TMDS_CTL2_DATA_NORMAL = 0 -TMDS_CTL2_DATA_INVERT_EN = 1 -TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_MODULATION' -TMDS_CTL2_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', -} -TMDS_CTL2_DATA_MODULATION_DISABLE = 0 -TMDS_CTL2_DATA_MODULATION_BIT0 = 1 -TMDS_CTL2_DATA_MODULATION_BIT1 = 2 -TMDS_CTL2_DATA_MODULATION_BIT2 = 3 -TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' -TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', -} -TMDS_CTL2_PATTERN_OUT_DISABLE = 0 -TMDS_CTL2_PATTERN_OUT_ENABLE = 1 -TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_INVERT' -TMDS_CTL3_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL3_DATA_NORMAL', - 1: 'TMDS_CTL3_DATA_INVERT_EN', -} -TMDS_CTL3_DATA_NORMAL = 0 -TMDS_CTL3_DATA_INVERT_EN = 1 -TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_MODULATION' -TMDS_CTL3_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', -} -TMDS_CTL3_DATA_MODULATION_DISABLE = 0 -TMDS_CTL3_DATA_MODULATION_BIT0 = 1 -TMDS_CTL3_DATA_MODULATION_BIT1 = 2 -TMDS_CTL3_DATA_MODULATION_BIT2 = 3 -TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' -TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', -} -TMDS_CTL3_PATTERN_OUT_DISABLE = 0 -TMDS_CTL3_PATTERN_OUT_ENABLE = 1 -TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_SEL' -TMDS_CTL3_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL3_DATA_SEL0_RESERVED = 0 -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL3_DATA_SEL2_VSYNC = 2 -TMDS_CTL3_DATA_SEL3_RESERVED = 3 -TMDS_CTL3_DATA_SEL4_HSYNC = 4 -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' -DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { - 0: 'DIG_FE_SOURCE_FROM_OTG0', - 1: 'DIG_FE_SOURCE_FROM_OTG1', - 2: 'DIG_FE_SOURCE_FROM_OTG2', - 3: 'DIG_FE_SOURCE_FROM_OTG3', - 4: 'DIG_FE_SOURCE_FROM_OTG4', - 5: 'DIG_FE_SOURCE_FROM_OTG5', - 6: 'DIG_FE_SOURCE_RESERVED', -} -DIG_FE_SOURCE_FROM_OTG0 = 0 -DIG_FE_SOURCE_FROM_OTG1 = 1 -DIG_FE_SOURCE_FROM_OTG2 = 2 -DIG_FE_SOURCE_FROM_OTG3 = 3 -DIG_FE_SOURCE_FROM_OTG4 = 4 -DIG_FE_SOURCE_FROM_OTG5 = 5 -DIG_FE_SOURCE_RESERVED = 6 -DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' -DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { - 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', - 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', - 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', - 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', - 4: 'DIG_FE_STEREOSYNC_FROM_OTG4', - 5: 'DIG_FE_STEREOSYNC_FROM_OTG5', - 6: 'DIG_FE_STEREOSYNC_RESERVED', -} -DIG_FE_STEREOSYNC_FROM_OTG0 = 0 -DIG_FE_STEREOSYNC_FROM_OTG1 = 1 -DIG_FE_STEREOSYNC_FROM_OTG2 = 2 -DIG_FE_STEREOSYNC_FROM_OTG3 = 3 -DIG_FE_STEREOSYNC_FROM_OTG4 = 4 -DIG_FE_STEREOSYNC_FROM_OTG5 = 5 -DIG_FE_STEREOSYNC_RESERVED = 6 -DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' -DIG_FIFO_READ_CLOCK_SRC__enumvalues = { - 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', -} -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 -DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' -DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_ON_LINK0', - 1: 'DIG_OUTPUT_CRC_ON_LINK1', -} -DIG_OUTPUT_CRC_ON_LINK0 = 0 -DIG_OUTPUT_CRC_ON_LINK1 = 1 -DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' -DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 2: 'DIG_OUTPUT_CRC_FOR_VBI', - 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', -} -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 -DIG_OUTPUT_CRC_FOR_VBI = 2 -DIG_OUTPUT_CRC_FOR_AUDIO = 3 -DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_IN_NORMAL_OPERATION', - 1: 'DIG_IN_DEBUG_MODE', -} -DIG_IN_NORMAL_OPERATION = 0 -DIG_IN_DEBUG_MODE = 1 -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { - 0: 'DIG_10BIT_TEST_PATTERN', - 1: 'DIG_ALTERNATING_TEST_PATTERN', -} -DIG_10BIT_TEST_PATTERN = 0 -DIG_ALTERNATING_TEST_PATTERN = 1 -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_NORMAL', - 1: 'DIG_TEST_PATTERN_RANDOM', -} -DIG_TEST_PATTERN_NORMAL = 0 -DIG_TEST_PATTERN_RANDOM = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_ENABLED', - 1: 'DIG_RANDOM_PATTERN_RESETED', -} -DIG_RANDOM_PATTERN_ENABLED = 0 -DIG_RANDOM_PATTERN_RESETED = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' -DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', -} -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 -DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' -DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', -} -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 -DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' -DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', -} -DIG_FIFO_USE_OVERWRITE_LEVEL = 0 -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 -DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_ERROR_ACK' -DIG_FIFO_ERROR_ACK__enumvalues = { - 0: 'DIG_FIFO_ERROR_ACK_INT', - 1: 'DIG_FIFO_ERROR_NOT_ACK', -} -DIG_FIFO_ERROR_ACK_INT = 0 -DIG_FIFO_ERROR_NOT_ACK = 1 -DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' -DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', -} -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 -DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' -DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', - 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', -} -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 -DIG_FIFO_FORCE_RECOMP_MINMAX = 1 -DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' -AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { - 0: 'AFMT_INTERRUPT_DISABLE', - 1: 'AFMT_INTERRUPT_ENABLE', -} -AFMT_INTERRUPT_DISABLE = 0 -AFMT_INTERRUPT_ENABLE = 1 -AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE' -HDMI_GC_AVMUTE__enumvalues = { - 0: 'HDMI_GC_AVMUTE_SET', - 1: 'HDMI_GC_AVMUTE_UNSET', -} -HDMI_GC_AVMUTE_SET = 0 -HDMI_GC_AVMUTE_UNSET = 1 -HDMI_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEFAULT_PAHSE' -HDMI_DEFAULT_PAHSE__enumvalues = { - 0: 'HDMI_DEFAULT_PHASE_IS_0', - 1: 'HDMI_DEFAULT_PHASE_IS_1', -} -HDMI_DEFAULT_PHASE_IS_0 = 0 -HDMI_DEFAULT_PHASE_IS_1 = 1 -HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { - 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', -} -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum - -# values for enumeration 'AUDIO_LAYOUT_SELECT' -AUDIO_LAYOUT_SELECT__enumvalues = { - 0: 'AUDIO_LAYOUT_0', - 1: 'AUDIO_LAYOUT_1', -} -AUDIO_LAYOUT_0 = 0 -AUDIO_LAYOUT_1 = 1 -AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' -AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'AFMT_AUDIO_CRC_ONESHOT', - 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', -} -AFMT_AUDIO_CRC_ONESHOT = 0 -AFMT_AUDIO_CRC_AUTO_RESTART = 1 -AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' -AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { - 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', -} -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 -AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' -AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'AFMT_AUDIO_CRC_CH0_SIG', - 1: 'AFMT_AUDIO_CRC_CH1_SIG', - 2: 'AFMT_AUDIO_CRC_CH2_SIG', - 3: 'AFMT_AUDIO_CRC_CH3_SIG', - 4: 'AFMT_AUDIO_CRC_CH4_SIG', - 5: 'AFMT_AUDIO_CRC_CH5_SIG', - 6: 'AFMT_AUDIO_CRC_CH6_SIG', - 7: 'AFMT_AUDIO_CRC_CH7_SIG', - 8: 'AFMT_AUDIO_CRC_RESERVED_8', - 9: 'AFMT_AUDIO_CRC_RESERVED_9', - 10: 'AFMT_AUDIO_CRC_RESERVED_10', - 11: 'AFMT_AUDIO_CRC_RESERVED_11', - 12: 'AFMT_AUDIO_CRC_RESERVED_12', - 13: 'AFMT_AUDIO_CRC_RESERVED_13', - 14: 'AFMT_AUDIO_CRC_RESERVED_14', - 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', -} -AFMT_AUDIO_CRC_CH0_SIG = 0 -AFMT_AUDIO_CRC_CH1_SIG = 1 -AFMT_AUDIO_CRC_CH2_SIG = 2 -AFMT_AUDIO_CRC_CH3_SIG = 3 -AFMT_AUDIO_CRC_CH4_SIG = 4 -AFMT_AUDIO_CRC_CH5_SIG = 5 -AFMT_AUDIO_CRC_CH6_SIG = 6 -AFMT_AUDIO_CRC_CH7_SIG = 7 -AFMT_AUDIO_CRC_RESERVED_8 = 8 -AFMT_AUDIO_CRC_RESERVED_9 = 9 -AFMT_AUDIO_CRC_RESERVED_10 = 10 -AFMT_AUDIO_CRC_RESERVED_11 = 11 -AFMT_AUDIO_CRC_RESERVED_12 = 12 -AFMT_AUDIO_CRC_RESERVED_13 = 13 -AFMT_AUDIO_CRC_RESERVED_14 = 14 -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 -AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' -AFMT_RAMP_CONTROL0_SIGN__enumvalues = { - 0: 'AFMT_RAMP_SIGNED', - 1: 'AFMT_RAMP_UNSIGNED', -} -AFMT_RAMP_SIGNED = 0 -AFMT_RAMP_UNSIGNED = 1 -AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { - 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', -} -AFMT_AUDIO_PACKET_SENT_DISABLED = 0 -AFMT_AUDIO_PACKET_SENT_ENABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { - 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', -} -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' -AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { - 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', - 6: 'AFMT_AUDIO_SRC_RESERVED', -} -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 -AFMT_AUDIO_SRC_RESERVED = 6 -AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_MODE' -DIG_BE_CNTL_MODE__enumvalues = { - 0: 'DIG_BE_DP_SST_MODE', - 1: 'DIG_BE_RESERVED1', - 2: 'DIG_BE_TMDS_DVI_MODE', - 3: 'DIG_BE_TMDS_HDMI_MODE', - 4: 'DIG_BE_RESERVED4', - 5: 'DIG_BE_DP_MST_MODE', - 6: 'DIG_BE_RESERVED2', - 7: 'DIG_BE_RESERVED3', -} -DIG_BE_DP_SST_MODE = 0 -DIG_BE_RESERVED1 = 1 -DIG_BE_TMDS_DVI_MODE = 2 -DIG_BE_TMDS_HDMI_MODE = 3 -DIG_BE_RESERVED4 = 4 -DIG_BE_DP_MST_MODE = 5 -DIG_BE_RESERVED2 = 6 -DIG_BE_RESERVED3 = 7 -DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' -DIG_BE_CNTL_HPD_SELECT__enumvalues = { - 0: 'DIG_BE_CNTL_HPD1', - 1: 'DIG_BE_CNTL_HPD2', - 2: 'DIG_BE_CNTL_HPD3', - 3: 'DIG_BE_CNTL_HPD4', - 4: 'DIG_BE_CNTL_HPD5', - 5: 'DIG_BE_CNTL_HPD6', - 6: 'DIG_BE_CNTL_NO_HPD', -} -DIG_BE_CNTL_HPD1 = 0 -DIG_BE_CNTL_HPD2 = 1 -DIG_BE_CNTL_HPD3 = 2 -DIG_BE_CNTL_HPD4 = 3 -DIG_BE_CNTL_HPD5 = 4 -DIG_BE_CNTL_HPD6 = 5 -DIG_BE_CNTL_NO_HPD = 6 -DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', -} -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_SYNC_PHASE' -TMDS_SYNC_PHASE__enumvalues = { - 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', -} -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TMDS_SYNC_PHASE_ON_FRAME_START = 1 -TMDS_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' -TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { - 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', -} -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', -} -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' -TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' -TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', -} -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', -} -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', -} -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' -TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', -} -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 -TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' -TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', - 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', -} -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 -TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_VBI_GSP_INDEX' -AFMT_VBI_GSP_INDEX__enumvalues = { - 0: 'AFMT_VBI_GSP0_INDEX', - 1: 'AFMT_VBI_GSP1_INDEX', - 2: 'AFMT_VBI_GSP2_INDEX', - 3: 'AFMT_VBI_GSP3_INDEX', - 4: 'AFMT_VBI_GSP4_INDEX', - 5: 'AFMT_VBI_GSP5_INDEX', - 6: 'AFMT_VBI_GSP6_INDEX', - 7: 'AFMT_VBI_GSP7_INDEX', - 8: 'AFMT_VBI_GSP8_INDEX', - 9: 'AFMT_VBI_GSP9_INDEX', - 10: 'AFMT_VBI_GSP10_INDEX', -} -AFMT_VBI_GSP0_INDEX = 0 -AFMT_VBI_GSP1_INDEX = 1 -AFMT_VBI_GSP2_INDEX = 2 -AFMT_VBI_GSP3_INDEX = 3 -AFMT_VBI_GSP4_INDEX = 4 -AFMT_VBI_GSP5_INDEX = 5 -AFMT_VBI_GSP6_INDEX = 6 -AFMT_VBI_GSP7_INDEX = 7 -AFMT_VBI_GSP8_INDEX = 8 -AFMT_VBI_GSP9_INDEX = 9 -AFMT_VBI_GSP10_INDEX = 10 -AFMT_VBI_GSP_INDEX = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' -DIG_DIGITAL_BYPASS_SEL__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', -} -DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 -DIG_DIGITAL_BYPASS_SEL_36BPP = 1 -DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 -DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 -DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 -DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 -DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 -DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_INPUT_PIXEL_SEL' -DIG_INPUT_PIXEL_SEL__enumvalues = { - 0: 'DIG_ALL_PIXEL', - 1: 'DIG_EVEN_PIXEL_ONLY', - 2: 'DIG_ODD_PIXEL_ONLY', -} -DIG_ALL_PIXEL = 0 -DIG_EVEN_PIXEL_ONLY = 1 -DIG_ODD_PIXEL_ONLY = 2 -DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOLBY_VISION_ENABLE' -DOLBY_VISION_ENABLE__enumvalues = { - 0: 'DOLBY_VISION_ENABLED', - 1: 'DOLBY_VISION_DISABLED', -} -DOLBY_VISION_ENABLED = 0 -DOLBY_VISION_DISABLED = 1 -DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_HUBP_SEL' -METADATA_HUBP_SEL__enumvalues = { - 0: 'METADATA_HUBP_SEL_0', - 1: 'METADATA_HUBP_SEL_1', - 2: 'METADATA_HUBP_SEL_2', - 3: 'METADATA_HUBP_SEL_3', - 4: 'METADATA_HUBP_SEL_4', - 5: 'METADATA_HUBP_SEL_5', - 6: 'METADATA_HUBP_SEL_RESERVED', -} -METADATA_HUBP_SEL_0 = 0 -METADATA_HUBP_SEL_1 = 1 -METADATA_HUBP_SEL_2 = 2 -METADATA_HUBP_SEL_3 = 3 -METADATA_HUBP_SEL_4 = 4 -METADATA_HUBP_SEL_5 = 5 -METADATA_HUBP_SEL_RESERVED = 6 -METADATA_HUBP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_STREAM_TYPE_SEL' -METADATA_STREAM_TYPE_SEL__enumvalues = { - 0: 'METADATA_STREAM_DP', - 1: 'METADATA_STREAM_DVE', -} -METADATA_STREAM_DP = 0 -METADATA_STREAM_DVE = 1 -METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_METADATA_ENABLE' -HDMI_METADATA_ENABLE__enumvalues = { - 0: 'HDMI_METADATA_NOT_SEND', - 1: 'HDMI_METADATA_PKT_SEND', -} -HDMI_METADATA_NOT_SEND = 0 -HDMI_METADATA_PKT_SEND = 1 -HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' -HDMI_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'HDMI_PKT_LINE_REF_VSYNC', - 1: 'HDMI_PKT_LINE_REF_OTGSOF', -} -HDMI_PKT_LINE_REF_VSYNC = 0 -HDMI_PKT_LINE_REF_OTGSOF = 1 -HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' -DP_AUX_CONTROL_HPD_SEL__enumvalues = { - 0: 'DP_AUX_CONTROL_HPD1_SELECTED', - 1: 'DP_AUX_CONTROL_HPD2_SELECTED', - 2: 'DP_AUX_CONTROL_HPD3_SELECTED', - 3: 'DP_AUX_CONTROL_HPD4_SELECTED', - 4: 'DP_AUX_CONTROL_HPD5_SELECTED', - 5: 'DP_AUX_CONTROL_HPD6_SELECTED', - 6: 'DP_AUX_CONTROL_NO_HPD_SELECTED', -} -DP_AUX_CONTROL_HPD1_SELECTED = 0 -DP_AUX_CONTROL_HPD2_SELECTED = 1 -DP_AUX_CONTROL_HPD3_SELECTED = 2 -DP_AUX_CONTROL_HPD4_SELECTED = 3 -DP_AUX_CONTROL_HPD5_SELECTED = 4 -DP_AUX_CONTROL_HPD6_SELECTED = 5 -DP_AUX_CONTROL_NO_HPD_SELECTED = 6 -DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' -DP_AUX_CONTROL_TEST_MODE__enumvalues = { - 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', -} -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 -DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 -DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' -DP_AUX_SW_CONTROL_SW_GO__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 1: 'DP_AUX_SW_CONTROL_SW__GO', -} -DP_AUX_SW_CONTROL_SW__NOT_GO = 0 -DP_AUX_SW_CONTROL_SW__GO = 1 -DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' -DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', -} -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 -DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 -DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' -DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', -} -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 -DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', -} -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', -} -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_INT_ACK' -DP_AUX_INT_ACK__enumvalues = { - 0: 'DP_AUX_INT__NOT_ACK', - 1: 'DP_AUX_INT__ACK', -} -DP_AUX_INT__NOT_ACK = 0 -DP_AUX_INT__ACK = 1 -DP_AUX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_LS_UPDATE_ACK' -DP_AUX_LS_UPDATE_ACK__enumvalues = { - 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', - 1: 'DP_AUX_INT_LS_UPDATE_ACK', -} -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 -DP_AUX_INT_LS_UPDATE_ACK = 1 -DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', -} -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', -} -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', -} -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' -DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { - 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', - 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', -} -DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 -DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 -DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 -DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 -DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' -DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { - 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', - 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', - 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', -} -DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 -DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 -DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 -DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 -DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { - 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', -} -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', -} -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', -} -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', -} -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', -} -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' -DP_AUX_ERR_OCCURRED_ACK__enumvalues = { - 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 1: 'DP_AUX_ERR_OCCURRED__ACK', -} -DP_AUX_ERR_OCCURRED__NOT_ACK = 0 -DP_AUX_ERR_OCCURRED__ACK = 1 -DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' -DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { - 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', - 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', -} -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 -DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' -DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { - 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', -} -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 -DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET' -DP_AUX_RESET__enumvalues = { - 0: 'DP_AUX_RESET_DEASSERTED', - 1: 'DP_AUX_RESET_ASSERTED', -} -DP_AUX_RESET_DEASSERTED = 0 -DP_AUX_RESET_ASSERTED = 1 -DP_AUX_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET_DONE' -DP_AUX_RESET_DONE__enumvalues = { - 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 1: 'DP_AUX_RESET_SEQUENCE_DONE', -} -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 -DP_AUX_RESET_SEQUENCE_DONE = 1 -DP_AUX_RESET_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' -DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { - 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', -} -DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 -DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 -DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_GO' -DOUT_I2C_CONTROL_GO__enumvalues = { - 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 1: 'DOUT_I2C_CONTROL_START_TRANSFER', -} -DOUT_I2C_CONTROL_STOP_TRANSFER = 0 -DOUT_I2C_CONTROL_START_TRANSFER = 1 -DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' -DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', -} -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 -DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' -DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 1: 'DOUT_I2C_CONTROL__SEND_RESET', -} -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 -DOUT_I2C_CONTROL__SEND_RESET = 1 -DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' -DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { - 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', -} -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 -DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' -DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', -} -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 -DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 -DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' -DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', - 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', - 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', - 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', - 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', - 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', - 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', -} -DOUT_I2C_CONTROL_SELECT_DDC1 = 0 -DOUT_I2C_CONTROL_SELECT_DDC2 = 1 -DOUT_I2C_CONTROL_SELECT_DDC3 = 2 -DOUT_I2C_CONTROL_SELECT_DDC4 = 3 -DOUT_I2C_CONTROL_SELECT_DDC5 = 4 -DOUT_I2C_CONTROL_SELECT_DDC6 = 5 -DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 -DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' -DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_TRANS0', - 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', -} -DOUT_I2C_CONTROL_TRANS0 = 0 -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 -DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' -DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', -} -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 -DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', -} -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' -DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', -} -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 -DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', -} -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', -} -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ACK' -DOUT_I2C_ACK__enumvalues = { - 0: 'DOUT_I2C_NO_ACK', - 1: 'DOUT_I2C_ACK_TO_CLEAN', -} -DOUT_I2C_NO_ACK = 0 -DOUT_I2C_ACK_TO_CLEAN = 1 -DOUT_I2C_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' -DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { - 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', -} -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 -DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', -} -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_EDID_DETECT_STATUS' -DOUT_I2C_DDC_EDID_DETECT_STATUS__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED', -} -DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED = 0 -DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED = 1 -DOUT_I2C_DDC_EDID_DETECT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', -} -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' -DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { - 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', -} -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 -DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' -DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { - 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 1: 'DOUT_I2C_DATA__INDEX_WRITE', -} -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 -DOUT_I2C_DATA__INDEX_WRITE = 1 -DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', -} -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { - 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', -} -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' -DIOMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQUEST', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', -} -DIOMEM_NO_FORCE_REQUEST = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 -DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' -DIOMEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQ', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', -} -DIOMEM_NO_FORCE_REQ = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 -DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_DIS_CTRL' -DIOMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', -} -DIOMEM_ENABLE_MEM_PWR_CTRL = 0 -DIOMEM_DISABLE_MEM_PWR_CTRL = 1 -DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_EN' -CLOCK_GATING_EN__enumvalues = { - 0: 'CLOCK_GATING_ENABLE', - 1: 'CLOCK_GATING_DISABLE', -} -CLOCK_GATING_ENABLE = 0 -CLOCK_GATING_DISABLE = 1 -CLOCK_GATING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL' -DIOMEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 -DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' -DIOMEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', -} -DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 -DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 -DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PM_ASSERT_RESET' -PM_ASSERT_RESET__enumvalues = { - 0: 'PM_ASSERT_RESET_0', - 1: 'PM_ASSERT_RESET_1', -} -PM_ASSERT_RESET_0 = 0 -PM_ASSERT_RESET_1 = 1 -PM_ASSERT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DAC_MUX_SELECT' -DAC_MUX_SELECT__enumvalues = { - 0: 'DAC_MUX_SELECT_DACA', - 1: 'DAC_MUX_SELECT_DACB', -} -DAC_MUX_SELECT_DACA = 0 -DAC_MUX_SELECT_DACB = 1 -DAC_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_MUX_SELECT' -TMDS_MUX_SELECT__enumvalues = { - 0: 'TMDS_MUX_SELECT_B', - 1: 'TMDS_MUX_SELECT_G', - 2: 'TMDS_MUX_SELECT_R', - 3: 'TMDS_MUX_SELECT_RESERVED', -} -TMDS_MUX_SELECT_B = 0 -TMDS_MUX_SELECT_G = 1 -TMDS_MUX_SELECT_R = 2 -TMDS_MUX_SELECT_RESERVED = 3 -TMDS_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SOFT_RESET' -SOFT_RESET__enumvalues = { - 0: 'SOFT_RESET_0', - 1: 'SOFT_RESET_1', -} -SOFT_RESET_0 = 0 -SOFT_RESET_1 = 1 -SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_STEREOSYNC_SEL' -GENERIC_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERIC_STEREOSYNC_SEL_D1', - 1: 'GENERIC_STEREOSYNC_SEL_D2', - 2: 'GENERIC_STEREOSYNC_SEL_D3', - 3: 'GENERIC_STEREOSYNC_SEL_D4', - 4: 'GENERIC_STEREOSYNC_SEL_D5', - 5: 'GENERIC_STEREOSYNC_SEL_D6', - 6: 'GENERIC_STEREOSYNC_SEL_RESERVED', -} -GENERIC_STEREOSYNC_SEL_D1 = 0 -GENERIC_STEREOSYNC_SEL_D2 = 1 -GENERIC_STEREOSYNC_SEL_D3 = 2 -GENERIC_STEREOSYNC_SEL_D4 = 3 -GENERIC_STEREOSYNC_SEL_D5 = 4 -GENERIC_STEREOSYNC_SEL_D6 = 5 -GENERIC_STEREOSYNC_SEL_RESERVED = 6 -GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { - 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', -} -DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 -DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { - 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', -} -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICA_SEL' -DCIO_DC_GENERICA_SEL__enumvalues = { - 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', - 1: 'DCIO_GENERICA_SEL_STEREOSYNC', - 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', - 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', - 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', - 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', - 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', - 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', - 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', - 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', - 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 11: 'DCIO_GENERICA_SEL_SYNCEN', - 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', - 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', - 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', - 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', - 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', - 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', -} -DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 -DCIO_GENERICA_SEL_STEREOSYNC = 1 -DCIO_GENERICA_SEL_DACA_PIXCLK = 2 -DCIO_GENERICA_SEL_DACB_PIXCLK = 3 -DCIO_GENERICA_SEL_DVOA_CTL3 = 4 -DCIO_GENERICA_SEL_P1_PLLCLK = 5 -DCIO_GENERICA_SEL_P2_PLLCLK = 6 -DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 -DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 -DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 -DCIO_GENERICA_SEL_GENERICA_DCCG = 10 -DCIO_GENERICA_SEL_SYNCEN = 11 -DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 -DCIO_GENERICA_SEL_GENERICA_DPRX = 16 -DCIO_GENERICA_SEL_GENERICB_DPRX = 17 -DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', - 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', - 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', - 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', - 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', - 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', - 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', -} -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 -DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 -DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 -DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 -DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 -DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 -DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_CLK', -} -DCIO_UNIPHYA_FBDIV_CLK = 0 -DCIO_UNIPHYB_FBDIV_CLK = 1 -DCIO_UNIPHYC_FBDIV_CLK = 2 -DCIO_UNIPHYD_FBDIV_CLK = 3 -DCIO_UNIPHYE_FBDIV_CLK = 4 -DCIO_UNIPHYF_FBDIV_CLK = 5 -DCIO_UNIPHYG_FBDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', -} -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 -DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 -DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 -DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 -DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 -DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 -DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', -} -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICB_SEL' -DCIO_DC_GENERICB_SEL__enumvalues = { - 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', - 1: 'DCIO_GENERICB_SEL_STEREOSYNC', - 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', - 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', - 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', - 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', - 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', - 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', - 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', - 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', - 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 11: 'DCIO_GENERICB_SEL_SYNCEN', - 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', - 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', - 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', - 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', -} -DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 -DCIO_GENERICB_SEL_STEREOSYNC = 1 -DCIO_GENERICB_SEL_DACA_PIXCLK = 2 -DCIO_GENERICB_SEL_DACB_PIXCLK = 3 -DCIO_GENERICB_SEL_DVOA_CTL3 = 4 -DCIO_GENERICB_SEL_P1_PLLCLK = 5 -DCIO_GENERICB_SEL_P2_PLLCLK = 6 -DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 -DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 -DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 -DCIO_GENERICB_SEL_GENERICB_DCCG = 10 -DCIO_GENERICB_SEL_SYNCEN = 11 -DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 -DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', - 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', -} -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', -} -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' -DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { - 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', - 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', - 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', - 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', - 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', - 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', - 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', - 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', -} -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 -DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', -} -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 -DCIO_UNIPHY_CHANNEL_INVERTED = 1 -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { - 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', -} -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', -} -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' -DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { - 0: 'DCIO_VIP_MUX_EN_DVO', - 1: 'DCIO_VIP_MUX_EN_VIP', -} -DCIO_VIP_MUX_EN_DVO = 0 -DCIO_VIP_MUX_EN_VIP = 1 -DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' -DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { - 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', - 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', -} -DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 -DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 -DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' -DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { - 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', - 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', -} -DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 -DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 -DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' -DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { - 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', - 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', -} -DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 -DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 -DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' -DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { - 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', - 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', -} -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { - 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', - 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', -} -DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 -DCIO_LVTMA_SYNCEN_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { - 0: 'DCIO_LVTMA_DIGON_OFF', - 1: 'DCIO_LVTMA_DIGON_ON', -} -DCIO_LVTMA_DIGON_OFF = 0 -DCIO_LVTMA_DIGON_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { - 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', - 1: 'DCIO_LVTMA_DIGON_POL_INVERT', -} -DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 -DCIO_LVTMA_DIGON_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { - 0: 'DCIO_LVTMA_BLON_OFF', - 1: 'DCIO_LVTMA_BLON_ON', -} -DCIO_LVTMA_BLON_OFF = 0 -DCIO_LVTMA_BLON_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { - 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', - 1: 'DCIO_LVTMA_BLON_POL_INVERT', -} -DCIO_LVTMA_BLON_POL_NON_INVERT = 0 -DCIO_LVTMA_BLON_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' -DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { - 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', - 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', -} -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 -DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' -DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { - 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', - 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', -} -DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 -DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 -DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' -DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { - 0: 'DCIO_BL_PWM_DISABLE', - 1: 'DCIO_BL_PWM_ENABLE', -} -DCIO_BL_PWM_DISABLE = 0 -DCIO_BL_PWM_ENABLE = 1 -DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { - 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', -} -DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 -DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { - 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', - 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', -} -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' -DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', - 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', -} -DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 -DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 -DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', -} -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', -} -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', -} -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', -} -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_SEL' -DCIO_GSL_SEL__enumvalues = { - 0: 'DCIO_GSL_SEL_GROUP_0', - 1: 'DCIO_GSL_SEL_GROUP_1', - 2: 'DCIO_GSL_SEL_GROUP_2', -} -DCIO_GSL_SEL_GROUP_0 = 0 -DCIO_GSL_SEL_GROUP_1 = 1 -DCIO_GSL_SEL_GROUP_2 = 2 -DCIO_GSL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' -DCIO_GENLK_CLK_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', - 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', -} -DCIO_GENLK_CLK_GSL_MASK_NO = 0 -DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 -DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 -DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' -DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', -} -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 -DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' -DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' -DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' -DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DCIO_GPU_TIMER_START_0_END_27', - 1: 'DCIO_GPU_TIMER_START_1_END_28', - 2: 'DCIO_GPU_TIMER_START_2_END_29', - 3: 'DCIO_GPU_TIMER_START_3_END_30', - 4: 'DCIO_GPU_TIMER_START_4_END_31', - 5: 'DCIO_GPU_TIMER_START_6_END_33', - 6: 'DCIO_GPU_TIMER_START_8_END_35', - 7: 'DCIO_GPU_TIMER_START_10_END_37', -} -DCIO_GPU_TIMER_START_0_END_27 = 0 -DCIO_GPU_TIMER_START_1_END_28 = 1 -DCIO_GPU_TIMER_START_2_END_29 = 2 -DCIO_GPU_TIMER_START_3_END_30 = 3 -DCIO_GPU_TIMER_START_4_END_31 = 4 -DCIO_GPU_TIMER_START_6_END_33 = 5 -DCIO_GPU_TIMER_START_8_END_35 = 6 -DCIO_GPU_TIMER_START_10_END_37 = 7 -DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { - 0: 'DCIO_TEST_CLK_SEL_DISPCLK', - 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', - 2: 'DCIO_TEST_CLK_SEL_SOCCLK', -} -DCIO_TEST_CLK_SEL_DISPCLK = 0 -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 -DCIO_TEST_CLK_SEL_SOCCLK = 2 -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { - 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', -} -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' -DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 1: 'DCIO_EXT_VSYNC_MUX_OTG0', - 2: 'DCIO_EXT_VSYNC_MUX_OTG1', - 3: 'DCIO_EXT_VSYNC_MUX_OTG2', - 4: 'DCIO_EXT_VSYNC_MUX_OTG3', - 5: 'DCIO_EXT_VSYNC_MUX_OTG4', - 6: 'DCIO_EXT_VSYNC_MUX_OTG5', - 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', -} -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 -DCIO_EXT_VSYNC_MUX_OTG0 = 1 -DCIO_EXT_VSYNC_MUX_OTG1 = 2 -DCIO_EXT_VSYNC_MUX_OTG2 = 3 -DCIO_EXT_VSYNC_MUX_OTG3 = 4 -DCIO_EXT_VSYNC_MUX_OTG4 = 5 -DCIO_EXT_VSYNC_MUX_OTG5 = 6 -DCIO_EXT_VSYNC_MUX_GENERICB = 7 -DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' -DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MASK_NONE', - 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', - 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', - 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', - 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', - 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', - 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', - 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', -} -DCIO_EXT_VSYNC_MASK_NONE = 0 -DCIO_EXT_VSYNC_MASK_PIPE0 = 1 -DCIO_EXT_VSYNC_MASK_PIPE1 = 2 -DCIO_EXT_VSYNC_MASK_PIPE2 = 3 -DCIO_EXT_VSYNC_MASK_PIPE3 = 4 -DCIO_EXT_VSYNC_MASK_PIPE4 = 5 -DCIO_EXT_VSYNC_MASK_PIPE5 = 6 -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 -DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DSYNC_SOFT_RESET' -DCIO_DSYNC_SOFT_RESET__enumvalues = { - 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', -} -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 -DCIO_DSYNC_SOFT_RESET_ASSERT = 1 -DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DACA_SOFT_RESET' -DCIO_DACA_SOFT_RESET__enumvalues = { - 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', - 1: 'DCIO_DACA_SOFT_RESET_ASSERT', -} -DCIO_DACA_SOFT_RESET_DEASSERT = 0 -DCIO_DACA_SOFT_RESET_ASSERT = 1 -DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' -DCIO_DCRXPHY_SOFT_RESET__enumvalues = { - 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', -} -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 -DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPHY_LANE_SEL' -DCIO_DPHY_LANE_SEL__enumvalues = { - 0: 'DCIO_DPHY_LANE_SEL_LANE0', - 1: 'DCIO_DPHY_LANE_SEL_LANE1', - 2: 'DCIO_DPHY_LANE_SEL_LANE2', - 3: 'DCIO_DPHY_LANE_SEL_LANE3', -} -DCIO_DPHY_LANE_SEL_LANE0 = 0 -DCIO_DPHY_LANE_SEL_LANE1 = 1 -DCIO_DPHY_LANE_SEL_LANE2 = 2 -DCIO_DPHY_LANE_SEL_LANE3 = 3 -DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' -DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', -} -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 -DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' -DCIO_DPCS_INTERRUPT_MASK__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_DISABLE', - 1: 'DCIO_DPCS_INTERRUPT_ENABLE', -} -DCIO_DPCS_INTERRUPT_DISABLE = 0 -DCIO_DPCS_INTERRUPT_ENABLE = 1 -DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' -DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', -} -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 -DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_IMPCAL_STEP_DELAY' -DCIO_IMPCAL_STEP_DELAY__enumvalues = { - 0: 'DCIO_IMPCAL_STEP_DELAY_1us', - 1: 'DCIO_IMPCAL_STEP_DELAY_2us', - 2: 'DCIO_IMPCAL_STEP_DELAY_3us', - 3: 'DCIO_IMPCAL_STEP_DELAY_4us', - 4: 'DCIO_IMPCAL_STEP_DELAY_5us', - 5: 'DCIO_IMPCAL_STEP_DELAY_6us', - 6: 'DCIO_IMPCAL_STEP_DELAY_7us', - 7: 'DCIO_IMPCAL_STEP_DELAY_8us', - 8: 'DCIO_IMPCAL_STEP_DELAY_9us', - 9: 'DCIO_IMPCAL_STEP_DELAY_10us', - 10: 'DCIO_IMPCAL_STEP_DELAY_11us', - 11: 'DCIO_IMPCAL_STEP_DELAY_12us', - 12: 'DCIO_IMPCAL_STEP_DELAY_13us', - 13: 'DCIO_IMPCAL_STEP_DELAY_14us', - 14: 'DCIO_IMPCAL_STEP_DELAY_15us', - 15: 'DCIO_IMPCAL_STEP_DELAY_16us', -} -DCIO_IMPCAL_STEP_DELAY_1us = 0 -DCIO_IMPCAL_STEP_DELAY_2us = 1 -DCIO_IMPCAL_STEP_DELAY_3us = 2 -DCIO_IMPCAL_STEP_DELAY_4us = 3 -DCIO_IMPCAL_STEP_DELAY_5us = 4 -DCIO_IMPCAL_STEP_DELAY_6us = 5 -DCIO_IMPCAL_STEP_DELAY_7us = 6 -DCIO_IMPCAL_STEP_DELAY_8us = 7 -DCIO_IMPCAL_STEP_DELAY_9us = 8 -DCIO_IMPCAL_STEP_DELAY_10us = 9 -DCIO_IMPCAL_STEP_DELAY_11us = 10 -DCIO_IMPCAL_STEP_DELAY_12us = 11 -DCIO_IMPCAL_STEP_DELAY_13us = 12 -DCIO_IMPCAL_STEP_DELAY_14us = 13 -DCIO_IMPCAL_STEP_DELAY_15us = 14 -DCIO_IMPCAL_STEP_DELAY_16us = 15 -DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' -DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { - 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', -} -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 -DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_HPD_SEL' -DCIOCHIP_HPD_SEL__enumvalues = { - 0: 'DCIOCHIP_HPD_SEL_ASYNC', - 1: 'DCIOCHIP_HPD_SEL_CLOCKED', -} -DCIOCHIP_HPD_SEL_ASYNC = 0 -DCIOCHIP_HPD_SEL_CLOCKED = 1 -DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PAD_MODE' -DCIOCHIP_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_PAD_MODE_DDC', - 1: 'DCIOCHIP_PAD_MODE_DP', -} -DCIOCHIP_PAD_MODE_DDC = 0 -DCIOCHIP_PAD_MODE_DP = 1 -DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' -DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', - 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', -} -DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 -DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 -DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_INVERT' -DCIOCHIP_INVERT__enumvalues = { - 0: 'DCIOCHIP_POL_NON_INVERT', - 1: 'DCIOCHIP_POL_INVERT', -} -DCIOCHIP_POL_NON_INVERT = 0 -DCIOCHIP_POL_INVERT = 1 -DCIOCHIP_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PD_EN' -DCIOCHIP_PD_EN__enumvalues = { - 0: 'DCIOCHIP_PD_EN_NOTALLOW', - 1: 'DCIOCHIP_PD_EN_ALLOW', -} -DCIOCHIP_PD_EN_NOTALLOW = 0 -DCIOCHIP_PD_EN_ALLOW = 1 -DCIOCHIP_PD_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' -DCIOCHIP_GPIO_MASK_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', -} -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 -DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK' -DCIOCHIP_MASK__enumvalues = { - 0: 'DCIOCHIP_MASK_DISABLE', - 1: 'DCIOCHIP_MASK_ENABLE', -} -DCIOCHIP_MASK_DISABLE = 0 -DCIOCHIP_MASK_ENABLE = 1 -DCIOCHIP_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' -DCIOCHIP_GPIO_I2C_MASK__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', - 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', -} -DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 -DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 -DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' -DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', - 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', -} -DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 -DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 -DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_EN' -DCIOCHIP_GPIO_I2C_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_DISABLE', - 1: 'DCIOCHIP_GPIO_I2C_ENABLE', -} -DCIOCHIP_GPIO_I2C_DISABLE = 0 -DCIOCHIP_GPIO_I2C_ENABLE = 1 -DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_4BIT' -DCIOCHIP_MASK_4BIT__enumvalues = { - 0: 'DCIOCHIP_MASK_4BIT_DISABLE', - 15: 'DCIOCHIP_MASK_4BIT_ENABLE', -} -DCIOCHIP_MASK_4BIT_DISABLE = 0 -DCIOCHIP_MASK_4BIT_ENABLE = 15 -DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_4BIT' -DCIOCHIP_ENABLE_4BIT__enumvalues = { - 0: 'DCIOCHIP_4BIT_DISABLE', - 15: 'DCIOCHIP_4BIT_ENABLE', -} -DCIOCHIP_4BIT_DISABLE = 0 -DCIOCHIP_4BIT_ENABLE = 15 -DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_5BIT' -DCIOCHIP_MASK_5BIT__enumvalues = { - 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', - 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', -} -DCIOCHIP_MASIK_5BIT_DISABLE = 0 -DCIOCHIP_MASIK_5BIT_ENABLE = 31 -DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_5BIT' -DCIOCHIP_ENABLE_5BIT__enumvalues = { - 0: 'DCIOCHIP_5BIT_DISABLE', - 31: 'DCIOCHIP_5BIT_ENABLE', -} -DCIOCHIP_5BIT_DISABLE = 0 -DCIOCHIP_5BIT_ENABLE = 31 -DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_2BIT' -DCIOCHIP_MASK_2BIT__enumvalues = { - 0: 'DCIOCHIP_MASK_2BIT_DISABLE', - 3: 'DCIOCHIP_MASK_2BIT_ENABLE', -} -DCIOCHIP_MASK_2BIT_DISABLE = 0 -DCIOCHIP_MASK_2BIT_ENABLE = 3 -DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_2BIT' -DCIOCHIP_ENABLE_2BIT__enumvalues = { - 0: 'DCIOCHIP_2BIT_DISABLE', - 3: 'DCIOCHIP_2BIT_ENABLE', -} -DCIOCHIP_2BIT_DISABLE = 0 -DCIOCHIP_2BIT_ENABLE = 3 -DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' -DCIOCHIP_REF_27_SRC_SEL__enumvalues = { - 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', -} -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 -DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_DVO_VREFPON' -DCIOCHIP_DVO_VREFPON__enumvalues = { - 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', - 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', -} -DCIOCHIP_DVO_VREFPON_DISABLE = 0 -DCIOCHIP_DVO_VREFPON_ENABLE = 1 -DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_DVO_VREFSEL' -DCIOCHIP_DVO_VREFSEL__enumvalues = { - 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', - 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', -} -DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 -DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 -DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_SPDIF1_IMODE' -DCIOCHIP_SPDIF1_IMODE__enumvalues = { - 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', - 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', -} -DCIOCHIP_SPDIF1_IMODE_OE_A = 0 -DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 -DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' -DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', - 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', -} -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 -DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' -DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', - 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', - 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', -} -DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 -DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 -DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 -DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 -DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' -DCIOCHIP_AUX_SPIKESEL__enumvalues = { - 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', - 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', -} -DCIOCHIP_AUX_SPIKESEL_50NS = 0 -DCIOCHIP_AUX_SPIKESEL_10NS = 1 -DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' -DCIOCHIP_AUX_CSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', -} -DCIOCHIP_AUX_CSEL_DEC1P0 = 0 -DCIOCHIP_AUX_CSEL_DEC0P9 = 1 -DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' -DCIOCHIP_AUX_CSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_INC1P0', - 1: 'DCIOCHIP_AUX_CSEL_INC1P1', -} -DCIOCHIP_AUX_CSEL_INC1P0 = 0 -DCIOCHIP_AUX_CSEL_INC1P1 = 1 -DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' -DCIOCHIP_AUX_RSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', -} -DCIOCHIP_AUX_RSEL_DEC1P0 = 0 -DCIOCHIP_AUX_RSEL_DEC0P9 = 1 -DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' -DCIOCHIP_AUX_RSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_INC1P0', - 1: 'DCIOCHIP_AUX_RSEL_INC1P1', -} -DCIOCHIP_AUX_RSEL_INC1P0 = 0 -DCIOCHIP_AUX_RSEL_INC1P1 = 1 -DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' -DCIOCHIP_AUX_HYS_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_HYS_TUNE_0', - 1: 'DCIOCHIP_AUX_HYS_TUNE_1', - 2: 'DCIOCHIP_AUX_HYS_TUNE_2', - 3: 'DCIOCHIP_AUX_HYS_TUNE_3', -} -DCIOCHIP_AUX_HYS_TUNE_0 = 0 -DCIOCHIP_AUX_HYS_TUNE_1 = 1 -DCIOCHIP_AUX_HYS_TUNE_2 = 2 -DCIOCHIP_AUX_HYS_TUNE_3 = 3 -DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' -DCIOCHIP_AUX_VOD_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_VOD_TUNE_0', - 1: 'DCIOCHIP_AUX_VOD_TUNE_1', - 2: 'DCIOCHIP_AUX_VOD_TUNE_2', - 3: 'DCIOCHIP_AUX_VOD_TUNE_3', -} -DCIOCHIP_AUX_VOD_TUNE_0 = 0 -DCIOCHIP_AUX_VOD_TUNE_1 = 1 -DCIOCHIP_AUX_VOD_TUNE_2 = 2 -DCIOCHIP_AUX_VOD_TUNE_3 = 3 -DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' -DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { - 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', - 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', -} -DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 -DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 -DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_COMPSEL' -DCIOCHIP_I2C_COMPSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_REC_SCHMIT', - 1: 'DCIOCHIP_I2C_REC_COMPARATOR', -} -DCIOCHIP_I2C_REC_SCHMIT = 0 -DCIOCHIP_I2C_REC_COMPARATOR = 1 -DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' -DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { - 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', - 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', -} -DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 -DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 -DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' -DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', - 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', -} -DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 -DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 -DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 -DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 -DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' -DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', - 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', -} -DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 -DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 -DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 -DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 -DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_GLOBAL_CAPABILITIES' -AZ_GLOBAL_CAPABILITIES__enumvalues = { - 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', -} -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 -AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { - 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', - 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', -} -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' -GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { - 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 1: 'FLUSH_CONTROL_FLUSH_STARTED', -} -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 -FLUSH_CONTROL_FLUSH_STARTED = 1 -GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' -GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { - 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', -} -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 -GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_STATE_CHANGE_STATUS' -AZ_STATE_CHANGE_STATUS__enumvalues = { - 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', -} -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 -AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' -GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { - 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', -} -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 -GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_0_SYNCHRONIZATION' -STREAM_0_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_1_SYNCHRONIZATION' -STREAM_1_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_2_SYNCHRONIZATION' -STREAM_2_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_3_SYNCHRONIZATION' -STREAM_3_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_4_SYNCHRONIZATION' -STREAM_4_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_5_SYNCHRONIZATION' -STREAM_5_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_6_SYNCHRONIZATION' -STREAM_6_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_7_SYNCHRONIZATION' -STREAM_7_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_8_SYNCHRONIZATION' -STREAM_8_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_9_SYNCHRONIZATION' -STREAM_9_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_10_SYNCHRONIZATION' -STREAM_10_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_11_SYNCHRONIZATION' -STREAM_11_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_12_SYNCHRONIZATION' -STREAM_12_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_13_SYNCHRONIZATION' -STREAM_13_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_14_SYNCHRONIZATION' -STREAM_14_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_15_SYNCHRONIZATION' -STREAM_15_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'CORB_READ_POINTER_RESET' -CORB_READ_POINTER_RESET__enumvalues = { - 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', -} -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 -CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_CORB_SIZE' -AZ_CORB_SIZE__enumvalues = { - 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_CORB_SIZE_256ENTRIES', - 3: 'AZ_CORB_SIZE_RESERVED', -} -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 -AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 -AZ_CORB_SIZE_256ENTRIES = 2 -AZ_CORB_SIZE_RESERVED = 3 -AZ_CORB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' -AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { - 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', - 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', -} -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 -AZ_RIRB_WRITE_POINTER_DO_RESET = 1 -AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_SIZE' -AZ_RIRB_SIZE__enumvalues = { - 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_RIRB_SIZE_256ENTRIES', - 3: 'AZ_RIRB_SIZE_UNDEFINED', -} -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 -AZ_RIRB_SIZE_256ENTRIES = 2 -AZ_RIRB_SIZE_UNDEFINED = 3 -AZ_RIRB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum - -# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { - 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', -} -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', -} -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL' -MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'NO_FORCE_REQUEST', - 1: 'FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FORCE_DEEP_SLEEP_REQUEST', - 3: 'FORCE_SHUT_DOWN_REQUEST', -} -NO_FORCE_REQUEST = 0 -FORCE_LIGHT_SLEEP_REQUEST = 1 -FORCE_DEEP_SLEEP_REQUEST = 2 -FORCE_SHUT_DOWN_REQUEST = 3 -MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL2' -MEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'NO_FORCE_REQ', - 1: 'FORCE_LIGHT_SLEEP_REQ', -} -NO_FORCE_REQ = 0 -FORCE_LIGHT_SLEEP_REQ = 1 -MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_CTRL' -MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'ENABLE_MEM_PWR_CTRL', - 1: 'DISABLE_MEM_PWR_CTRL', -} -ENABLE_MEM_PWR_CTRL = 0 -DISABLE_MEM_PWR_CTRL = 1 -MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL' -MEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DYNAMIC_SHUT_DOWN_ENABLE = 0 -DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL2' -MEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DYNAMIC_DEEP_SLEEP_EN', - 1: 'DYNAMIC_LIGHT_SLEEP_EN', -} -DYNAMIC_DEEP_SLEEP_EN = 0 -DYNAMIC_LIGHT_SLEEP_EN = 1 -MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { - 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', -} -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { - 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', -} -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' -AZ_LATENCY_COUNTER_CONTROL__enumvalues = { - 0: 'AZ_LATENCY_COUNTER_NO_RESET', - 1: 'AZ_LATENCY_COUNTER_RESET_DONE', -} -AZ_LATENCY_COUNTER_NO_RESET = 0 -AZ_LATENCY_COUNTER_RESET_DONE = 1 -AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', -} -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ICH_RESET_ENUM' -DSCC_ICH_RESET_ENUM__enumvalues = { - 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', -} -DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 -DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 -DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 -DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 -DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' -DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', -} -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 -DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' -DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', -} -DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 -DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' -DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { - 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', -} -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 -DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' -DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ENABLE_ENUM' -DSCC_ENABLE_ENUM__enumvalues = { - 0: 'DSCC_ENABLE_ENUM_DISABLED', - 1: 'DSCC_ENABLE_ENUM_ENABLED', -} -DSCC_ENABLE_ENUM_DISABLED = 0 -DSCC_ENABLE_ENUM_ENABLED = 1 -DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' -DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', -} -DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 -DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'POWER_STATE_ENUM' -POWER_STATE_ENUM__enumvalues = { - 0: 'POWER_STATE_ENUM_ON', - 1: 'POWER_STATE_ENUM_LS', - 2: 'POWER_STATE_ENUM_DS', - 3: 'POWER_STATE_ENUM_SD', -} -POWER_STATE_ENUM_ON = 0 -POWER_STATE_ENUM_LS = 1 -POWER_STATE_ENUM_DS = 2 -POWER_STATE_ENUM_SD = 3 -POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' -DSCC_MEM_PWR_DIS_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', - 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', -} -DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 -DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 -DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_ENABLE_ENUM' -DSCCIF_ENABLE_ENUM__enumvalues = { - 0: 'DSCCIF_ENABLE_ENUM_DISABLED', - 1: 'DSCCIF_ENABLE_ENUM_ENABLED', -} -DSCCIF_ENABLE_ENUM_DISABLED = 0 -DSCCIF_ENABLE_ENUM_ENABLED = 1 -DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' -DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', -} -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' -DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_ENUM' -ENABLE_ENUM__enumvalues = { - 0: 'ENABLE_ENUM_DISABLED', - 1: 'ENABLE_ENUM_ENABLED', -} -ENABLE_ENUM_DISABLED = 0 -ENABLE_ENUM_ENABLED = 1 -ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' -CLOCK_GATING_DISABLE_ENUM__enumvalues = { - 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', - 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', -} -CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 -CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 -CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' -TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { - 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', -} -TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 -TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 -TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 -TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 -TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 -TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 -TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_ENABLE_ENUM' -WB_ENABLE_ENUM__enumvalues = { - 0: 'WB_EN_DISABLE', - 1: 'WB_EN_ENABLE', -} -WB_EN_DISABLE = 0 -WB_EN_ENABLE = 1 -WB_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_CLK_GATE_DIS_ENUM' -WB_CLK_GATE_DIS_ENUM__enumvalues = { - 0: 'WB_CLK_GATE_ENABLE', - 1: 'WB_CLK_GATE_DISABLE', -} -WB_CLK_GATE_ENABLE = 0 -WB_CLK_GATE_DISABLE = 1 -WB_CLK_GATE_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_MEM_PWR_DIS_ENUM' -WB_MEM_PWR_DIS_ENUM__enumvalues = { - 0: 'WB_MEM_PWR_ENABLE', - 1: 'WB_MEM_PWR_DISABLE', -} -WB_MEM_PWR_ENABLE = 0 -WB_MEM_PWR_DISABLE = 1 -WB_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_TEST_CLK_SEL_ENUM' -WB_TEST_CLK_SEL_ENUM__enumvalues = { - 0: 'WB_TEST_CLK_SEL_REG', - 1: 'WB_TEST_CLK_SEL_WB', - 2: 'WB_TEST_CLK_SEL_WBSCL', - 3: 'WB_TEST_CLK_SEL_PERM', -} -WB_TEST_CLK_SEL_REG = 0 -WB_TEST_CLK_SEL_WB = 1 -WB_TEST_CLK_SEL_WBSCL = 2 -WB_TEST_CLK_SEL_PERM = 3 -WB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM' -WBSCL_LB_MEM_PWR_MODE_SEL_ENUM__enumvalues = { - 0: 'WBSCL_LB_MEM_PWR_MODE_SEL_SD', - 1: 'WBSCL_LB_MEM_PWR_MODE_SEL_DS', - 2: 'WBSCL_LB_MEM_PWR_MODE_SEL_LS', - 3: 'WBSCL_LB_MEM_PWR_MODE_SEL_ON', -} -WBSCL_LB_MEM_PWR_MODE_SEL_SD = 0 -WBSCL_LB_MEM_PWR_MODE_SEL_DS = 1 -WBSCL_LB_MEM_PWR_MODE_SEL_LS = 2 -WBSCL_LB_MEM_PWR_MODE_SEL_ON = 3 -WBSCL_LB_MEM_PWR_MODE_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_LB_MEM_PWR_FORCE_ENUM' -WBSCL_LB_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'WBSCL_LB_MEM_PWR_FORCE_NO', - 1: 'WBSCL_LB_MEM_PWR_FORCE_LS', - 2: 'WBSCL_LB_MEM_PWR_FORCE_DS', - 3: 'WBSCL_LB_MEM_PWR_FORCE_SD', -} -WBSCL_LB_MEM_PWR_FORCE_NO = 0 -WBSCL_LB_MEM_PWR_FORCE_LS = 1 -WBSCL_LB_MEM_PWR_FORCE_DS = 2 -WBSCL_LB_MEM_PWR_FORCE_SD = 3 -WBSCL_LB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_MEM_PWR_STATE_ENUM' -WBSCL_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'WBSCL_MEM_PWR_STATE_ON', - 1: 'WBSCL_MEM_PWR_STATE_LS', - 2: 'WBSCL_MEM_PWR_STATE_DS', - 3: 'WBSCL_MEM_PWR_STATE_SD', -} -WBSCL_MEM_PWR_STATE_ON = 0 -WBSCL_MEM_PWR_STATE_LS = 1 -WBSCL_MEM_PWR_STATE_DS = 2 -WBSCL_MEM_PWR_STATE_SD = 3 -WBSCL_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_LUT_MEM_PWR_STATE_ENUM' -WBSCL_LUT_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'WBSCL_LUT_MEM_PWR_STATE_ON', - 1: 'WBSCL_LUT_MEM_PWR_STATE_LS', - 2: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED2', - 3: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED3', -} -WBSCL_LUT_MEM_PWR_STATE_ON = 0 -WBSCL_LUT_MEM_PWR_STATE_LS = 1 -WBSCL_LUT_MEM_PWR_STATE_RESERVED2 = 2 -WBSCL_LUT_MEM_PWR_STATE_RESERVED3 = 3 -WBSCL_LUT_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_RAM_PW_SAVE_MODE_ENUM' -WB_RAM_PW_SAVE_MODE_ENUM__enumvalues = { - 0: 'WB_RAM_PW_SAVE_MODE_LS', - 1: 'WB_RAM_PW_SAVE_MODE_SD', -} -WB_RAM_PW_SAVE_MODE_LS = 0 -WB_RAM_PW_SAVE_MODE_SD = 1 -WB_RAM_PW_SAVE_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_OUT_BPC_ENUM' -CNV_OUT_BPC_ENUM__enumvalues = { - 0: 'CNV_OUT_BPC_8BPC', - 1: 'CNV_OUT_BPC_10BPC', -} -CNV_OUT_BPC_8BPC = 0 -CNV_OUT_BPC_10BPC = 1 -CNV_OUT_BPC_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_FRAME_CAPTURE_RATE_ENUM' -CNV_FRAME_CAPTURE_RATE_ENUM__enumvalues = { - 0: 'CNV_FRAME_CAPTURE_RATE_0', - 1: 'CNV_FRAME_CAPTURE_RATE_1', - 2: 'CNV_FRAME_CAPTURE_RATE_2', - 3: 'CNV_FRAME_CAPTURE_RATE_3', -} -CNV_FRAME_CAPTURE_RATE_0 = 0 -CNV_FRAME_CAPTURE_RATE_1 = 1 -CNV_FRAME_CAPTURE_RATE_2 = 2 -CNV_FRAME_CAPTURE_RATE_3 = 3 -CNV_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_WINDOW_CROP_EN_ENUM' -CNV_WINDOW_CROP_EN_ENUM__enumvalues = { - 0: 'CNV_WINDOW_CROP_DISABLE', - 1: 'CNV_WINDOW_CROP_ENABLE', -} -CNV_WINDOW_CROP_DISABLE = 0 -CNV_WINDOW_CROP_ENABLE = 1 -CNV_WINDOW_CROP_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_INTERLACED_MODE_ENUM' -CNV_INTERLACED_MODE_ENUM__enumvalues = { - 0: 'CNV_INTERLACED_MODE_PROGRESSIVE', - 1: 'CNV_INTERLACED_MODE_INTERLACED', -} -CNV_INTERLACED_MODE_PROGRESSIVE = 0 -CNV_INTERLACED_MODE_INTERLACED = 1 -CNV_INTERLACED_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_EYE_SELECT' -CNV_EYE_SELECT__enumvalues = { - 0: 'STEREO_DISABLED', - 1: 'LEFT_EYE', - 2: 'RIGHT_EYE', - 3: 'BOTH_EYE', -} -STEREO_DISABLED = 0 -LEFT_EYE = 1 -RIGHT_EYE = 2 -BOTH_EYE = 3 -CNV_EYE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_STEREO_TYPE_ENUM' -CNV_STEREO_TYPE_ENUM__enumvalues = { - 0: 'CNV_STEREO_TYPE_RESERVED0', - 1: 'CNV_STEREO_TYPE_RESERVED1', - 2: 'CNV_STEREO_TYPE_RESERVED2', - 3: 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL', -} -CNV_STEREO_TYPE_RESERVED0 = 0 -CNV_STEREO_TYPE_RESERVED1 = 1 -CNV_STEREO_TYPE_RESERVED2 = 2 -CNV_STEREO_TYPE_FRAME_SEQUENTIAL = 3 -CNV_STEREO_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_STEREO_POLARITY_ENUM' -CNV_STEREO_POLARITY_ENUM__enumvalues = { - 0: 'CNV_STEREO_POLARITY_LEFT', - 1: 'CNV_STEREO_POLARITY_RIGHT', -} -CNV_STEREO_POLARITY_LEFT = 0 -CNV_STEREO_POLARITY_RIGHT = 1 -CNV_STEREO_POLARITY_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_INTERLACED_FIELD_ORDER_ENUM' -CNV_INTERLACED_FIELD_ORDER_ENUM__enumvalues = { - 0: 'CNV_INTERLACED_FIELD_ORDER_TOP', - 1: 'CNV_INTERLACED_FIELD_ORDER_BOT', -} -CNV_INTERLACED_FIELD_ORDER_TOP = 0 -CNV_INTERLACED_FIELD_ORDER_BOT = 1 -CNV_INTERLACED_FIELD_ORDER_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_STEREO_SPLIT_ENUM' -CNV_STEREO_SPLIT_ENUM__enumvalues = { - 0: 'CNV_STEREO_SPLIT_DISABLE', - 1: 'CNV_STEREO_SPLIT_ENABLE', -} -CNV_STEREO_SPLIT_DISABLE = 0 -CNV_STEREO_SPLIT_ENABLE = 1 -CNV_STEREO_SPLIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_NEW_CONTENT_ENUM' -CNV_NEW_CONTENT_ENUM__enumvalues = { - 0: 'CNV_NEW_CONTENT_NEG', - 1: 'CNV_NEW_CONTENT_POS', -} -CNV_NEW_CONTENT_NEG = 0 -CNV_NEW_CONTENT_POS = 1 -CNV_NEW_CONTENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_FRAME_CAPTURE_EN_ENUM' -CNV_FRAME_CAPTURE_EN_ENUM__enumvalues = { - 0: 'CNV_FRAME_CAPTURE_DISABLE', - 1: 'CNV_FRAME_CAPTURE_ENABLE', -} -CNV_FRAME_CAPTURE_DISABLE = 0 -CNV_FRAME_CAPTURE_ENABLE = 1 -CNV_FRAME_CAPTURE_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_UPDATE_PENDING_ENUM' -CNV_UPDATE_PENDING_ENUM__enumvalues = { - 0: 'CNV_UPDATE_PENDING_NEG', - 1: 'CNV_UPDATE_PENDING_POS', -} -CNV_UPDATE_PENDING_NEG = 0 -CNV_UPDATE_PENDING_POS = 1 -CNV_UPDATE_PENDING_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_UPDATE_LOCK_ENUM' -CNV_UPDATE_LOCK_ENUM__enumvalues = { - 0: 'CNV_UPDATE_UNLOCK', - 1: 'CNV_UPDATE_LOCK', -} -CNV_UPDATE_UNLOCK = 0 -CNV_UPDATE_LOCK = 1 -CNV_UPDATE_LOCK_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_CSC_BYPASS_ENUM' -CNV_CSC_BYPASS_ENUM__enumvalues = { - 0: 'CNV_CSC_BYPASS_NEG', - 1: 'CNV_CSC_BYPASS_POS', -} -CNV_CSC_BYPASS_NEG = 0 -CNV_CSC_BYPASS_POS = 1 -CNV_CSC_BYPASS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_TEST_CRC_EN_ENUM' -CNV_TEST_CRC_EN_ENUM__enumvalues = { - 0: 'CNV_TEST_CRC_DISABLE', - 1: 'CNV_TEST_CRC_ENABLE', -} -CNV_TEST_CRC_DISABLE = 0 -CNV_TEST_CRC_ENABLE = 1 -CNV_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNV_TEST_CRC_CONT_EN_ENUM' -CNV_TEST_CRC_CONT_EN_ENUM__enumvalues = { - 0: 'CNV_TEST_CRC_CONT_DISABLE', - 1: 'CNV_TEST_CRC_CONT_ENABLE', -} -CNV_TEST_CRC_CONT_DISABLE = 0 -CNV_TEST_CRC_CONT_ENABLE = 1 -CNV_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WB_SOFT_RESET_ENUM' -WB_SOFT_RESET_ENUM__enumvalues = { - 0: 'WB_SOFT_RESET_NEG', - 1: 'WB_SOFT_RESET_POS', -} -WB_SOFT_RESET_NEG = 0 -WB_SOFT_RESET_POS = 1 -WB_SOFT_RESET_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GMC_WARM_UP_ENABLE_ENUM' -DWB_GMC_WARM_UP_ENABLE_ENUM__enumvalues = { - 0: 'DWB_GMC_WARM_UP_DISABLE', - 1: 'DWB_GMC_WARM_UP_ENABLE', -} -DWB_GMC_WARM_UP_DISABLE = 0 -DWB_GMC_WARM_UP_ENABLE = 1 -DWB_GMC_WARM_UP_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MODE_WARMUP_ENUM' -DWB_MODE_WARMUP_ENUM__enumvalues = { - 0: 'DWB_MODE_WARMUP_420', - 1: 'DWB_MODE_WARMUP_444', -} -DWB_MODE_WARMUP_420 = 0 -DWB_MODE_WARMUP_444 = 1 -DWB_MODE_WARMUP_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_DEPTH_WARMUP_ENUM' -DWB_DATA_DEPTH_WARMUP_ENUM__enumvalues = { - 0: 'DWB_DATA_DEPTH_WARMUP_8BPC', - 1: 'DWB_DATA_DEPTH_WARMUP_10BPC', -} -DWB_DATA_DEPTH_WARMUP_8BPC = 0 -DWB_DATA_DEPTH_WARMUP_10BPC = 1 -DWB_DATA_DEPTH_WARMUP_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM' -WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_TAP_PAIR_IDX0', - 1: 'WBSCL_COEF_RAM_TAP_PAIR_IDX1', - 2: 'WBSCL_COEF_RAM_TAP_PAIR_IDX2', - 3: 'WBSCL_COEF_RAM_TAP_PAIR_IDX3', - 4: 'WBSCL_COEF_RAM_TAP_PAIR_IDX4', - 5: 'WBSCL_COEF_RAM_TAP_PAIR_IDX5', -} -WBSCL_COEF_RAM_TAP_PAIR_IDX0 = 0 -WBSCL_COEF_RAM_TAP_PAIR_IDX1 = 1 -WBSCL_COEF_RAM_TAP_PAIR_IDX2 = 2 -WBSCL_COEF_RAM_TAP_PAIR_IDX3 = 3 -WBSCL_COEF_RAM_TAP_PAIR_IDX4 = 4 -WBSCL_COEF_RAM_TAP_PAIR_IDX5 = 5 -WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_PHASE_ENUM' -WBSCL_COEF_RAM_PHASE_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_PHASE0', - 1: 'WBSCL_COEF_RAM_PHASE1', - 2: 'WBSCL_COEF_RAM_PHASE2', - 3: 'WBSCL_COEF_RAM_PHASE3', - 4: 'WBSCL_COEF_RAM_PHASE4', - 5: 'WBSCL_COEF_RAM_PHASE5', - 6: 'WBSCL_COEF_RAM_PHASE6', - 7: 'WBSCL_COEF_RAM_PHASE7', - 8: 'WBSCL_COEF_RAM_PHASE8', -} -WBSCL_COEF_RAM_PHASE0 = 0 -WBSCL_COEF_RAM_PHASE1 = 1 -WBSCL_COEF_RAM_PHASE2 = 2 -WBSCL_COEF_RAM_PHASE3 = 3 -WBSCL_COEF_RAM_PHASE4 = 4 -WBSCL_COEF_RAM_PHASE5 = 5 -WBSCL_COEF_RAM_PHASE6 = 6 -WBSCL_COEF_RAM_PHASE7 = 7 -WBSCL_COEF_RAM_PHASE8 = 8 -WBSCL_COEF_RAM_PHASE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_FILTER_TYPE_ENUM' -WBSCL_COEF_RAM_FILTER_TYPE_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_FILTER_TYPE_VL', - 1: 'WBSCL_COEF_RAM_FILTER_TYPE_VC', - 2: 'WBSCL_COEF_RAM_FILTER_TYPE_HL', - 3: 'WBSCL_COEF_RAM_FILTER_TYPE_HC', -} -WBSCL_COEF_RAM_FILTER_TYPE_VL = 0 -WBSCL_COEF_RAM_FILTER_TYPE_VC = 1 -WBSCL_COEF_RAM_FILTER_TYPE_HL = 2 -WBSCL_COEF_RAM_FILTER_TYPE_HC = 3 -WBSCL_COEF_RAM_FILTER_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_FILTER_TYPE_SEL' -WBSCL_COEF_FILTER_TYPE_SEL__enumvalues = { - 0: 'WBSCL_COEF_LUMA_VERT_FILTER', - 1: 'WBSCL_COEF_CHROMA_VERT_FILTER', - 2: 'WBSCL_COEF_LUMA_HORZ_FILTER', - 3: 'WBSCL_COEF_CHROMA_HORZ_FILTER', -} -WBSCL_COEF_LUMA_VERT_FILTER = 0 -WBSCL_COEF_CHROMA_VERT_FILTER = 1 -WBSCL_COEF_LUMA_HORZ_FILTER = 2 -WBSCL_COEF_CHROMA_HORZ_FILTER = 3 -WBSCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_MODE_SEL' -WBSCL_MODE_SEL__enumvalues = { - 0: 'WBSCL_MODE_SCALING_444_BYPASS', - 1: 'WBSCL_MODE_SCALING_444_RGB_ENABLE', - 2: 'WBSCL_MODE_SCALING_444_YCBCR_ENABLE', - 3: 'WBSCL_MODE_SCALING_YCBCR_ENABLE', -} -WBSCL_MODE_SCALING_444_BYPASS = 0 -WBSCL_MODE_SCALING_444_RGB_ENABLE = 1 -WBSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 -WBSCL_MODE_SCALING_YCBCR_ENABLE = 3 -WBSCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_PIXEL_DEPTH' -WBSCL_PIXEL_DEPTH__enumvalues = { - 0: 'PIXEL_DEPTH_8BPC', - 1: 'PIXEL_DEPTH_10BPC', -} -PIXEL_DEPTH_8BPC = 0 -PIXEL_DEPTH_10BPC = 1 -WBSCL_PIXEL_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_SEL_ENUM' -WBSCL_COEF_RAM_SEL_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_SEL_0', - 1: 'WBSCL_COEF_RAM_SEL_1', -} -WBSCL_COEF_RAM_SEL_0 = 0 -WBSCL_COEF_RAM_SEL_1 = 1 -WBSCL_COEF_RAM_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_RD_SEL_ENUM' -WBSCL_COEF_RAM_RD_SEL_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_RD_SEL_0', - 1: 'WBSCL_COEF_RAM_RD_SEL_1', -} -WBSCL_COEF_RAM_RD_SEL_0 = 0 -WBSCL_COEF_RAM_RD_SEL_1 = 1 -WBSCL_COEF_RAM_RD_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM' -WBSCL_COEF_RAM_TAP_COEF_EN_ENUM__enumvalues = { - 0: 'WBSCL_COEF_RAM_TAP_COEF_DISABLE', - 1: 'WBSCL_COEF_RAM_TAP_COEF_ENABLE', -} -WBSCL_COEF_RAM_TAP_COEF_DISABLE = 0 -WBSCL_COEF_RAM_TAP_COEF_ENABLE = 1 -WBSCL_COEF_RAM_TAP_COEF_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_NUM_OF_TAPS_ENUM' -WBSCL_NUM_OF_TAPS_ENUM__enumvalues = { - 0: 'WBSCL_NUM_OF_TAPS0', - 1: 'WBSCL_NUM_OF_TAPS1', - 2: 'WBSCL_NUM_OF_TAPS2', - 3: 'WBSCL_NUM_OF_TAPS3', - 4: 'WBSCL_NUM_OF_TAPS4', - 5: 'WBSCL_NUM_OF_TAPS5', - 6: 'WBSCL_NUM_OF_TAPS6', - 7: 'WBSCL_NUM_OF_TAPS7', - 8: 'WBSCL_NUM_OF_TAPS8', - 9: 'WBSCL_NUM_OF_TAPS9', - 10: 'WBSCL_NUM_OF_TAPS10', - 11: 'WBSCL_NUM_OF_TAPS11', -} -WBSCL_NUM_OF_TAPS0 = 0 -WBSCL_NUM_OF_TAPS1 = 1 -WBSCL_NUM_OF_TAPS2 = 2 -WBSCL_NUM_OF_TAPS3 = 3 -WBSCL_NUM_OF_TAPS4 = 4 -WBSCL_NUM_OF_TAPS5 = 5 -WBSCL_NUM_OF_TAPS6 = 6 -WBSCL_NUM_OF_TAPS7 = 7 -WBSCL_NUM_OF_TAPS8 = 8 -WBSCL_NUM_OF_TAPS9 = 9 -WBSCL_NUM_OF_TAPS10 = 10 -WBSCL_NUM_OF_TAPS11 = 11 -WBSCL_NUM_OF_TAPS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_STATUS_ACK_ENUM' -WBSCL_STATUS_ACK_ENUM__enumvalues = { - 0: 'WBSCL_STATUS_ACK_NCLR', - 1: 'WBSCL_STATUS_ACK_CLR', -} -WBSCL_STATUS_ACK_NCLR = 0 -WBSCL_STATUS_ACK_CLR = 1 -WBSCL_STATUS_ACK_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_STATUS_MASK_ENUM' -WBSCL_STATUS_MASK_ENUM__enumvalues = { - 0: 'WBSCL_STATUS_MASK_DISABLE', - 1: 'WBSCL_STATUS_MASK_ENABLE', -} -WBSCL_STATUS_MASK_DISABLE = 0 -WBSCL_STATUS_MASK_ENABLE = 1 -WBSCL_STATUS_MASK_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM' -WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { - 0: 'WBSCL_DATA_OVERFLOW_INT_TYPE_REG', - 1: 'WBSCL_DATA_OVERFLOW_INT_TYPE_HW', -} -WBSCL_DATA_OVERFLOW_INT_TYPE_REG = 0 -WBSCL_DATA_OVERFLOW_INT_TYPE_HW = 1 -WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM' -WBSCL_HOST_CONFLICT_INT_TYPE_ENUM__enumvalues = { - 0: 'WBSCL_HOST_CONFLICT_INT_TYPE_REG', - 1: 'WBSCL_HOST_CONFLICT_INT_TYPE_HW', -} -WBSCL_HOST_CONFLICT_INT_TYPE_REG = 0 -WBSCL_HOST_CONFLICT_INT_TYPE_HW = 1 -WBSCL_HOST_CONFLICT_INT_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_TEST_CRC_EN_ENUM' -WBSCL_TEST_CRC_EN_ENUM__enumvalues = { - 0: 'WBSCL_TEST_CRC_DISABLE', - 1: 'WBSCL_TEST_CRC_ENABLE', -} -WBSCL_TEST_CRC_DISABLE = 0 -WBSCL_TEST_CRC_ENABLE = 1 -WBSCL_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_TEST_CRC_CONT_EN_ENUM' -WBSCL_TEST_CRC_CONT_EN_ENUM__enumvalues = { - 0: 'WBSCL_TEST_CRC_CONT_DISABLE', - 1: 'WBSCL_TEST_CRC_CONT_ENABLE', -} -WBSCL_TEST_CRC_CONT_DISABLE = 0 -WBSCL_TEST_CRC_CONT_ENABLE = 1 -WBSCL_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_TEST_CRC_MASK_ENUM' -WBSCL_TEST_CRC_MASK_ENUM__enumvalues = { - 0: 'WBSCL_TEST_CRC_MASKED', - 1: 'WBSCL_TEST_CRC_UNMASKED', -} -WBSCL_TEST_CRC_MASKED = 0 -WBSCL_TEST_CRC_UNMASKED = 1 -WBSCL_TEST_CRC_MASK_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_BACKPRESSURE_CNT_EN_ENUM' -WBSCL_BACKPRESSURE_CNT_EN_ENUM__enumvalues = { - 0: 'WBSCL_BACKPRESSURE_CNT_DISABLE', - 1: 'WBSCL_BACKPRESSURE_CNT_ENABLE', -} -WBSCL_BACKPRESSURE_CNT_DISABLE = 0 -WBSCL_BACKPRESSURE_CNT_ENABLE = 1 -WBSCL_BACKPRESSURE_CNT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM' -WBSCL_OUTSIDE_PIX_STRATEGY_ENUM__enumvalues = { - 0: 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK', - 1: 'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE', -} -WBSCL_OUTSIDE_PIX_STRATEGY_BLACK = 0 -WBSCL_OUTSIDE_PIX_STRATEGY_EDGE = 1 -WBSCL_OUTSIDE_PIX_STRATEGY_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' -DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { - 0: 'DPCSRX_BPHY_PCS_RX0_CLK', - 1: 'DPCSRX_BPHY_PCS_RX1_CLK', - 2: 'DPCSRX_BPHY_PCS_RX2_CLK', - 3: 'DPCSRX_BPHY_PCS_RX3_CLK', -} -DPCSRX_BPHY_PCS_RX0_CLK = 0 -DPCSRX_BPHY_PCS_RX1_CLK = 1 -DPCSRX_BPHY_PCS_RX2_CLK = 2 -DPCSRX_BPHY_PCS_RX3_CLK = 3 -DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSTX_DVI_LINK_MODE' -DPCSTX_DVI_LINK_MODE__enumvalues = { - 0: 'DPCSTX_DVI_LINK_MODE_NORMAL', - 1: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER', - 2: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER', -} -DPCSTX_DVI_LINK_MODE_NORMAL = 0 -DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 1 -DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 2 -DPCSTX_DVI_LINK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = { - 0: 'RDPCS_CBUS_SOFT_RESET_DISABLE', - 1: 'RDPCS_CBUS_SOFT_RESET_ENABLE', -} -RDPCS_CBUS_SOFT_RESET_DISABLE = 0 -RDPCS_CBUS_SOFT_RESET_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { - 0: 'RDPCS_SRAM_SRAM_RESET_DISABLE', -} -RDPCS_SRAM_SRAM_RESET_DISABLE = 0 -RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN' -RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = { - 0: 'RDPCS_TX_FIFO_LANE_DISABLE', - 1: 'RDPCS_TX_FIFO_LANE_ENABLE', -} -RDPCS_TX_FIFO_LANE_DISABLE = 0 -RDPCS_TX_FIFO_LANE_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN' -RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = { - 0: 'RDPCS_TX_FIFO_DISABLE', - 1: 'RDPCS_TX_FIFO_ENABLE', -} -RDPCS_TX_FIFO_DISABLE = 0 -RDPCS_TX_FIFO_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = { - 0: 'RDPCS_TX_SOFT_RESET_DISABLE', - 1: 'RDPCS_TX_SOFT_RESET_ENABLE', -} -RDPCS_TX_SOFT_RESET_DISABLE = 0 -RDPCS_TX_SOFT_RESET_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = { - 0: 'RDPCS_EXT_REFCLK_DISABLE', - 1: 'RDPCS_EXT_REFCLK_ENABLE', -} -RDPCS_EXT_REFCLK_DISABLE = 0 -RDPCS_EXT_REFCLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN__enumvalues = { - 0: 'RDPCS_EXT_REFCLK_EN_DISABLE', - 1: 'RDPCS_EXT_REFCLK_EN_ENABLE', -} -RDPCS_EXT_REFCLK_EN_DISABLE = 0 -RDPCS_EXT_REFCLK_EN_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS' -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS__enumvalues = { - 0: 'RDPCS_SYMCLK_DIV2_GATE_ENABLE', - 1: 'RDPCS_SYMCLK_DIV2_GATE_DISABLE', -} -RDPCS_SYMCLK_DIV2_GATE_ENABLE = 0 -RDPCS_SYMCLK_DIV2_GATE_DISABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN__enumvalues = { - 0: 'RDPCS_SYMCLK_DIV2_DISABLE', - 1: 'RDPCS_SYMCLK_DIV2_ENABLE', -} -RDPCS_SYMCLK_DIV2_DISABLE = 0 -RDPCS_SYMCLK_DIV2_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON' -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON__enumvalues = { - 0: 'RDPCS_SYMCLK_DIV2_CLOCK_OFF', - 1: 'RDPCS_SYMCLK_DIV2_CLOCK_ON', -} -RDPCS_SYMCLK_DIV2_CLOCK_OFF = 0 -RDPCS_SYMCLK_DIV2_CLOCK_ON = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_SRAMCLK_GATE_ENABLE', - 1: 'RDPCS_SRAMCLK_GATE_DISABLE', -} -RDPCS_SRAMCLK_GATE_ENABLE = 0 -RDPCS_SRAMCLK_GATE_DISABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { - 0: 'RDPCS_SRAMCLK_DISABLE', - 1: 'RDPCS_SRAMCLK_ENABLE', -} -RDPCS_SRAMCLK_DISABLE = 0 -RDPCS_SRAMCLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS__enumvalues = { - 0: 'RDPCS_SRAMCLK_NOT_BYPASS', - 1: 'RDPCS_SRAMCLK_BYPASS', -} -RDPCS_SRAMCLK_NOT_BYPASS = 0 -RDPCS_SRAMCLK_BYPASS = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', - 1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', -} -RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0 -RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { - 0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', - 1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', -} -RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0 -RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { - 0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', - 1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', -} -RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0 -RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', -} -RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0 -RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', -} -RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 -RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', -} -RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 -RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', -} -RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0 -RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { - 0: 'RDPCS_MEM_PWR_NO_FORCE', - 1: 'RDPCS_MEM_PWR_LIGHT_SLEEP', - 2: 'RDPCS_MEM_PWR_DEEP_SLEEP', - 3: 'RDPCS_MEM_PWR_SHUT_DOWN', -} -RDPCS_MEM_PWR_NO_FORCE = 0 -RDPCS_MEM_PWR_LIGHT_SLEEP = 1 -RDPCS_MEM_PWR_DEEP_SLEEP = 2 -RDPCS_MEM_PWR_SHUT_DOWN = 3 -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { - 0: 'RDPCS_MEM_PWR_PWR_STATE_ON', - 1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', -} -RDPCS_MEM_PWR_PWR_STATE_ON = 0 -RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 -RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 -RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF' -RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF__enumvalues = { - 0: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY', - 1: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD', - 2: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3', - 3: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD', -} -RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY = 0 -RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD = 1 -RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3 = 2 -RDPCS_MEM_POWER_CTRL_POFF_FOR_SD = 3 -RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { - 0: 'RDPCS_PHY_REF_RANGE_0', - 1: 'RDPCS_PHY_REF_RANGE_1', - 2: 'RDPCS_PHY_REF_RANGE_2', - 3: 'RDPCS_PHY_REF_RANGE_3', - 4: 'RDPCS_PHY_REF_RANGE_4', - 5: 'RDPCS_PHY_REF_RANGE_5', - 6: 'RDPCS_PHY_REF_RANGE_6', - 7: 'RDPCS_PHY_REF_RANGE_7', -} -RDPCS_PHY_REF_RANGE_0 = 0 -RDPCS_PHY_REF_RANGE_1 = 1 -RDPCS_PHY_REF_RANGE_2 = 2 -RDPCS_PHY_REF_RANGE_3 = 3 -RDPCS_PHY_REF_RANGE_4 = 4 -RDPCS_PHY_REF_RANGE_5 = 5 -RDPCS_PHY_REF_RANGE_6 = 6 -RDPCS_PHY_REF_RANGE_7 = 7 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { - 0: 'RDPCS_PHY_CR_PARA_SEL_JTAG', - 1: 'RDPCS_PHY_CR_PARA_SEL_CR', -} -RDPCS_PHY_CR_PARA_SEL_JTAG = 0 -RDPCS_PHY_CR_PARA_SEL_CR = 1 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { - 0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', - 1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', -} -RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0 -RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { - 0: 'RDPCS_SRAM_INIT_NOT_DONE', - 1: 'RDPCS_SRAM_INIT_DONE', -} -RDPCS_SRAM_INIT_NOT_DONE = 0 -RDPCS_SRAM_INIT_DONE = 1 -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { - 0: 'RDPCS_SRAM_EXT_LD_NOT_DONE', - 1: 'RDPCS_SRAM_EXT_LD_DONE', -} -RDPCS_SRAM_EXT_LD_NOT_DONE = 0 -RDPCS_SRAM_EXT_LD_DONE = 1 -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' -RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54', - 1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52', - 2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50', - 3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48', - 4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46', - 5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44', - 6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42', - 7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40', -} -RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0 -RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1 -RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2 -RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3 -RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4 -RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5 -RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6 -RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7 -RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' -RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { - 0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', - 1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', - 2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', - 3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', -} -RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0 -RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1 -RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2 -RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3 -RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_RATE', - 1: 'RDPCS_PHY_DP_TX_RATE_DIV2', - 2: 'RDPCS_PHY_DP_TX_RATE_DIV4', -} -RDPCS_PHY_DP_TX_RATE = 0 -RDPCS_PHY_DP_TX_RATE_DIV2 = 1 -RDPCS_PHY_DP_TX_RATE_DIV4 = 2 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_WIDTH_8', - 1: 'RDPCS_PHY_DP_TX_WIDTH_10', - 2: 'RDPCS_PHY_DP_TX_WIDTH_16', - 3: 'RDPCS_PHY_DP_TX_WIDTH_20', -} -RDPCS_PHY_DP_TX_WIDTH_8 = 0 -RDPCS_PHY_DP_TX_WIDTH_10 = 1 -RDPCS_PHY_DP_TX_WIDTH_16 = 2 -RDPCS_PHY_DP_TX_WIDTH_20 = 3 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', -} -RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 -RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' -RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { - 0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', - 1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', - 2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', - 3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', - 4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', -} -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 -RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' -RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { - 0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', -} -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 -RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' -RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { - 0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', - 2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', - 3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', - 4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', - 5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', - 6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', - 7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', -} -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 -RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TEST_CLK_SEL' -RDPCS_TEST_CLK_SEL__enumvalues = { - 0: 'RDPCS_TEST_CLK_SEL_NONE', - 1: 'RDPCS_TEST_CLK_SEL_CFGCLK', - 2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 6: 'RDPCS_TEST_CLK_SEL_SRAMCLK', - 7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', - 8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', - 16: 'RDPCS_TEST_CLK_SEL_dtb_out0', - 17: 'RDPCS_TEST_CLK_SEL_dtb_out1', -} -RDPCS_TEST_CLK_SEL_NONE = 0 -RDPCS_TEST_CLK_SEL_CFGCLK = 1 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 -RDPCS_TEST_CLK_SEL_SRAMCLK = 6 -RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7 -RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 -RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 -RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 -RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 -RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 -RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 -RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 -RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15 -RDPCS_TEST_CLK_SEL_dtb_out0 = 16 -RDPCS_TEST_CLK_SEL_dtb_out1 = 17 -RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CBMode' -CBMode__enumvalues = { - 0: 'CB_DISABLE', - 1: 'CB_NORMAL', - 2: 'CB_ELIMINATE_FAST_CLEAR', - 3: 'CB_RESOLVE', - 4: 'CB_DECOMPRESS', - 5: 'CB_FMASK_DECOMPRESS', - 6: 'CB_DCC_DECOMPRESS', - 7: 'CB_RESERVED', -} -CB_DISABLE = 0 -CB_NORMAL = 1 -CB_ELIMINATE_FAST_CLEAR = 2 -CB_RESOLVE = 3 -CB_DECOMPRESS = 4 -CB_FMASK_DECOMPRESS = 5 -CB_DCC_DECOMPRESS = 6 -CB_RESERVED = 7 -CBMode = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOp' -BlendOp__enumvalues = { - 0: 'BLEND_ZERO', - 1: 'BLEND_ONE', - 2: 'BLEND_SRC_COLOR', - 3: 'BLEND_ONE_MINUS_SRC_COLOR', - 4: 'BLEND_SRC_ALPHA', - 5: 'BLEND_ONE_MINUS_SRC_ALPHA', - 6: 'BLEND_DST_ALPHA', - 7: 'BLEND_ONE_MINUS_DST_ALPHA', - 8: 'BLEND_DST_COLOR', - 9: 'BLEND_ONE_MINUS_DST_COLOR', - 10: 'BLEND_SRC_ALPHA_SATURATE', - 11: 'BLEND_BOTH_SRC_ALPHA', - 12: 'BLEND_BOTH_INV_SRC_ALPHA', - 13: 'BLEND_CONSTANT_COLOR', - 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', - 15: 'BLEND_SRC1_COLOR', - 16: 'BLEND_INV_SRC1_COLOR', - 17: 'BLEND_SRC1_ALPHA', - 18: 'BLEND_INV_SRC1_ALPHA', - 19: 'BLEND_CONSTANT_ALPHA', - 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', -} -BLEND_ZERO = 0 -BLEND_ONE = 1 -BLEND_SRC_COLOR = 2 -BLEND_ONE_MINUS_SRC_COLOR = 3 -BLEND_SRC_ALPHA = 4 -BLEND_ONE_MINUS_SRC_ALPHA = 5 -BLEND_DST_ALPHA = 6 -BLEND_ONE_MINUS_DST_ALPHA = 7 -BLEND_DST_COLOR = 8 -BLEND_ONE_MINUS_DST_COLOR = 9 -BLEND_SRC_ALPHA_SATURATE = 10 -BLEND_BOTH_SRC_ALPHA = 11 -BLEND_BOTH_INV_SRC_ALPHA = 12 -BLEND_CONSTANT_COLOR = 13 -BLEND_ONE_MINUS_CONSTANT_COLOR = 14 -BLEND_SRC1_COLOR = 15 -BLEND_INV_SRC1_COLOR = 16 -BLEND_SRC1_ALPHA = 17 -BLEND_INV_SRC1_ALPHA = 18 -BLEND_CONSTANT_ALPHA = 19 -BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 -BlendOp = ctypes.c_uint32 # enum -GL__ZERO = BLEND_ZERO # macro -GL__ONE = BLEND_ONE # macro -GL__SRC_COLOR = BLEND_SRC_COLOR # macro -GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro -GL__DST_COLOR = BLEND_DST_COLOR # macro -GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro -GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro -GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro -GL__DST_ALPHA = BLEND_DST_ALPHA # macro -GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro -GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro -GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro -GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro -GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro -GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro - -# values for enumeration 'CombFunc' -CombFunc__enumvalues = { - 0: 'COMB_DST_PLUS_SRC', - 1: 'COMB_SRC_MINUS_DST', - 2: 'COMB_MIN_DST_SRC', - 3: 'COMB_MAX_DST_SRC', - 4: 'COMB_DST_MINUS_SRC', -} -COMB_DST_PLUS_SRC = 0 -COMB_SRC_MINUS_DST = 1 -COMB_MIN_DST_SRC = 2 -COMB_MAX_DST_SRC = 3 -COMB_DST_MINUS_SRC = 4 -CombFunc = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOpt' -BlendOpt__enumvalues = { - 0: 'FORCE_OPT_AUTO', - 1: 'FORCE_OPT_DISABLE', - 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', - 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', - 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', -} -FORCE_OPT_AUTO = 0 -FORCE_OPT_DISABLE = 1 -FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 -FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 -BlendOpt = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskCode' -CmaskCode__enumvalues = { - 0: 'CMASK_CLR00_F0', - 1: 'CMASK_CLR00_F1', - 2: 'CMASK_CLR00_F2', - 3: 'CMASK_CLR00_FX', - 4: 'CMASK_CLR01_F0', - 5: 'CMASK_CLR01_F1', - 6: 'CMASK_CLR01_F2', - 7: 'CMASK_CLR01_FX', - 8: 'CMASK_CLR10_F0', - 9: 'CMASK_CLR10_F1', - 10: 'CMASK_CLR10_F2', - 11: 'CMASK_CLR10_FX', - 12: 'CMASK_CLR11_F0', - 13: 'CMASK_CLR11_F1', - 14: 'CMASK_CLR11_F2', - 15: 'CMASK_CLR11_FX', -} -CMASK_CLR00_F0 = 0 -CMASK_CLR00_F1 = 1 -CMASK_CLR00_F2 = 2 -CMASK_CLR00_FX = 3 -CMASK_CLR01_F0 = 4 -CMASK_CLR01_F1 = 5 -CMASK_CLR01_F2 = 6 -CMASK_CLR01_FX = 7 -CMASK_CLR10_F0 = 8 -CMASK_CLR10_F1 = 9 -CMASK_CLR10_F2 = 10 -CMASK_CLR10_FX = 11 -CMASK_CLR11_F0 = 12 -CMASK_CLR11_F1 = 13 -CMASK_CLR11_F2 = 14 -CMASK_CLR11_FX = 15 -CmaskCode = ctypes.c_uint32 # enum - -# values for enumeration 'MemArbMode' -MemArbMode__enumvalues = { - 0: 'MEM_ARB_MODE_FIXED', - 1: 'MEM_ARB_MODE_AGE', - 2: 'MEM_ARB_MODE_WEIGHT', - 3: 'MEM_ARB_MODE_BOTH', -} -MEM_ARB_MODE_FIXED = 0 -MEM_ARB_MODE_AGE = 1 -MEM_ARB_MODE_WEIGHT = 2 -MEM_ARB_MODE_BOTH = 3 -MemArbMode = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfOpFilterSel' -CBPerfOpFilterSel__enumvalues = { - 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', -} -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 -CB_PERF_OP_FILTER_SEL_RESOLVE = 2 -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 -CBPerfOpFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfClearFilterSel' -CBPerfClearFilterSel__enumvalues = { - 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', -} -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 -CBPerfClearFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfSel' -CBPerfSel__enumvalues = { - 0: 'CB_PERF_SEL_NONE', - 1: 'CB_PERF_SEL_BUSY', - 2: 'CB_PERF_SEL_CORE_SCLK_VLD', - 3: 'CB_PERF_SEL_REG_SCLK0_VLD', - 4: 'CB_PERF_SEL_REG_SCLK1_VLD', - 5: 'CB_PERF_SEL_DRAWN_QUAD', - 6: 'CB_PERF_SEL_DRAWN_PIXEL', - 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', - 8: 'CB_PERF_SEL_DRAWN_TILE', - 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', - 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', - 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', - 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', - 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', - 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', - 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', - 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', - 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', - 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', - 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', - 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', - 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', - 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', - 23: 'CB_PERF_SEL_LQUAD_NO_TILE', - 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', - 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', - 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', - 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', - 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', - 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', - 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', - 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', - 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', - 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', - 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', - 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', - 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', - 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', - 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', - 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', - 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', - 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', - 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', - 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', - 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', - 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', - 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', - 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', - 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', - 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', - 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', - 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', - 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', - 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', - 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', - 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', - 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', - 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', - 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', - 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', - 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', - 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', - 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', - 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', - 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', - 65: 'CB_PERF_SEL_CM_CACHE_HIT', - 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', - 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', - 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', - 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', - 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', - 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', - 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', - 75: 'CB_PERF_SEL_CM_CACHE_STALL', - 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', - 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', - 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', - 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', - 80: 'CB_PERF_SEL_FC_CACHE_HIT', - 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', - 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', - 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', - 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', - 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', - 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', - 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', - 90: 'CB_PERF_SEL_FC_CACHE_STALL', - 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', - 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', - 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', - 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', - 95: 'CB_PERF_SEL_CC_CACHE_HIT', - 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', - 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 105: 'CB_PERF_SEL_CC_CACHE_STALL', - 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', - 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 111: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', - 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', - 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', - 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', - 115: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', - 116: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', - 117: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 118: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', - 119: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', - 120: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 121: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', - 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', - 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', - 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', - 125: 'CB_PERF_SEL_CM_MC_READ_REQUEST', - 126: 'CB_PERF_SEL_FC_MC_READ_REQUEST', - 127: 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 128: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', - 129: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', - 130: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 131: 'CB_PERF_SEL_CM_TQ_FULL', - 132: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', - 133: 'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL', - 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', - 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', - 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 137: 'CB_PERF_SEL_FC_TILE_STUTTER_STALL', - 138: 'CB_PERF_SEL_FC_QUAD_STUTTER_STALL', - 139: 'CB_PERF_SEL_FC_KEYID_STUTTER_STALL', - 140: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', - 141: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', - 142: 'CB_PERF_SEL_CC_SF_FULL', - 143: 'CB_PERF_SEL_CC_RB_FULL', - 144: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', - 145: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', - 146: 'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL', - 147: 'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL', - 148: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', - 149: 'CB_PERF_SEL_EVENT', - 150: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 151: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 152: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 153: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 154: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 155: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 156: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 157: 'CB_PERF_SEL_CC_SURFACE_SYNC', - 158: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', - 159: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', - 160: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', - 161: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', - 162: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', - 163: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', - 164: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', - 165: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', - 166: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', - 167: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 168: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', - 169: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', - 170: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 171: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 172: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 173: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 174: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 175: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 176: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 177: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', - 178: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', - 179: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', - 180: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', - 181: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', - 182: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', - 183: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', - 184: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', - 185: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', - 186: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', - 187: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', - 188: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', - 189: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', - 190: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', - 191: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', - 192: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', - 193: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', - 194: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', - 195: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', - 196: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', - 197: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', - 198: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', - 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', - 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', - 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', - 202: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', - 203: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', - 204: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', - 205: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', - 206: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', - 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', - 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', - 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', - 210: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', - 211: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', - 212: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', - 213: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', - 214: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', - 215: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', - 216: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', - 217: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', - 218: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 219: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 220: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', - 221: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 222: 'CB_PERF_SEL_DRAWN_BUSY', - 223: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', - 224: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', - 225: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', - 226: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', - 227: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', - 228: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', - 229: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', - 230: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', - 231: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', - 232: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 233: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', - 234: 'CB_PERF_SEL_FC_DOC_IS_STALLED', - 235: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', - 236: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', - 237: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', - 238: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', - 239: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', - 240: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', - 241: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', - 242: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', - 243: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', - 244: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', - 245: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', - 246: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', - 247: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', - 248: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', - 249: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', - 250: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', - 251: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 252: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 253: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 254: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', - 255: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', - 256: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', - 257: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', - 258: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', - 259: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', - 260: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', - 261: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 262: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', - 263: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', - 264: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', - 265: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', - 266: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', - 267: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', - 268: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', - 269: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', - 270: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', - 271: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', - 272: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', - 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', - 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', - 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', - 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', - 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', - 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', - 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', - 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', - 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', - 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', - 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', - 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', - 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', - 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', - 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', - 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', - 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', - 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', - 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', - 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', - 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', - 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', - 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', - 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', - 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', - 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', - 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', - 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', - 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', - 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', - 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', - 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', - 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', - 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', - 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', - 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', - 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', - 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', - 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', - 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', - 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', - 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', - 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', - 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', - 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', - 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', - 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', - 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', - 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', - 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', - 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', - 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', - 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', - 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', - 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', - 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', - 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', - 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', - 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', - 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', - 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', - 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', - 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', - 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', - 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', - 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', - 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', - 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', - 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', - 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', - 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', - 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', - 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', - 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', - 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', - 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', - 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', - 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', - 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', - 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', - 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', - 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', - 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', - 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', - 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', - 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', - 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', - 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', - 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', - 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', - 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', - 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', - 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', - 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', - 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', - 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', - 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', - 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', - 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', - 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', - 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', - 380: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', - 381: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', - 382: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', - 383: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', - 384: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', - 385: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', - 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', - 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', - 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', - 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', - 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', - 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', - 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', - 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', - 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', - 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', - 396: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', - 397: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', - 398: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', - 399: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', - 400: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', - 401: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', - 402: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 403: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 404: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 405: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', - 406: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', - 407: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', - 408: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', - 409: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', - 410: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', - 411: 'CB_PERF_SEL_NACK_CM_READ', - 412: 'CB_PERF_SEL_NACK_CM_WRITE', - 413: 'CB_PERF_SEL_NACK_FC_READ', - 414: 'CB_PERF_SEL_NACK_FC_WRITE', - 415: 'CB_PERF_SEL_NACK_DC_READ', - 416: 'CB_PERF_SEL_NACK_DC_WRITE', - 417: 'CB_PERF_SEL_NACK_CC_READ', - 418: 'CB_PERF_SEL_NACK_CC_WRITE', - 419: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN', - 420: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN', - 421: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN', - 422: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN', - 423: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 424: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 425: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 426: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 427: 'CB_PERF_SEL_CM_MC_WRITE_ACK64B', - 428: 'CB_PERF_SEL_FC_MC_WRITE_ACK64B', - 429: 'CB_PERF_SEL_DC_MC_WRITE_ACK64B', - 430: 'CB_PERF_SEL_CC_MC_WRITE_ACK64B', - 431: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', - 432: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS', - 433: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA', - 434: 'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT', - 435: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX', - 436: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX', - 437: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX', - 438: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX', - 439: 'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED', - 440: 'CB_PERF_SEL_DB_CB_CONTEXT_DONE', - 441: 'CB_PERF_SEL_DB_CB_EOP_DONE', - 442: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL', - 443: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD', -} -CB_PERF_SEL_NONE = 0 -CB_PERF_SEL_BUSY = 1 -CB_PERF_SEL_CORE_SCLK_VLD = 2 -CB_PERF_SEL_REG_SCLK0_VLD = 3 -CB_PERF_SEL_REG_SCLK1_VLD = 4 -CB_PERF_SEL_DRAWN_QUAD = 5 -CB_PERF_SEL_DRAWN_PIXEL = 6 -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 -CB_PERF_SEL_DRAWN_TILE = 8 -CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 -CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 -CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 -CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 -CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 -CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 -CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 -CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 -CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 -CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 -CB_PERF_SEL_LQUAD_NO_TILE = 23 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 -CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 -CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 -CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 -CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 -CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 -CB_PERF_SEL_FOP_IN_VALID_READY = 40 -CB_PERF_SEL_FOP_IN_VALID_READYB = 41 -CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 -CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 -CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 -CB_PERF_SEL_CM_CACHE_HIT = 65 -CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 -CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 -CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 -CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 -CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 -CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 -CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 -CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 -CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 -CB_PERF_SEL_CM_CACHE_STALL = 75 -CB_PERF_SEL_CM_CACHE_FLUSH = 76 -CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 -CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 -CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 -CB_PERF_SEL_FC_CACHE_HIT = 80 -CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 -CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 -CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 -CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 -CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 -CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 -CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 -CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 -CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 -CB_PERF_SEL_FC_CACHE_STALL = 90 -CB_PERF_SEL_FC_CACHE_FLUSH = 91 -CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 -CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 -CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 -CB_PERF_SEL_CC_CACHE_HIT = 95 -CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 -CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 -CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 -CB_PERF_SEL_CC_CACHE_STALL = 105 -CB_PERF_SEL_CC_CACHE_FLUSH = 106 -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 111 -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 112 -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 113 -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 114 -CB_PERF_SEL_CM_MC_WRITE_REQUEST = 115 -CB_PERF_SEL_FC_MC_WRITE_REQUEST = 116 -CB_PERF_SEL_CC_MC_WRITE_REQUEST = 117 -CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 118 -CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 119 -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 121 -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 122 -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 123 -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 124 -CB_PERF_SEL_CM_MC_READ_REQUEST = 125 -CB_PERF_SEL_FC_MC_READ_REQUEST = 126 -CB_PERF_SEL_CC_MC_READ_REQUEST = 127 -CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 128 -CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 129 -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 130 -CB_PERF_SEL_CM_TQ_FULL = 131 -CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 132 -CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL = 133 -CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 -CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 -CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 -CB_PERF_SEL_FC_TILE_STUTTER_STALL = 137 -CB_PERF_SEL_FC_QUAD_STUTTER_STALL = 138 -CB_PERF_SEL_FC_KEYID_STUTTER_STALL = 139 -CB_PERF_SEL_FOP_FMASK_RAW_STALL = 140 -CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 141 -CB_PERF_SEL_CC_SF_FULL = 142 -CB_PERF_SEL_CC_RB_FULL = 143 -CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 144 -CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 145 -CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL = 146 -CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL = 147 -CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 148 -CB_PERF_SEL_EVENT = 149 -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 150 -CB_PERF_SEL_EVENT_CONTEXT_DONE = 151 -CB_PERF_SEL_EVENT_CACHE_FLUSH = 152 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 153 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 154 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 155 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 156 -CB_PERF_SEL_CC_SURFACE_SYNC = 157 -CB_PERF_SEL_CMASK_READ_DATA_0xC = 158 -CB_PERF_SEL_CMASK_READ_DATA_0xD = 159 -CB_PERF_SEL_CMASK_READ_DATA_0xE = 160 -CB_PERF_SEL_CMASK_READ_DATA_0xF = 161 -CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 162 -CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 163 -CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 164 -CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 165 -CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 166 -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 167 -CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 168 -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 169 -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 170 -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 171 -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 172 -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 173 -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 174 -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 175 -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 176 -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 177 -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 178 -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 179 -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 180 -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 181 -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 182 -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 183 -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 184 -CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 185 -CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 186 -CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 187 -CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 188 -CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 189 -CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 190 -CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 191 -CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 192 -CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 193 -CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 194 -CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 195 -CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 196 -CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 197 -CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 198 -CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 199 -CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 200 -CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 201 -CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 202 -CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 203 -CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 204 -CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 205 -CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 206 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 207 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 208 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 209 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 210 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 211 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 212 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 213 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 214 -CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 215 -CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 216 -CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 217 -CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 218 -CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 219 -CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 220 -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 221 -CB_PERF_SEL_DRAWN_BUSY = 222 -CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 223 -CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 224 -CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 225 -CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 226 -CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 227 -CB_PERF_SEL_FC_SEQUENCER_CLEAR = 228 -CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 229 -CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 230 -CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 231 -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 232 -CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 233 -CB_PERF_SEL_FC_DOC_IS_STALLED = 234 -CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 235 -CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 236 -CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 237 -CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 238 -CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 239 -CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 240 -CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 241 -CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 242 -CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 243 -CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 244 -CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 245 -CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 246 -CB_PERF_SEL_FC_DCC_CACHE_HIT = 247 -CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 248 -CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 249 -CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 250 -CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 251 -CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 252 -CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 253 -CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 254 -CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 255 -CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 256 -CB_PERF_SEL_FC_DCC_CACHE_STALL = 257 -CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 258 -CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 259 -CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 260 -CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 261 -CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 262 -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 263 -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 264 -CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 265 -CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 266 -CB_PERF_SEL_CC_DCC_RDREQ_STALL = 267 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 268 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 269 -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 270 -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 271 -CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 272 -CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 273 -CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 274 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 276 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 277 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 278 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 279 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 281 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 282 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 283 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 284 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 285 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 286 -CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 287 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 288 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 289 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 290 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 291 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 292 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 293 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 294 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 295 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 296 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 297 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 298 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 299 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 300 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 301 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 302 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 303 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 304 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 305 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 306 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 307 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 308 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 309 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 310 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 311 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 312 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 313 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 314 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 315 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 316 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 317 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 318 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 319 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 320 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 321 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 322 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 323 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 324 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 325 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 326 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 327 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 328 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 329 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 330 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 331 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 332 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 333 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 334 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 335 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 336 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 337 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 338 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 339 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 340 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 341 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 342 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 343 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 344 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 345 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 346 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 347 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 348 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 349 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 350 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 351 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 352 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 353 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 354 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 355 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 356 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 357 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 358 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 359 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 360 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 361 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 362 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 363 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 364 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 365 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 366 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 367 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 368 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 369 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 370 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 371 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 372 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 373 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 374 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 375 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 376 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 377 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 378 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 379 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 380 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 381 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 382 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 383 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 384 -CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 385 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 386 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 387 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 388 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 389 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 390 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 391 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 392 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 393 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 394 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 395 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 396 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 397 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 398 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 399 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 400 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 401 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 402 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 403 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 404 -CB_PERF_SEL_RBP_SPLIT_MICROTILE = 405 -CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 406 -CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 407 -CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 408 -CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 409 -CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 410 -CB_PERF_SEL_NACK_CM_READ = 411 -CB_PERF_SEL_NACK_CM_WRITE = 412 -CB_PERF_SEL_NACK_FC_READ = 413 -CB_PERF_SEL_NACK_FC_WRITE = 414 -CB_PERF_SEL_NACK_DC_READ = 415 -CB_PERF_SEL_NACK_DC_WRITE = 416 -CB_PERF_SEL_NACK_CC_READ = 417 -CB_PERF_SEL_NACK_CC_WRITE = 418 -CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 419 -CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 420 -CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 421 -CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 422 -CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 423 -CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 424 -CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 425 -CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 426 -CB_PERF_SEL_CM_MC_WRITE_ACK64B = 427 -CB_PERF_SEL_FC_MC_WRITE_ACK64B = 428 -CB_PERF_SEL_DC_MC_WRITE_ACK64B = 429 -CB_PERF_SEL_CC_MC_WRITE_ACK64B = 430 -CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 431 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 432 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 433 -CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 434 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 435 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 436 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 437 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 438 -CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 439 -CB_PERF_SEL_DB_CB_CONTEXT_DONE = 440 -CB_PERF_SEL_DB_CB_EOP_DONE = 441 -CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 442 -CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 443 -CBPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskAddr' -CmaskAddr__enumvalues = { - 0: 'CMASK_ADDR_TILED', - 1: 'CMASK_ADDR_LINEAR', - 2: 'CMASK_ADDR_COMPATIBLE', -} -CMASK_ADDR_TILED = 0 -CMASK_ADDR_LINEAR = 1 -CMASK_ADDR_COMPATIBLE = 2 -CmaskAddr = ctypes.c_uint32 # enum - -# values for enumeration 'SourceFormat' -SourceFormat__enumvalues = { - 0: 'EXPORT_4C_32BPC', - 1: 'EXPORT_4C_16BPC', - 2: 'EXPORT_2C_32BPC_GR', - 3: 'EXPORT_2C_32BPC_AR', -} -EXPORT_4C_32BPC = 0 -EXPORT_4C_16BPC = 1 -EXPORT_2C_32BPC_GR = 2 -EXPORT_2C_32BPC_AR = 3 -SourceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP_MASKS' -TC_OP_MASKS__enumvalues = { - 8: 'TC_OP_MASK_FLUSH_DENROM', - 32: 'TC_OP_MASK_64', - 64: 'TC_OP_MASK_NO_RTN', -} -TC_OP_MASK_FLUSH_DENROM = 8 -TC_OP_MASK_64 = 32 -TC_OP_MASK_NO_RTN = 64 -TC_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP' -TC_OP__enumvalues = { - 0: 'TC_OP_READ', - 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'TC_OP_ATOMIC_FMIN_RTN_32', - 3: 'TC_OP_ATOMIC_FMAX_RTN_32', - 4: 'TC_OP_RESERVED_FOP_RTN_32_0', - 5: 'TC_OP_RESERVED_FOP_RTN_32_1', - 6: 'TC_OP_RESERVED_FOP_RTN_32_2', - 7: 'TC_OP_ATOMIC_SWAP_RTN_32', - 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'TC_OP_PROBE_FILTER', - 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'TC_OP_ATOMIC_ADD_RTN_32', - 16: 'TC_OP_ATOMIC_SUB_RTN_32', - 17: 'TC_OP_ATOMIC_SMIN_RTN_32', - 18: 'TC_OP_ATOMIC_UMIN_RTN_32', - 19: 'TC_OP_ATOMIC_SMAX_RTN_32', - 20: 'TC_OP_ATOMIC_UMAX_RTN_32', - 21: 'TC_OP_ATOMIC_AND_RTN_32', - 22: 'TC_OP_ATOMIC_OR_RTN_32', - 23: 'TC_OP_ATOMIC_XOR_RTN_32', - 24: 'TC_OP_ATOMIC_INC_RTN_32', - 25: 'TC_OP_ATOMIC_DEC_RTN_32', - 26: 'TC_OP_WBINVL1_VOL', - 27: 'TC_OP_WBINVL1_SD', - 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 32: 'TC_OP_WRITE', - 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'TC_OP_ATOMIC_FMIN_RTN_64', - 35: 'TC_OP_ATOMIC_FMAX_RTN_64', - 36: 'TC_OP_RESERVED_FOP_RTN_64_0', - 37: 'TC_OP_RESERVED_FOP_RTN_64_1', - 38: 'TC_OP_RESERVED_FOP_RTN_64_2', - 39: 'TC_OP_ATOMIC_SWAP_RTN_64', - 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 44: 'TC_OP_WBINVL2_SD', - 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 47: 'TC_OP_ATOMIC_ADD_RTN_64', - 48: 'TC_OP_ATOMIC_SUB_RTN_64', - 49: 'TC_OP_ATOMIC_SMIN_RTN_64', - 50: 'TC_OP_ATOMIC_UMIN_RTN_64', - 51: 'TC_OP_ATOMIC_SMAX_RTN_64', - 52: 'TC_OP_ATOMIC_UMAX_RTN_64', - 53: 'TC_OP_ATOMIC_AND_RTN_64', - 54: 'TC_OP_ATOMIC_OR_RTN_64', - 55: 'TC_OP_ATOMIC_XOR_RTN_64', - 56: 'TC_OP_ATOMIC_INC_RTN_64', - 57: 'TC_OP_ATOMIC_DEC_RTN_64', - 58: 'TC_OP_WBL2_NC', - 59: 'TC_OP_WBL2_WC', - 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', - 64: 'TC_OP_WBINVL1', - 65: 'TC_OP_ATOMIC_FCMPSWAP_32', - 66: 'TC_OP_ATOMIC_FMIN_32', - 67: 'TC_OP_ATOMIC_FMAX_32', - 68: 'TC_OP_RESERVED_FOP_32_0', - 69: 'TC_OP_RESERVED_FOP_32_1', - 70: 'TC_OP_RESERVED_FOP_32_2', - 71: 'TC_OP_ATOMIC_SWAP_32', - 72: 'TC_OP_ATOMIC_CMPSWAP_32', - 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'TC_OP_INV_METADATA', - 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', - 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 79: 'TC_OP_ATOMIC_ADD_32', - 80: 'TC_OP_ATOMIC_SUB_32', - 81: 'TC_OP_ATOMIC_SMIN_32', - 82: 'TC_OP_ATOMIC_UMIN_32', - 83: 'TC_OP_ATOMIC_SMAX_32', - 84: 'TC_OP_ATOMIC_UMAX_32', - 85: 'TC_OP_ATOMIC_AND_32', - 86: 'TC_OP_ATOMIC_OR_32', - 87: 'TC_OP_ATOMIC_XOR_32', - 88: 'TC_OP_ATOMIC_INC_32', - 89: 'TC_OP_ATOMIC_DEC_32', - 90: 'TC_OP_INVL2_NC', - 91: 'TC_OP_NOP_RTN0', - 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', - 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', - 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', - 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', - 96: 'TC_OP_WBINVL2', - 97: 'TC_OP_ATOMIC_FCMPSWAP_64', - 98: 'TC_OP_ATOMIC_FMIN_64', - 99: 'TC_OP_ATOMIC_FMAX_64', - 100: 'TC_OP_RESERVED_FOP_64_0', - 101: 'TC_OP_RESERVED_FOP_64_1', - 102: 'TC_OP_RESERVED_FOP_64_2', - 103: 'TC_OP_ATOMIC_SWAP_64', - 104: 'TC_OP_ATOMIC_CMPSWAP_64', - 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 111: 'TC_OP_ATOMIC_ADD_64', - 112: 'TC_OP_ATOMIC_SUB_64', - 113: 'TC_OP_ATOMIC_SMIN_64', - 114: 'TC_OP_ATOMIC_UMIN_64', - 115: 'TC_OP_ATOMIC_SMAX_64', - 116: 'TC_OP_ATOMIC_UMAX_64', - 117: 'TC_OP_ATOMIC_AND_64', - 118: 'TC_OP_ATOMIC_OR_64', - 119: 'TC_OP_ATOMIC_XOR_64', - 120: 'TC_OP_ATOMIC_INC_64', - 121: 'TC_OP_ATOMIC_DEC_64', - 122: 'TC_OP_WBINVL2_NC', - 123: 'TC_OP_NOP_ACK', - 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', - 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', - 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', - 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', -} -TC_OP_READ = 0 -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -TC_OP_ATOMIC_FMIN_RTN_32 = 2 -TC_OP_ATOMIC_FMAX_RTN_32 = 3 -TC_OP_RESERVED_FOP_RTN_32_0 = 4 -TC_OP_RESERVED_FOP_RTN_32_1 = 5 -TC_OP_RESERVED_FOP_RTN_32_2 = 6 -TC_OP_ATOMIC_SWAP_RTN_32 = 7 -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -TC_OP_PROBE_FILTER = 12 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -TC_OP_ATOMIC_ADD_RTN_32 = 15 -TC_OP_ATOMIC_SUB_RTN_32 = 16 -TC_OP_ATOMIC_SMIN_RTN_32 = 17 -TC_OP_ATOMIC_UMIN_RTN_32 = 18 -TC_OP_ATOMIC_SMAX_RTN_32 = 19 -TC_OP_ATOMIC_UMAX_RTN_32 = 20 -TC_OP_ATOMIC_AND_RTN_32 = 21 -TC_OP_ATOMIC_OR_RTN_32 = 22 -TC_OP_ATOMIC_XOR_RTN_32 = 23 -TC_OP_ATOMIC_INC_RTN_32 = 24 -TC_OP_ATOMIC_DEC_RTN_32 = 25 -TC_OP_WBINVL1_VOL = 26 -TC_OP_WBINVL1_SD = 27 -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 -TC_OP_WRITE = 32 -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -TC_OP_ATOMIC_FMIN_RTN_64 = 34 -TC_OP_ATOMIC_FMAX_RTN_64 = 35 -TC_OP_RESERVED_FOP_RTN_64_0 = 36 -TC_OP_RESERVED_FOP_RTN_64_1 = 37 -TC_OP_RESERVED_FOP_RTN_64_2 = 38 -TC_OP_ATOMIC_SWAP_RTN_64 = 39 -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -TC_OP_WBINVL2_SD = 44 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 -TC_OP_ATOMIC_ADD_RTN_64 = 47 -TC_OP_ATOMIC_SUB_RTN_64 = 48 -TC_OP_ATOMIC_SMIN_RTN_64 = 49 -TC_OP_ATOMIC_UMIN_RTN_64 = 50 -TC_OP_ATOMIC_SMAX_RTN_64 = 51 -TC_OP_ATOMIC_UMAX_RTN_64 = 52 -TC_OP_ATOMIC_AND_RTN_64 = 53 -TC_OP_ATOMIC_OR_RTN_64 = 54 -TC_OP_ATOMIC_XOR_RTN_64 = 55 -TC_OP_ATOMIC_INC_RTN_64 = 56 -TC_OP_ATOMIC_DEC_RTN_64 = 57 -TC_OP_WBL2_NC = 58 -TC_OP_WBL2_WC = 59 -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 -TC_OP_WBINVL1 = 64 -TC_OP_ATOMIC_FCMPSWAP_32 = 65 -TC_OP_ATOMIC_FMIN_32 = 66 -TC_OP_ATOMIC_FMAX_32 = 67 -TC_OP_RESERVED_FOP_32_0 = 68 -TC_OP_RESERVED_FOP_32_1 = 69 -TC_OP_RESERVED_FOP_32_2 = 70 -TC_OP_ATOMIC_SWAP_32 = 71 -TC_OP_ATOMIC_CMPSWAP_32 = 72 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -TC_OP_INV_METADATA = 76 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 -TC_OP_ATOMIC_ADD_32 = 79 -TC_OP_ATOMIC_SUB_32 = 80 -TC_OP_ATOMIC_SMIN_32 = 81 -TC_OP_ATOMIC_UMIN_32 = 82 -TC_OP_ATOMIC_SMAX_32 = 83 -TC_OP_ATOMIC_UMAX_32 = 84 -TC_OP_ATOMIC_AND_32 = 85 -TC_OP_ATOMIC_OR_32 = 86 -TC_OP_ATOMIC_XOR_32 = 87 -TC_OP_ATOMIC_INC_32 = 88 -TC_OP_ATOMIC_DEC_32 = 89 -TC_OP_INVL2_NC = 90 -TC_OP_NOP_RTN0 = 91 -TC_OP_RESERVED_NON_FLOAT_32_1 = 92 -TC_OP_RESERVED_NON_FLOAT_32_2 = 93 -TC_OP_RESERVED_NON_FLOAT_32_3 = 94 -TC_OP_RESERVED_NON_FLOAT_32_4 = 95 -TC_OP_WBINVL2 = 96 -TC_OP_ATOMIC_FCMPSWAP_64 = 97 -TC_OP_ATOMIC_FMIN_64 = 98 -TC_OP_ATOMIC_FMAX_64 = 99 -TC_OP_RESERVED_FOP_64_0 = 100 -TC_OP_RESERVED_FOP_64_1 = 101 -TC_OP_RESERVED_FOP_64_2 = 102 -TC_OP_ATOMIC_SWAP_64 = 103 -TC_OP_ATOMIC_CMPSWAP_64 = 104 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 -TC_OP_ATOMIC_ADD_64 = 111 -TC_OP_ATOMIC_SUB_64 = 112 -TC_OP_ATOMIC_SMIN_64 = 113 -TC_OP_ATOMIC_UMIN_64 = 114 -TC_OP_ATOMIC_SMAX_64 = 115 -TC_OP_ATOMIC_UMAX_64 = 116 -TC_OP_ATOMIC_AND_64 = 117 -TC_OP_ATOMIC_OR_64 = 118 -TC_OP_ATOMIC_XOR_64 = 119 -TC_OP_ATOMIC_INC_64 = 120 -TC_OP_ATOMIC_DEC_64 = 121 -TC_OP_WBINVL2_NC = 122 -TC_OP_NOP_ACK = 123 -TC_OP_RESERVED_NON_FLOAT_64_1 = 124 -TC_OP_RESERVED_NON_FLOAT_64_2 = 125 -TC_OP_RESERVED_NON_FLOAT_64_3 = 126 -TC_OP_RESERVED_NON_FLOAT_64_4 = 127 -TC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'TC_NACKS' -TC_NACKS__enumvalues = { - 0: 'TC_NACK_NO_FAULT', - 1: 'TC_NACK_PAGE_FAULT', - 2: 'TC_NACK_PROTECTION_FAULT', - 3: 'TC_NACK_DATA_ERROR', -} -TC_NACK_NO_FAULT = 0 -TC_NACK_PAGE_FAULT = 1 -TC_NACK_PROTECTION_FAULT = 2 -TC_NACK_DATA_ERROR = 3 -TC_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_EA_CID' -TC_EA_CID__enumvalues = { - 0: 'TC_EA_CID_RT', - 1: 'TC_EA_CID_FMASK', - 2: 'TC_EA_CID_DCC', - 3: 'TC_EA_CID_TCPMETA', - 4: 'TC_EA_CID_Z', - 5: 'TC_EA_CID_STENCIL', - 6: 'TC_EA_CID_HTILE', - 7: 'TC_EA_CID_MISC', - 8: 'TC_EA_CID_TCP', - 9: 'TC_EA_CID_SQC', - 10: 'TC_EA_CID_CPF', - 11: 'TC_EA_CID_CPG', - 12: 'TC_EA_CID_IA', - 13: 'TC_EA_CID_WD', - 14: 'TC_EA_CID_PA', - 15: 'TC_EA_CID_UTCL2_TPI', -} -TC_EA_CID_RT = 0 -TC_EA_CID_FMASK = 1 -TC_EA_CID_DCC = 2 -TC_EA_CID_TCPMETA = 3 -TC_EA_CID_Z = 4 -TC_EA_CID_STENCIL = 5 -TC_EA_CID_HTILE = 6 -TC_EA_CID_MISC = 7 -TC_EA_CID_TCP = 8 -TC_EA_CID_SQC = 9 -TC_EA_CID_CPF = 10 -TC_EA_CID_CPG = 11 -TC_EA_CID_IA = 12 -TC_EA_CID_WD = 13 -TC_EA_CID_PA = 14 -TC_EA_CID_UTCL2_TPI = 15 -TC_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP_MASKS' -GL2_OP_MASKS__enumvalues = { - 8: 'GL2_OP_MASK_FLUSH_DENROM', - 32: 'GL2_OP_MASK_64', - 64: 'GL2_OP_MASK_NO_RTN', -} -GL2_OP_MASK_FLUSH_DENROM = 8 -GL2_OP_MASK_64 = 32 -GL2_OP_MASK_NO_RTN = 64 -GL2_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP' -GL2_OP__enumvalues = { - 0: 'GL2_OP_READ', - 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', - 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', - 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', - 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'GL2_OP_PROBE_FILTER', - 13: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'GL2_OP_ATOMIC_ADD_RTN_32', - 16: 'GL2_OP_ATOMIC_SUB_RTN_32', - 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', - 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', - 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', - 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', - 21: 'GL2_OP_ATOMIC_AND_RTN_32', - 22: 'GL2_OP_ATOMIC_OR_RTN_32', - 23: 'GL2_OP_ATOMIC_XOR_RTN_32', - 24: 'GL2_OP_ATOMIC_INC_RTN_32', - 25: 'GL2_OP_ATOMIC_DEC_RTN_32', - 32: 'GL2_OP_WRITE', - 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', - 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', - 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', - 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 47: 'GL2_OP_ATOMIC_ADD_RTN_64', - 48: 'GL2_OP_ATOMIC_SUB_RTN_64', - 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', - 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', - 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', - 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', - 53: 'GL2_OP_ATOMIC_AND_RTN_64', - 54: 'GL2_OP_ATOMIC_OR_RTN_64', - 55: 'GL2_OP_ATOMIC_XOR_RTN_64', - 56: 'GL2_OP_ATOMIC_INC_RTN_64', - 57: 'GL2_OP_ATOMIC_DEC_RTN_64', - 64: 'GL2_OP_GL1_INV', - 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', - 66: 'GL2_OP_ATOMIC_FMIN_32', - 67: 'GL2_OP_ATOMIC_FMAX_32', - 71: 'GL2_OP_ATOMIC_SWAP_32', - 72: 'GL2_OP_ATOMIC_CMPSWAP_32', - 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 79: 'GL2_OP_ATOMIC_ADD_32', - 80: 'GL2_OP_ATOMIC_SUB_32', - 81: 'GL2_OP_ATOMIC_SMIN_32', - 82: 'GL2_OP_ATOMIC_UMIN_32', - 83: 'GL2_OP_ATOMIC_SMAX_32', - 84: 'GL2_OP_ATOMIC_UMAX_32', - 85: 'GL2_OP_ATOMIC_AND_32', - 86: 'GL2_OP_ATOMIC_OR_32', - 87: 'GL2_OP_ATOMIC_XOR_32', - 88: 'GL2_OP_ATOMIC_INC_32', - 89: 'GL2_OP_ATOMIC_DEC_32', - 91: 'GL2_OP_NOP_RTN0', - 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', - 98: 'GL2_OP_ATOMIC_FMIN_64', - 99: 'GL2_OP_ATOMIC_FMAX_64', - 103: 'GL2_OP_ATOMIC_SWAP_64', - 104: 'GL2_OP_ATOMIC_CMPSWAP_64', - 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 111: 'GL2_OP_ATOMIC_ADD_64', - 112: 'GL2_OP_ATOMIC_SUB_64', - 113: 'GL2_OP_ATOMIC_SMIN_64', - 114: 'GL2_OP_ATOMIC_UMIN_64', - 115: 'GL2_OP_ATOMIC_SMAX_64', - 116: 'GL2_OP_ATOMIC_UMAX_64', - 117: 'GL2_OP_ATOMIC_AND_64', - 118: 'GL2_OP_ATOMIC_OR_64', - 119: 'GL2_OP_ATOMIC_XOR_64', - 120: 'GL2_OP_ATOMIC_INC_64', - 121: 'GL2_OP_ATOMIC_DEC_64', - 123: 'GL2_OP_NOP_ACK', -} -GL2_OP_READ = 0 -GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -GL2_OP_ATOMIC_FMIN_RTN_32 = 2 -GL2_OP_ATOMIC_FMAX_RTN_32 = 3 -GL2_OP_ATOMIC_SWAP_RTN_32 = 7 -GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -GL2_OP_PROBE_FILTER = 12 -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -GL2_OP_ATOMIC_ADD_RTN_32 = 15 -GL2_OP_ATOMIC_SUB_RTN_32 = 16 -GL2_OP_ATOMIC_SMIN_RTN_32 = 17 -GL2_OP_ATOMIC_UMIN_RTN_32 = 18 -GL2_OP_ATOMIC_SMAX_RTN_32 = 19 -GL2_OP_ATOMIC_UMAX_RTN_32 = 20 -GL2_OP_ATOMIC_AND_RTN_32 = 21 -GL2_OP_ATOMIC_OR_RTN_32 = 22 -GL2_OP_ATOMIC_XOR_RTN_32 = 23 -GL2_OP_ATOMIC_INC_RTN_32 = 24 -GL2_OP_ATOMIC_DEC_RTN_32 = 25 -GL2_OP_WRITE = 32 -GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -GL2_OP_ATOMIC_FMIN_RTN_64 = 34 -GL2_OP_ATOMIC_FMAX_RTN_64 = 35 -GL2_OP_ATOMIC_SWAP_RTN_64 = 39 -GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -GL2_OP_ATOMIC_ADD_RTN_64 = 47 -GL2_OP_ATOMIC_SUB_RTN_64 = 48 -GL2_OP_ATOMIC_SMIN_RTN_64 = 49 -GL2_OP_ATOMIC_UMIN_RTN_64 = 50 -GL2_OP_ATOMIC_SMAX_RTN_64 = 51 -GL2_OP_ATOMIC_UMAX_RTN_64 = 52 -GL2_OP_ATOMIC_AND_RTN_64 = 53 -GL2_OP_ATOMIC_OR_RTN_64 = 54 -GL2_OP_ATOMIC_XOR_RTN_64 = 55 -GL2_OP_ATOMIC_INC_RTN_64 = 56 -GL2_OP_ATOMIC_DEC_RTN_64 = 57 -GL2_OP_GL1_INV = 64 -GL2_OP_ATOMIC_FCMPSWAP_32 = 65 -GL2_OP_ATOMIC_FMIN_32 = 66 -GL2_OP_ATOMIC_FMAX_32 = 67 -GL2_OP_ATOMIC_SWAP_32 = 71 -GL2_OP_ATOMIC_CMPSWAP_32 = 72 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -GL2_OP_ATOMIC_ADD_32 = 79 -GL2_OP_ATOMIC_SUB_32 = 80 -GL2_OP_ATOMIC_SMIN_32 = 81 -GL2_OP_ATOMIC_UMIN_32 = 82 -GL2_OP_ATOMIC_SMAX_32 = 83 -GL2_OP_ATOMIC_UMAX_32 = 84 -GL2_OP_ATOMIC_AND_32 = 85 -GL2_OP_ATOMIC_OR_32 = 86 -GL2_OP_ATOMIC_XOR_32 = 87 -GL2_OP_ATOMIC_INC_32 = 88 -GL2_OP_ATOMIC_DEC_32 = 89 -GL2_OP_NOP_RTN0 = 91 -GL2_OP_ATOMIC_FCMPSWAP_64 = 97 -GL2_OP_ATOMIC_FMIN_64 = 98 -GL2_OP_ATOMIC_FMAX_64 = 99 -GL2_OP_ATOMIC_SWAP_64 = 103 -GL2_OP_ATOMIC_CMPSWAP_64 = 104 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -GL2_OP_ATOMIC_ADD_64 = 111 -GL2_OP_ATOMIC_SUB_64 = 112 -GL2_OP_ATOMIC_SMIN_64 = 113 -GL2_OP_ATOMIC_UMIN_64 = 114 -GL2_OP_ATOMIC_SMAX_64 = 115 -GL2_OP_ATOMIC_UMAX_64 = 116 -GL2_OP_ATOMIC_AND_64 = 117 -GL2_OP_ATOMIC_OR_64 = 118 -GL2_OP_ATOMIC_XOR_64 = 119 -GL2_OP_ATOMIC_INC_64 = 120 -GL2_OP_ATOMIC_DEC_64 = 121 -GL2_OP_NOP_ACK = 123 -GL2_OP = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_NACKS' -GL2_NACKS__enumvalues = { - 0: 'GL2_NACK_NO_FAULT', - 1: 'GL2_NACK_PAGE_FAULT', - 2: 'GL2_NACK_PROTECTION_FAULT', - 3: 'GL2_NACK_DATA_ERROR', -} -GL2_NACK_NO_FAULT = 0 -GL2_NACK_PAGE_FAULT = 1 -GL2_NACK_PROTECTION_FAULT = 2 -GL2_NACK_DATA_ERROR = 3 -GL2_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_EA_CID' -GL2_EA_CID__enumvalues = { - 0: 'GL2_EA_CID_CLIENT', - 1: 'GL2_EA_CID_SDMA', - 2: 'GL2_EA_CID_RLC', - 4: 'GL2_EA_CID_CP', - 5: 'GL2_EA_CID_CPDMA', - 6: 'GL2_EA_CID_UTCL2', - 7: 'GL2_EA_CID_RT', - 8: 'GL2_EA_CID_FMASK', - 9: 'GL2_EA_CID_DCC', - 10: 'GL2_EA_CID_Z_STENCIL', - 11: 'GL2_EA_CID_ZPCPSD', - 12: 'GL2_EA_CID_HTILE', - 15: 'GL2_EA_CID_TCPMETA', -} -GL2_EA_CID_CLIENT = 0 -GL2_EA_CID_SDMA = 1 -GL2_EA_CID_RLC = 2 -GL2_EA_CID_CP = 4 -GL2_EA_CID_CPDMA = 5 -GL2_EA_CID_UTCL2 = 6 -GL2_EA_CID_RT = 7 -GL2_EA_CID_FMASK = 8 -GL2_EA_CID_DCC = 9 -GL2_EA_CID_Z_STENCIL = 10 -GL2_EA_CID_ZPCPSD = 11 -GL2_EA_CID_HTILE = 12 -GL2_EA_CID_TCPMETA = 15 -GL2_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SAMPLE_CNTL' -SPI_SAMPLE_CNTL__enumvalues = { - 0: 'CENTROIDS_ONLY', - 1: 'CENTERS_ONLY', - 2: 'CENTROIDS_AND_CENTERS', - 3: 'UNDEF', -} -CENTROIDS_ONLY = 0 -CENTERS_ONLY = 1 -CENTROIDS_AND_CENTERS = 2 -UNDEF = 3 -SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_FOG_MODE' -SPI_FOG_MODE__enumvalues = { - 0: 'SPI_FOG_NONE', - 1: 'SPI_FOG_EXP', - 2: 'SPI_FOG_EXP2', - 3: 'SPI_FOG_LINEAR', -} -SPI_FOG_NONE = 0 -SPI_FOG_EXP = 1 -SPI_FOG_EXP2 = 2 -SPI_FOG_LINEAR = 3 -SPI_FOG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' -SPI_PNT_SPRITE_OVERRIDE__enumvalues = { - 0: 'SPI_PNT_SPRITE_SEL_0', - 1: 'SPI_PNT_SPRITE_SEL_1', - 2: 'SPI_PNT_SPRITE_SEL_S', - 3: 'SPI_PNT_SPRITE_SEL_T', - 4: 'SPI_PNT_SPRITE_SEL_NONE', -} -SPI_PNT_SPRITE_SEL_0 = 0 -SPI_PNT_SPRITE_SEL_1 = 1 -SPI_PNT_SPRITE_SEL_S = 2 -SPI_PNT_SPRITE_SEL_T = 3 -SPI_PNT_SPRITE_SEL_NONE = 4 -SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PERFCNT_SEL' -SPI_PERFCNT_SEL__enumvalues = { - 0: 'SPI_PERF_VS_WINDOW_VALID', - 1: 'SPI_PERF_VS_BUSY', - 2: 'SPI_PERF_VS_FIRST_WAVE', - 3: 'SPI_PERF_VS_LAST_WAVE', - 4: 'SPI_PERF_VS_LSHS_DEALLOC', - 5: 'SPI_PERF_VS_PC_STALL', - 6: 'SPI_PERF_VS_POS0_STALL', - 7: 'SPI_PERF_VS_POS1_STALL', - 8: 'SPI_PERF_VS_CRAWLER_STALL', - 9: 'SPI_PERF_VS_EVENT_WAVE', - 10: 'SPI_PERF_VS_WAVE', - 11: 'SPI_PERF_VS_PERS_UPD_FULL0', - 12: 'SPI_PERF_VS_PERS_UPD_FULL1', - 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', - 14: 'SPI_PERF_VS_FIRST_SUBGRP', - 15: 'SPI_PERF_VS_LAST_SUBGRP', - 16: 'SPI_PERF_VS_ALLOC_CNT', - 17: 'SPI_PERF_VS_PC_ALLOC_CNT', - 18: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', - 19: 'SPI_PERF_GS_WINDOW_VALID', - 20: 'SPI_PERF_GS_BUSY', - 21: 'SPI_PERF_GS_CRAWLER_STALL', - 22: 'SPI_PERF_GS_EVENT_WAVE', - 23: 'SPI_PERF_GS_WAVE', - 24: 'SPI_PERF_GS_PERS_UPD_FULL0', - 25: 'SPI_PERF_GS_PERS_UPD_FULL1', - 26: 'SPI_PERF_GS_FIRST_SUBGRP', - 27: 'SPI_PERF_GS_LAST_SUBGRP', - 28: 'SPI_PERF_GS_HS_DEALLOC', - 29: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 30: 'SPI_PERF_GS_GRP_FIFO_FULL', - 31: 'SPI_PERF_HS_WINDOW_VALID', - 32: 'SPI_PERF_HS_BUSY', - 33: 'SPI_PERF_HS_CRAWLER_STALL', - 34: 'SPI_PERF_HS_FIRST_WAVE', - 35: 'SPI_PERF_HS_LAST_WAVE', - 36: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', - 37: 'SPI_PERF_HS_EVENT_WAVE', - 38: 'SPI_PERF_HS_WAVE', - 39: 'SPI_PERF_HS_PERS_UPD_FULL0', - 40: 'SPI_PERF_HS_PERS_UPD_FULL1', - 41: 'SPI_PERF_CSG_WINDOW_VALID', - 42: 'SPI_PERF_CSG_BUSY', - 43: 'SPI_PERF_CSG_NUM_THREADGROUPS', - 44: 'SPI_PERF_CSG_CRAWLER_STALL', - 45: 'SPI_PERF_CSG_EVENT_WAVE', - 46: 'SPI_PERF_CSG_WAVE', - 47: 'SPI_PERF_CSN_WINDOW_VALID', - 48: 'SPI_PERF_CSN_BUSY', - 49: 'SPI_PERF_CSN_NUM_THREADGROUPS', - 50: 'SPI_PERF_CSN_CRAWLER_STALL', - 51: 'SPI_PERF_CSN_EVENT_WAVE', - 52: 'SPI_PERF_CSN_WAVE', - 53: 'SPI_PERF_PS0_WINDOW_VALID', - 54: 'SPI_PERF_PS1_WINDOW_VALID', - 55: 'SPI_PERF_PS2_WINDOW_VALID', - 56: 'SPI_PERF_PS3_WINDOW_VALID', - 57: 'SPI_PERF_PS0_BUSY', - 58: 'SPI_PERF_PS1_BUSY', - 59: 'SPI_PERF_PS2_BUSY', - 60: 'SPI_PERF_PS3_BUSY', - 61: 'SPI_PERF_PS0_ACTIVE', - 62: 'SPI_PERF_PS1_ACTIVE', - 63: 'SPI_PERF_PS2_ACTIVE', - 64: 'SPI_PERF_PS3_ACTIVE', - 65: 'SPI_PERF_PS0_DEALLOC_BIN0', - 66: 'SPI_PERF_PS1_DEALLOC_BIN0', - 67: 'SPI_PERF_PS2_DEALLOC_BIN0', - 68: 'SPI_PERF_PS3_DEALLOC_BIN0', - 69: 'SPI_PERF_PS0_FPOS_BIN1_STALL', - 70: 'SPI_PERF_PS1_FPOS_BIN1_STALL', - 71: 'SPI_PERF_PS2_FPOS_BIN1_STALL', - 72: 'SPI_PERF_PS3_FPOS_BIN1_STALL', - 73: 'SPI_PERF_PS0_EVENT_WAVE', - 74: 'SPI_PERF_PS1_EVENT_WAVE', - 75: 'SPI_PERF_PS2_EVENT_WAVE', - 76: 'SPI_PERF_PS3_EVENT_WAVE', - 77: 'SPI_PERF_PS0_WAVE', - 78: 'SPI_PERF_PS1_WAVE', - 79: 'SPI_PERF_PS2_WAVE', - 80: 'SPI_PERF_PS3_WAVE', - 81: 'SPI_PERF_PS0_OPT_WAVE', - 82: 'SPI_PERF_PS1_OPT_WAVE', - 83: 'SPI_PERF_PS2_OPT_WAVE', - 84: 'SPI_PERF_PS3_OPT_WAVE', - 85: 'SPI_PERF_PS0_PASS_BIN0', - 86: 'SPI_PERF_PS1_PASS_BIN0', - 87: 'SPI_PERF_PS2_PASS_BIN0', - 88: 'SPI_PERF_PS3_PASS_BIN0', - 89: 'SPI_PERF_PS0_PASS_BIN1', - 90: 'SPI_PERF_PS1_PASS_BIN1', - 91: 'SPI_PERF_PS2_PASS_BIN1', - 92: 'SPI_PERF_PS3_PASS_BIN1', - 93: 'SPI_PERF_PS0_FPOS_BIN2', - 94: 'SPI_PERF_PS1_FPOS_BIN2', - 95: 'SPI_PERF_PS2_FPOS_BIN2', - 96: 'SPI_PERF_PS3_FPOS_BIN2', - 97: 'SPI_PERF_PS0_PRIM_BIN0', - 98: 'SPI_PERF_PS1_PRIM_BIN0', - 99: 'SPI_PERF_PS2_PRIM_BIN0', - 100: 'SPI_PERF_PS3_PRIM_BIN0', - 101: 'SPI_PERF_PS0_PRIM_BIN1', - 102: 'SPI_PERF_PS1_PRIM_BIN1', - 103: 'SPI_PERF_PS2_PRIM_BIN1', - 104: 'SPI_PERF_PS3_PRIM_BIN1', - 105: 'SPI_PERF_PS0_CNF_BIN2', - 106: 'SPI_PERF_PS1_CNF_BIN2', - 107: 'SPI_PERF_PS2_CNF_BIN2', - 108: 'SPI_PERF_PS3_CNF_BIN2', - 109: 'SPI_PERF_PS0_CNF_BIN3', - 110: 'SPI_PERF_PS1_CNF_BIN3', - 111: 'SPI_PERF_PS2_CNF_BIN3', - 112: 'SPI_PERF_PS3_CNF_BIN3', - 113: 'SPI_PERF_PS0_CRAWLER_STALL', - 114: 'SPI_PERF_PS1_CRAWLER_STALL', - 115: 'SPI_PERF_PS2_CRAWLER_STALL', - 116: 'SPI_PERF_PS3_CRAWLER_STALL', - 117: 'SPI_PERF_PS0_LDS_RES_FULL', - 118: 'SPI_PERF_PS1_LDS_RES_FULL', - 119: 'SPI_PERF_PS2_LDS_RES_FULL', - 120: 'SPI_PERF_PS3_LDS_RES_FULL', - 121: 'SPI_PERF_PS_PERS_UPD_FULL0', - 122: 'SPI_PERF_PS_PERS_UPD_FULL1', - 123: 'SPI_PERF_PS0_POPS_WAVE_SENT', - 124: 'SPI_PERF_PS1_POPS_WAVE_SENT', - 125: 'SPI_PERF_PS2_POPS_WAVE_SENT', - 126: 'SPI_PERF_PS3_POPS_WAVE_SENT', - 127: 'SPI_PERF_PS0_POPS_WAVE_EXIT', - 128: 'SPI_PERF_PS1_POPS_WAVE_EXIT', - 129: 'SPI_PERF_PS2_POPS_WAVE_EXIT', - 130: 'SPI_PERF_PS3_POPS_WAVE_EXIT', - 131: 'SPI_PERF_LDS0_PC_VALID', - 132: 'SPI_PERF_LDS1_PC_VALID', - 133: 'SPI_PERF_RA_PIPE_REQ_BIN2', - 134: 'SPI_PERF_RA_TASK_REQ_BIN3', - 135: 'SPI_PERF_RA_WR_CTL_FULL', - 136: 'SPI_PERF_RA_REQ_NO_ALLOC', - 137: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 138: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', - 139: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 140: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 141: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 142: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 143: 'SPI_PERF_RA_RES_STALL_PS', - 144: 'SPI_PERF_RA_RES_STALL_VS', - 145: 'SPI_PERF_RA_RES_STALL_GS', - 146: 'SPI_PERF_RA_RES_STALL_HS', - 147: 'SPI_PERF_RA_RES_STALL_CSG', - 148: 'SPI_PERF_RA_RES_STALL_CSN', - 149: 'SPI_PERF_RA_TMP_STALL_PS', - 150: 'SPI_PERF_RA_TMP_STALL_VS', - 151: 'SPI_PERF_RA_TMP_STALL_GS', - 152: 'SPI_PERF_RA_TMP_STALL_HS', - 153: 'SPI_PERF_RA_TMP_STALL_CSG', - 154: 'SPI_PERF_RA_TMP_STALL_CSN', - 155: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 156: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', - 157: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 158: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 159: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', - 161: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 162: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', - 163: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 164: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', - 167: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', - 168: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', - 169: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', - 170: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', - 171: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', - 172: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', - 173: 'SPI_PERF_RA_LDS_CU_FULL_PS', - 174: 'SPI_PERF_RA_LDS_CU_FULL_LS', - 175: 'SPI_PERF_RA_LDS_CU_FULL_ES', - 176: 'SPI_PERF_RA_LDS_CU_FULL_CSG', - 177: 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 178: 'SPI_PERF_RA_BAR_CU_FULL_HS', - 179: 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 180: 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 181: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 182: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', - 184: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 185: 'SPI_PERF_RA_WVLIM_STALL_PS', - 186: 'SPI_PERF_RA_WVLIM_STALL_VS', - 187: 'SPI_PERF_RA_WVLIM_STALL_GS', - 188: 'SPI_PERF_RA_WVLIM_STALL_HS', - 189: 'SPI_PERF_RA_WVLIM_STALL_CSG', - 190: 'SPI_PERF_RA_WVLIM_STALL_CSN', - 191: 'SPI_PERF_RA_VS_LOCK', - 192: 'SPI_PERF_RA_GS_LOCK', - 193: 'SPI_PERF_RA_HS_LOCK', - 194: 'SPI_PERF_RA_CSG_LOCK', - 195: 'SPI_PERF_RA_CSN_LOCK', - 196: 'SPI_PERF_RA_RSV_UPD', - 197: 'SPI_PERF_EXP_ARB_COL_CNT', - 198: 'SPI_PERF_EXP_ARB_PAR_CNT', - 199: 'SPI_PERF_EXP_ARB_POS_CNT', - 200: 'SPI_PERF_EXP_ARB_GDS_CNT', - 201: 'SPI_PERF_NUM_PS_COL_R0_EXPORTS', - 202: 'SPI_PERF_NUM_PS_COL_R1_EXPORTS', - 203: 'SPI_PERF_NUM_VS_POS_R0_EXPORTS', - 204: 'SPI_PERF_NUM_VS_POS_R1_EXPORTS', - 205: 'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS', - 206: 'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS', - 207: 'SPI_PERF_NUM_VS_GDS_R0_EXPORTS', - 208: 'SPI_PERF_NUM_VS_GDS_R1_EXPORTS', - 209: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 210: 'SPI_PERF_CLKGATE_BUSY_STALL', - 211: 'SPI_PERF_CLKGATE_ACTIVE_STALL', - 212: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', - 213: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', - 214: 'SPI_PERF_CLKGATE_CGTT_REG_ON', - 215: 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 216: 'SPI_PERF_PIX_ALLOC_SCB0_STALL', - 217: 'SPI_PERF_PIX_ALLOC_SCB1_STALL', - 218: 'SPI_PERF_PIX_ALLOC_SCB2_STALL', - 219: 'SPI_PERF_PIX_ALLOC_SCB3_STALL', - 220: 'SPI_PERF_PIX_ALLOC_DB0_STALL', - 221: 'SPI_PERF_PIX_ALLOC_DB1_STALL', - 222: 'SPI_PERF_PIX_ALLOC_DB2_STALL', - 223: 'SPI_PERF_PIX_ALLOC_DB3_STALL', - 224: 'SPI_PERF_PIX_ALLOC_DB4_STALL', - 225: 'SPI_PERF_PIX_ALLOC_DB5_STALL', - 226: 'SPI_PERF_PIX_ALLOC_DB6_STALL', - 227: 'SPI_PERF_PIX_ALLOC_DB7_STALL', - 228: 'SPI_PERF_PC_ALLOC_ACCUM', - 229: 'SPI_PERF_GS_NGG_SE_HAS_BATON', - 230: 'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON', - 231: 'SPI_PERF_GS_NGG_SE_FORWARDED_BATON', - 232: 'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT', - 233: 'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT', - 234: 'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT', - 235: 'SPI_PERF_GS_NGG_PC_FULL', - 236: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 237: 'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY', - 238: 'SPI_PERF_GSC_VTX_BUSY', - 239: 'SPI_PERF_GSC_VTX_INPUT_STARVED', - 240: 'SPI_PERF_GSC_VTX_VSR_STALL', - 241: 'SPI_PERF_GSC_VTX_VSR_FULL', - 242: 'SPI_PERF_GSC_VTX_CAC_BUSY', - 243: 'SPI_PERF_ESC_VTX_BUSY', - 244: 'SPI_PERF_ESC_VTX_INPUT_STARVED', - 245: 'SPI_PERF_ESC_VTX_VSR_STALL', - 246: 'SPI_PERF_ESC_VTX_VSR_FULL', - 247: 'SPI_PERF_ESC_VTX_CAC_BUSY', - 248: 'SPI_PERF_SWC_PS_WR', - 249: 'SPI_PERF_SWC_VS_WR', - 250: 'SPI_PERF_SWC_GS_WR', - 251: 'SPI_PERF_SWC_HS_WR', - 252: 'SPI_PERF_SWC_CSG_WR', - 253: 'SPI_PERF_SWC_CSC_WR', - 254: 'SPI_PERF_VWC_PS_WR', - 255: 'SPI_PERF_VWC_VS_WR', - 256: 'SPI_PERF_VWC_GS_WR', - 257: 'SPI_PERF_VWC_HS_WR', - 258: 'SPI_PERF_VWC_CSG_WR', - 259: 'SPI_PERF_VWC_CSC_WR', - 260: 'SPI_PERF_ES_WINDOW_VALID', - 261: 'SPI_PERF_ES_BUSY', - 262: 'SPI_PERF_ES_CRAWLER_STALL', - 263: 'SPI_PERF_ES_FIRST_WAVE', - 264: 'SPI_PERF_ES_LAST_WAVE', - 265: 'SPI_PERF_ES_LSHS_DEALLOC', - 266: 'SPI_PERF_ES_EVENT_WAVE', - 267: 'SPI_PERF_ES_WAVE', - 268: 'SPI_PERF_ES_PERS_UPD_FULL0', - 269: 'SPI_PERF_ES_PERS_UPD_FULL1', - 270: 'SPI_PERF_ES_FIRST_SUBGRP', - 271: 'SPI_PERF_ES_LAST_SUBGRP', - 272: 'SPI_PERF_LS_WINDOW_VALID', - 273: 'SPI_PERF_LS_BUSY', - 274: 'SPI_PERF_LS_CRAWLER_STALL', - 275: 'SPI_PERF_LS_FIRST_WAVE', - 276: 'SPI_PERF_LS_LAST_WAVE', - 277: 'SPI_PERF_LS_OFFCHIP_LDS_STALL', - 278: 'SPI_PERF_LS_EVENT_WAVE', - 279: 'SPI_PERF_LS_WAVE', - 280: 'SPI_PERF_LS_PERS_UPD_FULL0', - 281: 'SPI_PERF_LS_PERS_UPD_FULL1', -} -SPI_PERF_VS_WINDOW_VALID = 0 -SPI_PERF_VS_BUSY = 1 -SPI_PERF_VS_FIRST_WAVE = 2 -SPI_PERF_VS_LAST_WAVE = 3 -SPI_PERF_VS_LSHS_DEALLOC = 4 -SPI_PERF_VS_PC_STALL = 5 -SPI_PERF_VS_POS0_STALL = 6 -SPI_PERF_VS_POS1_STALL = 7 -SPI_PERF_VS_CRAWLER_STALL = 8 -SPI_PERF_VS_EVENT_WAVE = 9 -SPI_PERF_VS_WAVE = 10 -SPI_PERF_VS_PERS_UPD_FULL0 = 11 -SPI_PERF_VS_PERS_UPD_FULL1 = 12 -SPI_PERF_VS_LATE_ALLOC_FULL = 13 -SPI_PERF_VS_FIRST_SUBGRP = 14 -SPI_PERF_VS_LAST_SUBGRP = 15 -SPI_PERF_VS_ALLOC_CNT = 16 -SPI_PERF_VS_PC_ALLOC_CNT = 17 -SPI_PERF_VS_LATE_ALLOC_ACCUM = 18 -SPI_PERF_GS_WINDOW_VALID = 19 -SPI_PERF_GS_BUSY = 20 -SPI_PERF_GS_CRAWLER_STALL = 21 -SPI_PERF_GS_EVENT_WAVE = 22 -SPI_PERF_GS_WAVE = 23 -SPI_PERF_GS_PERS_UPD_FULL0 = 24 -SPI_PERF_GS_PERS_UPD_FULL1 = 25 -SPI_PERF_GS_FIRST_SUBGRP = 26 -SPI_PERF_GS_LAST_SUBGRP = 27 -SPI_PERF_GS_HS_DEALLOC = 28 -SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 29 -SPI_PERF_GS_GRP_FIFO_FULL = 30 -SPI_PERF_HS_WINDOW_VALID = 31 -SPI_PERF_HS_BUSY = 32 -SPI_PERF_HS_CRAWLER_STALL = 33 -SPI_PERF_HS_FIRST_WAVE = 34 -SPI_PERF_HS_LAST_WAVE = 35 -SPI_PERF_HS_OFFCHIP_LDS_STALL = 36 -SPI_PERF_HS_EVENT_WAVE = 37 -SPI_PERF_HS_WAVE = 38 -SPI_PERF_HS_PERS_UPD_FULL0 = 39 -SPI_PERF_HS_PERS_UPD_FULL1 = 40 -SPI_PERF_CSG_WINDOW_VALID = 41 -SPI_PERF_CSG_BUSY = 42 -SPI_PERF_CSG_NUM_THREADGROUPS = 43 -SPI_PERF_CSG_CRAWLER_STALL = 44 -SPI_PERF_CSG_EVENT_WAVE = 45 -SPI_PERF_CSG_WAVE = 46 -SPI_PERF_CSN_WINDOW_VALID = 47 -SPI_PERF_CSN_BUSY = 48 -SPI_PERF_CSN_NUM_THREADGROUPS = 49 -SPI_PERF_CSN_CRAWLER_STALL = 50 -SPI_PERF_CSN_EVENT_WAVE = 51 -SPI_PERF_CSN_WAVE = 52 -SPI_PERF_PS0_WINDOW_VALID = 53 -SPI_PERF_PS1_WINDOW_VALID = 54 -SPI_PERF_PS2_WINDOW_VALID = 55 -SPI_PERF_PS3_WINDOW_VALID = 56 -SPI_PERF_PS0_BUSY = 57 -SPI_PERF_PS1_BUSY = 58 -SPI_PERF_PS2_BUSY = 59 -SPI_PERF_PS3_BUSY = 60 -SPI_PERF_PS0_ACTIVE = 61 -SPI_PERF_PS1_ACTIVE = 62 -SPI_PERF_PS2_ACTIVE = 63 -SPI_PERF_PS3_ACTIVE = 64 -SPI_PERF_PS0_DEALLOC_BIN0 = 65 -SPI_PERF_PS1_DEALLOC_BIN0 = 66 -SPI_PERF_PS2_DEALLOC_BIN0 = 67 -SPI_PERF_PS3_DEALLOC_BIN0 = 68 -SPI_PERF_PS0_FPOS_BIN1_STALL = 69 -SPI_PERF_PS1_FPOS_BIN1_STALL = 70 -SPI_PERF_PS2_FPOS_BIN1_STALL = 71 -SPI_PERF_PS3_FPOS_BIN1_STALL = 72 -SPI_PERF_PS0_EVENT_WAVE = 73 -SPI_PERF_PS1_EVENT_WAVE = 74 -SPI_PERF_PS2_EVENT_WAVE = 75 -SPI_PERF_PS3_EVENT_WAVE = 76 -SPI_PERF_PS0_WAVE = 77 -SPI_PERF_PS1_WAVE = 78 -SPI_PERF_PS2_WAVE = 79 -SPI_PERF_PS3_WAVE = 80 -SPI_PERF_PS0_OPT_WAVE = 81 -SPI_PERF_PS1_OPT_WAVE = 82 -SPI_PERF_PS2_OPT_WAVE = 83 -SPI_PERF_PS3_OPT_WAVE = 84 -SPI_PERF_PS0_PASS_BIN0 = 85 -SPI_PERF_PS1_PASS_BIN0 = 86 -SPI_PERF_PS2_PASS_BIN0 = 87 -SPI_PERF_PS3_PASS_BIN0 = 88 -SPI_PERF_PS0_PASS_BIN1 = 89 -SPI_PERF_PS1_PASS_BIN1 = 90 -SPI_PERF_PS2_PASS_BIN1 = 91 -SPI_PERF_PS3_PASS_BIN1 = 92 -SPI_PERF_PS0_FPOS_BIN2 = 93 -SPI_PERF_PS1_FPOS_BIN2 = 94 -SPI_PERF_PS2_FPOS_BIN2 = 95 -SPI_PERF_PS3_FPOS_BIN2 = 96 -SPI_PERF_PS0_PRIM_BIN0 = 97 -SPI_PERF_PS1_PRIM_BIN0 = 98 -SPI_PERF_PS2_PRIM_BIN0 = 99 -SPI_PERF_PS3_PRIM_BIN0 = 100 -SPI_PERF_PS0_PRIM_BIN1 = 101 -SPI_PERF_PS1_PRIM_BIN1 = 102 -SPI_PERF_PS2_PRIM_BIN1 = 103 -SPI_PERF_PS3_PRIM_BIN1 = 104 -SPI_PERF_PS0_CNF_BIN2 = 105 -SPI_PERF_PS1_CNF_BIN2 = 106 -SPI_PERF_PS2_CNF_BIN2 = 107 -SPI_PERF_PS3_CNF_BIN2 = 108 -SPI_PERF_PS0_CNF_BIN3 = 109 -SPI_PERF_PS1_CNF_BIN3 = 110 -SPI_PERF_PS2_CNF_BIN3 = 111 -SPI_PERF_PS3_CNF_BIN3 = 112 -SPI_PERF_PS0_CRAWLER_STALL = 113 -SPI_PERF_PS1_CRAWLER_STALL = 114 -SPI_PERF_PS2_CRAWLER_STALL = 115 -SPI_PERF_PS3_CRAWLER_STALL = 116 -SPI_PERF_PS0_LDS_RES_FULL = 117 -SPI_PERF_PS1_LDS_RES_FULL = 118 -SPI_PERF_PS2_LDS_RES_FULL = 119 -SPI_PERF_PS3_LDS_RES_FULL = 120 -SPI_PERF_PS_PERS_UPD_FULL0 = 121 -SPI_PERF_PS_PERS_UPD_FULL1 = 122 -SPI_PERF_PS0_POPS_WAVE_SENT = 123 -SPI_PERF_PS1_POPS_WAVE_SENT = 124 -SPI_PERF_PS2_POPS_WAVE_SENT = 125 -SPI_PERF_PS3_POPS_WAVE_SENT = 126 -SPI_PERF_PS0_POPS_WAVE_EXIT = 127 -SPI_PERF_PS1_POPS_WAVE_EXIT = 128 -SPI_PERF_PS2_POPS_WAVE_EXIT = 129 -SPI_PERF_PS3_POPS_WAVE_EXIT = 130 -SPI_PERF_LDS0_PC_VALID = 131 -SPI_PERF_LDS1_PC_VALID = 132 -SPI_PERF_RA_PIPE_REQ_BIN2 = 133 -SPI_PERF_RA_TASK_REQ_BIN3 = 134 -SPI_PERF_RA_WR_CTL_FULL = 135 -SPI_PERF_RA_REQ_NO_ALLOC = 136 -SPI_PERF_RA_REQ_NO_ALLOC_PS = 137 -SPI_PERF_RA_REQ_NO_ALLOC_VS = 138 -SPI_PERF_RA_REQ_NO_ALLOC_GS = 139 -SPI_PERF_RA_REQ_NO_ALLOC_HS = 140 -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 141 -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 142 -SPI_PERF_RA_RES_STALL_PS = 143 -SPI_PERF_RA_RES_STALL_VS = 144 -SPI_PERF_RA_RES_STALL_GS = 145 -SPI_PERF_RA_RES_STALL_HS = 146 -SPI_PERF_RA_RES_STALL_CSG = 147 -SPI_PERF_RA_RES_STALL_CSN = 148 -SPI_PERF_RA_TMP_STALL_PS = 149 -SPI_PERF_RA_TMP_STALL_VS = 150 -SPI_PERF_RA_TMP_STALL_GS = 151 -SPI_PERF_RA_TMP_STALL_HS = 152 -SPI_PERF_RA_TMP_STALL_CSG = 153 -SPI_PERF_RA_TMP_STALL_CSN = 154 -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 155 -SPI_PERF_RA_WAVE_SIMD_FULL_VS = 156 -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 157 -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 158 -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 159 -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 160 -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 161 -SPI_PERF_RA_VGPR_SIMD_FULL_VS = 162 -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 163 -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 164 -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 165 -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 166 -SPI_PERF_RA_SGPR_SIMD_FULL_PS = 167 -SPI_PERF_RA_SGPR_SIMD_FULL_VS = 168 -SPI_PERF_RA_SGPR_SIMD_FULL_GS = 169 -SPI_PERF_RA_SGPR_SIMD_FULL_HS = 170 -SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 171 -SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 172 -SPI_PERF_RA_LDS_CU_FULL_PS = 173 -SPI_PERF_RA_LDS_CU_FULL_LS = 174 -SPI_PERF_RA_LDS_CU_FULL_ES = 175 -SPI_PERF_RA_LDS_CU_FULL_CSG = 176 -SPI_PERF_RA_LDS_CU_FULL_CSN = 177 -SPI_PERF_RA_BAR_CU_FULL_HS = 178 -SPI_PERF_RA_BAR_CU_FULL_CSG = 179 -SPI_PERF_RA_BAR_CU_FULL_CSN = 180 -SPI_PERF_RA_BULKY_CU_FULL_CSG = 181 -SPI_PERF_RA_BULKY_CU_FULL_CSN = 182 -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 183 -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 184 -SPI_PERF_RA_WVLIM_STALL_PS = 185 -SPI_PERF_RA_WVLIM_STALL_VS = 186 -SPI_PERF_RA_WVLIM_STALL_GS = 187 -SPI_PERF_RA_WVLIM_STALL_HS = 188 -SPI_PERF_RA_WVLIM_STALL_CSG = 189 -SPI_PERF_RA_WVLIM_STALL_CSN = 190 -SPI_PERF_RA_VS_LOCK = 191 -SPI_PERF_RA_GS_LOCK = 192 -SPI_PERF_RA_HS_LOCK = 193 -SPI_PERF_RA_CSG_LOCK = 194 -SPI_PERF_RA_CSN_LOCK = 195 -SPI_PERF_RA_RSV_UPD = 196 -SPI_PERF_EXP_ARB_COL_CNT = 197 -SPI_PERF_EXP_ARB_PAR_CNT = 198 -SPI_PERF_EXP_ARB_POS_CNT = 199 -SPI_PERF_EXP_ARB_GDS_CNT = 200 -SPI_PERF_NUM_PS_COL_R0_EXPORTS = 201 -SPI_PERF_NUM_PS_COL_R1_EXPORTS = 202 -SPI_PERF_NUM_VS_POS_R0_EXPORTS = 203 -SPI_PERF_NUM_VS_POS_R1_EXPORTS = 204 -SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 205 -SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 206 -SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 207 -SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 208 -SPI_PERF_NUM_EXPGRANT_EXPORTS = 209 -SPI_PERF_CLKGATE_BUSY_STALL = 210 -SPI_PERF_CLKGATE_ACTIVE_STALL = 211 -SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 212 -SPI_PERF_CLKGATE_CGTT_DYN_ON = 213 -SPI_PERF_CLKGATE_CGTT_REG_ON = 214 -SPI_PERF_PIX_ALLOC_PEND_CNT = 215 -SPI_PERF_PIX_ALLOC_SCB0_STALL = 216 -SPI_PERF_PIX_ALLOC_SCB1_STALL = 217 -SPI_PERF_PIX_ALLOC_SCB2_STALL = 218 -SPI_PERF_PIX_ALLOC_SCB3_STALL = 219 -SPI_PERF_PIX_ALLOC_DB0_STALL = 220 -SPI_PERF_PIX_ALLOC_DB1_STALL = 221 -SPI_PERF_PIX_ALLOC_DB2_STALL = 222 -SPI_PERF_PIX_ALLOC_DB3_STALL = 223 -SPI_PERF_PIX_ALLOC_DB4_STALL = 224 -SPI_PERF_PIX_ALLOC_DB5_STALL = 225 -SPI_PERF_PIX_ALLOC_DB6_STALL = 226 -SPI_PERF_PIX_ALLOC_DB7_STALL = 227 -SPI_PERF_PC_ALLOC_ACCUM = 228 -SPI_PERF_GS_NGG_SE_HAS_BATON = 229 -SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 230 -SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 231 -SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 232 -SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 233 -SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 234 -SPI_PERF_GS_NGG_PC_FULL = 235 -SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 236 -SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 237 -SPI_PERF_GSC_VTX_BUSY = 238 -SPI_PERF_GSC_VTX_INPUT_STARVED = 239 -SPI_PERF_GSC_VTX_VSR_STALL = 240 -SPI_PERF_GSC_VTX_VSR_FULL = 241 -SPI_PERF_GSC_VTX_CAC_BUSY = 242 -SPI_PERF_ESC_VTX_BUSY = 243 -SPI_PERF_ESC_VTX_INPUT_STARVED = 244 -SPI_PERF_ESC_VTX_VSR_STALL = 245 -SPI_PERF_ESC_VTX_VSR_FULL = 246 -SPI_PERF_ESC_VTX_CAC_BUSY = 247 -SPI_PERF_SWC_PS_WR = 248 -SPI_PERF_SWC_VS_WR = 249 -SPI_PERF_SWC_GS_WR = 250 -SPI_PERF_SWC_HS_WR = 251 -SPI_PERF_SWC_CSG_WR = 252 -SPI_PERF_SWC_CSC_WR = 253 -SPI_PERF_VWC_PS_WR = 254 -SPI_PERF_VWC_VS_WR = 255 -SPI_PERF_VWC_GS_WR = 256 -SPI_PERF_VWC_HS_WR = 257 -SPI_PERF_VWC_CSG_WR = 258 -SPI_PERF_VWC_CSC_WR = 259 -SPI_PERF_ES_WINDOW_VALID = 260 -SPI_PERF_ES_BUSY = 261 -SPI_PERF_ES_CRAWLER_STALL = 262 -SPI_PERF_ES_FIRST_WAVE = 263 -SPI_PERF_ES_LAST_WAVE = 264 -SPI_PERF_ES_LSHS_DEALLOC = 265 -SPI_PERF_ES_EVENT_WAVE = 266 -SPI_PERF_ES_WAVE = 267 -SPI_PERF_ES_PERS_UPD_FULL0 = 268 -SPI_PERF_ES_PERS_UPD_FULL1 = 269 -SPI_PERF_ES_FIRST_SUBGRP = 270 -SPI_PERF_ES_LAST_SUBGRP = 271 -SPI_PERF_LS_WINDOW_VALID = 272 -SPI_PERF_LS_BUSY = 273 -SPI_PERF_LS_CRAWLER_STALL = 274 -SPI_PERF_LS_FIRST_WAVE = 275 -SPI_PERF_LS_LAST_WAVE = 276 -SPI_PERF_LS_OFFCHIP_LDS_STALL = 277 -SPI_PERF_LS_EVENT_WAVE = 278 -SPI_PERF_LS_WAVE = 279 -SPI_PERF_LS_PERS_UPD_FULL0 = 280 -SPI_PERF_LS_PERS_UPD_FULL1 = 281 -SPI_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_FORMAT' -SPI_SHADER_FORMAT__enumvalues = { - 0: 'SPI_SHADER_NONE', - 1: 'SPI_SHADER_1COMP', - 2: 'SPI_SHADER_2COMP', - 3: 'SPI_SHADER_4COMPRESS', - 4: 'SPI_SHADER_4COMP', -} -SPI_SHADER_NONE = 0 -SPI_SHADER_1COMP = 1 -SPI_SHADER_2COMP = 2 -SPI_SHADER_4COMPRESS = 3 -SPI_SHADER_4COMP = 4 -SPI_SHADER_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_EX_FORMAT' -SPI_SHADER_EX_FORMAT__enumvalues = { - 0: 'SPI_SHADER_ZERO', - 1: 'SPI_SHADER_32_R', - 2: 'SPI_SHADER_32_GR', - 3: 'SPI_SHADER_32_AR', - 4: 'SPI_SHADER_FP16_ABGR', - 5: 'SPI_SHADER_UNORM16_ABGR', - 6: 'SPI_SHADER_SNORM16_ABGR', - 7: 'SPI_SHADER_UINT16_ABGR', - 8: 'SPI_SHADER_SINT16_ABGR', - 9: 'SPI_SHADER_32_ABGR', -} -SPI_SHADER_ZERO = 0 -SPI_SHADER_32_R = 1 -SPI_SHADER_32_GR = 2 -SPI_SHADER_32_AR = 3 -SPI_SHADER_FP16_ABGR = 4 -SPI_SHADER_UNORM16_ABGR = 5 -SPI_SHADER_SNORM16_ABGR = 6 -SPI_SHADER_UINT16_ABGR = 7 -SPI_SHADER_SINT16_ABGR = 8 -SPI_SHADER_32_ABGR = 9 -SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_SM_MODE' -CLKGATE_SM_MODE__enumvalues = { - 0: 'ON_SEQ', - 1: 'OFF_SEQ', - 2: 'PROG_SEQ', - 3: 'READ_SEQ', - 4: 'SM_MODE_RESERVED', -} -ON_SEQ = 0 -OFF_SEQ = 1 -PROG_SEQ = 2 -READ_SEQ = 3 -SM_MODE_RESERVED = 4 -CLKGATE_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_BASE_MODE' -CLKGATE_BASE_MODE__enumvalues = { - 0: 'MULT_8', - 1: 'MULT_16', -} -MULT_8 = 0 -MULT_16 = 1 -CLKGATE_BASE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_LB_WAVES_SELECT' -SPI_LB_WAVES_SELECT__enumvalues = { - 0: 'HS_GS', - 1: 'VS_PS', - 2: 'CS_NA', - 3: 'SPI_LB_WAVES_RSVD', -} -HS_GS = 0 -VS_PS = 1 -CS_NA = 2 -SPI_LB_WAVES_RSVD = 3 -SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_CLAMP' -SQ_TEX_CLAMP__enumvalues = { - 0: 'SQ_TEX_WRAP', - 1: 'SQ_TEX_MIRROR', - 2: 'SQ_TEX_CLAMP_LAST_TEXEL', - 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 4: 'SQ_TEX_CLAMP_HALF_BORDER', - 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', - 6: 'SQ_TEX_CLAMP_BORDER', - 7: 'SQ_TEX_MIRROR_ONCE_BORDER', -} -SQ_TEX_WRAP = 0 -SQ_TEX_MIRROR = 1 -SQ_TEX_CLAMP_LAST_TEXEL = 2 -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 -SQ_TEX_CLAMP_HALF_BORDER = 4 -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 -SQ_TEX_CLAMP_BORDER = 6 -SQ_TEX_MIRROR_ONCE_BORDER = 7 -SQ_TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_XY_FILTER' -SQ_TEX_XY_FILTER__enumvalues = { - 0: 'SQ_TEX_XY_FILTER_POINT', - 1: 'SQ_TEX_XY_FILTER_BILINEAR', - 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', - 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', -} -SQ_TEX_XY_FILTER_POINT = 0 -SQ_TEX_XY_FILTER_BILINEAR = 1 -SQ_TEX_XY_FILTER_ANISO_POINT = 2 -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 -SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_Z_FILTER' -SQ_TEX_Z_FILTER__enumvalues = { - 0: 'SQ_TEX_Z_FILTER_NONE', - 1: 'SQ_TEX_Z_FILTER_POINT', - 2: 'SQ_TEX_Z_FILTER_LINEAR', -} -SQ_TEX_Z_FILTER_NONE = 0 -SQ_TEX_Z_FILTER_POINT = 1 -SQ_TEX_Z_FILTER_LINEAR = 2 -SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_MIP_FILTER' -SQ_TEX_MIP_FILTER__enumvalues = { - 0: 'SQ_TEX_MIP_FILTER_NONE', - 1: 'SQ_TEX_MIP_FILTER_POINT', - 2: 'SQ_TEX_MIP_FILTER_LINEAR', - 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', -} -SQ_TEX_MIP_FILTER_NONE = 0 -SQ_TEX_MIP_FILTER_POINT = 1 -SQ_TEX_MIP_FILTER_LINEAR = 2 -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 -SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_ANISO_RATIO' -SQ_TEX_ANISO_RATIO__enumvalues = { - 0: 'SQ_TEX_ANISO_RATIO_1', - 1: 'SQ_TEX_ANISO_RATIO_2', - 2: 'SQ_TEX_ANISO_RATIO_4', - 3: 'SQ_TEX_ANISO_RATIO_8', - 4: 'SQ_TEX_ANISO_RATIO_16', -} -SQ_TEX_ANISO_RATIO_1 = 0 -SQ_TEX_ANISO_RATIO_2 = 1 -SQ_TEX_ANISO_RATIO_4 = 2 -SQ_TEX_ANISO_RATIO_8 = 3 -SQ_TEX_ANISO_RATIO_16 = 4 -SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_DEPTH_COMPARE' -SQ_TEX_DEPTH_COMPARE__enumvalues = { - 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', - 1: 'SQ_TEX_DEPTH_COMPARE_LESS', - 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', - 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', - 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', - 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', - 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', -} -SQ_TEX_DEPTH_COMPARE_NEVER = 0 -SQ_TEX_DEPTH_COMPARE_LESS = 1 -SQ_TEX_DEPTH_COMPARE_EQUAL = 2 -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 -SQ_TEX_DEPTH_COMPARE_GREATER = 4 -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 -SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 -SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_BORDER_COLOR' -SQ_TEX_BORDER_COLOR__enumvalues = { - 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 3: 'SQ_TEX_BORDER_COLOR_REGISTER', -} -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 -SQ_TEX_BORDER_COLOR_REGISTER = 3 -SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_BUF_TYPE' -SQ_RSRC_BUF_TYPE__enumvalues = { - 0: 'SQ_RSRC_BUF', - 1: 'SQ_RSRC_BUF_RSVD_1', - 2: 'SQ_RSRC_BUF_RSVD_2', - 3: 'SQ_RSRC_BUF_RSVD_3', -} -SQ_RSRC_BUF = 0 -SQ_RSRC_BUF_RSVD_1 = 1 -SQ_RSRC_BUF_RSVD_2 = 2 -SQ_RSRC_BUF_RSVD_3 = 3 -SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_IMG_TYPE' -SQ_RSRC_IMG_TYPE__enumvalues = { - 0: 'SQ_RSRC_IMG_RSVD_0', - 1: 'SQ_RSRC_IMG_RSVD_1', - 2: 'SQ_RSRC_IMG_RSVD_2', - 3: 'SQ_RSRC_IMG_RSVD_3', - 4: 'SQ_RSRC_IMG_RSVD_4', - 5: 'SQ_RSRC_IMG_RSVD_5', - 6: 'SQ_RSRC_IMG_RSVD_6', - 7: 'SQ_RSRC_IMG_RSVD_7', - 8: 'SQ_RSRC_IMG_1D', - 9: 'SQ_RSRC_IMG_2D', - 10: 'SQ_RSRC_IMG_3D', - 11: 'SQ_RSRC_IMG_CUBE', - 12: 'SQ_RSRC_IMG_1D_ARRAY', - 13: 'SQ_RSRC_IMG_2D_ARRAY', - 14: 'SQ_RSRC_IMG_2D_MSAA', - 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', -} -SQ_RSRC_IMG_RSVD_0 = 0 -SQ_RSRC_IMG_RSVD_1 = 1 -SQ_RSRC_IMG_RSVD_2 = 2 -SQ_RSRC_IMG_RSVD_3 = 3 -SQ_RSRC_IMG_RSVD_4 = 4 -SQ_RSRC_IMG_RSVD_5 = 5 -SQ_RSRC_IMG_RSVD_6 = 6 -SQ_RSRC_IMG_RSVD_7 = 7 -SQ_RSRC_IMG_1D = 8 -SQ_RSRC_IMG_2D = 9 -SQ_RSRC_IMG_3D = 10 -SQ_RSRC_IMG_CUBE = 11 -SQ_RSRC_IMG_1D_ARRAY = 12 -SQ_RSRC_IMG_2D_ARRAY = 13 -SQ_RSRC_IMG_2D_MSAA = 14 -SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 -SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_FLAT_TYPE' -SQ_RSRC_FLAT_TYPE__enumvalues = { - 0: 'SQ_RSRC_FLAT_RSVD_0', - 1: 'SQ_RSRC_FLAT', - 2: 'SQ_RSRC_FLAT_RSVD_2', - 3: 'SQ_RSRC_FLAT_RSVD_3', -} -SQ_RSRC_FLAT_RSVD_0 = 0 -SQ_RSRC_FLAT = 1 -SQ_RSRC_FLAT_RSVD_2 = 2 -SQ_RSRC_FLAT_RSVD_3 = 3 -SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IMG_FILTER_TYPE' -SQ_IMG_FILTER_TYPE__enumvalues = { - 0: 'SQ_IMG_FILTER_MODE_BLEND', - 1: 'SQ_IMG_FILTER_MODE_MIN', - 2: 'SQ_IMG_FILTER_MODE_MAX', -} -SQ_IMG_FILTER_MODE_BLEND = 0 -SQ_IMG_FILTER_MODE_MIN = 1 -SQ_IMG_FILTER_MODE_MAX = 2 -SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_SEL_XYZW01' -SQ_SEL_XYZW01__enumvalues = { - 0: 'SQ_SEL_0', - 1: 'SQ_SEL_1', - 2: 'SQ_SEL_N_BC_1', - 3: 'SQ_SEL_RESERVED_1', - 4: 'SQ_SEL_X', - 5: 'SQ_SEL_Y', - 6: 'SQ_SEL_Z', - 7: 'SQ_SEL_W', -} -SQ_SEL_0 = 0 -SQ_SEL_1 = 1 -SQ_SEL_N_BC_1 = 2 -SQ_SEL_RESERVED_1 = 3 -SQ_SEL_X = 4 -SQ_SEL_Y = 5 -SQ_SEL_Z = 6 -SQ_SEL_W = 7 -SQ_SEL_XYZW01 = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_OOB_SELECT' -SQ_OOB_SELECT__enumvalues = { - 0: 'SQ_OOB_INDEX_AND_OFFSET', - 1: 'SQ_OOB_INDEX_ONLY', - 2: 'SQ_OOB_NUM_RECORDS_0', - 3: 'SQ_OOB_COMPLETE', -} -SQ_OOB_INDEX_AND_OFFSET = 0 -SQ_OOB_INDEX_ONLY = 1 -SQ_OOB_NUM_RECORDS_0 = 2 -SQ_OOB_COMPLETE = 3 -SQ_OOB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_TYPE' -SQ_WAVE_TYPE__enumvalues = { - 0: 'SQ_WAVE_TYPE_PS', - 1: 'SQ_WAVE_TYPE_VS', - 2: 'SQ_WAVE_TYPE_GS', - 3: 'SQ_WAVE_TYPE_ES', - 4: 'SQ_WAVE_TYPE_HS', - 5: 'SQ_WAVE_TYPE_LS', - 6: 'SQ_WAVE_TYPE_CS', - 7: 'SQ_WAVE_TYPE_PS1', - 8: 'SQ_WAVE_TYPE_PS2', - 9: 'SQ_WAVE_TYPE_PS3', -} -SQ_WAVE_TYPE_PS = 0 -SQ_WAVE_TYPE_VS = 1 -SQ_WAVE_TYPE_GS = 2 -SQ_WAVE_TYPE_ES = 3 -SQ_WAVE_TYPE_HS = 4 -SQ_WAVE_TYPE_LS = 5 -SQ_WAVE_TYPE_CS = 6 -SQ_WAVE_TYPE_PS1 = 7 -SQ_WAVE_TYPE_PS2 = 8 -SQ_WAVE_TYPE_PS3 = 9 -SQ_WAVE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_PERF_SEL' -SQ_PERF_SEL__enumvalues = { - 0: 'SQ_PERF_SEL_NONE', - 1: 'SQ_PERF_SEL_ACCUM_PREV', - 2: 'SQ_PERF_SEL_CYCLES', - 3: 'SQ_PERF_SEL_BUSY_CYCLES', - 4: 'SQ_PERF_SEL_WAVES', - 5: 'SQ_PERF_SEL_WAVES_32', - 6: 'SQ_PERF_SEL_WAVES_64', - 7: 'SQ_PERF_SEL_LEVEL_WAVES', - 8: 'SQ_PERF_SEL_ITEMS', - 9: 'SQ_PERF_SEL_WAVE32_ITEMS', - 10: 'SQ_PERF_SEL_WAVE64_ITEMS', - 11: 'SQ_PERF_SEL_QUADS', - 12: 'SQ_PERF_SEL_EVENTS', - 13: 'SQ_PERF_SEL_WAVES_EQ_64', - 14: 'SQ_PERF_SEL_WAVES_LT_64', - 15: 'SQ_PERF_SEL_WAVES_LT_48', - 16: 'SQ_PERF_SEL_WAVES_LT_32', - 17: 'SQ_PERF_SEL_WAVES_LT_16', - 18: 'SQ_PERF_SEL_WAVES_RESTORED', - 19: 'SQ_PERF_SEL_WAVES_SAVED', - 20: 'SQ_PERF_SEL_MSG', - 21: 'SQ_PERF_SEL_MSG_GSCNT', - 22: 'SQ_PERF_SEL_MSG_INTERRUPT', - 23: 'SQ_PERF_SEL_Reserved_1', - 24: 'SQ_PERF_SEL_Reserved_2', - 25: 'SQ_PERF_SEL_Reserved_3', - 26: 'SQ_PERF_SEL_WAVE_CYCLES', - 27: 'SQ_PERF_SEL_WAVE_READY', - 28: 'SQ_PERF_SEL_WAIT_INST_ANY', - 29: 'SQ_PERF_SEL_WAIT_INST_VALU', - 30: 'SQ_PERF_SEL_WAIT_INST_SCA', - 31: 'SQ_PERF_SEL_WAIT_INST_LDS', - 32: 'SQ_PERF_SEL_WAIT_INST_TEX', - 33: 'SQ_PERF_SEL_WAIT_INST_FLAT', - 34: 'SQ_PERF_SEL_WAIT_INST_VMEM', - 35: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', - 36: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', - 37: 'SQ_PERF_SEL_WAIT_ANY', - 38: 'SQ_PERF_SEL_WAIT_CNT_ANY', - 39: 'SQ_PERF_SEL_WAIT_CNT_VMVS', - 40: 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 41: 'SQ_PERF_SEL_WAIT_CNT_EXP', - 42: 'SQ_PERF_SEL_WAIT_TTRACE', - 43: 'SQ_PERF_SEL_WAIT_IFETCH', - 44: 'SQ_PERF_SEL_WAIT_BARRIER', - 45: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 46: 'SQ_PERF_SEL_WAIT_SLEEP', - 47: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', - 48: 'SQ_PERF_SEL_WAIT_OTHER', - 49: 'SQ_PERF_SEL_INSTS_ALL', - 50: 'SQ_PERF_SEL_INSTS_BRANCH', - 51: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 53: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', - 54: 'SQ_PERF_SEL_INSTS_EXP_GDS', - 55: 'SQ_PERF_SEL_INSTS_GDS', - 56: 'SQ_PERF_SEL_INSTS_EXP', - 57: 'SQ_PERF_SEL_INSTS_FLAT', - 58: 'SQ_PERF_SEL_Reserved_4', - 59: 'SQ_PERF_SEL_INSTS_LDS', - 60: 'SQ_PERF_SEL_INSTS_SALU', - 61: 'SQ_PERF_SEL_INSTS_SMEM', - 62: 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 63: 'SQ_PERF_SEL_INSTS_SENDMSG', - 64: 'SQ_PERF_SEL_INSTS_VALU', - 65: 'SQ_PERF_SEL_Reserved_17', - 66: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 67: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 68: 'SQ_PERF_SEL_INSTS_TEX', - 69: 'SQ_PERF_SEL_INSTS_TEX_LOAD', - 70: 'SQ_PERF_SEL_INSTS_TEX_STORE', - 71: 'SQ_PERF_SEL_INSTS_WAVE32', - 72: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', - 73: 'SQ_PERF_SEL_Reserved_5', - 74: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 76: 'SQ_PERF_SEL_Reserved_16', - 77: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 78: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 80: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 81: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 82: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 83: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 84: 'SQ_PERF_SEL_WAVE32_INSTS', - 85: 'SQ_PERF_SEL_WAVE64_INSTS', - 86: 'SQ_PERF_SEL_Reserved_18', - 87: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 88: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 89: 'SQ_PERF_SEL_INSTS_TEX_REPLAY', - 90: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', - 91: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', - 92: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', - 93: 'SQ_PERF_SEL_XNACK_ALL', - 94: 'SQ_PERF_SEL_XNACK_FIRST', - 95: 'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD', - 96: 'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP', - 97: 'SQ_PERF_SEL_INST_LEVEL_EXP', - 98: 'SQ_PERF_SEL_INST_LEVEL_GDS', - 99: 'SQ_PERF_SEL_INST_LEVEL_LDS', - 100: 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 101: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 102: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', - 103: 'SQ_PERF_SEL_IFETCH_REQS', - 104: 'SQ_PERF_SEL_IFETCH_LEVEL', - 105: 'SQ_PERF_SEL_IFETCH_XNACK', - 106: 'SQ_PERF_SEL_Reserved_6', - 107: 'SQ_PERF_SEL_Reserved_7', - 108: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 109: 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 110: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 111: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 112: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 113: 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 114: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 115: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 116: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 117: 'SQ_PERF_SEL_INST_CYCLES_VALU', - 118: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 119: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 120: 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 121: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 122: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 123: 'SQ_PERF_SEL_INST_CYCLES_LDS', - 124: 'SQ_PERF_SEL_INST_CYCLES_TEX', - 125: 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 126: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', - 127: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 128: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 129: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 130: 'SQ_PERF_SEL_Reserved_8', - 131: 'SQ_PERF_SEL_Reserved_9', - 132: 'SQ_PERF_SEL_Reserved_10', - 133: 'SQ_PERF_SEL_Reserved_11', - 134: 'SQ_PERF_SEL_Reserved_12', - 135: 'SQ_PERF_SEL_Reserved_13', - 136: 'SQ_PERF_SEL_Reserved_14', - 137: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 138: 'SQ_PERF_SEL_VMEM_BUS_STALL', - 139: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 140: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 141: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 142: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 143: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 144: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 145: 'SQ_PERF_SEL_Reserved_15', - 146: 'SQ_PERF_SEL_SALU_PIPE_STALL', - 147: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 148: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL', - 149: 'SQ_PERF_SEL_MSG_BUS_BUSY', - 150: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', - 151: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', - 152: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 153: 'SQ_PERF_SEL_EXP_BUS0_BUSY', - 154: 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 155: 'SQ_PERF_SEL_INST_CACHE_REQS', - 156: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', - 157: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU', - 158: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU', - 159: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM', - 160: 'SQ_PERF_SEL_USER0', - 161: 'SQ_PERF_SEL_USER1', - 162: 'SQ_PERF_SEL_USER2', - 163: 'SQ_PERF_SEL_USER3', - 164: 'SQ_PERF_SEL_USER4', - 165: 'SQ_PERF_SEL_USER5', - 166: 'SQ_PERF_SEL_USER6', - 167: 'SQ_PERF_SEL_USER7', - 168: 'SQ_PERF_SEL_USER8', - 169: 'SQ_PERF_SEL_USER9', - 170: 'SQ_PERF_SEL_USER10', - 171: 'SQ_PERF_SEL_USER11', - 172: 'SQ_PERF_SEL_USER12', - 173: 'SQ_PERF_SEL_USER13', - 174: 'SQ_PERF_SEL_USER14', - 175: 'SQ_PERF_SEL_USER15', - 176: 'SQ_PERF_SEL_USER_LEVEL0', - 177: 'SQ_PERF_SEL_USER_LEVEL1', - 178: 'SQ_PERF_SEL_USER_LEVEL2', - 179: 'SQ_PERF_SEL_USER_LEVEL3', - 180: 'SQ_PERF_SEL_USER_LEVEL4', - 181: 'SQ_PERF_SEL_USER_LEVEL5', - 182: 'SQ_PERF_SEL_USER_LEVEL6', - 183: 'SQ_PERF_SEL_USER_LEVEL7', - 184: 'SQ_PERF_SEL_USER_LEVEL8', - 185: 'SQ_PERF_SEL_USER_LEVEL9', - 186: 'SQ_PERF_SEL_USER_LEVEL10', - 187: 'SQ_PERF_SEL_USER_LEVEL11', - 188: 'SQ_PERF_SEL_USER_LEVEL12', - 189: 'SQ_PERF_SEL_USER_LEVEL13', - 190: 'SQ_PERF_SEL_USER_LEVEL14', - 191: 'SQ_PERF_SEL_USER_LEVEL15', - 192: 'SQ_PERF_SEL_VALU_RETURN_SDST', - 193: 'SQ_PERF_SEL_VMEM_SECOND_TRY_USED', - 194: 'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL', - 195: 'SQ_PERF_SEL_DUMMY_END', - 255: 'SQ_PERF_SEL_DUMMY_LAST', - 256: 'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS', - 257: 'SQG_PERF_SEL_UTCL0_PERMISSION_MISS', - 258: 'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT', - 259: 'SQG_PERF_SEL_UTCL0_REQUEST', - 260: 'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 261: 'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 262: 'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 263: 'SQG_PERF_SEL_UTCL0_LFIFO_FULL', - 264: 'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 265: 'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 266: 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL', - 267: 'SQG_PERF_SEL_UTCL0_UTCL1_REQ', - 268: 'SQG_PERF_SEL_TLB_SHOOTDOWN', - 269: 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES', - 270: 'SQG_PERF_SEL_TTRACE_REQS', - 271: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 272: 'SQG_PERF_SEL_TTRACE_STALL', - 273: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', - 274: 'SQG_PERF_SEL_DUMMY_LAST', - 275: 'SQC_PERF_SEL_POWER_VALU', - 276: 'SQC_PERF_SEL_POWER_VALU0', - 277: 'SQC_PERF_SEL_POWER_VALU1', - 278: 'SQC_PERF_SEL_POWER_VALU2', - 279: 'SQC_PERF_SEL_POWER_GPR_RD', - 280: 'SQC_PERF_SEL_POWER_GPR_WR', - 281: 'SQC_PERF_SEL_POWER_LDS_BUSY', - 282: 'SQC_PERF_SEL_POWER_ALU_BUSY', - 283: 'SQC_PERF_SEL_POWER_TEX_BUSY', - 284: 'SQC_PERF_SEL_PT_POWER_STALL', - 285: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 286: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 287: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', - 288: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 289: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 290: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 291: 'SQC_PERF_SEL_LDS_DATA_FIFO_FULL', - 292: 'SQC_PERF_SEL_LDS_CMD_FIFO_FULL', - 293: 'SQC_PERF_SEL_LDS_ADDR_STALL', - 294: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', - 295: 'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL', - 296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', - 300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 301: 'SQC_PERF_SEL_ICACHE_REQ', - 302: 'SQC_PERF_SEL_ICACHE_HITS', - 303: 'SQC_PERF_SEL_ICACHE_MISSES', - 304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 305: 'SQC_PERF_SEL_ICACHE_INVAL_INST', - 306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', - 310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', - 313: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 314: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', - 315: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', - 316: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 317: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', - 318: 'SQC_PERF_SEL_TC_REQ', - 319: 'SQC_PERF_SEL_TC_INST_REQ', - 320: 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 321: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', - 322: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', - 323: 'SQC_PERF_SEL_TC_STALL', - 324: 'SQC_PERF_SEL_TC_STARVE', - 325: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 326: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 327: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 328: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', - 329: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 330: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', - 331: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 332: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 333: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', - 334: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 335: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 336: 'SQC_PERF_SEL_DCACHE_REQ', - 337: 'SQC_PERF_SEL_DCACHE_HITS', - 338: 'SQC_PERF_SEL_DCACHE_MISSES', - 339: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 340: 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 341: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 342: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 343: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', - 344: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', - 345: 'SQC_PERF_SEL_DCACHE_ATOMIC', - 346: 'SQC_PERF_SEL_DCACHE_WB_INST', - 347: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', - 348: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 349: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 350: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 351: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO', - 352: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 353: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 354: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', - 355: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', - 356: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', - 357: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', - 358: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', - 359: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', - 360: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 361: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 362: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', - 363: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 364: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 365: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 366: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 367: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 368: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 369: 'SQC_PERF_SEL_DCACHE_REQ_TIME', - 370: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', - 371: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', - 372: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', - 373: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 374: 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 375: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 376: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', - 377: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS', - 378: 'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS', - 379: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT', - 380: 'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST', - 381: 'SQC_PERF_SEL_ICACHE_UTCL0_XNACK', - 382: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX', - 383: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT', - 384: 'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL', - 385: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES', - 386: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 387: 'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT', - 388: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL', - 389: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS', - 390: 'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS', - 391: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT', - 392: 'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST', - 393: 'SQC_PERF_SEL_DCACHE_UTCL0_XNACK', - 394: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX', - 395: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT', - 396: 'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL', - 397: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES', - 398: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 399: 'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT', - 400: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL', - 401: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS', - 402: 'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL', - 403: 'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL', - 404: 'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ', - 405: 'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL', - 406: 'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ', - 407: 'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL', - 408: 'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ', - 409: 'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL', - 410: 'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ', - 411: 'SQC_PERF_SEL_ICACHE_GCR', - 412: 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 413: 'SQC_PERF_SEL_DCACHE_GCR', - 414: 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 415: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', - 416: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', - 417: 'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK', - 418: 'SQC_PERF_SEL_DUMMY_LAST', - 448: 'SP_PERF_SEL_DUMMY_BEGIN', - 511: 'SP_PERF_SEL_DUMMY_LAST', -} -SQ_PERF_SEL_NONE = 0 -SQ_PERF_SEL_ACCUM_PREV = 1 -SQ_PERF_SEL_CYCLES = 2 -SQ_PERF_SEL_BUSY_CYCLES = 3 -SQ_PERF_SEL_WAVES = 4 -SQ_PERF_SEL_WAVES_32 = 5 -SQ_PERF_SEL_WAVES_64 = 6 -SQ_PERF_SEL_LEVEL_WAVES = 7 -SQ_PERF_SEL_ITEMS = 8 -SQ_PERF_SEL_WAVE32_ITEMS = 9 -SQ_PERF_SEL_WAVE64_ITEMS = 10 -SQ_PERF_SEL_QUADS = 11 -SQ_PERF_SEL_EVENTS = 12 -SQ_PERF_SEL_WAVES_EQ_64 = 13 -SQ_PERF_SEL_WAVES_LT_64 = 14 -SQ_PERF_SEL_WAVES_LT_48 = 15 -SQ_PERF_SEL_WAVES_LT_32 = 16 -SQ_PERF_SEL_WAVES_LT_16 = 17 -SQ_PERF_SEL_WAVES_RESTORED = 18 -SQ_PERF_SEL_WAVES_SAVED = 19 -SQ_PERF_SEL_MSG = 20 -SQ_PERF_SEL_MSG_GSCNT = 21 -SQ_PERF_SEL_MSG_INTERRUPT = 22 -SQ_PERF_SEL_Reserved_1 = 23 -SQ_PERF_SEL_Reserved_2 = 24 -SQ_PERF_SEL_Reserved_3 = 25 -SQ_PERF_SEL_WAVE_CYCLES = 26 -SQ_PERF_SEL_WAVE_READY = 27 -SQ_PERF_SEL_WAIT_INST_ANY = 28 -SQ_PERF_SEL_WAIT_INST_VALU = 29 -SQ_PERF_SEL_WAIT_INST_SCA = 30 -SQ_PERF_SEL_WAIT_INST_LDS = 31 -SQ_PERF_SEL_WAIT_INST_TEX = 32 -SQ_PERF_SEL_WAIT_INST_FLAT = 33 -SQ_PERF_SEL_WAIT_INST_VMEM = 34 -SQ_PERF_SEL_WAIT_INST_EXP_GDS = 35 -SQ_PERF_SEL_WAIT_INST_BR_MSG = 36 -SQ_PERF_SEL_WAIT_ANY = 37 -SQ_PERF_SEL_WAIT_CNT_ANY = 38 -SQ_PERF_SEL_WAIT_CNT_VMVS = 39 -SQ_PERF_SEL_WAIT_CNT_LGKM = 40 -SQ_PERF_SEL_WAIT_CNT_EXP = 41 -SQ_PERF_SEL_WAIT_TTRACE = 42 -SQ_PERF_SEL_WAIT_IFETCH = 43 -SQ_PERF_SEL_WAIT_BARRIER = 44 -SQ_PERF_SEL_WAIT_EXP_ALLOC = 45 -SQ_PERF_SEL_WAIT_SLEEP = 46 -SQ_PERF_SEL_WAIT_SLEEP_XNACK = 47 -SQ_PERF_SEL_WAIT_OTHER = 48 -SQ_PERF_SEL_INSTS_ALL = 49 -SQ_PERF_SEL_INSTS_BRANCH = 50 -SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 51 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 52 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 53 -SQ_PERF_SEL_INSTS_EXP_GDS = 54 -SQ_PERF_SEL_INSTS_GDS = 55 -SQ_PERF_SEL_INSTS_EXP = 56 -SQ_PERF_SEL_INSTS_FLAT = 57 -SQ_PERF_SEL_Reserved_4 = 58 -SQ_PERF_SEL_INSTS_LDS = 59 -SQ_PERF_SEL_INSTS_SALU = 60 -SQ_PERF_SEL_INSTS_SMEM = 61 -SQ_PERF_SEL_INSTS_SMEM_NORM = 62 -SQ_PERF_SEL_INSTS_SENDMSG = 63 -SQ_PERF_SEL_INSTS_VALU = 64 -SQ_PERF_SEL_Reserved_17 = 65 -SQ_PERF_SEL_INSTS_VALU_TRANS32 = 66 -SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 67 -SQ_PERF_SEL_INSTS_TEX = 68 -SQ_PERF_SEL_INSTS_TEX_LOAD = 69 -SQ_PERF_SEL_INSTS_TEX_STORE = 70 -SQ_PERF_SEL_INSTS_WAVE32 = 71 -SQ_PERF_SEL_INSTS_WAVE32_FLAT = 72 -SQ_PERF_SEL_Reserved_5 = 73 -SQ_PERF_SEL_INSTS_WAVE32_LDS = 74 -SQ_PERF_SEL_INSTS_WAVE32_VALU = 75 -SQ_PERF_SEL_Reserved_16 = 76 -SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 77 -SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 78 -SQ_PERF_SEL_INSTS_WAVE32_TEX = 79 -SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 80 -SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 81 -SQ_PERF_SEL_ITEM_CYCLES_VALU = 82 -SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 83 -SQ_PERF_SEL_WAVE32_INSTS = 84 -SQ_PERF_SEL_WAVE64_INSTS = 85 -SQ_PERF_SEL_Reserved_18 = 86 -SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 87 -SQ_PERF_SEL_WAVE64_HALF_SKIP = 88 -SQ_PERF_SEL_INSTS_TEX_REPLAY = 89 -SQ_PERF_SEL_INSTS_SMEM_REPLAY = 90 -SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 91 -SQ_PERF_SEL_INSTS_FLAT_REPLAY = 92 -SQ_PERF_SEL_XNACK_ALL = 93 -SQ_PERF_SEL_XNACK_FIRST = 94 -SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD = 95 -SQ_PERF_SEL_INSTS_VALU_VINTRP_OP = 96 -SQ_PERF_SEL_INST_LEVEL_EXP = 97 -SQ_PERF_SEL_INST_LEVEL_GDS = 98 -SQ_PERF_SEL_INST_LEVEL_LDS = 99 -SQ_PERF_SEL_INST_LEVEL_SMEM = 100 -SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 101 -SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 102 -SQ_PERF_SEL_IFETCH_REQS = 103 -SQ_PERF_SEL_IFETCH_LEVEL = 104 -SQ_PERF_SEL_IFETCH_XNACK = 105 -SQ_PERF_SEL_Reserved_6 = 106 -SQ_PERF_SEL_Reserved_7 = 107 -SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 108 -SQ_PERF_SEL_VALU_SGATHER_STALL = 109 -SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 110 -SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 111 -SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 112 -SQ_PERF_SEL_SALU_SGATHER_STALL = 113 -SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 114 -SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 115 -SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 116 -SQ_PERF_SEL_INST_CYCLES_VALU = 117 -SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 118 -SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 119 -SQ_PERF_SEL_INST_CYCLES_VMEM = 120 -SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 121 -SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 122 -SQ_PERF_SEL_INST_CYCLES_LDS = 123 -SQ_PERF_SEL_INST_CYCLES_TEX = 124 -SQ_PERF_SEL_INST_CYCLES_FLAT = 125 -SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 126 -SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 127 -SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 128 -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 129 -SQ_PERF_SEL_Reserved_8 = 130 -SQ_PERF_SEL_Reserved_9 = 131 -SQ_PERF_SEL_Reserved_10 = 132 -SQ_PERF_SEL_Reserved_11 = 133 -SQ_PERF_SEL_Reserved_12 = 134 -SQ_PERF_SEL_Reserved_13 = 135 -SQ_PERF_SEL_Reserved_14 = 136 -SQ_PERF_SEL_VMEM_BUS_ACTIVE = 137 -SQ_PERF_SEL_VMEM_BUS_STALL = 138 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 139 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 140 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 141 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 142 -SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 143 -SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 144 -SQ_PERF_SEL_Reserved_15 = 145 -SQ_PERF_SEL_SALU_PIPE_STALL = 146 -SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 147 -SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL = 148 -SQ_PERF_SEL_MSG_BUS_BUSY = 149 -SQ_PERF_SEL_EXP_REQ_BUS_STALL = 150 -SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 151 -SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 152 -SQ_PERF_SEL_EXP_BUS0_BUSY = 153 -SQ_PERF_SEL_EXP_BUS1_BUSY = 154 -SQ_PERF_SEL_INST_CACHE_REQS = 155 -SQ_PERF_SEL_INST_CACHE_REQ_STALL = 156 -SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU = 157 -SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU = 158 -SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM = 159 -SQ_PERF_SEL_USER0 = 160 -SQ_PERF_SEL_USER1 = 161 -SQ_PERF_SEL_USER2 = 162 -SQ_PERF_SEL_USER3 = 163 -SQ_PERF_SEL_USER4 = 164 -SQ_PERF_SEL_USER5 = 165 -SQ_PERF_SEL_USER6 = 166 -SQ_PERF_SEL_USER7 = 167 -SQ_PERF_SEL_USER8 = 168 -SQ_PERF_SEL_USER9 = 169 -SQ_PERF_SEL_USER10 = 170 -SQ_PERF_SEL_USER11 = 171 -SQ_PERF_SEL_USER12 = 172 -SQ_PERF_SEL_USER13 = 173 -SQ_PERF_SEL_USER14 = 174 -SQ_PERF_SEL_USER15 = 175 -SQ_PERF_SEL_USER_LEVEL0 = 176 -SQ_PERF_SEL_USER_LEVEL1 = 177 -SQ_PERF_SEL_USER_LEVEL2 = 178 -SQ_PERF_SEL_USER_LEVEL3 = 179 -SQ_PERF_SEL_USER_LEVEL4 = 180 -SQ_PERF_SEL_USER_LEVEL5 = 181 -SQ_PERF_SEL_USER_LEVEL6 = 182 -SQ_PERF_SEL_USER_LEVEL7 = 183 -SQ_PERF_SEL_USER_LEVEL8 = 184 -SQ_PERF_SEL_USER_LEVEL9 = 185 -SQ_PERF_SEL_USER_LEVEL10 = 186 -SQ_PERF_SEL_USER_LEVEL11 = 187 -SQ_PERF_SEL_USER_LEVEL12 = 188 -SQ_PERF_SEL_USER_LEVEL13 = 189 -SQ_PERF_SEL_USER_LEVEL14 = 190 -SQ_PERF_SEL_USER_LEVEL15 = 191 -SQ_PERF_SEL_VALU_RETURN_SDST = 192 -SQ_PERF_SEL_VMEM_SECOND_TRY_USED = 193 -SQ_PERF_SEL_VMEM_SECOND_TRY_STALL = 194 -SQ_PERF_SEL_DUMMY_END = 195 -SQ_PERF_SEL_DUMMY_LAST = 255 -SQG_PERF_SEL_UTCL0_TRANSLATION_MISS = 256 -SQG_PERF_SEL_UTCL0_PERMISSION_MISS = 257 -SQG_PERF_SEL_UTCL0_TRANSLATION_HIT = 258 -SQG_PERF_SEL_UTCL0_REQUEST = 259 -SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 260 -SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 261 -SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 262 -SQG_PERF_SEL_UTCL0_LFIFO_FULL = 263 -SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 264 -SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 265 -SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL = 266 -SQG_PERF_SEL_UTCL0_UTCL1_REQ = 267 -SQG_PERF_SEL_TLB_SHOOTDOWN = 268 -SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 269 -SQG_PERF_SEL_TTRACE_REQS = 270 -SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 271 -SQG_PERF_SEL_TTRACE_STALL = 272 -SQG_PERF_SEL_TTRACE_LOST_PACKETS = 273 -SQG_PERF_SEL_DUMMY_LAST = 274 -SQC_PERF_SEL_POWER_VALU = 275 -SQC_PERF_SEL_POWER_VALU0 = 276 -SQC_PERF_SEL_POWER_VALU1 = 277 -SQC_PERF_SEL_POWER_VALU2 = 278 -SQC_PERF_SEL_POWER_GPR_RD = 279 -SQC_PERF_SEL_POWER_GPR_WR = 280 -SQC_PERF_SEL_POWER_LDS_BUSY = 281 -SQC_PERF_SEL_POWER_ALU_BUSY = 282 -SQC_PERF_SEL_POWER_TEX_BUSY = 283 -SQC_PERF_SEL_PT_POWER_STALL = 284 -SQC_PERF_SEL_LDS_BANK_CONFLICT = 285 -SQC_PERF_SEL_LDS_ADDR_CONFLICT = 286 -SQC_PERF_SEL_LDS_UNALIGNED_STALL = 287 -SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 288 -SQC_PERF_SEL_LDS_ATOMIC_RETURN = 289 -SQC_PERF_SEL_LDS_IDX_ACTIVE = 290 -SQC_PERF_SEL_LDS_DATA_FIFO_FULL = 291 -SQC_PERF_SEL_LDS_CMD_FIFO_FULL = 292 -SQC_PERF_SEL_LDS_ADDR_STALL = 293 -SQC_PERF_SEL_LDS_ADDR_ACTIVE = 294 -SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL = 295 -SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296 -SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297 -SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298 -SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299 -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300 -SQC_PERF_SEL_ICACHE_REQ = 301 -SQC_PERF_SEL_ICACHE_HITS = 302 -SQC_PERF_SEL_ICACHE_MISSES = 303 -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304 -SQC_PERF_SEL_ICACHE_INVAL_INST = 305 -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306 -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307 -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308 -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309 -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310 -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 312 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 313 -SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 314 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 315 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 316 -SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 317 -SQC_PERF_SEL_TC_REQ = 318 -SQC_PERF_SEL_TC_INST_REQ = 319 -SQC_PERF_SEL_TC_DATA_READ_REQ = 320 -SQC_PERF_SEL_TC_DATA_WRITE_REQ = 321 -SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 322 -SQC_PERF_SEL_TC_STALL = 323 -SQC_PERF_SEL_TC_STARVE = 324 -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 325 -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 326 -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 327 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 328 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 329 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 330 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 331 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 332 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 333 -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 334 -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 335 -SQC_PERF_SEL_DCACHE_REQ = 336 -SQC_PERF_SEL_DCACHE_HITS = 337 -SQC_PERF_SEL_DCACHE_MISSES = 338 -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 339 -SQC_PERF_SEL_DCACHE_INVAL_INST = 340 -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 341 -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 342 -SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 343 -SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 344 -SQC_PERF_SEL_DCACHE_ATOMIC = 345 -SQC_PERF_SEL_DCACHE_WB_INST = 346 -SQC_PERF_SEL_DCACHE_WB_ASYNC = 347 -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 348 -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 349 -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 350 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 351 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 352 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 353 -SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 354 -SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 355 -SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 356 -SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 357 -SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 358 -SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 359 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 360 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 361 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 362 -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 363 -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 364 -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 365 -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 366 -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 367 -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 368 -SQC_PERF_SEL_DCACHE_REQ_TIME = 369 -SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 370 -SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 371 -SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 372 -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 373 -SQC_PERF_SEL_SQ_DCACHE_REQS = 374 -SQC_PERF_SEL_DCACHE_FLAT_REQ = 375 -SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 376 -SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS = 377 -SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS = 378 -SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT = 379 -SQC_PERF_SEL_ICACHE_UTCL0_REQUEST = 380 -SQC_PERF_SEL_ICACHE_UTCL0_XNACK = 381 -SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX = 382 -SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT = 383 -SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL = 384 -SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES = 385 -SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 386 -SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT = 387 -SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL = 388 -SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS = 389 -SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS = 390 -SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT = 391 -SQC_PERF_SEL_DCACHE_UTCL0_REQUEST = 392 -SQC_PERF_SEL_DCACHE_UTCL0_XNACK = 393 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX = 394 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT = 395 -SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL = 396 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES = 397 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 398 -SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT = 399 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL = 400 -SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS = 401 -SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL = 402 -SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL = 403 -SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ = 404 -SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 405 -SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 406 -SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL = 407 -SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ = 408 -SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 409 -SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 410 -SQC_PERF_SEL_ICACHE_GCR = 411 -SQC_PERF_SEL_ICACHE_GCR_HITS = 412 -SQC_PERF_SEL_DCACHE_GCR = 413 -SQC_PERF_SEL_DCACHE_GCR_HITS = 414 -SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 415 -SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 416 -SQC_PERF_SEL_DCACHE_GCR_WRITEBACK = 417 -SQC_PERF_SEL_DUMMY_LAST = 418 -SP_PERF_SEL_DUMMY_BEGIN = 448 -SP_PERF_SEL_DUMMY_LAST = 511 -SQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_CAC_POWER_SEL' -SQ_CAC_POWER_SEL__enumvalues = { - 0: 'SQ_CAC_POWER_VALU', - 1: 'SQ_CAC_POWER_VALU0', - 2: 'SQ_CAC_POWER_VALU1', - 3: 'SQ_CAC_POWER_VALU2', - 4: 'SQ_CAC_POWER_GPR_RD', - 5: 'SQ_CAC_POWER_GPR_WR', - 6: 'SQ_CAC_POWER_LDS_BUSY', - 7: 'SQ_CAC_POWER_ALU_BUSY', - 8: 'SQ_CAC_POWER_TEX_BUSY', -} -SQ_CAC_POWER_VALU = 0 -SQ_CAC_POWER_VALU0 = 1 -SQ_CAC_POWER_VALU1 = 2 -SQ_CAC_POWER_VALU2 = 3 -SQ_CAC_POWER_GPR_RD = 4 -SQ_CAC_POWER_GPR_WR = 5 -SQ_CAC_POWER_LDS_BUSY = 6 -SQ_CAC_POWER_ALU_BUSY = 7 -SQ_CAC_POWER_TEX_BUSY = 8 -SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_CMD' -SQ_IND_CMD_CMD__enumvalues = { - 0: 'SQ_IND_CMD_CMD_NULL', - 1: 'SQ_IND_CMD_CMD_SETHALT', - 2: 'SQ_IND_CMD_CMD_SAVECTX', - 3: 'SQ_IND_CMD_CMD_KILL', - 4: 'SQ_IND_CMD_CMD_DEBUG', - 5: 'SQ_IND_CMD_CMD_TRAP', - 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 7: 'SQ_IND_CMD_CMD_SETFATALHALT', - 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', -} -SQ_IND_CMD_CMD_NULL = 0 -SQ_IND_CMD_CMD_SETHALT = 1 -SQ_IND_CMD_CMD_SAVECTX = 2 -SQ_IND_CMD_CMD_KILL = 3 -SQ_IND_CMD_CMD_DEBUG = 4 -SQ_IND_CMD_CMD_TRAP = 5 -SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 -SQ_IND_CMD_CMD_SETFATALHALT = 7 -SQ_IND_CMD_CMD_SINGLE_STEP = 8 -SQ_IND_CMD_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_MODE' -SQ_IND_CMD_MODE__enumvalues = { - 0: 'SQ_IND_CMD_MODE_SINGLE', - 1: 'SQ_IND_CMD_MODE_BROADCAST', - 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', - 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', -} -SQ_IND_CMD_MODE_SINGLE = 0 -SQ_IND_CMD_MODE_BROADCAST = 1 -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 -SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 -SQ_IND_CMD_MODE_BROADCAST_ME = 4 -SQ_IND_CMD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_EDC_INFO_SOURCE' -SQ_EDC_INFO_SOURCE__enumvalues = { - 0: 'SQ_EDC_INFO_SOURCE_INVALID', - 1: 'SQ_EDC_INFO_SOURCE_INST', - 2: 'SQ_EDC_INFO_SOURCE_SGPR', - 3: 'SQ_EDC_INFO_SOURCE_VGPR', - 4: 'SQ_EDC_INFO_SOURCE_LDS', - 5: 'SQ_EDC_INFO_SOURCE_GDS', - 6: 'SQ_EDC_INFO_SOURCE_TA', -} -SQ_EDC_INFO_SOURCE_INVALID = 0 -SQ_EDC_INFO_SOURCE_INST = 1 -SQ_EDC_INFO_SOURCE_SGPR = 2 -SQ_EDC_INFO_SOURCE_VGPR = 3 -SQ_EDC_INFO_SOURCE_LDS = 4 -SQ_EDC_INFO_SOURCE_GDS = 5 -SQ_EDC_INFO_SOURCE_TA = 6 -SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_ROUND_MODE' -SQ_ROUND_MODE__enumvalues = { - 0: 'SQ_ROUND_NEAREST_EVEN', - 1: 'SQ_ROUND_PLUS_INFINITY', - 2: 'SQ_ROUND_MINUS_INFINITY', - 3: 'SQ_ROUND_TO_ZERO', -} -SQ_ROUND_NEAREST_EVEN = 0 -SQ_ROUND_PLUS_INFINITY = 1 -SQ_ROUND_MINUS_INFINITY = 2 -SQ_ROUND_TO_ZERO = 3 -SQ_ROUND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' -SQ_INTERRUPT_WORD_ENCODING__enumvalues = { - 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', - 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', - 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', -} -SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 -SQ_INTERRUPT_WORD_ENCODING_INST = 1 -SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 -SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IBUF_ST' -SQ_IBUF_ST__enumvalues = { - 0: 'SQ_IBUF_IB_IDLE', - 1: 'SQ_IBUF_IB_INI_WAIT_GNT', - 2: 'SQ_IBUF_IB_INI_WAIT_DRET', - 3: 'SQ_IBUF_IB_LE_4DW', - 4: 'SQ_IBUF_IB_WAIT_DRET', - 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 6: 'SQ_IBUF_IB_DRET', - 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', -} -SQ_IBUF_IB_IDLE = 0 -SQ_IBUF_IB_INI_WAIT_GNT = 1 -SQ_IBUF_IB_INI_WAIT_DRET = 2 -SQ_IBUF_IB_LE_4DW = 3 -SQ_IBUF_IB_WAIT_DRET = 4 -SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 -SQ_IBUF_IB_DRET = 6 -SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 -SQ_IBUF_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_STR_ST' -SQ_INST_STR_ST__enumvalues = { - 0: 'SQ_INST_STR_IB_WAVE_NORML', - 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', - 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', - 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', - 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', -} -SQ_INST_STR_IB_WAVE_NORML = 0 -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 -SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 -SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 -SQ_INST_STR_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_IB_ECC_ST' -SQ_WAVE_IB_ECC_ST__enumvalues = { - 0: 'SQ_WAVE_IB_ECC_CLEAN', - 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 2: 'SQ_WAVE_IB_ECC_ERR_HALT', - 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', -} -SQ_WAVE_IB_ECC_CLEAN = 0 -SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 -SQ_WAVE_IB_ECC_ERR_HALT = 2 -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 -SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ADDRESS_MODE' -SH_MEM_ADDRESS_MODE__enumvalues = { - 0: 'SH_MEM_ADDRESS_MODE_64', - 1: 'SH_MEM_ADDRESS_MODE_32', -} -SH_MEM_ADDRESS_MODE_64 = 0 -SH_MEM_ADDRESS_MODE_32 = 1 -SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_RETRY_MODE' -SH_MEM_RETRY_MODE__enumvalues = { - 0: 'SH_MEM_RETRY_MODE_ALL', - 1: 'SH_MEM_RETRY_MODE_WRITEATOMIC', - 2: 'SH_MEM_RETRY_MODE_NONE', -} -SH_MEM_RETRY_MODE_ALL = 0 -SH_MEM_RETRY_MODE_WRITEATOMIC = 1 -SH_MEM_RETRY_MODE_NONE = 2 -SH_MEM_RETRY_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ALIGNMENT_MODE' -SH_MEM_ALIGNMENT_MODE__enumvalues = { - 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', - 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', - 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', -} -SH_MEM_ALIGNMENT_MODE_DWORD = 0 -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 -SH_MEM_ALIGNMENT_MODE_STRICT = 2 -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 -SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', - 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', - 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', - 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', - 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', - 6: 'SQ_TT_TOKEN_MASK_OTHER_SHIFT', - 7: 'SQ_TT_TOKEN_MASK_READS_SHIFT', -} -SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 -SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 -SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 -SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 -SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 -SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 -SQ_TT_TOKEN_MASK_OTHER_SHIFT = 6 -SQ_TT_TOKEN_MASK_READS_SHIFT = 7 -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' -SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { - 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', - 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', - 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', - 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', - 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', - 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', - 64: 'SQ_TT_TOKEN_MASK_OTHER_BIT', - 128: 'SQ_TT_TOKEN_MASK_READS_BIT', -} -SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 -SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 -SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 -SQ_TT_TOKEN_MASK_COMP_BIT = 8 -SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 -SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 -SQ_TT_TOKEN_MASK_OTHER_BIT = 64 -SQ_TT_TOKEN_MASK_READS_BIT = 128 -SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', - 4: 'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT', - 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', -} -SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 -SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 -SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 -SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 -SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT = 4 -SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 -SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 -SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 -SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 -SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 -SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 -SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' -SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { - 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD', - 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234', -} -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD = 0 -SQ_TT_INST_EXCLUDE_EXPGNT234 = 1 -SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_MODE' -SQ_TT_MODE__enumvalues = { - 0: 'SQ_TT_MODE_OFF', - 1: 'SQ_TT_MODE_ON', - 2: 'SQ_TT_MODE_GLOBAL', - 3: 'SQ_TT_MODE_DETAIL', -} -SQ_TT_MODE_OFF = 0 -SQ_TT_MODE_ON = 1 -SQ_TT_MODE_GLOBAL = 2 -SQ_TT_MODE_DETAIL = 3 -SQ_TT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' -SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', - 1: 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT', - 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', - 3: 'SQ_TT_WTYPE_INCLUDE_ES_SHIFT', - 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', - 5: 'SQ_TT_WTYPE_INCLUDE_LS_SHIFT', - 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', -} -SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 -SQ_TT_WTYPE_INCLUDE_VS_SHIFT = 1 -SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 -SQ_TT_WTYPE_INCLUDE_ES_SHIFT = 3 -SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 -SQ_TT_WTYPE_INCLUDE_LS_SHIFT = 5 -SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 -SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE' -SQ_TT_WTYPE_INCLUDE__enumvalues = { - 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 2: 'SQ_TT_WTYPE_INCLUDE_VS_BIT', - 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 8: 'SQ_TT_WTYPE_INCLUDE_ES_BIT', - 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 32: 'SQ_TT_WTYPE_INCLUDE_LS_BIT', - 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', -} -SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 -SQ_TT_WTYPE_INCLUDE_VS_BIT = 2 -SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 -SQ_TT_WTYPE_INCLUDE_ES_BIT = 8 -SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 -SQ_TT_WTYPE_INCLUDE_LS_BIT = 32 -SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 -SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_UTIL_TIMER' -SQ_TT_UTIL_TIMER__enumvalues = { - 0: 'SQ_TT_UTIL_TIMER_100_CLK', - 1: 'SQ_TT_UTIL_TIMER_250_CLK', -} -SQ_TT_UTIL_TIMER_100_CLK = 0 -SQ_TT_UTIL_TIMER_250_CLK = 1 -SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WAVESTART_MODE' -SQ_TT_WAVESTART_MODE__enumvalues = { - 0: 'SQ_TT_WAVESTART_MODE_SHORT', - 1: 'SQ_TT_WAVESTART_MODE_ALLOC', - 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', -} -SQ_TT_WAVESTART_MODE_SHORT = 0 -SQ_TT_WAVESTART_MODE_ALLOC = 1 -SQ_TT_WAVESTART_MODE_PBB_ID = 2 -SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_RT_FREQ' -SQ_TT_RT_FREQ__enumvalues = { - 0: 'SQ_TT_RT_FREQ_NEVER', - 1: 'SQ_TT_RT_FREQ_1024_CLK', - 2: 'SQ_TT_RT_FREQ_4096_CLK', -} -SQ_TT_RT_FREQ_NEVER = 0 -SQ_TT_RT_FREQ_1024_CLK = 1 -SQ_TT_RT_FREQ_4096_CLK = 2 -SQ_TT_RT_FREQ = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WATCH_MODES' -SQ_WATCH_MODES__enumvalues = { - 0: 'SQ_WATCH_MODE_READ', - 1: 'SQ_WATCH_MODE_NONREAD', - 2: 'SQ_WATCH_MODE_ATOMIC', - 3: 'SQ_WATCH_MODE_ALL', -} -SQ_WATCH_MODE_READ = 0 -SQ_WATCH_MODE_NONREAD = 1 -SQ_WATCH_MODE_ATOMIC = 2 -SQ_WATCH_MODE_ALL = 3 -SQ_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_SCHED_MODES' -SQ_WAVE_SCHED_MODES__enumvalues = { - 0: 'SQ_WAVE_SCHED_MODE_NORMAL', - 1: 'SQ_WAVE_SCHED_MODE_EXPERT', - 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', -} -SQ_WAVE_SCHED_MODE_NORMAL = 0 -SQ_WAVE_SCHED_MODE_EXPERT = 1 -SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 -SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'CSDATA_TYPE' -CSDATA_TYPE__enumvalues = { - 0: 'CSDATA_TYPE_TG', - 1: 'CSDATA_TYPE_STATE', - 2: 'CSDATA_TYPE_EVENT', - 3: 'CSDATA_TYPE_PRIVATE', -} -CSDATA_TYPE_TG = 0 -CSDATA_TYPE_STATE = 1 -CSDATA_TYPE_EVENT = 2 -CSDATA_TYPE_PRIVATE = 3 -CSDATA_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSCNTL_TYPE' -CSCNTL_TYPE__enumvalues = { - 0: 'CSCNTL_TYPE_TG', - 1: 'CSCNTL_TYPE_STATE', - 2: 'CSCNTL_TYPE_EVENT', - 3: 'CSCNTL_TYPE_PRIVATE', -} -CSCNTL_TYPE_TG = 0 -CSCNTL_TYPE_STATE = 1 -CSCNTL_TYPE_EVENT = 2 -CSCNTL_TYPE_PRIVATE = 3 -CSCNTL_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUT_PRIM_TYPE' -VGT_OUT_PRIM_TYPE__enumvalues = { - 0: 'VGT_OUT_POINT', - 1: 'VGT_OUT_LINE', - 2: 'VGT_OUT_TRI', - 3: 'VGT_OUT_RECT_V0', - 4: 'VGT_OUT_RECT_V1', - 5: 'VGT_OUT_RECT_V2', - 6: 'VGT_OUT_RECT_V3', - 7: 'VGT_OUT_2D_RECT', - 8: 'VGT_TE_QUAD', - 9: 'VGT_TE_PRIM_INDEX_LINE', - 10: 'VGT_TE_PRIM_INDEX_TRI', - 11: 'VGT_TE_PRIM_INDEX_QUAD', - 12: 'VGT_OUT_LINE_ADJ', - 13: 'VGT_OUT_TRI_ADJ', - 14: 'VGT_OUT_PATCH', -} -VGT_OUT_POINT = 0 -VGT_OUT_LINE = 1 -VGT_OUT_TRI = 2 -VGT_OUT_RECT_V0 = 3 -VGT_OUT_RECT_V1 = 4 -VGT_OUT_RECT_V2 = 5 -VGT_OUT_RECT_V3 = 6 -VGT_OUT_2D_RECT = 7 -VGT_TE_QUAD = 8 -VGT_TE_PRIM_INDEX_LINE = 9 -VGT_TE_PRIM_INDEX_TRI = 10 -VGT_TE_PRIM_INDEX_QUAD = 11 -VGT_OUT_LINE_ADJ = 12 -VGT_OUT_TRI_ADJ = 13 -VGT_OUT_PATCH = 14 -VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_PRIM_TYPE' -VGT_DI_PRIM_TYPE__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_2D_RECTANGLE', - 8: 'DI_PT_UNUSED_1', - 9: 'DI_PT_PATCH', - 10: 'DI_PT_LINELIST_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRILIST_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 14: 'DI_PT_UNUSED_3', - 15: 'DI_PT_UNUSED_4', - 16: 'DI_PT_TRI_WITH_WFLAGS', - 17: 'DI_PT_RECTLIST', - 18: 'DI_PT_LINELOOP', - 19: 'DI_PT_QUADLIST', - 20: 'DI_PT_QUADSTRIP', - 21: 'DI_PT_POLYGON', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_2D_RECTANGLE = 7 -DI_PT_UNUSED_1 = 8 -DI_PT_PATCH = 9 -DI_PT_LINELIST_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRILIST_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_UNUSED_3 = 14 -DI_PT_UNUSED_4 = 15 -DI_PT_TRI_WITH_WFLAGS = 16 -DI_PT_RECTLIST = 17 -DI_PT_LINELOOP = 18 -DI_PT_QUADLIST = 19 -DI_PT_QUADSTRIP = 20 -DI_PT_POLYGON = 21 -VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_SOURCE_SELECT' -VGT_DI_SOURCE_SELECT__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_RESERVED', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_RESERVED = 3 -VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' -VGT_DI_MAJOR_MODE_SELECT__enumvalues = { - 0: 'DI_MAJOR_MODE_0', - 1: 'DI_MAJOR_MODE_1', -} -DI_MAJOR_MODE_0 = 0 -DI_MAJOR_MODE_1 = 1 -VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_INDEX_SIZE' -VGT_DI_INDEX_SIZE__enumvalues = { - 0: 'DI_INDEX_SIZE_16_BIT', - 1: 'DI_INDEX_SIZE_32_BIT', - 2: 'DI_INDEX_SIZE_8_BIT', -} -DI_INDEX_SIZE_16_BIT = 0 -DI_INDEX_SIZE_32_BIT = 1 -DI_INDEX_SIZE_8_BIT = 2 -VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_EVENT_TYPE' -VGT_EVENT_TYPE__enumvalues = { - 0: 'Reserved_0x00', - 1: 'SAMPLE_STREAMOUTSTATS1', - 2: 'SAMPLE_STREAMOUTSTATS2', - 3: 'SAMPLE_STREAMOUTSTATS3', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'CS_PARTIAL_FLUSH', - 8: 'VGT_STREAMOUT_SYNC', - 9: 'SET_FE_ID', - 10: 'VGT_STREAMOUT_RESET', - 11: 'END_OF_PIPE_INCR_DE', - 12: 'END_OF_PIPE_IB_END', - 13: 'RST_PIX_CNT', - 14: 'BREAK_BATCH', - 15: 'VS_PARTIAL_FLUSH', - 16: 'PS_PARTIAL_FLUSH', - 17: 'FLUSH_HS_OUTPUT', - 18: 'FLUSH_DFSM', - 19: 'RESET_TO_LOWEST_VGT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'ZPASS_DONE', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 25: 'PIPELINESTAT_START', - 26: 'PIPELINESTAT_STOP', - 27: 'PERFCOUNTER_SAMPLE', - 28: 'FLUSH_ES_OUTPUT', - 29: 'BIN_CONF_OVERRIDE_CHECK', - 30: 'SAMPLE_PIPELINESTAT', - 31: 'SO_VGTSTREAMOUT_FLUSH', - 32: 'SAMPLE_STREAMOUTSTATS', - 33: 'RESET_VTX_CNT', - 34: 'BLOCK_CONTEXT_DONE', - 35: 'CS_CONTEXT_DONE', - 36: 'VGT_FLUSH', - 37: 'TGID_ROLLOVER', - 38: 'SQ_NON_EVENT', - 39: 'SC_SEND_DB_VPZ', - 40: 'BOTTOM_OF_PIPE_TS', - 41: 'FLUSH_SX_TS', - 42: 'DB_CACHE_FLUSH_AND_INV', - 43: 'FLUSH_AND_INV_DB_DATA_TS', - 44: 'FLUSH_AND_INV_DB_META', - 45: 'FLUSH_AND_INV_CB_DATA_TS', - 46: 'FLUSH_AND_INV_CB_META', - 47: 'CS_DONE', - 48: 'PS_DONE', - 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', - 50: 'SX_CB_RAT_ACK_REQUEST', - 51: 'THREAD_TRACE_START', - 52: 'THREAD_TRACE_STOP', - 53: 'THREAD_TRACE_MARKER', - 54: 'THREAD_TRACE_DRAW', - 55: 'THREAD_TRACE_FINISH', - 56: 'PIXEL_PIPE_STAT_CONTROL', - 57: 'PIXEL_PIPE_STAT_DUMP', - 58: 'PIXEL_PIPE_STAT_RESET', - 59: 'CONTEXT_SUSPEND', - 60: 'OFFCHIP_HS_DEALLOC', - 61: 'ENABLE_NGG_PIPELINE', - 62: 'ENABLE_LEGACY_PIPELINE', - 63: 'DRAW_DONE', -} -Reserved_0x00 = 0 -SAMPLE_STREAMOUTSTATS1 = 1 -SAMPLE_STREAMOUTSTATS2 = 2 -SAMPLE_STREAMOUTSTATS3 = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -CS_PARTIAL_FLUSH = 7 -VGT_STREAMOUT_SYNC = 8 -SET_FE_ID = 9 -VGT_STREAMOUT_RESET = 10 -END_OF_PIPE_INCR_DE = 11 -END_OF_PIPE_IB_END = 12 -RST_PIX_CNT = 13 -BREAK_BATCH = 14 -VS_PARTIAL_FLUSH = 15 -PS_PARTIAL_FLUSH = 16 -FLUSH_HS_OUTPUT = 17 -FLUSH_DFSM = 18 -RESET_TO_LOWEST_VGT = 19 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -ZPASS_DONE = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -PIPELINESTAT_START = 25 -PIPELINESTAT_STOP = 26 -PERFCOUNTER_SAMPLE = 27 -FLUSH_ES_OUTPUT = 28 -BIN_CONF_OVERRIDE_CHECK = 29 -SAMPLE_PIPELINESTAT = 30 -SO_VGTSTREAMOUT_FLUSH = 31 -SAMPLE_STREAMOUTSTATS = 32 -RESET_VTX_CNT = 33 -BLOCK_CONTEXT_DONE = 34 -CS_CONTEXT_DONE = 35 -VGT_FLUSH = 36 -TGID_ROLLOVER = 37 -SQ_NON_EVENT = 38 -SC_SEND_DB_VPZ = 39 -BOTTOM_OF_PIPE_TS = 40 -FLUSH_SX_TS = 41 -DB_CACHE_FLUSH_AND_INV = 42 -FLUSH_AND_INV_DB_DATA_TS = 43 -FLUSH_AND_INV_DB_META = 44 -FLUSH_AND_INV_CB_DATA_TS = 45 -FLUSH_AND_INV_CB_META = 46 -CS_DONE = 47 -PS_DONE = 48 -FLUSH_AND_INV_CB_PIXEL_DATA = 49 -SX_CB_RAT_ACK_REQUEST = 50 -THREAD_TRACE_START = 51 -THREAD_TRACE_STOP = 52 -THREAD_TRACE_MARKER = 53 -THREAD_TRACE_DRAW = 54 -THREAD_TRACE_FINISH = 55 -PIXEL_PIPE_STAT_CONTROL = 56 -PIXEL_PIPE_STAT_DUMP = 57 -PIXEL_PIPE_STAT_RESET = 58 -CONTEXT_SUSPEND = 59 -OFFCHIP_HS_DEALLOC = 60 -ENABLE_NGG_PIPELINE = 61 -ENABLE_LEGACY_PIPELINE = 62 -DRAW_DONE = 63 -VGT_EVENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_SWAP_MODE' -VGT_DMA_SWAP_MODE__enumvalues = { - 0: 'VGT_DMA_SWAP_NONE', - 1: 'VGT_DMA_SWAP_16_BIT', - 2: 'VGT_DMA_SWAP_32_BIT', - 3: 'VGT_DMA_SWAP_WORD', -} -VGT_DMA_SWAP_NONE = 0 -VGT_DMA_SWAP_16_BIT = 1 -VGT_DMA_SWAP_32_BIT = 2 -VGT_DMA_SWAP_WORD = 3 -VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_INDEX_TYPE_MODE' -VGT_INDEX_TYPE_MODE__enumvalues = { - 0: 'VGT_INDEX_16', - 1: 'VGT_INDEX_32', - 2: 'VGT_INDEX_8', -} -VGT_INDEX_16 = 0 -VGT_INDEX_32 = 1 -VGT_INDEX_8 = 2 -VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_BUF_TYPE' -VGT_DMA_BUF_TYPE__enumvalues = { - 0: 'VGT_DMA_BUF_MEM', - 1: 'VGT_DMA_BUF_RING', - 2: 'VGT_DMA_BUF_SETUP', - 3: 'VGT_DMA_PTR_UPDATE', -} -VGT_DMA_BUF_MEM = 0 -VGT_DMA_BUF_RING = 1 -VGT_DMA_BUF_SETUP = 2 -VGT_DMA_PTR_UPDATE = 3 -VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUTPATH_SELECT' -VGT_OUTPATH_SELECT__enumvalues = { - 0: 'VGT_OUTPATH_VTX_REUSE', - 1: 'VGT_OUTPATH_GS_BLOCK', - 2: 'VGT_OUTPATH_HS_BLOCK', - 3: 'VGT_OUTPATH_PRIM_GEN', - 4: 'VGT_OUTPATH_TE_PRIM_GEN', - 5: 'VGT_OUTPATH_TE_GS_BLOCK', - 6: 'VGT_OUTPATH_TE_OUTPUT', -} -VGT_OUTPATH_VTX_REUSE = 0 -VGT_OUTPATH_GS_BLOCK = 1 -VGT_OUTPATH_HS_BLOCK = 2 -VGT_OUTPATH_PRIM_GEN = 3 -VGT_OUTPATH_TE_PRIM_GEN = 4 -VGT_OUTPATH_TE_GS_BLOCK = 5 -VGT_OUTPATH_TE_OUTPUT = 6 -VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GRP_PRIM_TYPE' -VGT_GRP_PRIM_TYPE__enumvalues = { - 0: 'VGT_GRP_3D_POINT', - 1: 'VGT_GRP_3D_LINE', - 2: 'VGT_GRP_3D_TRI', - 3: 'VGT_GRP_3D_RECT', - 4: 'VGT_GRP_3D_QUAD', - 5: 'VGT_GRP_2D_COPY_RECT_V0', - 6: 'VGT_GRP_2D_COPY_RECT_V1', - 7: 'VGT_GRP_2D_COPY_RECT_V2', - 8: 'VGT_GRP_2D_COPY_RECT_V3', - 9: 'VGT_GRP_2D_FILL_RECT', - 10: 'VGT_GRP_2D_LINE', - 11: 'VGT_GRP_2D_TRI', - 12: 'VGT_GRP_PRIM_INDEX_LINE', - 13: 'VGT_GRP_PRIM_INDEX_TRI', - 14: 'VGT_GRP_PRIM_INDEX_QUAD', - 15: 'VGT_GRP_3D_LINE_ADJ', - 16: 'VGT_GRP_3D_TRI_ADJ', - 17: 'VGT_GRP_3D_PATCH', - 18: 'VGT_GRP_2D_RECT', -} -VGT_GRP_3D_POINT = 0 -VGT_GRP_3D_LINE = 1 -VGT_GRP_3D_TRI = 2 -VGT_GRP_3D_RECT = 3 -VGT_GRP_3D_QUAD = 4 -VGT_GRP_2D_COPY_RECT_V0 = 5 -VGT_GRP_2D_COPY_RECT_V1 = 6 -VGT_GRP_2D_COPY_RECT_V2 = 7 -VGT_GRP_2D_COPY_RECT_V3 = 8 -VGT_GRP_2D_FILL_RECT = 9 -VGT_GRP_2D_LINE = 10 -VGT_GRP_2D_TRI = 11 -VGT_GRP_PRIM_INDEX_LINE = 12 -VGT_GRP_PRIM_INDEX_TRI = 13 -VGT_GRP_PRIM_INDEX_QUAD = 14 -VGT_GRP_3D_LINE_ADJ = 15 -VGT_GRP_3D_TRI_ADJ = 16 -VGT_GRP_3D_PATCH = 17 -VGT_GRP_2D_RECT = 18 -VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GRP_PRIM_ORDER' -VGT_GRP_PRIM_ORDER__enumvalues = { - 0: 'VGT_GRP_LIST', - 1: 'VGT_GRP_STRIP', - 2: 'VGT_GRP_FAN', - 3: 'VGT_GRP_LOOP', - 4: 'VGT_GRP_POLYGON', -} -VGT_GRP_LIST = 0 -VGT_GRP_STRIP = 1 -VGT_GRP_FAN = 2 -VGT_GRP_LOOP = 3 -VGT_GRP_POLYGON = 4 -VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GROUP_CONV_SEL' -VGT_GROUP_CONV_SEL__enumvalues = { - 0: 'VGT_GRP_INDEX_16', - 1: 'VGT_GRP_INDEX_32', - 2: 'VGT_GRP_UINT_16', - 3: 'VGT_GRP_UINT_32', - 4: 'VGT_GRP_SINT_16', - 5: 'VGT_GRP_SINT_32', - 6: 'VGT_GRP_FLOAT_32', - 7: 'VGT_GRP_AUTO_PRIM', - 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', -} -VGT_GRP_INDEX_16 = 0 -VGT_GRP_INDEX_32 = 1 -VGT_GRP_UINT_16 = 2 -VGT_GRP_UINT_32 = 3 -VGT_GRP_SINT_16 = 4 -VGT_GRP_SINT_32 = 5 -VGT_GRP_FLOAT_32 = 6 -VGT_GRP_AUTO_PRIM = 7 -VGT_GRP_FIX_1_23_TO_FLOAT = 8 -VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_MODE_TYPE' -VGT_GS_MODE_TYPE__enumvalues = { - 0: 'GS_OFF', - 1: 'GS_SCENARIO_A', - 2: 'GS_SCENARIO_B', - 3: 'GS_SCENARIO_G', - 4: 'GS_SCENARIO_C', - 5: 'SPRITE_EN', -} -GS_OFF = 0 -GS_SCENARIO_A = 1 -GS_SCENARIO_B = 2 -GS_SCENARIO_G = 3 -GS_SCENARIO_C = 4 -SPRITE_EN = 5 -VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_CUT_MODE' -VGT_GS_CUT_MODE__enumvalues = { - 0: 'GS_CUT_1024', - 1: 'GS_CUT_512', - 2: 'GS_CUT_256', - 3: 'GS_CUT_128', -} -GS_CUT_1024 = 0 -GS_CUT_512 = 1 -GS_CUT_256 = 2 -GS_CUT_128 = 3 -VGT_GS_CUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_OUTPRIM_TYPE' -VGT_GS_OUTPRIM_TYPE__enumvalues = { - 0: 'POINTLIST', - 1: 'LINESTRIP', - 2: 'TRISTRIP', - 3: 'RECTLIST', -} -POINTLIST = 0 -LINESTRIP = 1 -TRISTRIP = 2 -RECTLIST = 3 -VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_CACHE_INVALID_MODE' -VGT_CACHE_INVALID_MODE__enumvalues = { - 0: 'VC_ONLY', - 1: 'TC_ONLY', - 2: 'VC_AND_TC', -} -VC_ONLY = 0 -TC_ONLY = 1 -VC_AND_TC = 2 -VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TYPE' -VGT_TESS_TYPE__enumvalues = { - 0: 'TESS_ISOLINE', - 1: 'TESS_TRIANGLE', - 2: 'TESS_QUAD', -} -TESS_ISOLINE = 0 -TESS_TRIANGLE = 1 -TESS_QUAD = 2 -VGT_TESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_PARTITION' -VGT_TESS_PARTITION__enumvalues = { - 0: 'PART_INTEGER', - 1: 'PART_POW2', - 2: 'PART_FRAC_ODD', - 3: 'PART_FRAC_EVEN', -} -PART_INTEGER = 0 -PART_POW2 = 1 -PART_FRAC_ODD = 2 -PART_FRAC_EVEN = 3 -VGT_TESS_PARTITION = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TOPOLOGY' -VGT_TESS_TOPOLOGY__enumvalues = { - 0: 'OUTPUT_POINT', - 1: 'OUTPUT_LINE', - 2: 'OUTPUT_TRIANGLE_CW', - 3: 'OUTPUT_TRIANGLE_CCW', -} -OUTPUT_POINT = 0 -OUTPUT_LINE = 1 -OUTPUT_TRIANGLE_CW = 2 -OUTPUT_TRIANGLE_CCW = 3 -VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_RDREQ_POLICY' -VGT_RDREQ_POLICY__enumvalues = { - 0: 'VGT_POLICY_LRU', - 1: 'VGT_POLICY_STREAM', - 2: 'VGT_POLICY_BYPASS', -} -VGT_POLICY_LRU = 0 -VGT_POLICY_STREAM = 1 -VGT_POLICY_BYPASS = 2 -VGT_RDREQ_POLICY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DIST_MODE' -VGT_DIST_MODE__enumvalues = { - 0: 'NO_DIST', - 1: 'PATCHES', - 2: 'DONUTS', - 3: 'TRAPEZOIDS', -} -NO_DIST = 0 -PATCHES = 1 -DONUTS = 2 -TRAPEZOIDS = 3 -VGT_DIST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ONE' -VGT_DETECT_ONE__enumvalues = { - 0: 'PRE_CLAMP_TF1', - 1: 'POST_CLAMP_TF1', - 2: 'DISABLE_TF1', -} -PRE_CLAMP_TF1 = 0 -POST_CLAMP_TF1 = 1 -DISABLE_TF1 = 2 -VGT_DETECT_ONE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ZERO' -VGT_DETECT_ZERO__enumvalues = { - 0: 'PRE_CLAMP_TF0', - 1: 'POST_CLAMP_TF0', - 2: 'DISABLE_TF0', -} -PRE_CLAMP_TF0 = 0 -POST_CLAMP_TF0 = 1 -DISABLE_TF0 = 2 -VGT_DETECT_ZERO = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_LS_EN' -VGT_STAGES_LS_EN__enumvalues = { - 0: 'LS_STAGE_OFF', - 1: 'LS_STAGE_ON', - 2: 'CS_STAGE_ON', - 3: 'RESERVED_LS', -} -LS_STAGE_OFF = 0 -LS_STAGE_ON = 1 -CS_STAGE_ON = 2 -RESERVED_LS = 3 -VGT_STAGES_LS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_HS_EN' -VGT_STAGES_HS_EN__enumvalues = { - 0: 'HS_STAGE_OFF', - 1: 'HS_STAGE_ON', -} -HS_STAGE_OFF = 0 -HS_STAGE_ON = 1 -VGT_STAGES_HS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_ES_EN' -VGT_STAGES_ES_EN__enumvalues = { - 0: 'ES_STAGE_OFF', - 1: 'ES_STAGE_DS', - 2: 'ES_STAGE_REAL', - 3: 'RESERVED_ES', -} -ES_STAGE_OFF = 0 -ES_STAGE_DS = 1 -ES_STAGE_REAL = 2 -RESERVED_ES = 3 -VGT_STAGES_ES_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_GS_EN' -VGT_STAGES_GS_EN__enumvalues = { - 0: 'GS_STAGE_OFF', - 1: 'GS_STAGE_ON', -} -GS_STAGE_OFF = 0 -GS_STAGE_ON = 1 -VGT_STAGES_GS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_VS_EN' -VGT_STAGES_VS_EN__enumvalues = { - 0: 'VS_STAGE_REAL', - 1: 'VS_STAGE_DS', - 2: 'VS_STAGE_COPY_SHADER', - 3: 'RESERVED_VS', -} -VS_STAGE_REAL = 0 -VS_STAGE_DS = 1 -VS_STAGE_COPY_SHADER = 2 -RESERVED_VS = 3 -VGT_STAGES_VS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'GE_PERFCOUNT_SELECT' -GE_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_assembler_busy', - 1: 'ge_assembler_stalled', - 2: 'ge_cm_reading_stalled', - 3: 'ge_cm_stalled_by_gog', - 4: 'ge_cm_stalled_by_gsfetch_done', - 5: 'ge_dma_busy', - 6: 'ge_dma_lat_bin_0', - 7: 'ge_dma_lat_bin_1', - 8: 'ge_dma_lat_bin_2', - 9: 'ge_dma_lat_bin_3', - 10: 'ge_dma_lat_bin_4', - 11: 'ge_dma_lat_bin_5', - 12: 'ge_dma_lat_bin_6', - 13: 'ge_dma_lat_bin_7', - 14: 'ge_dma_return', - 15: 'ge_dma_utcl1_consecutive_retry_event', - 16: 'ge_dma_utcl1_request_event', - 17: 'ge_dma_utcl1_retry_event', - 18: 'ge_dma_utcl1_stall_event', - 19: 'ge_dma_utcl1_stall_utcl2_event', - 20: 'ge_dma_utcl1_translation_hit_event', - 21: 'ge_dma_utcl1_translation_miss_event', - 22: 'ge_dma_utcl2_stall_on_trans', - 23: 'ge_dma_utcl2_trans_ack', - 24: 'ge_dma_utcl2_trans_xnack', - 25: 'ge_ds_cache_hits', - 26: 'ge_ds_prims', - 27: 'ge_es_done', - 28: 'ge_es_done_latency', - 29: 'ge_es_flush', - 30: 'ge_es_ring_high_water_mark', - 31: 'ge_es_thread_groups', - 32: 'ge_esthread_stalled_es_rb_full', - 33: 'ge_esthread_stalled_spi_bp', - 34: 'ge_esvert_stalled_es_tbl', - 35: 'ge_esvert_stalled_gs_event', - 36: 'ge_esvert_stalled_gs_tbl', - 37: 'ge_esvert_stalled_gsprim', - 38: 'ge_gea_dma_starved', - 39: 'ge_gog_busy', - 40: 'ge_gog_out_indx_stalled', - 41: 'ge_gog_out_prim_stalled', - 42: 'ge_gog_vs_tbl_stalled', - 43: 'ge_gs_cache_hits', - 44: 'ge_gs_counters_avail_stalled', - 45: 'ge_gs_done', - 46: 'ge_gs_done_latency', - 47: 'ge_gs_event_stall', - 48: 'ge_gs_issue_rtr_stalled', - 49: 'ge_gs_rb_space_avail_stalled', - 50: 'ge_gs_ring_high_water_mark', - 51: 'ge_gsprim_stalled_es_tbl', - 52: 'ge_gsprim_stalled_esvert', - 53: 'ge_gsprim_stalled_gs_event', - 54: 'ge_gsprim_stalled_gs_tbl', - 55: 'ge_gsthread_stalled', - 56: 'ge_hs_done', - 57: 'ge_hs_done_latency', - 58: 'ge_hs_done_se0', - 59: 'ge_hs_done_se1', - 60: 'ge_hs_done_se2_reserved', - 61: 'ge_hs_done_se3_reserved', - 62: 'ge_hs_tfm_stall', - 63: 'ge_hs_tgs_active_high_water_mark', - 64: 'ge_hs_thread_groups', - 65: 'ge_inside_tf_bin_0', - 66: 'ge_inside_tf_bin_1', - 67: 'ge_inside_tf_bin_2', - 68: 'ge_inside_tf_bin_3', - 69: 'ge_inside_tf_bin_4', - 70: 'ge_inside_tf_bin_5', - 71: 'ge_inside_tf_bin_6', - 72: 'ge_inside_tf_bin_7', - 73: 'ge_inside_tf_bin_8', - 74: 'ge_ls_done', - 75: 'ge_ls_done_latency', - 76: 'ge_null_patch', - 77: 'ge_pa_clipp_eop', - 78: 'ge_pa_clipp_is_event', - 79: 'ge_pa_clipp_new_vtx_vect', - 80: 'ge_pa_clipp_null_prim', - 81: 'ge_pa_clipp_send', - 82: 'ge_pa_clipp_send_not_event', - 83: 'ge_pa_clipp_stalled', - 84: 'ge_pa_clipp_starved_busy', - 85: 'ge_pa_clipp_starved_idle', - 86: 'ge_pa_clipp_valid_prim', - 87: 'ge_pa_clips_send', - 88: 'ge_pa_clips_stalled', - 89: 'ge_pa_clipv_send', - 90: 'ge_pa_clipv_stalled', - 91: 'ge_rbiu_di_fifo_stalled', - 92: 'ge_rbiu_di_fifo_starved', - 93: 'ge_rbiu_dr_fifo_stalled', - 94: 'ge_rbiu_dr_fifo_starved', - 95: 'ge_reused_es_indices', - 96: 'ge_reused_vs_indices', - 97: 'ge_sclk_core_vld', - 98: 'ge_sclk_gs_vld', - 99: 'ge_sclk_input_vld', - 100: 'ge_sclk_leg_gs_arb_vld', - 101: 'ge_sclk_ngg_vld', - 102: 'ge_sclk_reg_vld', - 103: 'ge_sclk_te11_vld', - 104: 'ge_sclk_vr_vld', - 105: 'ge_sclk_wd_te11_vld', - 106: 'ge_spi_esvert_eov', - 107: 'ge_spi_esvert_stalled', - 108: 'ge_spi_esvert_starved_busy', - 109: 'ge_spi_esvert_valid', - 110: 'ge_spi_eswave_is_event', - 111: 'ge_spi_eswave_send', - 112: 'ge_spi_gsprim_cont', - 113: 'ge_spi_gsprim_eov', - 114: 'ge_spi_gsprim_stalled', - 115: 'ge_spi_gsprim_starved_busy', - 116: 'ge_spi_gsprim_starved_idle', - 117: 'ge_spi_gsprim_valid', - 118: 'ge_spi_gssubgrp_is_event', - 119: 'ge_spi_gssubgrp_send', - 120: 'ge_spi_gswave_is_event', - 121: 'ge_spi_gswave_send', - 122: 'ge_spi_hsvert_eov', - 123: 'ge_spi_hsvert_stalled', - 124: 'ge_spi_hsvert_starved_busy', - 125: 'ge_spi_hsvert_valid', - 126: 'ge_spi_hswave_is_event', - 127: 'ge_spi_hswave_send', - 128: 'ge_spi_lsvert_eov', - 129: 'ge_spi_lsvert_stalled', - 130: 'ge_spi_lsvert_starved_busy', - 131: 'ge_spi_lsvert_starved_idle', - 132: 'ge_spi_lsvert_valid', - 133: 'ge_spi_lswave_is_event', - 134: 'ge_spi_lswave_send', - 135: 'ge_spi_vsvert_eov', - 136: 'ge_spi_vsvert_send', - 137: 'ge_spi_vsvert_stalled', - 138: 'ge_spi_vsvert_starved_busy', - 139: 'ge_spi_vsvert_starved_idle', - 140: 'ge_spi_vswave_is_event', - 141: 'ge_spi_vswave_send', - 142: 'ge_starved_on_hs_done', - 143: 'ge_stat_busy', - 144: 'ge_stat_combined_busy', - 145: 'ge_stat_no_dma_busy', - 146: 'ge_strmout_stalled', - 147: 'ge_te11_busy', - 148: 'ge_te11_starved', - 149: 'ge_tfreq_lat_bin_0', - 150: 'ge_tfreq_lat_bin_1', - 151: 'ge_tfreq_lat_bin_2', - 152: 'ge_tfreq_lat_bin_3', - 153: 'ge_tfreq_lat_bin_4', - 154: 'ge_tfreq_lat_bin_5', - 155: 'ge_tfreq_lat_bin_6', - 156: 'ge_tfreq_lat_bin_7', - 157: 'ge_tfreq_utcl1_consecutive_retry_event', - 158: 'ge_tfreq_utcl1_request_event', - 159: 'ge_tfreq_utcl1_retry_event', - 160: 'ge_tfreq_utcl1_stall_event', - 161: 'ge_tfreq_utcl1_stall_utcl2_event', - 162: 'ge_tfreq_utcl1_translation_hit_event', - 163: 'ge_tfreq_utcl1_translation_miss_event', - 164: 'ge_tfreq_utcl2_stall_on_trans', - 165: 'ge_tfreq_utcl2_trans_ack', - 166: 'ge_tfreq_utcl2_trans_xnack', - 167: 'ge_vs_cache_hits', - 168: 'ge_vs_done', - 169: 'ge_vs_pc_stall', - 170: 'ge_vs_table_high_water_mark', - 171: 'ge_vs_thread_groups', - 172: 'ge_vsvert_api_send', - 173: 'ge_vsvert_ds_send', - 174: 'ge_wait_for_es_done_stalled', - 175: 'ge_waveid_stalled', -} -ge_assembler_busy = 0 -ge_assembler_stalled = 1 -ge_cm_reading_stalled = 2 -ge_cm_stalled_by_gog = 3 -ge_cm_stalled_by_gsfetch_done = 4 -ge_dma_busy = 5 -ge_dma_lat_bin_0 = 6 -ge_dma_lat_bin_1 = 7 -ge_dma_lat_bin_2 = 8 -ge_dma_lat_bin_3 = 9 -ge_dma_lat_bin_4 = 10 -ge_dma_lat_bin_5 = 11 -ge_dma_lat_bin_6 = 12 -ge_dma_lat_bin_7 = 13 -ge_dma_return = 14 -ge_dma_utcl1_consecutive_retry_event = 15 -ge_dma_utcl1_request_event = 16 -ge_dma_utcl1_retry_event = 17 -ge_dma_utcl1_stall_event = 18 -ge_dma_utcl1_stall_utcl2_event = 19 -ge_dma_utcl1_translation_hit_event = 20 -ge_dma_utcl1_translation_miss_event = 21 -ge_dma_utcl2_stall_on_trans = 22 -ge_dma_utcl2_trans_ack = 23 -ge_dma_utcl2_trans_xnack = 24 -ge_ds_cache_hits = 25 -ge_ds_prims = 26 -ge_es_done = 27 -ge_es_done_latency = 28 -ge_es_flush = 29 -ge_es_ring_high_water_mark = 30 -ge_es_thread_groups = 31 -ge_esthread_stalled_es_rb_full = 32 -ge_esthread_stalled_spi_bp = 33 -ge_esvert_stalled_es_tbl = 34 -ge_esvert_stalled_gs_event = 35 -ge_esvert_stalled_gs_tbl = 36 -ge_esvert_stalled_gsprim = 37 -ge_gea_dma_starved = 38 -ge_gog_busy = 39 -ge_gog_out_indx_stalled = 40 -ge_gog_out_prim_stalled = 41 -ge_gog_vs_tbl_stalled = 42 -ge_gs_cache_hits = 43 -ge_gs_counters_avail_stalled = 44 -ge_gs_done = 45 -ge_gs_done_latency = 46 -ge_gs_event_stall = 47 -ge_gs_issue_rtr_stalled = 48 -ge_gs_rb_space_avail_stalled = 49 -ge_gs_ring_high_water_mark = 50 -ge_gsprim_stalled_es_tbl = 51 -ge_gsprim_stalled_esvert = 52 -ge_gsprim_stalled_gs_event = 53 -ge_gsprim_stalled_gs_tbl = 54 -ge_gsthread_stalled = 55 -ge_hs_done = 56 -ge_hs_done_latency = 57 -ge_hs_done_se0 = 58 -ge_hs_done_se1 = 59 -ge_hs_done_se2_reserved = 60 -ge_hs_done_se3_reserved = 61 -ge_hs_tfm_stall = 62 -ge_hs_tgs_active_high_water_mark = 63 -ge_hs_thread_groups = 64 -ge_inside_tf_bin_0 = 65 -ge_inside_tf_bin_1 = 66 -ge_inside_tf_bin_2 = 67 -ge_inside_tf_bin_3 = 68 -ge_inside_tf_bin_4 = 69 -ge_inside_tf_bin_5 = 70 -ge_inside_tf_bin_6 = 71 -ge_inside_tf_bin_7 = 72 -ge_inside_tf_bin_8 = 73 -ge_ls_done = 74 -ge_ls_done_latency = 75 -ge_null_patch = 76 -ge_pa_clipp_eop = 77 -ge_pa_clipp_is_event = 78 -ge_pa_clipp_new_vtx_vect = 79 -ge_pa_clipp_null_prim = 80 -ge_pa_clipp_send = 81 -ge_pa_clipp_send_not_event = 82 -ge_pa_clipp_stalled = 83 -ge_pa_clipp_starved_busy = 84 -ge_pa_clipp_starved_idle = 85 -ge_pa_clipp_valid_prim = 86 -ge_pa_clips_send = 87 -ge_pa_clips_stalled = 88 -ge_pa_clipv_send = 89 -ge_pa_clipv_stalled = 90 -ge_rbiu_di_fifo_stalled = 91 -ge_rbiu_di_fifo_starved = 92 -ge_rbiu_dr_fifo_stalled = 93 -ge_rbiu_dr_fifo_starved = 94 -ge_reused_es_indices = 95 -ge_reused_vs_indices = 96 -ge_sclk_core_vld = 97 -ge_sclk_gs_vld = 98 -ge_sclk_input_vld = 99 -ge_sclk_leg_gs_arb_vld = 100 -ge_sclk_ngg_vld = 101 -ge_sclk_reg_vld = 102 -ge_sclk_te11_vld = 103 -ge_sclk_vr_vld = 104 -ge_sclk_wd_te11_vld = 105 -ge_spi_esvert_eov = 106 -ge_spi_esvert_stalled = 107 -ge_spi_esvert_starved_busy = 108 -ge_spi_esvert_valid = 109 -ge_spi_eswave_is_event = 110 -ge_spi_eswave_send = 111 -ge_spi_gsprim_cont = 112 -ge_spi_gsprim_eov = 113 -ge_spi_gsprim_stalled = 114 -ge_spi_gsprim_starved_busy = 115 -ge_spi_gsprim_starved_idle = 116 -ge_spi_gsprim_valid = 117 -ge_spi_gssubgrp_is_event = 118 -ge_spi_gssubgrp_send = 119 -ge_spi_gswave_is_event = 120 -ge_spi_gswave_send = 121 -ge_spi_hsvert_eov = 122 -ge_spi_hsvert_stalled = 123 -ge_spi_hsvert_starved_busy = 124 -ge_spi_hsvert_valid = 125 -ge_spi_hswave_is_event = 126 -ge_spi_hswave_send = 127 -ge_spi_lsvert_eov = 128 -ge_spi_lsvert_stalled = 129 -ge_spi_lsvert_starved_busy = 130 -ge_spi_lsvert_starved_idle = 131 -ge_spi_lsvert_valid = 132 -ge_spi_lswave_is_event = 133 -ge_spi_lswave_send = 134 -ge_spi_vsvert_eov = 135 -ge_spi_vsvert_send = 136 -ge_spi_vsvert_stalled = 137 -ge_spi_vsvert_starved_busy = 138 -ge_spi_vsvert_starved_idle = 139 -ge_spi_vswave_is_event = 140 -ge_spi_vswave_send = 141 -ge_starved_on_hs_done = 142 -ge_stat_busy = 143 -ge_stat_combined_busy = 144 -ge_stat_no_dma_busy = 145 -ge_strmout_stalled = 146 -ge_te11_busy = 147 -ge_te11_starved = 148 -ge_tfreq_lat_bin_0 = 149 -ge_tfreq_lat_bin_1 = 150 -ge_tfreq_lat_bin_2 = 151 -ge_tfreq_lat_bin_3 = 152 -ge_tfreq_lat_bin_4 = 153 -ge_tfreq_lat_bin_5 = 154 -ge_tfreq_lat_bin_6 = 155 -ge_tfreq_lat_bin_7 = 156 -ge_tfreq_utcl1_consecutive_retry_event = 157 -ge_tfreq_utcl1_request_event = 158 -ge_tfreq_utcl1_retry_event = 159 -ge_tfreq_utcl1_stall_event = 160 -ge_tfreq_utcl1_stall_utcl2_event = 161 -ge_tfreq_utcl1_translation_hit_event = 162 -ge_tfreq_utcl1_translation_miss_event = 163 -ge_tfreq_utcl2_stall_on_trans = 164 -ge_tfreq_utcl2_trans_ack = 165 -ge_tfreq_utcl2_trans_xnack = 166 -ge_vs_cache_hits = 167 -ge_vs_done = 168 -ge_vs_pc_stall = 169 -ge_vs_table_high_water_mark = 170 -ge_vs_thread_groups = 171 -ge_vsvert_api_send = 172 -ge_vsvert_ds_send = 173 -ge_wait_for_es_done_stalled = 174 -ge_waveid_stalled = 175 -GE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_TYPE' -WD_IA_DRAW_TYPE__enumvalues = { - 0: 'WD_IA_DRAW_TYPE_DI_MM0', - 1: 'WD_IA_DRAW_TYPE_REG_XFER', - 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', - 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 4: 'WD_IA_DRAW_TYPE_MIN_INDX', - 5: 'WD_IA_DRAW_TYPE_MAX_INDX', - 6: 'WD_IA_DRAW_TYPE_INDX_OFF', - 7: 'WD_IA_DRAW_TYPE_IMM_DATA', -} -WD_IA_DRAW_TYPE_DI_MM0 = 0 -WD_IA_DRAW_TYPE_REG_XFER = 1 -WD_IA_DRAW_TYPE_EVENT_INIT = 2 -WD_IA_DRAW_TYPE_EVENT_ADDR = 3 -WD_IA_DRAW_TYPE_MIN_INDX = 4 -WD_IA_DRAW_TYPE_MAX_INDX = 5 -WD_IA_DRAW_TYPE_INDX_OFF = 6 -WD_IA_DRAW_TYPE_IMM_DATA = 7 -WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_REG_XFER' -WD_IA_DRAW_REG_XFER__enumvalues = { - 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', -} -WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 -WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 -WD_IA_DRAW_REG_XFER_GE_CNTL = 3 -WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_SOURCE' -WD_IA_DRAW_SOURCE__enumvalues = { - 0: 'WD_IA_DRAW_SOURCE_DMA', - 1: 'WD_IA_DRAW_SOURCE_IMMD', - 2: 'WD_IA_DRAW_SOURCE_AUTO', - 3: 'WD_IA_DRAW_SOURCE_OPAQ', -} -WD_IA_DRAW_SOURCE_DMA = 0 -WD_IA_DRAW_SOURCE_IMMD = 1 -WD_IA_DRAW_SOURCE_AUTO = 2 -WD_IA_DRAW_SOURCE_OPAQ = 3 -WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'GB_EDC_DED_MODE' -GB_EDC_DED_MODE__enumvalues = { - 0: 'GB_EDC_DED_MODE_LOG', - 1: 'GB_EDC_DED_MODE_HALT', - 2: 'GB_EDC_DED_MODE_INT_HALT', -} -GB_EDC_DED_MODE_LOG = 0 -GB_EDC_DED_MODE_HALT = 1 -GB_EDC_DED_MODE_INT_HALT = 2 -GB_EDC_DED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CHA_PERF_SEL' -CHA_PERF_SEL__enumvalues = { - 0: 'CHA_PERF_SEL_BUSY', - 1: 'CHA_PERF_SEL_STALL_CHC0', - 2: 'CHA_PERF_SEL_STALL_CHC1', - 3: 'CHA_PERF_SEL_STALL_CHC2', - 4: 'CHA_PERF_SEL_STALL_CHC3', - 5: 'CHA_PERF_SEL_STALL_CHC4', - 6: 'CHA_PERF_SEL_REQUEST_CHC0', - 7: 'CHA_PERF_SEL_REQUEST_CHC1', - 8: 'CHA_PERF_SEL_REQUEST_CHC2', - 9: 'CHA_PERF_SEL_REQUEST_CHC3', - 10: 'CHA_PERF_SEL_REQUEST_CHC4', - 11: 'CHA_PERF_SEL_REQUEST_CHC5', - 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', - 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', - 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', - 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', - 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 32: 'CHA_PERF_SEL_ARB_REQUESTS', - 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', - 39: 'CHA_PERF_SEL_CYCLE', -} -CHA_PERF_SEL_BUSY = 0 -CHA_PERF_SEL_STALL_CHC0 = 1 -CHA_PERF_SEL_STALL_CHC1 = 2 -CHA_PERF_SEL_STALL_CHC2 = 3 -CHA_PERF_SEL_STALL_CHC3 = 4 -CHA_PERF_SEL_STALL_CHC4 = 5 -CHA_PERF_SEL_REQUEST_CHC0 = 6 -CHA_PERF_SEL_REQUEST_CHC1 = 7 -CHA_PERF_SEL_REQUEST_CHC2 = 8 -CHA_PERF_SEL_REQUEST_CHC3 = 9 -CHA_PERF_SEL_REQUEST_CHC4 = 10 -CHA_PERF_SEL_REQUEST_CHC5 = 11 -CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 -CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 -CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 -CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 -CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 -CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 -CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 -CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 -CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 -CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 -CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 -CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 -CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 -CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 -CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 -CHA_PERF_SEL_ARB_REQUESTS = 32 -CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 -CHA_PERF_SEL_CYCLE = 39 -CHA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHC_PERF_SEL' -CHC_PERF_SEL__enumvalues = { - 0: 'CHC_PERF_SEL_GATE_EN1', - 1: 'CHC_PERF_SEL_GATE_EN2', - 2: 'CHC_PERF_SEL_CORE_REG_SCLK_VLD', - 3: 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', - 4: 'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', - 5: 'CHC_PERF_SEL_CYCLE', - 6: 'CHC_PERF_SEL_REQ', -} -CHC_PERF_SEL_GATE_EN1 = 0 -CHC_PERF_SEL_GATE_EN2 = 1 -CHC_PERF_SEL_CORE_REG_SCLK_VLD = 2 -CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3 -CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4 -CHC_PERF_SEL_CYCLE = 5 -CHC_PERF_SEL_REQ = 6 -CHC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHCG_PERF_SEL' -CHCG_PERF_SEL__enumvalues = { - 0: 'CHCG_PERF_SEL_GATE_EN1', - 1: 'CHCG_PERF_SEL_GATE_EN2', - 2: 'CHCG_PERF_SEL_CORE_REG_SCLK_VLD', - 3: 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', - 4: 'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', - 5: 'CHCG_PERF_SEL_CYCLE', - 6: 'CHCG_PERF_SEL_REQ', -} -CHCG_PERF_SEL_GATE_EN1 = 0 -CHCG_PERF_SEL_GATE_EN2 = 1 -CHCG_PERF_SEL_CORE_REG_SCLK_VLD = 2 -CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3 -CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4 -CHCG_PERF_SEL_CYCLE = 5 -CHCG_PERF_SEL_REQ = 6 -CHCG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1A_PERF_SEL' -GL1A_PERF_SEL__enumvalues = { - 0: 'GL1A_PERF_SEL_BUSY', - 1: 'GL1A_PERF_SEL_STALL_GL1C0', - 2: 'GL1A_PERF_SEL_STALL_GL1C1', - 3: 'GL1A_PERF_SEL_STALL_GL1C2', - 4: 'GL1A_PERF_SEL_STALL_GL1C3', - 5: 'GL1A_PERF_SEL_STALL_GL1C4', - 6: 'GL1A_PERF_SEL_REQUEST_GL1C0', - 7: 'GL1A_PERF_SEL_REQUEST_GL1C1', - 8: 'GL1A_PERF_SEL_REQUEST_GL1C2', - 9: 'GL1A_PERF_SEL_REQUEST_GL1C3', - 10: 'GL1A_PERF_SEL_REQUEST_GL1C4', - 11: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0', - 12: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1', - 13: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2', - 14: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3', - 15: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4', - 16: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C0', - 17: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C1', - 18: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C2', - 19: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C3', - 20: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C4', - 21: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0', - 22: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1', - 23: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2', - 24: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3', - 25: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4', - 26: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0', - 27: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1', - 28: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2', - 29: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3', - 30: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4', - 31: 'GL1A_PERF_SEL_ARB_REQUESTS', - 32: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 33: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 34: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 35: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 36: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 37: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4', - 38: 'GL1A_PERF_SEL_CYCLE', -} -GL1A_PERF_SEL_BUSY = 0 -GL1A_PERF_SEL_STALL_GL1C0 = 1 -GL1A_PERF_SEL_STALL_GL1C1 = 2 -GL1A_PERF_SEL_STALL_GL1C2 = 3 -GL1A_PERF_SEL_STALL_GL1C3 = 4 -GL1A_PERF_SEL_STALL_GL1C4 = 5 -GL1A_PERF_SEL_REQUEST_GL1C0 = 6 -GL1A_PERF_SEL_REQUEST_GL1C1 = 7 -GL1A_PERF_SEL_REQUEST_GL1C2 = 8 -GL1A_PERF_SEL_REQUEST_GL1C3 = 9 -GL1A_PERF_SEL_REQUEST_GL1C4 = 10 -GL1A_PERF_SEL_MEM_32B_WDS_GL1C0 = 11 -GL1A_PERF_SEL_MEM_32B_WDS_GL1C1 = 12 -GL1A_PERF_SEL_MEM_32B_WDS_GL1C2 = 13 -GL1A_PERF_SEL_MEM_32B_WDS_GL1C3 = 14 -GL1A_PERF_SEL_MEM_32B_WDS_GL1C4 = 15 -GL1A_PERF_SEL_IO_32B_WDS_GL1C0 = 16 -GL1A_PERF_SEL_IO_32B_WDS_GL1C1 = 17 -GL1A_PERF_SEL_IO_32B_WDS_GL1C2 = 18 -GL1A_PERF_SEL_IO_32B_WDS_GL1C3 = 19 -GL1A_PERF_SEL_IO_32B_WDS_GL1C4 = 20 -GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0 = 21 -GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1 = 22 -GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2 = 23 -GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3 = 24 -GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4 = 25 -GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0 = 26 -GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1 = 27 -GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2 = 28 -GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3 = 29 -GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4 = 30 -GL1A_PERF_SEL_ARB_REQUESTS = 31 -GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 32 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 33 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 34 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 35 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 36 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4 = 37 -GL1A_PERF_SEL_CYCLE = 38 -GL1A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1C_PERF_SEL' -GL1C_PERF_SEL__enumvalues = { - 0: 'GL1C_PERF_SEL_GATE_EN1', - 1: 'GL1C_PERF_SEL_GATE_EN2', - 2: 'GL1C_PERF_SEL_CORE_REG_SCLK_VLD', - 3: 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', - 4: 'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', - 5: 'GL1C_PERF_SEL_CYCLE', - 6: 'GL1C_PERF_SEL_REQ', -} -GL1C_PERF_SEL_GATE_EN1 = 0 -GL1C_PERF_SEL_GATE_EN2 = 1 -GL1C_PERF_SEL_CORE_REG_SCLK_VLD = 2 -GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3 -GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4 -GL1C_PERF_SEL_CYCLE = 5 -GL1C_PERF_SEL_REQ = 6 -GL1C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1CG_PERF_SEL' -GL1CG_PERF_SEL__enumvalues = { - 0: 'GL1CG_PERF_SEL_GATE_EN1', - 1: 'GL1CG_PERF_SEL_GATE_EN2', - 2: 'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD', - 3: 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', - 4: 'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', - 5: 'GL1CG_PERF_SEL_CYCLE', - 6: 'GL1CG_PERF_SEL_REQ', -} -GL1CG_PERF_SEL_GATE_EN1 = 0 -GL1CG_PERF_SEL_GATE_EN2 = 1 -GL1CG_PERF_SEL_CORE_REG_SCLK_VLD = 2 -GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3 -GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4 -GL1CG_PERF_SEL_CYCLE = 5 -GL1CG_PERF_SEL_REQ = 6 -GL1CG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_REQ_MODES' -TA_TC_REQ_MODES__enumvalues = { - 0: 'TA_TC_REQ_MODE_BORDER', - 1: 'TA_TC_REQ_MODE_TEX2', - 2: 'TA_TC_REQ_MODE_TEX1', - 3: 'TA_TC_REQ_MODE_TEX0', - 4: 'TA_TC_REQ_MODE_NORMAL', - 5: 'TA_TC_REQ_MODE_DWORD', - 6: 'TA_TC_REQ_MODE_BYTE', - 7: 'TA_TC_REQ_MODE_BYTE_NV', -} -TA_TC_REQ_MODE_BORDER = 0 -TA_TC_REQ_MODE_TEX2 = 1 -TA_TC_REQ_MODE_TEX1 = 2 -TA_TC_REQ_MODE_TEX0 = 3 -TA_TC_REQ_MODE_NORMAL = 4 -TA_TC_REQ_MODE_DWORD = 5 -TA_TC_REQ_MODE_BYTE = 6 -TA_TC_REQ_MODE_BYTE_NV = 7 -TA_TC_REQ_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_ADDR_MODES' -TA_TC_ADDR_MODES__enumvalues = { - 0: 'TA_TC_ADDR_MODE_DEFAULT', - 1: 'TA_TC_ADDR_MODE_COMP0', - 2: 'TA_TC_ADDR_MODE_COMP1', - 3: 'TA_TC_ADDR_MODE_COMP2', - 4: 'TA_TC_ADDR_MODE_COMP3', - 5: 'TA_TC_ADDR_MODE_UNALIGNED', - 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', -} -TA_TC_ADDR_MODE_DEFAULT = 0 -TA_TC_ADDR_MODE_COMP0 = 1 -TA_TC_ADDR_MODE_COMP1 = 2 -TA_TC_ADDR_MODE_COMP2 = 3 -TA_TC_ADDR_MODE_COMP3 = 4 -TA_TC_ADDR_MODE_UNALIGNED = 5 -TA_TC_ADDR_MODE_BORDER_COLOR = 6 -TA_TC_ADDR_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_PERFCOUNT_SEL' -TA_PERFCOUNT_SEL__enumvalues = { - 0: 'TA_PERF_SEL_NULL', - 1: 'TA_PERF_SEL_sh_fifo_busy', - 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', - 3: 'TA_PERF_SEL_sh_fifo_addr_busy', - 4: 'TA_PERF_SEL_sh_fifo_data_busy', - 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', - 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', - 7: 'TA_PERF_SEL_gradient_busy', - 8: 'TA_PERF_SEL_gradient_fifo_busy', - 9: 'TA_PERF_SEL_lod_busy', - 10: 'TA_PERF_SEL_lod_fifo_busy', - 11: 'TA_PERF_SEL_addresser_busy', - 12: 'TA_PERF_SEL_addresser_fifo_busy', - 13: 'TA_PERF_SEL_aligner_busy', - 14: 'TA_PERF_SEL_write_path_busy', - 15: 'TA_PERF_SEL_ta_busy', - 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', - 17: 'TA_PERF_SEL_sp_ta_addr_cycles', - 18: 'TA_PERF_SEL_sp_ta_data_cycles', - 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', - 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', - 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', - 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', - 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', - 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', - 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', - 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', - 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', - 28: 'TA_PERF_SEL_ta_sh_fifo_starved', - 29: 'TA_PERF_SEL_RESERVED_29', - 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', - 31: 'TA_PERF_SEL_sh_fifo_data_cycles', - 32: 'TA_PERF_SEL_total_wavefronts', - 33: 'TA_PERF_SEL_gradient_cycles', - 34: 'TA_PERF_SEL_walker_cycles', - 35: 'TA_PERF_SEL_aligner_cycles', - 36: 'TA_PERF_SEL_image_wavefronts', - 37: 'TA_PERF_SEL_image_read_wavefronts', - 38: 'TA_PERF_SEL_image_write_wavefronts', - 39: 'TA_PERF_SEL_image_atomic_wavefronts', - 40: 'TA_PERF_SEL_image_total_cycles', - 41: 'TA_PERF_SEL_RESERVED_41', - 42: 'TA_PERF_SEL_RESERVED_42', - 43: 'TA_PERF_SEL_RESERVED_43', - 44: 'TA_PERF_SEL_buffer_wavefronts', - 45: 'TA_PERF_SEL_buffer_read_wavefronts', - 46: 'TA_PERF_SEL_buffer_write_wavefronts', - 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', - 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', - 49: 'TA_PERF_SEL_buffer_total_cycles', - 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', - 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', - 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', - 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', - 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', - 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 58: 'TA_PERF_SEL_addresser_stalled_cycles', - 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 60: 'TA_PERF_SEL_aniso_stalled_cycles', - 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 62: 'TA_PERF_SEL_deriv_stalled_cycles', - 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 64: 'TA_PERF_SEL_color_1_cycle_pixels', - 65: 'TA_PERF_SEL_color_2_cycle_pixels', - 66: 'TA_PERF_SEL_color_3_cycle_pixels', - 67: 'TA_PERF_SEL_color_4_cycle_pixels', - 68: 'TA_PERF_SEL_mip_1_cycle_pixels', - 69: 'TA_PERF_SEL_mip_2_cycle_pixels', - 70: 'TA_PERF_SEL_vol_1_cycle_pixels', - 71: 'TA_PERF_SEL_vol_2_cycle_pixels', - 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', - 73: 'TA_PERF_SEL_mipmap_lod_0_samples', - 74: 'TA_PERF_SEL_mipmap_lod_1_samples', - 75: 'TA_PERF_SEL_mipmap_lod_2_samples', - 76: 'TA_PERF_SEL_mipmap_lod_3_samples', - 77: 'TA_PERF_SEL_mipmap_lod_4_samples', - 78: 'TA_PERF_SEL_mipmap_lod_5_samples', - 79: 'TA_PERF_SEL_mipmap_lod_6_samples', - 80: 'TA_PERF_SEL_mipmap_lod_7_samples', - 81: 'TA_PERF_SEL_mipmap_lod_8_samples', - 82: 'TA_PERF_SEL_mipmap_lod_9_samples', - 83: 'TA_PERF_SEL_mipmap_lod_10_samples', - 84: 'TA_PERF_SEL_mipmap_lod_11_samples', - 85: 'TA_PERF_SEL_mipmap_lod_12_samples', - 86: 'TA_PERF_SEL_mipmap_lod_13_samples', - 87: 'TA_PERF_SEL_mipmap_lod_14_samples', - 88: 'TA_PERF_SEL_mipmap_invalid_samples', - 89: 'TA_PERF_SEL_aniso_1_cycle_quads', - 90: 'TA_PERF_SEL_aniso_2_cycle_quads', - 91: 'TA_PERF_SEL_aniso_4_cycle_quads', - 92: 'TA_PERF_SEL_aniso_6_cycle_quads', - 93: 'TA_PERF_SEL_aniso_8_cycle_quads', - 94: 'TA_PERF_SEL_aniso_10_cycle_quads', - 95: 'TA_PERF_SEL_aniso_12_cycle_quads', - 96: 'TA_PERF_SEL_aniso_14_cycle_quads', - 97: 'TA_PERF_SEL_aniso_16_cycle_quads', - 98: 'TA_PERF_SEL_write_path_input_cycles', - 99: 'TA_PERF_SEL_write_path_output_cycles', - 100: 'TA_PERF_SEL_flat_wavefronts', - 101: 'TA_PERF_SEL_flat_read_wavefronts', - 102: 'TA_PERF_SEL_flat_write_wavefronts', - 103: 'TA_PERF_SEL_flat_atomic_wavefronts', - 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', - 105: 'TA_PERF_SEL_reg_sclk_vld', - 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', - 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', - 111: 'TA_PERF_SEL_xnack_on_phase0', - 112: 'TA_PERF_SEL_xnack_on_phase1', - 113: 'TA_PERF_SEL_xnack_on_phase2', - 114: 'TA_PERF_SEL_xnack_on_phase3', - 115: 'TA_PERF_SEL_first_xnack_on_phase0', - 116: 'TA_PERF_SEL_first_xnack_on_phase1', - 117: 'TA_PERF_SEL_first_xnack_on_phase2', - 118: 'TA_PERF_SEL_first_xnack_on_phase3', -} -TA_PERF_SEL_NULL = 0 -TA_PERF_SEL_sh_fifo_busy = 1 -TA_PERF_SEL_sh_fifo_cmd_busy = 2 -TA_PERF_SEL_sh_fifo_addr_busy = 3 -TA_PERF_SEL_sh_fifo_data_busy = 4 -TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 -TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 -TA_PERF_SEL_gradient_busy = 7 -TA_PERF_SEL_gradient_fifo_busy = 8 -TA_PERF_SEL_lod_busy = 9 -TA_PERF_SEL_lod_fifo_busy = 10 -TA_PERF_SEL_addresser_busy = 11 -TA_PERF_SEL_addresser_fifo_busy = 12 -TA_PERF_SEL_aligner_busy = 13 -TA_PERF_SEL_write_path_busy = 14 -TA_PERF_SEL_ta_busy = 15 -TA_PERF_SEL_sq_ta_cmd_cycles = 16 -TA_PERF_SEL_sp_ta_addr_cycles = 17 -TA_PERF_SEL_sp_ta_data_cycles = 18 -TA_PERF_SEL_ta_fa_data_state_cycles = 19 -TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 -TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 -TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 -TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 -TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 -TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 -TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 -TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 -TA_PERF_SEL_ta_sh_fifo_starved = 28 -TA_PERF_SEL_RESERVED_29 = 29 -TA_PERF_SEL_sh_fifo_addr_cycles = 30 -TA_PERF_SEL_sh_fifo_data_cycles = 31 -TA_PERF_SEL_total_wavefronts = 32 -TA_PERF_SEL_gradient_cycles = 33 -TA_PERF_SEL_walker_cycles = 34 -TA_PERF_SEL_aligner_cycles = 35 -TA_PERF_SEL_image_wavefronts = 36 -TA_PERF_SEL_image_read_wavefronts = 37 -TA_PERF_SEL_image_write_wavefronts = 38 -TA_PERF_SEL_image_atomic_wavefronts = 39 -TA_PERF_SEL_image_total_cycles = 40 -TA_PERF_SEL_RESERVED_41 = 41 -TA_PERF_SEL_RESERVED_42 = 42 -TA_PERF_SEL_RESERVED_43 = 43 -TA_PERF_SEL_buffer_wavefronts = 44 -TA_PERF_SEL_buffer_read_wavefronts = 45 -TA_PERF_SEL_buffer_write_wavefronts = 46 -TA_PERF_SEL_buffer_atomic_wavefronts = 47 -TA_PERF_SEL_buffer_coalescable_wavefronts = 48 -TA_PERF_SEL_buffer_total_cycles = 49 -TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 -TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 -TA_PERF_SEL_buffer_coalesced_read_cycles = 52 -TA_PERF_SEL_buffer_coalesced_write_cycles = 53 -TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 -TA_PERF_SEL_addr_stalled_by_td_cycles = 55 -TA_PERF_SEL_data_stalled_by_tc_cycles = 56 -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 -TA_PERF_SEL_addresser_stalled_cycles = 58 -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 -TA_PERF_SEL_aniso_stalled_cycles = 60 -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 -TA_PERF_SEL_deriv_stalled_cycles = 62 -TA_PERF_SEL_aniso_gt1_cycle_quads = 63 -TA_PERF_SEL_color_1_cycle_pixels = 64 -TA_PERF_SEL_color_2_cycle_pixels = 65 -TA_PERF_SEL_color_3_cycle_pixels = 66 -TA_PERF_SEL_color_4_cycle_pixels = 67 -TA_PERF_SEL_mip_1_cycle_pixels = 68 -TA_PERF_SEL_mip_2_cycle_pixels = 69 -TA_PERF_SEL_vol_1_cycle_pixels = 70 -TA_PERF_SEL_vol_2_cycle_pixels = 71 -TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 -TA_PERF_SEL_mipmap_lod_0_samples = 73 -TA_PERF_SEL_mipmap_lod_1_samples = 74 -TA_PERF_SEL_mipmap_lod_2_samples = 75 -TA_PERF_SEL_mipmap_lod_3_samples = 76 -TA_PERF_SEL_mipmap_lod_4_samples = 77 -TA_PERF_SEL_mipmap_lod_5_samples = 78 -TA_PERF_SEL_mipmap_lod_6_samples = 79 -TA_PERF_SEL_mipmap_lod_7_samples = 80 -TA_PERF_SEL_mipmap_lod_8_samples = 81 -TA_PERF_SEL_mipmap_lod_9_samples = 82 -TA_PERF_SEL_mipmap_lod_10_samples = 83 -TA_PERF_SEL_mipmap_lod_11_samples = 84 -TA_PERF_SEL_mipmap_lod_12_samples = 85 -TA_PERF_SEL_mipmap_lod_13_samples = 86 -TA_PERF_SEL_mipmap_lod_14_samples = 87 -TA_PERF_SEL_mipmap_invalid_samples = 88 -TA_PERF_SEL_aniso_1_cycle_quads = 89 -TA_PERF_SEL_aniso_2_cycle_quads = 90 -TA_PERF_SEL_aniso_4_cycle_quads = 91 -TA_PERF_SEL_aniso_6_cycle_quads = 92 -TA_PERF_SEL_aniso_8_cycle_quads = 93 -TA_PERF_SEL_aniso_10_cycle_quads = 94 -TA_PERF_SEL_aniso_12_cycle_quads = 95 -TA_PERF_SEL_aniso_14_cycle_quads = 96 -TA_PERF_SEL_aniso_16_cycle_quads = 97 -TA_PERF_SEL_write_path_input_cycles = 98 -TA_PERF_SEL_write_path_output_cycles = 99 -TA_PERF_SEL_flat_wavefronts = 100 -TA_PERF_SEL_flat_read_wavefronts = 101 -TA_PERF_SEL_flat_write_wavefronts = 102 -TA_PERF_SEL_flat_atomic_wavefronts = 103 -TA_PERF_SEL_flat_coalesceable_wavefronts = 104 -TA_PERF_SEL_reg_sclk_vld = 105 -TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 -TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 -TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 -TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 -TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 -TA_PERF_SEL_xnack_on_phase0 = 111 -TA_PERF_SEL_xnack_on_phase1 = 112 -TA_PERF_SEL_xnack_on_phase2 = 113 -TA_PERF_SEL_xnack_on_phase3 = 114 -TA_PERF_SEL_first_xnack_on_phase0 = 115 -TA_PERF_SEL_first_xnack_on_phase1 = 116 -TA_PERF_SEL_first_xnack_on_phase2 = 117 -TA_PERF_SEL_first_xnack_on_phase3 = 118 -TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TD_PERFCOUNT_SEL' -TD_PERFCOUNT_SEL__enumvalues = { - 0: 'TD_PERF_SEL_none', - 1: 'TD_PERF_SEL_td_busy', - 2: 'TD_PERF_SEL_input_busy', - 3: 'TD_PERF_SEL_sampler_lerp_busy', - 4: 'TD_PERF_SEL_sampler_out_busy', - 5: 'TD_PERF_SEL_nofilter_busy', - 6: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 7: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 8: 'TD_PERF_SEL_RESERVED_8', - 9: 'TD_PERF_SEL_core_state_rams_read', - 10: 'TD_PERF_SEL_weight_data_rams_read', - 11: 'TD_PERF_SEL_reference_data_rams_read', - 12: 'TD_PERF_SEL_tc_td_data_fifo_full', - 13: 'TD_PERF_SEL_tc_td_ram_fifo_full', - 14: 'TD_PERF_SEL_input_state_fifo_full', - 15: 'TD_PERF_SEL_ta_data_stall', - 16: 'TD_PERF_SEL_tc_data_stall', - 17: 'TD_PERF_SEL_tc_ram_stall', - 18: 'TD_PERF_SEL_lds_stall', - 19: 'TD_PERF_SEL_sampler_pkr_full', - 20: 'TD_PERF_SEL_nofilter_pkr_full', - 21: 'TD_PERF_SEL_RESERVED_21', - 22: 'TD_PERF_SEL_gather4_wavefront', - 23: 'TD_PERF_SEL_gather4h_wavefront', - 24: 'TD_PERF_SEL_gather4h_packed_wavefront', - 25: 'TD_PERF_SEL_gather8h_packed_wavefront', - 26: 'TD_PERF_SEL_sample_c_wavefront', - 27: 'TD_PERF_SEL_load_wavefront', - 28: 'TD_PERF_SEL_store_wavefront', - 29: 'TD_PERF_SEL_ldfptr_wavefront', - 30: 'TD_PERF_SEL_write_ack_wavefront', - 31: 'TD_PERF_SEL_d16_en_wavefront', - 32: 'TD_PERF_SEL_bypassLerp_wavefront', - 33: 'TD_PERF_SEL_min_max_filter_wavefront', - 34: 'TD_PERF_SEL_one_comp_wavefront', - 35: 'TD_PERF_SEL_two_comp_wavefront', - 36: 'TD_PERF_SEL_three_comp_wavefront', - 37: 'TD_PERF_SEL_four_comp_wavefront', - 38: 'TD_PERF_SEL_user_defined_border', - 39: 'TD_PERF_SEL_white_border', - 40: 'TD_PERF_SEL_opaque_black_border', - 41: 'TD_PERF_SEL_lod_warn_from_ta', - 42: 'TD_PERF_SEL_wavefront_dest_is_lds', - 43: 'TD_PERF_SEL_td_cycling_of_nofilter_instr', - 44: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr', - 45: 'TD_PERF_SEL_out_of_order_instr', - 46: 'TD_PERF_SEL_total_num_instr', - 47: 'TD_PERF_SEL_mixmode_instruction', - 48: 'TD_PERF_SEL_mixmode_resource', - 49: 'TD_PERF_SEL_status_packet', - 50: 'TD_PERF_SEL_address_cmd_poison', - 51: 'TD_PERF_SEL_data_poison', - 52: 'TD_PERF_SEL_done_scoreboard_not_empty', - 53: 'TD_PERF_SEL_done_scoreboard_is_full', - 54: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 55: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 56: 'TD_PERF_SEL_nofilter_formatters_turned_off', - 57: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 58: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', -} -TD_PERF_SEL_none = 0 -TD_PERF_SEL_td_busy = 1 -TD_PERF_SEL_input_busy = 2 -TD_PERF_SEL_sampler_lerp_busy = 3 -TD_PERF_SEL_sampler_out_busy = 4 -TD_PERF_SEL_nofilter_busy = 5 -TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 6 -TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 7 -TD_PERF_SEL_RESERVED_8 = 8 -TD_PERF_SEL_core_state_rams_read = 9 -TD_PERF_SEL_weight_data_rams_read = 10 -TD_PERF_SEL_reference_data_rams_read = 11 -TD_PERF_SEL_tc_td_data_fifo_full = 12 -TD_PERF_SEL_tc_td_ram_fifo_full = 13 -TD_PERF_SEL_input_state_fifo_full = 14 -TD_PERF_SEL_ta_data_stall = 15 -TD_PERF_SEL_tc_data_stall = 16 -TD_PERF_SEL_tc_ram_stall = 17 -TD_PERF_SEL_lds_stall = 18 -TD_PERF_SEL_sampler_pkr_full = 19 -TD_PERF_SEL_nofilter_pkr_full = 20 -TD_PERF_SEL_RESERVED_21 = 21 -TD_PERF_SEL_gather4_wavefront = 22 -TD_PERF_SEL_gather4h_wavefront = 23 -TD_PERF_SEL_gather4h_packed_wavefront = 24 -TD_PERF_SEL_gather8h_packed_wavefront = 25 -TD_PERF_SEL_sample_c_wavefront = 26 -TD_PERF_SEL_load_wavefront = 27 -TD_PERF_SEL_store_wavefront = 28 -TD_PERF_SEL_ldfptr_wavefront = 29 -TD_PERF_SEL_write_ack_wavefront = 30 -TD_PERF_SEL_d16_en_wavefront = 31 -TD_PERF_SEL_bypassLerp_wavefront = 32 -TD_PERF_SEL_min_max_filter_wavefront = 33 -TD_PERF_SEL_one_comp_wavefront = 34 -TD_PERF_SEL_two_comp_wavefront = 35 -TD_PERF_SEL_three_comp_wavefront = 36 -TD_PERF_SEL_four_comp_wavefront = 37 -TD_PERF_SEL_user_defined_border = 38 -TD_PERF_SEL_white_border = 39 -TD_PERF_SEL_opaque_black_border = 40 -TD_PERF_SEL_lod_warn_from_ta = 41 -TD_PERF_SEL_wavefront_dest_is_lds = 42 -TD_PERF_SEL_td_cycling_of_nofilter_instr = 43 -TD_PERF_SEL_tc_cycling_of_nofilter_instr = 44 -TD_PERF_SEL_out_of_order_instr = 45 -TD_PERF_SEL_total_num_instr = 46 -TD_PERF_SEL_mixmode_instruction = 47 -TD_PERF_SEL_mixmode_resource = 48 -TD_PERF_SEL_status_packet = 49 -TD_PERF_SEL_address_cmd_poison = 50 -TD_PERF_SEL_data_poison = 51 -TD_PERF_SEL_done_scoreboard_not_empty = 52 -TD_PERF_SEL_done_scoreboard_is_full = 53 -TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 54 -TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 55 -TD_PERF_SEL_nofilter_formatters_turned_off = 56 -TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 57 -TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 58 -TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_PERFCOUNT_SELECT' -TCP_PERFCOUNT_SELECT__enumvalues = { - 0: 'TCP_PERF_SEL_GATE_EN1', - 1: 'TCP_PERF_SEL_GATE_EN2', - 2: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', - 3: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', - 4: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', - 5: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', - 6: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', - 7: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', - 8: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', - 9: 'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES', - 10: 'TCP_PERF_SEL_LOD_STALL_CYCLES', - 11: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', - 12: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', - 13: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', - 14: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', - 15: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 16: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', - 17: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', - 18: 'TCP_PERF_SEL_TCR_RDRET_STALL', - 19: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', - 20: 'TCP_PERF_SEL_HOLE_READ_STALL', - 21: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', - 22: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', - 23: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', - 24: 'TCP_PERF_SEL_POWER_STALL', - 25: 'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL', - 26: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', - 27: 'TCP_PERF_SEL_TA_TCP_STATE_READ', - 28: 'TCP_PERF_SEL_TOTAL_ACCESSES', - 29: 'TCP_PERF_SEL_TOTAL_READ', - 30: 'TCP_PERF_SEL_TOTAL_NON_READ', - 31: 'TCP_PERF_SEL_TOTAL_WRITE', - 32: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', - 33: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', - 34: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', - 35: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', - 36: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', - 37: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', - 38: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', - 39: 'TCP_PERF_SEL_TOTAL_WBINVL1', - 40: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', - 41: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', - 42: 'TCP_PERF_SEL_SHOOTDOWN', - 43: 'TCP_PERF_SEL_UTCL0_REQUEST', - 44: 'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS', - 45: 'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT', - 46: 'TCP_PERF_SEL_UTCL0_PERMISSION_MISS', - 47: 'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 48: 'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 49: 'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 50: 'TCP_PERF_SEL_UTCL0_LFIFO_FULL', - 51: 'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 52: 'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 53: 'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 54: 'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT', - 55: 'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 56: 'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES', - 57: 'TCP_PERF_SEL_TAGRAM0_REQ', - 58: 'TCP_PERF_SEL_TAGRAM1_REQ', - 59: 'TCP_PERF_SEL_TAGRAM2_REQ', - 60: 'TCP_PERF_SEL_TAGRAM3_REQ', - 61: 'TCP_PERF_SEL_TCP_LATENCY', - 62: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', - 63: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', - 64: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', - 65: 'TCP_PERF_SEL_TCC_READ_REQ', - 66: 'TCP_PERF_SEL_TCC_WRITE_REQ', - 67: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', - 68: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', - 69: 'TCP_PERF_SEL_TCC_LRU_REQ', - 70: 'TCP_PERF_SEL_TCC_STREAM_REQ', - 71: 'TCP_PERF_SEL_TCC_NC_READ_REQ', - 72: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', - 73: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', - 74: 'TCP_PERF_SEL_TCC_UC_READ_REQ', - 75: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', - 76: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', - 77: 'TCP_PERF_SEL_TCC_CC_READ_REQ', - 78: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', - 79: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', - 80: 'TCP_PERF_SEL_TCC_DCC_REQ', - 81: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 82: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 83: 'TCP_PERF_SEL_GL1_REQ_READ', - 84: 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY', - 85: 'TCP_PERF_SEL_GL1_REQ_WRITE', - 86: 'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY', - 87: 'TCP_PERF_SEL_REQ_MISS_TAGRAM0', - 88: 'TCP_PERF_SEL_REQ_MISS_TAGRAM1', - 89: 'TCP_PERF_SEL_REQ_MISS_TAGRAM2', - 90: 'TCP_PERF_SEL_REQ_MISS_TAGRAM3', - 91: 'TCP_PERF_SEL_TA_REQ', - 92: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 93: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 94: 'TCP_PERF_SEL_TA_REQ_READ', - 95: 'TCP_PERF_SEL_TA_REQ_WRITE', - 96: 'TCP_PERF_SEL_TA_REQ_STATE_READ', -} -TCP_PERF_SEL_GATE_EN1 = 0 -TCP_PERF_SEL_GATE_EN2 = 1 -TCP_PERF_SEL_CORE_REG_SCLK_VLD = 2 -TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 3 -TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 4 -TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 5 -TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 6 -TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 7 -TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 8 -TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 9 -TCP_PERF_SEL_LOD_STALL_CYCLES = 10 -TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 11 -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 12 -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 13 -TCP_PERF_SEL_ALLOC_STALL_CYCLES = 14 -TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 15 -TCP_PERF_SEL_LFIFO_STALL_CYCLES = 16 -TCP_PERF_SEL_RFIFO_STALL_CYCLES = 17 -TCP_PERF_SEL_TCR_RDRET_STALL = 18 -TCP_PERF_SEL_WRITE_CONFLICT_STALL = 19 -TCP_PERF_SEL_HOLE_READ_STALL = 20 -TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 21 -TCP_PERF_SEL_PENDING_STALL_CYCLES = 22 -TCP_PERF_SEL_READFIFO_STALL_CYCLES = 23 -TCP_PERF_SEL_POWER_STALL = 24 -TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL = 25 -TCP_PERF_SEL_TC_TA_XNACK_STALL = 26 -TCP_PERF_SEL_TA_TCP_STATE_READ = 27 -TCP_PERF_SEL_TOTAL_ACCESSES = 28 -TCP_PERF_SEL_TOTAL_READ = 29 -TCP_PERF_SEL_TOTAL_NON_READ = 30 -TCP_PERF_SEL_TOTAL_WRITE = 31 -TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 32 -TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 33 -TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 34 -TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 35 -TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 36 -TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 37 -TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 38 -TCP_PERF_SEL_TOTAL_WBINVL1 = 39 -TCP_PERF_SEL_CP_TCP_INVALIDATE = 40 -TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 41 -TCP_PERF_SEL_SHOOTDOWN = 42 -TCP_PERF_SEL_UTCL0_REQUEST = 43 -TCP_PERF_SEL_UTCL0_TRANSLATION_MISS = 44 -TCP_PERF_SEL_UTCL0_TRANSLATION_HIT = 45 -TCP_PERF_SEL_UTCL0_PERMISSION_MISS = 46 -TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 47 -TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 48 -TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS = 49 -TCP_PERF_SEL_UTCL0_LFIFO_FULL = 50 -TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 51 -TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS = 52 -TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 53 -TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT = 54 -TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 55 -TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 56 -TCP_PERF_SEL_TAGRAM0_REQ = 57 -TCP_PERF_SEL_TAGRAM1_REQ = 58 -TCP_PERF_SEL_TAGRAM2_REQ = 59 -TCP_PERF_SEL_TAGRAM3_REQ = 60 -TCP_PERF_SEL_TCP_LATENCY = 61 -TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 62 -TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 63 -TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 64 -TCP_PERF_SEL_TCC_READ_REQ = 65 -TCP_PERF_SEL_TCC_WRITE_REQ = 66 -TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 67 -TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 68 -TCP_PERF_SEL_TCC_LRU_REQ = 69 -TCP_PERF_SEL_TCC_STREAM_REQ = 70 -TCP_PERF_SEL_TCC_NC_READ_REQ = 71 -TCP_PERF_SEL_TCC_NC_WRITE_REQ = 72 -TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 73 -TCP_PERF_SEL_TCC_UC_READ_REQ = 74 -TCP_PERF_SEL_TCC_UC_WRITE_REQ = 75 -TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 76 -TCP_PERF_SEL_TCC_CC_READ_REQ = 77 -TCP_PERF_SEL_TCC_CC_WRITE_REQ = 78 -TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 79 -TCP_PERF_SEL_TCC_DCC_REQ = 80 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 81 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 82 -TCP_PERF_SEL_GL1_REQ_READ = 83 -TCP_PERF_SEL_GL1_REQ_READ_LATENCY = 84 -TCP_PERF_SEL_GL1_REQ_WRITE = 85 -TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY = 86 -TCP_PERF_SEL_REQ_MISS_TAGRAM0 = 87 -TCP_PERF_SEL_REQ_MISS_TAGRAM1 = 88 -TCP_PERF_SEL_REQ_MISS_TAGRAM2 = 89 -TCP_PERF_SEL_REQ_MISS_TAGRAM3 = 90 -TCP_PERF_SEL_TA_REQ = 91 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 92 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 93 -TCP_PERF_SEL_TA_REQ_READ = 94 -TCP_PERF_SEL_TA_REQ_WRITE = 95 -TCP_PERF_SEL_TA_REQ_STATE_READ = 96 -TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_POLICIES' -TCP_CACHE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_POLICY_MISS_LRU', - 1: 'TCP_CACHE_POLICY_MISS_EVICT', - 2: 'TCP_CACHE_POLICY_HIT_LRU', - 3: 'TCP_CACHE_POLICY_HIT_EVICT', -} -TCP_CACHE_POLICY_MISS_LRU = 0 -TCP_CACHE_POLICY_MISS_EVICT = 1 -TCP_CACHE_POLICY_HIT_LRU = 2 -TCP_CACHE_POLICY_HIT_EVICT = 3 -TCP_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_STORE_POLICIES' -TCP_CACHE_STORE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', - 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', -} -TCP_CACHE_STORE_POLICY_WT_LRU = 0 -TCP_CACHE_STORE_POLICY_WT_EVICT = 1 -TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WATCH_MODES' -TCP_WATCH_MODES__enumvalues = { - 0: 'TCP_WATCH_MODE_READ', - 1: 'TCP_WATCH_MODE_NONREAD', - 2: 'TCP_WATCH_MODE_ATOMIC', - 3: 'TCP_WATCH_MODE_ALL', -} -TCP_WATCH_MODE_READ = 0 -TCP_WATCH_MODE_NONREAD = 1 -TCP_WATCH_MODE_ATOMIC = 2 -TCP_WATCH_MODE_ALL = 3 -TCP_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_DATA_SEL' -TCP_DSM_DATA_SEL__enumvalues = { - 0: 'TCP_DSM_DISABLE', - 1: 'TCP_DSM_SEL0', - 2: 'TCP_DSM_SEL1', - 3: 'TCP_DSM_SEL_BOTH', -} -TCP_DSM_DISABLE = 0 -TCP_DSM_SEL0 = 1 -TCP_DSM_SEL1 = 2 -TCP_DSM_SEL_BOTH = 3 -TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_SINGLE_WRITE' -TCP_DSM_SINGLE_WRITE__enumvalues = { - 0: 'TCP_DSM_SINGLE_WRITE_DIS', - 1: 'TCP_DSM_SINGLE_WRITE_EN', -} -TCP_DSM_SINGLE_WRITE_DIS = 0 -TCP_DSM_SINGLE_WRITE_EN = 1 -TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_INJECT_SEL' -TCP_DSM_INJECT_SEL__enumvalues = { - 0: 'TCP_DSM_INJECT_SEL0', - 1: 'TCP_DSM_INJECT_SEL1', - 2: 'TCP_DSM_INJECT_SEL2', - 3: 'TCP_DSM_INJECT_SEL3', -} -TCP_DSM_INJECT_SEL0 = 0 -TCP_DSM_INJECT_SEL1 = 1 -TCP_DSM_INJECT_SEL2 = 2 -TCP_DSM_INJECT_SEL3 = 3 -TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_OPCODE_TYPE' -TCP_OPCODE_TYPE__enumvalues = { - 0: 'TCP_OPCODE_READ', - 1: 'TCP_OPCODE_WRITE', - 2: 'TCP_OPCODE_ATOMIC', - 3: 'TCP_OPCODE_WBINVL1', - 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', - 5: 'TCP_OPCODE_GATHERH', -} -TCP_OPCODE_READ = 0 -TCP_OPCODE_WRITE = 1 -TCP_OPCODE_ATOMIC = 2 -TCP_OPCODE_WBINVL1 = 3 -TCP_OPCODE_ATOMIC_CMPSWAP = 4 -TCP_OPCODE_GATHERH = 5 -TCP_OPCODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GL2C_PERF_SEL' -GL2C_PERF_SEL__enumvalues = { - 0: 'GL2C_PERF_SEL_NONE', - 1: 'GL2C_PERF_SEL_CYCLE', - 2: 'GL2C_PERF_SEL_BUSY', - 3: 'GL2C_PERF_SEL_REQ', - 4: 'GL2C_PERF_SEL_VOL_REQ', - 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', - 6: 'GL2C_PERF_SEL_READ', - 7: 'GL2C_PERF_SEL_WRITE', - 8: 'GL2C_PERF_SEL_ATOMIC', - 9: 'GL2C_PERF_SEL_NOP_ACK', - 10: 'GL2C_PERF_SEL_NOP_RTN0', - 11: 'GL2C_PERF_SEL_PROBE', - 12: 'GL2C_PERF_SEL_PROBE_ALL', - 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', - 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', - 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', - 16: 'GL2C_PERF_SEL_CLIENT0_REQ', - 17: 'GL2C_PERF_SEL_CLIENT1_REQ', - 18: 'GL2C_PERF_SEL_CLIENT2_REQ', - 19: 'GL2C_PERF_SEL_CLIENT3_REQ', - 20: 'GL2C_PERF_SEL_CLIENT4_REQ', - 21: 'GL2C_PERF_SEL_CLIENT5_REQ', - 22: 'GL2C_PERF_SEL_CLIENT6_REQ', - 23: 'GL2C_PERF_SEL_CLIENT7_REQ', - 24: 'GL2C_PERF_SEL_C_RW_S_REQ', - 25: 'GL2C_PERF_SEL_C_RW_US_REQ', - 26: 'GL2C_PERF_SEL_C_RO_S_REQ', - 27: 'GL2C_PERF_SEL_C_RO_US_REQ', - 28: 'GL2C_PERF_SEL_UC_REQ', - 29: 'GL2C_PERF_SEL_LRU_REQ', - 30: 'GL2C_PERF_SEL_STREAM_REQ', - 31: 'GL2C_PERF_SEL_BYPASS_REQ', - 32: 'GL2C_PERF_SEL_NOA_REQ', - 33: 'GL2C_PERF_SEL_SHARED_REQ', - 34: 'GL2C_PERF_SEL_HIT', - 35: 'GL2C_PERF_SEL_MISS', - 36: 'GL2C_PERF_SEL_FULL_HIT', - 37: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', - 38: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 39: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', - 40: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', - 41: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', - 42: 'GL2C_PERF_SEL_UNCACHED_WRITE', - 43: 'GL2C_PERF_SEL_WRITEBACK', - 44: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 45: 'GL2C_PERF_SEL_EVICT', - 46: 'GL2C_PERF_SEL_NORMAL_EVICT', - 47: 'GL2C_PERF_SEL_PROBE_EVICT', - 48: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', - 49: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO', - 50: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP', - 51: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 52: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 59: 'GL2C_PERF_SEL_READ_32_REQ', - 60: 'GL2C_PERF_SEL_READ_64_REQ', - 61: 'GL2C_PERF_SEL_READ_128_REQ', - 62: 'GL2C_PERF_SEL_WRITE_32_REQ', - 63: 'GL2C_PERF_SEL_WRITE_64_REQ', - 64: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 65: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 66: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 67: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 68: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 69: 'GL2C_PERF_SEL_MC_WRREQ', - 70: 'GL2C_PERF_SEL_EA_WRREQ_64B', - 71: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 72: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', - 73: 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 74: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 75: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 76: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 77: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 78: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', - 79: 'GL2C_PERF_SEL_EA_ATOMIC', - 80: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', - 81: 'GL2C_PERF_SEL_MC_RDREQ', - 82: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 83: 'GL2C_PERF_SEL_EA_RDREQ_32B', - 84: 'GL2C_PERF_SEL_EA_RDREQ_64B', - 85: 'GL2C_PERF_SEL_EA_RDREQ_96B', - 86: 'GL2C_PERF_SEL_EA_RDREQ_128B', - 87: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 88: 'GL2C_PERF_SEL_EA_RD_MDC_32B', - 89: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 90: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 91: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 92: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 93: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', - 94: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', - 95: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 96: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 97: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 98: 'GL2C_PERF_SEL_ONION_READ', - 99: 'GL2C_PERF_SEL_ONION_WRITE', - 100: 'GL2C_PERF_SEL_IO_READ', - 101: 'GL2C_PERF_SEL_IO_WRITE', - 102: 'GL2C_PERF_SEL_GARLIC_READ', - 103: 'GL2C_PERF_SEL_GARLIC_WRITE', - 104: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 105: 'GL2C_PERF_SEL_SRC_FIFO_FULL', - 106: 'GL2C_PERF_SEL_TAG_STALL', - 107: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 108: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 109: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 110: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 111: 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 112: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 113: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 114: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', - 115: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', - 116: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 117: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 118: 'GL2C_PERF_SEL_BUBBLE', - 119: 'GL2C_PERF_SEL_IB_REQ', - 120: 'GL2C_PERF_SEL_IB_STALL', - 121: 'GL2C_PERF_SEL_IB_TAG_STALL', - 122: 'GL2C_PERF_SEL_IB_CM_STALL', - 123: 'GL2C_PERF_SEL_RETURN_ACK', - 124: 'GL2C_PERF_SEL_RETURN_DATA', - 125: 'GL2C_PERF_SEL_EA_RDRET_NACK', - 126: 'GL2C_PERF_SEL_EA_WRRET_NACK', - 127: 'GL2C_PERF_SEL_GL2A_LEVEL', - 128: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 129: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 130: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 131: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 132: 'GL2C_PERF_SEL_GCR_INV', - 133: 'GL2C_PERF_SEL_GCR_WB', - 134: 'GL2C_PERF_SEL_GCR_DISCARD', - 135: 'GL2C_PERF_SEL_GCR_RANGE', - 136: 'GL2C_PERF_SEL_GCR_ALL', - 137: 'GL2C_PERF_SEL_GCR_VOL', - 138: 'GL2C_PERF_SEL_GCR_UNSHARED', - 139: 'GL2C_PERF_SEL_GCR_MDC_INV', - 140: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 141: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 142: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 143: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', - 144: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', - 145: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 146: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', - 147: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 148: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 149: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 150: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 151: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 152: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 153: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', - 155: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 156: 'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT', - 157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', - 158: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 159: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 160: 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 161: 'GL2C_PERF_SEL_MDC_INV_METADATA', - 162: 'GL2C_PERF_SEL_MDC_REQ', - 163: 'GL2C_PERF_SEL_MDC_LEVEL', - 164: 'GL2C_PERF_SEL_MDC_TAG_HIT', - 165: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 166: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 167: 'GL2C_PERF_SEL_MDC_TAG_STALL', - 168: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 169: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 170: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 171: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', - 172: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 173: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 174: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 175: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', - 176: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 177: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', - 178: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 179: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', - 180: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 181: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 182: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 183: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 184: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 185: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 186: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 187: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 188: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 189: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 190: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', - 191: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 192: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 193: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 194: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 195: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 196: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 197: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 198: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 199: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 200: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', - 201: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 202: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', - 203: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 204: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 205: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 206: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 207: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 208: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 209: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 210: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 211: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 212: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', - 213: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 214: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', - 215: 'GL2C_PERF_SEL_CM_NOOP_REQ', - 216: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 217: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 218: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 219: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 220: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 221: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 222: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 223: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 224: 'GL2C_PERF_SEL_CM_RVF_FULL', - 225: 'GL2C_PERF_SEL_CM_SDR_FULL', - 226: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 227: 'GL2C_PERF_SEL_CM_DCC_STALL', -} -GL2C_PERF_SEL_NONE = 0 -GL2C_PERF_SEL_CYCLE = 1 -GL2C_PERF_SEL_BUSY = 2 -GL2C_PERF_SEL_REQ = 3 -GL2C_PERF_SEL_VOL_REQ = 4 -GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 -GL2C_PERF_SEL_READ = 6 -GL2C_PERF_SEL_WRITE = 7 -GL2C_PERF_SEL_ATOMIC = 8 -GL2C_PERF_SEL_NOP_ACK = 9 -GL2C_PERF_SEL_NOP_RTN0 = 10 -GL2C_PERF_SEL_PROBE = 11 -GL2C_PERF_SEL_PROBE_ALL = 12 -GL2C_PERF_SEL_INTERNAL_PROBE = 13 -GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 -GL2C_PERF_SEL_METADATA_READ_REQ = 15 -GL2C_PERF_SEL_CLIENT0_REQ = 16 -GL2C_PERF_SEL_CLIENT1_REQ = 17 -GL2C_PERF_SEL_CLIENT2_REQ = 18 -GL2C_PERF_SEL_CLIENT3_REQ = 19 -GL2C_PERF_SEL_CLIENT4_REQ = 20 -GL2C_PERF_SEL_CLIENT5_REQ = 21 -GL2C_PERF_SEL_CLIENT6_REQ = 22 -GL2C_PERF_SEL_CLIENT7_REQ = 23 -GL2C_PERF_SEL_C_RW_S_REQ = 24 -GL2C_PERF_SEL_C_RW_US_REQ = 25 -GL2C_PERF_SEL_C_RO_S_REQ = 26 -GL2C_PERF_SEL_C_RO_US_REQ = 27 -GL2C_PERF_SEL_UC_REQ = 28 -GL2C_PERF_SEL_LRU_REQ = 29 -GL2C_PERF_SEL_STREAM_REQ = 30 -GL2C_PERF_SEL_BYPASS_REQ = 31 -GL2C_PERF_SEL_NOA_REQ = 32 -GL2C_PERF_SEL_SHARED_REQ = 33 -GL2C_PERF_SEL_HIT = 34 -GL2C_PERF_SEL_MISS = 35 -GL2C_PERF_SEL_FULL_HIT = 36 -GL2C_PERF_SEL_PARTIAL_32B_HIT = 37 -GL2C_PERF_SEL_PARTIAL_64B_HIT = 38 -GL2C_PERF_SEL_PARTIAL_96B_HIT = 39 -GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 40 -GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 41 -GL2C_PERF_SEL_UNCACHED_WRITE = 42 -GL2C_PERF_SEL_WRITEBACK = 43 -GL2C_PERF_SEL_NORMAL_WRITEBACK = 44 -GL2C_PERF_SEL_EVICT = 45 -GL2C_PERF_SEL_NORMAL_EVICT = 46 -GL2C_PERF_SEL_PROBE_EVICT = 47 -GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 48 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO = 49 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP = 50 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 51 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 52 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 53 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 54 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 55 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 56 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 57 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 58 -GL2C_PERF_SEL_READ_32_REQ = 59 -GL2C_PERF_SEL_READ_64_REQ = 60 -GL2C_PERF_SEL_READ_128_REQ = 61 -GL2C_PERF_SEL_WRITE_32_REQ = 62 -GL2C_PERF_SEL_WRITE_64_REQ = 63 -GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 64 -GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 65 -GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 66 -GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 67 -GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 68 -GL2C_PERF_SEL_MC_WRREQ = 69 -GL2C_PERF_SEL_EA_WRREQ_64B = 70 -GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 71 -GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 72 -GL2C_PERF_SEL_MC_WRREQ_STALL = 73 -GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 74 -GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 75 -GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 76 -GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 77 -GL2C_PERF_SEL_MC_WRREQ_LEVEL = 78 -GL2C_PERF_SEL_EA_ATOMIC = 79 -GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 80 -GL2C_PERF_SEL_MC_RDREQ = 81 -GL2C_PERF_SEL_EA_RDREQ_SPLIT = 82 -GL2C_PERF_SEL_EA_RDREQ_32B = 83 -GL2C_PERF_SEL_EA_RDREQ_64B = 84 -GL2C_PERF_SEL_EA_RDREQ_96B = 85 -GL2C_PERF_SEL_EA_RDREQ_128B = 86 -GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 87 -GL2C_PERF_SEL_EA_RD_MDC_32B = 88 -GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 89 -GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 90 -GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 91 -GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 92 -GL2C_PERF_SEL_MC_RDREQ_LEVEL = 93 -GL2C_PERF_SEL_EA_RDREQ_DRAM = 94 -GL2C_PERF_SEL_EA_WRREQ_DRAM = 95 -GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 96 -GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 97 -GL2C_PERF_SEL_ONION_READ = 98 -GL2C_PERF_SEL_ONION_WRITE = 99 -GL2C_PERF_SEL_IO_READ = 100 -GL2C_PERF_SEL_IO_WRITE = 101 -GL2C_PERF_SEL_GARLIC_READ = 102 -GL2C_PERF_SEL_GARLIC_WRITE = 103 -GL2C_PERF_SEL_LATENCY_FIFO_FULL = 104 -GL2C_PERF_SEL_SRC_FIFO_FULL = 105 -GL2C_PERF_SEL_TAG_STALL = 106 -GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 107 -GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 108 -GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 109 -GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 110 -GL2C_PERF_SEL_TAG_PROBE_STALL = 111 -GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 112 -GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 113 -GL2C_PERF_SEL_TAG_READ_DST_STALL = 114 -GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 115 -GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 116 -GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 117 -GL2C_PERF_SEL_BUBBLE = 118 -GL2C_PERF_SEL_IB_REQ = 119 -GL2C_PERF_SEL_IB_STALL = 120 -GL2C_PERF_SEL_IB_TAG_STALL = 121 -GL2C_PERF_SEL_IB_CM_STALL = 122 -GL2C_PERF_SEL_RETURN_ACK = 123 -GL2C_PERF_SEL_RETURN_DATA = 124 -GL2C_PERF_SEL_EA_RDRET_NACK = 125 -GL2C_PERF_SEL_EA_WRRET_NACK = 126 -GL2C_PERF_SEL_GL2A_LEVEL = 127 -GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 128 -GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 129 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 130 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 131 -GL2C_PERF_SEL_GCR_INV = 132 -GL2C_PERF_SEL_GCR_WB = 133 -GL2C_PERF_SEL_GCR_DISCARD = 134 -GL2C_PERF_SEL_GCR_RANGE = 135 -GL2C_PERF_SEL_GCR_ALL = 136 -GL2C_PERF_SEL_GCR_VOL = 137 -GL2C_PERF_SEL_GCR_UNSHARED = 138 -GL2C_PERF_SEL_GCR_MDC_INV = 139 -GL2C_PERF_SEL_GCR_GL2_INV_ALL = 140 -GL2C_PERF_SEL_GCR_GL2_WB_ALL = 141 -GL2C_PERF_SEL_GCR_MDC_INV_ALL = 142 -GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 143 -GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 144 -GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 145 -GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 146 -GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 147 -GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 148 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 149 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 150 -GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 151 -GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 152 -GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 153 -GL2C_PERF_SEL_GCR_INVL2_VOL_START = 154 -GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 155 -GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT = 156 -GL2C_PERF_SEL_GCR_WBL2_VOL_START = 157 -GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 158 -GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 159 -GL2C_PERF_SEL_GCR_WBINVL2_START = 160 -GL2C_PERF_SEL_MDC_INV_METADATA = 161 -GL2C_PERF_SEL_MDC_REQ = 162 -GL2C_PERF_SEL_MDC_LEVEL = 163 -GL2C_PERF_SEL_MDC_TAG_HIT = 164 -GL2C_PERF_SEL_MDC_SECTOR_HIT = 165 -GL2C_PERF_SEL_MDC_SECTOR_MISS = 166 -GL2C_PERF_SEL_MDC_TAG_STALL = 167 -GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 168 -GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 169 -GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 170 -GL2C_PERF_SEL_CM_CHANNEL0_REQ = 171 -GL2C_PERF_SEL_CM_CHANNEL1_REQ = 172 -GL2C_PERF_SEL_CM_CHANNEL2_REQ = 173 -GL2C_PERF_SEL_CM_CHANNEL3_REQ = 174 -GL2C_PERF_SEL_CM_CHANNEL4_REQ = 175 -GL2C_PERF_SEL_CM_CHANNEL5_REQ = 176 -GL2C_PERF_SEL_CM_CHANNEL6_REQ = 177 -GL2C_PERF_SEL_CM_CHANNEL7_REQ = 178 -GL2C_PERF_SEL_CM_CHANNEL8_REQ = 179 -GL2C_PERF_SEL_CM_CHANNEL9_REQ = 180 -GL2C_PERF_SEL_CM_CHANNEL10_REQ = 181 -GL2C_PERF_SEL_CM_CHANNEL11_REQ = 182 -GL2C_PERF_SEL_CM_CHANNEL12_REQ = 183 -GL2C_PERF_SEL_CM_CHANNEL13_REQ = 184 -GL2C_PERF_SEL_CM_CHANNEL14_REQ = 185 -GL2C_PERF_SEL_CM_CHANNEL15_REQ = 186 -GL2C_PERF_SEL_CM_CHANNEL16_REQ = 187 -GL2C_PERF_SEL_CM_CHANNEL17_REQ = 188 -GL2C_PERF_SEL_CM_CHANNEL18_REQ = 189 -GL2C_PERF_SEL_CM_CHANNEL19_REQ = 190 -GL2C_PERF_SEL_CM_CHANNEL20_REQ = 191 -GL2C_PERF_SEL_CM_CHANNEL21_REQ = 192 -GL2C_PERF_SEL_CM_CHANNEL22_REQ = 193 -GL2C_PERF_SEL_CM_CHANNEL23_REQ = 194 -GL2C_PERF_SEL_CM_CHANNEL24_REQ = 195 -GL2C_PERF_SEL_CM_CHANNEL25_REQ = 196 -GL2C_PERF_SEL_CM_CHANNEL26_REQ = 197 -GL2C_PERF_SEL_CM_CHANNEL27_REQ = 198 -GL2C_PERF_SEL_CM_CHANNEL28_REQ = 199 -GL2C_PERF_SEL_CM_CHANNEL29_REQ = 200 -GL2C_PERF_SEL_CM_CHANNEL30_REQ = 201 -GL2C_PERF_SEL_CM_CHANNEL31_REQ = 202 -GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 203 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 204 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 205 -GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 206 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 207 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 208 -GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 209 -GL2C_PERF_SEL_CM_COMP_READ_REQ = 210 -GL2C_PERF_SEL_CM_READ_BACK_REQ = 211 -GL2C_PERF_SEL_CM_METADATA_WR_REQ = 212 -GL2C_PERF_SEL_CM_WR_ACK_REQ = 213 -GL2C_PERF_SEL_CM_NO_ACK_REQ = 214 -GL2C_PERF_SEL_CM_NOOP_REQ = 215 -GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 216 -GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 217 -GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 218 -GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 219 -GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 220 -GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 221 -GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 222 -GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 223 -GL2C_PERF_SEL_CM_RVF_FULL = 224 -GL2C_PERF_SEL_CM_SDR_FULL = 225 -GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 226 -GL2C_PERF_SEL_CM_DCC_STALL = 227 -GL2C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2A_PERF_SEL' -GL2A_PERF_SEL__enumvalues = { - 0: 'GL2A_PERF_SEL_NONE', - 1: 'GL2A_PERF_SEL_CYCLE', - 2: 'GL2A_PERF_SEL_BUSY', - 3: 'GL2A_PERF_SEL_REQ_GL2C0', - 4: 'GL2A_PERF_SEL_REQ_GL2C1', - 5: 'GL2A_PERF_SEL_REQ_GL2C2', - 6: 'GL2A_PERF_SEL_REQ_GL2C3', - 7: 'GL2A_PERF_SEL_REQ_GL2C4', - 8: 'GL2A_PERF_SEL_REQ_GL2C5', - 9: 'GL2A_PERF_SEL_REQ_GL2C6', - 10: 'GL2A_PERF_SEL_REQ_GL2C7', - 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', - 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', - 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', - 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', - 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', - 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', - 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', - 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', - 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', - 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', - 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', - 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', - 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 43: 'GL2A_PERF_SEL_RTN_CLIENT0', - 44: 'GL2A_PERF_SEL_RTN_CLIENT1', - 45: 'GL2A_PERF_SEL_RTN_CLIENT2', - 46: 'GL2A_PERF_SEL_RTN_CLIENT3', - 47: 'GL2A_PERF_SEL_RTN_CLIENT4', - 48: 'GL2A_PERF_SEL_RTN_CLIENT5', - 49: 'GL2A_PERF_SEL_RTN_CLIENT6', - 50: 'GL2A_PERF_SEL_RTN_CLIENT7', - 51: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 52: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 53: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 54: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 55: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 56: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 57: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 58: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', -} -GL2A_PERF_SEL_NONE = 0 -GL2A_PERF_SEL_CYCLE = 1 -GL2A_PERF_SEL_BUSY = 2 -GL2A_PERF_SEL_REQ_GL2C0 = 3 -GL2A_PERF_SEL_REQ_GL2C1 = 4 -GL2A_PERF_SEL_REQ_GL2C2 = 5 -GL2A_PERF_SEL_REQ_GL2C3 = 6 -GL2A_PERF_SEL_REQ_GL2C4 = 7 -GL2A_PERF_SEL_REQ_GL2C5 = 8 -GL2A_PERF_SEL_REQ_GL2C6 = 9 -GL2A_PERF_SEL_REQ_GL2C7 = 10 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 -GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 -GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 -GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 -GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 -GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 -GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 -GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 -GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 -GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 -GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 -GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 -GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 -GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 -GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 -GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 -GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 -GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 -GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 -GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 -GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 -GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 -GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 -GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 -GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 -GL2A_PERF_SEL_RTN_CLIENT0 = 43 -GL2A_PERF_SEL_RTN_CLIENT1 = 44 -GL2A_PERF_SEL_RTN_CLIENT2 = 45 -GL2A_PERF_SEL_RTN_CLIENT3 = 46 -GL2A_PERF_SEL_RTN_CLIENT4 = 47 -GL2A_PERF_SEL_RTN_CLIENT5 = 48 -GL2A_PERF_SEL_RTN_CLIENT6 = 49 -GL2A_PERF_SEL_RTN_CLIENT7 = 50 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 51 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 52 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 53 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 54 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 55 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 56 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 57 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 58 -GL2A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_PERF_SEL' -GRBM_PERF_SEL__enumvalues = { - 0: 'GRBM_PERF_SEL_COUNT', - 1: 'GRBM_PERF_SEL_USER_DEFINED', - 2: 'GRBM_PERF_SEL_GUI_ACTIVE', - 3: 'GRBM_PERF_SEL_CP_BUSY', - 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', - 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', - 6: 'GRBM_PERF_SEL_CB_BUSY', - 7: 'GRBM_PERF_SEL_DB_BUSY', - 8: 'GRBM_PERF_SEL_PA_BUSY', - 9: 'GRBM_PERF_SEL_SC_BUSY', - 10: 'GRBM_PERF_SEL_RESERVED_6', - 11: 'GRBM_PERF_SEL_SPI_BUSY', - 12: 'GRBM_PERF_SEL_SX_BUSY', - 13: 'GRBM_PERF_SEL_TA_BUSY', - 14: 'GRBM_PERF_SEL_CB_CLEAN', - 15: 'GRBM_PERF_SEL_DB_CLEAN', - 16: 'GRBM_PERF_SEL_RESERVED_5', - 17: 'GRBM_PERF_SEL_RESERVED_9', - 18: 'GRBM_PERF_SEL_RESERVED_4', - 19: 'GRBM_PERF_SEL_RESERVED_3', - 20: 'GRBM_PERF_SEL_RESERVED_2', - 21: 'GRBM_PERF_SEL_RESERVED_1', - 22: 'GRBM_PERF_SEL_RESERVED_0', - 23: 'GRBM_PERF_SEL_RESERVED_8', - 24: 'GRBM_PERF_SEL_RESERVED_7', - 25: 'GRBM_PERF_SEL_GDS_BUSY', - 26: 'GRBM_PERF_SEL_BCI_BUSY', - 27: 'GRBM_PERF_SEL_RLC_BUSY', - 28: 'GRBM_PERF_SEL_TCP_BUSY', - 29: 'GRBM_PERF_SEL_CPG_BUSY', - 30: 'GRBM_PERF_SEL_CPC_BUSY', - 31: 'GRBM_PERF_SEL_CPF_BUSY', - 32: 'GRBM_PERF_SEL_GE_BUSY', - 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 34: 'GRBM_PERF_SEL_UTCL2_BUSY', - 35: 'GRBM_PERF_SEL_EA_BUSY', - 36: 'GRBM_PERF_SEL_RMI_BUSY', - 37: 'GRBM_PERF_SEL_CPAXI_BUSY', - 39: 'GRBM_PERF_SEL_UTCL1_BUSY', - 40: 'GRBM_PERF_SEL_GL2CC_BUSY', - 41: 'GRBM_PERF_SEL_SDMA_BUSY', - 42: 'GRBM_PERF_SEL_CH_BUSY', - 43: 'GRBM_PERF_SEL_PH_BUSY', - 44: 'GRBM_PERF_SEL_PMM_BUSY', - 45: 'GRBM_PERF_SEL_GUS_BUSY', - 46: 'GRBM_PERF_SEL_GL1CC_BUSY', -} -GRBM_PERF_SEL_COUNT = 0 -GRBM_PERF_SEL_USER_DEFINED = 1 -GRBM_PERF_SEL_GUI_ACTIVE = 2 -GRBM_PERF_SEL_CP_BUSY = 3 -GRBM_PERF_SEL_CP_COHER_BUSY = 4 -GRBM_PERF_SEL_CP_DMA_BUSY = 5 -GRBM_PERF_SEL_CB_BUSY = 6 -GRBM_PERF_SEL_DB_BUSY = 7 -GRBM_PERF_SEL_PA_BUSY = 8 -GRBM_PERF_SEL_SC_BUSY = 9 -GRBM_PERF_SEL_RESERVED_6 = 10 -GRBM_PERF_SEL_SPI_BUSY = 11 -GRBM_PERF_SEL_SX_BUSY = 12 -GRBM_PERF_SEL_TA_BUSY = 13 -GRBM_PERF_SEL_CB_CLEAN = 14 -GRBM_PERF_SEL_DB_CLEAN = 15 -GRBM_PERF_SEL_RESERVED_5 = 16 -GRBM_PERF_SEL_RESERVED_9 = 17 -GRBM_PERF_SEL_RESERVED_4 = 18 -GRBM_PERF_SEL_RESERVED_3 = 19 -GRBM_PERF_SEL_RESERVED_2 = 20 -GRBM_PERF_SEL_RESERVED_1 = 21 -GRBM_PERF_SEL_RESERVED_0 = 22 -GRBM_PERF_SEL_RESERVED_8 = 23 -GRBM_PERF_SEL_RESERVED_7 = 24 -GRBM_PERF_SEL_GDS_BUSY = 25 -GRBM_PERF_SEL_BCI_BUSY = 26 -GRBM_PERF_SEL_RLC_BUSY = 27 -GRBM_PERF_SEL_TCP_BUSY = 28 -GRBM_PERF_SEL_CPG_BUSY = 29 -GRBM_PERF_SEL_CPC_BUSY = 30 -GRBM_PERF_SEL_CPF_BUSY = 31 -GRBM_PERF_SEL_GE_BUSY = 32 -GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 -GRBM_PERF_SEL_UTCL2_BUSY = 34 -GRBM_PERF_SEL_EA_BUSY = 35 -GRBM_PERF_SEL_RMI_BUSY = 36 -GRBM_PERF_SEL_CPAXI_BUSY = 37 -GRBM_PERF_SEL_UTCL1_BUSY = 39 -GRBM_PERF_SEL_GL2CC_BUSY = 40 -GRBM_PERF_SEL_SDMA_BUSY = 41 -GRBM_PERF_SEL_CH_BUSY = 42 -GRBM_PERF_SEL_PH_BUSY = 43 -GRBM_PERF_SEL_PMM_BUSY = 44 -GRBM_PERF_SEL_GUS_BUSY = 45 -GRBM_PERF_SEL_GL1CC_BUSY = 46 -GRBM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE0_PERF_SEL' -GRBM_SE0_PERF_SEL__enumvalues = { - 0: 'GRBM_SE0_PERF_SEL_COUNT', - 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE0_PERF_SEL_RESERVED_2', - 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', -} -GRBM_SE0_PERF_SEL_COUNT = 0 -GRBM_SE0_PERF_SEL_USER_DEFINED = 1 -GRBM_SE0_PERF_SEL_CB_BUSY = 2 -GRBM_SE0_PERF_SEL_DB_BUSY = 3 -GRBM_SE0_PERF_SEL_SC_BUSY = 4 -GRBM_SE0_PERF_SEL_RESERVED_1 = 5 -GRBM_SE0_PERF_SEL_SPI_BUSY = 6 -GRBM_SE0_PERF_SEL_SX_BUSY = 7 -GRBM_SE0_PERF_SEL_TA_BUSY = 8 -GRBM_SE0_PERF_SEL_CB_CLEAN = 9 -GRBM_SE0_PERF_SEL_DB_CLEAN = 10 -GRBM_SE0_PERF_SEL_RESERVED_0 = 11 -GRBM_SE0_PERF_SEL_PA_BUSY = 12 -GRBM_SE0_PERF_SEL_RESERVED_2 = 13 -GRBM_SE0_PERF_SEL_BCI_BUSY = 14 -GRBM_SE0_PERF_SEL_RMI_BUSY = 15 -GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE0_PERF_SEL_TCP_BUSY = 17 -GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE1_PERF_SEL' -GRBM_SE1_PERF_SEL__enumvalues = { - 0: 'GRBM_SE1_PERF_SEL_COUNT', - 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE1_PERF_SEL_RESERVED_2', - 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', -} -GRBM_SE1_PERF_SEL_COUNT = 0 -GRBM_SE1_PERF_SEL_USER_DEFINED = 1 -GRBM_SE1_PERF_SEL_CB_BUSY = 2 -GRBM_SE1_PERF_SEL_DB_BUSY = 3 -GRBM_SE1_PERF_SEL_SC_BUSY = 4 -GRBM_SE1_PERF_SEL_RESERVED_1 = 5 -GRBM_SE1_PERF_SEL_SPI_BUSY = 6 -GRBM_SE1_PERF_SEL_SX_BUSY = 7 -GRBM_SE1_PERF_SEL_TA_BUSY = 8 -GRBM_SE1_PERF_SEL_CB_CLEAN = 9 -GRBM_SE1_PERF_SEL_DB_CLEAN = 10 -GRBM_SE1_PERF_SEL_RESERVED_0 = 11 -GRBM_SE1_PERF_SEL_PA_BUSY = 12 -GRBM_SE1_PERF_SEL_RESERVED_2 = 13 -GRBM_SE1_PERF_SEL_BCI_BUSY = 14 -GRBM_SE1_PERF_SEL_RMI_BUSY = 15 -GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE1_PERF_SEL_TCP_BUSY = 17 -GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE2_PERF_SEL' -GRBM_SE2_PERF_SEL__enumvalues = { - 0: 'GRBM_SE2_PERF_SEL_COUNT', - 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE2_PERF_SEL_RESERVED_2', - 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', -} -GRBM_SE2_PERF_SEL_COUNT = 0 -GRBM_SE2_PERF_SEL_USER_DEFINED = 1 -GRBM_SE2_PERF_SEL_CB_BUSY = 2 -GRBM_SE2_PERF_SEL_DB_BUSY = 3 -GRBM_SE2_PERF_SEL_SC_BUSY = 4 -GRBM_SE2_PERF_SEL_RESERVED_1 = 5 -GRBM_SE2_PERF_SEL_SPI_BUSY = 6 -GRBM_SE2_PERF_SEL_SX_BUSY = 7 -GRBM_SE2_PERF_SEL_TA_BUSY = 8 -GRBM_SE2_PERF_SEL_CB_CLEAN = 9 -GRBM_SE2_PERF_SEL_DB_CLEAN = 10 -GRBM_SE2_PERF_SEL_RESERVED_0 = 11 -GRBM_SE2_PERF_SEL_PA_BUSY = 12 -GRBM_SE2_PERF_SEL_RESERVED_2 = 13 -GRBM_SE2_PERF_SEL_BCI_BUSY = 14 -GRBM_SE2_PERF_SEL_RMI_BUSY = 15 -GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE2_PERF_SEL_TCP_BUSY = 17 -GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE3_PERF_SEL' -GRBM_SE3_PERF_SEL__enumvalues = { - 0: 'GRBM_SE3_PERF_SEL_COUNT', - 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE3_PERF_SEL_RESERVED_2', - 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', -} -GRBM_SE3_PERF_SEL_COUNT = 0 -GRBM_SE3_PERF_SEL_USER_DEFINED = 1 -GRBM_SE3_PERF_SEL_CB_BUSY = 2 -GRBM_SE3_PERF_SEL_DB_BUSY = 3 -GRBM_SE3_PERF_SEL_SC_BUSY = 4 -GRBM_SE3_PERF_SEL_RESERVED_1 = 5 -GRBM_SE3_PERF_SEL_SPI_BUSY = 6 -GRBM_SE3_PERF_SEL_SX_BUSY = 7 -GRBM_SE3_PERF_SEL_TA_BUSY = 8 -GRBM_SE3_PERF_SEL_CB_CLEAN = 9 -GRBM_SE3_PERF_SEL_DB_CLEAN = 10 -GRBM_SE3_PERF_SEL_RESERVED_0 = 11 -GRBM_SE3_PERF_SEL_PA_BUSY = 12 -GRBM_SE3_PERF_SEL_RESERVED_2 = 13 -GRBM_SE3_PERF_SEL_BCI_BUSY = 14 -GRBM_SE3_PERF_SEL_RMI_BUSY = 15 -GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE3_PERF_SEL_TCP_BUSY = 17 -GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_RING_ID' -CP_RING_ID__enumvalues = { - 0: 'RINGID0', - 1: 'RINGID1', - 2: 'RINGID2', - 3: 'RINGID3', -} -RINGID0 = 0 -RINGID1 = 1 -RINGID2 = 2 -RINGID3 = 3 -CP_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PIPE_ID' -CP_PIPE_ID__enumvalues = { - 0: 'PIPE_ID0', - 1: 'PIPE_ID1', - 2: 'PIPE_ID2', - 3: 'PIPE_ID3', -} -PIPE_ID0 = 0 -PIPE_ID1 = 1 -PIPE_ID2 = 2 -PIPE_ID3 = 3 -CP_PIPE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ME_ID' -CP_ME_ID__enumvalues = { - 0: 'ME_ID0', - 1: 'ME_ID1', - 2: 'ME_ID2', - 3: 'ME_ID3', -} -ME_ID0 = 0 -ME_ID1 = 1 -ME_ID2 = 2 -ME_ID3 = 3 -CP_ME_ID = ctypes.c_uint32 # enum - -# values for enumeration 'SPM_PERFMON_STATE' -SPM_PERFMON_STATE__enumvalues = { - 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'STRM_PERFMON_STATE_START_COUNTING', - 2: 'STRM_PERFMON_STATE_STOP_COUNTING', - 3: 'STRM_PERFMON_STATE_RESERVED_3', - 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 -STRM_PERFMON_STATE_START_COUNTING = 1 -STRM_PERFMON_STATE_STOP_COUNTING = 2 -STRM_PERFMON_STATE_RESERVED_3 = 3 -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -SPM_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_STATE' -CP_PERFMON_STATE__enumvalues = { - 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'CP_PERFMON_STATE_START_COUNTING', - 2: 'CP_PERFMON_STATE_STOP_COUNTING', - 3: 'CP_PERFMON_STATE_RESERVED_3', - 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -CP_PERFMON_STATE_DISABLE_AND_RESET = 0 -CP_PERFMON_STATE_START_COUNTING = 1 -CP_PERFMON_STATE_STOP_COUNTING = 2 -CP_PERFMON_STATE_RESERVED_3 = 3 -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -CP_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_ENABLE_MODE' -CP_PERFMON_ENABLE_MODE__enumvalues = { - 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', - 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', -} -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 -CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNT_SEL' -CPG_PERFCOUNT_SEL__enumvalues = { - 0: 'CPG_PERF_SEL_ALWAYS_COUNT', - 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', - 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', - 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', - 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', - 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', - 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', - 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', - 53: 'CPG_PERF_SEL_CPG_STAT_STALL', - 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', - 56: 'CPF_PERF_SEL_CPG_TCIU_STALL', - 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', - 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', - 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', - 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', - 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', - 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', -} -CPG_PERF_SEL_ALWAYS_COUNT = 0 -CPG_PERF_SEL_RBIU_FIFO_FULL = 1 -CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 -CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 -CPG_PERF_SEL_ME_PARSER_BUSY = 5 -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 -CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 -CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 -CPG_PERF_SEL_REGISTER_CLK_VALID = 33 -CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 -CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 -CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 -CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 -CPG_PERF_SEL_CPG_STAT_BUSY = 51 -CPG_PERF_SEL_CPG_STAT_IDLE = 52 -CPG_PERF_SEL_CPG_STAT_STALL = 53 -CPG_PERF_SEL_CPG_TCIU_BUSY = 54 -CPG_PERF_SEL_CPG_TCIU_IDLE = 55 -CPF_PERF_SEL_CPG_TCIU_STALL = 56 -CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 -CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 -CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 -CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 -CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 -CPG_PERF_SEL_CPG_GCRIU_STALL = 62 -CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 -CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 -CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 -CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 -CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 -CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 -CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 -CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 -CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 -CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 -CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNT_SEL' -CPF_PERFCOUNT_SEL__enumvalues = { - 0: 'CPF_PERF_SEL_ALWAYS_COUNT', - 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', - 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', - 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', - 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', - 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND', - 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SEND', - 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', - 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', - 26: 'CPF_PERF_SEL_CPF_STAT_STALL', - 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', - 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', - 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', - 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', - 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', - 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', - 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', -} -CPF_PERF_SEL_ALWAYS_COUNT = 0 -CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 -CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 -CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 -CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 -CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 -CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND = 15 -CPF_PERF_SEL_GUS_READ_REQUEST_SEND = 16 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 -CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 -CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 -CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 -CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 -CPF_PERF_SEL_CPF_STAT_BUSY = 24 -CPF_PERF_SEL_CPF_STAT_IDLE = 25 -CPF_PERF_SEL_CPF_STAT_STALL = 26 -CPF_PERF_SEL_CPF_TCIU_BUSY = 27 -CPF_PERF_SEL_CPF_TCIU_IDLE = 28 -CPF_PERF_SEL_CPF_TCIU_STALL = 29 -CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 -CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 -CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 -CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 -CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 -CPF_PERF_SEL_CPF_GCRIU_STALL = 35 -CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 -CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 -CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 -CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_PERFCOUNT_SEL' -CPC_PERFCOUNT_SEL__enumvalues = { - 0: 'CPC_PERF_SEL_ALWAYS_COUNT', - 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', - 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', - 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', - 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', - 27: 'CPC_PERF_SEL_CPC_STAT_STALL', - 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', - 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', - 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', - 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', - 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', -} -CPC_PERF_SEL_ALWAYS_COUNT = 0 -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 -CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 -CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 -CPC_PERF_SEL_CPC_STAT_BUSY = 25 -CPC_PERF_SEL_CPC_STAT_IDLE = 26 -CPC_PERF_SEL_CPC_STAT_STALL = 27 -CPC_PERF_SEL_CPC_TCIU_BUSY = 28 -CPC_PERF_SEL_CPC_TCIU_IDLE = 29 -CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 -CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 -CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 -CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 -CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 -CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 -CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 -CPC_PERF_SEL_CPC_GCRIU_STALL = 37 -CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 -CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 -CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 -CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 -CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 -CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' -CP_ALPHA_TAG_RAM_SEL__enumvalues = { - 0: 'CPG_TAG_RAM', - 1: 'CPC_TAG_RAM', - 2: 'CPF_TAG_RAM', - 3: 'RSV_TAG_RAM', -} -CPG_TAG_RAM = 0 -CPC_TAG_RAM = 1 -CPF_TAG_RAM = 2 -RSV_TAG_RAM = 3 -CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' -CPF_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPF_PERFWINDOW_SEL_CSF', - 1: 'CPF_PERFWINDOW_SEL_HQD1', - 2: 'CPF_PERFWINDOW_SEL_HQD2', - 3: 'CPF_PERFWINDOW_SEL_RDMA', - 4: 'CPF_PERFWINDOW_SEL_RWPP', -} -CPF_PERFWINDOW_SEL_CSF = 0 -CPF_PERFWINDOW_SEL_HQD1 = 1 -CPF_PERFWINDOW_SEL_HQD2 = 2 -CPF_PERFWINDOW_SEL_RDMA = 3 -CPF_PERFWINDOW_SEL_RWPP = 4 -CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' -CPG_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPG_PERFWINDOW_SEL_PFP', - 1: 'CPG_PERFWINDOW_SEL_ME', - 2: 'CPG_PERFWINDOW_SEL_CE', - 3: 'CPG_PERFWINDOW_SEL_MES', - 4: 'CPG_PERFWINDOW_SEL_MEC1', - 5: 'CPG_PERFWINDOW_SEL_MEC2', - 6: 'CPG_PERFWINDOW_SEL_DFY', - 7: 'CPG_PERFWINDOW_SEL_DMA', - 8: 'CPG_PERFWINDOW_SEL_SHADOW', - 9: 'CPG_PERFWINDOW_SEL_RB', - 10: 'CPG_PERFWINDOW_SEL_CEDMA', - 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', - 13: 'CPG_PERFWINDOW_SEL_PQ1', - 14: 'CPG_PERFWINDOW_SEL_PQ2', - 15: 'CPG_PERFWINDOW_SEL_PQ3', - 16: 'CPG_PERFWINDOW_SEL_MEMWR', - 17: 'CPG_PERFWINDOW_SEL_MEMRD', - 18: 'CPG_PERFWINDOW_SEL_VGT0', - 19: 'CPG_PERFWINDOW_SEL_VGT1', - 20: 'CPG_PERFWINDOW_SEL_APPEND', - 21: 'CPG_PERFWINDOW_SEL_QURD', - 22: 'CPG_PERFWINDOW_SEL_DDID', - 23: 'CPG_PERFWINDOW_SEL_SR', - 24: 'CPG_PERFWINDOW_SEL_QU_EOP', - 25: 'CPG_PERFWINDOW_SEL_QU_STRM', - 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', - 27: 'CPG_PERFWINDOW_SEL_RESERVED1', - 28: 'CPG_PERFWINDOW_SEL_CPC_IC', - 29: 'CPG_PERFWINDOW_SEL_RESERVED2', - 30: 'CPG_PERFWINDOW_SEL_CPG_IC', -} -CPG_PERFWINDOW_SEL_PFP = 0 -CPG_PERFWINDOW_SEL_ME = 1 -CPG_PERFWINDOW_SEL_CE = 2 -CPG_PERFWINDOW_SEL_MES = 3 -CPG_PERFWINDOW_SEL_MEC1 = 4 -CPG_PERFWINDOW_SEL_MEC2 = 5 -CPG_PERFWINDOW_SEL_DFY = 6 -CPG_PERFWINDOW_SEL_DMA = 7 -CPG_PERFWINDOW_SEL_SHADOW = 8 -CPG_PERFWINDOW_SEL_RB = 9 -CPG_PERFWINDOW_SEL_CEDMA = 10 -CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 -CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 -CPG_PERFWINDOW_SEL_PQ1 = 13 -CPG_PERFWINDOW_SEL_PQ2 = 14 -CPG_PERFWINDOW_SEL_PQ3 = 15 -CPG_PERFWINDOW_SEL_MEMWR = 16 -CPG_PERFWINDOW_SEL_MEMRD = 17 -CPG_PERFWINDOW_SEL_VGT0 = 18 -CPG_PERFWINDOW_SEL_VGT1 = 19 -CPG_PERFWINDOW_SEL_APPEND = 20 -CPG_PERFWINDOW_SEL_QURD = 21 -CPG_PERFWINDOW_SEL_DDID = 22 -CPG_PERFWINDOW_SEL_SR = 23 -CPG_PERFWINDOW_SEL_QU_EOP = 24 -CPG_PERFWINDOW_SEL_QU_STRM = 25 -CPG_PERFWINDOW_SEL_QU_PIPE = 26 -CPG_PERFWINDOW_SEL_RESERVED1 = 27 -CPG_PERFWINDOW_SEL_CPC_IC = 28 -CPG_PERFWINDOW_SEL_RESERVED2 = 29 -CPG_PERFWINDOW_SEL_CPG_IC = 30 -CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_LATENCY_STATS_SEL' -CPF_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', - 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', - 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', - 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', -} -CPF_LATENCY_STATS_SEL_XACK_MAX = 0 -CPF_LATENCY_STATS_SEL_XACK_MIN = 1 -CPF_LATENCY_STATS_SEL_XACK_LAST = 2 -CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPF_LATENCY_STATS_SEL_READ_MAX = 6 -CPF_LATENCY_STATS_SEL_READ_MIN = 7 -CPF_LATENCY_STATS_SEL_READ_LAST = 8 -CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 -CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 -CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 -CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_LATENCY_STATS_SEL' -CPG_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', - 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', - 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', - 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', -} -CPG_LATENCY_STATS_SEL_XACK_MAX = 0 -CPG_LATENCY_STATS_SEL_XACK_MIN = 1 -CPG_LATENCY_STATS_SEL_XACK_LAST = 2 -CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 -CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 -CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 -CPG_LATENCY_STATS_SEL_READ_MAX = 9 -CPG_LATENCY_STATS_SEL_READ_MIN = 10 -CPG_LATENCY_STATS_SEL_READ_LAST = 11 -CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 -CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 -CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 -CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 -CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 -CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 -CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_LATENCY_STATS_SEL' -CPC_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', -} -CPC_LATENCY_STATS_SEL_XACK_MAX = 0 -CPC_LATENCY_STATS_SEL_XACK_MIN = 1 -CPC_LATENCY_STATS_SEL_XACK_LAST = 2 -CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 -CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 -CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 -CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_MODE' -CP_DDID_CNTL_MODE__enumvalues = { - 0: 'STALL', - 1: 'OVERRUN', -} -STALL = 0 -OVERRUN = 1 -CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_SIZE' -CP_DDID_CNTL_SIZE__enumvalues = { - 0: 'SIZE_8K', - 1: 'SIZE_16K', -} -SIZE_8K = 0 -SIZE_16K = 1 -CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_VMID_SEL' -CP_DDID_CNTL_VMID_SEL__enumvalues = { - 0: 'DDID_VMID_PIPE', - 1: 'DDID_VMID_CNTL', -} -DDID_VMID_PIPE = 0 -DDID_VMID_CNTL = 1 -CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SX_BLEND_OPT' -SX_BLEND_OPT__enumvalues = { - 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', -} -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 -SX_BLEND_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_OPT_COMB_FCN' -SX_OPT_COMB_FCN__enumvalues = { - 0: 'OPT_COMB_NONE', - 1: 'OPT_COMB_ADD', - 2: 'OPT_COMB_SUBTRACT', - 3: 'OPT_COMB_MIN', - 4: 'OPT_COMB_MAX', - 5: 'OPT_COMB_REVSUBTRACT', - 6: 'OPT_COMB_BLEND_DISABLED', - 7: 'OPT_COMB_SAFE_ADD', -} -OPT_COMB_NONE = 0 -OPT_COMB_ADD = 1 -OPT_COMB_SUBTRACT = 2 -OPT_COMB_MIN = 3 -OPT_COMB_MAX = 4 -OPT_COMB_REVSUBTRACT = 5 -OPT_COMB_BLEND_DISABLED = 6 -OPT_COMB_SAFE_ADD = 7 -SX_OPT_COMB_FCN = ctypes.c_uint32 # enum - -# values for enumeration 'SX_DOWNCONVERT_FORMAT' -SX_DOWNCONVERT_FORMAT__enumvalues = { - 0: 'SX_RT_EXPORT_NO_CONVERSION', - 1: 'SX_RT_EXPORT_32_R', - 2: 'SX_RT_EXPORT_32_A', - 3: 'SX_RT_EXPORT_10_11_11', - 4: 'SX_RT_EXPORT_2_10_10_10', - 5: 'SX_RT_EXPORT_8_8_8_8', - 6: 'SX_RT_EXPORT_5_6_5', - 7: 'SX_RT_EXPORT_1_5_5_5', - 8: 'SX_RT_EXPORT_4_4_4_4', - 9: 'SX_RT_EXPORT_16_16_GR', - 10: 'SX_RT_EXPORT_16_16_AR', -} -SX_RT_EXPORT_NO_CONVERSION = 0 -SX_RT_EXPORT_32_R = 1 -SX_RT_EXPORT_32_A = 2 -SX_RT_EXPORT_10_11_11 = 3 -SX_RT_EXPORT_2_10_10_10 = 4 -SX_RT_EXPORT_8_8_8_8 = 5 -SX_RT_EXPORT_5_6_5 = 6 -SX_RT_EXPORT_1_5_5_5 = 7 -SX_RT_EXPORT_4_4_4_4 = 8 -SX_RT_EXPORT_16_16_GR = 9 -SX_RT_EXPORT_16_16_AR = 10 -SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_PERFCOUNTER_VALS' -SX_PERFCOUNTER_VALS__enumvalues = { - 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', - 1: 'SX_PERF_SEL_PA_REQ', - 2: 'SX_PERF_SEL_PA_POS', - 3: 'SX_PERF_SEL_CLOCK', - 4: 'SX_PERF_SEL_GATE_EN1', - 5: 'SX_PERF_SEL_GATE_EN2', - 6: 'SX_PERF_SEL_GATE_EN3', - 7: 'SX_PERF_SEL_GATE_EN4', - 8: 'SX_PERF_SEL_SH_POS_STARVE', - 9: 'SX_PERF_SEL_SH_COLOR_STARVE', - 10: 'SX_PERF_SEL_SH_POS_STALL', - 11: 'SX_PERF_SEL_SH_COLOR_STALL', - 12: 'SX_PERF_SEL_DB0_PIXELS', - 13: 'SX_PERF_SEL_DB0_HALF_QUADS', - 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', - 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', - 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', - 17: 'SX_PERF_SEL_DB1_PIXELS', - 18: 'SX_PERF_SEL_DB1_HALF_QUADS', - 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', - 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', - 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', - 22: 'SX_PERF_SEL_DB2_PIXELS', - 23: 'SX_PERF_SEL_DB2_HALF_QUADS', - 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', - 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', - 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', - 27: 'SX_PERF_SEL_DB3_PIXELS', - 28: 'SX_PERF_SEL_DB3_HALF_QUADS', - 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', - 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', - 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', - 32: 'SX_PERF_SEL_COL_BUSY', - 33: 'SX_PERF_SEL_POS_BUSY', - 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', - 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', - 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', - 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', - 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', - 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', - 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', - 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', - 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', - 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', - 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', - 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', - 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', - 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', - 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', - 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', - 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', - 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', - 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', - 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', - 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', - 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', - 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', - 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', - 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', - 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', - 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', - 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', - 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', - 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', - 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', - 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', - 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', - 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', - 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', - 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', - 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', - 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', - 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', - 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', - 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', - 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', - 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', - 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', - 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', - 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', - 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', - 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', - 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', - 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', - 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', - 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', - 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', - 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', - 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', - 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', - 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', - 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', - 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', - 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', - 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', - 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', - 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', - 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', - 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', - 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', - 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', - 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', - 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', - 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', - 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', - 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', - 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', - 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', - 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', - 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', - 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', - 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', - 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', - 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', - 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', - 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', - 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', - 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', - 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', - 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', - 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', - 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', - 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', - 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', - 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', - 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', - 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', - 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', - 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', - 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', - 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', - 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', - 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', - 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', - 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', - 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', - 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', - 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', - 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', - 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', - 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', - 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', - 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', - 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', - 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', - 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', - 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', - 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', - 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', - 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', - 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', - 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', - 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', - 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', - 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', - 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', - 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', - 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', - 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', - 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', - 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', - 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', - 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', - 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', - 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', - 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', - 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', - 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', - 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', - 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', - 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', - 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', - 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', - 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', - 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', - 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', - 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', - 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', - 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', - 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', - 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', - 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', - 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', - 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', - 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', - 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', - 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', - 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', - 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', - 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', - 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', - 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', - 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', - 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', - 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', - 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', - 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', - 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', - 198: 'SX_PERF_SEL_PA_REQ_LATENCY', - 199: 'SX_PERF_SEL_POS_SCBD_STALL', - 200: 'SX_PERF_SEL_COL_SCBD_STALL', - 201: 'SX_PERF_SEL_CLOCK_DROP_STALL', - 202: 'SX_PERF_SEL_GATE_EN5', - 203: 'SX_PERF_SEL_GATE_EN6', - 204: 'SX_PERF_SEL_DB0_SIZE', - 205: 'SX_PERF_SEL_DB1_SIZE', - 206: 'SX_PERF_SEL_DB2_SIZE', - 207: 'SX_PERF_SEL_DB3_SIZE', - 208: 'SX_PERF_SEL_SPLITMODE', - 209: 'SX_PERF_SEL_COL_SCBD0_STALL', - 210: 'SX_PERF_SEL_COL_SCBD1_STALL', - 211: 'SX_PERF_SEL_IDX_STALL_CYCLES', - 212: 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 213: 'SX_PERF_SEL_IDX_REQ', - 214: 'SX_PERF_SEL_IDX_RET', - 215: 'SX_PERF_SEL_IDX_REQ_LATENCY', - 216: 'SX_PERF_SEL_IDX_SCBD_STALL', - 217: 'SX_PERF_SEL_GATE_EN7', - 218: 'SX_PERF_SEL_GATE_EN8', - 219: 'SX_PERF_SEL_SH_IDX_STARVE', - 220: 'SX_PERF_SEL_IDX_BUSY', -} -SX_PERF_SEL_PA_IDLE_CYCLES = 0 -SX_PERF_SEL_PA_REQ = 1 -SX_PERF_SEL_PA_POS = 2 -SX_PERF_SEL_CLOCK = 3 -SX_PERF_SEL_GATE_EN1 = 4 -SX_PERF_SEL_GATE_EN2 = 5 -SX_PERF_SEL_GATE_EN3 = 6 -SX_PERF_SEL_GATE_EN4 = 7 -SX_PERF_SEL_SH_POS_STARVE = 8 -SX_PERF_SEL_SH_COLOR_STARVE = 9 -SX_PERF_SEL_SH_POS_STALL = 10 -SX_PERF_SEL_SH_COLOR_STALL = 11 -SX_PERF_SEL_DB0_PIXELS = 12 -SX_PERF_SEL_DB0_HALF_QUADS = 13 -SX_PERF_SEL_DB0_PIXEL_STALL = 14 -SX_PERF_SEL_DB0_PIXEL_IDLE = 15 -SX_PERF_SEL_DB0_PRED_PIXELS = 16 -SX_PERF_SEL_DB1_PIXELS = 17 -SX_PERF_SEL_DB1_HALF_QUADS = 18 -SX_PERF_SEL_DB1_PIXEL_STALL = 19 -SX_PERF_SEL_DB1_PIXEL_IDLE = 20 -SX_PERF_SEL_DB1_PRED_PIXELS = 21 -SX_PERF_SEL_DB2_PIXELS = 22 -SX_PERF_SEL_DB2_HALF_QUADS = 23 -SX_PERF_SEL_DB2_PIXEL_STALL = 24 -SX_PERF_SEL_DB2_PIXEL_IDLE = 25 -SX_PERF_SEL_DB2_PRED_PIXELS = 26 -SX_PERF_SEL_DB3_PIXELS = 27 -SX_PERF_SEL_DB3_HALF_QUADS = 28 -SX_PERF_SEL_DB3_PIXEL_STALL = 29 -SX_PERF_SEL_DB3_PIXEL_IDLE = 30 -SX_PERF_SEL_DB3_PRED_PIXELS = 31 -SX_PERF_SEL_COL_BUSY = 32 -SX_PERF_SEL_POS_BUSY = 33 -SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 -SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 -SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 -SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 -SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 -SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 -SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 -SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 -SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 -SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 -SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 -SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 -SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 -SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 -SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 -SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 -SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 -SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 -SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 -SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 -SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 -SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 -SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 -SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 -SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 -SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 -SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 -SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 -SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 -SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 -SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 -SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 -SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 -SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 -SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 -SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 -SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 -SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 -SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 -SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 -SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 -SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 -SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 -SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 -SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 -SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 -SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 -SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 -SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 -SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 -SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 -SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 -SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 -SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 -SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 -SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 -SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 -SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 -SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 -SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 -SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 -SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 -SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 -SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 -SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 -SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 -SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 -SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 -SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 -SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 -SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 -SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 -SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 -SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 -SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 -SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 -SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 -SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 -SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 -SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 -SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 -SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 -SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 -SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 -SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 -SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 -SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 -SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 -SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 -SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 -SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 -SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 -SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 -SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 -SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 -SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 -SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 -SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 -SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 -SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 -SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 -SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 -SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 -SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 -SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 -SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 -SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 -SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 -SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 -SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 -SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 -SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 -SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 -SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 -SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 -SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 -SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 -SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 -SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 -SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 -SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 -SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 -SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 -SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 -SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 -SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 -SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 -SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 -SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 -SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 -SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 -SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 -SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 -SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 -SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 -SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 -SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 -SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 -SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 -SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 -SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 -SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 -SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 -SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 -SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 -SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 -SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 -SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 -SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 -SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 -SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 -SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 -SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 -SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 -SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 -SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 -SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 -SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 -SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 -SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 -SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 -SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 -SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 -SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 -SX_PERF_SEL_PA_REQ_LATENCY = 198 -SX_PERF_SEL_POS_SCBD_STALL = 199 -SX_PERF_SEL_COL_SCBD_STALL = 200 -SX_PERF_SEL_CLOCK_DROP_STALL = 201 -SX_PERF_SEL_GATE_EN5 = 202 -SX_PERF_SEL_GATE_EN6 = 203 -SX_PERF_SEL_DB0_SIZE = 204 -SX_PERF_SEL_DB1_SIZE = 205 -SX_PERF_SEL_DB2_SIZE = 206 -SX_PERF_SEL_DB3_SIZE = 207 -SX_PERF_SEL_SPLITMODE = 208 -SX_PERF_SEL_COL_SCBD0_STALL = 209 -SX_PERF_SEL_COL_SCBD1_STALL = 210 -SX_PERF_SEL_IDX_STALL_CYCLES = 211 -SX_PERF_SEL_IDX_IDLE_CYCLES = 212 -SX_PERF_SEL_IDX_REQ = 213 -SX_PERF_SEL_IDX_RET = 214 -SX_PERF_SEL_IDX_REQ_LATENCY = 215 -SX_PERF_SEL_IDX_SCBD_STALL = 216 -SX_PERF_SEL_GATE_EN7 = 217 -SX_PERF_SEL_GATE_EN8 = 218 -SX_PERF_SEL_SH_IDX_STARVE = 219 -SX_PERF_SEL_IDX_BUSY = 220 -SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum - -# values for enumeration 'ForceControl' -ForceControl__enumvalues = { - 0: 'FORCE_OFF', - 1: 'FORCE_ENABLE', - 2: 'FORCE_DISABLE', - 3: 'FORCE_RESERVED', -} -FORCE_OFF = 0 -FORCE_ENABLE = 1 -FORCE_DISABLE = 2 -FORCE_RESERVED = 3 -ForceControl = ctypes.c_uint32 # enum - -# values for enumeration 'ZSamplePosition' -ZSamplePosition__enumvalues = { - 0: 'Z_SAMPLE_CENTER', - 1: 'Z_SAMPLE_CENTROID', -} -Z_SAMPLE_CENTER = 0 -Z_SAMPLE_CENTROID = 1 -ZSamplePosition = ctypes.c_uint32 # enum - -# values for enumeration 'ZOrder' -ZOrder__enumvalues = { - 0: 'LATE_Z', - 1: 'EARLY_Z_THEN_LATE_Z', - 2: 'RE_Z', - 3: 'EARLY_Z_THEN_RE_Z', -} -LATE_Z = 0 -EARLY_Z_THEN_LATE_Z = 1 -RE_Z = 2 -EARLY_Z_THEN_RE_Z = 3 -ZOrder = ctypes.c_uint32 # enum - -# values for enumeration 'ZpassControl' -ZpassControl__enumvalues = { - 0: 'ZPASS_DISABLE', - 1: 'ZPASS_SAMPLES', - 2: 'ZPASS_PIXELS', -} -ZPASS_DISABLE = 0 -ZPASS_SAMPLES = 1 -ZPASS_PIXELS = 2 -ZpassControl = ctypes.c_uint32 # enum - -# values for enumeration 'ZModeForce' -ZModeForce__enumvalues = { - 0: 'NO_FORCE', - 1: 'FORCE_EARLY_Z', - 2: 'FORCE_LATE_Z', - 3: 'FORCE_RE_Z', -} -NO_FORCE = 0 -FORCE_EARLY_Z = 1 -FORCE_LATE_Z = 2 -FORCE_RE_Z = 3 -ZModeForce = ctypes.c_uint32 # enum - -# values for enumeration 'ZLimitSumm' -ZLimitSumm__enumvalues = { - 0: 'FORCE_SUMM_OFF', - 1: 'FORCE_SUMM_MINZ', - 2: 'FORCE_SUMM_MAXZ', - 3: 'FORCE_SUMM_BOTH', -} -FORCE_SUMM_OFF = 0 -FORCE_SUMM_MINZ = 1 -FORCE_SUMM_MAXZ = 2 -FORCE_SUMM_BOTH = 3 -ZLimitSumm = ctypes.c_uint32 # enum - -# values for enumeration 'CompareFrag' -CompareFrag__enumvalues = { - 0: 'FRAG_NEVER', - 1: 'FRAG_LESS', - 2: 'FRAG_EQUAL', - 3: 'FRAG_LEQUAL', - 4: 'FRAG_GREATER', - 5: 'FRAG_NOTEQUAL', - 6: 'FRAG_GEQUAL', - 7: 'FRAG_ALWAYS', -} -FRAG_NEVER = 0 -FRAG_LESS = 1 -FRAG_EQUAL = 2 -FRAG_LEQUAL = 3 -FRAG_GREATER = 4 -FRAG_NOTEQUAL = 5 -FRAG_GEQUAL = 6 -FRAG_ALWAYS = 7 -CompareFrag = ctypes.c_uint32 # enum - -# values for enumeration 'StencilOp' -StencilOp__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_ONES', - 3: 'STENCIL_REPLACE_TEST', - 4: 'STENCIL_REPLACE_OP', - 5: 'STENCIL_ADD_CLAMP', - 6: 'STENCIL_SUB_CLAMP', - 7: 'STENCIL_INVERT', - 8: 'STENCIL_ADD_WRAP', - 9: 'STENCIL_SUB_WRAP', - 10: 'STENCIL_AND', - 11: 'STENCIL_OR', - 12: 'STENCIL_XOR', - 13: 'STENCIL_NAND', - 14: 'STENCIL_NOR', - 15: 'STENCIL_XNOR', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_ONES = 2 -STENCIL_REPLACE_TEST = 3 -STENCIL_REPLACE_OP = 4 -STENCIL_ADD_CLAMP = 5 -STENCIL_SUB_CLAMP = 6 -STENCIL_INVERT = 7 -STENCIL_ADD_WRAP = 8 -STENCIL_SUB_WRAP = 9 -STENCIL_AND = 10 -STENCIL_OR = 11 -STENCIL_XOR = 12 -STENCIL_NAND = 13 -STENCIL_NOR = 14 -STENCIL_XNOR = 15 -StencilOp = ctypes.c_uint32 # enum - -# values for enumeration 'ConservativeZExport' -ConservativeZExport__enumvalues = { - 0: 'EXPORT_ANY_Z', - 1: 'EXPORT_LESS_THAN_Z', - 2: 'EXPORT_GREATER_THAN_Z', - 3: 'EXPORT_RESERVED', -} -EXPORT_ANY_Z = 0 -EXPORT_LESS_THAN_Z = 1 -EXPORT_GREATER_THAN_Z = 2 -EXPORT_RESERVED = 3 -ConservativeZExport = ctypes.c_uint32 # enum - -# values for enumeration 'DbPSLControl' -DbPSLControl__enumvalues = { - 0: 'PSLC_AUTO', - 1: 'PSLC_ON_HANG_ONLY', - 2: 'PSLC_ASAP', - 3: 'PSLC_COUNTDOWN', -} -PSLC_AUTO = 0 -PSLC_ON_HANG_ONLY = 1 -PSLC_ASAP = 2 -PSLC_COUNTDOWN = 3 -DbPSLControl = ctypes.c_uint32 # enum - -# values for enumeration 'DbPRTFaultBehavior' -DbPRTFaultBehavior__enumvalues = { - 0: 'FAULT_ZERO', - 1: 'FAULT_ONE', - 2: 'FAULT_FAIL', - 3: 'FAULT_PASS', -} -FAULT_ZERO = 0 -FAULT_ONE = 1 -FAULT_FAIL = 2 -FAULT_PASS = 3 -DbPRTFaultBehavior = ctypes.c_uint32 # enum - -# values for enumeration 'PerfCounter_Vals' -PerfCounter_Vals__enumvalues = { - 0: 'DB_PERF_SEL_SC_DB_tile_sends', - 1: 'DB_PERF_SEL_SC_DB_tile_busy', - 2: 'DB_PERF_SEL_SC_DB_tile_stalls', - 3: 'DB_PERF_SEL_SC_DB_tile_events', - 4: 'DB_PERF_SEL_SC_DB_tile_tiles', - 5: 'DB_PERF_SEL_SC_DB_tile_covered', - 6: 'DB_PERF_SEL_hiz_tc_read_starved', - 7: 'DB_PERF_SEL_hiz_tc_write_stall', - 8: 'DB_PERF_SEL_hiz_tile_culled', - 9: 'DB_PERF_SEL_his_tile_culled', - 10: 'DB_PERF_SEL_DB_SC_tile_sends', - 11: 'DB_PERF_SEL_DB_SC_tile_busy', - 12: 'DB_PERF_SEL_DB_SC_tile_stalls', - 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 14: 'DB_PERF_SEL_DB_SC_tile_tiles', - 15: 'DB_PERF_SEL_DB_SC_tile_culled', - 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', - 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 23: 'DB_PERF_SEL_SC_DB_quad_sends', - 24: 'DB_PERF_SEL_SC_DB_quad_busy', - 25: 'DB_PERF_SEL_SC_DB_quad_squads', - 26: 'DB_PERF_SEL_SC_DB_quad_tiles', - 27: 'DB_PERF_SEL_SC_DB_quad_pixels', - 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 29: 'DB_PERF_SEL_DB_SC_quad_sends', - 30: 'DB_PERF_SEL_DB_SC_quad_busy', - 31: 'DB_PERF_SEL_DB_SC_quad_stalls', - 32: 'DB_PERF_SEL_DB_SC_quad_tiles', - 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 34: 'DB_PERF_SEL_DB_CB_tile_sends', - 35: 'DB_PERF_SEL_DB_CB_tile_busy', - 36: 'DB_PERF_SEL_DB_CB_tile_stalls', - 37: 'DB_PERF_SEL_SX_DB_quad_sends', - 38: 'DB_PERF_SEL_SX_DB_quad_busy', - 39: 'DB_PERF_SEL_SX_DB_quad_stalls', - 40: 'DB_PERF_SEL_SX_DB_quad_quads', - 41: 'DB_PERF_SEL_SX_DB_quad_pixels', - 42: 'DB_PERF_SEL_SX_DB_quad_exports', - 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', - 44: 'DB_PERF_SEL_DB_CB_lquad_sends', - 45: 'DB_PERF_SEL_DB_CB_lquad_busy', - 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', - 47: 'DB_PERF_SEL_DB_CB_lquad_quads', - 48: 'DB_PERF_SEL_tile_rd_sends', - 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 50: 'DB_PERF_SEL_quad_rd_sends', - 51: 'DB_PERF_SEL_quad_rd_busy', - 52: 'DB_PERF_SEL_quad_rd_mi_stall', - 53: 'DB_PERF_SEL_quad_rd_rw_collision', - 54: 'DB_PERF_SEL_quad_rd_tag_stall', - 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', - 56: 'DB_PERF_SEL_quad_rd_panic', - 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 58: 'DB_PERF_SEL_quad_rdret_sends', - 59: 'DB_PERF_SEL_quad_rdret_busy', - 60: 'DB_PERF_SEL_tile_wr_sends', - 61: 'DB_PERF_SEL_tile_wr_acks', - 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 63: 'DB_PERF_SEL_quad_wr_sends', - 64: 'DB_PERF_SEL_quad_wr_busy', - 65: 'DB_PERF_SEL_quad_wr_mi_stall', - 66: 'DB_PERF_SEL_quad_wr_coherency_stall', - 67: 'DB_PERF_SEL_quad_wr_acks', - 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 69: 'DB_PERF_SEL_Tile_Cache_misses', - 70: 'DB_PERF_SEL_Tile_Cache_hits', - 71: 'DB_PERF_SEL_Tile_Cache_flushes', - 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', - 73: 'DB_PERF_SEL_Tile_Cache_starves', - 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 75: 'DB_PERF_SEL_tcp_dispatcher_reads', - 76: 'DB_PERF_SEL_tcp_prefetcher_reads', - 77: 'DB_PERF_SEL_tcp_preloader_reads', - 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', - 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', - 80: 'DB_PERF_SEL_tcp_preloader_flushes', - 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', - 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 95: 'DB_PERF_SEL_Stencil_Cache_misses', - 96: 'DB_PERF_SEL_Stencil_Cache_hits', - 97: 'DB_PERF_SEL_Stencil_Cache_flushes', - 98: 'DB_PERF_SEL_Stencil_Cache_starves', - 99: 'DB_PERF_SEL_Stencil_Cache_frees', - 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', - 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', - 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', - 108: 'DB_PERF_SEL_Z_Cache_frees', - 109: 'DB_PERF_SEL_Plane_Cache_misses', - 110: 'DB_PERF_SEL_Plane_Cache_hits', - 111: 'DB_PERF_SEL_Plane_Cache_flushes', - 112: 'DB_PERF_SEL_Plane_Cache_starves', - 113: 'DB_PERF_SEL_Plane_Cache_frees', - 114: 'DB_PERF_SEL_flush_expanded_stencil', - 115: 'DB_PERF_SEL_flush_compressed_stencil', - 116: 'DB_PERF_SEL_flush_single_stencil', - 117: 'DB_PERF_SEL_planes_flushed', - 118: 'DB_PERF_SEL_flush_1plane', - 119: 'DB_PERF_SEL_flush_2plane', - 120: 'DB_PERF_SEL_flush_3plane', - 121: 'DB_PERF_SEL_flush_4plane', - 122: 'DB_PERF_SEL_flush_5plane', - 123: 'DB_PERF_SEL_flush_6plane', - 124: 'DB_PERF_SEL_flush_7plane', - 125: 'DB_PERF_SEL_flush_8plane', - 126: 'DB_PERF_SEL_flush_9plane', - 127: 'DB_PERF_SEL_flush_10plane', - 128: 'DB_PERF_SEL_flush_11plane', - 129: 'DB_PERF_SEL_flush_12plane', - 130: 'DB_PERF_SEL_flush_13plane', - 131: 'DB_PERF_SEL_flush_14plane', - 132: 'DB_PERF_SEL_flush_15plane', - 133: 'DB_PERF_SEL_flush_16plane', - 134: 'DB_PERF_SEL_flush_expanded_z', - 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 137: 'DB_PERF_SEL_dk_tile_sends', - 138: 'DB_PERF_SEL_dk_tile_busy', - 139: 'DB_PERF_SEL_dk_tile_quad_starves', - 140: 'DB_PERF_SEL_dk_tile_stalls', - 141: 'DB_PERF_SEL_dk_squad_sends', - 142: 'DB_PERF_SEL_dk_squad_busy', - 143: 'DB_PERF_SEL_dk_squad_stalls', - 144: 'DB_PERF_SEL_Op_Pipe_Busy', - 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 146: 'DB_PERF_SEL_qc_busy', - 147: 'DB_PERF_SEL_qc_xfc', - 148: 'DB_PERF_SEL_qc_conflicts', - 149: 'DB_PERF_SEL_qc_full_stall', - 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', - 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', - 153: 'DB_PERF_SEL_tl_busy', - 154: 'DB_PERF_SEL_tl_dtc_read_starved', - 155: 'DB_PERF_SEL_tl_z_fetch_stall', - 156: 'DB_PERF_SEL_tl_stencil_stall', - 157: 'DB_PERF_SEL_tl_z_decompress_stall', - 158: 'DB_PERF_SEL_tl_stencil_locked_stall', - 159: 'DB_PERF_SEL_tl_events', - 160: 'DB_PERF_SEL_tl_summarize_squads', - 161: 'DB_PERF_SEL_tl_flush_expand_squads', - 162: 'DB_PERF_SEL_tl_expand_squads', - 163: 'DB_PERF_SEL_tl_preZ_squads', - 164: 'DB_PERF_SEL_tl_postZ_squads', - 165: 'DB_PERF_SEL_tl_preZ_noop_squads', - 166: 'DB_PERF_SEL_tl_postZ_noop_squads', - 167: 'DB_PERF_SEL_tl_tile_ops', - 168: 'DB_PERF_SEL_tl_in_xfc', - 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 170: 'DB_PERF_SEL_tl_in_fast_z_stall', - 171: 'DB_PERF_SEL_tl_out_xfc', - 172: 'DB_PERF_SEL_tl_out_squads', - 173: 'DB_PERF_SEL_zf_plane_multicycle', - 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', - 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', - 180: 'DB_PERF_SEL_ts_tc_update_stall', - 181: 'DB_PERF_SEL_sc_kick_start', - 182: 'DB_PERF_SEL_sc_kick_end', - 183: 'DB_PERF_SEL_clock_reg_active', - 184: 'DB_PERF_SEL_clock_main_active', - 185: 'DB_PERF_SEL_clock_mem_export_active', - 186: 'DB_PERF_SEL_esr_ps_out_busy', - 187: 'DB_PERF_SEL_esr_ps_lqf_busy', - 188: 'DB_PERF_SEL_esr_ps_lqf_stall', - 189: 'DB_PERF_SEL_etr_out_send', - 190: 'DB_PERF_SEL_etr_out_busy', - 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', - 193: 'DB_PERF_SEL_etr_out_esr_stall', - 194: 'DB_PERF_SEL_esr_ps_sqq_busy', - 195: 'DB_PERF_SEL_esr_ps_sqq_stall', - 196: 'DB_PERF_SEL_esr_eot_fwd_busy', - 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 198: 'DB_PERF_SEL_esr_eot_fwd_forward', - 199: 'DB_PERF_SEL_esr_sqq_zi_busy', - 200: 'DB_PERF_SEL_esr_sqq_zi_stall', - 201: 'DB_PERF_SEL_postzl_sq_pt_busy', - 202: 'DB_PERF_SEL_postzl_sq_pt_stall', - 203: 'DB_PERF_SEL_postzl_se_busy', - 204: 'DB_PERF_SEL_postzl_se_stall', - 205: 'DB_PERF_SEL_postzl_partial_launch', - 206: 'DB_PERF_SEL_postzl_full_launch', - 207: 'DB_PERF_SEL_postzl_partial_waiting', - 208: 'DB_PERF_SEL_postzl_tile_mem_stall', - 209: 'DB_PERF_SEL_postzl_tile_init_stall', - 210: 'DB_PERF_SEL_prezl_tile_mem_stall', - 211: 'DB_PERF_SEL_prezl_tile_init_stall', - 212: 'DB_PERF_SEL_dtt_sm_clash_stall', - 213: 'DB_PERF_SEL_dtt_sm_slot_stall', - 214: 'DB_PERF_SEL_dtt_sm_miss_stall', - 215: 'DB_PERF_SEL_mi_rdreq_busy', - 216: 'DB_PERF_SEL_mi_rdreq_stall', - 217: 'DB_PERF_SEL_mi_wrreq_busy', - 218: 'DB_PERF_SEL_mi_wrreq_stall', - 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 220: 'DB_PERF_SEL_dkg_tile_rate_tile', - 221: 'DB_PERF_SEL_prezl_src_in_sends', - 222: 'DB_PERF_SEL_prezl_src_in_stall', - 223: 'DB_PERF_SEL_prezl_src_in_squads', - 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', - 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 227: 'DB_PERF_SEL_prezl_src_out_stall', - 228: 'DB_PERF_SEL_postzl_src_in_sends', - 229: 'DB_PERF_SEL_postzl_src_in_stall', - 230: 'DB_PERF_SEL_postzl_src_in_squads', - 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', - 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 234: 'DB_PERF_SEL_postzl_src_out_stall', - 235: 'DB_PERF_SEL_esr_ps_src_in_sends', - 236: 'DB_PERF_SEL_esr_ps_src_in_stall', - 237: 'DB_PERF_SEL_esr_ps_src_in_squads', - 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 242: 'DB_PERF_SEL_esr_ps_src_out_stall', - 243: 'DB_PERF_SEL_depth_bounds_tile_culled', - 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 246: 'DB_PERF_SEL_flush_compressed', - 247: 'DB_PERF_SEL_flush_plane_le4', - 248: 'DB_PERF_SEL_tiles_z_fully_summarized', - 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', - 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', - 256: 'DB_PERF_SEL_di_dt_stall', - 257: 'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke', - 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', - 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', - 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', - 261: 'Spare_261', - 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', - 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', - 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', - 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 270: 'DB_PERF_SEL_DB_CB_rdret_ack', - 271: 'DB_PERF_SEL_DB_CB_rdret_nack', - 272: 'DB_PERF_SEL_DB_CB_wrret_ack', - 273: 'DB_PERF_SEL_DB_CB_wrret_nack', - 274: 'DB_PERF_SEL_DFSM_Stall_opmode_change', - 275: 'DB_PERF_SEL_DFSM_Stall_cam_fifo', - 276: 'DB_PERF_SEL_DFSM_Stall_bypass_fifo', - 277: 'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo', - 278: 'DB_PERF_SEL_DFSM_Stall_control_fifo', - 279: 'DB_PERF_SEL_DFSM_Stall_overflow_counter', - 280: 'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow', - 281: 'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush', - 282: 'DB_PERF_SEL_DFSM_Stall_middle_output', - 283: 'DB_PERF_SEL_DFSM_Stall_stalling_general', - 284: 'Spare_285', - 285: 'Spare_286', - 286: 'DB_PERF_SEL_DFSM_prez_killed_squad', - 287: 'DB_PERF_SEL_DFSM_squads_in', - 288: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', - 289: 'DB_PERF_SEL_DFSM_quads_in', - 290: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', - 291: 'DB_PERF_SEL_DFSM_lit_pixels_in', - 292: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', - 293: 'DB_PERF_SEL_DFSM_lit_samples_in', - 294: 'DB_PERF_SEL_DFSM_lit_samples_out', - 295: 'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark', - 296: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', - 297: 'DB_PERF_SEL_DFSM_stalled_by_downstream', - 298: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', - 299: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', - 300: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', - 301: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', - 302: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 303: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 304: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 305: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 306: 'DB_PERF_SEL_unmapped_z_tile_culled', - 307: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 308: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 309: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 310: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 311: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 312: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 313: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 314: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 315: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 316: 'DB_PERF_SEL_DB_CB_context_dones', - 317: 'DB_PERF_SEL_DB_CB_eop_dones', - 318: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 319: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 320: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 321: 'DB_PERF_SEL_SC_DB_tile_backface', - 322: 'DB_PERF_SEL_SC_DB_quad_quads', - 323: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 324: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 325: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 326: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 327: 'DB_PERF_SEL_DFSM_Flush_flushabit', - 328: 'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo', - 329: 'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough', - 330: 'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush', - 331: 'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull', - 332: 'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark', - 333: 'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling', - 334: 'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark', - 335: 'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark', - 336: 'DB_PERF_SEL_DFSM_Flush_flushall', - 337: 'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush', - 338: 'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange', - 339: 'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange', - 340: 'DB_PERF_SEL_DFSM_Flush_flushall_watchdog', - 341: 'DB_PERF_SEL_DB_SC_quad_double_quad', - 342: 'DB_PERF_SEL_SX_DB_quad_export_quads', - 343: 'DB_PERF_SEL_SX_DB_quad_double_format', - 344: 'DB_PERF_SEL_SX_DB_quad_fast_format', - 345: 'DB_PERF_SEL_SX_DB_quad_slow_format', -} -DB_PERF_SEL_SC_DB_tile_sends = 0 -DB_PERF_SEL_SC_DB_tile_busy = 1 -DB_PERF_SEL_SC_DB_tile_stalls = 2 -DB_PERF_SEL_SC_DB_tile_events = 3 -DB_PERF_SEL_SC_DB_tile_tiles = 4 -DB_PERF_SEL_SC_DB_tile_covered = 5 -DB_PERF_SEL_hiz_tc_read_starved = 6 -DB_PERF_SEL_hiz_tc_write_stall = 7 -DB_PERF_SEL_hiz_tile_culled = 8 -DB_PERF_SEL_his_tile_culled = 9 -DB_PERF_SEL_DB_SC_tile_sends = 10 -DB_PERF_SEL_DB_SC_tile_busy = 11 -DB_PERF_SEL_DB_SC_tile_stalls = 12 -DB_PERF_SEL_DB_SC_tile_df_stalls = 13 -DB_PERF_SEL_DB_SC_tile_tiles = 14 -DB_PERF_SEL_DB_SC_tile_culled = 15 -DB_PERF_SEL_DB_SC_tile_hier_kill = 16 -DB_PERF_SEL_DB_SC_tile_fast_ops = 17 -DB_PERF_SEL_DB_SC_tile_no_ops = 18 -DB_PERF_SEL_DB_SC_tile_tile_rate = 19 -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 -DB_PERF_SEL_SC_DB_quad_sends = 23 -DB_PERF_SEL_SC_DB_quad_busy = 24 -DB_PERF_SEL_SC_DB_quad_squads = 25 -DB_PERF_SEL_SC_DB_quad_tiles = 26 -DB_PERF_SEL_SC_DB_quad_pixels = 27 -DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 -DB_PERF_SEL_DB_SC_quad_sends = 29 -DB_PERF_SEL_DB_SC_quad_busy = 30 -DB_PERF_SEL_DB_SC_quad_stalls = 31 -DB_PERF_SEL_DB_SC_quad_tiles = 32 -DB_PERF_SEL_DB_SC_quad_lit_quad = 33 -DB_PERF_SEL_DB_CB_tile_sends = 34 -DB_PERF_SEL_DB_CB_tile_busy = 35 -DB_PERF_SEL_DB_CB_tile_stalls = 36 -DB_PERF_SEL_SX_DB_quad_sends = 37 -DB_PERF_SEL_SX_DB_quad_busy = 38 -DB_PERF_SEL_SX_DB_quad_stalls = 39 -DB_PERF_SEL_SX_DB_quad_quads = 40 -DB_PERF_SEL_SX_DB_quad_pixels = 41 -DB_PERF_SEL_SX_DB_quad_exports = 42 -DB_PERF_SEL_SH_quads_outstanding_sum = 43 -DB_PERF_SEL_DB_CB_lquad_sends = 44 -DB_PERF_SEL_DB_CB_lquad_busy = 45 -DB_PERF_SEL_DB_CB_lquad_stalls = 46 -DB_PERF_SEL_DB_CB_lquad_quads = 47 -DB_PERF_SEL_tile_rd_sends = 48 -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 -DB_PERF_SEL_quad_rd_sends = 50 -DB_PERF_SEL_quad_rd_busy = 51 -DB_PERF_SEL_quad_rd_mi_stall = 52 -DB_PERF_SEL_quad_rd_rw_collision = 53 -DB_PERF_SEL_quad_rd_tag_stall = 54 -DB_PERF_SEL_quad_rd_32byte_reqs = 55 -DB_PERF_SEL_quad_rd_panic = 56 -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 -DB_PERF_SEL_quad_rdret_sends = 58 -DB_PERF_SEL_quad_rdret_busy = 59 -DB_PERF_SEL_tile_wr_sends = 60 -DB_PERF_SEL_tile_wr_acks = 61 -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 -DB_PERF_SEL_quad_wr_sends = 63 -DB_PERF_SEL_quad_wr_busy = 64 -DB_PERF_SEL_quad_wr_mi_stall = 65 -DB_PERF_SEL_quad_wr_coherency_stall = 66 -DB_PERF_SEL_quad_wr_acks = 67 -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 -DB_PERF_SEL_Tile_Cache_misses = 69 -DB_PERF_SEL_Tile_Cache_hits = 70 -DB_PERF_SEL_Tile_Cache_flushes = 71 -DB_PERF_SEL_Tile_Cache_surface_stall = 72 -DB_PERF_SEL_Tile_Cache_starves = 73 -DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 -DB_PERF_SEL_tcp_dispatcher_reads = 75 -DB_PERF_SEL_tcp_prefetcher_reads = 76 -DB_PERF_SEL_tcp_preloader_reads = 77 -DB_PERF_SEL_tcp_dispatcher_flushes = 78 -DB_PERF_SEL_tcp_prefetcher_flushes = 79 -DB_PERF_SEL_tcp_preloader_flushes = 80 -DB_PERF_SEL_Depth_Tile_Cache_sends = 81 -DB_PERF_SEL_Depth_Tile_Cache_busy = 82 -DB_PERF_SEL_Depth_Tile_Cache_starves = 83 -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 -DB_PERF_SEL_Depth_Tile_Cache_misses = 86 -DB_PERF_SEL_Depth_Tile_Cache_hits = 87 -DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 -DB_PERF_SEL_Depth_Tile_Cache_event = 91 -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 -DB_PERF_SEL_Stencil_Cache_misses = 95 -DB_PERF_SEL_Stencil_Cache_hits = 96 -DB_PERF_SEL_Stencil_Cache_flushes = 97 -DB_PERF_SEL_Stencil_Cache_starves = 98 -DB_PERF_SEL_Stencil_Cache_frees = 99 -DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 -DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 -DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 -DB_PERF_SEL_Z_Cache_pmask_misses = 104 -DB_PERF_SEL_Z_Cache_pmask_hits = 105 -DB_PERF_SEL_Z_Cache_pmask_flushes = 106 -DB_PERF_SEL_Z_Cache_pmask_starves = 107 -DB_PERF_SEL_Z_Cache_frees = 108 -DB_PERF_SEL_Plane_Cache_misses = 109 -DB_PERF_SEL_Plane_Cache_hits = 110 -DB_PERF_SEL_Plane_Cache_flushes = 111 -DB_PERF_SEL_Plane_Cache_starves = 112 -DB_PERF_SEL_Plane_Cache_frees = 113 -DB_PERF_SEL_flush_expanded_stencil = 114 -DB_PERF_SEL_flush_compressed_stencil = 115 -DB_PERF_SEL_flush_single_stencil = 116 -DB_PERF_SEL_planes_flushed = 117 -DB_PERF_SEL_flush_1plane = 118 -DB_PERF_SEL_flush_2plane = 119 -DB_PERF_SEL_flush_3plane = 120 -DB_PERF_SEL_flush_4plane = 121 -DB_PERF_SEL_flush_5plane = 122 -DB_PERF_SEL_flush_6plane = 123 -DB_PERF_SEL_flush_7plane = 124 -DB_PERF_SEL_flush_8plane = 125 -DB_PERF_SEL_flush_9plane = 126 -DB_PERF_SEL_flush_10plane = 127 -DB_PERF_SEL_flush_11plane = 128 -DB_PERF_SEL_flush_12plane = 129 -DB_PERF_SEL_flush_13plane = 130 -DB_PERF_SEL_flush_14plane = 131 -DB_PERF_SEL_flush_15plane = 132 -DB_PERF_SEL_flush_16plane = 133 -DB_PERF_SEL_flush_expanded_z = 134 -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 -DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 -DB_PERF_SEL_dk_tile_sends = 137 -DB_PERF_SEL_dk_tile_busy = 138 -DB_PERF_SEL_dk_tile_quad_starves = 139 -DB_PERF_SEL_dk_tile_stalls = 140 -DB_PERF_SEL_dk_squad_sends = 141 -DB_PERF_SEL_dk_squad_busy = 142 -DB_PERF_SEL_dk_squad_stalls = 143 -DB_PERF_SEL_Op_Pipe_Busy = 144 -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 -DB_PERF_SEL_qc_busy = 146 -DB_PERF_SEL_qc_xfc = 147 -DB_PERF_SEL_qc_conflicts = 148 -DB_PERF_SEL_qc_full_stall = 149 -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 -DB_PERF_SEL_tsc_insert_summarize_stall = 152 -DB_PERF_SEL_tl_busy = 153 -DB_PERF_SEL_tl_dtc_read_starved = 154 -DB_PERF_SEL_tl_z_fetch_stall = 155 -DB_PERF_SEL_tl_stencil_stall = 156 -DB_PERF_SEL_tl_z_decompress_stall = 157 -DB_PERF_SEL_tl_stencil_locked_stall = 158 -DB_PERF_SEL_tl_events = 159 -DB_PERF_SEL_tl_summarize_squads = 160 -DB_PERF_SEL_tl_flush_expand_squads = 161 -DB_PERF_SEL_tl_expand_squads = 162 -DB_PERF_SEL_tl_preZ_squads = 163 -DB_PERF_SEL_tl_postZ_squads = 164 -DB_PERF_SEL_tl_preZ_noop_squads = 165 -DB_PERF_SEL_tl_postZ_noop_squads = 166 -DB_PERF_SEL_tl_tile_ops = 167 -DB_PERF_SEL_tl_in_xfc = 168 -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 -DB_PERF_SEL_tl_in_fast_z_stall = 170 -DB_PERF_SEL_tl_out_xfc = 171 -DB_PERF_SEL_tl_out_squads = 172 -DB_PERF_SEL_zf_plane_multicycle = 173 -DB_PERF_SEL_PostZ_Samples_passing_Z = 174 -DB_PERF_SEL_PostZ_Samples_failing_Z = 175 -DB_PERF_SEL_PostZ_Samples_failing_S = 176 -DB_PERF_SEL_PreZ_Samples_passing_Z = 177 -DB_PERF_SEL_PreZ_Samples_failing_Z = 178 -DB_PERF_SEL_PreZ_Samples_failing_S = 179 -DB_PERF_SEL_ts_tc_update_stall = 180 -DB_PERF_SEL_sc_kick_start = 181 -DB_PERF_SEL_sc_kick_end = 182 -DB_PERF_SEL_clock_reg_active = 183 -DB_PERF_SEL_clock_main_active = 184 -DB_PERF_SEL_clock_mem_export_active = 185 -DB_PERF_SEL_esr_ps_out_busy = 186 -DB_PERF_SEL_esr_ps_lqf_busy = 187 -DB_PERF_SEL_esr_ps_lqf_stall = 188 -DB_PERF_SEL_etr_out_send = 189 -DB_PERF_SEL_etr_out_busy = 190 -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 -DB_PERF_SEL_etr_out_cb_tile_stall = 192 -DB_PERF_SEL_etr_out_esr_stall = 193 -DB_PERF_SEL_esr_ps_sqq_busy = 194 -DB_PERF_SEL_esr_ps_sqq_stall = 195 -DB_PERF_SEL_esr_eot_fwd_busy = 196 -DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 -DB_PERF_SEL_esr_eot_fwd_forward = 198 -DB_PERF_SEL_esr_sqq_zi_busy = 199 -DB_PERF_SEL_esr_sqq_zi_stall = 200 -DB_PERF_SEL_postzl_sq_pt_busy = 201 -DB_PERF_SEL_postzl_sq_pt_stall = 202 -DB_PERF_SEL_postzl_se_busy = 203 -DB_PERF_SEL_postzl_se_stall = 204 -DB_PERF_SEL_postzl_partial_launch = 205 -DB_PERF_SEL_postzl_full_launch = 206 -DB_PERF_SEL_postzl_partial_waiting = 207 -DB_PERF_SEL_postzl_tile_mem_stall = 208 -DB_PERF_SEL_postzl_tile_init_stall = 209 -DB_PERF_SEL_prezl_tile_mem_stall = 210 -DB_PERF_SEL_prezl_tile_init_stall = 211 -DB_PERF_SEL_dtt_sm_clash_stall = 212 -DB_PERF_SEL_dtt_sm_slot_stall = 213 -DB_PERF_SEL_dtt_sm_miss_stall = 214 -DB_PERF_SEL_mi_rdreq_busy = 215 -DB_PERF_SEL_mi_rdreq_stall = 216 -DB_PERF_SEL_mi_wrreq_busy = 217 -DB_PERF_SEL_mi_wrreq_stall = 218 -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 -DB_PERF_SEL_dkg_tile_rate_tile = 220 -DB_PERF_SEL_prezl_src_in_sends = 221 -DB_PERF_SEL_prezl_src_in_stall = 222 -DB_PERF_SEL_prezl_src_in_squads = 223 -DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 -DB_PERF_SEL_prezl_src_in_tile_rate = 225 -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 -DB_PERF_SEL_prezl_src_out_stall = 227 -DB_PERF_SEL_postzl_src_in_sends = 228 -DB_PERF_SEL_postzl_src_in_stall = 229 -DB_PERF_SEL_postzl_src_in_squads = 230 -DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 -DB_PERF_SEL_postzl_src_in_tile_rate = 232 -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 -DB_PERF_SEL_postzl_src_out_stall = 234 -DB_PERF_SEL_esr_ps_src_in_sends = 235 -DB_PERF_SEL_esr_ps_src_in_stall = 236 -DB_PERF_SEL_esr_ps_src_in_squads = 237 -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 -DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 -DB_PERF_SEL_esr_ps_src_out_stall = 242 -DB_PERF_SEL_depth_bounds_tile_culled = 243 -DB_PERF_SEL_PreZ_Samples_failing_DB = 244 -DB_PERF_SEL_PostZ_Samples_failing_DB = 245 -DB_PERF_SEL_flush_compressed = 246 -DB_PERF_SEL_flush_plane_le4 = 247 -DB_PERF_SEL_tiles_z_fully_summarized = 248 -DB_PERF_SEL_tiles_stencil_fully_summarized = 249 -DB_PERF_SEL_tiles_z_clear_on_expclear = 250 -DB_PERF_SEL_tiles_s_clear_on_expclear = 251 -DB_PERF_SEL_tiles_decomp_on_expclear = 252 -DB_PERF_SEL_tiles_compressed_to_decompressed = 253 -DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 -DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 -DB_PERF_SEL_di_dt_stall = 256 -DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke = 257 -DB_PERF_SEL_DB_SC_s_tile_rate = 258 -DB_PERF_SEL_DB_SC_c_tile_rate = 259 -DB_PERF_SEL_DB_SC_z_tile_rate = 260 -Spare_261 = 261 -DB_PERF_SEL_DB_CB_lquad_export_quads = 262 -DB_PERF_SEL_DB_CB_lquad_double_format = 263 -DB_PERF_SEL_DB_CB_lquad_fast_format = 264 -DB_PERF_SEL_DB_CB_lquad_slow_format = 265 -DB_PERF_SEL_CB_DB_rdreq_sends = 266 -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 -DB_PERF_SEL_CB_DB_wrreq_sends = 268 -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 -DB_PERF_SEL_DB_CB_rdret_ack = 270 -DB_PERF_SEL_DB_CB_rdret_nack = 271 -DB_PERF_SEL_DB_CB_wrret_ack = 272 -DB_PERF_SEL_DB_CB_wrret_nack = 273 -DB_PERF_SEL_DFSM_Stall_opmode_change = 274 -DB_PERF_SEL_DFSM_Stall_cam_fifo = 275 -DB_PERF_SEL_DFSM_Stall_bypass_fifo = 276 -DB_PERF_SEL_DFSM_Stall_retained_tile_fifo = 277 -DB_PERF_SEL_DFSM_Stall_control_fifo = 278 -DB_PERF_SEL_DFSM_Stall_overflow_counter = 279 -DB_PERF_SEL_DFSM_Stall_pops_stall_overflow = 280 -DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush = 281 -DB_PERF_SEL_DFSM_Stall_middle_output = 282 -DB_PERF_SEL_DFSM_Stall_stalling_general = 283 -Spare_285 = 284 -Spare_286 = 285 -DB_PERF_SEL_DFSM_prez_killed_squad = 286 -DB_PERF_SEL_DFSM_squads_in = 287 -DB_PERF_SEL_DFSM_full_cleared_squads_out = 288 -DB_PERF_SEL_DFSM_quads_in = 289 -DB_PERF_SEL_DFSM_fully_cleared_quads_out = 290 -DB_PERF_SEL_DFSM_lit_pixels_in = 291 -DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 292 -DB_PERF_SEL_DFSM_lit_samples_in = 293 -DB_PERF_SEL_DFSM_lit_samples_out = 294 -DB_PERF_SEL_DFSM_evicted_tiles_above_watermark = 295 -DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 296 -DB_PERF_SEL_DFSM_stalled_by_downstream = 297 -DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 298 -DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 299 -DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 300 -DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 301 -DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 302 -DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 303 -DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 304 -DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 305 -DB_PERF_SEL_unmapped_z_tile_culled = 306 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 307 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 308 -DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 309 -DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 310 -DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 311 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 312 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 313 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 314 -DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 315 -DB_PERF_SEL_DB_CB_context_dones = 316 -DB_PERF_SEL_DB_CB_eop_dones = 317 -DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 318 -DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 319 -DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 320 -DB_PERF_SEL_SC_DB_tile_backface = 321 -DB_PERF_SEL_SC_DB_quad_quads = 322 -DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 323 -DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 324 -DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 325 -DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 326 -DB_PERF_SEL_DFSM_Flush_flushabit = 327 -DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo = 328 -DB_PERF_SEL_DFSM_Flush_flushabit_passthrough = 329 -DB_PERF_SEL_DFSM_Flush_flushabit_forceflush = 330 -DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull = 331 -DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark = 332 -DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling = 333 -DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark = 334 -DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark = 335 -DB_PERF_SEL_DFSM_Flush_flushall = 336 -DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush = 337 -DB_PERF_SEL_DFSM_Flush_flushall_opmodechange = 338 -DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange = 339 -DB_PERF_SEL_DFSM_Flush_flushall_watchdog = 340 -DB_PERF_SEL_DB_SC_quad_double_quad = 341 -DB_PERF_SEL_SX_DB_quad_export_quads = 342 -DB_PERF_SEL_SX_DB_quad_double_format = 343 -DB_PERF_SEL_SX_DB_quad_fast_format = 344 -DB_PERF_SEL_SX_DB_quad_slow_format = 345 -PerfCounter_Vals = ctypes.c_uint32 # enum - -# values for enumeration 'RingCounterControl' -RingCounterControl__enumvalues = { - 0: 'COUNTER_RING_SPLIT', - 1: 'COUNTER_RING_0', - 2: 'COUNTER_RING_1', -} -COUNTER_RING_SPLIT = 0 -COUNTER_RING_0 = 1 -COUNTER_RING_1 = 2 -RingCounterControl = ctypes.c_uint32 # enum - -# values for enumeration 'DbMemArbWatermarks' -DbMemArbWatermarks__enumvalues = { - 0: 'TRANSFERRED_64_BYTES', - 1: 'TRANSFERRED_128_BYTES', - 2: 'TRANSFERRED_256_BYTES', - 3: 'TRANSFERRED_512_BYTES', - 4: 'TRANSFERRED_1024_BYTES', - 5: 'TRANSFERRED_2048_BYTES', - 6: 'TRANSFERRED_4096_BYTES', - 7: 'TRANSFERRED_8192_BYTES', -} -TRANSFERRED_64_BYTES = 0 -TRANSFERRED_128_BYTES = 1 -TRANSFERRED_256_BYTES = 2 -TRANSFERRED_512_BYTES = 3 -TRANSFERRED_1024_BYTES = 4 -TRANSFERRED_2048_BYTES = 5 -TRANSFERRED_4096_BYTES = 6 -TRANSFERRED_8192_BYTES = 7 -DbMemArbWatermarks = ctypes.c_uint32 # enum - -# values for enumeration 'DFSMFlushEvents' -DFSMFlushEvents__enumvalues = { - 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', - 1: 'DB_FLUSH_AND_INV_DB_META', - 2: 'DB_CACHE_FLUSH', - 3: 'DB_CACHE_FLUSH_TS', - 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', - 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', - 6: 'DB_VPORT_CHANGED_EVENT', - 7: 'DB_CONTEXT_DONE_EVENT', - 8: 'DB_BREAK_BATCH_EVENT', - 9: 'DB_PSINVOKE_CHANGE_EVENT', - 10: 'DB_CONTEXT_SUSPEND_EVENT', -} -DB_FLUSH_AND_INV_DB_DATA_TS = 0 -DB_FLUSH_AND_INV_DB_META = 1 -DB_CACHE_FLUSH = 2 -DB_CACHE_FLUSH_TS = 3 -DB_CACHE_FLUSH_AND_INV_EVENT = 4 -DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 -DB_VPORT_CHANGED_EVENT = 6 -DB_CONTEXT_DONE_EVENT = 7 -DB_BREAK_BATCH_EVENT = 8 -DB_PSINVOKE_CHANGE_EVENT = 9 -DB_CONTEXT_SUSPEND_EVENT = 10 -DFSMFlushEvents = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeCounterId' -PixelPipeCounterId__enumvalues = { - 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', - 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', -} -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 -PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 -PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 -PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 -PixelPipeCounterId = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeStride' -PixelPipeStride__enumvalues = { - 0: 'PIXEL_PIPE_STRIDE_32_BITS', - 1: 'PIXEL_PIPE_STRIDE_64_BITS', - 2: 'PIXEL_PIPE_STRIDE_128_BITS', - 3: 'PIXEL_PIPE_STRIDE_256_BITS', -} -PIXEL_PIPE_STRIDE_32_BITS = 0 -PIXEL_PIPE_STRIDE_64_BITS = 1 -PIXEL_PIPE_STRIDE_128_BITS = 2 -PIXEL_PIPE_STRIDE_256_BITS = 3 -PixelPipeStride = ctypes.c_uint32 # enum - -# values for enumeration 'FullTileWaveBreak' -FullTileWaveBreak__enumvalues = { - 0: 'FULL_TILE_WAVE_BREAK_NBC_ONLY', - 1: 'FULL_TILE_WAVE_BREAK_BOTH', - 2: 'FULL_TILE_WAVE_BREAK_NONE', - 3: 'FULL_TILE_WAVE_BREAK_BC_ONLY', -} -FULL_TILE_WAVE_BREAK_NBC_ONLY = 0 -FULL_TILE_WAVE_BREAK_BOTH = 1 -FULL_TILE_WAVE_BREAK_NONE = 2 -FULL_TILE_WAVE_BREAK_BC_ONLY = 3 -FullTileWaveBreak = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BORDER_COLOR_TYPE' -TEX_BORDER_COLOR_TYPE__enumvalues = { - 0: 'TEX_BorderColor_TransparentBlack', - 1: 'TEX_BorderColor_OpaqueBlack', - 2: 'TEX_BorderColor_OpaqueWhite', - 3: 'TEX_BorderColor_Register', -} -TEX_BorderColor_TransparentBlack = 0 -TEX_BorderColor_OpaqueBlack = 1 -TEX_BorderColor_OpaqueWhite = 2 -TEX_BorderColor_Register = 3 -TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BC_SWIZZLE' -TEX_BC_SWIZZLE__enumvalues = { - 0: 'TEX_BC_Swizzle_XYZW', - 1: 'TEX_BC_Swizzle_XWYZ', - 2: 'TEX_BC_Swizzle_WZYX', - 3: 'TEX_BC_Swizzle_WXYZ', - 4: 'TEX_BC_Swizzle_ZYXW', - 5: 'TEX_BC_Swizzle_YXWZ', -} -TEX_BC_Swizzle_XYZW = 0 -TEX_BC_Swizzle_XWYZ = 1 -TEX_BC_Swizzle_WZYX = 2 -TEX_BC_Swizzle_WXYZ = 3 -TEX_BC_Swizzle_ZYXW = 4 -TEX_BC_Swizzle_YXWZ = 5 -TEX_BC_SWIZZLE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CHROMA_KEY' -TEX_CHROMA_KEY__enumvalues = { - 0: 'TEX_ChromaKey_Disabled', - 1: 'TEX_ChromaKey_Kill', - 2: 'TEX_ChromaKey_Blend', - 3: 'TEX_ChromaKey_RESERVED_3', -} -TEX_ChromaKey_Disabled = 0 -TEX_ChromaKey_Kill = 1 -TEX_ChromaKey_Blend = 2 -TEX_ChromaKey_RESERVED_3 = 3 -TEX_CHROMA_KEY = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CLAMP' -TEX_CLAMP__enumvalues = { - 0: 'TEX_Clamp_Repeat', - 1: 'TEX_Clamp_Mirror', - 2: 'TEX_Clamp_ClampToLast', - 3: 'TEX_Clamp_MirrorOnceToLast', - 4: 'TEX_Clamp_ClampHalfToBorder', - 5: 'TEX_Clamp_MirrorOnceHalfToBorder', - 6: 'TEX_Clamp_ClampToBorder', - 7: 'TEX_Clamp_MirrorOnceToBorder', -} -TEX_Clamp_Repeat = 0 -TEX_Clamp_Mirror = 1 -TEX_Clamp_ClampToLast = 2 -TEX_Clamp_MirrorOnceToLast = 3 -TEX_Clamp_ClampHalfToBorder = 4 -TEX_Clamp_MirrorOnceHalfToBorder = 5 -TEX_Clamp_ClampToBorder = 6 -TEX_Clamp_MirrorOnceToBorder = 7 -TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_COORD_TYPE' -TEX_COORD_TYPE__enumvalues = { - 0: 'TEX_CoordType_Unnormalized', - 1: 'TEX_CoordType_Normalized', -} -TEX_CoordType_Unnormalized = 0 -TEX_CoordType_Normalized = 1 -TEX_COORD_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' -TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { - 0: 'TEX_DepthCompareFunction_Never', - 1: 'TEX_DepthCompareFunction_Less', - 2: 'TEX_DepthCompareFunction_Equal', - 3: 'TEX_DepthCompareFunction_LessEqual', - 4: 'TEX_DepthCompareFunction_Greater', - 5: 'TEX_DepthCompareFunction_NotEqual', - 6: 'TEX_DepthCompareFunction_GreaterEqual', - 7: 'TEX_DepthCompareFunction_Always', -} -TEX_DepthCompareFunction_Never = 0 -TEX_DepthCompareFunction_Less = 1 -TEX_DepthCompareFunction_Equal = 2 -TEX_DepthCompareFunction_LessEqual = 3 -TEX_DepthCompareFunction_Greater = 4 -TEX_DepthCompareFunction_NotEqual = 5 -TEX_DepthCompareFunction_GreaterEqual = 6 -TEX_DepthCompareFunction_Always = 7 -TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DIM' -TEX_DIM__enumvalues = { - 0: 'TEX_Dim_1D', - 1: 'TEX_Dim_2D', - 2: 'TEX_Dim_3D', - 3: 'TEX_Dim_CubeMap', - 4: 'TEX_Dim_1DArray', - 5: 'TEX_Dim_2DArray', - 6: 'TEX_Dim_2D_MSAA', - 7: 'TEX_Dim_2DArray_MSAA', -} -TEX_Dim_1D = 0 -TEX_Dim_2D = 1 -TEX_Dim_3D = 2 -TEX_Dim_CubeMap = 3 -TEX_Dim_1DArray = 4 -TEX_Dim_2DArray = 5 -TEX_Dim_2D_MSAA = 6 -TEX_Dim_2DArray_MSAA = 7 -TEX_DIM = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_FORMAT_COMP' -TEX_FORMAT_COMP__enumvalues = { - 0: 'TEX_FormatComp_Unsigned', - 1: 'TEX_FormatComp_Signed', - 2: 'TEX_FormatComp_UnsignedBiased', - 3: 'TEX_FormatComp_RESERVED_3', -} -TEX_FormatComp_Unsigned = 0 -TEX_FormatComp_Signed = 1 -TEX_FormatComp_UnsignedBiased = 2 -TEX_FormatComp_RESERVED_3 = 3 -TEX_FORMAT_COMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MAX_ANISO_RATIO' -TEX_MAX_ANISO_RATIO__enumvalues = { - 0: 'TEX_MaxAnisoRatio_1to1', - 1: 'TEX_MaxAnisoRatio_2to1', - 2: 'TEX_MaxAnisoRatio_4to1', - 3: 'TEX_MaxAnisoRatio_8to1', - 4: 'TEX_MaxAnisoRatio_16to1', - 5: 'TEX_MaxAnisoRatio_RESERVED_5', - 6: 'TEX_MaxAnisoRatio_RESERVED_6', - 7: 'TEX_MaxAnisoRatio_RESERVED_7', -} -TEX_MaxAnisoRatio_1to1 = 0 -TEX_MaxAnisoRatio_2to1 = 1 -TEX_MaxAnisoRatio_4to1 = 2 -TEX_MaxAnisoRatio_8to1 = 3 -TEX_MaxAnisoRatio_16to1 = 4 -TEX_MaxAnisoRatio_RESERVED_5 = 5 -TEX_MaxAnisoRatio_RESERVED_6 = 6 -TEX_MaxAnisoRatio_RESERVED_7 = 7 -TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MIP_FILTER' -TEX_MIP_FILTER__enumvalues = { - 0: 'TEX_MipFilter_None', - 1: 'TEX_MipFilter_Point', - 2: 'TEX_MipFilter_Linear', - 3: 'TEX_MipFilter_Point_Aniso_Adj', -} -TEX_MipFilter_None = 0 -TEX_MipFilter_Point = 1 -TEX_MipFilter_Linear = 2 -TEX_MipFilter_Point_Aniso_Adj = 3 -TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_REQUEST_SIZE' -TEX_REQUEST_SIZE__enumvalues = { - 0: 'TEX_RequestSize_32B', - 1: 'TEX_RequestSize_64B', - 2: 'TEX_RequestSize_128B', - 3: 'TEX_RequestSize_2X64B', -} -TEX_RequestSize_32B = 0 -TEX_RequestSize_64B = 1 -TEX_RequestSize_128B = 2 -TEX_RequestSize_2X64B = 3 -TEX_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_SAMPLER_TYPE' -TEX_SAMPLER_TYPE__enumvalues = { - 0: 'TEX_SamplerType_Invalid', - 1: 'TEX_SamplerType_Valid', -} -TEX_SamplerType_Invalid = 0 -TEX_SamplerType_Valid = 1 -TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_XY_FILTER' -TEX_XY_FILTER__enumvalues = { - 0: 'TEX_XYFilter_Point', - 1: 'TEX_XYFilter_Linear', - 2: 'TEX_XYFilter_AnisoPoint', - 3: 'TEX_XYFilter_AnisoLinear', -} -TEX_XYFilter_Point = 0 -TEX_XYFilter_Linear = 1 -TEX_XYFilter_AnisoPoint = 2 -TEX_XYFilter_AnisoLinear = 3 -TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_Z_FILTER' -TEX_Z_FILTER__enumvalues = { - 0: 'TEX_ZFilter_None', - 1: 'TEX_ZFilter_Point', - 2: 'TEX_ZFilter_Linear', - 3: 'TEX_ZFilter_RESERVED_3', -} -TEX_ZFilter_None = 0 -TEX_ZFilter_Point = 1 -TEX_ZFilter_Linear = 2 -TEX_ZFilter_RESERVED_3 = 3 -TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_CLAMP' -VTX_CLAMP__enumvalues = { - 0: 'VTX_Clamp_ClampToZero', - 1: 'VTX_Clamp_ClampToNAN', -} -VTX_Clamp_ClampToZero = 0 -VTX_Clamp_ClampToNAN = 1 -VTX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_FETCH_TYPE' -VTX_FETCH_TYPE__enumvalues = { - 0: 'VTX_FetchType_VertexData', - 1: 'VTX_FetchType_InstanceData', - 2: 'VTX_FetchType_NoIndexOffset', - 3: 'VTX_FetchType_RESERVED_3', -} -VTX_FetchType_VertexData = 0 -VTX_FetchType_InstanceData = 1 -VTX_FetchType_NoIndexOffset = 2 -VTX_FetchType_RESERVED_3 = 3 -VTX_FETCH_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_FORMAT_COMP_ALL' -VTX_FORMAT_COMP_ALL__enumvalues = { - 0: 'VTX_FormatCompAll_Unsigned', - 1: 'VTX_FormatCompAll_Signed', -} -VTX_FormatCompAll_Unsigned = 0 -VTX_FormatCompAll_Signed = 1 -VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_MEM_REQUEST_SIZE' -VTX_MEM_REQUEST_SIZE__enumvalues = { - 0: 'VTX_MemRequestSize_32B', - 1: 'VTX_MemRequestSize_64B', -} -VTX_MemRequestSize_32B = 0 -VTX_MemRequestSize_64B = 1 -VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_DATA_FORMAT' -TVX_DATA_FORMAT__enumvalues = { - 0: 'TVX_FMT_INVALID', - 1: 'TVX_FMT_8', - 2: 'TVX_FMT_4_4', - 3: 'TVX_FMT_3_3_2', - 4: 'TVX_FMT_RESERVED_4', - 5: 'TVX_FMT_16', - 6: 'TVX_FMT_16_FLOAT', - 7: 'TVX_FMT_8_8', - 8: 'TVX_FMT_5_6_5', - 9: 'TVX_FMT_6_5_5', - 10: 'TVX_FMT_1_5_5_5', - 11: 'TVX_FMT_4_4_4_4', - 12: 'TVX_FMT_5_5_5_1', - 13: 'TVX_FMT_32', - 14: 'TVX_FMT_32_FLOAT', - 15: 'TVX_FMT_16_16', - 16: 'TVX_FMT_16_16_FLOAT', - 17: 'TVX_FMT_8_24', - 18: 'TVX_FMT_8_24_FLOAT', - 19: 'TVX_FMT_24_8', - 20: 'TVX_FMT_24_8_FLOAT', - 21: 'TVX_FMT_10_11_11', - 22: 'TVX_FMT_10_11_11_FLOAT', - 23: 'TVX_FMT_11_11_10', - 24: 'TVX_FMT_11_11_10_FLOAT', - 25: 'TVX_FMT_2_10_10_10', - 26: 'TVX_FMT_8_8_8_8', - 27: 'TVX_FMT_10_10_10_2', - 28: 'TVX_FMT_X24_8_32_FLOAT', - 29: 'TVX_FMT_32_32', - 30: 'TVX_FMT_32_32_FLOAT', - 31: 'TVX_FMT_16_16_16_16', - 32: 'TVX_FMT_16_16_16_16_FLOAT', - 33: 'TVX_FMT_RESERVED_33', - 34: 'TVX_FMT_32_32_32_32', - 35: 'TVX_FMT_32_32_32_32_FLOAT', - 36: 'TVX_FMT_RESERVED_36', - 37: 'TVX_FMT_1', - 38: 'TVX_FMT_1_REVERSED', - 39: 'TVX_FMT_GB_GR', - 40: 'TVX_FMT_BG_RG', - 41: 'TVX_FMT_32_AS_8', - 42: 'TVX_FMT_32_AS_8_8', - 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', - 44: 'TVX_FMT_8_8_8', - 45: 'TVX_FMT_16_16_16', - 46: 'TVX_FMT_16_16_16_FLOAT', - 47: 'TVX_FMT_32_32_32', - 48: 'TVX_FMT_32_32_32_FLOAT', - 49: 'TVX_FMT_BC1', - 50: 'TVX_FMT_BC2', - 51: 'TVX_FMT_BC3', - 52: 'TVX_FMT_BC4', - 53: 'TVX_FMT_BC5', - 54: 'TVX_FMT_APC0', - 55: 'TVX_FMT_APC1', - 56: 'TVX_FMT_APC2', - 57: 'TVX_FMT_APC3', - 58: 'TVX_FMT_APC4', - 59: 'TVX_FMT_APC5', - 60: 'TVX_FMT_APC6', - 61: 'TVX_FMT_APC7', - 62: 'TVX_FMT_CTX1', - 63: 'TVX_FMT_RESERVED_63', -} -TVX_FMT_INVALID = 0 -TVX_FMT_8 = 1 -TVX_FMT_4_4 = 2 -TVX_FMT_3_3_2 = 3 -TVX_FMT_RESERVED_4 = 4 -TVX_FMT_16 = 5 -TVX_FMT_16_FLOAT = 6 -TVX_FMT_8_8 = 7 -TVX_FMT_5_6_5 = 8 -TVX_FMT_6_5_5 = 9 -TVX_FMT_1_5_5_5 = 10 -TVX_FMT_4_4_4_4 = 11 -TVX_FMT_5_5_5_1 = 12 -TVX_FMT_32 = 13 -TVX_FMT_32_FLOAT = 14 -TVX_FMT_16_16 = 15 -TVX_FMT_16_16_FLOAT = 16 -TVX_FMT_8_24 = 17 -TVX_FMT_8_24_FLOAT = 18 -TVX_FMT_24_8 = 19 -TVX_FMT_24_8_FLOAT = 20 -TVX_FMT_10_11_11 = 21 -TVX_FMT_10_11_11_FLOAT = 22 -TVX_FMT_11_11_10 = 23 -TVX_FMT_11_11_10_FLOAT = 24 -TVX_FMT_2_10_10_10 = 25 -TVX_FMT_8_8_8_8 = 26 -TVX_FMT_10_10_10_2 = 27 -TVX_FMT_X24_8_32_FLOAT = 28 -TVX_FMT_32_32 = 29 -TVX_FMT_32_32_FLOAT = 30 -TVX_FMT_16_16_16_16 = 31 -TVX_FMT_16_16_16_16_FLOAT = 32 -TVX_FMT_RESERVED_33 = 33 -TVX_FMT_32_32_32_32 = 34 -TVX_FMT_32_32_32_32_FLOAT = 35 -TVX_FMT_RESERVED_36 = 36 -TVX_FMT_1 = 37 -TVX_FMT_1_REVERSED = 38 -TVX_FMT_GB_GR = 39 -TVX_FMT_BG_RG = 40 -TVX_FMT_32_AS_8 = 41 -TVX_FMT_32_AS_8_8 = 42 -TVX_FMT_5_9_9_9_SHAREDEXP = 43 -TVX_FMT_8_8_8 = 44 -TVX_FMT_16_16_16 = 45 -TVX_FMT_16_16_16_FLOAT = 46 -TVX_FMT_32_32_32 = 47 -TVX_FMT_32_32_32_FLOAT = 48 -TVX_FMT_BC1 = 49 -TVX_FMT_BC2 = 50 -TVX_FMT_BC3 = 51 -TVX_FMT_BC4 = 52 -TVX_FMT_BC5 = 53 -TVX_FMT_APC0 = 54 -TVX_FMT_APC1 = 55 -TVX_FMT_APC2 = 56 -TVX_FMT_APC3 = 57 -TVX_FMT_APC4 = 58 -TVX_FMT_APC5 = 59 -TVX_FMT_APC6 = 60 -TVX_FMT_APC7 = 61 -TVX_FMT_CTX1 = 62 -TVX_FMT_RESERVED_63 = 63 -TVX_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_DST_SEL' -TVX_DST_SEL__enumvalues = { - 0: 'TVX_DstSel_X', - 1: 'TVX_DstSel_Y', - 2: 'TVX_DstSel_Z', - 3: 'TVX_DstSel_W', - 4: 'TVX_DstSel_0f', - 5: 'TVX_DstSel_1f', - 6: 'TVX_DstSel_RESERVED_6', - 7: 'TVX_DstSel_Mask', -} -TVX_DstSel_X = 0 -TVX_DstSel_Y = 1 -TVX_DstSel_Z = 2 -TVX_DstSel_W = 3 -TVX_DstSel_0f = 4 -TVX_DstSel_1f = 5 -TVX_DstSel_RESERVED_6 = 6 -TVX_DstSel_Mask = 7 -TVX_DST_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_ENDIAN_SWAP' -TVX_ENDIAN_SWAP__enumvalues = { - 0: 'TVX_EndianSwap_None', - 1: 'TVX_EndianSwap_8in16', - 2: 'TVX_EndianSwap_8in32', - 3: 'TVX_EndianSwap_8in64', -} -TVX_EndianSwap_None = 0 -TVX_EndianSwap_8in16 = 1 -TVX_EndianSwap_8in32 = 2 -TVX_EndianSwap_8in64 = 3 -TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_INST' -TVX_INST__enumvalues = { - 0: 'TVX_Inst_NormalVertexFetch', - 1: 'TVX_Inst_SemanticVertexFetch', - 2: 'TVX_Inst_RESERVED_2', - 3: 'TVX_Inst_LD', - 4: 'TVX_Inst_GetTextureResInfo', - 5: 'TVX_Inst_GetNumberOfSamples', - 6: 'TVX_Inst_GetLOD', - 7: 'TVX_Inst_GetGradientsH', - 8: 'TVX_Inst_GetGradientsV', - 9: 'TVX_Inst_SetTextureOffsets', - 10: 'TVX_Inst_KeepGradients', - 11: 'TVX_Inst_SetGradientsH', - 12: 'TVX_Inst_SetGradientsV', - 13: 'TVX_Inst_Pass', - 14: 'TVX_Inst_GetBufferResInfo', - 15: 'TVX_Inst_RESERVED_15', - 16: 'TVX_Inst_Sample', - 17: 'TVX_Inst_Sample_L', - 18: 'TVX_Inst_Sample_LB', - 19: 'TVX_Inst_Sample_LZ', - 20: 'TVX_Inst_Sample_G', - 21: 'TVX_Inst_Gather4', - 22: 'TVX_Inst_Sample_G_LB', - 23: 'TVX_Inst_Gather4_O', - 24: 'TVX_Inst_Sample_C', - 25: 'TVX_Inst_Sample_C_L', - 26: 'TVX_Inst_Sample_C_LB', - 27: 'TVX_Inst_Sample_C_LZ', - 28: 'TVX_Inst_Sample_C_G', - 29: 'TVX_Inst_Gather4_C', - 30: 'TVX_Inst_Sample_C_G_LB', - 31: 'TVX_Inst_Gather4_C_O', -} -TVX_Inst_NormalVertexFetch = 0 -TVX_Inst_SemanticVertexFetch = 1 -TVX_Inst_RESERVED_2 = 2 -TVX_Inst_LD = 3 -TVX_Inst_GetTextureResInfo = 4 -TVX_Inst_GetNumberOfSamples = 5 -TVX_Inst_GetLOD = 6 -TVX_Inst_GetGradientsH = 7 -TVX_Inst_GetGradientsV = 8 -TVX_Inst_SetTextureOffsets = 9 -TVX_Inst_KeepGradients = 10 -TVX_Inst_SetGradientsH = 11 -TVX_Inst_SetGradientsV = 12 -TVX_Inst_Pass = 13 -TVX_Inst_GetBufferResInfo = 14 -TVX_Inst_RESERVED_15 = 15 -TVX_Inst_Sample = 16 -TVX_Inst_Sample_L = 17 -TVX_Inst_Sample_LB = 18 -TVX_Inst_Sample_LZ = 19 -TVX_Inst_Sample_G = 20 -TVX_Inst_Gather4 = 21 -TVX_Inst_Sample_G_LB = 22 -TVX_Inst_Gather4_O = 23 -TVX_Inst_Sample_C = 24 -TVX_Inst_Sample_C_L = 25 -TVX_Inst_Sample_C_LB = 26 -TVX_Inst_Sample_C_LZ = 27 -TVX_Inst_Sample_C_G = 28 -TVX_Inst_Gather4_C = 29 -TVX_Inst_Sample_C_G_LB = 30 -TVX_Inst_Gather4_C_O = 31 -TVX_INST = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_NUM_FORMAT_ALL' -TVX_NUM_FORMAT_ALL__enumvalues = { - 0: 'TVX_NumFormatAll_Norm', - 1: 'TVX_NumFormatAll_Int', - 2: 'TVX_NumFormatAll_Scaled', - 3: 'TVX_NumFormatAll_RESERVED_3', -} -TVX_NumFormatAll_Norm = 0 -TVX_NumFormatAll_Int = 1 -TVX_NumFormatAll_Scaled = 2 -TVX_NumFormatAll_RESERVED_3 = 3 -TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_SRC_SEL' -TVX_SRC_SEL__enumvalues = { - 0: 'TVX_SrcSel_X', - 1: 'TVX_SrcSel_Y', - 2: 'TVX_SrcSel_Z', - 3: 'TVX_SrcSel_W', - 4: 'TVX_SrcSel_0f', - 5: 'TVX_SrcSel_1f', -} -TVX_SrcSel_X = 0 -TVX_SrcSel_Y = 1 -TVX_SrcSel_Z = 2 -TVX_SrcSel_W = 3 -TVX_SrcSel_0f = 4 -TVX_SrcSel_1f = 5 -TVX_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_SRF_MODE_ALL' -TVX_SRF_MODE_ALL__enumvalues = { - 0: 'TVX_SRFModeAll_ZCMO', - 1: 'TVX_SRFModeAll_NZ', -} -TVX_SRFModeAll_ZCMO = 0 -TVX_SRFModeAll_NZ = 1 -TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_TYPE' -TVX_TYPE__enumvalues = { - 0: 'TVX_Type_InvalidTextureResource', - 1: 'TVX_Type_InvalidVertexBuffer', - 2: 'TVX_Type_ValidTextureResource', - 3: 'TVX_Type_ValidVertexBuffer', -} -TVX_Type_InvalidTextureResource = 0 -TVX_Type_InvalidVertexBuffer = 1 -TVX_Type_ValidTextureResource = 2 -TVX_Type_ValidVertexBuffer = 3 -TVX_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PH_PERFCNT_SEL' -PH_PERFCNT_SEL__enumvalues = { - 0: 'PH_SC0_SRPS_WINDOW_VALID', - 1: 'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 2: 'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 3: 'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 4: 'PH_SC0_ARB_STALLED_FROM_BELOW', - 5: 'PH_SC0_ARB_STARVED_FROM_ABOVE', - 6: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 7: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 8: 'PH_SC0_ARB_BUSY', - 9: 'PH_SC0_ARB_PA_BUSY_SOP', - 10: 'PH_SC0_ARB_EOP_POP_SYNC_POP', - 11: 'PH_SC0_ARB_EVENT_SYNC_POP', - 12: 'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 13: 'PH_SC0_EOP_SYNC_WINDOW', - 14: 'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 15: 'PH_SC0_BUSY_CNT_NOT_ZERO', - 16: 'PH_SC0_SEND', - 17: 'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 18: 'PH_SC0_CREDIT_AT_MAX', - 19: 'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 20: 'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 21: 'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 22: 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION', - 23: 'PH_SC0_GFX_PIPE1_TO_0_TRANSITION', - 24: 'PH_SC0_PA0_DATA_FIFO_RD', - 25: 'PH_SC0_PA0_DATA_FIFO_WE', - 26: 'PH_SC0_PA0_FIFO_EMPTY', - 27: 'PH_SC0_PA0_FIFO_FULL', - 28: 'PH_SC0_PA0_NULL_WE', - 29: 'PH_SC0_PA0_EVENT_WE', - 30: 'PH_SC0_PA0_FPOV_WE', - 31: 'PH_SC0_PA0_LPOV_WE', - 32: 'PH_SC0_PA0_EOP_WE', - 33: 'PH_SC0_PA0_DATA_FIFO_EOP_RD', - 34: 'PH_SC0_PA0_EOPG_WE', - 35: 'PH_SC0_PA0_DEALLOC_4_0_RD', - 36: 'PH_SC0_PA1_DATA_FIFO_RD', - 37: 'PH_SC0_PA1_DATA_FIFO_WE', - 38: 'PH_SC0_PA1_FIFO_EMPTY', - 39: 'PH_SC0_PA1_FIFO_FULL', - 40: 'PH_SC0_PA1_NULL_WE', - 41: 'PH_SC0_PA1_EVENT_WE', - 42: 'PH_SC0_PA1_FPOV_WE', - 43: 'PH_SC0_PA1_LPOV_WE', - 44: 'PH_SC0_PA1_EOP_WE', - 45: 'PH_SC0_PA1_DATA_FIFO_EOP_RD', - 46: 'PH_SC0_PA1_EOPG_WE', - 47: 'PH_SC0_PA1_DEALLOC_4_0_RD', - 48: 'PH_SC0_PA2_DATA_FIFO_RD', - 49: 'PH_SC0_PA2_DATA_FIFO_WE', - 50: 'PH_SC0_PA2_FIFO_EMPTY', - 51: 'PH_SC0_PA2_FIFO_FULL', - 52: 'PH_SC0_PA2_NULL_WE', - 53: 'PH_SC0_PA2_EVENT_WE', - 54: 'PH_SC0_PA2_FPOV_WE', - 55: 'PH_SC0_PA2_LPOV_WE', - 56: 'PH_SC0_PA2_EOP_WE', - 57: 'PH_SC0_PA2_DATA_FIFO_EOP_RD', - 58: 'PH_SC0_PA2_EOPG_WE', - 59: 'PH_SC0_PA2_DEALLOC_4_0_RD', - 60: 'PH_SC0_PA3_DATA_FIFO_RD', - 61: 'PH_SC0_PA3_DATA_FIFO_WE', - 62: 'PH_SC0_PA3_FIFO_EMPTY', - 63: 'PH_SC0_PA3_FIFO_FULL', - 64: 'PH_SC0_PA3_NULL_WE', - 65: 'PH_SC0_PA3_EVENT_WE', - 66: 'PH_SC0_PA3_FPOV_WE', - 67: 'PH_SC0_PA3_LPOV_WE', - 68: 'PH_SC0_PA3_EOP_WE', - 69: 'PH_SC0_PA3_DATA_FIFO_EOP_RD', - 70: 'PH_SC0_PA3_EOPG_WE', - 71: 'PH_SC0_PA3_DEALLOC_4_0_RD', - 72: 'PH_SC0_PA4_DATA_FIFO_RD', - 73: 'PH_SC0_PA4_DATA_FIFO_WE', - 74: 'PH_SC0_PA4_FIFO_EMPTY', - 75: 'PH_SC0_PA4_FIFO_FULL', - 76: 'PH_SC0_PA4_NULL_WE', - 77: 'PH_SC0_PA4_EVENT_WE', - 78: 'PH_SC0_PA4_FPOV_WE', - 79: 'PH_SC0_PA4_LPOV_WE', - 80: 'PH_SC0_PA4_EOP_WE', - 81: 'PH_SC0_PA4_DATA_FIFO_EOP_RD', - 82: 'PH_SC0_PA4_EOPG_WE', - 83: 'PH_SC0_PA4_DEALLOC_4_0_RD', - 84: 'PH_SC0_PA5_DATA_FIFO_RD', - 85: 'PH_SC0_PA5_DATA_FIFO_WE', - 86: 'PH_SC0_PA5_FIFO_EMPTY', - 87: 'PH_SC0_PA5_FIFO_FULL', - 88: 'PH_SC0_PA5_NULL_WE', - 89: 'PH_SC0_PA5_EVENT_WE', - 90: 'PH_SC0_PA5_FPOV_WE', - 91: 'PH_SC0_PA5_LPOV_WE', - 92: 'PH_SC0_PA5_EOP_WE', - 93: 'PH_SC0_PA5_DATA_FIFO_EOP_RD', - 94: 'PH_SC0_PA5_EOPG_WE', - 95: 'PH_SC0_PA5_DEALLOC_4_0_RD', - 96: 'PH_SC0_PA6_DATA_FIFO_RD', - 97: 'PH_SC0_PA6_DATA_FIFO_WE', - 98: 'PH_SC0_PA6_FIFO_EMPTY', - 99: 'PH_SC0_PA6_FIFO_FULL', - 100: 'PH_SC0_PA6_NULL_WE', - 101: 'PH_SC0_PA6_EVENT_WE', - 102: 'PH_SC0_PA6_FPOV_WE', - 103: 'PH_SC0_PA6_LPOV_WE', - 104: 'PH_SC0_PA6_EOP_WE', - 105: 'PH_SC0_PA6_DATA_FIFO_EOP_RD', - 106: 'PH_SC0_PA6_EOPG_WE', - 107: 'PH_SC0_PA6_DEALLOC_4_0_RD', - 108: 'PH_SC0_PA7_DATA_FIFO_RD', - 109: 'PH_SC0_PA7_DATA_FIFO_WE', - 110: 'PH_SC0_PA7_FIFO_EMPTY', - 111: 'PH_SC0_PA7_FIFO_FULL', - 112: 'PH_SC0_PA7_NULL_WE', - 113: 'PH_SC0_PA7_EVENT_WE', - 114: 'PH_SC0_PA7_FPOV_WE', - 115: 'PH_SC0_PA7_LPOV_WE', - 116: 'PH_SC0_PA7_EOP_WE', - 117: 'PH_SC0_PA7_DATA_FIFO_EOP_RD', - 118: 'PH_SC0_PA7_EOPG_WE', - 119: 'PH_SC0_PA7_DEALLOC_4_0_RD', - 120: 'PH_SC1_SRPS_WINDOW_VALID', - 121: 'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 122: 'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 123: 'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 124: 'PH_SC1_ARB_STALLED_FROM_BELOW', - 125: 'PH_SC1_ARB_STARVED_FROM_ABOVE', - 126: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 127: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 128: 'PH_SC1_ARB_BUSY', - 129: 'PH_SC1_ARB_PA_BUSY_SOP', - 130: 'PH_SC1_ARB_EOP_POP_SYNC_POP', - 131: 'PH_SC1_ARB_EVENT_SYNC_POP', - 132: 'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 133: 'PH_SC1_EOP_SYNC_WINDOW', - 134: 'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 135: 'PH_SC1_BUSY_CNT_NOT_ZERO', - 136: 'PH_SC1_SEND', - 137: 'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 138: 'PH_SC1_CREDIT_AT_MAX', - 139: 'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 140: 'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 141: 'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 142: 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION', - 143: 'PH_SC1_GFX_PIPE1_TO_0_TRANSITION', - 144: 'PH_SC1_PA0_DATA_FIFO_RD', - 145: 'PH_SC1_PA0_DATA_FIFO_WE', - 146: 'PH_SC1_PA0_FIFO_EMPTY', - 147: 'PH_SC1_PA0_FIFO_FULL', - 148: 'PH_SC1_PA0_NULL_WE', - 149: 'PH_SC1_PA0_EVENT_WE', - 150: 'PH_SC1_PA0_FPOV_WE', - 151: 'PH_SC1_PA0_LPOV_WE', - 152: 'PH_SC1_PA0_EOP_WE', - 153: 'PH_SC1_PA0_DATA_FIFO_EOP_RD', - 154: 'PH_SC1_PA0_EOPG_WE', - 155: 'PH_SC1_PA0_DEALLOC_4_0_RD', - 156: 'PH_SC1_PA1_DATA_FIFO_RD', - 157: 'PH_SC1_PA1_DATA_FIFO_WE', - 158: 'PH_SC1_PA1_FIFO_EMPTY', - 159: 'PH_SC1_PA1_FIFO_FULL', - 160: 'PH_SC1_PA1_NULL_WE', - 161: 'PH_SC1_PA1_EVENT_WE', - 162: 'PH_SC1_PA1_FPOV_WE', - 163: 'PH_SC1_PA1_LPOV_WE', - 164: 'PH_SC1_PA1_EOP_WE', - 165: 'PH_SC1_PA1_DATA_FIFO_EOP_RD', - 166: 'PH_SC1_PA1_EOPG_WE', - 167: 'PH_SC1_PA1_DEALLOC_4_0_RD', - 168: 'PH_SC1_PA2_DATA_FIFO_RD', - 169: 'PH_SC1_PA2_DATA_FIFO_WE', - 170: 'PH_SC1_PA2_FIFO_EMPTY', - 171: 'PH_SC1_PA2_FIFO_FULL', - 172: 'PH_SC1_PA2_NULL_WE', - 173: 'PH_SC1_PA2_EVENT_WE', - 174: 'PH_SC1_PA2_FPOV_WE', - 175: 'PH_SC1_PA2_LPOV_WE', - 176: 'PH_SC1_PA2_EOP_WE', - 177: 'PH_SC1_PA2_DATA_FIFO_EOP_RD', - 178: 'PH_SC1_PA2_EOPG_WE', - 179: 'PH_SC1_PA2_DEALLOC_4_0_RD', - 180: 'PH_SC1_PA3_DATA_FIFO_RD', - 181: 'PH_SC1_PA3_DATA_FIFO_WE', - 182: 'PH_SC1_PA3_FIFO_EMPTY', - 183: 'PH_SC1_PA3_FIFO_FULL', - 184: 'PH_SC1_PA3_NULL_WE', - 185: 'PH_SC1_PA3_EVENT_WE', - 186: 'PH_SC1_PA3_FPOV_WE', - 187: 'PH_SC1_PA3_LPOV_WE', - 188: 'PH_SC1_PA3_EOP_WE', - 189: 'PH_SC1_PA3_DATA_FIFO_EOP_RD', - 190: 'PH_SC1_PA3_EOPG_WE', - 191: 'PH_SC1_PA3_DEALLOC_4_0_RD', - 192: 'PH_SC1_PA4_DATA_FIFO_RD', - 193: 'PH_SC1_PA4_DATA_FIFO_WE', - 194: 'PH_SC1_PA4_FIFO_EMPTY', - 195: 'PH_SC1_PA4_FIFO_FULL', - 196: 'PH_SC1_PA4_NULL_WE', - 197: 'PH_SC1_PA4_EVENT_WE', - 198: 'PH_SC1_PA4_FPOV_WE', - 199: 'PH_SC1_PA4_LPOV_WE', - 200: 'PH_SC1_PA4_EOP_WE', - 201: 'PH_SC1_PA4_DATA_FIFO_EOP_RD', - 202: 'PH_SC1_PA4_EOPG_WE', - 203: 'PH_SC1_PA4_DEALLOC_4_0_RD', - 204: 'PH_SC1_PA5_DATA_FIFO_RD', - 205: 'PH_SC1_PA5_DATA_FIFO_WE', - 206: 'PH_SC1_PA5_FIFO_EMPTY', - 207: 'PH_SC1_PA5_FIFO_FULL', - 208: 'PH_SC1_PA5_NULL_WE', - 209: 'PH_SC1_PA5_EVENT_WE', - 210: 'PH_SC1_PA5_FPOV_WE', - 211: 'PH_SC1_PA5_LPOV_WE', - 212: 'PH_SC1_PA5_EOP_WE', - 213: 'PH_SC1_PA5_DATA_FIFO_EOP_RD', - 214: 'PH_SC1_PA5_EOPG_WE', - 215: 'PH_SC1_PA5_DEALLOC_4_0_RD', - 216: 'PH_SC1_PA6_DATA_FIFO_RD', - 217: 'PH_SC1_PA6_DATA_FIFO_WE', - 218: 'PH_SC1_PA6_FIFO_EMPTY', - 219: 'PH_SC1_PA6_FIFO_FULL', - 220: 'PH_SC1_PA6_NULL_WE', - 221: 'PH_SC1_PA6_EVENT_WE', - 222: 'PH_SC1_PA6_FPOV_WE', - 223: 'PH_SC1_PA6_LPOV_WE', - 224: 'PH_SC1_PA6_EOP_WE', - 225: 'PH_SC1_PA6_DATA_FIFO_EOP_RD', - 226: 'PH_SC1_PA6_EOPG_WE', - 227: 'PH_SC1_PA6_DEALLOC_4_0_RD', - 228: 'PH_SC1_PA7_DATA_FIFO_RD', - 229: 'PH_SC1_PA7_DATA_FIFO_WE', - 230: 'PH_SC1_PA7_FIFO_EMPTY', - 231: 'PH_SC1_PA7_FIFO_FULL', - 232: 'PH_SC1_PA7_NULL_WE', - 233: 'PH_SC1_PA7_EVENT_WE', - 234: 'PH_SC1_PA7_FPOV_WE', - 235: 'PH_SC1_PA7_LPOV_WE', - 236: 'PH_SC1_PA7_EOP_WE', - 237: 'PH_SC1_PA7_DATA_FIFO_EOP_RD', - 238: 'PH_SC1_PA7_EOPG_WE', - 239: 'PH_SC1_PA7_DEALLOC_4_0_RD', - 240: 'PH_SC2_SRPS_WINDOW_VALID', - 241: 'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 242: 'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 243: 'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 244: 'PH_SC2_ARB_STALLED_FROM_BELOW', - 245: 'PH_SC2_ARB_STARVED_FROM_ABOVE', - 246: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 247: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 248: 'PH_SC2_ARB_BUSY', - 249: 'PH_SC2_ARB_PA_BUSY_SOP', - 250: 'PH_SC2_ARB_EOP_POP_SYNC_POP', - 251: 'PH_SC2_ARB_EVENT_SYNC_POP', - 252: 'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 253: 'PH_SC2_EOP_SYNC_WINDOW', - 254: 'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 255: 'PH_SC2_BUSY_CNT_NOT_ZERO', - 256: 'PH_SC2_SEND', - 257: 'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 258: 'PH_SC2_CREDIT_AT_MAX', - 259: 'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 260: 'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 261: 'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 262: 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION', - 263: 'PH_SC2_GFX_PIPE1_TO_0_TRANSITION', - 264: 'PH_SC2_PA0_DATA_FIFO_RD', - 265: 'PH_SC2_PA0_DATA_FIFO_WE', - 266: 'PH_SC2_PA0_FIFO_EMPTY', - 267: 'PH_SC2_PA0_FIFO_FULL', - 268: 'PH_SC2_PA0_NULL_WE', - 269: 'PH_SC2_PA0_EVENT_WE', - 270: 'PH_SC2_PA0_FPOV_WE', - 271: 'PH_SC2_PA0_LPOV_WE', - 272: 'PH_SC2_PA0_EOP_WE', - 273: 'PH_SC2_PA0_DATA_FIFO_EOP_RD', - 274: 'PH_SC2_PA0_EOPG_WE', - 275: 'PH_SC2_PA0_DEALLOC_4_0_RD', - 276: 'PH_SC2_PA1_DATA_FIFO_RD', - 277: 'PH_SC2_PA1_DATA_FIFO_WE', - 278: 'PH_SC2_PA1_FIFO_EMPTY', - 279: 'PH_SC2_PA1_FIFO_FULL', - 280: 'PH_SC2_PA1_NULL_WE', - 281: 'PH_SC2_PA1_EVENT_WE', - 282: 'PH_SC2_PA1_FPOV_WE', - 283: 'PH_SC2_PA1_LPOV_WE', - 284: 'PH_SC2_PA1_EOP_WE', - 285: 'PH_SC2_PA1_DATA_FIFO_EOP_RD', - 286: 'PH_SC2_PA1_EOPG_WE', - 287: 'PH_SC2_PA1_DEALLOC_4_0_RD', - 288: 'PH_SC2_PA2_DATA_FIFO_RD', - 289: 'PH_SC2_PA2_DATA_FIFO_WE', - 290: 'PH_SC2_PA2_FIFO_EMPTY', - 291: 'PH_SC2_PA2_FIFO_FULL', - 292: 'PH_SC2_PA2_NULL_WE', - 293: 'PH_SC2_PA2_EVENT_WE', - 294: 'PH_SC2_PA2_FPOV_WE', - 295: 'PH_SC2_PA2_LPOV_WE', - 296: 'PH_SC2_PA2_EOP_WE', - 297: 'PH_SC2_PA2_DATA_FIFO_EOP_RD', - 298: 'PH_SC2_PA2_EOPG_WE', - 299: 'PH_SC2_PA2_DEALLOC_4_0_RD', - 300: 'PH_SC2_PA3_DATA_FIFO_RD', - 301: 'PH_SC2_PA3_DATA_FIFO_WE', - 302: 'PH_SC2_PA3_FIFO_EMPTY', - 303: 'PH_SC2_PA3_FIFO_FULL', - 304: 'PH_SC2_PA3_NULL_WE', - 305: 'PH_SC2_PA3_EVENT_WE', - 306: 'PH_SC2_PA3_FPOV_WE', - 307: 'PH_SC2_PA3_LPOV_WE', - 308: 'PH_SC2_PA3_EOP_WE', - 309: 'PH_SC2_PA3_DATA_FIFO_EOP_RD', - 310: 'PH_SC2_PA3_EOPG_WE', - 311: 'PH_SC2_PA3_DEALLOC_4_0_RD', - 312: 'PH_SC2_PA4_DATA_FIFO_RD', - 313: 'PH_SC2_PA4_DATA_FIFO_WE', - 314: 'PH_SC2_PA4_FIFO_EMPTY', - 315: 'PH_SC2_PA4_FIFO_FULL', - 316: 'PH_SC2_PA4_NULL_WE', - 317: 'PH_SC2_PA4_EVENT_WE', - 318: 'PH_SC2_PA4_FPOV_WE', - 319: 'PH_SC2_PA4_LPOV_WE', - 320: 'PH_SC2_PA4_EOP_WE', - 321: 'PH_SC2_PA4_DATA_FIFO_EOP_RD', - 322: 'PH_SC2_PA4_EOPG_WE', - 323: 'PH_SC2_PA4_DEALLOC_4_0_RD', - 324: 'PH_SC2_PA5_DATA_FIFO_RD', - 325: 'PH_SC2_PA5_DATA_FIFO_WE', - 326: 'PH_SC2_PA5_FIFO_EMPTY', - 327: 'PH_SC2_PA5_FIFO_FULL', - 328: 'PH_SC2_PA5_NULL_WE', - 329: 'PH_SC2_PA5_EVENT_WE', - 330: 'PH_SC2_PA5_FPOV_WE', - 331: 'PH_SC2_PA5_LPOV_WE', - 332: 'PH_SC2_PA5_EOP_WE', - 333: 'PH_SC2_PA5_DATA_FIFO_EOP_RD', - 334: 'PH_SC2_PA5_EOPG_WE', - 335: 'PH_SC2_PA5_DEALLOC_4_0_RD', - 336: 'PH_SC2_PA6_DATA_FIFO_RD', - 337: 'PH_SC2_PA6_DATA_FIFO_WE', - 338: 'PH_SC2_PA6_FIFO_EMPTY', - 339: 'PH_SC2_PA6_FIFO_FULL', - 340: 'PH_SC2_PA6_NULL_WE', - 341: 'PH_SC2_PA6_EVENT_WE', - 342: 'PH_SC2_PA6_FPOV_WE', - 343: 'PH_SC2_PA6_LPOV_WE', - 344: 'PH_SC2_PA6_EOP_WE', - 345: 'PH_SC2_PA6_DATA_FIFO_EOP_RD', - 346: 'PH_SC2_PA6_EOPG_WE', - 347: 'PH_SC2_PA6_DEALLOC_4_0_RD', - 348: 'PH_SC2_PA7_DATA_FIFO_RD', - 349: 'PH_SC2_PA7_DATA_FIFO_WE', - 350: 'PH_SC2_PA7_FIFO_EMPTY', - 351: 'PH_SC2_PA7_FIFO_FULL', - 352: 'PH_SC2_PA7_NULL_WE', - 353: 'PH_SC2_PA7_EVENT_WE', - 354: 'PH_SC2_PA7_FPOV_WE', - 355: 'PH_SC2_PA7_LPOV_WE', - 356: 'PH_SC2_PA7_EOP_WE', - 357: 'PH_SC2_PA7_DATA_FIFO_EOP_RD', - 358: 'PH_SC2_PA7_EOPG_WE', - 359: 'PH_SC2_PA7_DEALLOC_4_0_RD', - 360: 'PH_SC3_SRPS_WINDOW_VALID', - 361: 'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 362: 'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 363: 'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 364: 'PH_SC3_ARB_STALLED_FROM_BELOW', - 365: 'PH_SC3_ARB_STARVED_FROM_ABOVE', - 366: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 367: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 368: 'PH_SC3_ARB_BUSY', - 369: 'PH_SC3_ARB_PA_BUSY_SOP', - 370: 'PH_SC3_ARB_EOP_POP_SYNC_POP', - 371: 'PH_SC3_ARB_EVENT_SYNC_POP', - 372: 'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 373: 'PH_SC3_EOP_SYNC_WINDOW', - 374: 'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 375: 'PH_SC3_BUSY_CNT_NOT_ZERO', - 376: 'PH_SC3_SEND', - 377: 'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 378: 'PH_SC3_CREDIT_AT_MAX', - 379: 'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 380: 'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 381: 'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 382: 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION', - 383: 'PH_SC3_GFX_PIPE1_TO_0_TRANSITION', - 384: 'PH_SC3_PA0_DATA_FIFO_RD', - 385: 'PH_SC3_PA0_DATA_FIFO_WE', - 386: 'PH_SC3_PA0_FIFO_EMPTY', - 387: 'PH_SC3_PA0_FIFO_FULL', - 388: 'PH_SC3_PA0_NULL_WE', - 389: 'PH_SC3_PA0_EVENT_WE', - 390: 'PH_SC3_PA0_FPOV_WE', - 391: 'PH_SC3_PA0_LPOV_WE', - 392: 'PH_SC3_PA0_EOP_WE', - 393: 'PH_SC3_PA0_DATA_FIFO_EOP_RD', - 394: 'PH_SC3_PA0_EOPG_WE', - 395: 'PH_SC3_PA0_DEALLOC_4_0_RD', - 396: 'PH_SC3_PA1_DATA_FIFO_RD', - 397: 'PH_SC3_PA1_DATA_FIFO_WE', - 398: 'PH_SC3_PA1_FIFO_EMPTY', - 399: 'PH_SC3_PA1_FIFO_FULL', - 400: 'PH_SC3_PA1_NULL_WE', - 401: 'PH_SC3_PA1_EVENT_WE', - 402: 'PH_SC3_PA1_FPOV_WE', - 403: 'PH_SC3_PA1_LPOV_WE', - 404: 'PH_SC3_PA1_EOP_WE', - 405: 'PH_SC3_PA1_DATA_FIFO_EOP_RD', - 406: 'PH_SC3_PA1_EOPG_WE', - 407: 'PH_SC3_PA1_DEALLOC_4_0_RD', - 408: 'PH_SC3_PA2_DATA_FIFO_RD', - 409: 'PH_SC3_PA2_DATA_FIFO_WE', - 410: 'PH_SC3_PA2_FIFO_EMPTY', - 411: 'PH_SC3_PA2_FIFO_FULL', - 412: 'PH_SC3_PA2_NULL_WE', - 413: 'PH_SC3_PA2_EVENT_WE', - 414: 'PH_SC3_PA2_FPOV_WE', - 415: 'PH_SC3_PA2_LPOV_WE', - 416: 'PH_SC3_PA2_EOP_WE', - 417: 'PH_SC3_PA2_DATA_FIFO_EOP_RD', - 418: 'PH_SC3_PA2_EOPG_WE', - 419: 'PH_SC3_PA2_DEALLOC_4_0_RD', - 420: 'PH_SC3_PA3_DATA_FIFO_RD', - 421: 'PH_SC3_PA3_DATA_FIFO_WE', - 422: 'PH_SC3_PA3_FIFO_EMPTY', - 423: 'PH_SC3_PA3_FIFO_FULL', - 424: 'PH_SC3_PA3_NULL_WE', - 425: 'PH_SC3_PA3_EVENT_WE', - 426: 'PH_SC3_PA3_FPOV_WE', - 427: 'PH_SC3_PA3_LPOV_WE', - 428: 'PH_SC3_PA3_EOP_WE', - 429: 'PH_SC3_PA3_DATA_FIFO_EOP_RD', - 430: 'PH_SC3_PA3_EOPG_WE', - 431: 'PH_SC3_PA3_DEALLOC_4_0_RD', - 432: 'PH_SC3_PA4_DATA_FIFO_RD', - 433: 'PH_SC3_PA4_DATA_FIFO_WE', - 434: 'PH_SC3_PA4_FIFO_EMPTY', - 435: 'PH_SC3_PA4_FIFO_FULL', - 436: 'PH_SC3_PA4_NULL_WE', - 437: 'PH_SC3_PA4_EVENT_WE', - 438: 'PH_SC3_PA4_FPOV_WE', - 439: 'PH_SC3_PA4_LPOV_WE', - 440: 'PH_SC3_PA4_EOP_WE', - 441: 'PH_SC3_PA4_DATA_FIFO_EOP_RD', - 442: 'PH_SC3_PA4_EOPG_WE', - 443: 'PH_SC3_PA4_DEALLOC_4_0_RD', - 444: 'PH_SC3_PA5_DATA_FIFO_RD', - 445: 'PH_SC3_PA5_DATA_FIFO_WE', - 446: 'PH_SC3_PA5_FIFO_EMPTY', - 447: 'PH_SC3_PA5_FIFO_FULL', - 448: 'PH_SC3_PA5_NULL_WE', - 449: 'PH_SC3_PA5_EVENT_WE', - 450: 'PH_SC3_PA5_FPOV_WE', - 451: 'PH_SC3_PA5_LPOV_WE', - 452: 'PH_SC3_PA5_EOP_WE', - 453: 'PH_SC3_PA5_DATA_FIFO_EOP_RD', - 454: 'PH_SC3_PA5_EOPG_WE', - 455: 'PH_SC3_PA5_DEALLOC_4_0_RD', - 456: 'PH_SC3_PA6_DATA_FIFO_RD', - 457: 'PH_SC3_PA6_DATA_FIFO_WE', - 458: 'PH_SC3_PA6_FIFO_EMPTY', - 459: 'PH_SC3_PA6_FIFO_FULL', - 460: 'PH_SC3_PA6_NULL_WE', - 461: 'PH_SC3_PA6_EVENT_WE', - 462: 'PH_SC3_PA6_FPOV_WE', - 463: 'PH_SC3_PA6_LPOV_WE', - 464: 'PH_SC3_PA6_EOP_WE', - 465: 'PH_SC3_PA6_DATA_FIFO_EOP_RD', - 466: 'PH_SC3_PA6_EOPG_WE', - 467: 'PH_SC3_PA6_DEALLOC_4_0_RD', - 468: 'PH_SC3_PA7_DATA_FIFO_RD', - 469: 'PH_SC3_PA7_DATA_FIFO_WE', - 470: 'PH_SC3_PA7_FIFO_EMPTY', - 471: 'PH_SC3_PA7_FIFO_FULL', - 472: 'PH_SC3_PA7_NULL_WE', - 473: 'PH_SC3_PA7_EVENT_WE', - 474: 'PH_SC3_PA7_FPOV_WE', - 475: 'PH_SC3_PA7_LPOV_WE', - 476: 'PH_SC3_PA7_EOP_WE', - 477: 'PH_SC3_PA7_DATA_FIFO_EOP_RD', - 478: 'PH_SC3_PA7_EOPG_WE', - 479: 'PH_SC3_PA7_DEALLOC_4_0_RD', - 480: 'PH_SC4_SRPS_WINDOW_VALID', - 481: 'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 482: 'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 483: 'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 484: 'PH_SC4_ARB_STALLED_FROM_BELOW', - 485: 'PH_SC4_ARB_STARVED_FROM_ABOVE', - 486: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 487: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 488: 'PH_SC4_ARB_BUSY', - 489: 'PH_SC4_ARB_PA_BUSY_SOP', - 490: 'PH_SC4_ARB_EOP_POP_SYNC_POP', - 491: 'PH_SC4_ARB_EVENT_SYNC_POP', - 492: 'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 493: 'PH_SC4_EOP_SYNC_WINDOW', - 494: 'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 495: 'PH_SC4_BUSY_CNT_NOT_ZERO', - 496: 'PH_SC4_SEND', - 497: 'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 498: 'PH_SC4_CREDIT_AT_MAX', - 499: 'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 500: 'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 501: 'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 502: 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION', - 503: 'PH_SC4_GFX_PIPE1_TO_0_TRANSITION', - 504: 'PH_SC4_PA0_DATA_FIFO_RD', - 505: 'PH_SC4_PA0_DATA_FIFO_WE', - 506: 'PH_SC4_PA0_FIFO_EMPTY', - 507: 'PH_SC4_PA0_FIFO_FULL', - 508: 'PH_SC4_PA0_NULL_WE', - 509: 'PH_SC4_PA0_EVENT_WE', - 510: 'PH_SC4_PA0_FPOV_WE', - 511: 'PH_SC4_PA0_LPOV_WE', - 512: 'PH_SC4_PA0_EOP_WE', - 513: 'PH_SC4_PA0_DATA_FIFO_EOP_RD', - 514: 'PH_SC4_PA0_EOPG_WE', - 515: 'PH_SC4_PA0_DEALLOC_4_0_RD', - 516: 'PH_SC4_PA1_DATA_FIFO_RD', - 517: 'PH_SC4_PA1_DATA_FIFO_WE', - 518: 'PH_SC4_PA1_FIFO_EMPTY', - 519: 'PH_SC4_PA1_FIFO_FULL', - 520: 'PH_SC4_PA1_NULL_WE', - 521: 'PH_SC4_PA1_EVENT_WE', - 522: 'PH_SC4_PA1_FPOV_WE', - 523: 'PH_SC4_PA1_LPOV_WE', - 524: 'PH_SC4_PA1_EOP_WE', - 525: 'PH_SC4_PA1_DATA_FIFO_EOP_RD', - 526: 'PH_SC4_PA1_EOPG_WE', - 527: 'PH_SC4_PA1_DEALLOC_4_0_RD', - 528: 'PH_SC4_PA2_DATA_FIFO_RD', - 529: 'PH_SC4_PA2_DATA_FIFO_WE', - 530: 'PH_SC4_PA2_FIFO_EMPTY', - 531: 'PH_SC4_PA2_FIFO_FULL', - 532: 'PH_SC4_PA2_NULL_WE', - 533: 'PH_SC4_PA2_EVENT_WE', - 534: 'PH_SC4_PA2_FPOV_WE', - 535: 'PH_SC4_PA2_LPOV_WE', - 536: 'PH_SC4_PA2_EOP_WE', - 537: 'PH_SC4_PA2_DATA_FIFO_EOP_RD', - 538: 'PH_SC4_PA2_EOPG_WE', - 539: 'PH_SC4_PA2_DEALLOC_4_0_RD', - 540: 'PH_SC4_PA3_DATA_FIFO_RD', - 541: 'PH_SC4_PA3_DATA_FIFO_WE', - 542: 'PH_SC4_PA3_FIFO_EMPTY', - 543: 'PH_SC4_PA3_FIFO_FULL', - 544: 'PH_SC4_PA3_NULL_WE', - 545: 'PH_SC4_PA3_EVENT_WE', - 546: 'PH_SC4_PA3_FPOV_WE', - 547: 'PH_SC4_PA3_LPOV_WE', - 548: 'PH_SC4_PA3_EOP_WE', - 549: 'PH_SC4_PA3_DATA_FIFO_EOP_RD', - 550: 'PH_SC4_PA3_EOPG_WE', - 551: 'PH_SC4_PA3_DEALLOC_4_0_RD', - 552: 'PH_SC4_PA4_DATA_FIFO_RD', - 553: 'PH_SC4_PA4_DATA_FIFO_WE', - 554: 'PH_SC4_PA4_FIFO_EMPTY', - 555: 'PH_SC4_PA4_FIFO_FULL', - 556: 'PH_SC4_PA4_NULL_WE', - 557: 'PH_SC4_PA4_EVENT_WE', - 558: 'PH_SC4_PA4_FPOV_WE', - 559: 'PH_SC4_PA4_LPOV_WE', - 560: 'PH_SC4_PA4_EOP_WE', - 561: 'PH_SC4_PA4_DATA_FIFO_EOP_RD', - 562: 'PH_SC4_PA4_EOPG_WE', - 563: 'PH_SC4_PA4_DEALLOC_4_0_RD', - 564: 'PH_SC4_PA5_DATA_FIFO_RD', - 565: 'PH_SC4_PA5_DATA_FIFO_WE', - 566: 'PH_SC4_PA5_FIFO_EMPTY', - 567: 'PH_SC4_PA5_FIFO_FULL', - 568: 'PH_SC4_PA5_NULL_WE', - 569: 'PH_SC4_PA5_EVENT_WE', - 570: 'PH_SC4_PA5_FPOV_WE', - 571: 'PH_SC4_PA5_LPOV_WE', - 572: 'PH_SC4_PA5_EOP_WE', - 573: 'PH_SC4_PA5_DATA_FIFO_EOP_RD', - 574: 'PH_SC4_PA5_EOPG_WE', - 575: 'PH_SC4_PA5_DEALLOC_4_0_RD', - 576: 'PH_SC4_PA6_DATA_FIFO_RD', - 577: 'PH_SC4_PA6_DATA_FIFO_WE', - 578: 'PH_SC4_PA6_FIFO_EMPTY', - 579: 'PH_SC4_PA6_FIFO_FULL', - 580: 'PH_SC4_PA6_NULL_WE', - 581: 'PH_SC4_PA6_EVENT_WE', - 582: 'PH_SC4_PA6_FPOV_WE', - 583: 'PH_SC4_PA6_LPOV_WE', - 584: 'PH_SC4_PA6_EOP_WE', - 585: 'PH_SC4_PA6_DATA_FIFO_EOP_RD', - 586: 'PH_SC4_PA6_EOPG_WE', - 587: 'PH_SC4_PA6_DEALLOC_4_0_RD', - 588: 'PH_SC4_PA7_DATA_FIFO_RD', - 589: 'PH_SC4_PA7_DATA_FIFO_WE', - 590: 'PH_SC4_PA7_FIFO_EMPTY', - 591: 'PH_SC4_PA7_FIFO_FULL', - 592: 'PH_SC4_PA7_NULL_WE', - 593: 'PH_SC4_PA7_EVENT_WE', - 594: 'PH_SC4_PA7_FPOV_WE', - 595: 'PH_SC4_PA7_LPOV_WE', - 596: 'PH_SC4_PA7_EOP_WE', - 597: 'PH_SC4_PA7_DATA_FIFO_EOP_RD', - 598: 'PH_SC4_PA7_EOPG_WE', - 599: 'PH_SC4_PA7_DEALLOC_4_0_RD', - 600: 'PH_SC5_SRPS_WINDOW_VALID', - 601: 'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 602: 'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 603: 'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 604: 'PH_SC5_ARB_STALLED_FROM_BELOW', - 605: 'PH_SC5_ARB_STARVED_FROM_ABOVE', - 606: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 607: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 608: 'PH_SC5_ARB_BUSY', - 609: 'PH_SC5_ARB_PA_BUSY_SOP', - 610: 'PH_SC5_ARB_EOP_POP_SYNC_POP', - 611: 'PH_SC5_ARB_EVENT_SYNC_POP', - 612: 'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 613: 'PH_SC5_EOP_SYNC_WINDOW', - 614: 'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 615: 'PH_SC5_BUSY_CNT_NOT_ZERO', - 616: 'PH_SC5_SEND', - 617: 'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 618: 'PH_SC5_CREDIT_AT_MAX', - 619: 'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 620: 'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 621: 'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 622: 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION', - 623: 'PH_SC5_GFX_PIPE1_TO_0_TRANSITION', - 624: 'PH_SC5_PA0_DATA_FIFO_RD', - 625: 'PH_SC5_PA0_DATA_FIFO_WE', - 626: 'PH_SC5_PA0_FIFO_EMPTY', - 627: 'PH_SC5_PA0_FIFO_FULL', - 628: 'PH_SC5_PA0_NULL_WE', - 629: 'PH_SC5_PA0_EVENT_WE', - 630: 'PH_SC5_PA0_FPOV_WE', - 631: 'PH_SC5_PA0_LPOV_WE', - 632: 'PH_SC5_PA0_EOP_WE', - 633: 'PH_SC5_PA0_DATA_FIFO_EOP_RD', - 634: 'PH_SC5_PA0_EOPG_WE', - 635: 'PH_SC5_PA0_DEALLOC_4_0_RD', - 636: 'PH_SC5_PA1_DATA_FIFO_RD', - 637: 'PH_SC5_PA1_DATA_FIFO_WE', - 638: 'PH_SC5_PA1_FIFO_EMPTY', - 639: 'PH_SC5_PA1_FIFO_FULL', - 640: 'PH_SC5_PA1_NULL_WE', - 641: 'PH_SC5_PA1_EVENT_WE', - 642: 'PH_SC5_PA1_FPOV_WE', - 643: 'PH_SC5_PA1_LPOV_WE', - 644: 'PH_SC5_PA1_EOP_WE', - 645: 'PH_SC5_PA1_DATA_FIFO_EOP_RD', - 646: 'PH_SC5_PA1_EOPG_WE', - 647: 'PH_SC5_PA1_DEALLOC_4_0_RD', - 648: 'PH_SC5_PA2_DATA_FIFO_RD', - 649: 'PH_SC5_PA2_DATA_FIFO_WE', - 650: 'PH_SC5_PA2_FIFO_EMPTY', - 651: 'PH_SC5_PA2_FIFO_FULL', - 652: 'PH_SC5_PA2_NULL_WE', - 653: 'PH_SC5_PA2_EVENT_WE', - 654: 'PH_SC5_PA2_FPOV_WE', - 655: 'PH_SC5_PA2_LPOV_WE', - 656: 'PH_SC5_PA2_EOP_WE', - 657: 'PH_SC5_PA2_DATA_FIFO_EOP_RD', - 658: 'PH_SC5_PA2_EOPG_WE', - 659: 'PH_SC5_PA2_DEALLOC_4_0_RD', - 660: 'PH_SC5_PA3_DATA_FIFO_RD', - 661: 'PH_SC5_PA3_DATA_FIFO_WE', - 662: 'PH_SC5_PA3_FIFO_EMPTY', - 663: 'PH_SC5_PA3_FIFO_FULL', - 664: 'PH_SC5_PA3_NULL_WE', - 665: 'PH_SC5_PA3_EVENT_WE', - 666: 'PH_SC5_PA3_FPOV_WE', - 667: 'PH_SC5_PA3_LPOV_WE', - 668: 'PH_SC5_PA3_EOP_WE', - 669: 'PH_SC5_PA3_DATA_FIFO_EOP_RD', - 670: 'PH_SC5_PA3_EOPG_WE', - 671: 'PH_SC5_PA3_DEALLOC_4_0_RD', - 672: 'PH_SC5_PA4_DATA_FIFO_RD', - 673: 'PH_SC5_PA4_DATA_FIFO_WE', - 674: 'PH_SC5_PA4_FIFO_EMPTY', - 675: 'PH_SC5_PA4_FIFO_FULL', - 676: 'PH_SC5_PA4_NULL_WE', - 677: 'PH_SC5_PA4_EVENT_WE', - 678: 'PH_SC5_PA4_FPOV_WE', - 679: 'PH_SC5_PA4_LPOV_WE', - 680: 'PH_SC5_PA4_EOP_WE', - 681: 'PH_SC5_PA4_DATA_FIFO_EOP_RD', - 682: 'PH_SC5_PA4_EOPG_WE', - 683: 'PH_SC5_PA4_DEALLOC_4_0_RD', - 684: 'PH_SC5_PA5_DATA_FIFO_RD', - 685: 'PH_SC5_PA5_DATA_FIFO_WE', - 686: 'PH_SC5_PA5_FIFO_EMPTY', - 687: 'PH_SC5_PA5_FIFO_FULL', - 688: 'PH_SC5_PA5_NULL_WE', - 689: 'PH_SC5_PA5_EVENT_WE', - 690: 'PH_SC5_PA5_FPOV_WE', - 691: 'PH_SC5_PA5_LPOV_WE', - 692: 'PH_SC5_PA5_EOP_WE', - 693: 'PH_SC5_PA5_DATA_FIFO_EOP_RD', - 694: 'PH_SC5_PA5_EOPG_WE', - 695: 'PH_SC5_PA5_DEALLOC_4_0_RD', - 696: 'PH_SC5_PA6_DATA_FIFO_RD', - 697: 'PH_SC5_PA6_DATA_FIFO_WE', - 698: 'PH_SC5_PA6_FIFO_EMPTY', - 699: 'PH_SC5_PA6_FIFO_FULL', - 700: 'PH_SC5_PA6_NULL_WE', - 701: 'PH_SC5_PA6_EVENT_WE', - 702: 'PH_SC5_PA6_FPOV_WE', - 703: 'PH_SC5_PA6_LPOV_WE', - 704: 'PH_SC5_PA6_EOP_WE', - 705: 'PH_SC5_PA6_DATA_FIFO_EOP_RD', - 706: 'PH_SC5_PA6_EOPG_WE', - 707: 'PH_SC5_PA6_DEALLOC_4_0_RD', - 708: 'PH_SC5_PA7_DATA_FIFO_RD', - 709: 'PH_SC5_PA7_DATA_FIFO_WE', - 710: 'PH_SC5_PA7_FIFO_EMPTY', - 711: 'PH_SC5_PA7_FIFO_FULL', - 712: 'PH_SC5_PA7_NULL_WE', - 713: 'PH_SC5_PA7_EVENT_WE', - 714: 'PH_SC5_PA7_FPOV_WE', - 715: 'PH_SC5_PA7_LPOV_WE', - 716: 'PH_SC5_PA7_EOP_WE', - 717: 'PH_SC5_PA7_DATA_FIFO_EOP_RD', - 718: 'PH_SC5_PA7_EOPG_WE', - 719: 'PH_SC5_PA7_DEALLOC_4_0_RD', - 720: 'PH_SC6_SRPS_WINDOW_VALID', - 721: 'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 722: 'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 723: 'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 724: 'PH_SC6_ARB_STALLED_FROM_BELOW', - 725: 'PH_SC6_ARB_STARVED_FROM_ABOVE', - 726: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 727: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 728: 'PH_SC6_ARB_BUSY', - 729: 'PH_SC6_ARB_PA_BUSY_SOP', - 730: 'PH_SC6_ARB_EOP_POP_SYNC_POP', - 731: 'PH_SC6_ARB_EVENT_SYNC_POP', - 732: 'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 733: 'PH_SC6_EOP_SYNC_WINDOW', - 734: 'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 735: 'PH_SC6_BUSY_CNT_NOT_ZERO', - 736: 'PH_SC6_SEND', - 737: 'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 738: 'PH_SC6_CREDIT_AT_MAX', - 739: 'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 740: 'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 741: 'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 742: 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION', - 743: 'PH_SC6_GFX_PIPE1_TO_0_TRANSITION', - 744: 'PH_SC6_PA0_DATA_FIFO_RD', - 745: 'PH_SC6_PA0_DATA_FIFO_WE', - 746: 'PH_SC6_PA0_FIFO_EMPTY', - 747: 'PH_SC6_PA0_FIFO_FULL', - 748: 'PH_SC6_PA0_NULL_WE', - 749: 'PH_SC6_PA0_EVENT_WE', - 750: 'PH_SC6_PA0_FPOV_WE', - 751: 'PH_SC6_PA0_LPOV_WE', - 752: 'PH_SC6_PA0_EOP_WE', - 753: 'PH_SC6_PA0_DATA_FIFO_EOP_RD', - 754: 'PH_SC6_PA0_EOPG_WE', - 755: 'PH_SC6_PA0_DEALLOC_4_0_RD', - 756: 'PH_SC6_PA1_DATA_FIFO_RD', - 757: 'PH_SC6_PA1_DATA_FIFO_WE', - 758: 'PH_SC6_PA1_FIFO_EMPTY', - 759: 'PH_SC6_PA1_FIFO_FULL', - 760: 'PH_SC6_PA1_NULL_WE', - 761: 'PH_SC6_PA1_EVENT_WE', - 762: 'PH_SC6_PA1_FPOV_WE', - 763: 'PH_SC6_PA1_LPOV_WE', - 764: 'PH_SC6_PA1_EOP_WE', - 765: 'PH_SC6_PA1_DATA_FIFO_EOP_RD', - 766: 'PH_SC6_PA1_EOPG_WE', - 767: 'PH_SC6_PA1_DEALLOC_4_0_RD', - 768: 'PH_SC6_PA2_DATA_FIFO_RD', - 769: 'PH_SC6_PA2_DATA_FIFO_WE', - 770: 'PH_SC6_PA2_FIFO_EMPTY', - 771: 'PH_SC6_PA2_FIFO_FULL', - 772: 'PH_SC6_PA2_NULL_WE', - 773: 'PH_SC6_PA2_EVENT_WE', - 774: 'PH_SC6_PA2_FPOV_WE', - 775: 'PH_SC6_PA2_LPOV_WE', - 776: 'PH_SC6_PA2_EOP_WE', - 777: 'PH_SC6_PA2_DATA_FIFO_EOP_RD', - 778: 'PH_SC6_PA2_EOPG_WE', - 779: 'PH_SC6_PA2_DEALLOC_4_0_RD', - 780: 'PH_SC6_PA3_DATA_FIFO_RD', - 781: 'PH_SC6_PA3_DATA_FIFO_WE', - 782: 'PH_SC6_PA3_FIFO_EMPTY', - 783: 'PH_SC6_PA3_FIFO_FULL', - 784: 'PH_SC6_PA3_NULL_WE', - 785: 'PH_SC6_PA3_EVENT_WE', - 786: 'PH_SC6_PA3_FPOV_WE', - 787: 'PH_SC6_PA3_LPOV_WE', - 788: 'PH_SC6_PA3_EOP_WE', - 789: 'PH_SC6_PA3_DATA_FIFO_EOP_RD', - 790: 'PH_SC6_PA3_EOPG_WE', - 791: 'PH_SC6_PA3_DEALLOC_4_0_RD', - 792: 'PH_SC6_PA4_DATA_FIFO_RD', - 793: 'PH_SC6_PA4_DATA_FIFO_WE', - 794: 'PH_SC6_PA4_FIFO_EMPTY', - 795: 'PH_SC6_PA4_FIFO_FULL', - 796: 'PH_SC6_PA4_NULL_WE', - 797: 'PH_SC6_PA4_EVENT_WE', - 798: 'PH_SC6_PA4_FPOV_WE', - 799: 'PH_SC6_PA4_LPOV_WE', - 800: 'PH_SC6_PA4_EOP_WE', - 801: 'PH_SC6_PA4_DATA_FIFO_EOP_RD', - 802: 'PH_SC6_PA4_EOPG_WE', - 803: 'PH_SC6_PA4_DEALLOC_4_0_RD', - 804: 'PH_SC6_PA5_DATA_FIFO_RD', - 805: 'PH_SC6_PA5_DATA_FIFO_WE', - 806: 'PH_SC6_PA5_FIFO_EMPTY', - 807: 'PH_SC6_PA5_FIFO_FULL', - 808: 'PH_SC6_PA5_NULL_WE', - 809: 'PH_SC6_PA5_EVENT_WE', - 810: 'PH_SC6_PA5_FPOV_WE', - 811: 'PH_SC6_PA5_LPOV_WE', - 812: 'PH_SC6_PA5_EOP_WE', - 813: 'PH_SC6_PA5_DATA_FIFO_EOP_RD', - 814: 'PH_SC6_PA5_EOPG_WE', - 815: 'PH_SC6_PA5_DEALLOC_4_0_RD', - 816: 'PH_SC6_PA6_DATA_FIFO_RD', - 817: 'PH_SC6_PA6_DATA_FIFO_WE', - 818: 'PH_SC6_PA6_FIFO_EMPTY', - 819: 'PH_SC6_PA6_FIFO_FULL', - 820: 'PH_SC6_PA6_NULL_WE', - 821: 'PH_SC6_PA6_EVENT_WE', - 822: 'PH_SC6_PA6_FPOV_WE', - 823: 'PH_SC6_PA6_LPOV_WE', - 824: 'PH_SC6_PA6_EOP_WE', - 825: 'PH_SC6_PA6_DATA_FIFO_EOP_RD', - 826: 'PH_SC6_PA6_EOPG_WE', - 827: 'PH_SC6_PA6_DEALLOC_4_0_RD', - 828: 'PH_SC6_PA7_DATA_FIFO_RD', - 829: 'PH_SC6_PA7_DATA_FIFO_WE', - 830: 'PH_SC6_PA7_FIFO_EMPTY', - 831: 'PH_SC6_PA7_FIFO_FULL', - 832: 'PH_SC6_PA7_NULL_WE', - 833: 'PH_SC6_PA7_EVENT_WE', - 834: 'PH_SC6_PA7_FPOV_WE', - 835: 'PH_SC6_PA7_LPOV_WE', - 836: 'PH_SC6_PA7_EOP_WE', - 837: 'PH_SC6_PA7_DATA_FIFO_EOP_RD', - 838: 'PH_SC6_PA7_EOPG_WE', - 839: 'PH_SC6_PA7_DEALLOC_4_0_RD', - 840: 'PH_SC7_SRPS_WINDOW_VALID', - 841: 'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 842: 'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 843: 'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 844: 'PH_SC7_ARB_STALLED_FROM_BELOW', - 845: 'PH_SC7_ARB_STARVED_FROM_ABOVE', - 846: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 847: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 848: 'PH_SC7_ARB_BUSY', - 849: 'PH_SC7_ARB_PA_BUSY_SOP', - 850: 'PH_SC7_ARB_EOP_POP_SYNC_POP', - 851: 'PH_SC7_ARB_EVENT_SYNC_POP', - 852: 'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 853: 'PH_SC7_EOP_SYNC_WINDOW', - 854: 'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 855: 'PH_SC7_BUSY_CNT_NOT_ZERO', - 856: 'PH_SC7_SEND', - 857: 'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 858: 'PH_SC7_CREDIT_AT_MAX', - 859: 'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 860: 'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 861: 'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 862: 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION', - 863: 'PH_SC7_GFX_PIPE1_TO_0_TRANSITION', - 864: 'PH_SC7_PA0_DATA_FIFO_RD', - 865: 'PH_SC7_PA0_DATA_FIFO_WE', - 866: 'PH_SC7_PA0_FIFO_EMPTY', - 867: 'PH_SC7_PA0_FIFO_FULL', - 868: 'PH_SC7_PA0_NULL_WE', - 869: 'PH_SC7_PA0_EVENT_WE', - 870: 'PH_SC7_PA0_FPOV_WE', - 871: 'PH_SC7_PA0_LPOV_WE', - 872: 'PH_SC7_PA0_EOP_WE', - 873: 'PH_SC7_PA0_DATA_FIFO_EOP_RD', - 874: 'PH_SC7_PA0_EOPG_WE', - 875: 'PH_SC7_PA0_DEALLOC_4_0_RD', - 876: 'PH_SC7_PA1_DATA_FIFO_RD', - 877: 'PH_SC7_PA1_DATA_FIFO_WE', - 878: 'PH_SC7_PA1_FIFO_EMPTY', - 879: 'PH_SC7_PA1_FIFO_FULL', - 880: 'PH_SC7_PA1_NULL_WE', - 881: 'PH_SC7_PA1_EVENT_WE', - 882: 'PH_SC7_PA1_FPOV_WE', - 883: 'PH_SC7_PA1_LPOV_WE', - 884: 'PH_SC7_PA1_EOP_WE', - 885: 'PH_SC7_PA1_DATA_FIFO_EOP_RD', - 886: 'PH_SC7_PA1_EOPG_WE', - 887: 'PH_SC7_PA1_DEALLOC_4_0_RD', - 888: 'PH_SC7_PA2_DATA_FIFO_RD', - 889: 'PH_SC7_PA2_DATA_FIFO_WE', - 890: 'PH_SC7_PA2_FIFO_EMPTY', - 891: 'PH_SC7_PA2_FIFO_FULL', - 892: 'PH_SC7_PA2_NULL_WE', - 893: 'PH_SC7_PA2_EVENT_WE', - 894: 'PH_SC7_PA2_FPOV_WE', - 895: 'PH_SC7_PA2_LPOV_WE', - 896: 'PH_SC7_PA2_EOP_WE', - 897: 'PH_SC7_PA2_DATA_FIFO_EOP_RD', - 898: 'PH_SC7_PA2_EOPG_WE', - 899: 'PH_SC7_PA2_DEALLOC_4_0_RD', - 900: 'PH_SC7_PA3_DATA_FIFO_RD', - 901: 'PH_SC7_PA3_DATA_FIFO_WE', - 902: 'PH_SC7_PA3_FIFO_EMPTY', - 903: 'PH_SC7_PA3_FIFO_FULL', - 904: 'PH_SC7_PA3_NULL_WE', - 905: 'PH_SC7_PA3_EVENT_WE', - 906: 'PH_SC7_PA3_FPOV_WE', - 907: 'PH_SC7_PA3_LPOV_WE', - 908: 'PH_SC7_PA3_EOP_WE', - 909: 'PH_SC7_PA3_DATA_FIFO_EOP_RD', - 910: 'PH_SC7_PA3_EOPG_WE', - 911: 'PH_SC7_PA3_DEALLOC_4_0_RD', - 912: 'PH_SC7_PA4_DATA_FIFO_RD', - 913: 'PH_SC7_PA4_DATA_FIFO_WE', - 914: 'PH_SC7_PA4_FIFO_EMPTY', - 915: 'PH_SC7_PA4_FIFO_FULL', - 916: 'PH_SC7_PA4_NULL_WE', - 917: 'PH_SC7_PA4_EVENT_WE', - 918: 'PH_SC7_PA4_FPOV_WE', - 919: 'PH_SC7_PA4_LPOV_WE', - 920: 'PH_SC7_PA4_EOP_WE', - 921: 'PH_SC7_PA4_DATA_FIFO_EOP_RD', - 922: 'PH_SC7_PA4_EOPG_WE', - 923: 'PH_SC7_PA4_DEALLOC_4_0_RD', - 924: 'PH_SC7_PA5_DATA_FIFO_RD', - 925: 'PH_SC7_PA5_DATA_FIFO_WE', - 926: 'PH_SC7_PA5_FIFO_EMPTY', - 927: 'PH_SC7_PA5_FIFO_FULL', - 928: 'PH_SC7_PA5_NULL_WE', - 929: 'PH_SC7_PA5_EVENT_WE', - 930: 'PH_SC7_PA5_FPOV_WE', - 931: 'PH_SC7_PA5_LPOV_WE', - 932: 'PH_SC7_PA5_EOP_WE', - 933: 'PH_SC7_PA5_DATA_FIFO_EOP_RD', - 934: 'PH_SC7_PA5_EOPG_WE', - 935: 'PH_SC7_PA5_DEALLOC_4_0_RD', - 936: 'PH_SC7_PA6_DATA_FIFO_RD', - 937: 'PH_SC7_PA6_DATA_FIFO_WE', - 938: 'PH_SC7_PA6_FIFO_EMPTY', - 939: 'PH_SC7_PA6_FIFO_FULL', - 940: 'PH_SC7_PA6_NULL_WE', - 941: 'PH_SC7_PA6_EVENT_WE', - 942: 'PH_SC7_PA6_FPOV_WE', - 943: 'PH_SC7_PA6_LPOV_WE', - 944: 'PH_SC7_PA6_EOP_WE', - 945: 'PH_SC7_PA6_DATA_FIFO_EOP_RD', - 946: 'PH_SC7_PA6_EOPG_WE', - 947: 'PH_SC7_PA6_DEALLOC_4_0_RD', - 948: 'PH_SC7_PA7_DATA_FIFO_RD', - 949: 'PH_SC7_PA7_DATA_FIFO_WE', - 950: 'PH_SC7_PA7_FIFO_EMPTY', - 951: 'PH_SC7_PA7_FIFO_FULL', - 952: 'PH_SC7_PA7_NULL_WE', - 953: 'PH_SC7_PA7_EVENT_WE', - 954: 'PH_SC7_PA7_FPOV_WE', - 955: 'PH_SC7_PA7_LPOV_WE', - 956: 'PH_SC7_PA7_EOP_WE', - 957: 'PH_SC7_PA7_DATA_FIFO_EOP_RD', - 958: 'PH_SC7_PA7_EOPG_WE', - 959: 'PH_SC7_PA7_DEALLOC_4_0_RD', -} -PH_SC0_SRPS_WINDOW_VALID = 0 -PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 -PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 -PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 -PH_SC0_ARB_STALLED_FROM_BELOW = 4 -PH_SC0_ARB_STARVED_FROM_ABOVE = 5 -PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 -PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 -PH_SC0_ARB_BUSY = 8 -PH_SC0_ARB_PA_BUSY_SOP = 9 -PH_SC0_ARB_EOP_POP_SYNC_POP = 10 -PH_SC0_ARB_EVENT_SYNC_POP = 11 -PH_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 -PH_SC0_EOP_SYNC_WINDOW = 13 -PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 -PH_SC0_BUSY_CNT_NOT_ZERO = 15 -PH_SC0_SEND = 16 -PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 -PH_SC0_CREDIT_AT_MAX = 18 -PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 -PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 20 -PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 21 -PH_SC0_GFX_PIPE0_TO_1_TRANSITION = 22 -PH_SC0_GFX_PIPE1_TO_0_TRANSITION = 23 -PH_SC0_PA0_DATA_FIFO_RD = 24 -PH_SC0_PA0_DATA_FIFO_WE = 25 -PH_SC0_PA0_FIFO_EMPTY = 26 -PH_SC0_PA0_FIFO_FULL = 27 -PH_SC0_PA0_NULL_WE = 28 -PH_SC0_PA0_EVENT_WE = 29 -PH_SC0_PA0_FPOV_WE = 30 -PH_SC0_PA0_LPOV_WE = 31 -PH_SC0_PA0_EOP_WE = 32 -PH_SC0_PA0_DATA_FIFO_EOP_RD = 33 -PH_SC0_PA0_EOPG_WE = 34 -PH_SC0_PA0_DEALLOC_4_0_RD = 35 -PH_SC0_PA1_DATA_FIFO_RD = 36 -PH_SC0_PA1_DATA_FIFO_WE = 37 -PH_SC0_PA1_FIFO_EMPTY = 38 -PH_SC0_PA1_FIFO_FULL = 39 -PH_SC0_PA1_NULL_WE = 40 -PH_SC0_PA1_EVENT_WE = 41 -PH_SC0_PA1_FPOV_WE = 42 -PH_SC0_PA1_LPOV_WE = 43 -PH_SC0_PA1_EOP_WE = 44 -PH_SC0_PA1_DATA_FIFO_EOP_RD = 45 -PH_SC0_PA1_EOPG_WE = 46 -PH_SC0_PA1_DEALLOC_4_0_RD = 47 -PH_SC0_PA2_DATA_FIFO_RD = 48 -PH_SC0_PA2_DATA_FIFO_WE = 49 -PH_SC0_PA2_FIFO_EMPTY = 50 -PH_SC0_PA2_FIFO_FULL = 51 -PH_SC0_PA2_NULL_WE = 52 -PH_SC0_PA2_EVENT_WE = 53 -PH_SC0_PA2_FPOV_WE = 54 -PH_SC0_PA2_LPOV_WE = 55 -PH_SC0_PA2_EOP_WE = 56 -PH_SC0_PA2_DATA_FIFO_EOP_RD = 57 -PH_SC0_PA2_EOPG_WE = 58 -PH_SC0_PA2_DEALLOC_4_0_RD = 59 -PH_SC0_PA3_DATA_FIFO_RD = 60 -PH_SC0_PA3_DATA_FIFO_WE = 61 -PH_SC0_PA3_FIFO_EMPTY = 62 -PH_SC0_PA3_FIFO_FULL = 63 -PH_SC0_PA3_NULL_WE = 64 -PH_SC0_PA3_EVENT_WE = 65 -PH_SC0_PA3_FPOV_WE = 66 -PH_SC0_PA3_LPOV_WE = 67 -PH_SC0_PA3_EOP_WE = 68 -PH_SC0_PA3_DATA_FIFO_EOP_RD = 69 -PH_SC0_PA3_EOPG_WE = 70 -PH_SC0_PA3_DEALLOC_4_0_RD = 71 -PH_SC0_PA4_DATA_FIFO_RD = 72 -PH_SC0_PA4_DATA_FIFO_WE = 73 -PH_SC0_PA4_FIFO_EMPTY = 74 -PH_SC0_PA4_FIFO_FULL = 75 -PH_SC0_PA4_NULL_WE = 76 -PH_SC0_PA4_EVENT_WE = 77 -PH_SC0_PA4_FPOV_WE = 78 -PH_SC0_PA4_LPOV_WE = 79 -PH_SC0_PA4_EOP_WE = 80 -PH_SC0_PA4_DATA_FIFO_EOP_RD = 81 -PH_SC0_PA4_EOPG_WE = 82 -PH_SC0_PA4_DEALLOC_4_0_RD = 83 -PH_SC0_PA5_DATA_FIFO_RD = 84 -PH_SC0_PA5_DATA_FIFO_WE = 85 -PH_SC0_PA5_FIFO_EMPTY = 86 -PH_SC0_PA5_FIFO_FULL = 87 -PH_SC0_PA5_NULL_WE = 88 -PH_SC0_PA5_EVENT_WE = 89 -PH_SC0_PA5_FPOV_WE = 90 -PH_SC0_PA5_LPOV_WE = 91 -PH_SC0_PA5_EOP_WE = 92 -PH_SC0_PA5_DATA_FIFO_EOP_RD = 93 -PH_SC0_PA5_EOPG_WE = 94 -PH_SC0_PA5_DEALLOC_4_0_RD = 95 -PH_SC0_PA6_DATA_FIFO_RD = 96 -PH_SC0_PA6_DATA_FIFO_WE = 97 -PH_SC0_PA6_FIFO_EMPTY = 98 -PH_SC0_PA6_FIFO_FULL = 99 -PH_SC0_PA6_NULL_WE = 100 -PH_SC0_PA6_EVENT_WE = 101 -PH_SC0_PA6_FPOV_WE = 102 -PH_SC0_PA6_LPOV_WE = 103 -PH_SC0_PA6_EOP_WE = 104 -PH_SC0_PA6_DATA_FIFO_EOP_RD = 105 -PH_SC0_PA6_EOPG_WE = 106 -PH_SC0_PA6_DEALLOC_4_0_RD = 107 -PH_SC0_PA7_DATA_FIFO_RD = 108 -PH_SC0_PA7_DATA_FIFO_WE = 109 -PH_SC0_PA7_FIFO_EMPTY = 110 -PH_SC0_PA7_FIFO_FULL = 111 -PH_SC0_PA7_NULL_WE = 112 -PH_SC0_PA7_EVENT_WE = 113 -PH_SC0_PA7_FPOV_WE = 114 -PH_SC0_PA7_LPOV_WE = 115 -PH_SC0_PA7_EOP_WE = 116 -PH_SC0_PA7_DATA_FIFO_EOP_RD = 117 -PH_SC0_PA7_EOPG_WE = 118 -PH_SC0_PA7_DEALLOC_4_0_RD = 119 -PH_SC1_SRPS_WINDOW_VALID = 120 -PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 -PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 -PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 -PH_SC1_ARB_STALLED_FROM_BELOW = 124 -PH_SC1_ARB_STARVED_FROM_ABOVE = 125 -PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 -PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 -PH_SC1_ARB_BUSY = 128 -PH_SC1_ARB_PA_BUSY_SOP = 129 -PH_SC1_ARB_EOP_POP_SYNC_POP = 130 -PH_SC1_ARB_EVENT_SYNC_POP = 131 -PH_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 -PH_SC1_EOP_SYNC_WINDOW = 133 -PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 -PH_SC1_BUSY_CNT_NOT_ZERO = 135 -PH_SC1_SEND = 136 -PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 -PH_SC1_CREDIT_AT_MAX = 138 -PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 -PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 140 -PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 141 -PH_SC1_GFX_PIPE0_TO_1_TRANSITION = 142 -PH_SC1_GFX_PIPE1_TO_0_TRANSITION = 143 -PH_SC1_PA0_DATA_FIFO_RD = 144 -PH_SC1_PA0_DATA_FIFO_WE = 145 -PH_SC1_PA0_FIFO_EMPTY = 146 -PH_SC1_PA0_FIFO_FULL = 147 -PH_SC1_PA0_NULL_WE = 148 -PH_SC1_PA0_EVENT_WE = 149 -PH_SC1_PA0_FPOV_WE = 150 -PH_SC1_PA0_LPOV_WE = 151 -PH_SC1_PA0_EOP_WE = 152 -PH_SC1_PA0_DATA_FIFO_EOP_RD = 153 -PH_SC1_PA0_EOPG_WE = 154 -PH_SC1_PA0_DEALLOC_4_0_RD = 155 -PH_SC1_PA1_DATA_FIFO_RD = 156 -PH_SC1_PA1_DATA_FIFO_WE = 157 -PH_SC1_PA1_FIFO_EMPTY = 158 -PH_SC1_PA1_FIFO_FULL = 159 -PH_SC1_PA1_NULL_WE = 160 -PH_SC1_PA1_EVENT_WE = 161 -PH_SC1_PA1_FPOV_WE = 162 -PH_SC1_PA1_LPOV_WE = 163 -PH_SC1_PA1_EOP_WE = 164 -PH_SC1_PA1_DATA_FIFO_EOP_RD = 165 -PH_SC1_PA1_EOPG_WE = 166 -PH_SC1_PA1_DEALLOC_4_0_RD = 167 -PH_SC1_PA2_DATA_FIFO_RD = 168 -PH_SC1_PA2_DATA_FIFO_WE = 169 -PH_SC1_PA2_FIFO_EMPTY = 170 -PH_SC1_PA2_FIFO_FULL = 171 -PH_SC1_PA2_NULL_WE = 172 -PH_SC1_PA2_EVENT_WE = 173 -PH_SC1_PA2_FPOV_WE = 174 -PH_SC1_PA2_LPOV_WE = 175 -PH_SC1_PA2_EOP_WE = 176 -PH_SC1_PA2_DATA_FIFO_EOP_RD = 177 -PH_SC1_PA2_EOPG_WE = 178 -PH_SC1_PA2_DEALLOC_4_0_RD = 179 -PH_SC1_PA3_DATA_FIFO_RD = 180 -PH_SC1_PA3_DATA_FIFO_WE = 181 -PH_SC1_PA3_FIFO_EMPTY = 182 -PH_SC1_PA3_FIFO_FULL = 183 -PH_SC1_PA3_NULL_WE = 184 -PH_SC1_PA3_EVENT_WE = 185 -PH_SC1_PA3_FPOV_WE = 186 -PH_SC1_PA3_LPOV_WE = 187 -PH_SC1_PA3_EOP_WE = 188 -PH_SC1_PA3_DATA_FIFO_EOP_RD = 189 -PH_SC1_PA3_EOPG_WE = 190 -PH_SC1_PA3_DEALLOC_4_0_RD = 191 -PH_SC1_PA4_DATA_FIFO_RD = 192 -PH_SC1_PA4_DATA_FIFO_WE = 193 -PH_SC1_PA4_FIFO_EMPTY = 194 -PH_SC1_PA4_FIFO_FULL = 195 -PH_SC1_PA4_NULL_WE = 196 -PH_SC1_PA4_EVENT_WE = 197 -PH_SC1_PA4_FPOV_WE = 198 -PH_SC1_PA4_LPOV_WE = 199 -PH_SC1_PA4_EOP_WE = 200 -PH_SC1_PA4_DATA_FIFO_EOP_RD = 201 -PH_SC1_PA4_EOPG_WE = 202 -PH_SC1_PA4_DEALLOC_4_0_RD = 203 -PH_SC1_PA5_DATA_FIFO_RD = 204 -PH_SC1_PA5_DATA_FIFO_WE = 205 -PH_SC1_PA5_FIFO_EMPTY = 206 -PH_SC1_PA5_FIFO_FULL = 207 -PH_SC1_PA5_NULL_WE = 208 -PH_SC1_PA5_EVENT_WE = 209 -PH_SC1_PA5_FPOV_WE = 210 -PH_SC1_PA5_LPOV_WE = 211 -PH_SC1_PA5_EOP_WE = 212 -PH_SC1_PA5_DATA_FIFO_EOP_RD = 213 -PH_SC1_PA5_EOPG_WE = 214 -PH_SC1_PA5_DEALLOC_4_0_RD = 215 -PH_SC1_PA6_DATA_FIFO_RD = 216 -PH_SC1_PA6_DATA_FIFO_WE = 217 -PH_SC1_PA6_FIFO_EMPTY = 218 -PH_SC1_PA6_FIFO_FULL = 219 -PH_SC1_PA6_NULL_WE = 220 -PH_SC1_PA6_EVENT_WE = 221 -PH_SC1_PA6_FPOV_WE = 222 -PH_SC1_PA6_LPOV_WE = 223 -PH_SC1_PA6_EOP_WE = 224 -PH_SC1_PA6_DATA_FIFO_EOP_RD = 225 -PH_SC1_PA6_EOPG_WE = 226 -PH_SC1_PA6_DEALLOC_4_0_RD = 227 -PH_SC1_PA7_DATA_FIFO_RD = 228 -PH_SC1_PA7_DATA_FIFO_WE = 229 -PH_SC1_PA7_FIFO_EMPTY = 230 -PH_SC1_PA7_FIFO_FULL = 231 -PH_SC1_PA7_NULL_WE = 232 -PH_SC1_PA7_EVENT_WE = 233 -PH_SC1_PA7_FPOV_WE = 234 -PH_SC1_PA7_LPOV_WE = 235 -PH_SC1_PA7_EOP_WE = 236 -PH_SC1_PA7_DATA_FIFO_EOP_RD = 237 -PH_SC1_PA7_EOPG_WE = 238 -PH_SC1_PA7_DEALLOC_4_0_RD = 239 -PH_SC2_SRPS_WINDOW_VALID = 240 -PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 -PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 -PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 -PH_SC2_ARB_STALLED_FROM_BELOW = 244 -PH_SC2_ARB_STARVED_FROM_ABOVE = 245 -PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 -PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 -PH_SC2_ARB_BUSY = 248 -PH_SC2_ARB_PA_BUSY_SOP = 249 -PH_SC2_ARB_EOP_POP_SYNC_POP = 250 -PH_SC2_ARB_EVENT_SYNC_POP = 251 -PH_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 -PH_SC2_EOP_SYNC_WINDOW = 253 -PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 -PH_SC2_BUSY_CNT_NOT_ZERO = 255 -PH_SC2_SEND = 256 -PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 -PH_SC2_CREDIT_AT_MAX = 258 -PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 -PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 260 -PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 261 -PH_SC2_GFX_PIPE0_TO_1_TRANSITION = 262 -PH_SC2_GFX_PIPE1_TO_0_TRANSITION = 263 -PH_SC2_PA0_DATA_FIFO_RD = 264 -PH_SC2_PA0_DATA_FIFO_WE = 265 -PH_SC2_PA0_FIFO_EMPTY = 266 -PH_SC2_PA0_FIFO_FULL = 267 -PH_SC2_PA0_NULL_WE = 268 -PH_SC2_PA0_EVENT_WE = 269 -PH_SC2_PA0_FPOV_WE = 270 -PH_SC2_PA0_LPOV_WE = 271 -PH_SC2_PA0_EOP_WE = 272 -PH_SC2_PA0_DATA_FIFO_EOP_RD = 273 -PH_SC2_PA0_EOPG_WE = 274 -PH_SC2_PA0_DEALLOC_4_0_RD = 275 -PH_SC2_PA1_DATA_FIFO_RD = 276 -PH_SC2_PA1_DATA_FIFO_WE = 277 -PH_SC2_PA1_FIFO_EMPTY = 278 -PH_SC2_PA1_FIFO_FULL = 279 -PH_SC2_PA1_NULL_WE = 280 -PH_SC2_PA1_EVENT_WE = 281 -PH_SC2_PA1_FPOV_WE = 282 -PH_SC2_PA1_LPOV_WE = 283 -PH_SC2_PA1_EOP_WE = 284 -PH_SC2_PA1_DATA_FIFO_EOP_RD = 285 -PH_SC2_PA1_EOPG_WE = 286 -PH_SC2_PA1_DEALLOC_4_0_RD = 287 -PH_SC2_PA2_DATA_FIFO_RD = 288 -PH_SC2_PA2_DATA_FIFO_WE = 289 -PH_SC2_PA2_FIFO_EMPTY = 290 -PH_SC2_PA2_FIFO_FULL = 291 -PH_SC2_PA2_NULL_WE = 292 -PH_SC2_PA2_EVENT_WE = 293 -PH_SC2_PA2_FPOV_WE = 294 -PH_SC2_PA2_LPOV_WE = 295 -PH_SC2_PA2_EOP_WE = 296 -PH_SC2_PA2_DATA_FIFO_EOP_RD = 297 -PH_SC2_PA2_EOPG_WE = 298 -PH_SC2_PA2_DEALLOC_4_0_RD = 299 -PH_SC2_PA3_DATA_FIFO_RD = 300 -PH_SC2_PA3_DATA_FIFO_WE = 301 -PH_SC2_PA3_FIFO_EMPTY = 302 -PH_SC2_PA3_FIFO_FULL = 303 -PH_SC2_PA3_NULL_WE = 304 -PH_SC2_PA3_EVENT_WE = 305 -PH_SC2_PA3_FPOV_WE = 306 -PH_SC2_PA3_LPOV_WE = 307 -PH_SC2_PA3_EOP_WE = 308 -PH_SC2_PA3_DATA_FIFO_EOP_RD = 309 -PH_SC2_PA3_EOPG_WE = 310 -PH_SC2_PA3_DEALLOC_4_0_RD = 311 -PH_SC2_PA4_DATA_FIFO_RD = 312 -PH_SC2_PA4_DATA_FIFO_WE = 313 -PH_SC2_PA4_FIFO_EMPTY = 314 -PH_SC2_PA4_FIFO_FULL = 315 -PH_SC2_PA4_NULL_WE = 316 -PH_SC2_PA4_EVENT_WE = 317 -PH_SC2_PA4_FPOV_WE = 318 -PH_SC2_PA4_LPOV_WE = 319 -PH_SC2_PA4_EOP_WE = 320 -PH_SC2_PA4_DATA_FIFO_EOP_RD = 321 -PH_SC2_PA4_EOPG_WE = 322 -PH_SC2_PA4_DEALLOC_4_0_RD = 323 -PH_SC2_PA5_DATA_FIFO_RD = 324 -PH_SC2_PA5_DATA_FIFO_WE = 325 -PH_SC2_PA5_FIFO_EMPTY = 326 -PH_SC2_PA5_FIFO_FULL = 327 -PH_SC2_PA5_NULL_WE = 328 -PH_SC2_PA5_EVENT_WE = 329 -PH_SC2_PA5_FPOV_WE = 330 -PH_SC2_PA5_LPOV_WE = 331 -PH_SC2_PA5_EOP_WE = 332 -PH_SC2_PA5_DATA_FIFO_EOP_RD = 333 -PH_SC2_PA5_EOPG_WE = 334 -PH_SC2_PA5_DEALLOC_4_0_RD = 335 -PH_SC2_PA6_DATA_FIFO_RD = 336 -PH_SC2_PA6_DATA_FIFO_WE = 337 -PH_SC2_PA6_FIFO_EMPTY = 338 -PH_SC2_PA6_FIFO_FULL = 339 -PH_SC2_PA6_NULL_WE = 340 -PH_SC2_PA6_EVENT_WE = 341 -PH_SC2_PA6_FPOV_WE = 342 -PH_SC2_PA6_LPOV_WE = 343 -PH_SC2_PA6_EOP_WE = 344 -PH_SC2_PA6_DATA_FIFO_EOP_RD = 345 -PH_SC2_PA6_EOPG_WE = 346 -PH_SC2_PA6_DEALLOC_4_0_RD = 347 -PH_SC2_PA7_DATA_FIFO_RD = 348 -PH_SC2_PA7_DATA_FIFO_WE = 349 -PH_SC2_PA7_FIFO_EMPTY = 350 -PH_SC2_PA7_FIFO_FULL = 351 -PH_SC2_PA7_NULL_WE = 352 -PH_SC2_PA7_EVENT_WE = 353 -PH_SC2_PA7_FPOV_WE = 354 -PH_SC2_PA7_LPOV_WE = 355 -PH_SC2_PA7_EOP_WE = 356 -PH_SC2_PA7_DATA_FIFO_EOP_RD = 357 -PH_SC2_PA7_EOPG_WE = 358 -PH_SC2_PA7_DEALLOC_4_0_RD = 359 -PH_SC3_SRPS_WINDOW_VALID = 360 -PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 -PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 -PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 -PH_SC3_ARB_STALLED_FROM_BELOW = 364 -PH_SC3_ARB_STARVED_FROM_ABOVE = 365 -PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 -PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 -PH_SC3_ARB_BUSY = 368 -PH_SC3_ARB_PA_BUSY_SOP = 369 -PH_SC3_ARB_EOP_POP_SYNC_POP = 370 -PH_SC3_ARB_EVENT_SYNC_POP = 371 -PH_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 -PH_SC3_EOP_SYNC_WINDOW = 373 -PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 -PH_SC3_BUSY_CNT_NOT_ZERO = 375 -PH_SC3_SEND = 376 -PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 -PH_SC3_CREDIT_AT_MAX = 378 -PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 -PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 380 -PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 381 -PH_SC3_GFX_PIPE0_TO_1_TRANSITION = 382 -PH_SC3_GFX_PIPE1_TO_0_TRANSITION = 383 -PH_SC3_PA0_DATA_FIFO_RD = 384 -PH_SC3_PA0_DATA_FIFO_WE = 385 -PH_SC3_PA0_FIFO_EMPTY = 386 -PH_SC3_PA0_FIFO_FULL = 387 -PH_SC3_PA0_NULL_WE = 388 -PH_SC3_PA0_EVENT_WE = 389 -PH_SC3_PA0_FPOV_WE = 390 -PH_SC3_PA0_LPOV_WE = 391 -PH_SC3_PA0_EOP_WE = 392 -PH_SC3_PA0_DATA_FIFO_EOP_RD = 393 -PH_SC3_PA0_EOPG_WE = 394 -PH_SC3_PA0_DEALLOC_4_0_RD = 395 -PH_SC3_PA1_DATA_FIFO_RD = 396 -PH_SC3_PA1_DATA_FIFO_WE = 397 -PH_SC3_PA1_FIFO_EMPTY = 398 -PH_SC3_PA1_FIFO_FULL = 399 -PH_SC3_PA1_NULL_WE = 400 -PH_SC3_PA1_EVENT_WE = 401 -PH_SC3_PA1_FPOV_WE = 402 -PH_SC3_PA1_LPOV_WE = 403 -PH_SC3_PA1_EOP_WE = 404 -PH_SC3_PA1_DATA_FIFO_EOP_RD = 405 -PH_SC3_PA1_EOPG_WE = 406 -PH_SC3_PA1_DEALLOC_4_0_RD = 407 -PH_SC3_PA2_DATA_FIFO_RD = 408 -PH_SC3_PA2_DATA_FIFO_WE = 409 -PH_SC3_PA2_FIFO_EMPTY = 410 -PH_SC3_PA2_FIFO_FULL = 411 -PH_SC3_PA2_NULL_WE = 412 -PH_SC3_PA2_EVENT_WE = 413 -PH_SC3_PA2_FPOV_WE = 414 -PH_SC3_PA2_LPOV_WE = 415 -PH_SC3_PA2_EOP_WE = 416 -PH_SC3_PA2_DATA_FIFO_EOP_RD = 417 -PH_SC3_PA2_EOPG_WE = 418 -PH_SC3_PA2_DEALLOC_4_0_RD = 419 -PH_SC3_PA3_DATA_FIFO_RD = 420 -PH_SC3_PA3_DATA_FIFO_WE = 421 -PH_SC3_PA3_FIFO_EMPTY = 422 -PH_SC3_PA3_FIFO_FULL = 423 -PH_SC3_PA3_NULL_WE = 424 -PH_SC3_PA3_EVENT_WE = 425 -PH_SC3_PA3_FPOV_WE = 426 -PH_SC3_PA3_LPOV_WE = 427 -PH_SC3_PA3_EOP_WE = 428 -PH_SC3_PA3_DATA_FIFO_EOP_RD = 429 -PH_SC3_PA3_EOPG_WE = 430 -PH_SC3_PA3_DEALLOC_4_0_RD = 431 -PH_SC3_PA4_DATA_FIFO_RD = 432 -PH_SC3_PA4_DATA_FIFO_WE = 433 -PH_SC3_PA4_FIFO_EMPTY = 434 -PH_SC3_PA4_FIFO_FULL = 435 -PH_SC3_PA4_NULL_WE = 436 -PH_SC3_PA4_EVENT_WE = 437 -PH_SC3_PA4_FPOV_WE = 438 -PH_SC3_PA4_LPOV_WE = 439 -PH_SC3_PA4_EOP_WE = 440 -PH_SC3_PA4_DATA_FIFO_EOP_RD = 441 -PH_SC3_PA4_EOPG_WE = 442 -PH_SC3_PA4_DEALLOC_4_0_RD = 443 -PH_SC3_PA5_DATA_FIFO_RD = 444 -PH_SC3_PA5_DATA_FIFO_WE = 445 -PH_SC3_PA5_FIFO_EMPTY = 446 -PH_SC3_PA5_FIFO_FULL = 447 -PH_SC3_PA5_NULL_WE = 448 -PH_SC3_PA5_EVENT_WE = 449 -PH_SC3_PA5_FPOV_WE = 450 -PH_SC3_PA5_LPOV_WE = 451 -PH_SC3_PA5_EOP_WE = 452 -PH_SC3_PA5_DATA_FIFO_EOP_RD = 453 -PH_SC3_PA5_EOPG_WE = 454 -PH_SC3_PA5_DEALLOC_4_0_RD = 455 -PH_SC3_PA6_DATA_FIFO_RD = 456 -PH_SC3_PA6_DATA_FIFO_WE = 457 -PH_SC3_PA6_FIFO_EMPTY = 458 -PH_SC3_PA6_FIFO_FULL = 459 -PH_SC3_PA6_NULL_WE = 460 -PH_SC3_PA6_EVENT_WE = 461 -PH_SC3_PA6_FPOV_WE = 462 -PH_SC3_PA6_LPOV_WE = 463 -PH_SC3_PA6_EOP_WE = 464 -PH_SC3_PA6_DATA_FIFO_EOP_RD = 465 -PH_SC3_PA6_EOPG_WE = 466 -PH_SC3_PA6_DEALLOC_4_0_RD = 467 -PH_SC3_PA7_DATA_FIFO_RD = 468 -PH_SC3_PA7_DATA_FIFO_WE = 469 -PH_SC3_PA7_FIFO_EMPTY = 470 -PH_SC3_PA7_FIFO_FULL = 471 -PH_SC3_PA7_NULL_WE = 472 -PH_SC3_PA7_EVENT_WE = 473 -PH_SC3_PA7_FPOV_WE = 474 -PH_SC3_PA7_LPOV_WE = 475 -PH_SC3_PA7_EOP_WE = 476 -PH_SC3_PA7_DATA_FIFO_EOP_RD = 477 -PH_SC3_PA7_EOPG_WE = 478 -PH_SC3_PA7_DEALLOC_4_0_RD = 479 -PH_SC4_SRPS_WINDOW_VALID = 480 -PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 -PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 -PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 -PH_SC4_ARB_STALLED_FROM_BELOW = 484 -PH_SC4_ARB_STARVED_FROM_ABOVE = 485 -PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 -PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 -PH_SC4_ARB_BUSY = 488 -PH_SC4_ARB_PA_BUSY_SOP = 489 -PH_SC4_ARB_EOP_POP_SYNC_POP = 490 -PH_SC4_ARB_EVENT_SYNC_POP = 491 -PH_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 -PH_SC4_EOP_SYNC_WINDOW = 493 -PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 -PH_SC4_BUSY_CNT_NOT_ZERO = 495 -PH_SC4_SEND = 496 -PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 -PH_SC4_CREDIT_AT_MAX = 498 -PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 -PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 500 -PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 501 -PH_SC4_GFX_PIPE0_TO_1_TRANSITION = 502 -PH_SC4_GFX_PIPE1_TO_0_TRANSITION = 503 -PH_SC4_PA0_DATA_FIFO_RD = 504 -PH_SC4_PA0_DATA_FIFO_WE = 505 -PH_SC4_PA0_FIFO_EMPTY = 506 -PH_SC4_PA0_FIFO_FULL = 507 -PH_SC4_PA0_NULL_WE = 508 -PH_SC4_PA0_EVENT_WE = 509 -PH_SC4_PA0_FPOV_WE = 510 -PH_SC4_PA0_LPOV_WE = 511 -PH_SC4_PA0_EOP_WE = 512 -PH_SC4_PA0_DATA_FIFO_EOP_RD = 513 -PH_SC4_PA0_EOPG_WE = 514 -PH_SC4_PA0_DEALLOC_4_0_RD = 515 -PH_SC4_PA1_DATA_FIFO_RD = 516 -PH_SC4_PA1_DATA_FIFO_WE = 517 -PH_SC4_PA1_FIFO_EMPTY = 518 -PH_SC4_PA1_FIFO_FULL = 519 -PH_SC4_PA1_NULL_WE = 520 -PH_SC4_PA1_EVENT_WE = 521 -PH_SC4_PA1_FPOV_WE = 522 -PH_SC4_PA1_LPOV_WE = 523 -PH_SC4_PA1_EOP_WE = 524 -PH_SC4_PA1_DATA_FIFO_EOP_RD = 525 -PH_SC4_PA1_EOPG_WE = 526 -PH_SC4_PA1_DEALLOC_4_0_RD = 527 -PH_SC4_PA2_DATA_FIFO_RD = 528 -PH_SC4_PA2_DATA_FIFO_WE = 529 -PH_SC4_PA2_FIFO_EMPTY = 530 -PH_SC4_PA2_FIFO_FULL = 531 -PH_SC4_PA2_NULL_WE = 532 -PH_SC4_PA2_EVENT_WE = 533 -PH_SC4_PA2_FPOV_WE = 534 -PH_SC4_PA2_LPOV_WE = 535 -PH_SC4_PA2_EOP_WE = 536 -PH_SC4_PA2_DATA_FIFO_EOP_RD = 537 -PH_SC4_PA2_EOPG_WE = 538 -PH_SC4_PA2_DEALLOC_4_0_RD = 539 -PH_SC4_PA3_DATA_FIFO_RD = 540 -PH_SC4_PA3_DATA_FIFO_WE = 541 -PH_SC4_PA3_FIFO_EMPTY = 542 -PH_SC4_PA3_FIFO_FULL = 543 -PH_SC4_PA3_NULL_WE = 544 -PH_SC4_PA3_EVENT_WE = 545 -PH_SC4_PA3_FPOV_WE = 546 -PH_SC4_PA3_LPOV_WE = 547 -PH_SC4_PA3_EOP_WE = 548 -PH_SC4_PA3_DATA_FIFO_EOP_RD = 549 -PH_SC4_PA3_EOPG_WE = 550 -PH_SC4_PA3_DEALLOC_4_0_RD = 551 -PH_SC4_PA4_DATA_FIFO_RD = 552 -PH_SC4_PA4_DATA_FIFO_WE = 553 -PH_SC4_PA4_FIFO_EMPTY = 554 -PH_SC4_PA4_FIFO_FULL = 555 -PH_SC4_PA4_NULL_WE = 556 -PH_SC4_PA4_EVENT_WE = 557 -PH_SC4_PA4_FPOV_WE = 558 -PH_SC4_PA4_LPOV_WE = 559 -PH_SC4_PA4_EOP_WE = 560 -PH_SC4_PA4_DATA_FIFO_EOP_RD = 561 -PH_SC4_PA4_EOPG_WE = 562 -PH_SC4_PA4_DEALLOC_4_0_RD = 563 -PH_SC4_PA5_DATA_FIFO_RD = 564 -PH_SC4_PA5_DATA_FIFO_WE = 565 -PH_SC4_PA5_FIFO_EMPTY = 566 -PH_SC4_PA5_FIFO_FULL = 567 -PH_SC4_PA5_NULL_WE = 568 -PH_SC4_PA5_EVENT_WE = 569 -PH_SC4_PA5_FPOV_WE = 570 -PH_SC4_PA5_LPOV_WE = 571 -PH_SC4_PA5_EOP_WE = 572 -PH_SC4_PA5_DATA_FIFO_EOP_RD = 573 -PH_SC4_PA5_EOPG_WE = 574 -PH_SC4_PA5_DEALLOC_4_0_RD = 575 -PH_SC4_PA6_DATA_FIFO_RD = 576 -PH_SC4_PA6_DATA_FIFO_WE = 577 -PH_SC4_PA6_FIFO_EMPTY = 578 -PH_SC4_PA6_FIFO_FULL = 579 -PH_SC4_PA6_NULL_WE = 580 -PH_SC4_PA6_EVENT_WE = 581 -PH_SC4_PA6_FPOV_WE = 582 -PH_SC4_PA6_LPOV_WE = 583 -PH_SC4_PA6_EOP_WE = 584 -PH_SC4_PA6_DATA_FIFO_EOP_RD = 585 -PH_SC4_PA6_EOPG_WE = 586 -PH_SC4_PA6_DEALLOC_4_0_RD = 587 -PH_SC4_PA7_DATA_FIFO_RD = 588 -PH_SC4_PA7_DATA_FIFO_WE = 589 -PH_SC4_PA7_FIFO_EMPTY = 590 -PH_SC4_PA7_FIFO_FULL = 591 -PH_SC4_PA7_NULL_WE = 592 -PH_SC4_PA7_EVENT_WE = 593 -PH_SC4_PA7_FPOV_WE = 594 -PH_SC4_PA7_LPOV_WE = 595 -PH_SC4_PA7_EOP_WE = 596 -PH_SC4_PA7_DATA_FIFO_EOP_RD = 597 -PH_SC4_PA7_EOPG_WE = 598 -PH_SC4_PA7_DEALLOC_4_0_RD = 599 -PH_SC5_SRPS_WINDOW_VALID = 600 -PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 -PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 -PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 -PH_SC5_ARB_STALLED_FROM_BELOW = 604 -PH_SC5_ARB_STARVED_FROM_ABOVE = 605 -PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 -PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 -PH_SC5_ARB_BUSY = 608 -PH_SC5_ARB_PA_BUSY_SOP = 609 -PH_SC5_ARB_EOP_POP_SYNC_POP = 610 -PH_SC5_ARB_EVENT_SYNC_POP = 611 -PH_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 -PH_SC5_EOP_SYNC_WINDOW = 613 -PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 -PH_SC5_BUSY_CNT_NOT_ZERO = 615 -PH_SC5_SEND = 616 -PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 -PH_SC5_CREDIT_AT_MAX = 618 -PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 -PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 620 -PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 621 -PH_SC5_GFX_PIPE0_TO_1_TRANSITION = 622 -PH_SC5_GFX_PIPE1_TO_0_TRANSITION = 623 -PH_SC5_PA0_DATA_FIFO_RD = 624 -PH_SC5_PA0_DATA_FIFO_WE = 625 -PH_SC5_PA0_FIFO_EMPTY = 626 -PH_SC5_PA0_FIFO_FULL = 627 -PH_SC5_PA0_NULL_WE = 628 -PH_SC5_PA0_EVENT_WE = 629 -PH_SC5_PA0_FPOV_WE = 630 -PH_SC5_PA0_LPOV_WE = 631 -PH_SC5_PA0_EOP_WE = 632 -PH_SC5_PA0_DATA_FIFO_EOP_RD = 633 -PH_SC5_PA0_EOPG_WE = 634 -PH_SC5_PA0_DEALLOC_4_0_RD = 635 -PH_SC5_PA1_DATA_FIFO_RD = 636 -PH_SC5_PA1_DATA_FIFO_WE = 637 -PH_SC5_PA1_FIFO_EMPTY = 638 -PH_SC5_PA1_FIFO_FULL = 639 -PH_SC5_PA1_NULL_WE = 640 -PH_SC5_PA1_EVENT_WE = 641 -PH_SC5_PA1_FPOV_WE = 642 -PH_SC5_PA1_LPOV_WE = 643 -PH_SC5_PA1_EOP_WE = 644 -PH_SC5_PA1_DATA_FIFO_EOP_RD = 645 -PH_SC5_PA1_EOPG_WE = 646 -PH_SC5_PA1_DEALLOC_4_0_RD = 647 -PH_SC5_PA2_DATA_FIFO_RD = 648 -PH_SC5_PA2_DATA_FIFO_WE = 649 -PH_SC5_PA2_FIFO_EMPTY = 650 -PH_SC5_PA2_FIFO_FULL = 651 -PH_SC5_PA2_NULL_WE = 652 -PH_SC5_PA2_EVENT_WE = 653 -PH_SC5_PA2_FPOV_WE = 654 -PH_SC5_PA2_LPOV_WE = 655 -PH_SC5_PA2_EOP_WE = 656 -PH_SC5_PA2_DATA_FIFO_EOP_RD = 657 -PH_SC5_PA2_EOPG_WE = 658 -PH_SC5_PA2_DEALLOC_4_0_RD = 659 -PH_SC5_PA3_DATA_FIFO_RD = 660 -PH_SC5_PA3_DATA_FIFO_WE = 661 -PH_SC5_PA3_FIFO_EMPTY = 662 -PH_SC5_PA3_FIFO_FULL = 663 -PH_SC5_PA3_NULL_WE = 664 -PH_SC5_PA3_EVENT_WE = 665 -PH_SC5_PA3_FPOV_WE = 666 -PH_SC5_PA3_LPOV_WE = 667 -PH_SC5_PA3_EOP_WE = 668 -PH_SC5_PA3_DATA_FIFO_EOP_RD = 669 -PH_SC5_PA3_EOPG_WE = 670 -PH_SC5_PA3_DEALLOC_4_0_RD = 671 -PH_SC5_PA4_DATA_FIFO_RD = 672 -PH_SC5_PA4_DATA_FIFO_WE = 673 -PH_SC5_PA4_FIFO_EMPTY = 674 -PH_SC5_PA4_FIFO_FULL = 675 -PH_SC5_PA4_NULL_WE = 676 -PH_SC5_PA4_EVENT_WE = 677 -PH_SC5_PA4_FPOV_WE = 678 -PH_SC5_PA4_LPOV_WE = 679 -PH_SC5_PA4_EOP_WE = 680 -PH_SC5_PA4_DATA_FIFO_EOP_RD = 681 -PH_SC5_PA4_EOPG_WE = 682 -PH_SC5_PA4_DEALLOC_4_0_RD = 683 -PH_SC5_PA5_DATA_FIFO_RD = 684 -PH_SC5_PA5_DATA_FIFO_WE = 685 -PH_SC5_PA5_FIFO_EMPTY = 686 -PH_SC5_PA5_FIFO_FULL = 687 -PH_SC5_PA5_NULL_WE = 688 -PH_SC5_PA5_EVENT_WE = 689 -PH_SC5_PA5_FPOV_WE = 690 -PH_SC5_PA5_LPOV_WE = 691 -PH_SC5_PA5_EOP_WE = 692 -PH_SC5_PA5_DATA_FIFO_EOP_RD = 693 -PH_SC5_PA5_EOPG_WE = 694 -PH_SC5_PA5_DEALLOC_4_0_RD = 695 -PH_SC5_PA6_DATA_FIFO_RD = 696 -PH_SC5_PA6_DATA_FIFO_WE = 697 -PH_SC5_PA6_FIFO_EMPTY = 698 -PH_SC5_PA6_FIFO_FULL = 699 -PH_SC5_PA6_NULL_WE = 700 -PH_SC5_PA6_EVENT_WE = 701 -PH_SC5_PA6_FPOV_WE = 702 -PH_SC5_PA6_LPOV_WE = 703 -PH_SC5_PA6_EOP_WE = 704 -PH_SC5_PA6_DATA_FIFO_EOP_RD = 705 -PH_SC5_PA6_EOPG_WE = 706 -PH_SC5_PA6_DEALLOC_4_0_RD = 707 -PH_SC5_PA7_DATA_FIFO_RD = 708 -PH_SC5_PA7_DATA_FIFO_WE = 709 -PH_SC5_PA7_FIFO_EMPTY = 710 -PH_SC5_PA7_FIFO_FULL = 711 -PH_SC5_PA7_NULL_WE = 712 -PH_SC5_PA7_EVENT_WE = 713 -PH_SC5_PA7_FPOV_WE = 714 -PH_SC5_PA7_LPOV_WE = 715 -PH_SC5_PA7_EOP_WE = 716 -PH_SC5_PA7_DATA_FIFO_EOP_RD = 717 -PH_SC5_PA7_EOPG_WE = 718 -PH_SC5_PA7_DEALLOC_4_0_RD = 719 -PH_SC6_SRPS_WINDOW_VALID = 720 -PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 -PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 -PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 -PH_SC6_ARB_STALLED_FROM_BELOW = 724 -PH_SC6_ARB_STARVED_FROM_ABOVE = 725 -PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 -PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 -PH_SC6_ARB_BUSY = 728 -PH_SC6_ARB_PA_BUSY_SOP = 729 -PH_SC6_ARB_EOP_POP_SYNC_POP = 730 -PH_SC6_ARB_EVENT_SYNC_POP = 731 -PH_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 -PH_SC6_EOP_SYNC_WINDOW = 733 -PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 -PH_SC6_BUSY_CNT_NOT_ZERO = 735 -PH_SC6_SEND = 736 -PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 -PH_SC6_CREDIT_AT_MAX = 738 -PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 -PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 740 -PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 741 -PH_SC6_GFX_PIPE0_TO_1_TRANSITION = 742 -PH_SC6_GFX_PIPE1_TO_0_TRANSITION = 743 -PH_SC6_PA0_DATA_FIFO_RD = 744 -PH_SC6_PA0_DATA_FIFO_WE = 745 -PH_SC6_PA0_FIFO_EMPTY = 746 -PH_SC6_PA0_FIFO_FULL = 747 -PH_SC6_PA0_NULL_WE = 748 -PH_SC6_PA0_EVENT_WE = 749 -PH_SC6_PA0_FPOV_WE = 750 -PH_SC6_PA0_LPOV_WE = 751 -PH_SC6_PA0_EOP_WE = 752 -PH_SC6_PA0_DATA_FIFO_EOP_RD = 753 -PH_SC6_PA0_EOPG_WE = 754 -PH_SC6_PA0_DEALLOC_4_0_RD = 755 -PH_SC6_PA1_DATA_FIFO_RD = 756 -PH_SC6_PA1_DATA_FIFO_WE = 757 -PH_SC6_PA1_FIFO_EMPTY = 758 -PH_SC6_PA1_FIFO_FULL = 759 -PH_SC6_PA1_NULL_WE = 760 -PH_SC6_PA1_EVENT_WE = 761 -PH_SC6_PA1_FPOV_WE = 762 -PH_SC6_PA1_LPOV_WE = 763 -PH_SC6_PA1_EOP_WE = 764 -PH_SC6_PA1_DATA_FIFO_EOP_RD = 765 -PH_SC6_PA1_EOPG_WE = 766 -PH_SC6_PA1_DEALLOC_4_0_RD = 767 -PH_SC6_PA2_DATA_FIFO_RD = 768 -PH_SC6_PA2_DATA_FIFO_WE = 769 -PH_SC6_PA2_FIFO_EMPTY = 770 -PH_SC6_PA2_FIFO_FULL = 771 -PH_SC6_PA2_NULL_WE = 772 -PH_SC6_PA2_EVENT_WE = 773 -PH_SC6_PA2_FPOV_WE = 774 -PH_SC6_PA2_LPOV_WE = 775 -PH_SC6_PA2_EOP_WE = 776 -PH_SC6_PA2_DATA_FIFO_EOP_RD = 777 -PH_SC6_PA2_EOPG_WE = 778 -PH_SC6_PA2_DEALLOC_4_0_RD = 779 -PH_SC6_PA3_DATA_FIFO_RD = 780 -PH_SC6_PA3_DATA_FIFO_WE = 781 -PH_SC6_PA3_FIFO_EMPTY = 782 -PH_SC6_PA3_FIFO_FULL = 783 -PH_SC6_PA3_NULL_WE = 784 -PH_SC6_PA3_EVENT_WE = 785 -PH_SC6_PA3_FPOV_WE = 786 -PH_SC6_PA3_LPOV_WE = 787 -PH_SC6_PA3_EOP_WE = 788 -PH_SC6_PA3_DATA_FIFO_EOP_RD = 789 -PH_SC6_PA3_EOPG_WE = 790 -PH_SC6_PA3_DEALLOC_4_0_RD = 791 -PH_SC6_PA4_DATA_FIFO_RD = 792 -PH_SC6_PA4_DATA_FIFO_WE = 793 -PH_SC6_PA4_FIFO_EMPTY = 794 -PH_SC6_PA4_FIFO_FULL = 795 -PH_SC6_PA4_NULL_WE = 796 -PH_SC6_PA4_EVENT_WE = 797 -PH_SC6_PA4_FPOV_WE = 798 -PH_SC6_PA4_LPOV_WE = 799 -PH_SC6_PA4_EOP_WE = 800 -PH_SC6_PA4_DATA_FIFO_EOP_RD = 801 -PH_SC6_PA4_EOPG_WE = 802 -PH_SC6_PA4_DEALLOC_4_0_RD = 803 -PH_SC6_PA5_DATA_FIFO_RD = 804 -PH_SC6_PA5_DATA_FIFO_WE = 805 -PH_SC6_PA5_FIFO_EMPTY = 806 -PH_SC6_PA5_FIFO_FULL = 807 -PH_SC6_PA5_NULL_WE = 808 -PH_SC6_PA5_EVENT_WE = 809 -PH_SC6_PA5_FPOV_WE = 810 -PH_SC6_PA5_LPOV_WE = 811 -PH_SC6_PA5_EOP_WE = 812 -PH_SC6_PA5_DATA_FIFO_EOP_RD = 813 -PH_SC6_PA5_EOPG_WE = 814 -PH_SC6_PA5_DEALLOC_4_0_RD = 815 -PH_SC6_PA6_DATA_FIFO_RD = 816 -PH_SC6_PA6_DATA_FIFO_WE = 817 -PH_SC6_PA6_FIFO_EMPTY = 818 -PH_SC6_PA6_FIFO_FULL = 819 -PH_SC6_PA6_NULL_WE = 820 -PH_SC6_PA6_EVENT_WE = 821 -PH_SC6_PA6_FPOV_WE = 822 -PH_SC6_PA6_LPOV_WE = 823 -PH_SC6_PA6_EOP_WE = 824 -PH_SC6_PA6_DATA_FIFO_EOP_RD = 825 -PH_SC6_PA6_EOPG_WE = 826 -PH_SC6_PA6_DEALLOC_4_0_RD = 827 -PH_SC6_PA7_DATA_FIFO_RD = 828 -PH_SC6_PA7_DATA_FIFO_WE = 829 -PH_SC6_PA7_FIFO_EMPTY = 830 -PH_SC6_PA7_FIFO_FULL = 831 -PH_SC6_PA7_NULL_WE = 832 -PH_SC6_PA7_EVENT_WE = 833 -PH_SC6_PA7_FPOV_WE = 834 -PH_SC6_PA7_LPOV_WE = 835 -PH_SC6_PA7_EOP_WE = 836 -PH_SC6_PA7_DATA_FIFO_EOP_RD = 837 -PH_SC6_PA7_EOPG_WE = 838 -PH_SC6_PA7_DEALLOC_4_0_RD = 839 -PH_SC7_SRPS_WINDOW_VALID = 840 -PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 -PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 -PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 -PH_SC7_ARB_STALLED_FROM_BELOW = 844 -PH_SC7_ARB_STARVED_FROM_ABOVE = 845 -PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 -PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 -PH_SC7_ARB_BUSY = 848 -PH_SC7_ARB_PA_BUSY_SOP = 849 -PH_SC7_ARB_EOP_POP_SYNC_POP = 850 -PH_SC7_ARB_EVENT_SYNC_POP = 851 -PH_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 -PH_SC7_EOP_SYNC_WINDOW = 853 -PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 -PH_SC7_BUSY_CNT_NOT_ZERO = 855 -PH_SC7_SEND = 856 -PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 -PH_SC7_CREDIT_AT_MAX = 858 -PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 -PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 860 -PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 861 -PH_SC7_GFX_PIPE0_TO_1_TRANSITION = 862 -PH_SC7_GFX_PIPE1_TO_0_TRANSITION = 863 -PH_SC7_PA0_DATA_FIFO_RD = 864 -PH_SC7_PA0_DATA_FIFO_WE = 865 -PH_SC7_PA0_FIFO_EMPTY = 866 -PH_SC7_PA0_FIFO_FULL = 867 -PH_SC7_PA0_NULL_WE = 868 -PH_SC7_PA0_EVENT_WE = 869 -PH_SC7_PA0_FPOV_WE = 870 -PH_SC7_PA0_LPOV_WE = 871 -PH_SC7_PA0_EOP_WE = 872 -PH_SC7_PA0_DATA_FIFO_EOP_RD = 873 -PH_SC7_PA0_EOPG_WE = 874 -PH_SC7_PA0_DEALLOC_4_0_RD = 875 -PH_SC7_PA1_DATA_FIFO_RD = 876 -PH_SC7_PA1_DATA_FIFO_WE = 877 -PH_SC7_PA1_FIFO_EMPTY = 878 -PH_SC7_PA1_FIFO_FULL = 879 -PH_SC7_PA1_NULL_WE = 880 -PH_SC7_PA1_EVENT_WE = 881 -PH_SC7_PA1_FPOV_WE = 882 -PH_SC7_PA1_LPOV_WE = 883 -PH_SC7_PA1_EOP_WE = 884 -PH_SC7_PA1_DATA_FIFO_EOP_RD = 885 -PH_SC7_PA1_EOPG_WE = 886 -PH_SC7_PA1_DEALLOC_4_0_RD = 887 -PH_SC7_PA2_DATA_FIFO_RD = 888 -PH_SC7_PA2_DATA_FIFO_WE = 889 -PH_SC7_PA2_FIFO_EMPTY = 890 -PH_SC7_PA2_FIFO_FULL = 891 -PH_SC7_PA2_NULL_WE = 892 -PH_SC7_PA2_EVENT_WE = 893 -PH_SC7_PA2_FPOV_WE = 894 -PH_SC7_PA2_LPOV_WE = 895 -PH_SC7_PA2_EOP_WE = 896 -PH_SC7_PA2_DATA_FIFO_EOP_RD = 897 -PH_SC7_PA2_EOPG_WE = 898 -PH_SC7_PA2_DEALLOC_4_0_RD = 899 -PH_SC7_PA3_DATA_FIFO_RD = 900 -PH_SC7_PA3_DATA_FIFO_WE = 901 -PH_SC7_PA3_FIFO_EMPTY = 902 -PH_SC7_PA3_FIFO_FULL = 903 -PH_SC7_PA3_NULL_WE = 904 -PH_SC7_PA3_EVENT_WE = 905 -PH_SC7_PA3_FPOV_WE = 906 -PH_SC7_PA3_LPOV_WE = 907 -PH_SC7_PA3_EOP_WE = 908 -PH_SC7_PA3_DATA_FIFO_EOP_RD = 909 -PH_SC7_PA3_EOPG_WE = 910 -PH_SC7_PA3_DEALLOC_4_0_RD = 911 -PH_SC7_PA4_DATA_FIFO_RD = 912 -PH_SC7_PA4_DATA_FIFO_WE = 913 -PH_SC7_PA4_FIFO_EMPTY = 914 -PH_SC7_PA4_FIFO_FULL = 915 -PH_SC7_PA4_NULL_WE = 916 -PH_SC7_PA4_EVENT_WE = 917 -PH_SC7_PA4_FPOV_WE = 918 -PH_SC7_PA4_LPOV_WE = 919 -PH_SC7_PA4_EOP_WE = 920 -PH_SC7_PA4_DATA_FIFO_EOP_RD = 921 -PH_SC7_PA4_EOPG_WE = 922 -PH_SC7_PA4_DEALLOC_4_0_RD = 923 -PH_SC7_PA5_DATA_FIFO_RD = 924 -PH_SC7_PA5_DATA_FIFO_WE = 925 -PH_SC7_PA5_FIFO_EMPTY = 926 -PH_SC7_PA5_FIFO_FULL = 927 -PH_SC7_PA5_NULL_WE = 928 -PH_SC7_PA5_EVENT_WE = 929 -PH_SC7_PA5_FPOV_WE = 930 -PH_SC7_PA5_LPOV_WE = 931 -PH_SC7_PA5_EOP_WE = 932 -PH_SC7_PA5_DATA_FIFO_EOP_RD = 933 -PH_SC7_PA5_EOPG_WE = 934 -PH_SC7_PA5_DEALLOC_4_0_RD = 935 -PH_SC7_PA6_DATA_FIFO_RD = 936 -PH_SC7_PA6_DATA_FIFO_WE = 937 -PH_SC7_PA6_FIFO_EMPTY = 938 -PH_SC7_PA6_FIFO_FULL = 939 -PH_SC7_PA6_NULL_WE = 940 -PH_SC7_PA6_EVENT_WE = 941 -PH_SC7_PA6_FPOV_WE = 942 -PH_SC7_PA6_LPOV_WE = 943 -PH_SC7_PA6_EOP_WE = 944 -PH_SC7_PA6_DATA_FIFO_EOP_RD = 945 -PH_SC7_PA6_EOPG_WE = 946 -PH_SC7_PA6_DEALLOC_4_0_RD = 947 -PH_SC7_PA7_DATA_FIFO_RD = 948 -PH_SC7_PA7_DATA_FIFO_WE = 949 -PH_SC7_PA7_FIFO_EMPTY = 950 -PH_SC7_PA7_FIFO_FULL = 951 -PH_SC7_PA7_NULL_WE = 952 -PH_SC7_PA7_EVENT_WE = 953 -PH_SC7_PA7_FPOV_WE = 954 -PH_SC7_PA7_LPOV_WE = 955 -PH_SC7_PA7_EOP_WE = 956 -PH_SC7_PA7_DATA_FIFO_EOP_RD = 957 -PH_SC7_PA7_EOPG_WE = 958 -PH_SC7_PA7_DEALLOC_4_0_RD = 959 -PH_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SU_PERFCNT_SEL' -SU_PERFCNT_SEL__enumvalues = { - 0: 'PERF_PAPC_PASX_REQ', - 1: 'PERF_PAPC_PASX_DISABLE_PIPE', - 2: 'PERF_PAPC_PASX_FIRST_VECTOR', - 3: 'PERF_PAPC_PASX_SECOND_VECTOR', - 4: 'PERF_PAPC_PASX_FIRST_DEAD', - 5: 'PERF_PAPC_PASX_SECOND_DEAD', - 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 8: 'PERF_PAPC_PA_INPUT_PRIM', - 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', - 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 14: 'PERF_PAPC_CLPR_CULL_PRIM', - 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', - 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', - 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', - 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', - 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', - 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 39: 'PERF_PAPC_CLSM_NULL_PRIM', - 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', - 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', - 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', - 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', - 49: 'PERF_PAPC_SU_INPUT_PRIM', - 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', - 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 61: 'PERF_PAPC_SU_OUTPUT_PRIM', - 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', - 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', - 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 77: 'PERF_PAPC_PASX_REQ_IDLE', - 78: 'PERF_PAPC_PASX_REQ_BUSY', - 79: 'PERF_PAPC_PASX_REQ_STALLED', - 80: 'PERF_PAPC_PASX_REC_IDLE', - 81: 'PERF_PAPC_PASX_REC_BUSY', - 82: 'PERF_PAPC_PASX_REC_STARVED_SX', - 83: 'PERF_PAPC_PASX_REC_STALLED', - 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 86: 'PERF_PAPC_CCGSM_IDLE', - 87: 'PERF_PAPC_CCGSM_BUSY', - 88: 'PERF_PAPC_CCGSM_STALLED', - 89: 'PERF_PAPC_CLPRIM_IDLE', - 90: 'PERF_PAPC_CLPRIM_BUSY', - 91: 'PERF_PAPC_CLPRIM_STALLED', - 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 93: 'PERF_PAPC_CLIPSM_IDLE', - 94: 'PERF_PAPC_CLIPSM_BUSY', - 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', - 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 100: 'PERF_PAPC_CLIPGA_IDLE', - 101: 'PERF_PAPC_CLIPGA_BUSY', - 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 103: 'PERF_PAPC_CLIPGA_STALLED', - 104: 'PERF_PAPC_CLIP_IDLE', - 105: 'PERF_PAPC_CLIP_BUSY', - 106: 'PERF_PAPC_SU_IDLE', - 107: 'PERF_PAPC_SU_BUSY', - 108: 'PERF_PAPC_SU_STARVED_CLIP', - 109: 'PERF_PAPC_SU_STALLED_SC', - 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', - 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', - 112: 'PERF_PAPC_PA_REG_SCLK_VLD', - 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 114: 'PERF_PAPC_PASX_SE0_REQ', - 115: 'PERF_PAPC_PASX_SE1_REQ', - 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', - 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', - 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 131: 'PERF_PAPC_SU_SE0_STALLED_SC', - 132: 'PERF_PAPC_SU_SE1_STALLED_SC', - 133: 'PERF_PAPC_SU_SE01_STALLED_SC', - 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 135: 'PERF_PAPC_SU_CULLED_PRIM', - 136: 'PERF_PAPC_SU_OUTPUT_EOPG', - 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 151: 'PERF_PAPC_SU_SE2_STALLED_SC', - 152: 'PERF_PAPC_SU_SE3_STALLED_SC', - 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', - 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', - 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', - 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', - 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', - 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', - 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', - 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 177: 'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1', - 178: 'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT', - 179: 'PERF_UTC_SIDEBAND_DRIVER_BUSY', - 180: 'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1', - 181: 'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT', - 182: 'PERF_UTC_INDEX_DRIVER_BUSY', - 183: 'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1', - 184: 'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT', - 185: 'PERF_UTC_POSITION_DRIVER_BUSY', - 186: 'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1', - 187: 'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER', - 188: 'PERF_UTC_SIDEBAND_RECEIVER_BUSY', - 189: 'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1', - 190: 'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER', - 191: 'PERF_UTC_INDEX_RECEIVER_BUSY', - 192: 'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1', - 193: 'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER', - 194: 'PERF_UTC_POSITION_RECEIVER_BUSY', - 195: 'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE', - 196: 'PERF_TCIF_STALLING_CLIENT_NO_CREDITS', - 197: 'PERF_TCIF_BUSY', - 198: 'PERF_TCIF_SIDEBAND_RDREQ', - 199: 'PERF_TCIF_INDEX_RDREQ', - 200: 'PERF_TCIF_POSITION_RDREQ', - 201: 'PERF_SIDEBAND_WAITING_ON_UTCL1', - 202: 'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY', - 203: 'PERF_WRITING_TO_SIDEBAND_MEMORY', - 204: 'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD', - 205: 'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD', - 206: 'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD', - 207: 'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA', - 208: 'PERF_SIDEBAND_POP_BIT_FIFO_FULL', - 209: 'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL', - 210: 'PERF_SIDEBAND_INVALID_REFETCH', - 211: 'PERF_SIDEBAND_QUALIFIED_BUSY', - 212: 'PERF_SIDEBAND_QUALIFIED_STARVED', - 213: 'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_', - 214: 'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_', - 215: 'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_', - 216: 'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_', - 217: 'PERF_INDEX_REQUEST_WAITING_ON_TOKENS', - 218: 'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO', - 219: 'PERF_INDEX_REQUEST_QUALIFIED_BUSY', - 220: 'PERF_INDEX_REQUEST_QUALIFIED_STARVED', - 221: 'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE', - 222: 'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO', - 223: 'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE', - 224: 'PERF_INDEX_RECEIVE_QUALIFIED_BUSY', - 225: 'PERF_INDEX_RECEIVE_QUALIFIED_STARVED', - 226: 'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE', - 227: 'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE', - 228: 'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE', - 229: 'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE', - 230: 'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE', - 231: 'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE', - 232: 'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE', - 233: 'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE', - 234: 'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE', - 235: 'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE', - 236: 'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE', - 237: 'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE', - 238: 'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE', - 239: 'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE', - 240: 'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE', - 241: 'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE', - 242: 'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE', - 243: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 244: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 245: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO', - 246: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO', - 247: 'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO', - 248: 'PERF_POS_REQ_STALLED_BY_NO_TOKENS', - 249: 'PERF_POS_REQ_STARVED_BY_NO_PRIM', - 250: 'PERF_POS_REQ_STALLED_BY_UTCL1', - 251: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 252: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 253: 'PERF_POS_REQ_QUALIFIED_BUSY', - 254: 'PERF_POS_REQ_QUALIFIED_STARVED', - 255: 'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM', - 256: 'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM', - 257: 'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM', - 258: 'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM', - 259: 'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO', - 260: 'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO', - 261: 'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE', - 262: 'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE', - 263: 'PERF_POS_RET_QUALIFIED_BUSY', - 264: 'PERF_POS_RET_QUALIFIED_STARVED', - 265: 'PERF_POS_RET_1_CACHELINE_POSITION_USED', - 266: 'PERF_POS_RET_2_CACHELINE_POSITION_USED', - 267: 'PERF_POS_RET_3_CACHELINE_POSITION_USED', - 268: 'PERF_POS_RET_4_CACHELINE_POSITION_USED', - 269: 'PERF_TC_INDEX_LATENCY_BIN0', - 270: 'PERF_TC_INDEX_LATENCY_BIN1', - 271: 'PERF_TC_INDEX_LATENCY_BIN2', - 272: 'PERF_TC_INDEX_LATENCY_BIN3', - 273: 'PERF_TC_INDEX_LATENCY_BIN4', - 274: 'PERF_TC_INDEX_LATENCY_BIN5', - 275: 'PERF_TC_INDEX_LATENCY_BIN6', - 276: 'PERF_TC_INDEX_LATENCY_BIN7', - 277: 'PERF_TC_INDEX_LATENCY_BIN8', - 278: 'PERF_TC_INDEX_LATENCY_BIN9', - 279: 'PERF_TC_INDEX_LATENCY_BIN10', - 280: 'PERF_TC_INDEX_LATENCY_BIN11', - 281: 'PERF_TC_INDEX_LATENCY_BIN12', - 282: 'PERF_TC_INDEX_LATENCY_BIN13', - 283: 'PERF_TC_INDEX_LATENCY_BIN14', - 284: 'PERF_TC_INDEX_LATENCY_BIN15', - 285: 'PERF_TC_POSITION_LATENCY_BIN0', - 286: 'PERF_TC_POSITION_LATENCY_BIN1', - 287: 'PERF_TC_POSITION_LATENCY_BIN2', - 288: 'PERF_TC_POSITION_LATENCY_BIN3', - 289: 'PERF_TC_POSITION_LATENCY_BIN4', - 290: 'PERF_TC_POSITION_LATENCY_BIN5', - 291: 'PERF_TC_POSITION_LATENCY_BIN6', - 292: 'PERF_TC_POSITION_LATENCY_BIN7', - 293: 'PERF_TC_POSITION_LATENCY_BIN8', - 294: 'PERF_TC_POSITION_LATENCY_BIN9', - 295: 'PERF_TC_POSITION_LATENCY_BIN10', - 296: 'PERF_TC_POSITION_LATENCY_BIN11', - 297: 'PERF_TC_POSITION_LATENCY_BIN12', - 298: 'PERF_TC_POSITION_LATENCY_BIN13', - 299: 'PERF_TC_POSITION_LATENCY_BIN14', - 300: 'PERF_TC_POSITION_LATENCY_BIN15', - 301: 'PERF_TC_STREAM0_DATA_AVAILABLE', - 302: 'PERF_TC_STREAM1_DATA_AVAILABLE', - 303: 'PERF_TC_STREAM2_DATA_AVAILABLE', - 304: 'PERF_PAWD_DEALLOC_FIFO_IS_FULL', - 305: 'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ', - 306: 'PERF_SHOOTDOWN_WAIT_ON_UTCL1', - 307: 'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND', - 308: 'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX', - 309: 'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION', - 310: 'PERF_SHOOTDOWN_WAIT_ALL_CLEAN', - 311: 'PERF_SHOOTDOWN_WAIT_DEASSERT', - 312: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT0', - 313: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT1', - 314: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT2', - 315: 'PERF_UTCL1_PERMISSION_MISS_CLIENT0', - 316: 'PERF_UTCL1_PERMISSION_MISS_CLIENT1', - 317: 'PERF_UTCL1_PERMISSION_MISS_CLIENT2', - 318: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT0', - 319: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT1', - 320: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT2', - 321: 'PERF_UTCL1_REQUEST_CLIENT0', - 322: 'PERF_UTCL1_REQUEST_CLIENT1', - 323: 'PERF_UTCL1_REQUEST_CLIENT2', - 324: 'PERF_UTCL1_STALL_MISSFIFO_FULL', - 325: 'PERF_UTCL1_STALL_INFLIGHT_MAX', - 326: 'PERF_UTCL1_STALL_LRU_INFLIGHT', - 327: 'PERF_UTCL1_STALL_MULTI_MISS', - 328: 'PERF_UTCL1_LFIFO_FULL', - 329: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0', - 330: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1', - 331: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2', - 332: 'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 333: 'PERF_UTCL1_UTCL2_REQ', - 334: 'PERF_UTCL1_UTCL2_RET', - 335: 'PERF_UTCL1_UTCL2_INFLIGHT', - 336: 'PERF_CLIENT_UTCL1_INFLIGHT', - 337: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 338: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 339: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 340: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 341: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 342: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 343: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 344: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 345: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 346: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 347: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 348: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 349: 'PERF_PA_VERTEX_FIFO_FULL', - 350: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', - 351: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 352: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', - 355: 'ENGG_CSB_MACHINE_IS_STARVED', - 356: 'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 357: 'ENGG_CSB_MACHINE_STALLED_BY_SPI', - 358: 'ENGG_CSB_GE_INPUT_FIFO_FULL', - 359: 'ENGG_CSB_SPI_INPUT_FIFO_FULL', - 360: 'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL', - 361: 'ENGG_CSB_PRIM_COUNT_EQ0', - 362: 'ENGG_CSB_GE_SENDING_SUBGROUP', - 363: 'ENGG_CSB_DELAY_BIN00', - 364: 'ENGG_CSB_DELAY_BIN01', - 365: 'ENGG_CSB_DELAY_BIN02', - 366: 'ENGG_CSB_DELAY_BIN03', - 367: 'ENGG_CSB_DELAY_BIN04', - 368: 'ENGG_CSB_DELAY_BIN05', - 369: 'ENGG_CSB_DELAY_BIN06', - 370: 'ENGG_CSB_DELAY_BIN07', - 371: 'ENGG_CSB_DELAY_BIN08', - 372: 'ENGG_CSB_DELAY_BIN09', - 373: 'ENGG_CSB_DELAY_BIN10', - 374: 'ENGG_CSB_DELAY_BIN11', - 375: 'ENGG_CSB_DELAY_BIN12', - 376: 'ENGG_CSB_DELAY_BIN13', - 377: 'ENGG_CSB_DELAY_BIN14', - 378: 'ENGG_CSB_DELAY_BIN15', - 379: 'ENGG_CSB_SPI_DELAY_BIN00', - 380: 'ENGG_CSB_SPI_DELAY_BIN01', - 381: 'ENGG_CSB_SPI_DELAY_BIN02', - 382: 'ENGG_CSB_SPI_DELAY_BIN03', - 383: 'ENGG_CSB_SPI_DELAY_BIN04', - 384: 'ENGG_CSB_SPI_DELAY_BIN05', - 385: 'ENGG_CSB_SPI_DELAY_BIN06', - 386: 'ENGG_CSB_SPI_DELAY_BIN07', - 387: 'ENGG_CSB_SPI_DELAY_BIN08', - 388: 'ENGG_CSB_SPI_DELAY_BIN09', - 389: 'ENGG_CSB_SPI_DELAY_BIN10', - 390: 'ENGG_CSB_SPI_DELAY_BIN11', - 391: 'ENGG_CSB_SPI_DELAY_BIN12', - 392: 'ENGG_CSB_SPI_DELAY_BIN13', - 393: 'ENGG_CSB_SPI_DELAY_BIN14', - 394: 'ENGG_CSB_SPI_DELAY_BIN15', - 395: 'ENGG_INDEX_REQ_STARVED', - 396: 'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 397: 'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 398: 'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 399: 'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 400: 'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 401: 'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 402: 'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 403: 'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 404: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 405: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 406: 'ENGG_INDEX_RET_SXRX_READING_EVENT', - 407: 'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 408: 'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 409: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 410: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 411: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 412: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 413: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS', - 414: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS', - 415: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS', - 416: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 417: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 418: 'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 419: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 420: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 421: 'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY', - 422: 'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED', - 423: 'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM', - 424: 'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM', - 425: 'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM', - 426: 'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM', - 427: 'ENGG_POS_REQ_STARVED', - 428: 'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO', -} -PERF_PAPC_PASX_REQ = 0 -PERF_PAPC_PASX_DISABLE_PIPE = 1 -PERF_PAPC_PASX_FIRST_VECTOR = 2 -PERF_PAPC_PASX_SECOND_VECTOR = 3 -PERF_PAPC_PASX_FIRST_DEAD = 4 -PERF_PAPC_PASX_SECOND_DEAD = 5 -PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 -PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 -PERF_PAPC_PA_INPUT_PRIM = 8 -PERF_PAPC_PA_INPUT_NULL_PRIM = 9 -PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 -PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 -PERF_PAPC_CLPR_CULL_PRIM = 14 -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 -PERF_PAPC_CLPR_VV_CULL_PRIM = 16 -PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 -PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 -PERF_PAPC_CLSM_NULL_PRIM = 39 -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 -PERF_PAPC_SU_INPUT_PRIM = 49 -PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 -PERF_PAPC_SU_INPUT_NULL_PRIM = 51 -PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 -PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 -PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 -PERF_PAPC_SU_OUTPUT_PRIM = 61 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 -PERF_PAPC_PASX_REQ_IDLE = 77 -PERF_PAPC_PASX_REQ_BUSY = 78 -PERF_PAPC_PASX_REQ_STALLED = 79 -PERF_PAPC_PASX_REC_IDLE = 80 -PERF_PAPC_PASX_REC_BUSY = 81 -PERF_PAPC_PASX_REC_STARVED_SX = 82 -PERF_PAPC_PASX_REC_STALLED = 83 -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 -PERF_PAPC_CCGSM_IDLE = 86 -PERF_PAPC_CCGSM_BUSY = 87 -PERF_PAPC_CCGSM_STALLED = 88 -PERF_PAPC_CLPRIM_IDLE = 89 -PERF_PAPC_CLPRIM_BUSY = 90 -PERF_PAPC_CLPRIM_STALLED = 91 -PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 -PERF_PAPC_CLIPSM_IDLE = 93 -PERF_PAPC_CLIPSM_BUSY = 94 -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 -PERF_PAPC_CLIPGA_IDLE = 100 -PERF_PAPC_CLIPGA_BUSY = 101 -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 -PERF_PAPC_CLIPGA_STALLED = 103 -PERF_PAPC_CLIP_IDLE = 104 -PERF_PAPC_CLIP_BUSY = 105 -PERF_PAPC_SU_IDLE = 106 -PERF_PAPC_SU_BUSY = 107 -PERF_PAPC_SU_STARVED_CLIP = 108 -PERF_PAPC_SU_STALLED_SC = 109 -PERF_PAPC_CL_DYN_SCLK_VLD = 110 -PERF_PAPC_SU_DYN_SCLK_VLD = 111 -PERF_PAPC_PA_REG_SCLK_VLD = 112 -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 -PERF_PAPC_PASX_SE0_REQ = 114 -PERF_PAPC_PASX_SE1_REQ = 115 -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 -PERF_PAPC_SU_SE0_STALLED_SC = 131 -PERF_PAPC_SU_SE1_STALLED_SC = 132 -PERF_PAPC_SU_SE01_STALLED_SC = 133 -PERF_PAPC_CLSM_CLIPPING_PRIM = 134 -PERF_PAPC_SU_CULLED_PRIM = 135 -PERF_PAPC_SU_OUTPUT_EOPG = 136 -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 -PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 -PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 -PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 -PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 -PERF_PAPC_SU_SE2_STALLED_SC = 151 -PERF_PAPC_SU_SE3_STALLED_SC = 152 -PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 -PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 -PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 -PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 -PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 -PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 -PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 -PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 -PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 -PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 -PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 -PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 -PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 -PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 -PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 -PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 -PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169 -PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170 -PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171 -PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172 -PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173 -PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174 -PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175 -PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176 -PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 177 -PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 178 -PERF_UTC_SIDEBAND_DRIVER_BUSY = 179 -PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 180 -PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 181 -PERF_UTC_INDEX_DRIVER_BUSY = 182 -PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 183 -PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 184 -PERF_UTC_POSITION_DRIVER_BUSY = 185 -PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 186 -PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 187 -PERF_UTC_SIDEBAND_RECEIVER_BUSY = 188 -PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 189 -PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 190 -PERF_UTC_INDEX_RECEIVER_BUSY = 191 -PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 192 -PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 193 -PERF_UTC_POSITION_RECEIVER_BUSY = 194 -PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 195 -PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 196 -PERF_TCIF_BUSY = 197 -PERF_TCIF_SIDEBAND_RDREQ = 198 -PERF_TCIF_INDEX_RDREQ = 199 -PERF_TCIF_POSITION_RDREQ = 200 -PERF_SIDEBAND_WAITING_ON_UTCL1 = 201 -PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 202 -PERF_WRITING_TO_SIDEBAND_MEMORY = 203 -PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 204 -PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 205 -PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 206 -PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 207 -PERF_SIDEBAND_POP_BIT_FIFO_FULL = 208 -PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 209 -PERF_SIDEBAND_INVALID_REFETCH = 210 -PERF_SIDEBAND_QUALIFIED_BUSY = 211 -PERF_SIDEBAND_QUALIFIED_STARVED = 212 -PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 213 -PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 214 -PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 215 -PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 216 -PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 217 -PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 218 -PERF_INDEX_REQUEST_QUALIFIED_BUSY = 219 -PERF_INDEX_REQUEST_QUALIFIED_STARVED = 220 -PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 221 -PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 222 -PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 223 -PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 224 -PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 225 -PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 226 -PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE = 227 -PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE = 228 -PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE = 229 -PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE = 230 -PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE = 231 -PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE = 232 -PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE = 233 -PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE = 234 -PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE = 235 -PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE = 236 -PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE = 237 -PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE = 238 -PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE = 239 -PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE = 240 -PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE = 241 -PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 242 -PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 243 -PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 244 -PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 245 -PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 246 -PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 247 -PERF_POS_REQ_STALLED_BY_NO_TOKENS = 248 -PERF_POS_REQ_STARVED_BY_NO_PRIM = 249 -PERF_POS_REQ_STALLED_BY_UTCL1 = 250 -PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 251 -PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 252 -PERF_POS_REQ_QUALIFIED_BUSY = 253 -PERF_POS_REQ_QUALIFIED_STARVED = 254 -PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM = 255 -PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM = 256 -PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM = 257 -PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM = 258 -PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 259 -PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 260 -PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 261 -PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 262 -PERF_POS_RET_QUALIFIED_BUSY = 263 -PERF_POS_RET_QUALIFIED_STARVED = 264 -PERF_POS_RET_1_CACHELINE_POSITION_USED = 265 -PERF_POS_RET_2_CACHELINE_POSITION_USED = 266 -PERF_POS_RET_3_CACHELINE_POSITION_USED = 267 -PERF_POS_RET_4_CACHELINE_POSITION_USED = 268 -PERF_TC_INDEX_LATENCY_BIN0 = 269 -PERF_TC_INDEX_LATENCY_BIN1 = 270 -PERF_TC_INDEX_LATENCY_BIN2 = 271 -PERF_TC_INDEX_LATENCY_BIN3 = 272 -PERF_TC_INDEX_LATENCY_BIN4 = 273 -PERF_TC_INDEX_LATENCY_BIN5 = 274 -PERF_TC_INDEX_LATENCY_BIN6 = 275 -PERF_TC_INDEX_LATENCY_BIN7 = 276 -PERF_TC_INDEX_LATENCY_BIN8 = 277 -PERF_TC_INDEX_LATENCY_BIN9 = 278 -PERF_TC_INDEX_LATENCY_BIN10 = 279 -PERF_TC_INDEX_LATENCY_BIN11 = 280 -PERF_TC_INDEX_LATENCY_BIN12 = 281 -PERF_TC_INDEX_LATENCY_BIN13 = 282 -PERF_TC_INDEX_LATENCY_BIN14 = 283 -PERF_TC_INDEX_LATENCY_BIN15 = 284 -PERF_TC_POSITION_LATENCY_BIN0 = 285 -PERF_TC_POSITION_LATENCY_BIN1 = 286 -PERF_TC_POSITION_LATENCY_BIN2 = 287 -PERF_TC_POSITION_LATENCY_BIN3 = 288 -PERF_TC_POSITION_LATENCY_BIN4 = 289 -PERF_TC_POSITION_LATENCY_BIN5 = 290 -PERF_TC_POSITION_LATENCY_BIN6 = 291 -PERF_TC_POSITION_LATENCY_BIN7 = 292 -PERF_TC_POSITION_LATENCY_BIN8 = 293 -PERF_TC_POSITION_LATENCY_BIN9 = 294 -PERF_TC_POSITION_LATENCY_BIN10 = 295 -PERF_TC_POSITION_LATENCY_BIN11 = 296 -PERF_TC_POSITION_LATENCY_BIN12 = 297 -PERF_TC_POSITION_LATENCY_BIN13 = 298 -PERF_TC_POSITION_LATENCY_BIN14 = 299 -PERF_TC_POSITION_LATENCY_BIN15 = 300 -PERF_TC_STREAM0_DATA_AVAILABLE = 301 -PERF_TC_STREAM1_DATA_AVAILABLE = 302 -PERF_TC_STREAM2_DATA_AVAILABLE = 303 -PERF_PAWD_DEALLOC_FIFO_IS_FULL = 304 -PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 305 -PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 306 -PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 307 -PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 308 -PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 309 -PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 310 -PERF_SHOOTDOWN_WAIT_DEASSERT = 311 -PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 312 -PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 313 -PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 314 -PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 315 -PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 316 -PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 317 -PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 318 -PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 319 -PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 320 -PERF_UTCL1_REQUEST_CLIENT0 = 321 -PERF_UTCL1_REQUEST_CLIENT1 = 322 -PERF_UTCL1_REQUEST_CLIENT2 = 323 -PERF_UTCL1_STALL_MISSFIFO_FULL = 324 -PERF_UTCL1_STALL_INFLIGHT_MAX = 325 -PERF_UTCL1_STALL_LRU_INFLIGHT = 326 -PERF_UTCL1_STALL_MULTI_MISS = 327 -PERF_UTCL1_LFIFO_FULL = 328 -PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 329 -PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 330 -PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 331 -PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 332 -PERF_UTCL1_UTCL2_REQ = 333 -PERF_UTCL1_UTCL2_RET = 334 -PERF_UTCL1_UTCL2_INFLIGHT = 335 -PERF_CLIENT_UTCL1_INFLIGHT = 336 -PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 337 -PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 338 -PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 339 -PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 340 -PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 341 -PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 342 -PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 343 -PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 344 -PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 345 -PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 346 -PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 347 -PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 348 -PERF_PA_VERTEX_FIFO_FULL = 349 -PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 350 -PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 351 -PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 352 -ENGG_CSB_MACHINE_IS_STARVED = 355 -ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 356 -ENGG_CSB_MACHINE_STALLED_BY_SPI = 357 -ENGG_CSB_GE_INPUT_FIFO_FULL = 358 -ENGG_CSB_SPI_INPUT_FIFO_FULL = 359 -ENGG_CSB_OBJECTID_INPUT_FIFO_FULL = 360 -ENGG_CSB_PRIM_COUNT_EQ0 = 361 -ENGG_CSB_GE_SENDING_SUBGROUP = 362 -ENGG_CSB_DELAY_BIN00 = 363 -ENGG_CSB_DELAY_BIN01 = 364 -ENGG_CSB_DELAY_BIN02 = 365 -ENGG_CSB_DELAY_BIN03 = 366 -ENGG_CSB_DELAY_BIN04 = 367 -ENGG_CSB_DELAY_BIN05 = 368 -ENGG_CSB_DELAY_BIN06 = 369 -ENGG_CSB_DELAY_BIN07 = 370 -ENGG_CSB_DELAY_BIN08 = 371 -ENGG_CSB_DELAY_BIN09 = 372 -ENGG_CSB_DELAY_BIN10 = 373 -ENGG_CSB_DELAY_BIN11 = 374 -ENGG_CSB_DELAY_BIN12 = 375 -ENGG_CSB_DELAY_BIN13 = 376 -ENGG_CSB_DELAY_BIN14 = 377 -ENGG_CSB_DELAY_BIN15 = 378 -ENGG_CSB_SPI_DELAY_BIN00 = 379 -ENGG_CSB_SPI_DELAY_BIN01 = 380 -ENGG_CSB_SPI_DELAY_BIN02 = 381 -ENGG_CSB_SPI_DELAY_BIN03 = 382 -ENGG_CSB_SPI_DELAY_BIN04 = 383 -ENGG_CSB_SPI_DELAY_BIN05 = 384 -ENGG_CSB_SPI_DELAY_BIN06 = 385 -ENGG_CSB_SPI_DELAY_BIN07 = 386 -ENGG_CSB_SPI_DELAY_BIN08 = 387 -ENGG_CSB_SPI_DELAY_BIN09 = 388 -ENGG_CSB_SPI_DELAY_BIN10 = 389 -ENGG_CSB_SPI_DELAY_BIN11 = 390 -ENGG_CSB_SPI_DELAY_BIN12 = 391 -ENGG_CSB_SPI_DELAY_BIN13 = 392 -ENGG_CSB_SPI_DELAY_BIN14 = 393 -ENGG_CSB_SPI_DELAY_BIN15 = 394 -ENGG_INDEX_REQ_STARVED = 395 -ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 396 -ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 397 -ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 398 -ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 399 -ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 400 -ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 401 -ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 402 -ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 403 -ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 404 -ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 405 -ENGG_INDEX_RET_SXRX_READING_EVENT = 406 -ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 407 -ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 408 -ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 409 -ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 410 -ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 411 -ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 412 -ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS = 413 -ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS = 414 -ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS = 415 -ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 416 -ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 417 -ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 418 -ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 419 -ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 420 -ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY = 421 -ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED = 422 -ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM = 423 -ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM = 424 -ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM = 425 -ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM = 426 -ENGG_POS_REQ_STARVED = 427 -ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO = 428 -SU_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SC_PERFCNT_SEL' -SC_PERFCNT_SEL__enumvalues = { - 0: 'SC_SRPS_WINDOW_VALID', - 1: 'SC_PSSW_WINDOW_VALID', - 2: 'SC_TPQZ_WINDOW_VALID', - 3: 'SC_QZQP_WINDOW_VALID', - 4: 'SC_TRPK_WINDOW_VALID', - 5: 'SC_SRPS_WINDOW_VALID_BUSY', - 6: 'SC_PSSW_WINDOW_VALID_BUSY', - 7: 'SC_TPQZ_WINDOW_VALID_BUSY', - 8: 'SC_QZQP_WINDOW_VALID_BUSY', - 9: 'SC_TRPK_WINDOW_VALID_BUSY', - 10: 'SC_STARVED_BY_PA', - 11: 'SC_STALLED_BY_PRIMFIFO', - 12: 'SC_STALLED_BY_DB_TILE', - 13: 'SC_STARVED_BY_DB_TILE', - 14: 'SC_STALLED_BY_TILEORDERFIFO', - 15: 'SC_STALLED_BY_TILEFIFO', - 16: 'SC_STALLED_BY_DB_QUAD', - 17: 'SC_STARVED_BY_DB_QUAD', - 18: 'SC_STALLED_BY_QUADFIFO', - 19: 'SC_STALLED_BY_BCI', - 20: 'SC_STALLED_BY_SPI', - 21: 'SC_SCISSOR_DISCARD', - 22: 'SC_BB_DISCARD', - 23: 'SC_SUPERTILE_COUNT', - 24: 'SC_SUPERTILE_PER_PRIM_H0', - 25: 'SC_SUPERTILE_PER_PRIM_H1', - 26: 'SC_SUPERTILE_PER_PRIM_H2', - 27: 'SC_SUPERTILE_PER_PRIM_H3', - 28: 'SC_SUPERTILE_PER_PRIM_H4', - 29: 'SC_SUPERTILE_PER_PRIM_H5', - 30: 'SC_SUPERTILE_PER_PRIM_H6', - 31: 'SC_SUPERTILE_PER_PRIM_H7', - 32: 'SC_SUPERTILE_PER_PRIM_H8', - 33: 'SC_SUPERTILE_PER_PRIM_H9', - 34: 'SC_SUPERTILE_PER_PRIM_H10', - 35: 'SC_SUPERTILE_PER_PRIM_H11', - 36: 'SC_SUPERTILE_PER_PRIM_H12', - 37: 'SC_SUPERTILE_PER_PRIM_H13', - 38: 'SC_SUPERTILE_PER_PRIM_H14', - 39: 'SC_SUPERTILE_PER_PRIM_H15', - 40: 'SC_SUPERTILE_PER_PRIM_H16', - 41: 'SC_TILE_PER_PRIM_H0', - 42: 'SC_TILE_PER_PRIM_H1', - 43: 'SC_TILE_PER_PRIM_H2', - 44: 'SC_TILE_PER_PRIM_H3', - 45: 'SC_TILE_PER_PRIM_H4', - 46: 'SC_TILE_PER_PRIM_H5', - 47: 'SC_TILE_PER_PRIM_H6', - 48: 'SC_TILE_PER_PRIM_H7', - 49: 'SC_TILE_PER_PRIM_H8', - 50: 'SC_TILE_PER_PRIM_H9', - 51: 'SC_TILE_PER_PRIM_H10', - 52: 'SC_TILE_PER_PRIM_H11', - 53: 'SC_TILE_PER_PRIM_H12', - 54: 'SC_TILE_PER_PRIM_H13', - 55: 'SC_TILE_PER_PRIM_H14', - 56: 'SC_TILE_PER_PRIM_H15', - 57: 'SC_TILE_PER_PRIM_H16', - 58: 'SC_TILE_PER_SUPERTILE_H0', - 59: 'SC_TILE_PER_SUPERTILE_H1', - 60: 'SC_TILE_PER_SUPERTILE_H2', - 61: 'SC_TILE_PER_SUPERTILE_H3', - 62: 'SC_TILE_PER_SUPERTILE_H4', - 63: 'SC_TILE_PER_SUPERTILE_H5', - 64: 'SC_TILE_PER_SUPERTILE_H6', - 65: 'SC_TILE_PER_SUPERTILE_H7', - 66: 'SC_TILE_PER_SUPERTILE_H8', - 67: 'SC_TILE_PER_SUPERTILE_H9', - 68: 'SC_TILE_PER_SUPERTILE_H10', - 69: 'SC_TILE_PER_SUPERTILE_H11', - 70: 'SC_TILE_PER_SUPERTILE_H12', - 71: 'SC_TILE_PER_SUPERTILE_H13', - 72: 'SC_TILE_PER_SUPERTILE_H14', - 73: 'SC_TILE_PER_SUPERTILE_H15', - 74: 'SC_TILE_PER_SUPERTILE_H16', - 75: 'SC_TILE_PICKED_H1', - 76: 'SC_TILE_PICKED_H2', - 77: 'SC_TILE_PICKED_H3', - 78: 'SC_TILE_PICKED_H4', - 79: 'SC_QZ0_TILE_COUNT', - 80: 'SC_QZ1_TILE_COUNT', - 81: 'SC_QZ2_TILE_COUNT', - 82: 'SC_QZ3_TILE_COUNT', - 83: 'SC_QZ0_TILE_COVERED_COUNT', - 84: 'SC_QZ1_TILE_COVERED_COUNT', - 85: 'SC_QZ2_TILE_COVERED_COUNT', - 86: 'SC_QZ3_TILE_COVERED_COUNT', - 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', - 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 91: 'SC_QZ0_QUAD_PER_TILE_H0', - 92: 'SC_QZ0_QUAD_PER_TILE_H1', - 93: 'SC_QZ0_QUAD_PER_TILE_H2', - 94: 'SC_QZ0_QUAD_PER_TILE_H3', - 95: 'SC_QZ0_QUAD_PER_TILE_H4', - 96: 'SC_QZ0_QUAD_PER_TILE_H5', - 97: 'SC_QZ0_QUAD_PER_TILE_H6', - 98: 'SC_QZ0_QUAD_PER_TILE_H7', - 99: 'SC_QZ0_QUAD_PER_TILE_H8', - 100: 'SC_QZ0_QUAD_PER_TILE_H9', - 101: 'SC_QZ0_QUAD_PER_TILE_H10', - 102: 'SC_QZ0_QUAD_PER_TILE_H11', - 103: 'SC_QZ0_QUAD_PER_TILE_H12', - 104: 'SC_QZ0_QUAD_PER_TILE_H13', - 105: 'SC_QZ0_QUAD_PER_TILE_H14', - 106: 'SC_QZ0_QUAD_PER_TILE_H15', - 107: 'SC_QZ0_QUAD_PER_TILE_H16', - 108: 'SC_QZ1_QUAD_PER_TILE_H0', - 109: 'SC_QZ1_QUAD_PER_TILE_H1', - 110: 'SC_QZ1_QUAD_PER_TILE_H2', - 111: 'SC_QZ1_QUAD_PER_TILE_H3', - 112: 'SC_QZ1_QUAD_PER_TILE_H4', - 113: 'SC_QZ1_QUAD_PER_TILE_H5', - 114: 'SC_QZ1_QUAD_PER_TILE_H6', - 115: 'SC_QZ1_QUAD_PER_TILE_H7', - 116: 'SC_QZ1_QUAD_PER_TILE_H8', - 117: 'SC_QZ1_QUAD_PER_TILE_H9', - 118: 'SC_QZ1_QUAD_PER_TILE_H10', - 119: 'SC_QZ1_QUAD_PER_TILE_H11', - 120: 'SC_QZ1_QUAD_PER_TILE_H12', - 121: 'SC_QZ1_QUAD_PER_TILE_H13', - 122: 'SC_QZ1_QUAD_PER_TILE_H14', - 123: 'SC_QZ1_QUAD_PER_TILE_H15', - 124: 'SC_QZ1_QUAD_PER_TILE_H16', - 125: 'SC_QZ2_QUAD_PER_TILE_H0', - 126: 'SC_QZ2_QUAD_PER_TILE_H1', - 127: 'SC_QZ2_QUAD_PER_TILE_H2', - 128: 'SC_QZ2_QUAD_PER_TILE_H3', - 129: 'SC_QZ2_QUAD_PER_TILE_H4', - 130: 'SC_QZ2_QUAD_PER_TILE_H5', - 131: 'SC_QZ2_QUAD_PER_TILE_H6', - 132: 'SC_QZ2_QUAD_PER_TILE_H7', - 133: 'SC_QZ2_QUAD_PER_TILE_H8', - 134: 'SC_QZ2_QUAD_PER_TILE_H9', - 135: 'SC_QZ2_QUAD_PER_TILE_H10', - 136: 'SC_QZ2_QUAD_PER_TILE_H11', - 137: 'SC_QZ2_QUAD_PER_TILE_H12', - 138: 'SC_QZ2_QUAD_PER_TILE_H13', - 139: 'SC_QZ2_QUAD_PER_TILE_H14', - 140: 'SC_QZ2_QUAD_PER_TILE_H15', - 141: 'SC_QZ2_QUAD_PER_TILE_H16', - 142: 'SC_QZ3_QUAD_PER_TILE_H0', - 143: 'SC_QZ3_QUAD_PER_TILE_H1', - 144: 'SC_QZ3_QUAD_PER_TILE_H2', - 145: 'SC_QZ3_QUAD_PER_TILE_H3', - 146: 'SC_QZ3_QUAD_PER_TILE_H4', - 147: 'SC_QZ3_QUAD_PER_TILE_H5', - 148: 'SC_QZ3_QUAD_PER_TILE_H6', - 149: 'SC_QZ3_QUAD_PER_TILE_H7', - 150: 'SC_QZ3_QUAD_PER_TILE_H8', - 151: 'SC_QZ3_QUAD_PER_TILE_H9', - 152: 'SC_QZ3_QUAD_PER_TILE_H10', - 153: 'SC_QZ3_QUAD_PER_TILE_H11', - 154: 'SC_QZ3_QUAD_PER_TILE_H12', - 155: 'SC_QZ3_QUAD_PER_TILE_H13', - 156: 'SC_QZ3_QUAD_PER_TILE_H14', - 157: 'SC_QZ3_QUAD_PER_TILE_H15', - 158: 'SC_QZ3_QUAD_PER_TILE_H16', - 159: 'SC_QZ0_QUAD_COUNT', - 160: 'SC_QZ1_QUAD_COUNT', - 161: 'SC_QZ2_QUAD_COUNT', - 162: 'SC_QZ3_QUAD_COUNT', - 163: 'SC_P0_HIZ_TILE_COUNT', - 164: 'SC_P1_HIZ_TILE_COUNT', - 165: 'SC_P2_HIZ_TILE_COUNT', - 166: 'SC_P3_HIZ_TILE_COUNT', - 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 235: 'SC_P0_HIZ_QUAD_COUNT', - 236: 'SC_P1_HIZ_QUAD_COUNT', - 237: 'SC_P2_HIZ_QUAD_COUNT', - 238: 'SC_P3_HIZ_QUAD_COUNT', - 239: 'SC_P0_DETAIL_QUAD_COUNT', - 240: 'SC_P1_DETAIL_QUAD_COUNT', - 241: 'SC_P2_DETAIL_QUAD_COUNT', - 242: 'SC_P3_DETAIL_QUAD_COUNT', - 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 259: 'SC_EARLYZ_QUAD_COUNT', - 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', - 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', - 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', - 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', - 264: 'SC_PKR_QUAD_PER_ROW_H1', - 265: 'SC_PKR_QUAD_PER_ROW_H2', - 266: 'SC_PKR_4X2_QUAD_SPLIT', - 267: 'SC_PKR_4X2_FILL_QUAD', - 268: 'SC_PKR_END_OF_VECTOR', - 269: 'SC_PKR_CONTROL_XFER', - 270: 'SC_PKR_DBHANG_FORCE_EOV', - 271: 'SC_REG_SCLK_BUSY', - 272: 'SC_GRP0_DYN_SCLK_BUSY', - 273: 'SC_GRP1_DYN_SCLK_BUSY', - 274: 'SC_GRP2_DYN_SCLK_BUSY', - 275: 'SC_GRP3_DYN_SCLK_BUSY', - 276: 'SC_GRP4_DYN_SCLK_BUSY', - 277: 'SC_PA0_SC_DATA_FIFO_RD', - 278: 'SC_PA0_SC_DATA_FIFO_WE', - 279: 'SC_PA1_SC_DATA_FIFO_RD', - 280: 'SC_PA1_SC_DATA_FIFO_WE', - 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', - 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 284: 'SC_PS_ARB_STALLED_FROM_BELOW', - 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', - 286: 'SC_PS_ARB_SC_BUSY', - 287: 'SC_PS_ARB_PA_SC_BUSY', - 288: 'SC_PA2_SC_DATA_FIFO_RD', - 289: 'SC_PA2_SC_DATA_FIFO_WE', - 290: 'SC_PA3_SC_DATA_FIFO_RD', - 291: 'SC_PA3_SC_DATA_FIFO_WE', - 292: 'SC_PA_SC_DEALLOC_0_0_WE', - 293: 'SC_PA_SC_DEALLOC_0_1_WE', - 294: 'SC_PA_SC_DEALLOC_1_0_WE', - 295: 'SC_PA_SC_DEALLOC_1_1_WE', - 296: 'SC_PA_SC_DEALLOC_2_0_WE', - 297: 'SC_PA_SC_DEALLOC_2_1_WE', - 298: 'SC_PA_SC_DEALLOC_3_0_WE', - 299: 'SC_PA_SC_DEALLOC_3_1_WE', - 300: 'SC_PA0_SC_EOP_WE', - 301: 'SC_PA0_SC_EOPG_WE', - 302: 'SC_PA0_SC_EVENT_WE', - 303: 'SC_PA1_SC_EOP_WE', - 304: 'SC_PA1_SC_EOPG_WE', - 305: 'SC_PA1_SC_EVENT_WE', - 306: 'SC_PA2_SC_EOP_WE', - 307: 'SC_PA2_SC_EOPG_WE', - 308: 'SC_PA2_SC_EVENT_WE', - 309: 'SC_PA3_SC_EOP_WE', - 310: 'SC_PA3_SC_EOPG_WE', - 311: 'SC_PA3_SC_EVENT_WE', - 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', - 316: 'SC_PS_ARB_EVENT_SYNC_POP', - 317: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', - 318: 'SC_PA0_SC_FPOV_WE', - 319: 'SC_PA1_SC_FPOV_WE', - 320: 'SC_PA2_SC_FPOV_WE', - 321: 'SC_PA3_SC_FPOV_WE', - 322: 'SC_PA0_SC_LPOV_WE', - 323: 'SC_PA1_SC_LPOV_WE', - 324: 'SC_PA2_SC_LPOV_WE', - 325: 'SC_PA3_SC_LPOV_WE', - 326: 'SC_SC_SPI_DEALLOC_0_0', - 327: 'SC_SC_SPI_DEALLOC_0_1', - 328: 'SC_SC_SPI_DEALLOC_0_2', - 329: 'SC_SC_SPI_DEALLOC_1_0', - 330: 'SC_SC_SPI_DEALLOC_1_1', - 331: 'SC_SC_SPI_DEALLOC_1_2', - 332: 'SC_SC_SPI_DEALLOC_2_0', - 333: 'SC_SC_SPI_DEALLOC_2_1', - 334: 'SC_SC_SPI_DEALLOC_2_2', - 335: 'SC_SC_SPI_DEALLOC_3_0', - 336: 'SC_SC_SPI_DEALLOC_3_1', - 337: 'SC_SC_SPI_DEALLOC_3_2', - 338: 'SC_SC_SPI_FPOV_0', - 339: 'SC_SC_SPI_FPOV_1', - 340: 'SC_SC_SPI_FPOV_2', - 341: 'SC_SC_SPI_FPOV_3', - 342: 'SC_SC_SPI_EVENT', - 343: 'SC_PS_TS_EVENT_FIFO_PUSH', - 344: 'SC_PS_TS_EVENT_FIFO_POP', - 345: 'SC_PS_CTX_DONE_FIFO_PUSH', - 346: 'SC_PS_CTX_DONE_FIFO_POP', - 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', - 348: 'SC_EOP_SYNC_WINDOW', - 349: 'SC_PA0_SC_NULL_WE', - 350: 'SC_PA0_SC_NULL_DEALLOC_WE', - 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', - 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 353: 'SC_PA0_SC_DEALLOC_0_RD', - 354: 'SC_PA0_SC_DEALLOC_1_RD', - 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', - 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 357: 'SC_PA1_SC_DEALLOC_0_RD', - 358: 'SC_PA1_SC_DEALLOC_1_RD', - 359: 'SC_PA1_SC_NULL_WE', - 360: 'SC_PA1_SC_NULL_DEALLOC_WE', - 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', - 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 363: 'SC_PA2_SC_DEALLOC_0_RD', - 364: 'SC_PA2_SC_DEALLOC_1_RD', - 365: 'SC_PA2_SC_NULL_WE', - 366: 'SC_PA2_SC_NULL_DEALLOC_WE', - 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', - 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 369: 'SC_PA3_SC_DEALLOC_0_RD', - 370: 'SC_PA3_SC_DEALLOC_1_RD', - 371: 'SC_PA3_SC_NULL_WE', - 372: 'SC_PA3_SC_NULL_DEALLOC_WE', - 373: 'SC_PS_PA0_SC_FIFO_EMPTY', - 374: 'SC_PS_PA0_SC_FIFO_FULL', - 375: 'SC_RESERVED_0', - 376: 'SC_PS_PA1_SC_FIFO_EMPTY', - 377: 'SC_PS_PA1_SC_FIFO_FULL', - 378: 'SC_RESERVED_1', - 379: 'SC_PS_PA2_SC_FIFO_EMPTY', - 380: 'SC_PS_PA2_SC_FIFO_FULL', - 381: 'SC_RESERVED_2', - 382: 'SC_PS_PA3_SC_FIFO_EMPTY', - 383: 'SC_PS_PA3_SC_FIFO_FULL', - 384: 'SC_RESERVED_3', - 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', - 386: 'SC_BUSY_CNT_NOT_ZERO', - 387: 'SC_BM_BUSY', - 388: 'SC_BACKEND_BUSY', - 389: 'SC_SCF_SCB_INTERFACE_BUSY', - 390: 'SC_SCB_BUSY', - 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', - 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 403: 'SC_PBB_BUSY', - 404: 'SC_PBB_BUSY_AND_NO_SENDS', - 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 406: 'SC_PBB_NUM_BINS', - 407: 'SC_PBB_END_OF_BIN', - 408: 'SC_PBB_END_OF_BATCH', - 409: 'SC_PBB_PRIMBIN_PROCESSED', - 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', - 411: 'SC_PBB_NONBINNED_PRIM', - 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', - 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', - 424: 'SC_POPS_FORCE_EOV', - 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 428: 'SC_FULL_FULL_QUAD', - 429: 'SC_FULL_HALF_QUAD', - 430: 'SC_FULL_QTR_QUAD', - 431: 'SC_HALF_FULL_QUAD', - 432: 'SC_HALF_HALF_QUAD', - 433: 'SC_HALF_QTR_QUAD', - 434: 'SC_QTR_FULL_QUAD', - 435: 'SC_QTR_HALF_QUAD', - 436: 'SC_QTR_QTR_QUAD', - 437: 'SC_GRP5_DYN_SCLK_BUSY', - 438: 'SC_GRP6_DYN_SCLK_BUSY', - 439: 'SC_GRP7_DYN_SCLK_BUSY', - 440: 'SC_GRP8_DYN_SCLK_BUSY', - 441: 'SC_GRP9_DYN_SCLK_BUSY', - 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', - 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 444: 'SC_PK_BUSY', - 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 446: 'SC_PK_DEALLOC_WAVE_BREAK', - 447: 'SC_SPI_SEND', - 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 449: 'SC_SPI_CREDIT_AT_MAX', - 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 451: 'SC_BCI_SEND', - 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 453: 'SC_BCI_CREDIT_AT_MAX', - 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 455: 'SC_SPIBC_FULL_FREEZE', - 456: 'SC_PW_BM_PASS_EMPTY_PRIM', - 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 475: 'SC_DB0_TILE_INTERFACE_BUSY', - 476: 'SC_DB0_TILE_INTERFACE_SEND', - 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 483: 'SC_DB1_TILE_INTERFACE_BUSY', - 484: 'SC_DB1_TILE_INTERFACE_SEND', - 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 491: 'SC_BACKEND_PRIM_FIFO_FULL', - 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', -} -SC_SRPS_WINDOW_VALID = 0 -SC_PSSW_WINDOW_VALID = 1 -SC_TPQZ_WINDOW_VALID = 2 -SC_QZQP_WINDOW_VALID = 3 -SC_TRPK_WINDOW_VALID = 4 -SC_SRPS_WINDOW_VALID_BUSY = 5 -SC_PSSW_WINDOW_VALID_BUSY = 6 -SC_TPQZ_WINDOW_VALID_BUSY = 7 -SC_QZQP_WINDOW_VALID_BUSY = 8 -SC_TRPK_WINDOW_VALID_BUSY = 9 -SC_STARVED_BY_PA = 10 -SC_STALLED_BY_PRIMFIFO = 11 -SC_STALLED_BY_DB_TILE = 12 -SC_STARVED_BY_DB_TILE = 13 -SC_STALLED_BY_TILEORDERFIFO = 14 -SC_STALLED_BY_TILEFIFO = 15 -SC_STALLED_BY_DB_QUAD = 16 -SC_STARVED_BY_DB_QUAD = 17 -SC_STALLED_BY_QUADFIFO = 18 -SC_STALLED_BY_BCI = 19 -SC_STALLED_BY_SPI = 20 -SC_SCISSOR_DISCARD = 21 -SC_BB_DISCARD = 22 -SC_SUPERTILE_COUNT = 23 -SC_SUPERTILE_PER_PRIM_H0 = 24 -SC_SUPERTILE_PER_PRIM_H1 = 25 -SC_SUPERTILE_PER_PRIM_H2 = 26 -SC_SUPERTILE_PER_PRIM_H3 = 27 -SC_SUPERTILE_PER_PRIM_H4 = 28 -SC_SUPERTILE_PER_PRIM_H5 = 29 -SC_SUPERTILE_PER_PRIM_H6 = 30 -SC_SUPERTILE_PER_PRIM_H7 = 31 -SC_SUPERTILE_PER_PRIM_H8 = 32 -SC_SUPERTILE_PER_PRIM_H9 = 33 -SC_SUPERTILE_PER_PRIM_H10 = 34 -SC_SUPERTILE_PER_PRIM_H11 = 35 -SC_SUPERTILE_PER_PRIM_H12 = 36 -SC_SUPERTILE_PER_PRIM_H13 = 37 -SC_SUPERTILE_PER_PRIM_H14 = 38 -SC_SUPERTILE_PER_PRIM_H15 = 39 -SC_SUPERTILE_PER_PRIM_H16 = 40 -SC_TILE_PER_PRIM_H0 = 41 -SC_TILE_PER_PRIM_H1 = 42 -SC_TILE_PER_PRIM_H2 = 43 -SC_TILE_PER_PRIM_H3 = 44 -SC_TILE_PER_PRIM_H4 = 45 -SC_TILE_PER_PRIM_H5 = 46 -SC_TILE_PER_PRIM_H6 = 47 -SC_TILE_PER_PRIM_H7 = 48 -SC_TILE_PER_PRIM_H8 = 49 -SC_TILE_PER_PRIM_H9 = 50 -SC_TILE_PER_PRIM_H10 = 51 -SC_TILE_PER_PRIM_H11 = 52 -SC_TILE_PER_PRIM_H12 = 53 -SC_TILE_PER_PRIM_H13 = 54 -SC_TILE_PER_PRIM_H14 = 55 -SC_TILE_PER_PRIM_H15 = 56 -SC_TILE_PER_PRIM_H16 = 57 -SC_TILE_PER_SUPERTILE_H0 = 58 -SC_TILE_PER_SUPERTILE_H1 = 59 -SC_TILE_PER_SUPERTILE_H2 = 60 -SC_TILE_PER_SUPERTILE_H3 = 61 -SC_TILE_PER_SUPERTILE_H4 = 62 -SC_TILE_PER_SUPERTILE_H5 = 63 -SC_TILE_PER_SUPERTILE_H6 = 64 -SC_TILE_PER_SUPERTILE_H7 = 65 -SC_TILE_PER_SUPERTILE_H8 = 66 -SC_TILE_PER_SUPERTILE_H9 = 67 -SC_TILE_PER_SUPERTILE_H10 = 68 -SC_TILE_PER_SUPERTILE_H11 = 69 -SC_TILE_PER_SUPERTILE_H12 = 70 -SC_TILE_PER_SUPERTILE_H13 = 71 -SC_TILE_PER_SUPERTILE_H14 = 72 -SC_TILE_PER_SUPERTILE_H15 = 73 -SC_TILE_PER_SUPERTILE_H16 = 74 -SC_TILE_PICKED_H1 = 75 -SC_TILE_PICKED_H2 = 76 -SC_TILE_PICKED_H3 = 77 -SC_TILE_PICKED_H4 = 78 -SC_QZ0_TILE_COUNT = 79 -SC_QZ1_TILE_COUNT = 80 -SC_QZ2_TILE_COUNT = 81 -SC_QZ3_TILE_COUNT = 82 -SC_QZ0_TILE_COVERED_COUNT = 83 -SC_QZ1_TILE_COVERED_COUNT = 84 -SC_QZ2_TILE_COVERED_COUNT = 85 -SC_QZ3_TILE_COVERED_COUNT = 86 -SC_QZ0_TILE_NOT_COVERED_COUNT = 87 -SC_QZ1_TILE_NOT_COVERED_COUNT = 88 -SC_QZ2_TILE_NOT_COVERED_COUNT = 89 -SC_QZ3_TILE_NOT_COVERED_COUNT = 90 -SC_QZ0_QUAD_PER_TILE_H0 = 91 -SC_QZ0_QUAD_PER_TILE_H1 = 92 -SC_QZ0_QUAD_PER_TILE_H2 = 93 -SC_QZ0_QUAD_PER_TILE_H3 = 94 -SC_QZ0_QUAD_PER_TILE_H4 = 95 -SC_QZ0_QUAD_PER_TILE_H5 = 96 -SC_QZ0_QUAD_PER_TILE_H6 = 97 -SC_QZ0_QUAD_PER_TILE_H7 = 98 -SC_QZ0_QUAD_PER_TILE_H8 = 99 -SC_QZ0_QUAD_PER_TILE_H9 = 100 -SC_QZ0_QUAD_PER_TILE_H10 = 101 -SC_QZ0_QUAD_PER_TILE_H11 = 102 -SC_QZ0_QUAD_PER_TILE_H12 = 103 -SC_QZ0_QUAD_PER_TILE_H13 = 104 -SC_QZ0_QUAD_PER_TILE_H14 = 105 -SC_QZ0_QUAD_PER_TILE_H15 = 106 -SC_QZ0_QUAD_PER_TILE_H16 = 107 -SC_QZ1_QUAD_PER_TILE_H0 = 108 -SC_QZ1_QUAD_PER_TILE_H1 = 109 -SC_QZ1_QUAD_PER_TILE_H2 = 110 -SC_QZ1_QUAD_PER_TILE_H3 = 111 -SC_QZ1_QUAD_PER_TILE_H4 = 112 -SC_QZ1_QUAD_PER_TILE_H5 = 113 -SC_QZ1_QUAD_PER_TILE_H6 = 114 -SC_QZ1_QUAD_PER_TILE_H7 = 115 -SC_QZ1_QUAD_PER_TILE_H8 = 116 -SC_QZ1_QUAD_PER_TILE_H9 = 117 -SC_QZ1_QUAD_PER_TILE_H10 = 118 -SC_QZ1_QUAD_PER_TILE_H11 = 119 -SC_QZ1_QUAD_PER_TILE_H12 = 120 -SC_QZ1_QUAD_PER_TILE_H13 = 121 -SC_QZ1_QUAD_PER_TILE_H14 = 122 -SC_QZ1_QUAD_PER_TILE_H15 = 123 -SC_QZ1_QUAD_PER_TILE_H16 = 124 -SC_QZ2_QUAD_PER_TILE_H0 = 125 -SC_QZ2_QUAD_PER_TILE_H1 = 126 -SC_QZ2_QUAD_PER_TILE_H2 = 127 -SC_QZ2_QUAD_PER_TILE_H3 = 128 -SC_QZ2_QUAD_PER_TILE_H4 = 129 -SC_QZ2_QUAD_PER_TILE_H5 = 130 -SC_QZ2_QUAD_PER_TILE_H6 = 131 -SC_QZ2_QUAD_PER_TILE_H7 = 132 -SC_QZ2_QUAD_PER_TILE_H8 = 133 -SC_QZ2_QUAD_PER_TILE_H9 = 134 -SC_QZ2_QUAD_PER_TILE_H10 = 135 -SC_QZ2_QUAD_PER_TILE_H11 = 136 -SC_QZ2_QUAD_PER_TILE_H12 = 137 -SC_QZ2_QUAD_PER_TILE_H13 = 138 -SC_QZ2_QUAD_PER_TILE_H14 = 139 -SC_QZ2_QUAD_PER_TILE_H15 = 140 -SC_QZ2_QUAD_PER_TILE_H16 = 141 -SC_QZ3_QUAD_PER_TILE_H0 = 142 -SC_QZ3_QUAD_PER_TILE_H1 = 143 -SC_QZ3_QUAD_PER_TILE_H2 = 144 -SC_QZ3_QUAD_PER_TILE_H3 = 145 -SC_QZ3_QUAD_PER_TILE_H4 = 146 -SC_QZ3_QUAD_PER_TILE_H5 = 147 -SC_QZ3_QUAD_PER_TILE_H6 = 148 -SC_QZ3_QUAD_PER_TILE_H7 = 149 -SC_QZ3_QUAD_PER_TILE_H8 = 150 -SC_QZ3_QUAD_PER_TILE_H9 = 151 -SC_QZ3_QUAD_PER_TILE_H10 = 152 -SC_QZ3_QUAD_PER_TILE_H11 = 153 -SC_QZ3_QUAD_PER_TILE_H12 = 154 -SC_QZ3_QUAD_PER_TILE_H13 = 155 -SC_QZ3_QUAD_PER_TILE_H14 = 156 -SC_QZ3_QUAD_PER_TILE_H15 = 157 -SC_QZ3_QUAD_PER_TILE_H16 = 158 -SC_QZ0_QUAD_COUNT = 159 -SC_QZ1_QUAD_COUNT = 160 -SC_QZ2_QUAD_COUNT = 161 -SC_QZ3_QUAD_COUNT = 162 -SC_P0_HIZ_TILE_COUNT = 163 -SC_P1_HIZ_TILE_COUNT = 164 -SC_P2_HIZ_TILE_COUNT = 165 -SC_P3_HIZ_TILE_COUNT = 166 -SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 -SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 -SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 -SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 -SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 -SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 -SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 -SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 -SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 -SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 -SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 -SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 -SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 -SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 -SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 -SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 -SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 -SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 -SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 -SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 -SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 -SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 -SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 -SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 -SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 -SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 -SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 -SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 -SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 -SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 -SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 -SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 -SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 -SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 -SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 -SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 -SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 -SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 -SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 -SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 -SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 -SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 -SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 -SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 -SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 -SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 -SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 -SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 -SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 -SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 -SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 -SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 -SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 -SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 -SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 -SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 -SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 -SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 -SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 -SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 -SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 -SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 -SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 -SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 -SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 -SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 -SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 -SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 -SC_P0_HIZ_QUAD_COUNT = 235 -SC_P1_HIZ_QUAD_COUNT = 236 -SC_P2_HIZ_QUAD_COUNT = 237 -SC_P3_HIZ_QUAD_COUNT = 238 -SC_P0_DETAIL_QUAD_COUNT = 239 -SC_P1_DETAIL_QUAD_COUNT = 240 -SC_P2_DETAIL_QUAD_COUNT = 241 -SC_P3_DETAIL_QUAD_COUNT = 242 -SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 -SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 -SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 -SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 -SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 -SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 -SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 -SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 -SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 -SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 -SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 -SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 -SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 -SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 -SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 -SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 -SC_EARLYZ_QUAD_COUNT = 259 -SC_EARLYZ_QUAD_WITH_1_PIX = 260 -SC_EARLYZ_QUAD_WITH_2_PIX = 261 -SC_EARLYZ_QUAD_WITH_3_PIX = 262 -SC_EARLYZ_QUAD_WITH_4_PIX = 263 -SC_PKR_QUAD_PER_ROW_H1 = 264 -SC_PKR_QUAD_PER_ROW_H2 = 265 -SC_PKR_4X2_QUAD_SPLIT = 266 -SC_PKR_4X2_FILL_QUAD = 267 -SC_PKR_END_OF_VECTOR = 268 -SC_PKR_CONTROL_XFER = 269 -SC_PKR_DBHANG_FORCE_EOV = 270 -SC_REG_SCLK_BUSY = 271 -SC_GRP0_DYN_SCLK_BUSY = 272 -SC_GRP1_DYN_SCLK_BUSY = 273 -SC_GRP2_DYN_SCLK_BUSY = 274 -SC_GRP3_DYN_SCLK_BUSY = 275 -SC_GRP4_DYN_SCLK_BUSY = 276 -SC_PA0_SC_DATA_FIFO_RD = 277 -SC_PA0_SC_DATA_FIFO_WE = 278 -SC_PA1_SC_DATA_FIFO_RD = 279 -SC_PA1_SC_DATA_FIFO_WE = 280 -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 -SC_PS_ARB_STALLED_FROM_BELOW = 284 -SC_PS_ARB_STARVED_FROM_ABOVE = 285 -SC_PS_ARB_SC_BUSY = 286 -SC_PS_ARB_PA_SC_BUSY = 287 -SC_PA2_SC_DATA_FIFO_RD = 288 -SC_PA2_SC_DATA_FIFO_WE = 289 -SC_PA3_SC_DATA_FIFO_RD = 290 -SC_PA3_SC_DATA_FIFO_WE = 291 -SC_PA_SC_DEALLOC_0_0_WE = 292 -SC_PA_SC_DEALLOC_0_1_WE = 293 -SC_PA_SC_DEALLOC_1_0_WE = 294 -SC_PA_SC_DEALLOC_1_1_WE = 295 -SC_PA_SC_DEALLOC_2_0_WE = 296 -SC_PA_SC_DEALLOC_2_1_WE = 297 -SC_PA_SC_DEALLOC_3_0_WE = 298 -SC_PA_SC_DEALLOC_3_1_WE = 299 -SC_PA0_SC_EOP_WE = 300 -SC_PA0_SC_EOPG_WE = 301 -SC_PA0_SC_EVENT_WE = 302 -SC_PA1_SC_EOP_WE = 303 -SC_PA1_SC_EOPG_WE = 304 -SC_PA1_SC_EVENT_WE = 305 -SC_PA2_SC_EOP_WE = 306 -SC_PA2_SC_EOPG_WE = 307 -SC_PA2_SC_EVENT_WE = 308 -SC_PA3_SC_EOP_WE = 309 -SC_PA3_SC_EOPG_WE = 310 -SC_PA3_SC_EVENT_WE = 311 -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 -SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 -SC_PS_ARB_EOP_POP_SYNC_POP = 315 -SC_PS_ARB_EVENT_SYNC_POP = 316 -SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 317 -SC_PA0_SC_FPOV_WE = 318 -SC_PA1_SC_FPOV_WE = 319 -SC_PA2_SC_FPOV_WE = 320 -SC_PA3_SC_FPOV_WE = 321 -SC_PA0_SC_LPOV_WE = 322 -SC_PA1_SC_LPOV_WE = 323 -SC_PA2_SC_LPOV_WE = 324 -SC_PA3_SC_LPOV_WE = 325 -SC_SC_SPI_DEALLOC_0_0 = 326 -SC_SC_SPI_DEALLOC_0_1 = 327 -SC_SC_SPI_DEALLOC_0_2 = 328 -SC_SC_SPI_DEALLOC_1_0 = 329 -SC_SC_SPI_DEALLOC_1_1 = 330 -SC_SC_SPI_DEALLOC_1_2 = 331 -SC_SC_SPI_DEALLOC_2_0 = 332 -SC_SC_SPI_DEALLOC_2_1 = 333 -SC_SC_SPI_DEALLOC_2_2 = 334 -SC_SC_SPI_DEALLOC_3_0 = 335 -SC_SC_SPI_DEALLOC_3_1 = 336 -SC_SC_SPI_DEALLOC_3_2 = 337 -SC_SC_SPI_FPOV_0 = 338 -SC_SC_SPI_FPOV_1 = 339 -SC_SC_SPI_FPOV_2 = 340 -SC_SC_SPI_FPOV_3 = 341 -SC_SC_SPI_EVENT = 342 -SC_PS_TS_EVENT_FIFO_PUSH = 343 -SC_PS_TS_EVENT_FIFO_POP = 344 -SC_PS_CTX_DONE_FIFO_PUSH = 345 -SC_PS_CTX_DONE_FIFO_POP = 346 -SC_MULTICYCLE_BUBBLE_FREEZE = 347 -SC_EOP_SYNC_WINDOW = 348 -SC_PA0_SC_NULL_WE = 349 -SC_PA0_SC_NULL_DEALLOC_WE = 350 -SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 -SC_PA0_SC_DATA_FIFO_EOP_RD = 352 -SC_PA0_SC_DEALLOC_0_RD = 353 -SC_PA0_SC_DEALLOC_1_RD = 354 -SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 -SC_PA1_SC_DATA_FIFO_EOP_RD = 356 -SC_PA1_SC_DEALLOC_0_RD = 357 -SC_PA1_SC_DEALLOC_1_RD = 358 -SC_PA1_SC_NULL_WE = 359 -SC_PA1_SC_NULL_DEALLOC_WE = 360 -SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 -SC_PA2_SC_DATA_FIFO_EOP_RD = 362 -SC_PA2_SC_DEALLOC_0_RD = 363 -SC_PA2_SC_DEALLOC_1_RD = 364 -SC_PA2_SC_NULL_WE = 365 -SC_PA2_SC_NULL_DEALLOC_WE = 366 -SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 -SC_PA3_SC_DATA_FIFO_EOP_RD = 368 -SC_PA3_SC_DEALLOC_0_RD = 369 -SC_PA3_SC_DEALLOC_1_RD = 370 -SC_PA3_SC_NULL_WE = 371 -SC_PA3_SC_NULL_DEALLOC_WE = 372 -SC_PS_PA0_SC_FIFO_EMPTY = 373 -SC_PS_PA0_SC_FIFO_FULL = 374 -SC_RESERVED_0 = 375 -SC_PS_PA1_SC_FIFO_EMPTY = 376 -SC_PS_PA1_SC_FIFO_FULL = 377 -SC_RESERVED_1 = 378 -SC_PS_PA2_SC_FIFO_EMPTY = 379 -SC_PS_PA2_SC_FIFO_FULL = 380 -SC_RESERVED_2 = 381 -SC_PS_PA3_SC_FIFO_EMPTY = 382 -SC_PS_PA3_SC_FIFO_FULL = 383 -SC_RESERVED_3 = 384 -SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 -SC_BUSY_CNT_NOT_ZERO = 386 -SC_BM_BUSY = 387 -SC_BACKEND_BUSY = 388 -SC_SCF_SCB_INTERFACE_BUSY = 389 -SC_SCB_BUSY = 390 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 -SC_PBB_BIN_HIST_NUM_PRIMS = 393 -SC_PBB_BATCH_HIST_NUM_PRIMS = 394 -SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 -SC_PBB_BUSY = 403 -SC_PBB_BUSY_AND_NO_SENDS = 404 -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 -SC_PBB_NUM_BINS = 406 -SC_PBB_END_OF_BIN = 407 -SC_PBB_END_OF_BATCH = 408 -SC_PBB_PRIMBIN_PROCESSED = 409 -SC_PBB_PRIM_ADDED_TO_BATCH = 410 -SC_PBB_NONBINNED_PRIM = 411 -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 -SC_POPS_INTRA_WAVE_OVERLAPS = 423 -SC_POPS_FORCE_EOV = 424 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 -SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 -SC_FULL_FULL_QUAD = 428 -SC_FULL_HALF_QUAD = 429 -SC_FULL_QTR_QUAD = 430 -SC_HALF_FULL_QUAD = 431 -SC_HALF_HALF_QUAD = 432 -SC_HALF_QTR_QUAD = 433 -SC_QTR_FULL_QUAD = 434 -SC_QTR_HALF_QUAD = 435 -SC_QTR_QTR_QUAD = 436 -SC_GRP5_DYN_SCLK_BUSY = 437 -SC_GRP6_DYN_SCLK_BUSY = 438 -SC_GRP7_DYN_SCLK_BUSY = 439 -SC_GRP8_DYN_SCLK_BUSY = 440 -SC_GRP9_DYN_SCLK_BUSY = 441 -SC_PS_TO_BE_SCLK_GATE_STALL = 442 -SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 -SC_PK_BUSY = 444 -SC_PK_MAX_DEALLOC_FORCE_EOV = 445 -SC_PK_DEALLOC_WAVE_BREAK = 446 -SC_SPI_SEND = 447 -SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 -SC_SPI_CREDIT_AT_MAX = 449 -SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 -SC_BCI_SEND = 451 -SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 -SC_BCI_CREDIT_AT_MAX = 453 -SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 -SC_SPIBC_FULL_FREEZE = 455 -SC_PW_BM_PASS_EMPTY_PRIM = 456 -SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 -SC_DB0_TILE_INTERFACE_BUSY = 475 -SC_DB0_TILE_INTERFACE_SEND = 476 -SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 -SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 -SC_DB0_TILE_INTERFACE_SEND_SOP = 479 -SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 -SC_DB1_TILE_INTERFACE_BUSY = 483 -SC_DB1_TILE_INTERFACE_SEND = 484 -SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 -SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 -SC_DB1_TILE_INTERFACE_SEND_SOP = 487 -SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 -SC_BACKEND_PRIM_FIFO_FULL = 491 -SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 -SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 -SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 -SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 -SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 -SC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SePairXsel' -SePairXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 -SePairXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairYsel' -SePairYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 -SePairYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairMap' -SePairMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', - 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', - 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', - 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', -} -RASTER_CONFIG_SE_PAIR_MAP_0 = 0 -RASTER_CONFIG_SE_PAIR_MAP_1 = 1 -RASTER_CONFIG_SE_PAIR_MAP_2 = 2 -RASTER_CONFIG_SE_PAIR_MAP_3 = 3 -SePairMap = ctypes.c_uint32 # enum - -# values for enumeration 'SeXsel' -SeXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 -SeXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeYsel' -SeYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 -SeYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeMap' -SeMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_MAP_0', - 1: 'RASTER_CONFIG_SE_MAP_1', - 2: 'RASTER_CONFIG_SE_MAP_2', - 3: 'RASTER_CONFIG_SE_MAP_3', -} -RASTER_CONFIG_SE_MAP_0 = 0 -RASTER_CONFIG_SE_MAP_1 = 1 -RASTER_CONFIG_SE_MAP_2 = 2 -RASTER_CONFIG_SE_MAP_3 = 3 -SeMap = ctypes.c_uint32 # enum - -# values for enumeration 'ScXsel' -ScXsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 -ScXsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScYsel' -ScYsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 -ScYsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScMap' -ScMap__enumvalues = { - 0: 'RASTER_CONFIG_SC_MAP_0', - 1: 'RASTER_CONFIG_SC_MAP_1', - 2: 'RASTER_CONFIG_SC_MAP_2', - 3: 'RASTER_CONFIG_SC_MAP_3', -} -RASTER_CONFIG_SC_MAP_0 = 0 -RASTER_CONFIG_SC_MAP_1 = 1 -RASTER_CONFIG_SC_MAP_2 = 2 -RASTER_CONFIG_SC_MAP_3 = 3 -ScMap = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel2' -PkrXsel2__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL2_0', - 1: 'RASTER_CONFIG_PKR_XSEL2_1', - 2: 'RASTER_CONFIG_PKR_XSEL2_2', - 3: 'RASTER_CONFIG_PKR_XSEL2_3', -} -RASTER_CONFIG_PKR_XSEL2_0 = 0 -RASTER_CONFIG_PKR_XSEL2_1 = 1 -RASTER_CONFIG_PKR_XSEL2_2 = 2 -RASTER_CONFIG_PKR_XSEL2_3 = 3 -PkrXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel' -PkrXsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL_0', - 1: 'RASTER_CONFIG_PKR_XSEL_1', - 2: 'RASTER_CONFIG_PKR_XSEL_2', - 3: 'RASTER_CONFIG_PKR_XSEL_3', -} -RASTER_CONFIG_PKR_XSEL_0 = 0 -RASTER_CONFIG_PKR_XSEL_1 = 1 -RASTER_CONFIG_PKR_XSEL_2 = 2 -RASTER_CONFIG_PKR_XSEL_3 = 3 -PkrXsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrYsel' -PkrYsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_YSEL_0', - 1: 'RASTER_CONFIG_PKR_YSEL_1', - 2: 'RASTER_CONFIG_PKR_YSEL_2', - 3: 'RASTER_CONFIG_PKR_YSEL_3', -} -RASTER_CONFIG_PKR_YSEL_0 = 0 -RASTER_CONFIG_PKR_YSEL_1 = 1 -RASTER_CONFIG_PKR_YSEL_2 = 2 -RASTER_CONFIG_PKR_YSEL_3 = 3 -PkrYsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrMap' -PkrMap__enumvalues = { - 0: 'RASTER_CONFIG_PKR_MAP_0', - 1: 'RASTER_CONFIG_PKR_MAP_1', - 2: 'RASTER_CONFIG_PKR_MAP_2', - 3: 'RASTER_CONFIG_PKR_MAP_3', -} -RASTER_CONFIG_PKR_MAP_0 = 0 -RASTER_CONFIG_PKR_MAP_1 = 1 -RASTER_CONFIG_PKR_MAP_2 = 2 -RASTER_CONFIG_PKR_MAP_3 = 3 -PkrMap = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel' -RbXsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL_0', - 1: 'RASTER_CONFIG_RB_XSEL_1', -} -RASTER_CONFIG_RB_XSEL_0 = 0 -RASTER_CONFIG_RB_XSEL_1 = 1 -RbXsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbYsel' -RbYsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_YSEL_0', - 1: 'RASTER_CONFIG_RB_YSEL_1', -} -RASTER_CONFIG_RB_YSEL_0 = 0 -RASTER_CONFIG_RB_YSEL_1 = 1 -RbYsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel2' -RbXsel2__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL2_0', - 1: 'RASTER_CONFIG_RB_XSEL2_1', - 2: 'RASTER_CONFIG_RB_XSEL2_2', - 3: 'RASTER_CONFIG_RB_XSEL2_3', -} -RASTER_CONFIG_RB_XSEL2_0 = 0 -RASTER_CONFIG_RB_XSEL2_1 = 1 -RASTER_CONFIG_RB_XSEL2_2 = 2 -RASTER_CONFIG_RB_XSEL2_3 = 3 -RbXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'RbMap' -RbMap__enumvalues = { - 0: 'RASTER_CONFIG_RB_MAP_0', - 1: 'RASTER_CONFIG_RB_MAP_1', - 2: 'RASTER_CONFIG_RB_MAP_2', - 3: 'RASTER_CONFIG_RB_MAP_3', -} -RASTER_CONFIG_RB_MAP_0 = 0 -RASTER_CONFIG_RB_MAP_1 = 1 -RASTER_CONFIG_RB_MAP_2 = 2 -RASTER_CONFIG_RB_MAP_3 = 3 -RbMap = ctypes.c_uint32 # enum - -# values for enumeration 'BinningMode' -BinningMode__enumvalues = { - 0: 'BINNING_ALLOWED', - 1: 'FORCE_BINNING_ON', - 2: 'DISABLE_BINNING_USE_NEW_SC', - 3: 'DISABLE_BINNING_USE_LEGACY_SC', -} -BINNING_ALLOWED = 0 -FORCE_BINNING_ON = 1 -DISABLE_BINNING_USE_NEW_SC = 2 -DISABLE_BINNING_USE_LEGACY_SC = 3 -BinningMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinSizeExtend' -BinSizeExtend__enumvalues = { - 0: 'BIN_SIZE_32_PIXELS', - 1: 'BIN_SIZE_64_PIXELS', - 2: 'BIN_SIZE_128_PIXELS', - 3: 'BIN_SIZE_256_PIXELS', - 4: 'BIN_SIZE_512_PIXELS', -} -BIN_SIZE_32_PIXELS = 0 -BIN_SIZE_64_PIXELS = 1 -BIN_SIZE_128_PIXELS = 2 -BIN_SIZE_256_PIXELS = 3 -BIN_SIZE_512_PIXELS = 4 -BinSizeExtend = ctypes.c_uint32 # enum - -# values for enumeration 'BinMapMode' -BinMapMode__enumvalues = { - 0: 'BIN_MAP_MODE_NONE', - 1: 'BIN_MAP_MODE_RTA_INDEX', - 2: 'BIN_MAP_MODE_POPS', -} -BIN_MAP_MODE_NONE = 0 -BIN_MAP_MODE_RTA_INDEX = 1 -BIN_MAP_MODE_POPS = 2 -BinMapMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinEventCntl' -BinEventCntl__enumvalues = { - 0: 'BINNER_BREAK_BATCH', - 1: 'BINNER_PIPELINE', - 2: 'BINNER_DROP', - 3: 'BINNER_DROP_ASSERT', -} -BINNER_BREAK_BATCH = 0 -BINNER_PIPELINE = 1 -BINNER_DROP = 2 -BINNER_DROP_ASSERT = 3 -BinEventCntl = ctypes.c_uint32 # enum - -# values for enumeration 'CovToShaderSel' -CovToShaderSel__enumvalues = { - 0: 'INPUT_COVERAGE', - 1: 'INPUT_INNER_COVERAGE', - 2: 'INPUT_DEPTH_COVERAGE', - 3: 'RAW', -} -INPUT_COVERAGE = 0 -INPUT_INNER_COVERAGE = 1 -INPUT_DEPTH_COVERAGE = 2 -RAW = 3 -CovToShaderSel = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMode' -ScUncertaintyRegionMode__enumvalues = { - 0: 'SC_HALF_LSB', - 1: 'SC_LSB_ONE_SIDED', - 2: 'SC_LSB_TWO_SIDED', -} -SC_HALF_LSB = 0 -SC_LSB_ONE_SIDED = 1 -SC_LSB_TWO_SIDED = 2 -ScUncertaintyRegionMode = ctypes.c_uint32 # enum - -# values for enumeration 'RMIPerfSel' -RMIPerfSel__enumvalues = { - 0: 'RMI_PERF_SEL_NONE', - 1: 'RMI_PERF_SEL_BUSY', - 2: 'RMI_PERF_SEL_REG_CLK_VLD', - 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', - 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', - 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 6: 'RMI_PERF_SEL_PERF_WINDOW', - 7: 'RMI_PERF_SEL_EVENT_SEND', - 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', - 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', - 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', - 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', - 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', - 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', - 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', - 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', - 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', - 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', - 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', - 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', - 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', - 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', - 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', - 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', - 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', - 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', - 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', - 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', - 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', - 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', - 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', - 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', - 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', - 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', - 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', - 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', - 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', - 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', - 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', - 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', - 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', - 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', - 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', - 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', - 44: 'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT', - 45: 'RMI_PERF_SEL_UTCL1_REQUEST', - 46: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 47: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 48: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', - 49: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 50: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 51: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 52: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', - 53: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', - 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', - 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 64: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', - 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 67: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 80: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 81: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 83: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', - 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 91: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 99: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 100: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 103: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 116: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 117: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', - 118: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', - 119: 'RMI_PERF_SEL_RB_RMI_WR_IDLE', - 120: 'RMI_PERF_SEL_RB_RMI_WR_STARVE', - 121: 'RMI_PERF_SEL_RB_RMI_WR_STALL', - 122: 'RMI_PERF_SEL_RB_RMI_WR_BUSY', - 123: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', - 124: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', - 125: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', - 126: 'RMI_PERF_SEL_RB_RMI_RD_IDLE', - 127: 'RMI_PERF_SEL_RB_RMI_RD_STARVE', - 128: 'RMI_PERF_SEL_RB_RMI_RD_STALL', - 129: 'RMI_PERF_SEL_RB_RMI_RD_BUSY', - 130: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', - 131: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', - 132: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', - 133: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 134: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 135: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 136: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 137: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 138: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 139: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 140: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 141: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 142: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 143: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 144: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', - 145: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 146: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 147: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 148: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 149: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 150: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 151: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 152: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 153: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 154: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', - 155: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', - 156: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', - 157: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', - 158: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', - 159: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 160: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 161: 'RMI_PERF_SEL_UTCL1_BUSY', - 162: 'RMI_PERF_SEL_RMI_UTC_REQ', - 163: 'RMI_PERF_SEL_RMI_UTC_BUSY', - 164: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', - 165: 'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2', - 166: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', - 167: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', - 168: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', - 169: 'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS', - 170: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', - 171: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', - 172: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', - 173: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', - 174: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', - 175: 'RMI_PERF_SEL_XNACK_FIFO_FULL', - 176: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', - 177: 'RMI_PERF_SEL_LAT_FIFO_FULL', - 178: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', - 179: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 180: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', - 181: 'RMI_PERF_SEL_PRT_FIFO_REQ', - 182: 'RMI_PERF_SEL_PRT_FIFO_BUSY', - 183: 'RMI_PERF_SEL_TCIW_REQ', - 184: 'RMI_PERF_SEL_TCIW_BUSY', - 185: 'RMI_PERF_SEL_SKID_FIFO_REQ', - 186: 'RMI_PERF_SEL_SKID_FIFO_BUSY', - 187: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', - 188: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', - 189: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', - 190: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', - 191: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', - 192: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', - 193: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', - 194: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', - 195: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 196: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 197: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 198: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 199: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', - 200: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', - 201: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', - 202: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', - 203: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', - 204: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', - 205: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', - 206: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', - 207: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', - 208: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', - 209: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', - 210: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', - 211: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', - 212: 'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC', - 213: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', - 214: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', - 215: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', - 216: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', - 217: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', - 218: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', - 219: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', - 220: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', - 221: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', - 222: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', - 223: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', - 224: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', - 225: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', - 226: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', - 227: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', - 228: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', - 229: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', - 230: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', - 231: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', - 232: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', - 233: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', - 234: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', - 235: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', - 236: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', - 237: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', - 238: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', - 239: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', - 240: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', - 241: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', - 242: 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 243: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 244: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 245: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 246: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 247: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 248: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 249: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 250: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 251: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 252: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 253: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', - 254: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', - 255: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', - 256: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', -} -RMI_PERF_SEL_NONE = 0 -RMI_PERF_SEL_BUSY = 1 -RMI_PERF_SEL_REG_CLK_VLD = 2 -RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 -RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 -RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 -RMI_PERF_SEL_PERF_WINDOW = 6 -RMI_PERF_SEL_EVENT_SEND = 7 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 -RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 -RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 -RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 44 -RMI_PERF_SEL_UTCL1_REQUEST = 45 -RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 46 -RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 47 -RMI_PERF_SEL_UTCL1_LFIFO_FULL = 48 -RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 49 -RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 50 -RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 51 -RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 52 -RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 53 -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 54 -RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 55 -RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 56 -RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 57 -RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 58 -RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 59 -RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 60 -RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 61 -RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 62 -RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 63 -RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 64 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 65 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 66 -RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 67 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 68 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 69 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 70 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 71 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 72 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 73 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 74 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 75 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 76 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 77 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 78 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 79 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 80 -RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 81 -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 82 -RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 83 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 84 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 85 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 86 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 87 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 88 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 89 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 90 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 91 -RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 92 -RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 93 -RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 94 -RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 95 -RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 96 -RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 97 -RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 98 -RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 99 -RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 100 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 101 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 102 -RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 103 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 104 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 105 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 106 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 107 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 108 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 109 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 110 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 111 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 112 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 113 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 114 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 115 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 116 -RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 117 -RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 118 -RMI_PERF_SEL_RB_RMI_WR_IDLE = 119 -RMI_PERF_SEL_RB_RMI_WR_STARVE = 120 -RMI_PERF_SEL_RB_RMI_WR_STALL = 121 -RMI_PERF_SEL_RB_RMI_WR_BUSY = 122 -RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 123 -RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 124 -RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 125 -RMI_PERF_SEL_RB_RMI_RD_IDLE = 126 -RMI_PERF_SEL_RB_RMI_RD_STARVE = 127 -RMI_PERF_SEL_RB_RMI_RD_STALL = 128 -RMI_PERF_SEL_RB_RMI_RD_BUSY = 129 -RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 130 -RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 131 -RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 132 -RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 133 -RMI_PERF_SEL_RMI_TC_REQ_BUSY = 134 -RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 135 -RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 136 -RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 137 -RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 138 -RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 139 -RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 140 -RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 141 -RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 142 -RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 143 -RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 144 -RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 145 -RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 146 -RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 147 -RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 148 -RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 149 -RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 150 -RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 151 -RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 152 -RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 153 -RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 154 -RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 155 -RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 156 -RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 157 -RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 158 -RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 159 -RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 160 -RMI_PERF_SEL_UTCL1_BUSY = 161 -RMI_PERF_SEL_RMI_UTC_REQ = 162 -RMI_PERF_SEL_RMI_UTC_BUSY = 163 -RMI_PERF_SEL_UTCL1_UTCL2_REQ = 164 -RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 165 -RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 166 -RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 167 -RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 168 -RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 169 -RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 170 -RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 171 -RMI_PERF_SEL_LAT_FIFO_NUM_USED = 172 -RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 173 -RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 174 -RMI_PERF_SEL_XNACK_FIFO_FULL = 175 -RMI_PERF_SEL_XNACK_FIFO_BUSY = 176 -RMI_PERF_SEL_LAT_FIFO_FULL = 177 -RMI_PERF_SEL_SKID_FIFO_DEPTH = 178 -RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 179 -RMI_PERF_SEL_PRT_FIFO_NUM_USED = 180 -RMI_PERF_SEL_PRT_FIFO_REQ = 181 -RMI_PERF_SEL_PRT_FIFO_BUSY = 182 -RMI_PERF_SEL_TCIW_REQ = 183 -RMI_PERF_SEL_TCIW_BUSY = 184 -RMI_PERF_SEL_SKID_FIFO_REQ = 185 -RMI_PERF_SEL_SKID_FIFO_BUSY = 186 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 187 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 188 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 189 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 190 -RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 191 -RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 192 -RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 193 -RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 194 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 195 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 196 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 197 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 198 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 199 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 200 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 201 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 202 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 203 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 204 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 205 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 206 -RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 207 -RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 208 -RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 209 -RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 210 -RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 211 -RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 212 -RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 213 -RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 214 -RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 215 -RMI_PERF_SEL_UTC_POP_RTS_RTR = 216 -RMI_PERF_SEL_UTC_POP_RTSB_RTR = 217 -RMI_PERF_SEL_UTC_POP_RTS_RTRB = 218 -RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 219 -RMI_PERF_SEL_POP_XNACK_RTS_RTR = 220 -RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 221 -RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 222 -RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 223 -RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 224 -RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 225 -RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 226 -RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 227 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 228 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 229 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 230 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 231 -RMI_PERF_SEL_SKID_FIFO_IN_RTS = 232 -RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 233 -RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 234 -RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 235 -RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 236 -RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 237 -RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 238 -RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 239 -RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 240 -RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 241 -RMI_PERF_SEL_REORDER_FIFO_REQ = 242 -RMI_PERF_SEL_REORDER_FIFO_BUSY = 243 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 244 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 245 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 246 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 247 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 248 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 249 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 250 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 251 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 252 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 253 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 254 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 255 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 256 -RMIPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'GCRPerfSel' -GCRPerfSel__enumvalues = { - 0: 'GCR_PERF_SEL_NONE', - 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', - 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', - 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', - 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 33: 'GCR_PERF_SEL_CPG_ALL_REQ', - 34: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', - 35: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 36: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 37: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 38: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 39: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', - 40: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 41: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 42: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 43: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 44: 'GCR_PERF_SEL_CPG_METADATA_REQ', - 45: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', - 46: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 47: 'GCR_PERF_SEL_CPG_TCP_REQ', - 48: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', - 49: 'GCR_PERF_SEL_CPC_ALL_REQ', - 50: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', - 51: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 52: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 53: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 54: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 55: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', - 56: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 57: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 58: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 59: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 60: 'GCR_PERF_SEL_CPC_METADATA_REQ', - 61: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', - 62: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 63: 'GCR_PERF_SEL_CPC_TCP_REQ', - 64: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 65: 'GCR_PERF_SEL_CPF_ALL_REQ', - 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', - 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', - 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', - 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', - 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 79: 'GCR_PERF_SEL_CPF_TCP_REQ', - 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 81: 'GCR_PERF_SEL_VIRT_REQ', - 82: 'GCR_PERF_SEL_PHY_REQ', - 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 85: 'GCR_PERF_SEL_ALL_REQ', - 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 89: 'GCR_PERF_SEL_UTCL2_REQ', - 90: 'GCR_PERF_SEL_UTCL2_RET', - 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', -} -GCR_PERF_SEL_NONE = 0 -GCR_PERF_SEL_SDMA0_ALL_REQ = 1 -GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 -GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 -GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 -GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 -GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 -GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 -GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 -GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 -GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 -GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 -GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 -GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 -GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 -GCR_PERF_SEL_SDMA0_TCP_REQ = 15 -GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 -GCR_PERF_SEL_SDMA1_ALL_REQ = 17 -GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 -GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 -GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 -GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 -GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 -GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 -GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 -GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 -GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 -GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 -GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 -GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 -GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 -GCR_PERF_SEL_SDMA1_TCP_REQ = 31 -GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 -GCR_PERF_SEL_CPG_ALL_REQ = 33 -GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 34 -GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 35 -GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 36 -GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 37 -GCR_PERF_SEL_CPG_GL2_ALL_REQ = 38 -GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 39 -GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 40 -GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 41 -GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 42 -GCR_PERF_SEL_CPG_GL1_ALL_REQ = 43 -GCR_PERF_SEL_CPG_METADATA_REQ = 44 -GCR_PERF_SEL_CPG_SQC_DATA_REQ = 45 -GCR_PERF_SEL_CPG_SQC_INST_REQ = 46 -GCR_PERF_SEL_CPG_TCP_REQ = 47 -GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 48 -GCR_PERF_SEL_CPC_ALL_REQ = 49 -GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 50 -GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 51 -GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 52 -GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 53 -GCR_PERF_SEL_CPC_GL2_ALL_REQ = 54 -GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 55 -GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 56 -GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 57 -GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 58 -GCR_PERF_SEL_CPC_GL1_ALL_REQ = 59 -GCR_PERF_SEL_CPC_METADATA_REQ = 60 -GCR_PERF_SEL_CPC_SQC_DATA_REQ = 61 -GCR_PERF_SEL_CPC_SQC_INST_REQ = 62 -GCR_PERF_SEL_CPC_TCP_REQ = 63 -GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 64 -GCR_PERF_SEL_CPF_ALL_REQ = 65 -GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 -GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 -GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 -GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 -GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 -GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 -GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 -GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 -GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 -GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 -GCR_PERF_SEL_CPF_METADATA_REQ = 76 -GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 -GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 -GCR_PERF_SEL_CPF_TCP_REQ = 79 -GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 -GCR_PERF_SEL_VIRT_REQ = 81 -GCR_PERF_SEL_PHY_REQ = 82 -GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 -GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 -GCR_PERF_SEL_ALL_REQ = 85 -GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 -GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 -GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 -GCR_PERF_SEL_UTCL2_REQ = 89 -GCR_PERF_SEL_UTCL2_RET = 90 -GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 -GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 -GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 -GCRPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1PerfSel' -UTCL1PerfSel__enumvalues = { - 0: 'UTCL1_PERF_SEL_NONE', - 1: 'UTCL1_PERF_SEL_REQS', - 2: 'UTCL1_PERF_SEL_HITS', - 3: 'UTCL1_PERF_SEL_MISSES', - 4: 'UTCL1_PERF_SEL_BYPASS_REQS', - 5: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 6: 'UTCL1_PERF_SEL_NUM_SMALLK_PAGES', - 7: 'UTCL1_PERF_SEL_NUM_BIGK_PAGES', - 8: 'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS', - 9: 'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM', - 10: 'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS', - 11: 'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL', - 12: 'UTCL1_PERF_SEL_STALL_MH_CAM_FULL', - 13: 'UTCL1_PERF_SEL_NONRANGE_INV_REQS', - 14: 'UTCL1_PERF_SEL_RANGE_INV_REQS', -} -UTCL1_PERF_SEL_NONE = 0 -UTCL1_PERF_SEL_REQS = 1 -UTCL1_PERF_SEL_HITS = 2 -UTCL1_PERF_SEL_MISSES = 3 -UTCL1_PERF_SEL_BYPASS_REQS = 4 -UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 5 -UTCL1_PERF_SEL_NUM_SMALLK_PAGES = 6 -UTCL1_PERF_SEL_NUM_BIGK_PAGES = 7 -UTCL1_PERF_SEL_TOTAL_UTCL2_REQS = 8 -UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 9 -UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS = 10 -UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL = 11 -UTCL1_PERF_SEL_STALL_MH_CAM_FULL = 12 -UTCL1_PERF_SEL_NONRANGE_INV_REQS = 13 -UTCL1_PERF_SEL_RANGE_INV_REQS = 14 -UTCL1PerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERF_SEL' -SDMA_PERF_SEL__enumvalues = { - 0: 'SDMA_PERF_SEL_CYCLE', - 1: 'SDMA_PERF_SEL_IDLE', - 2: 'SDMA_PERF_SEL_REG_IDLE', - 3: 'SDMA_PERF_SEL_RB_EMPTY', - 4: 'SDMA_PERF_SEL_RB_FULL', - 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERF_SEL_RB_RPTR_WB', - 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERF_SEL_RB_CMD_FULL', - 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERF_SEL_IB_CMD_FULL', - 13: 'SDMA_PERF_SEL_EX_IDLE', - 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERF_SEL_MC_WR_IDLE', - 17: 'SDMA_PERF_SEL_MC_WR_COUNT', - 18: 'SDMA_PERF_SEL_MC_RD_IDLE', - 19: 'SDMA_PERF_SEL_MC_RD_COUNT', - 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'SDMA_PERF_SEL_SEM_IDLE', - 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'SDMA_PERF_SEL_INT_IDLE', - 31: 'SDMA_PERF_SEL_INT_REQ_STALL', - 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'SDMA_PERF_SEL_NUM_PACKET', - 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'SDMA_PERF_SEL_CE_WR_IDLE', - 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'SDMA_PERF_SEL_CE_IN_IDLE', - 43: 'SDMA_PERF_SEL_CE_DST_IDLE', - 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'SDMA_PERF_SEL_CE_INFO_FULL', - 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'SDMA_PERF_SEL_CE_RD_STALL', - 52: 'SDMA_PERF_SEL_CE_WR_STALL', - 53: 'SDMA_PERF_SEL_GFX_SELECT', - 54: 'SDMA_PERF_SEL_RLC0_SELECT', - 55: 'SDMA_PERF_SEL_RLC1_SELECT', - 56: 'SDMA_PERF_SEL_PAGE_SELECT', - 57: 'SDMA_PERF_SEL_CTX_CHANGE', - 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'SDMA_PERF_SEL_DOORBELL', - 61: 'SDMA_PERF_SEL_RD_BA_RTR', - 62: 'SDMA_PERF_SEL_WR_BA_RTR', - 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERF_SEL_UTCL2_FREE', - 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH', - 80: 'SDMA_PERF_SEL_GPUVM_INVREQ_LOW', - 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERF_SEL_META_REQ_SEND', - 94: 'SDMA_PERF_SEL_META_RTN_VLD', - 95: 'SDMA_PERF_SEL_TLBI_SEND', - 96: 'SDMA_PERF_SEL_TLBI_RTN', - 97: 'SDMA_PERF_SEL_GCR_SEND', - 98: 'SDMA_PERF_SEL_GCR_RTN', - 99: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', - 100: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', -} -SDMA_PERF_SEL_CYCLE = 0 -SDMA_PERF_SEL_IDLE = 1 -SDMA_PERF_SEL_REG_IDLE = 2 -SDMA_PERF_SEL_RB_EMPTY = 3 -SDMA_PERF_SEL_RB_FULL = 4 -SDMA_PERF_SEL_RB_WPTR_WRAP = 5 -SDMA_PERF_SEL_RB_RPTR_WRAP = 6 -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERF_SEL_RB_RPTR_WB = 8 -SDMA_PERF_SEL_RB_CMD_IDLE = 9 -SDMA_PERF_SEL_RB_CMD_FULL = 10 -SDMA_PERF_SEL_IB_CMD_IDLE = 11 -SDMA_PERF_SEL_IB_CMD_FULL = 12 -SDMA_PERF_SEL_EX_IDLE = 13 -SDMA_PERF_SEL_SRBM_REG_SEND = 14 -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERF_SEL_MC_WR_IDLE = 16 -SDMA_PERF_SEL_MC_WR_COUNT = 17 -SDMA_PERF_SEL_MC_RD_IDLE = 18 -SDMA_PERF_SEL_MC_RD_COUNT = 19 -SDMA_PERF_SEL_MC_RD_RET_STALL = 20 -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -SDMA_PERF_SEL_SEM_IDLE = 24 -SDMA_PERF_SEL_SEM_REQ_STALL = 25 -SDMA_PERF_SEL_SEM_REQ_COUNT = 26 -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -SDMA_PERF_SEL_SEM_RESP_FAIL = 28 -SDMA_PERF_SEL_SEM_RESP_PASS = 29 -SDMA_PERF_SEL_INT_IDLE = 30 -SDMA_PERF_SEL_INT_REQ_STALL = 31 -SDMA_PERF_SEL_INT_REQ_COUNT = 32 -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -SDMA_PERF_SEL_INT_RESP_RETRY = 34 -SDMA_PERF_SEL_NUM_PACKET = 35 -SDMA_PERF_SEL_CE_WREQ_IDLE = 37 -SDMA_PERF_SEL_CE_WR_IDLE = 38 -SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -SDMA_PERF_SEL_CE_RREQ_IDLE = 40 -SDMA_PERF_SEL_CE_OUT_IDLE = 41 -SDMA_PERF_SEL_CE_IN_IDLE = 42 -SDMA_PERF_SEL_CE_DST_IDLE = 43 -SDMA_PERF_SEL_CE_AFIFO_FULL = 46 -SDMA_PERF_SEL_CE_INFO_FULL = 49 -SDMA_PERF_SEL_CE_INFO1_FULL = 50 -SDMA_PERF_SEL_CE_RD_STALL = 51 -SDMA_PERF_SEL_CE_WR_STALL = 52 -SDMA_PERF_SEL_GFX_SELECT = 53 -SDMA_PERF_SEL_RLC0_SELECT = 54 -SDMA_PERF_SEL_RLC1_SELECT = 55 -SDMA_PERF_SEL_PAGE_SELECT = 56 -SDMA_PERF_SEL_CTX_CHANGE = 57 -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -SDMA_PERF_SEL_DOORBELL = 60 -SDMA_PERF_SEL_RD_BA_RTR = 61 -SDMA_PERF_SEL_WR_BA_RTR = 62 -SDMA_PERF_SEL_F32_L1_WR_VLD = 63 -SDMA_PERF_SEL_CE_L1_WR_VLD = 64 -SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERF_SEL_UTCL2_RET_ACK = 72 -SDMA_PERF_SEL_UTCL2_FREE = 73 -SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERF_SEL_GPUVM_INVREQ_HIGH = 79 -SDMA_PERF_SEL_GPUVM_INVREQ_LOW = 80 -SDMA_PERF_SEL_L1_WRL2_IDLE = 81 -SDMA_PERF_SEL_L1_RDL2_IDLE = 82 -SDMA_PERF_SEL_L1_WRMC_IDLE = 83 -SDMA_PERF_SEL_L1_RDMC_IDLE = 84 -SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERF_SEL_META_L2_REQ_SEND = 87 -SDMA_PERF_SEL_L2_META_RET_VLD = 88 -SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERF_SEL_META_REQ_SEND = 93 -SDMA_PERF_SEL_META_RTN_VLD = 94 -SDMA_PERF_SEL_TLBI_SEND = 95 -SDMA_PERF_SEL_TLBI_RTN = 96 -SDMA_PERF_SEL_GCR_SEND = 97 -SDMA_PERF_SEL_GCR_RTN = 98 -SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 99 -SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 100 -SDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_PIPES_BC_ENUM' -NUM_PIPES_BC_ENUM__enumvalues = { - 0: 'ADDR_NUM_PIPES_BC_P8', - 1: 'ADDR_NUM_PIPES_BC_P16', -} -ADDR_NUM_PIPES_BC_P8 = 0 -ADDR_NUM_PIPES_BC_P16 = 1 -NUM_PIPES_BC_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'NUM_BANKS_BC_ENUM' -NUM_BANKS_BC_ENUM__enumvalues = { - 0: 'ADDR_NUM_BANKS_BC_BANKS_1', - 1: 'ADDR_NUM_BANKS_BC_BANKS_2', - 2: 'ADDR_NUM_BANKS_BC_BANKS_4', - 3: 'ADDR_NUM_BANKS_BC_BANKS_8', - 4: 'ADDR_NUM_BANKS_BC_BANKS_16', -} -ADDR_NUM_BANKS_BC_BANKS_1 = 0 -ADDR_NUM_BANKS_BC_BANKS_2 = 1 -ADDR_NUM_BANKS_BC_BANKS_4 = 2 -ADDR_NUM_BANKS_BC_BANKS_8 = 3 -ADDR_NUM_BANKS_BC_BANKS_16 = 4 -NUM_BANKS_BC_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'SWIZZLE_TYPE_ENUM' -SWIZZLE_TYPE_ENUM__enumvalues = { - 0: 'SW_Z', - 1: 'SW_S', - 2: 'SW_D', - 3: 'SW_R', - 4: 'SW_L', -} -SW_Z = 0 -SW_S = 1 -SW_D = 2 -SW_R = 3 -SW_L = 4 -SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TC_MICRO_TILE_MODE' -TC_MICRO_TILE_MODE__enumvalues = { - 0: 'MICRO_TILE_MODE_LINEAR', - 1: 'MICRO_TILE_MODE_RENDER_TARGET', - 2: 'MICRO_TILE_MODE_STD_2D', - 3: 'MICRO_TILE_MODE_STD_3D', - 4: 'MICRO_TILE_MODE_DISPLAY_2D', - 5: 'MICRO_TILE_MODE_DISPLAY_3D', - 6: 'MICRO_TILE_MODE_Z', -} -MICRO_TILE_MODE_LINEAR = 0 -MICRO_TILE_MODE_RENDER_TARGET = 1 -MICRO_TILE_MODE_STD_2D = 2 -MICRO_TILE_MODE_STD_3D = 3 -MICRO_TILE_MODE_DISPLAY_2D = 4 -MICRO_TILE_MODE_DISPLAY_3D = 5 -MICRO_TILE_MODE_Z = 6 -TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SWIZZLE_MODE_ENUM' -SWIZZLE_MODE_ENUM__enumvalues = { - 0: 'SW_LINEAR', - 1: 'SW_256B_S', - 2: 'SW_256B_D', - 3: 'SW_256B_R', - 4: 'SW_4KB_Z', - 5: 'SW_4KB_S', - 6: 'SW_4KB_D', - 7: 'SW_4KB_R', - 8: 'SW_64KB_Z', - 9: 'SW_64KB_S', - 10: 'SW_64KB_D', - 11: 'SW_64KB_R', - 12: 'SW_VAR_Z', - 13: 'SW_VAR_S', - 14: 'SW_VAR_D', - 15: 'SW_VAR_R', - 16: 'SW_64KB_Z_T', - 17: 'SW_64KB_S_T', - 18: 'SW_64KB_D_T', - 19: 'SW_64KB_R_T', - 20: 'SW_4KB_Z_X', - 21: 'SW_4KB_S_X', - 22: 'SW_4KB_D_X', - 23: 'SW_4KB_R_X', - 24: 'SW_64KB_Z_X', - 25: 'SW_64KB_S_X', - 26: 'SW_64KB_D_X', - 27: 'SW_64KB_R_X', - 28: 'SW_VAR_Z_X', - 29: 'SW_VAR_S_X', - 30: 'SW_VAR_D_X', - 31: 'SW_VAR_R_X', -} -SW_LINEAR = 0 -SW_256B_S = 1 -SW_256B_D = 2 -SW_256B_R = 3 -SW_4KB_Z = 4 -SW_4KB_S = 5 -SW_4KB_D = 6 -SW_4KB_R = 7 -SW_64KB_Z = 8 -SW_64KB_S = 9 -SW_64KB_D = 10 -SW_64KB_R = 11 -SW_VAR_Z = 12 -SW_VAR_S = 13 -SW_VAR_D = 14 -SW_VAR_R = 15 -SW_64KB_Z_T = 16 -SW_64KB_S_T = 17 -SW_64KB_D_T = 18 -SW_64KB_R_T = 19 -SW_4KB_Z_X = 20 -SW_4KB_S_X = 21 -SW_4KB_D_X = 22 -SW_4KB_R_X = 23 -SW_64KB_Z_X = 24 -SW_64KB_S_X = 25 -SW_64KB_D_X = 26 -SW_64KB_R_X = 27 -SW_VAR_Z_X = 28 -SW_VAR_S_X = 29 -SW_VAR_D_X = 30 -SW_VAR_R_X = 31 -SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceEndian' -SurfaceEndian__enumvalues = { - 0: 'ENDIAN_NONE', - 1: 'ENDIAN_8IN16', - 2: 'ENDIAN_8IN32', - 3: 'ENDIAN_8IN64', -} -ENDIAN_NONE = 0 -ENDIAN_8IN16 = 1 -ENDIAN_8IN32 = 2 -ENDIAN_8IN64 = 3 -SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'ArrayMode' -ArrayMode__enumvalues = { - 0: 'ARRAY_LINEAR_GENERAL', - 1: 'ARRAY_LINEAR_ALIGNED', - 2: 'ARRAY_1D_TILED_THIN1', - 3: 'ARRAY_1D_TILED_THICK', - 4: 'ARRAY_2D_TILED_THIN1', - 5: 'ARRAY_PRT_TILED_THIN1', - 6: 'ARRAY_PRT_2D_TILED_THIN1', - 7: 'ARRAY_2D_TILED_THICK', - 8: 'ARRAY_2D_TILED_XTHICK', - 9: 'ARRAY_PRT_TILED_THICK', - 10: 'ARRAY_PRT_2D_TILED_THICK', - 11: 'ARRAY_PRT_3D_TILED_THIN1', - 12: 'ARRAY_3D_TILED_THIN1', - 13: 'ARRAY_3D_TILED_THICK', - 14: 'ARRAY_3D_TILED_XTHICK', - 15: 'ARRAY_PRT_3D_TILED_THICK', -} -ARRAY_LINEAR_GENERAL = 0 -ARRAY_LINEAR_ALIGNED = 1 -ARRAY_1D_TILED_THIN1 = 2 -ARRAY_1D_TILED_THICK = 3 -ARRAY_2D_TILED_THIN1 = 4 -ARRAY_PRT_TILED_THIN1 = 5 -ARRAY_PRT_2D_TILED_THIN1 = 6 -ARRAY_2D_TILED_THICK = 7 -ARRAY_2D_TILED_XTHICK = 8 -ARRAY_PRT_TILED_THICK = 9 -ARRAY_PRT_2D_TILED_THICK = 10 -ARRAY_PRT_3D_TILED_THIN1 = 11 -ARRAY_3D_TILED_THIN1 = 12 -ARRAY_3D_TILED_THICK = 13 -ARRAY_3D_TILED_XTHICK = 14 -ARRAY_PRT_3D_TILED_THICK = 15 -ArrayMode = ctypes.c_uint32 # enum - -# values for enumeration 'NumPipes' -NumPipes__enumvalues = { - 0: 'ADDR_CONFIG_1_PIPE', - 1: 'ADDR_CONFIG_2_PIPE', - 2: 'ADDR_CONFIG_4_PIPE', - 3: 'ADDR_CONFIG_8_PIPE', - 4: 'ADDR_CONFIG_16_PIPE', - 5: 'ADDR_CONFIG_32_PIPE', - 6: 'ADDR_CONFIG_64_PIPE', -} -ADDR_CONFIG_1_PIPE = 0 -ADDR_CONFIG_2_PIPE = 1 -ADDR_CONFIG_4_PIPE = 2 -ADDR_CONFIG_8_PIPE = 3 -ADDR_CONFIG_16_PIPE = 4 -ADDR_CONFIG_32_PIPE = 5 -ADDR_CONFIG_64_PIPE = 6 -NumPipes = ctypes.c_uint32 # enum - -# values for enumeration 'NumBanksConfig' -NumBanksConfig__enumvalues = { - 0: 'ADDR_CONFIG_1_BANK', - 1: 'ADDR_CONFIG_2_BANK', - 2: 'ADDR_CONFIG_4_BANK', - 3: 'ADDR_CONFIG_8_BANK', - 4: 'ADDR_CONFIG_16_BANK', -} -ADDR_CONFIG_1_BANK = 0 -ADDR_CONFIG_2_BANK = 1 -ADDR_CONFIG_4_BANK = 2 -ADDR_CONFIG_8_BANK = 3 -ADDR_CONFIG_16_BANK = 4 -NumBanksConfig = ctypes.c_uint32 # enum - -# values for enumeration 'PipeInterleaveSize' -PipeInterleaveSize__enumvalues = { - 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', - 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', - 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', - 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', -} -ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 -ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 -ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 -ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 -PipeInterleaveSize = ctypes.c_uint32 # enum - -# values for enumeration 'BankInterleaveSize' -BankInterleaveSize__enumvalues = { - 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', - 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', - 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', - 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', -} -ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 -ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 -ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 -ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 -BankInterleaveSize = ctypes.c_uint32 # enum - -# values for enumeration 'NumShaderEngines' -NumShaderEngines__enumvalues = { - 0: 'ADDR_CONFIG_1_SHADER_ENGINE', - 1: 'ADDR_CONFIG_2_SHADER_ENGINE', - 2: 'ADDR_CONFIG_4_SHADER_ENGINE', - 3: 'ADDR_CONFIG_8_SHADER_ENGINE', -} -ADDR_CONFIG_1_SHADER_ENGINE = 0 -ADDR_CONFIG_2_SHADER_ENGINE = 1 -ADDR_CONFIG_4_SHADER_ENGINE = 2 -ADDR_CONFIG_8_SHADER_ENGINE = 3 -NumShaderEngines = ctypes.c_uint32 # enum - -# values for enumeration 'NumRbPerShaderEngine' -NumRbPerShaderEngine__enumvalues = { - 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', - 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', - 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', -} -ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 -ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 -ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 -NumRbPerShaderEngine = ctypes.c_uint32 # enum - -# values for enumeration 'NumGPUs' -NumGPUs__enumvalues = { - 0: 'ADDR_CONFIG_1_GPU', - 1: 'ADDR_CONFIG_2_GPU', - 2: 'ADDR_CONFIG_4_GPU', - 3: 'ADDR_CONFIG_8_GPU', -} -ADDR_CONFIG_1_GPU = 0 -ADDR_CONFIG_2_GPU = 1 -ADDR_CONFIG_4_GPU = 2 -ADDR_CONFIG_8_GPU = 3 -NumGPUs = ctypes.c_uint32 # enum - -# values for enumeration 'NumMaxCompressedFragments' -NumMaxCompressedFragments__enumvalues = { - 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', - 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', - 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', - 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', -} -ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 -ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 -ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 -ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 -NumMaxCompressedFragments = ctypes.c_uint32 # enum - -# values for enumeration 'ShaderEngineTileSize' -ShaderEngineTileSize__enumvalues = { - 0: 'ADDR_CONFIG_SE_TILE_16', - 1: 'ADDR_CONFIG_SE_TILE_32', -} -ADDR_CONFIG_SE_TILE_16 = 0 -ADDR_CONFIG_SE_TILE_32 = 1 -ShaderEngineTileSize = ctypes.c_uint32 # enum - -# values for enumeration 'MultiGPUTileSize' -MultiGPUTileSize__enumvalues = { - 0: 'ADDR_CONFIG_GPU_TILE_16', - 1: 'ADDR_CONFIG_GPU_TILE_32', - 2: 'ADDR_CONFIG_GPU_TILE_64', - 3: 'ADDR_CONFIG_GPU_TILE_128', -} -ADDR_CONFIG_GPU_TILE_16 = 0 -ADDR_CONFIG_GPU_TILE_32 = 1 -ADDR_CONFIG_GPU_TILE_64 = 2 -ADDR_CONFIG_GPU_TILE_128 = 3 -MultiGPUTileSize = ctypes.c_uint32 # enum - -# values for enumeration 'RowSize' -RowSize__enumvalues = { - 0: 'ADDR_CONFIG_1KB_ROW', - 1: 'ADDR_CONFIG_2KB_ROW', - 2: 'ADDR_CONFIG_4KB_ROW', -} -ADDR_CONFIG_1KB_ROW = 0 -ADDR_CONFIG_2KB_ROW = 1 -ADDR_CONFIG_4KB_ROW = 2 -RowSize = ctypes.c_uint32 # enum - -# values for enumeration 'NumLowerPipes' -NumLowerPipes__enumvalues = { - 0: 'ADDR_CONFIG_1_LOWER_PIPES', - 1: 'ADDR_CONFIG_2_LOWER_PIPES', -} -ADDR_CONFIG_1_LOWER_PIPES = 0 -ADDR_CONFIG_2_LOWER_PIPES = 1 -NumLowerPipes = ctypes.c_uint32 # enum - -# values for enumeration 'ColorTransform' -ColorTransform__enumvalues = { - 0: 'DCC_CT_AUTO', - 1: 'DCC_CT_NONE', - 2: 'ABGR_TO_A_BG_G_RB', - 3: 'BGRA_TO_BG_G_RB_A', -} -DCC_CT_AUTO = 0 -DCC_CT_NONE = 1 -ABGR_TO_A_BG_G_RB = 2 -BGRA_TO_BG_G_RB_A = 3 -ColorTransform = ctypes.c_uint32 # enum - -# values for enumeration 'CompareRef' -CompareRef__enumvalues = { - 0: 'REF_NEVER', - 1: 'REF_LESS', - 2: 'REF_EQUAL', - 3: 'REF_LEQUAL', - 4: 'REF_GREATER', - 5: 'REF_NOTEQUAL', - 6: 'REF_GEQUAL', - 7: 'REF_ALWAYS', -} -REF_NEVER = 0 -REF_LESS = 1 -REF_EQUAL = 2 -REF_LEQUAL = 3 -REF_GREATER = 4 -REF_NOTEQUAL = 5 -REF_GEQUAL = 6 -REF_ALWAYS = 7 -CompareRef = ctypes.c_uint32 # enum - -# values for enumeration 'ReadSize' -ReadSize__enumvalues = { - 0: 'READ_256_BITS', - 1: 'READ_512_BITS', -} -READ_256_BITS = 0 -READ_512_BITS = 1 -ReadSize = ctypes.c_uint32 # enum - -# values for enumeration 'DepthFormat' -DepthFormat__enumvalues = { - 0: 'DEPTH_INVALID', - 1: 'DEPTH_16', - 2: 'DEPTH_X8_24', - 3: 'DEPTH_8_24', - 4: 'DEPTH_X8_24_FLOAT', - 5: 'DEPTH_8_24_FLOAT', - 6: 'DEPTH_32_FLOAT', - 7: 'DEPTH_X24_8_32_FLOAT', -} -DEPTH_INVALID = 0 -DEPTH_16 = 1 -DEPTH_X8_24 = 2 -DEPTH_8_24 = 3 -DEPTH_X8_24_FLOAT = 4 -DEPTH_8_24_FLOAT = 5 -DEPTH_32_FLOAT = 6 -DEPTH_X24_8_32_FLOAT = 7 -DepthFormat = ctypes.c_uint32 # enum - -# values for enumeration 'ZFormat' -ZFormat__enumvalues = { - 0: 'Z_INVALID', - 1: 'Z_16', - 2: 'Z_24', - 3: 'Z_32_FLOAT', -} -Z_INVALID = 0 -Z_16 = 1 -Z_24 = 2 -Z_32_FLOAT = 3 -ZFormat = ctypes.c_uint32 # enum - -# values for enumeration 'StencilFormat' -StencilFormat__enumvalues = { - 0: 'STENCIL_INVALID', - 1: 'STENCIL_8', -} -STENCIL_INVALID = 0 -STENCIL_8 = 1 -StencilFormat = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskMode' -CmaskMode__enumvalues = { - 0: 'CMASK_CLEAR_NONE', - 1: 'CMASK_CLEAR_ONE', - 2: 'CMASK_CLEAR_ALL', - 3: 'CMASK_ANY_EXPANDED', - 4: 'CMASK_ALPHA0_FRAG1', - 5: 'CMASK_ALPHA0_FRAG2', - 6: 'CMASK_ALPHA0_FRAG4', - 7: 'CMASK_ALPHA0_FRAGS', - 8: 'CMASK_ALPHA1_FRAG1', - 9: 'CMASK_ALPHA1_FRAG2', - 10: 'CMASK_ALPHA1_FRAG4', - 11: 'CMASK_ALPHA1_FRAGS', - 12: 'CMASK_ALPHAX_FRAG1', - 13: 'CMASK_ALPHAX_FRAG2', - 14: 'CMASK_ALPHAX_FRAG4', - 15: 'CMASK_ALPHAX_FRAGS', -} -CMASK_CLEAR_NONE = 0 -CMASK_CLEAR_ONE = 1 -CMASK_CLEAR_ALL = 2 -CMASK_ANY_EXPANDED = 3 -CMASK_ALPHA0_FRAG1 = 4 -CMASK_ALPHA0_FRAG2 = 5 -CMASK_ALPHA0_FRAG4 = 6 -CMASK_ALPHA0_FRAGS = 7 -CMASK_ALPHA1_FRAG1 = 8 -CMASK_ALPHA1_FRAG2 = 9 -CMASK_ALPHA1_FRAG4 = 10 -CMASK_ALPHA1_FRAGS = 11 -CMASK_ALPHAX_FRAG1 = 12 -CMASK_ALPHAX_FRAG2 = 13 -CMASK_ALPHAX_FRAG4 = 14 -CMASK_ALPHAX_FRAGS = 15 -CmaskMode = ctypes.c_uint32 # enum - -# values for enumeration 'QuadExportFormat' -QuadExportFormat__enumvalues = { - 0: 'EXPORT_UNUSED', - 1: 'EXPORT_32_R', - 2: 'EXPORT_32_GR', - 3: 'EXPORT_32_AR', - 4: 'EXPORT_FP16_ABGR', - 5: 'EXPORT_UNSIGNED16_ABGR', - 6: 'EXPORT_SIGNED16_ABGR', - 7: 'EXPORT_32_ABGR', - 8: 'EXPORT_32BPP_8PIX', - 9: 'EXPORT_16_16_UNSIGNED_8PIX', - 10: 'EXPORT_16_16_SIGNED_8PIX', - 11: 'EXPORT_16_16_FLOAT_8PIX', -} -EXPORT_UNUSED = 0 -EXPORT_32_R = 1 -EXPORT_32_GR = 2 -EXPORT_32_AR = 3 -EXPORT_FP16_ABGR = 4 -EXPORT_UNSIGNED16_ABGR = 5 -EXPORT_SIGNED16_ABGR = 6 -EXPORT_32_ABGR = 7 -EXPORT_32BPP_8PIX = 8 -EXPORT_16_16_UNSIGNED_8PIX = 9 -EXPORT_16_16_SIGNED_8PIX = 10 -EXPORT_16_16_FLOAT_8PIX = 11 -QuadExportFormat = ctypes.c_uint32 # enum - -# values for enumeration 'QuadExportFormatOld' -QuadExportFormatOld__enumvalues = { - 0: 'EXPORT_4P_32BPC_ABGR', - 1: 'EXPORT_4P_16BPC_ABGR', - 2: 'EXPORT_4P_32BPC_GR', - 3: 'EXPORT_4P_32BPC_AR', - 4: 'EXPORT_2P_32BPC_ABGR', - 5: 'EXPORT_8P_32BPC_R', -} -EXPORT_4P_32BPC_ABGR = 0 -EXPORT_4P_16BPC_ABGR = 1 -EXPORT_4P_32BPC_GR = 2 -EXPORT_4P_32BPC_AR = 3 -EXPORT_2P_32BPC_ABGR = 4 -EXPORT_8P_32BPC_R = 5 -QuadExportFormatOld = ctypes.c_uint32 # enum - -# values for enumeration 'ColorFormat' -ColorFormat__enumvalues = { - 0: 'COLOR_INVALID', - 1: 'COLOR_8', - 2: 'COLOR_16', - 3: 'COLOR_8_8', - 4: 'COLOR_32', - 5: 'COLOR_16_16', - 6: 'COLOR_10_11_11', - 7: 'COLOR_11_11_10', - 8: 'COLOR_10_10_10_2', - 9: 'COLOR_2_10_10_10', - 10: 'COLOR_8_8_8_8', - 11: 'COLOR_32_32', - 12: 'COLOR_16_16_16_16', - 13: 'COLOR_RESERVED_13', - 14: 'COLOR_32_32_32_32', - 15: 'COLOR_RESERVED_15', - 16: 'COLOR_5_6_5', - 17: 'COLOR_1_5_5_5', - 18: 'COLOR_5_5_5_1', - 19: 'COLOR_4_4_4_4', - 20: 'COLOR_8_24', - 21: 'COLOR_24_8', - 22: 'COLOR_X24_8_32_FLOAT', - 23: 'COLOR_RESERVED_23', - 24: 'COLOR_RESERVED_24', - 25: 'COLOR_RESERVED_25', - 26: 'COLOR_RESERVED_26', - 27: 'COLOR_RESERVED_27', - 28: 'COLOR_RESERVED_28', - 29: 'COLOR_RESERVED_29', - 30: 'COLOR_RESERVED_30', - 31: 'COLOR_2_10_10_10_6E4', -} -COLOR_INVALID = 0 -COLOR_8 = 1 -COLOR_16 = 2 -COLOR_8_8 = 3 -COLOR_32 = 4 -COLOR_16_16 = 5 -COLOR_10_11_11 = 6 -COLOR_11_11_10 = 7 -COLOR_10_10_10_2 = 8 -COLOR_2_10_10_10 = 9 -COLOR_8_8_8_8 = 10 -COLOR_32_32 = 11 -COLOR_16_16_16_16 = 12 -COLOR_RESERVED_13 = 13 -COLOR_32_32_32_32 = 14 -COLOR_RESERVED_15 = 15 -COLOR_5_6_5 = 16 -COLOR_1_5_5_5 = 17 -COLOR_5_5_5_1 = 18 -COLOR_4_4_4_4 = 19 -COLOR_8_24 = 20 -COLOR_24_8 = 21 -COLOR_X24_8_32_FLOAT = 22 -COLOR_RESERVED_23 = 23 -COLOR_RESERVED_24 = 24 -COLOR_RESERVED_25 = 25 -COLOR_RESERVED_26 = 26 -COLOR_RESERVED_27 = 27 -COLOR_RESERVED_28 = 28 -COLOR_RESERVED_29 = 29 -COLOR_RESERVED_30 = 30 -COLOR_2_10_10_10_6E4 = 31 -ColorFormat = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceFormat' -SurfaceFormat__enumvalues = { - 0: 'FMT_INVALID', - 1: 'FMT_8', - 2: 'FMT_16', - 3: 'FMT_8_8', - 4: 'FMT_32', - 5: 'FMT_16_16', - 6: 'FMT_10_11_11', - 7: 'FMT_11_11_10', - 8: 'FMT_10_10_10_2', - 9: 'FMT_2_10_10_10', - 10: 'FMT_8_8_8_8', - 11: 'FMT_32_32', - 12: 'FMT_16_16_16_16', - 13: 'FMT_32_32_32', - 14: 'FMT_32_32_32_32', - 15: 'FMT_RESERVED_4', - 16: 'FMT_5_6_5', - 17: 'FMT_1_5_5_5', - 18: 'FMT_5_5_5_1', - 19: 'FMT_4_4_4_4', - 20: 'FMT_8_24', - 21: 'FMT_24_8', - 22: 'FMT_X24_8_32_FLOAT', - 23: 'FMT_RESERVED_33', - 24: 'FMT_11_11_10_FLOAT', - 25: 'FMT_16_FLOAT', - 26: 'FMT_32_FLOAT', - 27: 'FMT_16_16_FLOAT', - 28: 'FMT_8_24_FLOAT', - 29: 'FMT_24_8_FLOAT', - 30: 'FMT_32_32_FLOAT', - 31: 'FMT_10_11_11_FLOAT', - 32: 'FMT_16_16_16_16_FLOAT', - 33: 'FMT_3_3_2', - 34: 'FMT_6_5_5', - 35: 'FMT_32_32_32_32_FLOAT', - 36: 'FMT_RESERVED_36', - 37: 'FMT_1', - 38: 'FMT_1_REVERSED', - 39: 'FMT_GB_GR', - 40: 'FMT_BG_RG', - 41: 'FMT_32_AS_8', - 42: 'FMT_32_AS_8_8', - 43: 'FMT_5_9_9_9_SHAREDEXP', - 44: 'FMT_8_8_8', - 45: 'FMT_16_16_16', - 46: 'FMT_16_16_16_FLOAT', - 47: 'FMT_4_4', - 48: 'FMT_32_32_32_FLOAT', - 49: 'FMT_BC1', - 50: 'FMT_BC2', - 51: 'FMT_BC3', - 52: 'FMT_BC4', - 53: 'FMT_BC5', - 54: 'FMT_BC6', - 55: 'FMT_BC7', - 56: 'FMT_32_AS_32_32_32_32', - 57: 'FMT_APC3', - 58: 'FMT_APC4', - 59: 'FMT_APC5', - 60: 'FMT_APC6', - 61: 'FMT_APC7', - 62: 'FMT_CTX1', - 63: 'FMT_RESERVED_63', -} -FMT_INVALID = 0 -FMT_8 = 1 -FMT_16 = 2 -FMT_8_8 = 3 -FMT_32 = 4 -FMT_16_16 = 5 -FMT_10_11_11 = 6 -FMT_11_11_10 = 7 -FMT_10_10_10_2 = 8 -FMT_2_10_10_10 = 9 -FMT_8_8_8_8 = 10 -FMT_32_32 = 11 -FMT_16_16_16_16 = 12 -FMT_32_32_32 = 13 -FMT_32_32_32_32 = 14 -FMT_RESERVED_4 = 15 -FMT_5_6_5 = 16 -FMT_1_5_5_5 = 17 -FMT_5_5_5_1 = 18 -FMT_4_4_4_4 = 19 -FMT_8_24 = 20 -FMT_24_8 = 21 -FMT_X24_8_32_FLOAT = 22 -FMT_RESERVED_33 = 23 -FMT_11_11_10_FLOAT = 24 -FMT_16_FLOAT = 25 -FMT_32_FLOAT = 26 -FMT_16_16_FLOAT = 27 -FMT_8_24_FLOAT = 28 -FMT_24_8_FLOAT = 29 -FMT_32_32_FLOAT = 30 -FMT_10_11_11_FLOAT = 31 -FMT_16_16_16_16_FLOAT = 32 -FMT_3_3_2 = 33 -FMT_6_5_5 = 34 -FMT_32_32_32_32_FLOAT = 35 -FMT_RESERVED_36 = 36 -FMT_1 = 37 -FMT_1_REVERSED = 38 -FMT_GB_GR = 39 -FMT_BG_RG = 40 -FMT_32_AS_8 = 41 -FMT_32_AS_8_8 = 42 -FMT_5_9_9_9_SHAREDEXP = 43 -FMT_8_8_8 = 44 -FMT_16_16_16 = 45 -FMT_16_16_16_FLOAT = 46 -FMT_4_4 = 47 -FMT_32_32_32_FLOAT = 48 -FMT_BC1 = 49 -FMT_BC2 = 50 -FMT_BC3 = 51 -FMT_BC4 = 52 -FMT_BC5 = 53 -FMT_BC6 = 54 -FMT_BC7 = 55 -FMT_32_AS_32_32_32_32 = 56 -FMT_APC3 = 57 -FMT_APC4 = 58 -FMT_APC5 = 59 -FMT_APC6 = 60 -FMT_APC7 = 61 -FMT_CTX1 = 62 -FMT_RESERVED_63 = 63 -SurfaceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_FMASK' -IMG_NUM_FORMAT_FMASK__enumvalues = { - 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', - 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', - 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', - 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', - 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', - 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', - 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', - 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', - 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', - 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', - 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', - 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', - 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', - 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', - 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', - 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', -} -IMG_NUM_FORMAT_FMASK_8_2_1 = 0 -IMG_NUM_FORMAT_FMASK_8_4_1 = 1 -IMG_NUM_FORMAT_FMASK_8_8_1 = 2 -IMG_NUM_FORMAT_FMASK_8_2_2 = 3 -IMG_NUM_FORMAT_FMASK_8_4_2 = 4 -IMG_NUM_FORMAT_FMASK_8_4_4 = 5 -IMG_NUM_FORMAT_FMASK_16_16_1 = 6 -IMG_NUM_FORMAT_FMASK_16_8_2 = 7 -IMG_NUM_FORMAT_FMASK_32_16_2 = 8 -IMG_NUM_FORMAT_FMASK_32_8_4 = 9 -IMG_NUM_FORMAT_FMASK_32_8_8 = 10 -IMG_NUM_FORMAT_FMASK_64_16_4 = 11 -IMG_NUM_FORMAT_FMASK_64_16_8 = 12 -IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 -IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 -IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 -IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_N_IN_16' -IMG_NUM_FORMAT_N_IN_16__enumvalues = { - 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', - 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', - 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', - 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', - 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', - 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', - 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', - 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', - 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', - 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', - 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', - 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', - 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', - 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', - 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', - 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', -} -IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 -IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 -IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 -IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 -IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 -IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 -IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 -IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 -IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 -IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 -IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 -IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 -IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 -IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 -IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 -IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 -IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum - -# values for enumeration 'TileType' -TileType__enumvalues = { - 0: 'ARRAY_COLOR_TILE', - 1: 'ARRAY_DEPTH_TILE', -} -ARRAY_COLOR_TILE = 0 -ARRAY_DEPTH_TILE = 1 -TileType = ctypes.c_uint32 # enum - -# values for enumeration 'NonDispTilingOrder' -NonDispTilingOrder__enumvalues = { - 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', - 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', -} -ADDR_SURF_MICRO_TILING_DISPLAY = 0 -ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 -NonDispTilingOrder = ctypes.c_uint32 # enum - -# values for enumeration 'MicroTileMode' -MicroTileMode__enumvalues = { - 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', - 1: 'ADDR_SURF_THIN_MICRO_TILING', - 2: 'ADDR_SURF_DEPTH_MICRO_TILING', - 3: 'ADDR_SURF_ROTATED_MICRO_TILING', - 4: 'ADDR_SURF_THICK_MICRO_TILING', -} -ADDR_SURF_DISPLAY_MICRO_TILING = 0 -ADDR_SURF_THIN_MICRO_TILING = 1 -ADDR_SURF_DEPTH_MICRO_TILING = 2 -ADDR_SURF_ROTATED_MICRO_TILING = 3 -ADDR_SURF_THICK_MICRO_TILING = 4 -MicroTileMode = ctypes.c_uint32 # enum - -# values for enumeration 'TileSplit' -TileSplit__enumvalues = { - 0: 'ADDR_SURF_TILE_SPLIT_64B', - 1: 'ADDR_SURF_TILE_SPLIT_128B', - 2: 'ADDR_SURF_TILE_SPLIT_256B', - 3: 'ADDR_SURF_TILE_SPLIT_512B', - 4: 'ADDR_SURF_TILE_SPLIT_1KB', - 5: 'ADDR_SURF_TILE_SPLIT_2KB', - 6: 'ADDR_SURF_TILE_SPLIT_4KB', -} -ADDR_SURF_TILE_SPLIT_64B = 0 -ADDR_SURF_TILE_SPLIT_128B = 1 -ADDR_SURF_TILE_SPLIT_256B = 2 -ADDR_SURF_TILE_SPLIT_512B = 3 -ADDR_SURF_TILE_SPLIT_1KB = 4 -ADDR_SURF_TILE_SPLIT_2KB = 5 -ADDR_SURF_TILE_SPLIT_4KB = 6 -TileSplit = ctypes.c_uint32 # enum - -# values for enumeration 'SampleSplit' -SampleSplit__enumvalues = { - 0: 'ADDR_SURF_SAMPLE_SPLIT_1', - 1: 'ADDR_SURF_SAMPLE_SPLIT_2', - 2: 'ADDR_SURF_SAMPLE_SPLIT_4', - 3: 'ADDR_SURF_SAMPLE_SPLIT_8', -} -ADDR_SURF_SAMPLE_SPLIT_1 = 0 -ADDR_SURF_SAMPLE_SPLIT_2 = 1 -ADDR_SURF_SAMPLE_SPLIT_4 = 2 -ADDR_SURF_SAMPLE_SPLIT_8 = 3 -SampleSplit = ctypes.c_uint32 # enum - -# values for enumeration 'PipeConfig' -PipeConfig__enumvalues = { - 0: 'ADDR_SURF_P2', - 1: 'ADDR_SURF_P2_RESERVED0', - 2: 'ADDR_SURF_P2_RESERVED1', - 3: 'ADDR_SURF_P2_RESERVED2', - 4: 'ADDR_SURF_P4_8x16', - 5: 'ADDR_SURF_P4_16x16', - 6: 'ADDR_SURF_P4_16x32', - 7: 'ADDR_SURF_P4_32x32', - 8: 'ADDR_SURF_P8_16x16_8x16', - 9: 'ADDR_SURF_P8_16x32_8x16', - 10: 'ADDR_SURF_P8_32x32_8x16', - 11: 'ADDR_SURF_P8_16x32_16x16', - 12: 'ADDR_SURF_P8_32x32_16x16', - 13: 'ADDR_SURF_P8_32x32_16x32', - 14: 'ADDR_SURF_P8_32x64_32x32', - 15: 'ADDR_SURF_P8_RESERVED0', - 16: 'ADDR_SURF_P16_32x32_8x16', - 17: 'ADDR_SURF_P16_32x32_16x16', - 18: 'ADDR_SURF_P16', -} -ADDR_SURF_P2 = 0 -ADDR_SURF_P2_RESERVED0 = 1 -ADDR_SURF_P2_RESERVED1 = 2 -ADDR_SURF_P2_RESERVED2 = 3 -ADDR_SURF_P4_8x16 = 4 -ADDR_SURF_P4_16x16 = 5 -ADDR_SURF_P4_16x32 = 6 -ADDR_SURF_P4_32x32 = 7 -ADDR_SURF_P8_16x16_8x16 = 8 -ADDR_SURF_P8_16x32_8x16 = 9 -ADDR_SURF_P8_32x32_8x16 = 10 -ADDR_SURF_P8_16x32_16x16 = 11 -ADDR_SURF_P8_32x32_16x16 = 12 -ADDR_SURF_P8_32x32_16x32 = 13 -ADDR_SURF_P8_32x64_32x32 = 14 -ADDR_SURF_P8_RESERVED0 = 15 -ADDR_SURF_P16_32x32_8x16 = 16 -ADDR_SURF_P16_32x32_16x16 = 17 -ADDR_SURF_P16 = 18 -PipeConfig = ctypes.c_uint32 # enum - -# values for enumeration 'SeEnable' -SeEnable__enumvalues = { - 0: 'ADDR_CONFIG_DISABLE_SE', - 1: 'ADDR_CONFIG_ENABLE_SE', -} -ADDR_CONFIG_DISABLE_SE = 0 -ADDR_CONFIG_ENABLE_SE = 1 -SeEnable = ctypes.c_uint32 # enum - -# values for enumeration 'NumBanks' -NumBanks__enumvalues = { - 0: 'ADDR_SURF_2_BANK', - 1: 'ADDR_SURF_4_BANK', - 2: 'ADDR_SURF_8_BANK', - 3: 'ADDR_SURF_16_BANK', -} -ADDR_SURF_2_BANK = 0 -ADDR_SURF_4_BANK = 1 -ADDR_SURF_8_BANK = 2 -ADDR_SURF_16_BANK = 3 -NumBanks = ctypes.c_uint32 # enum - -# values for enumeration 'BankWidth' -BankWidth__enumvalues = { - 0: 'ADDR_SURF_BANK_WIDTH_1', - 1: 'ADDR_SURF_BANK_WIDTH_2', - 2: 'ADDR_SURF_BANK_WIDTH_4', - 3: 'ADDR_SURF_BANK_WIDTH_8', -} -ADDR_SURF_BANK_WIDTH_1 = 0 -ADDR_SURF_BANK_WIDTH_2 = 1 -ADDR_SURF_BANK_WIDTH_4 = 2 -ADDR_SURF_BANK_WIDTH_8 = 3 -BankWidth = ctypes.c_uint32 # enum - -# values for enumeration 'BankHeight' -BankHeight__enumvalues = { - 0: 'ADDR_SURF_BANK_HEIGHT_1', - 1: 'ADDR_SURF_BANK_HEIGHT_2', - 2: 'ADDR_SURF_BANK_HEIGHT_4', - 3: 'ADDR_SURF_BANK_HEIGHT_8', -} -ADDR_SURF_BANK_HEIGHT_1 = 0 -ADDR_SURF_BANK_HEIGHT_2 = 1 -ADDR_SURF_BANK_HEIGHT_4 = 2 -ADDR_SURF_BANK_HEIGHT_8 = 3 -BankHeight = ctypes.c_uint32 # enum - -# values for enumeration 'BankWidthHeight' -BankWidthHeight__enumvalues = { - 0: 'ADDR_SURF_BANK_WH_1', - 1: 'ADDR_SURF_BANK_WH_2', - 2: 'ADDR_SURF_BANK_WH_4', - 3: 'ADDR_SURF_BANK_WH_8', -} -ADDR_SURF_BANK_WH_1 = 0 -ADDR_SURF_BANK_WH_2 = 1 -ADDR_SURF_BANK_WH_4 = 2 -ADDR_SURF_BANK_WH_8 = 3 -BankWidthHeight = ctypes.c_uint32 # enum - -# values for enumeration 'MacroTileAspect' -MacroTileAspect__enumvalues = { - 0: 'ADDR_SURF_MACRO_ASPECT_1', - 1: 'ADDR_SURF_MACRO_ASPECT_2', - 2: 'ADDR_SURF_MACRO_ASPECT_4', - 3: 'ADDR_SURF_MACRO_ASPECT_8', -} -ADDR_SURF_MACRO_ASPECT_1 = 0 -ADDR_SURF_MACRO_ASPECT_2 = 1 -ADDR_SURF_MACRO_ASPECT_4 = 2 -ADDR_SURF_MACRO_ASPECT_8 = 3 -MacroTileAspect = ctypes.c_uint32 # enum - -# values for enumeration 'PipeTiling' -PipeTiling__enumvalues = { - 0: 'CONFIG_1_PIPE', - 1: 'CONFIG_2_PIPE', - 2: 'CONFIG_4_PIPE', - 3: 'CONFIG_8_PIPE', -} -CONFIG_1_PIPE = 0 -CONFIG_2_PIPE = 1 -CONFIG_4_PIPE = 2 -CONFIG_8_PIPE = 3 -PipeTiling = ctypes.c_uint32 # enum - -# values for enumeration 'BankTiling' -BankTiling__enumvalues = { - 0: 'CONFIG_4_BANK', - 1: 'CONFIG_8_BANK', -} -CONFIG_4_BANK = 0 -CONFIG_8_BANK = 1 -BankTiling = ctypes.c_uint32 # enum - -# values for enumeration 'GroupInterleave' -GroupInterleave__enumvalues = { - 0: 'CONFIG_256B_GROUP', - 1: 'CONFIG_512B_GROUP', -} -CONFIG_256B_GROUP = 0 -CONFIG_512B_GROUP = 1 -GroupInterleave = ctypes.c_uint32 # enum - -# values for enumeration 'RowTiling' -RowTiling__enumvalues = { - 0: 'CONFIG_1KB_ROW', - 1: 'CONFIG_2KB_ROW', - 2: 'CONFIG_4KB_ROW', - 3: 'CONFIG_8KB_ROW', - 4: 'CONFIG_1KB_ROW_OPT', - 5: 'CONFIG_2KB_ROW_OPT', - 6: 'CONFIG_4KB_ROW_OPT', - 7: 'CONFIG_8KB_ROW_OPT', -} -CONFIG_1KB_ROW = 0 -CONFIG_2KB_ROW = 1 -CONFIG_4KB_ROW = 2 -CONFIG_8KB_ROW = 3 -CONFIG_1KB_ROW_OPT = 4 -CONFIG_2KB_ROW_OPT = 5 -CONFIG_4KB_ROW_OPT = 6 -CONFIG_8KB_ROW_OPT = 7 -RowTiling = ctypes.c_uint32 # enum - -# values for enumeration 'BankSwapBytes' -BankSwapBytes__enumvalues = { - 0: 'CONFIG_128B_SWAPS', - 1: 'CONFIG_256B_SWAPS', - 2: 'CONFIG_512B_SWAPS', - 3: 'CONFIG_1KB_SWAPS', -} -CONFIG_128B_SWAPS = 0 -CONFIG_256B_SWAPS = 1 -CONFIG_512B_SWAPS = 2 -CONFIG_1KB_SWAPS = 3 -BankSwapBytes = ctypes.c_uint32 # enum - -# values for enumeration 'SampleSplitBytes' -SampleSplitBytes__enumvalues = { - 0: 'CONFIG_1KB_SPLIT', - 1: 'CONFIG_2KB_SPLIT', - 2: 'CONFIG_4KB_SPLIT', - 3: 'CONFIG_8KB_SPLIT', -} -CONFIG_1KB_SPLIT = 0 -CONFIG_2KB_SPLIT = 1 -CONFIG_4KB_SPLIT = 2 -CONFIG_8KB_SPLIT = 3 -SampleSplitBytes = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceNumber' -SurfaceNumber__enumvalues = { - 0: 'NUMBER_UNORM', - 1: 'NUMBER_SNORM', - 2: 'NUMBER_USCALED', - 3: 'NUMBER_SSCALED', - 4: 'NUMBER_UINT', - 5: 'NUMBER_SINT', - 6: 'NUMBER_SRGB', - 7: 'NUMBER_FLOAT', -} -NUMBER_UNORM = 0 -NUMBER_SNORM = 1 -NUMBER_USCALED = 2 -NUMBER_SSCALED = 3 -NUMBER_UINT = 4 -NUMBER_SINT = 5 -NUMBER_SRGB = 6 -NUMBER_FLOAT = 7 -SurfaceNumber = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceSwap' -SurfaceSwap__enumvalues = { - 0: 'SWAP_STD', - 1: 'SWAP_ALT', - 2: 'SWAP_STD_REV', - 3: 'SWAP_ALT_REV', -} -SWAP_STD = 0 -SWAP_ALT = 1 -SWAP_STD_REV = 2 -SWAP_ALT_REV = 3 -SurfaceSwap = ctypes.c_uint32 # enum - -# values for enumeration 'RoundMode' -RoundMode__enumvalues = { - 0: 'ROUND_BY_HALF', - 1: 'ROUND_TRUNCATE', -} -ROUND_BY_HALF = 0 -ROUND_TRUNCATE = 1 -RoundMode = ctypes.c_uint32 # enum - -# values for enumeration 'BUF_FMT' -BUF_FMT__enumvalues = { - 0: 'BUF_FMT_INVALID', - 1: 'BUF_FMT_8_UNORM', - 2: 'BUF_FMT_8_SNORM', - 3: 'BUF_FMT_8_USCALED', - 4: 'BUF_FMT_8_SSCALED', - 5: 'BUF_FMT_8_UINT', - 6: 'BUF_FMT_8_SINT', - 7: 'BUF_FMT_16_UNORM', - 8: 'BUF_FMT_16_SNORM', - 9: 'BUF_FMT_16_USCALED', - 10: 'BUF_FMT_16_SSCALED', - 11: 'BUF_FMT_16_UINT', - 12: 'BUF_FMT_16_SINT', - 13: 'BUF_FMT_16_FLOAT', - 14: 'BUF_FMT_8_8_UNORM', - 15: 'BUF_FMT_8_8_SNORM', - 16: 'BUF_FMT_8_8_USCALED', - 17: 'BUF_FMT_8_8_SSCALED', - 18: 'BUF_FMT_8_8_UINT', - 19: 'BUF_FMT_8_8_SINT', - 20: 'BUF_FMT_32_UINT', - 21: 'BUF_FMT_32_SINT', - 22: 'BUF_FMT_32_FLOAT', - 23: 'BUF_FMT_16_16_UNORM', - 24: 'BUF_FMT_16_16_SNORM', - 25: 'BUF_FMT_16_16_USCALED', - 26: 'BUF_FMT_16_16_SSCALED', - 27: 'BUF_FMT_16_16_UINT', - 28: 'BUF_FMT_16_16_SINT', - 29: 'BUF_FMT_16_16_FLOAT', - 30: 'BUF_FMT_10_11_11_UNORM', - 31: 'BUF_FMT_10_11_11_SNORM', - 32: 'BUF_FMT_10_11_11_USCALED', - 33: 'BUF_FMT_10_11_11_SSCALED', - 34: 'BUF_FMT_10_11_11_UINT', - 35: 'BUF_FMT_10_11_11_SINT', - 36: 'BUF_FMT_10_11_11_FLOAT', - 37: 'BUF_FMT_11_11_10_UNORM', - 38: 'BUF_FMT_11_11_10_SNORM', - 39: 'BUF_FMT_11_11_10_USCALED', - 40: 'BUF_FMT_11_11_10_SSCALED', - 41: 'BUF_FMT_11_11_10_UINT', - 42: 'BUF_FMT_11_11_10_SINT', - 43: 'BUF_FMT_11_11_10_FLOAT', - 44: 'BUF_FMT_10_10_10_2_UNORM', - 45: 'BUF_FMT_10_10_10_2_SNORM', - 46: 'BUF_FMT_10_10_10_2_USCALED', - 47: 'BUF_FMT_10_10_10_2_SSCALED', - 48: 'BUF_FMT_10_10_10_2_UINT', - 49: 'BUF_FMT_10_10_10_2_SINT', - 50: 'BUF_FMT_2_10_10_10_UNORM', - 51: 'BUF_FMT_2_10_10_10_SNORM', - 52: 'BUF_FMT_2_10_10_10_USCALED', - 53: 'BUF_FMT_2_10_10_10_SSCALED', - 54: 'BUF_FMT_2_10_10_10_UINT', - 55: 'BUF_FMT_2_10_10_10_SINT', - 56: 'BUF_FMT_8_8_8_8_UNORM', - 57: 'BUF_FMT_8_8_8_8_SNORM', - 58: 'BUF_FMT_8_8_8_8_USCALED', - 59: 'BUF_FMT_8_8_8_8_SSCALED', - 60: 'BUF_FMT_8_8_8_8_UINT', - 61: 'BUF_FMT_8_8_8_8_SINT', - 62: 'BUF_FMT_32_32_UINT', - 63: 'BUF_FMT_32_32_SINT', - 64: 'BUF_FMT_32_32_FLOAT', - 65: 'BUF_FMT_16_16_16_16_UNORM', - 66: 'BUF_FMT_16_16_16_16_SNORM', - 67: 'BUF_FMT_16_16_16_16_USCALED', - 68: 'BUF_FMT_16_16_16_16_SSCALED', - 69: 'BUF_FMT_16_16_16_16_UINT', - 70: 'BUF_FMT_16_16_16_16_SINT', - 71: 'BUF_FMT_16_16_16_16_FLOAT', - 72: 'BUF_FMT_32_32_32_UINT', - 73: 'BUF_FMT_32_32_32_SINT', - 74: 'BUF_FMT_32_32_32_FLOAT', - 75: 'BUF_FMT_32_32_32_32_UINT', - 76: 'BUF_FMT_32_32_32_32_SINT', - 77: 'BUF_FMT_32_32_32_32_FLOAT', - 78: 'BUF_FMT_RESERVED_78', - 79: 'BUF_FMT_RESERVED_79', - 80: 'BUF_FMT_RESERVED_80', - 81: 'BUF_FMT_RESERVED_81', - 82: 'BUF_FMT_RESERVED_82', - 83: 'BUF_FMT_RESERVED_83', - 84: 'BUF_FMT_RESERVED_84', - 85: 'BUF_FMT_RESERVED_85', - 86: 'BUF_FMT_RESERVED_86', - 87: 'BUF_FMT_RESERVED_87', - 88: 'BUF_FMT_RESERVED_88', - 89: 'BUF_FMT_RESERVED_89', - 90: 'BUF_FMT_RESERVED_90', - 91: 'BUF_FMT_RESERVED_91', - 92: 'BUF_FMT_RESERVED_92', - 93: 'BUF_FMT_RESERVED_93', - 94: 'BUF_FMT_RESERVED_94', - 95: 'BUF_FMT_RESERVED_95', - 96: 'BUF_FMT_RESERVED_96', - 97: 'BUF_FMT_RESERVED_97', - 98: 'BUF_FMT_RESERVED_98', - 99: 'BUF_FMT_RESERVED_99', - 100: 'BUF_FMT_RESERVED_100', - 101: 'BUF_FMT_RESERVED_101', - 102: 'BUF_FMT_RESERVED_102', - 103: 'BUF_FMT_RESERVED_103', - 104: 'BUF_FMT_RESERVED_104', - 105: 'BUF_FMT_RESERVED_105', - 106: 'BUF_FMT_RESERVED_106', - 107: 'BUF_FMT_RESERVED_107', - 108: 'BUF_FMT_RESERVED_108', - 109: 'BUF_FMT_RESERVED_109', - 110: 'BUF_FMT_RESERVED_110', - 111: 'BUF_FMT_RESERVED_111', - 112: 'BUF_FMT_RESERVED_112', - 113: 'BUF_FMT_RESERVED_113', - 114: 'BUF_FMT_RESERVED_114', - 115: 'BUF_FMT_RESERVED_115', - 116: 'BUF_FMT_RESERVED_116', - 117: 'BUF_FMT_RESERVED_117', - 118: 'BUF_FMT_RESERVED_118', - 119: 'BUF_FMT_RESERVED_119', - 120: 'BUF_FMT_RESERVED_120', - 121: 'BUF_FMT_RESERVED_121', - 122: 'BUF_FMT_RESERVED_122', - 123: 'BUF_FMT_RESERVED_123', - 124: 'BUF_FMT_RESERVED_124', - 125: 'BUF_FMT_RESERVED_125', - 126: 'BUF_FMT_RESERVED_126', - 127: 'BUF_FMT_RESERVED_127', -} -BUF_FMT_INVALID = 0 -BUF_FMT_8_UNORM = 1 -BUF_FMT_8_SNORM = 2 -BUF_FMT_8_USCALED = 3 -BUF_FMT_8_SSCALED = 4 -BUF_FMT_8_UINT = 5 -BUF_FMT_8_SINT = 6 -BUF_FMT_16_UNORM = 7 -BUF_FMT_16_SNORM = 8 -BUF_FMT_16_USCALED = 9 -BUF_FMT_16_SSCALED = 10 -BUF_FMT_16_UINT = 11 -BUF_FMT_16_SINT = 12 -BUF_FMT_16_FLOAT = 13 -BUF_FMT_8_8_UNORM = 14 -BUF_FMT_8_8_SNORM = 15 -BUF_FMT_8_8_USCALED = 16 -BUF_FMT_8_8_SSCALED = 17 -BUF_FMT_8_8_UINT = 18 -BUF_FMT_8_8_SINT = 19 -BUF_FMT_32_UINT = 20 -BUF_FMT_32_SINT = 21 -BUF_FMT_32_FLOAT = 22 -BUF_FMT_16_16_UNORM = 23 -BUF_FMT_16_16_SNORM = 24 -BUF_FMT_16_16_USCALED = 25 -BUF_FMT_16_16_SSCALED = 26 -BUF_FMT_16_16_UINT = 27 -BUF_FMT_16_16_SINT = 28 -BUF_FMT_16_16_FLOAT = 29 -BUF_FMT_10_11_11_UNORM = 30 -BUF_FMT_10_11_11_SNORM = 31 -BUF_FMT_10_11_11_USCALED = 32 -BUF_FMT_10_11_11_SSCALED = 33 -BUF_FMT_10_11_11_UINT = 34 -BUF_FMT_10_11_11_SINT = 35 -BUF_FMT_10_11_11_FLOAT = 36 -BUF_FMT_11_11_10_UNORM = 37 -BUF_FMT_11_11_10_SNORM = 38 -BUF_FMT_11_11_10_USCALED = 39 -BUF_FMT_11_11_10_SSCALED = 40 -BUF_FMT_11_11_10_UINT = 41 -BUF_FMT_11_11_10_SINT = 42 -BUF_FMT_11_11_10_FLOAT = 43 -BUF_FMT_10_10_10_2_UNORM = 44 -BUF_FMT_10_10_10_2_SNORM = 45 -BUF_FMT_10_10_10_2_USCALED = 46 -BUF_FMT_10_10_10_2_SSCALED = 47 -BUF_FMT_10_10_10_2_UINT = 48 -BUF_FMT_10_10_10_2_SINT = 49 -BUF_FMT_2_10_10_10_UNORM = 50 -BUF_FMT_2_10_10_10_SNORM = 51 -BUF_FMT_2_10_10_10_USCALED = 52 -BUF_FMT_2_10_10_10_SSCALED = 53 -BUF_FMT_2_10_10_10_UINT = 54 -BUF_FMT_2_10_10_10_SINT = 55 -BUF_FMT_8_8_8_8_UNORM = 56 -BUF_FMT_8_8_8_8_SNORM = 57 -BUF_FMT_8_8_8_8_USCALED = 58 -BUF_FMT_8_8_8_8_SSCALED = 59 -BUF_FMT_8_8_8_8_UINT = 60 -BUF_FMT_8_8_8_8_SINT = 61 -BUF_FMT_32_32_UINT = 62 -BUF_FMT_32_32_SINT = 63 -BUF_FMT_32_32_FLOAT = 64 -BUF_FMT_16_16_16_16_UNORM = 65 -BUF_FMT_16_16_16_16_SNORM = 66 -BUF_FMT_16_16_16_16_USCALED = 67 -BUF_FMT_16_16_16_16_SSCALED = 68 -BUF_FMT_16_16_16_16_UINT = 69 -BUF_FMT_16_16_16_16_SINT = 70 -BUF_FMT_16_16_16_16_FLOAT = 71 -BUF_FMT_32_32_32_UINT = 72 -BUF_FMT_32_32_32_SINT = 73 -BUF_FMT_32_32_32_FLOAT = 74 -BUF_FMT_32_32_32_32_UINT = 75 -BUF_FMT_32_32_32_32_SINT = 76 -BUF_FMT_32_32_32_32_FLOAT = 77 -BUF_FMT_RESERVED_78 = 78 -BUF_FMT_RESERVED_79 = 79 -BUF_FMT_RESERVED_80 = 80 -BUF_FMT_RESERVED_81 = 81 -BUF_FMT_RESERVED_82 = 82 -BUF_FMT_RESERVED_83 = 83 -BUF_FMT_RESERVED_84 = 84 -BUF_FMT_RESERVED_85 = 85 -BUF_FMT_RESERVED_86 = 86 -BUF_FMT_RESERVED_87 = 87 -BUF_FMT_RESERVED_88 = 88 -BUF_FMT_RESERVED_89 = 89 -BUF_FMT_RESERVED_90 = 90 -BUF_FMT_RESERVED_91 = 91 -BUF_FMT_RESERVED_92 = 92 -BUF_FMT_RESERVED_93 = 93 -BUF_FMT_RESERVED_94 = 94 -BUF_FMT_RESERVED_95 = 95 -BUF_FMT_RESERVED_96 = 96 -BUF_FMT_RESERVED_97 = 97 -BUF_FMT_RESERVED_98 = 98 -BUF_FMT_RESERVED_99 = 99 -BUF_FMT_RESERVED_100 = 100 -BUF_FMT_RESERVED_101 = 101 -BUF_FMT_RESERVED_102 = 102 -BUF_FMT_RESERVED_103 = 103 -BUF_FMT_RESERVED_104 = 104 -BUF_FMT_RESERVED_105 = 105 -BUF_FMT_RESERVED_106 = 106 -BUF_FMT_RESERVED_107 = 107 -BUF_FMT_RESERVED_108 = 108 -BUF_FMT_RESERVED_109 = 109 -BUF_FMT_RESERVED_110 = 110 -BUF_FMT_RESERVED_111 = 111 -BUF_FMT_RESERVED_112 = 112 -BUF_FMT_RESERVED_113 = 113 -BUF_FMT_RESERVED_114 = 114 -BUF_FMT_RESERVED_115 = 115 -BUF_FMT_RESERVED_116 = 116 -BUF_FMT_RESERVED_117 = 117 -BUF_FMT_RESERVED_118 = 118 -BUF_FMT_RESERVED_119 = 119 -BUF_FMT_RESERVED_120 = 120 -BUF_FMT_RESERVED_121 = 121 -BUF_FMT_RESERVED_122 = 122 -BUF_FMT_RESERVED_123 = 123 -BUF_FMT_RESERVED_124 = 124 -BUF_FMT_RESERVED_125 = 125 -BUF_FMT_RESERVED_126 = 126 -BUF_FMT_RESERVED_127 = 127 -BUF_FMT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_FMT' -IMG_FMT__enumvalues = { - 0: 'IMG_FMT_INVALID', - 1: 'IMG_FMT_8_UNORM', - 2: 'IMG_FMT_8_SNORM', - 3: 'IMG_FMT_8_USCALED', - 4: 'IMG_FMT_8_SSCALED', - 5: 'IMG_FMT_8_UINT', - 6: 'IMG_FMT_8_SINT', - 7: 'IMG_FMT_16_UNORM', - 8: 'IMG_FMT_16_SNORM', - 9: 'IMG_FMT_16_USCALED', - 10: 'IMG_FMT_16_SSCALED', - 11: 'IMG_FMT_16_UINT', - 12: 'IMG_FMT_16_SINT', - 13: 'IMG_FMT_16_FLOAT', - 14: 'IMG_FMT_8_8_UNORM', - 15: 'IMG_FMT_8_8_SNORM', - 16: 'IMG_FMT_8_8_USCALED', - 17: 'IMG_FMT_8_8_SSCALED', - 18: 'IMG_FMT_8_8_UINT', - 19: 'IMG_FMT_8_8_SINT', - 20: 'IMG_FMT_32_UINT', - 21: 'IMG_FMT_32_SINT', - 22: 'IMG_FMT_32_FLOAT', - 23: 'IMG_FMT_16_16_UNORM', - 24: 'IMG_FMT_16_16_SNORM', - 25: 'IMG_FMT_16_16_USCALED', - 26: 'IMG_FMT_16_16_SSCALED', - 27: 'IMG_FMT_16_16_UINT', - 28: 'IMG_FMT_16_16_SINT', - 29: 'IMG_FMT_16_16_FLOAT', - 30: 'IMG_FMT_10_11_11_UNORM', - 31: 'IMG_FMT_10_11_11_SNORM', - 32: 'IMG_FMT_10_11_11_USCALED', - 33: 'IMG_FMT_10_11_11_SSCALED', - 34: 'IMG_FMT_10_11_11_UINT', - 35: 'IMG_FMT_10_11_11_SINT', - 36: 'IMG_FMT_10_11_11_FLOAT', - 37: 'IMG_FMT_11_11_10_UNORM', - 38: 'IMG_FMT_11_11_10_SNORM', - 39: 'IMG_FMT_11_11_10_USCALED', - 40: 'IMG_FMT_11_11_10_SSCALED', - 41: 'IMG_FMT_11_11_10_UINT', - 42: 'IMG_FMT_11_11_10_SINT', - 43: 'IMG_FMT_11_11_10_FLOAT', - 44: 'IMG_FMT_10_10_10_2_UNORM', - 45: 'IMG_FMT_10_10_10_2_SNORM', - 46: 'IMG_FMT_10_10_10_2_USCALED', - 47: 'IMG_FMT_10_10_10_2_SSCALED', - 48: 'IMG_FMT_10_10_10_2_UINT', - 49: 'IMG_FMT_10_10_10_2_SINT', - 50: 'IMG_FMT_2_10_10_10_UNORM', - 51: 'IMG_FMT_2_10_10_10_SNORM', - 52: 'IMG_FMT_2_10_10_10_USCALED', - 53: 'IMG_FMT_2_10_10_10_SSCALED', - 54: 'IMG_FMT_2_10_10_10_UINT', - 55: 'IMG_FMT_2_10_10_10_SINT', - 56: 'IMG_FMT_8_8_8_8_UNORM', - 57: 'IMG_FMT_8_8_8_8_SNORM', - 58: 'IMG_FMT_8_8_8_8_USCALED', - 59: 'IMG_FMT_8_8_8_8_SSCALED', - 60: 'IMG_FMT_8_8_8_8_UINT', - 61: 'IMG_FMT_8_8_8_8_SINT', - 62: 'IMG_FMT_32_32_UINT', - 63: 'IMG_FMT_32_32_SINT', - 64: 'IMG_FMT_32_32_FLOAT', - 65: 'IMG_FMT_16_16_16_16_UNORM', - 66: 'IMG_FMT_16_16_16_16_SNORM', - 67: 'IMG_FMT_16_16_16_16_USCALED', - 68: 'IMG_FMT_16_16_16_16_SSCALED', - 69: 'IMG_FMT_16_16_16_16_UINT', - 70: 'IMG_FMT_16_16_16_16_SINT', - 71: 'IMG_FMT_16_16_16_16_FLOAT', - 72: 'IMG_FMT_32_32_32_UINT', - 73: 'IMG_FMT_32_32_32_SINT', - 74: 'IMG_FMT_32_32_32_FLOAT', - 75: 'IMG_FMT_32_32_32_32_UINT', - 76: 'IMG_FMT_32_32_32_32_SINT', - 77: 'IMG_FMT_32_32_32_32_FLOAT', - 78: 'IMG_FMT_RESERVED_78', - 79: 'IMG_FMT_RESERVED_79', - 80: 'IMG_FMT_RESERVED_80', - 81: 'IMG_FMT_RESERVED_81', - 82: 'IMG_FMT_RESERVED_82', - 83: 'IMG_FMT_RESERVED_83', - 84: 'IMG_FMT_RESERVED_84', - 85: 'IMG_FMT_RESERVED_85', - 86: 'IMG_FMT_RESERVED_86', - 87: 'IMG_FMT_RESERVED_87', - 88: 'IMG_FMT_RESERVED_88', - 89: 'IMG_FMT_RESERVED_89', - 90: 'IMG_FMT_RESERVED_90', - 91: 'IMG_FMT_RESERVED_91', - 92: 'IMG_FMT_RESERVED_92', - 93: 'IMG_FMT_RESERVED_93', - 94: 'IMG_FMT_RESERVED_94', - 95: 'IMG_FMT_RESERVED_95', - 96: 'IMG_FMT_RESERVED_96', - 97: 'IMG_FMT_RESERVED_97', - 98: 'IMG_FMT_RESERVED_98', - 99: 'IMG_FMT_RESERVED_99', - 100: 'IMG_FMT_RESERVED_100', - 101: 'IMG_FMT_RESERVED_101', - 102: 'IMG_FMT_RESERVED_102', - 103: 'IMG_FMT_RESERVED_103', - 104: 'IMG_FMT_RESERVED_104', - 105: 'IMG_FMT_RESERVED_105', - 106: 'IMG_FMT_RESERVED_106', - 107: 'IMG_FMT_RESERVED_107', - 108: 'IMG_FMT_RESERVED_108', - 109: 'IMG_FMT_RESERVED_109', - 110: 'IMG_FMT_RESERVED_110', - 111: 'IMG_FMT_RESERVED_111', - 112: 'IMG_FMT_RESERVED_112', - 113: 'IMG_FMT_RESERVED_113', - 114: 'IMG_FMT_RESERVED_114', - 115: 'IMG_FMT_RESERVED_115', - 116: 'IMG_FMT_RESERVED_116', - 117: 'IMG_FMT_RESERVED_117', - 118: 'IMG_FMT_RESERVED_118', - 119: 'IMG_FMT_RESERVED_119', - 120: 'IMG_FMT_RESERVED_120', - 121: 'IMG_FMT_RESERVED_121', - 122: 'IMG_FMT_RESERVED_122', - 123: 'IMG_FMT_RESERVED_123', - 124: 'IMG_FMT_RESERVED_124', - 125: 'IMG_FMT_RESERVED_125', - 126: 'IMG_FMT_RESERVED_126', - 127: 'IMG_FMT_RESERVED_127', - 128: 'IMG_FMT_8_SRGB', - 129: 'IMG_FMT_8_8_SRGB', - 130: 'IMG_FMT_8_8_8_8_SRGB', - 131: 'IMG_FMT_6E4_FLOAT', - 132: 'IMG_FMT_5_9_9_9_FLOAT', - 133: 'IMG_FMT_5_6_5_UNORM', - 134: 'IMG_FMT_1_5_5_5_UNORM', - 135: 'IMG_FMT_5_5_5_1_UNORM', - 136: 'IMG_FMT_4_4_4_4_UNORM', - 137: 'IMG_FMT_4_4_UNORM', - 138: 'IMG_FMT_1_UNORM', - 139: 'IMG_FMT_1_REVERSED_UNORM', - 140: 'IMG_FMT_32_FLOAT_CLAMP', - 141: 'IMG_FMT_8_24_UNORM', - 142: 'IMG_FMT_8_24_UINT', - 143: 'IMG_FMT_24_8_UNORM', - 144: 'IMG_FMT_24_8_UINT', - 145: 'IMG_FMT_X24_8_32_UINT', - 146: 'IMG_FMT_X24_8_32_FLOAT', - 147: 'IMG_FMT_GB_GR_UNORM', - 148: 'IMG_FMT_GB_GR_SNORM', - 149: 'IMG_FMT_GB_GR_UINT', - 150: 'IMG_FMT_GB_GR_SRGB', - 151: 'IMG_FMT_BG_RG_UNORM', - 152: 'IMG_FMT_BG_RG_SNORM', - 153: 'IMG_FMT_BG_RG_UINT', - 154: 'IMG_FMT_BG_RG_SRGB', - 155: 'IMG_FMT_RESERVED_155', - 156: 'IMG_FMT_FMASK8_S2_F1', - 157: 'IMG_FMT_FMASK8_S4_F1', - 158: 'IMG_FMT_FMASK8_S8_F1', - 159: 'IMG_FMT_FMASK8_S2_F2', - 160: 'IMG_FMT_FMASK8_S4_F2', - 161: 'IMG_FMT_FMASK8_S4_F4', - 162: 'IMG_FMT_FMASK16_S16_F1', - 163: 'IMG_FMT_FMASK16_S8_F2', - 164: 'IMG_FMT_FMASK32_S16_F2', - 165: 'IMG_FMT_FMASK32_S8_F4', - 166: 'IMG_FMT_FMASK32_S8_F8', - 167: 'IMG_FMT_FMASK64_S16_F4', - 168: 'IMG_FMT_FMASK64_S16_F8', - 169: 'IMG_FMT_BC1_UNORM', - 170: 'IMG_FMT_BC1_SRGB', - 171: 'IMG_FMT_BC2_UNORM', - 172: 'IMG_FMT_BC2_SRGB', - 173: 'IMG_FMT_BC3_UNORM', - 174: 'IMG_FMT_BC3_SRGB', - 175: 'IMG_FMT_BC4_UNORM', - 176: 'IMG_FMT_BC4_SNORM', - 177: 'IMG_FMT_BC5_UNORM', - 178: 'IMG_FMT_BC5_SNORM', - 179: 'IMG_FMT_BC6_UFLOAT', - 180: 'IMG_FMT_BC6_SFLOAT', - 181: 'IMG_FMT_BC7_UNORM', - 182: 'IMG_FMT_BC7_SRGB', - 265: 'IMG_FMT_MM_8_UNORM', - 266: 'IMG_FMT_MM_8_UINT', - 267: 'IMG_FMT_MM_8_8_UNORM', - 268: 'IMG_FMT_MM_8_8_UINT', - 269: 'IMG_FMT_MM_8_8_8_8_UNORM', - 270: 'IMG_FMT_MM_8_8_8_8_UINT', - 271: 'IMG_FMT_MM_VYUY8_UNORM', - 272: 'IMG_FMT_MM_VYUY8_UINT', - 273: 'IMG_FMT_MM_10_11_11_UNORM', - 274: 'IMG_FMT_MM_10_11_11_UINT', - 275: 'IMG_FMT_MM_2_10_10_10_UNORM', - 276: 'IMG_FMT_MM_2_10_10_10_UINT', - 277: 'IMG_FMT_MM_16_16_16_16_UNORM', - 278: 'IMG_FMT_MM_16_16_16_16_UINT', - 279: 'IMG_FMT_MM_10_IN_16_UNORM', - 280: 'IMG_FMT_MM_10_IN_16_UINT', - 281: 'IMG_FMT_MM_10_IN_16_16_UNORM', - 282: 'IMG_FMT_MM_10_IN_16_16_UINT', - 283: 'IMG_FMT_MM_10_IN_16_16_16_16_UNORM', - 284: 'IMG_FMT_MM_10_IN_16_16_16_16_UINT', - 285: 'IMG_FMT_RESERVED_285', - 286: 'IMG_FMT_RESERVED_286', - 287: 'IMG_FMT_RESERVED_287', - 288: 'IMG_FMT_RESERVED_288', - 289: 'IMG_FMT_RESERVED_289', - 290: 'IMG_FMT_RESERVED_290', - 291: 'IMG_FMT_RESERVED_291', - 292: 'IMG_FMT_RESERVED_292', - 293: 'IMG_FMT_RESERVED_293', - 294: 'IMG_FMT_RESERVED_294', - 295: 'IMG_FMT_RESERVED_295', - 296: 'IMG_FMT_RESERVED_296', - 297: 'IMG_FMT_RESERVED_297', - 298: 'IMG_FMT_RESERVED_298', - 299: 'IMG_FMT_RESERVED_299', - 300: 'IMG_FMT_RESERVED_300', - 301: 'IMG_FMT_RESERVED_301', - 302: 'IMG_FMT_RESERVED_302', - 303: 'IMG_FMT_RESERVED_303', - 304: 'IMG_FMT_RESERVED_304', - 305: 'IMG_FMT_RESERVED_305', - 306: 'IMG_FMT_RESERVED_306', - 307: 'IMG_FMT_RESERVED_307', - 308: 'IMG_FMT_RESERVED_308', - 309: 'IMG_FMT_RESERVED_309', - 310: 'IMG_FMT_RESERVED_310', - 311: 'IMG_FMT_RESERVED_311', - 312: 'IMG_FMT_RESERVED_312', - 313: 'IMG_FMT_RESERVED_313', - 314: 'IMG_FMT_RESERVED_314', - 315: 'IMG_FMT_RESERVED_315', - 316: 'IMG_FMT_RESERVED_316', - 317: 'IMG_FMT_RESERVED_317', - 318: 'IMG_FMT_RESERVED_318', - 319: 'IMG_FMT_RESERVED_319', - 320: 'IMG_FMT_RESERVED_320', - 321: 'IMG_FMT_RESERVED_321', - 322: 'IMG_FMT_RESERVED_322', - 323: 'IMG_FMT_RESERVED_323', - 324: 'IMG_FMT_RESERVED_324', - 325: 'IMG_FMT_RESERVED_325', - 326: 'IMG_FMT_RESERVED_326', - 327: 'IMG_FMT_RESERVED_327', - 328: 'IMG_FMT_RESERVED_328', - 329: 'IMG_FMT_RESERVED_329', - 330: 'IMG_FMT_RESERVED_330', - 331: 'IMG_FMT_RESERVED_331', - 332: 'IMG_FMT_RESERVED_332', - 333: 'IMG_FMT_RESERVED_333', - 334: 'IMG_FMT_RESERVED_334', - 335: 'IMG_FMT_RESERVED_335', - 336: 'IMG_FMT_RESERVED_336', - 337: 'IMG_FMT_RESERVED_337', - 338: 'IMG_FMT_RESERVED_338', - 339: 'IMG_FMT_RESERVED_339', - 340: 'IMG_FMT_RESERVED_340', - 341: 'IMG_FMT_RESERVED_341', - 342: 'IMG_FMT_RESERVED_342', - 343: 'IMG_FMT_RESERVED_343', - 344: 'IMG_FMT_RESERVED_344', - 345: 'IMG_FMT_RESERVED_345', - 346: 'IMG_FMT_RESERVED_346', - 347: 'IMG_FMT_RESERVED_347', - 348: 'IMG_FMT_RESERVED_348', - 349: 'IMG_FMT_RESERVED_349', - 350: 'IMG_FMT_RESERVED_350', - 351: 'IMG_FMT_RESERVED_351', - 352: 'IMG_FMT_RESERVED_352', - 353: 'IMG_FMT_RESERVED_353', - 354: 'IMG_FMT_RESERVED_354', - 355: 'IMG_FMT_RESERVED_355', - 356: 'IMG_FMT_RESERVED_356', - 357: 'IMG_FMT_RESERVED_357', - 358: 'IMG_FMT_RESERVED_358', - 359: 'IMG_FMT_RESERVED_359', - 360: 'IMG_FMT_RESERVED_360', - 361: 'IMG_FMT_RESERVED_361', - 362: 'IMG_FMT_RESERVED_362', - 363: 'IMG_FMT_RESERVED_363', - 364: 'IMG_FMT_RESERVED_364', - 365: 'IMG_FMT_RESERVED_365', - 366: 'IMG_FMT_RESERVED_366', - 367: 'IMG_FMT_RESERVED_367', - 368: 'IMG_FMT_RESERVED_368', - 369: 'IMG_FMT_RESERVED_369', - 370: 'IMG_FMT_RESERVED_370', - 371: 'IMG_FMT_RESERVED_371', - 372: 'IMG_FMT_RESERVED_372', - 373: 'IMG_FMT_RESERVED_373', - 374: 'IMG_FMT_RESERVED_374', - 375: 'IMG_FMT_RESERVED_375', - 376: 'IMG_FMT_RESERVED_376', - 377: 'IMG_FMT_RESERVED_377', - 378: 'IMG_FMT_RESERVED_378', - 379: 'IMG_FMT_RESERVED_379', - 380: 'IMG_FMT_RESERVED_380', - 381: 'IMG_FMT_RESERVED_381', - 382: 'IMG_FMT_RESERVED_382', - 383: 'IMG_FMT_RESERVED_383', - 384: 'IMG_FMT_RESERVED_384', - 385: 'IMG_FMT_RESERVED_385', - 386: 'IMG_FMT_RESERVED_386', - 387: 'IMG_FMT_RESERVED_387', - 388: 'IMG_FMT_RESERVED_388', - 389: 'IMG_FMT_RESERVED_389', - 390: 'IMG_FMT_RESERVED_390', - 391: 'IMG_FMT_RESERVED_391', - 392: 'IMG_FMT_RESERVED_392', - 393: 'IMG_FMT_RESERVED_393', - 394: 'IMG_FMT_RESERVED_394', - 395: 'IMG_FMT_RESERVED_395', - 396: 'IMG_FMT_RESERVED_396', - 397: 'IMG_FMT_RESERVED_397', - 398: 'IMG_FMT_RESERVED_398', - 399: 'IMG_FMT_RESERVED_399', - 400: 'IMG_FMT_RESERVED_400', - 401: 'IMG_FMT_RESERVED_401', - 402: 'IMG_FMT_RESERVED_402', - 403: 'IMG_FMT_RESERVED_403', - 404: 'IMG_FMT_RESERVED_404', - 405: 'IMG_FMT_RESERVED_405', - 406: 'IMG_FMT_RESERVED_406', - 407: 'IMG_FMT_RESERVED_407', - 408: 'IMG_FMT_RESERVED_408', - 409: 'IMG_FMT_RESERVED_409', - 410: 'IMG_FMT_RESERVED_410', - 411: 'IMG_FMT_RESERVED_411', - 412: 'IMG_FMT_RESERVED_412', - 413: 'IMG_FMT_RESERVED_413', - 414: 'IMG_FMT_RESERVED_414', - 415: 'IMG_FMT_RESERVED_415', - 416: 'IMG_FMT_RESERVED_416', - 417: 'IMG_FMT_RESERVED_417', - 418: 'IMG_FMT_RESERVED_418', - 419: 'IMG_FMT_RESERVED_419', - 420: 'IMG_FMT_RESERVED_420', - 421: 'IMG_FMT_RESERVED_421', - 422: 'IMG_FMT_RESERVED_422', - 423: 'IMG_FMT_RESERVED_423', - 424: 'IMG_FMT_RESERVED_424', - 425: 'IMG_FMT_RESERVED_425', - 426: 'IMG_FMT_RESERVED_426', - 427: 'IMG_FMT_RESERVED_427', - 428: 'IMG_FMT_RESERVED_428', - 429: 'IMG_FMT_RESERVED_429', - 430: 'IMG_FMT_RESERVED_430', - 431: 'IMG_FMT_RESERVED_431', - 432: 'IMG_FMT_RESERVED_432', - 433: 'IMG_FMT_RESERVED_433', - 434: 'IMG_FMT_RESERVED_434', - 435: 'IMG_FMT_RESERVED_435', - 436: 'IMG_FMT_RESERVED_436', - 437: 'IMG_FMT_RESERVED_437', - 438: 'IMG_FMT_RESERVED_438', - 439: 'IMG_FMT_RESERVED_439', - 440: 'IMG_FMT_RESERVED_440', - 441: 'IMG_FMT_RESERVED_441', - 442: 'IMG_FMT_RESERVED_442', - 443: 'IMG_FMT_RESERVED_443', - 444: 'IMG_FMT_RESERVED_444', - 445: 'IMG_FMT_RESERVED_445', - 446: 'IMG_FMT_RESERVED_446', - 447: 'IMG_FMT_RESERVED_447', - 448: 'IMG_FMT_RESERVED_448', - 449: 'IMG_FMT_RESERVED_449', - 450: 'IMG_FMT_RESERVED_450', - 451: 'IMG_FMT_RESERVED_451', - 452: 'IMG_FMT_RESERVED_452', - 453: 'IMG_FMT_RESERVED_453', - 454: 'IMG_FMT_RESERVED_454', - 455: 'IMG_FMT_RESERVED_455', - 456: 'IMG_FMT_RESERVED_456', - 457: 'IMG_FMT_RESERVED_457', - 458: 'IMG_FMT_RESERVED_458', - 459: 'IMG_FMT_RESERVED_459', - 460: 'IMG_FMT_RESERVED_460', - 461: 'IMG_FMT_RESERVED_461', - 462: 'IMG_FMT_RESERVED_462', - 463: 'IMG_FMT_RESERVED_463', - 464: 'IMG_FMT_RESERVED_464', - 465: 'IMG_FMT_RESERVED_465', - 466: 'IMG_FMT_RESERVED_466', - 467: 'IMG_FMT_RESERVED_467', - 468: 'IMG_FMT_RESERVED_468', - 469: 'IMG_FMT_RESERVED_469', - 470: 'IMG_FMT_RESERVED_470', - 471: 'IMG_FMT_RESERVED_471', - 472: 'IMG_FMT_RESERVED_472', - 473: 'IMG_FMT_RESERVED_473', - 474: 'IMG_FMT_RESERVED_474', - 475: 'IMG_FMT_RESERVED_475', - 476: 'IMG_FMT_RESERVED_476', - 477: 'IMG_FMT_RESERVED_477', - 478: 'IMG_FMT_RESERVED_478', - 479: 'IMG_FMT_RESERVED_479', - 480: 'IMG_FMT_RESERVED_480', - 481: 'IMG_FMT_RESERVED_481', - 482: 'IMG_FMT_RESERVED_482', - 483: 'IMG_FMT_RESERVED_483', - 484: 'IMG_FMT_RESERVED_484', - 485: 'IMG_FMT_RESERVED_485', - 486: 'IMG_FMT_RESERVED_486', - 487: 'IMG_FMT_RESERVED_487', - 488: 'IMG_FMT_RESERVED_488', - 489: 'IMG_FMT_RESERVED_489', - 490: 'IMG_FMT_RESERVED_490', - 491: 'IMG_FMT_RESERVED_491', - 492: 'IMG_FMT_RESERVED_492', - 493: 'IMG_FMT_RESERVED_493', - 494: 'IMG_FMT_RESERVED_494', - 495: 'IMG_FMT_RESERVED_495', - 496: 'IMG_FMT_RESERVED_496', - 497: 'IMG_FMT_RESERVED_497', - 498: 'IMG_FMT_RESERVED_498', - 499: 'IMG_FMT_RESERVED_499', - 500: 'IMG_FMT_RESERVED_500', - 501: 'IMG_FMT_RESERVED_501', - 502: 'IMG_FMT_RESERVED_502', - 503: 'IMG_FMT_RESERVED_503', - 504: 'IMG_FMT_RESERVED_504', - 505: 'IMG_FMT_RESERVED_505', - 506: 'IMG_FMT_RESERVED_506', - 507: 'IMG_FMT_RESERVED_507', - 508: 'IMG_FMT_RESERVED_508', - 509: 'IMG_FMT_RESERVED_509', - 510: 'IMG_FMT_RESERVED_510', - 511: 'IMG_FMT_RESERVED_511', -} -IMG_FMT_INVALID = 0 -IMG_FMT_8_UNORM = 1 -IMG_FMT_8_SNORM = 2 -IMG_FMT_8_USCALED = 3 -IMG_FMT_8_SSCALED = 4 -IMG_FMT_8_UINT = 5 -IMG_FMT_8_SINT = 6 -IMG_FMT_16_UNORM = 7 -IMG_FMT_16_SNORM = 8 -IMG_FMT_16_USCALED = 9 -IMG_FMT_16_SSCALED = 10 -IMG_FMT_16_UINT = 11 -IMG_FMT_16_SINT = 12 -IMG_FMT_16_FLOAT = 13 -IMG_FMT_8_8_UNORM = 14 -IMG_FMT_8_8_SNORM = 15 -IMG_FMT_8_8_USCALED = 16 -IMG_FMT_8_8_SSCALED = 17 -IMG_FMT_8_8_UINT = 18 -IMG_FMT_8_8_SINT = 19 -IMG_FMT_32_UINT = 20 -IMG_FMT_32_SINT = 21 -IMG_FMT_32_FLOAT = 22 -IMG_FMT_16_16_UNORM = 23 -IMG_FMT_16_16_SNORM = 24 -IMG_FMT_16_16_USCALED = 25 -IMG_FMT_16_16_SSCALED = 26 -IMG_FMT_16_16_UINT = 27 -IMG_FMT_16_16_SINT = 28 -IMG_FMT_16_16_FLOAT = 29 -IMG_FMT_10_11_11_UNORM = 30 -IMG_FMT_10_11_11_SNORM = 31 -IMG_FMT_10_11_11_USCALED = 32 -IMG_FMT_10_11_11_SSCALED = 33 -IMG_FMT_10_11_11_UINT = 34 -IMG_FMT_10_11_11_SINT = 35 -IMG_FMT_10_11_11_FLOAT = 36 -IMG_FMT_11_11_10_UNORM = 37 -IMG_FMT_11_11_10_SNORM = 38 -IMG_FMT_11_11_10_USCALED = 39 -IMG_FMT_11_11_10_SSCALED = 40 -IMG_FMT_11_11_10_UINT = 41 -IMG_FMT_11_11_10_SINT = 42 -IMG_FMT_11_11_10_FLOAT = 43 -IMG_FMT_10_10_10_2_UNORM = 44 -IMG_FMT_10_10_10_2_SNORM = 45 -IMG_FMT_10_10_10_2_USCALED = 46 -IMG_FMT_10_10_10_2_SSCALED = 47 -IMG_FMT_10_10_10_2_UINT = 48 -IMG_FMT_10_10_10_2_SINT = 49 -IMG_FMT_2_10_10_10_UNORM = 50 -IMG_FMT_2_10_10_10_SNORM = 51 -IMG_FMT_2_10_10_10_USCALED = 52 -IMG_FMT_2_10_10_10_SSCALED = 53 -IMG_FMT_2_10_10_10_UINT = 54 -IMG_FMT_2_10_10_10_SINT = 55 -IMG_FMT_8_8_8_8_UNORM = 56 -IMG_FMT_8_8_8_8_SNORM = 57 -IMG_FMT_8_8_8_8_USCALED = 58 -IMG_FMT_8_8_8_8_SSCALED = 59 -IMG_FMT_8_8_8_8_UINT = 60 -IMG_FMT_8_8_8_8_SINT = 61 -IMG_FMT_32_32_UINT = 62 -IMG_FMT_32_32_SINT = 63 -IMG_FMT_32_32_FLOAT = 64 -IMG_FMT_16_16_16_16_UNORM = 65 -IMG_FMT_16_16_16_16_SNORM = 66 -IMG_FMT_16_16_16_16_USCALED = 67 -IMG_FMT_16_16_16_16_SSCALED = 68 -IMG_FMT_16_16_16_16_UINT = 69 -IMG_FMT_16_16_16_16_SINT = 70 -IMG_FMT_16_16_16_16_FLOAT = 71 -IMG_FMT_32_32_32_UINT = 72 -IMG_FMT_32_32_32_SINT = 73 -IMG_FMT_32_32_32_FLOAT = 74 -IMG_FMT_32_32_32_32_UINT = 75 -IMG_FMT_32_32_32_32_SINT = 76 -IMG_FMT_32_32_32_32_FLOAT = 77 -IMG_FMT_RESERVED_78 = 78 -IMG_FMT_RESERVED_79 = 79 -IMG_FMT_RESERVED_80 = 80 -IMG_FMT_RESERVED_81 = 81 -IMG_FMT_RESERVED_82 = 82 -IMG_FMT_RESERVED_83 = 83 -IMG_FMT_RESERVED_84 = 84 -IMG_FMT_RESERVED_85 = 85 -IMG_FMT_RESERVED_86 = 86 -IMG_FMT_RESERVED_87 = 87 -IMG_FMT_RESERVED_88 = 88 -IMG_FMT_RESERVED_89 = 89 -IMG_FMT_RESERVED_90 = 90 -IMG_FMT_RESERVED_91 = 91 -IMG_FMT_RESERVED_92 = 92 -IMG_FMT_RESERVED_93 = 93 -IMG_FMT_RESERVED_94 = 94 -IMG_FMT_RESERVED_95 = 95 -IMG_FMT_RESERVED_96 = 96 -IMG_FMT_RESERVED_97 = 97 -IMG_FMT_RESERVED_98 = 98 -IMG_FMT_RESERVED_99 = 99 -IMG_FMT_RESERVED_100 = 100 -IMG_FMT_RESERVED_101 = 101 -IMG_FMT_RESERVED_102 = 102 -IMG_FMT_RESERVED_103 = 103 -IMG_FMT_RESERVED_104 = 104 -IMG_FMT_RESERVED_105 = 105 -IMG_FMT_RESERVED_106 = 106 -IMG_FMT_RESERVED_107 = 107 -IMG_FMT_RESERVED_108 = 108 -IMG_FMT_RESERVED_109 = 109 -IMG_FMT_RESERVED_110 = 110 -IMG_FMT_RESERVED_111 = 111 -IMG_FMT_RESERVED_112 = 112 -IMG_FMT_RESERVED_113 = 113 -IMG_FMT_RESERVED_114 = 114 -IMG_FMT_RESERVED_115 = 115 -IMG_FMT_RESERVED_116 = 116 -IMG_FMT_RESERVED_117 = 117 -IMG_FMT_RESERVED_118 = 118 -IMG_FMT_RESERVED_119 = 119 -IMG_FMT_RESERVED_120 = 120 -IMG_FMT_RESERVED_121 = 121 -IMG_FMT_RESERVED_122 = 122 -IMG_FMT_RESERVED_123 = 123 -IMG_FMT_RESERVED_124 = 124 -IMG_FMT_RESERVED_125 = 125 -IMG_FMT_RESERVED_126 = 126 -IMG_FMT_RESERVED_127 = 127 -IMG_FMT_8_SRGB = 128 -IMG_FMT_8_8_SRGB = 129 -IMG_FMT_8_8_8_8_SRGB = 130 -IMG_FMT_6E4_FLOAT = 131 -IMG_FMT_5_9_9_9_FLOAT = 132 -IMG_FMT_5_6_5_UNORM = 133 -IMG_FMT_1_5_5_5_UNORM = 134 -IMG_FMT_5_5_5_1_UNORM = 135 -IMG_FMT_4_4_4_4_UNORM = 136 -IMG_FMT_4_4_UNORM = 137 -IMG_FMT_1_UNORM = 138 -IMG_FMT_1_REVERSED_UNORM = 139 -IMG_FMT_32_FLOAT_CLAMP = 140 -IMG_FMT_8_24_UNORM = 141 -IMG_FMT_8_24_UINT = 142 -IMG_FMT_24_8_UNORM = 143 -IMG_FMT_24_8_UINT = 144 -IMG_FMT_X24_8_32_UINT = 145 -IMG_FMT_X24_8_32_FLOAT = 146 -IMG_FMT_GB_GR_UNORM = 147 -IMG_FMT_GB_GR_SNORM = 148 -IMG_FMT_GB_GR_UINT = 149 -IMG_FMT_GB_GR_SRGB = 150 -IMG_FMT_BG_RG_UNORM = 151 -IMG_FMT_BG_RG_SNORM = 152 -IMG_FMT_BG_RG_UINT = 153 -IMG_FMT_BG_RG_SRGB = 154 -IMG_FMT_RESERVED_155 = 155 -IMG_FMT_FMASK8_S2_F1 = 156 -IMG_FMT_FMASK8_S4_F1 = 157 -IMG_FMT_FMASK8_S8_F1 = 158 -IMG_FMT_FMASK8_S2_F2 = 159 -IMG_FMT_FMASK8_S4_F2 = 160 -IMG_FMT_FMASK8_S4_F4 = 161 -IMG_FMT_FMASK16_S16_F1 = 162 -IMG_FMT_FMASK16_S8_F2 = 163 -IMG_FMT_FMASK32_S16_F2 = 164 -IMG_FMT_FMASK32_S8_F4 = 165 -IMG_FMT_FMASK32_S8_F8 = 166 -IMG_FMT_FMASK64_S16_F4 = 167 -IMG_FMT_FMASK64_S16_F8 = 168 -IMG_FMT_BC1_UNORM = 169 -IMG_FMT_BC1_SRGB = 170 -IMG_FMT_BC2_UNORM = 171 -IMG_FMT_BC2_SRGB = 172 -IMG_FMT_BC3_UNORM = 173 -IMG_FMT_BC3_SRGB = 174 -IMG_FMT_BC4_UNORM = 175 -IMG_FMT_BC4_SNORM = 176 -IMG_FMT_BC5_UNORM = 177 -IMG_FMT_BC5_SNORM = 178 -IMG_FMT_BC6_UFLOAT = 179 -IMG_FMT_BC6_SFLOAT = 180 -IMG_FMT_BC7_UNORM = 181 -IMG_FMT_BC7_SRGB = 182 -IMG_FMT_MM_8_UNORM = 265 -IMG_FMT_MM_8_UINT = 266 -IMG_FMT_MM_8_8_UNORM = 267 -IMG_FMT_MM_8_8_UINT = 268 -IMG_FMT_MM_8_8_8_8_UNORM = 269 -IMG_FMT_MM_8_8_8_8_UINT = 270 -IMG_FMT_MM_VYUY8_UNORM = 271 -IMG_FMT_MM_VYUY8_UINT = 272 -IMG_FMT_MM_10_11_11_UNORM = 273 -IMG_FMT_MM_10_11_11_UINT = 274 -IMG_FMT_MM_2_10_10_10_UNORM = 275 -IMG_FMT_MM_2_10_10_10_UINT = 276 -IMG_FMT_MM_16_16_16_16_UNORM = 277 -IMG_FMT_MM_16_16_16_16_UINT = 278 -IMG_FMT_MM_10_IN_16_UNORM = 279 -IMG_FMT_MM_10_IN_16_UINT = 280 -IMG_FMT_MM_10_IN_16_16_UNORM = 281 -IMG_FMT_MM_10_IN_16_16_UINT = 282 -IMG_FMT_MM_10_IN_16_16_16_16_UNORM = 283 -IMG_FMT_MM_10_IN_16_16_16_16_UINT = 284 -IMG_FMT_RESERVED_285 = 285 -IMG_FMT_RESERVED_286 = 286 -IMG_FMT_RESERVED_287 = 287 -IMG_FMT_RESERVED_288 = 288 -IMG_FMT_RESERVED_289 = 289 -IMG_FMT_RESERVED_290 = 290 -IMG_FMT_RESERVED_291 = 291 -IMG_FMT_RESERVED_292 = 292 -IMG_FMT_RESERVED_293 = 293 -IMG_FMT_RESERVED_294 = 294 -IMG_FMT_RESERVED_295 = 295 -IMG_FMT_RESERVED_296 = 296 -IMG_FMT_RESERVED_297 = 297 -IMG_FMT_RESERVED_298 = 298 -IMG_FMT_RESERVED_299 = 299 -IMG_FMT_RESERVED_300 = 300 -IMG_FMT_RESERVED_301 = 301 -IMG_FMT_RESERVED_302 = 302 -IMG_FMT_RESERVED_303 = 303 -IMG_FMT_RESERVED_304 = 304 -IMG_FMT_RESERVED_305 = 305 -IMG_FMT_RESERVED_306 = 306 -IMG_FMT_RESERVED_307 = 307 -IMG_FMT_RESERVED_308 = 308 -IMG_FMT_RESERVED_309 = 309 -IMG_FMT_RESERVED_310 = 310 -IMG_FMT_RESERVED_311 = 311 -IMG_FMT_RESERVED_312 = 312 -IMG_FMT_RESERVED_313 = 313 -IMG_FMT_RESERVED_314 = 314 -IMG_FMT_RESERVED_315 = 315 -IMG_FMT_RESERVED_316 = 316 -IMG_FMT_RESERVED_317 = 317 -IMG_FMT_RESERVED_318 = 318 -IMG_FMT_RESERVED_319 = 319 -IMG_FMT_RESERVED_320 = 320 -IMG_FMT_RESERVED_321 = 321 -IMG_FMT_RESERVED_322 = 322 -IMG_FMT_RESERVED_323 = 323 -IMG_FMT_RESERVED_324 = 324 -IMG_FMT_RESERVED_325 = 325 -IMG_FMT_RESERVED_326 = 326 -IMG_FMT_RESERVED_327 = 327 -IMG_FMT_RESERVED_328 = 328 -IMG_FMT_RESERVED_329 = 329 -IMG_FMT_RESERVED_330 = 330 -IMG_FMT_RESERVED_331 = 331 -IMG_FMT_RESERVED_332 = 332 -IMG_FMT_RESERVED_333 = 333 -IMG_FMT_RESERVED_334 = 334 -IMG_FMT_RESERVED_335 = 335 -IMG_FMT_RESERVED_336 = 336 -IMG_FMT_RESERVED_337 = 337 -IMG_FMT_RESERVED_338 = 338 -IMG_FMT_RESERVED_339 = 339 -IMG_FMT_RESERVED_340 = 340 -IMG_FMT_RESERVED_341 = 341 -IMG_FMT_RESERVED_342 = 342 -IMG_FMT_RESERVED_343 = 343 -IMG_FMT_RESERVED_344 = 344 -IMG_FMT_RESERVED_345 = 345 -IMG_FMT_RESERVED_346 = 346 -IMG_FMT_RESERVED_347 = 347 -IMG_FMT_RESERVED_348 = 348 -IMG_FMT_RESERVED_349 = 349 -IMG_FMT_RESERVED_350 = 350 -IMG_FMT_RESERVED_351 = 351 -IMG_FMT_RESERVED_352 = 352 -IMG_FMT_RESERVED_353 = 353 -IMG_FMT_RESERVED_354 = 354 -IMG_FMT_RESERVED_355 = 355 -IMG_FMT_RESERVED_356 = 356 -IMG_FMT_RESERVED_357 = 357 -IMG_FMT_RESERVED_358 = 358 -IMG_FMT_RESERVED_359 = 359 -IMG_FMT_RESERVED_360 = 360 -IMG_FMT_RESERVED_361 = 361 -IMG_FMT_RESERVED_362 = 362 -IMG_FMT_RESERVED_363 = 363 -IMG_FMT_RESERVED_364 = 364 -IMG_FMT_RESERVED_365 = 365 -IMG_FMT_RESERVED_366 = 366 -IMG_FMT_RESERVED_367 = 367 -IMG_FMT_RESERVED_368 = 368 -IMG_FMT_RESERVED_369 = 369 -IMG_FMT_RESERVED_370 = 370 -IMG_FMT_RESERVED_371 = 371 -IMG_FMT_RESERVED_372 = 372 -IMG_FMT_RESERVED_373 = 373 -IMG_FMT_RESERVED_374 = 374 -IMG_FMT_RESERVED_375 = 375 -IMG_FMT_RESERVED_376 = 376 -IMG_FMT_RESERVED_377 = 377 -IMG_FMT_RESERVED_378 = 378 -IMG_FMT_RESERVED_379 = 379 -IMG_FMT_RESERVED_380 = 380 -IMG_FMT_RESERVED_381 = 381 -IMG_FMT_RESERVED_382 = 382 -IMG_FMT_RESERVED_383 = 383 -IMG_FMT_RESERVED_384 = 384 -IMG_FMT_RESERVED_385 = 385 -IMG_FMT_RESERVED_386 = 386 -IMG_FMT_RESERVED_387 = 387 -IMG_FMT_RESERVED_388 = 388 -IMG_FMT_RESERVED_389 = 389 -IMG_FMT_RESERVED_390 = 390 -IMG_FMT_RESERVED_391 = 391 -IMG_FMT_RESERVED_392 = 392 -IMG_FMT_RESERVED_393 = 393 -IMG_FMT_RESERVED_394 = 394 -IMG_FMT_RESERVED_395 = 395 -IMG_FMT_RESERVED_396 = 396 -IMG_FMT_RESERVED_397 = 397 -IMG_FMT_RESERVED_398 = 398 -IMG_FMT_RESERVED_399 = 399 -IMG_FMT_RESERVED_400 = 400 -IMG_FMT_RESERVED_401 = 401 -IMG_FMT_RESERVED_402 = 402 -IMG_FMT_RESERVED_403 = 403 -IMG_FMT_RESERVED_404 = 404 -IMG_FMT_RESERVED_405 = 405 -IMG_FMT_RESERVED_406 = 406 -IMG_FMT_RESERVED_407 = 407 -IMG_FMT_RESERVED_408 = 408 -IMG_FMT_RESERVED_409 = 409 -IMG_FMT_RESERVED_410 = 410 -IMG_FMT_RESERVED_411 = 411 -IMG_FMT_RESERVED_412 = 412 -IMG_FMT_RESERVED_413 = 413 -IMG_FMT_RESERVED_414 = 414 -IMG_FMT_RESERVED_415 = 415 -IMG_FMT_RESERVED_416 = 416 -IMG_FMT_RESERVED_417 = 417 -IMG_FMT_RESERVED_418 = 418 -IMG_FMT_RESERVED_419 = 419 -IMG_FMT_RESERVED_420 = 420 -IMG_FMT_RESERVED_421 = 421 -IMG_FMT_RESERVED_422 = 422 -IMG_FMT_RESERVED_423 = 423 -IMG_FMT_RESERVED_424 = 424 -IMG_FMT_RESERVED_425 = 425 -IMG_FMT_RESERVED_426 = 426 -IMG_FMT_RESERVED_427 = 427 -IMG_FMT_RESERVED_428 = 428 -IMG_FMT_RESERVED_429 = 429 -IMG_FMT_RESERVED_430 = 430 -IMG_FMT_RESERVED_431 = 431 -IMG_FMT_RESERVED_432 = 432 -IMG_FMT_RESERVED_433 = 433 -IMG_FMT_RESERVED_434 = 434 -IMG_FMT_RESERVED_435 = 435 -IMG_FMT_RESERVED_436 = 436 -IMG_FMT_RESERVED_437 = 437 -IMG_FMT_RESERVED_438 = 438 -IMG_FMT_RESERVED_439 = 439 -IMG_FMT_RESERVED_440 = 440 -IMG_FMT_RESERVED_441 = 441 -IMG_FMT_RESERVED_442 = 442 -IMG_FMT_RESERVED_443 = 443 -IMG_FMT_RESERVED_444 = 444 -IMG_FMT_RESERVED_445 = 445 -IMG_FMT_RESERVED_446 = 446 -IMG_FMT_RESERVED_447 = 447 -IMG_FMT_RESERVED_448 = 448 -IMG_FMT_RESERVED_449 = 449 -IMG_FMT_RESERVED_450 = 450 -IMG_FMT_RESERVED_451 = 451 -IMG_FMT_RESERVED_452 = 452 -IMG_FMT_RESERVED_453 = 453 -IMG_FMT_RESERVED_454 = 454 -IMG_FMT_RESERVED_455 = 455 -IMG_FMT_RESERVED_456 = 456 -IMG_FMT_RESERVED_457 = 457 -IMG_FMT_RESERVED_458 = 458 -IMG_FMT_RESERVED_459 = 459 -IMG_FMT_RESERVED_460 = 460 -IMG_FMT_RESERVED_461 = 461 -IMG_FMT_RESERVED_462 = 462 -IMG_FMT_RESERVED_463 = 463 -IMG_FMT_RESERVED_464 = 464 -IMG_FMT_RESERVED_465 = 465 -IMG_FMT_RESERVED_466 = 466 -IMG_FMT_RESERVED_467 = 467 -IMG_FMT_RESERVED_468 = 468 -IMG_FMT_RESERVED_469 = 469 -IMG_FMT_RESERVED_470 = 470 -IMG_FMT_RESERVED_471 = 471 -IMG_FMT_RESERVED_472 = 472 -IMG_FMT_RESERVED_473 = 473 -IMG_FMT_RESERVED_474 = 474 -IMG_FMT_RESERVED_475 = 475 -IMG_FMT_RESERVED_476 = 476 -IMG_FMT_RESERVED_477 = 477 -IMG_FMT_RESERVED_478 = 478 -IMG_FMT_RESERVED_479 = 479 -IMG_FMT_RESERVED_480 = 480 -IMG_FMT_RESERVED_481 = 481 -IMG_FMT_RESERVED_482 = 482 -IMG_FMT_RESERVED_483 = 483 -IMG_FMT_RESERVED_484 = 484 -IMG_FMT_RESERVED_485 = 485 -IMG_FMT_RESERVED_486 = 486 -IMG_FMT_RESERVED_487 = 487 -IMG_FMT_RESERVED_488 = 488 -IMG_FMT_RESERVED_489 = 489 -IMG_FMT_RESERVED_490 = 490 -IMG_FMT_RESERVED_491 = 491 -IMG_FMT_RESERVED_492 = 492 -IMG_FMT_RESERVED_493 = 493 -IMG_FMT_RESERVED_494 = 494 -IMG_FMT_RESERVED_495 = 495 -IMG_FMT_RESERVED_496 = 496 -IMG_FMT_RESERVED_497 = 497 -IMG_FMT_RESERVED_498 = 498 -IMG_FMT_RESERVED_499 = 499 -IMG_FMT_RESERVED_500 = 500 -IMG_FMT_RESERVED_501 = 501 -IMG_FMT_RESERVED_502 = 502 -IMG_FMT_RESERVED_503 = 503 -IMG_FMT_RESERVED_504 = 504 -IMG_FMT_RESERVED_505 = 505 -IMG_FMT_RESERVED_506 = 506 -IMG_FMT_RESERVED_507 = 507 -IMG_FMT_RESERVED_508 = 508 -IMG_FMT_RESERVED_509 = 509 -IMG_FMT_RESERVED_510 = 510 -IMG_FMT_RESERVED_511 = 511 -IMG_FMT = ctypes.c_uint32 # enum - -# values for enumeration 'BUF_DATA_FORMAT' -BUF_DATA_FORMAT__enumvalues = { - 0: 'BUF_DATA_FORMAT_INVALID', - 1: 'BUF_DATA_FORMAT_8', - 2: 'BUF_DATA_FORMAT_16', - 3: 'BUF_DATA_FORMAT_8_8', - 4: 'BUF_DATA_FORMAT_32', - 5: 'BUF_DATA_FORMAT_16_16', - 6: 'BUF_DATA_FORMAT_10_11_11', - 7: 'BUF_DATA_FORMAT_11_11_10', - 8: 'BUF_DATA_FORMAT_10_10_10_2', - 9: 'BUF_DATA_FORMAT_2_10_10_10', - 10: 'BUF_DATA_FORMAT_8_8_8_8', - 11: 'BUF_DATA_FORMAT_32_32', - 12: 'BUF_DATA_FORMAT_16_16_16_16', - 13: 'BUF_DATA_FORMAT_32_32_32', - 14: 'BUF_DATA_FORMAT_32_32_32_32', - 15: 'BUF_DATA_FORMAT_RESERVED_15', -} -BUF_DATA_FORMAT_INVALID = 0 -BUF_DATA_FORMAT_8 = 1 -BUF_DATA_FORMAT_16 = 2 -BUF_DATA_FORMAT_8_8 = 3 -BUF_DATA_FORMAT_32 = 4 -BUF_DATA_FORMAT_16_16 = 5 -BUF_DATA_FORMAT_10_11_11 = 6 -BUF_DATA_FORMAT_11_11_10 = 7 -BUF_DATA_FORMAT_10_10_10_2 = 8 -BUF_DATA_FORMAT_2_10_10_10 = 9 -BUF_DATA_FORMAT_8_8_8_8 = 10 -BUF_DATA_FORMAT_32_32 = 11 -BUF_DATA_FORMAT_16_16_16_16 = 12 -BUF_DATA_FORMAT_32_32_32 = 13 -BUF_DATA_FORMAT_32_32_32_32 = 14 -BUF_DATA_FORMAT_RESERVED_15 = 15 -BUF_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_DATA_FORMAT' -IMG_DATA_FORMAT__enumvalues = { - 0: 'IMG_DATA_FORMAT_INVALID', - 1: 'IMG_DATA_FORMAT_8', - 2: 'IMG_DATA_FORMAT_16', - 3: 'IMG_DATA_FORMAT_8_8', - 4: 'IMG_DATA_FORMAT_32', - 5: 'IMG_DATA_FORMAT_16_16', - 6: 'IMG_DATA_FORMAT_10_11_11', - 7: 'IMG_DATA_FORMAT_11_11_10', - 8: 'IMG_DATA_FORMAT_10_10_10_2', - 9: 'IMG_DATA_FORMAT_2_10_10_10', - 10: 'IMG_DATA_FORMAT_8_8_8_8', - 11: 'IMG_DATA_FORMAT_32_32', - 12: 'IMG_DATA_FORMAT_16_16_16_16', - 13: 'IMG_DATA_FORMAT_32_32_32', - 14: 'IMG_DATA_FORMAT_32_32_32_32', - 15: 'IMG_DATA_FORMAT_RESERVED_15', - 16: 'IMG_DATA_FORMAT_5_6_5', - 17: 'IMG_DATA_FORMAT_1_5_5_5', - 18: 'IMG_DATA_FORMAT_5_5_5_1', - 19: 'IMG_DATA_FORMAT_4_4_4_4', - 20: 'IMG_DATA_FORMAT_8_24', - 21: 'IMG_DATA_FORMAT_24_8', - 22: 'IMG_DATA_FORMAT_X24_8_32', - 23: 'IMG_DATA_FORMAT_RESERVED_23', - 24: 'IMG_DATA_FORMAT_RESERVED_24', - 25: 'IMG_DATA_FORMAT_RESERVED_25', - 26: 'IMG_DATA_FORMAT_RESERVED_26', - 27: 'IMG_DATA_FORMAT_RESERVED_27', - 28: 'IMG_DATA_FORMAT_RESERVED_28', - 29: 'IMG_DATA_FORMAT_RESERVED_29', - 30: 'IMG_DATA_FORMAT_RESERVED_30', - 31: 'IMG_DATA_FORMAT_6E4', - 32: 'IMG_DATA_FORMAT_GB_GR', - 33: 'IMG_DATA_FORMAT_BG_RG', - 34: 'IMG_DATA_FORMAT_5_9_9_9', - 35: 'IMG_DATA_FORMAT_BC1', - 36: 'IMG_DATA_FORMAT_BC2', - 37: 'IMG_DATA_FORMAT_BC3', - 38: 'IMG_DATA_FORMAT_BC4', - 39: 'IMG_DATA_FORMAT_BC5', - 40: 'IMG_DATA_FORMAT_BC6', - 41: 'IMG_DATA_FORMAT_BC7', - 42: 'IMG_DATA_FORMAT_RESERVED_42', - 43: 'IMG_DATA_FORMAT_RESERVED_43', - 44: 'IMG_DATA_FORMAT_FMASK8_S2_F1', - 45: 'IMG_DATA_FORMAT_FMASK8_S4_F1', - 46: 'IMG_DATA_FORMAT_FMASK8_S8_F1', - 47: 'IMG_DATA_FORMAT_FMASK8_S2_F2', - 48: 'IMG_DATA_FORMAT_FMASK8_S4_F2', - 49: 'IMG_DATA_FORMAT_FMASK8_S4_F4', - 50: 'IMG_DATA_FORMAT_FMASK16_S16_F1', - 51: 'IMG_DATA_FORMAT_FMASK16_S8_F2', - 52: 'IMG_DATA_FORMAT_FMASK32_S16_F2', - 53: 'IMG_DATA_FORMAT_FMASK32_S8_F4', - 54: 'IMG_DATA_FORMAT_FMASK32_S8_F8', - 55: 'IMG_DATA_FORMAT_FMASK64_S16_F4', - 56: 'IMG_DATA_FORMAT_FMASK64_S16_F8', - 57: 'IMG_DATA_FORMAT_4_4', - 58: 'IMG_DATA_FORMAT_6_5_5', - 59: 'IMG_DATA_FORMAT_1', - 60: 'IMG_DATA_FORMAT_1_REVERSED', - 61: 'IMG_DATA_FORMAT_RESERVED_61', - 62: 'IMG_DATA_FORMAT_RESERVED_62', - 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', - 75: 'IMG_DATA_FORMAT_RESERVED_75', - 76: 'IMG_DATA_FORMAT_MM_8', - 77: 'IMG_DATA_FORMAT_MM_8_8', - 78: 'IMG_DATA_FORMAT_MM_8_8_8_8', - 79: 'IMG_DATA_FORMAT_MM_VYUY8', - 80: 'IMG_DATA_FORMAT_MM_10_11_11', - 81: 'IMG_DATA_FORMAT_MM_2_10_10_10', - 82: 'IMG_DATA_FORMAT_MM_16_16_16_16', - 83: 'IMG_DATA_FORMAT_MM_10_IN_16', - 84: 'IMG_DATA_FORMAT_MM_10_IN_16_16', - 85: 'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16', - 86: 'IMG_DATA_FORMAT_RESERVED_86', - 87: 'IMG_DATA_FORMAT_RESERVED_87', - 88: 'IMG_DATA_FORMAT_RESERVED_88', - 89: 'IMG_DATA_FORMAT_RESERVED_89', - 90: 'IMG_DATA_FORMAT_RESERVED_90', - 91: 'IMG_DATA_FORMAT_RESERVED_91', - 92: 'IMG_DATA_FORMAT_RESERVED_92', - 93: 'IMG_DATA_FORMAT_RESERVED_93', - 94: 'IMG_DATA_FORMAT_RESERVED_94', - 95: 'IMG_DATA_FORMAT_RESERVED_95', - 96: 'IMG_DATA_FORMAT_RESERVED_96', - 97: 'IMG_DATA_FORMAT_RESERVED_97', - 98: 'IMG_DATA_FORMAT_RESERVED_98', - 99: 'IMG_DATA_FORMAT_RESERVED_99', - 100: 'IMG_DATA_FORMAT_RESERVED_100', - 101: 'IMG_DATA_FORMAT_RESERVED_101', - 102: 'IMG_DATA_FORMAT_RESERVED_102', - 103: 'IMG_DATA_FORMAT_RESERVED_103', - 104: 'IMG_DATA_FORMAT_RESERVED_104', - 105: 'IMG_DATA_FORMAT_RESERVED_105', - 106: 'IMG_DATA_FORMAT_RESERVED_106', - 107: 'IMG_DATA_FORMAT_RESERVED_107', - 108: 'IMG_DATA_FORMAT_RESERVED_108', - 109: 'IMG_DATA_FORMAT_RESERVED_109', - 110: 'IMG_DATA_FORMAT_RESERVED_110', - 111: 'IMG_DATA_FORMAT_RESERVED_111', - 112: 'IMG_DATA_FORMAT_RESERVED_112', - 113: 'IMG_DATA_FORMAT_RESERVED_113', - 114: 'IMG_DATA_FORMAT_RESERVED_114', - 115: 'IMG_DATA_FORMAT_RESERVED_115', - 116: 'IMG_DATA_FORMAT_RESERVED_116', - 117: 'IMG_DATA_FORMAT_RESERVED_117', - 118: 'IMG_DATA_FORMAT_RESERVED_118', - 119: 'IMG_DATA_FORMAT_RESERVED_119', - 120: 'IMG_DATA_FORMAT_RESERVED_120', - 121: 'IMG_DATA_FORMAT_RESERVED_121', - 122: 'IMG_DATA_FORMAT_RESERVED_122', - 123: 'IMG_DATA_FORMAT_RESERVED_123', - 124: 'IMG_DATA_FORMAT_RESERVED_124', - 125: 'IMG_DATA_FORMAT_RESERVED_125', - 126: 'IMG_DATA_FORMAT_RESERVED_126', - 127: 'IMG_DATA_FORMAT_RESERVED_127', -} -IMG_DATA_FORMAT_INVALID = 0 -IMG_DATA_FORMAT_8 = 1 -IMG_DATA_FORMAT_16 = 2 -IMG_DATA_FORMAT_8_8 = 3 -IMG_DATA_FORMAT_32 = 4 -IMG_DATA_FORMAT_16_16 = 5 -IMG_DATA_FORMAT_10_11_11 = 6 -IMG_DATA_FORMAT_11_11_10 = 7 -IMG_DATA_FORMAT_10_10_10_2 = 8 -IMG_DATA_FORMAT_2_10_10_10 = 9 -IMG_DATA_FORMAT_8_8_8_8 = 10 -IMG_DATA_FORMAT_32_32 = 11 -IMG_DATA_FORMAT_16_16_16_16 = 12 -IMG_DATA_FORMAT_32_32_32 = 13 -IMG_DATA_FORMAT_32_32_32_32 = 14 -IMG_DATA_FORMAT_RESERVED_15 = 15 -IMG_DATA_FORMAT_5_6_5 = 16 -IMG_DATA_FORMAT_1_5_5_5 = 17 -IMG_DATA_FORMAT_5_5_5_1 = 18 -IMG_DATA_FORMAT_4_4_4_4 = 19 -IMG_DATA_FORMAT_8_24 = 20 -IMG_DATA_FORMAT_24_8 = 21 -IMG_DATA_FORMAT_X24_8_32 = 22 -IMG_DATA_FORMAT_RESERVED_23 = 23 -IMG_DATA_FORMAT_RESERVED_24 = 24 -IMG_DATA_FORMAT_RESERVED_25 = 25 -IMG_DATA_FORMAT_RESERVED_26 = 26 -IMG_DATA_FORMAT_RESERVED_27 = 27 -IMG_DATA_FORMAT_RESERVED_28 = 28 -IMG_DATA_FORMAT_RESERVED_29 = 29 -IMG_DATA_FORMAT_RESERVED_30 = 30 -IMG_DATA_FORMAT_6E4 = 31 -IMG_DATA_FORMAT_GB_GR = 32 -IMG_DATA_FORMAT_BG_RG = 33 -IMG_DATA_FORMAT_5_9_9_9 = 34 -IMG_DATA_FORMAT_BC1 = 35 -IMG_DATA_FORMAT_BC2 = 36 -IMG_DATA_FORMAT_BC3 = 37 -IMG_DATA_FORMAT_BC4 = 38 -IMG_DATA_FORMAT_BC5 = 39 -IMG_DATA_FORMAT_BC6 = 40 -IMG_DATA_FORMAT_BC7 = 41 -IMG_DATA_FORMAT_RESERVED_42 = 42 -IMG_DATA_FORMAT_RESERVED_43 = 43 -IMG_DATA_FORMAT_FMASK8_S2_F1 = 44 -IMG_DATA_FORMAT_FMASK8_S4_F1 = 45 -IMG_DATA_FORMAT_FMASK8_S8_F1 = 46 -IMG_DATA_FORMAT_FMASK8_S2_F2 = 47 -IMG_DATA_FORMAT_FMASK8_S4_F2 = 48 -IMG_DATA_FORMAT_FMASK8_S4_F4 = 49 -IMG_DATA_FORMAT_FMASK16_S16_F1 = 50 -IMG_DATA_FORMAT_FMASK16_S8_F2 = 51 -IMG_DATA_FORMAT_FMASK32_S16_F2 = 52 -IMG_DATA_FORMAT_FMASK32_S8_F4 = 53 -IMG_DATA_FORMAT_FMASK32_S8_F8 = 54 -IMG_DATA_FORMAT_FMASK64_S16_F4 = 55 -IMG_DATA_FORMAT_FMASK64_S16_F8 = 56 -IMG_DATA_FORMAT_4_4 = 57 -IMG_DATA_FORMAT_6_5_5 = 58 -IMG_DATA_FORMAT_1 = 59 -IMG_DATA_FORMAT_1_REVERSED = 60 -IMG_DATA_FORMAT_RESERVED_61 = 61 -IMG_DATA_FORMAT_RESERVED_62 = 62 -IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 -IMG_DATA_FORMAT_RESERVED_75 = 75 -IMG_DATA_FORMAT_MM_8 = 76 -IMG_DATA_FORMAT_MM_8_8 = 77 -IMG_DATA_FORMAT_MM_8_8_8_8 = 78 -IMG_DATA_FORMAT_MM_VYUY8 = 79 -IMG_DATA_FORMAT_MM_10_11_11 = 80 -IMG_DATA_FORMAT_MM_2_10_10_10 = 81 -IMG_DATA_FORMAT_MM_16_16_16_16 = 82 -IMG_DATA_FORMAT_MM_10_IN_16 = 83 -IMG_DATA_FORMAT_MM_10_IN_16_16 = 84 -IMG_DATA_FORMAT_MM_10_IN_16_16_16_16 = 85 -IMG_DATA_FORMAT_RESERVED_86 = 86 -IMG_DATA_FORMAT_RESERVED_87 = 87 -IMG_DATA_FORMAT_RESERVED_88 = 88 -IMG_DATA_FORMAT_RESERVED_89 = 89 -IMG_DATA_FORMAT_RESERVED_90 = 90 -IMG_DATA_FORMAT_RESERVED_91 = 91 -IMG_DATA_FORMAT_RESERVED_92 = 92 -IMG_DATA_FORMAT_RESERVED_93 = 93 -IMG_DATA_FORMAT_RESERVED_94 = 94 -IMG_DATA_FORMAT_RESERVED_95 = 95 -IMG_DATA_FORMAT_RESERVED_96 = 96 -IMG_DATA_FORMAT_RESERVED_97 = 97 -IMG_DATA_FORMAT_RESERVED_98 = 98 -IMG_DATA_FORMAT_RESERVED_99 = 99 -IMG_DATA_FORMAT_RESERVED_100 = 100 -IMG_DATA_FORMAT_RESERVED_101 = 101 -IMG_DATA_FORMAT_RESERVED_102 = 102 -IMG_DATA_FORMAT_RESERVED_103 = 103 -IMG_DATA_FORMAT_RESERVED_104 = 104 -IMG_DATA_FORMAT_RESERVED_105 = 105 -IMG_DATA_FORMAT_RESERVED_106 = 106 -IMG_DATA_FORMAT_RESERVED_107 = 107 -IMG_DATA_FORMAT_RESERVED_108 = 108 -IMG_DATA_FORMAT_RESERVED_109 = 109 -IMG_DATA_FORMAT_RESERVED_110 = 110 -IMG_DATA_FORMAT_RESERVED_111 = 111 -IMG_DATA_FORMAT_RESERVED_112 = 112 -IMG_DATA_FORMAT_RESERVED_113 = 113 -IMG_DATA_FORMAT_RESERVED_114 = 114 -IMG_DATA_FORMAT_RESERVED_115 = 115 -IMG_DATA_FORMAT_RESERVED_116 = 116 -IMG_DATA_FORMAT_RESERVED_117 = 117 -IMG_DATA_FORMAT_RESERVED_118 = 118 -IMG_DATA_FORMAT_RESERVED_119 = 119 -IMG_DATA_FORMAT_RESERVED_120 = 120 -IMG_DATA_FORMAT_RESERVED_121 = 121 -IMG_DATA_FORMAT_RESERVED_122 = 122 -IMG_DATA_FORMAT_RESERVED_123 = 123 -IMG_DATA_FORMAT_RESERVED_124 = 124 -IMG_DATA_FORMAT_RESERVED_125 = 125 -IMG_DATA_FORMAT_RESERVED_126 = 126 -IMG_DATA_FORMAT_RESERVED_127 = 127 -IMG_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'BUF_NUM_FORMAT' -BUF_NUM_FORMAT__enumvalues = { - 0: 'BUF_NUM_FORMAT_UNORM', - 1: 'BUF_NUM_FORMAT_SNORM', - 2: 'BUF_NUM_FORMAT_USCALED', - 3: 'BUF_NUM_FORMAT_SSCALED', - 4: 'BUF_NUM_FORMAT_UINT', - 5: 'BUF_NUM_FORMAT_SINT', - 6: 'BUF_NUM_FORMAT_SNORM_NZ', - 7: 'BUF_NUM_FORMAT_FLOAT', -} -BUF_NUM_FORMAT_UNORM = 0 -BUF_NUM_FORMAT_SNORM = 1 -BUF_NUM_FORMAT_USCALED = 2 -BUF_NUM_FORMAT_SSCALED = 3 -BUF_NUM_FORMAT_UINT = 4 -BUF_NUM_FORMAT_SINT = 5 -BUF_NUM_FORMAT_SNORM_NZ = 6 -BUF_NUM_FORMAT_FLOAT = 7 -BUF_NUM_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT' -IMG_NUM_FORMAT__enumvalues = { - 0: 'IMG_NUM_FORMAT_UNORM', - 1: 'IMG_NUM_FORMAT_SNORM', - 2: 'IMG_NUM_FORMAT_USCALED', - 3: 'IMG_NUM_FORMAT_SSCALED', - 4: 'IMG_NUM_FORMAT_UINT', - 5: 'IMG_NUM_FORMAT_SINT', - 6: 'IMG_NUM_FORMAT_SNORM_NZ', - 7: 'IMG_NUM_FORMAT_FLOAT', - 8: 'IMG_NUM_FORMAT_RESERVED_8', - 9: 'IMG_NUM_FORMAT_SRGB', - 10: 'IMG_NUM_FORMAT_UBNORM', - 11: 'IMG_NUM_FORMAT_UBNORM_NZ', - 12: 'IMG_NUM_FORMAT_UBINT', - 13: 'IMG_NUM_FORMAT_UBSCALED', - 14: 'IMG_NUM_FORMAT_RESERVED_14', - 15: 'IMG_NUM_FORMAT_RESERVED_15', -} -IMG_NUM_FORMAT_UNORM = 0 -IMG_NUM_FORMAT_SNORM = 1 -IMG_NUM_FORMAT_USCALED = 2 -IMG_NUM_FORMAT_SSCALED = 3 -IMG_NUM_FORMAT_UINT = 4 -IMG_NUM_FORMAT_SINT = 5 -IMG_NUM_FORMAT_SNORM_NZ = 6 -IMG_NUM_FORMAT_FLOAT = 7 -IMG_NUM_FORMAT_RESERVED_8 = 8 -IMG_NUM_FORMAT_SRGB = 9 -IMG_NUM_FORMAT_UBNORM = 10 -IMG_NUM_FORMAT_UBNORM_NZ = 11 -IMG_NUM_FORMAT_UBINT = 12 -IMG_NUM_FORMAT_UBSCALED = 13 -IMG_NUM_FORMAT_RESERVED_14 = 14 -IMG_NUM_FORMAT_RESERVED_15 = 15 -IMG_NUM_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IH_PERF_SEL' -IH_PERF_SEL__enumvalues = { - 0: 'IH_PERF_SEL_CYCLE', - 1: 'IH_PERF_SEL_IDLE', - 2: 'IH_PERF_SEL_INPUT_IDLE', - 3: 'IH_PERF_SEL_BUFFER_IDLE', - 4: 'IH_PERF_SEL_RB0_FULL', - 5: 'IH_PERF_SEL_RB0_OVERFLOW', - 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', - 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', - 9: 'IH_PERF_SEL_MC_WR_IDLE', - 10: 'IH_PERF_SEL_MC_WR_COUNT', - 11: 'IH_PERF_SEL_MC_WR_STALL', - 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', - 14: 'IH_PERF_SEL_BIF_LINE0_RISING', - 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', - 16: 'IH_PERF_SEL_RB1_FULL', - 17: 'IH_PERF_SEL_RB1_OVERFLOW', - 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', - 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', - 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', - 21: 'IH_PERF_SEL_RB2_FULL', - 22: 'IH_PERF_SEL_RB2_OVERFLOW', - 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', - 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', - 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', - 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 27: 'IH_PERF_SEL_SELF_IV_VALID', - 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', - 29: 'IH_PERF_SEL_RB0_FULL_VF0', - 30: 'IH_PERF_SEL_RB0_FULL_VF1', - 31: 'IH_PERF_SEL_RB0_FULL_VF2', - 32: 'IH_PERF_SEL_RB0_FULL_VF3', - 33: 'IH_PERF_SEL_RB0_FULL_VF4', - 34: 'IH_PERF_SEL_RB0_FULL_VF5', - 35: 'IH_PERF_SEL_RB0_FULL_VF6', - 36: 'IH_PERF_SEL_RB0_FULL_VF7', - 37: 'IH_PERF_SEL_RB0_FULL_VF8', - 38: 'IH_PERF_SEL_RB0_FULL_VF9', - 39: 'IH_PERF_SEL_RB0_FULL_VF10', - 40: 'IH_PERF_SEL_RB0_FULL_VF11', - 41: 'IH_PERF_SEL_RB0_FULL_VF12', - 42: 'IH_PERF_SEL_RB0_FULL_VF13', - 43: 'IH_PERF_SEL_RB0_FULL_VF14', - 44: 'IH_PERF_SEL_RB0_FULL_VF15', - 45: 'IH_PERF_SEL_RB0_FULL_VF16', - 46: 'IH_PERF_SEL_RB0_FULL_VF17', - 47: 'IH_PERF_SEL_RB0_FULL_VF18', - 48: 'IH_PERF_SEL_RB0_FULL_VF19', - 49: 'IH_PERF_SEL_RB0_FULL_VF20', - 50: 'IH_PERF_SEL_RB0_FULL_VF21', - 51: 'IH_PERF_SEL_RB0_FULL_VF22', - 52: 'IH_PERF_SEL_RB0_FULL_VF23', - 53: 'IH_PERF_SEL_RB0_FULL_VF24', - 54: 'IH_PERF_SEL_RB0_FULL_VF25', - 55: 'IH_PERF_SEL_RB0_FULL_VF26', - 56: 'IH_PERF_SEL_RB0_FULL_VF27', - 57: 'IH_PERF_SEL_RB0_FULL_VF28', - 58: 'IH_PERF_SEL_RB0_FULL_VF29', - 59: 'IH_PERF_SEL_RB0_FULL_VF30', - 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', - 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 62: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', - 63: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 64: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', - 65: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 66: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', - 67: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 68: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', - 69: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 70: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', - 71: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 72: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', - 73: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 74: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', - 75: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 76: 'IH_PERF_SEL_RB0_OVERFLOW_VF16', - 77: 'IH_PERF_SEL_RB0_OVERFLOW_VF17', - 78: 'IH_PERF_SEL_RB0_OVERFLOW_VF18', - 79: 'IH_PERF_SEL_RB0_OVERFLOW_VF19', - 80: 'IH_PERF_SEL_RB0_OVERFLOW_VF20', - 81: 'IH_PERF_SEL_RB0_OVERFLOW_VF21', - 82: 'IH_PERF_SEL_RB0_OVERFLOW_VF22', - 83: 'IH_PERF_SEL_RB0_OVERFLOW_VF23', - 84: 'IH_PERF_SEL_RB0_OVERFLOW_VF24', - 85: 'IH_PERF_SEL_RB0_OVERFLOW_VF25', - 86: 'IH_PERF_SEL_RB0_OVERFLOW_VF26', - 87: 'IH_PERF_SEL_RB0_OVERFLOW_VF27', - 88: 'IH_PERF_SEL_RB0_OVERFLOW_VF28', - 89: 'IH_PERF_SEL_RB0_OVERFLOW_VF29', - 90: 'IH_PERF_SEL_RB0_OVERFLOW_VF30', - 91: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 92: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 93: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 94: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 95: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 96: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 97: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 98: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 99: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 100: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', - 101: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 102: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 103: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 104: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 105: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 106: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 107: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16', - 108: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17', - 109: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18', - 110: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19', - 111: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20', - 112: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21', - 113: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22', - 114: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23', - 115: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24', - 116: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25', - 117: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26', - 118: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27', - 119: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28', - 120: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29', - 121: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30', - 122: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', - 123: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 124: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 125: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', - 126: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 127: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', - 128: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 129: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', - 130: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 131: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', - 132: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 133: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 134: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 135: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 136: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 137: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', - 138: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF16', - 139: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF17', - 140: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF18', - 141: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF19', - 142: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF20', - 143: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF21', - 144: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF22', - 145: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF23', - 146: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF24', - 147: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF25', - 148: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF26', - 149: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF27', - 150: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF28', - 151: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF29', - 152: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF30', - 153: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 154: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', - 155: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 156: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', - 157: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 158: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', - 159: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 160: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', - 161: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 162: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', - 163: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 164: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 165: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 166: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 167: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 168: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', - 169: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF16', - 170: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF17', - 171: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF18', - 172: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF19', - 173: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF20', - 174: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF21', - 175: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF22', - 176: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF23', - 177: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF24', - 178: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF25', - 179: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF26', - 180: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF27', - 181: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF28', - 182: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF29', - 183: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF30', - 184: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 185: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 186: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 187: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 188: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 189: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 190: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 191: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 192: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 193: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 194: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 195: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 196: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 197: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 198: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 199: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 200: 'IH_PERF_SEL_BIF_LINE0_RISING_VF16', - 201: 'IH_PERF_SEL_BIF_LINE0_RISING_VF17', - 202: 'IH_PERF_SEL_BIF_LINE0_RISING_VF18', - 203: 'IH_PERF_SEL_BIF_LINE0_RISING_VF19', - 204: 'IH_PERF_SEL_BIF_LINE0_RISING_VF20', - 205: 'IH_PERF_SEL_BIF_LINE0_RISING_VF21', - 206: 'IH_PERF_SEL_BIF_LINE0_RISING_VF22', - 207: 'IH_PERF_SEL_BIF_LINE0_RISING_VF23', - 208: 'IH_PERF_SEL_BIF_LINE0_RISING_VF24', - 209: 'IH_PERF_SEL_BIF_LINE0_RISING_VF25', - 210: 'IH_PERF_SEL_BIF_LINE0_RISING_VF26', - 211: 'IH_PERF_SEL_BIF_LINE0_RISING_VF27', - 212: 'IH_PERF_SEL_BIF_LINE0_RISING_VF28', - 213: 'IH_PERF_SEL_BIF_LINE0_RISING_VF29', - 214: 'IH_PERF_SEL_BIF_LINE0_RISING_VF30', - 215: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 216: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 217: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 218: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 219: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 220: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 221: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 222: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 223: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 224: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 225: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 226: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 227: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 228: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 229: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 230: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 231: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF16', - 232: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF17', - 233: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF18', - 234: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF19', - 235: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF20', - 236: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF21', - 237: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF22', - 238: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF23', - 239: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF24', - 240: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF25', - 241: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF26', - 242: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF27', - 243: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF28', - 244: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF29', - 245: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF30', - 246: 'IH_PERF_SEL_CLIENT0_INT', - 247: 'IH_PERF_SEL_CLIENT1_INT', - 248: 'IH_PERF_SEL_CLIENT2_INT', - 249: 'IH_PERF_SEL_CLIENT3_INT', - 250: 'IH_PERF_SEL_CLIENT4_INT', - 251: 'IH_PERF_SEL_CLIENT5_INT', - 252: 'IH_PERF_SEL_CLIENT6_INT', - 253: 'IH_PERF_SEL_CLIENT7_INT', - 254: 'IH_PERF_SEL_CLIENT8_INT', - 255: 'IH_PERF_SEL_CLIENT9_INT', - 256: 'IH_PERF_SEL_CLIENT10_INT', - 257: 'IH_PERF_SEL_CLIENT11_INT', - 258: 'IH_PERF_SEL_CLIENT12_INT', - 259: 'IH_PERF_SEL_CLIENT13_INT', - 260: 'IH_PERF_SEL_CLIENT14_INT', - 261: 'IH_PERF_SEL_CLIENT15_INT', - 262: 'IH_PERF_SEL_CLIENT16_INT', - 263: 'IH_PERF_SEL_CLIENT17_INT', - 264: 'IH_PERF_SEL_CLIENT18_INT', - 265: 'IH_PERF_SEL_CLIENT19_INT', - 266: 'IH_PERF_SEL_CLIENT20_INT', - 267: 'IH_PERF_SEL_CLIENT21_INT', - 268: 'IH_PERF_SEL_CLIENT22_INT', - 269: 'IH_PERF_SEL_CLIENT23_INT', - 270: 'IH_PERF_SEL_CLIENT24_INT', - 271: 'IH_PERF_SEL_CLIENT25_INT', - 272: 'IH_PERF_SEL_CLIENT26_INT', - 273: 'IH_PERF_SEL_CLIENT27_INT', - 274: 'IH_PERF_SEL_CLIENT28_INT', - 275: 'IH_PERF_SEL_CLIENT29_INT', - 276: 'IH_PERF_SEL_CLIENT30_INT', - 277: 'IH_PERF_SEL_CLIENT31_INT', - 278: 'IH_PERF_SEL_RB1_FULL_VF0', - 279: 'IH_PERF_SEL_RB1_FULL_VF1', - 280: 'IH_PERF_SEL_RB1_FULL_VF2', - 281: 'IH_PERF_SEL_RB1_FULL_VF3', - 282: 'IH_PERF_SEL_RB1_FULL_VF4', - 283: 'IH_PERF_SEL_RB1_FULL_VF5', - 284: 'IH_PERF_SEL_RB1_FULL_VF6', - 285: 'IH_PERF_SEL_RB1_FULL_VF7', - 286: 'IH_PERF_SEL_RB1_FULL_VF8', - 287: 'IH_PERF_SEL_RB1_FULL_VF9', - 288: 'IH_PERF_SEL_RB1_FULL_VF10', - 289: 'IH_PERF_SEL_RB1_FULL_VF11', - 290: 'IH_PERF_SEL_RB1_FULL_VF12', - 291: 'IH_PERF_SEL_RB1_FULL_VF13', - 292: 'IH_PERF_SEL_RB1_FULL_VF14', - 293: 'IH_PERF_SEL_RB1_FULL_VF15', - 294: 'IH_PERF_SEL_RB1_FULL_VF16', - 295: 'IH_PERF_SEL_RB1_FULL_VF17', - 296: 'IH_PERF_SEL_RB1_FULL_VF18', - 297: 'IH_PERF_SEL_RB1_FULL_VF19', - 298: 'IH_PERF_SEL_RB1_FULL_VF20', - 299: 'IH_PERF_SEL_RB1_FULL_VF21', - 300: 'IH_PERF_SEL_RB1_FULL_VF22', - 301: 'IH_PERF_SEL_RB1_FULL_VF23', - 302: 'IH_PERF_SEL_RB1_FULL_VF24', - 303: 'IH_PERF_SEL_RB1_FULL_VF25', - 304: 'IH_PERF_SEL_RB1_FULL_VF26', - 305: 'IH_PERF_SEL_RB1_FULL_VF27', - 306: 'IH_PERF_SEL_RB1_FULL_VF28', - 307: 'IH_PERF_SEL_RB1_FULL_VF29', - 308: 'IH_PERF_SEL_RB1_FULL_VF30', - 309: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', - 310: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 311: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', - 312: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 313: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 314: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 315: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 316: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 317: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 318: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 319: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', - 320: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 321: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', - 322: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 323: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', - 324: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 325: 'IH_PERF_SEL_RB1_OVERFLOW_VF16', - 326: 'IH_PERF_SEL_RB1_OVERFLOW_VF17', - 327: 'IH_PERF_SEL_RB1_OVERFLOW_VF18', - 328: 'IH_PERF_SEL_RB1_OVERFLOW_VF19', - 329: 'IH_PERF_SEL_RB1_OVERFLOW_VF20', - 330: 'IH_PERF_SEL_RB1_OVERFLOW_VF21', - 331: 'IH_PERF_SEL_RB1_OVERFLOW_VF22', - 332: 'IH_PERF_SEL_RB1_OVERFLOW_VF23', - 333: 'IH_PERF_SEL_RB1_OVERFLOW_VF24', - 334: 'IH_PERF_SEL_RB1_OVERFLOW_VF25', - 335: 'IH_PERF_SEL_RB1_OVERFLOW_VF26', - 336: 'IH_PERF_SEL_RB1_OVERFLOW_VF27', - 337: 'IH_PERF_SEL_RB1_OVERFLOW_VF28', - 338: 'IH_PERF_SEL_RB1_OVERFLOW_VF29', - 339: 'IH_PERF_SEL_RB1_OVERFLOW_VF30', - 340: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', - 341: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 342: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 343: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', - 344: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 345: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', - 346: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 347: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', - 348: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 349: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', - 350: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 351: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 352: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 353: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 354: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 355: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', - 356: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF16', - 357: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF17', - 358: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF18', - 359: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF19', - 360: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF20', - 361: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF21', - 362: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF22', - 363: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF23', - 364: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF24', - 365: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF25', - 366: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF26', - 367: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF27', - 368: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF28', - 369: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF29', - 370: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF30', - 371: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 372: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 373: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 374: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', - 375: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 376: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', - 377: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 378: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', - 379: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 380: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', - 381: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 382: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 383: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 384: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 385: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 386: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', - 387: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF16', - 388: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF17', - 389: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF18', - 390: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF19', - 391: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF20', - 392: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF21', - 393: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF22', - 394: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF23', - 395: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF24', - 396: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF25', - 397: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF26', - 398: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF27', - 399: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF28', - 400: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF29', - 401: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF30', - 402: 'IH_PERF_SEL_RB2_FULL_VF0', - 403: 'IH_PERF_SEL_RB2_FULL_VF1', - 404: 'IH_PERF_SEL_RB2_FULL_VF2', - 405: 'IH_PERF_SEL_RB2_FULL_VF3', - 406: 'IH_PERF_SEL_RB2_FULL_VF4', - 407: 'IH_PERF_SEL_RB2_FULL_VF5', - 408: 'IH_PERF_SEL_RB2_FULL_VF6', - 409: 'IH_PERF_SEL_RB2_FULL_VF7', - 410: 'IH_PERF_SEL_RB2_FULL_VF8', - 411: 'IH_PERF_SEL_RB2_FULL_VF9', - 412: 'IH_PERF_SEL_RB2_FULL_VF10', - 413: 'IH_PERF_SEL_RB2_FULL_VF11', - 414: 'IH_PERF_SEL_RB2_FULL_VF12', - 415: 'IH_PERF_SEL_RB2_FULL_VF13', - 416: 'IH_PERF_SEL_RB2_FULL_VF14', - 417: 'IH_PERF_SEL_RB2_FULL_VF15', - 418: 'IH_PERF_SEL_RB2_FULL_VF16', - 419: 'IH_PERF_SEL_RB2_FULL_VF17', - 420: 'IH_PERF_SEL_RB2_FULL_VF18', - 421: 'IH_PERF_SEL_RB2_FULL_VF19', - 422: 'IH_PERF_SEL_RB2_FULL_VF20', - 423: 'IH_PERF_SEL_RB2_FULL_VF21', - 424: 'IH_PERF_SEL_RB2_FULL_VF22', - 425: 'IH_PERF_SEL_RB2_FULL_VF23', - 426: 'IH_PERF_SEL_RB2_FULL_VF24', - 427: 'IH_PERF_SEL_RB2_FULL_VF25', - 428: 'IH_PERF_SEL_RB2_FULL_VF26', - 429: 'IH_PERF_SEL_RB2_FULL_VF27', - 430: 'IH_PERF_SEL_RB2_FULL_VF28', - 431: 'IH_PERF_SEL_RB2_FULL_VF29', - 432: 'IH_PERF_SEL_RB2_FULL_VF30', - 433: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', - 434: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 435: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', - 436: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 437: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 438: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 439: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 440: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 441: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 442: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 443: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', - 444: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 445: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', - 446: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 447: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', - 448: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 449: 'IH_PERF_SEL_RB2_OVERFLOW_VF16', - 450: 'IH_PERF_SEL_RB2_OVERFLOW_VF17', - 451: 'IH_PERF_SEL_RB2_OVERFLOW_VF18', - 452: 'IH_PERF_SEL_RB2_OVERFLOW_VF19', - 453: 'IH_PERF_SEL_RB2_OVERFLOW_VF20', - 454: 'IH_PERF_SEL_RB2_OVERFLOW_VF21', - 455: 'IH_PERF_SEL_RB2_OVERFLOW_VF22', - 456: 'IH_PERF_SEL_RB2_OVERFLOW_VF23', - 457: 'IH_PERF_SEL_RB2_OVERFLOW_VF24', - 458: 'IH_PERF_SEL_RB2_OVERFLOW_VF25', - 459: 'IH_PERF_SEL_RB2_OVERFLOW_VF26', - 460: 'IH_PERF_SEL_RB2_OVERFLOW_VF27', - 461: 'IH_PERF_SEL_RB2_OVERFLOW_VF28', - 462: 'IH_PERF_SEL_RB2_OVERFLOW_VF29', - 463: 'IH_PERF_SEL_RB2_OVERFLOW_VF30', - 464: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', - 465: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 466: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 467: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', - 468: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 469: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', - 470: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 471: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', - 472: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 473: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', - 474: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 475: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 476: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 477: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 478: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 479: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', - 480: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF16', - 481: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF17', - 482: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF18', - 483: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF19', - 484: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF20', - 485: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF21', - 486: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF22', - 487: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF23', - 488: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF24', - 489: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF25', - 490: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF26', - 491: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF27', - 492: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF28', - 493: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF29', - 494: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF30', - 495: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 496: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 497: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 498: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', - 499: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 500: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', - 501: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 502: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', - 503: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 504: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', - 505: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 506: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 507: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 508: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 509: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 510: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', - 511: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF16', - 512: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF17', - 513: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF18', - 514: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF19', - 515: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF20', - 516: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF21', - 517: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF22', - 518: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF23', - 519: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF24', - 520: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF25', - 521: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF26', - 522: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF27', - 523: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF28', - 524: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF29', - 525: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF30', - 526: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 527: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 528: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 529: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 530: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 531: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 532: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 533: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 534: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 535: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 536: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', - 537: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 538: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 539: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 540: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 541: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 542: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 543: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16', - 544: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17', - 545: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18', - 546: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19', - 547: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20', - 548: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21', - 549: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22', - 550: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23', - 551: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24', - 552: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25', - 553: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26', - 554: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27', - 555: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28', - 556: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29', - 557: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30', - 558: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 559: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 560: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 561: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 562: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 563: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 564: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 565: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 566: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 567: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 568: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', - 569: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 570: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 571: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 572: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 573: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 574: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 575: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16', - 576: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17', - 577: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18', - 578: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19', - 579: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20', - 580: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21', - 581: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22', - 582: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23', - 583: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24', - 584: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25', - 585: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26', - 586: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27', - 587: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28', - 588: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29', - 589: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30', - 590: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 591: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 592: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 593: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 594: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 595: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 596: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 597: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 598: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 599: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 600: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', - 601: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 602: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 603: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 604: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 605: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 606: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 607: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16', - 608: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17', - 609: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18', - 610: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19', - 611: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20', - 612: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21', - 613: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22', - 614: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23', - 615: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24', - 616: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25', - 617: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26', - 618: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27', - 619: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28', - 620: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29', - 621: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30', - 622: 'IH_PERF_SEL_RB0_LOAD_RPTR', - 623: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', - 624: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', - 625: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 626: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', - 627: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 628: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', - 629: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 630: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', - 631: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 632: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', - 633: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 634: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 635: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 636: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 637: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 638: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', - 639: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF16', - 640: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF17', - 641: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF18', - 642: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF19', - 643: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF20', - 644: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF21', - 645: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF22', - 646: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF23', - 647: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF24', - 648: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF25', - 649: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF26', - 650: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF27', - 651: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF28', - 652: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF29', - 653: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF30', - 654: 'IH_PERF_SEL_RB1_LOAD_RPTR', - 655: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', - 656: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', - 657: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 658: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', - 659: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 660: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', - 661: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 662: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', - 663: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 664: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', - 665: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 666: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 667: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 668: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 669: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 670: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', - 671: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF16', - 672: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF17', - 673: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF18', - 674: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF19', - 675: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF20', - 676: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF21', - 677: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF22', - 678: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF23', - 679: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF24', - 680: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF25', - 681: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF26', - 682: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF27', - 683: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF28', - 684: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF29', - 685: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF30', - 686: 'IH_PERF_SEL_RB2_LOAD_RPTR', - 687: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', - 688: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', - 689: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 690: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', - 691: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 692: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', - 693: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 694: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', - 695: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 696: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', - 697: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 698: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 699: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 700: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 701: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 702: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', - 703: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF16', - 704: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF17', - 705: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF18', - 706: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF19', - 707: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF20', - 708: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF21', - 709: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF22', - 710: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF23', - 711: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF24', - 712: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF25', - 713: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF26', - 714: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF27', - 715: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF28', - 716: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF29', - 717: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF30', -} -IH_PERF_SEL_CYCLE = 0 -IH_PERF_SEL_IDLE = 1 -IH_PERF_SEL_INPUT_IDLE = 2 -IH_PERF_SEL_BUFFER_IDLE = 3 -IH_PERF_SEL_RB0_FULL = 4 -IH_PERF_SEL_RB0_OVERFLOW = 5 -IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 -IH_PERF_SEL_RB0_WPTR_WRAP = 7 -IH_PERF_SEL_RB0_RPTR_WRAP = 8 -IH_PERF_SEL_MC_WR_IDLE = 9 -IH_PERF_SEL_MC_WR_COUNT = 10 -IH_PERF_SEL_MC_WR_STALL = 11 -IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 -IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 -IH_PERF_SEL_BIF_LINE0_RISING = 14 -IH_PERF_SEL_BIF_LINE0_FALLING = 15 -IH_PERF_SEL_RB1_FULL = 16 -IH_PERF_SEL_RB1_OVERFLOW = 17 -IH_PERF_SEL_COOKIE_REC_ERROR = 18 -IH_PERF_SEL_RB1_WPTR_WRAP = 19 -IH_PERF_SEL_RB1_RPTR_WRAP = 20 -IH_PERF_SEL_RB2_FULL = 21 -IH_PERF_SEL_RB2_OVERFLOW = 22 -IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 -IH_PERF_SEL_RB2_WPTR_WRAP = 24 -IH_PERF_SEL_RB2_RPTR_WRAP = 25 -IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 -IH_PERF_SEL_SELF_IV_VALID = 27 -IH_PERF_SEL_BUFFER_FIFO_FULL = 28 -IH_PERF_SEL_RB0_FULL_VF0 = 29 -IH_PERF_SEL_RB0_FULL_VF1 = 30 -IH_PERF_SEL_RB0_FULL_VF2 = 31 -IH_PERF_SEL_RB0_FULL_VF3 = 32 -IH_PERF_SEL_RB0_FULL_VF4 = 33 -IH_PERF_SEL_RB0_FULL_VF5 = 34 -IH_PERF_SEL_RB0_FULL_VF6 = 35 -IH_PERF_SEL_RB0_FULL_VF7 = 36 -IH_PERF_SEL_RB0_FULL_VF8 = 37 -IH_PERF_SEL_RB0_FULL_VF9 = 38 -IH_PERF_SEL_RB0_FULL_VF10 = 39 -IH_PERF_SEL_RB0_FULL_VF11 = 40 -IH_PERF_SEL_RB0_FULL_VF12 = 41 -IH_PERF_SEL_RB0_FULL_VF13 = 42 -IH_PERF_SEL_RB0_FULL_VF14 = 43 -IH_PERF_SEL_RB0_FULL_VF15 = 44 -IH_PERF_SEL_RB0_FULL_VF16 = 45 -IH_PERF_SEL_RB0_FULL_VF17 = 46 -IH_PERF_SEL_RB0_FULL_VF18 = 47 -IH_PERF_SEL_RB0_FULL_VF19 = 48 -IH_PERF_SEL_RB0_FULL_VF20 = 49 -IH_PERF_SEL_RB0_FULL_VF21 = 50 -IH_PERF_SEL_RB0_FULL_VF22 = 51 -IH_PERF_SEL_RB0_FULL_VF23 = 52 -IH_PERF_SEL_RB0_FULL_VF24 = 53 -IH_PERF_SEL_RB0_FULL_VF25 = 54 -IH_PERF_SEL_RB0_FULL_VF26 = 55 -IH_PERF_SEL_RB0_FULL_VF27 = 56 -IH_PERF_SEL_RB0_FULL_VF28 = 57 -IH_PERF_SEL_RB0_FULL_VF29 = 58 -IH_PERF_SEL_RB0_FULL_VF30 = 59 -IH_PERF_SEL_RB0_OVERFLOW_VF0 = 60 -IH_PERF_SEL_RB0_OVERFLOW_VF1 = 61 -IH_PERF_SEL_RB0_OVERFLOW_VF2 = 62 -IH_PERF_SEL_RB0_OVERFLOW_VF3 = 63 -IH_PERF_SEL_RB0_OVERFLOW_VF4 = 64 -IH_PERF_SEL_RB0_OVERFLOW_VF5 = 65 -IH_PERF_SEL_RB0_OVERFLOW_VF6 = 66 -IH_PERF_SEL_RB0_OVERFLOW_VF7 = 67 -IH_PERF_SEL_RB0_OVERFLOW_VF8 = 68 -IH_PERF_SEL_RB0_OVERFLOW_VF9 = 69 -IH_PERF_SEL_RB0_OVERFLOW_VF10 = 70 -IH_PERF_SEL_RB0_OVERFLOW_VF11 = 71 -IH_PERF_SEL_RB0_OVERFLOW_VF12 = 72 -IH_PERF_SEL_RB0_OVERFLOW_VF13 = 73 -IH_PERF_SEL_RB0_OVERFLOW_VF14 = 74 -IH_PERF_SEL_RB0_OVERFLOW_VF15 = 75 -IH_PERF_SEL_RB0_OVERFLOW_VF16 = 76 -IH_PERF_SEL_RB0_OVERFLOW_VF17 = 77 -IH_PERF_SEL_RB0_OVERFLOW_VF18 = 78 -IH_PERF_SEL_RB0_OVERFLOW_VF19 = 79 -IH_PERF_SEL_RB0_OVERFLOW_VF20 = 80 -IH_PERF_SEL_RB0_OVERFLOW_VF21 = 81 -IH_PERF_SEL_RB0_OVERFLOW_VF22 = 82 -IH_PERF_SEL_RB0_OVERFLOW_VF23 = 83 -IH_PERF_SEL_RB0_OVERFLOW_VF24 = 84 -IH_PERF_SEL_RB0_OVERFLOW_VF25 = 85 -IH_PERF_SEL_RB0_OVERFLOW_VF26 = 86 -IH_PERF_SEL_RB0_OVERFLOW_VF27 = 87 -IH_PERF_SEL_RB0_OVERFLOW_VF28 = 88 -IH_PERF_SEL_RB0_OVERFLOW_VF29 = 89 -IH_PERF_SEL_RB0_OVERFLOW_VF30 = 90 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 91 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 92 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 93 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 94 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 95 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 96 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 97 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 98 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 99 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 100 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 101 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 102 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 103 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 104 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 105 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 106 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16 = 107 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17 = 108 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18 = 109 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19 = 110 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20 = 111 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21 = 112 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22 = 113 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23 = 114 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24 = 115 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25 = 116 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26 = 117 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27 = 118 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28 = 119 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29 = 120 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30 = 121 -IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 122 -IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 123 -IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 124 -IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 125 -IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 126 -IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 127 -IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 128 -IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 129 -IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 130 -IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 131 -IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 132 -IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 133 -IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 134 -IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 135 -IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 136 -IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 137 -IH_PERF_SEL_RB0_WPTR_WRAP_VF16 = 138 -IH_PERF_SEL_RB0_WPTR_WRAP_VF17 = 139 -IH_PERF_SEL_RB0_WPTR_WRAP_VF18 = 140 -IH_PERF_SEL_RB0_WPTR_WRAP_VF19 = 141 -IH_PERF_SEL_RB0_WPTR_WRAP_VF20 = 142 -IH_PERF_SEL_RB0_WPTR_WRAP_VF21 = 143 -IH_PERF_SEL_RB0_WPTR_WRAP_VF22 = 144 -IH_PERF_SEL_RB0_WPTR_WRAP_VF23 = 145 -IH_PERF_SEL_RB0_WPTR_WRAP_VF24 = 146 -IH_PERF_SEL_RB0_WPTR_WRAP_VF25 = 147 -IH_PERF_SEL_RB0_WPTR_WRAP_VF26 = 148 -IH_PERF_SEL_RB0_WPTR_WRAP_VF27 = 149 -IH_PERF_SEL_RB0_WPTR_WRAP_VF28 = 150 -IH_PERF_SEL_RB0_WPTR_WRAP_VF29 = 151 -IH_PERF_SEL_RB0_WPTR_WRAP_VF30 = 152 -IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 153 -IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 154 -IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 155 -IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 156 -IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 157 -IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 158 -IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 159 -IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 160 -IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 161 -IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 162 -IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 163 -IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 164 -IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 165 -IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 166 -IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 167 -IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 168 -IH_PERF_SEL_RB0_RPTR_WRAP_VF16 = 169 -IH_PERF_SEL_RB0_RPTR_WRAP_VF17 = 170 -IH_PERF_SEL_RB0_RPTR_WRAP_VF18 = 171 -IH_PERF_SEL_RB0_RPTR_WRAP_VF19 = 172 -IH_PERF_SEL_RB0_RPTR_WRAP_VF20 = 173 -IH_PERF_SEL_RB0_RPTR_WRAP_VF21 = 174 -IH_PERF_SEL_RB0_RPTR_WRAP_VF22 = 175 -IH_PERF_SEL_RB0_RPTR_WRAP_VF23 = 176 -IH_PERF_SEL_RB0_RPTR_WRAP_VF24 = 177 -IH_PERF_SEL_RB0_RPTR_WRAP_VF25 = 178 -IH_PERF_SEL_RB0_RPTR_WRAP_VF26 = 179 -IH_PERF_SEL_RB0_RPTR_WRAP_VF27 = 180 -IH_PERF_SEL_RB0_RPTR_WRAP_VF28 = 181 -IH_PERF_SEL_RB0_RPTR_WRAP_VF29 = 182 -IH_PERF_SEL_RB0_RPTR_WRAP_VF30 = 183 -IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 184 -IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 185 -IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 186 -IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 187 -IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 188 -IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 189 -IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 190 -IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 191 -IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 192 -IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 193 -IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 194 -IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 195 -IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 196 -IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 197 -IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 198 -IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 199 -IH_PERF_SEL_BIF_LINE0_RISING_VF16 = 200 -IH_PERF_SEL_BIF_LINE0_RISING_VF17 = 201 -IH_PERF_SEL_BIF_LINE0_RISING_VF18 = 202 -IH_PERF_SEL_BIF_LINE0_RISING_VF19 = 203 -IH_PERF_SEL_BIF_LINE0_RISING_VF20 = 204 -IH_PERF_SEL_BIF_LINE0_RISING_VF21 = 205 -IH_PERF_SEL_BIF_LINE0_RISING_VF22 = 206 -IH_PERF_SEL_BIF_LINE0_RISING_VF23 = 207 -IH_PERF_SEL_BIF_LINE0_RISING_VF24 = 208 -IH_PERF_SEL_BIF_LINE0_RISING_VF25 = 209 -IH_PERF_SEL_BIF_LINE0_RISING_VF26 = 210 -IH_PERF_SEL_BIF_LINE0_RISING_VF27 = 211 -IH_PERF_SEL_BIF_LINE0_RISING_VF28 = 212 -IH_PERF_SEL_BIF_LINE0_RISING_VF29 = 213 -IH_PERF_SEL_BIF_LINE0_RISING_VF30 = 214 -IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 215 -IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 216 -IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 217 -IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 218 -IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 219 -IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 220 -IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 221 -IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 222 -IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 223 -IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 224 -IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 225 -IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 226 -IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 227 -IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 228 -IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 229 -IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 230 -IH_PERF_SEL_BIF_LINE0_FALLING_VF16 = 231 -IH_PERF_SEL_BIF_LINE0_FALLING_VF17 = 232 -IH_PERF_SEL_BIF_LINE0_FALLING_VF18 = 233 -IH_PERF_SEL_BIF_LINE0_FALLING_VF19 = 234 -IH_PERF_SEL_BIF_LINE0_FALLING_VF20 = 235 -IH_PERF_SEL_BIF_LINE0_FALLING_VF21 = 236 -IH_PERF_SEL_BIF_LINE0_FALLING_VF22 = 237 -IH_PERF_SEL_BIF_LINE0_FALLING_VF23 = 238 -IH_PERF_SEL_BIF_LINE0_FALLING_VF24 = 239 -IH_PERF_SEL_BIF_LINE0_FALLING_VF25 = 240 -IH_PERF_SEL_BIF_LINE0_FALLING_VF26 = 241 -IH_PERF_SEL_BIF_LINE0_FALLING_VF27 = 242 -IH_PERF_SEL_BIF_LINE0_FALLING_VF28 = 243 -IH_PERF_SEL_BIF_LINE0_FALLING_VF29 = 244 -IH_PERF_SEL_BIF_LINE0_FALLING_VF30 = 245 -IH_PERF_SEL_CLIENT0_INT = 246 -IH_PERF_SEL_CLIENT1_INT = 247 -IH_PERF_SEL_CLIENT2_INT = 248 -IH_PERF_SEL_CLIENT3_INT = 249 -IH_PERF_SEL_CLIENT4_INT = 250 -IH_PERF_SEL_CLIENT5_INT = 251 -IH_PERF_SEL_CLIENT6_INT = 252 -IH_PERF_SEL_CLIENT7_INT = 253 -IH_PERF_SEL_CLIENT8_INT = 254 -IH_PERF_SEL_CLIENT9_INT = 255 -IH_PERF_SEL_CLIENT10_INT = 256 -IH_PERF_SEL_CLIENT11_INT = 257 -IH_PERF_SEL_CLIENT12_INT = 258 -IH_PERF_SEL_CLIENT13_INT = 259 -IH_PERF_SEL_CLIENT14_INT = 260 -IH_PERF_SEL_CLIENT15_INT = 261 -IH_PERF_SEL_CLIENT16_INT = 262 -IH_PERF_SEL_CLIENT17_INT = 263 -IH_PERF_SEL_CLIENT18_INT = 264 -IH_PERF_SEL_CLIENT19_INT = 265 -IH_PERF_SEL_CLIENT20_INT = 266 -IH_PERF_SEL_CLIENT21_INT = 267 -IH_PERF_SEL_CLIENT22_INT = 268 -IH_PERF_SEL_CLIENT23_INT = 269 -IH_PERF_SEL_CLIENT24_INT = 270 -IH_PERF_SEL_CLIENT25_INT = 271 -IH_PERF_SEL_CLIENT26_INT = 272 -IH_PERF_SEL_CLIENT27_INT = 273 -IH_PERF_SEL_CLIENT28_INT = 274 -IH_PERF_SEL_CLIENT29_INT = 275 -IH_PERF_SEL_CLIENT30_INT = 276 -IH_PERF_SEL_CLIENT31_INT = 277 -IH_PERF_SEL_RB1_FULL_VF0 = 278 -IH_PERF_SEL_RB1_FULL_VF1 = 279 -IH_PERF_SEL_RB1_FULL_VF2 = 280 -IH_PERF_SEL_RB1_FULL_VF3 = 281 -IH_PERF_SEL_RB1_FULL_VF4 = 282 -IH_PERF_SEL_RB1_FULL_VF5 = 283 -IH_PERF_SEL_RB1_FULL_VF6 = 284 -IH_PERF_SEL_RB1_FULL_VF7 = 285 -IH_PERF_SEL_RB1_FULL_VF8 = 286 -IH_PERF_SEL_RB1_FULL_VF9 = 287 -IH_PERF_SEL_RB1_FULL_VF10 = 288 -IH_PERF_SEL_RB1_FULL_VF11 = 289 -IH_PERF_SEL_RB1_FULL_VF12 = 290 -IH_PERF_SEL_RB1_FULL_VF13 = 291 -IH_PERF_SEL_RB1_FULL_VF14 = 292 -IH_PERF_SEL_RB1_FULL_VF15 = 293 -IH_PERF_SEL_RB1_FULL_VF16 = 294 -IH_PERF_SEL_RB1_FULL_VF17 = 295 -IH_PERF_SEL_RB1_FULL_VF18 = 296 -IH_PERF_SEL_RB1_FULL_VF19 = 297 -IH_PERF_SEL_RB1_FULL_VF20 = 298 -IH_PERF_SEL_RB1_FULL_VF21 = 299 -IH_PERF_SEL_RB1_FULL_VF22 = 300 -IH_PERF_SEL_RB1_FULL_VF23 = 301 -IH_PERF_SEL_RB1_FULL_VF24 = 302 -IH_PERF_SEL_RB1_FULL_VF25 = 303 -IH_PERF_SEL_RB1_FULL_VF26 = 304 -IH_PERF_SEL_RB1_FULL_VF27 = 305 -IH_PERF_SEL_RB1_FULL_VF28 = 306 -IH_PERF_SEL_RB1_FULL_VF29 = 307 -IH_PERF_SEL_RB1_FULL_VF30 = 308 -IH_PERF_SEL_RB1_OVERFLOW_VF0 = 309 -IH_PERF_SEL_RB1_OVERFLOW_VF1 = 310 -IH_PERF_SEL_RB1_OVERFLOW_VF2 = 311 -IH_PERF_SEL_RB1_OVERFLOW_VF3 = 312 -IH_PERF_SEL_RB1_OVERFLOW_VF4 = 313 -IH_PERF_SEL_RB1_OVERFLOW_VF5 = 314 -IH_PERF_SEL_RB1_OVERFLOW_VF6 = 315 -IH_PERF_SEL_RB1_OVERFLOW_VF7 = 316 -IH_PERF_SEL_RB1_OVERFLOW_VF8 = 317 -IH_PERF_SEL_RB1_OVERFLOW_VF9 = 318 -IH_PERF_SEL_RB1_OVERFLOW_VF10 = 319 -IH_PERF_SEL_RB1_OVERFLOW_VF11 = 320 -IH_PERF_SEL_RB1_OVERFLOW_VF12 = 321 -IH_PERF_SEL_RB1_OVERFLOW_VF13 = 322 -IH_PERF_SEL_RB1_OVERFLOW_VF14 = 323 -IH_PERF_SEL_RB1_OVERFLOW_VF15 = 324 -IH_PERF_SEL_RB1_OVERFLOW_VF16 = 325 -IH_PERF_SEL_RB1_OVERFLOW_VF17 = 326 -IH_PERF_SEL_RB1_OVERFLOW_VF18 = 327 -IH_PERF_SEL_RB1_OVERFLOW_VF19 = 328 -IH_PERF_SEL_RB1_OVERFLOW_VF20 = 329 -IH_PERF_SEL_RB1_OVERFLOW_VF21 = 330 -IH_PERF_SEL_RB1_OVERFLOW_VF22 = 331 -IH_PERF_SEL_RB1_OVERFLOW_VF23 = 332 -IH_PERF_SEL_RB1_OVERFLOW_VF24 = 333 -IH_PERF_SEL_RB1_OVERFLOW_VF25 = 334 -IH_PERF_SEL_RB1_OVERFLOW_VF26 = 335 -IH_PERF_SEL_RB1_OVERFLOW_VF27 = 336 -IH_PERF_SEL_RB1_OVERFLOW_VF28 = 337 -IH_PERF_SEL_RB1_OVERFLOW_VF29 = 338 -IH_PERF_SEL_RB1_OVERFLOW_VF30 = 339 -IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 340 -IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 341 -IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 342 -IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 343 -IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 344 -IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 345 -IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 346 -IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 347 -IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 348 -IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 349 -IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 350 -IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 351 -IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 352 -IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 353 -IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 354 -IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 355 -IH_PERF_SEL_RB1_WPTR_WRAP_VF16 = 356 -IH_PERF_SEL_RB1_WPTR_WRAP_VF17 = 357 -IH_PERF_SEL_RB1_WPTR_WRAP_VF18 = 358 -IH_PERF_SEL_RB1_WPTR_WRAP_VF19 = 359 -IH_PERF_SEL_RB1_WPTR_WRAP_VF20 = 360 -IH_PERF_SEL_RB1_WPTR_WRAP_VF21 = 361 -IH_PERF_SEL_RB1_WPTR_WRAP_VF22 = 362 -IH_PERF_SEL_RB1_WPTR_WRAP_VF23 = 363 -IH_PERF_SEL_RB1_WPTR_WRAP_VF24 = 364 -IH_PERF_SEL_RB1_WPTR_WRAP_VF25 = 365 -IH_PERF_SEL_RB1_WPTR_WRAP_VF26 = 366 -IH_PERF_SEL_RB1_WPTR_WRAP_VF27 = 367 -IH_PERF_SEL_RB1_WPTR_WRAP_VF28 = 368 -IH_PERF_SEL_RB1_WPTR_WRAP_VF29 = 369 -IH_PERF_SEL_RB1_WPTR_WRAP_VF30 = 370 -IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 371 -IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 372 -IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 373 -IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 374 -IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 375 -IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 376 -IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 377 -IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 378 -IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 379 -IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 380 -IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 381 -IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 382 -IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 383 -IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 384 -IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 385 -IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 386 -IH_PERF_SEL_RB1_RPTR_WRAP_VF16 = 387 -IH_PERF_SEL_RB1_RPTR_WRAP_VF17 = 388 -IH_PERF_SEL_RB1_RPTR_WRAP_VF18 = 389 -IH_PERF_SEL_RB1_RPTR_WRAP_VF19 = 390 -IH_PERF_SEL_RB1_RPTR_WRAP_VF20 = 391 -IH_PERF_SEL_RB1_RPTR_WRAP_VF21 = 392 -IH_PERF_SEL_RB1_RPTR_WRAP_VF22 = 393 -IH_PERF_SEL_RB1_RPTR_WRAP_VF23 = 394 -IH_PERF_SEL_RB1_RPTR_WRAP_VF24 = 395 -IH_PERF_SEL_RB1_RPTR_WRAP_VF25 = 396 -IH_PERF_SEL_RB1_RPTR_WRAP_VF26 = 397 -IH_PERF_SEL_RB1_RPTR_WRAP_VF27 = 398 -IH_PERF_SEL_RB1_RPTR_WRAP_VF28 = 399 -IH_PERF_SEL_RB1_RPTR_WRAP_VF29 = 400 -IH_PERF_SEL_RB1_RPTR_WRAP_VF30 = 401 -IH_PERF_SEL_RB2_FULL_VF0 = 402 -IH_PERF_SEL_RB2_FULL_VF1 = 403 -IH_PERF_SEL_RB2_FULL_VF2 = 404 -IH_PERF_SEL_RB2_FULL_VF3 = 405 -IH_PERF_SEL_RB2_FULL_VF4 = 406 -IH_PERF_SEL_RB2_FULL_VF5 = 407 -IH_PERF_SEL_RB2_FULL_VF6 = 408 -IH_PERF_SEL_RB2_FULL_VF7 = 409 -IH_PERF_SEL_RB2_FULL_VF8 = 410 -IH_PERF_SEL_RB2_FULL_VF9 = 411 -IH_PERF_SEL_RB2_FULL_VF10 = 412 -IH_PERF_SEL_RB2_FULL_VF11 = 413 -IH_PERF_SEL_RB2_FULL_VF12 = 414 -IH_PERF_SEL_RB2_FULL_VF13 = 415 -IH_PERF_SEL_RB2_FULL_VF14 = 416 -IH_PERF_SEL_RB2_FULL_VF15 = 417 -IH_PERF_SEL_RB2_FULL_VF16 = 418 -IH_PERF_SEL_RB2_FULL_VF17 = 419 -IH_PERF_SEL_RB2_FULL_VF18 = 420 -IH_PERF_SEL_RB2_FULL_VF19 = 421 -IH_PERF_SEL_RB2_FULL_VF20 = 422 -IH_PERF_SEL_RB2_FULL_VF21 = 423 -IH_PERF_SEL_RB2_FULL_VF22 = 424 -IH_PERF_SEL_RB2_FULL_VF23 = 425 -IH_PERF_SEL_RB2_FULL_VF24 = 426 -IH_PERF_SEL_RB2_FULL_VF25 = 427 -IH_PERF_SEL_RB2_FULL_VF26 = 428 -IH_PERF_SEL_RB2_FULL_VF27 = 429 -IH_PERF_SEL_RB2_FULL_VF28 = 430 -IH_PERF_SEL_RB2_FULL_VF29 = 431 -IH_PERF_SEL_RB2_FULL_VF30 = 432 -IH_PERF_SEL_RB2_OVERFLOW_VF0 = 433 -IH_PERF_SEL_RB2_OVERFLOW_VF1 = 434 -IH_PERF_SEL_RB2_OVERFLOW_VF2 = 435 -IH_PERF_SEL_RB2_OVERFLOW_VF3 = 436 -IH_PERF_SEL_RB2_OVERFLOW_VF4 = 437 -IH_PERF_SEL_RB2_OVERFLOW_VF5 = 438 -IH_PERF_SEL_RB2_OVERFLOW_VF6 = 439 -IH_PERF_SEL_RB2_OVERFLOW_VF7 = 440 -IH_PERF_SEL_RB2_OVERFLOW_VF8 = 441 -IH_PERF_SEL_RB2_OVERFLOW_VF9 = 442 -IH_PERF_SEL_RB2_OVERFLOW_VF10 = 443 -IH_PERF_SEL_RB2_OVERFLOW_VF11 = 444 -IH_PERF_SEL_RB2_OVERFLOW_VF12 = 445 -IH_PERF_SEL_RB2_OVERFLOW_VF13 = 446 -IH_PERF_SEL_RB2_OVERFLOW_VF14 = 447 -IH_PERF_SEL_RB2_OVERFLOW_VF15 = 448 -IH_PERF_SEL_RB2_OVERFLOW_VF16 = 449 -IH_PERF_SEL_RB2_OVERFLOW_VF17 = 450 -IH_PERF_SEL_RB2_OVERFLOW_VF18 = 451 -IH_PERF_SEL_RB2_OVERFLOW_VF19 = 452 -IH_PERF_SEL_RB2_OVERFLOW_VF20 = 453 -IH_PERF_SEL_RB2_OVERFLOW_VF21 = 454 -IH_PERF_SEL_RB2_OVERFLOW_VF22 = 455 -IH_PERF_SEL_RB2_OVERFLOW_VF23 = 456 -IH_PERF_SEL_RB2_OVERFLOW_VF24 = 457 -IH_PERF_SEL_RB2_OVERFLOW_VF25 = 458 -IH_PERF_SEL_RB2_OVERFLOW_VF26 = 459 -IH_PERF_SEL_RB2_OVERFLOW_VF27 = 460 -IH_PERF_SEL_RB2_OVERFLOW_VF28 = 461 -IH_PERF_SEL_RB2_OVERFLOW_VF29 = 462 -IH_PERF_SEL_RB2_OVERFLOW_VF30 = 463 -IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 464 -IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 465 -IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 466 -IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 467 -IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 468 -IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 469 -IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 470 -IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 471 -IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 472 -IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 473 -IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 474 -IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 475 -IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 476 -IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 477 -IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 478 -IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 479 -IH_PERF_SEL_RB2_WPTR_WRAP_VF16 = 480 -IH_PERF_SEL_RB2_WPTR_WRAP_VF17 = 481 -IH_PERF_SEL_RB2_WPTR_WRAP_VF18 = 482 -IH_PERF_SEL_RB2_WPTR_WRAP_VF19 = 483 -IH_PERF_SEL_RB2_WPTR_WRAP_VF20 = 484 -IH_PERF_SEL_RB2_WPTR_WRAP_VF21 = 485 -IH_PERF_SEL_RB2_WPTR_WRAP_VF22 = 486 -IH_PERF_SEL_RB2_WPTR_WRAP_VF23 = 487 -IH_PERF_SEL_RB2_WPTR_WRAP_VF24 = 488 -IH_PERF_SEL_RB2_WPTR_WRAP_VF25 = 489 -IH_PERF_SEL_RB2_WPTR_WRAP_VF26 = 490 -IH_PERF_SEL_RB2_WPTR_WRAP_VF27 = 491 -IH_PERF_SEL_RB2_WPTR_WRAP_VF28 = 492 -IH_PERF_SEL_RB2_WPTR_WRAP_VF29 = 493 -IH_PERF_SEL_RB2_WPTR_WRAP_VF30 = 494 -IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 495 -IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 496 -IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 497 -IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 498 -IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 499 -IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 500 -IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 501 -IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 502 -IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 503 -IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 504 -IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 505 -IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 506 -IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 507 -IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 508 -IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 509 -IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 510 -IH_PERF_SEL_RB2_RPTR_WRAP_VF16 = 511 -IH_PERF_SEL_RB2_RPTR_WRAP_VF17 = 512 -IH_PERF_SEL_RB2_RPTR_WRAP_VF18 = 513 -IH_PERF_SEL_RB2_RPTR_WRAP_VF19 = 514 -IH_PERF_SEL_RB2_RPTR_WRAP_VF20 = 515 -IH_PERF_SEL_RB2_RPTR_WRAP_VF21 = 516 -IH_PERF_SEL_RB2_RPTR_WRAP_VF22 = 517 -IH_PERF_SEL_RB2_RPTR_WRAP_VF23 = 518 -IH_PERF_SEL_RB2_RPTR_WRAP_VF24 = 519 -IH_PERF_SEL_RB2_RPTR_WRAP_VF25 = 520 -IH_PERF_SEL_RB2_RPTR_WRAP_VF26 = 521 -IH_PERF_SEL_RB2_RPTR_WRAP_VF27 = 522 -IH_PERF_SEL_RB2_RPTR_WRAP_VF28 = 523 -IH_PERF_SEL_RB2_RPTR_WRAP_VF29 = 524 -IH_PERF_SEL_RB2_RPTR_WRAP_VF30 = 525 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 526 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 527 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 528 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 529 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 530 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 531 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 532 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 533 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 534 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 535 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 536 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 537 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 538 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 539 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 540 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 541 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 542 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 543 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17 = 544 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18 = 545 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19 = 546 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20 = 547 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21 = 548 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22 = 549 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23 = 550 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24 = 551 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25 = 552 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26 = 553 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27 = 554 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28 = 555 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29 = 556 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30 = 557 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 558 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 559 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 560 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 561 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 562 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 563 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 564 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 565 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 566 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 567 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 568 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 569 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 570 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 571 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 572 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 573 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 574 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 575 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17 = 576 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18 = 577 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19 = 578 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20 = 579 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21 = 580 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22 = 581 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23 = 582 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24 = 583 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25 = 584 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26 = 585 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27 = 586 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28 = 587 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29 = 588 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30 = 589 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 590 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 591 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 592 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 593 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 594 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 595 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 596 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 597 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 598 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 599 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 600 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 601 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 602 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 603 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 604 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 605 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 606 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 607 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17 = 608 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18 = 609 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19 = 610 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20 = 611 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21 = 612 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22 = 613 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23 = 614 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24 = 615 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25 = 616 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26 = 617 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27 = 618 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28 = 619 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29 = 620 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30 = 621 -IH_PERF_SEL_RB0_LOAD_RPTR = 622 -IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 623 -IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 624 -IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 625 -IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 626 -IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 627 -IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 628 -IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 629 -IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 630 -IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 631 -IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 632 -IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 633 -IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 634 -IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 635 -IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 636 -IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 637 -IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 638 -IH_PERF_SEL_RB0_LOAD_RPTR_VF16 = 639 -IH_PERF_SEL_RB0_LOAD_RPTR_VF17 = 640 -IH_PERF_SEL_RB0_LOAD_RPTR_VF18 = 641 -IH_PERF_SEL_RB0_LOAD_RPTR_VF19 = 642 -IH_PERF_SEL_RB0_LOAD_RPTR_VF20 = 643 -IH_PERF_SEL_RB0_LOAD_RPTR_VF21 = 644 -IH_PERF_SEL_RB0_LOAD_RPTR_VF22 = 645 -IH_PERF_SEL_RB0_LOAD_RPTR_VF23 = 646 -IH_PERF_SEL_RB0_LOAD_RPTR_VF24 = 647 -IH_PERF_SEL_RB0_LOAD_RPTR_VF25 = 648 -IH_PERF_SEL_RB0_LOAD_RPTR_VF26 = 649 -IH_PERF_SEL_RB0_LOAD_RPTR_VF27 = 650 -IH_PERF_SEL_RB0_LOAD_RPTR_VF28 = 651 -IH_PERF_SEL_RB0_LOAD_RPTR_VF29 = 652 -IH_PERF_SEL_RB0_LOAD_RPTR_VF30 = 653 -IH_PERF_SEL_RB1_LOAD_RPTR = 654 -IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 655 -IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 656 -IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 657 -IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 658 -IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 659 -IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 660 -IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 661 -IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 662 -IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 663 -IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 664 -IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 665 -IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 666 -IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 667 -IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 668 -IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 669 -IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 670 -IH_PERF_SEL_RB1_LOAD_RPTR_VF16 = 671 -IH_PERF_SEL_RB1_LOAD_RPTR_VF17 = 672 -IH_PERF_SEL_RB1_LOAD_RPTR_VF18 = 673 -IH_PERF_SEL_RB1_LOAD_RPTR_VF19 = 674 -IH_PERF_SEL_RB1_LOAD_RPTR_VF20 = 675 -IH_PERF_SEL_RB1_LOAD_RPTR_VF21 = 676 -IH_PERF_SEL_RB1_LOAD_RPTR_VF22 = 677 -IH_PERF_SEL_RB1_LOAD_RPTR_VF23 = 678 -IH_PERF_SEL_RB1_LOAD_RPTR_VF24 = 679 -IH_PERF_SEL_RB1_LOAD_RPTR_VF25 = 680 -IH_PERF_SEL_RB1_LOAD_RPTR_VF26 = 681 -IH_PERF_SEL_RB1_LOAD_RPTR_VF27 = 682 -IH_PERF_SEL_RB1_LOAD_RPTR_VF28 = 683 -IH_PERF_SEL_RB1_LOAD_RPTR_VF29 = 684 -IH_PERF_SEL_RB1_LOAD_RPTR_VF30 = 685 -IH_PERF_SEL_RB2_LOAD_RPTR = 686 -IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 687 -IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 688 -IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 689 -IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 690 -IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 691 -IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 692 -IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 693 -IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 694 -IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 695 -IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 696 -IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 697 -IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 698 -IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 699 -IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 700 -IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 701 -IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 702 -IH_PERF_SEL_RB2_LOAD_RPTR_VF16 = 703 -IH_PERF_SEL_RB2_LOAD_RPTR_VF17 = 704 -IH_PERF_SEL_RB2_LOAD_RPTR_VF18 = 705 -IH_PERF_SEL_RB2_LOAD_RPTR_VF19 = 706 -IH_PERF_SEL_RB2_LOAD_RPTR_VF20 = 707 -IH_PERF_SEL_RB2_LOAD_RPTR_VF21 = 708 -IH_PERF_SEL_RB2_LOAD_RPTR_VF22 = 709 -IH_PERF_SEL_RB2_LOAD_RPTR_VF23 = 710 -IH_PERF_SEL_RB2_LOAD_RPTR_VF24 = 711 -IH_PERF_SEL_RB2_LOAD_RPTR_VF25 = 712 -IH_PERF_SEL_RB2_LOAD_RPTR_VF26 = 713 -IH_PERF_SEL_RB2_LOAD_RPTR_VF27 = 714 -IH_PERF_SEL_RB2_LOAD_RPTR_VF28 = 715 -IH_PERF_SEL_RB2_LOAD_RPTR_VF29 = 716 -IH_PERF_SEL_RB2_LOAD_RPTR_VF30 = 717 -IH_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'IH_CLIENT_TYPE' -IH_CLIENT_TYPE__enumvalues = { - 0: 'IH_GFX_VMID_CLIENT', - 1: 'IH_MM_VMID_CLIENT', - 2: 'IH_MULTI_VMID_CLIENT', - 3: 'IH_CLIENT_TYPE_RESERVED', -} -IH_GFX_VMID_CLIENT = 0 -IH_MM_VMID_CLIENT = 1 -IH_MULTI_VMID_CLIENT = 2 -IH_CLIENT_TYPE_RESERVED = 3 -IH_CLIENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'IH_RING_ID' -IH_RING_ID__enumvalues = { - 0: 'IH_RING_ID_INTERRUPT', - 1: 'IH_RING_ID_REQUEST', - 2: 'IH_RING_ID_TRANSLATION', - 3: 'IH_RING_ID_RESERVED', -} -IH_RING_ID_INTERRUPT = 0 -IH_RING_ID_REQUEST = 1 -IH_RING_ID_TRANSLATION = 2 -IH_RING_ID_RESERVED = 3 -IH_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'IH_VF_RB_SELECT' -IH_VF_RB_SELECT__enumvalues = { - 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 1: 'IH_VF_RB_SELECT_IH_FCN_ID', - 2: 'IH_VF_RB_SELECT_PF', - 3: 'IH_VF_RB_SELECT_RESERVED', -} -IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 -IH_VF_RB_SELECT_IH_FCN_ID = 1 -IH_VF_RB_SELECT_PF = 2 -IH_VF_RB_SELECT_RESERVED = 3 -IH_VF_RB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'IH_INTERFACE_TYPE' -IH_INTERFACE_TYPE__enumvalues = { - 0: 'IH_LEGACY_INTERFACE', - 1: 'IH_REGISTER_WRITE_INTERFACE', -} -IH_LEGACY_INTERFACE = 0 -IH_REGISTER_WRITE_INTERFACE = 1 -IH_INTERFACE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SEM_PERF_SEL' -SEM_PERF_SEL__enumvalues = { - 0: 'SEM_PERF_SEL_CYCLE', - 1: 'SEM_PERF_SEL_IDLE', - 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', - 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', - 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', - 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', - 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', - 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', - 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', - 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', - 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', - 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', - 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', - 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', - 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', - 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 166: 'SEM_PERF_SEL_MC_RD_REQ', - 167: 'SEM_PERF_SEL_MC_RD_RET', - 168: 'SEM_PERF_SEL_MC_WR_REQ', - 169: 'SEM_PERF_SEL_MC_WR_RET', - 170: 'SEM_PERF_SEL_ATC_REQ', - 171: 'SEM_PERF_SEL_ATC_RET', - 172: 'SEM_PERF_SEL_ATC_XNACK', - 173: 'SEM_PERF_SEL_ATC_INVALIDATION', - 174: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', -} -SEM_PERF_SEL_CYCLE = 0 -SEM_PERF_SEL_IDLE = 1 -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 -SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 -SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 -SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 -SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 -SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 -SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 -SEM_PERF_SEL_UVD_REQ_WAIT = 22 -SEM_PERF_SEL_VCE0_REQ_WAIT = 23 -SEM_PERF_SEL_ACP_REQ_WAIT = 24 -SEM_PERF_SEL_ISP_REQ_WAIT = 25 -SEM_PERF_SEL_VCE1_REQ_WAIT = 26 -SEM_PERF_SEL_VP8_REQ_WAIT = 27 -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 -SEM_PERF_SEL_MC_RD_REQ = 166 -SEM_PERF_SEL_MC_RD_RET = 167 -SEM_PERF_SEL_MC_WR_REQ = 168 -SEM_PERF_SEL_MC_WR_RET = 169 -SEM_PERF_SEL_ATC_REQ = 170 -SEM_PERF_SEL_ATC_RET = 171 -SEM_PERF_SEL_ATC_XNACK = 172 -SEM_PERF_SEL_ATC_INVALIDATION = 173 -SEM_PERF_SEL_ATC_VM_INVALIDATION = 174 -SEM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' -EFC_SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'EFC_ARGB1555', - 2: 'EFC_RGBA5551', - 3: 'EFC_RGB565', - 4: 'EFC_BGR565', - 5: 'EFC_ARGB4444', - 6: 'EFC_RGBA4444', - 8: 'EFC_ARGB8888', - 9: 'EFC_RGBA8888', - 10: 'EFC_ARGB2101010', - 11: 'EFC_RGBA1010102', - 12: 'EFC_AYCrCb8888', - 13: 'EFC_YCrCbA8888', - 14: 'EFC_ACrYCb8888', - 15: 'EFC_CrYCbA8888', - 16: 'EFC_ARGB16161616_10MSB', - 17: 'EFC_RGBA16161616_10MSB', - 18: 'EFC_ARGB16161616_10LSB', - 19: 'EFC_RGBA16161616_10LSB', - 20: 'EFC_ARGB16161616_12MSB', - 21: 'EFC_RGBA16161616_12MSB', - 22: 'EFC_ARGB16161616_12LSB', - 23: 'EFC_RGBA16161616_12LSB', - 24: 'EFC_ARGB16161616_FLOAT', - 25: 'EFC_RGBA16161616_FLOAT', - 26: 'EFC_ARGB16161616_UNORM', - 27: 'EFC_RGBA16161616_UNORM', - 28: 'EFC_ARGB16161616_SNORM', - 29: 'EFC_RGBA16161616_SNORM', - 32: 'EFC_AYCrCb16161616_10MSB', - 33: 'EFC_AYCrCb16161616_10LSB', - 34: 'EFC_YCrCbA16161616_10MSB', - 35: 'EFC_YCrCbA16161616_10LSB', - 36: 'EFC_ACrYCb16161616_10MSB', - 37: 'EFC_ACrYCb16161616_10LSB', - 38: 'EFC_CrYCbA16161616_10MSB', - 39: 'EFC_CrYCbA16161616_10LSB', - 40: 'EFC_AYCrCb16161616_12MSB', - 41: 'EFC_AYCrCb16161616_12LSB', - 42: 'EFC_YCrCbA16161616_12MSB', - 43: 'EFC_YCrCbA16161616_12LSB', - 44: 'EFC_ACrYCb16161616_12MSB', - 45: 'EFC_ACrYCb16161616_12LSB', - 46: 'EFC_CrYCbA16161616_12MSB', - 47: 'EFC_CrYCbA16161616_12LSB', - 64: 'EFC_Y8_CrCb88_420_PLANAR', - 65: 'EFC_Y8_CbCr88_420_PLANAR', - 66: 'EFC_Y10_CrCb1010_420_PLANAR', - 67: 'EFC_Y10_CbCr1010_420_PLANAR', - 68: 'EFC_Y12_CrCb1212_420_PLANAR', - 69: 'EFC_Y12_CbCr1212_420_PLANAR', - 72: 'EFC_YCrYCb8888_422_PACKED', - 73: 'EFC_YCbYCr8888_422_PACKED', - 74: 'EFC_CrYCbY8888_422_PACKED', - 75: 'EFC_CbYCrY8888_422_PACKED', - 76: 'EFC_YCrYCb10101010_422_PACKED', - 77: 'EFC_YCbYCr10101010_422_PACKED', - 78: 'EFC_CrYCbY10101010_422_PACKED', - 79: 'EFC_CbYCrY10101010_422_PACKED', - 80: 'EFC_YCrYCb12121212_422_PACKED', - 81: 'EFC_YCbYCr12121212_422_PACKED', - 82: 'EFC_CrYCbY12121212_422_PACKED', - 83: 'EFC_CbYCrY12121212_422_PACKED', - 112: 'EFC_RGB111110_FIX', - 113: 'EFC_BGR101111_FIX', - 114: 'EFC_ACrYCb2101010', - 115: 'EFC_CrYCbA1010102', - 118: 'EFC_RGB111110_FLOAT', - 119: 'EFC_BGR101111_FLOAT', - 120: 'EFC_MONO_8', - 121: 'EFC_MONO_10MSB', - 122: 'EFC_MONO_10LSB', - 123: 'EFC_MONO_12MSB', - 124: 'EFC_MONO_12LSB', - 125: 'EFC_MONO_16', -} -EFC_ARGB1555 = 1 -EFC_RGBA5551 = 2 -EFC_RGB565 = 3 -EFC_BGR565 = 4 -EFC_ARGB4444 = 5 -EFC_RGBA4444 = 6 -EFC_ARGB8888 = 8 -EFC_RGBA8888 = 9 -EFC_ARGB2101010 = 10 -EFC_RGBA1010102 = 11 -EFC_AYCrCb8888 = 12 -EFC_YCrCbA8888 = 13 -EFC_ACrYCb8888 = 14 -EFC_CrYCbA8888 = 15 -EFC_ARGB16161616_10MSB = 16 -EFC_RGBA16161616_10MSB = 17 -EFC_ARGB16161616_10LSB = 18 -EFC_RGBA16161616_10LSB = 19 -EFC_ARGB16161616_12MSB = 20 -EFC_RGBA16161616_12MSB = 21 -EFC_ARGB16161616_12LSB = 22 -EFC_RGBA16161616_12LSB = 23 -EFC_ARGB16161616_FLOAT = 24 -EFC_RGBA16161616_FLOAT = 25 -EFC_ARGB16161616_UNORM = 26 -EFC_RGBA16161616_UNORM = 27 -EFC_ARGB16161616_SNORM = 28 -EFC_RGBA16161616_SNORM = 29 -EFC_AYCrCb16161616_10MSB = 32 -EFC_AYCrCb16161616_10LSB = 33 -EFC_YCrCbA16161616_10MSB = 34 -EFC_YCrCbA16161616_10LSB = 35 -EFC_ACrYCb16161616_10MSB = 36 -EFC_ACrYCb16161616_10LSB = 37 -EFC_CrYCbA16161616_10MSB = 38 -EFC_CrYCbA16161616_10LSB = 39 -EFC_AYCrCb16161616_12MSB = 40 -EFC_AYCrCb16161616_12LSB = 41 -EFC_YCrCbA16161616_12MSB = 42 -EFC_YCrCbA16161616_12LSB = 43 -EFC_ACrYCb16161616_12MSB = 44 -EFC_ACrYCb16161616_12LSB = 45 -EFC_CrYCbA16161616_12MSB = 46 -EFC_CrYCbA16161616_12LSB = 47 -EFC_Y8_CrCb88_420_PLANAR = 64 -EFC_Y8_CbCr88_420_PLANAR = 65 -EFC_Y10_CrCb1010_420_PLANAR = 66 -EFC_Y10_CbCr1010_420_PLANAR = 67 -EFC_Y12_CrCb1212_420_PLANAR = 68 -EFC_Y12_CbCr1212_420_PLANAR = 69 -EFC_YCrYCb8888_422_PACKED = 72 -EFC_YCbYCr8888_422_PACKED = 73 -EFC_CrYCbY8888_422_PACKED = 74 -EFC_CbYCrY8888_422_PACKED = 75 -EFC_YCrYCb10101010_422_PACKED = 76 -EFC_YCbYCr10101010_422_PACKED = 77 -EFC_CrYCbY10101010_422_PACKED = 78 -EFC_CbYCrY10101010_422_PACKED = 79 -EFC_YCrYCb12121212_422_PACKED = 80 -EFC_YCbYCr12121212_422_PACKED = 81 -EFC_CrYCbY12121212_422_PACKED = 82 -EFC_CbYCrY12121212_422_PACKED = 83 -EFC_RGB111110_FIX = 112 -EFC_BGR101111_FIX = 113 -EFC_ACrYCb2101010 = 114 -EFC_CrYCbA1010102 = 115 -EFC_RGB111110_FLOAT = 118 -EFC_BGR101111_FLOAT = 119 -EFC_MONO_8 = 120 -EFC_MONO_10MSB = 121 -EFC_MONO_10LSB = 122 -EFC_MONO_12MSB = 123 -EFC_MONO_12LSB = 124 -EFC_MONO_16 = 125 -EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'UVDFirmwareCommand' -UVDFirmwareCommand__enumvalues = { - 0: 'UVDFC_FENCE', - 1: 'UVDFC_TRAP', - 2: 'UVDFC_DECODED_ADDR', - 3: 'UVDFC_MBLOCK_ADDR', - 4: 'UVDFC_ITBUF_ADDR', - 5: 'UVDFC_DISPLAY_ADDR', - 6: 'UVDFC_EOD', - 7: 'UVDFC_DISPLAY_PITCH', - 8: 'UVDFC_DISPLAY_TILING', - 9: 'UVDFC_BITSTREAM_ADDR', - 10: 'UVDFC_BITSTREAM_SIZE', -} -UVDFC_FENCE = 0 -UVDFC_TRAP = 1 -UVDFC_DECODED_ADDR = 2 -UVDFC_MBLOCK_ADDR = 3 -UVDFC_ITBUF_ADDR = 4 -UVDFC_DISPLAY_ADDR = 5 -UVDFC_EOD = 6 -UVDFC_DISPLAY_PITCH = 7 -UVDFC_DISPLAY_TILING = 8 -UVDFC_BITSTREAM_ADDR = 9 -UVDFC_BITSTREAM_SIZE = 10 -UVDFirmwareCommand = ctypes.c_uint32 # enum -__all__ = \ - ['ABGR_TO_A_BG_G_RB', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', - 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACrYCb16161616_10LSB', - 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', - 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', - 'ADDR_CONFIG_16_BANK', 'ADDR_CONFIG_16_PIPE', - 'ADDR_CONFIG_1KB_ROW', 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', - 'ADDR_CONFIG_1_LOWER_PIPES', - 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', - 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', - 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', - 'ADDR_CONFIG_2_LOWER_PIPES', - 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', - 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', - 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', - 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', - 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_64_PIPE', - 'ADDR_CONFIG_8_BANK', 'ADDR_CONFIG_8_GPU', - 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_8_PIPE', - 'ADDR_CONFIG_8_SHADER_ENGINE', 'ADDR_CONFIG_BANK_INTERLEAVE_1', - 'ADDR_CONFIG_BANK_INTERLEAVE_2', 'ADDR_CONFIG_BANK_INTERLEAVE_4', - 'ADDR_CONFIG_BANK_INTERLEAVE_8', 'ADDR_CONFIG_DISABLE_SE', - 'ADDR_CONFIG_ENABLE_SE', 'ADDR_CONFIG_GPU_TILE_128', - 'ADDR_CONFIG_GPU_TILE_16', 'ADDR_CONFIG_GPU_TILE_32', - 'ADDR_CONFIG_GPU_TILE_64', 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', - 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', - 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', - 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', - 'ADDR_CONFIG_SE_TILE_32', 'ADDR_NUM_BANKS_BC_BANKS_1', - 'ADDR_NUM_BANKS_BC_BANKS_16', 'ADDR_NUM_BANKS_BC_BANKS_2', - 'ADDR_NUM_BANKS_BC_BANKS_4', 'ADDR_NUM_BANKS_BC_BANKS_8', - 'ADDR_NUM_PIPES_BC_P16', 'ADDR_NUM_PIPES_BC_P8', - 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', 'ADDR_SURF_4_BANK', - 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', - 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', - 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', - 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', - 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', - 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', - 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', - 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', - 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', - 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', - 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16', - 'ADDR_SURF_P16_32x32_16x16', 'ADDR_SURF_P16_32x32_8x16', - 'ADDR_SURF_P2', 'ADDR_SURF_P2_RESERVED0', - 'ADDR_SURF_P2_RESERVED1', 'ADDR_SURF_P2_RESERVED2', - 'ADDR_SURF_P4_16x16', 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', - 'ADDR_SURF_P4_8x16', 'ADDR_SURF_P8_16x16_8x16', - 'ADDR_SURF_P8_16x32_16x16', 'ADDR_SURF_P8_16x32_8x16', - 'ADDR_SURF_P8_32x32_16x16', 'ADDR_SURF_P8_32x32_16x32', - 'ADDR_SURF_P8_32x32_8x16', 'ADDR_SURF_P8_32x64_32x32', - 'ADDR_SURF_P8_RESERVED0', 'ADDR_SURF_ROTATED_MICRO_TILING', - 'ADDR_SURF_SAMPLE_SPLIT_1', 'ADDR_SURF_SAMPLE_SPLIT_2', - 'ADDR_SURF_SAMPLE_SPLIT_4', 'ADDR_SURF_SAMPLE_SPLIT_8', - 'ADDR_SURF_THICK_MICRO_TILING', 'ADDR_SURF_THIN_MICRO_TILING', - 'ADDR_SURF_TILE_SPLIT_128B', 'ADDR_SURF_TILE_SPLIT_1KB', - 'ADDR_SURF_TILE_SPLIT_256B', 'ADDR_SURF_TILE_SPLIT_2KB', - 'ADDR_SURF_TILE_SPLIT_4KB', 'ADDR_SURF_TILE_SPLIT_512B', - 'ADDR_SURF_TILE_SPLIT_64B', 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', - 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', - 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', - 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', - 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', - 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', - 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', - 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', - 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', - 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', - 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', - 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', - 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', - 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', - 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', - 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', - 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', - 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', - 'AFMT_INTERRUPT_STATUS_CHG_MASK', - 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', - 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', - 'AFMT_VBI_GSP0_INDEX', 'AFMT_VBI_GSP10_INDEX', - 'AFMT_VBI_GSP1_INDEX', 'AFMT_VBI_GSP2_INDEX', - 'AFMT_VBI_GSP3_INDEX', 'AFMT_VBI_GSP4_INDEX', - 'AFMT_VBI_GSP5_INDEX', 'AFMT_VBI_GSP6_INDEX', - 'AFMT_VBI_GSP7_INDEX', 'AFMT_VBI_GSP8_INDEX', - 'AFMT_VBI_GSP9_INDEX', 'AFMT_VBI_GSP_INDEX', - 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', - 'ALLOW_SR_ON_TRANS_REQ_ENABLE', 'ALPHA_DATA_ON_ALPHA_PORT', - 'ALPHA_DATA_ON_CB_B_PORT', 'ALPHA_DATA_ON_CR_R_PORT', - 'ALPHA_DATA_ON_Y_G_PORT', 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AM_1D_TILED_THICK', - 'AM_1D_TILED_THIN1', 'AM_2D_TILED_THICK', 'AM_2D_TILED_THIN1', - 'AM_2D_TILED_XTHICK', 'AM_3D_TILED_THICK', 'AM_3D_TILED_THIN1', - 'AM_3D_TILED_XTHICK', 'AM_LINEAR_ALIGNED', 'AM_LINEAR_GENERAL', - 'AM_PRT_2D_TILED_THICK', 'AM_PRT_2D_TILED_THIN1', - 'AM_PRT_3D_TILED_THICK', 'AM_PRT_3D_TILED_THIN1', - 'AM_PRT_TILED_THICK', 'AM_PRT_TILED_THIN1', 'ARGB1555', - 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', - 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', - 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', - 'ARRAY_1D', 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', - 'ARRAY_2D', 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', - 'ARRAY_2D_COLOR', 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', - 'ARRAY_2D_TILED_THIN1', 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', - 'ARRAY_3D_SLICE', 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', - 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', - 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', - 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', 'ARRAY_MODE', - 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', - 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', - 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', - 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', - 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', - 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', - 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', - 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', - 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', - 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', - 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', - 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', - 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', - 'AZ_RIRB_WRITE_POINTER_DO_RESET', - 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', - 'AZ_STATE_CHANGE_STATUS', - 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', - 'BANK_HEIGHT', 'BANK_WIDTH', 'BGR101111_FIX', 'BGR101111_FLOAT', - 'BGR565', 'BGRA_TO_BG_G_RB_A', 'BINNER_BREAK_BATCH', - 'BINNER_DROP', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', - 'BINNING_ALLOWED', 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', - 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', - 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', - 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', - 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', - 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_BOTH_INV_SRC_ALPHA', - 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', - 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', - 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', - 'BLEND_ONE_MINUS_CONSTANT_ALPHA', - 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', - 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', - 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', - 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', - 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BOTH_EYE', - 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BUF_DATA_FORMAT', - 'BUF_DATA_FORMAT_10_10_10_2', 'BUF_DATA_FORMAT_10_11_11', - 'BUF_DATA_FORMAT_11_11_10', 'BUF_DATA_FORMAT_16', - 'BUF_DATA_FORMAT_16_16', 'BUF_DATA_FORMAT_16_16_16_16', - 'BUF_DATA_FORMAT_2_10_10_10', 'BUF_DATA_FORMAT_32', - 'BUF_DATA_FORMAT_32_32', 'BUF_DATA_FORMAT_32_32_32', - 'BUF_DATA_FORMAT_32_32_32_32', 'BUF_DATA_FORMAT_8', - 'BUF_DATA_FORMAT_8_8', 'BUF_DATA_FORMAT_8_8_8_8', - 'BUF_DATA_FORMAT_INVALID', 'BUF_DATA_FORMAT_RESERVED_15', - 'BUF_FMT', 'BUF_FMT_10_10_10_2_SINT', 'BUF_FMT_10_10_10_2_SNORM', - 'BUF_FMT_10_10_10_2_SSCALED', 'BUF_FMT_10_10_10_2_UINT', - 'BUF_FMT_10_10_10_2_UNORM', 'BUF_FMT_10_10_10_2_USCALED', - 'BUF_FMT_10_11_11_FLOAT', 'BUF_FMT_10_11_11_SINT', - 'BUF_FMT_10_11_11_SNORM', 'BUF_FMT_10_11_11_SSCALED', - 'BUF_FMT_10_11_11_UINT', 'BUF_FMT_10_11_11_UNORM', - 'BUF_FMT_10_11_11_USCALED', 'BUF_FMT_11_11_10_FLOAT', - 'BUF_FMT_11_11_10_SINT', 'BUF_FMT_11_11_10_SNORM', - 'BUF_FMT_11_11_10_SSCALED', 'BUF_FMT_11_11_10_UINT', - 'BUF_FMT_11_11_10_UNORM', 'BUF_FMT_11_11_10_USCALED', - 'BUF_FMT_16_16_16_16_FLOAT', 'BUF_FMT_16_16_16_16_SINT', - 'BUF_FMT_16_16_16_16_SNORM', 'BUF_FMT_16_16_16_16_SSCALED', - 'BUF_FMT_16_16_16_16_UINT', 'BUF_FMT_16_16_16_16_UNORM', - 'BUF_FMT_16_16_16_16_USCALED', 'BUF_FMT_16_16_FLOAT', - 'BUF_FMT_16_16_SINT', 'BUF_FMT_16_16_SNORM', - 'BUF_FMT_16_16_SSCALED', 'BUF_FMT_16_16_UINT', - 'BUF_FMT_16_16_UNORM', 'BUF_FMT_16_16_USCALED', - 'BUF_FMT_16_FLOAT', 'BUF_FMT_16_SINT', 'BUF_FMT_16_SNORM', - 'BUF_FMT_16_SSCALED', 'BUF_FMT_16_UINT', 'BUF_FMT_16_UNORM', - 'BUF_FMT_16_USCALED', 'BUF_FMT_2_10_10_10_SINT', - 'BUF_FMT_2_10_10_10_SNORM', 'BUF_FMT_2_10_10_10_SSCALED', - 'BUF_FMT_2_10_10_10_UINT', 'BUF_FMT_2_10_10_10_UNORM', - 'BUF_FMT_2_10_10_10_USCALED', 'BUF_FMT_32_32_32_32_FLOAT', - 'BUF_FMT_32_32_32_32_SINT', 'BUF_FMT_32_32_32_32_UINT', - 'BUF_FMT_32_32_32_FLOAT', 'BUF_FMT_32_32_32_SINT', - 'BUF_FMT_32_32_32_UINT', 'BUF_FMT_32_32_FLOAT', - 'BUF_FMT_32_32_SINT', 'BUF_FMT_32_32_UINT', 'BUF_FMT_32_FLOAT', - 'BUF_FMT_32_SINT', 'BUF_FMT_32_UINT', 'BUF_FMT_8_8_8_8_SINT', - 'BUF_FMT_8_8_8_8_SNORM', 'BUF_FMT_8_8_8_8_SSCALED', - 'BUF_FMT_8_8_8_8_UINT', 'BUF_FMT_8_8_8_8_UNORM', - 'BUF_FMT_8_8_8_8_USCALED', 'BUF_FMT_8_8_SINT', - 'BUF_FMT_8_8_SNORM', 'BUF_FMT_8_8_SSCALED', 'BUF_FMT_8_8_UINT', - 'BUF_FMT_8_8_UNORM', 'BUF_FMT_8_8_USCALED', 'BUF_FMT_8_SINT', - 'BUF_FMT_8_SNORM', 'BUF_FMT_8_SSCALED', 'BUF_FMT_8_UINT', - 'BUF_FMT_8_UNORM', 'BUF_FMT_8_USCALED', 'BUF_FMT_INVALID', - 'BUF_FMT_RESERVED_100', 'BUF_FMT_RESERVED_101', - 'BUF_FMT_RESERVED_102', 'BUF_FMT_RESERVED_103', - 'BUF_FMT_RESERVED_104', 'BUF_FMT_RESERVED_105', - 'BUF_FMT_RESERVED_106', 'BUF_FMT_RESERVED_107', - 'BUF_FMT_RESERVED_108', 'BUF_FMT_RESERVED_109', - 'BUF_FMT_RESERVED_110', 'BUF_FMT_RESERVED_111', - 'BUF_FMT_RESERVED_112', 'BUF_FMT_RESERVED_113', - 'BUF_FMT_RESERVED_114', 'BUF_FMT_RESERVED_115', - 'BUF_FMT_RESERVED_116', 'BUF_FMT_RESERVED_117', - 'BUF_FMT_RESERVED_118', 'BUF_FMT_RESERVED_119', - 'BUF_FMT_RESERVED_120', 'BUF_FMT_RESERVED_121', - 'BUF_FMT_RESERVED_122', 'BUF_FMT_RESERVED_123', - 'BUF_FMT_RESERVED_124', 'BUF_FMT_RESERVED_125', - 'BUF_FMT_RESERVED_126', 'BUF_FMT_RESERVED_127', - 'BUF_FMT_RESERVED_78', 'BUF_FMT_RESERVED_79', - 'BUF_FMT_RESERVED_80', 'BUF_FMT_RESERVED_81', - 'BUF_FMT_RESERVED_82', 'BUF_FMT_RESERVED_83', - 'BUF_FMT_RESERVED_84', 'BUF_FMT_RESERVED_85', - 'BUF_FMT_RESERVED_86', 'BUF_FMT_RESERVED_87', - 'BUF_FMT_RESERVED_88', 'BUF_FMT_RESERVED_89', - 'BUF_FMT_RESERVED_90', 'BUF_FMT_RESERVED_91', - 'BUF_FMT_RESERVED_92', 'BUF_FMT_RESERVED_93', - 'BUF_FMT_RESERVED_94', 'BUF_FMT_RESERVED_95', - 'BUF_FMT_RESERVED_96', 'BUF_FMT_RESERVED_97', - 'BUF_FMT_RESERVED_98', 'BUF_FMT_RESERVED_99', 'BUF_NUM_FORMAT', - 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', - 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SNORM_NZ', - 'BUF_NUM_FORMAT_SSCALED', 'BUF_NUM_FORMAT_UINT', - 'BUF_NUM_FORMAT_UNORM', 'BUF_NUM_FORMAT_USCALED', 'BYPASS_EN', - 'BYPASS_GAMUT', 'BYPASS_ICSC', 'BankHeight', 'BankInterleaveSize', - 'BankSwapBytes', 'BankTiling', 'BankWidth', 'BankWidthHeight', - 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', 'BinningMode', - 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', 'CACHE_FLUSH', - 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', - 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA', - 'CACHE_STREAM', 'CBMode', 'CBPerfClearFilterSel', - 'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ON_ALPHA_PORT', - 'CB_B_DATA_ON_CB_B_PORT', 'CB_B_DATA_ON_CR_R_PORT', - 'CB_B_DATA_ON_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', - 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', - 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', - 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', - 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', - 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', - 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', - 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD', - 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', - 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', - 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', - 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', - 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', - 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', - 'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN', - 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_WRITE_ACK64B', - 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL', - 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', - 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', - 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', - 'CB_PERF_SEL_CMASK_READ_DATA_0xD', - 'CB_PERF_SEL_CMASK_READ_DATA_0xE', - 'CB_PERF_SEL_CMASK_READ_DATA_0xF', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', - 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', - 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', - 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', - 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_TAG_MISS', - 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', - 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', - 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', - 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', - 'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN', - 'CB_PERF_SEL_CM_MC_READ_REQUEST', - 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CM_MC_WRITE_ACK64B', - 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL', - 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', - 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', - 'CB_PERF_SEL_DB_CB_CONTEXT_DONE', 'CB_PERF_SEL_DB_CB_EOP_DONE', - 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', - 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', - 'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT', - 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', - 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', - 'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN', - 'CB_PERF_SEL_DC_MC_WRITE_ACK64B', 'CB_PERF_SEL_DRAWN_BUSY', - 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', - 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', - 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', - 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS', - 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', - 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', - 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', - 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_TAG_MISS', - 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', - 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', - 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', - 'CB_PERF_SEL_FC_DCC_CACHE_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', - 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', - 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', - 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', - 'CB_PERF_SEL_FC_DOC_IS_STALLED', - 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', - 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', - 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', - 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', - 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', - 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', - 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FC_KEYID_STUTTER_STALL', - 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', - 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', - 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN', - 'CB_PERF_SEL_FC_MC_READ_REQUEST', - 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_WRITE_ACK64B', - 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', - 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FC_QUAD_STUTTER_STALL', - 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', - 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', - 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', - 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', - 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FC_TILE_STUTTER_STALL', - 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', - 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', - 'CB_PERF_SEL_FOP_IN_VALIDB_READY', - 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', - 'CB_PERF_SEL_FOP_IN_VALID_READY', - 'CB_PERF_SEL_FOP_IN_VALID_READYB', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', - 'CB_PERF_SEL_LQUAD_NO_TILE', - 'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED', - 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', - 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', - 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', - 'CB_PERF_SEL_NACK_CM_READ', 'CB_PERF_SEL_NACK_CM_WRITE', - 'CB_PERF_SEL_NACK_DC_READ', 'CB_PERF_SEL_NACK_DC_WRITE', - 'CB_PERF_SEL_NACK_FC_READ', 'CB_PERF_SEL_NACK_FC_WRITE', - 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', - 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', - 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', - 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', - 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', - 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', - 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', - 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', - 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', - 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', - 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', - 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', - 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', - 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', - 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', - 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', - 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', - 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', - 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', - 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', - 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESERVED', - 'CB_RESOLVE', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', - 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', - 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', - 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', - 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', - 'CHA_PERF_SEL_REQUEST_CHC5', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1', - 'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3', - 'CHA_PERF_SEL_STALL_CHC4', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', - 'CHCG_PERF_SEL_CORE_REG_SCLK_VLD', 'CHCG_PERF_SEL_CYCLE', - 'CHCG_PERF_SEL_GATE_EN1', 'CHCG_PERF_SEL_GATE_EN2', - 'CHCG_PERF_SEL_REQ', 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', - 'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHC_PERF_SEL', - 'CHC_PERF_SEL_CORE_REG_SCLK_VLD', 'CHC_PERF_SEL_CYCLE', - 'CHC_PERF_SEL_GATE_EN1', 'CHC_PERF_SEL_GATE_EN2', - 'CHC_PERF_SEL_REQ', 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', - 'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHUNK_SIZE', - 'CHUNK_SIZE_16KB', 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', - 'CHUNK_SIZE_32KB', 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', - 'CHUNK_SIZE_8KB', 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', - 'CLKGATE_SM_MODE', 'CLOCK_BRANCH_SOFT_RESET', - 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED', - 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM', - 'CLOCK_GATING_DISABLE_ENUM_DISABLED', - 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', - 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', - 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', - 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', - 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', - 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', - 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', - 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', - 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', - 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', - 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', - 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', - 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', - 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', - 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', 'CMC_3DLUT_30BIT', - 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', 'CMC_3DLUT_9CUBE', - 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', - 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', - 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', - 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', - 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', - 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', - 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', - 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', - 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', - 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', - 'CMC_SEGMENTS_8', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', - 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', - 'CM_GAMUT_REMAP_MODE_ENUM', 'CM_ICSC_MODE_ENUM', - 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', - 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', 'CM_LUT_NUM_SEG', - 'CM_LUT_RAM_SEL', 'CM_NOT_PENDING', 'CM_PENDING', - 'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_BYPASS', - 'CNVC_BYPASS_DISABLE', 'CNVC_BYPASS_EN', 'CNVC_DIS', 'CNVC_EN', - 'CNVC_ENABLE', 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', - 'CNVC_TRUNCATE', 'CNVC_YES_PENDING', 'CNV_CSC_BYPASS_ENUM', - 'CNV_CSC_BYPASS_NEG', 'CNV_CSC_BYPASS_POS', 'CNV_EYE_SELECT', - 'CNV_FRAME_CAPTURE_DISABLE', 'CNV_FRAME_CAPTURE_ENABLE', - 'CNV_FRAME_CAPTURE_EN_ENUM', 'CNV_FRAME_CAPTURE_RATE_0', - 'CNV_FRAME_CAPTURE_RATE_1', 'CNV_FRAME_CAPTURE_RATE_2', - 'CNV_FRAME_CAPTURE_RATE_3', 'CNV_FRAME_CAPTURE_RATE_ENUM', - 'CNV_INTERLACED_FIELD_ORDER_BOT', - 'CNV_INTERLACED_FIELD_ORDER_ENUM', - 'CNV_INTERLACED_FIELD_ORDER_TOP', 'CNV_INTERLACED_MODE_ENUM', - 'CNV_INTERLACED_MODE_INTERLACED', - 'CNV_INTERLACED_MODE_PROGRESSIVE', 'CNV_NEW_CONTENT_ENUM', - 'CNV_NEW_CONTENT_NEG', 'CNV_NEW_CONTENT_POS', 'CNV_OUT_BPC_10BPC', - 'CNV_OUT_BPC_8BPC', 'CNV_OUT_BPC_ENUM', - 'CNV_STEREO_POLARITY_ENUM', 'CNV_STEREO_POLARITY_LEFT', - 'CNV_STEREO_POLARITY_RIGHT', 'CNV_STEREO_SPLIT_DISABLE', - 'CNV_STEREO_SPLIT_ENABLE', 'CNV_STEREO_SPLIT_ENUM', - 'CNV_STEREO_TYPE_ENUM', 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL', - 'CNV_STEREO_TYPE_RESERVED0', 'CNV_STEREO_TYPE_RESERVED1', - 'CNV_STEREO_TYPE_RESERVED2', 'CNV_TEST_CRC_CONT_DISABLE', - 'CNV_TEST_CRC_CONT_ENABLE', 'CNV_TEST_CRC_CONT_EN_ENUM', - 'CNV_TEST_CRC_DISABLE', 'CNV_TEST_CRC_ENABLE', - 'CNV_TEST_CRC_EN_ENUM', 'CNV_UPDATE_LOCK', 'CNV_UPDATE_LOCK_ENUM', - 'CNV_UPDATE_PENDING_ENUM', 'CNV_UPDATE_PENDING_NEG', - 'CNV_UPDATE_PENDING_POS', 'CNV_UPDATE_UNLOCK', - 'CNV_WINDOW_CROP_DISABLE', 'CNV_WINDOW_CROP_ENABLE', - 'CNV_WINDOW_CROP_EN_ENUM', 'COEF_ICSC', 'COEF_ICSC_B', - 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', - 'COEF_RAM_SELECT_RD', 'COLOR_10_10_10_2', 'COLOR_10_11_11', - 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', - 'COLOR_1_5_5_5', 'COLOR_24BIT_1BIT_AND', - 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_24_8', - 'COLOR_2_10_10_10', 'COLOR_2_10_10_10_6E4', 'COLOR_32', - 'COLOR_32_32', 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', - 'COLOR_5_5_5_1', 'COLOR_5_6_5', 'COLOR_64BIT_FP_PREMULT', - 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', - 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_KEYER_MODE', - 'COLOR_RESERVED_13', 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', - 'COLOR_RESERVED_24', 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', - 'COLOR_RESERVED_27', 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', - 'COLOR_RESERVED_30', 'COLOR_X24_8_32_FLOAT', 'COMB_DST_MINUS_SRC', - 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', 'COMB_MIN_DST_SRC', - 'COMB_SRC_MINUS_DST', 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', - 'CONFIG_1KB_ROW_OPT', 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', - 'CONFIG_1_PIPE', 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', - 'CONFIG_2KB_ROW', 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', - 'CONFIG_2_PIPE', 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', - 'CONFIG_4KB_SPLIT', 'CONFIG_4_BANK', 'CONFIG_4_PIPE', - 'CONFIG_512B_GROUP', 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', - 'CONFIG_8KB_ROW_OPT', 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', - 'CONFIG_8_PIPE', 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', - 'CONFIG_SPACE2_END', 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', - 'CONFIG_SPACE_START', 'CONTEXT_DONE', 'CONTEXT_SPACE_END', - 'CONTEXT_SPACE_START', 'CONTEXT_SUSPEND', - 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', - 'CORB_READ_POINTER_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', - 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', - 'CPC_LATENCY_STATS_SEL_INVAL_LAST', - 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', - 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', - 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', - 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', - 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', - 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', - 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', - 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 'CPF_LATENCY_STATS_SEL_READ_LAST', - 'CPF_LATENCY_STATS_SEL_READ_MAX', - 'CPF_LATENCY_STATS_SEL_READ_MIN', - 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', - 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', - 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', - 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', - 'CPF_PERF_SEL_ALWAYS_COUNT', - 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', - 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', - 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 'CPF_PERF_SEL_CPG_TCIU_STALL', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', - 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 'CPF_PERF_SEL_GUS_READ_REQUEST_SEND', - 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND', - 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', - 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', - 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', - 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 'CPG_LATENCY_STATS_SEL_INVAL_LAST', - 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 'CPG_LATENCY_STATS_SEL_READ_LAST', - 'CPG_LATENCY_STATS_SEL_READ_MAX', - 'CPG_LATENCY_STATS_SEL_READ_MIN', - 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', - 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', - 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', - 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', - 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', - 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', - 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', - 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', - 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', - 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', - 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', - 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', - 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', - 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', - 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', - 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', - 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', - 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', - 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', - 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', - 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', - 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', - 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', - 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', - 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', - 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', - 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', - 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', - 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_BITS_0', 'CRC_CUR_BITS_1', - 'CRC_CUR_BITS_SEL', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', - 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', - 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', - 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', - 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', - 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0', 'CRC_SRC_1', - 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', 'CRC_STEREO_0', - 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', 'CRC_STEREO_SEL', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', - 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', - 'CR_R_DATA_ON_ALPHA_PORT', 'CR_R_DATA_ON_CB_B_PORT', - 'CR_R_DATA_ON_CR_R_PORT', 'CR_R_DATA_ON_Y_G_PORT', - 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', - 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', - 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', - 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', - 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', - 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', - 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', - 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', - 'CURSOR_COLOR_24BIT_1BIT_AND', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 'CURSOR_COLOR_64BIT_FP_PREMULT', - 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', - 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', - 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', - 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', - 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', - 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', - 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', - 'CURSOR_MODE', 'CURSOR_MONO_2BIT', - 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_EN', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', - 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', - 'CURSOR_PITCH_64_PIXELS', 'CURSOR_SNOOP', 'CURSOR_STEREO_EN', - 'CURSOR_STEREO_IS_DISABLED', 'CURSOR_STEREO_IS_ENABLED', - 'CURSOR_SURFACE_IS_NOT_TMZ', 'CURSOR_SURFACE_IS_TMZ', - 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', - 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', - 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', - 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', - 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', - 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', - 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', - 'CbYCrY8888_422_PACKED', 'CmaskAddr', 'CmaskCode', 'CmaskMode', - 'ColorArray', 'ColorFormat', 'ColorTransform', 'CombFunc', - 'CompareFrag', 'CompareRef', 'ConservativeZExport', - 'CovToShaderSel', 'CrYCbA1010102', 'CrYCbA16161616_10LSB', - 'CrYCbA16161616_10MSB', 'CrYCbA16161616_12LSB', - 'CrYCbA16161616_12MSB', 'CrYCbA8888', 'CrYCbY10101010_422_PACKED', - 'CrYCbY12121212_422_PACKED', 'CrYCbY8888_422_PACKED', - 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', - 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', - 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', - 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', - 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', - 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', - 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 'DB_PERF_SEL_CB_DB_rdreq_sends', - 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 'DB_PERF_SEL_CB_DB_wrreq_sends', - 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', - 'DB_PERF_SEL_DB_CB_lquad_busy', - 'DB_PERF_SEL_DB_CB_lquad_double_format', - 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', - 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', - 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', - 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', - 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', - 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', - 'DB_PERF_SEL_DB_SC_quad_double_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke', - 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', - 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', - 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', - 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 'DB_PERF_SEL_DB_SC_tile_stalls', - 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', - 'DB_PERF_SEL_DFSM_Flush_flushabit', - 'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo', - 'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush', - 'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull', - 'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough', - 'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark', - 'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling', - 'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark', - 'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark', - 'DB_PERF_SEL_DFSM_Flush_flushall', - 'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush', - 'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange', - 'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange', - 'DB_PERF_SEL_DFSM_Flush_flushall_watchdog', - 'DB_PERF_SEL_DFSM_Stall_bypass_fifo', - 'DB_PERF_SEL_DFSM_Stall_cam_fifo', - 'DB_PERF_SEL_DFSM_Stall_control_fifo', - 'DB_PERF_SEL_DFSM_Stall_middle_output', - 'DB_PERF_SEL_DFSM_Stall_opmode_change', - 'DB_PERF_SEL_DFSM_Stall_overflow_counter', - 'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow', - 'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush', - 'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo', - 'DB_PERF_SEL_DFSM_Stall_stalling_general', - 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', - 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', - 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', - 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', - 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', - 'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark', - 'DB_PERF_SEL_DFSM_full_cleared_squads_out', - 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', - 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', - 'DB_PERF_SEL_DFSM_lit_pixels_in', - 'DB_PERF_SEL_DFSM_lit_samples_in', - 'DB_PERF_SEL_DFSM_lit_samples_out', - 'DB_PERF_SEL_DFSM_prez_killed_squad', 'DB_PERF_SEL_DFSM_quads_in', - 'DB_PERF_SEL_DFSM_squads_in', - 'DB_PERF_SEL_DFSM_stalled_by_downstream', - 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 'DB_PERF_SEL_Depth_Tile_Cache_event', - 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 'DB_PERF_SEL_Plane_Cache_flushes', - 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', - 'DB_PERF_SEL_Plane_Cache_misses', - 'DB_PERF_SEL_Plane_Cache_starves', - 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 'DB_PERF_SEL_PostZ_Samples_failing_S', - 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 'DB_PERF_SEL_PreZ_Samples_failing_S', - 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 'DB_PERF_SEL_SC_DB_quad_busy', - 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', - 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', - 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', - 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', - 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', - 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', - 'DB_PERF_SEL_SH_quads_outstanding_sum', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 'DB_PERF_SEL_SX_DB_quad_busy', - 'DB_PERF_SEL_SX_DB_quad_double_format', - 'DB_PERF_SEL_SX_DB_quad_export_quads', - 'DB_PERF_SEL_SX_DB_quad_exports', - 'DB_PERF_SEL_SX_DB_quad_fast_format', - 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', - 'DB_PERF_SEL_SX_DB_quad_sends', - 'DB_PERF_SEL_SX_DB_quad_slow_format', - 'DB_PERF_SEL_SX_DB_quad_stalls', - 'DB_PERF_SEL_Stencil_Cache_flushes', - 'DB_PERF_SEL_Stencil_Cache_frees', - 'DB_PERF_SEL_Stencil_Cache_hits', - 'DB_PERF_SEL_Stencil_Cache_misses', - 'DB_PERF_SEL_Stencil_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', - 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_surface_stall', - 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 'DB_PERF_SEL_Z_Cache_pmask_hits', - 'DB_PERF_SEL_Z_Cache_pmask_misses', - 'DB_PERF_SEL_Z_Cache_pmask_starves', - 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 'DB_PERF_SEL_clock_main_active', - 'DB_PERF_SEL_clock_mem_export_active', - 'DB_PERF_SEL_clock_reg_active', - 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', - 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', - 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', - 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', - 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', - 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', - 'DB_PERF_SEL_dtt_sm_slot_stall', - 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', - 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', - 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', - 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', - 'DB_PERF_SEL_esr_ps_src_in_squads', - 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_stall', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', - 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', - 'DB_PERF_SEL_etr_out_cb_tile_stall', - 'DB_PERF_SEL_etr_out_esr_stall', - 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', - 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', - 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', - 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', - 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', - 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', - 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', - 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', - 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', - 'DB_PERF_SEL_flush_compressed_stencil', - 'DB_PERF_SEL_flush_expanded_stencil', - 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', - 'DB_PERF_SEL_flush_single_stencil', 'DB_PERF_SEL_his_tile_culled', - 'DB_PERF_SEL_hiz_tc_read_starved', - 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', - 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', - 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', - 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', - 'DB_PERF_SEL_postzl_partial_launch', - 'DB_PERF_SEL_postzl_partial_waiting', - 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', - 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', - 'DB_PERF_SEL_postzl_src_in_sends', - 'DB_PERF_SEL_postzl_src_in_squads', - 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 'DB_PERF_SEL_postzl_src_in_stall', - 'DB_PERF_SEL_postzl_src_in_tile_rate', - 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_postzl_src_out_stall', - 'DB_PERF_SEL_postzl_tile_init_stall', - 'DB_PERF_SEL_postzl_tile_mem_stall', - 'DB_PERF_SEL_prezl_src_in_sends', - 'DB_PERF_SEL_prezl_src_in_squads', - 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 'DB_PERF_SEL_prezl_src_in_stall', - 'DB_PERF_SEL_prezl_src_in_tile_rate', - 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_prezl_src_out_stall', - 'DB_PERF_SEL_prezl_tile_init_stall', - 'DB_PERF_SEL_prezl_tile_mem_stall', 'DB_PERF_SEL_qc_busy', - 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', - 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', - 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', - 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', - 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', - 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', - 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', - 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', - 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', - 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', - 'DB_PERF_SEL_tcp_dispatcher_flushes', - 'DB_PERF_SEL_tcp_dispatcher_reads', - 'DB_PERF_SEL_tcp_prefetcher_flushes', - 'DB_PERF_SEL_tcp_prefetcher_reads', - 'DB_PERF_SEL_tcp_preloader_flushes', - 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', - 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', - 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 'DB_PERF_SEL_tiles_decomp_on_expclear', - 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', - 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', - 'DB_PERF_SEL_tl_expand_squads', - 'DB_PERF_SEL_tl_flush_expand_squads', - 'DB_PERF_SEL_tl_in_fast_z_stall', - 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', - 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', - 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', - 'DB_PERF_SEL_tl_preZ_squads', - 'DB_PERF_SEL_tl_stencil_locked_stall', - 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', - 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', - 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', - 'DB_PERF_SEL_tsc_insert_summarize_stall', - 'DB_PERF_SEL_unmapped_z_tile_culled', - 'DB_PERF_SEL_zf_plane_multicycle', 'DB_PSINVOKE_CHANGE_EVENT', - 'DB_VPORT_CHANGED_EVENT', 'DCCG_AUDIO_DTO0_SOURCE_SEL', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', - 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 'DCCG_AUDIO_DTO_USE_512FBR_DTO', - 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DEEP_COLOR_CNTL', - 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', - 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', - 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', - 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', - 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', - 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', - 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', - 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', - 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', - 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', - 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_OTG4', 'DCCG_PERF_SEL_OTG5', - 'DCCG_PERF_SEL_RESERVED', 'DCC_CT_AUTO', 'DCC_CT_NONE', - 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', - 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', - 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', - 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', - 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_ALL_PWR_OK', - 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', - 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', - 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', - 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', - 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', - 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', - 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', - 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', - 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', - 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', - 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', - 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', - 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', - 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', - 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_DVO_VREFPON', - 'DCIOCHIP_DVO_VREFPON_DISABLE', 'DCIOCHIP_DVO_VREFPON_ENABLE', - 'DCIOCHIP_DVO_VREFSEL', 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', - 'DCIOCHIP_DVO_VREFSEL_ONCHIP', 'DCIOCHIP_ENABLE_2BIT', - 'DCIOCHIP_ENABLE_4BIT', 'DCIOCHIP_ENABLE_5BIT', - 'DCIOCHIP_GPIO_I2C_DISABLE', 'DCIOCHIP_GPIO_I2C_DRIVE', - 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', - 'DCIOCHIP_GPIO_I2C_EN', 'DCIOCHIP_GPIO_I2C_ENABLE', - 'DCIOCHIP_GPIO_I2C_MASK', 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', - 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', 'DCIOCHIP_GPIO_MASK_EN', - 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', - 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', - 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', - 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', - 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', - 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', - 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', - 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', - 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', - 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', - 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', - 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', - 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', - 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', - 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', - 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', - 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', - 'DCIOCHIP_REF_27_SRC_SEL', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', - 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', - 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', - 'DCIO_BL_PWM_CNTL_BL_PWM_EN', - 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', - 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', - 'DCIO_BL_PWM_FRACTIONAL_ENABLE', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', - 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', - 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', - 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', - 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', - 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', - 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', - 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', - 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', - 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', - 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', - 'DCIO_DC_GENERICB_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', - 'DCIO_DC_GPU_TIMER_READ_SELECT', - 'DCIO_DC_GPU_TIMER_START_POSITION', - 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', - 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', - 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', - 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', - 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', - 'DCIO_DPCS_INTERRUPT_TYPE', - 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', - 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', - 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', - 'DCIO_DSYNC_SOFT_RESET', 'DCIO_DSYNC_SOFT_RESET_ASSERT', - 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', - 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', - 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', - 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', - 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', - 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB', - 'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1', - 'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3', - 'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5', - 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', - 'DCIO_GENERICA_SEL_DACA_PIXCLK', - 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', - 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', - 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', - 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', - 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 'DCIO_GENERICA_SEL_GENERICA_DPRX', - 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', - 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', - 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', - 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', - 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', - 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', - 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', - 'DCIO_GENERICB_SEL_DACA_PIXCLK', - 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', - 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', - 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', - 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', - 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', - 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', - 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', - 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', - 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', - 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', - 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', - 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', - 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', - 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', - 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', - 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', - 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', - 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', - 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_IMPCAL_STEP_DELAY', - 'DCIO_IMPCAL_STEP_DELAY_10us', 'DCIO_IMPCAL_STEP_DELAY_11us', - 'DCIO_IMPCAL_STEP_DELAY_12us', 'DCIO_IMPCAL_STEP_DELAY_13us', - 'DCIO_IMPCAL_STEP_DELAY_14us', 'DCIO_IMPCAL_STEP_DELAY_15us', - 'DCIO_IMPCAL_STEP_DELAY_16us', 'DCIO_IMPCAL_STEP_DELAY_1us', - 'DCIO_IMPCAL_STEP_DELAY_2us', 'DCIO_IMPCAL_STEP_DELAY_3us', - 'DCIO_IMPCAL_STEP_DELAY_4us', 'DCIO_IMPCAL_STEP_DELAY_5us', - 'DCIO_IMPCAL_STEP_DELAY_6us', 'DCIO_IMPCAL_STEP_DELAY_7us', - 'DCIO_IMPCAL_STEP_DELAY_8us', 'DCIO_IMPCAL_STEP_DELAY_9us', - 'DCIO_LVTMA_BLON_OFF', 'DCIO_LVTMA_BLON_ON', - 'DCIO_LVTMA_BLON_POL_INVERT', 'DCIO_LVTMA_BLON_POL_NON_INVERT', - 'DCIO_LVTMA_DIGON_OFF', 'DCIO_LVTMA_DIGON_ON', - 'DCIO_LVTMA_DIGON_POL_INVERT', 'DCIO_LVTMA_DIGON_POL_NON_INVERT', - 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', - 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', - 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', - 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', - 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', - 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', - 'DCIO_LVTMA_SYNCEN_POL_INVERT', - 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', - 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', - 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', - 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', - 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', - 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', - 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', - 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', - 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', - 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', - 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', - 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', - 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', - 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', - 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', - 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', - 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', - 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', - 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', - 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', - 'DCIO_VIP_MUX_EN_VIP', 'DC_DMCUB_INT_TYPE', - 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', - 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', - 'DENORM_TRUNCATE', 'DEPTH_16', 'DEPTH_32_FLOAT', 'DEPTH_8_24', - 'DEPTH_8_24_FLOAT', 'DEPTH_INVALID', 'DEPTH_MICRO_TILING', - 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', 'DEPTH_X8_24_FLOAT', - 'DETILE_BUFFER_PACKER_ENABLE', 'DETILE_BUFFER_PACKER_IS_DISABLE', - 'DETILE_BUFFER_PACKER_IS_ENABLE', - 'DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'DET_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'DET_MEM_PWR_LIGHT_SLEEP_MODE', 'DFQ_MIN_FREE_ENTRIES', - 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', - 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', - 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', - 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', - 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', - 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', - 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', - 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', - 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', - 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', - 'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL', - 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', - 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', - 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', - 'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', - 'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', - 'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', - 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_SEL', - 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', - 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', - 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', - 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_FROM_OTG4', - 'DIG_FE_SOURCE_FROM_OTG5', 'DIG_FE_SOURCE_RESERVED', - 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', - 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', - 'DIG_FE_STEREOSYNC_FROM_OTG4', 'DIG_FE_STEREOSYNC_FROM_OTG5', - 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_ERROR_ACK', - 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', - 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', - 'DIG_FIFO_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', - 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', - 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 'DIG_INPUT_PIXEL_SEL', 'DIG_IN_DEBUG_MODE', - 'DIG_IN_NORMAL_OPERATION', 'DIG_ODD_PIXEL_ONLY', - 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', - 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', - 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', - 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', - 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', - 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', - 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIM_TYPE', 'DIM_TYPE_1D', - 'DIM_TYPE_2D', 'DIM_TYPE_3D', 'DIM_TYPE_RESERVED', - 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', - 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', - 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', - 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', - 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_FIFO_ERROR', - 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', - 'DIO_FIFO_ERROR_11', - 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', - 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', - 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', - 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_TF0', - 'DISABLE_TF1', 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', - 'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE', - 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', - 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', - 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DISPLAY_MICRO_TILING', 'DIV_2', - 'DIV_4', 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', - 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', - 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', - 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', - 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', - 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', - 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', - 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DI_SRC_SEL_RESERVED', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', - 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', - 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', - 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', - 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', - 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', - 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', - 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', - 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', - 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', - 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_WAS_UPDATED', - 'DMU_CLOCK_GATING_DISABLE', 'DMU_CLOCK_ON', - 'DMU_CLOCK_STATUS_OFF', 'DMU_CLOCK_STATUS_ON', - 'DMU_DC_GPU_TIMER_READ_SELECT', 'DMU_DC_GPU_TIMER_START_POSITION', - 'DMU_DISABLE_CLOCK_GATING', 'DMU_ENABLE_CLOCK_GATING', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75', - 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', - 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', - 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', - 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', - 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', - 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', - 'DOUT_I2C_ACK_TO_CLEAN', - 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_ABORT_XFER', - 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', - 'DOUT_I2C_CONTROL_DDC_SELECT', 'DOUT_I2C_CONTROL_GO', - 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', - 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', - 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', - 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', - 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', - 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', - 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', - 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', - 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', - 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 'DOUT_I2C_DDC_EDID_DETECT_STATUS', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', - 'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', - 'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', - 'DOUT_I2C_DDC_SPEED_THRESHOLD', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', - 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', - 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', - 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCSRX_BPHY_PCS_RX0_CLK', - 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', - 'DPCSRX_BPHY_PCS_RX3_CLK', - 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSTX_DVI_LINK_MODE', - 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER', - 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER', - 'DPCSTX_DVI_LINK_MODE_NORMAL', 'DPHY_8B10B_CUR_DISP', - 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', - 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', - 'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0', - 'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2', - 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS', - 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN', - 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED', - 'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED', - 'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK', - 'DPHY_CRC_MST_PHASE_ERROR_ACKED', - 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', - 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', - 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', - 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', - 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', - 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', - 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', - 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', - 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', - 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', - 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', - 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS', - 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', - 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', - 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', - 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', - 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', - 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', - 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', - 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', - 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_4096B', - 'DPTE_GROUP_SIZE_512B', 'DPTE_GROUP_SIZE_64B', - 'DPTE_GROUP_SIZE_8192B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', - 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', - 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', - 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', - 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED', - 'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 'DP_AUX_CONTROL_TEST_MODE_ENABLE', - 'DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', - 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', - 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', - 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', - 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', - 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', 'DP_AUX_PHY_WAKE_LOW_PRIORITY', - 'DP_AUX_PHY_WAKE_PRIORITY', 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', - 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', - 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', - 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 'DP_AUX_SW_CONTROL_LS_READ_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', - 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', - 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMBINE_FOUR_PIXEL', - 'DP_COMBINE_ONE_PIXEL', 'DP_COMBINE_PIXEL_NUM', - 'DP_COMBINE_TWO_PIXEL', 'DP_COMPONENT_DEPTH', - 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', - 'DP_COMPONENT_DEPTH_16BPC_RESERVED', 'DP_COMPONENT_DEPTH_6BPC', - 'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPONENT_DEPTH_RESERVED', - 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', - 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', - 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', - 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', - 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', - 'DP_DSC_444_SIMPLE_422', 'DP_DSC_DISABLE', 'DP_DSC_MODE', - 'DP_DSC_NATIVE_422_420', 'DP_DTO_DESPREAD_DISABLE', - 'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE', - 'DP_EMBEDDED_PANEL', 'DP_EMBEDDED_PANEL_MODE', - 'DP_EXTERNAL_PANEL', 'DP_LINK_TRAINING_ALREADY_COMPLETE', - 'DP_LINK_TRAINING_COMPLETE', 'DP_LINK_TRAINING_NOT_COMPLETE', - 'DP_LINK_TRAINING_SWITCH_MODE', 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', - 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', - 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', - 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', - 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', - 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', - 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', - 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', - 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', - 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', - 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', - 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', - 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_PIXEL_ENCODING', - 'DP_PIXEL_ENCODING_RESERVED', 'DP_PIXEL_ENCODING_RGB444', - 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', 'DP_PIXEL_ENCODING_YCBCR420', - 'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_YCBCR444', - 'DP_PIXEL_ENCODING_Y_ONLY', 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', - 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', - 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', - 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', - 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', - 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', - 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', - 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', - 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', - 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', - 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', - 'DP_SYNC_POLARITY', 'DP_SYNC_POLARITY_ACTIVE_HIGH', - 'DP_SYNC_POLARITY_ACTIVE_LOW', 'DP_TU_OVERFLOW_ACK', - 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', - 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', - 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', - 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', - 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', - 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', - 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', - 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', - 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', - 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', - 'DRR_UPDATE_LOCK_SEL', 'DRR_UPDATE_LOCK_SEL_0', - 'DRR_UPDATE_LOCK_SEL_1', 'DRR_UPDATE_LOCK_SEL_2', - 'DRR_UPDATE_LOCK_SEL_3', 'DRR_UPDATE_LOCK_SEL_4', - 'DRR_UPDATE_LOCK_SEL_5', 'DSCCIF_BITS_PER_COMPONENT_ENUM', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', - 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 'DSCC_BITS_PER_COMPONENT_ENUM', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCC_DSC_VERSION_MAJOR_ENUM', - 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', - 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', - 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', - 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', - 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', - 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', - 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', - 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', - 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', - 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', - 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', - 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', - 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', - 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', - 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', - 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', - 'DS_REF_SRC', 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_IN_PHASE', 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', - 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', - 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', - 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', - 'DWB_DATA_DEPTH_WARMUP_10BPC', 'DWB_DATA_DEPTH_WARMUP_8BPC', - 'DWB_DATA_DEPTH_WARMUP_ENUM', 'DWB_GMC_WARM_UP_DISABLE', - 'DWB_GMC_WARM_UP_ENABLE', 'DWB_GMC_WARM_UP_ENABLE_ENUM', - 'DWB_MODE_WARMUP_420', 'DWB_MODE_WARMUP_444', - 'DWB_MODE_WARMUP_ENUM', 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', - 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', - 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', - 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', - 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', - 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', - 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', - 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', - 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', - 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', - 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', - 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', - 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', - 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', - 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', - 'EFC_BGR101111_FLOAT', 'EFC_BGR565', - 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', - 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', - 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', - 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', - 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', - 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', - 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', - 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', - 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', - 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', - 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', - 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', - 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', - 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', - 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', - 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', - 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', - 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', - 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', - 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', - 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', - 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', - 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', - 'EIGHT_BANKS', 'EIGHT_FRAGMENTS', 'EIGHT_PIPES', - 'EIGHT_SHADER_ENGINS', 'ENABLE', 'ENABLE_CLOCK', 'ENABLE_ENUM', - 'ENABLE_ENUM_DISABLED', 'ENABLE_ENUM_ENABLED', - 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', - 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', - 'ENABLE_THE_FEATURE', 'ENABLE_THE_INTERRUPT', 'ENDIAN_8IN16', - 'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', - 'END_OF_PIPE_IB_END', 'END_OF_PIPE_INCR_DE', - 'ENGG_CSB_DELAY_BIN00', 'ENGG_CSB_DELAY_BIN01', - 'ENGG_CSB_DELAY_BIN02', 'ENGG_CSB_DELAY_BIN03', - 'ENGG_CSB_DELAY_BIN04', 'ENGG_CSB_DELAY_BIN05', - 'ENGG_CSB_DELAY_BIN06', 'ENGG_CSB_DELAY_BIN07', - 'ENGG_CSB_DELAY_BIN08', 'ENGG_CSB_DELAY_BIN09', - 'ENGG_CSB_DELAY_BIN10', 'ENGG_CSB_DELAY_BIN11', - 'ENGG_CSB_DELAY_BIN12', 'ENGG_CSB_DELAY_BIN13', - 'ENGG_CSB_DELAY_BIN14', 'ENGG_CSB_DELAY_BIN15', - 'ENGG_CSB_GE_INPUT_FIFO_FULL', 'ENGG_CSB_GE_SENDING_SUBGROUP', - 'ENGG_CSB_MACHINE_IS_STARVED', - 'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 'ENGG_CSB_MACHINE_STALLED_BY_SPI', - 'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL', 'ENGG_CSB_PRIM_COUNT_EQ0', - 'ENGG_CSB_SPI_DELAY_BIN00', 'ENGG_CSB_SPI_DELAY_BIN01', - 'ENGG_CSB_SPI_DELAY_BIN02', 'ENGG_CSB_SPI_DELAY_BIN03', - 'ENGG_CSB_SPI_DELAY_BIN04', 'ENGG_CSB_SPI_DELAY_BIN05', - 'ENGG_CSB_SPI_DELAY_BIN06', 'ENGG_CSB_SPI_DELAY_BIN07', - 'ENGG_CSB_SPI_DELAY_BIN08', 'ENGG_CSB_SPI_DELAY_BIN09', - 'ENGG_CSB_SPI_DELAY_BIN10', 'ENGG_CSB_SPI_DELAY_BIN11', - 'ENGG_CSB_SPI_DELAY_BIN12', 'ENGG_CSB_SPI_DELAY_BIN13', - 'ENGG_CSB_SPI_DELAY_BIN14', 'ENGG_CSB_SPI_DELAY_BIN15', - 'ENGG_CSB_SPI_INPUT_FIFO_FULL', - 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY', - 'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED', - 'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM', - 'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM', - 'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM', - 'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM', - 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', 'ENGG_INDEX_REQ_STARVED', - 'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 'ENGG_INDEX_RET_SXRX_READING_EVENT', - 'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS', - 'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS', - 'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO', 'ENGG_POS_REQ_STARVED', - 'ENUMS_GDS_PERFCOUNT_SELECT_H', 'ENUM_DPG_BIT_DEPTH', - 'ENUM_DPG_BIT_DEPTH_10BPC', 'ENUM_DPG_BIT_DEPTH_12BPC', - 'ENUM_DPG_BIT_DEPTH_6BPC', 'ENUM_DPG_BIT_DEPTH_8BPC', - 'ENUM_DPG_DISABLE', 'ENUM_DPG_DYNAMIC_RANGE', - 'ENUM_DPG_DYNAMIC_RANGE_CEA', 'ENUM_DPG_DYNAMIC_RANGE_VESA', - 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', 'ENUM_DPG_FIELD_POLARITY', - 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', - 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', - 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 'ENUM_FMT_PTI_FIELD_POLARITY', - 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', - 'ENUM_NUM_SIMD_PER_CU', 'ES_STAGE_DS', 'ES_STAGE_OFF', - 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', - 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', - 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', - 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', - 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', - 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', - 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', - 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', - 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', - 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', - 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FEC_ACTIVE_STATUS', - 'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', - 'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', - 'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', - 'FLIP_RATE_7', 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', - 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', - 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', - 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', - 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', - 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', - 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', 'FMT_1', - 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', - 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', - 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', - 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', - 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', - 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', - 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', - 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', - 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', - 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', - 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', - 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', - 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', - 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', - 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 'FMT_CLAMP_CNTL_COLOR_FORMAT', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', - 'FMT_CONTROL_PIXEL_ENCODING', - 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', - 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 'FMT_CONTROL_SUBSAMPLING_MODE', - 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', - 'FMT_CONTROL_SUBSAMPLING_ORDER', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', 'FMT_CTX1', - 'FMT_DYNAMIC_EXP_MODE', 'FMT_DYNAMIC_EXP_MODE_10to12', - 'FMT_DYNAMIC_EXP_MODE_8to12', 'FMT_FRAME_RANDOM_ENABLE_CONTROL', - 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_GB_GR', 'FMT_INVALID', - 'FMT_POWER_STATE_ENUM', 'FMT_POWER_STATE_ENUM_DS', - 'FMT_POWER_STATE_ENUM_LS', 'FMT_POWER_STATE_ENUM_ON', - 'FMT_POWER_STATE_ENUM_SD', 'FMT_RESERVED_33', 'FMT_RESERVED_36', - 'FMT_RESERVED_4', 'FMT_RESERVED_63', - 'FMT_RGB_RANDOM_ENABLE_CONTROL', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', - 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', - 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', - 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', - 'FMT_X24_8_32_FLOAT', 'FORCE_00', 'FORCE_BINNING_ON', - 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', - 'FORCE_ENABLE', 'FORCE_FF', 'FORCE_LATE_Z', - 'FORCE_LIGHT_SLEEP_REQ', 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', - 'FORCE_OPT_AUTO', 'FORCE_OPT_DISABLE', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', - 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', - 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', - 'FOUR_BANKS', 'FOUR_FRAGMENTS', 'FOUR_PIPES', 'FOUR_RB_PER_SE', - 'FOUR_SHADER_ENGINS', 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', - 'FRAG_GREATER', 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', - 'FRAG_NOTEQUAL', 'FULL_TILE_WAVE_BREAK_BC_ONLY', - 'FULL_TILE_WAVE_BREAK_BOTH', 'FULL_TILE_WAVE_BREAK_NBC_ONLY', - 'FULL_TILE_WAVE_BREAK_NONE', 'ForceControl', 'FullTileWaveBreak', - 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', - 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', - 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', - 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', - 'GB_EDC_DED_MODE_LOG', 'GCRPerfSel', 'GCR_PERF_SEL_ALL_REQ', - 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', - 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 'GCR_PERF_SEL_CPC_TCP_REQ', - 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', - 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 'GCR_PERF_SEL_CPF_TCP_REQ', - 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', - 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 'GCR_PERF_SEL_CPG_TCP_REQ', - 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', - 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', - 'GCR_PERF_SEL_VIRT_REQ', 'GDS_PERFCOUNT_SELECT', - 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', - 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', - 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', - 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', - 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', - 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', - 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', - 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', - 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', - 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', - 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', - 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', - 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', - 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', - 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', - 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', - 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', - 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', - 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', - 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', - 'GDS_PERF_SEL_WR_COMP', 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', - 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', - 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', - 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_D5', - 'GENERIC_STEREOSYNC_SEL_D6', 'GENERIC_STEREOSYNC_SEL_RESERVED', - 'GE_PERFCOUNT_SELECT', 'GL0V_CACHE_POLICIES', - 'GL0V_CACHE_POLICY_HIT_EVICT', 'GL0V_CACHE_POLICY_HIT_LRU', - 'GL0V_CACHE_POLICY_MISS_EVICT', 'GL0V_CACHE_POLICY_MISS_LRU', - 'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS', - 'GL1A_PERF_SEL_BUSY', 'GL1A_PERF_SEL_CYCLE', - 'GL1A_PERF_SEL_IO_32B_WDS_GL1C0', - 'GL1A_PERF_SEL_IO_32B_WDS_GL1C1', - 'GL1A_PERF_SEL_IO_32B_WDS_GL1C2', - 'GL1A_PERF_SEL_IO_32B_WDS_GL1C3', - 'GL1A_PERF_SEL_IO_32B_WDS_GL1C4', - 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0', - 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1', - 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2', - 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3', - 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4', - 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0', - 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1', - 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2', - 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3', - 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4', - 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0', - 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1', - 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2', - 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3', - 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4', - 'GL1A_PERF_SEL_REQUEST_GL1C0', 'GL1A_PERF_SEL_REQUEST_GL1C1', - 'GL1A_PERF_SEL_REQUEST_GL1C2', 'GL1A_PERF_SEL_REQUEST_GL1C3', - 'GL1A_PERF_SEL_REQUEST_GL1C4', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', - 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', - 'GL1A_PERF_SEL_STALL_GL1C4', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4', 'GL1CG_PERF_SEL', - 'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1CG_PERF_SEL_CYCLE', - 'GL1CG_PERF_SEL_GATE_EN1', 'GL1CG_PERF_SEL_GATE_EN2', - 'GL1CG_PERF_SEL_REQ', 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', - 'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1C_PERF_SEL', - 'GL1C_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1C_PERF_SEL_CYCLE', - 'GL1C_PERF_SEL_GATE_EN1', 'GL1C_PERF_SEL_GATE_EN2', - 'GL1C_PERF_SEL_REQ', 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', - 'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1_CACHE_POLICIES', - 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', - 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', - 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', - 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', - 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_GL2C0', - 'GL2A_PERF_SEL_REQ_BURST_GL2C1', 'GL2A_PERF_SEL_REQ_BURST_GL2C2', - 'GL2A_PERF_SEL_REQ_BURST_GL2C3', 'GL2A_PERF_SEL_REQ_BURST_GL2C4', - 'GL2A_PERF_SEL_REQ_BURST_GL2C5', 'GL2A_PERF_SEL_REQ_BURST_GL2C6', - 'GL2A_PERF_SEL_REQ_BURST_GL2C7', 'GL2A_PERF_SEL_REQ_GL2C0', - 'GL2A_PERF_SEL_REQ_GL2C1', 'GL2A_PERF_SEL_REQ_GL2C2', - 'GL2A_PERF_SEL_REQ_GL2C3', 'GL2A_PERF_SEL_REQ_GL2C4', - 'GL2A_PERF_SEL_REQ_GL2C5', 'GL2A_PERF_SEL_REQ_GL2C6', - 'GL2A_PERF_SEL_REQ_GL2C7', 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', - 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', - 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', - 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', - 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', - 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', - 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', - 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', - 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', - 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', - 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', - 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', - 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', - 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', - 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', - 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_RDREQ_128B', - 'GL2C_PERF_SEL_EA_RDREQ_32B', 'GL2C_PERF_SEL_EA_RDREQ_64B', - 'GL2C_PERF_SEL_EA_RDREQ_96B', 'GL2C_PERF_SEL_EA_RDREQ_DRAM', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', 'GL2C_PERF_SEL_EA_RDRET_NACK', - 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 'GL2C_PERF_SEL_EA_WRRET_NACK', 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', - 'GL2C_PERF_SEL_EVICT', 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', - 'GL2C_PERF_SEL_FULL_HIT', 'GL2C_PERF_SEL_GARLIC_READ', - 'GL2C_PERF_SEL_GARLIC_WRITE', 'GL2C_PERF_SEL_GCR_ALL', - 'GL2C_PERF_SEL_GCR_DISCARD', 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', - 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', - 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', - 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', - 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO', - 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', - 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', - 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', - 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', - 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', - 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', - 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_MDC_TAG_HIT', - 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 'GL2C_PERF_SEL_MDC_TAG_STALL', - 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', - 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', - 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', - 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', - 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', - 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', - 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', - 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', - 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', - 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', - 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', - 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', - 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', - 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', - 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', - 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', - 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', - 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', - 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', - 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', - 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_RLC', - 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', 'GL2_EA_CID_TCPMETA', - 'GL2_EA_CID_UTCL2', 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', - 'GL2_NACKS', 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', - 'GL2_NACK_PAGE_FAULT', 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', - 'GL2_OP_ATOMIC_ADD_32', 'GL2_OP_ATOMIC_ADD_64', - 'GL2_OP_ATOMIC_ADD_RTN_32', 'GL2_OP_ATOMIC_ADD_RTN_64', - 'GL2_OP_ATOMIC_AND_32', 'GL2_OP_ATOMIC_AND_64', - 'GL2_OP_ATOMIC_AND_RTN_32', 'GL2_OP_ATOMIC_AND_RTN_64', - 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', - 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', - 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', - 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', - 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', - 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', - 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', - 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', - 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', - 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', - 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', - 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', - 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', - 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', - 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', - 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', - 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', - 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', - 'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64', - 'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64', - 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', - 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', - 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', - 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', - 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', - 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', - 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_WRITE', - 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', - 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', - 'GLOBAL_STATUS_FLUSH_STATUS', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', - 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', - 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', - 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', - 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', - 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', - 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', - 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', - 'GRBM_PERF_SEL_CH_BUSY', 'GRBM_PERF_SEL_COUNT', - 'GRBM_PERF_SEL_CPAXI_BUSY', 'GRBM_PERF_SEL_CPC_BUSY', - 'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY', - 'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY', - 'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY', - 'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY', - 'GRBM_PERF_SEL_GDS_BUSY', 'GRBM_PERF_SEL_GE_BUSY', - 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', 'GRBM_PERF_SEL_GL1CC_BUSY', - 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', - 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', - 'GRBM_PERF_SEL_PH_BUSY', 'GRBM_PERF_SEL_PMM_BUSY', - 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', - 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', - 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', - 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RESERVED_7', - 'GRBM_PERF_SEL_RESERVED_8', 'GRBM_PERF_SEL_RESERVED_9', - 'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_RMI_BUSY', - 'GRBM_PERF_SEL_SC_BUSY', 'GRBM_PERF_SEL_SDMA_BUSY', - 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', - 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TCP_BUSY', - 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL1_BUSY', - 'GRBM_PERF_SEL_UTCL2_BUSY', 'GRBM_SE0_PERF_SEL', - 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', - 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', - 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', - 'GRBM_SE0_PERF_SEL_RESERVED_0', 'GRBM_SE0_PERF_SEL_RESERVED_1', - 'GRBM_SE0_PERF_SEL_RESERVED_2', 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', - 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', - 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', - 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', - 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_PA_BUSY', - 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', - 'GRBM_SE1_PERF_SEL_RESERVED_2', 'GRBM_SE1_PERF_SEL_RMI_BUSY', - 'GRBM_SE1_PERF_SEL_SC_BUSY', 'GRBM_SE1_PERF_SEL_SPI_BUSY', - 'GRBM_SE1_PERF_SEL_SX_BUSY', 'GRBM_SE1_PERF_SEL_TA_BUSY', - 'GRBM_SE1_PERF_SEL_TCP_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', 'GRBM_SE2_PERF_SEL', - 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', - 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', - 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', - 'GRBM_SE2_PERF_SEL_RESERVED_0', 'GRBM_SE2_PERF_SEL_RESERVED_1', - 'GRBM_SE2_PERF_SEL_RESERVED_2', 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', - 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', - 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', - 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', - 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_PA_BUSY', - 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', - 'GRBM_SE3_PERF_SEL_RESERVED_2', 'GRBM_SE3_PERF_SEL_RMI_BUSY', - 'GRBM_SE3_PERF_SEL_SC_BUSY', 'GRBM_SE3_PERF_SEL_SPI_BUSY', - 'GRBM_SE3_PERF_SEL_SX_BUSY', 'GRBM_SE3_PERF_SEL_TA_BUSY', - 'GRBM_SE3_PERF_SEL_TCP_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', - 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', - 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', - 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', - 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', - 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', - 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', - 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', - 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', - 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', - 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', - 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', - 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', - 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', - 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', - 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', - 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', - 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', - 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', - 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', - 'HDMI_AUDIO_INFO_SEND', - 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'HDMI_AUDIO_SEND_MAX_PACKETS', - 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DEEP_COLOR_DEPTH', - 'HDMI_DEEP_COLOR_DEPTH_24BPP', 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 'HDMI_DEEP_COLOR_DEPTH_36BPP', 'HDMI_DEEP_COLOR_DEPTH_48BPP', - 'HDMI_DEFAULT_PAHSE', 'HDMI_DEFAULT_PHASE_IS_0', - 'HDMI_DEFAULT_PHASE_IS_1', 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', - 'HDMI_ERROR_MASK', 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', - 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', - 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', - 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', - 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', - 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', - 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', - 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE', - 'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND', - 'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', - 'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE', - 'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', - 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', - 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', - 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', - 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', - 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', - 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', - 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', - 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', - 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', - 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', - 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', - 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16', - 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', - 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', - 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', - 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', - 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', - 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_GS', 'HS_STAGE_OFF', - 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', - 'HUBP_BLANK_SW_DEASSERT', 'HUBP_DISABLE', 'HUBP_DISABLED', - 'HUBP_ENABLED', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', - 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', - 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', - 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', - 'HUBP_XFC_CHUNK_SIZE_16KB', 'HUBP_XFC_CHUNK_SIZE_1KB', - 'HUBP_XFC_CHUNK_SIZE_256B', 'HUBP_XFC_CHUNK_SIZE_2KB', - 'HUBP_XFC_CHUNK_SIZE_32KB', 'HUBP_XFC_CHUNK_SIZE_4KB', - 'HUBP_XFC_CHUNK_SIZE_512B', 'HUBP_XFC_CHUNK_SIZE_8KB', - 'HUBP_XFC_CHUNK_SIZE_ENUM', 'HUBP_XFC_FRAME_MODE_ENUM', - 'HUBP_XFC_FULL_FRAME_MODE', 'HUBP_XFC_PARTIAL_FRAME_MODE', - 'HUBP_XFC_PIXEL_FORMAT_ENUM', 'HUBP_XFC_PIXEL_IS_32BPP', - 'HUBP_XFC_PIXEL_IS_64BPP', 'HW_MIRRORING_DISABLE', - 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', 'Hdp_SurfaceEndian', - 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', - 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', - 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', - 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', - 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', - 'IH_PERF_SEL_BIF_LINE0_FALLING', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF16', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF17', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF18', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF19', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF20', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF21', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF22', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF23', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF24', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF25', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF26', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF27', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF28', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF29', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF30', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 'IH_PERF_SEL_BIF_LINE0_RISING', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF16', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF17', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF18', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF19', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF20', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF21', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF22', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF23', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF24', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF25', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF26', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF27', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF28', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF29', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF30', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', - 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', - 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', - 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', - 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', - 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', - 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', - 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', - 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', - 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', - 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', - 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', - 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', - 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', - 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', - 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', - 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', - 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', - 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', - 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', - 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', - 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', - 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', - 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', - 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', - 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF16', - 'IH_PERF_SEL_RB0_FULL_VF17', 'IH_PERF_SEL_RB0_FULL_VF18', - 'IH_PERF_SEL_RB0_FULL_VF19', 'IH_PERF_SEL_RB0_FULL_VF2', - 'IH_PERF_SEL_RB0_FULL_VF20', 'IH_PERF_SEL_RB0_FULL_VF21', - 'IH_PERF_SEL_RB0_FULL_VF22', 'IH_PERF_SEL_RB0_FULL_VF23', - 'IH_PERF_SEL_RB0_FULL_VF24', 'IH_PERF_SEL_RB0_FULL_VF25', - 'IH_PERF_SEL_RB0_FULL_VF26', 'IH_PERF_SEL_RB0_FULL_VF27', - 'IH_PERF_SEL_RB0_FULL_VF28', 'IH_PERF_SEL_RB0_FULL_VF29', - 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF30', - 'IH_PERF_SEL_RB0_FULL_VF4', 'IH_PERF_SEL_RB0_FULL_VF5', - 'IH_PERF_SEL_RB0_FULL_VF6', 'IH_PERF_SEL_RB0_FULL_VF7', - 'IH_PERF_SEL_RB0_FULL_VF8', 'IH_PERF_SEL_RB0_FULL_VF9', - 'IH_PERF_SEL_RB0_LOAD_RPTR', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF16', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF17', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF18', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF20', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF21', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF22', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF23', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF24', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF25', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF26', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF27', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF28', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', - 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 'IH_PERF_SEL_RB0_OVERFLOW_VF16', 'IH_PERF_SEL_RB0_OVERFLOW_VF17', - 'IH_PERF_SEL_RB0_OVERFLOW_VF18', 'IH_PERF_SEL_RB0_OVERFLOW_VF19', - 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF20', - 'IH_PERF_SEL_RB0_OVERFLOW_VF21', 'IH_PERF_SEL_RB0_OVERFLOW_VF22', - 'IH_PERF_SEL_RB0_OVERFLOW_VF23', 'IH_PERF_SEL_RB0_OVERFLOW_VF24', - 'IH_PERF_SEL_RB0_OVERFLOW_VF25', 'IH_PERF_SEL_RB0_OVERFLOW_VF26', - 'IH_PERF_SEL_RB0_OVERFLOW_VF27', 'IH_PERF_SEL_RB0_OVERFLOW_VF28', - 'IH_PERF_SEL_RB0_OVERFLOW_VF29', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 'IH_PERF_SEL_RB0_OVERFLOW_VF30', 'IH_PERF_SEL_RB0_OVERFLOW_VF4', - 'IH_PERF_SEL_RB0_OVERFLOW_VF5', 'IH_PERF_SEL_RB0_OVERFLOW_VF6', - 'IH_PERF_SEL_RB0_OVERFLOW_VF7', 'IH_PERF_SEL_RB0_OVERFLOW_VF8', - 'IH_PERF_SEL_RB0_OVERFLOW_VF9', 'IH_PERF_SEL_RB0_RPTR_WRAP', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF16', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF17', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF18', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF20', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF21', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF22', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF23', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF24', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF25', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF26', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF27', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF28', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF16', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF17', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF18', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF20', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF21', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF22', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF23', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF24', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF25', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF26', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF27', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF28', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', - 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', - 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', - 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', - 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF16', - 'IH_PERF_SEL_RB1_FULL_VF17', 'IH_PERF_SEL_RB1_FULL_VF18', - 'IH_PERF_SEL_RB1_FULL_VF19', 'IH_PERF_SEL_RB1_FULL_VF2', - 'IH_PERF_SEL_RB1_FULL_VF20', 'IH_PERF_SEL_RB1_FULL_VF21', - 'IH_PERF_SEL_RB1_FULL_VF22', 'IH_PERF_SEL_RB1_FULL_VF23', - 'IH_PERF_SEL_RB1_FULL_VF24', 'IH_PERF_SEL_RB1_FULL_VF25', - 'IH_PERF_SEL_RB1_FULL_VF26', 'IH_PERF_SEL_RB1_FULL_VF27', - 'IH_PERF_SEL_RB1_FULL_VF28', 'IH_PERF_SEL_RB1_FULL_VF29', - 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF30', - 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', - 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', - 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', - 'IH_PERF_SEL_RB1_LOAD_RPTR', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF16', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF17', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF18', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF20', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF21', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF22', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF23', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF24', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF25', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF26', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF27', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF28', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', - 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 'IH_PERF_SEL_RB1_OVERFLOW_VF16', 'IH_PERF_SEL_RB1_OVERFLOW_VF17', - 'IH_PERF_SEL_RB1_OVERFLOW_VF18', 'IH_PERF_SEL_RB1_OVERFLOW_VF19', - 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF20', - 'IH_PERF_SEL_RB1_OVERFLOW_VF21', 'IH_PERF_SEL_RB1_OVERFLOW_VF22', - 'IH_PERF_SEL_RB1_OVERFLOW_VF23', 'IH_PERF_SEL_RB1_OVERFLOW_VF24', - 'IH_PERF_SEL_RB1_OVERFLOW_VF25', 'IH_PERF_SEL_RB1_OVERFLOW_VF26', - 'IH_PERF_SEL_RB1_OVERFLOW_VF27', 'IH_PERF_SEL_RB1_OVERFLOW_VF28', - 'IH_PERF_SEL_RB1_OVERFLOW_VF29', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 'IH_PERF_SEL_RB1_OVERFLOW_VF30', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF16', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF17', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF18', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF20', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF21', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF22', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF23', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF24', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF25', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF26', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF27', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF28', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF16', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF17', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF18', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF20', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF21', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF22', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF23', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF24', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF25', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF26', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF27', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF28', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', - 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', - 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', - 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', - 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF16', - 'IH_PERF_SEL_RB2_FULL_VF17', 'IH_PERF_SEL_RB2_FULL_VF18', - 'IH_PERF_SEL_RB2_FULL_VF19', 'IH_PERF_SEL_RB2_FULL_VF2', - 'IH_PERF_SEL_RB2_FULL_VF20', 'IH_PERF_SEL_RB2_FULL_VF21', - 'IH_PERF_SEL_RB2_FULL_VF22', 'IH_PERF_SEL_RB2_FULL_VF23', - 'IH_PERF_SEL_RB2_FULL_VF24', 'IH_PERF_SEL_RB2_FULL_VF25', - 'IH_PERF_SEL_RB2_FULL_VF26', 'IH_PERF_SEL_RB2_FULL_VF27', - 'IH_PERF_SEL_RB2_FULL_VF28', 'IH_PERF_SEL_RB2_FULL_VF29', - 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF30', - 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', - 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', - 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', - 'IH_PERF_SEL_RB2_LOAD_RPTR', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF16', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF17', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF18', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF20', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF21', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF22', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF23', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF24', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF25', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF26', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF27', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF28', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', - 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 'IH_PERF_SEL_RB2_OVERFLOW_VF16', 'IH_PERF_SEL_RB2_OVERFLOW_VF17', - 'IH_PERF_SEL_RB2_OVERFLOW_VF18', 'IH_PERF_SEL_RB2_OVERFLOW_VF19', - 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF20', - 'IH_PERF_SEL_RB2_OVERFLOW_VF21', 'IH_PERF_SEL_RB2_OVERFLOW_VF22', - 'IH_PERF_SEL_RB2_OVERFLOW_VF23', 'IH_PERF_SEL_RB2_OVERFLOW_VF24', - 'IH_PERF_SEL_RB2_OVERFLOW_VF25', 'IH_PERF_SEL_RB2_OVERFLOW_VF26', - 'IH_PERF_SEL_RB2_OVERFLOW_VF27', 'IH_PERF_SEL_RB2_OVERFLOW_VF28', - 'IH_PERF_SEL_RB2_OVERFLOW_VF29', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 'IH_PERF_SEL_RB2_OVERFLOW_VF30', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF16', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF17', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF18', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF20', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF21', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF22', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF23', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF24', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF25', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF26', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF27', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF28', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF16', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF17', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF18', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF20', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF21', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF22', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF23', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF24', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF25', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF26', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF27', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF28', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', - 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', - 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', - 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', - 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', - 'IH_VF_RB_SELECT_RESERVED', 'IMG_DATA_FORMAT', - 'IMG_DATA_FORMAT_1', 'IMG_DATA_FORMAT_10_10_10_2', - 'IMG_DATA_FORMAT_10_11_11', 'IMG_DATA_FORMAT_11_11_10', - 'IMG_DATA_FORMAT_16', 'IMG_DATA_FORMAT_16_16', - 'IMG_DATA_FORMAT_16_16_16_16', 'IMG_DATA_FORMAT_1_5_5_5', - 'IMG_DATA_FORMAT_1_REVERSED', 'IMG_DATA_FORMAT_24_8', - 'IMG_DATA_FORMAT_2_10_10_10', 'IMG_DATA_FORMAT_32', - 'IMG_DATA_FORMAT_32_32', 'IMG_DATA_FORMAT_32_32_32', - 'IMG_DATA_FORMAT_32_32_32_32', - 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', - 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', - 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', - 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', - 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', - 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', - 'IMG_DATA_FORMAT_BC1', 'IMG_DATA_FORMAT_BC2', - 'IMG_DATA_FORMAT_BC3', 'IMG_DATA_FORMAT_BC4', - 'IMG_DATA_FORMAT_BC5', 'IMG_DATA_FORMAT_BC6', - 'IMG_DATA_FORMAT_BC7', 'IMG_DATA_FORMAT_BG_RG', - 'IMG_DATA_FORMAT_FMASK16_S16_F1', 'IMG_DATA_FORMAT_FMASK16_S8_F2', - 'IMG_DATA_FORMAT_FMASK32_S16_F2', 'IMG_DATA_FORMAT_FMASK32_S8_F4', - 'IMG_DATA_FORMAT_FMASK32_S8_F8', 'IMG_DATA_FORMAT_FMASK64_S16_F4', - 'IMG_DATA_FORMAT_FMASK64_S16_F8', 'IMG_DATA_FORMAT_FMASK8_S2_F1', - 'IMG_DATA_FORMAT_FMASK8_S2_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F1', - 'IMG_DATA_FORMAT_FMASK8_S4_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F4', - 'IMG_DATA_FORMAT_FMASK8_S8_F1', 'IMG_DATA_FORMAT_GB_GR', - 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_MM_10_11_11', - 'IMG_DATA_FORMAT_MM_10_IN_16', 'IMG_DATA_FORMAT_MM_10_IN_16_16', - 'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16', - 'IMG_DATA_FORMAT_MM_16_16_16_16', 'IMG_DATA_FORMAT_MM_2_10_10_10', - 'IMG_DATA_FORMAT_MM_8', 'IMG_DATA_FORMAT_MM_8_8', - 'IMG_DATA_FORMAT_MM_8_8_8_8', 'IMG_DATA_FORMAT_MM_VYUY8', - 'IMG_DATA_FORMAT_RESERVED_100', 'IMG_DATA_FORMAT_RESERVED_101', - 'IMG_DATA_FORMAT_RESERVED_102', 'IMG_DATA_FORMAT_RESERVED_103', - 'IMG_DATA_FORMAT_RESERVED_104', 'IMG_DATA_FORMAT_RESERVED_105', - 'IMG_DATA_FORMAT_RESERVED_106', 'IMG_DATA_FORMAT_RESERVED_107', - 'IMG_DATA_FORMAT_RESERVED_108', 'IMG_DATA_FORMAT_RESERVED_109', - 'IMG_DATA_FORMAT_RESERVED_110', 'IMG_DATA_FORMAT_RESERVED_111', - 'IMG_DATA_FORMAT_RESERVED_112', 'IMG_DATA_FORMAT_RESERVED_113', - 'IMG_DATA_FORMAT_RESERVED_114', 'IMG_DATA_FORMAT_RESERVED_115', - 'IMG_DATA_FORMAT_RESERVED_116', 'IMG_DATA_FORMAT_RESERVED_117', - 'IMG_DATA_FORMAT_RESERVED_118', 'IMG_DATA_FORMAT_RESERVED_119', - 'IMG_DATA_FORMAT_RESERVED_120', 'IMG_DATA_FORMAT_RESERVED_121', - 'IMG_DATA_FORMAT_RESERVED_122', 'IMG_DATA_FORMAT_RESERVED_123', - 'IMG_DATA_FORMAT_RESERVED_124', 'IMG_DATA_FORMAT_RESERVED_125', - 'IMG_DATA_FORMAT_RESERVED_126', 'IMG_DATA_FORMAT_RESERVED_127', - 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_23', - 'IMG_DATA_FORMAT_RESERVED_24', 'IMG_DATA_FORMAT_RESERVED_25', - 'IMG_DATA_FORMAT_RESERVED_26', 'IMG_DATA_FORMAT_RESERVED_27', - 'IMG_DATA_FORMAT_RESERVED_28', 'IMG_DATA_FORMAT_RESERVED_29', - 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_42', - 'IMG_DATA_FORMAT_RESERVED_43', 'IMG_DATA_FORMAT_RESERVED_61', - 'IMG_DATA_FORMAT_RESERVED_62', 'IMG_DATA_FORMAT_RESERVED_75', - 'IMG_DATA_FORMAT_RESERVED_86', 'IMG_DATA_FORMAT_RESERVED_87', - 'IMG_DATA_FORMAT_RESERVED_88', 'IMG_DATA_FORMAT_RESERVED_89', - 'IMG_DATA_FORMAT_RESERVED_90', 'IMG_DATA_FORMAT_RESERVED_91', - 'IMG_DATA_FORMAT_RESERVED_92', 'IMG_DATA_FORMAT_RESERVED_93', - 'IMG_DATA_FORMAT_RESERVED_94', 'IMG_DATA_FORMAT_RESERVED_95', - 'IMG_DATA_FORMAT_RESERVED_96', 'IMG_DATA_FORMAT_RESERVED_97', - 'IMG_DATA_FORMAT_RESERVED_98', 'IMG_DATA_FORMAT_RESERVED_99', - 'IMG_DATA_FORMAT_X24_8_32', 'IMG_FMT', 'IMG_FMT_10_10_10_2_SINT', - 'IMG_FMT_10_10_10_2_SNORM', 'IMG_FMT_10_10_10_2_SSCALED', - 'IMG_FMT_10_10_10_2_UINT', 'IMG_FMT_10_10_10_2_UNORM', - 'IMG_FMT_10_10_10_2_USCALED', 'IMG_FMT_10_11_11_FLOAT', - 'IMG_FMT_10_11_11_SINT', 'IMG_FMT_10_11_11_SNORM', - 'IMG_FMT_10_11_11_SSCALED', 'IMG_FMT_10_11_11_UINT', - 'IMG_FMT_10_11_11_UNORM', 'IMG_FMT_10_11_11_USCALED', - 'IMG_FMT_11_11_10_FLOAT', 'IMG_FMT_11_11_10_SINT', - 'IMG_FMT_11_11_10_SNORM', 'IMG_FMT_11_11_10_SSCALED', - 'IMG_FMT_11_11_10_UINT', 'IMG_FMT_11_11_10_UNORM', - 'IMG_FMT_11_11_10_USCALED', 'IMG_FMT_16_16_16_16_FLOAT', - 'IMG_FMT_16_16_16_16_SINT', 'IMG_FMT_16_16_16_16_SNORM', - 'IMG_FMT_16_16_16_16_SSCALED', 'IMG_FMT_16_16_16_16_UINT', - 'IMG_FMT_16_16_16_16_UNORM', 'IMG_FMT_16_16_16_16_USCALED', - 'IMG_FMT_16_16_FLOAT', 'IMG_FMT_16_16_SINT', - 'IMG_FMT_16_16_SNORM', 'IMG_FMT_16_16_SSCALED', - 'IMG_FMT_16_16_UINT', 'IMG_FMT_16_16_UNORM', - 'IMG_FMT_16_16_USCALED', 'IMG_FMT_16_FLOAT', 'IMG_FMT_16_SINT', - 'IMG_FMT_16_SNORM', 'IMG_FMT_16_SSCALED', 'IMG_FMT_16_UINT', - 'IMG_FMT_16_UNORM', 'IMG_FMT_16_USCALED', 'IMG_FMT_1_5_5_5_UNORM', - 'IMG_FMT_1_REVERSED_UNORM', 'IMG_FMT_1_UNORM', - 'IMG_FMT_24_8_UINT', 'IMG_FMT_24_8_UNORM', - 'IMG_FMT_2_10_10_10_SINT', 'IMG_FMT_2_10_10_10_SNORM', - 'IMG_FMT_2_10_10_10_SSCALED', 'IMG_FMT_2_10_10_10_UINT', - 'IMG_FMT_2_10_10_10_UNORM', 'IMG_FMT_2_10_10_10_USCALED', - 'IMG_FMT_32_32_32_32_FLOAT', 'IMG_FMT_32_32_32_32_SINT', - 'IMG_FMT_32_32_32_32_UINT', 'IMG_FMT_32_32_32_FLOAT', - 'IMG_FMT_32_32_32_SINT', 'IMG_FMT_32_32_32_UINT', - 'IMG_FMT_32_32_FLOAT', 'IMG_FMT_32_32_SINT', 'IMG_FMT_32_32_UINT', - 'IMG_FMT_32_FLOAT', 'IMG_FMT_32_FLOAT_CLAMP', 'IMG_FMT_32_SINT', - 'IMG_FMT_32_UINT', 'IMG_FMT_4_4_4_4_UNORM', 'IMG_FMT_4_4_UNORM', - 'IMG_FMT_5_5_5_1_UNORM', 'IMG_FMT_5_6_5_UNORM', - 'IMG_FMT_5_9_9_9_FLOAT', 'IMG_FMT_6E4_FLOAT', 'IMG_FMT_8_24_UINT', - 'IMG_FMT_8_24_UNORM', 'IMG_FMT_8_8_8_8_SINT', - 'IMG_FMT_8_8_8_8_SNORM', 'IMG_FMT_8_8_8_8_SRGB', - 'IMG_FMT_8_8_8_8_SSCALED', 'IMG_FMT_8_8_8_8_UINT', - 'IMG_FMT_8_8_8_8_UNORM', 'IMG_FMT_8_8_8_8_USCALED', - 'IMG_FMT_8_8_SINT', 'IMG_FMT_8_8_SNORM', 'IMG_FMT_8_8_SRGB', - 'IMG_FMT_8_8_SSCALED', 'IMG_FMT_8_8_UINT', 'IMG_FMT_8_8_UNORM', - 'IMG_FMT_8_8_USCALED', 'IMG_FMT_8_SINT', 'IMG_FMT_8_SNORM', - 'IMG_FMT_8_SRGB', 'IMG_FMT_8_SSCALED', 'IMG_FMT_8_UINT', - 'IMG_FMT_8_UNORM', 'IMG_FMT_8_USCALED', 'IMG_FMT_BC1_SRGB', - 'IMG_FMT_BC1_UNORM', 'IMG_FMT_BC2_SRGB', 'IMG_FMT_BC2_UNORM', - 'IMG_FMT_BC3_SRGB', 'IMG_FMT_BC3_UNORM', 'IMG_FMT_BC4_SNORM', - 'IMG_FMT_BC4_UNORM', 'IMG_FMT_BC5_SNORM', 'IMG_FMT_BC5_UNORM', - 'IMG_FMT_BC6_SFLOAT', 'IMG_FMT_BC6_UFLOAT', 'IMG_FMT_BC7_SRGB', - 'IMG_FMT_BC7_UNORM', 'IMG_FMT_BG_RG_SNORM', 'IMG_FMT_BG_RG_SRGB', - 'IMG_FMT_BG_RG_UINT', 'IMG_FMT_BG_RG_UNORM', - 'IMG_FMT_FMASK16_S16_F1', 'IMG_FMT_FMASK16_S8_F2', - 'IMG_FMT_FMASK32_S16_F2', 'IMG_FMT_FMASK32_S8_F4', - 'IMG_FMT_FMASK32_S8_F8', 'IMG_FMT_FMASK64_S16_F4', - 'IMG_FMT_FMASK64_S16_F8', 'IMG_FMT_FMASK8_S2_F1', - 'IMG_FMT_FMASK8_S2_F2', 'IMG_FMT_FMASK8_S4_F1', - 'IMG_FMT_FMASK8_S4_F2', 'IMG_FMT_FMASK8_S4_F4', - 'IMG_FMT_FMASK8_S8_F1', 'IMG_FMT_GB_GR_SNORM', - 'IMG_FMT_GB_GR_SRGB', 'IMG_FMT_GB_GR_UINT', 'IMG_FMT_GB_GR_UNORM', - 'IMG_FMT_INVALID', 'IMG_FMT_MM_10_11_11_UINT', - 'IMG_FMT_MM_10_11_11_UNORM', 'IMG_FMT_MM_10_IN_16_16_16_16_UINT', - 'IMG_FMT_MM_10_IN_16_16_16_16_UNORM', - 'IMG_FMT_MM_10_IN_16_16_UINT', 'IMG_FMT_MM_10_IN_16_16_UNORM', - 'IMG_FMT_MM_10_IN_16_UINT', 'IMG_FMT_MM_10_IN_16_UNORM', - 'IMG_FMT_MM_16_16_16_16_UINT', 'IMG_FMT_MM_16_16_16_16_UNORM', - 'IMG_FMT_MM_2_10_10_10_UINT', 'IMG_FMT_MM_2_10_10_10_UNORM', - 'IMG_FMT_MM_8_8_8_8_UINT', 'IMG_FMT_MM_8_8_8_8_UNORM', - 'IMG_FMT_MM_8_8_UINT', 'IMG_FMT_MM_8_8_UNORM', - 'IMG_FMT_MM_8_UINT', 'IMG_FMT_MM_8_UNORM', - 'IMG_FMT_MM_VYUY8_UINT', 'IMG_FMT_MM_VYUY8_UNORM', - 'IMG_FMT_RESERVED_100', 'IMG_FMT_RESERVED_101', - 'IMG_FMT_RESERVED_102', 'IMG_FMT_RESERVED_103', - 'IMG_FMT_RESERVED_104', 'IMG_FMT_RESERVED_105', - 'IMG_FMT_RESERVED_106', 'IMG_FMT_RESERVED_107', - 'IMG_FMT_RESERVED_108', 'IMG_FMT_RESERVED_109', - 'IMG_FMT_RESERVED_110', 'IMG_FMT_RESERVED_111', - 'IMG_FMT_RESERVED_112', 'IMG_FMT_RESERVED_113', - 'IMG_FMT_RESERVED_114', 'IMG_FMT_RESERVED_115', - 'IMG_FMT_RESERVED_116', 'IMG_FMT_RESERVED_117', - 'IMG_FMT_RESERVED_118', 'IMG_FMT_RESERVED_119', - 'IMG_FMT_RESERVED_120', 'IMG_FMT_RESERVED_121', - 'IMG_FMT_RESERVED_122', 'IMG_FMT_RESERVED_123', - 'IMG_FMT_RESERVED_124', 'IMG_FMT_RESERVED_125', - 'IMG_FMT_RESERVED_126', 'IMG_FMT_RESERVED_127', - 'IMG_FMT_RESERVED_155', 'IMG_FMT_RESERVED_285', - 'IMG_FMT_RESERVED_286', 'IMG_FMT_RESERVED_287', - 'IMG_FMT_RESERVED_288', 'IMG_FMT_RESERVED_289', - 'IMG_FMT_RESERVED_290', 'IMG_FMT_RESERVED_291', - 'IMG_FMT_RESERVED_292', 'IMG_FMT_RESERVED_293', - 'IMG_FMT_RESERVED_294', 'IMG_FMT_RESERVED_295', - 'IMG_FMT_RESERVED_296', 'IMG_FMT_RESERVED_297', - 'IMG_FMT_RESERVED_298', 'IMG_FMT_RESERVED_299', - 'IMG_FMT_RESERVED_300', 'IMG_FMT_RESERVED_301', - 'IMG_FMT_RESERVED_302', 'IMG_FMT_RESERVED_303', - 'IMG_FMT_RESERVED_304', 'IMG_FMT_RESERVED_305', - 'IMG_FMT_RESERVED_306', 'IMG_FMT_RESERVED_307', - 'IMG_FMT_RESERVED_308', 'IMG_FMT_RESERVED_309', - 'IMG_FMT_RESERVED_310', 'IMG_FMT_RESERVED_311', - 'IMG_FMT_RESERVED_312', 'IMG_FMT_RESERVED_313', - 'IMG_FMT_RESERVED_314', 'IMG_FMT_RESERVED_315', - 'IMG_FMT_RESERVED_316', 'IMG_FMT_RESERVED_317', - 'IMG_FMT_RESERVED_318', 'IMG_FMT_RESERVED_319', - 'IMG_FMT_RESERVED_320', 'IMG_FMT_RESERVED_321', - 'IMG_FMT_RESERVED_322', 'IMG_FMT_RESERVED_323', - 'IMG_FMT_RESERVED_324', 'IMG_FMT_RESERVED_325', - 'IMG_FMT_RESERVED_326', 'IMG_FMT_RESERVED_327', - 'IMG_FMT_RESERVED_328', 'IMG_FMT_RESERVED_329', - 'IMG_FMT_RESERVED_330', 'IMG_FMT_RESERVED_331', - 'IMG_FMT_RESERVED_332', 'IMG_FMT_RESERVED_333', - 'IMG_FMT_RESERVED_334', 'IMG_FMT_RESERVED_335', - 'IMG_FMT_RESERVED_336', 'IMG_FMT_RESERVED_337', - 'IMG_FMT_RESERVED_338', 'IMG_FMT_RESERVED_339', - 'IMG_FMT_RESERVED_340', 'IMG_FMT_RESERVED_341', - 'IMG_FMT_RESERVED_342', 'IMG_FMT_RESERVED_343', - 'IMG_FMT_RESERVED_344', 'IMG_FMT_RESERVED_345', - 'IMG_FMT_RESERVED_346', 'IMG_FMT_RESERVED_347', - 'IMG_FMT_RESERVED_348', 'IMG_FMT_RESERVED_349', - 'IMG_FMT_RESERVED_350', 'IMG_FMT_RESERVED_351', - 'IMG_FMT_RESERVED_352', 'IMG_FMT_RESERVED_353', - 'IMG_FMT_RESERVED_354', 'IMG_FMT_RESERVED_355', - 'IMG_FMT_RESERVED_356', 'IMG_FMT_RESERVED_357', - 'IMG_FMT_RESERVED_358', 'IMG_FMT_RESERVED_359', - 'IMG_FMT_RESERVED_360', 'IMG_FMT_RESERVED_361', - 'IMG_FMT_RESERVED_362', 'IMG_FMT_RESERVED_363', - 'IMG_FMT_RESERVED_364', 'IMG_FMT_RESERVED_365', - 'IMG_FMT_RESERVED_366', 'IMG_FMT_RESERVED_367', - 'IMG_FMT_RESERVED_368', 'IMG_FMT_RESERVED_369', - 'IMG_FMT_RESERVED_370', 'IMG_FMT_RESERVED_371', - 'IMG_FMT_RESERVED_372', 'IMG_FMT_RESERVED_373', - 'IMG_FMT_RESERVED_374', 'IMG_FMT_RESERVED_375', - 'IMG_FMT_RESERVED_376', 'IMG_FMT_RESERVED_377', - 'IMG_FMT_RESERVED_378', 'IMG_FMT_RESERVED_379', - 'IMG_FMT_RESERVED_380', 'IMG_FMT_RESERVED_381', - 'IMG_FMT_RESERVED_382', 'IMG_FMT_RESERVED_383', - 'IMG_FMT_RESERVED_384', 'IMG_FMT_RESERVED_385', - 'IMG_FMT_RESERVED_386', 'IMG_FMT_RESERVED_387', - 'IMG_FMT_RESERVED_388', 'IMG_FMT_RESERVED_389', - 'IMG_FMT_RESERVED_390', 'IMG_FMT_RESERVED_391', - 'IMG_FMT_RESERVED_392', 'IMG_FMT_RESERVED_393', - 'IMG_FMT_RESERVED_394', 'IMG_FMT_RESERVED_395', - 'IMG_FMT_RESERVED_396', 'IMG_FMT_RESERVED_397', - 'IMG_FMT_RESERVED_398', 'IMG_FMT_RESERVED_399', - 'IMG_FMT_RESERVED_400', 'IMG_FMT_RESERVED_401', - 'IMG_FMT_RESERVED_402', 'IMG_FMT_RESERVED_403', - 'IMG_FMT_RESERVED_404', 'IMG_FMT_RESERVED_405', - 'IMG_FMT_RESERVED_406', 'IMG_FMT_RESERVED_407', - 'IMG_FMT_RESERVED_408', 'IMG_FMT_RESERVED_409', - 'IMG_FMT_RESERVED_410', 'IMG_FMT_RESERVED_411', - 'IMG_FMT_RESERVED_412', 'IMG_FMT_RESERVED_413', - 'IMG_FMT_RESERVED_414', 'IMG_FMT_RESERVED_415', - 'IMG_FMT_RESERVED_416', 'IMG_FMT_RESERVED_417', - 'IMG_FMT_RESERVED_418', 'IMG_FMT_RESERVED_419', - 'IMG_FMT_RESERVED_420', 'IMG_FMT_RESERVED_421', - 'IMG_FMT_RESERVED_422', 'IMG_FMT_RESERVED_423', - 'IMG_FMT_RESERVED_424', 'IMG_FMT_RESERVED_425', - 'IMG_FMT_RESERVED_426', 'IMG_FMT_RESERVED_427', - 'IMG_FMT_RESERVED_428', 'IMG_FMT_RESERVED_429', - 'IMG_FMT_RESERVED_430', 'IMG_FMT_RESERVED_431', - 'IMG_FMT_RESERVED_432', 'IMG_FMT_RESERVED_433', - 'IMG_FMT_RESERVED_434', 'IMG_FMT_RESERVED_435', - 'IMG_FMT_RESERVED_436', 'IMG_FMT_RESERVED_437', - 'IMG_FMT_RESERVED_438', 'IMG_FMT_RESERVED_439', - 'IMG_FMT_RESERVED_440', 'IMG_FMT_RESERVED_441', - 'IMG_FMT_RESERVED_442', 'IMG_FMT_RESERVED_443', - 'IMG_FMT_RESERVED_444', 'IMG_FMT_RESERVED_445', - 'IMG_FMT_RESERVED_446', 'IMG_FMT_RESERVED_447', - 'IMG_FMT_RESERVED_448', 'IMG_FMT_RESERVED_449', - 'IMG_FMT_RESERVED_450', 'IMG_FMT_RESERVED_451', - 'IMG_FMT_RESERVED_452', 'IMG_FMT_RESERVED_453', - 'IMG_FMT_RESERVED_454', 'IMG_FMT_RESERVED_455', - 'IMG_FMT_RESERVED_456', 'IMG_FMT_RESERVED_457', - 'IMG_FMT_RESERVED_458', 'IMG_FMT_RESERVED_459', - 'IMG_FMT_RESERVED_460', 'IMG_FMT_RESERVED_461', - 'IMG_FMT_RESERVED_462', 'IMG_FMT_RESERVED_463', - 'IMG_FMT_RESERVED_464', 'IMG_FMT_RESERVED_465', - 'IMG_FMT_RESERVED_466', 'IMG_FMT_RESERVED_467', - 'IMG_FMT_RESERVED_468', 'IMG_FMT_RESERVED_469', - 'IMG_FMT_RESERVED_470', 'IMG_FMT_RESERVED_471', - 'IMG_FMT_RESERVED_472', 'IMG_FMT_RESERVED_473', - 'IMG_FMT_RESERVED_474', 'IMG_FMT_RESERVED_475', - 'IMG_FMT_RESERVED_476', 'IMG_FMT_RESERVED_477', - 'IMG_FMT_RESERVED_478', 'IMG_FMT_RESERVED_479', - 'IMG_FMT_RESERVED_480', 'IMG_FMT_RESERVED_481', - 'IMG_FMT_RESERVED_482', 'IMG_FMT_RESERVED_483', - 'IMG_FMT_RESERVED_484', 'IMG_FMT_RESERVED_485', - 'IMG_FMT_RESERVED_486', 'IMG_FMT_RESERVED_487', - 'IMG_FMT_RESERVED_488', 'IMG_FMT_RESERVED_489', - 'IMG_FMT_RESERVED_490', 'IMG_FMT_RESERVED_491', - 'IMG_FMT_RESERVED_492', 'IMG_FMT_RESERVED_493', - 'IMG_FMT_RESERVED_494', 'IMG_FMT_RESERVED_495', - 'IMG_FMT_RESERVED_496', 'IMG_FMT_RESERVED_497', - 'IMG_FMT_RESERVED_498', 'IMG_FMT_RESERVED_499', - 'IMG_FMT_RESERVED_500', 'IMG_FMT_RESERVED_501', - 'IMG_FMT_RESERVED_502', 'IMG_FMT_RESERVED_503', - 'IMG_FMT_RESERVED_504', 'IMG_FMT_RESERVED_505', - 'IMG_FMT_RESERVED_506', 'IMG_FMT_RESERVED_507', - 'IMG_FMT_RESERVED_508', 'IMG_FMT_RESERVED_509', - 'IMG_FMT_RESERVED_510', 'IMG_FMT_RESERVED_511', - 'IMG_FMT_RESERVED_78', 'IMG_FMT_RESERVED_79', - 'IMG_FMT_RESERVED_80', 'IMG_FMT_RESERVED_81', - 'IMG_FMT_RESERVED_82', 'IMG_FMT_RESERVED_83', - 'IMG_FMT_RESERVED_84', 'IMG_FMT_RESERVED_85', - 'IMG_FMT_RESERVED_86', 'IMG_FMT_RESERVED_87', - 'IMG_FMT_RESERVED_88', 'IMG_FMT_RESERVED_89', - 'IMG_FMT_RESERVED_90', 'IMG_FMT_RESERVED_91', - 'IMG_FMT_RESERVED_92', 'IMG_FMT_RESERVED_93', - 'IMG_FMT_RESERVED_94', 'IMG_FMT_RESERVED_95', - 'IMG_FMT_RESERVED_96', 'IMG_FMT_RESERVED_97', - 'IMG_FMT_RESERVED_98', 'IMG_FMT_RESERVED_99', - 'IMG_FMT_X24_8_32_FLOAT', 'IMG_FMT_X24_8_32_UINT', - 'IMG_NUM_FORMAT', 'IMG_NUM_FORMAT_FLOAT', 'IMG_NUM_FORMAT_FMASK', - 'IMG_NUM_FORMAT_FMASK_16_16_1', 'IMG_NUM_FORMAT_FMASK_16_8_2', - 'IMG_NUM_FORMAT_FMASK_32_16_2', 'IMG_NUM_FORMAT_FMASK_32_8_4', - 'IMG_NUM_FORMAT_FMASK_32_8_8', 'IMG_NUM_FORMAT_FMASK_64_16_4', - 'IMG_NUM_FORMAT_FMASK_64_16_8', 'IMG_NUM_FORMAT_FMASK_8_2_1', - 'IMG_NUM_FORMAT_FMASK_8_2_2', 'IMG_NUM_FORMAT_FMASK_8_4_1', - 'IMG_NUM_FORMAT_FMASK_8_4_2', 'IMG_NUM_FORMAT_FMASK_8_4_4', - 'IMG_NUM_FORMAT_FMASK_8_8_1', 'IMG_NUM_FORMAT_FMASK_RESERVED_13', - 'IMG_NUM_FORMAT_FMASK_RESERVED_14', - 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', - 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', - 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', - 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', - 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SNORM_NZ', - 'IMG_NUM_FORMAT_SRGB', 'IMG_NUM_FORMAT_SSCALED', - 'IMG_NUM_FORMAT_UBINT', 'IMG_NUM_FORMAT_UBNORM', - 'IMG_NUM_FORMAT_UBNORM_NZ', 'IMG_NUM_FORMAT_UBSCALED', - 'IMG_NUM_FORMAT_UINT', 'IMG_NUM_FORMAT_UNORM', - 'IMG_NUM_FORMAT_USCALED', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', - 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', - 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', - 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', - 'INTERRUPT_LINE_ASSERTED', 'INTERRUPT_LINE_NOT_ASSERTED', - 'INT_DISABLED', 'INT_ENABLED', 'INT_LEVEL', 'INT_MASK', - 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', 'IP_USB_PD_REVISION_ID', - 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', - 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', - 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', - 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', - 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', - 'LB_INTERLEAVE_ENABLE', 'LEFT_EYE', 'LEGACY_NUM_BANKS', - 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', - 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LS_STAGE_OFF', - 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B', - 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT', - 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B', - 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B', - 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT', - 'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT', - 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', - 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'MACRO_TILE_ASPECT', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', - 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', - 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', - 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_4', - 'MASTER_UPDATE_LOCK_SEL_5', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 'MAX_COMPRESSED_FRAGS', 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', - 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', - 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', - 'MEM_PWR_SEL_CTRL2', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', - 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', - 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_4', - 'METADATA_HUBP_SEL_5', 'METADATA_HUBP_SEL_RESERVED', - 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', - 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', - 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', - 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', - 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', - 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', - 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_NEW', - 'MICRO_TILE_MODE_RENDER_TARGET', 'MICRO_TILE_MODE_STD_2D', - 'MICRO_TILE_MODE_STD_3D', 'MICRO_TILE_MODE_Z', - 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', - 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', - 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', - 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', - 'MIN_META_CHUNK_SIZE_64B', 'MMHUBBUB_XFC_FRAME_MODE_ENUM', - 'MMHUBBUB_XFC_FULL_FRAME_MODE', 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE', - 'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM', 'MMHUBBUB_XFC_PIXEL_IS_32BPP', - 'MMHUBBUB_XFC_PIXEL_IS_64BPP', - 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM', - 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB', - 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB', - 'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS', - 'MMHUBBUB_XFC_XFCMON_MODE_ENUM', - 'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT', - 'MMHUBBUB_XFC_XFCMON_MODE_PERIODS', 'MONO_10LSB', 'MONO_10MSB', - 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', - 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', - 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', - 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', - 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', - 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_1', 'MPCC_OGAM_MODE_2', - 'MPCC_OGAM_MODE_MPCC_OGAM_MODE', 'MPCC_OGAM_MODE_RSV', - 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE', - 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', - 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', - 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', - 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', - 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', - 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', - 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', - 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', - 'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13', - 'MPC_OCSC_COEF_FORMAT_S3_12', 'MPC_OUT_CSC_MODE', - 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', 'MPC_OUT_CSC_MODE_2', - 'MPC_OUT_CSC_MODE_RSV', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', - 'MPC_OUT_RATE_CONTROL_DISABLE_SET', - 'MPC_OUT_RATE_CONTROL_SET_DISABLE', - 'MPC_OUT_RATE_CONTROL_SET_ENABLE', 'MPTE_GROUP_SIZE', - 'MPTE_GROUP_SIZE_1024B', 'MPTE_GROUP_SIZE_128B', - 'MPTE_GROUP_SIZE_2048B', 'MPTE_GROUP_SIZE_256B', - 'MPTE_GROUP_SIZE_4096B', 'MPTE_GROUP_SIZE_512B', - 'MPTE_GROUP_SIZE_64B', 'MPTE_GROUP_SIZE_8192B', - 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', - 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', - 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', - 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', - 'MULT_16', 'MULT_8', 'MacroTileAspect', 'MemArbMode', - 'MicroTileMode', 'MultiGPUTileSize', 'NON_BYPASS', 'NOT_SENT', - 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', - 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', - 'NO_OUTSTANDING_REQ', 'NUMBER_FLOAT', 'NUMBER_SINT', - 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', - 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_BANKS', - 'NUM_BANKS_BC_ENUM', 'NUM_PIPES', 'NUM_PIPES_BC_ENUM', - 'NUM_RB_PER_SE', 'NUM_SE', 'NUM_SIMD_PER_CU', - 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', - 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', - 'NumRbPerShaderEngine', 'NumShaderEngines', 'OBUF_BYPASS_DIS', - 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', - 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', - 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', - 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', - 'ONE_BANK', 'ONE_FRAGMENT', 'ONE_PIPE', 'ONE_RB_PER_SE', - 'ONE_SHADER_ENGIN', 'ON_SEQ', 'OPP_PIPE_CLOCK_DISABLE', - 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', - 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', - 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 'OPP_PIPE_CRC_INTERLACE_MODE', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', - 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', - 'OPP_PIPE_CRC_PIXEL_SELECT', - 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', - 'OPP_PIPE_CRC_STEREO_MODE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', - 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', 'OPP_TEST_CLK_SEL_DISPCLK_OPP4', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP5', 'OPP_TEST_CLK_SEL_DISPCLK_P', - 'OPP_TEST_CLK_SEL_DISPCLK_R', 'OPP_TEST_CLK_SEL_RESERVED0', - 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', - 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', - 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', - 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', - 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', - 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', - 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', - 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN', - 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE', - 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE', - 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE', - 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE', - 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED', - 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE', - 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE', - 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', - 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_SOF_PULL_EN', - 'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE', - 'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE', - 'OTG_CONTROL_OTG_START_POINT_CNTL', - 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', - 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3', - 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE', - 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE', - 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE', - 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_EN', - 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', - 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', - 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE', - 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', - 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', - 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', - 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', - 'OTG_GSL_MASTER_MODE', 'OTG_GSL_MASTER_MODE_0', - 'OTG_GSL_MASTER_MODE_1', 'OTG_GSL_MASTER_MODE_2', - 'OTG_GSL_MASTER_MODE_3', 'OTG_HORZ_REPETITION_COUNT', - 'OTG_HORZ_REPETITION_COUNT_0', 'OTG_HORZ_REPETITION_COUNT_1', - 'OTG_HORZ_REPETITION_COUNT_10', 'OTG_HORZ_REPETITION_COUNT_11', - 'OTG_HORZ_REPETITION_COUNT_12', 'OTG_HORZ_REPETITION_COUNT_13', - 'OTG_HORZ_REPETITION_COUNT_14', 'OTG_HORZ_REPETITION_COUNT_15', - 'OTG_HORZ_REPETITION_COUNT_2', 'OTG_HORZ_REPETITION_COUNT_3', - 'OTG_HORZ_REPETITION_COUNT_4', 'OTG_HORZ_REPETITION_COUNT_5', - 'OTG_HORZ_REPETITION_COUNT_6', 'OTG_HORZ_REPETITION_COUNT_7', - 'OTG_HORZ_REPETITION_COUNT_8', 'OTG_HORZ_REPETITION_COUNT_9', - 'OTG_H_SYNC_A_POL', 'OTG_H_SYNC_A_POL_HIGH', - 'OTG_H_SYNC_A_POL_LOW', 'OTG_H_TIMING_DIV_BY2', - 'OTG_H_TIMING_DIV_BY2_FALSE', 'OTG_H_TIMING_DIV_BY2_TRUE', - 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE', - 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0', - 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', - 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE', - 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG', - 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE', - 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL', - 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR', - 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', - 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', - 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR', - 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE', - 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE', 'OTG_PIPE_ABORT', - 'OTG_PIPE_ABORT_0', 'OTG_PIPE_ABORT_1', - 'OTG_PTI_CONTROL_OTG_PIT_EN', 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE', - 'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', - 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY', - 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE', - 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE', - 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN', - 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE', - 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE', - 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN', - 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE', - 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE', - 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY', - 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE', - 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', - 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', - 'OTG_TRIGA_FREQUENCY_SELECT_3', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', - 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', - 'OTG_TRIGB_FREQUENCY_SELECT_3', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', - 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE', - 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE', - 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', - 'OTG_V_SYNC_A_POL', 'OTG_V_SYNC_A_POL_HIGH', - 'OTG_V_SYNC_A_POL_LOW', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN', - 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', - 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR', - 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE', - 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE', - 'OUTPUT_LINE', 'OUTPUT_POINT', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', - 'OVERRUN', 'P16_32x32_16x16', 'P16_32x32_8x16', 'P16_ADDR_SURF', - 'P2', 'P4_16x16', 'P4_16x32', 'P4_32x32', 'P4_8x16', - 'P8_16x16_8x16', 'P8_16x32_16x16', 'P8_16x32_8x16', - 'P8_32x32_16x16', 'P8_32x32_16x32', 'P8_32x32_8x16', - 'P8_32x64_32x32', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', - 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE', - 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', - 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', - 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', - 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', - 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', - 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', - 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', - 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', - 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', - 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', - 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', - 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', - 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', - 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', - 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', - 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', - 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', - 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', - 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', - 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', - 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', - 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', - 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', - 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', - 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', - 'PERFCOUNTER_CNTOFF_START_DISABLE', - 'PERFCOUNTER_CNTOFF_START_ENABLE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', - 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', - 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', - 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', - 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', - 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', - 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', - 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', - 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', - 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', - 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', - 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', - 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', - 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', - 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', - 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', - 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', - 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', - 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', - 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', - 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', - 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', - 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', - 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', - 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', - 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', - 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', - 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', - 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', - 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', - 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', - 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', - 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', - 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', - 'PERFMON_COUNTER_MODE_ACCUM', - 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 'PERFMON_COUNTER_MODE_DIRTY', - 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', - 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', - 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', - 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', - 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', - 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', - 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', - 'PERFMON_STATE_START', 'PERF_CLIENT_UTCL1_INFLIGHT', - 'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE', - 'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE', - 'PERF_INDEX_RECEIVE_QUALIFIED_BUSY', - 'PERF_INDEX_RECEIVE_QUALIFIED_STARVED', - 'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO', - 'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE', - 'PERF_INDEX_REQUEST_QUALIFIED_BUSY', - 'PERF_INDEX_REQUEST_QUALIFIED_STARVED', - 'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO', - 'PERF_INDEX_REQUEST_WAITING_ON_TOKENS', 'PERF_PAPC_CCGSM_BUSY', - 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', - 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', - 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', - 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', - 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', - 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', - 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', - 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', - 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', - 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', - 'PERF_PAPC_PASX_REC_STALLED', - 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', - 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', - 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', - 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', - 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', - 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', - 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', - 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', - 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', - 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE01_STALLED_SC', - 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE0_STALLED_SC', - 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE1_STALLED_SC', - 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE2_STALLED_SC', - 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', - 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 'PERF_PAWD_DEALLOC_FIFO_IS_FULL', - 'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ', - 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', - 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', - 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', - 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', - 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', - 'PERF_PA_VERTEX_FIFO_FULL', - 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 'PERF_POS_REQ_QUALIFIED_BUSY', 'PERF_POS_REQ_QUALIFIED_STARVED', - 'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM', - 'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM', - 'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM', - 'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM', - 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO', - 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO', - 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO', - 'PERF_POS_REQ_STALLED_BY_NO_TOKENS', - 'PERF_POS_REQ_STALLED_BY_UTCL1', - 'PERF_POS_REQ_STARVED_BY_NO_PRIM', - 'PERF_POS_RET_1_CACHELINE_POSITION_USED', - 'PERF_POS_RET_2_CACHELINE_POSITION_USED', - 'PERF_POS_RET_3_CACHELINE_POSITION_USED', - 'PERF_POS_RET_4_CACHELINE_POSITION_USED', - 'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE', - 'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO', - 'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO', - 'PERF_POS_RET_QUALIFIED_BUSY', 'PERF_POS_RET_QUALIFIED_STARVED', - 'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE', - 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SHOOTDOWN_WAIT_ALL_CLEAN', 'PERF_SHOOTDOWN_WAIT_DEASSERT', - 'PERF_SHOOTDOWN_WAIT_ON_UTCL1', - 'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX', - 'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION', - 'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND', - 'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_', - 'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_', - 'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_', - 'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_', - 'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD', - 'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD', - 'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD', - 'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL', - 'PERF_SIDEBAND_INVALID_REFETCH', - 'PERF_SIDEBAND_POP_BIT_FIFO_FULL', 'PERF_SIDEBAND_QUALIFIED_BUSY', - 'PERF_SIDEBAND_QUALIFIED_STARVED', - 'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY', - 'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA', - 'PERF_SIDEBAND_WAITING_ON_UTCL1', 'PERF_SMALL_PRIM_CULL_PRIM_1X1', - 'PERF_SMALL_PRIM_CULL_PRIM_1X2', 'PERF_SMALL_PRIM_CULL_PRIM_1X3', - 'PERF_SMALL_PRIM_CULL_PRIM_1XN', 'PERF_SMALL_PRIM_CULL_PRIM_2X1', - 'PERF_SMALL_PRIM_CULL_PRIM_2X2', 'PERF_SMALL_PRIM_CULL_PRIM_2X3', - 'PERF_SMALL_PRIM_CULL_PRIM_2XN', 'PERF_SMALL_PRIM_CULL_PRIM_3X1', - 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERF_TCIF_BUSY', - 'PERF_TCIF_INDEX_RDREQ', 'PERF_TCIF_POSITION_RDREQ', - 'PERF_TCIF_SIDEBAND_RDREQ', - 'PERF_TCIF_STALLING_CLIENT_NO_CREDITS', - 'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE', - 'PERF_TC_INDEX_LATENCY_BIN0', 'PERF_TC_INDEX_LATENCY_BIN1', - 'PERF_TC_INDEX_LATENCY_BIN10', 'PERF_TC_INDEX_LATENCY_BIN11', - 'PERF_TC_INDEX_LATENCY_BIN12', 'PERF_TC_INDEX_LATENCY_BIN13', - 'PERF_TC_INDEX_LATENCY_BIN14', 'PERF_TC_INDEX_LATENCY_BIN15', - 'PERF_TC_INDEX_LATENCY_BIN2', 'PERF_TC_INDEX_LATENCY_BIN3', - 'PERF_TC_INDEX_LATENCY_BIN4', 'PERF_TC_INDEX_LATENCY_BIN5', - 'PERF_TC_INDEX_LATENCY_BIN6', 'PERF_TC_INDEX_LATENCY_BIN7', - 'PERF_TC_INDEX_LATENCY_BIN8', 'PERF_TC_INDEX_LATENCY_BIN9', - 'PERF_TC_POSITION_LATENCY_BIN0', 'PERF_TC_POSITION_LATENCY_BIN1', - 'PERF_TC_POSITION_LATENCY_BIN10', - 'PERF_TC_POSITION_LATENCY_BIN11', - 'PERF_TC_POSITION_LATENCY_BIN12', - 'PERF_TC_POSITION_LATENCY_BIN13', - 'PERF_TC_POSITION_LATENCY_BIN14', - 'PERF_TC_POSITION_LATENCY_BIN15', 'PERF_TC_POSITION_LATENCY_BIN2', - 'PERF_TC_POSITION_LATENCY_BIN3', 'PERF_TC_POSITION_LATENCY_BIN4', - 'PERF_TC_POSITION_LATENCY_BIN5', 'PERF_TC_POSITION_LATENCY_BIN6', - 'PERF_TC_POSITION_LATENCY_BIN7', 'PERF_TC_POSITION_LATENCY_BIN8', - 'PERF_TC_POSITION_LATENCY_BIN9', 'PERF_TC_STREAM0_DATA_AVAILABLE', - 'PERF_TC_STREAM1_DATA_AVAILABLE', - 'PERF_TC_STREAM2_DATA_AVAILABLE', 'PERF_UTCL1_LFIFO_FULL', - 'PERF_UTCL1_PERMISSION_MISS_CLIENT0', - 'PERF_UTCL1_PERMISSION_MISS_CLIENT1', - 'PERF_UTCL1_PERMISSION_MISS_CLIENT2', - 'PERF_UTCL1_REQUEST_CLIENT0', 'PERF_UTCL1_REQUEST_CLIENT1', - 'PERF_UTCL1_REQUEST_CLIENT2', 'PERF_UTCL1_STALL_INFLIGHT_MAX', - 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0', - 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1', - 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2', - 'PERF_UTCL1_STALL_LRU_INFLIGHT', 'PERF_UTCL1_STALL_MISSFIFO_FULL', - 'PERF_UTCL1_STALL_MULTI_MISS', - 'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'PERF_UTCL1_TRANSLATION_HIT_CLIENT0', - 'PERF_UTCL1_TRANSLATION_HIT_CLIENT1', - 'PERF_UTCL1_TRANSLATION_HIT_CLIENT2', - 'PERF_UTCL1_TRANSLATION_MISS_CLIENT0', - 'PERF_UTCL1_TRANSLATION_MISS_CLIENT1', - 'PERF_UTCL1_TRANSLATION_MISS_CLIENT2', - 'PERF_UTCL1_UTCL2_INFLIGHT', 'PERF_UTCL1_UTCL2_REQ', - 'PERF_UTCL1_UTCL2_RET', 'PERF_UTC_INDEX_DRIVER_BUSY', - 'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT', - 'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1', - 'PERF_UTC_INDEX_RECEIVER_BUSY', - 'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER', - 'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1', - 'PERF_UTC_POSITION_DRIVER_BUSY', - 'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT', - 'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1', - 'PERF_UTC_POSITION_RECEIVER_BUSY', - 'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER', - 'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1', - 'PERF_UTC_SIDEBAND_DRIVER_BUSY', - 'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT', - 'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1', - 'PERF_UTC_SIDEBAND_RECEIVER_BUSY', - 'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER', - 'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1', - 'PERF_WRITING_TO_SIDEBAND_MEMORY', 'PERSISTENT_SPACE_END', - 'PERSISTENT_SPACE_START', 'PH_PERFCNT_SEL', 'PH_SC0_ARB_BUSY', - 'PH_SC0_ARB_EOP_POP_SYNC_POP', 'PH_SC0_ARB_EVENT_SYNC_POP', - 'PH_SC0_ARB_PA_BUSY_SOP', 'PH_SC0_ARB_STALLED_FROM_BELOW', - 'PH_SC0_ARB_STARVED_FROM_ABOVE', - 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC0_BUSY_CNT_NOT_ZERO', - 'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC0_CREDIT_AT_MAX', - 'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC0_EOP_SYNC_WINDOW', 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC0_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 'PH_SC0_PA0_DATA_FIFO_EOP_RD', 'PH_SC0_PA0_DATA_FIFO_RD', - 'PH_SC0_PA0_DATA_FIFO_WE', 'PH_SC0_PA0_DEALLOC_4_0_RD', - 'PH_SC0_PA0_EOPG_WE', 'PH_SC0_PA0_EOP_WE', 'PH_SC0_PA0_EVENT_WE', - 'PH_SC0_PA0_FIFO_EMPTY', 'PH_SC0_PA0_FIFO_FULL', - 'PH_SC0_PA0_FPOV_WE', 'PH_SC0_PA0_LPOV_WE', 'PH_SC0_PA0_NULL_WE', - 'PH_SC0_PA1_DATA_FIFO_EOP_RD', 'PH_SC0_PA1_DATA_FIFO_RD', - 'PH_SC0_PA1_DATA_FIFO_WE', 'PH_SC0_PA1_DEALLOC_4_0_RD', - 'PH_SC0_PA1_EOPG_WE', 'PH_SC0_PA1_EOP_WE', 'PH_SC0_PA1_EVENT_WE', - 'PH_SC0_PA1_FIFO_EMPTY', 'PH_SC0_PA1_FIFO_FULL', - 'PH_SC0_PA1_FPOV_WE', 'PH_SC0_PA1_LPOV_WE', 'PH_SC0_PA1_NULL_WE', - 'PH_SC0_PA2_DATA_FIFO_EOP_RD', 'PH_SC0_PA2_DATA_FIFO_RD', - 'PH_SC0_PA2_DATA_FIFO_WE', 'PH_SC0_PA2_DEALLOC_4_0_RD', - 'PH_SC0_PA2_EOPG_WE', 'PH_SC0_PA2_EOP_WE', 'PH_SC0_PA2_EVENT_WE', - 'PH_SC0_PA2_FIFO_EMPTY', 'PH_SC0_PA2_FIFO_FULL', - 'PH_SC0_PA2_FPOV_WE', 'PH_SC0_PA2_LPOV_WE', 'PH_SC0_PA2_NULL_WE', - 'PH_SC0_PA3_DATA_FIFO_EOP_RD', 'PH_SC0_PA3_DATA_FIFO_RD', - 'PH_SC0_PA3_DATA_FIFO_WE', 'PH_SC0_PA3_DEALLOC_4_0_RD', - 'PH_SC0_PA3_EOPG_WE', 'PH_SC0_PA3_EOP_WE', 'PH_SC0_PA3_EVENT_WE', - 'PH_SC0_PA3_FIFO_EMPTY', 'PH_SC0_PA3_FIFO_FULL', - 'PH_SC0_PA3_FPOV_WE', 'PH_SC0_PA3_LPOV_WE', 'PH_SC0_PA3_NULL_WE', - 'PH_SC0_PA4_DATA_FIFO_EOP_RD', 'PH_SC0_PA4_DATA_FIFO_RD', - 'PH_SC0_PA4_DATA_FIFO_WE', 'PH_SC0_PA4_DEALLOC_4_0_RD', - 'PH_SC0_PA4_EOPG_WE', 'PH_SC0_PA4_EOP_WE', 'PH_SC0_PA4_EVENT_WE', - 'PH_SC0_PA4_FIFO_EMPTY', 'PH_SC0_PA4_FIFO_FULL', - 'PH_SC0_PA4_FPOV_WE', 'PH_SC0_PA4_LPOV_WE', 'PH_SC0_PA4_NULL_WE', - 'PH_SC0_PA5_DATA_FIFO_EOP_RD', 'PH_SC0_PA5_DATA_FIFO_RD', - 'PH_SC0_PA5_DATA_FIFO_WE', 'PH_SC0_PA5_DEALLOC_4_0_RD', - 'PH_SC0_PA5_EOPG_WE', 'PH_SC0_PA5_EOP_WE', 'PH_SC0_PA5_EVENT_WE', - 'PH_SC0_PA5_FIFO_EMPTY', 'PH_SC0_PA5_FIFO_FULL', - 'PH_SC0_PA5_FPOV_WE', 'PH_SC0_PA5_LPOV_WE', 'PH_SC0_PA5_NULL_WE', - 'PH_SC0_PA6_DATA_FIFO_EOP_RD', 'PH_SC0_PA6_DATA_FIFO_RD', - 'PH_SC0_PA6_DATA_FIFO_WE', 'PH_SC0_PA6_DEALLOC_4_0_RD', - 'PH_SC0_PA6_EOPG_WE', 'PH_SC0_PA6_EOP_WE', 'PH_SC0_PA6_EVENT_WE', - 'PH_SC0_PA6_FIFO_EMPTY', 'PH_SC0_PA6_FIFO_FULL', - 'PH_SC0_PA6_FPOV_WE', 'PH_SC0_PA6_LPOV_WE', 'PH_SC0_PA6_NULL_WE', - 'PH_SC0_PA7_DATA_FIFO_EOP_RD', 'PH_SC0_PA7_DATA_FIFO_RD', - 'PH_SC0_PA7_DATA_FIFO_WE', 'PH_SC0_PA7_DEALLOC_4_0_RD', - 'PH_SC0_PA7_EOPG_WE', 'PH_SC0_PA7_EOP_WE', 'PH_SC0_PA7_EVENT_WE', - 'PH_SC0_PA7_FIFO_EMPTY', 'PH_SC0_PA7_FIFO_FULL', - 'PH_SC0_PA7_FPOV_WE', 'PH_SC0_PA7_LPOV_WE', 'PH_SC0_PA7_NULL_WE', - 'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC0_SEND', - 'PH_SC0_SRPS_WINDOW_VALID', 'PH_SC1_ARB_BUSY', - 'PH_SC1_ARB_EOP_POP_SYNC_POP', 'PH_SC1_ARB_EVENT_SYNC_POP', - 'PH_SC1_ARB_PA_BUSY_SOP', 'PH_SC1_ARB_STALLED_FROM_BELOW', - 'PH_SC1_ARB_STARVED_FROM_ABOVE', - 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC1_BUSY_CNT_NOT_ZERO', - 'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC1_CREDIT_AT_MAX', - 'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC1_EOP_SYNC_WINDOW', 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC1_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC1_PA0_DATA_FIFO_EOP_RD', 'PH_SC1_PA0_DATA_FIFO_RD', - 'PH_SC1_PA0_DATA_FIFO_WE', 'PH_SC1_PA0_DEALLOC_4_0_RD', - 'PH_SC1_PA0_EOPG_WE', 'PH_SC1_PA0_EOP_WE', 'PH_SC1_PA0_EVENT_WE', - 'PH_SC1_PA0_FIFO_EMPTY', 'PH_SC1_PA0_FIFO_FULL', - 'PH_SC1_PA0_FPOV_WE', 'PH_SC1_PA0_LPOV_WE', 'PH_SC1_PA0_NULL_WE', - 'PH_SC1_PA1_DATA_FIFO_EOP_RD', 'PH_SC1_PA1_DATA_FIFO_RD', - 'PH_SC1_PA1_DATA_FIFO_WE', 'PH_SC1_PA1_DEALLOC_4_0_RD', - 'PH_SC1_PA1_EOPG_WE', 'PH_SC1_PA1_EOP_WE', 'PH_SC1_PA1_EVENT_WE', - 'PH_SC1_PA1_FIFO_EMPTY', 'PH_SC1_PA1_FIFO_FULL', - 'PH_SC1_PA1_FPOV_WE', 'PH_SC1_PA1_LPOV_WE', 'PH_SC1_PA1_NULL_WE', - 'PH_SC1_PA2_DATA_FIFO_EOP_RD', 'PH_SC1_PA2_DATA_FIFO_RD', - 'PH_SC1_PA2_DATA_FIFO_WE', 'PH_SC1_PA2_DEALLOC_4_0_RD', - 'PH_SC1_PA2_EOPG_WE', 'PH_SC1_PA2_EOP_WE', 'PH_SC1_PA2_EVENT_WE', - 'PH_SC1_PA2_FIFO_EMPTY', 'PH_SC1_PA2_FIFO_FULL', - 'PH_SC1_PA2_FPOV_WE', 'PH_SC1_PA2_LPOV_WE', 'PH_SC1_PA2_NULL_WE', - 'PH_SC1_PA3_DATA_FIFO_EOP_RD', 'PH_SC1_PA3_DATA_FIFO_RD', - 'PH_SC1_PA3_DATA_FIFO_WE', 'PH_SC1_PA3_DEALLOC_4_0_RD', - 'PH_SC1_PA3_EOPG_WE', 'PH_SC1_PA3_EOP_WE', 'PH_SC1_PA3_EVENT_WE', - 'PH_SC1_PA3_FIFO_EMPTY', 'PH_SC1_PA3_FIFO_FULL', - 'PH_SC1_PA3_FPOV_WE', 'PH_SC1_PA3_LPOV_WE', 'PH_SC1_PA3_NULL_WE', - 'PH_SC1_PA4_DATA_FIFO_EOP_RD', 'PH_SC1_PA4_DATA_FIFO_RD', - 'PH_SC1_PA4_DATA_FIFO_WE', 'PH_SC1_PA4_DEALLOC_4_0_RD', - 'PH_SC1_PA4_EOPG_WE', 'PH_SC1_PA4_EOP_WE', 'PH_SC1_PA4_EVENT_WE', - 'PH_SC1_PA4_FIFO_EMPTY', 'PH_SC1_PA4_FIFO_FULL', - 'PH_SC1_PA4_FPOV_WE', 'PH_SC1_PA4_LPOV_WE', 'PH_SC1_PA4_NULL_WE', - 'PH_SC1_PA5_DATA_FIFO_EOP_RD', 'PH_SC1_PA5_DATA_FIFO_RD', - 'PH_SC1_PA5_DATA_FIFO_WE', 'PH_SC1_PA5_DEALLOC_4_0_RD', - 'PH_SC1_PA5_EOPG_WE', 'PH_SC1_PA5_EOP_WE', 'PH_SC1_PA5_EVENT_WE', - 'PH_SC1_PA5_FIFO_EMPTY', 'PH_SC1_PA5_FIFO_FULL', - 'PH_SC1_PA5_FPOV_WE', 'PH_SC1_PA5_LPOV_WE', 'PH_SC1_PA5_NULL_WE', - 'PH_SC1_PA6_DATA_FIFO_EOP_RD', 'PH_SC1_PA6_DATA_FIFO_RD', - 'PH_SC1_PA6_DATA_FIFO_WE', 'PH_SC1_PA6_DEALLOC_4_0_RD', - 'PH_SC1_PA6_EOPG_WE', 'PH_SC1_PA6_EOP_WE', 'PH_SC1_PA6_EVENT_WE', - 'PH_SC1_PA6_FIFO_EMPTY', 'PH_SC1_PA6_FIFO_FULL', - 'PH_SC1_PA6_FPOV_WE', 'PH_SC1_PA6_LPOV_WE', 'PH_SC1_PA6_NULL_WE', - 'PH_SC1_PA7_DATA_FIFO_EOP_RD', 'PH_SC1_PA7_DATA_FIFO_RD', - 'PH_SC1_PA7_DATA_FIFO_WE', 'PH_SC1_PA7_DEALLOC_4_0_RD', - 'PH_SC1_PA7_EOPG_WE', 'PH_SC1_PA7_EOP_WE', 'PH_SC1_PA7_EVENT_WE', - 'PH_SC1_PA7_FIFO_EMPTY', 'PH_SC1_PA7_FIFO_FULL', - 'PH_SC1_PA7_FPOV_WE', 'PH_SC1_PA7_LPOV_WE', 'PH_SC1_PA7_NULL_WE', - 'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC1_SEND', - 'PH_SC1_SRPS_WINDOW_VALID', 'PH_SC2_ARB_BUSY', - 'PH_SC2_ARB_EOP_POP_SYNC_POP', 'PH_SC2_ARB_EVENT_SYNC_POP', - 'PH_SC2_ARB_PA_BUSY_SOP', 'PH_SC2_ARB_STALLED_FROM_BELOW', - 'PH_SC2_ARB_STARVED_FROM_ABOVE', - 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC2_BUSY_CNT_NOT_ZERO', - 'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC2_CREDIT_AT_MAX', - 'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC2_EOP_SYNC_WINDOW', 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC2_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC2_PA0_DATA_FIFO_EOP_RD', 'PH_SC2_PA0_DATA_FIFO_RD', - 'PH_SC2_PA0_DATA_FIFO_WE', 'PH_SC2_PA0_DEALLOC_4_0_RD', - 'PH_SC2_PA0_EOPG_WE', 'PH_SC2_PA0_EOP_WE', 'PH_SC2_PA0_EVENT_WE', - 'PH_SC2_PA0_FIFO_EMPTY', 'PH_SC2_PA0_FIFO_FULL', - 'PH_SC2_PA0_FPOV_WE', 'PH_SC2_PA0_LPOV_WE', 'PH_SC2_PA0_NULL_WE', - 'PH_SC2_PA1_DATA_FIFO_EOP_RD', 'PH_SC2_PA1_DATA_FIFO_RD', - 'PH_SC2_PA1_DATA_FIFO_WE', 'PH_SC2_PA1_DEALLOC_4_0_RD', - 'PH_SC2_PA1_EOPG_WE', 'PH_SC2_PA1_EOP_WE', 'PH_SC2_PA1_EVENT_WE', - 'PH_SC2_PA1_FIFO_EMPTY', 'PH_SC2_PA1_FIFO_FULL', - 'PH_SC2_PA1_FPOV_WE', 'PH_SC2_PA1_LPOV_WE', 'PH_SC2_PA1_NULL_WE', - 'PH_SC2_PA2_DATA_FIFO_EOP_RD', 'PH_SC2_PA2_DATA_FIFO_RD', - 'PH_SC2_PA2_DATA_FIFO_WE', 'PH_SC2_PA2_DEALLOC_4_0_RD', - 'PH_SC2_PA2_EOPG_WE', 'PH_SC2_PA2_EOP_WE', 'PH_SC2_PA2_EVENT_WE', - 'PH_SC2_PA2_FIFO_EMPTY', 'PH_SC2_PA2_FIFO_FULL', - 'PH_SC2_PA2_FPOV_WE', 'PH_SC2_PA2_LPOV_WE', 'PH_SC2_PA2_NULL_WE', - 'PH_SC2_PA3_DATA_FIFO_EOP_RD', 'PH_SC2_PA3_DATA_FIFO_RD', - 'PH_SC2_PA3_DATA_FIFO_WE', 'PH_SC2_PA3_DEALLOC_4_0_RD', - 'PH_SC2_PA3_EOPG_WE', 'PH_SC2_PA3_EOP_WE', 'PH_SC2_PA3_EVENT_WE', - 'PH_SC2_PA3_FIFO_EMPTY', 'PH_SC2_PA3_FIFO_FULL', - 'PH_SC2_PA3_FPOV_WE', 'PH_SC2_PA3_LPOV_WE', 'PH_SC2_PA3_NULL_WE', - 'PH_SC2_PA4_DATA_FIFO_EOP_RD', 'PH_SC2_PA4_DATA_FIFO_RD', - 'PH_SC2_PA4_DATA_FIFO_WE', 'PH_SC2_PA4_DEALLOC_4_0_RD', - 'PH_SC2_PA4_EOPG_WE', 'PH_SC2_PA4_EOP_WE', 'PH_SC2_PA4_EVENT_WE', - 'PH_SC2_PA4_FIFO_EMPTY', 'PH_SC2_PA4_FIFO_FULL', - 'PH_SC2_PA4_FPOV_WE', 'PH_SC2_PA4_LPOV_WE', 'PH_SC2_PA4_NULL_WE', - 'PH_SC2_PA5_DATA_FIFO_EOP_RD', 'PH_SC2_PA5_DATA_FIFO_RD', - 'PH_SC2_PA5_DATA_FIFO_WE', 'PH_SC2_PA5_DEALLOC_4_0_RD', - 'PH_SC2_PA5_EOPG_WE', 'PH_SC2_PA5_EOP_WE', 'PH_SC2_PA5_EVENT_WE', - 'PH_SC2_PA5_FIFO_EMPTY', 'PH_SC2_PA5_FIFO_FULL', - 'PH_SC2_PA5_FPOV_WE', 'PH_SC2_PA5_LPOV_WE', 'PH_SC2_PA5_NULL_WE', - 'PH_SC2_PA6_DATA_FIFO_EOP_RD', 'PH_SC2_PA6_DATA_FIFO_RD', - 'PH_SC2_PA6_DATA_FIFO_WE', 'PH_SC2_PA6_DEALLOC_4_0_RD', - 'PH_SC2_PA6_EOPG_WE', 'PH_SC2_PA6_EOP_WE', 'PH_SC2_PA6_EVENT_WE', - 'PH_SC2_PA6_FIFO_EMPTY', 'PH_SC2_PA6_FIFO_FULL', - 'PH_SC2_PA6_FPOV_WE', 'PH_SC2_PA6_LPOV_WE', 'PH_SC2_PA6_NULL_WE', - 'PH_SC2_PA7_DATA_FIFO_EOP_RD', 'PH_SC2_PA7_DATA_FIFO_RD', - 'PH_SC2_PA7_DATA_FIFO_WE', 'PH_SC2_PA7_DEALLOC_4_0_RD', - 'PH_SC2_PA7_EOPG_WE', 'PH_SC2_PA7_EOP_WE', 'PH_SC2_PA7_EVENT_WE', - 'PH_SC2_PA7_FIFO_EMPTY', 'PH_SC2_PA7_FIFO_FULL', - 'PH_SC2_PA7_FPOV_WE', 'PH_SC2_PA7_LPOV_WE', 'PH_SC2_PA7_NULL_WE', - 'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC2_SEND', - 'PH_SC2_SRPS_WINDOW_VALID', 'PH_SC3_ARB_BUSY', - 'PH_SC3_ARB_EOP_POP_SYNC_POP', 'PH_SC3_ARB_EVENT_SYNC_POP', - 'PH_SC3_ARB_PA_BUSY_SOP', 'PH_SC3_ARB_STALLED_FROM_BELOW', - 'PH_SC3_ARB_STARVED_FROM_ABOVE', - 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC3_BUSY_CNT_NOT_ZERO', - 'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC3_CREDIT_AT_MAX', - 'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC3_EOP_SYNC_WINDOW', 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC3_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC3_PA0_DATA_FIFO_EOP_RD', 'PH_SC3_PA0_DATA_FIFO_RD', - 'PH_SC3_PA0_DATA_FIFO_WE', 'PH_SC3_PA0_DEALLOC_4_0_RD', - 'PH_SC3_PA0_EOPG_WE', 'PH_SC3_PA0_EOP_WE', 'PH_SC3_PA0_EVENT_WE', - 'PH_SC3_PA0_FIFO_EMPTY', 'PH_SC3_PA0_FIFO_FULL', - 'PH_SC3_PA0_FPOV_WE', 'PH_SC3_PA0_LPOV_WE', 'PH_SC3_PA0_NULL_WE', - 'PH_SC3_PA1_DATA_FIFO_EOP_RD', 'PH_SC3_PA1_DATA_FIFO_RD', - 'PH_SC3_PA1_DATA_FIFO_WE', 'PH_SC3_PA1_DEALLOC_4_0_RD', - 'PH_SC3_PA1_EOPG_WE', 'PH_SC3_PA1_EOP_WE', 'PH_SC3_PA1_EVENT_WE', - 'PH_SC3_PA1_FIFO_EMPTY', 'PH_SC3_PA1_FIFO_FULL', - 'PH_SC3_PA1_FPOV_WE', 'PH_SC3_PA1_LPOV_WE', 'PH_SC3_PA1_NULL_WE', - 'PH_SC3_PA2_DATA_FIFO_EOP_RD', 'PH_SC3_PA2_DATA_FIFO_RD', - 'PH_SC3_PA2_DATA_FIFO_WE', 'PH_SC3_PA2_DEALLOC_4_0_RD', - 'PH_SC3_PA2_EOPG_WE', 'PH_SC3_PA2_EOP_WE', 'PH_SC3_PA2_EVENT_WE', - 'PH_SC3_PA2_FIFO_EMPTY', 'PH_SC3_PA2_FIFO_FULL', - 'PH_SC3_PA2_FPOV_WE', 'PH_SC3_PA2_LPOV_WE', 'PH_SC3_PA2_NULL_WE', - 'PH_SC3_PA3_DATA_FIFO_EOP_RD', 'PH_SC3_PA3_DATA_FIFO_RD', - 'PH_SC3_PA3_DATA_FIFO_WE', 'PH_SC3_PA3_DEALLOC_4_0_RD', - 'PH_SC3_PA3_EOPG_WE', 'PH_SC3_PA3_EOP_WE', 'PH_SC3_PA3_EVENT_WE', - 'PH_SC3_PA3_FIFO_EMPTY', 'PH_SC3_PA3_FIFO_FULL', - 'PH_SC3_PA3_FPOV_WE', 'PH_SC3_PA3_LPOV_WE', 'PH_SC3_PA3_NULL_WE', - 'PH_SC3_PA4_DATA_FIFO_EOP_RD', 'PH_SC3_PA4_DATA_FIFO_RD', - 'PH_SC3_PA4_DATA_FIFO_WE', 'PH_SC3_PA4_DEALLOC_4_0_RD', - 'PH_SC3_PA4_EOPG_WE', 'PH_SC3_PA4_EOP_WE', 'PH_SC3_PA4_EVENT_WE', - 'PH_SC3_PA4_FIFO_EMPTY', 'PH_SC3_PA4_FIFO_FULL', - 'PH_SC3_PA4_FPOV_WE', 'PH_SC3_PA4_LPOV_WE', 'PH_SC3_PA4_NULL_WE', - 'PH_SC3_PA5_DATA_FIFO_EOP_RD', 'PH_SC3_PA5_DATA_FIFO_RD', - 'PH_SC3_PA5_DATA_FIFO_WE', 'PH_SC3_PA5_DEALLOC_4_0_RD', - 'PH_SC3_PA5_EOPG_WE', 'PH_SC3_PA5_EOP_WE', 'PH_SC3_PA5_EVENT_WE', - 'PH_SC3_PA5_FIFO_EMPTY', 'PH_SC3_PA5_FIFO_FULL', - 'PH_SC3_PA5_FPOV_WE', 'PH_SC3_PA5_LPOV_WE', 'PH_SC3_PA5_NULL_WE', - 'PH_SC3_PA6_DATA_FIFO_EOP_RD', 'PH_SC3_PA6_DATA_FIFO_RD', - 'PH_SC3_PA6_DATA_FIFO_WE', 'PH_SC3_PA6_DEALLOC_4_0_RD', - 'PH_SC3_PA6_EOPG_WE', 'PH_SC3_PA6_EOP_WE', 'PH_SC3_PA6_EVENT_WE', - 'PH_SC3_PA6_FIFO_EMPTY', 'PH_SC3_PA6_FIFO_FULL', - 'PH_SC3_PA6_FPOV_WE', 'PH_SC3_PA6_LPOV_WE', 'PH_SC3_PA6_NULL_WE', - 'PH_SC3_PA7_DATA_FIFO_EOP_RD', 'PH_SC3_PA7_DATA_FIFO_RD', - 'PH_SC3_PA7_DATA_FIFO_WE', 'PH_SC3_PA7_DEALLOC_4_0_RD', - 'PH_SC3_PA7_EOPG_WE', 'PH_SC3_PA7_EOP_WE', 'PH_SC3_PA7_EVENT_WE', - 'PH_SC3_PA7_FIFO_EMPTY', 'PH_SC3_PA7_FIFO_FULL', - 'PH_SC3_PA7_FPOV_WE', 'PH_SC3_PA7_LPOV_WE', 'PH_SC3_PA7_NULL_WE', - 'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC3_SEND', - 'PH_SC3_SRPS_WINDOW_VALID', 'PH_SC4_ARB_BUSY', - 'PH_SC4_ARB_EOP_POP_SYNC_POP', 'PH_SC4_ARB_EVENT_SYNC_POP', - 'PH_SC4_ARB_PA_BUSY_SOP', 'PH_SC4_ARB_STALLED_FROM_BELOW', - 'PH_SC4_ARB_STARVED_FROM_ABOVE', - 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC4_BUSY_CNT_NOT_ZERO', - 'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC4_CREDIT_AT_MAX', - 'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC4_EOP_SYNC_WINDOW', 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC4_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC4_PA0_DATA_FIFO_EOP_RD', 'PH_SC4_PA0_DATA_FIFO_RD', - 'PH_SC4_PA0_DATA_FIFO_WE', 'PH_SC4_PA0_DEALLOC_4_0_RD', - 'PH_SC4_PA0_EOPG_WE', 'PH_SC4_PA0_EOP_WE', 'PH_SC4_PA0_EVENT_WE', - 'PH_SC4_PA0_FIFO_EMPTY', 'PH_SC4_PA0_FIFO_FULL', - 'PH_SC4_PA0_FPOV_WE', 'PH_SC4_PA0_LPOV_WE', 'PH_SC4_PA0_NULL_WE', - 'PH_SC4_PA1_DATA_FIFO_EOP_RD', 'PH_SC4_PA1_DATA_FIFO_RD', - 'PH_SC4_PA1_DATA_FIFO_WE', 'PH_SC4_PA1_DEALLOC_4_0_RD', - 'PH_SC4_PA1_EOPG_WE', 'PH_SC4_PA1_EOP_WE', 'PH_SC4_PA1_EVENT_WE', - 'PH_SC4_PA1_FIFO_EMPTY', 'PH_SC4_PA1_FIFO_FULL', - 'PH_SC4_PA1_FPOV_WE', 'PH_SC4_PA1_LPOV_WE', 'PH_SC4_PA1_NULL_WE', - 'PH_SC4_PA2_DATA_FIFO_EOP_RD', 'PH_SC4_PA2_DATA_FIFO_RD', - 'PH_SC4_PA2_DATA_FIFO_WE', 'PH_SC4_PA2_DEALLOC_4_0_RD', - 'PH_SC4_PA2_EOPG_WE', 'PH_SC4_PA2_EOP_WE', 'PH_SC4_PA2_EVENT_WE', - 'PH_SC4_PA2_FIFO_EMPTY', 'PH_SC4_PA2_FIFO_FULL', - 'PH_SC4_PA2_FPOV_WE', 'PH_SC4_PA2_LPOV_WE', 'PH_SC4_PA2_NULL_WE', - 'PH_SC4_PA3_DATA_FIFO_EOP_RD', 'PH_SC4_PA3_DATA_FIFO_RD', - 'PH_SC4_PA3_DATA_FIFO_WE', 'PH_SC4_PA3_DEALLOC_4_0_RD', - 'PH_SC4_PA3_EOPG_WE', 'PH_SC4_PA3_EOP_WE', 'PH_SC4_PA3_EVENT_WE', - 'PH_SC4_PA3_FIFO_EMPTY', 'PH_SC4_PA3_FIFO_FULL', - 'PH_SC4_PA3_FPOV_WE', 'PH_SC4_PA3_LPOV_WE', 'PH_SC4_PA3_NULL_WE', - 'PH_SC4_PA4_DATA_FIFO_EOP_RD', 'PH_SC4_PA4_DATA_FIFO_RD', - 'PH_SC4_PA4_DATA_FIFO_WE', 'PH_SC4_PA4_DEALLOC_4_0_RD', - 'PH_SC4_PA4_EOPG_WE', 'PH_SC4_PA4_EOP_WE', 'PH_SC4_PA4_EVENT_WE', - 'PH_SC4_PA4_FIFO_EMPTY', 'PH_SC4_PA4_FIFO_FULL', - 'PH_SC4_PA4_FPOV_WE', 'PH_SC4_PA4_LPOV_WE', 'PH_SC4_PA4_NULL_WE', - 'PH_SC4_PA5_DATA_FIFO_EOP_RD', 'PH_SC4_PA5_DATA_FIFO_RD', - 'PH_SC4_PA5_DATA_FIFO_WE', 'PH_SC4_PA5_DEALLOC_4_0_RD', - 'PH_SC4_PA5_EOPG_WE', 'PH_SC4_PA5_EOP_WE', 'PH_SC4_PA5_EVENT_WE', - 'PH_SC4_PA5_FIFO_EMPTY', 'PH_SC4_PA5_FIFO_FULL', - 'PH_SC4_PA5_FPOV_WE', 'PH_SC4_PA5_LPOV_WE', 'PH_SC4_PA5_NULL_WE', - 'PH_SC4_PA6_DATA_FIFO_EOP_RD', 'PH_SC4_PA6_DATA_FIFO_RD', - 'PH_SC4_PA6_DATA_FIFO_WE', 'PH_SC4_PA6_DEALLOC_4_0_RD', - 'PH_SC4_PA6_EOPG_WE', 'PH_SC4_PA6_EOP_WE', 'PH_SC4_PA6_EVENT_WE', - 'PH_SC4_PA6_FIFO_EMPTY', 'PH_SC4_PA6_FIFO_FULL', - 'PH_SC4_PA6_FPOV_WE', 'PH_SC4_PA6_LPOV_WE', 'PH_SC4_PA6_NULL_WE', - 'PH_SC4_PA7_DATA_FIFO_EOP_RD', 'PH_SC4_PA7_DATA_FIFO_RD', - 'PH_SC4_PA7_DATA_FIFO_WE', 'PH_SC4_PA7_DEALLOC_4_0_RD', - 'PH_SC4_PA7_EOPG_WE', 'PH_SC4_PA7_EOP_WE', 'PH_SC4_PA7_EVENT_WE', - 'PH_SC4_PA7_FIFO_EMPTY', 'PH_SC4_PA7_FIFO_FULL', - 'PH_SC4_PA7_FPOV_WE', 'PH_SC4_PA7_LPOV_WE', 'PH_SC4_PA7_NULL_WE', - 'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC4_SEND', - 'PH_SC4_SRPS_WINDOW_VALID', 'PH_SC5_ARB_BUSY', - 'PH_SC5_ARB_EOP_POP_SYNC_POP', 'PH_SC5_ARB_EVENT_SYNC_POP', - 'PH_SC5_ARB_PA_BUSY_SOP', 'PH_SC5_ARB_STALLED_FROM_BELOW', - 'PH_SC5_ARB_STARVED_FROM_ABOVE', - 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC5_BUSY_CNT_NOT_ZERO', - 'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC5_CREDIT_AT_MAX', - 'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC5_EOP_SYNC_WINDOW', 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC5_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC5_PA0_DATA_FIFO_EOP_RD', 'PH_SC5_PA0_DATA_FIFO_RD', - 'PH_SC5_PA0_DATA_FIFO_WE', 'PH_SC5_PA0_DEALLOC_4_0_RD', - 'PH_SC5_PA0_EOPG_WE', 'PH_SC5_PA0_EOP_WE', 'PH_SC5_PA0_EVENT_WE', - 'PH_SC5_PA0_FIFO_EMPTY', 'PH_SC5_PA0_FIFO_FULL', - 'PH_SC5_PA0_FPOV_WE', 'PH_SC5_PA0_LPOV_WE', 'PH_SC5_PA0_NULL_WE', - 'PH_SC5_PA1_DATA_FIFO_EOP_RD', 'PH_SC5_PA1_DATA_FIFO_RD', - 'PH_SC5_PA1_DATA_FIFO_WE', 'PH_SC5_PA1_DEALLOC_4_0_RD', - 'PH_SC5_PA1_EOPG_WE', 'PH_SC5_PA1_EOP_WE', 'PH_SC5_PA1_EVENT_WE', - 'PH_SC5_PA1_FIFO_EMPTY', 'PH_SC5_PA1_FIFO_FULL', - 'PH_SC5_PA1_FPOV_WE', 'PH_SC5_PA1_LPOV_WE', 'PH_SC5_PA1_NULL_WE', - 'PH_SC5_PA2_DATA_FIFO_EOP_RD', 'PH_SC5_PA2_DATA_FIFO_RD', - 'PH_SC5_PA2_DATA_FIFO_WE', 'PH_SC5_PA2_DEALLOC_4_0_RD', - 'PH_SC5_PA2_EOPG_WE', 'PH_SC5_PA2_EOP_WE', 'PH_SC5_PA2_EVENT_WE', - 'PH_SC5_PA2_FIFO_EMPTY', 'PH_SC5_PA2_FIFO_FULL', - 'PH_SC5_PA2_FPOV_WE', 'PH_SC5_PA2_LPOV_WE', 'PH_SC5_PA2_NULL_WE', - 'PH_SC5_PA3_DATA_FIFO_EOP_RD', 'PH_SC5_PA3_DATA_FIFO_RD', - 'PH_SC5_PA3_DATA_FIFO_WE', 'PH_SC5_PA3_DEALLOC_4_0_RD', - 'PH_SC5_PA3_EOPG_WE', 'PH_SC5_PA3_EOP_WE', 'PH_SC5_PA3_EVENT_WE', - 'PH_SC5_PA3_FIFO_EMPTY', 'PH_SC5_PA3_FIFO_FULL', - 'PH_SC5_PA3_FPOV_WE', 'PH_SC5_PA3_LPOV_WE', 'PH_SC5_PA3_NULL_WE', - 'PH_SC5_PA4_DATA_FIFO_EOP_RD', 'PH_SC5_PA4_DATA_FIFO_RD', - 'PH_SC5_PA4_DATA_FIFO_WE', 'PH_SC5_PA4_DEALLOC_4_0_RD', - 'PH_SC5_PA4_EOPG_WE', 'PH_SC5_PA4_EOP_WE', 'PH_SC5_PA4_EVENT_WE', - 'PH_SC5_PA4_FIFO_EMPTY', 'PH_SC5_PA4_FIFO_FULL', - 'PH_SC5_PA4_FPOV_WE', 'PH_SC5_PA4_LPOV_WE', 'PH_SC5_PA4_NULL_WE', - 'PH_SC5_PA5_DATA_FIFO_EOP_RD', 'PH_SC5_PA5_DATA_FIFO_RD', - 'PH_SC5_PA5_DATA_FIFO_WE', 'PH_SC5_PA5_DEALLOC_4_0_RD', - 'PH_SC5_PA5_EOPG_WE', 'PH_SC5_PA5_EOP_WE', 'PH_SC5_PA5_EVENT_WE', - 'PH_SC5_PA5_FIFO_EMPTY', 'PH_SC5_PA5_FIFO_FULL', - 'PH_SC5_PA5_FPOV_WE', 'PH_SC5_PA5_LPOV_WE', 'PH_SC5_PA5_NULL_WE', - 'PH_SC5_PA6_DATA_FIFO_EOP_RD', 'PH_SC5_PA6_DATA_FIFO_RD', - 'PH_SC5_PA6_DATA_FIFO_WE', 'PH_SC5_PA6_DEALLOC_4_0_RD', - 'PH_SC5_PA6_EOPG_WE', 'PH_SC5_PA6_EOP_WE', 'PH_SC5_PA6_EVENT_WE', - 'PH_SC5_PA6_FIFO_EMPTY', 'PH_SC5_PA6_FIFO_FULL', - 'PH_SC5_PA6_FPOV_WE', 'PH_SC5_PA6_LPOV_WE', 'PH_SC5_PA6_NULL_WE', - 'PH_SC5_PA7_DATA_FIFO_EOP_RD', 'PH_SC5_PA7_DATA_FIFO_RD', - 'PH_SC5_PA7_DATA_FIFO_WE', 'PH_SC5_PA7_DEALLOC_4_0_RD', - 'PH_SC5_PA7_EOPG_WE', 'PH_SC5_PA7_EOP_WE', 'PH_SC5_PA7_EVENT_WE', - 'PH_SC5_PA7_FIFO_EMPTY', 'PH_SC5_PA7_FIFO_FULL', - 'PH_SC5_PA7_FPOV_WE', 'PH_SC5_PA7_LPOV_WE', 'PH_SC5_PA7_NULL_WE', - 'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC5_SEND', - 'PH_SC5_SRPS_WINDOW_VALID', 'PH_SC6_ARB_BUSY', - 'PH_SC6_ARB_EOP_POP_SYNC_POP', 'PH_SC6_ARB_EVENT_SYNC_POP', - 'PH_SC6_ARB_PA_BUSY_SOP', 'PH_SC6_ARB_STALLED_FROM_BELOW', - 'PH_SC6_ARB_STARVED_FROM_ABOVE', - 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC6_BUSY_CNT_NOT_ZERO', - 'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC6_CREDIT_AT_MAX', - 'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC6_EOP_SYNC_WINDOW', 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC6_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC6_PA0_DATA_FIFO_EOP_RD', 'PH_SC6_PA0_DATA_FIFO_RD', - 'PH_SC6_PA0_DATA_FIFO_WE', 'PH_SC6_PA0_DEALLOC_4_0_RD', - 'PH_SC6_PA0_EOPG_WE', 'PH_SC6_PA0_EOP_WE', 'PH_SC6_PA0_EVENT_WE', - 'PH_SC6_PA0_FIFO_EMPTY', 'PH_SC6_PA0_FIFO_FULL', - 'PH_SC6_PA0_FPOV_WE', 'PH_SC6_PA0_LPOV_WE', 'PH_SC6_PA0_NULL_WE', - 'PH_SC6_PA1_DATA_FIFO_EOP_RD', 'PH_SC6_PA1_DATA_FIFO_RD', - 'PH_SC6_PA1_DATA_FIFO_WE', 'PH_SC6_PA1_DEALLOC_4_0_RD', - 'PH_SC6_PA1_EOPG_WE', 'PH_SC6_PA1_EOP_WE', 'PH_SC6_PA1_EVENT_WE', - 'PH_SC6_PA1_FIFO_EMPTY', 'PH_SC6_PA1_FIFO_FULL', - 'PH_SC6_PA1_FPOV_WE', 'PH_SC6_PA1_LPOV_WE', 'PH_SC6_PA1_NULL_WE', - 'PH_SC6_PA2_DATA_FIFO_EOP_RD', 'PH_SC6_PA2_DATA_FIFO_RD', - 'PH_SC6_PA2_DATA_FIFO_WE', 'PH_SC6_PA2_DEALLOC_4_0_RD', - 'PH_SC6_PA2_EOPG_WE', 'PH_SC6_PA2_EOP_WE', 'PH_SC6_PA2_EVENT_WE', - 'PH_SC6_PA2_FIFO_EMPTY', 'PH_SC6_PA2_FIFO_FULL', - 'PH_SC6_PA2_FPOV_WE', 'PH_SC6_PA2_LPOV_WE', 'PH_SC6_PA2_NULL_WE', - 'PH_SC6_PA3_DATA_FIFO_EOP_RD', 'PH_SC6_PA3_DATA_FIFO_RD', - 'PH_SC6_PA3_DATA_FIFO_WE', 'PH_SC6_PA3_DEALLOC_4_0_RD', - 'PH_SC6_PA3_EOPG_WE', 'PH_SC6_PA3_EOP_WE', 'PH_SC6_PA3_EVENT_WE', - 'PH_SC6_PA3_FIFO_EMPTY', 'PH_SC6_PA3_FIFO_FULL', - 'PH_SC6_PA3_FPOV_WE', 'PH_SC6_PA3_LPOV_WE', 'PH_SC6_PA3_NULL_WE', - 'PH_SC6_PA4_DATA_FIFO_EOP_RD', 'PH_SC6_PA4_DATA_FIFO_RD', - 'PH_SC6_PA4_DATA_FIFO_WE', 'PH_SC6_PA4_DEALLOC_4_0_RD', - 'PH_SC6_PA4_EOPG_WE', 'PH_SC6_PA4_EOP_WE', 'PH_SC6_PA4_EVENT_WE', - 'PH_SC6_PA4_FIFO_EMPTY', 'PH_SC6_PA4_FIFO_FULL', - 'PH_SC6_PA4_FPOV_WE', 'PH_SC6_PA4_LPOV_WE', 'PH_SC6_PA4_NULL_WE', - 'PH_SC6_PA5_DATA_FIFO_EOP_RD', 'PH_SC6_PA5_DATA_FIFO_RD', - 'PH_SC6_PA5_DATA_FIFO_WE', 'PH_SC6_PA5_DEALLOC_4_0_RD', - 'PH_SC6_PA5_EOPG_WE', 'PH_SC6_PA5_EOP_WE', 'PH_SC6_PA5_EVENT_WE', - 'PH_SC6_PA5_FIFO_EMPTY', 'PH_SC6_PA5_FIFO_FULL', - 'PH_SC6_PA5_FPOV_WE', 'PH_SC6_PA5_LPOV_WE', 'PH_SC6_PA5_NULL_WE', - 'PH_SC6_PA6_DATA_FIFO_EOP_RD', 'PH_SC6_PA6_DATA_FIFO_RD', - 'PH_SC6_PA6_DATA_FIFO_WE', 'PH_SC6_PA6_DEALLOC_4_0_RD', - 'PH_SC6_PA6_EOPG_WE', 'PH_SC6_PA6_EOP_WE', 'PH_SC6_PA6_EVENT_WE', - 'PH_SC6_PA6_FIFO_EMPTY', 'PH_SC6_PA6_FIFO_FULL', - 'PH_SC6_PA6_FPOV_WE', 'PH_SC6_PA6_LPOV_WE', 'PH_SC6_PA6_NULL_WE', - 'PH_SC6_PA7_DATA_FIFO_EOP_RD', 'PH_SC6_PA7_DATA_FIFO_RD', - 'PH_SC6_PA7_DATA_FIFO_WE', 'PH_SC6_PA7_DEALLOC_4_0_RD', - 'PH_SC6_PA7_EOPG_WE', 'PH_SC6_PA7_EOP_WE', 'PH_SC6_PA7_EVENT_WE', - 'PH_SC6_PA7_FIFO_EMPTY', 'PH_SC6_PA7_FIFO_FULL', - 'PH_SC6_PA7_FPOV_WE', 'PH_SC6_PA7_LPOV_WE', 'PH_SC6_PA7_NULL_WE', - 'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC6_SEND', - 'PH_SC6_SRPS_WINDOW_VALID', 'PH_SC7_ARB_BUSY', - 'PH_SC7_ARB_EOP_POP_SYNC_POP', 'PH_SC7_ARB_EVENT_SYNC_POP', - 'PH_SC7_ARB_PA_BUSY_SOP', 'PH_SC7_ARB_STALLED_FROM_BELOW', - 'PH_SC7_ARB_STARVED_FROM_ABOVE', - 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC7_BUSY_CNT_NOT_ZERO', - 'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC7_CREDIT_AT_MAX', - 'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_SC7_EOP_SYNC_WINDOW', 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION', - 'PH_SC7_GFX_PIPE1_TO_0_TRANSITION', - 'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_SC7_PA0_DATA_FIFO_EOP_RD', 'PH_SC7_PA0_DATA_FIFO_RD', - 'PH_SC7_PA0_DATA_FIFO_WE', 'PH_SC7_PA0_DEALLOC_4_0_RD', - 'PH_SC7_PA0_EOPG_WE', 'PH_SC7_PA0_EOP_WE', 'PH_SC7_PA0_EVENT_WE', - 'PH_SC7_PA0_FIFO_EMPTY', 'PH_SC7_PA0_FIFO_FULL', - 'PH_SC7_PA0_FPOV_WE', 'PH_SC7_PA0_LPOV_WE', 'PH_SC7_PA0_NULL_WE', - 'PH_SC7_PA1_DATA_FIFO_EOP_RD', 'PH_SC7_PA1_DATA_FIFO_RD', - 'PH_SC7_PA1_DATA_FIFO_WE', 'PH_SC7_PA1_DEALLOC_4_0_RD', - 'PH_SC7_PA1_EOPG_WE', 'PH_SC7_PA1_EOP_WE', 'PH_SC7_PA1_EVENT_WE', - 'PH_SC7_PA1_FIFO_EMPTY', 'PH_SC7_PA1_FIFO_FULL', - 'PH_SC7_PA1_FPOV_WE', 'PH_SC7_PA1_LPOV_WE', 'PH_SC7_PA1_NULL_WE', - 'PH_SC7_PA2_DATA_FIFO_EOP_RD', 'PH_SC7_PA2_DATA_FIFO_RD', - 'PH_SC7_PA2_DATA_FIFO_WE', 'PH_SC7_PA2_DEALLOC_4_0_RD', - 'PH_SC7_PA2_EOPG_WE', 'PH_SC7_PA2_EOP_WE', 'PH_SC7_PA2_EVENT_WE', - 'PH_SC7_PA2_FIFO_EMPTY', 'PH_SC7_PA2_FIFO_FULL', - 'PH_SC7_PA2_FPOV_WE', 'PH_SC7_PA2_LPOV_WE', 'PH_SC7_PA2_NULL_WE', - 'PH_SC7_PA3_DATA_FIFO_EOP_RD', 'PH_SC7_PA3_DATA_FIFO_RD', - 'PH_SC7_PA3_DATA_FIFO_WE', 'PH_SC7_PA3_DEALLOC_4_0_RD', - 'PH_SC7_PA3_EOPG_WE', 'PH_SC7_PA3_EOP_WE', 'PH_SC7_PA3_EVENT_WE', - 'PH_SC7_PA3_FIFO_EMPTY', 'PH_SC7_PA3_FIFO_FULL', - 'PH_SC7_PA3_FPOV_WE', 'PH_SC7_PA3_LPOV_WE', 'PH_SC7_PA3_NULL_WE', - 'PH_SC7_PA4_DATA_FIFO_EOP_RD', 'PH_SC7_PA4_DATA_FIFO_RD', - 'PH_SC7_PA4_DATA_FIFO_WE', 'PH_SC7_PA4_DEALLOC_4_0_RD', - 'PH_SC7_PA4_EOPG_WE', 'PH_SC7_PA4_EOP_WE', 'PH_SC7_PA4_EVENT_WE', - 'PH_SC7_PA4_FIFO_EMPTY', 'PH_SC7_PA4_FIFO_FULL', - 'PH_SC7_PA4_FPOV_WE', 'PH_SC7_PA4_LPOV_WE', 'PH_SC7_PA4_NULL_WE', - 'PH_SC7_PA5_DATA_FIFO_EOP_RD', 'PH_SC7_PA5_DATA_FIFO_RD', - 'PH_SC7_PA5_DATA_FIFO_WE', 'PH_SC7_PA5_DEALLOC_4_0_RD', - 'PH_SC7_PA5_EOPG_WE', 'PH_SC7_PA5_EOP_WE', 'PH_SC7_PA5_EVENT_WE', - 'PH_SC7_PA5_FIFO_EMPTY', 'PH_SC7_PA5_FIFO_FULL', - 'PH_SC7_PA5_FPOV_WE', 'PH_SC7_PA5_LPOV_WE', 'PH_SC7_PA5_NULL_WE', - 'PH_SC7_PA6_DATA_FIFO_EOP_RD', 'PH_SC7_PA6_DATA_FIFO_RD', - 'PH_SC7_PA6_DATA_FIFO_WE', 'PH_SC7_PA6_DEALLOC_4_0_RD', - 'PH_SC7_PA6_EOPG_WE', 'PH_SC7_PA6_EOP_WE', 'PH_SC7_PA6_EVENT_WE', - 'PH_SC7_PA6_FIFO_EMPTY', 'PH_SC7_PA6_FIFO_FULL', - 'PH_SC7_PA6_FPOV_WE', 'PH_SC7_PA6_LPOV_WE', 'PH_SC7_PA6_NULL_WE', - 'PH_SC7_PA7_DATA_FIFO_EOP_RD', 'PH_SC7_PA7_DATA_FIFO_RD', - 'PH_SC7_PA7_DATA_FIFO_WE', 'PH_SC7_PA7_DEALLOC_4_0_RD', - 'PH_SC7_PA7_EOPG_WE', 'PH_SC7_PA7_EOP_WE', 'PH_SC7_PA7_EVENT_WE', - 'PH_SC7_PA7_FIFO_EMPTY', 'PH_SC7_PA7_FIFO_FULL', - 'PH_SC7_PA7_FPOV_WE', 'PH_SC7_PA7_LPOV_WE', 'PH_SC7_PA7_NULL_WE', - 'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC7_SEND', - 'PH_SC7_SRPS_WINDOW_VALID', 'PIPELINESTAT_START', - 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', 'PIPE_ALIGNED_SURF', - 'PIPE_CONFIG', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', 'PIPE_ID3', - 'PIPE_INTERLEAVE', 'PIPE_INTERLEAVE_1KB', 'PIPE_INTERLEAVE_256B', - 'PIPE_INTERLEAVE_512B', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', - 'PIPE_PIXEL_RATE_PLL_SOURCE', - 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', - 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', - 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_DEPTH_10BPC', - 'PIXEL_DEPTH_8BPC', 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', - 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', - 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', - 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', - 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', - 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', - 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', - 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', - 'POST_CLAMP_TF0', 'POST_CLAMP_TF1', 'POWER_STATE_ENUM', - 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', - 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CLAMP_TF0', - 'PRE_CLAMP_TF1', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', - 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', - 'PS_PARTIAL_FLUSH', 'PTE_ROW_HEIGHT_LINEAR', - 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', - 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', - 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', - 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', - 'PerfCounter_Vals', 'PipeConfig', 'PipeInterleaveSize', - 'PipeTiling', 'PixelPipeCounterId', 'PixelPipeStride', 'PkrMap', - 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'QuadExportFormat', - 'QuadExportFormatOld', 'RAMA_ACCESS', 'RAMB_ACCESS', 'RANGE_00', - 'RANGE_FF', 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', - 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', - 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', - 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', - 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', - 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', - 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', - 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', - 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', - 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', - 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', - 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', - 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', - 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', - 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', - 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', - 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', - 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', - 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', - 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', - 'RASTER_CONFIG_SE_PAIR_MAP_3', - 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'RB_ALIGNED', - 'RB_ALIGNED_META_SURF', 'RB_UNALIGNED_META_SURF', - 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN', - 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET', - 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET', - 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN', - 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN', - 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK', - 'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE', - 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', - 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', - 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', - 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', - 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', - 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', - 'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE', - 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', - 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', - 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', - 'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE', - 'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE', - 'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY', - 'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3', - 'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD', - 'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD', - 'RDPCS_MEM_PWR_DEEP_SLEEP', 'RDPCS_MEM_PWR_LIGHT_SLEEP', - 'RDPCS_MEM_PWR_NO_FORCE', 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', - 'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', - 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR', - 'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', - 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', - 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE', - 'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4', - 'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42', - 'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46', - 'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50', - 'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54', - 'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16', - 'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', - 'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1', - 'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3', - 'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5', - 'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7', - 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', - 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_BYPASS', - 'RDPCS_SRAMCLK_DISABLE', 'RDPCS_SRAMCLK_ENABLE', - 'RDPCS_SRAMCLK_GATE_DISABLE', 'RDPCS_SRAMCLK_GATE_ENABLE', - 'RDPCS_SRAMCLK_NOT_BYPASS', 'RDPCS_SRAM_EXT_LD_DONE', - 'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE', - 'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE', - 'RDPCS_SYMCLK_DIV2_CLOCK_OFF', 'RDPCS_SYMCLK_DIV2_CLOCK_ON', - 'RDPCS_SYMCLK_DIV2_DISABLE', 'RDPCS_SYMCLK_DIV2_ENABLE', - 'RDPCS_SYMCLK_DIV2_GATE_DISABLE', 'RDPCS_SYMCLK_DIV2_GATE_ENABLE', - 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', - 'RDPCS_TEST_CLK_SEL', 'RDPCS_TEST_CLK_SEL_CFGCLK', - 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', - 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1', - 'RDPCS_TX_FIFO_DISABLE', 'RDPCS_TX_FIFO_ENABLE', - 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', - 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE', - 'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE', - 'RDPCS_TX_SOFT_RESET_ENABLE', - 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', - 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_256_BITS', - 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', - 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', - 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', - 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REFER_TO_DP_SOF', - 'REFER_TO_OTG_SOF', 'REF_ALWAYS', 'REF_EQUAL', 'REF_GEQUAL', - 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', 'REF_NEVER', - 'REF_NOTEQUAL', 'REG_UNALLOCATED_ADDR_READ', - 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', - 'REG_VIRTUAL_WRITE', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', - 'RESERVED_63', 'RESERVED_88', 'RESERVED_89', 'RESERVED_90', - 'RESERVED_91', 'RESERVED_ES', 'RESERVED_LS', 'RESERVED_RDPOLICY', - 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', - 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', - 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', - 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', - 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', - 'RIGHT_EYE', 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', - 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', - 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', - 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', - 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', - 'RMI_PERF_SEL_LAT_FIFO_FULL', - 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', - 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', - 'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC', - 'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2', 'RMI_PERF_SEL_NONE', - 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', - 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', - 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', - 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', - 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', - 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', - 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', - 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', - 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS', - 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', - 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', - 'RMI_PERF_SEL_PRT_FIFO_REQ', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', - 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE', - 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE', - 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', - 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE', - 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', - 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', - 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', - 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', - 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', - 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', - 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', - 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', - 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', - 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', - 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', - 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', - 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', - 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 'RMI_PERF_SEL_TCIW_REQ', - 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', - 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', - 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', - 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', - 'RMI_PERF_SEL_UTCL1_REQUEST', - 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', - 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT', - 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', - 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', - 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', - 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', - 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', - 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', - 'ROTATED_MICRO_TILING', 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', - 'ROTATE_270_DEGREES', 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', - 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', - 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', - 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', - 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RST_PIX_CNT', 'RSV_TAG_RAM', - 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadPolicy', 'ReadSize', - 'Reserved_0x00', 'RingCounterControl', 'RoundMode', 'RowSize', - 'RowTiling', 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS', - 'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2', - 'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', - 'SCL_ALPHA_COEF_ALPHA', 'SCL_ALPHA_COEF_LUMA', 'SCL_AUTOCAL_MODE', - 'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', - 'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_CHROMA', - 'SCL_CHROMA_COEF_LUMA', 'SCL_COEF_2TAP_HARDCODE_OFF', - 'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_ALPHA_HORZ_FILTER', - 'SCL_COEF_ALPHA_VERT_FILTER', 'SCL_COEF_CHROMA_HORZ_FILTER', - 'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL', - 'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER', - 'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', - 'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', - 'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', - 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', - 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', - 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'SC_DB0_TILE_INTERFACE_BUSY', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_DB1_TILE_INTERFACE_BUSY', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', - 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', - 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', - 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', 'SC_FULL_QTR_QUAD', - 'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY', - 'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY', - 'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY', - 'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY', - 'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY', - 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', 'SC_HALF_LSB', - 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED', - 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', - 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', - 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', - 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', - 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOPG_RD', - 'SC_PA0_SC_DATA_FIFO_EOP_RD', 'SC_PA0_SC_DATA_FIFO_RD', - 'SC_PA0_SC_DATA_FIFO_WE', 'SC_PA0_SC_DEALLOC_0_RD', - 'SC_PA0_SC_DEALLOC_1_RD', 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', - 'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', - 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', - 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', - 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', - 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', - 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', - 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', - 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', - 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', - 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', - 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', - 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', - 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', - 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', - 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', - 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', - 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', - 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', - 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', - 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', - 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', - 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', - 'SC_PBB_BUSY_AND_NO_SENDS', 'SC_PBB_END_OF_BATCH', - 'SC_PBB_END_OF_BIN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', - 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', - 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', - 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', - 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', - 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', 'SC_PK_BUSY', - 'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', - 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', - 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', - 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', - 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', - 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', - 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', - 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', - 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', - 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', - 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TO_BE_SCLK_GATE_STALL', - 'SC_PS_TS_EVENT_FIFO_POP', 'SC_PS_TS_EVENT_FIFO_PUSH', - 'SC_PW_BM_PASS_EMPTY_PRIM', 'SC_QTR_FULL_QUAD', - 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', 'SC_QZ0_QUAD_COUNT', - 'SC_QZ0_QUAD_PER_TILE_H0', 'SC_QZ0_QUAD_PER_TILE_H1', - 'SC_QZ0_QUAD_PER_TILE_H10', 'SC_QZ0_QUAD_PER_TILE_H11', - 'SC_QZ0_QUAD_PER_TILE_H12', 'SC_QZ0_QUAD_PER_TILE_H13', - 'SC_QZ0_QUAD_PER_TILE_H14', 'SC_QZ0_QUAD_PER_TILE_H15', - 'SC_QZ0_QUAD_PER_TILE_H16', 'SC_QZ0_QUAD_PER_TILE_H2', - 'SC_QZ0_QUAD_PER_TILE_H3', 'SC_QZ0_QUAD_PER_TILE_H4', - 'SC_QZ0_QUAD_PER_TILE_H5', 'SC_QZ0_QUAD_PER_TILE_H6', - 'SC_QZ0_QUAD_PER_TILE_H7', 'SC_QZ0_QUAD_PER_TILE_H8', - 'SC_QZ0_QUAD_PER_TILE_H9', 'SC_QZ0_TILE_COUNT', - 'SC_QZ0_TILE_COVERED_COUNT', 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', - 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', - 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', - 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', - 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', - 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', - 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', - 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', - 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', - 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', - 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_QUAD_COUNT', - 'SC_QZ2_QUAD_PER_TILE_H0', 'SC_QZ2_QUAD_PER_TILE_H1', - 'SC_QZ2_QUAD_PER_TILE_H10', 'SC_QZ2_QUAD_PER_TILE_H11', - 'SC_QZ2_QUAD_PER_TILE_H12', 'SC_QZ2_QUAD_PER_TILE_H13', - 'SC_QZ2_QUAD_PER_TILE_H14', 'SC_QZ2_QUAD_PER_TILE_H15', - 'SC_QZ2_QUAD_PER_TILE_H16', 'SC_QZ2_QUAD_PER_TILE_H2', - 'SC_QZ2_QUAD_PER_TILE_H3', 'SC_QZ2_QUAD_PER_TILE_H4', - 'SC_QZ2_QUAD_PER_TILE_H5', 'SC_QZ2_QUAD_PER_TILE_H6', - 'SC_QZ2_QUAD_PER_TILE_H7', 'SC_QZ2_QUAD_PER_TILE_H8', - 'SC_QZ2_QUAD_PER_TILE_H9', 'SC_QZ2_TILE_COUNT', - 'SC_QZ2_TILE_COVERED_COUNT', 'SC_QZ2_TILE_NOT_COVERED_COUNT', - 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', - 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', - 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', - 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', - 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', - 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', - 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', - 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', - 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', - 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', - 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', - 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', - 'SC_RESERVED_1', 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', - 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', - 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', - 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', - 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', - 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', - 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', - 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', - 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', - 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', - 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', - 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_SEND', - 'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY', - 'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB_QUAD', - 'SC_STALLED_BY_DB_TILE', 'SC_STALLED_BY_PRIMFIFO', - 'SC_STALLED_BY_QUADFIFO', 'SC_STALLED_BY_SPI', - 'SC_STALLED_BY_TILEFIFO', 'SC_STALLED_BY_TILEORDERFIFO', - 'SC_STARVED_BY_DB_QUAD', 'SC_STARVED_BY_DB_TILE', - 'SC_STARVED_BY_PA', 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 'SC_SUPERTILE_COUNT', - 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', - 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', - 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', - 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', - 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', - 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', - 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', - 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', - 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', - 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', - 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', - 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', - 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', - 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', - 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', - 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', - 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', - 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', - 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', - 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', - 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', - 'SDMA_PERF_SEL', 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 'SDMA_PERF_SEL_CE_DST_IDLE', 'SDMA_PERF_SEL_CE_INFO1_FULL', - 'SDMA_PERF_SEL_CE_INFO_FULL', 'SDMA_PERF_SEL_CE_IN_IDLE', - 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', - 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', - 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', - 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', - 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', - 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GCR_RTN', - 'SDMA_PERF_SEL_GCR_SEND', 'SDMA_PERF_SEL_GFX_SELECT', - 'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH', - 'SDMA_PERF_SEL_GPUVM_INVREQ_LOW', 'SDMA_PERF_SEL_IB_CMD_FULL', - 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', - 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', - 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', - 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', - 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', - 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', - 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', - 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', - 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', - 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', - 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', - 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', - 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', - 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', - 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', - 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', - 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', - 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WR_BA_RTR', - 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', - 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', - 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEM_ECC_ERROR', - 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', - 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', - 'SEM_PERF_SEL_ATC_VM_INVALIDATION', 'SEM_PERF_SEL_ATC_XNACK', - 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', - 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', - 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', - 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', - 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', - 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', - 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', - 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', - 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_FE_ID', - 'SET_STATIC_SCREEN_SMU_INTR', 'SH_MEM_ADDRESS_MODE', - 'SH_MEM_ADDRESS_MODE_32', 'SH_MEM_ADDRESS_MODE_64', - 'SH_MEM_ALIGNMENT_MODE', 'SH_MEM_ALIGNMENT_MODE_DWORD', - 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', - 'SH_MEM_RETRY_MODE', 'SH_MEM_RETRY_MODE_ALL', - 'SH_MEM_RETRY_MODE_NONE', 'SH_MEM_RETRY_MODE_WRITEATOMIC', - 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', - 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', - 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', - 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', - 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', - 'SIXTEEN_BANKS', 'SIXTEEN_PIPES', 'SIXTY_FOUR_PIPES', 'SIZE_16K', - 'SIZE_8K', 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', - 'SM_MODE_RESERVED', 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', - 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', - 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', - 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', - 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', - 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', - 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', - 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', - 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', - 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', - 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', - 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', - 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ESC_VTX_BUSY', - 'SPI_PERF_ESC_VTX_CAC_BUSY', 'SPI_PERF_ESC_VTX_INPUT_STARVED', - 'SPI_PERF_ESC_VTX_VSR_FULL', 'SPI_PERF_ESC_VTX_VSR_STALL', - 'SPI_PERF_ES_BUSY', 'SPI_PERF_ES_CRAWLER_STALL', - 'SPI_PERF_ES_EVENT_WAVE', 'SPI_PERF_ES_FIRST_SUBGRP', - 'SPI_PERF_ES_FIRST_WAVE', 'SPI_PERF_ES_LAST_SUBGRP', - 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', - 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', - 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', - 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', - 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', - 'SPI_PERF_GSC_VTX_BUSY', 'SPI_PERF_GSC_VTX_CAC_BUSY', - 'SPI_PERF_GSC_VTX_INPUT_STARVED', 'SPI_PERF_GSC_VTX_VSR_FULL', - 'SPI_PERF_GSC_VTX_VSR_STALL', 'SPI_PERF_GS_BUSY', - 'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE', - 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_GRP_FIFO_FULL', - 'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_LAST_SUBGRP', - 'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY', 'SPI_PERF_GS_NGG_PC_FULL', - 'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT', - 'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT', - 'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON', - 'SPI_PERF_GS_NGG_SE_FORWARDED_BATON', - 'SPI_PERF_GS_NGG_SE_HAS_BATON', - 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT', - 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', - 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', - 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', - 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', - 'SPI_PERF_HS_LAST_WAVE', 'SPI_PERF_HS_OFFCHIP_LDS_STALL', - 'SPI_PERF_HS_PERS_UPD_FULL0', 'SPI_PERF_HS_PERS_UPD_FULL1', - 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', - 'SPI_PERF_LDS0_PC_VALID', 'SPI_PERF_LDS1_PC_VALID', - 'SPI_PERF_LS_BUSY', 'SPI_PERF_LS_CRAWLER_STALL', - 'SPI_PERF_LS_EVENT_WAVE', 'SPI_PERF_LS_FIRST_WAVE', - 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_OFFCHIP_LDS_STALL', - 'SPI_PERF_LS_PERS_UPD_FULL0', 'SPI_PERF_LS_PERS_UPD_FULL1', - 'SPI_PERF_LS_WAVE', 'SPI_PERF_LS_WINDOW_VALID', - 'SPI_PERF_NUM_EXPGRANT_EXPORTS', 'SPI_PERF_NUM_PS_COL_R0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_R1_EXPORTS', - 'SPI_PERF_NUM_VS_GDS_R0_EXPORTS', - 'SPI_PERF_NUM_VS_GDS_R1_EXPORTS', - 'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS', - 'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS', - 'SPI_PERF_NUM_VS_POS_R0_EXPORTS', - 'SPI_PERF_NUM_VS_POS_R1_EXPORTS', 'SPI_PERF_PC_ALLOC_ACCUM', - 'SPI_PERF_PIX_ALLOC_DB0_STALL', 'SPI_PERF_PIX_ALLOC_DB1_STALL', - 'SPI_PERF_PIX_ALLOC_DB2_STALL', 'SPI_PERF_PIX_ALLOC_DB3_STALL', - 'SPI_PERF_PIX_ALLOC_DB4_STALL', 'SPI_PERF_PIX_ALLOC_DB5_STALL', - 'SPI_PERF_PIX_ALLOC_DB6_STALL', 'SPI_PERF_PIX_ALLOC_DB7_STALL', - 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PIX_ALLOC_SCB0_STALL', - 'SPI_PERF_PIX_ALLOC_SCB1_STALL', 'SPI_PERF_PIX_ALLOC_SCB2_STALL', - 'SPI_PERF_PIX_ALLOC_SCB3_STALL', 'SPI_PERF_PS0_ACTIVE', - 'SPI_PERF_PS0_BUSY', 'SPI_PERF_PS0_CNF_BIN2', - 'SPI_PERF_PS0_CNF_BIN3', 'SPI_PERF_PS0_CRAWLER_STALL', - 'SPI_PERF_PS0_DEALLOC_BIN0', 'SPI_PERF_PS0_EVENT_WAVE', - 'SPI_PERF_PS0_FPOS_BIN1_STALL', 'SPI_PERF_PS0_FPOS_BIN2', - 'SPI_PERF_PS0_LDS_RES_FULL', 'SPI_PERF_PS0_OPT_WAVE', - 'SPI_PERF_PS0_PASS_BIN0', 'SPI_PERF_PS0_PASS_BIN1', - 'SPI_PERF_PS0_POPS_WAVE_EXIT', 'SPI_PERF_PS0_POPS_WAVE_SENT', - 'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1', - 'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WINDOW_VALID', - 'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY', - 'SPI_PERF_PS1_CNF_BIN2', 'SPI_PERF_PS1_CNF_BIN3', - 'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC_BIN0', - 'SPI_PERF_PS1_EVENT_WAVE', 'SPI_PERF_PS1_FPOS_BIN1_STALL', - 'SPI_PERF_PS1_FPOS_BIN2', 'SPI_PERF_PS1_LDS_RES_FULL', - 'SPI_PERF_PS1_OPT_WAVE', 'SPI_PERF_PS1_PASS_BIN0', - 'SPI_PERF_PS1_PASS_BIN1', 'SPI_PERF_PS1_POPS_WAVE_EXIT', - 'SPI_PERF_PS1_POPS_WAVE_SENT', 'SPI_PERF_PS1_PRIM_BIN0', - 'SPI_PERF_PS1_PRIM_BIN1', 'SPI_PERF_PS1_WAVE', - 'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_ACTIVE', - 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CNF_BIN2', - 'SPI_PERF_PS2_CNF_BIN3', 'SPI_PERF_PS2_CRAWLER_STALL', - 'SPI_PERF_PS2_DEALLOC_BIN0', 'SPI_PERF_PS2_EVENT_WAVE', - 'SPI_PERF_PS2_FPOS_BIN1_STALL', 'SPI_PERF_PS2_FPOS_BIN2', - 'SPI_PERF_PS2_LDS_RES_FULL', 'SPI_PERF_PS2_OPT_WAVE', - 'SPI_PERF_PS2_PASS_BIN0', 'SPI_PERF_PS2_PASS_BIN1', - 'SPI_PERF_PS2_POPS_WAVE_EXIT', 'SPI_PERF_PS2_POPS_WAVE_SENT', - 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', - 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WINDOW_VALID', - 'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY', - 'SPI_PERF_PS3_CNF_BIN2', 'SPI_PERF_PS3_CNF_BIN3', - 'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC_BIN0', - 'SPI_PERF_PS3_EVENT_WAVE', 'SPI_PERF_PS3_FPOS_BIN1_STALL', - 'SPI_PERF_PS3_FPOS_BIN2', 'SPI_PERF_PS3_LDS_RES_FULL', - 'SPI_PERF_PS3_OPT_WAVE', 'SPI_PERF_PS3_PASS_BIN0', - 'SPI_PERF_PS3_PASS_BIN1', 'SPI_PERF_PS3_POPS_WAVE_EXIT', - 'SPI_PERF_PS3_POPS_WAVE_SENT', 'SPI_PERF_PS3_PRIM_BIN0', - 'SPI_PERF_PS3_PRIM_BIN1', 'SPI_PERF_PS3_WAVE', - 'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_PERS_UPD_FULL0', - 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', - 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 'SPI_PERF_RA_CSG_LOCK', 'SPI_PERF_RA_CSN_LOCK', - 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', - 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', - 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', - 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', - 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', - 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', - 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', - 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', - 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', - 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', - 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', - 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', - 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', - 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', - 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', - 'SPI_PERF_SWC_CSC_WR', 'SPI_PERF_SWC_CSG_WR', - 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR', - 'SPI_PERF_SWC_VS_WR', 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', - 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', - 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', - 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', - 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', - 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_ALLOC_CNT', - 'SPI_PERF_VS_PC_STALL', 'SPI_PERF_VS_PERS_UPD_FULL0', - 'SPI_PERF_VS_PERS_UPD_FULL1', 'SPI_PERF_VS_POS0_STALL', - 'SPI_PERF_VS_POS1_STALL', 'SPI_PERF_VS_WAVE', - 'SPI_PERF_VS_WINDOW_VALID', 'SPI_PERF_VWC_CSC_WR', - 'SPI_PERF_VWC_CSG_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR', - 'SPI_PERF_VWC_PS_WR', 'SPI_PERF_VWC_VS_WR', - 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', - 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', - 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', - 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', - 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', - 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', - 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', - 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', - 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', - 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', - 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', - 'SP_PERF_SEL_DUMMY_BEGIN', 'SP_PERF_SEL_DUMMY_LAST', - 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', - 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', - 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', - 'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK', 'SQC_PERF_SEL_DCACHE_HITS', - 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', - 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', - 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', - 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ', - 'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL', - 'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL', - 'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS', - 'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS', - 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT', - 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS', - 'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT', - 'SQC_PERF_SEL_DCACHE_UTCL0_XNACK', - 'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ', - 'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_WB_ASYNC', 'SQC_PERF_SEL_DCACHE_WB_INST', - 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', - 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', - 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', - 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', - 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', - 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', - 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ', - 'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL', - 'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS', - 'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST', - 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES', - 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT', - 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL', - 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT', - 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS', - 'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT', - 'SQC_PERF_SEL_ICACHE_UTCL0_XNACK', - 'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ', - 'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 'SQC_PERF_SEL_LDS_CMD_FIFO_FULL', - 'SQC_PERF_SEL_LDS_DATA_FIFO_FULL', - 'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL', - 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_POWER_ALU_BUSY', - 'SQC_PERF_SEL_POWER_GPR_RD', 'SQC_PERF_SEL_POWER_GPR_WR', - 'SQC_PERF_SEL_POWER_LDS_BUSY', 'SQC_PERF_SEL_POWER_TEX_BUSY', - 'SQC_PERF_SEL_POWER_VALU', 'SQC_PERF_SEL_POWER_VALU0', - 'SQC_PERF_SEL_POWER_VALU1', 'SQC_PERF_SEL_POWER_VALU2', - 'SQC_PERF_SEL_PT_POWER_STALL', 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', - 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', - 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', - 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', - 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', - 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQG_PERF_SEL_DUMMY_LAST', - 'SQG_PERF_SEL_TLB_SHOOTDOWN', 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES', - 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', - 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL', - 'SQG_PERF_SEL_UTCL0_LFIFO_FULL', - 'SQG_PERF_SEL_UTCL0_PERMISSION_MISS', - 'SQG_PERF_SEL_UTCL0_REQUEST', - 'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'SQG_PERF_SEL_UTCL0_UTCL1_REQ', 'SQIND_GLOBAL_REGS_OFFSET', - 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', - 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', - 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', - 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', - 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', - 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', - 'SQPWRDEC_END', 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', - 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', - 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', - 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', - 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', - 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', - 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', - 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', - 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', - 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', - 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', - 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', - 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', - 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', - 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', - 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', - 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', - 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', - 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', - 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', - 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', - 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', - 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', - 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', - 'SQ_IND_CMD_CMD_DEBUG', 'SQ_IND_CMD_CMD_KILL', - 'SQ_IND_CMD_CMD_NULL', 'SQ_IND_CMD_CMD_SAVECTX', - 'SQ_IND_CMD_CMD_SETFATALHALT', 'SQ_IND_CMD_CMD_SETHALT', - 'SQ_IND_CMD_CMD_SET_SPI_PRIO', 'SQ_IND_CMD_CMD_SINGLE_STEP', - 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', - 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', - 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', - 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', - 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', - 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', - 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', - 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', - 'SQ_INTERRUPT_WORD_ENCODING_ERROR', - 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_MAX_PGM_SGPRS', - 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', 'SQ_OOB_COMPLETE', - 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', - 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', - 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', - 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', - 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', - 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', - 'SQ_PERF_SEL_IFETCH_XNACK', 'SQ_PERF_SEL_INSTS_ALL', - 'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', 'SQ_PERF_SEL_INSTS_EXP', - 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', - 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', - 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', - 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', - 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_TEX', - 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_REPLAY', - 'SQ_PERF_SEL_INSTS_TEX_STORE', 'SQ_PERF_SEL_INSTS_VALU', - 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD', - 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP', 'SQ_PERF_SEL_INSTS_WAVE32', - 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CACHE_REQS', 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', - 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 'SQ_PERF_SEL_INST_CYCLES_LDS', 'SQ_PERF_SEL_INST_CYCLES_TEX', - 'SQ_PERF_SEL_INST_CYCLES_VALU', - 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', - 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', - 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_LEVEL_WAVES', - 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU', - 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU', - 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM', 'SQ_PERF_SEL_MSG', - 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', - 'SQ_PERF_SEL_NONE', 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_Reserved_1', - 'SQ_PERF_SEL_Reserved_10', 'SQ_PERF_SEL_Reserved_11', - 'SQ_PERF_SEL_Reserved_12', 'SQ_PERF_SEL_Reserved_13', - 'SQ_PERF_SEL_Reserved_14', 'SQ_PERF_SEL_Reserved_15', - 'SQ_PERF_SEL_Reserved_16', 'SQ_PERF_SEL_Reserved_17', - 'SQ_PERF_SEL_Reserved_18', 'SQ_PERF_SEL_Reserved_2', - 'SQ_PERF_SEL_Reserved_3', 'SQ_PERF_SEL_Reserved_4', - 'SQ_PERF_SEL_Reserved_5', 'SQ_PERF_SEL_Reserved_6', - 'SQ_PERF_SEL_Reserved_7', 'SQ_PERF_SEL_Reserved_8', - 'SQ_PERF_SEL_Reserved_9', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL', 'SQ_PERF_SEL_USER0', - 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', - 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', - 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', - 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', - 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', - 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', - 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', - 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', - 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', - 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', - 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', - 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', - 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', - 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 'SQ_PERF_SEL_VALU_RETURN_SDST', - 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 'SQ_PERF_SEL_VMEM_BUS_STALL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL', - 'SQ_PERF_SEL_VMEM_SECOND_TRY_USED', - 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', 'SQ_PERF_SEL_WAIT_ANY', - 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', - 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 'SQ_PERF_SEL_WAIT_CNT_VMVS', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', - 'SQ_PERF_SEL_WAIT_INST_BR_MSG', 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', - 'SQ_PERF_SEL_WAIT_INST_FLAT', 'SQ_PERF_SEL_WAIT_INST_LDS', - 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_TEX', - 'SQ_PERF_SEL_WAIT_INST_VALU', 'SQ_PERF_SEL_WAIT_INST_VMEM', - 'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP', - 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', 'SQ_PERF_SEL_WAIT_TTRACE', - 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_ITEMS', - 'SQ_PERF_SEL_WAVE64_HALF_SKIP', 'SQ_PERF_SEL_WAVE64_INSTS', - 'SQ_PERF_SEL_WAVE64_ITEMS', 'SQ_PERF_SEL_WAVES', - 'SQ_PERF_SEL_WAVES_32', 'SQ_PERF_SEL_WAVES_64', - 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_LT_16', - 'SQ_PERF_SEL_WAVES_LT_32', 'SQ_PERF_SEL_WAVES_LT_48', - 'SQ_PERF_SEL_WAVES_LT_64', 'SQ_PERF_SEL_WAVES_RESTORED', - 'SQ_PERF_SEL_WAVES_SAVED', 'SQ_PERF_SEL_WAVE_CYCLES', - 'SQ_PERF_SEL_WAVE_READY', 'SQ_PERF_SEL_XNACK_ALL', - 'SQ_PERF_SEL_XNACK_FIRST', 'SQ_ROUND_MINUS_INFINITY', - 'SQ_ROUND_MODE', 'SQ_ROUND_NEAREST_EVEN', - 'SQ_ROUND_PLUS_INFINITY', 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', - 'SQ_RSRC_BUF_RSVD_1', 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', - 'SQ_RSRC_BUF_TYPE', 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', - 'SQ_RSRC_FLAT_RSVD_2', 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', - 'SQ_RSRC_IMG_1D', 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', - 'SQ_RSRC_IMG_2D_ARRAY', 'SQ_RSRC_IMG_2D_MSAA', - 'SQ_RSRC_IMG_2D_MSAA_ARRAY', 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', - 'SQ_RSRC_IMG_RSVD_0', 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', - 'SQ_RSRC_IMG_RSVD_3', 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', - 'SQ_RSRC_IMG_RSVD_6', 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', - 'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', - 'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', - 'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1', - 'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2', - 'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8', - 'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', - 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', - 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 'SQ_TEX_DEPTH_COMPARE_GREATER', - 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', - 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', - 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', - 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', - 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', - 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', - 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', - 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', - 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', - 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', - 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', - 'SQ_TT_INST_EXCLUDE_EXPGNT234', - 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD', 'SQ_TT_MODE', - 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', - 'SQ_TT_MODE_ON', 'SQ_TT_RT_FREQ', 'SQ_TT_RT_FREQ_1024_CLK', - 'SQ_TT_RT_FREQ_4096_CLK', 'SQ_TT_RT_FREQ_NEVER', - 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', 'SQ_TT_TOKEN_MASK_COMP_BIT', - 'SQ_TT_TOKEN_MASK_COMP_SHIFT', 'SQ_TT_TOKEN_MASK_CONFIG_BIT', - 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', - 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', - 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', - 'SQ_TT_TOKEN_MASK_OTHER_BIT', 'SQ_TT_TOKEN_MASK_OTHER_SHIFT', - 'SQ_TT_TOKEN_MASK_READS_BIT', 'SQ_TT_TOKEN_MASK_READS_SHIFT', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', - 'SQ_TT_TOKEN_MASK_SHDEC_BIT', 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_SQDEC_BIT', 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', - 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', - 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', - 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', - 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', - 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_ES_BIT', - 'SQ_TT_WTYPE_INCLUDE_ES_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_LS_BIT', - 'SQ_TT_WTYPE_INCLUDE_LS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', - 'SQ_TT_WTYPE_INCLUDE_VS_BIT', 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT', - 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', - 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', - 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', - 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', - 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', - 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', - 'SQ_WAVE_TYPE_ES', 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', - 'SQ_WAVE_TYPE_LS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', - 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3', - 'SQ_WAVE_TYPE_VS', 'STALL', 'STATIC_SCREEN_SMU_INTR', - 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', - 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', - 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', - 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', - 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', 'STEREO_DISABLED', - 'STREAM_0_SYNCHRONIZATION', - 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_10_SYNCHRONIZATION', - 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION', - 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION', - 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION', - 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION', - 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION', - 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_1_SYNCHRONIZATION', - 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_2_SYNCHRONIZATION', - 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_3_SYNCHRONIZATION', - 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_4_SYNCHRONIZATION', - 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_5_SYNCHRONIZATION', - 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_6_SYNCHRONIZATION', - 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION', - 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION', - 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION', - 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'STRM_PERFMON_STATE_RESERVED_3', - 'STRM_PERFMON_STATE_START_COUNTING', - 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', - 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IS_IND_64B', - 'SURFACE_DCC_IS_NOT_IND_64B', 'SURFACE_FLIP_AWAY_INT_LEVEL', - 'SURFACE_FLIP_AWAY_INT_PULSE', 'SURFACE_FLIP_AWAY_INT_TYPE', - 'SURFACE_FLIP_INT_LEVEL', 'SURFACE_FLIP_INT_PULSE', - 'SURFACE_FLIP_INT_TYPE', 'SURFACE_FLIP_IN_STEREOSYNC', - 'SURFACE_FLIP_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', - 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLED', - 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', - 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', - 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', - 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', - 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', - 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', - 'SURFACE_V_FLIP', 'SURF_16_BANK', 'SURF_2_BANK', 'SURF_4_BANK', - 'SURF_8_BANK', 'SURF_BANK_HEIGHT_1', 'SURF_BANK_HEIGHT_2', - 'SURF_BANK_HEIGHT_4', 'SURF_BANK_HEIGHT_8', 'SURF_BANK_WIDTH_1', - 'SURF_BANK_WIDTH_2', 'SURF_BANK_WIDTH_4', 'SURF_BANK_WIDTH_8', - 'SURF_MACRO_ASPECT_1', 'SURF_MACRO_ASPECT_2', - 'SURF_MACRO_ASPECT_4', 'SURF_MACRO_ASPECT_8', - 'SURF_TILE_SPLIT_128B', 'SURF_TILE_SPLIT_1KB', - 'SURF_TILE_SPLIT_256B', 'SURF_TILE_SPLIT_2KB', - 'SURF_TILE_SPLIT_4KB', 'SURF_TILE_SPLIT_512B', - 'SURF_TILE_SPLIT_64B', 'SU_PERFCNT_SEL', 'SWAP_ALT', - 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWATH_HEIGHT', - 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', - 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SWIZZLE_4KB_D', - 'SWIZZLE_4KB_D_X', 'SWIZZLE_4KB_S', 'SWIZZLE_4KB_S_X', - 'SWIZZLE_64KB_D', 'SWIZZLE_64KB_D_T', 'SWIZZLE_64KB_D_X', - 'SWIZZLE_64KB_R_X', 'SWIZZLE_64KB_S', 'SWIZZLE_64KB_S_T', - 'SWIZZLE_64KB_S_X', 'SWIZZLE_LINEAR', 'SWIZZLE_MODE_ENUM', - 'SWIZZLE_TYPE_ENUM', 'SWIZZLE_VAR_D', 'SWIZZLE_VAR_D_X', - 'SWIZZLE_VAR_S', 'SWIZZLE_VAR_S_X', 'SW_256B_D', 'SW_256B_R', - 'SW_256B_S', 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', - 'SW_4KB_S', 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', - 'SW_64KB_D_T', 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_T', - 'SW_64KB_R_X', 'SW_64KB_S', 'SW_64KB_S_T', 'SW_64KB_S_X', - 'SW_64KB_Z', 'SW_64KB_Z_T', 'SW_64KB_Z_X', 'SW_D', 'SW_L', - 'SW_LINEAR', 'SW_MODE', 'SW_R', 'SW_S', 'SW_VAR_D', 'SW_VAR_D_X', - 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', 'SW_VAR_S_X', 'SW_VAR_Z', - 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', 'SX_CB_RAT_ACK_REQUEST', - 'SX_DOWNCONVERT_FORMAT', 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', - 'SX_PERF_SEL_CLOCK', 'SX_PERF_SEL_CLOCK_DROP_STALL', - 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_COL_SCBD0_STALL', - 'SX_PERF_SEL_COL_SCBD1_STALL', 'SX_PERF_SEL_COL_SCBD_STALL', - 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB0_HALF_QUADS', - 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', - 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', - 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', - 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', - 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', - 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', - 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', - 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', - 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', - 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', - 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', - 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', - 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', - 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', - 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', - 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', - 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', - 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', - 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', - 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', - 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', - 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', - 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', - 'SX_PERF_SEL_PA_REQ_LATENCY', 'SX_PERF_SEL_POS_BUSY', - 'SX_PERF_SEL_POS_SCBD_STALL', 'SX_PERF_SEL_SH_COLOR_STALL', - 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_IDX_STARVE', - 'SX_PERF_SEL_SH_POS_STALL', 'SX_PERF_SEL_SH_POS_STARVE', - 'SX_PERF_SEL_SPLITMODE', 'SX_RT_EXPORT_10_11_11', - 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', - 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', - 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', - 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', - 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', - 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', - 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_RESERVED', - 'SYMCLK_FE_FORCE_SRC_UNIPHYA', 'SYMCLK_FE_FORCE_SRC_UNIPHYB', - 'SYMCLK_FE_FORCE_SRC_UNIPHYC', 'SYMCLK_FE_FORCE_SRC_UNIPHYD', - 'SYMCLK_FE_FORCE_SRC_UNIPHYE', 'SYMCLK_FE_FORCE_SRC_UNIPHYF', - 'SampleSplit', 'SampleSplitBytes', 'ScMap', - 'ScUncertaintyRegionMode', 'ScXsel', 'ScYsel', 'SeEnable', - 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', - 'SeYsel', 'ShaderEngineTileSize', 'SourceFormat', 'Spare_261', - 'Spare_285', 'Spare_286', 'StencilFormat', 'StencilOp', - 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', 'SurfaceNumber', - 'SurfaceSwap', 'SurfaceTiling', 'TA_PERFCOUNT_SEL', - 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_29', - 'TA_PERF_SEL_RESERVED_41', 'TA_PERF_SEL_RESERVED_42', - 'TA_PERF_SEL_RESERVED_43', - 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', - 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 'TA_PERF_SEL_addresser_stalled_cycles', - 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', - 'TA_PERF_SEL_aniso_10_cycle_quads', - 'TA_PERF_SEL_aniso_12_cycle_quads', - 'TA_PERF_SEL_aniso_14_cycle_quads', - 'TA_PERF_SEL_aniso_16_cycle_quads', - 'TA_PERF_SEL_aniso_1_cycle_quads', - 'TA_PERF_SEL_aniso_2_cycle_quads', - 'TA_PERF_SEL_aniso_4_cycle_quads', - 'TA_PERF_SEL_aniso_6_cycle_quads', - 'TA_PERF_SEL_aniso_8_cycle_quads', - 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 'TA_PERF_SEL_aniso_stalled_cycles', - 'TA_PERF_SEL_bilin_point_1_cycle_pixels', - 'TA_PERF_SEL_buffer_atomic_wavefronts', - 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', - 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', - 'TA_PERF_SEL_buffer_coalescable_wavefronts', - 'TA_PERF_SEL_buffer_coalesced_read_cycles', - 'TA_PERF_SEL_buffer_coalesced_write_cycles', - 'TA_PERF_SEL_buffer_read_wavefronts', - 'TA_PERF_SEL_buffer_total_cycles', - 'TA_PERF_SEL_buffer_wavefronts', - 'TA_PERF_SEL_buffer_write_wavefronts', - 'TA_PERF_SEL_color_1_cycle_pixels', - 'TA_PERF_SEL_color_2_cycle_pixels', - 'TA_PERF_SEL_color_3_cycle_pixels', - 'TA_PERF_SEL_color_4_cycle_pixels', - 'TA_PERF_SEL_data_stalled_by_tc_cycles', - 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 'TA_PERF_SEL_deriv_stalled_cycles', - 'TA_PERF_SEL_first_xnack_on_phase0', - 'TA_PERF_SEL_first_xnack_on_phase1', - 'TA_PERF_SEL_first_xnack_on_phase2', - 'TA_PERF_SEL_first_xnack_on_phase3', - 'TA_PERF_SEL_flat_atomic_wavefronts', - 'TA_PERF_SEL_flat_coalesceable_wavefronts', - 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', - 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', - 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', - 'TA_PERF_SEL_image_atomic_wavefronts', - 'TA_PERF_SEL_image_read_wavefronts', - 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', - 'TA_PERF_SEL_image_write_wavefronts', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', - 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', - 'TA_PERF_SEL_mip_2_cycle_pixels', - 'TA_PERF_SEL_mipmap_invalid_samples', - 'TA_PERF_SEL_mipmap_lod_0_samples', - 'TA_PERF_SEL_mipmap_lod_10_samples', - 'TA_PERF_SEL_mipmap_lod_11_samples', - 'TA_PERF_SEL_mipmap_lod_12_samples', - 'TA_PERF_SEL_mipmap_lod_13_samples', - 'TA_PERF_SEL_mipmap_lod_14_samples', - 'TA_PERF_SEL_mipmap_lod_1_samples', - 'TA_PERF_SEL_mipmap_lod_2_samples', - 'TA_PERF_SEL_mipmap_lod_3_samples', - 'TA_PERF_SEL_mipmap_lod_4_samples', - 'TA_PERF_SEL_mipmap_lod_5_samples', - 'TA_PERF_SEL_mipmap_lod_6_samples', - 'TA_PERF_SEL_mipmap_lod_7_samples', - 'TA_PERF_SEL_mipmap_lod_8_samples', - 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', - 'TA_PERF_SEL_sh_fifo_addr_busy', - 'TA_PERF_SEL_sh_fifo_addr_cycles', - 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', - 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', - 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', - 'TA_PERF_SEL_sh_fifo_data_busy', - 'TA_PERF_SEL_sh_fifo_data_cycles', - 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', - 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', - 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', - 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', - 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', - 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', - 'TA_PERF_SEL_ta_fa_data_state_cycles', - 'TA_PERF_SEL_ta_sh_fifo_starved', 'TA_PERF_SEL_total_wavefronts', - 'TA_PERF_SEL_vol_1_cycle_pixels', - 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', - 'TA_PERF_SEL_write_path_busy', - 'TA_PERF_SEL_write_path_input_cycles', - 'TA_PERF_SEL_write_path_output_cycles', - 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', - 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', - 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', - 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', - 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', - 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', - 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', - 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', - 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', - 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', - 'TCC_CACHE_POLICIES', 'TCC_CACHE_POLICY_LRU', - 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', 'TCP_CACHE_POLICIES', - 'TCP_CACHE_POLICY_HIT_EVICT', 'TCP_CACHE_POLICY_HIT_LRU', - 'TCP_CACHE_POLICY_MISS_EVICT', 'TCP_CACHE_POLICY_MISS_LRU', - 'TCP_CACHE_STORE_POLICIES', 'TCP_CACHE_STORE_POLICY_WT_EVICT', - 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', - 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', - 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', - 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', - 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', - 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', - 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', - 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_READ', 'TCP_OPCODE_TYPE', - 'TCP_OPCODE_WBINVL1', 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', - 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', - 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', - 'TCP_PERF_SEL_CP_TCP_INVALIDATE', 'TCP_PERF_SEL_GATE_EN1', - 'TCP_PERF_SEL_GATE_EN2', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY', - 'TCP_PERF_SEL_GL1_REQ_WRITE', - 'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY', - 'TCP_PERF_SEL_HOLE_READ_STALL', 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', - 'TCP_PERF_SEL_LOD_STALL_CYCLES', - 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', - 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', - 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_REQ_MISS_TAGRAM0', 'TCP_PERF_SEL_REQ_MISS_TAGRAM1', - 'TCP_PERF_SEL_REQ_MISS_TAGRAM2', 'TCP_PERF_SEL_REQ_MISS_TAGRAM3', - 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', 'TCP_PERF_SEL_SHOOTDOWN', - 'TCP_PERF_SEL_TAGRAM0_REQ', 'TCP_PERF_SEL_TAGRAM1_REQ', - 'TCP_PERF_SEL_TAGRAM2_REQ', 'TCP_PERF_SEL_TAGRAM3_REQ', - 'TCP_PERF_SEL_TA_REQ', 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_TA_REQ_READ', - 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', - 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', - 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', - 'TCP_PERF_SEL_TA_TCP_STATE_READ', - 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', - 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', - 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', - 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DCC_REQ', - 'TCP_PERF_SEL_TCC_LRU_REQ', 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_NC_READ_REQ', 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', - 'TCP_PERF_SEL_TCC_READ_REQ', 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', - 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', - 'TCP_PERF_SEL_TCC_WRITE_REQ', - 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', - 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', - 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', - 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', - 'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES', - 'TCP_PERF_SEL_TCR_RDRET_STALL', - 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', - 'TCP_PERF_SEL_TC_TA_XNACK_STALL', - 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', 'TCP_PERF_SEL_TOTAL_ACCESSES', - 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES', - 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', - 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', - 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', - 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', - 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', - 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', - 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WRITE', - 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', - 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 'TCP_PERF_SEL_UTCL0_LFIFO_FULL', - 'TCP_PERF_SEL_UTCL0_PERMISSION_MISS', - 'TCP_PERF_SEL_UTCL0_REQUEST', - 'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL', - 'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT', - 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', - 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', - 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', - 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', - 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', - 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', - 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', - 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', - 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', - 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', - 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', - 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', - 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', - 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', - 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', - 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', - 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', - 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', - 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', - 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', - 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', - 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', - 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', - 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', - 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', - 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', - 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', - 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', - 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', - 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', - 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', - 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', - 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', - 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', - 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', - 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', - 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', - 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', - 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', - 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', - 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', - 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', - 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', - 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', - 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', - 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', - 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', - 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', - 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', - 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', - 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', - 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', - 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', - 'TD_PERF_SEL_RESERVED_21', 'TD_PERF_SEL_RESERVED_8', - 'TD_PERF_SEL_address_cmd_poison', - 'TD_PERF_SEL_bypassLerp_wavefront', - 'TD_PERF_SEL_core_state_rams_read', - 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 'TD_PERF_SEL_done_scoreboard_is_full', - 'TD_PERF_SEL_done_scoreboard_not_empty', - 'TD_PERF_SEL_four_comp_wavefront', - 'TD_PERF_SEL_gather4_wavefront', - 'TD_PERF_SEL_gather4h_packed_wavefront', - 'TD_PERF_SEL_gather4h_wavefront', - 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_input_busy', - 'TD_PERF_SEL_input_state_fifo_full', - 'TD_PERF_SEL_ldfptr_wavefront', 'TD_PERF_SEL_lds_stall', - 'TD_PERF_SEL_load_wavefront', 'TD_PERF_SEL_lod_warn_from_ta', - 'TD_PERF_SEL_min_max_filter_wavefront', - 'TD_PERF_SEL_mixmode_instruction', 'TD_PERF_SEL_mixmode_resource', - 'TD_PERF_SEL_nofilter_busy', - 'TD_PERF_SEL_nofilter_formatters_turned_off', - 'TD_PERF_SEL_nofilter_pkr_full', - 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_none', 'TD_PERF_SEL_one_comp_wavefront', - 'TD_PERF_SEL_opaque_black_border', - 'TD_PERF_SEL_out_of_order_instr', - 'TD_PERF_SEL_reference_data_rams_read', - 'TD_PERF_SEL_sample_c_wavefront', 'TD_PERF_SEL_sampler_lerp_busy', - 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_pkr_full', - 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_wavefront', - 'TD_PERF_SEL_ta_data_stall', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr', - 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', - 'TD_PERF_SEL_tc_td_data_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_full', 'TD_PERF_SEL_td_busy', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr', - 'TD_PERF_SEL_three_comp_wavefront', 'TD_PERF_SEL_total_num_instr', - 'TD_PERF_SEL_two_comp_wavefront', - 'TD_PERF_SEL_user_defined_border', - 'TD_PERF_SEL_wavefront_dest_is_lds', - 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', - 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', - 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', - 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', - 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', - 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', 'TEST_CLK_SEL_8', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', - 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', - 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', - 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', - 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', - 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', - 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', - 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', - 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', - 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', - 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', - 'TEX_Clamp_MirrorOnceHalfToBorder', - 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', - 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', - 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', - 'TEX_DIM', 'TEX_DepthCompareFunction_Always', - 'TEX_DepthCompareFunction_Equal', - 'TEX_DepthCompareFunction_Greater', - 'TEX_DepthCompareFunction_GreaterEqual', - 'TEX_DepthCompareFunction_Less', - 'TEX_DepthCompareFunction_LessEqual', - 'TEX_DepthCompareFunction_Never', - 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', - 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', - 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', - 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', - 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', - 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', - 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', - 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', - 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', - 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', - 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', - 'TEX_MipFilter_None', 'TEX_MipFilter_Point', - 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', - 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', - 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', - 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', - 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', - 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', - 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', - 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', - 'THICK_MICRO_TILING', 'THIN_MICRO_TILING', 'THIRTY_TWO_PIPES', - 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', - 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TILE_SPLIT', - 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', - 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', - 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', - 'TMDS_CTL0_DATA_MODULATION_BIT1', - 'TMDS_CTL0_DATA_MODULATION_BIT2', - 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', - 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', - 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', - 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', - 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', - 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', - 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', - 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', - 'TMDS_CTL1_DATA_MODULATION_BIT0', - 'TMDS_CTL1_DATA_MODULATION_BIT1', - 'TMDS_CTL1_DATA_MODULATION_BIT2', - 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', - 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', - 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', - 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', - 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', - 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', - 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', - 'TMDS_CTL2_DATA_MODULATION_BIT0', - 'TMDS_CTL2_DATA_MODULATION_BIT1', - 'TMDS_CTL2_DATA_MODULATION_BIT2', - 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', - 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', - 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', - 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', - 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', - 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', - 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', - 'TMDS_CTL3_DATA_MODULATION_BIT0', - 'TMDS_CTL3_DATA_MODULATION_BIT1', - 'TMDS_CTL3_DATA_MODULATION_BIT2', - 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', - 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', - 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', - 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', - 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', - 'TMDS_CTL3_PATTERN_OUT_ENABLE', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', - 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', - 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', - 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', - 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', - 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', - 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', - 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', - 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', - 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', - 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', - 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', - 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', - 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', - 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', - 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', - 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', - 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', - 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', - 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', - 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', - 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', - 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', - 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', - 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', - 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', - 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', - 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', - 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', - 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', - 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', - 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', - 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', - 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', - 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', - 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', - 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', - 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', - 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', - 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', - 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', - 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', - 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', - 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', - 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', - 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', - 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', - 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', - 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', - 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', - 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', - 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', - 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', - 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', - 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', - 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', - 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', - 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', - 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', - 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', - 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', - 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', - 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', - 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', - 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', - 'TVX_Type_ValidVertexBuffer', 'TWO_BANKS', 'TWO_FRAGMENTS', - 'TWO_PIPES', 'TWO_RB_PER_SE', 'TWO_SHADER_ENGINS', 'TileSplit', - 'TileType', 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', - 'UNCACHED_RD', 'UNCACHED_WR', 'UNDEF', 'UNSIGNED', - 'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', - 'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN', - 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY', - 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel', - 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', - 'UTCL1_PERF_SEL_HITS', 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 'UTCL1_PERF_SEL_MISSES', 'UTCL1_PERF_SEL_NONE', - 'UTCL1_PERF_SEL_NONRANGE_INV_REQS', - 'UTCL1_PERF_SEL_NUM_BIGK_PAGES', - 'UTCL1_PERF_SEL_NUM_SMALLK_PAGES', - 'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM', - 'UTCL1_PERF_SEL_RANGE_INV_REQS', 'UTCL1_PERF_SEL_REQS', - 'UTCL1_PERF_SEL_STALL_MH_CAM_FULL', - 'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL', - 'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS', - 'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS', 'UTCL1_TYPE_BYPASS', - 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', - 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', - 'UTCL1_XNACK_SUCCESS', 'UVDFC_BITSTREAM_ADDR', - 'UVDFC_BITSTREAM_SIZE', 'UVDFC_DECODED_ADDR', - 'UVDFC_DISPLAY_ADDR', 'UVDFC_DISPLAY_PITCH', - 'UVDFC_DISPLAY_TILING', 'UVDFC_EOD', 'UVDFC_FENCE', - 'UVDFC_ITBUF_ADDR', 'UVDFC_MBLOCK_ADDR', 'UVDFC_TRAP', - 'UVDFirmwareCommand', 'VC_AND_TC', 'VC_ONLY', - 'VGT_CACHE_INVALID_MODE', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', - 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', - 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', - 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', - 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', - 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', - 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', - 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', - 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', - 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', - 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', - 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', - 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', - 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', - 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', - 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', - 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', - 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', - 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', - 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', - 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', - 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', - 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', - 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PRIM_GEN', - 'VGT_OUTPATH_SELECT', 'VGT_OUTPATH_TE_GS_BLOCK', - 'VGT_OUTPATH_TE_OUTPUT', 'VGT_OUTPATH_TE_PRIM_GEN', - 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', - 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', 'VGT_OUT_POINT', - 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', - 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', - 'VGT_OUT_TRI_ADJ', 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', - 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', - 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', - 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', - 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', - 'VGT_TE_PRIM_INDEX_LINE', 'VGT_TE_PRIM_INDEX_QUAD', - 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', 'VID_ENHANCED_MODE', - 'VID_NORMAL_FRAME_MODE', 'VID_STREAM_DISABLE_MASKED', - 'VID_STREAM_DISABLE_UNMASK', 'VMEMCMD_RETURN_IN_ORDER', - 'VMEMCMD_RETURN_IN_ORDER_READ', 'VMEMCMD_RETURN_ORDER', - 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', 'VMPG_SIZE', - 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VREADY_AT_OR_AFTER_VSYNC', - 'VREADY_BEFORE_VSYNC', 'VSYNC_CNT_LATCH_MASK', - 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', - 'VSYNC_CNT_REFCLK_SEL', 'VSYNC_CNT_REFCLK_SEL_0', - 'VSYNC_CNT_REFCLK_SEL_1', 'VSYNC_CNT_RESET_SEL', - 'VSYNC_CNT_RESET_SEL_0', 'VSYNC_CNT_RESET_SEL_1', - 'VS_PARTIAL_FLUSH', 'VS_PS', 'VS_STAGE_COPY_SHADER', - 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTG_SEL_0', 'VTG_SEL_1', - 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5', 'VTX_CLAMP', - 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', - 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', - 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', - 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', - 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', - 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', - 'WBSCL_BACKPRESSURE_CNT_DISABLE', 'WBSCL_BACKPRESSURE_CNT_ENABLE', - 'WBSCL_BACKPRESSURE_CNT_EN_ENUM', 'WBSCL_COEF_CHROMA_HORZ_FILTER', - 'WBSCL_COEF_CHROMA_VERT_FILTER', 'WBSCL_COEF_FILTER_TYPE_SEL', - 'WBSCL_COEF_LUMA_HORZ_FILTER', 'WBSCL_COEF_LUMA_VERT_FILTER', - 'WBSCL_COEF_RAM_FILTER_TYPE_ENUM', - 'WBSCL_COEF_RAM_FILTER_TYPE_HC', 'WBSCL_COEF_RAM_FILTER_TYPE_HL', - 'WBSCL_COEF_RAM_FILTER_TYPE_VC', 'WBSCL_COEF_RAM_FILTER_TYPE_VL', - 'WBSCL_COEF_RAM_PHASE0', 'WBSCL_COEF_RAM_PHASE1', - 'WBSCL_COEF_RAM_PHASE2', 'WBSCL_COEF_RAM_PHASE3', - 'WBSCL_COEF_RAM_PHASE4', 'WBSCL_COEF_RAM_PHASE5', - 'WBSCL_COEF_RAM_PHASE6', 'WBSCL_COEF_RAM_PHASE7', - 'WBSCL_COEF_RAM_PHASE8', 'WBSCL_COEF_RAM_PHASE_ENUM', - 'WBSCL_COEF_RAM_RD_SEL_0', 'WBSCL_COEF_RAM_RD_SEL_1', - 'WBSCL_COEF_RAM_RD_SEL_ENUM', 'WBSCL_COEF_RAM_SEL_0', - 'WBSCL_COEF_RAM_SEL_1', 'WBSCL_COEF_RAM_SEL_ENUM', - 'WBSCL_COEF_RAM_TAP_COEF_DISABLE', - 'WBSCL_COEF_RAM_TAP_COEF_ENABLE', - 'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM', 'WBSCL_COEF_RAM_TAP_PAIR_IDX0', - 'WBSCL_COEF_RAM_TAP_PAIR_IDX1', 'WBSCL_COEF_RAM_TAP_PAIR_IDX2', - 'WBSCL_COEF_RAM_TAP_PAIR_IDX3', 'WBSCL_COEF_RAM_TAP_PAIR_IDX4', - 'WBSCL_COEF_RAM_TAP_PAIR_IDX5', - 'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM', - 'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM', - 'WBSCL_DATA_OVERFLOW_INT_TYPE_HW', - 'WBSCL_DATA_OVERFLOW_INT_TYPE_REG', - 'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM', - 'WBSCL_HOST_CONFLICT_INT_TYPE_HW', - 'WBSCL_HOST_CONFLICT_INT_TYPE_REG', 'WBSCL_LB_MEM_PWR_FORCE_DS', - 'WBSCL_LB_MEM_PWR_FORCE_ENUM', 'WBSCL_LB_MEM_PWR_FORCE_LS', - 'WBSCL_LB_MEM_PWR_FORCE_NO', 'WBSCL_LB_MEM_PWR_FORCE_SD', - 'WBSCL_LB_MEM_PWR_MODE_SEL_DS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM', - 'WBSCL_LB_MEM_PWR_MODE_SEL_LS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ON', - 'WBSCL_LB_MEM_PWR_MODE_SEL_SD', 'WBSCL_LUT_MEM_PWR_STATE_ENUM', - 'WBSCL_LUT_MEM_PWR_STATE_LS', 'WBSCL_LUT_MEM_PWR_STATE_ON', - 'WBSCL_LUT_MEM_PWR_STATE_RESERVED2', - 'WBSCL_LUT_MEM_PWR_STATE_RESERVED3', 'WBSCL_MEM_PWR_STATE_DS', - 'WBSCL_MEM_PWR_STATE_ENUM', 'WBSCL_MEM_PWR_STATE_LS', - 'WBSCL_MEM_PWR_STATE_ON', 'WBSCL_MEM_PWR_STATE_SD', - 'WBSCL_MODE_SCALING_444_BYPASS', - 'WBSCL_MODE_SCALING_444_RGB_ENABLE', - 'WBSCL_MODE_SCALING_444_YCBCR_ENABLE', - 'WBSCL_MODE_SCALING_YCBCR_ENABLE', 'WBSCL_MODE_SEL', - 'WBSCL_NUM_OF_TAPS0', 'WBSCL_NUM_OF_TAPS1', 'WBSCL_NUM_OF_TAPS10', - 'WBSCL_NUM_OF_TAPS11', 'WBSCL_NUM_OF_TAPS2', 'WBSCL_NUM_OF_TAPS3', - 'WBSCL_NUM_OF_TAPS4', 'WBSCL_NUM_OF_TAPS5', 'WBSCL_NUM_OF_TAPS6', - 'WBSCL_NUM_OF_TAPS7', 'WBSCL_NUM_OF_TAPS8', 'WBSCL_NUM_OF_TAPS9', - 'WBSCL_NUM_OF_TAPS_ENUM', 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK', - 'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE', - 'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM', 'WBSCL_PIXEL_DEPTH', - 'WBSCL_STATUS_ACK_CLR', 'WBSCL_STATUS_ACK_ENUM', - 'WBSCL_STATUS_ACK_NCLR', 'WBSCL_STATUS_MASK_DISABLE', - 'WBSCL_STATUS_MASK_ENABLE', 'WBSCL_STATUS_MASK_ENUM', - 'WBSCL_TEST_CRC_CONT_DISABLE', 'WBSCL_TEST_CRC_CONT_ENABLE', - 'WBSCL_TEST_CRC_CONT_EN_ENUM', 'WBSCL_TEST_CRC_DISABLE', - 'WBSCL_TEST_CRC_ENABLE', 'WBSCL_TEST_CRC_EN_ENUM', - 'WBSCL_TEST_CRC_MASKED', 'WBSCL_TEST_CRC_MASK_ENUM', - 'WBSCL_TEST_CRC_UNMASKED', 'WB_CLK_GATE_DISABLE', - 'WB_CLK_GATE_DIS_ENUM', 'WB_CLK_GATE_ENABLE', 'WB_ENABLE_ENUM', - 'WB_EN_DISABLE', 'WB_EN_ENABLE', 'WB_MEM_PWR_DISABLE', - 'WB_MEM_PWR_DIS_ENUM', 'WB_MEM_PWR_ENABLE', - 'WB_RAM_PW_SAVE_MODE_ENUM', 'WB_RAM_PW_SAVE_MODE_LS', - 'WB_RAM_PW_SAVE_MODE_SD', 'WB_SOFT_RESET_ENUM', - 'WB_SOFT_RESET_NEG', 'WB_SOFT_RESET_POS', 'WB_TEST_CLK_SEL_ENUM', - 'WB_TEST_CLK_SEL_PERM', 'WB_TEST_CLK_SEL_REG', - 'WB_TEST_CLK_SEL_WB', 'WB_TEST_CLK_SEL_WBSCL', - 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', - 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', - 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', - 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', - 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', - 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', - 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XNORM', - 'XNORM_A', 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', - 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', - 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', - 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', - 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', - 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', - 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', - 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', - 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', - 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', - 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', - 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ON_ALPHA_PORT', - 'Y_G_DATA_ON_CB_B_PORT', 'Y_G_DATA_ON_CR_R_PORT', - 'Y_G_DATA_ON_Y_G_PORT', 'ZFormat', 'ZLimitSumm', 'ZModeForce', - 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', 'ZPASS_PIXELS', - 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', 'Z_24', 'Z_32_FLOAT', - 'Z_INVALID', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', - 'ZpassControl', '_navi10_ENUM_HEADER', 'ge_assembler_busy', - 'ge_assembler_stalled', 'ge_cm_reading_stalled', - 'ge_cm_stalled_by_gog', 'ge_cm_stalled_by_gsfetch_done', - 'ge_dma_busy', 'ge_dma_lat_bin_0', 'ge_dma_lat_bin_1', - 'ge_dma_lat_bin_2', 'ge_dma_lat_bin_3', 'ge_dma_lat_bin_4', - 'ge_dma_lat_bin_5', 'ge_dma_lat_bin_6', 'ge_dma_lat_bin_7', - 'ge_dma_return', 'ge_dma_utcl1_consecutive_retry_event', - 'ge_dma_utcl1_request_event', 'ge_dma_utcl1_retry_event', - 'ge_dma_utcl1_stall_event', 'ge_dma_utcl1_stall_utcl2_event', - 'ge_dma_utcl1_translation_hit_event', - 'ge_dma_utcl1_translation_miss_event', - 'ge_dma_utcl2_stall_on_trans', 'ge_dma_utcl2_trans_ack', - 'ge_dma_utcl2_trans_xnack', 'ge_ds_cache_hits', 'ge_ds_prims', - 'ge_es_done', 'ge_es_done_latency', 'ge_es_flush', - 'ge_es_ring_high_water_mark', 'ge_es_thread_groups', - 'ge_esthread_stalled_es_rb_full', 'ge_esthread_stalled_spi_bp', - 'ge_esvert_stalled_es_tbl', 'ge_esvert_stalled_gs_event', - 'ge_esvert_stalled_gs_tbl', 'ge_esvert_stalled_gsprim', - 'ge_gea_dma_starved', 'ge_gog_busy', 'ge_gog_out_indx_stalled', - 'ge_gog_out_prim_stalled', 'ge_gog_vs_tbl_stalled', - 'ge_gs_cache_hits', 'ge_gs_counters_avail_stalled', 'ge_gs_done', - 'ge_gs_done_latency', 'ge_gs_event_stall', - 'ge_gs_issue_rtr_stalled', 'ge_gs_rb_space_avail_stalled', - 'ge_gs_ring_high_water_mark', 'ge_gsprim_stalled_es_tbl', - 'ge_gsprim_stalled_esvert', 'ge_gsprim_stalled_gs_event', - 'ge_gsprim_stalled_gs_tbl', 'ge_gsthread_stalled', 'ge_hs_done', - 'ge_hs_done_latency', 'ge_hs_done_se0', 'ge_hs_done_se1', - 'ge_hs_done_se2_reserved', 'ge_hs_done_se3_reserved', - 'ge_hs_tfm_stall', 'ge_hs_tgs_active_high_water_mark', - 'ge_hs_thread_groups', 'ge_inside_tf_bin_0', 'ge_inside_tf_bin_1', - 'ge_inside_tf_bin_2', 'ge_inside_tf_bin_3', 'ge_inside_tf_bin_4', - 'ge_inside_tf_bin_5', 'ge_inside_tf_bin_6', 'ge_inside_tf_bin_7', - 'ge_inside_tf_bin_8', 'ge_ls_done', 'ge_ls_done_latency', - 'ge_null_patch', 'ge_pa_clipp_eop', 'ge_pa_clipp_is_event', - 'ge_pa_clipp_new_vtx_vect', 'ge_pa_clipp_null_prim', - 'ge_pa_clipp_send', 'ge_pa_clipp_send_not_event', - 'ge_pa_clipp_stalled', 'ge_pa_clipp_starved_busy', - 'ge_pa_clipp_starved_idle', 'ge_pa_clipp_valid_prim', - 'ge_pa_clips_send', 'ge_pa_clips_stalled', 'ge_pa_clipv_send', - 'ge_pa_clipv_stalled', 'ge_rbiu_di_fifo_stalled', - 'ge_rbiu_di_fifo_starved', 'ge_rbiu_dr_fifo_stalled', - 'ge_rbiu_dr_fifo_starved', 'ge_reused_es_indices', - 'ge_reused_vs_indices', 'ge_sclk_core_vld', 'ge_sclk_gs_vld', - 'ge_sclk_input_vld', 'ge_sclk_leg_gs_arb_vld', 'ge_sclk_ngg_vld', - 'ge_sclk_reg_vld', 'ge_sclk_te11_vld', 'ge_sclk_vr_vld', - 'ge_sclk_wd_te11_vld', 'ge_spi_esvert_eov', - 'ge_spi_esvert_stalled', 'ge_spi_esvert_starved_busy', - 'ge_spi_esvert_valid', 'ge_spi_eswave_is_event', - 'ge_spi_eswave_send', 'ge_spi_gsprim_cont', 'ge_spi_gsprim_eov', - 'ge_spi_gsprim_stalled', 'ge_spi_gsprim_starved_busy', - 'ge_spi_gsprim_starved_idle', 'ge_spi_gsprim_valid', - 'ge_spi_gssubgrp_is_event', 'ge_spi_gssubgrp_send', - 'ge_spi_gswave_is_event', 'ge_spi_gswave_send', - 'ge_spi_hsvert_eov', 'ge_spi_hsvert_stalled', - 'ge_spi_hsvert_starved_busy', 'ge_spi_hsvert_valid', - 'ge_spi_hswave_is_event', 'ge_spi_hswave_send', - 'ge_spi_lsvert_eov', 'ge_spi_lsvert_stalled', - 'ge_spi_lsvert_starved_busy', 'ge_spi_lsvert_starved_idle', - 'ge_spi_lsvert_valid', 'ge_spi_lswave_is_event', - 'ge_spi_lswave_send', 'ge_spi_vsvert_eov', 'ge_spi_vsvert_send', - 'ge_spi_vsvert_stalled', 'ge_spi_vsvert_starved_busy', - 'ge_spi_vsvert_starved_idle', 'ge_spi_vswave_is_event', - 'ge_spi_vswave_send', 'ge_starved_on_hs_done', 'ge_stat_busy', - 'ge_stat_combined_busy', 'ge_stat_no_dma_busy', - 'ge_strmout_stalled', 'ge_te11_busy', 'ge_te11_starved', - 'ge_tfreq_lat_bin_0', 'ge_tfreq_lat_bin_1', 'ge_tfreq_lat_bin_2', - 'ge_tfreq_lat_bin_3', 'ge_tfreq_lat_bin_4', 'ge_tfreq_lat_bin_5', - 'ge_tfreq_lat_bin_6', 'ge_tfreq_lat_bin_7', - 'ge_tfreq_utcl1_consecutive_retry_event', - 'ge_tfreq_utcl1_request_event', 'ge_tfreq_utcl1_retry_event', - 'ge_tfreq_utcl1_stall_event', 'ge_tfreq_utcl1_stall_utcl2_event', - 'ge_tfreq_utcl1_translation_hit_event', - 'ge_tfreq_utcl1_translation_miss_event', - 'ge_tfreq_utcl2_stall_on_trans', 'ge_tfreq_utcl2_trans_ack', - 'ge_tfreq_utcl2_trans_xnack', 'ge_vs_cache_hits', 'ge_vs_done', - 'ge_vs_pc_stall', 'ge_vs_table_high_water_mark', - 'ge_vs_thread_groups', 'ge_vsvert_api_send', 'ge_vsvert_ds_send', - 'ge_wait_for_es_done_stalled', 'ge_waveid_stalled'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/pm4_nv.py b/tinygrad/tinygrad/runtime/autogen/am/pm4_nv.py deleted file mode 100644 index c21fbfb2..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/pm4_nv.py +++ /dev/null @@ -1,962 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -F32_MES_PM4_PACKETS_H = True # macro -uint32_t = True # macro -int32_t = True # macro -PM4_MES_HEADER_DEFINED = True # macro -PM4_MEC_RELEASE_MEM_DEFINED = True # macro -PM4_MEC_WRITE_DATA_DEFINED = True # macro -class union_PM4_MES_TYPE_3_HEADER(Union): - pass - -class struct_PM4_MES_TYPE_3_HEADER_0(Structure): - pass - -struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False -struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('opcode', ctypes.c_uint32, 8), - ('count', ctypes.c_uint32, 14), - ('type', ctypes.c_uint32, 2), -] - -union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False -union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) -union_PM4_MES_TYPE_3_HEADER._fields_ = [ - ('_0', struct_PM4_MES_TYPE_3_HEADER_0), - ('u32All', ctypes.c_uint32), -] - - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 5: 'event_index__mec_release_mem__end_of_pipe', - 6: 'event_index__mec_release_mem__shader_done', -} -event_index__mec_release_mem__end_of_pipe = 5 -event_index__mec_release_mem__shader_done = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'cache_policy__mec_release_mem__lru', - 1: 'cache_policy__mec_release_mem__stream', -} -cache_policy__mec_release_mem__lru = 0 -cache_policy__mec_release_mem__stream = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'pq_exe_status__mec_release_mem__default', - 1: 'pq_exe_status__mec_release_mem__phase_update', -} -pq_exe_status__mec_release_mem__default = 0 -pq_exe_status__mec_release_mem__phase_update = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'dst_sel__mec_release_mem__memory_controller', - 1: 'dst_sel__mec_release_mem__tc_l2', - 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', - 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', -} -dst_sel__mec_release_mem__memory_controller = 0 -dst_sel__mec_release_mem__tc_l2 = 1 -dst_sel__mec_release_mem__queue_write_pointer_register = 2 -dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'int_sel__mec_release_mem__none', - 1: 'int_sel__mec_release_mem__send_interrupt_only', - 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', - 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', -} -int_sel__mec_release_mem__none = 0 -int_sel__mec_release_mem__send_interrupt_only = 1 -int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 -int_sel__mec_release_mem__send_data_after_write_confirm = 3 -int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'data_sel__mec_release_mem__none', - 1: 'data_sel__mec_release_mem__send_32_bit_low', - 2: 'data_sel__mec_release_mem__send_64_bit_data', - 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', - 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', -} -data_sel__mec_release_mem__none = 0 -data_sel__mec_release_mem__send_32_bit_low = 1 -data_sel__mec_release_mem__send_64_bit_data = 2 -data_sel__mec_release_mem__send_gpu_clock_counter = 3 -data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 -data_sel__mec_release_mem__store_gds_data_to_memory = 5 -c_uint32 = ctypes.c_uint32 # enum -class struct_pm4_mec_release_mem(Structure): - pass - -class union_pm4_mec_release_mem_0(Union): - pass - -union_pm4_mec_release_mem_0._pack_ = 1 # source:False -union_pm4_mec_release_mem_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_1(Union): - pass - -class struct_pm4_mec_release_mem_1_bitfields2(Structure): - pass - -struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ - ('event_type', ctypes.c_uint32, 6), - ('reserved1', ctypes.c_uint32, 2), - ('event_index', c_uint32, 4), - ('tcl1_vol_action_ena', ctypes.c_uint32, 1), - ('tc_vol_action_ena', ctypes.c_uint32, 1), - ('reserved2', ctypes.c_uint32, 1), - ('tc_wb_action_ena', ctypes.c_uint32, 1), - ('tcl1_action_ena', ctypes.c_uint32, 1), - ('tc_action_ena', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 1), - ('tc_nc_action_ena', ctypes.c_uint32, 1), - ('tc_wc_action_ena', ctypes.c_uint32, 1), - ('tc_md_action_ena', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 3), - ('cache_policy', c_uint32, 2), - ('reserved5', ctypes.c_uint32, 2), - ('pq_exe_status', c_uint32, 1), - ('reserved6', ctypes.c_uint32, 2), -] - -union_pm4_mec_release_mem_1._pack_ = 1 # source:False -union_pm4_mec_release_mem_1._fields_ = [ - ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_2(Union): - pass - -class struct_pm4_mec_release_mem_2_bitfields3(Structure): - pass - -struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ - ('reserved7', ctypes.c_uint32, 16), - ('dst_sel', c_uint32, 2), - ('reserved8', ctypes.c_uint32, 6), - ('int_sel', c_uint32, 3), - ('reserved9', ctypes.c_uint32, 2), - ('data_sel', c_uint32, 3), -] - -union_pm4_mec_release_mem_2._pack_ = 1 # source:False -union_pm4_mec_release_mem_2._fields_ = [ - ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_3(Union): - pass - -class struct_pm4_mec_release_mem_3_bitfields4(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ - ('reserved10', ctypes.c_uint32, 2), - ('address_lo_32b', ctypes.c_uint32, 30), -] - -class struct_pm4_mec_release_mem_3_bitfields4b(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ - ('reserved11', ctypes.c_uint32, 3), - ('address_lo_64b', ctypes.c_uint32, 29), -] - -union_pm4_mec_release_mem_3._pack_ = 1 # source:False -union_pm4_mec_release_mem_3._fields_ = [ - ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), - ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), - ('reserved12', ctypes.c_uint32), - ('ordinal4', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_4(Union): - pass - -union_pm4_mec_release_mem_4._pack_ = 1 # source:False -union_pm4_mec_release_mem_4._fields_ = [ - ('address_hi', ctypes.c_uint32), - ('reserved13', ctypes.c_uint32), - ('ordinal5', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_5(Union): - pass - -class struct_pm4_mec_release_mem_5_bitfields6c(Structure): - pass - -struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False -struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ - ('dw_offset', ctypes.c_uint32, 16), - ('num_dwords', ctypes.c_uint32, 16), -] - -union_pm4_mec_release_mem_5._pack_ = 1 # source:False -union_pm4_mec_release_mem_5._fields_ = [ - ('data_lo', ctypes.c_uint32), - ('cmp_data_lo', ctypes.c_uint32), - ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), - ('reserved14', ctypes.c_uint32), - ('ordinal6', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_6(Union): - pass - -union_pm4_mec_release_mem_6._pack_ = 1 # source:False -union_pm4_mec_release_mem_6._fields_ = [ - ('data_hi', ctypes.c_uint32), - ('cmp_data_hi', ctypes.c_uint32), - ('reserved15', ctypes.c_uint32), - ('reserved16', ctypes.c_uint32), - ('ordinal7', ctypes.c_uint32), -] - -struct_pm4_mec_release_mem._pack_ = 1 # source:False -struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) -struct_pm4_mec_release_mem._fields_ = [ - ('_0', union_pm4_mec_release_mem_0), - ('_1', union_pm4_mec_release_mem_1), - ('_2', union_pm4_mec_release_mem_2), - ('_3', union_pm4_mec_release_mem_3), - ('_4', union_pm4_mec_release_mem_4), - ('_5', union_pm4_mec_release_mem_5), - ('_6', union_pm4_mec_release_mem_6), - ('int_ctxid', ctypes.c_uint32), -] - - -# values for enumeration 'WRITE_DATA_dst_sel_enum' -WRITE_DATA_dst_sel_enum__enumvalues = { - 0: 'dst_sel___write_data__mem_mapped_register', - 2: 'dst_sel___write_data__tc_l2', - 3: 'dst_sel___write_data__gds', - 5: 'dst_sel___write_data__memory', - 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', -} -dst_sel___write_data__mem_mapped_register = 0 -dst_sel___write_data__tc_l2 = 2 -dst_sel___write_data__gds = 3 -dst_sel___write_data__memory = 5 -dst_sel___write_data__memory_mapped_adc_persistent_state = 6 -WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_addr_incr_enum' -WRITE_DATA_addr_incr_enum__enumvalues = { - 0: 'addr_incr___write_data__increment_address', - 1: 'addr_incr___write_data__do_not_increment_address', -} -addr_incr___write_data__increment_address = 0 -addr_incr___write_data__do_not_increment_address = 1 -WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_wr_confirm_enum' -WRITE_DATA_wr_confirm_enum__enumvalues = { - 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 1: 'wr_confirm___write_data__wait_for_write_confirmation', -} -wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 -wr_confirm___write_data__wait_for_write_confirmation = 1 -WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_cache_policy_enum' -WRITE_DATA_cache_policy_enum__enumvalues = { - 0: 'cache_policy___write_data__lru', - 1: 'cache_policy___write_data__stream', -} -cache_policy___write_data__lru = 0 -cache_policy___write_data__stream = 1 -WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum -class struct_pm4_mec_write_data_mmio(Structure): - pass - -class union_pm4_mec_write_data_mmio_0(Union): - pass - -union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_1(Union): - pass - -class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): - pass - -struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('dst_sel', ctypes.c_uint32, 4), - ('reserved2', ctypes.c_uint32, 4), - ('addr_incr', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 2), - ('resume_vf', ctypes.c_uint32, 1), - ('wr_confirm', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 4), - ('cache_policy', ctypes.c_uint32, 2), - ('reserved5', ctypes.c_uint32, 5), -] - -union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_1._fields_ = [ - ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_2(Union): - pass - -class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): - pass - -struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ - ('dst_mmreg_addr', ctypes.c_uint32, 18), - ('reserved6', ctypes.c_uint32, 14), -] - -union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_2._fields_ = [ - ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) -struct_pm4_mec_write_data_mmio._fields_ = [ - ('_0', union_pm4_mec_write_data_mmio_0), - ('_1', union_pm4_mec_write_data_mmio_1), - ('_2', union_pm4_mec_write_data_mmio_2), - ('reserved7', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', -} -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum -NVD_H = True # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_INDIRECT_BUFFER_END = 0x17 # macro -PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro -PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro -PACKET3_COPY_DW = 0x3B # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_CP_DMA = 0x41 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_SURFACE_SYNC = 0x43 # macro -PACKET3_ME_INITIALIZE = 0x44 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_EVENT_WRITE_EOP = 0x47 # macro -PACKET3_EVENT_WRITE_EOS = 0x48 # macro -PACKET3_RELEASE_MEM = 0x49 # macro -def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro - return ((x)<<0) -def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro -PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro -PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro -PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro -PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro -PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro -PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro -PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro -PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro -PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro -def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro - return ((x)<<25) -PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro -def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro - return ((x)<<29) -def PACKET3_RELEASE_MEM_INT_SEL(x): # macro - return ((x)<<24) -def PACKET3_RELEASE_MEM_DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_CONTEXT_REG_RMW = 0x51 # macro -PACKET3_GFX_CNTX_UPDATE = 0x52 # macro -PACKET3_BLK_CNTX_UPDATE = 0x53 # macro -PACKET3_INCR_UPDT_STATE = 0x55 # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro - return ((x)<<0) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro - return ((x)<<2) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro - return ((x)<<6) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro - return ((x)<<7) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro - return ((x)<<8) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro - return ((x)<<9) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro - return ((x)<<10) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro - return ((x)<<11) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro - return ((x)<<13) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro - return ((x)<<14) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro - return ((x)<<16) -PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro -PACKET3_REWIND = 0x59 # macro -PACKET3_INTERRUPT = 0x5A # macro -PACKET3_GEN_PDEPTE = 0x5B # macro -PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro -PACKET3_PRIME_UTCL2 = 0x5D # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro -PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro -PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro -PACKET3_SET_SH_REG_DI = 0x72 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro -PACKET3_GFX_PIPE_LOCK = 0x75 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro -PACKET3_FORWARD_HEADER = 0x7C # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro -PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro -PACKET3_DISPATCH_DRAW = 0x8D # macro -PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro -PACKET3_GET_LOD_STATS = 0x8E # macro -PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro -PACKET3_WAIT_REG_MEM64 = 0x93 # macro -PACKET3_COND_PREEMPT = 0x94 # macro -PACKET3_HDP_FLUSH = 0x95 # macro -PACKET3_COPY_DATA_RB = 0x96 # macro -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -PACKET3_AQL_PACKET = 0x99 # macro -PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro -PACKET3_SET_SH_REG_INDEX = 0x9B # macro -PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro -PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro -PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro -PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_PROCESS = 0xA1 # macro -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_LIST = 0xA5 # macro -PACKET3_MAP_PROCESS_VM = 0xA6 # macro -PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro -def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro - return ((x)<<0) -PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro -__all__ = \ - ['CACHE_FLUSH_AND_INV_TS_EVENT', 'CE_PARTITION_BASE', - 'CP_PACKET2', 'F32_MES_PM4_PACKETS_H', 'FRAME_TMZ', - 'INDIRECT_BUFFER_VALID', 'NVD_H', 'PACKET2_PAD_MASK', - 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', - 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', 'PACKET3_AQL_PACKET', - 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', - 'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE', - 'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER', - 'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA', - 'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA', - 'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW', - 'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE', - 'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT', - 'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC', - 'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT', - 'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS', - 'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST', - 'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT', - 'PACKET3_DRAW_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE', - 'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS', - 'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL', - 'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS', - 'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK', - 'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER', - 'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE', - 'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE', - 'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE', - 'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST', - 'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END', - 'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV', - 'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG', - 'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG', - 'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG', - 'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM', - 'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE', - 'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', - 'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE', - 'PACKET3_RELEASE_MEM_GCR_GL1_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD', - 'PACKET3_RELEASE_MEM_GCR_GL2_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_RANGE', - 'PACKET3_RELEASE_MEM_GCR_GL2_US', - 'PACKET3_RELEASE_MEM_GCR_GL2_WB', - 'PACKET3_RELEASE_MEM_GCR_GLM_INV', - 'PACKET3_RELEASE_MEM_GCR_GLM_WB', - 'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ', - 'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ', - 'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL', - 'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT', - 'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE', - 'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END', - 'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG', - 'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE', - 'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM', - 'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG', - 'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI', - 'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START', - 'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER', - 'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER', - 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM', - 'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1', - 'PACKET_TYPE2', 'PACKET_TYPE3', 'PM4_MEC_RELEASE_MEM_DEFINED', - 'PM4_MEC_WRITE_DATA_DEFINED', 'PM4_MES_HEADER_DEFINED', - 'WRITE_DATA_addr_incr_enum', 'WRITE_DATA_cache_policy_enum', - 'WRITE_DATA_dst_sel_enum', 'WRITE_DATA_wr_confirm_enum', - 'WR_CONFIRM', 'WR_ONE_ADDR', - 'addr_incr___write_data__do_not_increment_address', - 'addr_incr___write_data__increment_address', - 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', - 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', - 'cache_policy___write_data__lru', - 'cache_policy___write_data__stream', - 'cache_policy__mec_release_mem__lru', - 'cache_policy__mec_release_mem__stream', - 'data_sel__mec_release_mem__none', - 'data_sel__mec_release_mem__send_32_bit_low', - 'data_sel__mec_release_mem__send_64_bit_data', - 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 'data_sel__mec_release_mem__send_gpu_clock_counter', - 'data_sel__mec_release_mem__store_gds_data_to_memory', - 'dst_sel___write_data__gds', - 'dst_sel___write_data__mem_mapped_register', - 'dst_sel___write_data__memory', - 'dst_sel___write_data__memory_mapped_adc_persistent_state', - 'dst_sel___write_data__tc_l2', - 'dst_sel__mec_release_mem__memory_controller', - 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', - 'dst_sel__mec_release_mem__queue_write_pointer_register', - 'dst_sel__mec_release_mem__tc_l2', - 'event_index__mec_release_mem__end_of_pipe', - 'event_index__mec_release_mem__shader_done', 'int32_t', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', - 'int_sel__mec_release_mem__none', - 'int_sel__mec_release_mem__send_data_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_only', - 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 'pq_exe_status__mec_release_mem__default', - 'pq_exe_status__mec_release_mem__phase_update', - 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_pm4_mec_release_mem', - 'struct_pm4_mec_release_mem_1_bitfields2', - 'struct_pm4_mec_release_mem_2_bitfields3', - 'struct_pm4_mec_release_mem_3_bitfields4', - 'struct_pm4_mec_release_mem_3_bitfields4b', - 'struct_pm4_mec_release_mem_5_bitfields6c', - 'struct_pm4_mec_write_data_mmio', - 'struct_pm4_mec_write_data_mmio_1_bitfields2', - 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', - 'union_PM4_MES_TYPE_3_HEADER', 'union_pm4_mec_release_mem_0', - 'union_pm4_mec_release_mem_1', 'union_pm4_mec_release_mem_2', - 'union_pm4_mec_release_mem_3', 'union_pm4_mec_release_mem_4', - 'union_pm4_mec_release_mem_5', 'union_pm4_mec_release_mem_6', - 'union_pm4_mec_write_data_mmio_0', - 'union_pm4_mec_write_data_mmio_1', - 'union_pm4_mec_write_data_mmio_2', - 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 'wr_confirm___write_data__wait_for_write_confirmation'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/pm4_soc15.py b/tinygrad/tinygrad/runtime/autogen/am/pm4_soc15.py deleted file mode 100644 index 16e9ee3d..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/pm4_soc15.py +++ /dev/null @@ -1,931 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -F32_MES_PM4_PACKETS_H = True # macro -uint32_t = True # macro -int32_t = True # macro -PM4_MES_HEADER_DEFINED = True # macro -PM4_MEC_RELEASE_MEM_DEFINED = True # macro -PM4_MEC_WRITE_DATA_DEFINED = True # macro -class union_PM4_MES_TYPE_3_HEADER(Union): - pass - -class struct_PM4_MES_TYPE_3_HEADER_0(Structure): - pass - -struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False -struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('opcode', ctypes.c_uint32, 8), - ('count', ctypes.c_uint32, 14), - ('type', ctypes.c_uint32, 2), -] - -union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False -union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) -union_PM4_MES_TYPE_3_HEADER._fields_ = [ - ('_0', struct_PM4_MES_TYPE_3_HEADER_0), - ('u32All', ctypes.c_uint32), -] - - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 5: 'event_index__mec_release_mem__end_of_pipe', - 6: 'event_index__mec_release_mem__shader_done', -} -event_index__mec_release_mem__end_of_pipe = 5 -event_index__mec_release_mem__shader_done = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'cache_policy__mec_release_mem__lru', - 1: 'cache_policy__mec_release_mem__stream', -} -cache_policy__mec_release_mem__lru = 0 -cache_policy__mec_release_mem__stream = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'pq_exe_status__mec_release_mem__default', - 1: 'pq_exe_status__mec_release_mem__phase_update', -} -pq_exe_status__mec_release_mem__default = 0 -pq_exe_status__mec_release_mem__phase_update = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'dst_sel__mec_release_mem__memory_controller', - 1: 'dst_sel__mec_release_mem__tc_l2', - 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', - 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', -} -dst_sel__mec_release_mem__memory_controller = 0 -dst_sel__mec_release_mem__tc_l2 = 1 -dst_sel__mec_release_mem__queue_write_pointer_register = 2 -dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'int_sel__mec_release_mem__none', - 1: 'int_sel__mec_release_mem__send_interrupt_only', - 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', - 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', -} -int_sel__mec_release_mem__none = 0 -int_sel__mec_release_mem__send_interrupt_only = 1 -int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 -int_sel__mec_release_mem__send_data_after_write_confirm = 3 -int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'data_sel__mec_release_mem__none', - 1: 'data_sel__mec_release_mem__send_32_bit_low', - 2: 'data_sel__mec_release_mem__send_64_bit_data', - 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', - 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', -} -data_sel__mec_release_mem__none = 0 -data_sel__mec_release_mem__send_32_bit_low = 1 -data_sel__mec_release_mem__send_64_bit_data = 2 -data_sel__mec_release_mem__send_gpu_clock_counter = 3 -data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 -data_sel__mec_release_mem__store_gds_data_to_memory = 5 -c_uint32 = ctypes.c_uint32 # enum -class struct_pm4_mec_release_mem(Structure): - pass - -class union_pm4_mec_release_mem_0(Union): - pass - -union_pm4_mec_release_mem_0._pack_ = 1 # source:False -union_pm4_mec_release_mem_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_1(Union): - pass - -class struct_pm4_mec_release_mem_1_bitfields2(Structure): - pass - -struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ - ('event_type', ctypes.c_uint32, 6), - ('reserved1', ctypes.c_uint32, 2), - ('event_index', c_uint32, 4), - ('tcl1_vol_action_ena', ctypes.c_uint32, 1), - ('tc_vol_action_ena', ctypes.c_uint32, 1), - ('reserved2', ctypes.c_uint32, 1), - ('tc_wb_action_ena', ctypes.c_uint32, 1), - ('tcl1_action_ena', ctypes.c_uint32, 1), - ('tc_action_ena', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 1), - ('tc_nc_action_ena', ctypes.c_uint32, 1), - ('tc_wc_action_ena', ctypes.c_uint32, 1), - ('tc_md_action_ena', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 3), - ('cache_policy', c_uint32, 2), - ('reserved5', ctypes.c_uint32, 2), - ('pq_exe_status', c_uint32, 1), - ('reserved6', ctypes.c_uint32, 2), -] - -union_pm4_mec_release_mem_1._pack_ = 1 # source:False -union_pm4_mec_release_mem_1._fields_ = [ - ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_2(Union): - pass - -class struct_pm4_mec_release_mem_2_bitfields3(Structure): - pass - -struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ - ('reserved7', ctypes.c_uint32, 16), - ('dst_sel', c_uint32, 2), - ('reserved8', ctypes.c_uint32, 6), - ('int_sel', c_uint32, 3), - ('reserved9', ctypes.c_uint32, 2), - ('data_sel', c_uint32, 3), -] - -union_pm4_mec_release_mem_2._pack_ = 1 # source:False -union_pm4_mec_release_mem_2._fields_ = [ - ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_3(Union): - pass - -class struct_pm4_mec_release_mem_3_bitfields4(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ - ('reserved10', ctypes.c_uint32, 2), - ('address_lo_32b', ctypes.c_uint32, 30), -] - -class struct_pm4_mec_release_mem_3_bitfields4b(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ - ('reserved11', ctypes.c_uint32, 3), - ('address_lo_64b', ctypes.c_uint32, 29), -] - -union_pm4_mec_release_mem_3._pack_ = 1 # source:False -union_pm4_mec_release_mem_3._fields_ = [ - ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), - ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), - ('reserved12', ctypes.c_uint32), - ('ordinal4', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_4(Union): - pass - -union_pm4_mec_release_mem_4._pack_ = 1 # source:False -union_pm4_mec_release_mem_4._fields_ = [ - ('address_hi', ctypes.c_uint32), - ('reserved13', ctypes.c_uint32), - ('ordinal5', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_5(Union): - pass - -class struct_pm4_mec_release_mem_5_bitfields6c(Structure): - pass - -struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False -struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ - ('dw_offset', ctypes.c_uint32, 16), - ('num_dwords', ctypes.c_uint32, 16), -] - -union_pm4_mec_release_mem_5._pack_ = 1 # source:False -union_pm4_mec_release_mem_5._fields_ = [ - ('data_lo', ctypes.c_uint32), - ('cmp_data_lo', ctypes.c_uint32), - ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), - ('reserved14', ctypes.c_uint32), - ('ordinal6', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_6(Union): - pass - -union_pm4_mec_release_mem_6._pack_ = 1 # source:False -union_pm4_mec_release_mem_6._fields_ = [ - ('data_hi', ctypes.c_uint32), - ('cmp_data_hi', ctypes.c_uint32), - ('reserved15', ctypes.c_uint32), - ('reserved16', ctypes.c_uint32), - ('ordinal7', ctypes.c_uint32), -] - -struct_pm4_mec_release_mem._pack_ = 1 # source:False -struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) -struct_pm4_mec_release_mem._fields_ = [ - ('_0', union_pm4_mec_release_mem_0), - ('_1', union_pm4_mec_release_mem_1), - ('_2', union_pm4_mec_release_mem_2), - ('_3', union_pm4_mec_release_mem_3), - ('_4', union_pm4_mec_release_mem_4), - ('_5', union_pm4_mec_release_mem_5), - ('_6', union_pm4_mec_release_mem_6), - ('int_ctxid', ctypes.c_uint32), -] - - -# values for enumeration 'WRITE_DATA_dst_sel_enum' -WRITE_DATA_dst_sel_enum__enumvalues = { - 0: 'dst_sel___write_data__mem_mapped_register', - 2: 'dst_sel___write_data__tc_l2', - 3: 'dst_sel___write_data__gds', - 5: 'dst_sel___write_data__memory', - 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', -} -dst_sel___write_data__mem_mapped_register = 0 -dst_sel___write_data__tc_l2 = 2 -dst_sel___write_data__gds = 3 -dst_sel___write_data__memory = 5 -dst_sel___write_data__memory_mapped_adc_persistent_state = 6 -WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_addr_incr_enum' -WRITE_DATA_addr_incr_enum__enumvalues = { - 0: 'addr_incr___write_data__increment_address', - 1: 'addr_incr___write_data__do_not_increment_address', -} -addr_incr___write_data__increment_address = 0 -addr_incr___write_data__do_not_increment_address = 1 -WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_wr_confirm_enum' -WRITE_DATA_wr_confirm_enum__enumvalues = { - 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 1: 'wr_confirm___write_data__wait_for_write_confirmation', -} -wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 -wr_confirm___write_data__wait_for_write_confirmation = 1 -WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_cache_policy_enum' -WRITE_DATA_cache_policy_enum__enumvalues = { - 0: 'cache_policy___write_data__lru', - 1: 'cache_policy___write_data__stream', -} -cache_policy___write_data__lru = 0 -cache_policy___write_data__stream = 1 -WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum -class struct_pm4_mec_write_data_mmio(Structure): - pass - -class union_pm4_mec_write_data_mmio_0(Union): - pass - -union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_1(Union): - pass - -class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): - pass - -struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('dst_sel', ctypes.c_uint32, 4), - ('reserved2', ctypes.c_uint32, 4), - ('addr_incr', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 2), - ('resume_vf', ctypes.c_uint32, 1), - ('wr_confirm', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 4), - ('cache_policy', ctypes.c_uint32, 2), - ('reserved5', ctypes.c_uint32, 5), -] - -union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_1._fields_ = [ - ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_2(Union): - pass - -class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): - pass - -struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ - ('dst_mmreg_addr', ctypes.c_uint32, 18), - ('reserved6', ctypes.c_uint32, 14), -] - -union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_2._fields_ = [ - ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) -struct_pm4_mec_write_data_mmio._fields_ = [ - ('_0', union_pm4_mec_write_data_mmio_0), - ('_1', union_pm4_mec_write_data_mmio_1), - ('_2', union_pm4_mec_write_data_mmio_2), - ('reserved7', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', -} -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum -SOC15_H = True # macro -GFX9_NUM_GFX_RINGS = 1 # macro -GFX9_NUM_COMPUTE_RINGS = 8 # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKETJ_CONDITION_CHECK0 = 0 # macro -PACKETJ_CONDITION_CHECK1 = 1 # macro -PACKETJ_CONDITION_CHECK2 = 2 # macro -PACKETJ_CONDITION_CHECK3 = 3 # macro -PACKETJ_CONDITION_CHECK4 = 4 # macro -PACKETJ_CONDITION_CHECK5 = 5 # macro -PACKETJ_CONDITION_CHECK6 = 6 # macro -PACKETJ_CONDITION_CHECK7 = 7 # macro -PACKETJ_TYPE0 = 0 # macro -PACKETJ_TYPE1 = 1 # macro -PACKETJ_TYPE2 = 2 # macro -PACKETJ_TYPE3 = 3 # macro -PACKETJ_TYPE4 = 4 # macro -PACKETJ_TYPE5 = 5 # macro -PACKETJ_TYPE6 = 6 # macro -PACKETJ_TYPE7 = 7 # macro -def PACKETJ(reg, r, cond, type): # macro - return ((reg&0x3FFFF)|((r&0x3F)<<18)|((cond&0xF)<<24)|((type&0xF)<<28)) -CP_PACKETJ_NOP = 0x60000000 # macro -def CP_PACKETJ_GET_REG(x): # macro - return ((x)&0x3FFFF) -def CP_PACKETJ_GET_RES(x): # macro - return (((x)>>18)&0x3F) -def CP_PACKETJ_GET_COND(x): # macro - return (((x)>>24)&0xF) -def CP_PACKETJ_GET_TYPE(x): # macro - return (((x)>>28)&0xF) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_CONST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM = 0x49 # macro -EOP_TCL1_VOL_ACTION_EN = (1<<12) # macro -EOP_TC_VOL_ACTION_EN = (1<<13) # macro -EOP_TC_WB_ACTION_EN = (1<<15) # macro -EOP_TCL1_ACTION_EN = (1<<16) # macro -EOP_TC_ACTION_EN = (1<<17) # macro -EOP_TC_NC_ACTION_EN = (1<<19) # macro -EOP_TC_MD_ACTION_EN = (1<<21) # macro -EOP_EXEC = (1<<28) # macro -def DATA_SEL(x): # macro - return ((x)<<29) -def INT_SEL(x): # macro - return ((x)<<24) -def DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x): # macro - return ((x)<<3) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x): # macro - return ((x)<<18) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x): # macro - return ((x)<<22) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x): # macro - return ((x)<<23) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x): # macro - return ((x)<<25) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x): # macro - return ((x)<<26) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x): # macro - return ((x)<<27) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x): # macro - return ((x)<<28) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x): # macro - return ((x)<<29) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x): # macro - return ((x)<<30) -PACKET3_REWIND = 0x59 # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX_TYPE = (2<<28) # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -def PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x): # macro - return ((x)<<29) -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_CLEANER_SHADER = 0xD2 # macro -VCE_CMD_NO_OP = 0x00000000 # macro -VCE_CMD_END = 0x00000001 # macro -VCE_CMD_IB = 0x00000002 # macro -VCE_CMD_FENCE = 0x00000003 # macro -VCE_CMD_TRAP = 0x00000004 # macro -VCE_CMD_IB_AUTO = 0x00000005 # macro -VCE_CMD_SEMAPHORE = 0x00000006 # macro -VCE_CMD_IB_VM = 0x00000102 # macro -VCE_CMD_WAIT_GE = 0x00000106 # macro -VCE_CMD_UPDATE_PTB = 0x00000107 # macro -VCE_CMD_FLUSH_TLB = 0x00000108 # macro -VCE_CMD_REG_WRITE = 0x00000109 # macro -VCE_CMD_REG_WAIT = 0x0000010a # macro -HEVC_ENC_CMD_NO_OP = 0x00000000 # macro -HEVC_ENC_CMD_END = 0x00000001 # macro -HEVC_ENC_CMD_FENCE = 0x00000003 # macro -HEVC_ENC_CMD_TRAP = 0x00000004 # macro -HEVC_ENC_CMD_IB_VM = 0x00000102 # macro -HEVC_ENC_CMD_REG_WRITE = 0x00000109 # macro -HEVC_ENC_CMD_REG_WAIT = 0x0000010a # macro -__all__ = \ - ['CACHE_FLUSH_AND_INV_TS_EVENT', 'CE_PARTITION_BASE', - 'CP_PACKET2', 'CP_PACKETJ_NOP', 'EOP_EXEC', 'EOP_TCL1_ACTION_EN', - 'EOP_TCL1_VOL_ACTION_EN', 'EOP_TC_ACTION_EN', - 'EOP_TC_MD_ACTION_EN', 'EOP_TC_NC_ACTION_EN', - 'EOP_TC_VOL_ACTION_EN', 'EOP_TC_WB_ACTION_EN', - 'F32_MES_PM4_PACKETS_H', 'FRAME_TMZ', 'GFX9_NUM_COMPUTE_RINGS', - 'GFX9_NUM_GFX_RINGS', 'HEVC_ENC_CMD_END', 'HEVC_ENC_CMD_FENCE', - 'HEVC_ENC_CMD_IB_VM', 'HEVC_ENC_CMD_NO_OP', - 'HEVC_ENC_CMD_REG_WAIT', 'HEVC_ENC_CMD_REG_WRITE', - 'HEVC_ENC_CMD_TRAP', 'INDIRECT_BUFFER_VALID', 'PACKET2_PAD_MASK', - 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', 'PACKET3_ATOMIC_GDS', - 'PACKET3_ATOMIC_MEM', 'PACKET3_CLEAR_STATE', 'PACKET3_COND_EXEC', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_COPY_DATA', 'PACKET3_DISPATCH_DIRECT', - 'PACKET3_DISPATCH_INDIRECT', 'PACKET3_DMA_DATA', - 'PACKET3_DMA_DATA_CMD_DAIC', 'PACKET3_DMA_DATA_CMD_DAS', - 'PACKET3_DMA_DATA_CMD_RAW_WAIT', 'PACKET3_DMA_DATA_CMD_SAIC', - 'PACKET3_DMA_DATA_CMD_SAS', 'PACKET3_DMA_DATA_CP_SYNC', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_OFFSET_2', - 'PACKET3_DRAW_INDIRECT', 'PACKET3_DRAW_INDIRECT_MULTI', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_EVENT_WRITE', 'PACKET3_FRAME_CONTROL', - 'PACKET3_INCREMENT_CE_COUNTER', 'PACKET3_INCREMENT_DE_COUNTER', - 'PACKET3_INDEX_BASE', 'PACKET3_INDEX_BUFFER_SIZE', - 'PACKET3_INDEX_TYPE', 'PACKET3_INDIRECT_BUFFER', - 'PACKET3_INDIRECT_BUFFER_CONST', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_CONFIG_REG', 'PACKET3_LOAD_CONST_RAM', - 'PACKET3_LOAD_CONTEXT_REG', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_UCONFIG_REG', 'PACKET3_MAP_QUEUES', - 'PACKET3_MEM_SEMAPHORE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', 'PACKET3_RELEASE_MEM', - 'PACKET3_REWIND', 'PACKET3_RUN_CLEANER_SHADER', - 'PACKET3_SCRATCH_RAM_READ', 'PACKET3_SCRATCH_RAM_WRITE', - 'PACKET3_SEM_SEL_SIGNAL', 'PACKET3_SEM_SEL_SIGNAL_TYPE', - 'PACKET3_SEM_SEL_WAIT', 'PACKET3_SEM_USE_MAILBOX', - 'PACKET3_SET_BASE', 'PACKET3_SET_CONFIG_REG', - 'PACKET3_SET_CONFIG_REG_END', 'PACKET3_SET_CONFIG_REG_START', - 'PACKET3_SET_CONTEXT_REG', 'PACKET3_SET_CONTEXT_REG_END', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_RESOURCES', - 'PACKET3_SET_SH_REG', 'PACKET3_SET_SH_REG_END', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX_TYPE', - 'PACKET3_SET_UCONFIG_REG_START', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SWITCH_BUFFER', 'PACKET3_UNMAP_QUEUES', - 'PACKET3_WAIT_ON_CE_COUNTER', 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', - 'PACKET3_WAIT_REG_MEM', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKETJ_CONDITION_CHECK0', - 'PACKETJ_CONDITION_CHECK1', 'PACKETJ_CONDITION_CHECK2', - 'PACKETJ_CONDITION_CHECK3', 'PACKETJ_CONDITION_CHECK4', - 'PACKETJ_CONDITION_CHECK5', 'PACKETJ_CONDITION_CHECK6', - 'PACKETJ_CONDITION_CHECK7', 'PACKETJ_TYPE0', 'PACKETJ_TYPE1', - 'PACKETJ_TYPE2', 'PACKETJ_TYPE3', 'PACKETJ_TYPE4', - 'PACKETJ_TYPE5', 'PACKETJ_TYPE6', 'PACKETJ_TYPE7', 'PACKET_TYPE0', - 'PACKET_TYPE1', 'PACKET_TYPE2', 'PACKET_TYPE3', - 'PM4_MEC_RELEASE_MEM_DEFINED', 'PM4_MEC_WRITE_DATA_DEFINED', - 'PM4_MES_HEADER_DEFINED', 'SOC15_H', 'VCE_CMD_END', - 'VCE_CMD_FENCE', 'VCE_CMD_FLUSH_TLB', 'VCE_CMD_IB', - 'VCE_CMD_IB_AUTO', 'VCE_CMD_IB_VM', 'VCE_CMD_NO_OP', - 'VCE_CMD_REG_WAIT', 'VCE_CMD_REG_WRITE', 'VCE_CMD_SEMAPHORE', - 'VCE_CMD_TRAP', 'VCE_CMD_UPDATE_PTB', 'VCE_CMD_WAIT_GE', - 'WRITE_DATA_addr_incr_enum', 'WRITE_DATA_cache_policy_enum', - 'WRITE_DATA_dst_sel_enum', 'WRITE_DATA_wr_confirm_enum', - 'WR_CONFIRM', 'WR_ONE_ADDR', - 'addr_incr___write_data__do_not_increment_address', - 'addr_incr___write_data__increment_address', - 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', - 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', - 'cache_policy___write_data__lru', - 'cache_policy___write_data__stream', - 'cache_policy__mec_release_mem__lru', - 'cache_policy__mec_release_mem__stream', - 'data_sel__mec_release_mem__none', - 'data_sel__mec_release_mem__send_32_bit_low', - 'data_sel__mec_release_mem__send_64_bit_data', - 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 'data_sel__mec_release_mem__send_gpu_clock_counter', - 'data_sel__mec_release_mem__store_gds_data_to_memory', - 'dst_sel___write_data__gds', - 'dst_sel___write_data__mem_mapped_register', - 'dst_sel___write_data__memory', - 'dst_sel___write_data__memory_mapped_adc_persistent_state', - 'dst_sel___write_data__tc_l2', - 'dst_sel__mec_release_mem__memory_controller', - 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', - 'dst_sel__mec_release_mem__queue_write_pointer_register', - 'dst_sel__mec_release_mem__tc_l2', - 'event_index__mec_release_mem__end_of_pipe', - 'event_index__mec_release_mem__shader_done', 'int32_t', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', - 'int_sel__mec_release_mem__none', - 'int_sel__mec_release_mem__send_data_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_only', - 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 'pq_exe_status__mec_release_mem__default', - 'pq_exe_status__mec_release_mem__phase_update', - 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_pm4_mec_release_mem', - 'struct_pm4_mec_release_mem_1_bitfields2', - 'struct_pm4_mec_release_mem_2_bitfields3', - 'struct_pm4_mec_release_mem_3_bitfields4', - 'struct_pm4_mec_release_mem_3_bitfields4b', - 'struct_pm4_mec_release_mem_5_bitfields6c', - 'struct_pm4_mec_write_data_mmio', - 'struct_pm4_mec_write_data_mmio_1_bitfields2', - 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', - 'union_PM4_MES_TYPE_3_HEADER', 'union_pm4_mec_release_mem_0', - 'union_pm4_mec_release_mem_1', 'union_pm4_mec_release_mem_2', - 'union_pm4_mec_release_mem_3', 'union_pm4_mec_release_mem_4', - 'union_pm4_mec_release_mem_5', 'union_pm4_mec_release_mem_6', - 'union_pm4_mec_write_data_mmio_0', - 'union_pm4_mec_write_data_mmio_1', - 'union_pm4_mec_write_data_mmio_2', - 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 'wr_confirm___write_data__wait_for_write_confirmation'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/sdma_4_0_0.py b/tinygrad/tinygrad/runtime/autogen/am/sdma_4_0_0.py deleted file mode 100644 index a48adeed..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/sdma_4_0_0.py +++ /dev/null @@ -1,5209 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__VEGA10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_DUMMY_TRAP = 16 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', - 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', - 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', - 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/sdma_4_4_2.py b/tinygrad/tinygrad/runtime/autogen/am/sdma_4_4_2.py deleted file mode 100644 index a48adeed..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/sdma_4_4_2.py +++ /dev/null @@ -1,5209 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__VEGA10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_DUMMY_TRAP = 16 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', - 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', - 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', - 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/sdma_5_0_0.py b/tinygrad/tinygrad/runtime/autogen/am/sdma_5_0_0.py deleted file mode 100644 index 1eb64252..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/sdma_5_0_0.py +++ /dev/null @@ -1,7103 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__NAVI10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_GPUVM_INV = 16 # macro -SDMA_OP_GCR_REQ = 17 # macro -SDMA_OP_DUMMY_TRAP = 32 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro -SDMA_SUBOP_COPY_TILED_BC = 17 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_WRITE_TILED_BC = 17 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -SDMA_SUBOP_VM_INVALIDATION = 4 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_GCR_RANGE_IS_PA = (1<<18) # macro -def SDMA_GCR_SEQ(x): # macro - return (((x)&0x3)<<16) -SDMA_GCR_GL2_WB = (1<<15) # macro -SDMA_GCR_GL2_INV = (1<<14) # macro -SDMA_GCR_GL2_DISCARD = (1<<13) # macro -def SDMA_GCR_GL2_RANGE(x): # macro - return (((x)&0x3)<<11) -SDMA_GCR_GL2_US = (1<<10) # macro -SDMA_GCR_GL1_INV = (1<<9) # macro -SDMA_GCR_GLV_INV = (1<<8) # macro -SDMA_GCR_GLK_INV = (1<<7) # macro -SDMA_GCR_GLK_WB = (1<<6) # macro -SDMA_GCR_GLM_INV = (1<<5) # macro -SDMA_GCR_GLM_WB = (1<<4) # macro -def SDMA_GCR_GL1_RANGE(x): # macro - return (((x)&0x3)<<2) -def SDMA_GCR_GLI_INV(x): # macro - return (((x)&0x3)<<0) -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 22 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 30 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 22 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 30 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift = 20 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 11 # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro - return ((x&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro -SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro -def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_FENCE_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro -def SDMA_PKT_FENCE_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro -def SDMA_PKT_FENCE_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_FENCE_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro - return (((x)&0x0000001F)<<24) -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro - return (((x)&0x000001FF)<<23) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro - return (((x)&0x00000001)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro - return (((x)&0x7FFFFFFF)<<1) -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro - return (((x)&0x0000003F)<<0) -SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro -def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', - 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', - 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', - 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', - 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', - 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', - 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', - 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', - 'SDMA_PKT_FENCE_HEADER_gcc_mask', - 'SDMA_PKT_FENCE_HEADER_gcc_offset', - 'SDMA_PKT_FENCE_HEADER_gcc_shift', - 'SDMA_PKT_FENCE_HEADER_gpa_mask', - 'SDMA_PKT_FENCE_HEADER_gpa_offset', - 'SDMA_PKT_FENCE_HEADER_gpa_shift', - 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', - 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', - 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', - 'SDMA_PKT_FENCE_HEADER_mtype_mask', - 'SDMA_PKT_FENCE_HEADER_mtype_offset', - 'SDMA_PKT_FENCE_HEADER_mtype_shift', - 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_snp_mask', - 'SDMA_PKT_FENCE_HEADER_snp_offset', - 'SDMA_PKT_FENCE_HEADER_snp_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', - 'SDMA_PKT_FENCE_HEADER_sys_mask', - 'SDMA_PKT_FENCE_HEADER_sys_offset', - 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_GCR_REQ_HEADER_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_op_shift', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_priv_mask', - 'SDMA_PKT_INDIRECT_HEADER_priv_offset', - 'SDMA_PKT_INDIRECT_HEADER_priv_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', - 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_VM_INVALIDATION', - 'SDMA_SUBOP_WRITE_LINEAR', 'SDMA_SUBOP_WRITE_TILED', - 'SDMA_SUBOP_WRITE_TILED_BC', '__NAVI10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/sdma_6_0_0.py b/tinygrad/tinygrad/runtime/autogen/am/sdma_6_0_0.py deleted file mode 100644 index b8934de7..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/sdma_6_0_0.py +++ /dev/null @@ -1,8085 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__SDMA_V6_0_0_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_GPUVM_INV = 16 # macro -SDMA_OP_GCR_REQ = 17 # macro -SDMA_OP_DUMMY_TRAP = 32 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 # macro -SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro -SDMA_SUBOP_COPY_TILED_BC = 17 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_WRITE_TILED_BC = 17 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_MEM_INCR = 1 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -SDMA_SUBOP_VM_INVALIDATION = 4 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_GCR_RANGE_IS_PA = (1<<18) # macro -def SDMA_GCR_SEQ(x): # macro - return (((x)&0x3)<<16) -SDMA_GCR_GL2_WB = (1<<15) # macro -SDMA_GCR_GL2_INV = (1<<14) # macro -SDMA_GCR_GL2_DISCARD = (1<<13) # macro -def SDMA_GCR_GL2_RANGE(x): # macro - return (((x)&0x3)<<11) -SDMA_GCR_GL2_US = (1<<10) # macro -SDMA_GCR_GL1_INV = (1<<9) # macro -SDMA_GCR_GLV_INV = (1<<8) # macro -SDMA_GCR_GLK_INV = (1<<7) # macro -SDMA_GCR_GLK_WB = (1<<6) # macro -SDMA_GCR_GLM_INV = (1<<5) # macro -SDMA_GCR_GLM_WB = (1<<4) # macro -def SDMA_GCR_GL1_RANGE(x): # macro - return (((x)&0x3)<<2) -def SDMA_GCR_GLI_INV(x): # macro - return (((x)&0x3)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x): # macro - return (((x)&0x000000FF)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_T2T_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<22) -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro -SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro -def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_MEM_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_MEM_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro - return (((x)&0x0000001F)<<24) -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro - return (((x)&0x000001FF)<<23) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_FENCE_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro -def SDMA_PKT_FENCE_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro -def SDMA_PKT_FENCE_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_FENCE_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_FENCE_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_FENCE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_FENCE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COND_EXE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_ATOMIC_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro - return (((x)&0x00000001)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro - return (((x)&0x7FFFFFFF)<<1) -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro - return (((x)&0x0000003F)<<0) -SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro -def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_HEADER_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x): # macro - return (((x)&0x00000007)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x): # macro - return (((x)&0x00000007)<<5) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x): # macro - return (((x)&0x00000007)<<10) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x): # macro - return (((x)&0x00000007)<<15) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', - 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', - 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', - 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', - 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', - 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', - 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', - 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_mask', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_offset', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_shift', - 'SDMA_PKT_ATOMIC_HEADER_cpv_mask', - 'SDMA_PKT_ATOMIC_HEADER_cpv_offset', - 'SDMA_PKT_ATOMIC_HEADER_cpv_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_mask', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_offset', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_shift', - 'SDMA_PKT_COND_EXE_HEADER_cpv_mask', - 'SDMA_PKT_COND_EXE_HEADER_cpv_offset', - 'SDMA_PKT_COND_EXE_HEADER_cpv_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_mask', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_offset', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', - 'SDMA_PKT_FENCE_HEADER_cpv_mask', - 'SDMA_PKT_FENCE_HEADER_cpv_offset', - 'SDMA_PKT_FENCE_HEADER_cpv_shift', - 'SDMA_PKT_FENCE_HEADER_gcc_mask', - 'SDMA_PKT_FENCE_HEADER_gcc_offset', - 'SDMA_PKT_FENCE_HEADER_gcc_shift', - 'SDMA_PKT_FENCE_HEADER_gpa_mask', - 'SDMA_PKT_FENCE_HEADER_gpa_offset', - 'SDMA_PKT_FENCE_HEADER_gpa_shift', - 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', - 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', - 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', - 'SDMA_PKT_FENCE_HEADER_llc_policy_mask', - 'SDMA_PKT_FENCE_HEADER_llc_policy_offset', - 'SDMA_PKT_FENCE_HEADER_llc_policy_shift', - 'SDMA_PKT_FENCE_HEADER_mtype_mask', - 'SDMA_PKT_FENCE_HEADER_mtype_offset', - 'SDMA_PKT_FENCE_HEADER_mtype_shift', - 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_snp_mask', - 'SDMA_PKT_FENCE_HEADER_snp_offset', - 'SDMA_PKT_FENCE_HEADER_snp_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', - 'SDMA_PKT_FENCE_HEADER_sys_mask', - 'SDMA_PKT_FENCE_HEADER_sys_offset', - 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_GCR_REQ_HEADER_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_op_shift', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', - 'SDMA_PKT_HDP_FLUSH', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_priv_mask', - 'SDMA_PKT_INDIRECT_HEADER_priv_offset', - 'SDMA_PKT_INDIRECT_HEADER_priv_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_mask', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_offset', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_shift', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_op_shift', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_mask', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_offset', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_shift', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_mask', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_offset', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', - 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_MEM_INCR', 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', - 'SDMA_SUBOP_POLL_MEM_VERIFY', 'SDMA_SUBOP_POLL_REG_WRITE_MEM', - 'SDMA_SUBOP_PTEPDE_COPY', 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', - 'SDMA_SUBOP_PTEPDE_GEN', 'SDMA_SUBOP_PTEPDE_RMW', - 'SDMA_SUBOP_TIMESTAMP_GET', 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', - 'SDMA_SUBOP_TIMESTAMP_SET', 'SDMA_SUBOP_USER_GCR', - 'SDMA_SUBOP_VM_INVALIDATION', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', 'SDMA_SUBOP_WRITE_TILED_BC', - '__SDMA_V6_0_0_PKT_OPEN_H_', 'hdp_flush_cmd', - 'struct_SDMA_PKT_ATOMIC_TAG', 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/smu_v13_0_0.py b/tinygrad/tinygrad/runtime/autogen/am/smu_v13_0_0.py deleted file mode 100644 index b67f1ce7..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/smu_v13_0_0.py +++ /dev/null @@ -1,3068 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -SMU_V13_0_0_PPSMC_H = True # macro -PPSMC_VERSION = 0x1 # macro -DEBUGSMC_VERSION = 0x1 # macro -PPSMC_Result_OK = 0x1 # macro -PPSMC_Result_Failed = 0xFF # macro -PPSMC_Result_UnknownCmd = 0xFE # macro -PPSMC_Result_CmdRejectedPrereq = 0xFD # macro -PPSMC_Result_CmdRejectedBusy = 0xFC # macro -PPSMC_MSG_TestMessage = 0x1 # macro -PPSMC_MSG_GetSmuVersion = 0x2 # macro -PPSMC_MSG_GetDriverIfVersion = 0x3 # macro -PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 # macro -PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 # macro -PPSMC_MSG_EnableAllSmuFeatures = 0x6 # macro -PPSMC_MSG_DisableAllSmuFeatures = 0x7 # macro -PPSMC_MSG_EnableSmuFeaturesLow = 0x8 # macro -PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 # macro -PPSMC_MSG_DisableSmuFeaturesLow = 0xA # macro -PPSMC_MSG_DisableSmuFeaturesHigh = 0xB # macro -PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC # macro -PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD # macro -PPSMC_MSG_SetDriverDramAddrHigh = 0xE # macro -PPSMC_MSG_SetDriverDramAddrLow = 0xF # macro -PPSMC_MSG_SetToolsDramAddrHigh = 0x10 # macro -PPSMC_MSG_SetToolsDramAddrLow = 0x11 # macro -PPSMC_MSG_TransferTableSmu2Dram = 0x12 # macro -PPSMC_MSG_TransferTableDram2Smu = 0x13 # macro -PPSMC_MSG_UseDefaultPPTable = 0x14 # macro -PPSMC_MSG_EnterBaco = 0x15 # macro -PPSMC_MSG_ExitBaco = 0x16 # macro -PPSMC_MSG_ArmD3 = 0x17 # macro -PPSMC_MSG_BacoAudioD3PME = 0x18 # macro -PPSMC_MSG_SetSoftMinByFreq = 0x19 # macro -PPSMC_MSG_SetSoftMaxByFreq = 0x1A # macro -PPSMC_MSG_SetHardMinByFreq = 0x1B # macro -PPSMC_MSG_SetHardMaxByFreq = 0x1C # macro -PPSMC_MSG_GetMinDpmFreq = 0x1D # macro -PPSMC_MSG_GetMaxDpmFreq = 0x1E # macro -PPSMC_MSG_GetDpmFreqByIndex = 0x1F # macro -PPSMC_MSG_OverridePcieParameters = 0x20 # macro -PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 # macro -PPSMC_MSG_DramLogSetDramAddrLow = 0x22 # macro -PPSMC_MSG_DramLogSetDramSize = 0x23 # macro -PPSMC_MSG_SetWorkloadMask = 0x24 # macro -PPSMC_MSG_GetVoltageByDpm = 0x25 # macro -PPSMC_MSG_SetVideoFps = 0x26 # macro -PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 # macro -PPSMC_MSG_AllowGfxOff = 0x28 # macro -PPSMC_MSG_DisallowGfxOff = 0x29 # macro -PPSMC_MSG_PowerUpVcn = 0x2A # macro -PPSMC_MSG_PowerDownVcn = 0x2B # macro -PPSMC_MSG_PowerUpJpeg = 0x2C # macro -PPSMC_MSG_PowerDownJpeg = 0x2D # macro -PPSMC_MSG_PrepareMp1ForUnload = 0x2E # macro -PPSMC_MSG_Mode1Reset = 0x2F # macro -PPSMC_MSG_Mode2Reset = 0x4F # macro -PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 # macro -PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 # macro -PPSMC_MSG_SetPptLimit = 0x32 # macro -PPSMC_MSG_GetPptLimit = 0x33 # macro -PPSMC_MSG_ReenableAcDcInterrupt = 0x34 # macro -PPSMC_MSG_NotifyPowerSource = 0x35 # macro -PPSMC_MSG_RunDcBtc = 0x36 # macro -PPSMC_MSG_GetDebugData = 0x37 # macro -PPSMC_MSG_SetTemperatureInputSelect = 0x38 # macro -PPSMC_MSG_SetFwDstatesMask = 0x39 # macro -PPSMC_MSG_SetThrottlerMask = 0x3A # macro -PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B # macro -PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C # macro -PPSMC_MSG_DumpSTBtoDram = 0x3D # macro -PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x3E # macro -PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x3F # macro -PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 # macro -PPSMC_MSG_SetGpoAllow = 0x41 # macro -PPSMC_MSG_AllowGfxDcs = 0x42 # macro -PPSMC_MSG_DisallowGfxDcs = 0x43 # macro -PPSMC_MSG_EnableAudioStutterWA = 0x44 # macro -PPSMC_MSG_PowerUpUmsch = 0x45 # macro -PPSMC_MSG_PowerDownUmsch = 0x46 # macro -PPSMC_MSG_SetDcsArch = 0x47 # macro -PPSMC_MSG_TriggerVFFLR = 0x48 # macro -PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x49 # macro -PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4A # macro -PPSMC_MSG_SetPriorityDeltaGain = 0x4B # macro -PPSMC_MSG_AllowIHHostInterrupt = 0x4C # macro -PPSMC_MSG_DALNotPresent = 0x4E # macro -PPSMC_MSG_EnableUCLKShadow = 0x51 # macro -PPSMC_Message_Count = 0x52 # macro -DEBUGSMC_MSG_TestMessage = 0x1 # macro -DEBUGSMC_MSG_GetDebugData = 0x2 # macro -DEBUGSMC_MSG_DebugDumpExit = 0x3 # macro -DEBUGSMC_Message_Count = 0x4 # macro -SMU13_DRIVER_IF_V13_0_0_H = True # macro -int32_t = True # macro -uint32_t = True # macro -int8_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -int16_t = True # macro -uint64_t = True # macro -bool = True # macro -SMU13_0_0_DRIVER_IF_VERSION = 0x3D # macro -PPTABLE_VERSION = 0x2B # macro -NUM_GFXCLK_DPM_LEVELS = 16 # macro -NUM_SOCCLK_DPM_LEVELS = 8 # macro -NUM_MP0CLK_DPM_LEVELS = 2 # macro -NUM_DCLK_DPM_LEVELS = 8 # macro -NUM_VCLK_DPM_LEVELS = 8 # macro -NUM_DISPCLK_DPM_LEVELS = 8 # macro -NUM_DPPCLK_DPM_LEVELS = 8 # macro -NUM_DPREFCLK_DPM_LEVELS = 8 # macro -NUM_DCFCLK_DPM_LEVELS = 8 # macro -NUM_DTBCLK_DPM_LEVELS = 8 # macro -NUM_UCLK_DPM_LEVELS = 4 # macro -NUM_LINK_LEVELS = 3 # macro -NUM_FCLK_DPM_LEVELS = 8 # macro -NUM_OD_FAN_MAX_POINTS = 6 # macro -FEATURE_FW_DATA_READ_BIT = 0 # macro -FEATURE_DPM_GFXCLK_BIT = 1 # macro -FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 # macro -FEATURE_DPM_UCLK_BIT = 3 # macro -FEATURE_DPM_FCLK_BIT = 4 # macro -FEATURE_DPM_SOCCLK_BIT = 5 # macro -FEATURE_DPM_MP0CLK_BIT = 6 # macro -FEATURE_DPM_LINK_BIT = 7 # macro -FEATURE_DPM_DCN_BIT = 8 # macro -FEATURE_VMEMP_SCALING_BIT = 9 # macro -FEATURE_VDDIO_MEM_SCALING_BIT = 10 # macro -FEATURE_DS_GFXCLK_BIT = 11 # macro -FEATURE_DS_SOCCLK_BIT = 12 # macro -FEATURE_DS_FCLK_BIT = 13 # macro -FEATURE_DS_LCLK_BIT = 14 # macro -FEATURE_DS_DCFCLK_BIT = 15 # macro -FEATURE_DS_UCLK_BIT = 16 # macro -FEATURE_GFX_ULV_BIT = 17 # macro -FEATURE_FW_DSTATE_BIT = 18 # macro -FEATURE_GFXOFF_BIT = 19 # macro -FEATURE_BACO_BIT = 20 # macro -FEATURE_MM_DPM_BIT = 21 # macro -FEATURE_SOC_MPCLK_DS_BIT = 22 # macro -FEATURE_BACO_MPCLK_DS_BIT = 23 # macro -FEATURE_THROTTLERS_BIT = 24 # macro -FEATURE_SMARTSHIFT_BIT = 25 # macro -FEATURE_GTHR_BIT = 26 # macro -FEATURE_ACDC_BIT = 27 # macro -FEATURE_VR0HOT_BIT = 28 # macro -FEATURE_FW_CTF_BIT = 29 # macro -FEATURE_FAN_CONTROL_BIT = 30 # macro -FEATURE_GFX_DCS_BIT = 31 # macro -FEATURE_GFX_READ_MARGIN_BIT = 32 # macro -FEATURE_LED_DISPLAY_BIT = 33 # macro -FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 34 # macro -FEATURE_OUT_OF_BAND_MONITOR_BIT = 35 # macro -FEATURE_OPTIMIZED_VMIN_BIT = 36 # macro -FEATURE_GFX_IMU_BIT = 37 # macro -FEATURE_BOOT_TIME_CAL_BIT = 38 # macro -FEATURE_GFX_PCC_DFLL_BIT = 39 # macro -FEATURE_SOC_CG_BIT = 40 # macro -FEATURE_DF_CSTATE_BIT = 41 # macro -FEATURE_GFX_EDC_BIT = 42 # macro -FEATURE_BOOT_POWER_OPT_BIT = 43 # macro -FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 44 # macro -FEATURE_DS_VCN_BIT = 45 # macro -FEATURE_BACO_CG_BIT = 46 # macro -FEATURE_MEM_TEMP_READ_BIT = 47 # macro -FEATURE_ATHUB_MMHUB_PG_BIT = 48 # macro -FEATURE_SOC_PCC_BIT = 49 # macro -FEATURE_EDC_PWRBRK_BIT = 50 # macro -FEATURE_BOMXCO_SVI3_PROG_BIT = 51 # macro -FEATURE_SPARE_52_BIT = 52 # macro -FEATURE_SPARE_53_BIT = 53 # macro -FEATURE_SPARE_54_BIT = 54 # macro -FEATURE_SPARE_55_BIT = 55 # macro -FEATURE_SPARE_56_BIT = 56 # macro -FEATURE_SPARE_57_BIT = 57 # macro -FEATURE_SPARE_58_BIT = 58 # macro -FEATURE_SPARE_59_BIT = 59 # macro -FEATURE_SPARE_60_BIT = 60 # macro -FEATURE_SPARE_61_BIT = 61 # macro -FEATURE_SPARE_62_BIT = 62 # macro -FEATURE_SPARE_63_BIT = 63 # macro -NUM_FEATURES = 64 # macro -ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF # macro -ALLOWED_FEATURE_CTRL_SCPM = ((1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<45)) # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK = 0x00000001 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 # macro -DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 # macro -DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 # macro -DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 # macro -DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 # macro -DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 # macro -DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 # macro -DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 # macro -DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 # macro -DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 # macro -VR_MAPPING_VR_SELECT_MASK = 0x01 # macro -VR_MAPPING_VR_SELECT_SHIFT = 0x00 # macro -VR_MAPPING_PLANE_SELECT_MASK = 0x02 # macro -VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI0 = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI1 = 0x02 # macro -PSI_SEL_VR0_PLANE1_PSI0 = 0x04 # macro -PSI_SEL_VR0_PLANE1_PSI1 = 0x08 # macro -PSI_SEL_VR1_PLANE0_PSI0 = 0x10 # macro -PSI_SEL_VR1_PLANE0_PSI1 = 0x20 # macro -PSI_SEL_VR1_PLANE1_PSI0 = 0x40 # macro -PSI_SEL_VR1_PLANE1_PSI1 = 0x80 # macro -THROTTLER_TEMP_EDGE_BIT = 0 # macro -THROTTLER_TEMP_HOTSPOT_BIT = 1 # macro -THROTTLER_TEMP_HOTSPOT_G_BIT = 2 # macro -THROTTLER_TEMP_HOTSPOT_M_BIT = 3 # macro -THROTTLER_TEMP_MEM_BIT = 4 # macro -THROTTLER_TEMP_VR_GFX_BIT = 5 # macro -THROTTLER_TEMP_VR_MEM0_BIT = 6 # macro -THROTTLER_TEMP_VR_MEM1_BIT = 7 # macro -THROTTLER_TEMP_VR_SOC_BIT = 8 # macro -THROTTLER_TEMP_VR_U_BIT = 9 # macro -THROTTLER_TEMP_LIQUID0_BIT = 10 # macro -THROTTLER_TEMP_LIQUID1_BIT = 11 # macro -THROTTLER_TEMP_PLX_BIT = 12 # macro -THROTTLER_TDC_GFX_BIT = 13 # macro -THROTTLER_TDC_SOC_BIT = 14 # macro -THROTTLER_TDC_U_BIT = 15 # macro -THROTTLER_PPT0_BIT = 16 # macro -THROTTLER_PPT1_BIT = 17 # macro -THROTTLER_PPT2_BIT = 18 # macro -THROTTLER_PPT3_BIT = 19 # macro -THROTTLER_FIT_BIT = 20 # macro -THROTTLER_GFX_APCC_PLUS_BIT = 21 # macro -THROTTLER_COUNT = 22 # macro -FW_DSTATE_SOC_ULV_BIT = 0 # macro -FW_DSTATE_G6_HSR_BIT = 1 # macro -FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 # macro -FW_DSTATE_SMN_DS_BIT = 3 # macro -FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 # macro -FW_DSTATE_SOC_LIV_MIN_BIT = 5 # macro -FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 # macro -FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 # macro -FW_DSTATE_MALL_ALLOC_BIT = 8 # macro -FW_DSTATE_MEM_PSI_BIT = 9 # macro -FW_DSTATE_HSR_NON_STROBE_BIT = 10 # macro -FW_DSTATE_MP0_ENTER_WFI_BIT = 11 # macro -FW_DSTATE_U_ULV_BIT = 12 # macro -FW_DSTATE_MALL_FLUSH_BIT = 13 # macro -FW_DSTATE_SOC_PSI_BIT = 14 # macro -FW_DSTATE_U_PSI_BIT = 15 # macro -FW_DSTATE_UCP_DS_BIT = 16 # macro -FW_DSTATE_CSRCLK_DS_BIT = 17 # macro -FW_DSTATE_MMHUB_INTERLOCK_BIT = 18 # macro -FW_DSTATE_D0i3_2_QUIET_FW_BIT = 19 # macro -FW_DSTATE_CLDO_PRG_BIT = 20 # macro -FW_DSTATE_DF_PLL_PWRDN_BIT = 21 # macro -FW_DSTATE_U_LOW_PWR_MODE_EN_BIT = 22 # macro -FW_DSTATE_GFX_PSI6_BIT = 23 # macro -FW_DSTATE_GFX_VR_PWR_STAGE_BIT = 24 # macro -LED_DISPLAY_GFX_DPM_BIT = 0 # macro -LED_DISPLAY_PCIE_BIT = 1 # macro -LED_DISPLAY_ERROR_BIT = 2 # macro -MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 # macro -MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 # macro -MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 # macro -NUM_I2C_CONTROLLERS = 8 # macro -I2C_CONTROLLER_ENABLED = 1 # macro -I2C_CONTROLLER_DISABLED = 0 # macro -MAX_SW_I2C_COMMANDS = 24 # macro -CMDCONFIG_STOP_BIT = 0 # macro -CMDCONFIG_RESTART_BIT = 1 # macro -CMDCONFIG_READWRITE_BIT = 2 # macro -CMDCONFIG_STOP_MASK = (1<<0) # macro -CMDCONFIG_RESTART_MASK = (1<<1) # macro -CMDCONFIG_READWRITE_MASK = (1<<2) # macro -PP_NUM_RTAVFS_PWL_ZONES = 5 # macro -PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 # macro -PP_OD_FEATURE_PPT_BIT = 2 # macro -PP_OD_FEATURE_FAN_CURVE_BIT = 3 # macro -PP_OD_FEATURE_GFXCLK_BIT = 7 # macro -PP_OD_FEATURE_UCLK_BIT = 8 # macro -PP_OD_FEATURE_ZERO_FAN_BIT = 9 # macro -PP_OD_FEATURE_TEMPERATURE_BIT = 10 # macro -PP_OD_FEATURE_COUNT = 13 # macro -PP_NUM_OD_VF_CURVE_POINTS = 5 + 1 # macro -INVALID_BOARD_GPIO = 0xFF # macro -MARKETING_BASE_CLOCKS = 0 # macro -MARKETING_GAME_CLOCKS = 1 # macro -MARKETING_BOOST_CLOCKS = 2 # macro -NUM_WM_RANGES = 4 # macro -WORKLOAD_PPLIB_DEFAULT_BIT = 0 # macro -WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 # macro -WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 # macro -WORKLOAD_PPLIB_VIDEO_BIT = 3 # macro -WORKLOAD_PPLIB_VR_BIT = 4 # macro -WORKLOAD_PPLIB_COMPUTE_BIT = 5 # macro -WORKLOAD_PPLIB_CUSTOM_BIT = 6 # macro -WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 # macro -WORKLOAD_PPLIB_COUNT = 8 # macro -TABLE_TRANSFER_OK = 0x0 # macro -TABLE_TRANSFER_FAILED = 0xFF # macro -TABLE_TRANSFER_PENDING = 0xAB # macro -TABLE_PPTABLE = 0 # macro -TABLE_COMBO_PPTABLE = 1 # macro -TABLE_WATERMARKS = 2 # macro -TABLE_AVFS_PSM_DEBUG = 3 # macro -TABLE_PMSTATUSLOG = 4 # macro -TABLE_SMU_METRICS = 5 # macro -TABLE_DRIVER_SMU_CONFIG = 6 # macro -TABLE_ACTIVITY_MONITOR_COEFF = 7 # macro -TABLE_OVERDRIVE = 8 # macro -TABLE_I2C_COMMANDS = 9 # macro -TABLE_DRIVER_INFO = 10 # macro -TABLE_ECCINFO = 11 # macro -TABLE_WIFIBAND = 12 # macro -TABLE_COUNT = 13 # macro -IH_INTERRUPT_ID_TO_DRIVER = 0xFE # macro -IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 # macro -IH_INTERRUPT_CONTEXT_ID_AC = 0x3 # macro -IH_INTERRUPT_CONTEXT_ID_DC = 0x4 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 # macro -IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 # macro - -# values for enumeration 'c__EA_FEATURE_PWR_DOMAIN_e' -c__EA_FEATURE_PWR_DOMAIN_e__enumvalues = { - 0: 'FEATURE_PWR_ALL', - 1: 'FEATURE_PWR_S5', - 2: 'FEATURE_PWR_BACO', - 3: 'FEATURE_PWR_SOC', - 4: 'FEATURE_PWR_GFX', - 5: 'FEATURE_PWR_DOMAIN_COUNT', -} -FEATURE_PWR_ALL = 0 -FEATURE_PWR_S5 = 1 -FEATURE_PWR_BACO = 2 -FEATURE_PWR_SOC = 3 -FEATURE_PWR_GFX = 4 -FEATURE_PWR_DOMAIN_COUNT = 5 -c__EA_FEATURE_PWR_DOMAIN_e = ctypes.c_uint32 # enum -FEATURE_PWR_DOMAIN_e = c__EA_FEATURE_PWR_DOMAIN_e -FEATURE_PWR_DOMAIN_e__enumvalues = c__EA_FEATURE_PWR_DOMAIN_e__enumvalues - -# values for enumeration 'c__EA_SVI_PSI_e' -c__EA_SVI_PSI_e__enumvalues = { - 0: 'SVI_PSI_0', - 1: 'SVI_PSI_1', - 2: 'SVI_PSI_2', - 3: 'SVI_PSI_3', - 4: 'SVI_PSI_4', - 5: 'SVI_PSI_5', - 6: 'SVI_PSI_6', - 7: 'SVI_PSI_7', -} -SVI_PSI_0 = 0 -SVI_PSI_1 = 1 -SVI_PSI_2 = 2 -SVI_PSI_3 = 3 -SVI_PSI_4 = 4 -SVI_PSI_5 = 5 -SVI_PSI_6 = 6 -SVI_PSI_7 = 7 -c__EA_SVI_PSI_e = ctypes.c_uint32 # enum -SVI_PSI_e = c__EA_SVI_PSI_e -SVI_PSI_e__enumvalues = c__EA_SVI_PSI_e__enumvalues - -# values for enumeration 'c__EA_SMARTSHIFT_VERSION_e' -c__EA_SMARTSHIFT_VERSION_e__enumvalues = { - 0: 'SMARTSHIFT_VERSION_1', - 1: 'SMARTSHIFT_VERSION_2', - 2: 'SMARTSHIFT_VERSION_3', -} -SMARTSHIFT_VERSION_1 = 0 -SMARTSHIFT_VERSION_2 = 1 -SMARTSHIFT_VERSION_3 = 2 -c__EA_SMARTSHIFT_VERSION_e = ctypes.c_uint32 # enum -SMARTSHIFT_VERSION_e = c__EA_SMARTSHIFT_VERSION_e -SMARTSHIFT_VERSION_e__enumvalues = c__EA_SMARTSHIFT_VERSION_e__enumvalues - -# values for enumeration 'c__EA_FOPT_CALC_e' -c__EA_FOPT_CALC_e__enumvalues = { - 0: 'FOPT_CALC_AC_CALC_DC', - 1: 'FOPT_PPTABLE_AC_CALC_DC', - 2: 'FOPT_CALC_AC_PPTABLE_DC', - 3: 'FOPT_PPTABLE_AC_PPTABLE_DC', -} -FOPT_CALC_AC_CALC_DC = 0 -FOPT_PPTABLE_AC_CALC_DC = 1 -FOPT_CALC_AC_PPTABLE_DC = 2 -FOPT_PPTABLE_AC_PPTABLE_DC = 3 -c__EA_FOPT_CALC_e = ctypes.c_uint32 # enum -FOPT_CALC_e = c__EA_FOPT_CALC_e -FOPT_CALC_e__enumvalues = c__EA_FOPT_CALC_e__enumvalues - -# values for enumeration 'c__EA_DRAM_BIT_WIDTH_TYPE_e' -c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues = { - 0: 'DRAM_BIT_WIDTH_DISABLED', - 8: 'DRAM_BIT_WIDTH_X_8', - 16: 'DRAM_BIT_WIDTH_X_16', - 32: 'DRAM_BIT_WIDTH_X_32', - 64: 'DRAM_BIT_WIDTH_X_64', - 128: 'DRAM_BIT_WIDTH_X_128', - 129: 'DRAM_BIT_WIDTH_COUNT', -} -DRAM_BIT_WIDTH_DISABLED = 0 -DRAM_BIT_WIDTH_X_8 = 8 -DRAM_BIT_WIDTH_X_16 = 16 -DRAM_BIT_WIDTH_X_32 = 32 -DRAM_BIT_WIDTH_X_64 = 64 -DRAM_BIT_WIDTH_X_128 = 128 -DRAM_BIT_WIDTH_COUNT = 129 -c__EA_DRAM_BIT_WIDTH_TYPE_e = ctypes.c_uint32 # enum -DRAM_BIT_WIDTH_TYPE_e = c__EA_DRAM_BIT_WIDTH_TYPE_e -DRAM_BIT_WIDTH_TYPE_e__enumvalues = c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerPort_e' -c__EA_I2cControllerPort_e__enumvalues = { - 0: 'I2C_CONTROLLER_PORT_0', - 1: 'I2C_CONTROLLER_PORT_1', - 2: 'I2C_CONTROLLER_PORT_COUNT', -} -I2C_CONTROLLER_PORT_0 = 0 -I2C_CONTROLLER_PORT_1 = 1 -I2C_CONTROLLER_PORT_COUNT = 2 -c__EA_I2cControllerPort_e = ctypes.c_uint32 # enum -I2cControllerPort_e = c__EA_I2cControllerPort_e -I2cControllerPort_e__enumvalues = c__EA_I2cControllerPort_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerName_e' -c__EA_I2cControllerName_e__enumvalues = { - 0: 'I2C_CONTROLLER_NAME_VR_GFX', - 1: 'I2C_CONTROLLER_NAME_VR_SOC', - 2: 'I2C_CONTROLLER_NAME_VR_VMEMP', - 3: 'I2C_CONTROLLER_NAME_VR_VDDIO', - 4: 'I2C_CONTROLLER_NAME_LIQUID0', - 5: 'I2C_CONTROLLER_NAME_LIQUID1', - 6: 'I2C_CONTROLLER_NAME_PLX', - 7: 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 8: 'I2C_CONTROLLER_NAME_COUNT', -} -I2C_CONTROLLER_NAME_VR_GFX = 0 -I2C_CONTROLLER_NAME_VR_SOC = 1 -I2C_CONTROLLER_NAME_VR_VMEMP = 2 -I2C_CONTROLLER_NAME_VR_VDDIO = 3 -I2C_CONTROLLER_NAME_LIQUID0 = 4 -I2C_CONTROLLER_NAME_LIQUID1 = 5 -I2C_CONTROLLER_NAME_PLX = 6 -I2C_CONTROLLER_NAME_FAN_INTAKE = 7 -I2C_CONTROLLER_NAME_COUNT = 8 -c__EA_I2cControllerName_e = ctypes.c_uint32 # enum -I2cControllerName_e = c__EA_I2cControllerName_e -I2cControllerName_e__enumvalues = c__EA_I2cControllerName_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerThrottler_e' -c__EA_I2cControllerThrottler_e__enumvalues = { - 0: 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 1: 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 2: 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 3: 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', - 4: 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 5: 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 6: 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 7: 'I2C_CONTROLLER_THROTTLER_PLX', - 8: 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 9: 'I2C_CONTROLLER_THROTTLER_INA3221', - 10: 'I2C_CONTROLLER_THROTTLER_COUNT', -} -I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0 -I2C_CONTROLLER_THROTTLER_VR_GFX = 1 -I2C_CONTROLLER_THROTTLER_VR_SOC = 2 -I2C_CONTROLLER_THROTTLER_VR_VMEMP = 3 -I2C_CONTROLLER_THROTTLER_VR_VDDIO = 4 -I2C_CONTROLLER_THROTTLER_LIQUID0 = 5 -I2C_CONTROLLER_THROTTLER_LIQUID1 = 6 -I2C_CONTROLLER_THROTTLER_PLX = 7 -I2C_CONTROLLER_THROTTLER_FAN_INTAKE = 8 -I2C_CONTROLLER_THROTTLER_INA3221 = 9 -I2C_CONTROLLER_THROTTLER_COUNT = 10 -c__EA_I2cControllerThrottler_e = ctypes.c_uint32 # enum -I2cControllerThrottler_e = c__EA_I2cControllerThrottler_e -I2cControllerThrottler_e__enumvalues = c__EA_I2cControllerThrottler_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerProtocol_e' -c__EA_I2cControllerProtocol_e__enumvalues = { - 0: 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 1: 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 2: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 3: 'I2C_CONTROLLER_PROTOCOL_INA3221', - 4: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 5: 'I2C_CONTROLLER_PROTOCOL_COUNT', -} -I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = 0 -I2C_CONTROLLER_PROTOCOL_VR_IR35217 = 1 -I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = 2 -I2C_CONTROLLER_PROTOCOL_INA3221 = 3 -I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = 4 -I2C_CONTROLLER_PROTOCOL_COUNT = 5 -c__EA_I2cControllerProtocol_e = ctypes.c_uint32 # enum -I2cControllerProtocol_e = c__EA_I2cControllerProtocol_e -I2cControllerProtocol_e__enumvalues = c__EA_I2cControllerProtocol_e__enumvalues -class struct_c__SA_I2cControllerConfig_t(Structure): - pass - -struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False -struct_c__SA_I2cControllerConfig_t._fields_ = [ - ('Enabled', ctypes.c_ubyte), - ('Speed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('ControllerPort', ctypes.c_ubyte), - ('ControllerName', ctypes.c_ubyte), - ('ThermalThrotter', ctypes.c_ubyte), - ('I2cProtocol', ctypes.c_ubyte), - ('PaddingConfig', ctypes.c_ubyte), -] - -I2cControllerConfig_t = struct_c__SA_I2cControllerConfig_t - -# values for enumeration 'c__EA_I2cPort_e' -c__EA_I2cPort_e__enumvalues = { - 0: 'I2C_PORT_SVD_SCL', - 1: 'I2C_PORT_GPIO', -} -I2C_PORT_SVD_SCL = 0 -I2C_PORT_GPIO = 1 -c__EA_I2cPort_e = ctypes.c_uint32 # enum -I2cPort_e = c__EA_I2cPort_e -I2cPort_e__enumvalues = c__EA_I2cPort_e__enumvalues - -# values for enumeration 'c__EA_I2cSpeed_e' -c__EA_I2cSpeed_e__enumvalues = { - 0: 'I2C_SPEED_FAST_50K', - 1: 'I2C_SPEED_FAST_100K', - 2: 'I2C_SPEED_FAST_400K', - 3: 'I2C_SPEED_FAST_PLUS_1M', - 4: 'I2C_SPEED_HIGH_1M', - 5: 'I2C_SPEED_HIGH_2M', - 6: 'I2C_SPEED_COUNT', -} -I2C_SPEED_FAST_50K = 0 -I2C_SPEED_FAST_100K = 1 -I2C_SPEED_FAST_400K = 2 -I2C_SPEED_FAST_PLUS_1M = 3 -I2C_SPEED_HIGH_1M = 4 -I2C_SPEED_HIGH_2M = 5 -I2C_SPEED_COUNT = 6 -c__EA_I2cSpeed_e = ctypes.c_uint32 # enum -I2cSpeed_e = c__EA_I2cSpeed_e -I2cSpeed_e__enumvalues = c__EA_I2cSpeed_e__enumvalues - -# values for enumeration 'c__EA_I2cCmdType_e' -c__EA_I2cCmdType_e__enumvalues = { - 0: 'I2C_CMD_READ', - 1: 'I2C_CMD_WRITE', - 2: 'I2C_CMD_COUNT', -} -I2C_CMD_READ = 0 -I2C_CMD_WRITE = 1 -I2C_CMD_COUNT = 2 -c__EA_I2cCmdType_e = ctypes.c_uint32 # enum -I2cCmdType_e = c__EA_I2cCmdType_e -I2cCmdType_e__enumvalues = c__EA_I2cCmdType_e__enumvalues -class struct_c__SA_SwI2cCmd_t(Structure): - pass - -struct_c__SA_SwI2cCmd_t._pack_ = 1 # source:False -struct_c__SA_SwI2cCmd_t._fields_ = [ - ('ReadWriteData', ctypes.c_ubyte), - ('CmdConfig', ctypes.c_ubyte), -] - -SwI2cCmd_t = struct_c__SA_SwI2cCmd_t -class struct_c__SA_SwI2cRequest_t(Structure): - pass - -struct_c__SA_SwI2cRequest_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequest_t._fields_ = [ - ('I2CcontrollerPort', ctypes.c_ubyte), - ('I2CSpeed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('NumCmds', ctypes.c_ubyte), - ('SwI2cCmds', struct_c__SA_SwI2cCmd_t * 24), -] - -SwI2cRequest_t = struct_c__SA_SwI2cRequest_t -class struct_c__SA_SwI2cRequestExternal_t(Structure): - pass - -struct_c__SA_SwI2cRequestExternal_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequestExternal_t._fields_ = [ - ('SwI2cRequest', SwI2cRequest_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SwI2cRequestExternal_t = struct_c__SA_SwI2cRequestExternal_t -class struct_c__SA_EccInfo_t(Structure): - pass - -struct_c__SA_EccInfo_t._pack_ = 1 # source:False -struct_c__SA_EccInfo_t._fields_ = [ - ('mca_umc_status', ctypes.c_uint64), - ('mca_umc_addr', ctypes.c_uint64), - ('ce_count_lo_chip', ctypes.c_uint16), - ('ce_count_hi_chip', ctypes.c_uint16), - ('eccPadding', ctypes.c_uint32), -] - -EccInfo_t = struct_c__SA_EccInfo_t -class struct_c__SA_EccInfoTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('EccInfo', struct_c__SA_EccInfo_t * 24), - ] - -EccInfoTable_t = struct_c__SA_EccInfoTable_t - -# values for enumeration 'c__EA_D3HOTSequence_e' -c__EA_D3HOTSequence_e__enumvalues = { - 0: 'BACO_SEQUENCE', - 1: 'MSR_SEQUENCE', - 2: 'BAMACO_SEQUENCE', - 3: 'ULPS_SEQUENCE', - 4: 'D3HOT_SEQUENCE_COUNT', -} -BACO_SEQUENCE = 0 -MSR_SEQUENCE = 1 -BAMACO_SEQUENCE = 2 -ULPS_SEQUENCE = 3 -D3HOT_SEQUENCE_COUNT = 4 -c__EA_D3HOTSequence_e = ctypes.c_uint32 # enum -D3HOTSequence_e = c__EA_D3HOTSequence_e -D3HOTSequence_e__enumvalues = c__EA_D3HOTSequence_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingMode_e' -c__EA_PowerGatingMode_e__enumvalues = { - 0: 'PG_DYNAMIC_MODE', - 1: 'PG_STATIC_MODE', -} -PG_DYNAMIC_MODE = 0 -PG_STATIC_MODE = 1 -c__EA_PowerGatingMode_e = ctypes.c_uint32 # enum -PowerGatingMode_e = c__EA_PowerGatingMode_e -PowerGatingMode_e__enumvalues = c__EA_PowerGatingMode_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingSettings_e' -c__EA_PowerGatingSettings_e__enumvalues = { - 0: 'PG_POWER_DOWN', - 1: 'PG_POWER_UP', -} -PG_POWER_DOWN = 0 -PG_POWER_UP = 1 -c__EA_PowerGatingSettings_e = ctypes.c_uint32 # enum -PowerGatingSettings_e = c__EA_PowerGatingSettings_e -PowerGatingSettings_e__enumvalues = c__EA_PowerGatingSettings_e__enumvalues -class struct_c__SA_QuadraticInt_t(Structure): - pass - -struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False -struct_c__SA_QuadraticInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -QuadraticInt_t = struct_c__SA_QuadraticInt_t -class struct_c__SA_LinearInt_t(Structure): - pass - -struct_c__SA_LinearInt_t._pack_ = 1 # source:False -struct_c__SA_LinearInt_t._fields_ = [ - ('m', ctypes.c_uint32), - ('b', ctypes.c_uint32), -] - -LinearInt_t = struct_c__SA_LinearInt_t -class struct_c__SA_DroopInt_t(Structure): - pass - -struct_c__SA_DroopInt_t._pack_ = 1 # source:False -struct_c__SA_DroopInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -DroopInt_t = struct_c__SA_DroopInt_t - -# values for enumeration 'c__EA_DCS_ARCH_e' -c__EA_DCS_ARCH_e__enumvalues = { - 0: 'DCS_ARCH_DISABLED', - 1: 'DCS_ARCH_FADCS', - 2: 'DCS_ARCH_ASYNC', -} -DCS_ARCH_DISABLED = 0 -DCS_ARCH_FADCS = 1 -DCS_ARCH_ASYNC = 2 -c__EA_DCS_ARCH_e = ctypes.c_uint32 # enum -DCS_ARCH_e = c__EA_DCS_ARCH_e -DCS_ARCH_e__enumvalues = c__EA_DCS_ARCH_e__enumvalues - -# values for enumeration 'c__EA_PPCLK_e' -c__EA_PPCLK_e__enumvalues = { - 0: 'PPCLK_GFXCLK', - 1: 'PPCLK_SOCCLK', - 2: 'PPCLK_UCLK', - 3: 'PPCLK_FCLK', - 4: 'PPCLK_DCLK_0', - 5: 'PPCLK_VCLK_0', - 6: 'PPCLK_DCLK_1', - 7: 'PPCLK_VCLK_1', - 8: 'PPCLK_DISPCLK', - 9: 'PPCLK_DPPCLK', - 10: 'PPCLK_DPREFCLK', - 11: 'PPCLK_DCFCLK', - 12: 'PPCLK_DTBCLK', - 13: 'PPCLK_COUNT', -} -PPCLK_GFXCLK = 0 -PPCLK_SOCCLK = 1 -PPCLK_UCLK = 2 -PPCLK_FCLK = 3 -PPCLK_DCLK_0 = 4 -PPCLK_VCLK_0 = 5 -PPCLK_DCLK_1 = 6 -PPCLK_VCLK_1 = 7 -PPCLK_DISPCLK = 8 -PPCLK_DPPCLK = 9 -PPCLK_DPREFCLK = 10 -PPCLK_DCFCLK = 11 -PPCLK_DTBCLK = 12 -PPCLK_COUNT = 13 -c__EA_PPCLK_e = ctypes.c_uint32 # enum -PPCLK_e = c__EA_PPCLK_e -PPCLK_e__enumvalues = c__EA_PPCLK_e__enumvalues - -# values for enumeration 'c__EA_VOLTAGE_MODE_e' -c__EA_VOLTAGE_MODE_e__enumvalues = { - 0: 'VOLTAGE_MODE_PPTABLE', - 1: 'VOLTAGE_MODE_FUSES', - 2: 'VOLTAGE_MODE_COUNT', -} -VOLTAGE_MODE_PPTABLE = 0 -VOLTAGE_MODE_FUSES = 1 -VOLTAGE_MODE_COUNT = 2 -c__EA_VOLTAGE_MODE_e = ctypes.c_uint32 # enum -VOLTAGE_MODE_e = c__EA_VOLTAGE_MODE_e -VOLTAGE_MODE_e__enumvalues = c__EA_VOLTAGE_MODE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_VOLTAGE_TYPE_e' -c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues = { - 0: 'AVFS_VOLTAGE_GFX', - 1: 'AVFS_VOLTAGE_SOC', - 2: 'AVFS_VOLTAGE_COUNT', -} -AVFS_VOLTAGE_GFX = 0 -AVFS_VOLTAGE_SOC = 1 -AVFS_VOLTAGE_COUNT = 2 -c__EA_AVFS_VOLTAGE_TYPE_e = ctypes.c_uint32 # enum -AVFS_VOLTAGE_TYPE_e = c__EA_AVFS_VOLTAGE_TYPE_e -AVFS_VOLTAGE_TYPE_e__enumvalues = c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_TEMP_e' -c__EA_AVFS_TEMP_e__enumvalues = { - 0: 'AVFS_TEMP_COLD', - 1: 'AVFS_TEMP_HOT', - 2: 'AVFS_TEMP_COUNT', -} -AVFS_TEMP_COLD = 0 -AVFS_TEMP_HOT = 1 -AVFS_TEMP_COUNT = 2 -c__EA_AVFS_TEMP_e = ctypes.c_uint32 # enum -AVFS_TEMP_e = c__EA_AVFS_TEMP_e -AVFS_TEMP_e__enumvalues = c__EA_AVFS_TEMP_e__enumvalues - -# values for enumeration 'c__EA_AVFS_D_e' -c__EA_AVFS_D_e__enumvalues = { - 0: 'AVFS_D_G', - 1: 'AVFS_D_M_B', - 2: 'AVFS_D_M_S', - 3: 'AVFS_D_COUNT', -} -AVFS_D_G = 0 -AVFS_D_M_B = 1 -AVFS_D_M_S = 2 -AVFS_D_COUNT = 3 -c__EA_AVFS_D_e = ctypes.c_uint32 # enum -AVFS_D_e = c__EA_AVFS_D_e -AVFS_D_e__enumvalues = c__EA_AVFS_D_e__enumvalues - -# values for enumeration 'c__EA_UCLK_DIV_e' -c__EA_UCLK_DIV_e__enumvalues = { - 0: 'UCLK_DIV_BY_1', - 1: 'UCLK_DIV_BY_2', - 2: 'UCLK_DIV_BY_4', - 3: 'UCLK_DIV_BY_8', -} -UCLK_DIV_BY_1 = 0 -UCLK_DIV_BY_2 = 1 -UCLK_DIV_BY_4 = 2 -UCLK_DIV_BY_8 = 3 -c__EA_UCLK_DIV_e = ctypes.c_uint32 # enum -UCLK_DIV_e = c__EA_UCLK_DIV_e -UCLK_DIV_e__enumvalues = c__EA_UCLK_DIV_e__enumvalues - -# values for enumeration 'c__EA_GpioIntPolarity_e' -c__EA_GpioIntPolarity_e__enumvalues = { - 0: 'GPIO_INT_POLARITY_ACTIVE_LOW', - 1: 'GPIO_INT_POLARITY_ACTIVE_HIGH', -} -GPIO_INT_POLARITY_ACTIVE_LOW = 0 -GPIO_INT_POLARITY_ACTIVE_HIGH = 1 -c__EA_GpioIntPolarity_e = ctypes.c_uint32 # enum -GpioIntPolarity_e = c__EA_GpioIntPolarity_e -GpioIntPolarity_e__enumvalues = c__EA_GpioIntPolarity_e__enumvalues - -# values for enumeration 'c__EA_PwrConfig_e' -c__EA_PwrConfig_e__enumvalues = { - 0: 'PWR_CONFIG_TDP', - 1: 'PWR_CONFIG_TGP', - 2: 'PWR_CONFIG_TCP_ESTIMATED', - 3: 'PWR_CONFIG_TCP_MEASURED', -} -PWR_CONFIG_TDP = 0 -PWR_CONFIG_TGP = 1 -PWR_CONFIG_TCP_ESTIMATED = 2 -PWR_CONFIG_TCP_MEASURED = 3 -c__EA_PwrConfig_e = ctypes.c_uint32 # enum -PwrConfig_e = c__EA_PwrConfig_e -PwrConfig_e__enumvalues = c__EA_PwrConfig_e__enumvalues -class struct_c__SA_DpmDescriptor_t(Structure): - pass - -struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False -struct_c__SA_DpmDescriptor_t._fields_ = [ - ('Padding', ctypes.c_ubyte), - ('SnapToDiscrete', ctypes.c_ubyte), - ('NumDiscreteLevels', ctypes.c_ubyte), - ('CalculateFopt', ctypes.c_ubyte), - ('ConversionToAvfsClk', LinearInt_t), - ('Padding3', ctypes.c_uint32 * 3), - ('Padding4', ctypes.c_uint16), - ('FoptimalDc', ctypes.c_uint16), - ('FoptimalAc', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), -] - -DpmDescriptor_t = struct_c__SA_DpmDescriptor_t - -# values for enumeration 'c__EA_PPT_THROTTLER_e' -c__EA_PPT_THROTTLER_e__enumvalues = { - 0: 'PPT_THROTTLER_PPT0', - 1: 'PPT_THROTTLER_PPT1', - 2: 'PPT_THROTTLER_PPT2', - 3: 'PPT_THROTTLER_PPT3', - 4: 'PPT_THROTTLER_COUNT', -} -PPT_THROTTLER_PPT0 = 0 -PPT_THROTTLER_PPT1 = 1 -PPT_THROTTLER_PPT2 = 2 -PPT_THROTTLER_PPT3 = 3 -PPT_THROTTLER_COUNT = 4 -c__EA_PPT_THROTTLER_e = ctypes.c_uint32 # enum -PPT_THROTTLER_e = c__EA_PPT_THROTTLER_e -PPT_THROTTLER_e__enumvalues = c__EA_PPT_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_TEMP_e' -c__EA_TEMP_e__enumvalues = { - 0: 'TEMP_EDGE', - 1: 'TEMP_HOTSPOT', - 2: 'TEMP_HOTSPOT_G', - 3: 'TEMP_HOTSPOT_M', - 4: 'TEMP_MEM', - 5: 'TEMP_VR_GFX', - 6: 'TEMP_VR_MEM0', - 7: 'TEMP_VR_MEM1', - 8: 'TEMP_VR_SOC', - 9: 'TEMP_VR_U', - 10: 'TEMP_LIQUID0', - 11: 'TEMP_LIQUID1', - 12: 'TEMP_PLX', - 13: 'TEMP_COUNT', -} -TEMP_EDGE = 0 -TEMP_HOTSPOT = 1 -TEMP_HOTSPOT_G = 2 -TEMP_HOTSPOT_M = 3 -TEMP_MEM = 4 -TEMP_VR_GFX = 5 -TEMP_VR_MEM0 = 6 -TEMP_VR_MEM1 = 7 -TEMP_VR_SOC = 8 -TEMP_VR_U = 9 -TEMP_LIQUID0 = 10 -TEMP_LIQUID1 = 11 -TEMP_PLX = 12 -TEMP_COUNT = 13 -c__EA_TEMP_e = ctypes.c_uint32 # enum -TEMP_e = c__EA_TEMP_e -TEMP_e__enumvalues = c__EA_TEMP_e__enumvalues - -# values for enumeration 'c__EA_TDC_THROTTLER_e' -c__EA_TDC_THROTTLER_e__enumvalues = { - 0: 'TDC_THROTTLER_GFX', - 1: 'TDC_THROTTLER_SOC', - 2: 'TDC_THROTTLER_U', - 3: 'TDC_THROTTLER_COUNT', -} -TDC_THROTTLER_GFX = 0 -TDC_THROTTLER_SOC = 1 -TDC_THROTTLER_U = 2 -TDC_THROTTLER_COUNT = 3 -c__EA_TDC_THROTTLER_e = ctypes.c_uint32 # enum -TDC_THROTTLER_e = c__EA_TDC_THROTTLER_e -TDC_THROTTLER_e__enumvalues = c__EA_TDC_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_SVI_PLANE_e' -c__EA_SVI_PLANE_e__enumvalues = { - 0: 'SVI_PLANE_GFX', - 1: 'SVI_PLANE_SOC', - 2: 'SVI_PLANE_VMEMP', - 3: 'SVI_PLANE_VDDIO_MEM', - 4: 'SVI_PLANE_U', - 5: 'SVI_PLANE_COUNT', -} -SVI_PLANE_GFX = 0 -SVI_PLANE_SOC = 1 -SVI_PLANE_VMEMP = 2 -SVI_PLANE_VDDIO_MEM = 3 -SVI_PLANE_U = 4 -SVI_PLANE_COUNT = 5 -c__EA_SVI_PLANE_e = ctypes.c_uint32 # enum -SVI_PLANE_e = c__EA_SVI_PLANE_e -SVI_PLANE_e__enumvalues = c__EA_SVI_PLANE_e__enumvalues - -# values for enumeration 'c__EA_PMFW_VOLT_PLANE_e' -c__EA_PMFW_VOLT_PLANE_e__enumvalues = { - 0: 'PMFW_VOLT_PLANE_GFX', - 1: 'PMFW_VOLT_PLANE_SOC', - 2: 'PMFW_VOLT_PLANE_COUNT', -} -PMFW_VOLT_PLANE_GFX = 0 -PMFW_VOLT_PLANE_SOC = 1 -PMFW_VOLT_PLANE_COUNT = 2 -c__EA_PMFW_VOLT_PLANE_e = ctypes.c_uint32 # enum -PMFW_VOLT_PLANE_e = c__EA_PMFW_VOLT_PLANE_e -PMFW_VOLT_PLANE_e__enumvalues = c__EA_PMFW_VOLT_PLANE_e__enumvalues - -# values for enumeration 'c__EA_CUSTOMER_VARIANT_e' -c__EA_CUSTOMER_VARIANT_e__enumvalues = { - 0: 'CUSTOMER_VARIANT_ROW', - 1: 'CUSTOMER_VARIANT_FALCON', - 2: 'CUSTOMER_VARIANT_COUNT', -} -CUSTOMER_VARIANT_ROW = 0 -CUSTOMER_VARIANT_FALCON = 1 -CUSTOMER_VARIANT_COUNT = 2 -c__EA_CUSTOMER_VARIANT_e = ctypes.c_uint32 # enum -CUSTOMER_VARIANT_e = c__EA_CUSTOMER_VARIANT_e -CUSTOMER_VARIANT_e__enumvalues = c__EA_CUSTOMER_VARIANT_e__enumvalues - -# values for enumeration 'c__EA_POWER_SOURCE_e' -c__EA_POWER_SOURCE_e__enumvalues = { - 0: 'POWER_SOURCE_AC', - 1: 'POWER_SOURCE_DC', - 2: 'POWER_SOURCE_COUNT', -} -POWER_SOURCE_AC = 0 -POWER_SOURCE_DC = 1 -POWER_SOURCE_COUNT = 2 -c__EA_POWER_SOURCE_e = ctypes.c_uint32 # enum -POWER_SOURCE_e = c__EA_POWER_SOURCE_e -POWER_SOURCE_e__enumvalues = c__EA_POWER_SOURCE_e__enumvalues - -# values for enumeration 'c__EA_MEM_VENDOR_e' -c__EA_MEM_VENDOR_e__enumvalues = { - 0: 'MEM_VENDOR_PLACEHOLDER0', - 1: 'MEM_VENDOR_SAMSUNG', - 2: 'MEM_VENDOR_INFINEON', - 3: 'MEM_VENDOR_ELPIDA', - 4: 'MEM_VENDOR_ETRON', - 5: 'MEM_VENDOR_NANYA', - 6: 'MEM_VENDOR_HYNIX', - 7: 'MEM_VENDOR_MOSEL', - 8: 'MEM_VENDOR_WINBOND', - 9: 'MEM_VENDOR_ESMT', - 10: 'MEM_VENDOR_PLACEHOLDER1', - 11: 'MEM_VENDOR_PLACEHOLDER2', - 12: 'MEM_VENDOR_PLACEHOLDER3', - 13: 'MEM_VENDOR_PLACEHOLDER4', - 14: 'MEM_VENDOR_PLACEHOLDER5', - 15: 'MEM_VENDOR_MICRON', - 16: 'MEM_VENDOR_COUNT', -} -MEM_VENDOR_PLACEHOLDER0 = 0 -MEM_VENDOR_SAMSUNG = 1 -MEM_VENDOR_INFINEON = 2 -MEM_VENDOR_ELPIDA = 3 -MEM_VENDOR_ETRON = 4 -MEM_VENDOR_NANYA = 5 -MEM_VENDOR_HYNIX = 6 -MEM_VENDOR_MOSEL = 7 -MEM_VENDOR_WINBOND = 8 -MEM_VENDOR_ESMT = 9 -MEM_VENDOR_PLACEHOLDER1 = 10 -MEM_VENDOR_PLACEHOLDER2 = 11 -MEM_VENDOR_PLACEHOLDER3 = 12 -MEM_VENDOR_PLACEHOLDER4 = 13 -MEM_VENDOR_PLACEHOLDER5 = 14 -MEM_VENDOR_MICRON = 15 -MEM_VENDOR_COUNT = 16 -c__EA_MEM_VENDOR_e = ctypes.c_uint32 # enum -MEM_VENDOR_e = c__EA_MEM_VENDOR_e -MEM_VENDOR_e__enumvalues = c__EA_MEM_VENDOR_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_HW_FUSE_e' -c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', - 1: 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 2: 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', - 3: 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 4: 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', - 5: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 6: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 7: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 8: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 9: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 10: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 11: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 12: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 13: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 14: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', - 15: 'PP_GRTAVFS_HW_ZONE0_VF', - 16: 'PP_GRTAVFS_HW_ZONE1_VF1', - 17: 'PP_GRTAVFS_HW_ZONE2_VF2', - 18: 'PP_GRTAVFS_HW_ZONE3_VF3', - 19: 'PP_GRTAVFS_HW_VOLTAGE_GB', - 20: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 21: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 22: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 23: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 24: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 25: 'PP_GRTAVFS_HW_RESERVED_0', - 26: 'PP_GRTAVFS_HW_RESERVED_1', - 27: 'PP_GRTAVFS_HW_RESERVED_2', - 28: 'PP_GRTAVFS_HW_RESERVED_3', - 29: 'PP_GRTAVFS_HW_RESERVED_4', - 30: 'PP_GRTAVFS_HW_RESERVED_5', - 31: 'PP_GRTAVFS_HW_RESERVED_6', - 32: 'PP_GRTAVFS_HW_FUSE_COUNT', -} -PP_GRTAVFS_HW_CPO_CTL_ZONE0 = 0 -PP_GRTAVFS_HW_CPO_CTL_ZONE1 = 1 -PP_GRTAVFS_HW_CPO_CTL_ZONE2 = 2 -PP_GRTAVFS_HW_CPO_CTL_ZONE3 = 3 -PP_GRTAVFS_HW_CPO_CTL_ZONE4 = 4 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = 5 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = 6 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = 7 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = 8 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = 9 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = 10 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = 11 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = 12 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = 13 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = 14 -PP_GRTAVFS_HW_ZONE0_VF = 15 -PP_GRTAVFS_HW_ZONE1_VF1 = 16 -PP_GRTAVFS_HW_ZONE2_VF2 = 17 -PP_GRTAVFS_HW_ZONE3_VF3 = 18 -PP_GRTAVFS_HW_VOLTAGE_GB = 19 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = 20 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = 21 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = 22 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = 23 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = 24 -PP_GRTAVFS_HW_RESERVED_0 = 25 -PP_GRTAVFS_HW_RESERVED_1 = 26 -PP_GRTAVFS_HW_RESERVED_2 = 27 -PP_GRTAVFS_HW_RESERVED_3 = 28 -PP_GRTAVFS_HW_RESERVED_4 = 29 -PP_GRTAVFS_HW_RESERVED_5 = 30 -PP_GRTAVFS_HW_RESERVED_6 = 31 -PP_GRTAVFS_HW_FUSE_COUNT = 32 -c__EA_PP_GRTAVFS_HW_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_HW_FUSE_e = c__EA_PP_GRTAVFS_HW_FUSE_e -PP_GRTAVFS_HW_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e' -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 1: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 2: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 3: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 4: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 5: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 6: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 7: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 8: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 9: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 10: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 11: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 12: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', - 13: 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', -} -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = 0 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = 1 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = 2 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = 3 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = 4 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = 5 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = 6 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = 7 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = 8 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = 9 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = 10 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = 11 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = 12 -PP_GRTAVFS_FW_COMMON_FUSE_COUNT = 13 -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_COMMON_FUSE_e = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e -PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e' -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 1: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 2: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 3: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 4: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 5: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 6: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 7: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 8: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 9: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 10: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 11: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 12: 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 13: 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 14: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 15: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 16: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 17: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 18: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 19: 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', -} -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = 0 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = 1 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = 2 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = 3 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = 4 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = 5 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = 6 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = 7 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = 8 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = 9 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = 10 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = 11 -PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = 12 -PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = 13 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = 14 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = 15 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = 16 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = 17 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = 18 -PP_GRTAVFS_FW_SEP_FUSE_COUNT = 19 -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_SEP_FUSE_e = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e -PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues -class struct_c__SA_SviTelemetryScale_t(Structure): - pass - -struct_c__SA_SviTelemetryScale_t._pack_ = 1 # source:False -struct_c__SA_SviTelemetryScale_t._fields_ = [ - ('Offset', ctypes.c_byte), - ('Padding', ctypes.c_ubyte), - ('MaxCurrent', ctypes.c_uint16), -] - -SviTelemetryScale_t = struct_c__SA_SviTelemetryScale_t - -# values for enumeration 'c__EA_FanMode_e' -c__EA_FanMode_e__enumvalues = { - 0: 'FAN_MODE_AUTO', - 1: 'FAN_MODE_MANUAL_LINEAR', -} -FAN_MODE_AUTO = 0 -FAN_MODE_MANUAL_LINEAR = 1 -c__EA_FanMode_e = ctypes.c_uint32 # enum -FanMode_e = c__EA_FanMode_e -FanMode_e__enumvalues = c__EA_FanMode_e__enumvalues -class struct_c__SA_OverDriveTable_t(Structure): - pass - -struct_c__SA_OverDriveTable_t._pack_ = 1 # source:False -struct_c__SA_OverDriveTable_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('Reserved', ctypes.c_uint32), - ('GfxclkFmin', ctypes.c_int16), - ('GfxclkFmax', ctypes.c_int16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Spare', ctypes.c_uint32 * 13), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -OverDriveTable_t = struct_c__SA_OverDriveTable_t -class struct_c__SA_OverDriveTableExternal_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('OverDriveTable', OverDriveTable_t), - ] - -OverDriveTableExternal_t = struct_c__SA_OverDriveTableExternal_t -class struct_c__SA_OverDriveLimits_t(Structure): - pass - -struct_c__SA_OverDriveLimits_t._pack_ = 1 # source:False -struct_c__SA_OverDriveLimits_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16), - ('Reserved1', ctypes.c_uint16), - ('Reserved2', ctypes.c_uint16), - ('GfxclkFmin', ctypes.c_int16), - ('GfxclkFmax', ctypes.c_int16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte), - ('FanLinearTempPoints', ctypes.c_ubyte), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Spare', ctypes.c_uint32 * 13), -] - -OverDriveLimits_t = struct_c__SA_OverDriveLimits_t - -# values for enumeration 'c__EA_BOARD_GPIO_TYPE_e' -c__EA_BOARD_GPIO_TYPE_e__enumvalues = { - 0: 'BOARD_GPIO_SMUIO_0', - 1: 'BOARD_GPIO_SMUIO_1', - 2: 'BOARD_GPIO_SMUIO_2', - 3: 'BOARD_GPIO_SMUIO_3', - 4: 'BOARD_GPIO_SMUIO_4', - 5: 'BOARD_GPIO_SMUIO_5', - 6: 'BOARD_GPIO_SMUIO_6', - 7: 'BOARD_GPIO_SMUIO_7', - 8: 'BOARD_GPIO_SMUIO_8', - 9: 'BOARD_GPIO_SMUIO_9', - 10: 'BOARD_GPIO_SMUIO_10', - 11: 'BOARD_GPIO_SMUIO_11', - 12: 'BOARD_GPIO_SMUIO_12', - 13: 'BOARD_GPIO_SMUIO_13', - 14: 'BOARD_GPIO_SMUIO_14', - 15: 'BOARD_GPIO_SMUIO_15', - 16: 'BOARD_GPIO_SMUIO_16', - 17: 'BOARD_GPIO_SMUIO_17', - 18: 'BOARD_GPIO_SMUIO_18', - 19: 'BOARD_GPIO_SMUIO_19', - 20: 'BOARD_GPIO_SMUIO_20', - 21: 'BOARD_GPIO_SMUIO_21', - 22: 'BOARD_GPIO_SMUIO_22', - 23: 'BOARD_GPIO_SMUIO_23', - 24: 'BOARD_GPIO_SMUIO_24', - 25: 'BOARD_GPIO_SMUIO_25', - 26: 'BOARD_GPIO_SMUIO_26', - 27: 'BOARD_GPIO_SMUIO_27', - 28: 'BOARD_GPIO_SMUIO_28', - 29: 'BOARD_GPIO_SMUIO_29', - 30: 'BOARD_GPIO_SMUIO_30', - 31: 'BOARD_GPIO_SMUIO_31', - 32: 'MAX_BOARD_GPIO_SMUIO_NUM', - 33: 'BOARD_GPIO_DC_GEN_A', - 34: 'BOARD_GPIO_DC_GEN_B', - 35: 'BOARD_GPIO_DC_GEN_C', - 36: 'BOARD_GPIO_DC_GEN_D', - 37: 'BOARD_GPIO_DC_GEN_E', - 38: 'BOARD_GPIO_DC_GEN_F', - 39: 'BOARD_GPIO_DC_GEN_G', - 40: 'BOARD_GPIO_DC_GENLK_CLK', - 41: 'BOARD_GPIO_DC_GENLK_VSYNC', - 42: 'BOARD_GPIO_DC_SWAPLOCK_A', - 43: 'BOARD_GPIO_DC_SWAPLOCK_B', -} -BOARD_GPIO_SMUIO_0 = 0 -BOARD_GPIO_SMUIO_1 = 1 -BOARD_GPIO_SMUIO_2 = 2 -BOARD_GPIO_SMUIO_3 = 3 -BOARD_GPIO_SMUIO_4 = 4 -BOARD_GPIO_SMUIO_5 = 5 -BOARD_GPIO_SMUIO_6 = 6 -BOARD_GPIO_SMUIO_7 = 7 -BOARD_GPIO_SMUIO_8 = 8 -BOARD_GPIO_SMUIO_9 = 9 -BOARD_GPIO_SMUIO_10 = 10 -BOARD_GPIO_SMUIO_11 = 11 -BOARD_GPIO_SMUIO_12 = 12 -BOARD_GPIO_SMUIO_13 = 13 -BOARD_GPIO_SMUIO_14 = 14 -BOARD_GPIO_SMUIO_15 = 15 -BOARD_GPIO_SMUIO_16 = 16 -BOARD_GPIO_SMUIO_17 = 17 -BOARD_GPIO_SMUIO_18 = 18 -BOARD_GPIO_SMUIO_19 = 19 -BOARD_GPIO_SMUIO_20 = 20 -BOARD_GPIO_SMUIO_21 = 21 -BOARD_GPIO_SMUIO_22 = 22 -BOARD_GPIO_SMUIO_23 = 23 -BOARD_GPIO_SMUIO_24 = 24 -BOARD_GPIO_SMUIO_25 = 25 -BOARD_GPIO_SMUIO_26 = 26 -BOARD_GPIO_SMUIO_27 = 27 -BOARD_GPIO_SMUIO_28 = 28 -BOARD_GPIO_SMUIO_29 = 29 -BOARD_GPIO_SMUIO_30 = 30 -BOARD_GPIO_SMUIO_31 = 31 -MAX_BOARD_GPIO_SMUIO_NUM = 32 -BOARD_GPIO_DC_GEN_A = 33 -BOARD_GPIO_DC_GEN_B = 34 -BOARD_GPIO_DC_GEN_C = 35 -BOARD_GPIO_DC_GEN_D = 36 -BOARD_GPIO_DC_GEN_E = 37 -BOARD_GPIO_DC_GEN_F = 38 -BOARD_GPIO_DC_GEN_G = 39 -BOARD_GPIO_DC_GENLK_CLK = 40 -BOARD_GPIO_DC_GENLK_VSYNC = 41 -BOARD_GPIO_DC_SWAPLOCK_A = 42 -BOARD_GPIO_DC_SWAPLOCK_B = 43 -c__EA_BOARD_GPIO_TYPE_e = ctypes.c_uint32 # enum -BOARD_GPIO_TYPE_e = c__EA_BOARD_GPIO_TYPE_e -BOARD_GPIO_TYPE_e__enumvalues = c__EA_BOARD_GPIO_TYPE_e__enumvalues -class struct_c__SA_BootValues_t(Structure): - pass - -struct_c__SA_BootValues_t._pack_ = 1 # source:False -struct_c__SA_BootValues_t._fields_ = [ - ('InitGfxclk_bypass', ctypes.c_uint16), - ('InitSocclk', ctypes.c_uint16), - ('InitMp0clk', ctypes.c_uint16), - ('InitMpioclk', ctypes.c_uint16), - ('InitSmnclk', ctypes.c_uint16), - ('InitUcpclk', ctypes.c_uint16), - ('InitCsrclk', ctypes.c_uint16), - ('InitDprefclk', ctypes.c_uint16), - ('InitDcfclk', ctypes.c_uint16), - ('InitDtbclk', ctypes.c_uint16), - ('InitDclk', ctypes.c_uint16), - ('InitVclk', ctypes.c_uint16), - ('InitUsbdfsclk', ctypes.c_uint16), - ('InitMp1clk', ctypes.c_uint16), - ('InitLclk', ctypes.c_uint16), - ('InitBaco400clk_bypass', ctypes.c_uint16), - ('InitBaco1200clk_bypass', ctypes.c_uint16), - ('InitBaco700clk_bypass', ctypes.c_uint16), - ('InitFclk', ctypes.c_uint16), - ('InitGfxclk_clkb', ctypes.c_uint16), - ('InitUclkDPMState', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('InitVcoFreqPll0', ctypes.c_uint32), - ('InitVcoFreqPll1', ctypes.c_uint32), - ('InitVcoFreqPll2', ctypes.c_uint32), - ('InitVcoFreqPll3', ctypes.c_uint32), - ('InitVcoFreqPll4', ctypes.c_uint32), - ('InitVcoFreqPll5', ctypes.c_uint32), - ('InitVcoFreqPll6', ctypes.c_uint32), - ('InitGfx', ctypes.c_uint16), - ('InitSoc', ctypes.c_uint16), - ('InitU', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 8), -] - -BootValues_t = struct_c__SA_BootValues_t -class struct_c__SA_MsgLimits_t(Structure): - pass - -struct_c__SA_MsgLimits_t._pack_ = 1 # source:False -struct_c__SA_MsgLimits_t._fields_ = [ - ('Power', ctypes.c_uint16 * 2 * 4), - ('Tdc', ctypes.c_uint16 * 3), - ('Temperature', ctypes.c_uint16 * 13), - ('PwmLimitMin', ctypes.c_ubyte), - ('PwmLimitMax', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_ubyte), - ('Spare1', ctypes.c_ubyte * 1), - ('AcousticTargetRpmThresholdMin', ctypes.c_uint16), - ('AcousticTargetRpmThresholdMax', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMin', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMax', ctypes.c_uint16), - ('PccLimitMin', ctypes.c_uint16), - ('PccLimitMax', ctypes.c_uint16), - ('FanStopTempMin', ctypes.c_uint16), - ('FanStopTempMax', ctypes.c_uint16), - ('FanStartTempMin', ctypes.c_uint16), - ('FanStartTempMax', ctypes.c_uint16), - ('PowerMinPpt0', ctypes.c_uint16 * 2), - ('Spare', ctypes.c_uint32 * 11), -] - -MsgLimits_t = struct_c__SA_MsgLimits_t -class struct_c__SA_DriverReportedClocks_t(Structure): - pass - -struct_c__SA_DriverReportedClocks_t._pack_ = 1 # source:False -struct_c__SA_DriverReportedClocks_t._fields_ = [ - ('BaseClockAc', ctypes.c_uint16), - ('GameClockAc', ctypes.c_uint16), - ('BoostClockAc', ctypes.c_uint16), - ('BaseClockDc', ctypes.c_uint16), - ('GameClockDc', ctypes.c_uint16), - ('BoostClockDc', ctypes.c_uint16), - ('Reserved', ctypes.c_uint32 * 4), -] - -DriverReportedClocks_t = struct_c__SA_DriverReportedClocks_t -class struct_c__SA_AvfsDcBtcParams_t(Structure): - pass - -struct_c__SA_AvfsDcBtcParams_t._pack_ = 1 # source:False -struct_c__SA_AvfsDcBtcParams_t._fields_ = [ - ('DcBtcEnabled', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('DcTol', ctypes.c_uint16), - ('DcBtcGb', ctypes.c_uint16), - ('DcBtcMin', ctypes.c_uint16), - ('DcBtcMax', ctypes.c_uint16), - ('DcBtcGbScalar', LinearInt_t), -] - -AvfsDcBtcParams_t = struct_c__SA_AvfsDcBtcParams_t -class struct_c__SA_AvfsFuseOverride_t(Structure): - pass - -struct_c__SA_AvfsFuseOverride_t._pack_ = 1 # source:False -struct_c__SA_AvfsFuseOverride_t._fields_ = [ - ('AvfsTemp', ctypes.c_uint16 * 2), - ('VftFMin', ctypes.c_uint16), - ('VInversion', ctypes.c_uint16), - ('qVft', struct_c__SA_QuadraticInt_t * 2), - ('qAvfsGb', QuadraticInt_t), - ('qAvfsGb2', QuadraticInt_t), -] - -AvfsFuseOverride_t = struct_c__SA_AvfsFuseOverride_t -class struct_c__SA_SkuTable_t(Structure): - pass - -struct_c__SA_SkuTable_t._pack_ = 1 # source:False -struct_c__SA_SkuTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('FeaturesToRun', ctypes.c_uint32 * 2), - ('TotalPowerConfig', ctypes.c_ubyte), - ('CustomerVariant', ctypes.c_ubyte), - ('MemoryTemperatureTypeMask', ctypes.c_ubyte), - ('SmartShiftVersion', ctypes.c_ubyte), - ('SocketPowerLimitAc', ctypes.c_uint16 * 4), - ('SocketPowerLimitDc', ctypes.c_uint16 * 4), - ('SocketPowerLimitSmartShift2', ctypes.c_uint16), - ('EnableLegacyPptLimit', ctypes.c_ubyte), - ('UseInputTelemetry', ctypes.c_ubyte), - ('SmartShiftMinReportedPptinDcs', ctypes.c_ubyte), - ('PaddingPpt', ctypes.c_ubyte * 1), - ('VrTdcLimit', ctypes.c_uint16 * 3), - ('PlatformTdcLimit', ctypes.c_uint16 * 3), - ('TemperatureLimit', ctypes.c_uint16 * 13), - ('HwCtfTempLimit', ctypes.c_uint16), - ('PaddingInfra', ctypes.c_uint16), - ('FitControllerFailureRateLimit', ctypes.c_uint32), - ('FitControllerGfxDutyCycle', ctypes.c_uint32), - ('FitControllerSocDutyCycle', ctypes.c_uint32), - ('FitControllerSocOffset', ctypes.c_uint32), - ('GfxApccPlusResidencyLimit', ctypes.c_uint32), - ('ThrottlerControlMask', ctypes.c_uint32), - ('FwDStateMask', ctypes.c_uint32), - ('UlvVoltageOffset', ctypes.c_uint16 * 2), - ('UlvVoltageOffsetU', ctypes.c_uint16), - ('DeepUlvVoltageOffsetSoc', ctypes.c_uint16), - ('DefaultMaxVoltage', ctypes.c_uint16 * 2), - ('BoostMaxVoltage', ctypes.c_uint16 * 2), - ('VminTempHystersis', ctypes.c_int16 * 2), - ('VminTempThreshold', ctypes.c_int16 * 2), - ('Vmin_Hot_T0', ctypes.c_uint16 * 2), - ('Vmin_Cold_T0', ctypes.c_uint16 * 2), - ('Vmin_Hot_Eol', ctypes.c_uint16 * 2), - ('Vmin_Cold_Eol', ctypes.c_uint16 * 2), - ('Vmin_Aging_Offset', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Hot', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Cold', ctypes.c_uint16 * 2), - ('VcBtcFixedVminAgingOffset', ctypes.c_uint16 * 2), - ('VcBtcVmin2PsmDegrationGb', ctypes.c_uint16 * 2), - ('VcBtcPsmA', ctypes.c_uint32 * 2), - ('VcBtcPsmB', ctypes.c_uint32 * 2), - ('VcBtcVminA', ctypes.c_uint32 * 2), - ('VcBtcVminB', ctypes.c_uint32 * 2), - ('PerPartVminEnabled', ctypes.c_ubyte * 2), - ('VcBtcEnabled', ctypes.c_ubyte * 2), - ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), - ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), - ('Vmin_droop', QuadraticInt_t), - ('SpareVmin', ctypes.c_uint32 * 9), - ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 13), - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 4), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint32 * 13), - ('Mp0clkFreq', ctypes.c_uint16 * 2), - ('Mp0DpmVoltage', ctypes.c_uint16 * 2), - ('GfxclkSpare', ctypes.c_ubyte * 2), - ('GfxclkFreqCap', ctypes.c_uint16), - ('GfxclkFgfxoffEntry', ctypes.c_uint16), - ('GfxclkFgfxoffExitImu', ctypes.c_uint16), - ('GfxclkFgfxoffExitRlc', ctypes.c_uint16), - ('GfxclkThrottleClock', ctypes.c_uint16), - ('EnableGfxPowerStagesGpio', ctypes.c_ubyte), - ('GfxIdlePadding', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivEn', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivVal', ctypes.c_ubyte), - ('GfxOffEntryEarlyMGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayVal', ctypes.c_ubyte), - ('GfxclkFreqGfxUlv', ctypes.c_uint16), - ('GfxIdlePadding2', ctypes.c_ubyte * 2), - ('GfxOffEntryHysteresis', ctypes.c_uint32), - ('GfxoffSpare', ctypes.c_uint32 * 15), - ('DfllBtcMasterScalerM', ctypes.c_uint32), - ('DfllBtcMasterScalerB', ctypes.c_int32), - ('DfllBtcSlaveScalerM', ctypes.c_uint32), - ('DfllBtcSlaveScalerB', ctypes.c_int32), - ('DfllPccAsWaitCtrl', ctypes.c_uint32), - ('DfllPccAsStepCtrl', ctypes.c_uint32), - ('DfllL2FrequencyBoostM', ctypes.c_uint32), - ('DfllL2FrequencyBoostB', ctypes.c_uint32), - ('GfxGpoSpare', ctypes.c_uint32 * 8), - ('DcsGfxOffVoltage', ctypes.c_uint16), - ('PaddingDcs', ctypes.c_uint16), - ('DcsMinGfxOffTime', ctypes.c_uint16), - ('DcsMaxGfxOffTime', ctypes.c_uint16), - ('DcsMinCreditAccum', ctypes.c_uint32), - ('DcsExitHysteresis', ctypes.c_uint16), - ('DcsTimeout', ctypes.c_uint16), - ('FoptEnabled', ctypes.c_ubyte), - ('DcsSpare2', ctypes.c_ubyte * 3), - ('DcsFoptM', ctypes.c_uint32), - ('DcsFoptB', ctypes.c_uint32), - ('DcsSpare', ctypes.c_uint32 * 11), - ('ShadowFreqTableUclk', ctypes.c_uint16 * 4), - ('UseStrobeModeOptimizations', ctypes.c_ubyte), - ('PaddingMem', ctypes.c_ubyte * 3), - ('UclkDpmPstates', ctypes.c_ubyte * 4), - ('FreqTableUclkDiv', ctypes.c_ubyte * 4), - ('MemVmempVoltage', ctypes.c_uint16 * 4), - ('MemVddioVoltage', ctypes.c_uint16 * 4), - ('FclkDpmUPstates', ctypes.c_ubyte * 8), - ('FclkDpmVddU', ctypes.c_uint16 * 8), - ('FclkDpmUSpeed', ctypes.c_uint16 * 8), - ('FclkDpmDisallowPstateFreq', ctypes.c_uint16), - ('PaddingFclk', ctypes.c_uint16), - ('PcieGenSpeed', ctypes.c_ubyte * 3), - ('PcieLaneCount', ctypes.c_ubyte * 3), - ('LclkFreq', ctypes.c_uint16 * 3), - ('FanStopTemp', ctypes.c_uint16 * 13), - ('FanStartTemp', ctypes.c_uint16 * 13), - ('FanGain', ctypes.c_uint16 * 13), - ('FanGainPadding', ctypes.c_uint16), - ('FanPwmMin', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanMaximumRpm', ctypes.c_uint16), - ('MGpuAcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetGfxclk', ctypes.c_uint16), - ('TempInputSelectMask', ctypes.c_uint32), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanTachEdgePerRev', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_uint16 * 13), - ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), - ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), - ('FuzzyFan_PwmSetDelta', ctypes.c_int16), - ('FuzzyFan_Reserved', ctypes.c_uint16), - ('FwCtfLimit', ctypes.c_uint16 * 13), - ('IntakeTempEnableRPM', ctypes.c_uint16), - ('IntakeTempOffsetTemp', ctypes.c_int16), - ('IntakeTempReleaseTemp', ctypes.c_uint16), - ('IntakeTempHighIntakeAcousticLimit', ctypes.c_uint16), - ('IntakeTempAcouticLimitReleaseRate', ctypes.c_uint16), - ('FanAbnormalTempLimitOffset', ctypes.c_int16), - ('FanStalledTriggerRpm', ctypes.c_uint16), - ('FanAbnormalTriggerRpmCoeff', ctypes.c_uint16), - ('FanAbnormalDetectionEnable', ctypes.c_uint16), - ('FanIntakeSensorSupport', ctypes.c_ubyte), - ('FanIntakePadding', ctypes.c_ubyte * 3), - ('FanSpare', ctypes.c_uint32 * 13), - ('OverrideGfxAvfsFuses', ctypes.c_ubyte), - ('GfxAvfsPadding', ctypes.c_ubyte * 3), - ('L2HwRtAvfsFuses', ctypes.c_uint32 * 32), - ('SeHwRtAvfsFuses', ctypes.c_uint32 * 32), - ('CommonRtAvfs', ctypes.c_uint32 * 13), - ('L2FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('SeFwRtAvfsFuses', ctypes.c_uint32 * 19), - ('Droop_PWL_F', ctypes.c_uint32 * 5), - ('Droop_PWL_a', ctypes.c_uint32 * 5), - ('Droop_PWL_b', ctypes.c_uint32 * 5), - ('Droop_PWL_c', ctypes.c_uint32 * 5), - ('Static_PWL_Offset', ctypes.c_uint32 * 5), - ('dGbV_dT_vmin', ctypes.c_uint32), - ('dGbV_dT_vmax', ctypes.c_uint32), - ('V2F_vmin_range_low', ctypes.c_uint32), - ('V2F_vmin_range_high', ctypes.c_uint32), - ('V2F_vmax_range_low', ctypes.c_uint32), - ('V2F_vmax_range_high', ctypes.c_uint32), - ('DcBtcGfxParams', AvfsDcBtcParams_t), - ('GfxAvfsSpare', ctypes.c_uint32 * 32), - ('OverrideSocAvfsFuses', ctypes.c_ubyte), - ('MinSocAvfsRevision', ctypes.c_ubyte), - ('SocAvfsPadding', ctypes.c_ubyte * 2), - ('SocAvfsFuseOverride', struct_c__SA_AvfsFuseOverride_t * 3), - ('dBtcGbSoc', struct_c__SA_DroopInt_t * 3), - ('qAgingGb', struct_c__SA_LinearInt_t * 3), - ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 3), - ('DcBtcSocParams', struct_c__SA_AvfsDcBtcParams_t * 3), - ('SocAvfsSpare', ctypes.c_uint32 * 32), - ('BootValues', BootValues_t), - ('DriverReportedClocks', DriverReportedClocks_t), - ('MsgLimits', MsgLimits_t), - ('OverDriveLimitsMin', OverDriveLimits_t), - ('OverDriveLimitsBasicMax', OverDriveLimits_t), - ('reserved', ctypes.c_uint32 * 22), - ('DebugOverrides', ctypes.c_uint32), - ('TotalBoardPowerSupport', ctypes.c_ubyte), - ('TotalBoardPowerPadding', ctypes.c_ubyte * 3), - ('TotalIdleBoardPowerM', ctypes.c_int16), - ('TotalIdleBoardPowerB', ctypes.c_int16), - ('TotalBoardPowerM', ctypes.c_int16), - ('TotalBoardPowerB', ctypes.c_int16), - ('qFeffCoeffGameClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBaseClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBoostClock', struct_c__SA_QuadraticInt_t * 2), - ('TemperatureLimit_Hynix', ctypes.c_uint16), - ('TemperatureLimit_Micron', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Hynix', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Micron', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 41), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SkuTable_t = struct_c__SA_SkuTable_t -class struct_c__SA_BoardTable_t(Structure): - pass - -struct_c__SA_BoardTable_t._pack_ = 1 # source:False -struct_c__SA_BoardTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), - ('VddGfxVrMapping', ctypes.c_ubyte), - ('VddSocVrMapping', ctypes.c_ubyte), - ('VddMem0VrMapping', ctypes.c_ubyte), - ('VddMem1VrMapping', ctypes.c_ubyte), - ('GfxUlvPhaseSheddingMask', ctypes.c_ubyte), - ('SocUlvPhaseSheddingMask', ctypes.c_ubyte), - ('VmempUlvPhaseSheddingMask', ctypes.c_ubyte), - ('VddioUlvPhaseSheddingMask', ctypes.c_ubyte), - ('SlaveAddrMapping', ctypes.c_ubyte * 5), - ('VrPsiSupport', ctypes.c_ubyte * 5), - ('PaddingPsi', ctypes.c_ubyte * 5), - ('EnablePsi6', ctypes.c_ubyte * 5), - ('SviTelemetryScale', struct_c__SA_SviTelemetryScale_t * 5), - ('VoltageTelemetryRatio', ctypes.c_uint32 * 5), - ('DownSlewRateVr', ctypes.c_ubyte * 5), - ('LedOffGpio', ctypes.c_ubyte), - ('FanOffGpio', ctypes.c_ubyte), - ('GfxVrPowerStageOffGpio', ctypes.c_ubyte), - ('AcDcGpio', ctypes.c_ubyte), - ('AcDcPolarity', ctypes.c_ubyte), - ('VR0HotGpio', ctypes.c_ubyte), - ('VR0HotPolarity', ctypes.c_ubyte), - ('GthrGpio', ctypes.c_ubyte), - ('GthrPolarity', ctypes.c_ubyte), - ('LedPin0', ctypes.c_ubyte), - ('LedPin1', ctypes.c_ubyte), - ('LedPin2', ctypes.c_ubyte), - ('LedEnableMask', ctypes.c_ubyte), - ('LedPcie', ctypes.c_ubyte), - ('LedError', ctypes.c_ubyte), - ('UclkTrainingModeSpreadPercent', ctypes.c_ubyte), - ('UclkSpreadPadding', ctypes.c_ubyte), - ('UclkSpreadFreq', ctypes.c_uint16), - ('UclkSpreadPercent', ctypes.c_ubyte * 16), - ('GfxclkSpreadEnable', ctypes.c_ubyte), - ('FclkSpreadPercent', ctypes.c_ubyte), - ('FclkSpreadFreq', ctypes.c_uint16), - ('DramWidth', ctypes.c_ubyte), - ('PaddingMem1', ctypes.c_ubyte * 7), - ('HsrEnabled', ctypes.c_ubyte), - ('VddqOffEnabled', ctypes.c_ubyte), - ('PaddingUmcFlags', ctypes.c_ubyte * 2), - ('PostVoltageSetBacoDelay', ctypes.c_uint32), - ('BacoEntryDelay', ctypes.c_uint32), - ('FuseWritePowerMuxPresent', ctypes.c_ubyte), - ('FuseWritePadding', ctypes.c_ubyte * 3), - ('BoardSpare', ctypes.c_uint32 * 63), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -BoardTable_t = struct_c__SA_BoardTable_t -class struct_c__SA_PPTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('SkuTable', SkuTable_t), - ('BoardTable', BoardTable_t), - ] - -PPTable_t = struct_c__SA_PPTable_t -class struct_c__SA_DriverSmuConfig_t(Structure): - pass - -struct_c__SA_DriverSmuConfig_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfig_t._fields_ = [ - ('GfxclkAverageLpfTau', ctypes.c_uint16), - ('FclkAverageLpfTau', ctypes.c_uint16), - ('UclkAverageLpfTau', ctypes.c_uint16), - ('GfxActivityLpfTau', ctypes.c_uint16), - ('UclkActivityLpfTau', ctypes.c_uint16), - ('SocketPowerLpfTau', ctypes.c_uint16), - ('VcnClkAverageLpfTau', ctypes.c_uint16), - ('VcnUsageAverageLpfTau', ctypes.c_uint16), -] - -DriverSmuConfig_t = struct_c__SA_DriverSmuConfig_t -class struct_c__SA_DriverSmuConfigExternal_t(Structure): - pass - -struct_c__SA_DriverSmuConfigExternal_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfigExternal_t._fields_ = [ - ('DriverSmuConfig', DriverSmuConfig_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverSmuConfigExternal_t = struct_c__SA_DriverSmuConfigExternal_t -class struct_c__SA_DriverInfoTable_t(Structure): - pass - -struct_c__SA_DriverInfoTable_t._pack_ = 1 # source:False -struct_c__SA_DriverInfoTable_t._fields_ = [ - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 4), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint16 * 13), - ('Padding', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 32), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverInfoTable_t = struct_c__SA_DriverInfoTable_t -class struct_c__SA_SmuMetrics_t(Structure): - pass - -struct_c__SA_SmuMetrics_t._pack_ = 1 # source:False -struct_c__SA_SmuMetrics_t._fields_ = [ - ('CurrClock', ctypes.c_uint32 * 13), - ('AverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('AverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('AverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('AverageFclkFrequencyPreDs', ctypes.c_uint16), - ('AverageFclkFrequencyPostDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('AverageVclk0Frequency', ctypes.c_uint16), - ('AverageDclk0Frequency', ctypes.c_uint16), - ('AverageVclk1Frequency', ctypes.c_uint16), - ('AverageDclk1Frequency', ctypes.c_uint16), - ('PCIeBusy', ctypes.c_uint16), - ('dGPU_W_MAX', ctypes.c_uint16), - ('padding', ctypes.c_uint16), - ('MetricsCounter', ctypes.c_uint32), - ('AvgVoltage', ctypes.c_uint16 * 5), - ('AvgCurrent', ctypes.c_uint16 * 5), - ('AverageGfxActivity', ctypes.c_uint16), - ('AverageUclkActivity', ctypes.c_uint16), - ('Vcn0ActivityPercentage', ctypes.c_uint16), - ('Vcn1ActivityPercentage', ctypes.c_uint16), - ('EnergyAccumulator', ctypes.c_uint32), - ('AverageSocketPower', ctypes.c_uint16), - ('AverageTotalBoardPower', ctypes.c_uint16), - ('AvgTemperature', ctypes.c_uint16 * 13), - ('AvgTemperatureFanIntake', ctypes.c_uint16), - ('PcieRate', ctypes.c_ubyte), - ('PcieWidth', ctypes.c_ubyte), - ('AvgFanPwm', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 1), - ('AvgFanRpm', ctypes.c_uint16), - ('ThrottlingPercentage', ctypes.c_ubyte * 22), - ('VmaxThrottlingPercentage', ctypes.c_ubyte), - ('Padding1', ctypes.c_ubyte * 3), - ('D3HotEntryCountPerMode', ctypes.c_uint32 * 4), - ('D3HotExitCountPerMode', ctypes.c_uint32 * 4), - ('ArmMsgReceivedCountPerMode', ctypes.c_uint32 * 4), - ('ApuSTAPMSmartShiftLimit', ctypes.c_uint16), - ('ApuSTAPMLimit', ctypes.c_uint16), - ('AvgApuSocketPower', ctypes.c_uint16), - ('AverageUclkActivity_MAX', ctypes.c_uint16), - ('PublicSerialNumberLower', ctypes.c_uint32), - ('PublicSerialNumberUpper', ctypes.c_uint32), -] - -SmuMetrics_t = struct_c__SA_SmuMetrics_t -class struct_c__SA_SmuMetricsExternal_t(Structure): - pass - -struct_c__SA_SmuMetricsExternal_t._pack_ = 1 # source:False -struct_c__SA_SmuMetricsExternal_t._fields_ = [ - ('SmuMetrics', SmuMetrics_t), - ('Spare', ctypes.c_uint32 * 29), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SmuMetricsExternal_t = struct_c__SA_SmuMetricsExternal_t -class struct_c__SA_WatermarkRowGeneric_t(Structure): - pass - -struct_c__SA_WatermarkRowGeneric_t._pack_ = 1 # source:False -struct_c__SA_WatermarkRowGeneric_t._fields_ = [ - ('WmSetting', ctypes.c_ubyte), - ('Flags', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 2), -] - -WatermarkRowGeneric_t = struct_c__SA_WatermarkRowGeneric_t - -# values for enumeration 'c__EA_WATERMARKS_FLAGS_e' -c__EA_WATERMARKS_FLAGS_e__enumvalues = { - 0: 'WATERMARKS_CLOCK_RANGE', - 1: 'WATERMARKS_DUMMY_PSTATE', - 2: 'WATERMARKS_MALL', - 3: 'WATERMARKS_COUNT', -} -WATERMARKS_CLOCK_RANGE = 0 -WATERMARKS_DUMMY_PSTATE = 1 -WATERMARKS_MALL = 2 -WATERMARKS_COUNT = 3 -c__EA_WATERMARKS_FLAGS_e = ctypes.c_uint32 # enum -WATERMARKS_FLAGS_e = c__EA_WATERMARKS_FLAGS_e -WATERMARKS_FLAGS_e__enumvalues = c__EA_WATERMARKS_FLAGS_e__enumvalues -class struct_c__SA_Watermarks_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('WatermarkRow', struct_c__SA_WatermarkRowGeneric_t * 4), - ] - -Watermarks_t = struct_c__SA_Watermarks_t -class struct_c__SA_WatermarksExternal_t(Structure): - pass - -struct_c__SA_WatermarksExternal_t._pack_ = 1 # source:False -struct_c__SA_WatermarksExternal_t._fields_ = [ - ('Watermarks', Watermarks_t), - ('Spare', ctypes.c_uint32 * 16), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -WatermarksExternal_t = struct_c__SA_WatermarksExternal_t -class struct_c__SA_AvfsDebugTable_t(Structure): - pass - -struct_c__SA_AvfsDebugTable_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTable_t._fields_ = [ - ('avgPsmCount', ctypes.c_uint16 * 214), - ('minPsmCount', ctypes.c_uint16 * 214), - ('avgPsmVoltage', ctypes.c_float * 214), - ('minPsmVoltage', ctypes.c_float * 214), -] - -AvfsDebugTable_t = struct_c__SA_AvfsDebugTable_t -class struct_c__SA_AvfsDebugTableExternal_t(Structure): - pass - -struct_c__SA_AvfsDebugTableExternal_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTableExternal_t._fields_ = [ - ('AvfsDebugTable', AvfsDebugTable_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -AvfsDebugTableExternal_t = struct_c__SA_AvfsDebugTableExternal_t -class struct_c__SA_DpmActivityMonitorCoeffInt_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffInt_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffInt_t._fields_ = [ - ('Gfx_ActiveHystLimit', ctypes.c_ubyte), - ('Gfx_IdleHystLimit', ctypes.c_ubyte), - ('Gfx_FPS', ctypes.c_ubyte), - ('Gfx_MinActiveFreqType', ctypes.c_ubyte), - ('Gfx_BoosterFreqType', ctypes.c_ubyte), - ('PaddingGfx', ctypes.c_ubyte), - ('Gfx_MinActiveFreq', ctypes.c_uint16), - ('Gfx_BoosterFreq', ctypes.c_uint16), - ('Gfx_PD_Data_time_constant', ctypes.c_uint16), - ('Gfx_PD_Data_limit_a', ctypes.c_uint32), - ('Gfx_PD_Data_limit_b', ctypes.c_uint32), - ('Gfx_PD_Data_limit_c', ctypes.c_uint32), - ('Gfx_PD_Data_error_coeff', ctypes.c_uint32), - ('Gfx_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Fclk_ActiveHystLimit', ctypes.c_ubyte), - ('Fclk_IdleHystLimit', ctypes.c_ubyte), - ('Fclk_FPS', ctypes.c_ubyte), - ('Fclk_MinActiveFreqType', ctypes.c_ubyte), - ('Fclk_BoosterFreqType', ctypes.c_ubyte), - ('PaddingFclk', ctypes.c_ubyte), - ('Fclk_MinActiveFreq', ctypes.c_uint16), - ('Fclk_BoosterFreq', ctypes.c_uint16), - ('Fclk_PD_Data_time_constant', ctypes.c_uint16), - ('Fclk_PD_Data_limit_a', ctypes.c_uint32), - ('Fclk_PD_Data_limit_b', ctypes.c_uint32), - ('Fclk_PD_Data_limit_c', ctypes.c_uint32), - ('Fclk_PD_Data_error_coeff', ctypes.c_uint32), - ('Fclk_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Mem_UpThreshold_Limit', ctypes.c_uint32 * 4), - ('Mem_UpHystLimit', ctypes.c_ubyte * 4), - ('Mem_DownHystLimit', ctypes.c_ubyte * 4), - ('Mem_Fps', ctypes.c_uint16), - ('padding', ctypes.c_ubyte * 2), -] - -DpmActivityMonitorCoeffInt_t = struct_c__SA_DpmActivityMonitorCoeffInt_t -class struct_c__SA_DpmActivityMonitorCoeffIntExternal_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._fields_ = [ - ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DpmActivityMonitorCoeffIntExternal_t = struct_c__SA_DpmActivityMonitorCoeffIntExternal_t -__AMDGPU_SMU_H__ = True # macro -u32 = True # macro -SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 # macro -SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 # macro -SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 # macro -SMU_FW_NAME_LEN = 0x24 # macro -SMU_DPM_USER_PROFILE_RESTORE = (1<<0) # macro -SMU_CUSTOM_FAN_SPEED_RPM = (1<<1) # macro -SMU_CUSTOM_FAN_SPEED_PWM = (1<<2) # macro -SMU_THROTTLER_PPT0_BIT = 0 # macro -SMU_THROTTLER_PPT1_BIT = 1 # macro -SMU_THROTTLER_PPT2_BIT = 2 # macro -SMU_THROTTLER_PPT3_BIT = 3 # macro -SMU_THROTTLER_SPL_BIT = 4 # macro -SMU_THROTTLER_FPPT_BIT = 5 # macro -SMU_THROTTLER_SPPT_BIT = 6 # macro -SMU_THROTTLER_SPPT_APU_BIT = 7 # macro -SMU_THROTTLER_TDC_GFX_BIT = 16 # macro -SMU_THROTTLER_TDC_SOC_BIT = 17 # macro -SMU_THROTTLER_TDC_MEM_BIT = 18 # macro -SMU_THROTTLER_TDC_VDD_BIT = 19 # macro -SMU_THROTTLER_TDC_CVIP_BIT = 20 # macro -SMU_THROTTLER_EDC_CPU_BIT = 21 # macro -SMU_THROTTLER_EDC_GFX_BIT = 22 # macro -SMU_THROTTLER_APCC_BIT = 23 # macro -SMU_THROTTLER_TEMP_GPU_BIT = 32 # macro -SMU_THROTTLER_TEMP_CORE_BIT = 33 # macro -SMU_THROTTLER_TEMP_MEM_BIT = 34 # macro -SMU_THROTTLER_TEMP_EDGE_BIT = 35 # macro -SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 # macro -SMU_THROTTLER_TEMP_SOC_BIT = 37 # macro -SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 # macro -SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 # macro -SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 # macro -SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 # macro -SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 # macro -SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 # macro -SMU_THROTTLER_VRHOT0_BIT = 44 # macro -SMU_THROTTLER_VRHOT1_BIT = 45 # macro -SMU_THROTTLER_PROCHOT_CPU_BIT = 46 # macro -SMU_THROTTLER_PROCHOT_GFX_BIT = 47 # macro -SMU_THROTTLER_PPM_BIT = 56 # macro -SMU_THROTTLER_FIT_BIT = 57 # macro -# def SMU_TABLE_INIT(tables, table_id, s, a, d): # macro -# return {tables[table_id].size=s;tables[table_id].align=a;tables[table_id].domain=d;}(0) -class struct_smu_hw_power_state(Structure): - pass - -struct_smu_hw_power_state._pack_ = 1 # source:False -struct_smu_hw_power_state._fields_ = [ - ('magic', ctypes.c_uint32), -] - -class struct_smu_power_state(Structure): - pass - - -# values for enumeration 'smu_state_ui_label' -smu_state_ui_label__enumvalues = { - 0: 'SMU_STATE_UI_LABEL_NONE', - 1: 'SMU_STATE_UI_LABEL_BATTERY', - 2: 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 3: 'SMU_STATE_UI_LABEL_BALLANCED', - 4: 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', - 5: 'SMU_STATE_UI_LABEL_PERFORMANCE', - 6: 'SMU_STATE_UI_LABEL_BACO', -} -SMU_STATE_UI_LABEL_NONE = 0 -SMU_STATE_UI_LABEL_BATTERY = 1 -SMU_STATE_UI_TABEL_MIDDLE_LOW = 2 -SMU_STATE_UI_LABEL_BALLANCED = 3 -SMU_STATE_UI_LABEL_MIDDLE_HIGHT = 4 -SMU_STATE_UI_LABEL_PERFORMANCE = 5 -SMU_STATE_UI_LABEL_BACO = 6 -smu_state_ui_label = ctypes.c_uint32 # enum - -# values for enumeration 'smu_state_classification_flag' -smu_state_classification_flag__enumvalues = { - 1: 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 2: 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 4: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 8: 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 16: 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 32: 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 64: 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 128: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 256: 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 512: 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 1024: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 2048: 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 4096: 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 8192: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 16384: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', - 32768: 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 65536: 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 131072: 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 262144: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 524288: 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 1048576: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', -} -SMU_STATE_CLASSIFICATION_FLAG_BOOT = 1 -SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 2 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 4 -SMU_STATE_CLASSIFICATION_FLAG_RESET = 8 -SMU_STATE_CLASSIFICATION_FLAG_FORCED = 16 -SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 32 -SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 64 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 128 -SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 256 -SMU_STATE_CLASSIFICATION_FLAG_UVD = 512 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 1024 -SMU_STATE_CLASSIFICATION_FLAG_ACPI = 2048 -SMU_STATE_CLASSIFICATION_FLAG_HD2 = 4096 -SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 8192 -SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 16384 -SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 32768 -SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 65536 -SMU_STATE_CLASSIFICATION_FLAG_BACO = 131072 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 262144 -SMU_STATE_CLASSIFICATION_FLAG_ULV = 524288 -SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 1048576 -smu_state_classification_flag = ctypes.c_uint32 # enum -class struct_smu_state_classification_block(Structure): - pass - -struct_smu_state_classification_block._pack_ = 1 # source:False -struct_smu_state_classification_block._fields_ = [ - ('ui_label', smu_state_ui_label), - ('flags', smu_state_classification_flag), - ('bios_index', ctypes.c_int32), - ('temporary_state', ctypes.c_bool), - ('to_be_deleted', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_smu_state_pcie_block(Structure): - pass - -struct_smu_state_pcie_block._pack_ = 1 # source:False -struct_smu_state_pcie_block._fields_ = [ - ('lanes', ctypes.c_uint32), -] - - -# values for enumeration 'smu_refreshrate_source' -smu_refreshrate_source__enumvalues = { - 0: 'SMU_REFRESHRATE_SOURCE_EDID', - 1: 'SMU_REFRESHRATE_SOURCE_EXPLICIT', -} -SMU_REFRESHRATE_SOURCE_EDID = 0 -SMU_REFRESHRATE_SOURCE_EXPLICIT = 1 -smu_refreshrate_source = ctypes.c_uint32 # enum -class struct_smu_state_display_block(Structure): - pass - -struct_smu_state_display_block._pack_ = 1 # source:False -struct_smu_state_display_block._fields_ = [ - ('disable_frame_modulation', ctypes.c_bool), - ('limit_refreshrate', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), - ('refreshrate_source', smu_refreshrate_source), - ('explicit_refreshrate', ctypes.c_int32), - ('edid_refreshrate_index', ctypes.c_int32), - ('enable_vari_bright', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -class struct_smu_state_memory_block(Structure): - pass - -struct_smu_state_memory_block._pack_ = 1 # source:False -struct_smu_state_memory_block._fields_ = [ - ('dll_off', ctypes.c_bool), - ('m3arb', ctypes.c_ubyte), - ('unused', ctypes.c_ubyte * 3), -] - -class struct_smu_state_software_algorithm_block(Structure): - pass - -struct_smu_state_software_algorithm_block._pack_ = 1 # source:False -struct_smu_state_software_algorithm_block._fields_ = [ - ('disable_load_balancing', ctypes.c_bool), - ('enable_sleep_for_timestamps', ctypes.c_bool), -] - -class struct_smu_temperature_range(Structure): - pass - -struct_smu_temperature_range._pack_ = 1 # source:False -struct_smu_temperature_range._fields_ = [ - ('min', ctypes.c_int32), - ('max', ctypes.c_int32), - ('edge_emergency_max', ctypes.c_int32), - ('hotspot_min', ctypes.c_int32), - ('hotspot_crit_max', ctypes.c_int32), - ('hotspot_emergency_max', ctypes.c_int32), - ('mem_min', ctypes.c_int32), - ('mem_crit_max', ctypes.c_int32), - ('mem_emergency_max', ctypes.c_int32), - ('software_shutdown_temp', ctypes.c_int32), - ('software_shutdown_temp_offset', ctypes.c_int32), -] - -class struct_smu_state_validation_block(Structure): - pass - -struct_smu_state_validation_block._pack_ = 1 # source:False -struct_smu_state_validation_block._fields_ = [ - ('single_display_only', ctypes.c_bool), - ('disallow_on_dc', ctypes.c_bool), - ('supported_power_levels', ctypes.c_ubyte), -] - -class struct_smu_uvd_clocks(Structure): - pass - -struct_smu_uvd_clocks._pack_ = 1 # source:False -struct_smu_uvd_clocks._fields_ = [ - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), -] - - -# values for enumeration 'smu_power_src_type' -smu_power_src_type__enumvalues = { - 0: 'SMU_POWER_SOURCE_AC', - 1: 'SMU_POWER_SOURCE_DC', - 2: 'SMU_POWER_SOURCE_COUNT', -} -SMU_POWER_SOURCE_AC = 0 -SMU_POWER_SOURCE_DC = 1 -SMU_POWER_SOURCE_COUNT = 2 -smu_power_src_type = ctypes.c_uint32 # enum - -# values for enumeration 'smu_ppt_limit_type' -smu_ppt_limit_type__enumvalues = { - 0: 'SMU_DEFAULT_PPT_LIMIT', - 1: 'SMU_FAST_PPT_LIMIT', -} -SMU_DEFAULT_PPT_LIMIT = 0 -SMU_FAST_PPT_LIMIT = 1 -smu_ppt_limit_type = ctypes.c_uint32 # enum - -# values for enumeration 'smu_ppt_limit_level' -smu_ppt_limit_level__enumvalues = { - -1: 'SMU_PPT_LIMIT_MIN', - 0: 'SMU_PPT_LIMIT_CURRENT', - 1: 'SMU_PPT_LIMIT_DEFAULT', - 2: 'SMU_PPT_LIMIT_MAX', -} -SMU_PPT_LIMIT_MIN = -1 -SMU_PPT_LIMIT_CURRENT = 0 -SMU_PPT_LIMIT_DEFAULT = 1 -SMU_PPT_LIMIT_MAX = 2 -smu_ppt_limit_level = ctypes.c_int32 # enum - -# values for enumeration 'smu_memory_pool_size' -smu_memory_pool_size__enumvalues = { - 0: 'SMU_MEMORY_POOL_SIZE_ZERO', - 268435456: 'SMU_MEMORY_POOL_SIZE_256_MB', - 536870912: 'SMU_MEMORY_POOL_SIZE_512_MB', - 1073741824: 'SMU_MEMORY_POOL_SIZE_1_GB', - 2147483648: 'SMU_MEMORY_POOL_SIZE_2_GB', -} -SMU_MEMORY_POOL_SIZE_ZERO = 0 -SMU_MEMORY_POOL_SIZE_256_MB = 268435456 -SMU_MEMORY_POOL_SIZE_512_MB = 536870912 -SMU_MEMORY_POOL_SIZE_1_GB = 1073741824 -SMU_MEMORY_POOL_SIZE_2_GB = 2147483648 -smu_memory_pool_size = ctypes.c_uint32 # enum - -# values for enumeration 'smu_clk_type' -smu_clk_type__enumvalues = { - 0: 'SMU_GFXCLK', - 1: 'SMU_VCLK', - 2: 'SMU_DCLK', - 3: 'SMU_VCLK1', - 4: 'SMU_DCLK1', - 5: 'SMU_ECLK', - 6: 'SMU_SOCCLK', - 7: 'SMU_UCLK', - 8: 'SMU_DCEFCLK', - 9: 'SMU_DISPCLK', - 10: 'SMU_PIXCLK', - 11: 'SMU_PHYCLK', - 12: 'SMU_FCLK', - 13: 'SMU_SCLK', - 14: 'SMU_MCLK', - 15: 'SMU_PCIE', - 16: 'SMU_LCLK', - 17: 'SMU_OD_CCLK', - 18: 'SMU_OD_SCLK', - 19: 'SMU_OD_MCLK', - 20: 'SMU_OD_VDDC_CURVE', - 21: 'SMU_OD_RANGE', - 22: 'SMU_OD_VDDGFX_OFFSET', - 23: 'SMU_OD_FAN_CURVE', - 24: 'SMU_OD_ACOUSTIC_LIMIT', - 25: 'SMU_OD_ACOUSTIC_TARGET', - 26: 'SMU_OD_FAN_TARGET_TEMPERATURE', - 27: 'SMU_OD_FAN_MINIMUM_PWM', - 28: 'SMU_CLK_COUNT', -} -SMU_GFXCLK = 0 -SMU_VCLK = 1 -SMU_DCLK = 2 -SMU_VCLK1 = 3 -SMU_DCLK1 = 4 -SMU_ECLK = 5 -SMU_SOCCLK = 6 -SMU_UCLK = 7 -SMU_DCEFCLK = 8 -SMU_DISPCLK = 9 -SMU_PIXCLK = 10 -SMU_PHYCLK = 11 -SMU_FCLK = 12 -SMU_SCLK = 13 -SMU_MCLK = 14 -SMU_PCIE = 15 -SMU_LCLK = 16 -SMU_OD_CCLK = 17 -SMU_OD_SCLK = 18 -SMU_OD_MCLK = 19 -SMU_OD_VDDC_CURVE = 20 -SMU_OD_RANGE = 21 -SMU_OD_VDDGFX_OFFSET = 22 -SMU_OD_FAN_CURVE = 23 -SMU_OD_ACOUSTIC_LIMIT = 24 -SMU_OD_ACOUSTIC_TARGET = 25 -SMU_OD_FAN_TARGET_TEMPERATURE = 26 -SMU_OD_FAN_MINIMUM_PWM = 27 -SMU_CLK_COUNT = 28 -smu_clk_type = ctypes.c_uint32 # enum -class struct_smu_user_dpm_profile(Structure): - pass - -struct_smu_user_dpm_profile._pack_ = 1 # source:False -struct_smu_user_dpm_profile._fields_ = [ - ('fan_mode', ctypes.c_uint32), - ('power_limit', ctypes.c_uint32), - ('fan_speed_pwm', ctypes.c_uint32), - ('fan_speed_rpm', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('user_od', ctypes.c_uint32), - ('clk_mask', ctypes.c_uint32 * 28), - ('clk_dependency', ctypes.c_uint32), -] - -class struct_smu_table(Structure): - pass - -class struct_amdgpu_bo(Structure): - pass - -struct_smu_table._pack_ = 1 # source:False -struct_smu_table._fields_ = [ - ('size', ctypes.c_uint64), - ('align', ctypes.c_uint32), - ('domain', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('mc_address', ctypes.c_uint64), - ('cpu_addr', ctypes.POINTER(None)), - ('bo', ctypes.POINTER(struct_amdgpu_bo)), - ('version', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'smu_perf_level_designation' -smu_perf_level_designation__enumvalues = { - 0: 'PERF_LEVEL_ACTIVITY', - 1: 'PERF_LEVEL_POWER_CONTAINMENT', -} -PERF_LEVEL_ACTIVITY = 0 -PERF_LEVEL_POWER_CONTAINMENT = 1 -smu_perf_level_designation = ctypes.c_uint32 # enum -class struct_smu_performance_level(Structure): - pass - -struct_smu_performance_level._pack_ = 1 # source:False -struct_smu_performance_level._fields_ = [ - ('core_clock', ctypes.c_uint32), - ('memory_clock', ctypes.c_uint32), - ('vddc', ctypes.c_uint32), - ('vddci', ctypes.c_uint32), - ('non_local_mem_freq', ctypes.c_uint32), - ('non_local_mem_width', ctypes.c_uint32), -] - -class struct_smu_clock_info(Structure): - pass - -struct_smu_clock_info._pack_ = 1 # source:False -struct_smu_clock_info._fields_ = [ - ('min_mem_clk', ctypes.c_uint32), - ('max_mem_clk', ctypes.c_uint32), - ('min_eng_clk', ctypes.c_uint32), - ('max_eng_clk', ctypes.c_uint32), - ('min_bus_bandwidth', ctypes.c_uint32), - ('max_bus_bandwidth', ctypes.c_uint32), -] - -class struct_smu_bios_boot_up_values(Structure): - pass - -struct_smu_bios_boot_up_values._pack_ = 1 # source:False -struct_smu_bios_boot_up_values._fields_ = [ - ('revision', ctypes.c_uint32), - ('gfxclk', ctypes.c_uint32), - ('uclk', ctypes.c_uint32), - ('socclk', ctypes.c_uint32), - ('dcefclk', ctypes.c_uint32), - ('eclk', ctypes.c_uint32), - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), - ('vddc', ctypes.c_uint16), - ('vddci', ctypes.c_uint16), - ('mvddc', ctypes.c_uint16), - ('vdd_gfx', ctypes.c_uint16), - ('cooling_id', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pp_table_id', ctypes.c_uint32), - ('format_revision', ctypes.c_uint32), - ('content_revision', ctypes.c_uint32), - ('fclk', ctypes.c_uint32), - ('lclk', ctypes.c_uint32), - ('firmware_caps', ctypes.c_uint32), -] - - -# values for enumeration 'smu_table_id' -smu_table_id__enumvalues = { - 0: 'SMU_TABLE_PPTABLE', - 1: 'SMU_TABLE_WATERMARKS', - 2: 'SMU_TABLE_CUSTOM_DPM', - 3: 'SMU_TABLE_DPMCLOCKS', - 4: 'SMU_TABLE_AVFS', - 5: 'SMU_TABLE_AVFS_PSM_DEBUG', - 6: 'SMU_TABLE_AVFS_FUSE_OVERRIDE', - 7: 'SMU_TABLE_PMSTATUSLOG', - 8: 'SMU_TABLE_SMU_METRICS', - 9: 'SMU_TABLE_DRIVER_SMU_CONFIG', - 10: 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', - 11: 'SMU_TABLE_OVERDRIVE', - 12: 'SMU_TABLE_I2C_COMMANDS', - 13: 'SMU_TABLE_PACE', - 14: 'SMU_TABLE_ECCINFO', - 15: 'SMU_TABLE_COMBO_PPTABLE', - 16: 'SMU_TABLE_WIFIBAND', - 17: 'SMU_TABLE_COUNT', -} -SMU_TABLE_PPTABLE = 0 -SMU_TABLE_WATERMARKS = 1 -SMU_TABLE_CUSTOM_DPM = 2 -SMU_TABLE_DPMCLOCKS = 3 -SMU_TABLE_AVFS = 4 -SMU_TABLE_AVFS_PSM_DEBUG = 5 -SMU_TABLE_AVFS_FUSE_OVERRIDE = 6 -SMU_TABLE_PMSTATUSLOG = 7 -SMU_TABLE_SMU_METRICS = 8 -SMU_TABLE_DRIVER_SMU_CONFIG = 9 -SMU_TABLE_ACTIVITY_MONITOR_COEFF = 10 -SMU_TABLE_OVERDRIVE = 11 -SMU_TABLE_I2C_COMMANDS = 12 -SMU_TABLE_PACE = 13 -SMU_TABLE_ECCINFO = 14 -SMU_TABLE_COMBO_PPTABLE = 15 -SMU_TABLE_WIFIBAND = 16 -SMU_TABLE_COUNT = 17 -smu_table_id = ctypes.c_uint32 # enum -__all__ = \ - ['ALLOWED_FEATURE_CTRL_DEFAULT', 'ALLOWED_FEATURE_CTRL_SCPM', - 'AVFS_D_COUNT', 'AVFS_D_G', 'AVFS_D_M_B', 'AVFS_D_M_S', - 'AVFS_D_e', 'AVFS_D_e__enumvalues', 'AVFS_TEMP_COLD', - 'AVFS_TEMP_COUNT', 'AVFS_TEMP_HOT', 'AVFS_TEMP_e', - 'AVFS_TEMP_e__enumvalues', 'AVFS_VOLTAGE_COUNT', - 'AVFS_VOLTAGE_GFX', 'AVFS_VOLTAGE_SOC', 'AVFS_VOLTAGE_TYPE_e', - 'AVFS_VOLTAGE_TYPE_e__enumvalues', 'AvfsDcBtcParams_t', - 'AvfsDebugTableExternal_t', 'AvfsDebugTable_t', - 'AvfsFuseOverride_t', 'BACO_SEQUENCE', 'BAMACO_SEQUENCE', - 'BOARD_GPIO_DC_GENLK_CLK', 'BOARD_GPIO_DC_GENLK_VSYNC', - 'BOARD_GPIO_DC_GEN_A', 'BOARD_GPIO_DC_GEN_B', - 'BOARD_GPIO_DC_GEN_C', 'BOARD_GPIO_DC_GEN_D', - 'BOARD_GPIO_DC_GEN_E', 'BOARD_GPIO_DC_GEN_F', - 'BOARD_GPIO_DC_GEN_G', 'BOARD_GPIO_DC_SWAPLOCK_A', - 'BOARD_GPIO_DC_SWAPLOCK_B', 'BOARD_GPIO_SMUIO_0', - 'BOARD_GPIO_SMUIO_1', 'BOARD_GPIO_SMUIO_10', - 'BOARD_GPIO_SMUIO_11', 'BOARD_GPIO_SMUIO_12', - 'BOARD_GPIO_SMUIO_13', 'BOARD_GPIO_SMUIO_14', - 'BOARD_GPIO_SMUIO_15', 'BOARD_GPIO_SMUIO_16', - 'BOARD_GPIO_SMUIO_17', 'BOARD_GPIO_SMUIO_18', - 'BOARD_GPIO_SMUIO_19', 'BOARD_GPIO_SMUIO_2', - 'BOARD_GPIO_SMUIO_20', 'BOARD_GPIO_SMUIO_21', - 'BOARD_GPIO_SMUIO_22', 'BOARD_GPIO_SMUIO_23', - 'BOARD_GPIO_SMUIO_24', 'BOARD_GPIO_SMUIO_25', - 'BOARD_GPIO_SMUIO_26', 'BOARD_GPIO_SMUIO_27', - 'BOARD_GPIO_SMUIO_28', 'BOARD_GPIO_SMUIO_29', - 'BOARD_GPIO_SMUIO_3', 'BOARD_GPIO_SMUIO_30', - 'BOARD_GPIO_SMUIO_31', 'BOARD_GPIO_SMUIO_4', 'BOARD_GPIO_SMUIO_5', - 'BOARD_GPIO_SMUIO_6', 'BOARD_GPIO_SMUIO_7', 'BOARD_GPIO_SMUIO_8', - 'BOARD_GPIO_SMUIO_9', 'BOARD_GPIO_TYPE_e', - 'BOARD_GPIO_TYPE_e__enumvalues', 'BoardTable_t', 'BootValues_t', - 'CMDCONFIG_READWRITE_BIT', 'CMDCONFIG_READWRITE_MASK', - 'CMDCONFIG_RESTART_BIT', 'CMDCONFIG_RESTART_MASK', - 'CMDCONFIG_STOP_BIT', 'CMDCONFIG_STOP_MASK', - 'CUSTOMER_VARIANT_COUNT', 'CUSTOMER_VARIANT_FALCON', - 'CUSTOMER_VARIANT_ROW', 'CUSTOMER_VARIANT_e', - 'CUSTOMER_VARIANT_e__enumvalues', 'D3HOTSequence_e', - 'D3HOTSequence_e__enumvalues', 'D3HOT_SEQUENCE_COUNT', - 'DCS_ARCH_ASYNC', 'DCS_ARCH_DISABLED', 'DCS_ARCH_FADCS', - 'DCS_ARCH_e', 'DCS_ARCH_e__enumvalues', - 'DEBUGSMC_MSG_DebugDumpExit', 'DEBUGSMC_MSG_GetDebugData', - 'DEBUGSMC_MSG_TestMessage', 'DEBUGSMC_Message_Count', - 'DEBUGSMC_VERSION', 'DEBUG_OVERRIDE_DFLL_MASTER_MODE', - 'DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK', - 'DEBUG_OVERRIDE_DISABLE_DFLL', - 'DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER', - 'DEBUG_OVERRIDE_DISABLE_FMAX_VMAX', - 'DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS', - 'DEBUG_OVERRIDE_DISABLE_VCN_PG', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK', - 'DEBUG_OVERRIDE_ENABLE_PROFILING_MODE', - 'DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE', - 'DRAM_BIT_WIDTH_COUNT', 'DRAM_BIT_WIDTH_DISABLED', - 'DRAM_BIT_WIDTH_TYPE_e', 'DRAM_BIT_WIDTH_TYPE_e__enumvalues', - 'DRAM_BIT_WIDTH_X_128', 'DRAM_BIT_WIDTH_X_16', - 'DRAM_BIT_WIDTH_X_32', 'DRAM_BIT_WIDTH_X_64', - 'DRAM_BIT_WIDTH_X_8', 'DpmActivityMonitorCoeffIntExternal_t', - 'DpmActivityMonitorCoeffInt_t', 'DpmDescriptor_t', - 'DriverInfoTable_t', 'DriverReportedClocks_t', - 'DriverSmuConfigExternal_t', 'DriverSmuConfig_t', 'DroopInt_t', - 'EccInfoTable_t', 'EccInfo_t', 'FAN_MODE_AUTO', - 'FAN_MODE_MANUAL_LINEAR', 'FEATURE_ACDC_BIT', - 'FEATURE_ATHUB_MMHUB_PG_BIT', 'FEATURE_BACO_BIT', - 'FEATURE_BACO_CG_BIT', 'FEATURE_BACO_MPCLK_DS_BIT', - 'FEATURE_BOMXCO_SVI3_PROG_BIT', 'FEATURE_BOOT_POWER_OPT_BIT', - 'FEATURE_BOOT_TIME_CAL_BIT', - 'FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT', 'FEATURE_DF_CSTATE_BIT', - 'FEATURE_DPM_DCN_BIT', 'FEATURE_DPM_FCLK_BIT', - 'FEATURE_DPM_GFXCLK_BIT', 'FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT', - 'FEATURE_DPM_LINK_BIT', 'FEATURE_DPM_MP0CLK_BIT', - 'FEATURE_DPM_SOCCLK_BIT', 'FEATURE_DPM_UCLK_BIT', - 'FEATURE_DS_DCFCLK_BIT', 'FEATURE_DS_FCLK_BIT', - 'FEATURE_DS_GFXCLK_BIT', 'FEATURE_DS_LCLK_BIT', - 'FEATURE_DS_SOCCLK_BIT', 'FEATURE_DS_UCLK_BIT', - 'FEATURE_DS_VCN_BIT', 'FEATURE_EDC_PWRBRK_BIT', - 'FEATURE_FAN_CONTROL_BIT', 'FEATURE_FW_CTF_BIT', - 'FEATURE_FW_DATA_READ_BIT', 'FEATURE_FW_DSTATE_BIT', - 'FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT', 'FEATURE_GFXOFF_BIT', - 'FEATURE_GFX_DCS_BIT', 'FEATURE_GFX_EDC_BIT', - 'FEATURE_GFX_IMU_BIT', 'FEATURE_GFX_PCC_DFLL_BIT', - 'FEATURE_GFX_READ_MARGIN_BIT', 'FEATURE_GFX_ULV_BIT', - 'FEATURE_GTHR_BIT', 'FEATURE_LED_DISPLAY_BIT', - 'FEATURE_MEM_TEMP_READ_BIT', 'FEATURE_MM_DPM_BIT', - 'FEATURE_OPTIMIZED_VMIN_BIT', 'FEATURE_OUT_OF_BAND_MONITOR_BIT', - 'FEATURE_PWR_ALL', 'FEATURE_PWR_BACO', 'FEATURE_PWR_DOMAIN_COUNT', - 'FEATURE_PWR_DOMAIN_e', 'FEATURE_PWR_DOMAIN_e__enumvalues', - 'FEATURE_PWR_GFX', 'FEATURE_PWR_S5', 'FEATURE_PWR_SOC', - 'FEATURE_SMARTSHIFT_BIT', 'FEATURE_SOC_CG_BIT', - 'FEATURE_SOC_MPCLK_DS_BIT', 'FEATURE_SOC_PCC_BIT', - 'FEATURE_SPARE_52_BIT', 'FEATURE_SPARE_53_BIT', - 'FEATURE_SPARE_54_BIT', 'FEATURE_SPARE_55_BIT', - 'FEATURE_SPARE_56_BIT', 'FEATURE_SPARE_57_BIT', - 'FEATURE_SPARE_58_BIT', 'FEATURE_SPARE_59_BIT', - 'FEATURE_SPARE_60_BIT', 'FEATURE_SPARE_61_BIT', - 'FEATURE_SPARE_62_BIT', 'FEATURE_SPARE_63_BIT', - 'FEATURE_THROTTLERS_BIT', 'FEATURE_VDDIO_MEM_SCALING_BIT', - 'FEATURE_VMEMP_SCALING_BIT', 'FEATURE_VR0HOT_BIT', - 'FOPT_CALC_AC_CALC_DC', 'FOPT_CALC_AC_PPTABLE_DC', 'FOPT_CALC_e', - 'FOPT_CALC_e__enumvalues', 'FOPT_PPTABLE_AC_CALC_DC', - 'FOPT_PPTABLE_AC_PPTABLE_DC', 'FW_DSTATE_CLDO_PRG_BIT', - 'FW_DSTATE_CSRCLK_DS_BIT', 'FW_DSTATE_D0i3_2_QUIET_FW_BIT', - 'FW_DSTATE_DF_PLL_PWRDN_BIT', 'FW_DSTATE_G6_HSR_BIT', - 'FW_DSTATE_G6_PHY_VMEMP_OFF_BIT', 'FW_DSTATE_GFX_PSI6_BIT', - 'FW_DSTATE_GFX_VR_PWR_STAGE_BIT', 'FW_DSTATE_HSR_NON_STROBE_BIT', - 'FW_DSTATE_MALL_ALLOC_BIT', 'FW_DSTATE_MALL_FLUSH_BIT', - 'FW_DSTATE_MEM_PLL_PWRDN_BIT', 'FW_DSTATE_MEM_PSI_BIT', - 'FW_DSTATE_MMHUB_INTERLOCK_BIT', 'FW_DSTATE_MP0_ENTER_WFI_BIT', - 'FW_DSTATE_MP1_WHISPER_MODE_BIT', 'FW_DSTATE_SMN_DS_BIT', - 'FW_DSTATE_SOC_LIV_MIN_BIT', 'FW_DSTATE_SOC_PLL_PWRDN_BIT', - 'FW_DSTATE_SOC_PSI_BIT', 'FW_DSTATE_SOC_ULV_BIT', - 'FW_DSTATE_UCP_DS_BIT', 'FW_DSTATE_U_LOW_PWR_MODE_EN_BIT', - 'FW_DSTATE_U_PSI_BIT', 'FW_DSTATE_U_ULV_BIT', 'FanMode_e', - 'FanMode_e__enumvalues', 'GPIO_INT_POLARITY_ACTIVE_HIGH', - 'GPIO_INT_POLARITY_ACTIVE_LOW', 'GpioIntPolarity_e', - 'GpioIntPolarity_e__enumvalues', 'I2C_CMD_COUNT', 'I2C_CMD_READ', - 'I2C_CMD_WRITE', 'I2C_CONTROLLER_DISABLED', - 'I2C_CONTROLLER_ENABLED', 'I2C_CONTROLLER_NAME_COUNT', - 'I2C_CONTROLLER_NAME_FAN_INTAKE', 'I2C_CONTROLLER_NAME_LIQUID0', - 'I2C_CONTROLLER_NAME_LIQUID1', 'I2C_CONTROLLER_NAME_PLX', - 'I2C_CONTROLLER_NAME_VR_GFX', 'I2C_CONTROLLER_NAME_VR_SOC', - 'I2C_CONTROLLER_NAME_VR_VDDIO', 'I2C_CONTROLLER_NAME_VR_VMEMP', - 'I2C_CONTROLLER_PORT_0', 'I2C_CONTROLLER_PORT_1', - 'I2C_CONTROLLER_PORT_COUNT', 'I2C_CONTROLLER_PROTOCOL_COUNT', - 'I2C_CONTROLLER_PROTOCOL_INA3221', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 'I2C_CONTROLLER_THROTTLER_COUNT', - 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 'I2C_CONTROLLER_THROTTLER_INA3221', - 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 'I2C_CONTROLLER_THROTTLER_PLX', - 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', 'I2C_PORT_GPIO', - 'I2C_PORT_SVD_SCL', 'I2C_SPEED_COUNT', 'I2C_SPEED_FAST_100K', - 'I2C_SPEED_FAST_400K', 'I2C_SPEED_FAST_50K', - 'I2C_SPEED_FAST_PLUS_1M', 'I2C_SPEED_HIGH_1M', - 'I2C_SPEED_HIGH_2M', 'I2cCmdType_e', 'I2cCmdType_e__enumvalues', - 'I2cControllerConfig_t', 'I2cControllerName_e', - 'I2cControllerName_e__enumvalues', 'I2cControllerPort_e', - 'I2cControllerPort_e__enumvalues', 'I2cControllerProtocol_e', - 'I2cControllerProtocol_e__enumvalues', 'I2cControllerThrottler_e', - 'I2cControllerThrottler_e__enumvalues', 'I2cPort_e', - 'I2cPort_e__enumvalues', 'I2cSpeed_e', 'I2cSpeed_e__enumvalues', - 'IH_INTERRUPT_CONTEXT_ID_AC', 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D0', - 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D3', - 'IH_INTERRUPT_CONTEXT_ID_BACO', 'IH_INTERRUPT_CONTEXT_ID_DC', - 'IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL', - 'IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY', - 'IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING', - 'IH_INTERRUPT_ID_TO_DRIVER', 'INVALID_BOARD_GPIO', - 'LED_DISPLAY_ERROR_BIT', 'LED_DISPLAY_GFX_DPM_BIT', - 'LED_DISPLAY_PCIE_BIT', 'LinearInt_t', 'MARKETING_BASE_CLOCKS', - 'MARKETING_BOOST_CLOCKS', 'MARKETING_GAME_CLOCKS', - 'MAX_BOARD_GPIO_SMUIO_NUM', 'MAX_SW_I2C_COMMANDS', - 'MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT', - 'MEM_TEMP_READ_IN_BAND_REFRESH_BIT', - 'MEM_TEMP_READ_OUT_OF_BAND_BIT', 'MEM_VENDOR_COUNT', - 'MEM_VENDOR_ELPIDA', 'MEM_VENDOR_ESMT', 'MEM_VENDOR_ETRON', - 'MEM_VENDOR_HYNIX', 'MEM_VENDOR_INFINEON', 'MEM_VENDOR_MICRON', - 'MEM_VENDOR_MOSEL', 'MEM_VENDOR_NANYA', 'MEM_VENDOR_PLACEHOLDER0', - 'MEM_VENDOR_PLACEHOLDER1', 'MEM_VENDOR_PLACEHOLDER2', - 'MEM_VENDOR_PLACEHOLDER3', 'MEM_VENDOR_PLACEHOLDER4', - 'MEM_VENDOR_PLACEHOLDER5', 'MEM_VENDOR_SAMSUNG', - 'MEM_VENDOR_WINBOND', 'MEM_VENDOR_e', 'MEM_VENDOR_e__enumvalues', - 'MSR_SEQUENCE', 'MsgLimits_t', 'NUM_DCFCLK_DPM_LEVELS', - 'NUM_DCLK_DPM_LEVELS', 'NUM_DISPCLK_DPM_LEVELS', - 'NUM_DPPCLK_DPM_LEVELS', 'NUM_DPREFCLK_DPM_LEVELS', - 'NUM_DTBCLK_DPM_LEVELS', 'NUM_FCLK_DPM_LEVELS', 'NUM_FEATURES', - 'NUM_GFXCLK_DPM_LEVELS', 'NUM_I2C_CONTROLLERS', 'NUM_LINK_LEVELS', - 'NUM_MP0CLK_DPM_LEVELS', 'NUM_OD_FAN_MAX_POINTS', - 'NUM_SOCCLK_DPM_LEVELS', 'NUM_UCLK_DPM_LEVELS', - 'NUM_VCLK_DPM_LEVELS', 'NUM_WM_RANGES', 'OverDriveLimits_t', - 'OverDriveTableExternal_t', 'OverDriveTable_t', - 'PERF_LEVEL_ACTIVITY', 'PERF_LEVEL_POWER_CONTAINMENT', - 'PG_DYNAMIC_MODE', 'PG_POWER_DOWN', 'PG_POWER_UP', - 'PG_STATIC_MODE', 'PMFW_VOLT_PLANE_COUNT', 'PMFW_VOLT_PLANE_GFX', - 'PMFW_VOLT_PLANE_SOC', 'PMFW_VOLT_PLANE_e', - 'PMFW_VOLT_PLANE_e__enumvalues', 'POWER_SOURCE_AC', - 'POWER_SOURCE_COUNT', 'POWER_SOURCE_DC', 'POWER_SOURCE_e', - 'POWER_SOURCE_e__enumvalues', 'PPCLK_COUNT', 'PPCLK_DCFCLK', - 'PPCLK_DCLK_0', 'PPCLK_DCLK_1', 'PPCLK_DISPCLK', 'PPCLK_DPPCLK', - 'PPCLK_DPREFCLK', 'PPCLK_DTBCLK', 'PPCLK_FCLK', 'PPCLK_GFXCLK', - 'PPCLK_SOCCLK', 'PPCLK_UCLK', 'PPCLK_VCLK_0', 'PPCLK_VCLK_1', - 'PPCLK_e', 'PPCLK_e__enumvalues', 'PPSMC_MSG_AllowGfxDcs', - 'PPSMC_MSG_AllowGfxOff', 'PPSMC_MSG_AllowIHHostInterrupt', - 'PPSMC_MSG_ArmD3', 'PPSMC_MSG_BacoAudioD3PME', - 'PPSMC_MSG_DALNotPresent', 'PPSMC_MSG_DisableAllSmuFeatures', - 'PPSMC_MSG_DisableSmuFeaturesHigh', - 'PPSMC_MSG_DisableSmuFeaturesLow', 'PPSMC_MSG_DisallowGfxDcs', - 'PPSMC_MSG_DisallowGfxOff', 'PPSMC_MSG_DramLogSetDramAddrHigh', - 'PPSMC_MSG_DramLogSetDramAddrLow', 'PPSMC_MSG_DramLogSetDramSize', - 'PPSMC_MSG_DumpSTBtoDram', 'PPSMC_MSG_EnableAllSmuFeatures', - 'PPSMC_MSG_EnableAudioStutterWA', - 'PPSMC_MSG_EnableSmuFeaturesHigh', - 'PPSMC_MSG_EnableSmuFeaturesLow', 'PPSMC_MSG_EnableUCLKShadow', - 'PPSMC_MSG_EnterBaco', 'PPSMC_MSG_ExitBaco', - 'PPSMC_MSG_GetDcModeMaxDpmFreq', 'PPSMC_MSG_GetDebugData', - 'PPSMC_MSG_GetDpmFreqByIndex', 'PPSMC_MSG_GetDriverIfVersion', - 'PPSMC_MSG_GetMaxDpmFreq', 'PPSMC_MSG_GetMinDpmFreq', - 'PPSMC_MSG_GetPptLimit', 'PPSMC_MSG_GetRunningSmuFeaturesHigh', - 'PPSMC_MSG_GetRunningSmuFeaturesLow', 'PPSMC_MSG_GetSmuVersion', - 'PPSMC_MSG_GetVoltageByDpm', 'PPSMC_MSG_Mode1Reset', - 'PPSMC_MSG_Mode2Reset', 'PPSMC_MSG_NotifyPowerSource', - 'PPSMC_MSG_OverridePcieParameters', 'PPSMC_MSG_PowerDownJpeg', - 'PPSMC_MSG_PowerDownUmsch', 'PPSMC_MSG_PowerDownVcn', - 'PPSMC_MSG_PowerUpJpeg', 'PPSMC_MSG_PowerUpUmsch', - 'PPSMC_MSG_PowerUpVcn', 'PPSMC_MSG_PrepareMp1ForUnload', - 'PPSMC_MSG_ReenableAcDcInterrupt', 'PPSMC_MSG_RunDcBtc', - 'PPSMC_MSG_STBtoDramLogSetDramAddrHigh', - 'PPSMC_MSG_STBtoDramLogSetDramAddrLow', - 'PPSMC_MSG_STBtoDramLogSetDramSize', - 'PPSMC_MSG_SetAllowedFeaturesMaskHigh', - 'PPSMC_MSG_SetAllowedFeaturesMaskLow', - 'PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel', - 'PPSMC_MSG_SetDcsArch', 'PPSMC_MSG_SetDriverDramAddrHigh', - 'PPSMC_MSG_SetDriverDramAddrLow', - 'PPSMC_MSG_SetExternalClientDfCstateAllow', - 'PPSMC_MSG_SetFwDstatesMask', 'PPSMC_MSG_SetGpoAllow', - 'PPSMC_MSG_SetHardMaxByFreq', 'PPSMC_MSG_SetHardMinByFreq', - 'PPSMC_MSG_SetMGpuFanBoostLimitRpm', - 'PPSMC_MSG_SetNumBadMemoryPagesRetired', 'PPSMC_MSG_SetPptLimit', - 'PPSMC_MSG_SetPriorityDeltaGain', 'PPSMC_MSG_SetSoftMaxByFreq', - 'PPSMC_MSG_SetSoftMinByFreq', - 'PPSMC_MSG_SetSystemVirtualDramAddrHigh', - 'PPSMC_MSG_SetSystemVirtualDramAddrLow', - 'PPSMC_MSG_SetTemperatureInputSelect', - 'PPSMC_MSG_SetThrottlerMask', 'PPSMC_MSG_SetToolsDramAddrHigh', - 'PPSMC_MSG_SetToolsDramAddrLow', 'PPSMC_MSG_SetVideoFps', - 'PPSMC_MSG_SetWorkloadMask', 'PPSMC_MSG_TestMessage', - 'PPSMC_MSG_TransferTableDram2Smu', - 'PPSMC_MSG_TransferTableSmu2Dram', 'PPSMC_MSG_TriggerVFFLR', - 'PPSMC_MSG_UseDefaultPPTable', 'PPSMC_Message_Count', - 'PPSMC_Result_CmdRejectedBusy', 'PPSMC_Result_CmdRejectedPrereq', - 'PPSMC_Result_Failed', 'PPSMC_Result_OK', - 'PPSMC_Result_UnknownCmd', 'PPSMC_VERSION', 'PPTABLE_VERSION', - 'PPT_THROTTLER_COUNT', 'PPT_THROTTLER_PPT0', 'PPT_THROTTLER_PPT1', - 'PPT_THROTTLER_PPT2', 'PPT_THROTTLER_PPT3', 'PPT_THROTTLER_e', - 'PPT_THROTTLER_e__enumvalues', 'PPTable_t', - 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 'PP_GRTAVFS_FW_COMMON_FUSE_e', - 'PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_e', - 'PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 'PP_GRTAVFS_HW_FUSE_COUNT', - 'PP_GRTAVFS_HW_FUSE_e', 'PP_GRTAVFS_HW_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_RESERVED_0', 'PP_GRTAVFS_HW_RESERVED_1', - 'PP_GRTAVFS_HW_RESERVED_2', 'PP_GRTAVFS_HW_RESERVED_3', - 'PP_GRTAVFS_HW_RESERVED_4', 'PP_GRTAVFS_HW_RESERVED_5', - 'PP_GRTAVFS_HW_RESERVED_6', 'PP_GRTAVFS_HW_VOLTAGE_GB', - 'PP_GRTAVFS_HW_ZONE0_VF', 'PP_GRTAVFS_HW_ZONE1_VF1', - 'PP_GRTAVFS_HW_ZONE2_VF2', 'PP_GRTAVFS_HW_ZONE3_VF3', - 'PP_NUM_OD_VF_CURVE_POINTS', 'PP_NUM_RTAVFS_PWL_ZONES', - 'PP_OD_FEATURE_COUNT', 'PP_OD_FEATURE_FAN_CURVE_BIT', - 'PP_OD_FEATURE_GFXCLK_BIT', 'PP_OD_FEATURE_GFX_VF_CURVE_BIT', - 'PP_OD_FEATURE_PPT_BIT', 'PP_OD_FEATURE_TEMPERATURE_BIT', - 'PP_OD_FEATURE_UCLK_BIT', 'PP_OD_FEATURE_ZERO_FAN_BIT', - 'PSI_SEL_VR0_PLANE0_PSI0', 'PSI_SEL_VR0_PLANE0_PSI1', - 'PSI_SEL_VR0_PLANE1_PSI0', 'PSI_SEL_VR0_PLANE1_PSI1', - 'PSI_SEL_VR1_PLANE0_PSI0', 'PSI_SEL_VR1_PLANE0_PSI1', - 'PSI_SEL_VR1_PLANE1_PSI0', 'PSI_SEL_VR1_PLANE1_PSI1', - 'PWR_CONFIG_TCP_ESTIMATED', 'PWR_CONFIG_TCP_MEASURED', - 'PWR_CONFIG_TDP', 'PWR_CONFIG_TGP', 'PowerGatingMode_e', - 'PowerGatingMode_e__enumvalues', 'PowerGatingSettings_e', - 'PowerGatingSettings_e__enumvalues', 'PwrConfig_e', - 'PwrConfig_e__enumvalues', 'QuadraticInt_t', - 'SMARTSHIFT_VERSION_1', 'SMARTSHIFT_VERSION_2', - 'SMARTSHIFT_VERSION_3', 'SMARTSHIFT_VERSION_e', - 'SMARTSHIFT_VERSION_e__enumvalues', 'SMU13_0_0_DRIVER_IF_VERSION', - 'SMU13_DRIVER_IF_V13_0_0_H', 'SMU_CLK_COUNT', - 'SMU_CUSTOM_FAN_SPEED_PWM', 'SMU_CUSTOM_FAN_SPEED_RPM', - 'SMU_DCEFCLK', 'SMU_DCLK', 'SMU_DCLK1', 'SMU_DEFAULT_PPT_LIMIT', - 'SMU_DISPCLK', 'SMU_DPM_USER_PROFILE_RESTORE', 'SMU_ECLK', - 'SMU_FAST_PPT_LIMIT', 'SMU_FCLK', 'SMU_FW_NAME_LEN', 'SMU_GFXCLK', - 'SMU_LCLK', 'SMU_MCLK', 'SMU_MEMORY_POOL_SIZE_1_GB', - 'SMU_MEMORY_POOL_SIZE_256_MB', 'SMU_MEMORY_POOL_SIZE_2_GB', - 'SMU_MEMORY_POOL_SIZE_512_MB', 'SMU_MEMORY_POOL_SIZE_ZERO', - 'SMU_OD_ACOUSTIC_LIMIT', 'SMU_OD_ACOUSTIC_TARGET', 'SMU_OD_CCLK', - 'SMU_OD_FAN_CURVE', 'SMU_OD_FAN_MINIMUM_PWM', - 'SMU_OD_FAN_TARGET_TEMPERATURE', 'SMU_OD_MCLK', 'SMU_OD_RANGE', - 'SMU_OD_SCLK', 'SMU_OD_VDDC_CURVE', 'SMU_OD_VDDGFX_OFFSET', - 'SMU_PCIE', 'SMU_PHYCLK', 'SMU_PIXCLK', 'SMU_POWER_SOURCE_AC', - 'SMU_POWER_SOURCE_COUNT', 'SMU_POWER_SOURCE_DC', - 'SMU_PPT_LIMIT_CURRENT', 'SMU_PPT_LIMIT_DEFAULT', - 'SMU_PPT_LIMIT_MAX', 'SMU_PPT_LIMIT_MIN', - 'SMU_REFRESHRATE_SOURCE_EDID', 'SMU_REFRESHRATE_SOURCE_EXPLICIT', - 'SMU_SCLK', 'SMU_SOCCLK', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 'SMU_STATE_UI_LABEL_BACO', - 'SMU_STATE_UI_LABEL_BALLANCED', 'SMU_STATE_UI_LABEL_BATTERY', - 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 'SMU_STATE_UI_LABEL_NONE', - 'SMU_STATE_UI_LABEL_PERFORMANCE', 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', 'SMU_TABLE_AVFS', - 'SMU_TABLE_AVFS_FUSE_OVERRIDE', 'SMU_TABLE_AVFS_PSM_DEBUG', - 'SMU_TABLE_COMBO_PPTABLE', 'SMU_TABLE_COUNT', - 'SMU_TABLE_CUSTOM_DPM', 'SMU_TABLE_DPMCLOCKS', - 'SMU_TABLE_DRIVER_SMU_CONFIG', 'SMU_TABLE_ECCINFO', - 'SMU_TABLE_I2C_COMMANDS', 'SMU_TABLE_OVERDRIVE', 'SMU_TABLE_PACE', - 'SMU_TABLE_PMSTATUSLOG', 'SMU_TABLE_PPTABLE', - 'SMU_TABLE_SMU_METRICS', 'SMU_TABLE_WATERMARKS', - 'SMU_TABLE_WIFIBAND', 'SMU_TEMPERATURE_UNITS_PER_CENTIGRADES', - 'SMU_THERMAL_MAXIMUM_ALERT_TEMP', - 'SMU_THERMAL_MINIMUM_ALERT_TEMP', 'SMU_THROTTLER_APCC_BIT', - 'SMU_THROTTLER_EDC_CPU_BIT', 'SMU_THROTTLER_EDC_GFX_BIT', - 'SMU_THROTTLER_FIT_BIT', 'SMU_THROTTLER_FPPT_BIT', - 'SMU_THROTTLER_PPM_BIT', 'SMU_THROTTLER_PPT0_BIT', - 'SMU_THROTTLER_PPT1_BIT', 'SMU_THROTTLER_PPT2_BIT', - 'SMU_THROTTLER_PPT3_BIT', 'SMU_THROTTLER_PROCHOT_CPU_BIT', - 'SMU_THROTTLER_PROCHOT_GFX_BIT', 'SMU_THROTTLER_SPL_BIT', - 'SMU_THROTTLER_SPPT_APU_BIT', 'SMU_THROTTLER_SPPT_BIT', - 'SMU_THROTTLER_TDC_CVIP_BIT', 'SMU_THROTTLER_TDC_GFX_BIT', - 'SMU_THROTTLER_TDC_MEM_BIT', 'SMU_THROTTLER_TDC_SOC_BIT', - 'SMU_THROTTLER_TDC_VDD_BIT', 'SMU_THROTTLER_TEMP_CORE_BIT', - 'SMU_THROTTLER_TEMP_EDGE_BIT', 'SMU_THROTTLER_TEMP_GPU_BIT', - 'SMU_THROTTLER_TEMP_HOTSPOT_BIT', - 'SMU_THROTTLER_TEMP_LIQUID0_BIT', - 'SMU_THROTTLER_TEMP_LIQUID1_BIT', 'SMU_THROTTLER_TEMP_MEM_BIT', - 'SMU_THROTTLER_TEMP_SOC_BIT', 'SMU_THROTTLER_TEMP_VR_GFX_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM0_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM1_BIT', 'SMU_THROTTLER_TEMP_VR_SOC_BIT', - 'SMU_THROTTLER_VRHOT0_BIT', 'SMU_THROTTLER_VRHOT1_BIT', - 'SMU_UCLK', 'SMU_V13_0_0_PPSMC_H', 'SMU_VCLK', 'SMU_VCLK1', - 'SVI_PLANE_COUNT', 'SVI_PLANE_GFX', 'SVI_PLANE_SOC', - 'SVI_PLANE_U', 'SVI_PLANE_VDDIO_MEM', 'SVI_PLANE_VMEMP', - 'SVI_PLANE_e', 'SVI_PLANE_e__enumvalues', 'SVI_PSI_0', - 'SVI_PSI_1', 'SVI_PSI_2', 'SVI_PSI_3', 'SVI_PSI_4', 'SVI_PSI_5', - 'SVI_PSI_6', 'SVI_PSI_7', 'SVI_PSI_e', 'SVI_PSI_e__enumvalues', - 'SkuTable_t', 'SmuMetricsExternal_t', 'SmuMetrics_t', - 'SviTelemetryScale_t', 'SwI2cCmd_t', 'SwI2cRequestExternal_t', - 'SwI2cRequest_t', 'TABLE_ACTIVITY_MONITOR_COEFF', - 'TABLE_AVFS_PSM_DEBUG', 'TABLE_COMBO_PPTABLE', 'TABLE_COUNT', - 'TABLE_DRIVER_INFO', 'TABLE_DRIVER_SMU_CONFIG', 'TABLE_ECCINFO', - 'TABLE_I2C_COMMANDS', 'TABLE_OVERDRIVE', 'TABLE_PMSTATUSLOG', - 'TABLE_PPTABLE', 'TABLE_SMU_METRICS', 'TABLE_TRANSFER_FAILED', - 'TABLE_TRANSFER_OK', 'TABLE_TRANSFER_PENDING', 'TABLE_WATERMARKS', - 'TABLE_WIFIBAND', 'TDC_THROTTLER_COUNT', 'TDC_THROTTLER_GFX', - 'TDC_THROTTLER_SOC', 'TDC_THROTTLER_U', 'TDC_THROTTLER_e', - 'TDC_THROTTLER_e__enumvalues', 'TEMP_COUNT', 'TEMP_EDGE', - 'TEMP_HOTSPOT', 'TEMP_HOTSPOT_G', 'TEMP_HOTSPOT_M', - 'TEMP_LIQUID0', 'TEMP_LIQUID1', 'TEMP_MEM', 'TEMP_PLX', - 'TEMP_VR_GFX', 'TEMP_VR_MEM0', 'TEMP_VR_MEM1', 'TEMP_VR_SOC', - 'TEMP_VR_U', 'TEMP_e', 'TEMP_e__enumvalues', 'THROTTLER_COUNT', - 'THROTTLER_FIT_BIT', 'THROTTLER_GFX_APCC_PLUS_BIT', - 'THROTTLER_PPT0_BIT', 'THROTTLER_PPT1_BIT', 'THROTTLER_PPT2_BIT', - 'THROTTLER_PPT3_BIT', 'THROTTLER_TDC_GFX_BIT', - 'THROTTLER_TDC_SOC_BIT', 'THROTTLER_TDC_U_BIT', - 'THROTTLER_TEMP_EDGE_BIT', 'THROTTLER_TEMP_HOTSPOT_BIT', - 'THROTTLER_TEMP_HOTSPOT_G_BIT', 'THROTTLER_TEMP_HOTSPOT_M_BIT', - 'THROTTLER_TEMP_LIQUID0_BIT', 'THROTTLER_TEMP_LIQUID1_BIT', - 'THROTTLER_TEMP_MEM_BIT', 'THROTTLER_TEMP_PLX_BIT', - 'THROTTLER_TEMP_VR_GFX_BIT', 'THROTTLER_TEMP_VR_MEM0_BIT', - 'THROTTLER_TEMP_VR_MEM1_BIT', 'THROTTLER_TEMP_VR_SOC_BIT', - 'THROTTLER_TEMP_VR_U_BIT', 'UCLK_DIV_BY_1', 'UCLK_DIV_BY_2', - 'UCLK_DIV_BY_4', 'UCLK_DIV_BY_8', 'UCLK_DIV_e', - 'UCLK_DIV_e__enumvalues', 'ULPS_SEQUENCE', 'VOLTAGE_MODE_COUNT', - 'VOLTAGE_MODE_FUSES', 'VOLTAGE_MODE_PPTABLE', 'VOLTAGE_MODE_e', - 'VOLTAGE_MODE_e__enumvalues', 'VR_MAPPING_PLANE_SELECT_MASK', - 'VR_MAPPING_PLANE_SELECT_SHIFT', 'VR_MAPPING_VR_SELECT_MASK', - 'VR_MAPPING_VR_SELECT_SHIFT', 'WATERMARKS_CLOCK_RANGE', - 'WATERMARKS_COUNT', 'WATERMARKS_DUMMY_PSTATE', - 'WATERMARKS_FLAGS_e', 'WATERMARKS_FLAGS_e__enumvalues', - 'WATERMARKS_MALL', 'WORKLOAD_PPLIB_COMPUTE_BIT', - 'WORKLOAD_PPLIB_COUNT', 'WORKLOAD_PPLIB_CUSTOM_BIT', - 'WORKLOAD_PPLIB_DEFAULT_BIT', 'WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT', - 'WORKLOAD_PPLIB_POWER_SAVING_BIT', 'WORKLOAD_PPLIB_VIDEO_BIT', - 'WORKLOAD_PPLIB_VR_BIT', 'WORKLOAD_PPLIB_WINDOW_3D_BIT', - 'WatermarkRowGeneric_t', 'WatermarksExternal_t', 'Watermarks_t', - '__AMDGPU_SMU_H__', 'bool', 'c__EA_AVFS_D_e', 'c__EA_AVFS_TEMP_e', - 'c__EA_AVFS_VOLTAGE_TYPE_e', 'c__EA_BOARD_GPIO_TYPE_e', - 'c__EA_CUSTOMER_VARIANT_e', 'c__EA_D3HOTSequence_e', - 'c__EA_DCS_ARCH_e', 'c__EA_DRAM_BIT_WIDTH_TYPE_e', - 'c__EA_FEATURE_PWR_DOMAIN_e', 'c__EA_FOPT_CALC_e', - 'c__EA_FanMode_e', 'c__EA_GpioIntPolarity_e', - 'c__EA_I2cCmdType_e', 'c__EA_I2cControllerName_e', - 'c__EA_I2cControllerPort_e', 'c__EA_I2cControllerProtocol_e', - 'c__EA_I2cControllerThrottler_e', 'c__EA_I2cPort_e', - 'c__EA_I2cSpeed_e', 'c__EA_MEM_VENDOR_e', - 'c__EA_PMFW_VOLT_PLANE_e', 'c__EA_POWER_SOURCE_e', - 'c__EA_PPCLK_e', 'c__EA_PPT_THROTTLER_e', - 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e', - 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e', 'c__EA_PP_GRTAVFS_HW_FUSE_e', - 'c__EA_PowerGatingMode_e', 'c__EA_PowerGatingSettings_e', - 'c__EA_PwrConfig_e', 'c__EA_SMARTSHIFT_VERSION_e', - 'c__EA_SVI_PLANE_e', 'c__EA_SVI_PSI_e', 'c__EA_TDC_THROTTLER_e', - 'c__EA_TEMP_e', 'c__EA_UCLK_DIV_e', 'c__EA_VOLTAGE_MODE_e', - 'c__EA_WATERMARKS_FLAGS_e', 'int16_t', 'int32_t', 'int8_t', - 'smu_clk_type', 'smu_memory_pool_size', - 'smu_perf_level_designation', 'smu_power_src_type', - 'smu_ppt_limit_level', 'smu_ppt_limit_type', - 'smu_refreshrate_source', 'smu_state_classification_flag', - 'smu_state_ui_label', 'smu_table_id', 'struct_amdgpu_bo', - 'struct_c__SA_AvfsDcBtcParams_t', - 'struct_c__SA_AvfsDebugTableExternal_t', - 'struct_c__SA_AvfsDebugTable_t', - 'struct_c__SA_AvfsFuseOverride_t', 'struct_c__SA_BoardTable_t', - 'struct_c__SA_BootValues_t', - 'struct_c__SA_DpmActivityMonitorCoeffIntExternal_t', - 'struct_c__SA_DpmActivityMonitorCoeffInt_t', - 'struct_c__SA_DpmDescriptor_t', 'struct_c__SA_DriverInfoTable_t', - 'struct_c__SA_DriverReportedClocks_t', - 'struct_c__SA_DriverSmuConfigExternal_t', - 'struct_c__SA_DriverSmuConfig_t', 'struct_c__SA_DroopInt_t', - 'struct_c__SA_EccInfoTable_t', 'struct_c__SA_EccInfo_t', - 'struct_c__SA_I2cControllerConfig_t', 'struct_c__SA_LinearInt_t', - 'struct_c__SA_MsgLimits_t', 'struct_c__SA_OverDriveLimits_t', - 'struct_c__SA_OverDriveTableExternal_t', - 'struct_c__SA_OverDriveTable_t', 'struct_c__SA_PPTable_t', - 'struct_c__SA_QuadraticInt_t', 'struct_c__SA_SkuTable_t', - 'struct_c__SA_SmuMetricsExternal_t', 'struct_c__SA_SmuMetrics_t', - 'struct_c__SA_SviTelemetryScale_t', 'struct_c__SA_SwI2cCmd_t', - 'struct_c__SA_SwI2cRequestExternal_t', - 'struct_c__SA_SwI2cRequest_t', - 'struct_c__SA_WatermarkRowGeneric_t', - 'struct_c__SA_WatermarksExternal_t', 'struct_c__SA_Watermarks_t', - 'struct_smu_bios_boot_up_values', 'struct_smu_clock_info', - 'struct_smu_hw_power_state', 'struct_smu_performance_level', - 'struct_smu_power_state', 'struct_smu_state_classification_block', - 'struct_smu_state_display_block', 'struct_smu_state_memory_block', - 'struct_smu_state_pcie_block', - 'struct_smu_state_software_algorithm_block', - 'struct_smu_state_validation_block', 'struct_smu_table', - 'struct_smu_temperature_range', 'struct_smu_user_dpm_profile', - 'struct_smu_uvd_clocks', 'u32', 'uint16_t', 'uint32_t', - 'uint64_t', 'uint8_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/smu_v14_0_3.py b/tinygrad/tinygrad/runtime/autogen/am/smu_v14_0_3.py deleted file mode 100644 index 46cc1dc9..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/smu_v14_0_3.py +++ /dev/null @@ -1,3605 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', 'stdint.h'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -__SMU_V14_0_0_PMFW_H__ = True # macro -ENABLE_DEBUG_FEATURES = True # macro -FEATURE_CCLK_DPM_BIT = 0 # macro -FEATURE_FAN_CONTROLLER_BIT = 1 # macro -FEATURE_DATA_CALCULATION_BIT = 2 # macro -FEATURE_PPT_BIT = 3 # macro -FEATURE_TDC_BIT = 4 # macro -FEATURE_THERMAL_BIT = 5 # macro -FEATURE_FIT_BIT = 6 # macro -FEATURE_EDC_BIT = 7 # macro -FEATURE_PLL_POWER_DOWN_BIT = 8 # macro -FEATURE_VDDOFF_BIT = 9 # macro -FEATURE_VCN_DPM_BIT = 10 # macro -FEATURE_DS_MPM_BIT = 11 # macro -FEATURE_FCLK_DPM_BIT = 12 # macro -FEATURE_SOCCLK_DPM_BIT = 13 # macro -FEATURE_DS_MPIO_BIT = 14 # macro -FEATURE_LCLK_DPM_BIT = 15 # macro -FEATURE_SHUBCLK_DPM_BIT = 16 # macro -FEATURE_DCFCLK_DPM_BIT = 17 # macro -FEATURE_ISP_DPM_BIT = 18 # macro -FEATURE_IPU_DPM_BIT = 19 # macro -FEATURE_GFX_DPM_BIT = 20 # macro -FEATURE_DS_GFXCLK_BIT = 10 # macro -FEATURE_DS_SOCCLK_BIT = 11 # macro -FEATURE_DS_LCLK_BIT = 13 # macro -FEATURE_LOW_POWER_DCNCLKS_BIT = 24 # macro -FEATURE_DS_SHUBCLK_BIT = 25 # macro -FEATURE_RESERVED0_BIT = 26 # macro -FEATURE_ZSTATES_BIT = 27 # macro -FEATURE_IOMMUL2_PG_BIT = 28 # macro -FEATURE_DS_FCLK_BIT = 12 # macro -FEATURE_DS_SMNCLK_BIT = 30 # macro -FEATURE_DS_MP1CLK_BIT = 31 # macro -FEATURE_WHISPER_MODE_BIT = 32 # macro -FEATURE_SMU_LOW_POWER_BIT = 33 # macro -FEATURE_RESERVED1_BIT = 34 # macro -FEATURE_GFX_DEM_BIT = 35 # macro -FEATURE_PSI_BIT = 36 # macro -FEATURE_PROCHOT_BIT = 37 # macro -FEATURE_CPUOFF_BIT = 38 # macro -FEATURE_STAPM_BIT = 39 # macro -FEATURE_S0I3_BIT = 40 # macro -FEATURE_DF_LIGHT_CSTATE = 41 # macro -FEATURE_PERF_LIMIT_BIT = 42 # macro -FEATURE_CORE_DLDO_BIT = 43 # macro -FEATURE_DVO_BIT = 44 # macro -FEATURE_DS_VCN_BIT = 44 # macro -FEATURE_CPPC_BIT = 46 # macro -FEATURE_CPPC_PREFERRED_CORES = 47 # macro -FEATURE_DF_CSTATES_BIT = 48 # macro -FEATURE_FAST_PSTATE_CLDO_BIT = 49 # macro -FEATURE_ATHUB_PG_BIT = 50 # macro -FEATURE_VDDOFF_ECO_BIT = 51 # macro -FEATURE_ZSTATES_ECO_BIT = 52 # macro -FEATURE_CC6_BIT = 53 # macro -FEATURE_DS_UMCCLK_BIT = 54 # macro -FEATURE_DS_ISPCLK_BIT = 55 # macro -FEATURE_DS_HSPCLK_BIT = 56 # macro -FEATURE_P3T_BIT = 57 # macro -FEATURE_DS_IPUCLK_BIT = 58 # macro -FEATURE_DS_VPECLK_BIT = 59 # macro -FEATURE_VPE_DPM_BIT = 60 # macro -FEATURE_SMART_L3_RINSER_BIT = 61 # macro -FEATURE_PCC_BIT = 62 # macro -NUM_FEATURES = 64 # macro -class struct_SMU14_Firmware_Footer(Structure): - pass - -struct_SMU14_Firmware_Footer._pack_ = 1 # source:False -struct_SMU14_Firmware_Footer._fields_ = [ - ('Signature', ctypes.c_uint32), -] - -SMU14_Firmware_Footer = struct_SMU14_Firmware_Footer -class struct_c__SA_SMU_Firmware_Header(Structure): - pass - -struct_c__SA_SMU_Firmware_Header._pack_ = 1 # source:False -struct_c__SA_SMU_Firmware_Header._fields_ = [ - ('ImageVersion', ctypes.c_uint32), - ('ImageVersion2', ctypes.c_uint32), - ('Padding0', ctypes.c_uint32 * 3), - ('SizeFWSigned', ctypes.c_uint32), - ('Padding1', ctypes.c_uint32 * 25), - ('FirmwareType', ctypes.c_uint32), - ('Filler', ctypes.c_uint32 * 32), -] - -SMU_Firmware_Header = struct_c__SA_SMU_Firmware_Header -class struct_c__SA_FwStatus_t(Structure): - pass - -struct_c__SA_FwStatus_t._pack_ = 1 # source:False -struct_c__SA_FwStatus_t._fields_ = [ - ('DpmHandlerID', ctypes.c_uint64, 8), - ('ActivityMonitorID', ctypes.c_uint64, 8), - ('DpmTimerID', ctypes.c_uint64, 8), - ('DpmHubID', ctypes.c_uint64, 4), - ('DpmHubTask', ctypes.c_uint64, 4), - ('CclkSyncStatus', ctypes.c_uint64, 8), - ('Ccx0CpuOff', ctypes.c_uint64, 2), - ('Ccx1CpuOff', ctypes.c_uint64, 2), - ('GfxOffStatus', ctypes.c_uint64, 2), - ('VddOff', ctypes.c_uint64, 1), - ('InWhisperMode', ctypes.c_uint64, 1), - ('ZstateStatus', ctypes.c_uint64, 4), - ('spare0', ctypes.c_uint64, 4), - ('DstateFun', ctypes.c_uint64, 4), - ('DstateDev', ctypes.c_uint64, 4), - ('P2JobHandler', ctypes.c_uint64, 24), - ('RsmuPmiP2PendingCnt', ctypes.c_uint64, 8), - ('PostCode', ctypes.c_uint64, 32), - ('MsgPortBusy', ctypes.c_uint64, 24), - ('RsmuPmiP1Pending', ctypes.c_uint64, 1), - ('DfCstateExitPending', ctypes.c_uint64, 1), - ('Ccx0Pc6ExitPending', ctypes.c_uint64, 1), - ('Ccx1Pc6ExitPending', ctypes.c_uint64, 1), - ('WarmResetPending', ctypes.c_uint64, 1), - ('spare1', ctypes.c_uint64, 3), - ('IdleMask', ctypes.c_uint64, 32), -] - -FwStatus_t = struct_c__SA_FwStatus_t -class struct_c__SA_FwStatus_t_v14_0_1(Structure): - pass - -struct_c__SA_FwStatus_t_v14_0_1._pack_ = 1 # source:False -struct_c__SA_FwStatus_t_v14_0_1._fields_ = [ - ('DpmHandlerID', ctypes.c_uint64, 8), - ('ActivityMonitorID', ctypes.c_uint64, 8), - ('DpmTimerID', ctypes.c_uint64, 8), - ('DpmHubID', ctypes.c_uint64, 4), - ('DpmHubTask', ctypes.c_uint64, 4), - ('CclkSyncStatus', ctypes.c_uint64, 8), - ('ZstateStatus', ctypes.c_uint64, 4), - ('Cpu1VddOff', ctypes.c_uint64, 4), - ('DstateFun', ctypes.c_uint64, 4), - ('DstateDev', ctypes.c_uint64, 4), - ('GfxOffStatus', ctypes.c_uint64, 2), - ('Cpu0Off', ctypes.c_uint64, 2), - ('Cpu1Off', ctypes.c_uint64, 2), - ('Cpu0VddOff', ctypes.c_uint64, 2), - ('P2JobHandler', ctypes.c_uint64, 32), - ('PostCode', ctypes.c_uint64, 32), - ('MsgPortBusy', ctypes.c_uint64, 15), - ('RsmuPmiP1Pending', ctypes.c_uint64, 1), - ('RsmuPmiP2PendingCnt', ctypes.c_uint64, 8), - ('DfCstateExitPending', ctypes.c_uint64, 1), - ('Pc6EntryPending', ctypes.c_uint64, 1), - ('Pc6ExitPending', ctypes.c_uint64, 1), - ('WarmResetPending', ctypes.c_uint64, 1), - ('Mp0ClkPending', ctypes.c_uint64, 1), - ('InWhisperMode', ctypes.c_uint64, 1), - ('spare2', ctypes.c_uint64, 2), - ('IdleMask', ctypes.c_uint64, 32), -] - -FwStatus_t_v14_0_1 = struct_c__SA_FwStatus_t_v14_0_1 -SMU_V14_0_2_PPSMC_H = True # macro -PPSMC_VERSION = 0x1 # macro -PPSMC_Result_OK = 0x1 # macro -PPSMC_Result_Failed = 0xFF # macro -PPSMC_Result_UnknownCmd = 0xFE # macro -PPSMC_Result_CmdRejectedPrereq = 0xFD # macro -PPSMC_Result_CmdRejectedBusy = 0xFC # macro -PPSMC_MSG_TestMessage = 0x1 # macro -PPSMC_MSG_GetSmuVersion = 0x2 # macro -PPSMC_MSG_GetDriverIfVersion = 0x3 # macro -PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 # macro -PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 # macro -PPSMC_MSG_EnableAllSmuFeatures = 0x6 # macro -PPSMC_MSG_DisableAllSmuFeatures = 0x7 # macro -PPSMC_MSG_EnableSmuFeaturesLow = 0x8 # macro -PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 # macro -PPSMC_MSG_DisableSmuFeaturesLow = 0xA # macro -PPSMC_MSG_DisableSmuFeaturesHigh = 0xB # macro -PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC # macro -PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD # macro -PPSMC_MSG_SetDriverDramAddrHigh = 0xE # macro -PPSMC_MSG_SetDriverDramAddrLow = 0xF # macro -PPSMC_MSG_SetToolsDramAddrHigh = 0x10 # macro -PPSMC_MSG_SetToolsDramAddrLow = 0x11 # macro -PPSMC_MSG_TransferTableSmu2Dram = 0x12 # macro -PPSMC_MSG_TransferTableDram2Smu = 0x13 # macro -PPSMC_MSG_UseDefaultPPTable = 0x14 # macro -PPSMC_MSG_EnterBaco = 0x15 # macro -PPSMC_MSG_ExitBaco = 0x16 # macro -PPSMC_MSG_ArmD3 = 0x17 # macro -PPSMC_MSG_BacoAudioD3PME = 0x18 # macro -PPSMC_MSG_SetSoftMinByFreq = 0x19 # macro -PPSMC_MSG_SetSoftMaxByFreq = 0x1A # macro -PPSMC_MSG_SetHardMinByFreq = 0x1B # macro -PPSMC_MSG_SetHardMaxByFreq = 0x1C # macro -PPSMC_MSG_GetMinDpmFreq = 0x1D # macro -PPSMC_MSG_GetMaxDpmFreq = 0x1E # macro -PPSMC_MSG_GetDpmFreqByIndex = 0x1F # macro -PPSMC_MSG_OverridePcieParameters = 0x20 # macro -PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 # macro -PPSMC_MSG_DramLogSetDramAddrLow = 0x22 # macro -PPSMC_MSG_DramLogSetDramSize = 0x23 # macro -PPSMC_MSG_SetWorkloadMask = 0x24 # macro -PPSMC_MSG_GetVoltageByDpm = 0x25 # macro -PPSMC_MSG_SetVideoFps = 0x26 # macro -PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 # macro -PPSMC_MSG_AllowGfxOff = 0x28 # macro -PPSMC_MSG_DisallowGfxOff = 0x29 # macro -PPSMC_MSG_PowerUpVcn = 0x2A # macro -PPSMC_MSG_PowerDownVcn = 0x2B # macro -PPSMC_MSG_PowerUpJpeg = 0x2C # macro -PPSMC_MSG_PowerDownJpeg = 0x2D # macro -PPSMC_MSG_PrepareMp1ForUnload = 0x2E # macro -PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 # macro -PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 # macro -PPSMC_MSG_SetPptLimit = 0x32 # macro -PPSMC_MSG_GetPptLimit = 0x33 # macro -PPSMC_MSG_ReenableAcDcInterrupt = 0x34 # macro -PPSMC_MSG_NotifyPowerSource = 0x35 # macro -PPSMC_MSG_RunDcBtc = 0x36 # macro -PPSMC_MSG_SetTemperatureInputSelect = 0x38 # macro -PPSMC_MSG_SetFwDstatesMask = 0x39 # macro -PPSMC_MSG_SetThrottlerMask = 0x3A # macro -PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B # macro -PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C # macro -PPSMC_MSG_DumpSTBtoDram = 0x3D # macro -PPSMC_MSG_STBtoDramLogSetDramAddress = 0x3E # macro -PPSMC_MSG_DummyUndefined = 0x3F # macro -PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 # macro -PPSMC_MSG_SetOBMTraceBufferLogging = 0x41 # macro -PPSMC_MSG_UseProfilingMode = 0x42 # macro -PPSMC_MSG_AllowGfxDcs = 0x43 # macro -PPSMC_MSG_DisallowGfxDcs = 0x44 # macro -PPSMC_MSG_EnableAudioStutterWA = 0x45 # macro -PPSMC_MSG_PowerUpUmsch = 0x46 # macro -PPSMC_MSG_PowerDownUmsch = 0x47 # macro -PPSMC_MSG_SetDcsArch = 0x48 # macro -PPSMC_MSG_TriggerVFFLR = 0x49 # macro -PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x4A # macro -PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4B # macro -PPSMC_MSG_SetPriorityDeltaGain = 0x4C # macro -PPSMC_MSG_AllowIHHostInterrupt = 0x4D # macro -PPSMC_MSG_EnableShadowDpm = 0x4E # macro -PPSMC_MSG_Mode3Reset = 0x4F # macro -PPSMC_MSG_SetDriverDramAddr = 0x50 # macro -PPSMC_MSG_SetToolsDramAddr = 0x51 # macro -PPSMC_MSG_TransferTableSmu2DramWithAddr = 0x52 # macro -PPSMC_MSG_TransferTableDram2SmuWithAddr = 0x53 # macro -PPSMC_MSG_GetAllRunningSmuFeatures = 0x54 # macro -PPSMC_MSG_GetSvi3Voltage = 0x55 # macro -PPSMC_MSG_UpdatePolicy = 0x56 # macro -PPSMC_MSG_ExtPwrConnSupport = 0x57 # macro -PPSMC_MSG_PreloadSwPstateForUclkOverDrive = 0x58 # macro -PPSMC_Message_Count = 0x59 # macro -SMU14_DRIVER_IF_V14_0_H = True # macro -PPTABLE_VERSION = 0x1B # macro -NUM_GFXCLK_DPM_LEVELS = 16 # macro -NUM_SOCCLK_DPM_LEVELS = 8 # macro -NUM_MP0CLK_DPM_LEVELS = 2 # macro -NUM_DCLK_DPM_LEVELS = 8 # macro -NUM_VCLK_DPM_LEVELS = 8 # macro -NUM_DISPCLK_DPM_LEVELS = 8 # macro -NUM_DPPCLK_DPM_LEVELS = 8 # macro -NUM_DPREFCLK_DPM_LEVELS = 8 # macro -NUM_DCFCLK_DPM_LEVELS = 8 # macro -NUM_DTBCLK_DPM_LEVELS = 8 # macro -NUM_UCLK_DPM_LEVELS = 6 # macro -NUM_LINK_LEVELS = 3 # macro -NUM_FCLK_DPM_LEVELS = 8 # macro -NUM_OD_FAN_MAX_POINTS = 6 # macro -FEATURE_FW_DATA_READ_BIT = 0 # macro -FEATURE_DPM_GFXCLK_BIT = 1 # macro -FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 # macro -FEATURE_DPM_UCLK_BIT = 3 # macro -FEATURE_DPM_FCLK_BIT = 4 # macro -FEATURE_DPM_SOCCLK_BIT = 5 # macro -FEATURE_DPM_LINK_BIT = 6 # macro -FEATURE_DPM_DCN_BIT = 7 # macro -FEATURE_VMEMP_SCALING_BIT = 8 # macro -FEATURE_VDDIO_MEM_SCALING_BIT = 9 # macro -FEATURE_DS_DCFCLK_BIT = 14 # macro -FEATURE_DS_UCLK_BIT = 15 # macro -FEATURE_GFX_ULV_BIT = 16 # macro -FEATURE_FW_DSTATE_BIT = 17 # macro -FEATURE_GFXOFF_BIT = 18 # macro -FEATURE_BACO_BIT = 19 # macro -FEATURE_MM_DPM_BIT = 20 # macro -FEATURE_SOC_MPCLK_DS_BIT = 21 # macro -FEATURE_BACO_MPCLK_DS_BIT = 22 # macro -FEATURE_THROTTLERS_BIT = 23 # macro -FEATURE_SMARTSHIFT_BIT = 24 # macro -FEATURE_GTHR_BIT = 25 # macro -FEATURE_ACDC_BIT = 26 # macro -FEATURE_VR0HOT_BIT = 27 # macro -FEATURE_FW_CTF_BIT = 28 # macro -FEATURE_FAN_CONTROL_BIT = 29 # macro -FEATURE_GFX_DCS_BIT = 30 # macro -FEATURE_GFX_READ_MARGIN_BIT = 31 # macro -FEATURE_LED_DISPLAY_BIT = 32 # macro -FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 33 # macro -FEATURE_OUT_OF_BAND_MONITOR_BIT = 34 # macro -FEATURE_OPTIMIZED_VMIN_BIT = 35 # macro -FEATURE_GFX_IMU_BIT = 36 # macro -FEATURE_BOOT_TIME_CAL_BIT = 37 # macro -FEATURE_GFX_PCC_DFLL_BIT = 38 # macro -FEATURE_SOC_CG_BIT = 39 # macro -FEATURE_DF_CSTATE_BIT = 40 # macro -FEATURE_GFX_EDC_BIT = 41 # macro -FEATURE_BOOT_POWER_OPT_BIT = 42 # macro -FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 43 # macro -FEATURE_BACO_CG_BIT = 45 # macro -FEATURE_MEM_TEMP_READ_BIT = 46 # macro -FEATURE_ATHUB_MMHUB_PG_BIT = 47 # macro -FEATURE_SOC_PCC_BIT = 48 # macro -FEATURE_EDC_PWRBRK_BIT = 49 # macro -FEATURE_SOC_EDC_XVMIN_BIT = 50 # macro -FEATURE_GFX_PSM_DIDT_BIT = 51 # macro -FEATURE_APT_ALL_ENABLE_BIT = 52 # macro -FEATURE_APT_SQ_THROTTLE_BIT = 53 # macro -FEATURE_APT_PF_DCS_BIT = 54 # macro -FEATURE_GFX_EDC_XVMIN_BIT = 55 # macro -FEATURE_GFX_DIDT_XVMIN_BIT = 56 # macro -FEATURE_FAN_ABNORMAL_BIT = 57 # macro -FEATURE_CLOCK_STRETCH_COMPENSATOR = 58 # macro -FEATURE_SPARE_59_BIT = 59 # macro -FEATURE_SPARE_60_BIT = 60 # macro -FEATURE_SPARE_61_BIT = 61 # macro -FEATURE_SPARE_62_BIT = 62 # macro -FEATURE_SPARE_63_BIT = 63 # macro -ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF # macro -ALLOWED_FEATURE_CTRL_SCPM = (1<<1) # macro -DEBUG_OVERRIDE_NOT_USE = 0x00000001 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 # macro -DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 # macro -DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 # macro -DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 # macro -DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 # macro -DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 # macro -DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 # macro -DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 # macro -DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 # macro -DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 # macro -DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE = 0x00002000 # macro -DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY = 0x00004000 # macro -DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING = 0x00008000 # macro -DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG = 0x00010000 # macro -VR_MAPPING_VR_SELECT_MASK = 0x01 # macro -VR_MAPPING_VR_SELECT_SHIFT = 0x00 # macro -VR_MAPPING_PLANE_SELECT_MASK = 0x02 # macro -VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI0 = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI1 = 0x02 # macro -PSI_SEL_VR0_PLANE1_PSI0 = 0x04 # macro -PSI_SEL_VR0_PLANE1_PSI1 = 0x08 # macro -PSI_SEL_VR1_PLANE0_PSI0 = 0x10 # macro -PSI_SEL_VR1_PLANE0_PSI1 = 0x20 # macro -PSI_SEL_VR1_PLANE1_PSI0 = 0x40 # macro -PSI_SEL_VR1_PLANE1_PSI1 = 0x80 # macro -THROTTLER_TEMP_EDGE_BIT = 0 # macro -THROTTLER_TEMP_HOTSPOT_BIT = 1 # macro -THROTTLER_TEMP_HOTSPOT_GFX_BIT = 2 # macro -THROTTLER_TEMP_HOTSPOT_SOC_BIT = 3 # macro -THROTTLER_TEMP_MEM_BIT = 4 # macro -THROTTLER_TEMP_VR_GFX_BIT = 5 # macro -THROTTLER_TEMP_VR_SOC_BIT = 6 # macro -THROTTLER_TEMP_VR_MEM0_BIT = 7 # macro -THROTTLER_TEMP_VR_MEM1_BIT = 8 # macro -THROTTLER_TEMP_LIQUID0_BIT = 9 # macro -THROTTLER_TEMP_LIQUID1_BIT = 10 # macro -THROTTLER_TEMP_PLX_BIT = 11 # macro -THROTTLER_TDC_GFX_BIT = 12 # macro -THROTTLER_TDC_SOC_BIT = 13 # macro -THROTTLER_PPT0_BIT = 14 # macro -THROTTLER_PPT1_BIT = 15 # macro -THROTTLER_PPT2_BIT = 16 # macro -THROTTLER_PPT3_BIT = 17 # macro -THROTTLER_FIT_BIT = 18 # macro -THROTTLER_GFX_APCC_PLUS_BIT = 19 # macro -THROTTLER_GFX_DVO_BIT = 20 # macro -THROTTLER_COUNT = 21 # macro -FW_DSTATE_SOC_ULV_BIT = 0 # macro -FW_DSTATE_G6_HSR_BIT = 1 # macro -FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 # macro -FW_DSTATE_SMN_DS_BIT = 3 # macro -FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 # macro -FW_DSTATE_SOC_LIV_MIN_BIT = 5 # macro -FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 # macro -FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 # macro -FW_DSTATE_MALL_ALLOC_BIT = 8 # macro -FW_DSTATE_MEM_PSI_BIT = 9 # macro -FW_DSTATE_HSR_NON_STROBE_BIT = 10 # macro -FW_DSTATE_MP0_ENTER_WFI_BIT = 11 # macro -FW_DSTATE_MALL_FLUSH_BIT = 12 # macro -FW_DSTATE_SOC_PSI_BIT = 13 # macro -FW_DSTATE_MMHUB_INTERLOCK_BIT = 14 # macro -FW_DSTATE_D0i3_2_QUIET_FW_BIT = 15 # macro -FW_DSTATE_CLDO_PRG_BIT = 16 # macro -FW_DSTATE_DF_PLL_PWRDN_BIT = 17 # macro -LED_DISPLAY_GFX_DPM_BIT = 0 # macro -LED_DISPLAY_PCIE_BIT = 1 # macro -LED_DISPLAY_ERROR_BIT = 2 # macro -MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 # macro -MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 # macro -MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 # macro -NUM_I2C_CONTROLLERS = 8 # macro -I2C_CONTROLLER_ENABLED = 1 # macro -I2C_CONTROLLER_DISABLED = 0 # macro -MAX_SW_I2C_COMMANDS = 24 # macro -CMDCONFIG_STOP_BIT = 0 # macro -CMDCONFIG_RESTART_BIT = 1 # macro -CMDCONFIG_READWRITE_BIT = 2 # macro -CMDCONFIG_STOP_MASK = (1<<0) # macro -CMDCONFIG_RESTART_MASK = (1<<1) # macro -CMDCONFIG_READWRITE_MASK = (1<<2) # macro -EPCS_HIGH_POWER = 600 # macro -EPCS_NORMAL_POWER = 450 # macro -EPCS_LOW_POWER = 300 # macro -EPCS_SHORTED_POWER = 150 # macro -EPCS_NO_BOOTUP = 0 # macro -PP_NUM_RTAVFS_PWL_ZONES = 5 # macro -PP_NUM_PSM_DIDT_PWL_ZONES = 3 # macro -PP_NUM_OD_VF_CURVE_POINTS = 5 + 1 # macro -PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 # macro -PP_OD_FEATURE_GFX_VMAX_BIT = 1 # macro -PP_OD_FEATURE_SOC_VMAX_BIT = 2 # macro -PP_OD_FEATURE_PPT_BIT = 3 # macro -PP_OD_FEATURE_FAN_CURVE_BIT = 4 # macro -PP_OD_FEATURE_FAN_LEGACY_BIT = 5 # macro -PP_OD_FEATURE_FULL_CTRL_BIT = 6 # macro -PP_OD_FEATURE_TDC_BIT = 7 # macro -PP_OD_FEATURE_GFXCLK_BIT = 8 # macro -PP_OD_FEATURE_UCLK_BIT = 9 # macro -PP_OD_FEATURE_FCLK_BIT = 10 # macro -PP_OD_FEATURE_ZERO_FAN_BIT = 11 # macro -PP_OD_FEATURE_TEMPERATURE_BIT = 12 # macro -PP_OD_FEATURE_EDC_BIT = 13 # macro -PP_OD_FEATURE_COUNT = 14 # macro -INVALID_BOARD_GPIO = 0xFF # macro -NUM_WM_RANGES = 4 # macro -WORKLOAD_PPLIB_DEFAULT_BIT = 0 # macro -WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 # macro -WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 # macro -WORKLOAD_PPLIB_VIDEO_BIT = 3 # macro -WORKLOAD_PPLIB_VR_BIT = 4 # macro -WORKLOAD_PPLIB_COMPUTE_BIT = 5 # macro -WORKLOAD_PPLIB_CUSTOM_BIT = 6 # macro -WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 # macro -WORKLOAD_PPLIB_DIRECT_ML_BIT = 8 # macro -WORKLOAD_PPLIB_CGVDI_BIT = 9 # macro -WORKLOAD_PPLIB_COUNT = 10 # macro -TABLE_TRANSFER_OK = 0x0 # macro -TABLE_TRANSFER_FAILED = 0xFF # macro -TABLE_TRANSFER_PENDING = 0xAB # macro -TABLE_PPT_FAILED = 0x100 # macro -TABLE_TDC_FAILED = 0x200 # macro -TABLE_TEMP_FAILED = 0x400 # macro -TABLE_FAN_TARGET_TEMP_FAILED = 0x800 # macro -TABLE_FAN_STOP_TEMP_FAILED = 0x1000 # macro -TABLE_FAN_START_TEMP_FAILED = 0x2000 # macro -TABLE_FAN_PWM_MIN_FAILED = 0x4000 # macro -TABLE_ACOUSTIC_TARGET_RPM_FAILED = 0x8000 # macro -TABLE_ACOUSTIC_LIMIT_RPM_FAILED = 0x10000 # macro -TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED = 0x20000 # macro -TABLE_PPTABLE = 0 # macro -TABLE_COMBO_PPTABLE = 1 # macro -TABLE_WATERMARKS = 2 # macro -TABLE_AVFS_PSM_DEBUG = 3 # macro -TABLE_PMSTATUSLOG = 4 # macro -TABLE_SMU_METRICS = 5 # macro -TABLE_DRIVER_SMU_CONFIG = 6 # macro -TABLE_ACTIVITY_MONITOR_COEFF = 7 # macro -TABLE_OVERDRIVE = 8 # macro -TABLE_I2C_COMMANDS = 9 # macro -TABLE_DRIVER_INFO = 10 # macro -TABLE_ECCINFO = 11 # macro -TABLE_CUSTOM_SKUTABLE = 12 # macro -TABLE_COUNT = 13 # macro -IH_INTERRUPT_ID_TO_DRIVER = 0xFE # macro -IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 # macro -IH_INTERRUPT_CONTEXT_ID_AC = 0x3 # macro -IH_INTERRUPT_CONTEXT_ID_DC = 0x4 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 # macro -IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 # macro -IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE = 0xA # macro - -# values for enumeration 'c__EA_FEATURE_PWR_DOMAIN_e' -c__EA_FEATURE_PWR_DOMAIN_e__enumvalues = { - 0: 'FEATURE_PWR_ALL', - 1: 'FEATURE_PWR_S5', - 2: 'FEATURE_PWR_BACO', - 3: 'FEATURE_PWR_SOC', - 4: 'FEATURE_PWR_GFX', - 5: 'FEATURE_PWR_DOMAIN_COUNT', -} -FEATURE_PWR_ALL = 0 -FEATURE_PWR_S5 = 1 -FEATURE_PWR_BACO = 2 -FEATURE_PWR_SOC = 3 -FEATURE_PWR_GFX = 4 -FEATURE_PWR_DOMAIN_COUNT = 5 -c__EA_FEATURE_PWR_DOMAIN_e = ctypes.c_uint32 # enum -FEATURE_PWR_DOMAIN_e = c__EA_FEATURE_PWR_DOMAIN_e -FEATURE_PWR_DOMAIN_e__enumvalues = c__EA_FEATURE_PWR_DOMAIN_e__enumvalues - -# values for enumeration 'c__EA_FEATURE_BTC_e' -c__EA_FEATURE_BTC_e__enumvalues = { - 0: 'FEATURE_BTC_NOP', - 1: 'FEATURE_BTC_SAVE', - 2: 'FEATURE_BTC_RESTORE', - 3: 'FEATURE_BTC_COUNT', -} -FEATURE_BTC_NOP = 0 -FEATURE_BTC_SAVE = 1 -FEATURE_BTC_RESTORE = 2 -FEATURE_BTC_COUNT = 3 -c__EA_FEATURE_BTC_e = ctypes.c_uint32 # enum -FEATURE_BTC_e = c__EA_FEATURE_BTC_e -FEATURE_BTC_e__enumvalues = c__EA_FEATURE_BTC_e__enumvalues - -# values for enumeration 'c__EA_SVI_PSI_e' -c__EA_SVI_PSI_e__enumvalues = { - 0: 'SVI_PSI_0', - 1: 'SVI_PSI_1', - 2: 'SVI_PSI_2', - 3: 'SVI_PSI_3', - 4: 'SVI_PSI_4', - 5: 'SVI_PSI_5', - 6: 'SVI_PSI_6', - 7: 'SVI_PSI_7', -} -SVI_PSI_0 = 0 -SVI_PSI_1 = 1 -SVI_PSI_2 = 2 -SVI_PSI_3 = 3 -SVI_PSI_4 = 4 -SVI_PSI_5 = 5 -SVI_PSI_6 = 6 -SVI_PSI_7 = 7 -c__EA_SVI_PSI_e = ctypes.c_uint32 # enum -SVI_PSI_e = c__EA_SVI_PSI_e -SVI_PSI_e__enumvalues = c__EA_SVI_PSI_e__enumvalues - -# values for enumeration 'c__EA_SMARTSHIFT_VERSION_e' -c__EA_SMARTSHIFT_VERSION_e__enumvalues = { - 0: 'SMARTSHIFT_VERSION_1', - 1: 'SMARTSHIFT_VERSION_2', - 2: 'SMARTSHIFT_VERSION_3', -} -SMARTSHIFT_VERSION_1 = 0 -SMARTSHIFT_VERSION_2 = 1 -SMARTSHIFT_VERSION_3 = 2 -c__EA_SMARTSHIFT_VERSION_e = ctypes.c_uint32 # enum -SMARTSHIFT_VERSION_e = c__EA_SMARTSHIFT_VERSION_e -SMARTSHIFT_VERSION_e__enumvalues = c__EA_SMARTSHIFT_VERSION_e__enumvalues - -# values for enumeration 'c__EA_FOPT_CALC_e' -c__EA_FOPT_CALC_e__enumvalues = { - 0: 'FOPT_CALC_AC_CALC_DC', - 1: 'FOPT_PPTABLE_AC_CALC_DC', - 2: 'FOPT_CALC_AC_PPTABLE_DC', - 3: 'FOPT_PPTABLE_AC_PPTABLE_DC', -} -FOPT_CALC_AC_CALC_DC = 0 -FOPT_PPTABLE_AC_CALC_DC = 1 -FOPT_CALC_AC_PPTABLE_DC = 2 -FOPT_PPTABLE_AC_PPTABLE_DC = 3 -c__EA_FOPT_CALC_e = ctypes.c_uint32 # enum -FOPT_CALC_e = c__EA_FOPT_CALC_e -FOPT_CALC_e__enumvalues = c__EA_FOPT_CALC_e__enumvalues - -# values for enumeration 'c__EA_DRAM_BIT_WIDTH_TYPE_e' -c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues = { - 0: 'DRAM_BIT_WIDTH_DISABLED', - 8: 'DRAM_BIT_WIDTH_X_8', - 16: 'DRAM_BIT_WIDTH_X_16', - 32: 'DRAM_BIT_WIDTH_X_32', - 64: 'DRAM_BIT_WIDTH_X_64', - 128: 'DRAM_BIT_WIDTH_X_128', - 129: 'DRAM_BIT_WIDTH_COUNT', -} -DRAM_BIT_WIDTH_DISABLED = 0 -DRAM_BIT_WIDTH_X_8 = 8 -DRAM_BIT_WIDTH_X_16 = 16 -DRAM_BIT_WIDTH_X_32 = 32 -DRAM_BIT_WIDTH_X_64 = 64 -DRAM_BIT_WIDTH_X_128 = 128 -DRAM_BIT_WIDTH_COUNT = 129 -c__EA_DRAM_BIT_WIDTH_TYPE_e = ctypes.c_uint32 # enum -DRAM_BIT_WIDTH_TYPE_e = c__EA_DRAM_BIT_WIDTH_TYPE_e -DRAM_BIT_WIDTH_TYPE_e__enumvalues = c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerPort_e' -c__EA_I2cControllerPort_e__enumvalues = { - 0: 'I2C_CONTROLLER_PORT_0', - 1: 'I2C_CONTROLLER_PORT_1', - 2: 'I2C_CONTROLLER_PORT_COUNT', -} -I2C_CONTROLLER_PORT_0 = 0 -I2C_CONTROLLER_PORT_1 = 1 -I2C_CONTROLLER_PORT_COUNT = 2 -c__EA_I2cControllerPort_e = ctypes.c_uint32 # enum -I2cControllerPort_e = c__EA_I2cControllerPort_e -I2cControllerPort_e__enumvalues = c__EA_I2cControllerPort_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerName_e' -c__EA_I2cControllerName_e__enumvalues = { - 0: 'I2C_CONTROLLER_NAME_VR_GFX', - 1: 'I2C_CONTROLLER_NAME_VR_SOC', - 2: 'I2C_CONTROLLER_NAME_VR_VMEMP', - 3: 'I2C_CONTROLLER_NAME_VR_VDDIO', - 4: 'I2C_CONTROLLER_NAME_LIQUID0', - 5: 'I2C_CONTROLLER_NAME_LIQUID1', - 6: 'I2C_CONTROLLER_NAME_PLX', - 7: 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 8: 'I2C_CONTROLLER_NAME_COUNT', -} -I2C_CONTROLLER_NAME_VR_GFX = 0 -I2C_CONTROLLER_NAME_VR_SOC = 1 -I2C_CONTROLLER_NAME_VR_VMEMP = 2 -I2C_CONTROLLER_NAME_VR_VDDIO = 3 -I2C_CONTROLLER_NAME_LIQUID0 = 4 -I2C_CONTROLLER_NAME_LIQUID1 = 5 -I2C_CONTROLLER_NAME_PLX = 6 -I2C_CONTROLLER_NAME_FAN_INTAKE = 7 -I2C_CONTROLLER_NAME_COUNT = 8 -c__EA_I2cControllerName_e = ctypes.c_uint32 # enum -I2cControllerName_e = c__EA_I2cControllerName_e -I2cControllerName_e__enumvalues = c__EA_I2cControllerName_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerThrottler_e' -c__EA_I2cControllerThrottler_e__enumvalues = { - 0: 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 1: 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 2: 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 3: 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', - 4: 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 5: 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 6: 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 7: 'I2C_CONTROLLER_THROTTLER_PLX', - 8: 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 9: 'I2C_CONTROLLER_THROTTLER_INA3221', - 10: 'I2C_CONTROLLER_THROTTLER_COUNT', -} -I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0 -I2C_CONTROLLER_THROTTLER_VR_GFX = 1 -I2C_CONTROLLER_THROTTLER_VR_SOC = 2 -I2C_CONTROLLER_THROTTLER_VR_VMEMP = 3 -I2C_CONTROLLER_THROTTLER_VR_VDDIO = 4 -I2C_CONTROLLER_THROTTLER_LIQUID0 = 5 -I2C_CONTROLLER_THROTTLER_LIQUID1 = 6 -I2C_CONTROLLER_THROTTLER_PLX = 7 -I2C_CONTROLLER_THROTTLER_FAN_INTAKE = 8 -I2C_CONTROLLER_THROTTLER_INA3221 = 9 -I2C_CONTROLLER_THROTTLER_COUNT = 10 -c__EA_I2cControllerThrottler_e = ctypes.c_uint32 # enum -I2cControllerThrottler_e = c__EA_I2cControllerThrottler_e -I2cControllerThrottler_e__enumvalues = c__EA_I2cControllerThrottler_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerProtocol_e' -c__EA_I2cControllerProtocol_e__enumvalues = { - 0: 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 1: 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 2: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 3: 'I2C_CONTROLLER_PROTOCOL_INA3221', - 4: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 5: 'I2C_CONTROLLER_PROTOCOL_COUNT', -} -I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = 0 -I2C_CONTROLLER_PROTOCOL_VR_IR35217 = 1 -I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = 2 -I2C_CONTROLLER_PROTOCOL_INA3221 = 3 -I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = 4 -I2C_CONTROLLER_PROTOCOL_COUNT = 5 -c__EA_I2cControllerProtocol_e = ctypes.c_uint32 # enum -I2cControllerProtocol_e = c__EA_I2cControllerProtocol_e -I2cControllerProtocol_e__enumvalues = c__EA_I2cControllerProtocol_e__enumvalues -class struct_c__SA_I2cControllerConfig_t(Structure): - pass - -struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False -struct_c__SA_I2cControllerConfig_t._fields_ = [ - ('Enabled', ctypes.c_ubyte), - ('Speed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('ControllerPort', ctypes.c_ubyte), - ('ControllerName', ctypes.c_ubyte), - ('ThermalThrotter', ctypes.c_ubyte), - ('I2cProtocol', ctypes.c_ubyte), - ('PaddingConfig', ctypes.c_ubyte), -] - -I2cControllerConfig_t = struct_c__SA_I2cControllerConfig_t - -# values for enumeration 'c__EA_I2cPort_e' -c__EA_I2cPort_e__enumvalues = { - 0: 'I2C_PORT_SVD_SCL', - 1: 'I2C_PORT_GPIO', -} -I2C_PORT_SVD_SCL = 0 -I2C_PORT_GPIO = 1 -c__EA_I2cPort_e = ctypes.c_uint32 # enum -I2cPort_e = c__EA_I2cPort_e -I2cPort_e__enumvalues = c__EA_I2cPort_e__enumvalues - -# values for enumeration 'c__EA_I2cSpeed_e' -c__EA_I2cSpeed_e__enumvalues = { - 0: 'I2C_SPEED_FAST_50K', - 1: 'I2C_SPEED_FAST_100K', - 2: 'I2C_SPEED_FAST_400K', - 3: 'I2C_SPEED_FAST_PLUS_1M', - 4: 'I2C_SPEED_HIGH_1M', - 5: 'I2C_SPEED_HIGH_2M', - 6: 'I2C_SPEED_COUNT', -} -I2C_SPEED_FAST_50K = 0 -I2C_SPEED_FAST_100K = 1 -I2C_SPEED_FAST_400K = 2 -I2C_SPEED_FAST_PLUS_1M = 3 -I2C_SPEED_HIGH_1M = 4 -I2C_SPEED_HIGH_2M = 5 -I2C_SPEED_COUNT = 6 -c__EA_I2cSpeed_e = ctypes.c_uint32 # enum -I2cSpeed_e = c__EA_I2cSpeed_e -I2cSpeed_e__enumvalues = c__EA_I2cSpeed_e__enumvalues - -# values for enumeration 'c__EA_I2cCmdType_e' -c__EA_I2cCmdType_e__enumvalues = { - 0: 'I2C_CMD_READ', - 1: 'I2C_CMD_WRITE', - 2: 'I2C_CMD_COUNT', -} -I2C_CMD_READ = 0 -I2C_CMD_WRITE = 1 -I2C_CMD_COUNT = 2 -c__EA_I2cCmdType_e = ctypes.c_uint32 # enum -I2cCmdType_e = c__EA_I2cCmdType_e -I2cCmdType_e__enumvalues = c__EA_I2cCmdType_e__enumvalues -class struct_c__SA_SwI2cCmd_t(Structure): - pass - -struct_c__SA_SwI2cCmd_t._pack_ = 1 # source:False -struct_c__SA_SwI2cCmd_t._fields_ = [ - ('ReadWriteData', ctypes.c_ubyte), - ('CmdConfig', ctypes.c_ubyte), -] - -SwI2cCmd_t = struct_c__SA_SwI2cCmd_t -class struct_c__SA_SwI2cRequest_t(Structure): - pass - -struct_c__SA_SwI2cRequest_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequest_t._fields_ = [ - ('I2CcontrollerPort', ctypes.c_ubyte), - ('I2CSpeed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('NumCmds', ctypes.c_ubyte), - ('SwI2cCmds', struct_c__SA_SwI2cCmd_t * 24), -] - -SwI2cRequest_t = struct_c__SA_SwI2cRequest_t -class struct_c__SA_SwI2cRequestExternal_t(Structure): - pass - -struct_c__SA_SwI2cRequestExternal_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequestExternal_t._fields_ = [ - ('SwI2cRequest', SwI2cRequest_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SwI2cRequestExternal_t = struct_c__SA_SwI2cRequestExternal_t -class struct_c__SA_EccInfo_t(Structure): - pass - -struct_c__SA_EccInfo_t._pack_ = 1 # source:False -struct_c__SA_EccInfo_t._fields_ = [ - ('mca_umc_status', ctypes.c_uint64), - ('mca_umc_addr', ctypes.c_uint64), - ('ce_count_lo_chip', ctypes.c_uint16), - ('ce_count_hi_chip', ctypes.c_uint16), - ('eccPadding', ctypes.c_uint32), -] - -EccInfo_t = struct_c__SA_EccInfo_t -class struct_c__SA_EccInfoTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('EccInfo', struct_c__SA_EccInfo_t * 24), - ] - -EccInfoTable_t = struct_c__SA_EccInfoTable_t - -# values for enumeration 'c__EA_EPCS_STATUS_e' -c__EA_EPCS_STATUS_e__enumvalues = { - 0: 'EPCS_SHORTED_LIMIT', - 1: 'EPCS_LOW_POWER_LIMIT', - 2: 'EPCS_NORMAL_POWER_LIMIT', - 3: 'EPCS_HIGH_POWER_LIMIT', - 4: 'EPCS_NOT_CONFIGURED', - 5: 'EPCS_STATUS_COUNT', -} -EPCS_SHORTED_LIMIT = 0 -EPCS_LOW_POWER_LIMIT = 1 -EPCS_NORMAL_POWER_LIMIT = 2 -EPCS_HIGH_POWER_LIMIT = 3 -EPCS_NOT_CONFIGURED = 4 -EPCS_STATUS_COUNT = 5 -c__EA_EPCS_STATUS_e = ctypes.c_uint32 # enum -EPCS_STATUS_e = c__EA_EPCS_STATUS_e -EPCS_STATUS_e__enumvalues = c__EA_EPCS_STATUS_e__enumvalues - -# values for enumeration 'c__EA_D3HOTSequence_e' -c__EA_D3HOTSequence_e__enumvalues = { - 0: 'BACO_SEQUENCE', - 1: 'MSR_SEQUENCE', - 2: 'BAMACO_SEQUENCE', - 3: 'ULPS_SEQUENCE', - 4: 'D3HOT_SEQUENCE_COUNT', -} -BACO_SEQUENCE = 0 -MSR_SEQUENCE = 1 -BAMACO_SEQUENCE = 2 -ULPS_SEQUENCE = 3 -D3HOT_SEQUENCE_COUNT = 4 -c__EA_D3HOTSequence_e = ctypes.c_uint32 # enum -D3HOTSequence_e = c__EA_D3HOTSequence_e -D3HOTSequence_e__enumvalues = c__EA_D3HOTSequence_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingMode_e' -c__EA_PowerGatingMode_e__enumvalues = { - 0: 'PG_DYNAMIC_MODE', - 1: 'PG_STATIC_MODE', -} -PG_DYNAMIC_MODE = 0 -PG_STATIC_MODE = 1 -c__EA_PowerGatingMode_e = ctypes.c_uint32 # enum -PowerGatingMode_e = c__EA_PowerGatingMode_e -PowerGatingMode_e__enumvalues = c__EA_PowerGatingMode_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingSettings_e' -c__EA_PowerGatingSettings_e__enumvalues = { - 0: 'PG_POWER_DOWN', - 1: 'PG_POWER_UP', -} -PG_POWER_DOWN = 0 -PG_POWER_UP = 1 -c__EA_PowerGatingSettings_e = ctypes.c_uint32 # enum -PowerGatingSettings_e = c__EA_PowerGatingSettings_e -PowerGatingSettings_e__enumvalues = c__EA_PowerGatingSettings_e__enumvalues -class struct_c__SA_QuadraticInt_t(Structure): - pass - -struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False -struct_c__SA_QuadraticInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -QuadraticInt_t = struct_c__SA_QuadraticInt_t -class struct_c__SA_LinearInt_t(Structure): - pass - -struct_c__SA_LinearInt_t._pack_ = 1 # source:False -struct_c__SA_LinearInt_t._fields_ = [ - ('m', ctypes.c_uint32), - ('b', ctypes.c_uint32), -] - -LinearInt_t = struct_c__SA_LinearInt_t -class struct_c__SA_DroopInt_t(Structure): - pass - -struct_c__SA_DroopInt_t._pack_ = 1 # source:False -struct_c__SA_DroopInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -DroopInt_t = struct_c__SA_DroopInt_t - -# values for enumeration 'c__EA_DCS_ARCH_e' -c__EA_DCS_ARCH_e__enumvalues = { - 0: 'DCS_ARCH_DISABLED', - 1: 'DCS_ARCH_FADCS', - 2: 'DCS_ARCH_ASYNC', -} -DCS_ARCH_DISABLED = 0 -DCS_ARCH_FADCS = 1 -DCS_ARCH_ASYNC = 2 -c__EA_DCS_ARCH_e = ctypes.c_uint32 # enum -DCS_ARCH_e = c__EA_DCS_ARCH_e -DCS_ARCH_e__enumvalues = c__EA_DCS_ARCH_e__enumvalues - -# values for enumeration 'c__EA_PPCLK_e' -c__EA_PPCLK_e__enumvalues = { - 0: 'PPCLK_GFXCLK', - 1: 'PPCLK_SOCCLK', - 2: 'PPCLK_UCLK', - 3: 'PPCLK_FCLK', - 4: 'PPCLK_DCLK_0', - 5: 'PPCLK_VCLK_0', - 6: 'PPCLK_DISPCLK', - 7: 'PPCLK_DPPCLK', - 8: 'PPCLK_DPREFCLK', - 9: 'PPCLK_DCFCLK', - 10: 'PPCLK_DTBCLK', - 11: 'PPCLK_COUNT', -} -PPCLK_GFXCLK = 0 -PPCLK_SOCCLK = 1 -PPCLK_UCLK = 2 -PPCLK_FCLK = 3 -PPCLK_DCLK_0 = 4 -PPCLK_VCLK_0 = 5 -PPCLK_DISPCLK = 6 -PPCLK_DPPCLK = 7 -PPCLK_DPREFCLK = 8 -PPCLK_DCFCLK = 9 -PPCLK_DTBCLK = 10 -PPCLK_COUNT = 11 -c__EA_PPCLK_e = ctypes.c_uint32 # enum -PPCLK_e = c__EA_PPCLK_e -PPCLK_e__enumvalues = c__EA_PPCLK_e__enumvalues - -# values for enumeration 'c__EA_VOLTAGE_MODE_e' -c__EA_VOLTAGE_MODE_e__enumvalues = { - 0: 'VOLTAGE_MODE_PPTABLE', - 1: 'VOLTAGE_MODE_FUSES', - 2: 'VOLTAGE_MODE_COUNT', -} -VOLTAGE_MODE_PPTABLE = 0 -VOLTAGE_MODE_FUSES = 1 -VOLTAGE_MODE_COUNT = 2 -c__EA_VOLTAGE_MODE_e = ctypes.c_uint32 # enum -VOLTAGE_MODE_e = c__EA_VOLTAGE_MODE_e -VOLTAGE_MODE_e__enumvalues = c__EA_VOLTAGE_MODE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_VOLTAGE_TYPE_e' -c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues = { - 0: 'AVFS_VOLTAGE_GFX', - 1: 'AVFS_VOLTAGE_SOC', - 2: 'AVFS_VOLTAGE_COUNT', -} -AVFS_VOLTAGE_GFX = 0 -AVFS_VOLTAGE_SOC = 1 -AVFS_VOLTAGE_COUNT = 2 -c__EA_AVFS_VOLTAGE_TYPE_e = ctypes.c_uint32 # enum -AVFS_VOLTAGE_TYPE_e = c__EA_AVFS_VOLTAGE_TYPE_e -AVFS_VOLTAGE_TYPE_e__enumvalues = c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_TEMP_e' -c__EA_AVFS_TEMP_e__enumvalues = { - 0: 'AVFS_TEMP_COLD', - 1: 'AVFS_TEMP_HOT', - 2: 'AVFS_TEMP_COUNT', -} -AVFS_TEMP_COLD = 0 -AVFS_TEMP_HOT = 1 -AVFS_TEMP_COUNT = 2 -c__EA_AVFS_TEMP_e = ctypes.c_uint32 # enum -AVFS_TEMP_e = c__EA_AVFS_TEMP_e -AVFS_TEMP_e__enumvalues = c__EA_AVFS_TEMP_e__enumvalues - -# values for enumeration 'c__EA_AVFS_D_e' -c__EA_AVFS_D_e__enumvalues = { - 0: 'AVFS_D_G', - 1: 'AVFS_D_COUNT', -} -AVFS_D_G = 0 -AVFS_D_COUNT = 1 -c__EA_AVFS_D_e = ctypes.c_uint32 # enum -AVFS_D_e = c__EA_AVFS_D_e -AVFS_D_e__enumvalues = c__EA_AVFS_D_e__enumvalues - -# values for enumeration 'c__EA_UCLK_DIV_e' -c__EA_UCLK_DIV_e__enumvalues = { - 0: 'UCLK_DIV_BY_1', - 1: 'UCLK_DIV_BY_2', - 2: 'UCLK_DIV_BY_4', - 3: 'UCLK_DIV_BY_8', -} -UCLK_DIV_BY_1 = 0 -UCLK_DIV_BY_2 = 1 -UCLK_DIV_BY_4 = 2 -UCLK_DIV_BY_8 = 3 -c__EA_UCLK_DIV_e = ctypes.c_uint32 # enum -UCLK_DIV_e = c__EA_UCLK_DIV_e -UCLK_DIV_e__enumvalues = c__EA_UCLK_DIV_e__enumvalues - -# values for enumeration 'c__EA_GpioIntPolarity_e' -c__EA_GpioIntPolarity_e__enumvalues = { - 0: 'GPIO_INT_POLARITY_ACTIVE_LOW', - 1: 'GPIO_INT_POLARITY_ACTIVE_HIGH', -} -GPIO_INT_POLARITY_ACTIVE_LOW = 0 -GPIO_INT_POLARITY_ACTIVE_HIGH = 1 -c__EA_GpioIntPolarity_e = ctypes.c_uint32 # enum -GpioIntPolarity_e = c__EA_GpioIntPolarity_e -GpioIntPolarity_e__enumvalues = c__EA_GpioIntPolarity_e__enumvalues - -# values for enumeration 'c__EA_PwrConfig_e' -c__EA_PwrConfig_e__enumvalues = { - 0: 'PWR_CONFIG_TDP', - 1: 'PWR_CONFIG_TGP', - 2: 'PWR_CONFIG_TCP_ESTIMATED', - 3: 'PWR_CONFIG_TCP_MEASURED', - 4: 'PWR_CONFIG_TBP_DESKTOP', - 5: 'PWR_CONFIG_TBP_MOBILE', -} -PWR_CONFIG_TDP = 0 -PWR_CONFIG_TGP = 1 -PWR_CONFIG_TCP_ESTIMATED = 2 -PWR_CONFIG_TCP_MEASURED = 3 -PWR_CONFIG_TBP_DESKTOP = 4 -PWR_CONFIG_TBP_MOBILE = 5 -c__EA_PwrConfig_e = ctypes.c_uint32 # enum -PwrConfig_e = c__EA_PwrConfig_e -PwrConfig_e__enumvalues = c__EA_PwrConfig_e__enumvalues -class struct_c__SA_DpmDescriptor_t(Structure): - pass - -struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False -struct_c__SA_DpmDescriptor_t._fields_ = [ - ('Padding', ctypes.c_ubyte), - ('SnapToDiscrete', ctypes.c_ubyte), - ('NumDiscreteLevels', ctypes.c_ubyte), - ('CalculateFopt', ctypes.c_ubyte), - ('ConversionToAvfsClk', LinearInt_t), - ('Padding3', ctypes.c_uint32 * 3), - ('Padding4', ctypes.c_uint16), - ('FoptimalDc', ctypes.c_uint16), - ('FoptimalAc', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), -] - -DpmDescriptor_t = struct_c__SA_DpmDescriptor_t - -# values for enumeration 'c__EA_PPT_THROTTLER_e' -c__EA_PPT_THROTTLER_e__enumvalues = { - 0: 'PPT_THROTTLER_PPT0', - 1: 'PPT_THROTTLER_PPT1', - 2: 'PPT_THROTTLER_PPT2', - 3: 'PPT_THROTTLER_PPT3', - 4: 'PPT_THROTTLER_COUNT', -} -PPT_THROTTLER_PPT0 = 0 -PPT_THROTTLER_PPT1 = 1 -PPT_THROTTLER_PPT2 = 2 -PPT_THROTTLER_PPT3 = 3 -PPT_THROTTLER_COUNT = 4 -c__EA_PPT_THROTTLER_e = ctypes.c_uint32 # enum -PPT_THROTTLER_e = c__EA_PPT_THROTTLER_e -PPT_THROTTLER_e__enumvalues = c__EA_PPT_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_TEMP_e' -c__EA_TEMP_e__enumvalues = { - 0: 'TEMP_EDGE', - 1: 'TEMP_HOTSPOT', - 2: 'TEMP_HOTSPOT_GFX', - 3: 'TEMP_HOTSPOT_SOC', - 4: 'TEMP_MEM', - 5: 'TEMP_VR_GFX', - 6: 'TEMP_VR_SOC', - 7: 'TEMP_VR_MEM0', - 8: 'TEMP_VR_MEM1', - 9: 'TEMP_LIQUID0', - 10: 'TEMP_LIQUID1', - 11: 'TEMP_PLX', - 12: 'TEMP_COUNT', -} -TEMP_EDGE = 0 -TEMP_HOTSPOT = 1 -TEMP_HOTSPOT_GFX = 2 -TEMP_HOTSPOT_SOC = 3 -TEMP_MEM = 4 -TEMP_VR_GFX = 5 -TEMP_VR_SOC = 6 -TEMP_VR_MEM0 = 7 -TEMP_VR_MEM1 = 8 -TEMP_LIQUID0 = 9 -TEMP_LIQUID1 = 10 -TEMP_PLX = 11 -TEMP_COUNT = 12 -c__EA_TEMP_e = ctypes.c_uint32 # enum -TEMP_e = c__EA_TEMP_e -TEMP_e__enumvalues = c__EA_TEMP_e__enumvalues - -# values for enumeration 'c__EA_TDC_THROTTLER_e' -c__EA_TDC_THROTTLER_e__enumvalues = { - 0: 'TDC_THROTTLER_GFX', - 1: 'TDC_THROTTLER_SOC', - 2: 'TDC_THROTTLER_COUNT', -} -TDC_THROTTLER_GFX = 0 -TDC_THROTTLER_SOC = 1 -TDC_THROTTLER_COUNT = 2 -c__EA_TDC_THROTTLER_e = ctypes.c_uint32 # enum -TDC_THROTTLER_e = c__EA_TDC_THROTTLER_e -TDC_THROTTLER_e__enumvalues = c__EA_TDC_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_SVI_PLANE_e' -c__EA_SVI_PLANE_e__enumvalues = { - 0: 'SVI_PLANE_VDD_GFX', - 1: 'SVI_PLANE_VDD_SOC', - 2: 'SVI_PLANE_VDDCI_MEM', - 3: 'SVI_PLANE_VDDIO_MEM', - 4: 'SVI_PLANE_COUNT', -} -SVI_PLANE_VDD_GFX = 0 -SVI_PLANE_VDD_SOC = 1 -SVI_PLANE_VDDCI_MEM = 2 -SVI_PLANE_VDDIO_MEM = 3 -SVI_PLANE_COUNT = 4 -c__EA_SVI_PLANE_e = ctypes.c_uint32 # enum -SVI_PLANE_e = c__EA_SVI_PLANE_e -SVI_PLANE_e__enumvalues = c__EA_SVI_PLANE_e__enumvalues - -# values for enumeration 'c__EA_PMFW_VOLT_PLANE_e' -c__EA_PMFW_VOLT_PLANE_e__enumvalues = { - 0: 'PMFW_VOLT_PLANE_GFX', - 1: 'PMFW_VOLT_PLANE_SOC', - 2: 'PMFW_VOLT_PLANE_COUNT', -} -PMFW_VOLT_PLANE_GFX = 0 -PMFW_VOLT_PLANE_SOC = 1 -PMFW_VOLT_PLANE_COUNT = 2 -c__EA_PMFW_VOLT_PLANE_e = ctypes.c_uint32 # enum -PMFW_VOLT_PLANE_e = c__EA_PMFW_VOLT_PLANE_e -PMFW_VOLT_PLANE_e__enumvalues = c__EA_PMFW_VOLT_PLANE_e__enumvalues - -# values for enumeration 'c__EA_CUSTOMER_VARIANT_e' -c__EA_CUSTOMER_VARIANT_e__enumvalues = { - 0: 'CUSTOMER_VARIANT_ROW', - 1: 'CUSTOMER_VARIANT_FALCON', - 2: 'CUSTOMER_VARIANT_COUNT', -} -CUSTOMER_VARIANT_ROW = 0 -CUSTOMER_VARIANT_FALCON = 1 -CUSTOMER_VARIANT_COUNT = 2 -c__EA_CUSTOMER_VARIANT_e = ctypes.c_uint32 # enum -CUSTOMER_VARIANT_e = c__EA_CUSTOMER_VARIANT_e -CUSTOMER_VARIANT_e__enumvalues = c__EA_CUSTOMER_VARIANT_e__enumvalues - -# values for enumeration 'c__EA_POWER_SOURCE_e' -c__EA_POWER_SOURCE_e__enumvalues = { - 0: 'POWER_SOURCE_AC', - 1: 'POWER_SOURCE_DC', - 2: 'POWER_SOURCE_COUNT', -} -POWER_SOURCE_AC = 0 -POWER_SOURCE_DC = 1 -POWER_SOURCE_COUNT = 2 -c__EA_POWER_SOURCE_e = ctypes.c_uint32 # enum -POWER_SOURCE_e = c__EA_POWER_SOURCE_e -POWER_SOURCE_e__enumvalues = c__EA_POWER_SOURCE_e__enumvalues - -# values for enumeration 'c__EA_MEM_VENDOR_e' -c__EA_MEM_VENDOR_e__enumvalues = { - 0: 'MEM_VENDOR_PLACEHOLDER0', - 1: 'MEM_VENDOR_SAMSUNG', - 2: 'MEM_VENDOR_INFINEON', - 3: 'MEM_VENDOR_ELPIDA', - 4: 'MEM_VENDOR_ETRON', - 5: 'MEM_VENDOR_NANYA', - 6: 'MEM_VENDOR_HYNIX', - 7: 'MEM_VENDOR_MOSEL', - 8: 'MEM_VENDOR_WINBOND', - 9: 'MEM_VENDOR_ESMT', - 10: 'MEM_VENDOR_PLACEHOLDER1', - 11: 'MEM_VENDOR_PLACEHOLDER2', - 12: 'MEM_VENDOR_PLACEHOLDER3', - 13: 'MEM_VENDOR_PLACEHOLDER4', - 14: 'MEM_VENDOR_PLACEHOLDER5', - 15: 'MEM_VENDOR_MICRON', - 16: 'MEM_VENDOR_COUNT', -} -MEM_VENDOR_PLACEHOLDER0 = 0 -MEM_VENDOR_SAMSUNG = 1 -MEM_VENDOR_INFINEON = 2 -MEM_VENDOR_ELPIDA = 3 -MEM_VENDOR_ETRON = 4 -MEM_VENDOR_NANYA = 5 -MEM_VENDOR_HYNIX = 6 -MEM_VENDOR_MOSEL = 7 -MEM_VENDOR_WINBOND = 8 -MEM_VENDOR_ESMT = 9 -MEM_VENDOR_PLACEHOLDER1 = 10 -MEM_VENDOR_PLACEHOLDER2 = 11 -MEM_VENDOR_PLACEHOLDER3 = 12 -MEM_VENDOR_PLACEHOLDER4 = 13 -MEM_VENDOR_PLACEHOLDER5 = 14 -MEM_VENDOR_MICRON = 15 -MEM_VENDOR_COUNT = 16 -c__EA_MEM_VENDOR_e = ctypes.c_uint32 # enum -MEM_VENDOR_e = c__EA_MEM_VENDOR_e -MEM_VENDOR_e__enumvalues = c__EA_MEM_VENDOR_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_HW_FUSE_e' -c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', - 1: 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 2: 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', - 3: 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 4: 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', - 5: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 6: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 7: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 8: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 9: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 10: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 11: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 12: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 13: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 14: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', - 15: 'PP_GRTAVFS_HW_ZONE0_VF', - 16: 'PP_GRTAVFS_HW_ZONE1_VF1', - 17: 'PP_GRTAVFS_HW_ZONE2_VF2', - 18: 'PP_GRTAVFS_HW_ZONE3_VF3', - 19: 'PP_GRTAVFS_HW_VOLTAGE_GB', - 20: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 21: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 22: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 23: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 24: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 25: 'PP_GRTAVFS_HW_RESERVED_0', - 26: 'PP_GRTAVFS_HW_RESERVED_1', - 27: 'PP_GRTAVFS_HW_RESERVED_2', - 28: 'PP_GRTAVFS_HW_RESERVED_3', - 29: 'PP_GRTAVFS_HW_RESERVED_4', - 30: 'PP_GRTAVFS_HW_RESERVED_5', - 31: 'PP_GRTAVFS_HW_RESERVED_6', - 32: 'PP_GRTAVFS_HW_FUSE_COUNT', -} -PP_GRTAVFS_HW_CPO_CTL_ZONE0 = 0 -PP_GRTAVFS_HW_CPO_CTL_ZONE1 = 1 -PP_GRTAVFS_HW_CPO_CTL_ZONE2 = 2 -PP_GRTAVFS_HW_CPO_CTL_ZONE3 = 3 -PP_GRTAVFS_HW_CPO_CTL_ZONE4 = 4 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = 5 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = 6 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = 7 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = 8 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = 9 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = 10 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = 11 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = 12 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = 13 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = 14 -PP_GRTAVFS_HW_ZONE0_VF = 15 -PP_GRTAVFS_HW_ZONE1_VF1 = 16 -PP_GRTAVFS_HW_ZONE2_VF2 = 17 -PP_GRTAVFS_HW_ZONE3_VF3 = 18 -PP_GRTAVFS_HW_VOLTAGE_GB = 19 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = 20 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = 21 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = 22 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = 23 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = 24 -PP_GRTAVFS_HW_RESERVED_0 = 25 -PP_GRTAVFS_HW_RESERVED_1 = 26 -PP_GRTAVFS_HW_RESERVED_2 = 27 -PP_GRTAVFS_HW_RESERVED_3 = 28 -PP_GRTAVFS_HW_RESERVED_4 = 29 -PP_GRTAVFS_HW_RESERVED_5 = 30 -PP_GRTAVFS_HW_RESERVED_6 = 31 -PP_GRTAVFS_HW_FUSE_COUNT = 32 -c__EA_PP_GRTAVFS_HW_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_HW_FUSE_e = c__EA_PP_GRTAVFS_HW_FUSE_e -PP_GRTAVFS_HW_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e' -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 1: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 2: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 3: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 4: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 5: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 6: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 7: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 8: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 9: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 10: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 11: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 12: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', - 13: 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', -} -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = 0 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = 1 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = 2 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = 3 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = 4 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = 5 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = 6 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = 7 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = 8 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = 9 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = 10 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = 11 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = 12 -PP_GRTAVFS_FW_COMMON_FUSE_COUNT = 13 -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_COMMON_FUSE_e = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e -PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e' -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 1: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 2: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 3: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 4: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 5: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 6: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 7: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 8: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 9: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 10: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 11: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 12: 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 13: 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 14: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 15: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 16: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 17: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 18: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 19: 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', -} -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = 0 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = 1 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = 2 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = 3 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = 4 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = 5 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = 6 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = 7 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = 8 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = 9 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = 10 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = 11 -PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = 12 -PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = 13 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = 14 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = 15 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = 16 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = 17 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = 18 -PP_GRTAVFS_FW_SEP_FUSE_COUNT = 19 -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_SEP_FUSE_e = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e -PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues -class struct_c__SA_SviTelemetryScale_t(Structure): - pass - -struct_c__SA_SviTelemetryScale_t._pack_ = 1 # source:False -struct_c__SA_SviTelemetryScale_t._fields_ = [ - ('Offset', ctypes.c_byte), - ('Padding', ctypes.c_ubyte), - ('MaxCurrent', ctypes.c_uint16), -] - -SviTelemetryScale_t = struct_c__SA_SviTelemetryScale_t - -# values for enumeration 'c__EA_PP_OD_POWER_FEATURE_e' -c__EA_PP_OD_POWER_FEATURE_e__enumvalues = { - 0: 'PP_OD_POWER_FEATURE_ALWAYS_ENABLED', - 1: 'PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', - 2: 'PP_OD_POWER_FEATURE_ALWAYS_DISABLED', -} -PP_OD_POWER_FEATURE_ALWAYS_ENABLED = 0 -PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING = 1 -PP_OD_POWER_FEATURE_ALWAYS_DISABLED = 2 -c__EA_PP_OD_POWER_FEATURE_e = ctypes.c_uint32 # enum -PP_OD_POWER_FEATURE_e = c__EA_PP_OD_POWER_FEATURE_e -PP_OD_POWER_FEATURE_e__enumvalues = c__EA_PP_OD_POWER_FEATURE_e__enumvalues - -# values for enumeration 'c__EA_FanMode_e' -c__EA_FanMode_e__enumvalues = { - 0: 'FAN_MODE_AUTO', - 1: 'FAN_MODE_MANUAL_LINEAR', -} -FAN_MODE_AUTO = 0 -FAN_MODE_MANUAL_LINEAR = 1 -c__EA_FanMode_e = ctypes.c_uint32 # enum -FanMode_e = c__EA_FanMode_e -FanMode_e__enumvalues = c__EA_FanMode_e__enumvalues - -# values for enumeration 'c__EA_OD_FAIL_e' -c__EA_OD_FAIL_e__enumvalues = { - 0: 'OD_NO_ERROR', - 1: 'OD_REQUEST_ADVANCED_NOT_SUPPORTED', - 2: 'OD_UNSUPPORTED_FEATURE', - 3: 'OD_INVALID_FEATURE_COMBO_ERROR', - 4: 'OD_GFXCLK_VF_CURVE_OFFSET_ERROR', - 5: 'OD_VDD_GFX_VMAX_ERROR', - 6: 'OD_VDD_SOC_VMAX_ERROR', - 7: 'OD_PPT_ERROR', - 8: 'OD_FAN_MIN_PWM_ERROR', - 9: 'OD_FAN_ACOUSTIC_TARGET_ERROR', - 10: 'OD_FAN_ACOUSTIC_LIMIT_ERROR', - 11: 'OD_FAN_TARGET_TEMP_ERROR', - 12: 'OD_FAN_ZERO_RPM_STOP_TEMP_ERROR', - 13: 'OD_FAN_CURVE_PWM_ERROR', - 14: 'OD_FAN_CURVE_TEMP_ERROR', - 15: 'OD_FULL_CTRL_GFXCLK_ERROR', - 16: 'OD_FULL_CTRL_UCLK_ERROR', - 17: 'OD_FULL_CTRL_FCLK_ERROR', - 18: 'OD_FULL_CTRL_VDD_GFX_ERROR', - 19: 'OD_FULL_CTRL_VDD_SOC_ERROR', - 20: 'OD_TDC_ERROR', - 21: 'OD_GFXCLK_ERROR', - 22: 'OD_UCLK_ERROR', - 23: 'OD_FCLK_ERROR', - 24: 'OD_OP_TEMP_ERROR', - 25: 'OD_OP_GFX_EDC_ERROR', - 26: 'OD_OP_GFX_PCC_ERROR', - 27: 'OD_POWER_FEATURE_CTRL_ERROR', -} -OD_NO_ERROR = 0 -OD_REQUEST_ADVANCED_NOT_SUPPORTED = 1 -OD_UNSUPPORTED_FEATURE = 2 -OD_INVALID_FEATURE_COMBO_ERROR = 3 -OD_GFXCLK_VF_CURVE_OFFSET_ERROR = 4 -OD_VDD_GFX_VMAX_ERROR = 5 -OD_VDD_SOC_VMAX_ERROR = 6 -OD_PPT_ERROR = 7 -OD_FAN_MIN_PWM_ERROR = 8 -OD_FAN_ACOUSTIC_TARGET_ERROR = 9 -OD_FAN_ACOUSTIC_LIMIT_ERROR = 10 -OD_FAN_TARGET_TEMP_ERROR = 11 -OD_FAN_ZERO_RPM_STOP_TEMP_ERROR = 12 -OD_FAN_CURVE_PWM_ERROR = 13 -OD_FAN_CURVE_TEMP_ERROR = 14 -OD_FULL_CTRL_GFXCLK_ERROR = 15 -OD_FULL_CTRL_UCLK_ERROR = 16 -OD_FULL_CTRL_FCLK_ERROR = 17 -OD_FULL_CTRL_VDD_GFX_ERROR = 18 -OD_FULL_CTRL_VDD_SOC_ERROR = 19 -OD_TDC_ERROR = 20 -OD_GFXCLK_ERROR = 21 -OD_UCLK_ERROR = 22 -OD_FCLK_ERROR = 23 -OD_OP_TEMP_ERROR = 24 -OD_OP_GFX_EDC_ERROR = 25 -OD_OP_GFX_PCC_ERROR = 26 -OD_POWER_FEATURE_CTRL_ERROR = 27 -c__EA_OD_FAIL_e = ctypes.c_uint32 # enum -OD_FAIL_e = c__EA_OD_FAIL_e -OD_FAIL_e__enumvalues = c__EA_OD_FAIL_e__enumvalues -class struct_c__SA_OverDriveTable_t(Structure): - pass - -struct_c__SA_OverDriveTable_t._pack_ = 1 # source:False -struct_c__SA_OverDriveTable_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('VddGfxVmax', ctypes.c_uint16), - ('VddSocVmax', ctypes.c_uint16), - ('IdlePwrSavingFeaturesCtrl', ctypes.c_ubyte), - ('RuntimePwrSavingFeaturesCtrl', ctypes.c_ubyte), - ('Padding', ctypes.c_uint16), - ('GfxclkFoffset', ctypes.c_int16), - ('Padding1', ctypes.c_uint16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('FclkFmin', ctypes.c_uint16), - ('FclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('AdvancedOdModeEnabled', ctypes.c_ubyte), - ('Padding2', ctypes.c_ubyte * 3), - ('GfxVoltageFullCtrlMode', ctypes.c_uint16), - ('SocVoltageFullCtrlMode', ctypes.c_uint16), - ('GfxclkFullCtrlMode', ctypes.c_uint16), - ('UclkFullCtrlMode', ctypes.c_uint16), - ('FclkFullCtrlMode', ctypes.c_uint16), - ('Padding3', ctypes.c_uint16), - ('GfxEdc', ctypes.c_int16), - ('GfxPccLimitControl', ctypes.c_int16), - ('GfxclkFmaxVmax', ctypes.c_uint16), - ('GfxclkFmaxVmaxTemperature', ctypes.c_ubyte), - ('Padding4', ctypes.c_ubyte * 1), - ('Spare', ctypes.c_uint32 * 9), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -OverDriveTable_t = struct_c__SA_OverDriveTable_t -class struct_c__SA_OverDriveTableExternal_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('OverDriveTable', OverDriveTable_t), - ] - -OverDriveTableExternal_t = struct_c__SA_OverDriveTableExternal_t -class struct_c__SA_OverDriveLimits_t(Structure): - pass - -struct_c__SA_OverDriveLimits_t._pack_ = 1 # source:False -struct_c__SA_OverDriveLimits_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('VddGfxVmax', ctypes.c_uint16), - ('VddSocVmax', ctypes.c_uint16), - ('GfxclkFoffset', ctypes.c_int16), - ('Padding', ctypes.c_uint16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('FclkFmin', ctypes.c_uint16), - ('FclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Padding1', ctypes.c_ubyte * 2), - ('GfxVoltageFullCtrlMode', ctypes.c_uint16), - ('SocVoltageFullCtrlMode', ctypes.c_uint16), - ('GfxclkFullCtrlMode', ctypes.c_uint16), - ('UclkFullCtrlMode', ctypes.c_uint16), - ('FclkFullCtrlMode', ctypes.c_uint16), - ('GfxEdc', ctypes.c_int16), - ('GfxPccLimitControl', ctypes.c_int16), - ('Padding2', ctypes.c_int16), - ('Spare', ctypes.c_uint32 * 5), -] - -OverDriveLimits_t = struct_c__SA_OverDriveLimits_t - -# values for enumeration 'c__EA_BOARD_GPIO_TYPE_e' -c__EA_BOARD_GPIO_TYPE_e__enumvalues = { - 0: 'BOARD_GPIO_SMUIO_0', - 1: 'BOARD_GPIO_SMUIO_1', - 2: 'BOARD_GPIO_SMUIO_2', - 3: 'BOARD_GPIO_SMUIO_3', - 4: 'BOARD_GPIO_SMUIO_4', - 5: 'BOARD_GPIO_SMUIO_5', - 6: 'BOARD_GPIO_SMUIO_6', - 7: 'BOARD_GPIO_SMUIO_7', - 8: 'BOARD_GPIO_SMUIO_8', - 9: 'BOARD_GPIO_SMUIO_9', - 10: 'BOARD_GPIO_SMUIO_10', - 11: 'BOARD_GPIO_SMUIO_11', - 12: 'BOARD_GPIO_SMUIO_12', - 13: 'BOARD_GPIO_SMUIO_13', - 14: 'BOARD_GPIO_SMUIO_14', - 15: 'BOARD_GPIO_SMUIO_15', - 16: 'BOARD_GPIO_SMUIO_16', - 17: 'BOARD_GPIO_SMUIO_17', - 18: 'BOARD_GPIO_SMUIO_18', - 19: 'BOARD_GPIO_SMUIO_19', - 20: 'BOARD_GPIO_SMUIO_20', - 21: 'BOARD_GPIO_SMUIO_21', - 22: 'BOARD_GPIO_SMUIO_22', - 23: 'BOARD_GPIO_SMUIO_23', - 24: 'BOARD_GPIO_SMUIO_24', - 25: 'BOARD_GPIO_SMUIO_25', - 26: 'BOARD_GPIO_SMUIO_26', - 27: 'BOARD_GPIO_SMUIO_27', - 28: 'BOARD_GPIO_SMUIO_28', - 29: 'BOARD_GPIO_SMUIO_29', - 30: 'BOARD_GPIO_SMUIO_30', - 31: 'BOARD_GPIO_SMUIO_31', - 32: 'MAX_BOARD_GPIO_SMUIO_NUM', - 33: 'BOARD_GPIO_DC_GEN_A', - 34: 'BOARD_GPIO_DC_GEN_B', - 35: 'BOARD_GPIO_DC_GEN_C', - 36: 'BOARD_GPIO_DC_GEN_D', - 37: 'BOARD_GPIO_DC_GEN_E', - 38: 'BOARD_GPIO_DC_GEN_F', - 39: 'BOARD_GPIO_DC_GEN_G', - 40: 'BOARD_GPIO_DC_GENLK_CLK', - 41: 'BOARD_GPIO_DC_GENLK_VSYNC', - 42: 'BOARD_GPIO_DC_SWAPLOCK_A', - 43: 'BOARD_GPIO_DC_SWAPLOCK_B', - 44: 'MAX_BOARD_DC_GPIO_NUM', - 45: 'BOARD_GPIO_LV_EN', -} -BOARD_GPIO_SMUIO_0 = 0 -BOARD_GPIO_SMUIO_1 = 1 -BOARD_GPIO_SMUIO_2 = 2 -BOARD_GPIO_SMUIO_3 = 3 -BOARD_GPIO_SMUIO_4 = 4 -BOARD_GPIO_SMUIO_5 = 5 -BOARD_GPIO_SMUIO_6 = 6 -BOARD_GPIO_SMUIO_7 = 7 -BOARD_GPIO_SMUIO_8 = 8 -BOARD_GPIO_SMUIO_9 = 9 -BOARD_GPIO_SMUIO_10 = 10 -BOARD_GPIO_SMUIO_11 = 11 -BOARD_GPIO_SMUIO_12 = 12 -BOARD_GPIO_SMUIO_13 = 13 -BOARD_GPIO_SMUIO_14 = 14 -BOARD_GPIO_SMUIO_15 = 15 -BOARD_GPIO_SMUIO_16 = 16 -BOARD_GPIO_SMUIO_17 = 17 -BOARD_GPIO_SMUIO_18 = 18 -BOARD_GPIO_SMUIO_19 = 19 -BOARD_GPIO_SMUIO_20 = 20 -BOARD_GPIO_SMUIO_21 = 21 -BOARD_GPIO_SMUIO_22 = 22 -BOARD_GPIO_SMUIO_23 = 23 -BOARD_GPIO_SMUIO_24 = 24 -BOARD_GPIO_SMUIO_25 = 25 -BOARD_GPIO_SMUIO_26 = 26 -BOARD_GPIO_SMUIO_27 = 27 -BOARD_GPIO_SMUIO_28 = 28 -BOARD_GPIO_SMUIO_29 = 29 -BOARD_GPIO_SMUIO_30 = 30 -BOARD_GPIO_SMUIO_31 = 31 -MAX_BOARD_GPIO_SMUIO_NUM = 32 -BOARD_GPIO_DC_GEN_A = 33 -BOARD_GPIO_DC_GEN_B = 34 -BOARD_GPIO_DC_GEN_C = 35 -BOARD_GPIO_DC_GEN_D = 36 -BOARD_GPIO_DC_GEN_E = 37 -BOARD_GPIO_DC_GEN_F = 38 -BOARD_GPIO_DC_GEN_G = 39 -BOARD_GPIO_DC_GENLK_CLK = 40 -BOARD_GPIO_DC_GENLK_VSYNC = 41 -BOARD_GPIO_DC_SWAPLOCK_A = 42 -BOARD_GPIO_DC_SWAPLOCK_B = 43 -MAX_BOARD_DC_GPIO_NUM = 44 -BOARD_GPIO_LV_EN = 45 -c__EA_BOARD_GPIO_TYPE_e = ctypes.c_uint32 # enum -BOARD_GPIO_TYPE_e = c__EA_BOARD_GPIO_TYPE_e -BOARD_GPIO_TYPE_e__enumvalues = c__EA_BOARD_GPIO_TYPE_e__enumvalues -class struct_c__SA_BootValues_t(Structure): - pass - -struct_c__SA_BootValues_t._pack_ = 1 # source:False -struct_c__SA_BootValues_t._fields_ = [ - ('InitImuClk', ctypes.c_uint16), - ('InitSocclk', ctypes.c_uint16), - ('InitMpioclk', ctypes.c_uint16), - ('InitSmnclk', ctypes.c_uint16), - ('InitDispClk', ctypes.c_uint16), - ('InitDppClk', ctypes.c_uint16), - ('InitDprefclk', ctypes.c_uint16), - ('InitDcfclk', ctypes.c_uint16), - ('InitDtbclk', ctypes.c_uint16), - ('InitDbguSocClk', ctypes.c_uint16), - ('InitGfxclk_bypass', ctypes.c_uint16), - ('InitMp1clk', ctypes.c_uint16), - ('InitLclk', ctypes.c_uint16), - ('InitDbguBacoClk', ctypes.c_uint16), - ('InitBaco400clk', ctypes.c_uint16), - ('InitBaco1200clk_bypass', ctypes.c_uint16), - ('InitBaco700clk_bypass', ctypes.c_uint16), - ('InitBaco500clk', ctypes.c_uint16), - ('InitDclk0', ctypes.c_uint16), - ('InitVclk0', ctypes.c_uint16), - ('InitFclk', ctypes.c_uint16), - ('Padding1', ctypes.c_uint16), - ('InitUclkLevel', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('InitVcoFreqPll0', ctypes.c_uint32), - ('InitVcoFreqPll1', ctypes.c_uint32), - ('InitVcoFreqPll2', ctypes.c_uint32), - ('InitVcoFreqPll3', ctypes.c_uint32), - ('InitVcoFreqPll4', ctypes.c_uint32), - ('InitVcoFreqPll5', ctypes.c_uint32), - ('InitVcoFreqPll6', ctypes.c_uint32), - ('InitVcoFreqPll7', ctypes.c_uint32), - ('InitVcoFreqPll8', ctypes.c_uint32), - ('InitGfx', ctypes.c_uint16), - ('InitSoc', ctypes.c_uint16), - ('InitVddIoMem', ctypes.c_uint16), - ('InitVddCiMem', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 8), -] - -BootValues_t = struct_c__SA_BootValues_t -class struct_c__SA_MsgLimits_t(Structure): - pass - -struct_c__SA_MsgLimits_t._pack_ = 1 # source:False -struct_c__SA_MsgLimits_t._fields_ = [ - ('Power', ctypes.c_uint16 * 2 * 4), - ('Tdc', ctypes.c_uint16 * 2), - ('Temperature', ctypes.c_uint16 * 12), - ('PwmLimitMin', ctypes.c_ubyte), - ('PwmLimitMax', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_ubyte), - ('Spare1', ctypes.c_ubyte * 1), - ('AcousticTargetRpmThresholdMin', ctypes.c_uint16), - ('AcousticTargetRpmThresholdMax', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMin', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMax', ctypes.c_uint16), - ('PccLimitMin', ctypes.c_uint16), - ('PccLimitMax', ctypes.c_uint16), - ('FanStopTempMin', ctypes.c_uint16), - ('FanStopTempMax', ctypes.c_uint16), - ('FanStartTempMin', ctypes.c_uint16), - ('FanStartTempMax', ctypes.c_uint16), - ('PowerMinPpt0', ctypes.c_uint16 * 2), - ('Spare', ctypes.c_uint32 * 11), -] - -MsgLimits_t = struct_c__SA_MsgLimits_t -class struct_c__SA_DriverReportedClocks_t(Structure): - pass - -struct_c__SA_DriverReportedClocks_t._pack_ = 1 # source:False -struct_c__SA_DriverReportedClocks_t._fields_ = [ - ('BaseClockAc', ctypes.c_uint16), - ('GameClockAc', ctypes.c_uint16), - ('BoostClockAc', ctypes.c_uint16), - ('BaseClockDc', ctypes.c_uint16), - ('GameClockDc', ctypes.c_uint16), - ('BoostClockDc', ctypes.c_uint16), - ('MaxReportedClock', ctypes.c_uint16), - ('Padding', ctypes.c_uint16), - ('Reserved', ctypes.c_uint32 * 3), -] - -DriverReportedClocks_t = struct_c__SA_DriverReportedClocks_t -class struct_c__SA_AvfsDcBtcParams_t(Structure): - pass - -struct_c__SA_AvfsDcBtcParams_t._pack_ = 1 # source:False -struct_c__SA_AvfsDcBtcParams_t._fields_ = [ - ('DcBtcEnabled', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('DcTol', ctypes.c_uint16), - ('DcBtcGb', ctypes.c_uint16), - ('DcBtcMin', ctypes.c_uint16), - ('DcBtcMax', ctypes.c_uint16), - ('DcBtcGbScalar', LinearInt_t), -] - -AvfsDcBtcParams_t = struct_c__SA_AvfsDcBtcParams_t -class struct_c__SA_AvfsFuseOverride_t(Structure): - pass - -struct_c__SA_AvfsFuseOverride_t._pack_ = 1 # source:False -struct_c__SA_AvfsFuseOverride_t._fields_ = [ - ('AvfsTemp', ctypes.c_uint16 * 2), - ('VftFMin', ctypes.c_uint16), - ('VInversion', ctypes.c_uint16), - ('qVft', struct_c__SA_QuadraticInt_t * 2), - ('qAvfsGb', QuadraticInt_t), - ('qAvfsGb2', QuadraticInt_t), -] - -AvfsFuseOverride_t = struct_c__SA_AvfsFuseOverride_t -class struct_c__SA_PFE_Settings_t(Structure): - pass - -struct_c__SA_PFE_Settings_t._pack_ = 1 # source:False -struct_c__SA_PFE_Settings_t._fields_ = [ - ('Version', ctypes.c_ubyte), - ('Spare8', ctypes.c_ubyte * 3), - ('FeaturesToRun', ctypes.c_uint32 * 2), - ('FwDStateMask', ctypes.c_uint32), - ('DebugOverrides', ctypes.c_uint32), - ('Spare', ctypes.c_uint32 * 2), -] - -PFE_Settings_t = struct_c__SA_PFE_Settings_t -class struct_c__SA_SkuTable_t(Structure): - pass - -struct_c__SA_SkuTable_t._pack_ = 1 # source:False -struct_c__SA_SkuTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('TotalPowerConfig', ctypes.c_ubyte), - ('CustomerVariant', ctypes.c_ubyte), - ('MemoryTemperatureTypeMask', ctypes.c_ubyte), - ('SmartShiftVersion', ctypes.c_ubyte), - ('SocketPowerLimitSpare', ctypes.c_ubyte * 10), - ('EnableLegacyPptLimit', ctypes.c_ubyte), - ('UseInputTelemetry', ctypes.c_ubyte), - ('SmartShiftMinReportedPptinDcs', ctypes.c_ubyte), - ('PaddingPpt', ctypes.c_ubyte * 7), - ('HwCtfTempLimit', ctypes.c_uint16), - ('PaddingInfra', ctypes.c_uint16), - ('FitControllerFailureRateLimit', ctypes.c_uint32), - ('FitControllerGfxDutyCycle', ctypes.c_uint32), - ('FitControllerSocDutyCycle', ctypes.c_uint32), - ('FitControllerSocOffset', ctypes.c_uint32), - ('GfxApccPlusResidencyLimit', ctypes.c_uint32), - ('ThrottlerControlMask', ctypes.c_uint32), - ('UlvVoltageOffset', ctypes.c_uint16 * 2), - ('Padding', ctypes.c_ubyte * 2), - ('DeepUlvVoltageOffsetSoc', ctypes.c_uint16), - ('DefaultMaxVoltage', ctypes.c_uint16 * 2), - ('BoostMaxVoltage', ctypes.c_uint16 * 2), - ('VminTempHystersis', ctypes.c_int16 * 2), - ('VminTempThreshold', ctypes.c_int16 * 2), - ('Vmin_Hot_T0', ctypes.c_uint16 * 2), - ('Vmin_Cold_T0', ctypes.c_uint16 * 2), - ('Vmin_Hot_Eol', ctypes.c_uint16 * 2), - ('Vmin_Cold_Eol', ctypes.c_uint16 * 2), - ('Vmin_Aging_Offset', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Hot', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Cold', ctypes.c_uint16 * 2), - ('VcBtcFixedVminAgingOffset', ctypes.c_uint16 * 2), - ('VcBtcVmin2PsmDegrationGb', ctypes.c_uint16 * 2), - ('VcBtcPsmA', ctypes.c_uint32 * 2), - ('VcBtcPsmB', ctypes.c_uint32 * 2), - ('VcBtcVminA', ctypes.c_uint32 * 2), - ('VcBtcVminB', ctypes.c_uint32 * 2), - ('PerPartVminEnabled', ctypes.c_ubyte * 2), - ('VcBtcEnabled', ctypes.c_ubyte * 2), - ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), - ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), - ('Gfx_Vmin_droop', QuadraticInt_t), - ('Soc_Vmin_droop', QuadraticInt_t), - ('SpareVmin', ctypes.c_uint32 * 6), - ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 11), - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 6), - ('FreqTableShadowUclk', ctypes.c_uint16 * 6), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint32 * 11), - ('GfxclkAibFmax', ctypes.c_uint16), - ('GfxDpmPadding', ctypes.c_uint16), - ('GfxclkFgfxoffEntry', ctypes.c_uint16), - ('GfxclkFgfxoffExitImu', ctypes.c_uint16), - ('GfxclkFgfxoffExitRlc', ctypes.c_uint16), - ('GfxclkThrottleClock', ctypes.c_uint16), - ('EnableGfxPowerStagesGpio', ctypes.c_ubyte), - ('GfxIdlePadding', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivEn', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivVal', ctypes.c_ubyte), - ('GfxOffEntryEarlyMGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayVal', ctypes.c_ubyte), - ('GfxclkFreqGfxUlv', ctypes.c_uint16), - ('GfxIdlePadding2', ctypes.c_ubyte * 2), - ('GfxOffEntryHysteresis', ctypes.c_uint32), - ('GfxoffSpare', ctypes.c_uint32 * 15), - ('DfllMstrOscConfigA', ctypes.c_uint16), - ('DfllSlvOscConfigA', ctypes.c_uint16), - ('DfllBtcMasterScalerM', ctypes.c_uint32), - ('DfllBtcMasterScalerB', ctypes.c_int32), - ('DfllBtcSlaveScalerM', ctypes.c_uint32), - ('DfllBtcSlaveScalerB', ctypes.c_int32), - ('DfllPccAsWaitCtrl', ctypes.c_uint32), - ('DfllPccAsStepCtrl', ctypes.c_uint32), - ('GfxDfllSpare', ctypes.c_uint32 * 9), - ('DvoPsmDownThresholdVoltage', ctypes.c_uint32), - ('DvoPsmUpThresholdVoltage', ctypes.c_uint32), - ('DvoFmaxLowScaler', ctypes.c_uint32), - ('PaddingDcs', ctypes.c_uint32), - ('DcsMinGfxOffTime', ctypes.c_uint16), - ('DcsMaxGfxOffTime', ctypes.c_uint16), - ('DcsMinCreditAccum', ctypes.c_uint32), - ('DcsExitHysteresis', ctypes.c_uint16), - ('DcsTimeout', ctypes.c_uint16), - ('DcsPfGfxFopt', ctypes.c_uint32), - ('DcsPfUclkFopt', ctypes.c_uint32), - ('FoptEnabled', ctypes.c_ubyte), - ('DcsSpare2', ctypes.c_ubyte * 3), - ('DcsFoptM', ctypes.c_uint32), - ('DcsFoptB', ctypes.c_uint32), - ('DcsSpare', ctypes.c_uint32 * 9), - ('UseStrobeModeOptimizations', ctypes.c_ubyte), - ('PaddingMem', ctypes.c_ubyte * 3), - ('UclkDpmPstates', ctypes.c_ubyte * 6), - ('UclkDpmShadowPstates', ctypes.c_ubyte * 6), - ('FreqTableUclkDiv', ctypes.c_ubyte * 6), - ('FreqTableShadowUclkDiv', ctypes.c_ubyte * 6), - ('MemVmempVoltage', ctypes.c_uint16 * 6), - ('MemVddioVoltage', ctypes.c_uint16 * 6), - ('DalDcModeMaxUclkFreq', ctypes.c_uint16), - ('PaddingsMem', ctypes.c_ubyte * 2), - ('PaddingFclk', ctypes.c_uint32), - ('PcieGenSpeed', ctypes.c_ubyte * 3), - ('PcieLaneCount', ctypes.c_ubyte * 3), - ('LclkFreq', ctypes.c_uint16 * 3), - ('OverrideGfxAvfsFuses', ctypes.c_ubyte), - ('GfxAvfsPadding', ctypes.c_ubyte * 1), - ('DroopGBStDev', ctypes.c_uint16), - ('SocHwRtAvfsFuses', ctypes.c_uint32 * 32), - ('GfxL2HwRtAvfsFuses', ctypes.c_uint32 * 32), - ('PsmDidt_Vcross', ctypes.c_uint16 * 2), - ('PsmDidt_StaticDroop_A', ctypes.c_uint32 * 3), - ('PsmDidt_StaticDroop_B', ctypes.c_uint32 * 3), - ('PsmDidt_DynDroop_A', ctypes.c_uint32 * 3), - ('PsmDidt_DynDroop_B', ctypes.c_uint32 * 3), - ('spare_HwRtAvfsFuses', ctypes.c_uint32 * 19), - ('SocCommonRtAvfs', ctypes.c_uint32 * 13), - ('GfxCommonRtAvfs', ctypes.c_uint32 * 13), - ('SocFwRtAvfsFuses', ctypes.c_uint32 * 19), - ('GfxL2FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('spare_FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('Soc_Droop_PWL_F', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_a', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_b', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_c', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_F', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_a', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_b', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_c', ctypes.c_uint32 * 5), - ('Gfx_Static_PWL_Offset', ctypes.c_uint32 * 5), - ('Soc_Static_PWL_Offset', ctypes.c_uint32 * 5), - ('dGbV_dT_vmin', ctypes.c_uint32), - ('dGbV_dT_vmax', ctypes.c_uint32), - ('PaddingV2F', ctypes.c_uint32 * 4), - ('DcBtcGfxParams', AvfsDcBtcParams_t), - ('SSCurve_GFX', QuadraticInt_t), - ('GfxAvfsSpare', ctypes.c_uint32 * 29), - ('OverrideSocAvfsFuses', ctypes.c_ubyte), - ('MinSocAvfsRevision', ctypes.c_ubyte), - ('SocAvfsPadding', ctypes.c_ubyte * 2), - ('SocAvfsFuseOverride', struct_c__SA_AvfsFuseOverride_t * 1), - ('dBtcGbSoc', struct_c__SA_DroopInt_t * 1), - ('qAgingGb', struct_c__SA_LinearInt_t * 1), - ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 1), - ('DcBtcSocParams', struct_c__SA_AvfsDcBtcParams_t * 1), - ('SSCurve_SOC', QuadraticInt_t), - ('SocAvfsSpare', ctypes.c_uint32 * 29), - ('BootValues', BootValues_t), - ('DriverReportedClocks', DriverReportedClocks_t), - ('MsgLimits', MsgLimits_t), - ('OverDriveLimitsBasicMin', OverDriveLimits_t), - ('OverDriveLimitsBasicMax', OverDriveLimits_t), - ('OverDriveLimitsAdvancedMin', OverDriveLimits_t), - ('OverDriveLimitsAdvancedMax', OverDriveLimits_t), - ('TotalBoardPowerSupport', ctypes.c_ubyte), - ('TotalBoardPowerPadding', ctypes.c_ubyte * 1), - ('TotalBoardPowerRoc', ctypes.c_uint16), - ('qFeffCoeffGameClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBaseClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBoostClock', struct_c__SA_QuadraticInt_t * 2), - ('AptUclkGfxclkLookup', ctypes.c_int32 * 6 * 2), - ('AptUclkGfxclkLookupHyst', ctypes.c_uint32 * 6 * 2), - ('AptPadding', ctypes.c_uint32), - ('GfxXvminDidtDroopThresh', QuadraticInt_t), - ('GfxXvminDidtResetDDWait', ctypes.c_uint32), - ('GfxXvminDidtClkStopWait', ctypes.c_uint32), - ('GfxXvminDidtFcsStepCtrl', ctypes.c_uint32), - ('GfxXvminDidtFcsWaitCtrl', ctypes.c_uint32), - ('PsmModeEnabled', ctypes.c_uint32), - ('P2v_a', ctypes.c_uint32), - ('P2v_b', ctypes.c_uint32), - ('P2v_c', ctypes.c_uint32), - ('T2p_a', ctypes.c_uint32), - ('T2p_b', ctypes.c_uint32), - ('T2p_c', ctypes.c_uint32), - ('P2vTemp', ctypes.c_uint32), - ('PsmDidtStaticSettings', QuadraticInt_t), - ('PsmDidtDynamicSettings', QuadraticInt_t), - ('PsmDidtAvgDiv', ctypes.c_ubyte), - ('PsmDidtForceStall', ctypes.c_ubyte), - ('PsmDidtReleaseTimer', ctypes.c_uint16), - ('PsmDidtStallPattern', ctypes.c_uint32), - ('CacEdcCacLeakageC0', ctypes.c_uint32), - ('CacEdcCacLeakageC1', ctypes.c_uint32), - ('CacEdcCacLeakageC2', ctypes.c_uint32), - ('CacEdcCacLeakageC3', ctypes.c_uint32), - ('CacEdcCacLeakageC4', ctypes.c_uint32), - ('CacEdcCacLeakageC5', ctypes.c_uint32), - ('CacEdcGfxClkScalar', ctypes.c_uint32), - ('CacEdcGfxClkIntercept', ctypes.c_uint32), - ('CacEdcCac_m', ctypes.c_uint32), - ('CacEdcCac_b', ctypes.c_uint32), - ('CacEdcCurrLimitGuardband', ctypes.c_uint32), - ('CacEdcDynToTotalCacRatio', ctypes.c_uint32), - ('XVmin_Gfx_EdcThreshScalar', ctypes.c_uint32), - ('XVmin_Gfx_EdcEnableFreq', ctypes.c_uint32), - ('XVmin_Gfx_EdcPccAsStepCtrl', ctypes.c_uint32), - ('XVmin_Gfx_EdcPccAsWaitCtrl', ctypes.c_uint32), - ('XVmin_Gfx_EdcThreshold', ctypes.c_uint16), - ('XVmin_Gfx_EdcFiltHysWaitCtrl', ctypes.c_uint16), - ('XVmin_Soc_EdcThreshScalar', ctypes.c_uint32), - ('XVmin_Soc_EdcEnableFreq', ctypes.c_uint32), - ('XVmin_Soc_EdcThreshold', ctypes.c_uint32), - ('XVmin_Soc_EdcStepUpTime', ctypes.c_uint16), - ('XVmin_Soc_EdcStepDownTime', ctypes.c_uint16), - ('XVmin_Soc_EdcInitPccStep', ctypes.c_ubyte), - ('PaddingSocEdc', ctypes.c_ubyte * 3), - ('GfxXvminFuseOverride', ctypes.c_ubyte), - ('SocXvminFuseOverride', ctypes.c_ubyte), - ('PaddingXvminFuseOverride', ctypes.c_ubyte * 2), - ('GfxXvminFddTempLow', ctypes.c_ubyte), - ('GfxXvminFddTempHigh', ctypes.c_ubyte), - ('SocXvminFddTempLow', ctypes.c_ubyte), - ('SocXvminFddTempHigh', ctypes.c_ubyte), - ('GfxXvminFddVolt0', ctypes.c_uint16), - ('GfxXvminFddVolt1', ctypes.c_uint16), - ('GfxXvminFddVolt2', ctypes.c_uint16), - ('SocXvminFddVolt0', ctypes.c_uint16), - ('SocXvminFddVolt1', ctypes.c_uint16), - ('SocXvminFddVolt2', ctypes.c_uint16), - ('GfxXvminDsFddDsm', ctypes.c_uint16 * 6), - ('GfxXvminEdcFddDsm', ctypes.c_uint16 * 6), - ('SocXvminEdcFddDsm', ctypes.c_uint16 * 6), - ('Spare', ctypes.c_uint32), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SkuTable_t = struct_c__SA_SkuTable_t -class struct_c__SA_Svi3RegulatorSettings_t(Structure): - pass - -struct_c__SA_Svi3RegulatorSettings_t._pack_ = 1 # source:False -struct_c__SA_Svi3RegulatorSettings_t._fields_ = [ - ('SlewRateConditions', ctypes.c_ubyte), - ('LoadLineAdjust', ctypes.c_ubyte), - ('VoutOffset', ctypes.c_ubyte), - ('VidMax', ctypes.c_ubyte), - ('VidMin', ctypes.c_ubyte), - ('TenBitTelEn', ctypes.c_ubyte), - ('SixteenBitTelEn', ctypes.c_ubyte), - ('OcpThresh', ctypes.c_ubyte), - ('OcpWarnThresh', ctypes.c_ubyte), - ('OcpSettings', ctypes.c_ubyte), - ('VrhotThresh', ctypes.c_ubyte), - ('OtpThresh', ctypes.c_ubyte), - ('UvpOvpDeltaRef', ctypes.c_ubyte), - ('PhaseShed', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 10), - ('SettingOverrideMask', ctypes.c_uint32), -] - -Svi3RegulatorSettings_t = struct_c__SA_Svi3RegulatorSettings_t -class struct_c__SA_BoardTable_t(Structure): - pass - -struct_c__SA_BoardTable_t._pack_ = 1 # source:False -struct_c__SA_BoardTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), - ('SlaveAddrMapping', ctypes.c_ubyte * 4), - ('VrPsiSupport', ctypes.c_ubyte * 4), - ('Svi3SvcSpeed', ctypes.c_uint32), - ('EnablePsi6', ctypes.c_ubyte * 4), - ('Svi3RegSettings', struct_c__SA_Svi3RegulatorSettings_t * 4), - ('LedOffGpio', ctypes.c_ubyte), - ('FanOffGpio', ctypes.c_ubyte), - ('GfxVrPowerStageOffGpio', ctypes.c_ubyte), - ('AcDcGpio', ctypes.c_ubyte), - ('AcDcPolarity', ctypes.c_ubyte), - ('VR0HotGpio', ctypes.c_ubyte), - ('VR0HotPolarity', ctypes.c_ubyte), - ('GthrGpio', ctypes.c_ubyte), - ('GthrPolarity', ctypes.c_ubyte), - ('LedPin0', ctypes.c_ubyte), - ('LedPin1', ctypes.c_ubyte), - ('LedPin2', ctypes.c_ubyte), - ('LedEnableMask', ctypes.c_ubyte), - ('LedPcie', ctypes.c_ubyte), - ('LedError', ctypes.c_ubyte), - ('PaddingLed', ctypes.c_ubyte), - ('UclkTrainingModeSpreadPercent', ctypes.c_ubyte), - ('UclkSpreadPadding', ctypes.c_ubyte), - ('UclkSpreadFreq', ctypes.c_uint16), - ('UclkSpreadPercent', ctypes.c_ubyte * 16), - ('GfxclkSpreadEnable', ctypes.c_ubyte), - ('FclkSpreadPercent', ctypes.c_ubyte), - ('FclkSpreadFreq', ctypes.c_uint16), - ('DramWidth', ctypes.c_ubyte), - ('PaddingMem1', ctypes.c_ubyte * 7), - ('HsrEnabled', ctypes.c_ubyte), - ('VddqOffEnabled', ctypes.c_ubyte), - ('PaddingUmcFlags', ctypes.c_ubyte * 2), - ('Paddign1', ctypes.c_uint32), - ('BacoEntryDelay', ctypes.c_uint32), - ('FuseWritePowerMuxPresent', ctypes.c_ubyte), - ('FuseWritePadding', ctypes.c_ubyte * 3), - ('LoadlineGfx', ctypes.c_uint32), - ('LoadlineSoc', ctypes.c_uint32), - ('GfxEdcLimit', ctypes.c_uint32), - ('SocEdcLimit', ctypes.c_uint32), - ('RestBoardPower', ctypes.c_uint32), - ('ConnectorsImpedance', ctypes.c_uint32), - ('EpcsSens0', ctypes.c_ubyte), - ('EpcsSens1', ctypes.c_ubyte), - ('PaddingEpcs', ctypes.c_ubyte * 2), - ('BoardSpare', ctypes.c_uint32 * 52), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -BoardTable_t = struct_c__SA_BoardTable_t -class struct_c__SA_CustomSkuTable_t(Structure): - pass - -struct_c__SA_CustomSkuTable_t._pack_ = 1 # source:False -struct_c__SA_CustomSkuTable_t._fields_ = [ - ('SocketPowerLimitAc', ctypes.c_uint16 * 4), - ('VrTdcLimit', ctypes.c_uint16 * 2), - ('TotalIdleBoardPowerM', ctypes.c_int16), - ('TotalIdleBoardPowerB', ctypes.c_int16), - ('TotalBoardPowerM', ctypes.c_int16), - ('TotalBoardPowerB', ctypes.c_int16), - ('TemperatureLimit', ctypes.c_uint16 * 12), - ('FanStopTemp', ctypes.c_uint16 * 12), - ('FanStartTemp', ctypes.c_uint16 * 12), - ('FanGain', ctypes.c_uint16 * 12), - ('FanPwmMin', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanMaximumRpm', ctypes.c_uint16), - ('MGpuAcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetGfxclk', ctypes.c_uint16), - ('TempInputSelectMask', ctypes.c_uint32), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanTachEdgePerRev', ctypes.c_ubyte), - ('FanPadding', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16 * 12), - ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), - ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), - ('FuzzyFan_PwmSetDelta', ctypes.c_int16), - ('FanPadding2', ctypes.c_uint16), - ('FwCtfLimit', ctypes.c_uint16 * 12), - ('IntakeTempEnableRPM', ctypes.c_uint16), - ('IntakeTempOffsetTemp', ctypes.c_int16), - ('IntakeTempReleaseTemp', ctypes.c_uint16), - ('IntakeTempHighIntakeAcousticLimit', ctypes.c_uint16), - ('IntakeTempAcouticLimitReleaseRate', ctypes.c_uint16), - ('FanAbnormalTempLimitOffset', ctypes.c_int16), - ('FanStalledTriggerRpm', ctypes.c_uint16), - ('FanAbnormalTriggerRpmCoeff', ctypes.c_uint16), - ('FanSpare', ctypes.c_uint16 * 1), - ('FanIntakeSensorSupport', ctypes.c_ubyte), - ('FanIntakePadding', ctypes.c_ubyte), - ('FanSpare2', ctypes.c_uint32 * 12), - ('ODFeatureCtrlMask', ctypes.c_uint32), - ('TemperatureLimit_Hynix', ctypes.c_uint16), - ('TemperatureLimit_Micron', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Hynix', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Micron', ctypes.c_uint16), - ('PlatformTdcLimit', ctypes.c_uint16 * 2), - ('SocketPowerLimitDc', ctypes.c_uint16 * 4), - ('SocketPowerLimitSmartShift2', ctypes.c_uint16), - ('CustomSkuSpare16b', ctypes.c_uint16), - ('CustomSkuSpare32b', ctypes.c_uint32 * 10), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -CustomSkuTable_t = struct_c__SA_CustomSkuTable_t -class struct_c__SA_PPTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('PFE_Settings', PFE_Settings_t), - ('SkuTable', SkuTable_t), - ('CustomSkuTable', CustomSkuTable_t), - ('BoardTable', BoardTable_t), - ] - -PPTable_t = struct_c__SA_PPTable_t -class struct_c__SA_DriverSmuConfig_t(Structure): - pass - -struct_c__SA_DriverSmuConfig_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfig_t._fields_ = [ - ('GfxclkAverageLpfTau', ctypes.c_uint16), - ('FclkAverageLpfTau', ctypes.c_uint16), - ('UclkAverageLpfTau', ctypes.c_uint16), - ('GfxActivityLpfTau', ctypes.c_uint16), - ('UclkActivityLpfTau', ctypes.c_uint16), - ('UclkMaxActivityLpfTau', ctypes.c_uint16), - ('SocketPowerLpfTau', ctypes.c_uint16), - ('VcnClkAverageLpfTau', ctypes.c_uint16), - ('VcnUsageAverageLpfTau', ctypes.c_uint16), - ('PcieActivityLpTau', ctypes.c_uint16), -] - -DriverSmuConfig_t = struct_c__SA_DriverSmuConfig_t -class struct_c__SA_DriverSmuConfigExternal_t(Structure): - pass - -struct_c__SA_DriverSmuConfigExternal_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfigExternal_t._fields_ = [ - ('DriverSmuConfig', DriverSmuConfig_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverSmuConfigExternal_t = struct_c__SA_DriverSmuConfigExternal_t -class struct_c__SA_DriverInfoTable_t(Structure): - pass - -struct_c__SA_DriverInfoTable_t._pack_ = 1 # source:False -struct_c__SA_DriverInfoTable_t._fields_ = [ - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 6), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint16 * 11), - ('Padding', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 32), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverInfoTable_t = struct_c__SA_DriverInfoTable_t -class struct_c__SA_SmuMetrics_t(Structure): - pass - -struct_c__SA_SmuMetrics_t._pack_ = 1 # source:False -struct_c__SA_SmuMetrics_t._fields_ = [ - ('CurrClock', ctypes.c_uint32 * 11), - ('AverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('AverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('AverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('AverageFclkFrequencyPreDs', ctypes.c_uint16), - ('AverageFclkFrequencyPostDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('AverageVclk0Frequency', ctypes.c_uint16), - ('AverageDclk0Frequency', ctypes.c_uint16), - ('AverageVclk1Frequency', ctypes.c_uint16), - ('AverageDclk1Frequency', ctypes.c_uint16), - ('AveragePCIeBusy', ctypes.c_uint16), - ('dGPU_W_MAX', ctypes.c_uint16), - ('padding', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageFclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageFclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageVclk0Frequency', ctypes.c_uint16), - ('MovingAverageDclk0Frequency', ctypes.c_uint16), - ('MovingAverageGfxActivity', ctypes.c_uint16), - ('MovingAverageUclkActivity', ctypes.c_uint16), - ('MovingAverageVcn0ActivityPercentage', ctypes.c_uint16), - ('MovingAveragePCIeBusy', ctypes.c_uint16), - ('MovingAverageUclkActivity_MAX', ctypes.c_uint16), - ('MovingAverageSocketPower', ctypes.c_uint16), - ('MovingAveragePadding', ctypes.c_uint16), - ('MetricsCounter', ctypes.c_uint32), - ('AvgVoltage', ctypes.c_uint16 * 4), - ('AvgCurrent', ctypes.c_uint16 * 4), - ('AverageGfxActivity', ctypes.c_uint16), - ('AverageUclkActivity', ctypes.c_uint16), - ('AverageVcn0ActivityPercentage', ctypes.c_uint16), - ('Vcn1ActivityPercentage', ctypes.c_uint16), - ('EnergyAccumulator', ctypes.c_uint32), - ('AverageSocketPower', ctypes.c_uint16), - ('AverageTotalBoardPower', ctypes.c_uint16), - ('AvgTemperature', ctypes.c_uint16 * 12), - ('AvgTemperatureFanIntake', ctypes.c_uint16), - ('PcieRate', ctypes.c_ubyte), - ('PcieWidth', ctypes.c_ubyte), - ('AvgFanPwm', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 1), - ('AvgFanRpm', ctypes.c_uint16), - ('ThrottlingPercentage', ctypes.c_ubyte * 21), - ('VmaxThrottlingPercentage', ctypes.c_ubyte), - ('padding1', ctypes.c_ubyte * 2), - ('D3HotEntryCountPerMode', ctypes.c_uint32 * 4), - ('D3HotExitCountPerMode', ctypes.c_uint32 * 4), - ('ArmMsgReceivedCountPerMode', ctypes.c_uint32 * 4), - ('ApuSTAPMSmartShiftLimit', ctypes.c_uint16), - ('ApuSTAPMLimit', ctypes.c_uint16), - ('AvgApuSocketPower', ctypes.c_uint16), - ('AverageUclkActivity_MAX', ctypes.c_uint16), - ('PublicSerialNumberLower', ctypes.c_uint32), - ('PublicSerialNumberUpper', ctypes.c_uint32), -] - -SmuMetrics_t = struct_c__SA_SmuMetrics_t -class struct_c__SA_SmuMetricsExternal_t(Structure): - pass - -struct_c__SA_SmuMetricsExternal_t._pack_ = 1 # source:False -struct_c__SA_SmuMetricsExternal_t._fields_ = [ - ('SmuMetrics', SmuMetrics_t), - ('Spare', ctypes.c_uint32 * 30), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SmuMetricsExternal_t = struct_c__SA_SmuMetricsExternal_t -class struct_c__SA_WatermarkRowGeneric_t(Structure): - pass - -struct_c__SA_WatermarkRowGeneric_t._pack_ = 1 # source:False -struct_c__SA_WatermarkRowGeneric_t._fields_ = [ - ('WmSetting', ctypes.c_ubyte), - ('Flags', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 2), -] - -WatermarkRowGeneric_t = struct_c__SA_WatermarkRowGeneric_t - -# values for enumeration 'c__EA_WATERMARKS_FLAGS_e' -c__EA_WATERMARKS_FLAGS_e__enumvalues = { - 0: 'WATERMARKS_CLOCK_RANGE', - 1: 'WATERMARKS_DUMMY_PSTATE', - 2: 'WATERMARKS_MALL', - 3: 'WATERMARKS_COUNT', -} -WATERMARKS_CLOCK_RANGE = 0 -WATERMARKS_DUMMY_PSTATE = 1 -WATERMARKS_MALL = 2 -WATERMARKS_COUNT = 3 -c__EA_WATERMARKS_FLAGS_e = ctypes.c_uint32 # enum -WATERMARKS_FLAGS_e = c__EA_WATERMARKS_FLAGS_e -WATERMARKS_FLAGS_e__enumvalues = c__EA_WATERMARKS_FLAGS_e__enumvalues -class struct_c__SA_Watermarks_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('WatermarkRow', struct_c__SA_WatermarkRowGeneric_t * 4), - ] - -Watermarks_t = struct_c__SA_Watermarks_t -class struct_c__SA_WatermarksExternal_t(Structure): - pass - -struct_c__SA_WatermarksExternal_t._pack_ = 1 # source:False -struct_c__SA_WatermarksExternal_t._fields_ = [ - ('Watermarks', Watermarks_t), - ('Spare', ctypes.c_uint32 * 16), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -WatermarksExternal_t = struct_c__SA_WatermarksExternal_t -class struct_c__SA_AvfsDebugTable_t(Structure): - pass - -struct_c__SA_AvfsDebugTable_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTable_t._fields_ = [ - ('avgPsmCount', ctypes.c_uint16 * 76), - ('minPsmCount', ctypes.c_uint16 * 76), - ('maxPsmCount', ctypes.c_uint16 * 76), - ('avgPsmVoltage', ctypes.c_float * 76), - ('minPsmVoltage', ctypes.c_float * 76), - ('maxPsmVoltage', ctypes.c_float * 76), -] - -AvfsDebugTable_t = struct_c__SA_AvfsDebugTable_t -class struct_c__SA_AvfsDebugTableExternal_t(Structure): - pass - -struct_c__SA_AvfsDebugTableExternal_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTableExternal_t._fields_ = [ - ('AvfsDebugTable', AvfsDebugTable_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -AvfsDebugTableExternal_t = struct_c__SA_AvfsDebugTableExternal_t -class struct_c__SA_DpmActivityMonitorCoeffInt_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffInt_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffInt_t._fields_ = [ - ('Gfx_ActiveHystLimit', ctypes.c_ubyte), - ('Gfx_IdleHystLimit', ctypes.c_ubyte), - ('Gfx_FPS', ctypes.c_ubyte), - ('Gfx_MinActiveFreqType', ctypes.c_ubyte), - ('Gfx_BoosterFreqType', ctypes.c_ubyte), - ('PaddingGfx', ctypes.c_ubyte), - ('Gfx_MinActiveFreq', ctypes.c_uint16), - ('Gfx_BoosterFreq', ctypes.c_uint16), - ('Gfx_PD_Data_time_constant', ctypes.c_uint16), - ('Gfx_PD_Data_limit_a', ctypes.c_uint32), - ('Gfx_PD_Data_limit_b', ctypes.c_uint32), - ('Gfx_PD_Data_limit_c', ctypes.c_uint32), - ('Gfx_PD_Data_error_coeff', ctypes.c_uint32), - ('Gfx_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Fclk_ActiveHystLimit', ctypes.c_ubyte), - ('Fclk_IdleHystLimit', ctypes.c_ubyte), - ('Fclk_FPS', ctypes.c_ubyte), - ('Fclk_MinActiveFreqType', ctypes.c_ubyte), - ('Fclk_BoosterFreqType', ctypes.c_ubyte), - ('PaddingFclk', ctypes.c_ubyte), - ('Fclk_MinActiveFreq', ctypes.c_uint16), - ('Fclk_BoosterFreq', ctypes.c_uint16), - ('Fclk_PD_Data_time_constant', ctypes.c_uint16), - ('Fclk_PD_Data_limit_a', ctypes.c_uint32), - ('Fclk_PD_Data_limit_b', ctypes.c_uint32), - ('Fclk_PD_Data_limit_c', ctypes.c_uint32), - ('Fclk_PD_Data_error_coeff', ctypes.c_uint32), - ('Fclk_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Mem_UpThreshold_Limit', ctypes.c_uint32 * 6), - ('Mem_UpHystLimit', ctypes.c_ubyte * 6), - ('Mem_DownHystLimit', ctypes.c_uint16 * 6), - ('Mem_Fps', ctypes.c_uint16), -] - -DpmActivityMonitorCoeffInt_t = struct_c__SA_DpmActivityMonitorCoeffInt_t -class struct_c__SA_DpmActivityMonitorCoeffIntExternal_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._fields_ = [ - ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DpmActivityMonitorCoeffIntExternal_t = struct_c__SA_DpmActivityMonitorCoeffIntExternal_t -__AMDGPU_SMU_H__ = True # macro -int32_t = True # macro -uint32_t = True # macro -int8_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -int16_t = True # macro -uint64_t = True # macro -bool = True # macro -u32 = True # macro -SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 # macro -SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 # macro -SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 # macro -SMU_FW_NAME_LEN = 0x24 # macro -SMU_DPM_USER_PROFILE_RESTORE = (1<<0) # macro -SMU_CUSTOM_FAN_SPEED_RPM = (1<<1) # macro -SMU_CUSTOM_FAN_SPEED_PWM = (1<<2) # macro -SMU_THROTTLER_PPT0_BIT = 0 # macro -SMU_THROTTLER_PPT1_BIT = 1 # macro -SMU_THROTTLER_PPT2_BIT = 2 # macro -SMU_THROTTLER_PPT3_BIT = 3 # macro -SMU_THROTTLER_SPL_BIT = 4 # macro -SMU_THROTTLER_FPPT_BIT = 5 # macro -SMU_THROTTLER_SPPT_BIT = 6 # macro -SMU_THROTTLER_SPPT_APU_BIT = 7 # macro -SMU_THROTTLER_TDC_GFX_BIT = 16 # macro -SMU_THROTTLER_TDC_SOC_BIT = 17 # macro -SMU_THROTTLER_TDC_MEM_BIT = 18 # macro -SMU_THROTTLER_TDC_VDD_BIT = 19 # macro -SMU_THROTTLER_TDC_CVIP_BIT = 20 # macro -SMU_THROTTLER_EDC_CPU_BIT = 21 # macro -SMU_THROTTLER_EDC_GFX_BIT = 22 # macro -SMU_THROTTLER_APCC_BIT = 23 # macro -SMU_THROTTLER_TEMP_GPU_BIT = 32 # macro -SMU_THROTTLER_TEMP_CORE_BIT = 33 # macro -SMU_THROTTLER_TEMP_MEM_BIT = 34 # macro -SMU_THROTTLER_TEMP_EDGE_BIT = 35 # macro -SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 # macro -SMU_THROTTLER_TEMP_SOC_BIT = 37 # macro -SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 # macro -SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 # macro -SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 # macro -SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 # macro -SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 # macro -SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 # macro -SMU_THROTTLER_VRHOT0_BIT = 44 # macro -SMU_THROTTLER_VRHOT1_BIT = 45 # macro -SMU_THROTTLER_PROCHOT_CPU_BIT = 46 # macro -SMU_THROTTLER_PROCHOT_GFX_BIT = 47 # macro -SMU_THROTTLER_PPM_BIT = 56 # macro -SMU_THROTTLER_FIT_BIT = 57 # macro -# def SMU_TABLE_INIT(tables, table_id, s, a, d): # macro -# return {tables[table_id].size=s;tables[table_id].align=a;tables[table_id].domain=d;}(0) -class struct_smu_hw_power_state(Structure): - pass - -struct_smu_hw_power_state._pack_ = 1 # source:False -struct_smu_hw_power_state._fields_ = [ - ('magic', ctypes.c_uint32), -] - -class struct_smu_power_state(Structure): - pass - - -# values for enumeration 'smu_state_ui_label' -smu_state_ui_label__enumvalues = { - 0: 'SMU_STATE_UI_LABEL_NONE', - 1: 'SMU_STATE_UI_LABEL_BATTERY', - 2: 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 3: 'SMU_STATE_UI_LABEL_BALLANCED', - 4: 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', - 5: 'SMU_STATE_UI_LABEL_PERFORMANCE', - 6: 'SMU_STATE_UI_LABEL_BACO', -} -SMU_STATE_UI_LABEL_NONE = 0 -SMU_STATE_UI_LABEL_BATTERY = 1 -SMU_STATE_UI_TABEL_MIDDLE_LOW = 2 -SMU_STATE_UI_LABEL_BALLANCED = 3 -SMU_STATE_UI_LABEL_MIDDLE_HIGHT = 4 -SMU_STATE_UI_LABEL_PERFORMANCE = 5 -SMU_STATE_UI_LABEL_BACO = 6 -smu_state_ui_label = ctypes.c_uint32 # enum - -# values for enumeration 'smu_state_classification_flag' -smu_state_classification_flag__enumvalues = { - 1: 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 2: 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 4: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 8: 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 16: 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 32: 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 64: 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 128: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 256: 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 512: 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 1024: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 2048: 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 4096: 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 8192: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 16384: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', - 32768: 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 65536: 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 131072: 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 262144: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 524288: 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 1048576: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', -} -SMU_STATE_CLASSIFICATION_FLAG_BOOT = 1 -SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 2 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 4 -SMU_STATE_CLASSIFICATION_FLAG_RESET = 8 -SMU_STATE_CLASSIFICATION_FLAG_FORCED = 16 -SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 32 -SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 64 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 128 -SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 256 -SMU_STATE_CLASSIFICATION_FLAG_UVD = 512 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 1024 -SMU_STATE_CLASSIFICATION_FLAG_ACPI = 2048 -SMU_STATE_CLASSIFICATION_FLAG_HD2 = 4096 -SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 8192 -SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 16384 -SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 32768 -SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 65536 -SMU_STATE_CLASSIFICATION_FLAG_BACO = 131072 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 262144 -SMU_STATE_CLASSIFICATION_FLAG_ULV = 524288 -SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 1048576 -smu_state_classification_flag = ctypes.c_uint32 # enum -class struct_smu_state_classification_block(Structure): - pass - -struct_smu_state_classification_block._pack_ = 1 # source:False -struct_smu_state_classification_block._fields_ = [ - ('ui_label', smu_state_ui_label), - ('flags', smu_state_classification_flag), - ('bios_index', ctypes.c_int32), - ('temporary_state', ctypes.c_bool), - ('to_be_deleted', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_smu_state_pcie_block(Structure): - pass - -struct_smu_state_pcie_block._pack_ = 1 # source:False -struct_smu_state_pcie_block._fields_ = [ - ('lanes', ctypes.c_uint32), -] - - -# values for enumeration 'smu_refreshrate_source' -smu_refreshrate_source__enumvalues = { - 0: 'SMU_REFRESHRATE_SOURCE_EDID', - 1: 'SMU_REFRESHRATE_SOURCE_EXPLICIT', -} -SMU_REFRESHRATE_SOURCE_EDID = 0 -SMU_REFRESHRATE_SOURCE_EXPLICIT = 1 -smu_refreshrate_source = ctypes.c_uint32 # enum -class struct_smu_state_display_block(Structure): - pass - -struct_smu_state_display_block._pack_ = 1 # source:False -struct_smu_state_display_block._fields_ = [ - ('disable_frame_modulation', ctypes.c_bool), - ('limit_refreshrate', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), - ('refreshrate_source', smu_refreshrate_source), - ('explicit_refreshrate', ctypes.c_int32), - ('edid_refreshrate_index', ctypes.c_int32), - ('enable_vari_bright', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -class struct_smu_state_memory_block(Structure): - pass - -struct_smu_state_memory_block._pack_ = 1 # source:False -struct_smu_state_memory_block._fields_ = [ - ('dll_off', ctypes.c_bool), - ('m3arb', ctypes.c_ubyte), - ('unused', ctypes.c_ubyte * 3), -] - -class struct_smu_state_software_algorithm_block(Structure): - pass - -struct_smu_state_software_algorithm_block._pack_ = 1 # source:False -struct_smu_state_software_algorithm_block._fields_ = [ - ('disable_load_balancing', ctypes.c_bool), - ('enable_sleep_for_timestamps', ctypes.c_bool), -] - -class struct_smu_temperature_range(Structure): - pass - -struct_smu_temperature_range._pack_ = 1 # source:False -struct_smu_temperature_range._fields_ = [ - ('min', ctypes.c_int32), - ('max', ctypes.c_int32), - ('edge_emergency_max', ctypes.c_int32), - ('hotspot_min', ctypes.c_int32), - ('hotspot_crit_max', ctypes.c_int32), - ('hotspot_emergency_max', ctypes.c_int32), - ('mem_min', ctypes.c_int32), - ('mem_crit_max', ctypes.c_int32), - ('mem_emergency_max', ctypes.c_int32), - ('software_shutdown_temp', ctypes.c_int32), - ('software_shutdown_temp_offset', ctypes.c_int32), -] - -class struct_smu_state_validation_block(Structure): - pass - -struct_smu_state_validation_block._pack_ = 1 # source:False -struct_smu_state_validation_block._fields_ = [ - ('single_display_only', ctypes.c_bool), - ('disallow_on_dc', ctypes.c_bool), - ('supported_power_levels', ctypes.c_ubyte), -] - -class struct_smu_uvd_clocks(Structure): - pass - -struct_smu_uvd_clocks._pack_ = 1 # source:False -struct_smu_uvd_clocks._fields_ = [ - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), -] - - -# values for enumeration 'smu_power_src_type' -smu_power_src_type__enumvalues = { - 0: 'SMU_POWER_SOURCE_AC', - 1: 'SMU_POWER_SOURCE_DC', - 2: 'SMU_POWER_SOURCE_COUNT', -} -SMU_POWER_SOURCE_AC = 0 -SMU_POWER_SOURCE_DC = 1 -SMU_POWER_SOURCE_COUNT = 2 -smu_power_src_type = ctypes.c_uint32 # enum - -# values for enumeration 'smu_ppt_limit_type' -smu_ppt_limit_type__enumvalues = { - 0: 'SMU_DEFAULT_PPT_LIMIT', - 1: 'SMU_FAST_PPT_LIMIT', -} -SMU_DEFAULT_PPT_LIMIT = 0 -SMU_FAST_PPT_LIMIT = 1 -smu_ppt_limit_type = ctypes.c_uint32 # enum - -# values for enumeration 'smu_ppt_limit_level' -smu_ppt_limit_level__enumvalues = { - -1: 'SMU_PPT_LIMIT_MIN', - 0: 'SMU_PPT_LIMIT_CURRENT', - 1: 'SMU_PPT_LIMIT_DEFAULT', - 2: 'SMU_PPT_LIMIT_MAX', -} -SMU_PPT_LIMIT_MIN = -1 -SMU_PPT_LIMIT_CURRENT = 0 -SMU_PPT_LIMIT_DEFAULT = 1 -SMU_PPT_LIMIT_MAX = 2 -smu_ppt_limit_level = ctypes.c_int32 # enum - -# values for enumeration 'smu_memory_pool_size' -smu_memory_pool_size__enumvalues = { - 0: 'SMU_MEMORY_POOL_SIZE_ZERO', - 268435456: 'SMU_MEMORY_POOL_SIZE_256_MB', - 536870912: 'SMU_MEMORY_POOL_SIZE_512_MB', - 1073741824: 'SMU_MEMORY_POOL_SIZE_1_GB', - 2147483648: 'SMU_MEMORY_POOL_SIZE_2_GB', -} -SMU_MEMORY_POOL_SIZE_ZERO = 0 -SMU_MEMORY_POOL_SIZE_256_MB = 268435456 -SMU_MEMORY_POOL_SIZE_512_MB = 536870912 -SMU_MEMORY_POOL_SIZE_1_GB = 1073741824 -SMU_MEMORY_POOL_SIZE_2_GB = 2147483648 -smu_memory_pool_size = ctypes.c_uint32 # enum - -# values for enumeration 'smu_clk_type' -smu_clk_type__enumvalues = { - 0: 'SMU_GFXCLK', - 1: 'SMU_VCLK', - 2: 'SMU_DCLK', - 3: 'SMU_VCLK1', - 4: 'SMU_DCLK1', - 5: 'SMU_ECLK', - 6: 'SMU_SOCCLK', - 7: 'SMU_UCLK', - 8: 'SMU_DCEFCLK', - 9: 'SMU_DISPCLK', - 10: 'SMU_PIXCLK', - 11: 'SMU_PHYCLK', - 12: 'SMU_FCLK', - 13: 'SMU_SCLK', - 14: 'SMU_MCLK', - 15: 'SMU_PCIE', - 16: 'SMU_LCLK', - 17: 'SMU_OD_CCLK', - 18: 'SMU_OD_SCLK', - 19: 'SMU_OD_MCLK', - 20: 'SMU_OD_VDDC_CURVE', - 21: 'SMU_OD_RANGE', - 22: 'SMU_OD_VDDGFX_OFFSET', - 23: 'SMU_OD_FAN_CURVE', - 24: 'SMU_OD_ACOUSTIC_LIMIT', - 25: 'SMU_OD_ACOUSTIC_TARGET', - 26: 'SMU_OD_FAN_TARGET_TEMPERATURE', - 27: 'SMU_OD_FAN_MINIMUM_PWM', - 28: 'SMU_CLK_COUNT', -} -SMU_GFXCLK = 0 -SMU_VCLK = 1 -SMU_DCLK = 2 -SMU_VCLK1 = 3 -SMU_DCLK1 = 4 -SMU_ECLK = 5 -SMU_SOCCLK = 6 -SMU_UCLK = 7 -SMU_DCEFCLK = 8 -SMU_DISPCLK = 9 -SMU_PIXCLK = 10 -SMU_PHYCLK = 11 -SMU_FCLK = 12 -SMU_SCLK = 13 -SMU_MCLK = 14 -SMU_PCIE = 15 -SMU_LCLK = 16 -SMU_OD_CCLK = 17 -SMU_OD_SCLK = 18 -SMU_OD_MCLK = 19 -SMU_OD_VDDC_CURVE = 20 -SMU_OD_RANGE = 21 -SMU_OD_VDDGFX_OFFSET = 22 -SMU_OD_FAN_CURVE = 23 -SMU_OD_ACOUSTIC_LIMIT = 24 -SMU_OD_ACOUSTIC_TARGET = 25 -SMU_OD_FAN_TARGET_TEMPERATURE = 26 -SMU_OD_FAN_MINIMUM_PWM = 27 -SMU_CLK_COUNT = 28 -smu_clk_type = ctypes.c_uint32 # enum -class struct_smu_user_dpm_profile(Structure): - pass - -struct_smu_user_dpm_profile._pack_ = 1 # source:False -struct_smu_user_dpm_profile._fields_ = [ - ('fan_mode', ctypes.c_uint32), - ('power_limit', ctypes.c_uint32), - ('fan_speed_pwm', ctypes.c_uint32), - ('fan_speed_rpm', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('user_od', ctypes.c_uint32), - ('clk_mask', ctypes.c_uint32 * 28), - ('clk_dependency', ctypes.c_uint32), -] - -class struct_smu_table(Structure): - pass - -class struct_amdgpu_bo(Structure): - pass - -struct_smu_table._pack_ = 1 # source:False -struct_smu_table._fields_ = [ - ('size', ctypes.c_uint64), - ('align', ctypes.c_uint32), - ('domain', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('mc_address', ctypes.c_uint64), - ('cpu_addr', ctypes.POINTER(None)), - ('bo', ctypes.POINTER(struct_amdgpu_bo)), - ('version', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'smu_perf_level_designation' -smu_perf_level_designation__enumvalues = { - 0: 'PERF_LEVEL_ACTIVITY', - 1: 'PERF_LEVEL_POWER_CONTAINMENT', -} -PERF_LEVEL_ACTIVITY = 0 -PERF_LEVEL_POWER_CONTAINMENT = 1 -smu_perf_level_designation = ctypes.c_uint32 # enum -class struct_smu_performance_level(Structure): - pass - -struct_smu_performance_level._pack_ = 1 # source:False -struct_smu_performance_level._fields_ = [ - ('core_clock', ctypes.c_uint32), - ('memory_clock', ctypes.c_uint32), - ('vddc', ctypes.c_uint32), - ('vddci', ctypes.c_uint32), - ('non_local_mem_freq', ctypes.c_uint32), - ('non_local_mem_width', ctypes.c_uint32), -] - -class struct_smu_clock_info(Structure): - pass - -struct_smu_clock_info._pack_ = 1 # source:False -struct_smu_clock_info._fields_ = [ - ('min_mem_clk', ctypes.c_uint32), - ('max_mem_clk', ctypes.c_uint32), - ('min_eng_clk', ctypes.c_uint32), - ('max_eng_clk', ctypes.c_uint32), - ('min_bus_bandwidth', ctypes.c_uint32), - ('max_bus_bandwidth', ctypes.c_uint32), -] - -class struct_smu_bios_boot_up_values(Structure): - pass - -struct_smu_bios_boot_up_values._pack_ = 1 # source:False -struct_smu_bios_boot_up_values._fields_ = [ - ('revision', ctypes.c_uint32), - ('gfxclk', ctypes.c_uint32), - ('uclk', ctypes.c_uint32), - ('socclk', ctypes.c_uint32), - ('dcefclk', ctypes.c_uint32), - ('eclk', ctypes.c_uint32), - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), - ('vddc', ctypes.c_uint16), - ('vddci', ctypes.c_uint16), - ('mvddc', ctypes.c_uint16), - ('vdd_gfx', ctypes.c_uint16), - ('cooling_id', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pp_table_id', ctypes.c_uint32), - ('format_revision', ctypes.c_uint32), - ('content_revision', ctypes.c_uint32), - ('fclk', ctypes.c_uint32), - ('lclk', ctypes.c_uint32), - ('firmware_caps', ctypes.c_uint32), -] - - -# values for enumeration 'smu_table_id' -smu_table_id__enumvalues = { - 0: 'SMU_TABLE_PPTABLE', - 1: 'SMU_TABLE_WATERMARKS', - 2: 'SMU_TABLE_CUSTOM_DPM', - 3: 'SMU_TABLE_DPMCLOCKS', - 4: 'SMU_TABLE_AVFS', - 5: 'SMU_TABLE_AVFS_PSM_DEBUG', - 6: 'SMU_TABLE_AVFS_FUSE_OVERRIDE', - 7: 'SMU_TABLE_PMSTATUSLOG', - 8: 'SMU_TABLE_SMU_METRICS', - 9: 'SMU_TABLE_DRIVER_SMU_CONFIG', - 10: 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', - 11: 'SMU_TABLE_OVERDRIVE', - 12: 'SMU_TABLE_I2C_COMMANDS', - 13: 'SMU_TABLE_PACE', - 14: 'SMU_TABLE_ECCINFO', - 15: 'SMU_TABLE_COMBO_PPTABLE', - 16: 'SMU_TABLE_WIFIBAND', - 17: 'SMU_TABLE_COUNT', -} -SMU_TABLE_PPTABLE = 0 -SMU_TABLE_WATERMARKS = 1 -SMU_TABLE_CUSTOM_DPM = 2 -SMU_TABLE_DPMCLOCKS = 3 -SMU_TABLE_AVFS = 4 -SMU_TABLE_AVFS_PSM_DEBUG = 5 -SMU_TABLE_AVFS_FUSE_OVERRIDE = 6 -SMU_TABLE_PMSTATUSLOG = 7 -SMU_TABLE_SMU_METRICS = 8 -SMU_TABLE_DRIVER_SMU_CONFIG = 9 -SMU_TABLE_ACTIVITY_MONITOR_COEFF = 10 -SMU_TABLE_OVERDRIVE = 11 -SMU_TABLE_I2C_COMMANDS = 12 -SMU_TABLE_PACE = 13 -SMU_TABLE_ECCINFO = 14 -SMU_TABLE_COMBO_PPTABLE = 15 -SMU_TABLE_WIFIBAND = 16 -SMU_TABLE_COUNT = 17 -smu_table_id = ctypes.c_uint32 # enum -__all__ = \ - ['ALLOWED_FEATURE_CTRL_DEFAULT', 'ALLOWED_FEATURE_CTRL_SCPM', - 'AVFS_D_COUNT', 'AVFS_D_G', 'AVFS_D_e', 'AVFS_D_e__enumvalues', - 'AVFS_TEMP_COLD', 'AVFS_TEMP_COUNT', 'AVFS_TEMP_HOT', - 'AVFS_TEMP_e', 'AVFS_TEMP_e__enumvalues', 'AVFS_VOLTAGE_COUNT', - 'AVFS_VOLTAGE_GFX', 'AVFS_VOLTAGE_SOC', 'AVFS_VOLTAGE_TYPE_e', - 'AVFS_VOLTAGE_TYPE_e__enumvalues', 'AvfsDcBtcParams_t', - 'AvfsDebugTableExternal_t', 'AvfsDebugTable_t', - 'AvfsFuseOverride_t', 'BACO_SEQUENCE', 'BAMACO_SEQUENCE', - 'BOARD_GPIO_DC_GENLK_CLK', 'BOARD_GPIO_DC_GENLK_VSYNC', - 'BOARD_GPIO_DC_GEN_A', 'BOARD_GPIO_DC_GEN_B', - 'BOARD_GPIO_DC_GEN_C', 'BOARD_GPIO_DC_GEN_D', - 'BOARD_GPIO_DC_GEN_E', 'BOARD_GPIO_DC_GEN_F', - 'BOARD_GPIO_DC_GEN_G', 'BOARD_GPIO_DC_SWAPLOCK_A', - 'BOARD_GPIO_DC_SWAPLOCK_B', 'BOARD_GPIO_LV_EN', - 'BOARD_GPIO_SMUIO_0', 'BOARD_GPIO_SMUIO_1', 'BOARD_GPIO_SMUIO_10', - 'BOARD_GPIO_SMUIO_11', 'BOARD_GPIO_SMUIO_12', - 'BOARD_GPIO_SMUIO_13', 'BOARD_GPIO_SMUIO_14', - 'BOARD_GPIO_SMUIO_15', 'BOARD_GPIO_SMUIO_16', - 'BOARD_GPIO_SMUIO_17', 'BOARD_GPIO_SMUIO_18', - 'BOARD_GPIO_SMUIO_19', 'BOARD_GPIO_SMUIO_2', - 'BOARD_GPIO_SMUIO_20', 'BOARD_GPIO_SMUIO_21', - 'BOARD_GPIO_SMUIO_22', 'BOARD_GPIO_SMUIO_23', - 'BOARD_GPIO_SMUIO_24', 'BOARD_GPIO_SMUIO_25', - 'BOARD_GPIO_SMUIO_26', 'BOARD_GPIO_SMUIO_27', - 'BOARD_GPIO_SMUIO_28', 'BOARD_GPIO_SMUIO_29', - 'BOARD_GPIO_SMUIO_3', 'BOARD_GPIO_SMUIO_30', - 'BOARD_GPIO_SMUIO_31', 'BOARD_GPIO_SMUIO_4', 'BOARD_GPIO_SMUIO_5', - 'BOARD_GPIO_SMUIO_6', 'BOARD_GPIO_SMUIO_7', 'BOARD_GPIO_SMUIO_8', - 'BOARD_GPIO_SMUIO_9', 'BOARD_GPIO_TYPE_e', - 'BOARD_GPIO_TYPE_e__enumvalues', 'BoardTable_t', 'BootValues_t', - 'CMDCONFIG_READWRITE_BIT', 'CMDCONFIG_READWRITE_MASK', - 'CMDCONFIG_RESTART_BIT', 'CMDCONFIG_RESTART_MASK', - 'CMDCONFIG_STOP_BIT', 'CMDCONFIG_STOP_MASK', - 'CUSTOMER_VARIANT_COUNT', 'CUSTOMER_VARIANT_FALCON', - 'CUSTOMER_VARIANT_ROW', 'CUSTOMER_VARIANT_e', - 'CUSTOMER_VARIANT_e__enumvalues', 'CustomSkuTable_t', - 'D3HOTSequence_e', 'D3HOTSequence_e__enumvalues', - 'D3HOT_SEQUENCE_COUNT', 'DCS_ARCH_ASYNC', 'DCS_ARCH_DISABLED', - 'DCS_ARCH_FADCS', 'DCS_ARCH_e', 'DCS_ARCH_e__enumvalues', - 'DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG', - 'DEBUG_OVERRIDE_DFLL_MASTER_MODE', - 'DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK', - 'DEBUG_OVERRIDE_DISABLE_DFLL', - 'DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER', - 'DEBUG_OVERRIDE_DISABLE_FMAX_VMAX', - 'DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS', - 'DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING', - 'DEBUG_OVERRIDE_DISABLE_VCN_PG', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK', - 'DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY', - 'DEBUG_OVERRIDE_ENABLE_PROFILING_MODE', - 'DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE', - 'DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE', - 'DEBUG_OVERRIDE_NOT_USE', 'DRAM_BIT_WIDTH_COUNT', - 'DRAM_BIT_WIDTH_DISABLED', 'DRAM_BIT_WIDTH_TYPE_e', - 'DRAM_BIT_WIDTH_TYPE_e__enumvalues', 'DRAM_BIT_WIDTH_X_128', - 'DRAM_BIT_WIDTH_X_16', 'DRAM_BIT_WIDTH_X_32', - 'DRAM_BIT_WIDTH_X_64', 'DRAM_BIT_WIDTH_X_8', - 'DpmActivityMonitorCoeffIntExternal_t', - 'DpmActivityMonitorCoeffInt_t', 'DpmDescriptor_t', - 'DriverInfoTable_t', 'DriverReportedClocks_t', - 'DriverSmuConfigExternal_t', 'DriverSmuConfig_t', 'DroopInt_t', - 'ENABLE_DEBUG_FEATURES', 'EPCS_HIGH_POWER', - 'EPCS_HIGH_POWER_LIMIT', 'EPCS_LOW_POWER', 'EPCS_LOW_POWER_LIMIT', - 'EPCS_NORMAL_POWER', 'EPCS_NORMAL_POWER_LIMIT', - 'EPCS_NOT_CONFIGURED', 'EPCS_NO_BOOTUP', 'EPCS_SHORTED_LIMIT', - 'EPCS_SHORTED_POWER', 'EPCS_STATUS_COUNT', 'EPCS_STATUS_e', - 'EPCS_STATUS_e__enumvalues', 'EccInfoTable_t', 'EccInfo_t', - 'FAN_MODE_AUTO', 'FAN_MODE_MANUAL_LINEAR', 'FEATURE_ACDC_BIT', - 'FEATURE_APT_ALL_ENABLE_BIT', 'FEATURE_APT_PF_DCS_BIT', - 'FEATURE_APT_SQ_THROTTLE_BIT', 'FEATURE_ATHUB_MMHUB_PG_BIT', - 'FEATURE_ATHUB_PG_BIT', 'FEATURE_BACO_BIT', 'FEATURE_BACO_CG_BIT', - 'FEATURE_BACO_MPCLK_DS_BIT', 'FEATURE_BOOT_POWER_OPT_BIT', - 'FEATURE_BOOT_TIME_CAL_BIT', 'FEATURE_BTC_COUNT', - 'FEATURE_BTC_NOP', 'FEATURE_BTC_RESTORE', 'FEATURE_BTC_SAVE', - 'FEATURE_BTC_e', 'FEATURE_BTC_e__enumvalues', 'FEATURE_CC6_BIT', - 'FEATURE_CCLK_DPM_BIT', 'FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT', - 'FEATURE_CLOCK_STRETCH_COMPENSATOR', 'FEATURE_CORE_DLDO_BIT', - 'FEATURE_CPPC_BIT', 'FEATURE_CPPC_PREFERRED_CORES', - 'FEATURE_CPUOFF_BIT', 'FEATURE_DATA_CALCULATION_BIT', - 'FEATURE_DCFCLK_DPM_BIT', 'FEATURE_DF_CSTATES_BIT', - 'FEATURE_DF_CSTATE_BIT', 'FEATURE_DF_LIGHT_CSTATE', - 'FEATURE_DPM_DCN_BIT', 'FEATURE_DPM_FCLK_BIT', - 'FEATURE_DPM_GFXCLK_BIT', 'FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT', - 'FEATURE_DPM_LINK_BIT', 'FEATURE_DPM_SOCCLK_BIT', - 'FEATURE_DPM_UCLK_BIT', 'FEATURE_DS_DCFCLK_BIT', - 'FEATURE_DS_FCLK_BIT', 'FEATURE_DS_GFXCLK_BIT', - 'FEATURE_DS_HSPCLK_BIT', 'FEATURE_DS_IPUCLK_BIT', - 'FEATURE_DS_ISPCLK_BIT', 'FEATURE_DS_LCLK_BIT', - 'FEATURE_DS_MP1CLK_BIT', 'FEATURE_DS_MPIO_BIT', - 'FEATURE_DS_MPM_BIT', 'FEATURE_DS_SHUBCLK_BIT', - 'FEATURE_DS_SMNCLK_BIT', 'FEATURE_DS_SOCCLK_BIT', - 'FEATURE_DS_UCLK_BIT', 'FEATURE_DS_UMCCLK_BIT', - 'FEATURE_DS_VCN_BIT', 'FEATURE_DS_VPECLK_BIT', 'FEATURE_DVO_BIT', - 'FEATURE_EDC_BIT', 'FEATURE_EDC_PWRBRK_BIT', - 'FEATURE_FAN_ABNORMAL_BIT', 'FEATURE_FAN_CONTROLLER_BIT', - 'FEATURE_FAN_CONTROL_BIT', 'FEATURE_FAST_PSTATE_CLDO_BIT', - 'FEATURE_FCLK_DPM_BIT', 'FEATURE_FIT_BIT', 'FEATURE_FW_CTF_BIT', - 'FEATURE_FW_DATA_READ_BIT', 'FEATURE_FW_DSTATE_BIT', - 'FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT', 'FEATURE_GFXOFF_BIT', - 'FEATURE_GFX_DCS_BIT', 'FEATURE_GFX_DEM_BIT', - 'FEATURE_GFX_DIDT_XVMIN_BIT', 'FEATURE_GFX_DPM_BIT', - 'FEATURE_GFX_EDC_BIT', 'FEATURE_GFX_EDC_XVMIN_BIT', - 'FEATURE_GFX_IMU_BIT', 'FEATURE_GFX_PCC_DFLL_BIT', - 'FEATURE_GFX_PSM_DIDT_BIT', 'FEATURE_GFX_READ_MARGIN_BIT', - 'FEATURE_GFX_ULV_BIT', 'FEATURE_GTHR_BIT', - 'FEATURE_IOMMUL2_PG_BIT', 'FEATURE_IPU_DPM_BIT', - 'FEATURE_ISP_DPM_BIT', 'FEATURE_LCLK_DPM_BIT', - 'FEATURE_LED_DISPLAY_BIT', 'FEATURE_LOW_POWER_DCNCLKS_BIT', - 'FEATURE_MEM_TEMP_READ_BIT', 'FEATURE_MM_DPM_BIT', - 'FEATURE_OPTIMIZED_VMIN_BIT', 'FEATURE_OUT_OF_BAND_MONITOR_BIT', - 'FEATURE_P3T_BIT', 'FEATURE_PCC_BIT', 'FEATURE_PERF_LIMIT_BIT', - 'FEATURE_PLL_POWER_DOWN_BIT', 'FEATURE_PPT_BIT', - 'FEATURE_PROCHOT_BIT', 'FEATURE_PSI_BIT', 'FEATURE_PWR_ALL', - 'FEATURE_PWR_BACO', 'FEATURE_PWR_DOMAIN_COUNT', - 'FEATURE_PWR_DOMAIN_e', 'FEATURE_PWR_DOMAIN_e__enumvalues', - 'FEATURE_PWR_GFX', 'FEATURE_PWR_S5', 'FEATURE_PWR_SOC', - 'FEATURE_RESERVED0_BIT', 'FEATURE_RESERVED1_BIT', - 'FEATURE_S0I3_BIT', 'FEATURE_SHUBCLK_DPM_BIT', - 'FEATURE_SMARTSHIFT_BIT', 'FEATURE_SMART_L3_RINSER_BIT', - 'FEATURE_SMU_LOW_POWER_BIT', 'FEATURE_SOCCLK_DPM_BIT', - 'FEATURE_SOC_CG_BIT', 'FEATURE_SOC_EDC_XVMIN_BIT', - 'FEATURE_SOC_MPCLK_DS_BIT', 'FEATURE_SOC_PCC_BIT', - 'FEATURE_SPARE_59_BIT', 'FEATURE_SPARE_60_BIT', - 'FEATURE_SPARE_61_BIT', 'FEATURE_SPARE_62_BIT', - 'FEATURE_SPARE_63_BIT', 'FEATURE_STAPM_BIT', 'FEATURE_TDC_BIT', - 'FEATURE_THERMAL_BIT', 'FEATURE_THROTTLERS_BIT', - 'FEATURE_VCN_DPM_BIT', 'FEATURE_VDDIO_MEM_SCALING_BIT', - 'FEATURE_VDDOFF_BIT', 'FEATURE_VDDOFF_ECO_BIT', - 'FEATURE_VMEMP_SCALING_BIT', 'FEATURE_VPE_DPM_BIT', - 'FEATURE_VR0HOT_BIT', 'FEATURE_WHISPER_MODE_BIT', - 'FEATURE_ZSTATES_BIT', 'FEATURE_ZSTATES_ECO_BIT', - 'FOPT_CALC_AC_CALC_DC', 'FOPT_CALC_AC_PPTABLE_DC', 'FOPT_CALC_e', - 'FOPT_CALC_e__enumvalues', 'FOPT_PPTABLE_AC_CALC_DC', - 'FOPT_PPTABLE_AC_PPTABLE_DC', 'FW_DSTATE_CLDO_PRG_BIT', - 'FW_DSTATE_D0i3_2_QUIET_FW_BIT', 'FW_DSTATE_DF_PLL_PWRDN_BIT', - 'FW_DSTATE_G6_HSR_BIT', 'FW_DSTATE_G6_PHY_VMEMP_OFF_BIT', - 'FW_DSTATE_HSR_NON_STROBE_BIT', 'FW_DSTATE_MALL_ALLOC_BIT', - 'FW_DSTATE_MALL_FLUSH_BIT', 'FW_DSTATE_MEM_PLL_PWRDN_BIT', - 'FW_DSTATE_MEM_PSI_BIT', 'FW_DSTATE_MMHUB_INTERLOCK_BIT', - 'FW_DSTATE_MP0_ENTER_WFI_BIT', 'FW_DSTATE_MP1_WHISPER_MODE_BIT', - 'FW_DSTATE_SMN_DS_BIT', 'FW_DSTATE_SOC_LIV_MIN_BIT', - 'FW_DSTATE_SOC_PLL_PWRDN_BIT', 'FW_DSTATE_SOC_PSI_BIT', - 'FW_DSTATE_SOC_ULV_BIT', 'FanMode_e', 'FanMode_e__enumvalues', - 'FwStatus_t', 'FwStatus_t_v14_0_1', - 'GPIO_INT_POLARITY_ACTIVE_HIGH', 'GPIO_INT_POLARITY_ACTIVE_LOW', - 'GpioIntPolarity_e', 'GpioIntPolarity_e__enumvalues', - 'I2C_CMD_COUNT', 'I2C_CMD_READ', 'I2C_CMD_WRITE', - 'I2C_CONTROLLER_DISABLED', 'I2C_CONTROLLER_ENABLED', - 'I2C_CONTROLLER_NAME_COUNT', 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 'I2C_CONTROLLER_NAME_LIQUID0', 'I2C_CONTROLLER_NAME_LIQUID1', - 'I2C_CONTROLLER_NAME_PLX', 'I2C_CONTROLLER_NAME_VR_GFX', - 'I2C_CONTROLLER_NAME_VR_SOC', 'I2C_CONTROLLER_NAME_VR_VDDIO', - 'I2C_CONTROLLER_NAME_VR_VMEMP', 'I2C_CONTROLLER_PORT_0', - 'I2C_CONTROLLER_PORT_1', 'I2C_CONTROLLER_PORT_COUNT', - 'I2C_CONTROLLER_PROTOCOL_COUNT', - 'I2C_CONTROLLER_PROTOCOL_INA3221', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 'I2C_CONTROLLER_THROTTLER_COUNT', - 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 'I2C_CONTROLLER_THROTTLER_INA3221', - 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 'I2C_CONTROLLER_THROTTLER_PLX', - 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', 'I2C_PORT_GPIO', - 'I2C_PORT_SVD_SCL', 'I2C_SPEED_COUNT', 'I2C_SPEED_FAST_100K', - 'I2C_SPEED_FAST_400K', 'I2C_SPEED_FAST_50K', - 'I2C_SPEED_FAST_PLUS_1M', 'I2C_SPEED_HIGH_1M', - 'I2C_SPEED_HIGH_2M', 'I2cCmdType_e', 'I2cCmdType_e__enumvalues', - 'I2cControllerConfig_t', 'I2cControllerName_e', - 'I2cControllerName_e__enumvalues', 'I2cControllerPort_e', - 'I2cControllerPort_e__enumvalues', 'I2cControllerProtocol_e', - 'I2cControllerProtocol_e__enumvalues', 'I2cControllerThrottler_e', - 'I2cControllerThrottler_e__enumvalues', 'I2cPort_e', - 'I2cPort_e__enumvalues', 'I2cSpeed_e', 'I2cSpeed_e__enumvalues', - 'IH_INTERRUPT_CONTEXT_ID_AC', 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D0', - 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D3', - 'IH_INTERRUPT_CONTEXT_ID_BACO', 'IH_INTERRUPT_CONTEXT_ID_DC', - 'IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE', - 'IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL', - 'IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY', - 'IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING', - 'IH_INTERRUPT_ID_TO_DRIVER', 'INVALID_BOARD_GPIO', - 'LED_DISPLAY_ERROR_BIT', 'LED_DISPLAY_GFX_DPM_BIT', - 'LED_DISPLAY_PCIE_BIT', 'LinearInt_t', 'MAX_BOARD_DC_GPIO_NUM', - 'MAX_BOARD_GPIO_SMUIO_NUM', 'MAX_SW_I2C_COMMANDS', - 'MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT', - 'MEM_TEMP_READ_IN_BAND_REFRESH_BIT', - 'MEM_TEMP_READ_OUT_OF_BAND_BIT', 'MEM_VENDOR_COUNT', - 'MEM_VENDOR_ELPIDA', 'MEM_VENDOR_ESMT', 'MEM_VENDOR_ETRON', - 'MEM_VENDOR_HYNIX', 'MEM_VENDOR_INFINEON', 'MEM_VENDOR_MICRON', - 'MEM_VENDOR_MOSEL', 'MEM_VENDOR_NANYA', 'MEM_VENDOR_PLACEHOLDER0', - 'MEM_VENDOR_PLACEHOLDER1', 'MEM_VENDOR_PLACEHOLDER2', - 'MEM_VENDOR_PLACEHOLDER3', 'MEM_VENDOR_PLACEHOLDER4', - 'MEM_VENDOR_PLACEHOLDER5', 'MEM_VENDOR_SAMSUNG', - 'MEM_VENDOR_WINBOND', 'MEM_VENDOR_e', 'MEM_VENDOR_e__enumvalues', - 'MSR_SEQUENCE', 'MsgLimits_t', 'NUM_DCFCLK_DPM_LEVELS', - 'NUM_DCLK_DPM_LEVELS', 'NUM_DISPCLK_DPM_LEVELS', - 'NUM_DPPCLK_DPM_LEVELS', 'NUM_DPREFCLK_DPM_LEVELS', - 'NUM_DTBCLK_DPM_LEVELS', 'NUM_FCLK_DPM_LEVELS', 'NUM_FEATURES', - 'NUM_GFXCLK_DPM_LEVELS', 'NUM_I2C_CONTROLLERS', 'NUM_LINK_LEVELS', - 'NUM_MP0CLK_DPM_LEVELS', 'NUM_OD_FAN_MAX_POINTS', - 'NUM_SOCCLK_DPM_LEVELS', 'NUM_UCLK_DPM_LEVELS', - 'NUM_VCLK_DPM_LEVELS', 'NUM_WM_RANGES', 'OD_FAIL_e', - 'OD_FAIL_e__enumvalues', 'OD_FAN_ACOUSTIC_LIMIT_ERROR', - 'OD_FAN_ACOUSTIC_TARGET_ERROR', 'OD_FAN_CURVE_PWM_ERROR', - 'OD_FAN_CURVE_TEMP_ERROR', 'OD_FAN_MIN_PWM_ERROR', - 'OD_FAN_TARGET_TEMP_ERROR', 'OD_FAN_ZERO_RPM_STOP_TEMP_ERROR', - 'OD_FCLK_ERROR', 'OD_FULL_CTRL_FCLK_ERROR', - 'OD_FULL_CTRL_GFXCLK_ERROR', 'OD_FULL_CTRL_UCLK_ERROR', - 'OD_FULL_CTRL_VDD_GFX_ERROR', 'OD_FULL_CTRL_VDD_SOC_ERROR', - 'OD_GFXCLK_ERROR', 'OD_GFXCLK_VF_CURVE_OFFSET_ERROR', - 'OD_INVALID_FEATURE_COMBO_ERROR', 'OD_NO_ERROR', - 'OD_OP_GFX_EDC_ERROR', 'OD_OP_GFX_PCC_ERROR', 'OD_OP_TEMP_ERROR', - 'OD_POWER_FEATURE_CTRL_ERROR', 'OD_PPT_ERROR', - 'OD_REQUEST_ADVANCED_NOT_SUPPORTED', 'OD_TDC_ERROR', - 'OD_UCLK_ERROR', 'OD_UNSUPPORTED_FEATURE', - 'OD_VDD_GFX_VMAX_ERROR', 'OD_VDD_SOC_VMAX_ERROR', - 'OverDriveLimits_t', 'OverDriveTableExternal_t', - 'OverDriveTable_t', 'PERF_LEVEL_ACTIVITY', - 'PERF_LEVEL_POWER_CONTAINMENT', 'PFE_Settings_t', - 'PG_DYNAMIC_MODE', 'PG_POWER_DOWN', 'PG_POWER_UP', - 'PG_STATIC_MODE', 'PMFW_VOLT_PLANE_COUNT', 'PMFW_VOLT_PLANE_GFX', - 'PMFW_VOLT_PLANE_SOC', 'PMFW_VOLT_PLANE_e', - 'PMFW_VOLT_PLANE_e__enumvalues', 'POWER_SOURCE_AC', - 'POWER_SOURCE_COUNT', 'POWER_SOURCE_DC', 'POWER_SOURCE_e', - 'POWER_SOURCE_e__enumvalues', 'PPCLK_COUNT', 'PPCLK_DCFCLK', - 'PPCLK_DCLK_0', 'PPCLK_DISPCLK', 'PPCLK_DPPCLK', 'PPCLK_DPREFCLK', - 'PPCLK_DTBCLK', 'PPCLK_FCLK', 'PPCLK_GFXCLK', 'PPCLK_SOCCLK', - 'PPCLK_UCLK', 'PPCLK_VCLK_0', 'PPCLK_e', 'PPCLK_e__enumvalues', - 'PPSMC_MSG_AllowGfxDcs', 'PPSMC_MSG_AllowGfxOff', - 'PPSMC_MSG_AllowIHHostInterrupt', 'PPSMC_MSG_ArmD3', - 'PPSMC_MSG_BacoAudioD3PME', 'PPSMC_MSG_DisableAllSmuFeatures', - 'PPSMC_MSG_DisableSmuFeaturesHigh', - 'PPSMC_MSG_DisableSmuFeaturesLow', 'PPSMC_MSG_DisallowGfxDcs', - 'PPSMC_MSG_DisallowGfxOff', 'PPSMC_MSG_DramLogSetDramAddrHigh', - 'PPSMC_MSG_DramLogSetDramAddrLow', 'PPSMC_MSG_DramLogSetDramSize', - 'PPSMC_MSG_DummyUndefined', 'PPSMC_MSG_DumpSTBtoDram', - 'PPSMC_MSG_EnableAllSmuFeatures', - 'PPSMC_MSG_EnableAudioStutterWA', 'PPSMC_MSG_EnableShadowDpm', - 'PPSMC_MSG_EnableSmuFeaturesHigh', - 'PPSMC_MSG_EnableSmuFeaturesLow', 'PPSMC_MSG_EnterBaco', - 'PPSMC_MSG_ExitBaco', 'PPSMC_MSG_ExtPwrConnSupport', - 'PPSMC_MSG_GetAllRunningSmuFeatures', - 'PPSMC_MSG_GetDcModeMaxDpmFreq', 'PPSMC_MSG_GetDpmFreqByIndex', - 'PPSMC_MSG_GetDriverIfVersion', 'PPSMC_MSG_GetMaxDpmFreq', - 'PPSMC_MSG_GetMinDpmFreq', 'PPSMC_MSG_GetPptLimit', - 'PPSMC_MSG_GetRunningSmuFeaturesHigh', - 'PPSMC_MSG_GetRunningSmuFeaturesLow', 'PPSMC_MSG_GetSmuVersion', - 'PPSMC_MSG_GetSvi3Voltage', 'PPSMC_MSG_GetVoltageByDpm', - 'PPSMC_MSG_Mode3Reset', 'PPSMC_MSG_NotifyPowerSource', - 'PPSMC_MSG_OverridePcieParameters', 'PPSMC_MSG_PowerDownJpeg', - 'PPSMC_MSG_PowerDownUmsch', 'PPSMC_MSG_PowerDownVcn', - 'PPSMC_MSG_PowerUpJpeg', 'PPSMC_MSG_PowerUpUmsch', - 'PPSMC_MSG_PowerUpVcn', - 'PPSMC_MSG_PreloadSwPstateForUclkOverDrive', - 'PPSMC_MSG_PrepareMp1ForUnload', - 'PPSMC_MSG_ReenableAcDcInterrupt', 'PPSMC_MSG_RunDcBtc', - 'PPSMC_MSG_STBtoDramLogSetDramAddress', - 'PPSMC_MSG_STBtoDramLogSetDramSize', - 'PPSMC_MSG_SetAllowedFeaturesMaskHigh', - 'PPSMC_MSG_SetAllowedFeaturesMaskLow', - 'PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel', - 'PPSMC_MSG_SetDcsArch', 'PPSMC_MSG_SetDriverDramAddr', - 'PPSMC_MSG_SetDriverDramAddrHigh', - 'PPSMC_MSG_SetDriverDramAddrLow', - 'PPSMC_MSG_SetExternalClientDfCstateAllow', - 'PPSMC_MSG_SetFwDstatesMask', 'PPSMC_MSG_SetHardMaxByFreq', - 'PPSMC_MSG_SetHardMinByFreq', 'PPSMC_MSG_SetMGpuFanBoostLimitRpm', - 'PPSMC_MSG_SetNumBadMemoryPagesRetired', - 'PPSMC_MSG_SetOBMTraceBufferLogging', 'PPSMC_MSG_SetPptLimit', - 'PPSMC_MSG_SetPriorityDeltaGain', 'PPSMC_MSG_SetSoftMaxByFreq', - 'PPSMC_MSG_SetSoftMinByFreq', - 'PPSMC_MSG_SetSystemVirtualDramAddrHigh', - 'PPSMC_MSG_SetSystemVirtualDramAddrLow', - 'PPSMC_MSG_SetTemperatureInputSelect', - 'PPSMC_MSG_SetThrottlerMask', 'PPSMC_MSG_SetToolsDramAddr', - 'PPSMC_MSG_SetToolsDramAddrHigh', 'PPSMC_MSG_SetToolsDramAddrLow', - 'PPSMC_MSG_SetVideoFps', 'PPSMC_MSG_SetWorkloadMask', - 'PPSMC_MSG_TestMessage', 'PPSMC_MSG_TransferTableDram2Smu', - 'PPSMC_MSG_TransferTableDram2SmuWithAddr', - 'PPSMC_MSG_TransferTableSmu2Dram', - 'PPSMC_MSG_TransferTableSmu2DramWithAddr', - 'PPSMC_MSG_TriggerVFFLR', 'PPSMC_MSG_UpdatePolicy', - 'PPSMC_MSG_UseDefaultPPTable', 'PPSMC_MSG_UseProfilingMode', - 'PPSMC_Message_Count', 'PPSMC_Result_CmdRejectedBusy', - 'PPSMC_Result_CmdRejectedPrereq', 'PPSMC_Result_Failed', - 'PPSMC_Result_OK', 'PPSMC_Result_UnknownCmd', 'PPSMC_VERSION', - 'PPTABLE_VERSION', 'PPT_THROTTLER_COUNT', 'PPT_THROTTLER_PPT0', - 'PPT_THROTTLER_PPT1', 'PPT_THROTTLER_PPT2', 'PPT_THROTTLER_PPT3', - 'PPT_THROTTLER_e', 'PPT_THROTTLER_e__enumvalues', 'PPTable_t', - 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 'PP_GRTAVFS_FW_COMMON_FUSE_e', - 'PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_e', - 'PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 'PP_GRTAVFS_HW_FUSE_COUNT', - 'PP_GRTAVFS_HW_FUSE_e', 'PP_GRTAVFS_HW_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_RESERVED_0', 'PP_GRTAVFS_HW_RESERVED_1', - 'PP_GRTAVFS_HW_RESERVED_2', 'PP_GRTAVFS_HW_RESERVED_3', - 'PP_GRTAVFS_HW_RESERVED_4', 'PP_GRTAVFS_HW_RESERVED_5', - 'PP_GRTAVFS_HW_RESERVED_6', 'PP_GRTAVFS_HW_VOLTAGE_GB', - 'PP_GRTAVFS_HW_ZONE0_VF', 'PP_GRTAVFS_HW_ZONE1_VF1', - 'PP_GRTAVFS_HW_ZONE2_VF2', 'PP_GRTAVFS_HW_ZONE3_VF3', - 'PP_NUM_OD_VF_CURVE_POINTS', 'PP_NUM_PSM_DIDT_PWL_ZONES', - 'PP_NUM_RTAVFS_PWL_ZONES', 'PP_OD_FEATURE_COUNT', - 'PP_OD_FEATURE_EDC_BIT', 'PP_OD_FEATURE_FAN_CURVE_BIT', - 'PP_OD_FEATURE_FAN_LEGACY_BIT', 'PP_OD_FEATURE_FCLK_BIT', - 'PP_OD_FEATURE_FULL_CTRL_BIT', 'PP_OD_FEATURE_GFXCLK_BIT', - 'PP_OD_FEATURE_GFX_VF_CURVE_BIT', 'PP_OD_FEATURE_GFX_VMAX_BIT', - 'PP_OD_FEATURE_PPT_BIT', 'PP_OD_FEATURE_SOC_VMAX_BIT', - 'PP_OD_FEATURE_TDC_BIT', 'PP_OD_FEATURE_TEMPERATURE_BIT', - 'PP_OD_FEATURE_UCLK_BIT', 'PP_OD_FEATURE_ZERO_FAN_BIT', - 'PP_OD_POWER_FEATURE_ALWAYS_DISABLED', - 'PP_OD_POWER_FEATURE_ALWAYS_ENABLED', - 'PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', - 'PP_OD_POWER_FEATURE_e', 'PP_OD_POWER_FEATURE_e__enumvalues', - 'PSI_SEL_VR0_PLANE0_PSI0', 'PSI_SEL_VR0_PLANE0_PSI1', - 'PSI_SEL_VR0_PLANE1_PSI0', 'PSI_SEL_VR0_PLANE1_PSI1', - 'PSI_SEL_VR1_PLANE0_PSI0', 'PSI_SEL_VR1_PLANE0_PSI1', - 'PSI_SEL_VR1_PLANE1_PSI0', 'PSI_SEL_VR1_PLANE1_PSI1', - 'PWR_CONFIG_TBP_DESKTOP', 'PWR_CONFIG_TBP_MOBILE', - 'PWR_CONFIG_TCP_ESTIMATED', 'PWR_CONFIG_TCP_MEASURED', - 'PWR_CONFIG_TDP', 'PWR_CONFIG_TGP', 'PowerGatingMode_e', - 'PowerGatingMode_e__enumvalues', 'PowerGatingSettings_e', - 'PowerGatingSettings_e__enumvalues', 'PwrConfig_e', - 'PwrConfig_e__enumvalues', 'QuadraticInt_t', - 'SMARTSHIFT_VERSION_1', 'SMARTSHIFT_VERSION_2', - 'SMARTSHIFT_VERSION_3', 'SMARTSHIFT_VERSION_e', - 'SMARTSHIFT_VERSION_e__enumvalues', 'SMU14_DRIVER_IF_V14_0_H', - 'SMU14_Firmware_Footer', 'SMU_CLK_COUNT', - 'SMU_CUSTOM_FAN_SPEED_PWM', 'SMU_CUSTOM_FAN_SPEED_RPM', - 'SMU_DCEFCLK', 'SMU_DCLK', 'SMU_DCLK1', 'SMU_DEFAULT_PPT_LIMIT', - 'SMU_DISPCLK', 'SMU_DPM_USER_PROFILE_RESTORE', 'SMU_ECLK', - 'SMU_FAST_PPT_LIMIT', 'SMU_FCLK', 'SMU_FW_NAME_LEN', - 'SMU_Firmware_Header', 'SMU_GFXCLK', 'SMU_LCLK', 'SMU_MCLK', - 'SMU_MEMORY_POOL_SIZE_1_GB', 'SMU_MEMORY_POOL_SIZE_256_MB', - 'SMU_MEMORY_POOL_SIZE_2_GB', 'SMU_MEMORY_POOL_SIZE_512_MB', - 'SMU_MEMORY_POOL_SIZE_ZERO', 'SMU_OD_ACOUSTIC_LIMIT', - 'SMU_OD_ACOUSTIC_TARGET', 'SMU_OD_CCLK', 'SMU_OD_FAN_CURVE', - 'SMU_OD_FAN_MINIMUM_PWM', 'SMU_OD_FAN_TARGET_TEMPERATURE', - 'SMU_OD_MCLK', 'SMU_OD_RANGE', 'SMU_OD_SCLK', 'SMU_OD_VDDC_CURVE', - 'SMU_OD_VDDGFX_OFFSET', 'SMU_PCIE', 'SMU_PHYCLK', 'SMU_PIXCLK', - 'SMU_POWER_SOURCE_AC', 'SMU_POWER_SOURCE_COUNT', - 'SMU_POWER_SOURCE_DC', 'SMU_PPT_LIMIT_CURRENT', - 'SMU_PPT_LIMIT_DEFAULT', 'SMU_PPT_LIMIT_MAX', 'SMU_PPT_LIMIT_MIN', - 'SMU_REFRESHRATE_SOURCE_EDID', 'SMU_REFRESHRATE_SOURCE_EXPLICIT', - 'SMU_SCLK', 'SMU_SOCCLK', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 'SMU_STATE_UI_LABEL_BACO', - 'SMU_STATE_UI_LABEL_BALLANCED', 'SMU_STATE_UI_LABEL_BATTERY', - 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 'SMU_STATE_UI_LABEL_NONE', - 'SMU_STATE_UI_LABEL_PERFORMANCE', 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', 'SMU_TABLE_AVFS', - 'SMU_TABLE_AVFS_FUSE_OVERRIDE', 'SMU_TABLE_AVFS_PSM_DEBUG', - 'SMU_TABLE_COMBO_PPTABLE', 'SMU_TABLE_COUNT', - 'SMU_TABLE_CUSTOM_DPM', 'SMU_TABLE_DPMCLOCKS', - 'SMU_TABLE_DRIVER_SMU_CONFIG', 'SMU_TABLE_ECCINFO', - 'SMU_TABLE_I2C_COMMANDS', 'SMU_TABLE_OVERDRIVE', 'SMU_TABLE_PACE', - 'SMU_TABLE_PMSTATUSLOG', 'SMU_TABLE_PPTABLE', - 'SMU_TABLE_SMU_METRICS', 'SMU_TABLE_WATERMARKS', - 'SMU_TABLE_WIFIBAND', 'SMU_TEMPERATURE_UNITS_PER_CENTIGRADES', - 'SMU_THERMAL_MAXIMUM_ALERT_TEMP', - 'SMU_THERMAL_MINIMUM_ALERT_TEMP', 'SMU_THROTTLER_APCC_BIT', - 'SMU_THROTTLER_EDC_CPU_BIT', 'SMU_THROTTLER_EDC_GFX_BIT', - 'SMU_THROTTLER_FIT_BIT', 'SMU_THROTTLER_FPPT_BIT', - 'SMU_THROTTLER_PPM_BIT', 'SMU_THROTTLER_PPT0_BIT', - 'SMU_THROTTLER_PPT1_BIT', 'SMU_THROTTLER_PPT2_BIT', - 'SMU_THROTTLER_PPT3_BIT', 'SMU_THROTTLER_PROCHOT_CPU_BIT', - 'SMU_THROTTLER_PROCHOT_GFX_BIT', 'SMU_THROTTLER_SPL_BIT', - 'SMU_THROTTLER_SPPT_APU_BIT', 'SMU_THROTTLER_SPPT_BIT', - 'SMU_THROTTLER_TDC_CVIP_BIT', 'SMU_THROTTLER_TDC_GFX_BIT', - 'SMU_THROTTLER_TDC_MEM_BIT', 'SMU_THROTTLER_TDC_SOC_BIT', - 'SMU_THROTTLER_TDC_VDD_BIT', 'SMU_THROTTLER_TEMP_CORE_BIT', - 'SMU_THROTTLER_TEMP_EDGE_BIT', 'SMU_THROTTLER_TEMP_GPU_BIT', - 'SMU_THROTTLER_TEMP_HOTSPOT_BIT', - 'SMU_THROTTLER_TEMP_LIQUID0_BIT', - 'SMU_THROTTLER_TEMP_LIQUID1_BIT', 'SMU_THROTTLER_TEMP_MEM_BIT', - 'SMU_THROTTLER_TEMP_SOC_BIT', 'SMU_THROTTLER_TEMP_VR_GFX_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM0_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM1_BIT', 'SMU_THROTTLER_TEMP_VR_SOC_BIT', - 'SMU_THROTTLER_VRHOT0_BIT', 'SMU_THROTTLER_VRHOT1_BIT', - 'SMU_UCLK', 'SMU_V14_0_2_PPSMC_H', 'SMU_VCLK', 'SMU_VCLK1', - 'SVI_PLANE_COUNT', 'SVI_PLANE_VDDCI_MEM', 'SVI_PLANE_VDDIO_MEM', - 'SVI_PLANE_VDD_GFX', 'SVI_PLANE_VDD_SOC', 'SVI_PLANE_e', - 'SVI_PLANE_e__enumvalues', 'SVI_PSI_0', 'SVI_PSI_1', 'SVI_PSI_2', - 'SVI_PSI_3', 'SVI_PSI_4', 'SVI_PSI_5', 'SVI_PSI_6', 'SVI_PSI_7', - 'SVI_PSI_e', 'SVI_PSI_e__enumvalues', 'SkuTable_t', - 'SmuMetricsExternal_t', 'SmuMetrics_t', 'Svi3RegulatorSettings_t', - 'SviTelemetryScale_t', 'SwI2cCmd_t', 'SwI2cRequestExternal_t', - 'SwI2cRequest_t', 'TABLE_ACOUSTIC_LIMIT_RPM_FAILED', - 'TABLE_ACOUSTIC_TARGET_RPM_FAILED', - 'TABLE_ACTIVITY_MONITOR_COEFF', 'TABLE_AVFS_PSM_DEBUG', - 'TABLE_COMBO_PPTABLE', 'TABLE_COUNT', 'TABLE_CUSTOM_SKUTABLE', - 'TABLE_DRIVER_INFO', 'TABLE_DRIVER_SMU_CONFIG', 'TABLE_ECCINFO', - 'TABLE_FAN_PWM_MIN_FAILED', 'TABLE_FAN_START_TEMP_FAILED', - 'TABLE_FAN_STOP_TEMP_FAILED', 'TABLE_FAN_TARGET_TEMP_FAILED', - 'TABLE_I2C_COMMANDS', 'TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED', - 'TABLE_OVERDRIVE', 'TABLE_PMSTATUSLOG', 'TABLE_PPTABLE', - 'TABLE_PPT_FAILED', 'TABLE_SMU_METRICS', 'TABLE_TDC_FAILED', - 'TABLE_TEMP_FAILED', 'TABLE_TRANSFER_FAILED', 'TABLE_TRANSFER_OK', - 'TABLE_TRANSFER_PENDING', 'TABLE_WATERMARKS', - 'TDC_THROTTLER_COUNT', 'TDC_THROTTLER_GFX', 'TDC_THROTTLER_SOC', - 'TDC_THROTTLER_e', 'TDC_THROTTLER_e__enumvalues', 'TEMP_COUNT', - 'TEMP_EDGE', 'TEMP_HOTSPOT', 'TEMP_HOTSPOT_GFX', - 'TEMP_HOTSPOT_SOC', 'TEMP_LIQUID0', 'TEMP_LIQUID1', 'TEMP_MEM', - 'TEMP_PLX', 'TEMP_VR_GFX', 'TEMP_VR_MEM0', 'TEMP_VR_MEM1', - 'TEMP_VR_SOC', 'TEMP_e', 'TEMP_e__enumvalues', 'THROTTLER_COUNT', - 'THROTTLER_FIT_BIT', 'THROTTLER_GFX_APCC_PLUS_BIT', - 'THROTTLER_GFX_DVO_BIT', 'THROTTLER_PPT0_BIT', - 'THROTTLER_PPT1_BIT', 'THROTTLER_PPT2_BIT', 'THROTTLER_PPT3_BIT', - 'THROTTLER_TDC_GFX_BIT', 'THROTTLER_TDC_SOC_BIT', - 'THROTTLER_TEMP_EDGE_BIT', 'THROTTLER_TEMP_HOTSPOT_BIT', - 'THROTTLER_TEMP_HOTSPOT_GFX_BIT', - 'THROTTLER_TEMP_HOTSPOT_SOC_BIT', 'THROTTLER_TEMP_LIQUID0_BIT', - 'THROTTLER_TEMP_LIQUID1_BIT', 'THROTTLER_TEMP_MEM_BIT', - 'THROTTLER_TEMP_PLX_BIT', 'THROTTLER_TEMP_VR_GFX_BIT', - 'THROTTLER_TEMP_VR_MEM0_BIT', 'THROTTLER_TEMP_VR_MEM1_BIT', - 'THROTTLER_TEMP_VR_SOC_BIT', 'UCLK_DIV_BY_1', 'UCLK_DIV_BY_2', - 'UCLK_DIV_BY_4', 'UCLK_DIV_BY_8', 'UCLK_DIV_e', - 'UCLK_DIV_e__enumvalues', 'ULPS_SEQUENCE', 'VOLTAGE_MODE_COUNT', - 'VOLTAGE_MODE_FUSES', 'VOLTAGE_MODE_PPTABLE', 'VOLTAGE_MODE_e', - 'VOLTAGE_MODE_e__enumvalues', 'VR_MAPPING_PLANE_SELECT_MASK', - 'VR_MAPPING_PLANE_SELECT_SHIFT', 'VR_MAPPING_VR_SELECT_MASK', - 'VR_MAPPING_VR_SELECT_SHIFT', 'WATERMARKS_CLOCK_RANGE', - 'WATERMARKS_COUNT', 'WATERMARKS_DUMMY_PSTATE', - 'WATERMARKS_FLAGS_e', 'WATERMARKS_FLAGS_e__enumvalues', - 'WATERMARKS_MALL', 'WORKLOAD_PPLIB_CGVDI_BIT', - 'WORKLOAD_PPLIB_COMPUTE_BIT', 'WORKLOAD_PPLIB_COUNT', - 'WORKLOAD_PPLIB_CUSTOM_BIT', 'WORKLOAD_PPLIB_DEFAULT_BIT', - 'WORKLOAD_PPLIB_DIRECT_ML_BIT', - 'WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT', - 'WORKLOAD_PPLIB_POWER_SAVING_BIT', 'WORKLOAD_PPLIB_VIDEO_BIT', - 'WORKLOAD_PPLIB_VR_BIT', 'WORKLOAD_PPLIB_WINDOW_3D_BIT', - 'WatermarkRowGeneric_t', 'WatermarksExternal_t', 'Watermarks_t', - '__AMDGPU_SMU_H__', '__SMU_V14_0_0_PMFW_H__', 'bool', - 'c__EA_AVFS_D_e', 'c__EA_AVFS_TEMP_e', - 'c__EA_AVFS_VOLTAGE_TYPE_e', 'c__EA_BOARD_GPIO_TYPE_e', - 'c__EA_CUSTOMER_VARIANT_e', 'c__EA_D3HOTSequence_e', - 'c__EA_DCS_ARCH_e', 'c__EA_DRAM_BIT_WIDTH_TYPE_e', - 'c__EA_EPCS_STATUS_e', 'c__EA_FEATURE_BTC_e', - 'c__EA_FEATURE_PWR_DOMAIN_e', 'c__EA_FOPT_CALC_e', - 'c__EA_FanMode_e', 'c__EA_GpioIntPolarity_e', - 'c__EA_I2cCmdType_e', 'c__EA_I2cControllerName_e', - 'c__EA_I2cControllerPort_e', 'c__EA_I2cControllerProtocol_e', - 'c__EA_I2cControllerThrottler_e', 'c__EA_I2cPort_e', - 'c__EA_I2cSpeed_e', 'c__EA_MEM_VENDOR_e', 'c__EA_OD_FAIL_e', - 'c__EA_PMFW_VOLT_PLANE_e', 'c__EA_POWER_SOURCE_e', - 'c__EA_PPCLK_e', 'c__EA_PPT_THROTTLER_e', - 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e', - 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e', 'c__EA_PP_GRTAVFS_HW_FUSE_e', - 'c__EA_PP_OD_POWER_FEATURE_e', 'c__EA_PowerGatingMode_e', - 'c__EA_PowerGatingSettings_e', 'c__EA_PwrConfig_e', - 'c__EA_SMARTSHIFT_VERSION_e', 'c__EA_SVI_PLANE_e', - 'c__EA_SVI_PSI_e', 'c__EA_TDC_THROTTLER_e', 'c__EA_TEMP_e', - 'c__EA_UCLK_DIV_e', 'c__EA_VOLTAGE_MODE_e', - 'c__EA_WATERMARKS_FLAGS_e', 'int16_t', 'int32_t', 'int8_t', - 'smu_clk_type', 'smu_memory_pool_size', - 'smu_perf_level_designation', 'smu_power_src_type', - 'smu_ppt_limit_level', 'smu_ppt_limit_type', - 'smu_refreshrate_source', 'smu_state_classification_flag', - 'smu_state_ui_label', 'smu_table_id', - 'struct_SMU14_Firmware_Footer', 'struct_amdgpu_bo', - 'struct_c__SA_AvfsDcBtcParams_t', - 'struct_c__SA_AvfsDebugTableExternal_t', - 'struct_c__SA_AvfsDebugTable_t', - 'struct_c__SA_AvfsFuseOverride_t', 'struct_c__SA_BoardTable_t', - 'struct_c__SA_BootValues_t', 'struct_c__SA_CustomSkuTable_t', - 'struct_c__SA_DpmActivityMonitorCoeffIntExternal_t', - 'struct_c__SA_DpmActivityMonitorCoeffInt_t', - 'struct_c__SA_DpmDescriptor_t', 'struct_c__SA_DriverInfoTable_t', - 'struct_c__SA_DriverReportedClocks_t', - 'struct_c__SA_DriverSmuConfigExternal_t', - 'struct_c__SA_DriverSmuConfig_t', 'struct_c__SA_DroopInt_t', - 'struct_c__SA_EccInfoTable_t', 'struct_c__SA_EccInfo_t', - 'struct_c__SA_FwStatus_t', 'struct_c__SA_FwStatus_t_v14_0_1', - 'struct_c__SA_I2cControllerConfig_t', 'struct_c__SA_LinearInt_t', - 'struct_c__SA_MsgLimits_t', 'struct_c__SA_OverDriveLimits_t', - 'struct_c__SA_OverDriveTableExternal_t', - 'struct_c__SA_OverDriveTable_t', 'struct_c__SA_PFE_Settings_t', - 'struct_c__SA_PPTable_t', 'struct_c__SA_QuadraticInt_t', - 'struct_c__SA_SMU_Firmware_Header', 'struct_c__SA_SkuTable_t', - 'struct_c__SA_SmuMetricsExternal_t', 'struct_c__SA_SmuMetrics_t', - 'struct_c__SA_Svi3RegulatorSettings_t', - 'struct_c__SA_SviTelemetryScale_t', 'struct_c__SA_SwI2cCmd_t', - 'struct_c__SA_SwI2cRequestExternal_t', - 'struct_c__SA_SwI2cRequest_t', - 'struct_c__SA_WatermarkRowGeneric_t', - 'struct_c__SA_WatermarksExternal_t', 'struct_c__SA_Watermarks_t', - 'struct_smu_bios_boot_up_values', 'struct_smu_clock_info', - 'struct_smu_hw_power_state', 'struct_smu_performance_level', - 'struct_smu_power_state', 'struct_smu_state_classification_block', - 'struct_smu_state_display_block', 'struct_smu_state_memory_block', - 'struct_smu_state_pcie_block', - 'struct_smu_state_software_algorithm_block', - 'struct_smu_state_validation_block', 'struct_smu_table', - 'struct_smu_temperature_range', 'struct_smu_user_dpm_profile', - 'struct_smu_uvd_clocks', 'u32', 'uint16_t', 'uint32_t', - 'uint64_t', 'uint8_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/soc21.py b/tinygrad/tinygrad/runtime/autogen/am/soc21.py deleted file mode 100644 index 34a95940..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/soc21.py +++ /dev/null @@ -1,39083 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - - - -_soc21_ENUM_HEADER = True # macro -SQ_WAVE_TYPE_PS0 = 0x00000000 # macro -SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro -SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro -SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro -SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro -SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro -SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro -SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro -SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro -SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro -SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro -SQ_GFXDEC_BEGIN = 0x0000a000 # macro -SQ_GFXDEC_END = 0x0000c000 # macro -SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro -SQDEC_BEGIN = 0x00002300 # macro -SQDEC_END = 0x000023ff # macro -SQPERFSDEC_BEGIN = 0x0000d9c0 # macro -SQPERFSDEC_END = 0x0000da40 # macro -SQPERFDDEC_BEGIN = 0x0000d1c0 # macro -SQPERFDDEC_END = 0x0000d240 # macro -SQGFXUDEC_BEGIN = 0x0000c330 # macro -SQGFXUDEC_END = 0x0000c380 # macro -SQPWRDEC_BEGIN = 0x0000f08c # macro -SQPWRDEC_END = 0x0000f094 # macro -SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro -SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro -SQ_MAX_PGM_SGPRS = 0x00000068 # macro -SQ_MAX_PGM_VGPRS = 0x00000100 # macro -SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro -SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro -SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro -SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro -SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro -SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro -SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro -SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro -SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro -SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro -SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro -INST_ID_PRIV_START = 0x80000000 # macro -INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro -INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro -INST_ID_HW_TRAP = 0xfffffff2 # macro -INST_ID_KILL_SEQ = 0xfffffff3 # macro -INST_ID_SPI_WREXEC = 0xfffffff4 # macro -INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro -INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro -SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro -SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro -SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro -SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro -SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro -SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro -SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro -SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro -SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro -SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro -SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro -SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro -SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro -SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro -CSDATA_TYPE_WIDTH = 0x00000002 # macro -CSDATA_ADDR_WIDTH = 0x00000007 # macro -CSDATA_DATA_WIDTH = 0x00000020 # macro -CSCNTL_TYPE_WIDTH = 0x00000002 # macro -CSCNTL_ADDR_WIDTH = 0x00000007 # macro -CSCNTL_DATA_WIDTH = 0x00000020 # macro -GSTHREADID_SIZE = 0x00000002 # macro -GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro -GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro -SEM_ECC_ERROR = 0x00000000 # macro -SEM_TRANS_ERROR = 0x00000001 # macro -SEM_RESP_FAILED = 0x00000002 # macro -SEM_RESP_PASSED = 0x00000003 # macro -IQ_QUEUE_SLEEP = 0x00000000 # macro -IQ_OFFLOAD_RETRY = 0x00000001 # macro -IQ_SCH_WAVE_MSG = 0x00000002 # macro -IQ_SEM_REARM = 0x00000003 # macro -IQ_DEQUEUE_RETRY = 0x00000004 # macro -IQ_INTR_TYPE_PQ = 0x00000000 # macro -IQ_INTR_TYPE_IB = 0x00000001 # macro -IQ_INTR_TYPE_MQD = 0x00000002 # macro -VMID_SZ = 0x00000004 # macro -SRCID_RLC = 0x00000000 # macro -SRCID_RLCV = 0x00000006 # macro -SRCID_SECURE_CP = 0x00000007 # macro -SRCID_NONSECURE_CP = 0x00000001 # macro -SRCID_SECURE_CP_RCIU = 0x00000007 # macro -SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro -CONFIG_SPACE_START = 0x00002000 # macro -CONFIG_SPACE_END = 0x00009fff # macro -CONFIG_SPACE1_START = 0x00002000 # macro -CONFIG_SPACE1_END = 0x00002bff # macro -CONFIG_SPACE2_START = 0x00003000 # macro -CONFIG_SPACE2_END = 0x00009fff # macro -UCONFIG_SPACE_START = 0x0000c000 # macro -UCONFIG_SPACE_END = 0x0000ffff # macro -PERSISTENT_SPACE_START = 0x00002c00 # macro -PERSISTENT_SPACE_END = 0x00002fff # macro -CONTEXT_SPACE_START = 0x0000a000 # macro -CONTEXT_SPACE_END = 0x0000a3ff # macro -ROM_SIGNATURE = 0x0000aa55 # macro - -# values for enumeration 'DSM_DATA_SEL' -DSM_DATA_SEL__enumvalues = { - 0: 'DSM_DATA_SEL_DISABLE', - 1: 'DSM_DATA_SEL_0', - 2: 'DSM_DATA_SEL_1', - 3: 'DSM_DATA_SEL_BOTH', -} -DSM_DATA_SEL_DISABLE = 0 -DSM_DATA_SEL_0 = 1 -DSM_DATA_SEL_1 = 2 -DSM_DATA_SEL_BOTH = 3 -DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_ENABLE_ERROR_INJECT' -DSM_ENABLE_ERROR_INJECT__enumvalues = { - 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', -} -DSM_ENABLE_ERROR_INJECT_FED_IN = 0 -DSM_ENABLE_ERROR_INJECT_SINGLE = 1 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 -DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SELECT_INJECT_DELAY' -DSM_SELECT_INJECT_DELAY__enumvalues = { - 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', - 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', -} -DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 -DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 -DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SINGLE_WRITE' -DSM_SINGLE_WRITE__enumvalues = { - 0: 'DSM_SINGLE_WRITE_DIS', - 1: 'DSM_SINGLE_WRITE_EN', -} -DSM_SINGLE_WRITE_DIS = 0 -DSM_SINGLE_WRITE_EN = 1 -DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_NUM_SIMD_PER_CU' -ENUM_NUM_SIMD_PER_CU__enumvalues = { - 2: 'NUM_SIMD_PER_CU', -} -NUM_SIMD_PER_CU = 2 -ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum - -# values for enumeration 'GATCL1RequestType' -GATCL1RequestType__enumvalues = { - 0: 'GATCL1_TYPE_NORMAL', - 1: 'GATCL1_TYPE_SHOOTDOWN', - 2: 'GATCL1_TYPE_BYPASS', -} -GATCL1_TYPE_NORMAL = 0 -GATCL1_TYPE_SHOOTDOWN = 1 -GATCL1_TYPE_BYPASS = 2 -GATCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'GL0V_CACHE_POLICIES' -GL0V_CACHE_POLICIES__enumvalues = { - 0: 'GL0V_CACHE_POLICY_MISS_LRU', - 1: 'GL0V_CACHE_POLICY_MISS_EVICT', - 2: 'GL0V_CACHE_POLICY_HIT_LRU', - 3: 'GL0V_CACHE_POLICY_HIT_EVICT', -} -GL0V_CACHE_POLICY_MISS_LRU = 0 -GL0V_CACHE_POLICY_MISS_EVICT = 1 -GL0V_CACHE_POLICY_HIT_LRU = 2 -GL0V_CACHE_POLICY_HIT_EVICT = 3 -GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_POLICIES' -GL1_CACHE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_POLICY_MISS_LRU', - 1: 'GL1_CACHE_POLICY_MISS_EVICT', - 2: 'GL1_CACHE_POLICY_HIT_LRU', - 3: 'GL1_CACHE_POLICY_HIT_EVICT', -} -GL1_CACHE_POLICY_MISS_LRU = 0 -GL1_CACHE_POLICY_MISS_EVICT = 1 -GL1_CACHE_POLICY_HIT_LRU = 2 -GL1_CACHE_POLICY_HIT_EVICT = 3 -GL1_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_STORE_POLICIES' -GL1_CACHE_STORE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_STORE_POLICY_BYPASS', -} -GL1_CACHE_STORE_POLICY_BYPASS = 0 -GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_CACHE_POLICIES' -GL2_CACHE_POLICIES__enumvalues = { - 0: 'GL2_CACHE_POLICY_LRU', - 1: 'GL2_CACHE_POLICY_STREAM', - 2: 'GL2_CACHE_POLICY_NOA', - 3: 'GL2_CACHE_POLICY_BYPASS', -} -GL2_CACHE_POLICY_LRU = 0 -GL2_CACHE_POLICY_STREAM = 1 -GL2_CACHE_POLICY_NOA = 2 -GL2_CACHE_POLICY_BYPASS = 3 -GL2_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'Hdp_SurfaceEndian' -Hdp_SurfaceEndian__enumvalues = { - 0: 'HDP_ENDIAN_NONE', - 1: 'HDP_ENDIAN_8IN16', - 2: 'HDP_ENDIAN_8IN32', - 3: 'HDP_ENDIAN_8IN64', -} -HDP_ENDIAN_NONE = 0 -HDP_ENDIAN_8IN16 = 1 -HDP_ENDIAN_8IN32 = 2 -HDP_ENDIAN_8IN64 = 3 -Hdp_SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'MTYPE' -MTYPE__enumvalues = { - 0: 'MTYPE_C_RW_US', - 1: 'MTYPE_RESERVED_1', - 2: 'MTYPE_C_RO_S', - 3: 'MTYPE_UC', - 4: 'MTYPE_C_RW_S', - 5: 'MTYPE_RESERVED_5', - 6: 'MTYPE_C_RO_US', - 7: 'MTYPE_RESERVED_7', -} -MTYPE_C_RW_US = 0 -MTYPE_RESERVED_1 = 1 -MTYPE_C_RO_S = 2 -MTYPE_UC = 3 -MTYPE_C_RW_S = 4 -MTYPE_RESERVED_5 = 5 -MTYPE_C_RO_US = 6 -MTYPE_RESERVED_7 = 7 -MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_COUNTER_MODE' -PERFMON_COUNTER_MODE__enumvalues = { - 0: 'PERFMON_COUNTER_MODE_ACCUM', - 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 2: 'PERFMON_COUNTER_MODE_MAX', - 3: 'PERFMON_COUNTER_MODE_DIRTY', - 4: 'PERFMON_COUNTER_MODE_SAMPLE', - 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 15: 'PERFMON_COUNTER_MODE_RESERVED', -} -PERFMON_COUNTER_MODE_ACCUM = 0 -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 -PERFMON_COUNTER_MODE_MAX = 2 -PERFMON_COUNTER_MODE_DIRTY = 3 -PERFMON_COUNTER_MODE_SAMPLE = 4 -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 -PERFMON_COUNTER_MODE_RESERVED = 15 -PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_SPM_MODE' -PERFMON_SPM_MODE__enumvalues = { - 0: 'PERFMON_SPM_MODE_OFF', - 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', - 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', - 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 5: 'PERFMON_SPM_MODE_RESERVED_5', - 6: 'PERFMON_SPM_MODE_RESERVED_6', - 7: 'PERFMON_SPM_MODE_RESERVED_7', - 8: 'PERFMON_SPM_MODE_TEST_MODE_0', - 9: 'PERFMON_SPM_MODE_TEST_MODE_1', - 10: 'PERFMON_SPM_MODE_TEST_MODE_2', -} -PERFMON_SPM_MODE_OFF = 0 -PERFMON_SPM_MODE_16BIT_CLAMP = 1 -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 -PERFMON_SPM_MODE_32BIT_CLAMP = 3 -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 -PERFMON_SPM_MODE_RESERVED_5 = 5 -PERFMON_SPM_MODE_RESERVED_6 = 6 -PERFMON_SPM_MODE_RESERVED_7 = 7 -PERFMON_SPM_MODE_TEST_MODE_0 = 8 -PERFMON_SPM_MODE_TEST_MODE_1 = 9 -PERFMON_SPM_MODE_TEST_MODE_2 = 10 -PERFMON_SPM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RMI_CID' -RMI_CID__enumvalues = { - 0: 'RMI_CID_CC', - 1: 'RMI_CID_FC', - 2: 'RMI_CID_CM', - 3: 'RMI_CID_DC', - 4: 'RMI_CID_Z', - 5: 'RMI_CID_S', - 6: 'RMI_CID_TILE', - 7: 'RMI_CID_ZPCPSD', -} -RMI_CID_CC = 0 -RMI_CID_FC = 1 -RMI_CID_CM = 2 -RMI_CID_DC = 3 -RMI_CID_Z = 4 -RMI_CID_S = 5 -RMI_CID_TILE = 6 -RMI_CID_ZPCPSD = 7 -RMI_CID = ctypes.c_uint32 # enum - -# values for enumeration 'ReadPolicy' -ReadPolicy__enumvalues = { - 0: 'CACHE_LRU_RD', - 1: 'CACHE_STREAM_RD', - 2: 'CACHE_NOA', - 3: 'RESERVED_RDPOLICY', -} -CACHE_LRU_RD = 0 -CACHE_STREAM_RD = 1 -CACHE_NOA = 2 -RESERVED_RDPOLICY = 3 -ReadPolicy = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERFMON_SEL' -SDMA_PERFMON_SEL__enumvalues = { - 0: 'SDMA_PERFMON_SEL_CYCLE', - 1: 'SDMA_PERFMON_SEL_IDLE', - 2: 'SDMA_PERFMON_SEL_REG_IDLE', - 3: 'SDMA_PERFMON_SEL_RB_EMPTY', - 4: 'SDMA_PERFMON_SEL_RB_FULL', - 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', - 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', - 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 13: 'SDMA_PERFMON_SEL_EX_IDLE', - 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', - 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', - 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', - 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', - 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 26: 'SDMA_PERFMON_SEL_SEM_IDLE', - 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 32: 'SDMA_PERFMON_SEL_INT_IDLE', - 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 37: 'SDMA_PERFMON_SEL_NUM_PACKET', - 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', - 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', - 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', - 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', - 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', - 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', - 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', - 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', - 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', - 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', - 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', - 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', - 55: 'SDMA_PERFMON_SEL_GFX_SELECT', - 56: 'SDMA_PERFMON_SEL_RLC0_SELECT', - 57: 'SDMA_PERFMON_SEL_RLC1_SELECT', - 58: 'SDMA_PERFMON_SEL_PAGE_SELECT', - 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', - 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', - 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 62: 'SDMA_PERFMON_SEL_DOORBELL', - 63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', - 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', - 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', - 95: 'SDMA_PERFMON_SEL_TLBI_SEND', - 96: 'SDMA_PERFMON_SEL_TLBI_RTN', - 97: 'SDMA_PERFMON_SEL_GCR_SEND', - 98: 'SDMA_PERFMON_SEL_GCR_RTN', - 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', -} -SDMA_PERFMON_SEL_CYCLE = 0 -SDMA_PERFMON_SEL_IDLE = 1 -SDMA_PERFMON_SEL_REG_IDLE = 2 -SDMA_PERFMON_SEL_RB_EMPTY = 3 -SDMA_PERFMON_SEL_RB_FULL = 4 -SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 -SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 -SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERFMON_SEL_RB_RPTR_WB = 8 -SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 -SDMA_PERFMON_SEL_RB_CMD_FULL = 10 -SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 -SDMA_PERFMON_SEL_IB_CMD_FULL = 12 -SDMA_PERFMON_SEL_EX_IDLE = 13 -SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 -SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERFMON_SEL_WR_BA_RTR = 16 -SDMA_PERFMON_SEL_MC_WR_IDLE = 17 -SDMA_PERFMON_SEL_MC_WR_COUNT = 18 -SDMA_PERFMON_SEL_RD_BA_RTR = 19 -SDMA_PERFMON_SEL_MC_RD_IDLE = 20 -SDMA_PERFMON_SEL_MC_RD_COUNT = 21 -SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 -SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 -SDMA_PERFMON_SEL_SEM_IDLE = 26 -SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 -SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 -SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 -SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 -SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 -SDMA_PERFMON_SEL_INT_IDLE = 32 -SDMA_PERFMON_SEL_INT_REQ_STALL = 33 -SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 -SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 -SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 -SDMA_PERFMON_SEL_NUM_PACKET = 37 -SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 -SDMA_PERFMON_SEL_CE_WR_IDLE = 40 -SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 -SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 -SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 -SDMA_PERFMON_SEL_CE_IN_IDLE = 44 -SDMA_PERFMON_SEL_CE_DST_IDLE = 45 -SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 -SDMA_PERFMON_SEL_CE_INFO_FULL = 51 -SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 -SDMA_PERFMON_SEL_CE_RD_STALL = 53 -SDMA_PERFMON_SEL_CE_WR_STALL = 54 -SDMA_PERFMON_SEL_GFX_SELECT = 55 -SDMA_PERFMON_SEL_RLC0_SELECT = 56 -SDMA_PERFMON_SEL_RLC1_SELECT = 57 -SDMA_PERFMON_SEL_PAGE_SELECT = 58 -SDMA_PERFMON_SEL_CTX_CHANGE = 59 -SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 -SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 -SDMA_PERFMON_SEL_DOORBELL = 62 -SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63 -SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 -SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 -SDMA_PERFMON_SEL_UTCL2_FREE = 73 -SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 -SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 -SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 -SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 -SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 -SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 -SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 -SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERFMON_SEL_META_REQ_SEND = 93 -SDMA_PERFMON_SEL_META_RTN_VLD = 94 -SDMA_PERFMON_SEL_TLBI_SEND = 95 -SDMA_PERFMON_SEL_TLBI_RTN = 96 -SDMA_PERFMON_SEL_GCR_SEND = 97 -SDMA_PERFMON_SEL_GCR_RTN = 98 -SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 -SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 -SDMA_PERFMON_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERF_SEL' -SDMA_PERF_SEL__enumvalues = { - 0: 'SDMA_PERF_SEL_CYCLE', - 1: 'SDMA_PERF_SEL_IDLE', - 2: 'SDMA_PERF_SEL_REG_IDLE', - 3: 'SDMA_PERF_SEL_RB_EMPTY', - 4: 'SDMA_PERF_SEL_RB_FULL', - 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERF_SEL_RB_RPTR_WB', - 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERF_SEL_RB_CMD_FULL', - 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERF_SEL_IB_CMD_FULL', - 13: 'SDMA_PERF_SEL_EX_IDLE', - 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERF_SEL_MC_WR_IDLE', - 17: 'SDMA_PERF_SEL_MC_WR_COUNT', - 18: 'SDMA_PERF_SEL_MC_RD_IDLE', - 19: 'SDMA_PERF_SEL_MC_RD_COUNT', - 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'SDMA_PERF_SEL_SEM_IDLE', - 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'SDMA_PERF_SEL_INT_IDLE', - 31: 'SDMA_PERF_SEL_INT_REQ_STALL', - 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'SDMA_PERF_SEL_NUM_PACKET', - 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'SDMA_PERF_SEL_CE_WR_IDLE', - 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'SDMA_PERF_SEL_CE_IN_IDLE', - 43: 'SDMA_PERF_SEL_CE_DST_IDLE', - 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'SDMA_PERF_SEL_CE_INFO_FULL', - 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'SDMA_PERF_SEL_CE_RD_STALL', - 52: 'SDMA_PERF_SEL_CE_WR_STALL', - 53: 'SDMA_PERF_SEL_GFX_SELECT', - 54: 'SDMA_PERF_SEL_RLC0_SELECT', - 55: 'SDMA_PERF_SEL_RLC1_SELECT', - 56: 'SDMA_PERF_SEL_PAGE_SELECT', - 57: 'SDMA_PERF_SEL_CTX_CHANGE', - 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'SDMA_PERF_SEL_DOORBELL', - 61: 'SDMA_PERF_SEL_RD_BA_RTR', - 62: 'SDMA_PERF_SEL_WR_BA_RTR', - 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERF_SEL_UTCL2_FREE', - 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERF_SEL_META_REQ_SEND', - 94: 'SDMA_PERF_SEL_META_RTN_VLD', - 95: 'SDMA_PERF_SEL_TLBI_SEND', - 96: 'SDMA_PERF_SEL_TLBI_RTN', - 97: 'SDMA_PERF_SEL_GCR_SEND', - 98: 'SDMA_PERF_SEL_GCR_RTN', - 99: 'SDMA_PERF_SEL_CGCG_FENCE', - 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', - 102: 'SDMA_PERF_SEL_F32_CH_WR_REQ', - 103: 'SDMA_PERF_SEL_F32_CH_WR_RET', - 104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', - 105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', - 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', - 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', - 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', - 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', - 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', - 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', - 115: 'SDMA_PERF_SEL_CMD_OP_START', - 116: 'SDMA_PERF_SEL_CMD_OP_END', - 117: 'SDMA_PERF_SEL_CE_BUSY', - 118: 'SDMA_PERF_SEL_CE_BUSY_START', - 119: 'SDMA_PERF_SEL_CE_BUSY_END', - 120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', - 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', - 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', -} -SDMA_PERF_SEL_CYCLE = 0 -SDMA_PERF_SEL_IDLE = 1 -SDMA_PERF_SEL_REG_IDLE = 2 -SDMA_PERF_SEL_RB_EMPTY = 3 -SDMA_PERF_SEL_RB_FULL = 4 -SDMA_PERF_SEL_RB_WPTR_WRAP = 5 -SDMA_PERF_SEL_RB_RPTR_WRAP = 6 -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERF_SEL_RB_RPTR_WB = 8 -SDMA_PERF_SEL_RB_CMD_IDLE = 9 -SDMA_PERF_SEL_RB_CMD_FULL = 10 -SDMA_PERF_SEL_IB_CMD_IDLE = 11 -SDMA_PERF_SEL_IB_CMD_FULL = 12 -SDMA_PERF_SEL_EX_IDLE = 13 -SDMA_PERF_SEL_SRBM_REG_SEND = 14 -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERF_SEL_MC_WR_IDLE = 16 -SDMA_PERF_SEL_MC_WR_COUNT = 17 -SDMA_PERF_SEL_MC_RD_IDLE = 18 -SDMA_PERF_SEL_MC_RD_COUNT = 19 -SDMA_PERF_SEL_MC_RD_RET_STALL = 20 -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -SDMA_PERF_SEL_SEM_IDLE = 24 -SDMA_PERF_SEL_SEM_REQ_STALL = 25 -SDMA_PERF_SEL_SEM_REQ_COUNT = 26 -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -SDMA_PERF_SEL_SEM_RESP_FAIL = 28 -SDMA_PERF_SEL_SEM_RESP_PASS = 29 -SDMA_PERF_SEL_INT_IDLE = 30 -SDMA_PERF_SEL_INT_REQ_STALL = 31 -SDMA_PERF_SEL_INT_REQ_COUNT = 32 -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -SDMA_PERF_SEL_INT_RESP_RETRY = 34 -SDMA_PERF_SEL_NUM_PACKET = 35 -SDMA_PERF_SEL_CE_WREQ_IDLE = 37 -SDMA_PERF_SEL_CE_WR_IDLE = 38 -SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -SDMA_PERF_SEL_CE_RREQ_IDLE = 40 -SDMA_PERF_SEL_CE_OUT_IDLE = 41 -SDMA_PERF_SEL_CE_IN_IDLE = 42 -SDMA_PERF_SEL_CE_DST_IDLE = 43 -SDMA_PERF_SEL_CE_AFIFO_FULL = 46 -SDMA_PERF_SEL_CE_INFO_FULL = 49 -SDMA_PERF_SEL_CE_INFO1_FULL = 50 -SDMA_PERF_SEL_CE_RD_STALL = 51 -SDMA_PERF_SEL_CE_WR_STALL = 52 -SDMA_PERF_SEL_GFX_SELECT = 53 -SDMA_PERF_SEL_RLC0_SELECT = 54 -SDMA_PERF_SEL_RLC1_SELECT = 55 -SDMA_PERF_SEL_PAGE_SELECT = 56 -SDMA_PERF_SEL_CTX_CHANGE = 57 -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -SDMA_PERF_SEL_DOORBELL = 60 -SDMA_PERF_SEL_RD_BA_RTR = 61 -SDMA_PERF_SEL_WR_BA_RTR = 62 -SDMA_PERF_SEL_F32_L1_WR_VLD = 63 -SDMA_PERF_SEL_CE_L1_WR_VLD = 64 -SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERF_SEL_UTCL2_RET_ACK = 72 -SDMA_PERF_SEL_UTCL2_FREE = 73 -SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERF_SEL_GPUVM_INV_LOW = 80 -SDMA_PERF_SEL_L1_WRL2_IDLE = 81 -SDMA_PERF_SEL_L1_RDL2_IDLE = 82 -SDMA_PERF_SEL_L1_WRMC_IDLE = 83 -SDMA_PERF_SEL_L1_RDMC_IDLE = 84 -SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERF_SEL_META_L2_REQ_SEND = 87 -SDMA_PERF_SEL_L2_META_RET_VLD = 88 -SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERF_SEL_META_REQ_SEND = 93 -SDMA_PERF_SEL_META_RTN_VLD = 94 -SDMA_PERF_SEL_TLBI_SEND = 95 -SDMA_PERF_SEL_TLBI_RTN = 96 -SDMA_PERF_SEL_GCR_SEND = 97 -SDMA_PERF_SEL_GCR_RTN = 98 -SDMA_PERF_SEL_CGCG_FENCE = 99 -SDMA_PERF_SEL_CE_CH_WR_REQ = 100 -SDMA_PERF_SEL_CE_CH_WR_RET = 101 -SDMA_PERF_SEL_F32_CH_WR_REQ = 102 -SDMA_PERF_SEL_F32_CH_WR_RET = 103 -SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104 -SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105 -SDMA_PERF_SEL_RB_CH_RD_REQ = 106 -SDMA_PERF_SEL_RB_CH_RD_RET = 107 -SDMA_PERF_SEL_IB_CH_RD_REQ = 108 -SDMA_PERF_SEL_IB_CH_RD_RET = 109 -SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 -SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 -SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 -SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 -SDMA_PERF_SEL_CMD_OP_MATCH = 114 -SDMA_PERF_SEL_CMD_OP_START = 115 -SDMA_PERF_SEL_CMD_OP_END = 116 -SDMA_PERF_SEL_CE_BUSY = 117 -SDMA_PERF_SEL_CE_BUSY_START = 118 -SDMA_PERF_SEL_CE_BUSY_END = 119 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122 -SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 -SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 -SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 -SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 -SDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_CACHE_POLICIES' -TCC_CACHE_POLICIES__enumvalues = { - 0: 'TCC_CACHE_POLICY_LRU', - 1: 'TCC_CACHE_POLICY_STREAM', -} -TCC_CACHE_POLICY_LRU = 0 -TCC_CACHE_POLICY_STREAM = 1 -TCC_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_MTYPE' -TCC_MTYPE__enumvalues = { - 0: 'MTYPE_NC', - 1: 'MTYPE_WC', - 2: 'MTYPE_CC', -} -MTYPE_NC = 0 -MTYPE_WC = 1 -MTYPE_CC = 2 -TCC_MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0FaultType' -UTCL0FaultType__enumvalues = { - 0: 'UTCL0_XNACK_SUCCESS', - 1: 'UTCL0_XNACK_RETRY', - 2: 'UTCL0_XNACK_PRT', - 3: 'UTCL0_XNACK_NO_RETRY', -} -UTCL0_XNACK_SUCCESS = 0 -UTCL0_XNACK_RETRY = 1 -UTCL0_XNACK_PRT = 2 -UTCL0_XNACK_NO_RETRY = 3 -UTCL0FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0RequestType' -UTCL0RequestType__enumvalues = { - 0: 'UTCL0_TYPE_NORMAL', - 1: 'UTCL0_TYPE_SHOOTDOWN', - 2: 'UTCL0_TYPE_BYPASS', -} -UTCL0_TYPE_NORMAL = 0 -UTCL0_TYPE_SHOOTDOWN = 1 -UTCL0_TYPE_BYPASS = 2 -UTCL0RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1FaultType' -UTCL1FaultType__enumvalues = { - 0: 'UTCL1_XNACK_SUCCESS', - 1: 'UTCL1_XNACK_RETRY', - 2: 'UTCL1_XNACK_PRT', - 3: 'UTCL1_XNACK_NO_RETRY', -} -UTCL1_XNACK_SUCCESS = 0 -UTCL1_XNACK_RETRY = 1 -UTCL1_XNACK_PRT = 2 -UTCL1_XNACK_NO_RETRY = 3 -UTCL1FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1RequestType' -UTCL1RequestType__enumvalues = { - 0: 'UTCL1_TYPE_NORMAL', - 1: 'UTCL1_TYPE_SHOOTDOWN', - 2: 'UTCL1_TYPE_BYPASS', -} -UTCL1_TYPE_NORMAL = 0 -UTCL1_TYPE_SHOOTDOWN = 1 -UTCL1_TYPE_BYPASS = 2 -UTCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'VMEMCMD_RETURN_ORDER' -VMEMCMD_RETURN_ORDER__enumvalues = { - 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', - 1: 'VMEMCMD_RETURN_IN_ORDER', - 2: 'VMEMCMD_RETURN_IN_ORDER_READ', -} -VMEMCMD_RETURN_OUT_OF_ORDER = 0 -VMEMCMD_RETURN_IN_ORDER = 1 -VMEMCMD_RETURN_IN_ORDER_READ = 2 -VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'WritePolicy' -WritePolicy__enumvalues = { - 0: 'CACHE_LRU_WR', - 1: 'CACHE_STREAM', - 2: 'CACHE_NOA_WR', - 3: 'CACHE_BYPASS', -} -CACHE_LRU_WR = 0 -CACHE_STREAM = 1 -CACHE_NOA_WR = 2 -CACHE_BYPASS = 3 -WritePolicy = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_BYPASS' -CNVC_BYPASS__enumvalues = { - 0: 'CNVC_BYPASS_DISABLE', - 1: 'CNVC_BYPASS_EN', -} -CNVC_BYPASS_DISABLE = 0 -CNVC_BYPASS_EN = 1 -CNVC_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_COEF_FORMAT_ENUM' -CNVC_COEF_FORMAT_ENUM__enumvalues = { - 0: 'CNVC_FIX_S2_13', - 1: 'CNVC_FIX_S3_12', -} -CNVC_FIX_S2_13 = 0 -CNVC_FIX_S3_12 = 1 -CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_ENABLE' -CNVC_ENABLE__enumvalues = { - 0: 'CNVC_DIS', - 1: 'CNVC_EN', -} -CNVC_DIS = 0 -CNVC_EN = 1 -CNVC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_PENDING' -CNVC_PENDING__enumvalues = { - 0: 'CNVC_NOT_PENDING', - 1: 'CNVC_YES_PENDING', -} -CNVC_NOT_PENDING = 0 -CNVC_YES_PENDING = 1 -CNVC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'COLOR_KEYER_MODE' -COLOR_KEYER_MODE__enumvalues = { - 0: 'FORCE_00', - 1: 'FORCE_FF', - 2: 'RANGE_00', - 3: 'RANGE_FF', -} -FORCE_00 = 0 -FORCE_FF = 1 -RANGE_00 = 2 -RANGE_FF = 3 -COLOR_KEYER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DENORM_TRUNCATE' -DENORM_TRUNCATE__enumvalues = { - 0: 'CNVC_ROUND', - 1: 'CNVC_TRUNCATE', -} -CNVC_ROUND = 0 -CNVC_TRUNCATE = 1 -DENORM_TRUNCATE = ctypes.c_uint32 # enum - -# values for enumeration 'FORMAT_CROSSBAR' -FORMAT_CROSSBAR__enumvalues = { - 0: 'FORMAT_CROSSBAR_R', - 1: 'FORMAT_CROSSBAR_G', - 2: 'FORMAT_CROSSBAR_B', -} -FORMAT_CROSSBAR_R = 0 -FORMAT_CROSSBAR_G = 1 -FORMAT_CROSSBAR_B = 2 -FORMAT_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'PIX_EXPAND_MODE' -PIX_EXPAND_MODE__enumvalues = { - 0: 'PIX_DYNAMIC_EXPANSION', - 1: 'PIX_ZERO_EXPANSION', -} -PIX_DYNAMIC_EXPANSION = 0 -PIX_ZERO_EXPANSION = 1 -PIX_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_CSC_MODE_ENUM' -PRE_CSC_MODE_ENUM__enumvalues = { - 0: 'PRE_CSC_BYPASS', - 1: 'PRE_CSC_SET_A', - 2: 'PRE_CSC_SET_B', -} -PRE_CSC_BYPASS = 0 -PRE_CSC_SET_A = 1 -PRE_CSC_SET_B = 2 -PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_MODE' -PRE_DEGAM_MODE__enumvalues = { - 0: 'PRE_DEGAM_BYPASS', - 1: 'PRE_DEGAM_ENABLE', -} -PRE_DEGAM_BYPASS = 0 -PRE_DEGAM_ENABLE = 1 -PRE_DEGAM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_SELECT' -PRE_DEGAM_SELECT__enumvalues = { - 0: 'PRE_DEGAM_SRGB', - 1: 'PRE_DEGAM_GAMMA_22', - 2: 'PRE_DEGAM_GAMMA_24', - 3: 'PRE_DEGAM_GAMMA_26', - 4: 'PRE_DEGAM_BT2020', - 5: 'PRE_DEGAM_BT2100PQ', - 6: 'PRE_DEGAM_BT2100HLG', -} -PRE_DEGAM_SRGB = 0 -PRE_DEGAM_GAMMA_22 = 1 -PRE_DEGAM_GAMMA_24 = 2 -PRE_DEGAM_GAMMA_26 = 3 -PRE_DEGAM_BT2020 = 4 -PRE_DEGAM_BT2100PQ = 5 -PRE_DEGAM_BT2100HLG = 6 -PRE_DEGAM_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_PIXEL_FORMAT' -SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'ARGB1555', - 2: 'RGBA5551', - 3: 'RGB565', - 4: 'BGR565', - 5: 'ARGB4444', - 6: 'RGBA4444', - 8: 'ARGB8888', - 9: 'RGBA8888', - 10: 'ARGB2101010', - 11: 'RGBA1010102', - 12: 'AYCrCb8888', - 13: 'YCrCbA8888', - 14: 'ACrYCb8888', - 15: 'CrYCbA8888', - 16: 'ARGB16161616_10MSB', - 17: 'RGBA16161616_10MSB', - 18: 'ARGB16161616_10LSB', - 19: 'RGBA16161616_10LSB', - 20: 'ARGB16161616_12MSB', - 21: 'RGBA16161616_12MSB', - 22: 'ARGB16161616_12LSB', - 23: 'RGBA16161616_12LSB', - 24: 'ARGB16161616_FLOAT', - 25: 'RGBA16161616_FLOAT', - 26: 'ARGB16161616_UNORM', - 27: 'RGBA16161616_UNORM', - 28: 'ARGB16161616_SNORM', - 29: 'RGBA16161616_SNORM', - 32: 'AYCrCb16161616_10MSB', - 33: 'AYCrCb16161616_10LSB', - 34: 'YCrCbA16161616_10MSB', - 35: 'YCrCbA16161616_10LSB', - 36: 'ACrYCb16161616_10MSB', - 37: 'ACrYCb16161616_10LSB', - 38: 'CrYCbA16161616_10MSB', - 39: 'CrYCbA16161616_10LSB', - 40: 'AYCrCb16161616_12MSB', - 41: 'AYCrCb16161616_12LSB', - 42: 'YCrCbA16161616_12MSB', - 43: 'YCrCbA16161616_12LSB', - 44: 'ACrYCb16161616_12MSB', - 45: 'ACrYCb16161616_12LSB', - 46: 'CrYCbA16161616_12MSB', - 47: 'CrYCbA16161616_12LSB', - 64: 'Y8_CrCb88_420_PLANAR', - 65: 'Y8_CbCr88_420_PLANAR', - 66: 'Y10_CrCb1010_420_PLANAR', - 67: 'Y10_CbCr1010_420_PLANAR', - 68: 'Y12_CrCb1212_420_PLANAR', - 69: 'Y12_CbCr1212_420_PLANAR', - 72: 'YCrYCb8888_422_PACKED', - 73: 'YCbYCr8888_422_PACKED', - 74: 'CrYCbY8888_422_PACKED', - 75: 'CbYCrY8888_422_PACKED', - 76: 'YCrYCb10101010_422_PACKED', - 77: 'YCbYCr10101010_422_PACKED', - 78: 'CrYCbY10101010_422_PACKED', - 79: 'CbYCrY10101010_422_PACKED', - 80: 'YCrYCb12121212_422_PACKED', - 81: 'YCbYCr12121212_422_PACKED', - 82: 'CrYCbY12121212_422_PACKED', - 83: 'CbYCrY12121212_422_PACKED', - 112: 'RGB111110_FIX', - 113: 'BGR101111_FIX', - 114: 'ACrYCb2101010', - 115: 'CrYCbA1010102', - 116: 'RGBE', - 118: 'RGB111110_FLOAT', - 119: 'BGR101111_FLOAT', - 120: 'MONO_8', - 121: 'MONO_10MSB', - 122: 'MONO_10LSB', - 123: 'MONO_12MSB', - 124: 'MONO_12LSB', - 125: 'MONO_16', -} -ARGB1555 = 1 -RGBA5551 = 2 -RGB565 = 3 -BGR565 = 4 -ARGB4444 = 5 -RGBA4444 = 6 -ARGB8888 = 8 -RGBA8888 = 9 -ARGB2101010 = 10 -RGBA1010102 = 11 -AYCrCb8888 = 12 -YCrCbA8888 = 13 -ACrYCb8888 = 14 -CrYCbA8888 = 15 -ARGB16161616_10MSB = 16 -RGBA16161616_10MSB = 17 -ARGB16161616_10LSB = 18 -RGBA16161616_10LSB = 19 -ARGB16161616_12MSB = 20 -RGBA16161616_12MSB = 21 -ARGB16161616_12LSB = 22 -RGBA16161616_12LSB = 23 -ARGB16161616_FLOAT = 24 -RGBA16161616_FLOAT = 25 -ARGB16161616_UNORM = 26 -RGBA16161616_UNORM = 27 -ARGB16161616_SNORM = 28 -RGBA16161616_SNORM = 29 -AYCrCb16161616_10MSB = 32 -AYCrCb16161616_10LSB = 33 -YCrCbA16161616_10MSB = 34 -YCrCbA16161616_10LSB = 35 -ACrYCb16161616_10MSB = 36 -ACrYCb16161616_10LSB = 37 -CrYCbA16161616_10MSB = 38 -CrYCbA16161616_10LSB = 39 -AYCrCb16161616_12MSB = 40 -AYCrCb16161616_12LSB = 41 -YCrCbA16161616_12MSB = 42 -YCrCbA16161616_12LSB = 43 -ACrYCb16161616_12MSB = 44 -ACrYCb16161616_12LSB = 45 -CrYCbA16161616_12MSB = 46 -CrYCbA16161616_12LSB = 47 -Y8_CrCb88_420_PLANAR = 64 -Y8_CbCr88_420_PLANAR = 65 -Y10_CrCb1010_420_PLANAR = 66 -Y10_CbCr1010_420_PLANAR = 67 -Y12_CrCb1212_420_PLANAR = 68 -Y12_CbCr1212_420_PLANAR = 69 -YCrYCb8888_422_PACKED = 72 -YCbYCr8888_422_PACKED = 73 -CrYCbY8888_422_PACKED = 74 -CbYCrY8888_422_PACKED = 75 -YCrYCb10101010_422_PACKED = 76 -YCbYCr10101010_422_PACKED = 77 -CrYCbY10101010_422_PACKED = 78 -CbYCrY10101010_422_PACKED = 79 -YCrYCb12121212_422_PACKED = 80 -YCbYCr12121212_422_PACKED = 81 -CrYCbY12121212_422_PACKED = 82 -CbYCrY12121212_422_PACKED = 83 -RGB111110_FIX = 112 -BGR101111_FIX = 113 -ACrYCb2101010 = 114 -CrYCbA1010102 = 115 -RGBE = 116 -RGB111110_FLOAT = 118 -BGR101111_FLOAT = 119 -MONO_8 = 120 -MONO_10MSB = 121 -MONO_10LSB = 122 -MONO_12MSB = 123 -MONO_12LSB = 124 -MONO_16 = 125 -SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'XNORM' -XNORM__enumvalues = { - 0: 'XNORM_A', - 1: 'XNORM_B', -} -XNORM_A = 0 -XNORM_B = 1 -XNORM = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ENABLE' -CUR_ENABLE__enumvalues = { - 0: 'CUR_DIS', - 1: 'CUR_EN', -} -CUR_DIS = 0 -CUR_EN = 1 -CUR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_EXPAND_MODE' -CUR_EXPAND_MODE__enumvalues = { - 0: 'CUR_DYNAMIC_EXPANSION', - 1: 'CUR_ZERO_EXPANSION', -} -CUR_DYNAMIC_EXPANSION = 0 -CUR_ZERO_EXPANSION = 1 -CUR_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_INV_CLAMP' -CUR_INV_CLAMP__enumvalues = { - 0: 'CUR_CLAMP_DIS', - 1: 'CUR_CLAMP_EN', -} -CUR_CLAMP_DIS = 0 -CUR_CLAMP_EN = 1 -CUR_INV_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_MODE' -CUR_MODE__enumvalues = { - 0: 'MONO_2BIT', - 1: 'COLOR_24BIT_1BIT_AND', - 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'COLOR_64BIT_FP_PREMULT', - 5: 'COLOR_64BIT_FP_UNPREMULT', -} -MONO_2BIT = 0 -COLOR_24BIT_1BIT_AND = 1 -COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -COLOR_64BIT_FP_PREMULT = 4 -COLOR_64BIT_FP_UNPREMULT = 5 -CUR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_PENDING' -CUR_PENDING__enumvalues = { - 0: 'CUR_NOT_PENDING', - 1: 'CUR_YES_PENDING', -} -CUR_NOT_PENDING = 0 -CUR_YES_PENDING = 1 -CUR_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ROM_EN' -CUR_ROM_EN__enumvalues = { - 0: 'CUR_FP_NO_ROM', - 1: 'CUR_FP_USE_ROM', -} -CUR_FP_NO_ROM = 0 -CUR_FP_USE_ROM = 1 -CUR_ROM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'COEF_RAM_SELECT_RD' -COEF_RAM_SELECT_RD__enumvalues = { - 0: 'COEF_RAM_SELECT_BACK', - 1: 'COEF_RAM_SELECT_CURRENT', -} -COEF_RAM_SELECT_BACK = 0 -COEF_RAM_SELECT_CURRENT = 1 -COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum - -# values for enumeration 'DSCL_MODE_SEL' -DSCL_MODE_SEL__enumvalues = { - 0: 'DSCL_MODE_SCALING_444_BYPASS', - 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', - 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', - 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', - 6: 'DSCL_MODE_DSCL_BYPASS', -} -DSCL_MODE_SCALING_444_BYPASS = 0 -DSCL_MODE_SCALING_444_RGB_ENABLE = 1 -DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 -DSCL_MODE_SCALING_YCBCR_ENABLE = 3 -DSCL_MODE_LUMA_SCALING_BYPASS = 4 -DSCL_MODE_CHROMA_SCALING_BYPASS = 5 -DSCL_MODE_DSCL_BYPASS = 6 -DSCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LB_ALPHA_EN' -LB_ALPHA_EN__enumvalues = { - 0: 'LB_ALPHA_DISABLE', - 1: 'LB_ALPHA_ENABLE', -} -LB_ALPHA_DISABLE = 0 -LB_ALPHA_ENABLE = 1 -LB_ALPHA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERLEAVE_EN' -LB_INTERLEAVE_EN__enumvalues = { - 0: 'LB_INTERLEAVE_DISABLE', - 1: 'LB_INTERLEAVE_ENABLE', -} -LB_INTERLEAVE_DISABLE = 0 -LB_INTERLEAVE_ENABLE = 1 -LB_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MEMORY_CONFIG' -LB_MEMORY_CONFIG__enumvalues = { - 0: 'LB_MEMORY_CONFIG_0', - 1: 'LB_MEMORY_CONFIG_1', - 2: 'LB_MEMORY_CONFIG_2', - 3: 'LB_MEMORY_CONFIG_3', -} -LB_MEMORY_CONFIG_0 = 0 -LB_MEMORY_CONFIG_1 = 1 -LB_MEMORY_CONFIG_2 = 2 -LB_MEMORY_CONFIG_3 = 3 -LB_MEMORY_CONFIG = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_BYPASS_SEL' -OBUF_BYPASS_SEL__enumvalues = { - 0: 'OBUF_BYPASS_DIS', - 1: 'OBUF_BYPASS_EN', -} -OBUF_BYPASS_DIS = 0 -OBUF_BYPASS_EN = 1 -OBUF_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' -OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { - 0: 'OBUF_FULL_RECOUT', - 1: 'OBUF_HALF_RECOUT', -} -OBUF_FULL_RECOUT = 0 -OBUF_HALF_RECOUT = 1 -OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' -OBUF_USE_FULL_BUFFER_SEL__enumvalues = { - 0: 'OBUF_RECOUT', - 1: 'OBUF_FULL', -} -OBUF_RECOUT = 0 -OBUF_FULL = 1 -OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_2TAP_HARDCODE' -SCL_2TAP_HARDCODE__enumvalues = { - 0: 'SCL_COEF_2TAP_HARDCODE_OFF', - 1: 'SCL_COEF_2TAP_HARDCODE_ON', -} -SCL_COEF_2TAP_HARDCODE_OFF = 0 -SCL_COEF_2TAP_HARDCODE_ON = 1 -SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_ALPHA_COEF' -SCL_ALPHA_COEF__enumvalues = { - 0: 'SCL_ALPHA_COEF_FIRST', - 1: 'SCL_ALPHA_COEF_SECOND', -} -SCL_ALPHA_COEF_FIRST = 0 -SCL_ALPHA_COEF_SECOND = 1 -SCL_ALPHA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_AUTOCAL_MODE' -SCL_AUTOCAL_MODE__enumvalues = { - 0: 'AUTOCAL_MODE_OFF', - 1: 'AUTOCAL_MODE_AUTOSCALE', - 2: 'AUTOCAL_MODE_AUTOCENTER', - 3: 'AUTOCAL_MODE_AUTOREPLICATE', -} -AUTOCAL_MODE_OFF = 0 -AUTOCAL_MODE_AUTOSCALE = 1 -AUTOCAL_MODE_AUTOCENTER = 2 -AUTOCAL_MODE_AUTOREPLICATE = 3 -SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BOUNDARY' -SCL_BOUNDARY__enumvalues = { - 0: 'SCL_BOUNDARY_EDGE', - 1: 'SCL_BOUNDARY_BLACK', -} -SCL_BOUNDARY_EDGE = 0 -SCL_BOUNDARY_BLACK = 1 -SCL_BOUNDARY = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_CHROMA_COEF' -SCL_CHROMA_COEF__enumvalues = { - 0: 'SCL_CHROMA_COEF_FIRST', - 1: 'SCL_CHROMA_COEF_SECOND', -} -SCL_CHROMA_COEF_FIRST = 0 -SCL_CHROMA_COEF_SECOND = 1 -SCL_CHROMA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' -SCL_COEF_FILTER_TYPE_SEL__enumvalues = { - 0: 'SCL_COEF_LUMA_VERT_FILTER', - 1: 'SCL_COEF_LUMA_HORZ_FILTER', - 2: 'SCL_COEF_CHROMA_VERT_FILTER', - 3: 'SCL_COEF_CHROMA_HORZ_FILTER', -} -SCL_COEF_LUMA_VERT_FILTER = 0 -SCL_COEF_LUMA_HORZ_FILTER = 1 -SCL_COEF_CHROMA_VERT_FILTER = 2 -SCL_COEF_CHROMA_HORZ_FILTER = 3 -SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_RAM_SEL' -SCL_COEF_RAM_SEL__enumvalues = { - 0: 'SCL_COEF_RAM_SEL_0', - 1: 'SCL_COEF_RAM_SEL_1', -} -SCL_COEF_RAM_SEL_0 = 0 -SCL_COEF_RAM_SEL_1 = 1 -SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_SHARP_EN' -SCL_SHARP_EN__enumvalues = { - 0: 'SCL_SHARP_DISABLE', - 1: 'SCL_SHARP_ENABLE', -} -SCL_SHARP_DISABLE = 0 -SCL_SHARP_ENABLE = 1 -SCL_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_30BIT_ENUM' -CMC_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'CMC_3DLUT_36BIT', - 1: 'CMC_3DLUT_30BIT', -} -CMC_3DLUT_36BIT = 0 -CMC_3DLUT_30BIT = 1 -CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_RAM_SEL' -CMC_3DLUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAM0_ACCESS', - 1: 'CMC_RAM1_ACCESS', - 2: 'CMC_RAM2_ACCESS', - 3: 'CMC_RAM3_ACCESS', -} -CMC_RAM0_ACCESS = 0 -CMC_RAM1_ACCESS = 1 -CMC_RAM2_ACCESS = 2 -CMC_RAM3_ACCESS = 3 -CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_SIZE_ENUM' -CMC_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'CMC_3DLUT_17CUBE', - 1: 'CMC_3DLUT_9CUBE', -} -CMC_3DLUT_17CUBE = 0 -CMC_3DLUT_9CUBE = 1 -CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' -CMC_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'CMC_LUT_2CFG_NO_MEMORY', - 1: 'CMC_LUT_2CFG_MEMORY_A', - 2: 'CMC_LUT_2CFG_MEMORY_B', -} -CMC_LUT_2CFG_NO_MEMORY = 0 -CMC_LUT_2CFG_MEMORY_A = 1 -CMC_LUT_2CFG_MEMORY_B = 2 -CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_MODE_ENUM' -CMC_LUT_2_MODE_ENUM__enumvalues = { - 0: 'CMC_LUT_2_MODE_BYPASS', - 1: 'CMC_LUT_2_MODE_RAMA_LUT', - 2: 'CMC_LUT_2_MODE_RAMB_LUT', -} -CMC_LUT_2_MODE_BYPASS = 0 -CMC_LUT_2_MODE_RAMA_LUT = 1 -CMC_LUT_2_MODE_RAMB_LUT = 2 -CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_NUM_SEG' -CMC_LUT_NUM_SEG__enumvalues = { - 0: 'CMC_SEGMENTS_1', - 1: 'CMC_SEGMENTS_2', - 2: 'CMC_SEGMENTS_4', - 3: 'CMC_SEGMENTS_8', - 4: 'CMC_SEGMENTS_16', - 5: 'CMC_SEGMENTS_32', - 6: 'CMC_SEGMENTS_64', - 7: 'CMC_SEGMENTS_128', -} -CMC_SEGMENTS_1 = 0 -CMC_SEGMENTS_2 = 1 -CMC_SEGMENTS_4 = 2 -CMC_SEGMENTS_8 = 3 -CMC_SEGMENTS_16 = 4 -CMC_SEGMENTS_32 = 5 -CMC_SEGMENTS_64 = 6 -CMC_SEGMENTS_128 = 7 -CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_RAM_SEL' -CMC_LUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAMA_ACCESS', - 1: 'CMC_RAMB_ACCESS', -} -CMC_RAMA_ACCESS = 0 -CMC_RAMB_ACCESS = 1 -CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_BYPASS' -CM_BYPASS__enumvalues = { - 0: 'NON_BYPASS', - 1: 'BYPASS_EN', -} -NON_BYPASS = 0 -BYPASS_EN = 1 -CM_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CM_COEF_FORMAT_ENUM' -CM_COEF_FORMAT_ENUM__enumvalues = { - 0: 'FIX_S2_13', - 1: 'FIX_S3_12', -} -FIX_S2_13 = 0 -FIX_S3_12 = 1 -CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_DATA_SIGNED' -CM_DATA_SIGNED__enumvalues = { - 0: 'UNSIGNED', - 1: 'SIGNED', -} -UNSIGNED = 0 -SIGNED = 1 -CM_DATA_SIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'CM_EN' -CM_EN__enumvalues = { - 0: 'CM_DISABLE', - 1: 'CM_ENABLE', -} -CM_DISABLE = 0 -CM_ENABLE = 1 -CM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' -CM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'BYPASS', - 1: 'RESERVED_1', - 2: 'RAM_LUT', - 3: 'RESERVED_3', -} -BYPASS = 0 -RESERVED_1 = 1 -RAM_LUT = 2 -RESERVED_3 = 3 -CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' -CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'ENABLE_PWL', - 1: 'DISABLE_PWL', -} -ENABLE_PWL = 0 -DISABLE_PWL = 1 -CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' -CM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'RAMA', - 1: 'RAMB', -} -RAMA = 0 -RAMB = 1 -CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' -CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'BYPASS_GAMUT', - 1: 'GAMUT_COEF', - 2: 'GAMUT_COEF_B', -} -BYPASS_GAMUT = 0 -GAMUT_COEF = 1 -GAMUT_COEF_B = 2 -CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_CONFIG_ENUM' -CM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'LUT_2CFG_NO_MEMORY', - 1: 'LUT_2CFG_MEMORY_A', - 2: 'LUT_2CFG_MEMORY_B', -} -LUT_2CFG_NO_MEMORY = 0 -LUT_2CFG_MEMORY_A = 1 -LUT_2CFG_MEMORY_B = 2 -CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_MODE_ENUM' -CM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'LUT_2_MODE_BYPASS', - 1: 'LUT_2_MODE_RAMA_LUT', - 2: 'LUT_2_MODE_RAMB_LUT', -} -LUT_2_MODE_BYPASS = 0 -LUT_2_MODE_RAMA_LUT = 1 -LUT_2_MODE_RAMB_LUT = 2 -CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_CONFIG_ENUM' -CM_LUT_4_CONFIG_ENUM__enumvalues = { - 0: 'LUT_4CFG_NO_MEMORY', - 1: 'LUT_4CFG_ROM_A', - 2: 'LUT_4CFG_ROM_B', - 3: 'LUT_4CFG_MEMORY_A', - 4: 'LUT_4CFG_MEMORY_B', -} -LUT_4CFG_NO_MEMORY = 0 -LUT_4CFG_ROM_A = 1 -LUT_4CFG_ROM_B = 2 -LUT_4CFG_MEMORY_A = 3 -LUT_4CFG_MEMORY_B = 4 -CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_MODE_ENUM' -CM_LUT_4_MODE_ENUM__enumvalues = { - 0: 'LUT_4_MODE_BYPASS', - 1: 'LUT_4_MODE_ROMA_LUT', - 2: 'LUT_4_MODE_ROMB_LUT', - 3: 'LUT_4_MODE_RAMA_LUT', - 4: 'LUT_4_MODE_RAMB_LUT', -} -LUT_4_MODE_BYPASS = 0 -LUT_4_MODE_ROMA_LUT = 1 -LUT_4_MODE_ROMB_LUT = 2 -LUT_4_MODE_RAMA_LUT = 3 -LUT_4_MODE_RAMB_LUT = 4 -CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_CONFIG_MODE' -CM_LUT_CONFIG_MODE__enumvalues = { - 0: 'DIFFERENT_RGB', - 1: 'ALL_USE_R', -} -DIFFERENT_RGB = 0 -ALL_USE_R = 1 -CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_NUM_SEG' -CM_LUT_NUM_SEG__enumvalues = { - 0: 'SEGMENTS_1', - 1: 'SEGMENTS_2', - 2: 'SEGMENTS_4', - 3: 'SEGMENTS_8', - 4: 'SEGMENTS_16', - 5: 'SEGMENTS_32', - 6: 'SEGMENTS_64', - 7: 'SEGMENTS_128', -} -SEGMENTS_1 = 0 -SEGMENTS_2 = 1 -SEGMENTS_4 = 2 -SEGMENTS_8 = 3 -SEGMENTS_16 = 4 -SEGMENTS_32 = 5 -SEGMENTS_64 = 6 -SEGMENTS_128 = 7 -CM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_RAM_SEL' -CM_LUT_RAM_SEL__enumvalues = { - 0: 'RAMA_ACCESS', - 1: 'RAMB_ACCESS', -} -RAMA_ACCESS = 0 -RAMB_ACCESS = 1 -CM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_COLOR_SEL' -CM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'BLUE_LUT', - 1: 'GREEN_LUT', - 2: 'RED_LUT', -} -BLUE_LUT = 0 -GREEN_LUT = 1 -RED_LUT = 2 -CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_DBG' -CM_LUT_READ_DBG__enumvalues = { - 0: 'DISABLE_DEBUG', - 1: 'ENABLE_DEBUG', -} -DISABLE_DEBUG = 0 -ENABLE_DEBUG = 1 -CM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_PENDING' -CM_PENDING__enumvalues = { - 0: 'CM_NOT_PENDING', - 1: 'CM_YES_PENDING', -} -CM_NOT_PENDING = 0 -CM_YES_PENDING = 1 -CM_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CM_POST_CSC_MODE_ENUM' -CM_POST_CSC_MODE_ENUM__enumvalues = { - 0: 'BYPASS_POST_CSC', - 1: 'COEF_POST_CSC', - 2: 'COEF_POST_CSC_B', -} -BYPASS_POST_CSC = 0 -COEF_POST_CSC = 1 -COEF_POST_CSC_B = 2 -CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_WRITE_BASE_ONLY' -CM_WRITE_BASE_ONLY__enumvalues = { - 0: 'WRITE_BOTH', - 1: 'WRITE_BASE_ONLY', -} -WRITE_BOTH = 0 -WRITE_BASE_ONLY = 1 -CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_CUR_SEL' -CRC_CUR_SEL__enumvalues = { - 0: 'CRC_CUR_0', - 1: 'CRC_CUR_1', -} -CRC_CUR_0 = 0 -CRC_CUR_1 = 1 -CRC_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_INTERLACE_SEL' -CRC_INTERLACE_SEL__enumvalues = { - 0: 'CRC_INTERLACE_0', - 1: 'CRC_INTERLACE_1', - 2: 'CRC_INTERLACE_2', - 3: 'CRC_INTERLACE_3', -} -CRC_INTERLACE_0 = 0 -CRC_INTERLACE_1 = 1 -CRC_INTERLACE_2 = 2 -CRC_INTERLACE_3 = 3 -CRC_INTERLACE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_CUR_SEL' -CRC_IN_CUR_SEL__enumvalues = { - 0: 'CRC_IN_CUR_0', - 1: 'CRC_IN_CUR_1', - 2: 'CRC_IN_CUR_2', - 3: 'CRC_IN_CUR_3', -} -CRC_IN_CUR_0 = 0 -CRC_IN_CUR_1 = 1 -CRC_IN_CUR_2 = 2 -CRC_IN_CUR_3 = 3 -CRC_IN_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_PIX_SEL' -CRC_IN_PIX_SEL__enumvalues = { - 0: 'CRC_IN_PIX_0', - 1: 'CRC_IN_PIX_1', - 2: 'CRC_IN_PIX_2', - 3: 'CRC_IN_PIX_3', - 4: 'CRC_IN_PIX_4', - 5: 'CRC_IN_PIX_5', - 6: 'CRC_IN_PIX_6', - 7: 'CRC_IN_PIX_7', -} -CRC_IN_PIX_0 = 0 -CRC_IN_PIX_1 = 1 -CRC_IN_PIX_2 = 2 -CRC_IN_PIX_3 = 3 -CRC_IN_PIX_4 = 4 -CRC_IN_PIX_5 = 5 -CRC_IN_PIX_6 = 6 -CRC_IN_PIX_7 = 7 -CRC_IN_PIX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_SRC_SEL' -CRC_SRC_SEL__enumvalues = { - 0: 'CRC_SRC_0', - 1: 'CRC_SRC_1', - 2: 'CRC_SRC_2', - 3: 'CRC_SRC_3', -} -CRC_SRC_0 = 0 -CRC_SRC_1 = 1 -CRC_SRC_2 = 2 -CRC_SRC_3 = 3 -CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_STEREO_SEL' -CRC_STEREO_SEL__enumvalues = { - 0: 'CRC_STEREO_0', - 1: 'CRC_STEREO_1', - 2: 'CRC_STEREO_2', - 3: 'CRC_STEREO_3', -} -CRC_STEREO_0 = 0 -CRC_STEREO_1 = 1 -CRC_STEREO_2 = 2 -CRC_STEREO_3 = 3 -CRC_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_SEL' -TEST_CLK_SEL__enumvalues = { - 0: 'TEST_CLK_SEL_0', - 1: 'TEST_CLK_SEL_1', - 2: 'TEST_CLK_SEL_2', - 3: 'TEST_CLK_SEL_3', - 4: 'TEST_CLK_SEL_4', - 5: 'TEST_CLK_SEL_5', - 6: 'TEST_CLK_SEL_6', - 7: 'TEST_CLK_SEL_7', -} -TEST_CLK_SEL_0 = 0 -TEST_CLK_SEL_1 = 1 -TEST_CLK_SEL_2 = 2 -TEST_CLK_SEL_3 = 3 -TEST_CLK_SEL_4 = 4 -TEST_CLK_SEL_5 = 5 -TEST_CLK_SEL_6 = 6 -TEST_CLK_SEL_7 = 7 -TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_ACTIVE' -PERFCOUNTER_ACTIVE__enumvalues = { - 0: 'PERFCOUNTER_IS_IDLE', - 1: 'PERFCOUNTER_IS_ACTIVE', -} -PERFCOUNTER_IS_IDLE = 0 -PERFCOUNTER_IS_ACTIVE = 1 -PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT0_STATE' -PERFCOUNTER_CNT0_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT0_STATE_RESET', - 1: 'PERFCOUNTER_CNT0_STATE_START', - 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT0_STATE_HW', -} -PERFCOUNTER_CNT0_STATE_RESET = 0 -PERFCOUNTER_CNT0_STATE_START = 1 -PERFCOUNTER_CNT0_STATE_FREEZE = 2 -PERFCOUNTER_CNT0_STATE_HW = 3 -PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT1_STATE' -PERFCOUNTER_CNT1_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT1_STATE_RESET', - 1: 'PERFCOUNTER_CNT1_STATE_START', - 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT1_STATE_HW', -} -PERFCOUNTER_CNT1_STATE_RESET = 0 -PERFCOUNTER_CNT1_STATE_START = 1 -PERFCOUNTER_CNT1_STATE_FREEZE = 2 -PERFCOUNTER_CNT1_STATE_HW = 3 -PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT2_STATE' -PERFCOUNTER_CNT2_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT2_STATE_RESET', - 1: 'PERFCOUNTER_CNT2_STATE_START', - 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT2_STATE_HW', -} -PERFCOUNTER_CNT2_STATE_RESET = 0 -PERFCOUNTER_CNT2_STATE_START = 1 -PERFCOUNTER_CNT2_STATE_FREEZE = 2 -PERFCOUNTER_CNT2_STATE_HW = 3 -PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT3_STATE' -PERFCOUNTER_CNT3_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT3_STATE_RESET', - 1: 'PERFCOUNTER_CNT3_STATE_START', - 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT3_STATE_HW', -} -PERFCOUNTER_CNT3_STATE_RESET = 0 -PERFCOUNTER_CNT3_STATE_START = 1 -PERFCOUNTER_CNT3_STATE_FREEZE = 2 -PERFCOUNTER_CNT3_STATE_HW = 3 -PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT4_STATE' -PERFCOUNTER_CNT4_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT4_STATE_RESET', - 1: 'PERFCOUNTER_CNT4_STATE_START', - 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT4_STATE_HW', -} -PERFCOUNTER_CNT4_STATE_RESET = 0 -PERFCOUNTER_CNT4_STATE_START = 1 -PERFCOUNTER_CNT4_STATE_FREEZE = 2 -PERFCOUNTER_CNT4_STATE_HW = 3 -PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT5_STATE' -PERFCOUNTER_CNT5_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT5_STATE_RESET', - 1: 'PERFCOUNTER_CNT5_STATE_START', - 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT5_STATE_HW', -} -PERFCOUNTER_CNT5_STATE_RESET = 0 -PERFCOUNTER_CNT5_STATE_START = 1 -PERFCOUNTER_CNT5_STATE_FREEZE = 2 -PERFCOUNTER_CNT5_STATE_HW = 3 -PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT6_STATE' -PERFCOUNTER_CNT6_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT6_STATE_RESET', - 1: 'PERFCOUNTER_CNT6_STATE_START', - 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT6_STATE_HW', -} -PERFCOUNTER_CNT6_STATE_RESET = 0 -PERFCOUNTER_CNT6_STATE_START = 1 -PERFCOUNTER_CNT6_STATE_FREEZE = 2 -PERFCOUNTER_CNT6_STATE_HW = 3 -PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT7_STATE' -PERFCOUNTER_CNT7_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT7_STATE_RESET', - 1: 'PERFCOUNTER_CNT7_STATE_START', - 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT7_STATE_HW', -} -PERFCOUNTER_CNT7_STATE_RESET = 0 -PERFCOUNTER_CNT7_STATE_START = 1 -PERFCOUNTER_CNT7_STATE_FREEZE = 2 -PERFCOUNTER_CNT7_STATE_HW = 3 -PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTL_SEL' -PERFCOUNTER_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_CNTL_SEL_0', - 1: 'PERFCOUNTER_CNTL_SEL_1', - 2: 'PERFCOUNTER_CNTL_SEL_2', - 3: 'PERFCOUNTER_CNTL_SEL_3', - 4: 'PERFCOUNTER_CNTL_SEL_4', - 5: 'PERFCOUNTER_CNTL_SEL_5', - 6: 'PERFCOUNTER_CNTL_SEL_6', - 7: 'PERFCOUNTER_CNTL_SEL_7', -} -PERFCOUNTER_CNTL_SEL_0 = 0 -PERFCOUNTER_CNTL_SEL_1 = 1 -PERFCOUNTER_CNTL_SEL_2 = 2 -PERFCOUNTER_CNTL_SEL_3 = 3 -PERFCOUNTER_CNTL_SEL_4 = 4 -PERFCOUNTER_CNTL_SEL_5 = 5 -PERFCOUNTER_CNTL_SEL_6 = 6 -PERFCOUNTER_CNTL_SEL_7 = 7 -PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' -PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { - 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', - 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', -} -PERFCOUNTER_CNTOFF_START_ENABLE = 0 -PERFCOUNTER_CNTOFF_START_DISABLE = 1 -PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' -PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { - 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', -} -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 -PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CVALUE_SEL' -PERFCOUNTER_CVALUE_SEL__enumvalues = { - 0: 'PERFCOUNTER_CVALUE_SEL_47_0', - 1: 'PERFCOUNTER_CVALUE_SEL_15_0', - 2: 'PERFCOUNTER_CVALUE_SEL_31_16', - 3: 'PERFCOUNTER_CVALUE_SEL_47_32', - 4: 'PERFCOUNTER_CVALUE_SEL_11_0', - 5: 'PERFCOUNTER_CVALUE_SEL_23_12', - 6: 'PERFCOUNTER_CVALUE_SEL_35_24', - 7: 'PERFCOUNTER_CVALUE_SEL_47_36', -} -PERFCOUNTER_CVALUE_SEL_47_0 = 0 -PERFCOUNTER_CVALUE_SEL_15_0 = 1 -PERFCOUNTER_CVALUE_SEL_31_16 = 2 -PERFCOUNTER_CVALUE_SEL_47_32 = 3 -PERFCOUNTER_CVALUE_SEL_11_0 = 4 -PERFCOUNTER_CVALUE_SEL_23_12 = 5 -PERFCOUNTER_CVALUE_SEL_35_24 = 6 -PERFCOUNTER_CVALUE_SEL_47_36 = 7 -PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' -PERFCOUNTER_HW_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', - 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', -} -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 -PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' -PERFCOUNTER_HW_STOP1_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP1_0', - 1: 'PERFCOUNTER_HW_STOP1_1', -} -PERFCOUNTER_HW_STOP1_0 = 0 -PERFCOUNTER_HW_STOP1_1 = 1 -PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' -PERFCOUNTER_HW_STOP2_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP2_0', - 1: 'PERFCOUNTER_HW_STOP2_1', -} -PERFCOUNTER_HW_STOP2_0 = 0 -PERFCOUNTER_HW_STOP2_1 = 1 -PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INC_MODE' -PERFCOUNTER_INC_MODE__enumvalues = { - 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', - 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', - 2: 'PERFCOUNTER_INC_MODE_LSB', - 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', - 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', -} -PERFCOUNTER_INC_MODE_MULTI_BIT = 0 -PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 -PERFCOUNTER_INC_MODE_LSB = 2 -PERFCOUNTER_INC_MODE_POS_EDGE = 3 -PERFCOUNTER_INC_MODE_NEG_EDGE = 4 -PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_EN' -PERFCOUNTER_INT_EN__enumvalues = { - 0: 'PERFCOUNTER_INT_DISABLE', - 1: 'PERFCOUNTER_INT_ENABLE', -} -PERFCOUNTER_INT_DISABLE = 0 -PERFCOUNTER_INT_ENABLE = 1 -PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_TYPE' -PERFCOUNTER_INT_TYPE__enumvalues = { - 0: 'PERFCOUNTER_INT_TYPE_LEVEL', - 1: 'PERFCOUNTER_INT_TYPE_PULSE', -} -PERFCOUNTER_INT_TYPE_LEVEL = 0 -PERFCOUNTER_INT_TYPE_PULSE = 1 -PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_OFF_MASK' -PERFCOUNTER_OFF_MASK__enumvalues = { - 0: 'PERFCOUNTER_OFF_MASK_DISABLE', - 1: 'PERFCOUNTER_OFF_MASK_ENABLE', -} -PERFCOUNTER_OFF_MASK_DISABLE = 0 -PERFCOUNTER_OFF_MASK_ENABLE = 1 -PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RESTART_EN' -PERFCOUNTER_RESTART_EN__enumvalues = { - 0: 'PERFCOUNTER_RESTART_DISABLE', - 1: 'PERFCOUNTER_RESTART_ENABLE', -} -PERFCOUNTER_RESTART_DISABLE = 0 -PERFCOUNTER_RESTART_ENABLE = 1 -PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RUNEN_MODE' -PERFCOUNTER_RUNEN_MODE__enumvalues = { - 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', -} -PERFCOUNTER_RUNEN_MODE_LEVEL = 0 -PERFCOUNTER_RUNEN_MODE_EDGE = 1 -PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL0' -PERFCOUNTER_STATE_SEL0__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', -} -PERFCOUNTER_STATE_SEL0_GLOBAL = 0 -PERFCOUNTER_STATE_SEL0_LOCAL = 1 -PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL1' -PERFCOUNTER_STATE_SEL1__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', -} -PERFCOUNTER_STATE_SEL1_GLOBAL = 0 -PERFCOUNTER_STATE_SEL1_LOCAL = 1 -PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL2' -PERFCOUNTER_STATE_SEL2__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', -} -PERFCOUNTER_STATE_SEL2_GLOBAL = 0 -PERFCOUNTER_STATE_SEL2_LOCAL = 1 -PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL3' -PERFCOUNTER_STATE_SEL3__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', -} -PERFCOUNTER_STATE_SEL3_GLOBAL = 0 -PERFCOUNTER_STATE_SEL3_LOCAL = 1 -PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL4' -PERFCOUNTER_STATE_SEL4__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', -} -PERFCOUNTER_STATE_SEL4_GLOBAL = 0 -PERFCOUNTER_STATE_SEL4_LOCAL = 1 -PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL5' -PERFCOUNTER_STATE_SEL5__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', -} -PERFCOUNTER_STATE_SEL5_GLOBAL = 0 -PERFCOUNTER_STATE_SEL5_LOCAL = 1 -PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL6' -PERFCOUNTER_STATE_SEL6__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', -} -PERFCOUNTER_STATE_SEL6_GLOBAL = 0 -PERFCOUNTER_STATE_SEL6_LOCAL = 1 -PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL7' -PERFCOUNTER_STATE_SEL7__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', -} -PERFCOUNTER_STATE_SEL7_GLOBAL = 0 -PERFCOUNTER_STATE_SEL7_LOCAL = 1 -PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_AND_OR' -PERFMON_CNTOFF_AND_OR__enumvalues = { - 0: 'PERFMON_CNTOFF_OR', - 1: 'PERFMON_CNTOFF_AND', -} -PERFMON_CNTOFF_OR = 0 -PERFMON_CNTOFF_AND = 1 -PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_EN' -PERFMON_CNTOFF_INT_EN__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_DISABLE', - 1: 'PERFMON_CNTOFF_INT_ENABLE', -} -PERFMON_CNTOFF_INT_DISABLE = 0 -PERFMON_CNTOFF_INT_ENABLE = 1 -PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' -PERFMON_CNTOFF_INT_TYPE__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', - 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', -} -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 -PERFMON_CNTOFF_INT_TYPE_PULSE = 1 -PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_STATE' -PERFMON_STATE__enumvalues = { - 0: 'PERFMON_STATE_RESET', - 1: 'PERFMON_STATE_START', - 2: 'PERFMON_STATE_FREEZE', - 3: 'PERFMON_STATE_HW', -} -PERFMON_STATE_RESET = 0 -PERFMON_STATE_START = 1 -PERFMON_STATE_FREEZE = 2 -PERFMON_STATE_HW = 3 -PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'BIGK_FRAGMENT_SIZE' -BIGK_FRAGMENT_SIZE__enumvalues = { - 0: 'VM_PG_SIZE_4KB', - 1: 'VM_PG_SIZE_8KB', - 2: 'VM_PG_SIZE_16KB', - 3: 'VM_PG_SIZE_32KB', - 4: 'VM_PG_SIZE_64KB', - 5: 'VM_PG_SIZE_128KB', - 6: 'VM_PG_SIZE_256KB', - 7: 'VM_PG_SIZE_512KB', - 8: 'VM_PG_SIZE_1024KB', - 9: 'VM_PG_SIZE_2048KB', -} -VM_PG_SIZE_4KB = 0 -VM_PG_SIZE_8KB = 1 -VM_PG_SIZE_16KB = 2 -VM_PG_SIZE_32KB = 3 -VM_PG_SIZE_64KB = 4 -VM_PG_SIZE_128KB = 5 -VM_PG_SIZE_256KB = 6 -VM_PG_SIZE_512KB = 7 -VM_PG_SIZE_1024KB = 8 -VM_PG_SIZE_2048KB = 9 -BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CHUNK_SIZE' -CHUNK_SIZE__enumvalues = { - 0: 'CHUNK_SIZE_1KB', - 1: 'CHUNK_SIZE_2KB', - 2: 'CHUNK_SIZE_4KB', - 3: 'CHUNK_SIZE_8KB', - 4: 'CHUNK_SIZE_16KB', - 5: 'CHUNK_SIZE_32KB', - 6: 'CHUNK_SIZE_64KB', -} -CHUNK_SIZE_1KB = 0 -CHUNK_SIZE_2KB = 1 -CHUNK_SIZE_4KB = 2 -CHUNK_SIZE_8KB = 3 -CHUNK_SIZE_16KB = 4 -CHUNK_SIZE_32KB = 5 -CHUNK_SIZE_64KB = 6 -CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'COMPAT_LEVEL' -COMPAT_LEVEL__enumvalues = { - 0: 'ADDR_GEN_ZERO', - 1: 'ADDR_GEN_ONE', - 2: 'ADDR_GEN_TWO', - 3: 'ADDR_RESERVED', -} -ADDR_GEN_ZERO = 0 -ADDR_GEN_ONE = 1 -ADDR_GEN_TWO = 2 -ADDR_RESERVED = 3 -COMPAT_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPTE_GROUP_SIZE' -DPTE_GROUP_SIZE__enumvalues = { - 0: 'DPTE_GROUP_SIZE_64B', - 1: 'DPTE_GROUP_SIZE_128B', - 2: 'DPTE_GROUP_SIZE_256B', - 3: 'DPTE_GROUP_SIZE_512B', - 4: 'DPTE_GROUP_SIZE_1024B', - 5: 'DPTE_GROUP_SIZE_2048B', -} -DPTE_GROUP_SIZE_64B = 0 -DPTE_GROUP_SIZE_128B = 1 -DPTE_GROUP_SIZE_256B = 2 -DPTE_GROUP_SIZE_512B = 3 -DPTE_GROUP_SIZE_1024B = 4 -DPTE_GROUP_SIZE_2048B = 5 -DPTE_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' -FORCE_ONE_ROW_FOR_FRAME__enumvalues = { - 0: 'FORCE_ONE_ROW_FOR_FRAME_0', - 1: 'FORCE_ONE_ROW_FOR_FRAME_1', -} -FORCE_ONE_ROW_FOR_FRAME_0 = 0 -FORCE_ONE_ROW_FOR_FRAME_1 = 1 -FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_BLANK_EN' -HUBP_BLANK_EN__enumvalues = { - 0: 'HUBP_BLANK_SW_DEASSERT', - 1: 'HUBP_BLANK_SW_ASSERT', -} -HUBP_BLANK_SW_DEASSERT = 0 -HUBP_BLANK_SW_ASSERT = 1 -HUBP_BLANK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_IN_BLANK' -HUBP_IN_BLANK__enumvalues = { - 0: 'HUBP_IN_ACTIVE', - 1: 'HUBP_IN_VBLANK', -} -HUBP_IN_ACTIVE = 0 -HUBP_IN_VBLANK = 1 -HUBP_IN_BLANK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' -HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { - 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', -} -HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 -HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 -HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 -HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 -HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' -HUBP_NO_OUTSTANDING_REQ__enumvalues = { - 0: 'OUTSTANDING_REQ', - 1: 'NO_OUTSTANDING_REQ', -} -OUTSTANDING_REQ = 0 -NO_OUTSTANDING_REQ = 1 -HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_SOFT_RESET' -HUBP_SOFT_RESET__enumvalues = { - 0: 'HUBP_SOFT_RESET_ON', - 1: 'HUBP_SOFT_RESET_OFF', -} -HUBP_SOFT_RESET_ON = 0 -HUBP_SOFT_RESET_OFF = 1 -HUBP_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_TTU_DISABLE' -HUBP_TTU_DISABLE__enumvalues = { - 0: 'HUBP_TTU_ENABLED', - 1: 'HUBP_TTU_DISABLED', -} -HUBP_TTU_ENABLED = 0 -HUBP_TTU_DISABLED = 1 -HUBP_TTU_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' -HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { - 0: 'VREADY_BEFORE_VSYNC', - 1: 'VREADY_AT_OR_AFTER_VSYNC', -} -VREADY_BEFORE_VSYNC = 0 -VREADY_AT_OR_AFTER_VSYNC = 1 -HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VTG_SEL' -HUBP_VTG_SEL__enumvalues = { - 0: 'VTG_SEL_0', - 1: 'VTG_SEL_1', - 2: 'VTG_SEL_2', - 3: 'VTG_SEL_3', - 4: 'VTG_SEL_4', - 5: 'VTG_SEL_5', -} -VTG_SEL_0 = 0 -VTG_SEL_1 = 1 -VTG_SEL_2 = 2 -VTG_SEL_3 = 3 -VTG_SEL_4 = 4 -VTG_SEL_5 = 5 -HUBP_VTG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'H_MIRROR_EN' -H_MIRROR_EN__enumvalues = { - 0: 'HW_MIRRORING_DISABLE', - 1: 'HW_MIRRORING_ENABLE', -} -HW_MIRRORING_DISABLE = 0 -HW_MIRRORING_ENABLE = 1 -H_MIRROR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LEGACY_PIPE_INTERLEAVE' -LEGACY_PIPE_INTERLEAVE__enumvalues = { - 0: 'LEGACY_PIPE_INTERLEAVE_256B', - 1: 'LEGACY_PIPE_INTERLEAVE_512B', -} -LEGACY_PIPE_INTERLEAVE_256B = 0 -LEGACY_PIPE_INTERLEAVE_512B = 1 -LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum - -# values for enumeration 'META_CHUNK_SIZE' -META_CHUNK_SIZE__enumvalues = { - 0: 'META_CHUNK_SIZE_1KB', - 1: 'META_CHUNK_SIZE_2KB', - 2: 'META_CHUNK_SIZE_4KB', - 3: 'META_CHUNK_SIZE_8KB', -} -META_CHUNK_SIZE_1KB = 0 -META_CHUNK_SIZE_2KB = 1 -META_CHUNK_SIZE_4KB = 2 -META_CHUNK_SIZE_8KB = 3 -META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'META_LINEAR' -META_LINEAR__enumvalues = { - 0: 'META_SURF_TILED', - 1: 'META_SURF_LINEAR', -} -META_SURF_TILED = 0 -META_SURF_LINEAR = 1 -META_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_CHUNK_SIZE' -MIN_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_CHUNK_SIZE', - 1: 'MIN_CHUNK_SIZE_256B', - 2: 'MIN_CHUNK_SIZE_512B', - 3: 'MIN_CHUNK_SIZE_1024B', -} -NO_MIN_CHUNK_SIZE = 0 -MIN_CHUNK_SIZE_256B = 1 -MIN_CHUNK_SIZE_512B = 2 -MIN_CHUNK_SIZE_1024B = 3 -MIN_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_META_CHUNK_SIZE' -MIN_META_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_META_CHUNK_SIZE', - 1: 'MIN_META_CHUNK_SIZE_64B', - 2: 'MIN_META_CHUNK_SIZE_128B', - 3: 'MIN_META_CHUNK_SIZE_256B', -} -NO_MIN_META_CHUNK_SIZE = 0 -MIN_META_CHUNK_SIZE_64B = 1 -MIN_META_CHUNK_SIZE_128B = 2 -MIN_META_CHUNK_SIZE_256B = 3 -MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_ALIGNED' -PIPE_ALIGNED__enumvalues = { - 0: 'PIPE_UNALIGNED_SURF', - 1: 'PIPE_ALIGNED_SURF', -} -PIPE_UNALIGNED_SURF = 0 -PIPE_ALIGNED_SURF = 1 -PIPE_ALIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_BUFFER_MODE' -PTE_BUFFER_MODE__enumvalues = { - 0: 'PTE_BUFFER_MODE_0', - 1: 'PTE_BUFFER_MODE_1', -} -PTE_BUFFER_MODE_0 = 0 -PTE_BUFFER_MODE_1 = 1 -PTE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' -PTE_ROW_HEIGHT_LINEAR__enumvalues = { - 0: 'PTE_ROW_HEIGHT_LINEAR_8L', - 1: 'PTE_ROW_HEIGHT_LINEAR_16L', - 2: 'PTE_ROW_HEIGHT_LINEAR_32L', - 3: 'PTE_ROW_HEIGHT_LINEAR_64L', - 4: 'PTE_ROW_HEIGHT_LINEAR_128L', - 5: 'PTE_ROW_HEIGHT_LINEAR_256L', - 6: 'PTE_ROW_HEIGHT_LINEAR_512L', - 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', -} -PTE_ROW_HEIGHT_LINEAR_8L = 0 -PTE_ROW_HEIGHT_LINEAR_16L = 1 -PTE_ROW_HEIGHT_LINEAR_32L = 2 -PTE_ROW_HEIGHT_LINEAR_64L = 3 -PTE_ROW_HEIGHT_LINEAR_128L = 4 -PTE_ROW_HEIGHT_LINEAR_256L = 5 -PTE_ROW_HEIGHT_LINEAR_512L = 6 -PTE_ROW_HEIGHT_LINEAR_1024L = 7 -PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'ROTATION_ANGLE' -ROTATION_ANGLE__enumvalues = { - 0: 'ROTATE_0_DEGREES', - 1: 'ROTATE_90_DEGREES', - 2: 'ROTATE_180_DEGREES', - 3: 'ROTATE_270_DEGREES', -} -ROTATE_0_DEGREES = 0 -ROTATE_90_DEGREES = 1 -ROTATE_180_DEGREES = 2 -ROTATE_270_DEGREES = 3 -ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'SWATH_HEIGHT' -SWATH_HEIGHT__enumvalues = { - 0: 'SWATH_HEIGHT_1L', - 1: 'SWATH_HEIGHT_2L', - 2: 'SWATH_HEIGHT_4L', - 3: 'SWATH_HEIGHT_8L', - 4: 'SWATH_HEIGHT_16L', -} -SWATH_HEIGHT_1L = 0 -SWATH_HEIGHT_2L = 1 -SWATH_HEIGHT_4L = 2 -SWATH_HEIGHT_8L = 3 -SWATH_HEIGHT_16L = 4 -SWATH_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_CURSOR' -USE_MALL_FOR_CURSOR__enumvalues = { - 0: 'USE_MALL_FOR_CURSOR_0', - 1: 'USE_MALL_FOR_CURSOR_1', -} -USE_MALL_FOR_CURSOR_0 = 0 -USE_MALL_FOR_CURSOR_1 = 1 -USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE' -USE_MALL_FOR_PSTATE_CHANGE__enumvalues = { - 0: 'USE_MALL_FOR_PSTATE_CHANGE_0', - 1: 'USE_MALL_FOR_PSTATE_CHANGE_1', -} -USE_MALL_FOR_PSTATE_CHANGE_0 = 0 -USE_MALL_FOR_PSTATE_CHANGE_1 = 1 -USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN' -USE_MALL_FOR_STATIC_SCREEN__enumvalues = { - 0: 'USE_MALL_FOR_STATIC_SCREEN_0', - 1: 'USE_MALL_FOR_STATIC_SCREEN_1', -} -USE_MALL_FOR_STATIC_SCREEN_0 = 0 -USE_MALL_FOR_STATIC_SCREEN_1 = 1 -USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum - -# values for enumeration 'VMPG_SIZE' -VMPG_SIZE__enumvalues = { - 0: 'VMPG_SIZE_4KB', - 1: 'VMPG_SIZE_64KB', -} -VMPG_SIZE_4KB = 0 -VMPG_SIZE_64KB = 1 -VMPG_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VM_GROUP_SIZE' -VM_GROUP_SIZE__enumvalues = { - 0: 'VM_GROUP_SIZE_64B', - 1: 'VM_GROUP_SIZE_128B', - 2: 'VM_GROUP_SIZE_256B', - 3: 'VM_GROUP_SIZE_512B', - 4: 'VM_GROUP_SIZE_1024B', - 5: 'VM_GROUP_SIZE_2048B', -} -VM_GROUP_SIZE_64B = 0 -VM_GROUP_SIZE_128B = 1 -VM_GROUP_SIZE_256B = 2 -VM_GROUP_SIZE_512B = 3 -VM_GROUP_SIZE_1024B = 4 -VM_GROUP_SIZE_2048B = 5 -VM_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_MIN_FREE_ENTRIES' -DFQ_MIN_FREE_ENTRIES__enumvalues = { - 0: 'DFQ_MIN_FREE_ENTRIES_0', - 1: 'DFQ_MIN_FREE_ENTRIES_1', - 2: 'DFQ_MIN_FREE_ENTRIES_2', - 3: 'DFQ_MIN_FREE_ENTRIES_3', - 4: 'DFQ_MIN_FREE_ENTRIES_4', - 5: 'DFQ_MIN_FREE_ENTRIES_5', - 6: 'DFQ_MIN_FREE_ENTRIES_6', - 7: 'DFQ_MIN_FREE_ENTRIES_7', -} -DFQ_MIN_FREE_ENTRIES_0 = 0 -DFQ_MIN_FREE_ENTRIES_1 = 1 -DFQ_MIN_FREE_ENTRIES_2 = 2 -DFQ_MIN_FREE_ENTRIES_3 = 3 -DFQ_MIN_FREE_ENTRIES_4 = 4 -DFQ_MIN_FREE_ENTRIES_5 = 5 -DFQ_MIN_FREE_ENTRIES_6 = 6 -DFQ_MIN_FREE_ENTRIES_7 = 7 -DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_NUM_ENTRIES' -DFQ_NUM_ENTRIES__enumvalues = { - 0: 'DFQ_NUM_ENTRIES_0', - 1: 'DFQ_NUM_ENTRIES_1', - 2: 'DFQ_NUM_ENTRIES_2', - 3: 'DFQ_NUM_ENTRIES_3', - 4: 'DFQ_NUM_ENTRIES_4', - 5: 'DFQ_NUM_ENTRIES_5', - 6: 'DFQ_NUM_ENTRIES_6', - 7: 'DFQ_NUM_ENTRIES_7', - 8: 'DFQ_NUM_ENTRIES_8', -} -DFQ_NUM_ENTRIES_0 = 0 -DFQ_NUM_ENTRIES_1 = 1 -DFQ_NUM_ENTRIES_2 = 2 -DFQ_NUM_ENTRIES_3 = 3 -DFQ_NUM_ENTRIES_4 = 4 -DFQ_NUM_ENTRIES_5 = 5 -DFQ_NUM_ENTRIES_6 = 6 -DFQ_NUM_ENTRIES_7 = 7 -DFQ_NUM_ENTRIES_8 = 8 -DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_SIZE' -DFQ_SIZE__enumvalues = { - 0: 'DFQ_SIZE_0', - 1: 'DFQ_SIZE_1', - 2: 'DFQ_SIZE_2', - 3: 'DFQ_SIZE_3', - 4: 'DFQ_SIZE_4', - 5: 'DFQ_SIZE_5', - 6: 'DFQ_SIZE_6', - 7: 'DFQ_SIZE_7', -} -DFQ_SIZE_0 = 0 -DFQ_SIZE_1 = 1 -DFQ_SIZE_2 = 2 -DFQ_SIZE_3 = 3 -DFQ_SIZE_4 = 4 -DFQ_SIZE_5 = 5 -DFQ_SIZE_6 = 6 -DFQ_SIZE_7 = 7 -DFQ_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_VM_DONE' -DMDATA_VM_DONE__enumvalues = { - 0: 'DMDATA_VM_IS_NOT_DONE', - 1: 'DMDATA_VM_IS_DONE', -} -DMDATA_VM_IS_NOT_DONE = 0 -DMDATA_VM_IS_DONE = 1 -DMDATA_VM_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'EXPANSION_MODE' -EXPANSION_MODE__enumvalues = { - 0: 'EXPANSION_MODE_ZERO', - 1: 'EXPANSION_MODE_CONSERVATIVE', - 2: 'EXPANSION_MODE_OPTIMAL', -} -EXPANSION_MODE_ZERO = 0 -EXPANSION_MODE_CONSERVATIVE = 1 -EXPANSION_MODE_OPTIMAL = 2 -EXPANSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FLIP_RATE' -FLIP_RATE__enumvalues = { - 0: 'FLIP_RATE_0', - 1: 'FLIP_RATE_1', - 2: 'FLIP_RATE_2', - 3: 'FLIP_RATE_3', - 4: 'FLIP_RATE_4', - 5: 'FLIP_RATE_5', - 6: 'FLIP_RATE_6', - 7: 'FLIP_RATE_7', -} -FLIP_RATE_0 = 0 -FLIP_RATE_1 = 1 -FLIP_RATE_2 = 2 -FLIP_RATE_3 = 3 -FLIP_RATE_4 = 4 -FLIP_RATE_5 = 5 -FLIP_RATE_6 = 6 -FLIP_RATE_7 = 7 -FLIP_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'INT_MASK' -INT_MASK__enumvalues = { - 0: 'INT_DISABLED', - 1: 'INT_ENABLED', -} -INT_DISABLED = 0 -INT_ENABLED = 1 -INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_IN_FLUSH_URGENT' -PIPE_IN_FLUSH_URGENT__enumvalues = { - 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', - 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', -} -PIPE_IN_FLUSH_URGENT_ENABLE = 0 -PIPE_IN_FLUSH_URGENT_DISABLE = 1 -PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' -PRQ_MRQ_FLUSH_URGENT__enumvalues = { - 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', - 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', -} -PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 -PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 -PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'ROW_TTU_MODE' -ROW_TTU_MODE__enumvalues = { - 0: 'END_OF_ROW_MODE', - 1: 'WATERMARK_MODE', -} -END_OF_ROW_MODE = 0 -WATERMARK_MODE = 1 -ROW_TTU_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC' -SURFACE_DCC__enumvalues = { - 0: 'SURFACE_IS_NOT_DCC', - 1: 'SURFACE_IS_DCC', -} -SURFACE_IS_NOT_DCC = 0 -SURFACE_IS_DCC = 1 -SURFACE_DCC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_128B' -SURFACE_DCC_IND_128B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_128B', - 1: 'SURFACE_DCC_IS_IND_128B', -} -SURFACE_DCC_IS_NOT_IND_128B = 0 -SURFACE_DCC_IS_IND_128B = 1 -SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_64B' -SURFACE_DCC_IND_64B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_64B', - 1: 'SURFACE_DCC_IS_IND_64B', -} -SURFACE_DCC_IS_NOT_IND_64B = 0 -SURFACE_DCC_IS_IND_64B = 1 -SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_BLK' -SURFACE_DCC_IND_BLK__enumvalues = { - 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', - 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', - 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', - 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', -} -SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 -SURFACE_DCC_BLOCK_IS_IND_64B = 1 -SURFACE_DCC_BLOCK_IS_IND_128B = 2 -SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 -SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' -SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', - 1: 'SURFACE_FLIP_AWAY_INT_PULSE', -} -SURFACE_FLIP_AWAY_INT_LEVEL = 0 -SURFACE_FLIP_AWAY_INT_PULSE = 1 -SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' -SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { - 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', - 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', -} -SURFACE_FLIP_EXEC_NORMAL_MODE = 0 -SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 -SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_INT_TYPE' -SURFACE_FLIP_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_INT_LEVEL', - 1: 'SURFACE_FLIP_INT_PULSE', -} -SURFACE_FLIP_INT_LEVEL = 0 -SURFACE_FLIP_INT_PULSE = 1 -SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' -SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { - 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', -} -SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 -SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 -SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' -SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { - 0: 'FLIP_ANY_FRAME', - 1: 'FLIP_LEFT_EYE', - 2: 'FLIP_RIGHT_EYE', - 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', -} -FLIP_ANY_FRAME = 0 -FLIP_LEFT_EYE = 1 -FLIP_RIGHT_EYE = 2 -SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 -SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' -SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', -} -SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 -SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 -SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' -SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', -} -SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 -SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 -SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_TYPE' -SURFACE_FLIP_TYPE__enumvalues = { - 0: 'SURFACE_V_FLIP', - 1: 'SURFACE_I_FLIP', -} -SURFACE_V_FLIP = 0 -SURFACE_I_FLIP = 1 -SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' -SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { - 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', - 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', -} -SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 -SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 -SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 -SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 -SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 -SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 -SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 -SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 -SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 -SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 -SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 -SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 -SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 -SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 -SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 -SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 -SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' -SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { - 0: 'SURFACE_INUSE_IS_LATCHED', - 1: 'SURFACE_INUSE_IS_NOT_LATCHED', -} -SURFACE_INUSE_IS_LATCHED = 0 -SURFACE_INUSE_IS_NOT_LATCHED = 1 -SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_TMZ' -SURFACE_TMZ__enumvalues = { - 0: 'SURFACE_IS_NOT_TMZ', - 1: 'SURFACE_IS_TMZ', -} -SURFACE_IS_NOT_TMZ = 0 -SURFACE_IS_TMZ = 1 -SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_UPDATE_LOCK' -SURFACE_UPDATE_LOCK__enumvalues = { - 0: 'SURFACE_UPDATE_IS_UNLOCKED', - 1: 'SURFACE_UPDATE_IS_LOCKED', -} -SURFACE_UPDATE_IS_UNLOCKED = 0 -SURFACE_UPDATE_IS_LOCKED = 1 -SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_ALPHA' -CROSSBAR_FOR_ALPHA__enumvalues = { - 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', - 1: 'Y_G_DATA_ONTO_ALPHA_PORT', - 2: 'CB_B_DATA_ONTO_ALPHA_PORT', - 3: 'CR_R_DATA_ONTO_ALPHA_PORT', -} -ALPHA_DATA_ONTO_ALPHA_PORT = 0 -Y_G_DATA_ONTO_ALPHA_PORT = 1 -CB_B_DATA_ONTO_ALPHA_PORT = 2 -CR_R_DATA_ONTO_ALPHA_PORT = 3 -CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CB_B' -CROSSBAR_FOR_CB_B__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CB_B_PORT', - 1: 'Y_G_DATA_ONTO_CB_B_PORT', - 2: 'CB_B_DATA_ONTO_CB_B_PORT', - 3: 'CR_R_DATA_ONTO_CB_B_PORT', -} -ALPHA_DATA_ONTO_CB_B_PORT = 0 -Y_G_DATA_ONTO_CB_B_PORT = 1 -CB_B_DATA_ONTO_CB_B_PORT = 2 -CR_R_DATA_ONTO_CB_B_PORT = 3 -CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CR_R' -CROSSBAR_FOR_CR_R__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CR_R_PORT', - 1: 'Y_G_DATA_ONTO_CR_R_PORT', - 2: 'CB_B_DATA_ONTO_CR_R_PORT', - 3: 'CR_R_DATA_ONTO_CR_R_PORT', -} -ALPHA_DATA_ONTO_CR_R_PORT = 0 -Y_G_DATA_ONTO_CR_R_PORT = 1 -CB_B_DATA_ONTO_CR_R_PORT = 2 -CR_R_DATA_ONTO_CR_R_PORT = 3 -CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_Y_G' -CROSSBAR_FOR_Y_G__enumvalues = { - 0: 'ALPHA_DATA_ONTO_Y_G_PORT', - 1: 'Y_G_DATA_ONTO_Y_G_PORT', - 2: 'CB_B_DATA_ONTO_Y_G_PORT', - 3: 'CR_R_DATA_ONTO_Y_G_PORT', -} -ALPHA_DATA_ONTO_Y_G_PORT = 0 -Y_G_DATA_ONTO_Y_G_PORT = 1 -CB_B_DATA_ONTO_Y_G_PORT = 2 -CR_R_DATA_ONTO_Y_G_PORT = 3 -CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum - -# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' -DETILE_BUFFER_PACKER_ENABLE__enumvalues = { - 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', - 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', -} -DETILE_BUFFER_PACKER_IS_DISABLE = 0 -DETILE_BUFFER_PACKER_IS_ENABLE = 1 -DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_MODE' -MEM_PWR_DIS_MODE__enumvalues = { - 0: 'MEM_POWER_DIS_MODE_ENABLE', - 1: 'MEM_POWER_DIS_MODE_DISABLE', -} -MEM_POWER_DIS_MODE_ENABLE = 0 -MEM_POWER_DIS_MODE_DISABLE = 1 -MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_MODE' -MEM_PWR_FORCE_MODE__enumvalues = { - 0: 'MEM_POWER_FORCE_MODE_OFF', - 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', - 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', -} -MEM_POWER_FORCE_MODE_OFF = 0 -MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 -MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 -MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 -MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_STATUS' -MEM_PWR_STATUS__enumvalues = { - 0: 'MEM_POWER_STATUS_ON', - 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', - 2: 'MEM_POWER_STATUS_DEEP_SLEEP', - 3: 'MEM_POWER_STATUS_SHUT_DOWN', -} -MEM_POWER_STATUS_ON = 0 -MEM_POWER_STATUS_LIGHT_SLEEP = 1 -MEM_POWER_STATUS_DEEP_SLEEP = 2 -MEM_POWER_STATUS_SHUT_DOWN = 3 -MEM_PWR_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_MASK_MODE' -PIPE_INT_MASK_MODE__enumvalues = { - 0: 'PIPE_INT_MASK_MODE_DISABLE', - 1: 'PIPE_INT_MASK_MODE_ENABLE', -} -PIPE_INT_MASK_MODE_DISABLE = 0 -PIPE_INT_MASK_MODE_ENABLE = 1 -PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_TYPE_MODE' -PIPE_INT_TYPE_MODE__enumvalues = { - 0: 'PIPE_INT_TYPE_MODE_DISABLE', - 1: 'PIPE_INT_TYPE_MODE_ENABLE', -} -PIPE_INT_TYPE_MODE_DISABLE = 0 -PIPE_INT_TYPE_MODE_ENABLE = 1 -PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', -} -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' -CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_2X_MAGNIFY' -CURSOR_2X_MAGNIFY__enumvalues = { - 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', - 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', -} -CURSOR_2X_MAGNIFY_IS_DISABLE = 0 -CURSOR_2X_MAGNIFY_IS_ENABLE = 1 -CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_ENABLE' -CURSOR_ENABLE__enumvalues = { - 0: 'CURSOR_IS_DISABLE', - 1: 'CURSOR_IS_ENABLE', -} -CURSOR_IS_DISABLE = 0 -CURSOR_IS_ENABLE = 1 -CURSOR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_LINES_PER_CHUNK' -CURSOR_LINES_PER_CHUNK__enumvalues = { - 0: 'CURSOR_LINE_PER_CHUNK_1', - 1: 'CURSOR_LINE_PER_CHUNK_2', - 2: 'CURSOR_LINE_PER_CHUNK_4', - 3: 'CURSOR_LINE_PER_CHUNK_8', - 4: 'CURSOR_LINE_PER_CHUNK_16', -} -CURSOR_LINE_PER_CHUNK_1 = 0 -CURSOR_LINE_PER_CHUNK_2 = 1 -CURSOR_LINE_PER_CHUNK_4 = 2 -CURSOR_LINE_PER_CHUNK_8 = 3 -CURSOR_LINE_PER_CHUNK_16 = 4 -CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_MODE' -CURSOR_MODE__enumvalues = { - 0: 'CURSOR_MONO_2BIT', - 1: 'CURSOR_COLOR_24BIT_1BIT_AND', - 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', - 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', -} -CURSOR_MONO_2BIT = 0 -CURSOR_COLOR_24BIT_1BIT_AND = 1 -CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -CURSOR_COLOR_64BIT_FP_PREMULT = 4 -CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 -CURSOR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' -CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', -} -CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 -CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 -CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' -CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', -} -CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 -CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 -CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PITCH' -CURSOR_PITCH__enumvalues = { - 0: 'CURSOR_PITCH_64_PIXELS', - 1: 'CURSOR_PITCH_128_PIXELS', - 2: 'CURSOR_PITCH_256_PIXELS', -} -CURSOR_PITCH_64_PIXELS = 0 -CURSOR_PITCH_128_PIXELS = 1 -CURSOR_PITCH_256_PIXELS = 2 -CURSOR_PITCH = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_REQ_MODE' -CURSOR_REQ_MODE__enumvalues = { - 0: 'CURSOR_REQUEST_NORMALLY', - 1: 'CURSOR_REQUEST_EARLY', -} -CURSOR_REQUEST_NORMALLY = 0 -CURSOR_REQUEST_EARLY = 1 -CURSOR_REQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SNOOP' -CURSOR_SNOOP__enumvalues = { - 0: 'CURSOR_IS_NOT_SNOOP', - 1: 'CURSOR_IS_SNOOP', -} -CURSOR_IS_NOT_SNOOP = 0 -CURSOR_IS_SNOOP = 1 -CURSOR_SNOOP = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_STEREO_EN' -CURSOR_STEREO_EN__enumvalues = { - 0: 'CURSOR_STEREO_IS_DISABLED', - 1: 'CURSOR_STEREO_IS_ENABLED', -} -CURSOR_STEREO_IS_DISABLED = 0 -CURSOR_STEREO_IS_ENABLED = 1 -CURSOR_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SURFACE_TMZ' -CURSOR_SURFACE_TMZ__enumvalues = { - 0: 'CURSOR_SURFACE_IS_NOT_TMZ', - 1: 'CURSOR_SURFACE_IS_TMZ', -} -CURSOR_SURFACE_IS_NOT_TMZ = 0 -CURSOR_SURFACE_IS_TMZ = 1 -CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SYSTEM' -CURSOR_SYSTEM__enumvalues = { - 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', - 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', -} -CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 -CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 -CURSOR_SYSTEM = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { - 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', -} -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_DONE' -DMDATA_DONE__enumvalues = { - 0: 'DMDATA_NOT_SENT_TO_DIG', - 1: 'DMDATA_SENT_TO_DIG', -} -DMDATA_NOT_SENT_TO_DIG = 0 -DMDATA_SENT_TO_DIG = 1 -DMDATA_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_MODE' -DMDATA_MODE__enumvalues = { - 0: 'DMDATA_SOFTWARE_UPDATE_MODE', - 1: 'DMDATA_HARDWARE_UPDATE_MODE', -} -DMDATA_SOFTWARE_UPDATE_MODE = 0 -DMDATA_HARDWARE_UPDATE_MODE = 1 -DMDATA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_QOS_MODE' -DMDATA_QOS_MODE__enumvalues = { - 0: 'DMDATA_QOS_LEVEL_FROM_TTU', - 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', -} -DMDATA_QOS_LEVEL_FROM_TTU = 0 -DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 -DMDATA_QOS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_REPEAT' -DMDATA_REPEAT__enumvalues = { - 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', - 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', -} -DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 -DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 -DMDATA_REPEAT = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW' -DMDATA_UNDERFLOW__enumvalues = { - 0: 'DMDATA_NOT_UNDERFLOW', - 1: 'DMDATA_UNDERFLOWED', -} -DMDATA_NOT_UNDERFLOW = 0 -DMDATA_UNDERFLOWED = 1 -DMDATA_UNDERFLOW = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' -DMDATA_UNDERFLOW_CLEAR__enumvalues = { - 0: 'DMDATA_DONT_CLEAR', - 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', -} -DMDATA_DONT_CLEAR = 0 -DMDATA_CLEAR_UNDERFLOW_STATUS = 1 -DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UPDATED' -DMDATA_UPDATED__enumvalues = { - 0: 'DMDATA_NOT_UPDATED', - 1: 'DMDATA_WAS_UPDATED', -} -DMDATA_NOT_UPDATED = 0 -DMDATA_WAS_UPDATED = 1 -DMDATA_UPDATED = ctypes.c_uint32 # enum - -# values for enumeration 'RESPONSE_STATUS' -RESPONSE_STATUS__enumvalues = { - 0: 'OKAY', - 1: 'EXOKAY', - 2: 'SLVERR', - 3: 'DECERR', - 4: 'EARLY', - 5: 'OKAY_NODATA', - 6: 'PROTVIOL', - 7: 'TRANSERR', - 8: 'CMPTO', - 12: 'CRS', -} -OKAY = 0 -EXOKAY = 1 -SLVERR = 2 -DECERR = 3 -EARLY = 4 -OKAY_NODATA = 5 -PROTVIOL = 6 -TRANSERR = 7 -CMPTO = 8 -CRS = 12 -RESPONSE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' -DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', -} -DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 -DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 -DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' -DCHUBBUB_MEM_PWR_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', - 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', -} -DCHUBBUB_MEM_POWER_MODE_OFF = 0 -DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 -DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 -DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 -DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' -MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' -MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { - 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', - 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', - 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', -} -MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 -MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 -MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 -MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 -MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' -MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { - 0: 'MPC_CRC_INTERLACE_MODE_TOP', - 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', - 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', -} -MPC_CRC_INTERLACE_MODE_TOP = 0 -MPC_CRC_INTERLACE_MODE_BOTTOM = 1 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_MODE' -MPC_CRC_CALC_MODE__enumvalues = { - 0: 'MPC_CRC_ONE_SHOT_MODE', - 1: 'MPC_CRC_CONTINUOUS_MODE', -} -MPC_CRC_ONE_SHOT_MODE = 0 -MPC_CRC_CONTINUOUS_MODE = 1 -MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' -MPC_CRC_CALC_STEREO_MODE__enumvalues = { - 0: 'MPC_CRC_STEREO_MODE_LEFT', - 1: 'MPC_CRC_STEREO_MODE_RIGHT', - 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', -} -MPC_CRC_STEREO_MODE_LEFT = 0 -MPC_CRC_STEREO_MODE_RIGHT = 1 -MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 -MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_SOURCE_SELECT' -MPC_CRC_SOURCE_SELECT__enumvalues = { - 0: 'MPC_CRC_SOURCE_SEL_DPP', - 1: 'MPC_CRC_SOURCE_SEL_OPP', - 2: 'MPC_CRC_SOURCE_SEL_DWB', - 3: 'MPC_CRC_SOURCE_SEL_OTHER', -} -MPC_CRC_SOURCE_SEL_DPP = 0 -MPC_CRC_SOURCE_SEL_OPP = 1 -MPC_CRC_SOURCE_SEL_DWB = 2 -MPC_CRC_SOURCE_SEL_OTHER = 3 -MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT' -MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', - 1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', - 2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', - 3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', -} -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3 -MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT' -MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', - 1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', - 2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', - 3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES', -} -MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0 -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1 -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2 -MPC_DEBUG_BUS2_DATA_SELECT_RES = 3 -MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT' -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', - 1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', - 2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', - 3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', - 4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', - 5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', - 6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', - 7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', -} -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT' -MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS_MPCC_BYTE0', - 1: 'MPC_DEBUG_BUS_MPCC_BYTE1', - 2: 'MPC_DEBUG_BUS_MPCC_BYTE2', - 3: 'MPC_DEBUG_BUS_MPCC_BYTE3', -} -MPC_DEBUG_BUS_MPCC_BYTE0 = 0 -MPC_DEBUG_BUS_MPCC_BYTE1 = 1 -MPC_DEBUG_BUS_MPCC_BYTE2 = 2 -MPC_DEBUG_BUS_MPCC_BYTE3 = 3 -MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_COEF_FORMAT' -MPC_OCSC_COEF_FORMAT__enumvalues = { - 0: 'MPC_OCSC_COEF_FORMAT_S2_13', - 1: 'MPC_OCSC_COEF_FORMAT_S3_12', -} -MPC_OCSC_COEF_FORMAT_S2_13 = 0 -MPC_OCSC_COEF_FORMAT_S3_12 = 1 -MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_CSC_MODE' -MPC_OUT_CSC_MODE__enumvalues = { - 0: 'MPC_OUT_CSC_MODE_0', - 1: 'MPC_OUT_CSC_MODE_1', - 2: 'MPC_OUT_CSC_MODE_2', - 3: 'MPC_OUT_CSC_MODE_RSV', -} -MPC_OUT_CSC_MODE_0 = 0 -MPC_OUT_CSC_MODE_1 = 1 -MPC_OUT_CSC_MODE_2 = 2 -MPC_OUT_CSC_MODE_RSV = 3 -MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { - 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', -} -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' -MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { - 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', -} -MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 -MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 -MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_BG_COLOR_BPC' -MPCC_BG_COLOR_BPC__enumvalues = { - 0: 'MPCC_BG_COLOR_BPC_8bit', - 1: 'MPCC_BG_COLOR_BPC_9bit', - 2: 'MPCC_BG_COLOR_BPC_10bit', - 3: 'MPCC_BG_COLOR_BPC_11bit', - 4: 'MPCC_BG_COLOR_BPC_12bit', -} -MPCC_BG_COLOR_BPC_8bit = 0 -MPCC_BG_COLOR_BPC_9bit = 1 -MPCC_BG_COLOR_BPC_10bit = 2 -MPCC_BG_COLOR_BPC_11bit = 3 -MPCC_BG_COLOR_BPC_12bit = 4 -MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', -} -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', -} -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', -} -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' -MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', -} -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_MODE' -MPCC_CONTROL_MPCC_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', -} -MPCC_CONTROL_MPCC_MODE_BYPASS = 0 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 -MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 -MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' -MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' -MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 -MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 -MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 -MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN' -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', -} -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' -MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_MODE_0', - 1: 'MPCC_GAMUT_REMAP_MODE_1', - 2: 'MPCC_GAMUT_REMAP_MODE_2', - 3: 'MPCC_GAMUT_REMAP_MODE_RSV', -} -MPCC_GAMUT_REMAP_MODE_0 = 0 -MPCC_GAMUT_REMAP_MODE_1 = 1 -MPCC_GAMUT_REMAP_MODE_2 = 2 -MPCC_GAMUT_REMAP_MODE_RSV = 3 -MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' -MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', -} -MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 -MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 -MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 -MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' -MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_OGAM_DIFFERENT_RGB', - 1: 'MPCC_OGAM_ALL_USE_R', -} -MPCC_OGAM_DIFFERENT_RGB = 0 -MPCC_OGAM_ALL_USE_R = 1 -MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' -MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_ENABLE_PWL', - 1: 'MPCC_OGAM_DISABLE_PWL', -} -MPCC_OGAM_ENABLE_PWL = 0 -MPCC_OGAM_DISABLE_PWL = 1 -MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', -} -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_RAMA_ACCESS', - 1: 'MPCC_OGAM_RAMB_ACCESS', -} -MPCC_OGAM_RAMA_ACCESS = 0 -MPCC_OGAM_RAMB_ACCESS = 1 -MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' -MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_OGAM_BLUE_LUT', - 1: 'MPCC_OGAM_GREEN_LUT', - 2: 'MPCC_OGAM_RED_LUT', -} -MPCC_OGAM_BLUE_LUT = 0 -MPCC_OGAM_GREEN_LUT = 1 -MPCC_OGAM_RED_LUT = 2 -MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' -MPCC_OGAM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_OGAM_DISABLE_DEBUG', - 1: 'MPCC_OGAM_ENABLE_DEBUG', -} -MPCC_OGAM_DISABLE_DEBUG = 0 -MPCC_OGAM_ENABLE_DEBUG = 1 -MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' -MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_OGAM_RAMA', - 1: 'MPCC_OGAM_RAMB', -} -MPCC_OGAM_RAMA = 0 -MPCC_OGAM_RAMB = 1 -MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_MODE_0', - 1: 'MPCC_OGAM_MODE_RSV1', - 2: 'MPCC_OGAM_MODE_2', - 3: 'MPCC_OGAM_MODE_RSV', -} -MPCC_OGAM_MODE_0 = 0 -MPCC_OGAM_MODE_RSV1 = 1 -MPCC_OGAM_MODE_2 = 2 -MPCC_OGAM_MODE_RSV = 3 -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_NUM_SEG' -MPCC_OGAM_NUM_SEG__enumvalues = { - 0: 'MPCC_OGAM_SEGMENTS_1', - 1: 'MPCC_OGAM_SEGMENTS_2', - 2: 'MPCC_OGAM_SEGMENTS_4', - 3: 'MPCC_OGAM_SEGMENTS_8', - 4: 'MPCC_OGAM_SEGMENTS_16', - 5: 'MPCC_OGAM_SEGMENTS_32', - 6: 'MPCC_OGAM_SEGMENTS_64', - 7: 'MPCC_OGAM_SEGMENTS_128', -} -MPCC_OGAM_SEGMENTS_1 = 0 -MPCC_OGAM_SEGMENTS_2 = 1 -MPCC_OGAM_SEGMENTS_4 = 2 -MPCC_OGAM_SEGMENTS_8 = 3 -MPCC_OGAM_SEGMENTS_16 = 4 -MPCC_OGAM_SEGMENTS_32 = 5 -MPCC_OGAM_SEGMENTS_64 = 6 -MPCC_OGAM_SEGMENTS_128 = 7 -MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', -} -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' -MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_36BIT', - 1: 'MPCC_MCM_3DLUT_30BIT', -} -MPCC_MCM_3DLUT_36BIT = 0 -MPCC_MCM_3DLUT_30BIT = 1 -MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' -MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_RAM0_ACCESS', - 1: 'MPCC_MCM_RAM1_ACCESS', - 2: 'MPCC_MCM_RAM2_ACCESS', - 3: 'MPCC_MCM_RAM3_ACCESS', -} -MPCC_MCM_RAM0_ACCESS = 0 -MPCC_MCM_RAM1_ACCESS = 1 -MPCC_MCM_RAM2_ACCESS = 2 -MPCC_MCM_RAM3_ACCESS = 3 -MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' -MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_17CUBE', - 1: 'MPCC_MCM_3DLUT_9CUBE', -} -MPCC_MCM_3DLUT_17CUBE = 0 -MPCC_MCM_3DLUT_9CUBE = 1 -MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' -MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', - 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', - 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', -} -MPCC_MCM_GAMMA_LUT_BYPASS = 0 -MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 -MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 -MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 -MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', -} -MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 -MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' -MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_RAMA', - 1: 'MPCC_MCM_GAMMA_LUT_RAMB', -} -MPCC_MCM_GAMMA_LUT_RAMA = 0 -MPCC_MCM_GAMMA_LUT_RAMB = 1 -MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' -MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', - 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', -} -MPCC_MCM_LUT_2_MODE_BYPASS = 0 -MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 -MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 -MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' -MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', - 1: 'MPCC_MCM_LUT_ALL_USE_R', -} -MPCC_MCM_LUT_DIFFERENT_RGB = 0 -MPCC_MCM_LUT_ALL_USE_R = 1 -MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' -MPCC_MCM_LUT_NUM_SEG__enumvalues = { - 0: 'MPCC_MCM_LUT_SEGMENTS_1', - 1: 'MPCC_MCM_LUT_SEGMENTS_2', - 2: 'MPCC_MCM_LUT_SEGMENTS_4', - 3: 'MPCC_MCM_LUT_SEGMENTS_8', - 4: 'MPCC_MCM_LUT_SEGMENTS_16', - 5: 'MPCC_MCM_LUT_SEGMENTS_32', - 6: 'MPCC_MCM_LUT_SEGMENTS_64', - 7: 'MPCC_MCM_LUT_SEGMENTS_128', -} -MPCC_MCM_LUT_SEGMENTS_1 = 0 -MPCC_MCM_LUT_SEGMENTS_2 = 1 -MPCC_MCM_LUT_SEGMENTS_4 = 2 -MPCC_MCM_LUT_SEGMENTS_8 = 3 -MPCC_MCM_LUT_SEGMENTS_16 = 4 -MPCC_MCM_LUT_SEGMENTS_32 = 5 -MPCC_MCM_LUT_SEGMENTS_64 = 6 -MPCC_MCM_LUT_SEGMENTS_128 = 7 -MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' -MPCC_MCM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_RAMA_ACCESS', - 1: 'MPCC_MCM_LUT_RAMB_ACCESS', -} -MPCC_MCM_LUT_RAMA_ACCESS = 0 -MPCC_MCM_LUT_RAMB_ACCESS = 1 -MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' -MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_BLUE_LUT', - 1: 'MPCC_MCM_LUT_GREEN_LUT', - 2: 'MPCC_MCM_LUT_RED_LUT', -} -MPCC_MCM_LUT_BLUE_LUT = 0 -MPCC_MCM_LUT_GREEN_LUT = 1 -MPCC_MCM_LUT_RED_LUT = 2 -MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_DBG' -MPCC_MCM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', - 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', -} -MPCC_MCM_LUT_DISABLE_DEBUG = 0 -MPCC_MCM_LUT_ENABLE_DEBUG = 1 -MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' -MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', - 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', - 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', -} -MPCC_MCM_MEM_PWR_FORCE_DIS = 0 -MPCC_MCM_MEM_PWR_FORCE_LS = 1 -MPCC_MCM_MEM_PWR_FORCE_DS = 2 -MPCC_MCM_MEM_PWR_FORCE_SD = 3 -MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' -MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_STATE_ON', - 1: 'MPCC_MCM_MEM_PWR_STATE_LS', - 2: 'MPCC_MCM_MEM_PWR_STATE_DS', - 3: 'MPCC_MCM_MEM_PWR_STATE_SD', -} -MPCC_MCM_MEM_PWR_STATE_ON = 0 -MPCC_MCM_MEM_PWR_STATE_LS = 1 -MPCC_MCM_MEM_PWR_STATE_DS = 2 -MPCC_MCM_MEM_PWR_STATE_SD = 3 -MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_BIT_DEPTH' -ENUM_DPG_BIT_DEPTH__enumvalues = { - 0: 'ENUM_DPG_BIT_DEPTH_6BPC', - 1: 'ENUM_DPG_BIT_DEPTH_8BPC', - 2: 'ENUM_DPG_BIT_DEPTH_10BPC', - 3: 'ENUM_DPG_BIT_DEPTH_12BPC', -} -ENUM_DPG_BIT_DEPTH_6BPC = 0 -ENUM_DPG_BIT_DEPTH_8BPC = 1 -ENUM_DPG_BIT_DEPTH_10BPC = 2 -ENUM_DPG_BIT_DEPTH_12BPC = 3 -ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' -ENUM_DPG_DYNAMIC_RANGE__enumvalues = { - 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', - 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', -} -ENUM_DPG_DYNAMIC_RANGE_VESA = 0 -ENUM_DPG_DYNAMIC_RANGE_CEA = 1 -ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_EN' -ENUM_DPG_EN__enumvalues = { - 0: 'ENUM_DPG_DISABLE', - 1: 'ENUM_DPG_ENABLE', -} -ENUM_DPG_DISABLE = 0 -ENUM_DPG_ENABLE = 1 -ENUM_DPG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_FIELD_POLARITY' -ENUM_DPG_FIELD_POLARITY__enumvalues = { - 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', -} -ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 -ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 -ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_MODE' -ENUM_DPG_MODE__enumvalues = { - 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 3: 'ENUM_DPG_MODE_VERTICAL_BAR', - 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', - 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', - 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', -} -ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 -ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 -ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 -ENUM_DPG_MODE_VERTICAL_BAR = 3 -ENUM_DPG_MODE_HORIZONTAL_BAR = 4 -ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 -ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 -ENUM_DPG_MODE_RGB_XR_BIAS = 7 -ENUM_DPG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_DIS_CTRL' -FMTMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', -} -FMTMEM_ENABLE_MEM_PWR_CTRL = 0 -FMTMEM_DISABLE_MEM_PWR_CTRL = 1 -FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' -FMTMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'FMTMEM_NO_FORCE_REQUEST', - 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', -} -FMTMEM_NO_FORCE_REQUEST = 0 -FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 -FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' -FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' -FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', -} -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' -FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' -FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { - 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', -} -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 -FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { - 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', -} -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' -FMT_CONTROL_PIXEL_ENCODING__enumvalues = { - 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', -} -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 -FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' -FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', -} -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 -FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' -FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', -} -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 -FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' -FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { - 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', -} -FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 -FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 -FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 -FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 -FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DYNAMIC_EXP_MODE' -FMT_DYNAMIC_EXP_MODE__enumvalues = { - 0: 'FMT_DYNAMIC_EXP_MODE_10to12', - 1: 'FMT_DYNAMIC_EXP_MODE_8to12', -} -FMT_DYNAMIC_EXP_MODE_10to12 = 0 -FMT_DYNAMIC_EXP_MODE_8to12 = 1 -FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' -FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', -} -FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 -FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 -FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_POWER_STATE_ENUM' -FMT_POWER_STATE_ENUM__enumvalues = { - 0: 'FMT_POWER_STATE_ENUM_ON', - 1: 'FMT_POWER_STATE_ENUM_LS', - 2: 'FMT_POWER_STATE_ENUM_DS', - 3: 'FMT_POWER_STATE_ENUM_SD', -} -FMT_POWER_STATE_ENUM_ON = 0 -FMT_POWER_STATE_ENUM_LS = 1 -FMT_POWER_STATE_ENUM_DS = 2 -FMT_POWER_STATE_ENUM_SD = 3 -FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' -FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', -} -FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 -FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 -FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', -} -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_MODE' -FMT_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_MODE_0', - 1: 'FMT_SPATIAL_DITHER_MODE_1', - 2: 'FMT_SPATIAL_DITHER_MODE_2', - 3: 'FMT_SPATIAL_DITHER_MODE_3', -} -FMT_SPATIAL_DITHER_MODE_0 = 0 -FMT_SPATIAL_DITHER_MODE_1 = 1 -FMT_SPATIAL_DITHER_MODE_2 = 2 -FMT_SPATIAL_DITHER_MODE_3 = 3 -FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' -FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { - 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', -} -FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 -FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 -FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum - -# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' -OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { - 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', -} -OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 -OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 -OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' -OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { - 0: 'OPP_PIPE_CLOCK_DISABLE', - 1: 'OPP_PIPE_CLOCK_ENABLE', -} -OPP_PIPE_CLOCK_DISABLE = 0 -OPP_PIPE_CLOCK_ENABLE = 1 -OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' -OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { - 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', -} -OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 -OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 -OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_CONT_EN' -OPP_PIPE_CRC_CONT_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', - 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', -} -OPP_PIPE_CRC_MODE_ONE_SHOT = 0 -OPP_PIPE_CRC_MODE_CONTINUOUS = 1 -OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_EN' -OPP_PIPE_CRC_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_DISABLE', - 1: 'OPP_PIPE_CRC_ENABLE', -} -OPP_PIPE_CRC_DISABLE = 0 -OPP_PIPE_CRC_ENABLE = 1 -OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' -OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', -} -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 -OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' -OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', - 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', -} -OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 -OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 -OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' -OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { - 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', -} -OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 -OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 -OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' -OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', -} -OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 -OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 -OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 -OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 -OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' -OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', -} -OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 -OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 -OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' -OPP_PIPE_CRC_STEREO_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', -} -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 -OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' -OPP_PIPE_CRC_STEREO_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', - 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', -} -OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 -OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 -OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL' -OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_ABM0', - 1: 'DEBUG_BUS_SELECT_ABM1', - 2: 'DEBUG_BUS_SELECT_ABM2', - 3: 'DEBUG_BUS_SELECT_ABM3', - 4: 'DEBUG_BUS_SELECT_ABM_RESERVED0', - 5: 'DEBUG_BUS_SELECT_ABM_RESERVED1', -} -DEBUG_BUS_SELECT_ABM0 = 0 -DEBUG_BUS_SELECT_ABM1 = 1 -DEBUG_BUS_SELECT_ABM2 = 2 -DEBUG_BUS_SELECT_ABM3 = 3 -DEBUG_BUS_SELECT_ABM_RESERVED0 = 4 -DEBUG_BUS_SELECT_ABM_RESERVED1 = 5 -OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL' -OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_DPG0', - 1: 'DEBUG_BUS_SELECT_DPG1', - 2: 'DEBUG_BUS_SELECT_DPG2', - 3: 'DEBUG_BUS_SELECT_DPG3', - 4: 'DEBUG_BUS_SELECT_DPG_RESERVED0', - 5: 'DEBUG_BUS_SELECT_DPG_RESERVED1', -} -DEBUG_BUS_SELECT_DPG0 = 0 -DEBUG_BUS_SELECT_DPG1 = 1 -DEBUG_BUS_SELECT_DPG2 = 2 -DEBUG_BUS_SELECT_DPG3 = 3 -DEBUG_BUS_SELECT_DPG_RESERVED0 = 4 -DEBUG_BUS_SELECT_DPG_RESERVED1 = 5 -OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL' -OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_FMT0', - 1: 'DEBUG_BUS_SELECT_FMT1', - 2: 'DEBUG_BUS_SELECT_FMT2', - 3: 'DEBUG_BUS_SELECT_FMT3', - 4: 'DEBUG_BUS_SELECT_FMT_RESERVED0', - 5: 'DEBUG_BUS_SELECT_FMT_RESERVED1', -} -DEBUG_BUS_SELECT_FMT0 = 0 -DEBUG_BUS_SELECT_FMT1 = 1 -DEBUG_BUS_SELECT_FMT2 = 2 -DEBUG_BUS_SELECT_FMT3 = 3 -DEBUG_BUS_SELECT_FMT_RESERVED0 = 4 -DEBUG_BUS_SELECT_FMT_RESERVED1 = 5 -OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL' -OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_OPPBUF0', - 1: 'DEBUG_BUS_SELECT_OPPBUF1', - 2: 'DEBUG_BUS_SELECT_OPPBUF2', - 3: 'DEBUG_BUS_SELECT_OPPBUF3', - 4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', - 5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', -} -DEBUG_BUS_SELECT_OPPBUF0 = 0 -DEBUG_BUS_SELECT_OPPBUF1 = 1 -DEBUG_BUS_SELECT_OPPBUF2 = 2 -DEBUG_BUS_SELECT_OPPBUF3 = 3 -DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4 -DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5 -OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL' -OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_OPP_PIPE0', - 1: 'DEBUG_BUS_SELECT_OPP_PIPE1', - 2: 'DEBUG_BUS_SELECT_OPP_PIPE2', - 3: 'DEBUG_BUS_SELECT_OPP_PIPE3', - 4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', - 5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', -} -DEBUG_BUS_SELECT_OPP_PIPE0 = 0 -DEBUG_BUS_SELECT_OPP_PIPE1 = 1 -DEBUG_BUS_SELECT_OPP_PIPE2 = 2 -DEBUG_BUS_SELECT_OPP_PIPE3 = 3 -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4 -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5 -OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' -OPP_TEST_CLK_SEL_CONTROL__enumvalues = { - 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', - 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', - 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', - 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', - 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 6: 'OPP_TEST_CLK_SEL_RESERVED0', - 7: 'OPP_TEST_CLK_SEL_RESERVED1', - 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', - 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', - 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 12: 'OPP_TEST_CLK_SEL_RESERVED2', - 13: 'OPP_TEST_CLK_SEL_RESERVED3', -} -OPP_TEST_CLK_SEL_DISPCLK_P = 0 -OPP_TEST_CLK_SEL_DISPCLK_R = 1 -OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 -OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 -OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 -OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 -OPP_TEST_CLK_SEL_RESERVED0 = 6 -OPP_TEST_CLK_SEL_RESERVED1 = 7 -OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 -OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 -OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 -OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 -OPP_TEST_CLK_SEL_RESERVED2 = 12 -OPP_TEST_CLK_SEL_RESERVED3 = 13 -OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' -OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { - 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', - 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', -} -OPP_TOP_CLOCK_DISABLED_STATUS = 0 -OPP_TOP_CLOCK_ENABLED_STATUS = 1 -OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' -OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { - 0: 'OPP_TOP_CLOCK_GATING_ENABLED', - 1: 'OPP_TOP_CLOCK_GATING_DISABLED', -} -OPP_TOP_CLOCK_GATING_ENABLED = 0 -OPP_TOP_CLOCK_GATING_DISABLED = 1 -OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DSCRM_EN' -ENUM_DSCRM_EN__enumvalues = { - 0: 'ENUM_DSCRM_DISABLE', - 1: 'ENUM_DSCRM_ENABLE', -} -ENUM_DSCRM_DISABLE = 0 -ENUM_DSCRM_ENABLE = 1 -ENUM_DSCRM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_SEL' -MASTER_UPDATE_LOCK_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_SEL_0', - 1: 'MASTER_UPDATE_LOCK_SEL_1', - 2: 'MASTER_UPDATE_LOCK_SEL_2', - 3: 'MASTER_UPDATE_LOCK_SEL_3', - 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', -} -MASTER_UPDATE_LOCK_SEL_0 = 0 -MASTER_UPDATE_LOCK_SEL_1 = 1 -MASTER_UPDATE_LOCK_SEL_2 = 2 -MASTER_UPDATE_LOCK_SEL_3 = 3 -MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 -MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 -MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' -OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', -} -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', -} -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', -} -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' -OTG_CONTROL_OTG_MASTER_EN__enumvalues = { - 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', -} -OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 -OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 -OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' -OTG_CONTROL_OTG_OUT_MUX__enumvalues = { - 0: 'OTG_CONTROL_OTG_OUT_MUX_0', - 1: 'OTG_CONTROL_OTG_OUT_MUX_1', - 2: 'OTG_CONTROL_OTG_OUT_MUX_2', -} -OTG_CONTROL_OTG_OUT_MUX_0 = 0 -OTG_CONTROL_OTG_OUT_MUX_1 = 1 -OTG_CONTROL_OTG_OUT_MUX_2 = 2 -OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' -OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', -} -OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 -OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { - 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', -} -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' -OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' -OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' -OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', -} -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' -OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', -} -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', -} -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' -OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { - 0: 'OTG_DIG_UPDATE_VCOUNT_0', - 1: 'OTG_DIG_UPDATE_VCOUNT_1', -} -OTG_DIG_UPDATE_VCOUNT_0 = 0 -OTG_DIG_UPDATE_VCOUNT_1 = 1 -OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { - 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', -} -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { - 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', -} -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { - 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', -} -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { - 0: 'DIG_UPDATE_EYE_SEL_BOTH', - 1: 'DIG_UPDATE_EYE_SEL_LEFT', - 2: 'DIG_UPDATE_EYE_SEL_RIGHT', -} -DIG_UPDATE_EYE_SEL_BOTH = 0 -DIG_UPDATE_EYE_SEL_LEFT = 1 -DIG_UPDATE_EYE_SEL_RIGHT = 2 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { - 0: 'DIG_UPDATE_FIELD_SEL_BOTH', - 1: 'DIG_UPDATE_FIELD_SEL_TOP', - 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', -} -DIG_UPDATE_FIELD_SEL_BOTH = 0 -DIG_UPDATE_FIELD_SEL_TOP = 1 -DIG_UPDATE_FIELD_SEL_BOTTOM = 2 -DIG_UPDATE_FIELD_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', -} -MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 -MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 -MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 -MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', -} -MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' -OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { - 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', - 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', -} -OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 -OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 -OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GSL_MASTER_MODE' -OTG_GSL_MASTER_MODE__enumvalues = { - 0: 'OTG_GSL_MASTER_MODE_0', - 1: 'OTG_GSL_MASTER_MODE_1', - 2: 'OTG_GSL_MASTER_MODE_2', - 3: 'OTG_GSL_MASTER_MODE_3', -} -OTG_GSL_MASTER_MODE_0 = 0 -OTG_GSL_MASTER_MODE_1 = 1 -OTG_GSL_MASTER_MODE_2 = 2 -OTG_GSL_MASTER_MODE_3 = 3 -OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_HORZ_REPETITION_COUNT' -OTG_HORZ_REPETITION_COUNT__enumvalues = { - 0: 'OTG_HORZ_REPETITION_COUNT_0', - 1: 'OTG_HORZ_REPETITION_COUNT_1', - 2: 'OTG_HORZ_REPETITION_COUNT_2', - 3: 'OTG_HORZ_REPETITION_COUNT_3', - 4: 'OTG_HORZ_REPETITION_COUNT_4', - 5: 'OTG_HORZ_REPETITION_COUNT_5', - 6: 'OTG_HORZ_REPETITION_COUNT_6', - 7: 'OTG_HORZ_REPETITION_COUNT_7', - 8: 'OTG_HORZ_REPETITION_COUNT_8', - 9: 'OTG_HORZ_REPETITION_COUNT_9', - 10: 'OTG_HORZ_REPETITION_COUNT_10', - 11: 'OTG_HORZ_REPETITION_COUNT_11', - 12: 'OTG_HORZ_REPETITION_COUNT_12', - 13: 'OTG_HORZ_REPETITION_COUNT_13', - 14: 'OTG_HORZ_REPETITION_COUNT_14', - 15: 'OTG_HORZ_REPETITION_COUNT_15', -} -OTG_HORZ_REPETITION_COUNT_0 = 0 -OTG_HORZ_REPETITION_COUNT_1 = 1 -OTG_HORZ_REPETITION_COUNT_2 = 2 -OTG_HORZ_REPETITION_COUNT_3 = 3 -OTG_HORZ_REPETITION_COUNT_4 = 4 -OTG_HORZ_REPETITION_COUNT_5 = 5 -OTG_HORZ_REPETITION_COUNT_6 = 6 -OTG_HORZ_REPETITION_COUNT_7 = 7 -OTG_HORZ_REPETITION_COUNT_8 = 8 -OTG_HORZ_REPETITION_COUNT_9 = 9 -OTG_HORZ_REPETITION_COUNT_10 = 10 -OTG_HORZ_REPETITION_COUNT_11 = 11 -OTG_HORZ_REPETITION_COUNT_12 = 12 -OTG_HORZ_REPETITION_COUNT_13 = 13 -OTG_HORZ_REPETITION_COUNT_14 = 14 -OTG_HORZ_REPETITION_COUNT_15 = 15 -OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_SYNC_A_POL' -OTG_H_SYNC_A_POL__enumvalues = { - 0: 'OTG_H_SYNC_A_POL_HIGH', - 1: 'OTG_H_SYNC_A_POL_LOW', -} -OTG_H_SYNC_A_POL_HIGH = 0 -OTG_H_SYNC_A_POL_LOW = 1 -OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE' -OTG_H_TIMING_DIV_MODE__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', - 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', - 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', - 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', -} -OTG_H_TIMING_DIV_MODE_NO_DIV = 0 -OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 -OTG_H_TIMING_DIV_MODE_RESERVED = 2 -OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 -OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' -OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_AUTO', - 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', -} -OTG_H_TIMING_DIV_MODE_AUTO = 0 -OTG_H_TIMING_DIV_MODE_NOAUTO = 1 -OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { - 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', -} -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' -OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', -} -OTG_MASTER_UPDATE_LOCK_DISABLE = 0 -OTG_MASTER_UPDATE_LOCK_ENABLE = 1 -OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' -OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', -} -OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 -OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 -OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', -} -OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 -OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { - 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', -} -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { - 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', -} -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', -} -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' -OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { - 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', -} -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', -} -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' -OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', -} -OTG_TRIGA_FREQUENCY_SELECT_0 = 0 -OTG_TRIGA_FREQUENCY_SELECT_1 = 1 -OTG_TRIGA_FREQUENCY_SELECT_2 = 2 -OTG_TRIGA_FREQUENCY_SELECT_3 = 3 -OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' -OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', -} -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' -OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', -} -OTG_TRIGB_FREQUENCY_SELECT_0 = 0 -OTG_TRIGB_FREQUENCY_SELECT_1 = 1 -OTG_TRIGB_FREQUENCY_SELECT_2 = 2 -OTG_TRIGB_FREQUENCY_SELECT_3 = 3 -OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' -OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { - 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', -} -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', -} -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', -} -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { - 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', -} -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' -OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { - 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', -} -OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 -OTG_VUPDATE_BLOCK_DISABLE_ON = 1 -OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_A_POL' -OTG_V_SYNC_A_POL__enumvalues = { - 0: 'OTG_V_SYNC_A_POL_HIGH', - 1: 'OTG_V_SYNC_A_POL_LOW', -} -OTG_V_SYNC_A_POL_HIGH = 0 -OTG_V_SYNC_A_POL_LOW = 1 -OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_MODE' -OTG_V_SYNC_MODE__enumvalues = { - 0: 'OTG_V_SYNC_MODE_HSYNC', - 1: 'OTG_V_SYNC_MODE_HBLANK', -} -OTG_V_SYNC_MODE_HSYNC = 0 -OTG_V_SYNC_MODE_HBLANK = 1 -OTG_V_SYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', -} -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { - 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', -} -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { - 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', -} -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_INT_TYPE' -DC_DMCUB_INT_TYPE__enumvalues = { - 0: 'INT_LEVEL', - 1: 'INT_PULSE', -} -INT_LEVEL = 0 -INT_PULSE = 1 -DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_TIMER_WINDOW' -DC_DMCUB_TIMER_WINDOW__enumvalues = { - 0: 'BITS_31_0', - 1: 'BITS_32_1', - 2: 'BITS_33_2', - 3: 'BITS_34_3', - 4: 'BITS_35_4', - 5: 'BITS_36_5', - 6: 'BITS_37_6', - 7: 'BITS_38_7', -} -BITS_31_0 = 0 -BITS_32_1 = 1 -BITS_33_2 = 2 -BITS_34_3 = 3 -BITS_35_4 = 4 -BITS_36_5 = 5 -BITS_37_6 = 6 -BITS_38_7 = 7 -DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'INVALID_REG_ACCESS_TYPE' -INVALID_REG_ACCESS_TYPE__enumvalues = { - 0: 'REG_UNALLOCATED_ADDR_WRITE', - 1: 'REG_UNALLOCATED_ADDR_READ', - 2: 'REG_VIRTUAL_WRITE', - 3: 'REG_VIRTUAL_READ', - 4: 'REG_SECURE_VIOLATE_WRITE', - 5: 'REG_SECURE_VIOLATE_READ', -} -REG_UNALLOCATED_ADDR_WRITE = 0 -REG_UNALLOCATED_ADDR_READ = 1 -REG_VIRTUAL_WRITE = 2 -REG_VIRTUAL_READ = 3 -REG_SECURE_VIOLATE_WRITE = 4 -REG_SECURE_VIOLATE_READ = 5 -INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' -DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 8: 'RESERVED_8', - 9: 'RESERVED_9', - 10: 'RESERVED_10', - 11: 'RESERVED_11', - 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 20: 'RESERVED_20', - 21: 'RESERVED_21', - 22: 'RESERVED_22', - 23: 'RESERVED_23', - 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 32: 'RESERVED_32', - 33: 'RESERVED_33', - 34: 'RESERVED_34', - 35: 'RESERVED_35', - 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 44: 'RESERVED_44', - 45: 'RESERVED_45', - 46: 'RESERVED_46', - 47: 'RESERVED_47', - 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 56: 'RESERVED_56', - 57: 'RESERVED_57', - 58: 'RESERVED_58', - 59: 'RESERVED_59', - 60: 'RESERVED_60', - 61: 'RESERVED_61', - 62: 'RESERVED_62', - 63: 'RESERVED_63', - 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 72: 'RESERVED_72', - 73: 'RESERVED_73', - 74: 'RESERVED_74', - 75: 'RESERVED_75', - 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 84: 'RESERVED_84', - 85: 'RESERVED_85', - 86: 'RESERVED_86', - 87: 'RESERVED_87', - 88: 'RESERVED_88', - 89: 'RESERVED_89', - 90: 'RESERVED_90', - 91: 'RESERVED_91', -} -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 -RESERVED_8 = 8 -RESERVED_9 = 9 -RESERVED_10 = 10 -RESERVED_11 = 11 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 -RESERVED_20 = 20 -RESERVED_21 = 21 -RESERVED_22 = 22 -RESERVED_23 = 23 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 -RESERVED_32 = 32 -RESERVED_33 = 33 -RESERVED_34 = 34 -RESERVED_35 = 35 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 -RESERVED_44 = 44 -RESERVED_45 = 45 -RESERVED_46 = 46 -RESERVED_47 = 47 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 -RESERVED_56 = 56 -RESERVED_57 = 57 -RESERVED_58 = 58 -RESERVED_59 = 59 -RESERVED_60 = 60 -RESERVED_61 = 61 -RESERVED_62 = 62 -RESERVED_63 = 63 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 -RESERVED_72 = 72 -RESERVED_73 = 73 -RESERVED_74 = 74 -RESERVED_75 = 75 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 -RESERVED_84 = 84 -RESERVED_85 = 85 -RESERVED_86 = 86 -RESERVED_87 = 87 -RESERVED_88 = 88 -RESERVED_89 = 89 -RESERVED_90 = 90 -RESERVED_91 = 91 -DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' -DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DMU_GPU_TIMER_START_0_END_27', - 1: 'DMU_GPU_TIMER_START_1_END_28', - 2: 'DMU_GPU_TIMER_START_2_END_29', - 3: 'DMU_GPU_TIMER_START_3_END_30', - 4: 'DMU_GPU_TIMER_START_4_END_31', - 5: 'DMU_GPU_TIMER_START_6_END_33', - 6: 'DMU_GPU_TIMER_START_8_END_35', - 7: 'DMU_GPU_TIMER_START_10_END_37', -} -DMU_GPU_TIMER_START_0_END_27 = 0 -DMU_GPU_TIMER_START_1_END_28 = 1 -DMU_GPU_TIMER_START_2_END_29 = 2 -DMU_GPU_TIMER_START_3_END_30 = 3 -DMU_GPU_TIMER_START_4_END_31 = 4 -DMU_GPU_TIMER_START_6_END_33 = 5 -DMU_GPU_TIMER_START_8_END_35 = 6 -DMU_GPU_TIMER_START_10_END_37 = 7 -DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_DEST' -IHC_INTERRUPT_DEST__enumvalues = { - 0: 'INTERRUPT_SENT_TO_IH', - 1: 'INTERRUPT_SENT_TO_DMCUB', -} -INTERRUPT_SENT_TO_IH = 0 -INTERRUPT_SENT_TO_DMCUB = 1 -IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' -IHC_INTERRUPT_LINE_STATUS__enumvalues = { - 0: 'INTERRUPT_LINE_NOT_ASSERTED', - 1: 'INTERRUPT_LINE_ASSERTED', -} -INTERRUPT_LINE_NOT_ASSERTED = 0 -INTERRUPT_LINE_ASSERTED = 1 -IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' -DC_SMU_INTERRUPT_ENABLE__enumvalues = { - 0: 'DISABLE_THE_INTERRUPT', - 1: 'ENABLE_THE_INTERRUPT', -} -DISABLE_THE_INTERRUPT = 0 -ENABLE_THE_INTERRUPT = 1 -DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_CLOCK_ON' -DMU_CLOCK_ON__enumvalues = { - 0: 'DMU_CLOCK_STATUS_ON', - 1: 'DMU_CLOCK_STATUS_OFF', -} -DMU_CLOCK_STATUS_ON = 0 -DMU_CLOCK_STATUS_OFF = 1 -DMU_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'SMU_INTR' -SMU_INTR__enumvalues = { - 0: 'SMU_MSG_INTR_NOOP', - 1: 'SET_SMU_MSG_INTR', -} -SMU_MSG_INTR_NOOP = 0 -SET_SMU_MSG_INTR = 1 -SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' -ALLOW_SR_ON_TRANS_REQ__enumvalues = { - 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', -} -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 -ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 -ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'AMCLOCK_ENABLE' -AMCLOCK_ENABLE__enumvalues = { - 0: 'ENABLE_AMCLK0', - 1: 'ENABLE_AMCLK1', -} -ENABLE_AMCLK0 = 0 -ENABLE_AMCLK1 = 1 -AMCLOCK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CLEAR_SMU_INTR' -CLEAR_SMU_INTR__enumvalues = { - 0: 'SMU_INTR_STATUS_NOOP', - 1: 'SMU_INTR_STATUS_CLEAR', -} -SMU_INTR_STATUS_NOOP = 0 -SMU_INTR_STATUS_CLEAR = 1 -CLEAR_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' -CLOCK_BRANCH_SOFT_RESET__enumvalues = { - 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', -} -CLOCK_BRANCH_SOFT_RESET_NOOP = 0 -CLOCK_BRANCH_SOFT_RESET_FORCE = 1 -CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' -DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', -} -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 -DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' -DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', -} -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 -DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_SEL' -DCCG_AUDIO_DTO_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', - 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', -} -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3 -DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' -DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { - 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', -} -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 -DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_BLOCK_SEL' -DCCG_DBG_BLOCK_SEL__enumvalues = { - 0: 'DCCG_DBG_BLOCK_SEL_DCCG', - 1: 'DCCG_DBG_BLOCK_SEL_PMON', - 2: 'DCCG_DBG_BLOCK_SEL_PMON2', -} -DCCG_DBG_BLOCK_SEL_DCCG = 0 -DCCG_DBG_BLOCK_SEL_PMON = 1 -DCCG_DBG_BLOCK_SEL_PMON2 = 2 -DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_EN' -DCCG_DBG_EN__enumvalues = { - 0: 'DCCG_DBG_EN_DISABLE', - 1: 'DCCG_DBG_EN_ENABLE', -} -DCCG_DBG_EN_DISABLE = 0 -DCCG_DBG_EN_ENABLE = 1 -DCCG_DBG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DEEP_COLOR_CNTL' -DCCG_DEEP_COLOR_CNTL__enumvalues = { - 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', - 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', - 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', -} -DCCG_DEEP_COLOR_DTO_DISABLE = 0 -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 -DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' -DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', - 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', -} -DCCG_FIFO_ERRDET_OVR_DISABLE = 0 -DCCG_FIFO_ERRDET_OVR_ENABLE = 1 -DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_RESET' -DCCG_FIFO_ERRDET_RESET__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', - 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', -} -DCCG_FIFO_ERRDET_RESET_NOOP = 0 -DCCG_FIFO_ERRDET_RESET_FORCE = 1 -DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_STATE' -DCCG_FIFO_ERRDET_STATE__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', -} -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 -DCCG_FIFO_ERRDET_STATE_DETECTION = 1 -DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_HSYNC' -DCCG_PERF_MODE_HSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_HSYNC_NOOP', - 1: 'DCCG_PERF_MODE_HSYNC_START', -} -DCCG_PERF_MODE_HSYNC_NOOP = 0 -DCCG_PERF_MODE_HSYNC_START = 1 -DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_VSYNC' -DCCG_PERF_MODE_VSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_VSYNC_NOOP', - 1: 'DCCG_PERF_MODE_VSYNC_START', -} -DCCG_PERF_MODE_VSYNC_NOOP = 0 -DCCG_PERF_MODE_VSYNC_START = 1 -DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_OTG_SELECT' -DCCG_PERF_OTG_SELECT__enumvalues = { - 0: 'DCCG_PERF_SEL_OTG0', - 1: 'DCCG_PERF_SEL_OTG1', - 2: 'DCCG_PERF_SEL_OTG2', - 3: 'DCCG_PERF_SEL_OTG3', - 4: 'DCCG_PERF_SEL_RESERVED', -} -DCCG_PERF_SEL_OTG0 = 0 -DCCG_PERF_SEL_OTG1 = 1 -DCCG_PERF_SEL_OTG2 = 2 -DCCG_PERF_SEL_OTG3 = 3 -DCCG_PERF_SEL_RESERVED = 4 -DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_RUN' -DCCG_PERF_RUN__enumvalues = { - 0: 'DCCG_PERF_RUN_NOOP', - 1: 'DCCG_PERF_RUN_START', -} -DCCG_PERF_RUN_NOOP = 0 -DCCG_PERF_RUN_START = 1 -DCCG_PERF_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' -DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { - 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', -} -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 -DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_FIFO_ERROR' -DIO_FIFO_ERROR__enumvalues = { - 0: 'DIO_FIFO_ERROR_00', - 1: 'DIO_FIFO_ERROR_01', - 2: 'DIO_FIFO_ERROR_10', - 3: 'DIO_FIFO_ERROR_11', -} -DIO_FIFO_ERROR_00 = 0 -DIO_FIFO_ERROR_01 = 1 -DIO_FIFO_ERROR_10 = 2 -DIO_FIFO_ERROR_11 = 3 -DIO_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING' -DISABLE_CLOCK_GATING__enumvalues = { - 0: 'CLOCK_GATING_ENABLED', - 1: 'CLOCK_GATING_DISABLED', -} -CLOCK_GATING_ENABLED = 0 -CLOCK_GATING_DISABLED = 1 -DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' -DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { - 0: 'CLOCK_GATING_ENABLED_IN_DCO', - 1: 'CLOCK_GATING_DISABLED_IN_DCO', -} -CLOCK_GATING_ENABLED_IN_DCO = 0 -CLOCK_GATING_DISABLED_IN_DCO = 1 -DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' -DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { - 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', -} -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 -DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' -DISPCLK_FREQ_RAMP_DONE__enumvalues = { - 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', - 1: 'DISPCLK_FREQ_RAMP_COMPLETED', -} -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 -DISPCLK_FREQ_RAMP_COMPLETED = 1 -DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DPREFCLK_SRC_SEL' -DPREFCLK_SRC_SEL__enumvalues = { - 0: 'DPREFCLK_SRC_SEL_CK', - 1: 'DPREFCLK_SRC_SEL_P0PLL', - 2: 'DPREFCLK_SRC_SEL_P1PLL', - 3: 'DPREFCLK_SRC_SEL_P2PLL', -} -DPREFCLK_SRC_SEL_CK = 0 -DPREFCLK_SRC_SEL_P0PLL = 1 -DPREFCLK_SRC_SEL_P1PLL = 2 -DPREFCLK_SRC_SEL_P2PLL = 3 -DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DTO_DS_DISABLE' -DP_DTO_DS_DISABLE__enumvalues = { - 0: 'DP_DTO_DESPREAD_DISABLE', - 1: 'DP_DTO_DESPREAD_ENABLE', -} -DP_DTO_DESPREAD_DISABLE = 0 -DP_DTO_DESPREAD_ENABLE = 1 -DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_HW_CAL_ENABLE' -DS_HW_CAL_ENABLE__enumvalues = { - 0: 'DS_HW_CAL_DIS', - 1: 'DS_HW_CAL_EN', -} -DS_HW_CAL_DIS = 0 -DS_HW_CAL_EN = 1 -DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' -DS_JITTER_COUNT_SRC_SEL__enumvalues = { - 0: 'DS_JITTER_COUNT_SRC_SEL0', - 1: 'DS_JITTER_COUNT_SRC_SEL1', -} -DS_JITTER_COUNT_SRC_SEL0 = 0 -DS_JITTER_COUNT_SRC_SEL1 = 1 -DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DS_REF_SRC' -DS_REF_SRC__enumvalues = { - 0: 'DS_REF_IS_XTALIN', - 1: 'DS_REF_IS_EXT_GENLOCK', - 2: 'DS_REF_IS_PCIE', -} -DS_REF_IS_XTALIN = 0 -DS_REF_IS_EXT_GENLOCK = 1 -DS_REF_IS_PCIE = 2 -DS_REF_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_IN_PHASE' -DVOACLKC_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_IN_PHASE' -DVOACLKC_MVP_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { - 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', -} -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKD_IN_PHASE' -DVOACLKD_IN_PHASE__enumvalues = { - 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' -DVOACLK_COARSE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', -} -DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 -DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 -DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 -DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 -DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 -DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 -DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 -DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 -DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 -DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 -DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 -DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 -DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 -DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 -DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 -DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 -DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 -DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 -DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 -DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 -DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 -DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 -DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 -DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 -DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 -DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 -DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 -DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' -DVOACLK_FINE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', -} -DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 -DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 -DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 -DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 -DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_ENABLE_RST' -DVO_ENABLE_RST__enumvalues = { - 0: 'DVO_ENABLE_RST_DISABLE', - 1: 'DVO_ENABLE_RST_ENABLE', -} -DVO_ENABLE_RST_DISABLE = 0 -DVO_ENABLE_RST_ENABLE = 1 -DVO_ENABLE_RST = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE' -ENABLE__enumvalues = { - 0: 'DISABLE_THE_FEATURE', - 1: 'ENABLE_THE_FEATURE', -} -DISABLE_THE_FEATURE = 0 -ENABLE_THE_FEATURE = 1 -ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_CLOCK' -ENABLE_CLOCK__enumvalues = { - 0: 'ENABLE_THE_REFCLK', - 1: 'ENABLE_THE_FUNC_CLOCK', -} -ENABLE_THE_REFCLK = 0 -ENABLE_THE_FUNC_CLOCK = 1 -ENABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_DISABLE_CLOCK' -FORCE_DISABLE_CLOCK__enumvalues = { - 0: 'NOT_FORCE_THE_CLOCK_DISABLED', - 1: 'FORCE_THE_CLOCK_DISABLED', -} -NOT_FORCE_THE_CLOCK_DISABLED = 0 -FORCE_THE_CLOCK_DISABLED = 1 -FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMICHARCLK_SRC_SEL' -HDMICHARCLK_SRC_SEL__enumvalues = { - 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', - 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', - 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', - 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', - 4: 'HDMICHARCLK_SRC_SEL_UNIPHYE', - 5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', -} -HDMICHARCLK_SRC_SEL_UNIPHYA = 0 -HDMICHARCLK_SRC_SEL_UNIPHYB = 1 -HDMICHARCLK_SRC_SEL_UNIPHYC = 2 -HDMICHARCLK_SRC_SEL_UNIPHYD = 3 -HDMICHARCLK_SRC_SEL_UNIPHYE = 4 -HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5 -HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS' -HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = { - 0: 'DTO_FORCE_NO_BYPASS', - 1: 'DTO_FORCE_BYPASS', -} -DTO_FORCE_NO_BYPASS = 0 -DTO_FORCE_BYPASS = 1 -HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'HDMISTREAMCLK_SRC_SEL' -HDMISTREAMCLK_SRC_SEL__enumvalues = { - 0: 'SEL_REFCLK0', - 1: 'SEL_DTBCLK0', - 2: 'SEL_DTBCLK1', -} -SEL_REFCLK0 = 0 -SEL_DTBCLK0 = 1 -SEL_DTBCLK1 = 2 -HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'JITTER_REMOVE_DISABLE' -JITTER_REMOVE_DISABLE__enumvalues = { - 0: 'ENABLE_JITTER_REMOVAL', - 1: 'DISABLE_JITTER_REMOVAL', -} -ENABLE_JITTER_REMOVAL = 0 -DISABLE_JITTER_REMOVAL = 1 -JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_ADD_PIXEL' -OTG_ADD_PIXEL__enumvalues = { - 0: 'OTG_ADD_PIXEL_NOOP', - 1: 'OTG_ADD_PIXEL_FORCE', -} -OTG_ADD_PIXEL_NOOP = 0 -OTG_ADD_PIXEL_FORCE = 1 -OTG_ADD_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DROP_PIXEL' -OTG_DROP_PIXEL__enumvalues = { - 0: 'OTG_DROP_PIXEL_NOOP', - 1: 'OTG_DROP_PIXEL_FORCE', -} -OTG_DROP_PIXEL_NOOP = 0 -OTG_DROP_PIXEL_FORCE = 1 -OTG_DROP_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_EN' -PHYSYMCLK_FORCE_EN__enumvalues = { - 0: 'PHYSYMCLK_FORCE_EN_DISABLE', - 1: 'PHYSYMCLK_FORCE_EN_ENABLE', -} -PHYSYMCLK_FORCE_EN_DISABLE = 0 -PHYSYMCLK_FORCE_EN_ENABLE = 1 -PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' -PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { - 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', - 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', - 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', -} -PHYSYMCLK_FORCE_SRC_SYMCLK = 0 -PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 -PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 -PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' -PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', -} -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 -PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' -PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', - 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', -} -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 -PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' -PIPE_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', - 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', -} -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 -PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 -PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 -PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PLL_CFG_IF_SOFT_RESET' -PLL_CFG_IF_SOFT_RESET__enumvalues = { - 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', - 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', -} -PLL_CFG_IF_SOFT_RESET_NOOP = 0 -PLL_CFG_IF_SOFT_RESET_FORCE = 1 -PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_EN' -SYMCLK_FE_FORCE_EN__enumvalues = { - 0: 'SYMCLK_FE_FORCE_EN_DISABLE', - 1: 'SYMCLK_FE_FORCE_EN_ENABLE', -} -SYMCLK_FE_FORCE_EN_DISABLE = 0 -SYMCLK_FE_FORCE_EN_ENABLE = 1 -SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_SRC' -SYMCLK_FE_FORCE_SRC__enumvalues = { - 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', - 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', - 4: 'SYMCLK_FE_FORCE_SRC_RESERVED', -} -SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 -SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 -SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 -SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 -SYMCLK_FE_FORCE_SRC_RESERVED = 4 -SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_DIV_SEL' -TEST_CLK_DIV_SEL__enumvalues = { - 0: 'NO_DIV', - 1: 'DIV_2', - 2: 'DIV_4', - 3: 'DIV_8', -} -NO_DIV = 0 -DIV_2 = 1 -DIV_4 = 2 -DIV_8 = 3 -TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_LATCH_MASK' -VSYNC_CNT_LATCH_MASK__enumvalues = { - 0: 'VSYNC_CNT_LATCH_MASK_0', - 1: 'VSYNC_CNT_LATCH_MASK_1', -} -VSYNC_CNT_LATCH_MASK_0 = 0 -VSYNC_CNT_LATCH_MASK_1 = 1 -VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_RESET_SEL' -VSYNC_CNT_RESET_SEL__enumvalues = { - 0: 'VSYNC_CNT_RESET_SEL_0', - 1: 'VSYNC_CNT_RESET_SEL_1', -} -VSYNC_CNT_RESET_SEL_0 = 0 -VSYNC_CNT_RESET_SEL_1 = 1 -VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' -XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', - 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', -} -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 -XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 -XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_SEL' -XTAL_REF_SEL__enumvalues = { - 0: 'XTAL_REF_SEL_1X', - 1: 'XTAL_REF_SEL_2X', -} -XTAL_REF_SEL_1X = 0 -XTAL_REF_SEL_2X = 1 -XTAL_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_ACK' -HPD_INT_CONTROL_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_ACK_0', - 1: 'HPD_INT_CONTROL_ACK_1', -} -HPD_INT_CONTROL_ACK_0 = 0 -HPD_INT_CONTROL_ACK_1 = 1 -HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_POLARITY' -HPD_INT_CONTROL_POLARITY__enumvalues = { - 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', - 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', -} -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 -HPD_INT_CONTROL_GEN_INT_ON_CON = 1 -HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' -HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', - 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', -} -HPD_INT_CONTROL_RX_INT_ACK_0 = 0 -HPD_INT_CONTROL_RX_INT_ACK_1 = 1 -HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_CUR_DISP' -DPHY_8B10B_CUR_DISP__enumvalues = { - 0: 'DPHY_8B10B_CUR_DISP_ZERO', - 1: 'DPHY_8B10B_CUR_DISP_ONE', -} -DPHY_8B10B_CUR_DISP_ZERO = 0 -DPHY_8B10B_CUR_DISP_ONE = 1 -DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_RESET' -DPHY_8B10B_RESET__enumvalues = { - 0: 'DPHY_8B10B_NOT_RESET', - 1: 'DPHY_8B10B_RESETET', -} -DPHY_8B10B_NOT_RESET = 0 -DPHY_8B10B_RESETET = 1 -DPHY_8B10B_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' -DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', -} -DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 -DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' -DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', -} -DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 -DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE0' -DPHY_ATEST_SEL_LANE0__enumvalues = { - 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE0_REG_PATTERN', -} -DPHY_ATEST_LANE0_PRBS_PATTERN = 0 -DPHY_ATEST_LANE0_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE1' -DPHY_ATEST_SEL_LANE1__enumvalues = { - 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE1_REG_PATTERN', -} -DPHY_ATEST_LANE1_PRBS_PATTERN = 0 -DPHY_ATEST_LANE1_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE2' -DPHY_ATEST_SEL_LANE2__enumvalues = { - 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE2_REG_PATTERN', -} -DPHY_ATEST_LANE2_PRBS_PATTERN = 0 -DPHY_ATEST_LANE2_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE3' -DPHY_ATEST_SEL_LANE3__enumvalues = { - 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE3_REG_PATTERN', -} -DPHY_ATEST_LANE3_PRBS_PATTERN = 0 -DPHY_ATEST_LANE3_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_BYPASS' -DPHY_BYPASS__enumvalues = { - 0: 'DPHY_8B10B_OUTPUT', - 1: 'DPHY_DBG_OUTPUT', -} -DPHY_8B10B_OUTPUT = 0 -DPHY_DBG_OUTPUT = 1 -DPHY_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_CONT_EN' -DPHY_CRC_CONT_EN__enumvalues = { - 0: 'DPHY_CRC_ONE_SHOT', - 1: 'DPHY_CRC_CONTINUOUS', -} -DPHY_CRC_ONE_SHOT = 0 -DPHY_CRC_CONTINUOUS = 1 -DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_EN' -DPHY_CRC_EN__enumvalues = { - 0: 'DPHY_CRC_DISABLED', - 1: 'DPHY_CRC_ENABLED', -} -DPHY_CRC_DISABLED = 0 -DPHY_CRC_ENABLED = 1 -DPHY_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_FIELD' -DPHY_CRC_FIELD__enumvalues = { - 0: 'DPHY_CRC_START_FROM_TOP_FIELD', - 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', -} -DPHY_CRC_START_FROM_TOP_FIELD = 0 -DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 -DPHY_CRC_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' -DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { - 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', - 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', -} -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 -DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 -DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_SEL' -DPHY_CRC_SEL__enumvalues = { - 0: 'DPHY_CRC_LANE0_SELECTED', - 1: 'DPHY_CRC_LANE1_SELECTED', - 2: 'DPHY_CRC_LANE2_SELECTED', - 3: 'DPHY_CRC_LANE3_SELECTED', -} -DPHY_CRC_LANE0_SELECTED = 0 -DPHY_CRC_LANE1_SELECTED = 1 -DPHY_CRC_LANE2_SELECTED = 2 -DPHY_CRC_LANE3_SELECTED = 3 -DPHY_CRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_ENABLE' -DPHY_FEC_ENABLE__enumvalues = { - 0: 'DPHY_FEC_DISABLED', - 1: 'DPHY_FEC_ENABLED', -} -DPHY_FEC_DISABLED = 0 -DPHY_FEC_ENABLED = 1 -DPHY_FEC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_READY' -DPHY_FEC_READY__enumvalues = { - 0: 'DPHY_FEC_READY_EN', - 1: 'DPHY_FEC_READY_DIS', -} -DPHY_FEC_READY_EN = 0 -DPHY_FEC_READY_DIS = 1 -DPHY_FEC_READY = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_LOAD_BS_COUNT_START' -DPHY_LOAD_BS_COUNT_START__enumvalues = { - 0: 'DPHY_LOAD_BS_COUNT_STARTED', - 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', -} -DPHY_LOAD_BS_COUNT_STARTED = 0 -DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 -DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_EN' -DPHY_PRBS_EN__enumvalues = { - 0: 'DPHY_PRBS_DISABLE', - 1: 'DPHY_PRBS_ENABLE', -} -DPHY_PRBS_DISABLE = 0 -DPHY_PRBS_ENABLE = 1 -DPHY_PRBS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_SEL' -DPHY_PRBS_SEL__enumvalues = { - 0: 'DPHY_PRBS7_SELECTED', - 1: 'DPHY_PRBS23_SELECTED', - 2: 'DPHY_PRBS11_SELECTED', -} -DPHY_PRBS7_SELECTED = 0 -DPHY_PRBS23_SELECTED = 1 -DPHY_PRBS11_SELECTED = 2 -DPHY_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' -DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { - 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 1: 'DPHY_FAST_TRAINING_CAPABLE', -} -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 -DPHY_FAST_TRAINING_CAPABLE = 1 -DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' -DPHY_SCRAMBLER_ADVANCE__enumvalues = { - 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', -} -DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 -DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 -DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_DIS' -DPHY_SCRAMBLER_DIS__enumvalues = { - 0: 'DPHY_SCR_ENABLED', - 1: 'DPHY_SCR_DISABLED', -} -DPHY_SCR_ENABLED = 0 -DPHY_SCR_DISABLED = 1 -DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_KCODE' -DPHY_SCRAMBLER_KCODE__enumvalues = { - 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', - 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', -} -DPHY_SCRAMBLER_KCODE_DISABLED = 0 -DPHY_SCRAMBLER_KCODE_ENABLED = 1 -DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_SEL' -DPHY_SCRAMBLER_SEL__enumvalues = { - 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', - 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', -} -DPHY_SCRAMBLER_SEL_LANE_DATA = 0 -DPHY_SCRAMBLER_SEL_DBG_DATA = 1 -DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SKEW_BYPASS' -DPHY_SKEW_BYPASS__enumvalues = { - 0: 'DPHY_WITH_SKEW', - 1: 'DPHY_NO_SKEW', -} -DPHY_WITH_SKEW = 0 -DPHY_NO_SKEW = 1 -DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { - 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', -} -DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SW_FAST_TRAINING_START' -DPHY_SW_FAST_TRAINING_START__enumvalues = { - 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 1: 'DPHY_SW_FAST_TRAINING_STARTED', -} -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 -DPHY_SW_FAST_TRAINING_STARTED = 1 -DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' -DPHY_TRAINING_PATTERN_SEL__enumvalues = { - 0: 'DPHY_TRAINING_PATTERN_1', - 1: 'DPHY_TRAINING_PATTERN_2', - 2: 'DPHY_TRAINING_PATTERN_3', - 3: 'DPHY_TRAINING_PATTERN_4', -} -DPHY_TRAINING_PATTERN_1 = 0 -DPHY_TRAINING_PATTERN_2 = 1 -DPHY_TRAINING_PATTERN_3 = 2 -DPHY_TRAINING_PATTERN_4 = 3 -DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPONENT_DEPTH' -DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_COMPONENT_DEPTH_6BPC', - 1: 'DP_COMPONENT_DEPTH_8BPC', - 2: 'DP_COMPONENT_DEPTH_10BPC', - 3: 'DP_COMPONENT_DEPTH_12BPC', - 4: 'DP_COMPONENT_DEPTH_16BPC', -} -DP_COMPONENT_DEPTH_6BPC = 0 -DP_COMPONENT_DEPTH_8BPC = 1 -DP_COMPONENT_DEPTH_10BPC = 2 -DP_COMPONENT_DEPTH_12BPC = 3 -DP_COMPONENT_DEPTH_16BPC = 4 -DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DP_CP_ENCRYPTION_TYPE' -DP_CP_ENCRYPTION_TYPE__enumvalues = { - 0: 'DP_CP_ENCRYPTION_TYPE_0', - 1: 'DP_CP_ENCRYPTION_TYPE_1', -} -DP_CP_ENCRYPTION_TYPE_0 = 0 -DP_CP_ENCRYPTION_TYPE_1 = 1 -DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' -DP_DPHY_8B10B_EXT_DISP__enumvalues = { - 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', -} -DP_DPHY_8B10B_EXT_DISP_ZERO = 0 -DP_DPHY_8B10B_EXT_DISP_ONE = 1 -DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' -DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' -DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', -} -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' -DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { - 0: 'DP_DPHY_HBR2_PASS_THROUGH', - 1: 'DP_DPHY_HBR2_PATTERN_1', - 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', - 3: 'DP_DPHY_HBR2_PATTERN_3', - 6: 'DP_DPHY_HBR2_PATTERN_2_POS', -} -DP_DPHY_HBR2_PASS_THROUGH = 0 -DP_DPHY_HBR2_PATTERN_1 = 1 -DP_DPHY_HBR2_PATTERN_2_NEG = 2 -DP_DPHY_HBR2_PATTERN_3 = 3 -DP_DPHY_HBR2_PATTERN_2_POS = 6 -DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DSC_MODE' -DP_DSC_MODE__enumvalues = { - 0: 'DP_DSC_DISABLE', - 1: 'DP_DSC_444_SIMPLE_422', - 2: 'DP_DSC_NATIVE_422_420', -} -DP_DSC_DISABLE = 0 -DP_DSC_444_SIMPLE_422 = 1 -DP_DSC_NATIVE_422_420 = 2 -DP_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_EMBEDDED_PANEL_MODE' -DP_EMBEDDED_PANEL_MODE__enumvalues = { - 0: 'DP_EXTERNAL_PANEL', - 1: 'DP_EMBEDDED_PANEL', -} -DP_EXTERNAL_PANEL = 0 -DP_EMBEDDED_PANEL = 1 -DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_COMPLETE' -DP_LINK_TRAINING_COMPLETE__enumvalues = { - 0: 'DP_LINK_TRAINING_NOT_COMPLETE', - 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', -} -DP_LINK_TRAINING_NOT_COMPLETE = 0 -DP_LINK_TRAINING_ALREADY_COMPLETE = 1 -DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' -DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { - 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', -} -DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 -DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 -DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_ML_PHY_SEQ_MODE' -DP_ML_PHY_SEQ_MODE__enumvalues = { - 0: 'DP_ML_PHY_SEQ_LINE_NUM', - 1: 'DP_ML_PHY_SEQ_IMMEDIATE', -} -DP_ML_PHY_SEQ_LINE_NUM = 0 -DP_ML_PHY_SEQ_IMMEDIATE = 1 -DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' -DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { - 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', - 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', -} -MSA_V_TIMING_OVERRIDE_DISABLED = 0 -MSA_V_TIMING_OVERRIDE_ENABLED = 1 -DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_BLANK_CODE' -DP_MSE_BLANK_CODE__enumvalues = { - 0: 'DP_MSE_BLANK_CODE_SF_FILLED', - 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', -} -DP_MSE_BLANK_CODE_SF_FILLED = 0 -DP_MSE_BLANK_CODE_ZERO_FILLED = 1 -DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_LINK_LINE' -DP_MSE_LINK_LINE__enumvalues = { - 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', - 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', - 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', - 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', -} -DP_MSE_LINK_LINE_32_MTP_LONG = 0 -DP_MSE_LINK_LINE_64_MTP_LONG = 1 -DP_MSE_LINK_LINE_128_MTP_LONG = 2 -DP_MSE_LINK_LINE_256_MTP_LONG = 3 -DP_MSE_LINK_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT0' -DP_MSE_SAT_ENCRYPT0__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT0_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT0_ENABLED', -} -DP_MSE_SAT_ENCRYPT0_DISABLED = 0 -DP_MSE_SAT_ENCRYPT0_ENABLED = 1 -DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT1' -DP_MSE_SAT_ENCRYPT1__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT1_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT1_ENABLED', -} -DP_MSE_SAT_ENCRYPT1_DISABLED = 0 -DP_MSE_SAT_ENCRYPT1_ENABLED = 1 -DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT2' -DP_MSE_SAT_ENCRYPT2__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT2_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT2_ENABLED', -} -DP_MSE_SAT_ENCRYPT2_DISABLED = 0 -DP_MSE_SAT_ENCRYPT2_ENABLED = 1 -DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT3' -DP_MSE_SAT_ENCRYPT3__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT3_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT3_ENABLED', -} -DP_MSE_SAT_ENCRYPT3_DISABLED = 0 -DP_MSE_SAT_ENCRYPT3_ENABLED = 1 -DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT4' -DP_MSE_SAT_ENCRYPT4__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT4_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT4_ENABLED', -} -DP_MSE_SAT_ENCRYPT4_DISABLED = 0 -DP_MSE_SAT_ENCRYPT4_ENABLED = 1 -DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT5' -DP_MSE_SAT_ENCRYPT5__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT5_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT5_ENABLED', -} -DP_MSE_SAT_ENCRYPT5_DISABLED = 0 -DP_MSE_SAT_ENCRYPT5_ENABLED = 1 -DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' -DP_MSE_SAT_UPDATE_ACT__enumvalues = { - 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', - 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', -} -DP_MSE_SAT_UPDATE_NO_ACTION = 0 -DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 -DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 -DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_TIMESTAMP_MODE' -DP_MSE_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', -} -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 -DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_ZERO_ENCODER' -DP_MSE_ZERO_ENCODER__enumvalues = { - 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', - 1: 'DP_MSE_ZERO_FE_ENCODER', -} -DP_MSE_NOT_ZERO_FE_ENCODER = 0 -DP_MSE_ZERO_FE_ENCODER = 1 -DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' -DP_MSO_NUM_OF_SST_LINKS__enumvalues = { - 0: 'DP_MSO_ONE_SSTLINK', - 1: 'DP_MSO_TWO_SSTLINK', - 2: 'DP_MSO_FOUR_SSTLINK', -} -DP_MSO_ONE_SSTLINK = 0 -DP_MSO_TWO_SSTLINK = 1 -DP_MSO_FOUR_SSTLINK = 2 -DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING' -DP_PIXEL_ENCODING__enumvalues = { - 0: 'DP_PIXEL_ENCODING_RGB444', - 1: 'DP_PIXEL_ENCODING_YCBCR422', - 2: 'DP_PIXEL_ENCODING_YCBCR444', - 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 4: 'DP_PIXEL_ENCODING_Y_ONLY', - 5: 'DP_PIXEL_ENCODING_YCBCR420', -} -DP_PIXEL_ENCODING_RGB444 = 0 -DP_PIXEL_ENCODING_YCBCR422 = 1 -DP_PIXEL_ENCODING_YCBCR444 = 2 -DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 -DP_PIXEL_ENCODING_Y_ONLY = 4 -DP_PIXEL_ENCODING_YCBCR420 = 5 -DP_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM' -DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = { - 0: 'DP_ONE_PIXEL_PER_CYCLE', - 1: 'DP_TWO_PIXEL_PER_CYCLE', -} -DP_ONE_PIXEL_PER_CYCLE = 0 -DP_TWO_PIXEL_PER_CYCLE = 1 -DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_PRIORITY' -DP_SEC_ASP_PRIORITY__enumvalues = { - 0: 'DP_SEC_ASP_LOW_PRIORITY', - 1: 'DP_SEC_ASP_HIGH_PRIORITY', -} -DP_SEC_ASP_LOW_PRIORITY = 0 -DP_SEC_ASP_HIGH_PRIORITY = 1 -DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_AUDIO_MUTE' -DP_SEC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', - 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', -} -DP_SEC_AUDIO_MUTE_HW_CTRL = 0 -DP_SEC_AUDIO_MUTE_SW_CTRL = 1 -DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_COLLISION_ACK' -DP_SEC_COLLISION_ACK__enumvalues = { - 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', - 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', -} -DP_SEC_COLLISION_ACK_NO_EFFECT = 0 -DP_SEC_COLLISION_ACK_CLR_FLAG = 1 -DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_PRIORITY' -DP_SEC_GSP0_PRIORITY__enumvalues = { - 0: 'SEC_GSP0_PRIORITY_LOW', - 1: 'SEC_GSP0_PRIORITY_HIGH', -} -SEC_GSP0_PRIORITY_LOW = 0 -SEC_GSP0_PRIORITY_HIGH = 1 -DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND' -DP_SEC_GSP_SEND__enumvalues = { - 0: 'NOT_SENT', - 1: 'FORCE_SENT', -} -NOT_SENT = 0 -FORCE_SENT = 1 -DP_SEC_GSP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' -DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { - 0: 'SEND_AT_LINK_NUMBER', - 1: 'SEND_AT_EARLIEST_TIME', -} -SEND_AT_LINK_NUMBER = 0 -SEND_AT_EARLIEST_TIME = 1 -DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_PPS' -DP_SEC_GSP_SEND_PPS__enumvalues = { - 0: 'SEND_NORMAL_PACKET', - 1: 'SEND_PPS_PACKET', -} -SEND_NORMAL_PACKET = 0 -SEND_PPS_PACKET = 1 -DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_LINE_REFERENCE' -DP_SEC_LINE_REFERENCE__enumvalues = { - 0: 'REFER_TO_DP_SOF', - 1: 'REFER_TO_OTG_SOF', -} -REFER_TO_DP_SOF = 0 -REFER_TO_OTG_SOF = 1 -DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_TIMESTAMP_MODE' -DP_SEC_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', -} -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 -DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_ACK' -DP_STEER_OVERFLOW_ACK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_MASK' -DP_STEER_OVERFLOW_MASK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_MASKED', - 1: 'DP_STEER_OVERFLOW_UNMASK', -} -DP_STEER_OVERFLOW_MASKED = 0 -DP_STEER_OVERFLOW_UNMASK = 1 -DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SYNC_POLARITY' -DP_SYNC_POLARITY__enumvalues = { - 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', - 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', -} -DP_SYNC_POLARITY_ACTIVE_HIGH = 0 -DP_SYNC_POLARITY_ACTIVE_LOW = 1 -DP_SYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_TU_OVERFLOW_ACK' -DP_TU_OVERFLOW_ACK__enumvalues = { - 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_UDI_LANES' -DP_UDI_LANES__enumvalues = { - 0: 'DP_UDI_1_LANE', - 1: 'DP_UDI_2_LANES', - 2: 'DP_UDI_LANES_RESERVED', - 3: 'DP_UDI_4_LANES', -} -DP_UDI_1_LANE = 0 -DP_UDI_2_LANES = 1 -DP_UDI_LANES_RESERVED = 2 -DP_UDI_4_LANES = 3 -DP_UDI_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' -DP_VID_ENHANCED_FRAME_MODE__enumvalues = { - 0: 'VID_NORMAL_FRAME_MODE', - 1: 'VID_ENHANCED_MODE', -} -VID_NORMAL_FRAME_MODE = 0 -VID_ENHANCED_MODE = 1 -DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' -DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { - 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', -} -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 -DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_GEN_EN' -DP_VID_M_N_GEN_EN__enumvalues = { - 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', - 1: 'DP_VID_M_N_CALC_AUTO', -} -DP_VID_M_N_PROGRAMMED_VIA_REG = 0 -DP_VID_M_N_CALC_AUTO = 1 -DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_N_MUL' -DP_VID_N_MUL__enumvalues = { - 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', - 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', -} -DP_VID_M_1X_INPUT_PIXEL_RATE = 0 -DP_VID_M_2X_INPUT_PIXEL_RATE = 1 -DP_VID_M_4X_INPUT_PIXEL_RATE = 2 -DP_VID_M_8X_INPUT_PIXEL_RATE = 3 -DP_VID_N_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' -DP_VID_STREAM_DISABLE_ACK__enumvalues = { - 0: 'ID_STREAM_DISABLE_NO_ACK', - 1: 'ID_STREAM_DISABLE_ACKED', -} -ID_STREAM_DISABLE_NO_ACK = 0 -ID_STREAM_DISABLE_ACKED = 1 -DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' -DP_VID_STREAM_DISABLE_MASK__enumvalues = { - 0: 'VID_STREAM_DISABLE_MASKED', - 1: 'VID_STREAM_DISABLE_UNMASK', -} -VID_STREAM_DISABLE_MASKED = 0 -VID_STREAM_DISABLE_UNMASK = 1 -DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DIS_DEFER' -DP_VID_STREAM_DIS_DEFER__enumvalues = { - 0: 'DP_VID_STREAM_DIS_NO_DEFER', - 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', -} -DP_VID_STREAM_DIS_NO_DEFER = 0 -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 -DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_VBID_FIELD_POL' -DP_VID_VBID_FIELD_POL__enumvalues = { - 0: 'DP_VID_VBID_FIELD_POL_NORMAL', - 1: 'DP_VID_VBID_FIELD_POL_INV', -} -DP_VID_VBID_FIELD_POL_NORMAL = 0 -DP_VID_VBID_FIELD_POL_INV = 1 -DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum - -# values for enumeration 'FEC_ACTIVE_STATUS' -FEC_ACTIVE_STATUS__enumvalues = { - 0: 'DPHY_FEC_NOT_ACTIVE', - 1: 'DPHY_FEC_ACTIVE', -} -DPHY_FEC_NOT_ACTIVE = 0 -DPHY_FEC_ACTIVE = 1 -FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' -DIG_BE_CNTL_HPD_SELECT__enumvalues = { - 0: 'DIG_BE_CNTL_HPD1', - 1: 'DIG_BE_CNTL_HPD2', - 2: 'DIG_BE_CNTL_HPD3', - 3: 'DIG_BE_CNTL_HPD4', - 4: 'DIG_BE_CNTL_HPD5', - 5: 'DIG_BE_CNTL_NO_HPD', -} -DIG_BE_CNTL_HPD1 = 0 -DIG_BE_CNTL_HPD2 = 1 -DIG_BE_CNTL_HPD3 = 2 -DIG_BE_CNTL_HPD4 = 3 -DIG_BE_CNTL_HPD5 = 4 -DIG_BE_CNTL_NO_HPD = 5 -DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_MODE' -DIG_BE_CNTL_MODE__enumvalues = { - 0: 'DIG_BE_DP_SST_MODE', - 1: 'DIG_BE_RESERVED1', - 2: 'DIG_BE_TMDS_DVI_MODE', - 3: 'DIG_BE_TMDS_HDMI_MODE', - 4: 'DIG_BE_RESERVED4', - 5: 'DIG_BE_DP_MST_MODE', - 6: 'DIG_BE_RESERVED2', - 7: 'DIG_BE_RESERVED3', -} -DIG_BE_DP_SST_MODE = 0 -DIG_BE_RESERVED1 = 1 -DIG_BE_TMDS_DVI_MODE = 2 -DIG_BE_TMDS_HDMI_MODE = 3 -DIG_BE_RESERVED4 = 4 -DIG_BE_DP_MST_MODE = 5 -DIG_BE_RESERVED2 = 6 -DIG_BE_RESERVED3 = 7 -DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' -DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_OFF', - 1: 'DIG_DIGITAL_BYPASS_ON', -} -DIG_DIGITAL_BYPASS_OFF = 0 -DIG_DIGITAL_BYPASS_ON = 1 -DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' -DIG_DIGITAL_BYPASS_SEL__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', -} -DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 -DIG_DIGITAL_BYPASS_SEL_36BPP = 1 -DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 -DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 -DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 -DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 -DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 -DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' -DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { - 0: 'DIG_FE_SOURCE_FROM_OTG0', - 1: 'DIG_FE_SOURCE_FROM_OTG1', - 2: 'DIG_FE_SOURCE_FROM_OTG2', - 3: 'DIG_FE_SOURCE_FROM_OTG3', - 4: 'DIG_FE_SOURCE_RESERVED', -} -DIG_FE_SOURCE_FROM_OTG0 = 0 -DIG_FE_SOURCE_FROM_OTG1 = 1 -DIG_FE_SOURCE_FROM_OTG2 = 2 -DIG_FE_SOURCE_FROM_OTG3 = 3 -DIG_FE_SOURCE_RESERVED = 4 -DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' -DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { - 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', - 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', - 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', - 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', - 4: 'DIG_FE_STEREOSYNC_RESERVED', -} -DIG_FE_STEREOSYNC_FROM_OTG0 = 0 -DIG_FE_STEREOSYNC_FROM_OTG1 = 1 -DIG_FE_STEREOSYNC_FROM_OTG2 = 2 -DIG_FE_STEREOSYNC_FROM_OTG3 = 3 -DIG_FE_STEREOSYNC_RESERVED = 4 -DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', - 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', -} -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 -DIG_FIFO_FORCE_RECOMP_MINMAX = 1 -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', -} -DIG_FIFO_USE_OVERWRITE_LEVEL = 0 -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' -DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', -} -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 -DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE' -DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = { - 0: 'DIG_FIFO_1_PIX_PER_CYCLE', - 1: 'DIG_FIFO_2_PIX_PER_CYCLE', -} -DIG_FIFO_1_PIX_PER_CYCLE = 0 -DIG_FIFO_2_PIX_PER_CYCLE = 1 -DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DIG_FIFO_NO_ERROR_OCCURRED', - 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', - 2: 'DIG_FIFO_OVERFLOW_OCCURRED', -} -DIG_FIFO_NO_ERROR_OCCURRED = 0 -DIG_FIFO_UNDERFLOW_OCCURRED = 1 -DIG_FIFO_OVERFLOW_OCCURRED = 2 -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' -DIG_FIFO_READ_CLOCK_SRC__enumvalues = { - 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', -} -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 -DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_INPUT_PIXEL_SEL' -DIG_INPUT_PIXEL_SEL__enumvalues = { - 0: 'DIG_ALL_PIXEL', - 1: 'DIG_EVEN_PIXEL_ONLY', - 2: 'DIG_ODD_PIXEL_ONLY', -} -DIG_ALL_PIXEL = 0 -DIG_EVEN_PIXEL_ONLY = 1 -DIG_ODD_PIXEL_ONLY = 2 -DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' -DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_ON_LINK0', - 1: 'DIG_OUTPUT_CRC_ON_LINK1', -} -DIG_OUTPUT_CRC_ON_LINK0 = 0 -DIG_OUTPUT_CRC_ON_LINK1 = 1 -DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' -DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 2: 'DIG_OUTPUT_CRC_FOR_VBI', - 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', -} -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 -DIG_OUTPUT_CRC_FOR_VBI = 2 -DIG_OUTPUT_CRC_FOR_AUDIO = 3 -DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' -DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', -} -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 -DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_SL_PIXEL_GROUPING' -DIG_SL_PIXEL_GROUPING__enumvalues = { - 0: 'DIG_SINGLETON_PIXELS', - 1: 'DIG_PAIR_PIXELS', -} -DIG_SINGLETON_PIXELS = 0 -DIG_PAIR_PIXELS = 1 -DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' -DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', -} -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 -DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { - 0: 'DIG_10BIT_TEST_PATTERN', - 1: 'DIG_ALTERNATING_TEST_PATTERN', -} -DIG_10BIT_TEST_PATTERN = 0 -DIG_ALTERNATING_TEST_PATTERN = 1 -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_NORMAL', - 1: 'DIG_TEST_PATTERN_RANDOM', -} -DIG_TEST_PATTERN_NORMAL = 0 -DIG_TEST_PATTERN_RANDOM = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_ENABLED', - 1: 'DIG_RANDOM_PATTERN_RESETED', -} -DIG_RANDOM_PATTERN_ENABLED = 0 -DIG_RANDOM_PATTERN_RESETED = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_IN_NORMAL_OPERATION', - 1: 'DIG_IN_DEBUG_MODE', -} -DIG_IN_NORMAL_OPERATION = 0 -DIG_IN_DEBUG_MODE = 1 -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOLBY_VISION_ENABLE' -DOLBY_VISION_ENABLE__enumvalues = { - 0: 'DOLBY_VISION_DISABLED', - 1: 'DOLBY_VISION_ENABLED', -} -DOLBY_VISION_DISABLED = 0 -DOLBY_VISION_ENABLED = 1 -DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACP_SEND' -HDMI_ACP_SEND__enumvalues = { - 0: 'HDMI_ACP_NOT_SEND', - 1: 'HDMI_ACP_PKT_SEND', -} -HDMI_ACP_NOT_SEND = 0 -HDMI_ACP_PKT_SEND = 1 -HDMI_ACP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' -HDMI_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_CONT' -HDMI_ACR_CONT__enumvalues = { - 0: 'HDMI_ACR_CONT_DISABLE', - 1: 'HDMI_ACR_CONT_ENABLE', -} -HDMI_ACR_CONT_DISABLE = 0 -HDMI_ACR_CONT_ENABLE = 1 -HDMI_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_N_MULTIPLE' -HDMI_ACR_N_MULTIPLE__enumvalues = { - 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', - 1: 'HDMI_ACR_1_MULTIPLE', - 2: 'HDMI_ACR_2_MULTIPLE', - 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', - 4: 'HDMI_ACR_4_MULTIPLE', - 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', - 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', - 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', -} -HDMI_ACR_0_MULTIPLE_RESERVED = 0 -HDMI_ACR_1_MULTIPLE = 1 -HDMI_ACR_2_MULTIPLE = 2 -HDMI_ACR_3_MULTIPLE_RESERVED = 3 -HDMI_ACR_4_MULTIPLE = 4 -HDMI_ACR_5_MULTIPLE_RESERVED = 5 -HDMI_ACR_6_MULTIPLE_RESERVED = 6 -HDMI_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SELECT' -HDMI_ACR_SELECT__enumvalues = { - 0: 'HDMI_ACR_SELECT_HW', - 1: 'HDMI_ACR_SELECT_32K', - 2: 'HDMI_ACR_SELECT_44K', - 3: 'HDMI_ACR_SELECT_48K', -} -HDMI_ACR_SELECT_HW = 0 -HDMI_ACR_SELECT_32K = 1 -HDMI_ACR_SELECT_44K = 2 -HDMI_ACR_SELECT_48K = 3 -HDMI_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SEND' -HDMI_ACR_SEND__enumvalues = { - 0: 'HDMI_ACR_NOT_SEND', - 1: 'HDMI_ACR_PKT_SEND', -} -HDMI_ACR_NOT_SEND = 0 -HDMI_ACR_PKT_SEND = 1 -HDMI_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SOURCE' -HDMI_ACR_SOURCE__enumvalues = { - 0: 'HDMI_ACR_SOURCE_HW', - 1: 'HDMI_ACR_SOURCE_SW', -} -HDMI_ACR_SOURCE_HW = 0 -HDMI_ACR_SOURCE_SW = 1 -HDMI_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_DELAY_EN' -HDMI_AUDIO_DELAY_EN__enumvalues = { - 0: 'HDMI_AUDIO_DELAY_DISABLE', - 1: 'HDMI_AUDIO_DELAY_58CLK', - 2: 'HDMI_AUDIO_DELAY_56CLK', - 3: 'HDMI_AUDIO_DELAY_RESERVED', -} -HDMI_AUDIO_DELAY_DISABLE = 0 -HDMI_AUDIO_DELAY_58CLK = 1 -HDMI_AUDIO_DELAY_56CLK = 2 -HDMI_AUDIO_DELAY_RESERVED = 3 -HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_CONT' -HDMI_AUDIO_INFO_CONT__enumvalues = { - 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', - 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', -} -HDMI_AUDIO_INFO_CONT_DISABLE = 0 -HDMI_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_SEND' -HDMI_AUDIO_INFO_SEND__enumvalues = { - 0: 'HDMI_AUDIO_INFO_NOT_SEND', - 1: 'HDMI_AUDIO_INFO_PKT_SEND', -} -HDMI_AUDIO_INFO_NOT_SEND = 0 -HDMI_AUDIO_INFO_PKT_SEND = 1 -HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' -HDMI_CLOCK_CHANNEL_RATE__enumvalues = { - 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', -} -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 -HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' -HDMI_DATA_SCRAMBLE_EN__enumvalues = { - 0: 'HDMI_DATA_SCRAMBLE_DISABLE', - 1: 'HDMI_DATA_SCRAMBLE_ENABLE', -} -HDMI_DATA_SCRAMBLE_DISABLE = 0 -HDMI_DATA_SCRAMBLE_ENABLE = 1 -HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' -HDMI_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', -} -HDMI_DEEP_COLOR_DEPTH_24BPP = 0 -HDMI_DEEP_COLOR_DEPTH_30BPP = 1 -HDMI_DEEP_COLOR_DEPTH_36BPP = 2 -HDMI_DEEP_COLOR_DEPTH_48BPP = 3 -HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEFAULT_PAHSE' -HDMI_DEFAULT_PAHSE__enumvalues = { - 0: 'HDMI_DEFAULT_PHASE_IS_0', - 1: 'HDMI_DEFAULT_PHASE_IS_1', -} -HDMI_DEFAULT_PHASE_IS_0 = 0 -HDMI_DEFAULT_PHASE_IS_1 = 1 -HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_ACK' -HDMI_ERROR_ACK__enumvalues = { - 0: 'HDMI_ERROR_ACK_INT', - 1: 'HDMI_ERROR_NOT_ACK', -} -HDMI_ERROR_ACK_INT = 0 -HDMI_ERROR_NOT_ACK = 1 -HDMI_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_MASK' -HDMI_ERROR_MASK__enumvalues = { - 0: 'HDMI_ERROR_MASK_INT', - 1: 'HDMI_ERROR_NOT_MASK', -} -HDMI_ERROR_MASK_INT = 0 -HDMI_ERROR_NOT_MASK = 1 -HDMI_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE' -HDMI_GC_AVMUTE__enumvalues = { - 0: 'HDMI_GC_AVMUTE_SET', - 1: 'HDMI_GC_AVMUTE_UNSET', -} -HDMI_GC_AVMUTE_SET = 0 -HDMI_GC_AVMUTE_UNSET = 1 -HDMI_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE_CONT' -HDMI_GC_AVMUTE_CONT__enumvalues = { - 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', - 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', -} -HDMI_GC_AVMUTE_CONT_DISABLE = 0 -HDMI_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_CONT' -HDMI_GC_CONT__enumvalues = { - 0: 'HDMI_GC_CONT_DISABLE', - 1: 'HDMI_GC_CONT_ENABLE', -} -HDMI_GC_CONT_DISABLE = 0 -HDMI_GC_CONT_ENABLE = 1 -HDMI_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_SEND' -HDMI_GC_SEND__enumvalues = { - 0: 'HDMI_GC_NOT_SEND', - 1: 'HDMI_GC_PKT_SEND', -} -HDMI_GC_NOT_SEND = 0 -HDMI_GC_PKT_SEND = 1 -HDMI_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_CONT' -HDMI_GENERIC_CONT__enumvalues = { - 0: 'HDMI_GENERIC_CONT_DISABLE', - 1: 'HDMI_GENERIC_CONT_ENABLE', -} -HDMI_GENERIC_CONT_DISABLE = 0 -HDMI_GENERIC_CONT_ENABLE = 1 -HDMI_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_SEND' -HDMI_GENERIC_SEND__enumvalues = { - 0: 'HDMI_GENERIC_NOT_SEND', - 1: 'HDMI_GENERIC_PKT_SEND', -} -HDMI_GENERIC_NOT_SEND = 0 -HDMI_GENERIC_PKT_SEND = 1 -HDMI_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_CONT' -HDMI_ISRC_CONT__enumvalues = { - 0: 'HDMI_ISRC_CONT_DISABLE', - 1: 'HDMI_ISRC_CONT_ENABLE', -} -HDMI_ISRC_CONT_DISABLE = 0 -HDMI_ISRC_CONT_ENABLE = 1 -HDMI_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_SEND' -HDMI_ISRC_SEND__enumvalues = { - 0: 'HDMI_ISRC_NOT_SEND', - 1: 'HDMI_ISRC_PKT_SEND', -} -HDMI_ISRC_NOT_SEND = 0 -HDMI_ISRC_PKT_SEND = 1 -HDMI_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_KEEPOUT_MODE' -HDMI_KEEPOUT_MODE__enumvalues = { - 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', -} -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 -HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_METADATA_ENABLE' -HDMI_METADATA_ENABLE__enumvalues = { - 0: 'HDMI_METADATA_NOT_SEND', - 1: 'HDMI_METADATA_PKT_SEND', -} -HDMI_METADATA_NOT_SEND = 0 -HDMI_METADATA_PKT_SEND = 1 -HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_CONT' -HDMI_MPEG_INFO_CONT__enumvalues = { - 0: 'HDMI_MPEG_INFO_CONT_DISABLE', - 1: 'HDMI_MPEG_INFO_CONT_ENABLE', -} -HDMI_MPEG_INFO_CONT_DISABLE = 0 -HDMI_MPEG_INFO_CONT_ENABLE = 1 -HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_SEND' -HDMI_MPEG_INFO_SEND__enumvalues = { - 0: 'HDMI_MPEG_INFO_NOT_SEND', - 1: 'HDMI_MPEG_INFO_PKT_SEND', -} -HDMI_MPEG_INFO_NOT_SEND = 0 -HDMI_MPEG_INFO_PKT_SEND = 1 -HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' -HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { - 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', - 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', -} -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 -HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NULL_SEND' -HDMI_NULL_SEND__enumvalues = { - 0: 'HDMI_NULL_NOT_SEND', - 1: 'HDMI_NULL_PKT_SEND', -} -HDMI_NULL_NOT_SEND = 0 -HDMI_NULL_PKT_SEND = 1 -HDMI_NULL_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_GEN_VERSION' -HDMI_PACKET_GEN_VERSION__enumvalues = { - 0: 'HDMI_PACKET_GEN_VERSION_OLD', - 1: 'HDMI_PACKET_GEN_VERSION_NEW', -} -HDMI_PACKET_GEN_VERSION_OLD = 0 -HDMI_PACKET_GEN_VERSION_NEW = 1 -HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' -HDMI_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'HDMI_PKT_LINE_REF_VSYNC', - 1: 'HDMI_PKT_LINE_REF_OTGSOF', -} -HDMI_PKT_LINE_REF_VSYNC = 0 -HDMI_PKT_LINE_REF_OTGSOF = 1 -HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' -HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { - 0: 'HDMI_PACKING_PHASE_SET_BY_HW', - 1: 'HDMI_PACKING_PHASE_SET_BY_SW', -} -HDMI_PACKING_PHASE_SET_BY_HW = 0 -HDMI_PACKING_PHASE_SET_BY_SW = 1 -HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', -} -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_COLOR_FORMAT' -TMDS_COLOR_FORMAT__enumvalues = { - 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', - 3: 'TMDS_COLOR_FORMAT_RESERVED', -} -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 -TMDS_COLOR_FORMAT_DUAL30BPP = 2 -TMDS_COLOR_FORMAT_RESERVED = 3 -TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_INVERT' -TMDS_CTL0_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL0_DATA_NORMAL', - 1: 'TMDS_CTL0_DATA_INVERT_EN', -} -TMDS_CTL0_DATA_NORMAL = 0 -TMDS_CTL0_DATA_INVERT_EN = 1 -TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_MODULATION' -TMDS_CTL0_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', -} -TMDS_CTL0_DATA_MODULATION_DISABLE = 0 -TMDS_CTL0_DATA_MODULATION_BIT0 = 1 -TMDS_CTL0_DATA_MODULATION_BIT1 = 2 -TMDS_CTL0_DATA_MODULATION_BIT2 = 3 -TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_SEL' -TMDS_CTL0_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', -} -TMDS_CTL0_DATA_SEL0_RESERVED = 0 -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL0_DATA_SEL2_VSYNC = 2 -TMDS_CTL0_DATA_SEL3_RESERVED = 3 -TMDS_CTL0_DATA_SEL4_HSYNC = 4 -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 -TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' -TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', -} -TMDS_CTL0_PATTERN_OUT_DISABLE = 0 -TMDS_CTL0_PATTERN_OUT_ENABLE = 1 -TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_INVERT' -TMDS_CTL1_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL1_DATA_NORMAL', - 1: 'TMDS_CTL1_DATA_INVERT_EN', -} -TMDS_CTL1_DATA_NORMAL = 0 -TMDS_CTL1_DATA_INVERT_EN = 1 -TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_MODULATION' -TMDS_CTL1_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', -} -TMDS_CTL1_DATA_MODULATION_DISABLE = 0 -TMDS_CTL1_DATA_MODULATION_BIT0 = 1 -TMDS_CTL1_DATA_MODULATION_BIT1 = 2 -TMDS_CTL1_DATA_MODULATION_BIT2 = 3 -TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_SEL' -TMDS_CTL1_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL1_DATA_SEL0_RESERVED = 0 -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL1_DATA_SEL2_VSYNC = 2 -TMDS_CTL1_DATA_SEL3_RESERVED = 3 -TMDS_CTL1_DATA_SEL4_HSYNC = 4 -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' -TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', -} -TMDS_CTL1_PATTERN_OUT_DISABLE = 0 -TMDS_CTL1_PATTERN_OUT_ENABLE = 1 -TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_INVERT' -TMDS_CTL2_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL2_DATA_NORMAL', - 1: 'TMDS_CTL2_DATA_INVERT_EN', -} -TMDS_CTL2_DATA_NORMAL = 0 -TMDS_CTL2_DATA_INVERT_EN = 1 -TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_MODULATION' -TMDS_CTL2_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', -} -TMDS_CTL2_DATA_MODULATION_DISABLE = 0 -TMDS_CTL2_DATA_MODULATION_BIT0 = 1 -TMDS_CTL2_DATA_MODULATION_BIT1 = 2 -TMDS_CTL2_DATA_MODULATION_BIT2 = 3 -TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_SEL' -TMDS_CTL2_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL2_DATA_SEL0_RESERVED = 0 -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL2_DATA_SEL2_VSYNC = 2 -TMDS_CTL2_DATA_SEL3_RESERVED = 3 -TMDS_CTL2_DATA_SEL4_HSYNC = 4 -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' -TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', -} -TMDS_CTL2_PATTERN_OUT_DISABLE = 0 -TMDS_CTL2_PATTERN_OUT_ENABLE = 1 -TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_INVERT' -TMDS_CTL3_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL3_DATA_NORMAL', - 1: 'TMDS_CTL3_DATA_INVERT_EN', -} -TMDS_CTL3_DATA_NORMAL = 0 -TMDS_CTL3_DATA_INVERT_EN = 1 -TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_MODULATION' -TMDS_CTL3_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', -} -TMDS_CTL3_DATA_MODULATION_DISABLE = 0 -TMDS_CTL3_DATA_MODULATION_BIT0 = 1 -TMDS_CTL3_DATA_MODULATION_BIT1 = 2 -TMDS_CTL3_DATA_MODULATION_BIT2 = 3 -TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_SEL' -TMDS_CTL3_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL3_DATA_SEL0_RESERVED = 0 -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL3_DATA_SEL2_VSYNC = 2 -TMDS_CTL3_DATA_SEL3_RESERVED = 3 -TMDS_CTL3_DATA_SEL4_HSYNC = 4 -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' -TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', -} -TMDS_CTL3_PATTERN_OUT_DISABLE = 0 -TMDS_CTL3_PATTERN_OUT_ENABLE = 1 -TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' -TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { - 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', -} -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_PIXEL_ENCODING' -TMDS_PIXEL_ENCODING__enumvalues = { - 0: 'TMDS_PIXEL_ENCODING_444_OR_420', - 1: 'TMDS_PIXEL_ENCODING_422', -} -TMDS_PIXEL_ENCODING_444_OR_420 = 0 -TMDS_PIXEL_ENCODING_422 = 1 -TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' -TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', -} -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 -TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' -TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', - 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', -} -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 -TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' -TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { - 0: 'TMDS_STEREOSYNC_CTL0', - 1: 'TMDS_STEREOSYNC_CTL1', - 2: 'TMDS_STEREOSYNC_CTL2', - 3: 'TMDS_STEREOSYNC_CTL3', -} -TMDS_STEREOSYNC_CTL0 = 0 -TMDS_STEREOSYNC_CTL1 = 1 -TMDS_STEREOSYNC_CTL2 = 2 -TMDS_STEREOSYNC_CTL3 = 3 -TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_SYNC_PHASE' -TMDS_SYNC_PHASE__enumvalues = { - 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', -} -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TMDS_SYNC_PHASE_ON_FRAME_START = 1 -TMDS_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' -TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' -TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', -} -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', -} -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', -} -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', -} -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' -DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', -} -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 -DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', -} -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', -} -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_STATUS' -DP_AUX_ARB_STATUS__enumvalues = { - 0: 'DP_AUX_IDLE', - 1: 'DP_AUX_IN_USE_LS', - 2: 'DP_AUX_IN_USE_GTC', - 3: 'DP_AUX_IN_USE_SW', - 4: 'DP_AUX_IN_USE_PHYWAKE', -} -DP_AUX_IDLE = 0 -DP_AUX_IN_USE_LS = 1 -DP_AUX_IN_USE_GTC = 2 -DP_AUX_IN_USE_SW = 3 -DP_AUX_IN_USE_PHYWAKE = 4 -DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' -DP_AUX_CONTROL_HPD_SEL__enumvalues = { - 0: 'DP_AUX_CONTROL_HPD1_SELECTED', - 1: 'DP_AUX_CONTROL_HPD2_SELECTED', - 2: 'DP_AUX_CONTROL_HPD3_SELECTED', - 3: 'DP_AUX_CONTROL_HPD4_SELECTED', - 4: 'DP_AUX_CONTROL_HPD5_SELECTED', - 5: 'DP_AUX_CONTROL_NO_HPD_SELECTED', -} -DP_AUX_CONTROL_HPD1_SELECTED = 0 -DP_AUX_CONTROL_HPD2_SELECTED = 1 -DP_AUX_CONTROL_HPD3_SELECTED = 2 -DP_AUX_CONTROL_HPD4_SELECTED = 3 -DP_AUX_CONTROL_HPD5_SELECTED = 4 -DP_AUX_CONTROL_NO_HPD_SELECTED = 5 -DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' -DP_AUX_CONTROL_TEST_MODE__enumvalues = { - 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', -} -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 -DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 -DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' -DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { - 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', -} -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 -DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', -} -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', -} -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { - 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', -} -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', -} -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' -DP_AUX_ERR_OCCURRED_ACK__enumvalues = { - 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 1: 'DP_AUX_ERR_OCCURRED__ACK', -} -DP_AUX_ERR_OCCURRED__NOT_ACK = 0 -DP_AUX_ERR_OCCURRED__ACK = 1 -DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', -} -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', -} -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', -} -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', -} -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_INT_ACK' -DP_AUX_INT_ACK__enumvalues = { - 0: 'DP_AUX_INT__NOT_ACK', - 1: 'DP_AUX_INT__ACK', -} -DP_AUX_INT__NOT_ACK = 0 -DP_AUX_INT__ACK = 1 -DP_AUX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_LS_UPDATE_ACK' -DP_AUX_LS_UPDATE_ACK__enumvalues = { - 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', - 1: 'DP_AUX_INT_LS_UPDATE_ACK', -} -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 -DP_AUX_INT_LS_UPDATE_ACK = 1 -DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' -DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { - 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', -} -DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 -DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 -DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' -DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { - 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', - 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', -} -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 -DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET' -DP_AUX_RESET__enumvalues = { - 0: 'DP_AUX_RESET_DEASSERTED', - 1: 'DP_AUX_RESET_ASSERTED', -} -DP_AUX_RESET_DEASSERTED = 0 -DP_AUX_RESET_ASSERTED = 1 -DP_AUX_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET_DONE' -DP_AUX_RESET_DONE__enumvalues = { - 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 1: 'DP_AUX_RESET_SEQUENCE_DONE', -} -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 -DP_AUX_RESET_SEQUENCE_DONE = 1 -DP_AUX_RESET_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' -DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { - 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', - 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', -} -DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 -DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 -DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 -DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 -DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' -DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', -} -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 -DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 -DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' -DP_AUX_SW_CONTROL_SW_GO__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 1: 'DP_AUX_SW_CONTROL_SW__GO', -} -DP_AUX_SW_CONTROL_SW__NOT_GO = 0 -DP_AUX_SW_CONTROL_SW__GO = 1 -DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' -DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { - 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', - 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', - 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', -} -DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 -DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 -DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 -DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 -DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ACK' -DOUT_I2C_ACK__enumvalues = { - 0: 'DOUT_I2C_NO_ACK', - 1: 'DOUT_I2C_ACK_TO_CLEAN', -} -DOUT_I2C_NO_ACK = 0 -DOUT_I2C_ACK_TO_CLEAN = 1 -DOUT_I2C_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' -DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', -} -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 -DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', -} -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', -} -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' -DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', -} -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 -DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', -} -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' -DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', -} -DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 -DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 -DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' -DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', - 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', - 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', - 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', - 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', - 5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', -} -DOUT_I2C_CONTROL_SELECT_DDC1 = 0 -DOUT_I2C_CONTROL_SELECT_DDC2 = 1 -DOUT_I2C_CONTROL_SELECT_DDC3 = 2 -DOUT_I2C_CONTROL_SELECT_DDC4 = 3 -DOUT_I2C_CONTROL_SELECT_DDC5 = 4 -DOUT_I2C_CONTROL_SELECT_DDCVGA = 5 -DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_GO' -DOUT_I2C_CONTROL_GO__enumvalues = { - 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 1: 'DOUT_I2C_CONTROL_START_TRANSFER', -} -DOUT_I2C_CONTROL_STOP_TRANSFER = 0 -DOUT_I2C_CONTROL_START_TRANSFER = 1 -DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' -DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 1: 'DOUT_I2C_CONTROL__SEND_RESET', -} -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 -DOUT_I2C_CONTROL__SEND_RESET = 1 -DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' -DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { - 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', -} -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 -DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' -DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', -} -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 -DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' -DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', -} -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 -DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 -DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' -DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_TRANS0', - 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', -} -DOUT_I2C_CONTROL_TRANS0 = 0 -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 -DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' -DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { - 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 1: 'DOUT_I2C_DATA__INDEX_WRITE', -} -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 -DOUT_I2C_DATA__INDEX_WRITE = 1 -DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', -} -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', -} -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' -DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { - 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', -} -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 -DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', -} -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { - 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', -} -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' -DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { - 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', -} -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 -DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_EN' -CLOCK_GATING_EN__enumvalues = { - 0: 'CLOCK_GATING_ENABLE', - 1: 'CLOCK_GATING_DISABLE', -} -CLOCK_GATING_ENABLE = 0 -CLOCK_GATING_DISABLE = 1 -CLOCK_GATING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DAC_MUX_SELECT' -DAC_MUX_SELECT__enumvalues = { - 0: 'DAC_MUX_SELECT_DACA', - 1: 'DAC_MUX_SELECT_DACB', -} -DAC_MUX_SELECT_DACA = 0 -DAC_MUX_SELECT_DACB = 1 -DAC_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_DIS_CTRL' -DIOMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', -} -DIOMEM_ENABLE_MEM_PWR_CTRL = 0 -DIOMEM_DISABLE_MEM_PWR_CTRL = 1 -DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' -DIOMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQUEST', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', -} -DIOMEM_NO_FORCE_REQUEST = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 -DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' -DIOMEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQ', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', -} -DIOMEM_NO_FORCE_REQ = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 -DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL' -DIOMEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 -DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' -DIOMEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', -} -DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 -DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 -DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_DBG_BLOCK_SEL' -DIO_DBG_BLOCK_SEL__enumvalues = { - 0: 'DIO_DBG_BLOCK_SEL_DIO', - 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', - 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', - 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', - 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', - 15: 'DIO_DBG_BLOCK_SEL_DIGFE_E', - 18: 'DIO_DBG_BLOCK_SEL_DIGA', - 19: 'DIO_DBG_BLOCK_SEL_DIGB', - 20: 'DIO_DBG_BLOCK_SEL_DIGC', - 21: 'DIO_DBG_BLOCK_SEL_DIGD', - 22: 'DIO_DBG_BLOCK_SEL_DIGE', - 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', - 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', - 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', - 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', - 29: 'DIO_DBG_BLOCK_SEL_DPFE_E', - 32: 'DIO_DBG_BLOCK_SEL_DPA', - 33: 'DIO_DBG_BLOCK_SEL_DPB', - 34: 'DIO_DBG_BLOCK_SEL_DPC', - 35: 'DIO_DBG_BLOCK_SEL_DPD', - 36: 'DIO_DBG_BLOCK_SEL_DPE', - 39: 'DIO_DBG_BLOCK_SEL_AUX0', - 40: 'DIO_DBG_BLOCK_SEL_AUX1', - 41: 'DIO_DBG_BLOCK_SEL_AUX2', - 42: 'DIO_DBG_BLOCK_SEL_AUX3', - 43: 'DIO_DBG_BLOCK_SEL_AUX4', - 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', - 46: 'DIO_DBG_BLOCK_SEL_RESERVED', -} -DIO_DBG_BLOCK_SEL_DIO = 0 -DIO_DBG_BLOCK_SEL_DIGFE_A = 11 -DIO_DBG_BLOCK_SEL_DIGFE_B = 12 -DIO_DBG_BLOCK_SEL_DIGFE_C = 13 -DIO_DBG_BLOCK_SEL_DIGFE_D = 14 -DIO_DBG_BLOCK_SEL_DIGFE_E = 15 -DIO_DBG_BLOCK_SEL_DIGA = 18 -DIO_DBG_BLOCK_SEL_DIGB = 19 -DIO_DBG_BLOCK_SEL_DIGC = 20 -DIO_DBG_BLOCK_SEL_DIGD = 21 -DIO_DBG_BLOCK_SEL_DIGE = 22 -DIO_DBG_BLOCK_SEL_DPFE_A = 25 -DIO_DBG_BLOCK_SEL_DPFE_B = 26 -DIO_DBG_BLOCK_SEL_DPFE_C = 27 -DIO_DBG_BLOCK_SEL_DPFE_D = 28 -DIO_DBG_BLOCK_SEL_DPFE_E = 29 -DIO_DBG_BLOCK_SEL_DPA = 32 -DIO_DBG_BLOCK_SEL_DPB = 33 -DIO_DBG_BLOCK_SEL_DPC = 34 -DIO_DBG_BLOCK_SEL_DPD = 35 -DIO_DBG_BLOCK_SEL_DPE = 36 -DIO_DBG_BLOCK_SEL_AUX0 = 39 -DIO_DBG_BLOCK_SEL_AUX1 = 40 -DIO_DBG_BLOCK_SEL_AUX2 = 41 -DIO_DBG_BLOCK_SEL_AUX3 = 42 -DIO_DBG_BLOCK_SEL_AUX4 = 43 -DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 -DIO_DBG_BLOCK_SEL_RESERVED = 46 -DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { - 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', -} -DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 -DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { - 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', -} -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' -ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { - 0: 'ENUM_DCN_NOT_ACTIVE', - 1: 'ENUM_DCN_ACTIVE', -} -ENUM_DCN_NOT_ACTIVE = 0 -ENUM_DCN_ACTIVE = 1 -ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_STEREOSYNC_SEL' -GENERIC_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERIC_STEREOSYNC_SEL_D1', - 1: 'GENERIC_STEREOSYNC_SEL_D2', - 2: 'GENERIC_STEREOSYNC_SEL_D3', - 3: 'GENERIC_STEREOSYNC_SEL_D4', - 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', -} -GENERIC_STEREOSYNC_SEL_D1 = 0 -GENERIC_STEREOSYNC_SEL_D2 = 1 -GENERIC_STEREOSYNC_SEL_D3 = 2 -GENERIC_STEREOSYNC_SEL_D4 = 3 -GENERIC_STEREOSYNC_SEL_RESERVED = 4 -GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PM_ASSERT_RESET' -PM_ASSERT_RESET__enumvalues = { - 0: 'PM_ASSERT_RESET_0', - 1: 'PM_ASSERT_RESET_1', -} -PM_ASSERT_RESET_0 = 0 -PM_ASSERT_RESET_1 = 1 -PM_ASSERT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SOFT_RESET' -SOFT_RESET__enumvalues = { - 0: 'SOFT_RESET_0', - 1: 'SOFT_RESET_1', -} -SOFT_RESET_0 = 0 -SOFT_RESET_1 = 1 -SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_MUX_SELECT' -TMDS_MUX_SELECT__enumvalues = { - 0: 'TMDS_MUX_SELECT_B', - 1: 'TMDS_MUX_SELECT_G', - 2: 'TMDS_MUX_SELECT_R', - 3: 'TMDS_MUX_SELECT_RESERVED', -} -TMDS_MUX_SELECT_B = 0 -TMDS_MUX_SELECT_G = 1 -TMDS_MUX_SELECT_R = 2 -TMDS_MUX_SELECT_RESERVED = 3 -TMDS_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_POWER_STATE_ENUM' -DME_MEM_POWER_STATE_ENUM__enumvalues = { - 0: 'DME_MEM_POWER_STATE_ENUM_ON', - 1: 'DME_MEM_POWER_STATE_ENUM_LS', - 2: 'DME_MEM_POWER_STATE_ENUM_DS', - 3: 'DME_MEM_POWER_STATE_ENUM_SD', -} -DME_MEM_POWER_STATE_ENUM_ON = 0 -DME_MEM_POWER_STATE_ENUM_LS = 1 -DME_MEM_POWER_STATE_ENUM_DS = 2 -DME_MEM_POWER_STATE_ENUM_SD = 3 -DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_DIS_CTRL' -DME_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', -} -DME_MEM_ENABLE_MEM_PWR_CTRL = 0 -DME_MEM_DISABLE_MEM_PWR_CTRL = 1 -DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' -DME_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DME_MEM_NO_FORCE_REQUEST', - 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', -} -DME_MEM_NO_FORCE_REQUEST = 0 -DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_HUBP_SEL' -METADATA_HUBP_SEL__enumvalues = { - 0: 'METADATA_HUBP_SEL_0', - 1: 'METADATA_HUBP_SEL_1', - 2: 'METADATA_HUBP_SEL_2', - 3: 'METADATA_HUBP_SEL_3', - 4: 'METADATA_HUBP_SEL_RESERVED', -} -METADATA_HUBP_SEL_0 = 0 -METADATA_HUBP_SEL_1 = 1 -METADATA_HUBP_SEL_2 = 2 -METADATA_HUBP_SEL_3 = 3 -METADATA_HUBP_SEL_RESERVED = 4 -METADATA_HUBP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_STREAM_TYPE_SEL' -METADATA_STREAM_TYPE_SEL__enumvalues = { - 0: 'METADATA_STREAM_DP', - 1: 'METADATA_STREAM_DVE', -} -METADATA_STREAM_DP = 0 -METADATA_STREAM_DVE = 1 -METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' -VPG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', -} -VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 -VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 -VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' -VPG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'VPG_MEM_NO_FORCE_REQ', - 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', -} -VPG_MEM_NO_FORCE_REQ = 0 -VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 -VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_ACP_TYPE' -AFMT_ACP_TYPE__enumvalues = { - 0: 'ACP_TYPE_GENERIC_AUDIO', - 1: 'ACP_TYPE_ICE60958_AUDIO', - 2: 'ACP_TYPE_DVD_AUDIO', - 3: 'ACP_TYPE_SUPER_AUDIO_CD', -} -ACP_TYPE_GENERIC_AUDIO = 0 -ACP_TYPE_ICE60958_AUDIO = 1 -ACP_TYPE_DVD_AUDIO = 2 -ACP_TYPE_SUPER_AUDIO_CD = 3 -AFMT_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' -AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'AFMT_AUDIO_CRC_CH0_SIG', - 1: 'AFMT_AUDIO_CRC_CH1_SIG', - 2: 'AFMT_AUDIO_CRC_CH2_SIG', - 3: 'AFMT_AUDIO_CRC_CH3_SIG', - 4: 'AFMT_AUDIO_CRC_CH4_SIG', - 5: 'AFMT_AUDIO_CRC_CH5_SIG', - 6: 'AFMT_AUDIO_CRC_CH6_SIG', - 7: 'AFMT_AUDIO_CRC_CH7_SIG', - 8: 'AFMT_AUDIO_CRC_RESERVED_8', - 9: 'AFMT_AUDIO_CRC_RESERVED_9', - 10: 'AFMT_AUDIO_CRC_RESERVED_10', - 11: 'AFMT_AUDIO_CRC_RESERVED_11', - 12: 'AFMT_AUDIO_CRC_RESERVED_12', - 13: 'AFMT_AUDIO_CRC_RESERVED_13', - 14: 'AFMT_AUDIO_CRC_RESERVED_14', - 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', -} -AFMT_AUDIO_CRC_CH0_SIG = 0 -AFMT_AUDIO_CRC_CH1_SIG = 1 -AFMT_AUDIO_CRC_CH2_SIG = 2 -AFMT_AUDIO_CRC_CH3_SIG = 3 -AFMT_AUDIO_CRC_CH4_SIG = 4 -AFMT_AUDIO_CRC_CH5_SIG = 5 -AFMT_AUDIO_CRC_CH6_SIG = 6 -AFMT_AUDIO_CRC_CH7_SIG = 7 -AFMT_AUDIO_CRC_RESERVED_8 = 8 -AFMT_AUDIO_CRC_RESERVED_9 = 9 -AFMT_AUDIO_CRC_RESERVED_10 = 10 -AFMT_AUDIO_CRC_RESERVED_11 = 11 -AFMT_AUDIO_CRC_RESERVED_12 = 12 -AFMT_AUDIO_CRC_RESERVED_13 = 13 -AFMT_AUDIO_CRC_RESERVED_14 = 14 -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 -AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' -AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'AFMT_AUDIO_CRC_ONESHOT', - 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', -} -AFMT_AUDIO_CRC_ONESHOT = 0 -AFMT_AUDIO_CRC_AUTO_RESTART = 1 -AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' -AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { - 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', -} -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 -AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { - 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', -} -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { - 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', -} -AFMT_AUDIO_PACKET_SENT_DISABLED = 0 -AFMT_AUDIO_PACKET_SENT_ENABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { - 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', -} -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' -AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { - 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', -} -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 -AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { - 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', -} -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 -HDMI_SEND_MAX_AUDIO_PACKETS = 1 -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' -AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { - 0: 'AFMT_INTERRUPT_DISABLE', - 1: 'AFMT_INTERRUPT_ENABLE', -} -AFMT_INTERRUPT_DISABLE = 0 -AFMT_INTERRUPT_ENABLE = 1 -AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' -AFMT_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', -} -AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 -AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 -AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' -AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'AFMT_MEM_NO_FORCE_REQUEST', - 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', -} -AFMT_MEM_NO_FORCE_REQUEST = 0 -AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' -AFMT_RAMP_CONTROL0_SIGN__enumvalues = { - 0: 'AFMT_RAMP_SIGNED', - 1: 'AFMT_RAMP_UNSIGNED', -} -AFMT_RAMP_SIGNED = 0 -AFMT_RAMP_UNSIGNED = 1 -AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', - 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_ACP_SOURCE_FROM_AZALIA = 0 -AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AUDIO_LAYOUT_SELECT' -AUDIO_LAYOUT_SELECT__enumvalues = { - 0: 'AUDIO_LAYOUT_0', - 1: 'AUDIO_LAYOUT_1', -} -AUDIO_LAYOUT_0 = 0 -AUDIO_LAYOUT_1 = 1 -AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' -HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { - 0: 'HPO_TOP_CLOCK_GATING_EN', - 1: 'HPO_TOP_CLOCK_GATING_DIS', -} -HPO_TOP_CLOCK_GATING_EN = 0 -HPO_TOP_CLOCK_GATING_DIS = 1 -HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_TEST_CLK_SEL' -HPO_TOP_TEST_CLK_SEL__enumvalues = { - 0: 'HPO_TOP_PERMANENT_DISPCLK', - 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', - 2: 'HPO_TOP_PERMANENT_SOCCLK', - 3: 'HPO_TOP_TEST_CLOCK_RESERVED', - 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', - 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', - 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', -} -HPO_TOP_PERMANENT_DISPCLK = 0 -HPO_TOP_REGISTER_GATED_DISPCLK = 1 -HPO_TOP_PERMANENT_SOCCLK = 2 -HPO_TOP_TEST_CLOCK_RESERVED = 3 -HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 -HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 -HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 -HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 -HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 -HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 -HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 -HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 -HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { - 0: 'DP_STREAM_MAPPER_LINK0', - 1: 'DP_STREAM_MAPPER_LINK1', - 2: 'DP_STREAM_MAPPER_RESERVED', -} -DP_STREAM_MAPPER_LINK0 = 0 -DP_STREAM_MAPPER_LINK1 = 1 -DP_STREAM_MAPPER_RESERVED = 2 -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL' -HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DB_ENABLE', - 1: 'HDMI_STREAM_ENC_DB_DISABLE', -} -HDMI_STREAM_ENC_DB_ENABLE = 0 -HDMI_STREAM_ENC_DB_DISABLE = 1 -HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE' -HDMI_STREAM_ENC_DSC_MODE__enumvalues = { - 0: 'STREAM_DSC_DISABLE', - 1: 'STREAM_DSC_444_RGB', - 2: 'STREAM_DSC_NATIVE_422_420', -} -STREAM_DSC_DISABLE = 0 -STREAM_DSC_444_RGB = 1 -STREAM_DSC_NATIVE_422_420 = 2 -HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL' -HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DISABLE', - 1: 'HDMI_STREAM_ENC_ENABLE', -} -HDMI_STREAM_ENC_DISABLE = 0 -HDMI_STREAM_ENC_ENABLE = 1 -HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE' -HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = { - 0: 'STREAM_ODM_COMBINE_1_SEGMENT', - 1: 'STREAM_ODM_COMBINE_2_SEGMENT', - 2: 'STREAM_ODM_COMBINE_RESERVED', - 3: 'STREAM_ODM_COMBINE_4_SEGMENT', -} -STREAM_ODM_COMBINE_1_SEGMENT = 0 -STREAM_ODM_COMBINE_2_SEGMENT = 1 -STREAM_ODM_COMBINE_RESERVED = 2 -STREAM_ODM_COMBINE_4_SEGMENT = 3 -HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' -HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', - 1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', - 2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', -} -HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0 -HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1 -HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2 -HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT' -HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { - 0: 'HDMI_STREAM_ENC_HARDWARE', - 1: 'HDMI_STREAM_ENC_PROGRAMMABLE', -} -HDMI_STREAM_ENC_HARDWARE = 0 -HDMI_STREAM_ENC_PROGRAMMABLE = 1 -HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING' -HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'STREAM_PIXEL_ENCODING_444_RGB', - 1: 'STREAM_PIXEL_ENCODING_422', - 2: 'STREAM_PIXEL_ENCODING_420', -} -STREAM_PIXEL_ENCODING_444_RGB = 0 -STREAM_PIXEL_ENCODING_422 = 1 -STREAM_PIXEL_ENCODING_420 = 2 -HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL' -HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DCCG', - 1: 'HDMI_STREAM_ENC_DISPLAY_PIPE', -} -HDMI_STREAM_ENC_DCCG = 0 -HDMI_STREAM_ENC_DISPLAY_PIPE = 1 -HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL' -HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_NOT_RESET', - 1: 'HDMI_STREAM_ENC_RESET', -} -HDMI_STREAM_ENC_NOT_RESET = 0 -HDMI_STREAM_ENC_RESET = 1 -HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE' -HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = { - 0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', -} -HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 -HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 -HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM' -BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = { - 0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', - 1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', - 2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', - 3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', -} -BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0 -BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1 -BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2 -BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3 -BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_BORROW_MODE' -HDMI_BORROW_MODE__enumvalues = { - 0: 'TB_BORROW_MODE_NONE', - 1: 'TB_BORROW_MODE_ACTIVE', - 2: 'TB_BORROW_MODE_BLANK', - 3: 'TB_BORROW_MODE_RESERVED', -} -TB_BORROW_MODE_NONE = 0 -TB_BORROW_MODE_ACTIVE = 1 -TB_BORROW_MODE_BLANK = 2 -TB_BORROW_MODE_RESERVED = 3 -HDMI_BORROW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACP_SEND' -HDMI_TB_ENC_ACP_SEND__enumvalues = { - 0: 'TB_ACP_NOT_SEND', - 1: 'TB_ACP_PKT_SEND', -} -TB_ACP_NOT_SEND = 0 -TB_ACP_PKT_SEND = 1 -HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY' -HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_CONT' -HDMI_TB_ENC_ACR_CONT__enumvalues = { - 0: 'TB_ACR_CONT_DISABLE', - 1: 'TB_ACR_CONT_ENABLE', -} -TB_ACR_CONT_DISABLE = 0 -TB_ACR_CONT_ENABLE = 1 -HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE' -HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = { - 0: 'TB_ACR_0_MULTIPLE_RESERVED', - 1: 'TB_ACR_1_MULTIPLE', - 2: 'TB_ACR_2_MULTIPLE', - 3: 'TB_ACR_3_MULTIPLE_RESERVED', - 4: 'TB_ACR_4_MULTIPLE', - 5: 'TB_ACR_5_MULTIPLE_RESERVED', - 6: 'TB_ACR_6_MULTIPLE_RESERVED', - 7: 'TB_ACR_7_MULTIPLE_RESERVED', -} -TB_ACR_0_MULTIPLE_RESERVED = 0 -TB_ACR_1_MULTIPLE = 1 -TB_ACR_2_MULTIPLE = 2 -TB_ACR_3_MULTIPLE_RESERVED = 3 -TB_ACR_4_MULTIPLE = 4 -TB_ACR_5_MULTIPLE_RESERVED = 5 -TB_ACR_6_MULTIPLE_RESERVED = 6 -TB_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SELECT' -HDMI_TB_ENC_ACR_SELECT__enumvalues = { - 0: 'TB_ACR_SELECT_HW', - 1: 'TB_ACR_SELECT_32K', - 2: 'TB_ACR_SELECT_44K', - 3: 'TB_ACR_SELECT_48K', -} -TB_ACR_SELECT_HW = 0 -TB_ACR_SELECT_32K = 1 -TB_ACR_SELECT_44K = 2 -TB_ACR_SELECT_48K = 3 -HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SEND' -HDMI_TB_ENC_ACR_SEND__enumvalues = { - 0: 'TB_ACR_NOT_SEND', - 1: 'TB_ACR_PKT_SEND', -} -TB_ACR_NOT_SEND = 0 -TB_ACR_PKT_SEND = 1 -HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE' -HDMI_TB_ENC_ACR_SOURCE__enumvalues = { - 0: 'TB_ACR_SOURCE_HW', - 1: 'TB_ACR_SOURCE_SW', -} -TB_ACR_SOURCE_HW = 0 -TB_ACR_SOURCE_SW = 1 -HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT' -HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = { - 0: 'TB_AUDIO_INFO_CONT_DISABLE', - 1: 'TB_AUDIO_INFO_CONT_ENABLE', -} -TB_AUDIO_INFO_CONT_DISABLE = 0 -TB_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND' -HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = { - 0: 'TB_AUDIO_INFO_NOT_SEND', - 1: 'TB_AUDIO_INFO_PKT_SEND', -} -TB_AUDIO_INFO_NOT_SEND = 0 -TB_AUDIO_INFO_PKT_SEND = 1 -HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL' -HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = { - 0: 'TB_CRC_TB_ENC_INPUT', - 1: 'TB_CRC_DSC_PACKER', - 2: 'TB_CRC_DEEP_COLOR_PACKER', - 3: 'TB_CRC_ENCRYPTOR_INPUT', -} -TB_CRC_TB_ENC_INPUT = 0 -TB_CRC_DSC_PACKER = 1 -TB_CRC_DEEP_COLOR_PACKER = 2 -TB_CRC_ENCRYPTOR_INPUT = 3 -HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_CRC_TYPE' -HDMI_TB_ENC_CRC_TYPE__enumvalues = { - 0: 'TB_CRC_ALL_TRIBYTES', - 1: 'TB_CRC_ACTIVE_TRIBYTES', - 2: 'TB_CRC_DATAISLAND_TRIBYTES', - 3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', -} -TB_CRC_ALL_TRIBYTES = 0 -TB_CRC_ACTIVE_TRIBYTES = 1 -TB_CRC_DATAISLAND_TRIBYTES = 2 -TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3 -HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH' -HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'TB_DEEP_COLOR_DEPTH_24BPP', - 1: 'TB_DEEP_COLOR_DEPTH_30BPP', - 2: 'TB_DEEP_COLOR_DEPTH_36BPP', - 3: 'TB_DEEP_COLOR_DEPTH_RESERVED', -} -TB_DEEP_COLOR_DEPTH_24BPP = 0 -TB_DEEP_COLOR_DEPTH_30BPP = 1 -TB_DEEP_COLOR_DEPTH_36BPP = 2 -TB_DEEP_COLOR_DEPTH_RESERVED = 3 -HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE' -HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = { - 0: 'TB_DEFAULT_PHASE_IS_0', - 1: 'TB_DEFAULT_PHASE_IS_1', -} -TB_DEFAULT_PHASE_IS_0 = 0 -TB_DEFAULT_PHASE_IS_1 = 1 -HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DSC_MODE' -HDMI_TB_ENC_DSC_MODE__enumvalues = { - 0: 'TB_DSC_DISABLE', - 1: 'TB_DSC_444_RGB', - 2: 'TB_DSC_NATIVE_422_420', -} -TB_DSC_DISABLE = 0 -TB_DSC_444_RGB = 1 -TB_DSC_NATIVE_422_420 = 2 -HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ENABLE' -HDMI_TB_ENC_ENABLE__enumvalues = { - 0: 'TB_DISABLE', - 1: 'TB_ENABLE', -} -TB_DISABLE = 0 -TB_ENABLE = 1 -HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE' -HDMI_TB_ENC_GC_AVMUTE__enumvalues = { - 0: 'TB_GC_AVMUTE_SET', - 1: 'TB_GC_AVMUTE_UNSET', -} -TB_GC_AVMUTE_SET = 0 -TB_GC_AVMUTE_UNSET = 1 -HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT' -HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = { - 0: 'TB_GC_AVMUTE_CONT_DISABLE', - 1: 'TB_GC_AVMUTE_CONT_ENABLE', -} -TB_GC_AVMUTE_CONT_DISABLE = 0 -TB_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_CONT' -HDMI_TB_ENC_GC_CONT__enumvalues = { - 0: 'TB_GC_CONT_DISABLE', - 1: 'TB_GC_CONT_ENABLE', -} -TB_GC_CONT_DISABLE = 0 -TB_GC_CONT_ENABLE = 1 -HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_SEND' -HDMI_TB_ENC_GC_SEND__enumvalues = { - 0: 'TB_GC_NOT_SEND', - 1: 'TB_GC_PKT_SEND', -} -TB_GC_NOT_SEND = 0 -TB_GC_PKT_SEND = 1 -HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT' -HDMI_TB_ENC_GENERIC_CONT__enumvalues = { - 0: 'TB_GENERIC_CONT_DISABLE', - 1: 'TB_GENERIC_CONT_ENABLE', -} -TB_GENERIC_CONT_DISABLE = 0 -TB_GENERIC_CONT_ENABLE = 1 -HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN' -HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = { - 0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', - 1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', -} -HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0 -HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1 -HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND' -HDMI_TB_ENC_GENERIC_SEND__enumvalues = { - 0: 'TB_GENERIC_NOT_SEND', - 1: 'TB_GENERIC_PKT_SEND', -} -TB_GENERIC_NOT_SEND = 0 -TB_GENERIC_PKT_SEND = 1 -HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ISRC_CONT' -HDMI_TB_ENC_ISRC_CONT__enumvalues = { - 0: 'TB_ISRC_CONT_DISABLE', - 1: 'TB_ISRC_CONT_ENABLE', -} -TB_ISRC_CONT_DISABLE = 0 -TB_ISRC_CONT_ENABLE = 1 -HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ISRC_SEND' -HDMI_TB_ENC_ISRC_SEND__enumvalues = { - 0: 'TB_ISRC_NOT_SEND', - 1: 'TB_ISRC_PKT_SEND', -} -TB_ISRC_NOT_SEND = 0 -TB_ISRC_PKT_SEND = 1 -HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE' -HDMI_TB_ENC_METADATA_ENABLE__enumvalues = { - 0: 'TB_METADATA_NOT_SEND', - 1: 'TB_METADATA_PKT_SEND', -} -TB_METADATA_NOT_SEND = 0 -TB_METADATA_PKT_SEND = 1 -HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE' -HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'TB_PKT_LINE_REF_END_OF_ACTIVE', - 1: 'TB_PKT_LINE_REF_OTGSOF', -} -TB_PKT_LINE_REF_END_OF_ACTIVE = 0 -TB_PKT_LINE_REF_OTGSOF = 1 -HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING' -HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'TB_PIXEL_ENCODING_444_RGB', - 1: 'TB_PIXEL_ENCODING_422', - 2: 'TB_PIXEL_ENCODING_420', -} -TB_PIXEL_ENCODING_444_RGB = 0 -TB_PIXEL_ENCODING_422 = 1 -TB_PIXEL_ENCODING_420 = 2 -HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_RESET' -HDMI_TB_ENC_RESET__enumvalues = { - 0: 'TB_NOT_RESET', - 1: 'TB_RESET', -} -TB_NOT_RESET = 0 -TB_RESET = 1 -HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE' -HDMI_TB_ENC_SYNC_PHASE__enumvalues = { - 0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TB_SYNC_PHASE_ON_FRAME_START', -} -TB_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TB_SYNC_PHASE_ON_FRAME_START = 1 -HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'INPUT_FIFO_ERROR_TYPE' -INPUT_FIFO_ERROR_TYPE__enumvalues = { - 0: 'TB_NO_ERROR_OCCURRED', - 1: 'TB_OVERFLOW_OCCURRED', -} -TB_NO_ERROR_OCCURRED = 0 -TB_OVERFLOW_OCCURRED = 1 -INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', -} -DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 -DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 -DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { - 0: 'DP_STREAM_ENC_HARDWARE', - 1: 'DP_STREAM_ENC_PROGRAMMABLE', -} -DP_STREAM_ENC_HARDWARE = 0 -DP_STREAM_ENC_PROGRAMMABLE = 1 -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' -DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_DCCG', - 1: 'DP_STREAM_ENC_DISPLAY_PIPE', -} -DP_STREAM_ENC_DCCG = 0 -DP_STREAM_ENC_DISPLAY_PIPE = 1 -DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' -DP_STREAM_ENC_RESET_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_NOT_RESET', - 1: 'DP_STREAM_ENC_RESET', -} -DP_STREAM_ENC_NOT_RESET = 0 -DP_STREAM_ENC_RESET = 1 -DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' -DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { - 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', -} -DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 -DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 -DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' -ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', -} -DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 -DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 -ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { - 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', - 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', -} -DP_SYM32_ENC_ONE_SHOT_MODE = 0 -DP_SYM32_ENC_CONTINUOUS_MODE = 1 -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' -ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { - 0: 'DP_SYM32_ENC_CRC_NOT_VALID', - 1: 'DP_SYM32_ENC_CRC_VALID', -} -DP_SYM32_ENC_CRC_NOT_VALID = 0 -DP_SYM32_ENC_CRC_VALID = 1 -ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', -} -DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 -DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 -DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 -DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' -ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { - 0: 'DP_SYM32_ENC_DISABLE', - 1: 'DP_SYM32_ENC_ENABLE', -} -DP_SYM32_ENC_DISABLE = 0 -DP_SYM32_ENC_ENABLE = 1 -ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', -} -DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 -DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', -} -DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 -DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', -} -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', -} -DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 -DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', -} -DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 -DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 -DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 -DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { - 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', - 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', -} -DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 -DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' -ENUM_DP_SYM32_ENC_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_PENDING', - 1: 'DP_SYM32_ENC_PENDING', -} -DP_SYM32_ENC_NOT_PENDING = 0 -DP_SYM32_ENC_PENDING = 1 -ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', -} -DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 -DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { - 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', -} -DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 -DP_SYM32_ENC_COMPRESSED_FORMAT = 1 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', -} -DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 -DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 -DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 -DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' -ENUM_DP_SYM32_ENC_RESET__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_RESET', - 1: 'DP_SYM32_ENC_RESET', -} -DP_SYM32_ENC_NOT_RESET = 0 -DP_SYM32_ENC_RESET = 1 -ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' -ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', -} -DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 -DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 -ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' -ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { - 0: 'DP_SYM32_ENC_DP_SOF', - 1: 'DP_SYM32_ENC_OTG_SOF', -} -DP_SYM32_ENC_DP_SOF = 0 -DP_SYM32_ENC_OTG_SOF = 1 -ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { - 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', - 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', -} -DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' -ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_END_LLCP', - 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', -} -DP_DPHY_SYM32_CRC_END_LLCP = 0 -DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_END_PS_ANY = 3 -ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' -ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_START_LLCP', - 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 4: 'DP_DPHY_SYM32_CRC_START_TP_START', -} -DP_DPHY_SYM32_CRC_START_LLCP = 0 -DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 -DP_DPHY_SYM32_CRC_START_TP_START = 4 -ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', -} -DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 -DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 -DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', -} -DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 -DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' -ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_DISABLE', - 1: 'DP_DPHY_SYM32_ENABLE', -} -DP_DPHY_SYM32_DISABLE = 0 -DP_DPHY_SYM32_ENABLE = 1 -ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE' -ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = { - 0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0', - 1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1', -} -DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0 -DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1 -ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' -ENUM_DP_DPHY_SYM32_MODE__enumvalues = { - 0: 'DP_DPHY_SYM32_LT_TPS1', - 1: 'DP_DPHY_SYM32_LT_TPS2', - 2: 'DP_DPHY_SYM32_ACTIVE', - 3: 'DP_DPHY_SYM32_TEST', -} -DP_DPHY_SYM32_LT_TPS1 = 0 -DP_DPHY_SYM32_LT_TPS2 = 1 -DP_DPHY_SYM32_ACTIVE = 2 -DP_DPHY_SYM32_TEST = 3 -ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' -ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { - 0: 'DP_DPHY_SYM32_1LANE', - 1: 'DP_DPHY_SYM32_2LANE', - 2: 'DP_DPHY_SYM32_RESERVED', - 3: 'DP_DPHY_SYM32_4LANE', -} -DP_DPHY_SYM32_1LANE = 0 -DP_DPHY_SYM32_2LANE = 1 -DP_DPHY_SYM32_RESERVED = 2 -DP_DPHY_SYM32_4LANE = 3 -ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', -} -DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 -DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' -ENUM_DP_DPHY_SYM32_RESET__enumvalues = { - 0: 'DP_DPHY_SYM32_NOT_RESET', - 1: 'DP_DPHY_SYM32_RESET', -} -DP_DPHY_SYM32_NOT_RESET = 0 -DP_DPHY_SYM32_RESET = 1 -ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' -ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', -} -DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 -DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 -ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' -ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', -} -DP_DPHY_SYM32_SAT_NO_UPDATE = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', -} -DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' -ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_STATUS_IDLE', - 1: 'DP_DPHY_SYM32_STATUS_ENABLED', -} -DP_DPHY_SYM32_STATUS_IDLE = 0 -DP_DPHY_SYM32_STATUS_ENABLED = 1 -ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', -} -DP_DPHY_SYM32_STREAM_OVR_NONE = 0 -DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 -DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', - 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', -} -DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 -DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', -} -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' -ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', - 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', - 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', -} -DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 -DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 -DP_DPHY_SYM32_TP_SELECT_PRBS = 2 -DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 -DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 -ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' -APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'APG_AUDIO_CRC_CH0_SIG', - 1: 'APG_AUDIO_CRC_CH1_SIG', - 2: 'APG_AUDIO_CRC_CH2_SIG', - 3: 'APG_AUDIO_CRC_CH3_SIG', - 4: 'APG_AUDIO_CRC_CH4_SIG', - 5: 'APG_AUDIO_CRC_CH5_SIG', - 6: 'APG_AUDIO_CRC_CH6_SIG', - 7: 'APG_AUDIO_CRC_CH7_SIG', - 8: 'APG_AUDIO_CRC_RESERVED_8', - 9: 'APG_AUDIO_CRC_RESERVED_9', - 10: 'APG_AUDIO_CRC_RESERVED_10', - 11: 'APG_AUDIO_CRC_RESERVED_11', - 12: 'APG_AUDIO_CRC_RESERVED_12', - 13: 'APG_AUDIO_CRC_RESERVED_13', - 14: 'APG_AUDIO_CRC_RESERVED_14', - 15: 'APG_AUDIO_CRC_RESERVED_15', -} -APG_AUDIO_CRC_CH0_SIG = 0 -APG_AUDIO_CRC_CH1_SIG = 1 -APG_AUDIO_CRC_CH2_SIG = 2 -APG_AUDIO_CRC_CH3_SIG = 3 -APG_AUDIO_CRC_CH4_SIG = 4 -APG_AUDIO_CRC_CH5_SIG = 5 -APG_AUDIO_CRC_CH6_SIG = 6 -APG_AUDIO_CRC_CH7_SIG = 7 -APG_AUDIO_CRC_RESERVED_8 = 8 -APG_AUDIO_CRC_RESERVED_9 = 9 -APG_AUDIO_CRC_RESERVED_10 = 10 -APG_AUDIO_CRC_RESERVED_11 = 11 -APG_AUDIO_CRC_RESERVED_12 = 12 -APG_AUDIO_CRC_RESERVED_13 = 13 -APG_AUDIO_CRC_RESERVED_14 = 14 -APG_AUDIO_CRC_RESERVED_15 = 15 -APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' -APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'APG_AUDIO_CRC_ONESHOT', - 1: 'APG_AUDIO_CRC_CONTINUOUS', -} -APG_AUDIO_CRC_ONESHOT = 0 -APG_AUDIO_CRC_CONTINUOUS = 1 -APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_ACP_TYPE' -APG_DBG_ACP_TYPE__enumvalues = { - 0: 'APG_ACP_TYPE_GENERIC_AUDIO', - 1: 'APG_ACP_TYPE_ICE60958_AUDIO', - 2: 'APG_ACP_TYPE_DVD_AUDIO', - 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', -} -APG_ACP_TYPE_GENERIC_AUDIO = 0 -APG_ACP_TYPE_ICE60958_AUDIO = 1 -APG_ACP_TYPE_DVD_AUDIO = 2 -APG_ACP_TYPE_SUPER_AUDIO_CD = 3 -APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' -APG_DBG_AUDIO_DTO_BASE__enumvalues = { - 0: 'BASE_RATE_48KHZ', - 1: 'BASE_RATE_44P1KHZ', -} -BASE_RATE_48KHZ = 0 -BASE_RATE_44P1KHZ = 1 -APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' -APG_DBG_AUDIO_DTO_DIV__enumvalues = { - 0: 'DIVISOR_BY1', - 1: 'DIVISOR_BY2_RESERVED', - 2: 'DIVISOR_BY3', - 3: 'DIVISOR_BY4_RESERVED', - 4: 'DIVISOR_BY5_RESERVED', - 5: 'DIVISOR_BY6_RESERVED', - 6: 'DIVISOR_BY7_RESERVED', - 7: 'DIVISOR_BY8_RESERVED', -} -DIVISOR_BY1 = 0 -DIVISOR_BY2_RESERVED = 1 -DIVISOR_BY3 = 2 -DIVISOR_BY4_RESERVED = 3 -DIVISOR_BY5_RESERVED = 4 -DIVISOR_BY6_RESERVED = 5 -DIVISOR_BY7_RESERVED = 6 -DIVISOR_BY8_RESERVED = 7 -APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' -APG_DBG_AUDIO_DTO_MULTI__enumvalues = { - 0: 'MULTIPLE_BY1', - 1: 'MULTIPLE_BY2', - 2: 'MULTIPLE_BY3_RESERVED', - 3: 'MULTIPLE_BY4', - 4: 'MULTIPLE_RESERVED', -} -MULTIPLE_BY1 = 0 -MULTIPLE_BY2 = 1 -MULTIPLE_BY3_RESERVED = 2 -MULTIPLE_BY4 = 3 -MULTIPLE_RESERVED = 4 -APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_MUX_SEL' -APG_DBG_MUX_SEL__enumvalues = { - 0: 'APG_FUNCTIONAL_MODE', - 1: 'APG_DEBUG_AUDIO_MODE', -} -APG_FUNCTIONAL_MODE = 0 -APG_DEBUG_AUDIO_MODE = 1 -APG_DBG_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_POWER_STATE' -APG_MEM_POWER_STATE__enumvalues = { - 0: 'APG_MEM_POWER_STATE_ON', - 1: 'APG_MEM_POWER_STATE_LS', - 2: 'APG_MEM_POWER_STATE_DS', - 3: 'APG_MEM_POWER_STATE_SD', -} -APG_MEM_POWER_STATE_ON = 0 -APG_MEM_POWER_STATE_LS = 1 -APG_MEM_POWER_STATE_DS = 2 -APG_MEM_POWER_STATE_SD = 3 -APG_MEM_POWER_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_DIS_CTRL' -APG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', -} -APG_MEM_ENABLE_MEM_PWR_CTRL = 0 -APG_MEM_DISABLE_MEM_PWR_CTRL = 1 -APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' -APG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'APG_MEM_NO_FORCE_REQUEST', - 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', -} -APG_MEM_NO_FORCE_REQUEST = 0 -APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' -APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'APG_ACP_SOURCE_NO_OVERRIDE', - 1: 'APG_ACP_OVERRIDE', -} -APG_ACP_SOURCE_NO_OVERRIDE = 0 -APG_ACP_OVERRIDE = 1 -APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', -} -APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 -APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_RAMP_CONTROL_SIGN' -APG_RAMP_CONTROL_SIGN__enumvalues = { - 0: 'APG_RAMP_SIGNED', - 1: 'APG_RAMP_UNSIGNED', -} -APG_RAMP_SIGNED = 0 -APG_RAMP_UNSIGNED = 1 -APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', -} -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { - 0: 'DCIO_TEST_CLK_SEL_DISPCLK', - 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', - 2: 'DCIO_TEST_CLK_SEL_SOCCLK', -} -DCIO_TEST_CLK_SEL_DISPCLK = 0 -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 -DCIO_TEST_CLK_SEL_SOCCLK = 2 -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { - 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', -} -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' -DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', - 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', -} -DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 -DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 -DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 -DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 -DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 -DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 -DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 -DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 -DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' -DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', - 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', - 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', -} -DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 -DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 -DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 -DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 -DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' -DCIO_DCRXPHY_SOFT_RESET__enumvalues = { - 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', -} -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 -DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICA_SEL' -DCIO_DC_GENERICA_SEL__enumvalues = { - 1: 'DCIO_GENERICA_SEL_STEREOSYNC', - 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 11: 'DCIO_GENERICA_SEL_SYNCEN', -} -DCIO_GENERICA_SEL_STEREOSYNC = 1 -DCIO_GENERICA_SEL_GENERICA_DCCG = 10 -DCIO_GENERICA_SEL_SYNCEN = 11 -DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICB_SEL' -DCIO_DC_GENERICB_SEL__enumvalues = { - 1: 'DCIO_GENERICB_SEL_STEREOSYNC', - 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 11: 'DCIO_GENERICB_SEL_SYNCEN', -} -DCIO_GENERICB_SEL_STEREOSYNC = 1 -DCIO_GENERICB_SEL_GENERICB_DCCG = 10 -DCIO_GENERICB_SEL_SYNCEN = 11 -DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', -} -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_CLK', -} -DCIO_UNIPHYA_FBDIV_CLK = 0 -DCIO_UNIPHYB_FBDIV_CLK = 1 -DCIO_UNIPHYC_FBDIV_CLK = 2 -DCIO_UNIPHYD_FBDIV_CLK = 3 -DCIO_UNIPHYE_FBDIV_CLK = 4 -DCIO_UNIPHYF_FBDIV_CLK = 5 -DCIO_UNIPHYG_FBDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', -} -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 -DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 -DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 -DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 -DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 -DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 -DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', - 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', - 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', - 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', - 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', - 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', - 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', -} -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 -DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 -DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 -DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 -DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 -DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 -DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { - 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', - 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', -} -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' -DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', -} -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 -DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' -DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DCIO_GPU_TIMER_START_0_END_27', - 1: 'DCIO_GPU_TIMER_START_1_END_28', - 2: 'DCIO_GPU_TIMER_START_2_END_29', - 3: 'DCIO_GPU_TIMER_START_3_END_30', - 4: 'DCIO_GPU_TIMER_START_4_END_31', - 5: 'DCIO_GPU_TIMER_START_6_END_33', - 6: 'DCIO_GPU_TIMER_START_8_END_35', - 7: 'DCIO_GPU_TIMER_START_10_END_37', -} -DCIO_GPU_TIMER_START_0_END_27 = 0 -DCIO_GPU_TIMER_START_1_END_28 = 1 -DCIO_GPU_TIMER_START_2_END_29 = 2 -DCIO_GPU_TIMER_START_3_END_30 = 3 -DCIO_GPU_TIMER_START_4_END_31 = 4 -DCIO_GPU_TIMER_START_6_END_33 = 5 -DCIO_GPU_TIMER_START_8_END_35 = 6 -DCIO_GPU_TIMER_START_10_END_37 = 7 -DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', -} -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', - 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', -} -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' -DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MASK_NONE', - 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', - 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', - 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', - 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', - 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', - 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', - 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', -} -DCIO_EXT_VSYNC_MASK_NONE = 0 -DCIO_EXT_VSYNC_MASK_PIPE0 = 1 -DCIO_EXT_VSYNC_MASK_PIPE1 = 2 -DCIO_EXT_VSYNC_MASK_PIPE2 = 3 -DCIO_EXT_VSYNC_MASK_PIPE3 = 4 -DCIO_EXT_VSYNC_MASK_PIPE4 = 5 -DCIO_EXT_VSYNC_MASK_PIPE5 = 6 -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 -DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' -DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 1: 'DCIO_EXT_VSYNC_MUX_OTG0', - 2: 'DCIO_EXT_VSYNC_MUX_OTG1', - 3: 'DCIO_EXT_VSYNC_MUX_OTG2', - 4: 'DCIO_EXT_VSYNC_MUX_OTG3', - 5: 'DCIO_EXT_VSYNC_MUX_OTG4', - 6: 'DCIO_EXT_VSYNC_MUX_OTG5', - 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', -} -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 -DCIO_EXT_VSYNC_MUX_OTG0 = 1 -DCIO_EXT_VSYNC_MUX_OTG1 = 2 -DCIO_EXT_VSYNC_MUX_OTG2 = 3 -DCIO_EXT_VSYNC_MUX_OTG3 = 4 -DCIO_EXT_VSYNC_MUX_OTG4 = 5 -DCIO_EXT_VSYNC_MUX_OTG5 = 6 -DCIO_EXT_VSYNC_MUX_GENERICB = 7 -DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' -DCIO_DPCS_INTERRUPT_MASK__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_DISABLE', - 1: 'DCIO_DPCS_INTERRUPT_ENABLE', -} -DCIO_DPCS_INTERRUPT_DISABLE = 0 -DCIO_DPCS_INTERRUPT_ENABLE = 1 -DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' -DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', -} -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 -DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DSYNC_SOFT_RESET' -DCIO_DSYNC_SOFT_RESET__enumvalues = { - 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', -} -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 -DCIO_DSYNC_SOFT_RESET_ASSERT = 1 -DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' -DCIO_GENLK_CLK_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', - 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', -} -DCIO_GENLK_CLK_GSL_MASK_NO = 0 -DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 -DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 -DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' -DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', -} -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 -DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_SEL' -DCIO_GSL_SEL__enumvalues = { - 0: 'DCIO_GSL_SEL_GROUP_0', - 1: 'DCIO_GSL_SEL_GROUP_1', - 2: 'DCIO_GSL_SEL_GROUP_2', -} -DCIO_GSL_SEL_GROUP_0 = 0 -DCIO_GSL_SEL_GROUP_1 = 1 -DCIO_GSL_SEL_GROUP_2 = 2 -DCIO_GSL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' -DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { - 0: 'HPO_SRC0', - 1: 'HPO_SRC_RESERVED', -} -HPO_SRC0 = 0 -HPO_SRC_RESERVED = 1 -DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' -DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' -DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', -} -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' -DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { - 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', -} -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 -DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', -} -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 -DCIO_UNIPHY_CHANNEL_INVERTED = 1 -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { - 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', -} -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' -DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { - 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', - 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', -} -DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 -DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 -DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' -DCIOCHIP_AUX_CSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', -} -DCIOCHIP_AUX_CSEL_DEC1P0 = 0 -DCIOCHIP_AUX_CSEL_DEC0P9 = 1 -DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' -DCIOCHIP_AUX_CSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_INC1P0', - 1: 'DCIOCHIP_AUX_CSEL_INC1P1', -} -DCIOCHIP_AUX_CSEL_INC1P0 = 0 -DCIOCHIP_AUX_CSEL_INC1P1 = 1 -DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' -DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', - 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', -} -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 -DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' -DCIOCHIP_AUX_HYS_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_HYS_TUNE_0', - 1: 'DCIOCHIP_AUX_HYS_TUNE_1', - 2: 'DCIOCHIP_AUX_HYS_TUNE_2', - 3: 'DCIOCHIP_AUX_HYS_TUNE_3', -} -DCIOCHIP_AUX_HYS_TUNE_0 = 0 -DCIOCHIP_AUX_HYS_TUNE_1 = 1 -DCIOCHIP_AUX_HYS_TUNE_2 = 2 -DCIOCHIP_AUX_HYS_TUNE_3 = 3 -DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' -DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', - 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', -} -DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 -DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 -DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 -DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 -DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' -DCIOCHIP_AUX_RSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', -} -DCIOCHIP_AUX_RSEL_DEC1P0 = 0 -DCIOCHIP_AUX_RSEL_DEC0P9 = 1 -DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' -DCIOCHIP_AUX_RSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_INC1P0', - 1: 'DCIOCHIP_AUX_RSEL_INC1P1', -} -DCIOCHIP_AUX_RSEL_INC1P0 = 0 -DCIOCHIP_AUX_RSEL_INC1P1 = 1 -DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' -DCIOCHIP_AUX_SPIKESEL__enumvalues = { - 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', - 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', -} -DCIOCHIP_AUX_SPIKESEL_50NS = 0 -DCIOCHIP_AUX_SPIKESEL_10NS = 1 -DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' -DCIOCHIP_AUX_VOD_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_VOD_TUNE_0', - 1: 'DCIOCHIP_AUX_VOD_TUNE_1', - 2: 'DCIOCHIP_AUX_VOD_TUNE_2', - 3: 'DCIOCHIP_AUX_VOD_TUNE_3', -} -DCIOCHIP_AUX_VOD_TUNE_0 = 0 -DCIOCHIP_AUX_VOD_TUNE_1 = 1 -DCIOCHIP_AUX_VOD_TUNE_2 = 2 -DCIOCHIP_AUX_VOD_TUNE_3 = 3 -DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' -DCIOCHIP_GPIO_MASK_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', -} -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 -DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_HPD_SEL' -DCIOCHIP_HPD_SEL__enumvalues = { - 0: 'DCIOCHIP_HPD_SEL_ASYNC', - 1: 'DCIOCHIP_HPD_SEL_CLOCKED', -} -DCIOCHIP_HPD_SEL_ASYNC = 0 -DCIOCHIP_HPD_SEL_CLOCKED = 1 -DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_COMPSEL' -DCIOCHIP_I2C_COMPSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_REC_SCHMIT', - 1: 'DCIOCHIP_I2C_REC_COMPARATOR', -} -DCIOCHIP_I2C_REC_SCHMIT = 0 -DCIOCHIP_I2C_REC_COMPARATOR = 1 -DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' -DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', - 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', - 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', -} -DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 -DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 -DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 -DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 -DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' -DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', - 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', -} -DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 -DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 -DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 -DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 -DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' -DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { - 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', - 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', -} -DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 -DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 -DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_INVERT' -DCIOCHIP_INVERT__enumvalues = { - 0: 'DCIOCHIP_POL_NON_INVERT', - 1: 'DCIOCHIP_POL_INVERT', -} -DCIOCHIP_POL_NON_INVERT = 0 -DCIOCHIP_POL_INVERT = 1 -DCIOCHIP_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK' -DCIOCHIP_MASK__enumvalues = { - 0: 'DCIOCHIP_MASK_DISABLE', - 1: 'DCIOCHIP_MASK_ENABLE', -} -DCIOCHIP_MASK_DISABLE = 0 -DCIOCHIP_MASK_ENABLE = 1 -DCIOCHIP_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PAD_MODE' -DCIOCHIP_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_PAD_MODE_DDC', - 1: 'DCIOCHIP_PAD_MODE_DP', -} -DCIOCHIP_PAD_MODE_DDC = 0 -DCIOCHIP_PAD_MODE_DP = 1 -DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PD_EN' -DCIOCHIP_PD_EN__enumvalues = { - 0: 'DCIOCHIP_PD_EN_NOTALLOW', - 1: 'DCIOCHIP_PD_EN_ALLOW', -} -DCIOCHIP_PD_EN_NOTALLOW = 0 -DCIOCHIP_PD_EN_ALLOW = 1 -DCIOCHIP_PD_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' -DCIOCHIP_REF_27_SRC_SEL__enumvalues = { - 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', -} -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 -DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', -} -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', -} -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { - 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', -} -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_DISABLE', - 1: 'PWRSEQ_BL_PWM_ENABLE', -} -PWRSEQ_BL_PWM_DISABLE = 0 -PWRSEQ_BL_PWM_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', -} -PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 -PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', -} -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', -} -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' -PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_GPIO_MASK_EN' -PWRSEQ_GPIO_MASK_EN__enumvalues = { - 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', -} -PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 -PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 -PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_OFF', - 1: 'PWRSEQ_PANEL_BLON_ON', -} -PWRSEQ_PANEL_BLON_OFF = 0 -PWRSEQ_PANEL_BLON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', -} -PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_BLON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_OFF', - 1: 'PWRSEQ_PANEL_DIGON_ON', -} -PWRSEQ_PANEL_DIGON_OFF = 0 -PWRSEQ_PANEL_DIGON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', -} -PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_DIGON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', -} -PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 -PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { - 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', -} -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { - 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', -} -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_CORB_SIZE' -AZ_CORB_SIZE__enumvalues = { - 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_CORB_SIZE_256ENTRIES', - 3: 'AZ_CORB_SIZE_RESERVED', -} -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 -AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 -AZ_CORB_SIZE_256ENTRIES = 2 -AZ_CORB_SIZE_RESERVED = 3 -AZ_CORB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_GLOBAL_CAPABILITIES' -AZ_GLOBAL_CAPABILITIES__enumvalues = { - 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', -} -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 -AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_SIZE' -AZ_RIRB_SIZE__enumvalues = { - 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_RIRB_SIZE_256ENTRIES', - 3: 'AZ_RIRB_SIZE_UNDEFINED', -} -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 -AZ_RIRB_SIZE_256ENTRIES = 2 -AZ_RIRB_SIZE_UNDEFINED = 3 -AZ_RIRB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' -AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { - 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', - 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', -} -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 -AZ_RIRB_WRITE_POINTER_DO_RESET = 1 -AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_STATE_CHANGE_STATUS' -AZ_STATE_CHANGE_STATUS__enumvalues = { - 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', -} -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 -AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'CORB_READ_POINTER_RESET' -CORB_READ_POINTER_RESET__enumvalues = { - 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', -} -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 -CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { - 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', -} -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { - 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', - 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', -} -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' -GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { - 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', -} -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 -GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' -GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { - 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 1: 'FLUSH_CONTROL_FLUSH_STARTED', -} -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 -FLUSH_CONTROL_FLUSH_STARTED = 1 -GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' -GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { - 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', -} -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 -GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_0_SYNCHRONIZATION' -STREAM_0_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_10_SYNCHRONIZATION' -STREAM_10_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_11_SYNCHRONIZATION' -STREAM_11_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_12_SYNCHRONIZATION' -STREAM_12_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_13_SYNCHRONIZATION' -STREAM_13_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_14_SYNCHRONIZATION' -STREAM_14_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_15_SYNCHRONIZATION' -STREAM_15_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_1_SYNCHRONIZATION' -STREAM_1_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_2_SYNCHRONIZATION' -STREAM_2_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_3_SYNCHRONIZATION' -STREAM_3_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_4_SYNCHRONIZATION' -STREAM_4_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_5_SYNCHRONIZATION' -STREAM_5_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_6_SYNCHRONIZATION' -STREAM_6_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_7_SYNCHRONIZATION' -STREAM_7_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_8_SYNCHRONIZATION' -STREAM_8_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_9_SYNCHRONIZATION' -STREAM_9_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', -} -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { - 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', -} -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_CTRL' -MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'ENABLE_MEM_PWR_CTRL', - 1: 'DISABLE_MEM_PWR_CTRL', -} -ENABLE_MEM_PWR_CTRL = 0 -DISABLE_MEM_PWR_CTRL = 1 -MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL' -MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'NO_FORCE_REQUEST', - 1: 'FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FORCE_DEEP_SLEEP_REQUEST', - 3: 'FORCE_SHUT_DOWN_REQUEST', -} -NO_FORCE_REQUEST = 0 -FORCE_LIGHT_SLEEP_REQUEST = 1 -FORCE_DEEP_SLEEP_REQUEST = 2 -FORCE_SHUT_DOWN_REQUEST = 3 -MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL2' -MEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'NO_FORCE_REQ', - 1: 'FORCE_LIGHT_SLEEP_REQ', -} -NO_FORCE_REQ = 0 -FORCE_LIGHT_SLEEP_REQ = 1 -MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL' -MEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DYNAMIC_SHUT_DOWN_ENABLE = 0 -DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL2' -MEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DYNAMIC_DEEP_SLEEP_EN', - 1: 'DYNAMIC_LIGHT_SLEEP_EN', -} -DYNAMIC_DEEP_SLEEP_EN = 0 -DYNAMIC_LIGHT_SLEEP_EN = 1 -MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { - 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', -} -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' -AZ_LATENCY_COUNTER_CONTROL__enumvalues = { - 0: 'AZ_LATENCY_COUNTER_NO_RESET', - 1: 'AZ_LATENCY_COUNTER_RESET_DONE', -} -AZ_LATENCY_COUNTER_NO_RESET = 0 -AZ_LATENCY_COUNTER_RESET_DONE = 1 -AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', -} -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' -DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' -DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', -} -DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 -DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' -DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', -} -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 -DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ENABLE_ENUM' -DSCC_ENABLE_ENUM__enumvalues = { - 0: 'DSCC_ENABLE_ENUM_DISABLED', - 1: 'DSCC_ENABLE_ENUM_ENABLED', -} -DSCC_ENABLE_ENUM_DISABLED = 0 -DSCC_ENABLE_ENUM_ENABLED = 1 -DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ICH_RESET_ENUM' -DSCC_ICH_RESET_ENUM__enumvalues = { - 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', -} -DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 -DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 -DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 -DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 -DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' -DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { - 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', -} -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 -DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' -DSCC_MEM_PWR_DIS_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', - 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', -} -DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 -DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 -DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' -DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', -} -DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 -DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'POWER_STATE_ENUM' -POWER_STATE_ENUM__enumvalues = { - 0: 'POWER_STATE_ENUM_ON', - 1: 'POWER_STATE_ENUM_LS', - 2: 'POWER_STATE_ENUM_DS', - 3: 'POWER_STATE_ENUM_SD', -} -POWER_STATE_ENUM_ON = 0 -POWER_STATE_ENUM_LS = 1 -POWER_STATE_ENUM_DS = 2 -POWER_STATE_ENUM_SD = 3 -POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' -DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_ENABLE_ENUM' -DSCCIF_ENABLE_ENUM__enumvalues = { - 0: 'DSCCIF_ENABLE_ENUM_DISABLED', - 1: 'DSCCIF_ENABLE_ENUM_ENABLED', -} -DSCCIF_ENABLE_ENUM_DISABLED = 0 -DSCCIF_ENABLE_ENUM_ENABLED = 1 -DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' -DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', -} -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' -CLOCK_GATING_DISABLE_ENUM__enumvalues = { - 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', - 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', -} -CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 -CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 -CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_ENUM' -ENABLE_ENUM__enumvalues = { - 0: 'ENABLE_ENUM_DISABLED', - 1: 'ENABLE_ENUM_ENABLED', -} -ENABLE_ENUM_DISABLED = 0 -ENABLE_ENUM_ENABLED = 1 -ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' -TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { - 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', -} -TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 -TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 -TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 -TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 -TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 -TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 -TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_CONT_EN_ENUM' -DWB_CRC_CONT_EN_ENUM__enumvalues = { - 0: 'DWB_CRC_CONT_EN_ONE_SHOT', - 1: 'DWB_CRC_CONT_EN_CONT', -} -DWB_CRC_CONT_EN_ONE_SHOT = 0 -DWB_CRC_CONT_EN_CONT = 1 -DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' -DWB_CRC_SRC_SEL_ENUM__enumvalues = { - 0: 'DWB_CRC_SRC_SEL_DWB_IN', - 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', - 2: 'DWB_CRC_SRC_SEL_DWB_OUT', -} -DWB_CRC_SRC_SEL_DWB_IN = 0 -DWB_CRC_SRC_SEL_OGAM_OUT = 1 -DWB_CRC_SRC_SEL_DWB_OUT = 2 -DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' -DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', - 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', -} -DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 -DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 -DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' -DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', - 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', -} -DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 -DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 -DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 -DWB_DATA_OVERFLOW_TYPE_VREADY = 3 -DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DEBUG_SEL_ENUM' -DWB_DEBUG_SEL_ENUM__enumvalues = { - 0: 'DWB_DEBUG_SEL_FC', - 1: 'DWB_DEBUG_SEL_RESERVED', - 2: 'DWB_DEBUG_SEL_DWBCP', - 3: 'DWB_DEBUG_SEL_PERFMON', -} -DWB_DEBUG_SEL_FC = 0 -DWB_DEBUG_SEL_RESERVED = 1 -DWB_DEBUG_SEL_DWBCP = 2 -DWB_DEBUG_SEL_PERFMON = 3 -DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' -DWB_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_FORCE_DIS', - 1: 'DWB_MEM_PWR_FORCE_LS', - 2: 'DWB_MEM_PWR_FORCE_DS', - 3: 'DWB_MEM_PWR_FORCE_SD', -} -DWB_MEM_PWR_FORCE_DIS = 0 -DWB_MEM_PWR_FORCE_LS = 1 -DWB_MEM_PWR_FORCE_DS = 2 -DWB_MEM_PWR_FORCE_SD = 3 -DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' -DWB_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_STATE_ON', - 1: 'DWB_MEM_PWR_STATE_LS', - 2: 'DWB_MEM_PWR_STATE_DS', - 3: 'DWB_MEM_PWR_STATE_SD', -} -DWB_MEM_PWR_STATE_ON = 0 -DWB_MEM_PWR_STATE_LS = 1 -DWB_MEM_PWR_STATE_DS = 2 -DWB_MEM_PWR_STATE_SD = 3 -DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' -DWB_TEST_CLK_SEL_ENUM__enumvalues = { - 0: 'DWB_TEST_CLK_SEL_R', - 1: 'DWB_TEST_CLK_SEL_G', - 2: 'DWB_TEST_CLK_SEL_P', -} -DWB_TEST_CLK_SEL_R = 0 -DWB_TEST_CLK_SEL_G = 1 -DWB_TEST_CLK_SEL_P = 2 -DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_EYE_SELECTION_ENUM' -FC_EYE_SELECTION_ENUM__enumvalues = { - 0: 'FC_EYE_SELECTION_STEREO_DIS', - 1: 'FC_EYE_SELECTION_LEFT_EYE', - 2: 'FC_EYE_SELECTION_RIGHT_EYE', -} -FC_EYE_SELECTION_STEREO_DIS = 0 -FC_EYE_SELECTION_LEFT_EYE = 1 -FC_EYE_SELECTION_RIGHT_EYE = 2 -FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' -FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { - 0: 'FC_FRAME_CAPTURE_RATE_FULL', - 1: 'FC_FRAME_CAPTURE_RATE_HALF', - 2: 'FC_FRAME_CAPTURE_RATE_THIRD', - 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', -} -FC_FRAME_CAPTURE_RATE_FULL = 0 -FC_FRAME_CAPTURE_RATE_HALF = 1 -FC_FRAME_CAPTURE_RATE_THIRD = 2 -FC_FRAME_CAPTURE_RATE_QUARTER = 3 -FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' -FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { - 0: 'FC_STEREO_EYE_POLARITY_LEFT', - 1: 'FC_STEREO_EYE_POLARITY_RIGHT', -} -FC_STEREO_EYE_POLARITY_LEFT = 0 -FC_STEREO_EYE_POLARITY_RIGHT = 1 -FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' -DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', - 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', - 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', - 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', -} -DWB_GAMUT_REMAP_MODE_BYPASS = 0 -DWB_GAMUT_REMAP_MODE_COEF_A = 1 -DWB_GAMUT_REMAP_MODE_COEF_B = 2 -DWB_GAMUT_REMAP_MODE_RESERVED = 3 -DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_LUT_NUM_SEG' -DWB_LUT_NUM_SEG__enumvalues = { - 0: 'DWB_SEGMENTS_1', - 1: 'DWB_SEGMENTS_2', - 2: 'DWB_SEGMENTS_4', - 3: 'DWB_SEGMENTS_8', - 4: 'DWB_SEGMENTS_16', - 5: 'DWB_SEGMENTS_32', - 6: 'DWB_SEGMENTS_64', - 7: 'DWB_SEGMENTS_128', -} -DWB_SEGMENTS_1 = 0 -DWB_SEGMENTS_2 = 1 -DWB_SEGMENTS_4 = 2 -DWB_SEGMENTS_8 = 3 -DWB_SEGMENTS_16 = 4 -DWB_SEGMENTS_32 = 5 -DWB_SEGMENTS_64 = 6 -DWB_SEGMENTS_128 = 7 -DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' -DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', - 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', -} -DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 -DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 -DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' -DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', - 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', -} -DWB_OGAM_LUT_HOST_SEL_RAMA = 0 -DWB_OGAM_LUT_HOST_SEL_RAMB = 1 -DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', - 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', -} -DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 -DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 -DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 -DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' -DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', - 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', -} -DWB_OGAM_LUT_READ_DBG_DISABLE = 0 -DWB_OGAM_LUT_READ_DBG_ENABLE = 1 -DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_MODE_ENUM' -DWB_OGAM_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_MODE_BYPASS', - 1: 'DWB_OGAM_MODE_RESERVED', - 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', -} -DWB_OGAM_MODE_BYPASS = 0 -DWB_OGAM_MODE_RESERVED = 1 -DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 -DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' -DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { - 0: 'DWB_OGAM_PWL_DISABLE_FALSE', - 1: 'DWB_OGAM_PWL_DISABLE_TRUE', -} -DWB_OGAM_PWL_DISABLE_FALSE = 0 -DWB_OGAM_PWL_DISABLE_TRUE = 1 -DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_SELECT_ENUM' -DWB_OGAM_SELECT_ENUM__enumvalues = { - 0: 'DWB_OGAM_SELECT_A', - 1: 'DWB_OGAM_SELECT_B', -} -DWB_OGAM_SELECT_A = 0 -DWB_OGAM_SELECT_B = 1 -DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN' -RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = { - 0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', - 1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', -} -RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0 -RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = { - 0: 'RDPCSPIPE_APBCLK_DISABLE', - 1: 'RDPCSPIPE_APBCLK_ENABLE', -} -RDPCSPIPE_APBCLK_DISABLE = 0 -RDPCSPIPE_APBCLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_PIPE_CLK_CLOCK_OFF', - 1: 'RDPCS_PIPE_CLK_CLOCK_ON', -} -RDPCS_PIPE_CLK_CLOCK_OFF = 0 -RDPCS_PIPE_CLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = { - 0: 'RDPCS_PIPE_CLK_DISABLE', - 1: 'RDPCS_PIPE_CLK_ENABLE', -} -RDPCS_PIPE_CLK_DISABLE = 0 -RDPCS_PIPE_CLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_PIPE_CLK_GATE_ENABLE', - 1: 'RDPCS_PIPE_CLK_GATE_DISABLE', -} -RDPCS_PIPE_CLK_GATE_ENABLE = 0 -RDPCS_PIPE_CLK_GATE_DISABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', - 1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', -} -RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0 -RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { - 0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', - 1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', -} -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0 -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_DISABLE', - 1: 'RDPCSPIPE_SRAMCLK_ENABLE', -} -RDPCSPIPE_SRAMCLK_DISABLE = 0 -RDPCSPIPE_SRAMCLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', - 1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', -} -RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0 -RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_NOT_PASS', - 1: 'RDPCSPIPE_SRAMCLK_PASS', -} -RDPCSPIPE_SRAMCLK_NOT_PASS = 0 -RDPCSPIPE_SRAMCLK_PASS = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN' -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = { - 0: 'RDPCS_PIPE_FIFO_DISABLE', - 1: 'RDPCS_PIPE_FIFO_ENABLE', -} -RDPCS_PIPE_FIFO_DISABLE = 0 -RDPCS_PIPE_FIFO_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN' -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = { - 0: 'RDPCS_PIPE_FIFO_LANE_DISABLE', - 1: 'RDPCS_PIPE_FIFO_LANE_ENABLE', -} -RDPCS_PIPE_FIFO_LANE_DISABLE = 0 -RDPCS_PIPE_FIFO_LANE_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET' -RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = { - 0: 'RDPCS_PIPE_SOFT_RESET_DISABLE', - 1: 'RDPCS_PIPE_SOFT_RESET_ENABLE', -} -RDPCS_PIPE_SOFT_RESET_DISABLE = 0 -RDPCS_PIPE_SOFT_RESET_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET' -RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { - 0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', - 1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', -} -RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0 -RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK' -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', - 1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', -} -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0 -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1 -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL' -RDPCSPIPE_DBG_OCLA_SEL__enumvalues = { - 0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', - 1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', - 2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', - 3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', - 4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', - 5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', - 6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', - 7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', -} -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7 -RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_ENC_TYPE' -RDPCSPIPE_ENC_TYPE__enumvalues = { - 0: 'HDMI_TMDS_OR_DP_8B10B', - 1: 'HDMI_FRL', - 2: 'DP_128B132B', -} -HDMI_TMDS_OR_DP_8B10B = 0 -HDMI_FRL = 1 -DP_128B132B = 2 -RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_FIFO_EMPTY' -RDPCSPIPE_FIFO_EMPTY__enumvalues = { - 0: 'RDPCSPIPE_FIFO_NOT_EMPTY', - 1: 'RDPCSPIPE_FIFO_IS_EMPTY', -} -RDPCSPIPE_FIFO_NOT_EMPTY = 0 -RDPCSPIPE_FIFO_IS_EMPTY = 1 -RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_FIFO_FULL' -RDPCSPIPE_FIFO_FULL__enumvalues = { - 0: 'RDPCSPIPE_FIFO_NOT_FULL', - 1: 'RDPCSPIPE_FIFO_IS_FULL', -} -RDPCSPIPE_FIFO_NOT_FULL = 0 -RDPCSPIPE_FIFO_IS_FULL = 1 -RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = { - 0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', - 1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', -} -RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0 -RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { - 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', - 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', -} -RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0 -RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', -} -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { - 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', - 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', -} -RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0 -RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', -} -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', -} -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0 -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', -} -RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0 -RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK' -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = { - 0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', - 1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', -} -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0 -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1 -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PACK_MODE' -RDPCSPIPE_PACK_MODE__enumvalues = { - 0: 'TIGHT_PACK', - 1: 'LOOSE_PACK', -} -TIGHT_PACK = 0 -LOOSE_PACK = 1 -RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { - 0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', - 1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', -} -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0 -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { - 0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', - 1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', -} -RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0 -RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { - 0: 'RDPCSPIPE_PHY_REF_RANGE_0', - 1: 'RDPCSPIPE_PHY_REF_RANGE_1', - 2: 'RDPCSPIPE_PHY_REF_RANGE_2', - 3: 'RDPCSPIPE_PHY_REF_RANGE_3', - 4: 'RDPCSPIPE_PHY_REF_RANGE_4', - 5: 'RDPCSPIPE_PHY_REF_RANGE_5', - 6: 'RDPCSPIPE_PHY_REF_RANGE_6', - 7: 'RDPCSPIPE_PHY_REF_RANGE_7', -} -RDPCSPIPE_PHY_REF_RANGE_0 = 0 -RDPCSPIPE_PHY_REF_RANGE_1 = 1 -RDPCSPIPE_PHY_REF_RANGE_2 = 2 -RDPCSPIPE_PHY_REF_RANGE_3 = 3 -RDPCSPIPE_PHY_REF_RANGE_4 = 4 -RDPCSPIPE_PHY_REF_RANGE_5 = 5 -RDPCSPIPE_PHY_REF_RANGE_6 = 6 -RDPCSPIPE_PHY_REF_RANGE_7 = 7 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { - 0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', - 1: 'RDPCSPIPE_SRAM_EXT_LD_DONE', -} -RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0 -RDPCSPIPE_SRAM_EXT_LD_DONE = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { - 0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE', - 1: 'RDPCSPIPE_SRAM_INIT_DONE', -} -RDPCSPIPE_SRAM_INIT_NOT_DONE = 0 -RDPCSPIPE_SRAM_INIT_DONE = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', - 1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', - 2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', - 3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', - 4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', -} -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', -} -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' -RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', - 1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', - 2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', - 3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', - 4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', - 5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', - 6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', - 7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', -} -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 -RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' -RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', - 1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', - 2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', - 3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', - 4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', - 5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', - 6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', - 7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', -} -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7 -RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', -} -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_RATE', - 1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', - 2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', -} -RDPCSPIPE_PHY_DP_TX_RATE = 0 -RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1 -RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', - 1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', - 2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', - 3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', -} -RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0 -RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1 -RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2 -RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' -RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { - 0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', - 1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', - 2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', - 3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', -} -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0 -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1 -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2 -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3 -RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH' -RDPCSPIPE_PHY_IF_WIDTH__enumvalues = { - 0: 'PHY_IF_WIDTH_10BIT', - 1: 'PHY_IF_WIDTH_20BIT', - 2: 'PHY_IF_WIDTH_40BIT', - 3: 'PHY_IF_WIDTH_80BIT', -} -PHY_IF_WIDTH_10BIT = 0 -PHY_IF_WIDTH_20BIT = 1 -PHY_IF_WIDTH_40BIT = 2 -PHY_IF_WIDTH_80BIT = 3 -RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_RATE' -RDPCSPIPE_PHY_RATE__enumvalues = { - 0: 'PHY_DP_RATE_1P62', - 1: 'PHY_DP_RATE_2P7', - 2: 'PHY_DP_RATE_5P4', - 3: 'PHY_DP_RATE_8P1', - 4: 'PHY_DP_RATE_2P16', - 5: 'PHY_DP_RATE_2P43', - 6: 'PHY_DP_RATE_3P24', - 7: 'PHY_DP_RATE_4P32', - 8: 'PHY_DP_RATE_10P', - 9: 'PHY_DP_RATE_13P5', - 10: 'PHY_DP_RATE_20P', - 15: 'PHY_CUSTOM_RATE', -} -PHY_DP_RATE_1P62 = 0 -PHY_DP_RATE_2P7 = 1 -PHY_DP_RATE_5P4 = 2 -PHY_DP_RATE_8P1 = 3 -PHY_DP_RATE_2P16 = 4 -PHY_DP_RATE_2P43 = 5 -PHY_DP_RATE_3P24 = 6 -PHY_DP_RATE_4P32 = 7 -PHY_DP_RATE_10P = 8 -PHY_DP_RATE_13P5 = 9 -PHY_DP_RATE_20P = 10 -PHY_CUSTOM_RATE = 15 -RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN' -RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = { - 0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', - 1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', -} -RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0 -RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1 -RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL' -RDPCSPIPE_TEST_CLK_SEL__enumvalues = { - 0: 'RDPCSPIPE_TEST_CLK_SEL_NONE', - 1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', - 2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', - 7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', - 8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', - 16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', - 17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', -} -RDPCSPIPE_TEST_CLK_SEL_NONE = 0 -RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 -RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6 -RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7 -RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 -RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 -RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 -RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 -RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 -RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 -RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 -RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15 -RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16 -RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17 -RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB' -RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { - 0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', - 1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', -} -RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0 -RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1 -RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { - 0: 'RDPCSPIPE_MEM_PWR_NO_FORCE', - 1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', - 2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', - 3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', -} -RDPCSPIPE_MEM_PWR_NO_FORCE = 0 -RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1 -RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2 -RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3 -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { - 0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', - 1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', -} -RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0 -RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 -RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 -RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' -RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { - 0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', - 1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', -} -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0 -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1 -RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum - -# values for enumeration 'GDS_PERFCOUNT_SELECT' -GDS_PERFCOUNT_SELECT__enumvalues = { - 0: 'GDS_PERF_SEL_WR_COMP', - 1: 'GDS_PERF_SEL_WBUF_WR', - 2: 'GDS_PERF_SEL_SE0_NORET', - 3: 'GDS_PERF_SEL_SE0_RET', - 4: 'GDS_PERF_SEL_SE0_ORD_CNT', - 5: 'GDS_PERF_SEL_SE0_2COMP_REQ', - 6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', - 7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', - 8: 'GDS_PERF_SEL_SE0_GDS_WR_OP', - 9: 'GDS_PERF_SEL_SE0_GDS_RD_OP', - 10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', - 11: 'GDS_PERF_SEL_SE0_GDS_REL_OP', - 12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', - 13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', - 14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', - 15: 'GDS_PERF_SEL_SE1_NORET', - 16: 'GDS_PERF_SEL_SE1_RET', - 17: 'GDS_PERF_SEL_SE1_ORD_CNT', - 18: 'GDS_PERF_SEL_SE1_2COMP_REQ', - 19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', - 20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', - 21: 'GDS_PERF_SEL_SE1_GDS_WR_OP', - 22: 'GDS_PERF_SEL_SE1_GDS_RD_OP', - 23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', - 24: 'GDS_PERF_SEL_SE1_GDS_REL_OP', - 25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', - 26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', - 27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', - 28: 'GDS_PERF_SEL_SE2_NORET', - 29: 'GDS_PERF_SEL_SE2_RET', - 30: 'GDS_PERF_SEL_SE2_ORD_CNT', - 31: 'GDS_PERF_SEL_SE2_2COMP_REQ', - 32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', - 33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', - 34: 'GDS_PERF_SEL_SE2_GDS_WR_OP', - 35: 'GDS_PERF_SEL_SE2_GDS_RD_OP', - 36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', - 37: 'GDS_PERF_SEL_SE2_GDS_REL_OP', - 38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', - 39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', - 40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', - 41: 'GDS_PERF_SEL_SE3_NORET', - 42: 'GDS_PERF_SEL_SE3_RET', - 43: 'GDS_PERF_SEL_SE3_ORD_CNT', - 44: 'GDS_PERF_SEL_SE3_2COMP_REQ', - 45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', - 46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', - 47: 'GDS_PERF_SEL_SE3_GDS_WR_OP', - 48: 'GDS_PERF_SEL_SE3_GDS_RD_OP', - 49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', - 50: 'GDS_PERF_SEL_SE3_GDS_REL_OP', - 51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', - 52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', - 53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', - 54: 'GDS_PERF_SEL_SE4_NORET', - 55: 'GDS_PERF_SEL_SE4_RET', - 56: 'GDS_PERF_SEL_SE4_ORD_CNT', - 57: 'GDS_PERF_SEL_SE4_2COMP_REQ', - 58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', - 59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', - 60: 'GDS_PERF_SEL_SE4_GDS_WR_OP', - 61: 'GDS_PERF_SEL_SE4_GDS_RD_OP', - 62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', - 63: 'GDS_PERF_SEL_SE4_GDS_REL_OP', - 64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', - 65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', - 66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', - 67: 'GDS_PERF_SEL_SE5_NORET', - 68: 'GDS_PERF_SEL_SE5_RET', - 69: 'GDS_PERF_SEL_SE5_ORD_CNT', - 70: 'GDS_PERF_SEL_SE5_2COMP_REQ', - 71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', - 72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', - 73: 'GDS_PERF_SEL_SE5_GDS_WR_OP', - 74: 'GDS_PERF_SEL_SE5_GDS_RD_OP', - 75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', - 76: 'GDS_PERF_SEL_SE5_GDS_REL_OP', - 77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', - 78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', - 79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', - 80: 'GDS_PERF_SEL_SE6_NORET', - 81: 'GDS_PERF_SEL_SE6_RET', - 82: 'GDS_PERF_SEL_SE6_ORD_CNT', - 83: 'GDS_PERF_SEL_SE6_2COMP_REQ', - 84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', - 85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', - 86: 'GDS_PERF_SEL_SE6_GDS_WR_OP', - 87: 'GDS_PERF_SEL_SE6_GDS_RD_OP', - 88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', - 89: 'GDS_PERF_SEL_SE6_GDS_REL_OP', - 90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', - 91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', - 92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', - 93: 'GDS_PERF_SEL_SE7_NORET', - 94: 'GDS_PERF_SEL_SE7_RET', - 95: 'GDS_PERF_SEL_SE7_ORD_CNT', - 96: 'GDS_PERF_SEL_SE7_2COMP_REQ', - 97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', - 98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', - 99: 'GDS_PERF_SEL_SE7_GDS_WR_OP', - 100: 'GDS_PERF_SEL_SE7_GDS_RD_OP', - 101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', - 102: 'GDS_PERF_SEL_SE7_GDS_REL_OP', - 103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', - 104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', - 105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', - 106: 'GDS_PERF_SEL_GWS_RELEASED', - 107: 'GDS_PERF_SEL_GWS_BYPASS', -} -GDS_PERF_SEL_WR_COMP = 0 -GDS_PERF_SEL_WBUF_WR = 1 -GDS_PERF_SEL_SE0_NORET = 2 -GDS_PERF_SEL_SE0_RET = 3 -GDS_PERF_SEL_SE0_ORD_CNT = 4 -GDS_PERF_SEL_SE0_2COMP_REQ = 5 -GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6 -GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7 -GDS_PERF_SEL_SE0_GDS_WR_OP = 8 -GDS_PERF_SEL_SE0_GDS_RD_OP = 9 -GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10 -GDS_PERF_SEL_SE0_GDS_REL_OP = 11 -GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12 -GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13 -GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14 -GDS_PERF_SEL_SE1_NORET = 15 -GDS_PERF_SEL_SE1_RET = 16 -GDS_PERF_SEL_SE1_ORD_CNT = 17 -GDS_PERF_SEL_SE1_2COMP_REQ = 18 -GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19 -GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20 -GDS_PERF_SEL_SE1_GDS_WR_OP = 21 -GDS_PERF_SEL_SE1_GDS_RD_OP = 22 -GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23 -GDS_PERF_SEL_SE1_GDS_REL_OP = 24 -GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25 -GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26 -GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27 -GDS_PERF_SEL_SE2_NORET = 28 -GDS_PERF_SEL_SE2_RET = 29 -GDS_PERF_SEL_SE2_ORD_CNT = 30 -GDS_PERF_SEL_SE2_2COMP_REQ = 31 -GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32 -GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33 -GDS_PERF_SEL_SE2_GDS_WR_OP = 34 -GDS_PERF_SEL_SE2_GDS_RD_OP = 35 -GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36 -GDS_PERF_SEL_SE2_GDS_REL_OP = 37 -GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38 -GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39 -GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40 -GDS_PERF_SEL_SE3_NORET = 41 -GDS_PERF_SEL_SE3_RET = 42 -GDS_PERF_SEL_SE3_ORD_CNT = 43 -GDS_PERF_SEL_SE3_2COMP_REQ = 44 -GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45 -GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46 -GDS_PERF_SEL_SE3_GDS_WR_OP = 47 -GDS_PERF_SEL_SE3_GDS_RD_OP = 48 -GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49 -GDS_PERF_SEL_SE3_GDS_REL_OP = 50 -GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51 -GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52 -GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53 -GDS_PERF_SEL_SE4_NORET = 54 -GDS_PERF_SEL_SE4_RET = 55 -GDS_PERF_SEL_SE4_ORD_CNT = 56 -GDS_PERF_SEL_SE4_2COMP_REQ = 57 -GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58 -GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59 -GDS_PERF_SEL_SE4_GDS_WR_OP = 60 -GDS_PERF_SEL_SE4_GDS_RD_OP = 61 -GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62 -GDS_PERF_SEL_SE4_GDS_REL_OP = 63 -GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64 -GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65 -GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66 -GDS_PERF_SEL_SE5_NORET = 67 -GDS_PERF_SEL_SE5_RET = 68 -GDS_PERF_SEL_SE5_ORD_CNT = 69 -GDS_PERF_SEL_SE5_2COMP_REQ = 70 -GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71 -GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72 -GDS_PERF_SEL_SE5_GDS_WR_OP = 73 -GDS_PERF_SEL_SE5_GDS_RD_OP = 74 -GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75 -GDS_PERF_SEL_SE5_GDS_REL_OP = 76 -GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77 -GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78 -GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79 -GDS_PERF_SEL_SE6_NORET = 80 -GDS_PERF_SEL_SE6_RET = 81 -GDS_PERF_SEL_SE6_ORD_CNT = 82 -GDS_PERF_SEL_SE6_2COMP_REQ = 83 -GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84 -GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85 -GDS_PERF_SEL_SE6_GDS_WR_OP = 86 -GDS_PERF_SEL_SE6_GDS_RD_OP = 87 -GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88 -GDS_PERF_SEL_SE6_GDS_REL_OP = 89 -GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90 -GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91 -GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92 -GDS_PERF_SEL_SE7_NORET = 93 -GDS_PERF_SEL_SE7_RET = 94 -GDS_PERF_SEL_SE7_ORD_CNT = 95 -GDS_PERF_SEL_SE7_2COMP_REQ = 96 -GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97 -GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98 -GDS_PERF_SEL_SE7_GDS_WR_OP = 99 -GDS_PERF_SEL_SE7_GDS_RD_OP = 100 -GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101 -GDS_PERF_SEL_SE7_GDS_REL_OP = 102 -GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103 -GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104 -GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105 -GDS_PERF_SEL_GWS_RELEASED = 106 -GDS_PERF_SEL_GWS_BYPASS = 107 -GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOp' -BlendOp__enumvalues = { - 0: 'BLEND_ZERO', - 1: 'BLEND_ONE', - 2: 'BLEND_SRC_COLOR', - 3: 'BLEND_ONE_MINUS_SRC_COLOR', - 4: 'BLEND_SRC_ALPHA', - 5: 'BLEND_ONE_MINUS_SRC_ALPHA', - 6: 'BLEND_DST_ALPHA', - 7: 'BLEND_ONE_MINUS_DST_ALPHA', - 8: 'BLEND_DST_COLOR', - 9: 'BLEND_ONE_MINUS_DST_COLOR', - 10: 'BLEND_SRC_ALPHA_SATURATE', - 11: 'BLEND_CONSTANT_COLOR', - 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', - 13: 'BLEND_SRC1_COLOR', - 14: 'BLEND_INV_SRC1_COLOR', - 15: 'BLEND_SRC1_ALPHA', - 16: 'BLEND_INV_SRC1_ALPHA', - 17: 'BLEND_CONSTANT_ALPHA', - 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', -} -BLEND_ZERO = 0 -BLEND_ONE = 1 -BLEND_SRC_COLOR = 2 -BLEND_ONE_MINUS_SRC_COLOR = 3 -BLEND_SRC_ALPHA = 4 -BLEND_ONE_MINUS_SRC_ALPHA = 5 -BLEND_DST_ALPHA = 6 -BLEND_ONE_MINUS_DST_ALPHA = 7 -BLEND_DST_COLOR = 8 -BLEND_ONE_MINUS_DST_COLOR = 9 -BLEND_SRC_ALPHA_SATURATE = 10 -BLEND_CONSTANT_COLOR = 11 -BLEND_ONE_MINUS_CONSTANT_COLOR = 12 -BLEND_SRC1_COLOR = 13 -BLEND_INV_SRC1_COLOR = 14 -BLEND_SRC1_ALPHA = 15 -BLEND_INV_SRC1_ALPHA = 16 -BLEND_CONSTANT_ALPHA = 17 -BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 -BlendOp = ctypes.c_uint32 # enum -GL__ZERO = BLEND_ZERO # macro -GL__ONE = BLEND_ONE # macro -GL__SRC_COLOR = BLEND_SRC_COLOR # macro -GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro -GL__DST_COLOR = BLEND_DST_COLOR # macro -GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro -GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro -GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro -GL__DST_ALPHA = BLEND_DST_ALPHA # macro -GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro -GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro -GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro -GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro -GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro -GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro - -# values for enumeration 'BlendOpt' -BlendOpt__enumvalues = { - 0: 'FORCE_OPT_AUTO', - 1: 'FORCE_OPT_DISABLE', - 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', - 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', - 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', -} -FORCE_OPT_AUTO = 0 -FORCE_OPT_DISABLE = 1 -FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 -FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 -BlendOpt = ctypes.c_uint32 # enum - -# values for enumeration 'CBMode' -CBMode__enumvalues = { - 0: 'CB_DISABLE', - 1: 'CB_NORMAL', - 2: 'CB_ELIMINATE_FAST_CLEAR', - 3: 'CB_DCC_DECOMPRESS', - 4: 'CB_RESERVED', -} -CB_DISABLE = 0 -CB_NORMAL = 1 -CB_ELIMINATE_FAST_CLEAR = 2 -CB_DCC_DECOMPRESS = 3 -CB_RESERVED = 4 -CBMode = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfClearFilterSel' -CBPerfClearFilterSel__enumvalues = { - 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', -} -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 -CBPerfClearFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfOpFilterSel' -CBPerfOpFilterSel__enumvalues = { - 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', -} -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 -CB_PERF_OP_FILTER_SEL_RESOLVE = 2 -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 -CBPerfOpFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfSel' -CBPerfSel__enumvalues = { - 0: 'CB_PERF_SEL_NONE', - 1: 'CB_PERF_SEL_DRAWN_PIXEL', - 2: 'CB_PERF_SEL_DRAWN_QUAD', - 3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', - 4: 'CB_PERF_SEL_DRAWN_TILE', - 5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', - 6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD', - 7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', - 8: 'CB_PERF_SEL_FILTER_DRAWN_TILE', - 9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', - 10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', - 11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', - 12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', - 13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 15: 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', - 19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 21: 'CB_PERF_SEL_RESERVED_21', - 22: 'CB_PERF_SEL_RESERVED_22', - 23: 'CB_PERF_SEL_RESERVED_23', - 24: 'CB_PERF_SEL_RESERVED_24', - 25: 'CB_PERF_SEL_RESERVED_25', - 26: 'CB_PERF_SEL_RESERVED_26', - 27: 'CB_PERF_SEL_RESERVED_27', - 28: 'CB_PERF_SEL_RESERVED_28', - 29: 'CB_PERF_SEL_RESERVED_29', - 30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', - 31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', - 32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', - 33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', - 34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', - 35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', - 36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', - 37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', - 38: 'CB_PERF_SEL_RESERVED_38', - 39: 'CB_PERF_SEL_RESERVED_39', - 40: 'CB_PERF_SEL_RESERVED_40', - 41: 'CB_PERF_SEL_RESERVED_41', - 42: 'CB_PERF_SEL_RESERVED_42', - 43: 'CB_PERF_SEL_RESERVED_43', - 44: 'CB_PERF_SEL_RESERVED_44', - 45: 'CB_PERF_SEL_RESERVED_45', - 46: 'CB_PERF_SEL_RESERVED_46', - 47: 'CB_PERF_SEL_RESERVED_47', - 48: 'CB_PERF_SEL_RESERVED_48', - 49: 'CB_PERF_SEL_RESERVED_49', - 50: 'CB_PERF_SEL_STATIC_CLOCK_EN', - 51: 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 52: 'CB_PERF_SEL_BLEND_CLOCK_EN', - 53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 55: 'CB_PERF_SEL_GRBM_CLOCK_EN', - 56: 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 65: 'CB_PERF_SEL_RESERVED_65', - 66: 'CB_PERF_SEL_RESERVED_66', - 67: 'CB_PERF_SEL_RESERVED_67', - 68: 'CB_PERF_SEL_RESERVED_68', - 69: 'CB_PERF_SEL_RESERVED_69', - 70: 'CB_PERF_SEL_RESERVED_70', - 71: 'CB_PERF_SEL_RESERVED_71', - 72: 'CB_PERF_SEL_RESERVED_72', - 73: 'CB_PERF_SEL_RESERVED_73', - 74: 'CB_PERF_SEL_RESERVED_74', - 75: 'CB_PERF_SEL_RESERVED_75', - 76: 'CB_PERF_SEL_RESERVED_76', - 77: 'CB_PERF_SEL_RESERVED_77', - 78: 'CB_PERF_SEL_RESERVED_78', - 79: 'CB_PERF_SEL_RESERVED_79', - 80: 'CB_PERF_SEL_RESERVED_80', - 81: 'CB_PERF_SEL_RESERVED_81', - 82: 'CB_PERF_SEL_RESERVED_82', - 83: 'CB_PERF_SEL_RESERVED_83', - 84: 'CB_PERF_SEL_RESERVED_84', - 85: 'CB_PERF_SEL_RESERVED_85', - 86: 'CB_PERF_SEL_RESERVED_86', - 87: 'CB_PERF_SEL_RESERVED_87', - 88: 'CB_PERF_SEL_RESERVED_88', - 89: 'CB_PERF_SEL_RESERVED_89', - 90: 'CB_PERF_SEL_RESERVED_90', - 91: 'CB_PERF_SEL_RESERVED_91', - 92: 'CB_PERF_SEL_RESERVED_92', - 93: 'CB_PERF_SEL_RESERVED_93', - 94: 'CB_PERF_SEL_RESERVED_94', - 95: 'CB_PERF_SEL_RESERVED_95', - 96: 'CB_PERF_SEL_RESERVED_96', - 97: 'CB_PERF_SEL_RESERVED_97', - 98: 'CB_PERF_SEL_RESERVED_98', - 99: 'CB_PERF_SEL_RESERVED_99', - 100: 'CB_PERF_SEL_CC_TAG_HIT', - 101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', - 103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 111: 'CB_PERF_SEL_CC_CACHE_STALL', - 112: 'CB_PERF_SEL_CC_CACHE_FLUSH', - 113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 118: 'CB_PERF_SEL_RESERVED_118', - 119: 'CB_PERF_SEL_RESERVED_119', - 120: 'CB_PERF_SEL_RESERVED_120', - 121: 'CB_PERF_SEL_RESERVED_121', - 122: 'CB_PERF_SEL_RESERVED_122', - 123: 'CB_PERF_SEL_RESERVED_123', - 124: 'CB_PERF_SEL_RESERVED_124', - 125: 'CB_PERF_SEL_RESERVED_125', - 126: 'CB_PERF_SEL_RESERVED_126', - 127: 'CB_PERF_SEL_RESERVED_127', - 128: 'CB_PERF_SEL_RESERVED_128', - 129: 'CB_PERF_SEL_RESERVED_129', - 130: 'CB_PERF_SEL_RESERVED_130', - 131: 'CB_PERF_SEL_RESERVED_131', - 132: 'CB_PERF_SEL_RESERVED_132', - 133: 'CB_PERF_SEL_RESERVED_133', - 134: 'CB_PERF_SEL_RESERVED_134', - 135: 'CB_PERF_SEL_RESERVED_135', - 136: 'CB_PERF_SEL_RESERVED_136', - 137: 'CB_PERF_SEL_RESERVED_137', - 138: 'CB_PERF_SEL_RESERVED_138', - 139: 'CB_PERF_SEL_RESERVED_139', - 140: 'CB_PERF_SEL_RESERVED_140', - 141: 'CB_PERF_SEL_RESERVED_141', - 142: 'CB_PERF_SEL_RESERVED_142', - 143: 'CB_PERF_SEL_RESERVED_143', - 144: 'CB_PERF_SEL_RESERVED_144', - 145: 'CB_PERF_SEL_RESERVED_145', - 146: 'CB_PERF_SEL_RESERVED_146', - 147: 'CB_PERF_SEL_RESERVED_147', - 148: 'CB_PERF_SEL_RESERVED_148', - 149: 'CB_PERF_SEL_RESERVED_149', - 150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', - 151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', - 152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', - 153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', - 154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', - 158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', - 159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', - 160: 'CB_PERF_SEL_DCC_CACHE_STALL', - 161: 'CB_PERF_SEL_DCC_CACHE_FLUSH', - 162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', - 163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', - 165: 'CB_PERF_SEL_RESERVED_165', - 166: 'CB_PERF_SEL_RESERVED_166', - 167: 'CB_PERF_SEL_RESERVED_167', - 168: 'CB_PERF_SEL_RESERVED_168', - 169: 'CB_PERF_SEL_RESERVED_169', - 170: 'CB_PERF_SEL_RESERVED_170', - 171: 'CB_PERF_SEL_RESERVED_171', - 172: 'CB_PERF_SEL_RESERVED_172', - 173: 'CB_PERF_SEL_RESERVED_173', - 174: 'CB_PERF_SEL_RESERVED_174', - 175: 'CB_PERF_SEL_RESERVED_175', - 176: 'CB_PERF_SEL_RESERVED_176', - 177: 'CB_PERF_SEL_RESERVED_177', - 178: 'CB_PERF_SEL_RESERVED_178', - 179: 'CB_PERF_SEL_RESERVED_179', - 180: 'CB_PERF_SEL_RESERVED_180', - 181: 'CB_PERF_SEL_RESERVED_181', - 182: 'CB_PERF_SEL_RESERVED_182', - 183: 'CB_PERF_SEL_RESERVED_183', - 184: 'CB_PERF_SEL_RESERVED_184', - 185: 'CB_PERF_SEL_RESERVED_185', - 186: 'CB_PERF_SEL_RESERVED_186', - 187: 'CB_PERF_SEL_RESERVED_187', - 188: 'CB_PERF_SEL_RESERVED_188', - 189: 'CB_PERF_SEL_RESERVED_189', - 190: 'CB_PERF_SEL_RESERVED_190', - 191: 'CB_PERF_SEL_RESERVED_191', - 192: 'CB_PERF_SEL_RESERVED_192', - 193: 'CB_PERF_SEL_RESERVED_193', - 194: 'CB_PERF_SEL_RESERVED_194', - 195: 'CB_PERF_SEL_RESERVED_195', - 196: 'CB_PERF_SEL_RESERVED_196', - 197: 'CB_PERF_SEL_RESERVED_197', - 198: 'CB_PERF_SEL_RESERVED_198', - 199: 'CB_PERF_SEL_RESERVED_199', - 200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 205: 'CB_PERF_SEL_RESERVED_205', - 206: 'CB_PERF_SEL_RESERVED_206', - 207: 'CB_PERF_SEL_RESERVED_207', - 208: 'CB_PERF_SEL_RESERVED_208', - 209: 'CB_PERF_SEL_RESERVED_209', - 210: 'CB_PERF_SEL_RESERVED_210', - 211: 'CB_PERF_SEL_RESERVED_211', - 212: 'CB_PERF_SEL_RESERVED_212', - 213: 'CB_PERF_SEL_RESERVED_213', - 214: 'CB_PERF_SEL_RESERVED_214', - 215: 'CB_PERF_SEL_RESERVED_215', - 216: 'CB_PERF_SEL_RESERVED_216', - 217: 'CB_PERF_SEL_RESERVED_217', - 218: 'CB_PERF_SEL_RESERVED_218', - 219: 'CB_PERF_SEL_RESERVED_219', - 220: 'CB_PERF_SEL_RESERVED_220', - 221: 'CB_PERF_SEL_RESERVED_221', - 222: 'CB_PERF_SEL_RESERVED_222', - 223: 'CB_PERF_SEL_RESERVED_223', - 224: 'CB_PERF_SEL_RESERVED_224', - 225: 'CB_PERF_SEL_RESERVED_225', - 226: 'CB_PERF_SEL_RESERVED_226', - 227: 'CB_PERF_SEL_RESERVED_227', - 228: 'CB_PERF_SEL_RESERVED_228', - 229: 'CB_PERF_SEL_RESERVED_229', - 230: 'CB_PERF_SEL_RESERVED_230', - 231: 'CB_PERF_SEL_RESERVED_231', - 232: 'CB_PERF_SEL_RESERVED_232', - 233: 'CB_PERF_SEL_RESERVED_233', - 234: 'CB_PERF_SEL_RESERVED_234', - 235: 'CB_PERF_SEL_RESERVED_235', - 236: 'CB_PERF_SEL_RESERVED_236', - 237: 'CB_PERF_SEL_RESERVED_237', - 238: 'CB_PERF_SEL_RESERVED_238', - 239: 'CB_PERF_SEL_RESERVED_239', - 240: 'CB_PERF_SEL_RESERVED_240', - 241: 'CB_PERF_SEL_RESERVED_241', - 242: 'CB_PERF_SEL_RESERVED_242', - 243: 'CB_PERF_SEL_RESERVED_243', - 244: 'CB_PERF_SEL_RESERVED_244', - 245: 'CB_PERF_SEL_RESERVED_245', - 246: 'CB_PERF_SEL_RESERVED_246', - 247: 'CB_PERF_SEL_RESERVED_247', - 248: 'CB_PERF_SEL_RESERVED_248', - 249: 'CB_PERF_SEL_RESERVED_249', - 250: 'CB_PERF_SEL_EVENT', - 251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 258: 'CB_PERF_SEL_CC_SURFACE_SYNC', - 259: 'CB_PERF_SEL_RESERVED_259', - 260: 'CB_PERF_SEL_RESERVED_260', - 261: 'CB_PERF_SEL_RESERVED_261', - 262: 'CB_PERF_SEL_RESERVED_262', - 263: 'CB_PERF_SEL_RESERVED_263', - 264: 'CB_PERF_SEL_RESERVED_264', - 265: 'CB_PERF_SEL_RESERVED_265', - 266: 'CB_PERF_SEL_RESERVED_266', - 267: 'CB_PERF_SEL_RESERVED_267', - 268: 'CB_PERF_SEL_RESERVED_268', - 269: 'CB_PERF_SEL_RESERVED_269', - 270: 'CB_PERF_SEL_RESERVED_270', - 271: 'CB_PERF_SEL_RESERVED_271', - 272: 'CB_PERF_SEL_RESERVED_272', - 273: 'CB_PERF_SEL_RESERVED_273', - 274: 'CB_PERF_SEL_RESERVED_274', - 275: 'CB_PERF_SEL_RESERVED_275', - 276: 'CB_PERF_SEL_RESERVED_276', - 277: 'CB_PERF_SEL_RESERVED_277', - 278: 'CB_PERF_SEL_RESERVED_278', - 279: 'CB_PERF_SEL_RESERVED_279', - 280: 'CB_PERF_SEL_RESERVED_280', - 281: 'CB_PERF_SEL_RESERVED_281', - 282: 'CB_PERF_SEL_RESERVED_282', - 283: 'CB_PERF_SEL_RESERVED_283', - 284: 'CB_PERF_SEL_RESERVED_284', - 285: 'CB_PERF_SEL_RESERVED_285', - 286: 'CB_PERF_SEL_RESERVED_286', - 287: 'CB_PERF_SEL_RESERVED_287', - 288: 'CB_PERF_SEL_RESERVED_288', - 289: 'CB_PERF_SEL_RESERVED_289', - 290: 'CB_PERF_SEL_RESERVED_290', - 291: 'CB_PERF_SEL_RESERVED_291', - 292: 'CB_PERF_SEL_RESERVED_292', - 293: 'CB_PERF_SEL_RESERVED_293', - 294: 'CB_PERF_SEL_RESERVED_294', - 295: 'CB_PERF_SEL_RESERVED_295', - 296: 'CB_PERF_SEL_RESERVED_296', - 297: 'CB_PERF_SEL_RESERVED_297', - 298: 'CB_PERF_SEL_RESERVED_298', - 299: 'CB_PERF_SEL_RESERVED_299', - 300: 'CB_PERF_SEL_NACK_CC_READ', - 301: 'CB_PERF_SEL_NACK_CC_WRITE', - 302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 303: 'CB_PERF_SEL_RESERVED_303', - 304: 'CB_PERF_SEL_RESERVED_304', - 305: 'CB_PERF_SEL_RESERVED_305', - 306: 'CB_PERF_SEL_RESERVED_306', - 307: 'CB_PERF_SEL_RESERVED_307', - 308: 'CB_PERF_SEL_RESERVED_308', - 309: 'CB_PERF_SEL_RESERVED_309', - 310: 'CB_PERF_SEL_RESERVED_310', - 311: 'CB_PERF_SEL_RESERVED_311', - 312: 'CB_PERF_SEL_RESERVED_312', - 313: 'CB_PERF_SEL_RESERVED_313', - 314: 'CB_PERF_SEL_RESERVED_314', - 315: 'CB_PERF_SEL_RESERVED_315', - 316: 'CB_PERF_SEL_RESERVED_316', - 317: 'CB_PERF_SEL_RESERVED_317', - 318: 'CB_PERF_SEL_RESERVED_318', - 319: 'CB_PERF_SEL_RESERVED_319', - 320: 'CB_PERF_SEL_RESERVED_320', - 321: 'CB_PERF_SEL_RESERVED_321', - 322: 'CB_PERF_SEL_RESERVED_322', - 323: 'CB_PERF_SEL_RESERVED_323', - 324: 'CB_PERF_SEL_RESERVED_324', - 325: 'CB_PERF_SEL_RESERVED_325', - 326: 'CB_PERF_SEL_RESERVED_326', - 327: 'CB_PERF_SEL_RESERVED_327', - 328: 'CB_PERF_SEL_RESERVED_328', - 329: 'CB_PERF_SEL_RESERVED_329', - 330: 'CB_PERF_SEL_RESERVED_330', - 331: 'CB_PERF_SEL_RESERVED_331', - 332: 'CB_PERF_SEL_RESERVED_332', - 333: 'CB_PERF_SEL_RESERVED_333', - 334: 'CB_PERF_SEL_RESERVED_334', - 335: 'CB_PERF_SEL_RESERVED_335', - 336: 'CB_PERF_SEL_RESERVED_336', - 337: 'CB_PERF_SEL_RESERVED_337', - 338: 'CB_PERF_SEL_RESERVED_338', - 339: 'CB_PERF_SEL_RESERVED_339', - 340: 'CB_PERF_SEL_RESERVED_340', - 341: 'CB_PERF_SEL_RESERVED_341', - 342: 'CB_PERF_SEL_RESERVED_342', - 343: 'CB_PERF_SEL_RESERVED_343', - 344: 'CB_PERF_SEL_RESERVED_344', - 345: 'CB_PERF_SEL_RESERVED_345', - 346: 'CB_PERF_SEL_RESERVED_346', - 347: 'CB_PERF_SEL_RESERVED_347', - 348: 'CB_PERF_SEL_RESERVED_348', - 349: 'CB_PERF_SEL_RESERVED_349', - 350: 'CB_PERF_SEL_RESERVED_350', - 351: 'CB_PERF_SEL_RESERVED_351', - 352: 'CB_PERF_SEL_RESERVED_352', - 353: 'CB_PERF_SEL_RESERVED_353', - 354: 'CB_PERF_SEL_RESERVED_354', - 355: 'CB_PERF_SEL_RESERVED_355', - 356: 'CB_PERF_SEL_RESERVED_356', - 357: 'CB_PERF_SEL_RESERVED_357', - 358: 'CB_PERF_SEL_RESERVED_358', - 359: 'CB_PERF_SEL_RESERVED_359', - 360: 'CB_PERF_SEL_RESERVED_360', - 361: 'CB_PERF_SEL_RESERVED_361', - 362: 'CB_PERF_SEL_RESERVED_362', - 363: 'CB_PERF_SEL_RESERVED_363', - 364: 'CB_PERF_SEL_RESERVED_364', - 365: 'CB_PERF_SEL_RESERVED_365', - 366: 'CB_PERF_SEL_RESERVED_366', - 367: 'CB_PERF_SEL_RESERVED_367', - 368: 'CB_PERF_SEL_RESERVED_368', - 369: 'CB_PERF_SEL_RESERVED_369', - 370: 'CB_PERF_SEL_RESERVED_370', - 371: 'CB_PERF_SEL_RESERVED_371', - 372: 'CB_PERF_SEL_RESERVED_372', - 373: 'CB_PERF_SEL_RESERVED_373', - 374: 'CB_PERF_SEL_RESERVED_374', - 375: 'CB_PERF_SEL_RESERVED_375', - 376: 'CB_PERF_SEL_RESERVED_376', - 377: 'CB_PERF_SEL_RESERVED_377', - 378: 'CB_PERF_SEL_RESERVED_378', - 379: 'CB_PERF_SEL_RESERVED_379', - 380: 'CB_PERF_SEL_RESERVED_380', - 381: 'CB_PERF_SEL_RESERVED_381', - 382: 'CB_PERF_SEL_RESERVED_382', - 383: 'CB_PERF_SEL_RESERVED_383', - 384: 'CB_PERF_SEL_RESERVED_384', - 385: 'CB_PERF_SEL_RESERVED_385', - 386: 'CB_PERF_SEL_RESERVED_386', - 387: 'CB_PERF_SEL_RESERVED_387', - 388: 'CB_PERF_SEL_RESERVED_388', - 389: 'CB_PERF_SEL_RESERVED_389', - 390: 'CB_PERF_SEL_RESERVED_390', - 391: 'CB_PERF_SEL_RESERVED_391', - 392: 'CB_PERF_SEL_RESERVED_392', - 393: 'CB_PERF_SEL_RESERVED_393', - 394: 'CB_PERF_SEL_RESERVED_394', - 395: 'CB_PERF_SEL_RESERVED_395', - 396: 'CB_PERF_SEL_RESERVED_396', - 397: 'CB_PERF_SEL_RESERVED_397', - 398: 'CB_PERF_SEL_RESERVED_398', - 399: 'CB_PERF_SEL_RESERVED_399', - 400: 'CB_PERF_SEL_RESERVED_400', - 401: 'CB_PERF_SEL_RESERVED_401', - 402: 'CB_PERF_SEL_RESERVED_402', - 403: 'CB_PERF_SEL_RESERVED_403', - 404: 'CB_PERF_SEL_RESERVED_404', - 405: 'CB_PERF_SEL_RESERVED_405', - 406: 'CB_PERF_SEL_RESERVED_406', - 407: 'CB_PERF_SEL_RESERVED_407', - 408: 'CB_PERF_SEL_RESERVED_408', - 409: 'CB_PERF_SEL_RESERVED_409', - 410: 'CB_PERF_SEL_RESERVED_410', - 411: 'CB_PERF_SEL_RESERVED_411', - 412: 'CB_PERF_SEL_RESERVED_412', - 413: 'CB_PERF_SEL_RESERVED_413', - 414: 'CB_PERF_SEL_RESERVED_414', - 415: 'CB_PERF_SEL_RESERVED_415', - 416: 'CB_PERF_SEL_RESERVED_416', - 417: 'CB_PERF_SEL_RESERVED_417', - 418: 'CB_PERF_SEL_RESERVED_418', - 419: 'CB_PERF_SEL_RESERVED_419', - 420: 'CB_PERF_SEL_RESERVED_420', - 421: 'CB_PERF_SEL_RESERVED_421', - 422: 'CB_PERF_SEL_RESERVED_422', - 423: 'CB_PERF_SEL_RESERVED_423', - 424: 'CB_PERF_SEL_RESERVED_424', - 425: 'CB_PERF_SEL_RESERVED_425', - 426: 'CB_PERF_SEL_RESERVED_426', - 427: 'CB_PERF_SEL_RESERVED_427', - 428: 'CB_PERF_SEL_RESERVED_428', - 429: 'CB_PERF_SEL_RESERVED_429', - 430: 'CB_PERF_SEL_RESERVED_430', - 431: 'CB_PERF_SEL_RESERVED_431', - 432: 'CB_PERF_SEL_RESERVED_432', - 433: 'CB_PERF_SEL_RESERVED_433', - 434: 'CB_PERF_SEL_RESERVED_434', - 435: 'CB_PERF_SEL_RESERVED_435', - 436: 'CB_PERF_SEL_RESERVED_436', - 437: 'CB_PERF_SEL_RESERVED_437', - 438: 'CB_PERF_SEL_RESERVED_438', - 439: 'CB_PERF_SEL_RESERVED_439', - 440: 'CB_PERF_SEL_RESERVED_440', - 441: 'CB_PERF_SEL_RESERVED_441', - 442: 'CB_PERF_SEL_RESERVED_442', - 443: 'CB_PERF_SEL_RESERVED_443', - 444: 'CB_PERF_SEL_RESERVED_444', - 445: 'CB_PERF_SEL_RESERVED_445', - 446: 'CB_PERF_SEL_RESERVED_446', - 447: 'CB_PERF_SEL_RESERVED_447', - 448: 'CB_PERF_SEL_RESERVED_448', - 449: 'CB_PERF_SEL_RESERVED_449', - 450: 'CB_PERF_SEL_RESERVED_450', - 451: 'CB_PERF_SEL_RESERVED_451', - 452: 'CB_PERF_SEL_RESERVED_452', - 453: 'CB_PERF_SEL_RESERVED_453', - 454: 'CB_PERF_SEL_RESERVED_454', - 455: 'CB_PERF_SEL_RESERVED_455', - 456: 'CB_PERF_SEL_RESERVED_456', - 457: 'CB_PERF_SEL_RESERVED_457', - 458: 'CB_PERF_SEL_RESERVED_458', - 459: 'CB_PERF_SEL_RESERVED_459', - 460: 'CB_PERF_SEL_RESERVED_460', - 461: 'CB_PERF_SEL_RESERVED_461', - 462: 'CB_PERF_SEL_RESERVED_462', - 463: 'CB_PERF_SEL_RESERVED_463', - 464: 'CB_PERF_SEL_RESERVED_464', - 465: 'CB_PERF_SEL_RESERVED_465', -} -CB_PERF_SEL_NONE = 0 -CB_PERF_SEL_DRAWN_PIXEL = 1 -CB_PERF_SEL_DRAWN_QUAD = 2 -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3 -CB_PERF_SEL_DRAWN_TILE = 4 -CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5 -CB_PERF_SEL_FILTER_DRAWN_QUAD = 6 -CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7 -CB_PERF_SEL_FILTER_DRAWN_TILE = 8 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10 -CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11 -CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12 -CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13 -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14 -CB_PERF_SEL_CC_MC_READ_REQUEST = 15 -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20 -CB_PERF_SEL_RESERVED_21 = 21 -CB_PERF_SEL_RESERVED_22 = 22 -CB_PERF_SEL_RESERVED_23 = 23 -CB_PERF_SEL_RESERVED_24 = 24 -CB_PERF_SEL_RESERVED_25 = 25 -CB_PERF_SEL_RESERVED_26 = 26 -CB_PERF_SEL_RESERVED_27 = 27 -CB_PERF_SEL_RESERVED_28 = 28 -CB_PERF_SEL_RESERVED_29 = 29 -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30 -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31 -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32 -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33 -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34 -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35 -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36 -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37 -CB_PERF_SEL_RESERVED_38 = 38 -CB_PERF_SEL_RESERVED_39 = 39 -CB_PERF_SEL_RESERVED_40 = 40 -CB_PERF_SEL_RESERVED_41 = 41 -CB_PERF_SEL_RESERVED_42 = 42 -CB_PERF_SEL_RESERVED_43 = 43 -CB_PERF_SEL_RESERVED_44 = 44 -CB_PERF_SEL_RESERVED_45 = 45 -CB_PERF_SEL_RESERVED_46 = 46 -CB_PERF_SEL_RESERVED_47 = 47 -CB_PERF_SEL_RESERVED_48 = 48 -CB_PERF_SEL_RESERVED_49 = 49 -CB_PERF_SEL_STATIC_CLOCK_EN = 50 -CB_PERF_SEL_PERFMON_CLOCK_EN = 51 -CB_PERF_SEL_BLEND_CLOCK_EN = 52 -CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53 -CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54 -CB_PERF_SEL_GRBM_CLOCK_EN = 55 -CB_PERF_SEL_MEMARB_CLOCK_EN = 56 -CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57 -CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58 -CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59 -CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60 -CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61 -CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62 -CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63 -CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64 -CB_PERF_SEL_RESERVED_65 = 65 -CB_PERF_SEL_RESERVED_66 = 66 -CB_PERF_SEL_RESERVED_67 = 67 -CB_PERF_SEL_RESERVED_68 = 68 -CB_PERF_SEL_RESERVED_69 = 69 -CB_PERF_SEL_RESERVED_70 = 70 -CB_PERF_SEL_RESERVED_71 = 71 -CB_PERF_SEL_RESERVED_72 = 72 -CB_PERF_SEL_RESERVED_73 = 73 -CB_PERF_SEL_RESERVED_74 = 74 -CB_PERF_SEL_RESERVED_75 = 75 -CB_PERF_SEL_RESERVED_76 = 76 -CB_PERF_SEL_RESERVED_77 = 77 -CB_PERF_SEL_RESERVED_78 = 78 -CB_PERF_SEL_RESERVED_79 = 79 -CB_PERF_SEL_RESERVED_80 = 80 -CB_PERF_SEL_RESERVED_81 = 81 -CB_PERF_SEL_RESERVED_82 = 82 -CB_PERF_SEL_RESERVED_83 = 83 -CB_PERF_SEL_RESERVED_84 = 84 -CB_PERF_SEL_RESERVED_85 = 85 -CB_PERF_SEL_RESERVED_86 = 86 -CB_PERF_SEL_RESERVED_87 = 87 -CB_PERF_SEL_RESERVED_88 = 88 -CB_PERF_SEL_RESERVED_89 = 89 -CB_PERF_SEL_RESERVED_90 = 90 -CB_PERF_SEL_RESERVED_91 = 91 -CB_PERF_SEL_RESERVED_92 = 92 -CB_PERF_SEL_RESERVED_93 = 93 -CB_PERF_SEL_RESERVED_94 = 94 -CB_PERF_SEL_RESERVED_95 = 95 -CB_PERF_SEL_RESERVED_96 = 96 -CB_PERF_SEL_RESERVED_97 = 97 -CB_PERF_SEL_RESERVED_98 = 98 -CB_PERF_SEL_RESERVED_99 = 99 -CB_PERF_SEL_CC_TAG_HIT = 100 -CB_PERF_SEL_CC_CACHE_TAG_MISS = 101 -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102 -CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103 -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104 -CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105 -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106 -CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107 -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108 -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109 -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110 -CB_PERF_SEL_CC_CACHE_STALL = 111 -CB_PERF_SEL_CC_CACHE_FLUSH = 112 -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113 -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114 -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115 -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116 -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117 -CB_PERF_SEL_RESERVED_118 = 118 -CB_PERF_SEL_RESERVED_119 = 119 -CB_PERF_SEL_RESERVED_120 = 120 -CB_PERF_SEL_RESERVED_121 = 121 -CB_PERF_SEL_RESERVED_122 = 122 -CB_PERF_SEL_RESERVED_123 = 123 -CB_PERF_SEL_RESERVED_124 = 124 -CB_PERF_SEL_RESERVED_125 = 125 -CB_PERF_SEL_RESERVED_126 = 126 -CB_PERF_SEL_RESERVED_127 = 127 -CB_PERF_SEL_RESERVED_128 = 128 -CB_PERF_SEL_RESERVED_129 = 129 -CB_PERF_SEL_RESERVED_130 = 130 -CB_PERF_SEL_RESERVED_131 = 131 -CB_PERF_SEL_RESERVED_132 = 132 -CB_PERF_SEL_RESERVED_133 = 133 -CB_PERF_SEL_RESERVED_134 = 134 -CB_PERF_SEL_RESERVED_135 = 135 -CB_PERF_SEL_RESERVED_136 = 136 -CB_PERF_SEL_RESERVED_137 = 137 -CB_PERF_SEL_RESERVED_138 = 138 -CB_PERF_SEL_RESERVED_139 = 139 -CB_PERF_SEL_RESERVED_140 = 140 -CB_PERF_SEL_RESERVED_141 = 141 -CB_PERF_SEL_RESERVED_142 = 142 -CB_PERF_SEL_RESERVED_143 = 143 -CB_PERF_SEL_RESERVED_144 = 144 -CB_PERF_SEL_RESERVED_145 = 145 -CB_PERF_SEL_RESERVED_146 = 146 -CB_PERF_SEL_RESERVED_147 = 147 -CB_PERF_SEL_RESERVED_148 = 148 -CB_PERF_SEL_RESERVED_149 = 149 -CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150 -CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151 -CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152 -CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153 -CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154 -CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155 -CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156 -CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157 -CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158 -CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159 -CB_PERF_SEL_DCC_CACHE_STALL = 160 -CB_PERF_SEL_DCC_CACHE_FLUSH = 161 -CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162 -CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163 -CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164 -CB_PERF_SEL_RESERVED_165 = 165 -CB_PERF_SEL_RESERVED_166 = 166 -CB_PERF_SEL_RESERVED_167 = 167 -CB_PERF_SEL_RESERVED_168 = 168 -CB_PERF_SEL_RESERVED_169 = 169 -CB_PERF_SEL_RESERVED_170 = 170 -CB_PERF_SEL_RESERVED_171 = 171 -CB_PERF_SEL_RESERVED_172 = 172 -CB_PERF_SEL_RESERVED_173 = 173 -CB_PERF_SEL_RESERVED_174 = 174 -CB_PERF_SEL_RESERVED_175 = 175 -CB_PERF_SEL_RESERVED_176 = 176 -CB_PERF_SEL_RESERVED_177 = 177 -CB_PERF_SEL_RESERVED_178 = 178 -CB_PERF_SEL_RESERVED_179 = 179 -CB_PERF_SEL_RESERVED_180 = 180 -CB_PERF_SEL_RESERVED_181 = 181 -CB_PERF_SEL_RESERVED_182 = 182 -CB_PERF_SEL_RESERVED_183 = 183 -CB_PERF_SEL_RESERVED_184 = 184 -CB_PERF_SEL_RESERVED_185 = 185 -CB_PERF_SEL_RESERVED_186 = 186 -CB_PERF_SEL_RESERVED_187 = 187 -CB_PERF_SEL_RESERVED_188 = 188 -CB_PERF_SEL_RESERVED_189 = 189 -CB_PERF_SEL_RESERVED_190 = 190 -CB_PERF_SEL_RESERVED_191 = 191 -CB_PERF_SEL_RESERVED_192 = 192 -CB_PERF_SEL_RESERVED_193 = 193 -CB_PERF_SEL_RESERVED_194 = 194 -CB_PERF_SEL_RESERVED_195 = 195 -CB_PERF_SEL_RESERVED_196 = 196 -CB_PERF_SEL_RESERVED_197 = 197 -CB_PERF_SEL_RESERVED_198 = 198 -CB_PERF_SEL_RESERVED_199 = 199 -CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200 -CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201 -CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202 -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203 -CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204 -CB_PERF_SEL_RESERVED_205 = 205 -CB_PERF_SEL_RESERVED_206 = 206 -CB_PERF_SEL_RESERVED_207 = 207 -CB_PERF_SEL_RESERVED_208 = 208 -CB_PERF_SEL_RESERVED_209 = 209 -CB_PERF_SEL_RESERVED_210 = 210 -CB_PERF_SEL_RESERVED_211 = 211 -CB_PERF_SEL_RESERVED_212 = 212 -CB_PERF_SEL_RESERVED_213 = 213 -CB_PERF_SEL_RESERVED_214 = 214 -CB_PERF_SEL_RESERVED_215 = 215 -CB_PERF_SEL_RESERVED_216 = 216 -CB_PERF_SEL_RESERVED_217 = 217 -CB_PERF_SEL_RESERVED_218 = 218 -CB_PERF_SEL_RESERVED_219 = 219 -CB_PERF_SEL_RESERVED_220 = 220 -CB_PERF_SEL_RESERVED_221 = 221 -CB_PERF_SEL_RESERVED_222 = 222 -CB_PERF_SEL_RESERVED_223 = 223 -CB_PERF_SEL_RESERVED_224 = 224 -CB_PERF_SEL_RESERVED_225 = 225 -CB_PERF_SEL_RESERVED_226 = 226 -CB_PERF_SEL_RESERVED_227 = 227 -CB_PERF_SEL_RESERVED_228 = 228 -CB_PERF_SEL_RESERVED_229 = 229 -CB_PERF_SEL_RESERVED_230 = 230 -CB_PERF_SEL_RESERVED_231 = 231 -CB_PERF_SEL_RESERVED_232 = 232 -CB_PERF_SEL_RESERVED_233 = 233 -CB_PERF_SEL_RESERVED_234 = 234 -CB_PERF_SEL_RESERVED_235 = 235 -CB_PERF_SEL_RESERVED_236 = 236 -CB_PERF_SEL_RESERVED_237 = 237 -CB_PERF_SEL_RESERVED_238 = 238 -CB_PERF_SEL_RESERVED_239 = 239 -CB_PERF_SEL_RESERVED_240 = 240 -CB_PERF_SEL_RESERVED_241 = 241 -CB_PERF_SEL_RESERVED_242 = 242 -CB_PERF_SEL_RESERVED_243 = 243 -CB_PERF_SEL_RESERVED_244 = 244 -CB_PERF_SEL_RESERVED_245 = 245 -CB_PERF_SEL_RESERVED_246 = 246 -CB_PERF_SEL_RESERVED_247 = 247 -CB_PERF_SEL_RESERVED_248 = 248 -CB_PERF_SEL_RESERVED_249 = 249 -CB_PERF_SEL_EVENT = 250 -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251 -CB_PERF_SEL_EVENT_CONTEXT_DONE = 252 -CB_PERF_SEL_EVENT_CACHE_FLUSH = 253 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257 -CB_PERF_SEL_CC_SURFACE_SYNC = 258 -CB_PERF_SEL_RESERVED_259 = 259 -CB_PERF_SEL_RESERVED_260 = 260 -CB_PERF_SEL_RESERVED_261 = 261 -CB_PERF_SEL_RESERVED_262 = 262 -CB_PERF_SEL_RESERVED_263 = 263 -CB_PERF_SEL_RESERVED_264 = 264 -CB_PERF_SEL_RESERVED_265 = 265 -CB_PERF_SEL_RESERVED_266 = 266 -CB_PERF_SEL_RESERVED_267 = 267 -CB_PERF_SEL_RESERVED_268 = 268 -CB_PERF_SEL_RESERVED_269 = 269 -CB_PERF_SEL_RESERVED_270 = 270 -CB_PERF_SEL_RESERVED_271 = 271 -CB_PERF_SEL_RESERVED_272 = 272 -CB_PERF_SEL_RESERVED_273 = 273 -CB_PERF_SEL_RESERVED_274 = 274 -CB_PERF_SEL_RESERVED_275 = 275 -CB_PERF_SEL_RESERVED_276 = 276 -CB_PERF_SEL_RESERVED_277 = 277 -CB_PERF_SEL_RESERVED_278 = 278 -CB_PERF_SEL_RESERVED_279 = 279 -CB_PERF_SEL_RESERVED_280 = 280 -CB_PERF_SEL_RESERVED_281 = 281 -CB_PERF_SEL_RESERVED_282 = 282 -CB_PERF_SEL_RESERVED_283 = 283 -CB_PERF_SEL_RESERVED_284 = 284 -CB_PERF_SEL_RESERVED_285 = 285 -CB_PERF_SEL_RESERVED_286 = 286 -CB_PERF_SEL_RESERVED_287 = 287 -CB_PERF_SEL_RESERVED_288 = 288 -CB_PERF_SEL_RESERVED_289 = 289 -CB_PERF_SEL_RESERVED_290 = 290 -CB_PERF_SEL_RESERVED_291 = 291 -CB_PERF_SEL_RESERVED_292 = 292 -CB_PERF_SEL_RESERVED_293 = 293 -CB_PERF_SEL_RESERVED_294 = 294 -CB_PERF_SEL_RESERVED_295 = 295 -CB_PERF_SEL_RESERVED_296 = 296 -CB_PERF_SEL_RESERVED_297 = 297 -CB_PERF_SEL_RESERVED_298 = 298 -CB_PERF_SEL_RESERVED_299 = 299 -CB_PERF_SEL_NACK_CC_READ = 300 -CB_PERF_SEL_NACK_CC_WRITE = 301 -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302 -CB_PERF_SEL_RESERVED_303 = 303 -CB_PERF_SEL_RESERVED_304 = 304 -CB_PERF_SEL_RESERVED_305 = 305 -CB_PERF_SEL_RESERVED_306 = 306 -CB_PERF_SEL_RESERVED_307 = 307 -CB_PERF_SEL_RESERVED_308 = 308 -CB_PERF_SEL_RESERVED_309 = 309 -CB_PERF_SEL_RESERVED_310 = 310 -CB_PERF_SEL_RESERVED_311 = 311 -CB_PERF_SEL_RESERVED_312 = 312 -CB_PERF_SEL_RESERVED_313 = 313 -CB_PERF_SEL_RESERVED_314 = 314 -CB_PERF_SEL_RESERVED_315 = 315 -CB_PERF_SEL_RESERVED_316 = 316 -CB_PERF_SEL_RESERVED_317 = 317 -CB_PERF_SEL_RESERVED_318 = 318 -CB_PERF_SEL_RESERVED_319 = 319 -CB_PERF_SEL_RESERVED_320 = 320 -CB_PERF_SEL_RESERVED_321 = 321 -CB_PERF_SEL_RESERVED_322 = 322 -CB_PERF_SEL_RESERVED_323 = 323 -CB_PERF_SEL_RESERVED_324 = 324 -CB_PERF_SEL_RESERVED_325 = 325 -CB_PERF_SEL_RESERVED_326 = 326 -CB_PERF_SEL_RESERVED_327 = 327 -CB_PERF_SEL_RESERVED_328 = 328 -CB_PERF_SEL_RESERVED_329 = 329 -CB_PERF_SEL_RESERVED_330 = 330 -CB_PERF_SEL_RESERVED_331 = 331 -CB_PERF_SEL_RESERVED_332 = 332 -CB_PERF_SEL_RESERVED_333 = 333 -CB_PERF_SEL_RESERVED_334 = 334 -CB_PERF_SEL_RESERVED_335 = 335 -CB_PERF_SEL_RESERVED_336 = 336 -CB_PERF_SEL_RESERVED_337 = 337 -CB_PERF_SEL_RESERVED_338 = 338 -CB_PERF_SEL_RESERVED_339 = 339 -CB_PERF_SEL_RESERVED_340 = 340 -CB_PERF_SEL_RESERVED_341 = 341 -CB_PERF_SEL_RESERVED_342 = 342 -CB_PERF_SEL_RESERVED_343 = 343 -CB_PERF_SEL_RESERVED_344 = 344 -CB_PERF_SEL_RESERVED_345 = 345 -CB_PERF_SEL_RESERVED_346 = 346 -CB_PERF_SEL_RESERVED_347 = 347 -CB_PERF_SEL_RESERVED_348 = 348 -CB_PERF_SEL_RESERVED_349 = 349 -CB_PERF_SEL_RESERVED_350 = 350 -CB_PERF_SEL_RESERVED_351 = 351 -CB_PERF_SEL_RESERVED_352 = 352 -CB_PERF_SEL_RESERVED_353 = 353 -CB_PERF_SEL_RESERVED_354 = 354 -CB_PERF_SEL_RESERVED_355 = 355 -CB_PERF_SEL_RESERVED_356 = 356 -CB_PERF_SEL_RESERVED_357 = 357 -CB_PERF_SEL_RESERVED_358 = 358 -CB_PERF_SEL_RESERVED_359 = 359 -CB_PERF_SEL_RESERVED_360 = 360 -CB_PERF_SEL_RESERVED_361 = 361 -CB_PERF_SEL_RESERVED_362 = 362 -CB_PERF_SEL_RESERVED_363 = 363 -CB_PERF_SEL_RESERVED_364 = 364 -CB_PERF_SEL_RESERVED_365 = 365 -CB_PERF_SEL_RESERVED_366 = 366 -CB_PERF_SEL_RESERVED_367 = 367 -CB_PERF_SEL_RESERVED_368 = 368 -CB_PERF_SEL_RESERVED_369 = 369 -CB_PERF_SEL_RESERVED_370 = 370 -CB_PERF_SEL_RESERVED_371 = 371 -CB_PERF_SEL_RESERVED_372 = 372 -CB_PERF_SEL_RESERVED_373 = 373 -CB_PERF_SEL_RESERVED_374 = 374 -CB_PERF_SEL_RESERVED_375 = 375 -CB_PERF_SEL_RESERVED_376 = 376 -CB_PERF_SEL_RESERVED_377 = 377 -CB_PERF_SEL_RESERVED_378 = 378 -CB_PERF_SEL_RESERVED_379 = 379 -CB_PERF_SEL_RESERVED_380 = 380 -CB_PERF_SEL_RESERVED_381 = 381 -CB_PERF_SEL_RESERVED_382 = 382 -CB_PERF_SEL_RESERVED_383 = 383 -CB_PERF_SEL_RESERVED_384 = 384 -CB_PERF_SEL_RESERVED_385 = 385 -CB_PERF_SEL_RESERVED_386 = 386 -CB_PERF_SEL_RESERVED_387 = 387 -CB_PERF_SEL_RESERVED_388 = 388 -CB_PERF_SEL_RESERVED_389 = 389 -CB_PERF_SEL_RESERVED_390 = 390 -CB_PERF_SEL_RESERVED_391 = 391 -CB_PERF_SEL_RESERVED_392 = 392 -CB_PERF_SEL_RESERVED_393 = 393 -CB_PERF_SEL_RESERVED_394 = 394 -CB_PERF_SEL_RESERVED_395 = 395 -CB_PERF_SEL_RESERVED_396 = 396 -CB_PERF_SEL_RESERVED_397 = 397 -CB_PERF_SEL_RESERVED_398 = 398 -CB_PERF_SEL_RESERVED_399 = 399 -CB_PERF_SEL_RESERVED_400 = 400 -CB_PERF_SEL_RESERVED_401 = 401 -CB_PERF_SEL_RESERVED_402 = 402 -CB_PERF_SEL_RESERVED_403 = 403 -CB_PERF_SEL_RESERVED_404 = 404 -CB_PERF_SEL_RESERVED_405 = 405 -CB_PERF_SEL_RESERVED_406 = 406 -CB_PERF_SEL_RESERVED_407 = 407 -CB_PERF_SEL_RESERVED_408 = 408 -CB_PERF_SEL_RESERVED_409 = 409 -CB_PERF_SEL_RESERVED_410 = 410 -CB_PERF_SEL_RESERVED_411 = 411 -CB_PERF_SEL_RESERVED_412 = 412 -CB_PERF_SEL_RESERVED_413 = 413 -CB_PERF_SEL_RESERVED_414 = 414 -CB_PERF_SEL_RESERVED_415 = 415 -CB_PERF_SEL_RESERVED_416 = 416 -CB_PERF_SEL_RESERVED_417 = 417 -CB_PERF_SEL_RESERVED_418 = 418 -CB_PERF_SEL_RESERVED_419 = 419 -CB_PERF_SEL_RESERVED_420 = 420 -CB_PERF_SEL_RESERVED_421 = 421 -CB_PERF_SEL_RESERVED_422 = 422 -CB_PERF_SEL_RESERVED_423 = 423 -CB_PERF_SEL_RESERVED_424 = 424 -CB_PERF_SEL_RESERVED_425 = 425 -CB_PERF_SEL_RESERVED_426 = 426 -CB_PERF_SEL_RESERVED_427 = 427 -CB_PERF_SEL_RESERVED_428 = 428 -CB_PERF_SEL_RESERVED_429 = 429 -CB_PERF_SEL_RESERVED_430 = 430 -CB_PERF_SEL_RESERVED_431 = 431 -CB_PERF_SEL_RESERVED_432 = 432 -CB_PERF_SEL_RESERVED_433 = 433 -CB_PERF_SEL_RESERVED_434 = 434 -CB_PERF_SEL_RESERVED_435 = 435 -CB_PERF_SEL_RESERVED_436 = 436 -CB_PERF_SEL_RESERVED_437 = 437 -CB_PERF_SEL_RESERVED_438 = 438 -CB_PERF_SEL_RESERVED_439 = 439 -CB_PERF_SEL_RESERVED_440 = 440 -CB_PERF_SEL_RESERVED_441 = 441 -CB_PERF_SEL_RESERVED_442 = 442 -CB_PERF_SEL_RESERVED_443 = 443 -CB_PERF_SEL_RESERVED_444 = 444 -CB_PERF_SEL_RESERVED_445 = 445 -CB_PERF_SEL_RESERVED_446 = 446 -CB_PERF_SEL_RESERVED_447 = 447 -CB_PERF_SEL_RESERVED_448 = 448 -CB_PERF_SEL_RESERVED_449 = 449 -CB_PERF_SEL_RESERVED_450 = 450 -CB_PERF_SEL_RESERVED_451 = 451 -CB_PERF_SEL_RESERVED_452 = 452 -CB_PERF_SEL_RESERVED_453 = 453 -CB_PERF_SEL_RESERVED_454 = 454 -CB_PERF_SEL_RESERVED_455 = 455 -CB_PERF_SEL_RESERVED_456 = 456 -CB_PERF_SEL_RESERVED_457 = 457 -CB_PERF_SEL_RESERVED_458 = 458 -CB_PERF_SEL_RESERVED_459 = 459 -CB_PERF_SEL_RESERVED_460 = 460 -CB_PERF_SEL_RESERVED_461 = 461 -CB_PERF_SEL_RESERVED_462 = 462 -CB_PERF_SEL_RESERVED_463 = 463 -CB_PERF_SEL_RESERVED_464 = 464 -CB_PERF_SEL_RESERVED_465 = 465 -CBPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBRamList' -CBRamList__enumvalues = { - 0: 'CB_DCG_CCC_CAS_TAG_ARRAY', - 1: 'CB_DCG_CCC_CAS_FRAG_PTR', - 2: 'CB_DCG_CCC_CAS_COLOR_PTR', - 3: 'CB_DCG_CCC_CAS_SURF_PARAM', - 4: 'CB_DCG_CCC_CAS_KEYID', - 5: 'CB_DCG_BACKEND_RDLAT_FIFO', - 6: 'CB_DCG_FRONTEND_RDLAT_FIFO', - 7: 'CB_DCG_SRC_FIFO', - 8: 'CB_DCG_COLOR_STORE', - 9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE', - 10: 'CB_DCG_FMASK_CACHE_STORE', - 11: 'CB_DCG_READ_SKID_FIFO', - 12: 'CB_DCG_QUAD_PTR_FIFO', - 13: 'CB_DCG_OUTPUT_FIFO', - 14: 'CB_DCG_DCC_CACHE', - 15: 'CB_DCG_DCC_DIRTY_BITS', - 16: 'CB_DCG_QBLOCK_ALLOC', -} -CB_DCG_CCC_CAS_TAG_ARRAY = 0 -CB_DCG_CCC_CAS_FRAG_PTR = 1 -CB_DCG_CCC_CAS_COLOR_PTR = 2 -CB_DCG_CCC_CAS_SURF_PARAM = 3 -CB_DCG_CCC_CAS_KEYID = 4 -CB_DCG_BACKEND_RDLAT_FIFO = 5 -CB_DCG_FRONTEND_RDLAT_FIFO = 6 -CB_DCG_SRC_FIFO = 7 -CB_DCG_COLOR_STORE = 8 -CB_DCG_COLOR_STORE_DIRTY_BYTE = 9 -CB_DCG_FMASK_CACHE_STORE = 10 -CB_DCG_READ_SKID_FIFO = 11 -CB_DCG_QUAD_PTR_FIFO = 12 -CB_DCG_OUTPUT_FIFO = 13 -CB_DCG_DCC_CACHE = 14 -CB_DCG_DCC_DIRTY_BITS = 15 -CB_DCG_QBLOCK_ALLOC = 16 -CBRamList = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskCode' -CmaskCode__enumvalues = { - 0: 'CMASK_CLR00_F0', - 1: 'CMASK_CLR00_F1', - 2: 'CMASK_CLR00_F2', - 3: 'CMASK_CLR00_FX', - 4: 'CMASK_CLR01_F0', - 5: 'CMASK_CLR01_F1', - 6: 'CMASK_CLR01_F2', - 7: 'CMASK_CLR01_FX', - 8: 'CMASK_CLR10_F0', - 9: 'CMASK_CLR10_F1', - 10: 'CMASK_CLR10_F2', - 11: 'CMASK_CLR10_FX', - 12: 'CMASK_CLR11_F0', - 13: 'CMASK_CLR11_F1', - 14: 'CMASK_CLR11_F2', - 15: 'CMASK_CLR11_FX', -} -CMASK_CLR00_F0 = 0 -CMASK_CLR00_F1 = 1 -CMASK_CLR00_F2 = 2 -CMASK_CLR00_FX = 3 -CMASK_CLR01_F0 = 4 -CMASK_CLR01_F1 = 5 -CMASK_CLR01_F2 = 6 -CMASK_CLR01_FX = 7 -CMASK_CLR10_F0 = 8 -CMASK_CLR10_F1 = 9 -CMASK_CLR10_F2 = 10 -CMASK_CLR10_FX = 11 -CMASK_CLR11_F0 = 12 -CMASK_CLR11_F1 = 13 -CMASK_CLR11_F2 = 14 -CMASK_CLR11_FX = 15 -CmaskCode = ctypes.c_uint32 # enum - -# values for enumeration 'CombFunc' -CombFunc__enumvalues = { - 0: 'COMB_DST_PLUS_SRC', - 1: 'COMB_SRC_MINUS_DST', - 2: 'COMB_MIN_DST_SRC', - 3: 'COMB_MAX_DST_SRC', - 4: 'COMB_DST_MINUS_SRC', -} -COMB_DST_PLUS_SRC = 0 -COMB_SRC_MINUS_DST = 1 -COMB_MIN_DST_SRC = 2 -COMB_MAX_DST_SRC = 3 -COMB_DST_MINUS_SRC = 4 -CombFunc = ctypes.c_uint32 # enum - -# values for enumeration 'MemArbMode' -MemArbMode__enumvalues = { - 0: 'MEM_ARB_MODE_FIXED', - 1: 'MEM_ARB_MODE_AGE', - 2: 'MEM_ARB_MODE_WEIGHT', - 3: 'MEM_ARB_MODE_BOTH', -} -MEM_ARB_MODE_FIXED = 0 -MEM_ARB_MODE_AGE = 1 -MEM_ARB_MODE_WEIGHT = 2 -MEM_ARB_MODE_BOTH = 3 -MemArbMode = ctypes.c_uint32 # enum - -# values for enumeration 'SourceFormat' -SourceFormat__enumvalues = { - 0: 'EXPORT_4C_32BPC', - 1: 'EXPORT_4C_16BPC', - 2: 'EXPORT_2C_32BPC_GR', - 3: 'EXPORT_2C_32BPC_AR', -} -EXPORT_4C_32BPC = 0 -EXPORT_4C_16BPC = 1 -EXPORT_2C_32BPC_GR = 2 -EXPORT_2C_32BPC_AR = 3 -SourceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'BinEventCntl' -BinEventCntl__enumvalues = { - 0: 'BINNER_BREAK_BATCH', - 1: 'BINNER_PIPELINE', - 2: 'BINNER_DROP', - 3: 'BINNER_PIPELINE_BREAK', -} -BINNER_BREAK_BATCH = 0 -BINNER_PIPELINE = 1 -BINNER_DROP = 2 -BINNER_PIPELINE_BREAK = 3 -BinEventCntl = ctypes.c_uint32 # enum - -# values for enumeration 'BinMapMode' -BinMapMode__enumvalues = { - 0: 'BIN_MAP_MODE_NONE', - 1: 'BIN_MAP_MODE_RTA_INDEX', - 2: 'BIN_MAP_MODE_POPS', -} -BIN_MAP_MODE_NONE = 0 -BIN_MAP_MODE_RTA_INDEX = 1 -BIN_MAP_MODE_POPS = 2 -BinMapMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinSizeExtend' -BinSizeExtend__enumvalues = { - 0: 'BIN_SIZE_32_PIXELS', - 1: 'BIN_SIZE_64_PIXELS', - 2: 'BIN_SIZE_128_PIXELS', - 3: 'BIN_SIZE_256_PIXELS', - 4: 'BIN_SIZE_512_PIXELS', -} -BIN_SIZE_32_PIXELS = 0 -BIN_SIZE_64_PIXELS = 1 -BIN_SIZE_128_PIXELS = 2 -BIN_SIZE_256_PIXELS = 3 -BIN_SIZE_512_PIXELS = 4 -BinSizeExtend = ctypes.c_uint32 # enum - -# values for enumeration 'BinningMode' -BinningMode__enumvalues = { - 0: 'BINNING_ALLOWED', - 1: 'FORCE_BINNING_ON', - 2: 'DISABLE_BINNING_USE_NEW_SC', - 3: 'DISABLE_BINNING_USE_LEGACY_SC', -} -BINNING_ALLOWED = 0 -FORCE_BINNING_ON = 1 -DISABLE_BINNING_USE_NEW_SC = 2 -DISABLE_BINNING_USE_LEGACY_SC = 3 -BinningMode = ctypes.c_uint32 # enum - -# values for enumeration 'CovToShaderSel' -CovToShaderSel__enumvalues = { - 0: 'INPUT_COVERAGE', - 1: 'INPUT_INNER_COVERAGE', - 2: 'INPUT_DEPTH_COVERAGE', - 3: 'RAW', -} -INPUT_COVERAGE = 0 -INPUT_INNER_COVERAGE = 1 -INPUT_DEPTH_COVERAGE = 2 -RAW = 3 -CovToShaderSel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrMap' -PkrMap__enumvalues = { - 0: 'RASTER_CONFIG_PKR_MAP_0', - 1: 'RASTER_CONFIG_PKR_MAP_1', - 2: 'RASTER_CONFIG_PKR_MAP_2', - 3: 'RASTER_CONFIG_PKR_MAP_3', -} -RASTER_CONFIG_PKR_MAP_0 = 0 -RASTER_CONFIG_PKR_MAP_1 = 1 -RASTER_CONFIG_PKR_MAP_2 = 2 -RASTER_CONFIG_PKR_MAP_3 = 3 -PkrMap = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel' -PkrXsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL_0', - 1: 'RASTER_CONFIG_PKR_XSEL_1', - 2: 'RASTER_CONFIG_PKR_XSEL_2', - 3: 'RASTER_CONFIG_PKR_XSEL_3', -} -RASTER_CONFIG_PKR_XSEL_0 = 0 -RASTER_CONFIG_PKR_XSEL_1 = 1 -RASTER_CONFIG_PKR_XSEL_2 = 2 -RASTER_CONFIG_PKR_XSEL_3 = 3 -PkrXsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel2' -PkrXsel2__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL2_0', - 1: 'RASTER_CONFIG_PKR_XSEL2_1', - 2: 'RASTER_CONFIG_PKR_XSEL2_2', - 3: 'RASTER_CONFIG_PKR_XSEL2_3', -} -RASTER_CONFIG_PKR_XSEL2_0 = 0 -RASTER_CONFIG_PKR_XSEL2_1 = 1 -RASTER_CONFIG_PKR_XSEL2_2 = 2 -RASTER_CONFIG_PKR_XSEL2_3 = 3 -PkrXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'PkrYsel' -PkrYsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_YSEL_0', - 1: 'RASTER_CONFIG_PKR_YSEL_1', - 2: 'RASTER_CONFIG_PKR_YSEL_2', - 3: 'RASTER_CONFIG_PKR_YSEL_3', -} -RASTER_CONFIG_PKR_YSEL_0 = 0 -RASTER_CONFIG_PKR_YSEL_1 = 1 -RASTER_CONFIG_PKR_YSEL_2 = 2 -RASTER_CONFIG_PKR_YSEL_3 = 3 -PkrYsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbMap' -RbMap__enumvalues = { - 0: 'RASTER_CONFIG_RB_MAP_0', - 1: 'RASTER_CONFIG_RB_MAP_1', - 2: 'RASTER_CONFIG_RB_MAP_2', - 3: 'RASTER_CONFIG_RB_MAP_3', -} -RASTER_CONFIG_RB_MAP_0 = 0 -RASTER_CONFIG_RB_MAP_1 = 1 -RASTER_CONFIG_RB_MAP_2 = 2 -RASTER_CONFIG_RB_MAP_3 = 3 -RbMap = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel' -RbXsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL_0', - 1: 'RASTER_CONFIG_RB_XSEL_1', -} -RASTER_CONFIG_RB_XSEL_0 = 0 -RASTER_CONFIG_RB_XSEL_1 = 1 -RbXsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel2' -RbXsel2__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL2_0', - 1: 'RASTER_CONFIG_RB_XSEL2_1', - 2: 'RASTER_CONFIG_RB_XSEL2_2', - 3: 'RASTER_CONFIG_RB_XSEL2_3', -} -RASTER_CONFIG_RB_XSEL2_0 = 0 -RASTER_CONFIG_RB_XSEL2_1 = 1 -RASTER_CONFIG_RB_XSEL2_2 = 2 -RASTER_CONFIG_RB_XSEL2_3 = 3 -RbXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'RbYsel' -RbYsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_YSEL_0', - 1: 'RASTER_CONFIG_RB_YSEL_1', -} -RASTER_CONFIG_RB_YSEL_0 = 0 -RASTER_CONFIG_RB_YSEL_1 = 1 -RbYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SC_PERFCNT_SEL' -SC_PERFCNT_SEL__enumvalues = { - 0: 'SC_SRPS_WINDOW_VALID', - 1: 'SC_PSSW_WINDOW_VALID', - 2: 'SC_TPQZ_WINDOW_VALID', - 3: 'SC_QZQP_WINDOW_VALID', - 4: 'SC_TRPK_WINDOW_VALID', - 5: 'SC_SRPS_WINDOW_VALID_BUSY', - 6: 'SC_PSSW_WINDOW_VALID_BUSY', - 7: 'SC_TPQZ_WINDOW_VALID_BUSY', - 8: 'SC_QZQP_WINDOW_VALID_BUSY', - 9: 'SC_TRPK_WINDOW_VALID_BUSY', - 10: 'SC_STARVED_BY_PA', - 11: 'SC_STALLED_BY_PRIMFIFO', - 12: 'SC_STALLED_BY_DB_TILE', - 13: 'SC_STARVED_BY_DB_TILE', - 14: 'SC_STALLED_BY_TILEORDERFIFO', - 15: 'SC_STALLED_BY_TILEFIFO', - 16: 'SC_STALLED_BY_DB_QUAD', - 17: 'SC_STARVED_BY_DB_QUAD', - 18: 'SC_STALLED_BY_QUADFIFO', - 19: 'SC_STALLED_BY_BCI', - 20: 'SC_STALLED_BY_SPI', - 21: 'SC_SCISSOR_DISCARD', - 22: 'SC_BB_DISCARD', - 23: 'SC_SUPERTILE_COUNT', - 24: 'SC_SUPERTILE_PER_PRIM_H0', - 25: 'SC_SUPERTILE_PER_PRIM_H1', - 26: 'SC_SUPERTILE_PER_PRIM_H2', - 27: 'SC_SUPERTILE_PER_PRIM_H3', - 28: 'SC_SUPERTILE_PER_PRIM_H4', - 29: 'SC_SUPERTILE_PER_PRIM_H5', - 30: 'SC_SUPERTILE_PER_PRIM_H6', - 31: 'SC_SUPERTILE_PER_PRIM_H7', - 32: 'SC_SUPERTILE_PER_PRIM_H8', - 33: 'SC_SUPERTILE_PER_PRIM_H9', - 34: 'SC_SUPERTILE_PER_PRIM_H10', - 35: 'SC_SUPERTILE_PER_PRIM_H11', - 36: 'SC_SUPERTILE_PER_PRIM_H12', - 37: 'SC_SUPERTILE_PER_PRIM_H13', - 38: 'SC_SUPERTILE_PER_PRIM_H14', - 39: 'SC_SUPERTILE_PER_PRIM_H15', - 40: 'SC_SUPERTILE_PER_PRIM_H16', - 41: 'SC_TILE_PER_PRIM_H0', - 42: 'SC_TILE_PER_PRIM_H1', - 43: 'SC_TILE_PER_PRIM_H2', - 44: 'SC_TILE_PER_PRIM_H3', - 45: 'SC_TILE_PER_PRIM_H4', - 46: 'SC_TILE_PER_PRIM_H5', - 47: 'SC_TILE_PER_PRIM_H6', - 48: 'SC_TILE_PER_PRIM_H7', - 49: 'SC_TILE_PER_PRIM_H8', - 50: 'SC_TILE_PER_PRIM_H9', - 51: 'SC_TILE_PER_PRIM_H10', - 52: 'SC_TILE_PER_PRIM_H11', - 53: 'SC_TILE_PER_PRIM_H12', - 54: 'SC_TILE_PER_PRIM_H13', - 55: 'SC_TILE_PER_PRIM_H14', - 56: 'SC_TILE_PER_PRIM_H15', - 57: 'SC_TILE_PER_PRIM_H16', - 58: 'SC_TILE_PER_SUPERTILE_H0', - 59: 'SC_TILE_PER_SUPERTILE_H1', - 60: 'SC_TILE_PER_SUPERTILE_H2', - 61: 'SC_TILE_PER_SUPERTILE_H3', - 62: 'SC_TILE_PER_SUPERTILE_H4', - 63: 'SC_TILE_PER_SUPERTILE_H5', - 64: 'SC_TILE_PER_SUPERTILE_H6', - 65: 'SC_TILE_PER_SUPERTILE_H7', - 66: 'SC_TILE_PER_SUPERTILE_H8', - 67: 'SC_TILE_PER_SUPERTILE_H9', - 68: 'SC_TILE_PER_SUPERTILE_H10', - 69: 'SC_TILE_PER_SUPERTILE_H11', - 70: 'SC_TILE_PER_SUPERTILE_H12', - 71: 'SC_TILE_PER_SUPERTILE_H13', - 72: 'SC_TILE_PER_SUPERTILE_H14', - 73: 'SC_TILE_PER_SUPERTILE_H15', - 74: 'SC_TILE_PER_SUPERTILE_H16', - 75: 'SC_TILE_PICKED_H1', - 76: 'SC_TILE_PICKED_H2', - 77: 'SC_TILE_PICKED_H3', - 78: 'SC_TILE_PICKED_H4', - 79: 'SC_QZ0_TILE_COUNT', - 80: 'SC_QZ1_TILE_COUNT', - 81: 'SC_QZ2_TILE_COUNT', - 82: 'SC_QZ3_TILE_COUNT', - 83: 'SC_QZ0_TILE_COVERED_COUNT', - 84: 'SC_QZ1_TILE_COVERED_COUNT', - 85: 'SC_QZ2_TILE_COVERED_COUNT', - 86: 'SC_QZ3_TILE_COVERED_COUNT', - 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', - 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 91: 'SC_QZ0_QUAD_PER_TILE_H0', - 92: 'SC_QZ0_QUAD_PER_TILE_H1', - 93: 'SC_QZ0_QUAD_PER_TILE_H2', - 94: 'SC_QZ0_QUAD_PER_TILE_H3', - 95: 'SC_QZ0_QUAD_PER_TILE_H4', - 96: 'SC_QZ0_QUAD_PER_TILE_H5', - 97: 'SC_QZ0_QUAD_PER_TILE_H6', - 98: 'SC_QZ0_QUAD_PER_TILE_H7', - 99: 'SC_QZ0_QUAD_PER_TILE_H8', - 100: 'SC_QZ0_QUAD_PER_TILE_H9', - 101: 'SC_QZ0_QUAD_PER_TILE_H10', - 102: 'SC_QZ0_QUAD_PER_TILE_H11', - 103: 'SC_QZ0_QUAD_PER_TILE_H12', - 104: 'SC_QZ0_QUAD_PER_TILE_H13', - 105: 'SC_QZ0_QUAD_PER_TILE_H14', - 106: 'SC_QZ0_QUAD_PER_TILE_H15', - 107: 'SC_QZ0_QUAD_PER_TILE_H16', - 108: 'SC_QZ1_QUAD_PER_TILE_H0', - 109: 'SC_QZ1_QUAD_PER_TILE_H1', - 110: 'SC_QZ1_QUAD_PER_TILE_H2', - 111: 'SC_QZ1_QUAD_PER_TILE_H3', - 112: 'SC_QZ1_QUAD_PER_TILE_H4', - 113: 'SC_QZ1_QUAD_PER_TILE_H5', - 114: 'SC_QZ1_QUAD_PER_TILE_H6', - 115: 'SC_QZ1_QUAD_PER_TILE_H7', - 116: 'SC_QZ1_QUAD_PER_TILE_H8', - 117: 'SC_QZ1_QUAD_PER_TILE_H9', - 118: 'SC_QZ1_QUAD_PER_TILE_H10', - 119: 'SC_QZ1_QUAD_PER_TILE_H11', - 120: 'SC_QZ1_QUAD_PER_TILE_H12', - 121: 'SC_QZ1_QUAD_PER_TILE_H13', - 122: 'SC_QZ1_QUAD_PER_TILE_H14', - 123: 'SC_QZ1_QUAD_PER_TILE_H15', - 124: 'SC_QZ1_QUAD_PER_TILE_H16', - 125: 'SC_QZ2_QUAD_PER_TILE_H0', - 126: 'SC_QZ2_QUAD_PER_TILE_H1', - 127: 'SC_QZ2_QUAD_PER_TILE_H2', - 128: 'SC_QZ2_QUAD_PER_TILE_H3', - 129: 'SC_QZ2_QUAD_PER_TILE_H4', - 130: 'SC_QZ2_QUAD_PER_TILE_H5', - 131: 'SC_QZ2_QUAD_PER_TILE_H6', - 132: 'SC_QZ2_QUAD_PER_TILE_H7', - 133: 'SC_QZ2_QUAD_PER_TILE_H8', - 134: 'SC_QZ2_QUAD_PER_TILE_H9', - 135: 'SC_QZ2_QUAD_PER_TILE_H10', - 136: 'SC_QZ2_QUAD_PER_TILE_H11', - 137: 'SC_QZ2_QUAD_PER_TILE_H12', - 138: 'SC_QZ2_QUAD_PER_TILE_H13', - 139: 'SC_QZ2_QUAD_PER_TILE_H14', - 140: 'SC_QZ2_QUAD_PER_TILE_H15', - 141: 'SC_QZ2_QUAD_PER_TILE_H16', - 142: 'SC_QZ3_QUAD_PER_TILE_H0', - 143: 'SC_QZ3_QUAD_PER_TILE_H1', - 144: 'SC_QZ3_QUAD_PER_TILE_H2', - 145: 'SC_QZ3_QUAD_PER_TILE_H3', - 146: 'SC_QZ3_QUAD_PER_TILE_H4', - 147: 'SC_QZ3_QUAD_PER_TILE_H5', - 148: 'SC_QZ3_QUAD_PER_TILE_H6', - 149: 'SC_QZ3_QUAD_PER_TILE_H7', - 150: 'SC_QZ3_QUAD_PER_TILE_H8', - 151: 'SC_QZ3_QUAD_PER_TILE_H9', - 152: 'SC_QZ3_QUAD_PER_TILE_H10', - 153: 'SC_QZ3_QUAD_PER_TILE_H11', - 154: 'SC_QZ3_QUAD_PER_TILE_H12', - 155: 'SC_QZ3_QUAD_PER_TILE_H13', - 156: 'SC_QZ3_QUAD_PER_TILE_H14', - 157: 'SC_QZ3_QUAD_PER_TILE_H15', - 158: 'SC_QZ3_QUAD_PER_TILE_H16', - 159: 'SC_QZ0_QUAD_COUNT', - 160: 'SC_QZ1_QUAD_COUNT', - 161: 'SC_QZ2_QUAD_COUNT', - 162: 'SC_QZ3_QUAD_COUNT', - 163: 'SC_P0_HIZ_TILE_COUNT', - 164: 'SC_P1_HIZ_TILE_COUNT', - 165: 'SC_P2_HIZ_TILE_COUNT', - 166: 'SC_P3_HIZ_TILE_COUNT', - 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 235: 'SC_P0_HIZ_QUAD_COUNT', - 236: 'SC_P1_HIZ_QUAD_COUNT', - 237: 'SC_P2_HIZ_QUAD_COUNT', - 238: 'SC_P3_HIZ_QUAD_COUNT', - 239: 'SC_P0_DETAIL_QUAD_COUNT', - 240: 'SC_P1_DETAIL_QUAD_COUNT', - 241: 'SC_P2_DETAIL_QUAD_COUNT', - 242: 'SC_P3_DETAIL_QUAD_COUNT', - 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 259: 'SC_EARLYZ_QUAD_COUNT', - 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', - 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', - 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', - 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', - 264: 'SC_PKR_QUAD_PER_ROW_H1', - 265: 'SC_PKR_QUAD_PER_ROW_H2', - 266: 'SC_PKR_4X2_QUAD_SPLIT', - 267: 'SC_PKR_4X2_FILL_QUAD', - 268: 'SC_PKR_END_OF_VECTOR', - 269: 'SC_PKR_CONTROL_XFER', - 270: 'SC_PKR_DBHANG_FORCE_EOV', - 271: 'SC_REG_SCLK_BUSY', - 272: 'SC_GRP0_DYN_SCLK_BUSY', - 273: 'SC_GRP1_DYN_SCLK_BUSY', - 274: 'SC_GRP2_DYN_SCLK_BUSY', - 275: 'SC_GRP3_DYN_SCLK_BUSY', - 276: 'SC_GRP4_DYN_SCLK_BUSY', - 277: 'SC_PA0_SC_DATA_FIFO_RD', - 278: 'SC_PA0_SC_DATA_FIFO_WE', - 279: 'SC_PA1_SC_DATA_FIFO_RD', - 280: 'SC_PA1_SC_DATA_FIFO_WE', - 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', - 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 284: 'SC_PS_ARB_STALLED_FROM_BELOW', - 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', - 286: 'SC_PS_ARB_SC_BUSY', - 287: 'SC_PS_ARB_PA_SC_BUSY', - 288: 'SC_PA2_SC_DATA_FIFO_RD', - 289: 'SC_PA2_SC_DATA_FIFO_WE', - 290: 'SC_PA3_SC_DATA_FIFO_RD', - 291: 'SC_PA3_SC_DATA_FIFO_WE', - 292: 'SC_PA_SC_DEALLOC_0_0_WE', - 293: 'SC_PA_SC_DEALLOC_0_1_WE', - 294: 'SC_PA_SC_DEALLOC_1_0_WE', - 295: 'SC_PA_SC_DEALLOC_1_1_WE', - 296: 'SC_PA_SC_DEALLOC_2_0_WE', - 297: 'SC_PA_SC_DEALLOC_2_1_WE', - 298: 'SC_PA_SC_DEALLOC_3_0_WE', - 299: 'SC_PA_SC_DEALLOC_3_1_WE', - 300: 'SC_PA0_SC_EOP_WE', - 301: 'SC_PA0_SC_EOPG_WE', - 302: 'SC_PA0_SC_EVENT_WE', - 303: 'SC_PA1_SC_EOP_WE', - 304: 'SC_PA1_SC_EOPG_WE', - 305: 'SC_PA1_SC_EVENT_WE', - 306: 'SC_PA2_SC_EOP_WE', - 307: 'SC_PA2_SC_EOPG_WE', - 308: 'SC_PA2_SC_EVENT_WE', - 309: 'SC_PA3_SC_EOP_WE', - 310: 'SC_PA3_SC_EOPG_WE', - 311: 'SC_PA3_SC_EVENT_WE', - 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', - 316: 'SC_PS_ARB_EVENT_SYNC_POP', - 317: 'SC_PS_ENG_MULTICYCLE_BUBBLE', - 318: 'SC_PA0_SC_FPOV_WE', - 319: 'SC_PA1_SC_FPOV_WE', - 320: 'SC_PA2_SC_FPOV_WE', - 321: 'SC_PA3_SC_FPOV_WE', - 322: 'SC_PA0_SC_LPOV_WE', - 323: 'SC_PA1_SC_LPOV_WE', - 324: 'SC_PA2_SC_LPOV_WE', - 325: 'SC_PA3_SC_LPOV_WE', - 326: 'SC_SPI_DEALLOC_0_0', - 327: 'SC_SPI_DEALLOC_0_1', - 328: 'SC_SPI_DEALLOC_0_2', - 329: 'SC_SPI_DEALLOC_1_0', - 330: 'SC_SPI_DEALLOC_1_1', - 331: 'SC_SPI_DEALLOC_1_2', - 332: 'SC_SPI_DEALLOC_2_0', - 333: 'SC_SPI_DEALLOC_2_1', - 334: 'SC_SPI_DEALLOC_2_2', - 335: 'SC_SPI_DEALLOC_3_0', - 336: 'SC_SPI_DEALLOC_3_1', - 337: 'SC_SPI_DEALLOC_3_2', - 338: 'SC_SPI_FPOV_0', - 339: 'SC_SPI_FPOV_1', - 340: 'SC_SPI_FPOV_2', - 341: 'SC_SPI_FPOV_3', - 342: 'SC_SPI_EVENT', - 343: 'SC_PS_TS_EVENT_FIFO_PUSH', - 344: 'SC_PS_TS_EVENT_FIFO_POP', - 345: 'SC_PS_CTX_DONE_FIFO_PUSH', - 346: 'SC_PS_CTX_DONE_FIFO_POP', - 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', - 348: 'SC_EOP_SYNC_WINDOW', - 349: 'SC_PA0_SC_NULL_WE', - 350: 'SC_PA0_SC_NULL_DEALLOC_WE', - 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', - 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 353: 'SC_PA0_SC_DEALLOC_0_RD', - 354: 'SC_PA0_SC_DEALLOC_1_RD', - 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', - 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 357: 'SC_PA1_SC_DEALLOC_0_RD', - 358: 'SC_PA1_SC_DEALLOC_1_RD', - 359: 'SC_PA1_SC_NULL_WE', - 360: 'SC_PA1_SC_NULL_DEALLOC_WE', - 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', - 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 363: 'SC_PA2_SC_DEALLOC_0_RD', - 364: 'SC_PA2_SC_DEALLOC_1_RD', - 365: 'SC_PA2_SC_NULL_WE', - 366: 'SC_PA2_SC_NULL_DEALLOC_WE', - 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', - 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 369: 'SC_PA3_SC_DEALLOC_0_RD', - 370: 'SC_PA3_SC_DEALLOC_1_RD', - 371: 'SC_PA3_SC_NULL_WE', - 372: 'SC_PA3_SC_NULL_DEALLOC_WE', - 373: 'SC_PS_PA0_SC_FIFO_EMPTY', - 374: 'SC_PS_PA0_SC_FIFO_FULL', - 375: 'SC_RESERVED_0', - 376: 'SC_PS_PA1_SC_FIFO_EMPTY', - 377: 'SC_PS_PA1_SC_FIFO_FULL', - 378: 'SC_RESERVED_1', - 379: 'SC_PS_PA2_SC_FIFO_EMPTY', - 380: 'SC_PS_PA2_SC_FIFO_FULL', - 381: 'SC_RESERVED_2', - 382: 'SC_PS_PA3_SC_FIFO_EMPTY', - 383: 'SC_PS_PA3_SC_FIFO_FULL', - 384: 'SC_RESERVED_3', - 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', - 386: 'SC_BUSY_CNT_NOT_ZERO', - 387: 'SC_BM_BUSY', - 388: 'SC_BACKEND_BUSY', - 389: 'SC_SCF_SCB_INTERFACE_BUSY', - 390: 'SC_SCB_BUSY', - 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', - 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 403: 'SC_PBB_BUSY', - 404: 'SC_PBB_BUSY_AND_NO_SENDS', - 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 406: 'SC_PBB_NUM_BINS', - 407: 'SC_PBB_END_OF_BIN', - 408: 'SC_PBB_END_OF_BATCH', - 409: 'SC_PBB_PRIMBIN_PROCESSED', - 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', - 411: 'SC_PBB_NONBINNED_PRIM', - 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', - 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', - 424: 'SC_POPS_FORCE_EOV', - 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 428: 'SC_FULL_FULL_QUAD', - 429: 'SC_FULL_HALF_QUAD', - 430: 'SC_FULL_QTR_QUAD', - 431: 'SC_HALF_FULL_QUAD', - 432: 'SC_HALF_HALF_QUAD', - 433: 'SC_HALF_QTR_QUAD', - 434: 'SC_QTR_FULL_QUAD', - 435: 'SC_QTR_HALF_QUAD', - 436: 'SC_QTR_QTR_QUAD', - 437: 'SC_GRP5_DYN_SCLK_BUSY', - 438: 'SC_GRP6_DYN_SCLK_BUSY', - 439: 'SC_GRP7_DYN_SCLK_BUSY', - 440: 'SC_GRP8_DYN_SCLK_BUSY', - 441: 'SC_GRP9_DYN_SCLK_BUSY', - 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', - 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 444: 'SC_PK_BUSY', - 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 446: 'SC_PK_DEALLOC_WAVE_BREAK', - 447: 'SC_SPI_SEND', - 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 449: 'SC_SPI_CREDIT_AT_MAX', - 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 451: 'SC_BCI_SEND', - 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 453: 'SC_BCI_CREDIT_AT_MAX', - 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 455: 'SC_SPIBC_FULL_FREEZE', - 456: 'SC_PW_BM_PASS_EMPTY_PRIM', - 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 475: 'SC_DB0_TILE_INTERFACE_BUSY', - 476: 'SC_DB0_TILE_INTERFACE_SEND', - 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 483: 'SC_DB1_TILE_INTERFACE_BUSY', - 484: 'SC_DB1_TILE_INTERFACE_SEND', - 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 491: 'SC_BACKEND_PRIM_FIFO_FULL', - 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 503: 'SC_STALLED_BY_DB0_TILEFIFO', - 504: 'SC_DB0_QUAD_INTF_SEND', - 505: 'SC_DB0_QUAD_INTF_BUSY', - 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', - 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', - 508: 'SC_DB0_QUAD_INTF_IDLE', - 509: 'SC_DB1_QUAD_INTF_SEND', - 510: 'SC_STALLED_BY_DB1_TILEFIFO', - 511: 'SC_DB1_QUAD_INTF_BUSY', - 512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB', - 513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', - 514: 'SC_DB1_QUAD_INTF_IDLE', - 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', - 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', - 517: 'SC_FSR_WALKED', - 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', - 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 522: 'SC_DB0_TILE_MASK_FIFO_FULL', - 523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', - 524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 525: 'SC_DB1_TILE_MASK_FIFO_FULL', - 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 529: 'SC_PS_PM_PFF_PW_FULL', - 530: 'SC_PS_PM_ZFF_PW_FULL', - 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', - 533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', - 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', - 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', - 569: 'SC_PBB_RESERVED', - 570: 'SC_BM_BE0_STALLED', - 571: 'SC_BM_BE1_STALLED', - 572: 'SC_BM_BE2_STALLED', - 573: 'SC_BM_BE3_STALLED', - 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', -} -SC_SRPS_WINDOW_VALID = 0 -SC_PSSW_WINDOW_VALID = 1 -SC_TPQZ_WINDOW_VALID = 2 -SC_QZQP_WINDOW_VALID = 3 -SC_TRPK_WINDOW_VALID = 4 -SC_SRPS_WINDOW_VALID_BUSY = 5 -SC_PSSW_WINDOW_VALID_BUSY = 6 -SC_TPQZ_WINDOW_VALID_BUSY = 7 -SC_QZQP_WINDOW_VALID_BUSY = 8 -SC_TRPK_WINDOW_VALID_BUSY = 9 -SC_STARVED_BY_PA = 10 -SC_STALLED_BY_PRIMFIFO = 11 -SC_STALLED_BY_DB_TILE = 12 -SC_STARVED_BY_DB_TILE = 13 -SC_STALLED_BY_TILEORDERFIFO = 14 -SC_STALLED_BY_TILEFIFO = 15 -SC_STALLED_BY_DB_QUAD = 16 -SC_STARVED_BY_DB_QUAD = 17 -SC_STALLED_BY_QUADFIFO = 18 -SC_STALLED_BY_BCI = 19 -SC_STALLED_BY_SPI = 20 -SC_SCISSOR_DISCARD = 21 -SC_BB_DISCARD = 22 -SC_SUPERTILE_COUNT = 23 -SC_SUPERTILE_PER_PRIM_H0 = 24 -SC_SUPERTILE_PER_PRIM_H1 = 25 -SC_SUPERTILE_PER_PRIM_H2 = 26 -SC_SUPERTILE_PER_PRIM_H3 = 27 -SC_SUPERTILE_PER_PRIM_H4 = 28 -SC_SUPERTILE_PER_PRIM_H5 = 29 -SC_SUPERTILE_PER_PRIM_H6 = 30 -SC_SUPERTILE_PER_PRIM_H7 = 31 -SC_SUPERTILE_PER_PRIM_H8 = 32 -SC_SUPERTILE_PER_PRIM_H9 = 33 -SC_SUPERTILE_PER_PRIM_H10 = 34 -SC_SUPERTILE_PER_PRIM_H11 = 35 -SC_SUPERTILE_PER_PRIM_H12 = 36 -SC_SUPERTILE_PER_PRIM_H13 = 37 -SC_SUPERTILE_PER_PRIM_H14 = 38 -SC_SUPERTILE_PER_PRIM_H15 = 39 -SC_SUPERTILE_PER_PRIM_H16 = 40 -SC_TILE_PER_PRIM_H0 = 41 -SC_TILE_PER_PRIM_H1 = 42 -SC_TILE_PER_PRIM_H2 = 43 -SC_TILE_PER_PRIM_H3 = 44 -SC_TILE_PER_PRIM_H4 = 45 -SC_TILE_PER_PRIM_H5 = 46 -SC_TILE_PER_PRIM_H6 = 47 -SC_TILE_PER_PRIM_H7 = 48 -SC_TILE_PER_PRIM_H8 = 49 -SC_TILE_PER_PRIM_H9 = 50 -SC_TILE_PER_PRIM_H10 = 51 -SC_TILE_PER_PRIM_H11 = 52 -SC_TILE_PER_PRIM_H12 = 53 -SC_TILE_PER_PRIM_H13 = 54 -SC_TILE_PER_PRIM_H14 = 55 -SC_TILE_PER_PRIM_H15 = 56 -SC_TILE_PER_PRIM_H16 = 57 -SC_TILE_PER_SUPERTILE_H0 = 58 -SC_TILE_PER_SUPERTILE_H1 = 59 -SC_TILE_PER_SUPERTILE_H2 = 60 -SC_TILE_PER_SUPERTILE_H3 = 61 -SC_TILE_PER_SUPERTILE_H4 = 62 -SC_TILE_PER_SUPERTILE_H5 = 63 -SC_TILE_PER_SUPERTILE_H6 = 64 -SC_TILE_PER_SUPERTILE_H7 = 65 -SC_TILE_PER_SUPERTILE_H8 = 66 -SC_TILE_PER_SUPERTILE_H9 = 67 -SC_TILE_PER_SUPERTILE_H10 = 68 -SC_TILE_PER_SUPERTILE_H11 = 69 -SC_TILE_PER_SUPERTILE_H12 = 70 -SC_TILE_PER_SUPERTILE_H13 = 71 -SC_TILE_PER_SUPERTILE_H14 = 72 -SC_TILE_PER_SUPERTILE_H15 = 73 -SC_TILE_PER_SUPERTILE_H16 = 74 -SC_TILE_PICKED_H1 = 75 -SC_TILE_PICKED_H2 = 76 -SC_TILE_PICKED_H3 = 77 -SC_TILE_PICKED_H4 = 78 -SC_QZ0_TILE_COUNT = 79 -SC_QZ1_TILE_COUNT = 80 -SC_QZ2_TILE_COUNT = 81 -SC_QZ3_TILE_COUNT = 82 -SC_QZ0_TILE_COVERED_COUNT = 83 -SC_QZ1_TILE_COVERED_COUNT = 84 -SC_QZ2_TILE_COVERED_COUNT = 85 -SC_QZ3_TILE_COVERED_COUNT = 86 -SC_QZ0_TILE_NOT_COVERED_COUNT = 87 -SC_QZ1_TILE_NOT_COVERED_COUNT = 88 -SC_QZ2_TILE_NOT_COVERED_COUNT = 89 -SC_QZ3_TILE_NOT_COVERED_COUNT = 90 -SC_QZ0_QUAD_PER_TILE_H0 = 91 -SC_QZ0_QUAD_PER_TILE_H1 = 92 -SC_QZ0_QUAD_PER_TILE_H2 = 93 -SC_QZ0_QUAD_PER_TILE_H3 = 94 -SC_QZ0_QUAD_PER_TILE_H4 = 95 -SC_QZ0_QUAD_PER_TILE_H5 = 96 -SC_QZ0_QUAD_PER_TILE_H6 = 97 -SC_QZ0_QUAD_PER_TILE_H7 = 98 -SC_QZ0_QUAD_PER_TILE_H8 = 99 -SC_QZ0_QUAD_PER_TILE_H9 = 100 -SC_QZ0_QUAD_PER_TILE_H10 = 101 -SC_QZ0_QUAD_PER_TILE_H11 = 102 -SC_QZ0_QUAD_PER_TILE_H12 = 103 -SC_QZ0_QUAD_PER_TILE_H13 = 104 -SC_QZ0_QUAD_PER_TILE_H14 = 105 -SC_QZ0_QUAD_PER_TILE_H15 = 106 -SC_QZ0_QUAD_PER_TILE_H16 = 107 -SC_QZ1_QUAD_PER_TILE_H0 = 108 -SC_QZ1_QUAD_PER_TILE_H1 = 109 -SC_QZ1_QUAD_PER_TILE_H2 = 110 -SC_QZ1_QUAD_PER_TILE_H3 = 111 -SC_QZ1_QUAD_PER_TILE_H4 = 112 -SC_QZ1_QUAD_PER_TILE_H5 = 113 -SC_QZ1_QUAD_PER_TILE_H6 = 114 -SC_QZ1_QUAD_PER_TILE_H7 = 115 -SC_QZ1_QUAD_PER_TILE_H8 = 116 -SC_QZ1_QUAD_PER_TILE_H9 = 117 -SC_QZ1_QUAD_PER_TILE_H10 = 118 -SC_QZ1_QUAD_PER_TILE_H11 = 119 -SC_QZ1_QUAD_PER_TILE_H12 = 120 -SC_QZ1_QUAD_PER_TILE_H13 = 121 -SC_QZ1_QUAD_PER_TILE_H14 = 122 -SC_QZ1_QUAD_PER_TILE_H15 = 123 -SC_QZ1_QUAD_PER_TILE_H16 = 124 -SC_QZ2_QUAD_PER_TILE_H0 = 125 -SC_QZ2_QUAD_PER_TILE_H1 = 126 -SC_QZ2_QUAD_PER_TILE_H2 = 127 -SC_QZ2_QUAD_PER_TILE_H3 = 128 -SC_QZ2_QUAD_PER_TILE_H4 = 129 -SC_QZ2_QUAD_PER_TILE_H5 = 130 -SC_QZ2_QUAD_PER_TILE_H6 = 131 -SC_QZ2_QUAD_PER_TILE_H7 = 132 -SC_QZ2_QUAD_PER_TILE_H8 = 133 -SC_QZ2_QUAD_PER_TILE_H9 = 134 -SC_QZ2_QUAD_PER_TILE_H10 = 135 -SC_QZ2_QUAD_PER_TILE_H11 = 136 -SC_QZ2_QUAD_PER_TILE_H12 = 137 -SC_QZ2_QUAD_PER_TILE_H13 = 138 -SC_QZ2_QUAD_PER_TILE_H14 = 139 -SC_QZ2_QUAD_PER_TILE_H15 = 140 -SC_QZ2_QUAD_PER_TILE_H16 = 141 -SC_QZ3_QUAD_PER_TILE_H0 = 142 -SC_QZ3_QUAD_PER_TILE_H1 = 143 -SC_QZ3_QUAD_PER_TILE_H2 = 144 -SC_QZ3_QUAD_PER_TILE_H3 = 145 -SC_QZ3_QUAD_PER_TILE_H4 = 146 -SC_QZ3_QUAD_PER_TILE_H5 = 147 -SC_QZ3_QUAD_PER_TILE_H6 = 148 -SC_QZ3_QUAD_PER_TILE_H7 = 149 -SC_QZ3_QUAD_PER_TILE_H8 = 150 -SC_QZ3_QUAD_PER_TILE_H9 = 151 -SC_QZ3_QUAD_PER_TILE_H10 = 152 -SC_QZ3_QUAD_PER_TILE_H11 = 153 -SC_QZ3_QUAD_PER_TILE_H12 = 154 -SC_QZ3_QUAD_PER_TILE_H13 = 155 -SC_QZ3_QUAD_PER_TILE_H14 = 156 -SC_QZ3_QUAD_PER_TILE_H15 = 157 -SC_QZ3_QUAD_PER_TILE_H16 = 158 -SC_QZ0_QUAD_COUNT = 159 -SC_QZ1_QUAD_COUNT = 160 -SC_QZ2_QUAD_COUNT = 161 -SC_QZ3_QUAD_COUNT = 162 -SC_P0_HIZ_TILE_COUNT = 163 -SC_P1_HIZ_TILE_COUNT = 164 -SC_P2_HIZ_TILE_COUNT = 165 -SC_P3_HIZ_TILE_COUNT = 166 -SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 -SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 -SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 -SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 -SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 -SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 -SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 -SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 -SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 -SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 -SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 -SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 -SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 -SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 -SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 -SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 -SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 -SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 -SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 -SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 -SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 -SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 -SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 -SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 -SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 -SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 -SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 -SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 -SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 -SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 -SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 -SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 -SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 -SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 -SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 -SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 -SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 -SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 -SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 -SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 -SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 -SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 -SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 -SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 -SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 -SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 -SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 -SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 -SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 -SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 -SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 -SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 -SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 -SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 -SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 -SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 -SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 -SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 -SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 -SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 -SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 -SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 -SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 -SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 -SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 -SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 -SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 -SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 -SC_P0_HIZ_QUAD_COUNT = 235 -SC_P1_HIZ_QUAD_COUNT = 236 -SC_P2_HIZ_QUAD_COUNT = 237 -SC_P3_HIZ_QUAD_COUNT = 238 -SC_P0_DETAIL_QUAD_COUNT = 239 -SC_P1_DETAIL_QUAD_COUNT = 240 -SC_P2_DETAIL_QUAD_COUNT = 241 -SC_P3_DETAIL_QUAD_COUNT = 242 -SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 -SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 -SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 -SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 -SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 -SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 -SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 -SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 -SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 -SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 -SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 -SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 -SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 -SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 -SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 -SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 -SC_EARLYZ_QUAD_COUNT = 259 -SC_EARLYZ_QUAD_WITH_1_PIX = 260 -SC_EARLYZ_QUAD_WITH_2_PIX = 261 -SC_EARLYZ_QUAD_WITH_3_PIX = 262 -SC_EARLYZ_QUAD_WITH_4_PIX = 263 -SC_PKR_QUAD_PER_ROW_H1 = 264 -SC_PKR_QUAD_PER_ROW_H2 = 265 -SC_PKR_4X2_QUAD_SPLIT = 266 -SC_PKR_4X2_FILL_QUAD = 267 -SC_PKR_END_OF_VECTOR = 268 -SC_PKR_CONTROL_XFER = 269 -SC_PKR_DBHANG_FORCE_EOV = 270 -SC_REG_SCLK_BUSY = 271 -SC_GRP0_DYN_SCLK_BUSY = 272 -SC_GRP1_DYN_SCLK_BUSY = 273 -SC_GRP2_DYN_SCLK_BUSY = 274 -SC_GRP3_DYN_SCLK_BUSY = 275 -SC_GRP4_DYN_SCLK_BUSY = 276 -SC_PA0_SC_DATA_FIFO_RD = 277 -SC_PA0_SC_DATA_FIFO_WE = 278 -SC_PA1_SC_DATA_FIFO_RD = 279 -SC_PA1_SC_DATA_FIFO_WE = 280 -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 -SC_PS_ARB_STALLED_FROM_BELOW = 284 -SC_PS_ARB_STARVED_FROM_ABOVE = 285 -SC_PS_ARB_SC_BUSY = 286 -SC_PS_ARB_PA_SC_BUSY = 287 -SC_PA2_SC_DATA_FIFO_RD = 288 -SC_PA2_SC_DATA_FIFO_WE = 289 -SC_PA3_SC_DATA_FIFO_RD = 290 -SC_PA3_SC_DATA_FIFO_WE = 291 -SC_PA_SC_DEALLOC_0_0_WE = 292 -SC_PA_SC_DEALLOC_0_1_WE = 293 -SC_PA_SC_DEALLOC_1_0_WE = 294 -SC_PA_SC_DEALLOC_1_1_WE = 295 -SC_PA_SC_DEALLOC_2_0_WE = 296 -SC_PA_SC_DEALLOC_2_1_WE = 297 -SC_PA_SC_DEALLOC_3_0_WE = 298 -SC_PA_SC_DEALLOC_3_1_WE = 299 -SC_PA0_SC_EOP_WE = 300 -SC_PA0_SC_EOPG_WE = 301 -SC_PA0_SC_EVENT_WE = 302 -SC_PA1_SC_EOP_WE = 303 -SC_PA1_SC_EOPG_WE = 304 -SC_PA1_SC_EVENT_WE = 305 -SC_PA2_SC_EOP_WE = 306 -SC_PA2_SC_EOPG_WE = 307 -SC_PA2_SC_EVENT_WE = 308 -SC_PA3_SC_EOP_WE = 309 -SC_PA3_SC_EOPG_WE = 310 -SC_PA3_SC_EVENT_WE = 311 -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 -SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 -SC_PS_ARB_EOP_POP_SYNC_POP = 315 -SC_PS_ARB_EVENT_SYNC_POP = 316 -SC_PS_ENG_MULTICYCLE_BUBBLE = 317 -SC_PA0_SC_FPOV_WE = 318 -SC_PA1_SC_FPOV_WE = 319 -SC_PA2_SC_FPOV_WE = 320 -SC_PA3_SC_FPOV_WE = 321 -SC_PA0_SC_LPOV_WE = 322 -SC_PA1_SC_LPOV_WE = 323 -SC_PA2_SC_LPOV_WE = 324 -SC_PA3_SC_LPOV_WE = 325 -SC_SPI_DEALLOC_0_0 = 326 -SC_SPI_DEALLOC_0_1 = 327 -SC_SPI_DEALLOC_0_2 = 328 -SC_SPI_DEALLOC_1_0 = 329 -SC_SPI_DEALLOC_1_1 = 330 -SC_SPI_DEALLOC_1_2 = 331 -SC_SPI_DEALLOC_2_0 = 332 -SC_SPI_DEALLOC_2_1 = 333 -SC_SPI_DEALLOC_2_2 = 334 -SC_SPI_DEALLOC_3_0 = 335 -SC_SPI_DEALLOC_3_1 = 336 -SC_SPI_DEALLOC_3_2 = 337 -SC_SPI_FPOV_0 = 338 -SC_SPI_FPOV_1 = 339 -SC_SPI_FPOV_2 = 340 -SC_SPI_FPOV_3 = 341 -SC_SPI_EVENT = 342 -SC_PS_TS_EVENT_FIFO_PUSH = 343 -SC_PS_TS_EVENT_FIFO_POP = 344 -SC_PS_CTX_DONE_FIFO_PUSH = 345 -SC_PS_CTX_DONE_FIFO_POP = 346 -SC_MULTICYCLE_BUBBLE_FREEZE = 347 -SC_EOP_SYNC_WINDOW = 348 -SC_PA0_SC_NULL_WE = 349 -SC_PA0_SC_NULL_DEALLOC_WE = 350 -SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 -SC_PA0_SC_DATA_FIFO_EOP_RD = 352 -SC_PA0_SC_DEALLOC_0_RD = 353 -SC_PA0_SC_DEALLOC_1_RD = 354 -SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 -SC_PA1_SC_DATA_FIFO_EOP_RD = 356 -SC_PA1_SC_DEALLOC_0_RD = 357 -SC_PA1_SC_DEALLOC_1_RD = 358 -SC_PA1_SC_NULL_WE = 359 -SC_PA1_SC_NULL_DEALLOC_WE = 360 -SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 -SC_PA2_SC_DATA_FIFO_EOP_RD = 362 -SC_PA2_SC_DEALLOC_0_RD = 363 -SC_PA2_SC_DEALLOC_1_RD = 364 -SC_PA2_SC_NULL_WE = 365 -SC_PA2_SC_NULL_DEALLOC_WE = 366 -SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 -SC_PA3_SC_DATA_FIFO_EOP_RD = 368 -SC_PA3_SC_DEALLOC_0_RD = 369 -SC_PA3_SC_DEALLOC_1_RD = 370 -SC_PA3_SC_NULL_WE = 371 -SC_PA3_SC_NULL_DEALLOC_WE = 372 -SC_PS_PA0_SC_FIFO_EMPTY = 373 -SC_PS_PA0_SC_FIFO_FULL = 374 -SC_RESERVED_0 = 375 -SC_PS_PA1_SC_FIFO_EMPTY = 376 -SC_PS_PA1_SC_FIFO_FULL = 377 -SC_RESERVED_1 = 378 -SC_PS_PA2_SC_FIFO_EMPTY = 379 -SC_PS_PA2_SC_FIFO_FULL = 380 -SC_RESERVED_2 = 381 -SC_PS_PA3_SC_FIFO_EMPTY = 382 -SC_PS_PA3_SC_FIFO_FULL = 383 -SC_RESERVED_3 = 384 -SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 -SC_BUSY_CNT_NOT_ZERO = 386 -SC_BM_BUSY = 387 -SC_BACKEND_BUSY = 388 -SC_SCF_SCB_INTERFACE_BUSY = 389 -SC_SCB_BUSY = 390 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 -SC_PBB_BIN_HIST_NUM_PRIMS = 393 -SC_PBB_BATCH_HIST_NUM_PRIMS = 394 -SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 -SC_PBB_BUSY = 403 -SC_PBB_BUSY_AND_NO_SENDS = 404 -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 -SC_PBB_NUM_BINS = 406 -SC_PBB_END_OF_BIN = 407 -SC_PBB_END_OF_BATCH = 408 -SC_PBB_PRIMBIN_PROCESSED = 409 -SC_PBB_PRIM_ADDED_TO_BATCH = 410 -SC_PBB_NONBINNED_PRIM = 411 -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 -SC_POPS_INTRA_WAVE_OVERLAPS = 423 -SC_POPS_FORCE_EOV = 424 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 -SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 -SC_FULL_FULL_QUAD = 428 -SC_FULL_HALF_QUAD = 429 -SC_FULL_QTR_QUAD = 430 -SC_HALF_FULL_QUAD = 431 -SC_HALF_HALF_QUAD = 432 -SC_HALF_QTR_QUAD = 433 -SC_QTR_FULL_QUAD = 434 -SC_QTR_HALF_QUAD = 435 -SC_QTR_QTR_QUAD = 436 -SC_GRP5_DYN_SCLK_BUSY = 437 -SC_GRP6_DYN_SCLK_BUSY = 438 -SC_GRP7_DYN_SCLK_BUSY = 439 -SC_GRP8_DYN_SCLK_BUSY = 440 -SC_GRP9_DYN_SCLK_BUSY = 441 -SC_PS_TO_BE_SCLK_GATE_STALL = 442 -SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 -SC_PK_BUSY = 444 -SC_PK_MAX_DEALLOC_FORCE_EOV = 445 -SC_PK_DEALLOC_WAVE_BREAK = 446 -SC_SPI_SEND = 447 -SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 -SC_SPI_CREDIT_AT_MAX = 449 -SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 -SC_BCI_SEND = 451 -SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 -SC_BCI_CREDIT_AT_MAX = 453 -SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 -SC_SPIBC_FULL_FREEZE = 455 -SC_PW_BM_PASS_EMPTY_PRIM = 456 -SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 -SC_DB0_TILE_INTERFACE_BUSY = 475 -SC_DB0_TILE_INTERFACE_SEND = 476 -SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 -SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 -SC_DB0_TILE_INTERFACE_SEND_SOP = 479 -SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 -SC_DB1_TILE_INTERFACE_BUSY = 483 -SC_DB1_TILE_INTERFACE_SEND = 484 -SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 -SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 -SC_DB1_TILE_INTERFACE_SEND_SOP = 487 -SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 -SC_BACKEND_PRIM_FIFO_FULL = 491 -SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 -SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 -SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 -SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 -SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 -SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 -SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 -SC_STALLED_BY_DB0_TILEFIFO = 503 -SC_DB0_QUAD_INTF_SEND = 504 -SC_DB0_QUAD_INTF_BUSY = 505 -SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 -SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 -SC_DB0_QUAD_INTF_IDLE = 508 -SC_DB1_QUAD_INTF_SEND = 509 -SC_STALLED_BY_DB1_TILEFIFO = 510 -SC_DB1_QUAD_INTF_BUSY = 511 -SC_DB1_QUAD_INTF_STALLED_BY_DB = 512 -SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513 -SC_DB1_QUAD_INTF_IDLE = 514 -SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 -SC_PKR_WAVE_BREAK_FULL_TILE = 516 -SC_FSR_WALKED = 517 -SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 -SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 -SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 -SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 -SC_DB0_TILE_MASK_FIFO_FULL = 522 -SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523 -SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524 -SC_DB1_TILE_MASK_FIFO_FULL = 525 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 -SC_PS_PM_PFF_PW_FULL = 529 -SC_PS_PM_ZFF_PW_FULL = 530 -SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 -SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532 -SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533 -SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534 -SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 -SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 -SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 -SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 -SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539 -SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 -SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 -SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 -SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 -SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 -SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 -SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 -SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547 -SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 -SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 -SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 -SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 -SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 -SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 -SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 -SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 -SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 -SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 -SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 -SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 -SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 -SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 -SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 -SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 -SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 -SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 -SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 -SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568 -SC_PBB_RESERVED = 569 -SC_BM_BE0_STALLED = 570 -SC_BM_BE1_STALLED = 571 -SC_BM_BE2_STALLED = 572 -SC_BM_BE3_STALLED = 573 -SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 -SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 -SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 -SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 -SC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ScMap' -ScMap__enumvalues = { - 0: 'RASTER_CONFIG_SC_MAP_0', - 1: 'RASTER_CONFIG_SC_MAP_1', - 2: 'RASTER_CONFIG_SC_MAP_2', - 3: 'RASTER_CONFIG_SC_MAP_3', -} -RASTER_CONFIG_SC_MAP_0 = 0 -RASTER_CONFIG_SC_MAP_1 = 1 -RASTER_CONFIG_SC_MAP_2 = 2 -RASTER_CONFIG_SC_MAP_3 = 3 -ScMap = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMode' -ScUncertaintyRegionMode__enumvalues = { - 0: 'SC_HALF_LSB', - 1: 'SC_LSB_ONE_SIDED', - 2: 'SC_LSB_TWO_SIDED', -} -SC_HALF_LSB = 0 -SC_LSB_ONE_SIDED = 1 -SC_LSB_TWO_SIDED = 2 -ScUncertaintyRegionMode = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMult' -ScUncertaintyRegionMult__enumvalues = { - 0: 'SC_UR_1X', - 1: 'SC_UR_2X', - 2: 'SC_UR_4X', - 3: 'SC_UR_8X', -} -SC_UR_1X = 0 -SC_UR_2X = 1 -SC_UR_4X = 2 -SC_UR_8X = 3 -ScUncertaintyRegionMult = ctypes.c_uint32 # enum - -# values for enumeration 'ScXsel' -ScXsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 -ScXsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScYsel' -ScYsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 -ScYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeMap' -SeMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_MAP_0', - 1: 'RASTER_CONFIG_SE_MAP_1', - 2: 'RASTER_CONFIG_SE_MAP_2', - 3: 'RASTER_CONFIG_SE_MAP_3', -} -RASTER_CONFIG_SE_MAP_0 = 0 -RASTER_CONFIG_SE_MAP_1 = 1 -RASTER_CONFIG_SE_MAP_2 = 2 -RASTER_CONFIG_SE_MAP_3 = 3 -SeMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairMap' -SePairMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', - 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', - 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', - 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', -} -RASTER_CONFIG_SE_PAIR_MAP_0 = 0 -RASTER_CONFIG_SE_PAIR_MAP_1 = 1 -RASTER_CONFIG_SE_PAIR_MAP_2 = 2 -RASTER_CONFIG_SE_PAIR_MAP_3 = 3 -SePairMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairXsel' -SePairXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 -SePairXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairYsel' -SePairYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 -SePairYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeXsel' -SeXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 -SeXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeYsel' -SeYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 -SeYsel = ctypes.c_uint32 # enum - -# values for enumeration 'VRSCombinerModeSC' -VRSCombinerModeSC__enumvalues = { - 0: 'SC_VRS_COMB_MODE_PASSTHRU', - 1: 'SC_VRS_COMB_MODE_OVERRIDE', - 2: 'SC_VRS_COMB_MODE_MIN', - 3: 'SC_VRS_COMB_MODE_MAX', - 4: 'SC_VRS_COMB_MODE_SATURATE', -} -SC_VRS_COMB_MODE_PASSTHRU = 0 -SC_VRS_COMB_MODE_OVERRIDE = 1 -SC_VRS_COMB_MODE_MIN = 2 -SC_VRS_COMB_MODE_MAX = 3 -SC_VRS_COMB_MODE_SATURATE = 4 -VRSCombinerModeSC = ctypes.c_uint32 # enum - -# values for enumeration 'VRSrate' -VRSrate__enumvalues = { - 0: 'VRS_SHADING_RATE_1X1', - 1: 'VRS_SHADING_RATE_1X2', - 2: 'VRS_SHADING_RATE_UNDEFINED0', - 3: 'VRS_SHADING_RATE_UNDEFINED1', - 4: 'VRS_SHADING_RATE_2X1', - 5: 'VRS_SHADING_RATE_2X2', - 6: 'VRS_SHADING_RATE_2X4', - 7: 'VRS_SHADING_RATE_UNDEFINED2', - 8: 'VRS_SHADING_RATE_UNDEFINED3', - 9: 'VRS_SHADING_RATE_4X2', - 10: 'VRS_SHADING_RATE_4X4', - 11: 'VRS_SHADING_RATE_UNDEFINED4', - 12: 'VRS_SHADING_RATE_16X_SSAA', - 13: 'VRS_SHADING_RATE_8X_SSAA', - 14: 'VRS_SHADING_RATE_4X_SSAA', - 15: 'VRS_SHADING_RATE_2X_SSAA', -} -VRS_SHADING_RATE_1X1 = 0 -VRS_SHADING_RATE_1X2 = 1 -VRS_SHADING_RATE_UNDEFINED0 = 2 -VRS_SHADING_RATE_UNDEFINED1 = 3 -VRS_SHADING_RATE_2X1 = 4 -VRS_SHADING_RATE_2X2 = 5 -VRS_SHADING_RATE_2X4 = 6 -VRS_SHADING_RATE_UNDEFINED2 = 7 -VRS_SHADING_RATE_UNDEFINED3 = 8 -VRS_SHADING_RATE_4X2 = 9 -VRS_SHADING_RATE_4X4 = 10 -VRS_SHADING_RATE_UNDEFINED4 = 11 -VRS_SHADING_RATE_16X_SSAA = 12 -VRS_SHADING_RATE_8X_SSAA = 13 -VRS_SHADING_RATE_4X_SSAA = 14 -VRS_SHADING_RATE_2X_SSAA = 15 -VRSrate = ctypes.c_uint32 # enum - -# values for enumeration 'TC_EA_CID' -TC_EA_CID__enumvalues = { - 0: 'TC_EA_CID_RT', - 1: 'TC_EA_CID_FMASK', - 2: 'TC_EA_CID_DCC', - 3: 'TC_EA_CID_TCPMETA', - 4: 'TC_EA_CID_Z', - 5: 'TC_EA_CID_STENCIL', - 6: 'TC_EA_CID_HTILE', - 7: 'TC_EA_CID_MISC', - 8: 'TC_EA_CID_TCP', - 9: 'TC_EA_CID_SQC', - 10: 'TC_EA_CID_CPF', - 11: 'TC_EA_CID_CPG', - 12: 'TC_EA_CID_IA', - 13: 'TC_EA_CID_WD', - 14: 'TC_EA_CID_PA', - 15: 'TC_EA_CID_UTCL2_TPI', -} -TC_EA_CID_RT = 0 -TC_EA_CID_FMASK = 1 -TC_EA_CID_DCC = 2 -TC_EA_CID_TCPMETA = 3 -TC_EA_CID_Z = 4 -TC_EA_CID_STENCIL = 5 -TC_EA_CID_HTILE = 6 -TC_EA_CID_MISC = 7 -TC_EA_CID_TCP = 8 -TC_EA_CID_SQC = 9 -TC_EA_CID_CPF = 10 -TC_EA_CID_CPG = 11 -TC_EA_CID_IA = 12 -TC_EA_CID_WD = 13 -TC_EA_CID_PA = 14 -TC_EA_CID_UTCL2_TPI = 15 -TC_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'TC_NACKS' -TC_NACKS__enumvalues = { - 0: 'TC_NACK_NO_FAULT', - 1: 'TC_NACK_PAGE_FAULT', - 2: 'TC_NACK_PROTECTION_FAULT', - 3: 'TC_NACK_DATA_ERROR', -} -TC_NACK_NO_FAULT = 0 -TC_NACK_PAGE_FAULT = 1 -TC_NACK_PROTECTION_FAULT = 2 -TC_NACK_DATA_ERROR = 3 -TC_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP' -TC_OP__enumvalues = { - 0: 'TC_OP_READ', - 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'TC_OP_ATOMIC_FMIN_RTN_32', - 3: 'TC_OP_ATOMIC_FMAX_RTN_32', - 4: 'TC_OP_RESERVED_FOP_RTN_32_0', - 5: 'TC_OP_RESERVED_FADD_RTN_32', - 6: 'TC_OP_RESERVED_FOP_RTN_32_2', - 7: 'TC_OP_ATOMIC_SWAP_RTN_32', - 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'TC_OP_PROBE_FILTER', - 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'TC_OP_ATOMIC_ADD_RTN_32', - 16: 'TC_OP_ATOMIC_SUB_RTN_32', - 17: 'TC_OP_ATOMIC_SMIN_RTN_32', - 18: 'TC_OP_ATOMIC_UMIN_RTN_32', - 19: 'TC_OP_ATOMIC_SMAX_RTN_32', - 20: 'TC_OP_ATOMIC_UMAX_RTN_32', - 21: 'TC_OP_ATOMIC_AND_RTN_32', - 22: 'TC_OP_ATOMIC_OR_RTN_32', - 23: 'TC_OP_ATOMIC_XOR_RTN_32', - 24: 'TC_OP_ATOMIC_INC_RTN_32', - 25: 'TC_OP_ATOMIC_DEC_RTN_32', - 26: 'TC_OP_WBINVL1_VOL', - 27: 'TC_OP_WBINVL1_SD', - 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 32: 'TC_OP_WRITE', - 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'TC_OP_ATOMIC_FMIN_RTN_64', - 35: 'TC_OP_ATOMIC_FMAX_RTN_64', - 36: 'TC_OP_RESERVED_FOP_RTN_64_0', - 37: 'TC_OP_RESERVED_FOP_RTN_64_1', - 38: 'TC_OP_RESERVED_FOP_RTN_64_2', - 39: 'TC_OP_ATOMIC_SWAP_RTN_64', - 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 44: 'TC_OP_WBINVL2_SD', - 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 47: 'TC_OP_ATOMIC_ADD_RTN_64', - 48: 'TC_OP_ATOMIC_SUB_RTN_64', - 49: 'TC_OP_ATOMIC_SMIN_RTN_64', - 50: 'TC_OP_ATOMIC_UMIN_RTN_64', - 51: 'TC_OP_ATOMIC_SMAX_RTN_64', - 52: 'TC_OP_ATOMIC_UMAX_RTN_64', - 53: 'TC_OP_ATOMIC_AND_RTN_64', - 54: 'TC_OP_ATOMIC_OR_RTN_64', - 55: 'TC_OP_ATOMIC_XOR_RTN_64', - 56: 'TC_OP_ATOMIC_INC_RTN_64', - 57: 'TC_OP_ATOMIC_DEC_RTN_64', - 58: 'TC_OP_WBL2_NC', - 59: 'TC_OP_WBL2_WC', - 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', - 64: 'TC_OP_WBINVL1', - 65: 'TC_OP_ATOMIC_FCMPSWAP_32', - 66: 'TC_OP_ATOMIC_FMIN_32', - 67: 'TC_OP_ATOMIC_FMAX_32', - 68: 'TC_OP_RESERVED_FOP_32_0', - 69: 'TC_OP_RESERVED_FADD_32', - 70: 'TC_OP_RESERVED_FOP_32_2', - 71: 'TC_OP_ATOMIC_SWAP_32', - 72: 'TC_OP_ATOMIC_CMPSWAP_32', - 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'TC_OP_INV_METADATA', - 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 79: 'TC_OP_ATOMIC_ADD_32', - 80: 'TC_OP_ATOMIC_SUB_32', - 81: 'TC_OP_ATOMIC_SMIN_32', - 82: 'TC_OP_ATOMIC_UMIN_32', - 83: 'TC_OP_ATOMIC_SMAX_32', - 84: 'TC_OP_ATOMIC_UMAX_32', - 85: 'TC_OP_ATOMIC_AND_32', - 86: 'TC_OP_ATOMIC_OR_32', - 87: 'TC_OP_ATOMIC_XOR_32', - 88: 'TC_OP_ATOMIC_INC_32', - 89: 'TC_OP_ATOMIC_DEC_32', - 90: 'TC_OP_INVL2_NC', - 91: 'TC_OP_NOP_RTN0', - 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', - 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', - 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', - 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', - 96: 'TC_OP_WBINVL2', - 97: 'TC_OP_ATOMIC_FCMPSWAP_64', - 98: 'TC_OP_ATOMIC_FMIN_64', - 99: 'TC_OP_ATOMIC_FMAX_64', - 100: 'TC_OP_RESERVED_FOP_64_0', - 101: 'TC_OP_RESERVED_FOP_64_1', - 102: 'TC_OP_RESERVED_FOP_64_2', - 103: 'TC_OP_ATOMIC_SWAP_64', - 104: 'TC_OP_ATOMIC_CMPSWAP_64', - 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 111: 'TC_OP_ATOMIC_ADD_64', - 112: 'TC_OP_ATOMIC_SUB_64', - 113: 'TC_OP_ATOMIC_SMIN_64', - 114: 'TC_OP_ATOMIC_UMIN_64', - 115: 'TC_OP_ATOMIC_SMAX_64', - 116: 'TC_OP_ATOMIC_UMAX_64', - 117: 'TC_OP_ATOMIC_AND_64', - 118: 'TC_OP_ATOMIC_OR_64', - 119: 'TC_OP_ATOMIC_XOR_64', - 120: 'TC_OP_ATOMIC_INC_64', - 121: 'TC_OP_ATOMIC_DEC_64', - 122: 'TC_OP_WBINVL2_NC', - 123: 'TC_OP_NOP_ACK', - 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', - 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', - 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', - 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', -} -TC_OP_READ = 0 -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -TC_OP_ATOMIC_FMIN_RTN_32 = 2 -TC_OP_ATOMIC_FMAX_RTN_32 = 3 -TC_OP_RESERVED_FOP_RTN_32_0 = 4 -TC_OP_RESERVED_FADD_RTN_32 = 5 -TC_OP_RESERVED_FOP_RTN_32_2 = 6 -TC_OP_ATOMIC_SWAP_RTN_32 = 7 -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -TC_OP_PROBE_FILTER = 12 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -TC_OP_ATOMIC_ADD_RTN_32 = 15 -TC_OP_ATOMIC_SUB_RTN_32 = 16 -TC_OP_ATOMIC_SMIN_RTN_32 = 17 -TC_OP_ATOMIC_UMIN_RTN_32 = 18 -TC_OP_ATOMIC_SMAX_RTN_32 = 19 -TC_OP_ATOMIC_UMAX_RTN_32 = 20 -TC_OP_ATOMIC_AND_RTN_32 = 21 -TC_OP_ATOMIC_OR_RTN_32 = 22 -TC_OP_ATOMIC_XOR_RTN_32 = 23 -TC_OP_ATOMIC_INC_RTN_32 = 24 -TC_OP_ATOMIC_DEC_RTN_32 = 25 -TC_OP_WBINVL1_VOL = 26 -TC_OP_WBINVL1_SD = 27 -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 -TC_OP_WRITE = 32 -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -TC_OP_ATOMIC_FMIN_RTN_64 = 34 -TC_OP_ATOMIC_FMAX_RTN_64 = 35 -TC_OP_RESERVED_FOP_RTN_64_0 = 36 -TC_OP_RESERVED_FOP_RTN_64_1 = 37 -TC_OP_RESERVED_FOP_RTN_64_2 = 38 -TC_OP_ATOMIC_SWAP_RTN_64 = 39 -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -TC_OP_WBINVL2_SD = 44 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 -TC_OP_ATOMIC_ADD_RTN_64 = 47 -TC_OP_ATOMIC_SUB_RTN_64 = 48 -TC_OP_ATOMIC_SMIN_RTN_64 = 49 -TC_OP_ATOMIC_UMIN_RTN_64 = 50 -TC_OP_ATOMIC_SMAX_RTN_64 = 51 -TC_OP_ATOMIC_UMAX_RTN_64 = 52 -TC_OP_ATOMIC_AND_RTN_64 = 53 -TC_OP_ATOMIC_OR_RTN_64 = 54 -TC_OP_ATOMIC_XOR_RTN_64 = 55 -TC_OP_ATOMIC_INC_RTN_64 = 56 -TC_OP_ATOMIC_DEC_RTN_64 = 57 -TC_OP_WBL2_NC = 58 -TC_OP_WBL2_WC = 59 -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 -TC_OP_WBINVL1 = 64 -TC_OP_ATOMIC_FCMPSWAP_32 = 65 -TC_OP_ATOMIC_FMIN_32 = 66 -TC_OP_ATOMIC_FMAX_32 = 67 -TC_OP_RESERVED_FOP_32_0 = 68 -TC_OP_RESERVED_FADD_32 = 69 -TC_OP_RESERVED_FOP_32_2 = 70 -TC_OP_ATOMIC_SWAP_32 = 71 -TC_OP_ATOMIC_CMPSWAP_32 = 72 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -TC_OP_INV_METADATA = 76 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 -TC_OP_ATOMIC_ADD_32 = 79 -TC_OP_ATOMIC_SUB_32 = 80 -TC_OP_ATOMIC_SMIN_32 = 81 -TC_OP_ATOMIC_UMIN_32 = 82 -TC_OP_ATOMIC_SMAX_32 = 83 -TC_OP_ATOMIC_UMAX_32 = 84 -TC_OP_ATOMIC_AND_32 = 85 -TC_OP_ATOMIC_OR_32 = 86 -TC_OP_ATOMIC_XOR_32 = 87 -TC_OP_ATOMIC_INC_32 = 88 -TC_OP_ATOMIC_DEC_32 = 89 -TC_OP_INVL2_NC = 90 -TC_OP_NOP_RTN0 = 91 -TC_OP_RESERVED_NON_FLOAT_32_1 = 92 -TC_OP_RESERVED_NON_FLOAT_32_2 = 93 -TC_OP_RESERVED_NON_FLOAT_32_3 = 94 -TC_OP_RESERVED_NON_FLOAT_32_4 = 95 -TC_OP_WBINVL2 = 96 -TC_OP_ATOMIC_FCMPSWAP_64 = 97 -TC_OP_ATOMIC_FMIN_64 = 98 -TC_OP_ATOMIC_FMAX_64 = 99 -TC_OP_RESERVED_FOP_64_0 = 100 -TC_OP_RESERVED_FOP_64_1 = 101 -TC_OP_RESERVED_FOP_64_2 = 102 -TC_OP_ATOMIC_SWAP_64 = 103 -TC_OP_ATOMIC_CMPSWAP_64 = 104 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 -TC_OP_ATOMIC_ADD_64 = 111 -TC_OP_ATOMIC_SUB_64 = 112 -TC_OP_ATOMIC_SMIN_64 = 113 -TC_OP_ATOMIC_UMIN_64 = 114 -TC_OP_ATOMIC_SMAX_64 = 115 -TC_OP_ATOMIC_UMAX_64 = 116 -TC_OP_ATOMIC_AND_64 = 117 -TC_OP_ATOMIC_OR_64 = 118 -TC_OP_ATOMIC_XOR_64 = 119 -TC_OP_ATOMIC_INC_64 = 120 -TC_OP_ATOMIC_DEC_64 = 121 -TC_OP_WBINVL2_NC = 122 -TC_OP_NOP_ACK = 123 -TC_OP_RESERVED_NON_FLOAT_64_1 = 124 -TC_OP_RESERVED_NON_FLOAT_64_2 = 125 -TC_OP_RESERVED_NON_FLOAT_64_3 = 126 -TC_OP_RESERVED_NON_FLOAT_64_4 = 127 -TC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP_MASKS' -TC_OP_MASKS__enumvalues = { - 8: 'TC_OP_MASK_FLUSH_DENROM', - 32: 'TC_OP_MASK_64', - 64: 'TC_OP_MASK_NO_RTN', -} -TC_OP_MASK_FLUSH_DENROM = 8 -TC_OP_MASK_64 = 32 -TC_OP_MASK_NO_RTN = 64 -TC_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_EA_CID' -GL2_EA_CID__enumvalues = { - 0: 'GL2_EA_CID_CLIENT', - 1: 'GL2_EA_CID_SDMA', - 2: 'GL2_EA_CID_RLC', - 3: 'GL2_EA_CID_SQC', - 4: 'GL2_EA_CID_CP', - 5: 'GL2_EA_CID_CPDMA', - 6: 'GL2_EA_CID_UTCL2', - 7: 'GL2_EA_CID_RT', - 8: 'GL2_EA_CID_FMASK', - 9: 'GL2_EA_CID_DCC', - 10: 'GL2_EA_CID_Z_STENCIL', - 11: 'GL2_EA_CID_ZPCPSD', - 12: 'GL2_EA_CID_HTILE', - 13: 'GL2_EA_CID_MES', - 15: 'GL2_EA_CID_TCPMETA', -} -GL2_EA_CID_CLIENT = 0 -GL2_EA_CID_SDMA = 1 -GL2_EA_CID_RLC = 2 -GL2_EA_CID_SQC = 3 -GL2_EA_CID_CP = 4 -GL2_EA_CID_CPDMA = 5 -GL2_EA_CID_UTCL2 = 6 -GL2_EA_CID_RT = 7 -GL2_EA_CID_FMASK = 8 -GL2_EA_CID_DCC = 9 -GL2_EA_CID_Z_STENCIL = 10 -GL2_EA_CID_ZPCPSD = 11 -GL2_EA_CID_HTILE = 12 -GL2_EA_CID_MES = 13 -GL2_EA_CID_TCPMETA = 15 -GL2_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_NACKS' -GL2_NACKS__enumvalues = { - 0: 'GL2_NACK_NO_FAULT', - 1: 'GL2_NACK_PAGE_FAULT', - 2: 'GL2_NACK_PROTECTION_FAULT', - 3: 'GL2_NACK_DATA_ERROR', -} -GL2_NACK_NO_FAULT = 0 -GL2_NACK_PAGE_FAULT = 1 -GL2_NACK_PROTECTION_FAULT = 2 -GL2_NACK_DATA_ERROR = 3 -GL2_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP' -GL2_OP__enumvalues = { - 0: 'GL2_OP_READ', - 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', - 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', - 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', - 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'GL2_OP_PROBE_FILTER', - 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'GL2_OP_ATOMIC_ADD_RTN_32', - 16: 'GL2_OP_ATOMIC_SUB_RTN_32', - 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', - 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', - 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', - 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', - 21: 'GL2_OP_ATOMIC_AND_RTN_32', - 22: 'GL2_OP_ATOMIC_OR_RTN_32', - 23: 'GL2_OP_ATOMIC_XOR_RTN_32', - 24: 'GL2_OP_ATOMIC_INC_RTN_32', - 25: 'GL2_OP_ATOMIC_DEC_RTN_32', - 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 32: 'GL2_OP_WRITE', - 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', - 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', - 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', - 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 47: 'GL2_OP_ATOMIC_ADD_RTN_64', - 48: 'GL2_OP_ATOMIC_SUB_RTN_64', - 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', - 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', - 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', - 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', - 53: 'GL2_OP_ATOMIC_AND_RTN_64', - 54: 'GL2_OP_ATOMIC_OR_RTN_64', - 55: 'GL2_OP_ATOMIC_XOR_RTN_64', - 56: 'GL2_OP_ATOMIC_INC_RTN_64', - 57: 'GL2_OP_ATOMIC_DEC_RTN_64', - 64: 'GL2_OP_GL1_INV', - 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', - 66: 'GL2_OP_ATOMIC_FMIN_32', - 67: 'GL2_OP_ATOMIC_FMAX_32', - 71: 'GL2_OP_ATOMIC_SWAP_32', - 72: 'GL2_OP_ATOMIC_CMPSWAP_32', - 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'GL2_OP_ATOMIC_UMIN_8', - 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 79: 'GL2_OP_ATOMIC_ADD_32', - 80: 'GL2_OP_ATOMIC_SUB_32', - 81: 'GL2_OP_ATOMIC_SMIN_32', - 82: 'GL2_OP_ATOMIC_UMIN_32', - 83: 'GL2_OP_ATOMIC_SMAX_32', - 84: 'GL2_OP_ATOMIC_UMAX_32', - 85: 'GL2_OP_ATOMIC_AND_32', - 86: 'GL2_OP_ATOMIC_OR_32', - 87: 'GL2_OP_ATOMIC_XOR_32', - 88: 'GL2_OP_ATOMIC_INC_32', - 89: 'GL2_OP_ATOMIC_DEC_32', - 91: 'GL2_OP_NOP_RTN0', - 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', - 98: 'GL2_OP_ATOMIC_FMIN_64', - 99: 'GL2_OP_ATOMIC_FMAX_64', - 103: 'GL2_OP_ATOMIC_SWAP_64', - 104: 'GL2_OP_ATOMIC_CMPSWAP_64', - 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 111: 'GL2_OP_ATOMIC_ADD_64', - 112: 'GL2_OP_ATOMIC_SUB_64', - 113: 'GL2_OP_ATOMIC_SMIN_64', - 114: 'GL2_OP_ATOMIC_UMIN_64', - 115: 'GL2_OP_ATOMIC_SMAX_64', - 116: 'GL2_OP_ATOMIC_UMAX_64', - 117: 'GL2_OP_ATOMIC_AND_64', - 118: 'GL2_OP_ATOMIC_OR_64', - 119: 'GL2_OP_ATOMIC_XOR_64', - 120: 'GL2_OP_ATOMIC_INC_64', - 121: 'GL2_OP_ATOMIC_DEC_64', - 122: 'GL2_OP_ATOMIC_UMAX_8', - 123: 'GL2_OP_NOP_ACK', -} -GL2_OP_READ = 0 -GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -GL2_OP_ATOMIC_FMIN_RTN_32 = 2 -GL2_OP_ATOMIC_FMAX_RTN_32 = 3 -GL2_OP_ATOMIC_SWAP_RTN_32 = 7 -GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -GL2_OP_PROBE_FILTER = 12 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -GL2_OP_ATOMIC_ADD_RTN_32 = 15 -GL2_OP_ATOMIC_SUB_RTN_32 = 16 -GL2_OP_ATOMIC_SMIN_RTN_32 = 17 -GL2_OP_ATOMIC_UMIN_RTN_32 = 18 -GL2_OP_ATOMIC_SMAX_RTN_32 = 19 -GL2_OP_ATOMIC_UMAX_RTN_32 = 20 -GL2_OP_ATOMIC_AND_RTN_32 = 21 -GL2_OP_ATOMIC_OR_RTN_32 = 22 -GL2_OP_ATOMIC_XOR_RTN_32 = 23 -GL2_OP_ATOMIC_INC_RTN_32 = 24 -GL2_OP_ATOMIC_DEC_RTN_32 = 25 -GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 -GL2_OP_WRITE = 32 -GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -GL2_OP_ATOMIC_FMIN_RTN_64 = 34 -GL2_OP_ATOMIC_FMAX_RTN_64 = 35 -GL2_OP_ATOMIC_SWAP_RTN_64 = 39 -GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -GL2_OP_ATOMIC_ADD_RTN_64 = 47 -GL2_OP_ATOMIC_SUB_RTN_64 = 48 -GL2_OP_ATOMIC_SMIN_RTN_64 = 49 -GL2_OP_ATOMIC_UMIN_RTN_64 = 50 -GL2_OP_ATOMIC_SMAX_RTN_64 = 51 -GL2_OP_ATOMIC_UMAX_RTN_64 = 52 -GL2_OP_ATOMIC_AND_RTN_64 = 53 -GL2_OP_ATOMIC_OR_RTN_64 = 54 -GL2_OP_ATOMIC_XOR_RTN_64 = 55 -GL2_OP_ATOMIC_INC_RTN_64 = 56 -GL2_OP_ATOMIC_DEC_RTN_64 = 57 -GL2_OP_GL1_INV = 64 -GL2_OP_ATOMIC_FCMPSWAP_32 = 65 -GL2_OP_ATOMIC_FMIN_32 = 66 -GL2_OP_ATOMIC_FMAX_32 = 67 -GL2_OP_ATOMIC_SWAP_32 = 71 -GL2_OP_ATOMIC_CMPSWAP_32 = 72 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -GL2_OP_ATOMIC_UMIN_8 = 76 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -GL2_OP_ATOMIC_ADD_32 = 79 -GL2_OP_ATOMIC_SUB_32 = 80 -GL2_OP_ATOMIC_SMIN_32 = 81 -GL2_OP_ATOMIC_UMIN_32 = 82 -GL2_OP_ATOMIC_SMAX_32 = 83 -GL2_OP_ATOMIC_UMAX_32 = 84 -GL2_OP_ATOMIC_AND_32 = 85 -GL2_OP_ATOMIC_OR_32 = 86 -GL2_OP_ATOMIC_XOR_32 = 87 -GL2_OP_ATOMIC_INC_32 = 88 -GL2_OP_ATOMIC_DEC_32 = 89 -GL2_OP_NOP_RTN0 = 91 -GL2_OP_ATOMIC_FCMPSWAP_64 = 97 -GL2_OP_ATOMIC_FMIN_64 = 98 -GL2_OP_ATOMIC_FMAX_64 = 99 -GL2_OP_ATOMIC_SWAP_64 = 103 -GL2_OP_ATOMIC_CMPSWAP_64 = 104 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -GL2_OP_ATOMIC_ADD_64 = 111 -GL2_OP_ATOMIC_SUB_64 = 112 -GL2_OP_ATOMIC_SMIN_64 = 113 -GL2_OP_ATOMIC_UMIN_64 = 114 -GL2_OP_ATOMIC_SMAX_64 = 115 -GL2_OP_ATOMIC_UMAX_64 = 116 -GL2_OP_ATOMIC_AND_64 = 117 -GL2_OP_ATOMIC_OR_64 = 118 -GL2_OP_ATOMIC_XOR_64 = 119 -GL2_OP_ATOMIC_INC_64 = 120 -GL2_OP_ATOMIC_DEC_64 = 121 -GL2_OP_ATOMIC_UMAX_8 = 122 -GL2_OP_NOP_ACK = 123 -GL2_OP = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP_MASKS' -GL2_OP_MASKS__enumvalues = { - 8: 'GL2_OP_MASK_FLUSH_DENROM', - 32: 'GL2_OP_MASK_64', - 64: 'GL2_OP_MASK_NO_RTN', -} -GL2_OP_MASK_FLUSH_DENROM = 8 -GL2_OP_MASK_64 = 32 -GL2_OP_MASK_NO_RTN = 64 -GL2_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_DOORBELL_MODE' -RLC_DOORBELL_MODE__enumvalues = { - 0: 'RLC_DOORBELL_MODE_DISABLE', - 1: 'RLC_DOORBELL_MODE_ENABLE', - 2: 'RLC_DOORBELL_MODE_ENABLE_PF', - 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', -} -RLC_DOORBELL_MODE_DISABLE = 0 -RLC_DOORBELL_MODE_ENABLE = 1 -RLC_DOORBELL_MODE_ENABLE_PF = 2 -RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 -RLC_DOORBELL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFCOUNTER_SEL' -RLC_PERFCOUNTER_SEL__enumvalues = { - 0: 'RLC_PERF_SEL_POWER_FEATURE_0', - 1: 'RLC_PERF_SEL_POWER_FEATURE_1', - 2: 'RLC_PERF_SEL_CP_INTERRUPT', - 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', - 4: 'RLC_PERF_SEL_SPM_INTERRUPT', - 5: 'RLC_PERF_SEL_IH_INTERRUPT', - 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', -} -RLC_PERF_SEL_POWER_FEATURE_0 = 0 -RLC_PERF_SEL_POWER_FEATURE_1 = 1 -RLC_PERF_SEL_CP_INTERRUPT = 2 -RLC_PERF_SEL_GRBM_INTERRUPT = 3 -RLC_PERF_SEL_SPM_INTERRUPT = 4 -RLC_PERF_SEL_IH_INTERRUPT = 5 -RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 -RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFMON_STATE' -RLC_PERFMON_STATE__enumvalues = { - 0: 'RLC_PERFMON_STATE_RESET', - 1: 'RLC_PERFMON_STATE_ENABLE', - 2: 'RLC_PERFMON_STATE_DISABLE', - 3: 'RLC_PERFMON_STATE_RESERVED_3', - 4: 'RLC_PERFMON_STATE_RESERVED_4', - 5: 'RLC_PERFMON_STATE_RESERVED_5', - 6: 'RLC_PERFMON_STATE_RESERVED_6', - 7: 'RLC_PERFMON_STATE_ROLLOVER', -} -RLC_PERFMON_STATE_RESET = 0 -RLC_PERFMON_STATE_ENABLE = 1 -RLC_PERFMON_STATE_DISABLE = 2 -RLC_PERFMON_STATE_RESERVED_3 = 3 -RLC_PERFMON_STATE_RESERVED_4 = 4 -RLC_PERFMON_STATE_RESERVED_5 = 5 -RLC_PERFMON_STATE_RESERVED_6 = 6 -RLC_PERFMON_STATE_ROLLOVER = 7 -RLC_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RSPM_CMD' -RSPM_CMD__enumvalues = { - 0: 'RSPM_CMD_INVALID', - 1: 'RSPM_CMD_IDLE', - 2: 'RSPM_CMD_CALIBRATE', - 3: 'RSPM_CMD_SPM_RESET', - 4: 'RSPM_CMD_SPM_START', - 5: 'RSPM_CMD_SPM_STOP', - 6: 'RSPM_CMD_PERF_RESET', - 7: 'RSPM_CMD_PERF_SAMPLE', - 8: 'RSPM_CMD_PROF_START', - 9: 'RSPM_CMD_PROF_STOP', - 10: 'RSPM_CMD_FORCE_SAMPLE', -} -RSPM_CMD_INVALID = 0 -RSPM_CMD_IDLE = 1 -RSPM_CMD_CALIBRATE = 2 -RSPM_CMD_SPM_RESET = 3 -RSPM_CMD_SPM_START = 4 -RSPM_CMD_SPM_STOP = 5 -RSPM_CMD_PERF_RESET = 6 -RSPM_CMD_PERF_SAMPLE = 7 -RSPM_CMD_PROF_START = 8 -RSPM_CMD_PROF_STOP = 9 -RSPM_CMD_FORCE_SAMPLE = 10 -RSPM_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_BASE_MODE' -CLKGATE_BASE_MODE__enumvalues = { - 0: 'MULT_8', - 1: 'MULT_16', -} -MULT_8 = 0 -MULT_16 = 1 -CLKGATE_BASE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_SM_MODE' -CLKGATE_SM_MODE__enumvalues = { - 0: 'ON_SEQ', - 1: 'OFF_SEQ', - 2: 'PROG_SEQ', - 3: 'READ_SEQ', - 4: 'SM_MODE_RESERVED', -} -ON_SEQ = 0 -OFF_SEQ = 1 -PROG_SEQ = 2 -READ_SEQ = 3 -SM_MODE_RESERVED = 4 -CLKGATE_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_FOG_MODE' -SPI_FOG_MODE__enumvalues = { - 0: 'SPI_FOG_NONE', - 1: 'SPI_FOG_EXP', - 2: 'SPI_FOG_EXP2', - 3: 'SPI_FOG_LINEAR', -} -SPI_FOG_NONE = 0 -SPI_FOG_EXP = 1 -SPI_FOG_EXP2 = 2 -SPI_FOG_LINEAR = 3 -SPI_FOG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_LB_WAVES_SELECT' -SPI_LB_WAVES_SELECT__enumvalues = { - 0: 'HS_GS', - 1: 'PS', - 2: 'CS_NA', - 3: 'SPI_LB_WAVES_RSVD', -} -HS_GS = 0 -PS = 1 -CS_NA = 2 -SPI_LB_WAVES_RSVD = 3 -SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PERFCNT_SEL' -SPI_PERFCNT_SEL__enumvalues = { - 1: 'SPI_PERF_GS_WINDOW_VALID', - 2: 'SPI_PERF_GS_BUSY', - 3: 'SPI_PERF_GS_CRAWLER_STALL', - 4: 'SPI_PERF_GS_EVENT_WAVE', - 5: 'SPI_PERF_GS_WAVE', - 6: 'SPI_PERF_GS_PERS_UPD_FULL0', - 7: 'SPI_PERF_GS_PERS_UPD_FULL1', - 8: 'SPI_PERF_GS_FIRST_SUBGRP', - 9: 'SPI_PERF_GS_HS_DEALLOC', - 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 11: 'SPI_PERF_GS_POS0_STALL', - 12: 'SPI_PERF_GS_POS1_STALL', - 13: 'SPI_PERF_GS_INDX0_STALL', - 14: 'SPI_PERF_GS_INDX1_STALL', - 15: 'SPI_PERF_GS_PWS_STALL', - 21: 'SPI_PERF_HS_WINDOW_VALID', - 22: 'SPI_PERF_HS_BUSY', - 23: 'SPI_PERF_HS_CRAWLER_STALL', - 24: 'SPI_PERF_HS_FIRST_WAVE', - 25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', - 26: 'SPI_PERF_HS_EVENT_WAVE', - 27: 'SPI_PERF_HS_WAVE', - 28: 'SPI_PERF_HS_PERS_UPD_FULL0', - 29: 'SPI_PERF_HS_PERS_UPD_FULL1', - 30: 'SPI_PERF_HS_PWS_STALL', - 37: 'SPI_PERF_CSGN_WINDOW_VALID', - 38: 'SPI_PERF_CSGN_BUSY', - 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', - 40: 'SPI_PERF_CSGN_CRAWLER_STALL', - 41: 'SPI_PERF_CSGN_EVENT_WAVE', - 42: 'SPI_PERF_CSGN_WAVE', - 43: 'SPI_PERF_CSGN_PWS_STALL', - 44: 'SPI_PERF_CSN_WINDOW_VALID', - 45: 'SPI_PERF_CSN_BUSY', - 46: 'SPI_PERF_CSN_NUM_THREADGROUPS', - 47: 'SPI_PERF_CSN_CRAWLER_STALL', - 48: 'SPI_PERF_CSN_EVENT_WAVE', - 49: 'SPI_PERF_CSN_WAVE', - 53: 'SPI_PERF_PS0_WINDOW_VALID', - 54: 'SPI_PERF_PS1_WINDOW_VALID', - 55: 'SPI_PERF_PS2_WINDOW_VALID', - 56: 'SPI_PERF_PS3_WINDOW_VALID', - 57: 'SPI_PERF_PS0_BUSY', - 58: 'SPI_PERF_PS1_BUSY', - 59: 'SPI_PERF_PS2_BUSY', - 60: 'SPI_PERF_PS3_BUSY', - 61: 'SPI_PERF_PS0_ACTIVE', - 62: 'SPI_PERF_PS1_ACTIVE', - 63: 'SPI_PERF_PS2_ACTIVE', - 64: 'SPI_PERF_PS3_ACTIVE', - 65: 'SPI_PERF_PS0_DEALLOC', - 66: 'SPI_PERF_PS1_DEALLOC', - 67: 'SPI_PERF_PS2_DEALLOC', - 68: 'SPI_PERF_PS3_DEALLOC', - 69: 'SPI_PERF_PS0_EVENT_WAVE', - 70: 'SPI_PERF_PS1_EVENT_WAVE', - 71: 'SPI_PERF_PS2_EVENT_WAVE', - 72: 'SPI_PERF_PS3_EVENT_WAVE', - 73: 'SPI_PERF_PS0_WAVE', - 74: 'SPI_PERF_PS1_WAVE', - 75: 'SPI_PERF_PS2_WAVE', - 76: 'SPI_PERF_PS3_WAVE', - 77: 'SPI_PERF_PS0_OPT_WAVE', - 78: 'SPI_PERF_PS1_OPT_WAVE', - 79: 'SPI_PERF_PS2_OPT_WAVE', - 80: 'SPI_PERF_PS3_OPT_WAVE', - 81: 'SPI_PERF_PS0_PRIM_BIN0', - 82: 'SPI_PERF_PS1_PRIM_BIN0', - 83: 'SPI_PERF_PS2_PRIM_BIN0', - 84: 'SPI_PERF_PS3_PRIM_BIN0', - 85: 'SPI_PERF_PS0_PRIM_BIN1', - 86: 'SPI_PERF_PS1_PRIM_BIN1', - 87: 'SPI_PERF_PS2_PRIM_BIN1', - 88: 'SPI_PERF_PS3_PRIM_BIN1', - 89: 'SPI_PERF_PS0_CRAWLER_STALL', - 90: 'SPI_PERF_PS1_CRAWLER_STALL', - 91: 'SPI_PERF_PS2_CRAWLER_STALL', - 92: 'SPI_PERF_PS3_CRAWLER_STALL', - 93: 'SPI_PERF_PS_PERS_UPD_FULL0', - 94: 'SPI_PERF_PS_PERS_UPD_FULL1', - 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', - 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', - 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', - 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', - 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', - 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', - 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', - 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', - 107: 'SPI_PERF_PS_PWS_STALL', - 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', - 142: 'SPI_PERF_RA_TASK_REQ_BIN3', - 143: 'SPI_PERF_RA_WR_CTL_FULL', - 144: 'SPI_PERF_RA_REQ_NO_ALLOC', - 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 150: 'SPI_PERF_RA_RES_STALL_PS', - 151: 'SPI_PERF_RA_RES_STALL_GS', - 152: 'SPI_PERF_RA_RES_STALL_HS', - 153: 'SPI_PERF_RA_RES_STALL_CSG', - 154: 'SPI_PERF_RA_RES_STALL_CSN', - 155: 'SPI_PERF_RA_TMP_STALL_PS', - 156: 'SPI_PERF_RA_TMP_STALL_GS', - 157: 'SPI_PERF_RA_TMP_STALL_HS', - 158: 'SPI_PERF_RA_TMP_STALL_CSG', - 159: 'SPI_PERF_RA_TMP_STALL_CSN', - 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', - 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', - 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', - 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', - 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', - 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', - 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 175: 'SPI_PERF_RA_BAR_CU_FULL_HS', - 176: 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 177: 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', - 181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 182: 'SPI_PERF_RA_WVLIM_STALL_PS', - 183: 'SPI_PERF_RA_WVLIM_STALL_GS', - 184: 'SPI_PERF_RA_WVLIM_STALL_HS', - 185: 'SPI_PERF_RA_WVLIM_STALL_CSG', - 186: 'SPI_PERF_RA_WVLIM_STALL_CSN', - 187: 'SPI_PERF_RA_GS_LOCK', - 188: 'SPI_PERF_RA_HS_LOCK', - 189: 'SPI_PERF_RA_CSG_LOCK', - 190: 'SPI_PERF_RA_CSN_LOCK', - 191: 'SPI_PERF_RA_RSV_UPD', - 192: 'SPI_PERF_RA_PRE_ALLOC_STALL', - 193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', - 195: 'SPI_PERF_RA_WVALLOC_STALL', - 196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', - 200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 216: 'SPI_PERF_EXP_ARB_COL_CNT', - 217: 'SPI_PERF_EXP_ARB_POS_CNT', - 218: 'SPI_PERF_EXP_ARB_GDS_CNT', - 219: 'SPI_PERF_EXP_ARB_IDX_CNT', - 220: 'SPI_PERF_EXP_WITH_CONFLICT', - 221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 222: 'SPI_PERF_GS_EXP_DONE', - 223: 'SPI_PERF_PS_EXP_DONE', - 224: 'SPI_PERF_PS_EXP_ARB_CONFLICT', - 225: 'SPI_PERF_PS_EXP_ALLOC', - 226: 'SPI_PERF_PS0_WAVEID_STARVED', - 227: 'SPI_PERF_PS1_WAVEID_STARVED', - 228: 'SPI_PERF_PS2_WAVEID_STARVED', - 229: 'SPI_PERF_PS3_WAVEID_STARVED', - 230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', - 232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', - 233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', - 234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 254: 'SPI_PERF_EXPORT_SCB0_STALL', - 255: 'SPI_PERF_EXPORT_SCB1_STALL', - 256: 'SPI_PERF_EXPORT_SCB2_STALL', - 257: 'SPI_PERF_EXPORT_SCB3_STALL', - 258: 'SPI_PERF_EXPORT_DB0_STALL', - 259: 'SPI_PERF_EXPORT_DB1_STALL', - 260: 'SPI_PERF_EXPORT_DB2_STALL', - 261: 'SPI_PERF_EXPORT_DB3_STALL', - 262: 'SPI_PERF_EXPORT_DB4_STALL', - 263: 'SPI_PERF_EXPORT_DB5_STALL', - 264: 'SPI_PERF_EXPORT_DB6_STALL', - 265: 'SPI_PERF_EXPORT_DB7_STALL', - 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', - 268: 'SPI_PERF_SWC_PS_WR', - 269: 'SPI_PERF_SWC_GS_WR', - 270: 'SPI_PERF_SWC_HS_WR', - 271: 'SPI_PERF_SWC_CSGN_WR', - 272: 'SPI_PERF_SWC_CSN_WR', - 273: 'SPI_PERF_VWC_PS_WR', - 274: 'SPI_PERF_VWC_ES_WR', - 275: 'SPI_PERF_VWC_GS_WR', - 276: 'SPI_PERF_VWC_LS_WR', - 277: 'SPI_PERF_VWC_HS_WR', - 278: 'SPI_PERF_VWC_CSGN_WR', - 279: 'SPI_PERF_VWC_CSN_WR', - 280: 'SPI_PERF_EXP_THROT_UPSTEP', - 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', - 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 283: 'SPI_PERF_BUSY', -} -SPI_PERF_GS_WINDOW_VALID = 1 -SPI_PERF_GS_BUSY = 2 -SPI_PERF_GS_CRAWLER_STALL = 3 -SPI_PERF_GS_EVENT_WAVE = 4 -SPI_PERF_GS_WAVE = 5 -SPI_PERF_GS_PERS_UPD_FULL0 = 6 -SPI_PERF_GS_PERS_UPD_FULL1 = 7 -SPI_PERF_GS_FIRST_SUBGRP = 8 -SPI_PERF_GS_HS_DEALLOC = 9 -SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 -SPI_PERF_GS_POS0_STALL = 11 -SPI_PERF_GS_POS1_STALL = 12 -SPI_PERF_GS_INDX0_STALL = 13 -SPI_PERF_GS_INDX1_STALL = 14 -SPI_PERF_GS_PWS_STALL = 15 -SPI_PERF_HS_WINDOW_VALID = 21 -SPI_PERF_HS_BUSY = 22 -SPI_PERF_HS_CRAWLER_STALL = 23 -SPI_PERF_HS_FIRST_WAVE = 24 -SPI_PERF_HS_OFFCHIP_LDS_STALL = 25 -SPI_PERF_HS_EVENT_WAVE = 26 -SPI_PERF_HS_WAVE = 27 -SPI_PERF_HS_PERS_UPD_FULL0 = 28 -SPI_PERF_HS_PERS_UPD_FULL1 = 29 -SPI_PERF_HS_PWS_STALL = 30 -SPI_PERF_CSGN_WINDOW_VALID = 37 -SPI_PERF_CSGN_BUSY = 38 -SPI_PERF_CSGN_NUM_THREADGROUPS = 39 -SPI_PERF_CSGN_CRAWLER_STALL = 40 -SPI_PERF_CSGN_EVENT_WAVE = 41 -SPI_PERF_CSGN_WAVE = 42 -SPI_PERF_CSGN_PWS_STALL = 43 -SPI_PERF_CSN_WINDOW_VALID = 44 -SPI_PERF_CSN_BUSY = 45 -SPI_PERF_CSN_NUM_THREADGROUPS = 46 -SPI_PERF_CSN_CRAWLER_STALL = 47 -SPI_PERF_CSN_EVENT_WAVE = 48 -SPI_PERF_CSN_WAVE = 49 -SPI_PERF_PS0_WINDOW_VALID = 53 -SPI_PERF_PS1_WINDOW_VALID = 54 -SPI_PERF_PS2_WINDOW_VALID = 55 -SPI_PERF_PS3_WINDOW_VALID = 56 -SPI_PERF_PS0_BUSY = 57 -SPI_PERF_PS1_BUSY = 58 -SPI_PERF_PS2_BUSY = 59 -SPI_PERF_PS3_BUSY = 60 -SPI_PERF_PS0_ACTIVE = 61 -SPI_PERF_PS1_ACTIVE = 62 -SPI_PERF_PS2_ACTIVE = 63 -SPI_PERF_PS3_ACTIVE = 64 -SPI_PERF_PS0_DEALLOC = 65 -SPI_PERF_PS1_DEALLOC = 66 -SPI_PERF_PS2_DEALLOC = 67 -SPI_PERF_PS3_DEALLOC = 68 -SPI_PERF_PS0_EVENT_WAVE = 69 -SPI_PERF_PS1_EVENT_WAVE = 70 -SPI_PERF_PS2_EVENT_WAVE = 71 -SPI_PERF_PS3_EVENT_WAVE = 72 -SPI_PERF_PS0_WAVE = 73 -SPI_PERF_PS1_WAVE = 74 -SPI_PERF_PS2_WAVE = 75 -SPI_PERF_PS3_WAVE = 76 -SPI_PERF_PS0_OPT_WAVE = 77 -SPI_PERF_PS1_OPT_WAVE = 78 -SPI_PERF_PS2_OPT_WAVE = 79 -SPI_PERF_PS3_OPT_WAVE = 80 -SPI_PERF_PS0_PRIM_BIN0 = 81 -SPI_PERF_PS1_PRIM_BIN0 = 82 -SPI_PERF_PS2_PRIM_BIN0 = 83 -SPI_PERF_PS3_PRIM_BIN0 = 84 -SPI_PERF_PS0_PRIM_BIN1 = 85 -SPI_PERF_PS1_PRIM_BIN1 = 86 -SPI_PERF_PS2_PRIM_BIN1 = 87 -SPI_PERF_PS3_PRIM_BIN1 = 88 -SPI_PERF_PS0_CRAWLER_STALL = 89 -SPI_PERF_PS1_CRAWLER_STALL = 90 -SPI_PERF_PS2_CRAWLER_STALL = 91 -SPI_PERF_PS3_CRAWLER_STALL = 92 -SPI_PERF_PS_PERS_UPD_FULL0 = 93 -SPI_PERF_PS_PERS_UPD_FULL1 = 94 -SPI_PERF_PS0_2_WAVE_GROUPS = 95 -SPI_PERF_PS1_2_WAVE_GROUPS = 96 -SPI_PERF_PS2_2_WAVE_GROUPS = 97 -SPI_PERF_PS3_2_WAVE_GROUPS = 98 -SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 -SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 -SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 -SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 -SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 -SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 -SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 -SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 -SPI_PERF_PS_PWS_STALL = 107 -SPI_PERF_RA_PIPE_REQ_BIN2 = 141 -SPI_PERF_RA_TASK_REQ_BIN3 = 142 -SPI_PERF_RA_WR_CTL_FULL = 143 -SPI_PERF_RA_REQ_NO_ALLOC = 144 -SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 -SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 -SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 -SPI_PERF_RA_RES_STALL_PS = 150 -SPI_PERF_RA_RES_STALL_GS = 151 -SPI_PERF_RA_RES_STALL_HS = 152 -SPI_PERF_RA_RES_STALL_CSG = 153 -SPI_PERF_RA_RES_STALL_CSN = 154 -SPI_PERF_RA_TMP_STALL_PS = 155 -SPI_PERF_RA_TMP_STALL_GS = 156 -SPI_PERF_RA_TMP_STALL_HS = 157 -SPI_PERF_RA_TMP_STALL_CSG = 158 -SPI_PERF_RA_TMP_STALL_CSN = 159 -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 -SPI_PERF_RA_LDS_CU_FULL_PS = 170 -SPI_PERF_RA_LDS_CU_FULL_HS = 171 -SPI_PERF_RA_LDS_CU_FULL_GS = 172 -SPI_PERF_RA_LDS_CU_FULL_CSG = 173 -SPI_PERF_RA_LDS_CU_FULL_CSN = 174 -SPI_PERF_RA_BAR_CU_FULL_HS = 175 -SPI_PERF_RA_BAR_CU_FULL_CSG = 176 -SPI_PERF_RA_BAR_CU_FULL_CSN = 177 -SPI_PERF_RA_BULKY_CU_FULL_CSG = 178 -SPI_PERF_RA_BULKY_CU_FULL_CSN = 179 -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180 -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181 -SPI_PERF_RA_WVLIM_STALL_PS = 182 -SPI_PERF_RA_WVLIM_STALL_GS = 183 -SPI_PERF_RA_WVLIM_STALL_HS = 184 -SPI_PERF_RA_WVLIM_STALL_CSG = 185 -SPI_PERF_RA_WVLIM_STALL_CSN = 186 -SPI_PERF_RA_GS_LOCK = 187 -SPI_PERF_RA_HS_LOCK = 188 -SPI_PERF_RA_CSG_LOCK = 189 -SPI_PERF_RA_CSN_LOCK = 190 -SPI_PERF_RA_RSV_UPD = 191 -SPI_PERF_RA_PRE_ALLOC_STALL = 192 -SPI_PERF_RA_GFX_UNDER_TUNNEL = 193 -SPI_PERF_RA_CSC_UNDER_TUNNEL = 194 -SPI_PERF_RA_WVALLOC_STALL = 195 -SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196 -SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197 -SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198 -SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199 -SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200 -SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201 -SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202 -SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203 -SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204 -SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205 -SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206 -SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215 -SPI_PERF_EXP_ARB_COL_CNT = 216 -SPI_PERF_EXP_ARB_POS_CNT = 217 -SPI_PERF_EXP_ARB_GDS_CNT = 218 -SPI_PERF_EXP_ARB_IDX_CNT = 219 -SPI_PERF_EXP_WITH_CONFLICT = 220 -SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221 -SPI_PERF_GS_EXP_DONE = 222 -SPI_PERF_PS_EXP_DONE = 223 -SPI_PERF_PS_EXP_ARB_CONFLICT = 224 -SPI_PERF_PS_EXP_ALLOC = 225 -SPI_PERF_PS0_WAVEID_STARVED = 226 -SPI_PERF_PS1_WAVEID_STARVED = 227 -SPI_PERF_PS2_WAVEID_STARVED = 228 -SPI_PERF_PS3_WAVEID_STARVED = 229 -SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230 -SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231 -SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232 -SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233 -SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234 -SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235 -SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236 -SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237 -SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238 -SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239 -SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240 -SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241 -SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242 -SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243 -SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244 -SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245 -SPI_PERF_NUM_EXPGRANT_EXPORTS = 246 -SPI_PERF_PIX_ALLOC_PEND_CNT = 253 -SPI_PERF_EXPORT_SCB0_STALL = 254 -SPI_PERF_EXPORT_SCB1_STALL = 255 -SPI_PERF_EXPORT_SCB2_STALL = 256 -SPI_PERF_EXPORT_SCB3_STALL = 257 -SPI_PERF_EXPORT_DB0_STALL = 258 -SPI_PERF_EXPORT_DB1_STALL = 259 -SPI_PERF_EXPORT_DB2_STALL = 260 -SPI_PERF_EXPORT_DB3_STALL = 261 -SPI_PERF_EXPORT_DB4_STALL = 262 -SPI_PERF_EXPORT_DB5_STALL = 263 -SPI_PERF_EXPORT_DB6_STALL = 264 -SPI_PERF_EXPORT_DB7_STALL = 265 -SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 -SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 -SPI_PERF_SWC_PS_WR = 268 -SPI_PERF_SWC_GS_WR = 269 -SPI_PERF_SWC_HS_WR = 270 -SPI_PERF_SWC_CSGN_WR = 271 -SPI_PERF_SWC_CSN_WR = 272 -SPI_PERF_VWC_PS_WR = 273 -SPI_PERF_VWC_ES_WR = 274 -SPI_PERF_VWC_GS_WR = 275 -SPI_PERF_VWC_LS_WR = 276 -SPI_PERF_VWC_HS_WR = 277 -SPI_PERF_VWC_CSGN_WR = 278 -SPI_PERF_VWC_CSN_WR = 279 -SPI_PERF_EXP_THROT_UPSTEP = 280 -SPI_PERF_EXP_THROT_DOWNSTEP = 281 -SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 -SPI_PERF_BUSY = 283 -SPI_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' -SPI_PNT_SPRITE_OVERRIDE__enumvalues = { - 0: 'SPI_PNT_SPRITE_SEL_0', - 1: 'SPI_PNT_SPRITE_SEL_1', - 2: 'SPI_PNT_SPRITE_SEL_S', - 3: 'SPI_PNT_SPRITE_SEL_T', - 4: 'SPI_PNT_SPRITE_SEL_NONE', -} -SPI_PNT_SPRITE_SEL_0 = 0 -SPI_PNT_SPRITE_SEL_1 = 1 -SPI_PNT_SPRITE_SEL_S = 2 -SPI_PNT_SPRITE_SEL_T = 3 -SPI_PNT_SPRITE_SEL_NONE = 4 -SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' -SPI_PS_LDS_GROUP_SIZE__enumvalues = { - 0: 'SPI_PS_LDS_GROUP_1', - 1: 'SPI_PS_LDS_GROUP_2', - 2: 'SPI_PS_LDS_GROUP_4', -} -SPI_PS_LDS_GROUP_1 = 0 -SPI_PS_LDS_GROUP_2 = 1 -SPI_PS_LDS_GROUP_4 = 2 -SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SAMPLE_CNTL' -SPI_SAMPLE_CNTL__enumvalues = { - 0: 'CENTROIDS_ONLY', - 1: 'CENTERS_ONLY', - 2: 'CENTROIDS_AND_CENTERS', - 3: 'UNDEF', -} -CENTROIDS_ONLY = 0 -CENTERS_ONLY = 1 -CENTROIDS_AND_CENTERS = 2 -UNDEF = 3 -SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_EX_FORMAT' -SPI_SHADER_EX_FORMAT__enumvalues = { - 0: 'SPI_SHADER_ZERO', - 1: 'SPI_SHADER_32_R', - 2: 'SPI_SHADER_32_GR', - 3: 'SPI_SHADER_32_AR', - 4: 'SPI_SHADER_FP16_ABGR', - 5: 'SPI_SHADER_UNORM16_ABGR', - 6: 'SPI_SHADER_SNORM16_ABGR', - 7: 'SPI_SHADER_UINT16_ABGR', - 8: 'SPI_SHADER_SINT16_ABGR', - 9: 'SPI_SHADER_32_ABGR', -} -SPI_SHADER_ZERO = 0 -SPI_SHADER_32_R = 1 -SPI_SHADER_32_GR = 2 -SPI_SHADER_32_AR = 3 -SPI_SHADER_FP16_ABGR = 4 -SPI_SHADER_UNORM16_ABGR = 5 -SPI_SHADER_SNORM16_ABGR = 6 -SPI_SHADER_UINT16_ABGR = 7 -SPI_SHADER_SINT16_ABGR = 8 -SPI_SHADER_32_ABGR = 9 -SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_FORMAT' -SPI_SHADER_FORMAT__enumvalues = { - 0: 'SPI_SHADER_NONE', - 1: 'SPI_SHADER_1COMP', - 2: 'SPI_SHADER_2COMP', - 3: 'SPI_SHADER_4COMPRESS', - 4: 'SPI_SHADER_4COMP', -} -SPI_SHADER_NONE = 0 -SPI_SHADER_1COMP = 1 -SPI_SHADER_2COMP = 2 -SPI_SHADER_4COMPRESS = 3 -SPI_SHADER_4COMP = 4 -SPI_SHADER_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ADDRESS_MODE' -SH_MEM_ADDRESS_MODE__enumvalues = { - 0: 'SH_MEM_ADDRESS_MODE_64', - 1: 'SH_MEM_ADDRESS_MODE_32', -} -SH_MEM_ADDRESS_MODE_64 = 0 -SH_MEM_ADDRESS_MODE_32 = 1 -SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ALIGNMENT_MODE' -SH_MEM_ALIGNMENT_MODE__enumvalues = { - 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', - 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', - 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', -} -SH_MEM_ALIGNMENT_MODE_DWORD = 0 -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 -SH_MEM_ALIGNMENT_MODE_STRICT = 2 -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 -SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQG_PERF_SEL' -SQG_PERF_SEL__enumvalues = { - 0: 'SQG_PERF_SEL_NONE', - 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', - 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', - 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', - 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 6: 'SQG_PERF_SEL_TTRACE_REQS', - 7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 8: 'SQG_PERF_SEL_TTRACE_STALL', - 9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', - 10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', - 11: 'SQG_PERF_SEL_EVENTS', - 12: 'SQG_PERF_SEL_WAVES_RESTORED', - 13: 'SQG_PERF_SEL_WAVES_SAVED', - 14: 'SQG_PERF_SEL_ACCUM_PREV', - 15: 'SQG_PERF_SEL_CYCLES', - 16: 'SQG_PERF_SEL_BUSY_CYCLES', - 17: 'SQG_PERF_SEL_WAVE_CYCLES', - 18: 'SQG_PERF_SEL_MSG', - 19: 'SQG_PERF_SEL_MSG_INTERRUPT', - 20: 'SQG_PERF_SEL_WAVES', - 21: 'SQG_PERF_SEL_WAVES_32', - 22: 'SQG_PERF_SEL_WAVES_64', - 23: 'SQG_PERF_SEL_LEVEL_WAVES', - 24: 'SQG_PERF_SEL_ITEMS', - 25: 'SQG_PERF_SEL_WAVE32_ITEMS', - 26: 'SQG_PERF_SEL_WAVE64_ITEMS', - 27: 'SQG_PERF_SEL_PS_QUADS', - 28: 'SQG_PERF_SEL_WAVES_EQ_64', - 29: 'SQG_PERF_SEL_WAVES_EQ_32', - 30: 'SQG_PERF_SEL_WAVES_LT_64', - 31: 'SQG_PERF_SEL_WAVES_LT_48', - 32: 'SQG_PERF_SEL_WAVES_LT_32', - 33: 'SQG_PERF_SEL_WAVES_LT_16', - 34: 'SQG_PERF_SEL_DUMMY_LAST', -} -SQG_PERF_SEL_NONE = 0 -SQG_PERF_SEL_MSG_BUS_BUSY = 1 -SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 -SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 -SQG_PERF_SEL_EXP_BUS0_BUSY = 4 -SQG_PERF_SEL_EXP_BUS1_BUSY = 5 -SQG_PERF_SEL_TTRACE_REQS = 6 -SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7 -SQG_PERF_SEL_TTRACE_STALL = 8 -SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9 -SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10 -SQG_PERF_SEL_EVENTS = 11 -SQG_PERF_SEL_WAVES_RESTORED = 12 -SQG_PERF_SEL_WAVES_SAVED = 13 -SQG_PERF_SEL_ACCUM_PREV = 14 -SQG_PERF_SEL_CYCLES = 15 -SQG_PERF_SEL_BUSY_CYCLES = 16 -SQG_PERF_SEL_WAVE_CYCLES = 17 -SQG_PERF_SEL_MSG = 18 -SQG_PERF_SEL_MSG_INTERRUPT = 19 -SQG_PERF_SEL_WAVES = 20 -SQG_PERF_SEL_WAVES_32 = 21 -SQG_PERF_SEL_WAVES_64 = 22 -SQG_PERF_SEL_LEVEL_WAVES = 23 -SQG_PERF_SEL_ITEMS = 24 -SQG_PERF_SEL_WAVE32_ITEMS = 25 -SQG_PERF_SEL_WAVE64_ITEMS = 26 -SQG_PERF_SEL_PS_QUADS = 27 -SQG_PERF_SEL_WAVES_EQ_64 = 28 -SQG_PERF_SEL_WAVES_EQ_32 = 29 -SQG_PERF_SEL_WAVES_LT_64 = 30 -SQG_PERF_SEL_WAVES_LT_48 = 31 -SQG_PERF_SEL_WAVES_LT_32 = 32 -SQG_PERF_SEL_WAVES_LT_16 = 33 -SQG_PERF_SEL_DUMMY_LAST = 34 -SQG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_CAC_POWER_SEL' -SQ_CAC_POWER_SEL__enumvalues = { - 0: 'SQ_CAC_POWER_VALU', - 1: 'SQ_CAC_POWER_VALU0', - 2: 'SQ_CAC_POWER_VALU1', - 3: 'SQ_CAC_POWER_VALU2', - 4: 'SQ_CAC_POWER_GPR_RD', - 5: 'SQ_CAC_POWER_GPR_WR', - 6: 'SQ_CAC_POWER_LDS_BUSY', - 7: 'SQ_CAC_POWER_ALU_BUSY', - 8: 'SQ_CAC_POWER_TEX_BUSY', -} -SQ_CAC_POWER_VALU = 0 -SQ_CAC_POWER_VALU0 = 1 -SQ_CAC_POWER_VALU1 = 2 -SQ_CAC_POWER_VALU2 = 3 -SQ_CAC_POWER_GPR_RD = 4 -SQ_CAC_POWER_GPR_WR = 5 -SQ_CAC_POWER_LDS_BUSY = 6 -SQ_CAC_POWER_ALU_BUSY = 7 -SQ_CAC_POWER_TEX_BUSY = 8 -SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_EDC_INFO_SOURCE' -SQ_EDC_INFO_SOURCE__enumvalues = { - 0: 'SQ_EDC_INFO_SOURCE_INVALID', - 1: 'SQ_EDC_INFO_SOURCE_INST', - 2: 'SQ_EDC_INFO_SOURCE_SGPR', - 3: 'SQ_EDC_INFO_SOURCE_VGPR', - 4: 'SQ_EDC_INFO_SOURCE_LDS', - 5: 'SQ_EDC_INFO_SOURCE_GDS', - 6: 'SQ_EDC_INFO_SOURCE_TA', -} -SQ_EDC_INFO_SOURCE_INVALID = 0 -SQ_EDC_INFO_SOURCE_INST = 1 -SQ_EDC_INFO_SOURCE_SGPR = 2 -SQ_EDC_INFO_SOURCE_VGPR = 3 -SQ_EDC_INFO_SOURCE_LDS = 4 -SQ_EDC_INFO_SOURCE_GDS = 5 -SQ_EDC_INFO_SOURCE_TA = 6 -SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IBUF_ST' -SQ_IBUF_ST__enumvalues = { - 0: 'SQ_IBUF_IB_IDLE', - 1: 'SQ_IBUF_IB_INI_WAIT_GNT', - 2: 'SQ_IBUF_IB_INI_WAIT_DRET', - 3: 'SQ_IBUF_IB_LE_4DW', - 4: 'SQ_IBUF_IB_WAIT_DRET', - 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 6: 'SQ_IBUF_IB_DRET', - 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', -} -SQ_IBUF_IB_IDLE = 0 -SQ_IBUF_IB_INI_WAIT_GNT = 1 -SQ_IBUF_IB_INI_WAIT_DRET = 2 -SQ_IBUF_IB_LE_4DW = 3 -SQ_IBUF_IB_WAIT_DRET = 4 -SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 -SQ_IBUF_IB_DRET = 6 -SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 -SQ_IBUF_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IMG_FILTER_TYPE' -SQ_IMG_FILTER_TYPE__enumvalues = { - 0: 'SQ_IMG_FILTER_MODE_BLEND', - 1: 'SQ_IMG_FILTER_MODE_MIN', - 2: 'SQ_IMG_FILTER_MODE_MAX', -} -SQ_IMG_FILTER_MODE_BLEND = 0 -SQ_IMG_FILTER_MODE_MIN = 1 -SQ_IMG_FILTER_MODE_MAX = 2 -SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_CMD' -SQ_IND_CMD_CMD__enumvalues = { - 0: 'SQ_IND_CMD_CMD_NULL', - 1: 'SQ_IND_CMD_CMD_SETHALT', - 2: 'SQ_IND_CMD_CMD_SAVECTX', - 3: 'SQ_IND_CMD_CMD_KILL', - 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', - 5: 'SQ_IND_CMD_CMD_TRAP', - 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 7: 'SQ_IND_CMD_CMD_SETFATALHALT', - 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', -} -SQ_IND_CMD_CMD_NULL = 0 -SQ_IND_CMD_CMD_SETHALT = 1 -SQ_IND_CMD_CMD_SAVECTX = 2 -SQ_IND_CMD_CMD_KILL = 3 -SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 -SQ_IND_CMD_CMD_TRAP = 5 -SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 -SQ_IND_CMD_CMD_SETFATALHALT = 7 -SQ_IND_CMD_CMD_SINGLE_STEP = 8 -SQ_IND_CMD_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_MODE' -SQ_IND_CMD_MODE__enumvalues = { - 0: 'SQ_IND_CMD_MODE_SINGLE', - 1: 'SQ_IND_CMD_MODE_BROADCAST', - 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', - 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', -} -SQ_IND_CMD_MODE_SINGLE = 0 -SQ_IND_CMD_MODE_BROADCAST = 1 -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 -SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 -SQ_IND_CMD_MODE_BROADCAST_ME = 4 -SQ_IND_CMD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_STR_ST' -SQ_INST_STR_ST__enumvalues = { - 0: 'SQ_INST_STR_IB_WAVE_NORML', - 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', - 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', -} -SQ_INST_STR_IB_WAVE_NORML = 0 -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 -SQ_INST_STR_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_TYPE' -SQ_INST_TYPE__enumvalues = { - 0: 'SQ_INST_TYPE_VALU', - 1: 'SQ_INST_TYPE_SCALAR', - 2: 'SQ_INST_TYPE_TEX', - 3: 'SQ_INST_TYPE_LDS', - 4: 'SQ_INST_TYPE_LDS_DIRECT', - 5: 'SQ_INST_TYPE_EXP', - 6: 'SQ_INST_TYPE_MSG', - 7: 'SQ_INST_TYPE_BARRIER', - 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', - 9: 'SQ_INST_TYPE_BRANCH_TAKEN', - 10: 'SQ_INST_TYPE_JUMP', - 11: 'SQ_INST_TYPE_OTHER', - 12: 'SQ_INST_TYPE_NONE', -} -SQ_INST_TYPE_VALU = 0 -SQ_INST_TYPE_SCALAR = 1 -SQ_INST_TYPE_TEX = 2 -SQ_INST_TYPE_LDS = 3 -SQ_INST_TYPE_LDS_DIRECT = 4 -SQ_INST_TYPE_EXP = 5 -SQ_INST_TYPE_MSG = 6 -SQ_INST_TYPE_BARRIER = 7 -SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 -SQ_INST_TYPE_BRANCH_TAKEN = 9 -SQ_INST_TYPE_JUMP = 10 -SQ_INST_TYPE_OTHER = 11 -SQ_INST_TYPE_NONE = 12 -SQ_INST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_LLC_CTL' -SQ_LLC_CTL__enumvalues = { - 0: 'SQ_LLC_0', - 1: 'SQ_LLC_1', - 2: 'SQ_LLC_RSVD_2', - 3: 'SQ_LLC_BYPASS', -} -SQ_LLC_0 = 0 -SQ_LLC_1 = 1 -SQ_LLC_RSVD_2 = 2 -SQ_LLC_BYPASS = 3 -SQ_LLC_CTL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_NO_INST_ISSUE' -SQ_NO_INST_ISSUE__enumvalues = { - 0: 'SQ_NO_INST_ISSUE_NO_INSTS', - 1: 'SQ_NO_INST_ISSUE_ALU_DEP', - 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', - 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', - 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', - 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', - 6: 'SQ_NO_INST_ISSUE_OTHER', -} -SQ_NO_INST_ISSUE_NO_INSTS = 0 -SQ_NO_INST_ISSUE_ALU_DEP = 1 -SQ_NO_INST_ISSUE_S_WAITCNT = 2 -SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 -SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 -SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 -SQ_NO_INST_ISSUE_OTHER = 6 -SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_OOB_SELECT' -SQ_OOB_SELECT__enumvalues = { - 0: 'SQ_OOB_INDEX_AND_OFFSET', - 1: 'SQ_OOB_INDEX_ONLY', - 2: 'SQ_OOB_NUM_RECORDS_0', - 3: 'SQ_OOB_COMPLETE', -} -SQ_OOB_INDEX_AND_OFFSET = 0 -SQ_OOB_INDEX_ONLY = 1 -SQ_OOB_NUM_RECORDS_0 = 2 -SQ_OOB_COMPLETE = 3 -SQ_OOB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_PERF_SEL' -SQ_PERF_SEL__enumvalues = { - 0: 'SQ_PERF_SEL_NONE', - 1: 'SQ_PERF_SEL_ACCUM_PREV', - 2: 'SQ_PERF_SEL_CYCLES', - 3: 'SQ_PERF_SEL_BUSY_CYCLES', - 4: 'SQ_PERF_SEL_WAVES', - 5: 'SQ_PERF_SEL_WAVES_32', - 6: 'SQ_PERF_SEL_WAVES_64', - 7: 'SQ_PERF_SEL_LEVEL_WAVES', - 8: 'SQ_PERF_SEL_ITEMS', - 9: 'SQ_PERF_SEL_WAVE32_ITEMS', - 10: 'SQ_PERF_SEL_WAVE64_ITEMS', - 11: 'SQ_PERF_SEL_PS_QUADS', - 12: 'SQ_PERF_SEL_EVENTS', - 13: 'SQ_PERF_SEL_WAVES_EQ_32', - 14: 'SQ_PERF_SEL_WAVES_EQ_64', - 15: 'SQ_PERF_SEL_WAVES_LT_64', - 16: 'SQ_PERF_SEL_WAVES_LT_48', - 17: 'SQ_PERF_SEL_WAVES_LT_32', - 18: 'SQ_PERF_SEL_WAVES_LT_16', - 19: 'SQ_PERF_SEL_WAVES_RESTORED', - 20: 'SQ_PERF_SEL_WAVES_SAVED', - 21: 'SQ_PERF_SEL_MSG', - 22: 'SQ_PERF_SEL_MSG_INTERRUPT', - 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 24: 'SQ_PERF_SEL_WAVE_CYCLES', - 25: 'SQ_PERF_SEL_WAVE_READY', - 26: 'SQ_PERF_SEL_WAIT_INST_ANY', - 27: 'SQ_PERF_SEL_WAIT_INST_VALU', - 28: 'SQ_PERF_SEL_WAIT_INST_SCA', - 29: 'SQ_PERF_SEL_WAIT_INST_LDS', - 30: 'SQ_PERF_SEL_WAIT_INST_TEX', - 31: 'SQ_PERF_SEL_WAIT_INST_FLAT', - 32: 'SQ_PERF_SEL_WAIT_INST_VMEM', - 33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', - 34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', - 35: 'SQ_PERF_SEL_WAIT_ANY', - 36: 'SQ_PERF_SEL_WAIT_CNT_ANY', - 37: 'SQ_PERF_SEL_WAIT_CNT_VMVS', - 38: 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 39: 'SQ_PERF_SEL_WAIT_CNT_EXP', - 40: 'SQ_PERF_SEL_WAIT_TTRACE', - 41: 'SQ_PERF_SEL_WAIT_IFETCH', - 42: 'SQ_PERF_SEL_WAIT_BARRIER', - 43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 44: 'SQ_PERF_SEL_WAIT_SLEEP', - 45: 'SQ_PERF_SEL_WAIT_DELAY_ALU', - 46: 'SQ_PERF_SEL_WAIT_DEPCTR', - 47: 'SQ_PERF_SEL_WAIT_OTHER', - 48: 'SQ_PERF_SEL_INSTS_ALL', - 49: 'SQ_PERF_SEL_INSTS_BRANCH', - 50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', - 53: 'SQ_PERF_SEL_INSTS_EXP_GDS', - 54: 'SQ_PERF_SEL_INSTS_GDS', - 55: 'SQ_PERF_SEL_INSTS_EXP', - 56: 'SQ_PERF_SEL_INSTS_FLAT', - 57: 'SQ_PERF_SEL_INSTS_LDS', - 58: 'SQ_PERF_SEL_INSTS_SALU', - 59: 'SQ_PERF_SEL_INSTS_SMEM', - 60: 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 61: 'SQ_PERF_SEL_INSTS_SENDMSG', - 62: 'SQ_PERF_SEL_INSTS_VALU', - 63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 65: 'SQ_PERF_SEL_INSTS_TEX', - 66: 'SQ_PERF_SEL_INSTS_TEX_LOAD', - 67: 'SQ_PERF_SEL_INSTS_TEX_STORE', - 68: 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 69: 'SQ_PERF_SEL_INSTS_INTERNAL', - 70: 'SQ_PERF_SEL_INSTS_WAVE32', - 71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', - 72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', - 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 82: 'SQ_PERF_SEL_WAVE32_INSTS', - 83: 'SQ_PERF_SEL_WAVE64_INSTS', - 84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 86: 'SQ_PERF_SEL_INST_LEVEL_EXP', - 87: 'SQ_PERF_SEL_INST_LEVEL_GDS', - 88: 'SQ_PERF_SEL_INST_LEVEL_LDS', - 89: 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', - 92: 'SQ_PERF_SEL_IFETCH_REQS', - 93: 'SQ_PERF_SEL_IFETCH_LEVEL', - 94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 95: 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 99: 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 103: 'SQ_PERF_SEL_INST_CYCLES_VALU', - 104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 106: 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 109: 'SQ_PERF_SEL_INST_CYCLES_LDS', - 110: 'SQ_PERF_SEL_INST_CYCLES_TEX', - 111: 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', - 113: 'SQ_PERF_SEL_INST_CYCLES_EXP', - 114: 'SQ_PERF_SEL_INST_CYCLES_GDS', - 115: 'SQ_PERF_SEL_VALU_STARVE', - 116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 120: 'SQ_PERF_SEL_VMEM_BUS_STALL', - 121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 127: 'SQ_PERF_SEL_SALU_PIPE_STALL', - 128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 129: 'SQ_PERF_SEL_MSG_BUS_BUSY', - 130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', - 131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', - 132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 133: 'SQ_PERF_SEL_EXP_BUS0_BUSY', - 134: 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', - 136: 'SQ_PERF_SEL_USER0', - 137: 'SQ_PERF_SEL_USER1', - 138: 'SQ_PERF_SEL_USER2', - 139: 'SQ_PERF_SEL_USER3', - 140: 'SQ_PERF_SEL_USER4', - 141: 'SQ_PERF_SEL_USER5', - 142: 'SQ_PERF_SEL_USER6', - 143: 'SQ_PERF_SEL_USER7', - 144: 'SQ_PERF_SEL_USER8', - 145: 'SQ_PERF_SEL_USER9', - 146: 'SQ_PERF_SEL_USER10', - 147: 'SQ_PERF_SEL_USER11', - 148: 'SQ_PERF_SEL_USER12', - 149: 'SQ_PERF_SEL_USER13', - 150: 'SQ_PERF_SEL_USER14', - 151: 'SQ_PERF_SEL_USER15', - 152: 'SQ_PERF_SEL_USER_LEVEL0', - 153: 'SQ_PERF_SEL_USER_LEVEL1', - 154: 'SQ_PERF_SEL_USER_LEVEL2', - 155: 'SQ_PERF_SEL_USER_LEVEL3', - 156: 'SQ_PERF_SEL_USER_LEVEL4', - 157: 'SQ_PERF_SEL_USER_LEVEL5', - 158: 'SQ_PERF_SEL_USER_LEVEL6', - 159: 'SQ_PERF_SEL_USER_LEVEL7', - 160: 'SQ_PERF_SEL_USER_LEVEL8', - 161: 'SQ_PERF_SEL_USER_LEVEL9', - 162: 'SQ_PERF_SEL_USER_LEVEL10', - 163: 'SQ_PERF_SEL_USER_LEVEL11', - 164: 'SQ_PERF_SEL_USER_LEVEL12', - 165: 'SQ_PERF_SEL_USER_LEVEL13', - 166: 'SQ_PERF_SEL_USER_LEVEL14', - 167: 'SQ_PERF_SEL_USER_LEVEL15', - 168: 'SQ_PERF_SEL_VALU_RETURN_SDST', - 169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 170: 'SQ_PERF_SEL_INSTS_VALU_TRANS', - 171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', - 173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', - 174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', - 176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', - 177: 'SQ_PERF_SEL_OVERFLOW_PREV', - 178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', - 179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', - 181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 182: 'SQ_PERF_SEL_INSTS_VALU_DP', - 183: 'SQ_PERF_SEL_SP_CONST_CYCLES', - 184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', - 185: 'SQ_PERF_SEL_ITEMS_VALU', - 186: 'SQ_PERF_SEL_ITEMS_MAX_VALU', - 187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 188: 'SQ_PERF_SEL_DUMMY_END', - 255: 'SQ_PERF_SEL_DUMMY_LAST', - 256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', - 259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 262: 'SQC_PERF_SEL_LDS_ADDR_STALL', - 263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', - 264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', - 268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 269: 'SQC_PERF_SEL_ICACHE_REQ', - 270: 'SQC_PERF_SEL_ICACHE_HITS', - 271: 'SQC_PERF_SEL_ICACHE_MISSES', - 272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 273: 'SQC_PERF_SEL_ICACHE_INVAL_INST', - 274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', - 278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 282: 'SQC_PERF_SEL_TC_REQ', - 283: 'SQC_PERF_SEL_TC_INST_REQ', - 284: 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 285: 'SQC_PERF_SEL_TC_STALL', - 286: 'SQC_PERF_SEL_TC_STARVE', - 287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 293: 'SQC_PERF_SEL_DCACHE_REQ', - 294: 'SQC_PERF_SEL_DCACHE_HITS', - 295: 'SQC_PERF_SEL_DCACHE_MISSES', - 296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 297: 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 312: 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 314: 'SQC_PERF_SEL_TD_VGPR_BUSY', - 315: 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 317: 'SQC_PERF_SEL_ICACHE_GCR', - 318: 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 319: 'SQC_PERF_SEL_DCACHE_GCR', - 320: 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', - 322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', - 323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 324: 'SQC_PERF_SEL_DUMMY_LAST', - 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', - 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', - 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', - 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', - 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 474: 'SP_PERF_SEL_VALU_OPERAND', - 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', - 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', - 480: 'SP_PERF_SEL_VALU_STALL', - 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 487: 'SP_PERF_SEL_VGPR_VMEM_RD', - 488: 'SP_PERF_SEL_VGPR_EXP_RD', - 489: 'SP_PERF_SEL_VGPR_SPI_WR', - 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', - 491: 'SP_PERF_SEL_VGPR_WR', - 492: 'SP_PERF_SEL_VGPR_RD', - 493: 'SP_PERF_SEL_DUMMY_LAST', - 511: 'SQ_PERF_SEL_NONE2', -} -SQ_PERF_SEL_NONE = 0 -SQ_PERF_SEL_ACCUM_PREV = 1 -SQ_PERF_SEL_CYCLES = 2 -SQ_PERF_SEL_BUSY_CYCLES = 3 -SQ_PERF_SEL_WAVES = 4 -SQ_PERF_SEL_WAVES_32 = 5 -SQ_PERF_SEL_WAVES_64 = 6 -SQ_PERF_SEL_LEVEL_WAVES = 7 -SQ_PERF_SEL_ITEMS = 8 -SQ_PERF_SEL_WAVE32_ITEMS = 9 -SQ_PERF_SEL_WAVE64_ITEMS = 10 -SQ_PERF_SEL_PS_QUADS = 11 -SQ_PERF_SEL_EVENTS = 12 -SQ_PERF_SEL_WAVES_EQ_32 = 13 -SQ_PERF_SEL_WAVES_EQ_64 = 14 -SQ_PERF_SEL_WAVES_LT_64 = 15 -SQ_PERF_SEL_WAVES_LT_48 = 16 -SQ_PERF_SEL_WAVES_LT_32 = 17 -SQ_PERF_SEL_WAVES_LT_16 = 18 -SQ_PERF_SEL_WAVES_RESTORED = 19 -SQ_PERF_SEL_WAVES_SAVED = 20 -SQ_PERF_SEL_MSG = 21 -SQ_PERF_SEL_MSG_INTERRUPT = 22 -SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 -SQ_PERF_SEL_WAVE_CYCLES = 24 -SQ_PERF_SEL_WAVE_READY = 25 -SQ_PERF_SEL_WAIT_INST_ANY = 26 -SQ_PERF_SEL_WAIT_INST_VALU = 27 -SQ_PERF_SEL_WAIT_INST_SCA = 28 -SQ_PERF_SEL_WAIT_INST_LDS = 29 -SQ_PERF_SEL_WAIT_INST_TEX = 30 -SQ_PERF_SEL_WAIT_INST_FLAT = 31 -SQ_PERF_SEL_WAIT_INST_VMEM = 32 -SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33 -SQ_PERF_SEL_WAIT_INST_BR_MSG = 34 -SQ_PERF_SEL_WAIT_ANY = 35 -SQ_PERF_SEL_WAIT_CNT_ANY = 36 -SQ_PERF_SEL_WAIT_CNT_VMVS = 37 -SQ_PERF_SEL_WAIT_CNT_LGKM = 38 -SQ_PERF_SEL_WAIT_CNT_EXP = 39 -SQ_PERF_SEL_WAIT_TTRACE = 40 -SQ_PERF_SEL_WAIT_IFETCH = 41 -SQ_PERF_SEL_WAIT_BARRIER = 42 -SQ_PERF_SEL_WAIT_EXP_ALLOC = 43 -SQ_PERF_SEL_WAIT_SLEEP = 44 -SQ_PERF_SEL_WAIT_DELAY_ALU = 45 -SQ_PERF_SEL_WAIT_DEPCTR = 46 -SQ_PERF_SEL_WAIT_OTHER = 47 -SQ_PERF_SEL_INSTS_ALL = 48 -SQ_PERF_SEL_INSTS_BRANCH = 49 -SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52 -SQ_PERF_SEL_INSTS_EXP_GDS = 53 -SQ_PERF_SEL_INSTS_GDS = 54 -SQ_PERF_SEL_INSTS_EXP = 55 -SQ_PERF_SEL_INSTS_FLAT = 56 -SQ_PERF_SEL_INSTS_LDS = 57 -SQ_PERF_SEL_INSTS_SALU = 58 -SQ_PERF_SEL_INSTS_SMEM = 59 -SQ_PERF_SEL_INSTS_SMEM_NORM = 60 -SQ_PERF_SEL_INSTS_SENDMSG = 61 -SQ_PERF_SEL_INSTS_VALU = 62 -SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63 -SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64 -SQ_PERF_SEL_INSTS_TEX = 65 -SQ_PERF_SEL_INSTS_TEX_LOAD = 66 -SQ_PERF_SEL_INSTS_TEX_STORE = 67 -SQ_PERF_SEL_INSTS_DELAY_ALU = 68 -SQ_PERF_SEL_INSTS_INTERNAL = 69 -SQ_PERF_SEL_INSTS_WAVE32 = 70 -SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71 -SQ_PERF_SEL_INSTS_WAVE32_LDS = 72 -SQ_PERF_SEL_INSTS_WAVE32_VALU = 73 -SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74 -SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75 -SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76 -SQ_PERF_SEL_INSTS_WAVE32_TEX = 77 -SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78 -SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79 -SQ_PERF_SEL_ITEM_CYCLES_VALU = 80 -SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81 -SQ_PERF_SEL_WAVE32_INSTS = 82 -SQ_PERF_SEL_WAVE64_INSTS = 83 -SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84 -SQ_PERF_SEL_WAVE64_HALF_SKIP = 85 -SQ_PERF_SEL_INST_LEVEL_EXP = 86 -SQ_PERF_SEL_INST_LEVEL_GDS = 87 -SQ_PERF_SEL_INST_LEVEL_LDS = 88 -SQ_PERF_SEL_INST_LEVEL_SMEM = 89 -SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90 -SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91 -SQ_PERF_SEL_IFETCH_REQS = 92 -SQ_PERF_SEL_IFETCH_LEVEL = 93 -SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94 -SQ_PERF_SEL_VALU_SGATHER_STALL = 95 -SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96 -SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97 -SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98 -SQ_PERF_SEL_SALU_SGATHER_STALL = 99 -SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100 -SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101 -SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102 -SQ_PERF_SEL_INST_CYCLES_VALU = 103 -SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104 -SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105 -SQ_PERF_SEL_INST_CYCLES_VMEM = 106 -SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107 -SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108 -SQ_PERF_SEL_INST_CYCLES_LDS = 109 -SQ_PERF_SEL_INST_CYCLES_TEX = 110 -SQ_PERF_SEL_INST_CYCLES_FLAT = 111 -SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112 -SQ_PERF_SEL_INST_CYCLES_EXP = 113 -SQ_PERF_SEL_INST_CYCLES_GDS = 114 -SQ_PERF_SEL_VALU_STARVE = 115 -SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116 -SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117 -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118 -SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119 -SQ_PERF_SEL_VMEM_BUS_STALL = 120 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124 -SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125 -SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126 -SQ_PERF_SEL_SALU_PIPE_STALL = 127 -SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128 -SQ_PERF_SEL_MSG_BUS_BUSY = 129 -SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130 -SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131 -SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132 -SQ_PERF_SEL_EXP_BUS0_BUSY = 133 -SQ_PERF_SEL_EXP_BUS1_BUSY = 134 -SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135 -SQ_PERF_SEL_USER0 = 136 -SQ_PERF_SEL_USER1 = 137 -SQ_PERF_SEL_USER2 = 138 -SQ_PERF_SEL_USER3 = 139 -SQ_PERF_SEL_USER4 = 140 -SQ_PERF_SEL_USER5 = 141 -SQ_PERF_SEL_USER6 = 142 -SQ_PERF_SEL_USER7 = 143 -SQ_PERF_SEL_USER8 = 144 -SQ_PERF_SEL_USER9 = 145 -SQ_PERF_SEL_USER10 = 146 -SQ_PERF_SEL_USER11 = 147 -SQ_PERF_SEL_USER12 = 148 -SQ_PERF_SEL_USER13 = 149 -SQ_PERF_SEL_USER14 = 150 -SQ_PERF_SEL_USER15 = 151 -SQ_PERF_SEL_USER_LEVEL0 = 152 -SQ_PERF_SEL_USER_LEVEL1 = 153 -SQ_PERF_SEL_USER_LEVEL2 = 154 -SQ_PERF_SEL_USER_LEVEL3 = 155 -SQ_PERF_SEL_USER_LEVEL4 = 156 -SQ_PERF_SEL_USER_LEVEL5 = 157 -SQ_PERF_SEL_USER_LEVEL6 = 158 -SQ_PERF_SEL_USER_LEVEL7 = 159 -SQ_PERF_SEL_USER_LEVEL8 = 160 -SQ_PERF_SEL_USER_LEVEL9 = 161 -SQ_PERF_SEL_USER_LEVEL10 = 162 -SQ_PERF_SEL_USER_LEVEL11 = 163 -SQ_PERF_SEL_USER_LEVEL12 = 164 -SQ_PERF_SEL_USER_LEVEL13 = 165 -SQ_PERF_SEL_USER_LEVEL14 = 166 -SQ_PERF_SEL_USER_LEVEL15 = 167 -SQ_PERF_SEL_VALU_RETURN_SDST = 168 -SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169 -SQ_PERF_SEL_INSTS_VALU_TRANS = 170 -SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171 -SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172 -SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173 -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174 -SQ_PERF_SEL_INSTS_VALU_VINTERP = 175 -SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176 -SQ_PERF_SEL_OVERFLOW_PREV = 177 -SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178 -SQ_PERF_SEL_INSTS_VALU_1_PASS = 179 -SQ_PERF_SEL_INSTS_VALU_2_PASS = 180 -SQ_PERF_SEL_INSTS_VALU_4_PASS = 181 -SQ_PERF_SEL_INSTS_VALU_DP = 182 -SQ_PERF_SEL_SP_CONST_CYCLES = 183 -SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184 -SQ_PERF_SEL_ITEMS_VALU = 185 -SQ_PERF_SEL_ITEMS_MAX_VALU = 186 -SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187 -SQ_PERF_SEL_DUMMY_END = 188 -SQ_PERF_SEL_DUMMY_LAST = 255 -SQC_PERF_SEL_LDS_BANK_CONFLICT = 256 -SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257 -SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258 -SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259 -SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260 -SQC_PERF_SEL_LDS_IDX_ACTIVE = 261 -SQC_PERF_SEL_LDS_ADDR_STALL = 262 -SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263 -SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264 -SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265 -SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266 -SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267 -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268 -SQC_PERF_SEL_ICACHE_REQ = 269 -SQC_PERF_SEL_ICACHE_HITS = 270 -SQC_PERF_SEL_ICACHE_MISSES = 271 -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272 -SQC_PERF_SEL_ICACHE_INVAL_INST = 273 -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274 -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275 -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276 -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277 -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278 -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281 -SQC_PERF_SEL_TC_REQ = 282 -SQC_PERF_SEL_TC_INST_REQ = 283 -SQC_PERF_SEL_TC_DATA_READ_REQ = 284 -SQC_PERF_SEL_TC_STALL = 285 -SQC_PERF_SEL_TC_STARVE = 286 -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287 -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288 -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290 -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291 -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292 -SQC_PERF_SEL_DCACHE_REQ = 293 -SQC_PERF_SEL_DCACHE_HITS = 294 -SQC_PERF_SEL_DCACHE_MISSES = 295 -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296 -SQC_PERF_SEL_DCACHE_INVAL_INST = 297 -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298 -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299 -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300 -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301 -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304 -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305 -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306 -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307 -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308 -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309 -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310 -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311 -SQC_PERF_SEL_SQ_DCACHE_REQS = 312 -SQC_PERF_SEL_DCACHE_FLAT_REQ = 313 -SQC_PERF_SEL_TD_VGPR_BUSY = 314 -SQC_PERF_SEL_LDS_VGPR_BUSY = 315 -SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316 -SQC_PERF_SEL_ICACHE_GCR = 317 -SQC_PERF_SEL_ICACHE_GCR_HITS = 318 -SQC_PERF_SEL_DCACHE_GCR = 319 -SQC_PERF_SEL_DCACHE_GCR_HITS = 320 -SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321 -SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322 -SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323 -SQC_PERF_SEL_DUMMY_LAST = 324 -SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 -SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 -SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 -SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 -SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 -SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 -SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 -SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 -SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 -SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 -SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 -SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 -SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 -SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 -SP_PERF_SEL_VALU_OPERAND = 474 -SP_PERF_SEL_VALU_VGPR_OPERAND = 475 -SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 -SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 -SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 -SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 -SP_PERF_SEL_VALU_STALL = 480 -SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 -SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 -SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 -SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 -SP_PERF_SEL_VALU_STALL_DST_STALL = 485 -SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 -SP_PERF_SEL_VGPR_VMEM_RD = 487 -SP_PERF_SEL_VGPR_EXP_RD = 488 -SP_PERF_SEL_VGPR_SPI_WR = 489 -SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 -SP_PERF_SEL_VGPR_WR = 491 -SP_PERF_SEL_VGPR_RD = 492 -SP_PERF_SEL_DUMMY_LAST = 493 -SQ_PERF_SEL_NONE2 = 511 -SQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_ROUND_MODE' -SQ_ROUND_MODE__enumvalues = { - 0: 'SQ_ROUND_NEAREST_EVEN', - 1: 'SQ_ROUND_PLUS_INFINITY', - 2: 'SQ_ROUND_MINUS_INFINITY', - 3: 'SQ_ROUND_TO_ZERO', -} -SQ_ROUND_NEAREST_EVEN = 0 -SQ_ROUND_PLUS_INFINITY = 1 -SQ_ROUND_MINUS_INFINITY = 2 -SQ_ROUND_TO_ZERO = 3 -SQ_ROUND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_BUF_TYPE' -SQ_RSRC_BUF_TYPE__enumvalues = { - 0: 'SQ_RSRC_BUF', - 1: 'SQ_RSRC_BUF_RSVD_1', - 2: 'SQ_RSRC_BUF_RSVD_2', - 3: 'SQ_RSRC_BUF_RSVD_3', -} -SQ_RSRC_BUF = 0 -SQ_RSRC_BUF_RSVD_1 = 1 -SQ_RSRC_BUF_RSVD_2 = 2 -SQ_RSRC_BUF_RSVD_3 = 3 -SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_FLAT_TYPE' -SQ_RSRC_FLAT_TYPE__enumvalues = { - 0: 'SQ_RSRC_FLAT_RSVD_0', - 1: 'SQ_RSRC_FLAT', - 2: 'SQ_RSRC_FLAT_RSVD_2', - 3: 'SQ_RSRC_FLAT_RSVD_3', -} -SQ_RSRC_FLAT_RSVD_0 = 0 -SQ_RSRC_FLAT = 1 -SQ_RSRC_FLAT_RSVD_2 = 2 -SQ_RSRC_FLAT_RSVD_3 = 3 -SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_IMG_TYPE' -SQ_RSRC_IMG_TYPE__enumvalues = { - 0: 'SQ_RSRC_IMG_RSVD_0', - 1: 'SQ_RSRC_IMG_RSVD_1', - 2: 'SQ_RSRC_IMG_RSVD_2', - 3: 'SQ_RSRC_IMG_RSVD_3', - 4: 'SQ_RSRC_IMG_RSVD_4', - 5: 'SQ_RSRC_IMG_RSVD_5', - 6: 'SQ_RSRC_IMG_RSVD_6', - 7: 'SQ_RSRC_IMG_RSVD_7', - 8: 'SQ_RSRC_IMG_1D', - 9: 'SQ_RSRC_IMG_2D', - 10: 'SQ_RSRC_IMG_3D', - 11: 'SQ_RSRC_IMG_CUBE', - 12: 'SQ_RSRC_IMG_1D_ARRAY', - 13: 'SQ_RSRC_IMG_2D_ARRAY', - 14: 'SQ_RSRC_IMG_2D_MSAA', - 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', -} -SQ_RSRC_IMG_RSVD_0 = 0 -SQ_RSRC_IMG_RSVD_1 = 1 -SQ_RSRC_IMG_RSVD_2 = 2 -SQ_RSRC_IMG_RSVD_3 = 3 -SQ_RSRC_IMG_RSVD_4 = 4 -SQ_RSRC_IMG_RSVD_5 = 5 -SQ_RSRC_IMG_RSVD_6 = 6 -SQ_RSRC_IMG_RSVD_7 = 7 -SQ_RSRC_IMG_1D = 8 -SQ_RSRC_IMG_2D = 9 -SQ_RSRC_IMG_3D = 10 -SQ_RSRC_IMG_CUBE = 11 -SQ_RSRC_IMG_1D_ARRAY = 12 -SQ_RSRC_IMG_2D_ARRAY = 13 -SQ_RSRC_IMG_2D_MSAA = 14 -SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 -SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_SEL_XYZW01' -SQ_SEL_XYZW01__enumvalues = { - 0: 'SQ_SEL_0', - 1: 'SQ_SEL_1', - 2: 'SQ_SEL_N_BC_1', - 3: 'SQ_SEL_RESERVED_1', - 4: 'SQ_SEL_X', - 5: 'SQ_SEL_Y', - 6: 'SQ_SEL_Z', - 7: 'SQ_SEL_W', -} -SQ_SEL_0 = 0 -SQ_SEL_1 = 1 -SQ_SEL_N_BC_1 = 2 -SQ_SEL_RESERVED_1 = 3 -SQ_SEL_X = 4 -SQ_SEL_Y = 5 -SQ_SEL_Z = 6 -SQ_SEL_W = 7 -SQ_SEL_XYZW01 = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_ANISO_RATIO' -SQ_TEX_ANISO_RATIO__enumvalues = { - 0: 'SQ_TEX_ANISO_RATIO_1', - 1: 'SQ_TEX_ANISO_RATIO_2', - 2: 'SQ_TEX_ANISO_RATIO_4', - 3: 'SQ_TEX_ANISO_RATIO_8', - 4: 'SQ_TEX_ANISO_RATIO_16', -} -SQ_TEX_ANISO_RATIO_1 = 0 -SQ_TEX_ANISO_RATIO_2 = 1 -SQ_TEX_ANISO_RATIO_4 = 2 -SQ_TEX_ANISO_RATIO_8 = 3 -SQ_TEX_ANISO_RATIO_16 = 4 -SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_BORDER_COLOR' -SQ_TEX_BORDER_COLOR__enumvalues = { - 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 3: 'SQ_TEX_BORDER_COLOR_REGISTER', -} -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 -SQ_TEX_BORDER_COLOR_REGISTER = 3 -SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_CLAMP' -SQ_TEX_CLAMP__enumvalues = { - 0: 'SQ_TEX_WRAP', - 1: 'SQ_TEX_MIRROR', - 2: 'SQ_TEX_CLAMP_LAST_TEXEL', - 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 4: 'SQ_TEX_CLAMP_HALF_BORDER', - 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', - 6: 'SQ_TEX_CLAMP_BORDER', - 7: 'SQ_TEX_MIRROR_ONCE_BORDER', -} -SQ_TEX_WRAP = 0 -SQ_TEX_MIRROR = 1 -SQ_TEX_CLAMP_LAST_TEXEL = 2 -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 -SQ_TEX_CLAMP_HALF_BORDER = 4 -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 -SQ_TEX_CLAMP_BORDER = 6 -SQ_TEX_MIRROR_ONCE_BORDER = 7 -SQ_TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_DEPTH_COMPARE' -SQ_TEX_DEPTH_COMPARE__enumvalues = { - 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', - 1: 'SQ_TEX_DEPTH_COMPARE_LESS', - 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', - 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', - 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', - 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', - 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', -} -SQ_TEX_DEPTH_COMPARE_NEVER = 0 -SQ_TEX_DEPTH_COMPARE_LESS = 1 -SQ_TEX_DEPTH_COMPARE_EQUAL = 2 -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 -SQ_TEX_DEPTH_COMPARE_GREATER = 4 -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 -SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 -SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_MIP_FILTER' -SQ_TEX_MIP_FILTER__enumvalues = { - 0: 'SQ_TEX_MIP_FILTER_NONE', - 1: 'SQ_TEX_MIP_FILTER_POINT', - 2: 'SQ_TEX_MIP_FILTER_LINEAR', - 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', -} -SQ_TEX_MIP_FILTER_NONE = 0 -SQ_TEX_MIP_FILTER_POINT = 1 -SQ_TEX_MIP_FILTER_LINEAR = 2 -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 -SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_XY_FILTER' -SQ_TEX_XY_FILTER__enumvalues = { - 0: 'SQ_TEX_XY_FILTER_POINT', - 1: 'SQ_TEX_XY_FILTER_BILINEAR', - 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', - 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', -} -SQ_TEX_XY_FILTER_POINT = 0 -SQ_TEX_XY_FILTER_BILINEAR = 1 -SQ_TEX_XY_FILTER_ANISO_POINT = 2 -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 -SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_Z_FILTER' -SQ_TEX_Z_FILTER__enumvalues = { - 0: 'SQ_TEX_Z_FILTER_NONE', - 1: 'SQ_TEX_Z_FILTER_POINT', - 2: 'SQ_TEX_Z_FILTER_LINEAR', -} -SQ_TEX_Z_FILTER_NONE = 0 -SQ_TEX_Z_FILTER_POINT = 1 -SQ_TEX_Z_FILTER_LINEAR = 2 -SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_MODE' -SQ_TT_MODE__enumvalues = { - 0: 'SQ_TT_MODE_OFF', - 1: 'SQ_TT_MODE_ON', - 2: 'SQ_TT_MODE_GLOBAL', - 3: 'SQ_TT_MODE_DETAIL', -} -SQ_TT_MODE_OFF = 0 -SQ_TT_MODE_ON = 1 -SQ_TT_MODE_GLOBAL = 2 -SQ_TT_MODE_DETAIL = 3 -SQ_TT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_RT_FREQ' -SQ_TT_RT_FREQ__enumvalues = { - 0: 'SQ_TT_RT_FREQ_NEVER', - 1: 'SQ_TT_RT_FREQ_1024_CLK', - 2: 'SQ_TT_RT_FREQ_4096_CLK', -} -SQ_TT_RT_FREQ_NEVER = 0 -SQ_TT_RT_FREQ_1024_CLK = 1 -SQ_TT_RT_FREQ_4096_CLK = 2 -SQ_TT_RT_FREQ = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' -SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { - 1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', - 2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', -} -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1 -SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2 -SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', - 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', -} -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0 -SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1 -SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE' -SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = { - 1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', - 2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', - 4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', -} -SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1 -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2 -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4 -SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', - 1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', - 2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', -} -SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0 -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1 -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2 -SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' -SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { - 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', - 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', - 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', - 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', - 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', - 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', - 64: 'SQ_TT_TOKEN_MASK_ALL_BIT', - 128: 'SQ_TT_TOKEN_MASK_RSVD_BIT', -} -SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 -SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 -SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 -SQ_TT_TOKEN_MASK_COMP_BIT = 8 -SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 -SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 -SQ_TT_TOKEN_MASK_ALL_BIT = 64 -SQ_TT_TOKEN_MASK_RSVD_BIT = 128 -SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', - 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', - 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', - 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', - 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', - 6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT', - 7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', -} -SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 -SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 -SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 -SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 -SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 -SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 -SQ_TT_TOKEN_MASK_ALL_SHIFT = 6 -SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7 -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', - 4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', - 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', -} -SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 -SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 -SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 -SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 -SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4 -SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 -SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 -SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 -SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 -SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 -SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 -SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_UTIL_TIMER' -SQ_TT_UTIL_TIMER__enumvalues = { - 0: 'SQ_TT_UTIL_TIMER_100_CLK', - 1: 'SQ_TT_UTIL_TIMER_250_CLK', -} -SQ_TT_UTIL_TIMER_100_CLK = 0 -SQ_TT_UTIL_TIMER_250_CLK = 1 -SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WAVESTART_MODE' -SQ_TT_WAVESTART_MODE__enumvalues = { - 0: 'SQ_TT_WAVESTART_MODE_SHORT', - 1: 'SQ_TT_WAVESTART_MODE_ALLOC', - 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', -} -SQ_TT_WAVESTART_MODE_SHORT = 0 -SQ_TT_WAVESTART_MODE_ALLOC = 1 -SQ_TT_WAVESTART_MODE_PBB_ID = 2 -SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE' -SQ_TT_WTYPE_INCLUDE__enumvalues = { - 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', - 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', - 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', - 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', -} -SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 -SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2 -SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 -SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8 -SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 -SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32 -SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 -SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' -SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', - 1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', - 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', - 3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', - 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', - 5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', - 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', -} -SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 -SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1 -SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 -SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3 -SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 -SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5 -SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 -SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WATCH_MODES' -SQ_WATCH_MODES__enumvalues = { - 0: 'SQ_WATCH_MODE_READ', - 1: 'SQ_WATCH_MODE_NONREAD', - 2: 'SQ_WATCH_MODE_ATOMIC', - 3: 'SQ_WATCH_MODE_ALL', -} -SQ_WATCH_MODE_READ = 0 -SQ_WATCH_MODE_NONREAD = 1 -SQ_WATCH_MODE_ATOMIC = 2 -SQ_WATCH_MODE_ALL = 3 -SQ_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' -SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { - 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', - 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', - 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', -} -SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 -SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 -SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 -SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 -SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_IB_ECC_ST' -SQ_WAVE_IB_ECC_ST__enumvalues = { - 0: 'SQ_WAVE_IB_ECC_CLEAN', - 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 2: 'SQ_WAVE_IB_ECC_ERR_HALT', - 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', -} -SQ_WAVE_IB_ECC_CLEAN = 0 -SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 -SQ_WAVE_IB_ECC_ERR_HALT = 2 -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 -SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_SCHED_MODES' -SQ_WAVE_SCHED_MODES__enumvalues = { - 0: 'SQ_WAVE_SCHED_MODE_NORMAL', - 1: 'SQ_WAVE_SCHED_MODE_EXPERT', - 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', -} -SQ_WAVE_SCHED_MODE_NORMAL = 0 -SQ_WAVE_SCHED_MODE_EXPERT = 1 -SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 -SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_TYPE' -SQ_WAVE_TYPE__enumvalues = { - 0: 'SQ_WAVE_TYPE_PS', - 1: 'SQ_WAVE_TYPE_RSVD0', - 2: 'SQ_WAVE_TYPE_GS', - 3: 'SQ_WAVE_TYPE_RSVD1', - 4: 'SQ_WAVE_TYPE_HS', - 5: 'SQ_WAVE_TYPE_RSVD2', - 6: 'SQ_WAVE_TYPE_CS', - 7: 'SQ_WAVE_TYPE_PS1', - 8: 'SQ_WAVE_TYPE_PS2', - 9: 'SQ_WAVE_TYPE_PS3', -} -SQ_WAVE_TYPE_PS = 0 -SQ_WAVE_TYPE_RSVD0 = 1 -SQ_WAVE_TYPE_GS = 2 -SQ_WAVE_TYPE_RSVD1 = 3 -SQ_WAVE_TYPE_HS = 4 -SQ_WAVE_TYPE_RSVD2 = 5 -SQ_WAVE_TYPE_CS = 6 -SQ_WAVE_TYPE_PS1 = 7 -SQ_WAVE_TYPE_PS2 = 8 -SQ_WAVE_TYPE_PS3 = 9 -SQ_WAVE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSCNTL_TYPE' -CSCNTL_TYPE__enumvalues = { - 0: 'CSCNTL_TYPE_TG', - 1: 'CSCNTL_TYPE_STATE', - 2: 'CSCNTL_TYPE_EVENT', - 3: 'CSCNTL_TYPE_PRIVATE', -} -CSCNTL_TYPE_TG = 0 -CSCNTL_TYPE_STATE = 1 -CSCNTL_TYPE_EVENT = 2 -CSCNTL_TYPE_PRIVATE = 3 -CSCNTL_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSDATA_TYPE' -CSDATA_TYPE__enumvalues = { - 0: 'CSDATA_TYPE_TG', - 1: 'CSDATA_TYPE_STATE', - 2: 'CSDATA_TYPE_EVENT', - 3: 'CSDATA_TYPE_PRIVATE', -} -CSDATA_TYPE_TG = 0 -CSDATA_TYPE_STATE = 1 -CSDATA_TYPE_EVENT = 2 -CSDATA_TYPE_PRIVATE = 3 -CSDATA_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GE1_PERFCOUNT_SELECT' -GE1_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge1_assembler_busy', - 1: 'ge1_assembler_stalled', - 2: 'ge1_dma_busy', - 3: 'ge1_dma_lat_bin_0', - 4: 'ge1_dma_lat_bin_1', - 5: 'ge1_dma_lat_bin_2', - 6: 'ge1_dma_lat_bin_3', - 7: 'ge1_dma_lat_bin_4', - 8: 'ge1_dma_lat_bin_5', - 9: 'ge1_dma_lat_bin_6', - 10: 'ge1_dma_lat_bin_7', - 11: 'ge1_dma_return_cl0', - 12: 'ge1_dma_return_cl1', - 13: 'ge1_dma_utcl1_consecutive_retry_event', - 14: 'ge1_dma_utcl1_request_event', - 15: 'ge1_dma_utcl1_retry_event', - 16: 'ge1_dma_utcl1_stall_event', - 17: 'ge1_dma_utcl1_stall_utcl2_event', - 18: 'ge1_dma_utcl1_translation_hit_event', - 19: 'ge1_dma_utcl1_translation_miss_event', - 20: 'ge1_assembler_dma_starved', - 21: 'ge1_rbiu_di_fifo_stalled_p0', - 22: 'ge1_rbiu_di_fifo_starved_p0', - 23: 'ge1_rbiu_dr_fifo_stalled_p0', - 24: 'ge1_rbiu_dr_fifo_starved_p0', - 25: 'ge1_sclk_reg_vld', - 26: 'ge1_stat_busy', - 27: 'ge1_stat_no_dma_busy', - 28: 'ge1_pipe0_to_pipe1', - 29: 'ge1_pipe1_to_pipe0', - 30: 'ge1_dma_return_size_cl0', - 31: 'ge1_dma_return_size_cl1', - 32: 'ge1_small_draws_one_instance', - 33: 'ge1_sclk_input_vld', - 34: 'ge1_prim_group_limit_hit', - 35: 'ge1_unopt_multi_instance_draws', - 36: 'ge1_rbiu_di_fifo_stalled_p1', - 37: 'ge1_rbiu_di_fifo_starved_p1', - 38: 'ge1_rbiu_dr_fifo_stalled_p1', - 39: 'ge1_rbiu_dr_fifo_starved_p1', -} -ge1_assembler_busy = 0 -ge1_assembler_stalled = 1 -ge1_dma_busy = 2 -ge1_dma_lat_bin_0 = 3 -ge1_dma_lat_bin_1 = 4 -ge1_dma_lat_bin_2 = 5 -ge1_dma_lat_bin_3 = 6 -ge1_dma_lat_bin_4 = 7 -ge1_dma_lat_bin_5 = 8 -ge1_dma_lat_bin_6 = 9 -ge1_dma_lat_bin_7 = 10 -ge1_dma_return_cl0 = 11 -ge1_dma_return_cl1 = 12 -ge1_dma_utcl1_consecutive_retry_event = 13 -ge1_dma_utcl1_request_event = 14 -ge1_dma_utcl1_retry_event = 15 -ge1_dma_utcl1_stall_event = 16 -ge1_dma_utcl1_stall_utcl2_event = 17 -ge1_dma_utcl1_translation_hit_event = 18 -ge1_dma_utcl1_translation_miss_event = 19 -ge1_assembler_dma_starved = 20 -ge1_rbiu_di_fifo_stalled_p0 = 21 -ge1_rbiu_di_fifo_starved_p0 = 22 -ge1_rbiu_dr_fifo_stalled_p0 = 23 -ge1_rbiu_dr_fifo_starved_p0 = 24 -ge1_sclk_reg_vld = 25 -ge1_stat_busy = 26 -ge1_stat_no_dma_busy = 27 -ge1_pipe0_to_pipe1 = 28 -ge1_pipe1_to_pipe0 = 29 -ge1_dma_return_size_cl0 = 30 -ge1_dma_return_size_cl1 = 31 -ge1_small_draws_one_instance = 32 -ge1_sclk_input_vld = 33 -ge1_prim_group_limit_hit = 34 -ge1_unopt_multi_instance_draws = 35 -ge1_rbiu_di_fifo_stalled_p1 = 36 -ge1_rbiu_di_fifo_starved_p1 = 37 -ge1_rbiu_dr_fifo_stalled_p1 = 38 -ge1_rbiu_dr_fifo_starved_p1 = 39 -GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' -GE2_DIST_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_dist_hs_done', - 1: 'ge_dist_hs_done_latency_se0', - 2: 'ge_dist_hs_done_latency_se1', - 3: 'ge_dist_hs_done_latency_se2', - 4: 'ge_dist_hs_done_latency_se3', - 5: 'ge_dist_hs_done_latency_se4', - 6: 'ge_dist_hs_done_latency_se5', - 7: 'ge_dist_hs_done_latency_se6', - 8: 'ge_dist_hs_done_latency_se7', - 9: 'ge_dist_inside_tf_bin_0', - 10: 'ge_dist_inside_tf_bin_1', - 11: 'ge_dist_inside_tf_bin_2', - 12: 'ge_dist_inside_tf_bin_3', - 13: 'ge_dist_inside_tf_bin_4', - 14: 'ge_dist_inside_tf_bin_5', - 15: 'ge_dist_inside_tf_bin_6', - 16: 'ge_dist_inside_tf_bin_7', - 17: 'ge_dist_inside_tf_bin_8', - 18: 'ge_dist_null_patch', - 19: 'ge_dist_sclk_core_vld', - 20: 'ge_dist_sclk_wd_te11_vld', - 21: 'ge_dist_tfreq_lat_bin_0', - 22: 'ge_dist_tfreq_lat_bin_1', - 23: 'ge_dist_tfreq_lat_bin_2', - 24: 'ge_dist_tfreq_lat_bin_3', - 25: 'ge_dist_tfreq_lat_bin_4', - 26: 'ge_dist_tfreq_lat_bin_5', - 27: 'ge_dist_tfreq_lat_bin_6', - 28: 'ge_dist_tfreq_lat_bin_7', - 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 30: 'ge_dist_tfreq_utcl1_request_event', - 31: 'ge_dist_tfreq_utcl1_retry_event', - 32: 'ge_dist_tfreq_utcl1_stall_event', - 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 34: 'ge_dist_tfreq_utcl1_translation_hit_event', - 35: 'ge_dist_tfreq_utcl1_translation_miss_event', - 36: 'ge_dist_vs_pc_stall', - 37: 'ge_dist_pc_feorder_fifo_full', - 38: 'ge_dist_pc_ge_manager_busy', - 39: 'ge_dist_pc_req_stall_se0', - 40: 'ge_dist_pc_req_stall_se1', - 41: 'ge_dist_pc_req_stall_se2', - 42: 'ge_dist_pc_req_stall_se3', - 43: 'ge_dist_pc_req_stall_se4', - 44: 'ge_dist_pc_req_stall_se5', - 45: 'ge_dist_pc_req_stall_se6', - 46: 'ge_dist_pc_req_stall_se7', - 47: 'ge_dist_pc_space_zero', - 48: 'ge_dist_sclk_input_vld', - 49: 'ge_dist_reserved', - 50: 'ge_dist_wd_te11_busy', - 51: 'ge_dist_te11_starved', - 52: 'ge_dist_switch_mode_stall', - 53: 'ge_all_tf_eq', - 54: 'ge_all_tf2', - 55: 'ge_all_tf3', - 56: 'ge_all_tf4', - 57: 'ge_all_tf5', - 58: 'ge_all_tf6', - 59: 'ge_se0_te11_starved_on_hs_done', - 60: 'ge_se1_te11_starved_on_hs_done', - 61: 'ge_se2_te11_starved_on_hs_done', - 62: 'ge_se3_te11_starved_on_hs_done', - 63: 'ge_se4_te11_starved_on_hs_done', - 64: 'ge_se5_te11_starved_on_hs_done', - 65: 'ge_se6_te11_starved_on_hs_done', - 66: 'ge_se7_te11_starved_on_hs_done', - 67: 'ge_dist_op_fifo_full_starve', - 68: 'ge_dist_hs_done_se0', - 69: 'ge_dist_hs_done_se1', - 70: 'ge_dist_hs_done_se2', - 71: 'ge_dist_hs_done_se3', - 72: 'ge_dist_hs_done_se4', - 73: 'ge_dist_hs_done_se5', - 74: 'ge_dist_hs_done_se6', - 75: 'ge_dist_hs_done_se7', - 76: 'ge_dist_hs_done_latency', - 77: 'ge_dist_distributer_busy', - 78: 'ge_tf_ret_data_stalling_hs_done', - 79: 'ge_num_of_no_dist_patches', - 80: 'ge_num_of_donut_dist_patches', - 81: 'ge_num_of_patch_dist_patches', - 82: 'ge_num_of_se_switches_due_to_patch_accum', - 83: 'ge_num_of_se_switches_due_to_donut', - 84: 'ge_num_of_se_switches_due_to_trap', - 85: 'ge_num_of_hs_alloc_events', - 86: 'ge_agm_gcr_req', - 87: 'ge_agm_gcr_tag_stall', - 88: 'ge_agm_gcr_crd_stall', - 89: 'ge_agm_gcr_stall', - 90: 'ge_agm_gcr_latency', - 91: 'ge_distclk_vld', -} -ge_dist_hs_done = 0 -ge_dist_hs_done_latency_se0 = 1 -ge_dist_hs_done_latency_se1 = 2 -ge_dist_hs_done_latency_se2 = 3 -ge_dist_hs_done_latency_se3 = 4 -ge_dist_hs_done_latency_se4 = 5 -ge_dist_hs_done_latency_se5 = 6 -ge_dist_hs_done_latency_se6 = 7 -ge_dist_hs_done_latency_se7 = 8 -ge_dist_inside_tf_bin_0 = 9 -ge_dist_inside_tf_bin_1 = 10 -ge_dist_inside_tf_bin_2 = 11 -ge_dist_inside_tf_bin_3 = 12 -ge_dist_inside_tf_bin_4 = 13 -ge_dist_inside_tf_bin_5 = 14 -ge_dist_inside_tf_bin_6 = 15 -ge_dist_inside_tf_bin_7 = 16 -ge_dist_inside_tf_bin_8 = 17 -ge_dist_null_patch = 18 -ge_dist_sclk_core_vld = 19 -ge_dist_sclk_wd_te11_vld = 20 -ge_dist_tfreq_lat_bin_0 = 21 -ge_dist_tfreq_lat_bin_1 = 22 -ge_dist_tfreq_lat_bin_2 = 23 -ge_dist_tfreq_lat_bin_3 = 24 -ge_dist_tfreq_lat_bin_4 = 25 -ge_dist_tfreq_lat_bin_5 = 26 -ge_dist_tfreq_lat_bin_6 = 27 -ge_dist_tfreq_lat_bin_7 = 28 -ge_dist_tfreq_utcl1_consecutive_retry_event = 29 -ge_dist_tfreq_utcl1_request_event = 30 -ge_dist_tfreq_utcl1_retry_event = 31 -ge_dist_tfreq_utcl1_stall_event = 32 -ge_dist_tfreq_utcl1_stall_utcl2_event = 33 -ge_dist_tfreq_utcl1_translation_hit_event = 34 -ge_dist_tfreq_utcl1_translation_miss_event = 35 -ge_dist_vs_pc_stall = 36 -ge_dist_pc_feorder_fifo_full = 37 -ge_dist_pc_ge_manager_busy = 38 -ge_dist_pc_req_stall_se0 = 39 -ge_dist_pc_req_stall_se1 = 40 -ge_dist_pc_req_stall_se2 = 41 -ge_dist_pc_req_stall_se3 = 42 -ge_dist_pc_req_stall_se4 = 43 -ge_dist_pc_req_stall_se5 = 44 -ge_dist_pc_req_stall_se6 = 45 -ge_dist_pc_req_stall_se7 = 46 -ge_dist_pc_space_zero = 47 -ge_dist_sclk_input_vld = 48 -ge_dist_reserved = 49 -ge_dist_wd_te11_busy = 50 -ge_dist_te11_starved = 51 -ge_dist_switch_mode_stall = 52 -ge_all_tf_eq = 53 -ge_all_tf2 = 54 -ge_all_tf3 = 55 -ge_all_tf4 = 56 -ge_all_tf5 = 57 -ge_all_tf6 = 58 -ge_se0_te11_starved_on_hs_done = 59 -ge_se1_te11_starved_on_hs_done = 60 -ge_se2_te11_starved_on_hs_done = 61 -ge_se3_te11_starved_on_hs_done = 62 -ge_se4_te11_starved_on_hs_done = 63 -ge_se5_te11_starved_on_hs_done = 64 -ge_se6_te11_starved_on_hs_done = 65 -ge_se7_te11_starved_on_hs_done = 66 -ge_dist_op_fifo_full_starve = 67 -ge_dist_hs_done_se0 = 68 -ge_dist_hs_done_se1 = 69 -ge_dist_hs_done_se2 = 70 -ge_dist_hs_done_se3 = 71 -ge_dist_hs_done_se4 = 72 -ge_dist_hs_done_se5 = 73 -ge_dist_hs_done_se6 = 74 -ge_dist_hs_done_se7 = 75 -ge_dist_hs_done_latency = 76 -ge_dist_distributer_busy = 77 -ge_tf_ret_data_stalling_hs_done = 78 -ge_num_of_no_dist_patches = 79 -ge_num_of_donut_dist_patches = 80 -ge_num_of_patch_dist_patches = 81 -ge_num_of_se_switches_due_to_patch_accum = 82 -ge_num_of_se_switches_due_to_donut = 83 -ge_num_of_se_switches_due_to_trap = 84 -ge_num_of_hs_alloc_events = 85 -ge_agm_gcr_req = 86 -ge_agm_gcr_tag_stall = 87 -ge_agm_gcr_crd_stall = 88 -ge_agm_gcr_stall = 89 -ge_agm_gcr_latency = 90 -ge_distclk_vld = 91 -GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' -GE2_SE_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_se_ds_prims', - 1: 'ge_se_es_thread_groups', - 2: 'ge_se_esvert_stalled_gsprim', - 3: 'ge_se_hs_tfm_stall', - 4: 'ge_se_hs_tgs_active_high_water_mark', - 5: 'ge_se_hs_thread_groups', - 6: 'ge_se_reused_es_indices', - 7: 'ge_se_sclk_ngg_vld', - 8: 'ge_se_sclk_te11_vld', - 9: 'ge_se_spi_esvert_eov', - 10: 'ge_se_spi_esvert_stalled', - 11: 'ge_se_spi_esvert_starved_busy', - 12: 'ge_se_spi_esvert_valid', - 13: 'ge_se_spi_gsprim_cont', - 14: 'ge_se_spi_gsprim_eov', - 15: 'ge_se_spi_gsprim_stalled', - 16: 'ge_se_spi_gsprim_starved_busy', - 17: 'ge_se_spi_gsprim_valid', - 18: 'ge_se_spi_gssubgrp_is_event', - 19: 'ge_se_spi_gssubgrp_send', - 20: 'ge_se_spi_hsvert_eov', - 21: 'ge_se_spi_hsvert_stalled', - 22: 'ge_se_spi_hsvert_starved_busy', - 23: 'ge_se_spi_hsvert_valid', - 24: 'ge_se_spi_hswave_is_event', - 25: 'ge_se_spi_hswave_send', - 26: 'ge_se_spi_lsvert_eov', - 27: 'ge_se_spi_lsvert_stalled', - 28: 'ge_se_spi_lsvert_starved_busy', - 29: 'ge_se_spi_lsvert_valid', - 30: 'ge_se_spi_hsvert_fifo_full_stall', - 31: 'ge_se_spi_tgrp_fifo_stall', - 32: 'ge_spi_hsgrp_spi_stall', - 33: 'ge_se_spi_gssubgrp_event_window_active', - 34: 'ge_se_hs_input_stall', - 35: 'ge_se_sending_vert_or_prim', - 36: 'ge_se_sclk_input_vld', - 37: 'ge_spi_lswave_fifo_full_stall', - 38: 'ge_spi_hswave_fifo_full_stall', - 39: 'ge_hs_tif_stall', - 40: 'ge_csb_spi_bp', - 41: 'ge_ngg_starving_for_pc_grant', - 42: 'ge_pa0_csb_eop', - 43: 'ge_pa1_csb_eop', - 44: 'ge_ngg_starved_idle', - 45: 'ge_gsprim_send', - 46: 'ge_esvert_send', - 47: 'ge_ngg_starved_after_work', - 48: 'ge_ngg_subgrp_fifo_stall', - 49: 'ge_ngg_ord_id_req_stall', - 50: 'ge_ngg_indx_bus_stall', - 51: 'ge_hs_stall_tfmm_fifo_full', - 52: 'ge_gs_issue_rtr_stalled', - 53: 'ge_gsprim_stalled_esvert', - 54: 'ge_gsthread_stalled', - 55: 'ge_te11_stall_prim_funnel', - 56: 'ge_te11_stall_vert_funnel', - 57: 'ge_ngg_attr_grp_alloc', - 58: 'ge_ngg_attr_discard_alloc', - 59: 'ge_ngg_pc_space_not_avail', - 60: 'ge_ngg_agm_req_stall', - 61: 'ge_ngg_spi_esvert_partial_eov', - 62: 'ge_ngg_spi_gsprim_partial_eov', - 63: 'ge_spi_gsgrp_valid', - 64: 'ge_ngg_attr_grp_latency', - 65: 'ge_ngg_reuse_prim_limit_hit', - 66: 'ge_ngg_reuse_vert_limit_hit', - 67: 'ge_te11_con_stall', - 68: 'ge_te11_compactor_starved', - 69: 'ge_ngg_stall_tess_off_tess_on', - 70: 'ge_ngg_stall_tess_on_tess_off', -} -ge_se_ds_prims = 0 -ge_se_es_thread_groups = 1 -ge_se_esvert_stalled_gsprim = 2 -ge_se_hs_tfm_stall = 3 -ge_se_hs_tgs_active_high_water_mark = 4 -ge_se_hs_thread_groups = 5 -ge_se_reused_es_indices = 6 -ge_se_sclk_ngg_vld = 7 -ge_se_sclk_te11_vld = 8 -ge_se_spi_esvert_eov = 9 -ge_se_spi_esvert_stalled = 10 -ge_se_spi_esvert_starved_busy = 11 -ge_se_spi_esvert_valid = 12 -ge_se_spi_gsprim_cont = 13 -ge_se_spi_gsprim_eov = 14 -ge_se_spi_gsprim_stalled = 15 -ge_se_spi_gsprim_starved_busy = 16 -ge_se_spi_gsprim_valid = 17 -ge_se_spi_gssubgrp_is_event = 18 -ge_se_spi_gssubgrp_send = 19 -ge_se_spi_hsvert_eov = 20 -ge_se_spi_hsvert_stalled = 21 -ge_se_spi_hsvert_starved_busy = 22 -ge_se_spi_hsvert_valid = 23 -ge_se_spi_hswave_is_event = 24 -ge_se_spi_hswave_send = 25 -ge_se_spi_lsvert_eov = 26 -ge_se_spi_lsvert_stalled = 27 -ge_se_spi_lsvert_starved_busy = 28 -ge_se_spi_lsvert_valid = 29 -ge_se_spi_hsvert_fifo_full_stall = 30 -ge_se_spi_tgrp_fifo_stall = 31 -ge_spi_hsgrp_spi_stall = 32 -ge_se_spi_gssubgrp_event_window_active = 33 -ge_se_hs_input_stall = 34 -ge_se_sending_vert_or_prim = 35 -ge_se_sclk_input_vld = 36 -ge_spi_lswave_fifo_full_stall = 37 -ge_spi_hswave_fifo_full_stall = 38 -ge_hs_tif_stall = 39 -ge_csb_spi_bp = 40 -ge_ngg_starving_for_pc_grant = 41 -ge_pa0_csb_eop = 42 -ge_pa1_csb_eop = 43 -ge_ngg_starved_idle = 44 -ge_gsprim_send = 45 -ge_esvert_send = 46 -ge_ngg_starved_after_work = 47 -ge_ngg_subgrp_fifo_stall = 48 -ge_ngg_ord_id_req_stall = 49 -ge_ngg_indx_bus_stall = 50 -ge_hs_stall_tfmm_fifo_full = 51 -ge_gs_issue_rtr_stalled = 52 -ge_gsprim_stalled_esvert = 53 -ge_gsthread_stalled = 54 -ge_te11_stall_prim_funnel = 55 -ge_te11_stall_vert_funnel = 56 -ge_ngg_attr_grp_alloc = 57 -ge_ngg_attr_discard_alloc = 58 -ge_ngg_pc_space_not_avail = 59 -ge_ngg_agm_req_stall = 60 -ge_ngg_spi_esvert_partial_eov = 61 -ge_ngg_spi_gsprim_partial_eov = 62 -ge_spi_gsgrp_valid = 63 -ge_ngg_attr_grp_latency = 64 -ge_ngg_reuse_prim_limit_hit = 65 -ge_ngg_reuse_vert_limit_hit = 66 -ge_te11_con_stall = 67 -ge_te11_compactor_starved = 68 -ge_ngg_stall_tess_off_tess_on = 69 -ge_ngg_stall_tess_on_tess_off = 70 -GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ONE' -VGT_DETECT_ONE__enumvalues = { - 0: 'ENABLE_TF1_OPT', - 1: 'DISABLE_TF1_OPT', -} -ENABLE_TF1_OPT = 0 -DISABLE_TF1_OPT = 1 -VGT_DETECT_ONE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ZERO' -VGT_DETECT_ZERO__enumvalues = { - 0: 'ENABLE_TF0_OPT', - 1: 'DISABLE_TF0_OPT', -} -ENABLE_TF0_OPT = 0 -DISABLE_TF0_OPT = 1 -VGT_DETECT_ZERO = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DIST_MODE' -VGT_DIST_MODE__enumvalues = { - 0: 'NO_DIST', - 1: 'PATCHES', - 2: 'DONUTS', - 3: 'TRAPEZOIDS', -} -NO_DIST = 0 -PATCHES = 1 -DONUTS = 2 -TRAPEZOIDS = 3 -VGT_DIST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_INDEX_SIZE' -VGT_DI_INDEX_SIZE__enumvalues = { - 0: 'DI_INDEX_SIZE_16_BIT', - 1: 'DI_INDEX_SIZE_32_BIT', - 2: 'DI_INDEX_SIZE_8_BIT', -} -DI_INDEX_SIZE_16_BIT = 0 -DI_INDEX_SIZE_32_BIT = 1 -DI_INDEX_SIZE_8_BIT = 2 -VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' -VGT_DI_MAJOR_MODE_SELECT__enumvalues = { - 0: 'DI_MAJOR_MODE_0', - 1: 'DI_MAJOR_MODE_1', -} -DI_MAJOR_MODE_0 = 0 -DI_MAJOR_MODE_1 = 1 -VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_PRIM_TYPE' -VGT_DI_PRIM_TYPE__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_2D_RECTANGLE', - 8: 'DI_PT_UNUSED_1', - 9: 'DI_PT_PATCH', - 10: 'DI_PT_LINELIST_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRILIST_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 14: 'DI_PT_UNUSED_3', - 15: 'DI_PT_UNUSED_4', - 16: 'DI_PT_UNUSED_5', - 17: 'DI_PT_RECTLIST', - 18: 'DI_PT_LINELOOP', - 19: 'DI_PT_QUADLIST', - 20: 'DI_PT_QUADSTRIP', - 21: 'DI_PT_POLYGON', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_2D_RECTANGLE = 7 -DI_PT_UNUSED_1 = 8 -DI_PT_PATCH = 9 -DI_PT_LINELIST_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRILIST_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_UNUSED_3 = 14 -DI_PT_UNUSED_4 = 15 -DI_PT_UNUSED_5 = 16 -DI_PT_RECTLIST = 17 -DI_PT_LINELOOP = 18 -DI_PT_QUADLIST = 19 -DI_PT_QUADSTRIP = 20 -DI_PT_POLYGON = 21 -VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_SOURCE_SELECT' -VGT_DI_SOURCE_SELECT__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_RESERVED', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_RESERVED = 3 -VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_BUF_TYPE' -VGT_DMA_BUF_TYPE__enumvalues = { - 0: 'VGT_DMA_BUF_MEM', - 1: 'VGT_DMA_BUF_RING', - 2: 'VGT_DMA_BUF_SETUP', - 3: 'VGT_DMA_PTR_UPDATE', -} -VGT_DMA_BUF_MEM = 0 -VGT_DMA_BUF_RING = 1 -VGT_DMA_BUF_SETUP = 2 -VGT_DMA_PTR_UPDATE = 3 -VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_SWAP_MODE' -VGT_DMA_SWAP_MODE__enumvalues = { - 0: 'VGT_DMA_SWAP_NONE', - 1: 'VGT_DMA_SWAP_16_BIT', - 2: 'VGT_DMA_SWAP_32_BIT', - 3: 'VGT_DMA_SWAP_WORD', -} -VGT_DMA_SWAP_NONE = 0 -VGT_DMA_SWAP_16_BIT = 1 -VGT_DMA_SWAP_32_BIT = 2 -VGT_DMA_SWAP_WORD = 3 -VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_EVENT_TYPE' -VGT_EVENT_TYPE__enumvalues = { - 0: 'Reserved_0x00', - 1: 'SAMPLE_STREAMOUTSTATS1', - 2: 'SAMPLE_STREAMOUTSTATS2', - 3: 'SAMPLE_STREAMOUTSTATS3', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'CS_PARTIAL_FLUSH', - 8: 'VGT_STREAMOUT_SYNC', - 9: 'Reserved_0x09', - 10: 'VGT_STREAMOUT_RESET', - 11: 'END_OF_PIPE_INCR_DE', - 12: 'END_OF_PIPE_IB_END', - 13: 'RST_PIX_CNT', - 14: 'BREAK_BATCH', - 15: 'VS_PARTIAL_FLUSH', - 16: 'PS_PARTIAL_FLUSH', - 17: 'FLUSH_HS_OUTPUT', - 18: 'FLUSH_DFSM', - 19: 'RESET_TO_LOWEST_VGT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'WAIT_SYNC', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 25: 'PIPELINESTAT_START', - 26: 'PIPELINESTAT_STOP', - 27: 'PERFCOUNTER_SAMPLE', - 28: 'FLUSH_ES_OUTPUT', - 29: 'BIN_CONF_OVERRIDE_CHECK', - 30: 'SAMPLE_PIPELINESTAT', - 31: 'SO_VGTSTREAMOUT_FLUSH', - 32: 'SAMPLE_STREAMOUTSTATS', - 33: 'RESET_VTX_CNT', - 34: 'BLOCK_CONTEXT_DONE', - 35: 'CS_CONTEXT_DONE', - 36: 'VGT_FLUSH', - 37: 'TGID_ROLLOVER', - 38: 'SQ_NON_EVENT', - 39: 'SC_SEND_DB_VPZ', - 40: 'BOTTOM_OF_PIPE_TS', - 41: 'FLUSH_SX_TS', - 42: 'DB_CACHE_FLUSH_AND_INV', - 43: 'FLUSH_AND_INV_DB_DATA_TS', - 44: 'FLUSH_AND_INV_DB_META', - 45: 'FLUSH_AND_INV_CB_DATA_TS', - 46: 'FLUSH_AND_INV_CB_META', - 47: 'CS_DONE', - 48: 'PS_DONE', - 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', - 50: 'SX_CB_RAT_ACK_REQUEST', - 51: 'THREAD_TRACE_START', - 52: 'THREAD_TRACE_STOP', - 53: 'THREAD_TRACE_MARKER', - 54: 'THREAD_TRACE_DRAW', - 55: 'THREAD_TRACE_FINISH', - 56: 'PIXEL_PIPE_STAT_CONTROL', - 57: 'PIXEL_PIPE_STAT_DUMP', - 58: 'PIXEL_PIPE_STAT_RESET', - 59: 'CONTEXT_SUSPEND', - 60: 'OFFCHIP_HS_DEALLOC', - 61: 'ENABLE_NGG_PIPELINE', - 62: 'ENABLE_LEGACY_PIPELINE', - 63: 'DRAW_DONE', -} -Reserved_0x00 = 0 -SAMPLE_STREAMOUTSTATS1 = 1 -SAMPLE_STREAMOUTSTATS2 = 2 -SAMPLE_STREAMOUTSTATS3 = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -CS_PARTIAL_FLUSH = 7 -VGT_STREAMOUT_SYNC = 8 -Reserved_0x09 = 9 -VGT_STREAMOUT_RESET = 10 -END_OF_PIPE_INCR_DE = 11 -END_OF_PIPE_IB_END = 12 -RST_PIX_CNT = 13 -BREAK_BATCH = 14 -VS_PARTIAL_FLUSH = 15 -PS_PARTIAL_FLUSH = 16 -FLUSH_HS_OUTPUT = 17 -FLUSH_DFSM = 18 -RESET_TO_LOWEST_VGT = 19 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -WAIT_SYNC = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -PIPELINESTAT_START = 25 -PIPELINESTAT_STOP = 26 -PERFCOUNTER_SAMPLE = 27 -FLUSH_ES_OUTPUT = 28 -BIN_CONF_OVERRIDE_CHECK = 29 -SAMPLE_PIPELINESTAT = 30 -SO_VGTSTREAMOUT_FLUSH = 31 -SAMPLE_STREAMOUTSTATS = 32 -RESET_VTX_CNT = 33 -BLOCK_CONTEXT_DONE = 34 -CS_CONTEXT_DONE = 35 -VGT_FLUSH = 36 -TGID_ROLLOVER = 37 -SQ_NON_EVENT = 38 -SC_SEND_DB_VPZ = 39 -BOTTOM_OF_PIPE_TS = 40 -FLUSH_SX_TS = 41 -DB_CACHE_FLUSH_AND_INV = 42 -FLUSH_AND_INV_DB_DATA_TS = 43 -FLUSH_AND_INV_DB_META = 44 -FLUSH_AND_INV_CB_DATA_TS = 45 -FLUSH_AND_INV_CB_META = 46 -CS_DONE = 47 -PS_DONE = 48 -FLUSH_AND_INV_CB_PIXEL_DATA = 49 -SX_CB_RAT_ACK_REQUEST = 50 -THREAD_TRACE_START = 51 -THREAD_TRACE_STOP = 52 -THREAD_TRACE_MARKER = 53 -THREAD_TRACE_DRAW = 54 -THREAD_TRACE_FINISH = 55 -PIXEL_PIPE_STAT_CONTROL = 56 -PIXEL_PIPE_STAT_DUMP = 57 -PIXEL_PIPE_STAT_RESET = 58 -CONTEXT_SUSPEND = 59 -OFFCHIP_HS_DEALLOC = 60 -ENABLE_NGG_PIPELINE = 61 -ENABLE_LEGACY_PIPELINE = 62 -DRAW_DONE = 63 -VGT_EVENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GROUP_CONV_SEL' -VGT_GROUP_CONV_SEL__enumvalues = { - 0: 'VGT_GRP_INDEX_16', - 1: 'VGT_GRP_INDEX_32', - 2: 'VGT_GRP_UINT_16', - 3: 'VGT_GRP_UINT_32', - 4: 'VGT_GRP_SINT_16', - 5: 'VGT_GRP_SINT_32', - 6: 'VGT_GRP_FLOAT_32', - 7: 'VGT_GRP_AUTO_PRIM', - 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', -} -VGT_GRP_INDEX_16 = 0 -VGT_GRP_INDEX_32 = 1 -VGT_GRP_UINT_16 = 2 -VGT_GRP_UINT_32 = 3 -VGT_GRP_SINT_16 = 4 -VGT_GRP_SINT_32 = 5 -VGT_GRP_FLOAT_32 = 6 -VGT_GRP_AUTO_PRIM = 7 -VGT_GRP_FIX_1_23_TO_FLOAT = 8 -VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_MODE_TYPE' -VGT_GS_MODE_TYPE__enumvalues = { - 0: 'GS_OFF', - 1: 'GS_SCENARIO_A', - 2: 'GS_SCENARIO_B', - 3: 'GS_SCENARIO_G', - 4: 'GS_SCENARIO_C', - 5: 'SPRITE_EN', -} -GS_OFF = 0 -GS_SCENARIO_A = 1 -GS_SCENARIO_B = 2 -GS_SCENARIO_G = 3 -GS_SCENARIO_C = 4 -SPRITE_EN = 5 -VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_OUTPRIM_TYPE' -VGT_GS_OUTPRIM_TYPE__enumvalues = { - 0: 'POINTLIST', - 1: 'LINESTRIP', - 2: 'TRISTRIP', - 3: 'RECT_2D', - 4: 'RECTLIST', -} -POINTLIST = 0 -LINESTRIP = 1 -TRISTRIP = 2 -RECT_2D = 3 -RECTLIST = 4 -VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_INDEX_TYPE_MODE' -VGT_INDEX_TYPE_MODE__enumvalues = { - 0: 'VGT_INDEX_16', - 1: 'VGT_INDEX_32', - 2: 'VGT_INDEX_8', -} -VGT_INDEX_16 = 0 -VGT_INDEX_32 = 1 -VGT_INDEX_8 = 2 -VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUTPATH_SELECT' -VGT_OUTPATH_SELECT__enumvalues = { - 0: 'VGT_OUTPATH_VTX_REUSE', - 1: 'VGT_OUTPATH_GS_BLOCK', - 2: 'VGT_OUTPATH_HS_BLOCK', - 3: 'VGT_OUTPATH_PRIM_GEN', - 4: 'VGT_OUTPATH_TE_PRIM_GEN', - 5: 'VGT_OUTPATH_TE_GS_BLOCK', - 6: 'VGT_OUTPATH_TE_OUTPUT', -} -VGT_OUTPATH_VTX_REUSE = 0 -VGT_OUTPATH_GS_BLOCK = 1 -VGT_OUTPATH_HS_BLOCK = 2 -VGT_OUTPATH_PRIM_GEN = 3 -VGT_OUTPATH_TE_PRIM_GEN = 4 -VGT_OUTPATH_TE_GS_BLOCK = 5 -VGT_OUTPATH_TE_OUTPUT = 6 -VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUT_PRIM_TYPE' -VGT_OUT_PRIM_TYPE__enumvalues = { - 0: 'VGT_OUT_POINT', - 1: 'VGT_OUT_LINE', - 2: 'VGT_OUT_TRI', - 3: 'VGT_OUT_RECT_V0', - 4: 'VGT_OUT_RECT_V1', - 5: 'VGT_OUT_RECT_V2', - 6: 'VGT_OUT_RECT_V3', - 7: 'VGT_OUT_2D_RECT', - 8: 'VGT_TE_QUAD', - 9: 'VGT_TE_PRIM_INDEX_LINE', - 10: 'VGT_TE_PRIM_INDEX_TRI', - 11: 'VGT_TE_PRIM_INDEX_QUAD', - 12: 'VGT_OUT_LINE_ADJ', - 13: 'VGT_OUT_TRI_ADJ', - 14: 'VGT_OUT_PATCH', -} -VGT_OUT_POINT = 0 -VGT_OUT_LINE = 1 -VGT_OUT_TRI = 2 -VGT_OUT_RECT_V0 = 3 -VGT_OUT_RECT_V1 = 4 -VGT_OUT_RECT_V2 = 5 -VGT_OUT_RECT_V3 = 6 -VGT_OUT_2D_RECT = 7 -VGT_TE_QUAD = 8 -VGT_TE_PRIM_INDEX_LINE = 9 -VGT_TE_PRIM_INDEX_TRI = 10 -VGT_TE_PRIM_INDEX_QUAD = 11 -VGT_OUT_LINE_ADJ = 12 -VGT_OUT_TRI_ADJ = 13 -VGT_OUT_PATCH = 14 -VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_RDREQ_POLICY' -VGT_RDREQ_POLICY__enumvalues = { - 0: 'VGT_POLICY_LRU', - 1: 'VGT_POLICY_STREAM', - 2: 'VGT_POLICY_BYPASS', -} -VGT_POLICY_LRU = 0 -VGT_POLICY_STREAM = 1 -VGT_POLICY_BYPASS = 2 -VGT_RDREQ_POLICY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_ES_EN' -VGT_STAGES_ES_EN__enumvalues = { - 0: 'ES_STAGE_OFF', - 1: 'ES_STAGE_DS', - 2: 'ES_STAGE_REAL', - 3: 'RESERVED_ES', -} -ES_STAGE_OFF = 0 -ES_STAGE_DS = 1 -ES_STAGE_REAL = 2 -RESERVED_ES = 3 -VGT_STAGES_ES_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_GS_EN' -VGT_STAGES_GS_EN__enumvalues = { - 0: 'GS_STAGE_OFF', - 1: 'GS_STAGE_ON', -} -GS_STAGE_OFF = 0 -GS_STAGE_ON = 1 -VGT_STAGES_GS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_HS_EN' -VGT_STAGES_HS_EN__enumvalues = { - 0: 'HS_STAGE_OFF', - 1: 'HS_STAGE_ON', -} -HS_STAGE_OFF = 0 -HS_STAGE_ON = 1 -VGT_STAGES_HS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_LS_EN' -VGT_STAGES_LS_EN__enumvalues = { - 0: 'LS_STAGE_OFF', - 1: 'LS_STAGE_ON', - 2: 'CS_STAGE_ON', - 3: 'RESERVED_LS', -} -LS_STAGE_OFF = 0 -LS_STAGE_ON = 1 -CS_STAGE_ON = 2 -RESERVED_LS = 3 -VGT_STAGES_LS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_VS_EN' -VGT_STAGES_VS_EN__enumvalues = { - 0: 'VS_STAGE_REAL', - 1: 'VS_STAGE_DS', - 2: 'VS_STAGE_COPY_SHADER', - 3: 'RESERVED_VS', -} -VS_STAGE_REAL = 0 -VS_STAGE_DS = 1 -VS_STAGE_COPY_SHADER = 2 -RESERVED_VS = 3 -VGT_STAGES_VS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_PARTITION' -VGT_TESS_PARTITION__enumvalues = { - 0: 'PART_INTEGER', - 1: 'PART_POW2', - 2: 'PART_FRAC_ODD', - 3: 'PART_FRAC_EVEN', -} -PART_INTEGER = 0 -PART_POW2 = 1 -PART_FRAC_ODD = 2 -PART_FRAC_EVEN = 3 -VGT_TESS_PARTITION = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TOPOLOGY' -VGT_TESS_TOPOLOGY__enumvalues = { - 0: 'OUTPUT_POINT', - 1: 'OUTPUT_LINE', - 2: 'OUTPUT_TRIANGLE_CW', - 3: 'OUTPUT_TRIANGLE_CCW', -} -OUTPUT_POINT = 0 -OUTPUT_LINE = 1 -OUTPUT_TRIANGLE_CW = 2 -OUTPUT_TRIANGLE_CCW = 3 -VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TYPE' -VGT_TESS_TYPE__enumvalues = { - 0: 'TESS_ISOLINE', - 1: 'TESS_TRIANGLE', - 2: 'TESS_QUAD', -} -TESS_ISOLINE = 0 -TESS_TRIANGLE = 1 -TESS_QUAD = 2 -VGT_TESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_REG_XFER' -WD_IA_DRAW_REG_XFER__enumvalues = { - 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', -} -WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 -WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 -WD_IA_DRAW_REG_XFER_GE_CNTL = 3 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6 -WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7 -WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8 -WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_SOURCE' -WD_IA_DRAW_SOURCE__enumvalues = { - 0: 'WD_IA_DRAW_SOURCE_DMA', - 1: 'WD_IA_DRAW_SOURCE_IMMD', - 2: 'WD_IA_DRAW_SOURCE_AUTO', - 3: 'WD_IA_DRAW_SOURCE_OPAQ', -} -WD_IA_DRAW_SOURCE_DMA = 0 -WD_IA_DRAW_SOURCE_IMMD = 1 -WD_IA_DRAW_SOURCE_AUTO = 2 -WD_IA_DRAW_SOURCE_OPAQ = 3 -WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_TYPE' -WD_IA_DRAW_TYPE__enumvalues = { - 0: 'WD_IA_DRAW_TYPE_DI_MM0', - 1: 'WD_IA_DRAW_TYPE_REG_XFER', - 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', - 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 4: 'WD_IA_DRAW_TYPE_MIN_INDX', - 5: 'WD_IA_DRAW_TYPE_MAX_INDX', - 6: 'WD_IA_DRAW_TYPE_INDX_OFF', - 7: 'WD_IA_DRAW_TYPE_IMM_DATA', -} -WD_IA_DRAW_TYPE_DI_MM0 = 0 -WD_IA_DRAW_TYPE_REG_XFER = 1 -WD_IA_DRAW_TYPE_EVENT_INIT = 2 -WD_IA_DRAW_TYPE_EVENT_ADDR = 3 -WD_IA_DRAW_TYPE_MIN_INDX = 4 -WD_IA_DRAW_TYPE_MAX_INDX = 5 -WD_IA_DRAW_TYPE_INDX_OFF = 6 -WD_IA_DRAW_TYPE_IMM_DATA = 7 -WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GB_EDC_DED_MODE' -GB_EDC_DED_MODE__enumvalues = { - 0: 'GB_EDC_DED_MODE_LOG', - 1: 'GB_EDC_DED_MODE_HALT', - 2: 'GB_EDC_DED_MODE_INT_HALT', -} -GB_EDC_DED_MODE_LOG = 0 -GB_EDC_DED_MODE_HALT = 1 -GB_EDC_DED_MODE_INT_HALT = 2 -GB_EDC_DED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CHA_PERF_SEL' -CHA_PERF_SEL__enumvalues = { - 0: 'CHA_PERF_SEL_BUSY', - 1: 'CHA_PERF_SEL_STALL_CHC0', - 2: 'CHA_PERF_SEL_STALL_CHC1', - 3: 'CHA_PERF_SEL_STALL_CHC2', - 4: 'CHA_PERF_SEL_STALL_CHC3', - 5: 'CHA_PERF_SEL_STALL_CHC4', - 6: 'CHA_PERF_SEL_STALL_CHC5', - 7: 'CHA_PERF_SEL_REQUEST_CHC0', - 8: 'CHA_PERF_SEL_REQUEST_CHC1', - 9: 'CHA_PERF_SEL_REQUEST_CHC2', - 10: 'CHA_PERF_SEL_REQUEST_CHC3', - 11: 'CHA_PERF_SEL_REQUEST_CHC4', - 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', - 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', - 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', - 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', - 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 32: 'CHA_PERF_SEL_ARB_REQUESTS', - 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', - 39: 'CHA_PERF_SEL_CYCLE', -} -CHA_PERF_SEL_BUSY = 0 -CHA_PERF_SEL_STALL_CHC0 = 1 -CHA_PERF_SEL_STALL_CHC1 = 2 -CHA_PERF_SEL_STALL_CHC2 = 3 -CHA_PERF_SEL_STALL_CHC3 = 4 -CHA_PERF_SEL_STALL_CHC4 = 5 -CHA_PERF_SEL_STALL_CHC5 = 6 -CHA_PERF_SEL_REQUEST_CHC0 = 7 -CHA_PERF_SEL_REQUEST_CHC1 = 8 -CHA_PERF_SEL_REQUEST_CHC2 = 9 -CHA_PERF_SEL_REQUEST_CHC3 = 10 -CHA_PERF_SEL_REQUEST_CHC4 = 11 -CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 -CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 -CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 -CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 -CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 -CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 -CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 -CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 -CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 -CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 -CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 -CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 -CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 -CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 -CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 -CHA_PERF_SEL_ARB_REQUESTS = 32 -CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 -CHA_PERF_SEL_CYCLE = 39 -CHA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHCG_PERF_SEL' -CHCG_PERF_SEL__enumvalues = { - 0: 'CHCG_PERF_SEL_CYCLE', - 1: 'CHCG_PERF_SEL_BUSY', - 2: 'CHCG_PERF_SEL_STARVE', - 3: 'CHCG_PERF_SEL_ARB_RET_LEVEL', - 4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'CHCG_PERF_SEL_REQ', - 7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'CHCG_PERF_SEL_REQ_NOP_ACK', - 10: 'CHCG_PERF_SEL_REQ_NOP_RTN0', - 11: 'CHCG_PERF_SEL_REQ_READ', - 12: 'CHCG_PERF_SEL_REQ_READ_128B', - 13: 'CHCG_PERF_SEL_REQ_READ_32B', - 14: 'CHCG_PERF_SEL_REQ_READ_64B', - 15: 'CHCG_PERF_SEL_REQ_WRITE', - 16: 'CHCG_PERF_SEL_REQ_WRITE_32B', - 17: 'CHCG_PERF_SEL_REQ_WRITE_64B', - 18: 'CHCG_PERF_SEL_STALL_GUS_GL1', - 19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL', - 20: 'CHCG_PERF_SEL_REQ_CLIENT0', - 21: 'CHCG_PERF_SEL_REQ_CLIENT1', - 22: 'CHCG_PERF_SEL_REQ_CLIENT2', - 23: 'CHCG_PERF_SEL_REQ_CLIENT3', - 24: 'CHCG_PERF_SEL_REQ_CLIENT4', - 25: 'CHCG_PERF_SEL_REQ_CLIENT5', - 26: 'CHCG_PERF_SEL_REQ_CLIENT6', - 27: 'CHCG_PERF_SEL_REQ_CLIENT7', - 28: 'CHCG_PERF_SEL_REQ_CLIENT8', - 29: 'CHCG_PERF_SEL_REQ_CLIENT9', - 30: 'CHCG_PERF_SEL_REQ_CLIENT10', - 31: 'CHCG_PERF_SEL_REQ_CLIENT11', - 32: 'CHCG_PERF_SEL_REQ_CLIENT12', - 33: 'CHCG_PERF_SEL_REQ_CLIENT13', - 34: 'CHCG_PERF_SEL_REQ_CLIENT14', - 35: 'CHCG_PERF_SEL_REQ_CLIENT15', - 36: 'CHCG_PERF_SEL_REQ_CLIENT16', - 37: 'CHCG_PERF_SEL_REQ_CLIENT17', - 38: 'CHCG_PERF_SEL_REQ_CLIENT18', - 39: 'CHCG_PERF_SEL_REQ_CLIENT19', - 40: 'CHCG_PERF_SEL_REQ_CLIENT20', - 41: 'CHCG_PERF_SEL_REQ_CLIENT21', - 42: 'CHCG_PERF_SEL_REQ_CLIENT22', - 43: 'CHCG_PERF_SEL_REQ_CLIENT23', -} -CHCG_PERF_SEL_CYCLE = 0 -CHCG_PERF_SEL_BUSY = 1 -CHCG_PERF_SEL_STARVE = 2 -CHCG_PERF_SEL_ARB_RET_LEVEL = 3 -CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -CHCG_PERF_SEL_REQ = 6 -CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -CHCG_PERF_SEL_REQ_NOP_ACK = 9 -CHCG_PERF_SEL_REQ_NOP_RTN0 = 10 -CHCG_PERF_SEL_REQ_READ = 11 -CHCG_PERF_SEL_REQ_READ_128B = 12 -CHCG_PERF_SEL_REQ_READ_32B = 13 -CHCG_PERF_SEL_REQ_READ_64B = 14 -CHCG_PERF_SEL_REQ_WRITE = 15 -CHCG_PERF_SEL_REQ_WRITE_32B = 16 -CHCG_PERF_SEL_REQ_WRITE_64B = 17 -CHCG_PERF_SEL_STALL_GUS_GL1 = 18 -CHCG_PERF_SEL_STALL_BUFFER_FULL = 19 -CHCG_PERF_SEL_REQ_CLIENT0 = 20 -CHCG_PERF_SEL_REQ_CLIENT1 = 21 -CHCG_PERF_SEL_REQ_CLIENT2 = 22 -CHCG_PERF_SEL_REQ_CLIENT3 = 23 -CHCG_PERF_SEL_REQ_CLIENT4 = 24 -CHCG_PERF_SEL_REQ_CLIENT5 = 25 -CHCG_PERF_SEL_REQ_CLIENT6 = 26 -CHCG_PERF_SEL_REQ_CLIENT7 = 27 -CHCG_PERF_SEL_REQ_CLIENT8 = 28 -CHCG_PERF_SEL_REQ_CLIENT9 = 29 -CHCG_PERF_SEL_REQ_CLIENT10 = 30 -CHCG_PERF_SEL_REQ_CLIENT11 = 31 -CHCG_PERF_SEL_REQ_CLIENT12 = 32 -CHCG_PERF_SEL_REQ_CLIENT13 = 33 -CHCG_PERF_SEL_REQ_CLIENT14 = 34 -CHCG_PERF_SEL_REQ_CLIENT15 = 35 -CHCG_PERF_SEL_REQ_CLIENT16 = 36 -CHCG_PERF_SEL_REQ_CLIENT17 = 37 -CHCG_PERF_SEL_REQ_CLIENT18 = 38 -CHCG_PERF_SEL_REQ_CLIENT19 = 39 -CHCG_PERF_SEL_REQ_CLIENT20 = 40 -CHCG_PERF_SEL_REQ_CLIENT21 = 41 -CHCG_PERF_SEL_REQ_CLIENT22 = 42 -CHCG_PERF_SEL_REQ_CLIENT23 = 43 -CHCG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHC_PERF_SEL' -CHC_PERF_SEL__enumvalues = { - 0: 'CHC_PERF_SEL_CYCLE', - 1: 'CHC_PERF_SEL_BUSY', - 2: 'CHC_PERF_SEL_STARVE', - 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', - 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'CHC_PERF_SEL_REQ', - 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'CHC_PERF_SEL_REQ_NOP_ACK', - 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', - 11: 'CHC_PERF_SEL_REQ_READ', - 12: 'CHC_PERF_SEL_REQ_READ_128B', - 13: 'CHC_PERF_SEL_REQ_READ_32B', - 14: 'CHC_PERF_SEL_REQ_READ_64B', - 15: 'CHC_PERF_SEL_REQ_WRITE', - 16: 'CHC_PERF_SEL_REQ_WRITE_32B', - 17: 'CHC_PERF_SEL_REQ_WRITE_64B', - 18: 'CHC_PERF_SEL_STALL_GL2_GL1', - 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', - 20: 'CHC_PERF_SEL_REQ_CLIENT0', - 21: 'CHC_PERF_SEL_REQ_CLIENT1', - 22: 'CHC_PERF_SEL_REQ_CLIENT2', - 23: 'CHC_PERF_SEL_REQ_CLIENT3', - 24: 'CHC_PERF_SEL_REQ_CLIENT4', - 25: 'CHC_PERF_SEL_REQ_CLIENT5', - 26: 'CHC_PERF_SEL_REQ_CLIENT6', - 27: 'CHC_PERF_SEL_REQ_CLIENT7', - 28: 'CHC_PERF_SEL_REQ_CLIENT8', - 29: 'CHC_PERF_SEL_REQ_CLIENT9', - 30: 'CHC_PERF_SEL_REQ_CLIENT10', - 31: 'CHC_PERF_SEL_REQ_CLIENT11', - 32: 'CHC_PERF_SEL_REQ_CLIENT12', - 33: 'CHC_PERF_SEL_REQ_CLIENT13', - 34: 'CHC_PERF_SEL_REQ_CLIENT14', - 35: 'CHC_PERF_SEL_REQ_CLIENT15', - 36: 'CHC_PERF_SEL_REQ_CLIENT16', - 37: 'CHC_PERF_SEL_REQ_CLIENT17', - 38: 'CHC_PERF_SEL_REQ_CLIENT18', - 39: 'CHC_PERF_SEL_REQ_CLIENT19', - 40: 'CHC_PERF_SEL_REQ_CLIENT20', - 41: 'CHC_PERF_SEL_REQ_CLIENT21', - 42: 'CHC_PERF_SEL_REQ_CLIENT22', - 43: 'CHC_PERF_SEL_REQ_CLIENT23', -} -CHC_PERF_SEL_CYCLE = 0 -CHC_PERF_SEL_BUSY = 1 -CHC_PERF_SEL_STARVE = 2 -CHC_PERF_SEL_ARB_RET_LEVEL = 3 -CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -CHC_PERF_SEL_REQ = 6 -CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -CHC_PERF_SEL_REQ_NOP_ACK = 9 -CHC_PERF_SEL_REQ_NOP_RTN0 = 10 -CHC_PERF_SEL_REQ_READ = 11 -CHC_PERF_SEL_REQ_READ_128B = 12 -CHC_PERF_SEL_REQ_READ_32B = 13 -CHC_PERF_SEL_REQ_READ_64B = 14 -CHC_PERF_SEL_REQ_WRITE = 15 -CHC_PERF_SEL_REQ_WRITE_32B = 16 -CHC_PERF_SEL_REQ_WRITE_64B = 17 -CHC_PERF_SEL_STALL_GL2_GL1 = 18 -CHC_PERF_SEL_STALL_BUFFER_FULL = 19 -CHC_PERF_SEL_REQ_CLIENT0 = 20 -CHC_PERF_SEL_REQ_CLIENT1 = 21 -CHC_PERF_SEL_REQ_CLIENT2 = 22 -CHC_PERF_SEL_REQ_CLIENT3 = 23 -CHC_PERF_SEL_REQ_CLIENT4 = 24 -CHC_PERF_SEL_REQ_CLIENT5 = 25 -CHC_PERF_SEL_REQ_CLIENT6 = 26 -CHC_PERF_SEL_REQ_CLIENT7 = 27 -CHC_PERF_SEL_REQ_CLIENT8 = 28 -CHC_PERF_SEL_REQ_CLIENT9 = 29 -CHC_PERF_SEL_REQ_CLIENT10 = 30 -CHC_PERF_SEL_REQ_CLIENT11 = 31 -CHC_PERF_SEL_REQ_CLIENT12 = 32 -CHC_PERF_SEL_REQ_CLIENT13 = 33 -CHC_PERF_SEL_REQ_CLIENT14 = 34 -CHC_PERF_SEL_REQ_CLIENT15 = 35 -CHC_PERF_SEL_REQ_CLIENT16 = 36 -CHC_PERF_SEL_REQ_CLIENT17 = 37 -CHC_PERF_SEL_REQ_CLIENT18 = 38 -CHC_PERF_SEL_REQ_CLIENT19 = 39 -CHC_PERF_SEL_REQ_CLIENT20 = 40 -CHC_PERF_SEL_REQ_CLIENT21 = 41 -CHC_PERF_SEL_REQ_CLIENT22 = 42 -CHC_PERF_SEL_REQ_CLIENT23 = 43 -CHC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1A_PERF_SEL' -GL1A_PERF_SEL__enumvalues = { - 0: 'GL1A_PERF_SEL_BUSY', - 1: 'GL1A_PERF_SEL_STALL_GL1C0', - 2: 'GL1A_PERF_SEL_STALL_GL1C1', - 3: 'GL1A_PERF_SEL_STALL_GL1C2', - 4: 'GL1A_PERF_SEL_STALL_GL1C3', - 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', - 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', - 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', - 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', - 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', - 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', - 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', - 17: 'GL1A_PERF_SEL_ARB_REQUESTS', - 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 23: 'GL1A_PERF_SEL_CYCLE', -} -GL1A_PERF_SEL_BUSY = 0 -GL1A_PERF_SEL_STALL_GL1C0 = 1 -GL1A_PERF_SEL_STALL_GL1C1 = 2 -GL1A_PERF_SEL_STALL_GL1C2 = 3 -GL1A_PERF_SEL_STALL_GL1C3 = 4 -GL1A_PERF_SEL_REQUEST_GL1C0 = 5 -GL1A_PERF_SEL_REQUEST_GL1C1 = 6 -GL1A_PERF_SEL_REQUEST_GL1C2 = 7 -GL1A_PERF_SEL_REQUEST_GL1C3 = 8 -GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 -GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 -GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 -GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 -GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 -GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 -GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 -GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 -GL1A_PERF_SEL_ARB_REQUESTS = 17 -GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 -GL1A_PERF_SEL_CYCLE = 23 -GL1A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1C_PERF_SEL' -GL1C_PERF_SEL__enumvalues = { - 0: 'GL1C_PERF_SEL_CYCLE', - 1: 'GL1C_PERF_SEL_BUSY', - 2: 'GL1C_PERF_SEL_STARVE', - 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 4: 'GL1C_PERF_SEL_GL2_REQ_READ', - 5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B', - 6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B', - 7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B', - 8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 9: 'GL1C_PERF_SEL_GL2_REQ_WRITE', - 10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', - 11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', - 12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', - 14: 'GL1C_PERF_SEL_REQ', - 15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', - 16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 17: 'GL1C_PERF_SEL_REQ_SHADER_INV', - 18: 'GL1C_PERF_SEL_REQ_MISS', - 19: 'GL1C_PERF_SEL_REQ_NOP_ACK', - 20: 'GL1C_PERF_SEL_REQ_NOP_RTN0', - 21: 'GL1C_PERF_SEL_REQ_READ', - 22: 'GL1C_PERF_SEL_REQ_READ_128B', - 23: 'GL1C_PERF_SEL_REQ_READ_32B', - 24: 'GL1C_PERF_SEL_REQ_READ_64B', - 25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', - 26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', - 27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', - 28: 'GL1C_PERF_SEL_REQ_WRITE', - 29: 'GL1C_PERF_SEL_REQ_WRITE_32B', - 30: 'GL1C_PERF_SEL_REQ_WRITE_64B', - 31: 'GL1C_PERF_SEL_STALL_GL2_GL1', - 32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL', - 33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', - 34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', - 35: 'GL1C_PERF_SEL_STALL_GCR_INV', - 36: 'GL1C_PERF_SEL_STALL_VM', - 37: 'GL1C_PERF_SEL_REQ_CLIENT0', - 38: 'GL1C_PERF_SEL_REQ_CLIENT1', - 39: 'GL1C_PERF_SEL_REQ_CLIENT2', - 40: 'GL1C_PERF_SEL_REQ_CLIENT3', - 41: 'GL1C_PERF_SEL_REQ_CLIENT4', - 42: 'GL1C_PERF_SEL_REQ_CLIENT5', - 43: 'GL1C_PERF_SEL_REQ_CLIENT6', - 44: 'GL1C_PERF_SEL_REQ_CLIENT7', - 45: 'GL1C_PERF_SEL_REQ_CLIENT8', - 46: 'GL1C_PERF_SEL_REQ_CLIENT9', - 47: 'GL1C_PERF_SEL_REQ_CLIENT10', - 48: 'GL1C_PERF_SEL_REQ_CLIENT11', - 49: 'GL1C_PERF_SEL_REQ_CLIENT12', - 50: 'GL1C_PERF_SEL_REQ_CLIENT13', - 51: 'GL1C_PERF_SEL_REQ_CLIENT14', - 52: 'GL1C_PERF_SEL_REQ_CLIENT15', - 53: 'GL1C_PERF_SEL_REQ_CLIENT16', - 54: 'GL1C_PERF_SEL_REQ_CLIENT17', - 55: 'GL1C_PERF_SEL_REQ_CLIENT18', - 56: 'GL1C_PERF_SEL_REQ_CLIENT19', - 57: 'GL1C_PERF_SEL_REQ_CLIENT20', - 58: 'GL1C_PERF_SEL_REQ_CLIENT21', - 59: 'GL1C_PERF_SEL_REQ_CLIENT22', - 60: 'GL1C_PERF_SEL_REQ_CLIENT23', - 61: 'GL1C_PERF_SEL_REQ_CLIENT24', - 62: 'GL1C_PERF_SEL_REQ_CLIENT25', - 63: 'GL1C_PERF_SEL_REQ_CLIENT26', - 64: 'GL1C_PERF_SEL_REQ_CLIENT27', - 65: 'GL1C_PERF_SEL_UTCL0_REQUEST', - 66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', -} -GL1C_PERF_SEL_CYCLE = 0 -GL1C_PERF_SEL_BUSY = 1 -GL1C_PERF_SEL_STARVE = 2 -GL1C_PERF_SEL_ARB_RET_LEVEL = 3 -GL1C_PERF_SEL_GL2_REQ_READ = 4 -GL1C_PERF_SEL_GL2_REQ_READ_128B = 5 -GL1C_PERF_SEL_GL2_REQ_READ_32B = 6 -GL1C_PERF_SEL_GL2_REQ_READ_64B = 7 -GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8 -GL1C_PERF_SEL_GL2_REQ_WRITE = 9 -GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10 -GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11 -GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12 -GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13 -GL1C_PERF_SEL_REQ = 14 -GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15 -GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16 -GL1C_PERF_SEL_REQ_SHADER_INV = 17 -GL1C_PERF_SEL_REQ_MISS = 18 -GL1C_PERF_SEL_REQ_NOP_ACK = 19 -GL1C_PERF_SEL_REQ_NOP_RTN0 = 20 -GL1C_PERF_SEL_REQ_READ = 21 -GL1C_PERF_SEL_REQ_READ_128B = 22 -GL1C_PERF_SEL_REQ_READ_32B = 23 -GL1C_PERF_SEL_REQ_READ_64B = 24 -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25 -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26 -GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27 -GL1C_PERF_SEL_REQ_WRITE = 28 -GL1C_PERF_SEL_REQ_WRITE_32B = 29 -GL1C_PERF_SEL_REQ_WRITE_64B = 30 -GL1C_PERF_SEL_STALL_GL2_GL1 = 31 -GL1C_PERF_SEL_STALL_LFIFO_FULL = 32 -GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33 -GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34 -GL1C_PERF_SEL_STALL_GCR_INV = 35 -GL1C_PERF_SEL_STALL_VM = 36 -GL1C_PERF_SEL_REQ_CLIENT0 = 37 -GL1C_PERF_SEL_REQ_CLIENT1 = 38 -GL1C_PERF_SEL_REQ_CLIENT2 = 39 -GL1C_PERF_SEL_REQ_CLIENT3 = 40 -GL1C_PERF_SEL_REQ_CLIENT4 = 41 -GL1C_PERF_SEL_REQ_CLIENT5 = 42 -GL1C_PERF_SEL_REQ_CLIENT6 = 43 -GL1C_PERF_SEL_REQ_CLIENT7 = 44 -GL1C_PERF_SEL_REQ_CLIENT8 = 45 -GL1C_PERF_SEL_REQ_CLIENT9 = 46 -GL1C_PERF_SEL_REQ_CLIENT10 = 47 -GL1C_PERF_SEL_REQ_CLIENT11 = 48 -GL1C_PERF_SEL_REQ_CLIENT12 = 49 -GL1C_PERF_SEL_REQ_CLIENT13 = 50 -GL1C_PERF_SEL_REQ_CLIENT14 = 51 -GL1C_PERF_SEL_REQ_CLIENT15 = 52 -GL1C_PERF_SEL_REQ_CLIENT16 = 53 -GL1C_PERF_SEL_REQ_CLIENT17 = 54 -GL1C_PERF_SEL_REQ_CLIENT18 = 55 -GL1C_PERF_SEL_REQ_CLIENT19 = 56 -GL1C_PERF_SEL_REQ_CLIENT20 = 57 -GL1C_PERF_SEL_REQ_CLIENT21 = 58 -GL1C_PERF_SEL_REQ_CLIENT22 = 59 -GL1C_PERF_SEL_REQ_CLIENT23 = 60 -GL1C_PERF_SEL_REQ_CLIENT24 = 61 -GL1C_PERF_SEL_REQ_CLIENT25 = 62 -GL1C_PERF_SEL_REQ_CLIENT26 = 63 -GL1C_PERF_SEL_REQ_CLIENT27 = 64 -GL1C_PERF_SEL_UTCL0_REQUEST = 65 -GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66 -GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67 -GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68 -GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69 -GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70 -GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71 -GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72 -GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73 -GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74 -GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75 -GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76 -GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77 -GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78 -GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79 -GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83 -GL1C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1H_REQ_PERF_SEL' -GL1H_REQ_PERF_SEL__enumvalues = { - 0: 'GL1H_REQ_PERF_SEL_BUSY', - 1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0', - 2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1', - 3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', - 4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', - 5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', - 6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', - 7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', - 8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', - 9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', - 10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', - 11: 'GL1H_REQ_PERF_SEL_CYCLE', -} -GL1H_REQ_PERF_SEL_BUSY = 0 -GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1 -GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2 -GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3 -GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4 -GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5 -GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6 -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7 -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8 -GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9 -GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10 -GL1H_REQ_PERF_SEL_CYCLE = 11 -GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TA_PERFCOUNT_SEL' -TA_PERFCOUNT_SEL__enumvalues = { - 0: 'TA_PERF_SEL_NULL', - 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 7: 'TA_PERF_SEL_gradient_busy', - 8: 'TA_PERF_SEL_gradient_fifo_busy', - 9: 'TA_PERF_SEL_lod_busy', - 10: 'TA_PERF_SEL_lod_fifo_busy', - 11: 'TA_PERF_SEL_addresser_busy', - 12: 'TA_PERF_SEL_addresser_fifo_busy', - 13: 'TA_PERF_SEL_aligner_busy', - 14: 'TA_PERF_SEL_write_path_busy', - 15: 'TA_PERF_SEL_ta_busy', - 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', - 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', - 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', - 32: 'TA_PERF_SEL_total_wavefronts', - 33: 'TA_PERF_SEL_gradient_cycles', - 34: 'TA_PERF_SEL_walker_cycles', - 35: 'TA_PERF_SEL_aligner_cycles', - 36: 'TA_PERF_SEL_image_wavefronts', - 37: 'TA_PERF_SEL_image_read_wavefronts', - 38: 'TA_PERF_SEL_image_store_wavefronts', - 39: 'TA_PERF_SEL_image_atomic_wavefronts', - 40: 'TA_PERF_SEL_image_sampler_total_cycles', - 41: 'TA_PERF_SEL_image_nosampler_total_cycles', - 42: 'TA_PERF_SEL_flat_total_cycles', - 43: 'TA_PERF_SEL_bvh_total_cycles', - 44: 'TA_PERF_SEL_buffer_wavefronts', - 45: 'TA_PERF_SEL_buffer_load_wavefronts', - 46: 'TA_PERF_SEL_buffer_store_wavefronts', - 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', - 49: 'TA_PERF_SEL_buffer_total_cycles', - 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 52: 'TA_PERF_SEL_buffer_has_index_instructions', - 53: 'TA_PERF_SEL_buffer_has_offset_instructions', - 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 56: 'TA_PERF_SEL_image_sampler_wavefronts', - 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 58: 'TA_PERF_SEL_addresser_stalled_cycles', - 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 60: 'TA_PERF_SEL_aniso_stalled_cycles', - 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 62: 'TA_PERF_SEL_deriv_stalled_cycles', - 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 64: 'TA_PERF_SEL_color_1_cycle_quads', - 65: 'TA_PERF_SEL_color_2_cycle_quads', - 66: 'TA_PERF_SEL_color_3_cycle_quads', - 68: 'TA_PERF_SEL_mip_1_cycle_quads', - 69: 'TA_PERF_SEL_mip_2_cycle_quads', - 70: 'TA_PERF_SEL_vol_1_cycle_quads', - 71: 'TA_PERF_SEL_vol_2_cycle_quads', - 72: 'TA_PERF_SEL_sampler_op_quads', - 73: 'TA_PERF_SEL_mipmap_lod_0_samples', - 74: 'TA_PERF_SEL_mipmap_lod_1_samples', - 75: 'TA_PERF_SEL_mipmap_lod_2_samples', - 76: 'TA_PERF_SEL_mipmap_lod_3_samples', - 77: 'TA_PERF_SEL_mipmap_lod_4_samples', - 78: 'TA_PERF_SEL_mipmap_lod_5_samples', - 79: 'TA_PERF_SEL_mipmap_lod_6_samples', - 80: 'TA_PERF_SEL_mipmap_lod_7_samples', - 81: 'TA_PERF_SEL_mipmap_lod_8_samples', - 82: 'TA_PERF_SEL_mipmap_lod_9_samples', - 83: 'TA_PERF_SEL_mipmap_lod_10_samples', - 84: 'TA_PERF_SEL_mipmap_lod_11_samples', - 85: 'TA_PERF_SEL_mipmap_lod_12_samples', - 86: 'TA_PERF_SEL_mipmap_lod_13_samples', - 87: 'TA_PERF_SEL_mipmap_lod_14_samples', - 88: 'TA_PERF_SEL_mipmap_invalid_samples', - 89: 'TA_PERF_SEL_aniso_1_cycle_quads', - 90: 'TA_PERF_SEL_aniso_2_cycle_quads', - 91: 'TA_PERF_SEL_aniso_4_cycle_quads', - 92: 'TA_PERF_SEL_aniso_6_cycle_quads', - 93: 'TA_PERF_SEL_aniso_8_cycle_quads', - 94: 'TA_PERF_SEL_aniso_10_cycle_quads', - 95: 'TA_PERF_SEL_aniso_12_cycle_quads', - 96: 'TA_PERF_SEL_aniso_14_cycle_quads', - 97: 'TA_PERF_SEL_aniso_16_cycle_quads', - 98: 'TA_PERF_SEL_store_write_data_input_cycles', - 99: 'TA_PERF_SEL_store_write_data_output_cycles', - 100: 'TA_PERF_SEL_flat_wavefronts', - 101: 'TA_PERF_SEL_flat_load_wavefronts', - 102: 'TA_PERF_SEL_flat_store_wavefronts', - 103: 'TA_PERF_SEL_flat_atomic_wavefronts', - 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 105: 'TA_PERF_SEL_register_clk_valid_cycles', - 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', - 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 117: 'TA_PERF_SEL_store_has_x_instructions', - 118: 'TA_PERF_SEL_store_has_y_instructions', - 119: 'TA_PERF_SEL_store_has_z_instructions', - 120: 'TA_PERF_SEL_store_has_w_instructions', - 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 128: 'TA_PERF_SEL_in_busy', - 129: 'TA_PERF_SEL_in_fifos_busy', - 130: 'TA_PERF_SEL_in_cfifo_busy', - 131: 'TA_PERF_SEL_in_qfifo_busy', - 132: 'TA_PERF_SEL_in_wfifo_busy', - 133: 'TA_PERF_SEL_in_rfifo_busy', - 134: 'TA_PERF_SEL_bf_busy', - 135: 'TA_PERF_SEL_ns_busy', - 136: 'TA_PERF_SEL_smp_busy_ns_idle', - 137: 'TA_PERF_SEL_smp_idle_ns_busy', - 144: 'TA_PERF_SEL_vmemcmd_cycles', - 145: 'TA_PERF_SEL_vmemreq_cycles', - 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', - 150: 'TA_PERF_SEL_in_addr_cycles', - 151: 'TA_PERF_SEL_in_data_cycles', - 154: 'TA_PERF_SEL_latency_ram_weights_written_cycles', - 155: 'TA_PERF_SEL_latency_ram_ws_required_quads', - 156: 'TA_PERF_SEL_latency_ram_whv_required_quads', - 157: 'TA_PERF_SEL_latency_ram_ws_required_instructions', - 158: 'TA_PERF_SEL_latency_ram_whv_required_instructions', - 159: 'TA_PERF_SEL_latency_ram_ref_required_instructions', - 160: 'TA_PERF_SEL_point_sampled_quads', - 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', - 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', - 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri', - 177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri', - 178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri', - 179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', - 180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', - 181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', - 182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', - 183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', - 184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', - 185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', - 186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', - 187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', - 188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', - 189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', - 190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', - 191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', - 192: 'TA_PERF_SEL_image_sampler_1_op_burst', - 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 196: 'TA_PERF_SEL_image_linked_1_op_burst', - 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', - 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', - 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', - 200: 'TA_PERF_SEL_image_bvh_1_op_burst', - 201: 'TA_PERF_SEL_image_bvh_2to3_op_burst', - 202: 'TA_PERF_SEL_image_bvh_4to7_op_burst', - 203: 'TA_PERF_SEL_image_bvh_ge8_op_burst', - 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', - 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', - 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 212: 'TA_PERF_SEL_write_1_op_burst', - 213: 'TA_PERF_SEL_write_2to3_op_burst', - 214: 'TA_PERF_SEL_write_4to31_op_burst', - 215: 'TA_PERF_SEL_write_ge32_op_burst', - 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', - 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', - 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', - 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', - 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', - 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', - 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', - 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', -} -TA_PERF_SEL_NULL = 0 -TA_PERF_SEL_image_sampler_has_offset_instructions = 1 -TA_PERF_SEL_image_sampler_has_bias_instructions = 2 -TA_PERF_SEL_image_sampler_has_reference_instructions = 3 -TA_PERF_SEL_image_sampler_has_ds_instructions = 4 -TA_PERF_SEL_image_sampler_has_dt_instructions = 5 -TA_PERF_SEL_image_sampler_has_dr_instructions = 6 -TA_PERF_SEL_gradient_busy = 7 -TA_PERF_SEL_gradient_fifo_busy = 8 -TA_PERF_SEL_lod_busy = 9 -TA_PERF_SEL_lod_fifo_busy = 10 -TA_PERF_SEL_addresser_busy = 11 -TA_PERF_SEL_addresser_fifo_busy = 12 -TA_PERF_SEL_aligner_busy = 13 -TA_PERF_SEL_write_path_busy = 14 -TA_PERF_SEL_ta_busy = 15 -TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 -TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 -TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 -TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 -TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 -TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 -TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 -TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 -TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 -TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 -TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 -TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 -TA_PERF_SEL_image_sampler_has_t_instructions = 28 -TA_PERF_SEL_image_sampler_has_r_instructions = 29 -TA_PERF_SEL_image_sampler_has_q_instructions = 30 -TA_PERF_SEL_total_wavefronts = 32 -TA_PERF_SEL_gradient_cycles = 33 -TA_PERF_SEL_walker_cycles = 34 -TA_PERF_SEL_aligner_cycles = 35 -TA_PERF_SEL_image_wavefronts = 36 -TA_PERF_SEL_image_read_wavefronts = 37 -TA_PERF_SEL_image_store_wavefronts = 38 -TA_PERF_SEL_image_atomic_wavefronts = 39 -TA_PERF_SEL_image_sampler_total_cycles = 40 -TA_PERF_SEL_image_nosampler_total_cycles = 41 -TA_PERF_SEL_flat_total_cycles = 42 -TA_PERF_SEL_bvh_total_cycles = 43 -TA_PERF_SEL_buffer_wavefronts = 44 -TA_PERF_SEL_buffer_load_wavefronts = 45 -TA_PERF_SEL_buffer_store_wavefronts = 46 -TA_PERF_SEL_buffer_atomic_wavefronts = 47 -TA_PERF_SEL_buffer_total_cycles = 49 -TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 -TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 -TA_PERF_SEL_buffer_has_index_instructions = 52 -TA_PERF_SEL_buffer_has_offset_instructions = 53 -TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 -TA_PERF_SEL_addr_stalled_by_td_cycles = 55 -TA_PERF_SEL_image_sampler_wavefronts = 56 -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 -TA_PERF_SEL_addresser_stalled_cycles = 58 -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 -TA_PERF_SEL_aniso_stalled_cycles = 60 -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 -TA_PERF_SEL_deriv_stalled_cycles = 62 -TA_PERF_SEL_aniso_gt1_cycle_quads = 63 -TA_PERF_SEL_color_1_cycle_quads = 64 -TA_PERF_SEL_color_2_cycle_quads = 65 -TA_PERF_SEL_color_3_cycle_quads = 66 -TA_PERF_SEL_mip_1_cycle_quads = 68 -TA_PERF_SEL_mip_2_cycle_quads = 69 -TA_PERF_SEL_vol_1_cycle_quads = 70 -TA_PERF_SEL_vol_2_cycle_quads = 71 -TA_PERF_SEL_sampler_op_quads = 72 -TA_PERF_SEL_mipmap_lod_0_samples = 73 -TA_PERF_SEL_mipmap_lod_1_samples = 74 -TA_PERF_SEL_mipmap_lod_2_samples = 75 -TA_PERF_SEL_mipmap_lod_3_samples = 76 -TA_PERF_SEL_mipmap_lod_4_samples = 77 -TA_PERF_SEL_mipmap_lod_5_samples = 78 -TA_PERF_SEL_mipmap_lod_6_samples = 79 -TA_PERF_SEL_mipmap_lod_7_samples = 80 -TA_PERF_SEL_mipmap_lod_8_samples = 81 -TA_PERF_SEL_mipmap_lod_9_samples = 82 -TA_PERF_SEL_mipmap_lod_10_samples = 83 -TA_PERF_SEL_mipmap_lod_11_samples = 84 -TA_PERF_SEL_mipmap_lod_12_samples = 85 -TA_PERF_SEL_mipmap_lod_13_samples = 86 -TA_PERF_SEL_mipmap_lod_14_samples = 87 -TA_PERF_SEL_mipmap_invalid_samples = 88 -TA_PERF_SEL_aniso_1_cycle_quads = 89 -TA_PERF_SEL_aniso_2_cycle_quads = 90 -TA_PERF_SEL_aniso_4_cycle_quads = 91 -TA_PERF_SEL_aniso_6_cycle_quads = 92 -TA_PERF_SEL_aniso_8_cycle_quads = 93 -TA_PERF_SEL_aniso_10_cycle_quads = 94 -TA_PERF_SEL_aniso_12_cycle_quads = 95 -TA_PERF_SEL_aniso_14_cycle_quads = 96 -TA_PERF_SEL_aniso_16_cycle_quads = 97 -TA_PERF_SEL_store_write_data_input_cycles = 98 -TA_PERF_SEL_store_write_data_output_cycles = 99 -TA_PERF_SEL_flat_wavefronts = 100 -TA_PERF_SEL_flat_load_wavefronts = 101 -TA_PERF_SEL_flat_store_wavefronts = 102 -TA_PERF_SEL_flat_atomic_wavefronts = 103 -TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 -TA_PERF_SEL_register_clk_valid_cycles = 105 -TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 -TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 -TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108 -TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 -TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 -TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 -TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 -TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 -TA_PERF_SEL_store_has_x_instructions = 117 -TA_PERF_SEL_store_has_y_instructions = 118 -TA_PERF_SEL_store_has_z_instructions = 119 -TA_PERF_SEL_store_has_w_instructions = 120 -TA_PERF_SEL_image_nosampler_has_t_instructions = 121 -TA_PERF_SEL_image_nosampler_has_r_instructions = 122 -TA_PERF_SEL_image_nosampler_has_q_instructions = 123 -TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 -TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 -TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 -TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 -TA_PERF_SEL_in_busy = 128 -TA_PERF_SEL_in_fifos_busy = 129 -TA_PERF_SEL_in_cfifo_busy = 130 -TA_PERF_SEL_in_qfifo_busy = 131 -TA_PERF_SEL_in_wfifo_busy = 132 -TA_PERF_SEL_in_rfifo_busy = 133 -TA_PERF_SEL_bf_busy = 134 -TA_PERF_SEL_ns_busy = 135 -TA_PERF_SEL_smp_busy_ns_idle = 136 -TA_PERF_SEL_smp_idle_ns_busy = 137 -TA_PERF_SEL_vmemcmd_cycles = 144 -TA_PERF_SEL_vmemreq_cycles = 145 -TA_PERF_SEL_in_waiting_on_req_cycles = 146 -TA_PERF_SEL_in_addr_cycles = 150 -TA_PERF_SEL_in_data_cycles = 151 -TA_PERF_SEL_latency_ram_weights_written_cycles = 154 -TA_PERF_SEL_latency_ram_ws_required_quads = 155 -TA_PERF_SEL_latency_ram_whv_required_quads = 156 -TA_PERF_SEL_latency_ram_ws_required_instructions = 157 -TA_PERF_SEL_latency_ram_whv_required_instructions = 158 -TA_PERF_SEL_latency_ram_ref_required_instructions = 159 -TA_PERF_SEL_point_sampled_quads = 160 -TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 -TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 -TA_PERF_SEL_atomic_write_data_input_cycles = 164 -TA_PERF_SEL_atomic_write_data_output_cycles = 165 -TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 -TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 -TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 -TA_PERF_SEL_num_of_bvh_valid_first_tri = 176 -TA_PERF_SEL_num_of_bvh_valid_second_tri = 177 -TA_PERF_SEL_num_of_bvh_valid_third_tri = 178 -TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179 -TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180 -TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181 -TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182 -TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183 -TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184 -TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185 -TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186 -TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187 -TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188 -TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189 -TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190 -TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191 -TA_PERF_SEL_image_sampler_1_op_burst = 192 -TA_PERF_SEL_image_sampler_2to3_op_burst = 193 -TA_PERF_SEL_image_sampler_4to7_op_burst = 194 -TA_PERF_SEL_image_sampler_ge8_op_burst = 195 -TA_PERF_SEL_image_linked_1_op_burst = 196 -TA_PERF_SEL_image_linked_2to3_op_burst = 197 -TA_PERF_SEL_image_linked_4to7_op_burst = 198 -TA_PERF_SEL_image_linked_ge8_op_burst = 199 -TA_PERF_SEL_image_bvh_1_op_burst = 200 -TA_PERF_SEL_image_bvh_2to3_op_burst = 201 -TA_PERF_SEL_image_bvh_4to7_op_burst = 202 -TA_PERF_SEL_image_bvh_ge8_op_burst = 203 -TA_PERF_SEL_image_nosampler_1_op_burst = 204 -TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 -TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 -TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 -TA_PERF_SEL_buffer_flat_1_op_burst = 208 -TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 -TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 -TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 -TA_PERF_SEL_write_1_op_burst = 212 -TA_PERF_SEL_write_2to3_op_burst = 213 -TA_PERF_SEL_write_4to31_op_burst = 214 -TA_PERF_SEL_write_ge32_op_burst = 215 -TA_PERF_SEL_ibubble_1_cycle_burst = 216 -TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 -TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 -TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 -TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 -TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 -TA_PERF_SEL_sampler_clk_valid_cycles = 224 -TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 -TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 -TA_PERF_SEL_write_data_clk_valid_cycles = 227 -TA_PERF_SEL_gradient_clk_valid_cycles = 228 -TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 -TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 -TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 -TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 -TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 -TA_PERF_SEL_aligner_clk_valid_cycles = 234 -TA_PERF_SEL_tcreq_clk_valid_cycles = 235 -TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BC_SWIZZLE' -TEX_BC_SWIZZLE__enumvalues = { - 0: 'TEX_BC_Swizzle_XYZW', - 1: 'TEX_BC_Swizzle_XWYZ', - 2: 'TEX_BC_Swizzle_WZYX', - 3: 'TEX_BC_Swizzle_WXYZ', - 4: 'TEX_BC_Swizzle_ZYXW', - 5: 'TEX_BC_Swizzle_YXWZ', -} -TEX_BC_Swizzle_XYZW = 0 -TEX_BC_Swizzle_XWYZ = 1 -TEX_BC_Swizzle_WZYX = 2 -TEX_BC_Swizzle_WXYZ = 3 -TEX_BC_Swizzle_ZYXW = 4 -TEX_BC_Swizzle_YXWZ = 5 -TEX_BC_SWIZZLE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BORDER_COLOR_TYPE' -TEX_BORDER_COLOR_TYPE__enumvalues = { - 0: 'TEX_BorderColor_TransparentBlack', - 1: 'TEX_BorderColor_OpaqueBlack', - 2: 'TEX_BorderColor_OpaqueWhite', - 3: 'TEX_BorderColor_Register', -} -TEX_BorderColor_TransparentBlack = 0 -TEX_BorderColor_OpaqueBlack = 1 -TEX_BorderColor_OpaqueWhite = 2 -TEX_BorderColor_Register = 3 -TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CHROMA_KEY' -TEX_CHROMA_KEY__enumvalues = { - 0: 'TEX_ChromaKey_Disabled', - 1: 'TEX_ChromaKey_Kill', - 2: 'TEX_ChromaKey_Blend', - 3: 'TEX_ChromaKey_RESERVED_3', -} -TEX_ChromaKey_Disabled = 0 -TEX_ChromaKey_Kill = 1 -TEX_ChromaKey_Blend = 2 -TEX_ChromaKey_RESERVED_3 = 3 -TEX_CHROMA_KEY = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CLAMP' -TEX_CLAMP__enumvalues = { - 0: 'TEX_Clamp_Repeat', - 1: 'TEX_Clamp_Mirror', - 2: 'TEX_Clamp_ClampToLast', - 3: 'TEX_Clamp_MirrorOnceToLast', - 4: 'TEX_Clamp_ClampHalfToBorder', - 5: 'TEX_Clamp_MirrorOnceHalfToBorder', - 6: 'TEX_Clamp_ClampToBorder', - 7: 'TEX_Clamp_MirrorOnceToBorder', -} -TEX_Clamp_Repeat = 0 -TEX_Clamp_Mirror = 1 -TEX_Clamp_ClampToLast = 2 -TEX_Clamp_MirrorOnceToLast = 3 -TEX_Clamp_ClampHalfToBorder = 4 -TEX_Clamp_MirrorOnceHalfToBorder = 5 -TEX_Clamp_ClampToBorder = 6 -TEX_Clamp_MirrorOnceToBorder = 7 -TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_COORD_TYPE' -TEX_COORD_TYPE__enumvalues = { - 0: 'TEX_CoordType_Unnormalized', - 1: 'TEX_CoordType_Normalized', -} -TEX_CoordType_Unnormalized = 0 -TEX_CoordType_Normalized = 1 -TEX_COORD_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' -TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { - 0: 'TEX_DepthCompareFunction_Never', - 1: 'TEX_DepthCompareFunction_Less', - 2: 'TEX_DepthCompareFunction_Equal', - 3: 'TEX_DepthCompareFunction_LessEqual', - 4: 'TEX_DepthCompareFunction_Greater', - 5: 'TEX_DepthCompareFunction_NotEqual', - 6: 'TEX_DepthCompareFunction_GreaterEqual', - 7: 'TEX_DepthCompareFunction_Always', -} -TEX_DepthCompareFunction_Never = 0 -TEX_DepthCompareFunction_Less = 1 -TEX_DepthCompareFunction_Equal = 2 -TEX_DepthCompareFunction_LessEqual = 3 -TEX_DepthCompareFunction_Greater = 4 -TEX_DepthCompareFunction_NotEqual = 5 -TEX_DepthCompareFunction_GreaterEqual = 6 -TEX_DepthCompareFunction_Always = 7 -TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_FORMAT_COMP' -TEX_FORMAT_COMP__enumvalues = { - 0: 'TEX_FormatComp_Unsigned', - 1: 'TEX_FormatComp_Signed', - 2: 'TEX_FormatComp_UnsignedBiased', - 3: 'TEX_FormatComp_RESERVED_3', -} -TEX_FormatComp_Unsigned = 0 -TEX_FormatComp_Signed = 1 -TEX_FormatComp_UnsignedBiased = 2 -TEX_FormatComp_RESERVED_3 = 3 -TEX_FORMAT_COMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MAX_ANISO_RATIO' -TEX_MAX_ANISO_RATIO__enumvalues = { - 0: 'TEX_MaxAnisoRatio_1to1', - 1: 'TEX_MaxAnisoRatio_2to1', - 2: 'TEX_MaxAnisoRatio_4to1', - 3: 'TEX_MaxAnisoRatio_8to1', - 4: 'TEX_MaxAnisoRatio_16to1', - 5: 'TEX_MaxAnisoRatio_RESERVED_5', - 6: 'TEX_MaxAnisoRatio_RESERVED_6', - 7: 'TEX_MaxAnisoRatio_RESERVED_7', -} -TEX_MaxAnisoRatio_1to1 = 0 -TEX_MaxAnisoRatio_2to1 = 1 -TEX_MaxAnisoRatio_4to1 = 2 -TEX_MaxAnisoRatio_8to1 = 3 -TEX_MaxAnisoRatio_16to1 = 4 -TEX_MaxAnisoRatio_RESERVED_5 = 5 -TEX_MaxAnisoRatio_RESERVED_6 = 6 -TEX_MaxAnisoRatio_RESERVED_7 = 7 -TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MIP_FILTER' -TEX_MIP_FILTER__enumvalues = { - 0: 'TEX_MipFilter_None', - 1: 'TEX_MipFilter_Point', - 2: 'TEX_MipFilter_Linear', - 3: 'TEX_MipFilter_Point_Aniso_Adj', -} -TEX_MipFilter_None = 0 -TEX_MipFilter_Point = 1 -TEX_MipFilter_Linear = 2 -TEX_MipFilter_Point_Aniso_Adj = 3 -TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_REQUEST_SIZE' -TEX_REQUEST_SIZE__enumvalues = { - 0: 'TEX_RequestSize_32B', - 1: 'TEX_RequestSize_64B', - 2: 'TEX_RequestSize_128B', - 3: 'TEX_RequestSize_2X64B', -} -TEX_RequestSize_32B = 0 -TEX_RequestSize_64B = 1 -TEX_RequestSize_128B = 2 -TEX_RequestSize_2X64B = 3 -TEX_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_SAMPLER_TYPE' -TEX_SAMPLER_TYPE__enumvalues = { - 0: 'TEX_SamplerType_Invalid', - 1: 'TEX_SamplerType_Valid', -} -TEX_SamplerType_Invalid = 0 -TEX_SamplerType_Valid = 1 -TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_XY_FILTER' -TEX_XY_FILTER__enumvalues = { - 0: 'TEX_XYFilter_Point', - 1: 'TEX_XYFilter_Linear', - 2: 'TEX_XYFilter_AnisoPoint', - 3: 'TEX_XYFilter_AnisoLinear', -} -TEX_XYFilter_Point = 0 -TEX_XYFilter_Linear = 1 -TEX_XYFilter_AnisoPoint = 2 -TEX_XYFilter_AnisoLinear = 3 -TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_Z_FILTER' -TEX_Z_FILTER__enumvalues = { - 0: 'TEX_ZFilter_None', - 1: 'TEX_ZFilter_Point', - 2: 'TEX_ZFilter_Linear', - 3: 'TEX_ZFilter_RESERVED_3', -} -TEX_ZFilter_None = 0 -TEX_ZFilter_Point = 1 -TEX_ZFilter_Linear = 2 -TEX_ZFilter_RESERVED_3 = 3 -TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_TYPE' -TVX_TYPE__enumvalues = { - 0: 'TVX_Type_InvalidTextureResource', - 1: 'TVX_Type_InvalidVertexBuffer', - 2: 'TVX_Type_ValidTextureResource', - 3: 'TVX_Type_ValidVertexBuffer', -} -TVX_Type_InvalidTextureResource = 0 -TVX_Type_InvalidVertexBuffer = 1 -TVX_Type_ValidTextureResource = 2 -TVX_Type_ValidVertexBuffer = 3 -TVX_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_ADDR_MODES' -TA_TC_ADDR_MODES__enumvalues = { - 0: 'TA_TC_ADDR_MODE_DEFAULT', - 1: 'TA_TC_ADDR_MODE_COMP0', - 2: 'TA_TC_ADDR_MODE_COMP1', - 3: 'TA_TC_ADDR_MODE_COMP2', - 4: 'TA_TC_ADDR_MODE_COMP3', - 5: 'TA_TC_ADDR_MODE_UNALIGNED', - 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', -} -TA_TC_ADDR_MODE_DEFAULT = 0 -TA_TC_ADDR_MODE_COMP0 = 1 -TA_TC_ADDR_MODE_COMP1 = 2 -TA_TC_ADDR_MODE_COMP2 = 3 -TA_TC_ADDR_MODE_COMP3 = 4 -TA_TC_ADDR_MODE_UNALIGNED = 5 -TA_TC_ADDR_MODE_BORDER_COLOR = 6 -TA_TC_ADDR_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_REQ_MODES' -TA_TC_REQ_MODES__enumvalues = { - 0: 'TA_TC_REQ_MODE_BORDER', - 1: 'TA_TC_REQ_MODE_TEX2', - 2: 'TA_TC_REQ_MODE_TEX1', - 3: 'TA_TC_REQ_MODE_TEX0', - 4: 'TA_TC_REQ_MODE_NORMAL', - 5: 'TA_TC_REQ_MODE_DWORD', - 6: 'TA_TC_REQ_MODE_BYTE', - 7: 'TA_TC_REQ_MODE_BYTE_NV', -} -TA_TC_REQ_MODE_BORDER = 0 -TA_TC_REQ_MODE_TEX2 = 1 -TA_TC_REQ_MODE_TEX1 = 2 -TA_TC_REQ_MODE_TEX0 = 3 -TA_TC_REQ_MODE_NORMAL = 4 -TA_TC_REQ_MODE_DWORD = 5 -TA_TC_REQ_MODE_BYTE = 6 -TA_TC_REQ_MODE_BYTE_NV = 7 -TA_TC_REQ_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_POLICIES' -TCP_CACHE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_POLICY_MISS_LRU', - 1: 'TCP_CACHE_POLICY_MISS_EVICT', - 2: 'TCP_CACHE_POLICY_HIT_LRU', - 3: 'TCP_CACHE_POLICY_HIT_EVICT', -} -TCP_CACHE_POLICY_MISS_LRU = 0 -TCP_CACHE_POLICY_MISS_EVICT = 1 -TCP_CACHE_POLICY_HIT_LRU = 2 -TCP_CACHE_POLICY_HIT_EVICT = 3 -TCP_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_STORE_POLICIES' -TCP_CACHE_STORE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', - 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', -} -TCP_CACHE_STORE_POLICY_WT_LRU = 0 -TCP_CACHE_STORE_POLICY_WT_EVICT = 1 -TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_DATA_SEL' -TCP_DSM_DATA_SEL__enumvalues = { - 0: 'TCP_DSM_DISABLE', - 1: 'TCP_DSM_SEL0', - 2: 'TCP_DSM_SEL1', - 3: 'TCP_DSM_SEL_BOTH', -} -TCP_DSM_DISABLE = 0 -TCP_DSM_SEL0 = 1 -TCP_DSM_SEL1 = 2 -TCP_DSM_SEL_BOTH = 3 -TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_INJECT_SEL' -TCP_DSM_INJECT_SEL__enumvalues = { - 0: 'TCP_DSM_INJECT_SEL0', - 1: 'TCP_DSM_INJECT_SEL1', - 2: 'TCP_DSM_INJECT_SEL2', - 3: 'TCP_DSM_INJECT_SEL3', -} -TCP_DSM_INJECT_SEL0 = 0 -TCP_DSM_INJECT_SEL1 = 1 -TCP_DSM_INJECT_SEL2 = 2 -TCP_DSM_INJECT_SEL3 = 3 -TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_SINGLE_WRITE' -TCP_DSM_SINGLE_WRITE__enumvalues = { - 0: 'TCP_DSM_SINGLE_WRITE_DIS', - 1: 'TCP_DSM_SINGLE_WRITE_EN', -} -TCP_DSM_SINGLE_WRITE_DIS = 0 -TCP_DSM_SINGLE_WRITE_EN = 1 -TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_OPCODE_TYPE' -TCP_OPCODE_TYPE__enumvalues = { - 0: 'TCP_OPCODE_READ', - 1: 'TCP_OPCODE_WRITE', - 2: 'TCP_OPCODE_ATOMIC', - 3: 'TCP_OPCODE_INV', - 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', - 5: 'TCP_OPCODE_SAMPLER', - 6: 'TCP_OPCODE_LOAD', - 7: 'TCP_OPCODE_GATHERH', -} -TCP_OPCODE_READ = 0 -TCP_OPCODE_WRITE = 1 -TCP_OPCODE_ATOMIC = 2 -TCP_OPCODE_INV = 3 -TCP_OPCODE_ATOMIC_CMPSWAP = 4 -TCP_OPCODE_SAMPLER = 5 -TCP_OPCODE_LOAD = 6 -TCP_OPCODE_GATHERH = 7 -TCP_OPCODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_PERFCOUNT_SELECT' -TCP_PERFCOUNT_SELECT__enumvalues = { - 0: 'TCP_PERF_SEL_GATE_EN1', - 1: 'TCP_PERF_SEL_GATE_EN2', - 2: 'TCP_PERF_SEL_TA_REQ', - 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', - 4: 'TCP_PERF_SEL_TA_REQ_READ', - 5: 'TCP_PERF_SEL_TA_REQ_WRITE', - 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', - 9: 'TCP_PERF_SEL_REQ', - 10: 'TCP_PERF_SEL_REQ_READ', - 11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', - 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 14: 'TCP_PERF_SEL_REQ_WRITE', - 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', - 17: 'TCP_PERF_SEL_REQ_NON_READ', - 18: 'TCP_PERF_SEL_REQ_MISS', - 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', - 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', - 31: 'TCP_PERF_SEL_GL1_REQ_READ', - 32: 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 33: 'TCP_PERF_SEL_GL1_REQ_READ_64B', - 34: 'TCP_PERF_SEL_GL1_REQ_WRITE', - 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 37: 'TCP_PERF_SEL_GL1_READ_LATENCY', - 38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', - 39: 'TCP_PERF_SEL_TCP_LATENCY', - 40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', - 42: 'TCP_PERF_SEL_DATA_FIFO_STALL', - 43: 'TCP_PERF_SEL_LOD_STALL', - 44: 'TCP_PERF_SEL_POWER_STALL', - 45: 'TCP_PERF_SEL_ALLOC_STALL', - 46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', - 48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', - 49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 50: 'TCP_PERF_SEL_LFIFO_STALL', - 51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 55: 'TCP_PERF_SEL_GL1_PENDING_STALL', - 56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', - 57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', - 58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', - 59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 62: 'TCP_PERF_SEL_TD_TCP_STALL', -} -TCP_PERF_SEL_GATE_EN1 = 0 -TCP_PERF_SEL_GATE_EN2 = 1 -TCP_PERF_SEL_TA_REQ = 2 -TCP_PERF_SEL_TA_REQ_STATE_READ = 3 -TCP_PERF_SEL_TA_REQ_READ = 4 -TCP_PERF_SEL_TA_REQ_WRITE = 5 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 -TCP_PERF_SEL_TA_REQ_GL0_INV = 8 -TCP_PERF_SEL_REQ = 9 -TCP_PERF_SEL_REQ_READ = 10 -TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11 -TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 -TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 -TCP_PERF_SEL_REQ_WRITE = 14 -TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 -TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16 -TCP_PERF_SEL_REQ_NON_READ = 17 -TCP_PERF_SEL_REQ_MISS = 18 -TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19 -TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20 -TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21 -TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22 -TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23 -TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24 -TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25 -TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26 -TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27 -TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28 -TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29 -TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30 -TCP_PERF_SEL_GL1_REQ_READ = 31 -TCP_PERF_SEL_GL1_REQ_READ_128B = 32 -TCP_PERF_SEL_GL1_REQ_READ_64B = 33 -TCP_PERF_SEL_GL1_REQ_WRITE = 34 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36 -TCP_PERF_SEL_GL1_READ_LATENCY = 37 -TCP_PERF_SEL_GL1_WRITE_LATENCY = 38 -TCP_PERF_SEL_TCP_LATENCY = 39 -TCP_PERF_SEL_TCP_TA_REQ_STALL = 40 -TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41 -TCP_PERF_SEL_DATA_FIFO_STALL = 42 -TCP_PERF_SEL_LOD_STALL = 43 -TCP_PERF_SEL_POWER_STALL = 44 -TCP_PERF_SEL_ALLOC_STALL = 45 -TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46 -TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47 -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48 -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49 -TCP_PERF_SEL_LFIFO_STALL = 50 -TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51 -TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52 -TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53 -TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54 -TCP_PERF_SEL_GL1_PENDING_STALL = 55 -TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56 -TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57 -TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58 -TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59 -TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60 -TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61 -TCP_PERF_SEL_TD_TCP_STALL = 62 -TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WATCH_MODES' -TCP_WATCH_MODES__enumvalues = { - 0: 'TCP_WATCH_MODE_READ', - 1: 'TCP_WATCH_MODE_NONREAD', - 2: 'TCP_WATCH_MODE_ATOMIC', - 3: 'TCP_WATCH_MODE_ALL', -} -TCP_WATCH_MODE_READ = 0 -TCP_WATCH_MODE_NONREAD = 1 -TCP_WATCH_MODE_ATOMIC = 2 -TCP_WATCH_MODE_ALL = 3 -TCP_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TD_PERFCOUNT_SEL' -TD_PERFCOUNT_SEL__enumvalues = { - 0: 'TD_PERF_SEL_none', - 1: 'TD_PERF_SEL_td_busy', - 2: 'TD_PERF_SEL_input_busy', - 3: 'TD_PERF_SEL_sampler_lerp_busy', - 4: 'TD_PERF_SEL_sampler_out_busy', - 5: 'TD_PERF_SEL_nofilter_busy', - 6: 'TD_PERF_SEL_ray_tracing_bvh4_busy', - 7: 'TD_PERF_SEL_sampler_core_sclk_en', - 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', - 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', - 12: 'TD_PERF_SEL_sampler_accum_sclk_en', - 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 15: 'TD_PERF_SEL_sampler_out_sclk_en', - 16: 'TD_PERF_SEL_nofilter_sclk_en', - 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', - 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', - 22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', - 23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', - 24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', - 25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', - 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', - 30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', - 31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', - 32: 'TD_PERF_SEL_core_state_ram_max_cnt', - 33: 'TD_PERF_SEL_core_state_rams_read', - 34: 'TD_PERF_SEL_weight_data_rams_read', - 35: 'TD_PERF_SEL_reference_data_rams_read', - 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', - 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', - 38: 'TD_PERF_SEL_tc_td_data_fifo_full', - 39: 'TD_PERF_SEL_input_state_fifo_full', - 40: 'TD_PERF_SEL_ta_data_stall', - 41: 'TD_PERF_SEL_tc_data_stall', - 42: 'TD_PERF_SEL_tc_ram_stall', - 43: 'TD_PERF_SEL_lds_stall', - 44: 'TD_PERF_SEL_sampler_pkr_full', - 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 46: 'TD_PERF_SEL_nofilter_pkr_full', - 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', - 49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', - 50: 'TD_PERF_SEL_gather4_instr', - 51: 'TD_PERF_SEL_gather4h_instr', - 54: 'TD_PERF_SEL_sample_instr', - 55: 'TD_PERF_SEL_sample_c_instr', - 56: 'TD_PERF_SEL_load_instr', - 57: 'TD_PERF_SEL_ldfptr_instr', - 58: 'TD_PERF_SEL_write_ack_instr', - 59: 'TD_PERF_SEL_d16_en_instr', - 60: 'TD_PERF_SEL_bypassLerp_instr', - 61: 'TD_PERF_SEL_min_max_filter_instr', - 62: 'TD_PERF_SEL_one_comp_return_instr', - 63: 'TD_PERF_SEL_two_comp_return_instr', - 64: 'TD_PERF_SEL_three_comp_return_instr', - 65: 'TD_PERF_SEL_four_comp_return_instr', - 66: 'TD_PERF_SEL_user_defined_border', - 67: 'TD_PERF_SEL_white_border', - 68: 'TD_PERF_SEL_opaque_black_border', - 69: 'TD_PERF_SEL_lod_warn_from_ta', - 70: 'TD_PERF_SEL_instruction_dest_is_lds', - 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 75: 'TD_PERF_SEL_out_of_order_instr', - 76: 'TD_PERF_SEL_total_num_instr', - 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 78: 'TD_PERF_SEL_total_num_sampler_instr', - 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 80: 'TD_PERF_SEL_total_num_nofilter_instr', - 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', - 83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', - 84: 'TD_PERF_SEL_mixmode_instr', - 85: 'TD_PERF_SEL_mixmode_resource', - 86: 'TD_PERF_SEL_status_packet', - 87: 'TD_PERF_SEL_address_cmd_poison', - 88: 'TD_PERF_SEL_data_poison', - 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 91: 'TD_PERF_SEL_done_scoreboard_not_empty', - 92: 'TD_PERF_SEL_done_scoreboard_is_full', - 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', - 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', - 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 99: 'TD_PERF_SEL_msaa_load_instr', - 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 101: 'TD_PERF_SEL_blend_prt_with_prt_default_1', - 102: 'TD_PERF_SEL_resmap_instr', - 103: 'TD_PERF_SEL_prt_ack_instr', - 104: 'TD_PERF_SEL_resmap_with_volume_filtering', - 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', - 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', - 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', - 108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', - 109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', - 110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', - 111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', - 112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', - 113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', - 114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', - 115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', - 116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', - 117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', - 118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', - 119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', - 120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', - 121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', - 122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', - 123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', - 124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', - 125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', - 126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', - 127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', - 128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', - 129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', - 130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', - 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 136: 'TD_PERF_SEL_burst_bin_sampler_1', - 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', - 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', - 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', - 140: 'TD_PERF_SEL_burst_bin_gather_1', - 141: 'TD_PERF_SEL_burst_bin_gather_2to8', - 142: 'TD_PERF_SEL_burst_bin_gather_9to16', - 143: 'TD_PERF_SEL_burst_bin_gather_gt16', - 144: 'TD_PERF_SEL_burst_bin_nofilter_1', - 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 149: 'TD_PERF_SEL_burst_bin_bvh4_1', - 150: 'TD_PERF_SEL_burst_bin_bvh4_2to8', - 151: 'TD_PERF_SEL_burst_bin_bvh4_9to16', - 152: 'TD_PERF_SEL_burst_bin_bvh4_gt16', - 153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', - 154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', - 155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', - 156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', - 157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', - 158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', - 159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', - 160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', - 161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', - 162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', - 163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', - 164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', - 165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', - 166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', - 167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', - 168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', - 169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', - 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 181: 'TD_PERF_SEL_sampler_lerp0_active', - 182: 'TD_PERF_SEL_sampler_lerp1_active', - 183: 'TD_PERF_SEL_sampler_lerp2_active', - 184: 'TD_PERF_SEL_sampler_lerp3_active', - 185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', - 186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', -} -TD_PERF_SEL_none = 0 -TD_PERF_SEL_td_busy = 1 -TD_PERF_SEL_input_busy = 2 -TD_PERF_SEL_sampler_lerp_busy = 3 -TD_PERF_SEL_sampler_out_busy = 4 -TD_PERF_SEL_nofilter_busy = 5 -TD_PERF_SEL_ray_tracing_bvh4_busy = 6 -TD_PERF_SEL_sampler_core_sclk_en = 7 -TD_PERF_SEL_sampler_preformatter_sclk_en = 8 -TD_PERF_SEL_sampler_bilerp_sclk_en = 9 -TD_PERF_SEL_sampler_bypass_sclk_en = 10 -TD_PERF_SEL_sampler_minmax_sclk_en = 11 -TD_PERF_SEL_sampler_accum_sclk_en = 12 -TD_PERF_SEL_sampler_format_flt_sclk_en = 13 -TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 -TD_PERF_SEL_sampler_out_sclk_en = 15 -TD_PERF_SEL_nofilter_sclk_en = 16 -TD_PERF_SEL_nofilter_d32_sclk_en = 17 -TD_PERF_SEL_nofilter_d16_sclk_en = 18 -TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22 -TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23 -TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24 -TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25 -TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 -TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 -TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 -TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29 -TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30 -TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31 -TD_PERF_SEL_core_state_ram_max_cnt = 32 -TD_PERF_SEL_core_state_rams_read = 33 -TD_PERF_SEL_weight_data_rams_read = 34 -TD_PERF_SEL_reference_data_rams_read = 35 -TD_PERF_SEL_tc_td_ram_fifo_full = 36 -TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 -TD_PERF_SEL_tc_td_data_fifo_full = 38 -TD_PERF_SEL_input_state_fifo_full = 39 -TD_PERF_SEL_ta_data_stall = 40 -TD_PERF_SEL_tc_data_stall = 41 -TD_PERF_SEL_tc_ram_stall = 42 -TD_PERF_SEL_lds_stall = 43 -TD_PERF_SEL_sampler_pkr_full = 44 -TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 -TD_PERF_SEL_nofilter_pkr_full = 46 -TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 -TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48 -TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49 -TD_PERF_SEL_gather4_instr = 50 -TD_PERF_SEL_gather4h_instr = 51 -TD_PERF_SEL_sample_instr = 54 -TD_PERF_SEL_sample_c_instr = 55 -TD_PERF_SEL_load_instr = 56 -TD_PERF_SEL_ldfptr_instr = 57 -TD_PERF_SEL_write_ack_instr = 58 -TD_PERF_SEL_d16_en_instr = 59 -TD_PERF_SEL_bypassLerp_instr = 60 -TD_PERF_SEL_min_max_filter_instr = 61 -TD_PERF_SEL_one_comp_return_instr = 62 -TD_PERF_SEL_two_comp_return_instr = 63 -TD_PERF_SEL_three_comp_return_instr = 64 -TD_PERF_SEL_four_comp_return_instr = 65 -TD_PERF_SEL_user_defined_border = 66 -TD_PERF_SEL_white_border = 67 -TD_PERF_SEL_opaque_black_border = 68 -TD_PERF_SEL_lod_warn_from_ta = 69 -TD_PERF_SEL_instruction_dest_is_lds = 70 -TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 -TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 -TD_PERF_SEL_out_of_order_instr = 75 -TD_PERF_SEL_total_num_instr = 76 -TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 -TD_PERF_SEL_total_num_sampler_instr = 78 -TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 -TD_PERF_SEL_total_num_nofilter_instr = 80 -TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82 -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83 -TD_PERF_SEL_mixmode_instr = 84 -TD_PERF_SEL_mixmode_resource = 85 -TD_PERF_SEL_status_packet = 86 -TD_PERF_SEL_address_cmd_poison = 87 -TD_PERF_SEL_data_poison = 88 -TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 -TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 -TD_PERF_SEL_done_scoreboard_not_empty = 91 -TD_PERF_SEL_done_scoreboard_is_full = 92 -TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 -TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 -TD_PERF_SEL_nofilter_formatters_turned_on = 95 -TD_PERF_SEL_nofilter_insert_extra_comps = 96 -TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 -TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 -TD_PERF_SEL_msaa_load_instr = 99 -TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 -TD_PERF_SEL_blend_prt_with_prt_default_1 = 101 -TD_PERF_SEL_resmap_instr = 102 -TD_PERF_SEL_prt_ack_instr = 103 -TD_PERF_SEL_resmap_with_volume_filtering = 104 -TD_PERF_SEL_resmap_with_aniso_filtering = 105 -TD_PERF_SEL_resmap_with_no_more_filtering = 106 -TD_PERF_SEL_resmap_with_cubemap_corner = 107 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115 -TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116 -TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117 -TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118 -TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119 -TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120 -TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121 -TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122 -TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123 -TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124 -TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126 -TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127 -TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130 -TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 -TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 -TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 -TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 -TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 -TD_PERF_SEL_burst_bin_sampler_1 = 136 -TD_PERF_SEL_burst_bin_sampler_2to8 = 137 -TD_PERF_SEL_burst_bin_sampler_9to16 = 138 -TD_PERF_SEL_burst_bin_sampler_gt16 = 139 -TD_PERF_SEL_burst_bin_gather_1 = 140 -TD_PERF_SEL_burst_bin_gather_2to8 = 141 -TD_PERF_SEL_burst_bin_gather_9to16 = 142 -TD_PERF_SEL_burst_bin_gather_gt16 = 143 -TD_PERF_SEL_burst_bin_nofilter_1 = 144 -TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 -TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 -TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 -TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 -TD_PERF_SEL_burst_bin_bvh4_1 = 149 -TD_PERF_SEL_burst_bin_bvh4_2to8 = 150 -TD_PERF_SEL_burst_bin_bvh4_9to16 = 151 -TD_PERF_SEL_burst_bin_bvh4_gt16 = 152 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 -TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 -TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 -TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 -TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 -TD_PERF_SEL_preempting_nofilter_max_cnt = 180 -TD_PERF_SEL_sampler_lerp0_active = 181 -TD_PERF_SEL_sampler_lerp1_active = 182 -TD_PERF_SEL_sampler_lerp2_active = 183 -TD_PERF_SEL_sampler_lerp3_active = 184 -TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185 -TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186 -TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187 -TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188 -TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189 -TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190 -TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191 -TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192 -TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2A_PERF_SEL' -GL2A_PERF_SEL__enumvalues = { - 0: 'GL2A_PERF_SEL_NONE', - 1: 'GL2A_PERF_SEL_CYCLE', - 2: 'GL2A_PERF_SEL_BUSY', - 3: 'GL2A_PERF_SEL_REQ_GL2C0', - 4: 'GL2A_PERF_SEL_REQ_GL2C1', - 5: 'GL2A_PERF_SEL_REQ_GL2C2', - 6: 'GL2A_PERF_SEL_REQ_GL2C3', - 7: 'GL2A_PERF_SEL_REQ_GL2C4', - 8: 'GL2A_PERF_SEL_REQ_GL2C5', - 9: 'GL2A_PERF_SEL_REQ_GL2C6', - 10: 'GL2A_PERF_SEL_REQ_GL2C7', - 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', - 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', - 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', - 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', - 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', - 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', - 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', - 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', - 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', - 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', - 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', - 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', - 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 43: 'GL2A_PERF_SEL_RTN_CLIENT0', - 44: 'GL2A_PERF_SEL_RTN_CLIENT1', - 45: 'GL2A_PERF_SEL_RTN_CLIENT2', - 46: 'GL2A_PERF_SEL_RTN_CLIENT3', - 47: 'GL2A_PERF_SEL_RTN_CLIENT4', - 48: 'GL2A_PERF_SEL_RTN_CLIENT5', - 49: 'GL2A_PERF_SEL_RTN_CLIENT6', - 50: 'GL2A_PERF_SEL_RTN_CLIENT7', - 51: 'GL2A_PERF_SEL_RTN_CLIENT8', - 52: 'GL2A_PERF_SEL_RTN_CLIENT9', - 53: 'GL2A_PERF_SEL_RTN_CLIENT10', - 54: 'GL2A_PERF_SEL_RTN_CLIENT11', - 55: 'GL2A_PERF_SEL_RTN_CLIENT12', - 56: 'GL2A_PERF_SEL_RTN_CLIENT13', - 57: 'GL2A_PERF_SEL_RTN_CLIENT14', - 58: 'GL2A_PERF_SEL_RTN_CLIENT15', - 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', -} -GL2A_PERF_SEL_NONE = 0 -GL2A_PERF_SEL_CYCLE = 1 -GL2A_PERF_SEL_BUSY = 2 -GL2A_PERF_SEL_REQ_GL2C0 = 3 -GL2A_PERF_SEL_REQ_GL2C1 = 4 -GL2A_PERF_SEL_REQ_GL2C2 = 5 -GL2A_PERF_SEL_REQ_GL2C3 = 6 -GL2A_PERF_SEL_REQ_GL2C4 = 7 -GL2A_PERF_SEL_REQ_GL2C5 = 8 -GL2A_PERF_SEL_REQ_GL2C6 = 9 -GL2A_PERF_SEL_REQ_GL2C7 = 10 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 -GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 -GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 -GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 -GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 -GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 -GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 -GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 -GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 -GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 -GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 -GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 -GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 -GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 -GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 -GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 -GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 -GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 -GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 -GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 -GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 -GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 -GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 -GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 -GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 -GL2A_PERF_SEL_RTN_CLIENT0 = 43 -GL2A_PERF_SEL_RTN_CLIENT1 = 44 -GL2A_PERF_SEL_RTN_CLIENT2 = 45 -GL2A_PERF_SEL_RTN_CLIENT3 = 46 -GL2A_PERF_SEL_RTN_CLIENT4 = 47 -GL2A_PERF_SEL_RTN_CLIENT5 = 48 -GL2A_PERF_SEL_RTN_CLIENT6 = 49 -GL2A_PERF_SEL_RTN_CLIENT7 = 50 -GL2A_PERF_SEL_RTN_CLIENT8 = 51 -GL2A_PERF_SEL_RTN_CLIENT9 = 52 -GL2A_PERF_SEL_RTN_CLIENT10 = 53 -GL2A_PERF_SEL_RTN_CLIENT11 = 54 -GL2A_PERF_SEL_RTN_CLIENT12 = 55 -GL2A_PERF_SEL_RTN_CLIENT13 = 56 -GL2A_PERF_SEL_RTN_CLIENT14 = 57 -GL2A_PERF_SEL_RTN_CLIENT15 = 58 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 -GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 -GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 -GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 -GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 -GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 -GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 -GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 -GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 -GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 -GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 -GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 -GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 -GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 -GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 -GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 -GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 -GL2A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2C_PERF_SEL' -GL2C_PERF_SEL__enumvalues = { - 0: 'GL2C_PERF_SEL_NONE', - 1: 'GL2C_PERF_SEL_CYCLE', - 2: 'GL2C_PERF_SEL_BUSY', - 3: 'GL2C_PERF_SEL_REQ', - 4: 'GL2C_PERF_SEL_VOL_REQ', - 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', - 6: 'GL2C_PERF_SEL_READ', - 7: 'GL2C_PERF_SEL_WRITE', - 8: 'GL2C_PERF_SEL_ATOMIC', - 9: 'GL2C_PERF_SEL_NOP_ACK', - 10: 'GL2C_PERF_SEL_NOP_RTN0', - 11: 'GL2C_PERF_SEL_PROBE', - 12: 'GL2C_PERF_SEL_PROBE_ALL', - 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', - 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', - 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', - 16: 'GL2C_PERF_SEL_CLIENT0_REQ', - 17: 'GL2C_PERF_SEL_CLIENT1_REQ', - 18: 'GL2C_PERF_SEL_CLIENT2_REQ', - 19: 'GL2C_PERF_SEL_CLIENT3_REQ', - 20: 'GL2C_PERF_SEL_CLIENT4_REQ', - 21: 'GL2C_PERF_SEL_CLIENT5_REQ', - 22: 'GL2C_PERF_SEL_CLIENT6_REQ', - 23: 'GL2C_PERF_SEL_CLIENT7_REQ', - 24: 'GL2C_PERF_SEL_CLIENT8_REQ', - 25: 'GL2C_PERF_SEL_CLIENT9_REQ', - 26: 'GL2C_PERF_SEL_CLIENT10_REQ', - 27: 'GL2C_PERF_SEL_CLIENT11_REQ', - 28: 'GL2C_PERF_SEL_CLIENT12_REQ', - 29: 'GL2C_PERF_SEL_CLIENT13_REQ', - 30: 'GL2C_PERF_SEL_CLIENT14_REQ', - 31: 'GL2C_PERF_SEL_CLIENT15_REQ', - 32: 'GL2C_PERF_SEL_C_RW_S_REQ', - 33: 'GL2C_PERF_SEL_C_RW_US_REQ', - 34: 'GL2C_PERF_SEL_C_RO_S_REQ', - 35: 'GL2C_PERF_SEL_C_RO_US_REQ', - 36: 'GL2C_PERF_SEL_UC_REQ', - 37: 'GL2C_PERF_SEL_LRU_REQ', - 38: 'GL2C_PERF_SEL_STREAM_REQ', - 39: 'GL2C_PERF_SEL_BYPASS_REQ', - 40: 'GL2C_PERF_SEL_NOA_REQ', - 41: 'GL2C_PERF_SEL_SHARED_REQ', - 42: 'GL2C_PERF_SEL_HIT', - 43: 'GL2C_PERF_SEL_MISS', - 44: 'GL2C_PERF_SEL_FULL_HIT', - 45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', - 46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', - 48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', - 49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', - 50: 'GL2C_PERF_SEL_UNCACHED_WRITE', - 51: 'GL2C_PERF_SEL_WRITEBACK', - 52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 53: 'GL2C_PERF_SEL_EVICT', - 54: 'GL2C_PERF_SEL_NORMAL_EVICT', - 55: 'GL2C_PERF_SEL_PROBE_EVICT', - 56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', - 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', - 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 73: 'GL2C_PERF_SEL_READ_32_REQ', - 74: 'GL2C_PERF_SEL_READ_64_REQ', - 75: 'GL2C_PERF_SEL_READ_128_REQ', - 76: 'GL2C_PERF_SEL_WRITE_32_REQ', - 77: 'GL2C_PERF_SEL_WRITE_64_REQ', - 78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 83: 'GL2C_PERF_SEL_MC_WRREQ', - 84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', - 85: 'GL2C_PERF_SEL_EA_WRREQ_64B', - 86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', - 88: 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', - 94: 'GL2C_PERF_SEL_EA_ATOMIC', - 95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', - 96: 'GL2C_PERF_SEL_MC_RDREQ', - 97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', - 98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 99: 'GL2C_PERF_SEL_EA_RDREQ_32B', - 100: 'GL2C_PERF_SEL_EA_RDREQ_64B', - 101: 'GL2C_PERF_SEL_EA_RDREQ_96B', - 102: 'GL2C_PERF_SEL_EA_RDREQ_128B', - 103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 104: 'GL2C_PERF_SEL_EA_RD_MDC_32B', - 105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', - 110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', - 111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 114: 'GL2C_PERF_SEL_ONION_READ', - 115: 'GL2C_PERF_SEL_ONION_WRITE', - 116: 'GL2C_PERF_SEL_IO_READ', - 117: 'GL2C_PERF_SEL_IO_WRITE', - 118: 'GL2C_PERF_SEL_GARLIC_READ', - 119: 'GL2C_PERF_SEL_GARLIC_WRITE', - 120: 'GL2C_PERF_SEL_EA_OUTSTANDING', - 121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 122: 'GL2C_PERF_SEL_SRC_FIFO_FULL', - 123: 'GL2C_PERF_SEL_TAG_STALL', - 124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 128: 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', - 132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', - 133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 135: 'GL2C_PERF_SEL_BUBBLE', - 136: 'GL2C_PERF_SEL_IB_REQ', - 137: 'GL2C_PERF_SEL_IB_STALL', - 138: 'GL2C_PERF_SEL_IB_TAG_STALL', - 139: 'GL2C_PERF_SEL_IB_CM_STALL', - 140: 'GL2C_PERF_SEL_RETURN_ACK', - 141: 'GL2C_PERF_SEL_RETURN_DATA', - 142: 'GL2C_PERF_SEL_EA_RDRET_NACK', - 143: 'GL2C_PERF_SEL_EA_WRRET_NACK', - 144: 'GL2C_PERF_SEL_GL2A_LEVEL', - 145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 149: 'GL2C_PERF_SEL_GCR_INV', - 150: 'GL2C_PERF_SEL_GCR_WB', - 151: 'GL2C_PERF_SEL_GCR_DISCARD', - 152: 'GL2C_PERF_SEL_GCR_RANGE', - 153: 'GL2C_PERF_SEL_GCR_ALL', - 154: 'GL2C_PERF_SEL_GCR_VOL', - 155: 'GL2C_PERF_SEL_GCR_UNSHARED', - 156: 'GL2C_PERF_SEL_GCR_MDC_INV', - 157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', - 161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', - 162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', - 164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', - 172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', - 174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 176: 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 177: 'GL2C_PERF_SEL_MDC_INV_METADATA', - 178: 'GL2C_PERF_SEL_MDC_REQ', - 179: 'GL2C_PERF_SEL_MDC_LEVEL', - 180: 'GL2C_PERF_SEL_MDC_TAG_HIT', - 181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 183: 'GL2C_PERF_SEL_MDC_TAG_STALL', - 184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', - 188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', - 192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', - 194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', - 196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', - 207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', - 217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', - 219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', - 223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', - 230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', - 232: 'GL2C_PERF_SEL_CM_NOOP_REQ', - 233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', - 239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 242: 'GL2C_PERF_SEL_CM_RVF_FULL', - 243: 'GL2C_PERF_SEL_CM_SDR_FULL', - 244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 245: 'GL2C_PERF_SEL_CM_DCC_STALL', - 246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC', - 247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', - 248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', - 249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', - 250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', - 251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', - 252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', - 253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', - 254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', -} -GL2C_PERF_SEL_NONE = 0 -GL2C_PERF_SEL_CYCLE = 1 -GL2C_PERF_SEL_BUSY = 2 -GL2C_PERF_SEL_REQ = 3 -GL2C_PERF_SEL_VOL_REQ = 4 -GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 -GL2C_PERF_SEL_READ = 6 -GL2C_PERF_SEL_WRITE = 7 -GL2C_PERF_SEL_ATOMIC = 8 -GL2C_PERF_SEL_NOP_ACK = 9 -GL2C_PERF_SEL_NOP_RTN0 = 10 -GL2C_PERF_SEL_PROBE = 11 -GL2C_PERF_SEL_PROBE_ALL = 12 -GL2C_PERF_SEL_INTERNAL_PROBE = 13 -GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 -GL2C_PERF_SEL_METADATA_READ_REQ = 15 -GL2C_PERF_SEL_CLIENT0_REQ = 16 -GL2C_PERF_SEL_CLIENT1_REQ = 17 -GL2C_PERF_SEL_CLIENT2_REQ = 18 -GL2C_PERF_SEL_CLIENT3_REQ = 19 -GL2C_PERF_SEL_CLIENT4_REQ = 20 -GL2C_PERF_SEL_CLIENT5_REQ = 21 -GL2C_PERF_SEL_CLIENT6_REQ = 22 -GL2C_PERF_SEL_CLIENT7_REQ = 23 -GL2C_PERF_SEL_CLIENT8_REQ = 24 -GL2C_PERF_SEL_CLIENT9_REQ = 25 -GL2C_PERF_SEL_CLIENT10_REQ = 26 -GL2C_PERF_SEL_CLIENT11_REQ = 27 -GL2C_PERF_SEL_CLIENT12_REQ = 28 -GL2C_PERF_SEL_CLIENT13_REQ = 29 -GL2C_PERF_SEL_CLIENT14_REQ = 30 -GL2C_PERF_SEL_CLIENT15_REQ = 31 -GL2C_PERF_SEL_C_RW_S_REQ = 32 -GL2C_PERF_SEL_C_RW_US_REQ = 33 -GL2C_PERF_SEL_C_RO_S_REQ = 34 -GL2C_PERF_SEL_C_RO_US_REQ = 35 -GL2C_PERF_SEL_UC_REQ = 36 -GL2C_PERF_SEL_LRU_REQ = 37 -GL2C_PERF_SEL_STREAM_REQ = 38 -GL2C_PERF_SEL_BYPASS_REQ = 39 -GL2C_PERF_SEL_NOA_REQ = 40 -GL2C_PERF_SEL_SHARED_REQ = 41 -GL2C_PERF_SEL_HIT = 42 -GL2C_PERF_SEL_MISS = 43 -GL2C_PERF_SEL_FULL_HIT = 44 -GL2C_PERF_SEL_PARTIAL_32B_HIT = 45 -GL2C_PERF_SEL_PARTIAL_64B_HIT = 46 -GL2C_PERF_SEL_PARTIAL_96B_HIT = 47 -GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48 -GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49 -GL2C_PERF_SEL_UNCACHED_WRITE = 50 -GL2C_PERF_SEL_WRITEBACK = 51 -GL2C_PERF_SEL_NORMAL_WRITEBACK = 52 -GL2C_PERF_SEL_EVICT = 53 -GL2C_PERF_SEL_NORMAL_EVICT = 54 -GL2C_PERF_SEL_PROBE_EVICT = 55 -GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72 -GL2C_PERF_SEL_READ_32_REQ = 73 -GL2C_PERF_SEL_READ_64_REQ = 74 -GL2C_PERF_SEL_READ_128_REQ = 75 -GL2C_PERF_SEL_WRITE_32_REQ = 76 -GL2C_PERF_SEL_WRITE_64_REQ = 77 -GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78 -GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79 -GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80 -GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81 -GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82 -GL2C_PERF_SEL_MC_WRREQ = 83 -GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84 -GL2C_PERF_SEL_EA_WRREQ_64B = 85 -GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86 -GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87 -GL2C_PERF_SEL_MC_WRREQ_STALL = 88 -GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89 -GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90 -GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91 -GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92 -GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93 -GL2C_PERF_SEL_EA_ATOMIC = 94 -GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95 -GL2C_PERF_SEL_MC_RDREQ = 96 -GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97 -GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98 -GL2C_PERF_SEL_EA_RDREQ_32B = 99 -GL2C_PERF_SEL_EA_RDREQ_64B = 100 -GL2C_PERF_SEL_EA_RDREQ_96B = 101 -GL2C_PERF_SEL_EA_RDREQ_128B = 102 -GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103 -GL2C_PERF_SEL_EA_RD_MDC_32B = 104 -GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105 -GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106 -GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107 -GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108 -GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109 -GL2C_PERF_SEL_EA_RDREQ_DRAM = 110 -GL2C_PERF_SEL_EA_WRREQ_DRAM = 111 -GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112 -GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113 -GL2C_PERF_SEL_ONION_READ = 114 -GL2C_PERF_SEL_ONION_WRITE = 115 -GL2C_PERF_SEL_IO_READ = 116 -GL2C_PERF_SEL_IO_WRITE = 117 -GL2C_PERF_SEL_GARLIC_READ = 118 -GL2C_PERF_SEL_GARLIC_WRITE = 119 -GL2C_PERF_SEL_EA_OUTSTANDING = 120 -GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121 -GL2C_PERF_SEL_SRC_FIFO_FULL = 122 -GL2C_PERF_SEL_TAG_STALL = 123 -GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124 -GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125 -GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126 -GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127 -GL2C_PERF_SEL_TAG_PROBE_STALL = 128 -GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129 -GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130 -GL2C_PERF_SEL_TAG_READ_DST_STALL = 131 -GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132 -GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133 -GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134 -GL2C_PERF_SEL_BUBBLE = 135 -GL2C_PERF_SEL_IB_REQ = 136 -GL2C_PERF_SEL_IB_STALL = 137 -GL2C_PERF_SEL_IB_TAG_STALL = 138 -GL2C_PERF_SEL_IB_CM_STALL = 139 -GL2C_PERF_SEL_RETURN_ACK = 140 -GL2C_PERF_SEL_RETURN_DATA = 141 -GL2C_PERF_SEL_EA_RDRET_NACK = 142 -GL2C_PERF_SEL_EA_WRRET_NACK = 143 -GL2C_PERF_SEL_GL2A_LEVEL = 144 -GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145 -GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148 -GL2C_PERF_SEL_GCR_INV = 149 -GL2C_PERF_SEL_GCR_WB = 150 -GL2C_PERF_SEL_GCR_DISCARD = 151 -GL2C_PERF_SEL_GCR_RANGE = 152 -GL2C_PERF_SEL_GCR_ALL = 153 -GL2C_PERF_SEL_GCR_VOL = 154 -GL2C_PERF_SEL_GCR_UNSHARED = 155 -GL2C_PERF_SEL_GCR_MDC_INV = 156 -GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157 -GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158 -GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159 -GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160 -GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161 -GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162 -GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163 -GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164 -GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167 -GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168 -GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169 -GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170 -GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171 -GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172 -GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173 -GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174 -GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175 -GL2C_PERF_SEL_GCR_WBINVL2_START = 176 -GL2C_PERF_SEL_MDC_INV_METADATA = 177 -GL2C_PERF_SEL_MDC_REQ = 178 -GL2C_PERF_SEL_MDC_LEVEL = 179 -GL2C_PERF_SEL_MDC_TAG_HIT = 180 -GL2C_PERF_SEL_MDC_SECTOR_HIT = 181 -GL2C_PERF_SEL_MDC_SECTOR_MISS = 182 -GL2C_PERF_SEL_MDC_TAG_STALL = 183 -GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184 -GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185 -GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186 -GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187 -GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188 -GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189 -GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190 -GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191 -GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192 -GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193 -GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194 -GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195 -GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196 -GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197 -GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198 -GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199 -GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200 -GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201 -GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202 -GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203 -GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204 -GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205 -GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206 -GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207 -GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208 -GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209 -GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210 -GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211 -GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212 -GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213 -GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214 -GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215 -GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216 -GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217 -GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218 -GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221 -GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222 -GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225 -GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226 -GL2C_PERF_SEL_CM_COMP_READ_REQ = 227 -GL2C_PERF_SEL_CM_READ_BACK_REQ = 228 -GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229 -GL2C_PERF_SEL_CM_WR_ACK_REQ = 230 -GL2C_PERF_SEL_CM_NO_ACK_REQ = 231 -GL2C_PERF_SEL_CM_NOOP_REQ = 232 -GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233 -GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234 -GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235 -GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236 -GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237 -GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238 -GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239 -GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240 -GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241 -GL2C_PERF_SEL_CM_RVF_FULL = 242 -GL2C_PERF_SEL_CM_SDR_FULL = 243 -GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244 -GL2C_PERF_SEL_CM_DCC_STALL = 245 -GL2C_PERF_SEL_CM_DCC_IN_XFC = 246 -GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247 -GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248 -GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249 -GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250 -GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251 -GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252 -GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257 -GL2C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_PERF_SEL' -GRBM_PERF_SEL__enumvalues = { - 0: 'GRBM_PERF_SEL_COUNT', - 1: 'GRBM_PERF_SEL_USER_DEFINED', - 2: 'GRBM_PERF_SEL_GUI_ACTIVE', - 3: 'GRBM_PERF_SEL_CP_BUSY', - 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', - 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', - 6: 'GRBM_PERF_SEL_CB_BUSY', - 7: 'GRBM_PERF_SEL_DB_BUSY', - 8: 'GRBM_PERF_SEL_PA_BUSY', - 9: 'GRBM_PERF_SEL_SC_BUSY', - 11: 'GRBM_PERF_SEL_SPI_BUSY', - 12: 'GRBM_PERF_SEL_SX_BUSY', - 13: 'GRBM_PERF_SEL_TA_BUSY', - 14: 'GRBM_PERF_SEL_CB_CLEAN', - 15: 'GRBM_PERF_SEL_DB_CLEAN', - 25: 'GRBM_PERF_SEL_GDS_BUSY', - 26: 'GRBM_PERF_SEL_BCI_BUSY', - 27: 'GRBM_PERF_SEL_RLC_BUSY', - 28: 'GRBM_PERF_SEL_TCP_BUSY', - 29: 'GRBM_PERF_SEL_CPG_BUSY', - 30: 'GRBM_PERF_SEL_CPC_BUSY', - 31: 'GRBM_PERF_SEL_CPF_BUSY', - 32: 'GRBM_PERF_SEL_GE_BUSY', - 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 34: 'GRBM_PERF_SEL_UTCL2_BUSY', - 35: 'GRBM_PERF_SEL_EA_BUSY', - 36: 'GRBM_PERF_SEL_RMI_BUSY', - 37: 'GRBM_PERF_SEL_CPAXI_BUSY', - 39: 'GRBM_PERF_SEL_UTCL1_BUSY', - 40: 'GRBM_PERF_SEL_GL2CC_BUSY', - 41: 'GRBM_PERF_SEL_SDMA_BUSY', - 42: 'GRBM_PERF_SEL_CH_BUSY', - 43: 'GRBM_PERF_SEL_PH_BUSY', - 44: 'GRBM_PERF_SEL_PMM_BUSY', - 45: 'GRBM_PERF_SEL_GUS_BUSY', - 46: 'GRBM_PERF_SEL_GL1CC_BUSY', - 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 48: 'GRBM_PERF_SEL_GL1H_BUSY', - 49: 'GRBM_PERF_SEL_PC_BUSY', -} -GRBM_PERF_SEL_COUNT = 0 -GRBM_PERF_SEL_USER_DEFINED = 1 -GRBM_PERF_SEL_GUI_ACTIVE = 2 -GRBM_PERF_SEL_CP_BUSY = 3 -GRBM_PERF_SEL_CP_COHER_BUSY = 4 -GRBM_PERF_SEL_CP_DMA_BUSY = 5 -GRBM_PERF_SEL_CB_BUSY = 6 -GRBM_PERF_SEL_DB_BUSY = 7 -GRBM_PERF_SEL_PA_BUSY = 8 -GRBM_PERF_SEL_SC_BUSY = 9 -GRBM_PERF_SEL_SPI_BUSY = 11 -GRBM_PERF_SEL_SX_BUSY = 12 -GRBM_PERF_SEL_TA_BUSY = 13 -GRBM_PERF_SEL_CB_CLEAN = 14 -GRBM_PERF_SEL_DB_CLEAN = 15 -GRBM_PERF_SEL_GDS_BUSY = 25 -GRBM_PERF_SEL_BCI_BUSY = 26 -GRBM_PERF_SEL_RLC_BUSY = 27 -GRBM_PERF_SEL_TCP_BUSY = 28 -GRBM_PERF_SEL_CPG_BUSY = 29 -GRBM_PERF_SEL_CPC_BUSY = 30 -GRBM_PERF_SEL_CPF_BUSY = 31 -GRBM_PERF_SEL_GE_BUSY = 32 -GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 -GRBM_PERF_SEL_UTCL2_BUSY = 34 -GRBM_PERF_SEL_EA_BUSY = 35 -GRBM_PERF_SEL_RMI_BUSY = 36 -GRBM_PERF_SEL_CPAXI_BUSY = 37 -GRBM_PERF_SEL_UTCL1_BUSY = 39 -GRBM_PERF_SEL_GL2CC_BUSY = 40 -GRBM_PERF_SEL_SDMA_BUSY = 41 -GRBM_PERF_SEL_CH_BUSY = 42 -GRBM_PERF_SEL_PH_BUSY = 43 -GRBM_PERF_SEL_PMM_BUSY = 44 -GRBM_PERF_SEL_GUS_BUSY = 45 -GRBM_PERF_SEL_GL1CC_BUSY = 46 -GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 -GRBM_PERF_SEL_GL1H_BUSY = 48 -GRBM_PERF_SEL_PC_BUSY = 49 -GRBM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE0_PERF_SEL' -GRBM_SE0_PERF_SEL__enumvalues = { - 0: 'GRBM_SE0_PERF_SEL_COUNT', - 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE0_PERF_SEL_PC_BUSY', -} -GRBM_SE0_PERF_SEL_COUNT = 0 -GRBM_SE0_PERF_SEL_USER_DEFINED = 1 -GRBM_SE0_PERF_SEL_CB_BUSY = 2 -GRBM_SE0_PERF_SEL_DB_BUSY = 3 -GRBM_SE0_PERF_SEL_SC_BUSY = 4 -GRBM_SE0_PERF_SEL_SPI_BUSY = 6 -GRBM_SE0_PERF_SEL_SX_BUSY = 7 -GRBM_SE0_PERF_SEL_TA_BUSY = 8 -GRBM_SE0_PERF_SEL_CB_CLEAN = 9 -GRBM_SE0_PERF_SEL_DB_CLEAN = 10 -GRBM_SE0_PERF_SEL_PA_BUSY = 12 -GRBM_SE0_PERF_SEL_BCI_BUSY = 14 -GRBM_SE0_PERF_SEL_RMI_BUSY = 15 -GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE0_PERF_SEL_TCP_BUSY = 17 -GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE0_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE0_PERF_SEL_PC_BUSY = 20 -GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE1_PERF_SEL' -GRBM_SE1_PERF_SEL__enumvalues = { - 0: 'GRBM_SE1_PERF_SEL_COUNT', - 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE1_PERF_SEL_PC_BUSY', -} -GRBM_SE1_PERF_SEL_COUNT = 0 -GRBM_SE1_PERF_SEL_USER_DEFINED = 1 -GRBM_SE1_PERF_SEL_CB_BUSY = 2 -GRBM_SE1_PERF_SEL_DB_BUSY = 3 -GRBM_SE1_PERF_SEL_SC_BUSY = 4 -GRBM_SE1_PERF_SEL_SPI_BUSY = 6 -GRBM_SE1_PERF_SEL_SX_BUSY = 7 -GRBM_SE1_PERF_SEL_TA_BUSY = 8 -GRBM_SE1_PERF_SEL_CB_CLEAN = 9 -GRBM_SE1_PERF_SEL_DB_CLEAN = 10 -GRBM_SE1_PERF_SEL_PA_BUSY = 12 -GRBM_SE1_PERF_SEL_BCI_BUSY = 14 -GRBM_SE1_PERF_SEL_RMI_BUSY = 15 -GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE1_PERF_SEL_TCP_BUSY = 17 -GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE1_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE1_PERF_SEL_PC_BUSY = 20 -GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE2_PERF_SEL' -GRBM_SE2_PERF_SEL__enumvalues = { - 0: 'GRBM_SE2_PERF_SEL_COUNT', - 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE2_PERF_SEL_PC_BUSY', -} -GRBM_SE2_PERF_SEL_COUNT = 0 -GRBM_SE2_PERF_SEL_USER_DEFINED = 1 -GRBM_SE2_PERF_SEL_CB_BUSY = 2 -GRBM_SE2_PERF_SEL_DB_BUSY = 3 -GRBM_SE2_PERF_SEL_SC_BUSY = 4 -GRBM_SE2_PERF_SEL_SPI_BUSY = 6 -GRBM_SE2_PERF_SEL_SX_BUSY = 7 -GRBM_SE2_PERF_SEL_TA_BUSY = 8 -GRBM_SE2_PERF_SEL_CB_CLEAN = 9 -GRBM_SE2_PERF_SEL_DB_CLEAN = 10 -GRBM_SE2_PERF_SEL_PA_BUSY = 12 -GRBM_SE2_PERF_SEL_BCI_BUSY = 14 -GRBM_SE2_PERF_SEL_RMI_BUSY = 15 -GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE2_PERF_SEL_TCP_BUSY = 17 -GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE2_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE2_PERF_SEL_PC_BUSY = 20 -GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE3_PERF_SEL' -GRBM_SE3_PERF_SEL__enumvalues = { - 0: 'GRBM_SE3_PERF_SEL_COUNT', - 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE3_PERF_SEL_PC_BUSY', -} -GRBM_SE3_PERF_SEL_COUNT = 0 -GRBM_SE3_PERF_SEL_USER_DEFINED = 1 -GRBM_SE3_PERF_SEL_CB_BUSY = 2 -GRBM_SE3_PERF_SEL_DB_BUSY = 3 -GRBM_SE3_PERF_SEL_SC_BUSY = 4 -GRBM_SE3_PERF_SEL_SPI_BUSY = 6 -GRBM_SE3_PERF_SEL_SX_BUSY = 7 -GRBM_SE3_PERF_SEL_TA_BUSY = 8 -GRBM_SE3_PERF_SEL_CB_CLEAN = 9 -GRBM_SE3_PERF_SEL_DB_CLEAN = 10 -GRBM_SE3_PERF_SEL_PA_BUSY = 12 -GRBM_SE3_PERF_SEL_BCI_BUSY = 14 -GRBM_SE3_PERF_SEL_RMI_BUSY = 15 -GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE3_PERF_SEL_TCP_BUSY = 17 -GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE3_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE3_PERF_SEL_PC_BUSY = 20 -GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE4_PERF_SEL' -GRBM_SE4_PERF_SEL__enumvalues = { - 0: 'GRBM_SE4_PERF_SEL_COUNT', - 1: 'GRBM_SE4_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE4_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE4_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE4_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE4_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE4_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE4_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE4_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE4_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE4_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE4_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE4_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE4_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE4_PERF_SEL_PC_BUSY', -} -GRBM_SE4_PERF_SEL_COUNT = 0 -GRBM_SE4_PERF_SEL_USER_DEFINED = 1 -GRBM_SE4_PERF_SEL_CB_BUSY = 2 -GRBM_SE4_PERF_SEL_DB_BUSY = 3 -GRBM_SE4_PERF_SEL_SC_BUSY = 4 -GRBM_SE4_PERF_SEL_SPI_BUSY = 6 -GRBM_SE4_PERF_SEL_SX_BUSY = 7 -GRBM_SE4_PERF_SEL_TA_BUSY = 8 -GRBM_SE4_PERF_SEL_CB_CLEAN = 9 -GRBM_SE4_PERF_SEL_DB_CLEAN = 10 -GRBM_SE4_PERF_SEL_PA_BUSY = 12 -GRBM_SE4_PERF_SEL_BCI_BUSY = 14 -GRBM_SE4_PERF_SEL_RMI_BUSY = 15 -GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE4_PERF_SEL_TCP_BUSY = 17 -GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE4_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE4_PERF_SEL_PC_BUSY = 20 -GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE5_PERF_SEL' -GRBM_SE5_PERF_SEL__enumvalues = { - 0: 'GRBM_SE5_PERF_SEL_COUNT', - 1: 'GRBM_SE5_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE5_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE5_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE5_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE5_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE5_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE5_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE5_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE5_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE5_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE5_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE5_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE5_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE5_PERF_SEL_PC_BUSY', -} -GRBM_SE5_PERF_SEL_COUNT = 0 -GRBM_SE5_PERF_SEL_USER_DEFINED = 1 -GRBM_SE5_PERF_SEL_CB_BUSY = 2 -GRBM_SE5_PERF_SEL_DB_BUSY = 3 -GRBM_SE5_PERF_SEL_SC_BUSY = 4 -GRBM_SE5_PERF_SEL_SPI_BUSY = 6 -GRBM_SE5_PERF_SEL_SX_BUSY = 7 -GRBM_SE5_PERF_SEL_TA_BUSY = 8 -GRBM_SE5_PERF_SEL_CB_CLEAN = 9 -GRBM_SE5_PERF_SEL_DB_CLEAN = 10 -GRBM_SE5_PERF_SEL_PA_BUSY = 12 -GRBM_SE5_PERF_SEL_BCI_BUSY = 14 -GRBM_SE5_PERF_SEL_RMI_BUSY = 15 -GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE5_PERF_SEL_TCP_BUSY = 17 -GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE5_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE5_PERF_SEL_PC_BUSY = 20 -GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE6_PERF_SEL' -GRBM_SE6_PERF_SEL__enumvalues = { - 0: 'GRBM_SE6_PERF_SEL_COUNT', - 1: 'GRBM_SE6_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE6_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE6_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE6_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE6_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE6_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE6_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE6_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE6_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE6_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE6_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE6_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE6_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE6_PERF_SEL_PC_BUSY', -} -GRBM_SE6_PERF_SEL_COUNT = 0 -GRBM_SE6_PERF_SEL_USER_DEFINED = 1 -GRBM_SE6_PERF_SEL_CB_BUSY = 2 -GRBM_SE6_PERF_SEL_DB_BUSY = 3 -GRBM_SE6_PERF_SEL_SC_BUSY = 4 -GRBM_SE6_PERF_SEL_SPI_BUSY = 6 -GRBM_SE6_PERF_SEL_SX_BUSY = 7 -GRBM_SE6_PERF_SEL_TA_BUSY = 8 -GRBM_SE6_PERF_SEL_CB_CLEAN = 9 -GRBM_SE6_PERF_SEL_DB_CLEAN = 10 -GRBM_SE6_PERF_SEL_PA_BUSY = 12 -GRBM_SE6_PERF_SEL_BCI_BUSY = 14 -GRBM_SE6_PERF_SEL_RMI_BUSY = 15 -GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE6_PERF_SEL_TCP_BUSY = 17 -GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE6_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE6_PERF_SEL_PC_BUSY = 20 -GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE7_PERF_SEL' -GRBM_SE7_PERF_SEL__enumvalues = { - 0: 'GRBM_SE7_PERF_SEL_COUNT', - 1: 'GRBM_SE7_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE7_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE7_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE7_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE7_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE7_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE7_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE7_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE7_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE7_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE7_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE7_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE7_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE7_PERF_SEL_PC_BUSY', -} -GRBM_SE7_PERF_SEL_COUNT = 0 -GRBM_SE7_PERF_SEL_USER_DEFINED = 1 -GRBM_SE7_PERF_SEL_CB_BUSY = 2 -GRBM_SE7_PERF_SEL_DB_BUSY = 3 -GRBM_SE7_PERF_SEL_SC_BUSY = 4 -GRBM_SE7_PERF_SEL_SPI_BUSY = 6 -GRBM_SE7_PERF_SEL_SX_BUSY = 7 -GRBM_SE7_PERF_SEL_TA_BUSY = 8 -GRBM_SE7_PERF_SEL_CB_CLEAN = 9 -GRBM_SE7_PERF_SEL_DB_CLEAN = 10 -GRBM_SE7_PERF_SEL_PA_BUSY = 12 -GRBM_SE7_PERF_SEL_BCI_BUSY = 14 -GRBM_SE7_PERF_SEL_RMI_BUSY = 15 -GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE7_PERF_SEL_TCP_BUSY = 17 -GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE7_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE7_PERF_SEL_PC_BUSY = 20 -GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_COMPAT_LEVEL' -PIPE_COMPAT_LEVEL__enumvalues = { - 0: 'GEN_ZERO', - 1: 'GEN_ONE', - 2: 'GEN_TWO', - 3: 'GEN_RESERVED', -} -GEN_ZERO = 0 -GEN_ONE = 1 -GEN_TWO = 2 -GEN_RESERVED = 3 -PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_LATENCY_STATS_SEL' -CPC_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', -} -CPC_LATENCY_STATS_SEL_XACK_MAX = 0 -CPC_LATENCY_STATS_SEL_XACK_MIN = 1 -CPC_LATENCY_STATS_SEL_XACK_LAST = 2 -CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 -CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 -CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 -CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_PERFCOUNT_SEL' -CPC_PERFCOUNT_SEL__enumvalues = { - 0: 'CPC_PERF_SEL_ALWAYS_COUNT', - 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', - 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', - 27: 'CPC_PERF_SEL_CPC_STAT_STALL', - 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', - 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', - 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', - 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', - 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', - 45: 'CPC_PERF_SEL_MES_THREAD0', - 46: 'CPC_PERF_SEL_MES_THREAD1', -} -CPC_PERF_SEL_ALWAYS_COUNT = 0 -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 -CPC_PERF_SEL_CPC_STAT_BUSY = 25 -CPC_PERF_SEL_CPC_STAT_IDLE = 26 -CPC_PERF_SEL_CPC_STAT_STALL = 27 -CPC_PERF_SEL_CPC_TCIU_BUSY = 28 -CPC_PERF_SEL_CPC_TCIU_IDLE = 29 -CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 -CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 -CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 -CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 -CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 -CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 -CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 -CPC_PERF_SEL_CPC_GCRIU_STALL = 37 -CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 -CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 -CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 -CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 -CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 -CPC_PERF_SEL_MES_THREAD0 = 45 -CPC_PERF_SEL_MES_THREAD1 = 46 -CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_LATENCY_STATS_SEL' -CPF_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', - 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', - 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', - 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', -} -CPF_LATENCY_STATS_SEL_XACK_MAX = 0 -CPF_LATENCY_STATS_SEL_XACK_MIN = 1 -CPF_LATENCY_STATS_SEL_XACK_LAST = 2 -CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPF_LATENCY_STATS_SEL_READ_MAX = 6 -CPF_LATENCY_STATS_SEL_READ_MIN = 7 -CPF_LATENCY_STATS_SEL_READ_LAST = 8 -CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 -CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 -CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 -CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' -CPF_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPF_PERFWINDOW_SEL_CSF', - 1: 'CPF_PERFWINDOW_SEL_HQD1', - 2: 'CPF_PERFWINDOW_SEL_HQD2', - 3: 'CPF_PERFWINDOW_SEL_RDMA', - 4: 'CPF_PERFWINDOW_SEL_RWPP', -} -CPF_PERFWINDOW_SEL_CSF = 0 -CPF_PERFWINDOW_SEL_HQD1 = 1 -CPF_PERFWINDOW_SEL_HQD2 = 2 -CPF_PERFWINDOW_SEL_RDMA = 3 -CPF_PERFWINDOW_SEL_RWPP = 4 -CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNT_SEL' -CPF_PERFCOUNT_SEL__enumvalues = { - 0: 'CPF_PERF_SEL_ALWAYS_COUNT', - 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', - 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', - 26: 'CPF_PERF_SEL_CPF_STAT_STALL', - 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', - 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', - 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', - 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', - 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', - 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', - 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', -} -CPF_PERF_SEL_ALWAYS_COUNT = 0 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 -CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 -CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 -CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 -CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 -CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 -CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 -CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 -CPF_PERF_SEL_CPF_STAT_BUSY = 24 -CPF_PERF_SEL_CPF_STAT_IDLE = 25 -CPF_PERF_SEL_CPF_STAT_STALL = 26 -CPF_PERF_SEL_CPF_TCIU_BUSY = 27 -CPF_PERF_SEL_CPF_TCIU_IDLE = 28 -CPF_PERF_SEL_CPF_TCIU_STALL = 29 -CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 -CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 -CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 -CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 -CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 -CPF_PERF_SEL_CPF_GCRIU_STALL = 35 -CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 -CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 -CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 -CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 -CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 -CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' -CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { - 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', - 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', - 2: 'CPF_SCRATCH_REG_ATOMIC_OR', - 3: 'CPF_SCRATCH_REG_ATOMIC_AND', - 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', - 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', - 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', - 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', -} -CPF_SCRATCH_REG_ATOMIC_ADD = 0 -CPF_SCRATCH_REG_ATOMIC_SUB = 1 -CPF_SCRATCH_REG_ATOMIC_OR = 2 -CPF_SCRATCH_REG_ATOMIC_AND = 3 -CPF_SCRATCH_REG_ATOMIC_NOT = 4 -CPF_SCRATCH_REG_ATOMIC_MIN = 5 -CPF_SCRATCH_REG_ATOMIC_MAX = 6 -CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 -CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_LATENCY_STATS_SEL' -CPG_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', - 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', - 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', - 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', -} -CPG_LATENCY_STATS_SEL_XACK_MAX = 0 -CPG_LATENCY_STATS_SEL_XACK_MIN = 1 -CPG_LATENCY_STATS_SEL_XACK_LAST = 2 -CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 -CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 -CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 -CPG_LATENCY_STATS_SEL_READ_MAX = 9 -CPG_LATENCY_STATS_SEL_READ_MIN = 10 -CPG_LATENCY_STATS_SEL_READ_LAST = 11 -CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 -CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 -CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 -CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 -CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 -CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 -CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' -CPG_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPG_PERFWINDOW_SEL_PFP', - 1: 'CPG_PERFWINDOW_SEL_ME', - 2: 'CPG_PERFWINDOW_SEL_CE', - 3: 'CPG_PERFWINDOW_SEL_MES', - 4: 'CPG_PERFWINDOW_SEL_MEC1', - 5: 'CPG_PERFWINDOW_SEL_MEC2', - 6: 'CPG_PERFWINDOW_SEL_DFY', - 7: 'CPG_PERFWINDOW_SEL_DMA', - 8: 'CPG_PERFWINDOW_SEL_SHADOW', - 9: 'CPG_PERFWINDOW_SEL_RB', - 10: 'CPG_PERFWINDOW_SEL_CEDMA', - 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', - 13: 'CPG_PERFWINDOW_SEL_PQ1', - 14: 'CPG_PERFWINDOW_SEL_PQ2', - 15: 'CPG_PERFWINDOW_SEL_PQ3', - 16: 'CPG_PERFWINDOW_SEL_MEMWR', - 17: 'CPG_PERFWINDOW_SEL_MEMRD', - 18: 'CPG_PERFWINDOW_SEL_VGT0', - 19: 'CPG_PERFWINDOW_SEL_VGT1', - 20: 'CPG_PERFWINDOW_SEL_APPEND', - 21: 'CPG_PERFWINDOW_SEL_QURD', - 22: 'CPG_PERFWINDOW_SEL_DDID', - 23: 'CPG_PERFWINDOW_SEL_SR', - 24: 'CPG_PERFWINDOW_SEL_QU_EOP', - 25: 'CPG_PERFWINDOW_SEL_QU_STRM', - 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', - 27: 'CPG_PERFWINDOW_SEL_RESERVED1', - 28: 'CPG_PERFWINDOW_SEL_CPC_IC', - 29: 'CPG_PERFWINDOW_SEL_RESERVED2', - 30: 'CPG_PERFWINDOW_SEL_CPG_IC', -} -CPG_PERFWINDOW_SEL_PFP = 0 -CPG_PERFWINDOW_SEL_ME = 1 -CPG_PERFWINDOW_SEL_CE = 2 -CPG_PERFWINDOW_SEL_MES = 3 -CPG_PERFWINDOW_SEL_MEC1 = 4 -CPG_PERFWINDOW_SEL_MEC2 = 5 -CPG_PERFWINDOW_SEL_DFY = 6 -CPG_PERFWINDOW_SEL_DMA = 7 -CPG_PERFWINDOW_SEL_SHADOW = 8 -CPG_PERFWINDOW_SEL_RB = 9 -CPG_PERFWINDOW_SEL_CEDMA = 10 -CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 -CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 -CPG_PERFWINDOW_SEL_PQ1 = 13 -CPG_PERFWINDOW_SEL_PQ2 = 14 -CPG_PERFWINDOW_SEL_PQ3 = 15 -CPG_PERFWINDOW_SEL_MEMWR = 16 -CPG_PERFWINDOW_SEL_MEMRD = 17 -CPG_PERFWINDOW_SEL_VGT0 = 18 -CPG_PERFWINDOW_SEL_VGT1 = 19 -CPG_PERFWINDOW_SEL_APPEND = 20 -CPG_PERFWINDOW_SEL_QURD = 21 -CPG_PERFWINDOW_SEL_DDID = 22 -CPG_PERFWINDOW_SEL_SR = 23 -CPG_PERFWINDOW_SEL_QU_EOP = 24 -CPG_PERFWINDOW_SEL_QU_STRM = 25 -CPG_PERFWINDOW_SEL_QU_PIPE = 26 -CPG_PERFWINDOW_SEL_RESERVED1 = 27 -CPG_PERFWINDOW_SEL_CPC_IC = 28 -CPG_PERFWINDOW_SEL_RESERVED2 = 29 -CPG_PERFWINDOW_SEL_CPG_IC = 30 -CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNT_SEL' -CPG_PERFCOUNT_SEL__enumvalues = { - 0: 'CPG_PERF_SEL_ALWAYS_COUNT', - 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', - 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', - 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', - 53: 'CPG_PERF_SEL_CPG_STAT_STALL', - 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', - 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', - 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', - 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', - 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', - 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', - 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', - 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 78: 'CPG_PERF_SEL_DMA_BUSY', - 79: 'CPG_PERF_SEL_DMA_STARVED', - 80: 'CPG_PERF_SEL_DMA_STALLED', - 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', - 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', - 84: 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 85: 'CPG_PERF_SEL_ME_PWS_STALLED1', -} -CPG_PERF_SEL_ALWAYS_COUNT = 0 -CPG_PERF_SEL_RBIU_FIFO_FULL = 1 -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 -CPG_PERF_SEL_ME_PARSER_BUSY = 5 -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 -CPG_PERF_SEL_REGISTER_CLK_VALID = 33 -CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 -CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 -CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 -CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 -CPG_PERF_SEL_CPG_STAT_BUSY = 51 -CPG_PERF_SEL_CPG_STAT_IDLE = 52 -CPG_PERF_SEL_CPG_STAT_STALL = 53 -CPG_PERF_SEL_CPG_TCIU_BUSY = 54 -CPG_PERF_SEL_CPG_TCIU_IDLE = 55 -CPG_PERF_SEL_CPG_TCIU_STALL = 56 -CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 -CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 -CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 -CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 -CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 -CPG_PERF_SEL_CPG_GCRIU_STALL = 62 -CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 -CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 -CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 -CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 -CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 -CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 -CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 -CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 -CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 -CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 -CPG_PERF_SEL_DMA_BUSY = 78 -CPG_PERF_SEL_DMA_STARVED = 79 -CPG_PERF_SEL_DMA_STALLED = 80 -CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 -CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 -CPG_PERF_SEL_ME_PWS_STALLED0 = 83 -CPG_PERF_SEL_PFP_PWS_STALLED1 = 84 -CPG_PERF_SEL_ME_PWS_STALLED1 = 85 -CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' -CP_ALPHA_TAG_RAM_SEL__enumvalues = { - 0: 'CPG_TAG_RAM', - 1: 'CPC_TAG_RAM', - 2: 'CPF_TAG_RAM', - 3: 'RSV_TAG_RAM', -} -CPG_TAG_RAM = 0 -CPC_TAG_RAM = 1 -CPF_TAG_RAM = 2 -RSV_TAG_RAM = 3 -CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_MODE' -CP_DDID_CNTL_MODE__enumvalues = { - 0: 'STALL', - 1: 'OVERRUN', -} -STALL = 0 -OVERRUN = 1 -CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_SIZE' -CP_DDID_CNTL_SIZE__enumvalues = { - 0: 'SIZE_8K', - 1: 'SIZE_16K', -} -SIZE_8K = 0 -SIZE_16K = 1 -CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_VMID_SEL' -CP_DDID_CNTL_VMID_SEL__enumvalues = { - 0: 'DDID_VMID_PIPE', - 1: 'DDID_VMID_CNTL', -} -DDID_VMID_PIPE = 0 -DDID_VMID_CNTL = 1 -CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ME_ID' -CP_ME_ID__enumvalues = { - 0: 'ME_ID0', - 1: 'ME_ID1', - 2: 'ME_ID2', - 3: 'ME_ID3', -} -ME_ID0 = 0 -ME_ID1 = 1 -ME_ID2 = 2 -ME_ID3 = 3 -CP_ME_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_ENABLE_MODE' -CP_PERFMON_ENABLE_MODE__enumvalues = { - 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', - 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', -} -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 -CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_STATE' -CP_PERFMON_STATE__enumvalues = { - 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'CP_PERFMON_STATE_START_COUNTING', - 2: 'CP_PERFMON_STATE_STOP_COUNTING', - 3: 'CP_PERFMON_STATE_RESERVED_3', - 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -CP_PERFMON_STATE_DISABLE_AND_RESET = 0 -CP_PERFMON_STATE_START_COUNTING = 1 -CP_PERFMON_STATE_STOP_COUNTING = 2 -CP_PERFMON_STATE_RESERVED_3 = 3 -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -CP_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PIPE_ID' -CP_PIPE_ID__enumvalues = { - 0: 'PIPE_ID0', - 1: 'PIPE_ID1', - 2: 'PIPE_ID2', - 3: 'PIPE_ID3', -} -PIPE_ID0 = 0 -PIPE_ID1 = 1 -PIPE_ID2 = 2 -PIPE_ID3 = 3 -CP_PIPE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_RING_ID' -CP_RING_ID__enumvalues = { - 0: 'RINGID0', - 1: 'RINGID1', - 2: 'RINGID2', - 3: 'RINGID3', -} -RINGID0 = 0 -RINGID1 = 1 -RINGID2 = 2 -RINGID3 = 3 -CP_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'SPM_PERFMON_STATE' -SPM_PERFMON_STATE__enumvalues = { - 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'STRM_PERFMON_STATE_START_COUNTING', - 2: 'STRM_PERFMON_STATE_STOP_COUNTING', - 3: 'STRM_PERFMON_STATE_RESERVED_3', - 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 -STRM_PERFMON_STATE_START_COUNTING = 1 -STRM_PERFMON_STATE_STOP_COUNTING = 2 -STRM_PERFMON_STATE_RESERVED_3 = 3 -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -SPM_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'SX_BLEND_OPT' -SX_BLEND_OPT__enumvalues = { - 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', -} -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 -SX_BLEND_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_DOWNCONVERT_FORMAT' -SX_DOWNCONVERT_FORMAT__enumvalues = { - 0: 'SX_RT_EXPORT_NO_CONVERSION', - 1: 'SX_RT_EXPORT_32_R', - 2: 'SX_RT_EXPORT_32_A', - 3: 'SX_RT_EXPORT_10_11_11', - 4: 'SX_RT_EXPORT_2_10_10_10', - 5: 'SX_RT_EXPORT_8_8_8_8', - 6: 'SX_RT_EXPORT_5_6_5', - 7: 'SX_RT_EXPORT_1_5_5_5', - 8: 'SX_RT_EXPORT_4_4_4_4', - 9: 'SX_RT_EXPORT_16_16_GR', - 10: 'SX_RT_EXPORT_16_16_AR', - 11: 'SX_RT_EXPORT_9_9_9_E5', - 12: 'SX_RT_EXPORT_2_10_10_10_7E3', - 13: 'SX_RT_EXPORT_2_10_10_10_6E4', -} -SX_RT_EXPORT_NO_CONVERSION = 0 -SX_RT_EXPORT_32_R = 1 -SX_RT_EXPORT_32_A = 2 -SX_RT_EXPORT_10_11_11 = 3 -SX_RT_EXPORT_2_10_10_10 = 4 -SX_RT_EXPORT_8_8_8_8 = 5 -SX_RT_EXPORT_5_6_5 = 6 -SX_RT_EXPORT_1_5_5_5 = 7 -SX_RT_EXPORT_4_4_4_4 = 8 -SX_RT_EXPORT_16_16_GR = 9 -SX_RT_EXPORT_16_16_AR = 10 -SX_RT_EXPORT_9_9_9_E5 = 11 -SX_RT_EXPORT_2_10_10_10_7E3 = 12 -SX_RT_EXPORT_2_10_10_10_6E4 = 13 -SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_OPT_COMB_FCN' -SX_OPT_COMB_FCN__enumvalues = { - 0: 'OPT_COMB_NONE', - 1: 'OPT_COMB_ADD', - 2: 'OPT_COMB_SUBTRACT', - 3: 'OPT_COMB_MIN', - 4: 'OPT_COMB_MAX', - 5: 'OPT_COMB_REVSUBTRACT', - 6: 'OPT_COMB_BLEND_DISABLED', - 7: 'OPT_COMB_SAFE_ADD', -} -OPT_COMB_NONE = 0 -OPT_COMB_ADD = 1 -OPT_COMB_SUBTRACT = 2 -OPT_COMB_MIN = 3 -OPT_COMB_MAX = 4 -OPT_COMB_REVSUBTRACT = 5 -OPT_COMB_BLEND_DISABLED = 6 -OPT_COMB_SAFE_ADD = 7 -SX_OPT_COMB_FCN = ctypes.c_uint32 # enum - -# values for enumeration 'SX_PERFCOUNTER_VALS' -SX_PERFCOUNTER_VALS__enumvalues = { - 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', - 1: 'SX_PERF_SEL_PA_REQ', - 2: 'SX_PERF_SEL_PA_POS', - 3: 'SX_PERF_SEL_CLOCK', - 4: 'SX_PERF_SEL_GATE_EN1', - 5: 'SX_PERF_SEL_GATE_EN2', - 6: 'SX_PERF_SEL_GATE_EN3', - 7: 'SX_PERF_SEL_GATE_EN4', - 8: 'SX_PERF_SEL_SH_POS_STARVE', - 9: 'SX_PERF_SEL_SH_COLOR_STARVE', - 10: 'SX_PERF_SEL_SH_POS_STALL', - 11: 'SX_PERF_SEL_SH_COLOR_STALL', - 12: 'SX_PERF_SEL_DB0_PIXELS', - 13: 'SX_PERF_SEL_DB0_HALF_QUADS', - 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', - 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', - 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', - 17: 'SX_PERF_SEL_DB1_PIXELS', - 18: 'SX_PERF_SEL_DB1_HALF_QUADS', - 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', - 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', - 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', - 22: 'SX_PERF_SEL_DB2_PIXELS', - 23: 'SX_PERF_SEL_DB2_HALF_QUADS', - 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', - 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', - 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', - 27: 'SX_PERF_SEL_DB3_PIXELS', - 28: 'SX_PERF_SEL_DB3_HALF_QUADS', - 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', - 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', - 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', - 32: 'SX_PERF_SEL_COL_BUSY', - 33: 'SX_PERF_SEL_POS_BUSY', - 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', - 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', - 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', - 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', - 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 54: 'SX_PERF_SEL_PA_REQ_LATENCY', - 55: 'SX_PERF_SEL_POS_SCBD_STALL', - 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', - 57: 'SX_PERF_SEL_GATE_EN5', - 58: 'SX_PERF_SEL_GATE_EN6', - 59: 'SX_PERF_SEL_DB0_SIZE', - 60: 'SX_PERF_SEL_DB1_SIZE', - 61: 'SX_PERF_SEL_DB2_SIZE', - 62: 'SX_PERF_SEL_DB3_SIZE', - 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', - 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 65: 'SX_PERF_SEL_IDX_REQ', - 66: 'SX_PERF_SEL_IDX_RET', - 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', - 68: 'SX_PERF_SEL_IDX_SCBD_STALL', - 69: 'SX_PERF_SEL_GATE_EN7', - 70: 'SX_PERF_SEL_GATE_EN8', - 71: 'SX_PERF_SEL_SH_IDX_STARVE', - 72: 'SX_PERF_SEL_IDX_BUSY', - 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', - 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', - 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', - 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', - 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', - 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', - 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', - 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', - 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', -} -SX_PERF_SEL_PA_IDLE_CYCLES = 0 -SX_PERF_SEL_PA_REQ = 1 -SX_PERF_SEL_PA_POS = 2 -SX_PERF_SEL_CLOCK = 3 -SX_PERF_SEL_GATE_EN1 = 4 -SX_PERF_SEL_GATE_EN2 = 5 -SX_PERF_SEL_GATE_EN3 = 6 -SX_PERF_SEL_GATE_EN4 = 7 -SX_PERF_SEL_SH_POS_STARVE = 8 -SX_PERF_SEL_SH_COLOR_STARVE = 9 -SX_PERF_SEL_SH_POS_STALL = 10 -SX_PERF_SEL_SH_COLOR_STALL = 11 -SX_PERF_SEL_DB0_PIXELS = 12 -SX_PERF_SEL_DB0_HALF_QUADS = 13 -SX_PERF_SEL_DB0_PIXEL_STALL = 14 -SX_PERF_SEL_DB0_PIXEL_IDLE = 15 -SX_PERF_SEL_DB0_PRED_PIXELS = 16 -SX_PERF_SEL_DB1_PIXELS = 17 -SX_PERF_SEL_DB1_HALF_QUADS = 18 -SX_PERF_SEL_DB1_PIXEL_STALL = 19 -SX_PERF_SEL_DB1_PIXEL_IDLE = 20 -SX_PERF_SEL_DB1_PRED_PIXELS = 21 -SX_PERF_SEL_DB2_PIXELS = 22 -SX_PERF_SEL_DB2_HALF_QUADS = 23 -SX_PERF_SEL_DB2_PIXEL_STALL = 24 -SX_PERF_SEL_DB2_PIXEL_IDLE = 25 -SX_PERF_SEL_DB2_PRED_PIXELS = 26 -SX_PERF_SEL_DB3_PIXELS = 27 -SX_PERF_SEL_DB3_HALF_QUADS = 28 -SX_PERF_SEL_DB3_PIXEL_STALL = 29 -SX_PERF_SEL_DB3_PIXEL_IDLE = 30 -SX_PERF_SEL_DB3_PRED_PIXELS = 31 -SX_PERF_SEL_COL_BUSY = 32 -SX_PERF_SEL_POS_BUSY = 33 -SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 -SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 -SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 -SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 -SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 -SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 -SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 -SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 -SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 -SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 -SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 -SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 -SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 -SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 -SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 -SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 -SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 -SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 -SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 -SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 -SX_PERF_SEL_PA_REQ_LATENCY = 54 -SX_PERF_SEL_POS_SCBD_STALL = 55 -SX_PERF_SEL_CLOCK_DROP_STALL = 56 -SX_PERF_SEL_GATE_EN5 = 57 -SX_PERF_SEL_GATE_EN6 = 58 -SX_PERF_SEL_DB0_SIZE = 59 -SX_PERF_SEL_DB1_SIZE = 60 -SX_PERF_SEL_DB2_SIZE = 61 -SX_PERF_SEL_DB3_SIZE = 62 -SX_PERF_SEL_IDX_STALL_CYCLES = 63 -SX_PERF_SEL_IDX_IDLE_CYCLES = 64 -SX_PERF_SEL_IDX_REQ = 65 -SX_PERF_SEL_IDX_RET = 66 -SX_PERF_SEL_IDX_REQ_LATENCY = 67 -SX_PERF_SEL_IDX_SCBD_STALL = 68 -SX_PERF_SEL_GATE_EN7 = 69 -SX_PERF_SEL_GATE_EN8 = 70 -SX_PERF_SEL_SH_IDX_STARVE = 71 -SX_PERF_SEL_IDX_BUSY = 72 -SX_PERF_SEL_PA_POS_BANK_CONF = 73 -SX_PERF_SEL_DB0_END_OF_WAVE = 74 -SX_PERF_SEL_DB0_4X2_DISCARD = 75 -SX_PERF_SEL_DB1_END_OF_WAVE = 76 -SX_PERF_SEL_DB1_4X2_DISCARD = 77 -SX_PERF_SEL_DB2_END_OF_WAVE = 78 -SX_PERF_SEL_DB2_4X2_DISCARD = 79 -SX_PERF_SEL_DB3_END_OF_WAVE = 80 -SX_PERF_SEL_DB3_4X2_DISCARD = 81 -SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum - -# values for enumeration 'CompareFrag' -CompareFrag__enumvalues = { - 0: 'FRAG_NEVER', - 1: 'FRAG_LESS', - 2: 'FRAG_EQUAL', - 3: 'FRAG_LEQUAL', - 4: 'FRAG_GREATER', - 5: 'FRAG_NOTEQUAL', - 6: 'FRAG_GEQUAL', - 7: 'FRAG_ALWAYS', -} -FRAG_NEVER = 0 -FRAG_LESS = 1 -FRAG_EQUAL = 2 -FRAG_LEQUAL = 3 -FRAG_GREATER = 4 -FRAG_NOTEQUAL = 5 -FRAG_GEQUAL = 6 -FRAG_ALWAYS = 7 -CompareFrag = ctypes.c_uint32 # enum - -# values for enumeration 'ConservativeZExport' -ConservativeZExport__enumvalues = { - 0: 'EXPORT_ANY_Z', - 1: 'EXPORT_LESS_THAN_Z', - 2: 'EXPORT_GREATER_THAN_Z', - 3: 'EXPORT_RESERVED', -} -EXPORT_ANY_Z = 0 -EXPORT_LESS_THAN_Z = 1 -EXPORT_GREATER_THAN_Z = 2 -EXPORT_RESERVED = 3 -ConservativeZExport = ctypes.c_uint32 # enum - -# values for enumeration 'DFSMFlushEvents' -DFSMFlushEvents__enumvalues = { - 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', - 1: 'DB_FLUSH_AND_INV_DB_META', - 2: 'DB_CACHE_FLUSH', - 3: 'DB_CACHE_FLUSH_TS', - 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', - 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', - 6: 'DB_VPORT_CHANGED_EVENT', - 7: 'DB_CONTEXT_DONE_EVENT', - 8: 'DB_BREAK_BATCH_EVENT', - 9: 'DB_INVOKE_CHANGE_EVENT', - 10: 'DB_CONTEXT_SUSPEND_EVENT', -} -DB_FLUSH_AND_INV_DB_DATA_TS = 0 -DB_FLUSH_AND_INV_DB_META = 1 -DB_CACHE_FLUSH = 2 -DB_CACHE_FLUSH_TS = 3 -DB_CACHE_FLUSH_AND_INV_EVENT = 4 -DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 -DB_VPORT_CHANGED_EVENT = 6 -DB_CONTEXT_DONE_EVENT = 7 -DB_BREAK_BATCH_EVENT = 8 -DB_INVOKE_CHANGE_EVENT = 9 -DB_CONTEXT_SUSPEND_EVENT = 10 -DFSMFlushEvents = ctypes.c_uint32 # enum - -# values for enumeration 'DbMemArbWatermarks' -DbMemArbWatermarks__enumvalues = { - 0: 'TRANSFERRED_64_BYTES', - 1: 'TRANSFERRED_128_BYTES', - 2: 'TRANSFERRED_256_BYTES', - 3: 'TRANSFERRED_512_BYTES', - 4: 'TRANSFERRED_1024_BYTES', - 5: 'TRANSFERRED_2048_BYTES', - 6: 'TRANSFERRED_4096_BYTES', - 7: 'TRANSFERRED_8192_BYTES', -} -TRANSFERRED_64_BYTES = 0 -TRANSFERRED_128_BYTES = 1 -TRANSFERRED_256_BYTES = 2 -TRANSFERRED_512_BYTES = 3 -TRANSFERRED_1024_BYTES = 4 -TRANSFERRED_2048_BYTES = 5 -TRANSFERRED_4096_BYTES = 6 -TRANSFERRED_8192_BYTES = 7 -DbMemArbWatermarks = ctypes.c_uint32 # enum - -# values for enumeration 'DbPRTFaultBehavior' -DbPRTFaultBehavior__enumvalues = { - 0: 'FAULT_ZERO', - 1: 'FAULT_ONE', - 2: 'FAULT_FAIL', - 3: 'FAULT_PASS', -} -FAULT_ZERO = 0 -FAULT_ONE = 1 -FAULT_FAIL = 2 -FAULT_PASS = 3 -DbPRTFaultBehavior = ctypes.c_uint32 # enum - -# values for enumeration 'DbPSLControl' -DbPSLControl__enumvalues = { - 0: 'PSLC_AUTO', - 1: 'PSLC_ON_HANG_ONLY', - 2: 'PSLC_ASAP', - 3: 'PSLC_COUNTDOWN', -} -PSLC_AUTO = 0 -PSLC_ON_HANG_ONLY = 1 -PSLC_ASAP = 2 -PSLC_COUNTDOWN = 3 -DbPSLControl = ctypes.c_uint32 # enum - -# values for enumeration 'ForceControl' -ForceControl__enumvalues = { - 0: 'FORCE_OFF', - 1: 'FORCE_ENABLE', - 2: 'FORCE_DISABLE', - 3: 'FORCE_RESERVED', -} -FORCE_OFF = 0 -FORCE_ENABLE = 1 -FORCE_DISABLE = 2 -FORCE_RESERVED = 3 -ForceControl = ctypes.c_uint32 # enum - -# values for enumeration 'OreoMode' -OreoMode__enumvalues = { - 0: 'OMODE_BLEND', - 1: 'OMODE_O_THEN_B', - 2: 'OMODE_P_THEN_O_THEN_B', - 3: 'OMODE_RESERVED_3', -} -OMODE_BLEND = 0 -OMODE_O_THEN_B = 1 -OMODE_P_THEN_O_THEN_B = 2 -OMODE_RESERVED_3 = 3 -OreoMode = ctypes.c_uint32 # enum - -# values for enumeration 'PerfCounter_Vals' -PerfCounter_Vals__enumvalues = { - 0: 'DB_PERF_SEL_SC_DB_tile_sends', - 1: 'DB_PERF_SEL_SC_DB_tile_busy', - 2: 'DB_PERF_SEL_SC_DB_tile_stalls', - 3: 'DB_PERF_SEL_SC_DB_tile_events', - 4: 'DB_PERF_SEL_SC_DB_tile_tiles', - 5: 'DB_PERF_SEL_SC_DB_tile_covered', - 6: 'DB_PERF_SEL_hiz_tc_read_starved', - 7: 'DB_PERF_SEL_hiz_tc_write_stall', - 8: 'DB_PERF_SEL_hiz_tile_culled', - 9: 'DB_PERF_SEL_his_tile_culled', - 10: 'DB_PERF_SEL_DB_SC_tile_sends', - 11: 'DB_PERF_SEL_DB_SC_tile_busy', - 12: 'DB_PERF_SEL_DB_SC_tile_stalls', - 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 14: 'DB_PERF_SEL_DB_SC_tile_tiles', - 15: 'DB_PERF_SEL_DB_SC_tile_culled', - 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', - 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 23: 'DB_PERF_SEL_SC_DB_quad_sends', - 24: 'DB_PERF_SEL_SC_DB_quad_busy', - 25: 'DB_PERF_SEL_SC_DB_quad_squads', - 26: 'DB_PERF_SEL_SC_DB_quad_tiles', - 27: 'DB_PERF_SEL_SC_DB_quad_pixels', - 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 29: 'DB_PERF_SEL_DB_SC_quad_sends', - 30: 'DB_PERF_SEL_DB_SC_quad_busy', - 31: 'DB_PERF_SEL_DB_SC_quad_stalls', - 32: 'DB_PERF_SEL_DB_SC_quad_tiles', - 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 34: 'DB_PERF_SEL_DB_CB_tile_sends', - 35: 'DB_PERF_SEL_DB_CB_tile_busy', - 36: 'DB_PERF_SEL_DB_CB_tile_stalls', - 37: 'DB_PERF_SEL_SX_DB_quad_sends', - 38: 'DB_PERF_SEL_SX_DB_quad_busy', - 39: 'DB_PERF_SEL_SX_DB_quad_stalls', - 40: 'DB_PERF_SEL_SX_DB_quad_quads', - 41: 'DB_PERF_SEL_SX_DB_quad_pixels', - 42: 'DB_PERF_SEL_SX_DB_quad_exports', - 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', - 44: 'DB_PERF_SEL_DB_CB_lquad_sends', - 45: 'DB_PERF_SEL_DB_CB_lquad_busy', - 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', - 47: 'DB_PERF_SEL_DB_CB_lquad_quads', - 48: 'DB_PERF_SEL_tile_rd_sends', - 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 50: 'DB_PERF_SEL_quad_rd_sends', - 51: 'DB_PERF_SEL_quad_rd_busy', - 52: 'DB_PERF_SEL_quad_rd_mi_stall', - 53: 'DB_PERF_SEL_quad_rd_rw_collision', - 54: 'DB_PERF_SEL_quad_rd_tag_stall', - 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', - 56: 'DB_PERF_SEL_quad_rd_panic', - 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 58: 'DB_PERF_SEL_quad_rdret_sends', - 59: 'DB_PERF_SEL_quad_rdret_busy', - 60: 'DB_PERF_SEL_tile_wr_sends', - 61: 'DB_PERF_SEL_tile_wr_acks', - 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 63: 'DB_PERF_SEL_quad_wr_sends', - 64: 'DB_PERF_SEL_quad_wr_busy', - 65: 'DB_PERF_SEL_quad_wr_mi_stall', - 66: 'DB_PERF_SEL_quad_wr_coherency_stall', - 67: 'DB_PERF_SEL_quad_wr_acks', - 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 69: 'DB_PERF_SEL_Tile_Cache_misses', - 70: 'DB_PERF_SEL_Tile_Cache_hits', - 71: 'DB_PERF_SEL_Tile_Cache_flushes', - 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', - 73: 'DB_PERF_SEL_Tile_Cache_starves', - 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 75: 'DB_PERF_SEL_tcp_dispatcher_reads', - 76: 'DB_PERF_SEL_tcp_prefetcher_reads', - 77: 'DB_PERF_SEL_tcp_preloader_reads', - 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', - 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', - 80: 'DB_PERF_SEL_tcp_preloader_flushes', - 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', - 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 95: 'DB_PERF_SEL_Stencil_Cache_misses', - 96: 'DB_PERF_SEL_Stencil_Cache_hits', - 97: 'DB_PERF_SEL_Stencil_Cache_flushes', - 98: 'DB_PERF_SEL_Stencil_Cache_starves', - 99: 'DB_PERF_SEL_Stencil_Cache_frees', - 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', - 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', - 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', - 108: 'DB_PERF_SEL_Z_Cache_frees', - 109: 'DB_PERF_SEL_Plane_Cache_misses', - 110: 'DB_PERF_SEL_Plane_Cache_hits', - 111: 'DB_PERF_SEL_Plane_Cache_flushes', - 112: 'DB_PERF_SEL_Plane_Cache_starves', - 113: 'DB_PERF_SEL_Plane_Cache_frees', - 114: 'DB_PERF_SEL_flush_expanded_stencil', - 115: 'DB_PERF_SEL_flush_compressed_stencil', - 116: 'DB_PERF_SEL_flush_single_stencil', - 117: 'DB_PERF_SEL_planes_flushed', - 118: 'DB_PERF_SEL_flush_1plane', - 119: 'DB_PERF_SEL_flush_2plane', - 120: 'DB_PERF_SEL_flush_3plane', - 121: 'DB_PERF_SEL_flush_4plane', - 122: 'DB_PERF_SEL_flush_5plane', - 123: 'DB_PERF_SEL_flush_6plane', - 124: 'DB_PERF_SEL_flush_7plane', - 125: 'DB_PERF_SEL_flush_8plane', - 126: 'DB_PERF_SEL_flush_9plane', - 127: 'DB_PERF_SEL_flush_10plane', - 128: 'DB_PERF_SEL_flush_11plane', - 129: 'DB_PERF_SEL_flush_12plane', - 130: 'DB_PERF_SEL_flush_13plane', - 131: 'DB_PERF_SEL_flush_14plane', - 132: 'DB_PERF_SEL_flush_15plane', - 133: 'DB_PERF_SEL_flush_16plane', - 134: 'DB_PERF_SEL_flush_expanded_z', - 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 137: 'DB_PERF_SEL_dk_tile_sends', - 138: 'DB_PERF_SEL_dk_tile_busy', - 139: 'DB_PERF_SEL_dk_tile_quad_starves', - 140: 'DB_PERF_SEL_dk_tile_stalls', - 141: 'DB_PERF_SEL_dk_squad_sends', - 142: 'DB_PERF_SEL_dk_squad_busy', - 143: 'DB_PERF_SEL_dk_squad_stalls', - 144: 'DB_PERF_SEL_Op_Pipe_Busy', - 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 146: 'DB_PERF_SEL_qc_busy', - 147: 'DB_PERF_SEL_qc_xfc', - 148: 'DB_PERF_SEL_qc_conflicts', - 149: 'DB_PERF_SEL_qc_full_stall', - 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', - 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', - 153: 'DB_PERF_SEL_tl_busy', - 154: 'DB_PERF_SEL_tl_dtc_read_starved', - 155: 'DB_PERF_SEL_tl_z_fetch_stall', - 156: 'DB_PERF_SEL_tl_stencil_stall', - 157: 'DB_PERF_SEL_tl_z_decompress_stall', - 158: 'DB_PERF_SEL_tl_stencil_locked_stall', - 159: 'DB_PERF_SEL_tl_events', - 160: 'DB_PERF_SEL_tl_summarize_squads', - 161: 'DB_PERF_SEL_tl_flush_expand_squads', - 162: 'DB_PERF_SEL_tl_expand_squads', - 163: 'DB_PERF_SEL_tl_preZ_squads', - 164: 'DB_PERF_SEL_tl_postZ_squads', - 165: 'DB_PERF_SEL_tl_preZ_noop_squads', - 166: 'DB_PERF_SEL_tl_postZ_noop_squads', - 167: 'DB_PERF_SEL_tl_tile_ops', - 168: 'DB_PERF_SEL_tl_in_xfc', - 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 170: 'DB_PERF_SEL_tl_in_fast_z_stall', - 171: 'DB_PERF_SEL_tl_out_xfc', - 172: 'DB_PERF_SEL_tl_out_squads', - 173: 'DB_PERF_SEL_zf_plane_multicycle', - 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', - 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', - 180: 'DB_PERF_SEL_ts_tc_update_stall', - 181: 'DB_PERF_SEL_sc_kick_start', - 182: 'DB_PERF_SEL_sc_kick_end', - 183: 'DB_PERF_SEL_clock_reg_active', - 184: 'DB_PERF_SEL_clock_main_active', - 185: 'DB_PERF_SEL_clock_mem_export_active', - 186: 'DB_PERF_SEL_esr_ps_out_busy', - 187: 'DB_PERF_SEL_esr_ps_lqf_busy', - 188: 'DB_PERF_SEL_esr_ps_lqf_stall', - 189: 'DB_PERF_SEL_etr_out_send', - 190: 'DB_PERF_SEL_etr_out_busy', - 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', - 193: 'DB_PERF_SEL_etr_out_esr_stall', - 194: 'DB_PERF_SEL_esr_ps_vic_busy', - 195: 'DB_PERF_SEL_esr_ps_vic_stall', - 196: 'DB_PERF_SEL_esr_eot_fwd_busy', - 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 198: 'DB_PERF_SEL_esr_eot_fwd_forward', - 199: 'DB_PERF_SEL_esr_sqq_zi_busy', - 200: 'DB_PERF_SEL_esr_sqq_zi_stall', - 201: 'DB_PERF_SEL_postzl_sq_pt_busy', - 202: 'DB_PERF_SEL_postzl_sq_pt_stall', - 203: 'DB_PERF_SEL_postzl_se_busy', - 204: 'DB_PERF_SEL_postzl_se_stall', - 205: 'DB_PERF_SEL_postzl_partial_launch', - 206: 'DB_PERF_SEL_postzl_full_launch', - 207: 'DB_PERF_SEL_postzl_partial_waiting', - 208: 'DB_PERF_SEL_postzl_tile_mem_stall', - 209: 'DB_PERF_SEL_postzl_tile_init_stall', - 210: 'DB_PERF_SEL_prezl_tile_mem_stall', - 211: 'DB_PERF_SEL_prezl_tile_init_stall', - 212: 'DB_PERF_SEL_dtt_sm_clash_stall', - 213: 'DB_PERF_SEL_dtt_sm_slot_stall', - 214: 'DB_PERF_SEL_dtt_sm_miss_stall', - 215: 'DB_PERF_SEL_mi_rdreq_busy', - 216: 'DB_PERF_SEL_mi_rdreq_stall', - 217: 'DB_PERF_SEL_mi_wrreq_busy', - 218: 'DB_PERF_SEL_mi_wrreq_stall', - 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 220: 'DB_PERF_SEL_dkg_tile_rate_tile', - 221: 'DB_PERF_SEL_prezl_src_in_sends', - 222: 'DB_PERF_SEL_prezl_src_in_stall', - 223: 'DB_PERF_SEL_prezl_src_in_squads', - 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', - 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 227: 'DB_PERF_SEL_prezl_src_out_stall', - 228: 'DB_PERF_SEL_postzl_src_in_sends', - 229: 'DB_PERF_SEL_postzl_src_in_stall', - 230: 'DB_PERF_SEL_postzl_src_in_squads', - 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', - 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 234: 'DB_PERF_SEL_postzl_src_out_stall', - 235: 'DB_PERF_SEL_esr_ps_src_in_sends', - 236: 'DB_PERF_SEL_esr_ps_src_in_stall', - 237: 'DB_PERF_SEL_esr_ps_src_in_squads', - 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 242: 'DB_PERF_SEL_esr_ps_src_out_stall', - 243: 'DB_PERF_SEL_depth_bounds_tile_culled', - 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 246: 'DB_PERF_SEL_flush_compressed', - 247: 'DB_PERF_SEL_flush_plane_le4', - 248: 'DB_PERF_SEL_tiles_z_fully_summarized', - 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', - 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', - 256: 'DB_PERF_SEL_di_dt_stall', - 257: 'Spare_257', - 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', - 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', - 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', - 261: 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 262: 'DB_PERF_SEL_DB_CB_lquad_double_format', - 263: 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 264: 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', - 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', - 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 269: 'DB_PERF_SEL_DB_CB_rdret_ack', - 270: 'DB_PERF_SEL_DB_CB_rdret_nack', - 271: 'DB_PERF_SEL_DB_CB_wrret_ack', - 272: 'DB_PERF_SEL_DB_CB_wrret_nack', - 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 277: 'DB_PERF_SEL_unmapped_z_tile_culled', - 278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 287: 'DB_PERF_SEL_DB_CB_context_dones', - 288: 'DB_PERF_SEL_DB_CB_eop_dones', - 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 292: 'DB_PERF_SEL_SC_DB_tile_backface', - 293: 'DB_PERF_SEL_SC_DB_quad_quads', - 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', - 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', - 300: 'DB_PERF_SEL_SX_DB_quad_double_format', - 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', - 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', - 303: 'DB_PERF_SEL_quad_rd_sends_unc', - 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', - 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', - 311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', - 312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', - 313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', - 314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', - 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', - 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 329: 'DB_PERF_SEL_esr_vic_sqq_busy', - 330: 'DB_PERF_SEL_esr_vic_sqq_stall', - 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 344: 'DB_PERF_SEL_ts_events_pws_enable', - 345: 'DB_PERF_SEL_ps_events_pws_enable', - 346: 'DB_PERF_SEL_cs_events_pws_enable', - 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', -} -DB_PERF_SEL_SC_DB_tile_sends = 0 -DB_PERF_SEL_SC_DB_tile_busy = 1 -DB_PERF_SEL_SC_DB_tile_stalls = 2 -DB_PERF_SEL_SC_DB_tile_events = 3 -DB_PERF_SEL_SC_DB_tile_tiles = 4 -DB_PERF_SEL_SC_DB_tile_covered = 5 -DB_PERF_SEL_hiz_tc_read_starved = 6 -DB_PERF_SEL_hiz_tc_write_stall = 7 -DB_PERF_SEL_hiz_tile_culled = 8 -DB_PERF_SEL_his_tile_culled = 9 -DB_PERF_SEL_DB_SC_tile_sends = 10 -DB_PERF_SEL_DB_SC_tile_busy = 11 -DB_PERF_SEL_DB_SC_tile_stalls = 12 -DB_PERF_SEL_DB_SC_tile_df_stalls = 13 -DB_PERF_SEL_DB_SC_tile_tiles = 14 -DB_PERF_SEL_DB_SC_tile_culled = 15 -DB_PERF_SEL_DB_SC_tile_hier_kill = 16 -DB_PERF_SEL_DB_SC_tile_fast_ops = 17 -DB_PERF_SEL_DB_SC_tile_no_ops = 18 -DB_PERF_SEL_DB_SC_tile_tile_rate = 19 -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 -DB_PERF_SEL_SC_DB_quad_sends = 23 -DB_PERF_SEL_SC_DB_quad_busy = 24 -DB_PERF_SEL_SC_DB_quad_squads = 25 -DB_PERF_SEL_SC_DB_quad_tiles = 26 -DB_PERF_SEL_SC_DB_quad_pixels = 27 -DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 -DB_PERF_SEL_DB_SC_quad_sends = 29 -DB_PERF_SEL_DB_SC_quad_busy = 30 -DB_PERF_SEL_DB_SC_quad_stalls = 31 -DB_PERF_SEL_DB_SC_quad_tiles = 32 -DB_PERF_SEL_DB_SC_quad_lit_quad = 33 -DB_PERF_SEL_DB_CB_tile_sends = 34 -DB_PERF_SEL_DB_CB_tile_busy = 35 -DB_PERF_SEL_DB_CB_tile_stalls = 36 -DB_PERF_SEL_SX_DB_quad_sends = 37 -DB_PERF_SEL_SX_DB_quad_busy = 38 -DB_PERF_SEL_SX_DB_quad_stalls = 39 -DB_PERF_SEL_SX_DB_quad_quads = 40 -DB_PERF_SEL_SX_DB_quad_pixels = 41 -DB_PERF_SEL_SX_DB_quad_exports = 42 -DB_PERF_SEL_SH_quads_outstanding_sum = 43 -DB_PERF_SEL_DB_CB_lquad_sends = 44 -DB_PERF_SEL_DB_CB_lquad_busy = 45 -DB_PERF_SEL_DB_CB_lquad_stalls = 46 -DB_PERF_SEL_DB_CB_lquad_quads = 47 -DB_PERF_SEL_tile_rd_sends = 48 -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 -DB_PERF_SEL_quad_rd_sends = 50 -DB_PERF_SEL_quad_rd_busy = 51 -DB_PERF_SEL_quad_rd_mi_stall = 52 -DB_PERF_SEL_quad_rd_rw_collision = 53 -DB_PERF_SEL_quad_rd_tag_stall = 54 -DB_PERF_SEL_quad_rd_32byte_reqs = 55 -DB_PERF_SEL_quad_rd_panic = 56 -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 -DB_PERF_SEL_quad_rdret_sends = 58 -DB_PERF_SEL_quad_rdret_busy = 59 -DB_PERF_SEL_tile_wr_sends = 60 -DB_PERF_SEL_tile_wr_acks = 61 -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 -DB_PERF_SEL_quad_wr_sends = 63 -DB_PERF_SEL_quad_wr_busy = 64 -DB_PERF_SEL_quad_wr_mi_stall = 65 -DB_PERF_SEL_quad_wr_coherency_stall = 66 -DB_PERF_SEL_quad_wr_acks = 67 -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 -DB_PERF_SEL_Tile_Cache_misses = 69 -DB_PERF_SEL_Tile_Cache_hits = 70 -DB_PERF_SEL_Tile_Cache_flushes = 71 -DB_PERF_SEL_Tile_Cache_surface_stall = 72 -DB_PERF_SEL_Tile_Cache_starves = 73 -DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 -DB_PERF_SEL_tcp_dispatcher_reads = 75 -DB_PERF_SEL_tcp_prefetcher_reads = 76 -DB_PERF_SEL_tcp_preloader_reads = 77 -DB_PERF_SEL_tcp_dispatcher_flushes = 78 -DB_PERF_SEL_tcp_prefetcher_flushes = 79 -DB_PERF_SEL_tcp_preloader_flushes = 80 -DB_PERF_SEL_Depth_Tile_Cache_sends = 81 -DB_PERF_SEL_Depth_Tile_Cache_busy = 82 -DB_PERF_SEL_Depth_Tile_Cache_starves = 83 -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 -DB_PERF_SEL_Depth_Tile_Cache_misses = 86 -DB_PERF_SEL_Depth_Tile_Cache_hits = 87 -DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 -DB_PERF_SEL_Depth_Tile_Cache_event = 91 -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 -DB_PERF_SEL_Stencil_Cache_misses = 95 -DB_PERF_SEL_Stencil_Cache_hits = 96 -DB_PERF_SEL_Stencil_Cache_flushes = 97 -DB_PERF_SEL_Stencil_Cache_starves = 98 -DB_PERF_SEL_Stencil_Cache_frees = 99 -DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 -DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 -DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 -DB_PERF_SEL_Z_Cache_pmask_misses = 104 -DB_PERF_SEL_Z_Cache_pmask_hits = 105 -DB_PERF_SEL_Z_Cache_pmask_flushes = 106 -DB_PERF_SEL_Z_Cache_pmask_starves = 107 -DB_PERF_SEL_Z_Cache_frees = 108 -DB_PERF_SEL_Plane_Cache_misses = 109 -DB_PERF_SEL_Plane_Cache_hits = 110 -DB_PERF_SEL_Plane_Cache_flushes = 111 -DB_PERF_SEL_Plane_Cache_starves = 112 -DB_PERF_SEL_Plane_Cache_frees = 113 -DB_PERF_SEL_flush_expanded_stencil = 114 -DB_PERF_SEL_flush_compressed_stencil = 115 -DB_PERF_SEL_flush_single_stencil = 116 -DB_PERF_SEL_planes_flushed = 117 -DB_PERF_SEL_flush_1plane = 118 -DB_PERF_SEL_flush_2plane = 119 -DB_PERF_SEL_flush_3plane = 120 -DB_PERF_SEL_flush_4plane = 121 -DB_PERF_SEL_flush_5plane = 122 -DB_PERF_SEL_flush_6plane = 123 -DB_PERF_SEL_flush_7plane = 124 -DB_PERF_SEL_flush_8plane = 125 -DB_PERF_SEL_flush_9plane = 126 -DB_PERF_SEL_flush_10plane = 127 -DB_PERF_SEL_flush_11plane = 128 -DB_PERF_SEL_flush_12plane = 129 -DB_PERF_SEL_flush_13plane = 130 -DB_PERF_SEL_flush_14plane = 131 -DB_PERF_SEL_flush_15plane = 132 -DB_PERF_SEL_flush_16plane = 133 -DB_PERF_SEL_flush_expanded_z = 134 -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 -DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 -DB_PERF_SEL_dk_tile_sends = 137 -DB_PERF_SEL_dk_tile_busy = 138 -DB_PERF_SEL_dk_tile_quad_starves = 139 -DB_PERF_SEL_dk_tile_stalls = 140 -DB_PERF_SEL_dk_squad_sends = 141 -DB_PERF_SEL_dk_squad_busy = 142 -DB_PERF_SEL_dk_squad_stalls = 143 -DB_PERF_SEL_Op_Pipe_Busy = 144 -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 -DB_PERF_SEL_qc_busy = 146 -DB_PERF_SEL_qc_xfc = 147 -DB_PERF_SEL_qc_conflicts = 148 -DB_PERF_SEL_qc_full_stall = 149 -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 -DB_PERF_SEL_tsc_insert_summarize_stall = 152 -DB_PERF_SEL_tl_busy = 153 -DB_PERF_SEL_tl_dtc_read_starved = 154 -DB_PERF_SEL_tl_z_fetch_stall = 155 -DB_PERF_SEL_tl_stencil_stall = 156 -DB_PERF_SEL_tl_z_decompress_stall = 157 -DB_PERF_SEL_tl_stencil_locked_stall = 158 -DB_PERF_SEL_tl_events = 159 -DB_PERF_SEL_tl_summarize_squads = 160 -DB_PERF_SEL_tl_flush_expand_squads = 161 -DB_PERF_SEL_tl_expand_squads = 162 -DB_PERF_SEL_tl_preZ_squads = 163 -DB_PERF_SEL_tl_postZ_squads = 164 -DB_PERF_SEL_tl_preZ_noop_squads = 165 -DB_PERF_SEL_tl_postZ_noop_squads = 166 -DB_PERF_SEL_tl_tile_ops = 167 -DB_PERF_SEL_tl_in_xfc = 168 -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 -DB_PERF_SEL_tl_in_fast_z_stall = 170 -DB_PERF_SEL_tl_out_xfc = 171 -DB_PERF_SEL_tl_out_squads = 172 -DB_PERF_SEL_zf_plane_multicycle = 173 -DB_PERF_SEL_PostZ_Samples_passing_Z = 174 -DB_PERF_SEL_PostZ_Samples_failing_Z = 175 -DB_PERF_SEL_PostZ_Samples_failing_S = 176 -DB_PERF_SEL_PreZ_Samples_passing_Z = 177 -DB_PERF_SEL_PreZ_Samples_failing_Z = 178 -DB_PERF_SEL_PreZ_Samples_failing_S = 179 -DB_PERF_SEL_ts_tc_update_stall = 180 -DB_PERF_SEL_sc_kick_start = 181 -DB_PERF_SEL_sc_kick_end = 182 -DB_PERF_SEL_clock_reg_active = 183 -DB_PERF_SEL_clock_main_active = 184 -DB_PERF_SEL_clock_mem_export_active = 185 -DB_PERF_SEL_esr_ps_out_busy = 186 -DB_PERF_SEL_esr_ps_lqf_busy = 187 -DB_PERF_SEL_esr_ps_lqf_stall = 188 -DB_PERF_SEL_etr_out_send = 189 -DB_PERF_SEL_etr_out_busy = 190 -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 -DB_PERF_SEL_etr_out_cb_tile_stall = 192 -DB_PERF_SEL_etr_out_esr_stall = 193 -DB_PERF_SEL_esr_ps_vic_busy = 194 -DB_PERF_SEL_esr_ps_vic_stall = 195 -DB_PERF_SEL_esr_eot_fwd_busy = 196 -DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 -DB_PERF_SEL_esr_eot_fwd_forward = 198 -DB_PERF_SEL_esr_sqq_zi_busy = 199 -DB_PERF_SEL_esr_sqq_zi_stall = 200 -DB_PERF_SEL_postzl_sq_pt_busy = 201 -DB_PERF_SEL_postzl_sq_pt_stall = 202 -DB_PERF_SEL_postzl_se_busy = 203 -DB_PERF_SEL_postzl_se_stall = 204 -DB_PERF_SEL_postzl_partial_launch = 205 -DB_PERF_SEL_postzl_full_launch = 206 -DB_PERF_SEL_postzl_partial_waiting = 207 -DB_PERF_SEL_postzl_tile_mem_stall = 208 -DB_PERF_SEL_postzl_tile_init_stall = 209 -DB_PERF_SEL_prezl_tile_mem_stall = 210 -DB_PERF_SEL_prezl_tile_init_stall = 211 -DB_PERF_SEL_dtt_sm_clash_stall = 212 -DB_PERF_SEL_dtt_sm_slot_stall = 213 -DB_PERF_SEL_dtt_sm_miss_stall = 214 -DB_PERF_SEL_mi_rdreq_busy = 215 -DB_PERF_SEL_mi_rdreq_stall = 216 -DB_PERF_SEL_mi_wrreq_busy = 217 -DB_PERF_SEL_mi_wrreq_stall = 218 -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 -DB_PERF_SEL_dkg_tile_rate_tile = 220 -DB_PERF_SEL_prezl_src_in_sends = 221 -DB_PERF_SEL_prezl_src_in_stall = 222 -DB_PERF_SEL_prezl_src_in_squads = 223 -DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 -DB_PERF_SEL_prezl_src_in_tile_rate = 225 -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 -DB_PERF_SEL_prezl_src_out_stall = 227 -DB_PERF_SEL_postzl_src_in_sends = 228 -DB_PERF_SEL_postzl_src_in_stall = 229 -DB_PERF_SEL_postzl_src_in_squads = 230 -DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 -DB_PERF_SEL_postzl_src_in_tile_rate = 232 -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 -DB_PERF_SEL_postzl_src_out_stall = 234 -DB_PERF_SEL_esr_ps_src_in_sends = 235 -DB_PERF_SEL_esr_ps_src_in_stall = 236 -DB_PERF_SEL_esr_ps_src_in_squads = 237 -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 -DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 -DB_PERF_SEL_esr_ps_src_out_stall = 242 -DB_PERF_SEL_depth_bounds_tile_culled = 243 -DB_PERF_SEL_PreZ_Samples_failing_DB = 244 -DB_PERF_SEL_PostZ_Samples_failing_DB = 245 -DB_PERF_SEL_flush_compressed = 246 -DB_PERF_SEL_flush_plane_le4 = 247 -DB_PERF_SEL_tiles_z_fully_summarized = 248 -DB_PERF_SEL_tiles_stencil_fully_summarized = 249 -DB_PERF_SEL_tiles_z_clear_on_expclear = 250 -DB_PERF_SEL_tiles_s_clear_on_expclear = 251 -DB_PERF_SEL_tiles_decomp_on_expclear = 252 -DB_PERF_SEL_tiles_compressed_to_decompressed = 253 -DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 -DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 -DB_PERF_SEL_di_dt_stall = 256 -Spare_257 = 257 -DB_PERF_SEL_DB_SC_s_tile_rate = 258 -DB_PERF_SEL_DB_SC_c_tile_rate = 259 -DB_PERF_SEL_DB_SC_z_tile_rate = 260 -DB_PERF_SEL_DB_CB_lquad_export_quads = 261 -DB_PERF_SEL_DB_CB_lquad_double_format = 262 -DB_PERF_SEL_DB_CB_lquad_fast_format = 263 -DB_PERF_SEL_DB_CB_lquad_slow_format = 264 -DB_PERF_SEL_CB_DB_rdreq_sends = 265 -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 -DB_PERF_SEL_CB_DB_wrreq_sends = 267 -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 -DB_PERF_SEL_DB_CB_rdret_ack = 269 -DB_PERF_SEL_DB_CB_rdret_nack = 270 -DB_PERF_SEL_DB_CB_wrret_ack = 271 -DB_PERF_SEL_DB_CB_wrret_nack = 272 -DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 -DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 -DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 -DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 -DB_PERF_SEL_unmapped_z_tile_culled = 277 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 -DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280 -DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281 -DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285 -DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286 -DB_PERF_SEL_DB_CB_context_dones = 287 -DB_PERF_SEL_DB_CB_eop_dones = 288 -DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 -DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 -DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 -DB_PERF_SEL_SC_DB_tile_backface = 292 -DB_PERF_SEL_SC_DB_quad_quads = 293 -DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 -DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 -DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 -DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 -DB_PERF_SEL_DB_SC_quad_double_quad = 298 -DB_PERF_SEL_SX_DB_quad_export_quads = 299 -DB_PERF_SEL_SX_DB_quad_double_format = 300 -DB_PERF_SEL_SX_DB_quad_fast_format = 301 -DB_PERF_SEL_SX_DB_quad_slow_format = 302 -DB_PERF_SEL_quad_rd_sends_unc = 303 -DB_PERF_SEL_quad_rd_mi_stall_unc = 304 -DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 -DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 -DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 -DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 -DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 -DB_PERF_SEL_noz_waiting_for_postz_done = 310 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314 -DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 -DB_PERF_SEL_RMI_rd_z_32byte_req = 316 -DB_PERF_SEL_RMI_rd_s_32byte_req = 317 -DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 -DB_PERF_SEL_RMI_wr_z_32byte_req = 319 -DB_PERF_SEL_RMI_wr_s_32byte_req = 320 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 -DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 -DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 -DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 -DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 -DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 -DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 -DB_PERF_SEL_esr_vic_sqq_busy = 329 -DB_PERF_SEL_esr_vic_sqq_stall = 330 -DB_PERF_SEL_esr_psi_vic_tile_rate = 331 -DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 -DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 -DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 -DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 -DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 -DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 -DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 -DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 -DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 -DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 -DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 -DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 -DB_PERF_SEL_ts_events_pws_enable = 344 -DB_PERF_SEL_ps_events_pws_enable = 345 -DB_PERF_SEL_cs_events_pws_enable = 346 -DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 -DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 -PerfCounter_Vals = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeCounterId' -PixelPipeCounterId__enumvalues = { - 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', - 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', -} -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 -PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 -PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 -PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 -PixelPipeCounterId = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeStride' -PixelPipeStride__enumvalues = { - 0: 'PIXEL_PIPE_STRIDE_32_BITS', - 1: 'PIXEL_PIPE_STRIDE_64_BITS', - 2: 'PIXEL_PIPE_STRIDE_128_BITS', - 3: 'PIXEL_PIPE_STRIDE_256_BITS', -} -PIXEL_PIPE_STRIDE_32_BITS = 0 -PIXEL_PIPE_STRIDE_64_BITS = 1 -PIXEL_PIPE_STRIDE_128_BITS = 2 -PIXEL_PIPE_STRIDE_256_BITS = 3 -PixelPipeStride = ctypes.c_uint32 # enum - -# values for enumeration 'RingCounterControl' -RingCounterControl__enumvalues = { - 0: 'COUNTER_RING_SPLIT', - 1: 'COUNTER_RING_0', - 2: 'COUNTER_RING_1', -} -COUNTER_RING_SPLIT = 0 -COUNTER_RING_0 = 1 -COUNTER_RING_1 = 2 -RingCounterControl = ctypes.c_uint32 # enum - -# values for enumeration 'StencilOp' -StencilOp__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_ONES', - 3: 'STENCIL_REPLACE_TEST', - 4: 'STENCIL_REPLACE_OP', - 5: 'STENCIL_ADD_CLAMP', - 6: 'STENCIL_SUB_CLAMP', - 7: 'STENCIL_INVERT', - 8: 'STENCIL_ADD_WRAP', - 9: 'STENCIL_SUB_WRAP', - 10: 'STENCIL_AND', - 11: 'STENCIL_OR', - 12: 'STENCIL_XOR', - 13: 'STENCIL_NAND', - 14: 'STENCIL_NOR', - 15: 'STENCIL_XNOR', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_ONES = 2 -STENCIL_REPLACE_TEST = 3 -STENCIL_REPLACE_OP = 4 -STENCIL_ADD_CLAMP = 5 -STENCIL_SUB_CLAMP = 6 -STENCIL_INVERT = 7 -STENCIL_ADD_WRAP = 8 -STENCIL_SUB_WRAP = 9 -STENCIL_AND = 10 -STENCIL_OR = 11 -STENCIL_XOR = 12 -STENCIL_NAND = 13 -STENCIL_NOR = 14 -STENCIL_XNOR = 15 -StencilOp = ctypes.c_uint32 # enum - -# values for enumeration 'ZLimitSumm' -ZLimitSumm__enumvalues = { - 0: 'FORCE_SUMM_OFF', - 1: 'FORCE_SUMM_MINZ', - 2: 'FORCE_SUMM_MAXZ', - 3: 'FORCE_SUMM_BOTH', -} -FORCE_SUMM_OFF = 0 -FORCE_SUMM_MINZ = 1 -FORCE_SUMM_MAXZ = 2 -FORCE_SUMM_BOTH = 3 -ZLimitSumm = ctypes.c_uint32 # enum - -# values for enumeration 'ZModeForce' -ZModeForce__enumvalues = { - 0: 'NO_FORCE', - 1: 'FORCE_EARLY_Z', - 2: 'FORCE_LATE_Z', - 3: 'FORCE_RE_Z', -} -NO_FORCE = 0 -FORCE_EARLY_Z = 1 -FORCE_LATE_Z = 2 -FORCE_RE_Z = 3 -ZModeForce = ctypes.c_uint32 # enum - -# values for enumeration 'ZOrder' -ZOrder__enumvalues = { - 0: 'LATE_Z', - 1: 'EARLY_Z_THEN_LATE_Z', - 2: 'RE_Z', - 3: 'EARLY_Z_THEN_RE_Z', -} -LATE_Z = 0 -EARLY_Z_THEN_LATE_Z = 1 -RE_Z = 2 -EARLY_Z_THEN_RE_Z = 3 -ZOrder = ctypes.c_uint32 # enum - -# values for enumeration 'ZSamplePosition' -ZSamplePosition__enumvalues = { - 0: 'Z_SAMPLE_CENTER', - 1: 'Z_SAMPLE_CENTROID', -} -Z_SAMPLE_CENTER = 0 -Z_SAMPLE_CENTROID = 1 -ZSamplePosition = ctypes.c_uint32 # enum - -# values for enumeration 'ZpassControl' -ZpassControl__enumvalues = { - 0: 'ZPASS_DISABLE', - 1: 'ZPASS_SAMPLES', - 2: 'ZPASS_PIXELS', -} -ZPASS_DISABLE = 0 -ZPASS_SAMPLES = 1 -ZPASS_PIXELS = 2 -ZpassControl = ctypes.c_uint32 # enum - -# values for enumeration 'SU_PERFCNT_SEL' -SU_PERFCNT_SEL__enumvalues = { - 0: 'PERF_PAPC_PASX_REQ', - 1: 'PERF_PAPC_PASX_DISABLE_PIPE', - 2: 'PERF_PAPC_PASX_FIRST_VECTOR', - 3: 'PERF_PAPC_PASX_SECOND_VECTOR', - 4: 'PERF_PAPC_PASX_FIRST_DEAD', - 5: 'PERF_PAPC_PASX_SECOND_DEAD', - 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 8: 'PERF_PAPC_PA_INPUT_PRIM', - 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', - 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 14: 'PERF_PAPC_CLPR_CULL_PRIM', - 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', - 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', - 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', - 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', - 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', - 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 39: 'PERF_PAPC_CLSM_NULL_PRIM', - 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', - 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', - 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', - 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', - 49: 'PERF_PAPC_SU_INPUT_PRIM', - 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', - 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 61: 'PERF_PAPC_SU_OUTPUT_PRIM', - 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', - 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', - 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 77: 'PERF_PAPC_PASX_REQ_IDLE', - 78: 'PERF_PAPC_PASX_REQ_BUSY', - 79: 'PERF_PAPC_PASX_REQ_STALLED', - 80: 'PERF_PAPC_PASX_REC_IDLE', - 81: 'PERF_PAPC_PASX_REC_BUSY', - 82: 'PERF_PAPC_PASX_REC_STARVED_SX', - 83: 'PERF_PAPC_PASX_REC_STALLED', - 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 86: 'PERF_PAPC_CCGSM_IDLE', - 87: 'PERF_PAPC_CCGSM_BUSY', - 88: 'PERF_PAPC_CCGSM_STALLED', - 89: 'PERF_PAPC_CLPRIM_IDLE', - 90: 'PERF_PAPC_CLPRIM_BUSY', - 91: 'PERF_PAPC_CLPRIM_STALLED', - 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 93: 'PERF_PAPC_CLIPSM_IDLE', - 94: 'PERF_PAPC_CLIPSM_BUSY', - 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', - 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 100: 'PERF_PAPC_CLIPGA_IDLE', - 101: 'PERF_PAPC_CLIPGA_BUSY', - 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 103: 'PERF_PAPC_CLIPGA_STALLED', - 104: 'PERF_PAPC_CLIP_IDLE', - 105: 'PERF_PAPC_CLIP_BUSY', - 106: 'PERF_PAPC_SU_IDLE', - 107: 'PERF_PAPC_SU_BUSY', - 108: 'PERF_PAPC_SU_STARVED_CLIP', - 109: 'PERF_PAPC_SU_STALLED_SC', - 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', - 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', - 112: 'PERF_PAPC_PA_REG_SCLK_VLD', - 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 114: 'PERF_PAPC_PASX_SE0_REQ', - 115: 'PERF_PAPC_PASX_SE1_REQ', - 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', - 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', - 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 131: 'PERF_PAPC_SU_SE0_STALLED_SC', - 132: 'PERF_PAPC_SU_SE1_STALLED_SC', - 133: 'PERF_PAPC_SU_SE01_STALLED_SC', - 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 135: 'PERF_PAPC_SU_CULLED_PRIM', - 136: 'PERF_PAPC_SU_OUTPUT_EOPG', - 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 151: 'PERF_PAPC_SU_SE2_STALLED_SC', - 152: 'PERF_PAPC_SU_SE3_STALLED_SC', - 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', - 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', - 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', - 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', - 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', - 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', - 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', - 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 179: 'PERF_PA_VERTEX_FIFO_FULL', - 180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', - 182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', - 185: 'PERF_PA_PIPE0_SWITCHED_GEN', - 186: 'PERF_PA_PIPE1_SWITCHED_GEN', - 188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', - 193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', - 196: 'PERF_ENGG_CSB_NULL_SUBGROUP', - 197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 198: 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', - 200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', - 202: 'PERF_ENGG_CSB_DELAY_BIN00', - 203: 'PERF_ENGG_CSB_DELAY_BIN01', - 204: 'PERF_ENGG_CSB_DELAY_BIN02', - 205: 'PERF_ENGG_CSB_DELAY_BIN03', - 206: 'PERF_ENGG_CSB_DELAY_BIN04', - 207: 'PERF_ENGG_CSB_DELAY_BIN05', - 208: 'PERF_ENGG_CSB_DELAY_BIN06', - 209: 'PERF_ENGG_CSB_DELAY_BIN07', - 210: 'PERF_ENGG_CSB_DELAY_BIN08', - 211: 'PERF_ENGG_CSB_DELAY_BIN09', - 212: 'PERF_ENGG_CSB_DELAY_BIN10', - 213: 'PERF_ENGG_CSB_DELAY_BIN11', - 214: 'PERF_ENGG_CSB_DELAY_BIN12', - 215: 'PERF_ENGG_CSB_DELAY_BIN13', - 216: 'PERF_ENGG_CSB_DELAY_BIN14', - 217: 'PERF_ENGG_CSB_DELAY_BIN15', - 218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00', - 219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01', - 220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02', - 221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03', - 222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04', - 223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05', - 224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06', - 225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07', - 226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08', - 227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09', - 228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10', - 229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', - 231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', - 232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', - 233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', - 234: 'PERF_ENGG_INDEX_REQ_STARVED', - 235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', - 259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', - 260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', - 261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', - 262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', - 263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 269: 'PERF_ENGG_POS_REQ_STARVED', - 270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 271: 'PERF_ENGG_BUSY', - 272: 'PERF_CLIPSM_CULL_PRIMS_CNT', - 273: 'PERF_PH_SEND_1_SC', - 274: 'PERF_PH_SEND_2_SC', - 275: 'PERF_PH_SEND_3_SC', - 276: 'PERF_PH_SEND_4_SC', - 277: 'PERF_OUTPUT_PRIM_1_SC', - 278: 'PERF_OUTPUT_PRIM_2_SC', - 279: 'PERF_OUTPUT_PRIM_3_SC', - 280: 'PERF_OUTPUT_PRIM_4_SC', -} -PERF_PAPC_PASX_REQ = 0 -PERF_PAPC_PASX_DISABLE_PIPE = 1 -PERF_PAPC_PASX_FIRST_VECTOR = 2 -PERF_PAPC_PASX_SECOND_VECTOR = 3 -PERF_PAPC_PASX_FIRST_DEAD = 4 -PERF_PAPC_PASX_SECOND_DEAD = 5 -PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 -PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 -PERF_PAPC_PA_INPUT_PRIM = 8 -PERF_PAPC_PA_INPUT_NULL_PRIM = 9 -PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 -PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 -PERF_PAPC_CLPR_CULL_PRIM = 14 -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 -PERF_PAPC_CLPR_VV_CULL_PRIM = 16 -PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 -PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 -PERF_PAPC_CLSM_NULL_PRIM = 39 -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 -PERF_PAPC_SU_INPUT_PRIM = 49 -PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 -PERF_PAPC_SU_INPUT_NULL_PRIM = 51 -PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 -PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 -PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 -PERF_PAPC_SU_OUTPUT_PRIM = 61 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 -PERF_PAPC_PASX_REQ_IDLE = 77 -PERF_PAPC_PASX_REQ_BUSY = 78 -PERF_PAPC_PASX_REQ_STALLED = 79 -PERF_PAPC_PASX_REC_IDLE = 80 -PERF_PAPC_PASX_REC_BUSY = 81 -PERF_PAPC_PASX_REC_STARVED_SX = 82 -PERF_PAPC_PASX_REC_STALLED = 83 -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 -PERF_PAPC_CCGSM_IDLE = 86 -PERF_PAPC_CCGSM_BUSY = 87 -PERF_PAPC_CCGSM_STALLED = 88 -PERF_PAPC_CLPRIM_IDLE = 89 -PERF_PAPC_CLPRIM_BUSY = 90 -PERF_PAPC_CLPRIM_STALLED = 91 -PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 -PERF_PAPC_CLIPSM_IDLE = 93 -PERF_PAPC_CLIPSM_BUSY = 94 -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 -PERF_PAPC_CLIPGA_IDLE = 100 -PERF_PAPC_CLIPGA_BUSY = 101 -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 -PERF_PAPC_CLIPGA_STALLED = 103 -PERF_PAPC_CLIP_IDLE = 104 -PERF_PAPC_CLIP_BUSY = 105 -PERF_PAPC_SU_IDLE = 106 -PERF_PAPC_SU_BUSY = 107 -PERF_PAPC_SU_STARVED_CLIP = 108 -PERF_PAPC_SU_STALLED_SC = 109 -PERF_PAPC_CL_DYN_SCLK_VLD = 110 -PERF_PAPC_SU_DYN_SCLK_VLD = 111 -PERF_PAPC_PA_REG_SCLK_VLD = 112 -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 -PERF_PAPC_PASX_SE0_REQ = 114 -PERF_PAPC_PASX_SE1_REQ = 115 -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 -PERF_PAPC_SU_SE0_STALLED_SC = 131 -PERF_PAPC_SU_SE1_STALLED_SC = 132 -PERF_PAPC_SU_SE01_STALLED_SC = 133 -PERF_PAPC_CLSM_CLIPPING_PRIM = 134 -PERF_PAPC_SU_CULLED_PRIM = 135 -PERF_PAPC_SU_OUTPUT_EOPG = 136 -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 -PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 -PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 -PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 -PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 -PERF_PAPC_SU_SE2_STALLED_SC = 151 -PERF_PAPC_SU_SE3_STALLED_SC = 152 -PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 -PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 -PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 -PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 -PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 -PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 -PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 -PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 -PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 -PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 -PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 -PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 -PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 -PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 -PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 -PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 -PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170 -PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171 -PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172 -PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173 -PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174 -PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175 -PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176 -PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177 -PERF_PA_VERTEX_FIFO_FULL = 179 -PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180 -PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182 -PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183 -PERF_PA_PIPE0_SWITCHED_GEN = 185 -PERF_PA_PIPE1_SWITCHED_GEN = 186 -PERF_ENGG_CSB_MACHINE_IS_STARVED = 188 -PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189 -PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190 -PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191 -PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192 -PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193 -PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194 -PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195 -PERF_ENGG_CSB_NULL_SUBGROUP = 196 -PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197 -PERF_ENGG_CSB_GE_MEMORY_FULL = 198 -PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199 -PERF_ENGG_CSB_SPI_MEMORY_FULL = 200 -PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201 -PERF_ENGG_CSB_DELAY_BIN00 = 202 -PERF_ENGG_CSB_DELAY_BIN01 = 203 -PERF_ENGG_CSB_DELAY_BIN02 = 204 -PERF_ENGG_CSB_DELAY_BIN03 = 205 -PERF_ENGG_CSB_DELAY_BIN04 = 206 -PERF_ENGG_CSB_DELAY_BIN05 = 207 -PERF_ENGG_CSB_DELAY_BIN06 = 208 -PERF_ENGG_CSB_DELAY_BIN07 = 209 -PERF_ENGG_CSB_DELAY_BIN08 = 210 -PERF_ENGG_CSB_DELAY_BIN09 = 211 -PERF_ENGG_CSB_DELAY_BIN10 = 212 -PERF_ENGG_CSB_DELAY_BIN11 = 213 -PERF_ENGG_CSB_DELAY_BIN12 = 214 -PERF_ENGG_CSB_DELAY_BIN13 = 215 -PERF_ENGG_CSB_DELAY_BIN14 = 216 -PERF_ENGG_CSB_DELAY_BIN15 = 217 -PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218 -PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219 -PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220 -PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221 -PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222 -PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223 -PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224 -PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225 -PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226 -PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227 -PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228 -PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229 -PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230 -PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231 -PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232 -PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233 -PERF_ENGG_INDEX_REQ_STARVED = 234 -PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235 -PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236 -PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239 -PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244 -PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245 -PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246 -PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268 -PERF_ENGG_POS_REQ_STARVED = 269 -PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270 -PERF_ENGG_BUSY = 271 -PERF_CLIPSM_CULL_PRIMS_CNT = 272 -PERF_PH_SEND_1_SC = 273 -PERF_PH_SEND_2_SC = 274 -PERF_PH_SEND_3_SC = 275 -PERF_PH_SEND_4_SC = 276 -PERF_OUTPUT_PRIM_1_SC = 277 -PERF_OUTPUT_PRIM_2_SC = 278 -PERF_OUTPUT_PRIM_3_SC = 279 -PERF_OUTPUT_PRIM_4_SC = 280 -SU_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PH_PERFCNT_SEL' -PH_PERFCNT_SEL__enumvalues = { - 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 8: 'PH_PERF_SEL_SC0_ARB_BUSY', - 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 16: 'PH_PERF_SEL_SC0_SEND', - 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', - 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', - 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', - 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE', - 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', - 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', - 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', - 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', - 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', - 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', - 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE', - 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', - 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', - 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', - 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', - 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', - 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', - 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE', - 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', - 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', - 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', - 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', - 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', - 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', - 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE', - 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', - 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', - 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', - 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', - 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', - 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', - 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE', - 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', - 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', - 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', - 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', - 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', - 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', - 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE', - 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', - 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', - 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', - 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', - 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', - 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', - 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE', - 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', - 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', - 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', - 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', - 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', - 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', - 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE', - 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', - 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', - 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', - 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 128: 'PH_PERF_SEL_SC1_ARB_BUSY', - 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 136: 'PH_PERF_SEL_SC1_SEND', - 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', - 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', - 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', - 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE', - 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', - 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', - 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', - 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', - 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', - 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', - 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE', - 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', - 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', - 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', - 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', - 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', - 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', - 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE', - 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', - 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', - 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', - 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', - 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', - 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', - 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE', - 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', - 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', - 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', - 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', - 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', - 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', - 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE', - 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', - 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', - 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', - 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', - 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', - 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', - 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE', - 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', - 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', - 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', - 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', - 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', - 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', - 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE', - 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', - 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', - 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', - 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', - 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', - 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', - 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE', - 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', - 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', - 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', - 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 248: 'PH_PERF_SEL_SC2_ARB_BUSY', - 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 256: 'PH_PERF_SEL_SC2_SEND', - 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', - 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', - 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', - 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE', - 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', - 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', - 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', - 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', - 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', - 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', - 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE', - 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', - 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', - 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', - 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', - 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', - 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', - 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE', - 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', - 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', - 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', - 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', - 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', - 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', - 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE', - 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', - 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', - 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', - 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', - 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', - 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', - 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE', - 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', - 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', - 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', - 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', - 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', - 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', - 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE', - 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', - 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', - 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', - 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', - 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', - 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', - 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE', - 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', - 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', - 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', - 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', - 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', - 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', - 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE', - 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', - 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', - 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', - 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 368: 'PH_PERF_SEL_SC3_ARB_BUSY', - 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 376: 'PH_PERF_SEL_SC3_SEND', - 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', - 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', - 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', - 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE', - 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', - 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', - 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', - 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', - 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', - 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', - 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE', - 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', - 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', - 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', - 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', - 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', - 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', - 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE', - 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', - 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', - 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', - 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', - 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', - 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', - 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE', - 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', - 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', - 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', - 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', - 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', - 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', - 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE', - 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', - 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', - 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', - 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', - 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', - 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', - 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE', - 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', - 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', - 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', - 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', - 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', - 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', - 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE', - 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', - 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', - 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', - 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', - 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', - 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', - 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE', - 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', - 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', - 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', - 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 488: 'PH_PERF_SEL_SC4_ARB_BUSY', - 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 496: 'PH_PERF_SEL_SC4_SEND', - 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', - 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', - 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', - 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE', - 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', - 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', - 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', - 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', - 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', - 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', - 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE', - 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', - 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', - 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', - 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', - 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', - 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', - 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE', - 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', - 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', - 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', - 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', - 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', - 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', - 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE', - 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', - 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', - 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', - 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', - 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', - 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', - 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE', - 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', - 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', - 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', - 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', - 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', - 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', - 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE', - 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', - 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', - 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', - 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', - 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', - 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', - 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE', - 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', - 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', - 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', - 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', - 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', - 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', - 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE', - 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', - 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', - 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', - 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 608: 'PH_PERF_SEL_SC5_ARB_BUSY', - 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 616: 'PH_PERF_SEL_SC5_SEND', - 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', - 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', - 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', - 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE', - 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', - 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', - 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', - 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', - 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', - 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', - 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE', - 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', - 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', - 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', - 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', - 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', - 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', - 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE', - 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', - 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', - 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', - 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', - 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', - 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', - 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE', - 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', - 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', - 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', - 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', - 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', - 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', - 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE', - 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', - 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', - 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', - 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', - 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', - 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', - 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE', - 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', - 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', - 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', - 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', - 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', - 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', - 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE', - 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', - 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', - 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', - 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', - 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', - 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', - 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE', - 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', - 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', - 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', - 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 728: 'PH_PERF_SEL_SC6_ARB_BUSY', - 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 736: 'PH_PERF_SEL_SC6_SEND', - 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', - 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', - 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', - 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE', - 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', - 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', - 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', - 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', - 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', - 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', - 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE', - 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', - 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', - 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', - 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', - 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', - 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', - 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE', - 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', - 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', - 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', - 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', - 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', - 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', - 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE', - 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', - 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', - 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', - 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', - 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', - 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', - 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE', - 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', - 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', - 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', - 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', - 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', - 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', - 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE', - 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', - 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', - 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', - 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', - 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', - 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', - 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE', - 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', - 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', - 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', - 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', - 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', - 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', - 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE', - 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', - 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', - 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', - 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 848: 'PH_PERF_SEL_SC7_ARB_BUSY', - 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 856: 'PH_PERF_SEL_SC7_SEND', - 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', - 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', - 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', - 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE', - 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', - 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', - 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', - 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', - 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', - 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', - 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE', - 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', - 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', - 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', - 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', - 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', - 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', - 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE', - 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', - 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', - 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', - 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', - 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', - 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', - 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE', - 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', - 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', - 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', - 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', - 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', - 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', - 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE', - 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', - 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', - 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', - 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', - 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', - 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', - 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE', - 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', - 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', - 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', - 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', - 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', - 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', - 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE', - 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', - 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', - 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', - 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', - 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', - 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', - 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE', - 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', - 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', - 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', - 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 992: 'PH_PERF_SC0_FIFO_STATUS_0', - 993: 'PH_PERF_SC0_FIFO_STATUS_1', - 994: 'PH_PERF_SC0_FIFO_STATUS_2', - 995: 'PH_PERF_SC0_FIFO_STATUS_3', - 996: 'PH_PERF_SC1_FIFO_STATUS_0', - 997: 'PH_PERF_SC1_FIFO_STATUS_1', - 998: 'PH_PERF_SC1_FIFO_STATUS_2', - 999: 'PH_PERF_SC1_FIFO_STATUS_3', - 1000: 'PH_PERF_SC2_FIFO_STATUS_0', - 1001: 'PH_PERF_SC2_FIFO_STATUS_1', - 1002: 'PH_PERF_SC2_FIFO_STATUS_2', - 1003: 'PH_PERF_SC2_FIFO_STATUS_3', - 1004: 'PH_PERF_SC3_FIFO_STATUS_0', - 1005: 'PH_PERF_SC3_FIFO_STATUS_1', - 1006: 'PH_PERF_SC3_FIFO_STATUS_2', - 1007: 'PH_PERF_SC3_FIFO_STATUS_3', - 1008: 'PH_PERF_SC4_FIFO_STATUS_0', - 1009: 'PH_PERF_SC4_FIFO_STATUS_1', - 1010: 'PH_PERF_SC4_FIFO_STATUS_2', - 1011: 'PH_PERF_SC4_FIFO_STATUS_3', - 1012: 'PH_PERF_SC5_FIFO_STATUS_0', - 1013: 'PH_PERF_SC5_FIFO_STATUS_1', - 1014: 'PH_PERF_SC5_FIFO_STATUS_2', - 1015: 'PH_PERF_SC5_FIFO_STATUS_3', - 1016: 'PH_PERF_SC6_FIFO_STATUS_0', - 1017: 'PH_PERF_SC6_FIFO_STATUS_1', - 1018: 'PH_PERF_SC6_FIFO_STATUS_2', - 1019: 'PH_PERF_SC6_FIFO_STATUS_3', - 1020: 'PH_PERF_SC7_FIFO_STATUS_0', - 1021: 'PH_PERF_SC7_FIFO_STATUS_1', - 1022: 'PH_PERF_SC7_FIFO_STATUS_2', - 1023: 'PH_PERF_SC7_FIFO_STATUS_3', -} -PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 -PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 -PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 -PH_PERF_SEL_SC0_ARB_BUSY = 8 -PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 -PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 -PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 -PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 -PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 -PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 -PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 -PH_PERF_SEL_SC0_SEND = 16 -PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 -PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 -PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 -PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 -PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 -PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 -PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 -PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 -PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 -PH_PERF_SEL_SC0_PA0_NULL_WE = 28 -PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 -PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 -PH_PERF_SEL_SC0_PA0_LPOV_WE = 31 -PH_PERF_SEL_SC0_PA0_EOP_WE = 32 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 -PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 -PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 -PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 -PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 -PH_PERF_SEL_SC0_PA1_NULL_WE = 40 -PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 -PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 -PH_PERF_SEL_SC0_PA1_LPOV_WE = 43 -PH_PERF_SEL_SC0_PA1_EOP_WE = 44 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 -PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 -PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 -PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 -PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 -PH_PERF_SEL_SC0_PA2_NULL_WE = 52 -PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 -PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 -PH_PERF_SEL_SC0_PA2_LPOV_WE = 55 -PH_PERF_SEL_SC0_PA2_EOP_WE = 56 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 -PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 -PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 -PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 -PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 -PH_PERF_SEL_SC0_PA3_NULL_WE = 64 -PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 -PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 -PH_PERF_SEL_SC0_PA3_LPOV_WE = 67 -PH_PERF_SEL_SC0_PA3_EOP_WE = 68 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 -PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 -PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 -PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 -PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 -PH_PERF_SEL_SC0_PA4_NULL_WE = 76 -PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 -PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 -PH_PERF_SEL_SC0_PA4_LPOV_WE = 79 -PH_PERF_SEL_SC0_PA4_EOP_WE = 80 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 -PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 -PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 -PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 -PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 -PH_PERF_SEL_SC0_PA5_NULL_WE = 88 -PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 -PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 -PH_PERF_SEL_SC0_PA5_LPOV_WE = 91 -PH_PERF_SEL_SC0_PA5_EOP_WE = 92 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 -PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 -PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 -PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 -PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 -PH_PERF_SEL_SC0_PA6_NULL_WE = 100 -PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 -PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 -PH_PERF_SEL_SC0_PA6_LPOV_WE = 103 -PH_PERF_SEL_SC0_PA6_EOP_WE = 104 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 -PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 -PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 -PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 -PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 -PH_PERF_SEL_SC0_PA7_NULL_WE = 112 -PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 -PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 -PH_PERF_SEL_SC0_PA7_LPOV_WE = 115 -PH_PERF_SEL_SC0_PA7_EOP_WE = 116 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 -PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 -PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119 -PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 -PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 -PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 -PH_PERF_SEL_SC1_ARB_BUSY = 128 -PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 -PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 -PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 -PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 -PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 -PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 -PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 -PH_PERF_SEL_SC1_SEND = 136 -PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 -PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 -PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 -PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 -PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 -PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 -PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 -PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 -PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 -PH_PERF_SEL_SC1_PA0_NULL_WE = 148 -PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 -PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 -PH_PERF_SEL_SC1_PA0_LPOV_WE = 151 -PH_PERF_SEL_SC1_PA0_EOP_WE = 152 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 -PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 -PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 -PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 -PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 -PH_PERF_SEL_SC1_PA1_NULL_WE = 160 -PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 -PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 -PH_PERF_SEL_SC1_PA1_LPOV_WE = 163 -PH_PERF_SEL_SC1_PA1_EOP_WE = 164 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 -PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 -PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 -PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 -PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 -PH_PERF_SEL_SC1_PA2_NULL_WE = 172 -PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 -PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 -PH_PERF_SEL_SC1_PA2_LPOV_WE = 175 -PH_PERF_SEL_SC1_PA2_EOP_WE = 176 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 -PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 -PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 -PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 -PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 -PH_PERF_SEL_SC1_PA3_NULL_WE = 184 -PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 -PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 -PH_PERF_SEL_SC1_PA3_LPOV_WE = 187 -PH_PERF_SEL_SC1_PA3_EOP_WE = 188 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 -PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 -PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 -PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 -PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 -PH_PERF_SEL_SC1_PA4_NULL_WE = 196 -PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 -PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 -PH_PERF_SEL_SC1_PA4_LPOV_WE = 199 -PH_PERF_SEL_SC1_PA4_EOP_WE = 200 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 -PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 -PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 -PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 -PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 -PH_PERF_SEL_SC1_PA5_NULL_WE = 208 -PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 -PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 -PH_PERF_SEL_SC1_PA5_LPOV_WE = 211 -PH_PERF_SEL_SC1_PA5_EOP_WE = 212 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 -PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 -PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 -PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 -PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 -PH_PERF_SEL_SC1_PA6_NULL_WE = 220 -PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 -PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 -PH_PERF_SEL_SC1_PA6_LPOV_WE = 223 -PH_PERF_SEL_SC1_PA6_EOP_WE = 224 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 -PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 -PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 -PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 -PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 -PH_PERF_SEL_SC1_PA7_NULL_WE = 232 -PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 -PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 -PH_PERF_SEL_SC1_PA7_LPOV_WE = 235 -PH_PERF_SEL_SC1_PA7_EOP_WE = 236 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 -PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 -PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239 -PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 -PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 -PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 -PH_PERF_SEL_SC2_ARB_BUSY = 248 -PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 -PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 -PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 -PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 -PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 -PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 -PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 -PH_PERF_SEL_SC2_SEND = 256 -PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 -PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 -PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 -PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 -PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 -PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 -PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 -PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 -PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 -PH_PERF_SEL_SC2_PA0_NULL_WE = 268 -PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 -PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 -PH_PERF_SEL_SC2_PA0_LPOV_WE = 271 -PH_PERF_SEL_SC2_PA0_EOP_WE = 272 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 -PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 -PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 -PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 -PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 -PH_PERF_SEL_SC2_PA1_NULL_WE = 280 -PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 -PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 -PH_PERF_SEL_SC2_PA1_LPOV_WE = 283 -PH_PERF_SEL_SC2_PA1_EOP_WE = 284 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 -PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 -PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 -PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 -PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 -PH_PERF_SEL_SC2_PA2_NULL_WE = 292 -PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 -PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 -PH_PERF_SEL_SC2_PA2_LPOV_WE = 295 -PH_PERF_SEL_SC2_PA2_EOP_WE = 296 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 -PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 -PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 -PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 -PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 -PH_PERF_SEL_SC2_PA3_NULL_WE = 304 -PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 -PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 -PH_PERF_SEL_SC2_PA3_LPOV_WE = 307 -PH_PERF_SEL_SC2_PA3_EOP_WE = 308 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 -PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 -PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 -PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 -PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 -PH_PERF_SEL_SC2_PA4_NULL_WE = 316 -PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 -PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 -PH_PERF_SEL_SC2_PA4_LPOV_WE = 319 -PH_PERF_SEL_SC2_PA4_EOP_WE = 320 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 -PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 -PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 -PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 -PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 -PH_PERF_SEL_SC2_PA5_NULL_WE = 328 -PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 -PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 -PH_PERF_SEL_SC2_PA5_LPOV_WE = 331 -PH_PERF_SEL_SC2_PA5_EOP_WE = 332 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 -PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 -PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 -PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 -PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 -PH_PERF_SEL_SC2_PA6_NULL_WE = 340 -PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 -PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 -PH_PERF_SEL_SC2_PA6_LPOV_WE = 343 -PH_PERF_SEL_SC2_PA6_EOP_WE = 344 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 -PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 -PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 -PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 -PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 -PH_PERF_SEL_SC2_PA7_NULL_WE = 352 -PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 -PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 -PH_PERF_SEL_SC2_PA7_LPOV_WE = 355 -PH_PERF_SEL_SC2_PA7_EOP_WE = 356 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 -PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 -PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359 -PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 -PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 -PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 -PH_PERF_SEL_SC3_ARB_BUSY = 368 -PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 -PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 -PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 -PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 -PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 -PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 -PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 -PH_PERF_SEL_SC3_SEND = 376 -PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 -PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 -PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 -PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 -PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 -PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 -PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 -PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 -PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 -PH_PERF_SEL_SC3_PA0_NULL_WE = 388 -PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 -PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 -PH_PERF_SEL_SC3_PA0_LPOV_WE = 391 -PH_PERF_SEL_SC3_PA0_EOP_WE = 392 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 -PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 -PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 -PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 -PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 -PH_PERF_SEL_SC3_PA1_NULL_WE = 400 -PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 -PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 -PH_PERF_SEL_SC3_PA1_LPOV_WE = 403 -PH_PERF_SEL_SC3_PA1_EOP_WE = 404 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 -PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 -PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 -PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 -PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 -PH_PERF_SEL_SC3_PA2_NULL_WE = 412 -PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 -PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 -PH_PERF_SEL_SC3_PA2_LPOV_WE = 415 -PH_PERF_SEL_SC3_PA2_EOP_WE = 416 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 -PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 -PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 -PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 -PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 -PH_PERF_SEL_SC3_PA3_NULL_WE = 424 -PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 -PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 -PH_PERF_SEL_SC3_PA3_LPOV_WE = 427 -PH_PERF_SEL_SC3_PA3_EOP_WE = 428 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 -PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 -PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 -PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 -PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 -PH_PERF_SEL_SC3_PA4_NULL_WE = 436 -PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 -PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 -PH_PERF_SEL_SC3_PA4_LPOV_WE = 439 -PH_PERF_SEL_SC3_PA4_EOP_WE = 440 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 -PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 -PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 -PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 -PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 -PH_PERF_SEL_SC3_PA5_NULL_WE = 448 -PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 -PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 -PH_PERF_SEL_SC3_PA5_LPOV_WE = 451 -PH_PERF_SEL_SC3_PA5_EOP_WE = 452 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 -PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 -PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 -PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 -PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 -PH_PERF_SEL_SC3_PA6_NULL_WE = 460 -PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 -PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 -PH_PERF_SEL_SC3_PA6_LPOV_WE = 463 -PH_PERF_SEL_SC3_PA6_EOP_WE = 464 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 -PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 -PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 -PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 -PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 -PH_PERF_SEL_SC3_PA7_NULL_WE = 472 -PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 -PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 -PH_PERF_SEL_SC3_PA7_LPOV_WE = 475 -PH_PERF_SEL_SC3_PA7_EOP_WE = 476 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 -PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 -PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479 -PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 -PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 -PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 -PH_PERF_SEL_SC4_ARB_BUSY = 488 -PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 -PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 -PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 -PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 -PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 -PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 -PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 -PH_PERF_SEL_SC4_SEND = 496 -PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 -PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 -PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 -PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 -PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 -PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 -PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 -PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 -PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 -PH_PERF_SEL_SC4_PA0_NULL_WE = 508 -PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 -PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 -PH_PERF_SEL_SC4_PA0_LPOV_WE = 511 -PH_PERF_SEL_SC4_PA0_EOP_WE = 512 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 -PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 -PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 -PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 -PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 -PH_PERF_SEL_SC4_PA1_NULL_WE = 520 -PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 -PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 -PH_PERF_SEL_SC4_PA1_LPOV_WE = 523 -PH_PERF_SEL_SC4_PA1_EOP_WE = 524 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 -PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 -PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 -PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 -PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 -PH_PERF_SEL_SC4_PA2_NULL_WE = 532 -PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 -PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 -PH_PERF_SEL_SC4_PA2_LPOV_WE = 535 -PH_PERF_SEL_SC4_PA2_EOP_WE = 536 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 -PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 -PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 -PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 -PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 -PH_PERF_SEL_SC4_PA3_NULL_WE = 544 -PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 -PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 -PH_PERF_SEL_SC4_PA3_LPOV_WE = 547 -PH_PERF_SEL_SC4_PA3_EOP_WE = 548 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 -PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 -PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 -PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 -PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 -PH_PERF_SEL_SC4_PA4_NULL_WE = 556 -PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 -PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 -PH_PERF_SEL_SC4_PA4_LPOV_WE = 559 -PH_PERF_SEL_SC4_PA4_EOP_WE = 560 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 -PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 -PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 -PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 -PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 -PH_PERF_SEL_SC4_PA5_NULL_WE = 568 -PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 -PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 -PH_PERF_SEL_SC4_PA5_LPOV_WE = 571 -PH_PERF_SEL_SC4_PA5_EOP_WE = 572 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 -PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 -PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 -PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 -PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 -PH_PERF_SEL_SC4_PA6_NULL_WE = 580 -PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 -PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 -PH_PERF_SEL_SC4_PA6_LPOV_WE = 583 -PH_PERF_SEL_SC4_PA6_EOP_WE = 584 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 -PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 -PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 -PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 -PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 -PH_PERF_SEL_SC4_PA7_NULL_WE = 592 -PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 -PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 -PH_PERF_SEL_SC4_PA7_LPOV_WE = 595 -PH_PERF_SEL_SC4_PA7_EOP_WE = 596 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 -PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 -PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599 -PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 -PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 -PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 -PH_PERF_SEL_SC5_ARB_BUSY = 608 -PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 -PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 -PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 -PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 -PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 -PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 -PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 -PH_PERF_SEL_SC5_SEND = 616 -PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 -PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 -PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 -PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 -PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 -PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 -PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 -PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 -PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 -PH_PERF_SEL_SC5_PA0_NULL_WE = 628 -PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 -PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 -PH_PERF_SEL_SC5_PA0_LPOV_WE = 631 -PH_PERF_SEL_SC5_PA0_EOP_WE = 632 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 -PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 -PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 -PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 -PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 -PH_PERF_SEL_SC5_PA1_NULL_WE = 640 -PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 -PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 -PH_PERF_SEL_SC5_PA1_LPOV_WE = 643 -PH_PERF_SEL_SC5_PA1_EOP_WE = 644 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 -PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 -PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 -PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 -PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 -PH_PERF_SEL_SC5_PA2_NULL_WE = 652 -PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 -PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 -PH_PERF_SEL_SC5_PA2_LPOV_WE = 655 -PH_PERF_SEL_SC5_PA2_EOP_WE = 656 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 -PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 -PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 -PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 -PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 -PH_PERF_SEL_SC5_PA3_NULL_WE = 664 -PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 -PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 -PH_PERF_SEL_SC5_PA3_LPOV_WE = 667 -PH_PERF_SEL_SC5_PA3_EOP_WE = 668 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 -PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 -PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 -PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 -PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 -PH_PERF_SEL_SC5_PA4_NULL_WE = 676 -PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 -PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 -PH_PERF_SEL_SC5_PA4_LPOV_WE = 679 -PH_PERF_SEL_SC5_PA4_EOP_WE = 680 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 -PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 -PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 -PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 -PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 -PH_PERF_SEL_SC5_PA5_NULL_WE = 688 -PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 -PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 -PH_PERF_SEL_SC5_PA5_LPOV_WE = 691 -PH_PERF_SEL_SC5_PA5_EOP_WE = 692 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 -PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 -PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 -PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 -PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 -PH_PERF_SEL_SC5_PA6_NULL_WE = 700 -PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 -PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 -PH_PERF_SEL_SC5_PA6_LPOV_WE = 703 -PH_PERF_SEL_SC5_PA6_EOP_WE = 704 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 -PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 -PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 -PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 -PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 -PH_PERF_SEL_SC5_PA7_NULL_WE = 712 -PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 -PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 -PH_PERF_SEL_SC5_PA7_LPOV_WE = 715 -PH_PERF_SEL_SC5_PA7_EOP_WE = 716 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 -PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 -PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719 -PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 -PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 -PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 -PH_PERF_SEL_SC6_ARB_BUSY = 728 -PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 -PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 -PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 -PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 -PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 -PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 -PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 -PH_PERF_SEL_SC6_SEND = 736 -PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 -PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 -PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 -PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 -PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 -PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 -PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 -PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 -PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 -PH_PERF_SEL_SC6_PA0_NULL_WE = 748 -PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 -PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 -PH_PERF_SEL_SC6_PA0_LPOV_WE = 751 -PH_PERF_SEL_SC6_PA0_EOP_WE = 752 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 -PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 -PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 -PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 -PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 -PH_PERF_SEL_SC6_PA1_NULL_WE = 760 -PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 -PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 -PH_PERF_SEL_SC6_PA1_LPOV_WE = 763 -PH_PERF_SEL_SC6_PA1_EOP_WE = 764 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 -PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 -PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 -PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 -PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 -PH_PERF_SEL_SC6_PA2_NULL_WE = 772 -PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 -PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 -PH_PERF_SEL_SC6_PA2_LPOV_WE = 775 -PH_PERF_SEL_SC6_PA2_EOP_WE = 776 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 -PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 -PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 -PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 -PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 -PH_PERF_SEL_SC6_PA3_NULL_WE = 784 -PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 -PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 -PH_PERF_SEL_SC6_PA3_LPOV_WE = 787 -PH_PERF_SEL_SC6_PA3_EOP_WE = 788 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 -PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 -PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 -PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 -PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 -PH_PERF_SEL_SC6_PA4_NULL_WE = 796 -PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 -PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 -PH_PERF_SEL_SC6_PA4_LPOV_WE = 799 -PH_PERF_SEL_SC6_PA4_EOP_WE = 800 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 -PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 -PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 -PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 -PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 -PH_PERF_SEL_SC6_PA5_NULL_WE = 808 -PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 -PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 -PH_PERF_SEL_SC6_PA5_LPOV_WE = 811 -PH_PERF_SEL_SC6_PA5_EOP_WE = 812 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 -PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 -PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 -PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 -PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 -PH_PERF_SEL_SC6_PA6_NULL_WE = 820 -PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 -PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 -PH_PERF_SEL_SC6_PA6_LPOV_WE = 823 -PH_PERF_SEL_SC6_PA6_EOP_WE = 824 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 -PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 -PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 -PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 -PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 -PH_PERF_SEL_SC6_PA7_NULL_WE = 832 -PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 -PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 -PH_PERF_SEL_SC6_PA7_LPOV_WE = 835 -PH_PERF_SEL_SC6_PA7_EOP_WE = 836 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 -PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 -PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839 -PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 -PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 -PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 -PH_PERF_SEL_SC7_ARB_BUSY = 848 -PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 -PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 -PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 -PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 -PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 -PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 -PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 -PH_PERF_SEL_SC7_SEND = 856 -PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 -PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 -PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 -PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 -PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 -PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 -PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 -PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 -PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 -PH_PERF_SEL_SC7_PA0_NULL_WE = 868 -PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 -PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 -PH_PERF_SEL_SC7_PA0_LPOV_WE = 871 -PH_PERF_SEL_SC7_PA0_EOP_WE = 872 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 -PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 -PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 -PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 -PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 -PH_PERF_SEL_SC7_PA1_NULL_WE = 880 -PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 -PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 -PH_PERF_SEL_SC7_PA1_LPOV_WE = 883 -PH_PERF_SEL_SC7_PA1_EOP_WE = 884 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 -PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 -PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 -PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 -PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 -PH_PERF_SEL_SC7_PA2_NULL_WE = 892 -PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 -PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 -PH_PERF_SEL_SC7_PA2_LPOV_WE = 895 -PH_PERF_SEL_SC7_PA2_EOP_WE = 896 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 -PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 -PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 -PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 -PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 -PH_PERF_SEL_SC7_PA3_NULL_WE = 904 -PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 -PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 -PH_PERF_SEL_SC7_PA3_LPOV_WE = 907 -PH_PERF_SEL_SC7_PA3_EOP_WE = 908 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 -PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 -PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 -PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 -PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 -PH_PERF_SEL_SC7_PA4_NULL_WE = 916 -PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 -PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 -PH_PERF_SEL_SC7_PA4_LPOV_WE = 919 -PH_PERF_SEL_SC7_PA4_EOP_WE = 920 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 -PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 -PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 -PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 -PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 -PH_PERF_SEL_SC7_PA5_NULL_WE = 928 -PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 -PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 -PH_PERF_SEL_SC7_PA5_LPOV_WE = 931 -PH_PERF_SEL_SC7_PA5_EOP_WE = 932 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 -PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 -PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 -PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 -PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 -PH_PERF_SEL_SC7_PA6_NULL_WE = 940 -PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 -PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 -PH_PERF_SEL_SC7_PA6_LPOV_WE = 943 -PH_PERF_SEL_SC7_PA6_EOP_WE = 944 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 -PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 -PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 -PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 -PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 -PH_PERF_SEL_SC7_PA7_NULL_WE = 952 -PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 -PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 -PH_PERF_SEL_SC7_PA7_LPOV_WE = 955 -PH_PERF_SEL_SC7_PA7_EOP_WE = 956 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 -PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 -PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959 -PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 -PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 -PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 -PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 -PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 -PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 -PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 -PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 -PH_PERF_SC0_FIFO_STATUS_0 = 992 -PH_PERF_SC0_FIFO_STATUS_1 = 993 -PH_PERF_SC0_FIFO_STATUS_2 = 994 -PH_PERF_SC0_FIFO_STATUS_3 = 995 -PH_PERF_SC1_FIFO_STATUS_0 = 996 -PH_PERF_SC1_FIFO_STATUS_1 = 997 -PH_PERF_SC1_FIFO_STATUS_2 = 998 -PH_PERF_SC1_FIFO_STATUS_3 = 999 -PH_PERF_SC2_FIFO_STATUS_0 = 1000 -PH_PERF_SC2_FIFO_STATUS_1 = 1001 -PH_PERF_SC2_FIFO_STATUS_2 = 1002 -PH_PERF_SC2_FIFO_STATUS_3 = 1003 -PH_PERF_SC3_FIFO_STATUS_0 = 1004 -PH_PERF_SC3_FIFO_STATUS_1 = 1005 -PH_PERF_SC3_FIFO_STATUS_2 = 1006 -PH_PERF_SC3_FIFO_STATUS_3 = 1007 -PH_PERF_SC4_FIFO_STATUS_0 = 1008 -PH_PERF_SC4_FIFO_STATUS_1 = 1009 -PH_PERF_SC4_FIFO_STATUS_2 = 1010 -PH_PERF_SC4_FIFO_STATUS_3 = 1011 -PH_PERF_SC5_FIFO_STATUS_0 = 1012 -PH_PERF_SC5_FIFO_STATUS_1 = 1013 -PH_PERF_SC5_FIFO_STATUS_2 = 1014 -PH_PERF_SC5_FIFO_STATUS_3 = 1015 -PH_PERF_SC6_FIFO_STATUS_0 = 1016 -PH_PERF_SC6_FIFO_STATUS_1 = 1017 -PH_PERF_SC6_FIFO_STATUS_2 = 1018 -PH_PERF_SC6_FIFO_STATUS_3 = 1019 -PH_PERF_SC7_FIFO_STATUS_0 = 1020 -PH_PERF_SC7_FIFO_STATUS_1 = 1021 -PH_PERF_SC7_FIFO_STATUS_2 = 1022 -PH_PERF_SC7_FIFO_STATUS_3 = 1023 -PH_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PhSPIstatusMode' -PhSPIstatusMode__enumvalues = { - 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 2: 'PH_SPI_MODE_DISABLED', -} -PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 -PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 -PH_SPI_MODE_DISABLED = 2 -PhSPIstatusMode = ctypes.c_uint32 # enum - -# values for enumeration 'RMIPerfSel' -RMIPerfSel__enumvalues = { - 0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', -} -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0 -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1 -RMIPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'GCRPerfSel' -GCRPerfSel__enumvalues = { - 0: 'GCR_PERF_SEL_NONE', - 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', - 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', - 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', - 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 33: 'GCR_PERF_SEL_CPC_ALL_REQ', - 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', - 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', - 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', - 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', - 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 47: 'GCR_PERF_SEL_CPC_TCP_REQ', - 48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 49: 'GCR_PERF_SEL_CPG_ALL_REQ', - 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', - 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', - 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', - 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', - 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 63: 'GCR_PERF_SEL_CPG_TCP_REQ', - 64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', - 65: 'GCR_PERF_SEL_CPF_ALL_REQ', - 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', - 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', - 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', - 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', - 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 79: 'GCR_PERF_SEL_CPF_TCP_REQ', - 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 81: 'GCR_PERF_SEL_VIRT_REQ', - 82: 'GCR_PERF_SEL_PHY_REQ', - 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 85: 'GCR_PERF_SEL_ALL_REQ', - 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 89: 'GCR_PERF_SEL_UTCL2_REQ', - 90: 'GCR_PERF_SEL_UTCL2_RET', - 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 94: 'GCR_PERF_SEL_RLC_ALL_REQ', - 95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', - 96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', - 101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 105: 'GCR_PERF_SEL_RLC_METADATA_REQ', - 106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', - 107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 108: 'GCR_PERF_SEL_RLC_TCP_REQ', - 109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', - 110: 'GCR_PERF_SEL_PM_ALL_REQ', - 111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', - 112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', - 117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 121: 'GCR_PERF_SEL_PM_METADATA_REQ', - 122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', - 123: 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 124: 'GCR_PERF_SEL_PM_TCP_REQ', - 125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', - 126: 'GCR_PERF_SEL_PIO_ALL_REQ', - 127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', - 128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', - 133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 137: 'GCR_PERF_SEL_PIO_METADATA_REQ', - 138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', - 139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 140: 'GCR_PERF_SEL_PIO_TCP_REQ', - 141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', -} -GCR_PERF_SEL_NONE = 0 -GCR_PERF_SEL_SDMA0_ALL_REQ = 1 -GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 -GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 -GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 -GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 -GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 -GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 -GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 -GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 -GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 -GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 -GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 -GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 -GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 -GCR_PERF_SEL_SDMA0_TCP_REQ = 15 -GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 -GCR_PERF_SEL_SDMA1_ALL_REQ = 17 -GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 -GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 -GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 -GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 -GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 -GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 -GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 -GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 -GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 -GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 -GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 -GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 -GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 -GCR_PERF_SEL_SDMA1_TCP_REQ = 31 -GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 -GCR_PERF_SEL_CPC_ALL_REQ = 33 -GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 -GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 -GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 -GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 -GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 -GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 -GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 -GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 -GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 -GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 -GCR_PERF_SEL_CPC_METADATA_REQ = 44 -GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 -GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 -GCR_PERF_SEL_CPC_TCP_REQ = 47 -GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48 -GCR_PERF_SEL_CPG_ALL_REQ = 49 -GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 -GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 -GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 -GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 -GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 -GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 -GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 -GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 -GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 -GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 -GCR_PERF_SEL_CPG_METADATA_REQ = 60 -GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 -GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 -GCR_PERF_SEL_CPG_TCP_REQ = 63 -GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64 -GCR_PERF_SEL_CPF_ALL_REQ = 65 -GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 -GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 -GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 -GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 -GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 -GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 -GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 -GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 -GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 -GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 -GCR_PERF_SEL_CPF_METADATA_REQ = 76 -GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 -GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 -GCR_PERF_SEL_CPF_TCP_REQ = 79 -GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 -GCR_PERF_SEL_VIRT_REQ = 81 -GCR_PERF_SEL_PHY_REQ = 82 -GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 -GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 -GCR_PERF_SEL_ALL_REQ = 85 -GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 -GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 -GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 -GCR_PERF_SEL_UTCL2_REQ = 89 -GCR_PERF_SEL_UTCL2_RET = 90 -GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 -GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 -GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 -GCR_PERF_SEL_RLC_ALL_REQ = 94 -GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95 -GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96 -GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97 -GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98 -GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99 -GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100 -GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101 -GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102 -GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103 -GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104 -GCR_PERF_SEL_RLC_METADATA_REQ = 105 -GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106 -GCR_PERF_SEL_RLC_SQC_INST_REQ = 107 -GCR_PERF_SEL_RLC_TCP_REQ = 108 -GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109 -GCR_PERF_SEL_PM_ALL_REQ = 110 -GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111 -GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112 -GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113 -GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114 -GCR_PERF_SEL_PM_GL2_ALL_REQ = 115 -GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116 -GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117 -GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118 -GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119 -GCR_PERF_SEL_PM_GL1_ALL_REQ = 120 -GCR_PERF_SEL_PM_METADATA_REQ = 121 -GCR_PERF_SEL_PM_SQC_DATA_REQ = 122 -GCR_PERF_SEL_PM_SQC_INST_REQ = 123 -GCR_PERF_SEL_PM_TCP_REQ = 124 -GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125 -GCR_PERF_SEL_PIO_ALL_REQ = 126 -GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127 -GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128 -GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129 -GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130 -GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131 -GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132 -GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133 -GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134 -GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135 -GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136 -GCR_PERF_SEL_PIO_METADATA_REQ = 137 -GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138 -GCR_PERF_SEL_PIO_SQC_INST_REQ = 139 -GCR_PERF_SEL_PIO_TCP_REQ = 140 -GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141 -GCRPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1PerfSel' -UTCL1PerfSel__enumvalues = { - 0: 'UTCL1_PERF_SEL_NONE', - 1: 'UTCL1_PERF_SEL_REQS', - 2: 'UTCL1_PERF_SEL_HITS', - 3: 'UTCL1_PERF_SEL_MISSES', - 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', - 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 6: 'UTCL1_PERF_SEL_UTCL2_REQS', - 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', - 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', - 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', - 13: 'UTCL1_PERF_SEL_RTNS', - 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', - 15: 'UTCL1_PERF_SEL_BYPASS_REQS', - 16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 19: 'UTCL1_PERF_SEL_CP_INVREQS', - 20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 21: 'UTCL1_PERF_SEL_RANGE_INVREQS', - 22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', -} -UTCL1_PERF_SEL_NONE = 0 -UTCL1_PERF_SEL_REQS = 1 -UTCL1_PERF_SEL_HITS = 2 -UTCL1_PERF_SEL_MISSES = 3 -UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 -UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 -UTCL1_PERF_SEL_UTCL2_REQS = 6 -UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 -UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 -UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 -UTCL1_PERF_SEL_STALL_MH_FULL = 10 -UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 -UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 -UTCL1_PERF_SEL_RTNS = 13 -UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 -UTCL1_PERF_SEL_BYPASS_REQS = 15 -UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16 -UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17 -UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18 -UTCL1_PERF_SEL_CP_INVREQS = 19 -UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20 -UTCL1_PERF_SEL_RANGE_INVREQS = 21 -UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22 -UTCL1PerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'IH_CLIENT_TYPE' -IH_CLIENT_TYPE__enumvalues = { - 0: 'IH_GFX_VMID_CLIENT', - 1: 'IH_MM_VMID_CLIENT', - 2: 'IH_MULTI_VMID_CLIENT', - 3: 'IH_CLIENT_TYPE_RESERVED', -} -IH_GFX_VMID_CLIENT = 0 -IH_MM_VMID_CLIENT = 1 -IH_MULTI_VMID_CLIENT = 2 -IH_CLIENT_TYPE_RESERVED = 3 -IH_CLIENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'IH_INTERFACE_TYPE' -IH_INTERFACE_TYPE__enumvalues = { - 0: 'IH_LEGACY_INTERFACE', - 1: 'IH_REGISTER_WRITE_INTERFACE', -} -IH_LEGACY_INTERFACE = 0 -IH_REGISTER_WRITE_INTERFACE = 1 -IH_INTERFACE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'IH_PERF_SEL' -IH_PERF_SEL__enumvalues = { - 0: 'IH_PERF_SEL_CYCLE', - 1: 'IH_PERF_SEL_IDLE', - 2: 'IH_PERF_SEL_INPUT_IDLE', - 3: 'IH_PERF_SEL_BUFFER_IDLE', - 4: 'IH_PERF_SEL_RB0_FULL', - 5: 'IH_PERF_SEL_RB0_OVERFLOW', - 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', - 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', - 9: 'IH_PERF_SEL_MC_WR_IDLE', - 10: 'IH_PERF_SEL_MC_WR_COUNT', - 11: 'IH_PERF_SEL_MC_WR_STALL', - 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', - 14: 'IH_PERF_SEL_BIF_LINE0_RISING', - 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', - 16: 'IH_PERF_SEL_RB1_FULL', - 17: 'IH_PERF_SEL_RB1_OVERFLOW', - 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', - 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', - 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', - 21: 'IH_PERF_SEL_RB2_FULL', - 22: 'IH_PERF_SEL_RB2_OVERFLOW', - 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', - 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', - 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', - 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 27: 'IH_PERF_SEL_SELF_IV_VALID', - 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', - 29: 'IH_PERF_SEL_RB0_FULL_VF0', - 30: 'IH_PERF_SEL_RB0_FULL_VF1', - 31: 'IH_PERF_SEL_RB0_FULL_VF2', - 32: 'IH_PERF_SEL_RB0_FULL_VF3', - 33: 'IH_PERF_SEL_RB0_FULL_VF4', - 34: 'IH_PERF_SEL_RB0_FULL_VF5', - 35: 'IH_PERF_SEL_RB0_FULL_VF6', - 36: 'IH_PERF_SEL_RB0_FULL_VF7', - 37: 'IH_PERF_SEL_RB0_FULL_VF8', - 38: 'IH_PERF_SEL_RB0_FULL_VF9', - 39: 'IH_PERF_SEL_RB0_FULL_VF10', - 40: 'IH_PERF_SEL_RB0_FULL_VF11', - 41: 'IH_PERF_SEL_RB0_FULL_VF12', - 42: 'IH_PERF_SEL_RB0_FULL_VF13', - 43: 'IH_PERF_SEL_RB0_FULL_VF14', - 44: 'IH_PERF_SEL_RB0_FULL_VF15', - 45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', - 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', - 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', - 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', - 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', - 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', - 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', - 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', - 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', - 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', - 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', - 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', - 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', - 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', - 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', - 93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', - 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', - 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', - 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', - 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', - 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', - 109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 141: 'IH_PERF_SEL_CLIENT0_INT', - 142: 'IH_PERF_SEL_CLIENT1_INT', - 143: 'IH_PERF_SEL_CLIENT2_INT', - 144: 'IH_PERF_SEL_CLIENT3_INT', - 145: 'IH_PERF_SEL_CLIENT4_INT', - 146: 'IH_PERF_SEL_CLIENT5_INT', - 147: 'IH_PERF_SEL_CLIENT6_INT', - 148: 'IH_PERF_SEL_CLIENT7_INT', - 149: 'IH_PERF_SEL_CLIENT8_INT', - 150: 'IH_PERF_SEL_CLIENT9_INT', - 151: 'IH_PERF_SEL_CLIENT10_INT', - 152: 'IH_PERF_SEL_CLIENT11_INT', - 153: 'IH_PERF_SEL_CLIENT12_INT', - 154: 'IH_PERF_SEL_CLIENT13_INT', - 155: 'IH_PERF_SEL_CLIENT14_INT', - 156: 'IH_PERF_SEL_CLIENT15_INT', - 157: 'IH_PERF_SEL_CLIENT16_INT', - 158: 'IH_PERF_SEL_CLIENT17_INT', - 159: 'IH_PERF_SEL_CLIENT18_INT', - 160: 'IH_PERF_SEL_CLIENT19_INT', - 161: 'IH_PERF_SEL_CLIENT20_INT', - 162: 'IH_PERF_SEL_CLIENT21_INT', - 163: 'IH_PERF_SEL_CLIENT22_INT', - 164: 'IH_PERF_SEL_CLIENT23_INT', - 165: 'IH_PERF_SEL_CLIENT24_INT', - 166: 'IH_PERF_SEL_CLIENT25_INT', - 167: 'IH_PERF_SEL_CLIENT26_INT', - 168: 'IH_PERF_SEL_CLIENT27_INT', - 169: 'IH_PERF_SEL_CLIENT28_INT', - 170: 'IH_PERF_SEL_CLIENT29_INT', - 171: 'IH_PERF_SEL_CLIENT30_INT', - 172: 'IH_PERF_SEL_CLIENT31_INT', - 173: 'IH_PERF_SEL_RB1_FULL_VF0', - 174: 'IH_PERF_SEL_RB1_FULL_VF1', - 175: 'IH_PERF_SEL_RB1_FULL_VF2', - 176: 'IH_PERF_SEL_RB1_FULL_VF3', - 177: 'IH_PERF_SEL_RB1_FULL_VF4', - 178: 'IH_PERF_SEL_RB1_FULL_VF5', - 179: 'IH_PERF_SEL_RB1_FULL_VF6', - 180: 'IH_PERF_SEL_RB1_FULL_VF7', - 181: 'IH_PERF_SEL_RB1_FULL_VF8', - 182: 'IH_PERF_SEL_RB1_FULL_VF9', - 183: 'IH_PERF_SEL_RB1_FULL_VF10', - 184: 'IH_PERF_SEL_RB1_FULL_VF11', - 185: 'IH_PERF_SEL_RB1_FULL_VF12', - 186: 'IH_PERF_SEL_RB1_FULL_VF13', - 187: 'IH_PERF_SEL_RB1_FULL_VF14', - 188: 'IH_PERF_SEL_RB1_FULL_VF15', - 189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', - 190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', - 192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', - 200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', - 202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', - 204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', - 206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', - 209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', - 211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', - 213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', - 215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', - 221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', - 225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', - 227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', - 229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', - 231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', - 237: 'IH_PERF_SEL_RB2_FULL_VF0', - 238: 'IH_PERF_SEL_RB2_FULL_VF1', - 239: 'IH_PERF_SEL_RB2_FULL_VF2', - 240: 'IH_PERF_SEL_RB2_FULL_VF3', - 241: 'IH_PERF_SEL_RB2_FULL_VF4', - 242: 'IH_PERF_SEL_RB2_FULL_VF5', - 243: 'IH_PERF_SEL_RB2_FULL_VF6', - 244: 'IH_PERF_SEL_RB2_FULL_VF7', - 245: 'IH_PERF_SEL_RB2_FULL_VF8', - 246: 'IH_PERF_SEL_RB2_FULL_VF9', - 247: 'IH_PERF_SEL_RB2_FULL_VF10', - 248: 'IH_PERF_SEL_RB2_FULL_VF11', - 249: 'IH_PERF_SEL_RB2_FULL_VF12', - 250: 'IH_PERF_SEL_RB2_FULL_VF13', - 251: 'IH_PERF_SEL_RB2_FULL_VF14', - 252: 'IH_PERF_SEL_RB2_FULL_VF15', - 253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', - 254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', - 256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', - 264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', - 266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', - 268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', - 270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', - 273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', - 275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', - 277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', - 279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', - 285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', - 289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', - 291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', - 293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', - 295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', - 301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', - 312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', - 329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', - 346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 352: 'IH_PERF_SEL_RB0_LOAD_RPTR', - 353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', - 354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', - 355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', - 357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', - 359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', - 361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', - 363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', - 369: 'IH_PERF_SEL_RB1_LOAD_RPTR', - 370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', - 371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', - 372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', - 374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', - 376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', - 378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', - 380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', - 386: 'IH_PERF_SEL_RB2_LOAD_RPTR', - 387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', - 388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', - 389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', - 391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', - 393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', - 395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', - 397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', -} -IH_PERF_SEL_CYCLE = 0 -IH_PERF_SEL_IDLE = 1 -IH_PERF_SEL_INPUT_IDLE = 2 -IH_PERF_SEL_BUFFER_IDLE = 3 -IH_PERF_SEL_RB0_FULL = 4 -IH_PERF_SEL_RB0_OVERFLOW = 5 -IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 -IH_PERF_SEL_RB0_WPTR_WRAP = 7 -IH_PERF_SEL_RB0_RPTR_WRAP = 8 -IH_PERF_SEL_MC_WR_IDLE = 9 -IH_PERF_SEL_MC_WR_COUNT = 10 -IH_PERF_SEL_MC_WR_STALL = 11 -IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 -IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 -IH_PERF_SEL_BIF_LINE0_RISING = 14 -IH_PERF_SEL_BIF_LINE0_FALLING = 15 -IH_PERF_SEL_RB1_FULL = 16 -IH_PERF_SEL_RB1_OVERFLOW = 17 -IH_PERF_SEL_COOKIE_REC_ERROR = 18 -IH_PERF_SEL_RB1_WPTR_WRAP = 19 -IH_PERF_SEL_RB1_RPTR_WRAP = 20 -IH_PERF_SEL_RB2_FULL = 21 -IH_PERF_SEL_RB2_OVERFLOW = 22 -IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 -IH_PERF_SEL_RB2_WPTR_WRAP = 24 -IH_PERF_SEL_RB2_RPTR_WRAP = 25 -IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 -IH_PERF_SEL_SELF_IV_VALID = 27 -IH_PERF_SEL_BUFFER_FIFO_FULL = 28 -IH_PERF_SEL_RB0_FULL_VF0 = 29 -IH_PERF_SEL_RB0_FULL_VF1 = 30 -IH_PERF_SEL_RB0_FULL_VF2 = 31 -IH_PERF_SEL_RB0_FULL_VF3 = 32 -IH_PERF_SEL_RB0_FULL_VF4 = 33 -IH_PERF_SEL_RB0_FULL_VF5 = 34 -IH_PERF_SEL_RB0_FULL_VF6 = 35 -IH_PERF_SEL_RB0_FULL_VF7 = 36 -IH_PERF_SEL_RB0_FULL_VF8 = 37 -IH_PERF_SEL_RB0_FULL_VF9 = 38 -IH_PERF_SEL_RB0_FULL_VF10 = 39 -IH_PERF_SEL_RB0_FULL_VF11 = 40 -IH_PERF_SEL_RB0_FULL_VF12 = 41 -IH_PERF_SEL_RB0_FULL_VF13 = 42 -IH_PERF_SEL_RB0_FULL_VF14 = 43 -IH_PERF_SEL_RB0_FULL_VF15 = 44 -IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45 -IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46 -IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47 -IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48 -IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49 -IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50 -IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51 -IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52 -IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53 -IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54 -IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55 -IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56 -IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57 -IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58 -IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59 -IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76 -IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77 -IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78 -IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79 -IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80 -IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81 -IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82 -IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83 -IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84 -IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85 -IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86 -IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87 -IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88 -IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89 -IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90 -IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91 -IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92 -IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93 -IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94 -IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95 -IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96 -IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97 -IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98 -IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99 -IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100 -IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101 -IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102 -IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103 -IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104 -IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105 -IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106 -IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107 -IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108 -IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109 -IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110 -IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111 -IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112 -IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113 -IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114 -IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115 -IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116 -IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117 -IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118 -IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119 -IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120 -IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121 -IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122 -IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123 -IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124 -IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125 -IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126 -IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127 -IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128 -IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129 -IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130 -IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131 -IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132 -IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133 -IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134 -IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135 -IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136 -IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137 -IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138 -IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139 -IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140 -IH_PERF_SEL_CLIENT0_INT = 141 -IH_PERF_SEL_CLIENT1_INT = 142 -IH_PERF_SEL_CLIENT2_INT = 143 -IH_PERF_SEL_CLIENT3_INT = 144 -IH_PERF_SEL_CLIENT4_INT = 145 -IH_PERF_SEL_CLIENT5_INT = 146 -IH_PERF_SEL_CLIENT6_INT = 147 -IH_PERF_SEL_CLIENT7_INT = 148 -IH_PERF_SEL_CLIENT8_INT = 149 -IH_PERF_SEL_CLIENT9_INT = 150 -IH_PERF_SEL_CLIENT10_INT = 151 -IH_PERF_SEL_CLIENT11_INT = 152 -IH_PERF_SEL_CLIENT12_INT = 153 -IH_PERF_SEL_CLIENT13_INT = 154 -IH_PERF_SEL_CLIENT14_INT = 155 -IH_PERF_SEL_CLIENT15_INT = 156 -IH_PERF_SEL_CLIENT16_INT = 157 -IH_PERF_SEL_CLIENT17_INT = 158 -IH_PERF_SEL_CLIENT18_INT = 159 -IH_PERF_SEL_CLIENT19_INT = 160 -IH_PERF_SEL_CLIENT20_INT = 161 -IH_PERF_SEL_CLIENT21_INT = 162 -IH_PERF_SEL_CLIENT22_INT = 163 -IH_PERF_SEL_CLIENT23_INT = 164 -IH_PERF_SEL_CLIENT24_INT = 165 -IH_PERF_SEL_CLIENT25_INT = 166 -IH_PERF_SEL_CLIENT26_INT = 167 -IH_PERF_SEL_CLIENT27_INT = 168 -IH_PERF_SEL_CLIENT28_INT = 169 -IH_PERF_SEL_CLIENT29_INT = 170 -IH_PERF_SEL_CLIENT30_INT = 171 -IH_PERF_SEL_CLIENT31_INT = 172 -IH_PERF_SEL_RB1_FULL_VF0 = 173 -IH_PERF_SEL_RB1_FULL_VF1 = 174 -IH_PERF_SEL_RB1_FULL_VF2 = 175 -IH_PERF_SEL_RB1_FULL_VF3 = 176 -IH_PERF_SEL_RB1_FULL_VF4 = 177 -IH_PERF_SEL_RB1_FULL_VF5 = 178 -IH_PERF_SEL_RB1_FULL_VF6 = 179 -IH_PERF_SEL_RB1_FULL_VF7 = 180 -IH_PERF_SEL_RB1_FULL_VF8 = 181 -IH_PERF_SEL_RB1_FULL_VF9 = 182 -IH_PERF_SEL_RB1_FULL_VF10 = 183 -IH_PERF_SEL_RB1_FULL_VF11 = 184 -IH_PERF_SEL_RB1_FULL_VF12 = 185 -IH_PERF_SEL_RB1_FULL_VF13 = 186 -IH_PERF_SEL_RB1_FULL_VF14 = 187 -IH_PERF_SEL_RB1_FULL_VF15 = 188 -IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189 -IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190 -IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191 -IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192 -IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193 -IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194 -IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195 -IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196 -IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197 -IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198 -IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199 -IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200 -IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201 -IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202 -IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203 -IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204 -IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205 -IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206 -IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207 -IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208 -IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209 -IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210 -IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211 -IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212 -IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213 -IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214 -IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215 -IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216 -IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217 -IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218 -IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219 -IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220 -IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221 -IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222 -IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223 -IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224 -IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225 -IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226 -IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227 -IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228 -IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229 -IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230 -IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231 -IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232 -IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233 -IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234 -IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235 -IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236 -IH_PERF_SEL_RB2_FULL_VF0 = 237 -IH_PERF_SEL_RB2_FULL_VF1 = 238 -IH_PERF_SEL_RB2_FULL_VF2 = 239 -IH_PERF_SEL_RB2_FULL_VF3 = 240 -IH_PERF_SEL_RB2_FULL_VF4 = 241 -IH_PERF_SEL_RB2_FULL_VF5 = 242 -IH_PERF_SEL_RB2_FULL_VF6 = 243 -IH_PERF_SEL_RB2_FULL_VF7 = 244 -IH_PERF_SEL_RB2_FULL_VF8 = 245 -IH_PERF_SEL_RB2_FULL_VF9 = 246 -IH_PERF_SEL_RB2_FULL_VF10 = 247 -IH_PERF_SEL_RB2_FULL_VF11 = 248 -IH_PERF_SEL_RB2_FULL_VF12 = 249 -IH_PERF_SEL_RB2_FULL_VF13 = 250 -IH_PERF_SEL_RB2_FULL_VF14 = 251 -IH_PERF_SEL_RB2_FULL_VF15 = 252 -IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253 -IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254 -IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255 -IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256 -IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257 -IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258 -IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259 -IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260 -IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261 -IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262 -IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263 -IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264 -IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265 -IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266 -IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267 -IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268 -IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269 -IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270 -IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271 -IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272 -IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273 -IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274 -IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275 -IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276 -IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277 -IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278 -IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279 -IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280 -IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281 -IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282 -IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283 -IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284 -IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285 -IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286 -IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287 -IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288 -IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289 -IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290 -IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291 -IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292 -IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293 -IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294 -IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295 -IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296 -IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297 -IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298 -IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299 -IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351 -IH_PERF_SEL_RB0_LOAD_RPTR = 352 -IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353 -IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354 -IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355 -IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356 -IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357 -IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358 -IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359 -IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360 -IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361 -IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362 -IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363 -IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364 -IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365 -IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366 -IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367 -IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368 -IH_PERF_SEL_RB1_LOAD_RPTR = 369 -IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370 -IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371 -IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372 -IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373 -IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374 -IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375 -IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376 -IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377 -IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378 -IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379 -IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380 -IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381 -IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382 -IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383 -IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384 -IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385 -IH_PERF_SEL_RB2_LOAD_RPTR = 386 -IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387 -IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388 -IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389 -IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390 -IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391 -IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392 -IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393 -IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394 -IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395 -IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396 -IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397 -IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398 -IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399 -IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400 -IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401 -IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402 -IH_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'IH_RING_ID' -IH_RING_ID__enumvalues = { - 0: 'IH_RING_ID_INTERRUPT', - 1: 'IH_RING_ID_REQUEST', - 2: 'IH_RING_ID_TRANSLATION', - 3: 'IH_RING_ID_RESERVED', -} -IH_RING_ID_INTERRUPT = 0 -IH_RING_ID_REQUEST = 1 -IH_RING_ID_TRANSLATION = 2 -IH_RING_ID_RESERVED = 3 -IH_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'IH_VF_RB_SELECT' -IH_VF_RB_SELECT__enumvalues = { - 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 1: 'IH_VF_RB_SELECT_IH_FCN_ID', - 2: 'IH_VF_RB_SELECT_PF', - 3: 'IH_VF_RB_SELECT_RESERVED', -} -IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 -IH_VF_RB_SELECT_IH_FCN_ID = 1 -IH_VF_RB_SELECT_PF = 2 -IH_VF_RB_SELECT_RESERVED = 3 -IH_VF_RB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SEM_PERF_SEL' -SEM_PERF_SEL__enumvalues = { - 0: 'SEM_PERF_SEL_CYCLE', - 1: 'SEM_PERF_SEL_IDLE', - 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', - 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', - 4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', - 5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', - 6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', - 7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', - 8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', - 9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', - 11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', - 12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', - 13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', - 14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', - 15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT', - 26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT', - 27: 'SEM_PERF_SEL_UVD_REQ_WAIT', - 28: 'SEM_PERF_SEL_UVD1_REQ_WAIT', - 29: 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 30: 'SEM_PERF_SEL_ACP_REQ_WAIT', - 31: 'SEM_PERF_SEL_ISP_REQ_WAIT', - 32: 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 33: 'SEM_PERF_SEL_VP8_REQ_WAIT', - 34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 172: 'SEM_PERF_SEL_MC_RD_REQ', - 173: 'SEM_PERF_SEL_MC_RD_RET', - 174: 'SEM_PERF_SEL_MC_WR_REQ', - 175: 'SEM_PERF_SEL_MC_WR_RET', - 176: 'SEM_PERF_SEL_ATC_REQ', - 177: 'SEM_PERF_SEL_ATC_RET', - 178: 'SEM_PERF_SEL_ATC_XNACK', - 179: 'SEM_PERF_SEL_ATC_INVALIDATION', - 180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', -} -SEM_PERF_SEL_CYCLE = 0 -SEM_PERF_SEL_IDLE = 1 -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 -SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4 -SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5 -SEM_PERF_SEL_UVD_REQ_SIGNAL = 6 -SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7 -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8 -SEM_PERF_SEL_ACP_REQ_SIGNAL = 9 -SEM_PERF_SEL_ISP_REQ_SIGNAL = 10 -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11 -SEM_PERF_SEL_VP8_REQ_SIGNAL = 12 -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13 -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22 -SEM_PERF_SEL_SDMA0_REQ_WAIT = 23 -SEM_PERF_SEL_SDMA1_REQ_WAIT = 24 -SEM_PERF_SEL_SDMA2_REQ_WAIT = 25 -SEM_PERF_SEL_SDMA3_REQ_WAIT = 26 -SEM_PERF_SEL_UVD_REQ_WAIT = 27 -SEM_PERF_SEL_UVD1_REQ_WAIT = 28 -SEM_PERF_SEL_VCE0_REQ_WAIT = 29 -SEM_PERF_SEL_ACP_REQ_WAIT = 30 -SEM_PERF_SEL_ISP_REQ_WAIT = 31 -SEM_PERF_SEL_VCE1_REQ_WAIT = 32 -SEM_PERF_SEL_VP8_REQ_WAIT = 33 -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34 -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43 -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44 -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45 -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46 -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47 -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48 -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49 -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50 -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51 -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52 -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53 -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54 -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55 -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56 -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57 -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58 -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59 -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60 -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61 -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62 -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63 -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64 -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65 -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66 -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67 -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68 -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69 -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70 -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71 -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72 -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73 -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74 -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75 -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76 -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77 -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78 -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79 -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80 -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81 -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82 -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83 -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84 -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85 -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86 -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87 -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88 -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89 -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90 -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91 -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92 -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93 -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94 -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95 -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96 -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97 -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98 -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99 -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100 -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101 -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102 -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103 -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104 -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105 -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106 -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107 -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108 -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109 -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110 -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111 -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112 -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113 -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114 -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115 -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116 -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117 -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118 -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119 -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120 -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121 -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122 -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123 -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124 -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125 -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126 -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127 -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128 -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129 -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130 -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131 -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132 -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133 -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134 -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135 -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136 -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137 -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138 -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139 -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140 -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141 -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142 -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143 -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144 -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145 -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146 -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147 -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148 -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149 -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150 -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151 -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152 -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153 -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154 -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155 -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156 -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157 -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158 -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159 -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160 -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161 -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162 -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163 -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164 -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165 -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166 -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167 -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168 -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169 -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170 -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171 -SEM_PERF_SEL_MC_RD_REQ = 172 -SEM_PERF_SEL_MC_RD_RET = 173 -SEM_PERF_SEL_MC_WR_REQ = 174 -SEM_PERF_SEL_MC_WR_RET = 175 -SEM_PERF_SEL_ATC_REQ = 176 -SEM_PERF_SEL_ATC_RET = 177 -SEM_PERF_SEL_ATC_XNACK = 178 -SEM_PERF_SEL_ATC_INVALIDATION = 179 -SEM_PERF_SEL_ATC_VM_INVALIDATION = 180 -SEM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LSDMA_PERF_SEL' -LSDMA_PERF_SEL__enumvalues = { - 0: 'LSDMA_PERF_SEL_CYCLE', - 1: 'LSDMA_PERF_SEL_IDLE', - 2: 'LSDMA_PERF_SEL_REG_IDLE', - 3: 'LSDMA_PERF_SEL_RB_EMPTY', - 4: 'LSDMA_PERF_SEL_RB_FULL', - 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', - 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', - 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', - 13: 'LSDMA_PERF_SEL_EX_IDLE', - 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', - 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', - 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', - 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', - 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'LSDMA_PERF_SEL_SEM_IDLE', - 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'LSDMA_PERF_SEL_INT_IDLE', - 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', - 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'LSDMA_PERF_SEL_NUM_PACKET', - 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', - 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', - 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', - 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', - 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'LSDMA_PERF_SEL_CE_RD_STALL', - 52: 'LSDMA_PERF_SEL_CE_WR_STALL', - 53: 'LSDMA_PERF_SEL_GFX_SELECT', - 54: 'LSDMA_PERF_SEL_RLC0_SELECT', - 55: 'LSDMA_PERF_SEL_RLC1_SELECT', - 56: 'LSDMA_PERF_SEL_PAGE_SELECT', - 57: 'LSDMA_PERF_SEL_CTX_CHANGE', - 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'LSDMA_PERF_SEL_DOORBELL', - 61: 'LSDMA_PERF_SEL_RD_BA_RTR', - 62: 'LSDMA_PERF_SEL_WR_BA_RTR', - 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'LSDMA_PERF_SEL_CE_L1_STALL', - 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', - 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', - 72: 'LSDMA_PERF_SEL_ATCL2_FREE', - 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', - 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', - 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', - 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', - 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', - 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', - 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', - 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', - 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', - 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', - 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', - 110: 'LSDMA_PERF_SEL_CMD_OP_START', - 111: 'LSDMA_PERF_SEL_CMD_OP_END', - 112: 'LSDMA_PERF_SEL_CE_BUSY', - 113: 'LSDMA_PERF_SEL_CE_BUSY_START', - 114: 'LSDMA_PERF_SEL_CE_BUSY_END', - 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 122: 'LSDMA_PERF_SEL_DRAM_ECC', - 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', -} -LSDMA_PERF_SEL_CYCLE = 0 -LSDMA_PERF_SEL_IDLE = 1 -LSDMA_PERF_SEL_REG_IDLE = 2 -LSDMA_PERF_SEL_RB_EMPTY = 3 -LSDMA_PERF_SEL_RB_FULL = 4 -LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 -LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 -LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -LSDMA_PERF_SEL_RB_RPTR_WB = 8 -LSDMA_PERF_SEL_RB_CMD_IDLE = 9 -LSDMA_PERF_SEL_RB_CMD_FULL = 10 -LSDMA_PERF_SEL_IB_CMD_IDLE = 11 -LSDMA_PERF_SEL_IB_CMD_FULL = 12 -LSDMA_PERF_SEL_EX_IDLE = 13 -LSDMA_PERF_SEL_SRBM_REG_SEND = 14 -LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -LSDMA_PERF_SEL_MC_WR_IDLE = 16 -LSDMA_PERF_SEL_MC_WR_COUNT = 17 -LSDMA_PERF_SEL_MC_RD_IDLE = 18 -LSDMA_PERF_SEL_MC_RD_COUNT = 19 -LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 -LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -LSDMA_PERF_SEL_SEM_IDLE = 24 -LSDMA_PERF_SEL_SEM_REQ_STALL = 25 -LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 -LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 -LSDMA_PERF_SEL_SEM_RESP_PASS = 29 -LSDMA_PERF_SEL_INT_IDLE = 30 -LSDMA_PERF_SEL_INT_REQ_STALL = 31 -LSDMA_PERF_SEL_INT_REQ_COUNT = 32 -LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -LSDMA_PERF_SEL_INT_RESP_RETRY = 34 -LSDMA_PERF_SEL_NUM_PACKET = 35 -LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 -LSDMA_PERF_SEL_CE_WR_IDLE = 38 -LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 -LSDMA_PERF_SEL_CE_OUT_IDLE = 41 -LSDMA_PERF_SEL_CE_IN_IDLE = 42 -LSDMA_PERF_SEL_CE_DST_IDLE = 43 -LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 -LSDMA_PERF_SEL_CE_INFO_FULL = 49 -LSDMA_PERF_SEL_CE_INFO1_FULL = 50 -LSDMA_PERF_SEL_CE_RD_STALL = 51 -LSDMA_PERF_SEL_CE_WR_STALL = 52 -LSDMA_PERF_SEL_GFX_SELECT = 53 -LSDMA_PERF_SEL_RLC0_SELECT = 54 -LSDMA_PERF_SEL_RLC1_SELECT = 55 -LSDMA_PERF_SEL_PAGE_SELECT = 56 -LSDMA_PERF_SEL_CTX_CHANGE = 57 -LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -LSDMA_PERF_SEL_DOORBELL = 60 -LSDMA_PERF_SEL_RD_BA_RTR = 61 -LSDMA_PERF_SEL_WR_BA_RTR = 62 -LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 -LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 -LSDMA_PERF_SEL_CE_L1_STALL = 65 -LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 -LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 -LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 -LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 -LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 -LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 -LSDMA_PERF_SEL_ATCL2_FREE = 72 -LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 -LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 -LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 -LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 -LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 -LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 -LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 -LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 -LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 -LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 -LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 -LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 -LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 -LSDMA_PERF_SEL_L1_WR_INV_EN = 86 -LSDMA_PERF_SEL_L1_RD_INV_EN = 87 -LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 -LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 -LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 -LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 -LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 -LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 -LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 -LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 -LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 -LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 -LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 -LSDMA_PERF_SEL_CMD_OP_MATCH = 109 -LSDMA_PERF_SEL_CMD_OP_START = 110 -LSDMA_PERF_SEL_CMD_OP_END = 111 -LSDMA_PERF_SEL_CE_BUSY = 112 -LSDMA_PERF_SEL_CE_BUSY_START = 113 -LSDMA_PERF_SEL_CE_BUSY_END = 114 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 -LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 -LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 -LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 -LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 -LSDMA_PERF_SEL_DRAM_ECC = 122 -LSDMA_PERF_SEL_NACK_GEN_ERR = 123 -LSDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' -EFC_SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'EFC_ARGB1555', - 2: 'EFC_RGBA5551', - 3: 'EFC_RGB565', - 4: 'EFC_BGR565', - 5: 'EFC_ARGB4444', - 6: 'EFC_RGBA4444', - 8: 'EFC_ARGB8888', - 9: 'EFC_RGBA8888', - 10: 'EFC_ARGB2101010', - 11: 'EFC_RGBA1010102', - 12: 'EFC_AYCrCb8888', - 13: 'EFC_YCrCbA8888', - 14: 'EFC_ACrYCb8888', - 15: 'EFC_CrYCbA8888', - 16: 'EFC_ARGB16161616_10MSB', - 17: 'EFC_RGBA16161616_10MSB', - 18: 'EFC_ARGB16161616_10LSB', - 19: 'EFC_RGBA16161616_10LSB', - 20: 'EFC_ARGB16161616_12MSB', - 21: 'EFC_RGBA16161616_12MSB', - 22: 'EFC_ARGB16161616_12LSB', - 23: 'EFC_RGBA16161616_12LSB', - 24: 'EFC_ARGB16161616_FLOAT', - 25: 'EFC_RGBA16161616_FLOAT', - 26: 'EFC_ARGB16161616_UNORM', - 27: 'EFC_RGBA16161616_UNORM', - 28: 'EFC_ARGB16161616_SNORM', - 29: 'EFC_RGBA16161616_SNORM', - 32: 'EFC_AYCrCb16161616_10MSB', - 33: 'EFC_AYCrCb16161616_10LSB', - 34: 'EFC_YCrCbA16161616_10MSB', - 35: 'EFC_YCrCbA16161616_10LSB', - 36: 'EFC_ACrYCb16161616_10MSB', - 37: 'EFC_ACrYCb16161616_10LSB', - 38: 'EFC_CrYCbA16161616_10MSB', - 39: 'EFC_CrYCbA16161616_10LSB', - 40: 'EFC_AYCrCb16161616_12MSB', - 41: 'EFC_AYCrCb16161616_12LSB', - 42: 'EFC_YCrCbA16161616_12MSB', - 43: 'EFC_YCrCbA16161616_12LSB', - 44: 'EFC_ACrYCb16161616_12MSB', - 45: 'EFC_ACrYCb16161616_12LSB', - 46: 'EFC_CrYCbA16161616_12MSB', - 47: 'EFC_CrYCbA16161616_12LSB', - 64: 'EFC_Y8_CrCb88_420_PLANAR', - 65: 'EFC_Y8_CbCr88_420_PLANAR', - 66: 'EFC_Y10_CrCb1010_420_PLANAR', - 67: 'EFC_Y10_CbCr1010_420_PLANAR', - 68: 'EFC_Y12_CrCb1212_420_PLANAR', - 69: 'EFC_Y12_CbCr1212_420_PLANAR', - 72: 'EFC_YCrYCb8888_422_PACKED', - 73: 'EFC_YCbYCr8888_422_PACKED', - 74: 'EFC_CrYCbY8888_422_PACKED', - 75: 'EFC_CbYCrY8888_422_PACKED', - 76: 'EFC_YCrYCb10101010_422_PACKED', - 77: 'EFC_YCbYCr10101010_422_PACKED', - 78: 'EFC_CrYCbY10101010_422_PACKED', - 79: 'EFC_CbYCrY10101010_422_PACKED', - 80: 'EFC_YCrYCb12121212_422_PACKED', - 81: 'EFC_YCbYCr12121212_422_PACKED', - 82: 'EFC_CrYCbY12121212_422_PACKED', - 83: 'EFC_CbYCrY12121212_422_PACKED', - 112: 'EFC_RGB111110_FIX', - 113: 'EFC_BGR101111_FIX', - 114: 'EFC_ACrYCb2101010', - 115: 'EFC_CrYCbA1010102', - 118: 'EFC_RGB111110_FLOAT', - 119: 'EFC_BGR101111_FLOAT', - 120: 'EFC_MONO_8', - 121: 'EFC_MONO_10MSB', - 122: 'EFC_MONO_10LSB', - 123: 'EFC_MONO_12MSB', - 124: 'EFC_MONO_12LSB', - 125: 'EFC_MONO_16', -} -EFC_ARGB1555 = 1 -EFC_RGBA5551 = 2 -EFC_RGB565 = 3 -EFC_BGR565 = 4 -EFC_ARGB4444 = 5 -EFC_RGBA4444 = 6 -EFC_ARGB8888 = 8 -EFC_RGBA8888 = 9 -EFC_ARGB2101010 = 10 -EFC_RGBA1010102 = 11 -EFC_AYCrCb8888 = 12 -EFC_YCrCbA8888 = 13 -EFC_ACrYCb8888 = 14 -EFC_CrYCbA8888 = 15 -EFC_ARGB16161616_10MSB = 16 -EFC_RGBA16161616_10MSB = 17 -EFC_ARGB16161616_10LSB = 18 -EFC_RGBA16161616_10LSB = 19 -EFC_ARGB16161616_12MSB = 20 -EFC_RGBA16161616_12MSB = 21 -EFC_ARGB16161616_12LSB = 22 -EFC_RGBA16161616_12LSB = 23 -EFC_ARGB16161616_FLOAT = 24 -EFC_RGBA16161616_FLOAT = 25 -EFC_ARGB16161616_UNORM = 26 -EFC_RGBA16161616_UNORM = 27 -EFC_ARGB16161616_SNORM = 28 -EFC_RGBA16161616_SNORM = 29 -EFC_AYCrCb16161616_10MSB = 32 -EFC_AYCrCb16161616_10LSB = 33 -EFC_YCrCbA16161616_10MSB = 34 -EFC_YCrCbA16161616_10LSB = 35 -EFC_ACrYCb16161616_10MSB = 36 -EFC_ACrYCb16161616_10LSB = 37 -EFC_CrYCbA16161616_10MSB = 38 -EFC_CrYCbA16161616_10LSB = 39 -EFC_AYCrCb16161616_12MSB = 40 -EFC_AYCrCb16161616_12LSB = 41 -EFC_YCrCbA16161616_12MSB = 42 -EFC_YCrCbA16161616_12LSB = 43 -EFC_ACrYCb16161616_12MSB = 44 -EFC_ACrYCb16161616_12LSB = 45 -EFC_CrYCbA16161616_12MSB = 46 -EFC_CrYCbA16161616_12LSB = 47 -EFC_Y8_CrCb88_420_PLANAR = 64 -EFC_Y8_CbCr88_420_PLANAR = 65 -EFC_Y10_CrCb1010_420_PLANAR = 66 -EFC_Y10_CbCr1010_420_PLANAR = 67 -EFC_Y12_CrCb1212_420_PLANAR = 68 -EFC_Y12_CbCr1212_420_PLANAR = 69 -EFC_YCrYCb8888_422_PACKED = 72 -EFC_YCbYCr8888_422_PACKED = 73 -EFC_CrYCbY8888_422_PACKED = 74 -EFC_CbYCrY8888_422_PACKED = 75 -EFC_YCrYCb10101010_422_PACKED = 76 -EFC_YCbYCr10101010_422_PACKED = 77 -EFC_CrYCbY10101010_422_PACKED = 78 -EFC_CbYCrY10101010_422_PACKED = 79 -EFC_YCrYCb12121212_422_PACKED = 80 -EFC_YCbYCr12121212_422_PACKED = 81 -EFC_CrYCbY12121212_422_PACKED = 82 -EFC_CbYCrY12121212_422_PACKED = 83 -EFC_RGB111110_FIX = 112 -EFC_BGR101111_FIX = 113 -EFC_ACrYCb2101010 = 114 -EFC_CrYCbA1010102 = 115 -EFC_RGB111110_FLOAT = 118 -EFC_BGR101111_FLOAT = 119 -EFC_MONO_8 = 120 -EFC_MONO_10MSB = 121 -EFC_MONO_10LSB = 122 -EFC_MONO_12MSB = 123 -EFC_MONO_12LSB = 124 -EFC_MONO_16 = 125 -EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum -__all__ = \ - ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', - 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', - 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', - 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', - 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', - 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', - 'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', 'ADDR_RESERVED', - 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', - 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', - 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', - 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', - 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', - 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', - 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', - 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', - 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', - 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', - 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', - 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', - 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', - 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', - 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', - 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', - 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', - 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', - 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', - 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', - 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', - 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', - 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', - 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', - 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', - 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', - 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', - 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', - 'ALPHA_DATA_ONTO_Y_G_PORT', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', - 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', - 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', - 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', - 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', - 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', - 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', - 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', - 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', - 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', - 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', - 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', - 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', - 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', - 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', - 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', - 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', - 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', - 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', - 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', - 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', - 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', - 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', - 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', - 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', - 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', - 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', - 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', - 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', - 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', - 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', - 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', - 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', - 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', - 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', - 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', - 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', - 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', - 'AZ_RIRB_WRITE_POINTER_DO_RESET', - 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', - 'AZ_STATE_CHANGE_STATUS', - 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', - 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', - 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', - 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', - 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', - 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', - 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', - 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', - 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', - 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', - 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', - 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', - 'BLEND_ONE_MINUS_CONSTANT_ALPHA', - 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', - 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', - 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', - 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', - 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS', - 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT', - 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', - 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', - 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', - 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', - 'CACHE_LRU_WR', 'CACHE_NOA', 'CACHE_NOA_WR', 'CACHE_STREAM', - 'CACHE_STREAM_RD', 'CBMode', 'CBPerfClearFilterSel', - 'CBPerfOpFilterSel', 'CBPerfSel', 'CBRamList', - 'CB_B_DATA_ONTO_ALPHA_PORT', 'CB_B_DATA_ONTO_CB_B_PORT', - 'CB_B_DATA_ONTO_CR_R_PORT', 'CB_B_DATA_ONTO_Y_G_PORT', - 'CB_DCC_DECOMPRESS', 'CB_DCG_BACKEND_RDLAT_FIFO', - 'CB_DCG_CCC_CAS_COLOR_PTR', 'CB_DCG_CCC_CAS_FRAG_PTR', - 'CB_DCG_CCC_CAS_KEYID', 'CB_DCG_CCC_CAS_SURF_PARAM', - 'CB_DCG_CCC_CAS_TAG_ARRAY', 'CB_DCG_COLOR_STORE', - 'CB_DCG_COLOR_STORE_DIRTY_BYTE', 'CB_DCG_DCC_CACHE', - 'CB_DCG_DCC_DIRTY_BITS', 'CB_DCG_FMASK_CACHE_STORE', - 'CB_DCG_FRONTEND_RDLAT_FIFO', 'CB_DCG_OUTPUT_FIFO', - 'CB_DCG_QBLOCK_ALLOC', 'CB_DCG_QUAD_PTR_FIFO', - 'CB_DCG_READ_SKID_FIFO', 'CB_DCG_SRC_FIFO', 'CB_DISABLE', - 'CB_ELIMINATE_FAST_CLEAR', 'CB_NORMAL', - 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', - 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', - 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 'CB_PERF_SEL_BLEND_CLOCK_EN', - 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', - 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CC_CACHE_FLUSH', - 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', - 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', - 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT', - 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', - 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_DCC_CACHE_FLUSH', - 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', - 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', - 'CB_PERF_SEL_DCC_CACHE_STALL', - 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', - 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', - 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', - 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD', - 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', - 'CB_PERF_SEL_FILTER_DRAWN_TILE', - 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', - 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119', - 'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121', - 'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123', - 'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125', - 'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127', - 'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129', - 'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131', - 'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133', - 'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135', - 'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137', - 'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139', - 'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141', - 'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143', - 'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145', - 'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147', - 'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149', - 'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166', - 'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168', - 'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170', - 'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172', - 'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174', - 'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176', - 'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178', - 'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180', - 'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182', - 'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184', - 'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186', - 'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188', - 'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190', - 'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192', - 'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194', - 'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196', - 'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198', - 'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205', - 'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207', - 'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209', - 'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210', - 'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212', - 'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214', - 'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216', - 'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218', - 'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22', - 'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221', - 'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223', - 'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225', - 'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227', - 'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229', - 'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230', - 'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232', - 'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234', - 'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236', - 'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238', - 'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24', - 'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241', - 'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243', - 'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245', - 'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247', - 'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249', - 'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259', - 'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260', - 'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262', - 'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264', - 'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266', - 'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268', - 'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27', - 'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271', - 'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273', - 'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275', - 'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277', - 'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279', - 'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280', - 'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282', - 'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284', - 'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286', - 'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288', - 'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29', - 'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291', - 'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293', - 'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295', - 'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297', - 'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299', - 'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304', - 'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306', - 'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308', - 'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310', - 'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312', - 'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314', - 'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316', - 'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318', - 'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320', - 'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322', - 'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324', - 'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326', - 'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328', - 'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330', - 'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332', - 'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334', - 'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336', - 'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338', - 'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340', - 'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342', - 'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344', - 'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346', - 'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348', - 'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350', - 'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352', - 'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354', - 'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356', - 'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358', - 'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360', - 'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362', - 'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364', - 'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366', - 'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368', - 'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370', - 'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372', - 'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374', - 'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376', - 'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378', - 'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38', - 'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381', - 'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383', - 'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385', - 'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387', - 'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389', - 'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390', - 'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392', - 'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394', - 'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396', - 'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398', - 'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40', - 'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401', - 'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403', - 'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405', - 'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407', - 'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409', - 'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410', - 'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412', - 'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414', - 'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416', - 'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418', - 'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42', - 'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421', - 'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423', - 'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425', - 'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427', - 'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429', - 'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430', - 'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432', - 'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434', - 'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436', - 'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438', - 'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44', - 'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441', - 'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443', - 'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445', - 'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447', - 'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449', - 'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450', - 'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452', - 'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454', - 'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456', - 'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458', - 'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46', - 'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461', - 'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463', - 'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465', - 'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48', - 'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65', - 'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67', - 'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69', - 'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71', - 'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73', - 'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75', - 'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77', - 'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79', - 'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81', - 'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83', - 'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85', - 'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87', - 'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89', - 'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91', - 'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93', - 'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95', - 'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97', - 'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99', - 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', - 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', - 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', - 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', - 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', - 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0', - 'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2', - 'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4', - 'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', - 'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY', - 'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', - 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ', - 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0', - 'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10', - 'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12', - 'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14', - 'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16', - 'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18', - 'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2', - 'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21', - 'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23', - 'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4', - 'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6', - 'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8', - 'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK', - 'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ', - 'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B', - 'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE', - 'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B', - 'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1', - 'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL', - 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', - 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', - 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', - 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', - 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', - 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', - 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', - 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', - 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', - 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', - 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', - 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', - 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', - 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', - 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', - 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', - 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', - 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', - 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', - 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', - 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', - 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', - 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', - 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', - 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', - 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLE', - 'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO', - 'CLOCK_GATING_DISABLE_ENUM', 'CLOCK_GATING_DISABLE_ENUM_DISABLED', - 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', - 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', - 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', - 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', - 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', - 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', - 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', - 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', - 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', - 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', - 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', - 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', - 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', - 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', - 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', - 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', - 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', - 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', - 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', - 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', - 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', - 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', - 'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM', - 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', - 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', - 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL', - 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING', - 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY', - 'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE', - 'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN', - 'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12', - 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE', - 'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B', - 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', - 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', - 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', - 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE', - 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', - 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL', - 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', - 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', - 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', - 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', - 'CORB_READ_POINTER_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', - 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', - 'CPC_LATENCY_STATS_SEL_INVAL_LAST', - 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', - 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', - 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0', - 'CPC_PERF_SEL_MES_THREAD1', - 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', - 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', - 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 'CPF_LATENCY_STATS_SEL_READ_LAST', - 'CPF_LATENCY_STATS_SEL_READ_MAX', - 'CPF_LATENCY_STATS_SEL_READ_MIN', - 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', - 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', - 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', - 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', - 'CPF_PERF_SEL_ALWAYS_COUNT', - 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', - 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', - 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', - 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', - 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', - 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', - 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', - 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 'CPG_LATENCY_STATS_SEL_INVAL_LAST', - 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 'CPG_LATENCY_STATS_SEL_READ_LAST', - 'CPG_LATENCY_STATS_SEL_READ_MAX', - 'CPG_LATENCY_STATS_SEL_READ_MIN', - 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', - 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', - 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', - 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', - 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', - 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', - 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', - 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', - 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', - 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', - 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', - 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', - 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', - 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', - 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', - 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', - 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', - 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', - 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_DMA_BUSY', - 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', - 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', - 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', - 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', - 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', - 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', - 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', - 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', - 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', - 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', - 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', - 'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', - 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', - 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', - 'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', - 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', - 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', - 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', - 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', - 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', - 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', - 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', - 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', - 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', - 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', - 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', - 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', - 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', - 'CURSOR_COLOR_24BIT_1BIT_AND', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 'CURSOR_COLOR_64BIT_FP_PREMULT', - 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', - 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', - 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', - 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', - 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', - 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', - 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', - 'CURSOR_MODE', 'CURSOR_MONO_2BIT', - 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_EN', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', - 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', - 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', - 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', - 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', - 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', - 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', - 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', - 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', - 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', - 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', - 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', - 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', - 'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag', - 'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102', - 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', - 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', - 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', - 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', - 'DAC_MUX_SELECT_DACB', 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', - 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', - 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', - 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', - 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', - 'DB_INVOKE_CHANGE_EVENT', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 'DB_PERF_SEL_CB_DB_rdreq_sends', - 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 'DB_PERF_SEL_CB_DB_wrreq_sends', - 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', - 'DB_PERF_SEL_DB_CB_lquad_busy', - 'DB_PERF_SEL_DB_CB_lquad_double_format', - 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 'DB_PERF_SEL_DB_CB_lquad_quads', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', - 'DB_PERF_SEL_DB_CB_lquad_sends', - 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', - 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', - 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', - 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', - 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', - 'DB_PERF_SEL_DB_SC_quad_double_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', - 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', - 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', - 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 'DB_PERF_SEL_DB_SC_tile_stalls', - 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', - 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 'DB_PERF_SEL_Depth_Tile_Cache_event', - 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 'DB_PERF_SEL_Plane_Cache_flushes', - 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', - 'DB_PERF_SEL_Plane_Cache_misses', - 'DB_PERF_SEL_Plane_Cache_starves', - 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 'DB_PERF_SEL_PostZ_Samples_failing_S', - 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 'DB_PERF_SEL_PreZ_Samples_failing_S', - 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', - 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', - 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', - 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', - 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', - 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 'DB_PERF_SEL_SH_quads_outstanding_sum', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 'DB_PERF_SEL_SX_DB_quad_busy', - 'DB_PERF_SEL_SX_DB_quad_double_format', - 'DB_PERF_SEL_SX_DB_quad_export_quads', - 'DB_PERF_SEL_SX_DB_quad_exports', - 'DB_PERF_SEL_SX_DB_quad_fast_format', - 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', - 'DB_PERF_SEL_SX_DB_quad_sends', - 'DB_PERF_SEL_SX_DB_quad_slow_format', - 'DB_PERF_SEL_SX_DB_quad_stalls', - 'DB_PERF_SEL_Stencil_Cache_flushes', - 'DB_PERF_SEL_Stencil_Cache_frees', - 'DB_PERF_SEL_Stencil_Cache_hits', - 'DB_PERF_SEL_Stencil_Cache_misses', - 'DB_PERF_SEL_Stencil_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', - 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_surface_stall', - 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 'DB_PERF_SEL_Z_Cache_pmask_hits', - 'DB_PERF_SEL_Z_Cache_pmask_misses', - 'DB_PERF_SEL_Z_Cache_pmask_starves', - 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 'DB_PERF_SEL_clock_main_active', - 'DB_PERF_SEL_clock_mem_export_active', - 'DB_PERF_SEL_clock_reg_active', - 'DB_PERF_SEL_cs_events_pws_enable', - 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', - 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', - 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', - 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', - 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', - 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', - 'DB_PERF_SEL_dtt_sm_slot_stall', - 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', - 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', - 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', - 'DB_PERF_SEL_esr_ps_src_in_squads', - 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_stall', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', - 'DB_PERF_SEL_esr_ps_vic_stall', - 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', - 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', - 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', - 'DB_PERF_SEL_etr_out_esr_stall', - 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', - 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', - 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', - 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', - 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', - 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', - 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', - 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', - 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', - 'DB_PERF_SEL_flush_compressed_stencil', - 'DB_PERF_SEL_flush_expanded_stencil', - 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', - 'DB_PERF_SEL_flush_single_stencil', - 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', - 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', - 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', - 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', - 'DB_PERF_SEL_noz_waiting_for_postz_done', - 'DB_PERF_SEL_planes_flushed', - 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_postzl_full_launch', - 'DB_PERF_SEL_postzl_partial_launch', - 'DB_PERF_SEL_postzl_partial_waiting', - 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', - 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', - 'DB_PERF_SEL_postzl_src_in_sends', - 'DB_PERF_SEL_postzl_src_in_squads', - 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 'DB_PERF_SEL_postzl_src_in_stall', - 'DB_PERF_SEL_postzl_src_in_tile_rate', - 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_postzl_src_out_stall', - 'DB_PERF_SEL_postzl_tile_init_stall', - 'DB_PERF_SEL_postzl_tile_mem_stall', - 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_prezl_src_in_sends', - 'DB_PERF_SEL_prezl_src_in_squads', - 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 'DB_PERF_SEL_prezl_src_in_stall', - 'DB_PERF_SEL_prezl_src_in_tile_rate', - 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_prezl_src_out_stall', - 'DB_PERF_SEL_prezl_tile_init_stall', - 'DB_PERF_SEL_prezl_tile_mem_stall', - 'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy', - 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', - 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', - 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', - 'DB_PERF_SEL_quad_rd_mi_stall', - 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', - 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', - 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', - 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', - 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', - 'DB_PERF_SEL_quad_wr_coherency_stall', - 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', - 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', - 'DB_PERF_SEL_tcp_dispatcher_flushes', - 'DB_PERF_SEL_tcp_dispatcher_reads', - 'DB_PERF_SEL_tcp_prefetcher_flushes', - 'DB_PERF_SEL_tcp_prefetcher_reads', - 'DB_PERF_SEL_tcp_preloader_flushes', - 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', - 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', - 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 'DB_PERF_SEL_tiles_decomp_on_expclear', - 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', - 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', - 'DB_PERF_SEL_tl_expand_squads', - 'DB_PERF_SEL_tl_flush_expand_squads', - 'DB_PERF_SEL_tl_in_fast_z_stall', - 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', - 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', - 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', - 'DB_PERF_SEL_tl_preZ_squads', - 'DB_PERF_SEL_tl_stencil_locked_stall', - 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', - 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', - 'DB_PERF_SEL_tl_z_fetch_stall', - 'DB_PERF_SEL_ts_events_pws_enable', - 'DB_PERF_SEL_ts_tc_update_stall', - 'DB_PERF_SEL_tsc_insert_summarize_stall', - 'DB_PERF_SEL_unmapped_z_tile_culled', - 'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT', - 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', - 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', - 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 'DCCG_AUDIO_DTO_USE_512FBR_DTO', - 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', - 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', - 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', - 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', - 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', - 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', - 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', - 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', - 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', - 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', - 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', - 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', - 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', - 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', - 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_OFF', - 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', - 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', - 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', - 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', - 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', - 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', - 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', - 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', - 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', - 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', - 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', - 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', - 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', - 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', - 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', - 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', - 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', - 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', - 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', - 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', - 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', - 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', - 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', - 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', - 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', - 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', - 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', - 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', - 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', - 'DCIOCHIP_REF_27_SRC_SEL', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', - 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', - 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', - 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', - 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', - 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', - 'DCIO_DC_GENERICB_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', - 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', - 'DCIO_DC_GPU_TIMER_READ_SELECT', - 'DCIO_DC_GPU_TIMER_START_POSITION', - 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', - 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', - 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', - 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', - 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', - 'DCIO_DPCS_INTERRUPT_TYPE', - 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', - 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', - 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', - 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', - 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', - 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', - 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', - 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0', - 'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2', - 'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4', - 'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC', - 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', - 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', - 'DCIO_GENLK_CLK_GSL_MASK_STEREO', - 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', - 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', - 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', - 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', - 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', - 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', - 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', - 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL', - 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', - 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', - 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', - 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', - 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', - 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', - 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', - 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', - 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', - 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', - 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', - 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', - 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', - 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DC_DMCUB_INT_TYPE', - 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', - 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', - 'DEBUG_BUS_SELECT_ABM0', 'DEBUG_BUS_SELECT_ABM1', - 'DEBUG_BUS_SELECT_ABM2', 'DEBUG_BUS_SELECT_ABM3', - 'DEBUG_BUS_SELECT_ABM_RESERVED0', - 'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0', - 'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2', - 'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0', - 'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0', - 'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2', - 'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0', - 'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0', - 'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2', - 'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', - 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0', - 'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2', - 'DEBUG_BUS_SELECT_OPP_PIPE3', - 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', - 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR', - 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', - 'DETILE_BUFFER_PACKER_IS_DISABLE', - 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', - 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', - 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', - 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', - 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', - 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', - 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', - 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', - 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', - 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', - 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DIFFERENT_RGB', - 'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL', - 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', - 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', - 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', - 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', - 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', - 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', - 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', - 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', - 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', - 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', - 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', - 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED', - 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', - 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', - 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE', - 'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', - 'DIG_FIFO_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', - 'DIG_FIFO_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', - 'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED', - 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', - 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', - 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL', - 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', - 'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', - 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', - 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS', - 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS', - 'DIG_SL_PIXEL_GROUPING', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', - 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', - 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', - 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', - 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', - 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', - 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', - 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', - 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', - 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', - 'DIO_DBG_BLOCK_SEL', 'DIO_DBG_BLOCK_SEL_AUX0', - 'DIO_DBG_BLOCK_SEL_AUX1', 'DIO_DBG_BLOCK_SEL_AUX2', - 'DIO_DBG_BLOCK_SEL_AUX3', 'DIO_DBG_BLOCK_SEL_AUX4', - 'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB', - 'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD', - 'DIO_DBG_BLOCK_SEL_DIGE', 'DIO_DBG_BLOCK_SEL_DIGFE_A', - 'DIO_DBG_BLOCK_SEL_DIGFE_B', 'DIO_DBG_BLOCK_SEL_DIGFE_C', - 'DIO_DBG_BLOCK_SEL_DIGFE_D', 'DIO_DBG_BLOCK_SEL_DIGFE_E', - 'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA', - 'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC', - 'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPE', - 'DIO_DBG_BLOCK_SEL_DPFE_A', 'DIO_DBG_BLOCK_SEL_DPFE_B', - 'DIO_DBG_BLOCK_SEL_DPFE_C', 'DIO_DBG_BLOCK_SEL_DPFE_D', - 'DIO_DBG_BLOCK_SEL_DPFE_E', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', - 'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR', - 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', - 'DIO_FIFO_ERROR_11', - 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', - 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', - 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', - 'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', - 'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', - 'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT', - 'DISPCLK_CHG_FWD_CORR_DISABLE', - 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', - 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', - 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', - 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', - 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', - 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', - 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', - 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', - 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', - 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', - 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', - 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', - 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', - 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DI_SRC_SEL_RESERVED', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', - 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', - 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', - 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', - 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', - 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', - 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', - 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', - 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', - 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', - 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', - 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', - 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', - 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', - 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', - 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', - 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', - 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', - 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', - 'DMU_DC_GPU_TIMER_START_POSITION', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', - 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', - 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', - 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', - 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', - 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', - 'DOUT_I2C_ACK_TO_CLEAN', - 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_ABORT_XFER', - 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', - 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', - 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', - 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', - 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', - 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', - 'DOUT_I2C_CONTROL_SEND_RESET', - 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', - 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', - 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', - 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', - 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', - 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', - 'DOUT_I2C_DDC_SPEED_THRESHOLD', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', - 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', - 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', - 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP', - 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', - 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', - 'DPHY_8B10B_RESETET', - 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', - 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', - 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', - 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', - 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', - 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', - 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', - 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', - 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', - 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', - 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', - 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', - 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', - 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', - 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', - 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', - 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', - 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', - 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', - 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', - 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', - 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', - 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', - 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', - 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', - 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', - 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', - 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', - 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', - 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', - 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', - 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', - 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', - 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', - 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', - 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', - 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', - 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', - 'DPTE_GROUP_SIZE_64B', 'DP_128B132B', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', - 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', - 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', - 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', - 'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE', - 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 'DP_AUX_CONTROL_TEST_MODE_ENABLE', - 'DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', - 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', - 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', - 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', - 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', - 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', - 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', - 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', - 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', - 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', - 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 'DP_AUX_SW_CONTROL_LS_READ_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', - 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', - 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', - 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', - 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', - 'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE', - 'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1', - 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', - 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', - 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', - 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', - 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', - 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', - 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', - 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', - 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_LLCP', - 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 'DP_DPHY_SYM32_CRC_START_TP_START', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', - 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', - 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0', - 'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1', - 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', - 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', - 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', - 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE', - 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', - 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422', - 'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420', - 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', - 'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL', - 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', - 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', - 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', - 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', - 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', - 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', - 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', - 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', - 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', - 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', - 'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED', - 'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1', - 'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED', - 'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED', - 'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3', - 'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED', - 'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED', - 'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5', - 'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED', - 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', - 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', - 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', - 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', - 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', - 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', - 'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING', - 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', - 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', - 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM', - 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', - 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', - 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', - 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', - 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', - 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', - 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', - 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', - 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', - 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', - 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', - 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', - 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', - 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', - 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', - 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', - 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', - 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', - 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', - 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', - 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', - 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', - 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', - 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', - 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', - 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', - 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', - 'DP_SYM32_ENC_PENDING', - 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', - 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', - 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', - 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', - 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE', - 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', - 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', - 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', - 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', - 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', - 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', - 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', - 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', - 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', - 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', - 'DSCCIF_BITS_PER_COMPONENT_ENUM', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', - 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 'DSCC_BITS_PER_COMPONENT_ENUM', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCC_DSC_VERSION_MAJOR_ENUM', - 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', - 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', - 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', - 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', - 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', - 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', - 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', - 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', - 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', - 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', - 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', - 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', - 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', - 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', - 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', - 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', - 'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS', - 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', - 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', - 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', - 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', - 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', - 'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM', - 'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN', - 'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM', - 'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0', - 'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', - 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', - 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', - 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', - 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', - 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', - 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', - 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', - 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', - 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', - 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', - 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', - 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', - 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', - 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', - 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', - 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', - 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', - 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', - 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', - 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', - 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', - 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', - 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', - 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', - 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', - 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', - 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', - 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', - 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', - 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', - 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', - 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', - 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', - 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', - 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', - 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', - 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', - 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', - 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', - 'EFC_BGR101111_FLOAT', 'EFC_BGR565', - 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', - 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', - 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', - 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', - 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', - 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', - 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', - 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', - 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', - 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', - 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', - 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', - 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', - 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', - 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', - 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', - 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', - 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', - 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', - 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', - 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', - 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', - 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', - 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', - 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', - 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', - 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', - 'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT', - 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', - 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', - 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', - 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', - 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', - 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', - 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', - 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', - 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', - 'ENUM_DPG_FIELD_POLARITY', - 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', - 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', - 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', - 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', - 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE', - 'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES', - 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_STATUS', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', - 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', - 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', - 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', - 'ENUM_DP_SYM32_ENC_CRC_VALID', - 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', - 'ENUM_DP_SYM32_ENC_ENABLE', - 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', - 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', - 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', - 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', - 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', - 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', - 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', - 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE', - 'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU', - 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY', - 'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE', - 'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO', - 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC', - 'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', - 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL', - 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FC_EYE_SELECTION_ENUM', - 'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE', - 'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM', - 'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF', - 'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD', - 'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT', - 'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13', - 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE', - 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3', - 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7', - 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', - 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', - 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', - 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', - 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', - 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', - 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 'FMT_CLAMP_CNTL_COLOR_FORMAT', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', - 'FMT_CONTROL_PIXEL_ENCODING', - 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', - 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 'FMT_CONTROL_SUBSAMPLING_MODE', - 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', - 'FMT_CONTROL_SUBSAMPLING_ORDER', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', - 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', - 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', - 'FMT_FRAME_RANDOM_ENABLE_CONTROL', - 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', - 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', - 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', - 'FMT_RGB_RANDOM_ENABLE_CONTROL', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', - 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', - 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', - 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', - 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', - 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', - 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', - 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', - 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', - 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', - 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', - 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', - 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', - 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', - 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', - 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', - 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', - 'ForceControl', 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', - 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', - 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', - 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', - 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', - 'GB_TILING_CONFIG_TABLE_SIZE', 'GCRPerfSel', - 'GCR_PERF_SEL_ALL_REQ', - 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', - 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 'GCR_PERF_SEL_CPC_TCP_REQ', - 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', - 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 'GCR_PERF_SEL_CPF_TCP_REQ', - 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', - 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 'GCR_PERF_SEL_CPG_TCP_REQ', - 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', - 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', - 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 'GCR_PERF_SEL_PIO_TCP_REQ', - 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', - 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 'GCR_PERF_SEL_PM_TCP_REQ', - 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', - 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 'GCR_PERF_SEL_RLC_TCP_REQ', - 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', - 'GCR_PERF_SEL_VIRT_REQ', 'GDS_PERFCOUNT_SELECT', - 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', - 'GDS_PERF_SEL_SE0_2COMP_REQ', 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE0_GDS_RD_OP', 'GDS_PERF_SEL_SE0_GDS_REL_OP', - 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP', - 'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT', - 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET', - 'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP', - 'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT', - 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET', - 'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP', - 'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT', - 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET', - 'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP', - 'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT', - 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET', - 'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP', - 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP', - 'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT', - 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET', - 'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP', - 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP', - 'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT', - 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET', - 'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP', - 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP', - 'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT', - 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET', - 'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP', - 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP', - 'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT', - 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET', - 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', - 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', - 'GE2_SE_PERFCOUNT_SELECT', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', - 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', - 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', - 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', - 'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO', - 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', - 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', - 'GL0V_CACHE_POLICY_MISS_LRU', 'GL1A_PERF_SEL', - 'GL1A_PERF_SEL_ARB_REQUESTS', 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', - 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', - 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', - 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', - 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', - 'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B', - 'GL1C_PERF_SEL_GL2_REQ_READ_32B', - 'GL1C_PERF_SEL_GL2_REQ_READ_64B', - 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', - 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', - 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', - 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', - 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', - 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', - 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', - 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', - 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', - 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', - 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', - 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', - 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', - 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', - 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', - 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', - 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS', - 'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0', - 'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B', - 'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B', - 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', - 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', - 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', - 'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE', - 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', - 'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1', - 'GL1C_PERF_SEL_STALL_LFIFO_FULL', - 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', - 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', - 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', - 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 'GL1C_PERF_SEL_UTCL0_REQUEST', - 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', - 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', - 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY', - 'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', - 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', - 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1', - 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', - 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES', - 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', - 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', - 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', - 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', - 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', - 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', - 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', - 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', - 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', - 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', - 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', - 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', - 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', - 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', - 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', - 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', - 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', - 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', - 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', - 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', - 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', - 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', - 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', - 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', - 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', - 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', - 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', - 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', - 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', - 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', - 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', - 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', - 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', - 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', - 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', - 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', - 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 'GL2C_PERF_SEL_EA_RDRET_NACK', - 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', - 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', - 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', - 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', - 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', - 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', - 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', - 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', - 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', - 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', - 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', - 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', - 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', - 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', - 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', - 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', - 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_MDC_TAG_HIT', - 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 'GL2C_PERF_SEL_MDC_TAG_STALL', - 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', - 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', - 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', - 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', - 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', - 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', - 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', - 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', - 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', - 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', - 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', - 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', - 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', - 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', - 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', - 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', - 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', - 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', - 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', - 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', - 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES', - 'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', - 'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2', - 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS', - 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', - 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', - 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', - 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', - 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', - 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', - 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', - 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', - 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', - 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', - 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', - 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', - 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', - 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', - 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', - 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', - 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', - 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', - 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', - 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', - 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', - 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', - 'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32', - 'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32', - 'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8', - 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', - 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', - 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', - 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', - 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', - 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', - 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', - 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', - 'GLOBAL_STATUS_FLUSH_STATUS', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', - 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', - 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', - 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', - 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', - 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', - 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', - 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', - 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', - 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', - 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', - 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', - 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', - 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', - 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY', - 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', - 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', - 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY', - 'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY', - 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', - 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', - 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', - 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', - 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', - 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', - 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', - 'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', - 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', - 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', - 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', - 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY', - 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY', - 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', - 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', - 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY', - 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', - 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', - 'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', - 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', - 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', - 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', - 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY', - 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY', - 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', - 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', - 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY', - 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY', - 'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN', - 'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY', - 'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY', - 'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY', - 'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY', - 'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY', - 'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED', - 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL', - 'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY', - 'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT', - 'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN', - 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY', - 'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY', - 'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY', - 'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY', - 'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY', - 'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY', - 'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN', - 'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY', - 'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY', - 'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY', - 'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY', - 'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY', - 'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED', - 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL', - 'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY', - 'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT', - 'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN', - 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY', - 'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY', - 'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY', - 'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY', - 'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY', - 'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', - 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', - 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', - 'GS_STAGE_ON', 'HDMICHARCLK_SRC_SEL', - 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', 'HDMICHARCLK_SRC_SEL_UNIPHYA', - 'HDMICHARCLK_SRC_SEL_UNIPHYB', 'HDMICHARCLK_SRC_SEL_UNIPHYC', - 'HDMICHARCLK_SRC_SEL_UNIPHYD', 'HDMICHARCLK_SRC_SEL_UNIPHYE', - 'HDMISTREAMCLK_DTO_FORCE_DIS', 'HDMISTREAMCLK_SRC_SEL', - 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', 'HDMI_ACP_SEND', - 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', - 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', - 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', - 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', - 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', - 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', - 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', - 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', - 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', - 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', - 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', - 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', - 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', - 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', - 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', - 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', - 'HDMI_AUDIO_INFO_SEND', - 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', - 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', - 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', - 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', - 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', - 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', - 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', - 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL', - 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', - 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', - 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', - 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', - 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', - 'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE', - 'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND', - 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', - 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', - 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', - 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', - 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', - 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', - 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', - 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', - 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', - 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', - 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', - 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', - 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', - 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', - 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE', - 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE', - 'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE', - 'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE', - 'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL', - 'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET', - 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', - 'HDMI_STREAM_ENC_ODM_COMBINE_MODE', - 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', - 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', - 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT', - 'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE', - 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET', - 'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE', - 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', - 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', - 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND', - 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT', - 'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT', - 'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE', - 'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND', - 'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE', - 'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE', - 'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE', - 'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT', - 'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND', - 'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', - 'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', - 'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT', - 'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE', - 'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING', - 'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE', - 'HDMI_TMDS_OR_DP_8B10B', 'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', - 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', 'HPD_INT_CONTROL_ACK', - 'HPD_INT_CONTROL_ACK_0', 'HPD_INT_CONTROL_ACK_1', - 'HPD_INT_CONTROL_GEN_INT_ON_CON', - 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', - 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', - 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', - 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', - 'HPO_TOP_CLOCK_GATING_EN', - 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', - 'HPO_TOP_REGISTER_GATED_DISPCLK', - 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', - 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', - 'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF', - 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', - 'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', - 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', - 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', - 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', - 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', - 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', - 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', - 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', - 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', - 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', - 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', - 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', - 'IH_PERF_SEL_BIF_LINE0_FALLING', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 'IH_PERF_SEL_BIF_LINE0_RISING', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', - 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', - 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', - 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', - 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', - 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', - 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', - 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', - 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', - 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', - 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', - 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', - 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', - 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', - 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', - 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', - 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', - 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', - 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', - 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', - 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', - 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', - 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', - 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', - 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', - 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', - 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', - 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', - 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', - 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', - 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', - 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', - 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', - 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', - 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', - 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', - 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', - 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', - 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', - 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', - 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', - 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', - 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', - 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', - 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', - 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', - 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', - 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', - 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', - 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', - 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', - 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', - 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', - 'IH_VF_RB_SELECT_RESERVED', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_FIFO_ERROR_TYPE', - 'INPUT_INNER_COVERAGE', 'INST_ID_ECC_INTERRUPT_MSG', - 'INST_ID_HOST_REG_TRAP_MSG', 'INST_ID_HW_TRAP', - 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', - 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', - 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', - 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', - 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', - 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', - 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', - 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', - 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', - 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', - 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', - 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0', - 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3', - 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', - 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK', - 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', - 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', - 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', - 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', - 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', - 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', - 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', - 'LSDMA_PERF_SEL_CTX_CHANGE', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', - 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', - 'LSDMA_PERF_SEL_EX_IDLE', - 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', - 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', - 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 'LSDMA_PERF_SEL_INT_REQ_STALL', - 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', - 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', - 'LSDMA_PERF_SEL_MC_WR_IDLE', - 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', - 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', - 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', - 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', - 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', - 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', - 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', - 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', - 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', - 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', - 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', - 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', - 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', - 'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT', - 'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', - 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', - 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', - 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', - 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 'MASTER_UPDATE_LOCK_SEL_RESERVED5', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', - 'MEM_ARB_MODE_WEIGHT', 'MEM_POWER_DIS_MODE_DISABLE', - 'MEM_POWER_DIS_MODE_ENABLE', 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', - 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', - 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', - 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', - 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', - 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', - 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', - 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', - 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', - 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', - 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', - 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', - 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', - 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', - 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', - 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', - 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', - 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', - 'MIN_META_CHUNK_SIZE_64B', 'MONO_10LSB', 'MONO_10MSB', - 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', - 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', - 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', - 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', - 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', - 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', - 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', - 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', - 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', - 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', - 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', - 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', - 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', - 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', - 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS', - 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', - 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', - 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', - 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', - 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', - 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', - 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', - 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', - 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', - 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', - 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', - 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', - 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', - 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', - 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', - 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', - 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', - 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', - 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', - 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', - 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', - 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', - 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', - 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', - 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', - 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', - 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', - 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', - 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', - 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', - 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', - 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', - 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', - 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', - 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', - 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', - 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', - 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', - 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', - 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', - 'MPC_DEBUG_BUS1_DATA_SELECT', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', - 'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', - 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', - 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', - 'MPC_DEBUG_BUS2_DATA_SELECT_RES', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', - 'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1', - 'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3', - 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT', - 'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', - 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', - 'MPC_OUT_RATE_CONTROL_DISABLE_SET', - 'MPC_OUT_RATE_CONTROL_SET_DISABLE', - 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', - 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', - 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', - 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', - 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', - 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', - 'MemArbMode', 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED', - 'NOT_SENT', 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', - 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', - 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS', - 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', - 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', - 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', - 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', - 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', - 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', - 'OPPBUF_DISPLAY_SEGMENTATION', - 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', - 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL', - 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL', - 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL', - 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL', - 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE', - 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', - 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', - 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 'OPP_PIPE_CRC_INTERLACE_MODE', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', - 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', - 'OPP_PIPE_CRC_PIXEL_SELECT', - 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', - 'OPP_PIPE_CRC_STEREO_MODE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', - 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', - 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', - 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', - 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', - 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', - 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', - 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', - 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', - 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', - 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', - 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', - 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', - 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', - 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', - 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', - 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', - 'OTG_DIG_UPDATE_VCOUNT_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', - 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', - 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', - 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', - 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', - 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', - 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', - 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', - 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', - 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', - 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', - 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', - 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', - 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', - 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', - 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', - 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', - 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', - 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', - 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', - 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', - 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', - 'OTG_TRIGA_FREQUENCY_SELECT_3', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', - 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', - 'OTG_TRIGB_FREQUENCY_SELECT_3', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', - 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', - 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', - 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', - 'OTG_V_SYNC_MODE_HSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', - 'OUTPUT_LINE', 'OUTPUT_POINT', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', - 'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', - 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE', - 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', - 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', - 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', - 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', - 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', - 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', - 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', - 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', - 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', - 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', - 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', - 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', - 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', - 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', - 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', - 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', - 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', - 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', - 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', - 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', - 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', - 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', - 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', - 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', - 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', - 'PERFCOUNTER_CNTOFF_START_DISABLE', - 'PERFCOUNTER_CNTOFF_START_ENABLE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', - 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', - 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', - 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', - 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', - 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', - 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', - 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', - 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', - 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', - 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', - 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', - 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', - 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', - 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', - 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', - 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', - 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', - 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', - 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', - 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', - 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', - 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', - 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', - 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', - 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', - 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', - 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', - 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', - 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', - 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', - 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', - 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', - 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', - 'PERFMON_COUNTER_MODE_ACCUM', - 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 'PERFMON_COUNTER_MODE_DIRTY', - 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', - 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', - 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', - 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', - 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', - 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', - 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', - 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', - 'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00', - 'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02', - 'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04', - 'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06', - 'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08', - 'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10', - 'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12', - 'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14', - 'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 'PERF_ENGG_CSB_NULL_SUBGROUP', - 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00', - 'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02', - 'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04', - 'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06', - 'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08', - 'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10', - 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 'PERF_ENGG_INDEX_REQ_STARVED', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', - 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', - 'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY', - 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', - 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', - 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', - 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', - 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', - 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', - 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', - 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', - 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', - 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', - 'PERF_PAPC_PASX_REC_STALLED', - 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', - 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', - 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', - 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', - 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', - 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', - 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', - 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', - 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', - 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE01_STALLED_SC', - 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE0_STALLED_SC', - 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE1_STALLED_SC', - 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE2_STALLED_SC', - 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', - 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN', - 'PERF_PA_PIPE1_SWITCHED_GEN', - 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', - 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', - 'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', - 'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN', - 'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE', - 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', - 'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK', - 'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5', - 'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16', - 'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24', - 'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1', - 'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT', - 'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL', - 'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1', - 'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3', - 'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1', - 'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3', - 'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1', - 'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3', - 'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1', - 'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3', - 'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1', - 'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3', - 'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1', - 'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3', - 'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1', - 'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3', - 'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1', - 'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3', - 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_BUSY', - 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE', - 'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE', - 'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE', - 'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE', - 'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE', - 'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE', - 'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE', - 'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE', - 'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC1_ARB_BUSY', - 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE', - 'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE', - 'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE', - 'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE', - 'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE', - 'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE', - 'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE', - 'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE', - 'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC2_ARB_BUSY', - 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE', - 'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE', - 'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE', - 'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE', - 'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE', - 'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE', - 'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE', - 'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE', - 'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC3_ARB_BUSY', - 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE', - 'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE', - 'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE', - 'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE', - 'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE', - 'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE', - 'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE', - 'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE', - 'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC4_ARB_BUSY', - 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE', - 'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE', - 'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE', - 'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE', - 'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE', - 'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE', - 'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE', - 'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE', - 'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC5_ARB_BUSY', - 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE', - 'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE', - 'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE', - 'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE', - 'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE', - 'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE', - 'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE', - 'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE', - 'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC6_ARB_BUSY', - 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE', - 'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE', - 'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE', - 'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE', - 'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE', - 'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE', - 'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE', - 'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE', - 'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC7_ARB_BUSY', - 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE', - 'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE', - 'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE', - 'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE', - 'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE', - 'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE', - 'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE', - 'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE', - 'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', - 'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1', - 'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE', - 'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE', - 'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE', - 'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT', - 'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 'PIPE_PIXEL_RATE_PLL_SOURCE', - 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', - 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', - 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', - 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', - 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', - 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', - 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', - 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', - 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', - 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', - 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', - 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', - 'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', - 'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', - 'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', - 'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', - 'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', - 'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE', - 'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO', - 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', - 'PS_PARTIAL_FLUSH', 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', - 'PTE_BUFFER_MODE_1', 'PTE_ROW_HEIGHT_LINEAR', - 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', - 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', - 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', - 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', - 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', - 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', - 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', - 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', - 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', - 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', - 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', - 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', - 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', - 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', - 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', - 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', - 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', - 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', - 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', - 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', - 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', - 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', - 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', - 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', - 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', - 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', - 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', - 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', - 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', - 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', - 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', - 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', - 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', - 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', - 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', - 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', - 'RASTER_CONFIG_SE_PAIR_MAP_3', - 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', - 'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE', - 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', - 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', - 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET', - 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', - 'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', - 'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', - 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY', - 'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY', - 'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY', - 'RDPCSPIPE_FIFO_NOT_FULL', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', - 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', - 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', - 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', - 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', - 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', - 'RDPCSPIPE_MEM_PWR_NO_FORCE', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', - 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', - 'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', - 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', - 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', - 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', - 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', - 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', - 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', - 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', - 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', - 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', - 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', - 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', - 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', - 'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE', - 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', - 'RDPCSPIPE_PHY_REF_ALT_CLK_EN', - 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0', - 'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2', - 'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4', - 'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6', - 'RDPCSPIPE_PHY_REF_RANGE_7', - 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', - 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', - 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', - 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', - 'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE', - 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', - 'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS', - 'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', - 'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE', - 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', - 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', - 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', - 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL', - 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_NONE', - 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', - 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', - 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF', - 'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE', - 'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE', - 'RDPCS_PIPE_CLK_GATE_ENABLE', - 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB', - 'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE', - 'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE', - 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', - 'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE', - 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', - 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ', - 'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF', - 'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ', - 'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ', - 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', - 'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11', - 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23', - 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34', - 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46', - 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58', - 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', - 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74', - 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85', - 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89', - 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES', - 'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS', - 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z', - 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', - 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', - 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', - 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', - 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', - 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', - 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', - 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', - 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', - 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', - 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', - 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', - 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', - 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', - 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', - 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', - 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', - 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE', - 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', - 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', - 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', - 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', - 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', - 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', - 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', - 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', - 'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09', - 'RingCounterControl', 'SAMPLE_PIPELINESTAT', - 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', - 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', - 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST', - 'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', - 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', - 'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND', - 'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON', - 'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER', - 'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER', - 'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL', - 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE', - 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SC_BACKEND_BUSY', - 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', - 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', - 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', - 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', - 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', - 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY', - 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE', - 'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB', - 'SC_DB0_TILE_INTERFACE_BUSY', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_DB0_TILE_MASK_FIFO_FULL', - 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', - 'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND', - 'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_DB1_TILE_MASK_FIFO_FULL', - 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', - 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', - 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', - 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', - 'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', - 'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY', - 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', - 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', - 'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY', - 'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY', - 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', - 'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', - 'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE', - 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', - 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', - 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', - 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', - 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', - 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', - 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', - 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', - 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', - 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', - 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', - 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', - 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', - 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', - 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', - 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', - 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', - 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', - 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', - 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', - 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', - 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', - 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', - 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', - 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', - 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', - 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', - 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', - 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', - 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', - 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', - 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', - 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', - 'SC_PBB_BUSY_AND_NO_SENDS', - 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', - 'SC_PBB_END_OF_BIN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', - 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', - 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', - 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', - 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', - 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', - 'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', - 'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK', - 'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', - 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', - 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', - 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', - 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', - 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', - 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE', - 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', - 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', - 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', - 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', - 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', - 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM', - 'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', - 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', - 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', - 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', - 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', - 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', - 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', - 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', - 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', - 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', - 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', - 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT', - 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', - 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', - 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', - 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', - 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', - 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', - 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', - 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', - 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', - 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', - 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', - 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', - 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', - 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', - 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', - 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', - 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', - 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', - 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', - 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT', - 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', - 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', - 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', - 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', - 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', - 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', - 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', - 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', - 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', - 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', - 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1', - 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', - 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', - 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', - 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0', - 'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0', - 'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0', - 'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0', - 'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT', - 'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2', - 'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID', - 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', - 'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO', - 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', - 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', - 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', - 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', - 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 'SC_SUPERTILE_COUNT', - 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', - 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', - 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', - 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', - 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', - 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', - 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', - 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', - 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', - 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', - 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', - 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', - 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', - 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', - 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', - 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', - 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', - 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', - 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', - 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', - 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', - 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX', - 'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE', - 'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE', - 'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', - 'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL', - 'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE', - 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE', - 'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', - 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', - 'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL', - 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', - 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', - 'SDMA_PERFMON_SEL_EX_IDLE', - 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN', - 'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT', - 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', - 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', - 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT', - 'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE', - 'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL', - 'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', - 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT', - 'SDMA_PERFMON_SEL_RLC1_SELECT', - 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', - 'SDMA_PERFMON_SEL_TLBI_SEND', - 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', - 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', - 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', - 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', - 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', - 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', - 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', - 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', - 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', - 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', - 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', - 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', - 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', - 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', - 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET', - 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', - 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH', - 'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ', - 'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL', - 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', - 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', - 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', - 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', - 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', - 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', - 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', - 'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET', - 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', - 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', - 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', - 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', - 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', - 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', - 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', - 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', - 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', - 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', - 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', - 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK0', - 'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', 'SEM_PERF_SEL', - 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT', - 'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ', - 'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_VM_INVALIDATION', - 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', - 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', - 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', - 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', - 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT', - 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT', - 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT', - 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', - 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', - 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', - 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', - 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', - 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', - 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', - 'SH_MEM_ALIGNMENT_MODE_DWORD', - 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', - 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', - 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', - 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', - 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', - 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', - 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', - 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', - 'SLVERR', 'SMU_INTR', 'SMU_INTR_STATUS_CLEAR', - 'SMU_INTR_STATUS_NOOP', 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', - 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', - 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', - 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', - 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', - 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', - 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', - 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', - 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID', - 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', - 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', - 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', - 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', - 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', - 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', - 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', - 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', - 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', - 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', - 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', - 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', - 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', - 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE', - 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC', - 'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL', - 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', - 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', - 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', - 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', - 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', - 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', - 'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0', - 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', - 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', - 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', - 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', - 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', - 'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0', - 'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE', - 'SPI_PERF_PS0_WAVEID_STARVED', - 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID', - 'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE', - 'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL', - 'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE', - 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE', - 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', - 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', - 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID', - 'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE', - 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL', - 'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE', - 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE', - 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', - 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', - 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID', - 'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE', - 'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL', - 'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE', - 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE', - 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', - 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', - 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID', - 'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT', - 'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0', - 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', - 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', - 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', - 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', - 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', - 'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC', - 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG', - 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', - 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', - 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3', - 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', - 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', - 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', - 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', - 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', - 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR', - 'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', - 'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR', - 'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', - 'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', - 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', - 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', - 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', - 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', - 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', - 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', - 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', - 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', - 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', - 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', - 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', - 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', - 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', - 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_OPERAND', - 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', - 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD', - 'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR', - 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD', - 'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', - 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', - 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', - 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ', - 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', - 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', - 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', - 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', - 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', - 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', - 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', - 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', - 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', - 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', - 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', - 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG', - 'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT', - 'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS', - 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', - 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS', - 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', - 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', - 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', - 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', - 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', - 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED', - 'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES', - 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', - 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', - 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', - 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', - 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', - 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', - 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', - 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', - 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', - 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', - 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', - 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', - 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', - 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', - 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', - 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', - 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', - 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', - 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', - 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', - 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', - 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', - 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', - 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', - 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', - 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', - 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', - 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', - 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', - 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', - 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', - 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', - 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', - 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', - 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', - 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', - 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', - 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', - 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', - 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', - 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', - 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', - 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', - 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', - 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1', - 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', - 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', - 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', - 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN', - 'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER', - 'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT', - 'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', - 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', - 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', - 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', - 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', - 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', - 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH', - 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', - 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', - 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', - 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL', - 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU', - 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX', - 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE', - 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 'SQ_PERF_SEL_INSTS_VALU_DP', - 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 'SQ_PERF_SEL_INSTS_VALU_VINTERP', - 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', - 'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', - 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', - 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS', - 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', - 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', - 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', - 'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU', - 'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', - 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', - 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', - 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 'SQ_PERF_SEL_SP_CONST_CYCLES', - 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', - 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', - 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', - 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', - 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', - 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', - 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', - 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', - 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', - 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', - 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', - 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', - 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', - 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', - 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 'SQ_PERF_SEL_VALU_RETURN_SDST', - 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', - 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', - 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS', - 'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR', - 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', - 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG', - 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', - 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA', - 'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU', - 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', - 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE', - 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', - 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', - 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', - 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', - 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', - 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', - 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', - 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', - 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', - 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', - 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', - 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', - 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', - 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', - 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', - 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', - 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', - 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', - 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', - 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1', - 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', - 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO', - 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', - 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', - 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', - 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', - 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', - 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 'SQ_TEX_DEPTH_COMPARE_GREATER', - 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', - 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', - 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', - 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', - 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', - 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', - 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', - 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', - 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', - 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', - 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', - 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', - 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', - 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', - 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE', - 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', - 'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', - 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', - 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', - 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', - 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', - 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ', - 'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK', - 'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', - 'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT', - 'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT', - 'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', - 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', - 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', - 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT', - 'SQ_TT_TOKEN_MASK_REG_EXCLUDE', - 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT', - 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT', - 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT', - 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', - 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', - 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', - 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', - 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', - 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', - 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', - 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', - 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', - 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', - 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', - 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', - 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', - 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', - 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', - 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', - 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', - 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', - 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', - 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', - 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', - 'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', - 'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP', - 'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV', - 'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'STALL', - 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', - 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', - 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', - 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', - 'STREAM_0_SYNCHRONIZATION', - 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_10_SYNCHRONIZATION', - 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION', - 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION', - 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION', - 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION', - 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION', - 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_1_SYNCHRONIZATION', - 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_2_SYNCHRONIZATION', - 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_3_SYNCHRONIZATION', - 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_4_SYNCHRONIZATION', - 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION', - 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION', - 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION', - 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION', - 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION', - 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE', - 'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT', - 'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT', - 'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420', - 'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB', - 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'STRM_PERFMON_STATE_RESERVED_3', - 'STRM_PERFMON_STATE_START_COUNTING', - 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', - 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', - 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', - 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', - 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', - 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', - 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', - 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', - 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', - 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', - 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', - 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', - 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', - 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLED', - 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', - 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', - 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', - 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', - 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', - 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', - 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', - 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', - 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', - 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', - 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', - 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', - 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', - 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', - 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', - 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', - 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', - 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', - 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', - 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', - 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', - 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', - 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', - 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', - 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', - 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', - 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', - 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', - 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', - 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', - 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', - 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', - 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', - 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', - 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', - 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', - 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', - 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', - 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', - 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', - 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', - 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', - 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', - 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', - 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', - 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', - 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', - 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', - 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', - 'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'ScMap', 'ScUncertaintyRegionMode', - 'ScUncertaintyRegionMult', 'ScXsel', 'ScYsel', 'SeMap', - 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', - 'SourceFormat', 'Spare_257', 'StencilOp', 'TA_PERFCOUNT_SEL', - 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', - 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 'TA_PERF_SEL_addresser_stalled_cycles', - 'TA_PERF_SEL_aligner_busy', - 'TA_PERF_SEL_aligner_clk_valid_cycles', - 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', - 'TA_PERF_SEL_aniso_12_cycle_quads', - 'TA_PERF_SEL_aniso_14_cycle_quads', - 'TA_PERF_SEL_aniso_16_cycle_quads', - 'TA_PERF_SEL_aniso_1_cycle_quads', - 'TA_PERF_SEL_aniso_2_cycle_quads', - 'TA_PERF_SEL_aniso_4_cycle_quads', - 'TA_PERF_SEL_aniso_6_cycle_quads', - 'TA_PERF_SEL_aniso_8_cycle_quads', - 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 'TA_PERF_SEL_aniso_stalled_cycles', - 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_write_data_input_cycles', - 'TA_PERF_SEL_atomic_write_data_output_cycles', - 'TA_PERF_SEL_bf_busy', - 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_atomic_wavefronts', - 'TA_PERF_SEL_buffer_flat_1_op_burst', - 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 'TA_PERF_SEL_buffer_has_index_instructions', - 'TA_PERF_SEL_buffer_has_offset_instructions', - 'TA_PERF_SEL_buffer_load_wavefronts', - 'TA_PERF_SEL_buffer_store_wavefronts', - 'TA_PERF_SEL_buffer_total_cycles', - 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles', - 'TA_PERF_SEL_color_1_cycle_quads', - 'TA_PERF_SEL_color_2_cycle_quads', - 'TA_PERF_SEL_color_3_cycle_quads', - 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 'TA_PERF_SEL_deriv_stalled_cycles', - 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_flat_atomic_wavefronts', - 'TA_PERF_SEL_flat_load_wavefronts', - 'TA_PERF_SEL_flat_store_wavefronts', - 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', - 'TA_PERF_SEL_gradient_busy', - 'TA_PERF_SEL_gradient_clk_valid_cycles', - 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', - 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', - 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 'TA_PERF_SEL_ibubble_1_cycle_burst', - 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 'TA_PERF_SEL_image_atomic_wavefronts', - 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_1_op_burst', - 'TA_PERF_SEL_image_bvh_2to3_op_burst', - 'TA_PERF_SEL_image_bvh_4to7_op_burst', - 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_ge8_op_burst', - 'TA_PERF_SEL_image_linked_1_op_burst', - 'TA_PERF_SEL_image_linked_2to3_op_burst', - 'TA_PERF_SEL_image_linked_4to7_op_burst', - 'TA_PERF_SEL_image_linked_ge8_op_burst', - 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_1_op_burst', - 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 'TA_PERF_SEL_image_nosampler_total_cycles', - 'TA_PERF_SEL_image_read_wavefronts', - 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_op_burst', - 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 'TA_PERF_SEL_image_sampler_has_q_instructions', - 'TA_PERF_SEL_image_sampler_has_r_instructions', - 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 'TA_PERF_SEL_image_sampler_has_t_instructions', - 'TA_PERF_SEL_image_sampler_total_cycles', - 'TA_PERF_SEL_image_sampler_wavefronts', - 'TA_PERF_SEL_image_store_wavefronts', - 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', - 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', - 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', - 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', - 'TA_PERF_SEL_in_waiting_on_req_cycles', - 'TA_PERF_SEL_in_wfifo_busy', - 'TA_PERF_SEL_latency_ram_ref_required_instructions', - 'TA_PERF_SEL_latency_ram_weights_written_cycles', - 'TA_PERF_SEL_latency_ram_whv_required_instructions', - 'TA_PERF_SEL_latency_ram_whv_required_quads', - 'TA_PERF_SEL_latency_ram_ws_required_instructions', - 'TA_PERF_SEL_latency_ram_ws_required_quads', - 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', - 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', - 'TA_PERF_SEL_mip_2_cycle_quads', - 'TA_PERF_SEL_mipmap_invalid_samples', - 'TA_PERF_SEL_mipmap_lod_0_samples', - 'TA_PERF_SEL_mipmap_lod_10_samples', - 'TA_PERF_SEL_mipmap_lod_11_samples', - 'TA_PERF_SEL_mipmap_lod_12_samples', - 'TA_PERF_SEL_mipmap_lod_13_samples', - 'TA_PERF_SEL_mipmap_lod_14_samples', - 'TA_PERF_SEL_mipmap_lod_1_samples', - 'TA_PERF_SEL_mipmap_lod_2_samples', - 'TA_PERF_SEL_mipmap_lod_3_samples', - 'TA_PERF_SEL_mipmap_lod_4_samples', - 'TA_PERF_SEL_mipmap_lod_5_samples', - 'TA_PERF_SEL_mipmap_lod_6_samples', - 'TA_PERF_SEL_mipmap_lod_7_samples', - 'TA_PERF_SEL_mipmap_lod_8_samples', - 'TA_PERF_SEL_mipmap_lod_9_samples', - 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', - 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', - 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', - 'TA_PERF_SEL_num_of_bvh_valid_first_tri', - 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', - 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', - 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', - 'TA_PERF_SEL_num_of_bvh_valid_second_tri', - 'TA_PERF_SEL_num_of_bvh_valid_third_tri', - 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 'TA_PERF_SEL_point_sampled_quads', - 'TA_PERF_SEL_register_clk_valid_cycles', - 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 'TA_PERF_SEL_sampler_clk_valid_cycles', - 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', - 'TA_PERF_SEL_smp_idle_ns_busy', - 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_has_w_instructions', - 'TA_PERF_SEL_store_has_x_instructions', - 'TA_PERF_SEL_store_has_y_instructions', - 'TA_PERF_SEL_store_has_z_instructions', - 'TA_PERF_SEL_store_write_data_input_cycles', - 'TA_PERF_SEL_store_write_data_output_cycles', - 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', - 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', - 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', - 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', - 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', - 'TA_PERF_SEL_write_4to31_op_burst', - 'TA_PERF_SEL_write_data_clk_valid_cycles', - 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', - 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', - 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', - 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', - 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', - 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', - 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', - 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', - 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TB_ACP_NOT_SEND', - 'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED', - 'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE', - 'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE', - 'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED', - 'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE', - 'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND', - 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND', - 'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K', - 'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW', - 'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE', - 'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND', - 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK', - 'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED', - 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES', - 'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES', - 'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER', - 'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT', - 'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP', - 'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED', - 'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE', - 'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420', - 'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE', - 'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET', - 'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE', - 'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE', - 'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND', - 'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE', - 'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND', - 'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET', - 'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED', - 'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420', - 'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB', - 'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF', - 'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES', - 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', - 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', - 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', - 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', - 'TCP_CACHE_STORE_POLICY_WT_EVICT', - 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', - 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', - 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', - 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', - 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', - 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', - 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', - 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', - 'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', - 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', - 'TCP_PERF_SEL_ALLOC_STALL', - 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', - 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', - 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', - 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', - 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL', - 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', - 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', - 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', - 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE', - 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ', - 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', - 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY', - 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', - 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', - 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', - 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', - 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', - 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', - 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', - 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', - 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', - 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', - 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', - 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', - 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', - 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', - 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', - 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', - 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', - 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', - 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', - 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', - 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', - 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', - 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', - 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', - 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', - 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', - 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', - 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', - 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', - 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', - 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', - 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', - 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', - 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', - 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', - 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', - 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', - 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', - 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', - 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', - 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', - 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', - 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', - 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', - 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', - 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', - 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', - 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', - 'TC_OP_RESERVED_NON_FLOAT_64_4', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', - 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', - 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', - 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', - 'TD_PERF_SEL_address_cmd_poison', - 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 'TD_PERF_SEL_blend_prt_with_prt_default_1', - 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', - 'TD_PERF_SEL_burst_bin_gather_1', - 'TD_PERF_SEL_burst_bin_gather_2to8', - 'TD_PERF_SEL_burst_bin_gather_9to16', - 'TD_PERF_SEL_burst_bin_gather_gt16', - 'TD_PERF_SEL_burst_bin_nofilter_1', - 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_sampler_1', - 'TD_PERF_SEL_burst_bin_sampler_2to8', - 'TD_PERF_SEL_burst_bin_sampler_9to16', - 'TD_PERF_SEL_burst_bin_sampler_gt16', - 'TD_PERF_SEL_bypassLerp_instr', - 'TD_PERF_SEL_core_state_ram_max_cnt', - 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', - 'TD_PERF_SEL_data_poison', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 'TD_PERF_SEL_done_scoreboard_is_full', - 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 'TD_PERF_SEL_done_scoreboard_not_empty', - 'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr', - 'TD_PERF_SEL_gather4h_instr', - 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', - 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr', - 'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr', - 'TD_PERF_SEL_lod_warn_from_ta', - 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', - 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', - 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_nofilter_busy', - 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 'TD_PERF_SEL_nofilter_d16_sclk_en', - 'TD_PERF_SEL_nofilter_d32_sclk_en', - 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 'TD_PERF_SEL_nofilter_formatters_turned_on', - 'TD_PERF_SEL_nofilter_insert_extra_comps', - 'TD_PERF_SEL_nofilter_pkr_full', - 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_sclk_en', - 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', - 'TD_PERF_SEL_one_comp_return_instr', - 'TD_PERF_SEL_opaque_black_border', - 'TD_PERF_SEL_out_of_order_instr', - 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 'TD_PERF_SEL_prt_ack_instr', - 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', - 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', - 'TD_PERF_SEL_ray_tracing_bvh4_busy', - 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', - 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', - 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', - 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', - 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', - 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', - 'TD_PERF_SEL_reference_data_rams_read', - 'TD_PERF_SEL_resmap_instr', - 'TD_PERF_SEL_resmap_with_aniso_filtering', - 'TD_PERF_SEL_resmap_with_cubemap_corner', - 'TD_PERF_SEL_resmap_with_no_more_filtering', - 'TD_PERF_SEL_resmap_with_volume_filtering', - 'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr', - 'TD_PERF_SEL_sampler_accum_sclk_en', - 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', - 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 'TD_PERF_SEL_sampler_bypass_sclk_en', - 'TD_PERF_SEL_sampler_core_sclk_en', - 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 'TD_PERF_SEL_sampler_lerp0_active', - 'TD_PERF_SEL_sampler_lerp1_active', - 'TD_PERF_SEL_sampler_lerp2_active', - 'TD_PERF_SEL_sampler_lerp3_active', - 'TD_PERF_SEL_sampler_lerp_busy', - 'TD_PERF_SEL_sampler_minmax_sclk_en', - 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', - 'TD_PERF_SEL_sampler_pkr_full', - 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', - 'TD_PERF_SEL_tc_td_data_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_three_comp_return_instr', - 'TD_PERF_SEL_total_num_instr', - 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_nofilter_instr', - 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', - 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_sampler_instr', - 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 'TD_PERF_SEL_two_comp_return_instr', - 'TD_PERF_SEL_user_defined_border', - 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', - 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', - 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', - 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', - 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', - 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', - 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', - 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', - 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', - 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', - 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', - 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', - 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', - 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', - 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', - 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', - 'TEX_Clamp_MirrorOnceHalfToBorder', - 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', - 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', - 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', - 'TEX_DepthCompareFunction_Always', - 'TEX_DepthCompareFunction_Equal', - 'TEX_DepthCompareFunction_Greater', - 'TEX_DepthCompareFunction_GreaterEqual', - 'TEX_DepthCompareFunction_Less', - 'TEX_DepthCompareFunction_LessEqual', - 'TEX_DepthCompareFunction_Never', - 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', - 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', - 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', - 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', - 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', - 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', - 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', - 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', - 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', - 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', - 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', - 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', - 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', - 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', - 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', - 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', - 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', - 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', - 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', - 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK', - 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', - 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', - 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', - 'TMDS_CTL0_DATA_MODULATION_BIT1', - 'TMDS_CTL0_DATA_MODULATION_BIT2', - 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', - 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', - 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', - 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', - 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', - 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', - 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', - 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', - 'TMDS_CTL1_DATA_MODULATION_BIT0', - 'TMDS_CTL1_DATA_MODULATION_BIT1', - 'TMDS_CTL1_DATA_MODULATION_BIT2', - 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', - 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', - 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', - 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', - 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', - 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', - 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', - 'TMDS_CTL2_DATA_MODULATION_BIT0', - 'TMDS_CTL2_DATA_MODULATION_BIT1', - 'TMDS_CTL2_DATA_MODULATION_BIT2', - 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', - 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', - 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', - 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', - 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', - 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', - 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', - 'TMDS_CTL3_DATA_MODULATION_BIT0', - 'TMDS_CTL3_DATA_MODULATION_BIT1', - 'TMDS_CTL3_DATA_MODULATION_BIT2', - 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', - 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', - 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', - 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', - 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', - 'TMDS_CTL3_PATTERN_OUT_ENABLE', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', - 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', - 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', - 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', - 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', - 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', - 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', - 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', - 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', - 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', - 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', - 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', - 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', - 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', - 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', - 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', - 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', - 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', - 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', - 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', - 'UCONFIG_SPACE_START', 'UNDEF', 'UNSIGNED', 'USE_MALL_FOR_CURSOR', - 'USE_MALL_FOR_CURSOR_0', 'USE_MALL_FOR_CURSOR_1', - 'USE_MALL_FOR_PSTATE_CHANGE', 'USE_MALL_FOR_PSTATE_CHANGE_0', - 'USE_MALL_FOR_PSTATE_CHANGE_1', 'USE_MALL_FOR_STATIC_SCREEN', - 'USE_MALL_FOR_STATIC_SCREEN_0', 'USE_MALL_FOR_STATIC_SCREEN_1', - 'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', - 'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN', - 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY', - 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel', - 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', - 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS', - 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', - 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', - 'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS', - 'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS', - 'UTCL1_PERF_SEL_STALL_MH_FULL', - 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS', - 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', - 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', - 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', - 'UTCL1_XNACK_SUCCESS', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', - 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', - 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', - 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', - 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', - 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', - 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', - 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', - 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', - 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', - 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', - 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', - 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', - 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', - 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', - 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', - 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', - 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', - 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', - 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', - 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', - 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', - 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', - 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', - 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', - 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', - 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', - 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', - 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', - 'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ', - 'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', - 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE', - 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', - 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', - 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB', - 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB', - 'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB', - 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB', - 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', - 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', - 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', - 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', - 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', - 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', - 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', - 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', - 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', - 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', - 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', - 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', - 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', - 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', - 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', - 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', - 'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', - 'VTG_SEL_5', 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', - 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', - 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', - 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', - 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', - 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', - 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', - 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', - 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XNORM', - 'XNORM_A', 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', - 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', - 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', - 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', - 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', - 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', - 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', - 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', - 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', - 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', - 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', - 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', - 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', - 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', - 'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', - 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', - 'ZpassControl', '_soc21_ENUM_HEADER', 'ge1_assembler_busy', - 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', - 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', - 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', - 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', - 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', - 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', - 'ge1_dma_utcl1_consecutive_retry_event', - 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', - 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', - 'ge1_dma_utcl1_translation_hit_event', - 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', - 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', - 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', - 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', - 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', - 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', - 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', - 'ge1_small_draws_one_instance', 'ge1_stat_busy', - 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', - 'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req', - 'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2', - 'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6', - 'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy', - 'ge_dist_hs_done', 'ge_dist_hs_done_latency', - 'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1', - 'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3', - 'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5', - 'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7', - 'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1', - 'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3', - 'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5', - 'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7', - 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', - 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', - 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', - 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', - 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', - 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', - 'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0', - 'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2', - 'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4', - 'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6', - 'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero', - 'ge_dist_reserved', 'ge_dist_sclk_core_vld', - 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', - 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', - 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', - 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', - 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', - 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', - 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 'ge_dist_tfreq_utcl1_request_event', - 'ge_dist_tfreq_utcl1_retry_event', - 'ge_dist_tfreq_utcl1_stall_event', - 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 'ge_dist_tfreq_utcl1_translation_hit_event', - 'ge_dist_tfreq_utcl1_translation_miss_event', - 'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld', - 'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', - 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', - 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', - 'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc', - 'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency', - 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', - 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', - 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', - 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', - 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', - 'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant', - 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', - 'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches', - 'ge_num_of_patch_dist_patches', - 'ge_num_of_se_switches_due_to_donut', - 'ge_num_of_se_switches_due_to_patch_accum', - 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', - 'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done', - 'ge_se1_te11_starved_on_hs_done', - 'ge_se2_te11_starved_on_hs_done', - 'ge_se3_te11_starved_on_hs_done', - 'ge_se4_te11_starved_on_hs_done', - 'ge_se5_te11_starved_on_hs_done', - 'ge_se6_te11_starved_on_hs_done', - 'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims', - 'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim', - 'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall', - 'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups', - 'ge_se_reused_es_indices', 'ge_se_sclk_input_vld', - 'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld', - 'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov', - 'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy', - 'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont', - 'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled', - 'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid', - 'ge_se_spi_gssubgrp_event_window_active', - 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', - 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', - 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', - 'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event', - 'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov', - 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', - 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', - 'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall', - 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall', - 'ge_te11_compactor_starved', 'ge_te11_con_stall', - 'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel', - 'ge_tf_ret_data_stalling_hs_done'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/soc24.py b/tinygrad/tinygrad/runtime/autogen/am/soc24.py deleted file mode 100644 index 42e5a603..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/soc24.py +++ /dev/null @@ -1,37140 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - - - -_soc24_ENUM_HEADER = True # macro -CSDATA_TYPE_WIDTH = 0x00000002 # macro -CSDATA_ADDR_WIDTH = 0x00000007 # macro -CSDATA_DATA_WIDTH = 0x00000020 # macro -CSCNTL_TYPE_WIDTH = 0x00000002 # macro -CSCNTL_ADDR_WIDTH = 0x00000007 # macro -CSCNTL_DATA_WIDTH = 0x00000020 # macro -GSTHREADID_SIZE = 0x00000002 # macro -IQ_QUEUE_SLEEP = 0x00000000 # macro -IQ_OFFLOAD_RETRY = 0x00000001 # macro -IQ_SCH_WAVE_MSG = 0x00000002 # macro -IQ_DEQUEUE_RETRY = 0x00000004 # macro -IQ_INTR_TYPE_PQ = 0x00000000 # macro -IQ_INTR_TYPE_IB = 0x00000001 # macro -IQ_INTR_TYPE_MQD = 0x00000002 # macro -VMID_SZ = 0x00000004 # macro -CONFIG_SPACE_START = 0x00002000 # macro -CONFIG_SPACE_END = 0x00009fff # macro -CONFIG_SPACE1_START = 0x00002000 # macro -CONFIG_SPACE1_END = 0x00002bff # macro -CONFIG_SPACE2_START = 0x00003000 # macro -CONFIG_SPACE2_END = 0x00009fff # macro -UCONFIG_SPACE_START = 0x0000c000 # macro -UCONFIG_SPACE_END = 0x0000ffff # macro -PERSISTENT_SPACE_START = 0x00002c00 # macro -PERSISTENT_SPACE_END = 0x00002fff # macro -CONTEXT_SPACE_START = 0x0000a000 # macro -CONTEXT_SPACE_END = 0x0000a3ff # macro -SQ_WAVE_TYPE_PS0 = 0x00000000 # macro -SQ_FLAT = 0x00000000 # macro -SQ_SCRATCH = 0x00000001 # macro -SQ_GLOBAL = 0x00000002 # macro -SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro -SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro -SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro -SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro -SQIND_WAVE_HW_REGS_OFFSET = 0x00000100 # macro -SQIND_WAVE_HW_REGS_SIZE = 0x00000040 # macro -SQIND_WAVE_HOST_REGS_OFFSET = 0x00000140 # macro -SQIND_WAVE_HOST_REGS_SIZE = 0x000000c0 # macro -SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro -SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro -SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro -SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro -SQ_GFXDEC_BEGIN = 0x0000a000 # macro -SQ_GFXDEC_END = 0x0000c000 # macro -SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro -SQDEC_BEGIN = 0x00002300 # macro -SQDEC_END = 0x000023ff # macro -PFVF_SQDEC_BEGIN = 0x0000a9e0 # macro -PFVF_SQDEC_END = 0x0000a9ff # macro -SQPERFSDEC_BEGIN = 0x0000d9c0 # macro -SQPERFSDEC_END = 0x0000da40 # macro -SQPERFDDEC_BEGIN = 0x0000d1c0 # macro -SQPERFDDEC_END = 0x0000d240 # macro -SQGFXUDEC_BEGIN = 0x0000c330 # macro -SQGFXUDEC_END = 0x0000c380 # macro -SQPWRDEC_BEGIN = 0x0000f08c # macro -SQPWRDEC_END = 0x0000f094 # macro -SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro -SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro -SQ_MAX_PGM_SGPRS = 0x00000068 # macro -SQ_MAX_PGM_VGPRS = 0x00000100 # macro -SQ_EX_EXCP_VALU_BASE = 0x00000000 # macro -SQ_EX_EXCP_VALU_SIZE = 0x00000007 # macro -SQ_EX_EXCP_ALU_INVALID = 0x00000000 # macro -SQ_EX_EXCP_ALU_INPUT_DENORM = 0x00000001 # macro -SQ_EX_EXCP_ALU_FLOAT_DIV0 = 0x00000002 # macro -SQ_EX_EXCP_ALU_OVERFLOW = 0x00000003 # macro -SQ_EX_EXCP_ALU_UNDERFLOW = 0x00000004 # macro -SQ_EX_EXCP_ALU_INEXACT = 0x00000005 # macro -SQ_EX_EXCP_ALU_INT_DIV0 = 0x00000006 # macro -SQ_EX_EXCP_ADDR_WATCH = 0x00000007 # macro -INST_ID_PRIV_START = 0x80000000 # macro -INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro -INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro -INST_ID_HW_TRAP = 0xfffffff2 # macro -INST_ID_KILL_SEQ = 0xfffffff3 # macro -INST_ID_SPI_WREXEC = 0xfffffff4 # macro -INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro -INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro -SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro -SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro -SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro -SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000007 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro -SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro -SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro -SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro -SQ_ARB_STATE_ISSUED_BRMSG = 0x00000000 # macro -SQ_ARB_STATE_ISSUED_EXPORT = 0x00000001 # macro -SQ_ARB_STATE_ISSUED_LDS_DIRECT = 0x00000002 # macro -SQ_ARB_STATE_ISSUED_LDS = 0x00000003 # macro -SQ_ARB_STATE_ISSUED_TEX = 0x00000004 # macro -SQ_ARB_STATE_ISSUED_SCALAR = 0x00000005 # macro -SQ_ARB_STATE_ISSUED_VALU = 0x00000006 # macro -SQ_ARB_STATE_STALLED_BRMSG = 0x00000008 # macro -SQ_ARB_STATE_STALLED_EXPORT = 0x00000009 # macro -SQ_ARB_STATE_STALLED_LDS_DIRECT = 0x0000000a # macro -SQ_ARB_STATE_STALLED_LDS = 0x0000000b # macro -SQ_ARB_STATE_STALLED_TEX = 0x0000000c # macro -SQ_ARB_STATE_STALLED_SCALAR = 0x0000000d # macro -SQ_ARB_STATE_STALLED_VALU = 0x0000000e # macro -ROM_SIGNATURE = 0x0000aa55 # macro - -# values for enumeration 'CP_PERFMON_ENABLE_MODE' -CP_PERFMON_ENABLE_MODE__enumvalues = { - 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', - 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', -} -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 -CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_STATE' -CP_PERFMON_STATE__enumvalues = { - 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'CP_PERFMON_STATE_START_COUNTING', - 2: 'CP_PERFMON_STATE_STOP_COUNTING', - 3: 'CP_PERFMON_STATE_RESERVED_3', - 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -CP_PERFMON_STATE_DISABLE_AND_RESET = 0 -CP_PERFMON_STATE_START_COUNTING = 1 -CP_PERFMON_STATE_STOP_COUNTING = 2 -CP_PERFMON_STATE_RESERVED_3 = 3 -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -CP_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_NUM_SIMD_PER_CU' -ENUM_NUM_SIMD_PER_CU__enumvalues = { - 2: 'NUM_SIMD_PER_CU', -} -NUM_SIMD_PER_CU = 2 -ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum - -# values for enumeration 'GATCL1RequestType' -GATCL1RequestType__enumvalues = { - 0: 'GATCL1_TYPE_NORMAL', - 1: 'GATCL1_TYPE_SHOOTDOWN', - 2: 'GATCL1_TYPE_BYPASS', -} -GATCL1_TYPE_NORMAL = 0 -GATCL1_TYPE_SHOOTDOWN = 1 -GATCL1_TYPE_BYPASS = 2 -GATCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'GL0V_CACHE_POLICIES' -GL0V_CACHE_POLICIES__enumvalues = { - 0: 'GL0V_CACHE_POLICY_MISS_LRU', - 1: 'GL0V_CACHE_POLICY_MISS_EVICT', - 2: 'GL0V_CACHE_POLICY_HIT_LRU', - 3: 'GL0V_CACHE_POLICY_HIT_EVICT', - 4: 'GL0V_CACHE_POLICY_MISS_INVAL', -} -GL0V_CACHE_POLICY_MISS_LRU = 0 -GL0V_CACHE_POLICY_MISS_EVICT = 1 -GL0V_CACHE_POLICY_HIT_LRU = 2 -GL0V_CACHE_POLICY_HIT_EVICT = 3 -GL0V_CACHE_POLICY_MISS_INVAL = 4 -GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_POLICIES' -GL1_CACHE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_POLICY_MISS_LRU', - 1: 'GL1_CACHE_POLICY_MISS_EVICT', - 2: 'GL1_CACHE_POLICY_HIT_LRU', - 3: 'GL1_CACHE_POLICY_HIT_EVICT', -} -GL1_CACHE_POLICY_MISS_LRU = 0 -GL1_CACHE_POLICY_MISS_EVICT = 1 -GL1_CACHE_POLICY_HIT_LRU = 2 -GL1_CACHE_POLICY_HIT_EVICT = 3 -GL1_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_STORE_POLICIES' -GL1_CACHE_STORE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_STORE_POLICY_BYPASS', -} -GL1_CACHE_STORE_POLICY_BYPASS = 0 -GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_CACHE_POLICIES' -GL2_CACHE_POLICIES__enumvalues = { - 0: 'GL2_CACHE_POLICY_LRU', - 1: 'GL2_CACHE_POLICY_STREAM', - 2: 'GL2_CACHE_POLICY_NOA', - 3: 'GL2_CACHE_POLICY_BYPASS', -} -GL2_CACHE_POLICY_LRU = 0 -GL2_CACHE_POLICY_STREAM = 1 -GL2_CACHE_POLICY_NOA = 2 -GL2_CACHE_POLICY_BYPASS = 3 -GL2_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_NACKS' -GL2_NACKS__enumvalues = { - 0: 'GL2_NACK_NO_FAULT', - 1: 'GL2_NACK_PAGE_FAULT', - 2: 'GL2_NACK_PROTECTION_FAULT', - 3: 'GL2_NACK_DATA_ERROR', -} -GL2_NACK_NO_FAULT = 0 -GL2_NACK_PAGE_FAULT = 1 -GL2_NACK_PROTECTION_FAULT = 2 -GL2_NACK_DATA_ERROR = 3 -GL2_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP' -GL2_OP__enumvalues = { - 0: 'GL2_OP_READ', - 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', - 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', - 4: 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN', - 5: 'GL2_OP_ATOMIC_FADD_RTN_32', - 6: 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN', - 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', - 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'GL2_OP_PROBE_FILTER', - 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'GL2_OP_ATOMIC_ADD_RTN_32', - 16: 'GL2_OP_ATOMIC_SUB_RTN_32', - 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', - 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', - 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', - 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', - 21: 'GL2_OP_ATOMIC_AND_RTN_32', - 22: 'GL2_OP_ATOMIC_OR_RTN_32', - 23: 'GL2_OP_ATOMIC_XOR_RTN_32', - 24: 'GL2_OP_ATOMIC_INC_RTN_32', - 25: 'GL2_OP_ATOMIC_DEC_RTN_32', - 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 27: 'GL2_OP_ATOMIC_COND_SUB_RTN_32', - 29: 'GL2_OP_UTC_PROBE', - 30: 'GL2_OP_LOAD_RESERVE', - 32: 'GL2_OP_WRITE', - 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', - 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', - 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', - 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 47: 'GL2_OP_ATOMIC_ADD_RTN_64', - 48: 'GL2_OP_ATOMIC_SUB_RTN_64', - 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', - 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', - 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', - 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', - 53: 'GL2_OP_ATOMIC_AND_RTN_64', - 54: 'GL2_OP_ATOMIC_OR_RTN_64', - 55: 'GL2_OP_ATOMIC_XOR_RTN_64', - 56: 'GL2_OP_ATOMIC_INC_RTN_64', - 57: 'GL2_OP_ATOMIC_DEC_RTN_64', - 59: 'GL2_OP_WRITE_ZERO_SIZE', - 61: 'GL2_OP_GL2_INV', - 62: 'GL2_OP_ATOMIC_STORE_COND_RTN', - 64: 'GL2_OP_GL1_INV', - 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', - 66: 'GL2_OP_ATOMIC_FMIN_32', - 67: 'GL2_OP_ATOMIC_FMAX_32', - 68: 'GL2_OP_ATOMIC_PK_ADD_FP16', - 69: 'GL2_OP_ATOMIC_FADD_32', - 70: 'GL2_OP_ATOMIC_PK_ADD_BF16', - 71: 'GL2_OP_ATOMIC_SWAP_32', - 72: 'GL2_OP_ATOMIC_CMPSWAP_32', - 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'GL2_OP_ATOMIC_UMIN_8', - 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 79: 'GL2_OP_ATOMIC_ADD_32', - 80: 'GL2_OP_ATOMIC_SUB_32', - 81: 'GL2_OP_ATOMIC_SMIN_32', - 82: 'GL2_OP_ATOMIC_UMIN_32', - 83: 'GL2_OP_ATOMIC_SMAX_32', - 84: 'GL2_OP_ATOMIC_UMAX_32', - 85: 'GL2_OP_ATOMIC_AND_32', - 86: 'GL2_OP_ATOMIC_OR_32', - 87: 'GL2_OP_ATOMIC_XOR_32', - 88: 'GL2_OP_ATOMIC_INC_32', - 89: 'GL2_OP_ATOMIC_DEC_32', - 91: 'GL2_OP_NOP_RTN0', - 93: 'GL2_OP_GL2_WB', - 94: 'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS', - 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', - 98: 'GL2_OP_ATOMIC_FMIN_64', - 99: 'GL2_OP_ATOMIC_FMAX_64', - 103: 'GL2_OP_ATOMIC_SWAP_64', - 104: 'GL2_OP_ATOMIC_CMPSWAP_64', - 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 111: 'GL2_OP_ATOMIC_ADD_64', - 112: 'GL2_OP_ATOMIC_SUB_64', - 113: 'GL2_OP_ATOMIC_SMIN_64', - 114: 'GL2_OP_ATOMIC_UMIN_64', - 115: 'GL2_OP_ATOMIC_SMAX_64', - 116: 'GL2_OP_ATOMIC_UMAX_64', - 117: 'GL2_OP_ATOMIC_AND_64', - 118: 'GL2_OP_ATOMIC_OR_64', - 119: 'GL2_OP_ATOMIC_XOR_64', - 120: 'GL2_OP_ATOMIC_INC_64', - 121: 'GL2_OP_ATOMIC_DEC_64', - 122: 'GL2_OP_ATOMIC_UMAX_8', - 123: 'GL2_OP_NOP_ACK', - 125: 'GL2_OP_GL2_WBINV', - 126: 'GL2_OP_READ_COMPRESSION_KEY', -} -GL2_OP_READ = 0 -GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -GL2_OP_ATOMIC_FMIN_RTN_32 = 2 -GL2_OP_ATOMIC_FMAX_RTN_32 = 3 -GL2_OP_ATOMIC_PK_ADD_FP16_RTN = 4 -GL2_OP_ATOMIC_FADD_RTN_32 = 5 -GL2_OP_ATOMIC_PK_ADD_BF16_RTN = 6 -GL2_OP_ATOMIC_SWAP_RTN_32 = 7 -GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -GL2_OP_PROBE_FILTER = 12 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -GL2_OP_ATOMIC_ADD_RTN_32 = 15 -GL2_OP_ATOMIC_SUB_RTN_32 = 16 -GL2_OP_ATOMIC_SMIN_RTN_32 = 17 -GL2_OP_ATOMIC_UMIN_RTN_32 = 18 -GL2_OP_ATOMIC_SMAX_RTN_32 = 19 -GL2_OP_ATOMIC_UMAX_RTN_32 = 20 -GL2_OP_ATOMIC_AND_RTN_32 = 21 -GL2_OP_ATOMIC_OR_RTN_32 = 22 -GL2_OP_ATOMIC_XOR_RTN_32 = 23 -GL2_OP_ATOMIC_INC_RTN_32 = 24 -GL2_OP_ATOMIC_DEC_RTN_32 = 25 -GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 -GL2_OP_ATOMIC_COND_SUB_RTN_32 = 27 -GL2_OP_UTC_PROBE = 29 -GL2_OP_LOAD_RESERVE = 30 -GL2_OP_WRITE = 32 -GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -GL2_OP_ATOMIC_FMIN_RTN_64 = 34 -GL2_OP_ATOMIC_FMAX_RTN_64 = 35 -GL2_OP_ATOMIC_SWAP_RTN_64 = 39 -GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -GL2_OP_ATOMIC_ADD_RTN_64 = 47 -GL2_OP_ATOMIC_SUB_RTN_64 = 48 -GL2_OP_ATOMIC_SMIN_RTN_64 = 49 -GL2_OP_ATOMIC_UMIN_RTN_64 = 50 -GL2_OP_ATOMIC_SMAX_RTN_64 = 51 -GL2_OP_ATOMIC_UMAX_RTN_64 = 52 -GL2_OP_ATOMIC_AND_RTN_64 = 53 -GL2_OP_ATOMIC_OR_RTN_64 = 54 -GL2_OP_ATOMIC_XOR_RTN_64 = 55 -GL2_OP_ATOMIC_INC_RTN_64 = 56 -GL2_OP_ATOMIC_DEC_RTN_64 = 57 -GL2_OP_WRITE_ZERO_SIZE = 59 -GL2_OP_GL2_INV = 61 -GL2_OP_ATOMIC_STORE_COND_RTN = 62 -GL2_OP_GL1_INV = 64 -GL2_OP_ATOMIC_FCMPSWAP_32 = 65 -GL2_OP_ATOMIC_FMIN_32 = 66 -GL2_OP_ATOMIC_FMAX_32 = 67 -GL2_OP_ATOMIC_PK_ADD_FP16 = 68 -GL2_OP_ATOMIC_FADD_32 = 69 -GL2_OP_ATOMIC_PK_ADD_BF16 = 70 -GL2_OP_ATOMIC_SWAP_32 = 71 -GL2_OP_ATOMIC_CMPSWAP_32 = 72 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -GL2_OP_ATOMIC_UMIN_8 = 76 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -GL2_OP_ATOMIC_ADD_32 = 79 -GL2_OP_ATOMIC_SUB_32 = 80 -GL2_OP_ATOMIC_SMIN_32 = 81 -GL2_OP_ATOMIC_UMIN_32 = 82 -GL2_OP_ATOMIC_SMAX_32 = 83 -GL2_OP_ATOMIC_UMAX_32 = 84 -GL2_OP_ATOMIC_AND_32 = 85 -GL2_OP_ATOMIC_OR_32 = 86 -GL2_OP_ATOMIC_XOR_32 = 87 -GL2_OP_ATOMIC_INC_32 = 88 -GL2_OP_ATOMIC_DEC_32 = 89 -GL2_OP_NOP_RTN0 = 91 -GL2_OP_GL2_WB = 93 -GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 94 -GL2_OP_ATOMIC_FCMPSWAP_64 = 97 -GL2_OP_ATOMIC_FMIN_64 = 98 -GL2_OP_ATOMIC_FMAX_64 = 99 -GL2_OP_ATOMIC_SWAP_64 = 103 -GL2_OP_ATOMIC_CMPSWAP_64 = 104 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -GL2_OP_ATOMIC_ADD_64 = 111 -GL2_OP_ATOMIC_SUB_64 = 112 -GL2_OP_ATOMIC_SMIN_64 = 113 -GL2_OP_ATOMIC_UMIN_64 = 114 -GL2_OP_ATOMIC_SMAX_64 = 115 -GL2_OP_ATOMIC_UMAX_64 = 116 -GL2_OP_ATOMIC_AND_64 = 117 -GL2_OP_ATOMIC_OR_64 = 118 -GL2_OP_ATOMIC_XOR_64 = 119 -GL2_OP_ATOMIC_INC_64 = 120 -GL2_OP_ATOMIC_DEC_64 = 121 -GL2_OP_ATOMIC_UMAX_8 = 122 -GL2_OP_NOP_ACK = 123 -GL2_OP_GL2_WBINV = 125 -GL2_OP_READ_COMPRESSION_KEY = 126 -GL2_OP = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP_MASKS' -GL2_OP_MASKS__enumvalues = { - 8: 'GL2_OP_MASK_FLUSH_DENROM', - 32: 'GL2_OP_MASK_64', - 64: 'GL2_OP_MASK_NO_RTN', -} -GL2_OP_MASK_FLUSH_DENROM = 8 -GL2_OP_MASK_64 = 32 -GL2_OP_MASK_NO_RTN = 64 -GL2_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'Hdp_SurfaceEndian' -Hdp_SurfaceEndian__enumvalues = { - 0: 'HDP_ENDIAN_NONE', - 1: 'HDP_ENDIAN_8IN16', - 2: 'HDP_ENDIAN_8IN32', - 3: 'HDP_ENDIAN_8IN64', -} -HDP_ENDIAN_NONE = 0 -HDP_ENDIAN_8IN16 = 1 -HDP_ENDIAN_8IN32 = 2 -HDP_ENDIAN_8IN64 = 3 -Hdp_SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'MTYPE' -MTYPE__enumvalues = { - 0: 'MTYPE_C_RW_US', - 1: 'MTYPE_RESERVED_1', - 2: 'MTYPE_C_RO_S', - 3: 'MTYPE_UC', - 4: 'MTYPE_C_RW_S', - 5: 'MTYPE_RESERVED_5', - 6: 'MTYPE_C_RO_US', - 7: 'MTYPE_RESERVED_7', -} -MTYPE_C_RW_US = 0 -MTYPE_RESERVED_1 = 1 -MTYPE_C_RO_S = 2 -MTYPE_UC = 3 -MTYPE_C_RW_S = 4 -MTYPE_RESERVED_5 = 5 -MTYPE_C_RO_US = 6 -MTYPE_RESERVED_7 = 7 -MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_COUNTER_MODE' -PERFMON_COUNTER_MODE__enumvalues = { - 0: 'PERFMON_COUNTER_MODE_ACCUM', - 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 2: 'PERFMON_COUNTER_MODE_MAX', - 3: 'PERFMON_COUNTER_MODE_DIRTY', - 4: 'PERFMON_COUNTER_MODE_SAMPLE', - 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 15: 'PERFMON_COUNTER_MODE_RESERVED', -} -PERFMON_COUNTER_MODE_ACCUM = 0 -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 -PERFMON_COUNTER_MODE_MAX = 2 -PERFMON_COUNTER_MODE_DIRTY = 3 -PERFMON_COUNTER_MODE_SAMPLE = 4 -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 -PERFMON_COUNTER_MODE_RESERVED = 15 -PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_SPM_MODE' -PERFMON_SPM_MODE__enumvalues = { - 0: 'PERFMON_SPM_MODE_OFF', - 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', - 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', - 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 5: 'PERFMON_SPM_MODE_RESERVED_5', - 6: 'PERFMON_SPM_MODE_RESERVED_6', - 7: 'PERFMON_SPM_MODE_RESERVED_7', - 8: 'PERFMON_SPM_MODE_TEST_MODE_0', - 9: 'PERFMON_SPM_MODE_TEST_MODE_1', - 10: 'PERFMON_SPM_MODE_TEST_MODE_2', -} -PERFMON_SPM_MODE_OFF = 0 -PERFMON_SPM_MODE_16BIT_CLAMP = 1 -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 -PERFMON_SPM_MODE_32BIT_CLAMP = 3 -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 -PERFMON_SPM_MODE_RESERVED_5 = 5 -PERFMON_SPM_MODE_RESERVED_6 = 6 -PERFMON_SPM_MODE_RESERVED_7 = 7 -PERFMON_SPM_MODE_TEST_MODE_0 = 8 -PERFMON_SPM_MODE_TEST_MODE_1 = 9 -PERFMON_SPM_MODE_TEST_MODE_2 = 10 -PERFMON_SPM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'READ_COMPRESSION_MODE' -READ_COMPRESSION_MODE__enumvalues = { - 0: 'COMPRESSION_MODE_BYPASS_COMPRESSION', - 1: 'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA', - 2: 'COMPRESSION_MODE_READ_DECOMPRESSED', -} -COMPRESSION_MODE_BYPASS_COMPRESSION = 0 -COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 1 -COMPRESSION_MODE_READ_DECOMPRESSED = 2 -READ_COMPRESSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ReadPolicy' -ReadPolicy__enumvalues = { - 0: 'CACHE_LRU_RD', - 1: 'CACHE_STREAM_RD', - 2: 'CACHE_NOA', - 3: 'RESERVED_RDPOLICY', -} -CACHE_LRU_RD = 0 -CACHE_STREAM_RD = 1 -CACHE_NOA = 2 -RESERVED_RDPOLICY = 3 -ReadPolicy = ctypes.c_uint32 # enum - -# values for enumeration 'SCOPE' -SCOPE__enumvalues = { - 0: 'SCOPE_CU', - 1: 'SCOPE_SE', - 2: 'SCOPE_DEV', - 3: 'SCOPE_SYS', -} -SCOPE_CU = 0 -SCOPE_SE = 1 -SCOPE_DEV = 2 -SCOPE_SYS = 3 -SCOPE = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERFMON_SEL' -SDMA_PERFMON_SEL__enumvalues = { - 0: 'SDMA_PERFMON_SEL_CYCLE', - 1: 'SDMA_PERFMON_SEL_IDLE', - 2: 'SDMA_PERFMON_SEL_REG_IDLE', - 3: 'SDMA_PERFMON_SEL_RB_EMPTY', - 4: 'SDMA_PERFMON_SEL_RB_FULL', - 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', - 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', - 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 13: 'SDMA_PERFMON_SEL_EX_IDLE', - 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', - 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', - 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', - 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', - 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 26: 'SDMA_PERFMON_SEL_SEM_IDLE', - 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 32: 'SDMA_PERFMON_SEL_INT_IDLE', - 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 37: 'SDMA_PERFMON_SEL_NUM_PACKET', - 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', - 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', - 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', - 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', - 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', - 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', - 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', - 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', - 49: 'SDMA_PERFMON_SEL_DUMMY_0', - 50: 'SDMA_PERFMON_SEL_DUMMY_1', - 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', - 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', - 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', - 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', - 55: 'SDMA_PERFMON_SEL_QUEUE0_SELECT', - 56: 'SDMA_PERFMON_SEL_QUEUE1_SELECT', - 57: 'SDMA_PERFMON_SEL_QUEUE2_SELECT', - 58: 'SDMA_PERFMON_SEL_QUEUE3_SELECT', - 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', - 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', - 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 62: 'SDMA_PERFMON_SEL_DOORBELL', - 63: 'SDMA_PERFMON_SEL_MCU_L1_WR_VLD', - 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', - 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', - 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', - 95: 'SDMA_PERFMON_SEL_TLBI_SEND', - 96: 'SDMA_PERFMON_SEL_TLBI_RTN', - 97: 'SDMA_PERFMON_SEL_GCR_SEND', - 98: 'SDMA_PERFMON_SEL_GCR_RTN', - 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', -} -SDMA_PERFMON_SEL_CYCLE = 0 -SDMA_PERFMON_SEL_IDLE = 1 -SDMA_PERFMON_SEL_REG_IDLE = 2 -SDMA_PERFMON_SEL_RB_EMPTY = 3 -SDMA_PERFMON_SEL_RB_FULL = 4 -SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 -SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 -SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERFMON_SEL_RB_RPTR_WB = 8 -SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 -SDMA_PERFMON_SEL_RB_CMD_FULL = 10 -SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 -SDMA_PERFMON_SEL_IB_CMD_FULL = 12 -SDMA_PERFMON_SEL_EX_IDLE = 13 -SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 -SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERFMON_SEL_WR_BA_RTR = 16 -SDMA_PERFMON_SEL_MC_WR_IDLE = 17 -SDMA_PERFMON_SEL_MC_WR_COUNT = 18 -SDMA_PERFMON_SEL_RD_BA_RTR = 19 -SDMA_PERFMON_SEL_MC_RD_IDLE = 20 -SDMA_PERFMON_SEL_MC_RD_COUNT = 21 -SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 -SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 -SDMA_PERFMON_SEL_SEM_IDLE = 26 -SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 -SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 -SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 -SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 -SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 -SDMA_PERFMON_SEL_INT_IDLE = 32 -SDMA_PERFMON_SEL_INT_REQ_STALL = 33 -SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 -SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 -SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 -SDMA_PERFMON_SEL_NUM_PACKET = 37 -SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 -SDMA_PERFMON_SEL_CE_WR_IDLE = 40 -SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 -SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 -SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 -SDMA_PERFMON_SEL_CE_IN_IDLE = 44 -SDMA_PERFMON_SEL_CE_DST_IDLE = 45 -SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 -SDMA_PERFMON_SEL_DUMMY_0 = 49 -SDMA_PERFMON_SEL_DUMMY_1 = 50 -SDMA_PERFMON_SEL_CE_INFO_FULL = 51 -SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 -SDMA_PERFMON_SEL_CE_RD_STALL = 53 -SDMA_PERFMON_SEL_CE_WR_STALL = 54 -SDMA_PERFMON_SEL_QUEUE0_SELECT = 55 -SDMA_PERFMON_SEL_QUEUE1_SELECT = 56 -SDMA_PERFMON_SEL_QUEUE2_SELECT = 57 -SDMA_PERFMON_SEL_QUEUE3_SELECT = 58 -SDMA_PERFMON_SEL_CTX_CHANGE = 59 -SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 -SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 -SDMA_PERFMON_SEL_DOORBELL = 62 -SDMA_PERFMON_SEL_MCU_L1_WR_VLD = 63 -SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 -SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 -SDMA_PERFMON_SEL_UTCL2_FREE = 73 -SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 -SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 -SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 -SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 -SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 -SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 -SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 -SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERFMON_SEL_META_REQ_SEND = 93 -SDMA_PERFMON_SEL_META_RTN_VLD = 94 -SDMA_PERFMON_SEL_TLBI_SEND = 95 -SDMA_PERFMON_SEL_TLBI_RTN = 96 -SDMA_PERFMON_SEL_GCR_SEND = 97 -SDMA_PERFMON_SEL_GCR_RTN = 98 -SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 -SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 -SDMA_PERFMON_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERF_SEL' -SDMA_PERF_SEL__enumvalues = { - 0: 'SDMA_PERF_SEL_CYCLE', - 1: 'SDMA_PERF_SEL_IDLE', - 2: 'SDMA_PERF_SEL_REG_IDLE', - 3: 'SDMA_PERF_SEL_RB_EMPTY', - 4: 'SDMA_PERF_SEL_RB_FULL', - 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERF_SEL_RB_RPTR_WB', - 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERF_SEL_RB_CMD_FULL', - 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERF_SEL_IB_CMD_FULL', - 13: 'SDMA_PERF_SEL_EX_IDLE', - 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERF_SEL_MC_WR_IDLE', - 17: 'SDMA_PERF_SEL_MC_WR_COUNT', - 18: 'SDMA_PERF_SEL_MC_RD_IDLE', - 19: 'SDMA_PERF_SEL_MC_RD_COUNT', - 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'SDMA_PERF_SEL_SEM_IDLE', - 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'SDMA_PERF_SEL_INT_IDLE', - 31: 'SDMA_PERF_SEL_INT_REQ_STALL', - 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'SDMA_PERF_SEL_NUM_PACKET', - 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'SDMA_PERF_SEL_CE_WR_IDLE', - 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'SDMA_PERF_SEL_CE_IN_IDLE', - 43: 'SDMA_PERF_SEL_CE_DST_IDLE', - 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 47: 'SDMA_PERF_SEL_DUMMY_0', - 48: 'SDMA_PERF_SEL_DUMMY_1', - 49: 'SDMA_PERF_SEL_CE_INFO_FULL', - 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'SDMA_PERF_SEL_CE_RD_STALL', - 52: 'SDMA_PERF_SEL_CE_WR_STALL', - 53: 'SDMA_PERF_SEL_QUEUE0_SELECT', - 54: 'SDMA_PERF_SEL_QUEUE1_SELECT', - 55: 'SDMA_PERF_SEL_QUEUE2_SELECT', - 56: 'SDMA_PERF_SEL_QUEUE3_SELECT', - 57: 'SDMA_PERF_SEL_CTX_CHANGE', - 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'SDMA_PERF_SEL_DOORBELL', - 61: 'SDMA_PERF_SEL_RD_BA_RTR', - 62: 'SDMA_PERF_SEL_WR_BA_RTR', - 63: 'SDMA_PERF_SEL_MCU_L1_WR_VLD', - 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERF_SEL_UTCL2_FREE', - 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERF_SEL_META_REQ_SEND', - 94: 'SDMA_PERF_SEL_META_RTN_VLD', - 95: 'SDMA_PERF_SEL_TLBI_SEND', - 96: 'SDMA_PERF_SEL_TLBI_RTN', - 97: 'SDMA_PERF_SEL_GCR_SEND', - 98: 'SDMA_PERF_SEL_GCR_RTN', - 99: 'SDMA_PERF_SEL_CGCG_FENCE', - 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', - 102: 'SDMA_PERF_SEL_MCU_CH_WR_REQ', - 103: 'SDMA_PERF_SEL_MCU_CH_WR_RET', - 104: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ', - 105: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET', - 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', - 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', - 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', - 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', - 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', - 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', - 115: 'SDMA_PERF_SEL_CMD_OP_START', - 116: 'SDMA_PERF_SEL_CMD_OP_END', - 117: 'SDMA_PERF_SEL_CE_BUSY', - 118: 'SDMA_PERF_SEL_CE_BUSY_START', - 119: 'SDMA_PERF_SEL_CE_BUSY_END', - 120: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER', - 121: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START', - 122: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END', - 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', - 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', - 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', - 127: 'SDMA_PERF_SEL_QUEUE4_SELECT', - 128: 'SDMA_PERF_SEL_QUEUE5_SELECT', - 129: 'SDMA_PERF_SEL_QUEUE6_SELECT', - 130: 'SDMA_PERF_SEL_QUEUE7_SELECT', -} -SDMA_PERF_SEL_CYCLE = 0 -SDMA_PERF_SEL_IDLE = 1 -SDMA_PERF_SEL_REG_IDLE = 2 -SDMA_PERF_SEL_RB_EMPTY = 3 -SDMA_PERF_SEL_RB_FULL = 4 -SDMA_PERF_SEL_RB_WPTR_WRAP = 5 -SDMA_PERF_SEL_RB_RPTR_WRAP = 6 -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERF_SEL_RB_RPTR_WB = 8 -SDMA_PERF_SEL_RB_CMD_IDLE = 9 -SDMA_PERF_SEL_RB_CMD_FULL = 10 -SDMA_PERF_SEL_IB_CMD_IDLE = 11 -SDMA_PERF_SEL_IB_CMD_FULL = 12 -SDMA_PERF_SEL_EX_IDLE = 13 -SDMA_PERF_SEL_SRBM_REG_SEND = 14 -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERF_SEL_MC_WR_IDLE = 16 -SDMA_PERF_SEL_MC_WR_COUNT = 17 -SDMA_PERF_SEL_MC_RD_IDLE = 18 -SDMA_PERF_SEL_MC_RD_COUNT = 19 -SDMA_PERF_SEL_MC_RD_RET_STALL = 20 -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -SDMA_PERF_SEL_SEM_IDLE = 24 -SDMA_PERF_SEL_SEM_REQ_STALL = 25 -SDMA_PERF_SEL_SEM_REQ_COUNT = 26 -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -SDMA_PERF_SEL_SEM_RESP_FAIL = 28 -SDMA_PERF_SEL_SEM_RESP_PASS = 29 -SDMA_PERF_SEL_INT_IDLE = 30 -SDMA_PERF_SEL_INT_REQ_STALL = 31 -SDMA_PERF_SEL_INT_REQ_COUNT = 32 -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -SDMA_PERF_SEL_INT_RESP_RETRY = 34 -SDMA_PERF_SEL_NUM_PACKET = 35 -SDMA_PERF_SEL_CE_WREQ_IDLE = 37 -SDMA_PERF_SEL_CE_WR_IDLE = 38 -SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -SDMA_PERF_SEL_CE_RREQ_IDLE = 40 -SDMA_PERF_SEL_CE_OUT_IDLE = 41 -SDMA_PERF_SEL_CE_IN_IDLE = 42 -SDMA_PERF_SEL_CE_DST_IDLE = 43 -SDMA_PERF_SEL_CE_AFIFO_FULL = 46 -SDMA_PERF_SEL_DUMMY_0 = 47 -SDMA_PERF_SEL_DUMMY_1 = 48 -SDMA_PERF_SEL_CE_INFO_FULL = 49 -SDMA_PERF_SEL_CE_INFO1_FULL = 50 -SDMA_PERF_SEL_CE_RD_STALL = 51 -SDMA_PERF_SEL_CE_WR_STALL = 52 -SDMA_PERF_SEL_QUEUE0_SELECT = 53 -SDMA_PERF_SEL_QUEUE1_SELECT = 54 -SDMA_PERF_SEL_QUEUE2_SELECT = 55 -SDMA_PERF_SEL_QUEUE3_SELECT = 56 -SDMA_PERF_SEL_CTX_CHANGE = 57 -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -SDMA_PERF_SEL_DOORBELL = 60 -SDMA_PERF_SEL_RD_BA_RTR = 61 -SDMA_PERF_SEL_WR_BA_RTR = 62 -SDMA_PERF_SEL_MCU_L1_WR_VLD = 63 -SDMA_PERF_SEL_CE_L1_WR_VLD = 64 -SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERF_SEL_UTCL2_RET_ACK = 72 -SDMA_PERF_SEL_UTCL2_FREE = 73 -SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERF_SEL_GPUVM_INV_LOW = 80 -SDMA_PERF_SEL_L1_WRL2_IDLE = 81 -SDMA_PERF_SEL_L1_RDL2_IDLE = 82 -SDMA_PERF_SEL_L1_WRMC_IDLE = 83 -SDMA_PERF_SEL_L1_RDMC_IDLE = 84 -SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERF_SEL_META_L2_REQ_SEND = 87 -SDMA_PERF_SEL_L2_META_RET_VLD = 88 -SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERF_SEL_META_REQ_SEND = 93 -SDMA_PERF_SEL_META_RTN_VLD = 94 -SDMA_PERF_SEL_TLBI_SEND = 95 -SDMA_PERF_SEL_TLBI_RTN = 96 -SDMA_PERF_SEL_GCR_SEND = 97 -SDMA_PERF_SEL_GCR_RTN = 98 -SDMA_PERF_SEL_CGCG_FENCE = 99 -SDMA_PERF_SEL_CE_CH_WR_REQ = 100 -SDMA_PERF_SEL_CE_CH_WR_RET = 101 -SDMA_PERF_SEL_MCU_CH_WR_REQ = 102 -SDMA_PERF_SEL_MCU_CH_WR_RET = 103 -SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ = 104 -SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET = 105 -SDMA_PERF_SEL_RB_CH_RD_REQ = 106 -SDMA_PERF_SEL_RB_CH_RD_RET = 107 -SDMA_PERF_SEL_IB_CH_RD_REQ = 108 -SDMA_PERF_SEL_IB_CH_RD_RET = 109 -SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 -SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 -SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 -SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 -SDMA_PERF_SEL_CMD_OP_MATCH = 114 -SDMA_PERF_SEL_CMD_OP_START = 115 -SDMA_PERF_SEL_CMD_OP_END = 116 -SDMA_PERF_SEL_CE_BUSY = 117 -SDMA_PERF_SEL_CE_BUSY_START = 118 -SDMA_PERF_SEL_CE_BUSY_END = 119 -SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER = 120 -SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START = 121 -SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END = 122 -SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 -SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 -SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 -SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 -SDMA_PERF_SEL_QUEUE4_SELECT = 127 -SDMA_PERF_SEL_QUEUE5_SELECT = 128 -SDMA_PERF_SEL_QUEUE6_SELECT = 129 -SDMA_PERF_SEL_QUEUE7_SELECT = 130 -SDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPM_PERFMON_STATE' -SPM_PERFMON_STATE__enumvalues = { - 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'STRM_PERFMON_STATE_START_COUNTING', - 2: 'STRM_PERFMON_STATE_STOP_COUNTING', - 3: 'STRM_PERFMON_STATE_RESERVED_3', - 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 -STRM_PERFMON_STATE_START_COUNTING = 1 -STRM_PERFMON_STATE_STOP_COUNTING = 2 -STRM_PERFMON_STATE_RESERVED_3 = 3 -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -SPM_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_MTYPE' -TCC_MTYPE__enumvalues = { - 0: 'MTYPE_NC', - 1: 'MTYPE_WC', - 2: 'MTYPE_CC', -} -MTYPE_NC = 0 -MTYPE_WC = 1 -MTYPE_CC = 2 -TCC_MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0FaultType' -UTCL0FaultType__enumvalues = { - 0: 'UTCL0_XNACK_SUCCESS', - 1: 'UTCL0_XNACK_RETRY', - 2: 'UTCL0_XNACK_PRT', - 3: 'UTCL0_XNACK_NO_RETRY', -} -UTCL0_XNACK_SUCCESS = 0 -UTCL0_XNACK_RETRY = 1 -UTCL0_XNACK_PRT = 2 -UTCL0_XNACK_NO_RETRY = 3 -UTCL0FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0RequestType' -UTCL0RequestType__enumvalues = { - 0: 'UTCL0_TYPE_NORMAL', - 1: 'UTCL0_TYPE_SHOOTDOWN', - 2: 'UTCL0_TYPE_BYPASS', -} -UTCL0_TYPE_NORMAL = 0 -UTCL0_TYPE_SHOOTDOWN = 1 -UTCL0_TYPE_BYPASS = 2 -UTCL0RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1FaultType' -UTCL1FaultType__enumvalues = { - 0: 'UTCL1_XNACK_SUCCESS', - 1: 'UTCL1_XNACK_RETRY', - 2: 'UTCL1_XNACK_PRT', - 3: 'UTCL1_XNACK_NO_RETRY', -} -UTCL1_XNACK_SUCCESS = 0 -UTCL1_XNACK_RETRY = 1 -UTCL1_XNACK_PRT = 2 -UTCL1_XNACK_NO_RETRY = 3 -UTCL1FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1RequestType' -UTCL1RequestType__enumvalues = { - 0: 'UTCL1_TYPE_NORMAL', - 1: 'UTCL1_TYPE_SHOOTDOWN', - 2: 'UTCL1_TYPE_BYPASS', -} -UTCL1_TYPE_NORMAL = 0 -UTCL1_TYPE_SHOOTDOWN = 1 -UTCL1_TYPE_BYPASS = 2 -UTCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_COMPRESSION_MODE' -WRITE_COMPRESSION_MODE__enumvalues = { - 0: 'COMPRESSION_MODE_BYPASS_METADATA_CACHE', - 1: 'COMPRESSION_MODE_COMPRESSION_ENABLED', - 2: 'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED', -} -COMPRESSION_MODE_BYPASS_METADATA_CACHE = 0 -COMPRESSION_MODE_COMPRESSION_ENABLED = 1 -COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 2 -WRITE_COMPRESSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'WritePolicy' -WritePolicy__enumvalues = { - 0: 'CACHE_LRU_WR', - 1: 'CACHE_STREAM', - 2: 'CACHE_NOA_WR', - 3: 'CACHE_BYPASS', -} -CACHE_LRU_WR = 0 -CACHE_STREAM = 1 -CACHE_NOA_WR = 2 -CACHE_BYPASS = 3 -WritePolicy = ctypes.c_uint32 # enum - -# values for enumeration 'COLOR_KEYER_ENABLE' -COLOR_KEYER_ENABLE__enumvalues = { - 0: 'COLOR_KEY_EN', - 1: 'COLOR_KEY_DIS', -} -COLOR_KEY_EN = 0 -COLOR_KEY_DIS = 1 -COLOR_KEYER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'COLOR_KEYER_MODE' -COLOR_KEYER_MODE__enumvalues = { - 0: 'FORCE_00', - 1: 'FORCE_FF', - 2: 'RANGE_00', - 3: 'RANGE_FF', -} -FORCE_00 = 0 -FORCE_FF = 1 -RANGE_00 = 2 -RANGE_FF = 3 -COLOR_KEYER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DENORM_TRUNCATE' -DENORM_TRUNCATE__enumvalues = { - 0: 'CNVC_ROUND', - 1: 'CNVC_TRUNCATE', -} -CNVC_ROUND = 0 -CNVC_TRUNCATE = 1 -DENORM_TRUNCATE = ctypes.c_uint32 # enum - -# values for enumeration 'FORMAT_CROSSBAR' -FORMAT_CROSSBAR__enumvalues = { - 0: 'FORMAT_CROSSBAR_R', - 1: 'FORMAT_CROSSBAR_G', - 2: 'FORMAT_CROSSBAR_B', -} -FORMAT_CROSSBAR_R = 0 -FORMAT_CROSSBAR_G = 1 -FORMAT_CROSSBAR_B = 2 -FORMAT_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'LUMA_KEYER_ENABLE' -LUMA_KEYER_ENABLE__enumvalues = { - 0: 'LUMA_KEY_EN', - 1: 'LUMA_KEY_DIS', -} -LUMA_KEY_EN = 0 -LUMA_KEY_DIS = 1 -LUMA_KEYER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'PIX_EXPAND_MODE' -PIX_EXPAND_MODE__enumvalues = { - 0: 'PIX_DYNAMIC_EXPANSION', - 1: 'PIX_ZERO_EXPANSION', -} -PIX_DYNAMIC_EXPANSION = 0 -PIX_ZERO_EXPANSION = 1 -PIX_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_CSC_MODE_ENUM' -PRE_CSC_MODE_ENUM__enumvalues = { - 0: 'PRE_CSC_BYPASS', - 1: 'PRE_CSC_SET_A', - 2: 'PRE_CSC_SET_B', -} -PRE_CSC_BYPASS = 0 -PRE_CSC_SET_A = 1 -PRE_CSC_SET_B = 2 -PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_MODE' -PRE_DEGAM_MODE__enumvalues = { - 0: 'PRE_DEGAM_BYPASS', - 1: 'PRE_DEGAM_ENABLE', -} -PRE_DEGAM_BYPASS = 0 -PRE_DEGAM_ENABLE = 1 -PRE_DEGAM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_SELECT' -PRE_DEGAM_SELECT__enumvalues = { - 0: 'PRE_DEGAM_SRGB', - 1: 'PRE_DEGAM_GAMMA_22', - 2: 'PRE_DEGAM_GAMMA_24', - 3: 'PRE_DEGAM_GAMMA_26', - 4: 'PRE_DEGAM_BT2020', - 5: 'PRE_DEGAM_BT2100PQ', - 6: 'PRE_DEGAM_BT2100HLG', -} -PRE_DEGAM_SRGB = 0 -PRE_DEGAM_GAMMA_22 = 1 -PRE_DEGAM_GAMMA_24 = 2 -PRE_DEGAM_GAMMA_26 = 3 -PRE_DEGAM_BT2020 = 4 -PRE_DEGAM_BT2100PQ = 5 -PRE_DEGAM_BT2100HLG = 6 -PRE_DEGAM_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_PIXEL_FORMAT' -SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'ARGB1555', - 2: 'RGBA5551', - 3: 'RGB565', - 4: 'BGR565', - 5: 'ARGB4444', - 6: 'RGBA4444', - 8: 'ARGB8888', - 9: 'RGBA8888', - 10: 'ARGB2101010', - 11: 'RGBA1010102', - 12: 'AYCrCb8888', - 13: 'YCrCbA8888', - 14: 'ACrYCb8888', - 15: 'CrYCbA8888', - 16: 'ARGB16161616_10MSB', - 17: 'RGBA16161616_10MSB', - 18: 'ARGB16161616_10LSB', - 19: 'RGBA16161616_10LSB', - 20: 'ARGB16161616_12MSB', - 21: 'RGBA16161616_12MSB', - 22: 'ARGB16161616_12LSB', - 23: 'RGBA16161616_12LSB', - 24: 'ARGB16161616_FLOAT', - 25: 'RGBA16161616_FLOAT', - 26: 'ARGB16161616_UNORM', - 27: 'RGBA16161616_UNORM', - 28: 'ARGB16161616_SNORM', - 29: 'RGBA16161616_SNORM', - 32: 'AYCrCb16161616_10MSB', - 33: 'AYCrCb16161616_10LSB', - 34: 'YCrCbA16161616_10MSB', - 35: 'YCrCbA16161616_10LSB', - 36: 'ACrYCb16161616_10MSB', - 37: 'ACrYCb16161616_10LSB', - 38: 'CrYCbA16161616_10MSB', - 39: 'CrYCbA16161616_10LSB', - 40: 'AYCrCb16161616_12MSB', - 41: 'AYCrCb16161616_12LSB', - 42: 'YCrCbA16161616_12MSB', - 43: 'YCrCbA16161616_12LSB', - 44: 'ACrYCb16161616_12MSB', - 45: 'ACrYCb16161616_12LSB', - 46: 'CrYCbA16161616_12MSB', - 47: 'CrYCbA16161616_12LSB', - 64: 'Y8_CrCb88_420_PLANAR', - 65: 'Y8_CbCr88_420_PLANAR', - 66: 'Y10_CrCb1010_420_PLANAR', - 67: 'Y10_CbCr1010_420_PLANAR', - 68: 'Y12_CrCb1212_420_PLANAR', - 69: 'Y12_CbCr1212_420_PLANAR', - 72: 'YCrYCb8888_422_PACKED', - 73: 'YCbYCr8888_422_PACKED', - 74: 'CrYCbY8888_422_PACKED', - 75: 'CbYCrY8888_422_PACKED', - 76: 'YCrYCb10101010_422_PACKED', - 77: 'YCbYCr10101010_422_PACKED', - 78: 'CrYCbY10101010_422_PACKED', - 79: 'CbYCrY10101010_422_PACKED', - 80: 'YCrYCb12121212_422_PACKED', - 81: 'YCbYCr12121212_422_PACKED', - 82: 'CrYCbY12121212_422_PACKED', - 83: 'CbYCrY12121212_422_PACKED', - 112: 'RGB111110_FIX', - 113: 'BGR101111_FIX', - 114: 'ACrYCb2101010', - 115: 'CrYCbA1010102', - 116: 'RGBE', - 118: 'RGB111110_FLOAT', - 119: 'BGR101111_FLOAT', - 120: 'MONO_8', - 121: 'MONO_10MSB', - 122: 'MONO_10LSB', - 123: 'MONO_12MSB', - 124: 'MONO_12LSB', - 125: 'MONO_16', -} -ARGB1555 = 1 -RGBA5551 = 2 -RGB565 = 3 -BGR565 = 4 -ARGB4444 = 5 -RGBA4444 = 6 -ARGB8888 = 8 -RGBA8888 = 9 -ARGB2101010 = 10 -RGBA1010102 = 11 -AYCrCb8888 = 12 -YCrCbA8888 = 13 -ACrYCb8888 = 14 -CrYCbA8888 = 15 -ARGB16161616_10MSB = 16 -RGBA16161616_10MSB = 17 -ARGB16161616_10LSB = 18 -RGBA16161616_10LSB = 19 -ARGB16161616_12MSB = 20 -RGBA16161616_12MSB = 21 -ARGB16161616_12LSB = 22 -RGBA16161616_12LSB = 23 -ARGB16161616_FLOAT = 24 -RGBA16161616_FLOAT = 25 -ARGB16161616_UNORM = 26 -RGBA16161616_UNORM = 27 -ARGB16161616_SNORM = 28 -RGBA16161616_SNORM = 29 -AYCrCb16161616_10MSB = 32 -AYCrCb16161616_10LSB = 33 -YCrCbA16161616_10MSB = 34 -YCrCbA16161616_10LSB = 35 -ACrYCb16161616_10MSB = 36 -ACrYCb16161616_10LSB = 37 -CrYCbA16161616_10MSB = 38 -CrYCbA16161616_10LSB = 39 -AYCrCb16161616_12MSB = 40 -AYCrCb16161616_12LSB = 41 -YCrCbA16161616_12MSB = 42 -YCrCbA16161616_12LSB = 43 -ACrYCb16161616_12MSB = 44 -ACrYCb16161616_12LSB = 45 -CrYCbA16161616_12MSB = 46 -CrYCbA16161616_12LSB = 47 -Y8_CrCb88_420_PLANAR = 64 -Y8_CbCr88_420_PLANAR = 65 -Y10_CrCb1010_420_PLANAR = 66 -Y10_CbCr1010_420_PLANAR = 67 -Y12_CrCb1212_420_PLANAR = 68 -Y12_CbCr1212_420_PLANAR = 69 -YCrYCb8888_422_PACKED = 72 -YCbYCr8888_422_PACKED = 73 -CrYCbY8888_422_PACKED = 74 -CbYCrY8888_422_PACKED = 75 -YCrYCb10101010_422_PACKED = 76 -YCbYCr10101010_422_PACKED = 77 -CrYCbY10101010_422_PACKED = 78 -CbYCrY10101010_422_PACKED = 79 -YCrYCb12121212_422_PACKED = 80 -YCbYCr12121212_422_PACKED = 81 -CrYCbY12121212_422_PACKED = 82 -CbYCrY12121212_422_PACKED = 83 -RGB111110_FIX = 112 -BGR101111_FIX = 113 -ACrYCb2101010 = 114 -CrYCbA1010102 = 115 -RGBE = 116 -RGB111110_FLOAT = 118 -BGR101111_FLOAT = 119 -MONO_8 = 120 -MONO_10MSB = 121 -MONO_10LSB = 122 -MONO_12MSB = 123 -MONO_12LSB = 124 -MONO_16 = 125 -SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'XNORM' -XNORM__enumvalues = { - 0: 'XNORM_A', - 1: 'XNORM_B', -} -XNORM_A = 0 -XNORM_B = 1 -XNORM = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ENABLE' -CUR_ENABLE__enumvalues = { - 0: 'CUR_DIS', - 1: 'CUR_EN', -} -CUR_DIS = 0 -CUR_EN = 1 -CUR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_EXPAND_MODE' -CUR_EXPAND_MODE__enumvalues = { - 0: 'CUR_DYNAMIC_EXPANSION', - 1: 'CUR_ZERO_EXPANSION', -} -CUR_DYNAMIC_EXPANSION = 0 -CUR_ZERO_EXPANSION = 1 -CUR_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_INV_CLAMP' -CUR_INV_CLAMP__enumvalues = { - 0: 'CUR_CLAMP_DIS', - 1: 'CUR_CLAMP_EN', -} -CUR_CLAMP_DIS = 0 -CUR_CLAMP_EN = 1 -CUR_INV_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_MATRIX_COEF_FORMAT_ENUM' -CUR_MATRIX_COEF_FORMAT_ENUM__enumvalues = { - 0: 'CUR_MATRIX_FIX_S2_13', - 1: 'CUR_MATRIX_FIX_S3_12', -} -CUR_MATRIX_FIX_S2_13 = 0 -CUR_MATRIX_FIX_S3_12 = 1 -CUR_MATRIX_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_MODE' -CUR_MODE__enumvalues = { - 0: 'MONO_2BIT', - 1: 'COLOR_24BIT_1BIT_AND', - 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'COLOR_64BIT_FP_PREMULT', - 5: 'COLOR_64BIT_FP_UNPREMULT', -} -MONO_2BIT = 0 -COLOR_24BIT_1BIT_AND = 1 -COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -COLOR_64BIT_FP_PREMULT = 4 -COLOR_64BIT_FP_UNPREMULT = 5 -CUR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_PENDING' -CUR_PENDING__enumvalues = { - 0: 'CUR_NOT_PENDING', - 1: 'CUR_YES_PENDING', -} -CUR_NOT_PENDING = 0 -CUR_YES_PENDING = 1 -CUR_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ROM_EN' -CUR_ROM_EN__enumvalues = { - 0: 'CUR_FP_NO_ROM', - 1: 'CUR_FP_USE_ROM', -} -CUR_FP_NO_ROM = 0 -CUR_FP_USE_ROM = 1 -CUR_ROM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'COEF_RAM_SELECT_RD' -COEF_RAM_SELECT_RD__enumvalues = { - 0: 'COEF_RAM_SELECT_BACK', - 1: 'COEF_RAM_SELECT_CURRENT', -} -COEF_RAM_SELECT_BACK = 0 -COEF_RAM_SELECT_CURRENT = 1 -COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum - -# values for enumeration 'DSCL_MODE_SEL' -DSCL_MODE_SEL__enumvalues = { - 0: 'DSCL_MODE_SCALING_444_BYPASS', - 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', - 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', - 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', - 6: 'DSCL_MODE_DSCL_BYPASS', -} -DSCL_MODE_SCALING_444_BYPASS = 0 -DSCL_MODE_SCALING_444_RGB_ENABLE = 1 -DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 -DSCL_MODE_SCALING_YCBCR_ENABLE = 3 -DSCL_MODE_LUMA_SCALING_BYPASS = 4 -DSCL_MODE_CHROMA_SCALING_BYPASS = 5 -DSCL_MODE_DSCL_BYPASS = 6 -DSCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ISHARP_FMT_MODE_ENUM' -ISHARP_FMT_MODE_ENUM__enumvalues = { - 0: 'ISHARP_FMT_MODE_0', - 1: 'ISHARP_FMT_MODE_1', -} -ISHARP_FMT_MODE_0 = 0 -ISHARP_FMT_MODE_1 = 1 -ISHARP_FMT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ISHARP_LBA_MODE_ENUM' -ISHARP_LBA_MODE_ENUM__enumvalues = { - 0: 'ISHARP_LBA_MODE_0', - 1: 'ISHARP_LBA_MODE_1', -} -ISHARP_LBA_MODE_0 = 0 -ISHARP_LBA_MODE_1 = 1 -ISHARP_LBA_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ISHARP_NOISEDET_MODE_ENUM' -ISHARP_NOISEDET_MODE_ENUM__enumvalues = { - 0: 'ISHARP_NOISEDET_MODE_0', - 1: 'ISHARP_NOISEDET_MODE_1', - 2: 'ISHARP_NOISEDET_MODE_2', - 3: 'ISHARP_NOISEDET_MODE_3', -} -ISHARP_NOISEDET_MODE_0 = 0 -ISHARP_NOISEDET_MODE_1 = 1 -ISHARP_NOISEDET_MODE_2 = 2 -ISHARP_NOISEDET_MODE_3 = 3 -ISHARP_NOISEDET_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'LB_ALPHA_EN' -LB_ALPHA_EN__enumvalues = { - 0: 'LB_ALPHA_DISABLE', - 1: 'LB_ALPHA_ENABLE', -} -LB_ALPHA_DISABLE = 0 -LB_ALPHA_ENABLE = 1 -LB_ALPHA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERLEAVE_EN' -LB_INTERLEAVE_EN__enumvalues = { - 0: 'LB_INTERLEAVE_DISABLE', - 1: 'LB_INTERLEAVE_ENABLE', -} -LB_INTERLEAVE_DISABLE = 0 -LB_INTERLEAVE_ENABLE = 1 -LB_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MEMORY_CONFIG' -LB_MEMORY_CONFIG__enumvalues = { - 0: 'LB_MEMORY_CONFIG_0', - 1: 'LB_MEMORY_CONFIG_1', - 2: 'LB_MEMORY_CONFIG_2', - 3: 'LB_MEMORY_CONFIG_3', -} -LB_MEMORY_CONFIG_0 = 0 -LB_MEMORY_CONFIG_1 = 1 -LB_MEMORY_CONFIG_2 = 2 -LB_MEMORY_CONFIG_3 = 3 -LB_MEMORY_CONFIG = ctypes.c_uint32 # enum - -# values for enumeration 'MATRIX_MODE_ENUM' -MATRIX_MODE_ENUM__enumvalues = { - 0: 'MATRIX_MODE_0', - 1: 'MATRIX_MODE_1', -} -MATRIX_MODE_0 = 0 -MATRIX_MODE_1 = 1 -MATRIX_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_BYPASS_SEL' -OBUF_BYPASS_SEL__enumvalues = { - 0: 'OBUF_BYPASS_DIS', - 1: 'OBUF_BYPASS_EN', -} -OBUF_BYPASS_DIS = 0 -OBUF_BYPASS_EN = 1 -OBUF_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' -OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { - 0: 'OBUF_FULL_RECOUT', - 1: 'OBUF_HALF_RECOUT', -} -OBUF_FULL_RECOUT = 0 -OBUF_HALF_RECOUT = 1 -OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' -OBUF_USE_FULL_BUFFER_SEL__enumvalues = { - 0: 'OBUF_RECOUT', - 1: 'OBUF_FULL', -} -OBUF_RECOUT = 0 -OBUF_FULL = 1 -OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_2TAP_HARDCODE' -SCL_2TAP_HARDCODE__enumvalues = { - 0: 'SCL_COEF_2TAP_HARDCODE_OFF', - 1: 'SCL_COEF_2TAP_HARDCODE_ON', -} -SCL_COEF_2TAP_HARDCODE_OFF = 0 -SCL_COEF_2TAP_HARDCODE_ON = 1 -SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_ALPHA_COEF' -SCL_ALPHA_COEF__enumvalues = { - 0: 'SCL_ALPHA_COEF_FIRST', - 1: 'SCL_ALPHA_COEF_SECOND', -} -SCL_ALPHA_COEF_FIRST = 0 -SCL_ALPHA_COEF_SECOND = 1 -SCL_ALPHA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_AUTOCAL_MODE' -SCL_AUTOCAL_MODE__enumvalues = { - 0: 'AUTOCAL_MODE_OFF', - 1: 'AUTOCAL_MODE_AUTOSCALE', - 2: 'AUTOCAL_MODE_AUTOCENTER', - 3: 'AUTOCAL_MODE_AUTOREPLICATE', -} -AUTOCAL_MODE_OFF = 0 -AUTOCAL_MODE_AUTOSCALE = 1 -AUTOCAL_MODE_AUTOCENTER = 2 -AUTOCAL_MODE_AUTOREPLICATE = 3 -SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BOUNDARY' -SCL_BOUNDARY__enumvalues = { - 0: 'SCL_BOUNDARY_EDGE', - 1: 'SCL_BOUNDARY_BLACK', -} -SCL_BOUNDARY_EDGE = 0 -SCL_BOUNDARY_BLACK = 1 -SCL_BOUNDARY = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_CHROMA_COEF' -SCL_CHROMA_COEF__enumvalues = { - 0: 'SCL_CHROMA_COEF_FIRST', - 1: 'SCL_CHROMA_COEF_SECOND', -} -SCL_CHROMA_COEF_FIRST = 0 -SCL_CHROMA_COEF_SECOND = 1 -SCL_CHROMA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' -SCL_COEF_FILTER_TYPE_SEL__enumvalues = { - 0: 'SCL_COEF_LUMA_VERT_FILTER', - 1: 'SCL_COEF_LUMA_HORZ_FILTER', - 2: 'SCL_COEF_CHROMA_VERT_FILTER', - 3: 'SCL_COEF_CHROMA_HORZ_FILTER', - 4: 'SCL_COEF_SC_VERT_FILTER', - 5: 'SCL_COEF_SC_HORZ_FILTER', -} -SCL_COEF_LUMA_VERT_FILTER = 0 -SCL_COEF_LUMA_HORZ_FILTER = 1 -SCL_COEF_CHROMA_VERT_FILTER = 2 -SCL_COEF_CHROMA_HORZ_FILTER = 3 -SCL_COEF_SC_VERT_FILTER = 4 -SCL_COEF_SC_HORZ_FILTER = 5 -SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_RAM_SEL' -SCL_COEF_RAM_SEL__enumvalues = { - 0: 'SCL_COEF_RAM_SEL_0', - 1: 'SCL_COEF_RAM_SEL_1', -} -SCL_COEF_RAM_SEL_0 = 0 -SCL_COEF_RAM_SEL_1 = 1 -SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_SHARP_EN' -SCL_SHARP_EN__enumvalues = { - 0: 'SCL_SHARP_DISABLE', - 1: 'SCL_SHARP_ENABLE', -} -SCL_SHARP_DISABLE = 0 -SCL_SHARP_ENABLE = 1 -SCL_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_30BIT_ENUM' -CMC_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'CMC_3DLUT_36BIT', - 1: 'CMC_3DLUT_30BIT', -} -CMC_3DLUT_36BIT = 0 -CMC_3DLUT_30BIT = 1 -CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_RAM_SEL' -CMC_3DLUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAM0_ACCESS', - 1: 'CMC_RAM1_ACCESS', - 2: 'CMC_RAM2_ACCESS', - 3: 'CMC_RAM3_ACCESS', -} -CMC_RAM0_ACCESS = 0 -CMC_RAM1_ACCESS = 1 -CMC_RAM2_ACCESS = 2 -CMC_RAM3_ACCESS = 3 -CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_SIZE_ENUM' -CMC_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'CMC_3DLUT_17CUBE', - 1: 'CMC_3DLUT_9CUBE', -} -CMC_3DLUT_17CUBE = 0 -CMC_3DLUT_9CUBE = 1 -CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' -CMC_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'CMC_LUT_2CFG_NO_MEMORY', - 1: 'CMC_LUT_2CFG_MEMORY_A', - 2: 'CMC_LUT_2CFG_MEMORY_B', -} -CMC_LUT_2CFG_NO_MEMORY = 0 -CMC_LUT_2CFG_MEMORY_A = 1 -CMC_LUT_2CFG_MEMORY_B = 2 -CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_MODE_ENUM' -CMC_LUT_2_MODE_ENUM__enumvalues = { - 0: 'CMC_LUT_2_MODE_BYPASS', - 1: 'CMC_LUT_2_MODE_RAMA_LUT', - 2: 'CMC_LUT_2_MODE_RAMB_LUT', -} -CMC_LUT_2_MODE_BYPASS = 0 -CMC_LUT_2_MODE_RAMA_LUT = 1 -CMC_LUT_2_MODE_RAMB_LUT = 2 -CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_NUM_SEG' -CMC_LUT_NUM_SEG__enumvalues = { - 0: 'CMC_SEGMENTS_1', - 1: 'CMC_SEGMENTS_2', - 2: 'CMC_SEGMENTS_4', - 3: 'CMC_SEGMENTS_8', - 4: 'CMC_SEGMENTS_16', - 5: 'CMC_SEGMENTS_32', - 6: 'CMC_SEGMENTS_64', - 7: 'CMC_SEGMENTS_128', -} -CMC_SEGMENTS_1 = 0 -CMC_SEGMENTS_2 = 1 -CMC_SEGMENTS_4 = 2 -CMC_SEGMENTS_8 = 3 -CMC_SEGMENTS_16 = 4 -CMC_SEGMENTS_32 = 5 -CMC_SEGMENTS_64 = 6 -CMC_SEGMENTS_128 = 7 -CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_RAM_SEL' -CMC_LUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAMA_ACCESS', - 1: 'CMC_RAMB_ACCESS', -} -CMC_RAMA_ACCESS = 0 -CMC_RAMB_ACCESS = 1 -CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_BYPASS' -CM_BYPASS__enumvalues = { - 0: 'NON_BYPASS', - 1: 'BYPASS_EN', -} -NON_BYPASS = 0 -BYPASS_EN = 1 -CM_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CM_COEF_FORMAT_ENUM' -CM_COEF_FORMAT_ENUM__enumvalues = { - 0: 'FIX_S2_13', - 1: 'FIX_S3_12', -} -FIX_S2_13 = 0 -FIX_S3_12 = 1 -CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_DATA_SIGNED' -CM_DATA_SIGNED__enumvalues = { - 0: 'UNSIGNED', - 1: 'SIGNED', -} -UNSIGNED = 0 -SIGNED = 1 -CM_DATA_SIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'CM_EN' -CM_EN__enumvalues = { - 0: 'CM_DISABLE', - 1: 'CM_ENABLE', -} -CM_DISABLE = 0 -CM_ENABLE = 1 -CM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' -CM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'BYPASS', - 1: 'RESERVED_1', - 2: 'RAM_LUT', - 3: 'RESERVED_3', -} -BYPASS = 0 -RESERVED_1 = 1 -RAM_LUT = 2 -RESERVED_3 = 3 -CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' -CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'ENABLE_PWL', - 1: 'DISABLE_PWL', -} -ENABLE_PWL = 0 -DISABLE_PWL = 1 -CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' -CM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'RAMA', - 1: 'RAMB', -} -RAMA = 0 -RAMB = 1 -CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_CONFIG_ENUM' -CM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'LUT_2CFG_NO_MEMORY', - 1: 'LUT_2CFG_MEMORY_A', - 2: 'LUT_2CFG_MEMORY_B', -} -LUT_2CFG_NO_MEMORY = 0 -LUT_2CFG_MEMORY_A = 1 -LUT_2CFG_MEMORY_B = 2 -CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_MODE_ENUM' -CM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'LUT_2_MODE_BYPASS', - 1: 'LUT_2_MODE_RAMA_LUT', - 2: 'LUT_2_MODE_RAMB_LUT', -} -LUT_2_MODE_BYPASS = 0 -LUT_2_MODE_RAMA_LUT = 1 -LUT_2_MODE_RAMB_LUT = 2 -CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_CONFIG_ENUM' -CM_LUT_4_CONFIG_ENUM__enumvalues = { - 0: 'LUT_4CFG_NO_MEMORY', - 1: 'LUT_4CFG_ROM_A', - 2: 'LUT_4CFG_ROM_B', - 3: 'LUT_4CFG_MEMORY_A', - 4: 'LUT_4CFG_MEMORY_B', -} -LUT_4CFG_NO_MEMORY = 0 -LUT_4CFG_ROM_A = 1 -LUT_4CFG_ROM_B = 2 -LUT_4CFG_MEMORY_A = 3 -LUT_4CFG_MEMORY_B = 4 -CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_MODE_ENUM' -CM_LUT_4_MODE_ENUM__enumvalues = { - 0: 'LUT_4_MODE_BYPASS', - 1: 'LUT_4_MODE_ROMA_LUT', - 2: 'LUT_4_MODE_ROMB_LUT', - 3: 'LUT_4_MODE_RAMA_LUT', - 4: 'LUT_4_MODE_RAMB_LUT', -} -LUT_4_MODE_BYPASS = 0 -LUT_4_MODE_ROMA_LUT = 1 -LUT_4_MODE_ROMB_LUT = 2 -LUT_4_MODE_RAMA_LUT = 3 -LUT_4_MODE_RAMB_LUT = 4 -CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_CONFIG_MODE' -CM_LUT_CONFIG_MODE__enumvalues = { - 0: 'DIFFERENT_RGB', - 1: 'ALL_USE_R', -} -DIFFERENT_RGB = 0 -ALL_USE_R = 1 -CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_NUM_SEG' -CM_LUT_NUM_SEG__enumvalues = { - 0: 'SEGMENTS_1', - 1: 'SEGMENTS_2', - 2: 'SEGMENTS_4', - 3: 'SEGMENTS_8', - 4: 'SEGMENTS_16', - 5: 'SEGMENTS_32', - 6: 'SEGMENTS_64', - 7: 'SEGMENTS_128', -} -SEGMENTS_1 = 0 -SEGMENTS_2 = 1 -SEGMENTS_4 = 2 -SEGMENTS_8 = 3 -SEGMENTS_16 = 4 -SEGMENTS_32 = 5 -SEGMENTS_64 = 6 -SEGMENTS_128 = 7 -CM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_RAM_SEL' -CM_LUT_RAM_SEL__enumvalues = { - 0: 'RAMA_ACCESS', - 1: 'RAMB_ACCESS', -} -RAMA_ACCESS = 0 -RAMB_ACCESS = 1 -CM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_COLOR_SEL' -CM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'BLUE_LUT', - 1: 'GREEN_LUT', - 2: 'RED_LUT', -} -BLUE_LUT = 0 -GREEN_LUT = 1 -RED_LUT = 2 -CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_DBG' -CM_LUT_READ_DBG__enumvalues = { - 0: 'DISABLE_DEBUG', - 1: 'ENABLE_DEBUG', -} -DISABLE_DEBUG = 0 -ENABLE_DEBUG = 1 -CM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_PENDING' -CM_PENDING__enumvalues = { - 0: 'CM_NOT_PENDING', - 1: 'CM_YES_PENDING', -} -CM_NOT_PENDING = 0 -CM_YES_PENDING = 1 -CM_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CM_POST_CSC_MODE_ENUM' -CM_POST_CSC_MODE_ENUM__enumvalues = { - 0: 'BYPASS_POST_CSC', - 1: 'COEF_POST_CSC', - 2: 'COEF_POST_CSC_B', -} -BYPASS_POST_CSC = 0 -COEF_POST_CSC = 1 -COEF_POST_CSC_B = 2 -CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_WRITE_BASE_ONLY' -CM_WRITE_BASE_ONLY__enumvalues = { - 0: 'WRITE_BOTH', - 1: 'WRITE_BASE_ONLY', -} -WRITE_BOTH = 0 -WRITE_BASE_ONLY = 1 -CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_CUR_SEL' -CRC_CUR_SEL__enumvalues = { - 0: 'CRC_CUR_0', - 1: 'CRC_CUR_1', -} -CRC_CUR_0 = 0 -CRC_CUR_1 = 1 -CRC_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_INTERLACE_SEL' -CRC_INTERLACE_SEL__enumvalues = { - 0: 'CRC_INTERLACE_0', - 1: 'CRC_INTERLACE_1', - 2: 'CRC_INTERLACE_2', - 3: 'CRC_INTERLACE_3', -} -CRC_INTERLACE_0 = 0 -CRC_INTERLACE_1 = 1 -CRC_INTERLACE_2 = 2 -CRC_INTERLACE_3 = 3 -CRC_INTERLACE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_PIX_SEL' -CRC_IN_PIX_SEL__enumvalues = { - 0: 'CRC_IN_PIX_0', - 1: 'CRC_IN_PIX_1', - 2: 'CRC_IN_PIX_2', - 3: 'CRC_IN_PIX_3', - 4: 'CRC_IN_PIX_4', - 5: 'CRC_IN_PIX_5', - 6: 'CRC_IN_PIX_6', - 7: 'CRC_IN_PIX_7', -} -CRC_IN_PIX_0 = 0 -CRC_IN_PIX_1 = 1 -CRC_IN_PIX_2 = 2 -CRC_IN_PIX_3 = 3 -CRC_IN_PIX_4 = 4 -CRC_IN_PIX_5 = 5 -CRC_IN_PIX_6 = 6 -CRC_IN_PIX_7 = 7 -CRC_IN_PIX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_SRC_SEL' -CRC_SRC_SEL__enumvalues = { - 0: 'CRC_SRC_0', - 1: 'CRC_SRC_1', - 2: 'CRC_SRC_2', - 3: 'CRC_SRC_3', -} -CRC_SRC_0 = 0 -CRC_SRC_1 = 1 -CRC_SRC_2 = 2 -CRC_SRC_3 = 3 -CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_STEREO_SEL' -CRC_STEREO_SEL__enumvalues = { - 0: 'CRC_STEREO_0', - 1: 'CRC_STEREO_1', - 2: 'CRC_STEREO_2', - 3: 'CRC_STEREO_3', -} -CRC_STEREO_0 = 0 -CRC_STEREO_1 = 1 -CRC_STEREO_2 = 2 -CRC_STEREO_3 = 3 -CRC_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_SEL' -TEST_CLK_SEL__enumvalues = { - 0: 'TEST_CLK_SEL_0', - 1: 'TEST_CLK_SEL_1', - 2: 'TEST_CLK_SEL_2', - 3: 'TEST_CLK_SEL_3', - 4: 'TEST_CLK_SEL_4', - 5: 'TEST_CLK_SEL_5', - 6: 'TEST_CLK_SEL_6', - 7: 'TEST_CLK_SEL_7', -} -TEST_CLK_SEL_0 = 0 -TEST_CLK_SEL_1 = 1 -TEST_CLK_SEL_2 = 2 -TEST_CLK_SEL_3 = 3 -TEST_CLK_SEL_4 = 4 -TEST_CLK_SEL_5 = 5 -TEST_CLK_SEL_6 = 6 -TEST_CLK_SEL_7 = 7 -TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_ACTIVE' -PERFCOUNTER_ACTIVE__enumvalues = { - 0: 'PERFCOUNTER_IS_IDLE', - 1: 'PERFCOUNTER_IS_ACTIVE', -} -PERFCOUNTER_IS_IDLE = 0 -PERFCOUNTER_IS_ACTIVE = 1 -PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT0_STATE' -PERFCOUNTER_CNT0_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT0_STATE_RESET', - 1: 'PERFCOUNTER_CNT0_STATE_START', - 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT0_STATE_HW', -} -PERFCOUNTER_CNT0_STATE_RESET = 0 -PERFCOUNTER_CNT0_STATE_START = 1 -PERFCOUNTER_CNT0_STATE_FREEZE = 2 -PERFCOUNTER_CNT0_STATE_HW = 3 -PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT1_STATE' -PERFCOUNTER_CNT1_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT1_STATE_RESET', - 1: 'PERFCOUNTER_CNT1_STATE_START', - 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT1_STATE_HW', -} -PERFCOUNTER_CNT1_STATE_RESET = 0 -PERFCOUNTER_CNT1_STATE_START = 1 -PERFCOUNTER_CNT1_STATE_FREEZE = 2 -PERFCOUNTER_CNT1_STATE_HW = 3 -PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT2_STATE' -PERFCOUNTER_CNT2_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT2_STATE_RESET', - 1: 'PERFCOUNTER_CNT2_STATE_START', - 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT2_STATE_HW', -} -PERFCOUNTER_CNT2_STATE_RESET = 0 -PERFCOUNTER_CNT2_STATE_START = 1 -PERFCOUNTER_CNT2_STATE_FREEZE = 2 -PERFCOUNTER_CNT2_STATE_HW = 3 -PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT3_STATE' -PERFCOUNTER_CNT3_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT3_STATE_RESET', - 1: 'PERFCOUNTER_CNT3_STATE_START', - 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT3_STATE_HW', -} -PERFCOUNTER_CNT3_STATE_RESET = 0 -PERFCOUNTER_CNT3_STATE_START = 1 -PERFCOUNTER_CNT3_STATE_FREEZE = 2 -PERFCOUNTER_CNT3_STATE_HW = 3 -PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT4_STATE' -PERFCOUNTER_CNT4_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT4_STATE_RESET', - 1: 'PERFCOUNTER_CNT4_STATE_START', - 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT4_STATE_HW', -} -PERFCOUNTER_CNT4_STATE_RESET = 0 -PERFCOUNTER_CNT4_STATE_START = 1 -PERFCOUNTER_CNT4_STATE_FREEZE = 2 -PERFCOUNTER_CNT4_STATE_HW = 3 -PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT5_STATE' -PERFCOUNTER_CNT5_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT5_STATE_RESET', - 1: 'PERFCOUNTER_CNT5_STATE_START', - 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT5_STATE_HW', -} -PERFCOUNTER_CNT5_STATE_RESET = 0 -PERFCOUNTER_CNT5_STATE_START = 1 -PERFCOUNTER_CNT5_STATE_FREEZE = 2 -PERFCOUNTER_CNT5_STATE_HW = 3 -PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT6_STATE' -PERFCOUNTER_CNT6_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT6_STATE_RESET', - 1: 'PERFCOUNTER_CNT6_STATE_START', - 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT6_STATE_HW', -} -PERFCOUNTER_CNT6_STATE_RESET = 0 -PERFCOUNTER_CNT6_STATE_START = 1 -PERFCOUNTER_CNT6_STATE_FREEZE = 2 -PERFCOUNTER_CNT6_STATE_HW = 3 -PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT7_STATE' -PERFCOUNTER_CNT7_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT7_STATE_RESET', - 1: 'PERFCOUNTER_CNT7_STATE_START', - 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT7_STATE_HW', -} -PERFCOUNTER_CNT7_STATE_RESET = 0 -PERFCOUNTER_CNT7_STATE_START = 1 -PERFCOUNTER_CNT7_STATE_FREEZE = 2 -PERFCOUNTER_CNT7_STATE_HW = 3 -PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTL_SEL' -PERFCOUNTER_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_CNTL_SEL_0', - 1: 'PERFCOUNTER_CNTL_SEL_1', - 2: 'PERFCOUNTER_CNTL_SEL_2', - 3: 'PERFCOUNTER_CNTL_SEL_3', - 4: 'PERFCOUNTER_CNTL_SEL_4', - 5: 'PERFCOUNTER_CNTL_SEL_5', - 6: 'PERFCOUNTER_CNTL_SEL_6', - 7: 'PERFCOUNTER_CNTL_SEL_7', -} -PERFCOUNTER_CNTL_SEL_0 = 0 -PERFCOUNTER_CNTL_SEL_1 = 1 -PERFCOUNTER_CNTL_SEL_2 = 2 -PERFCOUNTER_CNTL_SEL_3 = 3 -PERFCOUNTER_CNTL_SEL_4 = 4 -PERFCOUNTER_CNTL_SEL_5 = 5 -PERFCOUNTER_CNTL_SEL_6 = 6 -PERFCOUNTER_CNTL_SEL_7 = 7 -PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' -PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { - 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', - 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', -} -PERFCOUNTER_CNTOFF_START_ENABLE = 0 -PERFCOUNTER_CNTOFF_START_DISABLE = 1 -PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' -PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { - 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', -} -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 -PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CVALUE_SEL' -PERFCOUNTER_CVALUE_SEL__enumvalues = { - 0: 'PERFCOUNTER_CVALUE_SEL_47_0', - 1: 'PERFCOUNTER_CVALUE_SEL_15_0', - 2: 'PERFCOUNTER_CVALUE_SEL_31_16', - 3: 'PERFCOUNTER_CVALUE_SEL_47_32', - 4: 'PERFCOUNTER_CVALUE_SEL_11_0', - 5: 'PERFCOUNTER_CVALUE_SEL_23_12', - 6: 'PERFCOUNTER_CVALUE_SEL_35_24', - 7: 'PERFCOUNTER_CVALUE_SEL_47_36', -} -PERFCOUNTER_CVALUE_SEL_47_0 = 0 -PERFCOUNTER_CVALUE_SEL_15_0 = 1 -PERFCOUNTER_CVALUE_SEL_31_16 = 2 -PERFCOUNTER_CVALUE_SEL_47_32 = 3 -PERFCOUNTER_CVALUE_SEL_11_0 = 4 -PERFCOUNTER_CVALUE_SEL_23_12 = 5 -PERFCOUNTER_CVALUE_SEL_35_24 = 6 -PERFCOUNTER_CVALUE_SEL_47_36 = 7 -PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' -PERFCOUNTER_HW_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', - 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', -} -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 -PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' -PERFCOUNTER_HW_STOP1_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP1_0', - 1: 'PERFCOUNTER_HW_STOP1_1', -} -PERFCOUNTER_HW_STOP1_0 = 0 -PERFCOUNTER_HW_STOP1_1 = 1 -PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' -PERFCOUNTER_HW_STOP2_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP2_0', - 1: 'PERFCOUNTER_HW_STOP2_1', -} -PERFCOUNTER_HW_STOP2_0 = 0 -PERFCOUNTER_HW_STOP2_1 = 1 -PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INC_MODE' -PERFCOUNTER_INC_MODE__enumvalues = { - 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', - 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', - 2: 'PERFCOUNTER_INC_MODE_LSB', - 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', - 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', -} -PERFCOUNTER_INC_MODE_MULTI_BIT = 0 -PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 -PERFCOUNTER_INC_MODE_LSB = 2 -PERFCOUNTER_INC_MODE_POS_EDGE = 3 -PERFCOUNTER_INC_MODE_NEG_EDGE = 4 -PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_EN' -PERFCOUNTER_INT_EN__enumvalues = { - 0: 'PERFCOUNTER_INT_DISABLE', - 1: 'PERFCOUNTER_INT_ENABLE', -} -PERFCOUNTER_INT_DISABLE = 0 -PERFCOUNTER_INT_ENABLE = 1 -PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_TYPE' -PERFCOUNTER_INT_TYPE__enumvalues = { - 0: 'PERFCOUNTER_INT_TYPE_LEVEL', - 1: 'PERFCOUNTER_INT_TYPE_PULSE', -} -PERFCOUNTER_INT_TYPE_LEVEL = 0 -PERFCOUNTER_INT_TYPE_PULSE = 1 -PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_OFF_MASK' -PERFCOUNTER_OFF_MASK__enumvalues = { - 0: 'PERFCOUNTER_OFF_MASK_DISABLE', - 1: 'PERFCOUNTER_OFF_MASK_ENABLE', -} -PERFCOUNTER_OFF_MASK_DISABLE = 0 -PERFCOUNTER_OFF_MASK_ENABLE = 1 -PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RESTART_EN' -PERFCOUNTER_RESTART_EN__enumvalues = { - 0: 'PERFCOUNTER_RESTART_DISABLE', - 1: 'PERFCOUNTER_RESTART_ENABLE', -} -PERFCOUNTER_RESTART_DISABLE = 0 -PERFCOUNTER_RESTART_ENABLE = 1 -PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RUNEN_MODE' -PERFCOUNTER_RUNEN_MODE__enumvalues = { - 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', -} -PERFCOUNTER_RUNEN_MODE_LEVEL = 0 -PERFCOUNTER_RUNEN_MODE_EDGE = 1 -PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL0' -PERFCOUNTER_STATE_SEL0__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', -} -PERFCOUNTER_STATE_SEL0_GLOBAL = 0 -PERFCOUNTER_STATE_SEL0_LOCAL = 1 -PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL1' -PERFCOUNTER_STATE_SEL1__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', -} -PERFCOUNTER_STATE_SEL1_GLOBAL = 0 -PERFCOUNTER_STATE_SEL1_LOCAL = 1 -PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL2' -PERFCOUNTER_STATE_SEL2__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', -} -PERFCOUNTER_STATE_SEL2_GLOBAL = 0 -PERFCOUNTER_STATE_SEL2_LOCAL = 1 -PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL3' -PERFCOUNTER_STATE_SEL3__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', -} -PERFCOUNTER_STATE_SEL3_GLOBAL = 0 -PERFCOUNTER_STATE_SEL3_LOCAL = 1 -PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL4' -PERFCOUNTER_STATE_SEL4__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', -} -PERFCOUNTER_STATE_SEL4_GLOBAL = 0 -PERFCOUNTER_STATE_SEL4_LOCAL = 1 -PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL5' -PERFCOUNTER_STATE_SEL5__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', -} -PERFCOUNTER_STATE_SEL5_GLOBAL = 0 -PERFCOUNTER_STATE_SEL5_LOCAL = 1 -PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL6' -PERFCOUNTER_STATE_SEL6__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', -} -PERFCOUNTER_STATE_SEL6_GLOBAL = 0 -PERFCOUNTER_STATE_SEL6_LOCAL = 1 -PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL7' -PERFCOUNTER_STATE_SEL7__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', -} -PERFCOUNTER_STATE_SEL7_GLOBAL = 0 -PERFCOUNTER_STATE_SEL7_LOCAL = 1 -PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_AND_OR' -PERFMON_CNTOFF_AND_OR__enumvalues = { - 0: 'PERFMON_CNTOFF_OR', - 1: 'PERFMON_CNTOFF_AND', -} -PERFMON_CNTOFF_OR = 0 -PERFMON_CNTOFF_AND = 1 -PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_EN' -PERFMON_CNTOFF_INT_EN__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_DISABLE', - 1: 'PERFMON_CNTOFF_INT_ENABLE', -} -PERFMON_CNTOFF_INT_DISABLE = 0 -PERFMON_CNTOFF_INT_ENABLE = 1 -PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' -PERFMON_CNTOFF_INT_TYPE__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', - 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', -} -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 -PERFMON_CNTOFF_INT_TYPE_PULSE = 1 -PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_STATE' -PERFMON_STATE__enumvalues = { - 0: 'PERFMON_STATE_RESET', - 1: 'PERFMON_STATE_START', - 2: 'PERFMON_STATE_FREEZE', - 3: 'PERFMON_STATE_HW', -} -PERFMON_STATE_RESET = 0 -PERFMON_STATE_START = 1 -PERFMON_STATE_FREEZE = 2 -PERFMON_STATE_HW = 3 -PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'BIGK_FRAGMENT_SIZE' -BIGK_FRAGMENT_SIZE__enumvalues = { - 0: 'VM_PG_SIZE_4KB', - 1: 'VM_PG_SIZE_8KB', - 2: 'VM_PG_SIZE_16KB', - 3: 'VM_PG_SIZE_32KB', - 4: 'VM_PG_SIZE_64KB', - 5: 'VM_PG_SIZE_128KB', - 6: 'VM_PG_SIZE_256KB', - 7: 'VM_PG_SIZE_512KB', - 8: 'VM_PG_SIZE_1MB', - 9: 'VM_PG_SIZE_2MB', - 10: 'VM_PG_SIZE_4MB', - 11: 'VM_PG_SIZE_8MB', - 12: 'VM_PG_SIZE_16MB', - 13: 'VM_PG_SIZE_32MB', - 14: 'VM_PG_SIZE_64MB', - 15: 'VM_PG_SIZE_128MB', -} -VM_PG_SIZE_4KB = 0 -VM_PG_SIZE_8KB = 1 -VM_PG_SIZE_16KB = 2 -VM_PG_SIZE_32KB = 3 -VM_PG_SIZE_64KB = 4 -VM_PG_SIZE_128KB = 5 -VM_PG_SIZE_256KB = 6 -VM_PG_SIZE_512KB = 7 -VM_PG_SIZE_1MB = 8 -VM_PG_SIZE_2MB = 9 -VM_PG_SIZE_4MB = 10 -VM_PG_SIZE_8MB = 11 -VM_PG_SIZE_16MB = 12 -VM_PG_SIZE_32MB = 13 -VM_PG_SIZE_64MB = 14 -VM_PG_SIZE_128MB = 15 -BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CHUNK_SIZE' -CHUNK_SIZE__enumvalues = { - 0: 'CHUNK_SIZE_1KB', - 1: 'CHUNK_SIZE_2KB', - 2: 'CHUNK_SIZE_4KB', - 3: 'CHUNK_SIZE_8KB', - 4: 'CHUNK_SIZE_16KB', - 5: 'CHUNK_SIZE_32KB', - 6: 'CHUNK_SIZE_64KB', -} -CHUNK_SIZE_1KB = 0 -CHUNK_SIZE_2KB = 1 -CHUNK_SIZE_4KB = 2 -CHUNK_SIZE_8KB = 3 -CHUNK_SIZE_16KB = 4 -CHUNK_SIZE_32KB = 5 -CHUNK_SIZE_64KB = 6 -CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DPTE_GROUP_SIZE' -DPTE_GROUP_SIZE__enumvalues = { - 0: 'DPTE_GROUP_SIZE_64B', - 1: 'DPTE_GROUP_SIZE_128B', - 2: 'DPTE_GROUP_SIZE_256B', - 3: 'DPTE_GROUP_SIZE_512B', - 4: 'DPTE_GROUP_SIZE_1024B', - 5: 'DPTE_GROUP_SIZE_2048B', -} -DPTE_GROUP_SIZE_64B = 0 -DPTE_GROUP_SIZE_128B = 1 -DPTE_GROUP_SIZE_256B = 2 -DPTE_GROUP_SIZE_512B = 3 -DPTE_GROUP_SIZE_1024B = 4 -DPTE_GROUP_SIZE_2048B = 5 -DPTE_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' -FORCE_ONE_ROW_FOR_FRAME__enumvalues = { - 0: 'FORCE_ONE_ROW_FOR_FRAME_0', - 1: 'FORCE_ONE_ROW_FOR_FRAME_1', -} -FORCE_ONE_ROW_FOR_FRAME_0 = 0 -FORCE_ONE_ROW_FOR_FRAME_1 = 1 -FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_BLANK_EN' -HUBP_BLANK_EN__enumvalues = { - 0: 'HUBP_BLANK_SW_DEASSERT', - 1: 'HUBP_BLANK_SW_ASSERT', -} -HUBP_BLANK_SW_DEASSERT = 0 -HUBP_BLANK_SW_ASSERT = 1 -HUBP_BLANK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_IN_BLANK' -HUBP_IN_BLANK__enumvalues = { - 0: 'HUBP_IN_ACTIVE', - 1: 'HUBP_IN_VBLANK', -} -HUBP_IN_ACTIVE = 0 -HUBP_IN_VBLANK = 1 -HUBP_IN_BLANK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' -HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { - 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', -} -HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 -HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 -HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 -HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 -HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' -HUBP_NO_OUTSTANDING_REQ__enumvalues = { - 0: 'OUTSTANDING_REQ', - 1: 'NO_OUTSTANDING_REQ', -} -OUTSTANDING_REQ = 0 -NO_OUTSTANDING_REQ = 1 -HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_SOFT_RESET' -HUBP_SOFT_RESET__enumvalues = { - 0: 'HUBP_SOFT_RESET_ON', - 1: 'HUBP_SOFT_RESET_OFF', -} -HUBP_SOFT_RESET_ON = 0 -HUBP_SOFT_RESET_OFF = 1 -HUBP_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_TTU_DISABLE' -HUBP_TTU_DISABLE__enumvalues = { - 0: 'HUBP_TTU_ENABLED', - 1: 'HUBP_TTU_DISABLED', -} -HUBP_TTU_ENABLED = 0 -HUBP_TTU_DISABLED = 1 -HUBP_TTU_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' -HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { - 0: 'VREADY_BEFORE_VSYNC', - 1: 'VREADY_AT_OR_AFTER_VSYNC', -} -VREADY_BEFORE_VSYNC = 0 -VREADY_AT_OR_AFTER_VSYNC = 1 -HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VTG_SEL' -HUBP_VTG_SEL__enumvalues = { - 0: 'VTG_SEL_0', - 1: 'VTG_SEL_1', - 2: 'VTG_SEL_2', - 3: 'VTG_SEL_3', - 4: 'VTG_SEL_4', - 5: 'VTG_SEL_5', -} -VTG_SEL_0 = 0 -VTG_SEL_1 = 1 -VTG_SEL_2 = 2 -VTG_SEL_3 = 3 -VTG_SEL_4 = 4 -VTG_SEL_5 = 5 -HUBP_VTG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'H_MIRROR_EN' -H_MIRROR_EN__enumvalues = { - 0: 'HW_MIRRORING_DISABLE', - 1: 'HW_MIRRORING_ENABLE', -} -HW_MIRRORING_DISABLE = 0 -HW_MIRRORING_ENABLE = 1 -H_MIRROR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LEGACY_PIPE_INTERLEAVE' -LEGACY_PIPE_INTERLEAVE__enumvalues = { - 0: 'LEGACY_PIPE_INTERLEAVE_256B', - 1: 'LEGACY_PIPE_INTERLEAVE_512B', -} -LEGACY_PIPE_INTERLEAVE_256B = 0 -LEGACY_PIPE_INTERLEAVE_512B = 1 -LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum - -# values for enumeration 'META_CHUNK_SIZE' -META_CHUNK_SIZE__enumvalues = { - 0: 'META_CHUNK_SIZE_1KB', - 1: 'META_CHUNK_SIZE_2KB', - 2: 'META_CHUNK_SIZE_4KB', - 3: 'META_CHUNK_SIZE_8KB', -} -META_CHUNK_SIZE_1KB = 0 -META_CHUNK_SIZE_2KB = 1 -META_CHUNK_SIZE_4KB = 2 -META_CHUNK_SIZE_8KB = 3 -META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'META_LINEAR' -META_LINEAR__enumvalues = { - 0: 'META_SURF_TILED', - 1: 'META_SURF_LINEAR', -} -META_SURF_TILED = 0 -META_SURF_LINEAR = 1 -META_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_CHUNK_SIZE' -MIN_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_CHUNK_SIZE', - 1: 'MIN_CHUNK_SIZE_256B', - 2: 'MIN_CHUNK_SIZE_512B', - 3: 'MIN_CHUNK_SIZE_1024B', -} -NO_MIN_CHUNK_SIZE = 0 -MIN_CHUNK_SIZE_256B = 1 -MIN_CHUNK_SIZE_512B = 2 -MIN_CHUNK_SIZE_1024B = 3 -MIN_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_META_CHUNK_SIZE' -MIN_META_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_META_CHUNK_SIZE', - 1: 'MIN_META_CHUNK_SIZE_64B', - 2: 'MIN_META_CHUNK_SIZE_128B', - 3: 'MIN_META_CHUNK_SIZE_256B', -} -NO_MIN_META_CHUNK_SIZE = 0 -MIN_META_CHUNK_SIZE_64B = 1 -MIN_META_CHUNK_SIZE_128B = 2 -MIN_META_CHUNK_SIZE_256B = 3 -MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_ALIGNED' -PIPE_ALIGNED__enumvalues = { - 0: 'PIPE_UNALIGNED_SURF', - 1: 'PIPE_ALIGNED_SURF', -} -PIPE_UNALIGNED_SURF = 0 -PIPE_ALIGNED_SURF = 1 -PIPE_ALIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_BUFFER_MODE' -PTE_BUFFER_MODE__enumvalues = { - 0: 'PTE_BUFFER_MODE_0', - 1: 'PTE_BUFFER_MODE_1', -} -PTE_BUFFER_MODE_0 = 0 -PTE_BUFFER_MODE_1 = 1 -PTE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' -PTE_ROW_HEIGHT_LINEAR__enumvalues = { - 0: 'PTE_ROW_HEIGHT_LINEAR_8L', - 1: 'PTE_ROW_HEIGHT_LINEAR_16L', - 2: 'PTE_ROW_HEIGHT_LINEAR_32L', - 3: 'PTE_ROW_HEIGHT_LINEAR_64L', - 4: 'PTE_ROW_HEIGHT_LINEAR_128L', - 5: 'PTE_ROW_HEIGHT_LINEAR_256L', - 6: 'PTE_ROW_HEIGHT_LINEAR_512L', - 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', -} -PTE_ROW_HEIGHT_LINEAR_8L = 0 -PTE_ROW_HEIGHT_LINEAR_16L = 1 -PTE_ROW_HEIGHT_LINEAR_32L = 2 -PTE_ROW_HEIGHT_LINEAR_64L = 3 -PTE_ROW_HEIGHT_LINEAR_128L = 4 -PTE_ROW_HEIGHT_LINEAR_256L = 5 -PTE_ROW_HEIGHT_LINEAR_512L = 6 -PTE_ROW_HEIGHT_LINEAR_1024L = 7 -PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'ROTATION_ANGLE' -ROTATION_ANGLE__enumvalues = { - 0: 'ROTATE_0_DEGREES', - 1: 'ROTATE_90_DEGREES', - 2: 'ROTATE_180_DEGREES', - 3: 'ROTATE_270_DEGREES', -} -ROTATE_0_DEGREES = 0 -ROTATE_90_DEGREES = 1 -ROTATE_180_DEGREES = 2 -ROTATE_270_DEGREES = 3 -ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'SWATH_HEIGHT' -SWATH_HEIGHT__enumvalues = { - 0: 'SWATH_HEIGHT_1L', - 1: 'SWATH_HEIGHT_2L', - 2: 'SWATH_HEIGHT_4L', - 3: 'SWATH_HEIGHT_8L', - 4: 'SWATH_HEIGHT_16L', -} -SWATH_HEIGHT_1L = 0 -SWATH_HEIGHT_2L = 1 -SWATH_HEIGHT_4L = 2 -SWATH_HEIGHT_8L = 3 -SWATH_HEIGHT_16L = 4 -SWATH_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'VMPG_SIZE' -VMPG_SIZE__enumvalues = { - 0: 'VMPG_SIZE_4KB', - 1: 'VMPG_SIZE_64KB', -} -VMPG_SIZE_4KB = 0 -VMPG_SIZE_64KB = 1 -VMPG_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VM_GROUP_SIZE' -VM_GROUP_SIZE__enumvalues = { - 0: 'VM_GROUP_SIZE_64B', - 1: 'VM_GROUP_SIZE_128B', - 2: 'VM_GROUP_SIZE_256B', - 3: 'VM_GROUP_SIZE_512B', - 4: 'VM_GROUP_SIZE_1024B', - 5: 'VM_GROUP_SIZE_2048B', -} -VM_GROUP_SIZE_64B = 0 -VM_GROUP_SIZE_128B = 1 -VM_GROUP_SIZE_256B = 2 -VM_GROUP_SIZE_512B = 3 -VM_GROUP_SIZE_1024B = 4 -VM_GROUP_SIZE_2048B = 5 -VM_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_MIN_FREE_ENTRIES' -DFQ_MIN_FREE_ENTRIES__enumvalues = { - 0: 'DFQ_MIN_FREE_ENTRIES_0', - 1: 'DFQ_MIN_FREE_ENTRIES_1', - 2: 'DFQ_MIN_FREE_ENTRIES_2', - 3: 'DFQ_MIN_FREE_ENTRIES_3', - 4: 'DFQ_MIN_FREE_ENTRIES_4', - 5: 'DFQ_MIN_FREE_ENTRIES_5', - 6: 'DFQ_MIN_FREE_ENTRIES_6', - 7: 'DFQ_MIN_FREE_ENTRIES_7', -} -DFQ_MIN_FREE_ENTRIES_0 = 0 -DFQ_MIN_FREE_ENTRIES_1 = 1 -DFQ_MIN_FREE_ENTRIES_2 = 2 -DFQ_MIN_FREE_ENTRIES_3 = 3 -DFQ_MIN_FREE_ENTRIES_4 = 4 -DFQ_MIN_FREE_ENTRIES_5 = 5 -DFQ_MIN_FREE_ENTRIES_6 = 6 -DFQ_MIN_FREE_ENTRIES_7 = 7 -DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_NUM_ENTRIES' -DFQ_NUM_ENTRIES__enumvalues = { - 0: 'DFQ_NUM_ENTRIES_0', - 1: 'DFQ_NUM_ENTRIES_1', - 2: 'DFQ_NUM_ENTRIES_2', - 3: 'DFQ_NUM_ENTRIES_3', - 4: 'DFQ_NUM_ENTRIES_4', - 5: 'DFQ_NUM_ENTRIES_5', - 6: 'DFQ_NUM_ENTRIES_6', - 7: 'DFQ_NUM_ENTRIES_7', - 8: 'DFQ_NUM_ENTRIES_8', -} -DFQ_NUM_ENTRIES_0 = 0 -DFQ_NUM_ENTRIES_1 = 1 -DFQ_NUM_ENTRIES_2 = 2 -DFQ_NUM_ENTRIES_3 = 3 -DFQ_NUM_ENTRIES_4 = 4 -DFQ_NUM_ENTRIES_5 = 5 -DFQ_NUM_ENTRIES_6 = 6 -DFQ_NUM_ENTRIES_7 = 7 -DFQ_NUM_ENTRIES_8 = 8 -DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_SIZE' -DFQ_SIZE__enumvalues = { - 0: 'DFQ_SIZE_0', - 1: 'DFQ_SIZE_1', - 2: 'DFQ_SIZE_2', - 3: 'DFQ_SIZE_3', - 4: 'DFQ_SIZE_4', - 5: 'DFQ_SIZE_5', - 6: 'DFQ_SIZE_6', - 7: 'DFQ_SIZE_7', -} -DFQ_SIZE_0 = 0 -DFQ_SIZE_1 = 1 -DFQ_SIZE_2 = 2 -DFQ_SIZE_3 = 3 -DFQ_SIZE_4 = 4 -DFQ_SIZE_5 = 5 -DFQ_SIZE_6 = 6 -DFQ_SIZE_7 = 7 -DFQ_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_VM_DONE' -DMDATA_VM_DONE__enumvalues = { - 0: 'DMDATA_VM_IS_NOT_DONE', - 1: 'DMDATA_VM_IS_DONE', -} -DMDATA_VM_IS_NOT_DONE = 0 -DMDATA_VM_IS_DONE = 1 -DMDATA_VM_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'EXPANSION_MODE' -EXPANSION_MODE__enumvalues = { - 0: 'EXPANSION_MODE_ZERO', - 1: 'EXPANSION_MODE_CONSERVATIVE', - 2: 'EXPANSION_MODE_OPTIMAL', -} -EXPANSION_MODE_ZERO = 0 -EXPANSION_MODE_CONSERVATIVE = 1 -EXPANSION_MODE_OPTIMAL = 2 -EXPANSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FLIP_RATE' -FLIP_RATE__enumvalues = { - 0: 'FLIP_RATE_0', - 1: 'FLIP_RATE_1', - 2: 'FLIP_RATE_2', - 3: 'FLIP_RATE_3', - 4: 'FLIP_RATE_4', - 5: 'FLIP_RATE_5', - 6: 'FLIP_RATE_6', - 7: 'FLIP_RATE_7', -} -FLIP_RATE_0 = 0 -FLIP_RATE_1 = 1 -FLIP_RATE_2 = 2 -FLIP_RATE_3 = 3 -FLIP_RATE_4 = 4 -FLIP_RATE_5 = 5 -FLIP_RATE_6 = 6 -FLIP_RATE_7 = 7 -FLIP_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'INT_MASK' -INT_MASK__enumvalues = { - 0: 'INT_DISABLED', - 1: 'INT_ENABLED', -} -INT_DISABLED = 0 -INT_ENABLED = 1 -INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_IN_FLUSH_URGENT' -PIPE_IN_FLUSH_URGENT__enumvalues = { - 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', - 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', -} -PIPE_IN_FLUSH_URGENT_ENABLE = 0 -PIPE_IN_FLUSH_URGENT_DISABLE = 1 -PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' -PRQ_MRQ_FLUSH_URGENT__enumvalues = { - 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', - 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', -} -PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 -PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 -PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'ROW_TTU_MODE' -ROW_TTU_MODE__enumvalues = { - 0: 'END_OF_ROW_MODE', - 1: 'WATERMARK_MODE', -} -END_OF_ROW_MODE = 0 -WATERMARK_MODE = 1 -ROW_TTU_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC' -SURFACE_DCC__enumvalues = { - 0: 'SURFACE_IS_NOT_DCC', - 1: 'SURFACE_IS_DCC', -} -SURFACE_IS_NOT_DCC = 0 -SURFACE_IS_DCC = 1 -SURFACE_DCC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_128B' -SURFACE_DCC_IND_128B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_128B', - 1: 'SURFACE_DCC_IS_IND_128B', -} -SURFACE_DCC_IS_NOT_IND_128B = 0 -SURFACE_DCC_IS_IND_128B = 1 -SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_64B' -SURFACE_DCC_IND_64B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_64B', - 1: 'SURFACE_DCC_IS_IND_64B', -} -SURFACE_DCC_IS_NOT_IND_64B = 0 -SURFACE_DCC_IS_IND_64B = 1 -SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_BLK' -SURFACE_DCC_IND_BLK__enumvalues = { - 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', - 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', - 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', - 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', -} -SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 -SURFACE_DCC_BLOCK_IS_IND_64B = 1 -SURFACE_DCC_BLOCK_IS_IND_128B = 2 -SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 -SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' -SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', - 1: 'SURFACE_FLIP_AWAY_INT_PULSE', -} -SURFACE_FLIP_AWAY_INT_LEVEL = 0 -SURFACE_FLIP_AWAY_INT_PULSE = 1 -SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' -SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { - 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', - 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', -} -SURFACE_FLIP_EXEC_NORMAL_MODE = 0 -SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 -SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_INT_TYPE' -SURFACE_FLIP_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_INT_LEVEL', - 1: 'SURFACE_FLIP_INT_PULSE', -} -SURFACE_FLIP_INT_LEVEL = 0 -SURFACE_FLIP_INT_PULSE = 1 -SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' -SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { - 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', -} -SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 -SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 -SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' -SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { - 0: 'FLIP_ANY_FRAME', - 1: 'FLIP_LEFT_EYE', - 2: 'FLIP_RIGHT_EYE', - 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', -} -FLIP_ANY_FRAME = 0 -FLIP_LEFT_EYE = 1 -FLIP_RIGHT_EYE = 2 -SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 -SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' -SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', -} -SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 -SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 -SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' -SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', -} -SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 -SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 -SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_TYPE' -SURFACE_FLIP_TYPE__enumvalues = { - 0: 'SURFACE_V_FLIP', - 1: 'SURFACE_I_FLIP', -} -SURFACE_V_FLIP = 0 -SURFACE_I_FLIP = 1 -SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' -SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { - 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', - 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', -} -SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 -SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 -SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 -SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 -SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 -SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 -SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 -SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 -SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 -SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 -SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 -SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 -SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 -SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 -SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 -SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 -SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' -SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { - 0: 'SURFACE_INUSE_IS_LATCHED', - 1: 'SURFACE_INUSE_IS_NOT_LATCHED', -} -SURFACE_INUSE_IS_LATCHED = 0 -SURFACE_INUSE_IS_NOT_LATCHED = 1 -SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_TMZ' -SURFACE_TMZ__enumvalues = { - 0: 'SURFACE_IS_NOT_TMZ', - 1: 'SURFACE_IS_TMZ', -} -SURFACE_IS_NOT_TMZ = 0 -SURFACE_IS_TMZ = 1 -SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_UPDATE_LOCK' -SURFACE_UPDATE_LOCK__enumvalues = { - 0: 'SURFACE_UPDATE_IS_UNLOCKED', - 1: 'SURFACE_UPDATE_IS_LOCKED', -} -SURFACE_UPDATE_IS_UNLOCKED = 0 -SURFACE_UPDATE_IS_LOCKED = 1 -SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_ALPHA' -CROSSBAR_FOR_ALPHA__enumvalues = { - 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', - 1: 'Y_G_DATA_ONTO_ALPHA_PORT', - 2: 'CB_B_DATA_ONTO_ALPHA_PORT', - 3: 'CR_R_DATA_ONTO_ALPHA_PORT', -} -ALPHA_DATA_ONTO_ALPHA_PORT = 0 -Y_G_DATA_ONTO_ALPHA_PORT = 1 -CB_B_DATA_ONTO_ALPHA_PORT = 2 -CR_R_DATA_ONTO_ALPHA_PORT = 3 -CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CB_B' -CROSSBAR_FOR_CB_B__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CB_B_PORT', - 1: 'Y_G_DATA_ONTO_CB_B_PORT', - 2: 'CB_B_DATA_ONTO_CB_B_PORT', - 3: 'CR_R_DATA_ONTO_CB_B_PORT', -} -ALPHA_DATA_ONTO_CB_B_PORT = 0 -Y_G_DATA_ONTO_CB_B_PORT = 1 -CB_B_DATA_ONTO_CB_B_PORT = 2 -CR_R_DATA_ONTO_CB_B_PORT = 3 -CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CR_R' -CROSSBAR_FOR_CR_R__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CR_R_PORT', - 1: 'Y_G_DATA_ONTO_CR_R_PORT', - 2: 'CB_B_DATA_ONTO_CR_R_PORT', - 3: 'CR_R_DATA_ONTO_CR_R_PORT', -} -ALPHA_DATA_ONTO_CR_R_PORT = 0 -Y_G_DATA_ONTO_CR_R_PORT = 1 -CB_B_DATA_ONTO_CR_R_PORT = 2 -CR_R_DATA_ONTO_CR_R_PORT = 3 -CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_Y_G' -CROSSBAR_FOR_Y_G__enumvalues = { - 0: 'ALPHA_DATA_ONTO_Y_G_PORT', - 1: 'Y_G_DATA_ONTO_Y_G_PORT', - 2: 'CB_B_DATA_ONTO_Y_G_PORT', - 3: 'CR_R_DATA_ONTO_Y_G_PORT', -} -ALPHA_DATA_ONTO_Y_G_PORT = 0 -Y_G_DATA_ONTO_Y_G_PORT = 1 -CB_B_DATA_ONTO_Y_G_PORT = 2 -CR_R_DATA_ONTO_Y_G_PORT = 3 -CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum - -# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' -DETILE_BUFFER_PACKER_ENABLE__enumvalues = { - 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', - 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', -} -DETILE_BUFFER_PACKER_IS_DISABLE = 0 -DETILE_BUFFER_PACKER_IS_ENABLE = 1 -DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_MODE' -MEM_PWR_DIS_MODE__enumvalues = { - 0: 'MEM_POWER_DIS_MODE_ENABLE', - 1: 'MEM_POWER_DIS_MODE_DISABLE', -} -MEM_POWER_DIS_MODE_ENABLE = 0 -MEM_POWER_DIS_MODE_DISABLE = 1 -MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_MODE' -MEM_PWR_FORCE_MODE__enumvalues = { - 0: 'MEM_POWER_FORCE_MODE_OFF', - 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', - 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', -} -MEM_POWER_FORCE_MODE_OFF = 0 -MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 -MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 -MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 -MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_STATUS' -MEM_PWR_STATUS__enumvalues = { - 0: 'MEM_POWER_STATUS_ON', - 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', - 2: 'MEM_POWER_STATUS_DEEP_SLEEP', - 3: 'MEM_POWER_STATUS_SHUT_DOWN', -} -MEM_POWER_STATUS_ON = 0 -MEM_POWER_STATUS_LIGHT_SLEEP = 1 -MEM_POWER_STATUS_DEEP_SLEEP = 2 -MEM_POWER_STATUS_SHUT_DOWN = 3 -MEM_PWR_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_MASK_MODE' -PIPE_INT_MASK_MODE__enumvalues = { - 0: 'PIPE_INT_MASK_MODE_DISABLE', - 1: 'PIPE_INT_MASK_MODE_ENABLE', -} -PIPE_INT_MASK_MODE_DISABLE = 0 -PIPE_INT_MASK_MODE_ENABLE = 1 -PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_TYPE_MODE' -PIPE_INT_TYPE_MODE__enumvalues = { - 0: 'PIPE_INT_TYPE_MODE_DISABLE', - 1: 'PIPE_INT_TYPE_MODE_ENABLE', -} -PIPE_INT_TYPE_MODE_DISABLE = 0 -PIPE_INT_TYPE_MODE_ENABLE = 1 -PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', -} -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' -CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_2X_MAGNIFY' -CURSOR_2X_MAGNIFY__enumvalues = { - 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', - 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', -} -CURSOR_2X_MAGNIFY_IS_DISABLE = 0 -CURSOR_2X_MAGNIFY_IS_ENABLE = 1 -CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_ENABLE' -CURSOR_ENABLE__enumvalues = { - 0: 'CURSOR_IS_DISABLE', - 1: 'CURSOR_IS_ENABLE', -} -CURSOR_IS_DISABLE = 0 -CURSOR_IS_ENABLE = 1 -CURSOR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_LINES_PER_CHUNK' -CURSOR_LINES_PER_CHUNK__enumvalues = { - 0: 'CURSOR_LINE_PER_CHUNK_1', - 1: 'CURSOR_LINE_PER_CHUNK_2', - 2: 'CURSOR_LINE_PER_CHUNK_4', - 3: 'CURSOR_LINE_PER_CHUNK_8', - 4: 'CURSOR_LINE_PER_CHUNK_16', -} -CURSOR_LINE_PER_CHUNK_1 = 0 -CURSOR_LINE_PER_CHUNK_2 = 1 -CURSOR_LINE_PER_CHUNK_4 = 2 -CURSOR_LINE_PER_CHUNK_8 = 3 -CURSOR_LINE_PER_CHUNK_16 = 4 -CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_MODE' -CURSOR_MODE__enumvalues = { - 0: 'CURSOR_MONO_2BIT', - 1: 'CURSOR_COLOR_24BIT_1BIT_AND', - 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', - 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', -} -CURSOR_MONO_2BIT = 0 -CURSOR_COLOR_24BIT_1BIT_AND = 1 -CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -CURSOR_COLOR_64BIT_FP_PREMULT = 4 -CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 -CURSOR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' -CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', -} -CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 -CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 -CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' -CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', -} -CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 -CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 -CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PITCH' -CURSOR_PITCH__enumvalues = { - 0: 'CURSOR_PITCH_64_PIXELS', - 1: 'CURSOR_PITCH_128_PIXELS', - 2: 'CURSOR_PITCH_256_PIXELS', -} -CURSOR_PITCH_64_PIXELS = 0 -CURSOR_PITCH_128_PIXELS = 1 -CURSOR_PITCH_256_PIXELS = 2 -CURSOR_PITCH = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_REQ_MODE' -CURSOR_REQ_MODE__enumvalues = { - 0: 'CURSOR_REQUEST_NORMALLY', - 1: 'CURSOR_REQUEST_EARLY', -} -CURSOR_REQUEST_NORMALLY = 0 -CURSOR_REQUEST_EARLY = 1 -CURSOR_REQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SNOOP' -CURSOR_SNOOP__enumvalues = { - 0: 'CURSOR_IS_NOT_SNOOP', - 1: 'CURSOR_IS_SNOOP', -} -CURSOR_IS_NOT_SNOOP = 0 -CURSOR_IS_SNOOP = 1 -CURSOR_SNOOP = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_STEREO_EN' -CURSOR_STEREO_EN__enumvalues = { - 0: 'CURSOR_STEREO_IS_DISABLED', - 1: 'CURSOR_STEREO_IS_ENABLED', -} -CURSOR_STEREO_IS_DISABLED = 0 -CURSOR_STEREO_IS_ENABLED = 1 -CURSOR_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SURFACE_TMZ' -CURSOR_SURFACE_TMZ__enumvalues = { - 0: 'CURSOR_SURFACE_IS_NOT_TMZ', - 1: 'CURSOR_SURFACE_IS_TMZ', -} -CURSOR_SURFACE_IS_NOT_TMZ = 0 -CURSOR_SURFACE_IS_TMZ = 1 -CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SYSTEM' -CURSOR_SYSTEM__enumvalues = { - 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', - 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', -} -CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 -CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 -CURSOR_SYSTEM = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { - 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', -} -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_DONE' -DMDATA_DONE__enumvalues = { - 0: 'DMDATA_NOT_SENT_TO_DIG', - 1: 'DMDATA_SENT_TO_DIG', -} -DMDATA_NOT_SENT_TO_DIG = 0 -DMDATA_SENT_TO_DIG = 1 -DMDATA_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_MODE' -DMDATA_MODE__enumvalues = { - 0: 'DMDATA_SOFTWARE_UPDATE_MODE', - 1: 'DMDATA_HARDWARE_UPDATE_MODE', -} -DMDATA_SOFTWARE_UPDATE_MODE = 0 -DMDATA_HARDWARE_UPDATE_MODE = 1 -DMDATA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_QOS_MODE' -DMDATA_QOS_MODE__enumvalues = { - 0: 'DMDATA_QOS_LEVEL_FROM_TTU', - 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', -} -DMDATA_QOS_LEVEL_FROM_TTU = 0 -DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 -DMDATA_QOS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_REPEAT' -DMDATA_REPEAT__enumvalues = { - 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', - 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', -} -DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 -DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 -DMDATA_REPEAT = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW' -DMDATA_UNDERFLOW__enumvalues = { - 0: 'DMDATA_NOT_UNDERFLOW', - 1: 'DMDATA_UNDERFLOWED', -} -DMDATA_NOT_UNDERFLOW = 0 -DMDATA_UNDERFLOWED = 1 -DMDATA_UNDERFLOW = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' -DMDATA_UNDERFLOW_CLEAR__enumvalues = { - 0: 'DMDATA_DONT_CLEAR', - 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', -} -DMDATA_DONT_CLEAR = 0 -DMDATA_CLEAR_UNDERFLOW_STATUS = 1 -DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UPDATED' -DMDATA_UPDATED__enumvalues = { - 0: 'DMDATA_NOT_UPDATED', - 1: 'DMDATA_WAS_UPDATED', -} -DMDATA_NOT_UPDATED = 0 -DMDATA_WAS_UPDATED = 1 -DMDATA_UPDATED = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_3DLUT_ADDRESSING_MODE' -HUBP_3DLUT_ADDRESSING_MODE__enumvalues = { - 0: 'HUBP_3DLUT_SW_LINEAR', - 1: 'HUBP_3DLUT_SIMPLE_LINEAR', -} -HUBP_3DLUT_SW_LINEAR = 0 -HUBP_3DLUT_SIMPLE_LINEAR = 1 -HUBP_3DLUT_ADDRESSING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RESPONSE_STATUS' -RESPONSE_STATUS__enumvalues = { - 0: 'OKAY', - 1: 'EXOKAY', - 2: 'SLVERR', - 3: 'DECERR', - 4: 'EARLY', - 5: 'OKAY_NODATA', - 6: 'PROTVIOL', - 7: 'TRANSERR', - 8: 'CMPTO', - 12: 'CRS', -} -OKAY = 0 -EXOKAY = 1 -SLVERR = 2 -DECERR = 3 -EARLY = 4 -OKAY_NODATA = 5 -PROTVIOL = 6 -TRANSERR = 7 -CMPTO = 8 -CRS = 12 -RESPONSE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' -DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', -} -DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 -DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 -DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' -DCHUBBUB_MEM_PWR_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', - 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', -} -DCHUBBUB_MEM_POWER_MODE_OFF = 0 -DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 -DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 -DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 -DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_3DLUT_FL_FORMAT' -MPC_CFG_3DLUT_FL_FORMAT__enumvalues = { - 0: 'MPC_CFG_3DLUT_FL_FORMAT_0', - 1: 'MPC_CFG_3DLUT_FL_FORMAT_1', - 2: 'MPC_CFG_3DLUT_FL_FORMAT_2', -} -MPC_CFG_3DLUT_FL_FORMAT_0 = 0 -MPC_CFG_3DLUT_FL_FORMAT_1 = 1 -MPC_CFG_3DLUT_FL_FORMAT_2 = 2 -MPC_CFG_3DLUT_FL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_3DLUT_FL_MODE' -MPC_CFG_3DLUT_FL_MODE__enumvalues = { - 0: 'MPC_CFG_3DLUT_FL_MODE_0', - 1: 'MPC_CFG_3DLUT_FL_MODE_1', - 2: 'MPC_CFG_3DLUT_FL_MODE_2', - 3: 'MPC_CFG_3DLUT_FL_MODE_3', -} -MPC_CFG_3DLUT_FL_MODE_0 = 0 -MPC_CFG_3DLUT_FL_MODE_1 = 1 -MPC_CFG_3DLUT_FL_MODE_2 = 2 -MPC_CFG_3DLUT_FL_MODE_3 = 3 -MPC_CFG_3DLUT_FL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' -MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' -MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { - 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', - 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', - 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', -} -MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 -MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 -MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 -MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 -MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' -MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { - 0: 'MPC_CRC_INTERLACE_MODE_TOP', - 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', - 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', -} -MPC_CRC_INTERLACE_MODE_TOP = 0 -MPC_CRC_INTERLACE_MODE_BOTTOM = 1 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_MODE' -MPC_CRC_CALC_MODE__enumvalues = { - 0: 'MPC_CRC_ONE_SHOT_MODE', - 1: 'MPC_CRC_CONTINUOUS_MODE', -} -MPC_CRC_ONE_SHOT_MODE = 0 -MPC_CRC_CONTINUOUS_MODE = 1 -MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' -MPC_CRC_CALC_STEREO_MODE__enumvalues = { - 0: 'MPC_CRC_STEREO_MODE_LEFT', - 1: 'MPC_CRC_STEREO_MODE_RIGHT', - 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', -} -MPC_CRC_STEREO_MODE_LEFT = 0 -MPC_CRC_STEREO_MODE_RIGHT = 1 -MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 -MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_SOURCE_SELECT' -MPC_CRC_SOURCE_SELECT__enumvalues = { - 0: 'MPC_CRC_SOURCE_SEL_DPP', - 1: 'MPC_CRC_SOURCE_SEL_OPP', - 2: 'MPC_CRC_SOURCE_SEL_DWB', - 3: 'MPC_CRC_SOURCE_SEL_OTHER', -} -MPC_CRC_SOURCE_SEL_DPP = 0 -MPC_CRC_SOURCE_SEL_OPP = 1 -MPC_CRC_SOURCE_SEL_DWB = 2 -MPC_CRC_SOURCE_SEL_OTHER = 3 -MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_COEF_FORMAT' -MPC_OCSC_COEF_FORMAT__enumvalues = { - 0: 'MPC_OCSC_COEF_FORMAT_S2_13', - 1: 'MPC_OCSC_COEF_FORMAT_S3_12', -} -MPC_OCSC_COEF_FORMAT_S2_13 = 0 -MPC_OCSC_COEF_FORMAT_S3_12 = 1 -MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_CSC_MODE' -MPC_OUT_CSC_MODE__enumvalues = { - 0: 'MPC_OUT_CSC_MODE_0', - 1: 'MPC_OUT_CSC_MODE_1', - 2: 'MPC_OUT_CSC_MODE_2', - 3: 'MPC_OUT_CSC_MODE_RSV', -} -MPC_OUT_CSC_MODE_0 = 0 -MPC_OUT_CSC_MODE_1 = 1 -MPC_OUT_CSC_MODE_2 = 2 -MPC_OUT_CSC_MODE_RSV = 3 -MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { - 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', -} -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' -MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { - 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', -} -MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 -MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 -MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_BG_COLOR_BPC' -MPCC_BG_COLOR_BPC__enumvalues = { - 0: 'MPCC_BG_COLOR_BPC_8bit', - 1: 'MPCC_BG_COLOR_BPC_9bit', - 2: 'MPCC_BG_COLOR_BPC_10bit', - 3: 'MPCC_BG_COLOR_BPC_11bit', - 4: 'MPCC_BG_COLOR_BPC_12bit', -} -MPCC_BG_COLOR_BPC_8bit = 0 -MPCC_BG_COLOR_BPC_9bit = 1 -MPCC_BG_COLOR_BPC_10bit = 2 -MPCC_BG_COLOR_BPC_11bit = 3 -MPCC_BG_COLOR_BPC_12bit = 4 -MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', -} -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', -} -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', -} -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' -MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', -} -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_MODE' -MPCC_CONTROL_MPCC_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', -} -MPCC_CONTROL_MPCC_MODE_BYPASS = 0 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 -MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 -MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' -MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' -MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 -MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 -MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 -MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' -MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_MODE_0', - 1: 'MPCC_GAMUT_REMAP_MODE_1', - 2: 'MPCC_GAMUT_REMAP_MODE_2', - 3: 'MPCC_GAMUT_REMAP_MODE_RSV', -} -MPCC_GAMUT_REMAP_MODE_0 = 0 -MPCC_GAMUT_REMAP_MODE_1 = 1 -MPCC_GAMUT_REMAP_MODE_2 = 2 -MPCC_GAMUT_REMAP_MODE_RSV = 3 -MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' -MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', -} -MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 -MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 -MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 -MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' -MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_OGAM_DIFFERENT_RGB', - 1: 'MPCC_OGAM_ALL_USE_R', -} -MPCC_OGAM_DIFFERENT_RGB = 0 -MPCC_OGAM_ALL_USE_R = 1 -MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' -MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_ENABLE_PWL', - 1: 'MPCC_OGAM_DISABLE_PWL', -} -MPCC_OGAM_ENABLE_PWL = 0 -MPCC_OGAM_DISABLE_PWL = 1 -MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', -} -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_RAMA_ACCESS', - 1: 'MPCC_OGAM_RAMB_ACCESS', -} -MPCC_OGAM_RAMA_ACCESS = 0 -MPCC_OGAM_RAMB_ACCESS = 1 -MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' -MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_OGAM_BLUE_LUT', - 1: 'MPCC_OGAM_GREEN_LUT', - 2: 'MPCC_OGAM_RED_LUT', -} -MPCC_OGAM_BLUE_LUT = 0 -MPCC_OGAM_GREEN_LUT = 1 -MPCC_OGAM_RED_LUT = 2 -MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' -MPCC_OGAM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_OGAM_DISABLE_DEBUG', - 1: 'MPCC_OGAM_ENABLE_DEBUG', -} -MPCC_OGAM_DISABLE_DEBUG = 0 -MPCC_OGAM_ENABLE_DEBUG = 1 -MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' -MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_OGAM_RAMA', - 1: 'MPCC_OGAM_RAMB', -} -MPCC_OGAM_RAMA = 0 -MPCC_OGAM_RAMB = 1 -MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_MODE_0', - 1: 'MPCC_OGAM_MODE_RSV1', - 2: 'MPCC_OGAM_MODE_2', - 3: 'MPCC_OGAM_MODE_RSV', -} -MPCC_OGAM_MODE_0 = 0 -MPCC_OGAM_MODE_RSV1 = 1 -MPCC_OGAM_MODE_2 = 2 -MPCC_OGAM_MODE_RSV = 3 -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_NUM_SEG' -MPCC_OGAM_NUM_SEG__enumvalues = { - 0: 'MPCC_OGAM_SEGMENTS_1', - 1: 'MPCC_OGAM_SEGMENTS_2', - 2: 'MPCC_OGAM_SEGMENTS_4', - 3: 'MPCC_OGAM_SEGMENTS_8', - 4: 'MPCC_OGAM_SEGMENTS_16', - 5: 'MPCC_OGAM_SEGMENTS_32', - 6: 'MPCC_OGAM_SEGMENTS_64', - 7: 'MPCC_OGAM_SEGMENTS_128', -} -MPCC_OGAM_SEGMENTS_1 = 0 -MPCC_OGAM_SEGMENTS_2 = 1 -MPCC_OGAM_SEGMENTS_4 = 2 -MPCC_OGAM_SEGMENTS_8 = 3 -MPCC_OGAM_SEGMENTS_16 = 4 -MPCC_OGAM_SEGMENTS_32 = 5 -MPCC_OGAM_SEGMENTS_64 = 6 -MPCC_OGAM_SEGMENTS_128 = 7 -MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', -} -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' -MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_36BIT', - 1: 'MPCC_MCM_3DLUT_30BIT', -} -MPCC_MCM_3DLUT_36BIT = 0 -MPCC_MCM_3DLUT_30BIT = 1 -MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' -MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_RAM0_ACCESS', - 1: 'MPCC_MCM_RAM1_ACCESS', - 2: 'MPCC_MCM_RAM2_ACCESS', - 3: 'MPCC_MCM_RAM3_ACCESS', -} -MPCC_MCM_RAM0_ACCESS = 0 -MPCC_MCM_RAM1_ACCESS = 1 -MPCC_MCM_RAM2_ACCESS = 2 -MPCC_MCM_RAM3_ACCESS = 3 -MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' -MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_17CUBE', - 1: 'MPCC_MCM_3DLUT_9CUBE', -} -MPCC_MCM_3DLUT_17CUBE = 0 -MPCC_MCM_3DLUT_9CUBE = 1 -MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' -MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', - 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', - 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', -} -MPCC_MCM_GAMMA_LUT_BYPASS = 0 -MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 -MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 -MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 -MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', -} -MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 -MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' -MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_RAMA', - 1: 'MPCC_MCM_GAMMA_LUT_RAMB', -} -MPCC_MCM_GAMMA_LUT_RAMA = 0 -MPCC_MCM_GAMMA_LUT_RAMB = 1 -MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM' -MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM' -MPCC_MCM_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMUT_REMAP_MODE_0', - 1: 'MPCC_MCM_GAMUT_REMAP_MODE_1', - 2: 'MPCC_MCM_GAMUT_REMAP_MODE_2', - 3: 'MPCC_MCM_GAMUT_REMAP_MODE_RSV', -} -MPCC_MCM_GAMUT_REMAP_MODE_0 = 0 -MPCC_MCM_GAMUT_REMAP_MODE_1 = 1 -MPCC_MCM_GAMUT_REMAP_MODE_2 = 2 -MPCC_MCM_GAMUT_REMAP_MODE_RSV = 3 -MPCC_MCM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' -MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', - 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', -} -MPCC_MCM_LUT_2_MODE_BYPASS = 0 -MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 -MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 -MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' -MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', - 1: 'MPCC_MCM_LUT_ALL_USE_R', -} -MPCC_MCM_LUT_DIFFERENT_RGB = 0 -MPCC_MCM_LUT_ALL_USE_R = 1 -MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' -MPCC_MCM_LUT_NUM_SEG__enumvalues = { - 0: 'MPCC_MCM_LUT_SEGMENTS_1', - 1: 'MPCC_MCM_LUT_SEGMENTS_2', - 2: 'MPCC_MCM_LUT_SEGMENTS_4', - 3: 'MPCC_MCM_LUT_SEGMENTS_8', - 4: 'MPCC_MCM_LUT_SEGMENTS_16', - 5: 'MPCC_MCM_LUT_SEGMENTS_32', - 6: 'MPCC_MCM_LUT_SEGMENTS_64', - 7: 'MPCC_MCM_LUT_SEGMENTS_128', -} -MPCC_MCM_LUT_SEGMENTS_1 = 0 -MPCC_MCM_LUT_SEGMENTS_2 = 1 -MPCC_MCM_LUT_SEGMENTS_4 = 2 -MPCC_MCM_LUT_SEGMENTS_8 = 3 -MPCC_MCM_LUT_SEGMENTS_16 = 4 -MPCC_MCM_LUT_SEGMENTS_32 = 5 -MPCC_MCM_LUT_SEGMENTS_64 = 6 -MPCC_MCM_LUT_SEGMENTS_128 = 7 -MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' -MPCC_MCM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_RAMA_ACCESS', - 1: 'MPCC_MCM_LUT_RAMB_ACCESS', -} -MPCC_MCM_LUT_RAMA_ACCESS = 0 -MPCC_MCM_LUT_RAMB_ACCESS = 1 -MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' -MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_BLUE_LUT', - 1: 'MPCC_MCM_LUT_GREEN_LUT', - 2: 'MPCC_MCM_LUT_RED_LUT', -} -MPCC_MCM_LUT_BLUE_LUT = 0 -MPCC_MCM_LUT_GREEN_LUT = 1 -MPCC_MCM_LUT_RED_LUT = 2 -MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_DBG' -MPCC_MCM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', - 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', -} -MPCC_MCM_LUT_DISABLE_DEBUG = 0 -MPCC_MCM_LUT_ENABLE_DEBUG = 1 -MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' -MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', - 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', - 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', -} -MPCC_MCM_MEM_PWR_FORCE_DIS = 0 -MPCC_MCM_MEM_PWR_FORCE_LS = 1 -MPCC_MCM_MEM_PWR_FORCE_DS = 2 -MPCC_MCM_MEM_PWR_FORCE_SD = 3 -MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' -MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_STATE_ON', - 1: 'MPCC_MCM_MEM_PWR_STATE_LS', - 2: 'MPCC_MCM_MEM_PWR_STATE_DS', - 3: 'MPCC_MCM_MEM_PWR_STATE_SD', -} -MPCC_MCM_MEM_PWR_STATE_ON = 0 -MPCC_MCM_MEM_PWR_STATE_LS = 1 -MPCC_MCM_MEM_PWR_STATE_DS = 2 -MPCC_MCM_MEM_PWR_STATE_SD = 3 -MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_BIT_DEPTH' -ENUM_DPG_BIT_DEPTH__enumvalues = { - 0: 'ENUM_DPG_BIT_DEPTH_6BPC', - 1: 'ENUM_DPG_BIT_DEPTH_8BPC', - 2: 'ENUM_DPG_BIT_DEPTH_10BPC', - 3: 'ENUM_DPG_BIT_DEPTH_12BPC', -} -ENUM_DPG_BIT_DEPTH_6BPC = 0 -ENUM_DPG_BIT_DEPTH_8BPC = 1 -ENUM_DPG_BIT_DEPTH_10BPC = 2 -ENUM_DPG_BIT_DEPTH_12BPC = 3 -ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' -ENUM_DPG_DYNAMIC_RANGE__enumvalues = { - 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', - 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', -} -ENUM_DPG_DYNAMIC_RANGE_VESA = 0 -ENUM_DPG_DYNAMIC_RANGE_CEA = 1 -ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_EN' -ENUM_DPG_EN__enumvalues = { - 0: 'ENUM_DPG_DISABLE', - 1: 'ENUM_DPG_ENABLE', -} -ENUM_DPG_DISABLE = 0 -ENUM_DPG_ENABLE = 1 -ENUM_DPG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_FIELD_POLARITY' -ENUM_DPG_FIELD_POLARITY__enumvalues = { - 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', -} -ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 -ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 -ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_MODE' -ENUM_DPG_MODE__enumvalues = { - 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 3: 'ENUM_DPG_MODE_VERTICAL_BAR', - 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', - 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', - 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', -} -ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 -ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 -ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 -ENUM_DPG_MODE_VERTICAL_BAR = 3 -ENUM_DPG_MODE_HORIZONTAL_BAR = 4 -ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 -ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 -ENUM_DPG_MODE_RGB_XR_BIAS = 7 -ENUM_DPG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_DIS_CTRL' -FMTMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', -} -FMTMEM_ENABLE_MEM_PWR_CTRL = 0 -FMTMEM_DISABLE_MEM_PWR_CTRL = 1 -FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' -FMTMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'FMTMEM_NO_FORCE_REQUEST', - 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', -} -FMTMEM_NO_FORCE_REQUEST = 0 -FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 -FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' -FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' -FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', -} -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' -FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' -FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { - 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', -} -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 -FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { - 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', -} -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' -FMT_CONTROL_PIXEL_ENCODING__enumvalues = { - 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', -} -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 -FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' -FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', -} -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 -FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' -FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', -} -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 -FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' -FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { - 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', -} -FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 -FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 -FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 -FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 -FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DYNAMIC_EXP_MODE' -FMT_DYNAMIC_EXP_MODE__enumvalues = { - 0: 'FMT_DYNAMIC_EXP_MODE_10to12', - 1: 'FMT_DYNAMIC_EXP_MODE_8to12', -} -FMT_DYNAMIC_EXP_MODE_10to12 = 0 -FMT_DYNAMIC_EXP_MODE_8to12 = 1 -FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' -FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', -} -FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 -FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 -FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_POWER_STATE_ENUM' -FMT_POWER_STATE_ENUM__enumvalues = { - 0: 'FMT_POWER_STATE_ENUM_ON', - 1: 'FMT_POWER_STATE_ENUM_LS', - 2: 'FMT_POWER_STATE_ENUM_DS', - 3: 'FMT_POWER_STATE_ENUM_SD', -} -FMT_POWER_STATE_ENUM_ON = 0 -FMT_POWER_STATE_ENUM_LS = 1 -FMT_POWER_STATE_ENUM_DS = 2 -FMT_POWER_STATE_ENUM_SD = 3 -FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' -FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', -} -FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 -FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 -FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', -} -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_MODE' -FMT_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_MODE_0', - 1: 'FMT_SPATIAL_DITHER_MODE_1', - 2: 'FMT_SPATIAL_DITHER_MODE_2', - 3: 'FMT_SPATIAL_DITHER_MODE_3', -} -FMT_SPATIAL_DITHER_MODE_0 = 0 -FMT_SPATIAL_DITHER_MODE_1 = 1 -FMT_SPATIAL_DITHER_MODE_2 = 2 -FMT_SPATIAL_DITHER_MODE_3 = 3 -FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' -FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { - 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', -} -FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 -FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 -FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum - -# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' -OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { - 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', -} -OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 -OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 -OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' -OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { - 0: 'OPP_PIPE_CLOCK_DISABLE', - 1: 'OPP_PIPE_CLOCK_ENABLE', -} -OPP_PIPE_CLOCK_DISABLE = 0 -OPP_PIPE_CLOCK_ENABLE = 1 -OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' -OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { - 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', -} -OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 -OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 -OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_CONT_EN' -OPP_PIPE_CRC_CONT_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', - 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', -} -OPP_PIPE_CRC_MODE_ONE_SHOT = 0 -OPP_PIPE_CRC_MODE_CONTINUOUS = 1 -OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_EN' -OPP_PIPE_CRC_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_DISABLE', - 1: 'OPP_PIPE_CRC_ENABLE', -} -OPP_PIPE_CRC_DISABLE = 0 -OPP_PIPE_CRC_ENABLE = 1 -OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' -OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', -} -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 -OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' -OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', - 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', -} -OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 -OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 -OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' -OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { - 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', -} -OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 -OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 -OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' -OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', -} -OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 -OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 -OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 -OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 -OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' -OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', -} -OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 -OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 -OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' -OPP_PIPE_CRC_STEREO_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', -} -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 -OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' -OPP_PIPE_CRC_STEREO_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', - 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', -} -OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 -OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 -OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' -OPP_TEST_CLK_SEL_CONTROL__enumvalues = { - 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', - 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', - 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', - 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', - 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 6: 'OPP_TEST_CLK_SEL_RESERVED0', - 7: 'OPP_TEST_CLK_SEL_RESERVED1', - 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', - 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', - 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 12: 'OPP_TEST_CLK_SEL_RESERVED2', - 13: 'OPP_TEST_CLK_SEL_RESERVED3', -} -OPP_TEST_CLK_SEL_DISPCLK_P = 0 -OPP_TEST_CLK_SEL_DISPCLK_R = 1 -OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 -OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 -OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 -OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 -OPP_TEST_CLK_SEL_RESERVED0 = 6 -OPP_TEST_CLK_SEL_RESERVED1 = 7 -OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 -OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 -OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 -OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 -OPP_TEST_CLK_SEL_RESERVED2 = 12 -OPP_TEST_CLK_SEL_RESERVED3 = 13 -OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' -OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { - 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', - 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', -} -OPP_TOP_CLOCK_DISABLED_STATUS = 0 -OPP_TOP_CLOCK_ENABLED_STATUS = 1 -OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' -OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { - 0: 'OPP_TOP_CLOCK_GATING_ENABLED', - 1: 'OPP_TOP_CLOCK_GATING_DISABLED', -} -OPP_TOP_CLOCK_GATING_ENABLED = 0 -OPP_TOP_CLOCK_GATING_DISABLED = 1 -OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_SEL' -MASTER_UPDATE_LOCK_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_SEL_0', - 1: 'MASTER_UPDATE_LOCK_SEL_1', - 2: 'MASTER_UPDATE_LOCK_SEL_2', - 3: 'MASTER_UPDATE_LOCK_SEL_3', - 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', -} -MASTER_UPDATE_LOCK_SEL_0 = 0 -MASTER_UPDATE_LOCK_SEL_1 = 1 -MASTER_UPDATE_LOCK_SEL_2 = 2 -MASTER_UPDATE_LOCK_SEL_3 = 3 -MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 -MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 -MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' -OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', -} -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', -} -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', -} -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' -OTG_CONTROL_OTG_MASTER_EN__enumvalues = { - 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', -} -OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 -OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 -OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' -OTG_CONTROL_OTG_OUT_MUX__enumvalues = { - 0: 'OTG_CONTROL_OTG_OUT_MUX_0', - 1: 'OTG_CONTROL_OTG_OUT_MUX_1', - 2: 'OTG_CONTROL_OTG_OUT_MUX_2', -} -OTG_CONTROL_OTG_OUT_MUX_0 = 0 -OTG_CONTROL_OTG_OUT_MUX_1 = 1 -OTG_CONTROL_OTG_OUT_MUX_2 = 2 -OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' -OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', -} -OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 -OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { - 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', -} -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' -OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' -OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' -OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', -} -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' -OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', -} -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', -} -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' -OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { - 0: 'OTG_DIG_UPDATE_VCOUNT_0', - 1: 'OTG_DIG_UPDATE_VCOUNT_1', -} -OTG_DIG_UPDATE_VCOUNT_0 = 0 -OTG_DIG_UPDATE_VCOUNT_1 = 1 -OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE' -OTG_DLPC_CONTROL_OTG_RESYNC_MODE__enumvalues = { - 0: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0', - 1: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1', -} -OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0 = 0 -OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1 = 1 -OTG_DLPC_CONTROL_OTG_RESYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { - 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', -} -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { - 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', -} -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { - 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', -} -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { - 0: 'DIG_UPDATE_EYE_SEL_BOTH', - 1: 'DIG_UPDATE_EYE_SEL_LEFT', - 2: 'DIG_UPDATE_EYE_SEL_RIGHT', -} -DIG_UPDATE_EYE_SEL_BOTH = 0 -DIG_UPDATE_EYE_SEL_LEFT = 1 -DIG_UPDATE_EYE_SEL_RIGHT = 2 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { - 0: 'DIG_UPDATE_FIELD_SEL_BOTH', - 1: 'DIG_UPDATE_FIELD_SEL_TOP', - 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', -} -DIG_UPDATE_FIELD_SEL_BOTH = 0 -DIG_UPDATE_FIELD_SEL_TOP = 1 -DIG_UPDATE_FIELD_SEL_BOTTOM = 2 -DIG_UPDATE_FIELD_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', -} -MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 -MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 -MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 -MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', -} -MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' -OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { - 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', - 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', -} -OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 -OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 -OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GSL_MASTER_MODE' -OTG_GSL_MASTER_MODE__enumvalues = { - 0: 'OTG_GSL_MASTER_MODE_0', - 1: 'OTG_GSL_MASTER_MODE_1', - 2: 'OTG_GSL_MASTER_MODE_2', - 3: 'OTG_GSL_MASTER_MODE_3', -} -OTG_GSL_MASTER_MODE_0 = 0 -OTG_GSL_MASTER_MODE_1 = 1 -OTG_GSL_MASTER_MODE_2 = 2 -OTG_GSL_MASTER_MODE_3 = 3 -OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_HORZ_REPETITION_COUNT' -OTG_HORZ_REPETITION_COUNT__enumvalues = { - 0: 'OTG_HORZ_REPETITION_COUNT_0', - 1: 'OTG_HORZ_REPETITION_COUNT_1', - 2: 'OTG_HORZ_REPETITION_COUNT_2', - 3: 'OTG_HORZ_REPETITION_COUNT_3', - 4: 'OTG_HORZ_REPETITION_COUNT_4', - 5: 'OTG_HORZ_REPETITION_COUNT_5', - 6: 'OTG_HORZ_REPETITION_COUNT_6', - 7: 'OTG_HORZ_REPETITION_COUNT_7', - 8: 'OTG_HORZ_REPETITION_COUNT_8', - 9: 'OTG_HORZ_REPETITION_COUNT_9', - 10: 'OTG_HORZ_REPETITION_COUNT_10', - 11: 'OTG_HORZ_REPETITION_COUNT_11', - 12: 'OTG_HORZ_REPETITION_COUNT_12', - 13: 'OTG_HORZ_REPETITION_COUNT_13', - 14: 'OTG_HORZ_REPETITION_COUNT_14', - 15: 'OTG_HORZ_REPETITION_COUNT_15', -} -OTG_HORZ_REPETITION_COUNT_0 = 0 -OTG_HORZ_REPETITION_COUNT_1 = 1 -OTG_HORZ_REPETITION_COUNT_2 = 2 -OTG_HORZ_REPETITION_COUNT_3 = 3 -OTG_HORZ_REPETITION_COUNT_4 = 4 -OTG_HORZ_REPETITION_COUNT_5 = 5 -OTG_HORZ_REPETITION_COUNT_6 = 6 -OTG_HORZ_REPETITION_COUNT_7 = 7 -OTG_HORZ_REPETITION_COUNT_8 = 8 -OTG_HORZ_REPETITION_COUNT_9 = 9 -OTG_HORZ_REPETITION_COUNT_10 = 10 -OTG_HORZ_REPETITION_COUNT_11 = 11 -OTG_HORZ_REPETITION_COUNT_12 = 12 -OTG_HORZ_REPETITION_COUNT_13 = 13 -OTG_HORZ_REPETITION_COUNT_14 = 14 -OTG_HORZ_REPETITION_COUNT_15 = 15 -OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_SYNC_A_POL' -OTG_H_SYNC_A_POL__enumvalues = { - 0: 'OTG_H_SYNC_A_POL_HIGH', - 1: 'OTG_H_SYNC_A_POL_LOW', -} -OTG_H_SYNC_A_POL_HIGH = 0 -OTG_H_SYNC_A_POL_LOW = 1 -OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE' -OTG_H_TIMING_DIV_MODE__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', - 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', - 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', - 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', -} -OTG_H_TIMING_DIV_MODE_NO_DIV = 0 -OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 -OTG_H_TIMING_DIV_MODE_RESERVED = 2 -OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 -OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' -OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_AUTO', - 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', -} -OTG_H_TIMING_DIV_MODE_AUTO = 0 -OTG_H_TIMING_DIV_MODE_NOAUTO = 1 -OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { - 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', -} -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' -OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', -} -OTG_MASTER_UPDATE_LOCK_DISABLE = 0 -OTG_MASTER_UPDATE_LOCK_ENABLE = 1 -OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' -OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', -} -OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 -OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 -OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', -} -OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 -OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { - 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', -} -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { - 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', -} -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', -} -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' -OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { - 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', -} -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', -} -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' -OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', -} -OTG_TRIGA_FREQUENCY_SELECT_0 = 0 -OTG_TRIGA_FREQUENCY_SELECT_1 = 1 -OTG_TRIGA_FREQUENCY_SELECT_2 = 2 -OTG_TRIGA_FREQUENCY_SELECT_3 = 3 -OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' -OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', -} -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' -OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', -} -OTG_TRIGB_FREQUENCY_SELECT_0 = 0 -OTG_TRIGB_FREQUENCY_SELECT_1 = 1 -OTG_TRIGB_FREQUENCY_SELECT_2 = 2 -OTG_TRIGB_FREQUENCY_SELECT_3 = 3 -OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' -OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { - 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', -} -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', -} -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', -} -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { - 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', -} -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' -OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { - 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', -} -OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 -OTG_VUPDATE_BLOCK_DISABLE_ON = 1 -OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_A_POL' -OTG_V_SYNC_A_POL__enumvalues = { - 0: 'OTG_V_SYNC_A_POL_HIGH', - 1: 'OTG_V_SYNC_A_POL_LOW', -} -OTG_V_SYNC_A_POL_HIGH = 0 -OTG_V_SYNC_A_POL_LOW = 1 -OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_MODE' -OTG_V_SYNC_MODE__enumvalues = { - 0: 'OTG_V_SYNC_MODE_HSYNC', - 1: 'OTG_V_SYNC_MODE_HBLANK', -} -OTG_V_SYNC_MODE_HSYNC = 0 -OTG_V_SYNC_MODE_HBLANK = 1 -OTG_V_SYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', -} -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { - 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', -} -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { - 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', -} -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_INT_TYPE' -DC_DMCUB_INT_TYPE__enumvalues = { - 0: 'INT_LEVEL', - 1: 'INT_PULSE', -} -INT_LEVEL = 0 -INT_PULSE = 1 -DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_TIMER_WINDOW' -DC_DMCUB_TIMER_WINDOW__enumvalues = { - 0: 'BITS_31_0', - 1: 'BITS_32_1', - 2: 'BITS_33_2', - 3: 'BITS_34_3', - 4: 'BITS_35_4', - 5: 'BITS_36_5', - 6: 'BITS_37_6', - 7: 'BITS_38_7', -} -BITS_31_0 = 0 -BITS_32_1 = 1 -BITS_33_2 = 2 -BITS_34_3 = 3 -BITS_35_4 = 4 -BITS_36_5 = 5 -BITS_37_6 = 6 -BITS_38_7 = 7 -DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'INVALID_REG_ACCESS_TYPE' -INVALID_REG_ACCESS_TYPE__enumvalues = { - 0: 'REG_UNALLOCATED_ADDR_WRITE', - 1: 'REG_UNALLOCATED_ADDR_READ', - 2: 'REG_VIRTUAL_WRITE', - 3: 'REG_VIRTUAL_READ', - 4: 'REG_SECURE_VIOLATE_WRITE', - 5: 'REG_SECURE_VIOLATE_READ', -} -REG_UNALLOCATED_ADDR_WRITE = 0 -REG_UNALLOCATED_ADDR_READ = 1 -REG_VIRTUAL_WRITE = 2 -REG_VIRTUAL_READ = 3 -REG_SECURE_VIOLATE_WRITE = 4 -REG_SECURE_VIOLATE_READ = 5 -INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' -DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 8: 'RESERVED_8', - 9: 'RESERVED_9', - 10: 'RESERVED_10', - 11: 'RESERVED_11', - 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 20: 'RESERVED_20', - 21: 'RESERVED_21', - 22: 'RESERVED_22', - 23: 'RESERVED_23', - 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 32: 'RESERVED_32', - 33: 'RESERVED_33', - 34: 'RESERVED_34', - 35: 'RESERVED_35', - 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 44: 'RESERVED_44', - 45: 'RESERVED_45', - 46: 'RESERVED_46', - 47: 'RESERVED_47', - 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 56: 'RESERVED_56', - 57: 'RESERVED_57', - 58: 'RESERVED_58', - 59: 'RESERVED_59', - 60: 'RESERVED_60', - 61: 'RESERVED_61', - 62: 'RESERVED_62', - 63: 'RESERVED_63', - 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 72: 'RESERVED_72', - 73: 'RESERVED_73', - 74: 'RESERVED_74', - 75: 'RESERVED_75', - 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 84: 'RESERVED_84', - 85: 'RESERVED_85', - 86: 'RESERVED_86', - 87: 'RESERVED_87', - 88: 'RESERVED_88', - 89: 'RESERVED_89', - 90: 'RESERVED_90', - 91: 'RESERVED_91', -} -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 -RESERVED_8 = 8 -RESERVED_9 = 9 -RESERVED_10 = 10 -RESERVED_11 = 11 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 -RESERVED_20 = 20 -RESERVED_21 = 21 -RESERVED_22 = 22 -RESERVED_23 = 23 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 -RESERVED_32 = 32 -RESERVED_33 = 33 -RESERVED_34 = 34 -RESERVED_35 = 35 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 -RESERVED_44 = 44 -RESERVED_45 = 45 -RESERVED_46 = 46 -RESERVED_47 = 47 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 -RESERVED_56 = 56 -RESERVED_57 = 57 -RESERVED_58 = 58 -RESERVED_59 = 59 -RESERVED_60 = 60 -RESERVED_61 = 61 -RESERVED_62 = 62 -RESERVED_63 = 63 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 -RESERVED_72 = 72 -RESERVED_73 = 73 -RESERVED_74 = 74 -RESERVED_75 = 75 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 -RESERVED_84 = 84 -RESERVED_85 = 85 -RESERVED_86 = 86 -RESERVED_87 = 87 -RESERVED_88 = 88 -RESERVED_89 = 89 -RESERVED_90 = 90 -RESERVED_91 = 91 -DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' -DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DMU_GPU_TIMER_START_0_END_27', - 1: 'DMU_GPU_TIMER_START_1_END_28', - 2: 'DMU_GPU_TIMER_START_2_END_29', - 3: 'DMU_GPU_TIMER_START_3_END_30', - 4: 'DMU_GPU_TIMER_START_4_END_31', - 5: 'DMU_GPU_TIMER_START_6_END_33', - 6: 'DMU_GPU_TIMER_START_8_END_35', - 7: 'DMU_GPU_TIMER_START_10_END_37', -} -DMU_GPU_TIMER_START_0_END_27 = 0 -DMU_GPU_TIMER_START_1_END_28 = 1 -DMU_GPU_TIMER_START_2_END_29 = 2 -DMU_GPU_TIMER_START_3_END_30 = 3 -DMU_GPU_TIMER_START_4_END_31 = 4 -DMU_GPU_TIMER_START_6_END_33 = 5 -DMU_GPU_TIMER_START_8_END_35 = 6 -DMU_GPU_TIMER_START_10_END_37 = 7 -DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_DEST' -IHC_INTERRUPT_DEST__enumvalues = { - 0: 'INTERRUPT_SENT_TO_IH', - 1: 'INTERRUPT_SENT_TO_DMCUB', -} -INTERRUPT_SENT_TO_IH = 0 -INTERRUPT_SENT_TO_DMCUB = 1 -IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' -IHC_INTERRUPT_LINE_STATUS__enumvalues = { - 0: 'INTERRUPT_LINE_NOT_ASSERTED', - 1: 'INTERRUPT_LINE_ASSERTED', -} -INTERRUPT_LINE_NOT_ASSERTED = 0 -INTERRUPT_LINE_ASSERTED = 1 -IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' -DC_SMU_INTERRUPT_ENABLE__enumvalues = { - 0: 'DISABLE_THE_INTERRUPT', - 1: 'ENABLE_THE_INTERRUPT', -} -DISABLE_THE_INTERRUPT = 0 -ENABLE_THE_INTERRUPT = 1 -DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_CLOCK_ON' -DMU_CLOCK_ON__enumvalues = { - 0: 'DMU_CLOCK_STATUS_ON', - 1: 'DMU_CLOCK_STATUS_OFF', -} -DMU_CLOCK_STATUS_ON = 0 -DMU_CLOCK_STATUS_OFF = 1 -DMU_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'SMU_INTR' -SMU_INTR__enumvalues = { - 0: 'SMU_MSG_INTR_NOOP', - 1: 'SET_SMU_MSG_INTR', -} -SMU_MSG_INTR_NOOP = 0 -SET_SMU_MSG_INTR = 1 -SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' -ALLOW_SR_ON_TRANS_REQ__enumvalues = { - 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', -} -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 -ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 -ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'AMCLOCK_ENABLE' -AMCLOCK_ENABLE__enumvalues = { - 0: 'ENABLE_AMCLK0', - 1: 'ENABLE_AMCLK1', -} -ENABLE_AMCLK0 = 0 -ENABLE_AMCLK1 = 1 -AMCLOCK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CLEAR_SMU_INTR' -CLEAR_SMU_INTR__enumvalues = { - 0: 'SMU_INTR_STATUS_NOOP', - 1: 'SMU_INTR_STATUS_CLEAR', -} -SMU_INTR_STATUS_NOOP = 0 -SMU_INTR_STATUS_CLEAR = 1 -CLEAR_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' -CLOCK_BRANCH_SOFT_RESET__enumvalues = { - 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', -} -CLOCK_BRANCH_SOFT_RESET_NOOP = 0 -CLOCK_BRANCH_SOFT_RESET_FORCE = 1 -CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' -DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', -} -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 -DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' -DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', -} -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 -DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_SEL' -DCCG_AUDIO_DTO_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', - 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', -} -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 -DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' -DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { - 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', -} -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 -DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_BLOCK_SEL' -DCCG_DBG_BLOCK_SEL__enumvalues = { - 0: 'DCCG_DBG_BLOCK_SEL_DCCG', - 1: 'DCCG_DBG_BLOCK_SEL_PMON', - 2: 'DCCG_DBG_BLOCK_SEL_PMON2', -} -DCCG_DBG_BLOCK_SEL_DCCG = 0 -DCCG_DBG_BLOCK_SEL_PMON = 1 -DCCG_DBG_BLOCK_SEL_PMON2 = 2 -DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_EN' -DCCG_DBG_EN__enumvalues = { - 0: 'DCCG_DBG_EN_DISABLE', - 1: 'DCCG_DBG_EN_ENABLE', -} -DCCG_DBG_EN_DISABLE = 0 -DCCG_DBG_EN_ENABLE = 1 -DCCG_DBG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DEEP_COLOR_CNTL' -DCCG_DEEP_COLOR_CNTL__enumvalues = { - 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', - 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', - 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', -} -DCCG_DEEP_COLOR_DTO_DISABLE = 0 -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 -DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' -DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', - 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', -} -DCCG_FIFO_ERRDET_OVR_DISABLE = 0 -DCCG_FIFO_ERRDET_OVR_ENABLE = 1 -DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_RESET' -DCCG_FIFO_ERRDET_RESET__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', - 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', -} -DCCG_FIFO_ERRDET_RESET_NOOP = 0 -DCCG_FIFO_ERRDET_RESET_FORCE = 1 -DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_STATE' -DCCG_FIFO_ERRDET_STATE__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', -} -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 -DCCG_FIFO_ERRDET_STATE_DETECTION = 1 -DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_HSYNC' -DCCG_PERF_MODE_HSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_HSYNC_NOOP', - 1: 'DCCG_PERF_MODE_HSYNC_START', -} -DCCG_PERF_MODE_HSYNC_NOOP = 0 -DCCG_PERF_MODE_HSYNC_START = 1 -DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_VSYNC' -DCCG_PERF_MODE_VSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_VSYNC_NOOP', - 1: 'DCCG_PERF_MODE_VSYNC_START', -} -DCCG_PERF_MODE_VSYNC_NOOP = 0 -DCCG_PERF_MODE_VSYNC_START = 1 -DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_OTG_SELECT' -DCCG_PERF_OTG_SELECT__enumvalues = { - 0: 'DCCG_PERF_SEL_OTG0', - 1: 'DCCG_PERF_SEL_OTG1', - 2: 'DCCG_PERF_SEL_OTG2', - 3: 'DCCG_PERF_SEL_OTG3', - 4: 'DCCG_PERF_SEL_RESERVED', -} -DCCG_PERF_SEL_OTG0 = 0 -DCCG_PERF_SEL_OTG1 = 1 -DCCG_PERF_SEL_OTG2 = 2 -DCCG_PERF_SEL_OTG3 = 3 -DCCG_PERF_SEL_RESERVED = 4 -DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_RUN' -DCCG_PERF_RUN__enumvalues = { - 0: 'DCCG_PERF_RUN_NOOP', - 1: 'DCCG_PERF_RUN_START', -} -DCCG_PERF_RUN_NOOP = 0 -DCCG_PERF_RUN_START = 1 -DCCG_PERF_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' -DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { - 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', -} -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 -DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_FIFO_ERROR' -DIO_FIFO_ERROR__enumvalues = { - 0: 'DIO_FIFO_ERROR_00', - 1: 'DIO_FIFO_ERROR_01', - 2: 'DIO_FIFO_ERROR_10', - 3: 'DIO_FIFO_ERROR_11', -} -DIO_FIFO_ERROR_00 = 0 -DIO_FIFO_ERROR_01 = 1 -DIO_FIFO_ERROR_10 = 2 -DIO_FIFO_ERROR_11 = 3 -DIO_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING' -DISABLE_CLOCK_GATING__enumvalues = { - 0: 'CLOCK_GATING_ENABLED', - 1: 'CLOCK_GATING_DISABLED', -} -CLOCK_GATING_ENABLED = 0 -CLOCK_GATING_DISABLED = 1 -DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' -DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { - 0: 'CLOCK_GATING_ENABLED_IN_DCO', - 1: 'CLOCK_GATING_DISABLED_IN_DCO', -} -CLOCK_GATING_ENABLED_IN_DCO = 0 -CLOCK_GATING_DISABLED_IN_DCO = 1 -DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' -DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { - 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', -} -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 -DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' -DISPCLK_FREQ_RAMP_DONE__enumvalues = { - 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', - 1: 'DISPCLK_FREQ_RAMP_COMPLETED', -} -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 -DISPCLK_FREQ_RAMP_COMPLETED = 1 -DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DPREFCLK_SRC_SEL' -DPREFCLK_SRC_SEL__enumvalues = { - 0: 'DPREFCLK_SRC_SEL_CK', - 1: 'DPREFCLK_SRC_SEL_P0PLL', - 2: 'DPREFCLK_SRC_SEL_P1PLL', - 3: 'DPREFCLK_SRC_SEL_P2PLL', -} -DPREFCLK_SRC_SEL_CK = 0 -DPREFCLK_SRC_SEL_P0PLL = 1 -DPREFCLK_SRC_SEL_P1PLL = 2 -DPREFCLK_SRC_SEL_P2PLL = 3 -DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DTO_DS_DISABLE' -DP_DTO_DS_DISABLE__enumvalues = { - 0: 'DP_DTO_DESPREAD_DISABLE', - 1: 'DP_DTO_DESPREAD_ENABLE', -} -DP_DTO_DESPREAD_DISABLE = 0 -DP_DTO_DESPREAD_ENABLE = 1 -DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_HW_CAL_ENABLE' -DS_HW_CAL_ENABLE__enumvalues = { - 0: 'DS_HW_CAL_DIS', - 1: 'DS_HW_CAL_EN', -} -DS_HW_CAL_DIS = 0 -DS_HW_CAL_EN = 1 -DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_REF_SRC' -DS_REF_SRC__enumvalues = { - 0: 'DS_REF_IS_XTALIN', - 1: 'DS_REF_IS_EXT_GENLOCK', - 2: 'DS_REF_IS_PCIE', -} -DS_REF_IS_XTALIN = 0 -DS_REF_IS_EXT_GENLOCK = 1 -DS_REF_IS_PCIE = 2 -DS_REF_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_ENABLE_RST' -DVO_ENABLE_RST__enumvalues = { - 0: 'DVO_ENABLE_RST_DISABLE', - 1: 'DVO_ENABLE_RST_ENABLE', -} -DVO_ENABLE_RST_DISABLE = 0 -DVO_ENABLE_RST_ENABLE = 1 -DVO_ENABLE_RST = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE' -ENABLE__enumvalues = { - 0: 'DISABLE_THE_FEATURE', - 1: 'ENABLE_THE_FEATURE', -} -DISABLE_THE_FEATURE = 0 -ENABLE_THE_FEATURE = 1 -ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_CLOCK' -ENABLE_CLOCK__enumvalues = { - 0: 'ENABLE_THE_REFCLK', - 1: 'ENABLE_THE_FUNC_CLOCK', -} -ENABLE_THE_REFCLK = 0 -ENABLE_THE_FUNC_CLOCK = 1 -ENABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_DISABLE_CLOCK' -FORCE_DISABLE_CLOCK__enumvalues = { - 0: 'NOT_FORCE_THE_CLOCK_DISABLED', - 1: 'FORCE_THE_CLOCK_DISABLED', -} -NOT_FORCE_THE_CLOCK_DISABLED = 0 -FORCE_THE_CLOCK_DISABLED = 1 -FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMICHARCLK_SRC_SEL' -HDMICHARCLK_SRC_SEL__enumvalues = { - 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', - 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', - 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', - 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', - 4: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', -} -HDMICHARCLK_SRC_SEL_UNIPHYA = 0 -HDMICHARCLK_SRC_SEL_UNIPHYB = 1 -HDMICHARCLK_SRC_SEL_UNIPHYC = 2 -HDMICHARCLK_SRC_SEL_UNIPHYD = 3 -HDMICHARCLK_SRC_SEL_SRC_RESERVED = 4 -HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMISTREAMCLK_SRC_SEL' -HDMISTREAMCLK_SRC_SEL__enumvalues = { - 0: 'SEL_DTBCLK_P0', - 1: 'SEL_DTBCLK_P1', - 2: 'SEL_DTBCLK_P2', - 3: 'SEL_DTBCLK_P3', -} -SEL_DTBCLK_P0 = 0 -SEL_DTBCLK_P1 = 1 -SEL_DTBCLK_P2 = 2 -SEL_DTBCLK_P3 = 3 -HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'JITTER_REMOVE_DISABLE' -JITTER_REMOVE_DISABLE__enumvalues = { - 0: 'ENABLE_JITTER_REMOVAL', - 1: 'DISABLE_JITTER_REMOVAL', -} -ENABLE_JITTER_REMOVAL = 0 -DISABLE_JITTER_REMOVAL = 1 -JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_ADD_PIXEL' -OTG_ADD_PIXEL__enumvalues = { - 0: 'OTG_ADD_PIXEL_NOOP', - 1: 'OTG_ADD_PIXEL_FORCE', -} -OTG_ADD_PIXEL_NOOP = 0 -OTG_ADD_PIXEL_FORCE = 1 -OTG_ADD_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DROP_PIXEL' -OTG_DROP_PIXEL__enumvalues = { - 0: 'OTG_DROP_PIXEL_NOOP', - 1: 'OTG_DROP_PIXEL_FORCE', -} -OTG_DROP_PIXEL_NOOP = 0 -OTG_DROP_PIXEL_FORCE = 1 -OTG_DROP_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_EN' -PHYSYMCLK_FORCE_EN__enumvalues = { - 0: 'PHYSYMCLK_FORCE_EN_DISABLE', - 1: 'PHYSYMCLK_FORCE_EN_ENABLE', -} -PHYSYMCLK_FORCE_EN_DISABLE = 0 -PHYSYMCLK_FORCE_EN_ENABLE = 1 -PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' -PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { - 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', - 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', - 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', -} -PHYSYMCLK_FORCE_SRC_SYMCLK = 0 -PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 -PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 -PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' -PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', -} -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 -PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' -PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', - 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', -} -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 -PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' -PIPE_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', - 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', -} -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 -PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 -PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 -PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PLL_CFG_IF_SOFT_RESET' -PLL_CFG_IF_SOFT_RESET__enumvalues = { - 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', - 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', -} -PLL_CFG_IF_SOFT_RESET_NOOP = 0 -PLL_CFG_IF_SOFT_RESET_FORCE = 1 -PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_SRC' -SYMCLK_FE_SRC__enumvalues = { - 0: 'SYMCLK_FE_SRC_UNIPHYA', - 1: 'SYMCLK_FE_SRC_UNIPHYB', - 2: 'SYMCLK_FE_SRC_UNIPHYC', - 3: 'SYMCLK_FE_SRC_UNIPHYD', - 4: 'SYMCLK_FE_SRC_RESERVED', -} -SYMCLK_FE_SRC_UNIPHYA = 0 -SYMCLK_FE_SRC_UNIPHYB = 1 -SYMCLK_FE_SRC_UNIPHYC = 2 -SYMCLK_FE_SRC_UNIPHYD = 3 -SYMCLK_FE_SRC_RESERVED = 4 -SYMCLK_FE_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_DIV_SEL' -TEST_CLK_DIV_SEL__enumvalues = { - 0: 'NO_DIV', - 1: 'DIV_2', - 2: 'DIV_4', - 3: 'DIV_8', -} -NO_DIV = 0 -DIV_2 = 1 -DIV_4 = 2 -DIV_8 = 3 -TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_LATCH_MASK' -VSYNC_CNT_LATCH_MASK__enumvalues = { - 0: 'VSYNC_CNT_LATCH_MASK_0', - 1: 'VSYNC_CNT_LATCH_MASK_1', -} -VSYNC_CNT_LATCH_MASK_0 = 0 -VSYNC_CNT_LATCH_MASK_1 = 1 -VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_RESET_SEL' -VSYNC_CNT_RESET_SEL__enumvalues = { - 0: 'VSYNC_CNT_RESET_SEL_0', - 1: 'VSYNC_CNT_RESET_SEL_1', -} -VSYNC_CNT_RESET_SEL_0 = 0 -VSYNC_CNT_RESET_SEL_1 = 1 -VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' -XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', - 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', -} -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 -XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 -XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_SEL' -XTAL_REF_SEL__enumvalues = { - 0: 'XTAL_REF_SEL_1X', - 1: 'XTAL_REF_SEL_2X', -} -XTAL_REF_SEL_1X = 0 -XTAL_REF_SEL_2X = 1 -XTAL_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_CUR_DISP' -DPHY_8B10B_CUR_DISP__enumvalues = { - 0: 'DPHY_8B10B_CUR_DISP_ZERO', - 1: 'DPHY_8B10B_CUR_DISP_ONE', -} -DPHY_8B10B_CUR_DISP_ZERO = 0 -DPHY_8B10B_CUR_DISP_ONE = 1 -DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_RESET' -DPHY_8B10B_RESET__enumvalues = { - 0: 'DPHY_8B10B_NOT_RESET', - 1: 'DPHY_8B10B_RESETET', -} -DPHY_8B10B_NOT_RESET = 0 -DPHY_8B10B_RESETET = 1 -DPHY_8B10B_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE0' -DPHY_ATEST_SEL_LANE0__enumvalues = { - 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE0_REG_PATTERN', -} -DPHY_ATEST_LANE0_PRBS_PATTERN = 0 -DPHY_ATEST_LANE0_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE1' -DPHY_ATEST_SEL_LANE1__enumvalues = { - 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE1_REG_PATTERN', -} -DPHY_ATEST_LANE1_PRBS_PATTERN = 0 -DPHY_ATEST_LANE1_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE2' -DPHY_ATEST_SEL_LANE2__enumvalues = { - 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE2_REG_PATTERN', -} -DPHY_ATEST_LANE2_PRBS_PATTERN = 0 -DPHY_ATEST_LANE2_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE3' -DPHY_ATEST_SEL_LANE3__enumvalues = { - 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE3_REG_PATTERN', -} -DPHY_ATEST_LANE3_PRBS_PATTERN = 0 -DPHY_ATEST_LANE3_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_BYPASS' -DPHY_BYPASS__enumvalues = { - 0: 'DPHY_8B10B_OUTPUT', - 1: 'DPHY_DBG_OUTPUT', -} -DPHY_8B10B_OUTPUT = 0 -DPHY_DBG_OUTPUT = 1 -DPHY_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_CONT_EN' -DPHY_CRC_CONT_EN__enumvalues = { - 0: 'DPHY_CRC_ONE_SHOT', - 1: 'DPHY_CRC_CONTINUOUS', -} -DPHY_CRC_ONE_SHOT = 0 -DPHY_CRC_CONTINUOUS = 1 -DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_EN' -DPHY_CRC_EN__enumvalues = { - 0: 'DPHY_CRC_DISABLED', - 1: 'DPHY_CRC_ENABLED', -} -DPHY_CRC_DISABLED = 0 -DPHY_CRC_ENABLED = 1 -DPHY_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_FIELD' -DPHY_CRC_FIELD__enumvalues = { - 0: 'DPHY_CRC_START_FROM_TOP_FIELD', - 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', -} -DPHY_CRC_START_FROM_TOP_FIELD = 0 -DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 -DPHY_CRC_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' -DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { - 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', - 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', -} -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 -DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 -DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_SEL' -DPHY_CRC_SEL__enumvalues = { - 0: 'DPHY_CRC_LANE0_SELECTED', - 1: 'DPHY_CRC_LANE1_SELECTED', - 2: 'DPHY_CRC_LANE2_SELECTED', - 3: 'DPHY_CRC_LANE3_SELECTED', -} -DPHY_CRC_LANE0_SELECTED = 0 -DPHY_CRC_LANE1_SELECTED = 1 -DPHY_CRC_LANE2_SELECTED = 2 -DPHY_CRC_LANE3_SELECTED = 3 -DPHY_CRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_ENABLE' -DPHY_FEC_ENABLE__enumvalues = { - 0: 'DPHY_FEC_DISABLED', - 1: 'DPHY_FEC_ENABLED', -} -DPHY_FEC_DISABLED = 0 -DPHY_FEC_ENABLED = 1 -DPHY_FEC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_READY' -DPHY_FEC_READY__enumvalues = { - 0: 'DPHY_FEC_READY_EN', - 1: 'DPHY_FEC_READY_DIS', -} -DPHY_FEC_READY_EN = 0 -DPHY_FEC_READY_DIS = 1 -DPHY_FEC_READY = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_LOAD_BS_COUNT_START' -DPHY_LOAD_BS_COUNT_START__enumvalues = { - 0: 'DPHY_LOAD_BS_COUNT_STARTED', - 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', -} -DPHY_LOAD_BS_COUNT_STARTED = 0 -DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 -DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_EN' -DPHY_PRBS_EN__enumvalues = { - 0: 'DPHY_PRBS_DISABLE', - 1: 'DPHY_PRBS_ENABLE', -} -DPHY_PRBS_DISABLE = 0 -DPHY_PRBS_ENABLE = 1 -DPHY_PRBS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_SEL' -DPHY_PRBS_SEL__enumvalues = { - 0: 'DPHY_PRBS7_SELECTED', - 1: 'DPHY_PRBS23_SELECTED', - 2: 'DPHY_PRBS11_SELECTED', -} -DPHY_PRBS7_SELECTED = 0 -DPHY_PRBS23_SELECTED = 1 -DPHY_PRBS11_SELECTED = 2 -DPHY_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' -DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { - 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 1: 'DPHY_FAST_TRAINING_CAPABLE', -} -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 -DPHY_FAST_TRAINING_CAPABLE = 1 -DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SKEW_BYPASS' -DPHY_SKEW_BYPASS__enumvalues = { - 0: 'DPHY_WITH_SKEW', - 1: 'DPHY_NO_SKEW', -} -DPHY_WITH_SKEW = 0 -DPHY_NO_SKEW = 1 -DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { - 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', -} -DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SW_FAST_TRAINING_START' -DPHY_SW_FAST_TRAINING_START__enumvalues = { - 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 1: 'DPHY_SW_FAST_TRAINING_STARTED', -} -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 -DPHY_SW_FAST_TRAINING_STARTED = 1 -DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' -DPHY_TRAINING_PATTERN_SEL__enumvalues = { - 0: 'DPHY_TRAINING_PATTERN_1', - 1: 'DPHY_TRAINING_PATTERN_2', - 2: 'DPHY_TRAINING_PATTERN_3', - 3: 'DPHY_TRAINING_PATTERN_4', -} -DPHY_TRAINING_PATTERN_1 = 0 -DPHY_TRAINING_PATTERN_2 = 1 -DPHY_TRAINING_PATTERN_3 = 2 -DPHY_TRAINING_PATTERN_4 = 3 -DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPONENT_DEPTH' -DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_COMPONENT_DEPTH_6BPC', - 1: 'DP_COMPONENT_DEPTH_8BPC', - 2: 'DP_COMPONENT_DEPTH_10BPC', - 3: 'DP_COMPONENT_DEPTH_12BPC', - 4: 'DP_COMPONENT_DEPTH_16BPC', -} -DP_COMPONENT_DEPTH_6BPC = 0 -DP_COMPONENT_DEPTH_8BPC = 1 -DP_COMPONENT_DEPTH_10BPC = 2 -DP_COMPONENT_DEPTH_12BPC = 3 -DP_COMPONENT_DEPTH_16BPC = 4 -DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPRESSED_PIXEL_FORMAT' -DP_COMPRESSED_PIXEL_FORMAT__enumvalues = { - 0: 'DP_DSC_444_S422', - 1: 'DP_DSC_N422_N420', -} -DP_DSC_444_S422 = 0 -DP_DSC_N422_N420 = 1 -DP_COMPRESSED_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' -DP_DPHY_8B10B_EXT_DISP__enumvalues = { - 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', -} -DP_DPHY_8B10B_EXT_DISP_ZERO = 0 -DP_DPHY_8B10B_EXT_DISP_ONE = 1 -DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' -DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' -DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', -} -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' -DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { - 0: 'DP_DPHY_HBR2_PASS_THROUGH', - 1: 'DP_DPHY_HBR2_PATTERN_1', - 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', - 3: 'DP_DPHY_HBR2_PATTERN_3', - 6: 'DP_DPHY_HBR2_PATTERN_2_POS', -} -DP_DPHY_HBR2_PASS_THROUGH = 0 -DP_DPHY_HBR2_PATTERN_1 = 1 -DP_DPHY_HBR2_PATTERN_2_NEG = 2 -DP_DPHY_HBR2_PATTERN_3 = 3 -DP_DPHY_HBR2_PATTERN_2_POS = 6 -DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_COMPLETE' -DP_LINK_TRAINING_COMPLETE__enumvalues = { - 0: 'DP_LINK_TRAINING_NOT_COMPLETE', - 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', -} -DP_LINK_TRAINING_NOT_COMPLETE = 0 -DP_LINK_TRAINING_ALREADY_COMPLETE = 1 -DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' -DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { - 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', -} -DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 -DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 -DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_ML_PHY_SEQ_MODE' -DP_ML_PHY_SEQ_MODE__enumvalues = { - 0: 'DP_ML_PHY_SEQ_LINE_NUM', - 1: 'DP_ML_PHY_SEQ_IMMEDIATE', -} -DP_ML_PHY_SEQ_LINE_NUM = 0 -DP_ML_PHY_SEQ_IMMEDIATE = 1 -DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' -DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { - 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', - 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', -} -MSA_V_TIMING_OVERRIDE_DISABLED = 0 -MSA_V_TIMING_OVERRIDE_ENABLED = 1 -DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_BLANK_CODE' -DP_MSE_BLANK_CODE__enumvalues = { - 0: 'DP_MSE_BLANK_CODE_SF_FILLED', - 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', -} -DP_MSE_BLANK_CODE_SF_FILLED = 0 -DP_MSE_BLANK_CODE_ZERO_FILLED = 1 -DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_LINK_LINE' -DP_MSE_LINK_LINE__enumvalues = { - 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', - 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', - 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', - 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', -} -DP_MSE_LINK_LINE_32_MTP_LONG = 0 -DP_MSE_LINK_LINE_64_MTP_LONG = 1 -DP_MSE_LINK_LINE_128_MTP_LONG = 2 -DP_MSE_LINK_LINE_256_MTP_LONG = 3 -DP_MSE_LINK_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_TIMESTAMP_MODE' -DP_MSE_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', -} -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 -DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_ZERO_ENCODER' -DP_MSE_ZERO_ENCODER__enumvalues = { - 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', - 1: 'DP_MSE_ZERO_FE_ENCODER', -} -DP_MSE_NOT_ZERO_FE_ENCODER = 0 -DP_MSE_ZERO_FE_ENCODER = 1 -DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' -DP_MSO_NUM_OF_SST_LINKS__enumvalues = { - 0: 'DP_MSO_ONE_SSTLINK', - 1: 'DP_MSO_TWO_SSTLINK', - 2: 'DP_MSO_FOUR_SSTLINK', -} -DP_MSO_ONE_SSTLINK = 0 -DP_MSO_TWO_SSTLINK = 1 -DP_MSO_FOUR_SSTLINK = 2 -DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING' -DP_PIXEL_ENCODING__enumvalues = { - 0: 'DP_PIXEL_ENCODING_RGB_YCBCR444', - 1: 'DP_PIXEL_ENCODING_YCBCR422', - 2: 'DP_PIXEL_ENCODING_YCBCR420', - 3: 'DP_PIXEL_ENCODING_Y_ONLY', -} -DP_PIXEL_ENCODING_RGB_YCBCR444 = 0 -DP_PIXEL_ENCODING_YCBCR422 = 1 -DP_PIXEL_ENCODING_YCBCR420 = 2 -DP_PIXEL_ENCODING_Y_ONLY = 3 -DP_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING_TYPE' -DP_PIXEL_ENCODING_TYPE__enumvalues = { - 0: 'DP_PIXEL_ENCODING_UNCOMPRESSED', - 1: 'DP_PIXEL_ENCODING_COMPRESSED', -} -DP_PIXEL_ENCODING_UNCOMPRESSED = 0 -DP_PIXEL_ENCODING_COMPRESSED = 1 -DP_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_PRIORITY' -DP_SEC_ASP_PRIORITY__enumvalues = { - 0: 'DP_SEC_ASP_LOW_PRIORITY', - 1: 'DP_SEC_ASP_HIGH_PRIORITY', -} -DP_SEC_ASP_LOW_PRIORITY = 0 -DP_SEC_ASP_HIGH_PRIORITY = 1 -DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_AUDIO_MUTE' -DP_SEC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', - 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', -} -DP_SEC_AUDIO_MUTE_HW_CTRL = 0 -DP_SEC_AUDIO_MUTE_SW_CTRL = 1 -DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_COLLISION_ACK' -DP_SEC_COLLISION_ACK__enumvalues = { - 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', - 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', -} -DP_SEC_COLLISION_ACK_NO_EFFECT = 0 -DP_SEC_COLLISION_ACK_CLR_FLAG = 1 -DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_PRIORITY' -DP_SEC_GSP0_PRIORITY__enumvalues = { - 0: 'SEC_GSP0_PRIORITY_LOW', - 1: 'SEC_GSP0_PRIORITY_HIGH', -} -SEC_GSP0_PRIORITY_LOW = 0 -SEC_GSP0_PRIORITY_HIGH = 1 -DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND' -DP_SEC_GSP_SEND__enumvalues = { - 0: 'NOT_SENT', - 1: 'FORCE_SENT', -} -NOT_SENT = 0 -FORCE_SENT = 1 -DP_SEC_GSP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' -DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { - 0: 'SEND_AT_LINK_NUMBER', - 1: 'SEND_AT_EARLIEST_TIME', -} -SEND_AT_LINK_NUMBER = 0 -SEND_AT_EARLIEST_TIME = 1 -DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_PPS' -DP_SEC_GSP_SEND_PPS__enumvalues = { - 0: 'SEND_NORMAL_PACKET', - 1: 'SEND_PPS_PACKET', -} -SEND_NORMAL_PACKET = 0 -SEND_PPS_PACKET = 1 -DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_LINE_REFERENCE' -DP_SEC_LINE_REFERENCE__enumvalues = { - 0: 'REFER_TO_DP_SOF', - 1: 'REFER_TO_OTG_SOF', -} -REFER_TO_DP_SOF = 0 -REFER_TO_OTG_SOF = 1 -DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_TIMESTAMP_MODE' -DP_SEC_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', -} -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 -DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OUTPUT_PIXEL_PER_CYCLE' -DP_STEER_OUTPUT_PIXEL_PER_CYCLE__enumvalues = { - 0: 'DP_STEER_1_PIX_PER_CYCLE', - 1: 'DP_STEER_2_PIX_PER_CYCLE', - 2: 'DP_STEER_4_PIX_PER_CYCLE', - 3: 'DP_STEER_8_PIX_PER_CYCLE', -} -DP_STEER_1_PIX_PER_CYCLE = 0 -DP_STEER_2_PIX_PER_CYCLE = 1 -DP_STEER_4_PIX_PER_CYCLE = 2 -DP_STEER_8_PIX_PER_CYCLE = 3 -DP_STEER_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_ACK' -DP_STEER_OVERFLOW_ACK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_MASK' -DP_STEER_OVERFLOW_MASK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_MASKED', - 1: 'DP_STEER_OVERFLOW_UNMASK', -} -DP_STEER_OVERFLOW_MASKED = 0 -DP_STEER_OVERFLOW_UNMASK = 1 -DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SYNC_POLARITY' -DP_SYNC_POLARITY__enumvalues = { - 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', - 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', -} -DP_SYNC_POLARITY_ACTIVE_HIGH = 0 -DP_SYNC_POLARITY_ACTIVE_LOW = 1 -DP_SYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_TU_OVERFLOW_ACK' -DP_TU_OVERFLOW_ACK__enumvalues = { - 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_UDI_LANES' -DP_UDI_LANES__enumvalues = { - 0: 'DP_UDI_1_LANE', - 1: 'DP_UDI_2_LANES', - 2: 'DP_UDI_LANES_RESERVED', - 3: 'DP_UDI_4_LANES', -} -DP_UDI_1_LANE = 0 -DP_UDI_2_LANES = 1 -DP_UDI_LANES_RESERVED = 2 -DP_UDI_4_LANES = 3 -DP_UDI_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' -DP_VID_ENHANCED_FRAME_MODE__enumvalues = { - 0: 'VID_NORMAL_FRAME_MODE', - 1: 'VID_ENHANCED_MODE', -} -VID_NORMAL_FRAME_MODE = 0 -VID_ENHANCED_MODE = 1 -DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' -DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { - 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', -} -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 -DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_GEN_EN' -DP_VID_M_N_GEN_EN__enumvalues = { - 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', - 1: 'DP_VID_M_N_CALC_AUTO', -} -DP_VID_M_N_PROGRAMMED_VIA_REG = 0 -DP_VID_M_N_CALC_AUTO = 1 -DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_N_INTERVAL' -DP_VID_N_INTERVAL__enumvalues = { - 0: 'DP_VID_1X_Nvid', - 1: 'DP_VID_2X_Nvid', - 2: 'DP_VID_4X_Nvid', - 3: 'DP_VID_8X_Nvid', -} -DP_VID_1X_Nvid = 0 -DP_VID_2X_Nvid = 1 -DP_VID_4X_Nvid = 2 -DP_VID_8X_Nvid = 3 -DP_VID_N_INTERVAL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' -DP_VID_STREAM_DISABLE_ACK__enumvalues = { - 0: 'ID_STREAM_DISABLE_NO_ACK', - 1: 'ID_STREAM_DISABLE_ACKED', -} -ID_STREAM_DISABLE_NO_ACK = 0 -ID_STREAM_DISABLE_ACKED = 1 -DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' -DP_VID_STREAM_DISABLE_MASK__enumvalues = { - 0: 'VID_STREAM_DISABLE_MASKED', - 1: 'VID_STREAM_DISABLE_UNMASK', -} -VID_STREAM_DISABLE_MASKED = 0 -VID_STREAM_DISABLE_UNMASK = 1 -DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DIS_DEFER' -DP_VID_STREAM_DIS_DEFER__enumvalues = { - 0: 'DP_VID_STREAM_DIS_NO_DEFER', - 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', -} -DP_VID_STREAM_DIS_NO_DEFER = 0 -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 -DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_VBID_FIELD_POL' -DP_VID_VBID_FIELD_POL__enumvalues = { - 0: 'DP_VID_VBID_FIELD_POL_NORMAL', - 1: 'DP_VID_VBID_FIELD_POL_INV', -} -DP_VID_VBID_FIELD_POL_NORMAL = 0 -DP_VID_VBID_FIELD_POL_INV = 1 -DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum - -# values for enumeration 'FEC_ACTIVE_STATUS' -FEC_ACTIVE_STATUS__enumvalues = { - 0: 'DPHY_FEC_NOT_ACTIVE', - 1: 'DPHY_FEC_ACTIVE', -} -DPHY_FEC_NOT_ACTIVE = 0 -DPHY_FEC_ACTIVE = 1 -FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' -DIG_BE_CNTL_HPD_SELECT__enumvalues = { - 0: 'DIG_BE_CNTL_HPD1', - 1: 'DIG_BE_CNTL_HPD2', - 2: 'DIG_BE_CNTL_HPD3', - 3: 'DIG_BE_CNTL_HPD4', - 4: 'DIG_BE_CNTL_NO_HPD', -} -DIG_BE_CNTL_HPD1 = 0 -DIG_BE_CNTL_HPD2 = 1 -DIG_BE_CNTL_HPD3 = 2 -DIG_BE_CNTL_HPD4 = 3 -DIG_BE_CNTL_NO_HPD = 4 -DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_MODE' -DIG_BE_CNTL_MODE__enumvalues = { - 0: 'DIG_BE_DP_SST_MODE', - 1: 'DIG_BE_RESERVED1', - 2: 'DIG_BE_TMDS_DVI_MODE', - 3: 'DIG_BE_TMDS_HDMI_MODE', - 4: 'DIG_BE_RESERVED4', - 5: 'DIG_BE_DP_MST_MODE', - 6: 'DIG_BE_RESERVED2', - 7: 'DIG_BE_RESERVED3', -} -DIG_BE_DP_SST_MODE = 0 -DIG_BE_RESERVED1 = 1 -DIG_BE_TMDS_DVI_MODE = 2 -DIG_BE_TMDS_HDMI_MODE = 3 -DIG_BE_RESERVED4 = 4 -DIG_BE_DP_MST_MODE = 5 -DIG_BE_RESERVED2 = 6 -DIG_BE_RESERVED3 = 7 -DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' -DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_OFF', - 1: 'DIG_DIGITAL_BYPASS_ON', -} -DIG_DIGITAL_BYPASS_OFF = 0 -DIG_DIGITAL_BYPASS_ON = 1 -DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' -DIG_DIGITAL_BYPASS_SEL__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', -} -DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 -DIG_DIGITAL_BYPASS_SEL_36BPP = 1 -DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 -DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 -DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 -DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 -DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 -DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' -DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { - 0: 'DIG_FE_SOURCE_FROM_OTG0', - 1: 'DIG_FE_SOURCE_FROM_OTG1', - 2: 'DIG_FE_SOURCE_FROM_OTG2', - 3: 'DIG_FE_SOURCE_FROM_OTG3', - 4: 'DIG_FE_SOURCE_RESERVED', -} -DIG_FE_SOURCE_FROM_OTG0 = 0 -DIG_FE_SOURCE_FROM_OTG1 = 1 -DIG_FE_SOURCE_FROM_OTG2 = 2 -DIG_FE_SOURCE_FROM_OTG3 = 3 -DIG_FE_SOURCE_RESERVED = 4 -DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' -DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { - 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', - 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', - 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', - 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', - 4: 'DIG_FE_STEREOSYNC_RESERVED', -} -DIG_FE_STEREOSYNC_FROM_OTG0 = 0 -DIG_FE_STEREOSYNC_FROM_OTG1 = 1 -DIG_FE_STEREOSYNC_FROM_OTG2 = 2 -DIG_FE_STEREOSYNC_FROM_OTG3 = 3 -DIG_FE_STEREOSYNC_RESERVED = 4 -DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', - 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', -} -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 -DIG_FIFO_FORCE_RECOMP_MINMAX = 1 -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', -} -DIG_FIFO_USE_OVERWRITE_LEVEL = 0 -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' -DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', -} -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 -DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE' -DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__enumvalues = { - 0: 'DIG_FIFO_1_PIX_PER_CYCLE', - 1: 'DIG_FIFO_2_PIX_PER_CYCLE', - 2: 'DIG_FIFO_4_PIX_PER_CYCLE', - 3: 'DIG_FIFO_8_PIX_PER_CYCLE', -} -DIG_FIFO_1_PIX_PER_CYCLE = 0 -DIG_FIFO_2_PIX_PER_CYCLE = 1 -DIG_FIFO_4_PIX_PER_CYCLE = 2 -DIG_FIFO_8_PIX_PER_CYCLE = 3 -DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DIG_FIFO_NO_ERROR_OCCURRED', - 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', - 2: 'DIG_FIFO_OVERFLOW_OCCURRED', -} -DIG_FIFO_NO_ERROR_OCCURRED = 0 -DIG_FIFO_UNDERFLOW_OCCURRED = 1 -DIG_FIFO_OVERFLOW_OCCURRED = 2 -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' -DIG_FIFO_READ_CLOCK_SRC__enumvalues = { - 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', -} -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 -DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_MODE' -DIG_MODE__enumvalues = { - 0: 'DP_SST_MODE', - 1: 'RESERVED1', - 2: 'TMDS_DVI_MODE', - 3: 'TMDS_HDMI_MODE', - 4: 'RESERVED4', - 5: 'DP_MST_MODE', - 6: 'RESERVED2', - 7: 'RESERVED3', -} -DP_SST_MODE = 0 -RESERVED1 = 1 -TMDS_DVI_MODE = 2 -TMDS_HDMI_MODE = 3 -RESERVED4 = 4 -DP_MST_MODE = 5 -RESERVED2 = 6 -RESERVED3 = 7 -DIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' -DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_ON_LINK0', - 1: 'DIG_OUTPUT_CRC_ON_LINK1', -} -DIG_OUTPUT_CRC_ON_LINK0 = 0 -DIG_OUTPUT_CRC_ON_LINK1 = 1 -DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' -DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 2: 'DIG_OUTPUT_CRC_FOR_VBI', - 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', -} -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 -DIG_OUTPUT_CRC_FOR_VBI = 2 -DIG_OUTPUT_CRC_FOR_AUDIO = 3 -DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' -DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', -} -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 -DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' -DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', -} -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 -DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { - 0: 'DIG_10BIT_TEST_PATTERN', - 1: 'DIG_ALTERNATING_TEST_PATTERN', -} -DIG_10BIT_TEST_PATTERN = 0 -DIG_ALTERNATING_TEST_PATTERN = 1 -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_NORMAL', - 1: 'DIG_TEST_PATTERN_RANDOM', -} -DIG_TEST_PATTERN_NORMAL = 0 -DIG_TEST_PATTERN_RANDOM = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_ENABLED', - 1: 'DIG_RANDOM_PATTERN_RESETED', -} -DIG_RANDOM_PATTERN_ENABLED = 0 -DIG_RANDOM_PATTERN_RESETED = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_IN_NORMAL_OPERATION', - 1: 'DIG_IN_DEBUG_MODE', -} -DIG_IN_NORMAL_OPERATION = 0 -DIG_IN_DEBUG_MODE = 1 -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACP_SEND' -HDMI_ACP_SEND__enumvalues = { - 0: 'HDMI_ACP_NOT_SEND', - 1: 'HDMI_ACP_PKT_SEND', -} -HDMI_ACP_NOT_SEND = 0 -HDMI_ACP_PKT_SEND = 1 -HDMI_ACP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' -HDMI_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_CONT' -HDMI_ACR_CONT__enumvalues = { - 0: 'HDMI_ACR_CONT_DISABLE', - 1: 'HDMI_ACR_CONT_ENABLE', -} -HDMI_ACR_CONT_DISABLE = 0 -HDMI_ACR_CONT_ENABLE = 1 -HDMI_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_N_MULTIPLE' -HDMI_ACR_N_MULTIPLE__enumvalues = { - 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', - 1: 'HDMI_ACR_1_MULTIPLE', - 2: 'HDMI_ACR_2_MULTIPLE', - 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', - 4: 'HDMI_ACR_4_MULTIPLE', - 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', - 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', - 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', -} -HDMI_ACR_0_MULTIPLE_RESERVED = 0 -HDMI_ACR_1_MULTIPLE = 1 -HDMI_ACR_2_MULTIPLE = 2 -HDMI_ACR_3_MULTIPLE_RESERVED = 3 -HDMI_ACR_4_MULTIPLE = 4 -HDMI_ACR_5_MULTIPLE_RESERVED = 5 -HDMI_ACR_6_MULTIPLE_RESERVED = 6 -HDMI_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SELECT' -HDMI_ACR_SELECT__enumvalues = { - 0: 'HDMI_ACR_SELECT_HW', - 1: 'HDMI_ACR_SELECT_32K', - 2: 'HDMI_ACR_SELECT_44K', - 3: 'HDMI_ACR_SELECT_48K', -} -HDMI_ACR_SELECT_HW = 0 -HDMI_ACR_SELECT_32K = 1 -HDMI_ACR_SELECT_44K = 2 -HDMI_ACR_SELECT_48K = 3 -HDMI_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SEND' -HDMI_ACR_SEND__enumvalues = { - 0: 'HDMI_ACR_NOT_SEND', - 1: 'HDMI_ACR_PKT_SEND', -} -HDMI_ACR_NOT_SEND = 0 -HDMI_ACR_PKT_SEND = 1 -HDMI_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SOURCE' -HDMI_ACR_SOURCE__enumvalues = { - 0: 'HDMI_ACR_SOURCE_HW', - 1: 'HDMI_ACR_SOURCE_SW', -} -HDMI_ACR_SOURCE_HW = 0 -HDMI_ACR_SOURCE_SW = 1 -HDMI_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_DELAY_EN' -HDMI_AUDIO_DELAY_EN__enumvalues = { - 0: 'HDMI_AUDIO_DELAY_DISABLE', - 1: 'HDMI_AUDIO_DELAY_58CLK', - 2: 'HDMI_AUDIO_DELAY_56CLK', - 3: 'HDMI_AUDIO_DELAY_RESERVED', -} -HDMI_AUDIO_DELAY_DISABLE = 0 -HDMI_AUDIO_DELAY_58CLK = 1 -HDMI_AUDIO_DELAY_56CLK = 2 -HDMI_AUDIO_DELAY_RESERVED = 3 -HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_CONT' -HDMI_AUDIO_INFO_CONT__enumvalues = { - 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', - 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', -} -HDMI_AUDIO_INFO_CONT_DISABLE = 0 -HDMI_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_SEND' -HDMI_AUDIO_INFO_SEND__enumvalues = { - 0: 'HDMI_AUDIO_INFO_NOT_SEND', - 1: 'HDMI_AUDIO_INFO_PKT_SEND', -} -HDMI_AUDIO_INFO_NOT_SEND = 0 -HDMI_AUDIO_INFO_PKT_SEND = 1 -HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' -HDMI_CLOCK_CHANNEL_RATE__enumvalues = { - 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', -} -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 -HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' -HDMI_DATA_SCRAMBLE_EN__enumvalues = { - 0: 'HDMI_DATA_SCRAMBLE_DISABLE', - 1: 'HDMI_DATA_SCRAMBLE_ENABLE', -} -HDMI_DATA_SCRAMBLE_DISABLE = 0 -HDMI_DATA_SCRAMBLE_ENABLE = 1 -HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' -HDMI_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', -} -HDMI_DEEP_COLOR_DEPTH_24BPP = 0 -HDMI_DEEP_COLOR_DEPTH_30BPP = 1 -HDMI_DEEP_COLOR_DEPTH_36BPP = 2 -HDMI_DEEP_COLOR_DEPTH_48BPP = 3 -HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEFAULT_PAHSE' -HDMI_DEFAULT_PAHSE__enumvalues = { - 0: 'HDMI_DEFAULT_PHASE_IS_0', - 1: 'HDMI_DEFAULT_PHASE_IS_1', -} -HDMI_DEFAULT_PHASE_IS_0 = 0 -HDMI_DEFAULT_PHASE_IS_1 = 1 -HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_ACK' -HDMI_ERROR_ACK__enumvalues = { - 0: 'HDMI_ERROR_ACK_INT', - 1: 'HDMI_ERROR_NOT_ACK', -} -HDMI_ERROR_ACK_INT = 0 -HDMI_ERROR_NOT_ACK = 1 -HDMI_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_MASK' -HDMI_ERROR_MASK__enumvalues = { - 0: 'HDMI_ERROR_MASK_INT', - 1: 'HDMI_ERROR_NOT_MASK', -} -HDMI_ERROR_MASK_INT = 0 -HDMI_ERROR_NOT_MASK = 1 -HDMI_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE' -HDMI_GC_AVMUTE__enumvalues = { - 0: 'HDMI_GC_AVMUTE_SET', - 1: 'HDMI_GC_AVMUTE_UNSET', -} -HDMI_GC_AVMUTE_SET = 0 -HDMI_GC_AVMUTE_UNSET = 1 -HDMI_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE_CONT' -HDMI_GC_AVMUTE_CONT__enumvalues = { - 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', - 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', -} -HDMI_GC_AVMUTE_CONT_DISABLE = 0 -HDMI_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_CONT' -HDMI_GC_CONT__enumvalues = { - 0: 'HDMI_GC_CONT_DISABLE', - 1: 'HDMI_GC_CONT_ENABLE', -} -HDMI_GC_CONT_DISABLE = 0 -HDMI_GC_CONT_ENABLE = 1 -HDMI_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_SEND' -HDMI_GC_SEND__enumvalues = { - 0: 'HDMI_GC_NOT_SEND', - 1: 'HDMI_GC_PKT_SEND', -} -HDMI_GC_NOT_SEND = 0 -HDMI_GC_PKT_SEND = 1 -HDMI_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_CONT' -HDMI_GENERIC_CONT__enumvalues = { - 0: 'HDMI_GENERIC_CONT_DISABLE', - 1: 'HDMI_GENERIC_CONT_ENABLE', -} -HDMI_GENERIC_CONT_DISABLE = 0 -HDMI_GENERIC_CONT_ENABLE = 1 -HDMI_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_SEND' -HDMI_GENERIC_SEND__enumvalues = { - 0: 'HDMI_GENERIC_NOT_SEND', - 1: 'HDMI_GENERIC_PKT_SEND', -} -HDMI_GENERIC_NOT_SEND = 0 -HDMI_GENERIC_PKT_SEND = 1 -HDMI_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_CONT' -HDMI_ISRC_CONT__enumvalues = { - 0: 'HDMI_ISRC_CONT_DISABLE', - 1: 'HDMI_ISRC_CONT_ENABLE', -} -HDMI_ISRC_CONT_DISABLE = 0 -HDMI_ISRC_CONT_ENABLE = 1 -HDMI_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_SEND' -HDMI_ISRC_SEND__enumvalues = { - 0: 'HDMI_ISRC_NOT_SEND', - 1: 'HDMI_ISRC_PKT_SEND', -} -HDMI_ISRC_NOT_SEND = 0 -HDMI_ISRC_PKT_SEND = 1 -HDMI_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_KEEPOUT_MODE' -HDMI_KEEPOUT_MODE__enumvalues = { - 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', -} -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 -HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_METADATA_ENABLE' -HDMI_METADATA_ENABLE__enumvalues = { - 0: 'HDMI_METADATA_NOT_SEND', - 1: 'HDMI_METADATA_PKT_SEND', -} -HDMI_METADATA_NOT_SEND = 0 -HDMI_METADATA_PKT_SEND = 1 -HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_CONT' -HDMI_MPEG_INFO_CONT__enumvalues = { - 0: 'HDMI_MPEG_INFO_CONT_DISABLE', - 1: 'HDMI_MPEG_INFO_CONT_ENABLE', -} -HDMI_MPEG_INFO_CONT_DISABLE = 0 -HDMI_MPEG_INFO_CONT_ENABLE = 1 -HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_SEND' -HDMI_MPEG_INFO_SEND__enumvalues = { - 0: 'HDMI_MPEG_INFO_NOT_SEND', - 1: 'HDMI_MPEG_INFO_PKT_SEND', -} -HDMI_MPEG_INFO_NOT_SEND = 0 -HDMI_MPEG_INFO_PKT_SEND = 1 -HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' -HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { - 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', - 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', -} -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 -HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NULL_SEND' -HDMI_NULL_SEND__enumvalues = { - 0: 'HDMI_NULL_NOT_SEND', - 1: 'HDMI_NULL_PKT_SEND', -} -HDMI_NULL_NOT_SEND = 0 -HDMI_NULL_PKT_SEND = 1 -HDMI_NULL_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_GEN_VERSION' -HDMI_PACKET_GEN_VERSION__enumvalues = { - 0: 'HDMI_PACKET_GEN_VERSION_OLD', - 1: 'HDMI_PACKET_GEN_VERSION_NEW', -} -HDMI_PACKET_GEN_VERSION_OLD = 0 -HDMI_PACKET_GEN_VERSION_NEW = 1 -HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' -HDMI_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'HDMI_PKT_LINE_REF_VSYNC', - 1: 'HDMI_PKT_LINE_REF_OTGSOF', -} -HDMI_PKT_LINE_REF_VSYNC = 0 -HDMI_PKT_LINE_REF_OTGSOF = 1 -HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' -HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { - 0: 'HDMI_PACKING_PHASE_SET_BY_HW', - 1: 'HDMI_PACKING_PHASE_SET_BY_SW', -} -HDMI_PACKING_PHASE_SET_BY_HW = 0 -HDMI_PACKING_PHASE_SET_BY_SW = 1 -HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', -} -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_COLOR_FORMAT' -TMDS_COLOR_FORMAT__enumvalues = { - 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', - 3: 'TMDS_COLOR_FORMAT_RESERVED', -} -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 -TMDS_COLOR_FORMAT_DUAL30BPP = 2 -TMDS_COLOR_FORMAT_RESERVED = 3 -TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_INVERT' -TMDS_CTL0_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL0_DATA_NORMAL', - 1: 'TMDS_CTL0_DATA_INVERT_EN', -} -TMDS_CTL0_DATA_NORMAL = 0 -TMDS_CTL0_DATA_INVERT_EN = 1 -TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_MODULATION' -TMDS_CTL0_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', -} -TMDS_CTL0_DATA_MODULATION_DISABLE = 0 -TMDS_CTL0_DATA_MODULATION_BIT0 = 1 -TMDS_CTL0_DATA_MODULATION_BIT1 = 2 -TMDS_CTL0_DATA_MODULATION_BIT2 = 3 -TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_SEL' -TMDS_CTL0_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', -} -TMDS_CTL0_DATA_SEL0_RESERVED = 0 -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL0_DATA_SEL2_VSYNC = 2 -TMDS_CTL0_DATA_SEL3_RESERVED = 3 -TMDS_CTL0_DATA_SEL4_HSYNC = 4 -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 -TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' -TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', -} -TMDS_CTL0_PATTERN_OUT_DISABLE = 0 -TMDS_CTL0_PATTERN_OUT_ENABLE = 1 -TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_INVERT' -TMDS_CTL1_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL1_DATA_NORMAL', - 1: 'TMDS_CTL1_DATA_INVERT_EN', -} -TMDS_CTL1_DATA_NORMAL = 0 -TMDS_CTL1_DATA_INVERT_EN = 1 -TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_MODULATION' -TMDS_CTL1_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', -} -TMDS_CTL1_DATA_MODULATION_DISABLE = 0 -TMDS_CTL1_DATA_MODULATION_BIT0 = 1 -TMDS_CTL1_DATA_MODULATION_BIT1 = 2 -TMDS_CTL1_DATA_MODULATION_BIT2 = 3 -TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_SEL' -TMDS_CTL1_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL1_DATA_SEL0_RESERVED = 0 -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL1_DATA_SEL2_VSYNC = 2 -TMDS_CTL1_DATA_SEL3_RESERVED = 3 -TMDS_CTL1_DATA_SEL4_HSYNC = 4 -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' -TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', -} -TMDS_CTL1_PATTERN_OUT_DISABLE = 0 -TMDS_CTL1_PATTERN_OUT_ENABLE = 1 -TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_INVERT' -TMDS_CTL2_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL2_DATA_NORMAL', - 1: 'TMDS_CTL2_DATA_INVERT_EN', -} -TMDS_CTL2_DATA_NORMAL = 0 -TMDS_CTL2_DATA_INVERT_EN = 1 -TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_MODULATION' -TMDS_CTL2_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', -} -TMDS_CTL2_DATA_MODULATION_DISABLE = 0 -TMDS_CTL2_DATA_MODULATION_BIT0 = 1 -TMDS_CTL2_DATA_MODULATION_BIT1 = 2 -TMDS_CTL2_DATA_MODULATION_BIT2 = 3 -TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_SEL' -TMDS_CTL2_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL2_DATA_SEL0_RESERVED = 0 -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL2_DATA_SEL2_VSYNC = 2 -TMDS_CTL2_DATA_SEL3_RESERVED = 3 -TMDS_CTL2_DATA_SEL4_HSYNC = 4 -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' -TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', -} -TMDS_CTL2_PATTERN_OUT_DISABLE = 0 -TMDS_CTL2_PATTERN_OUT_ENABLE = 1 -TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_INVERT' -TMDS_CTL3_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL3_DATA_NORMAL', - 1: 'TMDS_CTL3_DATA_INVERT_EN', -} -TMDS_CTL3_DATA_NORMAL = 0 -TMDS_CTL3_DATA_INVERT_EN = 1 -TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_MODULATION' -TMDS_CTL3_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', -} -TMDS_CTL3_DATA_MODULATION_DISABLE = 0 -TMDS_CTL3_DATA_MODULATION_BIT0 = 1 -TMDS_CTL3_DATA_MODULATION_BIT1 = 2 -TMDS_CTL3_DATA_MODULATION_BIT2 = 3 -TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_SEL' -TMDS_CTL3_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL3_DATA_SEL0_RESERVED = 0 -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL3_DATA_SEL2_VSYNC = 2 -TMDS_CTL3_DATA_SEL3_RESERVED = 3 -TMDS_CTL3_DATA_SEL4_HSYNC = 4 -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' -TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', -} -TMDS_CTL3_PATTERN_OUT_DISABLE = 0 -TMDS_CTL3_PATTERN_OUT_ENABLE = 1 -TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' -TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { - 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', -} -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_PIXEL_ENCODING' -TMDS_PIXEL_ENCODING__enumvalues = { - 0: 'TMDS_PIXEL_ENCODING_444_OR_420', - 1: 'TMDS_PIXEL_ENCODING_422', -} -TMDS_PIXEL_ENCODING_444_OR_420 = 0 -TMDS_PIXEL_ENCODING_422 = 1 -TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' -TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', -} -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 -TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' -TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', - 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', -} -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 -TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' -TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { - 0: 'TMDS_STEREOSYNC_CTL0', - 1: 'TMDS_STEREOSYNC_CTL1', - 2: 'TMDS_STEREOSYNC_CTL2', - 3: 'TMDS_STEREOSYNC_CTL3', -} -TMDS_STEREOSYNC_CTL0 = 0 -TMDS_STEREOSYNC_CTL1 = 1 -TMDS_STEREOSYNC_CTL2 = 2 -TMDS_STEREOSYNC_CTL3 = 3 -TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_SYNC_PHASE' -TMDS_SYNC_PHASE__enumvalues = { - 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', -} -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TMDS_SYNC_PHASE_ON_FRAME_START = 1 -TMDS_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' -TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' -TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', -} -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', -} -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', -} -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', -} -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ACK' -DOUT_I2C_ACK__enumvalues = { - 0: 'DOUT_I2C_NO_ACK', - 1: 'DOUT_I2C_ACK_TO_CLEAN', -} -DOUT_I2C_NO_ACK = 0 -DOUT_I2C_ACK_TO_CLEAN = 1 -DOUT_I2C_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' -DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', -} -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 -DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', -} -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', -} -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' -DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', -} -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 -DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', -} -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' -DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', -} -DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 -DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 -DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' -DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', - 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', - 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', - 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', - 4: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', -} -DOUT_I2C_CONTROL_SELECT_DDC1 = 0 -DOUT_I2C_CONTROL_SELECT_DDC2 = 1 -DOUT_I2C_CONTROL_SELECT_DDC3 = 2 -DOUT_I2C_CONTROL_SELECT_DDC4 = 3 -DOUT_I2C_CONTROL_SELECT_DDCVGA = 4 -DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_GO' -DOUT_I2C_CONTROL_GO__enumvalues = { - 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 1: 'DOUT_I2C_CONTROL_START_TRANSFER', -} -DOUT_I2C_CONTROL_STOP_TRANSFER = 0 -DOUT_I2C_CONTROL_START_TRANSFER = 1 -DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' -DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 1: 'DOUT_I2C_CONTROL__SEND_RESET', -} -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 -DOUT_I2C_CONTROL__SEND_RESET = 1 -DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' -DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { - 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', -} -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 -DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' -DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', -} -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 -DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' -DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', -} -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 -DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 -DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' -DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_TRANS0', - 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', -} -DOUT_I2C_CONTROL_TRANS0 = 0 -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 -DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' -DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { - 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 1: 'DOUT_I2C_DATA__INDEX_WRITE', -} -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 -DOUT_I2C_DATA__INDEX_WRITE = 1 -DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', -} -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', -} -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' -DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { - 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', -} -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 -DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', -} -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { - 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', -} -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' -DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { - 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', -} -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 -DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_EN' -CLOCK_GATING_EN__enumvalues = { - 0: 'CLOCK_GATING_ENABLE', - 1: 'CLOCK_GATING_DISABLE', -} -CLOCK_GATING_ENABLE = 0 -CLOCK_GATING_DISABLE = 1 -CLOCK_GATING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DAC_MUX_SELECT' -DAC_MUX_SELECT__enumvalues = { - 0: 'DAC_MUX_SELECT_DACA', - 1: 'DAC_MUX_SELECT_DACB', -} -DAC_MUX_SELECT_DACA = 0 -DAC_MUX_SELECT_DACB = 1 -DAC_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_DIS_CTRL' -DIOMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', -} -DIOMEM_ENABLE_MEM_PWR_CTRL = 0 -DIOMEM_DISABLE_MEM_PWR_CTRL = 1 -DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' -DIOMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQUEST', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', -} -DIOMEM_NO_FORCE_REQUEST = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 -DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' -DIOMEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQ', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', -} -DIOMEM_NO_FORCE_REQ = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 -DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL' -DIOMEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 -DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' -DIOMEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', -} -DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 -DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 -DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_CLOCK_GATING_DISABLE' -DIO_CLOCK_GATING_DISABLE__enumvalues = { - 0: 'DIO_CLOCK_GATING_EN', - 1: 'DIO_CLOCK_GATING_DIS', -} -DIO_CLOCK_GATING_EN = 0 -DIO_CLOCK_GATING_DIS = 1 -DIO_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_DBG_BLOCK_SEL' -DIO_DBG_BLOCK_SEL__enumvalues = { - 0: 'DIO_DBG_BLOCK_SEL_DIO', - 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', - 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', - 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', - 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', - 18: 'DIO_DBG_BLOCK_SEL_DIGA', - 19: 'DIO_DBG_BLOCK_SEL_DIGB', - 20: 'DIO_DBG_BLOCK_SEL_DIGC', - 21: 'DIO_DBG_BLOCK_SEL_DIGD', - 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', - 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', - 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', - 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', - 32: 'DIO_DBG_BLOCK_SEL_DPA', - 33: 'DIO_DBG_BLOCK_SEL_DPB', - 34: 'DIO_DBG_BLOCK_SEL_DPC', - 35: 'DIO_DBG_BLOCK_SEL_DPD', - 39: 'DIO_DBG_BLOCK_SEL_AUX0', - 40: 'DIO_DBG_BLOCK_SEL_AUX1', - 41: 'DIO_DBG_BLOCK_SEL_AUX2', - 42: 'DIO_DBG_BLOCK_SEL_AUX3', - 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', - 46: 'DIO_DBG_BLOCK_SEL_RESERVED', -} -DIO_DBG_BLOCK_SEL_DIO = 0 -DIO_DBG_BLOCK_SEL_DIGFE_A = 11 -DIO_DBG_BLOCK_SEL_DIGFE_B = 12 -DIO_DBG_BLOCK_SEL_DIGFE_C = 13 -DIO_DBG_BLOCK_SEL_DIGFE_D = 14 -DIO_DBG_BLOCK_SEL_DIGA = 18 -DIO_DBG_BLOCK_SEL_DIGB = 19 -DIO_DBG_BLOCK_SEL_DIGC = 20 -DIO_DBG_BLOCK_SEL_DIGD = 21 -DIO_DBG_BLOCK_SEL_DPFE_A = 25 -DIO_DBG_BLOCK_SEL_DPFE_B = 26 -DIO_DBG_BLOCK_SEL_DPFE_C = 27 -DIO_DBG_BLOCK_SEL_DPFE_D = 28 -DIO_DBG_BLOCK_SEL_DPA = 32 -DIO_DBG_BLOCK_SEL_DPB = 33 -DIO_DBG_BLOCK_SEL_DPC = 34 -DIO_DBG_BLOCK_SEL_DPD = 35 -DIO_DBG_BLOCK_SEL_AUX0 = 39 -DIO_DBG_BLOCK_SEL_AUX1 = 40 -DIO_DBG_BLOCK_SEL_AUX2 = 41 -DIO_DBG_BLOCK_SEL_AUX3 = 42 -DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 -DIO_DBG_BLOCK_SEL_RESERVED = 46 -DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { - 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', -} -DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 -DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' -ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { - 0: 'ENUM_DCN_NOT_ACTIVE', - 1: 'ENUM_DCN_ACTIVE', -} -ENUM_DCN_NOT_ACTIVE = 0 -ENUM_DCN_ACTIVE = 1 -ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_STEREOSYNC_SEL' -GENERIC_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERIC_STEREOSYNC_SEL_D1', - 1: 'GENERIC_STEREOSYNC_SEL_D2', - 2: 'GENERIC_STEREOSYNC_SEL_D3', - 3: 'GENERIC_STEREOSYNC_SEL_D4', - 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', -} -GENERIC_STEREOSYNC_SEL_D1 = 0 -GENERIC_STEREOSYNC_SEL_D2 = 1 -GENERIC_STEREOSYNC_SEL_D3 = 2 -GENERIC_STEREOSYNC_SEL_D4 = 3 -GENERIC_STEREOSYNC_SEL_RESERVED = 4 -GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PM_ASSERT_RESET' -PM_ASSERT_RESET__enumvalues = { - 0: 'PM_ASSERT_RESET_0', - 1: 'PM_ASSERT_RESET_1', -} -PM_ASSERT_RESET_0 = 0 -PM_ASSERT_RESET_1 = 1 -PM_ASSERT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SOFT_RESET' -SOFT_RESET__enumvalues = { - 0: 'SOFT_RESET_0', - 1: 'SOFT_RESET_1', -} -SOFT_RESET_0 = 0 -SOFT_RESET_1 = 1 -SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_MUX_SELECT' -TMDS_MUX_SELECT__enumvalues = { - 0: 'TMDS_MUX_SELECT_B', - 1: 'TMDS_MUX_SELECT_G', - 2: 'TMDS_MUX_SELECT_R', - 3: 'TMDS_MUX_SELECT_RESERVED', -} -TMDS_MUX_SELECT_B = 0 -TMDS_MUX_SELECT_G = 1 -TMDS_MUX_SELECT_R = 2 -TMDS_MUX_SELECT_RESERVED = 3 -TMDS_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET' -DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET__enumvalues = { - 0: 'DIG_STREAM_MAPPER_LINK0', - 1: 'DIG_STREAM_MAPPER_LINK1', - 2: 'DIG_STREAM_MAPPER_LINK2', - 3: 'DIG_STREAM_MAPPER_LINK3', - 4: 'DIG_STREAM_MAPPER_LINK6', -} -DIG_STREAM_MAPPER_LINK0 = 0 -DIG_STREAM_MAPPER_LINK1 = 1 -DIG_STREAM_MAPPER_LINK2 = 2 -DIG_STREAM_MAPPER_LINK3 = 3 -DIG_STREAM_MAPPER_LINK6 = 4 -DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_POWER_STATE_ENUM' -DME_MEM_POWER_STATE_ENUM__enumvalues = { - 0: 'DME_MEM_POWER_STATE_ENUM_ON', - 1: 'DME_MEM_POWER_STATE_ENUM_LS', - 2: 'DME_MEM_POWER_STATE_ENUM_DS', - 3: 'DME_MEM_POWER_STATE_ENUM_SD', -} -DME_MEM_POWER_STATE_ENUM_ON = 0 -DME_MEM_POWER_STATE_ENUM_LS = 1 -DME_MEM_POWER_STATE_ENUM_DS = 2 -DME_MEM_POWER_STATE_ENUM_SD = 3 -DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_DIS_CTRL' -DME_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', -} -DME_MEM_ENABLE_MEM_PWR_CTRL = 0 -DME_MEM_DISABLE_MEM_PWR_CTRL = 1 -DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' -DME_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DME_MEM_NO_FORCE_REQUEST', - 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', -} -DME_MEM_NO_FORCE_REQUEST = 0 -DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_HUBP_SEL' -METADATA_HUBP_SEL__enumvalues = { - 0: 'METADATA_HUBP_SEL_0', - 1: 'METADATA_HUBP_SEL_1', - 2: 'METADATA_HUBP_SEL_2', - 3: 'METADATA_HUBP_SEL_3', - 4: 'METADATA_HUBP_SEL_RESERVED', -} -METADATA_HUBP_SEL_0 = 0 -METADATA_HUBP_SEL_1 = 1 -METADATA_HUBP_SEL_2 = 2 -METADATA_HUBP_SEL_3 = 3 -METADATA_HUBP_SEL_RESERVED = 4 -METADATA_HUBP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_STREAM_TYPE_SEL' -METADATA_STREAM_TYPE_SEL__enumvalues = { - 0: 'METADATA_STREAM_DP', - 1: 'METADATA_STREAM_DVE', -} -METADATA_STREAM_DP = 0 -METADATA_STREAM_DVE = 1 -METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' -VPG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', -} -VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 -VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 -VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' -VPG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'VPG_MEM_NO_FORCE_REQ', - 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', -} -VPG_MEM_NO_FORCE_REQ = 0 -VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 -VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_ACP_TYPE' -AFMT_ACP_TYPE__enumvalues = { - 0: 'ACP_TYPE_GENERIC_AUDIO', - 1: 'ACP_TYPE_ICE60958_AUDIO', - 2: 'ACP_TYPE_DVD_AUDIO', - 3: 'ACP_TYPE_SUPER_AUDIO_CD', -} -ACP_TYPE_GENERIC_AUDIO = 0 -ACP_TYPE_ICE60958_AUDIO = 1 -ACP_TYPE_DVD_AUDIO = 2 -ACP_TYPE_SUPER_AUDIO_CD = 3 -AFMT_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' -AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'AFMT_AUDIO_CRC_CH0_SIG', - 1: 'AFMT_AUDIO_CRC_CH1_SIG', - 2: 'AFMT_AUDIO_CRC_CH2_SIG', - 3: 'AFMT_AUDIO_CRC_CH3_SIG', - 4: 'AFMT_AUDIO_CRC_CH4_SIG', - 5: 'AFMT_AUDIO_CRC_CH5_SIG', - 6: 'AFMT_AUDIO_CRC_CH6_SIG', - 7: 'AFMT_AUDIO_CRC_CH7_SIG', - 8: 'AFMT_AUDIO_CRC_RESERVED_8', - 9: 'AFMT_AUDIO_CRC_RESERVED_9', - 10: 'AFMT_AUDIO_CRC_RESERVED_10', - 11: 'AFMT_AUDIO_CRC_RESERVED_11', - 12: 'AFMT_AUDIO_CRC_RESERVED_12', - 13: 'AFMT_AUDIO_CRC_RESERVED_13', - 14: 'AFMT_AUDIO_CRC_RESERVED_14', - 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', -} -AFMT_AUDIO_CRC_CH0_SIG = 0 -AFMT_AUDIO_CRC_CH1_SIG = 1 -AFMT_AUDIO_CRC_CH2_SIG = 2 -AFMT_AUDIO_CRC_CH3_SIG = 3 -AFMT_AUDIO_CRC_CH4_SIG = 4 -AFMT_AUDIO_CRC_CH5_SIG = 5 -AFMT_AUDIO_CRC_CH6_SIG = 6 -AFMT_AUDIO_CRC_CH7_SIG = 7 -AFMT_AUDIO_CRC_RESERVED_8 = 8 -AFMT_AUDIO_CRC_RESERVED_9 = 9 -AFMT_AUDIO_CRC_RESERVED_10 = 10 -AFMT_AUDIO_CRC_RESERVED_11 = 11 -AFMT_AUDIO_CRC_RESERVED_12 = 12 -AFMT_AUDIO_CRC_RESERVED_13 = 13 -AFMT_AUDIO_CRC_RESERVED_14 = 14 -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 -AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' -AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'AFMT_AUDIO_CRC_ONESHOT', - 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', -} -AFMT_AUDIO_CRC_ONESHOT = 0 -AFMT_AUDIO_CRC_AUTO_RESTART = 1 -AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' -AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { - 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', -} -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 -AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { - 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', -} -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { - 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', -} -AFMT_AUDIO_PACKET_SENT_DISABLED = 0 -AFMT_AUDIO_PACKET_SENT_ENABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { - 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', -} -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' -AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { - 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', -} -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 -AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { - 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', -} -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 -HDMI_SEND_MAX_AUDIO_PACKETS = 1 -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' -AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { - 0: 'AFMT_INTERRUPT_DISABLE', - 1: 'AFMT_INTERRUPT_ENABLE', -} -AFMT_INTERRUPT_DISABLE = 0 -AFMT_INTERRUPT_ENABLE = 1 -AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' -AFMT_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', -} -AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 -AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 -AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' -AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'AFMT_MEM_NO_FORCE_REQUEST', - 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', -} -AFMT_MEM_NO_FORCE_REQUEST = 0 -AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' -AFMT_RAMP_CONTROL0_SIGN__enumvalues = { - 0: 'AFMT_RAMP_SIGNED', - 1: 'AFMT_RAMP_UNSIGNED', -} -AFMT_RAMP_SIGNED = 0 -AFMT_RAMP_UNSIGNED = 1 -AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', - 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_ACP_SOURCE_FROM_AZALIA = 0 -AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AUDIO_LAYOUT_SELECT' -AUDIO_LAYOUT_SELECT__enumvalues = { - 0: 'AUDIO_LAYOUT_0', - 1: 'AUDIO_LAYOUT_1', -} -AUDIO_LAYOUT_0 = 0 -AUDIO_LAYOUT_1 = 1 -AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCOH_TEST_CLOCK_MUX_SELECT_ENUM' -DCOH_TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { - 0: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 1: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 2: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1', - 3: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2', - 4: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3', - 5: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4', - 6: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5', - 7: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6', - 8: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P', - 9: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R', - 10: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1', - 11: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2', - 12: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3', - 13: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4', - 14: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5', - 15: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6', - 16: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0', - 17: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1', - 18: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2', - 19: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3', - 20: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4', - 21: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5', - 22: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6', - 23: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7', - 24: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK', - 25: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK', - 26: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK', - 27: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK', - 28: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK', - 29: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK', - 30: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK', -} -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R = 1 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1 = 2 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2 = 3 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3 = 4 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4 = 5 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5 = 6 -DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6 = 7 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P = 8 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R = 9 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1 = 10 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2 = 11 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3 = 12 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4 = 13 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5 = 14 -DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6 = 15 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0 = 16 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1 = 17 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2 = 18 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3 = 19 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4 = 20 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5 = 21 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6 = 22 -DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7 = 23 -DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK = 24 -DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK = 25 -DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK = 26 -DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK = 27 -DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK = 28 -DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK = 29 -DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK = 30 -DCOH_TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM' -DCOH_TOP_CLOCK_GATING_DISABLE_ENUM__enumvalues = { - 0: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED', - 1: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED', -} -DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 -DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 -DCOH_TOP_CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DCOH_TOP_ENABLE_ENUM' -DCOH_TOP_ENABLE_ENUM__enumvalues = { - 0: 'DCOH_TOP_ENABLE_ENUM_DISABLED', - 1: 'DCOH_TOP_ENABLE_ENUM_ENABLED', -} -DCOH_TOP_ENABLE_ENUM_DISABLED = 0 -DCOH_TOP_ENABLE_ENUM_ENABLED = 1 -DCOH_TOP_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'PHY_MUX_ENABLE_ENUM' -PHY_MUX_ENABLE_ENUM__enumvalues = { - 0: 'PHY_MUX_ENABLE_ENUM_DISABLED', - 1: 'PHY_MUX_ENABLE_ENUM_ENABLED', -} -PHY_MUX_ENABLE_ENUM_DISABLED = 0 -PHY_MUX_ENABLE_ENUM_ENABLED = 1 -PHY_MUX_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' -DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', -} -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 -DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', -} -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', -} -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_STATUS' -DP_AUX_ARB_STATUS__enumvalues = { - 0: 'DP_AUX_IDLE', - 1: 'DP_AUX_IN_USE_LS', - 2: 'DP_AUX_IN_USE_GTC', - 3: 'DP_AUX_IN_USE_SW', - 4: 'DP_AUX_IN_USE_PHYWAKE', -} -DP_AUX_IDLE = 0 -DP_AUX_IN_USE_LS = 1 -DP_AUX_IN_USE_GTC = 2 -DP_AUX_IN_USE_SW = 3 -DP_AUX_IN_USE_PHYWAKE = 4 -DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' -DP_AUX_CONTROL_HPD_SEL__enumvalues = { - 0: 'DP_AUX_CONTROL_HPD1_SELECTED', - 1: 'DP_AUX_CONTROL_HPD2_SELECTED', - 2: 'DP_AUX_CONTROL_HPD3_SELECTED', - 3: 'DP_AUX_CONTROL_HPD4_SELECTED', - 4: 'DP_AUX_CONTROL_NO_HPD_SELECTED', -} -DP_AUX_CONTROL_HPD1_SELECTED = 0 -DP_AUX_CONTROL_HPD2_SELECTED = 1 -DP_AUX_CONTROL_HPD3_SELECTED = 2 -DP_AUX_CONTROL_HPD4_SELECTED = 3 -DP_AUX_CONTROL_NO_HPD_SELECTED = 4 -DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' -DP_AUX_CONTROL_TEST_MODE__enumvalues = { - 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', -} -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 -DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 -DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' -DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { - 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', -} -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 -DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', -} -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', -} -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { - 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', -} -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', -} -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' -DP_AUX_ERR_OCCURRED_ACK__enumvalues = { - 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 1: 'DP_AUX_ERR_OCCURRED__ACK', -} -DP_AUX_ERR_OCCURRED__NOT_ACK = 0 -DP_AUX_ERR_OCCURRED__ACK = 1 -DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', -} -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', -} -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', -} -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', -} -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_INT_ACK' -DP_AUX_INT_ACK__enumvalues = { - 0: 'DP_AUX_INT__NOT_ACK', - 1: 'DP_AUX_INT__ACK', -} -DP_AUX_INT__NOT_ACK = 0 -DP_AUX_INT__ACK = 1 -DP_AUX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_LS_UPDATE_ACK' -DP_AUX_LS_UPDATE_ACK__enumvalues = { - 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', - 1: 'DP_AUX_INT_LS_UPDATE_ACK', -} -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 -DP_AUX_INT_LS_UPDATE_ACK = 1 -DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' -DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { - 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', -} -DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 -DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 -DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' -DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { - 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', - 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', -} -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 -DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET' -DP_AUX_RESET__enumvalues = { - 0: 'DP_AUX_RESET_DEASSERTED', - 1: 'DP_AUX_RESET_ASSERTED', -} -DP_AUX_RESET_DEASSERTED = 0 -DP_AUX_RESET_ASSERTED = 1 -DP_AUX_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET_DONE' -DP_AUX_RESET_DONE__enumvalues = { - 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 1: 'DP_AUX_RESET_SEQUENCE_DONE', -} -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 -DP_AUX_RESET_SEQUENCE_DONE = 1 -DP_AUX_RESET_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' -DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { - 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', - 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', -} -DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 -DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 -DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 -DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 -DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' -DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', -} -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 -DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 -DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' -DP_AUX_SW_CONTROL_SW_GO__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 1: 'DP_AUX_SW_CONTROL_SW__GO', -} -DP_AUX_SW_CONTROL_SW__NOT_GO = 0 -DP_AUX_SW_CONTROL_SW__GO = 1 -DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' -DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { - 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', - 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', - 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', -} -DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 -DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 -DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 -DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 -DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_ACK' -HPD_INT_CONTROL_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_ACK_0', - 1: 'HPD_INT_CONTROL_ACK_1', -} -HPD_INT_CONTROL_ACK_0 = 0 -HPD_INT_CONTROL_ACK_1 = 1 -HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_POLARITY' -HPD_INT_CONTROL_POLARITY__enumvalues = { - 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', - 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', -} -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 -HPD_INT_CONTROL_GEN_INT_ON_CON = 1 -HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' -HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', - 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', -} -HPD_INT_CONTROL_RX_INT_ACK_0 = 0 -HPD_INT_CONTROL_RX_INT_ACK_1 = 1 -HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' -HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { - 0: 'HPO_TOP_CLOCK_GATING_EN', - 1: 'HPO_TOP_CLOCK_GATING_DIS', -} -HPO_TOP_CLOCK_GATING_EN = 0 -HPO_TOP_CLOCK_GATING_DIS = 1 -HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_TEST_CLK_SEL' -HPO_TOP_TEST_CLK_SEL__enumvalues = { - 0: 'HPO_TOP_PERMANENT_DISPCLK', - 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', - 2: 'HPO_TOP_PERMANENT_SOCCLK', - 3: 'HPO_TOP_TEST_CLOCK_RESERVED', - 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', - 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', - 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', -} -HPO_TOP_PERMANENT_DISPCLK = 0 -HPO_TOP_REGISTER_GATED_DISPCLK = 1 -HPO_TOP_PERMANENT_SOCCLK = 2 -HPO_TOP_TEST_CLOCK_RESERVED = 3 -HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 -HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 -HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 -HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 -HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 -HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 -HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 -HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 -HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { - 0: 'DP_STREAM_MAPPER_LINK0', - 1: 'DP_STREAM_MAPPER_LINK1', - 2: 'DP_STREAM_MAPPER_LINK2', - 3: 'DP_STREAM_MAPPER_LINK3', - 4: 'DP_STREAM_MAPPER_RESERVED', -} -DP_STREAM_MAPPER_LINK0 = 0 -DP_STREAM_MAPPER_LINK1 = 1 -DP_STREAM_MAPPER_LINK2 = 2 -DP_STREAM_MAPPER_LINK3 = 3 -DP_STREAM_MAPPER_RESERVED = 4 -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', -} -DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 -DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 -DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { - 0: 'DP_STREAM_ENC_HARDWARE', - 1: 'DP_STREAM_ENC_PROGRAMMABLE', -} -DP_STREAM_ENC_HARDWARE = 0 -DP_STREAM_ENC_PROGRAMMABLE = 1 -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' -DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_DCCG', - 1: 'DP_STREAM_ENC_DISPLAY_PIPE', -} -DP_STREAM_ENC_DCCG = 0 -DP_STREAM_ENC_DISPLAY_PIPE = 1 -DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' -DP_STREAM_ENC_RESET_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_NOT_RESET', - 1: 'DP_STREAM_ENC_RESET', -} -DP_STREAM_ENC_NOT_RESET = 0 -DP_STREAM_ENC_RESET = 1 -DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' -DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { - 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', -} -DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 -DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 -DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' -ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', -} -DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 -DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 -ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { - 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', - 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', -} -DP_SYM32_ENC_ONE_SHOT_MODE = 0 -DP_SYM32_ENC_CONTINUOUS_MODE = 1 -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' -ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { - 0: 'DP_SYM32_ENC_CRC_NOT_VALID', - 1: 'DP_SYM32_ENC_CRC_VALID', -} -DP_SYM32_ENC_CRC_NOT_VALID = 0 -DP_SYM32_ENC_CRC_VALID = 1 -ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', -} -DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 -DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 -DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 -DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' -ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { - 0: 'DP_SYM32_ENC_DISABLE', - 1: 'DP_SYM32_ENC_ENABLE', -} -DP_SYM32_ENC_DISABLE = 0 -DP_SYM32_ENC_ENABLE = 1 -ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', -} -DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 -DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', -} -DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 -DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', -} -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', -} -DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 -DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', -} -DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 -DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 -DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 -DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { - 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', - 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', -} -DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 -DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' -ENUM_DP_SYM32_ENC_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_PENDING', - 1: 'DP_SYM32_ENC_PENDING', -} -DP_SYM32_ENC_NOT_PENDING = 0 -DP_SYM32_ENC_PENDING = 1 -ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', -} -DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 -DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { - 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', -} -DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 -DP_SYM32_ENC_COMPRESSED_FORMAT = 1 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', -} -DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 -DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 -DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 -DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' -ENUM_DP_SYM32_ENC_RESET__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_RESET', - 1: 'DP_SYM32_ENC_RESET', -} -DP_SYM32_ENC_NOT_RESET = 0 -DP_SYM32_ENC_RESET = 1 -ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' -ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', -} -DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 -DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 -ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' -ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { - 0: 'DP_SYM32_ENC_DP_SOF', - 1: 'DP_SYM32_ENC_OTG_SOF', -} -DP_SYM32_ENC_DP_SOF = 0 -DP_SYM32_ENC_OTG_SOF = 1 -ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { - 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', - 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', -} -DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' -ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_END_LLCP', - 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', -} -DP_DPHY_SYM32_CRC_END_LLCP = 0 -DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_END_PS_ANY = 3 -ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' -ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_START_LLCP', - 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 4: 'DP_DPHY_SYM32_CRC_START_TP_START', -} -DP_DPHY_SYM32_CRC_START_LLCP = 0 -DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 -DP_DPHY_SYM32_CRC_START_TP_START = 4 -ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', -} -DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 -DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 -DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', -} -DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 -DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' -ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_DISABLE', - 1: 'DP_DPHY_SYM32_ENABLE', -} -DP_DPHY_SYM32_DISABLE = 0 -DP_DPHY_SYM32_ENABLE = 1 -ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' -ENUM_DP_DPHY_SYM32_MODE__enumvalues = { - 0: 'DP_DPHY_SYM32_LT_TPS1', - 1: 'DP_DPHY_SYM32_LT_TPS2', - 2: 'DP_DPHY_SYM32_ACTIVE', - 3: 'DP_DPHY_SYM32_TEST', -} -DP_DPHY_SYM32_LT_TPS1 = 0 -DP_DPHY_SYM32_LT_TPS2 = 1 -DP_DPHY_SYM32_ACTIVE = 2 -DP_DPHY_SYM32_TEST = 3 -ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' -ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { - 0: 'DP_DPHY_SYM32_1LANE', - 1: 'DP_DPHY_SYM32_2LANE', - 2: 'DP_DPHY_SYM32_RESERVED', - 3: 'DP_DPHY_SYM32_4LANE', -} -DP_DPHY_SYM32_1LANE = 0 -DP_DPHY_SYM32_2LANE = 1 -DP_DPHY_SYM32_RESERVED = 2 -DP_DPHY_SYM32_4LANE = 3 -ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE' -ENUM_DP_DPHY_SYM32_OUTPUT_MODE__enumvalues = { - 0: 'DP_DPHY_SYM32_OUTPUT_PHY', - 1: 'DP_DPHY_SYM32_OUTPUT_DPIA', -} -DP_DPHY_SYM32_OUTPUT_PHY = 0 -DP_DPHY_SYM32_OUTPUT_DPIA = 1 -ENUM_DP_DPHY_SYM32_OUTPUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', -} -DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 -DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' -ENUM_DP_DPHY_SYM32_RESET__enumvalues = { - 0: 'DP_DPHY_SYM32_NOT_RESET', - 1: 'DP_DPHY_SYM32_RESET', -} -DP_DPHY_SYM32_NOT_RESET = 0 -DP_DPHY_SYM32_RESET = 1 -ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' -ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', -} -DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 -DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 -ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' -ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', -} -DP_DPHY_SYM32_SAT_NO_UPDATE = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', -} -DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS' -ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_SCHEDULER_OFF', - 1: 'DP_DPHY_SYM32_SCHEDULER_ASLEEP', - 2: 'DP_DPHY_SYM32_SCHEDULER_AWAKE', -} -DP_DPHY_SYM32_SCHEDULER_OFF = 0 -DP_DPHY_SYM32_SCHEDULER_ASLEEP = 1 -DP_DPHY_SYM32_SCHEDULER_AWAKE = 2 -ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' -ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_STATUS_IDLE', - 1: 'DP_DPHY_SYM32_STATUS_ENABLED', -} -DP_DPHY_SYM32_STATUS_IDLE = 0 -DP_DPHY_SYM32_STATUS_ENABLED = 1 -ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', -} -DP_DPHY_SYM32_STREAM_OVR_NONE = 0 -DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 -DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', - 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', -} -DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 -DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', -} -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' -ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', - 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', - 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', -} -DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 -DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 -DP_DPHY_SYM32_TP_SELECT_PRBS = 2 -DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 -DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 -ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' -APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'APG_AUDIO_CRC_CH0_SIG', - 1: 'APG_AUDIO_CRC_CH1_SIG', - 2: 'APG_AUDIO_CRC_CH2_SIG', - 3: 'APG_AUDIO_CRC_CH3_SIG', - 4: 'APG_AUDIO_CRC_CH4_SIG', - 5: 'APG_AUDIO_CRC_CH5_SIG', - 6: 'APG_AUDIO_CRC_CH6_SIG', - 7: 'APG_AUDIO_CRC_CH7_SIG', - 8: 'APG_AUDIO_CRC_RESERVED_8', - 9: 'APG_AUDIO_CRC_RESERVED_9', - 10: 'APG_AUDIO_CRC_RESERVED_10', - 11: 'APG_AUDIO_CRC_RESERVED_11', - 12: 'APG_AUDIO_CRC_RESERVED_12', - 13: 'APG_AUDIO_CRC_RESERVED_13', - 14: 'APG_AUDIO_CRC_RESERVED_14', - 15: 'APG_AUDIO_CRC_RESERVED_15', -} -APG_AUDIO_CRC_CH0_SIG = 0 -APG_AUDIO_CRC_CH1_SIG = 1 -APG_AUDIO_CRC_CH2_SIG = 2 -APG_AUDIO_CRC_CH3_SIG = 3 -APG_AUDIO_CRC_CH4_SIG = 4 -APG_AUDIO_CRC_CH5_SIG = 5 -APG_AUDIO_CRC_CH6_SIG = 6 -APG_AUDIO_CRC_CH7_SIG = 7 -APG_AUDIO_CRC_RESERVED_8 = 8 -APG_AUDIO_CRC_RESERVED_9 = 9 -APG_AUDIO_CRC_RESERVED_10 = 10 -APG_AUDIO_CRC_RESERVED_11 = 11 -APG_AUDIO_CRC_RESERVED_12 = 12 -APG_AUDIO_CRC_RESERVED_13 = 13 -APG_AUDIO_CRC_RESERVED_14 = 14 -APG_AUDIO_CRC_RESERVED_15 = 15 -APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' -APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'APG_AUDIO_CRC_ONESHOT', - 1: 'APG_AUDIO_CRC_CONTINUOUS', -} -APG_AUDIO_CRC_ONESHOT = 0 -APG_AUDIO_CRC_CONTINUOUS = 1 -APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_ACP_TYPE' -APG_DBG_ACP_TYPE__enumvalues = { - 0: 'APG_ACP_TYPE_GENERIC_AUDIO', - 1: 'APG_ACP_TYPE_ICE60958_AUDIO', - 2: 'APG_ACP_TYPE_DVD_AUDIO', - 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', -} -APG_ACP_TYPE_GENERIC_AUDIO = 0 -APG_ACP_TYPE_ICE60958_AUDIO = 1 -APG_ACP_TYPE_DVD_AUDIO = 2 -APG_ACP_TYPE_SUPER_AUDIO_CD = 3 -APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' -APG_DBG_AUDIO_DTO_BASE__enumvalues = { - 0: 'BASE_RATE_48KHZ', - 1: 'BASE_RATE_44P1KHZ', -} -BASE_RATE_48KHZ = 0 -BASE_RATE_44P1KHZ = 1 -APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' -APG_DBG_AUDIO_DTO_DIV__enumvalues = { - 0: 'DIVISOR_BY1', - 1: 'DIVISOR_BY2_RESERVED', - 2: 'DIVISOR_BY3', - 3: 'DIVISOR_BY4_RESERVED', - 4: 'DIVISOR_BY5_RESERVED', - 5: 'DIVISOR_BY6_RESERVED', - 6: 'DIVISOR_BY7_RESERVED', - 7: 'DIVISOR_BY8_RESERVED', -} -DIVISOR_BY1 = 0 -DIVISOR_BY2_RESERVED = 1 -DIVISOR_BY3 = 2 -DIVISOR_BY4_RESERVED = 3 -DIVISOR_BY5_RESERVED = 4 -DIVISOR_BY6_RESERVED = 5 -DIVISOR_BY7_RESERVED = 6 -DIVISOR_BY8_RESERVED = 7 -APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' -APG_DBG_AUDIO_DTO_MULTI__enumvalues = { - 0: 'MULTIPLE_BY1', - 1: 'MULTIPLE_BY2', - 2: 'MULTIPLE_BY3_RESERVED', - 3: 'MULTIPLE_BY4', - 4: 'MULTIPLE_RESERVED', -} -MULTIPLE_BY1 = 0 -MULTIPLE_BY2 = 1 -MULTIPLE_BY3_RESERVED = 2 -MULTIPLE_BY4 = 3 -MULTIPLE_RESERVED = 4 -APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_MUX_SEL' -APG_DBG_MUX_SEL__enumvalues = { - 0: 'APG_FUNCTIONAL_MODE', - 1: 'APG_DEBUG_AUDIO_MODE', -} -APG_FUNCTIONAL_MODE = 0 -APG_DEBUG_AUDIO_MODE = 1 -APG_DBG_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_POWER_STATE' -APG_MEM_POWER_STATE__enumvalues = { - 0: 'APG_MEM_POWER_STATE_ON', - 1: 'APG_MEM_POWER_STATE_LS', - 2: 'APG_MEM_POWER_STATE_DS', - 3: 'APG_MEM_POWER_STATE_SD', -} -APG_MEM_POWER_STATE_ON = 0 -APG_MEM_POWER_STATE_LS = 1 -APG_MEM_POWER_STATE_DS = 2 -APG_MEM_POWER_STATE_SD = 3 -APG_MEM_POWER_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_DIS_CTRL' -APG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', -} -APG_MEM_ENABLE_MEM_PWR_CTRL = 0 -APG_MEM_DISABLE_MEM_PWR_CTRL = 1 -APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' -APG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'APG_MEM_NO_FORCE_REQUEST', - 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', -} -APG_MEM_NO_FORCE_REQUEST = 0 -APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' -APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'APG_ACP_SOURCE_NO_OVERRIDE', - 1: 'APG_ACP_OVERRIDE', -} -APG_ACP_SOURCE_NO_OVERRIDE = 0 -APG_ACP_OVERRIDE = 1 -APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', -} -APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 -APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_RAMP_CONTROL_SIGN' -APG_RAMP_CONTROL_SIGN__enumvalues = { - 0: 'APG_RAMP_SIGNED', - 1: 'APG_RAMP_UNSIGNED', -} -APG_RAMP_SIGNED = 0 -APG_RAMP_UNSIGNED = 1 -APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', -} -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { - 0: 'DCIO_TEST_CLK_SEL_DISPCLK', - 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', - 2: 'DCIO_TEST_CLK_SEL_SOCCLK', -} -DCIO_TEST_CLK_SEL_DISPCLK = 0 -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 -DCIO_TEST_CLK_SEL_SOCCLK = 2 -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { - 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', -} -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' -DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', - 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', -} -DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 -DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 -DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 -DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 -DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 -DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 -DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 -DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 -DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' -DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', - 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', - 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', -} -DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 -DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 -DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 -DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 -DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' -DCIO_DCRXPHY_SOFT_RESET__enumvalues = { - 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', -} -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 -DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICA_SEL' -DCIO_DC_GENERICA_SEL__enumvalues = { - 1: 'DCIO_GENERICA_SEL_STEREOSYNC', - 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 11: 'DCIO_GENERICA_SEL_SYNCEN', -} -DCIO_GENERICA_SEL_STEREOSYNC = 1 -DCIO_GENERICA_SEL_GENERICA_DCCG = 10 -DCIO_GENERICA_SEL_SYNCEN = 11 -DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICB_SEL' -DCIO_DC_GENERICB_SEL__enumvalues = { - 1: 'DCIO_GENERICB_SEL_STEREOSYNC', - 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 11: 'DCIO_GENERICB_SEL_SYNCEN', -} -DCIO_GENERICB_SEL_STEREOSYNC = 1 -DCIO_GENERICB_SEL_GENERICB_DCCG = 10 -DCIO_GENERICB_SEL_SYNCEN = 11 -DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', -} -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_CLK', -} -DCIO_UNIPHYA_FBDIV_CLK = 0 -DCIO_UNIPHYB_FBDIV_CLK = 1 -DCIO_UNIPHYC_FBDIV_CLK = 2 -DCIO_UNIPHYD_FBDIV_CLK = 3 -DCIO_UNIPHYE_FBDIV_CLK = 4 -DCIO_UNIPHYF_FBDIV_CLK = 5 -DCIO_UNIPHYG_FBDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', -} -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 -DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 -DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 -DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 -DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 -DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 -DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', - 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', - 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', - 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', - 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', - 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', - 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', -} -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 -DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 -DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 -DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 -DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 -DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 -DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { - 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', - 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', -} -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' -DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', -} -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 -DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' -DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DCIO_GPU_TIMER_START_0_END_27', - 1: 'DCIO_GPU_TIMER_START_1_END_28', - 2: 'DCIO_GPU_TIMER_START_2_END_29', - 3: 'DCIO_GPU_TIMER_START_3_END_30', - 4: 'DCIO_GPU_TIMER_START_4_END_31', - 5: 'DCIO_GPU_TIMER_START_6_END_33', - 6: 'DCIO_GPU_TIMER_START_8_END_35', - 7: 'DCIO_GPU_TIMER_START_10_END_37', -} -DCIO_GPU_TIMER_START_0_END_27 = 0 -DCIO_GPU_TIMER_START_1_END_28 = 1 -DCIO_GPU_TIMER_START_2_END_29 = 2 -DCIO_GPU_TIMER_START_3_END_30 = 3 -DCIO_GPU_TIMER_START_4_END_31 = 4 -DCIO_GPU_TIMER_START_6_END_33 = 5 -DCIO_GPU_TIMER_START_8_END_35 = 6 -DCIO_GPU_TIMER_START_10_END_37 = 7 -DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', -} -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' -DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MASK_NONE', - 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', - 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', - 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', - 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', - 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', - 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', - 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', -} -DCIO_EXT_VSYNC_MASK_NONE = 0 -DCIO_EXT_VSYNC_MASK_PIPE0 = 1 -DCIO_EXT_VSYNC_MASK_PIPE1 = 2 -DCIO_EXT_VSYNC_MASK_PIPE2 = 3 -DCIO_EXT_VSYNC_MASK_PIPE3 = 4 -DCIO_EXT_VSYNC_MASK_PIPE4 = 5 -DCIO_EXT_VSYNC_MASK_PIPE5 = 6 -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 -DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' -DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 1: 'DCIO_EXT_VSYNC_MUX_OTG0', - 2: 'DCIO_EXT_VSYNC_MUX_OTG1', - 3: 'DCIO_EXT_VSYNC_MUX_OTG2', - 4: 'DCIO_EXT_VSYNC_MUX_OTG3', - 5: 'DCIO_EXT_VSYNC_MUX_OTG4', - 6: 'DCIO_EXT_VSYNC_MUX_OTG5', - 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', -} -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 -DCIO_EXT_VSYNC_MUX_OTG0 = 1 -DCIO_EXT_VSYNC_MUX_OTG1 = 2 -DCIO_EXT_VSYNC_MUX_OTG2 = 3 -DCIO_EXT_VSYNC_MUX_OTG3 = 4 -DCIO_EXT_VSYNC_MUX_OTG4 = 5 -DCIO_EXT_VSYNC_MUX_OTG5 = 6 -DCIO_EXT_VSYNC_MUX_GENERICB = 7 -DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' -DCIO_DPCS_INTERRUPT_MASK__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_DISABLE', - 1: 'DCIO_DPCS_INTERRUPT_ENABLE', -} -DCIO_DPCS_INTERRUPT_DISABLE = 0 -DCIO_DPCS_INTERRUPT_ENABLE = 1 -DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' -DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', -} -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 -DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' -DCIO_GENLK_CLK_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', - 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', -} -DCIO_GENLK_CLK_GSL_MASK_NO = 0 -DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 -DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 -DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' -DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', -} -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 -DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_SEL' -DCIO_GSL_SEL__enumvalues = { - 0: 'DCIO_GSL_SEL_GROUP_0', - 1: 'DCIO_GSL_SEL_GROUP_1', - 2: 'DCIO_GSL_SEL_GROUP_2', -} -DCIO_GSL_SEL_GROUP_0 = 0 -DCIO_GSL_SEL_GROUP_1 = 1 -DCIO_GSL_SEL_GROUP_2 = 2 -DCIO_GSL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' -DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { - 0: 'HPO_SRC0', - 1: 'HPO_SRC_RESERVED', -} -HPO_SRC0 = 0 -HPO_SRC_RESERVED = 1 -DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' -DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' -DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', -} -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' -DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { - 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', -} -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 -DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', -} -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 -DCIO_UNIPHY_CHANNEL_INVERTED = 1 -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { - 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', -} -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' -DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { - 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', - 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', -} -DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 -DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 -DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' -DCIOCHIP_AUX_CSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', -} -DCIOCHIP_AUX_CSEL_DEC1P0 = 0 -DCIOCHIP_AUX_CSEL_DEC0P9 = 1 -DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' -DCIOCHIP_AUX_CSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_INC1P0', - 1: 'DCIOCHIP_AUX_CSEL_INC1P1', -} -DCIOCHIP_AUX_CSEL_INC1P0 = 0 -DCIOCHIP_AUX_CSEL_INC1P1 = 1 -DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' -DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', - 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', -} -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 -DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' -DCIOCHIP_AUX_HYS_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_HYS_TUNE_0', - 1: 'DCIOCHIP_AUX_HYS_TUNE_1', - 2: 'DCIOCHIP_AUX_HYS_TUNE_2', - 3: 'DCIOCHIP_AUX_HYS_TUNE_3', -} -DCIOCHIP_AUX_HYS_TUNE_0 = 0 -DCIOCHIP_AUX_HYS_TUNE_1 = 1 -DCIOCHIP_AUX_HYS_TUNE_2 = 2 -DCIOCHIP_AUX_HYS_TUNE_3 = 3 -DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' -DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', - 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', -} -DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 -DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 -DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 -DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 -DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' -DCIOCHIP_AUX_RSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', -} -DCIOCHIP_AUX_RSEL_DEC1P0 = 0 -DCIOCHIP_AUX_RSEL_DEC0P9 = 1 -DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' -DCIOCHIP_AUX_RSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_INC1P0', - 1: 'DCIOCHIP_AUX_RSEL_INC1P1', -} -DCIOCHIP_AUX_RSEL_INC1P0 = 0 -DCIOCHIP_AUX_RSEL_INC1P1 = 1 -DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' -DCIOCHIP_AUX_SPIKESEL__enumvalues = { - 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', - 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', -} -DCIOCHIP_AUX_SPIKESEL_50NS = 0 -DCIOCHIP_AUX_SPIKESEL_10NS = 1 -DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' -DCIOCHIP_AUX_VOD_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_VOD_TUNE_0', - 1: 'DCIOCHIP_AUX_VOD_TUNE_1', - 2: 'DCIOCHIP_AUX_VOD_TUNE_2', - 3: 'DCIOCHIP_AUX_VOD_TUNE_3', -} -DCIOCHIP_AUX_VOD_TUNE_0 = 0 -DCIOCHIP_AUX_VOD_TUNE_1 = 1 -DCIOCHIP_AUX_VOD_TUNE_2 = 2 -DCIOCHIP_AUX_VOD_TUNE_3 = 3 -DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' -DCIOCHIP_GPIO_MASK_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', -} -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 -DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_HPD_SEL' -DCIOCHIP_HPD_SEL__enumvalues = { - 0: 'DCIOCHIP_HPD_SEL_ASYNC', - 1: 'DCIOCHIP_HPD_SEL_CLOCKED', -} -DCIOCHIP_HPD_SEL_ASYNC = 0 -DCIOCHIP_HPD_SEL_CLOCKED = 1 -DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_COMPSEL' -DCIOCHIP_I2C_COMPSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_REC_SCHMIT', - 1: 'DCIOCHIP_I2C_REC_COMPARATOR', -} -DCIOCHIP_I2C_REC_SCHMIT = 0 -DCIOCHIP_I2C_REC_COMPARATOR = 1 -DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' -DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', - 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', - 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', -} -DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 -DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 -DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 -DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 -DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' -DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', - 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', -} -DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 -DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 -DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 -DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 -DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' -DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { - 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', - 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', -} -DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 -DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 -DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_INVERT' -DCIOCHIP_INVERT__enumvalues = { - 0: 'DCIOCHIP_POL_NON_INVERT', - 1: 'DCIOCHIP_POL_INVERT', -} -DCIOCHIP_POL_NON_INVERT = 0 -DCIOCHIP_POL_INVERT = 1 -DCIOCHIP_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK' -DCIOCHIP_MASK__enumvalues = { - 0: 'DCIOCHIP_MASK_DISABLE', - 1: 'DCIOCHIP_MASK_ENABLE', -} -DCIOCHIP_MASK_DISABLE = 0 -DCIOCHIP_MASK_ENABLE = 1 -DCIOCHIP_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PAD_MODE' -DCIOCHIP_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_PAD_MODE_DDC', - 1: 'DCIOCHIP_PAD_MODE_DP', -} -DCIOCHIP_PAD_MODE_DDC = 0 -DCIOCHIP_PAD_MODE_DP = 1 -DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PD_EN' -DCIOCHIP_PD_EN__enumvalues = { - 0: 'DCIOCHIP_PD_EN_NOTALLOW', - 1: 'DCIOCHIP_PD_EN_ALLOW', -} -DCIOCHIP_PD_EN_NOTALLOW = 0 -DCIOCHIP_PD_EN_ALLOW = 1 -DCIOCHIP_PD_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' -DCIOCHIP_REF_27_SRC_SEL__enumvalues = { - 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', -} -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 -DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', -} -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', -} -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { - 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', -} -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_DISABLE', - 1: 'PWRSEQ_BL_PWM_ENABLE', -} -PWRSEQ_BL_PWM_DISABLE = 0 -PWRSEQ_BL_PWM_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', -} -PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 -PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', -} -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', -} -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' -PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_GPIO_MASK_EN' -PWRSEQ_GPIO_MASK_EN__enumvalues = { - 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', -} -PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 -PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 -PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_OFF', - 1: 'PWRSEQ_PANEL_BLON_ON', -} -PWRSEQ_PANEL_BLON_OFF = 0 -PWRSEQ_PANEL_BLON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', -} -PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_BLON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_OFF', - 1: 'PWRSEQ_PANEL_DIGON_ON', -} -PWRSEQ_PANEL_DIGON_OFF = 0 -PWRSEQ_PANEL_DIGON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', -} -PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_DIGON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', -} -PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 -PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { - 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', -} -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { - 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', -} -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_CORB_SIZE' -AZ_CORB_SIZE__enumvalues = { - 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_CORB_SIZE_256ENTRIES', - 3: 'AZ_CORB_SIZE_RESERVED', -} -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 -AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 -AZ_CORB_SIZE_256ENTRIES = 2 -AZ_CORB_SIZE_RESERVED = 3 -AZ_CORB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_GLOBAL_CAPABILITIES' -AZ_GLOBAL_CAPABILITIES__enumvalues = { - 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', -} -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 -AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_SIZE' -AZ_RIRB_SIZE__enumvalues = { - 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_RIRB_SIZE_256ENTRIES', - 3: 'AZ_RIRB_SIZE_UNDEFINED', -} -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 -AZ_RIRB_SIZE_256ENTRIES = 2 -AZ_RIRB_SIZE_UNDEFINED = 3 -AZ_RIRB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' -AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { - 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', - 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', -} -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 -AZ_RIRB_WRITE_POINTER_DO_RESET = 1 -AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_STATE_CHANGE_STATUS' -AZ_STATE_CHANGE_STATUS__enumvalues = { - 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', -} -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 -AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'CORB_READ_POINTER_RESET' -CORB_READ_POINTER_RESET__enumvalues = { - 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', -} -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 -CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { - 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', -} -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { - 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', - 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', -} -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' -GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { - 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', -} -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 -GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' -GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { - 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 1: 'FLUSH_CONTROL_FLUSH_STARTED', -} -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 -FLUSH_CONTROL_FLUSH_STARTED = 1 -GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' -GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { - 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', -} -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 -GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_0_SYNCHRONIZATION' -STREAM_0_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_10_SYNCHRONIZATION' -STREAM_10_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_11_SYNCHRONIZATION' -STREAM_11_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_12_SYNCHRONIZATION' -STREAM_12_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_13_SYNCHRONIZATION' -STREAM_13_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_14_SYNCHRONIZATION' -STREAM_14_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_15_SYNCHRONIZATION' -STREAM_15_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_1_SYNCHRONIZATION' -STREAM_1_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_2_SYNCHRONIZATION' -STREAM_2_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_3_SYNCHRONIZATION' -STREAM_3_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_4_SYNCHRONIZATION' -STREAM_4_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_5_SYNCHRONIZATION' -STREAM_5_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_6_SYNCHRONIZATION' -STREAM_6_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_7_SYNCHRONIZATION' -STREAM_7_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_8_SYNCHRONIZATION' -STREAM_8_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_9_SYNCHRONIZATION' -STREAM_9_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', -} -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { - 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', -} -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_CTRL' -MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'ENABLE_MEM_PWR_CTRL', - 1: 'DISABLE_MEM_PWR_CTRL', -} -ENABLE_MEM_PWR_CTRL = 0 -DISABLE_MEM_PWR_CTRL = 1 -MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL' -MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'NO_FORCE_REQUEST', - 1: 'FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FORCE_DEEP_SLEEP_REQUEST', - 3: 'FORCE_SHUT_DOWN_REQUEST', -} -NO_FORCE_REQUEST = 0 -FORCE_LIGHT_SLEEP_REQUEST = 1 -FORCE_DEEP_SLEEP_REQUEST = 2 -FORCE_SHUT_DOWN_REQUEST = 3 -MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL2' -MEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'NO_FORCE_REQ', - 1: 'FORCE_LIGHT_SLEEP_REQ', -} -NO_FORCE_REQ = 0 -FORCE_LIGHT_SLEEP_REQ = 1 -MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL' -MEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DYNAMIC_SHUT_DOWN_ENABLE = 0 -DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL2' -MEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DYNAMIC_DEEP_SLEEP_EN', - 1: 'DYNAMIC_LIGHT_SLEEP_EN', -} -DYNAMIC_DEEP_SLEEP_EN = 0 -DYNAMIC_LIGHT_SLEEP_EN = 1 -MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { - 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', -} -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' -AZ_LATENCY_COUNTER_CONTROL__enumvalues = { - 0: 'AZ_LATENCY_COUNTER_NO_RESET', - 1: 'AZ_LATENCY_COUNTER_RESET_DONE', -} -AZ_LATENCY_COUNTER_NO_RESET = 0 -AZ_LATENCY_COUNTER_RESET_DONE = 1 -AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', -} -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' -DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' -DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', -} -DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 -DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' -DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', -} -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 -DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ENABLE_ENUM' -DSCC_ENABLE_ENUM__enumvalues = { - 0: 'DSCC_ENABLE_ENUM_DISABLED', - 1: 'DSCC_ENABLE_ENUM_ENABLED', -} -DSCC_ENABLE_ENUM_DISABLED = 0 -DSCC_ENABLE_ENUM_ENABLED = 1 -DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ICH_RESET_ENUM' -DSCC_ICH_RESET_ENUM__enumvalues = { - 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', -} -DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 -DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 -DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 -DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 -DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' -DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { - 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', -} -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 -DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' -DSCC_MEM_PWR_DIS_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', - 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', -} -DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 -DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 -DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' -DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', -} -DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 -DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'POWER_STATE_ENUM' -POWER_STATE_ENUM__enumvalues = { - 0: 'POWER_STATE_ENUM_ON', - 1: 'POWER_STATE_ENUM_LS', - 2: 'POWER_STATE_ENUM_DS', - 3: 'POWER_STATE_ENUM_SD', -} -POWER_STATE_ENUM_ON = 0 -POWER_STATE_ENUM_LS = 1 -POWER_STATE_ENUM_DS = 2 -POWER_STATE_ENUM_SD = 3 -POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' -DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_ENABLE_ENUM' -DSCCIF_ENABLE_ENUM__enumvalues = { - 0: 'DSCCIF_ENABLE_ENUM_DISABLED', - 1: 'DSCCIF_ENABLE_ENUM_ENABLED', -} -DSCCIF_ENABLE_ENUM_DISABLED = 0 -DSCCIF_ENABLE_ENUM_ENABLED = 1 -DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' -DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', -} -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' -CLOCK_GATING_DISABLE_ENUM__enumvalues = { - 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', - 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', -} -CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 -CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 -CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_ENUM' -ENABLE_ENUM__enumvalues = { - 0: 'ENABLE_ENUM_DISABLED', - 1: 'ENABLE_ENUM_ENABLED', -} -ENABLE_ENUM_DISABLED = 0 -ENABLE_ENUM_ENABLED = 1 -ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' -TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { - 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', - 6: 'TEST_CLOCK_MUX_SELECT_DSCCLK_D', -} -TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 -TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 -TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 -TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 -TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 -TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 -TEST_CLOCK_MUX_SELECT_DSCCLK_D = 6 -TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_CONT_EN_ENUM' -DWB_CRC_CONT_EN_ENUM__enumvalues = { - 0: 'DWB_CRC_CONT_EN_ONE_SHOT', - 1: 'DWB_CRC_CONT_EN_CONT', -} -DWB_CRC_CONT_EN_ONE_SHOT = 0 -DWB_CRC_CONT_EN_CONT = 1 -DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' -DWB_CRC_SRC_SEL_ENUM__enumvalues = { - 0: 'DWB_CRC_SRC_SEL_DWB_IN', - 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', - 2: 'DWB_CRC_SRC_SEL_DWB_OUT', -} -DWB_CRC_SRC_SEL_DWB_IN = 0 -DWB_CRC_SRC_SEL_OGAM_OUT = 1 -DWB_CRC_SRC_SEL_DWB_OUT = 2 -DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' -DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', - 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', -} -DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 -DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 -DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' -DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', - 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', -} -DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 -DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 -DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 -DWB_DATA_OVERFLOW_TYPE_VREADY = 3 -DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DEBUG_SEL_ENUM' -DWB_DEBUG_SEL_ENUM__enumvalues = { - 0: 'DWB_DEBUG_SEL_FC', - 1: 'DWB_DEBUG_SEL_RESERVED', - 2: 'DWB_DEBUG_SEL_DWBCP', - 3: 'DWB_DEBUG_SEL_PERFMON', -} -DWB_DEBUG_SEL_FC = 0 -DWB_DEBUG_SEL_RESERVED = 1 -DWB_DEBUG_SEL_DWBCP = 2 -DWB_DEBUG_SEL_PERFMON = 3 -DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' -DWB_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_FORCE_DIS', - 1: 'DWB_MEM_PWR_FORCE_LS', - 2: 'DWB_MEM_PWR_FORCE_DS', - 3: 'DWB_MEM_PWR_FORCE_SD', -} -DWB_MEM_PWR_FORCE_DIS = 0 -DWB_MEM_PWR_FORCE_LS = 1 -DWB_MEM_PWR_FORCE_DS = 2 -DWB_MEM_PWR_FORCE_SD = 3 -DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' -DWB_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_STATE_ON', - 1: 'DWB_MEM_PWR_STATE_LS', - 2: 'DWB_MEM_PWR_STATE_DS', - 3: 'DWB_MEM_PWR_STATE_SD', -} -DWB_MEM_PWR_STATE_ON = 0 -DWB_MEM_PWR_STATE_LS = 1 -DWB_MEM_PWR_STATE_DS = 2 -DWB_MEM_PWR_STATE_SD = 3 -DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' -DWB_TEST_CLK_SEL_ENUM__enumvalues = { - 0: 'DWB_TEST_CLK_SEL_R', - 1: 'DWB_TEST_CLK_SEL_G', - 2: 'DWB_TEST_CLK_SEL_P', -} -DWB_TEST_CLK_SEL_R = 0 -DWB_TEST_CLK_SEL_G = 1 -DWB_TEST_CLK_SEL_P = 2 -DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_EYE_SELECTION_ENUM' -FC_EYE_SELECTION_ENUM__enumvalues = { - 0: 'FC_EYE_SELECTION_STEREO_DIS', - 1: 'FC_EYE_SELECTION_LEFT_EYE', - 2: 'FC_EYE_SELECTION_RIGHT_EYE', -} -FC_EYE_SELECTION_STEREO_DIS = 0 -FC_EYE_SELECTION_LEFT_EYE = 1 -FC_EYE_SELECTION_RIGHT_EYE = 2 -FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' -FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { - 0: 'FC_FRAME_CAPTURE_RATE_FULL', - 1: 'FC_FRAME_CAPTURE_RATE_HALF', - 2: 'FC_FRAME_CAPTURE_RATE_THIRD', - 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', -} -FC_FRAME_CAPTURE_RATE_FULL = 0 -FC_FRAME_CAPTURE_RATE_HALF = 1 -FC_FRAME_CAPTURE_RATE_THIRD = 2 -FC_FRAME_CAPTURE_RATE_QUARTER = 3 -FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' -FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { - 0: 'FC_STEREO_EYE_POLARITY_LEFT', - 1: 'FC_STEREO_EYE_POLARITY_RIGHT', -} -FC_STEREO_EYE_POLARITY_LEFT = 0 -FC_STEREO_EYE_POLARITY_RIGHT = 1 -FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' -DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', - 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', - 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', - 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', -} -DWB_GAMUT_REMAP_MODE_BYPASS = 0 -DWB_GAMUT_REMAP_MODE_COEF_A = 1 -DWB_GAMUT_REMAP_MODE_COEF_B = 2 -DWB_GAMUT_REMAP_MODE_RESERVED = 3 -DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_LUT_NUM_SEG' -DWB_LUT_NUM_SEG__enumvalues = { - 0: 'DWB_SEGMENTS_1', - 1: 'DWB_SEGMENTS_2', - 2: 'DWB_SEGMENTS_4', - 3: 'DWB_SEGMENTS_8', - 4: 'DWB_SEGMENTS_16', - 5: 'DWB_SEGMENTS_32', - 6: 'DWB_SEGMENTS_64', - 7: 'DWB_SEGMENTS_128', -} -DWB_SEGMENTS_1 = 0 -DWB_SEGMENTS_2 = 1 -DWB_SEGMENTS_4 = 2 -DWB_SEGMENTS_8 = 3 -DWB_SEGMENTS_16 = 4 -DWB_SEGMENTS_32 = 5 -DWB_SEGMENTS_64 = 6 -DWB_SEGMENTS_128 = 7 -DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' -DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', - 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', -} -DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 -DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 -DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' -DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', - 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', -} -DWB_OGAM_LUT_HOST_SEL_RAMA = 0 -DWB_OGAM_LUT_HOST_SEL_RAMB = 1 -DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', - 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', -} -DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 -DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 -DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 -DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' -DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', - 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', -} -DWB_OGAM_LUT_READ_DBG_DISABLE = 0 -DWB_OGAM_LUT_READ_DBG_ENABLE = 1 -DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_MODE_ENUM' -DWB_OGAM_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_MODE_BYPASS', - 1: 'DWB_OGAM_MODE_RESERVED', - 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', -} -DWB_OGAM_MODE_BYPASS = 0 -DWB_OGAM_MODE_RESERVED = 1 -DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 -DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' -DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { - 0: 'DWB_OGAM_PWL_DISABLE_FALSE', - 1: 'DWB_OGAM_PWL_DISABLE_TRUE', -} -DWB_OGAM_PWL_DISABLE_FALSE = 0 -DWB_OGAM_PWL_DISABLE_TRUE = 1 -DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_SELECT_ENUM' -DWB_OGAM_SELECT_ENUM__enumvalues = { - 0: 'DWB_OGAM_SELECT_A', - 1: 'DWB_OGAM_SELECT_B', -} -DWB_OGAM_SELECT_A = 0 -DWB_OGAM_SELECT_B = 1 -DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = { - 0: 'RDPCS_EXT_REFCLK_DISABLE', - 1: 'RDPCS_EXT_REFCLK_ENABLE', -} -RDPCS_EXT_REFCLK_DISABLE = 0 -RDPCS_EXT_REFCLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON' -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_OCLACLK_CLOCK_OFF', - 1: 'RDPCS_OCLACLK_CLOCK_ON', -} -RDPCS_OCLACLK_CLOCK_OFF = 0 -RDPCS_OCLACLK_CLOCK_ON = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN__enumvalues = { - 0: 'RDPCS_OCLACLK_DISABLE', - 1: 'RDPCS_OCLACLK_ENABLE', -} -RDPCS_OCLACLK_DISABLE = 0 -RDPCS_OCLACLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS' -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_OCLACLK_GATE_ENABLE', - 1: 'RDPCS_OCLACLK_GATE_DISABLE', -} -RDPCS_OCLACLK_GATE_ENABLE = 0 -RDPCS_OCLACLK_GATE_DISABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', - 1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', -} -RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0 -RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { - 0: 'RDPCS_SRAMCLK_DISABLE', - 1: 'RDPCS_SRAMCLK_ENABLE', -} -RDPCS_SRAMCLK_DISABLE = 0 -RDPCS_SRAMCLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_SRAMCLK_GATE_ENABLE', - 1: 'RDPCS_SRAMCLK_GATE_DISABLE', -} -RDPCS_SRAMCLK_GATE_ENABLE = 0 -RDPCS_SRAMCLK_GATE_DISABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { - 0: 'RDPCS_SRAMCLK_NOT_PASS', - 1: 'RDPCS_SRAMCLK_PASS', -} -RDPCS_SRAMCLK_NOT_PASS = 0 -RDPCS_SRAMCLK_PASS = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON' -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_TX_CLK_CLOCK_OFF', - 1: 'RDPCS_TX_CLK_CLOCK_ON', -} -RDPCS_TX_CLK_CLOCK_OFF = 0 -RDPCS_TX_CLK_CLOCK_ON = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN' -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN__enumvalues = { - 0: 'RDPCS_TX_CLK_DISABLE', - 1: 'RDPCS_TX_CLK_ENABLE', -} -RDPCS_TX_CLK_DISABLE = 0 -RDPCS_TX_CLK_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS' -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_TX_CLK_GATE_ENABLE', - 1: 'RDPCS_TX_CLK_GATE_DISABLE', -} -RDPCS_TX_CLK_GATE_ENABLE = 0 -RDPCS_TX_CLK_GATE_DISABLE = 1 -RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CLOCK_CNTL_TX_CLK_EN' -RDPCSTX_CLOCK_CNTL_TX_CLK_EN__enumvalues = { - 0: 'RDPCS_EXT_REFCLK_EN_DISABLE', - 1: 'RDPCS_EXT_REFCLK_EN_ENABLE', -} -RDPCS_EXT_REFCLK_EN_DISABLE = 0 -RDPCS_EXT_REFCLK_EN_ENABLE = 1 -RDPCSTX_CLOCK_CNTL_TX_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = { - 0: 'RDPCS_CBUS_SOFT_RESET_DISABLE', - 1: 'RDPCS_CBUS_SOFT_RESET_ENABLE', -} -RDPCS_CBUS_SOFT_RESET_DISABLE = 0 -RDPCS_CBUS_SOFT_RESET_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { - 0: 'RDPCS_SRAM_SRAM_RESET_DISABLE', - 1: 'RDPCS_SRAM_SRAM_RESET_ENABLE', -} -RDPCS_SRAM_SRAM_RESET_DISABLE = 0 -RDPCS_SRAM_SRAM_RESET_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN' -RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = { - 0: 'RDPCS_TX_FIFO_DISABLE', - 1: 'RDPCS_TX_FIFO_ENABLE', -} -RDPCS_TX_FIFO_DISABLE = 0 -RDPCS_TX_FIFO_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN' -RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = { - 0: 'RDPCS_TX_FIFO_LANE_DISABLE', - 1: 'RDPCS_TX_FIFO_LANE_ENABLE', -} -RDPCS_TX_FIFO_LANE_DISABLE = 0 -RDPCS_TX_FIFO_LANE_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET' -RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = { - 0: 'RDPCS_TX_SOFT_RESET_DISABLE', - 1: 'RDPCS_TX_SOFT_RESET_ENABLE', -} -RDPCS_TX_SOFT_RESET_DISABLE = 0 -RDPCS_TX_SOFT_RESET_ENABLE = 1 -RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_FIFO_EMPTY' -RDPCSTX_FIFO_EMPTY__enumvalues = { - 0: 'RDPCSTX_FIFO_NOT_EMPTY', - 1: 'RDPCSTX_FIFO_IS_EMPTY', -} -RDPCSTX_FIFO_NOT_EMPTY = 0 -RDPCSTX_FIFO_IS_EMPTY = 1 -RDPCSTX_FIFO_EMPTY = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_FIFO_FULL' -RDPCSTX_FIFO_FULL__enumvalues = { - 0: 'RDPCSTX_FIFO_NOT_FULL', - 1: 'RDPCSTX_FIFO_IS_FULL', -} -RDPCSTX_FIFO_NOT_FULL = 0 -RDPCSTX_FIFO_IS_FULL = 1 -RDPCSTX_FIFO_FULL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { - 0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', - 1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', -} -RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0 -RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', -} -RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 -RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { - 0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', - 1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', -} -RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0 -RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', -} -RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 -RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', -} -RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0 -RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK' -RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', -} -RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0 -RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { - 0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', - 1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', -} -RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0 -RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { - 0: 'RDPCS_PHY_CR_PARA_SEL_JTAG', - 1: 'RDPCS_PHY_CR_PARA_SEL_CR', -} -RDPCS_PHY_CR_PARA_SEL_JTAG = 0 -RDPCS_PHY_CR_PARA_SEL_CR = 1 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE' -RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { - 0: 'RDPCS_PHY_REF_RANGE_0', - 1: 'RDPCS_PHY_REF_RANGE_1', - 2: 'RDPCS_PHY_REF_RANGE_2', - 3: 'RDPCS_PHY_REF_RANGE_3', - 4: 'RDPCS_PHY_REF_RANGE_4', - 5: 'RDPCS_PHY_REF_RANGE_5', - 6: 'RDPCS_PHY_REF_RANGE_6', - 7: 'RDPCS_PHY_REF_RANGE_7', -} -RDPCS_PHY_REF_RANGE_0 = 0 -RDPCS_PHY_REF_RANGE_1 = 1 -RDPCS_PHY_REF_RANGE_2 = 2 -RDPCS_PHY_REF_RANGE_3 = 3 -RDPCS_PHY_REF_RANGE_4 = 4 -RDPCS_PHY_REF_RANGE_5 = 5 -RDPCS_PHY_REF_RANGE_6 = 6 -RDPCS_PHY_REF_RANGE_7 = 7 -RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { - 0: 'RDPCS_SRAM_EXT_LD_NOT_DONE', - 1: 'RDPCS_SRAM_EXT_LD_DONE', -} -RDPCS_SRAM_EXT_LD_NOT_DONE = 0 -RDPCS_SRAM_EXT_LD_DONE = 1 -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { - 0: 'RDPCS_SRAM_INIT_NOT_DONE', - 1: 'RDPCS_SRAM_INIT_DONE', -} -RDPCS_SRAM_INIT_NOT_DONE = 0 -RDPCS_SRAM_INIT_DONE = 1 -RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' -RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { - 0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', - 1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', - 2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', - 3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', - 4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', -} -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 -RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 -RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' -RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { - 0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', -} -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 -RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 -RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' -RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { - 0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', - 2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', - 3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', - 4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', - 5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', - 6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', - 7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', -} -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 -RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 -RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' -RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54', - 1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52', - 2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50', - 3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48', - 4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46', - 5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44', - 6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42', - 7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40', -} -RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0 -RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1 -RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2 -RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3 -RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4 -RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5 -RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6 -RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7 -RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', -} -RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 -RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_RATE', - 1: 'RDPCS_PHY_DP_TX_RATE_DIV2', - 2: 'RDPCS_PHY_DP_TX_RATE_DIV4', -} -RDPCS_PHY_DP_TX_RATE = 0 -RDPCS_PHY_DP_TX_RATE_DIV2 = 1 -RDPCS_PHY_DP_TX_RATE_DIV4 = 2 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { - 0: 'RDPCS_PHY_DP_TX_WIDTH_8', - 1: 'RDPCS_PHY_DP_TX_WIDTH_10', - 2: 'RDPCS_PHY_DP_TX_WIDTH_16', - 3: 'RDPCS_PHY_DP_TX_WIDTH_20', -} -RDPCS_PHY_DP_TX_WIDTH_8 = 0 -RDPCS_PHY_DP_TX_WIDTH_10 = 1 -RDPCS_PHY_DP_TX_WIDTH_16 = 2 -RDPCS_PHY_DP_TX_WIDTH_20 = 3 -RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' -RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { - 0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', - 1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', - 2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', - 3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', -} -RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0 -RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1 -RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2 -RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3 -RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_PHY_REF_ALT_CLK_EN' -RDPCSTX_PHY_REF_ALT_CLK_EN__enumvalues = { - 0: 'RDPCS_PHY_REF_ALT_CLK_DISABLE', - 1: 'RDPCS_PHY_REF_ALT_CLK_ENABLE', -} -RDPCS_PHY_REF_ALT_CLK_DISABLE = 0 -RDPCS_PHY_REF_ALT_CLK_ENABLE = 1 -RDPCSTX_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSTX_TX_FIFO_DISABLED_MASK' -RDPCSTX_TX_FIFO_DISABLED_MASK__enumvalues = { - 0: 'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE', - 1: 'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE', -} -RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE = 0 -RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE = 1 -RDPCSTX_TX_FIFO_DISABLED_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_DBG_OCLA_SEL' -RDPCS_DBG_OCLA_SEL__enumvalues = { - 0: 'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0', - 1: 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8', - 2: 'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16', - 3: 'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24', - 4: 'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32', - 5: 'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40', - 6: 'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48', - 7: 'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56', -} -RDPCS_DBG_OCLA_SEL_MON_OUT_7_0 = 0 -RDPCS_DBG_OCLA_SEL_MON_OUT_15_8 = 1 -RDPCS_DBG_OCLA_SEL_MON_OUT_23_16 = 2 -RDPCS_DBG_OCLA_SEL_MON_OUT_31_24 = 3 -RDPCS_DBG_OCLA_SEL_MON_OUT_39_32 = 4 -RDPCS_DBG_OCLA_SEL_MON_OUT_47_40 = 5 -RDPCS_DBG_OCLA_SEL_MON_OUT_55_48 = 6 -RDPCS_DBG_OCLA_SEL_MON_OUT_63_56 = 7 -RDPCS_DBG_OCLA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TEST_CLK_SEL' -RDPCS_TEST_CLK_SEL__enumvalues = { - 0: 'RDPCS_TEST_CLK_SEL_NONE', - 1: 'RDPCS_TEST_CLK_SEL_CFGCLK', - 2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 6: 'RDPCS_TEST_CLK_SEL_SRAMCLK', - 7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', - 8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', - 16: 'RDPCS_TEST_CLK_SEL_dtb_out0', - 17: 'RDPCS_TEST_CLK_SEL_dtb_out1', -} -RDPCS_TEST_CLK_SEL_NONE = 0 -RDPCS_TEST_CLK_SEL_CFGCLK = 1 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 -RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 -RDPCS_TEST_CLK_SEL_SRAMCLK = 6 -RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7 -RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 -RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 -RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 -RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 -RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 -RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 -RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 -RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15 -RDPCS_TEST_CLK_SEL_dtb_out0 = 16 -RDPCS_TEST_CLK_SEL_dtb_out1 = 17 -RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB' -RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { - 0: 'RDPCS_LANE_PACK_FROM_MSB_DISABLE', - 1: 'RDPCS_LANE_PACK_FROM_MSB_ENABLE', -} -RDPCS_LANE_PACK_FROM_MSB_DISABLE = 0 -RDPCS_LANE_PACK_FROM_MSB_ENABLE = 1 -RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { - 0: 'RDPCS_MEM_PWR_NO_FORCE', - 1: 'RDPCS_MEM_PWR_LIGHT_SLEEP', - 2: 'RDPCS_MEM_PWR_DEEP_SLEEP', - 3: 'RDPCS_MEM_PWR_SHUT_DOWN', -} -RDPCS_MEM_PWR_NO_FORCE = 0 -RDPCS_MEM_PWR_LIGHT_SLEEP = 1 -RDPCS_MEM_PWR_DEEP_SLEEP = 2 -RDPCS_MEM_PWR_SHUT_DOWN = 3 -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { - 0: 'RDPCS_MEM_PWR_PWR_STATE_ON', - 1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', -} -RDPCS_MEM_PWR_PWR_STATE_ON = 0 -RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 -RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 -RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 -RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' -RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { - 0: 'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE', - 1: 'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE', -} -RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE = 0 -RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE = 1 -RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_DOORBELL_MODE' -RLC_DOORBELL_MODE__enumvalues = { - 0: 'RLC_DOORBELL_MODE_DISABLE', - 1: 'RLC_DOORBELL_MODE_ENABLE', - 2: 'RLC_DOORBELL_MODE_ENABLE_PF', - 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', -} -RLC_DOORBELL_MODE_DISABLE = 0 -RLC_DOORBELL_MODE_ENABLE = 1 -RLC_DOORBELL_MODE_ENABLE_PF = 2 -RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 -RLC_DOORBELL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFCOUNTER_SEL' -RLC_PERFCOUNTER_SEL__enumvalues = { - 0: 'RLC_PERF_SEL_POWER_FEATURE_0', - 1: 'RLC_PERF_SEL_POWER_FEATURE_1', - 2: 'RLC_PERF_SEL_CP_INTERRUPT', - 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', - 4: 'RLC_PERF_SEL_SPM_INTERRUPT', - 5: 'RLC_PERF_SEL_IH_INTERRUPT', - 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', -} -RLC_PERF_SEL_POWER_FEATURE_0 = 0 -RLC_PERF_SEL_POWER_FEATURE_1 = 1 -RLC_PERF_SEL_CP_INTERRUPT = 2 -RLC_PERF_SEL_GRBM_INTERRUPT = 3 -RLC_PERF_SEL_SPM_INTERRUPT = 4 -RLC_PERF_SEL_IH_INTERRUPT = 5 -RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 -RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFMON_STATE' -RLC_PERFMON_STATE__enumvalues = { - 0: 'RLC_PERFMON_STATE_RESET', - 1: 'RLC_PERFMON_STATE_ENABLE', - 2: 'RLC_PERFMON_STATE_DISABLE', - 3: 'RLC_PERFMON_STATE_RESERVED_3', - 4: 'RLC_PERFMON_STATE_RESERVED_4', - 5: 'RLC_PERFMON_STATE_RESERVED_5', - 6: 'RLC_PERFMON_STATE_RESERVED_6', - 7: 'RLC_PERFMON_STATE_ROLLOVER', -} -RLC_PERFMON_STATE_RESET = 0 -RLC_PERFMON_STATE_ENABLE = 1 -RLC_PERFMON_STATE_DISABLE = 2 -RLC_PERFMON_STATE_RESERVED_3 = 3 -RLC_PERFMON_STATE_RESERVED_4 = 4 -RLC_PERFMON_STATE_RESERVED_5 = 5 -RLC_PERFMON_STATE_RESERVED_6 = 6 -RLC_PERFMON_STATE_ROLLOVER = 7 -RLC_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RSPM_CMD' -RSPM_CMD__enumvalues = { - 0: 'RSPM_CMD_INVALID', - 1: 'RSPM_CMD_IDLE', - 2: 'RSPM_CMD_CALIBRATE', - 3: 'RSPM_CMD_SPM_RESET', - 4: 'RSPM_CMD_SPM_START', - 5: 'RSPM_CMD_SPM_STOP', - 6: 'RSPM_CMD_PERF_RESET', - 7: 'RSPM_CMD_PERF_SAMPLE', - 8: 'RSPM_CMD_PROF_START', - 9: 'RSPM_CMD_PROF_STOP', - 10: 'RSPM_CMD_FORCE_SAMPLE', -} -RSPM_CMD_INVALID = 0 -RSPM_CMD_IDLE = 1 -RSPM_CMD_CALIBRATE = 2 -RSPM_CMD_SPM_RESET = 3 -RSPM_CMD_SPM_START = 4 -RSPM_CMD_SPM_STOP = 5 -RSPM_CMD_PERF_RESET = 6 -RSPM_CMD_PERF_SAMPLE = 7 -RSPM_CMD_PROF_START = 8 -RSPM_CMD_PROF_STOP = 9 -RSPM_CMD_FORCE_SAMPLE = 10 -RSPM_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'CSCNTL_TYPE' -CSCNTL_TYPE__enumvalues = { - 0: 'CSCNTL_TYPE_TG', - 1: 'CSCNTL_TYPE_STATE', - 2: 'CSCNTL_TYPE_EVENT', - 3: 'CSCNTL_TYPE_PRIVATE', -} -CSCNTL_TYPE_TG = 0 -CSCNTL_TYPE_STATE = 1 -CSCNTL_TYPE_EVENT = 2 -CSCNTL_TYPE_PRIVATE = 3 -CSCNTL_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSDATA_TYPE' -CSDATA_TYPE__enumvalues = { - 0: 'CSDATA_TYPE_TG', - 1: 'CSDATA_TYPE_STATE', - 2: 'CSDATA_TYPE_EVENT', - 3: 'CSDATA_TYPE_PRIVATE', -} -CSDATA_TYPE_TG = 0 -CSDATA_TYPE_STATE = 1 -CSDATA_TYPE_EVENT = 2 -CSDATA_TYPE_PRIVATE = 3 -CSDATA_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GE1_PERFCOUNT_SELECT' -GE1_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge1_assembler_busy', - 1: 'ge1_assembler_stalled', - 2: 'ge1_dma_busy', - 3: 'ge1_dma_lat_bin_0', - 4: 'ge1_dma_lat_bin_1', - 5: 'ge1_dma_lat_bin_2', - 6: 'ge1_dma_lat_bin_3', - 7: 'ge1_dma_lat_bin_4', - 8: 'ge1_dma_lat_bin_5', - 9: 'ge1_dma_lat_bin_6', - 10: 'ge1_dma_lat_bin_7', - 11: 'ge1_dma_return_cl0', - 12: 'ge1_dma_return_cl1', - 13: 'ge1_dma_utcl1_consecutive_retry_event', - 14: 'ge1_dma_utcl1_request_event', - 15: 'ge1_dma_utcl1_retry_event', - 16: 'ge1_dma_utcl1_stall_event', - 17: 'ge1_dma_utcl1_stall_utcl2_event', - 18: 'ge1_dma_utcl1_translation_hit_event', - 19: 'ge1_dma_utcl1_translation_miss_event', - 20: 'ge1_assembler_dma_starved', - 21: 'ge1_rbiu_di_fifo_stalled_p0', - 22: 'ge1_rbiu_di_fifo_starved_p0', - 23: 'ge1_rbiu_dr_fifo_stalled_p0', - 24: 'ge1_rbiu_dr_fifo_starved_p0', - 25: 'ge1_sclk_reg_vld', - 26: 'ge1_stat_busy', - 27: 'ge1_stat_no_dma_busy', - 28: 'ge1_pipe0_to_pipe1', - 29: 'ge1_pipe1_to_pipe0', - 30: 'ge1_dma_return_size_cl0', - 31: 'ge1_dma_return_size_cl1', - 32: 'ge1_small_draws_one_instance', - 33: 'ge1_sclk_input_vld', - 34: 'ge1_prim_group_limit_hit', - 35: 'ge1_unopt_multi_instance_draws', - 36: 'ge1_rbiu_di_fifo_stalled_p1', - 37: 'ge1_rbiu_di_fifo_starved_p1', - 38: 'ge1_rbiu_dr_fifo_stalled_p1', - 39: 'ge1_rbiu_dr_fifo_starved_p1', -} -ge1_assembler_busy = 0 -ge1_assembler_stalled = 1 -ge1_dma_busy = 2 -ge1_dma_lat_bin_0 = 3 -ge1_dma_lat_bin_1 = 4 -ge1_dma_lat_bin_2 = 5 -ge1_dma_lat_bin_3 = 6 -ge1_dma_lat_bin_4 = 7 -ge1_dma_lat_bin_5 = 8 -ge1_dma_lat_bin_6 = 9 -ge1_dma_lat_bin_7 = 10 -ge1_dma_return_cl0 = 11 -ge1_dma_return_cl1 = 12 -ge1_dma_utcl1_consecutive_retry_event = 13 -ge1_dma_utcl1_request_event = 14 -ge1_dma_utcl1_retry_event = 15 -ge1_dma_utcl1_stall_event = 16 -ge1_dma_utcl1_stall_utcl2_event = 17 -ge1_dma_utcl1_translation_hit_event = 18 -ge1_dma_utcl1_translation_miss_event = 19 -ge1_assembler_dma_starved = 20 -ge1_rbiu_di_fifo_stalled_p0 = 21 -ge1_rbiu_di_fifo_starved_p0 = 22 -ge1_rbiu_dr_fifo_stalled_p0 = 23 -ge1_rbiu_dr_fifo_starved_p0 = 24 -ge1_sclk_reg_vld = 25 -ge1_stat_busy = 26 -ge1_stat_no_dma_busy = 27 -ge1_pipe0_to_pipe1 = 28 -ge1_pipe1_to_pipe0 = 29 -ge1_dma_return_size_cl0 = 30 -ge1_dma_return_size_cl1 = 31 -ge1_small_draws_one_instance = 32 -ge1_sclk_input_vld = 33 -ge1_prim_group_limit_hit = 34 -ge1_unopt_multi_instance_draws = 35 -ge1_rbiu_di_fifo_stalled_p1 = 36 -ge1_rbiu_di_fifo_starved_p1 = 37 -ge1_rbiu_dr_fifo_stalled_p1 = 38 -ge1_rbiu_dr_fifo_starved_p1 = 39 -GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' -GE2_DIST_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_dist_hs_done', - 1: 'ge_dist_hs_done_latency_se0', - 2: 'ge_dist_hs_done_latency_se1', - 3: 'ge_dist_hs_done_latency_se2', - 4: 'ge_dist_hs_done_latency_se3', - 5: 'ge_dist_hs_done_latency_se4', - 6: 'ge_dist_hs_done_latency_se5', - 7: 'ge_dist_hs_done_latency_se6', - 8: 'ge_dist_hs_done_latency_se7', - 9: 'ge_dist_inside_tf_bin_0', - 10: 'ge_dist_inside_tf_bin_1', - 11: 'ge_dist_inside_tf_bin_2', - 12: 'ge_dist_inside_tf_bin_3', - 13: 'ge_dist_inside_tf_bin_4', - 14: 'ge_dist_inside_tf_bin_5', - 15: 'ge_dist_inside_tf_bin_6', - 16: 'ge_dist_inside_tf_bin_7', - 17: 'ge_dist_inside_tf_bin_8', - 18: 'ge_dist_null_patch', - 19: 'ge_dist_sclk_core_vld', - 20: 'ge_dist_sclk_wd_te11_vld', - 21: 'ge_dist_tfreq_lat_bin_0', - 22: 'ge_dist_tfreq_lat_bin_1', - 23: 'ge_dist_tfreq_lat_bin_2', - 24: 'ge_dist_tfreq_lat_bin_3', - 25: 'ge_dist_tfreq_lat_bin_4', - 26: 'ge_dist_tfreq_lat_bin_5', - 27: 'ge_dist_tfreq_lat_bin_6', - 28: 'ge_dist_tfreq_lat_bin_7', - 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 30: 'ge_dist_tfreq_utcl1_request_event', - 31: 'ge_dist_tfreq_utcl1_retry_event', - 32: 'ge_dist_tfreq_utcl1_stall_event', - 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 34: 'ge_dist_tfreq_utcl1_translation_hit_event', - 35: 'ge_dist_tfreq_utcl1_translation_miss_event', - 36: 'ge_dist_pc_feorder_fifo_full', - 37: 'ge_dist_pc_ge_manager_busy', - 38: 'ge_dist_sclk_input_vld', - 39: 'ge_dist_wd_te11_busy', - 40: 'ge_dist_te11_starved', - 41: 'ge_dist_switch_mode_stall', - 42: 'ge_all_tf_eq', - 43: 'ge_all_tf2', - 44: 'ge_all_tf3', - 45: 'ge_all_tf4', - 46: 'ge_all_tf5', - 47: 'ge_all_tf6', - 48: 'ge_se0_te11_starved_on_hs_done', - 49: 'ge_se1_te11_starved_on_hs_done', - 50: 'ge_se2_te11_starved_on_hs_done', - 51: 'ge_se3_te11_starved_on_hs_done', - 52: 'ge_se4_te11_starved_on_hs_done', - 53: 'ge_se5_te11_starved_on_hs_done', - 54: 'ge_se6_te11_starved_on_hs_done', - 55: 'ge_se7_te11_starved_on_hs_done', - 56: 'ge_dist_op_fifo_full_starve', - 57: 'ge_dist_hs_done_se0', - 58: 'ge_dist_hs_done_se1', - 59: 'ge_dist_hs_done_se2', - 60: 'ge_dist_hs_done_se3', - 61: 'ge_dist_hs_done_se4', - 62: 'ge_dist_hs_done_se5', - 63: 'ge_dist_hs_done_se6', - 64: 'ge_dist_hs_done_se7', - 65: 'ge_dist_hs_done_latency', - 66: 'ge_dist_distributer_busy', - 67: 'ge_tf_ret_data_stalling_hs_done', - 68: 'ge_num_of_no_dist_patches', - 69: 'ge_num_of_donut_dist_patches', - 70: 'ge_num_of_patch_dist_patches', - 71: 'ge_num_of_se_switches_due_to_patch_accum', - 72: 'ge_num_of_se_switches_due_to_donut', - 73: 'ge_num_of_se_switches_due_to_trap', - 74: 'ge_num_of_hs_dealloc_events', - 75: 'ge_agm_gcr_req', - 76: 'ge_agm_gcr_tag_stall', - 77: 'ge_agm_gcr_crd_stall', - 78: 'ge_agm_gcr_stall', - 79: 'ge_agm_gcr_latency', - 80: 'ge_distclk_vld', - 81: 'ge_dist_indx_fifos_full_and_empty', - 82: 'ge_hs_done_all_tf0_se0', - 83: 'ge_hs_done_all_tf0_se1', - 84: 'ge_hs_done_all_tf0_se2', - 85: 'ge_hs_done_all_tf0_se3', - 86: 'ge_hs_done_all_tf0_se4', - 87: 'ge_hs_done_all_tf0_se5', - 88: 'ge_hs_done_all_tf0_se6', - 89: 'ge_hs_done_all_tf0_se7', - 90: 'ge_hs_done_all_tf1_se0', - 91: 'ge_hs_done_all_tf1_se1', - 92: 'ge_hs_done_all_tf1_se2', - 93: 'ge_hs_done_all_tf1_se3', - 94: 'ge_hs_done_all_tf1_se4', - 95: 'ge_hs_done_all_tf1_se5', - 96: 'ge_hs_done_all_tf1_se6', - 97: 'ge_hs_done_all_tf1_se7', - 98: 'ge_agm_gcr_req_outstanding', - 99: 'ge_agm_gcr_req_amount', - 100: 'ge_agm_gcr_combine', -} -ge_dist_hs_done = 0 -ge_dist_hs_done_latency_se0 = 1 -ge_dist_hs_done_latency_se1 = 2 -ge_dist_hs_done_latency_se2 = 3 -ge_dist_hs_done_latency_se3 = 4 -ge_dist_hs_done_latency_se4 = 5 -ge_dist_hs_done_latency_se5 = 6 -ge_dist_hs_done_latency_se6 = 7 -ge_dist_hs_done_latency_se7 = 8 -ge_dist_inside_tf_bin_0 = 9 -ge_dist_inside_tf_bin_1 = 10 -ge_dist_inside_tf_bin_2 = 11 -ge_dist_inside_tf_bin_3 = 12 -ge_dist_inside_tf_bin_4 = 13 -ge_dist_inside_tf_bin_5 = 14 -ge_dist_inside_tf_bin_6 = 15 -ge_dist_inside_tf_bin_7 = 16 -ge_dist_inside_tf_bin_8 = 17 -ge_dist_null_patch = 18 -ge_dist_sclk_core_vld = 19 -ge_dist_sclk_wd_te11_vld = 20 -ge_dist_tfreq_lat_bin_0 = 21 -ge_dist_tfreq_lat_bin_1 = 22 -ge_dist_tfreq_lat_bin_2 = 23 -ge_dist_tfreq_lat_bin_3 = 24 -ge_dist_tfreq_lat_bin_4 = 25 -ge_dist_tfreq_lat_bin_5 = 26 -ge_dist_tfreq_lat_bin_6 = 27 -ge_dist_tfreq_lat_bin_7 = 28 -ge_dist_tfreq_utcl1_consecutive_retry_event = 29 -ge_dist_tfreq_utcl1_request_event = 30 -ge_dist_tfreq_utcl1_retry_event = 31 -ge_dist_tfreq_utcl1_stall_event = 32 -ge_dist_tfreq_utcl1_stall_utcl2_event = 33 -ge_dist_tfreq_utcl1_translation_hit_event = 34 -ge_dist_tfreq_utcl1_translation_miss_event = 35 -ge_dist_pc_feorder_fifo_full = 36 -ge_dist_pc_ge_manager_busy = 37 -ge_dist_sclk_input_vld = 38 -ge_dist_wd_te11_busy = 39 -ge_dist_te11_starved = 40 -ge_dist_switch_mode_stall = 41 -ge_all_tf_eq = 42 -ge_all_tf2 = 43 -ge_all_tf3 = 44 -ge_all_tf4 = 45 -ge_all_tf5 = 46 -ge_all_tf6 = 47 -ge_se0_te11_starved_on_hs_done = 48 -ge_se1_te11_starved_on_hs_done = 49 -ge_se2_te11_starved_on_hs_done = 50 -ge_se3_te11_starved_on_hs_done = 51 -ge_se4_te11_starved_on_hs_done = 52 -ge_se5_te11_starved_on_hs_done = 53 -ge_se6_te11_starved_on_hs_done = 54 -ge_se7_te11_starved_on_hs_done = 55 -ge_dist_op_fifo_full_starve = 56 -ge_dist_hs_done_se0 = 57 -ge_dist_hs_done_se1 = 58 -ge_dist_hs_done_se2 = 59 -ge_dist_hs_done_se3 = 60 -ge_dist_hs_done_se4 = 61 -ge_dist_hs_done_se5 = 62 -ge_dist_hs_done_se6 = 63 -ge_dist_hs_done_se7 = 64 -ge_dist_hs_done_latency = 65 -ge_dist_distributer_busy = 66 -ge_tf_ret_data_stalling_hs_done = 67 -ge_num_of_no_dist_patches = 68 -ge_num_of_donut_dist_patches = 69 -ge_num_of_patch_dist_patches = 70 -ge_num_of_se_switches_due_to_patch_accum = 71 -ge_num_of_se_switches_due_to_donut = 72 -ge_num_of_se_switches_due_to_trap = 73 -ge_num_of_hs_dealloc_events = 74 -ge_agm_gcr_req = 75 -ge_agm_gcr_tag_stall = 76 -ge_agm_gcr_crd_stall = 77 -ge_agm_gcr_stall = 78 -ge_agm_gcr_latency = 79 -ge_distclk_vld = 80 -ge_dist_indx_fifos_full_and_empty = 81 -ge_hs_done_all_tf0_se0 = 82 -ge_hs_done_all_tf0_se1 = 83 -ge_hs_done_all_tf0_se2 = 84 -ge_hs_done_all_tf0_se3 = 85 -ge_hs_done_all_tf0_se4 = 86 -ge_hs_done_all_tf0_se5 = 87 -ge_hs_done_all_tf0_se6 = 88 -ge_hs_done_all_tf0_se7 = 89 -ge_hs_done_all_tf1_se0 = 90 -ge_hs_done_all_tf1_se1 = 91 -ge_hs_done_all_tf1_se2 = 92 -ge_hs_done_all_tf1_se3 = 93 -ge_hs_done_all_tf1_se4 = 94 -ge_hs_done_all_tf1_se5 = 95 -ge_hs_done_all_tf1_se6 = 96 -ge_hs_done_all_tf1_se7 = 97 -ge_agm_gcr_req_outstanding = 98 -ge_agm_gcr_req_amount = 99 -ge_agm_gcr_combine = 100 -GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' -GE2_SE_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_se_ds_prims', - 1: 'ge_se_es_thread_groups', - 2: 'ge_se_esvert_stalled_gsprim', - 3: 'ge_se_hs_tfm_stall', - 4: 'ge_se_hs_tgs_active_high_water_mark', - 5: 'ge_se_hs_thread_groups', - 6: 'ge_se_reused_es_indices', - 7: 'ge_se_sclk_ngg_vld', - 8: 'ge_se_sclk_te11_vld', - 9: 'ge_se_spi_esvert_eov', - 10: 'ge_se_spi_esvert_stalled', - 11: 'ge_se_spi_esvert_starved_busy', - 12: 'ge_se_spi_esvert_valid', - 13: 'ge_se_spi_gsprim_cont', - 14: 'ge_se_spi_gsprim_eov', - 15: 'ge_se_spi_gsprim_stalled', - 16: 'ge_se_spi_gsprim_starved_busy', - 17: 'ge_se_spi_gsprim_valid', - 18: 'ge_se_spi_gssubgrp_is_event', - 19: 'ge_se_spi_gssubgrp_send', - 20: 'ge_se_spi_hsvert_eov', - 21: 'ge_se_spi_hsvert_stalled', - 22: 'ge_se_spi_hsvert_starved_busy', - 23: 'ge_se_spi_hsvert_valid', - 24: 'ge_se_spi_hsgrp_is_event', - 25: 'ge_se_spi_hsgrp_send', - 26: 'ge_se_spi_lsvert_eov', - 27: 'ge_se_spi_lsvert_stalled', - 28: 'ge_se_spi_lsvert_starved_busy', - 29: 'ge_se_spi_lsvert_valid', - 30: 'ge_se_spi_hsvert_fifo_full_stall', - 31: 'ge_se_spi_tgrp_fifo_stall', - 32: 'ge_spi_hsgrp_spi_stall', - 33: 'ge_se_spi_gssubgrp_event_window_active', - 34: 'ge_se_hs_input_stall', - 35: 'ge_se_sending_vert_or_prim', - 36: 'ge_se_sclk_input_vld', - 37: 'ge_spi_lswave_fifo_full_stall', - 38: 'ge_spi_hswave_fifo_full_stall', - 39: 'ge_hs_tif_stall', - 40: 'ge_csb_spi_bp', - 41: 'ge_ngg_starving_for_wave_id', - 42: 'ge_pa0_csb_eop', - 43: 'ge_ngg_starved_idle', - 44: 'ge_gsprim_send', - 45: 'ge_esvert_send', - 46: 'ge_ngg_starved_after_work', - 47: 'ge_ngg_subgrp_fifo_stall', - 48: 'ge_ngg_ord_id_req_stall', - 49: 'ge_ngg_indx_bus_stall', - 50: 'ge_hs_stall_tfmm_fifo_full', - 51: 'ge_gs_issue_rtr_stalled', - 52: 'ge_gsprim_stalled_esvert', - 53: 'ge_gsthread_stalled', - 54: 'ge_ngg_attr_grp_alloc', - 55: 'ge_ngg_attr_discard_alloc', - 56: 'ge_ngg_pc_space_not_avail', - 57: 'ge_ngg_agm_req_stall', - 58: 'ge_ngg_spi_esvert_partial_eov', - 59: 'ge_ngg_spi_gsprim_partial_eov', - 60: 'ge_spi_gsgrp_valid', - 61: 'ge_ngg_attr_grp_latency', - 62: 'ge_ngg_reuse_prim_limit_hit', - 63: 'ge_ngg_reuse_vert_limit_hit', - 64: 'ge_te11_con_stall', - 65: 'ge_te11_compactor_starved', - 66: 'ge_ngg_stall_tess_off_tess_on', - 67: 'ge_ngg_stall_tess_on_tess_off', - 68: 'ge_merged_lses_vert_stalled', - 69: 'ge_merged_hsgs_vert_stalled', - 70: 'ge_merged_hsgs_grp_stalled', - 71: 'ge_merge_lses_fifo_blocked', - 72: 'ge_merge_hsgs_fifo_blocked', - 73: 'ge_merge_lses_vert_switch', - 74: 'ge_merge_hsgs_vert_switch', - 75: 'ge_merge_hsgs_grp_switch', - 76: 'ge_merge_gsgrp_rdy_pending_verts', - 77: 'ge_merge_hsgrp_rdy_pending_verts', - 78: 'ge_se_ds_cache_hits', - 79: 'ge_se_api_vs_verts', - 80: 'ge_se_api_ds_verts', - 81: 'ge_se_combined_busy', - 82: 'ge_spi_lsvert_send', - 83: 'ge_spi_hsvert_send', - 84: 'ge_ngg_attr_grp_wasted', - 85: 'ge_spi_gssubgrp_stalled', - 86: 'ge_ngg_attr_null_dealloc', - 87: 'ge_ngg_busy_base', -} -ge_se_ds_prims = 0 -ge_se_es_thread_groups = 1 -ge_se_esvert_stalled_gsprim = 2 -ge_se_hs_tfm_stall = 3 -ge_se_hs_tgs_active_high_water_mark = 4 -ge_se_hs_thread_groups = 5 -ge_se_reused_es_indices = 6 -ge_se_sclk_ngg_vld = 7 -ge_se_sclk_te11_vld = 8 -ge_se_spi_esvert_eov = 9 -ge_se_spi_esvert_stalled = 10 -ge_se_spi_esvert_starved_busy = 11 -ge_se_spi_esvert_valid = 12 -ge_se_spi_gsprim_cont = 13 -ge_se_spi_gsprim_eov = 14 -ge_se_spi_gsprim_stalled = 15 -ge_se_spi_gsprim_starved_busy = 16 -ge_se_spi_gsprim_valid = 17 -ge_se_spi_gssubgrp_is_event = 18 -ge_se_spi_gssubgrp_send = 19 -ge_se_spi_hsvert_eov = 20 -ge_se_spi_hsvert_stalled = 21 -ge_se_spi_hsvert_starved_busy = 22 -ge_se_spi_hsvert_valid = 23 -ge_se_spi_hsgrp_is_event = 24 -ge_se_spi_hsgrp_send = 25 -ge_se_spi_lsvert_eov = 26 -ge_se_spi_lsvert_stalled = 27 -ge_se_spi_lsvert_starved_busy = 28 -ge_se_spi_lsvert_valid = 29 -ge_se_spi_hsvert_fifo_full_stall = 30 -ge_se_spi_tgrp_fifo_stall = 31 -ge_spi_hsgrp_spi_stall = 32 -ge_se_spi_gssubgrp_event_window_active = 33 -ge_se_hs_input_stall = 34 -ge_se_sending_vert_or_prim = 35 -ge_se_sclk_input_vld = 36 -ge_spi_lswave_fifo_full_stall = 37 -ge_spi_hswave_fifo_full_stall = 38 -ge_hs_tif_stall = 39 -ge_csb_spi_bp = 40 -ge_ngg_starving_for_wave_id = 41 -ge_pa0_csb_eop = 42 -ge_ngg_starved_idle = 43 -ge_gsprim_send = 44 -ge_esvert_send = 45 -ge_ngg_starved_after_work = 46 -ge_ngg_subgrp_fifo_stall = 47 -ge_ngg_ord_id_req_stall = 48 -ge_ngg_indx_bus_stall = 49 -ge_hs_stall_tfmm_fifo_full = 50 -ge_gs_issue_rtr_stalled = 51 -ge_gsprim_stalled_esvert = 52 -ge_gsthread_stalled = 53 -ge_ngg_attr_grp_alloc = 54 -ge_ngg_attr_discard_alloc = 55 -ge_ngg_pc_space_not_avail = 56 -ge_ngg_agm_req_stall = 57 -ge_ngg_spi_esvert_partial_eov = 58 -ge_ngg_spi_gsprim_partial_eov = 59 -ge_spi_gsgrp_valid = 60 -ge_ngg_attr_grp_latency = 61 -ge_ngg_reuse_prim_limit_hit = 62 -ge_ngg_reuse_vert_limit_hit = 63 -ge_te11_con_stall = 64 -ge_te11_compactor_starved = 65 -ge_ngg_stall_tess_off_tess_on = 66 -ge_ngg_stall_tess_on_tess_off = 67 -ge_merged_lses_vert_stalled = 68 -ge_merged_hsgs_vert_stalled = 69 -ge_merged_hsgs_grp_stalled = 70 -ge_merge_lses_fifo_blocked = 71 -ge_merge_hsgs_fifo_blocked = 72 -ge_merge_lses_vert_switch = 73 -ge_merge_hsgs_vert_switch = 74 -ge_merge_hsgs_grp_switch = 75 -ge_merge_gsgrp_rdy_pending_verts = 76 -ge_merge_hsgrp_rdy_pending_verts = 77 -ge_se_ds_cache_hits = 78 -ge_se_api_vs_verts = 79 -ge_se_api_ds_verts = 80 -ge_se_combined_busy = 81 -ge_spi_lsvert_send = 82 -ge_spi_hsvert_send = 83 -ge_ngg_attr_grp_wasted = 84 -ge_spi_gssubgrp_stalled = 85 -ge_ngg_attr_null_dealloc = 86 -ge_ngg_busy_base = 87 -GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ONE' -VGT_DETECT_ONE__enumvalues = { - 0: 'ENABLE_TF1_OPT', - 1: 'DISABLE_TF1_OPT', -} -ENABLE_TF1_OPT = 0 -DISABLE_TF1_OPT = 1 -VGT_DETECT_ONE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ZERO' -VGT_DETECT_ZERO__enumvalues = { - 0: 'ENABLE_TF0_OPT', - 1: 'DISABLE_TF0_OPT', -} -ENABLE_TF0_OPT = 0 -DISABLE_TF0_OPT = 1 -VGT_DETECT_ZERO = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DIST_MODE' -VGT_DIST_MODE__enumvalues = { - 0: 'NO_DIST', - 1: 'PATCHES', - 2: 'DONUTS', - 3: 'TRAPEZOIDS', -} -NO_DIST = 0 -PATCHES = 1 -DONUTS = 2 -TRAPEZOIDS = 3 -VGT_DIST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_INDEX_SIZE' -VGT_DI_INDEX_SIZE__enumvalues = { - 0: 'DI_INDEX_SIZE_16_BIT', - 1: 'DI_INDEX_SIZE_32_BIT', - 2: 'DI_INDEX_SIZE_8_BIT', -} -DI_INDEX_SIZE_16_BIT = 0 -DI_INDEX_SIZE_32_BIT = 1 -DI_INDEX_SIZE_8_BIT = 2 -VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_PRIM_TYPE' -VGT_DI_PRIM_TYPE__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_2D_RECTANGLE', - 8: 'DI_PT_UNUSED_1', - 9: 'DI_PT_PATCH', - 10: 'DI_PT_LINELIST_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRILIST_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 14: 'DI_PT_UNUSED_3', - 15: 'DI_PT_UNUSED_4', - 16: 'DI_PT_UNUSED_5', - 17: 'DI_PT_RECTLIST', - 18: 'DI_PT_LINELOOP', - 19: 'DI_PT_QUADLIST', - 20: 'DI_PT_QUADSTRIP', - 21: 'DI_PT_POLYGON', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_2D_RECTANGLE = 7 -DI_PT_UNUSED_1 = 8 -DI_PT_PATCH = 9 -DI_PT_LINELIST_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRILIST_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_UNUSED_3 = 14 -DI_PT_UNUSED_4 = 15 -DI_PT_UNUSED_5 = 16 -DI_PT_RECTLIST = 17 -DI_PT_LINELOOP = 18 -DI_PT_QUADLIST = 19 -DI_PT_QUADSTRIP = 20 -DI_PT_POLYGON = 21 -VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_SOURCE_SELECT' -VGT_DI_SOURCE_SELECT__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_RESERVED', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_RESERVED = 3 -VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_BUF_TYPE' -VGT_DMA_BUF_TYPE__enumvalues = { - 0: 'VGT_DMA_BUF_MEM', - 1: 'VGT_DMA_BUF_RING', - 2: 'VGT_DMA_BUF_SETUP', - 3: 'VGT_DMA_PTR_UPDATE', -} -VGT_DMA_BUF_MEM = 0 -VGT_DMA_BUF_RING = 1 -VGT_DMA_BUF_SETUP = 2 -VGT_DMA_PTR_UPDATE = 3 -VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_SWAP_MODE' -VGT_DMA_SWAP_MODE__enumvalues = { - 0: 'VGT_DMA_SWAP_NONE', - 1: 'VGT_DMA_SWAP_16_BIT', - 2: 'VGT_DMA_SWAP_32_BIT', - 3: 'VGT_DMA_SWAP_WORD', -} -VGT_DMA_SWAP_NONE = 0 -VGT_DMA_SWAP_16_BIT = 1 -VGT_DMA_SWAP_32_BIT = 2 -VGT_DMA_SWAP_WORD = 3 -VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_EVENT_TYPE' -VGT_EVENT_TYPE__enumvalues = { - 0: 'Reserved_0x00', - 1: 'SAMPLE_STREAMOUTSTATS1', - 2: 'SAMPLE_STREAMOUTSTATS2', - 3: 'SAMPLE_STREAMOUTSTATS3', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'CS_PARTIAL_FLUSH', - 8: 'VGT_STREAMOUT_SYNC', - 9: 'EVENT_STATE_CHANGE', - 10: 'VGT_STREAMOUT_RESET', - 11: 'END_OF_PIPE_INCR_DE', - 12: 'END_OF_PIPE_IB_END', - 13: 'RST_PIX_CNT', - 14: 'BREAK_BATCH', - 15: 'VS_PARTIAL_FLUSH', - 16: 'PS_PARTIAL_FLUSH', - 17: 'FLUSH_HS_OUTPUT', - 18: 'FLUSH_DFSM', - 19: 'RESET_TO_LOWEST_VGT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'WAIT_SYNC', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 25: 'PIPELINESTAT_START', - 26: 'PIPELINESTAT_STOP', - 27: 'PERFCOUNTER_SAMPLE', - 28: 'FLUSH_ES_OUTPUT', - 29: 'BIN_CONF_OVERRIDE_CHECK', - 30: 'SAMPLE_PIPELINESTAT', - 31: 'SO_VGTSTREAMOUT_FLUSH', - 32: 'SAMPLE_STREAMOUTSTATS', - 33: 'RESET_VTX_CNT', - 34: 'BLOCK_CONTEXT_DONE', - 35: 'CS_CONTEXT_DONE', - 36: 'VGT_FLUSH', - 37: 'TGID_ROLLOVER', - 38: 'SQ_NON_EVENT', - 39: 'SC_SEND_DB_VPZ', - 40: 'BOTTOM_OF_PIPE_TS', - 41: 'FLUSH_SX_TS', - 42: 'DB_CACHE_FLUSH_AND_INV', - 43: 'FLUSH_AND_INV_DB_DATA_TS', - 44: 'FLUSH_AND_INV_DB_META', - 45: 'FLUSH_AND_INV_CB_DATA_TS', - 46: 'FLUSH_AND_INV_CB_META', - 47: 'CS_DONE', - 48: 'PS_DONE', - 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', - 50: 'SX_CB_RAT_ACK_REQUEST', - 51: 'THREAD_TRACE_START', - 52: 'THREAD_TRACE_STOP', - 53: 'THREAD_TRACE_MARKER', - 54: 'THREAD_TRACE_DRAW', - 55: 'THREAD_TRACE_FINISH', - 56: 'PIXEL_PIPE_STAT_CONTROL', - 57: 'PIXEL_PIPE_STAT_DUMP', - 58: 'PIXEL_PIPE_STAT_RESET', - 59: 'CONTEXT_SUSPEND', - 60: 'OFFCHIP_HS_DEALLOC', - 61: 'ENABLE_NGG_PIPELINE', - 62: 'ENABLE_PIPELINE_NOT_USED', - 63: 'DRAW_DONE', -} -Reserved_0x00 = 0 -SAMPLE_STREAMOUTSTATS1 = 1 -SAMPLE_STREAMOUTSTATS2 = 2 -SAMPLE_STREAMOUTSTATS3 = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -CS_PARTIAL_FLUSH = 7 -VGT_STREAMOUT_SYNC = 8 -EVENT_STATE_CHANGE = 9 -VGT_STREAMOUT_RESET = 10 -END_OF_PIPE_INCR_DE = 11 -END_OF_PIPE_IB_END = 12 -RST_PIX_CNT = 13 -BREAK_BATCH = 14 -VS_PARTIAL_FLUSH = 15 -PS_PARTIAL_FLUSH = 16 -FLUSH_HS_OUTPUT = 17 -FLUSH_DFSM = 18 -RESET_TO_LOWEST_VGT = 19 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -WAIT_SYNC = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -PIPELINESTAT_START = 25 -PIPELINESTAT_STOP = 26 -PERFCOUNTER_SAMPLE = 27 -FLUSH_ES_OUTPUT = 28 -BIN_CONF_OVERRIDE_CHECK = 29 -SAMPLE_PIPELINESTAT = 30 -SO_VGTSTREAMOUT_FLUSH = 31 -SAMPLE_STREAMOUTSTATS = 32 -RESET_VTX_CNT = 33 -BLOCK_CONTEXT_DONE = 34 -CS_CONTEXT_DONE = 35 -VGT_FLUSH = 36 -TGID_ROLLOVER = 37 -SQ_NON_EVENT = 38 -SC_SEND_DB_VPZ = 39 -BOTTOM_OF_PIPE_TS = 40 -FLUSH_SX_TS = 41 -DB_CACHE_FLUSH_AND_INV = 42 -FLUSH_AND_INV_DB_DATA_TS = 43 -FLUSH_AND_INV_DB_META = 44 -FLUSH_AND_INV_CB_DATA_TS = 45 -FLUSH_AND_INV_CB_META = 46 -CS_DONE = 47 -PS_DONE = 48 -FLUSH_AND_INV_CB_PIXEL_DATA = 49 -SX_CB_RAT_ACK_REQUEST = 50 -THREAD_TRACE_START = 51 -THREAD_TRACE_STOP = 52 -THREAD_TRACE_MARKER = 53 -THREAD_TRACE_DRAW = 54 -THREAD_TRACE_FINISH = 55 -PIXEL_PIPE_STAT_CONTROL = 56 -PIXEL_PIPE_STAT_DUMP = 57 -PIXEL_PIPE_STAT_RESET = 58 -CONTEXT_SUSPEND = 59 -OFFCHIP_HS_DEALLOC = 60 -ENABLE_NGG_PIPELINE = 61 -ENABLE_PIPELINE_NOT_USED = 62 -DRAW_DONE = 63 -VGT_EVENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GROUP_CONV_SEL' -VGT_GROUP_CONV_SEL__enumvalues = { - 0: 'VGT_GRP_INDEX_16', - 1: 'VGT_GRP_INDEX_32', - 2: 'VGT_GRP_UINT_16', - 3: 'VGT_GRP_UINT_32', - 4: 'VGT_GRP_SINT_16', - 5: 'VGT_GRP_SINT_32', - 6: 'VGT_GRP_FLOAT_32', - 7: 'VGT_GRP_AUTO_PRIM', - 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', -} -VGT_GRP_INDEX_16 = 0 -VGT_GRP_INDEX_32 = 1 -VGT_GRP_UINT_16 = 2 -VGT_GRP_UINT_32 = 3 -VGT_GRP_SINT_16 = 4 -VGT_GRP_SINT_32 = 5 -VGT_GRP_FLOAT_32 = 6 -VGT_GRP_AUTO_PRIM = 7 -VGT_GRP_FIX_1_23_TO_FLOAT = 8 -VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_MODE_TYPE' -VGT_GS_MODE_TYPE__enumvalues = { - 0: 'GS_OFF', - 1: 'GS_SCENARIO_A', - 2: 'GS_SCENARIO_B', - 3: 'GS_SCENARIO_G', - 4: 'GS_SCENARIO_C', - 5: 'SPRITE_EN', -} -GS_OFF = 0 -GS_SCENARIO_A = 1 -GS_SCENARIO_B = 2 -GS_SCENARIO_G = 3 -GS_SCENARIO_C = 4 -SPRITE_EN = 5 -VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_OUTPRIM_TYPE' -VGT_GS_OUTPRIM_TYPE__enumvalues = { - 0: 'POINTLIST', - 1: 'LINESTRIP', - 2: 'TRISTRIP', - 3: 'RECT_2D', - 4: 'RECTLIST', -} -POINTLIST = 0 -LINESTRIP = 1 -TRISTRIP = 2 -RECT_2D = 3 -RECTLIST = 4 -VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_INDEX_TYPE_MODE' -VGT_INDEX_TYPE_MODE__enumvalues = { - 0: 'VGT_INDEX_16', - 1: 'VGT_INDEX_32', - 2: 'VGT_INDEX_8', -} -VGT_INDEX_16 = 0 -VGT_INDEX_32 = 1 -VGT_INDEX_8 = 2 -VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUTPATH_SELECT' -VGT_OUTPATH_SELECT__enumvalues = { - 0: 'VGT_OUTPATH_VTX_REUSE', - 1: 'VGT_OUTPATH_GS_BLOCK', - 2: 'VGT_OUTPATH_HS_BLOCK', - 3: 'VGT_OUTPATH_PRIM_GEN', - 4: 'VGT_OUTPATH_TE_PRIM_GEN', - 5: 'VGT_OUTPATH_TE_GS_BLOCK', - 6: 'VGT_OUTPATH_TE_OUTPUT', -} -VGT_OUTPATH_VTX_REUSE = 0 -VGT_OUTPATH_GS_BLOCK = 1 -VGT_OUTPATH_HS_BLOCK = 2 -VGT_OUTPATH_PRIM_GEN = 3 -VGT_OUTPATH_TE_PRIM_GEN = 4 -VGT_OUTPATH_TE_GS_BLOCK = 5 -VGT_OUTPATH_TE_OUTPUT = 6 -VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUT_PRIM_TYPE' -VGT_OUT_PRIM_TYPE__enumvalues = { - 0: 'VGT_OUT_POINT', - 1: 'VGT_OUT_LINE', - 2: 'VGT_OUT_TRI', - 3: 'VGT_OUT_2D_RECT', - 4: 'VGT_OUT_RECT_V0', - 5: 'VGT_OUT_DUMMY_1', - 6: 'VGT_OUT_DUMMY_2', - 7: 'VGT_OUT_DUMMY_3', - 8: 'VGT_OUT_PATCH', - 9: 'VGT_OUT_LINE_ADJ', - 10: 'VGT_OUT_TRI_ADJ', -} -VGT_OUT_POINT = 0 -VGT_OUT_LINE = 1 -VGT_OUT_TRI = 2 -VGT_OUT_2D_RECT = 3 -VGT_OUT_RECT_V0 = 4 -VGT_OUT_DUMMY_1 = 5 -VGT_OUT_DUMMY_2 = 6 -VGT_OUT_DUMMY_3 = 7 -VGT_OUT_PATCH = 8 -VGT_OUT_LINE_ADJ = 9 -VGT_OUT_TRI_ADJ = 10 -VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_RDREQ_POLICY' -VGT_RDREQ_POLICY__enumvalues = { - 0: 'VGT_POLICY_LRU', - 1: 'VGT_POLICY_STREAM', - 2: 'VGT_POLICY_BYPASS', -} -VGT_POLICY_LRU = 0 -VGT_POLICY_STREAM = 1 -VGT_POLICY_BYPASS = 2 -VGT_RDREQ_POLICY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_SPEC_DATA_READ' -VGT_SPEC_DATA_READ__enumvalues = { - 0: 'VGT_SPEC_DATA_READ_AUTO', - 1: 'VGT_SPEC_DATA_READ_FORCE_ON', - 2: 'VGT_SPEC_DATA_READ_FORCE_OFF', -} -VGT_SPEC_DATA_READ_AUTO = 0 -VGT_SPEC_DATA_READ_FORCE_ON = 1 -VGT_SPEC_DATA_READ_FORCE_OFF = 2 -VGT_SPEC_DATA_READ = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_GS_EN' -VGT_STAGES_GS_EN__enumvalues = { - 0: 'GS_STAGE_OFF', - 1: 'GS_STAGE_ON', -} -GS_STAGE_OFF = 0 -GS_STAGE_ON = 1 -VGT_STAGES_GS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_HS_EN' -VGT_STAGES_HS_EN__enumvalues = { - 0: 'HS_STAGE_OFF', - 1: 'HS_STAGE_ON', -} -HS_STAGE_OFF = 0 -HS_STAGE_ON = 1 -VGT_STAGES_HS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TEMPORAL' -VGT_TEMPORAL__enumvalues = { - 0: 'VGT_TEMPORAL_NORMAL', - 1: 'VGT_TEMPORAL_HIGH_PRIORITY', - 2: 'VGT_TEMPORAL_STREAM', - 3: 'VGT_TEMPORAL_DISCARD', -} -VGT_TEMPORAL_NORMAL = 0 -VGT_TEMPORAL_HIGH_PRIORITY = 1 -VGT_TEMPORAL_STREAM = 2 -VGT_TEMPORAL_DISCARD = 3 -VGT_TEMPORAL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_PARTITION' -VGT_TESS_PARTITION__enumvalues = { - 0: 'PART_INTEGER', - 1: 'PART_POW2', - 2: 'PART_FRAC_ODD', - 3: 'PART_FRAC_EVEN', -} -PART_INTEGER = 0 -PART_POW2 = 1 -PART_FRAC_ODD = 2 -PART_FRAC_EVEN = 3 -VGT_TESS_PARTITION = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TOPOLOGY' -VGT_TESS_TOPOLOGY__enumvalues = { - 0: 'OUTPUT_POINT', - 1: 'OUTPUT_LINE', - 2: 'OUTPUT_TRIANGLE_CW', - 3: 'OUTPUT_TRIANGLE_CCW', -} -OUTPUT_POINT = 0 -OUTPUT_LINE = 1 -OUTPUT_TRIANGLE_CW = 2 -OUTPUT_TRIANGLE_CCW = 3 -VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TYPE' -VGT_TESS_TYPE__enumvalues = { - 0: 'TESS_ISOLINE', - 1: 'TESS_TRIANGLE', - 2: 'TESS_QUAD', -} -TESS_ISOLINE = 0 -TESS_TRIANGLE = 1 -TESS_QUAD = 2 -VGT_TESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_REG_XFER' -WD_IA_DRAW_REG_XFER__enumvalues = { - 0: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 2: 'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE', - 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 4: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE', - 5: 'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL', - 6: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 7: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 8: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 9: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', - 10: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 11: 'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL', - 12: 'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL', - 13: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET', - 14: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN', - 15: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1', - 16: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2', - 17: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3', - 18: 'WD_IA_DRAW_REG_XFER_GE_VRS_RATE', - 19: 'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC', - 20: 'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS', - 21: 'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE', -} -WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0 -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 -WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE = 2 -WD_IA_DRAW_REG_XFER_GE_CNTL = 3 -WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE = 4 -WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL = 5 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 6 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 7 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 8 -WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 9 -WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 10 -WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL = 11 -WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL = 12 -WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET = 13 -WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN = 14 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR1 = 15 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR2 = 16 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR3 = 17 -WD_IA_DRAW_REG_XFER_GE_VRS_RATE = 18 -WD_IA_DRAW_REG_XFER_GE_PC_ALLOC = 19 -WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS = 20 -WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE = 21 -WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_SOURCE' -WD_IA_DRAW_SOURCE__enumvalues = { - 0: 'WD_IA_DRAW_SOURCE_DMA', - 1: 'WD_IA_DRAW_SOURCE_IMMD', - 2: 'WD_IA_DRAW_SOURCE_AUTO', - 3: 'WD_IA_DRAW_SOURCE_OPAQ', -} -WD_IA_DRAW_SOURCE_DMA = 0 -WD_IA_DRAW_SOURCE_IMMD = 1 -WD_IA_DRAW_SOURCE_AUTO = 2 -WD_IA_DRAW_SOURCE_OPAQ = 3 -WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_TYPE' -WD_IA_DRAW_TYPE__enumvalues = { - 0: 'WD_IA_DRAW_TYPE_DI_MM0', - 1: 'WD_IA_DRAW_TYPE_INDX_OFF', - 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', - 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 4: 'WD_IA_DRAW_TYPE_REG_XFER', - 5: 'WD_IA_DRAW_TYPE_MIN_INDX', - 6: 'WD_IA_DRAW_TYPE_MAX_INDX', - 7: 'WD_IA_DRAW_TYPE_IMM_DATA', -} -WD_IA_DRAW_TYPE_DI_MM0 = 0 -WD_IA_DRAW_TYPE_INDX_OFF = 1 -WD_IA_DRAW_TYPE_EVENT_INIT = 2 -WD_IA_DRAW_TYPE_EVENT_ADDR = 3 -WD_IA_DRAW_TYPE_REG_XFER = 4 -WD_IA_DRAW_TYPE_MIN_INDX = 5 -WD_IA_DRAW_TYPE_MAX_INDX = 6 -WD_IA_DRAW_TYPE_IMM_DATA = 7 -WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CHA_PERF_SEL' -CHA_PERF_SEL__enumvalues = { - 0: 'CHA_PERF_SEL_BUSY', - 1: 'CHA_PERF_SEL_STALL_CHC0', - 2: 'CHA_PERF_SEL_STALL_CHC1', - 3: 'CHA_PERF_SEL_STALL_CHC2', - 4: 'CHA_PERF_SEL_STALL_CHC3', - 5: 'CHA_PERF_SEL_REQUEST_CHC0', - 6: 'CHA_PERF_SEL_REQUEST_CHC1', - 7: 'CHA_PERF_SEL_REQUEST_CHC2', - 8: 'CHA_PERF_SEL_REQUEST_CHC3', - 9: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', - 10: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 11: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', - 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 13: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 14: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', - 15: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 16: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 17: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 18: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 19: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 20: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 21: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 22: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 23: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 24: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 25: 'CHA_PERF_SEL_ARB_REQUESTS', - 26: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 27: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 28: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 29: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 30: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 31: 'CHA_PERF_SEL_CYCLE', -} -CHA_PERF_SEL_BUSY = 0 -CHA_PERF_SEL_STALL_CHC0 = 1 -CHA_PERF_SEL_STALL_CHC1 = 2 -CHA_PERF_SEL_STALL_CHC2 = 3 -CHA_PERF_SEL_STALL_CHC3 = 4 -CHA_PERF_SEL_REQUEST_CHC0 = 5 -CHA_PERF_SEL_REQUEST_CHC1 = 6 -CHA_PERF_SEL_REQUEST_CHC2 = 7 -CHA_PERF_SEL_REQUEST_CHC3 = 8 -CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 9 -CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 10 -CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 11 -CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 12 -CHA_PERF_SEL_IO_32B_WDS_CHC0 = 13 -CHA_PERF_SEL_IO_32B_WDS_CHC1 = 14 -CHA_PERF_SEL_IO_32B_WDS_CHC2 = 15 -CHA_PERF_SEL_IO_32B_WDS_CHC3 = 16 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 17 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 18 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 19 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 20 -CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 21 -CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 22 -CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 23 -CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 24 -CHA_PERF_SEL_ARB_REQUESTS = 25 -CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 26 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 27 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 28 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 29 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 30 -CHA_PERF_SEL_CYCLE = 31 -CHA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHC_PERF_SEL' -CHC_PERF_SEL__enumvalues = { - 0: 'CHC_PERF_SEL_CYCLE', - 1: 'CHC_PERF_SEL_BUSY', - 2: 'CHC_PERF_SEL_STARVE', - 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', - 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'CHC_PERF_SEL_REQ', - 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'CHC_PERF_SEL_REQ_NOP_ACK', - 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', - 11: 'CHC_PERF_SEL_REQ_READ', - 12: 'CHC_PERF_SEL_REQ_READ_128B', - 13: 'CHC_PERF_SEL_REQ_READ_32B', - 14: 'CHC_PERF_SEL_REQ_READ_64B', - 15: 'CHC_PERF_SEL_REQ_WRITE', - 16: 'CHC_PERF_SEL_REQ_WRITE_32B', - 17: 'CHC_PERF_SEL_REQ_WRITE_64B', - 18: 'CHC_PERF_SEL_STALL_GL2_GL1', - 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', - 20: 'CHC_PERF_SEL_REQ_CLIENT0', - 21: 'CHC_PERF_SEL_REQ_CLIENT1', - 22: 'CHC_PERF_SEL_REQ_CLIENT2', - 23: 'CHC_PERF_SEL_REQ_CLIENT3', - 24: 'CHC_PERF_SEL_REQ_CLIENT4', - 25: 'CHC_PERF_SEL_REQ_CLIENT5', - 26: 'CHC_PERF_SEL_REQ_CLIENT6', - 27: 'CHC_PERF_SEL_REQ_CLIENT7', - 28: 'CHC_PERF_SEL_REQ_CLIENT8', - 29: 'CHC_PERF_SEL_REQ_CLIENT9', - 30: 'CHC_PERF_SEL_REQ_CLIENT10', - 31: 'CHC_PERF_SEL_REQ_CLIENT11', - 32: 'CHC_PERF_SEL_REQ_CLIENT12', - 33: 'CHC_PERF_SEL_REQ_CLIENT13', - 34: 'CHC_PERF_SEL_REQ_CLIENT14', - 35: 'CHC_PERF_SEL_REQ_CLIENT15', - 36: 'CHC_PERF_SEL_REQ_CLIENT16', - 37: 'CHC_PERF_SEL_REQ_CLIENT17', - 38: 'CHC_PERF_SEL_REQ_CLIENT18', - 39: 'CHC_PERF_SEL_REQ_CLIENT19', - 40: 'CHC_PERF_SEL_REQ_CLIENT20', - 41: 'CHC_PERF_SEL_REQ_CLIENT21', - 42: 'CHC_PERF_SEL_REQ_CLIENT22', - 43: 'CHC_PERF_SEL_REQ_CLIENT23', -} -CHC_PERF_SEL_CYCLE = 0 -CHC_PERF_SEL_BUSY = 1 -CHC_PERF_SEL_STARVE = 2 -CHC_PERF_SEL_ARB_RET_LEVEL = 3 -CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -CHC_PERF_SEL_REQ = 6 -CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -CHC_PERF_SEL_REQ_NOP_ACK = 9 -CHC_PERF_SEL_REQ_NOP_RTN0 = 10 -CHC_PERF_SEL_REQ_READ = 11 -CHC_PERF_SEL_REQ_READ_128B = 12 -CHC_PERF_SEL_REQ_READ_32B = 13 -CHC_PERF_SEL_REQ_READ_64B = 14 -CHC_PERF_SEL_REQ_WRITE = 15 -CHC_PERF_SEL_REQ_WRITE_32B = 16 -CHC_PERF_SEL_REQ_WRITE_64B = 17 -CHC_PERF_SEL_STALL_GL2_GL1 = 18 -CHC_PERF_SEL_STALL_BUFFER_FULL = 19 -CHC_PERF_SEL_REQ_CLIENT0 = 20 -CHC_PERF_SEL_REQ_CLIENT1 = 21 -CHC_PERF_SEL_REQ_CLIENT2 = 22 -CHC_PERF_SEL_REQ_CLIENT3 = 23 -CHC_PERF_SEL_REQ_CLIENT4 = 24 -CHC_PERF_SEL_REQ_CLIENT5 = 25 -CHC_PERF_SEL_REQ_CLIENT6 = 26 -CHC_PERF_SEL_REQ_CLIENT7 = 27 -CHC_PERF_SEL_REQ_CLIENT8 = 28 -CHC_PERF_SEL_REQ_CLIENT9 = 29 -CHC_PERF_SEL_REQ_CLIENT10 = 30 -CHC_PERF_SEL_REQ_CLIENT11 = 31 -CHC_PERF_SEL_REQ_CLIENT12 = 32 -CHC_PERF_SEL_REQ_CLIENT13 = 33 -CHC_PERF_SEL_REQ_CLIENT14 = 34 -CHC_PERF_SEL_REQ_CLIENT15 = 35 -CHC_PERF_SEL_REQ_CLIENT16 = 36 -CHC_PERF_SEL_REQ_CLIENT17 = 37 -CHC_PERF_SEL_REQ_CLIENT18 = 38 -CHC_PERF_SEL_REQ_CLIENT19 = 39 -CHC_PERF_SEL_REQ_CLIENT20 = 40 -CHC_PERF_SEL_REQ_CLIENT21 = 41 -CHC_PERF_SEL_REQ_CLIENT22 = 42 -CHC_PERF_SEL_REQ_CLIENT23 = 43 -CHC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_PERF_SEL' -GRBM_PERF_SEL__enumvalues = { - 0: 'GRBM_PERF_SEL_COUNT', - 1: 'GRBM_PERF_SEL_USER_DEFINED', - 2: 'GRBM_PERF_SEL_GUI_ACTIVE', - 3: 'GRBM_PERF_SEL_CP_BUSY', - 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', - 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', - 6: 'GRBM_PERF_SEL_CB_BUSY', - 7: 'GRBM_PERF_SEL_DB_BUSY', - 8: 'GRBM_PERF_SEL_PA_BUSY', - 9: 'GRBM_PERF_SEL_SC_BUSY', - 11: 'GRBM_PERF_SEL_SPI_BUSY', - 12: 'GRBM_PERF_SEL_SX_BUSY', - 13: 'GRBM_PERF_SEL_TA_BUSY', - 14: 'GRBM_PERF_SEL_CB_CLEAN', - 15: 'GRBM_PERF_SEL_DB_CLEAN', - 26: 'GRBM_PERF_SEL_BCI_BUSY', - 27: 'GRBM_PERF_SEL_RLC_BUSY', - 28: 'GRBM_PERF_SEL_TCP_BUSY', - 29: 'GRBM_PERF_SEL_CPG_BUSY', - 30: 'GRBM_PERF_SEL_CPC_BUSY', - 31: 'GRBM_PERF_SEL_CPF_BUSY', - 32: 'GRBM_PERF_SEL_GE_BUSY', - 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 34: 'GRBM_PERF_SEL_UTCL2_BUSY', - 35: 'GRBM_PERF_SEL_EA_BUSY', - 39: 'GRBM_PERF_SEL_UTCL1_BUSY', - 40: 'GRBM_PERF_SEL_GL2CC_BUSY', - 41: 'GRBM_PERF_SEL_SDMA_BUSY', - 42: 'GRBM_PERF_SEL_CH_BUSY', - 44: 'GRBM_PERF_SEL_PMM_BUSY', - 45: 'GRBM_PERF_SEL_GUS_BUSY', - 46: 'GRBM_PERF_SEL_GL1CC_BUSY', - 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 48: 'GRBM_PERF_SEL_GL1XCC_BUSY', - 49: 'GRBM_PERF_SEL_PC_BUSY', -} -GRBM_PERF_SEL_COUNT = 0 -GRBM_PERF_SEL_USER_DEFINED = 1 -GRBM_PERF_SEL_GUI_ACTIVE = 2 -GRBM_PERF_SEL_CP_BUSY = 3 -GRBM_PERF_SEL_CP_COHER_BUSY = 4 -GRBM_PERF_SEL_CP_DMA_BUSY = 5 -GRBM_PERF_SEL_CB_BUSY = 6 -GRBM_PERF_SEL_DB_BUSY = 7 -GRBM_PERF_SEL_PA_BUSY = 8 -GRBM_PERF_SEL_SC_BUSY = 9 -GRBM_PERF_SEL_SPI_BUSY = 11 -GRBM_PERF_SEL_SX_BUSY = 12 -GRBM_PERF_SEL_TA_BUSY = 13 -GRBM_PERF_SEL_CB_CLEAN = 14 -GRBM_PERF_SEL_DB_CLEAN = 15 -GRBM_PERF_SEL_BCI_BUSY = 26 -GRBM_PERF_SEL_RLC_BUSY = 27 -GRBM_PERF_SEL_TCP_BUSY = 28 -GRBM_PERF_SEL_CPG_BUSY = 29 -GRBM_PERF_SEL_CPC_BUSY = 30 -GRBM_PERF_SEL_CPF_BUSY = 31 -GRBM_PERF_SEL_GE_BUSY = 32 -GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 -GRBM_PERF_SEL_UTCL2_BUSY = 34 -GRBM_PERF_SEL_EA_BUSY = 35 -GRBM_PERF_SEL_UTCL1_BUSY = 39 -GRBM_PERF_SEL_GL2CC_BUSY = 40 -GRBM_PERF_SEL_SDMA_BUSY = 41 -GRBM_PERF_SEL_CH_BUSY = 42 -GRBM_PERF_SEL_PMM_BUSY = 44 -GRBM_PERF_SEL_GUS_BUSY = 45 -GRBM_PERF_SEL_GL1CC_BUSY = 46 -GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 -GRBM_PERF_SEL_GL1XCC_BUSY = 48 -GRBM_PERF_SEL_PC_BUSY = 49 -GRBM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_LATENCY_STATS_SEL' -CPC_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', -} -CPC_LATENCY_STATS_SEL_XACK_MAX = 0 -CPC_LATENCY_STATS_SEL_XACK_MIN = 1 -CPC_LATENCY_STATS_SEL_XACK_LAST = 2 -CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 -CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 -CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 -CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_PERFCOUNT_SEL' -CPC_PERFCOUNT_SEL__enumvalues = { - 0: 'CPC_PERF_SEL_ALWAYS_COUNT', - 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ', - 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE', - 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ', - 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE', - 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', - 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', - 27: 'CPC_PERF_SEL_CPC_STAT_STALL', - 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', - 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', - 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', - 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', - 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', - 45: 'CPC_PERF_SEL_MES_THREAD0', - 46: 'CPC_PERF_SEL_MES_THREAD1', - 47: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 48: 'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 49: 'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT', - 50: 'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 51: 'CPC_PERF_SEL_GUS_READ_REQUEST_SENT', - 52: 'CPC_PERF_SEL_MEC_THREAD0', - 53: 'CPC_PERF_SEL_MEC_THREAD1', - 54: 'CPC_PERF_SEL_MEC_THREAD2', - 55: 'CPC_PERF_SEL_MEC_THREAD3', -} -CPC_PERF_SEL_ALWAYS_COUNT = 0 -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ = 9 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE = 10 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ = 17 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE = 18 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 -CPC_PERF_SEL_CPC_STAT_BUSY = 25 -CPC_PERF_SEL_CPC_STAT_IDLE = 26 -CPC_PERF_SEL_CPC_STAT_STALL = 27 -CPC_PERF_SEL_CPC_TCIU_BUSY = 28 -CPC_PERF_SEL_CPC_TCIU_IDLE = 29 -CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 -CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 -CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 -CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 -CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 -CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 -CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 -CPC_PERF_SEL_CPC_GCRIU_STALL = 37 -CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 -CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 -CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 -CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 -CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 -CPC_PERF_SEL_MES_THREAD0 = 45 -CPC_PERF_SEL_MES_THREAD1 = 46 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 47 -CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 48 -CPC_PERF_SEL_TCIU_READ_REQUEST_SENT = 49 -CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT = 50 -CPC_PERF_SEL_GUS_READ_REQUEST_SENT = 51 -CPC_PERF_SEL_MEC_THREAD0 = 52 -CPC_PERF_SEL_MEC_THREAD1 = 53 -CPC_PERF_SEL_MEC_THREAD2 = 54 -CPC_PERF_SEL_MEC_THREAD3 = 55 -CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_LATENCY_STATS_SEL' -CPF_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', - 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', - 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', - 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', -} -CPF_LATENCY_STATS_SEL_XACK_MAX = 0 -CPF_LATENCY_STATS_SEL_XACK_MIN = 1 -CPF_LATENCY_STATS_SEL_XACK_LAST = 2 -CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPF_LATENCY_STATS_SEL_READ_MAX = 6 -CPF_LATENCY_STATS_SEL_READ_MIN = 7 -CPF_LATENCY_STATS_SEL_READ_LAST = 8 -CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 -CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 -CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 -CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' -CPF_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPF_PERFWINDOW_SEL_CSF', - 1: 'CPF_PERFWINDOW_SEL_HQD1', - 2: 'CPF_PERFWINDOW_SEL_HQD2', - 3: 'CPF_PERFWINDOW_SEL_RDMA', - 4: 'CPF_PERFWINDOW_SEL_RWPP', -} -CPF_PERFWINDOW_SEL_CSF = 0 -CPF_PERFWINDOW_SEL_HQD1 = 1 -CPF_PERFWINDOW_SEL_HQD2 = 2 -CPF_PERFWINDOW_SEL_RDMA = 3 -CPF_PERFWINDOW_SEL_RWPP = 4 -CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNT_SEL' -CPF_PERFCOUNT_SEL__enumvalues = { - 0: 'CPF_PERF_SEL_ALWAYS_COUNT', - 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', - 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', - 26: 'CPF_PERF_SEL_CPF_STAT_STALL', - 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', - 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', - 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', - 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', - 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', - 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', - 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', -} -CPF_PERF_SEL_ALWAYS_COUNT = 0 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 -CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 -CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 -CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 -CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 -CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 -CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 -CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 -CPF_PERF_SEL_CPF_STAT_BUSY = 24 -CPF_PERF_SEL_CPF_STAT_IDLE = 25 -CPF_PERF_SEL_CPF_STAT_STALL = 26 -CPF_PERF_SEL_CPF_TCIU_BUSY = 27 -CPF_PERF_SEL_CPF_TCIU_IDLE = 28 -CPF_PERF_SEL_CPF_TCIU_STALL = 29 -CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 -CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 -CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 -CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 -CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 -CPF_PERF_SEL_CPF_GCRIU_STALL = 35 -CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 -CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 -CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 -CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 -CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 -CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' -CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { - 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', - 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', - 2: 'CPF_SCRATCH_REG_ATOMIC_OR', - 3: 'CPF_SCRATCH_REG_ATOMIC_AND', - 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', - 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', - 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', - 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', -} -CPF_SCRATCH_REG_ATOMIC_ADD = 0 -CPF_SCRATCH_REG_ATOMIC_SUB = 1 -CPF_SCRATCH_REG_ATOMIC_OR = 2 -CPF_SCRATCH_REG_ATOMIC_AND = 3 -CPF_SCRATCH_REG_ATOMIC_NOT = 4 -CPF_SCRATCH_REG_ATOMIC_MIN = 5 -CPF_SCRATCH_REG_ATOMIC_MAX = 6 -CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 -CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_LATENCY_STATS_SEL' -CPG_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', - 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', - 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', - 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', -} -CPG_LATENCY_STATS_SEL_XACK_MAX = 0 -CPG_LATENCY_STATS_SEL_XACK_MIN = 1 -CPG_LATENCY_STATS_SEL_XACK_LAST = 2 -CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 -CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 -CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 -CPG_LATENCY_STATS_SEL_READ_MAX = 9 -CPG_LATENCY_STATS_SEL_READ_MIN = 10 -CPG_LATENCY_STATS_SEL_READ_LAST = 11 -CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 -CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 -CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 -CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 -CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 -CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 -CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' -CPG_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPG_PERFWINDOW_SEL_PFP', - 1: 'CPG_PERFWINDOW_SEL_ME', - 2: 'CPG_PERFWINDOW_SEL_CE', - 3: 'CPG_PERFWINDOW_SEL_MES', - 4: 'CPG_PERFWINDOW_SEL_MEC1', - 5: 'CPG_PERFWINDOW_SEL_MEC2', - 6: 'CPG_PERFWINDOW_SEL_DFY', - 7: 'CPG_PERFWINDOW_SEL_DMA', - 8: 'CPG_PERFWINDOW_SEL_SHADOW', - 9: 'CPG_PERFWINDOW_SEL_RB', - 10: 'CPG_PERFWINDOW_SEL_CEDMA', - 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', - 13: 'CPG_PERFWINDOW_SEL_PQ1', - 14: 'CPG_PERFWINDOW_SEL_PQ2', - 15: 'CPG_PERFWINDOW_SEL_PQ3', - 16: 'CPG_PERFWINDOW_SEL_MEMWR', - 17: 'CPG_PERFWINDOW_SEL_MEMRD', - 18: 'CPG_PERFWINDOW_SEL_VGT0', - 19: 'CPG_PERFWINDOW_SEL_VGT1', - 20: 'CPG_PERFWINDOW_SEL_APPEND', - 21: 'CPG_PERFWINDOW_SEL_QURD', - 22: 'CPG_PERFWINDOW_SEL_DDID', - 23: 'CPG_PERFWINDOW_SEL_SR', - 24: 'CPG_PERFWINDOW_SEL_QU_EOP', - 25: 'CPG_PERFWINDOW_SEL_QU_STRM', - 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', - 27: 'CPG_PERFWINDOW_SEL_RESERVED1', - 28: 'CPG_PERFWINDOW_SEL_CPC_IC', - 29: 'CPG_PERFWINDOW_SEL_RESERVED2', - 30: 'CPG_PERFWINDOW_SEL_CPG_IC', -} -CPG_PERFWINDOW_SEL_PFP = 0 -CPG_PERFWINDOW_SEL_ME = 1 -CPG_PERFWINDOW_SEL_CE = 2 -CPG_PERFWINDOW_SEL_MES = 3 -CPG_PERFWINDOW_SEL_MEC1 = 4 -CPG_PERFWINDOW_SEL_MEC2 = 5 -CPG_PERFWINDOW_SEL_DFY = 6 -CPG_PERFWINDOW_SEL_DMA = 7 -CPG_PERFWINDOW_SEL_SHADOW = 8 -CPG_PERFWINDOW_SEL_RB = 9 -CPG_PERFWINDOW_SEL_CEDMA = 10 -CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 -CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 -CPG_PERFWINDOW_SEL_PQ1 = 13 -CPG_PERFWINDOW_SEL_PQ2 = 14 -CPG_PERFWINDOW_SEL_PQ3 = 15 -CPG_PERFWINDOW_SEL_MEMWR = 16 -CPG_PERFWINDOW_SEL_MEMRD = 17 -CPG_PERFWINDOW_SEL_VGT0 = 18 -CPG_PERFWINDOW_SEL_VGT1 = 19 -CPG_PERFWINDOW_SEL_APPEND = 20 -CPG_PERFWINDOW_SEL_QURD = 21 -CPG_PERFWINDOW_SEL_DDID = 22 -CPG_PERFWINDOW_SEL_SR = 23 -CPG_PERFWINDOW_SEL_QU_EOP = 24 -CPG_PERFWINDOW_SEL_QU_STRM = 25 -CPG_PERFWINDOW_SEL_QU_PIPE = 26 -CPG_PERFWINDOW_SEL_RESERVED1 = 27 -CPG_PERFWINDOW_SEL_CPC_IC = 28 -CPG_PERFWINDOW_SEL_RESERVED2 = 29 -CPG_PERFWINDOW_SEL_CPG_IC = 30 -CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNT_SEL' -CPG_PERFCOUNT_SEL__enumvalues = { - 0: 'CPG_PERF_SEL_ALWAYS_COUNT', - 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', - 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', - 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', - 53: 'CPG_PERF_SEL_CPG_STAT_STALL', - 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', - 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', - 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', - 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', - 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', - 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', - 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', - 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 78: 'CPG_PERF_SEL_DMA_BUSY', - 79: 'CPG_PERF_SEL_DMA_STARVED', - 80: 'CPG_PERF_SEL_DMA_STALLED', - 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', - 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', - 84: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0', - 85: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0', - 86: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0', - 87: 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 88: 'CPG_PERF_SEL_ME_PWS_STALLED1', - 89: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1', - 90: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1', - 91: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1', -} -CPG_PERF_SEL_ALWAYS_COUNT = 0 -CPG_PERF_SEL_RBIU_FIFO_FULL = 1 -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 -CPG_PERF_SEL_ME_PARSER_BUSY = 5 -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 -CPG_PERF_SEL_REGISTER_CLK_VALID = 33 -CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 -CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 -CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 -CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 -CPG_PERF_SEL_CPG_STAT_BUSY = 51 -CPG_PERF_SEL_CPG_STAT_IDLE = 52 -CPG_PERF_SEL_CPG_STAT_STALL = 53 -CPG_PERF_SEL_CPG_TCIU_BUSY = 54 -CPG_PERF_SEL_CPG_TCIU_IDLE = 55 -CPG_PERF_SEL_CPG_TCIU_STALL = 56 -CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 -CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 -CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 -CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 -CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 -CPG_PERF_SEL_CPG_GCRIU_STALL = 62 -CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 -CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 -CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 -CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 -CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 -CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 -CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 -CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 -CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 -CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 -CPG_PERF_SEL_DMA_BUSY = 78 -CPG_PERF_SEL_DMA_STARVED = 79 -CPG_PERF_SEL_DMA_STALLED = 80 -CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 -CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 -CPG_PERF_SEL_ME_PWS_STALLED0 = 83 -CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0 = 84 -CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0 = 85 -CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0 = 86 -CPG_PERF_SEL_PFP_PWS_STALLED1 = 87 -CPG_PERF_SEL_ME_PWS_STALLED1 = 88 -CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1 = 89 -CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1 = 90 -CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1 = 91 -CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' -CP_ALPHA_TAG_RAM_SEL__enumvalues = { - 0: 'CPG_TAG_RAM', - 1: 'CPC_TAG_RAM', - 2: 'CPF_TAG_RAM', - 3: 'RSV_TAG_RAM', -} -CPG_TAG_RAM = 0 -CPC_TAG_RAM = 1 -CPF_TAG_RAM = 2 -RSV_TAG_RAM = 3 -CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_MODE' -CP_DDID_CNTL_MODE__enumvalues = { - 0: 'STALL', - 1: 'OVERRUN', -} -STALL = 0 -OVERRUN = 1 -CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_SIZE' -CP_DDID_CNTL_SIZE__enumvalues = { - 0: 'SIZE_8K', - 1: 'SIZE_16K', -} -SIZE_8K = 0 -SIZE_16K = 1 -CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_VMID_SEL' -CP_DDID_CNTL_VMID_SEL__enumvalues = { - 0: 'DDID_VMID_PIPE', - 1: 'DDID_VMID_CNTL', -} -DDID_VMID_PIPE = 0 -DDID_VMID_CNTL = 1 -CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ME_ID' -CP_ME_ID__enumvalues = { - 0: 'ME_ID0', - 1: 'ME_ID1', - 2: 'ME_ID2', - 3: 'ME_ID3', -} -ME_ID0 = 0 -ME_ID1 = 1 -ME_ID2 = 2 -ME_ID3 = 3 -CP_ME_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PIPE_ID' -CP_PIPE_ID__enumvalues = { - 0: 'PIPE_ID0', - 1: 'PIPE_ID1', - 2: 'PIPE_ID2', - 3: 'PIPE_ID3', -} -PIPE_ID0 = 0 -PIPE_ID1 = 1 -PIPE_ID2 = 2 -PIPE_ID3 = 3 -CP_PIPE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_RING_ID' -CP_RING_ID__enumvalues = { - 0: 'RINGID0', - 1: 'RINGID1', - 2: 'RINGID2', - 3: 'RINGID3', -} -RINGID0 = 0 -RINGID1 = 1 -RINGID2 = 2 -RINGID3 = 3 -CP_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'GCRPerfSel' -GCRPerfSel__enumvalues = { - 0: 'GCR_PERF_SEL_NONE', - 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', - 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 16: 'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ', - 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', - 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', - 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 32: 'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ', - 33: 'GCR_PERF_SEL_CPC_ALL_REQ', - 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', - 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', - 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', - 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', - 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 47: 'GCR_PERF_SEL_CPC_TCP_REQ', - 48: 'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ', - 49: 'GCR_PERF_SEL_CPG_ALL_REQ', - 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', - 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', - 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', - 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', - 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 63: 'GCR_PERF_SEL_CPG_TCP_REQ', - 64: 'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ', - 65: 'GCR_PERF_SEL_CPF_ALL_REQ', - 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', - 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', - 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', - 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', - 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 79: 'GCR_PERF_SEL_CPF_TCP_REQ', - 80: 'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ', - 81: 'GCR_PERF_SEL_VIRT_REQ', - 82: 'GCR_PERF_SEL_PHY_REQ', - 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 85: 'GCR_PERF_SEL_ALL_REQ', - 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 89: 'GCR_PERF_SEL_UTCL2_REQ', - 90: 'GCR_PERF_SEL_UTCL2_RET', - 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 94: 'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH', - 95: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING', - 96: 'GCR_PERF_SEL_PMM_NUM_INTERRUPT', - 97: 'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS', - 98: 'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND', - 99: 'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH', - 100: 'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH', - 101: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT', - 102: 'GCR_PERF_SEL_PMM_ALOG_INTERRUPT', - 103: 'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ', - 104: 'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP', - 105: 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ', - 106: 'GCR_PERF_SEL_PMM_RLC_CGCG_RESP', - 107: 'GCR_PERF_SEL_RLC_ALL_REQ', - 108: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', - 109: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 110: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 111: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 112: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 113: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', - 114: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 115: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 116: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 117: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 118: 'GCR_PERF_SEL_RLC_METADATA_REQ', - 119: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', - 120: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 121: 'GCR_PERF_SEL_RLC_TCP_REQ', - 122: 'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ', - 123: 'GCR_PERF_SEL_PM_ALL_REQ', - 124: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', - 125: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 126: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 127: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 128: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 129: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', - 130: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 131: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 132: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 133: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 134: 'GCR_PERF_SEL_PM_METADATA_REQ', - 135: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', - 136: 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 137: 'GCR_PERF_SEL_PM_TCP_REQ', - 138: 'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ', - 139: 'GCR_PERF_SEL_PIO_ALL_REQ', - 140: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', - 141: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 142: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 143: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 144: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 145: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', - 146: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 147: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 148: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 149: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 150: 'GCR_PERF_SEL_PIO_METADATA_REQ', - 151: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', - 152: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 153: 'GCR_PERF_SEL_PIO_TCP_REQ', - 154: 'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ', -} -GCR_PERF_SEL_NONE = 0 -GCR_PERF_SEL_SDMA0_ALL_REQ = 1 -GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 -GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 -GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 -GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 -GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 -GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 -GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 -GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 -GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 -GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 -GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 -GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 -GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 -GCR_PERF_SEL_SDMA0_TCP_REQ = 15 -GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ = 16 -GCR_PERF_SEL_SDMA1_ALL_REQ = 17 -GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 -GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 -GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 -GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 -GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 -GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 -GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 -GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 -GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 -GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 -GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 -GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 -GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 -GCR_PERF_SEL_SDMA1_TCP_REQ = 31 -GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ = 32 -GCR_PERF_SEL_CPC_ALL_REQ = 33 -GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 -GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 -GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 -GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 -GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 -GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 -GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 -GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 -GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 -GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 -GCR_PERF_SEL_CPC_METADATA_REQ = 44 -GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 -GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 -GCR_PERF_SEL_CPC_TCP_REQ = 47 -GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ = 48 -GCR_PERF_SEL_CPG_ALL_REQ = 49 -GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 -GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 -GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 -GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 -GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 -GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 -GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 -GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 -GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 -GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 -GCR_PERF_SEL_CPG_METADATA_REQ = 60 -GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 -GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 -GCR_PERF_SEL_CPG_TCP_REQ = 63 -GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ = 64 -GCR_PERF_SEL_CPF_ALL_REQ = 65 -GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 -GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 -GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 -GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 -GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 -GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 -GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 -GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 -GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 -GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 -GCR_PERF_SEL_CPF_METADATA_REQ = 76 -GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 -GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 -GCR_PERF_SEL_CPF_TCP_REQ = 79 -GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ = 80 -GCR_PERF_SEL_VIRT_REQ = 81 -GCR_PERF_SEL_PHY_REQ = 82 -GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 -GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 -GCR_PERF_SEL_ALL_REQ = 85 -GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 -GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 -GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 -GCR_PERF_SEL_UTCL2_REQ = 89 -GCR_PERF_SEL_UTCL2_RET = 90 -GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 -GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 -GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 -GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH = 94 -GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING = 95 -GCR_PERF_SEL_PMM_NUM_INTERRUPT = 96 -GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS = 97 -GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND = 98 -GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH = 99 -GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH = 100 -GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT = 101 -GCR_PERF_SEL_PMM_ALOG_INTERRUPT = 102 -GCR_PERF_SEL_PMM_MAM_FLUSH_REQ = 103 -GCR_PERF_SEL_PMM_MAM_FLUSH_RESP = 104 -GCR_PERF_SEL_PMM_RLC_CGCG_REQ = 105 -GCR_PERF_SEL_PMM_RLC_CGCG_RESP = 106 -GCR_PERF_SEL_RLC_ALL_REQ = 107 -GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 108 -GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 109 -GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 110 -GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 111 -GCR_PERF_SEL_RLC_GL2_ALL_REQ = 112 -GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 113 -GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 114 -GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 115 -GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 116 -GCR_PERF_SEL_RLC_GL1_ALL_REQ = 117 -GCR_PERF_SEL_RLC_METADATA_REQ = 118 -GCR_PERF_SEL_RLC_SQC_DATA_REQ = 119 -GCR_PERF_SEL_RLC_SQC_INST_REQ = 120 -GCR_PERF_SEL_RLC_TCP_REQ = 121 -GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ = 122 -GCR_PERF_SEL_PM_ALL_REQ = 123 -GCR_PERF_SEL_PM_GL2_RANGE_REQ = 124 -GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 125 -GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 126 -GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 127 -GCR_PERF_SEL_PM_GL2_ALL_REQ = 128 -GCR_PERF_SEL_PM_GL1_RANGE_REQ = 129 -GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 130 -GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 131 -GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 132 -GCR_PERF_SEL_PM_GL1_ALL_REQ = 133 -GCR_PERF_SEL_PM_METADATA_REQ = 134 -GCR_PERF_SEL_PM_SQC_DATA_REQ = 135 -GCR_PERF_SEL_PM_SQC_INST_REQ = 136 -GCR_PERF_SEL_PM_TCP_REQ = 137 -GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ = 138 -GCR_PERF_SEL_PIO_ALL_REQ = 139 -GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 140 -GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 141 -GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 142 -GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 143 -GCR_PERF_SEL_PIO_GL2_ALL_REQ = 144 -GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 145 -GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 146 -GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 147 -GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 148 -GCR_PERF_SEL_PIO_GL1_ALL_REQ = 149 -GCR_PERF_SEL_PIO_METADATA_REQ = 150 -GCR_PERF_SEL_PIO_SQC_DATA_REQ = 151 -GCR_PERF_SEL_PIO_SQC_INST_REQ = 152 -GCR_PERF_SEL_PIO_TCP_REQ = 153 -GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ = 154 -GCRPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'GC_EA_CPWD_PERFCOUNT_SEL' -GC_EA_CPWD_PERFCOUNT_SEL__enumvalues = { - 0: 'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT', - 1: 'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD', - 2: 'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP', - 3: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', - 4: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0', - 5: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0', - 6: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1', - 7: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1', - 8: 'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD', - 9: 'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP', - 10: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', - 11: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0', - 12: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0', - 13: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1', - 14: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1', - 15: 'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD', - 16: 'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP', - 17: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', - 18: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0', - 19: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0', - 20: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1', - 21: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1', - 22: 'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD', - 23: 'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP', - 24: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', - 25: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0', - 26: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0', - 27: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1', - 28: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1', - 29: 'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP', - 30: 'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ', - 31: 'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ', - 32: 'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ', - 33: 'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ', - 34: 'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ', - 35: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0', - 36: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0', - 37: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1', - 38: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1', - 39: 'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP', - 40: 'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', - 41: 'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ', - 42: 'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ', - 43: 'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ', - 44: 'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ', - 45: 'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ', - 46: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0', - 47: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0', - 48: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1', - 49: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1', - 50: 'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC', - 51: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC', - 52: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC', - 53: 'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC', - 54: 'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ', - 55: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ', - 56: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ', - 57: 'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ', - 58: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0', - 59: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0', - 60: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1', - 61: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1', - 62: 'GC_EA_CPWD_PERF_SEL_SARB_BUSY', - 63: 'GC_EA_CPWD_PERF_SEL_SARB_STALLED', - 64: 'GC_EA_CPWD_PERF_SEL_SARB_STARVING', - 65: 'GC_EA_CPWD_PERF_SEL_SARB_IDLE', - 66: 'GC_EA_CPWD_PERF_SEL_RRET_VLD', - 67: 'GC_EA_CPWD_PERF_SEL_WRET_VLD', - 68: 'GC_EA_CPWD_PERF_SEL_PRB_REQ', - 69: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT', - 70: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD', - 71: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT', - 72: 'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY', - 73: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT', - 74: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', - 75: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED', - 76: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING', - 77: 'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ', - 78: 'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ', - 79: 'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ', - 80: 'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ', - 81: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', - 82: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND', - 83: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 84: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 85: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 86: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 87: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT', - 88: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD', - 89: 'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ', - 90: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', - 91: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', - 92: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ', - 93: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP', - 94: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', - 95: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', - 96: 'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING', - 97: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT', -} -GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT = 0 -GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1 -GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2 -GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3 -GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0 = 4 -GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0 = 5 -GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1 = 6 -GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1 = 7 -GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8 -GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9 -GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10 -GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0 = 11 -GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0 = 12 -GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1 = 13 -GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1 = 14 -GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD = 15 -GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16 -GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17 -GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0 = 18 -GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0 = 19 -GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1 = 20 -GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1 = 21 -GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD = 22 -GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23 -GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24 -GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0 = 25 -GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0 = 26 -GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1 = 27 -GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1 = 28 -GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP = 29 -GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ = 30 -GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ = 31 -GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ = 32 -GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ = 33 -GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ = 34 -GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0 = 35 -GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0 = 36 -GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1 = 37 -GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1 = 38 -GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP = 39 -GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40 -GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ = 41 -GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ = 42 -GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ = 43 -GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ = 44 -GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ = 45 -GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0 = 46 -GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0 = 47 -GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1 = 48 -GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1 = 49 -GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC = 50 -GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51 -GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC = 52 -GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC = 53 -GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ = 54 -GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ = 55 -GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ = 56 -GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ = 57 -GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0 = 58 -GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0 = 59 -GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1 = 60 -GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1 = 61 -GC_EA_CPWD_PERF_SEL_SARB_BUSY = 62 -GC_EA_CPWD_PERF_SEL_SARB_STALLED = 63 -GC_EA_CPWD_PERF_SEL_SARB_STARVING = 64 -GC_EA_CPWD_PERF_SEL_SARB_IDLE = 65 -GC_EA_CPWD_PERF_SEL_RRET_VLD = 66 -GC_EA_CPWD_PERF_SEL_WRET_VLD = 67 -GC_EA_CPWD_PERF_SEL_PRB_REQ = 68 -GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT = 69 -GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD = 70 -GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT = 71 -GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY = 72 -GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73 -GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74 -GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED = 75 -GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING = 76 -GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ = 77 -GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ = 78 -GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ = 79 -GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ = 80 -GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81 -GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82 -GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83 -GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84 -GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85 -GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86 -GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT = 87 -GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD = 88 -GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89 -GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90 -GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91 -GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ = 92 -GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP = 93 -GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94 -GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95 -GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING = 96 -GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT = 97 -GC_EA_CPWD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GCVML2_SPM_PERF_SEL' -GCVML2_SPM_PERF_SEL__enumvalues = { - 0: 'GCVML2_SPM_PERF_SEL_EVENT_0', - 1: 'GCVML2_SPM_PERF_SEL_EVENT_1', - 2: 'GCVML2_SPM_PERF_SEL_EVENT_2', - 3: 'GCVML2_SPM_PERF_SEL_EVENT_3', - 4: 'GCVML2_SPM_PERF_SEL_EVENT_4', - 5: 'GCVML2_SPM_PERF_SEL_EVENT_5', - 6: 'GCVML2_SPM_PERF_SEL_EVENT_6', - 7: 'GCVML2_SPM_PERF_SEL_EVENT_7', - 8: 'GCVML2_SPM_PERF_SEL_EVENT_8', - 9: 'GCVML2_SPM_PERF_SEL_EVENT_9', - 10: 'GCVML2_SPM_PERF_SEL_EVENT_10', - 11: 'GCVML2_SPM_PERF_SEL_EVENT_11', - 12: 'GCVML2_SPM_PERF_SEL_EVENT_12', - 13: 'GCVML2_SPM_PERF_SEL_EVENT_13', - 14: 'GCVML2_SPM_PERF_SEL_EVENT_14', - 15: 'GCVML2_SPM_PERF_SEL_EVENT_15', - 16: 'GCVML2_SPM_PERF_SEL_EVENT_16', - 17: 'GCVML2_SPM_PERF_SEL_EVENT_17', - 18: 'GCVML2_SPM_PERF_SEL_EVENT_18', - 19: 'GCVML2_SPM_PERF_SEL_EVENT_19', - 20: 'GCVML2_SPM_PERF_SEL_EVENT_20', - 21: 'GCVML2_SPM_PERF_SEL_EVENT_21', - 22: 'GCVML2_SPM_PERF_SEL_EVENT_22', - 23: 'GCVML2_SPM_PERF_SEL_EVENT_23', - 24: 'GCVML2_SPM_PERF_SEL_EVENT_24', - 25: 'GCVML2_SPM_PERF_SEL_EVENT_25', - 26: 'GCVML2_SPM_PERF_SEL_EVENT_26', - 27: 'GCVML2_SPM_PERF_SEL_EVENT_27', - 28: 'GCVML2_SPM_PERF_SEL_EVENT_28', - 29: 'GCVML2_SPM_PERF_SEL_EVENT_29', - 30: 'GCVML2_SPM_PERF_SEL_EVENT_30', - 31: 'GCVML2_SPM_PERF_SEL_EVENT_31', - 32: 'GCVML2_SPM_PERF_SEL_EVENT_32', - 33: 'GCVML2_SPM_PERF_SEL_EVENT_33', - 34: 'GCVML2_SPM_PERF_SEL_EVENT_34', - 35: 'GCVML2_SPM_PERF_SEL_EVENT_35', - 36: 'GCVML2_SPM_PERF_SEL_EVENT_36', - 37: 'GCVML2_SPM_PERF_SEL_EVENT_37', - 38: 'GCVML2_SPM_PERF_SEL_EVENT_38', - 39: 'GCVML2_SPM_PERF_SEL_EVENT_39', - 40: 'GCVML2_SPM_PERF_SEL_EVENT_40', - 41: 'GCVML2_SPM_PERF_SEL_EVENT_41', - 42: 'GCVML2_SPM_PERF_SEL_EVENT_42', - 43: 'GCVML2_SPM_PERF_SEL_EVENT_43', - 44: 'GCVML2_SPM_PERF_SEL_EVENT_44', - 45: 'GCVML2_SPM_PERF_SEL_EVENT_45', - 46: 'GCVML2_SPM_PERF_SEL_EVENT_46', - 47: 'GCVML2_SPM_PERF_SEL_EVENT_47', - 48: 'GCVML2_SPM_PERF_SEL_EVENT_48', - 49: 'GCVML2_SPM_PERF_SEL_EVENT_49', - 50: 'GCVML2_SPM_PERF_SEL_EVENT_50', - 51: 'GCVML2_SPM_PERF_SEL_EVENT_51', - 52: 'GCVML2_SPM_PERF_SEL_EVENT_52', - 53: 'GCVML2_SPM_PERF_SEL_EVENT_53', - 54: 'GCVML2_SPM_PERF_SEL_EVENT_54', - 55: 'GCVML2_SPM_PERF_SEL_EVENT_55', - 56: 'GCVML2_SPM_PERF_SEL_EVENT_56', - 57: 'GCVML2_SPM_PERF_SEL_EVENT_57', - 58: 'GCVML2_SPM_PERF_SEL_EVENT_58', - 59: 'GCVML2_SPM_PERF_SEL_EVENT_59', - 60: 'GCVML2_SPM_PERF_SEL_EVENT_60', - 61: 'GCVML2_SPM_PERF_SEL_EVENT_61', - 62: 'GCVML2_SPM_PERF_SEL_EVENT_62', - 63: 'GCVML2_SPM_PERF_SEL_EVENT_63', - 64: 'GCVML2_SPM_PERF_SEL_EVENT_64', - 65: 'GCVML2_SPM_PERF_SEL_EVENT_65', - 66: 'GCVML2_SPM_PERF_SEL_EVENT_66', - 67: 'GCVML2_SPM_PERF_SEL_EVENT_67', - 68: 'GCVML2_SPM_PERF_SEL_EVENT_68', - 69: 'GCVML2_SPM_PERF_SEL_EVENT_69', - 70: 'GCVML2_SPM_PERF_SEL_EVENT_70', - 71: 'GCVML2_SPM_PERF_SEL_EVENT_71', - 72: 'GCVML2_SPM_PERF_SEL_EVENT_72', - 73: 'GCVML2_SPM_PERF_SEL_EVENT_73', - 74: 'GCVML2_SPM_PERF_SEL_EVENT_74', - 75: 'GCVML2_SPM_PERF_SEL_EVENT_75', - 76: 'GCVML2_SPM_PERF_SEL_EVENT_76', - 77: 'GCVML2_SPM_PERF_SEL_EVENT_77', - 78: 'GCVML2_SPM_PERF_SEL_EVENT_78', - 79: 'GCVML2_SPM_PERF_SEL_EVENT_79', - 80: 'GCVML2_SPM_PERF_SEL_EVENT_80', - 81: 'GCVML2_SPM_PERF_SEL_EVENT_81', - 82: 'GCVML2_SPM_PERF_SEL_EVENT_82', - 83: 'GCVML2_SPM_PERF_SEL_EVENT_83', - 84: 'GCVML2_SPM_PERF_SEL_EVENT_84', - 85: 'GCVML2_SPM_PERF_SEL_EVENT_85', - 86: 'GCVML2_SPM_PERF_SEL_EVENT_86', - 87: 'GCVML2_SPM_PERF_SEL_EVENT_87', - 88: 'GCVML2_SPM_PERF_SEL_EVENT_88', - 89: 'GCVML2_SPM_PERF_SEL_EVENT_89', - 90: 'GCVML2_SPM_PERF_SEL_EVENT_90', -} -GCVML2_SPM_PERF_SEL_EVENT_0 = 0 -GCVML2_SPM_PERF_SEL_EVENT_1 = 1 -GCVML2_SPM_PERF_SEL_EVENT_2 = 2 -GCVML2_SPM_PERF_SEL_EVENT_3 = 3 -GCVML2_SPM_PERF_SEL_EVENT_4 = 4 -GCVML2_SPM_PERF_SEL_EVENT_5 = 5 -GCVML2_SPM_PERF_SEL_EVENT_6 = 6 -GCVML2_SPM_PERF_SEL_EVENT_7 = 7 -GCVML2_SPM_PERF_SEL_EVENT_8 = 8 -GCVML2_SPM_PERF_SEL_EVENT_9 = 9 -GCVML2_SPM_PERF_SEL_EVENT_10 = 10 -GCVML2_SPM_PERF_SEL_EVENT_11 = 11 -GCVML2_SPM_PERF_SEL_EVENT_12 = 12 -GCVML2_SPM_PERF_SEL_EVENT_13 = 13 -GCVML2_SPM_PERF_SEL_EVENT_14 = 14 -GCVML2_SPM_PERF_SEL_EVENT_15 = 15 -GCVML2_SPM_PERF_SEL_EVENT_16 = 16 -GCVML2_SPM_PERF_SEL_EVENT_17 = 17 -GCVML2_SPM_PERF_SEL_EVENT_18 = 18 -GCVML2_SPM_PERF_SEL_EVENT_19 = 19 -GCVML2_SPM_PERF_SEL_EVENT_20 = 20 -GCVML2_SPM_PERF_SEL_EVENT_21 = 21 -GCVML2_SPM_PERF_SEL_EVENT_22 = 22 -GCVML2_SPM_PERF_SEL_EVENT_23 = 23 -GCVML2_SPM_PERF_SEL_EVENT_24 = 24 -GCVML2_SPM_PERF_SEL_EVENT_25 = 25 -GCVML2_SPM_PERF_SEL_EVENT_26 = 26 -GCVML2_SPM_PERF_SEL_EVENT_27 = 27 -GCVML2_SPM_PERF_SEL_EVENT_28 = 28 -GCVML2_SPM_PERF_SEL_EVENT_29 = 29 -GCVML2_SPM_PERF_SEL_EVENT_30 = 30 -GCVML2_SPM_PERF_SEL_EVENT_31 = 31 -GCVML2_SPM_PERF_SEL_EVENT_32 = 32 -GCVML2_SPM_PERF_SEL_EVENT_33 = 33 -GCVML2_SPM_PERF_SEL_EVENT_34 = 34 -GCVML2_SPM_PERF_SEL_EVENT_35 = 35 -GCVML2_SPM_PERF_SEL_EVENT_36 = 36 -GCVML2_SPM_PERF_SEL_EVENT_37 = 37 -GCVML2_SPM_PERF_SEL_EVENT_38 = 38 -GCVML2_SPM_PERF_SEL_EVENT_39 = 39 -GCVML2_SPM_PERF_SEL_EVENT_40 = 40 -GCVML2_SPM_PERF_SEL_EVENT_41 = 41 -GCVML2_SPM_PERF_SEL_EVENT_42 = 42 -GCVML2_SPM_PERF_SEL_EVENT_43 = 43 -GCVML2_SPM_PERF_SEL_EVENT_44 = 44 -GCVML2_SPM_PERF_SEL_EVENT_45 = 45 -GCVML2_SPM_PERF_SEL_EVENT_46 = 46 -GCVML2_SPM_PERF_SEL_EVENT_47 = 47 -GCVML2_SPM_PERF_SEL_EVENT_48 = 48 -GCVML2_SPM_PERF_SEL_EVENT_49 = 49 -GCVML2_SPM_PERF_SEL_EVENT_50 = 50 -GCVML2_SPM_PERF_SEL_EVENT_51 = 51 -GCVML2_SPM_PERF_SEL_EVENT_52 = 52 -GCVML2_SPM_PERF_SEL_EVENT_53 = 53 -GCVML2_SPM_PERF_SEL_EVENT_54 = 54 -GCVML2_SPM_PERF_SEL_EVENT_55 = 55 -GCVML2_SPM_PERF_SEL_EVENT_56 = 56 -GCVML2_SPM_PERF_SEL_EVENT_57 = 57 -GCVML2_SPM_PERF_SEL_EVENT_58 = 58 -GCVML2_SPM_PERF_SEL_EVENT_59 = 59 -GCVML2_SPM_PERF_SEL_EVENT_60 = 60 -GCVML2_SPM_PERF_SEL_EVENT_61 = 61 -GCVML2_SPM_PERF_SEL_EVENT_62 = 62 -GCVML2_SPM_PERF_SEL_EVENT_63 = 63 -GCVML2_SPM_PERF_SEL_EVENT_64 = 64 -GCVML2_SPM_PERF_SEL_EVENT_65 = 65 -GCVML2_SPM_PERF_SEL_EVENT_66 = 66 -GCVML2_SPM_PERF_SEL_EVENT_67 = 67 -GCVML2_SPM_PERF_SEL_EVENT_68 = 68 -GCVML2_SPM_PERF_SEL_EVENT_69 = 69 -GCVML2_SPM_PERF_SEL_EVENT_70 = 70 -GCVML2_SPM_PERF_SEL_EVENT_71 = 71 -GCVML2_SPM_PERF_SEL_EVENT_72 = 72 -GCVML2_SPM_PERF_SEL_EVENT_73 = 73 -GCVML2_SPM_PERF_SEL_EVENT_74 = 74 -GCVML2_SPM_PERF_SEL_EVENT_75 = 75 -GCVML2_SPM_PERF_SEL_EVENT_76 = 76 -GCVML2_SPM_PERF_SEL_EVENT_77 = 77 -GCVML2_SPM_PERF_SEL_EVENT_78 = 78 -GCVML2_SPM_PERF_SEL_EVENT_79 = 79 -GCVML2_SPM_PERF_SEL_EVENT_80 = 80 -GCVML2_SPM_PERF_SEL_EVENT_81 = 81 -GCVML2_SPM_PERF_SEL_EVENT_82 = 82 -GCVML2_SPM_PERF_SEL_EVENT_83 = 83 -GCVML2_SPM_PERF_SEL_EVENT_84 = 84 -GCVML2_SPM_PERF_SEL_EVENT_85 = 85 -GCVML2_SPM_PERF_SEL_EVENT_86 = 86 -GCVML2_SPM_PERF_SEL_EVENT_87 = 87 -GCVML2_SPM_PERF_SEL_EVENT_88 = 88 -GCVML2_SPM_PERF_SEL_EVENT_89 = 89 -GCVML2_SPM_PERF_SEL_EVENT_90 = 90 -GCVML2_SPM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GCUTCL2_PERF_SEL' -GCUTCL2_PERF_SEL__enumvalues = { - 0: 'GCUTCL2_PERF_SEL_EVENT_0', - 1: 'GCUTCL2_PERF_SEL_EVENT_1', - 2: 'GCUTCL2_PERF_SEL_EVENT_2', - 3: 'GCUTCL2_PERF_SEL_EVENT_3', - 4: 'GCUTCL2_PERF_SEL_EVENT_4', - 5: 'GCUTCL2_PERF_SEL_EVENT_5', - 6: 'GCUTCL2_PERF_SEL_EVENT_6', - 7: 'GCUTCL2_PERF_SEL_EVENT_7', - 8: 'GCUTCL2_PERF_SEL_EVENT_8', - 9: 'GCUTCL2_PERF_SEL_EVENT_9', - 10: 'GCUTCL2_PERF_SEL_EVENT_10', - 11: 'GCUTCL2_PERF_SEL_EVENT_11', - 12: 'GCUTCL2_PERF_SEL_EVENT_12', - 13: 'GCUTCL2_PERF_SEL_EVENT_13', - 14: 'GCUTCL2_PERF_SEL_EVENT_14', - 15: 'GCUTCL2_PERF_SEL_EVENT_15', - 16: 'GCUTCL2_PERF_SEL_EVENT_16', - 17: 'GCUTCL2_PERF_SEL_EVENT_17', - 18: 'GCUTCL2_PERF_SEL_EVENT_18', - 19: 'GCUTCL2_PERF_SEL_EVENT_19', - 20: 'GCUTCL2_PERF_SEL_EVENT_20', - 21: 'GCUTCL2_PERF_SEL_EVENT_21', - 22: 'GCUTCL2_PERF_SEL_EVENT_22', - 23: 'GCUTCL2_PERF_SEL_EVENT_23', - 24: 'GCUTCL2_PERF_SEL_EVENT_24', - 25: 'GCUTCL2_PERF_SEL_EVENT_25', - 26: 'GCUTCL2_PERF_SEL_EVENT_26', - 27: 'GCUTCL2_PERF_SEL_EVENT_27', - 28: 'GCUTCL2_PERF_SEL_EVENT_28', - 29: 'GCUTCL2_PERF_SEL_EVENT_29', - 30: 'GCUTCL2_PERF_SEL_EVENT_30', - 31: 'GCUTCL2_PERF_SEL_EVENT_31', - 32: 'GCUTCL2_PERF_SEL_EVENT_32', - 33: 'GCUTCL2_PERF_SEL_EVENT_33', - 34: 'GCUTCL2_PERF_SEL_EVENT_34', - 35: 'GCUTCL2_PERF_SEL_EVENT_35', - 36: 'GCUTCL2_PERF_SEL_EVENT_36', -} -GCUTCL2_PERF_SEL_EVENT_0 = 0 -GCUTCL2_PERF_SEL_EVENT_1 = 1 -GCUTCL2_PERF_SEL_EVENT_2 = 2 -GCUTCL2_PERF_SEL_EVENT_3 = 3 -GCUTCL2_PERF_SEL_EVENT_4 = 4 -GCUTCL2_PERF_SEL_EVENT_5 = 5 -GCUTCL2_PERF_SEL_EVENT_6 = 6 -GCUTCL2_PERF_SEL_EVENT_7 = 7 -GCUTCL2_PERF_SEL_EVENT_8 = 8 -GCUTCL2_PERF_SEL_EVENT_9 = 9 -GCUTCL2_PERF_SEL_EVENT_10 = 10 -GCUTCL2_PERF_SEL_EVENT_11 = 11 -GCUTCL2_PERF_SEL_EVENT_12 = 12 -GCUTCL2_PERF_SEL_EVENT_13 = 13 -GCUTCL2_PERF_SEL_EVENT_14 = 14 -GCUTCL2_PERF_SEL_EVENT_15 = 15 -GCUTCL2_PERF_SEL_EVENT_16 = 16 -GCUTCL2_PERF_SEL_EVENT_17 = 17 -GCUTCL2_PERF_SEL_EVENT_18 = 18 -GCUTCL2_PERF_SEL_EVENT_19 = 19 -GCUTCL2_PERF_SEL_EVENT_20 = 20 -GCUTCL2_PERF_SEL_EVENT_21 = 21 -GCUTCL2_PERF_SEL_EVENT_22 = 22 -GCUTCL2_PERF_SEL_EVENT_23 = 23 -GCUTCL2_PERF_SEL_EVENT_24 = 24 -GCUTCL2_PERF_SEL_EVENT_25 = 25 -GCUTCL2_PERF_SEL_EVENT_26 = 26 -GCUTCL2_PERF_SEL_EVENT_27 = 27 -GCUTCL2_PERF_SEL_EVENT_28 = 28 -GCUTCL2_PERF_SEL_EVENT_29 = 29 -GCUTCL2_PERF_SEL_EVENT_30 = 30 -GCUTCL2_PERF_SEL_EVENT_31 = 31 -GCUTCL2_PERF_SEL_EVENT_32 = 32 -GCUTCL2_PERF_SEL_EVENT_33 = 33 -GCUTCL2_PERF_SEL_EVENT_34 = 34 -GCUTCL2_PERF_SEL_EVENT_35 = 35 -GCUTCL2_PERF_SEL_EVENT_36 = 36 -GCUTCL2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GCVML2_PERF_SEL' -GCVML2_PERF_SEL__enumvalues = { - 0: 'GCVML2_PERF_SEL_EVENT_0', - 1: 'GCVML2_PERF_SEL_EVENT_1', - 2: 'GCVML2_PERF_SEL_EVENT_2', - 3: 'GCVML2_PERF_SEL_EVENT_3', - 4: 'GCVML2_PERF_SEL_EVENT_4', - 5: 'GCVML2_PERF_SEL_EVENT_5', - 6: 'GCVML2_PERF_SEL_EVENT_6', - 7: 'GCVML2_PERF_SEL_EVENT_7', - 8: 'GCVML2_PERF_SEL_EVENT_8', - 9: 'GCVML2_PERF_SEL_EVENT_9', - 10: 'GCVML2_PERF_SEL_EVENT_10', - 11: 'GCVML2_PERF_SEL_EVENT_11', - 12: 'GCVML2_PERF_SEL_EVENT_12', - 13: 'GCVML2_PERF_SEL_EVENT_13', - 14: 'GCVML2_PERF_SEL_EVENT_14', - 15: 'GCVML2_PERF_SEL_EVENT_15', - 16: 'GCVML2_PERF_SEL_EVENT_16', - 17: 'GCVML2_PERF_SEL_EVENT_17', - 18: 'GCVML2_PERF_SEL_EVENT_18', - 19: 'GCVML2_PERF_SEL_EVENT_19', - 20: 'GCVML2_PERF_SEL_EVENT_20', - 21: 'GCVML2_PERF_SEL_EVENT_21', - 22: 'GCVML2_PERF_SEL_EVENT_22', - 23: 'GCVML2_PERF_SEL_EVENT_23', - 24: 'GCVML2_PERF_SEL_EVENT_24', - 25: 'GCVML2_PERF_SEL_EVENT_25', - 26: 'GCVML2_PERF_SEL_EVENT_26', - 27: 'GCVML2_PERF_SEL_EVENT_27', - 28: 'GCVML2_PERF_SEL_EVENT_28', - 29: 'GCVML2_PERF_SEL_EVENT_29', - 30: 'GCVML2_PERF_SEL_EVENT_30', - 31: 'GCVML2_PERF_SEL_EVENT_31', - 32: 'GCVML2_PERF_SEL_EVENT_32', - 33: 'GCVML2_PERF_SEL_EVENT_33', - 34: 'GCVML2_PERF_SEL_EVENT_34', - 35: 'GCVML2_PERF_SEL_EVENT_35', - 36: 'GCVML2_PERF_SEL_EVENT_36', - 37: 'GCVML2_PERF_SEL_EVENT_37', - 38: 'GCVML2_PERF_SEL_EVENT_38', - 39: 'GCVML2_PERF_SEL_EVENT_39', - 40: 'GCVML2_PERF_SEL_EVENT_40', - 41: 'GCVML2_PERF_SEL_EVENT_41', - 42: 'GCVML2_PERF_SEL_EVENT_42', - 43: 'GCVML2_PERF_SEL_EVENT_43', - 44: 'GCVML2_PERF_SEL_EVENT_44', - 45: 'GCVML2_PERF_SEL_EVENT_45', - 46: 'GCVML2_PERF_SEL_EVENT_46', - 47: 'GCVML2_PERF_SEL_EVENT_47', - 48: 'GCVML2_PERF_SEL_EVENT_48', - 49: 'GCVML2_PERF_SEL_EVENT_49', - 50: 'GCVML2_PERF_SEL_EVENT_50', - 51: 'GCVML2_PERF_SEL_EVENT_51', - 52: 'GCVML2_PERF_SEL_EVENT_52', - 53: 'GCVML2_PERF_SEL_EVENT_53', - 54: 'GCVML2_PERF_SEL_EVENT_54', - 55: 'GCVML2_PERF_SEL_EVENT_55', - 56: 'GCVML2_PERF_SEL_EVENT_56', - 57: 'GCVML2_PERF_SEL_EVENT_57', - 58: 'GCVML2_PERF_SEL_EVENT_58', - 59: 'GCVML2_PERF_SEL_EVENT_59', - 60: 'GCVML2_PERF_SEL_EVENT_60', - 61: 'GCVML2_PERF_SEL_EVENT_61', - 62: 'GCVML2_PERF_SEL_EVENT_62', - 63: 'GCVML2_PERF_SEL_EVENT_63', - 64: 'GCVML2_PERF_SEL_EVENT_64', - 65: 'GCVML2_PERF_SEL_EVENT_65', - 66: 'GCVML2_PERF_SEL_EVENT_66', - 67: 'GCVML2_PERF_SEL_EVENT_67', - 68: 'GCVML2_PERF_SEL_EVENT_68', - 69: 'GCVML2_PERF_SEL_EVENT_69', - 70: 'GCVML2_PERF_SEL_EVENT_70', - 71: 'GCVML2_PERF_SEL_EVENT_71', - 72: 'GCVML2_PERF_SEL_EVENT_72', - 73: 'GCVML2_PERF_SEL_EVENT_73', - 74: 'GCVML2_PERF_SEL_EVENT_74', - 75: 'GCVML2_PERF_SEL_EVENT_75', - 76: 'GCVML2_PERF_SEL_EVENT_76', - 77: 'GCVML2_PERF_SEL_EVENT_77', - 78: 'GCVML2_PERF_SEL_EVENT_78', - 79: 'GCVML2_PERF_SEL_EVENT_79', - 80: 'GCVML2_PERF_SEL_EVENT_80', - 81: 'GCVML2_PERF_SEL_EVENT_81', - 82: 'GCVML2_PERF_SEL_EVENT_82', - 83: 'GCVML2_PERF_SEL_EVENT_83', - 84: 'GCVML2_PERF_SEL_EVENT_84', - 85: 'GCVML2_PERF_SEL_EVENT_85', - 86: 'GCVML2_PERF_SEL_EVENT_86', - 87: 'GCVML2_PERF_SEL_EVENT_87', - 88: 'GCVML2_PERF_SEL_EVENT_88', - 89: 'GCVML2_PERF_SEL_EVENT_89', - 90: 'GCVML2_PERF_SEL_EVENT_90', -} -GCVML2_PERF_SEL_EVENT_0 = 0 -GCVML2_PERF_SEL_EVENT_1 = 1 -GCVML2_PERF_SEL_EVENT_2 = 2 -GCVML2_PERF_SEL_EVENT_3 = 3 -GCVML2_PERF_SEL_EVENT_4 = 4 -GCVML2_PERF_SEL_EVENT_5 = 5 -GCVML2_PERF_SEL_EVENT_6 = 6 -GCVML2_PERF_SEL_EVENT_7 = 7 -GCVML2_PERF_SEL_EVENT_8 = 8 -GCVML2_PERF_SEL_EVENT_9 = 9 -GCVML2_PERF_SEL_EVENT_10 = 10 -GCVML2_PERF_SEL_EVENT_11 = 11 -GCVML2_PERF_SEL_EVENT_12 = 12 -GCVML2_PERF_SEL_EVENT_13 = 13 -GCVML2_PERF_SEL_EVENT_14 = 14 -GCVML2_PERF_SEL_EVENT_15 = 15 -GCVML2_PERF_SEL_EVENT_16 = 16 -GCVML2_PERF_SEL_EVENT_17 = 17 -GCVML2_PERF_SEL_EVENT_18 = 18 -GCVML2_PERF_SEL_EVENT_19 = 19 -GCVML2_PERF_SEL_EVENT_20 = 20 -GCVML2_PERF_SEL_EVENT_21 = 21 -GCVML2_PERF_SEL_EVENT_22 = 22 -GCVML2_PERF_SEL_EVENT_23 = 23 -GCVML2_PERF_SEL_EVENT_24 = 24 -GCVML2_PERF_SEL_EVENT_25 = 25 -GCVML2_PERF_SEL_EVENT_26 = 26 -GCVML2_PERF_SEL_EVENT_27 = 27 -GCVML2_PERF_SEL_EVENT_28 = 28 -GCVML2_PERF_SEL_EVENT_29 = 29 -GCVML2_PERF_SEL_EVENT_30 = 30 -GCVML2_PERF_SEL_EVENT_31 = 31 -GCVML2_PERF_SEL_EVENT_32 = 32 -GCVML2_PERF_SEL_EVENT_33 = 33 -GCVML2_PERF_SEL_EVENT_34 = 34 -GCVML2_PERF_SEL_EVENT_35 = 35 -GCVML2_PERF_SEL_EVENT_36 = 36 -GCVML2_PERF_SEL_EVENT_37 = 37 -GCVML2_PERF_SEL_EVENT_38 = 38 -GCVML2_PERF_SEL_EVENT_39 = 39 -GCVML2_PERF_SEL_EVENT_40 = 40 -GCVML2_PERF_SEL_EVENT_41 = 41 -GCVML2_PERF_SEL_EVENT_42 = 42 -GCVML2_PERF_SEL_EVENT_43 = 43 -GCVML2_PERF_SEL_EVENT_44 = 44 -GCVML2_PERF_SEL_EVENT_45 = 45 -GCVML2_PERF_SEL_EVENT_46 = 46 -GCVML2_PERF_SEL_EVENT_47 = 47 -GCVML2_PERF_SEL_EVENT_48 = 48 -GCVML2_PERF_SEL_EVENT_49 = 49 -GCVML2_PERF_SEL_EVENT_50 = 50 -GCVML2_PERF_SEL_EVENT_51 = 51 -GCVML2_PERF_SEL_EVENT_52 = 52 -GCVML2_PERF_SEL_EVENT_53 = 53 -GCVML2_PERF_SEL_EVENT_54 = 54 -GCVML2_PERF_SEL_EVENT_55 = 55 -GCVML2_PERF_SEL_EVENT_56 = 56 -GCVML2_PERF_SEL_EVENT_57 = 57 -GCVML2_PERF_SEL_EVENT_58 = 58 -GCVML2_PERF_SEL_EVENT_59 = 59 -GCVML2_PERF_SEL_EVENT_60 = 60 -GCVML2_PERF_SEL_EVENT_61 = 61 -GCVML2_PERF_SEL_EVENT_62 = 62 -GCVML2_PERF_SEL_EVENT_63 = 63 -GCVML2_PERF_SEL_EVENT_64 = 64 -GCVML2_PERF_SEL_EVENT_65 = 65 -GCVML2_PERF_SEL_EVENT_66 = 66 -GCVML2_PERF_SEL_EVENT_67 = 67 -GCVML2_PERF_SEL_EVENT_68 = 68 -GCVML2_PERF_SEL_EVENT_69 = 69 -GCVML2_PERF_SEL_EVENT_70 = 70 -GCVML2_PERF_SEL_EVENT_71 = 71 -GCVML2_PERF_SEL_EVENT_72 = 72 -GCVML2_PERF_SEL_EVENT_73 = 73 -GCVML2_PERF_SEL_EVENT_74 = 74 -GCVML2_PERF_SEL_EVENT_75 = 75 -GCVML2_PERF_SEL_EVENT_76 = 76 -GCVML2_PERF_SEL_EVENT_77 = 77 -GCVML2_PERF_SEL_EVENT_78 = 78 -GCVML2_PERF_SEL_EVENT_79 = 79 -GCVML2_PERF_SEL_EVENT_80 = 80 -GCVML2_PERF_SEL_EVENT_81 = 81 -GCVML2_PERF_SEL_EVENT_82 = 82 -GCVML2_PERF_SEL_EVENT_83 = 83 -GCVML2_PERF_SEL_EVENT_84 = 84 -GCVML2_PERF_SEL_EVENT_85 = 85 -GCVML2_PERF_SEL_EVENT_86 = 86 -GCVML2_PERF_SEL_EVENT_87 = 87 -GCVML2_PERF_SEL_EVENT_88 = 88 -GCVML2_PERF_SEL_EVENT_89 = 89 -GCVML2_PERF_SEL_EVENT_90 = 90 -GCVML2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOp' -BlendOp__enumvalues = { - 0: 'BLEND_ZERO', - 1: 'BLEND_ONE', - 2: 'BLEND_SRC_COLOR', - 3: 'BLEND_ONE_MINUS_SRC_COLOR', - 4: 'BLEND_SRC_ALPHA', - 5: 'BLEND_ONE_MINUS_SRC_ALPHA', - 6: 'BLEND_DST_ALPHA', - 7: 'BLEND_ONE_MINUS_DST_ALPHA', - 8: 'BLEND_DST_COLOR', - 9: 'BLEND_ONE_MINUS_DST_COLOR', - 10: 'BLEND_SRC_ALPHA_SATURATE', - 11: 'BLEND_CONSTANT_COLOR', - 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', - 13: 'BLEND_SRC1_COLOR', - 14: 'BLEND_INV_SRC1_COLOR', - 15: 'BLEND_SRC1_ALPHA', - 16: 'BLEND_INV_SRC1_ALPHA', - 17: 'BLEND_CONSTANT_ALPHA', - 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', -} -BLEND_ZERO = 0 -BLEND_ONE = 1 -BLEND_SRC_COLOR = 2 -BLEND_ONE_MINUS_SRC_COLOR = 3 -BLEND_SRC_ALPHA = 4 -BLEND_ONE_MINUS_SRC_ALPHA = 5 -BLEND_DST_ALPHA = 6 -BLEND_ONE_MINUS_DST_ALPHA = 7 -BLEND_DST_COLOR = 8 -BLEND_ONE_MINUS_DST_COLOR = 9 -BLEND_SRC_ALPHA_SATURATE = 10 -BLEND_CONSTANT_COLOR = 11 -BLEND_ONE_MINUS_CONSTANT_COLOR = 12 -BLEND_SRC1_COLOR = 13 -BLEND_INV_SRC1_COLOR = 14 -BLEND_SRC1_ALPHA = 15 -BLEND_INV_SRC1_ALPHA = 16 -BLEND_CONSTANT_ALPHA = 17 -BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 -BlendOp = ctypes.c_uint32 # enum -GL__ZERO = BLEND_ZERO # macro -GL__ONE = BLEND_ONE # macro -GL__SRC_COLOR = BLEND_SRC_COLOR # macro -GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro -GL__DST_COLOR = BLEND_DST_COLOR # macro -GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro -GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro -GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro -GL__DST_ALPHA = BLEND_DST_ALPHA # macro -GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro -GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro -GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro -GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro -GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro -GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro - -# values for enumeration 'BlendOpt' -BlendOpt__enumvalues = { - 0: 'FORCE_OPT_AUTO', - 1: 'FORCE_OPT_DISABLE', - 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', - 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', - 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', -} -FORCE_OPT_AUTO = 0 -FORCE_OPT_DISABLE = 1 -FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 -FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 -BlendOpt = ctypes.c_uint32 # enum - -# values for enumeration 'CBMode' -CBMode__enumvalues = { - 0: 'CB_DISABLE', - 1: 'CB_NORMAL', - 2: 'CB_ELIMINATE_FAST_CLEAR', - 3: 'CB_DCC_DECOMPRESS', - 4: 'CB_RESERVED', -} -CB_DISABLE = 0 -CB_NORMAL = 1 -CB_ELIMINATE_FAST_CLEAR = 2 -CB_DCC_DECOMPRESS = 3 -CB_RESERVED = 4 -CBMode = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfClearFilterSel' -CBPerfClearFilterSel__enumvalues = { - 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', -} -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 -CBPerfClearFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfOpFilterSel' -CBPerfOpFilterSel__enumvalues = { - 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', -} -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 -CB_PERF_OP_FILTER_SEL_RESOLVE = 2 -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 -CBPerfOpFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfSel' -CBPerfSel__enumvalues = { - 1: 'CB_PERF_SEL_BUSY', - 2: 'CB_PERF_SEL_DRAWN_BUSY', - 3: 'CB_PERF_SEL_DRAWN_PIXEL', - 4: 'CB_PERF_SEL_DRAWN_QUAD', - 5: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', - 15: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 16: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', - 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 21: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST', - 22: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT', - 23: 'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST', - 24: 'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES', - 25: 'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN', - 26: 'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT', - 50: 'CB_PERF_SEL_EVENT', - 51: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 52: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 53: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 54: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 55: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 56: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 57: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 58: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', - 60: 'CB_PERF_SEL_STATIC_CLOCK_EN', - 61: 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 62: 'CB_PERF_SEL_BLEND_CLOCK_EN', - 63: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 64: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 65: 'CB_PERF_SEL_GRBM_CLOCK_EN', - 66: 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 67: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 68: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 69: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 70: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 71: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 72: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 73: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 74: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 75: 'CB_PERF_SEL_EVENTS_CLK_EN', - 80: 'CB_PERF_SEL_CC_TAG_HIT', - 81: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 82: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', - 83: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 88: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 89: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 90: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 91: 'CB_PERF_SEL_CC_CACHE_STALL', - 92: 'CB_PERF_SEL_CC_CACHE_FLUSH', - 93: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 94: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 95: 'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED', - 96: 'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED', - 97: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 98: 'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL', - 99: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC', - 100: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC', - 101: 'CB_PERF_SEL_CCC_FREE_WAYS_PANIC', - 102: 'CB_PERF_SEL_CCC_SKID_FIFO_FULL', - 103: 'CB_PERF_SEL_CCC_SKID_FIFO_STALL', - 104: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL', - 105: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL', - 106: 'CB_PERF_SEL_CCC_FREE_WAYS_STALL', - 110: 'CB_PERF_SEL_BE_SRCFIFO_FULL', - 111: 'CB_PERF_SEL_BE_RDLATFIFO_FULL', - 112: 'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 113: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READY', - 114: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB', - 115: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY', - 116: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB', - 118: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY', - 119: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB', - 120: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY', - 121: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB', - 150: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 151: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 152: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 180: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 181: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 182: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 183: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 184: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 185: 'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS', - 186: 'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE', - 187: 'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL', - 190: 'CB_PERF_SEL_BE_CS_FILLRATE_1X2', - 191: 'CB_PERF_SEL_BE_CS_FILLRATE_2X1', - 192: 'CB_PERF_SEL_BE_CS_FILLRATE_2X2', - 250: 'CB_PERF_SEL_FORMAT_IS_32_R', - 251: 'CB_PERF_SEL_FORMAT_IS_32_AR', - 252: 'CB_PERF_SEL_FORMAT_IS_32_GR', - 253: 'CB_PERF_SEL_FORMAT_IS_32_ABGR', - 254: 'CB_PERF_SEL_FORMAT_IS_FP16_ABGR', - 255: 'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR', - 256: 'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR', - 257: 'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX', - 258: 'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX', - 259: 'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX', - 260: 'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX', - 261: 'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT', - 262: 'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS', - 263: 'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS', - 264: 'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS', - 265: 'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS', - 266: 'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS', - 267: 'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS', - 268: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST', - 269: 'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS', - 270: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS', - 271: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE', - 272: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE', - 273: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 274: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE', - 275: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 276: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE', - 277: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 278: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE', - 279: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 280: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE', - 281: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 282: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE', - 283: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 284: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE', - 285: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 286: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE', - 287: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0', - 288: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1', - 289: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2', - 290: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3', - 291: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4', - 292: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5', - 293: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6', - 294: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7', - 295: 'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT', - 296: 'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS', - 297: 'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS', - 298: 'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS', - 299: 'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS', - 300: 'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS', - 301: 'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS', - 302: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0', - 303: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1', - 304: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2', - 305: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3', - 306: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4', - 307: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5', - 308: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6', - 309: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7', - 310: 'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID', - 311: 'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL', - 312: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK', - 313: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK', -} -CB_PERF_SEL_BUSY = 1 -CB_PERF_SEL_DRAWN_BUSY = 2 -CB_PERF_SEL_DRAWN_PIXEL = 3 -CB_PERF_SEL_DRAWN_QUAD = 4 -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 5 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 15 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 16 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 17 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 18 -CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST = 21 -CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT = 22 -CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST = 23 -CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES = 24 -CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN = 25 -CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT = 26 -CB_PERF_SEL_EVENT = 50 -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 51 -CB_PERF_SEL_EVENT_CONTEXT_DONE = 52 -CB_PERF_SEL_EVENT_CACHE_FLUSH = 53 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 54 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 55 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 56 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 57 -CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 58 -CB_PERF_SEL_STATIC_CLOCK_EN = 60 -CB_PERF_SEL_PERFMON_CLOCK_EN = 61 -CB_PERF_SEL_BLEND_CLOCK_EN = 62 -CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 63 -CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 64 -CB_PERF_SEL_GRBM_CLOCK_EN = 65 -CB_PERF_SEL_MEMARB_CLOCK_EN = 66 -CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 67 -CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 68 -CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 69 -CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 70 -CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 71 -CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 72 -CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 73 -CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 74 -CB_PERF_SEL_EVENTS_CLK_EN = 75 -CB_PERF_SEL_CC_TAG_HIT = 80 -CB_PERF_SEL_CC_CACHE_TAG_MISS = 81 -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 82 -CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 83 -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 88 -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 89 -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 90 -CB_PERF_SEL_CC_CACHE_STALL = 91 -CB_PERF_SEL_CC_CACHE_FLUSH = 92 -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 93 -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 94 -CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED = 95 -CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED = 96 -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 97 -CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL = 98 -CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC = 99 -CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC = 100 -CB_PERF_SEL_CCC_FREE_WAYS_PANIC = 101 -CB_PERF_SEL_CCC_SKID_FIFO_FULL = 102 -CB_PERF_SEL_CCC_SKID_FIFO_STALL = 103 -CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL = 104 -CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL = 105 -CB_PERF_SEL_CCC_FREE_WAYS_STALL = 106 -CB_PERF_SEL_BE_SRCFIFO_FULL = 110 -CB_PERF_SEL_BE_RDLATFIFO_FULL = 111 -CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 112 -CB_PERF_SEL_CC_QUADFRAG_VALID_READY = 113 -CB_PERF_SEL_CC_QUADFRAG_VALID_READYB = 114 -CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY = 115 -CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB = 116 -CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY = 118 -CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB = 119 -CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY = 120 -CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB = 121 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 150 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 151 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 152 -CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 180 -CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 181 -CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 182 -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 183 -CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 184 -CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS = 185 -CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE = 186 -CB_PERF_SEL_BLEND_RAW_HAZARD_STALL = 187 -CB_PERF_SEL_BE_CS_FILLRATE_1X2 = 190 -CB_PERF_SEL_BE_CS_FILLRATE_2X1 = 191 -CB_PERF_SEL_BE_CS_FILLRATE_2X2 = 192 -CB_PERF_SEL_FORMAT_IS_32_R = 250 -CB_PERF_SEL_FORMAT_IS_32_AR = 251 -CB_PERF_SEL_FORMAT_IS_32_GR = 252 -CB_PERF_SEL_FORMAT_IS_32_ABGR = 253 -CB_PERF_SEL_FORMAT_IS_FP16_ABGR = 254 -CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR = 255 -CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR = 256 -CB_PERF_SEL_FORMAT_IS_32BPP_8PIX = 257 -CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX = 258 -CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX = 259 -CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX = 260 -CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT = 261 -CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS = 262 -CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS = 263 -CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS = 264 -CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS = 265 -CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS = 266 -CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS = 267 -CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST = 268 -CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS = 269 -CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS = 270 -CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE = 271 -CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE = 272 -CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE = 273 -CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE = 274 -CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE = 275 -CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE = 276 -CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE = 277 -CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE = 278 -CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE = 279 -CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE = 280 -CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE = 281 -CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE = 282 -CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE = 283 -CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE = 284 -CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE = 285 -CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE = 286 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_0 = 287 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_1 = 288 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_2 = 289 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_3 = 290 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_4 = 291 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_5 = 292 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_6 = 293 -CB_PERF_SEL_EXPORT_READS_FRAGMENT_7 = 294 -CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT = 295 -CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS = 296 -CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS = 297 -CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS = 298 -CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS = 299 -CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS = 300 -CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS = 301 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0 = 302 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1 = 303 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2 = 304 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3 = 305 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4 = 306 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5 = 307 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6 = 308 -CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7 = 309 -CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID = 310 -CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL = 311 -CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK = 312 -CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK = 313 -CBPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'CombFunc' -CombFunc__enumvalues = { - 0: 'COMB_DST_PLUS_SRC', - 1: 'COMB_SRC_MINUS_DST', - 2: 'COMB_MIN_DST_SRC', - 3: 'COMB_MAX_DST_SRC', - 4: 'COMB_DST_MINUS_SRC', -} -COMB_DST_PLUS_SRC = 0 -COMB_SRC_MINUS_DST = 1 -COMB_MIN_DST_SRC = 2 -COMB_MAX_DST_SRC = 3 -COMB_DST_MINUS_SRC = 4 -CombFunc = ctypes.c_uint32 # enum - -# values for enumeration 'MemArbMode' -MemArbMode__enumvalues = { - 0: 'MEM_ARB_MODE_FIXED', - 1: 'MEM_ARB_MODE_AGE', - 2: 'MEM_ARB_MODE_WEIGHT', - 3: 'MEM_ARB_MODE_BOTH', -} -MEM_ARB_MODE_FIXED = 0 -MEM_ARB_MODE_AGE = 1 -MEM_ARB_MODE_WEIGHT = 2 -MEM_ARB_MODE_BOTH = 3 -MemArbMode = ctypes.c_uint32 # enum - -# values for enumeration 'PH_PERFCNT_SEL' -PH_PERFCNT_SEL__enumvalues = { - 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 8: 'PH_PERF_SEL_SC0_ARB_BUSY', - 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 16: 'PH_PERF_SEL_SC0_SEND', - 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', - 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', - 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', - 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 31: 'PH_PERF_SEL_SC0_PA0_FPOP_WE', - 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', - 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', - 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_WE', - 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', - 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', - 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', - 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 43: 'PH_PERF_SEL_SC0_PA1_FPOP_WE', - 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', - 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', - 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_WE', - 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', - 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', - 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', - 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 55: 'PH_PERF_SEL_SC0_PA2_FPOP_WE', - 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', - 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', - 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_WE', - 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', - 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', - 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', - 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 67: 'PH_PERF_SEL_SC0_PA3_FPOP_WE', - 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', - 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', - 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_WE', - 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', - 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', - 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', - 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 79: 'PH_PERF_SEL_SC0_PA4_FPOP_WE', - 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', - 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', - 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_WE', - 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', - 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', - 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', - 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 91: 'PH_PERF_SEL_SC0_PA5_FPOP_WE', - 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', - 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', - 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_WE', - 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', - 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', - 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', - 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 103: 'PH_PERF_SEL_SC0_PA6_FPOP_WE', - 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', - 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', - 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_WE', - 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', - 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', - 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', - 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 115: 'PH_PERF_SEL_SC0_PA7_FPOP_WE', - 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', - 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', - 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_WE', - 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 128: 'PH_PERF_SEL_SC1_ARB_BUSY', - 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 136: 'PH_PERF_SEL_SC1_SEND', - 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', - 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', - 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', - 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 151: 'PH_PERF_SEL_SC1_PA0_FPOP_WE', - 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', - 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', - 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_WE', - 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', - 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', - 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', - 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 163: 'PH_PERF_SEL_SC1_PA1_FPOP_WE', - 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', - 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', - 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_WE', - 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', - 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', - 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', - 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 175: 'PH_PERF_SEL_SC1_PA2_FPOP_WE', - 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', - 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', - 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_WE', - 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', - 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', - 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', - 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 187: 'PH_PERF_SEL_SC1_PA3_FPOP_WE', - 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', - 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', - 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_WE', - 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', - 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', - 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', - 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 199: 'PH_PERF_SEL_SC1_PA4_FPOP_WE', - 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', - 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', - 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_WE', - 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', - 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', - 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', - 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 211: 'PH_PERF_SEL_SC1_PA5_FPOP_WE', - 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', - 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', - 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_WE', - 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', - 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', - 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', - 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 223: 'PH_PERF_SEL_SC1_PA6_FPOP_WE', - 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', - 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', - 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_WE', - 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', - 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', - 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', - 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 235: 'PH_PERF_SEL_SC1_PA7_FPOP_WE', - 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', - 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', - 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_WE', - 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 248: 'PH_PERF_SEL_SC2_ARB_BUSY', - 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 256: 'PH_PERF_SEL_SC2_SEND', - 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', - 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', - 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', - 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 271: 'PH_PERF_SEL_SC2_PA0_FPOP_WE', - 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', - 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', - 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_WE', - 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', - 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', - 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', - 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 283: 'PH_PERF_SEL_SC2_PA1_FPOP_WE', - 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', - 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', - 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_WE', - 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', - 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', - 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', - 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 295: 'PH_PERF_SEL_SC2_PA2_FPOP_WE', - 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', - 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', - 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_WE', - 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', - 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', - 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', - 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 307: 'PH_PERF_SEL_SC2_PA3_FPOP_WE', - 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', - 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', - 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_WE', - 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', - 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', - 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', - 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 319: 'PH_PERF_SEL_SC2_PA4_FPOP_WE', - 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', - 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', - 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_WE', - 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', - 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', - 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', - 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 331: 'PH_PERF_SEL_SC2_PA5_FPOP_WE', - 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', - 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', - 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_WE', - 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', - 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', - 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', - 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 343: 'PH_PERF_SEL_SC2_PA6_FPOP_WE', - 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', - 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', - 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_WE', - 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', - 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', - 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', - 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 355: 'PH_PERF_SEL_SC2_PA7_FPOP_WE', - 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', - 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', - 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_WE', - 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 368: 'PH_PERF_SEL_SC3_ARB_BUSY', - 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 376: 'PH_PERF_SEL_SC3_SEND', - 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', - 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', - 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', - 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 391: 'PH_PERF_SEL_SC3_PA0_FPOP_WE', - 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', - 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', - 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_WE', - 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', - 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', - 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', - 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 403: 'PH_PERF_SEL_SC3_PA1_FPOP_WE', - 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', - 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', - 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_WE', - 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', - 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', - 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', - 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 415: 'PH_PERF_SEL_SC3_PA2_FPOP_WE', - 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', - 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', - 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_WE', - 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', - 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', - 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', - 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 427: 'PH_PERF_SEL_SC3_PA3_FPOP_WE', - 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', - 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', - 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_WE', - 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', - 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', - 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', - 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 439: 'PH_PERF_SEL_SC3_PA4_FPOP_WE', - 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', - 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', - 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_WE', - 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', - 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', - 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', - 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 451: 'PH_PERF_SEL_SC3_PA5_FPOP_WE', - 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', - 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', - 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_WE', - 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', - 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', - 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', - 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 463: 'PH_PERF_SEL_SC3_PA6_FPOP_WE', - 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', - 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', - 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_WE', - 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', - 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', - 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', - 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 475: 'PH_PERF_SEL_SC3_PA7_FPOP_WE', - 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', - 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', - 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_WE', - 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 488: 'PH_PERF_SEL_SC4_ARB_BUSY', - 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 496: 'PH_PERF_SEL_SC4_SEND', - 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', - 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', - 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', - 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 511: 'PH_PERF_SEL_SC4_PA0_FPOP_WE', - 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', - 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', - 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_WE', - 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', - 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', - 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', - 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 523: 'PH_PERF_SEL_SC4_PA1_FPOP_WE', - 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', - 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', - 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_WE', - 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', - 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', - 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', - 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 535: 'PH_PERF_SEL_SC4_PA2_FPOP_WE', - 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', - 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', - 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_WE', - 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', - 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', - 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', - 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 547: 'PH_PERF_SEL_SC4_PA3_FPOP_WE', - 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', - 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', - 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_WE', - 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', - 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', - 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', - 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 559: 'PH_PERF_SEL_SC4_PA4_FPOP_WE', - 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', - 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', - 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_WE', - 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', - 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', - 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', - 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 571: 'PH_PERF_SEL_SC4_PA5_FPOP_WE', - 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', - 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', - 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_WE', - 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', - 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', - 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', - 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 583: 'PH_PERF_SEL_SC4_PA6_FPOP_WE', - 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', - 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', - 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_WE', - 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', - 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', - 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', - 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 595: 'PH_PERF_SEL_SC4_PA7_FPOP_WE', - 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', - 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', - 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_WE', - 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 608: 'PH_PERF_SEL_SC5_ARB_BUSY', - 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 616: 'PH_PERF_SEL_SC5_SEND', - 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', - 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', - 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', - 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 631: 'PH_PERF_SEL_SC5_PA0_FPOP_WE', - 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', - 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', - 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_WE', - 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', - 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', - 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', - 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 643: 'PH_PERF_SEL_SC5_PA1_FPOP_WE', - 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', - 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', - 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_WE', - 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', - 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', - 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', - 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 655: 'PH_PERF_SEL_SC5_PA2_FPOP_WE', - 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', - 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', - 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_WE', - 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', - 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', - 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', - 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 667: 'PH_PERF_SEL_SC5_PA3_FPOP_WE', - 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', - 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', - 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_WE', - 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', - 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', - 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', - 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 679: 'PH_PERF_SEL_SC5_PA4_FPOP_WE', - 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', - 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', - 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_WE', - 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', - 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', - 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', - 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 691: 'PH_PERF_SEL_SC5_PA5_FPOP_WE', - 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', - 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', - 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_WE', - 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', - 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', - 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', - 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 703: 'PH_PERF_SEL_SC5_PA6_FPOP_WE', - 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', - 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', - 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_WE', - 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', - 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', - 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', - 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 715: 'PH_PERF_SEL_SC5_PA7_FPOP_WE', - 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', - 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', - 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_WE', - 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 728: 'PH_PERF_SEL_SC6_ARB_BUSY', - 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 736: 'PH_PERF_SEL_SC6_SEND', - 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', - 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', - 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', - 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 751: 'PH_PERF_SEL_SC6_PA0_FPOP_WE', - 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', - 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', - 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_WE', - 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', - 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', - 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', - 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 763: 'PH_PERF_SEL_SC6_PA1_FPOP_WE', - 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', - 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', - 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_WE', - 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', - 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', - 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', - 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 775: 'PH_PERF_SEL_SC6_PA2_FPOP_WE', - 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', - 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', - 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_WE', - 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', - 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', - 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', - 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 787: 'PH_PERF_SEL_SC6_PA3_FPOP_WE', - 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', - 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', - 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_WE', - 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', - 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', - 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', - 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 799: 'PH_PERF_SEL_SC6_PA4_FPOP_WE', - 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', - 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', - 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_WE', - 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', - 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', - 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', - 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 811: 'PH_PERF_SEL_SC6_PA5_FPOP_WE', - 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', - 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', - 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_WE', - 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', - 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', - 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', - 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 823: 'PH_PERF_SEL_SC6_PA6_FPOP_WE', - 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', - 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', - 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_WE', - 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', - 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', - 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', - 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 835: 'PH_PERF_SEL_SC6_PA7_FPOP_WE', - 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', - 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', - 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_WE', - 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 848: 'PH_PERF_SEL_SC7_ARB_BUSY', - 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 856: 'PH_PERF_SEL_SC7_SEND', - 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', - 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', - 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', - 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 871: 'PH_PERF_SEL_SC7_PA0_FPOP_WE', - 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', - 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', - 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_WE', - 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', - 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', - 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', - 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 883: 'PH_PERF_SEL_SC7_PA1_FPOP_WE', - 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', - 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', - 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_WE', - 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', - 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', - 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', - 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 895: 'PH_PERF_SEL_SC7_PA2_FPOP_WE', - 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', - 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', - 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_WE', - 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', - 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', - 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', - 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 907: 'PH_PERF_SEL_SC7_PA3_FPOP_WE', - 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', - 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', - 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_WE', - 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', - 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', - 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', - 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 919: 'PH_PERF_SEL_SC7_PA4_FPOP_WE', - 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', - 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', - 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_WE', - 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', - 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', - 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', - 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 931: 'PH_PERF_SEL_SC7_PA5_FPOP_WE', - 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', - 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', - 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_WE', - 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', - 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', - 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', - 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 943: 'PH_PERF_SEL_SC7_PA6_FPOP_WE', - 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', - 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', - 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_WE', - 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', - 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', - 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', - 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 955: 'PH_PERF_SEL_SC7_PA7_FPOP_WE', - 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', - 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', - 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_WE', - 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 992: 'PH_PERF_SC0_FIFO_STATUS_0', - 993: 'PH_PERF_SC0_FIFO_STATUS_1', - 994: 'PH_PERF_SC0_FIFO_STATUS_2', - 995: 'PH_PERF_SC0_FIFO_STATUS_3', - 996: 'PH_PERF_SC1_FIFO_STATUS_0', - 997: 'PH_PERF_SC1_FIFO_STATUS_1', - 998: 'PH_PERF_SC1_FIFO_STATUS_2', - 999: 'PH_PERF_SC1_FIFO_STATUS_3', - 1000: 'PH_PERF_SC2_FIFO_STATUS_0', - 1001: 'PH_PERF_SC2_FIFO_STATUS_1', - 1002: 'PH_PERF_SC2_FIFO_STATUS_2', - 1003: 'PH_PERF_SC2_FIFO_STATUS_3', - 1004: 'PH_PERF_SC3_FIFO_STATUS_0', - 1005: 'PH_PERF_SC3_FIFO_STATUS_1', - 1006: 'PH_PERF_SC3_FIFO_STATUS_2', - 1007: 'PH_PERF_SC3_FIFO_STATUS_3', - 1008: 'PH_PERF_SC4_FIFO_STATUS_0', - 1009: 'PH_PERF_SC4_FIFO_STATUS_1', - 1010: 'PH_PERF_SC4_FIFO_STATUS_2', - 1011: 'PH_PERF_SC4_FIFO_STATUS_3', - 1012: 'PH_PERF_SC5_FIFO_STATUS_0', - 1013: 'PH_PERF_SC5_FIFO_STATUS_1', - 1014: 'PH_PERF_SC5_FIFO_STATUS_2', - 1015: 'PH_PERF_SC5_FIFO_STATUS_3', - 1016: 'PH_PERF_SC6_FIFO_STATUS_0', - 1017: 'PH_PERF_SC6_FIFO_STATUS_1', - 1018: 'PH_PERF_SC6_FIFO_STATUS_2', - 1019: 'PH_PERF_SC6_FIFO_STATUS_3', - 1020: 'PH_PERF_SC7_FIFO_STATUS_0', - 1021: 'PH_PERF_SC7_FIFO_STATUS_1', - 1022: 'PH_PERF_SC7_FIFO_STATUS_2', - 1023: 'PH_PERF_SC7_FIFO_STATUS_3', -} -PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 -PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 -PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 -PH_PERF_SEL_SC0_ARB_BUSY = 8 -PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 -PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 -PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 -PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 -PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 -PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 -PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 -PH_PERF_SEL_SC0_SEND = 16 -PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 -PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 -PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 -PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 -PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 -PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 -PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 -PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 -PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 -PH_PERF_SEL_SC0_PA0_NULL_WE = 28 -PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 -PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 -PH_PERF_SEL_SC0_PA0_FPOP_WE = 31 -PH_PERF_SEL_SC0_PA0_EOP_WE = 32 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 -PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 -PH_PERF_SEL_SC0_PA0_DEALLOC_WE = 35 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 -PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 -PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 -PH_PERF_SEL_SC0_PA1_NULL_WE = 40 -PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 -PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 -PH_PERF_SEL_SC0_PA1_FPOP_WE = 43 -PH_PERF_SEL_SC0_PA1_EOP_WE = 44 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 -PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 -PH_PERF_SEL_SC0_PA1_DEALLOC_WE = 47 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 -PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 -PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 -PH_PERF_SEL_SC0_PA2_NULL_WE = 52 -PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 -PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 -PH_PERF_SEL_SC0_PA2_FPOP_WE = 55 -PH_PERF_SEL_SC0_PA2_EOP_WE = 56 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 -PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 -PH_PERF_SEL_SC0_PA2_DEALLOC_WE = 59 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 -PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 -PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 -PH_PERF_SEL_SC0_PA3_NULL_WE = 64 -PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 -PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 -PH_PERF_SEL_SC0_PA3_FPOP_WE = 67 -PH_PERF_SEL_SC0_PA3_EOP_WE = 68 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 -PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 -PH_PERF_SEL_SC0_PA3_DEALLOC_WE = 71 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 -PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 -PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 -PH_PERF_SEL_SC0_PA4_NULL_WE = 76 -PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 -PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 -PH_PERF_SEL_SC0_PA4_FPOP_WE = 79 -PH_PERF_SEL_SC0_PA4_EOP_WE = 80 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 -PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 -PH_PERF_SEL_SC0_PA4_DEALLOC_WE = 83 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 -PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 -PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 -PH_PERF_SEL_SC0_PA5_NULL_WE = 88 -PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 -PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 -PH_PERF_SEL_SC0_PA5_FPOP_WE = 91 -PH_PERF_SEL_SC0_PA5_EOP_WE = 92 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 -PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 -PH_PERF_SEL_SC0_PA5_DEALLOC_WE = 95 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 -PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 -PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 -PH_PERF_SEL_SC0_PA6_NULL_WE = 100 -PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 -PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 -PH_PERF_SEL_SC0_PA6_FPOP_WE = 103 -PH_PERF_SEL_SC0_PA6_EOP_WE = 104 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 -PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 -PH_PERF_SEL_SC0_PA6_DEALLOC_WE = 107 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 -PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 -PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 -PH_PERF_SEL_SC0_PA7_NULL_WE = 112 -PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 -PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 -PH_PERF_SEL_SC0_PA7_FPOP_WE = 115 -PH_PERF_SEL_SC0_PA7_EOP_WE = 116 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 -PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 -PH_PERF_SEL_SC0_PA7_DEALLOC_WE = 119 -PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 -PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 -PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 -PH_PERF_SEL_SC1_ARB_BUSY = 128 -PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 -PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 -PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 -PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 -PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 -PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 -PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 -PH_PERF_SEL_SC1_SEND = 136 -PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 -PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 -PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 -PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 -PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 -PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 -PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 -PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 -PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 -PH_PERF_SEL_SC1_PA0_NULL_WE = 148 -PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 -PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 -PH_PERF_SEL_SC1_PA0_FPOP_WE = 151 -PH_PERF_SEL_SC1_PA0_EOP_WE = 152 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 -PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 -PH_PERF_SEL_SC1_PA0_DEALLOC_WE = 155 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 -PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 -PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 -PH_PERF_SEL_SC1_PA1_NULL_WE = 160 -PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 -PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 -PH_PERF_SEL_SC1_PA1_FPOP_WE = 163 -PH_PERF_SEL_SC1_PA1_EOP_WE = 164 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 -PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 -PH_PERF_SEL_SC1_PA1_DEALLOC_WE = 167 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 -PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 -PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 -PH_PERF_SEL_SC1_PA2_NULL_WE = 172 -PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 -PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 -PH_PERF_SEL_SC1_PA2_FPOP_WE = 175 -PH_PERF_SEL_SC1_PA2_EOP_WE = 176 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 -PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 -PH_PERF_SEL_SC1_PA2_DEALLOC_WE = 179 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 -PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 -PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 -PH_PERF_SEL_SC1_PA3_NULL_WE = 184 -PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 -PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 -PH_PERF_SEL_SC1_PA3_FPOP_WE = 187 -PH_PERF_SEL_SC1_PA3_EOP_WE = 188 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 -PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 -PH_PERF_SEL_SC1_PA3_DEALLOC_WE = 191 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 -PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 -PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 -PH_PERF_SEL_SC1_PA4_NULL_WE = 196 -PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 -PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 -PH_PERF_SEL_SC1_PA4_FPOP_WE = 199 -PH_PERF_SEL_SC1_PA4_EOP_WE = 200 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 -PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 -PH_PERF_SEL_SC1_PA4_DEALLOC_WE = 203 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 -PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 -PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 -PH_PERF_SEL_SC1_PA5_NULL_WE = 208 -PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 -PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 -PH_PERF_SEL_SC1_PA5_FPOP_WE = 211 -PH_PERF_SEL_SC1_PA5_EOP_WE = 212 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 -PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 -PH_PERF_SEL_SC1_PA5_DEALLOC_WE = 215 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 -PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 -PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 -PH_PERF_SEL_SC1_PA6_NULL_WE = 220 -PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 -PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 -PH_PERF_SEL_SC1_PA6_FPOP_WE = 223 -PH_PERF_SEL_SC1_PA6_EOP_WE = 224 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 -PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 -PH_PERF_SEL_SC1_PA6_DEALLOC_WE = 227 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 -PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 -PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 -PH_PERF_SEL_SC1_PA7_NULL_WE = 232 -PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 -PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 -PH_PERF_SEL_SC1_PA7_FPOP_WE = 235 -PH_PERF_SEL_SC1_PA7_EOP_WE = 236 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 -PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 -PH_PERF_SEL_SC1_PA7_DEALLOC_WE = 239 -PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 -PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 -PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 -PH_PERF_SEL_SC2_ARB_BUSY = 248 -PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 -PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 -PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 -PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 -PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 -PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 -PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 -PH_PERF_SEL_SC2_SEND = 256 -PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 -PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 -PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 -PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 -PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 -PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 -PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 -PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 -PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 -PH_PERF_SEL_SC2_PA0_NULL_WE = 268 -PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 -PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 -PH_PERF_SEL_SC2_PA0_FPOP_WE = 271 -PH_PERF_SEL_SC2_PA0_EOP_WE = 272 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 -PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 -PH_PERF_SEL_SC2_PA0_DEALLOC_WE = 275 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 -PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 -PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 -PH_PERF_SEL_SC2_PA1_NULL_WE = 280 -PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 -PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 -PH_PERF_SEL_SC2_PA1_FPOP_WE = 283 -PH_PERF_SEL_SC2_PA1_EOP_WE = 284 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 -PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 -PH_PERF_SEL_SC2_PA1_DEALLOC_WE = 287 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 -PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 -PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 -PH_PERF_SEL_SC2_PA2_NULL_WE = 292 -PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 -PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 -PH_PERF_SEL_SC2_PA2_FPOP_WE = 295 -PH_PERF_SEL_SC2_PA2_EOP_WE = 296 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 -PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 -PH_PERF_SEL_SC2_PA2_DEALLOC_WE = 299 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 -PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 -PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 -PH_PERF_SEL_SC2_PA3_NULL_WE = 304 -PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 -PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 -PH_PERF_SEL_SC2_PA3_FPOP_WE = 307 -PH_PERF_SEL_SC2_PA3_EOP_WE = 308 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 -PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 -PH_PERF_SEL_SC2_PA3_DEALLOC_WE = 311 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 -PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 -PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 -PH_PERF_SEL_SC2_PA4_NULL_WE = 316 -PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 -PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 -PH_PERF_SEL_SC2_PA4_FPOP_WE = 319 -PH_PERF_SEL_SC2_PA4_EOP_WE = 320 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 -PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 -PH_PERF_SEL_SC2_PA4_DEALLOC_WE = 323 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 -PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 -PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 -PH_PERF_SEL_SC2_PA5_NULL_WE = 328 -PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 -PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 -PH_PERF_SEL_SC2_PA5_FPOP_WE = 331 -PH_PERF_SEL_SC2_PA5_EOP_WE = 332 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 -PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 -PH_PERF_SEL_SC2_PA5_DEALLOC_WE = 335 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 -PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 -PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 -PH_PERF_SEL_SC2_PA6_NULL_WE = 340 -PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 -PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 -PH_PERF_SEL_SC2_PA6_FPOP_WE = 343 -PH_PERF_SEL_SC2_PA6_EOP_WE = 344 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 -PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 -PH_PERF_SEL_SC2_PA6_DEALLOC_WE = 347 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 -PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 -PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 -PH_PERF_SEL_SC2_PA7_NULL_WE = 352 -PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 -PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 -PH_PERF_SEL_SC2_PA7_FPOP_WE = 355 -PH_PERF_SEL_SC2_PA7_EOP_WE = 356 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 -PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 -PH_PERF_SEL_SC2_PA7_DEALLOC_WE = 359 -PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 -PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 -PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 -PH_PERF_SEL_SC3_ARB_BUSY = 368 -PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 -PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 -PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 -PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 -PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 -PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 -PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 -PH_PERF_SEL_SC3_SEND = 376 -PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 -PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 -PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 -PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 -PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 -PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 -PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 -PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 -PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 -PH_PERF_SEL_SC3_PA0_NULL_WE = 388 -PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 -PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 -PH_PERF_SEL_SC3_PA0_FPOP_WE = 391 -PH_PERF_SEL_SC3_PA0_EOP_WE = 392 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 -PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 -PH_PERF_SEL_SC3_PA0_DEALLOC_WE = 395 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 -PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 -PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 -PH_PERF_SEL_SC3_PA1_NULL_WE = 400 -PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 -PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 -PH_PERF_SEL_SC3_PA1_FPOP_WE = 403 -PH_PERF_SEL_SC3_PA1_EOP_WE = 404 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 -PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 -PH_PERF_SEL_SC3_PA1_DEALLOC_WE = 407 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 -PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 -PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 -PH_PERF_SEL_SC3_PA2_NULL_WE = 412 -PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 -PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 -PH_PERF_SEL_SC3_PA2_FPOP_WE = 415 -PH_PERF_SEL_SC3_PA2_EOP_WE = 416 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 -PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 -PH_PERF_SEL_SC3_PA2_DEALLOC_WE = 419 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 -PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 -PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 -PH_PERF_SEL_SC3_PA3_NULL_WE = 424 -PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 -PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 -PH_PERF_SEL_SC3_PA3_FPOP_WE = 427 -PH_PERF_SEL_SC3_PA3_EOP_WE = 428 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 -PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 -PH_PERF_SEL_SC3_PA3_DEALLOC_WE = 431 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 -PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 -PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 -PH_PERF_SEL_SC3_PA4_NULL_WE = 436 -PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 -PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 -PH_PERF_SEL_SC3_PA4_FPOP_WE = 439 -PH_PERF_SEL_SC3_PA4_EOP_WE = 440 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 -PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 -PH_PERF_SEL_SC3_PA4_DEALLOC_WE = 443 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 -PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 -PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 -PH_PERF_SEL_SC3_PA5_NULL_WE = 448 -PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 -PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 -PH_PERF_SEL_SC3_PA5_FPOP_WE = 451 -PH_PERF_SEL_SC3_PA5_EOP_WE = 452 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 -PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 -PH_PERF_SEL_SC3_PA5_DEALLOC_WE = 455 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 -PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 -PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 -PH_PERF_SEL_SC3_PA6_NULL_WE = 460 -PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 -PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 -PH_PERF_SEL_SC3_PA6_FPOP_WE = 463 -PH_PERF_SEL_SC3_PA6_EOP_WE = 464 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 -PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 -PH_PERF_SEL_SC3_PA6_DEALLOC_WE = 467 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 -PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 -PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 -PH_PERF_SEL_SC3_PA7_NULL_WE = 472 -PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 -PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 -PH_PERF_SEL_SC3_PA7_FPOP_WE = 475 -PH_PERF_SEL_SC3_PA7_EOP_WE = 476 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 -PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 -PH_PERF_SEL_SC3_PA7_DEALLOC_WE = 479 -PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 -PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 -PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 -PH_PERF_SEL_SC4_ARB_BUSY = 488 -PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 -PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 -PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 -PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 -PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 -PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 -PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 -PH_PERF_SEL_SC4_SEND = 496 -PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 -PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 -PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 -PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 -PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 -PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 -PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 -PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 -PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 -PH_PERF_SEL_SC4_PA0_NULL_WE = 508 -PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 -PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 -PH_PERF_SEL_SC4_PA0_FPOP_WE = 511 -PH_PERF_SEL_SC4_PA0_EOP_WE = 512 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 -PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 -PH_PERF_SEL_SC4_PA0_DEALLOC_WE = 515 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 -PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 -PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 -PH_PERF_SEL_SC4_PA1_NULL_WE = 520 -PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 -PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 -PH_PERF_SEL_SC4_PA1_FPOP_WE = 523 -PH_PERF_SEL_SC4_PA1_EOP_WE = 524 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 -PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 -PH_PERF_SEL_SC4_PA1_DEALLOC_WE = 527 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 -PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 -PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 -PH_PERF_SEL_SC4_PA2_NULL_WE = 532 -PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 -PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 -PH_PERF_SEL_SC4_PA2_FPOP_WE = 535 -PH_PERF_SEL_SC4_PA2_EOP_WE = 536 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 -PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 -PH_PERF_SEL_SC4_PA2_DEALLOC_WE = 539 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 -PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 -PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 -PH_PERF_SEL_SC4_PA3_NULL_WE = 544 -PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 -PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 -PH_PERF_SEL_SC4_PA3_FPOP_WE = 547 -PH_PERF_SEL_SC4_PA3_EOP_WE = 548 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 -PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 -PH_PERF_SEL_SC4_PA3_DEALLOC_WE = 551 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 -PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 -PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 -PH_PERF_SEL_SC4_PA4_NULL_WE = 556 -PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 -PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 -PH_PERF_SEL_SC4_PA4_FPOP_WE = 559 -PH_PERF_SEL_SC4_PA4_EOP_WE = 560 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 -PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 -PH_PERF_SEL_SC4_PA4_DEALLOC_WE = 563 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 -PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 -PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 -PH_PERF_SEL_SC4_PA5_NULL_WE = 568 -PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 -PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 -PH_PERF_SEL_SC4_PA5_FPOP_WE = 571 -PH_PERF_SEL_SC4_PA5_EOP_WE = 572 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 -PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 -PH_PERF_SEL_SC4_PA5_DEALLOC_WE = 575 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 -PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 -PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 -PH_PERF_SEL_SC4_PA6_NULL_WE = 580 -PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 -PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 -PH_PERF_SEL_SC4_PA6_FPOP_WE = 583 -PH_PERF_SEL_SC4_PA6_EOP_WE = 584 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 -PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 -PH_PERF_SEL_SC4_PA6_DEALLOC_WE = 587 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 -PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 -PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 -PH_PERF_SEL_SC4_PA7_NULL_WE = 592 -PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 -PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 -PH_PERF_SEL_SC4_PA7_FPOP_WE = 595 -PH_PERF_SEL_SC4_PA7_EOP_WE = 596 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 -PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 -PH_PERF_SEL_SC4_PA7_DEALLOC_WE = 599 -PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 -PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 -PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 -PH_PERF_SEL_SC5_ARB_BUSY = 608 -PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 -PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 -PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 -PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 -PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 -PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 -PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 -PH_PERF_SEL_SC5_SEND = 616 -PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 -PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 -PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 -PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 -PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 -PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 -PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 -PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 -PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 -PH_PERF_SEL_SC5_PA0_NULL_WE = 628 -PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 -PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 -PH_PERF_SEL_SC5_PA0_FPOP_WE = 631 -PH_PERF_SEL_SC5_PA0_EOP_WE = 632 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 -PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 -PH_PERF_SEL_SC5_PA0_DEALLOC_WE = 635 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 -PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 -PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 -PH_PERF_SEL_SC5_PA1_NULL_WE = 640 -PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 -PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 -PH_PERF_SEL_SC5_PA1_FPOP_WE = 643 -PH_PERF_SEL_SC5_PA1_EOP_WE = 644 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 -PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 -PH_PERF_SEL_SC5_PA1_DEALLOC_WE = 647 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 -PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 -PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 -PH_PERF_SEL_SC5_PA2_NULL_WE = 652 -PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 -PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 -PH_PERF_SEL_SC5_PA2_FPOP_WE = 655 -PH_PERF_SEL_SC5_PA2_EOP_WE = 656 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 -PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 -PH_PERF_SEL_SC5_PA2_DEALLOC_WE = 659 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 -PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 -PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 -PH_PERF_SEL_SC5_PA3_NULL_WE = 664 -PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 -PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 -PH_PERF_SEL_SC5_PA3_FPOP_WE = 667 -PH_PERF_SEL_SC5_PA3_EOP_WE = 668 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 -PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 -PH_PERF_SEL_SC5_PA3_DEALLOC_WE = 671 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 -PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 -PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 -PH_PERF_SEL_SC5_PA4_NULL_WE = 676 -PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 -PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 -PH_PERF_SEL_SC5_PA4_FPOP_WE = 679 -PH_PERF_SEL_SC5_PA4_EOP_WE = 680 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 -PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 -PH_PERF_SEL_SC5_PA4_DEALLOC_WE = 683 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 -PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 -PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 -PH_PERF_SEL_SC5_PA5_NULL_WE = 688 -PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 -PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 -PH_PERF_SEL_SC5_PA5_FPOP_WE = 691 -PH_PERF_SEL_SC5_PA5_EOP_WE = 692 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 -PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 -PH_PERF_SEL_SC5_PA5_DEALLOC_WE = 695 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 -PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 -PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 -PH_PERF_SEL_SC5_PA6_NULL_WE = 700 -PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 -PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 -PH_PERF_SEL_SC5_PA6_FPOP_WE = 703 -PH_PERF_SEL_SC5_PA6_EOP_WE = 704 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 -PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 -PH_PERF_SEL_SC5_PA6_DEALLOC_WE = 707 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 -PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 -PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 -PH_PERF_SEL_SC5_PA7_NULL_WE = 712 -PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 -PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 -PH_PERF_SEL_SC5_PA7_FPOP_WE = 715 -PH_PERF_SEL_SC5_PA7_EOP_WE = 716 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 -PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 -PH_PERF_SEL_SC5_PA7_DEALLOC_WE = 719 -PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 -PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 -PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 -PH_PERF_SEL_SC6_ARB_BUSY = 728 -PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 -PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 -PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 -PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 -PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 -PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 -PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 -PH_PERF_SEL_SC6_SEND = 736 -PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 -PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 -PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 -PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 -PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 -PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 -PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 -PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 -PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 -PH_PERF_SEL_SC6_PA0_NULL_WE = 748 -PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 -PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 -PH_PERF_SEL_SC6_PA0_FPOP_WE = 751 -PH_PERF_SEL_SC6_PA0_EOP_WE = 752 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 -PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 -PH_PERF_SEL_SC6_PA0_DEALLOC_WE = 755 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 -PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 -PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 -PH_PERF_SEL_SC6_PA1_NULL_WE = 760 -PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 -PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 -PH_PERF_SEL_SC6_PA1_FPOP_WE = 763 -PH_PERF_SEL_SC6_PA1_EOP_WE = 764 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 -PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 -PH_PERF_SEL_SC6_PA1_DEALLOC_WE = 767 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 -PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 -PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 -PH_PERF_SEL_SC6_PA2_NULL_WE = 772 -PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 -PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 -PH_PERF_SEL_SC6_PA2_FPOP_WE = 775 -PH_PERF_SEL_SC6_PA2_EOP_WE = 776 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 -PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 -PH_PERF_SEL_SC6_PA2_DEALLOC_WE = 779 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 -PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 -PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 -PH_PERF_SEL_SC6_PA3_NULL_WE = 784 -PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 -PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 -PH_PERF_SEL_SC6_PA3_FPOP_WE = 787 -PH_PERF_SEL_SC6_PA3_EOP_WE = 788 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 -PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 -PH_PERF_SEL_SC6_PA3_DEALLOC_WE = 791 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 -PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 -PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 -PH_PERF_SEL_SC6_PA4_NULL_WE = 796 -PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 -PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 -PH_PERF_SEL_SC6_PA4_FPOP_WE = 799 -PH_PERF_SEL_SC6_PA4_EOP_WE = 800 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 -PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 -PH_PERF_SEL_SC6_PA4_DEALLOC_WE = 803 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 -PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 -PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 -PH_PERF_SEL_SC6_PA5_NULL_WE = 808 -PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 -PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 -PH_PERF_SEL_SC6_PA5_FPOP_WE = 811 -PH_PERF_SEL_SC6_PA5_EOP_WE = 812 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 -PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 -PH_PERF_SEL_SC6_PA5_DEALLOC_WE = 815 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 -PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 -PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 -PH_PERF_SEL_SC6_PA6_NULL_WE = 820 -PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 -PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 -PH_PERF_SEL_SC6_PA6_FPOP_WE = 823 -PH_PERF_SEL_SC6_PA6_EOP_WE = 824 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 -PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 -PH_PERF_SEL_SC6_PA6_DEALLOC_WE = 827 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 -PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 -PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 -PH_PERF_SEL_SC6_PA7_NULL_WE = 832 -PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 -PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 -PH_PERF_SEL_SC6_PA7_FPOP_WE = 835 -PH_PERF_SEL_SC6_PA7_EOP_WE = 836 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 -PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 -PH_PERF_SEL_SC6_PA7_DEALLOC_WE = 839 -PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 -PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 -PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 -PH_PERF_SEL_SC7_ARB_BUSY = 848 -PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 -PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 -PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 -PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 -PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 -PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 -PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 -PH_PERF_SEL_SC7_SEND = 856 -PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 -PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 -PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 -PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 -PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 -PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 -PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 -PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 -PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 -PH_PERF_SEL_SC7_PA0_NULL_WE = 868 -PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 -PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 -PH_PERF_SEL_SC7_PA0_FPOP_WE = 871 -PH_PERF_SEL_SC7_PA0_EOP_WE = 872 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 -PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 -PH_PERF_SEL_SC7_PA0_DEALLOC_WE = 875 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 -PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 -PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 -PH_PERF_SEL_SC7_PA1_NULL_WE = 880 -PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 -PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 -PH_PERF_SEL_SC7_PA1_FPOP_WE = 883 -PH_PERF_SEL_SC7_PA1_EOP_WE = 884 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 -PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 -PH_PERF_SEL_SC7_PA1_DEALLOC_WE = 887 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 -PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 -PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 -PH_PERF_SEL_SC7_PA2_NULL_WE = 892 -PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 -PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 -PH_PERF_SEL_SC7_PA2_FPOP_WE = 895 -PH_PERF_SEL_SC7_PA2_EOP_WE = 896 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 -PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 -PH_PERF_SEL_SC7_PA2_DEALLOC_WE = 899 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 -PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 -PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 -PH_PERF_SEL_SC7_PA3_NULL_WE = 904 -PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 -PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 -PH_PERF_SEL_SC7_PA3_FPOP_WE = 907 -PH_PERF_SEL_SC7_PA3_EOP_WE = 908 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 -PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 -PH_PERF_SEL_SC7_PA3_DEALLOC_WE = 911 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 -PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 -PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 -PH_PERF_SEL_SC7_PA4_NULL_WE = 916 -PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 -PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 -PH_PERF_SEL_SC7_PA4_FPOP_WE = 919 -PH_PERF_SEL_SC7_PA4_EOP_WE = 920 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 -PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 -PH_PERF_SEL_SC7_PA4_DEALLOC_WE = 923 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 -PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 -PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 -PH_PERF_SEL_SC7_PA5_NULL_WE = 928 -PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 -PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 -PH_PERF_SEL_SC7_PA5_FPOP_WE = 931 -PH_PERF_SEL_SC7_PA5_EOP_WE = 932 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 -PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 -PH_PERF_SEL_SC7_PA5_DEALLOC_WE = 935 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 -PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 -PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 -PH_PERF_SEL_SC7_PA6_NULL_WE = 940 -PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 -PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 -PH_PERF_SEL_SC7_PA6_FPOP_WE = 943 -PH_PERF_SEL_SC7_PA6_EOP_WE = 944 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 -PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 -PH_PERF_SEL_SC7_PA6_DEALLOC_WE = 947 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 -PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 -PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 -PH_PERF_SEL_SC7_PA7_NULL_WE = 952 -PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 -PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 -PH_PERF_SEL_SC7_PA7_FPOP_WE = 955 -PH_PERF_SEL_SC7_PA7_EOP_WE = 956 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 -PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 -PH_PERF_SEL_SC7_PA7_DEALLOC_WE = 959 -PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 -PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 -PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 -PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 -PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 -PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 -PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 -PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 -PH_PERF_SC0_FIFO_STATUS_0 = 992 -PH_PERF_SC0_FIFO_STATUS_1 = 993 -PH_PERF_SC0_FIFO_STATUS_2 = 994 -PH_PERF_SC0_FIFO_STATUS_3 = 995 -PH_PERF_SC1_FIFO_STATUS_0 = 996 -PH_PERF_SC1_FIFO_STATUS_1 = 997 -PH_PERF_SC1_FIFO_STATUS_2 = 998 -PH_PERF_SC1_FIFO_STATUS_3 = 999 -PH_PERF_SC2_FIFO_STATUS_0 = 1000 -PH_PERF_SC2_FIFO_STATUS_1 = 1001 -PH_PERF_SC2_FIFO_STATUS_2 = 1002 -PH_PERF_SC2_FIFO_STATUS_3 = 1003 -PH_PERF_SC3_FIFO_STATUS_0 = 1004 -PH_PERF_SC3_FIFO_STATUS_1 = 1005 -PH_PERF_SC3_FIFO_STATUS_2 = 1006 -PH_PERF_SC3_FIFO_STATUS_3 = 1007 -PH_PERF_SC4_FIFO_STATUS_0 = 1008 -PH_PERF_SC4_FIFO_STATUS_1 = 1009 -PH_PERF_SC4_FIFO_STATUS_2 = 1010 -PH_PERF_SC4_FIFO_STATUS_3 = 1011 -PH_PERF_SC5_FIFO_STATUS_0 = 1012 -PH_PERF_SC5_FIFO_STATUS_1 = 1013 -PH_PERF_SC5_FIFO_STATUS_2 = 1014 -PH_PERF_SC5_FIFO_STATUS_3 = 1015 -PH_PERF_SC6_FIFO_STATUS_0 = 1016 -PH_PERF_SC6_FIFO_STATUS_1 = 1017 -PH_PERF_SC6_FIFO_STATUS_2 = 1018 -PH_PERF_SC6_FIFO_STATUS_3 = 1019 -PH_PERF_SC7_FIFO_STATUS_0 = 1020 -PH_PERF_SC7_FIFO_STATUS_1 = 1021 -PH_PERF_SC7_FIFO_STATUS_2 = 1022 -PH_PERF_SC7_FIFO_STATUS_3 = 1023 -PH_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PhSPIstatusMode' -PhSPIstatusMode__enumvalues = { - 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 2: 'PH_SPI_MODE_DISABLED', -} -PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 -PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 -PH_SPI_MODE_DISABLED = 2 -PhSPIstatusMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinEventCntl' -BinEventCntl__enumvalues = { - 0: 'BINNER_BREAK_BATCH', - 1: 'BINNER_PIPELINE', - 2: 'BINNER_DROP', - 3: 'BINNER_PIPELINE_BREAK', -} -BINNER_BREAK_BATCH = 0 -BINNER_PIPELINE = 1 -BINNER_DROP = 2 -BINNER_PIPELINE_BREAK = 3 -BinEventCntl = ctypes.c_uint32 # enum - -# values for enumeration 'BinMapMode' -BinMapMode__enumvalues = { - 0: 'BIN_MAP_MODE_NONE', - 1: 'BIN_MAP_MODE_RTA_INDEX', - 2: 'BIN_MAP_MODE_POPS', -} -BIN_MAP_MODE_NONE = 0 -BIN_MAP_MODE_RTA_INDEX = 1 -BIN_MAP_MODE_POPS = 2 -BinMapMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinSizeExtend' -BinSizeExtend__enumvalues = { - 0: 'BIN_SIZE_32_PIXELS', - 1: 'BIN_SIZE_64_PIXELS', - 2: 'BIN_SIZE_128_PIXELS', - 3: 'BIN_SIZE_256_PIXELS', - 4: 'BIN_SIZE_512_PIXELS', -} -BIN_SIZE_32_PIXELS = 0 -BIN_SIZE_64_PIXELS = 1 -BIN_SIZE_128_PIXELS = 2 -BIN_SIZE_256_PIXELS = 3 -BIN_SIZE_512_PIXELS = 4 -BinSizeExtend = ctypes.c_uint32 # enum - -# values for enumeration 'BinningMode' -BinningMode__enumvalues = { - 0: 'BINNING_ALLOWED', - 1: 'FORCE_BINNING_ON', - 2: 'BINNING_ONE_PRIM_PER_BATCH', - 3: 'BINNING_DISABLED', -} -BINNING_ALLOWED = 0 -FORCE_BINNING_ON = 1 -BINNING_ONE_PRIM_PER_BATCH = 2 -BINNING_DISABLED = 3 -BinningMode = ctypes.c_uint32 # enum - -# values for enumeration 'PkrMap' -PkrMap__enumvalues = { - 0: 'RASTER_CONFIG_PKR_MAP_0', - 1: 'RASTER_CONFIG_PKR_MAP_1', - 2: 'RASTER_CONFIG_PKR_MAP_2', - 3: 'RASTER_CONFIG_PKR_MAP_3', -} -RASTER_CONFIG_PKR_MAP_0 = 0 -RASTER_CONFIG_PKR_MAP_1 = 1 -RASTER_CONFIG_PKR_MAP_2 = 2 -RASTER_CONFIG_PKR_MAP_3 = 3 -PkrMap = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel' -PkrXsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL_0', - 1: 'RASTER_CONFIG_PKR_XSEL_1', - 2: 'RASTER_CONFIG_PKR_XSEL_2', - 3: 'RASTER_CONFIG_PKR_XSEL_3', -} -RASTER_CONFIG_PKR_XSEL_0 = 0 -RASTER_CONFIG_PKR_XSEL_1 = 1 -RASTER_CONFIG_PKR_XSEL_2 = 2 -RASTER_CONFIG_PKR_XSEL_3 = 3 -PkrXsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel2' -PkrXsel2__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL2_0', - 1: 'RASTER_CONFIG_PKR_XSEL2_1', - 2: 'RASTER_CONFIG_PKR_XSEL2_2', - 3: 'RASTER_CONFIG_PKR_XSEL2_3', -} -RASTER_CONFIG_PKR_XSEL2_0 = 0 -RASTER_CONFIG_PKR_XSEL2_1 = 1 -RASTER_CONFIG_PKR_XSEL2_2 = 2 -RASTER_CONFIG_PKR_XSEL2_3 = 3 -PkrXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'PkrYsel' -PkrYsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_YSEL_0', - 1: 'RASTER_CONFIG_PKR_YSEL_1', - 2: 'RASTER_CONFIG_PKR_YSEL_2', - 3: 'RASTER_CONFIG_PKR_YSEL_3', -} -RASTER_CONFIG_PKR_YSEL_0 = 0 -RASTER_CONFIG_PKR_YSEL_1 = 1 -RASTER_CONFIG_PKR_YSEL_2 = 2 -RASTER_CONFIG_PKR_YSEL_3 = 3 -PkrYsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbMap' -RbMap__enumvalues = { - 0: 'RASTER_CONFIG_RB_MAP_0', - 1: 'RASTER_CONFIG_RB_MAP_1', - 2: 'RASTER_CONFIG_RB_MAP_2', - 3: 'RASTER_CONFIG_RB_MAP_3', -} -RASTER_CONFIG_RB_MAP_0 = 0 -RASTER_CONFIG_RB_MAP_1 = 1 -RASTER_CONFIG_RB_MAP_2 = 2 -RASTER_CONFIG_RB_MAP_3 = 3 -RbMap = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel' -RbXsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL_0', - 1: 'RASTER_CONFIG_RB_XSEL_1', -} -RASTER_CONFIG_RB_XSEL_0 = 0 -RASTER_CONFIG_RB_XSEL_1 = 1 -RbXsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel2' -RbXsel2__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL2_0', - 1: 'RASTER_CONFIG_RB_XSEL2_1', - 2: 'RASTER_CONFIG_RB_XSEL2_2', - 3: 'RASTER_CONFIG_RB_XSEL2_3', -} -RASTER_CONFIG_RB_XSEL2_0 = 0 -RASTER_CONFIG_RB_XSEL2_1 = 1 -RASTER_CONFIG_RB_XSEL2_2 = 2 -RASTER_CONFIG_RB_XSEL2_3 = 3 -RbXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'RbYsel' -RbYsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_YSEL_0', - 1: 'RASTER_CONFIG_RB_YSEL_1', -} -RASTER_CONFIG_RB_YSEL_0 = 0 -RASTER_CONFIG_RB_YSEL_1 = 1 -RbYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SC_PERFCNT_SEL' -SC_PERFCNT_SEL__enumvalues = { - 0: 'SC_SRPS_WINDOW_VALID', - 1: 'SC_PSSW_WINDOW_VALID', - 2: 'SC_TPQZ_WINDOW_VALID', - 3: 'SC_QZQP_WINDOW_VALID', - 4: 'SC_TRPK_WINDOW_VALID', - 5: 'SC_SRPS_WINDOW_VALID_BUSY', - 6: 'SC_PSSW_WINDOW_VALID_BUSY', - 7: 'SC_TPQZ_WINDOW_VALID_BUSY', - 8: 'SC_QZQP_WINDOW_VALID_BUSY', - 9: 'SC_TRPK_WINDOW_VALID_BUSY', - 10: 'SC_STARVED_BY_PA', - 11: 'SC_STALLED_BY_PRIMFIFO', - 12: 'SC_STALLED_BY_DB_TILE', - 13: 'SC_STARVED_BY_DB_TILE', - 14: 'SC_STALLED_BY_TILEORDERFIFO', - 15: 'SC_STALLED_BY_TILEFIFO', - 16: 'SC_STALLED_BY_DB_QUAD', - 17: 'SC_STARVED_BY_DB_QUAD', - 18: 'SC_STALLED_BY_QUADFIFO', - 19: 'SC_STALLED_BY_BCI', - 20: 'SC_STALLED_BY_SPI', - 21: 'SC_SCISSOR_DISCARD', - 22: 'SC_BB_DISCARD', - 23: 'SC_SUPERTILE_COUNT', - 24: 'SC_SUPERTILE_PER_PRIM_H0', - 25: 'SC_SUPERTILE_PER_PRIM_H1', - 26: 'SC_SUPERTILE_PER_PRIM_H2', - 27: 'SC_SUPERTILE_PER_PRIM_H3', - 28: 'SC_SUPERTILE_PER_PRIM_H4', - 29: 'SC_SUPERTILE_PER_PRIM_H5', - 30: 'SC_SUPERTILE_PER_PRIM_H6', - 31: 'SC_SUPERTILE_PER_PRIM_H7', - 32: 'SC_SUPERTILE_PER_PRIM_H8', - 33: 'SC_SUPERTILE_PER_PRIM_H9', - 34: 'SC_SUPERTILE_PER_PRIM_H10', - 35: 'SC_SUPERTILE_PER_PRIM_H11', - 36: 'SC_SUPERTILE_PER_PRIM_H12', - 37: 'SC_SUPERTILE_PER_PRIM_H13', - 38: 'SC_SUPERTILE_PER_PRIM_H14', - 39: 'SC_SUPERTILE_PER_PRIM_H15', - 40: 'SC_SUPERTILE_PER_PRIM_H16', - 41: 'SC_TILE_PER_PRIM_H0', - 42: 'SC_TILE_PER_PRIM_H1', - 43: 'SC_TILE_PER_PRIM_H2', - 44: 'SC_TILE_PER_PRIM_H3', - 45: 'SC_TILE_PER_PRIM_H4', - 46: 'SC_TILE_PER_PRIM_H5', - 47: 'SC_TILE_PER_PRIM_H6', - 48: 'SC_TILE_PER_PRIM_H7', - 49: 'SC_TILE_PER_PRIM_H8', - 50: 'SC_TILE_PER_PRIM_H9', - 51: 'SC_TILE_PER_PRIM_H10', - 52: 'SC_TILE_PER_PRIM_H11', - 53: 'SC_TILE_PER_PRIM_H12', - 54: 'SC_TILE_PER_PRIM_H13', - 55: 'SC_TILE_PER_PRIM_H14', - 56: 'SC_TILE_PER_PRIM_H15', - 57: 'SC_TILE_PER_PRIM_H16', - 58: 'SC_TILE_PER_SUPERTILE_H0', - 59: 'SC_TILE_PER_SUPERTILE_H1', - 60: 'SC_TILE_PER_SUPERTILE_H2', - 61: 'SC_TILE_PER_SUPERTILE_H3', - 62: 'SC_TILE_PER_SUPERTILE_H4', - 63: 'SC_TILE_PER_SUPERTILE_H5', - 64: 'SC_TILE_PER_SUPERTILE_H6', - 65: 'SC_TILE_PER_SUPERTILE_H7', - 66: 'SC_TILE_PER_SUPERTILE_H8', - 67: 'SC_TILE_PER_SUPERTILE_H9', - 68: 'SC_TILE_PER_SUPERTILE_H10', - 69: 'SC_TILE_PER_SUPERTILE_H11', - 70: 'SC_TILE_PER_SUPERTILE_H12', - 71: 'SC_TILE_PER_SUPERTILE_H13', - 72: 'SC_TILE_PER_SUPERTILE_H14', - 73: 'SC_TILE_PER_SUPERTILE_H15', - 74: 'SC_TILE_PER_SUPERTILE_H16', - 75: 'SC_TILE_PICKED_H1', - 76: 'SC_PERF_SEL_RESERVED_76', - 77: 'SC_PERF_SEL_RESERVED_77', - 78: 'SC_PERF_SEL_RESERVED_78', - 79: 'SC_QZ0_TILE_COUNT', - 80: 'SC_PERF_SEL_RESERVED_80', - 81: 'SC_PERF_SEL_RESERVED_81', - 82: 'SC_PERF_SEL_RESERVED_82', - 83: 'SC_QZ0_TILE_COVERED_COUNT', - 84: 'SC_PERF_SEL_RESERVED_84', - 85: 'SC_PERF_SEL_RESERVED_85', - 86: 'SC_PERF_SEL_RESERVED_86', - 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 88: 'SC_PERF_SEL_RESERVED_88', - 89: 'SC_PERF_SEL_RESERVED_89', - 90: 'SC_PERF_SEL_RESERVED_90', - 91: 'SC_QZ0_QUAD_PER_TILE_H0', - 92: 'SC_QZ0_QUAD_PER_TILE_H1', - 93: 'SC_QZ0_QUAD_PER_TILE_H2', - 94: 'SC_QZ0_QUAD_PER_TILE_H3', - 95: 'SC_QZ0_QUAD_PER_TILE_H4', - 96: 'SC_QZ0_QUAD_PER_TILE_H5', - 97: 'SC_QZ0_QUAD_PER_TILE_H6', - 98: 'SC_QZ0_QUAD_PER_TILE_H7', - 99: 'SC_QZ0_QUAD_PER_TILE_H8', - 100: 'SC_QZ0_QUAD_PER_TILE_H9', - 101: 'SC_QZ0_QUAD_PER_TILE_H10', - 102: 'SC_QZ0_QUAD_PER_TILE_H11', - 103: 'SC_QZ0_QUAD_PER_TILE_H12', - 104: 'SC_QZ0_QUAD_PER_TILE_H13', - 105: 'SC_QZ0_QUAD_PER_TILE_H14', - 106: 'SC_QZ0_QUAD_PER_TILE_H15', - 107: 'SC_QZ0_QUAD_PER_TILE_H16', - 108: 'SC_PERF_SEL_RESERVED_108', - 109: 'SC_PERF_SEL_RESERVED_109', - 110: 'SC_PERF_SEL_RESERVED_110', - 111: 'SC_PERF_SEL_RESERVED_111', - 112: 'SC_PERF_SEL_RESERVED_112', - 113: 'SC_PERF_SEL_RESERVED_113', - 114: 'SC_PERF_SEL_RESERVED_114', - 115: 'SC_PERF_SEL_RESERVED_115', - 116: 'SC_PERF_SEL_RESERVED_116', - 117: 'SC_PERF_SEL_RESERVED_117', - 118: 'SC_PERF_SEL_RESERVED_118', - 119: 'SC_PERF_SEL_RESERVED_119', - 120: 'SC_PERF_SEL_RESERVED_120', - 121: 'SC_PERF_SEL_RESERVED_121', - 122: 'SC_PERF_SEL_RESERVED_122', - 123: 'SC_PERF_SEL_RESERVED_123', - 124: 'SC_PERF_SEL_RESERVED_124', - 125: 'SC_PERF_SEL_RESERVED_125', - 126: 'SC_PERF_SEL_RESERVED_126', - 127: 'SC_PERF_SEL_RESERVED_127', - 128: 'SC_PERF_SEL_RESERVED_128', - 129: 'SC_PERF_SEL_RESERVED_129', - 130: 'SC_PERF_SEL_RESERVED_130', - 131: 'SC_PERF_SEL_RESERVED_131', - 132: 'SC_PERF_SEL_RESERVED_132', - 133: 'SC_PERF_SEL_RESERVED_133', - 134: 'SC_PERF_SEL_RESERVED_134', - 135: 'SC_PERF_SEL_RESERVED_135', - 136: 'SC_PERF_SEL_RESERVED_136', - 137: 'SC_PERF_SEL_RESERVED_137', - 138: 'SC_PERF_SEL_RESERVED_138', - 139: 'SC_PERF_SEL_RESERVED_139', - 140: 'SC_PERF_SEL_RESERVED_140', - 141: 'SC_PERF_SEL_RESERVED_141', - 142: 'SC_PERF_SEL_RESERVED_142', - 143: 'SC_PERF_SEL_RESERVED_143', - 144: 'SC_PERF_SEL_RESERVED_144', - 145: 'SC_PERF_SEL_RESERVED_145', - 146: 'SC_PERF_SEL_RESERVED_146', - 147: 'SC_PERF_SEL_RESERVED_147', - 148: 'SC_PERF_SEL_RESERVED_148', - 149: 'SC_PERF_SEL_RESERVED_149', - 150: 'SC_PERF_SEL_RESERVED_150', - 151: 'SC_PERF_SEL_RESERVED_151', - 152: 'SC_PERF_SEL_RESERVED_152', - 153: 'SC_PERF_SEL_RESERVED_153', - 154: 'SC_PERF_SEL_RESERVED_154', - 155: 'SC_PERF_SEL_RESERVED_155', - 156: 'SC_PERF_SEL_RESERVED_156', - 157: 'SC_PERF_SEL_RESERVED_157', - 158: 'SC_PERF_SEL_RESERVED_158', - 159: 'SC_QZ0_QUAD_COUNT', - 160: 'SC_PERF_SEL_RESERVED_160', - 161: 'SC_PERF_SEL_RESERVED_161', - 162: 'SC_PERF_SEL_RESERVED_162', - 163: 'SC_P0_HIZ_TILE_COUNT', - 164: 'SC_PERF_SEL_RESERVED_164', - 165: 'SC_PERF_SEL_RESERVED_165', - 166: 'SC_PERF_SEL_RESERVED_166', - 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 184: 'SC_PERF_SEL_RESERVED_184', - 185: 'SC_PERF_SEL_RESERVED_185', - 186: 'SC_PERF_SEL_RESERVED_186', - 187: 'SC_PERF_SEL_RESERVED_187', - 188: 'SC_PERF_SEL_RESERVED_188', - 189: 'SC_PERF_SEL_RESERVED_189', - 190: 'SC_PERF_SEL_RESERVED_190', - 191: 'SC_PERF_SEL_RESERVED_191', - 192: 'SC_PERF_SEL_RESERVED_192', - 193: 'SC_PERF_SEL_RESERVED_193', - 194: 'SC_PERF_SEL_RESERVED_194', - 195: 'SC_PERF_SEL_RESERVED_195', - 196: 'SC_PERF_SEL_RESERVED_196', - 197: 'SC_PERF_SEL_RESERVED_197', - 198: 'SC_PERF_SEL_RESERVED_198', - 199: 'SC_PERF_SEL_RESERVED_199', - 200: 'SC_PERF_SEL_RESERVED_200', - 201: 'SC_PERF_SEL_RESERVED_201', - 202: 'SC_PERF_SEL_RESERVED_202', - 203: 'SC_PERF_SEL_RESERVED_203', - 204: 'SC_PERF_SEL_RESERVED_204', - 205: 'SC_PERF_SEL_RESERVED_205', - 206: 'SC_PERF_SEL_RESERVED_206', - 207: 'SC_PERF_SEL_RESERVED_207', - 208: 'SC_PERF_SEL_RESERVED_208', - 209: 'SC_PERF_SEL_RESERVED_209', - 210: 'SC_PERF_SEL_RESERVED_210', - 211: 'SC_PERF_SEL_RESERVED_211', - 212: 'SC_PERF_SEL_RESERVED_212', - 213: 'SC_PERF_SEL_RESERVED_213', - 214: 'SC_PERF_SEL_RESERVED_214', - 215: 'SC_PERF_SEL_RESERVED_215', - 216: 'SC_PERF_SEL_RESERVED_216', - 217: 'SC_PERF_SEL_RESERVED_217', - 218: 'SC_PERF_SEL_RESERVED_218', - 219: 'SC_PERF_SEL_RESERVED_219', - 220: 'SC_PERF_SEL_RESERVED_220', - 221: 'SC_PERF_SEL_RESERVED_221', - 222: 'SC_PERF_SEL_RESERVED_222', - 223: 'SC_PERF_SEL_RESERVED_223', - 224: 'SC_PERF_SEL_RESERVED_224', - 225: 'SC_PERF_SEL_RESERVED_225', - 226: 'SC_PERF_SEL_RESERVED_226', - 227: 'SC_PERF_SEL_RESERVED_227', - 228: 'SC_PERF_SEL_RESERVED_228', - 229: 'SC_PERF_SEL_RESERVED_229', - 230: 'SC_PERF_SEL_RESERVED_230', - 231: 'SC_PERF_SEL_RESERVED_231', - 232: 'SC_PERF_SEL_RESERVED_232', - 233: 'SC_PERF_SEL_RESERVED_233', - 234: 'SC_PERF_SEL_RESERVED_234', - 235: 'SC_P0_HIZ_QUAD_COUNT', - 236: 'SC_PERF_SEL_RESERVED_236', - 237: 'SC_PERF_SEL_RESERVED_237', - 238: 'SC_PERF_SEL_RESERVED_238', - 239: 'SC_P0_DETAIL_QUAD_COUNT', - 240: 'SC_PERF_SEL_RESERVED_240', - 241: 'SC_PERF_SEL_RESERVED_241', - 242: 'SC_PERF_SEL_RESERVED_242', - 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 247: 'SC_PERF_SEL_RESERVED_247', - 248: 'SC_PERF_SEL_RESERVED_248', - 249: 'SC_PERF_SEL_RESERVED_249', - 250: 'SC_PERF_SEL_RESERVED_250', - 251: 'SC_PERF_SEL_RESERVED_251', - 252: 'SC_PERF_SEL_RESERVED_252', - 253: 'SC_PERF_SEL_RESERVED_253', - 254: 'SC_PERF_SEL_RESERVED_254', - 255: 'SC_PERF_SEL_RESERVED_255', - 256: 'SC_PERF_SEL_RESERVED_256', - 257: 'SC_PERF_SEL_RESERVED_257', - 258: 'SC_PERF_SEL_RESERVED_258', - 259: 'SC_EARLYZ_QUAD_COUNT', - 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', - 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', - 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', - 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', - 264: 'SC_PKR_QUAD_PER_ROW_H1', - 265: 'SC_PKR_QUAD_PER_ROW_H2', - 266: 'SC_PKR_4X2_QUAD_SPLIT', - 267: 'SC_PKR_4X2_FILL_QUAD', - 268: 'SC_PKR_END_OF_VECTOR', - 269: 'SC_PKR_CONTROL_XFER', - 270: 'SC_PKR_DBHANG_FORCE_EOV', - 271: 'SC_REG_SCLK_BUSY', - 272: 'SC_GRP0_DYN_SCLK_BUSY', - 273: 'SC_GRP1_DYN_SCLK_BUSY', - 274: 'SC_GRP2_DYN_SCLK_BUSY', - 275: 'SC_GRP3_DYN_SCLK_BUSY', - 276: 'SC_GRP4_DYN_SCLK_BUSY', - 277: 'SC_PA0_SC_DATA_FIFO_RD', - 278: 'SC_PA0_SC_DATA_FIFO_WE', - 279: 'SC_PERF_SEL_RESERVED_279', - 280: 'SC_PERF_SEL_RESERVED_280', - 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', - 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 284: 'SC_PS_ARB_STALLED_FROM_BELOW', - 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', - 286: 'SC_PS_ARB_SC_BUSY', - 287: 'SC_PS_ARB_PA_SC_BUSY', - 288: 'SC_PERF_SEL_RESERVED_288', - 289: 'SC_PERF_SEL_RESERVED_289', - 290: 'SC_PERF_SEL_RESERVED_290', - 291: 'SC_PERF_SEL_RESERVED_291', - 292: 'SC_PA_SC_DEALLOC_2_0_WE', - 293: 'SC_PERF_SEL_RESERVED_293', - 294: 'SC_PERF_SEL_RESERVED_294', - 295: 'SC_PERF_SEL_RESERVED_295', - 296: 'SC_PERF_SEL_RESERVED_296', - 297: 'SC_PERF_SEL_RESERVED_297', - 298: 'SC_PERF_SEL_RESERVED_298', - 299: 'SC_PERF_SEL_RESERVED_299', - 300: 'SC_PA0_SC_EOP_WE', - 301: 'SC_PERF_SEL_RESERVED_301', - 302: 'SC_PA0_SC_EVENT_WE', - 303: 'SC_PERF_SEL_RESERVED_303', - 304: 'SC_PERF_SEL_RESERVED_304', - 305: 'SC_PERF_SEL_RESERVED_305', - 306: 'SC_PERF_SEL_RESERVED_306', - 307: 'SC_PERF_SEL_RESERVED_307', - 308: 'SC_PERF_SEL_RESERVED_308', - 309: 'SC_PERF_SEL_RESERVED_309', - 310: 'SC_PERF_SEL_RESERVED_310', - 311: 'SC_PERF_SEL_RESERVED_311', - 312: 'SC_PERF_SEL_RESERVED_312', - 313: 'SC_PERF_SEL_RESERVED_313', - 314: 'SC_PERF_SEL_RESERVED_314', - 315: 'SC_PERF_SEL_RESERVED_315', - 316: 'SC_PERF_SEL_RESERVED_316', - 317: 'SC_PERF_SEL_RESERVED_317', - 318: 'SC_PA_SC_FPOV_WE', - 319: 'SC_PERF_SEL_RESERVED_319', - 320: 'SC_PERF_SEL_RESERVED_320', - 321: 'SC_PERF_SEL_RESERVED_321', - 322: 'SC_PERF_SEL_RESERVED_322', - 323: 'SC_PERF_SEL_RESERVED_323', - 324: 'SC_PERF_SEL_RESERVED_324', - 325: 'SC_PERF_SEL_RESERVED_325', - 326: 'SC_SPI_DEALLOC_4_0', - 327: 'SC_SPI_DEALLOC_7_5', - 328: 'SC_PERF_SEL_RESERVED_328', - 329: 'SC_PERF_SEL_RESERVED_329', - 330: 'SC_PERF_SEL_RESERVED_330', - 331: 'SC_PERF_SEL_RESERVED_331', - 332: 'SC_PERF_SEL_RESERVED_332', - 333: 'SC_PERF_SEL_RESERVED_333', - 334: 'SC_PERF_SEL_RESERVED_334', - 335: 'SC_PERF_SEL_RESERVED_335', - 336: 'SC_PERF_SEL_RESERVED_336', - 337: 'SC_PERF_SEL_RESERVED_337', - 338: 'SC_SPI_FPOV_4_0', - 339: 'SC_SPI_FPOV_7_5', - 340: 'SC_PERF_SEL_RESERVED_340', - 341: 'SC_PERF_SEL_RESERVED_341', - 342: 'SC_SPI_EVENT', - 343: 'SC_PS_TS_EVENT_FIFO_PUSH', - 344: 'SC_PS_TS_EVENT_FIFO_POP', - 345: 'SC_PS_CTX_DONE_FIFO_PUSH', - 346: 'SC_PS_CTX_DONE_FIFO_POP', - 347: 'SC_PERF_SEL_RESERVED_347', - 348: 'SC_PERF_SEL_RESERVED_348', - 349: 'SC_PA0_SC_NULL_WE', - 350: 'SC_PA0_SC_NULL_DEALLOC_WE', - 351: 'SC_PERF_SEL_RESERVED_351', - 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 353: 'SC_PA0_SC_DEALLOC_2_0_RD', - 354: 'SC_PERF_SEL_RESERVED_354', - 355: 'SC_PERF_SEL_RESERVED_355', - 356: 'SC_PERF_SEL_RESERVED_356', - 357: 'SC_PERF_SEL_RESERVED_357', - 358: 'SC_PERF_SEL_RESERVED_358', - 359: 'SC_PERF_SEL_RESERVED_359', - 360: 'SC_PERF_SEL_RESERVED_360', - 361: 'SC_PERF_SEL_RESERVED_361', - 362: 'SC_PERF_SEL_RESERVED_362', - 363: 'SC_PERF_SEL_RESERVED_363', - 364: 'SC_PERF_SEL_RESERVED_364', - 365: 'SC_PERF_SEL_RESERVED_365', - 366: 'SC_PERF_SEL_RESERVED_366', - 367: 'SC_PERF_SEL_RESERVED_367', - 368: 'SC_PERF_SEL_RESERVED_368', - 369: 'SC_PERF_SEL_RESERVED_369', - 370: 'SC_PERF_SEL_RESERVED_370', - 371: 'SC_PERF_SEL_RESERVED_371', - 372: 'SC_PERF_SEL_RESERVED_372', - 373: 'SC_PS_PA0_SC_FIFO_EMPTY', - 374: 'SC_PS_PA0_SC_FIFO_FULL', - 375: 'SC_PERF_SEL_RESERVED_375', - 376: 'SC_PERF_SEL_RESERVED_376', - 377: 'SC_PERF_SEL_RESERVED_377', - 378: 'SC_PERF_SEL_RESERVED_378', - 379: 'SC_PERF_SEL_RESERVED_379', - 380: 'SC_PERF_SEL_RESERVED_380', - 381: 'SC_PERF_SEL_RESERVED_381', - 382: 'SC_PERF_SEL_RESERVED_382', - 383: 'SC_PERF_SEL_RESERVED_383', - 384: 'SC_PERF_SEL_RESERVED_384', - 385: 'SC_PERF_SEL_RESERVED_385', - 386: 'SC_BUSY_CNT_NOT_ZERO', - 387: 'SC_BM_BUSY', - 388: 'SC_BACKEND_BUSY', - 389: 'SC_SCF_SCB_INTERFACE_BUSY', - 390: 'SC_SCB_BUSY', - 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', - 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 403: 'SC_PBB_BUSY', - 404: 'SC_PBB_BUSY_AND_NO_SENDS', - 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 406: 'SC_PBB_NUM_BINS', - 407: 'SC_PBB_END_OF_BIN', - 408: 'SC_PBB_END_OF_BATCH', - 409: 'SC_PBB_PRIMBIN_PROCESSED', - 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', - 411: 'SC_PBB_NONBINNED_PRIM', - 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', - 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 423: 'SC_PERF_SEL_RESERVED_423', - 424: 'SC_PERF_SEL_RESERVED_424', - 425: 'SC_PERF_SEL_RESERVED_425', - 426: 'SC_PERF_SEL_RESERVED_426', - 427: 'SC_PERF_SEL_RESERVED_427', - 428: 'SC_PERF_SEL_RESERVED_428', - 429: 'SC_PERF_SEL_RESERVED_429', - 430: 'SC_PERF_SEL_RESERVED_430', - 431: 'SC_PERF_SEL_RESERVED_431', - 432: 'SC_PERF_SEL_RESERVED_432', - 433: 'SC_PERF_SEL_RESERVED_433', - 434: 'SC_PERF_SEL_RESERVED_434', - 435: 'SC_PERF_SEL_RESERVED_435', - 436: 'SC_PERF_SEL_RESERVED_436', - 437: 'SC_GRP5_DYN_SCLK_BUSY', - 438: 'SC_GRP6_DYN_SCLK_BUSY', - 439: 'SC_GRP7_DYN_SCLK_BUSY', - 440: 'SC_GRP8_DYN_SCLK_BUSY', - 441: 'SC_GRP9_DYN_SCLK_BUSY', - 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', - 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 444: 'SC_PK_BUSY', - 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 446: 'SC_PK_DEALLOC_WAVE_BREAK', - 447: 'SC_SPI_SEND', - 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 449: 'SC_SPI_CREDIT_AT_MAX', - 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 451: 'SC_BCI_SEND', - 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 453: 'SC_BCI_CREDIT_AT_MAX', - 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 455: 'SC_SPIBC_FULL_FREEZE', - 456: 'SC_PW_BM_PASS_EMPTY_PRIM', - 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 475: 'SC_DB0_TILE_INTERFACE_BUSY', - 476: 'SC_DB0_TILE_INTERFACE_SEND', - 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 478: 'SC_PERF_SEL_RESERVED_478', - 479: 'SC_PERF_SEL_RESERVED_479', - 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 483: 'SC_PERF_SEL_RESERVED_483', - 484: 'SC_PERF_SEL_RESERVED_484', - 485: 'SC_PERF_SEL_RESERVED_485', - 486: 'SC_PERF_SEL_RESERVED_486', - 487: 'SC_PERF_SEL_RESERVED_487', - 488: 'SC_PERF_SEL_RESERVED_488', - 489: 'SC_PERF_SEL_RESERVED_489', - 490: 'SC_PERF_SEL_RESERVED_490', - 491: 'SC_BACKEND_PRIM_FIFO_FULL', - 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 503: 'SC_STALLED_BY_DB0_TILEFIFO', - 504: 'SC_DB0_QUAD_INTF_SEND', - 505: 'SC_DB0_QUAD_INTF_BUSY', - 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', - 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', - 508: 'SC_DB0_QUAD_INTF_IDLE', - 509: 'SC_PERF_SEL_RESERVED_509', - 510: 'SC_PERF_SEL_RESERVED_510', - 511: 'SC_PERF_SEL_RESERVED_511', - 512: 'SC_PERF_SEL_RESERVED_512', - 513: 'SC_PERF_SEL_RESERVED_513', - 514: 'SC_PERF_SEL_RESERVED_514', - 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', - 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', - 517: 'SC_RESERVED_60', - 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', - 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 522: 'SC_DB0_TILE_MASK_FIFO_FULL', - 523: 'SC_PERF_SEL_RESERVED_523', - 524: 'SC_PERF_SEL_RESERVED_524', - 525: 'SC_PERF_SEL_RESERVED_525', - 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 529: 'SC_PS_PM_PFF_PW_FULL', - 530: 'SC_PS_PM_ZFF_PW_FULL', - 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 532: 'SC_PERF_SEL_RESERVED_532', - 533: 'SC_PERF_SEL_RESERVED_533', - 534: 'SC_PERF_SEL_RESERVED_534', - 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 539: 'SC_PERF_SEL_RESERVED_539', - 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 547: 'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H', - 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 568: 'SC_PERF_SEL_RESERVED_568', - 569: 'SC_PBB_RESERVED', - 570: 'SC_BM_BE0_STALLED', - 571: 'SC_BM_BE1_STALLED', - 572: 'SC_BM_BE2_STALLED', - 573: 'SC_BM_BE3_STALLED', - 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', - 578: 'SC_PBB_READ_PH0', - 579: 'SC_PBB_READ_DEALLOC_4_0', - 580: 'SC_PBB_READ_DEALLOC_7_5', - 581: 'SC_PBB_READ_FPOG_4_0', - 582: 'SC_PBB_READ_FPOG_7_5', - 583: 'SC_VRC_SECTOR_HIT', - 584: 'SC_VRC_TAG_MISS', - 585: 'SC_VRC_SECTOR_MISS', - 586: 'SC_VRC_LRU_EVICT_STALL', - 587: 'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL', - 588: 'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL', - 589: 'SC_VRC_REEVICTION_STALL', - 590: 'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL', - 591: 'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL', - 592: 'SC_VRC_REPLACE_PENDING_EVICT_STALL', - 593: 'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL', - 594: 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL', - 595: 'SC_VRC_READ_OUTPUT_STALL', - 596: 'SC_VRC_WRITE_OUTPUT_STALL', - 597: 'SC_VRC_ACK_OUTPUT_STALL', - 598: 'SC_VRC_FLUSH_EVICT_STALL', - 599: 'SC_VRC_FLUSH_REFLUSH_STALL', - 600: 'SC_VRC_FLUSH_FIP_HIT_STALL', - 601: 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL', - 602: 'SC_VRC_FLUSH_DONE_STALL', - 603: 'SC_VRC_FLUSH_STALL', - 604: 'SC_VRC_STALL', - 605: 'SC_VRC_FLUSH', - 606: 'SC_VRC_SECTORS_FLUSHED', - 607: 'SC_VRC_DIRTY_SECTORS_FLUSHED', - 608: 'SC_VRC_TAGS_FLUSHED', - 609: 'SC_VRC_HPF_REQ', - 610: 'SC_VRC_HPF_EVENT', - 611: 'SC_VRC_HPF_STALLED', - 612: 'SC_VRC_PROBE_ACK_TILES', - 613: 'SC_VRC_GL1X_RD_REQ', - 614: 'SC_VRC_GL1X_WR_REQ', - 615: 'SC_VRC_GL1X_SRC_XFR', - 616: 'SC_VRC_GL1X_RD_RET', - 617: 'SC_VRC_GL1X_WR_ACK', - 618: 'SC_VRC_GL1X_RD_XNACK', - 619: 'SC_VRC_GL1X_WR_XNACK', - 620: 'SC_VRC_GL1X_REQ_STALLED', - 621: 'SC_VRC_GL1X_SRC_STALLED', - 622: 'SC_VRC_RATEMEM_WE_CNT', - 623: 'SC_VRC_RATEMEM_RE_CNT', - 624: 'SC_VRC_HINTMEM_WE_CNT', - 625: 'SC_VRC_HINTMEM_RE_CNT', - 626: 'SC_VRC_BUSY', - 627: 'SC_GL1X_BUSY', - 628: 'SC_BE_VRS_RD_REQ', - 629: 'SC_BE_VRS_RD_REQ_STALLED', - 630: 'SC_BE_VRS_RD_REQ_HIT', - 631: 'SC_BE_VRS_RD_RET', - 632: 'SC_BE_VRS_RD_RET_STALLED', - 633: 'SC_BE_VRS_FB_RET', - 634: 'SC_BE_VRS_FB_RET_STALLED', - 635: 'SC_BE_VRS_FB_RET_HIT', - 636: 'SC_VRS_BE_BUSY', - 637: 'SC_PWS_CS_EVENTS_PWS_ENABLE', - 638: 'SC_PWS_PS_EVENTS_PWS_ENABLE', - 639: 'SC_PWS_TS_EVENTS_PWS_ENABLE', - 640: 'SC_PWS_STALLED', - 641: 'SC_PWS_P0_CS_SYNC_COMPLETE', - 642: 'SC_PWS_P0_PS_SYNC_COMPLETE', - 643: 'SC_PWS_P0_TS_SYNC_COMPLETE', - 644: 'SC_PWS_P1_CS_SYNC_COMPLETE', - 645: 'SC_PWS_P1_PS_SYNC_COMPLETE', - 646: 'SC_PWS_P1_TS_SYNC_COMPLETE', - 647: 'SC_PKR_PC_NO_CREDITS', - 648: 'SC_PKR_PC_STALLED', - 649: 'SC_PKR_PC_SEND', - 650: 'SC_PKR_PC_SEND_PRIM_VALID_1', - 651: 'SC_PKR_PC_SEND_PRIM_VALID_0', - 652: 'SC_PKR_PC_SEND_TRUE_PRIM', - 653: 'SC_PKR_PC_SEND_EOV', - 654: 'SC_PKR_PC_SEND_EVENT', - 655: 'SC_PKR_DB_WAVE_STALL', - 656: 'SC_PKR_PSINVOC_SEDC_FIFO_FULL', - 657: 'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID', - 658: 'SC_PKR_SPI_QUAD_COUNT', - 659: 'SC_PKR_DB_OREO_WAVE_QUAD_COUNT', - 660: 'SC_PKR_BCI_QUAD_NEW_PRIM', - 661: 'SC_SPI_WAVE_STALLED_BY_SPI', -} -SC_SRPS_WINDOW_VALID = 0 -SC_PSSW_WINDOW_VALID = 1 -SC_TPQZ_WINDOW_VALID = 2 -SC_QZQP_WINDOW_VALID = 3 -SC_TRPK_WINDOW_VALID = 4 -SC_SRPS_WINDOW_VALID_BUSY = 5 -SC_PSSW_WINDOW_VALID_BUSY = 6 -SC_TPQZ_WINDOW_VALID_BUSY = 7 -SC_QZQP_WINDOW_VALID_BUSY = 8 -SC_TRPK_WINDOW_VALID_BUSY = 9 -SC_STARVED_BY_PA = 10 -SC_STALLED_BY_PRIMFIFO = 11 -SC_STALLED_BY_DB_TILE = 12 -SC_STARVED_BY_DB_TILE = 13 -SC_STALLED_BY_TILEORDERFIFO = 14 -SC_STALLED_BY_TILEFIFO = 15 -SC_STALLED_BY_DB_QUAD = 16 -SC_STARVED_BY_DB_QUAD = 17 -SC_STALLED_BY_QUADFIFO = 18 -SC_STALLED_BY_BCI = 19 -SC_STALLED_BY_SPI = 20 -SC_SCISSOR_DISCARD = 21 -SC_BB_DISCARD = 22 -SC_SUPERTILE_COUNT = 23 -SC_SUPERTILE_PER_PRIM_H0 = 24 -SC_SUPERTILE_PER_PRIM_H1 = 25 -SC_SUPERTILE_PER_PRIM_H2 = 26 -SC_SUPERTILE_PER_PRIM_H3 = 27 -SC_SUPERTILE_PER_PRIM_H4 = 28 -SC_SUPERTILE_PER_PRIM_H5 = 29 -SC_SUPERTILE_PER_PRIM_H6 = 30 -SC_SUPERTILE_PER_PRIM_H7 = 31 -SC_SUPERTILE_PER_PRIM_H8 = 32 -SC_SUPERTILE_PER_PRIM_H9 = 33 -SC_SUPERTILE_PER_PRIM_H10 = 34 -SC_SUPERTILE_PER_PRIM_H11 = 35 -SC_SUPERTILE_PER_PRIM_H12 = 36 -SC_SUPERTILE_PER_PRIM_H13 = 37 -SC_SUPERTILE_PER_PRIM_H14 = 38 -SC_SUPERTILE_PER_PRIM_H15 = 39 -SC_SUPERTILE_PER_PRIM_H16 = 40 -SC_TILE_PER_PRIM_H0 = 41 -SC_TILE_PER_PRIM_H1 = 42 -SC_TILE_PER_PRIM_H2 = 43 -SC_TILE_PER_PRIM_H3 = 44 -SC_TILE_PER_PRIM_H4 = 45 -SC_TILE_PER_PRIM_H5 = 46 -SC_TILE_PER_PRIM_H6 = 47 -SC_TILE_PER_PRIM_H7 = 48 -SC_TILE_PER_PRIM_H8 = 49 -SC_TILE_PER_PRIM_H9 = 50 -SC_TILE_PER_PRIM_H10 = 51 -SC_TILE_PER_PRIM_H11 = 52 -SC_TILE_PER_PRIM_H12 = 53 -SC_TILE_PER_PRIM_H13 = 54 -SC_TILE_PER_PRIM_H14 = 55 -SC_TILE_PER_PRIM_H15 = 56 -SC_TILE_PER_PRIM_H16 = 57 -SC_TILE_PER_SUPERTILE_H0 = 58 -SC_TILE_PER_SUPERTILE_H1 = 59 -SC_TILE_PER_SUPERTILE_H2 = 60 -SC_TILE_PER_SUPERTILE_H3 = 61 -SC_TILE_PER_SUPERTILE_H4 = 62 -SC_TILE_PER_SUPERTILE_H5 = 63 -SC_TILE_PER_SUPERTILE_H6 = 64 -SC_TILE_PER_SUPERTILE_H7 = 65 -SC_TILE_PER_SUPERTILE_H8 = 66 -SC_TILE_PER_SUPERTILE_H9 = 67 -SC_TILE_PER_SUPERTILE_H10 = 68 -SC_TILE_PER_SUPERTILE_H11 = 69 -SC_TILE_PER_SUPERTILE_H12 = 70 -SC_TILE_PER_SUPERTILE_H13 = 71 -SC_TILE_PER_SUPERTILE_H14 = 72 -SC_TILE_PER_SUPERTILE_H15 = 73 -SC_TILE_PER_SUPERTILE_H16 = 74 -SC_TILE_PICKED_H1 = 75 -SC_PERF_SEL_RESERVED_76 = 76 -SC_PERF_SEL_RESERVED_77 = 77 -SC_PERF_SEL_RESERVED_78 = 78 -SC_QZ0_TILE_COUNT = 79 -SC_PERF_SEL_RESERVED_80 = 80 -SC_PERF_SEL_RESERVED_81 = 81 -SC_PERF_SEL_RESERVED_82 = 82 -SC_QZ0_TILE_COVERED_COUNT = 83 -SC_PERF_SEL_RESERVED_84 = 84 -SC_PERF_SEL_RESERVED_85 = 85 -SC_PERF_SEL_RESERVED_86 = 86 -SC_QZ0_TILE_NOT_COVERED_COUNT = 87 -SC_PERF_SEL_RESERVED_88 = 88 -SC_PERF_SEL_RESERVED_89 = 89 -SC_PERF_SEL_RESERVED_90 = 90 -SC_QZ0_QUAD_PER_TILE_H0 = 91 -SC_QZ0_QUAD_PER_TILE_H1 = 92 -SC_QZ0_QUAD_PER_TILE_H2 = 93 -SC_QZ0_QUAD_PER_TILE_H3 = 94 -SC_QZ0_QUAD_PER_TILE_H4 = 95 -SC_QZ0_QUAD_PER_TILE_H5 = 96 -SC_QZ0_QUAD_PER_TILE_H6 = 97 -SC_QZ0_QUAD_PER_TILE_H7 = 98 -SC_QZ0_QUAD_PER_TILE_H8 = 99 -SC_QZ0_QUAD_PER_TILE_H9 = 100 -SC_QZ0_QUAD_PER_TILE_H10 = 101 -SC_QZ0_QUAD_PER_TILE_H11 = 102 -SC_QZ0_QUAD_PER_TILE_H12 = 103 -SC_QZ0_QUAD_PER_TILE_H13 = 104 -SC_QZ0_QUAD_PER_TILE_H14 = 105 -SC_QZ0_QUAD_PER_TILE_H15 = 106 -SC_QZ0_QUAD_PER_TILE_H16 = 107 -SC_PERF_SEL_RESERVED_108 = 108 -SC_PERF_SEL_RESERVED_109 = 109 -SC_PERF_SEL_RESERVED_110 = 110 -SC_PERF_SEL_RESERVED_111 = 111 -SC_PERF_SEL_RESERVED_112 = 112 -SC_PERF_SEL_RESERVED_113 = 113 -SC_PERF_SEL_RESERVED_114 = 114 -SC_PERF_SEL_RESERVED_115 = 115 -SC_PERF_SEL_RESERVED_116 = 116 -SC_PERF_SEL_RESERVED_117 = 117 -SC_PERF_SEL_RESERVED_118 = 118 -SC_PERF_SEL_RESERVED_119 = 119 -SC_PERF_SEL_RESERVED_120 = 120 -SC_PERF_SEL_RESERVED_121 = 121 -SC_PERF_SEL_RESERVED_122 = 122 -SC_PERF_SEL_RESERVED_123 = 123 -SC_PERF_SEL_RESERVED_124 = 124 -SC_PERF_SEL_RESERVED_125 = 125 -SC_PERF_SEL_RESERVED_126 = 126 -SC_PERF_SEL_RESERVED_127 = 127 -SC_PERF_SEL_RESERVED_128 = 128 -SC_PERF_SEL_RESERVED_129 = 129 -SC_PERF_SEL_RESERVED_130 = 130 -SC_PERF_SEL_RESERVED_131 = 131 -SC_PERF_SEL_RESERVED_132 = 132 -SC_PERF_SEL_RESERVED_133 = 133 -SC_PERF_SEL_RESERVED_134 = 134 -SC_PERF_SEL_RESERVED_135 = 135 -SC_PERF_SEL_RESERVED_136 = 136 -SC_PERF_SEL_RESERVED_137 = 137 -SC_PERF_SEL_RESERVED_138 = 138 -SC_PERF_SEL_RESERVED_139 = 139 -SC_PERF_SEL_RESERVED_140 = 140 -SC_PERF_SEL_RESERVED_141 = 141 -SC_PERF_SEL_RESERVED_142 = 142 -SC_PERF_SEL_RESERVED_143 = 143 -SC_PERF_SEL_RESERVED_144 = 144 -SC_PERF_SEL_RESERVED_145 = 145 -SC_PERF_SEL_RESERVED_146 = 146 -SC_PERF_SEL_RESERVED_147 = 147 -SC_PERF_SEL_RESERVED_148 = 148 -SC_PERF_SEL_RESERVED_149 = 149 -SC_PERF_SEL_RESERVED_150 = 150 -SC_PERF_SEL_RESERVED_151 = 151 -SC_PERF_SEL_RESERVED_152 = 152 -SC_PERF_SEL_RESERVED_153 = 153 -SC_PERF_SEL_RESERVED_154 = 154 -SC_PERF_SEL_RESERVED_155 = 155 -SC_PERF_SEL_RESERVED_156 = 156 -SC_PERF_SEL_RESERVED_157 = 157 -SC_PERF_SEL_RESERVED_158 = 158 -SC_QZ0_QUAD_COUNT = 159 -SC_PERF_SEL_RESERVED_160 = 160 -SC_PERF_SEL_RESERVED_161 = 161 -SC_PERF_SEL_RESERVED_162 = 162 -SC_P0_HIZ_TILE_COUNT = 163 -SC_PERF_SEL_RESERVED_164 = 164 -SC_PERF_SEL_RESERVED_165 = 165 -SC_PERF_SEL_RESERVED_166 = 166 -SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 -SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 -SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 -SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 -SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 -SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 -SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 -SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 -SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 -SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 -SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 -SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 -SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 -SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 -SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 -SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 -SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 -SC_PERF_SEL_RESERVED_184 = 184 -SC_PERF_SEL_RESERVED_185 = 185 -SC_PERF_SEL_RESERVED_186 = 186 -SC_PERF_SEL_RESERVED_187 = 187 -SC_PERF_SEL_RESERVED_188 = 188 -SC_PERF_SEL_RESERVED_189 = 189 -SC_PERF_SEL_RESERVED_190 = 190 -SC_PERF_SEL_RESERVED_191 = 191 -SC_PERF_SEL_RESERVED_192 = 192 -SC_PERF_SEL_RESERVED_193 = 193 -SC_PERF_SEL_RESERVED_194 = 194 -SC_PERF_SEL_RESERVED_195 = 195 -SC_PERF_SEL_RESERVED_196 = 196 -SC_PERF_SEL_RESERVED_197 = 197 -SC_PERF_SEL_RESERVED_198 = 198 -SC_PERF_SEL_RESERVED_199 = 199 -SC_PERF_SEL_RESERVED_200 = 200 -SC_PERF_SEL_RESERVED_201 = 201 -SC_PERF_SEL_RESERVED_202 = 202 -SC_PERF_SEL_RESERVED_203 = 203 -SC_PERF_SEL_RESERVED_204 = 204 -SC_PERF_SEL_RESERVED_205 = 205 -SC_PERF_SEL_RESERVED_206 = 206 -SC_PERF_SEL_RESERVED_207 = 207 -SC_PERF_SEL_RESERVED_208 = 208 -SC_PERF_SEL_RESERVED_209 = 209 -SC_PERF_SEL_RESERVED_210 = 210 -SC_PERF_SEL_RESERVED_211 = 211 -SC_PERF_SEL_RESERVED_212 = 212 -SC_PERF_SEL_RESERVED_213 = 213 -SC_PERF_SEL_RESERVED_214 = 214 -SC_PERF_SEL_RESERVED_215 = 215 -SC_PERF_SEL_RESERVED_216 = 216 -SC_PERF_SEL_RESERVED_217 = 217 -SC_PERF_SEL_RESERVED_218 = 218 -SC_PERF_SEL_RESERVED_219 = 219 -SC_PERF_SEL_RESERVED_220 = 220 -SC_PERF_SEL_RESERVED_221 = 221 -SC_PERF_SEL_RESERVED_222 = 222 -SC_PERF_SEL_RESERVED_223 = 223 -SC_PERF_SEL_RESERVED_224 = 224 -SC_PERF_SEL_RESERVED_225 = 225 -SC_PERF_SEL_RESERVED_226 = 226 -SC_PERF_SEL_RESERVED_227 = 227 -SC_PERF_SEL_RESERVED_228 = 228 -SC_PERF_SEL_RESERVED_229 = 229 -SC_PERF_SEL_RESERVED_230 = 230 -SC_PERF_SEL_RESERVED_231 = 231 -SC_PERF_SEL_RESERVED_232 = 232 -SC_PERF_SEL_RESERVED_233 = 233 -SC_PERF_SEL_RESERVED_234 = 234 -SC_P0_HIZ_QUAD_COUNT = 235 -SC_PERF_SEL_RESERVED_236 = 236 -SC_PERF_SEL_RESERVED_237 = 237 -SC_PERF_SEL_RESERVED_238 = 238 -SC_P0_DETAIL_QUAD_COUNT = 239 -SC_PERF_SEL_RESERVED_240 = 240 -SC_PERF_SEL_RESERVED_241 = 241 -SC_PERF_SEL_RESERVED_242 = 242 -SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 -SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 -SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 -SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 -SC_PERF_SEL_RESERVED_247 = 247 -SC_PERF_SEL_RESERVED_248 = 248 -SC_PERF_SEL_RESERVED_249 = 249 -SC_PERF_SEL_RESERVED_250 = 250 -SC_PERF_SEL_RESERVED_251 = 251 -SC_PERF_SEL_RESERVED_252 = 252 -SC_PERF_SEL_RESERVED_253 = 253 -SC_PERF_SEL_RESERVED_254 = 254 -SC_PERF_SEL_RESERVED_255 = 255 -SC_PERF_SEL_RESERVED_256 = 256 -SC_PERF_SEL_RESERVED_257 = 257 -SC_PERF_SEL_RESERVED_258 = 258 -SC_EARLYZ_QUAD_COUNT = 259 -SC_EARLYZ_QUAD_WITH_1_PIX = 260 -SC_EARLYZ_QUAD_WITH_2_PIX = 261 -SC_EARLYZ_QUAD_WITH_3_PIX = 262 -SC_EARLYZ_QUAD_WITH_4_PIX = 263 -SC_PKR_QUAD_PER_ROW_H1 = 264 -SC_PKR_QUAD_PER_ROW_H2 = 265 -SC_PKR_4X2_QUAD_SPLIT = 266 -SC_PKR_4X2_FILL_QUAD = 267 -SC_PKR_END_OF_VECTOR = 268 -SC_PKR_CONTROL_XFER = 269 -SC_PKR_DBHANG_FORCE_EOV = 270 -SC_REG_SCLK_BUSY = 271 -SC_GRP0_DYN_SCLK_BUSY = 272 -SC_GRP1_DYN_SCLK_BUSY = 273 -SC_GRP2_DYN_SCLK_BUSY = 274 -SC_GRP3_DYN_SCLK_BUSY = 275 -SC_GRP4_DYN_SCLK_BUSY = 276 -SC_PA0_SC_DATA_FIFO_RD = 277 -SC_PA0_SC_DATA_FIFO_WE = 278 -SC_PERF_SEL_RESERVED_279 = 279 -SC_PERF_SEL_RESERVED_280 = 280 -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 -SC_PS_ARB_STALLED_FROM_BELOW = 284 -SC_PS_ARB_STARVED_FROM_ABOVE = 285 -SC_PS_ARB_SC_BUSY = 286 -SC_PS_ARB_PA_SC_BUSY = 287 -SC_PERF_SEL_RESERVED_288 = 288 -SC_PERF_SEL_RESERVED_289 = 289 -SC_PERF_SEL_RESERVED_290 = 290 -SC_PERF_SEL_RESERVED_291 = 291 -SC_PA_SC_DEALLOC_2_0_WE = 292 -SC_PERF_SEL_RESERVED_293 = 293 -SC_PERF_SEL_RESERVED_294 = 294 -SC_PERF_SEL_RESERVED_295 = 295 -SC_PERF_SEL_RESERVED_296 = 296 -SC_PERF_SEL_RESERVED_297 = 297 -SC_PERF_SEL_RESERVED_298 = 298 -SC_PERF_SEL_RESERVED_299 = 299 -SC_PA0_SC_EOP_WE = 300 -SC_PERF_SEL_RESERVED_301 = 301 -SC_PA0_SC_EVENT_WE = 302 -SC_PERF_SEL_RESERVED_303 = 303 -SC_PERF_SEL_RESERVED_304 = 304 -SC_PERF_SEL_RESERVED_305 = 305 -SC_PERF_SEL_RESERVED_306 = 306 -SC_PERF_SEL_RESERVED_307 = 307 -SC_PERF_SEL_RESERVED_308 = 308 -SC_PERF_SEL_RESERVED_309 = 309 -SC_PERF_SEL_RESERVED_310 = 310 -SC_PERF_SEL_RESERVED_311 = 311 -SC_PERF_SEL_RESERVED_312 = 312 -SC_PERF_SEL_RESERVED_313 = 313 -SC_PERF_SEL_RESERVED_314 = 314 -SC_PERF_SEL_RESERVED_315 = 315 -SC_PERF_SEL_RESERVED_316 = 316 -SC_PERF_SEL_RESERVED_317 = 317 -SC_PA_SC_FPOV_WE = 318 -SC_PERF_SEL_RESERVED_319 = 319 -SC_PERF_SEL_RESERVED_320 = 320 -SC_PERF_SEL_RESERVED_321 = 321 -SC_PERF_SEL_RESERVED_322 = 322 -SC_PERF_SEL_RESERVED_323 = 323 -SC_PERF_SEL_RESERVED_324 = 324 -SC_PERF_SEL_RESERVED_325 = 325 -SC_SPI_DEALLOC_4_0 = 326 -SC_SPI_DEALLOC_7_5 = 327 -SC_PERF_SEL_RESERVED_328 = 328 -SC_PERF_SEL_RESERVED_329 = 329 -SC_PERF_SEL_RESERVED_330 = 330 -SC_PERF_SEL_RESERVED_331 = 331 -SC_PERF_SEL_RESERVED_332 = 332 -SC_PERF_SEL_RESERVED_333 = 333 -SC_PERF_SEL_RESERVED_334 = 334 -SC_PERF_SEL_RESERVED_335 = 335 -SC_PERF_SEL_RESERVED_336 = 336 -SC_PERF_SEL_RESERVED_337 = 337 -SC_SPI_FPOV_4_0 = 338 -SC_SPI_FPOV_7_5 = 339 -SC_PERF_SEL_RESERVED_340 = 340 -SC_PERF_SEL_RESERVED_341 = 341 -SC_SPI_EVENT = 342 -SC_PS_TS_EVENT_FIFO_PUSH = 343 -SC_PS_TS_EVENT_FIFO_POP = 344 -SC_PS_CTX_DONE_FIFO_PUSH = 345 -SC_PS_CTX_DONE_FIFO_POP = 346 -SC_PERF_SEL_RESERVED_347 = 347 -SC_PERF_SEL_RESERVED_348 = 348 -SC_PA0_SC_NULL_WE = 349 -SC_PA0_SC_NULL_DEALLOC_WE = 350 -SC_PERF_SEL_RESERVED_351 = 351 -SC_PA0_SC_DATA_FIFO_EOP_RD = 352 -SC_PA0_SC_DEALLOC_2_0_RD = 353 -SC_PERF_SEL_RESERVED_354 = 354 -SC_PERF_SEL_RESERVED_355 = 355 -SC_PERF_SEL_RESERVED_356 = 356 -SC_PERF_SEL_RESERVED_357 = 357 -SC_PERF_SEL_RESERVED_358 = 358 -SC_PERF_SEL_RESERVED_359 = 359 -SC_PERF_SEL_RESERVED_360 = 360 -SC_PERF_SEL_RESERVED_361 = 361 -SC_PERF_SEL_RESERVED_362 = 362 -SC_PERF_SEL_RESERVED_363 = 363 -SC_PERF_SEL_RESERVED_364 = 364 -SC_PERF_SEL_RESERVED_365 = 365 -SC_PERF_SEL_RESERVED_366 = 366 -SC_PERF_SEL_RESERVED_367 = 367 -SC_PERF_SEL_RESERVED_368 = 368 -SC_PERF_SEL_RESERVED_369 = 369 -SC_PERF_SEL_RESERVED_370 = 370 -SC_PERF_SEL_RESERVED_371 = 371 -SC_PERF_SEL_RESERVED_372 = 372 -SC_PS_PA0_SC_FIFO_EMPTY = 373 -SC_PS_PA0_SC_FIFO_FULL = 374 -SC_PERF_SEL_RESERVED_375 = 375 -SC_PERF_SEL_RESERVED_376 = 376 -SC_PERF_SEL_RESERVED_377 = 377 -SC_PERF_SEL_RESERVED_378 = 378 -SC_PERF_SEL_RESERVED_379 = 379 -SC_PERF_SEL_RESERVED_380 = 380 -SC_PERF_SEL_RESERVED_381 = 381 -SC_PERF_SEL_RESERVED_382 = 382 -SC_PERF_SEL_RESERVED_383 = 383 -SC_PERF_SEL_RESERVED_384 = 384 -SC_PERF_SEL_RESERVED_385 = 385 -SC_BUSY_CNT_NOT_ZERO = 386 -SC_BM_BUSY = 387 -SC_BACKEND_BUSY = 388 -SC_SCF_SCB_INTERFACE_BUSY = 389 -SC_SCB_BUSY = 390 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 -SC_PBB_BIN_HIST_NUM_PRIMS = 393 -SC_PBB_BATCH_HIST_NUM_PRIMS = 394 -SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 -SC_PBB_BUSY = 403 -SC_PBB_BUSY_AND_NO_SENDS = 404 -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 -SC_PBB_NUM_BINS = 406 -SC_PBB_END_OF_BIN = 407 -SC_PBB_END_OF_BATCH = 408 -SC_PBB_PRIMBIN_PROCESSED = 409 -SC_PBB_PRIM_ADDED_TO_BATCH = 410 -SC_PBB_NONBINNED_PRIM = 411 -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 -SC_PERF_SEL_RESERVED_423 = 423 -SC_PERF_SEL_RESERVED_424 = 424 -SC_PERF_SEL_RESERVED_425 = 425 -SC_PERF_SEL_RESERVED_426 = 426 -SC_PERF_SEL_RESERVED_427 = 427 -SC_PERF_SEL_RESERVED_428 = 428 -SC_PERF_SEL_RESERVED_429 = 429 -SC_PERF_SEL_RESERVED_430 = 430 -SC_PERF_SEL_RESERVED_431 = 431 -SC_PERF_SEL_RESERVED_432 = 432 -SC_PERF_SEL_RESERVED_433 = 433 -SC_PERF_SEL_RESERVED_434 = 434 -SC_PERF_SEL_RESERVED_435 = 435 -SC_PERF_SEL_RESERVED_436 = 436 -SC_GRP5_DYN_SCLK_BUSY = 437 -SC_GRP6_DYN_SCLK_BUSY = 438 -SC_GRP7_DYN_SCLK_BUSY = 439 -SC_GRP8_DYN_SCLK_BUSY = 440 -SC_GRP9_DYN_SCLK_BUSY = 441 -SC_PS_TO_BE_SCLK_GATE_STALL = 442 -SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 -SC_PK_BUSY = 444 -SC_PK_MAX_DEALLOC_FORCE_EOV = 445 -SC_PK_DEALLOC_WAVE_BREAK = 446 -SC_SPI_SEND = 447 -SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 -SC_SPI_CREDIT_AT_MAX = 449 -SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 -SC_BCI_SEND = 451 -SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 -SC_BCI_CREDIT_AT_MAX = 453 -SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 -SC_SPIBC_FULL_FREEZE = 455 -SC_PW_BM_PASS_EMPTY_PRIM = 456 -SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 -SC_DB0_TILE_INTERFACE_BUSY = 475 -SC_DB0_TILE_INTERFACE_SEND = 476 -SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 -SC_PERF_SEL_RESERVED_478 = 478 -SC_PERF_SEL_RESERVED_479 = 479 -SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 -SC_PERF_SEL_RESERVED_483 = 483 -SC_PERF_SEL_RESERVED_484 = 484 -SC_PERF_SEL_RESERVED_485 = 485 -SC_PERF_SEL_RESERVED_486 = 486 -SC_PERF_SEL_RESERVED_487 = 487 -SC_PERF_SEL_RESERVED_488 = 488 -SC_PERF_SEL_RESERVED_489 = 489 -SC_PERF_SEL_RESERVED_490 = 490 -SC_BACKEND_PRIM_FIFO_FULL = 491 -SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 -SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 -SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 -SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 -SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 -SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 -SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 -SC_STALLED_BY_DB0_TILEFIFO = 503 -SC_DB0_QUAD_INTF_SEND = 504 -SC_DB0_QUAD_INTF_BUSY = 505 -SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 -SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 -SC_DB0_QUAD_INTF_IDLE = 508 -SC_PERF_SEL_RESERVED_509 = 509 -SC_PERF_SEL_RESERVED_510 = 510 -SC_PERF_SEL_RESERVED_511 = 511 -SC_PERF_SEL_RESERVED_512 = 512 -SC_PERF_SEL_RESERVED_513 = 513 -SC_PERF_SEL_RESERVED_514 = 514 -SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 -SC_PKR_WAVE_BREAK_FULL_TILE = 516 -SC_RESERVED_60 = 517 -SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 -SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 -SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 -SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 -SC_DB0_TILE_MASK_FIFO_FULL = 522 -SC_PERF_SEL_RESERVED_523 = 523 -SC_PERF_SEL_RESERVED_524 = 524 -SC_PERF_SEL_RESERVED_525 = 525 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 -SC_PS_PM_PFF_PW_FULL = 529 -SC_PS_PM_ZFF_PW_FULL = 530 -SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 -SC_PERF_SEL_RESERVED_532 = 532 -SC_PERF_SEL_RESERVED_533 = 533 -SC_PERF_SEL_RESERVED_534 = 534 -SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 -SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 -SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 -SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 -SC_PERF_SEL_RESERVED_539 = 539 -SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 -SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 -SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 -SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 -SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 -SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 -SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 -SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H = 547 -SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 -SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 -SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 -SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 -SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 -SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 -SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 -SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 -SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 -SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 -SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 -SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 -SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 -SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 -SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 -SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 -SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 -SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 -SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 -SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 -SC_PERF_SEL_RESERVED_568 = 568 -SC_PBB_RESERVED = 569 -SC_BM_BE0_STALLED = 570 -SC_BM_BE1_STALLED = 571 -SC_BM_BE2_STALLED = 572 -SC_BM_BE3_STALLED = 573 -SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 -SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 -SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 -SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 -SC_PBB_READ_PH0 = 578 -SC_PBB_READ_DEALLOC_4_0 = 579 -SC_PBB_READ_DEALLOC_7_5 = 580 -SC_PBB_READ_FPOG_4_0 = 581 -SC_PBB_READ_FPOG_7_5 = 582 -SC_VRC_SECTOR_HIT = 583 -SC_VRC_TAG_MISS = 584 -SC_VRC_SECTOR_MISS = 585 -SC_VRC_LRU_EVICT_STALL = 586 -SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL = 587 -SC_VRC_LRU_EVICT_PENDING_EVICT_STALL = 588 -SC_VRC_REEVICTION_STALL = 589 -SC_VRC_EVICT_NONZERO_INFLIGHT_STALL = 590 -SC_VRC_REPLACE_SCHEDULED_EVICT_STALL = 591 -SC_VRC_REPLACE_PENDING_EVICT_STALL = 592 -SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL = 593 -SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL = 594 -SC_VRC_READ_OUTPUT_STALL = 595 -SC_VRC_WRITE_OUTPUT_STALL = 596 -SC_VRC_ACK_OUTPUT_STALL = 597 -SC_VRC_FLUSH_EVICT_STALL = 598 -SC_VRC_FLUSH_REFLUSH_STALL = 599 -SC_VRC_FLUSH_FIP_HIT_STALL = 600 -SC_VRC_FLUSH_WRREQ_DRAIN_STALL = 601 -SC_VRC_FLUSH_DONE_STALL = 602 -SC_VRC_FLUSH_STALL = 603 -SC_VRC_STALL = 604 -SC_VRC_FLUSH = 605 -SC_VRC_SECTORS_FLUSHED = 606 -SC_VRC_DIRTY_SECTORS_FLUSHED = 607 -SC_VRC_TAGS_FLUSHED = 608 -SC_VRC_HPF_REQ = 609 -SC_VRC_HPF_EVENT = 610 -SC_VRC_HPF_STALLED = 611 -SC_VRC_PROBE_ACK_TILES = 612 -SC_VRC_GL1X_RD_REQ = 613 -SC_VRC_GL1X_WR_REQ = 614 -SC_VRC_GL1X_SRC_XFR = 615 -SC_VRC_GL1X_RD_RET = 616 -SC_VRC_GL1X_WR_ACK = 617 -SC_VRC_GL1X_RD_XNACK = 618 -SC_VRC_GL1X_WR_XNACK = 619 -SC_VRC_GL1X_REQ_STALLED = 620 -SC_VRC_GL1X_SRC_STALLED = 621 -SC_VRC_RATEMEM_WE_CNT = 622 -SC_VRC_RATEMEM_RE_CNT = 623 -SC_VRC_HINTMEM_WE_CNT = 624 -SC_VRC_HINTMEM_RE_CNT = 625 -SC_VRC_BUSY = 626 -SC_GL1X_BUSY = 627 -SC_BE_VRS_RD_REQ = 628 -SC_BE_VRS_RD_REQ_STALLED = 629 -SC_BE_VRS_RD_REQ_HIT = 630 -SC_BE_VRS_RD_RET = 631 -SC_BE_VRS_RD_RET_STALLED = 632 -SC_BE_VRS_FB_RET = 633 -SC_BE_VRS_FB_RET_STALLED = 634 -SC_BE_VRS_FB_RET_HIT = 635 -SC_VRS_BE_BUSY = 636 -SC_PWS_CS_EVENTS_PWS_ENABLE = 637 -SC_PWS_PS_EVENTS_PWS_ENABLE = 638 -SC_PWS_TS_EVENTS_PWS_ENABLE = 639 -SC_PWS_STALLED = 640 -SC_PWS_P0_CS_SYNC_COMPLETE = 641 -SC_PWS_P0_PS_SYNC_COMPLETE = 642 -SC_PWS_P0_TS_SYNC_COMPLETE = 643 -SC_PWS_P1_CS_SYNC_COMPLETE = 644 -SC_PWS_P1_PS_SYNC_COMPLETE = 645 -SC_PWS_P1_TS_SYNC_COMPLETE = 646 -SC_PKR_PC_NO_CREDITS = 647 -SC_PKR_PC_STALLED = 648 -SC_PKR_PC_SEND = 649 -SC_PKR_PC_SEND_PRIM_VALID_1 = 650 -SC_PKR_PC_SEND_PRIM_VALID_0 = 651 -SC_PKR_PC_SEND_TRUE_PRIM = 652 -SC_PKR_PC_SEND_EOV = 653 -SC_PKR_PC_SEND_EVENT = 654 -SC_PKR_DB_WAVE_STALL = 655 -SC_PKR_PSINVOC_SEDC_FIFO_FULL = 656 -SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID = 657 -SC_PKR_SPI_QUAD_COUNT = 658 -SC_PKR_DB_OREO_WAVE_QUAD_COUNT = 659 -SC_PKR_BCI_QUAD_NEW_PRIM = 660 -SC_SPI_WAVE_STALLED_BY_SPI = 661 -SC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ScMap' -ScMap__enumvalues = { - 0: 'RASTER_CONFIG_SC_MAP_0', - 1: 'RASTER_CONFIG_SC_MAP_1', - 2: 'RASTER_CONFIG_SC_MAP_2', - 3: 'RASTER_CONFIG_SC_MAP_3', -} -RASTER_CONFIG_SC_MAP_0 = 0 -RASTER_CONFIG_SC_MAP_1 = 1 -RASTER_CONFIG_SC_MAP_2 = 2 -RASTER_CONFIG_SC_MAP_3 = 3 -ScMap = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMode' -ScUncertaintyRegionMode__enumvalues = { - 0: 'SC_HALF_LSB', - 1: 'SC_LSB_ONE_SIDED', - 2: 'SC_LSB_TWO_SIDED', -} -SC_HALF_LSB = 0 -SC_LSB_ONE_SIDED = 1 -SC_LSB_TWO_SIDED = 2 -ScUncertaintyRegionMode = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMult' -ScUncertaintyRegionMult__enumvalues = { - 0: 'SC_UR_1X', - 1: 'SC_UR_2X', - 2: 'SC_UR_4X', - 3: 'SC_UR_8X', -} -SC_UR_1X = 0 -SC_UR_2X = 1 -SC_UR_4X = 2 -SC_UR_8X = 3 -ScUncertaintyRegionMult = ctypes.c_uint32 # enum - -# values for enumeration 'ScXsel' -ScXsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 -ScXsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScYsel' -ScYsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 -ScYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeMap' -SeMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_MAP_0', - 1: 'RASTER_CONFIG_SE_MAP_1', - 2: 'RASTER_CONFIG_SE_MAP_2', - 3: 'RASTER_CONFIG_SE_MAP_3', -} -RASTER_CONFIG_SE_MAP_0 = 0 -RASTER_CONFIG_SE_MAP_1 = 1 -RASTER_CONFIG_SE_MAP_2 = 2 -RASTER_CONFIG_SE_MAP_3 = 3 -SeMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairMap' -SePairMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', - 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', - 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', - 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', -} -RASTER_CONFIG_SE_PAIR_MAP_0 = 0 -RASTER_CONFIG_SE_PAIR_MAP_1 = 1 -RASTER_CONFIG_SE_PAIR_MAP_2 = 2 -RASTER_CONFIG_SE_PAIR_MAP_3 = 3 -SePairMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairXsel' -SePairXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 -SePairXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairYsel' -SePairYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 -SePairYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeXsel' -SeXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 -SeXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeYsel' -SeYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 -SeYsel = ctypes.c_uint32 # enum - -# values for enumeration 'VRSCombinerModeSC' -VRSCombinerModeSC__enumvalues = { - 0: 'SC_VRS_COMB_MODE_PASSTHRU', - 1: 'SC_VRS_COMB_MODE_OVERRIDE', - 2: 'SC_VRS_COMB_MODE_MIN', - 3: 'SC_VRS_COMB_MODE_MAX', - 4: 'SC_VRS_COMB_MODE_SATURATE', -} -SC_VRS_COMB_MODE_PASSTHRU = 0 -SC_VRS_COMB_MODE_OVERRIDE = 1 -SC_VRS_COMB_MODE_MIN = 2 -SC_VRS_COMB_MODE_MAX = 3 -SC_VRS_COMB_MODE_SATURATE = 4 -VRSCombinerModeSC = ctypes.c_uint32 # enum - -# values for enumeration 'VRSrate' -VRSrate__enumvalues = { - 0: 'VRS_SHADING_RATE_1X1', - 1: 'VRS_SHADING_RATE_1X2', - 2: 'VRS_SHADING_RATE_UNDEFINED0', - 3: 'VRS_SHADING_RATE_UNDEFINED1', - 4: 'VRS_SHADING_RATE_2X1', - 5: 'VRS_SHADING_RATE_2X2', - 6: 'VRS_SHADING_RATE_2X4', - 7: 'VRS_SHADING_RATE_UNDEFINED2', - 8: 'VRS_SHADING_RATE_UNDEFINED3', - 9: 'VRS_SHADING_RATE_4X2', - 10: 'VRS_SHADING_RATE_4X4', - 11: 'VRS_SHADING_RATE_UNDEFINED4', - 12: 'VRS_SHADING_RATE_16X_SSAA', - 13: 'VRS_SHADING_RATE_8X_SSAA', - 14: 'VRS_SHADING_RATE_4X_SSAA', - 15: 'VRS_SHADING_RATE_2X_SSAA', -} -VRS_SHADING_RATE_1X1 = 0 -VRS_SHADING_RATE_1X2 = 1 -VRS_SHADING_RATE_UNDEFINED0 = 2 -VRS_SHADING_RATE_UNDEFINED1 = 3 -VRS_SHADING_RATE_2X1 = 4 -VRS_SHADING_RATE_2X2 = 5 -VRS_SHADING_RATE_2X4 = 6 -VRS_SHADING_RATE_UNDEFINED2 = 7 -VRS_SHADING_RATE_UNDEFINED3 = 8 -VRS_SHADING_RATE_4X2 = 9 -VRS_SHADING_RATE_4X4 = 10 -VRS_SHADING_RATE_UNDEFINED4 = 11 -VRS_SHADING_RATE_16X_SSAA = 12 -VRS_SHADING_RATE_8X_SSAA = 13 -VRS_SHADING_RATE_4X_SSAA = 14 -VRS_SHADING_RATE_2X_SSAA = 15 -VRSrate = ctypes.c_uint32 # enum - -# values for enumeration 'TC_EA_CID' -TC_EA_CID__enumvalues = { - 0: 'TC_EA_CID_RT', - 1: 'TC_EA_CID_FMASK', - 2: 'TC_EA_CID_DCC', - 3: 'TC_EA_CID_TCPMETA', - 4: 'TC_EA_CID_Z', - 5: 'TC_EA_CID_STENCIL', - 6: 'TC_EA_CID_HTILE', - 7: 'TC_EA_CID_MISC', - 8: 'TC_EA_CID_TCP', - 9: 'TC_EA_CID_SQC', - 10: 'TC_EA_CID_CPF', - 11: 'TC_EA_CID_CPG', - 12: 'TC_EA_CID_IA', - 13: 'TC_EA_CID_WD', - 14: 'TC_EA_CID_PA', - 15: 'TC_EA_CID_UTCL2_TPI', -} -TC_EA_CID_RT = 0 -TC_EA_CID_FMASK = 1 -TC_EA_CID_DCC = 2 -TC_EA_CID_TCPMETA = 3 -TC_EA_CID_Z = 4 -TC_EA_CID_STENCIL = 5 -TC_EA_CID_HTILE = 6 -TC_EA_CID_MISC = 7 -TC_EA_CID_TCP = 8 -TC_EA_CID_SQC = 9 -TC_EA_CID_CPF = 10 -TC_EA_CID_CPG = 11 -TC_EA_CID_IA = 12 -TC_EA_CID_WD = 13 -TC_EA_CID_PA = 14 -TC_EA_CID_UTCL2_TPI = 15 -TC_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'TC_NACKS' -TC_NACKS__enumvalues = { - 0: 'TC_NACK_NO_FAULT', - 1: 'TC_NACK_PAGE_FAULT', - 2: 'TC_NACK_PROTECTION_FAULT', - 3: 'TC_NACK_DATA_ERROR', -} -TC_NACK_NO_FAULT = 0 -TC_NACK_PAGE_FAULT = 1 -TC_NACK_PROTECTION_FAULT = 2 -TC_NACK_DATA_ERROR = 3 -TC_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP' -TC_OP__enumvalues = { - 0: 'TC_OP_READ', - 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'TC_OP_ATOMIC_FMIN_RTN_32', - 3: 'TC_OP_ATOMIC_FMAX_RTN_32', - 4: 'TC_OP_RESERVED_FOP_RTN_32_0', - 5: 'TC_OP_RESERVED_FADD_RTN_32', - 6: 'TC_OP_RESERVED_FOP_RTN_32_2', - 7: 'TC_OP_ATOMIC_SWAP_RTN_32', - 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'TC_OP_PROBE_FILTER', - 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'TC_OP_ATOMIC_ADD_RTN_32', - 16: 'TC_OP_ATOMIC_SUB_RTN_32', - 17: 'TC_OP_ATOMIC_SMIN_RTN_32', - 18: 'TC_OP_ATOMIC_UMIN_RTN_32', - 19: 'TC_OP_ATOMIC_SMAX_RTN_32', - 20: 'TC_OP_ATOMIC_UMAX_RTN_32', - 21: 'TC_OP_ATOMIC_AND_RTN_32', - 22: 'TC_OP_ATOMIC_OR_RTN_32', - 23: 'TC_OP_ATOMIC_XOR_RTN_32', - 24: 'TC_OP_ATOMIC_INC_RTN_32', - 25: 'TC_OP_ATOMIC_DEC_RTN_32', - 26: 'TC_OP_WBINVL1_VOL', - 27: 'TC_OP_WBINVL1_SD', - 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 32: 'TC_OP_WRITE', - 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'TC_OP_ATOMIC_FMIN_RTN_64', - 35: 'TC_OP_ATOMIC_FMAX_RTN_64', - 36: 'TC_OP_RESERVED_FOP_RTN_64_0', - 37: 'TC_OP_RESERVED_FOP_RTN_64_1', - 38: 'TC_OP_RESERVED_FOP_RTN_64_2', - 39: 'TC_OP_ATOMIC_SWAP_RTN_64', - 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 44: 'TC_OP_WBINVL2_SD', - 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 47: 'TC_OP_ATOMIC_ADD_RTN_64', - 48: 'TC_OP_ATOMIC_SUB_RTN_64', - 49: 'TC_OP_ATOMIC_SMIN_RTN_64', - 50: 'TC_OP_ATOMIC_UMIN_RTN_64', - 51: 'TC_OP_ATOMIC_SMAX_RTN_64', - 52: 'TC_OP_ATOMIC_UMAX_RTN_64', - 53: 'TC_OP_ATOMIC_AND_RTN_64', - 54: 'TC_OP_ATOMIC_OR_RTN_64', - 55: 'TC_OP_ATOMIC_XOR_RTN_64', - 56: 'TC_OP_ATOMIC_INC_RTN_64', - 57: 'TC_OP_ATOMIC_DEC_RTN_64', - 58: 'TC_OP_WBL2_NC', - 59: 'TC_OP_WBL2_WC', - 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', - 64: 'TC_OP_WBINVL1', - 65: 'TC_OP_ATOMIC_FCMPSWAP_32', - 66: 'TC_OP_ATOMIC_FMIN_32', - 67: 'TC_OP_ATOMIC_FMAX_32', - 68: 'TC_OP_RESERVED_FOP_32_0', - 69: 'TC_OP_RESERVED_FADD_32', - 70: 'TC_OP_RESERVED_FOP_32_2', - 71: 'TC_OP_ATOMIC_SWAP_32', - 72: 'TC_OP_ATOMIC_CMPSWAP_32', - 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'TC_OP_INV_METADATA', - 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 79: 'TC_OP_ATOMIC_ADD_32', - 80: 'TC_OP_ATOMIC_SUB_32', - 81: 'TC_OP_ATOMIC_SMIN_32', - 82: 'TC_OP_ATOMIC_UMIN_32', - 83: 'TC_OP_ATOMIC_SMAX_32', - 84: 'TC_OP_ATOMIC_UMAX_32', - 85: 'TC_OP_ATOMIC_AND_32', - 86: 'TC_OP_ATOMIC_OR_32', - 87: 'TC_OP_ATOMIC_XOR_32', - 88: 'TC_OP_ATOMIC_INC_32', - 89: 'TC_OP_ATOMIC_DEC_32', - 90: 'TC_OP_INVL2_NC', - 91: 'TC_OP_NOP_RTN0', - 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', - 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', - 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', - 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', - 96: 'TC_OP_WBINVL2', - 97: 'TC_OP_ATOMIC_FCMPSWAP_64', - 98: 'TC_OP_ATOMIC_FMIN_64', - 99: 'TC_OP_ATOMIC_FMAX_64', - 100: 'TC_OP_RESERVED_FOP_64_0', - 101: 'TC_OP_RESERVED_FOP_64_1', - 102: 'TC_OP_RESERVED_FOP_64_2', - 103: 'TC_OP_ATOMIC_SWAP_64', - 104: 'TC_OP_ATOMIC_CMPSWAP_64', - 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 111: 'TC_OP_ATOMIC_ADD_64', - 112: 'TC_OP_ATOMIC_SUB_64', - 113: 'TC_OP_ATOMIC_SMIN_64', - 114: 'TC_OP_ATOMIC_UMIN_64', - 115: 'TC_OP_ATOMIC_SMAX_64', - 116: 'TC_OP_ATOMIC_UMAX_64', - 117: 'TC_OP_ATOMIC_AND_64', - 118: 'TC_OP_ATOMIC_OR_64', - 119: 'TC_OP_ATOMIC_XOR_64', - 120: 'TC_OP_ATOMIC_INC_64', - 121: 'TC_OP_ATOMIC_DEC_64', - 122: 'TC_OP_WBINVL2_NC', - 123: 'TC_OP_NOP_ACK', - 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', - 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', - 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', - 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', -} -TC_OP_READ = 0 -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -TC_OP_ATOMIC_FMIN_RTN_32 = 2 -TC_OP_ATOMIC_FMAX_RTN_32 = 3 -TC_OP_RESERVED_FOP_RTN_32_0 = 4 -TC_OP_RESERVED_FADD_RTN_32 = 5 -TC_OP_RESERVED_FOP_RTN_32_2 = 6 -TC_OP_ATOMIC_SWAP_RTN_32 = 7 -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -TC_OP_PROBE_FILTER = 12 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -TC_OP_ATOMIC_ADD_RTN_32 = 15 -TC_OP_ATOMIC_SUB_RTN_32 = 16 -TC_OP_ATOMIC_SMIN_RTN_32 = 17 -TC_OP_ATOMIC_UMIN_RTN_32 = 18 -TC_OP_ATOMIC_SMAX_RTN_32 = 19 -TC_OP_ATOMIC_UMAX_RTN_32 = 20 -TC_OP_ATOMIC_AND_RTN_32 = 21 -TC_OP_ATOMIC_OR_RTN_32 = 22 -TC_OP_ATOMIC_XOR_RTN_32 = 23 -TC_OP_ATOMIC_INC_RTN_32 = 24 -TC_OP_ATOMIC_DEC_RTN_32 = 25 -TC_OP_WBINVL1_VOL = 26 -TC_OP_WBINVL1_SD = 27 -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 -TC_OP_WRITE = 32 -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -TC_OP_ATOMIC_FMIN_RTN_64 = 34 -TC_OP_ATOMIC_FMAX_RTN_64 = 35 -TC_OP_RESERVED_FOP_RTN_64_0 = 36 -TC_OP_RESERVED_FOP_RTN_64_1 = 37 -TC_OP_RESERVED_FOP_RTN_64_2 = 38 -TC_OP_ATOMIC_SWAP_RTN_64 = 39 -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -TC_OP_WBINVL2_SD = 44 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 -TC_OP_ATOMIC_ADD_RTN_64 = 47 -TC_OP_ATOMIC_SUB_RTN_64 = 48 -TC_OP_ATOMIC_SMIN_RTN_64 = 49 -TC_OP_ATOMIC_UMIN_RTN_64 = 50 -TC_OP_ATOMIC_SMAX_RTN_64 = 51 -TC_OP_ATOMIC_UMAX_RTN_64 = 52 -TC_OP_ATOMIC_AND_RTN_64 = 53 -TC_OP_ATOMIC_OR_RTN_64 = 54 -TC_OP_ATOMIC_XOR_RTN_64 = 55 -TC_OP_ATOMIC_INC_RTN_64 = 56 -TC_OP_ATOMIC_DEC_RTN_64 = 57 -TC_OP_WBL2_NC = 58 -TC_OP_WBL2_WC = 59 -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 -TC_OP_WBINVL1 = 64 -TC_OP_ATOMIC_FCMPSWAP_32 = 65 -TC_OP_ATOMIC_FMIN_32 = 66 -TC_OP_ATOMIC_FMAX_32 = 67 -TC_OP_RESERVED_FOP_32_0 = 68 -TC_OP_RESERVED_FADD_32 = 69 -TC_OP_RESERVED_FOP_32_2 = 70 -TC_OP_ATOMIC_SWAP_32 = 71 -TC_OP_ATOMIC_CMPSWAP_32 = 72 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -TC_OP_INV_METADATA = 76 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 -TC_OP_ATOMIC_ADD_32 = 79 -TC_OP_ATOMIC_SUB_32 = 80 -TC_OP_ATOMIC_SMIN_32 = 81 -TC_OP_ATOMIC_UMIN_32 = 82 -TC_OP_ATOMIC_SMAX_32 = 83 -TC_OP_ATOMIC_UMAX_32 = 84 -TC_OP_ATOMIC_AND_32 = 85 -TC_OP_ATOMIC_OR_32 = 86 -TC_OP_ATOMIC_XOR_32 = 87 -TC_OP_ATOMIC_INC_32 = 88 -TC_OP_ATOMIC_DEC_32 = 89 -TC_OP_INVL2_NC = 90 -TC_OP_NOP_RTN0 = 91 -TC_OP_RESERVED_NON_FLOAT_32_1 = 92 -TC_OP_RESERVED_NON_FLOAT_32_2 = 93 -TC_OP_RESERVED_NON_FLOAT_32_3 = 94 -TC_OP_RESERVED_NON_FLOAT_32_4 = 95 -TC_OP_WBINVL2 = 96 -TC_OP_ATOMIC_FCMPSWAP_64 = 97 -TC_OP_ATOMIC_FMIN_64 = 98 -TC_OP_ATOMIC_FMAX_64 = 99 -TC_OP_RESERVED_FOP_64_0 = 100 -TC_OP_RESERVED_FOP_64_1 = 101 -TC_OP_RESERVED_FOP_64_2 = 102 -TC_OP_ATOMIC_SWAP_64 = 103 -TC_OP_ATOMIC_CMPSWAP_64 = 104 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 -TC_OP_ATOMIC_ADD_64 = 111 -TC_OP_ATOMIC_SUB_64 = 112 -TC_OP_ATOMIC_SMIN_64 = 113 -TC_OP_ATOMIC_UMIN_64 = 114 -TC_OP_ATOMIC_SMAX_64 = 115 -TC_OP_ATOMIC_UMAX_64 = 116 -TC_OP_ATOMIC_AND_64 = 117 -TC_OP_ATOMIC_OR_64 = 118 -TC_OP_ATOMIC_XOR_64 = 119 -TC_OP_ATOMIC_INC_64 = 120 -TC_OP_ATOMIC_DEC_64 = 121 -TC_OP_WBINVL2_NC = 122 -TC_OP_NOP_ACK = 123 -TC_OP_RESERVED_NON_FLOAT_64_1 = 124 -TC_OP_RESERVED_NON_FLOAT_64_2 = 125 -TC_OP_RESERVED_NON_FLOAT_64_3 = 126 -TC_OP_RESERVED_NON_FLOAT_64_4 = 127 -TC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP_MASKS' -TC_OP_MASKS__enumvalues = { - 8: 'TC_OP_MASK_FLUSH_DENROM', - 32: 'TC_OP_MASK_64', - 64: 'TC_OP_MASK_NO_RTN', -} -TC_OP_MASK_FLUSH_DENROM = 8 -TC_OP_MASK_64 = 32 -TC_OP_MASK_NO_RTN = 64 -TC_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_BASE_MODE' -CLKGATE_BASE_MODE__enumvalues = { - 0: 'MULT_8', - 1: 'MULT_16', -} -MULT_8 = 0 -MULT_16 = 1 -CLKGATE_BASE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_SM_MODE' -CLKGATE_SM_MODE__enumvalues = { - 0: 'ON_SEQ', - 1: 'OFF_SEQ', - 2: 'PROG_SEQ', - 3: 'READ_SEQ', - 4: 'SM_MODE_RESERVED', -} -ON_SEQ = 0 -OFF_SEQ = 1 -PROG_SEQ = 2 -READ_SEQ = 3 -SM_MODE_RESERVED = 4 -CLKGATE_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CovToShaderSel' -CovToShaderSel__enumvalues = { - 0: 'INPUT_COVERAGE', - 1: 'INPUT_INNER_COVERAGE', - 2: 'INPUT_DEPTH_COVERAGE', - 3: 'RAW', -} -INPUT_COVERAGE = 0 -INPUT_INNER_COVERAGE = 1 -INPUT_DEPTH_COVERAGE = 2 -RAW = 3 -CovToShaderSel = ctypes.c_uint32 # enum - -# values for enumeration 'PC_PERFCNT_SEL' -PC_PERFCNT_SEL__enumvalues = { - 0: 'PC_PERF_SC_PC_PTR_SEND0', - 1: 'PC_PERF_SC_PC_PTR_VALID0', - 2: 'PC_PERF_SC_FPOSG0', - 3: 'PC_PERF_SC_FPOSG_WAIT0', - 4: 'PC_PERF_SC_WAIT_SYNC0', - 5: 'PC_PERF_SC_PQ_FREEZE0', - 6: 'PC_PERF_PKR0_FPOSG_EQ1', - 7: 'PC_PERF_PKR0_FPOSG_GT1', - 8: 'PC_PERF_PKR0_FPOSG_GT16', - 9: 'PC_PERF_PKR0_FPOSG_GT64', - 10: 'PC_PERF_PKR0_FPOSG_GT128', - 11: 'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE', - 12: 'PC_PERF_PKR0_NUM_PROBES', - 13: 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1', - 14: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1', - 15: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2', - 16: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4', - 17: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8', - 18: 'PC_PERF_PKR0_NUM_WAVES', - 19: 'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1', - 20: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1', - 21: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2', - 22: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4', - 23: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8', - 24: 'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1', - 25: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT1', - 26: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT2', - 27: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT4', - 28: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT8', - 29: 'PC_PERF_PKR0_PRIMS_REUSE', - 30: 'PC_PERF_SC_PC_PTR_SEND1', - 31: 'PC_PERF_SC_PC_PTR_VALID1', - 32: 'PC_PERF_SC_FPOSG1', - 33: 'PC_PERF_SC_FPOSG_WAIT1', - 34: 'PC_PERF_SC_WAIT_SYNC1', - 35: 'PC_PERF_SC_PQ_FREEZE1', - 36: 'PC_PERF_PKR1_FPOSG_EQ1', - 37: 'PC_PERF_PKR1_FPOSG_GT1', - 38: 'PC_PERF_PKR1_FPOSG_GT16', - 39: 'PC_PERF_PKR1_FPOSG_GT64', - 40: 'PC_PERF_PKR1_FPOSG_GT128', - 41: 'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE', - 42: 'PC_PERF_PKR1_NUM_PROBES', - 43: 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1', - 44: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1', - 45: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2', - 46: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4', - 47: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8', - 48: 'PC_PERF_PKR1_NUM_WAVES', - 49: 'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1', - 50: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1', - 51: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2', - 52: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4', - 53: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8', - 54: 'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1', - 55: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT1', - 56: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT2', - 57: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT4', - 58: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT8', - 59: 'PC_PERF_PKR1_PRIMS_REUSE', - 60: 'PC_PERF_SC_PC_PTR_SEND2', - 61: 'PC_PERF_SC_PC_PTR_VALID2', - 62: 'PC_PERF_SC_FPOSG2', - 63: 'PC_PERF_SC_FPOSG_WAIT2', - 64: 'PC_PERF_SC_WAIT_SYNC2', - 65: 'PC_PERF_SC_PQ_FREEZE2', - 66: 'PC_PERF_PKR2_FPOSG_EQ1', - 67: 'PC_PERF_PKR2_FPOSG_GT1', - 68: 'PC_PERF_PKR2_FPOSG_GT16', - 69: 'PC_PERF_PKR2_FPOSG_GT64', - 70: 'PC_PERF_PKR2_FPOSG_GT128', - 71: 'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE', - 72: 'PC_PERF_PKR2_NUM_PROBES', - 73: 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1', - 74: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1', - 75: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2', - 76: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4', - 77: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8', - 78: 'PC_PERF_PKR2_NUM_WAVES', - 79: 'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1', - 80: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1', - 81: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2', - 82: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4', - 83: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8', - 84: 'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1', - 85: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT1', - 86: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT2', - 87: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT4', - 88: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT8', - 89: 'PC_PERF_PKR2_PRIMS_REUSE', - 90: 'PC_PERF_SC_PC_PTR_SEND3', - 91: 'PC_PERF_SC_PC_PTR_VALID3', - 92: 'PC_PERF_SC_FPOSG3', - 93: 'PC_PERF_SC_FPOSG_WAIT3', - 94: 'PC_PERF_SC_WAIT_SYNC3', - 95: 'PC_PERF_SC_PQ_FREEZE3', - 96: 'PC_PERF_PKR3_FPOSG_EQ1', - 97: 'PC_PERF_PKR3_FPOSG_GT1', - 98: 'PC_PERF_PKR3_FPOSG_GT16', - 99: 'PC_PERF_PKR3_FPOSG_GT64', - 100: 'PC_PERF_PKR3_FPOSG_GT128', - 101: 'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE', - 102: 'PC_PERF_PKR3_NUM_PROBES', - 103: 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1', - 104: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1', - 105: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2', - 106: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4', - 107: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8', - 108: 'PC_PERF_PKR3_NUM_WAVES', - 109: 'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1', - 110: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1', - 111: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2', - 112: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4', - 113: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8', - 114: 'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1', - 115: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT1', - 116: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT2', - 117: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT4', - 118: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT8', - 119: 'PC_PERF_PKR3_PRIMS_REUSE', - 120: 'PC_PERF_SC_MW_FREEZE', - 121: 'PC_PERF_SC_NUM_PROBES', - 122: 'PC_PERF_SC_NUM_WAVES', - 123: 'PC_PERF_SC_NUM_SPLIT_WAVES', - 124: 'PC_PERF_GE_GSDONE', - 125: 'PC_PERF_PKR0_GSDONE_WHILE_IDLE', - 126: 'PC_PERF_PKR1_GSDONE_WHILE_IDLE', - 127: 'PC_PERF_PKR2_GSDONE_WHILE_IDLE', - 128: 'PC_PERF_PKR3_GSDONE_WHILE_IDLE', - 129: 'PC_PERF_PC_SPI_PROBE_FREEZE', - 130: 'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT', - 131: 'PC_PERF_MW_RTN_ADDR_FREEZE', - 132: 'PC_PERF_MW_PROBE_CNT_FREEZE', - 133: 'PC_PERF_MW_GL1H_REQ_FREEZE', - 134: 'PC_PERF_MW_GL1H_NUM_REQS', - 135: 'PC_PERF_MW_DLINE_ALLOC', - 136: 'PC_PERF_MW_DLINE_DEALLOC', - 137: 'PC_PERF_MW_TAGLINE_ALLOC', - 138: 'PC_PERF_MW_TAGLINE_DEALLOC', - 139: 'PC_PERF_MW_PHY_DLINE_FULL_STALL', - 140: 'PC_PERF_MW_CACHE_CNTL_FULL_STALL', - 141: 'PC_PERF_MW_STAMP_LIMIT_STALL', - 142: 'PC_PERF_MW_CACHE_MISS', - 143: 'PC_PERF_MW_CACHE_HIT', - 144: 'PC_PERF_MW_CACHE_REUSE', - 145: 'PC_PERF_MW_DEALLOC_HIT', - 146: 'PC_PERF_PC_MEM_BANK_CONF0', - 147: 'PC_PERF_PC_MEM_BANK_CONF1', - 148: 'PC_PERF_PC_LDS_VERTEX_REUSE0', - 149: 'PC_PERF_PC_LDS_CNTL_VALID0', - 150: 'PC_PERF_PC_LDS_VERTEX_REUSE1', - 151: 'PC_PERF_PC_LDS_CNTL_VALID1', - 152: 'PC_PERF_GRBM_BUSY', - 153: 'PC_PERF_GL1_RTN_CNT_GTE1', - 154: 'PC_PERF_GL1_RTN_CNT_GT512', - 155: 'PC_PERF_GL1_RTN_CNT_GT768', - 156: 'PC_PERF_LWC0_PROBE_ORDER_STALL', - 157: 'PC_PERF_LWC0_PC_MEM_READ_STALL', - 158: 'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING', - 159: 'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING', - 160: 'PC_PERF_LWC1_PROBE_ORDER_STALL', - 161: 'PC_PERF_LWC1_PC_MEM_READ_STALL', - 162: 'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING', - 163: 'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING', - 164: 'PC_PERF_NUM_PSWAVE', -} -PC_PERF_SC_PC_PTR_SEND0 = 0 -PC_PERF_SC_PC_PTR_VALID0 = 1 -PC_PERF_SC_FPOSG0 = 2 -PC_PERF_SC_FPOSG_WAIT0 = 3 -PC_PERF_SC_WAIT_SYNC0 = 4 -PC_PERF_SC_PQ_FREEZE0 = 5 -PC_PERF_PKR0_FPOSG_EQ1 = 6 -PC_PERF_PKR0_FPOSG_GT1 = 7 -PC_PERF_PKR0_FPOSG_GT16 = 8 -PC_PERF_PKR0_FPOSG_GT64 = 9 -PC_PERF_PKR0_FPOSG_GT128 = 10 -PC_PERF_PKR0_FPOSG_OUT_OF_WAVE = 11 -PC_PERF_PKR0_NUM_PROBES = 12 -PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1 = 13 -PC_PERF_PKR0_PRIMS_PER_PROBE_GT1 = 14 -PC_PERF_PKR0_PRIMS_PER_PROBE_GT2 = 15 -PC_PERF_PKR0_PRIMS_PER_PROBE_GT4 = 16 -PC_PERF_PKR0_PRIMS_PER_PROBE_GT8 = 17 -PC_PERF_PKR0_NUM_WAVES = 18 -PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1 = 19 -PC_PERF_PKR0_PRIMS_PER_WAVE_GT1 = 20 -PC_PERF_PKR0_PRIMS_PER_WAVE_GT2 = 21 -PC_PERF_PKR0_PRIMS_PER_WAVE_GT4 = 22 -PC_PERF_PKR0_PRIMS_PER_WAVE_GT8 = 23 -PC_PERF_PKR0_PROBES_PER_WAVE_EQ1 = 24 -PC_PERF_PKR0_PROBES_PER_WAVE_GT1 = 25 -PC_PERF_PKR0_PROBES_PER_WAVE_GT2 = 26 -PC_PERF_PKR0_PROBES_PER_WAVE_GT4 = 27 -PC_PERF_PKR0_PROBES_PER_WAVE_GT8 = 28 -PC_PERF_PKR0_PRIMS_REUSE = 29 -PC_PERF_SC_PC_PTR_SEND1 = 30 -PC_PERF_SC_PC_PTR_VALID1 = 31 -PC_PERF_SC_FPOSG1 = 32 -PC_PERF_SC_FPOSG_WAIT1 = 33 -PC_PERF_SC_WAIT_SYNC1 = 34 -PC_PERF_SC_PQ_FREEZE1 = 35 -PC_PERF_PKR1_FPOSG_EQ1 = 36 -PC_PERF_PKR1_FPOSG_GT1 = 37 -PC_PERF_PKR1_FPOSG_GT16 = 38 -PC_PERF_PKR1_FPOSG_GT64 = 39 -PC_PERF_PKR1_FPOSG_GT128 = 40 -PC_PERF_PKR1_FPOSG_OUT_OF_WAVE = 41 -PC_PERF_PKR1_NUM_PROBES = 42 -PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1 = 43 -PC_PERF_PKR1_PRIMS_PER_PROBE_GT1 = 44 -PC_PERF_PKR1_PRIMS_PER_PROBE_GT2 = 45 -PC_PERF_PKR1_PRIMS_PER_PROBE_GT4 = 46 -PC_PERF_PKR1_PRIMS_PER_PROBE_GT8 = 47 -PC_PERF_PKR1_NUM_WAVES = 48 -PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1 = 49 -PC_PERF_PKR1_PRIMS_PER_WAVE_GT1 = 50 -PC_PERF_PKR1_PRIMS_PER_WAVE_GT2 = 51 -PC_PERF_PKR1_PRIMS_PER_WAVE_GT4 = 52 -PC_PERF_PKR1_PRIMS_PER_WAVE_GT8 = 53 -PC_PERF_PKR1_PROBES_PER_WAVE_EQ1 = 54 -PC_PERF_PKR1_PROBES_PER_WAVE_GT1 = 55 -PC_PERF_PKR1_PROBES_PER_WAVE_GT2 = 56 -PC_PERF_PKR1_PROBES_PER_WAVE_GT4 = 57 -PC_PERF_PKR1_PROBES_PER_WAVE_GT8 = 58 -PC_PERF_PKR1_PRIMS_REUSE = 59 -PC_PERF_SC_PC_PTR_SEND2 = 60 -PC_PERF_SC_PC_PTR_VALID2 = 61 -PC_PERF_SC_FPOSG2 = 62 -PC_PERF_SC_FPOSG_WAIT2 = 63 -PC_PERF_SC_WAIT_SYNC2 = 64 -PC_PERF_SC_PQ_FREEZE2 = 65 -PC_PERF_PKR2_FPOSG_EQ1 = 66 -PC_PERF_PKR2_FPOSG_GT1 = 67 -PC_PERF_PKR2_FPOSG_GT16 = 68 -PC_PERF_PKR2_FPOSG_GT64 = 69 -PC_PERF_PKR2_FPOSG_GT128 = 70 -PC_PERF_PKR2_FPOSG_OUT_OF_WAVE = 71 -PC_PERF_PKR2_NUM_PROBES = 72 -PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1 = 73 -PC_PERF_PKR2_PRIMS_PER_PROBE_GT1 = 74 -PC_PERF_PKR2_PRIMS_PER_PROBE_GT2 = 75 -PC_PERF_PKR2_PRIMS_PER_PROBE_GT4 = 76 -PC_PERF_PKR2_PRIMS_PER_PROBE_GT8 = 77 -PC_PERF_PKR2_NUM_WAVES = 78 -PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1 = 79 -PC_PERF_PKR2_PRIMS_PER_WAVE_GT1 = 80 -PC_PERF_PKR2_PRIMS_PER_WAVE_GT2 = 81 -PC_PERF_PKR2_PRIMS_PER_WAVE_GT4 = 82 -PC_PERF_PKR2_PRIMS_PER_WAVE_GT8 = 83 -PC_PERF_PKR2_PROBES_PER_WAVE_EQ1 = 84 -PC_PERF_PKR2_PROBES_PER_WAVE_GT1 = 85 -PC_PERF_PKR2_PROBES_PER_WAVE_GT2 = 86 -PC_PERF_PKR2_PROBES_PER_WAVE_GT4 = 87 -PC_PERF_PKR2_PROBES_PER_WAVE_GT8 = 88 -PC_PERF_PKR2_PRIMS_REUSE = 89 -PC_PERF_SC_PC_PTR_SEND3 = 90 -PC_PERF_SC_PC_PTR_VALID3 = 91 -PC_PERF_SC_FPOSG3 = 92 -PC_PERF_SC_FPOSG_WAIT3 = 93 -PC_PERF_SC_WAIT_SYNC3 = 94 -PC_PERF_SC_PQ_FREEZE3 = 95 -PC_PERF_PKR3_FPOSG_EQ1 = 96 -PC_PERF_PKR3_FPOSG_GT1 = 97 -PC_PERF_PKR3_FPOSG_GT16 = 98 -PC_PERF_PKR3_FPOSG_GT64 = 99 -PC_PERF_PKR3_FPOSG_GT128 = 100 -PC_PERF_PKR3_FPOSG_OUT_OF_WAVE = 101 -PC_PERF_PKR3_NUM_PROBES = 102 -PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1 = 103 -PC_PERF_PKR3_PRIMS_PER_PROBE_GT1 = 104 -PC_PERF_PKR3_PRIMS_PER_PROBE_GT2 = 105 -PC_PERF_PKR3_PRIMS_PER_PROBE_GT4 = 106 -PC_PERF_PKR3_PRIMS_PER_PROBE_GT8 = 107 -PC_PERF_PKR3_NUM_WAVES = 108 -PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1 = 109 -PC_PERF_PKR3_PRIMS_PER_WAVE_GT1 = 110 -PC_PERF_PKR3_PRIMS_PER_WAVE_GT2 = 111 -PC_PERF_PKR3_PRIMS_PER_WAVE_GT4 = 112 -PC_PERF_PKR3_PRIMS_PER_WAVE_GT8 = 113 -PC_PERF_PKR3_PROBES_PER_WAVE_EQ1 = 114 -PC_PERF_PKR3_PROBES_PER_WAVE_GT1 = 115 -PC_PERF_PKR3_PROBES_PER_WAVE_GT2 = 116 -PC_PERF_PKR3_PROBES_PER_WAVE_GT4 = 117 -PC_PERF_PKR3_PROBES_PER_WAVE_GT8 = 118 -PC_PERF_PKR3_PRIMS_REUSE = 119 -PC_PERF_SC_MW_FREEZE = 120 -PC_PERF_SC_NUM_PROBES = 121 -PC_PERF_SC_NUM_WAVES = 122 -PC_PERF_SC_NUM_SPLIT_WAVES = 123 -PC_PERF_GE_GSDONE = 124 -PC_PERF_PKR0_GSDONE_WHILE_IDLE = 125 -PC_PERF_PKR1_GSDONE_WHILE_IDLE = 126 -PC_PERF_PKR2_GSDONE_WHILE_IDLE = 127 -PC_PERF_PKR3_GSDONE_WHILE_IDLE = 128 -PC_PERF_PC_SPI_PROBE_FREEZE = 129 -PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT = 130 -PC_PERF_MW_RTN_ADDR_FREEZE = 131 -PC_PERF_MW_PROBE_CNT_FREEZE = 132 -PC_PERF_MW_GL1H_REQ_FREEZE = 133 -PC_PERF_MW_GL1H_NUM_REQS = 134 -PC_PERF_MW_DLINE_ALLOC = 135 -PC_PERF_MW_DLINE_DEALLOC = 136 -PC_PERF_MW_TAGLINE_ALLOC = 137 -PC_PERF_MW_TAGLINE_DEALLOC = 138 -PC_PERF_MW_PHY_DLINE_FULL_STALL = 139 -PC_PERF_MW_CACHE_CNTL_FULL_STALL = 140 -PC_PERF_MW_STAMP_LIMIT_STALL = 141 -PC_PERF_MW_CACHE_MISS = 142 -PC_PERF_MW_CACHE_HIT = 143 -PC_PERF_MW_CACHE_REUSE = 144 -PC_PERF_MW_DEALLOC_HIT = 145 -PC_PERF_PC_MEM_BANK_CONF0 = 146 -PC_PERF_PC_MEM_BANK_CONF1 = 147 -PC_PERF_PC_LDS_VERTEX_REUSE0 = 148 -PC_PERF_PC_LDS_CNTL_VALID0 = 149 -PC_PERF_PC_LDS_VERTEX_REUSE1 = 150 -PC_PERF_PC_LDS_CNTL_VALID1 = 151 -PC_PERF_GRBM_BUSY = 152 -PC_PERF_GL1_RTN_CNT_GTE1 = 153 -PC_PERF_GL1_RTN_CNT_GT512 = 154 -PC_PERF_GL1_RTN_CNT_GT768 = 155 -PC_PERF_LWC0_PROBE_ORDER_STALL = 156 -PC_PERF_LWC0_PC_MEM_READ_STALL = 157 -PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING = 158 -PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING = 159 -PC_PERF_LWC1_PROBE_ORDER_STALL = 160 -PC_PERF_LWC1_PC_MEM_READ_STALL = 161 -PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING = 162 -PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING = 163 -PC_PERF_NUM_PSWAVE = 164 -PC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_FOG_MODE' -SPI_FOG_MODE__enumvalues = { - 0: 'SPI_FOG_NONE', - 1: 'SPI_FOG_EXP', - 2: 'SPI_FOG_EXP2', - 3: 'SPI_FOG_LINEAR', -} -SPI_FOG_NONE = 0 -SPI_FOG_EXP = 1 -SPI_FOG_EXP2 = 2 -SPI_FOG_LINEAR = 3 -SPI_FOG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_LB_WAVES_SELECT' -SPI_LB_WAVES_SELECT__enumvalues = { - 0: 'HS_GS', - 1: 'PS', - 2: 'CS_NA', - 3: 'SPI_LB_WAVES_RSVD', -} -HS_GS = 0 -PS = 1 -CS_NA = 2 -SPI_LB_WAVES_RSVD = 3 -SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PERFCNT_SEL' -SPI_PERFCNT_SEL__enumvalues = { - 1: 'SPI_PERF_GS_WINDOW_VALID', - 2: 'SPI_PERF_GS_BUSY', - 3: 'SPI_PERF_GS_CRAWLER_STALL', - 4: 'SPI_PERF_GS_EVENT_WAVE', - 5: 'SPI_PERF_GS_WAVE', - 6: 'SPI_PERF_GS_PERS_UPD_FULL0', - 7: 'SPI_PERF_GS_PERS_UPD_FULL1', - 8: 'SPI_PERF_GS_FIRST_SUBGRP', - 9: 'SPI_PERF_GS_HS_DEALLOC', - 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 11: 'SPI_PERF_GS_POS0_STALL', - 12: 'SPI_PERF_GS_POS1_STALL', - 13: 'SPI_PERF_GS_INDX0_STALL', - 14: 'SPI_PERF_GS_INDX1_STALL', - 15: 'SPI_PERF_GS_PWS_STALL', - 16: 'SPI_PERF_GS_GRP_LIFETIME', - 17: 'SPI_PERF_GS_WAVE_IN_FLIGHT', - 18: 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE', - 21: 'SPI_PERF_HS_WINDOW_VALID', - 22: 'SPI_PERF_HS_BUSY', - 23: 'SPI_PERF_HS_CRAWLER_STALL', - 24: 'SPI_PERF_HS_FIRST_WAVE', - 26: 'SPI_PERF_HS_EVENT_WAVE', - 27: 'SPI_PERF_HS_WAVE', - 28: 'SPI_PERF_HS_PERS_UPD_FULL0', - 29: 'SPI_PERF_HS_PERS_UPD_FULL1', - 30: 'SPI_PERF_HS_PWS_STALL', - 31: 'SPI_PERF_HS_WAVE_IN_FLIGHT', - 37: 'SPI_PERF_CSGN_WINDOW_VALID', - 38: 'SPI_PERF_CSGN_BUSY', - 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', - 40: 'SPI_PERF_CSGN_CRAWLER_STALL', - 41: 'SPI_PERF_CSGN_EVENT_WAVE', - 42: 'SPI_PERF_CSGN_WAVE', - 43: 'SPI_PERF_CSGN_PWS_STALL', - 44: 'SPI_PERF_CSGN_WAVE_IN_FLIGHT', - 45: 'SPI_PERF_CSN_WINDOW_VALID', - 46: 'SPI_PERF_CSN_BUSY', - 47: 'SPI_PERF_CSN_NUM_THREADGROUPS', - 48: 'SPI_PERF_CSN_CRAWLER_STALL', - 49: 'SPI_PERF_CSN_EVENT_WAVE', - 50: 'SPI_PERF_CSN_WAVE', - 51: 'SPI_PERF_CSN_WAVE_IN_FLIGHT', - 53: 'SPI_PERF_PS0_WINDOW_VALID', - 54: 'SPI_PERF_PS1_WINDOW_VALID', - 55: 'SPI_PERF_PS2_WINDOW_VALID', - 56: 'SPI_PERF_PS3_WINDOW_VALID', - 57: 'SPI_PERF_PS0_BUSY', - 58: 'SPI_PERF_PS1_BUSY', - 59: 'SPI_PERF_PS2_BUSY', - 60: 'SPI_PERF_PS3_BUSY', - 61: 'SPI_PERF_PS0_ACTIVE', - 62: 'SPI_PERF_PS1_ACTIVE', - 63: 'SPI_PERF_PS2_ACTIVE', - 64: 'SPI_PERF_PS3_ACTIVE', - 65: 'SPI_PERF_PS0_DEALLOC', - 66: 'SPI_PERF_PS1_DEALLOC', - 67: 'SPI_PERF_PS2_DEALLOC', - 68: 'SPI_PERF_PS3_DEALLOC', - 69: 'SPI_PERF_PS0_EVENT_WAVE', - 70: 'SPI_PERF_PS1_EVENT_WAVE', - 71: 'SPI_PERF_PS2_EVENT_WAVE', - 72: 'SPI_PERF_PS3_EVENT_WAVE', - 73: 'SPI_PERF_PS0_WAVE', - 74: 'SPI_PERF_PS1_WAVE', - 75: 'SPI_PERF_PS2_WAVE', - 76: 'SPI_PERF_PS3_WAVE', - 77: 'SPI_PERF_PS0_OPT_WAVE', - 78: 'SPI_PERF_PS1_OPT_WAVE', - 79: 'SPI_PERF_PS2_OPT_WAVE', - 80: 'SPI_PERF_PS3_OPT_WAVE', - 81: 'SPI_PERF_PS0_PRIM_BIN0', - 82: 'SPI_PERF_PS1_PRIM_BIN0', - 83: 'SPI_PERF_PS2_PRIM_BIN0', - 84: 'SPI_PERF_PS3_PRIM_BIN0', - 85: 'SPI_PERF_PS0_PRIM_BIN1', - 86: 'SPI_PERF_PS1_PRIM_BIN1', - 87: 'SPI_PERF_PS2_PRIM_BIN1', - 88: 'SPI_PERF_PS3_PRIM_BIN1', - 89: 'SPI_PERF_PS0_CRAWLER_STALL', - 90: 'SPI_PERF_PS1_CRAWLER_STALL', - 91: 'SPI_PERF_PS2_CRAWLER_STALL', - 92: 'SPI_PERF_PS3_CRAWLER_STALL', - 93: 'SPI_PERF_PS_PERS_UPD_FULL0', - 94: 'SPI_PERF_PS_PERS_UPD_FULL1', - 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', - 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', - 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', - 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', - 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', - 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', - 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', - 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', - 107: 'SPI_PERF_PS_PWS_STALL', - 108: 'SPI_PERF_PS0_LDS_DONE_FULL', - 109: 'SPI_PERF_PS1_LDS_DONE_FULL', - 110: 'SPI_PERF_PS2_LDS_DONE_FULL', - 111: 'SPI_PERF_PS3_LDS_DONE_FULL', - 112: 'SPI_PERF_PS0_DEALLOC_FULL', - 113: 'SPI_PERF_PS1_DEALLOC_FULL', - 114: 'SPI_PERF_PS2_DEALLOC_FULL', - 115: 'SPI_PERF_PS3_DEALLOC_FULL', - 116: 'SPI_PERF_PS0_WAVE_IN_FLIGHT', - 117: 'SPI_PERF_PS1_WAVE_IN_FLIGHT', - 118: 'SPI_PERF_PS2_WAVE_IN_FLIGHT', - 119: 'SPI_PERF_PS3_WAVE_IN_FLIGHT', - 133: 'SPI_PERF_RA_GS_LDS_OCCUPANCY', - 134: 'SPI_PERF_RA_GS_VGPR_OCCUPANCY', - 135: 'SPI_PERF_RA_PS_LDS_OCCUPANCY', - 136: 'SPI_PERF_RA_PS_VGPR_OCCUPANCY', - 137: 'SPI_PERF_RA_SPI_THROTTLE', - 138: 'SPI_PERF_RA_PH_THROTTLE', - 139: 'SPI_PERF_RA_PC_PROBE_STALL_PS', - 140: 'SPI_PERF_RA_PC_PSWAVE_STALL_PS', - 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', - 142: 'SPI_PERF_RA_TASK_REQ_BIN3', - 143: 'SPI_PERF_RA_WR_CTL_FULL', - 144: 'SPI_PERF_RA_REQ_NO_ALLOC', - 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 150: 'SPI_PERF_RA_RES_STALL_PS', - 151: 'SPI_PERF_RA_RES_STALL_GS', - 152: 'SPI_PERF_RA_RES_STALL_HS', - 153: 'SPI_PERF_RA_RES_STALL_CSG', - 154: 'SPI_PERF_RA_RES_STALL_CSN', - 155: 'SPI_PERF_RA_TMP_STALL_PS', - 156: 'SPI_PERF_RA_TMP_STALL_GS', - 157: 'SPI_PERF_RA_TMP_STALL_HS', - 158: 'SPI_PERF_RA_TMP_STALL_CSG', - 159: 'SPI_PERF_RA_TMP_STALL_CSN', - 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', - 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', - 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', - 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', - 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', - 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', - 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 175: 'SPI_PERF_RA_BAR_CU_FULL_PS', - 176: 'SPI_PERF_RA_BAR_CU_FULL_GS', - 177: 'SPI_PERF_RA_BAR_CU_FULL_HS', - 178: 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 179: 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 180: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 181: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 182: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', - 183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 184: 'SPI_PERF_RA_WVLIM_STALL_PS', - 185: 'SPI_PERF_RA_WVLIM_STALL_GS', - 186: 'SPI_PERF_RA_WVLIM_STALL_HS', - 187: 'SPI_PERF_RA_WVLIM_STALL_CSG', - 188: 'SPI_PERF_RA_WVLIM_STALL_CSN', - 189: 'SPI_PERF_RA_GS_LOCK', - 190: 'SPI_PERF_RA_HS_LOCK', - 191: 'SPI_PERF_RA_CSG_LOCK', - 192: 'SPI_PERF_RA_CSN_LOCK', - 193: 'SPI_PERF_RA_RSV_UPD', - 194: 'SPI_PERF_RA_PRE_ALLOC_STALL', - 195: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 196: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', - 197: 'SPI_PERF_RA_WVALLOC_STALL', - 198: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 199: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 200: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 201: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', - 202: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 203: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 204: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 205: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 206: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 207: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 208: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 209: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 210: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 211: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 212: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 213: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 214: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 215: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 216: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 217: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 218: 'SPI_PERF_EXP_ARB_COL_CNT', - 219: 'SPI_PERF_EXP_ARB_POS_CNT', - 220: 'SPI_PERF_EXP_ARB_GDS_CNT', - 221: 'SPI_PERF_EXP_ARB_IDX_CNT', - 222: 'SPI_PERF_EXP_WITH_CONFLICT', - 223: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 224: 'SPI_PERF_GS_EXP_DONE', - 225: 'SPI_PERF_PS_EXP_DONE', - 226: 'SPI_PERF_PS_EXP_ARB_CONFLICT', - 227: 'SPI_PERF_GS_SCBD_IDX_CLEANUP', - 228: 'SPI_PERF_GS_SCBD_POS_CLEANUP', - 229: 'SPI_PERF_PS_EXP_ALLOC', - 230: 'SPI_PERF_PS0_WAVEID_STARVED', - 231: 'SPI_PERF_PS1_WAVEID_STARVED', - 232: 'SPI_PERF_PS2_WAVEID_STARVED', - 233: 'SPI_PERF_PS3_WAVEID_STARVED', - 234: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 235: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', - 236: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', - 237: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', - 238: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 239: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 240: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 241: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 242: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 243: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 244: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 245: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 246: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 247: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 248: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 249: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 250: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 251: 'SPI_PERF_GS_ALLOC_IDX', - 252: 'SPI_PERF_GS_ALLOC_POS', - 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 254: 'SPI_PERF_EXPORT_SCB0_STALL', - 255: 'SPI_PERF_EXPORT_SCB1_STALL', - 256: 'SPI_PERF_EXPORT_SCB2_STALL', - 257: 'SPI_PERF_EXPORT_SCB3_STALL', - 258: 'SPI_PERF_EXPORT_DB0_STALL', - 259: 'SPI_PERF_EXPORT_DB1_STALL', - 260: 'SPI_PERF_EXPORT_DB2_STALL', - 261: 'SPI_PERF_EXPORT_DB3_STALL', - 262: 'SPI_PERF_EXPORT_DB4_STALL', - 263: 'SPI_PERF_EXPORT_DB5_STALL', - 264: 'SPI_PERF_EXPORT_DB6_STALL', - 265: 'SPI_PERF_EXPORT_DB7_STALL', - 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', - 268: 'SPI_PERF_SWC_PS_WR', - 269: 'SPI_PERF_SWC_GS_WR', - 270: 'SPI_PERF_SWC_HS_WR', - 271: 'SPI_PERF_SWC_CSGN_WR', - 272: 'SPI_PERF_SWC_CSN_WR', - 273: 'SPI_PERF_VWC_PS_WR', - 274: 'SPI_PERF_VWC_ES_WR', - 275: 'SPI_PERF_VWC_GS_WR', - 276: 'SPI_PERF_VWC_LS_WR', - 277: 'SPI_PERF_VWC_HS_WR', - 278: 'SPI_PERF_VWC_CSGN_WR', - 279: 'SPI_PERF_VWC_CSN_WR', - 280: 'SPI_PERF_EXP_THROT_UPSTEP', - 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', - 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 283: 'SPI_PERF_BUSY', - 284: 'SPI_PERF_ALL_PS_WAVE', - 285: 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT', - 286: 'SPI_PERF_ALL_WAVE', - 287: 'SPI_PERF_ALL_WAVE_IN_FLIGHT', - 288: 'SPI_PERF_RA_REQ_ALLOC', - 289: 'SPI_PERF_VGPR_INIT', - 290: 'SPI_PERF_SGPR_INIT', - 291: 'SPI_PERF_VGPR_ALLOC_LEVEL', - 292: 'SPI_PERF_LDS_ALLOC_LEVEL', - 293: 'SPI_PERF_GFX_TEMP_ALLOC_LEVEL', - 294: 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL', - 295: 'SPI_PERF_CSN_TEMP_ALLOC_LEVEL', - 296: 'SPI_PERF_ALL_WAVE_RESTORED', - 297: 'SPI_PERF_ALL_WAVE_SAVED', - 298: 'SPI_PERF_ALL_WAVE_W32', - 299: 'SPI_PERF_ALL_WAVE_W64', - 300: 'SPI_PERF_ALL_WAVE_ITEMS', - 301: 'SPI_PERF_ALL_WAVE_ITEMS_W32', - 302: 'SPI_PERF_ALL_WAVE_ITEMS_W64', - 303: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL', - 304: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL', - 305: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL', - 306: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL', -} -SPI_PERF_GS_WINDOW_VALID = 1 -SPI_PERF_GS_BUSY = 2 -SPI_PERF_GS_CRAWLER_STALL = 3 -SPI_PERF_GS_EVENT_WAVE = 4 -SPI_PERF_GS_WAVE = 5 -SPI_PERF_GS_PERS_UPD_FULL0 = 6 -SPI_PERF_GS_PERS_UPD_FULL1 = 7 -SPI_PERF_GS_FIRST_SUBGRP = 8 -SPI_PERF_GS_HS_DEALLOC = 9 -SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 -SPI_PERF_GS_POS0_STALL = 11 -SPI_PERF_GS_POS1_STALL = 12 -SPI_PERF_GS_INDX0_STALL = 13 -SPI_PERF_GS_INDX1_STALL = 14 -SPI_PERF_GS_PWS_STALL = 15 -SPI_PERF_GS_GRP_LIFETIME = 16 -SPI_PERF_GS_WAVE_IN_FLIGHT = 17 -SPI_PERF_GS_GRP_LIFETIME_SAMPLE = 18 -SPI_PERF_HS_WINDOW_VALID = 21 -SPI_PERF_HS_BUSY = 22 -SPI_PERF_HS_CRAWLER_STALL = 23 -SPI_PERF_HS_FIRST_WAVE = 24 -SPI_PERF_HS_EVENT_WAVE = 26 -SPI_PERF_HS_WAVE = 27 -SPI_PERF_HS_PERS_UPD_FULL0 = 28 -SPI_PERF_HS_PERS_UPD_FULL1 = 29 -SPI_PERF_HS_PWS_STALL = 30 -SPI_PERF_HS_WAVE_IN_FLIGHT = 31 -SPI_PERF_CSGN_WINDOW_VALID = 37 -SPI_PERF_CSGN_BUSY = 38 -SPI_PERF_CSGN_NUM_THREADGROUPS = 39 -SPI_PERF_CSGN_CRAWLER_STALL = 40 -SPI_PERF_CSGN_EVENT_WAVE = 41 -SPI_PERF_CSGN_WAVE = 42 -SPI_PERF_CSGN_PWS_STALL = 43 -SPI_PERF_CSGN_WAVE_IN_FLIGHT = 44 -SPI_PERF_CSN_WINDOW_VALID = 45 -SPI_PERF_CSN_BUSY = 46 -SPI_PERF_CSN_NUM_THREADGROUPS = 47 -SPI_PERF_CSN_CRAWLER_STALL = 48 -SPI_PERF_CSN_EVENT_WAVE = 49 -SPI_PERF_CSN_WAVE = 50 -SPI_PERF_CSN_WAVE_IN_FLIGHT = 51 -SPI_PERF_PS0_WINDOW_VALID = 53 -SPI_PERF_PS1_WINDOW_VALID = 54 -SPI_PERF_PS2_WINDOW_VALID = 55 -SPI_PERF_PS3_WINDOW_VALID = 56 -SPI_PERF_PS0_BUSY = 57 -SPI_PERF_PS1_BUSY = 58 -SPI_PERF_PS2_BUSY = 59 -SPI_PERF_PS3_BUSY = 60 -SPI_PERF_PS0_ACTIVE = 61 -SPI_PERF_PS1_ACTIVE = 62 -SPI_PERF_PS2_ACTIVE = 63 -SPI_PERF_PS3_ACTIVE = 64 -SPI_PERF_PS0_DEALLOC = 65 -SPI_PERF_PS1_DEALLOC = 66 -SPI_PERF_PS2_DEALLOC = 67 -SPI_PERF_PS3_DEALLOC = 68 -SPI_PERF_PS0_EVENT_WAVE = 69 -SPI_PERF_PS1_EVENT_WAVE = 70 -SPI_PERF_PS2_EVENT_WAVE = 71 -SPI_PERF_PS3_EVENT_WAVE = 72 -SPI_PERF_PS0_WAVE = 73 -SPI_PERF_PS1_WAVE = 74 -SPI_PERF_PS2_WAVE = 75 -SPI_PERF_PS3_WAVE = 76 -SPI_PERF_PS0_OPT_WAVE = 77 -SPI_PERF_PS1_OPT_WAVE = 78 -SPI_PERF_PS2_OPT_WAVE = 79 -SPI_PERF_PS3_OPT_WAVE = 80 -SPI_PERF_PS0_PRIM_BIN0 = 81 -SPI_PERF_PS1_PRIM_BIN0 = 82 -SPI_PERF_PS2_PRIM_BIN0 = 83 -SPI_PERF_PS3_PRIM_BIN0 = 84 -SPI_PERF_PS0_PRIM_BIN1 = 85 -SPI_PERF_PS1_PRIM_BIN1 = 86 -SPI_PERF_PS2_PRIM_BIN1 = 87 -SPI_PERF_PS3_PRIM_BIN1 = 88 -SPI_PERF_PS0_CRAWLER_STALL = 89 -SPI_PERF_PS1_CRAWLER_STALL = 90 -SPI_PERF_PS2_CRAWLER_STALL = 91 -SPI_PERF_PS3_CRAWLER_STALL = 92 -SPI_PERF_PS_PERS_UPD_FULL0 = 93 -SPI_PERF_PS_PERS_UPD_FULL1 = 94 -SPI_PERF_PS0_2_WAVE_GROUPS = 95 -SPI_PERF_PS1_2_WAVE_GROUPS = 96 -SPI_PERF_PS2_2_WAVE_GROUPS = 97 -SPI_PERF_PS3_2_WAVE_GROUPS = 98 -SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 -SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 -SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 -SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 -SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 -SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 -SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 -SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 -SPI_PERF_PS_PWS_STALL = 107 -SPI_PERF_PS0_LDS_DONE_FULL = 108 -SPI_PERF_PS1_LDS_DONE_FULL = 109 -SPI_PERF_PS2_LDS_DONE_FULL = 110 -SPI_PERF_PS3_LDS_DONE_FULL = 111 -SPI_PERF_PS0_DEALLOC_FULL = 112 -SPI_PERF_PS1_DEALLOC_FULL = 113 -SPI_PERF_PS2_DEALLOC_FULL = 114 -SPI_PERF_PS3_DEALLOC_FULL = 115 -SPI_PERF_PS0_WAVE_IN_FLIGHT = 116 -SPI_PERF_PS1_WAVE_IN_FLIGHT = 117 -SPI_PERF_PS2_WAVE_IN_FLIGHT = 118 -SPI_PERF_PS3_WAVE_IN_FLIGHT = 119 -SPI_PERF_RA_GS_LDS_OCCUPANCY = 133 -SPI_PERF_RA_GS_VGPR_OCCUPANCY = 134 -SPI_PERF_RA_PS_LDS_OCCUPANCY = 135 -SPI_PERF_RA_PS_VGPR_OCCUPANCY = 136 -SPI_PERF_RA_SPI_THROTTLE = 137 -SPI_PERF_RA_PH_THROTTLE = 138 -SPI_PERF_RA_PC_PROBE_STALL_PS = 139 -SPI_PERF_RA_PC_PSWAVE_STALL_PS = 140 -SPI_PERF_RA_PIPE_REQ_BIN2 = 141 -SPI_PERF_RA_TASK_REQ_BIN3 = 142 -SPI_PERF_RA_WR_CTL_FULL = 143 -SPI_PERF_RA_REQ_NO_ALLOC = 144 -SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 -SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 -SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 -SPI_PERF_RA_RES_STALL_PS = 150 -SPI_PERF_RA_RES_STALL_GS = 151 -SPI_PERF_RA_RES_STALL_HS = 152 -SPI_PERF_RA_RES_STALL_CSG = 153 -SPI_PERF_RA_RES_STALL_CSN = 154 -SPI_PERF_RA_TMP_STALL_PS = 155 -SPI_PERF_RA_TMP_STALL_GS = 156 -SPI_PERF_RA_TMP_STALL_HS = 157 -SPI_PERF_RA_TMP_STALL_CSG = 158 -SPI_PERF_RA_TMP_STALL_CSN = 159 -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 -SPI_PERF_RA_LDS_CU_FULL_PS = 170 -SPI_PERF_RA_LDS_CU_FULL_HS = 171 -SPI_PERF_RA_LDS_CU_FULL_GS = 172 -SPI_PERF_RA_LDS_CU_FULL_CSG = 173 -SPI_PERF_RA_LDS_CU_FULL_CSN = 174 -SPI_PERF_RA_BAR_CU_FULL_PS = 175 -SPI_PERF_RA_BAR_CU_FULL_GS = 176 -SPI_PERF_RA_BAR_CU_FULL_HS = 177 -SPI_PERF_RA_BAR_CU_FULL_CSG = 178 -SPI_PERF_RA_BAR_CU_FULL_CSN = 179 -SPI_PERF_RA_BULKY_CU_FULL_CSG = 180 -SPI_PERF_RA_BULKY_CU_FULL_CSN = 181 -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 182 -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 183 -SPI_PERF_RA_WVLIM_STALL_PS = 184 -SPI_PERF_RA_WVLIM_STALL_GS = 185 -SPI_PERF_RA_WVLIM_STALL_HS = 186 -SPI_PERF_RA_WVLIM_STALL_CSG = 187 -SPI_PERF_RA_WVLIM_STALL_CSN = 188 -SPI_PERF_RA_GS_LOCK = 189 -SPI_PERF_RA_HS_LOCK = 190 -SPI_PERF_RA_CSG_LOCK = 191 -SPI_PERF_RA_CSN_LOCK = 192 -SPI_PERF_RA_RSV_UPD = 193 -SPI_PERF_RA_PRE_ALLOC_STALL = 194 -SPI_PERF_RA_GFX_UNDER_TUNNEL = 195 -SPI_PERF_RA_CSC_UNDER_TUNNEL = 196 -SPI_PERF_RA_WVALLOC_STALL = 197 -SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 198 -SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 199 -SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 200 -SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 201 -SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 202 -SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 203 -SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 204 -SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 205 -SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 206 -SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 207 -SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 208 -SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 209 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 210 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 211 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 212 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 213 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 214 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 215 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 216 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 217 -SPI_PERF_EXP_ARB_COL_CNT = 218 -SPI_PERF_EXP_ARB_POS_CNT = 219 -SPI_PERF_EXP_ARB_GDS_CNT = 220 -SPI_PERF_EXP_ARB_IDX_CNT = 221 -SPI_PERF_EXP_WITH_CONFLICT = 222 -SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 223 -SPI_PERF_GS_EXP_DONE = 224 -SPI_PERF_PS_EXP_DONE = 225 -SPI_PERF_PS_EXP_ARB_CONFLICT = 226 -SPI_PERF_GS_SCBD_IDX_CLEANUP = 227 -SPI_PERF_GS_SCBD_POS_CLEANUP = 228 -SPI_PERF_PS_EXP_ALLOC = 229 -SPI_PERF_PS0_WAVEID_STARVED = 230 -SPI_PERF_PS1_WAVEID_STARVED = 231 -SPI_PERF_PS2_WAVEID_STARVED = 232 -SPI_PERF_PS3_WAVEID_STARVED = 233 -SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 234 -SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 235 -SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 236 -SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 237 -SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 238 -SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 239 -SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 240 -SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 241 -SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 242 -SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 243 -SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 244 -SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 245 -SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 246 -SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 247 -SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 248 -SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 249 -SPI_PERF_NUM_EXPGRANT_EXPORTS = 250 -SPI_PERF_GS_ALLOC_IDX = 251 -SPI_PERF_GS_ALLOC_POS = 252 -SPI_PERF_PIX_ALLOC_PEND_CNT = 253 -SPI_PERF_EXPORT_SCB0_STALL = 254 -SPI_PERF_EXPORT_SCB1_STALL = 255 -SPI_PERF_EXPORT_SCB2_STALL = 256 -SPI_PERF_EXPORT_SCB3_STALL = 257 -SPI_PERF_EXPORT_DB0_STALL = 258 -SPI_PERF_EXPORT_DB1_STALL = 259 -SPI_PERF_EXPORT_DB2_STALL = 260 -SPI_PERF_EXPORT_DB3_STALL = 261 -SPI_PERF_EXPORT_DB4_STALL = 262 -SPI_PERF_EXPORT_DB5_STALL = 263 -SPI_PERF_EXPORT_DB6_STALL = 264 -SPI_PERF_EXPORT_DB7_STALL = 265 -SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 -SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 -SPI_PERF_SWC_PS_WR = 268 -SPI_PERF_SWC_GS_WR = 269 -SPI_PERF_SWC_HS_WR = 270 -SPI_PERF_SWC_CSGN_WR = 271 -SPI_PERF_SWC_CSN_WR = 272 -SPI_PERF_VWC_PS_WR = 273 -SPI_PERF_VWC_ES_WR = 274 -SPI_PERF_VWC_GS_WR = 275 -SPI_PERF_VWC_LS_WR = 276 -SPI_PERF_VWC_HS_WR = 277 -SPI_PERF_VWC_CSGN_WR = 278 -SPI_PERF_VWC_CSN_WR = 279 -SPI_PERF_EXP_THROT_UPSTEP = 280 -SPI_PERF_EXP_THROT_DOWNSTEP = 281 -SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 -SPI_PERF_BUSY = 283 -SPI_PERF_ALL_PS_WAVE = 284 -SPI_PERF_ALL_PS_WAVE_IN_FLIGHT = 285 -SPI_PERF_ALL_WAVE = 286 -SPI_PERF_ALL_WAVE_IN_FLIGHT = 287 -SPI_PERF_RA_REQ_ALLOC = 288 -SPI_PERF_VGPR_INIT = 289 -SPI_PERF_SGPR_INIT = 290 -SPI_PERF_VGPR_ALLOC_LEVEL = 291 -SPI_PERF_LDS_ALLOC_LEVEL = 292 -SPI_PERF_GFX_TEMP_ALLOC_LEVEL = 293 -SPI_PERF_CSG_TEMP_ALLOC_LEVEL = 294 -SPI_PERF_CSN_TEMP_ALLOC_LEVEL = 295 -SPI_PERF_ALL_WAVE_RESTORED = 296 -SPI_PERF_ALL_WAVE_SAVED = 297 -SPI_PERF_ALL_WAVE_W32 = 298 -SPI_PERF_ALL_WAVE_W64 = 299 -SPI_PERF_ALL_WAVE_ITEMS = 300 -SPI_PERF_ALL_WAVE_ITEMS_W32 = 301 -SPI_PERF_ALL_WAVE_ITEMS_W64 = 302 -SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL = 303 -SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL = 304 -SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL = 305 -SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL = 306 -SPI_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' -SPI_PNT_SPRITE_OVERRIDE__enumvalues = { - 0: 'SPI_PNT_SPRITE_SEL_0', - 1: 'SPI_PNT_SPRITE_SEL_1', - 2: 'SPI_PNT_SPRITE_SEL_S', - 3: 'SPI_PNT_SPRITE_SEL_T', - 4: 'SPI_PNT_SPRITE_SEL_NONE', -} -SPI_PNT_SPRITE_SEL_0 = 0 -SPI_PNT_SPRITE_SEL_1 = 1 -SPI_PNT_SPRITE_SEL_S = 2 -SPI_PNT_SPRITE_SEL_T = 3 -SPI_PNT_SPRITE_SEL_NONE = 4 -SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' -SPI_PS_LDS_GROUP_SIZE__enumvalues = { - 0: 'SPI_PS_LDS_GROUP_1', - 1: 'SPI_PS_LDS_GROUP_2', - 2: 'SPI_PS_LDS_GROUP_4', -} -SPI_PS_LDS_GROUP_1 = 0 -SPI_PS_LDS_GROUP_2 = 1 -SPI_PS_LDS_GROUP_4 = 2 -SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SAMPLE_CNTL' -SPI_SAMPLE_CNTL__enumvalues = { - 0: 'CENTROIDS_ONLY', - 1: 'CENTERS_ONLY', - 2: 'CENTROIDS_AND_CENTERS', - 3: 'UNDEF', -} -CENTROIDS_ONLY = 0 -CENTERS_ONLY = 1 -CENTROIDS_AND_CENTERS = 2 -UNDEF = 3 -SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_EX_FORMAT' -SPI_SHADER_EX_FORMAT__enumvalues = { - 0: 'SPI_SHADER_ZERO', - 1: 'SPI_SHADER_32_R', - 2: 'SPI_SHADER_32_GR', - 3: 'SPI_SHADER_32_AR', - 4: 'SPI_SHADER_FP16_ABGR', - 5: 'SPI_SHADER_UNORM16_ABGR', - 6: 'SPI_SHADER_SNORM16_ABGR', - 7: 'SPI_SHADER_UINT16_ABGR', - 8: 'SPI_SHADER_SINT16_ABGR', - 9: 'SPI_SHADER_32_ABGR', -} -SPI_SHADER_ZERO = 0 -SPI_SHADER_32_R = 1 -SPI_SHADER_32_GR = 2 -SPI_SHADER_32_AR = 3 -SPI_SHADER_FP16_ABGR = 4 -SPI_SHADER_UNORM16_ABGR = 5 -SPI_SHADER_SNORM16_ABGR = 6 -SPI_SHADER_UINT16_ABGR = 7 -SPI_SHADER_SINT16_ABGR = 8 -SPI_SHADER_32_ABGR = 9 -SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_FORMAT' -SPI_SHADER_FORMAT__enumvalues = { - 0: 'SPI_SHADER_NONE', - 1: 'SPI_SHADER_1COMP', - 2: 'SPI_SHADER_2COMP', - 3: 'SPI_SHADER_4COMPRESS', - 4: 'SPI_SHADER_4COMP', -} -SPI_SHADER_NONE = 0 -SPI_SHADER_1COMP = 1 -SPI_SHADER_2COMP = 2 -SPI_SHADER_4COMPRESS = 3 -SPI_SHADER_4COMP = 4 -SPI_SHADER_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ADDRESS_MODE' -SH_MEM_ADDRESS_MODE__enumvalues = { - 0: 'SH_MEM_ADDRESS_MODE_64', - 1: 'SH_MEM_ADDRESS_MODE_32', -} -SH_MEM_ADDRESS_MODE_64 = 0 -SH_MEM_ADDRESS_MODE_32 = 1 -SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ALIGNMENT_MODE' -SH_MEM_ALIGNMENT_MODE__enumvalues = { - 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', - 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', - 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', -} -SH_MEM_ALIGNMENT_MODE_DWORD = 0 -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 -SH_MEM_ALIGNMENT_MODE_STRICT = 2 -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 -SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQG_PERF_SEL' -SQG_PERF_SEL__enumvalues = { - 0: 'SQG_PERF_SEL_NONE', - 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', - 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', - 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', - 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 6: 'SQG_PERF_SEL_TTRACE_WRITE_DATA', - 7: 'SQG_PERF_SEL_TTRACE_STALL', - 8: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', - 9: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', - 10: 'SQG_PERF_SEL_EVENTS', - 11: 'SQG_PERF_SEL_WAVES_RESTORED', - 12: 'SQG_PERF_SEL_WAVES_SAVED', - 13: 'SQG_PERF_SEL_ACCUM_PREV', - 14: 'SQG_PERF_SEL_CYCLES', - 15: 'SQG_PERF_SEL_BUSY_CYCLES', - 16: 'SQG_PERF_SEL_WAVE_CYCLES', - 17: 'SQG_PERF_SEL_MSG', - 18: 'SQG_PERF_SEL_MSG_INTERRUPT', - 19: 'SQG_PERF_SEL_WAVES', - 20: 'SQG_PERF_SEL_WAVES_32', - 21: 'SQG_PERF_SEL_WAVES_64', - 22: 'SQG_PERF_SEL_LEVEL_WAVES', - 23: 'SQG_PERF_SEL_ITEMS', - 24: 'SQG_PERF_SEL_WAVE32_ITEMS', - 25: 'SQG_PERF_SEL_WAVE64_ITEMS', - 26: 'SQG_PERF_SEL_PS_QUADS', - 27: 'SQG_PERF_SEL_WAVES_EQ_64', - 28: 'SQG_PERF_SEL_WAVES_EQ_32', - 29: 'SQG_PERF_SEL_WAVES_LT_64', - 30: 'SQG_PERF_SEL_WAVES_LT_48', - 31: 'SQG_PERF_SEL_WAVES_LT_32', - 32: 'SQG_PERF_SEL_WAVES_LT_16', - 33: 'SQG_PERF_SEL_REFCLKS', - 34: 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER', - 35: 'SQG_PERF_SEL_WAVES_DYN_VGPR', - 36: 'SQG_PERF_SEL_ITEMS_PS', - 37: 'SQG_PERF_SEL_ITEMS_GS', - 38: 'SQG_PERF_SEL_ITEMS_HS', - 39: 'SQG_PERF_SEL_ITEMS_CS', - 40: 'SQG_PERF_SEL_WAVES_VEC32', - 41: 'SQG_PERF_SEL_WAVES_PS_VEC32', - 42: 'SQG_PERF_SEL_WAVES_GS_VEC32', - 43: 'SQG_PERF_SEL_WAVES_HS_VEC32', - 44: 'SQG_PERF_SEL_WAVES_CS_VEC32', - 45: 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE', - 46: 'SQG_PERF_SEL_DUMMY_LAST', -} -SQG_PERF_SEL_NONE = 0 -SQG_PERF_SEL_MSG_BUS_BUSY = 1 -SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 -SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 -SQG_PERF_SEL_EXP_BUS0_BUSY = 4 -SQG_PERF_SEL_EXP_BUS1_BUSY = 5 -SQG_PERF_SEL_TTRACE_WRITE_DATA = 6 -SQG_PERF_SEL_TTRACE_STALL = 7 -SQG_PERF_SEL_TTRACE_LOST_PACKETS = 8 -SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 9 -SQG_PERF_SEL_EVENTS = 10 -SQG_PERF_SEL_WAVES_RESTORED = 11 -SQG_PERF_SEL_WAVES_SAVED = 12 -SQG_PERF_SEL_ACCUM_PREV = 13 -SQG_PERF_SEL_CYCLES = 14 -SQG_PERF_SEL_BUSY_CYCLES = 15 -SQG_PERF_SEL_WAVE_CYCLES = 16 -SQG_PERF_SEL_MSG = 17 -SQG_PERF_SEL_MSG_INTERRUPT = 18 -SQG_PERF_SEL_WAVES = 19 -SQG_PERF_SEL_WAVES_32 = 20 -SQG_PERF_SEL_WAVES_64 = 21 -SQG_PERF_SEL_LEVEL_WAVES = 22 -SQG_PERF_SEL_ITEMS = 23 -SQG_PERF_SEL_WAVE32_ITEMS = 24 -SQG_PERF_SEL_WAVE64_ITEMS = 25 -SQG_PERF_SEL_PS_QUADS = 26 -SQG_PERF_SEL_WAVES_EQ_64 = 27 -SQG_PERF_SEL_WAVES_EQ_32 = 28 -SQG_PERF_SEL_WAVES_LT_64 = 29 -SQG_PERF_SEL_WAVES_LT_48 = 30 -SQG_PERF_SEL_WAVES_LT_32 = 31 -SQG_PERF_SEL_WAVES_LT_16 = 32 -SQG_PERF_SEL_REFCLKS = 33 -SQG_PERF_SEL_WAVES_WGP_TAKEOVER = 34 -SQG_PERF_SEL_WAVES_DYN_VGPR = 35 -SQG_PERF_SEL_ITEMS_PS = 36 -SQG_PERF_SEL_ITEMS_GS = 37 -SQG_PERF_SEL_ITEMS_HS = 38 -SQG_PERF_SEL_ITEMS_CS = 39 -SQG_PERF_SEL_WAVES_VEC32 = 40 -SQG_PERF_SEL_WAVES_PS_VEC32 = 41 -SQG_PERF_SEL_WAVES_GS_VEC32 = 42 -SQG_PERF_SEL_WAVES_HS_VEC32 = 43 -SQG_PERF_SEL_WAVES_CS_VEC32 = 44 -SQG_PERF_SEL_LEVEL_WGP_ACTIVE = 45 -SQG_PERF_SEL_DUMMY_LAST = 46 -SQG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_CAC_POWER_SEL' -SQ_CAC_POWER_SEL__enumvalues = { - 0: 'SQ_CAC_POWER_VALU', - 1: 'SQ_CAC_POWER_VALU0', - 2: 'SQ_CAC_POWER_VALU1', - 3: 'SQ_CAC_POWER_VALU2', - 4: 'SQ_CAC_POWER_GPR_RD', - 5: 'SQ_CAC_POWER_GPR_WR', - 6: 'SQ_CAC_POWER_LDS_BUSY', - 7: 'SQ_CAC_POWER_ALU_BUSY', - 8: 'SQ_CAC_POWER_TEX_BUSY', -} -SQ_CAC_POWER_VALU = 0 -SQ_CAC_POWER_VALU0 = 1 -SQ_CAC_POWER_VALU1 = 2 -SQ_CAC_POWER_VALU2 = 3 -SQ_CAC_POWER_GPR_RD = 4 -SQ_CAC_POWER_GPR_WR = 5 -SQ_CAC_POWER_LDS_BUSY = 6 -SQ_CAC_POWER_ALU_BUSY = 7 -SQ_CAC_POWER_TEX_BUSY = 8 -SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_EDC_INFO_SOURCE' -SQ_EDC_INFO_SOURCE__enumvalues = { - 0: 'SQ_EDC_INFO_SOURCE_INVALID', - 1: 'SQ_EDC_INFO_SOURCE_INST', - 2: 'SQ_EDC_INFO_SOURCE_SGPR', - 3: 'SQ_EDC_INFO_SOURCE_VGPR', - 4: 'SQ_EDC_INFO_SOURCE_LDS', - 5: 'SQ_EDC_INFO_SOURCE_GDS', - 6: 'SQ_EDC_INFO_SOURCE_TA', -} -SQ_EDC_INFO_SOURCE_INVALID = 0 -SQ_EDC_INFO_SOURCE_INST = 1 -SQ_EDC_INFO_SOURCE_SGPR = 2 -SQ_EDC_INFO_SOURCE_VGPR = 3 -SQ_EDC_INFO_SOURCE_LDS = 4 -SQ_EDC_INFO_SOURCE_GDS = 5 -SQ_EDC_INFO_SOURCE_TA = 6 -SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IBUF_ST' -SQ_IBUF_ST__enumvalues = { - 0: 'SQ_IBUF_IB_IDLE', - 1: 'SQ_IBUF_IB_INI_WAIT_GNT', - 2: 'SQ_IBUF_IB_INI_WAIT_DRET', - 3: 'SQ_IBUF_IB_LE_4DW', - 4: 'SQ_IBUF_IB_WAIT_DRET', - 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 6: 'SQ_IBUF_IB_DRET', - 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', -} -SQ_IBUF_IB_IDLE = 0 -SQ_IBUF_IB_INI_WAIT_GNT = 1 -SQ_IBUF_IB_INI_WAIT_DRET = 2 -SQ_IBUF_IB_LE_4DW = 3 -SQ_IBUF_IB_WAIT_DRET = 4 -SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 -SQ_IBUF_IB_DRET = 6 -SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 -SQ_IBUF_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IMG_FILTER_TYPE' -SQ_IMG_FILTER_TYPE__enumvalues = { - 0: 'SQ_IMG_FILTER_MODE_BLEND', - 1: 'SQ_IMG_FILTER_MODE_MIN', - 2: 'SQ_IMG_FILTER_MODE_MAX', -} -SQ_IMG_FILTER_MODE_BLEND = 0 -SQ_IMG_FILTER_MODE_MIN = 1 -SQ_IMG_FILTER_MODE_MAX = 2 -SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_CMD' -SQ_IND_CMD_CMD__enumvalues = { - 0: 'SQ_IND_CMD_CMD_NULL', - 1: 'SQ_IND_CMD_CMD_SETHALT', - 2: 'SQ_IND_CMD_CMD_SAVECTX', - 3: 'SQ_IND_CMD_CMD_KILL', - 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', - 5: 'SQ_IND_CMD_CMD_TRAP', - 6: 'SQ_IND_CMD_CMD_SET_SYS_PRIO', - 7: 'SQ_IND_CMD_CMD_SETFATALHALT', - 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', -} -SQ_IND_CMD_CMD_NULL = 0 -SQ_IND_CMD_CMD_SETHALT = 1 -SQ_IND_CMD_CMD_SAVECTX = 2 -SQ_IND_CMD_CMD_KILL = 3 -SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 -SQ_IND_CMD_CMD_TRAP = 5 -SQ_IND_CMD_CMD_SET_SYS_PRIO = 6 -SQ_IND_CMD_CMD_SETFATALHALT = 7 -SQ_IND_CMD_CMD_SINGLE_STEP = 8 -SQ_IND_CMD_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_MODE' -SQ_IND_CMD_MODE__enumvalues = { - 0: 'SQ_IND_CMD_MODE_SINGLE', - 1: 'SQ_IND_CMD_MODE_BROADCAST', - 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', - 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', -} -SQ_IND_CMD_MODE_SINGLE = 0 -SQ_IND_CMD_MODE_BROADCAST = 1 -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 -SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 -SQ_IND_CMD_MODE_BROADCAST_ME = 4 -SQ_IND_CMD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_STR_ST' -SQ_INST_STR_ST__enumvalues = { - 0: 'SQ_INST_STR_IB_WAVE_NORML', - 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', - 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', -} -SQ_INST_STR_IB_WAVE_NORML = 0 -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 -SQ_INST_STR_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_TYPE' -SQ_INST_TYPE__enumvalues = { - 0: 'SQ_INST_TYPE_VALU', - 1: 'SQ_INST_TYPE_SCALAR', - 2: 'SQ_INST_TYPE_TEX', - 3: 'SQ_INST_TYPE_LDS', - 4: 'SQ_INST_TYPE_LDS_DIRECT', - 5: 'SQ_INST_TYPE_EXP', - 6: 'SQ_INST_TYPE_MSG', - 7: 'SQ_INST_TYPE_BARRIER', - 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', - 9: 'SQ_INST_TYPE_BRANCH_TAKEN', - 10: 'SQ_INST_TYPE_JUMP', - 11: 'SQ_INST_TYPE_OTHER', - 12: 'SQ_INST_TYPE_NONE', - 13: 'SQ_INST_TYPE_DUAL_VALU', - 14: 'SQ_INST_TYPE_FLAT', - 15: 'SQ_INST_TYPE_VALU_MATRIX', -} -SQ_INST_TYPE_VALU = 0 -SQ_INST_TYPE_SCALAR = 1 -SQ_INST_TYPE_TEX = 2 -SQ_INST_TYPE_LDS = 3 -SQ_INST_TYPE_LDS_DIRECT = 4 -SQ_INST_TYPE_EXP = 5 -SQ_INST_TYPE_MSG = 6 -SQ_INST_TYPE_BARRIER = 7 -SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 -SQ_INST_TYPE_BRANCH_TAKEN = 9 -SQ_INST_TYPE_JUMP = 10 -SQ_INST_TYPE_OTHER = 11 -SQ_INST_TYPE_NONE = 12 -SQ_INST_TYPE_DUAL_VALU = 13 -SQ_INST_TYPE_FLAT = 14 -SQ_INST_TYPE_VALU_MATRIX = 15 -SQ_INST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_LLC_CTL' -SQ_LLC_CTL__enumvalues = { - 0: 'SQ_LLC_0', - 1: 'SQ_LLC_1', - 2: 'SQ_LLC_RSVD_2', - 3: 'SQ_LLC_BYPASS', -} -SQ_LLC_0 = 0 -SQ_LLC_1 = 1 -SQ_LLC_RSVD_2 = 2 -SQ_LLC_BYPASS = 3 -SQ_LLC_CTL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_NO_INST_ISSUE' -SQ_NO_INST_ISSUE__enumvalues = { - 0: 'SQ_NO_INST_ISSUE_NO_INSTS', - 1: 'SQ_NO_INST_ISSUE_ALU_DEP', - 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', - 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', - 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', - 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', - 6: 'SQ_NO_INST_ISSUE_OTHER', - 7: 'SQ_NO_INST_ISSUE_INTERNAL', -} -SQ_NO_INST_ISSUE_NO_INSTS = 0 -SQ_NO_INST_ISSUE_ALU_DEP = 1 -SQ_NO_INST_ISSUE_S_WAITCNT = 2 -SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 -SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 -SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 -SQ_NO_INST_ISSUE_OTHER = 6 -SQ_NO_INST_ISSUE_INTERNAL = 7 -SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_OOB_SELECT' -SQ_OOB_SELECT__enumvalues = { - 0: 'SQ_OOB_INDEX_AND_OFFSET', - 1: 'SQ_OOB_INDEX_ONLY', - 2: 'SQ_OOB_NUM_RECORDS_0', - 3: 'SQ_OOB_COMPLETE', -} -SQ_OOB_INDEX_AND_OFFSET = 0 -SQ_OOB_INDEX_ONLY = 1 -SQ_OOB_NUM_RECORDS_0 = 2 -SQ_OOB_COMPLETE = 3 -SQ_OOB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_PERF_SEL' -SQ_PERF_SEL__enumvalues = { - 0: 'SQ_PERF_SEL_NONE', - 1: 'SQ_PERF_SEL_ACCUM_PREV', - 2: 'SQ_PERF_SEL_CYCLES', - 3: 'SQ_PERF_SEL_BUSY_CYCLES', - 4: 'SQ_PERF_SEL_WAVES', - 5: 'SQ_PERF_SEL_WAVES_32', - 6: 'SQ_PERF_SEL_WAVES_64', - 7: 'SQ_PERF_SEL_LEVEL_WAVES', - 8: 'SQ_PERF_SEL_ITEMS', - 9: 'SQ_PERF_SEL_WAVE32_ITEMS', - 10: 'SQ_PERF_SEL_WAVE64_ITEMS', - 11: 'SQ_PERF_SEL_PS_QUADS', - 12: 'SQ_PERF_SEL_EVENTS', - 13: 'SQ_PERF_SEL_WAVES_EQ_32', - 14: 'SQ_PERF_SEL_WAVES_EQ_64', - 15: 'SQ_PERF_SEL_WAVES_LT_64', - 16: 'SQ_PERF_SEL_WAVES_LT_48', - 17: 'SQ_PERF_SEL_WAVES_LT_32', - 18: 'SQ_PERF_SEL_WAVES_LT_16', - 19: 'SQ_PERF_SEL_WAVES_RESTORED', - 20: 'SQ_PERF_SEL_WAVES_SAVED', - 21: 'SQ_PERF_SEL_MSG', - 22: 'SQ_PERF_SEL_MSG_INTERRUPT', - 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 24: 'SQ_PERF_SEL_WAVE_CYCLES', - 25: 'SQ_PERF_SEL_WAVE_READY', - 26: 'SQ_PERF_SEL_WAIT_INST_ANY', - 27: 'SQ_PERF_SEL_WAIT_ANY', - 28: 'SQ_PERF_SEL_WAIT_CNT_ANY', - 29: 'SQ_PERF_SEL_WAIT_CNT_LOAD', - 30: 'SQ_PERF_SEL_WAIT_CNT_STORE', - 31: 'SQ_PERF_SEL_WAIT_TTRACE', - 32: 'SQ_PERF_SEL_WAIT_IFETCH', - 33: 'SQ_PERF_SEL_WAIT_BARRIER', - 34: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 35: 'SQ_PERF_SEL_WAIT_SLEEP', - 36: 'SQ_PERF_SEL_WAIT_DELAY_ALU', - 37: 'SQ_PERF_SEL_WAIT_DEPCTR', - 38: 'SQ_PERF_SEL_WAIT_OTHER', - 39: 'SQ_PERF_SEL_INSTS_ALL', - 40: 'SQ_PERF_SEL_INSTS_BRANCH', - 41: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 42: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 43: 'SQ_PERF_SEL_INSTS_EXP', - 44: 'SQ_PERF_SEL_INSTS_FLAT', - 45: 'SQ_PERF_SEL_INSTS_LDS', - 46: 'SQ_PERF_SEL_INSTS_SALU', - 47: 'SQ_PERF_SEL_INSTS_SMEM', - 48: 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 49: 'SQ_PERF_SEL_INSTS_SENDMSG', - 50: 'SQ_PERF_SEL_INSTS_VALU', - 51: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 52: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 53: 'SQ_PERF_SEL_INSTS_TEX', - 54: 'SQ_PERF_SEL_INSTS_TEX_LOAD', - 55: 'SQ_PERF_SEL_INSTS_TEX_STORE', - 56: 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 57: 'SQ_PERF_SEL_INSTS_INTERNAL', - 58: 'SQ_PERF_SEL_INSTS_VEC32', - 59: 'SQ_PERF_SEL_INSTS_VEC32_FLAT', - 60: 'SQ_PERF_SEL_INSTS_VEC32_LDS', - 61: 'SQ_PERF_SEL_INSTS_VEC32_VALU', - 62: 'SQ_PERF_SEL_VEC32_INSTS_EXP', - 63: 'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32', - 64: 'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC', - 65: 'SQ_PERF_SEL_INSTS_VEC32_TEX', - 66: 'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD', - 67: 'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE', - 68: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 69: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 70: 'SQ_PERF_SEL_WAVE32_INSTS', - 71: 'SQ_PERF_SEL_WAVE64_INSTS', - 72: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 73: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 74: 'SQ_PERF_SEL_INST_LEVEL_EXP', - 75: 'SQ_PERF_SEL_INST_LEVEL_LDS', - 76: 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 77: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 78: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', - 79: 'SQ_PERF_SEL_IFETCH_REQS', - 80: 'SQ_PERF_SEL_IFETCH_LEVEL', - 81: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 82: 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 83: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 84: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 85: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 86: 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 87: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 88: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 89: 'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL', - 90: 'SQ_PERF_SEL_INST_ISSUE_ALL_STALL', - 91: 'SQ_PERF_SEL_INST_ISSUE_VALU_STALL', - 92: 'SQ_PERF_SEL_INST_ISSUE_SALU_STALL', - 93: 'SQ_PERF_SEL_INST_ISSUE_TEX_STALL', - 94: 'SQ_PERF_SEL_INST_ISSUE_LDS_STALL', - 96: 'SQ_PERF_SEL_INST_ISSUE_EXP_STALL', - 97: 'SQ_PERF_SEL_INST_WAITCNT_STALL', - 98: 'SQ_PERF_SEL_INST_BARRIER_STALL', - 99: 'SQ_PERF_SEL_INST_CYCLES_VALU', - 100: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 101: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 102: 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 103: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 104: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 105: 'SQ_PERF_SEL_INST_CYCLES_LDS', - 106: 'SQ_PERF_SEL_INST_CYCLES_TEX', - 107: 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 108: 'SQ_PERF_SEL_INST_CYCLES_EXP', - 109: 'SQ_PERF_SEL_VALU_STARVE', - 110: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 111: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 112: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 113: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 114: 'SQ_PERF_SEL_VMEM_BUS_STALL', - 115: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 116: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 117: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 118: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 119: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 120: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 121: 'SQ_PERF_SEL_SALU_PIPE_STALL', - 122: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 123: 'SQ_PERF_SEL_MSG_BUS_BUSY', - 124: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', - 125: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', - 126: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 127: 'SQ_PERF_SEL_EXP_BUS0_BUSY', - 128: 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 129: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', - 130: 'SQ_PERF_SEL_USER0', - 131: 'SQ_PERF_SEL_USER1', - 132: 'SQ_PERF_SEL_USER2', - 133: 'SQ_PERF_SEL_USER3', - 134: 'SQ_PERF_SEL_USER4', - 135: 'SQ_PERF_SEL_USER5', - 136: 'SQ_PERF_SEL_USER6', - 137: 'SQ_PERF_SEL_USER7', - 138: 'SQ_PERF_SEL_USER8', - 139: 'SQ_PERF_SEL_USER9', - 140: 'SQ_PERF_SEL_USER10', - 141: 'SQ_PERF_SEL_USER11', - 142: 'SQ_PERF_SEL_USER12', - 143: 'SQ_PERF_SEL_USER13', - 144: 'SQ_PERF_SEL_USER14', - 145: 'SQ_PERF_SEL_USER15', - 146: 'SQ_PERF_SEL_USER_LEVEL0', - 147: 'SQ_PERF_SEL_USER_LEVEL1', - 148: 'SQ_PERF_SEL_USER_LEVEL2', - 149: 'SQ_PERF_SEL_USER_LEVEL3', - 150: 'SQ_PERF_SEL_USER_LEVEL4', - 151: 'SQ_PERF_SEL_USER_LEVEL5', - 152: 'SQ_PERF_SEL_USER_LEVEL6', - 153: 'SQ_PERF_SEL_USER_LEVEL7', - 154: 'SQ_PERF_SEL_USER_LEVEL8', - 155: 'SQ_PERF_SEL_USER_LEVEL9', - 156: 'SQ_PERF_SEL_USER_LEVEL10', - 157: 'SQ_PERF_SEL_USER_LEVEL11', - 158: 'SQ_PERF_SEL_USER_LEVEL12', - 159: 'SQ_PERF_SEL_USER_LEVEL13', - 160: 'SQ_PERF_SEL_USER_LEVEL14', - 161: 'SQ_PERF_SEL_USER_LEVEL15', - 162: 'SQ_PERF_SEL_VALU_RETURN_SDST', - 163: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 164: 'SQ_PERF_SEL_INSTS_VALU_TRANS', - 165: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 166: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', - 167: 'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD', - 168: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 169: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', - 170: 'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP', - 171: 'SQ_PERF_SEL_OVERFLOW_PREV', - 172: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', - 173: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 174: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', - 175: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 176: 'SQ_PERF_SEL_INSTS_VALU_DP', - 177: 'SQ_PERF_SEL_SP_CONST_CYCLES', - 178: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', - 179: 'SQ_PERF_SEL_ITEMS_VALU', - 180: 'SQ_PERF_SEL_ITEMS_MAX_VALU', - 181: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 182: 'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE', - 183: 'SQ_PERF_SEL_INSTS_FLAT_LOAD', - 184: 'SQ_PERF_SEL_INSTS_FLAT_STORE', - 185: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT', - 186: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT', - 187: 'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED', - 188: 'SQ_PERF_SEL_INSTS_BARRIER_LOCK', - 189: 'SQ_PERF_SEL_INSTS_WAKEUP', - 190: 'SQ_PERF_SEL_IS_CACHE_REQ', - 191: 'SQ_PERF_SEL_INSTS_SALU_PS', - 192: 'SQ_PERF_SEL_INSTS_SALU_GS', - 193: 'SQ_PERF_SEL_INSTS_SALU_HS', - 194: 'SQ_PERF_SEL_INSTS_SALU_CS', - 195: 'SQ_PERF_SEL_INSTS_SMEM_PS', - 196: 'SQ_PERF_SEL_INSTS_SMEM_GS', - 197: 'SQ_PERF_SEL_INSTS_SMEM_HS', - 198: 'SQ_PERF_SEL_INSTS_SMEM_CS', - 199: 'SQ_PERF_SEL_INSTS_VEC32_TEX_PS', - 200: 'SQ_PERF_SEL_INSTS_VEC32_TEX_GS', - 201: 'SQ_PERF_SEL_INSTS_VEC32_TEX_HS', - 202: 'SQ_PERF_SEL_INSTS_VEC32_TEX_CS', - 203: 'SQ_PERF_SEL_INSTS_VEC32_VALU_PS', - 204: 'SQ_PERF_SEL_INSTS_VEC32_VALU_GS', - 205: 'SQ_PERF_SEL_INSTS_VEC32_VALU_HS', - 206: 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS', - 207: 'SQ_PERF_SEL_WAIT_CNT_SAMPLE', - 209: 'SQ_PERF_SEL_WAIT_CNT_KM', - 210: 'SQ_PERF_SEL_WAIT_CNT_DS', - 211: 'SQ_PERF_SEL_WAIT_CNT_EXP', - 212: 'SQ_PERF_SEL_INSTS_SALU_FLOAT', - 213: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC', - 214: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL', - 215: 'SQ_PERF_SEL_INSTS_LOCK', - 216: 'SQ_PERF_SEL_INSTS_VALU_COISSUE', - 217: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD', - 218: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE', - 219: 'SQ_PERF_SEL_IS_CACHE_MISS', - 220: 'SQ_PERF_SEL_IS_CACHE_DUP_MISS', - 221: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC', - 222: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD', - 224: 'SQ_PERF_SEL_INSTS_TEX_SAMPLE', - 225: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN', - 226: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE', - 227: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN', - 228: 'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH', - 229: 'SQ_PERF_SEL_INSTS_WMMA_LOAD', - 230: 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC', - 231: 'SQ_PERF_SEL_INSTS_EXP_MRT', - 232: 'SQ_PERF_SEL_INSTS_EXP_Z', - 233: 'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA', - 234: 'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD', - 235: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN', - 236: 'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE', - 237: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN', - 239: 'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER', - 241: 'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE', - 242: 'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC', - 243: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD', - 244: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE', - 245: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC', - 246: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH', - 247: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD', - 248: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE', - 249: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC', - 250: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS', - 251: 'SQ_PERF_SEL_DUMMY_END', - 287: 'SQ_PERF_SEL_DUMMY_LAST', - 288: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 289: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 290: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', - 291: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 292: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 293: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 294: 'SQC_PERF_SEL_LDS_ADDR_STALL', - 295: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', - 296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', - 300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 301: 'SQC_PERF_SEL_ICACHE_REQ', - 302: 'SQC_PERF_SEL_ICACHE_HITS', - 303: 'SQC_PERF_SEL_ICACHE_MISSES', - 304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 305: 'SQC_PERF_SEL_ICACHE_INVAL_INST', - 306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', - 310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 313: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 314: 'SQC_PERF_SEL_TC_REQ', - 315: 'SQC_PERF_SEL_TC_INST_REQ', - 316: 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 317: 'SQC_PERF_SEL_TC_STALL', - 318: 'SQC_PERF_SEL_TC_STARVE', - 319: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 320: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 321: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 322: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 323: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 324: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 325: 'SQC_PERF_SEL_DCACHE_REQ', - 326: 'SQC_PERF_SEL_DCACHE_HITS', - 327: 'SQC_PERF_SEL_DCACHE_MISSES', - 328: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 329: 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 330: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 331: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 332: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 333: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 334: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 335: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 336: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 337: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 338: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 339: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 340: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 341: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 342: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 343: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 344: 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 345: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 346: 'SQC_PERF_SEL_TD_VGPR_BUSY', - 347: 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 348: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 349: 'SQC_PERF_SEL_ICACHE_GCR', - 350: 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 351: 'SQC_PERF_SEL_DCACHE_GCR', - 352: 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 353: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', - 354: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', - 355: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 356: 'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES', - 357: 'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES', - 358: 'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES', - 359: 'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES', - 360: 'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT', - 361: 'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT', - 362: 'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT', - 363: 'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT', - 364: 'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT', - 365: 'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT', - 366: 'SQC_PERF_SEL_LDS_STORE_DWORDS', - 367: 'SQC_PERF_SEL_LDS_LOAD_DWORDS', - 368: 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS', - 369: 'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL', - 370: 'SQC_PERF_SEL_DUMMY_LAST', - 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', - 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', - 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', - 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', - 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 474: 'SP_PERF_SEL_VALU_OPERAND', - 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', - 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', - 480: 'SP_PERF_SEL_VALU_STALL', - 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 487: 'SP_PERF_SEL_VGPR_VMEM_RD', - 488: 'SP_PERF_SEL_VGPR_EXP_RD', - 489: 'SP_PERF_SEL_VGPR_SPI_WR', - 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', - 491: 'SP_PERF_SEL_VGPR_WR', - 492: 'SP_PERF_SEL_VGPR_RD', - 493: 'SP_PERF_SEL_VGPR_WR_KILL', - 494: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP', - 495: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS', - 496: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX', - 497: 'SP_PERF_SEL_DUMMY_LAST', - 511: 'SQ_PERF_SEL_NONE2', -} -SQ_PERF_SEL_NONE = 0 -SQ_PERF_SEL_ACCUM_PREV = 1 -SQ_PERF_SEL_CYCLES = 2 -SQ_PERF_SEL_BUSY_CYCLES = 3 -SQ_PERF_SEL_WAVES = 4 -SQ_PERF_SEL_WAVES_32 = 5 -SQ_PERF_SEL_WAVES_64 = 6 -SQ_PERF_SEL_LEVEL_WAVES = 7 -SQ_PERF_SEL_ITEMS = 8 -SQ_PERF_SEL_WAVE32_ITEMS = 9 -SQ_PERF_SEL_WAVE64_ITEMS = 10 -SQ_PERF_SEL_PS_QUADS = 11 -SQ_PERF_SEL_EVENTS = 12 -SQ_PERF_SEL_WAVES_EQ_32 = 13 -SQ_PERF_SEL_WAVES_EQ_64 = 14 -SQ_PERF_SEL_WAVES_LT_64 = 15 -SQ_PERF_SEL_WAVES_LT_48 = 16 -SQ_PERF_SEL_WAVES_LT_32 = 17 -SQ_PERF_SEL_WAVES_LT_16 = 18 -SQ_PERF_SEL_WAVES_RESTORED = 19 -SQ_PERF_SEL_WAVES_SAVED = 20 -SQ_PERF_SEL_MSG = 21 -SQ_PERF_SEL_MSG_INTERRUPT = 22 -SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 -SQ_PERF_SEL_WAVE_CYCLES = 24 -SQ_PERF_SEL_WAVE_READY = 25 -SQ_PERF_SEL_WAIT_INST_ANY = 26 -SQ_PERF_SEL_WAIT_ANY = 27 -SQ_PERF_SEL_WAIT_CNT_ANY = 28 -SQ_PERF_SEL_WAIT_CNT_LOAD = 29 -SQ_PERF_SEL_WAIT_CNT_STORE = 30 -SQ_PERF_SEL_WAIT_TTRACE = 31 -SQ_PERF_SEL_WAIT_IFETCH = 32 -SQ_PERF_SEL_WAIT_BARRIER = 33 -SQ_PERF_SEL_WAIT_EXP_ALLOC = 34 -SQ_PERF_SEL_WAIT_SLEEP = 35 -SQ_PERF_SEL_WAIT_DELAY_ALU = 36 -SQ_PERF_SEL_WAIT_DEPCTR = 37 -SQ_PERF_SEL_WAIT_OTHER = 38 -SQ_PERF_SEL_INSTS_ALL = 39 -SQ_PERF_SEL_INSTS_BRANCH = 40 -SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 41 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 42 -SQ_PERF_SEL_INSTS_EXP = 43 -SQ_PERF_SEL_INSTS_FLAT = 44 -SQ_PERF_SEL_INSTS_LDS = 45 -SQ_PERF_SEL_INSTS_SALU = 46 -SQ_PERF_SEL_INSTS_SMEM = 47 -SQ_PERF_SEL_INSTS_SMEM_NORM = 48 -SQ_PERF_SEL_INSTS_SENDMSG = 49 -SQ_PERF_SEL_INSTS_VALU = 50 -SQ_PERF_SEL_INSTS_VALU_TRANS32 = 51 -SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 52 -SQ_PERF_SEL_INSTS_TEX = 53 -SQ_PERF_SEL_INSTS_TEX_LOAD = 54 -SQ_PERF_SEL_INSTS_TEX_STORE = 55 -SQ_PERF_SEL_INSTS_DELAY_ALU = 56 -SQ_PERF_SEL_INSTS_INTERNAL = 57 -SQ_PERF_SEL_INSTS_VEC32 = 58 -SQ_PERF_SEL_INSTS_VEC32_FLAT = 59 -SQ_PERF_SEL_INSTS_VEC32_LDS = 60 -SQ_PERF_SEL_INSTS_VEC32_VALU = 61 -SQ_PERF_SEL_VEC32_INSTS_EXP = 62 -SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32 = 63 -SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC = 64 -SQ_PERF_SEL_INSTS_VEC32_TEX = 65 -SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD = 66 -SQ_PERF_SEL_INSTS_VEC32_TEX_STORE = 67 -SQ_PERF_SEL_ITEM_CYCLES_VALU = 68 -SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 69 -SQ_PERF_SEL_WAVE32_INSTS = 70 -SQ_PERF_SEL_WAVE64_INSTS = 71 -SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 72 -SQ_PERF_SEL_WAVE64_HALF_SKIP = 73 -SQ_PERF_SEL_INST_LEVEL_EXP = 74 -SQ_PERF_SEL_INST_LEVEL_LDS = 75 -SQ_PERF_SEL_INST_LEVEL_SMEM = 76 -SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 77 -SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 78 -SQ_PERF_SEL_IFETCH_REQS = 79 -SQ_PERF_SEL_IFETCH_LEVEL = 80 -SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 81 -SQ_PERF_SEL_VALU_SGATHER_STALL = 82 -SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 83 -SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 84 -SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 85 -SQ_PERF_SEL_SALU_SGATHER_STALL = 86 -SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 87 -SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 88 -SQ_PERF_SEL_INST_ISSUE_SMEM_STALL = 89 -SQ_PERF_SEL_INST_ISSUE_ALL_STALL = 90 -SQ_PERF_SEL_INST_ISSUE_VALU_STALL = 91 -SQ_PERF_SEL_INST_ISSUE_SALU_STALL = 92 -SQ_PERF_SEL_INST_ISSUE_TEX_STALL = 93 -SQ_PERF_SEL_INST_ISSUE_LDS_STALL = 94 -SQ_PERF_SEL_INST_ISSUE_EXP_STALL = 96 -SQ_PERF_SEL_INST_WAITCNT_STALL = 97 -SQ_PERF_SEL_INST_BARRIER_STALL = 98 -SQ_PERF_SEL_INST_CYCLES_VALU = 99 -SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 100 -SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 101 -SQ_PERF_SEL_INST_CYCLES_VMEM = 102 -SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 103 -SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 104 -SQ_PERF_SEL_INST_CYCLES_LDS = 105 -SQ_PERF_SEL_INST_CYCLES_TEX = 106 -SQ_PERF_SEL_INST_CYCLES_FLAT = 107 -SQ_PERF_SEL_INST_CYCLES_EXP = 108 -SQ_PERF_SEL_VALU_STARVE = 109 -SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 110 -SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 111 -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 112 -SQ_PERF_SEL_VMEM_BUS_ACTIVE = 113 -SQ_PERF_SEL_VMEM_BUS_STALL = 114 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 115 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 116 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 117 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 118 -SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 119 -SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 120 -SQ_PERF_SEL_SALU_PIPE_STALL = 121 -SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 122 -SQ_PERF_SEL_MSG_BUS_BUSY = 123 -SQ_PERF_SEL_EXP_REQ_BUS_STALL = 124 -SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 125 -SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 126 -SQ_PERF_SEL_EXP_BUS0_BUSY = 127 -SQ_PERF_SEL_EXP_BUS1_BUSY = 128 -SQ_PERF_SEL_INST_CACHE_REQ_STALL = 129 -SQ_PERF_SEL_USER0 = 130 -SQ_PERF_SEL_USER1 = 131 -SQ_PERF_SEL_USER2 = 132 -SQ_PERF_SEL_USER3 = 133 -SQ_PERF_SEL_USER4 = 134 -SQ_PERF_SEL_USER5 = 135 -SQ_PERF_SEL_USER6 = 136 -SQ_PERF_SEL_USER7 = 137 -SQ_PERF_SEL_USER8 = 138 -SQ_PERF_SEL_USER9 = 139 -SQ_PERF_SEL_USER10 = 140 -SQ_PERF_SEL_USER11 = 141 -SQ_PERF_SEL_USER12 = 142 -SQ_PERF_SEL_USER13 = 143 -SQ_PERF_SEL_USER14 = 144 -SQ_PERF_SEL_USER15 = 145 -SQ_PERF_SEL_USER_LEVEL0 = 146 -SQ_PERF_SEL_USER_LEVEL1 = 147 -SQ_PERF_SEL_USER_LEVEL2 = 148 -SQ_PERF_SEL_USER_LEVEL3 = 149 -SQ_PERF_SEL_USER_LEVEL4 = 150 -SQ_PERF_SEL_USER_LEVEL5 = 151 -SQ_PERF_SEL_USER_LEVEL6 = 152 -SQ_PERF_SEL_USER_LEVEL7 = 153 -SQ_PERF_SEL_USER_LEVEL8 = 154 -SQ_PERF_SEL_USER_LEVEL9 = 155 -SQ_PERF_SEL_USER_LEVEL10 = 156 -SQ_PERF_SEL_USER_LEVEL11 = 157 -SQ_PERF_SEL_USER_LEVEL12 = 158 -SQ_PERF_SEL_USER_LEVEL13 = 159 -SQ_PERF_SEL_USER_LEVEL14 = 160 -SQ_PERF_SEL_USER_LEVEL15 = 161 -SQ_PERF_SEL_VALU_RETURN_SDST = 162 -SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 163 -SQ_PERF_SEL_INSTS_VALU_TRANS = 164 -SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 165 -SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 166 -SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD = 167 -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 168 -SQ_PERF_SEL_INSTS_VALU_VINTERP = 169 -SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP = 170 -SQ_PERF_SEL_OVERFLOW_PREV = 171 -SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 172 -SQ_PERF_SEL_INSTS_VALU_1_PASS = 173 -SQ_PERF_SEL_INSTS_VALU_2_PASS = 174 -SQ_PERF_SEL_INSTS_VALU_4_PASS = 175 -SQ_PERF_SEL_INSTS_VALU_DP = 176 -SQ_PERF_SEL_SP_CONST_CYCLES = 177 -SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 178 -SQ_PERF_SEL_ITEMS_VALU = 179 -SQ_PERF_SEL_ITEMS_MAX_VALU = 180 -SQ_PERF_SEL_ITEM_CYCLES_VMEM = 181 -SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE = 182 -SQ_PERF_SEL_INSTS_FLAT_LOAD = 183 -SQ_PERF_SEL_INSTS_FLAT_STORE = 184 -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT = 185 -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT = 186 -SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED = 187 -SQ_PERF_SEL_INSTS_BARRIER_LOCK = 188 -SQ_PERF_SEL_INSTS_WAKEUP = 189 -SQ_PERF_SEL_IS_CACHE_REQ = 190 -SQ_PERF_SEL_INSTS_SALU_PS = 191 -SQ_PERF_SEL_INSTS_SALU_GS = 192 -SQ_PERF_SEL_INSTS_SALU_HS = 193 -SQ_PERF_SEL_INSTS_SALU_CS = 194 -SQ_PERF_SEL_INSTS_SMEM_PS = 195 -SQ_PERF_SEL_INSTS_SMEM_GS = 196 -SQ_PERF_SEL_INSTS_SMEM_HS = 197 -SQ_PERF_SEL_INSTS_SMEM_CS = 198 -SQ_PERF_SEL_INSTS_VEC32_TEX_PS = 199 -SQ_PERF_SEL_INSTS_VEC32_TEX_GS = 200 -SQ_PERF_SEL_INSTS_VEC32_TEX_HS = 201 -SQ_PERF_SEL_INSTS_VEC32_TEX_CS = 202 -SQ_PERF_SEL_INSTS_VEC32_VALU_PS = 203 -SQ_PERF_SEL_INSTS_VEC32_VALU_GS = 204 -SQ_PERF_SEL_INSTS_VEC32_VALU_HS = 205 -SQ_PERF_SEL_INSTS_VEC32_VALU_CS = 206 -SQ_PERF_SEL_WAIT_CNT_SAMPLE = 207 -SQ_PERF_SEL_WAIT_CNT_KM = 209 -SQ_PERF_SEL_WAIT_CNT_DS = 210 -SQ_PERF_SEL_WAIT_CNT_EXP = 211 -SQ_PERF_SEL_INSTS_SALU_FLOAT = 212 -SQ_PERF_SEL_INSTS_VGPR_ALLOC = 213 -SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL = 214 -SQ_PERF_SEL_INSTS_LOCK = 215 -SQ_PERF_SEL_INSTS_VALU_COISSUE = 216 -SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD = 217 -SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE = 218 -SQ_PERF_SEL_IS_CACHE_MISS = 219 -SQ_PERF_SEL_IS_CACHE_DUP_MISS = 220 -SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC = 221 -SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD = 222 -SQ_PERF_SEL_INSTS_TEX_SAMPLE = 224 -SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN = 225 -SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE = 226 -SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN = 227 -SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH = 228 -SQ_PERF_SEL_INSTS_WMMA_LOAD = 229 -SQ_PERF_SEL_INSTS_FLAT_ATOMIC = 230 -SQ_PERF_SEL_INSTS_EXP_MRT = 231 -SQ_PERF_SEL_INSTS_EXP_Z = 232 -SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA = 233 -SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD = 234 -SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN = 235 -SQ_PERF_SEL_INSTS_VEC32_LDS_STORE = 236 -SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN = 237 -SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER = 239 -SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE = 241 -SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC = 242 -SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD = 243 -SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE = 244 -SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC = 245 -SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH = 246 -SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD = 247 -SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE = 248 -SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC = 249 -SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS = 250 -SQ_PERF_SEL_DUMMY_END = 251 -SQ_PERF_SEL_DUMMY_LAST = 287 -SQC_PERF_SEL_LDS_BANK_CONFLICT = 288 -SQC_PERF_SEL_LDS_ADDR_CONFLICT = 289 -SQC_PERF_SEL_LDS_UNALIGNED_STALL = 290 -SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 291 -SQC_PERF_SEL_LDS_ATOMIC_RETURN = 292 -SQC_PERF_SEL_LDS_IDX_ACTIVE = 293 -SQC_PERF_SEL_LDS_ADDR_STALL = 294 -SQC_PERF_SEL_LDS_ADDR_ACTIVE = 295 -SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296 -SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297 -SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298 -SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299 -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300 -SQC_PERF_SEL_ICACHE_REQ = 301 -SQC_PERF_SEL_ICACHE_HITS = 302 -SQC_PERF_SEL_ICACHE_MISSES = 303 -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304 -SQC_PERF_SEL_ICACHE_INVAL_INST = 305 -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306 -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307 -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308 -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309 -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310 -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 312 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 313 -SQC_PERF_SEL_TC_REQ = 314 -SQC_PERF_SEL_TC_INST_REQ = 315 -SQC_PERF_SEL_TC_DATA_READ_REQ = 316 -SQC_PERF_SEL_TC_STALL = 317 -SQC_PERF_SEL_TC_STARVE = 318 -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 319 -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 320 -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 321 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 322 -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 323 -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 324 -SQC_PERF_SEL_DCACHE_REQ = 325 -SQC_PERF_SEL_DCACHE_HITS = 326 -SQC_PERF_SEL_DCACHE_MISSES = 327 -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 328 -SQC_PERF_SEL_DCACHE_INVAL_INST = 329 -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 330 -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 331 -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 332 -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 333 -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 334 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 335 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 336 -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 337 -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 338 -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 339 -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 340 -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 341 -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 342 -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 343 -SQC_PERF_SEL_SQ_DCACHE_REQS = 344 -SQC_PERF_SEL_DCACHE_FLAT_REQ = 345 -SQC_PERF_SEL_TD_VGPR_BUSY = 346 -SQC_PERF_SEL_LDS_VGPR_BUSY = 347 -SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 348 -SQC_PERF_SEL_ICACHE_GCR = 349 -SQC_PERF_SEL_ICACHE_GCR_HITS = 350 -SQC_PERF_SEL_DCACHE_GCR = 351 -SQC_PERF_SEL_DCACHE_GCR_HITS = 352 -SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 353 -SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 354 -SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 355 -SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES = 356 -SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES = 357 -SQC_PERF_SEL_ICACHE_PREFETCH_MISSES = 358 -SQC_PERF_SEL_DCACHE_PREFETCH_MISSES = 359 -SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT = 360 -SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT = 361 -SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT = 362 -SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT = 363 -SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT = 364 -SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT = 365 -SQC_PERF_SEL_LDS_STORE_DWORDS = 366 -SQC_PERF_SEL_LDS_LOAD_DWORDS = 367 -SQC_PERF_SEL_LDS_ATOMIC_DWORDS = 368 -SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL = 369 -SQC_PERF_SEL_DUMMY_LAST = 370 -SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 -SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 -SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 -SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 -SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 -SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 -SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 -SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 -SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 -SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 -SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 -SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 -SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 -SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 -SP_PERF_SEL_VALU_OPERAND = 474 -SP_PERF_SEL_VALU_VGPR_OPERAND = 475 -SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 -SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 -SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 -SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 -SP_PERF_SEL_VALU_STALL = 480 -SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 -SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 -SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 -SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 -SP_PERF_SEL_VALU_STALL_DST_STALL = 485 -SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 -SP_PERF_SEL_VGPR_VMEM_RD = 487 -SP_PERF_SEL_VGPR_EXP_RD = 488 -SP_PERF_SEL_VGPR_SPI_WR = 489 -SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 -SP_PERF_SEL_VGPR_WR = 491 -SP_PERF_SEL_VGPR_RD = 492 -SP_PERF_SEL_VGPR_WR_KILL = 493 -SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP = 494 -SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS = 495 -SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX = 496 -SP_PERF_SEL_DUMMY_LAST = 497 -SQ_PERF_SEL_NONE2 = 511 -SQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_ROUND_MODE' -SQ_ROUND_MODE__enumvalues = { - 0: 'SQ_ROUND_NEAREST_EVEN', - 1: 'SQ_ROUND_PLUS_INFINITY', - 2: 'SQ_ROUND_MINUS_INFINITY', - 3: 'SQ_ROUND_TO_ZERO', -} -SQ_ROUND_NEAREST_EVEN = 0 -SQ_ROUND_PLUS_INFINITY = 1 -SQ_ROUND_MINUS_INFINITY = 2 -SQ_ROUND_TO_ZERO = 3 -SQ_ROUND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_BUF_TYPE' -SQ_RSRC_BUF_TYPE__enumvalues = { - 0: 'SQ_RSRC_BUF', - 1: 'SQ_RSRC_BUF_RSVD_1', - 2: 'SQ_RSRC_BUF_RSVD_2', - 3: 'SQ_RSRC_BUF_RSVD_3', -} -SQ_RSRC_BUF = 0 -SQ_RSRC_BUF_RSVD_1 = 1 -SQ_RSRC_BUF_RSVD_2 = 2 -SQ_RSRC_BUF_RSVD_3 = 3 -SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_FLAT_TYPE' -SQ_RSRC_FLAT_TYPE__enumvalues = { - 0: 'SQ_RSRC_FLAT_RSVD_0', - 1: 'SQ_RSRC_FLAT', - 2: 'SQ_RSRC_FLAT_RSVD_2', - 3: 'SQ_RSRC_FLAT_RSVD_3', -} -SQ_RSRC_FLAT_RSVD_0 = 0 -SQ_RSRC_FLAT = 1 -SQ_RSRC_FLAT_RSVD_2 = 2 -SQ_RSRC_FLAT_RSVD_3 = 3 -SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_IMG_TYPE' -SQ_RSRC_IMG_TYPE__enumvalues = { - 0: 'SQ_RSRC_IMG_RSVD_0', - 1: 'SQ_RSRC_IMG_RSVD_1', - 2: 'SQ_RSRC_IMG_RSVD_2', - 3: 'SQ_RSRC_IMG_RSVD_3', - 4: 'SQ_RSRC_IMG_RSVD_4', - 5: 'SQ_RSRC_IMG_RSVD_5', - 6: 'SQ_RSRC_IMG_RSVD_6', - 7: 'SQ_RSRC_IMG_RSVD_7', - 8: 'SQ_RSRC_IMG_1D', - 9: 'SQ_RSRC_IMG_2D', - 10: 'SQ_RSRC_IMG_3D', - 11: 'SQ_RSRC_IMG_CUBE', - 12: 'SQ_RSRC_IMG_1D_ARRAY', - 13: 'SQ_RSRC_IMG_2D_ARRAY', - 14: 'SQ_RSRC_IMG_2D_MSAA', - 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', -} -SQ_RSRC_IMG_RSVD_0 = 0 -SQ_RSRC_IMG_RSVD_1 = 1 -SQ_RSRC_IMG_RSVD_2 = 2 -SQ_RSRC_IMG_RSVD_3 = 3 -SQ_RSRC_IMG_RSVD_4 = 4 -SQ_RSRC_IMG_RSVD_5 = 5 -SQ_RSRC_IMG_RSVD_6 = 6 -SQ_RSRC_IMG_RSVD_7 = 7 -SQ_RSRC_IMG_1D = 8 -SQ_RSRC_IMG_2D = 9 -SQ_RSRC_IMG_3D = 10 -SQ_RSRC_IMG_CUBE = 11 -SQ_RSRC_IMG_1D_ARRAY = 12 -SQ_RSRC_IMG_2D_ARRAY = 13 -SQ_RSRC_IMG_2D_MSAA = 14 -SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 -SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_SEL_XYZW01' -SQ_SEL_XYZW01__enumvalues = { - 0: 'SQ_SEL_0', - 1: 'SQ_SEL_1', - 2: 'SQ_SEL_N_BC_1', - 3: 'SQ_SEL_RESERVED_1', - 4: 'SQ_SEL_X', - 5: 'SQ_SEL_Y', - 6: 'SQ_SEL_Z', - 7: 'SQ_SEL_W', -} -SQ_SEL_0 = 0 -SQ_SEL_1 = 1 -SQ_SEL_N_BC_1 = 2 -SQ_SEL_RESERVED_1 = 3 -SQ_SEL_X = 4 -SQ_SEL_Y = 5 -SQ_SEL_Z = 6 -SQ_SEL_W = 7 -SQ_SEL_XYZW01 = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_ANISO_RATIO' -SQ_TEX_ANISO_RATIO__enumvalues = { - 0: 'SQ_TEX_ANISO_RATIO_1', - 1: 'SQ_TEX_ANISO_RATIO_2', - 2: 'SQ_TEX_ANISO_RATIO_4', - 3: 'SQ_TEX_ANISO_RATIO_8', - 4: 'SQ_TEX_ANISO_RATIO_16', -} -SQ_TEX_ANISO_RATIO_1 = 0 -SQ_TEX_ANISO_RATIO_2 = 1 -SQ_TEX_ANISO_RATIO_4 = 2 -SQ_TEX_ANISO_RATIO_8 = 3 -SQ_TEX_ANISO_RATIO_16 = 4 -SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_BORDER_COLOR' -SQ_TEX_BORDER_COLOR__enumvalues = { - 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 3: 'SQ_TEX_BORDER_COLOR_REGISTER', -} -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 -SQ_TEX_BORDER_COLOR_REGISTER = 3 -SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_CLAMP' -SQ_TEX_CLAMP__enumvalues = { - 0: 'SQ_TEX_WRAP', - 1: 'SQ_TEX_MIRROR', - 2: 'SQ_TEX_CLAMP_LAST_TEXEL', - 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 4: 'SQ_TEX_CLAMP_HALF_BORDER', - 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', - 6: 'SQ_TEX_CLAMP_BORDER', - 7: 'SQ_TEX_MIRROR_ONCE_BORDER', -} -SQ_TEX_WRAP = 0 -SQ_TEX_MIRROR = 1 -SQ_TEX_CLAMP_LAST_TEXEL = 2 -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 -SQ_TEX_CLAMP_HALF_BORDER = 4 -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 -SQ_TEX_CLAMP_BORDER = 6 -SQ_TEX_MIRROR_ONCE_BORDER = 7 -SQ_TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_DEPTH_COMPARE' -SQ_TEX_DEPTH_COMPARE__enumvalues = { - 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', - 1: 'SQ_TEX_DEPTH_COMPARE_LESS', - 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', - 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', - 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', - 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', - 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', -} -SQ_TEX_DEPTH_COMPARE_NEVER = 0 -SQ_TEX_DEPTH_COMPARE_LESS = 1 -SQ_TEX_DEPTH_COMPARE_EQUAL = 2 -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 -SQ_TEX_DEPTH_COMPARE_GREATER = 4 -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 -SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 -SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_MIP_FILTER' -SQ_TEX_MIP_FILTER__enumvalues = { - 0: 'SQ_TEX_MIP_FILTER_NONE', - 1: 'SQ_TEX_MIP_FILTER_POINT', - 2: 'SQ_TEX_MIP_FILTER_LINEAR', - 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', -} -SQ_TEX_MIP_FILTER_NONE = 0 -SQ_TEX_MIP_FILTER_POINT = 1 -SQ_TEX_MIP_FILTER_LINEAR = 2 -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 -SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_XY_FILTER' -SQ_TEX_XY_FILTER__enumvalues = { - 0: 'SQ_TEX_XY_FILTER_POINT', - 1: 'SQ_TEX_XY_FILTER_BILINEAR', - 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', - 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', -} -SQ_TEX_XY_FILTER_POINT = 0 -SQ_TEX_XY_FILTER_BILINEAR = 1 -SQ_TEX_XY_FILTER_ANISO_POINT = 2 -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 -SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_Z_FILTER' -SQ_TEX_Z_FILTER__enumvalues = { - 0: 'SQ_TEX_Z_FILTER_NONE', - 1: 'SQ_TEX_Z_FILTER_POINT', - 2: 'SQ_TEX_Z_FILTER_LINEAR', -} -SQ_TEX_Z_FILTER_NONE = 0 -SQ_TEX_Z_FILTER_POINT = 1 -SQ_TEX_Z_FILTER_LINEAR = 2 -SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WATCH_MODES' -SQ_WATCH_MODES__enumvalues = { - 0: 'SQ_WATCH_MODE_READ', - 1: 'SQ_WATCH_MODE_NONREAD', - 2: 'SQ_WATCH_MODE_ATOMIC', - 3: 'SQ_WATCH_MODE_ALL', -} -SQ_WATCH_MODE_READ = 0 -SQ_WATCH_MODE_NONREAD = 1 -SQ_WATCH_MODE_ATOMIC = 2 -SQ_WATCH_MODE_ALL = 3 -SQ_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' -SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { - 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', - 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', - 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', -} -SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 -SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 -SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 -SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 -SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_SCHED_MODES' -SQ_WAVE_SCHED_MODES__enumvalues = { - 0: 'SQ_WAVE_SCHED_MODE_NORMAL', - 1: 'SQ_WAVE_SCHED_MODE_EXPERT', - 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC', -} -SQ_WAVE_SCHED_MODE_NORMAL = 0 -SQ_WAVE_SCHED_MODE_EXPERT = 1 -SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC = 2 -SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_TYPE' -SQ_WAVE_TYPE__enumvalues = { - 0: 'SQ_WAVE_TYPE_PS', - 1: 'SQ_WAVE_TYPE_RSVD0', - 2: 'SQ_WAVE_TYPE_GS', - 3: 'SQ_WAVE_TYPE_RSVD1', - 4: 'SQ_WAVE_TYPE_HS', - 5: 'SQ_WAVE_TYPE_RSVD2', - 6: 'SQ_WAVE_TYPE_CS', - 7: 'SQ_WAVE_TYPE_PS1', - 8: 'SQ_WAVE_TYPE_PS2', - 9: 'SQ_WAVE_TYPE_PS3', -} -SQ_WAVE_TYPE_PS = 0 -SQ_WAVE_TYPE_RSVD0 = 1 -SQ_WAVE_TYPE_GS = 2 -SQ_WAVE_TYPE_RSVD1 = 3 -SQ_WAVE_TYPE_HS = 4 -SQ_WAVE_TYPE_RSVD2 = 5 -SQ_WAVE_TYPE_CS = 6 -SQ_WAVE_TYPE_PS1 = 7 -SQ_WAVE_TYPE_PS2 = 8 -SQ_WAVE_TYPE_PS3 = 9 -SQ_WAVE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GL1A_PERF_SEL' -GL1A_PERF_SEL__enumvalues = { - 0: 'GL1A_PERF_SEL_BUSY', - 1: 'GL1A_PERF_SEL_STALL_GL1C0', - 2: 'GL1A_PERF_SEL_STALL_GL1C1', - 3: 'GL1A_PERF_SEL_STALL_GL1C2', - 4: 'GL1A_PERF_SEL_STALL_GL1C3', - 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', - 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', - 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', - 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', - 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', - 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', - 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', - 17: 'GL1A_PERF_SEL_ARB_REQUESTS', - 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 23: 'GL1A_PERF_SEL_CYCLE', -} -GL1A_PERF_SEL_BUSY = 0 -GL1A_PERF_SEL_STALL_GL1C0 = 1 -GL1A_PERF_SEL_STALL_GL1C1 = 2 -GL1A_PERF_SEL_STALL_GL1C2 = 3 -GL1A_PERF_SEL_STALL_GL1C3 = 4 -GL1A_PERF_SEL_REQUEST_GL1C0 = 5 -GL1A_PERF_SEL_REQUEST_GL1C1 = 6 -GL1A_PERF_SEL_REQUEST_GL1C2 = 7 -GL1A_PERF_SEL_REQUEST_GL1C3 = 8 -GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 -GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 -GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 -GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 -GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 -GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 -GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 -GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 -GL1A_PERF_SEL_ARB_REQUESTS = 17 -GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 -GL1A_PERF_SEL_CYCLE = 23 -GL1A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1C_PERF_SEL' -GL1C_PERF_SEL__enumvalues = { - 0: 'GL1C_PERF_SEL_CYCLE', - 1: 'GL1C_PERF_SEL_BUSY', - 2: 'GL1C_PERF_SEL_STARVE', - 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 4: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'GL1C_PERF_SEL_REQ', - 7: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'GL1C_PERF_SEL_REQ_NOP_ACK', - 10: 'GL1C_PERF_SEL_REQ_NOP_RTN0', - 11: 'GL1C_PERF_SEL_REQ_READ', - 12: 'GL1C_PERF_SEL_REQ_READ_128B', - 13: 'GL1C_PERF_SEL_REQ_READ_32B', - 14: 'GL1C_PERF_SEL_REQ_READ_64B', - 15: 'GL1C_PERF_SEL_REQ_WRITE', - 16: 'GL1C_PERF_SEL_REQ_WRITE_32B', - 17: 'GL1C_PERF_SEL_REQ_WRITE_64B', - 18: 'GL1C_PERF_SEL_STALL_GL2_GL1', - 19: 'GL1C_PERF_SEL_STALL_BUFFER_FULL', - 20: 'GL1C_PERF_SEL_STALL_VM', - 21: 'GL1C_PERF_SEL_REQ_CLIENT0', - 22: 'GL1C_PERF_SEL_REQ_CLIENT1', - 23: 'GL1C_PERF_SEL_REQ_CLIENT2', - 24: 'GL1C_PERF_SEL_REQ_CLIENT3', - 25: 'GL1C_PERF_SEL_REQ_CLIENT4', - 26: 'GL1C_PERF_SEL_REQ_CLIENT5', - 27: 'GL1C_PERF_SEL_REQ_CLIENT6', - 28: 'GL1C_PERF_SEL_REQ_CLIENT7', - 29: 'GL1C_PERF_SEL_REQ_CLIENT8', - 30: 'GL1C_PERF_SEL_REQ_CLIENT9', - 31: 'GL1C_PERF_SEL_REQ_CLIENT10', - 32: 'GL1C_PERF_SEL_REQ_CLIENT11', - 33: 'GL1C_PERF_SEL_REQ_CLIENT12', - 34: 'GL1C_PERF_SEL_REQ_CLIENT13', - 35: 'GL1C_PERF_SEL_REQ_CLIENT14', - 36: 'GL1C_PERF_SEL_REQ_CLIENT15', - 37: 'GL1C_PERF_SEL_REQ_CLIENT16', - 38: 'GL1C_PERF_SEL_REQ_CLIENT17', - 39: 'GL1C_PERF_SEL_REQ_CLIENT18', - 40: 'GL1C_PERF_SEL_REQ_CLIENT19', - 41: 'GL1C_PERF_SEL_REQ_CLIENT20', - 42: 'GL1C_PERF_SEL_REQ_CLIENT21', - 43: 'GL1C_PERF_SEL_REQ_CLIENT22', - 44: 'GL1C_PERF_SEL_REQ_CLIENT23', - 45: 'GL1C_PERF_SEL_REQ_CLIENT24', - 46: 'GL1C_PERF_SEL_REQ_CLIENT25', - 47: 'GL1C_PERF_SEL_REQ_CLIENT26', - 48: 'GL1C_PERF_SEL_REQ_CLIENT27', - 49: 'GL1C_PERF_SEL_UTCL0_REQUEST', - 50: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 51: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 52: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 53: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 54: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 55: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 56: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 57: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 58: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 59: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 60: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 61: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 62: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 63: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 64: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 65: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 66: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 67: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 68: 'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST', -} -GL1C_PERF_SEL_CYCLE = 0 -GL1C_PERF_SEL_BUSY = 1 -GL1C_PERF_SEL_STARVE = 2 -GL1C_PERF_SEL_ARB_RET_LEVEL = 3 -GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -GL1C_PERF_SEL_REQ = 6 -GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -GL1C_PERF_SEL_REQ_NOP_ACK = 9 -GL1C_PERF_SEL_REQ_NOP_RTN0 = 10 -GL1C_PERF_SEL_REQ_READ = 11 -GL1C_PERF_SEL_REQ_READ_128B = 12 -GL1C_PERF_SEL_REQ_READ_32B = 13 -GL1C_PERF_SEL_REQ_READ_64B = 14 -GL1C_PERF_SEL_REQ_WRITE = 15 -GL1C_PERF_SEL_REQ_WRITE_32B = 16 -GL1C_PERF_SEL_REQ_WRITE_64B = 17 -GL1C_PERF_SEL_STALL_GL2_GL1 = 18 -GL1C_PERF_SEL_STALL_BUFFER_FULL = 19 -GL1C_PERF_SEL_STALL_VM = 20 -GL1C_PERF_SEL_REQ_CLIENT0 = 21 -GL1C_PERF_SEL_REQ_CLIENT1 = 22 -GL1C_PERF_SEL_REQ_CLIENT2 = 23 -GL1C_PERF_SEL_REQ_CLIENT3 = 24 -GL1C_PERF_SEL_REQ_CLIENT4 = 25 -GL1C_PERF_SEL_REQ_CLIENT5 = 26 -GL1C_PERF_SEL_REQ_CLIENT6 = 27 -GL1C_PERF_SEL_REQ_CLIENT7 = 28 -GL1C_PERF_SEL_REQ_CLIENT8 = 29 -GL1C_PERF_SEL_REQ_CLIENT9 = 30 -GL1C_PERF_SEL_REQ_CLIENT10 = 31 -GL1C_PERF_SEL_REQ_CLIENT11 = 32 -GL1C_PERF_SEL_REQ_CLIENT12 = 33 -GL1C_PERF_SEL_REQ_CLIENT13 = 34 -GL1C_PERF_SEL_REQ_CLIENT14 = 35 -GL1C_PERF_SEL_REQ_CLIENT15 = 36 -GL1C_PERF_SEL_REQ_CLIENT16 = 37 -GL1C_PERF_SEL_REQ_CLIENT17 = 38 -GL1C_PERF_SEL_REQ_CLIENT18 = 39 -GL1C_PERF_SEL_REQ_CLIENT19 = 40 -GL1C_PERF_SEL_REQ_CLIENT20 = 41 -GL1C_PERF_SEL_REQ_CLIENT21 = 42 -GL1C_PERF_SEL_REQ_CLIENT22 = 43 -GL1C_PERF_SEL_REQ_CLIENT23 = 44 -GL1C_PERF_SEL_REQ_CLIENT24 = 45 -GL1C_PERF_SEL_REQ_CLIENT25 = 46 -GL1C_PERF_SEL_REQ_CLIENT26 = 47 -GL1C_PERF_SEL_REQ_CLIENT27 = 48 -GL1C_PERF_SEL_UTCL0_REQUEST = 49 -GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 50 -GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 51 -GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 52 -GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53 -GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 54 -GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55 -GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56 -GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57 -GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58 -GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59 -GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60 -GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61 -GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62 -GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63 -GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67 -GL1C_PERF_SEL_UTCL0_GPA3_REQUEST = 68 -GL1C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1XA_PERF_SEL' -GL1XA_PERF_SEL__enumvalues = { - 0: 'GL1XA_PERF_SEL_BUSY', - 1: 'GL1XA_PERF_SEL_STALL_GL1XC0', - 2: 'GL1XA_PERF_SEL_STALL_GL1XC1', - 3: 'GL1XA_PERF_SEL_STALL_GL1XC2', - 4: 'GL1XA_PERF_SEL_STALL_GL1XC3', - 5: 'GL1XA_PERF_SEL_REQUEST_GL1XC0', - 6: 'GL1XA_PERF_SEL_REQUEST_GL1XC1', - 7: 'GL1XA_PERF_SEL_REQUEST_GL1XC2', - 8: 'GL1XA_PERF_SEL_REQUEST_GL1XC3', - 9: 'GL1XA_PERF_SEL_WDS_32B_GL1XC0', - 10: 'GL1XA_PERF_SEL_WDS_32B_GL1XC1', - 11: 'GL1XA_PERF_SEL_WDS_32B_GL1XC2', - 12: 'GL1XA_PERF_SEL_WDS_32B_GL1XC3', - 13: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0', - 14: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1', - 15: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2', - 16: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3', - 17: 'GL1XA_PERF_SEL_ARB_REQUESTS', - 18: 'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 19: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0', - 20: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1', - 21: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2', - 22: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3', - 23: 'GL1XA_PERF_SEL_CYCLE', -} -GL1XA_PERF_SEL_BUSY = 0 -GL1XA_PERF_SEL_STALL_GL1XC0 = 1 -GL1XA_PERF_SEL_STALL_GL1XC1 = 2 -GL1XA_PERF_SEL_STALL_GL1XC2 = 3 -GL1XA_PERF_SEL_STALL_GL1XC3 = 4 -GL1XA_PERF_SEL_REQUEST_GL1XC0 = 5 -GL1XA_PERF_SEL_REQUEST_GL1XC1 = 6 -GL1XA_PERF_SEL_REQUEST_GL1XC2 = 7 -GL1XA_PERF_SEL_REQUEST_GL1XC3 = 8 -GL1XA_PERF_SEL_WDS_32B_GL1XC0 = 9 -GL1XA_PERF_SEL_WDS_32B_GL1XC1 = 10 -GL1XA_PERF_SEL_WDS_32B_GL1XC2 = 11 -GL1XA_PERF_SEL_WDS_32B_GL1XC3 = 12 -GL1XA_PERF_SEL_BURST_COUNT_GL1XC0 = 13 -GL1XA_PERF_SEL_BURST_COUNT_GL1XC1 = 14 -GL1XA_PERF_SEL_BURST_COUNT_GL1XC2 = 15 -GL1XA_PERF_SEL_BURST_COUNT_GL1XC3 = 16 -GL1XA_PERF_SEL_ARB_REQUESTS = 17 -GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 -GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0 = 19 -GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1 = 20 -GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2 = 21 -GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3 = 22 -GL1XA_PERF_SEL_CYCLE = 23 -GL1XA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1XC_PERF_SEL' -GL1XC_PERF_SEL__enumvalues = { - 0: 'GL1XC_PERF_SEL_CYCLE', - 1: 'GL1XC_PERF_SEL_BUSY', - 2: 'GL1XC_PERF_SEL_STARVE', - 3: 'GL1XC_PERF_SEL_ARB_RET_LEVEL', - 4: 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'GL1XC_PERF_SEL_REQ', - 7: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'GL1XC_PERF_SEL_REQ_NOP_ACK', - 10: 'GL1XC_PERF_SEL_REQ_NOP_RTN0', - 11: 'GL1XC_PERF_SEL_REQ_READ', - 12: 'GL1XC_PERF_SEL_REQ_READ_128B', - 13: 'GL1XC_PERF_SEL_REQ_READ_32B', - 14: 'GL1XC_PERF_SEL_REQ_READ_64B', - 15: 'GL1XC_PERF_SEL_REQ_WRITE', - 16: 'GL1XC_PERF_SEL_REQ_WRITE_32B', - 17: 'GL1XC_PERF_SEL_REQ_WRITE_64B', - 18: 'GL1XC_PERF_SEL_STALL_GL2_GL1', - 19: 'GL1XC_PERF_SEL_STALL_BUFFER_FULL', - 20: 'GL1XC_PERF_SEL_STALL_VM', - 21: 'GL1XC_PERF_SEL_REQ_CLIENT0', - 22: 'GL1XC_PERF_SEL_REQ_CLIENT1', - 23: 'GL1XC_PERF_SEL_REQ_CLIENT2', - 24: 'GL1XC_PERF_SEL_REQ_CLIENT3', - 25: 'GL1XC_PERF_SEL_REQ_CLIENT4', - 26: 'GL1XC_PERF_SEL_REQ_CLIENT5', - 27: 'GL1XC_PERF_SEL_REQ_CLIENT6', - 28: 'GL1XC_PERF_SEL_REQ_CLIENT7', - 29: 'GL1XC_PERF_SEL_REQ_CLIENT8', - 30: 'GL1XC_PERF_SEL_REQ_CLIENT9', - 31: 'GL1XC_PERF_SEL_REQ_CLIENT10', - 32: 'GL1XC_PERF_SEL_REQ_CLIENT11', - 33: 'GL1XC_PERF_SEL_REQ_CLIENT12', - 34: 'GL1XC_PERF_SEL_REQ_CLIENT13', - 35: 'GL1XC_PERF_SEL_REQ_CLIENT14', - 36: 'GL1XC_PERF_SEL_REQ_CLIENT15', - 37: 'GL1XC_PERF_SEL_REQ_CLIENT16', - 38: 'GL1XC_PERF_SEL_REQ_CLIENT17', - 39: 'GL1XC_PERF_SEL_REQ_CLIENT18', - 40: 'GL1XC_PERF_SEL_REQ_CLIENT19', - 41: 'GL1XC_PERF_SEL_REQ_CLIENT20', - 42: 'GL1XC_PERF_SEL_REQ_CLIENT21', - 43: 'GL1XC_PERF_SEL_REQ_CLIENT22', - 44: 'GL1XC_PERF_SEL_REQ_CLIENT23', - 45: 'GL1XC_PERF_SEL_REQ_CLIENT24', - 46: 'GL1XC_PERF_SEL_REQ_CLIENT25', - 47: 'GL1XC_PERF_SEL_REQ_CLIENT26', - 48: 'GL1XC_PERF_SEL_REQ_CLIENT27', - 49: 'GL1XC_PERF_SEL_UTCL0_REQUEST', - 50: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT', - 51: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS', - 52: 'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS', - 53: 'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 54: 'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL', - 55: 'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 56: 'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 57: 'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 58: 'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 59: 'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 60: 'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 61: 'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 62: 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 63: 'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 64: 'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 65: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 66: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 67: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 68: 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST', -} -GL1XC_PERF_SEL_CYCLE = 0 -GL1XC_PERF_SEL_BUSY = 1 -GL1XC_PERF_SEL_STARVE = 2 -GL1XC_PERF_SEL_ARB_RET_LEVEL = 3 -GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -GL1XC_PERF_SEL_REQ = 6 -GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -GL1XC_PERF_SEL_REQ_NOP_ACK = 9 -GL1XC_PERF_SEL_REQ_NOP_RTN0 = 10 -GL1XC_PERF_SEL_REQ_READ = 11 -GL1XC_PERF_SEL_REQ_READ_128B = 12 -GL1XC_PERF_SEL_REQ_READ_32B = 13 -GL1XC_PERF_SEL_REQ_READ_64B = 14 -GL1XC_PERF_SEL_REQ_WRITE = 15 -GL1XC_PERF_SEL_REQ_WRITE_32B = 16 -GL1XC_PERF_SEL_REQ_WRITE_64B = 17 -GL1XC_PERF_SEL_STALL_GL2_GL1 = 18 -GL1XC_PERF_SEL_STALL_BUFFER_FULL = 19 -GL1XC_PERF_SEL_STALL_VM = 20 -GL1XC_PERF_SEL_REQ_CLIENT0 = 21 -GL1XC_PERF_SEL_REQ_CLIENT1 = 22 -GL1XC_PERF_SEL_REQ_CLIENT2 = 23 -GL1XC_PERF_SEL_REQ_CLIENT3 = 24 -GL1XC_PERF_SEL_REQ_CLIENT4 = 25 -GL1XC_PERF_SEL_REQ_CLIENT5 = 26 -GL1XC_PERF_SEL_REQ_CLIENT6 = 27 -GL1XC_PERF_SEL_REQ_CLIENT7 = 28 -GL1XC_PERF_SEL_REQ_CLIENT8 = 29 -GL1XC_PERF_SEL_REQ_CLIENT9 = 30 -GL1XC_PERF_SEL_REQ_CLIENT10 = 31 -GL1XC_PERF_SEL_REQ_CLIENT11 = 32 -GL1XC_PERF_SEL_REQ_CLIENT12 = 33 -GL1XC_PERF_SEL_REQ_CLIENT13 = 34 -GL1XC_PERF_SEL_REQ_CLIENT14 = 35 -GL1XC_PERF_SEL_REQ_CLIENT15 = 36 -GL1XC_PERF_SEL_REQ_CLIENT16 = 37 -GL1XC_PERF_SEL_REQ_CLIENT17 = 38 -GL1XC_PERF_SEL_REQ_CLIENT18 = 39 -GL1XC_PERF_SEL_REQ_CLIENT19 = 40 -GL1XC_PERF_SEL_REQ_CLIENT20 = 41 -GL1XC_PERF_SEL_REQ_CLIENT21 = 42 -GL1XC_PERF_SEL_REQ_CLIENT22 = 43 -GL1XC_PERF_SEL_REQ_CLIENT23 = 44 -GL1XC_PERF_SEL_REQ_CLIENT24 = 45 -GL1XC_PERF_SEL_REQ_CLIENT25 = 46 -GL1XC_PERF_SEL_REQ_CLIENT26 = 47 -GL1XC_PERF_SEL_REQ_CLIENT27 = 48 -GL1XC_PERF_SEL_UTCL0_REQUEST = 49 -GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT = 50 -GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS = 51 -GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS = 52 -GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53 -GL1XC_PERF_SEL_UTCL0_LFIFO_FULL = 54 -GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55 -GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56 -GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57 -GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58 -GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59 -GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60 -GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61 -GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62 -GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63 -GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64 -GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65 -GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66 -GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67 -GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST = 68 -GL1XC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBMH_PERF_SEL' -GRBMH_PERF_SEL__enumvalues = { - 0: 'GRBMH_PERF_SEL_COUNT', - 1: 'GRBMH_PERF_SEL_USER_DEFINED', - 2: 'GRBMH_PERF_SEL_CB_BUSY', - 3: 'GRBMH_PERF_SEL_CB_CLEAN', - 4: 'GRBMH_PERF_SEL_DB_BUSY', - 5: 'GRBMH_PERF_SEL_DB_CLEAN', - 6: 'GRBMH_PERF_SEL_SC_BUSY', - 7: 'GRBMH_PERF_SEL_SC_CLEAN', - 9: 'GRBMH_PERF_SEL_SPI_BUSY', - 10: 'GRBMH_PERF_SEL_SX_BUSY', - 11: 'GRBMH_PERF_SEL_TA_BUSY', - 12: 'GRBMH_PERF_SEL_EA_BUSY', - 13: 'GRBMH_PERF_SEL_EA_LINK_BUSY', - 14: 'GRBMH_PERF_SEL_PA_BUSY', - 15: 'GRBMH_PERF_SEL_BCI_BUSY', - 16: 'GRBMH_PERF_SEL_GL2A_BUSY', - 17: 'GRBMH_PERF_SEL_GL2C_BUSY', - 18: 'GRBMH_PERF_SEL_UTCL1_BUSY', - 19: 'GRBMH_PERF_SEL_TCP_BUSY', - 20: 'GRBMH_PERF_SEL_GL1A_BUSY', - 21: 'GRBMH_PERF_SEL_GL1CC_BUSY', - 22: 'GRBMH_PERF_SEL_GL1XCC_BUSY', - 23: 'GRBMH_PERF_SEL_PC_BUSY', - 24: 'GRBMH_PERF_SEL_GE_BUSY', - 25: 'GRBMH_PERF_SEL_RLC_BUSY', -} -GRBMH_PERF_SEL_COUNT = 0 -GRBMH_PERF_SEL_USER_DEFINED = 1 -GRBMH_PERF_SEL_CB_BUSY = 2 -GRBMH_PERF_SEL_CB_CLEAN = 3 -GRBMH_PERF_SEL_DB_BUSY = 4 -GRBMH_PERF_SEL_DB_CLEAN = 5 -GRBMH_PERF_SEL_SC_BUSY = 6 -GRBMH_PERF_SEL_SC_CLEAN = 7 -GRBMH_PERF_SEL_SPI_BUSY = 9 -GRBMH_PERF_SEL_SX_BUSY = 10 -GRBMH_PERF_SEL_TA_BUSY = 11 -GRBMH_PERF_SEL_EA_BUSY = 12 -GRBMH_PERF_SEL_EA_LINK_BUSY = 13 -GRBMH_PERF_SEL_PA_BUSY = 14 -GRBMH_PERF_SEL_BCI_BUSY = 15 -GRBMH_PERF_SEL_GL2A_BUSY = 16 -GRBMH_PERF_SEL_GL2C_BUSY = 17 -GRBMH_PERF_SEL_UTCL1_BUSY = 18 -GRBMH_PERF_SEL_TCP_BUSY = 19 -GRBMH_PERF_SEL_GL1A_BUSY = 20 -GRBMH_PERF_SEL_GL1CC_BUSY = 21 -GRBMH_PERF_SEL_GL1XCC_BUSY = 22 -GRBMH_PERF_SEL_PC_BUSY = 23 -GRBMH_PERF_SEL_GE_BUSY = 24 -GRBMH_PERF_SEL_RLC_BUSY = 25 -GRBMH_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TA_PERFCOUNT_SEL' -TA_PERFCOUNT_SEL__enumvalues = { - 0: 'TA_PERF_SEL_NULL', - 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 7: 'TA_PERF_SEL_gradient_busy', - 8: 'TA_PERF_SEL_gradient_fifo_busy', - 9: 'TA_PERF_SEL_lod_busy', - 10: 'TA_PERF_SEL_lod_fifo_busy', - 11: 'TA_PERF_SEL_addresser_busy', - 12: 'TA_PERF_SEL_addresser_fifo_busy', - 13: 'TA_PERF_SEL_aligner_busy', - 14: 'TA_PERF_SEL_write_path_busy', - 15: 'TA_PERF_SEL_ta_busy', - 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', - 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', - 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', - 32: 'TA_PERF_SEL_total_wavefronts', - 33: 'TA_PERF_SEL_gradient_cycles', - 34: 'TA_PERF_SEL_walker_cycles', - 35: 'TA_PERF_SEL_aligner_cycles', - 36: 'TA_PERF_SEL_image_wavefronts', - 37: 'TA_PERF_SEL_image_read_wavefronts', - 38: 'TA_PERF_SEL_image_store_wavefronts', - 39: 'TA_PERF_SEL_image_atomic_wavefronts', - 40: 'TA_PERF_SEL_image_sampler_total_cycles', - 41: 'TA_PERF_SEL_image_nosampler_total_cycles', - 42: 'TA_PERF_SEL_flat_total_cycles', - 44: 'TA_PERF_SEL_buffer_wavefronts', - 45: 'TA_PERF_SEL_buffer_load_wavefronts', - 46: 'TA_PERF_SEL_buffer_store_wavefronts', - 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', - 49: 'TA_PERF_SEL_buffer_total_cycles', - 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 52: 'TA_PERF_SEL_buffer_has_index_instructions', - 53: 'TA_PERF_SEL_buffer_has_offset_instructions', - 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 56: 'TA_PERF_SEL_image_sampler_wavefronts', - 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 58: 'TA_PERF_SEL_addresser_stalled_cycles', - 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 60: 'TA_PERF_SEL_aniso_stalled_cycles', - 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 62: 'TA_PERF_SEL_deriv_stalled_cycles', - 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 64: 'TA_PERF_SEL_color_1_cycle_quads', - 65: 'TA_PERF_SEL_color_2_cycle_quads', - 66: 'TA_PERF_SEL_color_3_cycle_quads', - 68: 'TA_PERF_SEL_mip_1_cycle_quads', - 69: 'TA_PERF_SEL_mip_2_cycle_quads', - 70: 'TA_PERF_SEL_vol_1_cycle_quads', - 71: 'TA_PERF_SEL_vol_2_cycle_quads', - 72: 'TA_PERF_SEL_sampler_op_quads', - 73: 'TA_PERF_SEL_mipmap_lod_0_samples', - 74: 'TA_PERF_SEL_mipmap_lod_1_samples', - 75: 'TA_PERF_SEL_mipmap_lod_2_samples', - 76: 'TA_PERF_SEL_mipmap_lod_3_samples', - 77: 'TA_PERF_SEL_mipmap_lod_4_samples', - 78: 'TA_PERF_SEL_mipmap_lod_5_samples', - 79: 'TA_PERF_SEL_mipmap_lod_6_samples', - 80: 'TA_PERF_SEL_mipmap_lod_7_samples', - 81: 'TA_PERF_SEL_mipmap_lod_8_samples', - 82: 'TA_PERF_SEL_mipmap_lod_9_samples', - 83: 'TA_PERF_SEL_mipmap_lod_10_samples', - 84: 'TA_PERF_SEL_mipmap_lod_11_samples', - 85: 'TA_PERF_SEL_mipmap_lod_12_samples', - 86: 'TA_PERF_SEL_mipmap_lod_13_samples', - 87: 'TA_PERF_SEL_mipmap_lod_14_samples', - 88: 'TA_PERF_SEL_mipmap_invalid_samples', - 89: 'TA_PERF_SEL_aniso_1_cycle_quads', - 90: 'TA_PERF_SEL_aniso_2_cycle_quads', - 91: 'TA_PERF_SEL_aniso_4_cycle_quads', - 92: 'TA_PERF_SEL_aniso_6_cycle_quads', - 93: 'TA_PERF_SEL_aniso_8_cycle_quads', - 94: 'TA_PERF_SEL_aniso_10_cycle_quads', - 95: 'TA_PERF_SEL_aniso_12_cycle_quads', - 96: 'TA_PERF_SEL_aniso_14_cycle_quads', - 97: 'TA_PERF_SEL_aniso_16_cycle_quads', - 98: 'TA_PERF_SEL_store_write_data_input_cycles', - 99: 'TA_PERF_SEL_store_write_data_output_cycles', - 100: 'TA_PERF_SEL_flat_wavefronts', - 101: 'TA_PERF_SEL_flat_load_wavefronts', - 102: 'TA_PERF_SEL_flat_store_wavefronts', - 103: 'TA_PERF_SEL_flat_atomic_wavefronts', - 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 105: 'TA_PERF_SEL_register_clk_valid_cycles', - 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 108: 'TA_PERF_SEL_flat_2_address_input_vgpr_instructions', - 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 112: 'TA_PERF_SEL_mipmap_lod_15_samples', - 113: 'TA_PERF_SEL_mipmap_lod_16_samples', - 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 117: 'TA_PERF_SEL_store_has_x_instructions', - 118: 'TA_PERF_SEL_store_has_y_instructions', - 119: 'TA_PERF_SEL_store_has_z_instructions', - 120: 'TA_PERF_SEL_store_has_w_instructions', - 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 128: 'TA_PERF_SEL_in_busy', - 129: 'TA_PERF_SEL_in_fifos_busy', - 130: 'TA_PERF_SEL_in_cfifo_busy', - 131: 'TA_PERF_SEL_in_qfifo_busy', - 132: 'TA_PERF_SEL_in_wfifo_busy', - 133: 'TA_PERF_SEL_in_rfifo_busy', - 134: 'TA_PERF_SEL_bf_busy', - 135: 'TA_PERF_SEL_ns_busy', - 136: 'TA_PERF_SEL_smp_busy_ns_idle', - 137: 'TA_PERF_SEL_smp_idle_ns_busy', - 144: 'TA_PERF_SEL_vmemcmd_cycles', - 145: 'TA_PERF_SEL_vmemreq_cycles', - 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', - 150: 'TA_PERF_SEL_in_addr_cycles', - 151: 'TA_PERF_SEL_in_data_cycles', - 160: 'TA_PERF_SEL_point_sampled_quads', - 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', - 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', - 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 192: 'TA_PERF_SEL_image_sampler_1_op_burst', - 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 196: 'TA_PERF_SEL_image_linked_1_op_burst', - 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', - 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', - 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', - 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', - 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', - 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 212: 'TA_PERF_SEL_write_1_op_burst', - 213: 'TA_PERF_SEL_write_2to3_op_burst', - 214: 'TA_PERF_SEL_write_4to31_op_burst', - 215: 'TA_PERF_SEL_write_ge32_op_burst', - 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', - 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', - 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', - 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', - 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', - 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', - 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', - 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', -} -TA_PERF_SEL_NULL = 0 -TA_PERF_SEL_image_sampler_has_offset_instructions = 1 -TA_PERF_SEL_image_sampler_has_bias_instructions = 2 -TA_PERF_SEL_image_sampler_has_reference_instructions = 3 -TA_PERF_SEL_image_sampler_has_ds_instructions = 4 -TA_PERF_SEL_image_sampler_has_dt_instructions = 5 -TA_PERF_SEL_image_sampler_has_dr_instructions = 6 -TA_PERF_SEL_gradient_busy = 7 -TA_PERF_SEL_gradient_fifo_busy = 8 -TA_PERF_SEL_lod_busy = 9 -TA_PERF_SEL_lod_fifo_busy = 10 -TA_PERF_SEL_addresser_busy = 11 -TA_PERF_SEL_addresser_fifo_busy = 12 -TA_PERF_SEL_aligner_busy = 13 -TA_PERF_SEL_write_path_busy = 14 -TA_PERF_SEL_ta_busy = 15 -TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 -TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 -TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 -TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 -TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 -TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 -TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 -TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 -TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 -TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 -TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 -TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 -TA_PERF_SEL_image_sampler_has_t_instructions = 28 -TA_PERF_SEL_image_sampler_has_r_instructions = 29 -TA_PERF_SEL_image_sampler_has_q_instructions = 30 -TA_PERF_SEL_total_wavefronts = 32 -TA_PERF_SEL_gradient_cycles = 33 -TA_PERF_SEL_walker_cycles = 34 -TA_PERF_SEL_aligner_cycles = 35 -TA_PERF_SEL_image_wavefronts = 36 -TA_PERF_SEL_image_read_wavefronts = 37 -TA_PERF_SEL_image_store_wavefronts = 38 -TA_PERF_SEL_image_atomic_wavefronts = 39 -TA_PERF_SEL_image_sampler_total_cycles = 40 -TA_PERF_SEL_image_nosampler_total_cycles = 41 -TA_PERF_SEL_flat_total_cycles = 42 -TA_PERF_SEL_buffer_wavefronts = 44 -TA_PERF_SEL_buffer_load_wavefronts = 45 -TA_PERF_SEL_buffer_store_wavefronts = 46 -TA_PERF_SEL_buffer_atomic_wavefronts = 47 -TA_PERF_SEL_buffer_total_cycles = 49 -TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 -TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 -TA_PERF_SEL_buffer_has_index_instructions = 52 -TA_PERF_SEL_buffer_has_offset_instructions = 53 -TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 -TA_PERF_SEL_addr_stalled_by_td_cycles = 55 -TA_PERF_SEL_image_sampler_wavefronts = 56 -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 -TA_PERF_SEL_addresser_stalled_cycles = 58 -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 -TA_PERF_SEL_aniso_stalled_cycles = 60 -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 -TA_PERF_SEL_deriv_stalled_cycles = 62 -TA_PERF_SEL_aniso_gt1_cycle_quads = 63 -TA_PERF_SEL_color_1_cycle_quads = 64 -TA_PERF_SEL_color_2_cycle_quads = 65 -TA_PERF_SEL_color_3_cycle_quads = 66 -TA_PERF_SEL_mip_1_cycle_quads = 68 -TA_PERF_SEL_mip_2_cycle_quads = 69 -TA_PERF_SEL_vol_1_cycle_quads = 70 -TA_PERF_SEL_vol_2_cycle_quads = 71 -TA_PERF_SEL_sampler_op_quads = 72 -TA_PERF_SEL_mipmap_lod_0_samples = 73 -TA_PERF_SEL_mipmap_lod_1_samples = 74 -TA_PERF_SEL_mipmap_lod_2_samples = 75 -TA_PERF_SEL_mipmap_lod_3_samples = 76 -TA_PERF_SEL_mipmap_lod_4_samples = 77 -TA_PERF_SEL_mipmap_lod_5_samples = 78 -TA_PERF_SEL_mipmap_lod_6_samples = 79 -TA_PERF_SEL_mipmap_lod_7_samples = 80 -TA_PERF_SEL_mipmap_lod_8_samples = 81 -TA_PERF_SEL_mipmap_lod_9_samples = 82 -TA_PERF_SEL_mipmap_lod_10_samples = 83 -TA_PERF_SEL_mipmap_lod_11_samples = 84 -TA_PERF_SEL_mipmap_lod_12_samples = 85 -TA_PERF_SEL_mipmap_lod_13_samples = 86 -TA_PERF_SEL_mipmap_lod_14_samples = 87 -TA_PERF_SEL_mipmap_invalid_samples = 88 -TA_PERF_SEL_aniso_1_cycle_quads = 89 -TA_PERF_SEL_aniso_2_cycle_quads = 90 -TA_PERF_SEL_aniso_4_cycle_quads = 91 -TA_PERF_SEL_aniso_6_cycle_quads = 92 -TA_PERF_SEL_aniso_8_cycle_quads = 93 -TA_PERF_SEL_aniso_10_cycle_quads = 94 -TA_PERF_SEL_aniso_12_cycle_quads = 95 -TA_PERF_SEL_aniso_14_cycle_quads = 96 -TA_PERF_SEL_aniso_16_cycle_quads = 97 -TA_PERF_SEL_store_write_data_input_cycles = 98 -TA_PERF_SEL_store_write_data_output_cycles = 99 -TA_PERF_SEL_flat_wavefronts = 100 -TA_PERF_SEL_flat_load_wavefronts = 101 -TA_PERF_SEL_flat_store_wavefronts = 102 -TA_PERF_SEL_flat_atomic_wavefronts = 103 -TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 -TA_PERF_SEL_register_clk_valid_cycles = 105 -TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 -TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 -TA_PERF_SEL_flat_2_address_input_vgpr_instructions = 108 -TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 -TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 -TA_PERF_SEL_mipmap_lod_15_samples = 112 -TA_PERF_SEL_mipmap_lod_16_samples = 113 -TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 -TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 -TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 -TA_PERF_SEL_store_has_x_instructions = 117 -TA_PERF_SEL_store_has_y_instructions = 118 -TA_PERF_SEL_store_has_z_instructions = 119 -TA_PERF_SEL_store_has_w_instructions = 120 -TA_PERF_SEL_image_nosampler_has_t_instructions = 121 -TA_PERF_SEL_image_nosampler_has_r_instructions = 122 -TA_PERF_SEL_image_nosampler_has_q_instructions = 123 -TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 -TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 -TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 -TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 -TA_PERF_SEL_in_busy = 128 -TA_PERF_SEL_in_fifos_busy = 129 -TA_PERF_SEL_in_cfifo_busy = 130 -TA_PERF_SEL_in_qfifo_busy = 131 -TA_PERF_SEL_in_wfifo_busy = 132 -TA_PERF_SEL_in_rfifo_busy = 133 -TA_PERF_SEL_bf_busy = 134 -TA_PERF_SEL_ns_busy = 135 -TA_PERF_SEL_smp_busy_ns_idle = 136 -TA_PERF_SEL_smp_idle_ns_busy = 137 -TA_PERF_SEL_vmemcmd_cycles = 144 -TA_PERF_SEL_vmemreq_cycles = 145 -TA_PERF_SEL_in_waiting_on_req_cycles = 146 -TA_PERF_SEL_in_addr_cycles = 150 -TA_PERF_SEL_in_data_cycles = 151 -TA_PERF_SEL_point_sampled_quads = 160 -TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 -TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 -TA_PERF_SEL_atomic_write_data_input_cycles = 164 -TA_PERF_SEL_atomic_write_data_output_cycles = 165 -TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 -TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 -TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 -TA_PERF_SEL_image_sampler_1_op_burst = 192 -TA_PERF_SEL_image_sampler_2to3_op_burst = 193 -TA_PERF_SEL_image_sampler_4to7_op_burst = 194 -TA_PERF_SEL_image_sampler_ge8_op_burst = 195 -TA_PERF_SEL_image_linked_1_op_burst = 196 -TA_PERF_SEL_image_linked_2to3_op_burst = 197 -TA_PERF_SEL_image_linked_4to7_op_burst = 198 -TA_PERF_SEL_image_linked_ge8_op_burst = 199 -TA_PERF_SEL_image_nosampler_1_op_burst = 204 -TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 -TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 -TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 -TA_PERF_SEL_buffer_flat_1_op_burst = 208 -TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 -TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 -TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 -TA_PERF_SEL_write_1_op_burst = 212 -TA_PERF_SEL_write_2to3_op_burst = 213 -TA_PERF_SEL_write_4to31_op_burst = 214 -TA_PERF_SEL_write_ge32_op_burst = 215 -TA_PERF_SEL_ibubble_1_cycle_burst = 216 -TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 -TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 -TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 -TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 -TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 -TA_PERF_SEL_sampler_clk_valid_cycles = 224 -TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 -TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 -TA_PERF_SEL_write_data_clk_valid_cycles = 227 -TA_PERF_SEL_gradient_clk_valid_cycles = 228 -TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 -TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 -TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 -TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 -TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 -TA_PERF_SEL_aligner_clk_valid_cycles = 234 -TA_PERF_SEL_tcreq_clk_valid_cycles = 235 -TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BC_SWIZZLE' -TEX_BC_SWIZZLE__enumvalues = { - 0: 'TEX_BC_Swizzle_XYZW', - 1: 'TEX_BC_Swizzle_XWYZ', - 2: 'TEX_BC_Swizzle_WZYX', - 3: 'TEX_BC_Swizzle_WXYZ', - 4: 'TEX_BC_Swizzle_ZYXW', - 5: 'TEX_BC_Swizzle_YXWZ', -} -TEX_BC_Swizzle_XYZW = 0 -TEX_BC_Swizzle_XWYZ = 1 -TEX_BC_Swizzle_WZYX = 2 -TEX_BC_Swizzle_WXYZ = 3 -TEX_BC_Swizzle_ZYXW = 4 -TEX_BC_Swizzle_YXWZ = 5 -TEX_BC_SWIZZLE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BORDER_COLOR_TYPE' -TEX_BORDER_COLOR_TYPE__enumvalues = { - 0: 'TEX_BorderColor_TransparentBlack', - 1: 'TEX_BorderColor_OpaqueBlack', - 2: 'TEX_BorderColor_OpaqueWhite', - 3: 'TEX_BorderColor_Register', -} -TEX_BorderColor_TransparentBlack = 0 -TEX_BorderColor_OpaqueBlack = 1 -TEX_BorderColor_OpaqueWhite = 2 -TEX_BorderColor_Register = 3 -TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CHROMA_KEY' -TEX_CHROMA_KEY__enumvalues = { - 0: 'TEX_ChromaKey_Disabled', - 1: 'TEX_ChromaKey_Kill', - 2: 'TEX_ChromaKey_Blend', - 3: 'TEX_ChromaKey_RESERVED_3', -} -TEX_ChromaKey_Disabled = 0 -TEX_ChromaKey_Kill = 1 -TEX_ChromaKey_Blend = 2 -TEX_ChromaKey_RESERVED_3 = 3 -TEX_CHROMA_KEY = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CLAMP' -TEX_CLAMP__enumvalues = { - 0: 'TEX_Clamp_Repeat', - 1: 'TEX_Clamp_Mirror', - 2: 'TEX_Clamp_ClampToLast', - 3: 'TEX_Clamp_MirrorOnceToLast', - 4: 'TEX_Clamp_ClampHalfToBorder', - 5: 'TEX_Clamp_MirrorOnceHalfToBorder', - 6: 'TEX_Clamp_ClampToBorder', - 7: 'TEX_Clamp_MirrorOnceToBorder', -} -TEX_Clamp_Repeat = 0 -TEX_Clamp_Mirror = 1 -TEX_Clamp_ClampToLast = 2 -TEX_Clamp_MirrorOnceToLast = 3 -TEX_Clamp_ClampHalfToBorder = 4 -TEX_Clamp_MirrorOnceHalfToBorder = 5 -TEX_Clamp_ClampToBorder = 6 -TEX_Clamp_MirrorOnceToBorder = 7 -TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_COORD_TYPE' -TEX_COORD_TYPE__enumvalues = { - 0: 'TEX_CoordType_Unnormalized', - 1: 'TEX_CoordType_Normalized', -} -TEX_CoordType_Unnormalized = 0 -TEX_CoordType_Normalized = 1 -TEX_COORD_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' -TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { - 0: 'TEX_DepthCompareFunction_Never', - 1: 'TEX_DepthCompareFunction_Less', - 2: 'TEX_DepthCompareFunction_Equal', - 3: 'TEX_DepthCompareFunction_LessEqual', - 4: 'TEX_DepthCompareFunction_Greater', - 5: 'TEX_DepthCompareFunction_NotEqual', - 6: 'TEX_DepthCompareFunction_GreaterEqual', - 7: 'TEX_DepthCompareFunction_Always', -} -TEX_DepthCompareFunction_Never = 0 -TEX_DepthCompareFunction_Less = 1 -TEX_DepthCompareFunction_Equal = 2 -TEX_DepthCompareFunction_LessEqual = 3 -TEX_DepthCompareFunction_Greater = 4 -TEX_DepthCompareFunction_NotEqual = 5 -TEX_DepthCompareFunction_GreaterEqual = 6 -TEX_DepthCompareFunction_Always = 7 -TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_FORMAT_COMP' -TEX_FORMAT_COMP__enumvalues = { - 0: 'TEX_FormatComp_Unsigned', - 1: 'TEX_FormatComp_Signed', - 2: 'TEX_FormatComp_UnsignedBiased', - 3: 'TEX_FormatComp_RESERVED_3', -} -TEX_FormatComp_Unsigned = 0 -TEX_FormatComp_Signed = 1 -TEX_FormatComp_UnsignedBiased = 2 -TEX_FormatComp_RESERVED_3 = 3 -TEX_FORMAT_COMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MAX_ANISO_RATIO' -TEX_MAX_ANISO_RATIO__enumvalues = { - 0: 'TEX_MaxAnisoRatio_1to1', - 1: 'TEX_MaxAnisoRatio_2to1', - 2: 'TEX_MaxAnisoRatio_4to1', - 3: 'TEX_MaxAnisoRatio_8to1', - 4: 'TEX_MaxAnisoRatio_16to1', - 5: 'TEX_MaxAnisoRatio_RESERVED_5', - 6: 'TEX_MaxAnisoRatio_RESERVED_6', - 7: 'TEX_MaxAnisoRatio_RESERVED_7', -} -TEX_MaxAnisoRatio_1to1 = 0 -TEX_MaxAnisoRatio_2to1 = 1 -TEX_MaxAnisoRatio_4to1 = 2 -TEX_MaxAnisoRatio_8to1 = 3 -TEX_MaxAnisoRatio_16to1 = 4 -TEX_MaxAnisoRatio_RESERVED_5 = 5 -TEX_MaxAnisoRatio_RESERVED_6 = 6 -TEX_MaxAnisoRatio_RESERVED_7 = 7 -TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MIP_FILTER' -TEX_MIP_FILTER__enumvalues = { - 0: 'TEX_MipFilter_None', - 1: 'TEX_MipFilter_Point', - 2: 'TEX_MipFilter_Linear', - 3: 'TEX_MipFilter_Point_Aniso_Adj', -} -TEX_MipFilter_None = 0 -TEX_MipFilter_Point = 1 -TEX_MipFilter_Linear = 2 -TEX_MipFilter_Point_Aniso_Adj = 3 -TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_REQUEST_SIZE' -TEX_REQUEST_SIZE__enumvalues = { - 0: 'TEX_RequestSize_32B', - 1: 'TEX_RequestSize_64B', - 2: 'TEX_RequestSize_128B', - 3: 'TEX_RequestSize_2X64B', -} -TEX_RequestSize_32B = 0 -TEX_RequestSize_64B = 1 -TEX_RequestSize_128B = 2 -TEX_RequestSize_2X64B = 3 -TEX_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_SAMPLER_TYPE' -TEX_SAMPLER_TYPE__enumvalues = { - 0: 'TEX_SamplerType_Invalid', - 1: 'TEX_SamplerType_Valid', -} -TEX_SamplerType_Invalid = 0 -TEX_SamplerType_Valid = 1 -TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_XY_FILTER' -TEX_XY_FILTER__enumvalues = { - 0: 'TEX_XYFilter_Point', - 1: 'TEX_XYFilter_Linear', - 2: 'TEX_XYFilter_AnisoPoint', - 3: 'TEX_XYFilter_AnisoLinear', -} -TEX_XYFilter_Point = 0 -TEX_XYFilter_Linear = 1 -TEX_XYFilter_AnisoPoint = 2 -TEX_XYFilter_AnisoLinear = 3 -TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_Z_FILTER' -TEX_Z_FILTER__enumvalues = { - 0: 'TEX_ZFilter_None', - 1: 'TEX_ZFilter_Point', - 2: 'TEX_ZFilter_Linear', - 3: 'TEX_ZFilter_RESERVED_3', -} -TEX_ZFilter_None = 0 -TEX_ZFilter_Point = 1 -TEX_ZFilter_Linear = 2 -TEX_ZFilter_RESERVED_3 = 3 -TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_TYPE' -TVX_TYPE__enumvalues = { - 0: 'TVX_Type_InvalidTextureResource', - 1: 'TVX_Type_InvalidVertexBuffer', - 2: 'TVX_Type_ValidTextureResource', - 3: 'TVX_Type_ValidVertexBuffer', -} -TVX_Type_InvalidTextureResource = 0 -TVX_Type_InvalidVertexBuffer = 1 -TVX_Type_ValidTextureResource = 2 -TVX_Type_ValidVertexBuffer = 3 -TVX_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_ADDR_MODES' -TA_TC_ADDR_MODES__enumvalues = { - 0: 'TA_TC_ADDR_MODE_DEFAULT', - 1: 'TA_TC_ADDR_MODE_COMP0', - 2: 'TA_TC_ADDR_MODE_COMP1', - 3: 'TA_TC_ADDR_MODE_COMP2', - 4: 'TA_TC_ADDR_MODE_COMP3', - 5: 'TA_TC_ADDR_MODE_UNALIGNED', - 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', -} -TA_TC_ADDR_MODE_DEFAULT = 0 -TA_TC_ADDR_MODE_COMP0 = 1 -TA_TC_ADDR_MODE_COMP1 = 2 -TA_TC_ADDR_MODE_COMP2 = 3 -TA_TC_ADDR_MODE_COMP3 = 4 -TA_TC_ADDR_MODE_UNALIGNED = 5 -TA_TC_ADDR_MODE_BORDER_COLOR = 6 -TA_TC_ADDR_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_REQ_MODES' -TA_TC_REQ_MODES__enumvalues = { - 0: 'TA_TC_REQ_MODE_BORDER', - 1: 'TA_TC_REQ_MODE_TEX2', - 2: 'TA_TC_REQ_MODE_TEX1', - 3: 'TA_TC_REQ_MODE_TEX0', - 4: 'TA_TC_REQ_MODE_NORMAL', - 5: 'TA_TC_REQ_MODE_DWORD', - 6: 'TA_TC_REQ_MODE_BYTE', - 7: 'TA_TC_REQ_MODE_BYTE_NV', -} -TA_TC_REQ_MODE_BORDER = 0 -TA_TC_REQ_MODE_TEX2 = 1 -TA_TC_REQ_MODE_TEX1 = 2 -TA_TC_REQ_MODE_TEX0 = 3 -TA_TC_REQ_MODE_NORMAL = 4 -TA_TC_REQ_MODE_DWORD = 5 -TA_TC_REQ_MODE_BYTE = 6 -TA_TC_REQ_MODE_BYTE_NV = 7 -TA_TC_REQ_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_POLICIES' -TCP_CACHE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_POLICY_MISS_LRU', - 1: 'TCP_CACHE_POLICY_MISS_EVICT', - 2: 'TCP_CACHE_POLICY_HIT_LRU', - 3: 'TCP_CACHE_POLICY_HIT_EVICT', -} -TCP_CACHE_POLICY_MISS_LRU = 0 -TCP_CACHE_POLICY_MISS_EVICT = 1 -TCP_CACHE_POLICY_HIT_LRU = 2 -TCP_CACHE_POLICY_HIT_EVICT = 3 -TCP_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_STORE_POLICIES' -TCP_CACHE_STORE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', - 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', -} -TCP_CACHE_STORE_POLICY_WT_LRU = 0 -TCP_CACHE_STORE_POLICY_WT_EVICT = 1 -TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_COMPRESSION_BYPASS' -TCP_COMPRESSION_BYPASS__enumvalues = { - 0: 'TCP_COMPRESSION_BYPASS_DIS', - 1: 'TCP_COMPRESSION_BYPASS_EN', -} -TCP_COMPRESSION_BYPASS_DIS = 0 -TCP_COMPRESSION_BYPASS_EN = 1 -TCP_COMPRESSION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_COMPRESSION_OVERRIDE' -TCP_COMPRESSION_OVERRIDE__enumvalues = { - 0: 'TCP_COMPRESSION_OVERRIDE_DIS', - 1: 'TCP_COMPRESSION_OVERRIDE_EN', -} -TCP_COMPRESSION_OVERRIDE_DIS = 0 -TCP_COMPRESSION_OVERRIDE_EN = 1 -TCP_COMPRESSION_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_OPCODE_TYPE' -TCP_OPCODE_TYPE__enumvalues = { - 0: 'TCP_OPCODE_READ', - 1: 'TCP_OPCODE_WRITE', - 2: 'TCP_OPCODE_ATOMIC', - 3: 'TCP_OPCODE_INV', - 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', - 5: 'TCP_OPCODE_SAMPLER', - 6: 'TCP_OPCODE_LOAD', - 7: 'TCP_OPCODE_GATHERH', -} -TCP_OPCODE_READ = 0 -TCP_OPCODE_WRITE = 1 -TCP_OPCODE_ATOMIC = 2 -TCP_OPCODE_INV = 3 -TCP_OPCODE_ATOMIC_CMPSWAP = 4 -TCP_OPCODE_SAMPLER = 5 -TCP_OPCODE_LOAD = 6 -TCP_OPCODE_GATHERH = 7 -TCP_OPCODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_PERFCOUNT_SELECT' -TCP_PERFCOUNT_SELECT__enumvalues = { - 0: 'TCP_PERF_SEL_GATE_EN1', - 1: 'TCP_PERF_SEL_GATE_EN2', - 2: 'TCP_PERF_SEL_TA_REQ', - 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', - 4: 'TCP_PERF_SEL_TA_REQ_READ', - 5: 'TCP_PERF_SEL_TA_REQ_WRITE', - 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', - 9: 'TCP_PERF_SEL_REQ', - 10: 'TCP_PERF_SEL_REQ_READ', - 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 14: 'TCP_PERF_SEL_REQ_WRITE', - 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 16: 'TCP_PERF_SEL_REQ_NON_READ', - 17: 'TCP_PERF_SEL_REQ_MISS', - 18: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 20: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 22: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 24: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', - 26: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', - 30: 'TCP_PERF_SEL_GL1_REQ_READ', - 31: 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 32: 'TCP_PERF_SEL_GL1_REQ_READ_64B', - 33: 'TCP_PERF_SEL_GL1_REQ_WRITE', - 34: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 36: 'TCP_PERF_SEL_GL1_READ_LATENCY', - 37: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', - 38: 'TCP_PERF_SEL_TCP_LATENCY', - 39: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 40: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', - 41: 'TCP_PERF_SEL_DATA_FIFO_STALL', - 42: 'TCP_PERF_SEL_LOD_STALL', - 43: 'TCP_PERF_SEL_POWER_STALL', - 44: 'TCP_PERF_SEL_ALLOC_STALL', - 46: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', - 47: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', - 48: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 49: 'TCP_PERF_SEL_LFIFO_STALL', - 50: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 51: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 52: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 53: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 54: 'TCP_PERF_SEL_GL1_PENDING_STALL', - 55: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', - 56: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 57: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 58: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 59: 'TCP_PERF_SEL_TD_TCP_STALL', - 60: 'TCP_PERF_SEL_TA_REQ_BUFFERNOP', - 61: 'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE', - 62: 'TCP_PERF_SEL_TAGFAKE_EOW', - 63: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID', - 64: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0', - 65: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2', - 66: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4', - 67: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8', - 68: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16', - 70: 'TCP_PERF_SEL_BURST_BIN_READHIT_0', - 71: 'TCP_PERF_SEL_BURST_BIN_READHIT_1', - 72: 'TCP_PERF_SEL_BURST_BIN_READHIT_2to4', - 73: 'TCP_PERF_SEL_BURST_BIN_READHIT_5to8', - 74: 'TCP_PERF_SEL_BURST_BIN_READHIT_9to16', - 75: 'TCP_PERF_SEL_BURST_BIN_READHIT_gt16', - 76: 'TCP_PERF_SEL_TA_TC_REQ_EN_SUM', - 77: 'TCP_PERF_SEL_GL1_REQ_LU', - 78: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE', -} -TCP_PERF_SEL_GATE_EN1 = 0 -TCP_PERF_SEL_GATE_EN2 = 1 -TCP_PERF_SEL_TA_REQ = 2 -TCP_PERF_SEL_TA_REQ_STATE_READ = 3 -TCP_PERF_SEL_TA_REQ_READ = 4 -TCP_PERF_SEL_TA_REQ_WRITE = 5 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 -TCP_PERF_SEL_TA_REQ_GL0_INV = 8 -TCP_PERF_SEL_REQ = 9 -TCP_PERF_SEL_REQ_READ = 10 -TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 -TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 -TCP_PERF_SEL_REQ_WRITE = 14 -TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 -TCP_PERF_SEL_REQ_NON_READ = 16 -TCP_PERF_SEL_REQ_MISS = 17 -TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 18 -TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 19 -TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 20 -TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 21 -TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 22 -TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 23 -TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 24 -TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 25 -TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 26 -TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 27 -TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 28 -TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 29 -TCP_PERF_SEL_GL1_REQ_READ = 30 -TCP_PERF_SEL_GL1_REQ_READ_128B = 31 -TCP_PERF_SEL_GL1_REQ_READ_64B = 32 -TCP_PERF_SEL_GL1_REQ_WRITE = 33 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 34 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 35 -TCP_PERF_SEL_GL1_READ_LATENCY = 36 -TCP_PERF_SEL_GL1_WRITE_LATENCY = 37 -TCP_PERF_SEL_TCP_LATENCY = 38 -TCP_PERF_SEL_TCP_TA_REQ_STALL = 39 -TCP_PERF_SEL_TA_TCP_REQ_STARVE = 40 -TCP_PERF_SEL_DATA_FIFO_STALL = 41 -TCP_PERF_SEL_LOD_STALL = 42 -TCP_PERF_SEL_POWER_STALL = 43 -TCP_PERF_SEL_ALLOC_STALL = 44 -TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 46 -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 47 -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 48 -TCP_PERF_SEL_LFIFO_STALL = 49 -TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 50 -TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 51 -TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 52 -TCP_PERF_SEL_GL1_GRANT_READ_STALL = 53 -TCP_PERF_SEL_GL1_PENDING_STALL = 54 -TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 55 -TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 56 -TCP_PERF_SEL_READ_DATACONFLICT_STALL = 57 -TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 58 -TCP_PERF_SEL_TD_TCP_STALL = 59 -TCP_PERF_SEL_TA_REQ_BUFFERNOP = 60 -TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE = 61 -TCP_PERF_SEL_TAGFAKE_EOW = 62 -TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID = 63 -TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0 = 64 -TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2 = 65 -TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4 = 66 -TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8 = 67 -TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16 = 68 -TCP_PERF_SEL_BURST_BIN_READHIT_0 = 70 -TCP_PERF_SEL_BURST_BIN_READHIT_1 = 71 -TCP_PERF_SEL_BURST_BIN_READHIT_2to4 = 72 -TCP_PERF_SEL_BURST_BIN_READHIT_5to8 = 73 -TCP_PERF_SEL_BURST_BIN_READHIT_9to16 = 74 -TCP_PERF_SEL_BURST_BIN_READHIT_gt16 = 75 -TCP_PERF_SEL_TA_TC_REQ_EN_SUM = 76 -TCP_PERF_SEL_GL1_REQ_LU = 77 -TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE = 78 -TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WATCH_MODES' -TCP_WATCH_MODES__enumvalues = { - 0: 'TCP_WATCH_MODE_READ', - 1: 'TCP_WATCH_MODE_NONREAD', - 2: 'TCP_WATCH_MODE_ATOMIC', - 3: 'TCP_WATCH_MODE_ALL', -} -TCP_WATCH_MODE_READ = 0 -TCP_WATCH_MODE_NONREAD = 1 -TCP_WATCH_MODE_ATOMIC = 2 -TCP_WATCH_MODE_ALL = 3 -TCP_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WRITE_COMPRESSION_DISABLE' -TCP_WRITE_COMPRESSION_DISABLE__enumvalues = { - 0: 'TCP_WRITE_COMPRESSION_DISABLE_DIS', - 1: 'TCP_WRITE_COMPRESSION_DISABLE_EN', -} -TCP_WRITE_COMPRESSION_DISABLE_DIS = 0 -TCP_WRITE_COMPRESSION_DISABLE_EN = 1 -TCP_WRITE_COMPRESSION_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'TD_PERFCOUNT_SEL' -TD_PERFCOUNT_SEL__enumvalues = { - 0: 'TD_PERF_SEL_none', - 1: 'TD_PERF_SEL_td_busy', - 2: 'TD_PERF_SEL_input_busy', - 3: 'TD_PERF_SEL_sampler_lerp_busy', - 4: 'TD_PERF_SEL_sampler_out_busy', - 5: 'TD_PERF_SEL_nofilter_busy', - 7: 'TD_PERF_SEL_sampler_core_sclk_en', - 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', - 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', - 12: 'TD_PERF_SEL_sampler_accum_sclk_en', - 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 15: 'TD_PERF_SEL_sampler_out_sclk_en', - 16: 'TD_PERF_SEL_nofilter_sclk_en', - 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', - 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', - 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 32: 'TD_PERF_SEL_core_state_ram_max_cnt', - 33: 'TD_PERF_SEL_core_state_rams_read', - 34: 'TD_PERF_SEL_weight_data_rams_read', - 35: 'TD_PERF_SEL_reference_data_rams_read', - 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', - 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', - 38: 'TD_PERF_SEL_tc_td_data_fifo_full', - 39: 'TD_PERF_SEL_input_state_fifo_full', - 40: 'TD_PERF_SEL_ta_data_stall', - 41: 'TD_PERF_SEL_tc_data_stall', - 42: 'TD_PERF_SEL_tc_ram_stall', - 43: 'TD_PERF_SEL_lds_stall', - 44: 'TD_PERF_SEL_sampler_pkr_full', - 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 46: 'TD_PERF_SEL_nofilter_pkr_full', - 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 50: 'TD_PERF_SEL_gather4_instr', - 51: 'TD_PERF_SEL_gather4h_instr', - 52: 'TD_PERF_SEL_getlod_instr', - 54: 'TD_PERF_SEL_sample_instr', - 55: 'TD_PERF_SEL_sample_c_instr', - 56: 'TD_PERF_SEL_load_instr', - 57: 'TD_PERF_SEL_ps_load_instr', - 58: 'TD_PERF_SEL_write_ack_instr', - 59: 'TD_PERF_SEL_d16_en_instr', - 60: 'TD_PERF_SEL_bypassLerp_instr', - 61: 'TD_PERF_SEL_min_max_filter_instr', - 62: 'TD_PERF_SEL_one_comp_return_instr', - 63: 'TD_PERF_SEL_two_comp_return_instr', - 64: 'TD_PERF_SEL_three_comp_return_instr', - 65: 'TD_PERF_SEL_four_comp_return_instr', - 66: 'TD_PERF_SEL_user_defined_border', - 67: 'TD_PERF_SEL_white_border', - 68: 'TD_PERF_SEL_opaque_black_border', - 69: 'TD_PERF_SEL_lod_warn_from_ta', - 70: 'TD_PERF_SEL_instruction_dest_is_lds', - 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 75: 'TD_PERF_SEL_out_of_order_instr', - 76: 'TD_PERF_SEL_total_num_instr', - 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 78: 'TD_PERF_SEL_total_num_sampler_instr', - 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 80: 'TD_PERF_SEL_total_num_nofilter_instr', - 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 84: 'TD_PERF_SEL_mixmode_instr', - 85: 'TD_PERF_SEL_mixmode_resource', - 86: 'TD_PERF_SEL_status_packet', - 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 91: 'TD_PERF_SEL_done_scoreboard_not_empty', - 92: 'TD_PERF_SEL_done_scoreboard_is_full', - 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', - 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', - 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 99: 'TD_PERF_SEL_msaa_load_instr', - 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 102: 'TD_PERF_SEL_resmap_instr', - 103: 'TD_PERF_SEL_prt_ack_instr', - 104: 'TD_PERF_SEL_resmap_with_volume_filtering', - 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', - 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', - 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', - 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 136: 'TD_PERF_SEL_burst_bin_sampler_1', - 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', - 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', - 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', - 140: 'TD_PERF_SEL_burst_bin_gather_1', - 141: 'TD_PERF_SEL_burst_bin_gather_2to8', - 142: 'TD_PERF_SEL_burst_bin_gather_9to16', - 143: 'TD_PERF_SEL_burst_bin_gather_gt16', - 144: 'TD_PERF_SEL_burst_bin_nofilter_1', - 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 181: 'TD_PERF_SEL_sampler_lerp0_active', - 182: 'TD_PERF_SEL_sampler_lerp1_active', - 183: 'TD_PERF_SEL_sampler_lerp2_active', - 184: 'TD_PERF_SEL_sampler_lerp3_active', - 185: 'TD_PERF_SEL_sampler_lerp4_active', - 186: 'TD_PERF_SEL_sampler_lerp5_active', - 187: 'TD_PERF_SEL_sampler_lerp6_active', - 188: 'TD_PERF_SEL_sampler_lerp7_active', - 189: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', - 190: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 191: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 192: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 193: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 194: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 195: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 200: 'TD_PERF_SEL_store_preempts_a_load', - 201: 'TD_PERF_SEL_sample_2x_instr', - 202: 'TD_PERF_SEL_gather4_2x_instr', - 203: 'TD_PERF_SEL_gather4h_2x_instr', - 204: 'TD_PERF_SEL_getlod_2x_instr', - 205: 'TD_PERF_SEL_resmap_2x_instr', - 206: 'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad', - 207: 'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit', - 208: 'TD_PERF_SEL_tri_proc_node_override_slot0', - 209: 'TD_PERF_SEL_tri_run_intersect_ahs_slot0', - 210: 'TD_PERF_SEL_tri_run_ahs_slot0', - 231: 'TD_PERF_SEL_tri_proc_node_override_slot1', - 232: 'TD_PERF_SEL_tri_run_intersect_ahs_slot1', - 233: 'TD_PERF_SEL_tri_run_ahs_slot1', - 241: 'TD_PERF_SEL_instance_mask_culled', - 242: 'TD_PERF_SEL_box_opaque_culled', - 243: 'TD_PERF_SEL_box_non_opaque_culled', - 244: 'TD_PERF_SEL_box_with_triangle_children_only_culled', - 245: 'TD_PERF_SEL_box_with_procedural_children_only_culled', - 246: 'TD_PERF_SEL_triangle_opaque_culled', - 247: 'TD_PERF_SEL_triangle_non_opaque_culled', - 248: 'TD_PERF_SEL_triangle_front_facing_culled', - 249: 'TD_PERF_SEL_triangle_back_facing_culled', -} -TD_PERF_SEL_none = 0 -TD_PERF_SEL_td_busy = 1 -TD_PERF_SEL_input_busy = 2 -TD_PERF_SEL_sampler_lerp_busy = 3 -TD_PERF_SEL_sampler_out_busy = 4 -TD_PERF_SEL_nofilter_busy = 5 -TD_PERF_SEL_sampler_core_sclk_en = 7 -TD_PERF_SEL_sampler_preformatter_sclk_en = 8 -TD_PERF_SEL_sampler_bilerp_sclk_en = 9 -TD_PERF_SEL_sampler_bypass_sclk_en = 10 -TD_PERF_SEL_sampler_minmax_sclk_en = 11 -TD_PERF_SEL_sampler_accum_sclk_en = 12 -TD_PERF_SEL_sampler_format_flt_sclk_en = 13 -TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 -TD_PERF_SEL_sampler_out_sclk_en = 15 -TD_PERF_SEL_nofilter_sclk_en = 16 -TD_PERF_SEL_nofilter_d32_sclk_en = 17 -TD_PERF_SEL_nofilter_d16_sclk_en = 18 -TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 -TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 -TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 -TD_PERF_SEL_core_state_ram_max_cnt = 32 -TD_PERF_SEL_core_state_rams_read = 33 -TD_PERF_SEL_weight_data_rams_read = 34 -TD_PERF_SEL_reference_data_rams_read = 35 -TD_PERF_SEL_tc_td_ram_fifo_full = 36 -TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 -TD_PERF_SEL_tc_td_data_fifo_full = 38 -TD_PERF_SEL_input_state_fifo_full = 39 -TD_PERF_SEL_ta_data_stall = 40 -TD_PERF_SEL_tc_data_stall = 41 -TD_PERF_SEL_tc_ram_stall = 42 -TD_PERF_SEL_lds_stall = 43 -TD_PERF_SEL_sampler_pkr_full = 44 -TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 -TD_PERF_SEL_nofilter_pkr_full = 46 -TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 -TD_PERF_SEL_gather4_instr = 50 -TD_PERF_SEL_gather4h_instr = 51 -TD_PERF_SEL_getlod_instr = 52 -TD_PERF_SEL_sample_instr = 54 -TD_PERF_SEL_sample_c_instr = 55 -TD_PERF_SEL_load_instr = 56 -TD_PERF_SEL_ps_load_instr = 57 -TD_PERF_SEL_write_ack_instr = 58 -TD_PERF_SEL_d16_en_instr = 59 -TD_PERF_SEL_bypassLerp_instr = 60 -TD_PERF_SEL_min_max_filter_instr = 61 -TD_PERF_SEL_one_comp_return_instr = 62 -TD_PERF_SEL_two_comp_return_instr = 63 -TD_PERF_SEL_three_comp_return_instr = 64 -TD_PERF_SEL_four_comp_return_instr = 65 -TD_PERF_SEL_user_defined_border = 66 -TD_PERF_SEL_white_border = 67 -TD_PERF_SEL_opaque_black_border = 68 -TD_PERF_SEL_lod_warn_from_ta = 69 -TD_PERF_SEL_instruction_dest_is_lds = 70 -TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 -TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 -TD_PERF_SEL_out_of_order_instr = 75 -TD_PERF_SEL_total_num_instr = 76 -TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 -TD_PERF_SEL_total_num_sampler_instr = 78 -TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 -TD_PERF_SEL_total_num_nofilter_instr = 80 -TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 -TD_PERF_SEL_mixmode_instr = 84 -TD_PERF_SEL_mixmode_resource = 85 -TD_PERF_SEL_status_packet = 86 -TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 -TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 -TD_PERF_SEL_done_scoreboard_not_empty = 91 -TD_PERF_SEL_done_scoreboard_is_full = 92 -TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 -TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 -TD_PERF_SEL_nofilter_formatters_turned_on = 95 -TD_PERF_SEL_nofilter_insert_extra_comps = 96 -TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 -TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 -TD_PERF_SEL_msaa_load_instr = 99 -TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 -TD_PERF_SEL_resmap_instr = 102 -TD_PERF_SEL_prt_ack_instr = 103 -TD_PERF_SEL_resmap_with_volume_filtering = 104 -TD_PERF_SEL_resmap_with_aniso_filtering = 105 -TD_PERF_SEL_resmap_with_no_more_filtering = 106 -TD_PERF_SEL_resmap_with_cubemap_corner = 107 -TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 -TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 -TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 -TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 -TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 -TD_PERF_SEL_burst_bin_sampler_1 = 136 -TD_PERF_SEL_burst_bin_sampler_2to8 = 137 -TD_PERF_SEL_burst_bin_sampler_9to16 = 138 -TD_PERF_SEL_burst_bin_sampler_gt16 = 139 -TD_PERF_SEL_burst_bin_gather_1 = 140 -TD_PERF_SEL_burst_bin_gather_2to8 = 141 -TD_PERF_SEL_burst_bin_gather_9to16 = 142 -TD_PERF_SEL_burst_bin_gather_gt16 = 143 -TD_PERF_SEL_burst_bin_nofilter_1 = 144 -TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 -TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 -TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 -TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 -TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 -TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 -TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 -TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 -TD_PERF_SEL_preempting_nofilter_max_cnt = 180 -TD_PERF_SEL_sampler_lerp0_active = 181 -TD_PERF_SEL_sampler_lerp1_active = 182 -TD_PERF_SEL_sampler_lerp2_active = 183 -TD_PERF_SEL_sampler_lerp3_active = 184 -TD_PERF_SEL_sampler_lerp4_active = 185 -TD_PERF_SEL_sampler_lerp5_active = 186 -TD_PERF_SEL_sampler_lerp6_active = 187 -TD_PERF_SEL_sampler_lerp7_active = 188 -TD_PERF_SEL_nofilter_total_num_comps_to_lds = 189 -TD_PERF_SEL_nofilter_byte_cycling_4cycles = 190 -TD_PERF_SEL_nofilter_byte_cycling_8cycles = 191 -TD_PERF_SEL_nofilter_byte_cycling_16cycles = 192 -TD_PERF_SEL_nofilter_dword_cycling_2cycles = 193 -TD_PERF_SEL_nofilter_dword_cycling_4cycles = 194 -TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 195 -TD_PERF_SEL_store_preempts_a_load = 200 -TD_PERF_SEL_sample_2x_instr = 201 -TD_PERF_SEL_gather4_2x_instr = 202 -TD_PERF_SEL_gather4h_2x_instr = 203 -TD_PERF_SEL_getlod_2x_instr = 204 -TD_PERF_SEL_resmap_2x_instr = 205 -TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad = 206 -TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit = 207 -TD_PERF_SEL_tri_proc_node_override_slot0 = 208 -TD_PERF_SEL_tri_run_intersect_ahs_slot0 = 209 -TD_PERF_SEL_tri_run_ahs_slot0 = 210 -TD_PERF_SEL_tri_proc_node_override_slot1 = 231 -TD_PERF_SEL_tri_run_intersect_ahs_slot1 = 232 -TD_PERF_SEL_tri_run_ahs_slot1 = 233 -TD_PERF_SEL_instance_mask_culled = 241 -TD_PERF_SEL_box_opaque_culled = 242 -TD_PERF_SEL_box_non_opaque_culled = 243 -TD_PERF_SEL_box_with_triangle_children_only_culled = 244 -TD_PERF_SEL_box_with_procedural_children_only_culled = 245 -TD_PERF_SEL_triangle_opaque_culled = 246 -TD_PERF_SEL_triangle_non_opaque_culled = 247 -TD_PERF_SEL_triangle_front_facing_culled = 248 -TD_PERF_SEL_triangle_back_facing_culled = 249 -TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2A_PERF_SEL' -GL2A_PERF_SEL__enumvalues = { - 0: 'GL2A_PERF_SEL_NONE', - 1: 'GL2A_PERF_SEL_CYCLE', - 2: 'GL2A_PERF_SEL_BUSY', - 3: 'GL2A_PERF_SEL_REQ_GL2C0', - 4: 'GL2A_PERF_SEL_REQ_GL2C1', - 5: 'GL2A_PERF_SEL_REQ_GL2C2', - 6: 'GL2A_PERF_SEL_REQ_GL2C3', - 7: 'GL2A_PERF_SEL_REQ_GL2C4', - 8: 'GL2A_PERF_SEL_REQ_GL2C5', - 9: 'GL2A_PERF_SEL_REQ_GL2C6', - 10: 'GL2A_PERF_SEL_REQ_GL2C7', - 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', - 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', - 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', - 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', - 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', - 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', - 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', - 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', - 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', - 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', - 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', - 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', - 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 43: 'GL2A_PERF_SEL_RTN_CLIENT0', - 44: 'GL2A_PERF_SEL_RTN_CLIENT1', - 45: 'GL2A_PERF_SEL_RTN_CLIENT2', - 46: 'GL2A_PERF_SEL_RTN_CLIENT3', - 47: 'GL2A_PERF_SEL_RTN_CLIENT4', - 48: 'GL2A_PERF_SEL_RTN_CLIENT5', - 49: 'GL2A_PERF_SEL_RTN_CLIENT6', - 50: 'GL2A_PERF_SEL_RTN_CLIENT7', - 51: 'GL2A_PERF_SEL_RTN_CLIENT8', - 52: 'GL2A_PERF_SEL_RTN_CLIENT9', - 53: 'GL2A_PERF_SEL_RTN_CLIENT10', - 54: 'GL2A_PERF_SEL_RTN_CLIENT11', - 55: 'GL2A_PERF_SEL_RTN_CLIENT12', - 56: 'GL2A_PERF_SEL_RTN_CLIENT13', - 57: 'GL2A_PERF_SEL_RTN_CLIENT14', - 58: 'GL2A_PERF_SEL_RTN_CLIENT15', - 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', -} -GL2A_PERF_SEL_NONE = 0 -GL2A_PERF_SEL_CYCLE = 1 -GL2A_PERF_SEL_BUSY = 2 -GL2A_PERF_SEL_REQ_GL2C0 = 3 -GL2A_PERF_SEL_REQ_GL2C1 = 4 -GL2A_PERF_SEL_REQ_GL2C2 = 5 -GL2A_PERF_SEL_REQ_GL2C3 = 6 -GL2A_PERF_SEL_REQ_GL2C4 = 7 -GL2A_PERF_SEL_REQ_GL2C5 = 8 -GL2A_PERF_SEL_REQ_GL2C6 = 9 -GL2A_PERF_SEL_REQ_GL2C7 = 10 -GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 -GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 -GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 -GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 -GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 -GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 -GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 -GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 -GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 -GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 -GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 -GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 -GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 -GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 -GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 -GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 -GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 -GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 -GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 -GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 -GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 -GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 -GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 -GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 -GL2A_PERF_SEL_RTN_CLIENT0 = 43 -GL2A_PERF_SEL_RTN_CLIENT1 = 44 -GL2A_PERF_SEL_RTN_CLIENT2 = 45 -GL2A_PERF_SEL_RTN_CLIENT3 = 46 -GL2A_PERF_SEL_RTN_CLIENT4 = 47 -GL2A_PERF_SEL_RTN_CLIENT5 = 48 -GL2A_PERF_SEL_RTN_CLIENT6 = 49 -GL2A_PERF_SEL_RTN_CLIENT7 = 50 -GL2A_PERF_SEL_RTN_CLIENT8 = 51 -GL2A_PERF_SEL_RTN_CLIENT9 = 52 -GL2A_PERF_SEL_RTN_CLIENT10 = 53 -GL2A_PERF_SEL_RTN_CLIENT11 = 54 -GL2A_PERF_SEL_RTN_CLIENT12 = 55 -GL2A_PERF_SEL_RTN_CLIENT13 = 56 -GL2A_PERF_SEL_RTN_CLIENT14 = 57 -GL2A_PERF_SEL_RTN_CLIENT15 = 58 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 -GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 -GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 -GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 -GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 -GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 -GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 -GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 -GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 -GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 -GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 -GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 -GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 -GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 -GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 -GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 -GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 -GL2A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2C_PERF_SEL' -GL2C_PERF_SEL__enumvalues = { - 0: 'GL2C_PERF_SEL_NONE', - 1: 'GL2C_PERF_SEL_CYCLE', - 2: 'GL2C_PERF_SEL_BUSY', - 3: 'GL2C_PERF_SEL_REQ', - 4: 'GL2C_PERF_SEL_VOL_REQ', - 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', - 6: 'GL2C_PERF_SEL_READ', - 7: 'GL2C_PERF_SEL_WRITE', - 8: 'GL2C_PERF_SEL_ATOMIC', - 9: 'GL2C_PERF_SEL_NOP_ACK', - 10: 'GL2C_PERF_SEL_NOP_RTN0', - 11: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', - 12: 'GL2C_PERF_SEL_METADATA_READ_REQ', - 13: 'GL2C_PERF_SEL_CLIENT0_REQ', - 14: 'GL2C_PERF_SEL_CLIENT1_REQ', - 15: 'GL2C_PERF_SEL_CLIENT2_REQ', - 16: 'GL2C_PERF_SEL_CLIENT3_REQ', - 17: 'GL2C_PERF_SEL_CLIENT4_REQ', - 18: 'GL2C_PERF_SEL_CLIENT5_REQ', - 19: 'GL2C_PERF_SEL_CLIENT6_REQ', - 20: 'GL2C_PERF_SEL_CLIENT7_REQ', - 21: 'GL2C_PERF_SEL_CLIENT8_REQ', - 22: 'GL2C_PERF_SEL_CLIENT9_REQ', - 23: 'GL2C_PERF_SEL_CLIENT10_REQ', - 24: 'GL2C_PERF_SEL_CLIENT11_REQ', - 25: 'GL2C_PERF_SEL_CLIENT12_REQ', - 26: 'GL2C_PERF_SEL_CLIENT13_REQ', - 27: 'GL2C_PERF_SEL_CLIENT14_REQ', - 28: 'GL2C_PERF_SEL_CLIENT15_REQ', - 29: 'GL2C_PERF_SEL_C_RW_S_REQ', - 30: 'GL2C_PERF_SEL_C_RW_US_REQ', - 31: 'GL2C_PERF_SEL_C_RO_S_REQ', - 32: 'GL2C_PERF_SEL_C_RO_US_REQ', - 33: 'GL2C_PERF_SEL_UC_REQ', - 34: 'GL2C_PERF_SEL_LRU_REQ', - 35: 'GL2C_PERF_SEL_STREAM_REQ', - 36: 'GL2C_PERF_SEL_BYPASS_REQ', - 37: 'GL2C_PERF_SEL_NOA_REQ', - 38: 'GL2C_PERF_SEL_SHARED_REQ', - 39: 'GL2C_PERF_SEL_HIT', - 40: 'GL2C_PERF_SEL_MISS', - 41: 'GL2C_PERF_SEL_FULL_HIT', - 42: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', - 43: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 44: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', - 45: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', - 46: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', - 47: 'GL2C_PERF_SEL_UNCACHED_WRITE', - 48: 'GL2C_PERF_SEL_WRITEBACK', - 49: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 50: 'GL2C_PERF_SEL_EVICT', - 51: 'GL2C_PERF_SEL_NORMAL_EVICT', - 52: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', - 53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', - 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 69: 'GL2C_PERF_SEL_READ_32_REQ', - 70: 'GL2C_PERF_SEL_READ_64_REQ', - 71: 'GL2C_PERF_SEL_READ_128_REQ', - 72: 'GL2C_PERF_SEL_WRITE_32_REQ', - 73: 'GL2C_PERF_SEL_WRITE_64_REQ', - 74: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 75: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 76: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 77: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 78: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 79: 'GL2C_PERF_SEL_MC_WRREQ', - 80: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', - 81: 'GL2C_PERF_SEL_EA_WRREQ_64B', - 82: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', - 83: 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 84: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 85: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 86: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 87: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 88: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', - 89: 'GL2C_PERF_SEL_EA_ATOMIC', - 90: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', - 91: 'GL2C_PERF_SEL_MC_RDREQ', - 92: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', - 93: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 94: 'GL2C_PERF_SEL_EA_RDREQ_32B', - 95: 'GL2C_PERF_SEL_EA_RDREQ_64B', - 96: 'GL2C_PERF_SEL_EA_RDREQ_96B', - 97: 'GL2C_PERF_SEL_EA_RDREQ_128B', - 98: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 99: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 100: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 101: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 102: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 103: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', - 104: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', - 105: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 106: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 107: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 108: 'GL2C_PERF_SEL_ONION_READ', - 109: 'GL2C_PERF_SEL_ONION_WRITE', - 110: 'GL2C_PERF_SEL_IO_READ', - 111: 'GL2C_PERF_SEL_IO_WRITE', - 112: 'GL2C_PERF_SEL_GARLIC_READ', - 113: 'GL2C_PERF_SEL_GARLIC_WRITE', - 114: 'GL2C_PERF_SEL_EA_OUTSTANDING', - 115: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 116: 'GL2C_PERF_SEL_SRC_FIFO_FULL', - 117: 'GL2C_PERF_SEL_TAG_STALL', - 118: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 119: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 120: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 121: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 122: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', - 123: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', - 124: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 125: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 126: 'GL2C_PERF_SEL_BUBBLE', - 127: 'GL2C_PERF_SEL_IB_REQ', - 128: 'GL2C_PERF_SEL_IB_STALL', - 129: 'GL2C_PERF_SEL_IB_TAG_STALL', - 130: 'GL2C_PERF_SEL_RETURN_ACK', - 131: 'GL2C_PERF_SEL_RETURN_DATA', - 132: 'GL2C_PERF_SEL_EA_RDRET_NACK', - 133: 'GL2C_PERF_SEL_EA_WRRET_NACK', - 134: 'GL2C_PERF_SEL_GL2A_LEVEL', - 135: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 136: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 137: 'GL2C_PERF_SEL_GCR_INV', - 138: 'GL2C_PERF_SEL_GCR_WB', - 139: 'GL2C_PERF_SEL_GCR_DISCARD', - 140: 'GL2C_PERF_SEL_GCR_RANGE', - 141: 'GL2C_PERF_SEL_GCR_ALL', - 142: 'GL2C_PERF_SEL_GCR_VOL', - 143: 'GL2C_PERF_SEL_GCR_UNSHARED', - 144: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 145: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 146: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', - 147: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', - 148: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 149: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 150: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 151: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 152: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 153: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 155: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 156: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', - 157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 158: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', - 159: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 160: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 161: 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 162: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 163: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 164: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 165: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', -} -GL2C_PERF_SEL_NONE = 0 -GL2C_PERF_SEL_CYCLE = 1 -GL2C_PERF_SEL_BUSY = 2 -GL2C_PERF_SEL_REQ = 3 -GL2C_PERF_SEL_VOL_REQ = 4 -GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 -GL2C_PERF_SEL_READ = 6 -GL2C_PERF_SEL_WRITE = 7 -GL2C_PERF_SEL_ATOMIC = 8 -GL2C_PERF_SEL_NOP_ACK = 9 -GL2C_PERF_SEL_NOP_RTN0 = 10 -GL2C_PERF_SEL_COMPRESSED_READ_REQ = 11 -GL2C_PERF_SEL_METADATA_READ_REQ = 12 -GL2C_PERF_SEL_CLIENT0_REQ = 13 -GL2C_PERF_SEL_CLIENT1_REQ = 14 -GL2C_PERF_SEL_CLIENT2_REQ = 15 -GL2C_PERF_SEL_CLIENT3_REQ = 16 -GL2C_PERF_SEL_CLIENT4_REQ = 17 -GL2C_PERF_SEL_CLIENT5_REQ = 18 -GL2C_PERF_SEL_CLIENT6_REQ = 19 -GL2C_PERF_SEL_CLIENT7_REQ = 20 -GL2C_PERF_SEL_CLIENT8_REQ = 21 -GL2C_PERF_SEL_CLIENT9_REQ = 22 -GL2C_PERF_SEL_CLIENT10_REQ = 23 -GL2C_PERF_SEL_CLIENT11_REQ = 24 -GL2C_PERF_SEL_CLIENT12_REQ = 25 -GL2C_PERF_SEL_CLIENT13_REQ = 26 -GL2C_PERF_SEL_CLIENT14_REQ = 27 -GL2C_PERF_SEL_CLIENT15_REQ = 28 -GL2C_PERF_SEL_C_RW_S_REQ = 29 -GL2C_PERF_SEL_C_RW_US_REQ = 30 -GL2C_PERF_SEL_C_RO_S_REQ = 31 -GL2C_PERF_SEL_C_RO_US_REQ = 32 -GL2C_PERF_SEL_UC_REQ = 33 -GL2C_PERF_SEL_LRU_REQ = 34 -GL2C_PERF_SEL_STREAM_REQ = 35 -GL2C_PERF_SEL_BYPASS_REQ = 36 -GL2C_PERF_SEL_NOA_REQ = 37 -GL2C_PERF_SEL_SHARED_REQ = 38 -GL2C_PERF_SEL_HIT = 39 -GL2C_PERF_SEL_MISS = 40 -GL2C_PERF_SEL_FULL_HIT = 41 -GL2C_PERF_SEL_PARTIAL_32B_HIT = 42 -GL2C_PERF_SEL_PARTIAL_64B_HIT = 43 -GL2C_PERF_SEL_PARTIAL_96B_HIT = 44 -GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 45 -GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 46 -GL2C_PERF_SEL_UNCACHED_WRITE = 47 -GL2C_PERF_SEL_WRITEBACK = 48 -GL2C_PERF_SEL_NORMAL_WRITEBACK = 49 -GL2C_PERF_SEL_EVICT = 50 -GL2C_PERF_SEL_NORMAL_EVICT = 51 -GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 52 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 53 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 54 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 55 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 56 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 57 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 58 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 59 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 60 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 61 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 62 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 63 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 64 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 65 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 66 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 67 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 68 -GL2C_PERF_SEL_READ_32_REQ = 69 -GL2C_PERF_SEL_READ_64_REQ = 70 -GL2C_PERF_SEL_READ_128_REQ = 71 -GL2C_PERF_SEL_WRITE_32_REQ = 72 -GL2C_PERF_SEL_WRITE_64_REQ = 73 -GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 74 -GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 75 -GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 76 -GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 77 -GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 78 -GL2C_PERF_SEL_MC_WRREQ = 79 -GL2C_PERF_SEL_EA_WRREQ_SNOOP = 80 -GL2C_PERF_SEL_EA_WRREQ_64B = 81 -GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 82 -GL2C_PERF_SEL_MC_WRREQ_STALL = 83 -GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 84 -GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 85 -GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 86 -GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 87 -GL2C_PERF_SEL_MC_WRREQ_LEVEL = 88 -GL2C_PERF_SEL_EA_ATOMIC = 89 -GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 90 -GL2C_PERF_SEL_MC_RDREQ = 91 -GL2C_PERF_SEL_EA_RDREQ_SNOOP = 92 -GL2C_PERF_SEL_EA_RDREQ_SPLIT = 93 -GL2C_PERF_SEL_EA_RDREQ_32B = 94 -GL2C_PERF_SEL_EA_RDREQ_64B = 95 -GL2C_PERF_SEL_EA_RDREQ_96B = 96 -GL2C_PERF_SEL_EA_RDREQ_128B = 97 -GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 98 -GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 99 -GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 100 -GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 101 -GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 102 -GL2C_PERF_SEL_MC_RDREQ_LEVEL = 103 -GL2C_PERF_SEL_EA_RDREQ_DRAM = 104 -GL2C_PERF_SEL_EA_WRREQ_DRAM = 105 -GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 106 -GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 107 -GL2C_PERF_SEL_ONION_READ = 108 -GL2C_PERF_SEL_ONION_WRITE = 109 -GL2C_PERF_SEL_IO_READ = 110 -GL2C_PERF_SEL_IO_WRITE = 111 -GL2C_PERF_SEL_GARLIC_READ = 112 -GL2C_PERF_SEL_GARLIC_WRITE = 113 -GL2C_PERF_SEL_EA_OUTSTANDING = 114 -GL2C_PERF_SEL_LATENCY_FIFO_FULL = 115 -GL2C_PERF_SEL_SRC_FIFO_FULL = 116 -GL2C_PERF_SEL_TAG_STALL = 117 -GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 118 -GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 119 -GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 120 -GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 121 -GL2C_PERF_SEL_TAG_READ_DST_STALL = 122 -GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 123 -GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 124 -GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 125 -GL2C_PERF_SEL_BUBBLE = 126 -GL2C_PERF_SEL_IB_REQ = 127 -GL2C_PERF_SEL_IB_STALL = 128 -GL2C_PERF_SEL_IB_TAG_STALL = 129 -GL2C_PERF_SEL_RETURN_ACK = 130 -GL2C_PERF_SEL_RETURN_DATA = 131 -GL2C_PERF_SEL_EA_RDRET_NACK = 132 -GL2C_PERF_SEL_EA_WRRET_NACK = 133 -GL2C_PERF_SEL_GL2A_LEVEL = 134 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 135 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 136 -GL2C_PERF_SEL_GCR_INV = 137 -GL2C_PERF_SEL_GCR_WB = 138 -GL2C_PERF_SEL_GCR_DISCARD = 139 -GL2C_PERF_SEL_GCR_RANGE = 140 -GL2C_PERF_SEL_GCR_ALL = 141 -GL2C_PERF_SEL_GCR_VOL = 142 -GL2C_PERF_SEL_GCR_UNSHARED = 143 -GL2C_PERF_SEL_GCR_GL2_INV_ALL = 144 -GL2C_PERF_SEL_GCR_GL2_WB_ALL = 145 -GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 146 -GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 147 -GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 148 -GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 149 -GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 150 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 151 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 152 -GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 153 -GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 154 -GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 155 -GL2C_PERF_SEL_GCR_INVL2_VOL_START = 156 -GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 157 -GL2C_PERF_SEL_GCR_WBL2_VOL_START = 158 -GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 159 -GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 160 -GL2C_PERF_SEL_GCR_WBINVL2_START = 161 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 162 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 163 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 164 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 165 -GL2C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SX_BLEND_OPT' -SX_BLEND_OPT__enumvalues = { - 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', -} -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 -SX_BLEND_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_DOWNCONVERT_FORMAT' -SX_DOWNCONVERT_FORMAT__enumvalues = { - 0: 'SX_RT_EXPORT_NO_CONVERSION', - 1: 'SX_RT_EXPORT_32_R', - 2: 'SX_RT_EXPORT_32_A', - 3: 'SX_RT_EXPORT_10_11_11', - 4: 'SX_RT_EXPORT_2_10_10_10', - 5: 'SX_RT_EXPORT_8_8_8_8', - 6: 'SX_RT_EXPORT_5_6_5', - 7: 'SX_RT_EXPORT_1_5_5_5', - 8: 'SX_RT_EXPORT_4_4_4_4', - 9: 'SX_RT_EXPORT_16_16_GR', - 10: 'SX_RT_EXPORT_16_16_AR', - 11: 'SX_RT_EXPORT_9_9_9_E5', - 12: 'SX_RT_EXPORT_2_10_10_10_7E3', - 13: 'SX_RT_EXPORT_2_10_10_10_6E4', -} -SX_RT_EXPORT_NO_CONVERSION = 0 -SX_RT_EXPORT_32_R = 1 -SX_RT_EXPORT_32_A = 2 -SX_RT_EXPORT_10_11_11 = 3 -SX_RT_EXPORT_2_10_10_10 = 4 -SX_RT_EXPORT_8_8_8_8 = 5 -SX_RT_EXPORT_5_6_5 = 6 -SX_RT_EXPORT_1_5_5_5 = 7 -SX_RT_EXPORT_4_4_4_4 = 8 -SX_RT_EXPORT_16_16_GR = 9 -SX_RT_EXPORT_16_16_AR = 10 -SX_RT_EXPORT_9_9_9_E5 = 11 -SX_RT_EXPORT_2_10_10_10_7E3 = 12 -SX_RT_EXPORT_2_10_10_10_6E4 = 13 -SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_OPT_COMB_FCN' -SX_OPT_COMB_FCN__enumvalues = { - 0: 'OPT_COMB_NONE', - 1: 'OPT_COMB_ADD', - 2: 'OPT_COMB_SUBTRACT', - 3: 'OPT_COMB_MIN', - 4: 'OPT_COMB_MAX', - 5: 'OPT_COMB_REVSUBTRACT', - 6: 'OPT_COMB_BLEND_DISABLED', - 7: 'OPT_COMB_SAFE_ADD', -} -OPT_COMB_NONE = 0 -OPT_COMB_ADD = 1 -OPT_COMB_SUBTRACT = 2 -OPT_COMB_MIN = 3 -OPT_COMB_MAX = 4 -OPT_COMB_REVSUBTRACT = 5 -OPT_COMB_BLEND_DISABLED = 6 -OPT_COMB_SAFE_ADD = 7 -SX_OPT_COMB_FCN = ctypes.c_uint32 # enum - -# values for enumeration 'SX_PERFCOUNTER_VALS' -SX_PERFCOUNTER_VALS__enumvalues = { - 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', - 1: 'SX_PERF_SEL_PA_REQ', - 2: 'SX_PERF_SEL_PA_POS', - 3: 'SX_PERF_SEL_CLOCK', - 4: 'SX_PERF_SEL_GATE_EN1', - 5: 'SX_PERF_SEL_GATE_EN2', - 6: 'SX_PERF_SEL_GATE_EN3', - 7: 'SX_PERF_SEL_GATE_EN4', - 8: 'SX_PERF_SEL_SH_POS_STARVE', - 9: 'SX_PERF_SEL_SH_COLOR_STARVE', - 10: 'SX_PERF_SEL_SH_POS_STALL', - 11: 'SX_PERF_SEL_SH_COLOR_STALL', - 12: 'SX_PERF_SEL_DB0_PIXELS', - 13: 'SX_PERF_SEL_DB0_HALF_QUADS', - 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', - 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', - 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', - 17: 'SX_PERF_SEL_DB1_PIXELS', - 18: 'SX_PERF_SEL_DB1_HALF_QUADS', - 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', - 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', - 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', - 22: 'SX_PERF_SEL_DB2_PIXELS', - 23: 'SX_PERF_SEL_DB2_HALF_QUADS', - 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', - 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', - 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', - 27: 'SX_PERF_SEL_DB3_PIXELS', - 28: 'SX_PERF_SEL_DB3_HALF_QUADS', - 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', - 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', - 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', - 32: 'SX_PERF_SEL_COL_BUSY', - 33: 'SX_PERF_SEL_POS_BUSY', - 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', - 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', - 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', - 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', - 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 54: 'SX_PERF_SEL_PA_REQ_LATENCY', - 55: 'SX_PERF_SEL_POS_SCBD_STALL', - 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', - 57: 'SX_PERF_SEL_GATE_EN5', - 58: 'SX_PERF_SEL_GATE_EN6', - 59: 'SX_PERF_SEL_DB0_SIZE', - 60: 'SX_PERF_SEL_DB1_SIZE', - 61: 'SX_PERF_SEL_DB2_SIZE', - 62: 'SX_PERF_SEL_DB3_SIZE', - 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', - 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 65: 'SX_PERF_SEL_IDX_REQ', - 66: 'SX_PERF_SEL_IDX_RET', - 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', - 68: 'SX_PERF_SEL_IDX_SCBD_STALL', - 69: 'SX_PERF_SEL_GATE_EN7', - 70: 'SX_PERF_SEL_GATE_EN8', - 71: 'SX_PERF_SEL_SH_IDX_STARVE', - 72: 'SX_PERF_SEL_IDX_BUSY', - 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', - 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', - 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', - 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', - 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', - 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', - 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', - 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', - 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', -} -SX_PERF_SEL_PA_IDLE_CYCLES = 0 -SX_PERF_SEL_PA_REQ = 1 -SX_PERF_SEL_PA_POS = 2 -SX_PERF_SEL_CLOCK = 3 -SX_PERF_SEL_GATE_EN1 = 4 -SX_PERF_SEL_GATE_EN2 = 5 -SX_PERF_SEL_GATE_EN3 = 6 -SX_PERF_SEL_GATE_EN4 = 7 -SX_PERF_SEL_SH_POS_STARVE = 8 -SX_PERF_SEL_SH_COLOR_STARVE = 9 -SX_PERF_SEL_SH_POS_STALL = 10 -SX_PERF_SEL_SH_COLOR_STALL = 11 -SX_PERF_SEL_DB0_PIXELS = 12 -SX_PERF_SEL_DB0_HALF_QUADS = 13 -SX_PERF_SEL_DB0_PIXEL_STALL = 14 -SX_PERF_SEL_DB0_PIXEL_IDLE = 15 -SX_PERF_SEL_DB0_PRED_PIXELS = 16 -SX_PERF_SEL_DB1_PIXELS = 17 -SX_PERF_SEL_DB1_HALF_QUADS = 18 -SX_PERF_SEL_DB1_PIXEL_STALL = 19 -SX_PERF_SEL_DB1_PIXEL_IDLE = 20 -SX_PERF_SEL_DB1_PRED_PIXELS = 21 -SX_PERF_SEL_DB2_PIXELS = 22 -SX_PERF_SEL_DB2_HALF_QUADS = 23 -SX_PERF_SEL_DB2_PIXEL_STALL = 24 -SX_PERF_SEL_DB2_PIXEL_IDLE = 25 -SX_PERF_SEL_DB2_PRED_PIXELS = 26 -SX_PERF_SEL_DB3_PIXELS = 27 -SX_PERF_SEL_DB3_HALF_QUADS = 28 -SX_PERF_SEL_DB3_PIXEL_STALL = 29 -SX_PERF_SEL_DB3_PIXEL_IDLE = 30 -SX_PERF_SEL_DB3_PRED_PIXELS = 31 -SX_PERF_SEL_COL_BUSY = 32 -SX_PERF_SEL_POS_BUSY = 33 -SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 -SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 -SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 -SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 -SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 -SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 -SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 -SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 -SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 -SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 -SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 -SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 -SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 -SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 -SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 -SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 -SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 -SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 -SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 -SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 -SX_PERF_SEL_PA_REQ_LATENCY = 54 -SX_PERF_SEL_POS_SCBD_STALL = 55 -SX_PERF_SEL_CLOCK_DROP_STALL = 56 -SX_PERF_SEL_GATE_EN5 = 57 -SX_PERF_SEL_GATE_EN6 = 58 -SX_PERF_SEL_DB0_SIZE = 59 -SX_PERF_SEL_DB1_SIZE = 60 -SX_PERF_SEL_DB2_SIZE = 61 -SX_PERF_SEL_DB3_SIZE = 62 -SX_PERF_SEL_IDX_STALL_CYCLES = 63 -SX_PERF_SEL_IDX_IDLE_CYCLES = 64 -SX_PERF_SEL_IDX_REQ = 65 -SX_PERF_SEL_IDX_RET = 66 -SX_PERF_SEL_IDX_REQ_LATENCY = 67 -SX_PERF_SEL_IDX_SCBD_STALL = 68 -SX_PERF_SEL_GATE_EN7 = 69 -SX_PERF_SEL_GATE_EN8 = 70 -SX_PERF_SEL_SH_IDX_STARVE = 71 -SX_PERF_SEL_IDX_BUSY = 72 -SX_PERF_SEL_PA_POS_BANK_CONF = 73 -SX_PERF_SEL_DB0_END_OF_WAVE = 74 -SX_PERF_SEL_DB0_4X2_DISCARD = 75 -SX_PERF_SEL_DB1_END_OF_WAVE = 76 -SX_PERF_SEL_DB1_4X2_DISCARD = 77 -SX_PERF_SEL_DB2_END_OF_WAVE = 78 -SX_PERF_SEL_DB2_4X2_DISCARD = 79 -SX_PERF_SEL_DB3_END_OF_WAVE = 80 -SX_PERF_SEL_DB3_4X2_DISCARD = 81 -SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum - -# values for enumeration 'CompareFrag' -CompareFrag__enumvalues = { - 0: 'FRAG_NEVER', - 1: 'FRAG_LESS', - 2: 'FRAG_EQUAL', - 3: 'FRAG_LEQUAL', - 4: 'FRAG_GREATER', - 5: 'FRAG_NOTEQUAL', - 6: 'FRAG_GEQUAL', - 7: 'FRAG_ALWAYS', -} -FRAG_NEVER = 0 -FRAG_LESS = 1 -FRAG_EQUAL = 2 -FRAG_LEQUAL = 3 -FRAG_GREATER = 4 -FRAG_NOTEQUAL = 5 -FRAG_GEQUAL = 6 -FRAG_ALWAYS = 7 -CompareFrag = ctypes.c_uint32 # enum - -# values for enumeration 'ConservativeZExport' -ConservativeZExport__enumvalues = { - 0: 'EXPORT_ANY_Z', - 1: 'EXPORT_LESS_THAN_Z', - 2: 'EXPORT_GREATER_THAN_Z', - 3: 'EXPORT_RESERVED', -} -EXPORT_ANY_Z = 0 -EXPORT_LESS_THAN_Z = 1 -EXPORT_GREATER_THAN_Z = 2 -EXPORT_RESERVED = 3 -ConservativeZExport = ctypes.c_uint32 # enum - -# values for enumeration 'DbMemArbWatermarks' -DbMemArbWatermarks__enumvalues = { - 0: 'TRANSFERRED_64_BYTES', - 1: 'TRANSFERRED_128_BYTES', - 2: 'TRANSFERRED_256_BYTES', - 3: 'TRANSFERRED_512_BYTES', - 4: 'TRANSFERRED_1024_BYTES', - 5: 'TRANSFERRED_2048_BYTES', - 6: 'TRANSFERRED_4096_BYTES', - 7: 'TRANSFERRED_8192_BYTES', -} -TRANSFERRED_64_BYTES = 0 -TRANSFERRED_128_BYTES = 1 -TRANSFERRED_256_BYTES = 2 -TRANSFERRED_512_BYTES = 3 -TRANSFERRED_1024_BYTES = 4 -TRANSFERRED_2048_BYTES = 5 -TRANSFERRED_4096_BYTES = 6 -TRANSFERRED_8192_BYTES = 7 -DbMemArbWatermarks = ctypes.c_uint32 # enum - -# values for enumeration 'DbPRTFaultBehavior' -DbPRTFaultBehavior__enumvalues = { - 0: 'FAULT_ZERO', - 1: 'FAULT_ONE', - 2: 'FAULT_FAIL', - 3: 'FAULT_PASS', -} -FAULT_ZERO = 0 -FAULT_ONE = 1 -FAULT_FAIL = 2 -FAULT_PASS = 3 -DbPRTFaultBehavior = ctypes.c_uint32 # enum - -# values for enumeration 'DbPSLControl' -DbPSLControl__enumvalues = { - 0: 'PSLC_AUTO', - 1: 'PSLC_ON_HANG_ONLY', - 2: 'PSLC_ASAP', - 3: 'PSLC_COUNTDOWN', -} -PSLC_AUTO = 0 -PSLC_ON_HANG_ONLY = 1 -PSLC_ASAP = 2 -PSLC_COUNTDOWN = 3 -DbPSLControl = ctypes.c_uint32 # enum - -# values for enumeration 'ForceControl' -ForceControl__enumvalues = { - 0: 'FORCE_OFF', - 1: 'FORCE_ENABLE', - 2: 'FORCE_DISABLE', - 3: 'FORCE_RESERVED', -} -FORCE_OFF = 0 -FORCE_ENABLE = 1 -FORCE_DISABLE = 2 -FORCE_RESERVED = 3 -ForceControl = ctypes.c_uint32 # enum - -# values for enumeration 'GLCompressionMode' -GLCompressionMode__enumvalues = { - 0: 'DB_DEFAULT', - 1: 'DB_BYPASS', - 2: 'DB_COMP_WR_DISABLE', - 3: 'DB_BYPASS_WR_DISABLE', -} -DB_DEFAULT = 0 -DB_BYPASS = 1 -DB_COMP_WR_DISABLE = 2 -DB_BYPASS_WR_DISABLE = 3 -GLCompressionMode = ctypes.c_uint32 # enum - -# values for enumeration 'OreoMode' -OreoMode__enumvalues = { - 0: 'OMODE_BLEND', - 1: 'OMODE_O_THEN_B', - 2: 'OMODE_P_THEN_O_THEN_B', - 3: 'OMODE_RESERVED_3', -} -OMODE_BLEND = 0 -OMODE_O_THEN_B = 1 -OMODE_P_THEN_O_THEN_B = 2 -OMODE_RESERVED_3 = 3 -OreoMode = ctypes.c_uint32 # enum - -# values for enumeration 'PerfCounter_Vals' -PerfCounter_Vals__enumvalues = { - 0: 'DB_PERF_SEL_SC_DB_tile_sends', - 1: 'DB_PERF_SEL_SC_DB_tile_busy', - 2: 'DB_PERF_SEL_SC_DB_tile_stalls', - 3: 'DB_PERF_SEL_SC_DB_tile_events', - 4: 'DB_PERF_SEL_SC_DB_tile_tiles', - 5: 'DB_PERF_SEL_SC_DB_tile_covered', - 6: 'DB_PERF_SEL_hiz_tc_read_starved', - 7: 'DB_PERF_SEL_hiz_tc_write_stall', - 8: 'DB_PERF_SEL_hiz_tile_culled', - 9: 'DB_PERF_SEL_his_tile_culled', - 10: 'DB_PERF_SEL_DB_SC_tile_sends', - 11: 'DB_PERF_SEL_DB_SC_tile_busy', - 12: 'DB_PERF_SEL_DB_SC_tile_stalls', - 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 14: 'DB_PERF_SEL_DB_SC_tile_tiles', - 15: 'DB_PERF_SEL_DB_SC_tile_culled', - 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', - 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 23: 'DB_PERF_SEL_SC_DB_quad_sends', - 24: 'DB_PERF_SEL_SC_DB_quad_busy', - 25: 'DB_PERF_SEL_SC_DB_quad_squads', - 26: 'DB_PERF_SEL_SC_DB_quad_tiles', - 27: 'DB_PERF_SEL_SC_DB_quad_pixels', - 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 29: 'DB_PERF_SEL_DB_SC_quad_sends', - 30: 'DB_PERF_SEL_DB_SC_quad_busy', - 31: 'DB_PERF_SEL_DB_SC_quad_stalls', - 32: 'DB_PERF_SEL_DB_SC_quad_tiles', - 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 34: 'DB_PERF_SEL_DB_CB_export_events', - 37: 'DB_PERF_SEL_SX_DB_quad_sends', - 38: 'DB_PERF_SEL_SX_DB_quad_busy', - 39: 'DB_PERF_SEL_SX_DB_quad_stalls', - 40: 'DB_PERF_SEL_SX_DB_quad_quads', - 41: 'DB_PERF_SEL_SX_DB_quad_pixels', - 42: 'DB_PERF_SEL_SX_DB_quad_exports', - 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', - 44: 'DB_PERF_SEL_DB_CB_export_sends', - 45: 'DB_PERF_SEL_DB_CB_export_busy', - 46: 'DB_PERF_SEL_DB_CB_export_stalls', - 47: 'DB_PERF_SEL_DB_CB_export_quads', - 48: 'DB_PERF_SEL_tile_rd_sends', - 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 50: 'DB_PERF_SEL_quad_rd_sends', - 51: 'DB_PERF_SEL_quad_rd_busy', - 52: 'DB_PERF_SEL_quad_rd_mi_stall', - 53: 'DB_PERF_SEL_quad_rd_rw_collision', - 54: 'DB_PERF_SEL_quad_rd_tag_stall', - 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', - 56: 'DB_PERF_SEL_quad_rd_panic', - 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 58: 'DB_PERF_SEL_quad_rdret_sends', - 59: 'DB_PERF_SEL_quad_rdret_busy', - 60: 'DB_PERF_SEL_tile_wr_sends', - 61: 'DB_PERF_SEL_tile_wr_acks', - 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 63: 'DB_PERF_SEL_quad_wr_sends', - 64: 'DB_PERF_SEL_quad_wr_busy', - 65: 'DB_PERF_SEL_quad_wr_mi_stall', - 66: 'DB_PERF_SEL_quad_wr_coherency_stall', - 67: 'DB_PERF_SEL_quad_wr_acks', - 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 69: 'DB_PERF_SEL_Tile_Cache_misses', - 70: 'DB_PERF_SEL_Tile_Cache_hits', - 71: 'DB_PERF_SEL_Tile_Cache_flushes', - 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', - 73: 'DB_PERF_SEL_Tile_Cache_starves', - 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 75: 'DB_PERF_SEL_tcp_dispatcher_reads', - 76: 'DB_PERF_SEL_tcp_prefetcher_reads', - 77: 'DB_PERF_SEL_tcp_preloader_reads', - 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', - 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', - 80: 'DB_PERF_SEL_tcp_preloader_flushes', - 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', - 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 95: 'DB_PERF_SEL_Stencil_Cache_misses', - 96: 'DB_PERF_SEL_Stencil_Cache_hits', - 97: 'DB_PERF_SEL_Stencil_Cache_flushes', - 98: 'DB_PERF_SEL_Stencil_Cache_starves', - 99: 'DB_PERF_SEL_Stencil_Cache_frees', - 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', - 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', - 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', - 108: 'DB_PERF_SEL_Z_Cache_frees', - 109: 'DB_PERF_SEL_Plane_Cache_misses', - 110: 'DB_PERF_SEL_Plane_Cache_hits', - 111: 'DB_PERF_SEL_Plane_Cache_flushes', - 112: 'DB_PERF_SEL_Plane_Cache_starves', - 113: 'DB_PERF_SEL_Plane_Cache_frees', - 114: 'DB_PERF_SEL_flush_expanded_stencil', - 115: 'DB_PERF_SEL_flush_compressed_stencil', - 116: 'DB_PERF_SEL_flush_single_stencil', - 117: 'DB_PERF_SEL_planes_flushed', - 118: 'DB_PERF_SEL_flush_1plane', - 119: 'DB_PERF_SEL_flush_2plane', - 120: 'DB_PERF_SEL_flush_3plane', - 121: 'DB_PERF_SEL_flush_4plane', - 122: 'DB_PERF_SEL_flush_5plane', - 123: 'DB_PERF_SEL_flush_6plane', - 124: 'DB_PERF_SEL_flush_7plane', - 125: 'DB_PERF_SEL_flush_8plane', - 126: 'DB_PERF_SEL_flush_9plane', - 127: 'DB_PERF_SEL_flush_10plane', - 128: 'DB_PERF_SEL_flush_11plane', - 129: 'DB_PERF_SEL_flush_12plane', - 130: 'DB_PERF_SEL_flush_13plane', - 131: 'DB_PERF_SEL_flush_14plane', - 132: 'DB_PERF_SEL_flush_15plane', - 133: 'DB_PERF_SEL_flush_16plane', - 134: 'DB_PERF_SEL_flush_expanded_z', - 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 137: 'DB_PERF_SEL_dk_tile_sends', - 138: 'DB_PERF_SEL_dk_tile_busy', - 139: 'DB_PERF_SEL_dk_tile_quad_starves', - 140: 'DB_PERF_SEL_dk_tile_stalls', - 141: 'DB_PERF_SEL_dk_squad_sends', - 142: 'DB_PERF_SEL_dk_squad_busy', - 143: 'DB_PERF_SEL_dk_squad_stalls', - 144: 'DB_PERF_SEL_Op_Pipe_Busy', - 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 146: 'DB_PERF_SEL_qc_busy', - 147: 'DB_PERF_SEL_qc_xfc', - 148: 'DB_PERF_SEL_qc_conflicts', - 149: 'DB_PERF_SEL_qc_full_stall', - 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', - 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', - 153: 'DB_PERF_SEL_tl_busy', - 154: 'DB_PERF_SEL_tl_dtc_read_starved', - 155: 'DB_PERF_SEL_tl_z_fetch_stall', - 156: 'DB_PERF_SEL_tl_stencil_stall', - 157: 'DB_PERF_SEL_tl_z_decompress_stall', - 158: 'DB_PERF_SEL_tl_stencil_locked_stall', - 159: 'DB_PERF_SEL_tl_events', - 160: 'DB_PERF_SEL_tl_summarize_squads', - 161: 'DB_PERF_SEL_tl_flush_expand_squads', - 162: 'DB_PERF_SEL_tl_expand_squads', - 163: 'DB_PERF_SEL_tl_preZ_squads', - 164: 'DB_PERF_SEL_tl_postZ_squads', - 165: 'DB_PERF_SEL_tl_preZ_noop_squads', - 166: 'DB_PERF_SEL_tl_postZ_noop_squads', - 167: 'DB_PERF_SEL_tl_tile_ops', - 168: 'DB_PERF_SEL_tl_in_xfc', - 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 170: 'DB_PERF_SEL_tl_in_fast_z_stall', - 171: 'DB_PERF_SEL_tl_out_xfc', - 172: 'DB_PERF_SEL_tl_out_squads', - 173: 'DB_PERF_SEL_zf_plane_multicycle', - 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', - 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', - 180: 'DB_PERF_SEL_ts_tc_update_stall', - 181: 'DB_PERF_SEL_sc_kick_start', - 182: 'DB_PERF_SEL_sc_kick_end', - 183: 'DB_PERF_SEL_clock_reg_active', - 184: 'DB_PERF_SEL_clock_main_active', - 185: 'DB_PERF_SEL_clock_mem_export_active', - 186: 'DB_PERF_SEL_esr_ps_out_busy', - 187: 'DB_PERF_SEL_esr_ps_lqf_busy', - 188: 'DB_PERF_SEL_esr_ps_lqf_stall', - 189: 'DB_PERF_SEL_etr_out_send', - 190: 'DB_PERF_SEL_etr_out_busy', - 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 193: 'DB_PERF_SEL_etr_out_esr_stall', - 194: 'DB_PERF_SEL_esr_ps_vic_busy', - 195: 'DB_PERF_SEL_esr_ps_vic_stall', - 196: 'DB_PERF_SEL_esr_eot_fwd_busy', - 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 198: 'DB_PERF_SEL_esr_eot_fwd_forward', - 199: 'DB_PERF_SEL_esr_sqq_zi_busy', - 200: 'DB_PERF_SEL_esr_sqq_zi_stall', - 201: 'DB_PERF_SEL_postzl_sq_pt_busy', - 202: 'DB_PERF_SEL_postzl_sq_pt_stall', - 203: 'DB_PERF_SEL_postzl_se_busy', - 204: 'DB_PERF_SEL_postzl_se_stall', - 205: 'DB_PERF_SEL_postzl_partial_launch', - 206: 'DB_PERF_SEL_postzl_full_launch', - 207: 'DB_PERF_SEL_postzl_partial_waiting', - 208: 'DB_PERF_SEL_postzl_tile_mem_stall', - 209: 'DB_PERF_SEL_postzl_tile_init_stall', - 210: 'DB_PERF_SEL_prezl_tile_mem_stall', - 211: 'DB_PERF_SEL_prezl_tile_init_stall', - 212: 'DB_PERF_SEL_dtt_sm_clash_stall', - 213: 'DB_PERF_SEL_dtt_sm_slot_stall', - 214: 'DB_PERF_SEL_dtt_sm_miss_stall', - 215: 'DB_PERF_SEL_mi_rdreq_busy', - 216: 'DB_PERF_SEL_mi_rdreq_stall', - 217: 'DB_PERF_SEL_mi_wrreq_busy', - 218: 'DB_PERF_SEL_mi_wrreq_stall', - 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 220: 'DB_PERF_SEL_dkg_tile_rate_tile', - 221: 'DB_PERF_SEL_prezl_src_in_sends', - 222: 'DB_PERF_SEL_prezl_src_in_stall', - 223: 'DB_PERF_SEL_prezl_src_in_squads', - 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', - 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 227: 'DB_PERF_SEL_prezl_src_out_stall', - 228: 'DB_PERF_SEL_postzl_src_in_sends', - 229: 'DB_PERF_SEL_postzl_src_in_stall', - 230: 'DB_PERF_SEL_postzl_src_in_squads', - 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', - 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 234: 'DB_PERF_SEL_postzl_src_out_stall', - 235: 'DB_PERF_SEL_esr_ps_src_in_sends', - 236: 'DB_PERF_SEL_esr_ps_src_in_stall', - 237: 'DB_PERF_SEL_esr_ps_src_in_squads', - 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 242: 'DB_PERF_SEL_esr_ps_src_out_stall', - 243: 'DB_PERF_SEL_depth_bounds_tile_culled', - 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 246: 'DB_PERF_SEL_flush_compressed', - 247: 'DB_PERF_SEL_flush_plane_le4', - 248: 'DB_PERF_SEL_tiles_z_fully_summarized', - 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', - 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', - 256: 'DB_PERF_SEL_di_dt_stall', - 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', - 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', - 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', - 261: 'DB_PERF_SEL_DB_CB_export_export_quads', - 262: 'DB_PERF_SEL_DB_CB_export_double_format', - 263: 'DB_PERF_SEL_DB_CB_export_fast_format', - 264: 'DB_PERF_SEL_DB_CB_export_slow_format', - 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', - 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', - 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 269: 'DB_PERF_SEL_DB_CB_rdret_ack', - 270: 'DB_PERF_SEL_DB_CB_rdret_nack', - 271: 'DB_PERF_SEL_DB_CB_wrret_ack', - 272: 'DB_PERF_SEL_DB_CB_wrret_nack', - 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 277: 'DB_PERF_SEL_unmapped_z_tile_culled', - 278: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS', - 279: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 280: 'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS', - 281: 'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event', - 282: 'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix', - 283: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix', - 284: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix', - 285: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix', - 286: 'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending', - 287: 'DB_PERF_SEL_DB_CB_context_dones', - 288: 'DB_PERF_SEL_DB_CB_eop_dones', - 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 292: 'DB_PERF_SEL_SC_DB_tile_backface', - 293: 'DB_PERF_SEL_SC_DB_quad_quads', - 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', - 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', - 300: 'DB_PERF_SEL_SX_DB_quad_double_format', - 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', - 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', - 303: 'DB_PERF_SEL_quad_rd_sends_unc', - 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', - 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', - 311: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1', - 312: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1', - 313: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2', - 314: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2', - 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', - 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 329: 'DB_PERF_SEL_esr_vic_sqq_busy', - 330: 'DB_PERF_SEL_esr_vic_sqq_stall', - 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 344: 'DB_PERF_SEL_ts_events_pws_enable', - 345: 'DB_PERF_SEL_ps_events_pws_enable', - 346: 'DB_PERF_SEL_cs_events_pws_enable', - 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', - 349: 'DB_PERF_SEL_DB_SC_quad_conflicts', - 350: 'DB_PERF_SEL_SC_DB_quad_vrs_1x1', - 351: 'DB_PERF_SEL_SC_DB_quad_vrs_1x2', - 352: 'DB_PERF_SEL_SC_DB_quad_vrs_2x1', - 353: 'DB_PERF_SEL_SC_DB_quad_vrs_2x2', - 354: 'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa', - 355: 'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa', - 356: 'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa', - 357: 'DB_PERF_SEL_SC_DB_wave_sends', - 358: 'DB_PERF_SEL_SC_DB_wave_busy', - 359: 'DB_PERF_SEL_SC_DB_wave_quads', - 360: 'DB_PERF_SEL_SC_DB_wave_id_wrapped', - 361: 'DB_PERF_SEL_DB_SC_wave_sends', - 362: 'DB_PERF_SEL_DB_SC_wave_busy', - 363: 'DB_PERF_SEL_DB_SC_wave_stalls', - 364: 'DB_PERF_SEL_DB_SC_wave_conflict', - 365: 'DB_PERF_SEL_DB_SC_wave_hard_conflict', - 366: 'DB_PERF_SEL_DB_SC_wave_id_wrapped', - 367: 'DB_PERF_SEL_SX_DB_quad_waves', - 368: 'DB_PERF_SEL_pws_stall', - 369: 'DB_PERF_SEL_pws_liveness_stall_dtt_tag', - 370: 'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr', - 371: 'DB_PERF_SEL_OREO_TT_load', - 372: 'DB_PERF_SEL_OREO_TT_read', - 373: 'DB_PERF_SEL_OREO_TT_stalls', - 374: 'DB_PERF_SEL_OREO_ST_load', - 375: 'DB_PERF_SEL_OREO_ST_read', - 376: 'DB_PERF_SEL_OREO_ST_stalls', - 377: 'DB_PERF_SEL_OREO_WT_load', - 378: 'DB_PERF_SEL_OREO_WT_read', - 379: 'DB_PERF_SEL_OREO_SB_misses', - 380: 'DB_PERF_SEL_OREO_SB_hits', - 381: 'DB_PERF_SEL_OREO_SB_evicts', - 382: 'DB_PERF_SEL_OREO_SB_stalls', - 383: 'DB_PERF_SEL_OREO_Events_load', - 384: 'DB_PERF_SEL_OREO_Events_transition', - 385: 'DB_PERF_SEL_OREO_Events_non_transition', - 386: 'DB_PERF_SEL_OREO_Events_delayed', - 387: 'DB_PERF_SEL_OREO_Events_stalls', -} -DB_PERF_SEL_SC_DB_tile_sends = 0 -DB_PERF_SEL_SC_DB_tile_busy = 1 -DB_PERF_SEL_SC_DB_tile_stalls = 2 -DB_PERF_SEL_SC_DB_tile_events = 3 -DB_PERF_SEL_SC_DB_tile_tiles = 4 -DB_PERF_SEL_SC_DB_tile_covered = 5 -DB_PERF_SEL_hiz_tc_read_starved = 6 -DB_PERF_SEL_hiz_tc_write_stall = 7 -DB_PERF_SEL_hiz_tile_culled = 8 -DB_PERF_SEL_his_tile_culled = 9 -DB_PERF_SEL_DB_SC_tile_sends = 10 -DB_PERF_SEL_DB_SC_tile_busy = 11 -DB_PERF_SEL_DB_SC_tile_stalls = 12 -DB_PERF_SEL_DB_SC_tile_df_stalls = 13 -DB_PERF_SEL_DB_SC_tile_tiles = 14 -DB_PERF_SEL_DB_SC_tile_culled = 15 -DB_PERF_SEL_DB_SC_tile_hier_kill = 16 -DB_PERF_SEL_DB_SC_tile_fast_ops = 17 -DB_PERF_SEL_DB_SC_tile_no_ops = 18 -DB_PERF_SEL_DB_SC_tile_tile_rate = 19 -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 -DB_PERF_SEL_SC_DB_quad_sends = 23 -DB_PERF_SEL_SC_DB_quad_busy = 24 -DB_PERF_SEL_SC_DB_quad_squads = 25 -DB_PERF_SEL_SC_DB_quad_tiles = 26 -DB_PERF_SEL_SC_DB_quad_pixels = 27 -DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 -DB_PERF_SEL_DB_SC_quad_sends = 29 -DB_PERF_SEL_DB_SC_quad_busy = 30 -DB_PERF_SEL_DB_SC_quad_stalls = 31 -DB_PERF_SEL_DB_SC_quad_tiles = 32 -DB_PERF_SEL_DB_SC_quad_lit_quad = 33 -DB_PERF_SEL_DB_CB_export_events = 34 -DB_PERF_SEL_SX_DB_quad_sends = 37 -DB_PERF_SEL_SX_DB_quad_busy = 38 -DB_PERF_SEL_SX_DB_quad_stalls = 39 -DB_PERF_SEL_SX_DB_quad_quads = 40 -DB_PERF_SEL_SX_DB_quad_pixels = 41 -DB_PERF_SEL_SX_DB_quad_exports = 42 -DB_PERF_SEL_SH_quads_outstanding_sum = 43 -DB_PERF_SEL_DB_CB_export_sends = 44 -DB_PERF_SEL_DB_CB_export_busy = 45 -DB_PERF_SEL_DB_CB_export_stalls = 46 -DB_PERF_SEL_DB_CB_export_quads = 47 -DB_PERF_SEL_tile_rd_sends = 48 -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 -DB_PERF_SEL_quad_rd_sends = 50 -DB_PERF_SEL_quad_rd_busy = 51 -DB_PERF_SEL_quad_rd_mi_stall = 52 -DB_PERF_SEL_quad_rd_rw_collision = 53 -DB_PERF_SEL_quad_rd_tag_stall = 54 -DB_PERF_SEL_quad_rd_32byte_reqs = 55 -DB_PERF_SEL_quad_rd_panic = 56 -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 -DB_PERF_SEL_quad_rdret_sends = 58 -DB_PERF_SEL_quad_rdret_busy = 59 -DB_PERF_SEL_tile_wr_sends = 60 -DB_PERF_SEL_tile_wr_acks = 61 -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 -DB_PERF_SEL_quad_wr_sends = 63 -DB_PERF_SEL_quad_wr_busy = 64 -DB_PERF_SEL_quad_wr_mi_stall = 65 -DB_PERF_SEL_quad_wr_coherency_stall = 66 -DB_PERF_SEL_quad_wr_acks = 67 -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 -DB_PERF_SEL_Tile_Cache_misses = 69 -DB_PERF_SEL_Tile_Cache_hits = 70 -DB_PERF_SEL_Tile_Cache_flushes = 71 -DB_PERF_SEL_Tile_Cache_surface_stall = 72 -DB_PERF_SEL_Tile_Cache_starves = 73 -DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 -DB_PERF_SEL_tcp_dispatcher_reads = 75 -DB_PERF_SEL_tcp_prefetcher_reads = 76 -DB_PERF_SEL_tcp_preloader_reads = 77 -DB_PERF_SEL_tcp_dispatcher_flushes = 78 -DB_PERF_SEL_tcp_prefetcher_flushes = 79 -DB_PERF_SEL_tcp_preloader_flushes = 80 -DB_PERF_SEL_Depth_Tile_Cache_sends = 81 -DB_PERF_SEL_Depth_Tile_Cache_busy = 82 -DB_PERF_SEL_Depth_Tile_Cache_starves = 83 -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 -DB_PERF_SEL_Depth_Tile_Cache_misses = 86 -DB_PERF_SEL_Depth_Tile_Cache_hits = 87 -DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 -DB_PERF_SEL_Depth_Tile_Cache_event = 91 -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 -DB_PERF_SEL_Stencil_Cache_misses = 95 -DB_PERF_SEL_Stencil_Cache_hits = 96 -DB_PERF_SEL_Stencil_Cache_flushes = 97 -DB_PERF_SEL_Stencil_Cache_starves = 98 -DB_PERF_SEL_Stencil_Cache_frees = 99 -DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 -DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 -DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 -DB_PERF_SEL_Z_Cache_pmask_misses = 104 -DB_PERF_SEL_Z_Cache_pmask_hits = 105 -DB_PERF_SEL_Z_Cache_pmask_flushes = 106 -DB_PERF_SEL_Z_Cache_pmask_starves = 107 -DB_PERF_SEL_Z_Cache_frees = 108 -DB_PERF_SEL_Plane_Cache_misses = 109 -DB_PERF_SEL_Plane_Cache_hits = 110 -DB_PERF_SEL_Plane_Cache_flushes = 111 -DB_PERF_SEL_Plane_Cache_starves = 112 -DB_PERF_SEL_Plane_Cache_frees = 113 -DB_PERF_SEL_flush_expanded_stencil = 114 -DB_PERF_SEL_flush_compressed_stencil = 115 -DB_PERF_SEL_flush_single_stencil = 116 -DB_PERF_SEL_planes_flushed = 117 -DB_PERF_SEL_flush_1plane = 118 -DB_PERF_SEL_flush_2plane = 119 -DB_PERF_SEL_flush_3plane = 120 -DB_PERF_SEL_flush_4plane = 121 -DB_PERF_SEL_flush_5plane = 122 -DB_PERF_SEL_flush_6plane = 123 -DB_PERF_SEL_flush_7plane = 124 -DB_PERF_SEL_flush_8plane = 125 -DB_PERF_SEL_flush_9plane = 126 -DB_PERF_SEL_flush_10plane = 127 -DB_PERF_SEL_flush_11plane = 128 -DB_PERF_SEL_flush_12plane = 129 -DB_PERF_SEL_flush_13plane = 130 -DB_PERF_SEL_flush_14plane = 131 -DB_PERF_SEL_flush_15plane = 132 -DB_PERF_SEL_flush_16plane = 133 -DB_PERF_SEL_flush_expanded_z = 134 -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 -DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 -DB_PERF_SEL_dk_tile_sends = 137 -DB_PERF_SEL_dk_tile_busy = 138 -DB_PERF_SEL_dk_tile_quad_starves = 139 -DB_PERF_SEL_dk_tile_stalls = 140 -DB_PERF_SEL_dk_squad_sends = 141 -DB_PERF_SEL_dk_squad_busy = 142 -DB_PERF_SEL_dk_squad_stalls = 143 -DB_PERF_SEL_Op_Pipe_Busy = 144 -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 -DB_PERF_SEL_qc_busy = 146 -DB_PERF_SEL_qc_xfc = 147 -DB_PERF_SEL_qc_conflicts = 148 -DB_PERF_SEL_qc_full_stall = 149 -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 -DB_PERF_SEL_tsc_insert_summarize_stall = 152 -DB_PERF_SEL_tl_busy = 153 -DB_PERF_SEL_tl_dtc_read_starved = 154 -DB_PERF_SEL_tl_z_fetch_stall = 155 -DB_PERF_SEL_tl_stencil_stall = 156 -DB_PERF_SEL_tl_z_decompress_stall = 157 -DB_PERF_SEL_tl_stencil_locked_stall = 158 -DB_PERF_SEL_tl_events = 159 -DB_PERF_SEL_tl_summarize_squads = 160 -DB_PERF_SEL_tl_flush_expand_squads = 161 -DB_PERF_SEL_tl_expand_squads = 162 -DB_PERF_SEL_tl_preZ_squads = 163 -DB_PERF_SEL_tl_postZ_squads = 164 -DB_PERF_SEL_tl_preZ_noop_squads = 165 -DB_PERF_SEL_tl_postZ_noop_squads = 166 -DB_PERF_SEL_tl_tile_ops = 167 -DB_PERF_SEL_tl_in_xfc = 168 -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 -DB_PERF_SEL_tl_in_fast_z_stall = 170 -DB_PERF_SEL_tl_out_xfc = 171 -DB_PERF_SEL_tl_out_squads = 172 -DB_PERF_SEL_zf_plane_multicycle = 173 -DB_PERF_SEL_PostZ_Samples_passing_Z = 174 -DB_PERF_SEL_PostZ_Samples_failing_Z = 175 -DB_PERF_SEL_PostZ_Samples_failing_S = 176 -DB_PERF_SEL_PreZ_Samples_passing_Z = 177 -DB_PERF_SEL_PreZ_Samples_failing_Z = 178 -DB_PERF_SEL_PreZ_Samples_failing_S = 179 -DB_PERF_SEL_ts_tc_update_stall = 180 -DB_PERF_SEL_sc_kick_start = 181 -DB_PERF_SEL_sc_kick_end = 182 -DB_PERF_SEL_clock_reg_active = 183 -DB_PERF_SEL_clock_main_active = 184 -DB_PERF_SEL_clock_mem_export_active = 185 -DB_PERF_SEL_esr_ps_out_busy = 186 -DB_PERF_SEL_esr_ps_lqf_busy = 187 -DB_PERF_SEL_esr_ps_lqf_stall = 188 -DB_PERF_SEL_etr_out_send = 189 -DB_PERF_SEL_etr_out_busy = 190 -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 -DB_PERF_SEL_etr_out_esr_stall = 193 -DB_PERF_SEL_esr_ps_vic_busy = 194 -DB_PERF_SEL_esr_ps_vic_stall = 195 -DB_PERF_SEL_esr_eot_fwd_busy = 196 -DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 -DB_PERF_SEL_esr_eot_fwd_forward = 198 -DB_PERF_SEL_esr_sqq_zi_busy = 199 -DB_PERF_SEL_esr_sqq_zi_stall = 200 -DB_PERF_SEL_postzl_sq_pt_busy = 201 -DB_PERF_SEL_postzl_sq_pt_stall = 202 -DB_PERF_SEL_postzl_se_busy = 203 -DB_PERF_SEL_postzl_se_stall = 204 -DB_PERF_SEL_postzl_partial_launch = 205 -DB_PERF_SEL_postzl_full_launch = 206 -DB_PERF_SEL_postzl_partial_waiting = 207 -DB_PERF_SEL_postzl_tile_mem_stall = 208 -DB_PERF_SEL_postzl_tile_init_stall = 209 -DB_PERF_SEL_prezl_tile_mem_stall = 210 -DB_PERF_SEL_prezl_tile_init_stall = 211 -DB_PERF_SEL_dtt_sm_clash_stall = 212 -DB_PERF_SEL_dtt_sm_slot_stall = 213 -DB_PERF_SEL_dtt_sm_miss_stall = 214 -DB_PERF_SEL_mi_rdreq_busy = 215 -DB_PERF_SEL_mi_rdreq_stall = 216 -DB_PERF_SEL_mi_wrreq_busy = 217 -DB_PERF_SEL_mi_wrreq_stall = 218 -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 -DB_PERF_SEL_dkg_tile_rate_tile = 220 -DB_PERF_SEL_prezl_src_in_sends = 221 -DB_PERF_SEL_prezl_src_in_stall = 222 -DB_PERF_SEL_prezl_src_in_squads = 223 -DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 -DB_PERF_SEL_prezl_src_in_tile_rate = 225 -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 -DB_PERF_SEL_prezl_src_out_stall = 227 -DB_PERF_SEL_postzl_src_in_sends = 228 -DB_PERF_SEL_postzl_src_in_stall = 229 -DB_PERF_SEL_postzl_src_in_squads = 230 -DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 -DB_PERF_SEL_postzl_src_in_tile_rate = 232 -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 -DB_PERF_SEL_postzl_src_out_stall = 234 -DB_PERF_SEL_esr_ps_src_in_sends = 235 -DB_PERF_SEL_esr_ps_src_in_stall = 236 -DB_PERF_SEL_esr_ps_src_in_squads = 237 -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 -DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 -DB_PERF_SEL_esr_ps_src_out_stall = 242 -DB_PERF_SEL_depth_bounds_tile_culled = 243 -DB_PERF_SEL_PreZ_Samples_failing_DB = 244 -DB_PERF_SEL_PostZ_Samples_failing_DB = 245 -DB_PERF_SEL_flush_compressed = 246 -DB_PERF_SEL_flush_plane_le4 = 247 -DB_PERF_SEL_tiles_z_fully_summarized = 248 -DB_PERF_SEL_tiles_stencil_fully_summarized = 249 -DB_PERF_SEL_tiles_z_clear_on_expclear = 250 -DB_PERF_SEL_tiles_s_clear_on_expclear = 251 -DB_PERF_SEL_tiles_decomp_on_expclear = 252 -DB_PERF_SEL_tiles_compressed_to_decompressed = 253 -DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 -DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 -DB_PERF_SEL_di_dt_stall = 256 -DB_PERF_SEL_DB_SC_s_tile_rate = 258 -DB_PERF_SEL_DB_SC_c_tile_rate = 259 -DB_PERF_SEL_DB_SC_z_tile_rate = 260 -DB_PERF_SEL_DB_CB_export_export_quads = 261 -DB_PERF_SEL_DB_CB_export_double_format = 262 -DB_PERF_SEL_DB_CB_export_fast_format = 263 -DB_PERF_SEL_DB_CB_export_slow_format = 264 -DB_PERF_SEL_CB_DB_rdreq_sends = 265 -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 -DB_PERF_SEL_CB_DB_wrreq_sends = 267 -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 -DB_PERF_SEL_DB_CB_rdret_ack = 269 -DB_PERF_SEL_DB_CB_rdret_nack = 270 -DB_PERF_SEL_DB_CB_wrret_ack = 271 -DB_PERF_SEL_DB_CB_wrret_nack = 272 -DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 -DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 -DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 -DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 -DB_PERF_SEL_unmapped_z_tile_culled = 277 -DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 -DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 -DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS = 280 -DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event = 281 -DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix = 282 -DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix = 283 -DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix = 284 -DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix = 285 -DB_PERF_SEL_DB_CB_export_num_pixels_need_blending = 286 -DB_PERF_SEL_DB_CB_context_dones = 287 -DB_PERF_SEL_DB_CB_eop_dones = 288 -DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 -DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 -DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 -DB_PERF_SEL_SC_DB_tile_backface = 292 -DB_PERF_SEL_SC_DB_quad_quads = 293 -DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 -DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 -DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 -DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 -DB_PERF_SEL_DB_SC_quad_double_quad = 298 -DB_PERF_SEL_SX_DB_quad_export_quads = 299 -DB_PERF_SEL_SX_DB_quad_double_format = 300 -DB_PERF_SEL_SX_DB_quad_fast_format = 301 -DB_PERF_SEL_SX_DB_quad_slow_format = 302 -DB_PERF_SEL_quad_rd_sends_unc = 303 -DB_PERF_SEL_quad_rd_mi_stall_unc = 304 -DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 -DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 -DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 -DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 -DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 -DB_PERF_SEL_noz_waiting_for_postz_done = 310 -DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1 = 311 -DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1 = 312 -DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2 = 313 -DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2 = 314 -DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 -DB_PERF_SEL_RMI_rd_z_32byte_req = 316 -DB_PERF_SEL_RMI_rd_s_32byte_req = 317 -DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 -DB_PERF_SEL_RMI_wr_z_32byte_req = 319 -DB_PERF_SEL_RMI_wr_s_32byte_req = 320 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 -DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 -DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 -DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 -DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 -DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 -DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 -DB_PERF_SEL_esr_vic_sqq_busy = 329 -DB_PERF_SEL_esr_vic_sqq_stall = 330 -DB_PERF_SEL_esr_psi_vic_tile_rate = 331 -DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 -DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 -DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 -DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 -DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 -DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 -DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 -DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 -DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 -DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 -DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 -DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 -DB_PERF_SEL_ts_events_pws_enable = 344 -DB_PERF_SEL_ps_events_pws_enable = 345 -DB_PERF_SEL_cs_events_pws_enable = 346 -DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 -DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 -DB_PERF_SEL_DB_SC_quad_conflicts = 349 -DB_PERF_SEL_SC_DB_quad_vrs_1x1 = 350 -DB_PERF_SEL_SC_DB_quad_vrs_1x2 = 351 -DB_PERF_SEL_SC_DB_quad_vrs_2x1 = 352 -DB_PERF_SEL_SC_DB_quad_vrs_2x2 = 353 -DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa = 354 -DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa = 355 -DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa = 356 -DB_PERF_SEL_SC_DB_wave_sends = 357 -DB_PERF_SEL_SC_DB_wave_busy = 358 -DB_PERF_SEL_SC_DB_wave_quads = 359 -DB_PERF_SEL_SC_DB_wave_id_wrapped = 360 -DB_PERF_SEL_DB_SC_wave_sends = 361 -DB_PERF_SEL_DB_SC_wave_busy = 362 -DB_PERF_SEL_DB_SC_wave_stalls = 363 -DB_PERF_SEL_DB_SC_wave_conflict = 364 -DB_PERF_SEL_DB_SC_wave_hard_conflict = 365 -DB_PERF_SEL_DB_SC_wave_id_wrapped = 366 -DB_PERF_SEL_SX_DB_quad_waves = 367 -DB_PERF_SEL_pws_stall = 368 -DB_PERF_SEL_pws_liveness_stall_dtt_tag = 369 -DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr = 370 -DB_PERF_SEL_OREO_TT_load = 371 -DB_PERF_SEL_OREO_TT_read = 372 -DB_PERF_SEL_OREO_TT_stalls = 373 -DB_PERF_SEL_OREO_ST_load = 374 -DB_PERF_SEL_OREO_ST_read = 375 -DB_PERF_SEL_OREO_ST_stalls = 376 -DB_PERF_SEL_OREO_WT_load = 377 -DB_PERF_SEL_OREO_WT_read = 378 -DB_PERF_SEL_OREO_SB_misses = 379 -DB_PERF_SEL_OREO_SB_hits = 380 -DB_PERF_SEL_OREO_SB_evicts = 381 -DB_PERF_SEL_OREO_SB_stalls = 382 -DB_PERF_SEL_OREO_Events_load = 383 -DB_PERF_SEL_OREO_Events_transition = 384 -DB_PERF_SEL_OREO_Events_non_transition = 385 -DB_PERF_SEL_OREO_Events_delayed = 386 -DB_PERF_SEL_OREO_Events_stalls = 387 -PerfCounter_Vals = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeCounterId' -PixelPipeCounterId__enumvalues = { - 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', - 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', -} -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 -PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 -PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 -PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 -PixelPipeCounterId = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeStride' -PixelPipeStride__enumvalues = { - 0: 'PIXEL_PIPE_STRIDE_32_BITS', - 1: 'PIXEL_PIPE_STRIDE_64_BITS', - 2: 'PIXEL_PIPE_STRIDE_128_BITS', - 3: 'PIXEL_PIPE_STRIDE_256_BITS', -} -PIXEL_PIPE_STRIDE_32_BITS = 0 -PIXEL_PIPE_STRIDE_64_BITS = 1 -PIXEL_PIPE_STRIDE_128_BITS = 2 -PIXEL_PIPE_STRIDE_256_BITS = 3 -PixelPipeStride = ctypes.c_uint32 # enum - -# values for enumeration 'RingCounterControl' -RingCounterControl__enumvalues = { - 0: 'COUNTER_RING_SPLIT', - 1: 'COUNTER_RING_0', - 2: 'COUNTER_RING_1', -} -COUNTER_RING_SPLIT = 0 -COUNTER_RING_0 = 1 -COUNTER_RING_1 = 2 -RingCounterControl = ctypes.c_uint32 # enum - -# values for enumeration 'StencilOp' -StencilOp__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_ONES', - 3: 'STENCIL_REPLACE_TEST', - 4: 'STENCIL_REPLACE_OP', - 5: 'STENCIL_ADD_CLAMP', - 6: 'STENCIL_SUB_CLAMP', - 7: 'STENCIL_INVERT', - 8: 'STENCIL_ADD_WRAP', - 9: 'STENCIL_SUB_WRAP', - 10: 'STENCIL_AND', - 11: 'STENCIL_OR', - 12: 'STENCIL_XOR', - 13: 'STENCIL_NAND', - 14: 'STENCIL_NOR', - 15: 'STENCIL_XNOR', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_ONES = 2 -STENCIL_REPLACE_TEST = 3 -STENCIL_REPLACE_OP = 4 -STENCIL_ADD_CLAMP = 5 -STENCIL_SUB_CLAMP = 6 -STENCIL_INVERT = 7 -STENCIL_ADD_WRAP = 8 -STENCIL_SUB_WRAP = 9 -STENCIL_AND = 10 -STENCIL_OR = 11 -STENCIL_XOR = 12 -STENCIL_NAND = 13 -STENCIL_NOR = 14 -STENCIL_XNOR = 15 -StencilOp = ctypes.c_uint32 # enum - -# values for enumeration 'ZLimitSumm' -ZLimitSumm__enumvalues = { - 0: 'FORCE_SUMM_OFF', - 1: 'FORCE_SUMM_MINZ', - 2: 'FORCE_SUMM_MAXZ', - 3: 'FORCE_SUMM_BOTH', -} -FORCE_SUMM_OFF = 0 -FORCE_SUMM_MINZ = 1 -FORCE_SUMM_MAXZ = 2 -FORCE_SUMM_BOTH = 3 -ZLimitSumm = ctypes.c_uint32 # enum - -# values for enumeration 'ZModeForce' -ZModeForce__enumvalues = { - 0: 'NO_FORCE', - 1: 'FORCE_EARLY_Z', - 2: 'FORCE_LATE_Z', - 3: 'FORCE_RE_Z', -} -NO_FORCE = 0 -FORCE_EARLY_Z = 1 -FORCE_LATE_Z = 2 -FORCE_RE_Z = 3 -ZModeForce = ctypes.c_uint32 # enum - -# values for enumeration 'ZOrder' -ZOrder__enumvalues = { - 0: 'LATE_Z', - 1: 'EARLY_Z_THEN_LATE_Z', - 2: 'RE_Z', - 3: 'EARLY_Z_THEN_RE_Z', -} -LATE_Z = 0 -EARLY_Z_THEN_LATE_Z = 1 -RE_Z = 2 -EARLY_Z_THEN_RE_Z = 3 -ZOrder = ctypes.c_uint32 # enum - -# values for enumeration 'ZSamplePosition' -ZSamplePosition__enumvalues = { - 0: 'Z_SAMPLE_CENTER', - 1: 'Z_SAMPLE_CENTROID', -} -Z_SAMPLE_CENTER = 0 -Z_SAMPLE_CENTROID = 1 -ZSamplePosition = ctypes.c_uint32 # enum - -# values for enumeration 'SU_PERFCNT_SEL' -SU_PERFCNT_SEL__enumvalues = { - 0: 'PERF_PAPC_PASX_REQ', - 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 8: 'PERF_CLPR_INPUT_PRIM', - 9: 'PERF_CLPR_INPUT_NULL_PRIM', - 10: 'PERF_CLPR_INPUT_EVENT', - 11: 'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP', - 12: 'PERF_CLPR_INPUT_END_OF_PACKET', - 13: 'PERF_CLPR_INPUT_EXTENDED_EVENT', - 14: 'PERF_PAPC_CLPR_CULL_PRIM', - 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', - 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', - 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', - 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 30: 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS', - 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', - 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', - 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 39: 'PERF_PAPC_CLSM_NULL_PRIM', - 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', - 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', - 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', - 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS', - 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', - 49: 'PERF_PAPC_SU_INPUT_PRIM', - 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', - 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 61: 'PERF_PAPC_SU_OUTPUT_PRIM', - 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', - 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', - 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 77: 'PERF_PAPC_PASX_REQ_IDLE', - 78: 'PERF_PAPC_PASX_REQ_BUSY', - 79: 'PERF_PAPC_PASX_REQ_STALLED', - 80: 'PERF_PAPC_PASX_REC_IDLE', - 81: 'PERF_PAPC_PASX_REC_BUSY', - 82: 'PERF_PAPC_PASX_REC_STARVED_SX', - 83: 'PERF_PAPC_PASX_REC_STALLED', - 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 86: 'PERF_PAPC_CCGSM_IDLE', - 87: 'PERF_PAPC_CCGSM_BUSY', - 88: 'PERF_PAPC_CCGSM_STALLED', - 89: 'PERF_PAPC_CLPRIM_IDLE', - 90: 'PERF_PAPC_CLPRIM_BUSY', - 91: 'PERF_PAPC_CLPRIM_STALLED', - 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 93: 'PERF_PAPC_CLIPSM_IDLE', - 94: 'PERF_PAPC_CLIPSM_BUSY', - 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', - 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 100: 'PERF_PAPC_CLIPGA_IDLE', - 101: 'PERF_PAPC_CLIPGA_BUSY', - 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 103: 'PERF_PAPC_CLIPGA_STALLED', - 104: 'PERF_PAPC_CLIP_IDLE', - 105: 'PERF_PAPC_CLIP_BUSY', - 106: 'PERF_PAPC_SU_IDLE', - 107: 'PERF_PAPC_SU_BUSY', - 108: 'PERF_PAPC_SU_STARVED_CLIP', - 109: 'PERF_PAPC_SU_STALLED_SC', - 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', - 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', - 112: 'PERF_PAPC_PA_REG_SCLK_VLD', - 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 125: 'PERF_PAPC_SU_ALL_OUTPUT_PRIM', - 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 128: 'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM', - 131: 'PERF_PAPC_SU_SE0_STALLED_SC', - 132: 'PERF_PAPC_SU_SE1_STALLED_SC', - 133: 'PERF_PAPC_SU_ALL_STALLED_SC', - 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 135: 'PERF_PAPC_SU_CULLED_PRIM', - 136: 'PERF_PAPC_SU_OUTPUT_EOPG', - 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 151: 'PERF_PAPC_SU_SE2_STALLED_SC', - 152: 'PERF_PAPC_SU_SE3_STALLED_SC', - 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', - 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', - 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', - 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', - 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', - 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', - 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', - 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 177: 'PERF_PA_VERTEX_FIFO_FULL', - 178: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', - 179: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 183: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 184: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 185: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 186: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 188: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 189: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 190: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', - 191: 'PERF_ENGG_CSB_NULL_SUBGROUP', - 192: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 193: 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 194: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', - 195: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 196: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', - 224: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 225: 'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM', - 226: 'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM', - 227: 'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM', - 228: 'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM', - 229: 'PERF_ENGG_INDEX_REQ_STARVED', - 230: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 231: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 232: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 233: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 234: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 235: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 236: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 237: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 238: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 239: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 240: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 241: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 242: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 243: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 244: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 258: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 259: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 260: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 261: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 262: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 263: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 264: 'PERF_ENGG_POS_REQ_STARVED', - 265: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 266: 'PERF_ENGG_BUSY', - 267: 'PERF_CLIPSM_CULL_PRIMS_CNT', - 268: 'PERF_PH_SEND_1_SC', - 269: 'PERF_PH_SEND_2_SC', - 270: 'PERF_PH_SEND_3_SC', - 271: 'PERF_PH_SEND_4_SC', - 272: 'PERF_OUTPUT_PRIM_1_SC', - 273: 'PERF_OUTPUT_PRIM_2_SC', - 274: 'PERF_OUTPUT_PRIM_3_SC', - 275: 'PERF_OUTPUT_PRIM_4_SC', - 276: 'PERF_PASX_POS_VECTOR', - 277: 'PERF_PASX_MISC_VECTOR', - 278: 'PERF_PASX_CCDIST0_VECTOR', - 279: 'PERF_PASX_CCDIST1_VECTOR', - 280: 'PERF_PASX_STEREO_POS_VECTOR', - 281: 'PERF_CLPR_INPUT_SEND', - 282: 'PERF_SU_INPUT_SEND', - 283: 'PERF_SU_OUTPUT_SEND', - 284: 'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL', - 285: 'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL', - 286: 'PERF_PAPC_SU_SE4_OUTPUT_PRIM', - 287: 'PERF_PAPC_SU_SE5_OUTPUT_PRIM', - 288: 'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM', - 289: 'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM', - 290: 'PERF_PAPC_SU_SE4_STALLED_SC', - 291: 'PERF_PAPC_SU_SE5_STALLED_SC', - 292: 'PERF_ENGG_INDEX_RET0_NEW_VERTS', - 293: 'PERF_ENGG_INDEX_RET1_NEW_VERTS', - 294: 'PERF_ENGG_INDEX_RET2_NEW_VERTS', - 295: 'PERF_ENGG_INDEX_RET3_NEW_VERTS', - 296: 'PERF_ENGG_INDEX_RET4_NEW_VERTS', - 297: 'PERF_ENGG_INDEX_RET5_NEW_VERTS', - 298: 'PERF_ENGG_INDEX_RET6_NEW_VERTS', - 299: 'PERF_ENGG_INDEX_RET7_NEW_VERTS', - 300: 'PERF_ENGG_INDEX_RET8_NEW_VERTS', - 301: 'PERF_ENGG_INDEX_RET9_NEW_VERTS', - 302: 'PERF_ENGG_INDEX_RET10_NEW_VERTS', - 303: 'PERF_ENGG_INDEX_RET11_NEW_VERTS', - 304: 'PERF_ENGG_INDEX_RET12_NEW_VERTS', - 305: 'PERF_PH_SEND_5_SC', - 306: 'PERF_PH_SEND_6_SC', - 307: 'PERF_OUTPUT_PRIM_5_SC', - 308: 'PERF_OUTPUT_PRIM_6_SC', - 309: 'PERF_CLPR_BACK_PRIM', - 310: 'PERF_PA_BUSY', -} -PERF_PAPC_PASX_REQ = 0 -PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 -PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 -PERF_CLPR_INPUT_PRIM = 8 -PERF_CLPR_INPUT_NULL_PRIM = 9 -PERF_CLPR_INPUT_EVENT = 10 -PERF_CLPR_INPUT_FIRST_OF_SUBGROUP = 11 -PERF_CLPR_INPUT_END_OF_PACKET = 12 -PERF_CLPR_INPUT_EXTENDED_EVENT = 13 -PERF_PAPC_CLPR_CULL_PRIM = 14 -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 -PERF_PAPC_CLPR_VV_CULL_PRIM = 16 -PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 -PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 -PERF_CLPR_CLIP_PLANE_CNT_9_PLUS = 30 -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 -PERF_PAPC_CLSM_NULL_PRIM = 39 -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS = 47 -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 -PERF_PAPC_SU_INPUT_PRIM = 49 -PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 -PERF_PAPC_SU_INPUT_NULL_PRIM = 51 -PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 -PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 -PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 -PERF_PAPC_SU_OUTPUT_PRIM = 61 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 -PERF_PAPC_PASX_REQ_IDLE = 77 -PERF_PAPC_PASX_REQ_BUSY = 78 -PERF_PAPC_PASX_REQ_STALLED = 79 -PERF_PAPC_PASX_REC_IDLE = 80 -PERF_PAPC_PASX_REC_BUSY = 81 -PERF_PAPC_PASX_REC_STARVED_SX = 82 -PERF_PAPC_PASX_REC_STALLED = 83 -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 -PERF_PAPC_CCGSM_IDLE = 86 -PERF_PAPC_CCGSM_BUSY = 87 -PERF_PAPC_CCGSM_STALLED = 88 -PERF_PAPC_CLPRIM_IDLE = 89 -PERF_PAPC_CLPRIM_BUSY = 90 -PERF_PAPC_CLPRIM_STALLED = 91 -PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 -PERF_PAPC_CLIPSM_IDLE = 93 -PERF_PAPC_CLIPSM_BUSY = 94 -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 -PERF_PAPC_CLIPGA_IDLE = 100 -PERF_PAPC_CLIPGA_BUSY = 101 -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 -PERF_PAPC_CLIPGA_STALLED = 103 -PERF_PAPC_CLIP_IDLE = 104 -PERF_PAPC_CLIP_BUSY = 105 -PERF_PAPC_SU_IDLE = 106 -PERF_PAPC_SU_BUSY = 107 -PERF_PAPC_SU_STARVED_CLIP = 108 -PERF_PAPC_SU_STALLED_SC = 109 -PERF_PAPC_CL_DYN_SCLK_VLD = 110 -PERF_PAPC_SU_DYN_SCLK_VLD = 111 -PERF_PAPC_PA_REG_SCLK_VLD = 112 -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 -PERF_PAPC_SU_ALL_OUTPUT_PRIM = 125 -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 -PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM = 128 -PERF_PAPC_SU_SE0_STALLED_SC = 131 -PERF_PAPC_SU_SE1_STALLED_SC = 132 -PERF_PAPC_SU_ALL_STALLED_SC = 133 -PERF_PAPC_CLSM_CLIPPING_PRIM = 134 -PERF_PAPC_SU_CULLED_PRIM = 135 -PERF_PAPC_SU_OUTPUT_EOPG = 136 -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 -PERF_PAPC_SU_SE2_STALLED_SC = 151 -PERF_PAPC_SU_SE3_STALLED_SC = 152 -PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 -PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 -PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 -PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 -PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 -PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 -PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 -PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 -PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 -PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 -PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 -PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 -PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 -PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169 -PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170 -PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171 -PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172 -PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173 -PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174 -PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175 -PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176 -PERF_PA_VERTEX_FIFO_FULL = 177 -PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 178 -PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 179 -PERF_ENGG_CSB_MACHINE_IS_STARVED = 183 -PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 184 -PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 185 -PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 186 -PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 188 -PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 189 -PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 190 -PERF_ENGG_CSB_NULL_SUBGROUP = 191 -PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 192 -PERF_ENGG_CSB_GE_MEMORY_FULL = 193 -PERF_ENGG_CSB_GE_MEMORY_EMPTY = 194 -PERF_ENGG_CSB_SPI_MEMORY_FULL = 195 -PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 196 -PERF_ENGG_INDEX_REQ_NULL_REQUEST = 224 -PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM = 225 -PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM = 226 -PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM = 227 -PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM = 228 -PERF_ENGG_INDEX_REQ_STARVED = 229 -PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 230 -PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 231 -PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 232 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 233 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 234 -PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 235 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 236 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 237 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 238 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 239 -PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 240 -PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 241 -PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 242 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 243 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 244 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 245 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 246 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 247 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 248 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 249 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 250 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 251 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 252 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 258 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 259 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 260 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 261 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 262 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 263 -PERF_ENGG_POS_REQ_STARVED = 264 -PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 265 -PERF_ENGG_BUSY = 266 -PERF_CLIPSM_CULL_PRIMS_CNT = 267 -PERF_PH_SEND_1_SC = 268 -PERF_PH_SEND_2_SC = 269 -PERF_PH_SEND_3_SC = 270 -PERF_PH_SEND_4_SC = 271 -PERF_OUTPUT_PRIM_1_SC = 272 -PERF_OUTPUT_PRIM_2_SC = 273 -PERF_OUTPUT_PRIM_3_SC = 274 -PERF_OUTPUT_PRIM_4_SC = 275 -PERF_PASX_POS_VECTOR = 276 -PERF_PASX_MISC_VECTOR = 277 -PERF_PASX_CCDIST0_VECTOR = 278 -PERF_PASX_CCDIST1_VECTOR = 279 -PERF_PASX_STEREO_POS_VECTOR = 280 -PERF_CLPR_INPUT_SEND = 281 -PERF_SU_INPUT_SEND = 282 -PERF_SU_OUTPUT_SEND = 283 -PERF_PAPC_SU_SE4_PRIM_FILTER_CULL = 284 -PERF_PAPC_SU_SE5_PRIM_FILTER_CULL = 285 -PERF_PAPC_SU_SE4_OUTPUT_PRIM = 286 -PERF_PAPC_SU_SE5_OUTPUT_PRIM = 287 -PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM = 288 -PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM = 289 -PERF_PAPC_SU_SE4_STALLED_SC = 290 -PERF_PAPC_SU_SE5_STALLED_SC = 291 -PERF_ENGG_INDEX_RET0_NEW_VERTS = 292 -PERF_ENGG_INDEX_RET1_NEW_VERTS = 293 -PERF_ENGG_INDEX_RET2_NEW_VERTS = 294 -PERF_ENGG_INDEX_RET3_NEW_VERTS = 295 -PERF_ENGG_INDEX_RET4_NEW_VERTS = 296 -PERF_ENGG_INDEX_RET5_NEW_VERTS = 297 -PERF_ENGG_INDEX_RET6_NEW_VERTS = 298 -PERF_ENGG_INDEX_RET7_NEW_VERTS = 299 -PERF_ENGG_INDEX_RET8_NEW_VERTS = 300 -PERF_ENGG_INDEX_RET9_NEW_VERTS = 301 -PERF_ENGG_INDEX_RET10_NEW_VERTS = 302 -PERF_ENGG_INDEX_RET11_NEW_VERTS = 303 -PERF_ENGG_INDEX_RET12_NEW_VERTS = 304 -PERF_PH_SEND_5_SC = 305 -PERF_PH_SEND_6_SC = 306 -PERF_OUTPUT_PRIM_5_SC = 307 -PERF_OUTPUT_PRIM_6_SC = 308 -PERF_CLPR_BACK_PRIM = 309 -PERF_PA_BUSY = 310 -SU_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RMIPerfSel' -RMIPerfSel__enumvalues = { - 0: 'RMI_PERF_SEL_NONE', - 1: 'RMI_PERF_SEL_BUSY', - 2: 'RMI_PERF_SEL_REG_CLK_VLD', - 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', - 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', - 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 6: 'RMI_PERF_SEL_PERF_WINDOW', - 7: 'RMI_PERF_SEL_EVENT_SEND', - 8: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 9: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', - 10: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 11: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 12: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 13: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 14: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 15: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 16: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 17: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 18: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', - 19: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 20: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 21: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 22: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 23: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 24: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 25: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 26: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 27: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 28: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 29: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 30: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 31: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 32: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 33: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 34: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 35: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 36: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 37: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', - 38: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 39: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 40: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 41: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 42: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 43: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 44: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 45: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 46: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 47: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 48: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 49: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 50: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 51: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 52: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 53: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 54: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 55: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 56: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 57: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 58: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 59: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 60: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 61: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 62: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 63: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 64: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 65: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 66: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 67: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 68: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 69: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 70: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 71: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', - 72: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', - 73: 'RMI_PERF_SEL_RB_RMI_WR_IDLE', - 74: 'RMI_PERF_SEL_RB_RMI_WR_STARVE', - 75: 'RMI_PERF_SEL_RB_RMI_WR_STALL', - 76: 'RMI_PERF_SEL_RB_RMI_WR_BUSY', - 77: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', - 78: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', - 79: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', - 80: 'RMI_PERF_SEL_RB_RMI_RD_IDLE', - 81: 'RMI_PERF_SEL_RB_RMI_RD_STARVE', - 82: 'RMI_PERF_SEL_RB_RMI_RD_STALL', - 83: 'RMI_PERF_SEL_RB_RMI_RD_BUSY', - 84: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', - 85: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', - 86: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', - 87: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 88: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 89: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 90: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 91: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 92: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 93: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 94: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 95: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 96: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 97: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 98: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', - 99: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 100: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 101: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 102: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 103: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 104: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 105: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 106: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 107: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 108: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', - 109: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', - 110: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', - 111: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', - 112: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', - 113: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 114: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 115: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 116: 'RMI_PERF_SEL_TCIW_REQ', - 117: 'RMI_PERF_SEL_TCIW_BUSY', - 118: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 119: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 120: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 121: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 122: 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 123: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 124: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 125: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 126: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 127: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 128: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 129: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 130: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 131: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 132: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 133: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR', - 134: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR', - 135: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR', - 136: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR', - 137: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR', - 138: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR', -} -RMI_PERF_SEL_NONE = 0 -RMI_PERF_SEL_BUSY = 1 -RMI_PERF_SEL_REG_CLK_VLD = 2 -RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 -RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 -RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 -RMI_PERF_SEL_PERF_WINDOW = 6 -RMI_PERF_SEL_EVENT_SEND = 7 -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 8 -RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 9 -RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 10 -RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 11 -RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 12 -RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 13 -RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 14 -RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 15 -RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 16 -RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 17 -RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 18 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 19 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 20 -RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 21 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 22 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 23 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 24 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 25 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 26 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 27 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 28 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 29 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 30 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 31 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 32 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 33 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 34 -RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 35 -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 36 -RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 37 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 38 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 39 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 40 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 41 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 42 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 43 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 44 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 45 -RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 46 -RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 47 -RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 48 -RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 49 -RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 50 -RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 51 -RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 52 -RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 53 -RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 54 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 55 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 56 -RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 57 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 58 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 59 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 60 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 61 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 62 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 63 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 64 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 65 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 66 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 67 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 68 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 69 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 70 -RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 71 -RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 72 -RMI_PERF_SEL_RB_RMI_WR_IDLE = 73 -RMI_PERF_SEL_RB_RMI_WR_STARVE = 74 -RMI_PERF_SEL_RB_RMI_WR_STALL = 75 -RMI_PERF_SEL_RB_RMI_WR_BUSY = 76 -RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 77 -RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 78 -RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 79 -RMI_PERF_SEL_RB_RMI_RD_IDLE = 80 -RMI_PERF_SEL_RB_RMI_RD_STARVE = 81 -RMI_PERF_SEL_RB_RMI_RD_STALL = 82 -RMI_PERF_SEL_RB_RMI_RD_BUSY = 83 -RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 84 -RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 85 -RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 86 -RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 87 -RMI_PERF_SEL_RMI_TC_REQ_BUSY = 88 -RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 89 -RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 90 -RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 91 -RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 92 -RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 93 -RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 94 -RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 95 -RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 96 -RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 97 -RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 98 -RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 99 -RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 100 -RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 101 -RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 102 -RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 103 -RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 104 -RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 105 -RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 106 -RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 107 -RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 108 -RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 109 -RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 110 -RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 111 -RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 112 -RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 113 -RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 114 -RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 115 -RMI_PERF_SEL_TCIW_REQ = 116 -RMI_PERF_SEL_TCIW_BUSY = 117 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 118 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 119 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 120 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 121 -RMI_PERF_SEL_REORDER_FIFO_REQ = 122 -RMI_PERF_SEL_REORDER_FIFO_BUSY = 123 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 124 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 125 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 126 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 127 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 128 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 129 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 130 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 131 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 132 -RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR = 133 -RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR = 134 -RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR = 135 -RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR = 136 -RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR = 137 -RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR = 138 -RMIPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1PerfSel' -UTCL1PerfSel__enumvalues = { - 0: 'UTCL1_PERF_SEL_NONE', - 1: 'UTCL1_PERF_SEL_REQS', - 2: 'UTCL1_PERF_SEL_HITS', - 3: 'UTCL1_PERF_SEL_MISSES', - 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', - 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 6: 'UTCL1_PERF_SEL_UTCL2_REQS', - 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', - 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', - 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', - 13: 'UTCL1_PERF_SEL_RTNS', - 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', - 15: 'UTCL1_PERF_SEL_RANGE_INVREQS', - 16: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', - 17: 'UTCL1_PERF_SEL_BYPASS_REQS', - 18: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 19: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 20: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 21: 'UTCL1_PERF_SEL_CP_INVREQS', - 22: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 23: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K', - 24: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K', - 25: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K', - 26: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M', - 27: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M', - 28: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M', - 29: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M', - 30: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M', - 31: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M', - 32: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF', - 33: 'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM', - 34: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0', - 35: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1', - 36: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2', - 37: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3', - 38: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0', - 39: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1', - 40: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2', - 41: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3', - 42: 'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS', - 43: 'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS', - 44: 'UTCL1_PERF_SEL_HITS_PG_SIZE_1', - 45: 'UTCL1_PERF_SEL_HITS_PG_SIZE_2', - 46: 'UTCL1_PERF_SEL_HITS_PG_SIZE_3', - 47: 'UTCL1_PERF_SEL_HITS_PG_SIZE_4', - 48: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0', - 49: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1', - 50: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2', - 51: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3', - 52: 'UTCL1_PERF_SEL_AVG_INV_LATENCY', - 53: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0', - 54: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1', - 55: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2', - 56: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3', - 57: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0', - 58: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1', - 59: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2', - 60: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3', - 61: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0', - 62: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1', - 63: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2', - 64: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3', - 65: 'UTCL1_PERF_SEL_ALOG_INTERRUPT', - 66: 'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED', - 67: 'UTCL1_PERF_SEL_ALOG_CACHE_REQ', - 68: 'UTCL1_PERF_SEL_ALOG_CACHE_HIT', - 69: 'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS', -} -UTCL1_PERF_SEL_NONE = 0 -UTCL1_PERF_SEL_REQS = 1 -UTCL1_PERF_SEL_HITS = 2 -UTCL1_PERF_SEL_MISSES = 3 -UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 -UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 -UTCL1_PERF_SEL_UTCL2_REQS = 6 -UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 -UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 -UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 -UTCL1_PERF_SEL_STALL_MH_FULL = 10 -UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 -UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 -UTCL1_PERF_SEL_RTNS = 13 -UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 -UTCL1_PERF_SEL_RANGE_INVREQS = 15 -UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 16 -UTCL1_PERF_SEL_BYPASS_REQS = 17 -UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 18 -UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 19 -UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 20 -UTCL1_PERF_SEL_CP_INVREQS = 21 -UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 22 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K = 23 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K = 24 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K = 25 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M = 26 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M = 27 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M = 28 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M = 29 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M = 30 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M = 31 -UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF = 32 -UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM = 33 -UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0 = 34 -UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1 = 35 -UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2 = 36 -UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3 = 37 -UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0 = 38 -UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1 = 39 -UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2 = 40 -UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3 = 41 -UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS = 42 -UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS = 43 -UTCL1_PERF_SEL_HITS_PG_SIZE_1 = 44 -UTCL1_PERF_SEL_HITS_PG_SIZE_2 = 45 -UTCL1_PERF_SEL_HITS_PG_SIZE_3 = 46 -UTCL1_PERF_SEL_HITS_PG_SIZE_4 = 47 -UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0 = 48 -UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1 = 49 -UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2 = 50 -UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3 = 51 -UTCL1_PERF_SEL_AVG_INV_LATENCY = 52 -UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0 = 53 -UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1 = 54 -UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2 = 55 -UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3 = 56 -UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0 = 57 -UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1 = 58 -UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2 = 59 -UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3 = 60 -UTCL1_PERF_SEL_EVICTIONS_NUM_CC0 = 61 -UTCL1_PERF_SEL_EVICTIONS_NUM_CC1 = 62 -UTCL1_PERF_SEL_EVICTIONS_NUM_CC2 = 63 -UTCL1_PERF_SEL_EVICTIONS_NUM_CC3 = 64 -UTCL1_PERF_SEL_ALOG_INTERRUPT = 65 -UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED = 66 -UTCL1_PERF_SEL_ALOG_CACHE_REQ = 67 -UTCL1_PERF_SEL_ALOG_CACHE_HIT = 68 -UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS = 69 -UTCL1PerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'GC_EA_SE_PERFCOUNT_SEL' -GC_EA_SE_PERFCOUNT_SEL__enumvalues = { - 0: 'GC_EA_SE_PERF_SEL_ALWAYS_COUNT', - 1: 'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD', - 2: 'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP', - 3: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', - 4: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0', - 5: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0', - 6: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1', - 7: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1', - 8: 'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD', - 9: 'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP', - 10: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', - 11: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0', - 12: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0', - 13: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1', - 14: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1', - 15: 'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD', - 16: 'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP', - 17: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', - 18: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0', - 19: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0', - 20: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1', - 21: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1', - 22: 'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD', - 23: 'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP', - 24: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', - 25: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0', - 26: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0', - 27: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1', - 28: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1', - 29: 'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP', - 30: 'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ', - 31: 'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ', - 32: 'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ', - 33: 'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ', - 34: 'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ', - 35: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0', - 36: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0', - 37: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1', - 38: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1', - 39: 'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP', - 40: 'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', - 41: 'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ', - 42: 'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ', - 43: 'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ', - 44: 'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ', - 45: 'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ', - 46: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0', - 47: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0', - 48: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1', - 49: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1', - 50: 'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC', - 51: 'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC', - 52: 'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC', - 53: 'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC', - 54: 'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ', - 55: 'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ', - 56: 'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ', - 57: 'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ', - 58: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0', - 59: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0', - 60: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1', - 61: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1', - 62: 'GC_EA_SE_PERF_SEL_SARB_BUSY', - 63: 'GC_EA_SE_PERF_SEL_SARB_STALLED', - 64: 'GC_EA_SE_PERF_SEL_SARB_STARVING', - 65: 'GC_EA_SE_PERF_SEL_SARB_IDLE', - 66: 'GC_EA_SE_PERF_SEL_RRET_VLD', - 67: 'GC_EA_SE_PERF_SEL_WRET_VLD', - 68: 'GC_EA_SE_PERF_SEL_PRB_REQ', - 69: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT', - 70: 'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD', - 71: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT', - 72: 'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY', - 73: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT', - 74: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', - 75: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED', - 76: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING', - 77: 'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ', - 78: 'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ', - 79: 'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ', - 80: 'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ', - 81: 'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', - 82: 'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND', - 83: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 84: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 85: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 86: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 87: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT', - 88: 'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD', - 89: 'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ', - 90: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', - 91: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', - 92: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ', - 93: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP', - 94: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', - 95: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', - 96: 'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING', - 97: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT', -} -GC_EA_SE_PERF_SEL_ALWAYS_COUNT = 0 -GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1 -GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2 -GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3 -GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0 = 4 -GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0 = 5 -GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1 = 6 -GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1 = 7 -GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8 -GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9 -GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10 -GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0 = 11 -GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0 = 12 -GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1 = 13 -GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1 = 14 -GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD = 15 -GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16 -GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17 -GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0 = 18 -GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0 = 19 -GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1 = 20 -GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1 = 21 -GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD = 22 -GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23 -GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24 -GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0 = 25 -GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0 = 26 -GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1 = 27 -GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1 = 28 -GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP = 29 -GC_EA_SE_PERF_SEL_RIO_SIZE_REQ = 30 -GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ = 31 -GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ = 32 -GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ = 33 -GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ = 34 -GC_EA_SE_PERF_SEL_RIO_LATENCY_START0 = 35 -GC_EA_SE_PERF_SEL_RIO_LATENCY_END0 = 36 -GC_EA_SE_PERF_SEL_RIO_LATENCY_START1 = 37 -GC_EA_SE_PERF_SEL_RIO_LATENCY_END1 = 38 -GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP = 39 -GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40 -GC_EA_SE_PERF_SEL_WIO_SIZE_REQ = 41 -GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ = 42 -GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ = 43 -GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ = 44 -GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ = 45 -GC_EA_SE_PERF_SEL_WIO_LATENCY_START0 = 46 -GC_EA_SE_PERF_SEL_WIO_LATENCY_END0 = 47 -GC_EA_SE_PERF_SEL_WIO_LATENCY_START1 = 48 -GC_EA_SE_PERF_SEL_WIO_LATENCY_END1 = 49 -GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC = 50 -GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51 -GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC = 52 -GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC = 53 -GC_EA_SE_PERF_SEL_SARB_SIZE_REQ = 54 -GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ = 55 -GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ = 56 -GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ = 57 -GC_EA_SE_PERF_SEL_SARB_LATENCY_START0 = 58 -GC_EA_SE_PERF_SEL_SARB_LATENCY_END0 = 59 -GC_EA_SE_PERF_SEL_SARB_LATENCY_START1 = 60 -GC_EA_SE_PERF_SEL_SARB_LATENCY_END1 = 61 -GC_EA_SE_PERF_SEL_SARB_BUSY = 62 -GC_EA_SE_PERF_SEL_SARB_STALLED = 63 -GC_EA_SE_PERF_SEL_SARB_STARVING = 64 -GC_EA_SE_PERF_SEL_SARB_IDLE = 65 -GC_EA_SE_PERF_SEL_RRET_VLD = 66 -GC_EA_SE_PERF_SEL_WRET_VLD = 67 -GC_EA_SE_PERF_SEL_PRB_REQ = 68 -GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT = 69 -GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD = 70 -GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT = 71 -GC_EA_SE_PERF_SEL_MAM_NUM_DQRY = 72 -GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73 -GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74 -GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED = 75 -GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING = 76 -GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ = 77 -GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ = 78 -GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ = 79 -GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ = 80 -GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81 -GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82 -GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83 -GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84 -GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85 -GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86 -GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT = 87 -GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD = 88 -GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89 -GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90 -GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91 -GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ = 92 -GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP = 93 -GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94 -GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95 -GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING = 96 -GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT = 97 -GC_EA_SE_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LSDMA_PERF_SEL' -LSDMA_PERF_SEL__enumvalues = { - 0: 'LSDMA_PERF_SEL_CYCLE', - 1: 'LSDMA_PERF_SEL_IDLE', - 2: 'LSDMA_PERF_SEL_REG_IDLE', - 3: 'LSDMA_PERF_SEL_RB_EMPTY', - 4: 'LSDMA_PERF_SEL_RB_FULL', - 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', - 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', - 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', - 13: 'LSDMA_PERF_SEL_EX_IDLE', - 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', - 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', - 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', - 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', - 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'LSDMA_PERF_SEL_SEM_IDLE', - 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'LSDMA_PERF_SEL_INT_IDLE', - 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', - 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'LSDMA_PERF_SEL_NUM_PACKET', - 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', - 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', - 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', - 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', - 47: 'LSDMA_PERF_SEL_DUMMY_0', - 48: 'LSDMA_PERF_SEL_DUMMY_1', - 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', - 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'LSDMA_PERF_SEL_CE_RD_STALL', - 52: 'LSDMA_PERF_SEL_CE_WR_STALL', - 53: 'LSDMA_PERF_SEL_GFX_SELECT', - 54: 'LSDMA_PERF_SEL_RLC0_SELECT', - 55: 'LSDMA_PERF_SEL_RLC1_SELECT', - 56: 'LSDMA_PERF_SEL_PAGE_SELECT', - 57: 'LSDMA_PERF_SEL_CTX_CHANGE', - 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'LSDMA_PERF_SEL_DOORBELL', - 61: 'LSDMA_PERF_SEL_RD_BA_RTR', - 62: 'LSDMA_PERF_SEL_WR_BA_RTR', - 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'LSDMA_PERF_SEL_CE_L1_STALL', - 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', - 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', - 72: 'LSDMA_PERF_SEL_ATCL2_FREE', - 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', - 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', - 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', - 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', - 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', - 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', - 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', - 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', - 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', - 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', - 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', - 110: 'LSDMA_PERF_SEL_CMD_OP_START', - 111: 'LSDMA_PERF_SEL_CMD_OP_END', - 112: 'LSDMA_PERF_SEL_CE_BUSY', - 113: 'LSDMA_PERF_SEL_CE_BUSY_START', - 114: 'LSDMA_PERF_SEL_CE_BUSY_END', - 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 122: 'LSDMA_PERF_SEL_DRAM_ECC', - 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', -} -LSDMA_PERF_SEL_CYCLE = 0 -LSDMA_PERF_SEL_IDLE = 1 -LSDMA_PERF_SEL_REG_IDLE = 2 -LSDMA_PERF_SEL_RB_EMPTY = 3 -LSDMA_PERF_SEL_RB_FULL = 4 -LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 -LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 -LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -LSDMA_PERF_SEL_RB_RPTR_WB = 8 -LSDMA_PERF_SEL_RB_CMD_IDLE = 9 -LSDMA_PERF_SEL_RB_CMD_FULL = 10 -LSDMA_PERF_SEL_IB_CMD_IDLE = 11 -LSDMA_PERF_SEL_IB_CMD_FULL = 12 -LSDMA_PERF_SEL_EX_IDLE = 13 -LSDMA_PERF_SEL_SRBM_REG_SEND = 14 -LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -LSDMA_PERF_SEL_MC_WR_IDLE = 16 -LSDMA_PERF_SEL_MC_WR_COUNT = 17 -LSDMA_PERF_SEL_MC_RD_IDLE = 18 -LSDMA_PERF_SEL_MC_RD_COUNT = 19 -LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 -LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -LSDMA_PERF_SEL_SEM_IDLE = 24 -LSDMA_PERF_SEL_SEM_REQ_STALL = 25 -LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 -LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 -LSDMA_PERF_SEL_SEM_RESP_PASS = 29 -LSDMA_PERF_SEL_INT_IDLE = 30 -LSDMA_PERF_SEL_INT_REQ_STALL = 31 -LSDMA_PERF_SEL_INT_REQ_COUNT = 32 -LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -LSDMA_PERF_SEL_INT_RESP_RETRY = 34 -LSDMA_PERF_SEL_NUM_PACKET = 35 -LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 -LSDMA_PERF_SEL_CE_WR_IDLE = 38 -LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 -LSDMA_PERF_SEL_CE_OUT_IDLE = 41 -LSDMA_PERF_SEL_CE_IN_IDLE = 42 -LSDMA_PERF_SEL_CE_DST_IDLE = 43 -LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 -LSDMA_PERF_SEL_DUMMY_0 = 47 -LSDMA_PERF_SEL_DUMMY_1 = 48 -LSDMA_PERF_SEL_CE_INFO_FULL = 49 -LSDMA_PERF_SEL_CE_INFO1_FULL = 50 -LSDMA_PERF_SEL_CE_RD_STALL = 51 -LSDMA_PERF_SEL_CE_WR_STALL = 52 -LSDMA_PERF_SEL_GFX_SELECT = 53 -LSDMA_PERF_SEL_RLC0_SELECT = 54 -LSDMA_PERF_SEL_RLC1_SELECT = 55 -LSDMA_PERF_SEL_PAGE_SELECT = 56 -LSDMA_PERF_SEL_CTX_CHANGE = 57 -LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -LSDMA_PERF_SEL_DOORBELL = 60 -LSDMA_PERF_SEL_RD_BA_RTR = 61 -LSDMA_PERF_SEL_WR_BA_RTR = 62 -LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 -LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 -LSDMA_PERF_SEL_CE_L1_STALL = 65 -LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 -LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 -LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 -LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 -LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 -LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 -LSDMA_PERF_SEL_ATCL2_FREE = 72 -LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 -LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 -LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 -LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 -LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 -LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 -LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 -LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 -LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 -LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 -LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 -LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 -LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 -LSDMA_PERF_SEL_L1_WR_INV_EN = 86 -LSDMA_PERF_SEL_L1_RD_INV_EN = 87 -LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 -LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 -LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 -LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 -LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 -LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 -LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 -LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 -LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 -LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 -LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 -LSDMA_PERF_SEL_CMD_OP_MATCH = 109 -LSDMA_PERF_SEL_CMD_OP_START = 110 -LSDMA_PERF_SEL_CMD_OP_END = 111 -LSDMA_PERF_SEL_CE_BUSY = 112 -LSDMA_PERF_SEL_CE_BUSY_START = 113 -LSDMA_PERF_SEL_CE_BUSY_END = 114 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 -LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 -LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 -LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 -LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 -LSDMA_PERF_SEL_DRAM_ECC = 122 -LSDMA_PERF_SEL_NACK_GEN_ERR = 123 -LSDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' -EFC_SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'EFC_ARGB1555', - 2: 'EFC_RGBA5551', - 3: 'EFC_RGB565', - 4: 'EFC_BGR565', - 5: 'EFC_ARGB4444', - 6: 'EFC_RGBA4444', - 8: 'EFC_ARGB8888', - 9: 'EFC_RGBA8888', - 10: 'EFC_ARGB2101010', - 11: 'EFC_RGBA1010102', - 12: 'EFC_AYCrCb8888', - 13: 'EFC_YCrCbA8888', - 14: 'EFC_ACrYCb8888', - 15: 'EFC_CrYCbA8888', - 16: 'EFC_ARGB16161616_10MSB', - 17: 'EFC_RGBA16161616_10MSB', - 18: 'EFC_ARGB16161616_10LSB', - 19: 'EFC_RGBA16161616_10LSB', - 20: 'EFC_ARGB16161616_12MSB', - 21: 'EFC_RGBA16161616_12MSB', - 22: 'EFC_ARGB16161616_12LSB', - 23: 'EFC_RGBA16161616_12LSB', - 24: 'EFC_ARGB16161616_FLOAT', - 25: 'EFC_RGBA16161616_FLOAT', - 26: 'EFC_ARGB16161616_UNORM', - 27: 'EFC_RGBA16161616_UNORM', - 28: 'EFC_ARGB16161616_SNORM', - 29: 'EFC_RGBA16161616_SNORM', - 32: 'EFC_AYCrCb16161616_10MSB', - 33: 'EFC_AYCrCb16161616_10LSB', - 34: 'EFC_YCrCbA16161616_10MSB', - 35: 'EFC_YCrCbA16161616_10LSB', - 36: 'EFC_ACrYCb16161616_10MSB', - 37: 'EFC_ACrYCb16161616_10LSB', - 38: 'EFC_CrYCbA16161616_10MSB', - 39: 'EFC_CrYCbA16161616_10LSB', - 40: 'EFC_AYCrCb16161616_12MSB', - 41: 'EFC_AYCrCb16161616_12LSB', - 42: 'EFC_YCrCbA16161616_12MSB', - 43: 'EFC_YCrCbA16161616_12LSB', - 44: 'EFC_ACrYCb16161616_12MSB', - 45: 'EFC_ACrYCb16161616_12LSB', - 46: 'EFC_CrYCbA16161616_12MSB', - 47: 'EFC_CrYCbA16161616_12LSB', - 64: 'EFC_Y8_CrCb88_420_PLANAR', - 65: 'EFC_Y8_CbCr88_420_PLANAR', - 66: 'EFC_Y10_CrCb1010_420_PLANAR', - 67: 'EFC_Y10_CbCr1010_420_PLANAR', - 68: 'EFC_Y12_CrCb1212_420_PLANAR', - 69: 'EFC_Y12_CbCr1212_420_PLANAR', - 72: 'EFC_YCrYCb8888_422_PACKED', - 73: 'EFC_YCbYCr8888_422_PACKED', - 74: 'EFC_CrYCbY8888_422_PACKED', - 75: 'EFC_CbYCrY8888_422_PACKED', - 76: 'EFC_YCrYCb10101010_422_PACKED', - 77: 'EFC_YCbYCr10101010_422_PACKED', - 78: 'EFC_CrYCbY10101010_422_PACKED', - 79: 'EFC_CbYCrY10101010_422_PACKED', - 80: 'EFC_YCrYCb12121212_422_PACKED', - 81: 'EFC_YCbYCr12121212_422_PACKED', - 82: 'EFC_CrYCbY12121212_422_PACKED', - 83: 'EFC_CbYCrY12121212_422_PACKED', - 112: 'EFC_RGB111110_FIX', - 113: 'EFC_BGR101111_FIX', - 114: 'EFC_ACrYCb2101010', - 115: 'EFC_CrYCbA1010102', - 118: 'EFC_RGB111110_FLOAT', - 119: 'EFC_BGR101111_FLOAT', - 120: 'EFC_MONO_8', - 121: 'EFC_MONO_10MSB', - 122: 'EFC_MONO_10LSB', - 123: 'EFC_MONO_12MSB', - 124: 'EFC_MONO_12LSB', - 125: 'EFC_MONO_16', -} -EFC_ARGB1555 = 1 -EFC_RGBA5551 = 2 -EFC_RGB565 = 3 -EFC_BGR565 = 4 -EFC_ARGB4444 = 5 -EFC_RGBA4444 = 6 -EFC_ARGB8888 = 8 -EFC_RGBA8888 = 9 -EFC_ARGB2101010 = 10 -EFC_RGBA1010102 = 11 -EFC_AYCrCb8888 = 12 -EFC_YCrCbA8888 = 13 -EFC_ACrYCb8888 = 14 -EFC_CrYCbA8888 = 15 -EFC_ARGB16161616_10MSB = 16 -EFC_RGBA16161616_10MSB = 17 -EFC_ARGB16161616_10LSB = 18 -EFC_RGBA16161616_10LSB = 19 -EFC_ARGB16161616_12MSB = 20 -EFC_RGBA16161616_12MSB = 21 -EFC_ARGB16161616_12LSB = 22 -EFC_RGBA16161616_12LSB = 23 -EFC_ARGB16161616_FLOAT = 24 -EFC_RGBA16161616_FLOAT = 25 -EFC_ARGB16161616_UNORM = 26 -EFC_RGBA16161616_UNORM = 27 -EFC_ARGB16161616_SNORM = 28 -EFC_RGBA16161616_SNORM = 29 -EFC_AYCrCb16161616_10MSB = 32 -EFC_AYCrCb16161616_10LSB = 33 -EFC_YCrCbA16161616_10MSB = 34 -EFC_YCrCbA16161616_10LSB = 35 -EFC_ACrYCb16161616_10MSB = 36 -EFC_ACrYCb16161616_10LSB = 37 -EFC_CrYCbA16161616_10MSB = 38 -EFC_CrYCbA16161616_10LSB = 39 -EFC_AYCrCb16161616_12MSB = 40 -EFC_AYCrCb16161616_12LSB = 41 -EFC_YCrCbA16161616_12MSB = 42 -EFC_YCrCbA16161616_12LSB = 43 -EFC_ACrYCb16161616_12MSB = 44 -EFC_ACrYCb16161616_12LSB = 45 -EFC_CrYCbA16161616_12MSB = 46 -EFC_CrYCbA16161616_12LSB = 47 -EFC_Y8_CrCb88_420_PLANAR = 64 -EFC_Y8_CbCr88_420_PLANAR = 65 -EFC_Y10_CrCb1010_420_PLANAR = 66 -EFC_Y10_CbCr1010_420_PLANAR = 67 -EFC_Y12_CrCb1212_420_PLANAR = 68 -EFC_Y12_CbCr1212_420_PLANAR = 69 -EFC_YCrYCb8888_422_PACKED = 72 -EFC_YCbYCr8888_422_PACKED = 73 -EFC_CrYCbY8888_422_PACKED = 74 -EFC_CbYCrY8888_422_PACKED = 75 -EFC_YCrYCb10101010_422_PACKED = 76 -EFC_YCbYCr10101010_422_PACKED = 77 -EFC_CrYCbY10101010_422_PACKED = 78 -EFC_CbYCrY10101010_422_PACKED = 79 -EFC_YCrYCb12121212_422_PACKED = 80 -EFC_YCbYCr12121212_422_PACKED = 81 -EFC_CrYCbY12121212_422_PACKED = 82 -EFC_CbYCrY12121212_422_PACKED = 83 -EFC_RGB111110_FIX = 112 -EFC_BGR101111_FIX = 113 -EFC_ACrYCb2101010 = 114 -EFC_CrYCbA1010102 = 115 -EFC_RGB111110_FLOAT = 118 -EFC_BGR101111_FLOAT = 119 -EFC_MONO_8 = 120 -EFC_MONO_10MSB = 121 -EFC_MONO_10LSB = 122 -EFC_MONO_12MSB = 123 -EFC_MONO_12LSB = 124 -EFC_MONO_16 = 125 -EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum -__all__ = \ - ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', - 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', - 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', - 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', - 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', - 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', - 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', - 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', - 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', - 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', - 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', - 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', - 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', - 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', - 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', - 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', - 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', - 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', - 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', - 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', - 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', - 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', - 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', - 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', - 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', - 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', - 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', - 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', - 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', - 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', - 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', - 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', - 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', - 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', - 'ALPHA_DATA_ONTO_Y_G_PORT', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', - 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', - 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', - 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', - 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', - 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', - 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', - 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', - 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', - 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', - 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', - 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', - 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', - 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', - 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', - 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', - 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', - 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', - 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', - 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', - 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', - 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', - 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', - 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', - 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', - 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', - 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', - 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', - 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', - 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', - 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', - 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', - 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', - 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', - 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', - 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', - 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', - 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', - 'AZ_RIRB_WRITE_POINTER_DO_RESET', - 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', - 'AZ_STATE_CHANGE_STATUS', - 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', - 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', - 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', - 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', - 'BINNING_DISABLED', 'BINNING_ONE_PRIM_PER_BATCH', - 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', - 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', - 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', - 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', - 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', - 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', - 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', - 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', - 'BLEND_ONE_MINUS_CONSTANT_ALPHA', - 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', - 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', - 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', - 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', - 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', - 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', - 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', - 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', - 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', - 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', - 'CACHE_LRU_WR', 'CACHE_NOA', 'CACHE_NOA_WR', 'CACHE_STREAM', - 'CACHE_STREAM_RD', 'CBMode', 'CBPerfClearFilterSel', - 'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ONTO_ALPHA_PORT', - 'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT', - 'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DISABLE', - 'CB_ELIMINATE_FAST_CLEAR', 'CB_NORMAL', - 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', - 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', - 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 'CB_PERF_SEL_BE_CS_FILLRATE_1X2', - 'CB_PERF_SEL_BE_CS_FILLRATE_2X1', - 'CB_PERF_SEL_BE_CS_FILLRATE_2X2', 'CB_PERF_SEL_BE_RDLATFIFO_FULL', - 'CB_PERF_SEL_BE_SRCFIFO_FULL', 'CB_PERF_SEL_BLEND_CLOCK_EN', - 'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE', - 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL', - 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS', 'CB_PERF_SEL_BUSY', - 'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC', - 'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL', - 'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC', - 'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL', - 'CB_PERF_SEL_CCC_FREE_WAYS_PANIC', - 'CB_PERF_SEL_CCC_FREE_WAYS_STALL', - 'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL', - 'CB_PERF_SEL_CCC_SKID_FIFO_FULL', - 'CB_PERF_SEL_CCC_SKID_FIFO_STALL', - 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY', - 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB', - 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY', - 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB', - 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_FLUSH', - 'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', - 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST', - 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT', - 'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST', - 'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES', - 'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN', - 'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT', - 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_QUADFRAG_VALID_READY', - 'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB', 'CB_PERF_SEL_CC_TAG_HIT', - 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', - 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', - 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_EVENT', - 'CB_PERF_SEL_EVENTS_CLK_EN', - 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT', - 'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS', - 'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS', - 'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST', - 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID', - 'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL', - 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK', - 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6', - 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7', - 'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT', - 'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6', - 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7', - 'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX', - 'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX', - 'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX', - 'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX', - 'CB_PERF_SEL_FORMAT_IS_32_ABGR', 'CB_PERF_SEL_FORMAT_IS_32_AR', - 'CB_PERF_SEL_FORMAT_IS_32_GR', 'CB_PERF_SEL_FORMAT_IS_32_R', - 'CB_PERF_SEL_FORMAT_IS_FP16_ABGR', - 'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR', - 'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR', - 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', - 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', - 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', 'CHA_PERF_SEL_REQUEST_CHC0', - 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', - 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1', - 'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', 'CHC_PERF_SEL', - 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', - 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', - 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', - 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', - 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', - 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', - 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', - 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', - 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', - 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', - 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', - 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', - 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', - 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', - 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', - 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', - 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', - 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', - 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', - 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', - 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', - 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', - 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', - 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', - 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', - 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLE', - 'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO', - 'CLOCK_GATING_DISABLE_ENUM', 'CLOCK_GATING_DISABLE_ENUM_DISABLED', - 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', - 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', - 'CLOCK_GATING_ENABLED_IN_DCO', 'CMC_3DLUT_17CUBE', - 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', - 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', - 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', - 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', - 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', - 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', - 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', - 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', - 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', - 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', - 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', - 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', - 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', - 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', - 'CM_GAMMA_LUT_SEL_ENUM', 'CM_LUT_2_CONFIG_ENUM', - 'CM_LUT_2_MODE_ENUM', 'CM_LUT_4_CONFIG_ENUM', - 'CM_LUT_4_MODE_ENUM', 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', - 'CM_LUT_RAM_SEL', 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', - 'CM_NOT_PENDING', 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', - 'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_ROUND', - 'CNVC_TRUNCATE', 'COEF_POST_CSC', 'COEF_POST_CSC_B', - 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', - 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', - 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', - 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_ENABLE', - 'COLOR_KEYER_MODE', 'COLOR_KEY_DIS', 'COLOR_KEY_EN', - 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', - 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', - 'COMPRESSION_MODE_BYPASS_COMPRESSION', - 'COMPRESSION_MODE_BYPASS_METADATA_CACHE', - 'COMPRESSION_MODE_COMPRESSION_ENABLED', - 'COMPRESSION_MODE_READ_DECOMPRESSED', - 'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA', - 'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED', - 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', - 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', - 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', - 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', - 'CORB_READ_POINTER_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', - 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', - 'CPC_LATENCY_STATS_SEL_INVAL_LAST', - 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', - 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', - 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MEC_THREAD0', - 'CPC_PERF_SEL_MEC_THREAD1', 'CPC_PERF_SEL_MEC_THREAD2', - 'CPC_PERF_SEL_MEC_THREAD3', 'CPC_PERF_SEL_MES_THREAD0', - 'CPC_PERF_SEL_MES_THREAD1', - 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', - 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', - 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 'CPF_LATENCY_STATS_SEL_READ_LAST', - 'CPF_LATENCY_STATS_SEL_READ_MAX', - 'CPF_LATENCY_STATS_SEL_READ_MIN', - 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', - 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', - 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', - 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', - 'CPF_PERF_SEL_ALWAYS_COUNT', - 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', - 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', - 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', - 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', - 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', - 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', - 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', - 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 'CPG_LATENCY_STATS_SEL_INVAL_LAST', - 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 'CPG_LATENCY_STATS_SEL_READ_LAST', - 'CPG_LATENCY_STATS_SEL_READ_MAX', - 'CPG_LATENCY_STATS_SEL_READ_MIN', - 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', - 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', - 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', - 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', - 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', - 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', - 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', - 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', - 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', - 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', - 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', - 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', - 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', - 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', - 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', - 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', - 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', - 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', - 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_DMA_BUSY', - 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', - 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', - 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0', - 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1', - 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0', - 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1', - 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0', - 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', - 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', - 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', - 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', - 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', - 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', - 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', - 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', - 'CRC_INTERLACE_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1', - 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5', - 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0', - 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', - 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', - 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', - 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', - 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', - 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', - 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', - 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', - 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', - 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', - 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', - 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', - 'CS_PARTIAL_FLUSH', 'CURSOR_2X_MAGNIFY', - 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', - 'CURSOR_COLOR_24BIT_1BIT_AND', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 'CURSOR_COLOR_64BIT_FP_PREMULT', - 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', - 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', - 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', - 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', - 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', - 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', - 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', - 'CURSOR_MODE', 'CURSOR_MONO_2BIT', - 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_EN', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', - 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', - 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', - 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', - 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', - 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', - 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', - 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', - 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', - 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', - 'CUR_INV_CLAMP', 'CUR_MATRIX_COEF_FORMAT_ENUM', - 'CUR_MATRIX_FIX_S2_13', 'CUR_MATRIX_FIX_S3_12', 'CUR_MODE', - 'CUR_NOT_PENDING', 'CUR_PENDING', 'CUR_ROM_EN', 'CUR_YES_PENDING', - 'CUR_ZERO_EXPANSION', 'CbYCrY10101010_422_PACKED', - 'CbYCrY12121212_422_PACKED', 'CbYCrY8888_422_PACKED', 'CombFunc', - 'CompareFrag', 'ConservativeZExport', 'CovToShaderSel', - 'CrYCbA1010102', 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', - 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', - 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', - 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', - 'DAC_MUX_SELECT_DACB', 'DB_BYPASS', 'DB_BYPASS_WR_DISABLE', - 'DB_CACHE_FLUSH_AND_INV', 'DB_COMP_WR_DISABLE', 'DB_DEFAULT', - 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 'DB_PERF_SEL_CB_DB_rdreq_sends', - 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 'DB_PERF_SEL_CB_DB_wrreq_sends', - 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', - 'DB_PERF_SEL_DB_CB_export_busy', - 'DB_PERF_SEL_DB_CB_export_double_format', - 'DB_PERF_SEL_DB_CB_export_events', - 'DB_PERF_SEL_DB_CB_export_export_quads', - 'DB_PERF_SEL_DB_CB_export_fast_format', - 'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix', - 'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix', - 'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix', - 'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix', - 'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS', - 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS', - 'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending', - 'DB_PERF_SEL_DB_CB_export_quads', - 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1', - 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2', - 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1', - 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2', - 'DB_PERF_SEL_DB_CB_export_sends', - 'DB_PERF_SEL_DB_CB_export_slow_format', - 'DB_PERF_SEL_DB_CB_export_stalls', - 'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event', - 'DB_PERF_SEL_DB_CB_rdret_ack', 'DB_PERF_SEL_DB_CB_rdret_nack', - 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', - 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', - 'DB_PERF_SEL_DB_SC_quad_conflicts', - 'DB_PERF_SEL_DB_SC_quad_double_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', - 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', - 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', - 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 'DB_PERF_SEL_DB_SC_tile_stalls', - 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_wave_busy', - 'DB_PERF_SEL_DB_SC_wave_conflict', - 'DB_PERF_SEL_DB_SC_wave_hard_conflict', - 'DB_PERF_SEL_DB_SC_wave_id_wrapped', - 'DB_PERF_SEL_DB_SC_wave_sends', 'DB_PERF_SEL_DB_SC_wave_stalls', - 'DB_PERF_SEL_DB_SC_z_tile_rate', - 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 'DB_PERF_SEL_Depth_Tile_Cache_event', - 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 'DB_PERF_SEL_OREO_Events_delayed', 'DB_PERF_SEL_OREO_Events_load', - 'DB_PERF_SEL_OREO_Events_non_transition', - 'DB_PERF_SEL_OREO_Events_stalls', - 'DB_PERF_SEL_OREO_Events_transition', - 'DB_PERF_SEL_OREO_SB_evicts', 'DB_PERF_SEL_OREO_SB_hits', - 'DB_PERF_SEL_OREO_SB_misses', 'DB_PERF_SEL_OREO_SB_stalls', - 'DB_PERF_SEL_OREO_ST_load', 'DB_PERF_SEL_OREO_ST_read', - 'DB_PERF_SEL_OREO_ST_stalls', 'DB_PERF_SEL_OREO_TT_load', - 'DB_PERF_SEL_OREO_TT_read', 'DB_PERF_SEL_OREO_TT_stalls', - 'DB_PERF_SEL_OREO_WT_load', 'DB_PERF_SEL_OREO_WT_read', - 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 'DB_PERF_SEL_Plane_Cache_flushes', - 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', - 'DB_PERF_SEL_Plane_Cache_misses', - 'DB_PERF_SEL_Plane_Cache_starves', - 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 'DB_PERF_SEL_PostZ_Samples_failing_S', - 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 'DB_PERF_SEL_PreZ_Samples_failing_S', - 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', - 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', - 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_quad_vrs_1x1', - 'DB_PERF_SEL_SC_DB_quad_vrs_1x2', - 'DB_PERF_SEL_SC_DB_quad_vrs_2x1', - 'DB_PERF_SEL_SC_DB_quad_vrs_2x2', - 'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa', - 'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa', - 'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa', - 'DB_PERF_SEL_SC_DB_tile_backface', 'DB_PERF_SEL_SC_DB_tile_busy', - 'DB_PERF_SEL_SC_DB_tile_covered', 'DB_PERF_SEL_SC_DB_tile_events', - 'DB_PERF_SEL_SC_DB_tile_sends', 'DB_PERF_SEL_SC_DB_tile_stalls', - 'DB_PERF_SEL_SC_DB_tile_tiles', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 'DB_PERF_SEL_SC_DB_wave_busy', - 'DB_PERF_SEL_SC_DB_wave_id_wrapped', - 'DB_PERF_SEL_SC_DB_wave_quads', 'DB_PERF_SEL_SC_DB_wave_sends', - 'DB_PERF_SEL_SH_quads_outstanding_sum', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 'DB_PERF_SEL_SX_DB_quad_busy', - 'DB_PERF_SEL_SX_DB_quad_double_format', - 'DB_PERF_SEL_SX_DB_quad_export_quads', - 'DB_PERF_SEL_SX_DB_quad_exports', - 'DB_PERF_SEL_SX_DB_quad_fast_format', - 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', - 'DB_PERF_SEL_SX_DB_quad_sends', - 'DB_PERF_SEL_SX_DB_quad_slow_format', - 'DB_PERF_SEL_SX_DB_quad_stalls', 'DB_PERF_SEL_SX_DB_quad_waves', - 'DB_PERF_SEL_Stencil_Cache_flushes', - 'DB_PERF_SEL_Stencil_Cache_frees', - 'DB_PERF_SEL_Stencil_Cache_hits', - 'DB_PERF_SEL_Stencil_Cache_misses', - 'DB_PERF_SEL_Stencil_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', - 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_surface_stall', - 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 'DB_PERF_SEL_Z_Cache_pmask_hits', - 'DB_PERF_SEL_Z_Cache_pmask_misses', - 'DB_PERF_SEL_Z_Cache_pmask_starves', - 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 'DB_PERF_SEL_clock_main_active', - 'DB_PERF_SEL_clock_mem_export_active', - 'DB_PERF_SEL_clock_reg_active', - 'DB_PERF_SEL_cs_events_pws_enable', - 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', - 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', - 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', - 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', - 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', - 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', - 'DB_PERF_SEL_dtt_sm_slot_stall', - 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', - 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', - 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', - 'DB_PERF_SEL_esr_ps_src_in_squads', - 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_stall', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', - 'DB_PERF_SEL_esr_ps_vic_stall', - 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', - 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', - 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_esr_stall', - 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', - 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', - 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', - 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', - 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', - 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', - 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', - 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', - 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', - 'DB_PERF_SEL_flush_compressed_stencil', - 'DB_PERF_SEL_flush_expanded_stencil', - 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', - 'DB_PERF_SEL_flush_single_stencil', - 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', - 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', - 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', - 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', - 'DB_PERF_SEL_noz_waiting_for_postz_done', - 'DB_PERF_SEL_planes_flushed', - 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_postzl_full_launch', - 'DB_PERF_SEL_postzl_partial_launch', - 'DB_PERF_SEL_postzl_partial_waiting', - 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', - 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', - 'DB_PERF_SEL_postzl_src_in_sends', - 'DB_PERF_SEL_postzl_src_in_squads', - 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 'DB_PERF_SEL_postzl_src_in_stall', - 'DB_PERF_SEL_postzl_src_in_tile_rate', - 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_postzl_src_out_stall', - 'DB_PERF_SEL_postzl_tile_init_stall', - 'DB_PERF_SEL_postzl_tile_mem_stall', - 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_prezl_src_in_sends', - 'DB_PERF_SEL_prezl_src_in_squads', - 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 'DB_PERF_SEL_prezl_src_in_stall', - 'DB_PERF_SEL_prezl_src_in_tile_rate', - 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_prezl_src_out_stall', - 'DB_PERF_SEL_prezl_tile_init_stall', - 'DB_PERF_SEL_prezl_tile_mem_stall', - 'DB_PERF_SEL_ps_events_pws_enable', - 'DB_PERF_SEL_pws_liveness_stall_dtt_tag', - 'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr', - 'DB_PERF_SEL_pws_stall', 'DB_PERF_SEL_qc_busy', - 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', - 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', - 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', - 'DB_PERF_SEL_quad_rd_mi_stall', - 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', - 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', - 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', - 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', - 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', - 'DB_PERF_SEL_quad_wr_coherency_stall', - 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', - 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', - 'DB_PERF_SEL_tcp_dispatcher_flushes', - 'DB_PERF_SEL_tcp_dispatcher_reads', - 'DB_PERF_SEL_tcp_prefetcher_flushes', - 'DB_PERF_SEL_tcp_prefetcher_reads', - 'DB_PERF_SEL_tcp_preloader_flushes', - 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', - 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', - 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 'DB_PERF_SEL_tiles_decomp_on_expclear', - 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', - 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', - 'DB_PERF_SEL_tl_expand_squads', - 'DB_PERF_SEL_tl_flush_expand_squads', - 'DB_PERF_SEL_tl_in_fast_z_stall', - 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', - 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', - 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', - 'DB_PERF_SEL_tl_preZ_squads', - 'DB_PERF_SEL_tl_stencil_locked_stall', - 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', - 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', - 'DB_PERF_SEL_tl_z_fetch_stall', - 'DB_PERF_SEL_ts_events_pws_enable', - 'DB_PERF_SEL_ts_tc_update_stall', - 'DB_PERF_SEL_tsc_insert_summarize_stall', - 'DB_PERF_SEL_unmapped_z_tile_culled', - 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', - 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 'DCCG_AUDIO_DTO_USE_512FBR_DTO', - 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', - 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', - 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', - 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', - 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', - 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', - 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', - 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', - 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', - 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', - 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', - 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', - 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', - 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', - 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_OFF', - 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', - 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', - 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', - 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', - 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', - 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', - 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', - 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', - 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', - 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', - 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', - 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', - 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', - 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', - 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', - 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', - 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', - 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', - 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', - 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', - 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', - 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', - 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', - 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', - 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', - 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', - 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', - 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', - 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', - 'DCIOCHIP_REF_27_SRC_SEL', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', - 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', - 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', - 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', - 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', - 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', - 'DCIO_DC_GENERICB_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', - 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', - 'DCIO_DC_GPU_TIMER_READ_SELECT', - 'DCIO_DC_GPU_TIMER_START_POSITION', - 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', - 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', - 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', - 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', - 'DCIO_DPCS_INTERRUPT_TYPE', - 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', - 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', - 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_EXT_VSYNC_MASK_NONE', - 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', - 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', - 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', - 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB', - 'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1', - 'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3', - 'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5', - 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 'DCIO_GENERICA_SEL_STEREOSYNC', 'DCIO_GENERICA_SEL_SYNCEN', - 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_STEREOSYNC', - 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENLK_CLK_GSL_MASK', - 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', - 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', - 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', - 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', - 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', - 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', - 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', - 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', - 'DCIO_GSL_SEL_GROUP_2', 'DCIO_PHY_HPO_ENC_SRC_SEL', - 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', - 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', - 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', - 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', - 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', - 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', - 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', - 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', - 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', - 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', - 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', - 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', - 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', - 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6', - 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7', - 'DCOH_TEST_CLOCK_MUX_SELECT_ENUM', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P', - 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R', - 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM', - 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED', - 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED', - 'DCOH_TOP_ENABLE_ENUM', 'DCOH_TOP_ENABLE_ENUM_DISABLED', - 'DCOH_TOP_ENABLE_ENUM_ENABLED', 'DC_DMCUB_INT_TYPE', - 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', - 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', - 'DECERR', 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', - 'DETILE_BUFFER_PACKER_IS_DISABLE', - 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', - 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', - 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', - 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', - 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', - 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', - 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', - 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', - 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', - 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', - 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DIFFERENT_RGB', - 'DIG_10BIT_TEST_PATTERN', 'DIG_ALTERNATING_TEST_PATTERN', - 'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', - 'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', - 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', - 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', - 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', - 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', - 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', - 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 'DIG_FE_CNTL_SOURCE_SELECT', 'DIG_FE_CNTL_STEREOSYNC_SELECT', - 'DIG_FE_SOURCE_FROM_OTG0', 'DIG_FE_SOURCE_FROM_OTG1', - 'DIG_FE_SOURCE_FROM_OTG2', 'DIG_FE_SOURCE_FROM_OTG3', - 'DIG_FE_SOURCE_RESERVED', 'DIG_FE_STEREOSYNC_FROM_OTG0', - 'DIG_FE_STEREOSYNC_FROM_OTG1', 'DIG_FE_STEREOSYNC_FROM_OTG2', - 'DIG_FE_STEREOSYNC_FROM_OTG3', 'DIG_FE_STEREOSYNC_RESERVED', - 'DIG_FIFO_1_PIX_PER_CYCLE', 'DIG_FIFO_2_PIX_PER_CYCLE', - 'DIG_FIFO_4_PIX_PER_CYCLE', 'DIG_FIFO_8_PIX_PER_CYCLE', - 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', - 'DIG_FIFO_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', - 'DIG_FIFO_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', - 'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE', 'DIG_FIFO_OVERFLOW_OCCURRED', - 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', - 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', - 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_IN_DEBUG_MODE', - 'DIG_IN_NORMAL_OPERATION', 'DIG_MODE', - 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', - 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', - 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', - 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', - 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', - 'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET', - 'DIG_STREAM_MAPPER_LINK0', 'DIG_STREAM_MAPPER_LINK1', - 'DIG_STREAM_MAPPER_LINK2', 'DIG_STREAM_MAPPER_LINK3', - 'DIG_STREAM_MAPPER_LINK6', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', - 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', - 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', - 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', - 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', - 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', - 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', - 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', - 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', - 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', - 'DIO_CLOCK_GATING_DIS', 'DIO_CLOCK_GATING_DISABLE', - 'DIO_CLOCK_GATING_EN', 'DIO_DBG_BLOCK_SEL', - 'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1', - 'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3', - 'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB', - 'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD', - 'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B', - 'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D', - 'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA', - 'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC', - 'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPFE_A', - 'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C', - 'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', - 'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR', - 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', - 'DIO_FIFO_ERROR_11', - 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', 'DISABLE_CLOCK_GATING', - 'DISABLE_CLOCK_GATING_IN_DCO', 'DISABLE_DEBUG', - 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_PWL', - 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', 'DISABLE_THE_FEATURE', - 'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE', - 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', - 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', - 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', - 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', - 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', - 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', - 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', - 'DI_INDEX_SIZE_8_BIT', 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', - 'DI_PT_LINELIST_ADJ', 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', - 'DI_PT_LINESTRIP_ADJ', 'DI_PT_NONE', 'DI_PT_PATCH', - 'DI_PT_POINTLIST', 'DI_PT_POLYGON', 'DI_PT_QUADLIST', - 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', 'DI_PT_TRIFAN', - 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', 'DI_PT_TRISTRIP', - 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', - 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', 'DI_SRC_SEL_AUTO_INDEX', - 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', 'DI_SRC_SEL_RESERVED', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', - 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', - 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', - 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', - 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', - 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', - 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', - 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', - 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', - 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', - 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', - 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', - 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', - 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', - 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', - 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', - 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', - 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', - 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', - 'DMU_DC_GPU_TIMER_START_POSITION', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', - 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', - 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', - 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', - 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', - 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_ABORT_XFER', - 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', - 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', - 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', - 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', - 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', - 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', - 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', - 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', - 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', - 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', - 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', - 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', - 'DOUT_I2C_DDC_SPEED_THRESHOLD', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', - 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', - 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', - 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP', - 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', - 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', - 'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0', - 'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2', - 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS', - 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN', - 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED', - 'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED', - 'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK', - 'DPHY_CRC_MST_PHASE_ERROR_ACKED', - 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', - 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', - 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', - 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', - 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', - 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', - 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', - 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', - 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', - 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', - 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', - 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', - 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', - 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', - 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', - 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', - 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', - 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', - 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', - 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', - 'DPTE_GROUP_SIZE_64B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', - 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', - 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', - 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED', - 'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 'DP_AUX_CONTROL_TEST_MODE_ENABLE', - 'DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', - 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', - 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', - 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', - 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', - 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', - 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', - 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', - 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', - 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', - 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 'DP_AUX_SW_CONTROL_LS_READ_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', - 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', - 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', - 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', - 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', - 'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPRESSED_PIXEL_FORMAT', - 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', - 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', - 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', - 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', - 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', - 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', - 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', - 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', - 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_LLCP', - 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 'DP_DPHY_SYM32_CRC_START_TP_START', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', - 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', - 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_LT_TPS1', - 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', - 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 'DP_DPHY_SYM32_OUTPUT_DPIA', 'DP_DPHY_SYM32_OUTPUT_PHY', - 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', - 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', - 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_SCHEDULER_ASLEEP', 'DP_DPHY_SYM32_SCHEDULER_AWAKE', - 'DP_DPHY_SYM32_SCHEDULER_OFF', 'DP_DPHY_SYM32_STATUS_ENABLED', - 'DP_DPHY_SYM32_STATUS_IDLE', 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', - 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_S422', - 'DP_DSC_N422_N420', 'DP_DTO_DESPREAD_DISABLE', - 'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE', - 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', - 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', - 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', - 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', - 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', - 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', - 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', - 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', - 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', - 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', - 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', - 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_MST_MODE', - 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_COMPRESSED', - 'DP_PIXEL_ENCODING_RGB_YCBCR444', 'DP_PIXEL_ENCODING_TYPE', - 'DP_PIXEL_ENCODING_UNCOMPRESSED', 'DP_PIXEL_ENCODING_YCBCR420', - 'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_Y_ONLY', - 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', - 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', - 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', - 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', - 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', - 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', - 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', - 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', - 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_SST_MODE', - 'DP_STEER_1_PIX_PER_CYCLE', 'DP_STEER_2_PIX_PER_CYCLE', - 'DP_STEER_4_PIX_PER_CYCLE', 'DP_STEER_8_PIX_PER_CYCLE', - 'DP_STEER_OUTPUT_PIXEL_PER_CYCLE', 'DP_STEER_OVERFLOW_ACK', - 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', - 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', - 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', - 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', - 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', - 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', - 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', - 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', - 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', - 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', - 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', - 'DP_STREAM_MAPPER_LINK2', 'DP_STREAM_MAPPER_LINK3', - 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', - 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', - 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', - 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', - 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', - 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', - 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', - 'DP_SYM32_ENC_PENDING', - 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', - 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', - 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', - 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', - 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', - 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', - 'DP_VID_1X_Nvid', 'DP_VID_2X_Nvid', 'DP_VID_4X_Nvid', - 'DP_VID_8X_Nvid', 'DP_VID_ENHANCED_FRAME_MODE', - 'DP_VID_M_N_CALC_AUTO', - 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', - 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', - 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_INTERVAL', - 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', - 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', - 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', - 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', - 'DSCCIF_BITS_PER_COMPONENT_ENUM', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', - 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 'DSCC_BITS_PER_COMPONENT_ENUM', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCC_DSC_VERSION_MAJOR_ENUM', - 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', - 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', - 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', - 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', - 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', - 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', - 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', - 'DS_HW_CAL_DIS', 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', - 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', - 'DS_REF_SRC', 'DVO_ENABLE_RST', 'DVO_ENABLE_RST_DISABLE', - 'DVO_ENABLE_RST_ENABLE', 'DWB_CRC_CONT_EN_CONT', - 'DWB_CRC_CONT_EN_ENUM', 'DWB_CRC_CONT_EN_ONE_SHOT', - 'DWB_CRC_SRC_SEL_DWB_IN', 'DWB_CRC_SRC_SEL_DWB_OUT', - 'DWB_CRC_SRC_SEL_ENUM', 'DWB_CRC_SRC_SEL_OGAM_OUT', - 'DWB_DATA_OVERFLOW_INT_TYPE_0', 'DWB_DATA_OVERFLOW_INT_TYPE_1', - 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', - 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', - 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', - 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', - 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', - 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', - 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', - 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', - 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', - 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', - 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', - 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', - 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', - 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', - 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', - 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', - 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', - 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', - 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', - 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', - 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', - 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', - 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', - 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', - 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', - 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', - 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', - 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', - 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', - 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', - 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', - 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', - 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', - 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', - 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', - 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', - 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', - 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', - 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', - 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', - 'EFC_BGR101111_FLOAT', 'EFC_BGR565', - 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', - 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', - 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', - 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', - 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', - 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', - 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', - 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', - 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', - 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', - 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', - 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', - 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', - 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', - 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', - 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', - 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', - 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', - 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', - 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', - 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', - 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', - 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', - 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', - 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', - 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', - 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', - 'ENABLE_PIPELINE_NOT_USED', 'ENABLE_PWL', 'ENABLE_TF0_OPT', - 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', - 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', - 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', - 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', - 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', - 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', - 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', - 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', - 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', - 'ENUM_DPG_FIELD_POLARITY', - 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', - 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', - 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', - 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', - 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_MODE', - 'ENUM_DP_DPHY_SYM32_NUM_LANES', 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE', - 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS', - 'ENUM_DP_DPHY_SYM32_STATUS', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', - 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', - 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', - 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', - 'ENUM_DP_SYM32_ENC_CRC_VALID', - 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', - 'ENUM_DP_SYM32_ENC_ENABLE', - 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', - 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', - 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', - 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', - 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', - 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', - 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', - 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_NUM_SIMD_PER_CU', - 'EVENT_STATE_CHANGE', 'EXOKAY', 'EXPANSION_MODE', - 'EXPANSION_MODE_CONSERVATIVE', 'EXPANSION_MODE_OPTIMAL', - 'EXPANSION_MODE_ZERO', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', - 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL', - 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FC_EYE_SELECTION_ENUM', - 'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE', - 'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM', - 'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF', - 'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD', - 'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT', - 'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13', - 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE', - 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3', - 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7', - 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', - 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', - 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', - 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', - 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', - 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', - 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 'FMT_CLAMP_CNTL_COLOR_FORMAT', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', - 'FMT_CONTROL_PIXEL_ENCODING', - 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', - 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 'FMT_CONTROL_SUBSAMPLING_MODE', - 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', - 'FMT_CONTROL_SUBSAMPLING_ORDER', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', - 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', - 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', - 'FMT_FRAME_RANDOM_ENABLE_CONTROL', - 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', - 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', - 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', - 'FMT_RGB_RANDOM_ENABLE_CONTROL', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', - 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', - 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', - 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', - 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', - 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', - 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', - 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', - 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', - 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', - 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', - 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', - 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', - 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', - 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', - 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', - 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', - 'ForceControl', 'GATCL1RequestType', 'GATCL1_TYPE_BYPASS', - 'GATCL1_TYPE_NORMAL', 'GATCL1_TYPE_SHOOTDOWN', 'GCRPerfSel', - 'GCR_PERF_SEL_ALL_REQ', - 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', - 'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', - 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 'GCR_PERF_SEL_CPC_TCP_REQ', 'GCR_PERF_SEL_CPF_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', - 'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', - 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 'GCR_PERF_SEL_CPF_TCP_REQ', 'GCR_PERF_SEL_CPG_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', - 'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', - 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 'GCR_PERF_SEL_CPG_TCP_REQ', 'GCR_PERF_SEL_NONE', - 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', - 'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', - 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 'GCR_PERF_SEL_PIO_TCP_REQ', - 'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT', - 'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING', - 'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH', - 'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH', - 'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH', - 'GCR_PERF_SEL_PMM_ALOG_INTERRUPT', - 'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND', - 'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ', - 'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP', - 'GCR_PERF_SEL_PMM_NUM_INTERRUPT', 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ', - 'GCR_PERF_SEL_PMM_RLC_CGCG_RESP', - 'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS', - 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', - 'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', - 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 'GCR_PERF_SEL_PM_TCP_REQ', 'GCR_PERF_SEL_RLC_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', - 'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', - 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 'GCR_PERF_SEL_RLC_TCP_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', - 'GCR_PERF_SEL_VIRT_REQ', 'GCUTCL2_PERF_SEL', - 'GCUTCL2_PERF_SEL_EVENT_0', 'GCUTCL2_PERF_SEL_EVENT_1', - 'GCUTCL2_PERF_SEL_EVENT_10', 'GCUTCL2_PERF_SEL_EVENT_11', - 'GCUTCL2_PERF_SEL_EVENT_12', 'GCUTCL2_PERF_SEL_EVENT_13', - 'GCUTCL2_PERF_SEL_EVENT_14', 'GCUTCL2_PERF_SEL_EVENT_15', - 'GCUTCL2_PERF_SEL_EVENT_16', 'GCUTCL2_PERF_SEL_EVENT_17', - 'GCUTCL2_PERF_SEL_EVENT_18', 'GCUTCL2_PERF_SEL_EVENT_19', - 'GCUTCL2_PERF_SEL_EVENT_2', 'GCUTCL2_PERF_SEL_EVENT_20', - 'GCUTCL2_PERF_SEL_EVENT_21', 'GCUTCL2_PERF_SEL_EVENT_22', - 'GCUTCL2_PERF_SEL_EVENT_23', 'GCUTCL2_PERF_SEL_EVENT_24', - 'GCUTCL2_PERF_SEL_EVENT_25', 'GCUTCL2_PERF_SEL_EVENT_26', - 'GCUTCL2_PERF_SEL_EVENT_27', 'GCUTCL2_PERF_SEL_EVENT_28', - 'GCUTCL2_PERF_SEL_EVENT_29', 'GCUTCL2_PERF_SEL_EVENT_3', - 'GCUTCL2_PERF_SEL_EVENT_30', 'GCUTCL2_PERF_SEL_EVENT_31', - 'GCUTCL2_PERF_SEL_EVENT_32', 'GCUTCL2_PERF_SEL_EVENT_33', - 'GCUTCL2_PERF_SEL_EVENT_34', 'GCUTCL2_PERF_SEL_EVENT_35', - 'GCUTCL2_PERF_SEL_EVENT_36', 'GCUTCL2_PERF_SEL_EVENT_4', - 'GCUTCL2_PERF_SEL_EVENT_5', 'GCUTCL2_PERF_SEL_EVENT_6', - 'GCUTCL2_PERF_SEL_EVENT_7', 'GCUTCL2_PERF_SEL_EVENT_8', - 'GCUTCL2_PERF_SEL_EVENT_9', 'GCVML2_PERF_SEL', - 'GCVML2_PERF_SEL_EVENT_0', 'GCVML2_PERF_SEL_EVENT_1', - 'GCVML2_PERF_SEL_EVENT_10', 'GCVML2_PERF_SEL_EVENT_11', - 'GCVML2_PERF_SEL_EVENT_12', 'GCVML2_PERF_SEL_EVENT_13', - 'GCVML2_PERF_SEL_EVENT_14', 'GCVML2_PERF_SEL_EVENT_15', - 'GCVML2_PERF_SEL_EVENT_16', 'GCVML2_PERF_SEL_EVENT_17', - 'GCVML2_PERF_SEL_EVENT_18', 'GCVML2_PERF_SEL_EVENT_19', - 'GCVML2_PERF_SEL_EVENT_2', 'GCVML2_PERF_SEL_EVENT_20', - 'GCVML2_PERF_SEL_EVENT_21', 'GCVML2_PERF_SEL_EVENT_22', - 'GCVML2_PERF_SEL_EVENT_23', 'GCVML2_PERF_SEL_EVENT_24', - 'GCVML2_PERF_SEL_EVENT_25', 'GCVML2_PERF_SEL_EVENT_26', - 'GCVML2_PERF_SEL_EVENT_27', 'GCVML2_PERF_SEL_EVENT_28', - 'GCVML2_PERF_SEL_EVENT_29', 'GCVML2_PERF_SEL_EVENT_3', - 'GCVML2_PERF_SEL_EVENT_30', 'GCVML2_PERF_SEL_EVENT_31', - 'GCVML2_PERF_SEL_EVENT_32', 'GCVML2_PERF_SEL_EVENT_33', - 'GCVML2_PERF_SEL_EVENT_34', 'GCVML2_PERF_SEL_EVENT_35', - 'GCVML2_PERF_SEL_EVENT_36', 'GCVML2_PERF_SEL_EVENT_37', - 'GCVML2_PERF_SEL_EVENT_38', 'GCVML2_PERF_SEL_EVENT_39', - 'GCVML2_PERF_SEL_EVENT_4', 'GCVML2_PERF_SEL_EVENT_40', - 'GCVML2_PERF_SEL_EVENT_41', 'GCVML2_PERF_SEL_EVENT_42', - 'GCVML2_PERF_SEL_EVENT_43', 'GCVML2_PERF_SEL_EVENT_44', - 'GCVML2_PERF_SEL_EVENT_45', 'GCVML2_PERF_SEL_EVENT_46', - 'GCVML2_PERF_SEL_EVENT_47', 'GCVML2_PERF_SEL_EVENT_48', - 'GCVML2_PERF_SEL_EVENT_49', 'GCVML2_PERF_SEL_EVENT_5', - 'GCVML2_PERF_SEL_EVENT_50', 'GCVML2_PERF_SEL_EVENT_51', - 'GCVML2_PERF_SEL_EVENT_52', 'GCVML2_PERF_SEL_EVENT_53', - 'GCVML2_PERF_SEL_EVENT_54', 'GCVML2_PERF_SEL_EVENT_55', - 'GCVML2_PERF_SEL_EVENT_56', 'GCVML2_PERF_SEL_EVENT_57', - 'GCVML2_PERF_SEL_EVENT_58', 'GCVML2_PERF_SEL_EVENT_59', - 'GCVML2_PERF_SEL_EVENT_6', 'GCVML2_PERF_SEL_EVENT_60', - 'GCVML2_PERF_SEL_EVENT_61', 'GCVML2_PERF_SEL_EVENT_62', - 'GCVML2_PERF_SEL_EVENT_63', 'GCVML2_PERF_SEL_EVENT_64', - 'GCVML2_PERF_SEL_EVENT_65', 'GCVML2_PERF_SEL_EVENT_66', - 'GCVML2_PERF_SEL_EVENT_67', 'GCVML2_PERF_SEL_EVENT_68', - 'GCVML2_PERF_SEL_EVENT_69', 'GCVML2_PERF_SEL_EVENT_7', - 'GCVML2_PERF_SEL_EVENT_70', 'GCVML2_PERF_SEL_EVENT_71', - 'GCVML2_PERF_SEL_EVENT_72', 'GCVML2_PERF_SEL_EVENT_73', - 'GCVML2_PERF_SEL_EVENT_74', 'GCVML2_PERF_SEL_EVENT_75', - 'GCVML2_PERF_SEL_EVENT_76', 'GCVML2_PERF_SEL_EVENT_77', - 'GCVML2_PERF_SEL_EVENT_78', 'GCVML2_PERF_SEL_EVENT_79', - 'GCVML2_PERF_SEL_EVENT_8', 'GCVML2_PERF_SEL_EVENT_80', - 'GCVML2_PERF_SEL_EVENT_81', 'GCVML2_PERF_SEL_EVENT_82', - 'GCVML2_PERF_SEL_EVENT_83', 'GCVML2_PERF_SEL_EVENT_84', - 'GCVML2_PERF_SEL_EVENT_85', 'GCVML2_PERF_SEL_EVENT_86', - 'GCVML2_PERF_SEL_EVENT_87', 'GCVML2_PERF_SEL_EVENT_88', - 'GCVML2_PERF_SEL_EVENT_89', 'GCVML2_PERF_SEL_EVENT_9', - 'GCVML2_PERF_SEL_EVENT_90', 'GCVML2_SPM_PERF_SEL', - 'GCVML2_SPM_PERF_SEL_EVENT_0', 'GCVML2_SPM_PERF_SEL_EVENT_1', - 'GCVML2_SPM_PERF_SEL_EVENT_10', 'GCVML2_SPM_PERF_SEL_EVENT_11', - 'GCVML2_SPM_PERF_SEL_EVENT_12', 'GCVML2_SPM_PERF_SEL_EVENT_13', - 'GCVML2_SPM_PERF_SEL_EVENT_14', 'GCVML2_SPM_PERF_SEL_EVENT_15', - 'GCVML2_SPM_PERF_SEL_EVENT_16', 'GCVML2_SPM_PERF_SEL_EVENT_17', - 'GCVML2_SPM_PERF_SEL_EVENT_18', 'GCVML2_SPM_PERF_SEL_EVENT_19', - 'GCVML2_SPM_PERF_SEL_EVENT_2', 'GCVML2_SPM_PERF_SEL_EVENT_20', - 'GCVML2_SPM_PERF_SEL_EVENT_21', 'GCVML2_SPM_PERF_SEL_EVENT_22', - 'GCVML2_SPM_PERF_SEL_EVENT_23', 'GCVML2_SPM_PERF_SEL_EVENT_24', - 'GCVML2_SPM_PERF_SEL_EVENT_25', 'GCVML2_SPM_PERF_SEL_EVENT_26', - 'GCVML2_SPM_PERF_SEL_EVENT_27', 'GCVML2_SPM_PERF_SEL_EVENT_28', - 'GCVML2_SPM_PERF_SEL_EVENT_29', 'GCVML2_SPM_PERF_SEL_EVENT_3', - 'GCVML2_SPM_PERF_SEL_EVENT_30', 'GCVML2_SPM_PERF_SEL_EVENT_31', - 'GCVML2_SPM_PERF_SEL_EVENT_32', 'GCVML2_SPM_PERF_SEL_EVENT_33', - 'GCVML2_SPM_PERF_SEL_EVENT_34', 'GCVML2_SPM_PERF_SEL_EVENT_35', - 'GCVML2_SPM_PERF_SEL_EVENT_36', 'GCVML2_SPM_PERF_SEL_EVENT_37', - 'GCVML2_SPM_PERF_SEL_EVENT_38', 'GCVML2_SPM_PERF_SEL_EVENT_39', - 'GCVML2_SPM_PERF_SEL_EVENT_4', 'GCVML2_SPM_PERF_SEL_EVENT_40', - 'GCVML2_SPM_PERF_SEL_EVENT_41', 'GCVML2_SPM_PERF_SEL_EVENT_42', - 'GCVML2_SPM_PERF_SEL_EVENT_43', 'GCVML2_SPM_PERF_SEL_EVENT_44', - 'GCVML2_SPM_PERF_SEL_EVENT_45', 'GCVML2_SPM_PERF_SEL_EVENT_46', - 'GCVML2_SPM_PERF_SEL_EVENT_47', 'GCVML2_SPM_PERF_SEL_EVENT_48', - 'GCVML2_SPM_PERF_SEL_EVENT_49', 'GCVML2_SPM_PERF_SEL_EVENT_5', - 'GCVML2_SPM_PERF_SEL_EVENT_50', 'GCVML2_SPM_PERF_SEL_EVENT_51', - 'GCVML2_SPM_PERF_SEL_EVENT_52', 'GCVML2_SPM_PERF_SEL_EVENT_53', - 'GCVML2_SPM_PERF_SEL_EVENT_54', 'GCVML2_SPM_PERF_SEL_EVENT_55', - 'GCVML2_SPM_PERF_SEL_EVENT_56', 'GCVML2_SPM_PERF_SEL_EVENT_57', - 'GCVML2_SPM_PERF_SEL_EVENT_58', 'GCVML2_SPM_PERF_SEL_EVENT_59', - 'GCVML2_SPM_PERF_SEL_EVENT_6', 'GCVML2_SPM_PERF_SEL_EVENT_60', - 'GCVML2_SPM_PERF_SEL_EVENT_61', 'GCVML2_SPM_PERF_SEL_EVENT_62', - 'GCVML2_SPM_PERF_SEL_EVENT_63', 'GCVML2_SPM_PERF_SEL_EVENT_64', - 'GCVML2_SPM_PERF_SEL_EVENT_65', 'GCVML2_SPM_PERF_SEL_EVENT_66', - 'GCVML2_SPM_PERF_SEL_EVENT_67', 'GCVML2_SPM_PERF_SEL_EVENT_68', - 'GCVML2_SPM_PERF_SEL_EVENT_69', 'GCVML2_SPM_PERF_SEL_EVENT_7', - 'GCVML2_SPM_PERF_SEL_EVENT_70', 'GCVML2_SPM_PERF_SEL_EVENT_71', - 'GCVML2_SPM_PERF_SEL_EVENT_72', 'GCVML2_SPM_PERF_SEL_EVENT_73', - 'GCVML2_SPM_PERF_SEL_EVENT_74', 'GCVML2_SPM_PERF_SEL_EVENT_75', - 'GCVML2_SPM_PERF_SEL_EVENT_76', 'GCVML2_SPM_PERF_SEL_EVENT_77', - 'GCVML2_SPM_PERF_SEL_EVENT_78', 'GCVML2_SPM_PERF_SEL_EVENT_79', - 'GCVML2_SPM_PERF_SEL_EVENT_8', 'GCVML2_SPM_PERF_SEL_EVENT_80', - 'GCVML2_SPM_PERF_SEL_EVENT_81', 'GCVML2_SPM_PERF_SEL_EVENT_82', - 'GCVML2_SPM_PERF_SEL_EVENT_83', 'GCVML2_SPM_PERF_SEL_EVENT_84', - 'GCVML2_SPM_PERF_SEL_EVENT_85', 'GCVML2_SPM_PERF_SEL_EVENT_86', - 'GCVML2_SPM_PERF_SEL_EVENT_87', 'GCVML2_SPM_PERF_SEL_EVENT_88', - 'GCVML2_SPM_PERF_SEL_EVENT_89', 'GCVML2_SPM_PERF_SEL_EVENT_9', - 'GCVML2_SPM_PERF_SEL_EVENT_90', 'GC_EA_CPWD_PERFCOUNT_SEL', - 'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT', - 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED', - 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT', - 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', - 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING', - 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT', - 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD', - 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT', - 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', - 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD', - 'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING', - 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ', - 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP', - 'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_CPWD_PERF_SEL_PRB_REQ', - 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD', - 'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', - 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD', - 'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_RRET_VLD', 'GC_EA_CPWD_PERF_SEL_SARB_BUSY', - 'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC', - 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', - 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC', - 'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND', - 'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_SARB_IDLE', - 'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC', - 'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC', - 'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_SARB_STALLED', - 'GC_EA_CPWD_PERF_SEL_SARB_STARVING', - 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD', - 'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD', - 'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0', - 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1', - 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0', - 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1', - 'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP', - 'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ', - 'GC_EA_CPWD_PERF_SEL_WRET_VLD', 'GC_EA_SE_PERFCOUNT_SEL', - 'GC_EA_SE_PERF_SEL_ALWAYS_COUNT', - 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED', - 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT', - 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', - 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING', - 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT', - 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD', - 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT', - 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', - 'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD', - 'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING', - 'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ', - 'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP', - 'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_SE_PERF_SEL_PRB_REQ', - 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD', - 'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', - 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD', - 'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_RRET_VLD', - 'GC_EA_SE_PERF_SEL_SARB_BUSY', - 'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC', - 'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', - 'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC', - 'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND', - 'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_SARB_IDLE', - 'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC', - 'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC', - 'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_SARB_STALLED', - 'GC_EA_SE_PERF_SEL_SARB_STARVING', - 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD', - 'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', - 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD', - 'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ', - 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0', - 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1', - 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0', - 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1', - 'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP', - 'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_WRET_VLD', - 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', - 'GE2_SE_PERFCOUNT_SELECT', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', - 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', - 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', - 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', - 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', - 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', - 'GL0V_CACHE_POLICY_MISS_INVAL', 'GL0V_CACHE_POLICY_MISS_LRU', - 'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', - 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', - 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', - 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', - 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', - 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', - 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', - 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', - 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', - 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', - 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', - 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', - 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', - 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', - 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', - 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', - 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', - 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', - 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_NOP_ACK', - 'GL1C_PERF_SEL_REQ_NOP_RTN0', 'GL1C_PERF_SEL_REQ_READ', - 'GL1C_PERF_SEL_REQ_READ_128B', 'GL1C_PERF_SEL_REQ_READ_32B', - 'GL1C_PERF_SEL_REQ_READ_64B', 'GL1C_PERF_SEL_REQ_WRITE', - 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', - 'GL1C_PERF_SEL_STALL_BUFFER_FULL', 'GL1C_PERF_SEL_STALL_GL2_GL1', - 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', - 'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST', - 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 'GL1C_PERF_SEL_UTCL0_REQUEST', - 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', 'GL1XA_PERF_SEL', - 'GL1XA_PERF_SEL_ARB_REQUESTS', - 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0', - 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1', - 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2', - 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3', 'GL1XA_PERF_SEL_BUSY', - 'GL1XA_PERF_SEL_CYCLE', 'GL1XA_PERF_SEL_REQUEST_GL1XC0', - 'GL1XA_PERF_SEL_REQUEST_GL1XC1', 'GL1XA_PERF_SEL_REQUEST_GL1XC2', - 'GL1XA_PERF_SEL_REQUEST_GL1XC3', - 'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1XA_PERF_SEL_STALL_GL1XC0', 'GL1XA_PERF_SEL_STALL_GL1XC1', - 'GL1XA_PERF_SEL_STALL_GL1XC2', 'GL1XA_PERF_SEL_STALL_GL1XC3', - 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0', - 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1', - 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2', - 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3', - 'GL1XA_PERF_SEL_WDS_32B_GL1XC0', 'GL1XA_PERF_SEL_WDS_32B_GL1XC1', - 'GL1XA_PERF_SEL_WDS_32B_GL1XC2', 'GL1XA_PERF_SEL_WDS_32B_GL1XC3', - 'GL1XC_PERF_SEL', 'GL1XC_PERF_SEL_ARB_RET_LEVEL', - 'GL1XC_PERF_SEL_BUSY', 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 'GL1XC_PERF_SEL_CYCLE', 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY', - 'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1XC_PERF_SEL_REQ', - 'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET', - 'GL1XC_PERF_SEL_REQ_CLIENT0', 'GL1XC_PERF_SEL_REQ_CLIENT1', - 'GL1XC_PERF_SEL_REQ_CLIENT10', 'GL1XC_PERF_SEL_REQ_CLIENT11', - 'GL1XC_PERF_SEL_REQ_CLIENT12', 'GL1XC_PERF_SEL_REQ_CLIENT13', - 'GL1XC_PERF_SEL_REQ_CLIENT14', 'GL1XC_PERF_SEL_REQ_CLIENT15', - 'GL1XC_PERF_SEL_REQ_CLIENT16', 'GL1XC_PERF_SEL_REQ_CLIENT17', - 'GL1XC_PERF_SEL_REQ_CLIENT18', 'GL1XC_PERF_SEL_REQ_CLIENT19', - 'GL1XC_PERF_SEL_REQ_CLIENT2', 'GL1XC_PERF_SEL_REQ_CLIENT20', - 'GL1XC_PERF_SEL_REQ_CLIENT21', 'GL1XC_PERF_SEL_REQ_CLIENT22', - 'GL1XC_PERF_SEL_REQ_CLIENT23', 'GL1XC_PERF_SEL_REQ_CLIENT24', - 'GL1XC_PERF_SEL_REQ_CLIENT25', 'GL1XC_PERF_SEL_REQ_CLIENT26', - 'GL1XC_PERF_SEL_REQ_CLIENT27', 'GL1XC_PERF_SEL_REQ_CLIENT3', - 'GL1XC_PERF_SEL_REQ_CLIENT4', 'GL1XC_PERF_SEL_REQ_CLIENT5', - 'GL1XC_PERF_SEL_REQ_CLIENT6', 'GL1XC_PERF_SEL_REQ_CLIENT7', - 'GL1XC_PERF_SEL_REQ_CLIENT8', 'GL1XC_PERF_SEL_REQ_CLIENT9', - 'GL1XC_PERF_SEL_REQ_NOP_ACK', 'GL1XC_PERF_SEL_REQ_NOP_RTN0', - 'GL1XC_PERF_SEL_REQ_READ', 'GL1XC_PERF_SEL_REQ_READ_128B', - 'GL1XC_PERF_SEL_REQ_READ_32B', 'GL1XC_PERF_SEL_REQ_READ_64B', - 'GL1XC_PERF_SEL_REQ_WRITE', 'GL1XC_PERF_SEL_REQ_WRITE_32B', - 'GL1XC_PERF_SEL_REQ_WRITE_64B', - 'GL1XC_PERF_SEL_STALL_BUFFER_FULL', - 'GL1XC_PERF_SEL_STALL_GL2_GL1', 'GL1XC_PERF_SEL_STALL_VM', - 'GL1XC_PERF_SEL_STARVE', 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST', - 'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL', - 'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS', - 'GL1XC_PERF_SEL_UTCL0_REQUEST', - 'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 'GL1_CACHE_POLICIES', 'GL1_CACHE_POLICY_HIT_EVICT', - 'GL1_CACHE_POLICY_HIT_LRU', 'GL1_CACHE_POLICY_MISS_EVICT', - 'GL1_CACHE_POLICY_MISS_LRU', 'GL1_CACHE_STORE_POLICIES', - 'GL1_CACHE_STORE_POLICY_BYPASS', 'GL2A_PERF_SEL', - 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', 'GL2A_PERF_SEL_NONE', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', - 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', - 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', - 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', - 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', - 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', - 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', - 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', - 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', - 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', - 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', - 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', - 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', - 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', - 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', - 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', - 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', - 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', - 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', - 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', - 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', - 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', - 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', - 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', - 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', - 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', - 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 'GL2C_PERF_SEL_EA_RDRET_NACK', - 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', 'GL2C_PERF_SEL_EA_WRREQ_64B', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM', 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', - 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', - 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', - 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', - 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', - 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_RANGE', - 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', - 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', - 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', 'GL2C_PERF_SEL_IB_REQ', - 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', - 'GL2C_PERF_SEL_IO_READ', 'GL2C_PERF_SEL_IO_WRITE', - 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', 'GL2C_PERF_SEL_LRU_REQ', - 'GL2C_PERF_SEL_MC_RDREQ', 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', - 'GL2C_PERF_SEL_MC_WRREQ', 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', - 'GL2C_PERF_SEL_MC_WRREQ_STALL', 'GL2C_PERF_SEL_METADATA_READ_REQ', - 'GL2C_PERF_SEL_MISS', 'GL2C_PERF_SEL_NOA_REQ', - 'GL2C_PERF_SEL_NONE', 'GL2C_PERF_SEL_NOP_ACK', - 'GL2C_PERF_SEL_NOP_RTN0', 'GL2C_PERF_SEL_NORMAL_EVICT', - 'GL2C_PERF_SEL_NORMAL_WRITEBACK', 'GL2C_PERF_SEL_ONION_READ', - 'GL2C_PERF_SEL_ONION_WRITE', 'GL2C_PERF_SEL_PARTIAL_32B_HIT', - 'GL2C_PERF_SEL_PARTIAL_64B_HIT', 'GL2C_PERF_SEL_PARTIAL_96B_HIT', - 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', - 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', - 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', - 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', - 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', - 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', - 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', - 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', - 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', - 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', - 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', - 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', - 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', - 'GL2_CACHE_POLICY_STREAM', 'GL2_NACKS', 'GL2_NACK_DATA_ERROR', - 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', - 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', - 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', - 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', - 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', - 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', - 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_COND_SUB_RTN_32', 'GL2_OP_ATOMIC_DEC_32', - 'GL2_OP_ATOMIC_DEC_64', 'GL2_OP_ATOMIC_DEC_RTN_32', - 'GL2_OP_ATOMIC_DEC_RTN_64', 'GL2_OP_ATOMIC_FADD_32', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FADD_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_32', - 'GL2_OP_ATOMIC_FCMPSWAP_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', - 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', - 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', - 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', - 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', - 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', - 'GL2_OP_ATOMIC_PK_ADD_BF16', 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN', - 'GL2_OP_ATOMIC_PK_ADD_FP16', 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN', - 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', - 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', - 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', - 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', - 'GL2_OP_ATOMIC_STORE_COND_RTN', 'GL2_OP_ATOMIC_SUB_32', - 'GL2_OP_ATOMIC_SUB_64', 'GL2_OP_ATOMIC_SUB_RTN_32', - 'GL2_OP_ATOMIC_SUB_RTN_64', 'GL2_OP_ATOMIC_SWAP_32', - 'GL2_OP_ATOMIC_SWAP_64', 'GL2_OP_ATOMIC_SWAP_RTN_32', - 'GL2_OP_ATOMIC_SWAP_RTN_64', 'GL2_OP_ATOMIC_UMAX_32', - 'GL2_OP_ATOMIC_UMAX_64', 'GL2_OP_ATOMIC_UMAX_8', - 'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64', - 'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64', - 'GL2_OP_ATOMIC_UMIN_8', 'GL2_OP_ATOMIC_UMIN_RTN_32', - 'GL2_OP_ATOMIC_UMIN_RTN_64', 'GL2_OP_ATOMIC_XOR_32', - 'GL2_OP_ATOMIC_XOR_64', 'GL2_OP_ATOMIC_XOR_RTN_32', - 'GL2_OP_ATOMIC_XOR_RTN_64', - 'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS', 'GL2_OP_GL1_INV', - 'GL2_OP_GL2_INV', 'GL2_OP_GL2_WB', 'GL2_OP_GL2_WBINV', - 'GL2_OP_LOAD_RESERVE', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', - 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', - 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', - 'GL2_OP_READ', 'GL2_OP_READ_COMPRESSION_KEY', - 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_UTC_PROBE', - 'GL2_OP_WRITE', 'GL2_OP_WRITE_ZERO_SIZE', 'GLCompressionMode', - 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', - 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', - 'GLOBAL_STATUS_FLUSH_STATUS', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', - 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', - 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', - 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', - 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', - 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', - 'GRBMH_PERF_SEL', 'GRBMH_PERF_SEL_BCI_BUSY', - 'GRBMH_PERF_SEL_CB_BUSY', 'GRBMH_PERF_SEL_CB_CLEAN', - 'GRBMH_PERF_SEL_COUNT', 'GRBMH_PERF_SEL_DB_BUSY', - 'GRBMH_PERF_SEL_DB_CLEAN', 'GRBMH_PERF_SEL_EA_BUSY', - 'GRBMH_PERF_SEL_EA_LINK_BUSY', 'GRBMH_PERF_SEL_GE_BUSY', - 'GRBMH_PERF_SEL_GL1A_BUSY', 'GRBMH_PERF_SEL_GL1CC_BUSY', - 'GRBMH_PERF_SEL_GL1XCC_BUSY', 'GRBMH_PERF_SEL_GL2A_BUSY', - 'GRBMH_PERF_SEL_GL2C_BUSY', 'GRBMH_PERF_SEL_PA_BUSY', - 'GRBMH_PERF_SEL_PC_BUSY', 'GRBMH_PERF_SEL_RLC_BUSY', - 'GRBMH_PERF_SEL_SC_BUSY', 'GRBMH_PERF_SEL_SC_CLEAN', - 'GRBMH_PERF_SEL_SPI_BUSY', 'GRBMH_PERF_SEL_SX_BUSY', - 'GRBMH_PERF_SEL_TA_BUSY', 'GRBMH_PERF_SEL_TCP_BUSY', - 'GRBMH_PERF_SEL_USER_DEFINED', 'GRBMH_PERF_SEL_UTCL1_BUSY', - 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', - 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', - 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPC_BUSY', - 'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY', - 'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY', - 'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY', - 'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY', - 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1XCC_BUSY', - 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', - 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', - 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PMM_BUSY', - 'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_SC_BUSY', - 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', - 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', - 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', - 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', - 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', - 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', - 'GS_STAGE_ON', 'HDMICHARCLK_SRC_SEL', - 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', 'HDMICHARCLK_SRC_SEL_UNIPHYA', - 'HDMICHARCLK_SRC_SEL_UNIPHYB', 'HDMICHARCLK_SRC_SEL_UNIPHYC', - 'HDMICHARCLK_SRC_SEL_UNIPHYD', 'HDMISTREAMCLK_SRC_SEL', - 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', 'HDMI_ACP_SEND', - 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', - 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', - 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', - 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', - 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', - 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', - 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', - 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', - 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', - 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', - 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', - 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', - 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', - 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', - 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', - 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', - 'HDMI_AUDIO_INFO_SEND', - 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', - 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', - 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', - 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', - 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', - 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', - 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', - 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', - 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', - 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', - 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', - 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', - 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE', - 'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND', - 'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', - 'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE', - 'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', - 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', - 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', - 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', - 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', - 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', - 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', - 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', - 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', - 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', - 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', - 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', - 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16', - 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', - 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', - 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', - 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', - 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', - 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', - 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', - 'HPO_TOP_CLOCK_GATING_EN', - 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', - 'HPO_TOP_REGISTER_GATED_DISPCLK', - 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', - 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', - 'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF', - 'HS_STAGE_ON', 'HUBP_3DLUT_ADDRESSING_MODE', - 'HUBP_3DLUT_SIMPLE_LINEAR', 'HUBP_3DLUT_SW_LINEAR', - 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', 'HUBP_BLANK_SW_DEASSERT', - 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', 'HUBP_IN_VBLANK', - 'HUBP_MEASURE_WIN_MODE_DCFCLK', 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', - 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', - 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', - 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', - 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', - 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', - 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', - 'IHC_INTERRUPT_LINE_STATUS', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', - 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', - 'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', - 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', - 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', - 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', - 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', - 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', - 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', - 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', - 'IQ_SCH_WAVE_MSG', 'ISHARP_FMT_MODE_0', 'ISHARP_FMT_MODE_1', - 'ISHARP_FMT_MODE_ENUM', 'ISHARP_LBA_MODE_0', 'ISHARP_LBA_MODE_1', - 'ISHARP_LBA_MODE_ENUM', 'ISHARP_NOISEDET_MODE_0', - 'ISHARP_NOISEDET_MODE_1', 'ISHARP_NOISEDET_MODE_2', - 'ISHARP_NOISEDET_MODE_3', 'ISHARP_NOISEDET_MODE_ENUM', - 'JITTER_REMOVE_DISABLE', 'LATE_Z', 'LB_ALPHA_DISABLE', - 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', 'LB_INTERLEAVE_DISABLE', - 'LB_INTERLEAVE_EN', 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', - 'LB_MEMORY_CONFIG_0', 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', - 'LB_MEMORY_CONFIG_3', 'LEGACY_PIPE_INTERLEAVE', - 'LEGACY_PIPE_INTERLEAVE_256B', 'LEGACY_PIPE_INTERLEAVE_512B', - 'LINESTRIP', 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', - 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', - 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', - 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', - 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', - 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', - 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', - 'LSDMA_PERF_SEL_CTX_CHANGE', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', - 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', - 'LSDMA_PERF_SEL_DUMMY_0', 'LSDMA_PERF_SEL_DUMMY_1', - 'LSDMA_PERF_SEL_EX_IDLE', - 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', - 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', - 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 'LSDMA_PERF_SEL_INT_REQ_STALL', - 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', - 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', - 'LSDMA_PERF_SEL_MC_WR_IDLE', - 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', - 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', - 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', - 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', - 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', - 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', - 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', - 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', - 'LUMA_KEYER_ENABLE', 'LUMA_KEY_DIS', 'LUMA_KEY_EN', - 'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', - 'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', - 'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', - 'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', - 'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT', - 'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT', - 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', - 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', - 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', - 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', - 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 'MASTER_UPDATE_LOCK_SEL_RESERVED5', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 'MATRIX_MODE_0', 'MATRIX_MODE_1', 'MATRIX_MODE_ENUM', - 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', - 'MEM_ARB_MODE_WEIGHT', 'MEM_POWER_DIS_MODE_DISABLE', - 'MEM_POWER_DIS_MODE_ENABLE', 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', - 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', - 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', - 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', - 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', - 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', - 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', - 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', - 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', - 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', - 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', - 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', - 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', - 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', - 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', - 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', - 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', - 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', - 'MIN_META_CHUNK_SIZE_64B', 'MONO_10LSB', 'MONO_10MSB', - 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', - 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', - 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', - 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', - 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', - 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', - 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', - 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', - 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', - 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', - 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', - 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', - 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', - 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', - 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', - 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12', - 'MPCC_MCM_GAMUT_REMAP_MODE_0', 'MPCC_MCM_GAMUT_REMAP_MODE_1', - 'MPCC_MCM_GAMUT_REMAP_MODE_2', 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM', - 'MPCC_MCM_GAMUT_REMAP_MODE_RSV', 'MPCC_MCM_LUT_2_MODE_BYPASS', - 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', - 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', - 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', - 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', - 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', - 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', - 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', - 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', - 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', - 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', - 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', - 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', - 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', - 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', - 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', - 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', - 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', - 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', - 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', - 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', - 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', - 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', - 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', - 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', - 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', - 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', - 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', - 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', - 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', - 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', - 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', - 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', - 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', - 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 'MPC_CFG_3DLUT_FL_FORMAT', 'MPC_CFG_3DLUT_FL_FORMAT_0', - 'MPC_CFG_3DLUT_FL_FORMAT_1', 'MPC_CFG_3DLUT_FL_FORMAT_2', - 'MPC_CFG_3DLUT_FL_MODE', 'MPC_CFG_3DLUT_FL_MODE_0', - 'MPC_CFG_3DLUT_FL_MODE_1', 'MPC_CFG_3DLUT_FL_MODE_2', - 'MPC_CFG_3DLUT_FL_MODE_3', 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', - 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', - 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', - 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', - 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', - 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', - 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', - 'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13', - 'MPC_OCSC_COEF_FORMAT_S3_12', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', - 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', - 'MPC_OUT_RATE_CONTROL_DISABLE_SET', - 'MPC_OUT_RATE_CONTROL_SET_DISABLE', - 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', - 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', - 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', - 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', - 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', - 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', - 'MemArbMode', 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED', - 'NOT_SENT', 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', - 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', - 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS', - 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', - 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', - 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', - 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', - 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', - 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', - 'OPPBUF_DISPLAY_SEGMENTATION', - 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', - 'OPP_PIPE_CLOCK_DISABLE', 'OPP_PIPE_CLOCK_ENABLE', - 'OPP_PIPE_CLOCK_ENABLE_CONTROL', 'OPP_PIPE_CRC_CONT_EN', - 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', 'OPP_PIPE_CRC_ENABLE', - 'OPP_PIPE_CRC_INTERLACE_EN', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 'OPP_PIPE_CRC_INTERLACE_MODE', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', - 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', - 'OPP_PIPE_CRC_PIXEL_SELECT', - 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', - 'OPP_PIPE_CRC_STEREO_MODE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', - 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', - 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', - 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', - 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', - 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', - 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', - 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', - 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', - 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', - 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', - 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', - 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', - 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', - 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', - 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', - 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', - 'OTG_DIG_UPDATE_VCOUNT_MODE', 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE', - 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0', - 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', - 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', - 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', - 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', - 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', - 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', - 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', - 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', - 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', - 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', - 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', - 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', - 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', - 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', - 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', - 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', - 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', - 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', - 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', - 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', - 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', - 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', - 'OTG_TRIGA_FREQUENCY_SELECT_3', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', - 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', - 'OTG_TRIGB_FREQUENCY_SELECT_3', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', - 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', - 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', - 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', - 'OTG_V_SYNC_MODE_HSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', - 'OUTPUT_LINE', 'OUTPUT_POINT', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', - 'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', - 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PC_PERFCNT_SEL', - 'PC_PERF_GE_GSDONE', 'PC_PERF_GL1_RTN_CNT_GT512', - 'PC_PERF_GL1_RTN_CNT_GT768', 'PC_PERF_GL1_RTN_CNT_GTE1', - 'PC_PERF_GRBM_BUSY', 'PC_PERF_LWC0_PC_MEM_READ_STALL', - 'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING', - 'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING', - 'PC_PERF_LWC0_PROBE_ORDER_STALL', - 'PC_PERF_LWC1_PC_MEM_READ_STALL', - 'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING', - 'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING', - 'PC_PERF_LWC1_PROBE_ORDER_STALL', - 'PC_PERF_MW_CACHE_CNTL_FULL_STALL', 'PC_PERF_MW_CACHE_HIT', - 'PC_PERF_MW_CACHE_MISS', 'PC_PERF_MW_CACHE_REUSE', - 'PC_PERF_MW_DEALLOC_HIT', 'PC_PERF_MW_DLINE_ALLOC', - 'PC_PERF_MW_DLINE_DEALLOC', 'PC_PERF_MW_GL1H_NUM_REQS', - 'PC_PERF_MW_GL1H_REQ_FREEZE', 'PC_PERF_MW_PHY_DLINE_FULL_STALL', - 'PC_PERF_MW_PROBE_CNT_FREEZE', 'PC_PERF_MW_RTN_ADDR_FREEZE', - 'PC_PERF_MW_STAMP_LIMIT_STALL', 'PC_PERF_MW_TAGLINE_ALLOC', - 'PC_PERF_MW_TAGLINE_DEALLOC', 'PC_PERF_NUM_PSWAVE', - 'PC_PERF_PC_LDS_CNTL_VALID0', 'PC_PERF_PC_LDS_CNTL_VALID1', - 'PC_PERF_PC_LDS_VERTEX_REUSE0', 'PC_PERF_PC_LDS_VERTEX_REUSE1', - 'PC_PERF_PC_MEM_BANK_CONF0', 'PC_PERF_PC_MEM_BANK_CONF1', - 'PC_PERF_PC_SPI_PROBE_FREEZE', - 'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT', 'PC_PERF_PKR0_FPOSG_EQ1', - 'PC_PERF_PKR0_FPOSG_GT1', 'PC_PERF_PKR0_FPOSG_GT128', - 'PC_PERF_PKR0_FPOSG_GT16', 'PC_PERF_PKR0_FPOSG_GT64', - 'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE', - 'PC_PERF_PKR0_GSDONE_WHILE_IDLE', 'PC_PERF_PKR0_NUM_PROBES', - 'PC_PERF_PKR0_NUM_WAVES', 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1', - 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1', - 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2', - 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4', - 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8', - 'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1', - 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1', - 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2', - 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4', - 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR0_PRIMS_REUSE', - 'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1', - 'PC_PERF_PKR0_PROBES_PER_WAVE_GT1', - 'PC_PERF_PKR0_PROBES_PER_WAVE_GT2', - 'PC_PERF_PKR0_PROBES_PER_WAVE_GT4', - 'PC_PERF_PKR0_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR1_FPOSG_EQ1', - 'PC_PERF_PKR1_FPOSG_GT1', 'PC_PERF_PKR1_FPOSG_GT128', - 'PC_PERF_PKR1_FPOSG_GT16', 'PC_PERF_PKR1_FPOSG_GT64', - 'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE', - 'PC_PERF_PKR1_GSDONE_WHILE_IDLE', 'PC_PERF_PKR1_NUM_PROBES', - 'PC_PERF_PKR1_NUM_WAVES', 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1', - 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1', - 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2', - 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4', - 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8', - 'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1', - 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1', - 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2', - 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4', - 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR1_PRIMS_REUSE', - 'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1', - 'PC_PERF_PKR1_PROBES_PER_WAVE_GT1', - 'PC_PERF_PKR1_PROBES_PER_WAVE_GT2', - 'PC_PERF_PKR1_PROBES_PER_WAVE_GT4', - 'PC_PERF_PKR1_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR2_FPOSG_EQ1', - 'PC_PERF_PKR2_FPOSG_GT1', 'PC_PERF_PKR2_FPOSG_GT128', - 'PC_PERF_PKR2_FPOSG_GT16', 'PC_PERF_PKR2_FPOSG_GT64', - 'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE', - 'PC_PERF_PKR2_GSDONE_WHILE_IDLE', 'PC_PERF_PKR2_NUM_PROBES', - 'PC_PERF_PKR2_NUM_WAVES', 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1', - 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1', - 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2', - 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4', - 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8', - 'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1', - 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1', - 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2', - 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4', - 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR2_PRIMS_REUSE', - 'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1', - 'PC_PERF_PKR2_PROBES_PER_WAVE_GT1', - 'PC_PERF_PKR2_PROBES_PER_WAVE_GT2', - 'PC_PERF_PKR2_PROBES_PER_WAVE_GT4', - 'PC_PERF_PKR2_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR3_FPOSG_EQ1', - 'PC_PERF_PKR3_FPOSG_GT1', 'PC_PERF_PKR3_FPOSG_GT128', - 'PC_PERF_PKR3_FPOSG_GT16', 'PC_PERF_PKR3_FPOSG_GT64', - 'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE', - 'PC_PERF_PKR3_GSDONE_WHILE_IDLE', 'PC_PERF_PKR3_NUM_PROBES', - 'PC_PERF_PKR3_NUM_WAVES', 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1', - 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1', - 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2', - 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4', - 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8', - 'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1', - 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1', - 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2', - 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4', - 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR3_PRIMS_REUSE', - 'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1', - 'PC_PERF_PKR3_PROBES_PER_WAVE_GT1', - 'PC_PERF_PKR3_PROBES_PER_WAVE_GT2', - 'PC_PERF_PKR3_PROBES_PER_WAVE_GT4', - 'PC_PERF_PKR3_PROBES_PER_WAVE_GT8', 'PC_PERF_SC_FPOSG0', - 'PC_PERF_SC_FPOSG1', 'PC_PERF_SC_FPOSG2', 'PC_PERF_SC_FPOSG3', - 'PC_PERF_SC_FPOSG_WAIT0', 'PC_PERF_SC_FPOSG_WAIT1', - 'PC_PERF_SC_FPOSG_WAIT2', 'PC_PERF_SC_FPOSG_WAIT3', - 'PC_PERF_SC_MW_FREEZE', 'PC_PERF_SC_NUM_PROBES', - 'PC_PERF_SC_NUM_SPLIT_WAVES', 'PC_PERF_SC_NUM_WAVES', - 'PC_PERF_SC_PC_PTR_SEND0', 'PC_PERF_SC_PC_PTR_SEND1', - 'PC_PERF_SC_PC_PTR_SEND2', 'PC_PERF_SC_PC_PTR_SEND3', - 'PC_PERF_SC_PC_PTR_VALID0', 'PC_PERF_SC_PC_PTR_VALID1', - 'PC_PERF_SC_PC_PTR_VALID2', 'PC_PERF_SC_PC_PTR_VALID3', - 'PC_PERF_SC_PQ_FREEZE0', 'PC_PERF_SC_PQ_FREEZE1', - 'PC_PERF_SC_PQ_FREEZE2', 'PC_PERF_SC_PQ_FREEZE3', - 'PC_PERF_SC_WAIT_SYNC0', 'PC_PERF_SC_WAIT_SYNC1', - 'PC_PERF_SC_WAIT_SYNC2', 'PC_PERF_SC_WAIT_SYNC3', - 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', - 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', - 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', - 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', - 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', - 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', - 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', - 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', - 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', - 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', - 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', - 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', - 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', - 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', - 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', - 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', - 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', - 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', - 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', - 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', - 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', - 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', - 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', - 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', - 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', - 'PERFCOUNTER_CNTOFF_START_DIS', - 'PERFCOUNTER_CNTOFF_START_DISABLE', - 'PERFCOUNTER_CNTOFF_START_ENABLE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', - 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', - 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', - 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', - 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', - 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', - 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', - 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', - 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', - 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', - 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', - 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', - 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', - 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', - 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', - 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', - 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', - 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', - 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', - 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', - 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', - 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', - 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', - 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', - 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', - 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', - 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', - 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', - 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', - 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', - 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', - 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', - 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', - 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', - 'PERFMON_COUNTER_MODE_ACCUM', - 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 'PERFMON_COUNTER_MODE_DIRTY', - 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', - 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', - 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', - 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', - 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', - 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', - 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', - 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', - 'PERF_CLPR_BACK_PRIM', 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS', - 'PERF_CLPR_INPUT_END_OF_PACKET', 'PERF_CLPR_INPUT_EVENT', - 'PERF_CLPR_INPUT_EXTENDED_EVENT', - 'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP', 'PERF_CLPR_INPUT_NULL_PRIM', - 'PERF_CLPR_INPUT_PRIM', 'PERF_CLPR_INPUT_SEND', 'PERF_ENGG_BUSY', - 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 'PERF_ENGG_CSB_NULL_SUBGROUP', - 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', - 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 'PERF_ENGG_INDEX_REQ_STARVED', 'PERF_ENGG_INDEX_RET0_NEW_VERTS', - 'PERF_ENGG_INDEX_RET10_NEW_VERTS', - 'PERF_ENGG_INDEX_RET11_NEW_VERTS', - 'PERF_ENGG_INDEX_RET12_NEW_VERTS', - 'PERF_ENGG_INDEX_RET1_NEW_VERTS', - 'PERF_ENGG_INDEX_RET2_NEW_VERTS', - 'PERF_ENGG_INDEX_RET3_NEW_VERTS', - 'PERF_ENGG_INDEX_RET4_NEW_VERTS', - 'PERF_ENGG_INDEX_RET5_NEW_VERTS', - 'PERF_ENGG_INDEX_RET6_NEW_VERTS', - 'PERF_ENGG_INDEX_RET7_NEW_VERTS', - 'PERF_ENGG_INDEX_RET8_NEW_VERTS', - 'PERF_ENGG_INDEX_RET9_NEW_VERTS', - 'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', - 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', - 'PERF_OUTPUT_PRIM_4_SC', 'PERF_OUTPUT_PRIM_5_SC', - 'PERF_OUTPUT_PRIM_6_SC', 'PERF_PAPC_CCGSM_BUSY', - 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', - 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', - 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', - 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', - 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', - 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', - 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', - 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS', - 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_REC_BUSY', - 'PERF_PAPC_PASX_REC_IDLE', 'PERF_PAPC_PASX_REC_STALLED', - 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', - 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', - 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 'PERF_PAPC_PASX_VTX_NAN_DISCARD', 'PERF_PAPC_PA_REG_SCLK_VLD', - 'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_ALL_OUTPUT_PRIM', 'PERF_PAPC_SU_ALL_STALLED_SC', - 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', 'PERF_PAPC_SU_BUSY', - 'PERF_PAPC_SU_CULLED_PRIM', 'PERF_PAPC_SU_DYN_SCLK_VLD', - 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', 'PERF_PAPC_SU_IDLE', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', - 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', - 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', - 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE0_STALLED_SC', - 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE1_STALLED_SC', - 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE2_STALLED_SC', - 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE3_STALLED_SC', - 'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE4_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE4_STALLED_SC', - 'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE5_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE5_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', - 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 'PERF_PASX_CCDIST0_VECTOR', 'PERF_PASX_CCDIST1_VECTOR', - 'PERF_PASX_MISC_VECTOR', 'PERF_PASX_POS_VECTOR', - 'PERF_PASX_STEREO_POS_VECTOR', 'PERF_PA_BUSY', - 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', - 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', - 'PERF_PH_SEND_4_SC', 'PERF_PH_SEND_5_SC', 'PERF_PH_SEND_6_SC', - 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 'PERF_SU_INPUT_SEND', 'PERF_SU_OUTPUT_SEND', - 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', - 'PERSISTENT_SPACE_START', 'PFVF_SQDEC_BEGIN', 'PFVF_SQDEC_END', - 'PHYSYMCLK_FORCE_EN', 'PHYSYMCLK_FORCE_EN_DISABLE', - 'PHYSYMCLK_FORCE_EN_ENABLE', 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', - 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', 'PHYSYMCLK_FORCE_SRC_SEL', - 'PHYSYMCLK_FORCE_SRC_SYMCLK', 'PHY_MUX_ENABLE_ENUM', - 'PHY_MUX_ENABLE_ENUM_DISABLED', 'PHY_MUX_ENABLE_ENUM_ENABLED', - 'PH_PERFCNT_SEL', 'PH_PERF_SC0_FIFO_STATUS_0', - 'PH_PERF_SC0_FIFO_STATUS_1', 'PH_PERF_SC0_FIFO_STATUS_2', - 'PH_PERF_SC0_FIFO_STATUS_3', 'PH_PERF_SC1_FIFO_STATUS_0', - 'PH_PERF_SC1_FIFO_STATUS_1', 'PH_PERF_SC1_FIFO_STATUS_2', - 'PH_PERF_SC1_FIFO_STATUS_3', 'PH_PERF_SC2_FIFO_STATUS_0', - 'PH_PERF_SC2_FIFO_STATUS_1', 'PH_PERF_SC2_FIFO_STATUS_2', - 'PH_PERF_SC2_FIFO_STATUS_3', 'PH_PERF_SC3_FIFO_STATUS_0', - 'PH_PERF_SC3_FIFO_STATUS_1', 'PH_PERF_SC3_FIFO_STATUS_2', - 'PH_PERF_SC3_FIFO_STATUS_3', 'PH_PERF_SC4_FIFO_STATUS_0', - 'PH_PERF_SC4_FIFO_STATUS_1', 'PH_PERF_SC4_FIFO_STATUS_2', - 'PH_PERF_SC4_FIFO_STATUS_3', 'PH_PERF_SC5_FIFO_STATUS_0', - 'PH_PERF_SC5_FIFO_STATUS_1', 'PH_PERF_SC5_FIFO_STATUS_2', - 'PH_PERF_SC5_FIFO_STATUS_3', 'PH_PERF_SC6_FIFO_STATUS_0', - 'PH_PERF_SC6_FIFO_STATUS_1', 'PH_PERF_SC6_FIFO_STATUS_2', - 'PH_PERF_SC6_FIFO_STATUS_3', 'PH_PERF_SC7_FIFO_STATUS_0', - 'PH_PERF_SC7_FIFO_STATUS_1', 'PH_PERF_SC7_FIFO_STATUS_2', - 'PH_PERF_SC7_FIFO_STATUS_3', - 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_BUSY', - 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA0_EOPG_WE', - 'PH_PERF_SEL_SC0_PA0_EOP_WE', 'PH_PERF_SEL_SC0_PA0_EVENT_WE', - 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA0_FPOP_WE', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA1_EOPG_WE', - 'PH_PERF_SEL_SC0_PA1_EOP_WE', 'PH_PERF_SEL_SC0_PA1_EVENT_WE', - 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA1_FPOP_WE', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA2_EOPG_WE', - 'PH_PERF_SEL_SC0_PA2_EOP_WE', 'PH_PERF_SEL_SC0_PA2_EVENT_WE', - 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA2_FPOP_WE', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA3_EOPG_WE', - 'PH_PERF_SEL_SC0_PA3_EOP_WE', 'PH_PERF_SEL_SC0_PA3_EVENT_WE', - 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA3_FPOP_WE', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA4_EOPG_WE', - 'PH_PERF_SEL_SC0_PA4_EOP_WE', 'PH_PERF_SEL_SC0_PA4_EVENT_WE', - 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA4_FPOP_WE', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA5_EOPG_WE', - 'PH_PERF_SEL_SC0_PA5_EOP_WE', 'PH_PERF_SEL_SC0_PA5_EVENT_WE', - 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA5_FPOP_WE', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA6_EOPG_WE', - 'PH_PERF_SEL_SC0_PA6_EOP_WE', 'PH_PERF_SEL_SC0_PA6_EVENT_WE', - 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA6_FPOP_WE', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA7_EOPG_WE', - 'PH_PERF_SEL_SC0_PA7_EOP_WE', 'PH_PERF_SEL_SC0_PA7_EVENT_WE', - 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC0_PA7_FPOP_WE', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC1_ARB_BUSY', - 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA0_EOPG_WE', - 'PH_PERF_SEL_SC1_PA0_EOP_WE', 'PH_PERF_SEL_SC1_PA0_EVENT_WE', - 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA0_FPOP_WE', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA1_EOPG_WE', - 'PH_PERF_SEL_SC1_PA1_EOP_WE', 'PH_PERF_SEL_SC1_PA1_EVENT_WE', - 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA1_FPOP_WE', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA2_EOPG_WE', - 'PH_PERF_SEL_SC1_PA2_EOP_WE', 'PH_PERF_SEL_SC1_PA2_EVENT_WE', - 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA2_FPOP_WE', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA3_EOPG_WE', - 'PH_PERF_SEL_SC1_PA3_EOP_WE', 'PH_PERF_SEL_SC1_PA3_EVENT_WE', - 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA3_FPOP_WE', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA4_EOPG_WE', - 'PH_PERF_SEL_SC1_PA4_EOP_WE', 'PH_PERF_SEL_SC1_PA4_EVENT_WE', - 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA4_FPOP_WE', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA5_EOPG_WE', - 'PH_PERF_SEL_SC1_PA5_EOP_WE', 'PH_PERF_SEL_SC1_PA5_EVENT_WE', - 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA5_FPOP_WE', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA6_EOPG_WE', - 'PH_PERF_SEL_SC1_PA6_EOP_WE', 'PH_PERF_SEL_SC1_PA6_EVENT_WE', - 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA6_FPOP_WE', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA7_EOPG_WE', - 'PH_PERF_SEL_SC1_PA7_EOP_WE', 'PH_PERF_SEL_SC1_PA7_EVENT_WE', - 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC1_PA7_FPOP_WE', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC2_ARB_BUSY', - 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA0_EOPG_WE', - 'PH_PERF_SEL_SC2_PA0_EOP_WE', 'PH_PERF_SEL_SC2_PA0_EVENT_WE', - 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA0_FPOP_WE', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA1_EOPG_WE', - 'PH_PERF_SEL_SC2_PA1_EOP_WE', 'PH_PERF_SEL_SC2_PA1_EVENT_WE', - 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA1_FPOP_WE', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA2_EOPG_WE', - 'PH_PERF_SEL_SC2_PA2_EOP_WE', 'PH_PERF_SEL_SC2_PA2_EVENT_WE', - 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA2_FPOP_WE', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA3_EOPG_WE', - 'PH_PERF_SEL_SC2_PA3_EOP_WE', 'PH_PERF_SEL_SC2_PA3_EVENT_WE', - 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA3_FPOP_WE', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA4_EOPG_WE', - 'PH_PERF_SEL_SC2_PA4_EOP_WE', 'PH_PERF_SEL_SC2_PA4_EVENT_WE', - 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA4_FPOP_WE', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA5_EOPG_WE', - 'PH_PERF_SEL_SC2_PA5_EOP_WE', 'PH_PERF_SEL_SC2_PA5_EVENT_WE', - 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA5_FPOP_WE', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA6_EOPG_WE', - 'PH_PERF_SEL_SC2_PA6_EOP_WE', 'PH_PERF_SEL_SC2_PA6_EVENT_WE', - 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA6_FPOP_WE', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA7_EOPG_WE', - 'PH_PERF_SEL_SC2_PA7_EOP_WE', 'PH_PERF_SEL_SC2_PA7_EVENT_WE', - 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC2_PA7_FPOP_WE', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC3_ARB_BUSY', - 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA0_EOPG_WE', - 'PH_PERF_SEL_SC3_PA0_EOP_WE', 'PH_PERF_SEL_SC3_PA0_EVENT_WE', - 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA0_FPOP_WE', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA1_EOPG_WE', - 'PH_PERF_SEL_SC3_PA1_EOP_WE', 'PH_PERF_SEL_SC3_PA1_EVENT_WE', - 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA1_FPOP_WE', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA2_EOPG_WE', - 'PH_PERF_SEL_SC3_PA2_EOP_WE', 'PH_PERF_SEL_SC3_PA2_EVENT_WE', - 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA2_FPOP_WE', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA3_EOPG_WE', - 'PH_PERF_SEL_SC3_PA3_EOP_WE', 'PH_PERF_SEL_SC3_PA3_EVENT_WE', - 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA3_FPOP_WE', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA4_EOPG_WE', - 'PH_PERF_SEL_SC3_PA4_EOP_WE', 'PH_PERF_SEL_SC3_PA4_EVENT_WE', - 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA4_FPOP_WE', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA5_EOPG_WE', - 'PH_PERF_SEL_SC3_PA5_EOP_WE', 'PH_PERF_SEL_SC3_PA5_EVENT_WE', - 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA5_FPOP_WE', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA6_EOPG_WE', - 'PH_PERF_SEL_SC3_PA6_EOP_WE', 'PH_PERF_SEL_SC3_PA6_EVENT_WE', - 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA6_FPOP_WE', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA7_EOPG_WE', - 'PH_PERF_SEL_SC3_PA7_EOP_WE', 'PH_PERF_SEL_SC3_PA7_EVENT_WE', - 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC3_PA7_FPOP_WE', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC4_ARB_BUSY', - 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA0_EOPG_WE', - 'PH_PERF_SEL_SC4_PA0_EOP_WE', 'PH_PERF_SEL_SC4_PA0_EVENT_WE', - 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA0_FPOP_WE', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA1_EOPG_WE', - 'PH_PERF_SEL_SC4_PA1_EOP_WE', 'PH_PERF_SEL_SC4_PA1_EVENT_WE', - 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA1_FPOP_WE', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA2_EOPG_WE', - 'PH_PERF_SEL_SC4_PA2_EOP_WE', 'PH_PERF_SEL_SC4_PA2_EVENT_WE', - 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA2_FPOP_WE', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA3_EOPG_WE', - 'PH_PERF_SEL_SC4_PA3_EOP_WE', 'PH_PERF_SEL_SC4_PA3_EVENT_WE', - 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA3_FPOP_WE', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA4_EOPG_WE', - 'PH_PERF_SEL_SC4_PA4_EOP_WE', 'PH_PERF_SEL_SC4_PA4_EVENT_WE', - 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA4_FPOP_WE', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA5_EOPG_WE', - 'PH_PERF_SEL_SC4_PA5_EOP_WE', 'PH_PERF_SEL_SC4_PA5_EVENT_WE', - 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA5_FPOP_WE', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA6_EOPG_WE', - 'PH_PERF_SEL_SC4_PA6_EOP_WE', 'PH_PERF_SEL_SC4_PA6_EVENT_WE', - 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA6_FPOP_WE', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA7_EOPG_WE', - 'PH_PERF_SEL_SC4_PA7_EOP_WE', 'PH_PERF_SEL_SC4_PA7_EVENT_WE', - 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC4_PA7_FPOP_WE', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC5_ARB_BUSY', - 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA0_EOPG_WE', - 'PH_PERF_SEL_SC5_PA0_EOP_WE', 'PH_PERF_SEL_SC5_PA0_EVENT_WE', - 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA0_FPOP_WE', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA1_EOPG_WE', - 'PH_PERF_SEL_SC5_PA1_EOP_WE', 'PH_PERF_SEL_SC5_PA1_EVENT_WE', - 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA1_FPOP_WE', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA2_EOPG_WE', - 'PH_PERF_SEL_SC5_PA2_EOP_WE', 'PH_PERF_SEL_SC5_PA2_EVENT_WE', - 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA2_FPOP_WE', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA3_EOPG_WE', - 'PH_PERF_SEL_SC5_PA3_EOP_WE', 'PH_PERF_SEL_SC5_PA3_EVENT_WE', - 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA3_FPOP_WE', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA4_EOPG_WE', - 'PH_PERF_SEL_SC5_PA4_EOP_WE', 'PH_PERF_SEL_SC5_PA4_EVENT_WE', - 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA4_FPOP_WE', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA5_EOPG_WE', - 'PH_PERF_SEL_SC5_PA5_EOP_WE', 'PH_PERF_SEL_SC5_PA5_EVENT_WE', - 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA5_FPOP_WE', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA6_EOPG_WE', - 'PH_PERF_SEL_SC5_PA6_EOP_WE', 'PH_PERF_SEL_SC5_PA6_EVENT_WE', - 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA6_FPOP_WE', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA7_EOPG_WE', - 'PH_PERF_SEL_SC5_PA7_EOP_WE', 'PH_PERF_SEL_SC5_PA7_EVENT_WE', - 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC5_PA7_FPOP_WE', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC6_ARB_BUSY', - 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA0_EOPG_WE', - 'PH_PERF_SEL_SC6_PA0_EOP_WE', 'PH_PERF_SEL_SC6_PA0_EVENT_WE', - 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA0_FPOP_WE', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA1_EOPG_WE', - 'PH_PERF_SEL_SC6_PA1_EOP_WE', 'PH_PERF_SEL_SC6_PA1_EVENT_WE', - 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA1_FPOP_WE', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA2_EOPG_WE', - 'PH_PERF_SEL_SC6_PA2_EOP_WE', 'PH_PERF_SEL_SC6_PA2_EVENT_WE', - 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA2_FPOP_WE', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA3_EOPG_WE', - 'PH_PERF_SEL_SC6_PA3_EOP_WE', 'PH_PERF_SEL_SC6_PA3_EVENT_WE', - 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA3_FPOP_WE', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA4_EOPG_WE', - 'PH_PERF_SEL_SC6_PA4_EOP_WE', 'PH_PERF_SEL_SC6_PA4_EVENT_WE', - 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA4_FPOP_WE', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA5_EOPG_WE', - 'PH_PERF_SEL_SC6_PA5_EOP_WE', 'PH_PERF_SEL_SC6_PA5_EVENT_WE', - 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA5_FPOP_WE', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA6_EOPG_WE', - 'PH_PERF_SEL_SC6_PA6_EOP_WE', 'PH_PERF_SEL_SC6_PA6_EVENT_WE', - 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA6_FPOP_WE', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA7_EOPG_WE', - 'PH_PERF_SEL_SC6_PA7_EOP_WE', 'PH_PERF_SEL_SC6_PA7_EVENT_WE', - 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC6_PA7_FPOP_WE', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC7_ARB_BUSY', - 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA0_EOPG_WE', - 'PH_PERF_SEL_SC7_PA0_EOP_WE', 'PH_PERF_SEL_SC7_PA0_EVENT_WE', - 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA0_FPOP_WE', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA1_EOPG_WE', - 'PH_PERF_SEL_SC7_PA1_EOP_WE', 'PH_PERF_SEL_SC7_PA1_EVENT_WE', - 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA1_FPOP_WE', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA2_EOPG_WE', - 'PH_PERF_SEL_SC7_PA2_EOP_WE', 'PH_PERF_SEL_SC7_PA2_EVENT_WE', - 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA2_FPOP_WE', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA3_EOPG_WE', - 'PH_PERF_SEL_SC7_PA3_EOP_WE', 'PH_PERF_SEL_SC7_PA3_EVENT_WE', - 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA3_FPOP_WE', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA4_EOPG_WE', - 'PH_PERF_SEL_SC7_PA4_EOP_WE', 'PH_PERF_SEL_SC7_PA4_EVENT_WE', - 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA4_FPOP_WE', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA5_EOPG_WE', - 'PH_PERF_SEL_SC7_PA5_EOP_WE', 'PH_PERF_SEL_SC7_PA5_EVENT_WE', - 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA5_FPOP_WE', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA6_EOPG_WE', - 'PH_PERF_SEL_SC7_PA6_EOP_WE', 'PH_PERF_SEL_SC7_PA6_EVENT_WE', - 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA6_FPOP_WE', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA7_EOPG_WE', - 'PH_PERF_SEL_SC7_PA7_EOP_WE', 'PH_PERF_SEL_SC7_PA7_EVENT_WE', - 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', - 'PH_PERF_SEL_SC7_PA7_FPOP_WE', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', - 'PIPE_ALIGNED_SURF', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', - 'PIPE_ID3', 'PIPE_INT_MASK_MODE', 'PIPE_INT_MASK_MODE_DISABLE', - 'PIPE_INT_MASK_MODE_ENABLE', 'PIPE_INT_TYPE_MODE', - 'PIPE_INT_TYPE_MODE_DISABLE', 'PIPE_INT_TYPE_MODE_ENABLE', - 'PIPE_IN_FLUSH_URGENT', 'PIPE_IN_FLUSH_URGENT_DISABLE', - 'PIPE_IN_FLUSH_URGENT_ENABLE', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 'PIPE_PIXEL_RATE_PLL_SOURCE', - 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', - 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', - 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', - 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', - 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', - 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', - 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', - 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', - 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', - 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', - 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', - 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', - 'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', - 'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', - 'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', - 'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', - 'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', - 'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE', - 'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO', - 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', - 'PS_PARTIAL_FLUSH', 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', - 'PTE_BUFFER_MODE_1', 'PTE_ROW_HEIGHT_LINEAR', - 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', - 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', - 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', - 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', - 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', - 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', - 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', - 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', - 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', - 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', - 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', - 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', - 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', - 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', - 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', - 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', - 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', - 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', - 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', - 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', - 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', - 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', - 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', - 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', - 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', - 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', - 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', - 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', - 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', - 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', - 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', - 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', - 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', - 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', - 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', - 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', - 'RASTER_CONFIG_SE_PAIR_MAP_3', - 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', - 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON', - 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', - 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON', - 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN', - 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS', - 'RDPCSTX_CLOCK_CNTL_TX_CLK_EN', - 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET', - 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET', - 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN', - 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN', - 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET', 'RDPCSTX_FIFO_EMPTY', - 'RDPCSTX_FIFO_FULL', 'RDPCSTX_FIFO_IS_EMPTY', - 'RDPCSTX_FIFO_IS_FULL', 'RDPCSTX_FIFO_NOT_EMPTY', - 'RDPCSTX_FIFO_NOT_FULL', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', - 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', - 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE', - 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', - 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', - 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', - 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', - 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', - 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', - 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', - 'RDPCSTX_PHY_REF_ALT_CLK_EN', 'RDPCSTX_TX_FIFO_DISABLED_MASK', - 'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE', - 'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE', - 'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE', - 'RDPCS_DBG_OCLA_SEL', 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56', - 'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0', - 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', - 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', - 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', - 'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE', - 'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE', - 'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE', - 'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE', - 'RDPCS_LANE_PACK_FROM_MSB_DISABLE', - 'RDPCS_LANE_PACK_FROM_MSB_ENABLE', 'RDPCS_MEM_PWR_DEEP_SLEEP', - 'RDPCS_MEM_PWR_LIGHT_SLEEP', 'RDPCS_MEM_PWR_NO_FORCE', - 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', - 'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_OCLACLK_CLOCK_OFF', - 'RDPCS_OCLACLK_CLOCK_ON', 'RDPCS_OCLACLK_DISABLE', - 'RDPCS_OCLACLK_ENABLE', 'RDPCS_OCLACLK_GATE_DISABLE', - 'RDPCS_OCLACLK_GATE_ENABLE', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', - 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR', - 'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', - 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', - 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', - 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', - 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE', - 'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4', - 'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42', - 'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46', - 'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50', - 'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54', - 'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16', - 'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', - 'RDPCS_PHY_REF_ALT_CLK_DISABLE', 'RDPCS_PHY_REF_ALT_CLK_ENABLE', - 'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1', - 'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3', - 'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5', - 'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7', - 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', - 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_DISABLE', - 'RDPCS_SRAMCLK_ENABLE', 'RDPCS_SRAMCLK_GATE_DISABLE', - 'RDPCS_SRAMCLK_GATE_ENABLE', 'RDPCS_SRAMCLK_NOT_PASS', - 'RDPCS_SRAMCLK_PASS', 'RDPCS_SRAM_EXT_LD_DONE', - 'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE', - 'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE', - 'RDPCS_SRAM_SRAM_RESET_ENABLE', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', - 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCS_TEST_CLK_SEL', - 'RDPCS_TEST_CLK_SEL_CFGCLK', - 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', - 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1', - 'RDPCS_TX_CLK_CLOCK_OFF', 'RDPCS_TX_CLK_CLOCK_ON', - 'RDPCS_TX_CLK_DISABLE', 'RDPCS_TX_CLK_ENABLE', - 'RDPCS_TX_CLK_GATE_DISABLE', 'RDPCS_TX_CLK_GATE_ENABLE', - 'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB', 'RDPCS_TX_FIFO_DISABLE', - 'RDPCS_TX_FIFO_ENABLE', 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', - 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE', - 'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE', - 'RDPCS_TX_SOFT_RESET_ENABLE', - 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', - 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', - 'READ_COMPRESSION_MODE', 'READ_SEQ', 'RECTLIST', 'RECT_2D', - 'RED_LUT', 'REFER_TO_DP_SOF', 'REFER_TO_OTG_SOF', - 'REG_SECURE_VIOLATE_READ', 'REG_SECURE_VIOLATE_WRITE', - 'REG_UNALLOCATED_ADDR_READ', 'REG_UNALLOCATED_ADDR_WRITE', - 'REG_VIRTUAL_READ', 'REG_VIRTUAL_WRITE', 'RESERVED1', 'RESERVED2', - 'RESERVED3', 'RESERVED4', 'RESERVED_1', 'RESERVED_10', - 'RESERVED_11', 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', - 'RESERVED_23', 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', - 'RESERVED_34', 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', - 'RESERVED_46', 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', - 'RESERVED_58', 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', - 'RESERVED_62', 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', - 'RESERVED_74', 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', - 'RESERVED_85', 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', - 'RESERVED_89', 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', - 'RESERVED_RDPOLICY', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', - 'RESPONSE_STATUS', 'RE_Z', 'RGB111110_FIX', 'RGB111110_FLOAT', - 'RGB565', 'RGBA1010102', 'RGBA16161616_10LSB', - 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', 'RGBA16161616_12MSB', - 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', 'RGBA16161616_UNORM', - 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', 'RINGID0', 'RINGID1', - 'RINGID2', 'RINGID3', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', - 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', - 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', - 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', - 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', - 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', - 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', - 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', - 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', - 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', - 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', - 'RMIPerfSel', 'RMI_PERF_SEL_BUSY', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR', - 'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', - 'RMI_PERF_SEL_NONE', 'RMI_PERF_SEL_PERF_WINDOW', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', - 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE', - 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', - 'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE', - 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', - 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE', - 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', - 'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE', - 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', - 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', - 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', - 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', - 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', - 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', - 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', - 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 'RMI_PERF_SEL_TCIW_REQ', - 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', 'ROM_SIGNATURE', - 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', - 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', - 'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', - 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', - 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', - 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', - 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', - 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', - 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', - 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', - 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', - 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', - 'ReadPolicy', 'Reserved_0x00', 'RingCounterControl', - 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS', - 'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2', - 'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', - 'SCL_ALPHA_COEF_FIRST', 'SCL_ALPHA_COEF_SECOND', - 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK', - 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_FIRST', - 'SCL_CHROMA_COEF_SECOND', 'SCL_COEF_2TAP_HARDCODE_OFF', - 'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_CHROMA_HORZ_FILTER', - 'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL', - 'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER', - 'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', - 'SCL_COEF_SC_HORZ_FILTER', 'SCL_COEF_SC_VERT_FILTER', - 'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SCOPE', - 'SCOPE_CU', 'SCOPE_DEV', 'SCOPE_SE', 'SCOPE_SYS', - 'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', - 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', - 'SC_BE_VRS_FB_RET', 'SC_BE_VRS_FB_RET_HIT', - 'SC_BE_VRS_FB_RET_STALLED', 'SC_BE_VRS_RD_REQ', - 'SC_BE_VRS_RD_REQ_HIT', 'SC_BE_VRS_RD_REQ_STALLED', - 'SC_BE_VRS_RD_RET', 'SC_BE_VRS_RD_RET_STALLED', - 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', - 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', - 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', - 'SC_DB0_QUAD_INTF_BUSY', 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', - 'SC_DB0_QUAD_INTF_IDLE', 'SC_DB0_QUAD_INTF_SEND', - 'SC_DB0_QUAD_INTF_STALLED_BY_DB', 'SC_DB0_TILE_INTERFACE_BUSY', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 'SC_DB0_TILE_MASK_FIFO_FULL', - 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', - 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', - 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_GL1X_BUSY', - 'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY', - 'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY', - 'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY', - 'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY', - 'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_LSB', - 'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED', 'SC_P0_DETAIL_QUAD_COUNT', - 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 'SC_P0_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', - 'SC_PA0_SC_DEALLOC_2_0_RD', 'SC_PA0_SC_EOP_WE', - 'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_NULL_DEALLOC_WE', - 'SC_PA0_SC_NULL_WE', 'SC_PA_SC_DEALLOC_2_0_WE', - 'SC_PA_SC_FPOV_WE', 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', - 'SC_PBB_BUSY_AND_NO_SENDS', - 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', - 'SC_PBB_END_OF_BIN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', - 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', - 'SC_PBB_READ_DEALLOC_4_0', 'SC_PBB_READ_DEALLOC_7_5', - 'SC_PBB_READ_FPOG_4_0', 'SC_PBB_READ_FPOG_7_5', 'SC_PBB_READ_PH0', - 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', - 'SC_PERF_SEL_RESERVED_108', 'SC_PERF_SEL_RESERVED_109', - 'SC_PERF_SEL_RESERVED_110', 'SC_PERF_SEL_RESERVED_111', - 'SC_PERF_SEL_RESERVED_112', 'SC_PERF_SEL_RESERVED_113', - 'SC_PERF_SEL_RESERVED_114', 'SC_PERF_SEL_RESERVED_115', - 'SC_PERF_SEL_RESERVED_116', 'SC_PERF_SEL_RESERVED_117', - 'SC_PERF_SEL_RESERVED_118', 'SC_PERF_SEL_RESERVED_119', - 'SC_PERF_SEL_RESERVED_120', 'SC_PERF_SEL_RESERVED_121', - 'SC_PERF_SEL_RESERVED_122', 'SC_PERF_SEL_RESERVED_123', - 'SC_PERF_SEL_RESERVED_124', 'SC_PERF_SEL_RESERVED_125', - 'SC_PERF_SEL_RESERVED_126', 'SC_PERF_SEL_RESERVED_127', - 'SC_PERF_SEL_RESERVED_128', 'SC_PERF_SEL_RESERVED_129', - 'SC_PERF_SEL_RESERVED_130', 'SC_PERF_SEL_RESERVED_131', - 'SC_PERF_SEL_RESERVED_132', 'SC_PERF_SEL_RESERVED_133', - 'SC_PERF_SEL_RESERVED_134', 'SC_PERF_SEL_RESERVED_135', - 'SC_PERF_SEL_RESERVED_136', 'SC_PERF_SEL_RESERVED_137', - 'SC_PERF_SEL_RESERVED_138', 'SC_PERF_SEL_RESERVED_139', - 'SC_PERF_SEL_RESERVED_140', 'SC_PERF_SEL_RESERVED_141', - 'SC_PERF_SEL_RESERVED_142', 'SC_PERF_SEL_RESERVED_143', - 'SC_PERF_SEL_RESERVED_144', 'SC_PERF_SEL_RESERVED_145', - 'SC_PERF_SEL_RESERVED_146', 'SC_PERF_SEL_RESERVED_147', - 'SC_PERF_SEL_RESERVED_148', 'SC_PERF_SEL_RESERVED_149', - 'SC_PERF_SEL_RESERVED_150', 'SC_PERF_SEL_RESERVED_151', - 'SC_PERF_SEL_RESERVED_152', 'SC_PERF_SEL_RESERVED_153', - 'SC_PERF_SEL_RESERVED_154', 'SC_PERF_SEL_RESERVED_155', - 'SC_PERF_SEL_RESERVED_156', 'SC_PERF_SEL_RESERVED_157', - 'SC_PERF_SEL_RESERVED_158', 'SC_PERF_SEL_RESERVED_160', - 'SC_PERF_SEL_RESERVED_161', 'SC_PERF_SEL_RESERVED_162', - 'SC_PERF_SEL_RESERVED_164', 'SC_PERF_SEL_RESERVED_165', - 'SC_PERF_SEL_RESERVED_166', 'SC_PERF_SEL_RESERVED_184', - 'SC_PERF_SEL_RESERVED_185', 'SC_PERF_SEL_RESERVED_186', - 'SC_PERF_SEL_RESERVED_187', 'SC_PERF_SEL_RESERVED_188', - 'SC_PERF_SEL_RESERVED_189', 'SC_PERF_SEL_RESERVED_190', - 'SC_PERF_SEL_RESERVED_191', 'SC_PERF_SEL_RESERVED_192', - 'SC_PERF_SEL_RESERVED_193', 'SC_PERF_SEL_RESERVED_194', - 'SC_PERF_SEL_RESERVED_195', 'SC_PERF_SEL_RESERVED_196', - 'SC_PERF_SEL_RESERVED_197', 'SC_PERF_SEL_RESERVED_198', - 'SC_PERF_SEL_RESERVED_199', 'SC_PERF_SEL_RESERVED_200', - 'SC_PERF_SEL_RESERVED_201', 'SC_PERF_SEL_RESERVED_202', - 'SC_PERF_SEL_RESERVED_203', 'SC_PERF_SEL_RESERVED_204', - 'SC_PERF_SEL_RESERVED_205', 'SC_PERF_SEL_RESERVED_206', - 'SC_PERF_SEL_RESERVED_207', 'SC_PERF_SEL_RESERVED_208', - 'SC_PERF_SEL_RESERVED_209', 'SC_PERF_SEL_RESERVED_210', - 'SC_PERF_SEL_RESERVED_211', 'SC_PERF_SEL_RESERVED_212', - 'SC_PERF_SEL_RESERVED_213', 'SC_PERF_SEL_RESERVED_214', - 'SC_PERF_SEL_RESERVED_215', 'SC_PERF_SEL_RESERVED_216', - 'SC_PERF_SEL_RESERVED_217', 'SC_PERF_SEL_RESERVED_218', - 'SC_PERF_SEL_RESERVED_219', 'SC_PERF_SEL_RESERVED_220', - 'SC_PERF_SEL_RESERVED_221', 'SC_PERF_SEL_RESERVED_222', - 'SC_PERF_SEL_RESERVED_223', 'SC_PERF_SEL_RESERVED_224', - 'SC_PERF_SEL_RESERVED_225', 'SC_PERF_SEL_RESERVED_226', - 'SC_PERF_SEL_RESERVED_227', 'SC_PERF_SEL_RESERVED_228', - 'SC_PERF_SEL_RESERVED_229', 'SC_PERF_SEL_RESERVED_230', - 'SC_PERF_SEL_RESERVED_231', 'SC_PERF_SEL_RESERVED_232', - 'SC_PERF_SEL_RESERVED_233', 'SC_PERF_SEL_RESERVED_234', - 'SC_PERF_SEL_RESERVED_236', 'SC_PERF_SEL_RESERVED_237', - 'SC_PERF_SEL_RESERVED_238', 'SC_PERF_SEL_RESERVED_240', - 'SC_PERF_SEL_RESERVED_241', 'SC_PERF_SEL_RESERVED_242', - 'SC_PERF_SEL_RESERVED_247', 'SC_PERF_SEL_RESERVED_248', - 'SC_PERF_SEL_RESERVED_249', 'SC_PERF_SEL_RESERVED_250', - 'SC_PERF_SEL_RESERVED_251', 'SC_PERF_SEL_RESERVED_252', - 'SC_PERF_SEL_RESERVED_253', 'SC_PERF_SEL_RESERVED_254', - 'SC_PERF_SEL_RESERVED_255', 'SC_PERF_SEL_RESERVED_256', - 'SC_PERF_SEL_RESERVED_257', 'SC_PERF_SEL_RESERVED_258', - 'SC_PERF_SEL_RESERVED_279', 'SC_PERF_SEL_RESERVED_280', - 'SC_PERF_SEL_RESERVED_288', 'SC_PERF_SEL_RESERVED_289', - 'SC_PERF_SEL_RESERVED_290', 'SC_PERF_SEL_RESERVED_291', - 'SC_PERF_SEL_RESERVED_293', 'SC_PERF_SEL_RESERVED_294', - 'SC_PERF_SEL_RESERVED_295', 'SC_PERF_SEL_RESERVED_296', - 'SC_PERF_SEL_RESERVED_297', 'SC_PERF_SEL_RESERVED_298', - 'SC_PERF_SEL_RESERVED_299', 'SC_PERF_SEL_RESERVED_301', - 'SC_PERF_SEL_RESERVED_303', 'SC_PERF_SEL_RESERVED_304', - 'SC_PERF_SEL_RESERVED_305', 'SC_PERF_SEL_RESERVED_306', - 'SC_PERF_SEL_RESERVED_307', 'SC_PERF_SEL_RESERVED_308', - 'SC_PERF_SEL_RESERVED_309', 'SC_PERF_SEL_RESERVED_310', - 'SC_PERF_SEL_RESERVED_311', 'SC_PERF_SEL_RESERVED_312', - 'SC_PERF_SEL_RESERVED_313', 'SC_PERF_SEL_RESERVED_314', - 'SC_PERF_SEL_RESERVED_315', 'SC_PERF_SEL_RESERVED_316', - 'SC_PERF_SEL_RESERVED_317', 'SC_PERF_SEL_RESERVED_319', - 'SC_PERF_SEL_RESERVED_320', 'SC_PERF_SEL_RESERVED_321', - 'SC_PERF_SEL_RESERVED_322', 'SC_PERF_SEL_RESERVED_323', - 'SC_PERF_SEL_RESERVED_324', 'SC_PERF_SEL_RESERVED_325', - 'SC_PERF_SEL_RESERVED_328', 'SC_PERF_SEL_RESERVED_329', - 'SC_PERF_SEL_RESERVED_330', 'SC_PERF_SEL_RESERVED_331', - 'SC_PERF_SEL_RESERVED_332', 'SC_PERF_SEL_RESERVED_333', - 'SC_PERF_SEL_RESERVED_334', 'SC_PERF_SEL_RESERVED_335', - 'SC_PERF_SEL_RESERVED_336', 'SC_PERF_SEL_RESERVED_337', - 'SC_PERF_SEL_RESERVED_340', 'SC_PERF_SEL_RESERVED_341', - 'SC_PERF_SEL_RESERVED_347', 'SC_PERF_SEL_RESERVED_348', - 'SC_PERF_SEL_RESERVED_351', 'SC_PERF_SEL_RESERVED_354', - 'SC_PERF_SEL_RESERVED_355', 'SC_PERF_SEL_RESERVED_356', - 'SC_PERF_SEL_RESERVED_357', 'SC_PERF_SEL_RESERVED_358', - 'SC_PERF_SEL_RESERVED_359', 'SC_PERF_SEL_RESERVED_360', - 'SC_PERF_SEL_RESERVED_361', 'SC_PERF_SEL_RESERVED_362', - 'SC_PERF_SEL_RESERVED_363', 'SC_PERF_SEL_RESERVED_364', - 'SC_PERF_SEL_RESERVED_365', 'SC_PERF_SEL_RESERVED_366', - 'SC_PERF_SEL_RESERVED_367', 'SC_PERF_SEL_RESERVED_368', - 'SC_PERF_SEL_RESERVED_369', 'SC_PERF_SEL_RESERVED_370', - 'SC_PERF_SEL_RESERVED_371', 'SC_PERF_SEL_RESERVED_372', - 'SC_PERF_SEL_RESERVED_375', 'SC_PERF_SEL_RESERVED_376', - 'SC_PERF_SEL_RESERVED_377', 'SC_PERF_SEL_RESERVED_378', - 'SC_PERF_SEL_RESERVED_379', 'SC_PERF_SEL_RESERVED_380', - 'SC_PERF_SEL_RESERVED_381', 'SC_PERF_SEL_RESERVED_382', - 'SC_PERF_SEL_RESERVED_383', 'SC_PERF_SEL_RESERVED_384', - 'SC_PERF_SEL_RESERVED_385', 'SC_PERF_SEL_RESERVED_423', - 'SC_PERF_SEL_RESERVED_424', 'SC_PERF_SEL_RESERVED_425', - 'SC_PERF_SEL_RESERVED_426', 'SC_PERF_SEL_RESERVED_427', - 'SC_PERF_SEL_RESERVED_428', 'SC_PERF_SEL_RESERVED_429', - 'SC_PERF_SEL_RESERVED_430', 'SC_PERF_SEL_RESERVED_431', - 'SC_PERF_SEL_RESERVED_432', 'SC_PERF_SEL_RESERVED_433', - 'SC_PERF_SEL_RESERVED_434', 'SC_PERF_SEL_RESERVED_435', - 'SC_PERF_SEL_RESERVED_436', 'SC_PERF_SEL_RESERVED_478', - 'SC_PERF_SEL_RESERVED_479', 'SC_PERF_SEL_RESERVED_483', - 'SC_PERF_SEL_RESERVED_484', 'SC_PERF_SEL_RESERVED_485', - 'SC_PERF_SEL_RESERVED_486', 'SC_PERF_SEL_RESERVED_487', - 'SC_PERF_SEL_RESERVED_488', 'SC_PERF_SEL_RESERVED_489', - 'SC_PERF_SEL_RESERVED_490', 'SC_PERF_SEL_RESERVED_509', - 'SC_PERF_SEL_RESERVED_510', 'SC_PERF_SEL_RESERVED_511', - 'SC_PERF_SEL_RESERVED_512', 'SC_PERF_SEL_RESERVED_513', - 'SC_PERF_SEL_RESERVED_514', 'SC_PERF_SEL_RESERVED_523', - 'SC_PERF_SEL_RESERVED_524', 'SC_PERF_SEL_RESERVED_525', - 'SC_PERF_SEL_RESERVED_532', 'SC_PERF_SEL_RESERVED_533', - 'SC_PERF_SEL_RESERVED_534', 'SC_PERF_SEL_RESERVED_539', - 'SC_PERF_SEL_RESERVED_568', 'SC_PERF_SEL_RESERVED_76', - 'SC_PERF_SEL_RESERVED_77', 'SC_PERF_SEL_RESERVED_78', - 'SC_PERF_SEL_RESERVED_80', 'SC_PERF_SEL_RESERVED_81', - 'SC_PERF_SEL_RESERVED_82', 'SC_PERF_SEL_RESERVED_84', - 'SC_PERF_SEL_RESERVED_85', 'SC_PERF_SEL_RESERVED_86', - 'SC_PERF_SEL_RESERVED_88', 'SC_PERF_SEL_RESERVED_89', - 'SC_PERF_SEL_RESERVED_90', 'SC_PKR_4X2_FILL_QUAD', - 'SC_PKR_4X2_QUAD_SPLIT', 'SC_PKR_BCI_QUAD_NEW_PRIM', - 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', - 'SC_PKR_DB_OREO_WAVE_QUAD_COUNT', 'SC_PKR_DB_WAVE_STALL', - 'SC_PKR_END_OF_VECTOR', - 'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID', - 'SC_PKR_PC_NO_CREDITS', 'SC_PKR_PC_SEND', 'SC_PKR_PC_SEND_EOV', - 'SC_PKR_PC_SEND_EVENT', 'SC_PKR_PC_SEND_PRIM_VALID_0', - 'SC_PKR_PC_SEND_PRIM_VALID_1', 'SC_PKR_PC_SEND_TRUE_PRIM', - 'SC_PKR_PC_STALLED', 'SC_PKR_PSINVOC_SEDC_FIFO_FULL', - 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', - 'SC_PKR_SPI_QUAD_COUNT', 'SC_PKR_WAVE_BREAK_FULL_TILE', - 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', 'SC_PK_BUSY', - 'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', - 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', - 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', - 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', - 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', - 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', - 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', - 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PWS_CS_EVENTS_PWS_ENABLE', - 'SC_PWS_P0_CS_SYNC_COMPLETE', 'SC_PWS_P0_PS_SYNC_COMPLETE', - 'SC_PWS_P0_TS_SYNC_COMPLETE', 'SC_PWS_P1_CS_SYNC_COMPLETE', - 'SC_PWS_P1_PS_SYNC_COMPLETE', 'SC_PWS_P1_TS_SYNC_COMPLETE', - 'SC_PWS_PS_EVENTS_PWS_ENABLE', 'SC_PWS_STALLED', - 'SC_PWS_TS_EVENTS_PWS_ENABLE', 'SC_PW_BM_PASS_EMPTY_PRIM', - 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', - 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', - 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', - 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', - 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', - 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', - 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', - 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', - 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', - 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', - 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', - 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_60', - 'SC_SCB_BUSY', 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', - 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', - 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_4_0', - 'SC_SPI_DEALLOC_7_5', 'SC_SPI_EVENT', 'SC_SPI_FPOV_4_0', - 'SC_SPI_FPOV_7_5', 'SC_SPI_SEND', 'SC_SPI_WAVE_STALLED_BY_SPI', - 'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY', - 'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB0_TILEFIFO', - 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', - 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', - 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', - 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', - 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 'SC_SUPERTILE_COUNT', - 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', - 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', - 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', - 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', - 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', - 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', - 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', - 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', - 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', - 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', - 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', - 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', - 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', - 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', - 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', - 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', - 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', - 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', - 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', - 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', - 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRC_ACK_OUTPUT_STALL', - 'SC_VRC_BUSY', 'SC_VRC_DIRTY_SECTORS_FLUSHED', - 'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL', 'SC_VRC_FLUSH', - 'SC_VRC_FLUSH_DONE_STALL', 'SC_VRC_FLUSH_EVICT_STALL', - 'SC_VRC_FLUSH_FIP_HIT_STALL', 'SC_VRC_FLUSH_REFLUSH_STALL', - 'SC_VRC_FLUSH_STALL', 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL', - 'SC_VRC_GL1X_RD_REQ', 'SC_VRC_GL1X_RD_RET', - 'SC_VRC_GL1X_RD_XNACK', 'SC_VRC_GL1X_REQ_STALLED', - 'SC_VRC_GL1X_SRC_STALLED', 'SC_VRC_GL1X_SRC_XFR', - 'SC_VRC_GL1X_WR_ACK', 'SC_VRC_GL1X_WR_REQ', - 'SC_VRC_GL1X_WR_XNACK', 'SC_VRC_HINTMEM_RE_CNT', - 'SC_VRC_HINTMEM_WE_CNT', 'SC_VRC_HPF_EVENT', 'SC_VRC_HPF_REQ', - 'SC_VRC_HPF_STALLED', 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL', - 'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL', - 'SC_VRC_LRU_EVICT_STALL', 'SC_VRC_PROBE_ACK_TILES', - 'SC_VRC_RATEMEM_RE_CNT', 'SC_VRC_RATEMEM_WE_CNT', - 'SC_VRC_READ_OUTPUT_STALL', 'SC_VRC_REEVICTION_STALL', - 'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL', - 'SC_VRC_REPLACE_PENDING_EVICT_STALL', - 'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL', 'SC_VRC_SECTORS_FLUSHED', - 'SC_VRC_SECTOR_HIT', 'SC_VRC_SECTOR_MISS', 'SC_VRC_STALL', - 'SC_VRC_TAGS_FLUSHED', 'SC_VRC_TAG_MISS', - 'SC_VRC_WRITE_OUTPUT_STALL', 'SC_VRS_BE_BUSY', - 'SC_VRS_COMB_MODE_MAX', 'SC_VRS_COMB_MODE_MIN', - 'SC_VRS_COMB_MODE_OVERRIDE', 'SC_VRS_COMB_MODE_PASSTHRU', - 'SC_VRS_COMB_MODE_SATURATE', 'SDMA_PERFMON_SEL', - 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', 'SDMA_PERFMON_SEL_CE_DST_IDLE', - 'SDMA_PERFMON_SEL_CE_INFO1_FULL', 'SDMA_PERFMON_SEL_CE_INFO_FULL', - 'SDMA_PERFMON_SEL_CE_IN_IDLE', 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', - 'SDMA_PERFMON_SEL_CE_OUT_IDLE', 'SDMA_PERFMON_SEL_CE_RD_STALL', - 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', - 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', 'SDMA_PERFMON_SEL_CE_WR_IDLE', - 'SDMA_PERFMON_SEL_CE_WR_STALL', - 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', - 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', - 'SDMA_PERFMON_SEL_DUMMY_0', 'SDMA_PERFMON_SEL_DUMMY_1', - 'SDMA_PERFMON_SEL_EX_IDLE', - 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERFMON_SEL_GCR_RTN', 'SDMA_PERFMON_SEL_GCR_SEND', - 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', - 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 'SDMA_PERFMON_SEL_MCU_L1_WR_VLD', 'SDMA_PERFMON_SEL_MC_RD_COUNT', - 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', - 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_QUEUE0_SELECT', - 'SDMA_PERFMON_SEL_QUEUE1_SELECT', - 'SDMA_PERFMON_SEL_QUEUE2_SELECT', - 'SDMA_PERFMON_SEL_QUEUE3_SELECT', 'SDMA_PERFMON_SEL_RB_CMD_FULL', - 'SDMA_PERFMON_SEL_RB_CMD_IDLE', 'SDMA_PERFMON_SEL_RB_EMPTY', - 'SDMA_PERFMON_SEL_RB_FULL', 'SDMA_PERFMON_SEL_RB_RPTR_WB', - 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', - 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', - 'SDMA_PERFMON_SEL_TLBI_SEND', - 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', - 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', - 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', - 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', - 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', - 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ', - 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', - 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', - 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', - 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', - 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', - 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', - 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', - 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_DUMMY_0', - 'SDMA_PERF_SEL_DUMMY_1', 'SDMA_PERF_SEL_EX_IDLE', - 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', - 'SDMA_PERF_SEL_GPUVM_INV_HIGH', 'SDMA_PERF_SEL_GPUVM_INV_LOW', - 'SDMA_PERF_SEL_IB_CH_RD_REQ', 'SDMA_PERF_SEL_IB_CH_RD_RET', - 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', - 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', - 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', - 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', - 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 'SDMA_PERF_SEL_L2_META_RET_VLD', 'SDMA_PERF_SEL_MCU_CH_WR_REQ', - 'SDMA_PERF_SEL_MCU_CH_WR_RET', 'SDMA_PERF_SEL_MCU_L1_WR_VLD', - 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER', - 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END', - 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START', - 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', - 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', - 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', - 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_QUEUE0_SELECT', - 'SDMA_PERF_SEL_QUEUE1_SELECT', 'SDMA_PERF_SEL_QUEUE2_SELECT', - 'SDMA_PERF_SEL_QUEUE3_SELECT', 'SDMA_PERF_SEL_QUEUE4_SELECT', - 'SDMA_PERF_SEL_QUEUE5_SELECT', 'SDMA_PERF_SEL_QUEUE6_SELECT', - 'SDMA_PERF_SEL_QUEUE7_SELECT', 'SDMA_PERF_SEL_RB_CH_RD_REQ', - 'SDMA_PERF_SEL_RB_CH_RD_RET', 'SDMA_PERF_SEL_RB_CMD_FULL', - 'SDMA_PERF_SEL_RB_CMD_IDLE', 'SDMA_PERF_SEL_RB_EMPTY', - 'SDMA_PERF_SEL_RB_FULL', 'SDMA_PERF_SEL_RB_RPTR_WB', - 'SDMA_PERF_SEL_RB_RPTR_WRAP', 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 'SDMA_PERF_SEL_RB_WPTR_WRAP', 'SDMA_PERF_SEL_RD_BA_RTR', - 'SDMA_PERF_SEL_REG_IDLE', 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', - 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', - 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', - 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', - 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', - 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', - 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', - 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK_P0', - 'SEL_DTBCLK_P1', 'SEL_DTBCLK_P2', 'SEL_DTBCLK_P3', - 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', - 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', - 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', - 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', - 'SH_MEM_ALIGNMENT_MODE_DWORD', - 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', - 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', - 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', - 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', - 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', - 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', - 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', - 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', - 'SLVERR', 'SMU_INTR', 'SMU_INTR_STATUS_CLEAR', - 'SMU_INTR_STATUS_NOOP', 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', - 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', - 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', - 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', - 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', - 'SPI_PERF_ALL_PS_WAVE', 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT', - 'SPI_PERF_ALL_WAVE', 'SPI_PERF_ALL_WAVE_IN_FLIGHT', - 'SPI_PERF_ALL_WAVE_ITEMS', 'SPI_PERF_ALL_WAVE_ITEMS_W32', - 'SPI_PERF_ALL_WAVE_ITEMS_W64', 'SPI_PERF_ALL_WAVE_RESTORED', - 'SPI_PERF_ALL_WAVE_SAVED', 'SPI_PERF_ALL_WAVE_W32', - 'SPI_PERF_ALL_WAVE_W64', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', - 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', - 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', - 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WAVE_IN_FLIGHT', - 'SPI_PERF_CSGN_WINDOW_VALID', 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL', - 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', - 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', - 'SPI_PERF_CSN_TEMP_ALLOC_LEVEL', 'SPI_PERF_CSN_WAVE', - 'SPI_PERF_CSN_WAVE_IN_FLIGHT', 'SPI_PERF_CSN_WINDOW_VALID', - 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', - 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', - 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', - 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', - 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', - 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', - 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', - 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', - 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', - 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 'SPI_PERF_GFX_TEMP_ALLOC_LEVEL', 'SPI_PERF_GS_ALLOC_IDX', - 'SPI_PERF_GS_ALLOC_POS', 'SPI_PERF_GS_BUSY', - 'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE', - 'SPI_PERF_GS_EXP_DONE', 'SPI_PERF_GS_FIRST_SUBGRP', - 'SPI_PERF_GS_GRP_LIFETIME', 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE', - 'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_INDX0_STALL', - 'SPI_PERF_GS_INDX1_STALL', 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', - 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', - 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', - 'SPI_PERF_GS_SCBD_IDX_CLEANUP', 'SPI_PERF_GS_SCBD_POS_CLEANUP', - 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WAVE_IN_FLIGHT', - 'SPI_PERF_GS_WINDOW_VALID', 'SPI_PERF_HS_BUSY', - 'SPI_PERF_HS_CRAWLER_STALL', 'SPI_PERF_HS_EVENT_WAVE', - 'SPI_PERF_HS_FIRST_WAVE', 'SPI_PERF_HS_PERS_UPD_FULL0', - 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', - 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WAVE_IN_FLIGHT', - 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS_ALLOC_LEVEL', - 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', - 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', - 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', - 'SPI_PERF_PS0_DEALLOC_FULL', 'SPI_PERF_PS0_EVENT_WAVE', - 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS0_LDS_DONE_FULL', 'SPI_PERF_PS0_OPT_WAVE', - 'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1', - 'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WAVEID_STARVED', - 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WAVE_IN_FLIGHT', - 'SPI_PERF_PS0_WINDOW_VALID', 'SPI_PERF_PS1_2_WAVE_GROUPS', - 'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY', - 'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC', - 'SPI_PERF_PS1_DEALLOC_FULL', 'SPI_PERF_PS1_EVENT_WAVE', - 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS1_LDS_DONE_FULL', 'SPI_PERF_PS1_OPT_WAVE', - 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', - 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', - 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WAVE_IN_FLIGHT', - 'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_2_WAVE_GROUPS', - 'SPI_PERF_PS2_ACTIVE', 'SPI_PERF_PS2_BUSY', - 'SPI_PERF_PS2_CRAWLER_STALL', 'SPI_PERF_PS2_DEALLOC', - 'SPI_PERF_PS2_DEALLOC_FULL', 'SPI_PERF_PS2_EVENT_WAVE', - 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS2_LDS_DONE_FULL', 'SPI_PERF_PS2_OPT_WAVE', - 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', - 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', - 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WAVE_IN_FLIGHT', - 'SPI_PERF_PS2_WINDOW_VALID', 'SPI_PERF_PS3_2_WAVE_GROUPS', - 'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY', - 'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC', - 'SPI_PERF_PS3_DEALLOC_FULL', 'SPI_PERF_PS3_EVENT_WAVE', - 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS3_LDS_DONE_FULL', 'SPI_PERF_PS3_OPT_WAVE', - 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', - 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', - 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WAVE_IN_FLIGHT', - 'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_EXP_ALLOC', - 'SPI_PERF_PS_EXP_ARB_CONFLICT', 'SPI_PERF_PS_EXP_DONE', - 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', - 'SPI_PERF_PS_PWS_STALL', 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_GS', - 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BAR_CU_FULL_PS', - 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', - 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 'SPI_PERF_RA_GS_LDS_OCCUPANCY', 'SPI_PERF_RA_GS_LOCK', - 'SPI_PERF_RA_GS_VGPR_OCCUPANCY', 'SPI_PERF_RA_HS_LOCK', - 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', - 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PC_PROBE_STALL_PS', - 'SPI_PERF_RA_PC_PSWAVE_STALL_PS', 'SPI_PERF_RA_PH_THROTTLE', - 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PRE_ALLOC_STALL', - 'SPI_PERF_RA_PS_LDS_OCCUPANCY', 'SPI_PERF_RA_PS_VGPR_OCCUPANCY', - 'SPI_PERF_RA_REQ_ALLOC', - 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL', - 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL', - 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL', - 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL', - 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 'SPI_PERF_RA_RES_STALL_CSG', 'SPI_PERF_RA_RES_STALL_CSN', - 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', - 'SPI_PERF_RA_RES_STALL_PS', 'SPI_PERF_RA_RSV_UPD', - 'SPI_PERF_RA_SPI_THROTTLE', 'SPI_PERF_RA_TASK_REQ_BIN3', - 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', - 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', - 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', - 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', - 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', - 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SGPR_INIT', - 'SPI_PERF_SWC_CSGN_WR', 'SPI_PERF_SWC_CSN_WR', - 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR', - 'SPI_PERF_VGPR_ALLOC_LEVEL', 'SPI_PERF_VGPR_INIT', - 'SPI_PERF_VWC_CSGN_WR', 'SPI_PERF_VWC_CSN_WR', - 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR', - 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', - 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', - 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', - 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', - 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', - 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', - 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', - 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', - 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', - 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', - 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', - 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', - 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', - 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', - 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_OPERAND', - 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', - 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_VGPR_OPERAND', - 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP', - 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS', - 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX', - 'SP_PERF_SEL_VGPR_EXP_RD', 'SP_PERF_SEL_VGPR_RD', - 'SP_PERF_SEL_VGPR_SPI_WR', 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', - 'SP_PERF_SEL_VGPR_VMEM_RD', 'SP_PERF_SEL_VGPR_WR', - 'SP_PERF_SEL_VGPR_WR_KILL', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', - 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', - 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', - 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES', - 'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES', - 'SQC_PERF_SEL_DCACHE_REQ', 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', - 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', - 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES', - 'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES', - 'SQC_PERF_SEL_ICACHE_REQ', - 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT', - 'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT', - 'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT', - 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS', - 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT', - 'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT', - 'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT', - 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL', - 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 'SQC_PERF_SEL_LDS_LOAD_DWORDS', 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_STORE_DWORDS', - 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', - 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', - 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', - 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', - 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', - 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', - 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', - 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', - 'SQG_PERF_SEL_ITEMS_CS', 'SQG_PERF_SEL_ITEMS_GS', - 'SQG_PERF_SEL_ITEMS_HS', 'SQG_PERF_SEL_ITEMS_PS', - 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE', - 'SQG_PERF_SEL_MSG', 'SQG_PERF_SEL_MSG_BUS_BUSY', - 'SQG_PERF_SEL_MSG_INTERRUPT', 'SQG_PERF_SEL_NONE', - 'SQG_PERF_SEL_PS_QUADS', 'SQG_PERF_SEL_REFCLKS', - 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_STALL', - 'SQG_PERF_SEL_TTRACE_WRITE_DATA', 'SQG_PERF_SEL_WAVE32_ITEMS', - 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', - 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', - 'SQG_PERF_SEL_WAVES_CS_VEC32', 'SQG_PERF_SEL_WAVES_DYN_VGPR', - 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', - 'SQG_PERF_SEL_WAVES_GS_VEC32', 'SQG_PERF_SEL_WAVES_HS_VEC32', - 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', - 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', - 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_PS_VEC32', - 'SQG_PERF_SEL_WAVES_RESTORED', 'SQG_PERF_SEL_WAVES_SAVED', - 'SQG_PERF_SEL_WAVES_VEC32', 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER', - 'SQG_PERF_SEL_WAVE_CYCLES', 'SQIND_GLOBAL_REGS_OFFSET', - 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', - 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HOST_REGS_OFFSET', - 'SQIND_WAVE_HOST_REGS_SIZE', 'SQIND_WAVE_HW_REGS_OFFSET', - 'SQIND_WAVE_HW_REGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', - 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', - 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', - 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', - 'SQPWRDEC_END', 'SQ_ARB_STATE_ISSUED_BRMSG', - 'SQ_ARB_STATE_ISSUED_EXPORT', 'SQ_ARB_STATE_ISSUED_LDS', - 'SQ_ARB_STATE_ISSUED_LDS_DIRECT', 'SQ_ARB_STATE_ISSUED_SCALAR', - 'SQ_ARB_STATE_ISSUED_TEX', 'SQ_ARB_STATE_ISSUED_VALU', - 'SQ_ARB_STATE_STALLED_BRMSG', 'SQ_ARB_STATE_STALLED_EXPORT', - 'SQ_ARB_STATE_STALLED_LDS', 'SQ_ARB_STATE_STALLED_LDS_DIRECT', - 'SQ_ARB_STATE_STALLED_SCALAR', 'SQ_ARB_STATE_STALLED_TEX', - 'SQ_ARB_STATE_STALLED_VALU', 'SQ_CAC_POWER_ALU_BUSY', - 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', - 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', - 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', - 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', - 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', - 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', - 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', - 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', - 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', - 'SQ_EX_EXCP_ADDR_WATCH', 'SQ_EX_EXCP_ALU_FLOAT_DIV0', - 'SQ_EX_EXCP_ALU_INEXACT', 'SQ_EX_EXCP_ALU_INPUT_DENORM', - 'SQ_EX_EXCP_ALU_INT_DIV0', 'SQ_EX_EXCP_ALU_INVALID', - 'SQ_EX_EXCP_ALU_OVERFLOW', 'SQ_EX_EXCP_ALU_UNDERFLOW', - 'SQ_EX_EXCP_VALU_BASE', 'SQ_EX_EXCP_VALU_SIZE', 'SQ_FLAT', - 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', - 'SQ_GLOBAL', 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', - 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', - 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', - 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', - 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', - 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', - 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', - 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SYS_PRIO', - 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', - 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', - 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', - 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', - 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', - 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', - 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', - 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', - 'SQ_INST_TYPE_DUAL_VALU', 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_FLAT', - 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', - 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', - 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', - 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', - 'SQ_INST_TYPE_VALU_MATRIX', 'SQ_LLC_0', 'SQ_LLC_1', - 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', - 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', - 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', - 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_INTERNAL', - 'SQ_NO_INST_ISSUE_NO_ARB_WIN', 'SQ_NO_INST_ISSUE_NO_INSTS', - 'SQ_NO_INST_ISSUE_OTHER', 'SQ_NO_INST_ISSUE_SLEEP_WAIT', - 'SQ_NO_INST_ISSUE_S_WAITCNT', 'SQ_OOB_COMPLETE', - 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', - 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', - 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', - 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', - 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', - 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', - 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BARRIER_LOCK', - 'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE', - 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', - 'SQ_PERF_SEL_INSTS_EXP_MRT', 'SQ_PERF_SEL_INSTS_EXP_Z', - 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC', - 'SQ_PERF_SEL_INSTS_FLAT_LOAD', 'SQ_PERF_SEL_INSTS_FLAT_STORE', - 'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH', 'SQ_PERF_SEL_INSTS_INTERNAL', - 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_LOCK', - 'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED', - 'SQ_PERF_SEL_INSTS_SALU', 'SQ_PERF_SEL_INSTS_SALU_CS', - 'SQ_PERF_SEL_INSTS_SALU_FLOAT', 'SQ_PERF_SEL_INSTS_SALU_GS', - 'SQ_PERF_SEL_INSTS_SALU_HS', 'SQ_PERF_SEL_INSTS_SALU_PS', - 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', - 'SQ_PERF_SEL_INSTS_SMEM_CS', 'SQ_PERF_SEL_INSTS_SMEM_GS', - 'SQ_PERF_SEL_INSTS_SMEM_HS', 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 'SQ_PERF_SEL_INSTS_SMEM_PS', 'SQ_PERF_SEL_INSTS_TEX', - 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN', - 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN', - 'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD', - 'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE', 'SQ_PERF_SEL_INSTS_TEX_LOAD', - 'SQ_PERF_SEL_INSTS_TEX_SAMPLE', 'SQ_PERF_SEL_INSTS_TEX_STORE', - 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 'SQ_PERF_SEL_INSTS_VALU_COISSUE', 'SQ_PERF_SEL_INSTS_VALU_DP', - 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT', - 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT', - 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 'SQ_PERF_SEL_INSTS_VALU_VINTERP', 'SQ_PERF_SEL_INSTS_VEC32', - 'SQ_PERF_SEL_INSTS_VEC32_FLAT', - 'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC', - 'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE', - 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH', - 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC', - 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE', - 'SQ_PERF_SEL_INSTS_VEC32_LDS', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE', - 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS', - 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE', - 'SQ_PERF_SEL_INSTS_VEC32_TEX', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_CS', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_GS', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_HS', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_PS', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE', - 'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE', - 'SQ_PERF_SEL_INSTS_VEC32_VALU', 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_GS', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_HS', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_PS', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP', - 'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA', - 'SQ_PERF_SEL_INSTS_VGPR_ALLOC', - 'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL', 'SQ_PERF_SEL_INSTS_WAKEUP', - 'SQ_PERF_SEL_INSTS_WMMA_LOAD', 'SQ_PERF_SEL_INST_BARRIER_STALL', - 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', - 'SQ_PERF_SEL_INST_CYCLES_FLAT', 'SQ_PERF_SEL_INST_CYCLES_LDS', - 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', - 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 'SQ_PERF_SEL_INST_ISSUE_ALL_STALL', - 'SQ_PERF_SEL_INST_ISSUE_EXP_STALL', - 'SQ_PERF_SEL_INST_ISSUE_LDS_STALL', - 'SQ_PERF_SEL_INST_ISSUE_SALU_STALL', - 'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL', - 'SQ_PERF_SEL_INST_ISSUE_TEX_STALL', - 'SQ_PERF_SEL_INST_ISSUE_VALU_STALL', 'SQ_PERF_SEL_INST_LEVEL_EXP', - 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', - 'SQ_PERF_SEL_INST_WAITCNT_STALL', 'SQ_PERF_SEL_IS_CACHE_DUP_MISS', - 'SQ_PERF_SEL_IS_CACHE_MISS', 'SQ_PERF_SEL_IS_CACHE_REQ', - 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_ITEMS_MAX_VALU', - 'SQ_PERF_SEL_ITEMS_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', - 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', - 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', - 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 'SQ_PERF_SEL_SP_CONST_CYCLES', - 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', - 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', - 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', - 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', - 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', - 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', - 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', - 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', - 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', - 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', - 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', - 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', - 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', - 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', - 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 'SQ_PERF_SEL_VALU_RETURN_SDST', - 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VEC32_INSTS_EXP', - 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 'SQ_PERF_SEL_VMEM_BUS_STALL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', - 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_DS', - 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_KM', - 'SQ_PERF_SEL_WAIT_CNT_LOAD', 'SQ_PERF_SEL_WAIT_CNT_SAMPLE', - 'SQ_PERF_SEL_WAIT_CNT_STORE', 'SQ_PERF_SEL_WAIT_DELAY_ALU', - 'SQ_PERF_SEL_WAIT_DEPCTR', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', - 'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP', - 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVE32_INSTS', - 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', - 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', - 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', - 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', - 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', - 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', - 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', - 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', - 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', - 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', - 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', - 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', - 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', - 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', - 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', - 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', - 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', - 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', - 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', - 'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', - 'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', - 'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1', - 'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2', - 'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8', - 'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', - 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', - 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 'SQ_TEX_DEPTH_COMPARE_GREATER', - 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', - 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', - 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', - 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', - 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', - 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', - 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', - 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', - 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', - 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', - 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', 'SQ_WATCH_MODES', - 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', - 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', - 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', - 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', - 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', - 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', - 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', - 'SQ_WAVE_SCHED_MODES', - 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC', - 'SQ_WAVE_SCHED_MODE_EXPERT', 'SQ_WAVE_SCHED_MODE_NORMAL', - 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_GS', - 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', - 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3', - 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', 'SQ_WAVE_TYPE_RSVD2', - 'STALL', 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', - 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', - 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', - 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', - 'STREAM_0_SYNCHRONIZATION', - 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_10_SYNCHRONIZATION', - 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION', - 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION', - 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION', - 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION', - 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION', - 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_1_SYNCHRONIZATION', - 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_2_SYNCHRONIZATION', - 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_3_SYNCHRONIZATION', - 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_4_SYNCHRONIZATION', - 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION', - 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION', - 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION', - 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION', - 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION', - 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'STRM_PERFMON_STATE_RESERVED_3', - 'STRM_PERFMON_STATE_START_COUNTING', - 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', - 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', - 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', - 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', - 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', - 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', - 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', - 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', - 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', - 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', - 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', - 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', - 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', - 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLED', - 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', - 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', - 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', - 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', - 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', - 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', - 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', - 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', - 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', - 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', - 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', - 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', - 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', - 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', - 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', - 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', - 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', - 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', - 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', - 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', - 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', - 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', - 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', - 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', - 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', - 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', - 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', - 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', - 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', - 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', - 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', - 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', - 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', - 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', - 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', - 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', - 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', - 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', - 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', - 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', - 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', - 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', - 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', - 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', - 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', - 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', - 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', - 'SYMCLK_FE_SRC', 'SYMCLK_FE_SRC_RESERVED', - 'SYMCLK_FE_SRC_UNIPHYA', 'SYMCLK_FE_SRC_UNIPHYB', - 'SYMCLK_FE_SRC_UNIPHYC', 'SYMCLK_FE_SRC_UNIPHYD', 'ScMap', - 'ScUncertaintyRegionMode', 'ScUncertaintyRegionMult', 'ScXsel', - 'ScYsel', 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', - 'SeXsel', 'SeYsel', 'StencilOp', 'TA_PERFCOUNT_SEL', - 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', - 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 'TA_PERF_SEL_addresser_stalled_cycles', - 'TA_PERF_SEL_aligner_busy', - 'TA_PERF_SEL_aligner_clk_valid_cycles', - 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', - 'TA_PERF_SEL_aniso_12_cycle_quads', - 'TA_PERF_SEL_aniso_14_cycle_quads', - 'TA_PERF_SEL_aniso_16_cycle_quads', - 'TA_PERF_SEL_aniso_1_cycle_quads', - 'TA_PERF_SEL_aniso_2_cycle_quads', - 'TA_PERF_SEL_aniso_4_cycle_quads', - 'TA_PERF_SEL_aniso_6_cycle_quads', - 'TA_PERF_SEL_aniso_8_cycle_quads', - 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 'TA_PERF_SEL_aniso_stalled_cycles', - 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_write_data_input_cycles', - 'TA_PERF_SEL_atomic_write_data_output_cycles', - 'TA_PERF_SEL_bf_busy', - 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_atomic_wavefronts', - 'TA_PERF_SEL_buffer_flat_1_op_burst', - 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 'TA_PERF_SEL_buffer_has_index_instructions', - 'TA_PERF_SEL_buffer_has_offset_instructions', - 'TA_PERF_SEL_buffer_load_wavefronts', - 'TA_PERF_SEL_buffer_store_wavefronts', - 'TA_PERF_SEL_buffer_total_cycles', - 'TA_PERF_SEL_buffer_wavefronts', - 'TA_PERF_SEL_color_1_cycle_quads', - 'TA_PERF_SEL_color_2_cycle_quads', - 'TA_PERF_SEL_color_3_cycle_quads', - 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 'TA_PERF_SEL_deriv_stalled_cycles', - 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_flat_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_flat_atomic_wavefronts', - 'TA_PERF_SEL_flat_load_wavefronts', - 'TA_PERF_SEL_flat_store_wavefronts', - 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', - 'TA_PERF_SEL_gradient_busy', - 'TA_PERF_SEL_gradient_clk_valid_cycles', - 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', - 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 'TA_PERF_SEL_ibubble_1_cycle_burst', - 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 'TA_PERF_SEL_image_atomic_wavefronts', - 'TA_PERF_SEL_image_linked_1_op_burst', - 'TA_PERF_SEL_image_linked_2to3_op_burst', - 'TA_PERF_SEL_image_linked_4to7_op_burst', - 'TA_PERF_SEL_image_linked_ge8_op_burst', - 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_1_op_burst', - 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 'TA_PERF_SEL_image_nosampler_total_cycles', - 'TA_PERF_SEL_image_read_wavefronts', - 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_op_burst', - 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 'TA_PERF_SEL_image_sampler_has_q_instructions', - 'TA_PERF_SEL_image_sampler_has_r_instructions', - 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 'TA_PERF_SEL_image_sampler_has_t_instructions', - 'TA_PERF_SEL_image_sampler_total_cycles', - 'TA_PERF_SEL_image_sampler_wavefronts', - 'TA_PERF_SEL_image_store_wavefronts', - 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', - 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', - 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', - 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', - 'TA_PERF_SEL_in_waiting_on_req_cycles', - 'TA_PERF_SEL_in_wfifo_busy', - 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', - 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', - 'TA_PERF_SEL_mip_2_cycle_quads', - 'TA_PERF_SEL_mipmap_invalid_samples', - 'TA_PERF_SEL_mipmap_lod_0_samples', - 'TA_PERF_SEL_mipmap_lod_10_samples', - 'TA_PERF_SEL_mipmap_lod_11_samples', - 'TA_PERF_SEL_mipmap_lod_12_samples', - 'TA_PERF_SEL_mipmap_lod_13_samples', - 'TA_PERF_SEL_mipmap_lod_14_samples', - 'TA_PERF_SEL_mipmap_lod_15_samples', - 'TA_PERF_SEL_mipmap_lod_16_samples', - 'TA_PERF_SEL_mipmap_lod_1_samples', - 'TA_PERF_SEL_mipmap_lod_2_samples', - 'TA_PERF_SEL_mipmap_lod_3_samples', - 'TA_PERF_SEL_mipmap_lod_4_samples', - 'TA_PERF_SEL_mipmap_lod_5_samples', - 'TA_PERF_SEL_mipmap_lod_6_samples', - 'TA_PERF_SEL_mipmap_lod_7_samples', - 'TA_PERF_SEL_mipmap_lod_8_samples', - 'TA_PERF_SEL_mipmap_lod_9_samples', - 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 'TA_PERF_SEL_point_sampled_quads', - 'TA_PERF_SEL_register_clk_valid_cycles', - 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 'TA_PERF_SEL_sampler_clk_valid_cycles', - 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', - 'TA_PERF_SEL_smp_idle_ns_busy', - 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_has_w_instructions', - 'TA_PERF_SEL_store_has_x_instructions', - 'TA_PERF_SEL_store_has_y_instructions', - 'TA_PERF_SEL_store_has_z_instructions', - 'TA_PERF_SEL_store_write_data_input_cycles', - 'TA_PERF_SEL_store_write_data_output_cycles', - 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', - 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', - 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', - 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', - 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', - 'TA_PERF_SEL_write_4to31_op_burst', - 'TA_PERF_SEL_write_data_clk_valid_cycles', - 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', - 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', - 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', - 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', - 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', - 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', - 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', - 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', - 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TCC_MTYPE', - 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', - 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', - 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', - 'TCP_CACHE_STORE_POLICY_WT_EVICT', - 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_COMPRESSION_BYPASS', - 'TCP_COMPRESSION_BYPASS_DIS', 'TCP_COMPRESSION_BYPASS_EN', - 'TCP_COMPRESSION_OVERRIDE', 'TCP_COMPRESSION_OVERRIDE_DIS', - 'TCP_COMPRESSION_OVERRIDE_EN', 'TCP_OPCODE_ATOMIC', - 'TCP_OPCODE_ATOMIC_CMPSWAP', 'TCP_OPCODE_GATHERH', - 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', 'TCP_OPCODE_READ', - 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', 'TCP_OPCODE_WRITE', - 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL', - 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 'TCP_PERF_SEL_BURST_BIN_READHIT_0', - 'TCP_PERF_SEL_BURST_BIN_READHIT_1', - 'TCP_PERF_SEL_BURST_BIN_READHIT_2to4', - 'TCP_PERF_SEL_BURST_BIN_READHIT_5to8', - 'TCP_PERF_SEL_BURST_BIN_READHIT_9to16', - 'TCP_PERF_SEL_BURST_BIN_READHIT_gt16', - 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0', - 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2', - 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4', - 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8', - 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16', - 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', - 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_GL1_REQ_LU', - 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', - 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', - 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 'TCP_PERF_SEL_POWER_STALL', - 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', - 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', - 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', - 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE', - 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID', - 'TCP_PERF_SEL_REQ_WRITE', 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 'TCP_PERF_SEL_TAGFAKE_EOW', 'TCP_PERF_SEL_TA_REQ', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_TA_REQ_BUFFERNOP', 'TCP_PERF_SEL_TA_REQ_GL0_INV', - 'TCP_PERF_SEL_TA_REQ_READ', 'TCP_PERF_SEL_TA_REQ_STATE_READ', - 'TCP_PERF_SEL_TA_REQ_WRITE', 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', - 'TCP_PERF_SEL_TA_TC_REQ_EN_SUM', 'TCP_PERF_SEL_TCP_LATENCY', - 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', - 'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE', - 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', - 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', - 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', - 'TCP_WRITE_COMPRESSION_DISABLE', - 'TCP_WRITE_COMPRESSION_DISABLE_DIS', - 'TCP_WRITE_COMPRESSION_DISABLE_EN', 'TC_EA_CID', 'TC_EA_CID_CPF', - 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', 'TC_EA_CID_FMASK', - 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', 'TC_EA_CID_MISC', - 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', - 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', - 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', - 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', - 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', - 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', - 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', - 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', - 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', - 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', - 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', - 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', - 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', - 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', - 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', - 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', - 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', - 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', - 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', - 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', - 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', - 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', - 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', - 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', - 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', - 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', - 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', - 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', - 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', - 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', - 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', - 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', - 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', - 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', - 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', - 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', - 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', - 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', - 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', - 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', - 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', - 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', - 'TC_OP_RESERVED_NON_FLOAT_64_4', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', - 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', - 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', - 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', - 'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad', - 'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit', - 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 'TD_PERF_SEL_box_non_opaque_culled', - 'TD_PERF_SEL_box_opaque_culled', - 'TD_PERF_SEL_box_with_procedural_children_only_culled', - 'TD_PERF_SEL_box_with_triangle_children_only_culled', - 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 'TD_PERF_SEL_burst_bin_gather_1', - 'TD_PERF_SEL_burst_bin_gather_2to8', - 'TD_PERF_SEL_burst_bin_gather_9to16', - 'TD_PERF_SEL_burst_bin_gather_gt16', - 'TD_PERF_SEL_burst_bin_nofilter_1', - 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_sampler_1', - 'TD_PERF_SEL_burst_bin_sampler_2to8', - 'TD_PERF_SEL_burst_bin_sampler_9to16', - 'TD_PERF_SEL_burst_bin_sampler_gt16', - 'TD_PERF_SEL_bypassLerp_instr', - 'TD_PERF_SEL_core_state_ram_max_cnt', - 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 'TD_PERF_SEL_done_scoreboard_is_full', - 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 'TD_PERF_SEL_done_scoreboard_not_empty', - 'TD_PERF_SEL_four_comp_return_instr', - 'TD_PERF_SEL_gather4_2x_instr', 'TD_PERF_SEL_gather4_instr', - 'TD_PERF_SEL_gather4h_2x_instr', 'TD_PERF_SEL_gather4h_instr', - 'TD_PERF_SEL_getlod_2x_instr', 'TD_PERF_SEL_getlod_instr', - 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', - 'TD_PERF_SEL_instance_mask_culled', - 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_lds_stall', - 'TD_PERF_SEL_load_instr', 'TD_PERF_SEL_lod_warn_from_ta', - 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', - 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', - 'TD_PERF_SEL_nofilter_busy', - 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 'TD_PERF_SEL_nofilter_d16_sclk_en', - 'TD_PERF_SEL_nofilter_d32_sclk_en', - 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 'TD_PERF_SEL_nofilter_formatters_turned_on', - 'TD_PERF_SEL_nofilter_insert_extra_comps', - 'TD_PERF_SEL_nofilter_pkr_full', - 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_sclk_en', - 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', - 'TD_PERF_SEL_one_comp_return_instr', - 'TD_PERF_SEL_opaque_black_border', - 'TD_PERF_SEL_out_of_order_instr', - 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 'TD_PERF_SEL_prt_ack_instr', 'TD_PERF_SEL_ps_load_instr', - 'TD_PERF_SEL_reference_data_rams_read', - 'TD_PERF_SEL_resmap_2x_instr', 'TD_PERF_SEL_resmap_instr', - 'TD_PERF_SEL_resmap_with_aniso_filtering', - 'TD_PERF_SEL_resmap_with_cubemap_corner', - 'TD_PERF_SEL_resmap_with_no_more_filtering', - 'TD_PERF_SEL_resmap_with_volume_filtering', - 'TD_PERF_SEL_sample_2x_instr', 'TD_PERF_SEL_sample_c_instr', - 'TD_PERF_SEL_sample_instr', 'TD_PERF_SEL_sampler_accum_sclk_en', - 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 'TD_PERF_SEL_sampler_bypass_sclk_en', - 'TD_PERF_SEL_sampler_core_sclk_en', - 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 'TD_PERF_SEL_sampler_lerp0_active', - 'TD_PERF_SEL_sampler_lerp1_active', - 'TD_PERF_SEL_sampler_lerp2_active', - 'TD_PERF_SEL_sampler_lerp3_active', - 'TD_PERF_SEL_sampler_lerp4_active', - 'TD_PERF_SEL_sampler_lerp5_active', - 'TD_PERF_SEL_sampler_lerp6_active', - 'TD_PERF_SEL_sampler_lerp7_active', - 'TD_PERF_SEL_sampler_lerp_busy', - 'TD_PERF_SEL_sampler_minmax_sclk_en', - 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', - 'TD_PERF_SEL_sampler_pkr_full', - 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_preempts_a_load', - 'TD_PERF_SEL_ta_data_stall', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', - 'TD_PERF_SEL_tc_td_data_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_three_comp_return_instr', - 'TD_PERF_SEL_total_num_instr', - 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_nofilter_instr', - 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_sampler_instr', - 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 'TD_PERF_SEL_tri_proc_node_override_slot0', - 'TD_PERF_SEL_tri_proc_node_override_slot1', - 'TD_PERF_SEL_tri_run_ahs_slot0', 'TD_PERF_SEL_tri_run_ahs_slot1', - 'TD_PERF_SEL_tri_run_intersect_ahs_slot0', - 'TD_PERF_SEL_tri_run_intersect_ahs_slot1', - 'TD_PERF_SEL_triangle_back_facing_culled', - 'TD_PERF_SEL_triangle_front_facing_culled', - 'TD_PERF_SEL_triangle_non_opaque_culled', - 'TD_PERF_SEL_triangle_opaque_culled', - 'TD_PERF_SEL_two_comp_return_instr', - 'TD_PERF_SEL_user_defined_border', - 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', - 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', - 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', - 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', - 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', - 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_D', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', - 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', - 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', - 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', - 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', - 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', - 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', - 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', - 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', - 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', - 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', - 'TEX_Clamp_MirrorOnceHalfToBorder', - 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', - 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', - 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', - 'TEX_DepthCompareFunction_Always', - 'TEX_DepthCompareFunction_Equal', - 'TEX_DepthCompareFunction_Greater', - 'TEX_DepthCompareFunction_GreaterEqual', - 'TEX_DepthCompareFunction_Less', - 'TEX_DepthCompareFunction_LessEqual', - 'TEX_DepthCompareFunction_Never', - 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', - 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', - 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', - 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', - 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', - 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', - 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', - 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', - 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', - 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', - 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', - 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', - 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', - 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', - 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', - 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', - 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', - 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', - 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', - 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TMDS_COLOR_FORMAT', - 'TMDS_COLOR_FORMAT_DUAL30BPP', 'TMDS_COLOR_FORMAT_RESERVED', - 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', - 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', - 'TMDS_CTL0_DATA_MODULATION_BIT1', - 'TMDS_CTL0_DATA_MODULATION_BIT2', - 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', - 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', - 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', - 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', - 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', - 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', - 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', - 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', - 'TMDS_CTL1_DATA_MODULATION_BIT0', - 'TMDS_CTL1_DATA_MODULATION_BIT1', - 'TMDS_CTL1_DATA_MODULATION_BIT2', - 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', - 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', - 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', - 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', - 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', - 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', - 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', - 'TMDS_CTL2_DATA_MODULATION_BIT0', - 'TMDS_CTL2_DATA_MODULATION_BIT1', - 'TMDS_CTL2_DATA_MODULATION_BIT2', - 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', - 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', - 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', - 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', - 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', - 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', - 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', - 'TMDS_CTL3_DATA_MODULATION_BIT0', - 'TMDS_CTL3_DATA_MODULATION_BIT1', - 'TMDS_CTL3_DATA_MODULATION_BIT2', - 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', - 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', - 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', - 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', - 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', - 'TMDS_CTL3_PATTERN_OUT_ENABLE', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_DVI_MODE', - 'TMDS_HDMI_MODE', 'TMDS_MUX_SELECT', 'TMDS_MUX_SELECT_B', - 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', - 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', - 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', - 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', - 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', - 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', - 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', - 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', - 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', - 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', - 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', - 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', - 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', - 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', - 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', - 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', - 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', - 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', - 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', - 'UCONFIG_SPACE_START', 'UNDEF', 'UNSIGNED', 'UTCL0FaultType', - 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL', - 'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', - 'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', - 'UTCL1PerfSel', 'UTCL1RequestType', - 'UTCL1_PERF_SEL_ALOG_CACHE_HIT', 'UTCL1_PERF_SEL_ALOG_CACHE_REQ', - 'UTCL1_PERF_SEL_ALOG_INTERRUPT', - 'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED', - 'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS', - 'UTCL1_PERF_SEL_AVG_INV_LATENCY', 'UTCL1_PERF_SEL_BYPASS_REQS', - 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0', - 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1', - 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2', - 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3', 'UTCL1_PERF_SEL_HITS', - 'UTCL1_PERF_SEL_HITS_PG_SIZE_1', 'UTCL1_PERF_SEL_HITS_PG_SIZE_2', - 'UTCL1_PERF_SEL_HITS_PG_SIZE_3', 'UTCL1_PERF_SEL_HITS_PG_SIZE_4', - 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', - 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', - 'UTCL1_PERF_SEL_NONE', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2', - 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K', - 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M', - 'UTCL1_PERF_SEL_RANGE_INVREQS', 'UTCL1_PERF_SEL_REQS', - 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0', - 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1', - 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2', - 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3', - 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0', - 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1', - 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2', - 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3', 'UTCL1_PERF_SEL_RTNS', - 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0', - 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1', - 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2', - 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3', - 'UTCL1_PERF_SEL_STALL_MH_FULL', - 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', - 'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS', - 'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS', 'UTCL1_PERF_SEL_UTCL2_REQS', - 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM', - 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', - 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', - 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', - 'UTCL1_XNACK_SUCCESS', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', - 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_PRIM_TYPE', - 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', - 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', - 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', - 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', - 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', - 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', - 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', - 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', - 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', - 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', - 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', - 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', - 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', - 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', - 'VGT_OUT_2D_RECT', 'VGT_OUT_DUMMY_1', 'VGT_OUT_DUMMY_2', - 'VGT_OUT_DUMMY_3', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', - 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', - 'VGT_OUT_RECT_V0', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', - 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', - 'VGT_RDREQ_POLICY', 'VGT_SPEC_DATA_READ', - 'VGT_SPEC_DATA_READ_AUTO', 'VGT_SPEC_DATA_READ_FORCE_OFF', - 'VGT_SPEC_DATA_READ_FORCE_ON', 'VGT_STAGES_GS_EN', - 'VGT_STAGES_HS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', - 'VGT_TEMPORAL', 'VGT_TEMPORAL_DISCARD', - 'VGT_TEMPORAL_HIGH_PRIORITY', 'VGT_TEMPORAL_NORMAL', - 'VGT_TEMPORAL_STREAM', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', - 'VGT_TESS_TYPE', 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', - 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', - 'VMID_SZ', 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', - 'VM_GROUP_SIZE', 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', - 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', - 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_128KB', 'VM_PG_SIZE_128MB', - 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_16MB', 'VM_PG_SIZE_1MB', - 'VM_PG_SIZE_256KB', 'VM_PG_SIZE_2MB', 'VM_PG_SIZE_32KB', - 'VM_PG_SIZE_32MB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_4MB', - 'VM_PG_SIZE_512KB', 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_64MB', - 'VM_PG_SIZE_8KB', 'VM_PG_SIZE_8MB', - 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', - 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', - 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', - 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', - 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', - 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', - 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', - 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', - 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', - 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', - 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', - 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', - 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', - 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', - 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', 'VTG_SEL_0', - 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5', - 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', - 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', - 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE', - 'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC', - 'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 'WD_IA_DRAW_REG_XFER_GE_VRS_RATE', - 'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL', - 'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS', - 'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL', - 'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE', - 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN', - 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET', - 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE', 'WD_IA_DRAW_SOURCE', - 'WD_IA_DRAW_SOURCE_AUTO', 'WD_IA_DRAW_SOURCE_DMA', - 'WD_IA_DRAW_SOURCE_IMMD', 'WD_IA_DRAW_SOURCE_OPAQ', - 'WD_IA_DRAW_TYPE', 'WD_IA_DRAW_TYPE_DI_MM0', - 'WD_IA_DRAW_TYPE_EVENT_ADDR', 'WD_IA_DRAW_TYPE_EVENT_INIT', - 'WD_IA_DRAW_TYPE_IMM_DATA', 'WD_IA_DRAW_TYPE_INDX_OFF', - 'WD_IA_DRAW_TYPE_MAX_INDX', 'WD_IA_DRAW_TYPE_MIN_INDX', - 'WD_IA_DRAW_TYPE_REG_XFER', 'WRITE_BASE_ONLY', 'WRITE_BOTH', - 'WRITE_COMPRESSION_MODE', 'WritePolicy', 'XNORM', 'XNORM_A', - 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', - 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', - 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', - 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', - 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', - 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', - 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', - 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', - 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', - 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', - 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', - 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', - 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', - 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', - 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', - '_soc24_ENUM_HEADER', 'ge1_assembler_busy', - 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', - 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', - 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', - 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', - 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', - 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', - 'ge1_dma_utcl1_consecutive_retry_event', - 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', - 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', - 'ge1_dma_utcl1_translation_hit_event', - 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', - 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', - 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', - 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', - 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', - 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', - 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', - 'ge1_small_draws_one_instance', 'ge1_stat_busy', - 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', - 'ge_agm_gcr_combine', 'ge_agm_gcr_crd_stall', - 'ge_agm_gcr_latency', 'ge_agm_gcr_req', 'ge_agm_gcr_req_amount', - 'ge_agm_gcr_req_outstanding', 'ge_agm_gcr_stall', - 'ge_agm_gcr_tag_stall', 'ge_all_tf2', 'ge_all_tf3', 'ge_all_tf4', - 'ge_all_tf5', 'ge_all_tf6', 'ge_all_tf_eq', 'ge_csb_spi_bp', - 'ge_dist_distributer_busy', 'ge_dist_hs_done', - 'ge_dist_hs_done_latency', 'ge_dist_hs_done_latency_se0', - 'ge_dist_hs_done_latency_se1', 'ge_dist_hs_done_latency_se2', - 'ge_dist_hs_done_latency_se3', 'ge_dist_hs_done_latency_se4', - 'ge_dist_hs_done_latency_se5', 'ge_dist_hs_done_latency_se6', - 'ge_dist_hs_done_latency_se7', 'ge_dist_hs_done_se0', - 'ge_dist_hs_done_se1', 'ge_dist_hs_done_se2', - 'ge_dist_hs_done_se3', 'ge_dist_hs_done_se4', - 'ge_dist_hs_done_se5', 'ge_dist_hs_done_se6', - 'ge_dist_hs_done_se7', 'ge_dist_indx_fifos_full_and_empty', - 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', - 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', - 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', - 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', - 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', - 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', - 'ge_dist_pc_ge_manager_busy', 'ge_dist_sclk_core_vld', - 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', - 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', - 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', - 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', - 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', - 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', - 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 'ge_dist_tfreq_utcl1_request_event', - 'ge_dist_tfreq_utcl1_retry_event', - 'ge_dist_tfreq_utcl1_stall_event', - 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 'ge_dist_tfreq_utcl1_translation_hit_event', - 'ge_dist_tfreq_utcl1_translation_miss_event', - 'ge_dist_wd_te11_busy', 'ge_distclk_vld', 'ge_esvert_send', - 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', - 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', - 'ge_hs_done_all_tf0_se0', 'ge_hs_done_all_tf0_se1', - 'ge_hs_done_all_tf0_se2', 'ge_hs_done_all_tf0_se3', - 'ge_hs_done_all_tf0_se4', 'ge_hs_done_all_tf0_se5', - 'ge_hs_done_all_tf0_se6', 'ge_hs_done_all_tf0_se7', - 'ge_hs_done_all_tf1_se0', 'ge_hs_done_all_tf1_se1', - 'ge_hs_done_all_tf1_se2', 'ge_hs_done_all_tf1_se3', - 'ge_hs_done_all_tf1_se4', 'ge_hs_done_all_tf1_se5', - 'ge_hs_done_all_tf1_se6', 'ge_hs_done_all_tf1_se7', - 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', - 'ge_merge_gsgrp_rdy_pending_verts', - 'ge_merge_hsgrp_rdy_pending_verts', 'ge_merge_hsgs_fifo_blocked', - 'ge_merge_hsgs_grp_switch', 'ge_merge_hsgs_vert_switch', - 'ge_merge_lses_fifo_blocked', 'ge_merge_lses_vert_switch', - 'ge_merged_hsgs_grp_stalled', 'ge_merged_hsgs_vert_stalled', - 'ge_merged_lses_vert_stalled', 'ge_ngg_agm_req_stall', - 'ge_ngg_attr_discard_alloc', 'ge_ngg_attr_grp_alloc', - 'ge_ngg_attr_grp_latency', 'ge_ngg_attr_grp_wasted', - 'ge_ngg_attr_null_dealloc', 'ge_ngg_busy_base', - 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', - 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', - 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', - 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', - 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', - 'ge_ngg_starved_idle', 'ge_ngg_starving_for_wave_id', - 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', - 'ge_num_of_hs_dealloc_events', 'ge_num_of_no_dist_patches', - 'ge_num_of_patch_dist_patches', - 'ge_num_of_se_switches_due_to_donut', - 'ge_num_of_se_switches_due_to_patch_accum', - 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', - 'ge_se0_te11_starved_on_hs_done', - 'ge_se1_te11_starved_on_hs_done', - 'ge_se2_te11_starved_on_hs_done', - 'ge_se3_te11_starved_on_hs_done', - 'ge_se4_te11_starved_on_hs_done', - 'ge_se5_te11_starved_on_hs_done', - 'ge_se6_te11_starved_on_hs_done', - 'ge_se7_te11_starved_on_hs_done', 'ge_se_api_ds_verts', - 'ge_se_api_vs_verts', 'ge_se_combined_busy', - 'ge_se_ds_cache_hits', 'ge_se_ds_prims', 'ge_se_es_thread_groups', - 'ge_se_esvert_stalled_gsprim', 'ge_se_hs_input_stall', - 'ge_se_hs_tfm_stall', 'ge_se_hs_tgs_active_high_water_mark', - 'ge_se_hs_thread_groups', 'ge_se_reused_es_indices', - 'ge_se_sclk_input_vld', 'ge_se_sclk_ngg_vld', - 'ge_se_sclk_te11_vld', 'ge_se_sending_vert_or_prim', - 'ge_se_spi_esvert_eov', 'ge_se_spi_esvert_stalled', - 'ge_se_spi_esvert_starved_busy', 'ge_se_spi_esvert_valid', - 'ge_se_spi_gsprim_cont', 'ge_se_spi_gsprim_eov', - 'ge_se_spi_gsprim_stalled', 'ge_se_spi_gsprim_starved_busy', - 'ge_se_spi_gsprim_valid', - 'ge_se_spi_gssubgrp_event_window_active', - 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', - 'ge_se_spi_hsgrp_is_event', 'ge_se_spi_hsgrp_send', - 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', - 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', - 'ge_se_spi_hsvert_valid', 'ge_se_spi_lsvert_eov', - 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', - 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', - 'ge_spi_gsgrp_valid', 'ge_spi_gssubgrp_stalled', - 'ge_spi_hsgrp_spi_stall', 'ge_spi_hsvert_send', - 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lsvert_send', - 'ge_spi_lswave_fifo_full_stall', 'ge_te11_compactor_starved', - 'ge_te11_con_stall', 'ge_tf_ret_data_stalling_hs_done'] diff --git a/tinygrad/tinygrad/runtime/autogen/am/vega10.py b/tinygrad/tinygrad/runtime/autogen/am/vega10.py deleted file mode 100644 index 510fbe6a..00000000 --- a/tinygrad/tinygrad/runtime/autogen/am/vega10.py +++ /dev/null @@ -1,36196 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - - - -_vega10_ENUM_HEADER = True # macro -ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro -SQ_WAVE_TYPE_PS0 = 0x00000000 # macro -SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro -SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro -SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro -SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro -SQIND_WAVE_HWREGS_OFFSET = 0x00000010 # macro -SQIND_WAVE_HWREGS_SIZE = 0x000001f0 # macro -SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro -SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro -SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro -SQIND_WAVE_VGPRS_SIZE = 0x00000100 # macro -SQ_GFXDEC_BEGIN = 0x0000a000 # macro -SQ_GFXDEC_END = 0x0000c000 # macro -SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro -SQDEC_BEGIN = 0x00002300 # macro -SQDEC_END = 0x000023ff # macro -SQPERFSDEC_BEGIN = 0x0000d9c0 # macro -SQPERFSDEC_END = 0x0000da40 # macro -SQPERFDDEC_BEGIN = 0x0000d1c0 # macro -SQPERFDDEC_END = 0x0000d240 # macro -SQGFXUDEC_BEGIN = 0x0000c330 # macro -SQGFXUDEC_END = 0x0000c380 # macro -SQPWRDEC_BEGIN = 0x0000f08c # macro -SQPWRDEC_END = 0x0000f094 # macro -SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro -SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro -SQ_MAX_PGM_SGPRS = 0x00000068 # macro -SQ_MAX_PGM_VGPRS = 0x00000100 # macro -SQ_THREAD_TRACE_TIME_UNIT = 0x00000004 # macro -SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro -SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro -SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro -SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro -SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro -SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro -SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro -SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro -SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro -SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro -SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro -INST_ID_PRIV_START = 0x80000000 # macro -INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro -INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro -INST_ID_HW_TRAP = 0xfffffff2 # macro -INST_ID_KILL_SEQ = 0xfffffff3 # macro -INST_ID_SPI_WREXEC = 0xfffffff4 # macro -INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro -SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro -SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro -SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro -SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro -SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro -SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro -SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro -SQ_EDC_FUE_CNTL_SQ = 0x00000000 # macro -SQ_EDC_FUE_CNTL_LDS = 0x00000001 # macro -SQ_EDC_FUE_CNTL_SIMD0 = 0x00000002 # macro -SQ_EDC_FUE_CNTL_SIMD1 = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SIMD2 = 0x00000004 # macro -SQ_EDC_FUE_CNTL_SIMD3 = 0x00000005 # macro -SQ_EDC_FUE_CNTL_TA = 0x00000006 # macro -SQ_EDC_FUE_CNTL_TD = 0x00000007 # macro -SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro -CSDATA_TYPE_WIDTH = 0x00000002 # macro -CSDATA_ADDR_WIDTH = 0x00000007 # macro -CSDATA_DATA_WIDTH = 0x00000020 # macro -GSTHREADID_SIZE = 0x00000002 # macro -GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro -GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro -SEM_ECC_ERROR = 0x00000000 # macro -SEM_TRANS_ERROR = 0x00000001 # macro -SEM_FAILED = 0x00000002 # macro -SEM_PASSED = 0x00000003 # macro -IQ_QUEUE_SLEEP = 0x00000000 # macro -IQ_OFFLOAD_RETRY = 0x00000001 # macro -IQ_SCH_WAVE_MSG = 0x00000002 # macro -IQ_SEM_REARM = 0x00000003 # macro -IQ_DEQUEUE_RETRY = 0x00000004 # macro -IQ_INTR_TYPE_PQ = 0x00000000 # macro -IQ_INTR_TYPE_IB = 0x00000001 # macro -IQ_INTR_TYPE_MQD = 0x00000002 # macro -VMID_SZ = 0x00000004 # macro -CONFIG_SPACE_START = 0x00002000 # macro -CONFIG_SPACE_END = 0x00009fff # macro -CONFIG_SPACE1_START = 0x00002000 # macro -CONFIG_SPACE1_END = 0x00002bff # macro -CONFIG_SPACE2_START = 0x00003000 # macro -CONFIG_SPACE2_END = 0x00009fff # macro -UCONFIG_SPACE_START = 0x0000c000 # macro -UCONFIG_SPACE_END = 0x0000ffff # macro -PERSISTENT_SPACE_START = 0x00002c00 # macro -PERSISTENT_SPACE_END = 0x00002fff # macro -CONTEXT_SPACE_START = 0x0000a000 # macro -CONTEXT_SPACE_END = 0x0000bfff # macro -SQ_ENC_SOP1_BITS = 0xbe800000 # macro -SQ_ENC_SOP1_MASK = 0xff800000 # macro -SQ_ENC_SOP1_FIELD = 0x0000017d # macro -SQ_ENC_SOPC_BITS = 0xbf000000 # macro -SQ_ENC_SOPC_MASK = 0xff800000 # macro -SQ_ENC_SOPC_FIELD = 0x0000017e # macro -SQ_ENC_SOPP_BITS = 0xbf800000 # macro -SQ_ENC_SOPP_MASK = 0xff800000 # macro -SQ_ENC_SOPP_FIELD = 0x0000017f # macro -SQ_ENC_SOPK_BITS = 0xb0000000 # macro -SQ_ENC_SOPK_MASK = 0xf0000000 # macro -SQ_ENC_SOPK_FIELD = 0x0000000b # macro -SQ_ENC_SOP2_BITS = 0x80000000 # macro -SQ_ENC_SOP2_MASK = 0xc0000000 # macro -SQ_ENC_SOP2_FIELD = 0x00000002 # macro -SQ_ENC_SMEM_BITS = 0xc0000000 # macro -SQ_ENC_SMEM_MASK = 0xfc000000 # macro -SQ_ENC_SMEM_FIELD = 0x00000030 # macro -SQ_ENC_VOP1_BITS = 0x7e000000 # macro -SQ_ENC_VOP1_MASK = 0xfe000000 # macro -SQ_ENC_VOP1_FIELD = 0x0000003f # macro -SQ_ENC_VOPC_BITS = 0x7c000000 # macro -SQ_ENC_VOPC_MASK = 0xfe000000 # macro -SQ_ENC_VOPC_FIELD = 0x0000003e # macro -SQ_ENC_VOP2_BITS = 0x00000000 # macro -SQ_ENC_VOP2_MASK = 0x80000000 # macro -SQ_ENC_VOP2_FIELD = 0x00000000 # macro -SQ_ENC_VINTRP_BITS = 0xd4000000 # macro -SQ_ENC_VINTRP_MASK = 0xfc000000 # macro -SQ_ENC_VINTRP_FIELD = 0x00000035 # macro -SQ_ENC_VOP3P_BITS = 0xd3800000 # macro -SQ_ENC_VOP3P_MASK = 0xff800000 # macro -SQ_ENC_VOP3P_FIELD = 0x000001a7 # macro -SQ_ENC_VOP3_BITS = 0xd0000000 # macro -SQ_ENC_VOP3_MASK = 0xfc000000 # macro -SQ_ENC_VOP3_FIELD = 0x00000034 # macro -SQ_ENC_DS_BITS = 0xd8000000 # macro -SQ_ENC_DS_MASK = 0xfc000000 # macro -SQ_ENC_DS_FIELD = 0x00000036 # macro -SQ_ENC_MUBUF_BITS = 0xe0000000 # macro -SQ_ENC_MUBUF_MASK = 0xfc000000 # macro -SQ_ENC_MUBUF_FIELD = 0x00000038 # macro -SQ_ENC_MTBUF_BITS = 0xe8000000 # macro -SQ_ENC_MTBUF_MASK = 0xfc000000 # macro -SQ_ENC_MTBUF_FIELD = 0x0000003a # macro -SQ_ENC_MIMG_BITS = 0xf0000000 # macro -SQ_ENC_MIMG_MASK = 0xfc000000 # macro -SQ_ENC_MIMG_FIELD = 0x0000003c # macro -SQ_ENC_EXP_BITS = 0xc4000000 # macro -SQ_ENC_EXP_MASK = 0xfc000000 # macro -SQ_ENC_EXP_FIELD = 0x00000031 # macro -SQ_ENC_FLAT_BITS = 0xdc000000 # macro -SQ_ENC_FLAT_MASK = 0xfc000000 # macro -SQ_ENC_FLAT_FIELD = 0x00000037 # macro -SQ_V_OP3_INTRP_COUNT = 0x0000000c # macro -SQ_SENDMSG_SYSTEM_SIZE = 0x00000003 # macro -SQ_HWREG_ID_SIZE = 0x00000006 # macro -SQ_V_OPC_COUNT = 0x00000100 # macro -SQ_NUM_VGPR = 0x00000100 # macro -SQ_WAITCNT_LGKM_SHIFT = 0x00000008 # macro -SQ_HWREG_ID_SHIFT = 0x00000000 # macro -SQ_EXP_NUM_POS = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VOPC_OFFSET = 0x00000000 # macro -SQ_V_OP3_2IN_OFFSET = 0x00000280 # macro -SQ_XLATE_VOP3_TO_VOP2_OFFSET = 0x00000100 # macro -SQ_EXP_NUM_MRT = 0x00000008 # macro -SQ_NUM_TTMP = 0x00000010 # macro -SQ_SENDMSG_STREAMID_SHIFT = 0x00000008 # macro -SQ_V_OP1_COUNT = 0x00000080 # macro -SQ_WAITCNT_LGKM_SIZE = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VOPC_COUNT = 0x00000100 # macro -SQ_SENDMSG_MSG_SHIFT = 0x00000000 # macro -SQ_V_OP3_3IN_OFFSET = 0x000001c0 # macro -SQ_HWREG_OFFSET_SHIFT = 0x00000006 # macro -SQ_HWREG_SIZE_SHIFT = 0x0000000b # macro -SQ_HWREG_OFFSET_SIZE = 0x00000005 # macro -SQ_V_OP3_3IN_COUNT = 0x000000b0 # macro -SQ_SENDMSG_MSG_SIZE = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VOP1_COUNT = 0x00000080 # macro -SQ_EXP_NUM_GDS = 0x00000005 # macro -SQ_V_OP2_COUNT = 0x00000040 # macro -SQ_SENDMSG_GSOP_SIZE = 0x00000002 # macro -SQ_WAITCNT_VM_SHIFT = 0x00000000 # macro -SQ_XLATE_VOP3_TO_VOP3P_COUNT = 0x00000080 # macro -SQ_V_OP3_2IN_COUNT = 0x00000080 # macro -SQ_SENDMSG_SYSTEM_SHIFT = 0x00000004 # macro -SQ_WAITCNT_VM_SIZE = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VOP3P_OFFSET = 0x00000380 # macro -SQ_WAITCNT_EXP_SHIFT = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VOP2_COUNT = 0x00000040 # macro -SQ_EXP_NUM_PARAM = 0x00000020 # macro -SQ_HWREG_SIZE_SIZE = 0x00000005 # macro -SQ_WAITCNT_EXP_SIZE = 0x00000003 # macro -SQ_V_OP3_INTRP_OFFSET = 0x00000274 # macro -SQ_SENDMSG_GSOP_SHIFT = 0x00000004 # macro -SQ_XLATE_VOP3_TO_VINTRP_OFFSET = 0x00000270 # macro -SQ_NUM_ATTR = 0x00000021 # macro -SQ_NUM_SGPR = 0x00000066 # macro -SQ_SRC_VGPR_BIT = 0x00000100 # macro -SQ_V_INTRP_COUNT = 0x00000004 # macro -SQ_SENDMSG_STREAMID_SIZE = 0x00000002 # macro -SQ_V_OP3P_COUNT = 0x00000080 # macro -SQ_XLATE_VOP3_TO_VOP1_OFFSET = 0x00000140 # macro -SQ_XLATE_VOP3_TO_VINTRP_COUNT = 0x00000004 # macro -SQ_SRC_DPP = 0x000000fa # macro -SQ_TBUFFER_LOAD_FORMAT_X = 0x00000000 # macro -SQ_TBUFFER_LOAD_FORMAT_XY = 0x00000001 # macro -SQ_TBUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro -SQ_TBUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro -SQ_TBUFFER_STORE_FORMAT_X = 0x00000004 # macro -SQ_TBUFFER_STORE_FORMAT_XY = 0x00000005 # macro -SQ_TBUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro -SQ_TBUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro -SQ_TBUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro -SQ_TBUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro -SQ_TBUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro -SQ_TBUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro -SQ_TBUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro -SQ_TBUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro -SQ_TBUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro -SQ_TBUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro -SQ_GLOBAL_LOAD_UBYTE = 0x00000010 # macro -SQ_GLOBAL_LOAD_SBYTE = 0x00000011 # macro -SQ_GLOBAL_LOAD_USHORT = 0x00000012 # macro -SQ_GLOBAL_LOAD_SSHORT = 0x00000013 # macro -SQ_GLOBAL_LOAD_DWORD = 0x00000014 # macro -SQ_GLOBAL_LOAD_DWORDX2 = 0x00000015 # macro -SQ_GLOBAL_LOAD_DWORDX3 = 0x00000016 # macro -SQ_GLOBAL_LOAD_DWORDX4 = 0x00000017 # macro -SQ_GLOBAL_STORE_BYTE = 0x00000018 # macro -SQ_GLOBAL_STORE_SHORT = 0x0000001a # macro -SQ_GLOBAL_STORE_DWORD = 0x0000001c # macro -SQ_GLOBAL_STORE_DWORDX2 = 0x0000001d # macro -SQ_GLOBAL_STORE_DWORDX3 = 0x0000001e # macro -SQ_GLOBAL_STORE_DWORDX4 = 0x0000001f # macro -SQ_GLOBAL_ATOMIC_SWAP = 0x00000040 # macro -SQ_GLOBAL_ATOMIC_CMPSWAP = 0x00000041 # macro -SQ_GLOBAL_ATOMIC_ADD = 0x00000042 # macro -SQ_GLOBAL_ATOMIC_SUB = 0x00000043 # macro -SQ_GLOBAL_ATOMIC_SMIN = 0x00000044 # macro -SQ_GLOBAL_ATOMIC_UMIN = 0x00000045 # macro -SQ_GLOBAL_ATOMIC_SMAX = 0x00000046 # macro -SQ_GLOBAL_ATOMIC_UMAX = 0x00000047 # macro -SQ_GLOBAL_ATOMIC_AND = 0x00000048 # macro -SQ_GLOBAL_ATOMIC_OR = 0x00000049 # macro -SQ_GLOBAL_ATOMIC_XOR = 0x0000004a # macro -SQ_GLOBAL_ATOMIC_INC = 0x0000004b # macro -SQ_GLOBAL_ATOMIC_DEC = 0x0000004c # macro -SQ_GLOBAL_ATOMIC_SWAP_X2 = 0x00000060 # macro -SQ_GLOBAL_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro -SQ_GLOBAL_ATOMIC_ADD_X2 = 0x00000062 # macro -SQ_GLOBAL_ATOMIC_SUB_X2 = 0x00000063 # macro -SQ_GLOBAL_ATOMIC_SMIN_X2 = 0x00000064 # macro -SQ_GLOBAL_ATOMIC_UMIN_X2 = 0x00000065 # macro -SQ_GLOBAL_ATOMIC_SMAX_X2 = 0x00000066 # macro -SQ_GLOBAL_ATOMIC_UMAX_X2 = 0x00000067 # macro -SQ_GLOBAL_ATOMIC_AND_X2 = 0x00000068 # macro -SQ_GLOBAL_ATOMIC_OR_X2 = 0x00000069 # macro -SQ_GLOBAL_ATOMIC_XOR_X2 = 0x0000006a # macro -SQ_GLOBAL_ATOMIC_INC_X2 = 0x0000006b # macro -SQ_GLOBAL_ATOMIC_DEC_X2 = 0x0000006c # macro -SQ_VGPR0 = 0x00000000 # macro -SQ_SCRATCH_LOAD_UBYTE = 0x00000010 # macro -SQ_SCRATCH_LOAD_SBYTE = 0x00000011 # macro -SQ_SCRATCH_LOAD_USHORT = 0x00000012 # macro -SQ_SCRATCH_LOAD_SSHORT = 0x00000013 # macro -SQ_SCRATCH_LOAD_DWORD = 0x00000014 # macro -SQ_SCRATCH_LOAD_DWORDX2 = 0x00000015 # macro -SQ_SCRATCH_LOAD_DWORDX3 = 0x00000016 # macro -SQ_SCRATCH_LOAD_DWORDX4 = 0x00000017 # macro -SQ_SCRATCH_STORE_BYTE = 0x00000018 # macro -SQ_SCRATCH_STORE_SHORT = 0x0000001a # macro -SQ_SCRATCH_STORE_DWORD = 0x0000001c # macro -SQ_SCRATCH_STORE_DWORDX2 = 0x0000001d # macro -SQ_SCRATCH_STORE_DWORDX3 = 0x0000001e # macro -SQ_SCRATCH_STORE_DWORDX4 = 0x0000001f # macro -SQ_VCC_ALL = 0x00000000 # macro -SQ_SRC_0 = 0x00000080 # macro -SQ_SRC_1_INT = 0x00000081 # macro -SQ_SRC_2_INT = 0x00000082 # macro -SQ_SRC_3_INT = 0x00000083 # macro -SQ_SRC_4_INT = 0x00000084 # macro -SQ_SRC_5_INT = 0x00000085 # macro -SQ_SRC_6_INT = 0x00000086 # macro -SQ_SRC_7_INT = 0x00000087 # macro -SQ_SRC_8_INT = 0x00000088 # macro -SQ_SRC_9_INT = 0x00000089 # macro -SQ_SRC_10_INT = 0x0000008a # macro -SQ_SRC_11_INT = 0x0000008b # macro -SQ_SRC_12_INT = 0x0000008c # macro -SQ_SRC_13_INT = 0x0000008d # macro -SQ_SRC_14_INT = 0x0000008e # macro -SQ_SRC_15_INT = 0x0000008f # macro -SQ_SRC_16_INT = 0x00000090 # macro -SQ_SRC_17_INT = 0x00000091 # macro -SQ_SRC_18_INT = 0x00000092 # macro -SQ_SRC_19_INT = 0x00000093 # macro -SQ_SRC_20_INT = 0x00000094 # macro -SQ_SRC_21_INT = 0x00000095 # macro -SQ_SRC_22_INT = 0x00000096 # macro -SQ_SRC_23_INT = 0x00000097 # macro -SQ_SRC_24_INT = 0x00000098 # macro -SQ_SRC_25_INT = 0x00000099 # macro -SQ_SRC_26_INT = 0x0000009a # macro -SQ_SRC_27_INT = 0x0000009b # macro -SQ_SRC_28_INT = 0x0000009c # macro -SQ_SRC_29_INT = 0x0000009d # macro -SQ_SRC_30_INT = 0x0000009e # macro -SQ_SRC_31_INT = 0x0000009f # macro -SQ_SRC_32_INT = 0x000000a0 # macro -SQ_SRC_33_INT = 0x000000a1 # macro -SQ_SRC_34_INT = 0x000000a2 # macro -SQ_SRC_35_INT = 0x000000a3 # macro -SQ_SRC_36_INT = 0x000000a4 # macro -SQ_SRC_37_INT = 0x000000a5 # macro -SQ_SRC_38_INT = 0x000000a6 # macro -SQ_SRC_39_INT = 0x000000a7 # macro -SQ_SRC_40_INT = 0x000000a8 # macro -SQ_SRC_41_INT = 0x000000a9 # macro -SQ_SRC_42_INT = 0x000000aa # macro -SQ_SRC_43_INT = 0x000000ab # macro -SQ_SRC_44_INT = 0x000000ac # macro -SQ_SRC_45_INT = 0x000000ad # macro -SQ_SRC_46_INT = 0x000000ae # macro -SQ_SRC_47_INT = 0x000000af # macro -SQ_SRC_48_INT = 0x000000b0 # macro -SQ_SRC_49_INT = 0x000000b1 # macro -SQ_SRC_50_INT = 0x000000b2 # macro -SQ_SRC_51_INT = 0x000000b3 # macro -SQ_SRC_52_INT = 0x000000b4 # macro -SQ_SRC_53_INT = 0x000000b5 # macro -SQ_SRC_54_INT = 0x000000b6 # macro -SQ_SRC_55_INT = 0x000000b7 # macro -SQ_SRC_56_INT = 0x000000b8 # macro -SQ_SRC_57_INT = 0x000000b9 # macro -SQ_SRC_58_INT = 0x000000ba # macro -SQ_SRC_59_INT = 0x000000bb # macro -SQ_SRC_60_INT = 0x000000bc # macro -SQ_SRC_61_INT = 0x000000bd # macro -SQ_SRC_62_INT = 0x000000be # macro -SQ_SRC_63_INT = 0x000000bf # macro -SQ_IMAGE_LOAD = 0x00000000 # macro -SQ_IMAGE_LOAD_MIP = 0x00000001 # macro -SQ_IMAGE_LOAD_PCK = 0x00000002 # macro -SQ_IMAGE_LOAD_PCK_SGN = 0x00000003 # macro -SQ_IMAGE_LOAD_MIP_PCK = 0x00000004 # macro -SQ_IMAGE_LOAD_MIP_PCK_SGN = 0x00000005 # macro -SQ_IMAGE_STORE = 0x00000008 # macro -SQ_IMAGE_STORE_MIP = 0x00000009 # macro -SQ_IMAGE_STORE_PCK = 0x0000000a # macro -SQ_IMAGE_STORE_MIP_PCK = 0x0000000b # macro -SQ_IMAGE_GET_RESINFO = 0x0000000e # macro -SQ_IMAGE_ATOMIC_SWAP = 0x00000010 # macro -SQ_IMAGE_ATOMIC_CMPSWAP = 0x00000011 # macro -SQ_IMAGE_ATOMIC_ADD = 0x00000012 # macro -SQ_IMAGE_ATOMIC_SUB = 0x00000013 # macro -SQ_IMAGE_ATOMIC_SMIN = 0x00000014 # macro -SQ_IMAGE_ATOMIC_UMIN = 0x00000015 # macro -SQ_IMAGE_ATOMIC_SMAX = 0x00000016 # macro -SQ_IMAGE_ATOMIC_UMAX = 0x00000017 # macro -SQ_IMAGE_ATOMIC_AND = 0x00000018 # macro -SQ_IMAGE_ATOMIC_OR = 0x00000019 # macro -SQ_IMAGE_ATOMIC_XOR = 0x0000001a # macro -SQ_IMAGE_ATOMIC_INC = 0x0000001b # macro -SQ_IMAGE_ATOMIC_DEC = 0x0000001c # macro -SQ_IMAGE_SAMPLE = 0x00000020 # macro -SQ_IMAGE_SAMPLE_CL = 0x00000021 # macro -SQ_IMAGE_SAMPLE_D = 0x00000022 # macro -SQ_IMAGE_SAMPLE_D_CL = 0x00000023 # macro -SQ_IMAGE_SAMPLE_L = 0x00000024 # macro -SQ_IMAGE_SAMPLE_B = 0x00000025 # macro -SQ_IMAGE_SAMPLE_B_CL = 0x00000026 # macro -SQ_IMAGE_SAMPLE_LZ = 0x00000027 # macro -SQ_IMAGE_SAMPLE_C = 0x00000028 # macro -SQ_IMAGE_SAMPLE_C_CL = 0x00000029 # macro -SQ_IMAGE_SAMPLE_C_D = 0x0000002a # macro -SQ_IMAGE_SAMPLE_C_D_CL = 0x0000002b # macro -SQ_IMAGE_SAMPLE_C_L = 0x0000002c # macro -SQ_IMAGE_SAMPLE_C_B = 0x0000002d # macro -SQ_IMAGE_SAMPLE_C_B_CL = 0x0000002e # macro -SQ_IMAGE_SAMPLE_C_LZ = 0x0000002f # macro -SQ_IMAGE_SAMPLE_O = 0x00000030 # macro -SQ_IMAGE_SAMPLE_CL_O = 0x00000031 # macro -SQ_IMAGE_SAMPLE_D_O = 0x00000032 # macro -SQ_IMAGE_SAMPLE_D_CL_O = 0x00000033 # macro -SQ_IMAGE_SAMPLE_L_O = 0x00000034 # macro -SQ_IMAGE_SAMPLE_B_O = 0x00000035 # macro -SQ_IMAGE_SAMPLE_B_CL_O = 0x00000036 # macro -SQ_IMAGE_SAMPLE_LZ_O = 0x00000037 # macro -SQ_IMAGE_SAMPLE_C_O = 0x00000038 # macro -SQ_IMAGE_SAMPLE_C_CL_O = 0x00000039 # macro -SQ_IMAGE_SAMPLE_C_D_O = 0x0000003a # macro -SQ_IMAGE_SAMPLE_C_D_CL_O = 0x0000003b # macro -SQ_IMAGE_SAMPLE_C_L_O = 0x0000003c # macro -SQ_IMAGE_SAMPLE_C_B_O = 0x0000003d # macro -SQ_IMAGE_SAMPLE_C_B_CL_O = 0x0000003e # macro -SQ_IMAGE_SAMPLE_C_LZ_O = 0x0000003f # macro -SQ_IMAGE_GATHER4 = 0x00000040 # macro -SQ_IMAGE_GATHER4_CL = 0x00000041 # macro -SQ_IMAGE_GATHER4H = 0x00000042 # macro -SQ_IMAGE_GATHER4_L = 0x00000044 # macro -SQ_IMAGE_GATHER4_B = 0x00000045 # macro -SQ_IMAGE_GATHER4_B_CL = 0x00000046 # macro -SQ_IMAGE_GATHER4_LZ = 0x00000047 # macro -SQ_IMAGE_GATHER4_C = 0x00000048 # macro -SQ_IMAGE_GATHER4_C_CL = 0x00000049 # macro -SQ_IMAGE_GATHER4H_PCK = 0x0000004a # macro -SQ_IMAGE_GATHER8H_PCK = 0x0000004b # macro -SQ_IMAGE_GATHER4_C_L = 0x0000004c # macro -SQ_IMAGE_GATHER4_C_B = 0x0000004d # macro -SQ_IMAGE_GATHER4_C_B_CL = 0x0000004e # macro -SQ_IMAGE_GATHER4_C_LZ = 0x0000004f # macro -SQ_IMAGE_GATHER4_O = 0x00000050 # macro -SQ_IMAGE_GATHER4_CL_O = 0x00000051 # macro -SQ_IMAGE_GATHER4_L_O = 0x00000054 # macro -SQ_IMAGE_GATHER4_B_O = 0x00000055 # macro -SQ_IMAGE_GATHER4_B_CL_O = 0x00000056 # macro -SQ_IMAGE_GATHER4_LZ_O = 0x00000057 # macro -SQ_IMAGE_GATHER4_C_O = 0x00000058 # macro -SQ_IMAGE_GATHER4_C_CL_O = 0x00000059 # macro -SQ_IMAGE_GATHER4_C_L_O = 0x0000005c # macro -SQ_IMAGE_GATHER4_C_B_O = 0x0000005d # macro -SQ_IMAGE_GATHER4_C_B_CL_O = 0x0000005e # macro -SQ_IMAGE_GATHER4_C_LZ_O = 0x0000005f # macro -SQ_IMAGE_GET_LOD = 0x00000060 # macro -SQ_IMAGE_SAMPLE_CD = 0x00000068 # macro -SQ_IMAGE_SAMPLE_CD_CL = 0x00000069 # macro -SQ_IMAGE_SAMPLE_C_CD = 0x0000006a # macro -SQ_IMAGE_SAMPLE_C_CD_CL = 0x0000006b # macro -SQ_IMAGE_SAMPLE_CD_O = 0x0000006c # macro -SQ_IMAGE_SAMPLE_CD_CL_O = 0x0000006d # macro -SQ_IMAGE_SAMPLE_C_CD_O = 0x0000006e # macro -SQ_IMAGE_SAMPLE_C_CD_CL_O = 0x0000006f # macro -SQ_IMAGE_RSRC256 = 0x0000007e # macro -SQ_IMAGE_SAMPLER = 0x0000007f # macro -SQ_HW_REG_MODE = 0x00000001 # macro -SQ_HW_REG_STATUS = 0x00000002 # macro -SQ_HW_REG_TRAPSTS = 0x00000003 # macro -SQ_HW_REG_HW_ID = 0x00000004 # macro -SQ_HW_REG_GPR_ALLOC = 0x00000005 # macro -SQ_HW_REG_LDS_ALLOC = 0x00000006 # macro -SQ_HW_REG_IB_STS = 0x00000007 # macro -SQ_HW_REG_PC_LO = 0x00000008 # macro -SQ_HW_REG_PC_HI = 0x00000009 # macro -SQ_HW_REG_INST_DW0 = 0x0000000a # macro -SQ_HW_REG_INST_DW1 = 0x0000000b # macro -SQ_HW_REG_IB_DBG0 = 0x0000000c # macro -SQ_HW_REG_IB_DBG1 = 0x0000000d # macro -SQ_HW_REG_FLUSH_IB = 0x0000000e # macro -SQ_HW_REG_SH_MEM_BASES = 0x0000000f # macro -SQ_HW_REG_SQ_SHADER_TBA_LO = 0x00000010 # macro -SQ_HW_REG_SQ_SHADER_TBA_HI = 0x00000011 # macro -SQ_HW_REG_SQ_SHADER_TMA_LO = 0x00000012 # macro -SQ_HW_REG_SQ_SHADER_TMA_HI = 0x00000013 # macro -SQ_S_MOV_B32 = 0x00000000 # macro -SQ_S_MOV_B64 = 0x00000001 # macro -SQ_S_CMOV_B32 = 0x00000002 # macro -SQ_S_CMOV_B64 = 0x00000003 # macro -SQ_S_NOT_B32 = 0x00000004 # macro -SQ_S_NOT_B64 = 0x00000005 # macro -SQ_S_WQM_B32 = 0x00000006 # macro -SQ_S_WQM_B64 = 0x00000007 # macro -SQ_S_BREV_B32 = 0x00000008 # macro -SQ_S_BREV_B64 = 0x00000009 # macro -SQ_S_BCNT0_I32_B32 = 0x0000000a # macro -SQ_S_BCNT0_I32_B64 = 0x0000000b # macro -SQ_S_BCNT1_I32_B32 = 0x0000000c # macro -SQ_S_BCNT1_I32_B64 = 0x0000000d # macro -SQ_S_FF0_I32_B32 = 0x0000000e # macro -SQ_S_FF0_I32_B64 = 0x0000000f # macro -SQ_S_FF1_I32_B32 = 0x00000010 # macro -SQ_S_FF1_I32_B64 = 0x00000011 # macro -SQ_S_FLBIT_I32_B32 = 0x00000012 # macro -SQ_S_FLBIT_I32_B64 = 0x00000013 # macro -SQ_S_FLBIT_I32 = 0x00000014 # macro -SQ_S_FLBIT_I32_I64 = 0x00000015 # macro -SQ_S_SEXT_I32_I8 = 0x00000016 # macro -SQ_S_SEXT_I32_I16 = 0x00000017 # macro -SQ_S_BITSET0_B32 = 0x00000018 # macro -SQ_S_BITSET0_B64 = 0x00000019 # macro -SQ_S_BITSET1_B32 = 0x0000001a # macro -SQ_S_BITSET1_B64 = 0x0000001b # macro -SQ_S_GETPC_B64 = 0x0000001c # macro -SQ_S_SETPC_B64 = 0x0000001d # macro -SQ_S_SWAPPC_B64 = 0x0000001e # macro -SQ_S_RFE_B64 = 0x0000001f # macro -SQ_S_AND_SAVEEXEC_B64 = 0x00000020 # macro -SQ_S_OR_SAVEEXEC_B64 = 0x00000021 # macro -SQ_S_XOR_SAVEEXEC_B64 = 0x00000022 # macro -SQ_S_ANDN2_SAVEEXEC_B64 = 0x00000023 # macro -SQ_S_ORN2_SAVEEXEC_B64 = 0x00000024 # macro -SQ_S_NAND_SAVEEXEC_B64 = 0x00000025 # macro -SQ_S_NOR_SAVEEXEC_B64 = 0x00000026 # macro -SQ_S_XNOR_SAVEEXEC_B64 = 0x00000027 # macro -SQ_S_QUADMASK_B32 = 0x00000028 # macro -SQ_S_QUADMASK_B64 = 0x00000029 # macro -SQ_S_MOVRELS_B32 = 0x0000002a # macro -SQ_S_MOVRELS_B64 = 0x0000002b # macro -SQ_S_MOVRELD_B32 = 0x0000002c # macro -SQ_S_MOVRELD_B64 = 0x0000002d # macro -SQ_S_CBRANCH_JOIN = 0x0000002e # macro -SQ_S_MOV_REGRD_B32 = 0x0000002f # macro -SQ_S_ABS_I32 = 0x00000030 # macro -SQ_S_MOV_FED_B32 = 0x00000031 # macro -SQ_S_SET_GPR_IDX_IDX = 0x00000032 # macro -SQ_S_ANDN1_SAVEEXEC_B64 = 0x00000033 # macro -SQ_S_ORN1_SAVEEXEC_B64 = 0x00000034 # macro -SQ_S_ANDN1_WREXEC_B64 = 0x00000035 # macro -SQ_S_ANDN2_WREXEC_B64 = 0x00000036 # macro -SQ_S_BITREPLICATE_B64_B32 = 0x00000037 # macro -SQ_CNT1 = 0x00000000 # macro -SQ_CNT2 = 0x00000001 # macro -SQ_CNT3 = 0x00000002 # macro -SQ_CNT4 = 0x00000003 # macro -SQ_V_MAD_LEGACY_F32 = 0x000001c0 # macro -SQ_V_MAD_F32 = 0x000001c1 # macro -SQ_V_MAD_I32_I24 = 0x000001c2 # macro -SQ_V_MAD_U32_U24 = 0x000001c3 # macro -SQ_V_CUBEID_F32 = 0x000001c4 # macro -SQ_V_CUBESC_F32 = 0x000001c5 # macro -SQ_V_CUBETC_F32 = 0x000001c6 # macro -SQ_V_CUBEMA_F32 = 0x000001c7 # macro -SQ_V_BFE_U32 = 0x000001c8 # macro -SQ_V_BFE_I32 = 0x000001c9 # macro -SQ_V_BFI_B32 = 0x000001ca # macro -SQ_V_FMA_F32 = 0x000001cb # macro -SQ_V_FMA_F64 = 0x000001cc # macro -SQ_V_LERP_U8 = 0x000001cd # macro -SQ_V_ALIGNBIT_B32 = 0x000001ce # macro -SQ_V_ALIGNBYTE_B32 = 0x000001cf # macro -SQ_V_MIN3_F32 = 0x000001d0 # macro -SQ_V_MIN3_I32 = 0x000001d1 # macro -SQ_V_MIN3_U32 = 0x000001d2 # macro -SQ_V_MAX3_F32 = 0x000001d3 # macro -SQ_V_MAX3_I32 = 0x000001d4 # macro -SQ_V_MAX3_U32 = 0x000001d5 # macro -SQ_V_MED3_F32 = 0x000001d6 # macro -SQ_V_MED3_I32 = 0x000001d7 # macro -SQ_V_MED3_U32 = 0x000001d8 # macro -SQ_V_SAD_U8 = 0x000001d9 # macro -SQ_V_SAD_HI_U8 = 0x000001da # macro -SQ_V_SAD_U16 = 0x000001db # macro -SQ_V_SAD_U32 = 0x000001dc # macro -SQ_V_CVT_PK_U8_F32 = 0x000001dd # macro -SQ_V_DIV_FIXUP_F32 = 0x000001de # macro -SQ_V_DIV_FIXUP_F64 = 0x000001df # macro -SQ_V_DIV_SCALE_F32 = 0x000001e0 # macro -SQ_V_DIV_SCALE_F64 = 0x000001e1 # macro -SQ_V_DIV_FMAS_F32 = 0x000001e2 # macro -SQ_V_DIV_FMAS_F64 = 0x000001e3 # macro -SQ_V_MSAD_U8 = 0x000001e4 # macro -SQ_V_QSAD_PK_U16_U8 = 0x000001e5 # macro -SQ_V_MQSAD_PK_U16_U8 = 0x000001e6 # macro -SQ_V_MQSAD_U32_U8 = 0x000001e7 # macro -SQ_V_MAD_U64_U32 = 0x000001e8 # macro -SQ_V_MAD_I64_I32 = 0x000001e9 # macro -SQ_V_MAD_LEGACY_F16 = 0x000001ea # macro -SQ_V_MAD_LEGACY_U16 = 0x000001eb # macro -SQ_V_MAD_LEGACY_I16 = 0x000001ec # macro -SQ_V_PERM_B32 = 0x000001ed # macro -SQ_V_FMA_LEGACY_F16 = 0x000001ee # macro -SQ_V_DIV_FIXUP_LEGACY_F16 = 0x000001ef # macro -SQ_V_CVT_PKACCUM_U8_F32 = 0x000001f0 # macro -SQ_V_MAD_U32_U16 = 0x000001f1 # macro -SQ_V_MAD_I32_I16 = 0x000001f2 # macro -SQ_V_XAD_U32 = 0x000001f3 # macro -SQ_V_MIN3_F16 = 0x000001f4 # macro -SQ_V_MIN3_I16 = 0x000001f5 # macro -SQ_V_MIN3_U16 = 0x000001f6 # macro -SQ_V_MAX3_F16 = 0x000001f7 # macro -SQ_V_MAX3_I16 = 0x000001f8 # macro -SQ_V_MAX3_U16 = 0x000001f9 # macro -SQ_V_MED3_F16 = 0x000001fa # macro -SQ_V_MED3_I16 = 0x000001fb # macro -SQ_V_MED3_U16 = 0x000001fc # macro -SQ_V_LSHL_ADD_U32 = 0x000001fd # macro -SQ_V_ADD_LSHL_U32 = 0x000001fe # macro -SQ_V_ADD3_U32 = 0x000001ff # macro -SQ_V_LSHL_OR_B32 = 0x00000200 # macro -SQ_V_AND_OR_B32 = 0x00000201 # macro -SQ_V_OR3_B32 = 0x00000202 # macro -SQ_V_MAD_F16 = 0x00000203 # macro -SQ_V_MAD_U16 = 0x00000204 # macro -SQ_V_MAD_I16 = 0x00000205 # macro -SQ_V_FMA_F16 = 0x00000206 # macro -SQ_V_DIV_FIXUP_F16 = 0x00000207 # macro -SQ_V_INTERP_P1LL_F16 = 0x00000274 # macro -SQ_V_INTERP_P1LV_F16 = 0x00000275 # macro -SQ_V_INTERP_P2_LEGACY_F16 = 0x00000276 # macro -SQ_V_INTERP_P2_F16 = 0x00000277 # macro -SQ_V_ADD_F64 = 0x00000280 # macro -SQ_V_MUL_F64 = 0x00000281 # macro -SQ_V_MIN_F64 = 0x00000282 # macro -SQ_V_MAX_F64 = 0x00000283 # macro -SQ_V_LDEXP_F64 = 0x00000284 # macro -SQ_V_MUL_LO_U32 = 0x00000285 # macro -SQ_V_MUL_HI_U32 = 0x00000286 # macro -SQ_V_MUL_HI_I32 = 0x00000287 # macro -SQ_V_LDEXP_F32 = 0x00000288 # macro -SQ_V_READLANE_B32 = 0x00000289 # macro -SQ_V_WRITELANE_B32 = 0x0000028a # macro -SQ_V_BCNT_U32_B32 = 0x0000028b # macro -SQ_V_MBCNT_LO_U32_B32 = 0x0000028c # macro -SQ_V_MBCNT_HI_U32_B32 = 0x0000028d # macro -SQ_V_MAC_LEGACY_F32 = 0x0000028e # macro -SQ_V_LSHLREV_B64 = 0x0000028f # macro -SQ_V_LSHRREV_B64 = 0x00000290 # macro -SQ_V_ASHRREV_I64 = 0x00000291 # macro -SQ_V_TRIG_PREOP_F64 = 0x00000292 # macro -SQ_V_BFM_B32 = 0x00000293 # macro -SQ_V_CVT_PKNORM_I16_F32 = 0x00000294 # macro -SQ_V_CVT_PKNORM_U16_F32 = 0x00000295 # macro -SQ_V_CVT_PKRTZ_F16_F32 = 0x00000296 # macro -SQ_V_CVT_PK_U16_U32 = 0x00000297 # macro -SQ_V_CVT_PK_I16_I32 = 0x00000298 # macro -SQ_V_CVT_PKNORM_I16_F16 = 0x00000299 # macro -SQ_V_CVT_PKNORM_U16_F16 = 0x0000029a # macro -SQ_V_READLANE_REGRD_B32 = 0x0000029b # macro -SQ_V_ADD_I32 = 0x0000029c # macro -SQ_V_SUB_I32 = 0x0000029d # macro -SQ_V_ADD_I16 = 0x0000029e # macro -SQ_V_SUB_I16 = 0x0000029f # macro -SQ_V_PACK_B32_F16 = 0x000002a0 # macro -SQ_SRC_LITERAL = 0x000000ff # macro -SQ_DPP_QUAD_PERM = 0x00000000 # macro -SQ_DPP_ROW_SL1 = 0x00000101 # macro -SQ_DPP_ROW_SL2 = 0x00000102 # macro -SQ_DPP_ROW_SL3 = 0x00000103 # macro -SQ_DPP_ROW_SL4 = 0x00000104 # macro -SQ_DPP_ROW_SL5 = 0x00000105 # macro -SQ_DPP_ROW_SL6 = 0x00000106 # macro -SQ_DPP_ROW_SL7 = 0x00000107 # macro -SQ_DPP_ROW_SL8 = 0x00000108 # macro -SQ_DPP_ROW_SL9 = 0x00000109 # macro -SQ_DPP_ROW_SL10 = 0x0000010a # macro -SQ_DPP_ROW_SL11 = 0x0000010b # macro -SQ_DPP_ROW_SL12 = 0x0000010c # macro -SQ_DPP_ROW_SL13 = 0x0000010d # macro -SQ_DPP_ROW_SL14 = 0x0000010e # macro -SQ_DPP_ROW_SL15 = 0x0000010f # macro -SQ_DPP_ROW_SR1 = 0x00000111 # macro -SQ_DPP_ROW_SR2 = 0x00000112 # macro -SQ_DPP_ROW_SR3 = 0x00000113 # macro -SQ_DPP_ROW_SR4 = 0x00000114 # macro -SQ_DPP_ROW_SR5 = 0x00000115 # macro -SQ_DPP_ROW_SR6 = 0x00000116 # macro -SQ_DPP_ROW_SR7 = 0x00000117 # macro -SQ_DPP_ROW_SR8 = 0x00000118 # macro -SQ_DPP_ROW_SR9 = 0x00000119 # macro -SQ_DPP_ROW_SR10 = 0x0000011a # macro -SQ_DPP_ROW_SR11 = 0x0000011b # macro -SQ_DPP_ROW_SR12 = 0x0000011c # macro -SQ_DPP_ROW_SR13 = 0x0000011d # macro -SQ_DPP_ROW_SR14 = 0x0000011e # macro -SQ_DPP_ROW_SR15 = 0x0000011f # macro -SQ_DPP_ROW_RR1 = 0x00000121 # macro -SQ_DPP_ROW_RR2 = 0x00000122 # macro -SQ_DPP_ROW_RR3 = 0x00000123 # macro -SQ_DPP_ROW_RR4 = 0x00000124 # macro -SQ_DPP_ROW_RR5 = 0x00000125 # macro -SQ_DPP_ROW_RR6 = 0x00000126 # macro -SQ_DPP_ROW_RR7 = 0x00000127 # macro -SQ_DPP_ROW_RR8 = 0x00000128 # macro -SQ_DPP_ROW_RR9 = 0x00000129 # macro -SQ_DPP_ROW_RR10 = 0x0000012a # macro -SQ_DPP_ROW_RR11 = 0x0000012b # macro -SQ_DPP_ROW_RR12 = 0x0000012c # macro -SQ_DPP_ROW_RR13 = 0x0000012d # macro -SQ_DPP_ROW_RR14 = 0x0000012e # macro -SQ_DPP_ROW_RR15 = 0x0000012f # macro -SQ_DPP_WF_SL1 = 0x00000130 # macro -SQ_DPP_WF_RL1 = 0x00000134 # macro -SQ_DPP_WF_SR1 = 0x00000138 # macro -SQ_DPP_WF_RR1 = 0x0000013c # macro -SQ_DPP_ROW_MIRROR = 0x00000140 # macro -SQ_DPP_ROW_HALF_MIRROR = 0x00000141 # macro -SQ_DPP_ROW_BCAST15 = 0x00000142 # macro -SQ_DPP_ROW_BCAST31 = 0x00000143 # macro -SQ_FLAT_SCRATCH_LO = 0x00000066 # macro -SQ_FLAT_SCRATCH_HI = 0x00000067 # macro -SQ_V_NOP = 0x00000000 # macro -SQ_V_MOV_B32 = 0x00000001 # macro -SQ_V_READFIRSTLANE_B32 = 0x00000002 # macro -SQ_V_CVT_I32_F64 = 0x00000003 # macro -SQ_V_CVT_F64_I32 = 0x00000004 # macro -SQ_V_CVT_F32_I32 = 0x00000005 # macro -SQ_V_CVT_F32_U32 = 0x00000006 # macro -SQ_V_CVT_U32_F32 = 0x00000007 # macro -SQ_V_CVT_I32_F32 = 0x00000008 # macro -SQ_V_MOV_FED_B32 = 0x00000009 # macro -SQ_V_CVT_F16_F32 = 0x0000000a # macro -SQ_V_CVT_F32_F16 = 0x0000000b # macro -SQ_V_CVT_RPI_I32_F32 = 0x0000000c # macro -SQ_V_CVT_FLR_I32_F32 = 0x0000000d # macro -SQ_V_CVT_OFF_F32_I4 = 0x0000000e # macro -SQ_V_CVT_F32_F64 = 0x0000000f # macro -SQ_V_CVT_F64_F32 = 0x00000010 # macro -SQ_V_CVT_F32_UBYTE0 = 0x00000011 # macro -SQ_V_CVT_F32_UBYTE1 = 0x00000012 # macro -SQ_V_CVT_F32_UBYTE2 = 0x00000013 # macro -SQ_V_CVT_F32_UBYTE3 = 0x00000014 # macro -SQ_V_CVT_U32_F64 = 0x00000015 # macro -SQ_V_CVT_F64_U32 = 0x00000016 # macro -SQ_V_TRUNC_F64 = 0x00000017 # macro -SQ_V_CEIL_F64 = 0x00000018 # macro -SQ_V_RNDNE_F64 = 0x00000019 # macro -SQ_V_FLOOR_F64 = 0x0000001a # macro -SQ_V_FRACT_F32 = 0x0000001b # macro -SQ_V_TRUNC_F32 = 0x0000001c # macro -SQ_V_CEIL_F32 = 0x0000001d # macro -SQ_V_RNDNE_F32 = 0x0000001e # macro -SQ_V_FLOOR_F32 = 0x0000001f # macro -SQ_V_EXP_F32 = 0x00000020 # macro -SQ_V_LOG_F32 = 0x00000021 # macro -SQ_V_RCP_F32 = 0x00000022 # macro -SQ_V_RCP_IFLAG_F32 = 0x00000023 # macro -SQ_V_RSQ_F32 = 0x00000024 # macro -SQ_V_RCP_F64 = 0x00000025 # macro -SQ_V_RSQ_F64 = 0x00000026 # macro -SQ_V_SQRT_F32 = 0x00000027 # macro -SQ_V_SQRT_F64 = 0x00000028 # macro -SQ_V_SIN_F32 = 0x00000029 # macro -SQ_V_COS_F32 = 0x0000002a # macro -SQ_V_NOT_B32 = 0x0000002b # macro -SQ_V_BFREV_B32 = 0x0000002c # macro -SQ_V_FFBH_U32 = 0x0000002d # macro -SQ_V_FFBL_B32 = 0x0000002e # macro -SQ_V_FFBH_I32 = 0x0000002f # macro -SQ_V_FREXP_EXP_I32_F64 = 0x00000030 # macro -SQ_V_FREXP_MANT_F64 = 0x00000031 # macro -SQ_V_FRACT_F64 = 0x00000032 # macro -SQ_V_FREXP_EXP_I32_F32 = 0x00000033 # macro -SQ_V_FREXP_MANT_F32 = 0x00000034 # macro -SQ_V_CLREXCP = 0x00000035 # macro -SQ_V_MOV_PRSV_B32 = 0x00000036 # macro -SQ_V_CVT_F16_U16 = 0x00000039 # macro -SQ_V_CVT_F16_I16 = 0x0000003a # macro -SQ_V_CVT_U16_F16 = 0x0000003b # macro -SQ_V_CVT_I16_F16 = 0x0000003c # macro -SQ_V_RCP_F16 = 0x0000003d # macro -SQ_V_SQRT_F16 = 0x0000003e # macro -SQ_V_RSQ_F16 = 0x0000003f # macro -SQ_V_LOG_F16 = 0x00000040 # macro -SQ_V_EXP_F16 = 0x00000041 # macro -SQ_V_FREXP_MANT_F16 = 0x00000042 # macro -SQ_V_FREXP_EXP_I16_F16 = 0x00000043 # macro -SQ_V_FLOOR_F16 = 0x00000044 # macro -SQ_V_CEIL_F16 = 0x00000045 # macro -SQ_V_TRUNC_F16 = 0x00000046 # macro -SQ_V_RNDNE_F16 = 0x00000047 # macro -SQ_V_FRACT_F16 = 0x00000048 # macro -SQ_V_SIN_F16 = 0x00000049 # macro -SQ_V_COS_F16 = 0x0000004a # macro -SQ_V_EXP_LEGACY_F32 = 0x0000004b # macro -SQ_V_LOG_LEGACY_F32 = 0x0000004c # macro -SQ_V_CVT_NORM_I16_F16 = 0x0000004d # macro -SQ_V_CVT_NORM_U16_F16 = 0x0000004e # macro -SQ_V_SAT_PK_U8_I16 = 0x0000004f # macro -SQ_V_WRITELANE_IMM32 = 0x00000050 # macro -SQ_V_SWAP_B32 = 0x00000051 # macro -SQ_FLAT_LOAD_UBYTE = 0x00000010 # macro -SQ_FLAT_LOAD_SBYTE = 0x00000011 # macro -SQ_FLAT_LOAD_USHORT = 0x00000012 # macro -SQ_FLAT_LOAD_SSHORT = 0x00000013 # macro -SQ_FLAT_LOAD_DWORD = 0x00000014 # macro -SQ_FLAT_LOAD_DWORDX2 = 0x00000015 # macro -SQ_FLAT_LOAD_DWORDX3 = 0x00000016 # macro -SQ_FLAT_LOAD_DWORDX4 = 0x00000017 # macro -SQ_FLAT_STORE_BYTE = 0x00000018 # macro -SQ_FLAT_STORE_SHORT = 0x0000001a # macro -SQ_FLAT_STORE_DWORD = 0x0000001c # macro -SQ_FLAT_STORE_DWORDX2 = 0x0000001d # macro -SQ_FLAT_STORE_DWORDX3 = 0x0000001e # macro -SQ_FLAT_STORE_DWORDX4 = 0x0000001f # macro -SQ_FLAT_ATOMIC_SWAP = 0x00000040 # macro -SQ_FLAT_ATOMIC_CMPSWAP = 0x00000041 # macro -SQ_FLAT_ATOMIC_ADD = 0x00000042 # macro -SQ_FLAT_ATOMIC_SUB = 0x00000043 # macro -SQ_FLAT_ATOMIC_SMIN = 0x00000044 # macro -SQ_FLAT_ATOMIC_UMIN = 0x00000045 # macro -SQ_FLAT_ATOMIC_SMAX = 0x00000046 # macro -SQ_FLAT_ATOMIC_UMAX = 0x00000047 # macro -SQ_FLAT_ATOMIC_AND = 0x00000048 # macro -SQ_FLAT_ATOMIC_OR = 0x00000049 # macro -SQ_FLAT_ATOMIC_XOR = 0x0000004a # macro -SQ_FLAT_ATOMIC_INC = 0x0000004b # macro -SQ_FLAT_ATOMIC_DEC = 0x0000004c # macro -SQ_FLAT_ATOMIC_SWAP_X2 = 0x00000060 # macro -SQ_FLAT_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro -SQ_FLAT_ATOMIC_ADD_X2 = 0x00000062 # macro -SQ_FLAT_ATOMIC_SUB_X2 = 0x00000063 # macro -SQ_FLAT_ATOMIC_SMIN_X2 = 0x00000064 # macro -SQ_FLAT_ATOMIC_UMIN_X2 = 0x00000065 # macro -SQ_FLAT_ATOMIC_SMAX_X2 = 0x00000066 # macro -SQ_FLAT_ATOMIC_UMAX_X2 = 0x00000067 # macro -SQ_FLAT_ATOMIC_AND_X2 = 0x00000068 # macro -SQ_FLAT_ATOMIC_OR_X2 = 0x00000069 # macro -SQ_FLAT_ATOMIC_XOR_X2 = 0x0000006a # macro -SQ_FLAT_ATOMIC_INC_X2 = 0x0000006b # macro -SQ_FLAT_ATOMIC_DEC_X2 = 0x0000006c # macro -SQ_DS_ADD_U32 = 0x00000000 # macro -SQ_DS_SUB_U32 = 0x00000001 # macro -SQ_DS_RSUB_U32 = 0x00000002 # macro -SQ_DS_INC_U32 = 0x00000003 # macro -SQ_DS_DEC_U32 = 0x00000004 # macro -SQ_DS_MIN_I32 = 0x00000005 # macro -SQ_DS_MAX_I32 = 0x00000006 # macro -SQ_DS_MIN_U32 = 0x00000007 # macro -SQ_DS_MAX_U32 = 0x00000008 # macro -SQ_DS_AND_B32 = 0x00000009 # macro -SQ_DS_OR_B32 = 0x0000000a # macro -SQ_DS_XOR_B32 = 0x0000000b # macro -SQ_DS_MSKOR_B32 = 0x0000000c # macro -SQ_DS_WRITE_B32 = 0x0000000d # macro -SQ_DS_WRITE2_B32 = 0x0000000e # macro -SQ_DS_WRITE2ST64_B32 = 0x0000000f # macro -SQ_DS_CMPST_B32 = 0x00000010 # macro -SQ_DS_CMPST_F32 = 0x00000011 # macro -SQ_DS_MIN_F32 = 0x00000012 # macro -SQ_DS_MAX_F32 = 0x00000013 # macro -SQ_DS_NOP = 0x00000014 # macro -SQ_DS_ADD_F32 = 0x00000015 # macro -SQ_DS_WRITE_ADDTID_B32 = 0x0000001d # macro -SQ_DS_WRITE_B8 = 0x0000001e # macro -SQ_DS_WRITE_B16 = 0x0000001f # macro -SQ_DS_ADD_RTN_U32 = 0x00000020 # macro -SQ_DS_SUB_RTN_U32 = 0x00000021 # macro -SQ_DS_RSUB_RTN_U32 = 0x00000022 # macro -SQ_DS_INC_RTN_U32 = 0x00000023 # macro -SQ_DS_DEC_RTN_U32 = 0x00000024 # macro -SQ_DS_MIN_RTN_I32 = 0x00000025 # macro -SQ_DS_MAX_RTN_I32 = 0x00000026 # macro -SQ_DS_MIN_RTN_U32 = 0x00000027 # macro -SQ_DS_MAX_RTN_U32 = 0x00000028 # macro -SQ_DS_AND_RTN_B32 = 0x00000029 # macro -SQ_DS_OR_RTN_B32 = 0x0000002a # macro -SQ_DS_XOR_RTN_B32 = 0x0000002b # macro -SQ_DS_MSKOR_RTN_B32 = 0x0000002c # macro -SQ_DS_WRXCHG_RTN_B32 = 0x0000002d # macro -SQ_DS_WRXCHG2_RTN_B32 = 0x0000002e # macro -SQ_DS_WRXCHG2ST64_RTN_B32 = 0x0000002f # macro -SQ_DS_CMPST_RTN_B32 = 0x00000030 # macro -SQ_DS_CMPST_RTN_F32 = 0x00000031 # macro -SQ_DS_MIN_RTN_F32 = 0x00000032 # macro -SQ_DS_MAX_RTN_F32 = 0x00000033 # macro -SQ_DS_WRAP_RTN_B32 = 0x00000034 # macro -SQ_DS_ADD_RTN_F32 = 0x00000035 # macro -SQ_DS_READ_B32 = 0x00000036 # macro -SQ_DS_READ2_B32 = 0x00000037 # macro -SQ_DS_READ2ST64_B32 = 0x00000038 # macro -SQ_DS_READ_I8 = 0x00000039 # macro -SQ_DS_READ_U8 = 0x0000003a # macro -SQ_DS_READ_I16 = 0x0000003b # macro -SQ_DS_READ_U16 = 0x0000003c # macro -SQ_DS_SWIZZLE_B32 = 0x0000003d # macro -SQ_DS_PERMUTE_B32 = 0x0000003e # macro -SQ_DS_BPERMUTE_B32 = 0x0000003f # macro -SQ_DS_ADD_U64 = 0x00000040 # macro -SQ_DS_SUB_U64 = 0x00000041 # macro -SQ_DS_RSUB_U64 = 0x00000042 # macro -SQ_DS_INC_U64 = 0x00000043 # macro -SQ_DS_DEC_U64 = 0x00000044 # macro -SQ_DS_MIN_I64 = 0x00000045 # macro -SQ_DS_MAX_I64 = 0x00000046 # macro -SQ_DS_MIN_U64 = 0x00000047 # macro -SQ_DS_MAX_U64 = 0x00000048 # macro -SQ_DS_AND_B64 = 0x00000049 # macro -SQ_DS_OR_B64 = 0x0000004a # macro -SQ_DS_XOR_B64 = 0x0000004b # macro -SQ_DS_MSKOR_B64 = 0x0000004c # macro -SQ_DS_WRITE_B64 = 0x0000004d # macro -SQ_DS_WRITE2_B64 = 0x0000004e # macro -SQ_DS_WRITE2ST64_B64 = 0x0000004f # macro -SQ_DS_CMPST_B64 = 0x00000050 # macro -SQ_DS_CMPST_F64 = 0x00000051 # macro -SQ_DS_MIN_F64 = 0x00000052 # macro -SQ_DS_MAX_F64 = 0x00000053 # macro -SQ_DS_ADD_RTN_U64 = 0x00000060 # macro -SQ_DS_SUB_RTN_U64 = 0x00000061 # macro -SQ_DS_RSUB_RTN_U64 = 0x00000062 # macro -SQ_DS_INC_RTN_U64 = 0x00000063 # macro -SQ_DS_DEC_RTN_U64 = 0x00000064 # macro -SQ_DS_MIN_RTN_I64 = 0x00000065 # macro -SQ_DS_MAX_RTN_I64 = 0x00000066 # macro -SQ_DS_MIN_RTN_U64 = 0x00000067 # macro -SQ_DS_MAX_RTN_U64 = 0x00000068 # macro -SQ_DS_AND_RTN_B64 = 0x00000069 # macro -SQ_DS_OR_RTN_B64 = 0x0000006a # macro -SQ_DS_XOR_RTN_B64 = 0x0000006b # macro -SQ_DS_MSKOR_RTN_B64 = 0x0000006c # macro -SQ_DS_WRXCHG_RTN_B64 = 0x0000006d # macro -SQ_DS_WRXCHG2_RTN_B64 = 0x0000006e # macro -SQ_DS_WRXCHG2ST64_RTN_B64 = 0x0000006f # macro -SQ_DS_CMPST_RTN_B64 = 0x00000070 # macro -SQ_DS_CMPST_RTN_F64 = 0x00000071 # macro -SQ_DS_MIN_RTN_F64 = 0x00000072 # macro -SQ_DS_MAX_RTN_F64 = 0x00000073 # macro -SQ_DS_READ_B64 = 0x00000076 # macro -SQ_DS_READ2_B64 = 0x00000077 # macro -SQ_DS_READ2ST64_B64 = 0x00000078 # macro -SQ_DS_CONDXCHG32_RTN_B64 = 0x0000007e # macro -SQ_DS_ADD_SRC2_U32 = 0x00000080 # macro -SQ_DS_SUB_SRC2_U32 = 0x00000081 # macro -SQ_DS_RSUB_SRC2_U32 = 0x00000082 # macro -SQ_DS_INC_SRC2_U32 = 0x00000083 # macro -SQ_DS_DEC_SRC2_U32 = 0x00000084 # macro -SQ_DS_MIN_SRC2_I32 = 0x00000085 # macro -SQ_DS_MAX_SRC2_I32 = 0x00000086 # macro -SQ_DS_MIN_SRC2_U32 = 0x00000087 # macro -SQ_DS_MAX_SRC2_U32 = 0x00000088 # macro -SQ_DS_AND_SRC2_B32 = 0x00000089 # macro -SQ_DS_OR_SRC2_B32 = 0x0000008a # macro -SQ_DS_XOR_SRC2_B32 = 0x0000008b # macro -SQ_DS_WRITE_SRC2_B32 = 0x0000008d # macro -SQ_DS_MIN_SRC2_F32 = 0x00000092 # macro -SQ_DS_MAX_SRC2_F32 = 0x00000093 # macro -SQ_DS_ADD_SRC2_F32 = 0x00000095 # macro -SQ_DS_GWS_SEMA_RELEASE_ALL = 0x00000098 # macro -SQ_DS_GWS_INIT = 0x00000099 # macro -SQ_DS_GWS_SEMA_V = 0x0000009a # macro -SQ_DS_GWS_SEMA_BR = 0x0000009b # macro -SQ_DS_GWS_SEMA_P = 0x0000009c # macro -SQ_DS_GWS_BARRIER = 0x0000009d # macro -SQ_DS_READ_ADDTID_B32 = 0x000000b6 # macro -SQ_DS_CONSUME = 0x000000bd # macro -SQ_DS_APPEND = 0x000000be # macro -SQ_DS_ORDERED_COUNT = 0x000000bf # macro -SQ_DS_ADD_SRC2_U64 = 0x000000c0 # macro -SQ_DS_SUB_SRC2_U64 = 0x000000c1 # macro -SQ_DS_RSUB_SRC2_U64 = 0x000000c2 # macro -SQ_DS_INC_SRC2_U64 = 0x000000c3 # macro -SQ_DS_DEC_SRC2_U64 = 0x000000c4 # macro -SQ_DS_MIN_SRC2_I64 = 0x000000c5 # macro -SQ_DS_MAX_SRC2_I64 = 0x000000c6 # macro -SQ_DS_MIN_SRC2_U64 = 0x000000c7 # macro -SQ_DS_MAX_SRC2_U64 = 0x000000c8 # macro -SQ_DS_AND_SRC2_B64 = 0x000000c9 # macro -SQ_DS_OR_SRC2_B64 = 0x000000ca # macro -SQ_DS_XOR_SRC2_B64 = 0x000000cb # macro -SQ_DS_WRITE_SRC2_B64 = 0x000000cd # macro -SQ_DS_MIN_SRC2_F64 = 0x000000d2 # macro -SQ_DS_MAX_SRC2_F64 = 0x000000d3 # macro -SQ_DS_WRITE_B96 = 0x000000de # macro -SQ_DS_WRITE_B128 = 0x000000df # macro -SQ_DS_CONDXCHG32_RTN_B128 = 0x000000fd # macro -SQ_DS_READ_B96 = 0x000000fe # macro -SQ_DS_READ_B128 = 0x000000ff # macro -SQ_S_LOAD_DWORD = 0x00000000 # macro -SQ_S_LOAD_DWORDX2 = 0x00000001 # macro -SQ_S_LOAD_DWORDX4 = 0x00000002 # macro -SQ_S_LOAD_DWORDX8 = 0x00000003 # macro -SQ_S_LOAD_DWORDX16 = 0x00000004 # macro -SQ_S_SCRATCH_LOAD_DWORD = 0x00000005 # macro -SQ_S_SCRATCH_LOAD_DWORDX2 = 0x00000006 # macro -SQ_S_SCRATCH_LOAD_DWORDX4 = 0x00000007 # macro -SQ_S_BUFFER_LOAD_DWORD = 0x00000008 # macro -SQ_S_BUFFER_LOAD_DWORDX2 = 0x00000009 # macro -SQ_S_BUFFER_LOAD_DWORDX4 = 0x0000000a # macro -SQ_S_BUFFER_LOAD_DWORDX8 = 0x0000000b # macro -SQ_S_BUFFER_LOAD_DWORDX16 = 0x0000000c # macro -SQ_S_STORE_DWORD = 0x00000010 # macro -SQ_S_STORE_DWORDX2 = 0x00000011 # macro -SQ_S_STORE_DWORDX4 = 0x00000012 # macro -SQ_S_SCRATCH_STORE_DWORD = 0x00000015 # macro -SQ_S_SCRATCH_STORE_DWORDX2 = 0x00000016 # macro -SQ_S_SCRATCH_STORE_DWORDX4 = 0x00000017 # macro -SQ_S_BUFFER_STORE_DWORD = 0x00000018 # macro -SQ_S_BUFFER_STORE_DWORDX2 = 0x00000019 # macro -SQ_S_BUFFER_STORE_DWORDX4 = 0x0000001a # macro -SQ_S_DCACHE_INV = 0x00000020 # macro -SQ_S_DCACHE_WB = 0x00000021 # macro -SQ_S_DCACHE_INV_VOL = 0x00000022 # macro -SQ_S_DCACHE_WB_VOL = 0x00000023 # macro -SQ_S_MEMTIME = 0x00000024 # macro -SQ_S_MEMREALTIME = 0x00000025 # macro -SQ_S_ATC_PROBE = 0x00000026 # macro -SQ_S_ATC_PROBE_BUFFER = 0x00000027 # macro -SQ_S_BUFFER_ATOMIC_SWAP = 0x00000040 # macro -SQ_S_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro -SQ_S_BUFFER_ATOMIC_ADD = 0x00000042 # macro -SQ_S_BUFFER_ATOMIC_SUB = 0x00000043 # macro -SQ_S_BUFFER_ATOMIC_SMIN = 0x00000044 # macro -SQ_S_BUFFER_ATOMIC_UMIN = 0x00000045 # macro -SQ_S_BUFFER_ATOMIC_SMAX = 0x00000046 # macro -SQ_S_BUFFER_ATOMIC_UMAX = 0x00000047 # macro -SQ_S_BUFFER_ATOMIC_AND = 0x00000048 # macro -SQ_S_BUFFER_ATOMIC_OR = 0x00000049 # macro -SQ_S_BUFFER_ATOMIC_XOR = 0x0000004a # macro -SQ_S_BUFFER_ATOMIC_INC = 0x0000004b # macro -SQ_S_BUFFER_ATOMIC_DEC = 0x0000004c # macro -SQ_S_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro -SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro -SQ_S_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro -SQ_S_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro -SQ_S_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro -SQ_S_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro -SQ_S_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro -SQ_S_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro -SQ_S_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro -SQ_S_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro -SQ_S_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro -SQ_S_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro -SQ_S_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro -SQ_S_ATOMIC_SWAP = 0x00000080 # macro -SQ_S_ATOMIC_CMPSWAP = 0x00000081 # macro -SQ_S_ATOMIC_ADD = 0x00000082 # macro -SQ_S_ATOMIC_SUB = 0x00000083 # macro -SQ_S_ATOMIC_SMIN = 0x00000084 # macro -SQ_S_ATOMIC_UMIN = 0x00000085 # macro -SQ_S_ATOMIC_SMAX = 0x00000086 # macro -SQ_S_ATOMIC_UMAX = 0x00000087 # macro -SQ_S_ATOMIC_AND = 0x00000088 # macro -SQ_S_ATOMIC_OR = 0x00000089 # macro -SQ_S_ATOMIC_XOR = 0x0000008a # macro -SQ_S_ATOMIC_INC = 0x0000008b # macro -SQ_S_ATOMIC_DEC = 0x0000008c # macro -SQ_S_ATOMIC_SWAP_X2 = 0x000000a0 # macro -SQ_S_ATOMIC_CMPSWAP_X2 = 0x000000a1 # macro -SQ_S_ATOMIC_ADD_X2 = 0x000000a2 # macro -SQ_S_ATOMIC_SUB_X2 = 0x000000a3 # macro -SQ_S_ATOMIC_SMIN_X2 = 0x000000a4 # macro -SQ_S_ATOMIC_UMIN_X2 = 0x000000a5 # macro -SQ_S_ATOMIC_SMAX_X2 = 0x000000a6 # macro -SQ_S_ATOMIC_UMAX_X2 = 0x000000a7 # macro -SQ_S_ATOMIC_AND_X2 = 0x000000a8 # macro -SQ_S_ATOMIC_OR_X2 = 0x000000a9 # macro -SQ_S_ATOMIC_XOR_X2 = 0x000000aa # macro -SQ_S_ATOMIC_INC_X2 = 0x000000ab # macro -SQ_S_ATOMIC_DEC_X2 = 0x000000ac # macro -SQ_V_CNDMASK_B32 = 0x00000000 # macro -SQ_V_ADD_F32 = 0x00000001 # macro -SQ_V_SUB_F32 = 0x00000002 # macro -SQ_V_SUBREV_F32 = 0x00000003 # macro -SQ_V_MUL_LEGACY_F32 = 0x00000004 # macro -SQ_V_MUL_F32 = 0x00000005 # macro -SQ_V_MUL_I32_I24 = 0x00000006 # macro -SQ_V_MUL_HI_I32_I24 = 0x00000007 # macro -SQ_V_MUL_U32_U24 = 0x00000008 # macro -SQ_V_MUL_HI_U32_U24 = 0x00000009 # macro -SQ_V_MIN_F32 = 0x0000000a # macro -SQ_V_MAX_F32 = 0x0000000b # macro -SQ_V_MIN_I32 = 0x0000000c # macro -SQ_V_MAX_I32 = 0x0000000d # macro -SQ_V_MIN_U32 = 0x0000000e # macro -SQ_V_MAX_U32 = 0x0000000f # macro -SQ_V_LSHRREV_B32 = 0x00000010 # macro -SQ_V_ASHRREV_I32 = 0x00000011 # macro -SQ_V_LSHLREV_B32 = 0x00000012 # macro -SQ_V_AND_B32 = 0x00000013 # macro -SQ_V_OR_B32 = 0x00000014 # macro -SQ_V_XOR_B32 = 0x00000015 # macro -SQ_V_MAC_F32 = 0x00000016 # macro -SQ_V_MADMK_F32 = 0x00000017 # macro -SQ_V_MADAK_F32 = 0x00000018 # macro -SQ_V_ADD_CO_U32 = 0x00000019 # macro -SQ_V_SUB_CO_U32 = 0x0000001a # macro -SQ_V_SUBREV_CO_U32 = 0x0000001b # macro -SQ_V_ADDC_CO_U32 = 0x0000001c # macro -SQ_V_SUBB_CO_U32 = 0x0000001d # macro -SQ_V_SUBBREV_CO_U32 = 0x0000001e # macro -SQ_V_ADD_F16 = 0x0000001f # macro -SQ_V_SUB_F16 = 0x00000020 # macro -SQ_V_SUBREV_F16 = 0x00000021 # macro -SQ_V_MUL_F16 = 0x00000022 # macro -SQ_V_MAC_F16 = 0x00000023 # macro -SQ_V_MADMK_F16 = 0x00000024 # macro -SQ_V_MADAK_F16 = 0x00000025 # macro -SQ_V_ADD_U16 = 0x00000026 # macro -SQ_V_SUB_U16 = 0x00000027 # macro -SQ_V_SUBREV_U16 = 0x00000028 # macro -SQ_V_MUL_LO_U16 = 0x00000029 # macro -SQ_V_LSHLREV_B16 = 0x0000002a # macro -SQ_V_LSHRREV_B16 = 0x0000002b # macro -SQ_V_ASHRREV_I16 = 0x0000002c # macro -SQ_V_MAX_F16 = 0x0000002d # macro -SQ_V_MIN_F16 = 0x0000002e # macro -SQ_V_MAX_U16 = 0x0000002f # macro -SQ_V_MAX_I16 = 0x00000030 # macro -SQ_V_MIN_U16 = 0x00000031 # macro -SQ_V_MIN_I16 = 0x00000032 # macro -SQ_V_LDEXP_F16 = 0x00000033 # macro -SQ_V_ADD_U32 = 0x00000034 # macro -SQ_V_SUB_U32 = 0x00000035 # macro -SQ_V_SUBREV_U32 = 0x00000036 # macro -SQ_SYSMSG_OP_ECC_ERR_INTERRUPT = 0x00000001 # macro -SQ_SYSMSG_OP_REG_RD = 0x00000002 # macro -SQ_SYSMSG_OP_HOST_TRAP_ACK = 0x00000003 # macro -SQ_SYSMSG_OP_TTRACE_PC = 0x00000004 # macro -SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT = 0x00000005 # macro -SQ_SYSMSG_OP_MEMVIOL_INTERRUPT = 0x00000006 # macro -SQ_SRC_VCCZ = 0x000000fb # macro -SQ_CHAN_X = 0x00000000 # macro -SQ_CHAN_Y = 0x00000001 # macro -SQ_CHAN_Z = 0x00000002 # macro -SQ_CHAN_W = 0x00000003 # macro -SQ_S_MOVK_I32 = 0x00000000 # macro -SQ_S_CMOVK_I32 = 0x00000001 # macro -SQ_S_CMPK_EQ_I32 = 0x00000002 # macro -SQ_S_CMPK_LG_I32 = 0x00000003 # macro -SQ_S_CMPK_GT_I32 = 0x00000004 # macro -SQ_S_CMPK_GE_I32 = 0x00000005 # macro -SQ_S_CMPK_LT_I32 = 0x00000006 # macro -SQ_S_CMPK_LE_I32 = 0x00000007 # macro -SQ_S_CMPK_EQ_U32 = 0x00000008 # macro -SQ_S_CMPK_LG_U32 = 0x00000009 # macro -SQ_S_CMPK_GT_U32 = 0x0000000a # macro -SQ_S_CMPK_GE_U32 = 0x0000000b # macro -SQ_S_CMPK_LT_U32 = 0x0000000c # macro -SQ_S_CMPK_LE_U32 = 0x0000000d # macro -SQ_S_ADDK_I32 = 0x0000000e # macro -SQ_S_MULK_I32 = 0x0000000f # macro -SQ_S_CBRANCH_I_FORK = 0x00000010 # macro -SQ_S_GETREG_B32 = 0x00000011 # macro -SQ_S_SETREG_B32 = 0x00000012 # macro -SQ_S_GETREG_REGRD_B32 = 0x00000013 # macro -SQ_S_SETREG_IMM32_B32 = 0x00000014 # macro -SQ_S_CALL_B64 = 0x00000015 # macro -SQ_L1 = 0x00000001 # macro -SQ_L2 = 0x00000002 # macro -SQ_L3 = 0x00000003 # macro -SQ_L4 = 0x00000004 # macro -SQ_L5 = 0x00000005 # macro -SQ_L6 = 0x00000006 # macro -SQ_L7 = 0x00000007 # macro -SQ_L8 = 0x00000008 # macro -SQ_L9 = 0x00000009 # macro -SQ_L10 = 0x0000000a # macro -SQ_L11 = 0x0000000b # macro -SQ_L12 = 0x0000000c # macro -SQ_L13 = 0x0000000d # macro -SQ_L14 = 0x0000000e # macro -SQ_L15 = 0x0000000f # macro -SQ_SGPR0 = 0x00000000 # macro -SQ_V_PK_MAD_I16 = 0x00000000 # macro -SQ_V_PK_MUL_LO_U16 = 0x00000001 # macro -SQ_V_PK_ADD_I16 = 0x00000002 # macro -SQ_V_PK_SUB_I16 = 0x00000003 # macro -SQ_V_PK_LSHLREV_B16 = 0x00000004 # macro -SQ_V_PK_LSHRREV_B16 = 0x00000005 # macro -SQ_V_PK_ASHRREV_I16 = 0x00000006 # macro -SQ_V_PK_MAX_I16 = 0x00000007 # macro -SQ_V_PK_MIN_I16 = 0x00000008 # macro -SQ_V_PK_MAD_U16 = 0x00000009 # macro -SQ_V_PK_ADD_U16 = 0x0000000a # macro -SQ_V_PK_SUB_U16 = 0x0000000b # macro -SQ_V_PK_MAX_U16 = 0x0000000c # macro -SQ_V_PK_MIN_U16 = 0x0000000d # macro -SQ_V_PK_MAD_F16 = 0x0000000e # macro -SQ_V_PK_ADD_F16 = 0x0000000f # macro -SQ_V_PK_MUL_F16 = 0x00000010 # macro -SQ_V_PK_MIN_F16 = 0x00000011 # macro -SQ_V_PK_MAX_F16 = 0x00000012 # macro -SQ_V_MAD_MIX_F32 = 0x00000020 # macro -SQ_V_MAD_MIXLO_F16 = 0x00000021 # macro -SQ_V_MAD_MIXHI_F16 = 0x00000022 # macro -SQ_V_INTERP_P1_F32 = 0x00000000 # macro -SQ_V_INTERP_P2_F32 = 0x00000001 # macro -SQ_V_INTERP_MOV_F32 = 0x00000002 # macro -SQ_R1 = 0x00000001 # macro -SQ_R2 = 0x00000002 # macro -SQ_R3 = 0x00000003 # macro -SQ_R4 = 0x00000004 # macro -SQ_R5 = 0x00000005 # macro -SQ_R6 = 0x00000006 # macro -SQ_R7 = 0x00000007 # macro -SQ_R8 = 0x00000008 # macro -SQ_R9 = 0x00000009 # macro -SQ_R10 = 0x0000000a # macro -SQ_R11 = 0x0000000b # macro -SQ_R12 = 0x0000000c # macro -SQ_R13 = 0x0000000d # macro -SQ_R14 = 0x0000000e # macro -SQ_R15 = 0x0000000f # macro -SQ_S_ADD_U32 = 0x00000000 # macro -SQ_S_SUB_U32 = 0x00000001 # macro -SQ_S_ADD_I32 = 0x00000002 # macro -SQ_S_SUB_I32 = 0x00000003 # macro -SQ_S_ADDC_U32 = 0x00000004 # macro -SQ_S_SUBB_U32 = 0x00000005 # macro -SQ_S_MIN_I32 = 0x00000006 # macro -SQ_S_MIN_U32 = 0x00000007 # macro -SQ_S_MAX_I32 = 0x00000008 # macro -SQ_S_MAX_U32 = 0x00000009 # macro -SQ_S_CSELECT_B32 = 0x0000000a # macro -SQ_S_CSELECT_B64 = 0x0000000b # macro -SQ_S_AND_B32 = 0x0000000c # macro -SQ_S_AND_B64 = 0x0000000d # macro -SQ_S_OR_B32 = 0x0000000e # macro -SQ_S_OR_B64 = 0x0000000f # macro -SQ_S_XOR_B32 = 0x00000010 # macro -SQ_S_XOR_B64 = 0x00000011 # macro -SQ_S_ANDN2_B32 = 0x00000012 # macro -SQ_S_ANDN2_B64 = 0x00000013 # macro -SQ_S_ORN2_B32 = 0x00000014 # macro -SQ_S_ORN2_B64 = 0x00000015 # macro -SQ_S_NAND_B32 = 0x00000016 # macro -SQ_S_NAND_B64 = 0x00000017 # macro -SQ_S_NOR_B32 = 0x00000018 # macro -SQ_S_NOR_B64 = 0x00000019 # macro -SQ_S_XNOR_B32 = 0x0000001a # macro -SQ_S_XNOR_B64 = 0x0000001b # macro -SQ_S_LSHL_B32 = 0x0000001c # macro -SQ_S_LSHL_B64 = 0x0000001d # macro -SQ_S_LSHR_B32 = 0x0000001e # macro -SQ_S_LSHR_B64 = 0x0000001f # macro -SQ_S_ASHR_I32 = 0x00000020 # macro -SQ_S_ASHR_I64 = 0x00000021 # macro -SQ_S_BFM_B32 = 0x00000022 # macro -SQ_S_BFM_B64 = 0x00000023 # macro -SQ_S_MUL_I32 = 0x00000024 # macro -SQ_S_BFE_U32 = 0x00000025 # macro -SQ_S_BFE_I32 = 0x00000026 # macro -SQ_S_BFE_U64 = 0x00000027 # macro -SQ_S_BFE_I64 = 0x00000028 # macro -SQ_S_CBRANCH_G_FORK = 0x00000029 # macro -SQ_S_ABSDIFF_I32 = 0x0000002a # macro -SQ_S_RFE_RESTORE_B64 = 0x0000002b # macro -SQ_S_MUL_HI_U32 = 0x0000002c # macro -SQ_S_MUL_HI_I32 = 0x0000002d # macro -SQ_S_LSHL1_ADD_U32 = 0x0000002e # macro -SQ_S_LSHL2_ADD_U32 = 0x0000002f # macro -SQ_S_LSHL3_ADD_U32 = 0x00000030 # macro -SQ_S_LSHL4_ADD_U32 = 0x00000031 # macro -SQ_S_PACK_LL_B32_B16 = 0x00000032 # macro -SQ_S_PACK_LH_B32_B16 = 0x00000033 # macro -SQ_S_PACK_HH_B32_B16 = 0x00000034 # macro -SQ_FLAT = 0x00000000 # macro -SQ_SCRATCH = 0x00000001 # macro -SQ_GLOBAL = 0x00000002 # macro -SQ_EXEC_LO = 0x0000007e # macro -SQ_EXEC_HI = 0x0000007f # macro -SQ_SRC_64_INT = 0x000000c0 # macro -SQ_SRC_M_1_INT = 0x000000c1 # macro -SQ_SRC_M_2_INT = 0x000000c2 # macro -SQ_SRC_M_3_INT = 0x000000c3 # macro -SQ_SRC_M_4_INT = 0x000000c4 # macro -SQ_SRC_M_5_INT = 0x000000c5 # macro -SQ_SRC_M_6_INT = 0x000000c6 # macro -SQ_SRC_M_7_INT = 0x000000c7 # macro -SQ_SRC_M_8_INT = 0x000000c8 # macro -SQ_SRC_M_9_INT = 0x000000c9 # macro -SQ_SRC_M_10_INT = 0x000000ca # macro -SQ_SRC_M_11_INT = 0x000000cb # macro -SQ_SRC_M_12_INT = 0x000000cc # macro -SQ_SRC_M_13_INT = 0x000000cd # macro -SQ_SRC_M_14_INT = 0x000000ce # macro -SQ_SRC_M_15_INT = 0x000000cf # macro -SQ_SRC_M_16_INT = 0x000000d0 # macro -SQ_SRC_0_5 = 0x000000f0 # macro -SQ_SRC_M_0_5 = 0x000000f1 # macro -SQ_SRC_1 = 0x000000f2 # macro -SQ_SRC_M_1 = 0x000000f3 # macro -SQ_SRC_2 = 0x000000f4 # macro -SQ_SRC_M_2 = 0x000000f5 # macro -SQ_SRC_4 = 0x000000f6 # macro -SQ_SRC_M_4 = 0x000000f7 # macro -SQ_SRC_INV_2PI = 0x000000f8 # macro -SQ_VCC_LO = 0x0000006a # macro -SQ_VCC_HI = 0x0000006b # macro -SQ_EXP_MRT0 = 0x00000000 # macro -SQ_EXP_MRTZ = 0x00000008 # macro -SQ_EXP_NULL = 0x00000009 # macro -SQ_EXP_POS0 = 0x0000000c # macro -SQ_EXP_PARAM0 = 0x00000020 # macro -SQ_S_NOP = 0x00000000 # macro -SQ_S_ENDPGM = 0x00000001 # macro -SQ_S_BRANCH = 0x00000002 # macro -SQ_S_WAKEUP = 0x00000003 # macro -SQ_S_CBRANCH_SCC0 = 0x00000004 # macro -SQ_S_CBRANCH_SCC1 = 0x00000005 # macro -SQ_S_CBRANCH_VCCZ = 0x00000006 # macro -SQ_S_CBRANCH_VCCNZ = 0x00000007 # macro -SQ_S_CBRANCH_EXECZ = 0x00000008 # macro -SQ_S_CBRANCH_EXECNZ = 0x00000009 # macro -SQ_S_BARRIER = 0x0000000a # macro -SQ_S_SETKILL = 0x0000000b # macro -SQ_S_WAITCNT = 0x0000000c # macro -SQ_S_SETHALT = 0x0000000d # macro -SQ_S_SLEEP = 0x0000000e # macro -SQ_S_SETPRIO = 0x0000000f # macro -SQ_S_SENDMSG = 0x00000010 # macro -SQ_S_SENDMSGHALT = 0x00000011 # macro -SQ_S_TRAP = 0x00000012 # macro -SQ_S_ICACHE_INV = 0x00000013 # macro -SQ_S_INCPERFLEVEL = 0x00000014 # macro -SQ_S_DECPERFLEVEL = 0x00000015 # macro -SQ_S_TTRACEDATA = 0x00000016 # macro -SQ_S_CBRANCH_CDBGSYS = 0x00000017 # macro -SQ_S_CBRANCH_CDBGUSER = 0x00000018 # macro -SQ_S_CBRANCH_CDBGSYS_OR_USER = 0x00000019 # macro -SQ_S_CBRANCH_CDBGSYS_AND_USER = 0x0000001a # macro -SQ_S_ENDPGM_SAVED = 0x0000001b # macro -SQ_S_SET_GPR_IDX_OFF = 0x0000001c # macro -SQ_S_SET_GPR_IDX_MODE = 0x0000001d # macro -SQ_S_ENDPGM_ORDERED_PS_DONE = 0x0000001e # macro -SQ_EXP = 0x00000000 # macro -SQ_SRC_POPS_EXITING_WAVE_ID = 0x000000ef # macro -SQ_XNACK_MASK_LO = 0x00000068 # macro -SQ_XNACK_MASK_HI = 0x00000069 # macro -SQ_OMOD_OFF = 0x00000000 # macro -SQ_OMOD_M2 = 0x00000001 # macro -SQ_OMOD_M4 = 0x00000002 # macro -SQ_OMOD_D2 = 0x00000003 # macro -SQ_SRC_EXECZ = 0x000000fc # macro -SQ_F = 0x00000000 # macro -SQ_LT = 0x00000001 # macro -SQ_EQ = 0x00000002 # macro -SQ_LE = 0x00000003 # macro -SQ_GT = 0x00000004 # macro -SQ_NE = 0x00000005 # macro -SQ_GE = 0x00000006 # macro -SQ_T = 0x00000007 # macro -SQ_DPP_BOUND_OFF = 0x00000000 # macro -SQ_DPP_BOUND_ZERO = 0x00000001 # macro -SQ_M0 = 0x0000007c # macro -SQ_MSG_INTERRUPT = 0x00000001 # macro -SQ_MSG_GS = 0x00000002 # macro -SQ_MSG_GS_DONE = 0x00000003 # macro -SQ_MSG_SAVEWAVE = 0x00000004 # macro -SQ_MSG_STALL_WAVE_GEN = 0x00000005 # macro -SQ_MSG_HALT_WAVES = 0x00000006 # macro -SQ_MSG_ORDERED_PS_DONE = 0x00000007 # macro -SQ_MSG_EARLY_PRIM_DEALLOC = 0x00000008 # macro -SQ_MSG_GS_ALLOC_REQ = 0x00000009 # macro -SQ_MSG_SYSMSG = 0x0000000f # macro -SQ_PARAM_P10 = 0x00000000 # macro -SQ_PARAM_P20 = 0x00000001 # macro -SQ_PARAM_P0 = 0x00000002 # macro -SQ_V_OPC_OFFSET = 0x00000000 # macro -SQ_V_OP2_OFFSET = 0x00000100 # macro -SQ_V_OP1_OFFSET = 0x00000140 # macro -SQ_V_INTRP_OFFSET = 0x00000270 # macro -SQ_V_OP3P_OFFSET = 0x00000380 # macro -SQ_SRC_SDWA = 0x000000f9 # macro -SQ_SRC_SHARED_BASE = 0x000000eb # macro -SQ_SRC_SHARED_LIMIT = 0x000000ec # macro -SQ_SRC_PRIVATE_BASE = 0x000000ed # macro -SQ_SRC_PRIVATE_LIMIT = 0x000000ee # macro -SQ_LG = 0x00000005 # macro -SQ_O = 0x00000007 # macro -SQ_U = 0x00000008 # macro -SQ_NGE = 0x00000009 # macro -SQ_NLG = 0x0000000a # macro -SQ_NGT = 0x0000000b # macro -SQ_NLE = 0x0000000c # macro -SQ_NEQ = 0x0000000d # macro -SQ_NLT = 0x0000000e # macro -SQ_TRU = 0x0000000f # macro -SQ_SDWA_UNUSED_PAD = 0x00000000 # macro -SQ_SDWA_UNUSED_SEXT = 0x00000001 # macro -SQ_SDWA_UNUSED_PRESERVE = 0x00000002 # macro -SQ_SRC_SCC = 0x000000fd # macro -SQ_V_CMP_CLASS_F32 = 0x00000010 # macro -SQ_V_CMPX_CLASS_F32 = 0x00000011 # macro -SQ_V_CMP_CLASS_F64 = 0x00000012 # macro -SQ_V_CMPX_CLASS_F64 = 0x00000013 # macro -SQ_V_CMP_CLASS_F16 = 0x00000014 # macro -SQ_V_CMPX_CLASS_F16 = 0x00000015 # macro -SQ_V_CMP_F_F16 = 0x00000020 # macro -SQ_V_CMP_LT_F16 = 0x00000021 # macro -SQ_V_CMP_EQ_F16 = 0x00000022 # macro -SQ_V_CMP_LE_F16 = 0x00000023 # macro -SQ_V_CMP_GT_F16 = 0x00000024 # macro -SQ_V_CMP_LG_F16 = 0x00000025 # macro -SQ_V_CMP_GE_F16 = 0x00000026 # macro -SQ_V_CMP_O_F16 = 0x00000027 # macro -SQ_V_CMP_U_F16 = 0x00000028 # macro -SQ_V_CMP_NGE_F16 = 0x00000029 # macro -SQ_V_CMP_NLG_F16 = 0x0000002a # macro -SQ_V_CMP_NGT_F16 = 0x0000002b # macro -SQ_V_CMP_NLE_F16 = 0x0000002c # macro -SQ_V_CMP_NEQ_F16 = 0x0000002d # macro -SQ_V_CMP_NLT_F16 = 0x0000002e # macro -SQ_V_CMP_TRU_F16 = 0x0000002f # macro -SQ_V_CMPX_F_F16 = 0x00000030 # macro -SQ_V_CMPX_LT_F16 = 0x00000031 # macro -SQ_V_CMPX_EQ_F16 = 0x00000032 # macro -SQ_V_CMPX_LE_F16 = 0x00000033 # macro -SQ_V_CMPX_GT_F16 = 0x00000034 # macro -SQ_V_CMPX_LG_F16 = 0x00000035 # macro -SQ_V_CMPX_GE_F16 = 0x00000036 # macro -SQ_V_CMPX_O_F16 = 0x00000037 # macro -SQ_V_CMPX_U_F16 = 0x00000038 # macro -SQ_V_CMPX_NGE_F16 = 0x00000039 # macro -SQ_V_CMPX_NLG_F16 = 0x0000003a # macro -SQ_V_CMPX_NGT_F16 = 0x0000003b # macro -SQ_V_CMPX_NLE_F16 = 0x0000003c # macro -SQ_V_CMPX_NEQ_F16 = 0x0000003d # macro -SQ_V_CMPX_NLT_F16 = 0x0000003e # macro -SQ_V_CMPX_TRU_F16 = 0x0000003f # macro -SQ_V_CMP_F_F32 = 0x00000040 # macro -SQ_V_CMP_LT_F32 = 0x00000041 # macro -SQ_V_CMP_EQ_F32 = 0x00000042 # macro -SQ_V_CMP_LE_F32 = 0x00000043 # macro -SQ_V_CMP_GT_F32 = 0x00000044 # macro -SQ_V_CMP_LG_F32 = 0x00000045 # macro -SQ_V_CMP_GE_F32 = 0x00000046 # macro -SQ_V_CMP_O_F32 = 0x00000047 # macro -SQ_V_CMP_U_F32 = 0x00000048 # macro -SQ_V_CMP_NGE_F32 = 0x00000049 # macro -SQ_V_CMP_NLG_F32 = 0x0000004a # macro -SQ_V_CMP_NGT_F32 = 0x0000004b # macro -SQ_V_CMP_NLE_F32 = 0x0000004c # macro -SQ_V_CMP_NEQ_F32 = 0x0000004d # macro -SQ_V_CMP_NLT_F32 = 0x0000004e # macro -SQ_V_CMP_TRU_F32 = 0x0000004f # macro -SQ_V_CMPX_F_F32 = 0x00000050 # macro -SQ_V_CMPX_LT_F32 = 0x00000051 # macro -SQ_V_CMPX_EQ_F32 = 0x00000052 # macro -SQ_V_CMPX_LE_F32 = 0x00000053 # macro -SQ_V_CMPX_GT_F32 = 0x00000054 # macro -SQ_V_CMPX_LG_F32 = 0x00000055 # macro -SQ_V_CMPX_GE_F32 = 0x00000056 # macro -SQ_V_CMPX_O_F32 = 0x00000057 # macro -SQ_V_CMPX_U_F32 = 0x00000058 # macro -SQ_V_CMPX_NGE_F32 = 0x00000059 # macro -SQ_V_CMPX_NLG_F32 = 0x0000005a # macro -SQ_V_CMPX_NGT_F32 = 0x0000005b # macro -SQ_V_CMPX_NLE_F32 = 0x0000005c # macro -SQ_V_CMPX_NEQ_F32 = 0x0000005d # macro -SQ_V_CMPX_NLT_F32 = 0x0000005e # macro -SQ_V_CMPX_TRU_F32 = 0x0000005f # macro -SQ_V_CMP_F_F64 = 0x00000060 # macro -SQ_V_CMP_LT_F64 = 0x00000061 # macro -SQ_V_CMP_EQ_F64 = 0x00000062 # macro -SQ_V_CMP_LE_F64 = 0x00000063 # macro -SQ_V_CMP_GT_F64 = 0x00000064 # macro -SQ_V_CMP_LG_F64 = 0x00000065 # macro -SQ_V_CMP_GE_F64 = 0x00000066 # macro -SQ_V_CMP_O_F64 = 0x00000067 # macro -SQ_V_CMP_U_F64 = 0x00000068 # macro -SQ_V_CMP_NGE_F64 = 0x00000069 # macro -SQ_V_CMP_NLG_F64 = 0x0000006a # macro -SQ_V_CMP_NGT_F64 = 0x0000006b # macro -SQ_V_CMP_NLE_F64 = 0x0000006c # macro -SQ_V_CMP_NEQ_F64 = 0x0000006d # macro -SQ_V_CMP_NLT_F64 = 0x0000006e # macro -SQ_V_CMP_TRU_F64 = 0x0000006f # macro -SQ_V_CMPX_F_F64 = 0x00000070 # macro -SQ_V_CMPX_LT_F64 = 0x00000071 # macro -SQ_V_CMPX_EQ_F64 = 0x00000072 # macro -SQ_V_CMPX_LE_F64 = 0x00000073 # macro -SQ_V_CMPX_GT_F64 = 0x00000074 # macro -SQ_V_CMPX_LG_F64 = 0x00000075 # macro -SQ_V_CMPX_GE_F64 = 0x00000076 # macro -SQ_V_CMPX_O_F64 = 0x00000077 # macro -SQ_V_CMPX_U_F64 = 0x00000078 # macro -SQ_V_CMPX_NGE_F64 = 0x00000079 # macro -SQ_V_CMPX_NLG_F64 = 0x0000007a # macro -SQ_V_CMPX_NGT_F64 = 0x0000007b # macro -SQ_V_CMPX_NLE_F64 = 0x0000007c # macro -SQ_V_CMPX_NEQ_F64 = 0x0000007d # macro -SQ_V_CMPX_NLT_F64 = 0x0000007e # macro -SQ_V_CMPX_TRU_F64 = 0x0000007f # macro -SQ_V_CMP_F_I16 = 0x000000a0 # macro -SQ_V_CMP_LT_I16 = 0x000000a1 # macro -SQ_V_CMP_EQ_I16 = 0x000000a2 # macro -SQ_V_CMP_LE_I16 = 0x000000a3 # macro -SQ_V_CMP_GT_I16 = 0x000000a4 # macro -SQ_V_CMP_NE_I16 = 0x000000a5 # macro -SQ_V_CMP_GE_I16 = 0x000000a6 # macro -SQ_V_CMP_T_I16 = 0x000000a7 # macro -SQ_V_CMP_F_U16 = 0x000000a8 # macro -SQ_V_CMP_LT_U16 = 0x000000a9 # macro -SQ_V_CMP_EQ_U16 = 0x000000aa # macro -SQ_V_CMP_LE_U16 = 0x000000ab # macro -SQ_V_CMP_GT_U16 = 0x000000ac # macro -SQ_V_CMP_NE_U16 = 0x000000ad # macro -SQ_V_CMP_GE_U16 = 0x000000ae # macro -SQ_V_CMP_T_U16 = 0x000000af # macro -SQ_V_CMPX_F_I16 = 0x000000b0 # macro -SQ_V_CMPX_LT_I16 = 0x000000b1 # macro -SQ_V_CMPX_EQ_I16 = 0x000000b2 # macro -SQ_V_CMPX_LE_I16 = 0x000000b3 # macro -SQ_V_CMPX_GT_I16 = 0x000000b4 # macro -SQ_V_CMPX_NE_I16 = 0x000000b5 # macro -SQ_V_CMPX_GE_I16 = 0x000000b6 # macro -SQ_V_CMPX_T_I16 = 0x000000b7 # macro -SQ_V_CMPX_F_U16 = 0x000000b8 # macro -SQ_V_CMPX_LT_U16 = 0x000000b9 # macro -SQ_V_CMPX_EQ_U16 = 0x000000ba # macro -SQ_V_CMPX_LE_U16 = 0x000000bb # macro -SQ_V_CMPX_GT_U16 = 0x000000bc # macro -SQ_V_CMPX_NE_U16 = 0x000000bd # macro -SQ_V_CMPX_GE_U16 = 0x000000be # macro -SQ_V_CMPX_T_U16 = 0x000000bf # macro -SQ_V_CMP_F_I32 = 0x000000c0 # macro -SQ_V_CMP_LT_I32 = 0x000000c1 # macro -SQ_V_CMP_EQ_I32 = 0x000000c2 # macro -SQ_V_CMP_LE_I32 = 0x000000c3 # macro -SQ_V_CMP_GT_I32 = 0x000000c4 # macro -SQ_V_CMP_NE_I32 = 0x000000c5 # macro -SQ_V_CMP_GE_I32 = 0x000000c6 # macro -SQ_V_CMP_T_I32 = 0x000000c7 # macro -SQ_V_CMP_F_U32 = 0x000000c8 # macro -SQ_V_CMP_LT_U32 = 0x000000c9 # macro -SQ_V_CMP_EQ_U32 = 0x000000ca # macro -SQ_V_CMP_LE_U32 = 0x000000cb # macro -SQ_V_CMP_GT_U32 = 0x000000cc # macro -SQ_V_CMP_NE_U32 = 0x000000cd # macro -SQ_V_CMP_GE_U32 = 0x000000ce # macro -SQ_V_CMP_T_U32 = 0x000000cf # macro -SQ_V_CMPX_F_I32 = 0x000000d0 # macro -SQ_V_CMPX_LT_I32 = 0x000000d1 # macro -SQ_V_CMPX_EQ_I32 = 0x000000d2 # macro -SQ_V_CMPX_LE_I32 = 0x000000d3 # macro -SQ_V_CMPX_GT_I32 = 0x000000d4 # macro -SQ_V_CMPX_NE_I32 = 0x000000d5 # macro -SQ_V_CMPX_GE_I32 = 0x000000d6 # macro -SQ_V_CMPX_T_I32 = 0x000000d7 # macro -SQ_V_CMPX_F_U32 = 0x000000d8 # macro -SQ_V_CMPX_LT_U32 = 0x000000d9 # macro -SQ_V_CMPX_EQ_U32 = 0x000000da # macro -SQ_V_CMPX_LE_U32 = 0x000000db # macro -SQ_V_CMPX_GT_U32 = 0x000000dc # macro -SQ_V_CMPX_NE_U32 = 0x000000dd # macro -SQ_V_CMPX_GE_U32 = 0x000000de # macro -SQ_V_CMPX_T_U32 = 0x000000df # macro -SQ_V_CMP_F_I64 = 0x000000e0 # macro -SQ_V_CMP_LT_I64 = 0x000000e1 # macro -SQ_V_CMP_EQ_I64 = 0x000000e2 # macro -SQ_V_CMP_LE_I64 = 0x000000e3 # macro -SQ_V_CMP_GT_I64 = 0x000000e4 # macro -SQ_V_CMP_NE_I64 = 0x000000e5 # macro -SQ_V_CMP_GE_I64 = 0x000000e6 # macro -SQ_V_CMP_T_I64 = 0x000000e7 # macro -SQ_V_CMP_F_U64 = 0x000000e8 # macro -SQ_V_CMP_LT_U64 = 0x000000e9 # macro -SQ_V_CMP_EQ_U64 = 0x000000ea # macro -SQ_V_CMP_LE_U64 = 0x000000eb # macro -SQ_V_CMP_GT_U64 = 0x000000ec # macro -SQ_V_CMP_NE_U64 = 0x000000ed # macro -SQ_V_CMP_GE_U64 = 0x000000ee # macro -SQ_V_CMP_T_U64 = 0x000000ef # macro -SQ_V_CMPX_F_I64 = 0x000000f0 # macro -SQ_V_CMPX_LT_I64 = 0x000000f1 # macro -SQ_V_CMPX_EQ_I64 = 0x000000f2 # macro -SQ_V_CMPX_LE_I64 = 0x000000f3 # macro -SQ_V_CMPX_GT_I64 = 0x000000f4 # macro -SQ_V_CMPX_NE_I64 = 0x000000f5 # macro -SQ_V_CMPX_GE_I64 = 0x000000f6 # macro -SQ_V_CMPX_T_I64 = 0x000000f7 # macro -SQ_V_CMPX_F_U64 = 0x000000f8 # macro -SQ_V_CMPX_LT_U64 = 0x000000f9 # macro -SQ_V_CMPX_EQ_U64 = 0x000000fa # macro -SQ_V_CMPX_LE_U64 = 0x000000fb # macro -SQ_V_CMPX_GT_U64 = 0x000000fc # macro -SQ_V_CMPX_NE_U64 = 0x000000fd # macro -SQ_V_CMPX_GE_U64 = 0x000000fe # macro -SQ_V_CMPX_T_U64 = 0x000000ff # macro -SQ_GS_OP_NOP = 0x00000000 # macro -SQ_GS_OP_CUT = 0x00000001 # macro -SQ_GS_OP_EMIT = 0x00000002 # macro -SQ_GS_OP_EMIT_CUT = 0x00000003 # macro -SQ_SRC_LDS_DIRECT = 0x000000fe # macro -SQ_ATTR0 = 0x00000000 # macro -SQ_EXP_GDS0 = 0x00000018 # macro -SQ_S_CMP_EQ_I32 = 0x00000000 # macro -SQ_S_CMP_LG_I32 = 0x00000001 # macro -SQ_S_CMP_GT_I32 = 0x00000002 # macro -SQ_S_CMP_GE_I32 = 0x00000003 # macro -SQ_S_CMP_LT_I32 = 0x00000004 # macro -SQ_S_CMP_LE_I32 = 0x00000005 # macro -SQ_S_CMP_EQ_U32 = 0x00000006 # macro -SQ_S_CMP_LG_U32 = 0x00000007 # macro -SQ_S_CMP_GT_U32 = 0x00000008 # macro -SQ_S_CMP_GE_U32 = 0x00000009 # macro -SQ_S_CMP_LT_U32 = 0x0000000a # macro -SQ_S_CMP_LE_U32 = 0x0000000b # macro -SQ_S_BITCMP0_B32 = 0x0000000c # macro -SQ_S_BITCMP1_B32 = 0x0000000d # macro -SQ_S_BITCMP0_B64 = 0x0000000e # macro -SQ_S_BITCMP1_B64 = 0x0000000f # macro -SQ_S_SETVSKIP = 0x00000010 # macro -SQ_S_SET_GPR_IDX_ON = 0x00000011 # macro -SQ_S_CMP_EQ_U64 = 0x00000012 # macro -SQ_S_CMP_LG_U64 = 0x00000013 # macro -SQ_TTMP0 = 0x0000006c # macro -SQ_TTMP1 = 0x0000006d # macro -SQ_TTMP2 = 0x0000006e # macro -SQ_TTMP3 = 0x0000006f # macro -SQ_TTMP4 = 0x00000070 # macro -SQ_TTMP5 = 0x00000071 # macro -SQ_TTMP6 = 0x00000072 # macro -SQ_TTMP7 = 0x00000073 # macro -SQ_TTMP8 = 0x00000074 # macro -SQ_TTMP9 = 0x00000075 # macro -SQ_TTMP10 = 0x00000076 # macro -SQ_TTMP11 = 0x00000077 # macro -SQ_TTMP12 = 0x00000078 # macro -SQ_TTMP13 = 0x00000079 # macro -SQ_TTMP14 = 0x0000007a # macro -SQ_TTMP15 = 0x0000007b # macro -SQ_SRC_VGPR0 = 0x00000100 # macro -SQ_BUFFER_LOAD_FORMAT_X = 0x00000000 # macro -SQ_BUFFER_LOAD_FORMAT_XY = 0x00000001 # macro -SQ_BUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro -SQ_BUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro -SQ_BUFFER_STORE_FORMAT_X = 0x00000004 # macro -SQ_BUFFER_STORE_FORMAT_XY = 0x00000005 # macro -SQ_BUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro -SQ_BUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro -SQ_BUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro -SQ_BUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro -SQ_BUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro -SQ_BUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro -SQ_BUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro -SQ_BUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro -SQ_BUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro -SQ_BUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro -SQ_BUFFER_LOAD_UBYTE = 0x00000010 # macro -SQ_BUFFER_LOAD_SBYTE = 0x00000011 # macro -SQ_BUFFER_LOAD_USHORT = 0x00000012 # macro -SQ_BUFFER_LOAD_SSHORT = 0x00000013 # macro -SQ_BUFFER_LOAD_DWORD = 0x00000014 # macro -SQ_BUFFER_LOAD_DWORDX2 = 0x00000015 # macro -SQ_BUFFER_LOAD_DWORDX3 = 0x00000016 # macro -SQ_BUFFER_LOAD_DWORDX4 = 0x00000017 # macro -SQ_BUFFER_STORE_BYTE = 0x00000018 # macro -SQ_BUFFER_STORE_SHORT = 0x0000001a # macro -SQ_BUFFER_STORE_DWORD = 0x0000001c # macro -SQ_BUFFER_STORE_DWORDX2 = 0x0000001d # macro -SQ_BUFFER_STORE_DWORDX3 = 0x0000001e # macro -SQ_BUFFER_STORE_DWORDX4 = 0x0000001f # macro -SQ_BUFFER_STORE_LDS_DWORD = 0x0000003d # macro -SQ_BUFFER_WBINVL1 = 0x0000003e # macro -SQ_BUFFER_WBINVL1_VOL = 0x0000003f # macro -SQ_BUFFER_ATOMIC_SWAP = 0x00000040 # macro -SQ_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro -SQ_BUFFER_ATOMIC_ADD = 0x00000042 # macro -SQ_BUFFER_ATOMIC_SUB = 0x00000043 # macro -SQ_BUFFER_ATOMIC_SMIN = 0x00000044 # macro -SQ_BUFFER_ATOMIC_UMIN = 0x00000045 # macro -SQ_BUFFER_ATOMIC_SMAX = 0x00000046 # macro -SQ_BUFFER_ATOMIC_UMAX = 0x00000047 # macro -SQ_BUFFER_ATOMIC_AND = 0x00000048 # macro -SQ_BUFFER_ATOMIC_OR = 0x00000049 # macro -SQ_BUFFER_ATOMIC_XOR = 0x0000004a # macro -SQ_BUFFER_ATOMIC_INC = 0x0000004b # macro -SQ_BUFFER_ATOMIC_DEC = 0x0000004c # macro -SQ_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro -SQ_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro -SQ_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro -SQ_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro -SQ_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro -SQ_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro -SQ_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro -SQ_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro -SQ_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro -SQ_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro -SQ_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro -SQ_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro -SQ_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro -SQ_SDWA_BYTE_0 = 0x00000000 # macro -SQ_SDWA_BYTE_1 = 0x00000001 # macro -SQ_SDWA_BYTE_2 = 0x00000002 # macro -SQ_SDWA_BYTE_3 = 0x00000003 # macro -SQ_SDWA_WORD_0 = 0x00000004 # macro -SQ_SDWA_WORD_1 = 0x00000005 # macro -SQ_SDWA_DWORD = 0x00000006 # macro -ROM_SIGNATURE = 0x0000aa55 # macro - -# values for enumeration 'GDS_PERFCOUNT_SELECT' -GDS_PERFCOUNT_SELECT__enumvalues = { - 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', - 1: 'GDS_PERF_SEL_DS_BANK_CONFL', - 2: 'GDS_PERF_SEL_WBUF_FLUSH', - 3: 'GDS_PERF_SEL_WR_COMP', - 4: 'GDS_PERF_SEL_WBUF_WR', - 5: 'GDS_PERF_SEL_RBUF_HIT', - 6: 'GDS_PERF_SEL_RBUF_MISS', - 7: 'GDS_PERF_SEL_SE0_SH0_NORET', - 8: 'GDS_PERF_SEL_SE0_SH0_RET', - 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', - 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', - 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', - 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', - 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', - 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', - 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', - 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', - 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', - 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', - 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', - 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', - 21: 'GDS_PERF_SEL_SE0_SH1_NORET', - 22: 'GDS_PERF_SEL_SE0_SH1_RET', - 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', - 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', - 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', - 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', - 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', - 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', - 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', - 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', - 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', - 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', - 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', - 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', - 35: 'GDS_PERF_SEL_SE1_SH0_NORET', - 36: 'GDS_PERF_SEL_SE1_SH0_RET', - 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', - 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', - 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', - 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', - 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', - 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', - 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', - 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', - 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', - 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', - 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', - 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', - 49: 'GDS_PERF_SEL_SE1_SH1_NORET', - 50: 'GDS_PERF_SEL_SE1_SH1_RET', - 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', - 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', - 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', - 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', - 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', - 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', - 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', - 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', - 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', - 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', - 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', - 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', - 63: 'GDS_PERF_SEL_SE2_SH0_NORET', - 64: 'GDS_PERF_SEL_SE2_SH0_RET', - 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', - 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', - 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', - 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', - 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', - 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', - 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', - 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', - 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', - 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', - 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', - 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', - 77: 'GDS_PERF_SEL_SE2_SH1_NORET', - 78: 'GDS_PERF_SEL_SE2_SH1_RET', - 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', - 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', - 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', - 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', - 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', - 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', - 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', - 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', - 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', - 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', - 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', - 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', - 91: 'GDS_PERF_SEL_SE3_SH0_NORET', - 92: 'GDS_PERF_SEL_SE3_SH0_RET', - 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', - 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', - 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', - 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', - 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', - 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', - 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', - 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', - 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', - 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', - 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', - 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', - 105: 'GDS_PERF_SEL_SE3_SH1_NORET', - 106: 'GDS_PERF_SEL_SE3_SH1_RET', - 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', - 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', - 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', - 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', - 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', - 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', - 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', - 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', - 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', - 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', - 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', - 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', - 119: 'GDS_PERF_SEL_GWS_RELEASED', - 120: 'GDS_PERF_SEL_GWS_BYPASS', -} -GDS_PERF_SEL_DS_ADDR_CONFL = 0 -GDS_PERF_SEL_DS_BANK_CONFL = 1 -GDS_PERF_SEL_WBUF_FLUSH = 2 -GDS_PERF_SEL_WR_COMP = 3 -GDS_PERF_SEL_WBUF_WR = 4 -GDS_PERF_SEL_RBUF_HIT = 5 -GDS_PERF_SEL_RBUF_MISS = 6 -GDS_PERF_SEL_SE0_SH0_NORET = 7 -GDS_PERF_SEL_SE0_SH0_RET = 8 -GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 -GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 -GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 -GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 -GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 -GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 -GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 -GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 -GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 -GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 -GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 -GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 -GDS_PERF_SEL_SE0_SH1_NORET = 21 -GDS_PERF_SEL_SE0_SH1_RET = 22 -GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 -GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 -GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 -GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 -GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 -GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 -GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 -GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 -GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 -GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 -GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 -GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 -GDS_PERF_SEL_SE1_SH0_NORET = 35 -GDS_PERF_SEL_SE1_SH0_RET = 36 -GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 -GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 -GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 -GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 -GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 -GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 -GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 -GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 -GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 -GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 -GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 -GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 -GDS_PERF_SEL_SE1_SH1_NORET = 49 -GDS_PERF_SEL_SE1_SH1_RET = 50 -GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 -GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 -GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 -GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 -GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 -GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 -GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 -GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 -GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 -GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 -GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 -GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 -GDS_PERF_SEL_SE2_SH0_NORET = 63 -GDS_PERF_SEL_SE2_SH0_RET = 64 -GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 -GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 -GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 -GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 -GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 -GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 -GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 -GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 -GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 -GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 -GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 -GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 -GDS_PERF_SEL_SE2_SH1_NORET = 77 -GDS_PERF_SEL_SE2_SH1_RET = 78 -GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 -GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 -GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 -GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 -GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 -GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 -GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 -GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 -GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 -GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 -GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 -GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 -GDS_PERF_SEL_SE3_SH0_NORET = 91 -GDS_PERF_SEL_SE3_SH0_RET = 92 -GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 -GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 -GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 -GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 -GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 -GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 -GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 -GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 -GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 -GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 -GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 -GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 -GDS_PERF_SEL_SE3_SH1_NORET = 105 -GDS_PERF_SEL_SE3_SH1_RET = 106 -GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 -GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 -GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 -GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 -GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 -GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 -GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 -GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 -GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 -GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 -GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 -GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 -GDS_PERF_SEL_GWS_RELEASED = 119 -GDS_PERF_SEL_GWS_BYPASS = 120 -GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL' -MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'NO_FORCE_REQUEST', - 1: 'FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FORCE_DEEP_SLEEP_REQUEST', - 3: 'FORCE_SHUT_DOWN_REQUEST', -} -NO_FORCE_REQUEST = 0 -FORCE_LIGHT_SLEEP_REQUEST = 1 -FORCE_DEEP_SLEEP_REQUEST = 2 -FORCE_SHUT_DOWN_REQUEST = 3 -MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL2' -MEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'NO_FORCE_REQ', - 1: 'FORCE_LIGHT_SLEEP_REQ', -} -NO_FORCE_REQ = 0 -FORCE_LIGHT_SLEEP_REQ = 1 -MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_CTRL' -MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'ENABLE_MEM_PWR_CTRL', - 1: 'DISABLE_MEM_PWR_CTRL', -} -ENABLE_MEM_PWR_CTRL = 0 -DISABLE_MEM_PWR_CTRL = 1 -MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL' -MEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DYNAMIC_SHUT_DOWN_ENABLE = 0 -DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL2' -MEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DYNAMIC_DEEP_SLEEP_EN', - 1: 'DYNAMIC_LIGHT_SLEEP_EN', -} -DYNAMIC_DEEP_SLEEP_EN = 0 -DYNAMIC_LIGHT_SLEEP_EN = 1 -MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'RowSize' -RowSize__enumvalues = { - 0: 'ADDR_CONFIG_1KB_ROW', - 1: 'ADDR_CONFIG_2KB_ROW', - 2: 'ADDR_CONFIG_4KB_ROW', -} -ADDR_CONFIG_1KB_ROW = 0 -ADDR_CONFIG_2KB_ROW = 1 -ADDR_CONFIG_4KB_ROW = 2 -RowSize = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceEndian' -SurfaceEndian__enumvalues = { - 0: 'ENDIAN_NONE', - 1: 'ENDIAN_8IN16', - 2: 'ENDIAN_8IN32', - 3: 'ENDIAN_8IN64', -} -ENDIAN_NONE = 0 -ENDIAN_8IN16 = 1 -ENDIAN_8IN32 = 2 -ENDIAN_8IN64 = 3 -SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'ArrayMode' -ArrayMode__enumvalues = { - 0: 'ARRAY_LINEAR_GENERAL', - 1: 'ARRAY_LINEAR_ALIGNED', - 2: 'ARRAY_1D_TILED_THIN1', - 3: 'ARRAY_1D_TILED_THICK', - 4: 'ARRAY_2D_TILED_THIN1', - 5: 'ARRAY_PRT_TILED_THIN1', - 6: 'ARRAY_PRT_2D_TILED_THIN1', - 7: 'ARRAY_2D_TILED_THICK', - 8: 'ARRAY_2D_TILED_XTHICK', - 9: 'ARRAY_PRT_TILED_THICK', - 10: 'ARRAY_PRT_2D_TILED_THICK', - 11: 'ARRAY_PRT_3D_TILED_THIN1', - 12: 'ARRAY_3D_TILED_THIN1', - 13: 'ARRAY_3D_TILED_THICK', - 14: 'ARRAY_3D_TILED_XTHICK', - 15: 'ARRAY_PRT_3D_TILED_THICK', -} -ARRAY_LINEAR_GENERAL = 0 -ARRAY_LINEAR_ALIGNED = 1 -ARRAY_1D_TILED_THIN1 = 2 -ARRAY_1D_TILED_THICK = 3 -ARRAY_2D_TILED_THIN1 = 4 -ARRAY_PRT_TILED_THIN1 = 5 -ARRAY_PRT_2D_TILED_THIN1 = 6 -ARRAY_2D_TILED_THICK = 7 -ARRAY_2D_TILED_XTHICK = 8 -ARRAY_PRT_TILED_THICK = 9 -ARRAY_PRT_2D_TILED_THICK = 10 -ARRAY_PRT_3D_TILED_THIN1 = 11 -ARRAY_3D_TILED_THIN1 = 12 -ARRAY_3D_TILED_THICK = 13 -ARRAY_3D_TILED_XTHICK = 14 -ARRAY_PRT_3D_TILED_THICK = 15 -ArrayMode = ctypes.c_uint32 # enum - -# values for enumeration 'NumPipes' -NumPipes__enumvalues = { - 0: 'ADDR_CONFIG_1_PIPE', - 1: 'ADDR_CONFIG_2_PIPE', - 2: 'ADDR_CONFIG_4_PIPE', - 3: 'ADDR_CONFIG_8_PIPE', - 4: 'ADDR_CONFIG_16_PIPE', - 5: 'ADDR_CONFIG_32_PIPE', -} -ADDR_CONFIG_1_PIPE = 0 -ADDR_CONFIG_2_PIPE = 1 -ADDR_CONFIG_4_PIPE = 2 -ADDR_CONFIG_8_PIPE = 3 -ADDR_CONFIG_16_PIPE = 4 -ADDR_CONFIG_32_PIPE = 5 -NumPipes = ctypes.c_uint32 # enum - -# values for enumeration 'NumBanksConfig' -NumBanksConfig__enumvalues = { - 0: 'ADDR_CONFIG_1_BANK', - 1: 'ADDR_CONFIG_2_BANK', - 2: 'ADDR_CONFIG_4_BANK', - 3: 'ADDR_CONFIG_8_BANK', - 4: 'ADDR_CONFIG_16_BANK', -} -ADDR_CONFIG_1_BANK = 0 -ADDR_CONFIG_2_BANK = 1 -ADDR_CONFIG_4_BANK = 2 -ADDR_CONFIG_8_BANK = 3 -ADDR_CONFIG_16_BANK = 4 -NumBanksConfig = ctypes.c_uint32 # enum - -# values for enumeration 'PipeInterleaveSize' -PipeInterleaveSize__enumvalues = { - 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', - 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', - 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', - 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', -} -ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 -ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 -ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 -ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 -PipeInterleaveSize = ctypes.c_uint32 # enum - -# values for enumeration 'BankInterleaveSize' -BankInterleaveSize__enumvalues = { - 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', - 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', - 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', - 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', -} -ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 -ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 -ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 -ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 -BankInterleaveSize = ctypes.c_uint32 # enum - -# values for enumeration 'NumShaderEngines' -NumShaderEngines__enumvalues = { - 0: 'ADDR_CONFIG_1_SHADER_ENGINE', - 1: 'ADDR_CONFIG_2_SHADER_ENGINE', - 2: 'ADDR_CONFIG_4_SHADER_ENGINE', - 3: 'ADDR_CONFIG_8_SHADER_ENGINE', -} -ADDR_CONFIG_1_SHADER_ENGINE = 0 -ADDR_CONFIG_2_SHADER_ENGINE = 1 -ADDR_CONFIG_4_SHADER_ENGINE = 2 -ADDR_CONFIG_8_SHADER_ENGINE = 3 -NumShaderEngines = ctypes.c_uint32 # enum - -# values for enumeration 'NumRbPerShaderEngine' -NumRbPerShaderEngine__enumvalues = { - 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', - 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', - 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', -} -ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 -ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 -ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 -NumRbPerShaderEngine = ctypes.c_uint32 # enum - -# values for enumeration 'NumGPUs' -NumGPUs__enumvalues = { - 0: 'ADDR_CONFIG_1_GPU', - 1: 'ADDR_CONFIG_2_GPU', - 2: 'ADDR_CONFIG_4_GPU', - 3: 'ADDR_CONFIG_8_GPU', -} -ADDR_CONFIG_1_GPU = 0 -ADDR_CONFIG_2_GPU = 1 -ADDR_CONFIG_4_GPU = 2 -ADDR_CONFIG_8_GPU = 3 -NumGPUs = ctypes.c_uint32 # enum - -# values for enumeration 'NumMaxCompressedFragments' -NumMaxCompressedFragments__enumvalues = { - 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', - 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', - 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', - 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', -} -ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 -ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 -ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 -ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 -NumMaxCompressedFragments = ctypes.c_uint32 # enum - -# values for enumeration 'ShaderEngineTileSize' -ShaderEngineTileSize__enumvalues = { - 0: 'ADDR_CONFIG_SE_TILE_16', - 1: 'ADDR_CONFIG_SE_TILE_32', -} -ADDR_CONFIG_SE_TILE_16 = 0 -ADDR_CONFIG_SE_TILE_32 = 1 -ShaderEngineTileSize = ctypes.c_uint32 # enum - -# values for enumeration 'MultiGPUTileSize' -MultiGPUTileSize__enumvalues = { - 0: 'ADDR_CONFIG_GPU_TILE_16', - 1: 'ADDR_CONFIG_GPU_TILE_32', - 2: 'ADDR_CONFIG_GPU_TILE_64', - 3: 'ADDR_CONFIG_GPU_TILE_128', -} -ADDR_CONFIG_GPU_TILE_16 = 0 -ADDR_CONFIG_GPU_TILE_32 = 1 -ADDR_CONFIG_GPU_TILE_64 = 2 -ADDR_CONFIG_GPU_TILE_128 = 3 -MultiGPUTileSize = ctypes.c_uint32 # enum - -# values for enumeration 'NumLowerPipes' -NumLowerPipes__enumvalues = { - 0: 'ADDR_CONFIG_1_LOWER_PIPES', - 1: 'ADDR_CONFIG_2_LOWER_PIPES', -} -ADDR_CONFIG_1_LOWER_PIPES = 0 -ADDR_CONFIG_2_LOWER_PIPES = 1 -NumLowerPipes = ctypes.c_uint32 # enum - -# values for enumeration 'ColorTransform' -ColorTransform__enumvalues = { - 0: 'DCC_CT_AUTO', - 1: 'DCC_CT_NONE', - 2: 'ABGR_TO_A_BG_G_RB', - 3: 'BGRA_TO_BG_G_RB_A', -} -DCC_CT_AUTO = 0 -DCC_CT_NONE = 1 -ABGR_TO_A_BG_G_RB = 2 -BGRA_TO_BG_G_RB_A = 3 -ColorTransform = ctypes.c_uint32 # enum - -# values for enumeration 'CompareRef' -CompareRef__enumvalues = { - 0: 'REF_NEVER', - 1: 'REF_LESS', - 2: 'REF_EQUAL', - 3: 'REF_LEQUAL', - 4: 'REF_GREATER', - 5: 'REF_NOTEQUAL', - 6: 'REF_GEQUAL', - 7: 'REF_ALWAYS', -} -REF_NEVER = 0 -REF_LESS = 1 -REF_EQUAL = 2 -REF_LEQUAL = 3 -REF_GREATER = 4 -REF_NOTEQUAL = 5 -REF_GEQUAL = 6 -REF_ALWAYS = 7 -CompareRef = ctypes.c_uint32 # enum - -# values for enumeration 'ReadSize' -ReadSize__enumvalues = { - 0: 'READ_256_BITS', - 1: 'READ_512_BITS', -} -READ_256_BITS = 0 -READ_512_BITS = 1 -ReadSize = ctypes.c_uint32 # enum - -# values for enumeration 'DepthFormat' -DepthFormat__enumvalues = { - 0: 'DEPTH_INVALID', - 1: 'DEPTH_16', - 2: 'DEPTH_X8_24', - 3: 'DEPTH_8_24', - 4: 'DEPTH_X8_24_FLOAT', - 5: 'DEPTH_8_24_FLOAT', - 6: 'DEPTH_32_FLOAT', - 7: 'DEPTH_X24_8_32_FLOAT', -} -DEPTH_INVALID = 0 -DEPTH_16 = 1 -DEPTH_X8_24 = 2 -DEPTH_8_24 = 3 -DEPTH_X8_24_FLOAT = 4 -DEPTH_8_24_FLOAT = 5 -DEPTH_32_FLOAT = 6 -DEPTH_X24_8_32_FLOAT = 7 -DepthFormat = ctypes.c_uint32 # enum - -# values for enumeration 'ZFormat' -ZFormat__enumvalues = { - 0: 'Z_INVALID', - 1: 'Z_16', - 2: 'Z_24', - 3: 'Z_32_FLOAT', -} -Z_INVALID = 0 -Z_16 = 1 -Z_24 = 2 -Z_32_FLOAT = 3 -ZFormat = ctypes.c_uint32 # enum - -# values for enumeration 'StencilFormat' -StencilFormat__enumvalues = { - 0: 'STENCIL_INVALID', - 1: 'STENCIL_8', -} -STENCIL_INVALID = 0 -STENCIL_8 = 1 -StencilFormat = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskMode' -CmaskMode__enumvalues = { - 0: 'CMASK_CLEAR_NONE', - 1: 'CMASK_CLEAR_ONE', - 2: 'CMASK_CLEAR_ALL', - 3: 'CMASK_ANY_EXPANDED', - 4: 'CMASK_ALPHA0_FRAG1', - 5: 'CMASK_ALPHA0_FRAG2', - 6: 'CMASK_ALPHA0_FRAG4', - 7: 'CMASK_ALPHA0_FRAGS', - 8: 'CMASK_ALPHA1_FRAG1', - 9: 'CMASK_ALPHA1_FRAG2', - 10: 'CMASK_ALPHA1_FRAG4', - 11: 'CMASK_ALPHA1_FRAGS', - 12: 'CMASK_ALPHAX_FRAG1', - 13: 'CMASK_ALPHAX_FRAG2', - 14: 'CMASK_ALPHAX_FRAG4', - 15: 'CMASK_ALPHAX_FRAGS', -} -CMASK_CLEAR_NONE = 0 -CMASK_CLEAR_ONE = 1 -CMASK_CLEAR_ALL = 2 -CMASK_ANY_EXPANDED = 3 -CMASK_ALPHA0_FRAG1 = 4 -CMASK_ALPHA0_FRAG2 = 5 -CMASK_ALPHA0_FRAG4 = 6 -CMASK_ALPHA0_FRAGS = 7 -CMASK_ALPHA1_FRAG1 = 8 -CMASK_ALPHA1_FRAG2 = 9 -CMASK_ALPHA1_FRAG4 = 10 -CMASK_ALPHA1_FRAGS = 11 -CMASK_ALPHAX_FRAG1 = 12 -CMASK_ALPHAX_FRAG2 = 13 -CMASK_ALPHAX_FRAG4 = 14 -CMASK_ALPHAX_FRAGS = 15 -CmaskMode = ctypes.c_uint32 # enum - -# values for enumeration 'QuadExportFormat' -QuadExportFormat__enumvalues = { - 0: 'EXPORT_UNUSED', - 1: 'EXPORT_32_R', - 2: 'EXPORT_32_GR', - 3: 'EXPORT_32_AR', - 4: 'EXPORT_FP16_ABGR', - 5: 'EXPORT_UNSIGNED16_ABGR', - 6: 'EXPORT_SIGNED16_ABGR', - 7: 'EXPORT_32_ABGR', - 8: 'EXPORT_32BPP_8PIX', - 9: 'EXPORT_16_16_UNSIGNED_8PIX', - 10: 'EXPORT_16_16_SIGNED_8PIX', - 11: 'EXPORT_16_16_FLOAT_8PIX', -} -EXPORT_UNUSED = 0 -EXPORT_32_R = 1 -EXPORT_32_GR = 2 -EXPORT_32_AR = 3 -EXPORT_FP16_ABGR = 4 -EXPORT_UNSIGNED16_ABGR = 5 -EXPORT_SIGNED16_ABGR = 6 -EXPORT_32_ABGR = 7 -EXPORT_32BPP_8PIX = 8 -EXPORT_16_16_UNSIGNED_8PIX = 9 -EXPORT_16_16_SIGNED_8PIX = 10 -EXPORT_16_16_FLOAT_8PIX = 11 -QuadExportFormat = ctypes.c_uint32 # enum - -# values for enumeration 'QuadExportFormatOld' -QuadExportFormatOld__enumvalues = { - 0: 'EXPORT_4P_32BPC_ABGR', - 1: 'EXPORT_4P_16BPC_ABGR', - 2: 'EXPORT_4P_32BPC_GR', - 3: 'EXPORT_4P_32BPC_AR', - 4: 'EXPORT_2P_32BPC_ABGR', - 5: 'EXPORT_8P_32BPC_R', -} -EXPORT_4P_32BPC_ABGR = 0 -EXPORT_4P_16BPC_ABGR = 1 -EXPORT_4P_32BPC_GR = 2 -EXPORT_4P_32BPC_AR = 3 -EXPORT_2P_32BPC_ABGR = 4 -EXPORT_8P_32BPC_R = 5 -QuadExportFormatOld = ctypes.c_uint32 # enum - -# values for enumeration 'ColorFormat' -ColorFormat__enumvalues = { - 0: 'COLOR_INVALID', - 1: 'COLOR_8', - 2: 'COLOR_16', - 3: 'COLOR_8_8', - 4: 'COLOR_32', - 5: 'COLOR_16_16', - 6: 'COLOR_10_11_11', - 7: 'COLOR_11_11_10', - 8: 'COLOR_10_10_10_2', - 9: 'COLOR_2_10_10_10', - 10: 'COLOR_8_8_8_8', - 11: 'COLOR_32_32', - 12: 'COLOR_16_16_16_16', - 13: 'COLOR_RESERVED_13', - 14: 'COLOR_32_32_32_32', - 15: 'COLOR_RESERVED_15', - 16: 'COLOR_5_6_5', - 17: 'COLOR_1_5_5_5', - 18: 'COLOR_5_5_5_1', - 19: 'COLOR_4_4_4_4', - 20: 'COLOR_8_24', - 21: 'COLOR_24_8', - 22: 'COLOR_X24_8_32_FLOAT', - 23: 'COLOR_RESERVED_23', - 24: 'COLOR_RESERVED_24', - 25: 'COLOR_RESERVED_25', - 26: 'COLOR_RESERVED_26', - 27: 'COLOR_RESERVED_27', - 28: 'COLOR_RESERVED_28', - 29: 'COLOR_RESERVED_29', - 30: 'COLOR_RESERVED_30', - 31: 'COLOR_2_10_10_10_6E4', -} -COLOR_INVALID = 0 -COLOR_8 = 1 -COLOR_16 = 2 -COLOR_8_8 = 3 -COLOR_32 = 4 -COLOR_16_16 = 5 -COLOR_10_11_11 = 6 -COLOR_11_11_10 = 7 -COLOR_10_10_10_2 = 8 -COLOR_2_10_10_10 = 9 -COLOR_8_8_8_8 = 10 -COLOR_32_32 = 11 -COLOR_16_16_16_16 = 12 -COLOR_RESERVED_13 = 13 -COLOR_32_32_32_32 = 14 -COLOR_RESERVED_15 = 15 -COLOR_5_6_5 = 16 -COLOR_1_5_5_5 = 17 -COLOR_5_5_5_1 = 18 -COLOR_4_4_4_4 = 19 -COLOR_8_24 = 20 -COLOR_24_8 = 21 -COLOR_X24_8_32_FLOAT = 22 -COLOR_RESERVED_23 = 23 -COLOR_RESERVED_24 = 24 -COLOR_RESERVED_25 = 25 -COLOR_RESERVED_26 = 26 -COLOR_RESERVED_27 = 27 -COLOR_RESERVED_28 = 28 -COLOR_RESERVED_29 = 29 -COLOR_RESERVED_30 = 30 -COLOR_2_10_10_10_6E4 = 31 -ColorFormat = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceFormat' -SurfaceFormat__enumvalues = { - 0: 'FMT_INVALID', - 1: 'FMT_8', - 2: 'FMT_16', - 3: 'FMT_8_8', - 4: 'FMT_32', - 5: 'FMT_16_16', - 6: 'FMT_10_11_11', - 7: 'FMT_11_11_10', - 8: 'FMT_10_10_10_2', - 9: 'FMT_2_10_10_10', - 10: 'FMT_8_8_8_8', - 11: 'FMT_32_32', - 12: 'FMT_16_16_16_16', - 13: 'FMT_32_32_32', - 14: 'FMT_32_32_32_32', - 15: 'FMT_RESERVED_4', - 16: 'FMT_5_6_5', - 17: 'FMT_1_5_5_5', - 18: 'FMT_5_5_5_1', - 19: 'FMT_4_4_4_4', - 20: 'FMT_8_24', - 21: 'FMT_24_8', - 22: 'FMT_X24_8_32_FLOAT', - 23: 'FMT_RESERVED_33', - 24: 'FMT_11_11_10_FLOAT', - 25: 'FMT_16_FLOAT', - 26: 'FMT_32_FLOAT', - 27: 'FMT_16_16_FLOAT', - 28: 'FMT_8_24_FLOAT', - 29: 'FMT_24_8_FLOAT', - 30: 'FMT_32_32_FLOAT', - 31: 'FMT_10_11_11_FLOAT', - 32: 'FMT_16_16_16_16_FLOAT', - 33: 'FMT_3_3_2', - 34: 'FMT_6_5_5', - 35: 'FMT_32_32_32_32_FLOAT', - 36: 'FMT_RESERVED_36', - 37: 'FMT_1', - 38: 'FMT_1_REVERSED', - 39: 'FMT_GB_GR', - 40: 'FMT_BG_RG', - 41: 'FMT_32_AS_8', - 42: 'FMT_32_AS_8_8', - 43: 'FMT_5_9_9_9_SHAREDEXP', - 44: 'FMT_8_8_8', - 45: 'FMT_16_16_16', - 46: 'FMT_16_16_16_FLOAT', - 47: 'FMT_4_4', - 48: 'FMT_32_32_32_FLOAT', - 49: 'FMT_BC1', - 50: 'FMT_BC2', - 51: 'FMT_BC3', - 52: 'FMT_BC4', - 53: 'FMT_BC5', - 54: 'FMT_BC6', - 55: 'FMT_BC7', - 56: 'FMT_32_AS_32_32_32_32', - 57: 'FMT_APC3', - 58: 'FMT_APC4', - 59: 'FMT_APC5', - 60: 'FMT_APC6', - 61: 'FMT_APC7', - 62: 'FMT_CTX1', - 63: 'FMT_RESERVED_63', -} -FMT_INVALID = 0 -FMT_8 = 1 -FMT_16 = 2 -FMT_8_8 = 3 -FMT_32 = 4 -FMT_16_16 = 5 -FMT_10_11_11 = 6 -FMT_11_11_10 = 7 -FMT_10_10_10_2 = 8 -FMT_2_10_10_10 = 9 -FMT_8_8_8_8 = 10 -FMT_32_32 = 11 -FMT_16_16_16_16 = 12 -FMT_32_32_32 = 13 -FMT_32_32_32_32 = 14 -FMT_RESERVED_4 = 15 -FMT_5_6_5 = 16 -FMT_1_5_5_5 = 17 -FMT_5_5_5_1 = 18 -FMT_4_4_4_4 = 19 -FMT_8_24 = 20 -FMT_24_8 = 21 -FMT_X24_8_32_FLOAT = 22 -FMT_RESERVED_33 = 23 -FMT_11_11_10_FLOAT = 24 -FMT_16_FLOAT = 25 -FMT_32_FLOAT = 26 -FMT_16_16_FLOAT = 27 -FMT_8_24_FLOAT = 28 -FMT_24_8_FLOAT = 29 -FMT_32_32_FLOAT = 30 -FMT_10_11_11_FLOAT = 31 -FMT_16_16_16_16_FLOAT = 32 -FMT_3_3_2 = 33 -FMT_6_5_5 = 34 -FMT_32_32_32_32_FLOAT = 35 -FMT_RESERVED_36 = 36 -FMT_1 = 37 -FMT_1_REVERSED = 38 -FMT_GB_GR = 39 -FMT_BG_RG = 40 -FMT_32_AS_8 = 41 -FMT_32_AS_8_8 = 42 -FMT_5_9_9_9_SHAREDEXP = 43 -FMT_8_8_8 = 44 -FMT_16_16_16 = 45 -FMT_16_16_16_FLOAT = 46 -FMT_4_4 = 47 -FMT_32_32_32_FLOAT = 48 -FMT_BC1 = 49 -FMT_BC2 = 50 -FMT_BC3 = 51 -FMT_BC4 = 52 -FMT_BC5 = 53 -FMT_BC6 = 54 -FMT_BC7 = 55 -FMT_32_AS_32_32_32_32 = 56 -FMT_APC3 = 57 -FMT_APC4 = 58 -FMT_APC5 = 59 -FMT_APC6 = 60 -FMT_APC7 = 61 -FMT_CTX1 = 62 -FMT_RESERVED_63 = 63 -SurfaceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'BUF_DATA_FORMAT' -BUF_DATA_FORMAT__enumvalues = { - 0: 'BUF_DATA_FORMAT_INVALID', - 1: 'BUF_DATA_FORMAT_8', - 2: 'BUF_DATA_FORMAT_16', - 3: 'BUF_DATA_FORMAT_8_8', - 4: 'BUF_DATA_FORMAT_32', - 5: 'BUF_DATA_FORMAT_16_16', - 6: 'BUF_DATA_FORMAT_10_11_11', - 7: 'BUF_DATA_FORMAT_11_11_10', - 8: 'BUF_DATA_FORMAT_10_10_10_2', - 9: 'BUF_DATA_FORMAT_2_10_10_10', - 10: 'BUF_DATA_FORMAT_8_8_8_8', - 11: 'BUF_DATA_FORMAT_32_32', - 12: 'BUF_DATA_FORMAT_16_16_16_16', - 13: 'BUF_DATA_FORMAT_32_32_32', - 14: 'BUF_DATA_FORMAT_32_32_32_32', - 15: 'BUF_DATA_FORMAT_RESERVED_15', -} -BUF_DATA_FORMAT_INVALID = 0 -BUF_DATA_FORMAT_8 = 1 -BUF_DATA_FORMAT_16 = 2 -BUF_DATA_FORMAT_8_8 = 3 -BUF_DATA_FORMAT_32 = 4 -BUF_DATA_FORMAT_16_16 = 5 -BUF_DATA_FORMAT_10_11_11 = 6 -BUF_DATA_FORMAT_11_11_10 = 7 -BUF_DATA_FORMAT_10_10_10_2 = 8 -BUF_DATA_FORMAT_2_10_10_10 = 9 -BUF_DATA_FORMAT_8_8_8_8 = 10 -BUF_DATA_FORMAT_32_32 = 11 -BUF_DATA_FORMAT_16_16_16_16 = 12 -BUF_DATA_FORMAT_32_32_32 = 13 -BUF_DATA_FORMAT_32_32_32_32 = 14 -BUF_DATA_FORMAT_RESERVED_15 = 15 -BUF_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_DATA_FORMAT' -IMG_DATA_FORMAT__enumvalues = { - 0: 'IMG_DATA_FORMAT_INVALID', - 1: 'IMG_DATA_FORMAT_8', - 2: 'IMG_DATA_FORMAT_16', - 3: 'IMG_DATA_FORMAT_8_8', - 4: 'IMG_DATA_FORMAT_32', - 5: 'IMG_DATA_FORMAT_16_16', - 6: 'IMG_DATA_FORMAT_10_11_11', - 7: 'IMG_DATA_FORMAT_11_11_10', - 8: 'IMG_DATA_FORMAT_10_10_10_2', - 9: 'IMG_DATA_FORMAT_2_10_10_10', - 10: 'IMG_DATA_FORMAT_8_8_8_8', - 11: 'IMG_DATA_FORMAT_32_32', - 12: 'IMG_DATA_FORMAT_16_16_16_16', - 13: 'IMG_DATA_FORMAT_32_32_32', - 14: 'IMG_DATA_FORMAT_32_32_32_32', - 15: 'IMG_DATA_FORMAT_RESERVED_15', - 16: 'IMG_DATA_FORMAT_5_6_5', - 17: 'IMG_DATA_FORMAT_1_5_5_5', - 18: 'IMG_DATA_FORMAT_5_5_5_1', - 19: 'IMG_DATA_FORMAT_4_4_4_4', - 20: 'IMG_DATA_FORMAT_8_24', - 21: 'IMG_DATA_FORMAT_24_8', - 22: 'IMG_DATA_FORMAT_X24_8_32', - 23: 'IMG_DATA_FORMAT_8_AS_8_8_8_8', - 24: 'IMG_DATA_FORMAT_ETC2_RGB', - 25: 'IMG_DATA_FORMAT_ETC2_RGBA', - 26: 'IMG_DATA_FORMAT_ETC2_R', - 27: 'IMG_DATA_FORMAT_ETC2_RG', - 28: 'IMG_DATA_FORMAT_ETC2_RGBA1', - 29: 'IMG_DATA_FORMAT_RESERVED_29', - 30: 'IMG_DATA_FORMAT_RESERVED_30', - 31: 'IMG_DATA_FORMAT_6E4', - 32: 'IMG_DATA_FORMAT_GB_GR', - 33: 'IMG_DATA_FORMAT_BG_RG', - 34: 'IMG_DATA_FORMAT_5_9_9_9', - 35: 'IMG_DATA_FORMAT_BC1', - 36: 'IMG_DATA_FORMAT_BC2', - 37: 'IMG_DATA_FORMAT_BC3', - 38: 'IMG_DATA_FORMAT_BC4', - 39: 'IMG_DATA_FORMAT_BC5', - 40: 'IMG_DATA_FORMAT_BC6', - 41: 'IMG_DATA_FORMAT_BC7', - 42: 'IMG_DATA_FORMAT_16_AS_32_32', - 43: 'IMG_DATA_FORMAT_16_AS_16_16_16_16', - 44: 'IMG_DATA_FORMAT_16_AS_32_32_32_32', - 45: 'IMG_DATA_FORMAT_FMASK', - 46: 'IMG_DATA_FORMAT_ASTC_2D_LDR', - 47: 'IMG_DATA_FORMAT_ASTC_2D_HDR', - 48: 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', - 49: 'IMG_DATA_FORMAT_ASTC_3D_LDR', - 50: 'IMG_DATA_FORMAT_ASTC_3D_HDR', - 51: 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', - 52: 'IMG_DATA_FORMAT_N_IN_16', - 53: 'IMG_DATA_FORMAT_N_IN_16_16', - 54: 'IMG_DATA_FORMAT_N_IN_16_16_16_16', - 55: 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', - 56: 'IMG_DATA_FORMAT_RESERVED_56', - 57: 'IMG_DATA_FORMAT_4_4', - 58: 'IMG_DATA_FORMAT_6_5_5', - 59: 'IMG_DATA_FORMAT_RESERVED_59', - 60: 'IMG_DATA_FORMAT_RESERVED_60', - 61: 'IMG_DATA_FORMAT_8_AS_32', - 62: 'IMG_DATA_FORMAT_8_AS_32_32', - 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', -} -IMG_DATA_FORMAT_INVALID = 0 -IMG_DATA_FORMAT_8 = 1 -IMG_DATA_FORMAT_16 = 2 -IMG_DATA_FORMAT_8_8 = 3 -IMG_DATA_FORMAT_32 = 4 -IMG_DATA_FORMAT_16_16 = 5 -IMG_DATA_FORMAT_10_11_11 = 6 -IMG_DATA_FORMAT_11_11_10 = 7 -IMG_DATA_FORMAT_10_10_10_2 = 8 -IMG_DATA_FORMAT_2_10_10_10 = 9 -IMG_DATA_FORMAT_8_8_8_8 = 10 -IMG_DATA_FORMAT_32_32 = 11 -IMG_DATA_FORMAT_16_16_16_16 = 12 -IMG_DATA_FORMAT_32_32_32 = 13 -IMG_DATA_FORMAT_32_32_32_32 = 14 -IMG_DATA_FORMAT_RESERVED_15 = 15 -IMG_DATA_FORMAT_5_6_5 = 16 -IMG_DATA_FORMAT_1_5_5_5 = 17 -IMG_DATA_FORMAT_5_5_5_1 = 18 -IMG_DATA_FORMAT_4_4_4_4 = 19 -IMG_DATA_FORMAT_8_24 = 20 -IMG_DATA_FORMAT_24_8 = 21 -IMG_DATA_FORMAT_X24_8_32 = 22 -IMG_DATA_FORMAT_8_AS_8_8_8_8 = 23 -IMG_DATA_FORMAT_ETC2_RGB = 24 -IMG_DATA_FORMAT_ETC2_RGBA = 25 -IMG_DATA_FORMAT_ETC2_R = 26 -IMG_DATA_FORMAT_ETC2_RG = 27 -IMG_DATA_FORMAT_ETC2_RGBA1 = 28 -IMG_DATA_FORMAT_RESERVED_29 = 29 -IMG_DATA_FORMAT_RESERVED_30 = 30 -IMG_DATA_FORMAT_6E4 = 31 -IMG_DATA_FORMAT_GB_GR = 32 -IMG_DATA_FORMAT_BG_RG = 33 -IMG_DATA_FORMAT_5_9_9_9 = 34 -IMG_DATA_FORMAT_BC1 = 35 -IMG_DATA_FORMAT_BC2 = 36 -IMG_DATA_FORMAT_BC3 = 37 -IMG_DATA_FORMAT_BC4 = 38 -IMG_DATA_FORMAT_BC5 = 39 -IMG_DATA_FORMAT_BC6 = 40 -IMG_DATA_FORMAT_BC7 = 41 -IMG_DATA_FORMAT_16_AS_32_32 = 42 -IMG_DATA_FORMAT_16_AS_16_16_16_16 = 43 -IMG_DATA_FORMAT_16_AS_32_32_32_32 = 44 -IMG_DATA_FORMAT_FMASK = 45 -IMG_DATA_FORMAT_ASTC_2D_LDR = 46 -IMG_DATA_FORMAT_ASTC_2D_HDR = 47 -IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 48 -IMG_DATA_FORMAT_ASTC_3D_LDR = 49 -IMG_DATA_FORMAT_ASTC_3D_HDR = 50 -IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 51 -IMG_DATA_FORMAT_N_IN_16 = 52 -IMG_DATA_FORMAT_N_IN_16_16 = 53 -IMG_DATA_FORMAT_N_IN_16_16_16_16 = 54 -IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 55 -IMG_DATA_FORMAT_RESERVED_56 = 56 -IMG_DATA_FORMAT_4_4 = 57 -IMG_DATA_FORMAT_6_5_5 = 58 -IMG_DATA_FORMAT_RESERVED_59 = 59 -IMG_DATA_FORMAT_RESERVED_60 = 60 -IMG_DATA_FORMAT_8_AS_32 = 61 -IMG_DATA_FORMAT_8_AS_32_32 = 62 -IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 -IMG_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'BUF_NUM_FORMAT' -BUF_NUM_FORMAT__enumvalues = { - 0: 'BUF_NUM_FORMAT_UNORM', - 1: 'BUF_NUM_FORMAT_SNORM', - 2: 'BUF_NUM_FORMAT_USCALED', - 3: 'BUF_NUM_FORMAT_SSCALED', - 4: 'BUF_NUM_FORMAT_UINT', - 5: 'BUF_NUM_FORMAT_SINT', - 6: 'BUF_NUM_FORMAT_UNORM_UINT', - 7: 'BUF_NUM_FORMAT_FLOAT', -} -BUF_NUM_FORMAT_UNORM = 0 -BUF_NUM_FORMAT_SNORM = 1 -BUF_NUM_FORMAT_USCALED = 2 -BUF_NUM_FORMAT_SSCALED = 3 -BUF_NUM_FORMAT_UINT = 4 -BUF_NUM_FORMAT_SINT = 5 -BUF_NUM_FORMAT_UNORM_UINT = 6 -BUF_NUM_FORMAT_FLOAT = 7 -BUF_NUM_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT' -IMG_NUM_FORMAT__enumvalues = { - 0: 'IMG_NUM_FORMAT_UNORM', - 1: 'IMG_NUM_FORMAT_SNORM', - 2: 'IMG_NUM_FORMAT_USCALED', - 3: 'IMG_NUM_FORMAT_SSCALED', - 4: 'IMG_NUM_FORMAT_UINT', - 5: 'IMG_NUM_FORMAT_SINT', - 6: 'IMG_NUM_FORMAT_UNORM_UINT', - 7: 'IMG_NUM_FORMAT_FLOAT', - 8: 'IMG_NUM_FORMAT_RESERVED_8', - 9: 'IMG_NUM_FORMAT_SRGB', - 10: 'IMG_NUM_FORMAT_RESERVED_10', - 11: 'IMG_NUM_FORMAT_RESERVED_11', - 12: 'IMG_NUM_FORMAT_RESERVED_12', - 13: 'IMG_NUM_FORMAT_RESERVED_13', - 14: 'IMG_NUM_FORMAT_RESERVED_14', - 15: 'IMG_NUM_FORMAT_RESERVED_15', -} -IMG_NUM_FORMAT_UNORM = 0 -IMG_NUM_FORMAT_SNORM = 1 -IMG_NUM_FORMAT_USCALED = 2 -IMG_NUM_FORMAT_SSCALED = 3 -IMG_NUM_FORMAT_UINT = 4 -IMG_NUM_FORMAT_SINT = 5 -IMG_NUM_FORMAT_UNORM_UINT = 6 -IMG_NUM_FORMAT_FLOAT = 7 -IMG_NUM_FORMAT_RESERVED_8 = 8 -IMG_NUM_FORMAT_SRGB = 9 -IMG_NUM_FORMAT_RESERVED_10 = 10 -IMG_NUM_FORMAT_RESERVED_11 = 11 -IMG_NUM_FORMAT_RESERVED_12 = 12 -IMG_NUM_FORMAT_RESERVED_13 = 13 -IMG_NUM_FORMAT_RESERVED_14 = 14 -IMG_NUM_FORMAT_RESERVED_15 = 15 -IMG_NUM_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_FMASK' -IMG_NUM_FORMAT_FMASK__enumvalues = { - 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', - 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', - 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', - 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', - 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', - 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', - 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', - 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', - 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', - 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', - 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', - 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', - 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', - 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', - 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', - 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', -} -IMG_NUM_FORMAT_FMASK_8_2_1 = 0 -IMG_NUM_FORMAT_FMASK_8_4_1 = 1 -IMG_NUM_FORMAT_FMASK_8_8_1 = 2 -IMG_NUM_FORMAT_FMASK_8_2_2 = 3 -IMG_NUM_FORMAT_FMASK_8_4_2 = 4 -IMG_NUM_FORMAT_FMASK_8_4_4 = 5 -IMG_NUM_FORMAT_FMASK_16_16_1 = 6 -IMG_NUM_FORMAT_FMASK_16_8_2 = 7 -IMG_NUM_FORMAT_FMASK_32_16_2 = 8 -IMG_NUM_FORMAT_FMASK_32_8_4 = 9 -IMG_NUM_FORMAT_FMASK_32_8_8 = 10 -IMG_NUM_FORMAT_FMASK_64_16_4 = 11 -IMG_NUM_FORMAT_FMASK_64_16_8 = 12 -IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 -IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 -IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 -IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_N_IN_16' -IMG_NUM_FORMAT_N_IN_16__enumvalues = { - 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', - 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', - 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', - 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', - 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', - 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', - 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', - 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', - 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', - 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', - 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', - 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', - 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', - 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', - 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', - 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', -} -IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 -IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 -IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 -IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 -IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 -IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 -IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 -IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 -IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 -IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 -IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 -IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 -IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 -IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 -IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 -IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 -IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_ASTC_2D' -IMG_NUM_FORMAT_ASTC_2D__enumvalues = { - 0: 'IMG_NUM_FORMAT_ASTC_2D_4x4', - 1: 'IMG_NUM_FORMAT_ASTC_2D_5x4', - 2: 'IMG_NUM_FORMAT_ASTC_2D_5x5', - 3: 'IMG_NUM_FORMAT_ASTC_2D_6x5', - 4: 'IMG_NUM_FORMAT_ASTC_2D_6x6', - 5: 'IMG_NUM_FORMAT_ASTC_2D_8x5', - 6: 'IMG_NUM_FORMAT_ASTC_2D_8x6', - 7: 'IMG_NUM_FORMAT_ASTC_2D_8x8', - 8: 'IMG_NUM_FORMAT_ASTC_2D_10x5', - 9: 'IMG_NUM_FORMAT_ASTC_2D_10x6', - 10: 'IMG_NUM_FORMAT_ASTC_2D_10x8', - 11: 'IMG_NUM_FORMAT_ASTC_2D_10x10', - 12: 'IMG_NUM_FORMAT_ASTC_2D_12x10', - 13: 'IMG_NUM_FORMAT_ASTC_2D_12x12', - 14: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', - 15: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', -} -IMG_NUM_FORMAT_ASTC_2D_4x4 = 0 -IMG_NUM_FORMAT_ASTC_2D_5x4 = 1 -IMG_NUM_FORMAT_ASTC_2D_5x5 = 2 -IMG_NUM_FORMAT_ASTC_2D_6x5 = 3 -IMG_NUM_FORMAT_ASTC_2D_6x6 = 4 -IMG_NUM_FORMAT_ASTC_2D_8x5 = 5 -IMG_NUM_FORMAT_ASTC_2D_8x6 = 6 -IMG_NUM_FORMAT_ASTC_2D_8x8 = 7 -IMG_NUM_FORMAT_ASTC_2D_10x5 = 8 -IMG_NUM_FORMAT_ASTC_2D_10x6 = 9 -IMG_NUM_FORMAT_ASTC_2D_10x8 = 10 -IMG_NUM_FORMAT_ASTC_2D_10x10 = 11 -IMG_NUM_FORMAT_ASTC_2D_12x10 = 12 -IMG_NUM_FORMAT_ASTC_2D_12x12 = 13 -IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 14 -IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 15 -IMG_NUM_FORMAT_ASTC_2D = ctypes.c_uint32 # enum - -# values for enumeration 'IMG_NUM_FORMAT_ASTC_3D' -IMG_NUM_FORMAT_ASTC_3D__enumvalues = { - 0: 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', - 1: 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', - 2: 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', - 3: 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', - 4: 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', - 5: 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', - 6: 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', - 7: 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', - 8: 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', - 9: 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', - 10: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', - 11: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', - 12: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', - 13: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', - 14: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', - 15: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', -} -IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0 -IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 1 -IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 2 -IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 3 -IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 4 -IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 5 -IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 6 -IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 7 -IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 8 -IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 9 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 10 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 11 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 12 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 13 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 14 -IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 15 -IMG_NUM_FORMAT_ASTC_3D = ctypes.c_uint32 # enum - -# values for enumeration 'TileType' -TileType__enumvalues = { - 0: 'ARRAY_COLOR_TILE', - 1: 'ARRAY_DEPTH_TILE', -} -ARRAY_COLOR_TILE = 0 -ARRAY_DEPTH_TILE = 1 -TileType = ctypes.c_uint32 # enum - -# values for enumeration 'NonDispTilingOrder' -NonDispTilingOrder__enumvalues = { - 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', - 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', -} -ADDR_SURF_MICRO_TILING_DISPLAY = 0 -ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 -NonDispTilingOrder = ctypes.c_uint32 # enum - -# values for enumeration 'MicroTileMode' -MicroTileMode__enumvalues = { - 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', - 1: 'ADDR_SURF_THIN_MICRO_TILING', - 2: 'ADDR_SURF_DEPTH_MICRO_TILING', - 3: 'ADDR_SURF_ROTATED_MICRO_TILING', - 4: 'ADDR_SURF_THICK_MICRO_TILING', -} -ADDR_SURF_DISPLAY_MICRO_TILING = 0 -ADDR_SURF_THIN_MICRO_TILING = 1 -ADDR_SURF_DEPTH_MICRO_TILING = 2 -ADDR_SURF_ROTATED_MICRO_TILING = 3 -ADDR_SURF_THICK_MICRO_TILING = 4 -MicroTileMode = ctypes.c_uint32 # enum - -# values for enumeration 'TileSplit' -TileSplit__enumvalues = { - 0: 'ADDR_SURF_TILE_SPLIT_64B', - 1: 'ADDR_SURF_TILE_SPLIT_128B', - 2: 'ADDR_SURF_TILE_SPLIT_256B', - 3: 'ADDR_SURF_TILE_SPLIT_512B', - 4: 'ADDR_SURF_TILE_SPLIT_1KB', - 5: 'ADDR_SURF_TILE_SPLIT_2KB', - 6: 'ADDR_SURF_TILE_SPLIT_4KB', -} -ADDR_SURF_TILE_SPLIT_64B = 0 -ADDR_SURF_TILE_SPLIT_128B = 1 -ADDR_SURF_TILE_SPLIT_256B = 2 -ADDR_SURF_TILE_SPLIT_512B = 3 -ADDR_SURF_TILE_SPLIT_1KB = 4 -ADDR_SURF_TILE_SPLIT_2KB = 5 -ADDR_SURF_TILE_SPLIT_4KB = 6 -TileSplit = ctypes.c_uint32 # enum - -# values for enumeration 'SampleSplit' -SampleSplit__enumvalues = { - 0: 'ADDR_SURF_SAMPLE_SPLIT_1', - 1: 'ADDR_SURF_SAMPLE_SPLIT_2', - 2: 'ADDR_SURF_SAMPLE_SPLIT_4', - 3: 'ADDR_SURF_SAMPLE_SPLIT_8', -} -ADDR_SURF_SAMPLE_SPLIT_1 = 0 -ADDR_SURF_SAMPLE_SPLIT_2 = 1 -ADDR_SURF_SAMPLE_SPLIT_4 = 2 -ADDR_SURF_SAMPLE_SPLIT_8 = 3 -SampleSplit = ctypes.c_uint32 # enum - -# values for enumeration 'PipeConfig' -PipeConfig__enumvalues = { - 0: 'ADDR_SURF_P2', - 1: 'ADDR_SURF_P2_RESERVED0', - 2: 'ADDR_SURF_P2_RESERVED1', - 3: 'ADDR_SURF_P2_RESERVED2', - 4: 'ADDR_SURF_P4_8x16', - 5: 'ADDR_SURF_P4_16x16', - 6: 'ADDR_SURF_P4_16x32', - 7: 'ADDR_SURF_P4_32x32', - 8: 'ADDR_SURF_P8_16x16_8x16', - 9: 'ADDR_SURF_P8_16x32_8x16', - 10: 'ADDR_SURF_P8_32x32_8x16', - 11: 'ADDR_SURF_P8_16x32_16x16', - 12: 'ADDR_SURF_P8_32x32_16x16', - 13: 'ADDR_SURF_P8_32x32_16x32', - 14: 'ADDR_SURF_P8_32x64_32x32', - 15: 'ADDR_SURF_P8_RESERVED0', - 16: 'ADDR_SURF_P16_32x32_8x16', - 17: 'ADDR_SURF_P16_32x32_16x16', -} -ADDR_SURF_P2 = 0 -ADDR_SURF_P2_RESERVED0 = 1 -ADDR_SURF_P2_RESERVED1 = 2 -ADDR_SURF_P2_RESERVED2 = 3 -ADDR_SURF_P4_8x16 = 4 -ADDR_SURF_P4_16x16 = 5 -ADDR_SURF_P4_16x32 = 6 -ADDR_SURF_P4_32x32 = 7 -ADDR_SURF_P8_16x16_8x16 = 8 -ADDR_SURF_P8_16x32_8x16 = 9 -ADDR_SURF_P8_32x32_8x16 = 10 -ADDR_SURF_P8_16x32_16x16 = 11 -ADDR_SURF_P8_32x32_16x16 = 12 -ADDR_SURF_P8_32x32_16x32 = 13 -ADDR_SURF_P8_32x64_32x32 = 14 -ADDR_SURF_P8_RESERVED0 = 15 -ADDR_SURF_P16_32x32_8x16 = 16 -ADDR_SURF_P16_32x32_16x16 = 17 -PipeConfig = ctypes.c_uint32 # enum - -# values for enumeration 'SeEnable' -SeEnable__enumvalues = { - 0: 'ADDR_CONFIG_DISABLE_SE', - 1: 'ADDR_CONFIG_ENABLE_SE', -} -ADDR_CONFIG_DISABLE_SE = 0 -ADDR_CONFIG_ENABLE_SE = 1 -SeEnable = ctypes.c_uint32 # enum - -# values for enumeration 'NumBanks' -NumBanks__enumvalues = { - 0: 'ADDR_SURF_2_BANK', - 1: 'ADDR_SURF_4_BANK', - 2: 'ADDR_SURF_8_BANK', - 3: 'ADDR_SURF_16_BANK', -} -ADDR_SURF_2_BANK = 0 -ADDR_SURF_4_BANK = 1 -ADDR_SURF_8_BANK = 2 -ADDR_SURF_16_BANK = 3 -NumBanks = ctypes.c_uint32 # enum - -# values for enumeration 'BankWidth' -BankWidth__enumvalues = { - 0: 'ADDR_SURF_BANK_WIDTH_1', - 1: 'ADDR_SURF_BANK_WIDTH_2', - 2: 'ADDR_SURF_BANK_WIDTH_4', - 3: 'ADDR_SURF_BANK_WIDTH_8', -} -ADDR_SURF_BANK_WIDTH_1 = 0 -ADDR_SURF_BANK_WIDTH_2 = 1 -ADDR_SURF_BANK_WIDTH_4 = 2 -ADDR_SURF_BANK_WIDTH_8 = 3 -BankWidth = ctypes.c_uint32 # enum - -# values for enumeration 'BankHeight' -BankHeight__enumvalues = { - 0: 'ADDR_SURF_BANK_HEIGHT_1', - 1: 'ADDR_SURF_BANK_HEIGHT_2', - 2: 'ADDR_SURF_BANK_HEIGHT_4', - 3: 'ADDR_SURF_BANK_HEIGHT_8', -} -ADDR_SURF_BANK_HEIGHT_1 = 0 -ADDR_SURF_BANK_HEIGHT_2 = 1 -ADDR_SURF_BANK_HEIGHT_4 = 2 -ADDR_SURF_BANK_HEIGHT_8 = 3 -BankHeight = ctypes.c_uint32 # enum - -# values for enumeration 'BankWidthHeight' -BankWidthHeight__enumvalues = { - 0: 'ADDR_SURF_BANK_WH_1', - 1: 'ADDR_SURF_BANK_WH_2', - 2: 'ADDR_SURF_BANK_WH_4', - 3: 'ADDR_SURF_BANK_WH_8', -} -ADDR_SURF_BANK_WH_1 = 0 -ADDR_SURF_BANK_WH_2 = 1 -ADDR_SURF_BANK_WH_4 = 2 -ADDR_SURF_BANK_WH_8 = 3 -BankWidthHeight = ctypes.c_uint32 # enum - -# values for enumeration 'MacroTileAspect' -MacroTileAspect__enumvalues = { - 0: 'ADDR_SURF_MACRO_ASPECT_1', - 1: 'ADDR_SURF_MACRO_ASPECT_2', - 2: 'ADDR_SURF_MACRO_ASPECT_4', - 3: 'ADDR_SURF_MACRO_ASPECT_8', -} -ADDR_SURF_MACRO_ASPECT_1 = 0 -ADDR_SURF_MACRO_ASPECT_2 = 1 -ADDR_SURF_MACRO_ASPECT_4 = 2 -ADDR_SURF_MACRO_ASPECT_8 = 3 -MacroTileAspect = ctypes.c_uint32 # enum - -# values for enumeration 'GATCL1RequestType' -GATCL1RequestType__enumvalues = { - 0: 'GATCL1_TYPE_NORMAL', - 1: 'GATCL1_TYPE_SHOOTDOWN', - 2: 'GATCL1_TYPE_BYPASS', -} -GATCL1_TYPE_NORMAL = 0 -GATCL1_TYPE_SHOOTDOWN = 1 -GATCL1_TYPE_BYPASS = 2 -GATCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1RequestType' -UTCL1RequestType__enumvalues = { - 0: 'UTCL1_TYPE_NORMAL', - 1: 'UTCL1_TYPE_SHOOTDOWN', - 2: 'UTCL1_TYPE_BYPASS', -} -UTCL1_TYPE_NORMAL = 0 -UTCL1_TYPE_SHOOTDOWN = 1 -UTCL1_TYPE_BYPASS = 2 -UTCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1FaultType' -UTCL1FaultType__enumvalues = { - 0: 'UTCL1_XNACK_SUCCESS', - 1: 'UTCL1_XNACK_RETRY', - 2: 'UTCL1_XNACK_PRT', - 3: 'UTCL1_XNACK_NO_RETRY', -} -UTCL1_XNACK_SUCCESS = 0 -UTCL1_XNACK_RETRY = 1 -UTCL1_XNACK_PRT = 2 -UTCL1_XNACK_NO_RETRY = 3 -UTCL1FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_CACHE_POLICIES' -TCC_CACHE_POLICIES__enumvalues = { - 0: 'TCC_CACHE_POLICY_LRU', - 1: 'TCC_CACHE_POLICY_STREAM', -} -TCC_CACHE_POLICY_LRU = 0 -TCC_CACHE_POLICY_STREAM = 1 -TCC_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'MTYPE' -MTYPE__enumvalues = { - 0: 'MTYPE_NC', - 1: 'MTYPE_WC', - 1: 'MTYPE_RW', - 2: 'MTYPE_CC', - 3: 'MTYPE_UC', -} -MTYPE_NC = 0 -MTYPE_WC = 1 -MTYPE_RW = 1 -MTYPE_CC = 2 -MTYPE_UC = 3 -MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'RMI_CID' -RMI_CID__enumvalues = { - 0: 'RMI_CID_CC', - 1: 'RMI_CID_FC', - 2: 'RMI_CID_CM', - 3: 'RMI_CID_DC', - 4: 'RMI_CID_Z', - 5: 'RMI_CID_S', - 6: 'RMI_CID_TILE', - 7: 'RMI_CID_ZPCPSD', -} -RMI_CID_CC = 0 -RMI_CID_FC = 1 -RMI_CID_CM = 2 -RMI_CID_DC = 3 -RMI_CID_Z = 4 -RMI_CID_S = 5 -RMI_CID_TILE = 6 -RMI_CID_ZPCPSD = 7 -RMI_CID = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_COUNTER_MODE' -PERFMON_COUNTER_MODE__enumvalues = { - 0: 'PERFMON_COUNTER_MODE_ACCUM', - 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 2: 'PERFMON_COUNTER_MODE_MAX', - 3: 'PERFMON_COUNTER_MODE_DIRTY', - 4: 'PERFMON_COUNTER_MODE_SAMPLE', - 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 15: 'PERFMON_COUNTER_MODE_RESERVED', -} -PERFMON_COUNTER_MODE_ACCUM = 0 -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 -PERFMON_COUNTER_MODE_MAX = 2 -PERFMON_COUNTER_MODE_DIRTY = 3 -PERFMON_COUNTER_MODE_SAMPLE = 4 -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 -PERFMON_COUNTER_MODE_RESERVED = 15 -PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_SPM_MODE' -PERFMON_SPM_MODE__enumvalues = { - 0: 'PERFMON_SPM_MODE_OFF', - 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', - 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', - 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 5: 'PERFMON_SPM_MODE_RESERVED_5', - 6: 'PERFMON_SPM_MODE_RESERVED_6', - 7: 'PERFMON_SPM_MODE_RESERVED_7', - 8: 'PERFMON_SPM_MODE_TEST_MODE_0', - 9: 'PERFMON_SPM_MODE_TEST_MODE_1', - 10: 'PERFMON_SPM_MODE_TEST_MODE_2', -} -PERFMON_SPM_MODE_OFF = 0 -PERFMON_SPM_MODE_16BIT_CLAMP = 1 -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 -PERFMON_SPM_MODE_32BIT_CLAMP = 3 -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 -PERFMON_SPM_MODE_RESERVED_5 = 5 -PERFMON_SPM_MODE_RESERVED_6 = 6 -PERFMON_SPM_MODE_RESERVED_7 = 7 -PERFMON_SPM_MODE_TEST_MODE_0 = 8 -PERFMON_SPM_MODE_TEST_MODE_1 = 9 -PERFMON_SPM_MODE_TEST_MODE_2 = 10 -PERFMON_SPM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceTiling' -SurfaceTiling__enumvalues = { - 0: 'ARRAY_LINEAR', - 1: 'ARRAY_TILED', -} -ARRAY_LINEAR = 0 -ARRAY_TILED = 1 -SurfaceTiling = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceArray' -SurfaceArray__enumvalues = { - 0: 'ARRAY_1D', - 1: 'ARRAY_2D', - 2: 'ARRAY_3D', - 3: 'ARRAY_3D_SLICE', -} -ARRAY_1D = 0 -ARRAY_2D = 1 -ARRAY_3D = 2 -ARRAY_3D_SLICE = 3 -SurfaceArray = ctypes.c_uint32 # enum - -# values for enumeration 'ColorArray' -ColorArray__enumvalues = { - 0: 'ARRAY_2D_ALT_COLOR', - 1: 'ARRAY_2D_COLOR', - 3: 'ARRAY_3D_SLICE_COLOR', -} -ARRAY_2D_ALT_COLOR = 0 -ARRAY_2D_COLOR = 1 -ARRAY_3D_SLICE_COLOR = 3 -ColorArray = ctypes.c_uint32 # enum - -# values for enumeration 'DepthArray' -DepthArray__enumvalues = { - 0: 'ARRAY_2D_ALT_DEPTH', - 1: 'ARRAY_2D_DEPTH', -} -ARRAY_2D_ALT_DEPTH = 0 -ARRAY_2D_DEPTH = 1 -DepthArray = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_NUM_SIMD_PER_CU' -ENUM_NUM_SIMD_PER_CU__enumvalues = { - 4: 'NUM_SIMD_PER_CU', -} -NUM_SIMD_PER_CU = 4 -ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_ENABLE_ERROR_INJECT' -DSM_ENABLE_ERROR_INJECT__enumvalues = { - 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 2: 'DSM_ENABLE_ERROR_INJECT_DOUBLE', - 3: 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', -} -DSM_ENABLE_ERROR_INJECT_FED_IN = 0 -DSM_ENABLE_ERROR_INJECT_SINGLE = 1 -DSM_ENABLE_ERROR_INJECT_DOUBLE = 2 -DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 3 -DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SELECT_INJECT_DELAY' -DSM_SELECT_INJECT_DELAY__enumvalues = { - 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', - 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', -} -DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 -DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 -DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'SWIZZLE_TYPE_ENUM' -SWIZZLE_TYPE_ENUM__enumvalues = { - 0: 'SW_Z', - 1: 'SW_S', - 2: 'SW_D', - 3: 'SW_R', - 4: 'SW_L', -} -SW_Z = 0 -SW_S = 1 -SW_D = 2 -SW_R = 3 -SW_L = 4 -SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TC_MICRO_TILE_MODE' -TC_MICRO_TILE_MODE__enumvalues = { - 0: 'MICRO_TILE_MODE_LINEAR', - 1: 'MICRO_TILE_MODE_ROTATED', - 2: 'MICRO_TILE_MODE_STD_2D', - 3: 'MICRO_TILE_MODE_STD_3D', - 4: 'MICRO_TILE_MODE_DISPLAY_2D', - 5: 'MICRO_TILE_MODE_DISPLAY_3D', - 6: 'MICRO_TILE_MODE_Z_2D', - 7: 'MICRO_TILE_MODE_Z_3D', -} -MICRO_TILE_MODE_LINEAR = 0 -MICRO_TILE_MODE_ROTATED = 1 -MICRO_TILE_MODE_STD_2D = 2 -MICRO_TILE_MODE_STD_3D = 3 -MICRO_TILE_MODE_DISPLAY_2D = 4 -MICRO_TILE_MODE_DISPLAY_3D = 5 -MICRO_TILE_MODE_Z_2D = 6 -MICRO_TILE_MODE_Z_3D = 7 -TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SWIZZLE_MODE_ENUM' -SWIZZLE_MODE_ENUM__enumvalues = { - 0: 'SW_LINEAR', - 1: 'SW_256B_S', - 2: 'SW_256B_D', - 3: 'SW_256B_R', - 4: 'SW_4KB_Z', - 5: 'SW_4KB_S', - 6: 'SW_4KB_D', - 7: 'SW_4KB_R', - 8: 'SW_64KB_Z', - 9: 'SW_64KB_S', - 10: 'SW_64KB_D', - 11: 'SW_64KB_R', - 12: 'SW_VAR_Z', - 13: 'SW_VAR_S', - 14: 'SW_VAR_D', - 15: 'SW_VAR_R', - 16: 'SW_RESERVED_16', - 17: 'SW_RESERVED_17', - 18: 'SW_RESERVED_18', - 19: 'SW_RESERVED_19', - 20: 'SW_4KB_Z_X', - 21: 'SW_4KB_S_X', - 22: 'SW_4KB_D_X', - 23: 'SW_4KB_R_X', - 24: 'SW_64KB_Z_X', - 25: 'SW_64KB_S_X', - 26: 'SW_64KB_D_X', - 27: 'SW_64KB_R_X', - 28: 'SW_VAR_Z_X', - 29: 'SW_VAR_S_X', - 30: 'SW_VAR_D_X', - 31: 'SW_VAR_R_X', - 32: 'SW_RESERVED_12', - 33: 'SW_RESERVED_13', - 34: 'SW_RESERVED_14', - 35: 'SW_RESERVED_15', -} -SW_LINEAR = 0 -SW_256B_S = 1 -SW_256B_D = 2 -SW_256B_R = 3 -SW_4KB_Z = 4 -SW_4KB_S = 5 -SW_4KB_D = 6 -SW_4KB_R = 7 -SW_64KB_Z = 8 -SW_64KB_S = 9 -SW_64KB_D = 10 -SW_64KB_R = 11 -SW_VAR_Z = 12 -SW_VAR_S = 13 -SW_VAR_D = 14 -SW_VAR_R = 15 -SW_RESERVED_16 = 16 -SW_RESERVED_17 = 17 -SW_RESERVED_18 = 18 -SW_RESERVED_19 = 19 -SW_4KB_Z_X = 20 -SW_4KB_S_X = 21 -SW_4KB_D_X = 22 -SW_4KB_R_X = 23 -SW_64KB_Z_X = 24 -SW_64KB_S_X = 25 -SW_64KB_D_X = 26 -SW_64KB_R_X = 27 -SW_VAR_Z_X = 28 -SW_VAR_S_X = 29 -SW_VAR_D_X = 30 -SW_VAR_R_X = 31 -SW_RESERVED_12 = 32 -SW_RESERVED_13 = 33 -SW_RESERVED_14 = 34 -SW_RESERVED_15 = 35 -SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'PipeTiling' -PipeTiling__enumvalues = { - 0: 'CONFIG_1_PIPE', - 1: 'CONFIG_2_PIPE', - 2: 'CONFIG_4_PIPE', - 3: 'CONFIG_8_PIPE', -} -CONFIG_1_PIPE = 0 -CONFIG_2_PIPE = 1 -CONFIG_4_PIPE = 2 -CONFIG_8_PIPE = 3 -PipeTiling = ctypes.c_uint32 # enum - -# values for enumeration 'BankTiling' -BankTiling__enumvalues = { - 0: 'CONFIG_4_BANK', - 1: 'CONFIG_8_BANK', -} -CONFIG_4_BANK = 0 -CONFIG_8_BANK = 1 -BankTiling = ctypes.c_uint32 # enum - -# values for enumeration 'GroupInterleave' -GroupInterleave__enumvalues = { - 0: 'CONFIG_256B_GROUP', - 1: 'CONFIG_512B_GROUP', -} -CONFIG_256B_GROUP = 0 -CONFIG_512B_GROUP = 1 -GroupInterleave = ctypes.c_uint32 # enum - -# values for enumeration 'RowTiling' -RowTiling__enumvalues = { - 0: 'CONFIG_1KB_ROW', - 1: 'CONFIG_2KB_ROW', - 2: 'CONFIG_4KB_ROW', - 3: 'CONFIG_8KB_ROW', - 4: 'CONFIG_1KB_ROW_OPT', - 5: 'CONFIG_2KB_ROW_OPT', - 6: 'CONFIG_4KB_ROW_OPT', - 7: 'CONFIG_8KB_ROW_OPT', -} -CONFIG_1KB_ROW = 0 -CONFIG_2KB_ROW = 1 -CONFIG_4KB_ROW = 2 -CONFIG_8KB_ROW = 3 -CONFIG_1KB_ROW_OPT = 4 -CONFIG_2KB_ROW_OPT = 5 -CONFIG_4KB_ROW_OPT = 6 -CONFIG_8KB_ROW_OPT = 7 -RowTiling = ctypes.c_uint32 # enum - -# values for enumeration 'BankSwapBytes' -BankSwapBytes__enumvalues = { - 0: 'CONFIG_128B_SWAPS', - 1: 'CONFIG_256B_SWAPS', - 2: 'CONFIG_512B_SWAPS', - 3: 'CONFIG_1KB_SWAPS', -} -CONFIG_128B_SWAPS = 0 -CONFIG_256B_SWAPS = 1 -CONFIG_512B_SWAPS = 2 -CONFIG_1KB_SWAPS = 3 -BankSwapBytes = ctypes.c_uint32 # enum - -# values for enumeration 'SampleSplitBytes' -SampleSplitBytes__enumvalues = { - 0: 'CONFIG_1KB_SPLIT', - 1: 'CONFIG_2KB_SPLIT', - 2: 'CONFIG_4KB_SPLIT', - 3: 'CONFIG_8KB_SPLIT', -} -CONFIG_1KB_SPLIT = 0 -CONFIG_2KB_SPLIT = 1 -CONFIG_4KB_SPLIT = 2 -CONFIG_8KB_SPLIT = 3 -SampleSplitBytes = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_MODE' -BLNDV_CONTROL_BLND_MODE__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', - 1: 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', - 2: 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', - 3: 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', -} -BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 -BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 -BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 -BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 -BLNDV_CONTROL_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_TYPE' -BLNDV_CONTROL_BLND_STEREO_TYPE__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', - 1: 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', - 2: 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', - 3: 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', -} -BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 -BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 -BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 -BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 -BLNDV_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_POLARITY' -BLNDV_CONTROL_BLND_STEREO_POLARITY__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', - 1: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', -} -BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0 -BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 -BLNDV_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN' -BLNDV_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', - 1: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', -} -BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 -BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 -BLNDV_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_ALPHA_MODE' -BLNDV_CONTROL_BLND_ALPHA_MODE__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', - 1: 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', - 3: 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', -} -BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 -BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 -BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 -BLNDV_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' -BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', - 1: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', -} -BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0 -BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 1 -BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE' -BLNDV_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { - 0: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', - 1: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', -} -BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 -BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 -BLNDV_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_SM_CONTROL2_SM_MODE' -BLNDV_SM_CONTROL2_SM_MODE__enumvalues = { - 0: 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', - 2: 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', - 4: 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 -BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 -BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 -BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -BLNDV_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE' -BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { - 0: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', - 1: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', -} -BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 -BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 -BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE' -BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { - 0: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', - 1: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', -} -BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 -BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 -BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL2_PTI_ENABLE' -BLNDV_CONTROL2_PTI_ENABLE__enumvalues = { - 0: 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', - 1: 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', -} -BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0 -BLNDV_CONTROL2_PTI_ENABLE_TRUE = 1 -BLNDV_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' -BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { - 0: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', - 1: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', -} -BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 -BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 -BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN' -BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { - 0: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', - 1: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', -} -BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 -BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 -BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { - 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', - 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', -} -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { - 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', - 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', -} -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 -BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' -BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' -BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { - 0: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', - 1: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', -} -BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 -BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 -BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT' -BLNDV_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { - 0: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', - 1: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', -} -BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 -BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 -BLNDV_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' -BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', -} -BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 -BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 -BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_PIXEL_DEPTH' -LBV_PIXEL_DEPTH__enumvalues = { - 0: 'PIXEL_DEPTH_30BPP', - 1: 'PIXEL_DEPTH_24BPP', - 2: 'PIXEL_DEPTH_18BPP', - 3: 'PIXEL_DEPTH_38BPP', -} -PIXEL_DEPTH_30BPP = 0 -PIXEL_DEPTH_24BPP = 1 -PIXEL_DEPTH_18BPP = 2 -PIXEL_DEPTH_38BPP = 3 -LBV_PIXEL_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_PIXEL_EXPAN_MODE' -LBV_PIXEL_EXPAN_MODE__enumvalues = { - 0: 'PIXEL_EXPAN_MODE_ZERO_EXP', - 1: 'PIXEL_EXPAN_MODE_DYN_EXP', -} -PIXEL_EXPAN_MODE_ZERO_EXP = 0 -PIXEL_EXPAN_MODE_DYN_EXP = 1 -LBV_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_INTERLEAVE_EN' -LBV_INTERLEAVE_EN__enumvalues = { - 0: 'INTERLEAVE_DIS', - 1: 'INTERLEAVE_EN', -} -INTERLEAVE_DIS = 0 -INTERLEAVE_EN = 1 -LBV_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_PIXEL_REDUCE_MODE' -LBV_PIXEL_REDUCE_MODE__enumvalues = { - 0: 'PIXEL_REDUCE_MODE_TRUNCATION', - 1: 'PIXEL_REDUCE_MODE_ROUNDING', -} -PIXEL_REDUCE_MODE_TRUNCATION = 0 -PIXEL_REDUCE_MODE_ROUNDING = 1 -LBV_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_DYNAMIC_PIXEL_DEPTH' -LBV_DYNAMIC_PIXEL_DEPTH__enumvalues = { - 0: 'DYNAMIC_PIXEL_DEPTH_36BPP', - 1: 'DYNAMIC_PIXEL_DEPTH_30BPP', -} -DYNAMIC_PIXEL_DEPTH_36BPP = 0 -DYNAMIC_PIXEL_DEPTH_30BPP = 1 -LBV_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_DITHER_EN' -LBV_DITHER_EN__enumvalues = { - 0: 'DITHER_DIS', - 1: 'DITHER_EN', -} -DITHER_DIS = 0 -DITHER_EN = 1 -LBV_DITHER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_DOWNSCALE_PREFETCH_EN' -LBV_DOWNSCALE_PREFETCH_EN__enumvalues = { - 0: 'DOWNSCALE_PREFETCH_DIS', - 1: 'DOWNSCALE_PREFETCH_EN', -} -DOWNSCALE_PREFETCH_DIS = 0 -DOWNSCALE_PREFETCH_EN = 1 -LBV_DOWNSCALE_PREFETCH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_MEMORY_CONFIG' -LBV_MEMORY_CONFIG__enumvalues = { - 0: 'MEMORY_CONFIG_0', - 1: 'MEMORY_CONFIG_1', - 2: 'MEMORY_CONFIG_2', - 3: 'MEMORY_CONFIG_3', -} -MEMORY_CONFIG_0 = 0 -MEMORY_CONFIG_1 = 1 -MEMORY_CONFIG_2 = 2 -MEMORY_CONFIG_3 = 3 -LBV_MEMORY_CONFIG = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_SYNC_RESET_SEL2' -LBV_SYNC_RESET_SEL2__enumvalues = { - 0: 'SYNC_RESET_SEL2_VBLANK', - 1: 'SYNC_RESET_SEL2_VSYNC', -} -SYNC_RESET_SEL2_VBLANK = 0 -SYNC_RESET_SEL2_VSYNC = 1 -LBV_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'LBV_SYNC_DURATION' -LBV_SYNC_DURATION__enumvalues = { - 0: 'SYNC_DURATION_16', - 1: 'SYNC_DURATION_32', - 2: 'SYNC_DURATION_64', - 3: 'SYNC_DURATION_128', -} -SYNC_DURATION_16 = 0 -SYNC_DURATION_32 = 1 -SYNC_DURATION_64 = 2 -SYNC_DURATION_128 = 3 -LBV_SYNC_DURATION = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_START_POINT_CNTL' -CRTC_CONTROL_CRTC_START_POINT_CNTL__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', - 1: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', -} -CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0 -CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 1 -CRTC_CONTROL_CRTC_START_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL' -CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', - 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', -} -CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0 -CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 1 -CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL' -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', - 1: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 2: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', - 3: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', -} -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0 -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 2 -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 -CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY' -CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', - 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', -} -CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0 -CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 1 -CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE' -CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', - 1: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', -} -CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0 -CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 1 -CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_SOF_PULL_EN' -CRTC_CONTROL_CRTC_SOF_PULL_EN__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', - 1: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', -} -CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0 -CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 1 -CRTC_CONTROL_CRTC_SOF_PULL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL' -CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL__enumvalues = { - 0: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', - 1: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', -} -CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0 -CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 1 -CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL' -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL__enumvalues = { - 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', - 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', -} -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0 -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 1 -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL' -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL__enumvalues = { - 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', - 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', -} -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0 -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 1 -CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN' -CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { - 0: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', - 1: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', -} -CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 -CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 -CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC' -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { - 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', -} -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT' -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT__enumvalues = { - 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', - 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', -} -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0 -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 1 -CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' -CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { - 0: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', - 1: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', -} -CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 -CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 -CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR' -CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR__enumvalues = { - 0: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', - 1: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', -} -CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0 -CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 1 -CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL' -CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL__enumvalues = { - 0: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', - 1: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', -} -CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0 -CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 1 -CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN' -CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN__enumvalues = { - 0: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', - 1: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', -} -CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0 -CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 1 -CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT' -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT__enumvalues = { - 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', - 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', - 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', - 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', - 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', - 8: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', - 9: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', - 10: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', - 11: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', - 12: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', - 13: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', - 14: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', - 16: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', - 17: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', - 18: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', - 19: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', - 20: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', - 21: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', - 22: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', - 23: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', -} -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 1 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 2 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 5 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 6 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 7 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 8 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 9 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 10 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 11 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 12 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 13 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 14 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 16 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 17 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 18 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 19 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 20 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 21 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 22 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 23 -CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT' -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT__enumvalues = { - 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', - 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', - 3: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', - 4: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', - 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', - 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', - 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', -} -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 1 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 2 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 3 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 4 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 5 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 6 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 7 -CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN' -CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN__enumvalues = { - 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', - 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', -} -CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 -CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 -CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR' -CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR__enumvalues = { - 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', - 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', -} -CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0 -CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 1 -CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT' -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT__enumvalues = { - 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', - 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', - 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', - 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', - 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', - 8: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', - 9: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', - 10: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', - 11: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', - 12: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', - 13: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', - 14: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', - 16: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', - 17: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', - 18: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', - 19: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', - 20: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', - 21: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', - 22: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', - 23: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', -} -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 1 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 2 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 5 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 6 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 7 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 8 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 9 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 10 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 11 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 12 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 13 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 14 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 16 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 17 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 18 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 19 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 20 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 21 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 22 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 23 -CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT' -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT__enumvalues = { - 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', - 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', - 3: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', - 4: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', - 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', - 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', - 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', -} -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 1 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 2 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 3 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 4 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 5 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 6 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 7 -CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN' -CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN__enumvalues = { - 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', - 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', -} -CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 -CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 -CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR' -CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR__enumvalues = { - 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', - 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', -} -CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0 -CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 1 -CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE' -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE__enumvalues = { - 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', - 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', - 2: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 3: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', -} -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 1 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 3 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK' -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK__enumvalues = { - 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', - 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', -} -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 1 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL' -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { - 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', -} -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR' -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR__enumvalues = { - 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', - 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', -} -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 1 -CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT' -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { - 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 2: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 3: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 4: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 5: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 6: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 7: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 8: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 9: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', - 10: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', - 11: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 12: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 13: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 14: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 15: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', -} -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 1 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 2 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 3 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 4 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 5 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 6 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 7 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 8 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 9 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 10 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 11 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 12 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 13 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 14 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 15 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY' -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY__enumvalues = { - 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', - 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', -} -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 1 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY' -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY__enumvalues = { - 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', - 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', -} -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 1 -CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE' -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE__enumvalues = { - 0: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', - 1: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', - 2: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', - 3: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', -} -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0 -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 1 -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 2 -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 3 -CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CONTROL_CRTC_MASTER_EN' -CRTC_CONTROL_CRTC_MASTER_EN__enumvalues = { - 0: 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', - 1: 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', -} -CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0 -CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 1 -CRTC_CONTROL_CRTC_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN' -CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN__enumvalues = { - 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', - 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', -} -CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0 -CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 1 -CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE' -CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE__enumvalues = { - 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', - 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', -} -CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0 -CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 1 -CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE' -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE__enumvalues = { - 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', - 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', -} -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 1 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD' -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { - 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', - 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', - 2: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', - 3: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', -} -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 1 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 2 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 -CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY' -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { - 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', - 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', -} -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT' -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT__enumvalues = { - 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', - 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', -} -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0 -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 1 -CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN' -CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN__enumvalues = { - 0: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', - 1: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', -} -CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0 -CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 1 -CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE' -CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { - 0: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 1: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', -} -CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 -CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 -CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR' -CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { - 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', -} -CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 -CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 -CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE' -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE__enumvalues = { - 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', - 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 2: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 3: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', -} -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 -CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY' -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { - 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', -} -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY' -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY__enumvalues = { - 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', - 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', -} -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0 -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 1 -CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY' -CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY__enumvalues = { - 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', - 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', -} -CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0 -CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 1 -CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN' -CRTC_STEREO_CONTROL_CRTC_STEREO_EN__enumvalues = { - 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', - 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', -} -CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0 -CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 1 -CRTC_STEREO_CONTROL_CRTC_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR' -CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR__enumvalues = { - 0: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', - 1: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', -} -CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0 -CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 1 -CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL' -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { - 0: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 1: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 2: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 3: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', -} -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 -CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY' -CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY__enumvalues = { - 0: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', - 1: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', -} -CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 -CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 -CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY' -CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY__enumvalues = { - 0: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', - 1: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', -} -CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0 -CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 1 -CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN' -CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN__enumvalues = { - 0: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', - 1: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', -} -CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0 -CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 1 -CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN' -CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN__enumvalues = { - 0: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', - 1: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', -} -CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0 -CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 1 -CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK' -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE' -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { - 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', -} -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 -CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK' -CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK__enumvalues = { - 0: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', - 1: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', -} -CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0 -CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 1 -CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY' -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY__enumvalues = { - 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', - 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', -} -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 1 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN' -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { - 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', - 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', -} -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE' -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { - 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', - 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', -} -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 -CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE' -CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { - 0: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', - 1: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', -} -CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 -CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 -CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN' -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN__enumvalues = { - 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', - 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', -} -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 1 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE' -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE__enumvalues = { - 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', - 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', - 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', - 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', - 4: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', - 5: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', - 6: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', - 7: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', -} -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 1 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 2 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 3 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 4 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 5 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 6 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 7 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE' -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE__enumvalues = { - 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', - 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', -} -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 1 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT' -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT__enumvalues = { - 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', - 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', - 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', - 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', -} -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 1 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 2 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 3 -CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE' -CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE__enumvalues = { - 0: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', - 1: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', - 2: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', -} -CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0 -CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 1 -CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 2 -CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR' -CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR__enumvalues = { - 0: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', - 1: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', -} -CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0 -CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 1 -CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR' -CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { - 0: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', - 1: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', -} -CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 -CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 -CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR' -CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR__enumvalues = { - 0: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', - 1: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', -} -CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0 -CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 1 -CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', -} -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE' -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', -} -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR' -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', -} -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE' -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', -} -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR' -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', -} -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE' -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', -} -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE' -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', -} -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR' -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', -} -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE' -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', -} -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE' -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { - 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', -} -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 -CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_EN' -CRTC_CRC_CNTL_CRTC_CRC_EN__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', - 1: 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', -} -CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0 -CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 1 -CRTC_CRC_CNTL_CRTC_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN' -CRTC_CRC_CNTL_CRTC_CRC_CONT_EN__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', - 1: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', -} -CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0 -CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 1 -CRTC_CRC_CNTL_CRTC_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE' -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', - 1: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', - 2: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', - 3: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', -} -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0 -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 1 -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 2 -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 3 -CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE' -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', - 1: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', - 2: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', -} -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0 -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 1 -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 3 -CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS' -CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 1: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', -} -CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 -CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 -CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT' -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', - 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', - 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', - 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', - 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', - 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', - 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', - 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', -} -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 1 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 2 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 3 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 4 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 5 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 6 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 7 -CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT' -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT__enumvalues = { - 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', - 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', - 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', - 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', - 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', - 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', - 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', - 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', -} -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 1 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 2 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 3 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 4 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 5 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 6 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 7 -CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', - 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', - 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', - 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', - 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE' -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', -} -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE' -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR' -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', -} -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE' -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', -} -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', - 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', - 2: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', - 3: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', - 4: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', - 5: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', - 6: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', - 7: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', -} -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 -CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE' -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR' -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', -} -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 1 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE' -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', -} -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', -} -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR' -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', -} -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { - 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', - 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', -} -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 -CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE' -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE__enumvalues = { - 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', - 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', -} -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 1 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR' -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR__enumvalues = { - 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', - 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', -} -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 1 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE' -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE__enumvalues = { - 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', - 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', -} -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 1 -CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE' -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE__enumvalues = { - 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', - 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', -} -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0 -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 1 -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE' -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { - 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', -} -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 -CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN' -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN__enumvalues = { - 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', - 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', -} -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 1 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB' -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB__enumvalues = { - 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', - 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', -} -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 1 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE' -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { - 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 2: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 3: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', -} -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR' -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { - 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', -} -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 -CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_V_SYNC_A_POL' -CRTC_V_SYNC_A_POL__enumvalues = { - 0: 'CRTC_V_SYNC_A_POL_HIGH', - 1: 'CRTC_V_SYNC_A_POL_LOW', -} -CRTC_V_SYNC_A_POL_HIGH = 0 -CRTC_V_SYNC_A_POL_LOW = 1 -CRTC_V_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_H_SYNC_A_POL' -CRTC_H_SYNC_A_POL__enumvalues = { - 0: 'CRTC_H_SYNC_A_POL_HIGH', - 1: 'CRTC_H_SYNC_A_POL_LOW', -} -CRTC_H_SYNC_A_POL_HIGH = 0 -CRTC_H_SYNC_A_POL_LOW = 1 -CRTC_H_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_HORZ_REPETITION_COUNT' -CRTC_HORZ_REPETITION_COUNT__enumvalues = { - 0: 'CRTC_HORZ_REPETITION_COUNT_0', - 1: 'CRTC_HORZ_REPETITION_COUNT_1', - 2: 'CRTC_HORZ_REPETITION_COUNT_2', - 3: 'CRTC_HORZ_REPETITION_COUNT_3', - 4: 'CRTC_HORZ_REPETITION_COUNT_4', - 5: 'CRTC_HORZ_REPETITION_COUNT_5', - 6: 'CRTC_HORZ_REPETITION_COUNT_6', - 7: 'CRTC_HORZ_REPETITION_COUNT_7', - 8: 'CRTC_HORZ_REPETITION_COUNT_8', - 9: 'CRTC_HORZ_REPETITION_COUNT_9', - 10: 'CRTC_HORZ_REPETITION_COUNT_10', - 11: 'CRTC_HORZ_REPETITION_COUNT_11', - 12: 'CRTC_HORZ_REPETITION_COUNT_12', - 13: 'CRTC_HORZ_REPETITION_COUNT_13', - 14: 'CRTC_HORZ_REPETITION_COUNT_14', - 15: 'CRTC_HORZ_REPETITION_COUNT_15', -} -CRTC_HORZ_REPETITION_COUNT_0 = 0 -CRTC_HORZ_REPETITION_COUNT_1 = 1 -CRTC_HORZ_REPETITION_COUNT_2 = 2 -CRTC_HORZ_REPETITION_COUNT_3 = 3 -CRTC_HORZ_REPETITION_COUNT_4 = 4 -CRTC_HORZ_REPETITION_COUNT_5 = 5 -CRTC_HORZ_REPETITION_COUNT_6 = 6 -CRTC_HORZ_REPETITION_COUNT_7 = 7 -CRTC_HORZ_REPETITION_COUNT_8 = 8 -CRTC_HORZ_REPETITION_COUNT_9 = 9 -CRTC_HORZ_REPETITION_COUNT_10 = 10 -CRTC_HORZ_REPETITION_COUNT_11 = 11 -CRTC_HORZ_REPETITION_COUNT_12 = 12 -CRTC_HORZ_REPETITION_COUNT_13 = 13 -CRTC_HORZ_REPETITION_COUNT_14 = 14 -CRTC_HORZ_REPETITION_COUNT_15 = 15 -CRTC_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DRR_MODE_DBUF_UPDATE_MODE' -CRTC_DRR_MODE_DBUF_UPDATE_MODE__enumvalues = { - 0: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', - 1: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', - 2: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', - 3: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', -} -CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0 -CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 1 -CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 2 -CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 3 -CRTC_DRR_MODE_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' -FMT_CONTROL_PIXEL_ENCODING__enumvalues = { - 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', -} -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 -FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' -FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', -} -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 -FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' -FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', -} -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 -FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { - 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', -} -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' -FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' -FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', -} -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' -FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' -FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { - 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', -} -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 -FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_CONT_EN' -FMT_CRC_CNTL_CONT_EN__enumvalues = { - 0: 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', - 1: 'FMT_CRC_CNTL_CONT_EN_CONT', -} -FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0 -FMT_CRC_CNTL_CONT_EN_CONT = 1 -FMT_CRC_CNTL_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_INCLUDE_OVERSCAN' -FMT_CRC_CNTL_INCLUDE_OVERSCAN__enumvalues = { - 0: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', - 1: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', -} -FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0 -FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 1 -FMT_CRC_CNTL_INCLUDE_OVERSCAN = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_ONLY_BLANKB' -FMT_CRC_CNTL_ONLY_BLANKB__enumvalues = { - 0: 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', - 1: 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', -} -FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0 -FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 1 -FMT_CRC_CNTL_ONLY_BLANKB = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_PSR_MODE_ENABLE' -FMT_CRC_CNTL_PSR_MODE_ENABLE__enumvalues = { - 0: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', - 1: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', -} -FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0 -FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 1 -FMT_CRC_CNTL_PSR_MODE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_INTERLACE_MODE' -FMT_CRC_CNTL_INTERLACE_MODE__enumvalues = { - 0: 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', - 1: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', - 2: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', -} -FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0 -FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 1 -FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 2 -FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 3 -FMT_CRC_CNTL_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE' -FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE__enumvalues = { - 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', - 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', -} -FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0 -FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 1 -FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT' -FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT__enumvalues = { - 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', - 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', -} -FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0 -FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 1 -FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' -FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { - 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', -} -FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 -FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 -FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 -FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 -FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_MODE' -FMT_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_MODE_0', - 1: 'FMT_SPATIAL_DITHER_MODE_1', - 2: 'FMT_SPATIAL_DITHER_MODE_2', - 3: 'FMT_SPATIAL_DITHER_MODE_3', -} -FMT_SPATIAL_DITHER_MODE_0 = 0 -FMT_SPATIAL_DITHER_MODE_1 = 1 -FMT_SPATIAL_DITHER_MODE_2 = 2 -FMT_SPATIAL_DITHER_MODE_3 = 3 -FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_STEREOSYNC_OVR_POL' -FMT_STEREOSYNC_OVR_POL__enumvalues = { - 0: 'FMT_STEREOSYNC_OVR_POL_INVERTED', - 1: 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', -} -FMT_STEREOSYNC_OVR_POL_INVERTED = 0 -FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 1 -FMT_STEREOSYNC_OVR_POL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DYNAMIC_EXP_MODE' -FMT_DYNAMIC_EXP_MODE__enumvalues = { - 0: 'FMT_DYNAMIC_EXP_MODE_10to12', - 1: 'FMT_DYNAMIC_EXP_MODE_8to12', -} -FMT_DYNAMIC_EXP_MODE_10to12 = 0 -FMT_DYNAMIC_EXP_MODE_8to12 = 1 -FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_ACK' -HPD_INT_CONTROL_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_ACK_0', - 1: 'HPD_INT_CONTROL_ACK_1', -} -HPD_INT_CONTROL_ACK_0 = 0 -HPD_INT_CONTROL_ACK_1 = 1 -HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_POLARITY' -HPD_INT_CONTROL_POLARITY__enumvalues = { - 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', - 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', -} -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 -HPD_INT_CONTROL_GEN_INT_ON_CON = 1 -HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' -HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', - 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', -} -HPD_INT_CONTROL_RX_INT_ACK_0 = 0 -HPD_INT_CONTROL_RX_INT_ACK_1 = 1 -HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_PIXEL_DEPTH' -LB_DATA_FORMAT_PIXEL_DEPTH__enumvalues = { - 0: 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', - 1: 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', - 2: 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', - 3: 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', -} -LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0 -LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 1 -LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 2 -LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 3 -LB_DATA_FORMAT_PIXEL_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE' -LB_DATA_FORMAT_PIXEL_EXPAN_MODE__enumvalues = { - 0: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', - 1: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', -} -LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0 -LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 1 -LB_DATA_FORMAT_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE' -LB_DATA_FORMAT_PIXEL_REDUCE_MODE__enumvalues = { - 0: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', - 1: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', -} -LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0 -LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 1 -LB_DATA_FORMAT_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH' -LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH__enumvalues = { - 0: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', - 1: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', -} -LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0 -LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 1 -LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_INTERLEAVE_EN' -LB_DATA_FORMAT_INTERLEAVE_EN__enumvalues = { - 0: 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', - 1: 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', -} -LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0 -LB_DATA_FORMAT_INTERLEAVE_ENABLE = 1 -LB_DATA_FORMAT_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_REQUEST_MODE' -LB_DATA_FORMAT_REQUEST_MODE__enumvalues = { - 0: 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', - 1: 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', -} -LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0 -LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 1 -LB_DATA_FORMAT_REQUEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DATA_FORMAT_ALPHA_EN' -LB_DATA_FORMAT_ALPHA_EN__enumvalues = { - 0: 'LB_DATA_FORMAT_ALPHA_DISABLE', - 1: 'LB_DATA_FORMAT_ALPHA_ENABLE', -} -LB_DATA_FORMAT_ALPHA_DISABLE = 0 -LB_DATA_FORMAT_ALPHA_ENABLE = 1 -LB_DATA_FORMAT_ALPHA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE_START_END_VLINE_INV' -LB_VLINE_START_END_VLINE_INV__enumvalues = { - 0: 'LB_VLINE_START_END_VLINE_NORMAL', - 1: 'LB_VLINE_START_END_VLINE_INVERSE', -} -LB_VLINE_START_END_VLINE_NORMAL = 0 -LB_VLINE_START_END_VLINE_INVERSE = 1 -LB_VLINE_START_END_VLINE_INV = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE2_START_END_VLINE2_INV' -LB_VLINE2_START_END_VLINE2_INV__enumvalues = { - 0: 'LB_VLINE2_START_END_VLINE2_NORMAL', - 1: 'LB_VLINE2_START_END_VLINE2_INVERSE', -} -LB_VLINE2_START_END_VLINE2_NORMAL = 0 -LB_VLINE2_START_END_VLINE2_INVERSE = 1 -LB_VLINE2_START_END_VLINE2_INV = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK' -LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK__enumvalues = { - 0: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', - 1: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', -} -LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0 -LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 1 -LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK' -LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK__enumvalues = { - 0: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', - 1: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', -} -LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0 -LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 1 -LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK' -LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK__enumvalues = { - 0: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', - 1: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', -} -LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0 -LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 1 -LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE_STATUS_VLINE_ACK' -LB_VLINE_STATUS_VLINE_ACK__enumvalues = { - 0: 'LB_VLINE_STATUS_VLINE_NORMAL', - 1: 'LB_VLINE_STATUS_VLINE_CLEAR', -} -LB_VLINE_STATUS_VLINE_NORMAL = 0 -LB_VLINE_STATUS_VLINE_CLEAR = 1 -LB_VLINE_STATUS_VLINE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE' -LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE__enumvalues = { - 0: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', -} -LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0 -LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 1 -LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE2_STATUS_VLINE2_ACK' -LB_VLINE2_STATUS_VLINE2_ACK__enumvalues = { - 0: 'LB_VLINE2_STATUS_VLINE2_NORMAL', - 1: 'LB_VLINE2_STATUS_VLINE2_CLEAR', -} -LB_VLINE2_STATUS_VLINE2_NORMAL = 0 -LB_VLINE2_STATUS_VLINE2_CLEAR = 1 -LB_VLINE2_STATUS_VLINE2_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE' -LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE__enumvalues = { - 0: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', -} -LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0 -LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 1 -LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VBLANK_STATUS_VBLANK_ACK' -LB_VBLANK_STATUS_VBLANK_ACK__enumvalues = { - 0: 'LB_VBLANK_STATUS_VBLANK_NORMAL', - 1: 'LB_VBLANK_STATUS_VBLANK_CLEAR', -} -LB_VBLANK_STATUS_VBLANK_NORMAL = 0 -LB_VBLANK_STATUS_VBLANK_CLEAR = 1 -LB_VBLANK_STATUS_VBLANK_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE' -LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE__enumvalues = { - 0: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', -} -LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0 -LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 1 -LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL' -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL__enumvalues = { - 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', - 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', - 2: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', - 3: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', -} -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 1 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 2 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 3 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2' -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2__enumvalues = { - 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', - 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', -} -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 1 -LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION' -LB_SYNC_RESET_SEL_LB_SYNC_DURATION__enumvalues = { - 0: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', - 1: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', - 2: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', - 3: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', -} -LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0 -LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 1 -LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 2 -LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 3 -LB_SYNC_RESET_SEL_LB_SYNC_DURATION = ctypes.c_uint32 # enum - -# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN' -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN__enumvalues = { - 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', - 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', -} -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0 -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 1 -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN' -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN__enumvalues = { - 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', - 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', -} -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0 -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 1 -LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK' -LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK__enumvalues = { - 0: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', - 1: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', -} -LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0 -LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 1 -LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK' -LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK__enumvalues = { - 0: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', - 1: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', -} -LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0 -LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 1 -LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE' -LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE__enumvalues = { - 2: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', - 3: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', -} -LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 2 -LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 3 -LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET' -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET__enumvalues = { - 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', - 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', -} -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0 -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 1 -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK' -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK__enumvalues = { - 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', - 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', -} -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0 -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 1 -LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE' -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE__enumvalues = { - 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', - 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', - 2: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', -} -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0 -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 1 -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 2 -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE' -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE__enumvalues = { - 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', - 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', -} -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0 -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 1 -LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE' -LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE__enumvalues = { - 1: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', - 2: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', -} -ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 1 -ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 2 -LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL' -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL__enumvalues = { - 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', - 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', -} -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 1 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE' -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__enumvalues = { - 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', - 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', -} -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 1 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE = ctypes.c_uint32 # enum - -# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO' -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__enumvalues = { - 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', - 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', -} -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 1 -LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO = ctypes.c_uint32 # enum - -# values for enumeration 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN' -LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', - 1: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', -} -LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0 -LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 1 -LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_KEEPOUT_MODE' -HDMI_KEEPOUT_MODE__enumvalues = { - 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', -} -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 -HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' -HDMI_DATA_SCRAMBLE_EN__enumvalues = { - 0: 'HDMI_DATA_SCRAMBLE_DISABLE', - 1: 'HDMI_DATA_SCRAMBLE_ENABLE', -} -HDMI_DATA_SCRAMBLE_DISABLE = 0 -HDMI_DATA_SCRAMBLE_ENABLE = 1 -HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' -HDMI_CLOCK_CHANNEL_RATE__enumvalues = { - 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', -} -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 -HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' -HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { - 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', - 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', -} -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 -HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_GEN_VERSION' -HDMI_PACKET_GEN_VERSION__enumvalues = { - 0: 'HDMI_PACKET_GEN_VERSION_OLD', - 1: 'HDMI_PACKET_GEN_VERSION_NEW', -} -HDMI_PACKET_GEN_VERSION_OLD = 0 -HDMI_PACKET_GEN_VERSION_NEW = 1 -HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_ACK' -HDMI_ERROR_ACK__enumvalues = { - 0: 'HDMI_ERROR_ACK_INT', - 1: 'HDMI_ERROR_NOT_ACK', -} -HDMI_ERROR_ACK_INT = 0 -HDMI_ERROR_NOT_ACK = 1 -HDMI_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_MASK' -HDMI_ERROR_MASK__enumvalues = { - 0: 'HDMI_ERROR_MASK_INT', - 1: 'HDMI_ERROR_NOT_MASK', -} -HDMI_ERROR_MASK_INT = 0 -HDMI_ERROR_NOT_MASK = 1 -HDMI_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' -HDMI_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 3: 'HDMI_DEEP_COLOR_DEPTH_RESERVED', -} -HDMI_DEEP_COLOR_DEPTH_24BPP = 0 -HDMI_DEEP_COLOR_DEPTH_30BPP = 1 -HDMI_DEEP_COLOR_DEPTH_36BPP = 2 -HDMI_DEEP_COLOR_DEPTH_RESERVED = 3 -HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_DELAY_EN' -HDMI_AUDIO_DELAY_EN__enumvalues = { - 0: 'HDMI_AUDIO_DELAY_DISABLE', - 1: 'HDMI_AUDIO_DELAY_58CLK', - 2: 'HDMI_AUDIO_DELAY_56CLK', - 3: 'HDMI_AUDIO_DELAY_RESERVED', -} -HDMI_AUDIO_DELAY_DISABLE = 0 -HDMI_AUDIO_DELAY_58CLK = 1 -HDMI_AUDIO_DELAY_56CLK = 2 -HDMI_AUDIO_DELAY_RESERVED = 3 -HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' -HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { - 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', -} -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 -HDMI_SEND_MAX_AUDIO_PACKETS = 1 -HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SEND' -HDMI_ACR_SEND__enumvalues = { - 0: 'HDMI_ACR_NOT_SEND', - 1: 'HDMI_ACR_PKT_SEND', -} -HDMI_ACR_NOT_SEND = 0 -HDMI_ACR_PKT_SEND = 1 -HDMI_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_CONT' -HDMI_ACR_CONT__enumvalues = { - 0: 'HDMI_ACR_CONT_DISABLE', - 1: 'HDMI_ACR_CONT_ENABLE', -} -HDMI_ACR_CONT_DISABLE = 0 -HDMI_ACR_CONT_ENABLE = 1 -HDMI_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SELECT' -HDMI_ACR_SELECT__enumvalues = { - 0: 'HDMI_ACR_SELECT_HW', - 1: 'HDMI_ACR_SELECT_32K', - 2: 'HDMI_ACR_SELECT_44K', - 3: 'HDMI_ACR_SELECT_48K', -} -HDMI_ACR_SELECT_HW = 0 -HDMI_ACR_SELECT_32K = 1 -HDMI_ACR_SELECT_44K = 2 -HDMI_ACR_SELECT_48K = 3 -HDMI_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SOURCE' -HDMI_ACR_SOURCE__enumvalues = { - 0: 'HDMI_ACR_SOURCE_HW', - 1: 'HDMI_ACR_SOURCE_SW', -} -HDMI_ACR_SOURCE_HW = 0 -HDMI_ACR_SOURCE_SW = 1 -HDMI_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_N_MULTIPLE' -HDMI_ACR_N_MULTIPLE__enumvalues = { - 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', - 1: 'HDMI_ACR_1_MULTIPLE', - 2: 'HDMI_ACR_2_MULTIPLE', - 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', - 4: 'HDMI_ACR_4_MULTIPLE', - 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', - 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', - 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', -} -HDMI_ACR_0_MULTIPLE_RESERVED = 0 -HDMI_ACR_1_MULTIPLE = 1 -HDMI_ACR_2_MULTIPLE = 2 -HDMI_ACR_3_MULTIPLE_RESERVED = 3 -HDMI_ACR_4_MULTIPLE = 4 -HDMI_ACR_5_MULTIPLE_RESERVED = 5 -HDMI_ACR_6_MULTIPLE_RESERVED = 6 -HDMI_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' -HDMI_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NULL_SEND' -HDMI_NULL_SEND__enumvalues = { - 0: 'HDMI_NULL_NOT_SEND', - 1: 'HDMI_NULL_PKT_SEND', -} -HDMI_NULL_NOT_SEND = 0 -HDMI_NULL_PKT_SEND = 1 -HDMI_NULL_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_SEND' -HDMI_GC_SEND__enumvalues = { - 0: 'HDMI_GC_NOT_SEND', - 1: 'HDMI_GC_PKT_SEND', -} -HDMI_GC_NOT_SEND = 0 -HDMI_GC_PKT_SEND = 1 -HDMI_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_CONT' -HDMI_GC_CONT__enumvalues = { - 0: 'HDMI_GC_CONT_DISABLE', - 1: 'HDMI_GC_CONT_ENABLE', -} -HDMI_GC_CONT_DISABLE = 0 -HDMI_GC_CONT_ENABLE = 1 -HDMI_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_SEND' -HDMI_ISRC_SEND__enumvalues = { - 0: 'HDMI_ISRC_NOT_SEND', - 1: 'HDMI_ISRC_PKT_SEND', -} -HDMI_ISRC_NOT_SEND = 0 -HDMI_ISRC_PKT_SEND = 1 -HDMI_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_CONT' -HDMI_ISRC_CONT__enumvalues = { - 0: 'HDMI_ISRC_CONT_DISABLE', - 1: 'HDMI_ISRC_CONT_ENABLE', -} -HDMI_ISRC_CONT_DISABLE = 0 -HDMI_ISRC_CONT_ENABLE = 1 -HDMI_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AVI_INFO_SEND' -HDMI_AVI_INFO_SEND__enumvalues = { - 0: 'HDMI_AVI_INFO_NOT_SEND', - 1: 'HDMI_AVI_INFO_PKT_SEND', -} -HDMI_AVI_INFO_NOT_SEND = 0 -HDMI_AVI_INFO_PKT_SEND = 1 -HDMI_AVI_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AVI_INFO_CONT' -HDMI_AVI_INFO_CONT__enumvalues = { - 0: 'HDMI_AVI_INFO_CONT_DISABLE', - 1: 'HDMI_AVI_INFO_CONT_ENABLE', -} -HDMI_AVI_INFO_CONT_DISABLE = 0 -HDMI_AVI_INFO_CONT_ENABLE = 1 -HDMI_AVI_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_SEND' -HDMI_AUDIO_INFO_SEND__enumvalues = { - 0: 'HDMI_AUDIO_INFO_NOT_SEND', - 1: 'HDMI_AUDIO_INFO_PKT_SEND', -} -HDMI_AUDIO_INFO_NOT_SEND = 0 -HDMI_AUDIO_INFO_PKT_SEND = 1 -HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_CONT' -HDMI_AUDIO_INFO_CONT__enumvalues = { - 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', - 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', -} -HDMI_AUDIO_INFO_CONT_DISABLE = 0 -HDMI_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_SEND' -HDMI_MPEG_INFO_SEND__enumvalues = { - 0: 'HDMI_MPEG_INFO_NOT_SEND', - 1: 'HDMI_MPEG_INFO_PKT_SEND', -} -HDMI_MPEG_INFO_NOT_SEND = 0 -HDMI_MPEG_INFO_PKT_SEND = 1 -HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_CONT' -HDMI_MPEG_INFO_CONT__enumvalues = { - 0: 'HDMI_MPEG_INFO_CONT_DISABLE', - 1: 'HDMI_MPEG_INFO_CONT_ENABLE', -} -HDMI_MPEG_INFO_CONT_DISABLE = 0 -HDMI_MPEG_INFO_CONT_ENABLE = 1 -HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC0_SEND' -HDMI_GENERIC0_SEND__enumvalues = { - 0: 'HDMI_GENERIC0_NOT_SEND', - 1: 'HDMI_GENERIC0_PKT_SEND', -} -HDMI_GENERIC0_NOT_SEND = 0 -HDMI_GENERIC0_PKT_SEND = 1 -HDMI_GENERIC0_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC0_CONT' -HDMI_GENERIC0_CONT__enumvalues = { - 0: 'HDMI_GENERIC0_CONT_DISABLE', - 1: 'HDMI_GENERIC0_CONT_ENABLE', -} -HDMI_GENERIC0_CONT_DISABLE = 0 -HDMI_GENERIC0_CONT_ENABLE = 1 -HDMI_GENERIC0_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC1_SEND' -HDMI_GENERIC1_SEND__enumvalues = { - 0: 'HDMI_GENERIC1_NOT_SEND', - 1: 'HDMI_GENERIC1_PKT_SEND', -} -HDMI_GENERIC1_NOT_SEND = 0 -HDMI_GENERIC1_PKT_SEND = 1 -HDMI_GENERIC1_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC1_CONT' -HDMI_GENERIC1_CONT__enumvalues = { - 0: 'HDMI_GENERIC1_CONT_DISABLE', - 1: 'HDMI_GENERIC1_CONT_ENABLE', -} -HDMI_GENERIC1_CONT_DISABLE = 0 -HDMI_GENERIC1_CONT_ENABLE = 1 -HDMI_GENERIC1_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE_CONT' -HDMI_GC_AVMUTE_CONT__enumvalues = { - 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', - 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', -} -HDMI_GC_AVMUTE_CONT_DISABLE = 0 -HDMI_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' -HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { - 0: 'HDMI_PACKING_PHASE_SET_BY_HW', - 1: 'HDMI_PACKING_PHASE_SET_BY_SW', -} -HDMI_PACKING_PHASE_SET_BY_HW = 0 -HDMI_PACKING_PHASE_SET_BY_SW = 1 -HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC2_SEND' -HDMI_GENERIC2_SEND__enumvalues = { - 0: 'HDMI_GENERIC2_NOT_SEND', - 1: 'HDMI_GENERIC2_PKT_SEND', -} -HDMI_GENERIC2_NOT_SEND = 0 -HDMI_GENERIC2_PKT_SEND = 1 -HDMI_GENERIC2_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC2_CONT' -HDMI_GENERIC2_CONT__enumvalues = { - 0: 'HDMI_GENERIC2_CONT_DISABLE', - 1: 'HDMI_GENERIC2_CONT_ENABLE', -} -HDMI_GENERIC2_CONT_DISABLE = 0 -HDMI_GENERIC2_CONT_ENABLE = 1 -HDMI_GENERIC2_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC3_SEND' -HDMI_GENERIC3_SEND__enumvalues = { - 0: 'HDMI_GENERIC3_NOT_SEND', - 1: 'HDMI_GENERIC3_PKT_SEND', -} -HDMI_GENERIC3_NOT_SEND = 0 -HDMI_GENERIC3_PKT_SEND = 1 -HDMI_GENERIC3_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC3_CONT' -HDMI_GENERIC3_CONT__enumvalues = { - 0: 'HDMI_GENERIC3_CONT_DISABLE', - 1: 'HDMI_GENERIC3_CONT_ENABLE', -} -HDMI_GENERIC3_CONT_DISABLE = 0 -HDMI_GENERIC3_CONT_ENABLE = 1 -HDMI_GENERIC3_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_PIXEL_ENCODING' -TMDS_PIXEL_ENCODING__enumvalues = { - 0: 'TMDS_PIXEL_ENCODING_444_OR_420', - 1: 'TMDS_PIXEL_ENCODING_422', -} -TMDS_PIXEL_ENCODING_444_OR_420 = 0 -TMDS_PIXEL_ENCODING_422 = 1 -TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_COLOR_FORMAT' -TMDS_COLOR_FORMAT__enumvalues = { - 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', - 3: 'TMDS_COLOR_FORMAT_RESERVED', -} -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 -TMDS_COLOR_FORMAT_DUAL30BPP = 2 -TMDS_COLOR_FORMAT_RESERVED = 3 -TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' -TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { - 0: 'TMDS_STEREOSYNC_CTL0', - 1: 'TMDS_STEREOSYNC_CTL1', - 2: 'TMDS_STEREOSYNC_CTL2', - 3: 'TMDS_STEREOSYNC_CTL3', -} -TMDS_STEREOSYNC_CTL0 = 0 -TMDS_STEREOSYNC_CTL1 = 1 -TMDS_STEREOSYNC_CTL2 = 2 -TMDS_STEREOSYNC_CTL3 = 3 -TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_SEL' -TMDS_CTL0_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', -} -TMDS_CTL0_DATA_SEL0_RESERVED = 0 -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL0_DATA_SEL2_VSYNC = 2 -TMDS_CTL0_DATA_SEL3_RESERVED = 3 -TMDS_CTL0_DATA_SEL4_HSYNC = 4 -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 -TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_INVERT' -TMDS_CTL0_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL0_DATA_NORMAL', - 1: 'TMDS_CTL0_DATA_INVERT_EN', -} -TMDS_CTL0_DATA_NORMAL = 0 -TMDS_CTL0_DATA_INVERT_EN = 1 -TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_MODULATION' -TMDS_CTL0_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', -} -TMDS_CTL0_DATA_MODULATION_DISABLE = 0 -TMDS_CTL0_DATA_MODULATION_BIT0 = 1 -TMDS_CTL0_DATA_MODULATION_BIT1 = 2 -TMDS_CTL0_DATA_MODULATION_BIT2 = 3 -TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' -TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', -} -TMDS_CTL0_PATTERN_OUT_DISABLE = 0 -TMDS_CTL0_PATTERN_OUT_ENABLE = 1 -TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_SEL' -TMDS_CTL1_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL1_DATA_SEL0_RESERVED = 0 -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL1_DATA_SEL2_VSYNC = 2 -TMDS_CTL1_DATA_SEL3_RESERVED = 3 -TMDS_CTL1_DATA_SEL4_HSYNC = 4 -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_INVERT' -TMDS_CTL1_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL1_DATA_NORMAL', - 1: 'TMDS_CTL1_DATA_INVERT_EN', -} -TMDS_CTL1_DATA_NORMAL = 0 -TMDS_CTL1_DATA_INVERT_EN = 1 -TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_MODULATION' -TMDS_CTL1_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', -} -TMDS_CTL1_DATA_MODULATION_DISABLE = 0 -TMDS_CTL1_DATA_MODULATION_BIT0 = 1 -TMDS_CTL1_DATA_MODULATION_BIT1 = 2 -TMDS_CTL1_DATA_MODULATION_BIT2 = 3 -TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' -TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', -} -TMDS_CTL1_PATTERN_OUT_DISABLE = 0 -TMDS_CTL1_PATTERN_OUT_ENABLE = 1 -TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_SEL' -TMDS_CTL2_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL2_DATA_SEL0_RESERVED = 0 -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL2_DATA_SEL2_VSYNC = 2 -TMDS_CTL2_DATA_SEL3_RESERVED = 3 -TMDS_CTL2_DATA_SEL4_HSYNC = 4 -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_INVERT' -TMDS_CTL2_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL2_DATA_NORMAL', - 1: 'TMDS_CTL2_DATA_INVERT_EN', -} -TMDS_CTL2_DATA_NORMAL = 0 -TMDS_CTL2_DATA_INVERT_EN = 1 -TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_MODULATION' -TMDS_CTL2_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', -} -TMDS_CTL2_DATA_MODULATION_DISABLE = 0 -TMDS_CTL2_DATA_MODULATION_BIT0 = 1 -TMDS_CTL2_DATA_MODULATION_BIT1 = 2 -TMDS_CTL2_DATA_MODULATION_BIT2 = 3 -TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' -TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', -} -TMDS_CTL2_PATTERN_OUT_DISABLE = 0 -TMDS_CTL2_PATTERN_OUT_ENABLE = 1 -TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_INVERT' -TMDS_CTL3_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL3_DATA_NORMAL', - 1: 'TMDS_CTL3_DATA_INVERT_EN', -} -TMDS_CTL3_DATA_NORMAL = 0 -TMDS_CTL3_DATA_INVERT_EN = 1 -TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_MODULATION' -TMDS_CTL3_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', -} -TMDS_CTL3_DATA_MODULATION_DISABLE = 0 -TMDS_CTL3_DATA_MODULATION_BIT0 = 1 -TMDS_CTL3_DATA_MODULATION_BIT1 = 2 -TMDS_CTL3_DATA_MODULATION_BIT2 = 3 -TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' -TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', -} -TMDS_CTL3_PATTERN_OUT_DISABLE = 0 -TMDS_CTL3_PATTERN_OUT_ENABLE = 1 -TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_SEL' -TMDS_CTL3_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL3_DATA_SEL0_RESERVED = 0 -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL3_DATA_SEL2_VSYNC = 2 -TMDS_CTL3_DATA_SEL3_RESERVED = 3 -TMDS_CTL3_DATA_SEL4_HSYNC = 4 -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' -DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { - 0: 'DIG_FE_SOURCE_FROM_FMT0', - 1: 'DIG_FE_SOURCE_FROM_FMT1', - 2: 'DIG_FE_SOURCE_FROM_FMT2', - 3: 'DIG_FE_SOURCE_FROM_FMT3', - 4: 'DIG_FE_SOURCE_FROM_FMT4', - 5: 'DIG_FE_SOURCE_FROM_FMT5', -} -DIG_FE_SOURCE_FROM_FMT0 = 0 -DIG_FE_SOURCE_FROM_FMT1 = 1 -DIG_FE_SOURCE_FROM_FMT2 = 2 -DIG_FE_SOURCE_FROM_FMT3 = 3 -DIG_FE_SOURCE_FROM_FMT4 = 4 -DIG_FE_SOURCE_FROM_FMT5 = 5 -DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' -DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { - 0: 'DIG_FE_STEREOSYNC_FROM_FMT0', - 1: 'DIG_FE_STEREOSYNC_FROM_FMT1', - 2: 'DIG_FE_STEREOSYNC_FROM_FMT2', - 3: 'DIG_FE_STEREOSYNC_FROM_FMT3', - 4: 'DIG_FE_STEREOSYNC_FROM_FMT4', - 5: 'DIG_FE_STEREOSYNC_FROM_FMT5', -} -DIG_FE_STEREOSYNC_FROM_FMT0 = 0 -DIG_FE_STEREOSYNC_FROM_FMT1 = 1 -DIG_FE_STEREOSYNC_FROM_FMT2 = 2 -DIG_FE_STEREOSYNC_FROM_FMT3 = 3 -DIG_FE_STEREOSYNC_FROM_FMT4 = 4 -DIG_FE_STEREOSYNC_FROM_FMT5 = 5 -DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' -DIG_FIFO_READ_CLOCK_SRC__enumvalues = { - 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', -} -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 -DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' -DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_ON_LINK0', - 1: 'DIG_OUTPUT_CRC_ON_LINK1', -} -DIG_OUTPUT_CRC_ON_LINK0 = 0 -DIG_OUTPUT_CRC_ON_LINK1 = 1 -DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' -DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 2: 'DIG_OUTPUT_CRC_FOR_VBI', - 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', -} -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 -DIG_OUTPUT_CRC_FOR_VBI = 2 -DIG_OUTPUT_CRC_FOR_AUDIO = 3 -DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_IN_NORMAL_OPERATION', - 1: 'DIG_IN_DEBUG_MODE', -} -DIG_IN_NORMAL_OPERATION = 0 -DIG_IN_DEBUG_MODE = 1 -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { - 0: 'DIG_10BIT_TEST_PATTERN', - 1: 'DIG_ALTERNATING_TEST_PATTERN', -} -DIG_10BIT_TEST_PATTERN = 0 -DIG_ALTERNATING_TEST_PATTERN = 1 -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_NORMAL', - 1: 'DIG_TEST_PATTERN_RANDOM', -} -DIG_TEST_PATTERN_NORMAL = 0 -DIG_TEST_PATTERN_RANDOM = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_ENABLED', - 1: 'DIG_RANDOM_PATTERN_RESETED', -} -DIG_RANDOM_PATTERN_ENABLED = 0 -DIG_RANDOM_PATTERN_RESETED = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' -DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', -} -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 -DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' -DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', -} -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 -DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' -DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', -} -DIG_FIFO_USE_OVERWRITE_LEVEL = 0 -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 -DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_ERROR_ACK' -DIG_FIFO_ERROR_ACK__enumvalues = { - 0: 'DIG_FIFO_ERROR_ACK_INT', - 1: 'DIG_FIFO_ERROR_NOT_ACK', -} -DIG_FIFO_ERROR_ACK_INT = 0 -DIG_FIFO_ERROR_NOT_ACK = 1 -DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' -DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', -} -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 -DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' -DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', - 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', -} -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 -DIG_FIFO_FORCE_RECOMP_MINMAX = 1 -DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' -AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { - 0: 'AFMT_INTERRUPT_DISABLE', - 1: 'AFMT_INTERRUPT_ENABLE', -} -AFMT_INTERRUPT_DISABLE = 0 -AFMT_INTERRUPT_ENABLE = 1 -AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE' -HDMI_GC_AVMUTE__enumvalues = { - 0: 'HDMI_GC_AVMUTE_SET', - 1: 'HDMI_GC_AVMUTE_UNSET', -} -HDMI_GC_AVMUTE_SET = 0 -HDMI_GC_AVMUTE_UNSET = 1 -HDMI_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEFAULT_PAHSE' -HDMI_DEFAULT_PAHSE__enumvalues = { - 0: 'HDMI_DEFAULT_PHASE_IS_0', - 1: 'HDMI_DEFAULT_PHASE_IS_1', -} -HDMI_DEFAULT_PHASE_IS_0 = 0 -HDMI_DEFAULT_PHASE_IS_1 = 1 -HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { - 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', -} -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum - -# values for enumeration 'AUDIO_LAYOUT_SELECT' -AUDIO_LAYOUT_SELECT__enumvalues = { - 0: 'AUDIO_LAYOUT_0', - 1: 'AUDIO_LAYOUT_1', -} -AUDIO_LAYOUT_0 = 0 -AUDIO_LAYOUT_1 = 1 -AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' -AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'AFMT_AUDIO_CRC_ONESHOT', - 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', -} -AFMT_AUDIO_CRC_ONESHOT = 0 -AFMT_AUDIO_CRC_AUTO_RESTART = 1 -AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' -AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { - 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', -} -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 -AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' -AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'AFMT_AUDIO_CRC_CH0_SIG', - 1: 'AFMT_AUDIO_CRC_CH1_SIG', - 2: 'AFMT_AUDIO_CRC_CH2_SIG', - 3: 'AFMT_AUDIO_CRC_CH3_SIG', - 4: 'AFMT_AUDIO_CRC_CH4_SIG', - 5: 'AFMT_AUDIO_CRC_CH5_SIG', - 6: 'AFMT_AUDIO_CRC_CH6_SIG', - 7: 'AFMT_AUDIO_CRC_CH7_SIG', - 8: 'AFMT_AUDIO_CRC_RESERVED_8', - 9: 'AFMT_AUDIO_CRC_RESERVED_9', - 10: 'AFMT_AUDIO_CRC_RESERVED_10', - 11: 'AFMT_AUDIO_CRC_RESERVED_11', - 12: 'AFMT_AUDIO_CRC_RESERVED_12', - 13: 'AFMT_AUDIO_CRC_RESERVED_13', - 14: 'AFMT_AUDIO_CRC_RESERVED_14', - 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', -} -AFMT_AUDIO_CRC_CH0_SIG = 0 -AFMT_AUDIO_CRC_CH1_SIG = 1 -AFMT_AUDIO_CRC_CH2_SIG = 2 -AFMT_AUDIO_CRC_CH3_SIG = 3 -AFMT_AUDIO_CRC_CH4_SIG = 4 -AFMT_AUDIO_CRC_CH5_SIG = 5 -AFMT_AUDIO_CRC_CH6_SIG = 6 -AFMT_AUDIO_CRC_CH7_SIG = 7 -AFMT_AUDIO_CRC_RESERVED_8 = 8 -AFMT_AUDIO_CRC_RESERVED_9 = 9 -AFMT_AUDIO_CRC_RESERVED_10 = 10 -AFMT_AUDIO_CRC_RESERVED_11 = 11 -AFMT_AUDIO_CRC_RESERVED_12 = 12 -AFMT_AUDIO_CRC_RESERVED_13 = 13 -AFMT_AUDIO_CRC_RESERVED_14 = 14 -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 -AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' -AFMT_RAMP_CONTROL0_SIGN__enumvalues = { - 0: 'AFMT_RAMP_SIGNED', - 1: 'AFMT_RAMP_UNSIGNED', -} -AFMT_RAMP_SIGNED = 0 -AFMT_RAMP_UNSIGNED = 1 -AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { - 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', -} -AFMT_AUDIO_PACKET_SENT_DISABLED = 0 -AFMT_AUDIO_PACKET_SENT_ENABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { - 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', -} -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' -AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { - 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', - 6: 'AFMT_AUDIO_SRC_RESERVED', -} -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 -AFMT_AUDIO_SRC_RESERVED = 6 -AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_MODE' -DIG_BE_CNTL_MODE__enumvalues = { - 0: 'DIG_BE_DP_SST_MODE', - 1: 'DIG_BE_RESERVED1', - 2: 'DIG_BE_TMDS_DVI_MODE', - 3: 'DIG_BE_TMDS_HDMI_MODE', - 4: 'DIG_BE_SDVO_RESERVED', - 5: 'DIG_BE_DP_MST_MODE', - 6: 'DIG_BE_RESERVED2', - 7: 'DIG_BE_RESERVED3', -} -DIG_BE_DP_SST_MODE = 0 -DIG_BE_RESERVED1 = 1 -DIG_BE_TMDS_DVI_MODE = 2 -DIG_BE_TMDS_HDMI_MODE = 3 -DIG_BE_SDVO_RESERVED = 4 -DIG_BE_DP_MST_MODE = 5 -DIG_BE_RESERVED2 = 6 -DIG_BE_RESERVED3 = 7 -DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' -DIG_BE_CNTL_HPD_SELECT__enumvalues = { - 0: 'DIG_BE_CNTL_HPD1', - 1: 'DIG_BE_CNTL_HPD2', - 2: 'DIG_BE_CNTL_HPD3', - 3: 'DIG_BE_CNTL_HPD4', - 4: 'DIG_BE_CNTL_HPD5', - 5: 'DIG_BE_CNTL_HPD6', -} -DIG_BE_CNTL_HPD1 = 0 -DIG_BE_CNTL_HPD2 = 1 -DIG_BE_CNTL_HPD3 = 2 -DIG_BE_CNTL_HPD4 = 3 -DIG_BE_CNTL_HPD5 = 4 -DIG_BE_CNTL_HPD6 = 5 -DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', -} -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_SYNC_PHASE' -TMDS_SYNC_PHASE__enumvalues = { - 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', -} -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TMDS_SYNC_PHASE_ON_FRAME_START = 1 -TMDS_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' -TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { - 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', -} -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', -} -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' -TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' -TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', -} -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', -} -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', -} -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' -TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', -} -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 -TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' -TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', - 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', -} -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 -TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_ENABLE' -DCP_GRPH_ENABLE__enumvalues = { - 0: 'DCP_GRPH_ENABLE_FALSE', - 1: 'DCP_GRPH_ENABLE_TRUE', -} -DCP_GRPH_ENABLE_FALSE = 0 -DCP_GRPH_ENABLE_TRUE = 1 -DCP_GRPH_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_KEYER_ALPHA_SEL' -DCP_GRPH_KEYER_ALPHA_SEL__enumvalues = { - 0: 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', - 1: 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', -} -DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0 -DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 1 -DCP_GRPH_KEYER_ALPHA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DEPTH' -DCP_GRPH_DEPTH__enumvalues = { - 0: 'DCP_GRPH_DEPTH_8BPP', - 1: 'DCP_GRPH_DEPTH_16BPP', - 2: 'DCP_GRPH_DEPTH_32BPP', - 3: 'DCP_GRPH_DEPTH_64BPP', -} -DCP_GRPH_DEPTH_8BPP = 0 -DCP_GRPH_DEPTH_16BPP = 1 -DCP_GRPH_DEPTH_32BPP = 2 -DCP_GRPH_DEPTH_64BPP = 3 -DCP_GRPH_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_NUM_BANKS' -DCP_GRPH_NUM_BANKS__enumvalues = { - 0: 'DCP_GRPH_NUM_BANKS_1BANK', - 1: 'DCP_GRPH_NUM_BANKS_2BANK', - 2: 'DCP_GRPH_NUM_BANKS_4BANK', - 3: 'DCP_GRPH_NUM_BANKS_8BANK', - 4: 'DCP_GRPH_NUM_BANKS_16BANK', -} -DCP_GRPH_NUM_BANKS_1BANK = 0 -DCP_GRPH_NUM_BANKS_2BANK = 1 -DCP_GRPH_NUM_BANKS_4BANK = 2 -DCP_GRPH_NUM_BANKS_8BANK = 3 -DCP_GRPH_NUM_BANKS_16BANK = 4 -DCP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_NUM_PIPES' -DCP_GRPH_NUM_PIPES__enumvalues = { - 0: 'DCP_GRPH_NUM_PIPES_1PIPE', - 1: 'DCP_GRPH_NUM_PIPES_2PIPE', - 2: 'DCP_GRPH_NUM_PIPES_4PIPE', - 3: 'DCP_GRPH_NUM_PIPES_8PIPE', -} -DCP_GRPH_NUM_PIPES_1PIPE = 0 -DCP_GRPH_NUM_PIPES_2PIPE = 1 -DCP_GRPH_NUM_PIPES_4PIPE = 2 -DCP_GRPH_NUM_PIPES_8PIPE = 3 -DCP_GRPH_NUM_PIPES = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_FORMAT' -DCP_GRPH_FORMAT__enumvalues = { - 0: 'DCP_GRPH_FORMAT_8BPP', - 1: 'DCP_GRPH_FORMAT_16BPP', - 2: 'DCP_GRPH_FORMAT_32BPP', - 3: 'DCP_GRPH_FORMAT_64BPP', -} -DCP_GRPH_FORMAT_8BPP = 0 -DCP_GRPH_FORMAT_16BPP = 1 -DCP_GRPH_FORMAT_32BPP = 2 -DCP_GRPH_FORMAT_64BPP = 3 -DCP_GRPH_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE' -DCP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { - 0: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', - 1: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', -} -DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0 -DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 1 -DCP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SW_MODE' -DCP_GRPH_SW_MODE__enumvalues = { - 0: 'DCP_GRPH_SW_MODE_0', - 2: 'DCP_GRPH_SW_MODE_2', - 3: 'DCP_GRPH_SW_MODE_3', - 22: 'DCP_GRPH_SW_MODE_22', - 23: 'DCP_GRPH_SW_MODE_23', - 26: 'DCP_GRPH_SW_MODE_26', - 27: 'DCP_GRPH_SW_MODE_27', - 30: 'DCP_GRPH_SW_MODE_30', - 31: 'DCP_GRPH_SW_MODE_31', -} -DCP_GRPH_SW_MODE_0 = 0 -DCP_GRPH_SW_MODE_2 = 2 -DCP_GRPH_SW_MODE_3 = 3 -DCP_GRPH_SW_MODE_22 = 22 -DCP_GRPH_SW_MODE_23 = 23 -DCP_GRPH_SW_MODE_26 = 26 -DCP_GRPH_SW_MODE_27 = 27 -DCP_GRPH_SW_MODE_30 = 30 -DCP_GRPH_SW_MODE_31 = 31 -DCP_GRPH_SW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_COLOR_EXPANSION_MODE' -DCP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { - 0: 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', - 1: 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', -} -DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0 -DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 1 -DCP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_EN' -DCP_GRPH_LUT_10BIT_BYPASS_EN__enumvalues = { - 0: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', - 1: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', -} -DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0 -DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 1 -DCP_GRPH_LUT_10BIT_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN' -DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__enumvalues = { - 0: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', - 1: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', -} -DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0 -DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 1 -DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_ENDIAN_SWAP' -DCP_GRPH_ENDIAN_SWAP__enumvalues = { - 0: 'DCP_GRPH_ENDIAN_SWAP_NONE', - 1: 'DCP_GRPH_ENDIAN_SWAP_8IN16', - 2: 'DCP_GRPH_ENDIAN_SWAP_8IN32', - 3: 'DCP_GRPH_ENDIAN_SWAP_8IN64', -} -DCP_GRPH_ENDIAN_SWAP_NONE = 0 -DCP_GRPH_ENDIAN_SWAP_8IN16 = 1 -DCP_GRPH_ENDIAN_SWAP_8IN32 = 2 -DCP_GRPH_ENDIAN_SWAP_8IN64 = 3 -DCP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_RED_CROSSBAR' -DCP_GRPH_RED_CROSSBAR__enumvalues = { - 0: 'DCP_GRPH_RED_CROSSBAR_FROM_R', - 1: 'DCP_GRPH_RED_CROSSBAR_FROM_G', - 2: 'DCP_GRPH_RED_CROSSBAR_FROM_B', - 3: 'DCP_GRPH_RED_CROSSBAR_FROM_A', -} -DCP_GRPH_RED_CROSSBAR_FROM_R = 0 -DCP_GRPH_RED_CROSSBAR_FROM_G = 1 -DCP_GRPH_RED_CROSSBAR_FROM_B = 2 -DCP_GRPH_RED_CROSSBAR_FROM_A = 3 -DCP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_GREEN_CROSSBAR' -DCP_GRPH_GREEN_CROSSBAR__enumvalues = { - 0: 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', - 1: 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', - 2: 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', - 3: 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', -} -DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0 -DCP_GRPH_GREEN_CROSSBAR_FROM_B = 1 -DCP_GRPH_GREEN_CROSSBAR_FROM_A = 2 -DCP_GRPH_GREEN_CROSSBAR_FROM_R = 3 -DCP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_BLUE_CROSSBAR' -DCP_GRPH_BLUE_CROSSBAR__enumvalues = { - 0: 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', - 1: 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', - 2: 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', - 3: 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', -} -DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0 -DCP_GRPH_BLUE_CROSSBAR_FROM_A = 1 -DCP_GRPH_BLUE_CROSSBAR_FROM_R = 2 -DCP_GRPH_BLUE_CROSSBAR_FROM_G = 3 -DCP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_ALPHA_CROSSBAR' -DCP_GRPH_ALPHA_CROSSBAR__enumvalues = { - 0: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', - 1: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', - 2: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', - 3: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', -} -DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0 -DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 1 -DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 2 -DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 3 -DCP_GRPH_ALPHA_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRIMARY_DFQ_ENABLE' -DCP_GRPH_PRIMARY_DFQ_ENABLE__enumvalues = { - 0: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', - 1: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', -} -DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0 -DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 1 -DCP_GRPH_PRIMARY_DFQ_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SECONDARY_DFQ_ENABLE' -DCP_GRPH_SECONDARY_DFQ_ENABLE__enumvalues = { - 0: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', - 1: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', -} -DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0 -DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 1 -DCP_GRPH_SECONDARY_DFQ_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_INPUT_GAMMA_MODE' -DCP_GRPH_INPUT_GAMMA_MODE__enumvalues = { - 0: 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', - 1: 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', -} -DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0 -DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 1 -DCP_GRPH_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_MODE_UPDATE_PENDING' -DCP_GRPH_MODE_UPDATE_PENDING__enumvalues = { - 0: 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', - 1: 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', -} -DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0 -DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 1 -DCP_GRPH_MODE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_MODE_UPDATE_TAKEN' -DCP_GRPH_MODE_UPDATE_TAKEN__enumvalues = { - 0: 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', - 1: 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', -} -DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0 -DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 1 -DCP_GRPH_MODE_UPDATE_TAKEN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_PENDING' -DCP_GRPH_SURFACE_UPDATE_PENDING__enumvalues = { - 0: 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', - 1: 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', -} -DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0 -DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 1 -DCP_GRPH_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_TAKEN' -DCP_GRPH_SURFACE_UPDATE_TAKEN__enumvalues = { - 0: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', - 1: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', -} -DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0 -DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 1 -DCP_GRPH_SURFACE_UPDATE_TAKEN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE' -DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE__enumvalues = { - 0: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', - 1: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', -} -DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0 -DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 1 -DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_UPDATE_LOCK' -DCP_GRPH_UPDATE_LOCK__enumvalues = { - 0: 'DCP_GRPH_UPDATE_LOCK_FALSE', - 1: 'DCP_GRPH_UPDATE_LOCK_TRUE', -} -DCP_GRPH_UPDATE_LOCK_FALSE = 0 -DCP_GRPH_UPDATE_LOCK_TRUE = 1 -DCP_GRPH_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' -DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { - 0: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', - 1: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', -} -DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0 -DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 1 -DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' -DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', - 1: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', -} -DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 -DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 -DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' -DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', - 1: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', -} -DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 -DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 -DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN' -DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN__enumvalues = { - 0: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', - 1: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', -} -DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0 -DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 1 -DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_SUPER_AA_EN' -DCP_GRPH_XDMA_SUPER_AA_EN__enumvalues = { - 0: 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', - 1: 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', -} -DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0 -DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 1 -DCP_GRPH_XDMA_SUPER_AA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DFQ_RESET' -DCP_GRPH_DFQ_RESET__enumvalues = { - 0: 'DCP_GRPH_DFQ_RESET_FALSE', - 1: 'DCP_GRPH_DFQ_RESET_TRUE', -} -DCP_GRPH_DFQ_RESET_FALSE = 0 -DCP_GRPH_DFQ_RESET_TRUE = 1 -DCP_GRPH_DFQ_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DFQ_SIZE' -DCP_GRPH_DFQ_SIZE__enumvalues = { - 0: 'DCP_GRPH_DFQ_SIZE_DEEP1', - 1: 'DCP_GRPH_DFQ_SIZE_DEEP2', - 2: 'DCP_GRPH_DFQ_SIZE_DEEP3', - 3: 'DCP_GRPH_DFQ_SIZE_DEEP4', - 4: 'DCP_GRPH_DFQ_SIZE_DEEP5', - 5: 'DCP_GRPH_DFQ_SIZE_DEEP6', - 6: 'DCP_GRPH_DFQ_SIZE_DEEP7', - 7: 'DCP_GRPH_DFQ_SIZE_DEEP8', -} -DCP_GRPH_DFQ_SIZE_DEEP1 = 0 -DCP_GRPH_DFQ_SIZE_DEEP2 = 1 -DCP_GRPH_DFQ_SIZE_DEEP3 = 2 -DCP_GRPH_DFQ_SIZE_DEEP4 = 3 -DCP_GRPH_DFQ_SIZE_DEEP5 = 4 -DCP_GRPH_DFQ_SIZE_DEEP6 = 5 -DCP_GRPH_DFQ_SIZE_DEEP7 = 6 -DCP_GRPH_DFQ_SIZE_DEEP8 = 7 -DCP_GRPH_DFQ_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES' -DCP_GRPH_DFQ_MIN_FREE_ENTRIES__enumvalues = { - 0: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', - 1: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', - 2: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', - 3: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', - 4: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', - 5: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', - 6: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', - 7: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', -} -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 1 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 2 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 3 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 4 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 5 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 6 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 7 -DCP_GRPH_DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DFQ_RESET_ACK' -DCP_GRPH_DFQ_RESET_ACK__enumvalues = { - 0: 'DCP_GRPH_DFQ_RESET_ACK_FALSE', - 1: 'DCP_GRPH_DFQ_RESET_ACK_TRUE', -} -DCP_GRPH_DFQ_RESET_ACK_FALSE = 0 -DCP_GRPH_DFQ_RESET_ACK_TRUE = 1 -DCP_GRPH_DFQ_RESET_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PFLIP_INT_CLEAR' -DCP_GRPH_PFLIP_INT_CLEAR__enumvalues = { - 0: 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', - 1: 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', -} -DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0 -DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 1 -DCP_GRPH_PFLIP_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PFLIP_INT_MASK' -DCP_GRPH_PFLIP_INT_MASK__enumvalues = { - 0: 'DCP_GRPH_PFLIP_INT_MASK_FALSE', - 1: 'DCP_GRPH_PFLIP_INT_MASK_TRUE', -} -DCP_GRPH_PFLIP_INT_MASK_FALSE = 0 -DCP_GRPH_PFLIP_INT_MASK_TRUE = 1 -DCP_GRPH_PFLIP_INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PFLIP_INT_TYPE' -DCP_GRPH_PFLIP_INT_TYPE__enumvalues = { - 0: 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', - 1: 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', -} -DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0 -DCP_GRPH_PFLIP_INT_TYPE_PULSE = 1 -DCP_GRPH_PFLIP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRESCALE_SELECT' -DCP_GRPH_PRESCALE_SELECT__enumvalues = { - 0: 'DCP_GRPH_PRESCALE_SELECT_FIXED', - 1: 'DCP_GRPH_PRESCALE_SELECT_FLOATING', -} -DCP_GRPH_PRESCALE_SELECT_FIXED = 0 -DCP_GRPH_PRESCALE_SELECT_FLOATING = 1 -DCP_GRPH_PRESCALE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRESCALE_R_SIGN' -DCP_GRPH_PRESCALE_R_SIGN__enumvalues = { - 0: 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', - 1: 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', -} -DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0 -DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 1 -DCP_GRPH_PRESCALE_R_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRESCALE_G_SIGN' -DCP_GRPH_PRESCALE_G_SIGN__enumvalues = { - 0: 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', - 1: 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', -} -DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0 -DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 1 -DCP_GRPH_PRESCALE_G_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRESCALE_B_SIGN' -DCP_GRPH_PRESCALE_B_SIGN__enumvalues = { - 0: 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', - 1: 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', -} -DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0 -DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 1 -DCP_GRPH_PRESCALE_B_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_PRESCALE_BYPASS' -DCP_GRPH_PRESCALE_BYPASS__enumvalues = { - 0: 'DCP_GRPH_PRESCALE_BYPASS_FALSE', - 1: 'DCP_GRPH_PRESCALE_BYPASS_TRUE', -} -DCP_GRPH_PRESCALE_BYPASS_FALSE = 0 -DCP_GRPH_PRESCALE_BYPASS_TRUE = 1 -DCP_GRPH_PRESCALE_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_INPUT_CSC_GRPH_MODE' -DCP_INPUT_CSC_GRPH_MODE__enumvalues = { - 0: 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', - 1: 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', - 2: 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', - 3: 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', -} -DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0 -DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 1 -DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 2 -DCP_INPUT_CSC_GRPH_MODE_RESERVED = 3 -DCP_INPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_OUTPUT_CSC_GRPH_MODE' -DCP_OUTPUT_CSC_GRPH_MODE__enumvalues = { - 0: 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', - 1: 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', - 2: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', - 3: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', - 4: 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', - 5: 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', - 6: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', - 7: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', -} -DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0 -DCP_OUTPUT_CSC_GRPH_MODE_RGB = 1 -DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 2 -DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 3 -DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 4 -DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 5 -DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 6 -DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 7 -DCP_OUTPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DENORM_MODE' -DCP_DENORM_MODE__enumvalues = { - 0: 'DCP_DENORM_MODE_UNITY', - 1: 'DCP_DENORM_MODE_6BIT', - 2: 'DCP_DENORM_MODE_8BIT', - 3: 'DCP_DENORM_MODE_10BIT', - 4: 'DCP_DENORM_MODE_11BIT', - 5: 'DCP_DENORM_MODE_12BIT', - 6: 'DCP_DENORM_MODE_RESERVED0', - 7: 'DCP_DENORM_MODE_RESERVED1', -} -DCP_DENORM_MODE_UNITY = 0 -DCP_DENORM_MODE_6BIT = 1 -DCP_DENORM_MODE_8BIT = 2 -DCP_DENORM_MODE_10BIT = 3 -DCP_DENORM_MODE_11BIT = 4 -DCP_DENORM_MODE_12BIT = 5 -DCP_DENORM_MODE_RESERVED0 = 6 -DCP_DENORM_MODE_RESERVED1 = 7 -DCP_DENORM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DENORM_14BIT_OUT' -DCP_DENORM_14BIT_OUT__enumvalues = { - 0: 'DCP_DENORM_14BIT_OUT_FALSE', - 1: 'DCP_DENORM_14BIT_OUT_TRUE', -} -DCP_DENORM_14BIT_OUT_FALSE = 0 -DCP_DENORM_14BIT_OUT_TRUE = 1 -DCP_DENORM_14BIT_OUT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_OUT_ROUND_TRUNC_MODE' -DCP_OUT_ROUND_TRUNC_MODE__enumvalues = { - 0: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', - 1: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', - 2: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', - 3: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', - 4: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', - 5: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', - 6: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', - 7: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', - 8: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', - 9: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', - 10: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', - 11: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', - 12: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', - 13: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', - 14: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', - 15: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', -} -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 1 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 2 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 3 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 4 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 5 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 6 -DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 7 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 8 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 9 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 10 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 11 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 12 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 13 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 14 -DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 15 -DCP_OUT_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_KEY_MODE' -DCP_KEY_MODE__enumvalues = { - 0: 'DCP_KEY_MODE_ALPHA0', - 1: 'DCP_KEY_MODE_ALPHA1', - 2: 'DCP_KEY_MODE_IN_RANGE_ALPHA1', - 3: 'DCP_KEY_MODE_IN_RANGE_ALPHA0', -} -DCP_KEY_MODE_ALPHA0 = 0 -DCP_KEY_MODE_ALPHA1 = 1 -DCP_KEY_MODE_IN_RANGE_ALPHA1 = 2 -DCP_KEY_MODE_IN_RANGE_ALPHA0 = 3 -DCP_KEY_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_DEGAMMA_MODE' -DCP_GRPH_DEGAMMA_MODE__enumvalues = { - 0: 'DCP_GRPH_DEGAMMA_MODE_BYPASS', - 1: 'DCP_GRPH_DEGAMMA_MODE_ROMA', - 2: 'DCP_GRPH_DEGAMMA_MODE_ROMB', - 3: 'DCP_GRPH_DEGAMMA_MODE_RESERVED', -} -DCP_GRPH_DEGAMMA_MODE_BYPASS = 0 -DCP_GRPH_DEGAMMA_MODE_ROMA = 1 -DCP_GRPH_DEGAMMA_MODE_ROMB = 2 -DCP_GRPH_DEGAMMA_MODE_RESERVED = 3 -DCP_GRPH_DEGAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_DEGAMMA_MODE' -DCP_CURSOR_DEGAMMA_MODE__enumvalues = { - 0: 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', - 1: 'DCP_CURSOR_DEGAMMA_MODE_ROMA', - 2: 'DCP_CURSOR_DEGAMMA_MODE_ROMB', - 3: 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', -} -DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0 -DCP_CURSOR_DEGAMMA_MODE_ROMA = 1 -DCP_CURSOR_DEGAMMA_MODE_ROMB = 2 -DCP_CURSOR_DEGAMMA_MODE_RESERVED = 3 -DCP_CURSOR_DEGAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_GAMUT_REMAP_MODE' -DCP_GRPH_GAMUT_REMAP_MODE__enumvalues = { - 0: 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', - 1: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', - 2: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', - 3: 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', -} -DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0 -DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 1 -DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 2 -DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 3 -DCP_GRPH_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_SPATIAL_DITHER_EN' -DCP_SPATIAL_DITHER_EN__enumvalues = { - 0: 'DCP_SPATIAL_DITHER_EN_FALSE', - 1: 'DCP_SPATIAL_DITHER_EN_TRUE', -} -DCP_SPATIAL_DITHER_EN_FALSE = 0 -DCP_SPATIAL_DITHER_EN_TRUE = 1 -DCP_SPATIAL_DITHER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_SPATIAL_DITHER_MODE' -DCP_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'DCP_SPATIAL_DITHER_MODE_BYPASS', - 1: 'DCP_SPATIAL_DITHER_MODE_ROMA', - 2: 'DCP_SPATIAL_DITHER_MODE_ROMB', - 3: 'DCP_SPATIAL_DITHER_MODE_RESERVED', -} -DCP_SPATIAL_DITHER_MODE_BYPASS = 0 -DCP_SPATIAL_DITHER_MODE_ROMA = 1 -DCP_SPATIAL_DITHER_MODE_ROMB = 2 -DCP_SPATIAL_DITHER_MODE_RESERVED = 3 -DCP_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_SPATIAL_DITHER_DEPTH' -DCP_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'DCP_SPATIAL_DITHER_DEPTH_30BPP', - 1: 'DCP_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'DCP_SPATIAL_DITHER_DEPTH_36BPP', - 3: 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', -} -DCP_SPATIAL_DITHER_DEPTH_30BPP = 0 -DCP_SPATIAL_DITHER_DEPTH_24BPP = 1 -DCP_SPATIAL_DITHER_DEPTH_36BPP = 2 -DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 3 -DCP_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_FRAME_RANDOM_ENABLE' -DCP_FRAME_RANDOM_ENABLE__enumvalues = { - 0: 'DCP_FRAME_RANDOM_ENABLE_FALSE', - 1: 'DCP_FRAME_RANDOM_ENABLE_TRUE', -} -DCP_FRAME_RANDOM_ENABLE_FALSE = 0 -DCP_FRAME_RANDOM_ENABLE_TRUE = 1 -DCP_FRAME_RANDOM_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_RGB_RANDOM_ENABLE' -DCP_RGB_RANDOM_ENABLE__enumvalues = { - 0: 'DCP_RGB_RANDOM_ENABLE_FALSE', - 1: 'DCP_RGB_RANDOM_ENABLE_TRUE', -} -DCP_RGB_RANDOM_ENABLE_FALSE = 0 -DCP_RGB_RANDOM_ENABLE_TRUE = 1 -DCP_RGB_RANDOM_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_HIGHPASS_RANDOM_ENABLE' -DCP_HIGHPASS_RANDOM_ENABLE__enumvalues = { - 0: 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', - 1: 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', -} -DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0 -DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 1 -DCP_HIGHPASS_RANDOM_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_EN' -DCP_CURSOR_EN__enumvalues = { - 0: 'DCP_CURSOR_EN_FALSE', - 1: 'DCP_CURSOR_EN_TRUE', -} -DCP_CURSOR_EN_FALSE = 0 -DCP_CURSOR_EN_TRUE = 1 -DCP_CURSOR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CUR_INV_TRANS_CLAMP' -DCP_CUR_INV_TRANS_CLAMP__enumvalues = { - 0: 'DCP_CUR_INV_TRANS_CLAMP_FALSE', - 1: 'DCP_CUR_INV_TRANS_CLAMP_TRUE', -} -DCP_CUR_INV_TRANS_CLAMP_FALSE = 0 -DCP_CUR_INV_TRANS_CLAMP_TRUE = 1 -DCP_CUR_INV_TRANS_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_MODE' -DCP_CURSOR_MODE__enumvalues = { - 0: 'DCP_CURSOR_MODE_MONO_2BPP', - 1: 'DCP_CURSOR_MODE_24BPP_1BIT', - 2: 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', - 3: 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', -} -DCP_CURSOR_MODE_MONO_2BPP = 0 -DCP_CURSOR_MODE_24BPP_1BIT = 1 -DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 2 -DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 3 -DCP_CURSOR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM' -DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM__enumvalues = { - 0: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', - 1: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', -} -DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0 -DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 1 -DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_2X_MAGNIFY' -DCP_CURSOR_2X_MAGNIFY__enumvalues = { - 0: 'DCP_CURSOR_2X_MAGNIFY_FALSE', - 1: 'DCP_CURSOR_2X_MAGNIFY_TRUE', -} -DCP_CURSOR_2X_MAGNIFY_FALSE = 0 -DCP_CURSOR_2X_MAGNIFY_TRUE = 1 -DCP_CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_FORCE_MC_ON' -DCP_CURSOR_FORCE_MC_ON__enumvalues = { - 0: 'DCP_CURSOR_FORCE_MC_ON_FALSE', - 1: 'DCP_CURSOR_FORCE_MC_ON_TRUE', -} -DCP_CURSOR_FORCE_MC_ON_FALSE = 0 -DCP_CURSOR_FORCE_MC_ON_TRUE = 1 -DCP_CURSOR_FORCE_MC_ON = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_URGENT_CONTROL' -DCP_CURSOR_URGENT_CONTROL__enumvalues = { - 0: 'DCP_CURSOR_URGENT_CONTROL_MODE_0', - 1: 'DCP_CURSOR_URGENT_CONTROL_MODE_1', - 2: 'DCP_CURSOR_URGENT_CONTROL_MODE_2', - 3: 'DCP_CURSOR_URGENT_CONTROL_MODE_3', - 4: 'DCP_CURSOR_URGENT_CONTROL_MODE_4', -} -DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0 -DCP_CURSOR_URGENT_CONTROL_MODE_1 = 1 -DCP_CURSOR_URGENT_CONTROL_MODE_2 = 2 -DCP_CURSOR_URGENT_CONTROL_MODE_3 = 3 -DCP_CURSOR_URGENT_CONTROL_MODE_4 = 4 -DCP_CURSOR_URGENT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_UPDATE_PENDING' -DCP_CURSOR_UPDATE_PENDING__enumvalues = { - 0: 'DCP_CURSOR_UPDATE_PENDING_FALSE', - 1: 'DCP_CURSOR_UPDATE_PENDING_TRUE', -} -DCP_CURSOR_UPDATE_PENDING_FALSE = 0 -DCP_CURSOR_UPDATE_PENDING_TRUE = 1 -DCP_CURSOR_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_UPDATE_TAKEN' -DCP_CURSOR_UPDATE_TAKEN__enumvalues = { - 0: 'DCP_CURSOR_UPDATE_TAKEN_FALSE', - 1: 'DCP_CURSOR_UPDATE_TAKEN_TRUE', -} -DCP_CURSOR_UPDATE_TAKEN_FALSE = 0 -DCP_CURSOR_UPDATE_TAKEN_TRUE = 1 -DCP_CURSOR_UPDATE_TAKEN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_UPDATE_LOCK' -DCP_CURSOR_UPDATE_LOCK__enumvalues = { - 0: 'DCP_CURSOR_UPDATE_LOCK_FALSE', - 1: 'DCP_CURSOR_UPDATE_LOCK_TRUE', -} -DCP_CURSOR_UPDATE_LOCK_FALSE = 0 -DCP_CURSOR_UPDATE_LOCK_TRUE = 1 -DCP_CURSOR_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE' -DCP_CURSOR_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', - 1: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', -} -DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0 -DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 1 -DCP_CURSOR_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_UPDATE_STEREO_MODE' -DCP_CURSOR_UPDATE_STEREO_MODE__enumvalues = { - 0: 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', - 1: 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', - 2: 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', - 3: 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', -} -DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0 -DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 1 -DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 2 -DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 3 -DCP_CURSOR_UPDATE_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CUR2_INV_TRANS_CLAMP' -DCP_CUR2_INV_TRANS_CLAMP__enumvalues = { - 0: 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', - 1: 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', -} -DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0 -DCP_CUR2_INV_TRANS_CLAMP_TRUE = 1 -DCP_CUR2_INV_TRANS_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CUR_REQUEST_FILTER_DIS' -DCP_CUR_REQUEST_FILTER_DIS__enumvalues = { - 0: 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', - 1: 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', -} -DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0 -DCP_CUR_REQUEST_FILTER_DIS_TRUE = 1 -DCP_CUR_REQUEST_FILTER_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_STEREO_EN' -DCP_CURSOR_STEREO_EN__enumvalues = { - 0: 'DCP_CURSOR_STEREO_EN_FALSE', - 1: 'DCP_CURSOR_STEREO_EN_TRUE', -} -DCP_CURSOR_STEREO_EN_FALSE = 0 -DCP_CURSOR_STEREO_EN_TRUE = 1 -DCP_CURSOR_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_STEREO_OFFSET_YNX' -DCP_CURSOR_STEREO_OFFSET_YNX__enumvalues = { - 0: 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', - 1: 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', -} -DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0 -DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 1 -DCP_CURSOR_STEREO_OFFSET_YNX = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_RW_MODE' -DCP_DC_LUT_RW_MODE__enumvalues = { - 0: 'DCP_DC_LUT_RW_MODE_256_ENTRY', - 1: 'DCP_DC_LUT_RW_MODE_PWL', -} -DCP_DC_LUT_RW_MODE_256_ENTRY = 0 -DCP_DC_LUT_RW_MODE_PWL = 1 -DCP_DC_LUT_RW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_VGA_ACCESS_ENABLE' -DCP_DC_LUT_VGA_ACCESS_ENABLE__enumvalues = { - 0: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', - 1: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', -} -DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0 -DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 1 -DCP_DC_LUT_VGA_ACCESS_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_AUTOFILL' -DCP_DC_LUT_AUTOFILL__enumvalues = { - 0: 'DCP_DC_LUT_AUTOFILL_FALSE', - 1: 'DCP_DC_LUT_AUTOFILL_TRUE', -} -DCP_DC_LUT_AUTOFILL_FALSE = 0 -DCP_DC_LUT_AUTOFILL_TRUE = 1 -DCP_DC_LUT_AUTOFILL = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_AUTOFILL_DONE' -DCP_DC_LUT_AUTOFILL_DONE__enumvalues = { - 0: 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', - 1: 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', -} -DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0 -DCP_DC_LUT_AUTOFILL_DONE_TRUE = 1 -DCP_DC_LUT_AUTOFILL_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_INC_B' -DCP_DC_LUT_INC_B__enumvalues = { - 0: 'DCP_DC_LUT_INC_B_NA', - 1: 'DCP_DC_LUT_INC_B_2', - 2: 'DCP_DC_LUT_INC_B_4', - 3: 'DCP_DC_LUT_INC_B_8', - 4: 'DCP_DC_LUT_INC_B_16', - 5: 'DCP_DC_LUT_INC_B_32', - 6: 'DCP_DC_LUT_INC_B_64', - 7: 'DCP_DC_LUT_INC_B_128', - 8: 'DCP_DC_LUT_INC_B_256', - 9: 'DCP_DC_LUT_INC_B_512', -} -DCP_DC_LUT_INC_B_NA = 0 -DCP_DC_LUT_INC_B_2 = 1 -DCP_DC_LUT_INC_B_4 = 2 -DCP_DC_LUT_INC_B_8 = 3 -DCP_DC_LUT_INC_B_16 = 4 -DCP_DC_LUT_INC_B_32 = 5 -DCP_DC_LUT_INC_B_64 = 6 -DCP_DC_LUT_INC_B_128 = 7 -DCP_DC_LUT_INC_B_256 = 8 -DCP_DC_LUT_INC_B_512 = 9 -DCP_DC_LUT_INC_B = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_B_SIGNED_EN' -DCP_DC_LUT_DATA_B_SIGNED_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', -} -DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0 -DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 1 -DCP_DC_LUT_DATA_B_SIGNED_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN' -DCP_DC_LUT_DATA_B_FLOAT_POINT_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', -} -DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0 -DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 1 -DCP_DC_LUT_DATA_B_FLOAT_POINT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_B_FORMAT' -DCP_DC_LUT_DATA_B_FORMAT__enumvalues = { - 0: 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', - 1: 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', - 2: 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', - 3: 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', -} -DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0 -DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 1 -DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 2 -DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 3 -DCP_DC_LUT_DATA_B_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_INC_G' -DCP_DC_LUT_INC_G__enumvalues = { - 0: 'DCP_DC_LUT_INC_G_NA', - 1: 'DCP_DC_LUT_INC_G_2', - 2: 'DCP_DC_LUT_INC_G_4', - 3: 'DCP_DC_LUT_INC_G_8', - 4: 'DCP_DC_LUT_INC_G_16', - 5: 'DCP_DC_LUT_INC_G_32', - 6: 'DCP_DC_LUT_INC_G_64', - 7: 'DCP_DC_LUT_INC_G_128', - 8: 'DCP_DC_LUT_INC_G_256', - 9: 'DCP_DC_LUT_INC_G_512', -} -DCP_DC_LUT_INC_G_NA = 0 -DCP_DC_LUT_INC_G_2 = 1 -DCP_DC_LUT_INC_G_4 = 2 -DCP_DC_LUT_INC_G_8 = 3 -DCP_DC_LUT_INC_G_16 = 4 -DCP_DC_LUT_INC_G_32 = 5 -DCP_DC_LUT_INC_G_64 = 6 -DCP_DC_LUT_INC_G_128 = 7 -DCP_DC_LUT_INC_G_256 = 8 -DCP_DC_LUT_INC_G_512 = 9 -DCP_DC_LUT_INC_G = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_G_SIGNED_EN' -DCP_DC_LUT_DATA_G_SIGNED_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', -} -DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0 -DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 1 -DCP_DC_LUT_DATA_G_SIGNED_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN' -DCP_DC_LUT_DATA_G_FLOAT_POINT_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', -} -DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0 -DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 1 -DCP_DC_LUT_DATA_G_FLOAT_POINT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_G_FORMAT' -DCP_DC_LUT_DATA_G_FORMAT__enumvalues = { - 0: 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', - 1: 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', - 2: 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', - 3: 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', -} -DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0 -DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 1 -DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 2 -DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 3 -DCP_DC_LUT_DATA_G_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_INC_R' -DCP_DC_LUT_INC_R__enumvalues = { - 0: 'DCP_DC_LUT_INC_R_NA', - 1: 'DCP_DC_LUT_INC_R_2', - 2: 'DCP_DC_LUT_INC_R_4', - 3: 'DCP_DC_LUT_INC_R_8', - 4: 'DCP_DC_LUT_INC_R_16', - 5: 'DCP_DC_LUT_INC_R_32', - 6: 'DCP_DC_LUT_INC_R_64', - 7: 'DCP_DC_LUT_INC_R_128', - 8: 'DCP_DC_LUT_INC_R_256', - 9: 'DCP_DC_LUT_INC_R_512', -} -DCP_DC_LUT_INC_R_NA = 0 -DCP_DC_LUT_INC_R_2 = 1 -DCP_DC_LUT_INC_R_4 = 2 -DCP_DC_LUT_INC_R_8 = 3 -DCP_DC_LUT_INC_R_16 = 4 -DCP_DC_LUT_INC_R_32 = 5 -DCP_DC_LUT_INC_R_64 = 6 -DCP_DC_LUT_INC_R_128 = 7 -DCP_DC_LUT_INC_R_256 = 8 -DCP_DC_LUT_INC_R_512 = 9 -DCP_DC_LUT_INC_R = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_R_SIGNED_EN' -DCP_DC_LUT_DATA_R_SIGNED_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', -} -DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0 -DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 1 -DCP_DC_LUT_DATA_R_SIGNED_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN' -DCP_DC_LUT_DATA_R_FLOAT_POINT_EN__enumvalues = { - 0: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', - 1: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', -} -DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0 -DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 1 -DCP_DC_LUT_DATA_R_FLOAT_POINT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_DC_LUT_DATA_R_FORMAT' -DCP_DC_LUT_DATA_R_FORMAT__enumvalues = { - 0: 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', - 1: 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', - 2: 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', - 3: 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', -} -DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0 -DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 1 -DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 2 -DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 3 -DCP_DC_LUT_DATA_R_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CRC_ENABLE' -DCP_CRC_ENABLE__enumvalues = { - 0: 'DCP_CRC_ENABLE_FALSE', - 1: 'DCP_CRC_ENABLE_TRUE', -} -DCP_CRC_ENABLE_FALSE = 0 -DCP_CRC_ENABLE_TRUE = 1 -DCP_CRC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CRC_SOURCE_SEL' -DCP_CRC_SOURCE_SEL__enumvalues = { - 0: 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', - 1: 'DCP_CRC_SOURCE_SEL_INPUT_L32', - 2: 'DCP_CRC_SOURCE_SEL_INPUT_H32', - 4: 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', -} -DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0 -DCP_CRC_SOURCE_SEL_INPUT_L32 = 1 -DCP_CRC_SOURCE_SEL_INPUT_H32 = 2 -DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 4 -DCP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CRC_LINE_SEL' -DCP_CRC_LINE_SEL__enumvalues = { - 0: 'DCP_CRC_LINE_SEL_RESERVED', - 1: 'DCP_CRC_LINE_SEL_EVEN', - 2: 'DCP_CRC_LINE_SEL_ODD', - 3: 'DCP_CRC_LINE_SEL_BOTH', -} -DCP_CRC_LINE_SEL_RESERVED = 0 -DCP_CRC_LINE_SEL_EVEN = 1 -DCP_CRC_LINE_SEL_ODD = 2 -DCP_CRC_LINE_SEL_BOTH = 3 -DCP_CRC_LINE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_FLIP_RATE' -DCP_GRPH_FLIP_RATE__enumvalues = { - 0: 'DCP_GRPH_FLIP_RATE_1FRAME', - 1: 'DCP_GRPH_FLIP_RATE_2FRAME', - 2: 'DCP_GRPH_FLIP_RATE_3FRAME', - 3: 'DCP_GRPH_FLIP_RATE_4FRAME', - 4: 'DCP_GRPH_FLIP_RATE_5FRAME', - 5: 'DCP_GRPH_FLIP_RATE_6FRAME', - 6: 'DCP_GRPH_FLIP_RATE_7FRAME', - 7: 'DCP_GRPH_FLIP_RATE_8FRAME', -} -DCP_GRPH_FLIP_RATE_1FRAME = 0 -DCP_GRPH_FLIP_RATE_2FRAME = 1 -DCP_GRPH_FLIP_RATE_3FRAME = 2 -DCP_GRPH_FLIP_RATE_4FRAME = 3 -DCP_GRPH_FLIP_RATE_5FRAME = 4 -DCP_GRPH_FLIP_RATE_6FRAME = 5 -DCP_GRPH_FLIP_RATE_7FRAME = 6 -DCP_GRPH_FLIP_RATE_8FRAME = 7 -DCP_GRPH_FLIP_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_FLIP_RATE_ENABLE' -DCP_GRPH_FLIP_RATE_ENABLE__enumvalues = { - 0: 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', - 1: 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', -} -DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0 -DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 1 -DCP_GRPH_FLIP_RATE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL0_EN' -DCP_GSL0_EN__enumvalues = { - 0: 'DCP_GSL0_EN_FALSE', - 1: 'DCP_GSL0_EN_TRUE', -} -DCP_GSL0_EN_FALSE = 0 -DCP_GSL0_EN_TRUE = 1 -DCP_GSL0_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL1_EN' -DCP_GSL1_EN__enumvalues = { - 0: 'DCP_GSL1_EN_FALSE', - 1: 'DCP_GSL1_EN_TRUE', -} -DCP_GSL1_EN_FALSE = 0 -DCP_GSL1_EN_TRUE = 1 -DCP_GSL1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL2_EN' -DCP_GSL2_EN__enumvalues = { - 0: 'DCP_GSL2_EN_FALSE', - 1: 'DCP_GSL2_EN_TRUE', -} -DCP_GSL2_EN_FALSE = 0 -DCP_GSL2_EN_TRUE = 1 -DCP_GSL2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_MASTER_EN' -DCP_GSL_MASTER_EN__enumvalues = { - 0: 'DCP_GSL_MASTER_EN_FALSE', - 1: 'DCP_GSL_MASTER_EN_TRUE', -} -DCP_GSL_MASTER_EN_FALSE = 0 -DCP_GSL_MASTER_EN_TRUE = 1 -DCP_GSL_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_XDMA_GROUP' -DCP_GSL_XDMA_GROUP__enumvalues = { - 0: 'DCP_GSL_XDMA_GROUP_VSYNC', - 1: 'DCP_GSL_XDMA_GROUP_HSYNC0', - 2: 'DCP_GSL_XDMA_GROUP_HSYNC1', - 3: 'DCP_GSL_XDMA_GROUP_HSYNC2', -} -DCP_GSL_XDMA_GROUP_VSYNC = 0 -DCP_GSL_XDMA_GROUP_HSYNC0 = 1 -DCP_GSL_XDMA_GROUP_HSYNC1 = 2 -DCP_GSL_XDMA_GROUP_HSYNC2 = 3 -DCP_GSL_XDMA_GROUP = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN' -DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__enumvalues = { - 0: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', - 1: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', -} -DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0 -DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 1 -DCP_GSL_XDMA_GROUP_UNDERFLOW_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_SYNC_SOURCE' -DCP_GSL_SYNC_SOURCE__enumvalues = { - 0: 'DCP_GSL_SYNC_SOURCE_FLIP', - 1: 'DCP_GSL_SYNC_SOURCE_PHASE0', - 2: 'DCP_GSL_SYNC_SOURCE_RESET', - 3: 'DCP_GSL_SYNC_SOURCE_PHASE1', -} -DCP_GSL_SYNC_SOURCE_FLIP = 0 -DCP_GSL_SYNC_SOURCE_PHASE0 = 1 -DCP_GSL_SYNC_SOURCE_RESET = 2 -DCP_GSL_SYNC_SOURCE_PHASE1 = 3 -DCP_GSL_SYNC_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC' -DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__enumvalues = { - 0: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', - 1: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', -} -DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0 -DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 1 -DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING' -DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__enumvalues = { - 0: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', - 1: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', -} -DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0 -DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 1 -DCP_GSL_DELAY_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_TEST_DEBUG_WRITE_EN' -DCP_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'DCP_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'DCP_TEST_DEBUG_WRITE_EN_TRUE', -} -DCP_TEST_DEBUG_WRITE_EN_FALSE = 0 -DCP_TEST_DEBUG_WRITE_EN_TRUE = 1 -DCP_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_EN' -DCP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { - 0: 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', - 1: 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', -} -DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0 -DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 1 -DCP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_MODE' -DCP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { - 0: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', - 1: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', - 2: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', - 3: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', -} -DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0 -DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 1 -DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 2 -DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 3 -DCP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE' -DCP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { - 0: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', - 1: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', -} -DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0 -DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 1 -DCP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_ROTATION_ANGLE' -DCP_GRPH_ROTATION_ANGLE__enumvalues = { - 0: 'DCP_GRPH_ROTATION_ANGLE_0', - 1: 'DCP_GRPH_ROTATION_ANGLE_90', - 2: 'DCP_GRPH_ROTATION_ANGLE_180', - 3: 'DCP_GRPH_ROTATION_ANGLE_270', -} -DCP_GRPH_ROTATION_ANGLE_0 = 0 -DCP_GRPH_ROTATION_ANGLE_90 = 1 -DCP_GRPH_ROTATION_ANGLE_180 = 2 -DCP_GRPH_ROTATION_ANGLE_270 = 3 -DCP_GRPH_ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_REGAMMA_MODE' -DCP_GRPH_REGAMMA_MODE__enumvalues = { - 0: 'DCP_GRPH_REGAMMA_MODE_BYPASS', - 1: 'DCP_GRPH_REGAMMA_MODE_SRGB', - 2: 'DCP_GRPH_REGAMMA_MODE_XVYCC', - 3: 'DCP_GRPH_REGAMMA_MODE_PROGA', - 4: 'DCP_GRPH_REGAMMA_MODE_PROGB', -} -DCP_GRPH_REGAMMA_MODE_BYPASS = 0 -DCP_GRPH_REGAMMA_MODE_SRGB = 1 -DCP_GRPH_REGAMMA_MODE_XVYCC = 2 -DCP_GRPH_REGAMMA_MODE_PROGA = 3 -DCP_GRPH_REGAMMA_MODE_PROGB = 4 -DCP_GRPH_REGAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_ALPHA_ROUND_TRUNC_MODE' -DCP_ALPHA_ROUND_TRUNC_MODE__enumvalues = { - 0: 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', - 1: 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', -} -DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0 -DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 1 -DCP_ALPHA_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_CURSOR_ALPHA_BLND_ENA' -DCP_CURSOR_ALPHA_BLND_ENA__enumvalues = { - 0: 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', - 1: 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', -} -DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0 -DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 1 -DCP_CURSOR_ALPHA_BLND_ENA = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK' -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__enumvalues = { - 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', - 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', -} -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 1 -DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EN' -DCP_GRPH_SURFACE_COUNTER_EN__enumvalues = { - 0: 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', - 1: 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', -} -DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0 -DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 1 -DCP_GRPH_SURFACE_COUNTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT' -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT__enumvalues = { - 0: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', - 1: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', - 2: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', - 3: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', - 4: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', - 5: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', - 6: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', - 7: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', - 8: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', - 9: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', - 10: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', - 11: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', -} -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 1 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 2 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 3 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 4 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 5 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 6 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 7 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 8 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 9 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 10 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 11 -DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED' -DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__enumvalues = { - 0: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', - 1: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', -} -DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0 -DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 1 -DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR' -DCP_GRPH_XDMA_FLIP_TYPE_CLEAR__enumvalues = { - 0: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', - 1: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', -} -DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0 -DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 1 -DCP_GRPH_XDMA_FLIP_TYPE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_DRR_MODE_ENABLE' -DCP_GRPH_XDMA_DRR_MODE_ENABLE__enumvalues = { - 0: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', - 1: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', -} -DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0 -DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 1 -DCP_GRPH_XDMA_DRR_MODE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE' -DCP_GRPH_XDMA_MULTIFLIP_ENABLE__enumvalues = { - 0: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', - 1: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', -} -DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0 -DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 1 -DCP_GRPH_XDMA_MULTIFLIP_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK' -DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK__enumvalues = { - 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', - 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', -} -DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0 -DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 1 -DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK' -DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK__enumvalues = { - 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', - 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', -} -DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0 -DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 1 -DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CVALUE_SEL' -PERFCOUNTER_CVALUE_SEL__enumvalues = { - 0: 'PERFCOUNTER_CVALUE_SEL_47_0', - 1: 'PERFCOUNTER_CVALUE_SEL_15_0', - 2: 'PERFCOUNTER_CVALUE_SEL_31_16', - 3: 'PERFCOUNTER_CVALUE_SEL_47_32', - 4: 'PERFCOUNTER_CVALUE_SEL_11_0', - 5: 'PERFCOUNTER_CVALUE_SEL_23_12', - 6: 'PERFCOUNTER_CVALUE_SEL_35_24', - 7: 'PERFCOUNTER_CVALUE_SEL_47_36', -} -PERFCOUNTER_CVALUE_SEL_47_0 = 0 -PERFCOUNTER_CVALUE_SEL_15_0 = 1 -PERFCOUNTER_CVALUE_SEL_31_16 = 2 -PERFCOUNTER_CVALUE_SEL_47_32 = 3 -PERFCOUNTER_CVALUE_SEL_11_0 = 4 -PERFCOUNTER_CVALUE_SEL_23_12 = 5 -PERFCOUNTER_CVALUE_SEL_35_24 = 6 -PERFCOUNTER_CVALUE_SEL_47_36 = 7 -PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INC_MODE' -PERFCOUNTER_INC_MODE__enumvalues = { - 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', - 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', - 2: 'PERFCOUNTER_INC_MODE_LSB', - 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', - 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', -} -PERFCOUNTER_INC_MODE_MULTI_BIT = 0 -PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 -PERFCOUNTER_INC_MODE_LSB = 2 -PERFCOUNTER_INC_MODE_POS_EDGE = 3 -PERFCOUNTER_INC_MODE_NEG_EDGE = 4 -PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' -PERFCOUNTER_HW_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', - 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', -} -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 -PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RUNEN_MODE' -PERFCOUNTER_RUNEN_MODE__enumvalues = { - 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', -} -PERFCOUNTER_RUNEN_MODE_LEVEL = 0 -PERFCOUNTER_RUNEN_MODE_EDGE = 1 -PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' -PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { - 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', - 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', -} -PERFCOUNTER_CNTOFF_START_ENABLE = 0 -PERFCOUNTER_CNTOFF_START_DISABLE = 1 -PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RESTART_EN' -PERFCOUNTER_RESTART_EN__enumvalues = { - 0: 'PERFCOUNTER_RESTART_DISABLE', - 1: 'PERFCOUNTER_RESTART_ENABLE', -} -PERFCOUNTER_RESTART_DISABLE = 0 -PERFCOUNTER_RESTART_ENABLE = 1 -PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_EN' -PERFCOUNTER_INT_EN__enumvalues = { - 0: 'PERFCOUNTER_INT_DISABLE', - 1: 'PERFCOUNTER_INT_ENABLE', -} -PERFCOUNTER_INT_DISABLE = 0 -PERFCOUNTER_INT_ENABLE = 1 -PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_OFF_MASK' -PERFCOUNTER_OFF_MASK__enumvalues = { - 0: 'PERFCOUNTER_OFF_MASK_DISABLE', - 1: 'PERFCOUNTER_OFF_MASK_ENABLE', -} -PERFCOUNTER_OFF_MASK_DISABLE = 0 -PERFCOUNTER_OFF_MASK_ENABLE = 1 -PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_ACTIVE' -PERFCOUNTER_ACTIVE__enumvalues = { - 0: 'PERFCOUNTER_IS_IDLE', - 1: 'PERFCOUNTER_IS_ACTIVE', -} -PERFCOUNTER_IS_IDLE = 0 -PERFCOUNTER_IS_ACTIVE = 1 -PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_TYPE' -PERFCOUNTER_INT_TYPE__enumvalues = { - 0: 'PERFCOUNTER_INT_TYPE_LEVEL', - 1: 'PERFCOUNTER_INT_TYPE_PULSE', -} -PERFCOUNTER_INT_TYPE_LEVEL = 0 -PERFCOUNTER_INT_TYPE_PULSE = 1 -PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' -PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { - 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', -} -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 -PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTL_SEL' -PERFCOUNTER_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_CNTL_SEL_0', - 1: 'PERFCOUNTER_CNTL_SEL_1', - 2: 'PERFCOUNTER_CNTL_SEL_2', - 3: 'PERFCOUNTER_CNTL_SEL_3', - 4: 'PERFCOUNTER_CNTL_SEL_4', - 5: 'PERFCOUNTER_CNTL_SEL_5', - 6: 'PERFCOUNTER_CNTL_SEL_6', - 7: 'PERFCOUNTER_CNTL_SEL_7', -} -PERFCOUNTER_CNTL_SEL_0 = 0 -PERFCOUNTER_CNTL_SEL_1 = 1 -PERFCOUNTER_CNTL_SEL_2 = 2 -PERFCOUNTER_CNTL_SEL_3 = 3 -PERFCOUNTER_CNTL_SEL_4 = 4 -PERFCOUNTER_CNTL_SEL_5 = 5 -PERFCOUNTER_CNTL_SEL_6 = 6 -PERFCOUNTER_CNTL_SEL_7 = 7 -PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT0_STATE' -PERFCOUNTER_CNT0_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT0_STATE_RESET', - 1: 'PERFCOUNTER_CNT0_STATE_START', - 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT0_STATE_HW', -} -PERFCOUNTER_CNT0_STATE_RESET = 0 -PERFCOUNTER_CNT0_STATE_START = 1 -PERFCOUNTER_CNT0_STATE_FREEZE = 2 -PERFCOUNTER_CNT0_STATE_HW = 3 -PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL0' -PERFCOUNTER_STATE_SEL0__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', -} -PERFCOUNTER_STATE_SEL0_GLOBAL = 0 -PERFCOUNTER_STATE_SEL0_LOCAL = 1 -PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT1_STATE' -PERFCOUNTER_CNT1_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT1_STATE_RESET', - 1: 'PERFCOUNTER_CNT1_STATE_START', - 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT1_STATE_HW', -} -PERFCOUNTER_CNT1_STATE_RESET = 0 -PERFCOUNTER_CNT1_STATE_START = 1 -PERFCOUNTER_CNT1_STATE_FREEZE = 2 -PERFCOUNTER_CNT1_STATE_HW = 3 -PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL1' -PERFCOUNTER_STATE_SEL1__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', -} -PERFCOUNTER_STATE_SEL1_GLOBAL = 0 -PERFCOUNTER_STATE_SEL1_LOCAL = 1 -PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT2_STATE' -PERFCOUNTER_CNT2_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT2_STATE_RESET', - 1: 'PERFCOUNTER_CNT2_STATE_START', - 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT2_STATE_HW', -} -PERFCOUNTER_CNT2_STATE_RESET = 0 -PERFCOUNTER_CNT2_STATE_START = 1 -PERFCOUNTER_CNT2_STATE_FREEZE = 2 -PERFCOUNTER_CNT2_STATE_HW = 3 -PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL2' -PERFCOUNTER_STATE_SEL2__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', -} -PERFCOUNTER_STATE_SEL2_GLOBAL = 0 -PERFCOUNTER_STATE_SEL2_LOCAL = 1 -PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT3_STATE' -PERFCOUNTER_CNT3_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT3_STATE_RESET', - 1: 'PERFCOUNTER_CNT3_STATE_START', - 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT3_STATE_HW', -} -PERFCOUNTER_CNT3_STATE_RESET = 0 -PERFCOUNTER_CNT3_STATE_START = 1 -PERFCOUNTER_CNT3_STATE_FREEZE = 2 -PERFCOUNTER_CNT3_STATE_HW = 3 -PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL3' -PERFCOUNTER_STATE_SEL3__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', -} -PERFCOUNTER_STATE_SEL3_GLOBAL = 0 -PERFCOUNTER_STATE_SEL3_LOCAL = 1 -PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT4_STATE' -PERFCOUNTER_CNT4_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT4_STATE_RESET', - 1: 'PERFCOUNTER_CNT4_STATE_START', - 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT4_STATE_HW', -} -PERFCOUNTER_CNT4_STATE_RESET = 0 -PERFCOUNTER_CNT4_STATE_START = 1 -PERFCOUNTER_CNT4_STATE_FREEZE = 2 -PERFCOUNTER_CNT4_STATE_HW = 3 -PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL4' -PERFCOUNTER_STATE_SEL4__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', -} -PERFCOUNTER_STATE_SEL4_GLOBAL = 0 -PERFCOUNTER_STATE_SEL4_LOCAL = 1 -PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT5_STATE' -PERFCOUNTER_CNT5_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT5_STATE_RESET', - 1: 'PERFCOUNTER_CNT5_STATE_START', - 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT5_STATE_HW', -} -PERFCOUNTER_CNT5_STATE_RESET = 0 -PERFCOUNTER_CNT5_STATE_START = 1 -PERFCOUNTER_CNT5_STATE_FREEZE = 2 -PERFCOUNTER_CNT5_STATE_HW = 3 -PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL5' -PERFCOUNTER_STATE_SEL5__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', -} -PERFCOUNTER_STATE_SEL5_GLOBAL = 0 -PERFCOUNTER_STATE_SEL5_LOCAL = 1 -PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT6_STATE' -PERFCOUNTER_CNT6_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT6_STATE_RESET', - 1: 'PERFCOUNTER_CNT6_STATE_START', - 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT6_STATE_HW', -} -PERFCOUNTER_CNT6_STATE_RESET = 0 -PERFCOUNTER_CNT6_STATE_START = 1 -PERFCOUNTER_CNT6_STATE_FREEZE = 2 -PERFCOUNTER_CNT6_STATE_HW = 3 -PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL6' -PERFCOUNTER_STATE_SEL6__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', -} -PERFCOUNTER_STATE_SEL6_GLOBAL = 0 -PERFCOUNTER_STATE_SEL6_LOCAL = 1 -PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT7_STATE' -PERFCOUNTER_CNT7_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT7_STATE_RESET', - 1: 'PERFCOUNTER_CNT7_STATE_START', - 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT7_STATE_HW', -} -PERFCOUNTER_CNT7_STATE_RESET = 0 -PERFCOUNTER_CNT7_STATE_START = 1 -PERFCOUNTER_CNT7_STATE_FREEZE = 2 -PERFCOUNTER_CNT7_STATE_HW = 3 -PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL7' -PERFCOUNTER_STATE_SEL7__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', -} -PERFCOUNTER_STATE_SEL7_GLOBAL = 0 -PERFCOUNTER_STATE_SEL7_LOCAL = 1 -PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_STATE' -PERFMON_STATE__enumvalues = { - 0: 'PERFMON_STATE_RESET', - 1: 'PERFMON_STATE_START', - 2: 'PERFMON_STATE_FREEZE', - 3: 'PERFMON_STATE_HW', -} -PERFMON_STATE_RESET = 0 -PERFMON_STATE_START = 1 -PERFMON_STATE_FREEZE = 2 -PERFMON_STATE_HW = 3 -PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_AND_OR' -PERFMON_CNTOFF_AND_OR__enumvalues = { - 0: 'PERFMON_CNTOFF_OR', - 1: 'PERFMON_CNTOFF_AND', -} -PERFMON_CNTOFF_OR = 0 -PERFMON_CNTOFF_AND = 1 -PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_EN' -PERFMON_CNTOFF_INT_EN__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_DISABLE', - 1: 'PERFMON_CNTOFF_INT_ENABLE', -} -PERFMON_CNTOFF_INT_DISABLE = 0 -PERFMON_CNTOFF_INT_ENABLE = 1 -PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' -PERFMON_CNTOFF_INT_TYPE__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', - 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', -} -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 -PERFMON_CNTOFF_INT_TYPE_PULSE = 1 -PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_C_RAM_TAP_PAIR_IDX' -SCL_C_RAM_TAP_PAIR_IDX__enumvalues = { - 0: 'SCL_C_RAM_TAP_PAIR_ID0', - 1: 'SCL_C_RAM_TAP_PAIR_ID1', - 2: 'SCL_C_RAM_TAP_PAIR_ID2', - 3: 'SCL_C_RAM_TAP_PAIR_ID3', - 4: 'SCL_C_RAM_TAP_PAIR_ID4', -} -SCL_C_RAM_TAP_PAIR_ID0 = 0 -SCL_C_RAM_TAP_PAIR_ID1 = 1 -SCL_C_RAM_TAP_PAIR_ID2 = 2 -SCL_C_RAM_TAP_PAIR_ID3 = 3 -SCL_C_RAM_TAP_PAIR_ID4 = 4 -SCL_C_RAM_TAP_PAIR_IDX = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_C_RAM_PHASE' -SCL_C_RAM_PHASE__enumvalues = { - 0: 'SCL_C_RAM_PHASE_0', - 1: 'SCL_C_RAM_PHASE_1', - 2: 'SCL_C_RAM_PHASE_2', - 3: 'SCL_C_RAM_PHASE_3', - 4: 'SCL_C_RAM_PHASE_4', - 5: 'SCL_C_RAM_PHASE_5', - 6: 'SCL_C_RAM_PHASE_6', - 7: 'SCL_C_RAM_PHASE_7', - 8: 'SCL_C_RAM_PHASE_8', -} -SCL_C_RAM_PHASE_0 = 0 -SCL_C_RAM_PHASE_1 = 1 -SCL_C_RAM_PHASE_2 = 2 -SCL_C_RAM_PHASE_3 = 3 -SCL_C_RAM_PHASE_4 = 4 -SCL_C_RAM_PHASE_5 = 5 -SCL_C_RAM_PHASE_6 = 6 -SCL_C_RAM_PHASE_7 = 7 -SCL_C_RAM_PHASE_8 = 8 -SCL_C_RAM_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_C_RAM_FILTER_TYPE' -SCL_C_RAM_FILTER_TYPE__enumvalues = { - 0: 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', - 1: 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', - 2: 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', - 3: 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', -} -SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0 -SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 1 -SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 2 -SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 3 -SCL_C_RAM_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_MODE_SEL' -SCL_MODE_SEL__enumvalues = { - 0: 'SCL_MODE_RGB_BYPASS', - 1: 'SCL_MODE_RGB_SCALING', - 2: 'SCL_MODE_YCBCR_SCALING', - 3: 'SCL_MODE_YCBCR_BYPASS', -} -SCL_MODE_RGB_BYPASS = 0 -SCL_MODE_RGB_SCALING = 1 -SCL_MODE_YCBCR_SCALING = 2 -SCL_MODE_YCBCR_BYPASS = 3 -SCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_PSCL_EN' -SCL_PSCL_EN__enumvalues = { - 0: 'SCL_PSCL_DISABLE', - 1: 'SCL_PSCL_ENANBLE', -} -SCL_PSCL_DISABLE = 0 -SCL_PSCL_ENANBLE = 1 -SCL_PSCL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_V_NUM_OF_TAPS' -SCL_V_NUM_OF_TAPS__enumvalues = { - 0: 'SCL_V_NUM_OF_TAPS_1', - 1: 'SCL_V_NUM_OF_TAPS_2', - 2: 'SCL_V_NUM_OF_TAPS_3', - 3: 'SCL_V_NUM_OF_TAPS_4', - 4: 'SCL_V_NUM_OF_TAPS_5', - 5: 'SCL_V_NUM_OF_TAPS_6', -} -SCL_V_NUM_OF_TAPS_1 = 0 -SCL_V_NUM_OF_TAPS_2 = 1 -SCL_V_NUM_OF_TAPS_3 = 2 -SCL_V_NUM_OF_TAPS_4 = 3 -SCL_V_NUM_OF_TAPS_5 = 4 -SCL_V_NUM_OF_TAPS_6 = 5 -SCL_V_NUM_OF_TAPS = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_H_NUM_OF_TAPS' -SCL_H_NUM_OF_TAPS__enumvalues = { - 0: 'SCL_H_NUM_OF_TAPS_1', - 1: 'SCL_H_NUM_OF_TAPS_2', - 3: 'SCL_H_NUM_OF_TAPS_4', - 5: 'SCL_H_NUM_OF_TAPS_6', - 7: 'SCL_H_NUM_OF_TAPS_8', - 9: 'SCL_H_NUM_OF_TAPS_10', -} -SCL_H_NUM_OF_TAPS_1 = 0 -SCL_H_NUM_OF_TAPS_2 = 1 -SCL_H_NUM_OF_TAPS_4 = 3 -SCL_H_NUM_OF_TAPS_6 = 5 -SCL_H_NUM_OF_TAPS_8 = 7 -SCL_H_NUM_OF_TAPS_10 = 9 -SCL_H_NUM_OF_TAPS = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BOUNDARY_MODE' -SCL_BOUNDARY_MODE__enumvalues = { - 0: 'SCL_BOUNDARY_MODE_BLACK', - 1: 'SCL_BOUNDARY_MODE_EDGE', -} -SCL_BOUNDARY_MODE_BLACK = 0 -SCL_BOUNDARY_MODE_EDGE = 1 -SCL_BOUNDARY_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_EARLY_EOL_MOD' -SCL_EARLY_EOL_MOD__enumvalues = { - 0: 'SCL_EARLY_EOL_MODE_CRTC', - 1: 'SCL_EARLY_EOL_MODE_INTERNAL', -} -SCL_EARLY_EOL_MODE_CRTC = 0 -SCL_EARLY_EOL_MODE_INTERNAL = 1 -SCL_EARLY_EOL_MOD = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BYPASS_MODE' -SCL_BYPASS_MODE__enumvalues = { - 0: 'SCL_BYPASS_MODE_MC_MR', - 1: 'SCL_BYPASS_MODE_AC_NR', - 2: 'SCL_BYPASS_MODE_AC_AR', - 3: 'SCL_BYPASS_MODE_RESERVED', -} -SCL_BYPASS_MODE_MC_MR = 0 -SCL_BYPASS_MODE_AC_NR = 1 -SCL_BYPASS_MODE_AC_AR = 2 -SCL_BYPASS_MODE_RESERVED = 3 -SCL_BYPASS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_V_MANUAL_REPLICATE_FACTOR' -SCL_V_MANUAL_REPLICATE_FACTOR__enumvalues = { - 0: 'SCL_V_MANUAL_REPLICATE_FACTOR_1', - 1: 'SCL_V_MANUAL_REPLICATE_FACTOR_2', - 2: 'SCL_V_MANUAL_REPLICATE_FACTOR_3', - 3: 'SCL_V_MANUAL_REPLICATE_FACTOR_4', - 4: 'SCL_V_MANUAL_REPLICATE_FACTOR_5', - 5: 'SCL_V_MANUAL_REPLICATE_FACTOR_6', - 6: 'SCL_V_MANUAL_REPLICATE_FACTOR_7', - 7: 'SCL_V_MANUAL_REPLICATE_FACTOR_8', - 8: 'SCL_V_MANUAL_REPLICATE_FACTOR_9', - 9: 'SCL_V_MANUAL_REPLICATE_FACTOR_10', - 10: 'SCL_V_MANUAL_REPLICATE_FACTOR_11', - 11: 'SCL_V_MANUAL_REPLICATE_FACTOR_12', - 12: 'SCL_V_MANUAL_REPLICATE_FACTOR_13', - 13: 'SCL_V_MANUAL_REPLICATE_FACTOR_14', - 14: 'SCL_V_MANUAL_REPLICATE_FACTOR_15', - 15: 'SCL_V_MANUAL_REPLICATE_FACTOR_16', -} -SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0 -SCL_V_MANUAL_REPLICATE_FACTOR_2 = 1 -SCL_V_MANUAL_REPLICATE_FACTOR_3 = 2 -SCL_V_MANUAL_REPLICATE_FACTOR_4 = 3 -SCL_V_MANUAL_REPLICATE_FACTOR_5 = 4 -SCL_V_MANUAL_REPLICATE_FACTOR_6 = 5 -SCL_V_MANUAL_REPLICATE_FACTOR_7 = 6 -SCL_V_MANUAL_REPLICATE_FACTOR_8 = 7 -SCL_V_MANUAL_REPLICATE_FACTOR_9 = 8 -SCL_V_MANUAL_REPLICATE_FACTOR_10 = 9 -SCL_V_MANUAL_REPLICATE_FACTOR_11 = 10 -SCL_V_MANUAL_REPLICATE_FACTOR_12 = 11 -SCL_V_MANUAL_REPLICATE_FACTOR_13 = 12 -SCL_V_MANUAL_REPLICATE_FACTOR_14 = 13 -SCL_V_MANUAL_REPLICATE_FACTOR_15 = 14 -SCL_V_MANUAL_REPLICATE_FACTOR_16 = 15 -SCL_V_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_H_MANUAL_REPLICATE_FACTOR' -SCL_H_MANUAL_REPLICATE_FACTOR__enumvalues = { - 0: 'SCL_H_MANUAL_REPLICATE_FACTOR_1', - 1: 'SCL_H_MANUAL_REPLICATE_FACTOR_2', - 2: 'SCL_H_MANUAL_REPLICATE_FACTOR_3', - 3: 'SCL_H_MANUAL_REPLICATE_FACTOR_4', - 4: 'SCL_H_MANUAL_REPLICATE_FACTOR_5', - 5: 'SCL_H_MANUAL_REPLICATE_FACTOR_6', - 6: 'SCL_H_MANUAL_REPLICATE_FACTOR_7', - 7: 'SCL_H_MANUAL_REPLICATE_FACTOR_8', - 8: 'SCL_H_MANUAL_REPLICATE_FACTOR_9', - 9: 'SCL_H_MANUAL_REPLICATE_FACTOR_10', - 10: 'SCL_H_MANUAL_REPLICATE_FACTOR_11', - 11: 'SCL_H_MANUAL_REPLICATE_FACTOR_12', - 12: 'SCL_H_MANUAL_REPLICATE_FACTOR_13', - 13: 'SCL_H_MANUAL_REPLICATE_FACTOR_14', - 14: 'SCL_H_MANUAL_REPLICATE_FACTOR_15', - 15: 'SCL_H_MANUAL_REPLICATE_FACTOR_16', -} -SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0 -SCL_H_MANUAL_REPLICATE_FACTOR_2 = 1 -SCL_H_MANUAL_REPLICATE_FACTOR_3 = 2 -SCL_H_MANUAL_REPLICATE_FACTOR_4 = 3 -SCL_H_MANUAL_REPLICATE_FACTOR_5 = 4 -SCL_H_MANUAL_REPLICATE_FACTOR_6 = 5 -SCL_H_MANUAL_REPLICATE_FACTOR_7 = 6 -SCL_H_MANUAL_REPLICATE_FACTOR_8 = 7 -SCL_H_MANUAL_REPLICATE_FACTOR_9 = 8 -SCL_H_MANUAL_REPLICATE_FACTOR_10 = 9 -SCL_H_MANUAL_REPLICATE_FACTOR_11 = 10 -SCL_H_MANUAL_REPLICATE_FACTOR_12 = 11 -SCL_H_MANUAL_REPLICATE_FACTOR_13 = 12 -SCL_H_MANUAL_REPLICATE_FACTOR_14 = 13 -SCL_H_MANUAL_REPLICATE_FACTOR_15 = 14 -SCL_H_MANUAL_REPLICATE_FACTOR_16 = 15 -SCL_H_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_V_CALC_AUTO_RATIO_EN' -SCL_V_CALC_AUTO_RATIO_EN__enumvalues = { - 0: 'SCL_V_CALC_AUTO_RATIO_DISABLE', - 1: 'SCL_V_CALC_AUTO_RATIO_ENABLE', -} -SCL_V_CALC_AUTO_RATIO_DISABLE = 0 -SCL_V_CALC_AUTO_RATIO_ENABLE = 1 -SCL_V_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_H_CALC_AUTO_RATIO_EN' -SCL_H_CALC_AUTO_RATIO_EN__enumvalues = { - 0: 'SCL_H_CALC_AUTO_RATIO_DISABLE', - 1: 'SCL_H_CALC_AUTO_RATIO_ENABLE', -} -SCL_H_CALC_AUTO_RATIO_DISABLE = 0 -SCL_H_CALC_AUTO_RATIO_ENABLE = 1 -SCL_H_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_H_FILTER_PICK_NEAREST' -SCL_H_FILTER_PICK_NEAREST__enumvalues = { - 0: 'SCL_H_FILTER_PICK_NEAREST_DISABLE', - 1: 'SCL_H_FILTER_PICK_NEAREST_ENABLE', -} -SCL_H_FILTER_PICK_NEAREST_DISABLE = 0 -SCL_H_FILTER_PICK_NEAREST_ENABLE = 1 -SCL_H_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_H_2TAP_HARDCODE_COEF_EN' -SCL_H_2TAP_HARDCODE_COEF_EN__enumvalues = { - 0: 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', - 1: 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', -} -SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0 -SCL_H_2TAP_HARDCODE_COEF_ENABLE = 1 -SCL_H_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_V_FILTER_PICK_NEAREST' -SCL_V_FILTER_PICK_NEAREST__enumvalues = { - 0: 'SCL_V_FILTER_PICK_NEAREST_DISABLE', - 1: 'SCL_V_FILTER_PICK_NEAREST_ENABLE', -} -SCL_V_FILTER_PICK_NEAREST_DISABLE = 0 -SCL_V_FILTER_PICK_NEAREST_ENABLE = 1 -SCL_V_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_V_2TAP_HARDCODE_COEF_EN' -SCL_V_2TAP_HARDCODE_COEF_EN__enumvalues = { - 0: 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', - 1: 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', -} -SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0 -SCL_V_2TAP_HARDCODE_COEF_ENABLE = 1 -SCL_V_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_UPDATE_TAKEN' -SCL_UPDATE_TAKEN__enumvalues = { - 0: 'SCL_UPDATE_TAKEN_NO', - 1: 'SCL_UPDATE_TAKEN_YES', -} -SCL_UPDATE_TAKEN_NO = 0 -SCL_UPDATE_TAKEN_YES = 1 -SCL_UPDATE_TAKEN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_UPDATE_LOCK' -SCL_UPDATE_LOCK__enumvalues = { - 0: 'SCL_UPDATE_UNLOCKED', - 1: 'SCL_UPDATE_LOCKED', -} -SCL_UPDATE_UNLOCKED = 0 -SCL_UPDATE_LOCKED = 1 -SCL_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_UPDATE_COMPLETE' -SCL_COEF_UPDATE_COMPLETE__enumvalues = { - 0: 'SCL_COEF_UPDATE_NOT_COMPLETED', - 1: 'SCL_COEF_UPDATE_COMPLETED', -} -SCL_COEF_UPDATE_NOT_COMPLETED = 0 -SCL_COEF_UPDATE_COMPLETED = 1 -SCL_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_HF_SHARP_SCALE_FACTOR' -SCL_HF_SHARP_SCALE_FACTOR__enumvalues = { - 0: 'SCL_HF_SHARP_SCALE_FACTOR_0', - 1: 'SCL_HF_SHARP_SCALE_FACTOR_1', - 2: 'SCL_HF_SHARP_SCALE_FACTOR_2', - 3: 'SCL_HF_SHARP_SCALE_FACTOR_3', - 4: 'SCL_HF_SHARP_SCALE_FACTOR_4', - 5: 'SCL_HF_SHARP_SCALE_FACTOR_5', - 6: 'SCL_HF_SHARP_SCALE_FACTOR_6', - 7: 'SCL_HF_SHARP_SCALE_FACTOR_7', -} -SCL_HF_SHARP_SCALE_FACTOR_0 = 0 -SCL_HF_SHARP_SCALE_FACTOR_1 = 1 -SCL_HF_SHARP_SCALE_FACTOR_2 = 2 -SCL_HF_SHARP_SCALE_FACTOR_3 = 3 -SCL_HF_SHARP_SCALE_FACTOR_4 = 4 -SCL_HF_SHARP_SCALE_FACTOR_5 = 5 -SCL_HF_SHARP_SCALE_FACTOR_6 = 6 -SCL_HF_SHARP_SCALE_FACTOR_7 = 7 -SCL_HF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_HF_SHARP_EN' -SCL_HF_SHARP_EN__enumvalues = { - 0: 'SCL_HF_SHARP_DISABLE', - 1: 'SCL_HF_SHARP_ENABLE', -} -SCL_HF_SHARP_DISABLE = 0 -SCL_HF_SHARP_ENABLE = 1 -SCL_HF_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_VF_SHARP_SCALE_FACTOR' -SCL_VF_SHARP_SCALE_FACTOR__enumvalues = { - 0: 'SCL_VF_SHARP_SCALE_FACTOR_0', - 1: 'SCL_VF_SHARP_SCALE_FACTOR_1', - 2: 'SCL_VF_SHARP_SCALE_FACTOR_2', - 3: 'SCL_VF_SHARP_SCALE_FACTOR_3', - 4: 'SCL_VF_SHARP_SCALE_FACTOR_4', - 5: 'SCL_VF_SHARP_SCALE_FACTOR_5', - 6: 'SCL_VF_SHARP_SCALE_FACTOR_6', - 7: 'SCL_VF_SHARP_SCALE_FACTOR_7', -} -SCL_VF_SHARP_SCALE_FACTOR_0 = 0 -SCL_VF_SHARP_SCALE_FACTOR_1 = 1 -SCL_VF_SHARP_SCALE_FACTOR_2 = 2 -SCL_VF_SHARP_SCALE_FACTOR_3 = 3 -SCL_VF_SHARP_SCALE_FACTOR_4 = 4 -SCL_VF_SHARP_SCALE_FACTOR_5 = 5 -SCL_VF_SHARP_SCALE_FACTOR_6 = 6 -SCL_VF_SHARP_SCALE_FACTOR_7 = 7 -SCL_VF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_VF_SHARP_EN' -SCL_VF_SHARP_EN__enumvalues = { - 0: 'SCL_VF_SHARP_DISABLE', - 1: 'SCL_VF_SHARP_ENABLE', -} -SCL_VF_SHARP_DISABLE = 0 -SCL_VF_SHARP_ENABLE = 1 -SCL_VF_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_ALU_DISABLE' -SCL_ALU_DISABLE__enumvalues = { - 0: 'SCL_ALU_ENABLED', - 1: 'SCL_ALU_DISABLED', -} -SCL_ALU_ENABLED = 0 -SCL_ALU_DISABLED = 1 -SCL_ALU_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_HOST_CONFLICT_MASK' -SCL_HOST_CONFLICT_MASK__enumvalues = { - 0: 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', - 1: 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', -} -SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0 -SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 1 -SCL_HOST_CONFLICT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_SCL_MODE_CHANGE_MASK' -SCL_SCL_MODE_CHANGE_MASK__enumvalues = { - 0: 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', - 1: 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', -} -SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0 -SCL_MODE_CHANGE_ENABLE_INTERRUPT = 1 -SCL_SCL_MODE_CHANGE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SCLV_MODE_SEL' -SCLV_MODE_SEL__enumvalues = { - 0: 'SCLV_MODE_RGB_BYPASS', - 1: 'SCLV_MODE_RGB_SCALING', - 2: 'SCLV_MODE_YCBCR_SCALING', - 3: 'SCLV_MODE_YCBCR_BYPASS', -} -SCLV_MODE_RGB_BYPASS = 0 -SCLV_MODE_RGB_SCALING = 1 -SCLV_MODE_YCBCR_SCALING = 2 -SCLV_MODE_YCBCR_BYPASS = 3 -SCLV_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCLV_INTERLACE_SOURCE' -SCLV_INTERLACE_SOURCE__enumvalues = { - 0: 'INTERLACE_SOURCE_PROGRESSIVE', - 1: 'INTERLACE_SOURCE_INTERLEAVE', - 2: 'INTERLACE_SOURCE_STACK', -} -INTERLACE_SOURCE_PROGRESSIVE = 0 -INTERLACE_SOURCE_INTERLEAVE = 1 -INTERLACE_SOURCE_STACK = 2 -SCLV_INTERLACE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SCLV_UPDATE_LOCK' -SCLV_UPDATE_LOCK__enumvalues = { - 0: 'UPDATE_UNLOCKED', - 1: 'UPDATE_LOCKED', -} -UPDATE_UNLOCKED = 0 -UPDATE_LOCKED = 1 -SCLV_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'SCLV_COEF_UPDATE_COMPLETE' -SCLV_COEF_UPDATE_COMPLETE__enumvalues = { - 0: 'COEF_UPDATE_NOT_COMPLETE', - 1: 'COEF_UPDATE_COMPLETE', -} -COEF_UPDATE_NOT_COMPLETE = 0 -COEF_UPDATE_COMPLETE = 1 -SCLV_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DPRX_SD_PIXEL_ENCODING' -DPRX_SD_PIXEL_ENCODING__enumvalues = { - 0: 'PIXEL_FORMAT_RGB_444', - 1: 'PIXEL_FORMAT_YCBCR_444', - 2: 'PIXEL_FORMAT_YCBCR_422', - 3: 'PIXEL_FORMAT_Y_ONLY', -} -PIXEL_FORMAT_RGB_444 = 0 -PIXEL_FORMAT_YCBCR_444 = 1 -PIXEL_FORMAT_YCBCR_422 = 2 -PIXEL_FORMAT_Y_ONLY = 3 -DPRX_SD_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DPRX_SD_COMPONENT_DEPTH' -DPRX_SD_COMPONENT_DEPTH__enumvalues = { - 0: 'COMPONENT_DEPTH_6BPC', - 1: 'COMPONENT_DEPTH_8BPC', - 2: 'COMPONENT_DEPTH_10BPC', - 3: 'COMPONENT_DEPTH_12BPC', - 4: 'COMPONENT_DEPTH_16BPC', -} -COMPONENT_DEPTH_6BPC = 0 -COMPONENT_DEPTH_8BPC = 1 -COMPONENT_DEPTH_10BPC = 2 -COMPONENT_DEPTH_12BPC = 3 -COMPONENT_DEPTH_16BPC = 4 -DPRX_SD_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' -AZ_LATENCY_COUNTER_CONTROL__enumvalues = { - 0: 'AZ_LATENCY_COUNTER_NO_RESET', - 1: 'AZ_LATENCY_COUNTER_RESET_DONE', -} -AZ_LATENCY_COUNTER_NO_RESET = 0 -AZ_LATENCY_COUNTER_RESET_DONE = 1 -AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_MODE' -BLND_CONTROL_BLND_MODE__enumvalues = { - 0: 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', - 1: 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', - 2: 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', - 3: 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', -} -BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 -BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 -BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 -BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 -BLND_CONTROL_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_STEREO_TYPE' -BLND_CONTROL_BLND_STEREO_TYPE__enumvalues = { - 0: 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', - 1: 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', - 2: 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', - 3: 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', -} -BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 -BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 -BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 -BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 -BLND_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_STEREO_POLARITY' -BLND_CONTROL_BLND_STEREO_POLARITY__enumvalues = { - 0: 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', - 1: 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', -} -BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0 -BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 -BLND_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_FEEDTHROUGH_EN' -BLND_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { - 0: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', - 1: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', -} -BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 -BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 -BLND_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_ALPHA_MODE' -BLND_CONTROL_BLND_ALPHA_MODE__enumvalues = { - 0: 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', - 1: 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', - 3: 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', -} -BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 -BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 -BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 -BLND_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' -BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', - 1: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', -} -BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0 -BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 1 -BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL_BLND_MULTIPLIED_MODE' -BLND_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { - 0: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', - 1: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', -} -BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 -BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 -BLND_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_SM_CONTROL2_SM_MODE' -BLND_SM_CONTROL2_SM_MODE__enumvalues = { - 0: 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', - 2: 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', - 4: 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 -BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 -BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 -BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -BLND_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE' -BLND_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { - 0: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', - 1: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', -} -BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 -BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 -BLND_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE' -BLND_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { - 0: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', - 1: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', -} -BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 -BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 -BLND_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL2_PTI_ENABLE' -BLND_CONTROL2_PTI_ENABLE__enumvalues = { - 0: 'BLND_CONTROL2_PTI_ENABLE_FALSE', - 1: 'BLND_CONTROL2_PTI_ENABLE_TRUE', -} -BLND_CONTROL2_PTI_ENABLE_FALSE = 0 -BLND_CONTROL2_PTI_ENABLE_TRUE = 1 -BLND_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' -BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { - 0: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', - 1: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', -} -BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 -BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 -BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN' -BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { - 0: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', - 1: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', -} -BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 -BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 -BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { - 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', - 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', -} -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { - 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', - 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', -} -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 -BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' -BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' -BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { - 0: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', - 1: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', -} -BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 -BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 -BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_DEBUG_BLND_CNV_MUX_SELECT' -BLND_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { - 0: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', - 1: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', -} -BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 -BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 -BLND_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' -BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', -} -BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 -BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 -BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', -} -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_EN' -UNP_GRPH_EN__enumvalues = { - 0: 'UNP_GRPH_DISABLED', - 1: 'UNP_GRPH_ENABLED', -} -UNP_GRPH_DISABLED = 0 -UNP_GRPH_ENABLED = 1 -UNP_GRPH_EN = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_DEPTH' -UNP_GRPH_DEPTH__enumvalues = { - 0: 'UNP_GRPH_8BPP', - 1: 'UNP_GRPH_16BPP', - 2: 'UNP_GRPH_32BPP', -} -UNP_GRPH_8BPP = 0 -UNP_GRPH_16BPP = 1 -UNP_GRPH_32BPP = 2 -UNP_GRPH_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_NUM_BANKS' -UNP_GRPH_NUM_BANKS__enumvalues = { - 0: 'UNP_GRPH_ADDR_SURF_2_BANK', - 1: 'UNP_GRPH_ADDR_SURF_4_BANK', - 2: 'UNP_GRPH_ADDR_SURF_8_BANK', - 3: 'UNP_GRPH_ADDR_SURF_16_BANK', -} -UNP_GRPH_ADDR_SURF_2_BANK = 0 -UNP_GRPH_ADDR_SURF_4_BANK = 1 -UNP_GRPH_ADDR_SURF_8_BANK = 2 -UNP_GRPH_ADDR_SURF_16_BANK = 3 -UNP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_BANK_WIDTH' -UNP_GRPH_BANK_WIDTH__enumvalues = { - 0: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', - 1: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', - 2: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', - 3: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', -} -UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0 -UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 1 -UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 2 -UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 3 -UNP_GRPH_BANK_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_BANK_HEIGHT' -UNP_GRPH_BANK_HEIGHT__enumvalues = { - 0: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', - 1: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', - 2: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', - 3: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', -} -UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0 -UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 1 -UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 2 -UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 3 -UNP_GRPH_BANK_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_TILE_SPLIT' -UNP_GRPH_TILE_SPLIT__enumvalues = { - 0: 'UNP_ADDR_SURF_TILE_SPLIT_64B', - 1: 'UNP_ADDR_SURF_TILE_SPLIT_128B', - 2: 'UNP_ADDR_SURF_TILE_SPLIT_256B', - 3: 'UNP_ADDR_SURF_TILE_SPLIT_512B', - 4: 'UNP_ADDR_SURF_TILE_SPLIT_1KB', - 5: 'UNP_ADDR_SURF_TILE_SPLIT_2KB', - 6: 'UNP_ADDR_SURF_TILE_SPLIT_4KB', -} -UNP_ADDR_SURF_TILE_SPLIT_64B = 0 -UNP_ADDR_SURF_TILE_SPLIT_128B = 1 -UNP_ADDR_SURF_TILE_SPLIT_256B = 2 -UNP_ADDR_SURF_TILE_SPLIT_512B = 3 -UNP_ADDR_SURF_TILE_SPLIT_1KB = 4 -UNP_ADDR_SURF_TILE_SPLIT_2KB = 5 -UNP_ADDR_SURF_TILE_SPLIT_4KB = 6 -UNP_GRPH_TILE_SPLIT = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE' -UNP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { - 0: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', - 1: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', -} -UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0 -UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 1 -UNP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_MACRO_TILE_ASPECT' -UNP_GRPH_MACRO_TILE_ASPECT__enumvalues = { - 0: 'UNP_ADDR_SURF_MACRO_ASPECT_1', - 1: 'UNP_ADDR_SURF_MACRO_ASPECT_2', - 2: 'UNP_ADDR_SURF_MACRO_ASPECT_4', - 3: 'UNP_ADDR_SURF_MACRO_ASPECT_8', -} -UNP_ADDR_SURF_MACRO_ASPECT_1 = 0 -UNP_ADDR_SURF_MACRO_ASPECT_2 = 1 -UNP_ADDR_SURF_MACRO_ASPECT_4 = 2 -UNP_ADDR_SURF_MACRO_ASPECT_8 = 3 -UNP_GRPH_MACRO_TILE_ASPECT = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_COLOR_EXPANSION_MODE' -UNP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { - 0: 'UNP_GRPH_DYNAMIC_EXPANSION', - 1: 'UNP_GRPH_ZERO_EXPANSION', -} -UNP_GRPH_DYNAMIC_EXPANSION = 0 -UNP_GRPH_ZERO_EXPANSION = 1 -UNP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_VIDEO_FORMAT' -UNP_VIDEO_FORMAT__enumvalues = { - 0: 'UNP_VIDEO_FORMAT0', - 1: 'UNP_VIDEO_FORMAT1', - 2: 'UNP_VIDEO_FORMAT_YUV420_YCbCr', - 3: 'UNP_VIDEO_FORMAT_YUV420_YCrCb', - 4: 'UNP_VIDEO_FORMAT_YUV422_YCb', - 5: 'UNP_VIDEO_FORMAT_YUV422_YCr', - 6: 'UNP_VIDEO_FORMAT_YUV422_CbY', - 7: 'UNP_VIDEO_FORMAT_YUV422_CrY', -} -UNP_VIDEO_FORMAT0 = 0 -UNP_VIDEO_FORMAT1 = 1 -UNP_VIDEO_FORMAT_YUV420_YCbCr = 2 -UNP_VIDEO_FORMAT_YUV420_YCrCb = 3 -UNP_VIDEO_FORMAT_YUV422_YCb = 4 -UNP_VIDEO_FORMAT_YUV422_YCr = 5 -UNP_VIDEO_FORMAT_YUV422_CbY = 6 -UNP_VIDEO_FORMAT_YUV422_CrY = 7 -UNP_VIDEO_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_ENDIAN_SWAP' -UNP_GRPH_ENDIAN_SWAP__enumvalues = { - 0: 'UNP_GRPH_ENDIAN_SWAP_NONE', - 1: 'UNP_GRPH_ENDIAN_SWAP_8IN16', - 2: 'UNP_GRPH_ENDIAN_SWAP_8IN32', - 3: 'UNP_GRPH_ENDIAN_SWAP_8IN43', -} -UNP_GRPH_ENDIAN_SWAP_NONE = 0 -UNP_GRPH_ENDIAN_SWAP_8IN16 = 1 -UNP_GRPH_ENDIAN_SWAP_8IN32 = 2 -UNP_GRPH_ENDIAN_SWAP_8IN43 = 3 -UNP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_RED_CROSSBAR' -UNP_GRPH_RED_CROSSBAR__enumvalues = { - 0: 'UNP_GRPH_RED_CROSSBAR_R_Cr', - 1: 'UNP_GRPH_RED_CROSSBAR_G_Y', - 2: 'UNP_GRPH_RED_CROSSBAR_B_Cb', - 3: 'UNP_GRPH_RED_CROSSBAR_A', -} -UNP_GRPH_RED_CROSSBAR_R_Cr = 0 -UNP_GRPH_RED_CROSSBAR_G_Y = 1 -UNP_GRPH_RED_CROSSBAR_B_Cb = 2 -UNP_GRPH_RED_CROSSBAR_A = 3 -UNP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_GREEN_CROSSBAR' -UNP_GRPH_GREEN_CROSSBAR__enumvalues = { - 0: 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', - 1: 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', - 2: 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', - 3: 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', -} -UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0 -UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 1 -UNP_UNP_GRPH_GREEN_CROSSBAR_A = 2 -UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 3 -UNP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_BLUE_CROSSBAR' -UNP_GRPH_BLUE_CROSSBAR__enumvalues = { - 0: 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', - 1: 'UNP_GRPH_BLUE_CROSSBAR_A', - 2: 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', - 3: 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', -} -UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0 -UNP_GRPH_BLUE_CROSSBAR_A = 1 -UNP_GRPH_BLUE_CROSSBAR_R_Cr = 2 -UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 3 -UNP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_MODE_UPDATE_LOCKG' -UNP_GRPH_MODE_UPDATE_LOCKG__enumvalues = { - 0: 'UNP_GRPH_UPDATE_LOCK_0', - 1: 'UNP_GRPH_UPDATE_LOCK_1', -} -UNP_GRPH_UPDATE_LOCK_0 = 0 -UNP_GRPH_UPDATE_LOCK_1 = 1 -UNP_GRPH_MODE_UPDATE_LOCKG = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' -UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { - 0: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', - 1: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', -} -UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0 -UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 1 -UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' -UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', - 1: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', -} -UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0 -UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 1 -UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' -UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', - 1: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', -} -UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0 -UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 1 -UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_EN' -UNP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { - 0: 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', - 1: 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', -} -UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0 -UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 1 -UNP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_MODE' -UNP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { - 0: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', - 1: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', - 2: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', - 3: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', -} -UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0 -UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 1 -UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 2 -UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 3 -UNP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_EN' -UNP_GRPH_STACK_INTERLACE_FLIP_EN__enumvalues = { - 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', - 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', -} -UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0 -UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 1 -UNP_GRPH_STACK_INTERLACE_FLIP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE' -UNP_GRPH_STACK_INTERLACE_FLIP_MODE__enumvalues = { - 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', - 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', - 2: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', - 3: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', -} -UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0 -UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 1 -UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 2 -UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 3 -UNP_GRPH_STACK_INTERLACE_FLIP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE' -UNP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { - 0: 'UNP_GRPH_STEREOSYNC_SELECT_EN', - 1: 'UNP_GRPH_STEREOSYNC_SELECT_DIS', -} -UNP_GRPH_STEREOSYNC_SELECT_EN = 0 -UNP_GRPH_STEREOSYNC_SELECT_DIS = 1 -UNP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_CRC_SOURCE_SEL' -UNP_CRC_SOURCE_SEL__enumvalues = { - 0: 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', - 1: 'UNP_CRC_SOURCE_SEL_LOWER32', - 2: 'UNP_CRC_SOURCE_SEL_RESERVED', - 3: 'UNP_CRC_SOURCE_SEL_LOWER16', - 4: 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', -} -UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0 -UNP_CRC_SOURCE_SEL_LOWER32 = 1 -UNP_CRC_SOURCE_SEL_RESERVED = 2 -UNP_CRC_SOURCE_SEL_LOWER16 = 3 -UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 4 -UNP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_CRC_LINE_SEL' -UNP_CRC_LINE_SEL__enumvalues = { - 0: 'UNP_CRC_LINE_SEL_RESERVED', - 1: 'UNP_CRC_LINE_SEL_EVEN_ONLY', - 2: 'UNP_CRC_LINE_SEL_ODD_ONLY', - 3: 'UNP_CRC_LINE_SEL_ODD_EVEN', -} -UNP_CRC_LINE_SEL_RESERVED = 0 -UNP_CRC_LINE_SEL_EVEN_ONLY = 1 -UNP_CRC_LINE_SEL_ODD_ONLY = 2 -UNP_CRC_LINE_SEL_ODD_EVEN = 3 -UNP_CRC_LINE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_ROTATION_ANGLE' -UNP_ROTATION_ANGLE__enumvalues = { - 0: 'UNP_ROTATION_ANGLE_0', - 1: 'UNP_ROTATION_ANGLE_90', - 2: 'UNP_ROTATION_ANGLE_180', - 3: 'UNP_ROTATION_ANGLE_270', - 4: 'UNP_ROTATION_ANGLE_0m', - 5: 'UNP_ROTATION_ANGLE_90m', - 6: 'UNP_ROTATION_ANGLE_180m', - 7: 'UNP_ROTATION_ANGLE_270m', -} -UNP_ROTATION_ANGLE_0 = 0 -UNP_ROTATION_ANGLE_90 = 1 -UNP_ROTATION_ANGLE_180 = 2 -UNP_ROTATION_ANGLE_270 = 3 -UNP_ROTATION_ANGLE_0m = 4 -UNP_ROTATION_ANGLE_90m = 5 -UNP_ROTATION_ANGLE_180m = 6 -UNP_ROTATION_ANGLE_270m = 7 -UNP_ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_PIXEL_DROP' -UNP_PIXEL_DROP__enumvalues = { - 0: 'UNP_PIXEL_NO_DROP', - 1: 'UNP_PIXEL_DROPPING', -} -UNP_PIXEL_NO_DROP = 0 -UNP_PIXEL_DROPPING = 1 -UNP_PIXEL_DROP = ctypes.c_uint32 # enum - -# values for enumeration 'UNP_BUFFER_MODE' -UNP_BUFFER_MODE__enumvalues = { - 0: 'UNP_BUFFER_MODE_LUMA', - 1: 'UNP_BUFFER_MODE_LUMA_CHROMA', -} -UNP_BUFFER_MODE_LUMA = 0 -UNP_BUFFER_MODE_LUMA_CHROMA = 1 -UNP_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_COMPLETE' -DP_LINK_TRAINING_COMPLETE__enumvalues = { - 0: 'DP_LINK_TRAINING_NOT_COMPLETE', - 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', -} -DP_LINK_TRAINING_NOT_COMPLETE = 0 -DP_LINK_TRAINING_ALREADY_COMPLETE = 1 -DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_EMBEDDED_PANEL_MODE' -DP_EMBEDDED_PANEL_MODE__enumvalues = { - 0: 'DP_EXTERNAL_PANEL', - 1: 'DP_EMBEDDED_PANEL', -} -DP_EXTERNAL_PANEL = 0 -DP_EMBEDDED_PANEL = 1 -DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING' -DP_PIXEL_ENCODING__enumvalues = { - 0: 'DP_PIXEL_ENCODING_RGB444', - 1: 'DP_PIXEL_ENCODING_YCBCR422', - 2: 'DP_PIXEL_ENCODING_YCBCR444', - 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 4: 'DP_PIXEL_ENCODING_Y_ONLY', - 5: 'DP_PIXEL_ENCODING_YCBCR420', - 6: 'DP_PIXEL_ENCODING_RESERVED', -} -DP_PIXEL_ENCODING_RGB444 = 0 -DP_PIXEL_ENCODING_YCBCR422 = 1 -DP_PIXEL_ENCODING_YCBCR444 = 2 -DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 -DP_PIXEL_ENCODING_Y_ONLY = 4 -DP_PIXEL_ENCODING_YCBCR420 = 5 -DP_PIXEL_ENCODING_RESERVED = 6 -DP_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DYN_RANGE' -DP_DYN_RANGE__enumvalues = { - 0: 'DP_DYN_VESA_RANGE', - 1: 'DP_DYN_CEA_RANGE', -} -DP_DYN_VESA_RANGE = 0 -DP_DYN_CEA_RANGE = 1 -DP_DYN_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_YCBCR_RANGE' -DP_YCBCR_RANGE__enumvalues = { - 0: 'DP_YCBCR_RANGE_BT601_5', - 1: 'DP_YCBCR_RANGE_BT709_5', -} -DP_YCBCR_RANGE_BT601_5 = 0 -DP_YCBCR_RANGE_BT709_5 = 1 -DP_YCBCR_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPONENT_DEPTH' -DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_COMPONENT_DEPTH_6BPC', - 1: 'DP_COMPONENT_DEPTH_8BPC', - 2: 'DP_COMPONENT_DEPTH_10BPC', - 3: 'DP_COMPONENT_DEPTH_12BPC', - 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', - 5: 'DP_COMPONENT_DEPTH_RESERVED', -} -DP_COMPONENT_DEPTH_6BPC = 0 -DP_COMPONENT_DEPTH_8BPC = 1 -DP_COMPONENT_DEPTH_10BPC = 2 -DP_COMPONENT_DEPTH_12BPC = 3 -DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 -DP_COMPONENT_DEPTH_RESERVED = 5 -DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_MISC0_OVERRIDE_ENABLE' -DP_MSA_MISC0_OVERRIDE_ENABLE__enumvalues = { - 0: 'MSA_MISC0_OVERRIDE_DISABLE', - 1: 'MSA_MISC0_OVERRIDE_ENABLE', -} -MSA_MISC0_OVERRIDE_DISABLE = 0 -MSA_MISC0_OVERRIDE_ENABLE = 1 -DP_MSA_MISC0_OVERRIDE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE' -DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__enumvalues = { - 0: 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', - 1: 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', -} -MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0 -MSA_MISC1_BIT7_OVERRIDE_ENABLE = 1 -DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_UDI_LANES' -DP_UDI_LANES__enumvalues = { - 0: 'DP_UDI_1_LANE', - 1: 'DP_UDI_2_LANES', - 2: 'DP_UDI_LANES_RESERVED', - 3: 'DP_UDI_4_LANES', -} -DP_UDI_1_LANE = 0 -DP_UDI_2_LANES = 1 -DP_UDI_LANES_RESERVED = 2 -DP_UDI_4_LANES = 3 -DP_UDI_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DIS_DEFER' -DP_VID_STREAM_DIS_DEFER__enumvalues = { - 0: 'DP_VID_STREAM_DIS_NO_DEFER', - 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', -} -DP_VID_STREAM_DIS_NO_DEFER = 0 -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 -DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_ACK' -DP_STEER_OVERFLOW_ACK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_MASK' -DP_STEER_OVERFLOW_MASK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_MASKED', - 1: 'DP_STEER_OVERFLOW_UNMASK', -} -DP_STEER_OVERFLOW_MASKED = 0 -DP_STEER_OVERFLOW_UNMASK = 1 -DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_TU_OVERFLOW_ACK' -DP_TU_OVERFLOW_ACK__enumvalues = { - 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' -DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', -} -DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 -DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' -DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', -} -DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 -DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_TIMING_MODE' -DP_VID_TIMING_MODE__enumvalues = { - 0: 'DP_VID_TIMING_MODE_ASYNC', - 1: 'DP_VID_TIMING_MODE_SYNC', -} -DP_VID_TIMING_MODE_ASYNC = 0 -DP_VID_TIMING_MODE_SYNC = 1 -DP_VID_TIMING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' -DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { - 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', -} -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 -DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_GEN_EN' -DP_VID_M_N_GEN_EN__enumvalues = { - 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', - 1: 'DP_VID_M_N_CALC_AUTO', -} -DP_VID_M_N_PROGRAMMED_VIA_REG = 0 -DP_VID_M_N_CALC_AUTO = 1 -DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_DOUBLE_VALUE_EN' -DP_VID_M_DOUBLE_VALUE_EN__enumvalues = { - 0: 'DP_VID_M_INPUT_PIXEL_RATE', - 1: 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', -} -DP_VID_M_INPUT_PIXEL_RATE = 0 -DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 1 -DP_VID_M_DOUBLE_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' -DP_VID_ENHANCED_FRAME_MODE__enumvalues = { - 0: 'VID_NORMAL_FRAME_MODE', - 1: 'VID_ENHANCED_MODE', -} -VID_NORMAL_FRAME_MODE = 0 -VID_ENHANCED_MODE = 1 -DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_MSA_TOP_FIELD_MODE' -DP_VID_MSA_TOP_FIELD_MODE__enumvalues = { - 0: 'DP_TOP_FIELD_ONLY', - 1: 'DP_TOP_PLUS_BOTTOM_FIELD', -} -DP_TOP_FIELD_ONLY = 0 -DP_TOP_PLUS_BOTTOM_FIELD = 1 -DP_VID_MSA_TOP_FIELD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_VBID_FIELD_POL' -DP_VID_VBID_FIELD_POL__enumvalues = { - 0: 'DP_VID_VBID_FIELD_POL_NORMAL', - 1: 'DP_VID_VBID_FIELD_POL_INV', -} -DP_VID_VBID_FIELD_POL_NORMAL = 0 -DP_VID_VBID_FIELD_POL_INV = 1 -DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' -DP_VID_STREAM_DISABLE_ACK__enumvalues = { - 0: 'ID_STREAM_DISABLE_NO_ACK', - 1: 'ID_STREAM_DISABLE_ACKED', -} -ID_STREAM_DISABLE_NO_ACK = 0 -ID_STREAM_DISABLE_ACKED = 1 -DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' -DP_VID_STREAM_DISABLE_MASK__enumvalues = { - 0: 'VID_STREAM_DISABLE_MASKED', - 1: 'VID_STREAM_DISABLE_UNMASK', -} -VID_STREAM_DISABLE_MASKED = 0 -VID_STREAM_DISABLE_UNMASK = 1 -DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE0' -DPHY_ATEST_SEL_LANE0__enumvalues = { - 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE0_REG_PATTERN', -} -DPHY_ATEST_LANE0_PRBS_PATTERN = 0 -DPHY_ATEST_LANE0_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE1' -DPHY_ATEST_SEL_LANE1__enumvalues = { - 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE1_REG_PATTERN', -} -DPHY_ATEST_LANE1_PRBS_PATTERN = 0 -DPHY_ATEST_LANE1_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE2' -DPHY_ATEST_SEL_LANE2__enumvalues = { - 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE2_REG_PATTERN', -} -DPHY_ATEST_LANE2_PRBS_PATTERN = 0 -DPHY_ATEST_LANE2_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE3' -DPHY_ATEST_SEL_LANE3__enumvalues = { - 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE3_REG_PATTERN', -} -DPHY_ATEST_LANE3_PRBS_PATTERN = 0 -DPHY_ATEST_LANE3_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_SEL' -DPHY_SCRAMBLER_SEL__enumvalues = { - 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', - 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', -} -DPHY_SCRAMBLER_SEL_LANE_DATA = 0 -DPHY_SCRAMBLER_SEL_DBG_DATA = 1 -DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_BYPASS' -DPHY_BYPASS__enumvalues = { - 0: 'DPHY_8B10B_OUTPUT', - 1: 'DPHY_DBG_OUTPUT', -} -DPHY_8B10B_OUTPUT = 0 -DPHY_DBG_OUTPUT = 1 -DPHY_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SKEW_BYPASS' -DPHY_SKEW_BYPASS__enumvalues = { - 0: 'DPHY_WITH_SKEW', - 1: 'DPHY_NO_SKEW', -} -DPHY_WITH_SKEW = 0 -DPHY_NO_SKEW = 1 -DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' -DPHY_TRAINING_PATTERN_SEL__enumvalues = { - 0: 'DPHY_TRAINING_PATTERN_1', - 1: 'DPHY_TRAINING_PATTERN_2', - 2: 'DPHY_TRAINING_PATTERN_3', - 3: 'DPHY_TRAINING_PATTERN_4', -} -DPHY_TRAINING_PATTERN_1 = 0 -DPHY_TRAINING_PATTERN_2 = 1 -DPHY_TRAINING_PATTERN_3 = 2 -DPHY_TRAINING_PATTERN_4 = 3 -DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_RESET' -DPHY_8B10B_RESET__enumvalues = { - 0: 'DPHY_8B10B_NOT_RESET', - 1: 'DPHY_8B10B_RESETET', -} -DPHY_8B10B_NOT_RESET = 0 -DPHY_8B10B_RESETET = 1 -DPHY_8B10B_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' -DP_DPHY_8B10B_EXT_DISP__enumvalues = { - 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', -} -DP_DPHY_8B10B_EXT_DISP_ZERO = 0 -DP_DPHY_8B10B_EXT_DISP_ONE = 1 -DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_CUR_DISP' -DPHY_8B10B_CUR_DISP__enumvalues = { - 0: 'DPHY_8B10B_CUR_DISP_ZERO', - 1: 'DPHY_8B10B_CUR_DISP_ONE', -} -DPHY_8B10B_CUR_DISP_ZERO = 0 -DPHY_8B10B_CUR_DISP_ONE = 1 -DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_EN' -DPHY_PRBS_EN__enumvalues = { - 0: 'DPHY_PRBS_DISABLE', - 1: 'DPHY_PRBS_ENABLE', -} -DPHY_PRBS_DISABLE = 0 -DPHY_PRBS_ENABLE = 1 -DPHY_PRBS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_SEL' -DPHY_PRBS_SEL__enumvalues = { - 0: 'DPHY_PRBS7_SELECTED', - 1: 'DPHY_PRBS23_SELECTED', - 2: 'DPHY_PRBS11_SELECTED', -} -DPHY_PRBS7_SELECTED = 0 -DPHY_PRBS23_SELECTED = 1 -DPHY_PRBS11_SELECTED = 2 -DPHY_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_DIS' -DPHY_SCRAMBLER_DIS__enumvalues = { - 0: 'DPHY_SCR_ENABLED', - 1: 'DPHY_SCR_DISABLED', -} -DPHY_SCR_ENABLED = 0 -DPHY_SCR_DISABLED = 1 -DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' -DPHY_SCRAMBLER_ADVANCE__enumvalues = { - 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', -} -DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 -DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 -DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_KCODE' -DPHY_SCRAMBLER_KCODE__enumvalues = { - 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', - 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', -} -DPHY_SCRAMBLER_KCODE_DISABLED = 0 -DPHY_SCRAMBLER_KCODE_ENABLED = 1 -DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_LOAD_BS_COUNT_START' -DPHY_LOAD_BS_COUNT_START__enumvalues = { - 0: 'DPHY_LOAD_BS_COUNT_STARTED', - 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', -} -DPHY_LOAD_BS_COUNT_STARTED = 0 -DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 -DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_EN' -DPHY_CRC_EN__enumvalues = { - 0: 'DPHY_CRC_DISABLED', - 1: 'DPHY_CRC_ENABLED', -} -DPHY_CRC_DISABLED = 0 -DPHY_CRC_ENABLED = 1 -DPHY_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_CONT_EN' -DPHY_CRC_CONT_EN__enumvalues = { - 0: 'DPHY_CRC_ONE_SHOT', - 1: 'DPHY_CRC_CONTINUOUS', -} -DPHY_CRC_ONE_SHOT = 0 -DPHY_CRC_CONTINUOUS = 1 -DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_FIELD' -DPHY_CRC_FIELD__enumvalues = { - 0: 'DPHY_CRC_START_FROM_TOP_FIELD', - 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', -} -DPHY_CRC_START_FROM_TOP_FIELD = 0 -DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 -DPHY_CRC_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_SEL' -DPHY_CRC_SEL__enumvalues = { - 0: 'DPHY_CRC_LANE0_SELECTED', - 1: 'DPHY_CRC_LANE1_SELECTED', - 2: 'DPHY_CRC_LANE2_SELECTED', - 3: 'DPHY_CRC_LANE3_SELECTED', -} -DPHY_CRC_LANE0_SELECTED = 0 -DPHY_CRC_LANE1_SELECTED = 1 -DPHY_CRC_LANE2_SELECTED = 2 -DPHY_CRC_LANE3_SELECTED = 3 -DPHY_CRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' -DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { - 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 1: 'DPHY_FAST_TRAINING_CAPABLE', -} -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 -DPHY_FAST_TRAINING_CAPABLE = 1 -DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_COLLISION_ACK' -DP_SEC_COLLISION_ACK__enumvalues = { - 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', - 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', -} -DP_SEC_COLLISION_ACK_NO_EFFECT = 0 -DP_SEC_COLLISION_ACK_CLR_FLAG = 1 -DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_AUDIO_MUTE' -DP_SEC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', - 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', -} -DP_SEC_AUDIO_MUTE_HW_CTRL = 0 -DP_SEC_AUDIO_MUTE_SW_CTRL = 1 -DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_TIMESTAMP_MODE' -DP_SEC_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', -} -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 -DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_PRIORITY' -DP_SEC_ASP_PRIORITY__enumvalues = { - 0: 'DP_SEC_ASP_LOW_PRIORITY', - 1: 'DP_SEC_ASP_HIGH_PRIORITY', -} -DP_SEC_ASP_LOW_PRIORITY = 0 -DP_SEC_ASP_HIGH_PRIORITY = 1 -DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' -DP_MSE_SAT_UPDATE_ACT__enumvalues = { - 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', - 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', -} -DP_MSE_SAT_UPDATE_NO_ACTION = 0 -DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 -DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 -DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_LINK_LINE' -DP_MSE_LINK_LINE__enumvalues = { - 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', - 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', - 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', - 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', -} -DP_MSE_LINK_LINE_32_MTP_LONG = 0 -DP_MSE_LINK_LINE_64_MTP_LONG = 1 -DP_MSE_LINK_LINE_128_MTP_LONG = 2 -DP_MSE_LINK_LINE_256_MTP_LONG = 3 -DP_MSE_LINK_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_BLANK_CODE' -DP_MSE_BLANK_CODE__enumvalues = { - 0: 'DP_MSE_BLANK_CODE_SF_FILLED', - 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', -} -DP_MSE_BLANK_CODE_SF_FILLED = 0 -DP_MSE_BLANK_CODE_ZERO_FILLED = 1 -DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_TIMESTAMP_MODE' -DP_MSE_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', -} -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 -DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_ZERO_ENCODER' -DP_MSE_ZERO_ENCODER__enumvalues = { - 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', - 1: 'DP_MSE_ZERO_FE_ENCODER', -} -DP_MSE_NOT_ZERO_FE_ENCODER = 0 -DP_MSE_ZERO_FE_ENCODER = 1 -DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_OUTPUT_DPDBG_DATA' -DP_MSE_OUTPUT_DPDBG_DATA__enumvalues = { - 0: 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', - 1: 'DP_MSE_OUTPUT_DPDBG_DATA_EN', -} -DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0 -DP_MSE_OUTPUT_DPDBG_DATA_EN = 1 -DP_MSE_OUTPUT_DPDBG_DATA = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' -DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { - 0: 'DP_DPHY_HBR2_PASS_THROUGH', - 1: 'DP_DPHY_HBR2_PATTERN_1', - 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', - 3: 'DP_DPHY_HBR2_PATTERN_3', - 6: 'DP_DPHY_HBR2_PATTERN_2_POS', -} -DP_DPHY_HBR2_PASS_THROUGH = 0 -DP_DPHY_HBR2_PATTERN_1 = 1 -DP_DPHY_HBR2_PATTERN_2_NEG = 2 -DP_DPHY_HBR2_PATTERN_3 = 3 -DP_DPHY_HBR2_PATTERN_2_POS = 6 -DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' -DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { - 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', - 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', -} -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 -DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 -DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SW_FAST_TRAINING_START' -DPHY_SW_FAST_TRAINING_START__enumvalues = { - 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 1: 'DPHY_SW_FAST_TRAINING_STARTED', -} -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 -DPHY_SW_FAST_TRAINING_STARTED = 1 -DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', -} -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' -DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' -DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' -DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { - 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', - 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', -} -MSA_V_TIMING_OVERRIDE_DISABLED = 0 -MSA_V_TIMING_OVERRIDE_ENABLED = 1 -DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_PRIORITY' -DP_SEC_GSP0_PRIORITY__enumvalues = { - 0: 'SEC_GSP0_PRIORITY_LOW', - 1: 'SEC_GSP0_PRIORITY_HIGH', -} -SEC_GSP0_PRIORITY_LOW = 0 -SEC_GSP0_PRIORITY_HIGH = 1 -DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_SEND' -DP_SEC_GSP0_SEND__enumvalues = { - 0: 'NOT_SENT', - 1: 'FORCE_SENT', -} -NOT_SENT = 0 -FORCE_SENT = 1 -DP_SEC_GSP0_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_UPDATE_LOCK' -COL_MAN_UPDATE_LOCK__enumvalues = { - 0: 'COL_MAN_UPDATE_UNLOCKED', - 1: 'COL_MAN_UPDATE_LOCKED', -} -COL_MAN_UPDATE_UNLOCKED = 0 -COL_MAN_UPDATE_LOCKED = 1 -COL_MAN_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_DISABLE_MULTIPLE_UPDATE' -COL_MAN_DISABLE_MULTIPLE_UPDATE__enumvalues = { - 0: 'COL_MAN_MULTIPLE_UPDATE', - 1: 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', -} -COL_MAN_MULTIPLE_UPDATE = 0 -COL_MAN_MULTIPLE_UPDAT_EDISABLE = 1 -COL_MAN_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_INPUTCSC_MODE' -COL_MAN_INPUTCSC_MODE__enumvalues = { - 0: 'INPUTCSC_MODE_BYPASS', - 1: 'INPUTCSC_MODE_A', - 2: 'INPUTCSC_MODE_B', - 3: 'INPUTCSC_MODE_UNITY', -} -INPUTCSC_MODE_BYPASS = 0 -INPUTCSC_MODE_A = 1 -INPUTCSC_MODE_B = 2 -INPUTCSC_MODE_UNITY = 3 -COL_MAN_INPUTCSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_INPUTCSC_TYPE' -COL_MAN_INPUTCSC_TYPE__enumvalues = { - 0: 'INPUTCSC_TYPE_12_0', - 1: 'INPUTCSC_TYPE_10_2', - 2: 'INPUTCSC_TYPE_8_4', -} -INPUTCSC_TYPE_12_0 = 0 -INPUTCSC_TYPE_10_2 = 1 -INPUTCSC_TYPE_8_4 = 2 -COL_MAN_INPUTCSC_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_INPUTCSC_CONVERT' -COL_MAN_INPUTCSC_CONVERT__enumvalues = { - 0: 'INPUTCSC_ROUND', - 1: 'INPUTCSC_TRUNCATE', -} -INPUTCSC_ROUND = 0 -INPUTCSC_TRUNCATE = 1 -COL_MAN_INPUTCSC_CONVERT = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_PRESCALE_MODE' -COL_MAN_PRESCALE_MODE__enumvalues = { - 0: 'PRESCALE_MODE_BYPASS', - 1: 'PRESCALE_MODE_PROGRAM', - 2: 'PRESCALE_MODE_UNITY', -} -PRESCALE_MODE_BYPASS = 0 -PRESCALE_MODE_PROGRAM = 1 -PRESCALE_MODE_UNITY = 2 -COL_MAN_PRESCALE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_INPUT_GAMMA_MODE' -COL_MAN_INPUT_GAMMA_MODE__enumvalues = { - 0: 'INGAMMA_MODE_BYPASS', - 1: 'INGAMMA_MODE_FIX', - 2: 'INGAMMA_MODE_FLOAT', -} -INGAMMA_MODE_BYPASS = 0 -INGAMMA_MODE_FIX = 1 -INGAMMA_MODE_FLOAT = 2 -COL_MAN_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_OUTPUT_CSC_MODE' -COL_MAN_OUTPUT_CSC_MODE__enumvalues = { - 0: 'COL_MAN_OUTPUT_CSC_BYPASS', - 1: 'COL_MAN_OUTPUT_CSC_RGB', - 2: 'COL_MAN_OUTPUT_CSC_YCrCb601', - 3: 'COL_MAN_OUTPUT_CSC_YCrCb709', - 4: 'COL_MAN_OUTPUT_CSC_A', - 5: 'COL_MAN_OUTPUT_CSC_B', - 6: 'COL_MAN_OUTPUT_CSC_UNITY', -} -COL_MAN_OUTPUT_CSC_BYPASS = 0 -COL_MAN_OUTPUT_CSC_RGB = 1 -COL_MAN_OUTPUT_CSC_YCrCb601 = 2 -COL_MAN_OUTPUT_CSC_YCrCb709 = 3 -COL_MAN_OUTPUT_CSC_A = 4 -COL_MAN_OUTPUT_CSC_B = 5 -COL_MAN_OUTPUT_CSC_UNITY = 6 -COL_MAN_OUTPUT_CSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_DENORM_CLAMP_CONTROL' -COL_MAN_DENORM_CLAMP_CONTROL__enumvalues = { - 0: 'DENORM_CLAMP_MODE_UNITY', - 1: 'DENORM_CLAMP_MODE_8', - 2: 'DENORM_CLAMP_MODE_10', - 3: 'DENORM_CLAMP_MODE_12', -} -DENORM_CLAMP_MODE_UNITY = 0 -DENORM_CLAMP_MODE_8 = 1 -DENORM_CLAMP_MODE_10 = 2 -DENORM_CLAMP_MODE_12 = 3 -COL_MAN_DENORM_CLAMP_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_REGAMMA_MODE_CONTROL' -COL_MAN_REGAMMA_MODE_CONTROL__enumvalues = { - 0: 'COL_MAN_REGAMMA_MODE_BYPASS', - 1: 'COL_MAN_REGAMMA_MODE_ROM_A', - 2: 'COL_MAN_REGAMMA_MODE_ROM_B', - 3: 'COL_MAN_REGAMMA_MODE_A', - 4: 'COL_MAN_REGAMMA_MODE_B', -} -COL_MAN_REGAMMA_MODE_BYPASS = 0 -COL_MAN_REGAMMA_MODE_ROM_A = 1 -COL_MAN_REGAMMA_MODE_ROM_B = 2 -COL_MAN_REGAMMA_MODE_A = 3 -COL_MAN_REGAMMA_MODE_B = 4 -COL_MAN_REGAMMA_MODE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE' -COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__enumvalues = { - 0: 'CM_GLOBAL_PASSTHROUGH_DISBALE', - 1: 'CM_GLOBAL_PASSTHROUGH_ENABLE', -} -CM_GLOBAL_PASSTHROUGH_DISBALE = 0 -CM_GLOBAL_PASSTHROUGH_ENABLE = 1 -COL_MAN_GLOBAL_PASSTHROUGH_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_DEGAMMA_MODE' -COL_MAN_DEGAMMA_MODE__enumvalues = { - 0: 'DEGAMMA_MODE_BYPASS', - 1: 'DEGAMMA_MODE_A', - 2: 'DEGAMMA_MODE_B', -} -DEGAMMA_MODE_BYPASS = 0 -DEGAMMA_MODE_A = 1 -DEGAMMA_MODE_B = 2 -COL_MAN_DEGAMMA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'COL_MAN_GAMUT_REMAP_MODE' -COL_MAN_GAMUT_REMAP_MODE__enumvalues = { - 0: 'GAMUT_REMAP_MODE_BYPASS', - 1: 'GAMUT_REMAP_MODE_1', - 2: 'GAMUT_REMAP_MODE_2', - 3: 'GAMUT_REMAP_MODE_3', -} -GAMUT_REMAP_MODE_BYPASS = 0 -GAMUT_REMAP_MODE_1 = 1 -GAMUT_REMAP_MODE_2 = 2 -GAMUT_REMAP_MODE_3 = 3 -COL_MAN_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' -DP_AUX_CONTROL_HPD_SEL__enumvalues = { - 0: 'DP_AUX_CONTROL_HPD1_SELECTED', - 1: 'DP_AUX_CONTROL_HPD2_SELECTED', - 2: 'DP_AUX_CONTROL_HPD3_SELECTED', - 3: 'DP_AUX_CONTROL_HPD4_SELECTED', - 4: 'DP_AUX_CONTROL_HPD5_SELECTED', - 5: 'DP_AUX_CONTROL_HPD6_SELECTED', -} -DP_AUX_CONTROL_HPD1_SELECTED = 0 -DP_AUX_CONTROL_HPD2_SELECTED = 1 -DP_AUX_CONTROL_HPD3_SELECTED = 2 -DP_AUX_CONTROL_HPD4_SELECTED = 3 -DP_AUX_CONTROL_HPD5_SELECTED = 4 -DP_AUX_CONTROL_HPD6_SELECTED = 5 -DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' -DP_AUX_CONTROL_TEST_MODE__enumvalues = { - 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', -} -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 -DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 -DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' -DP_AUX_SW_CONTROL_SW_GO__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 1: 'DP_AUX_SW_CONTROL_SW__GO', -} -DP_AUX_SW_CONTROL_SW__NOT_GO = 0 -DP_AUX_SW_CONTROL_SW__GO = 1 -DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' -DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', -} -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 -DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 -DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' -DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', -} -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 -DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', -} -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', -} -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_INT_ACK' -DP_AUX_INT_ACK__enumvalues = { - 0: 'DP_AUX_INT__NOT_ACK', - 1: 'DP_AUX_INT__ACK', -} -DP_AUX_INT__NOT_ACK = 0 -DP_AUX_INT__ACK = 1 -DP_AUX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_LS_UPDATE_ACK' -DP_AUX_LS_UPDATE_ACK__enumvalues = { - 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', - 1: 'DP_AUX_INT_LS_UPDATE_ACK', -} -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 -DP_AUX_INT_LS_UPDATE_ACK = 1 -DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN' -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', - 1: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', - 2: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', - 3: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', - 4: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', - 5: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', - 6: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', - 7: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', -} -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 1 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 2 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 3 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 4 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 5 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 6 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 7 -DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', -} -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', -} -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', -} -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN' -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', - 1: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', - 2: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', - 3: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', - 4: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', - 5: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', - 6: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', - 7: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', -} -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 1 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 2 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 3 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 4 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 5 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 6 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 7 -DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { - 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', -} -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', -} -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', -} -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', -} -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', -} -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' -DP_AUX_ERR_OCCURRED_ACK__enumvalues = { - 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 1: 'DP_AUX_ERR_OCCURRED__ACK', -} -DP_AUX_ERR_OCCURRED__NOT_ACK = 0 -DP_AUX_ERR_OCCURRED__ACK = 1 -DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' -DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { - 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', - 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', -} -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 -DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' -DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { - 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', -} -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 -DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET' -DP_AUX_RESET__enumvalues = { - 0: 'DP_AUX_RESET_DEASSERTED', - 1: 'DP_AUX_RESET_ASSERTED', -} -DP_AUX_RESET_DEASSERTED = 0 -DP_AUX_RESET_ASSERTED = 1 -DP_AUX_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET_DONE' -DP_AUX_RESET_DONE__enumvalues = { - 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 1: 'DP_AUX_RESET_SEQUENCE_DONE', -} -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 -DP_AUX_RESET_SEQUENCE_DONE = 1 -DP_AUX_RESET_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_COMMAND_MODE_SRC_FORMAT' -DSI_COMMAND_MODE_SRC_FORMAT__enumvalues = { - 2: 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', - 3: 'DSI_COMMAND_SRC_FORMAT_RGB332', - 4: 'DSI_COMMAND_SRC_FORMAT_RGB444', - 5: 'DSI_COMMAND_SRC_FORMAT_RGB555', - 6: 'DSI_COMMAND_SRC_FORMAT_RGB565', - 8: 'DSI_COMMAND_SRC_FORMAT_RGB888', -} -DSI_COMMAND_SRC_FORMAT_RGB8BIT = 2 -DSI_COMMAND_SRC_FORMAT_RGB332 = 3 -DSI_COMMAND_SRC_FORMAT_RGB444 = 4 -DSI_COMMAND_SRC_FORMAT_RGB555 = 5 -DSI_COMMAND_SRC_FORMAT_RGB565 = 6 -DSI_COMMAND_SRC_FORMAT_RGB888 = 8 -DSI_COMMAND_MODE_SRC_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_COMMAND_MODE_DST_FORMAT' -DSI_COMMAND_MODE_DST_FORMAT__enumvalues = { - 0: 'DSI_COMMAND_DST_FORMAT_RGB111', - 3: 'DSI_COMMAND_DST_FORMAT_RGB332', - 4: 'DSI_COMMAND_DST_FORMAT_RGB444', - 6: 'DSI_COMMAND_DST_FORMAT_RGB565', - 7: 'DSI_COMMAND_DST_FORMAT_RGB666', - 8: 'DSI_COMMAND_DST_FORMAT_RGB888', -} -DSI_COMMAND_DST_FORMAT_RGB111 = 0 -DSI_COMMAND_DST_FORMAT_RGB332 = 3 -DSI_COMMAND_DST_FORMAT_RGB444 = 4 -DSI_COMMAND_DST_FORMAT_RGB565 = 6 -DSI_COMMAND_DST_FORMAT_RGB666 = 7 -DSI_COMMAND_DST_FORMAT_RGB888 = 8 -DSI_COMMAND_MODE_DST_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_FLAG_CLR' -DSI_FLAG_CLR__enumvalues = { - 0: 'DSI_FLAG_NO_CLEAR', - 1: 'DSI_FLAG_CLEAR', -} -DSI_FLAG_NO_CLEAR = 0 -DSI_FLAG_CLEAR = 1 -DSI_FLAG_CLR = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_BIT_SWAP' -DSI_BIT_SWAP__enumvalues = { - 0: 'DSI_BIT_SWAP_DISABLE', - 1: 'DSI_BIT_SWAP_ENABLE', -} -DSI_BIT_SWAP_DISABLE = 0 -DSI_BIT_SWAP_ENABLE = 1 -DSI_BIT_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CLK_GATING' -DSI_CLK_GATING__enumvalues = { - 0: 'DSI_CLK_GATING_ENABLE', - 1: 'DSI_CLK_GATING_DISABLE', -} -DSI_CLK_GATING_ENABLE = 0 -DSI_CLK_GATING_DISABLE = 1 -DSI_CLK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_LANE_ULPS_REQUEST' -DSI_LANE_ULPS_REQUEST__enumvalues = { - 0: 'DSI_LANE_ULPS_REQUEST_DEASSERT', - 1: 'DSI_LANE_ULPS_REQUEST_ASSERT', -} -DSI_LANE_ULPS_REQUEST_DEASSERT = 0 -DSI_LANE_ULPS_REQUEST_ASSERT = 1 -DSI_LANE_ULPS_REQUEST = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_LANE_ULPS_EXIT' -DSI_LANE_ULPS_EXIT__enumvalues = { - 0: 'DSI_LANE_ULPS_EXIT_DEASSERT', - 1: 'DSI_LANE_ULPS_EXIT_ASSERT', -} -DSI_LANE_ULPS_EXIT_DEASSERT = 0 -DSI_LANE_ULPS_EXIT_ASSERT = 1 -DSI_LANE_ULPS_EXIT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_LANE_FORCE_TX_STOP' -DSI_LANE_FORCE_TX_STOP__enumvalues = { - 0: 'DSI_LANE_FORCE_TX_STOP_DEASSERT', - 1: 'DSI_LANE_FORCE_TX_STOP_ASSERT', -} -DSI_LANE_FORCE_TX_STOP_DEASSERT = 0 -DSI_LANE_FORCE_TX_STOP_ASSERT = 1 -DSI_LANE_FORCE_TX_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CLOCK_LANE_HS_FORCE_REQUEST' -DSI_CLOCK_LANE_HS_FORCE_REQUEST__enumvalues = { - 0: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', - 1: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', -} -DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0 -DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 1 -DSI_CLOCK_LANE_HS_FORCE_REQUEST = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CONTROLLER_EN' -DSI_CONTROLLER_EN__enumvalues = { - 0: 'DSI_CONTROLLER_DISABLE', - 1: 'DSI_CONTROLLER_ENABLE', -} -DSI_CONTROLLER_DISABLE = 0 -DSI_CONTROLLER_ENABLE = 1 -DSI_CONTROLLER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_MODE_EN' -DSI_VIDEO_MODE_EN__enumvalues = { - 0: 'DSI_VIDEO_MODE_DISABLE', - 1: 'DSI_VIDEO_MODE_ENABLE', -} -DSI_VIDEO_MODE_DISABLE = 0 -DSI_VIDEO_MODE_ENABLE = 1 -DSI_VIDEO_MODE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CMD_MODE_EN' -DSI_CMD_MODE_EN__enumvalues = { - 0: 'DSI_CMD_MODE_DISABLE', - 1: 'DSI_CMD_MODE_ENABLE', -} -DSI_CMD_MODE_DISABLE = 0 -DSI_CMD_MODE_ENABLE = 1 -DSI_CMD_MODE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DATA_LANE0_EN' -DSI_DATA_LANE0_EN__enumvalues = { - 0: 'DSI_DATA_LANE0_DISABLE', - 1: 'DSI_DATA_LANE0_ENABLE', -} -DSI_DATA_LANE0_DISABLE = 0 -DSI_DATA_LANE0_ENABLE = 1 -DSI_DATA_LANE0_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DATA_LANE1_EN' -DSI_DATA_LANE1_EN__enumvalues = { - 0: 'DSI_DATA_LANE1_DISABLE', - 1: 'DSI_DATA_LANE1_ENABLE', -} -DSI_DATA_LANE1_DISABLE = 0 -DSI_DATA_LANE1_ENABLE = 1 -DSI_DATA_LANE1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DATA_LANE2_EN' -DSI_DATA_LANE2_EN__enumvalues = { - 0: 'DSI_DATA_LANE2_DISABLE', - 1: 'DSI_DATA_LANE2_ENABLE', -} -DSI_DATA_LANE2_DISABLE = 0 -DSI_DATA_LANE2_ENABLE = 1 -DSI_DATA_LANE2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DATA_LANE3_EN' -DSI_DATA_LANE3_EN__enumvalues = { - 0: 'DSI_DATA_LANE3_DISABLE', - 1: 'DSI_DATA_LANE3_ENABLE', -} -DSI_DATA_LANE3_DISABLE = 0 -DSI_DATA_LANE3_ENABLE = 1 -DSI_DATA_LANE3_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CLOCK_LANE_EN' -DSI_CLOCK_LANE_EN__enumvalues = { - 0: 'DSI_CLOCK_LANE_DISABLE', - 1: 'DSI_CLOCK_LANE_ENABLE', -} -DSI_CLOCK_LANE_DISABLE = 0 -DSI_CLOCK_LANE_ENABLE = 1 -DSI_CLOCK_LANE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PHY_DATA_LANE0_EN' -DSI_PHY_DATA_LANE0_EN__enumvalues = { - 0: 'DSI_PHY_DATA_LANE0_DISABLE', - 1: 'DSI_PHY_DATA_LANE0_ENABLE', -} -DSI_PHY_DATA_LANE0_DISABLE = 0 -DSI_PHY_DATA_LANE0_ENABLE = 1 -DSI_PHY_DATA_LANE0_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PHY_DATA_LANE1_EN' -DSI_PHY_DATA_LANE1_EN__enumvalues = { - 0: 'DSI_PHY_DATA_LANE1_DISABLE', - 1: 'DSI_PHY_DATA_LANE1_ENABLE', -} -DSI_PHY_DATA_LANE1_DISABLE = 0 -DSI_PHY_DATA_LANE1_ENABLE = 1 -DSI_PHY_DATA_LANE1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PHY_DATA_LANE2_EN' -DSI_PHY_DATA_LANE2_EN__enumvalues = { - 0: 'DSI_PHY_DATA_LANE2_DISABLE', - 1: 'DSI_PHY_DATA_LANE2_ENABLE', -} -DSI_PHY_DATA_LANE2_DISABLE = 0 -DSI_PHY_DATA_LANE2_ENABLE = 1 -DSI_PHY_DATA_LANE2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PHY_DATA_LANE3_EN' -DSI_PHY_DATA_LANE3_EN__enumvalues = { - 0: 'DSI_PHY_DATA_LANE3_DISABLE', - 1: 'DSI_PHY_DATA_LANE3_ENABLE', -} -DSI_PHY_DATA_LANE3_DISABLE = 0 -DSI_PHY_DATA_LANE3_ENABLE = 1 -DSI_PHY_DATA_LANE3_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RESET_DISPCLK' -DSI_RESET_DISPCLK__enumvalues = { - 0: 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', - 1: 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', -} -DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0 -DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 1 -DSI_RESET_DISPCLK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RESET_DSICLK' -DSI_RESET_DSICLK__enumvalues = { - 0: 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', - 1: 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', -} -DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0 -DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 1 -DSI_RESET_DSICLK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RESET_BYTECLK' -DSI_RESET_BYTECLK__enumvalues = { - 0: 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', - 1: 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', -} -DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0 -DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 1 -DSI_RESET_BYTECLK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RESET_ESCCLK' -DSI_RESET_ESCCLK__enumvalues = { - 0: 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', - 1: 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', -} -DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0 -DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 1 -DSI_RESET_ESCCLK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CRTC_SEL' -DSI_CRTC_SEL__enumvalues = { - 0: 'DSI_GET_PIXEL_STREAM_FROM_FMT0', - 1: 'DSI_GET_PIXEL_STREAM_FROM_FMT1', - 2: 'DSI_GET_PIXEL_STREAM_FROM_FMT2', - 3: 'DSI_GET_PIXEL_STREAM_FROM_FMT3', - 4: 'DSI_GET_PIXEL_STREAM_FROM_FMT4', - 5: 'DSI_GET_PIXEL_STREAM_FROM_FMT5', -} -DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0 -DSI_GET_PIXEL_STREAM_FROM_FMT1 = 1 -DSI_GET_PIXEL_STREAM_FROM_FMT2 = 2 -DSI_GET_PIXEL_STREAM_FROM_FMT3 = 3 -DSI_GET_PIXEL_STREAM_FROM_FMT4 = 4 -DSI_GET_PIXEL_STREAM_FROM_FMT5 = 5 -DSI_CRTC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PACKET_BYTE_MSB_LSB_FLIP' -DSI_PACKET_BYTE_MSB_LSB_FLIP__enumvalues = { - 0: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', - 1: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', -} -DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0 -DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 1 -DSI_PACKET_BYTE_MSB_LSB_FLIP = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_MODE_DST_FORMAT' -DSI_VIDEO_MODE_DST_FORMAT__enumvalues = { - 0: 'DSI_VIDEO_DST_FORMAT_RGB565', - 1: 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', - 2: 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', - 3: 'DSI_VIDEO_DST_FORMAT_RGB888', -} -DSI_VIDEO_DST_FORMAT_RGB565 = 0 -DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 1 -DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 2 -DSI_VIDEO_DST_FORMAT_RGB888 = 3 -DSI_VIDEO_MODE_DST_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_TRAFFIC_MODE' -DSI_VIDEO_TRAFFIC_MODE__enumvalues = { - 0: 'DSI_TRAFFIC_MODE_SYNC_PULSES', - 1: 'DSI_TRAFFIC_MODE_SYNC_EVENTS', - 2: 'DSI_TRAFFIC_MODE_BURST', - 3: 'DSI_TRAFFIC_MODE_RESERVED', -} -DSI_TRAFFIC_MODE_SYNC_PULSES = 0 -DSI_TRAFFIC_MODE_SYNC_EVENTS = 1 -DSI_TRAFFIC_MODE_BURST = 2 -DSI_TRAFFIC_MODE_RESERVED = 3 -DSI_VIDEO_TRAFFIC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_BLLP_PWR_MODE' -DSI_VIDEO_BLLP_PWR_MODE__enumvalues = { - 0: 'DSI_VIDEO_BLLP_PWR_MODE_HS', - 1: 'DSI_VIDEO_BLLP_PWR_MODE_LP', -} -DSI_VIDEO_BLLP_PWR_MODE_HS = 0 -DSI_VIDEO_BLLP_PWR_MODE_LP = 1 -DSI_VIDEO_BLLP_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_EOF_BLLP_PWR_MODE' -DSI_VIDEO_EOF_BLLP_PWR_MODE__enumvalues = { - 0: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', - 1: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', -} -DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0 -DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 1 -DSI_VIDEO_EOF_BLLP_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_PWR_MODE' -DSI_VIDEO_PWR_MODE__enumvalues = { - 0: 'DSI_VIDEO_PWR_MODE_HS', - 1: 'DSI_VIDEO_PWR_MODE_LP', -} -DSI_VIDEO_PWR_MODE_HS = 0 -DSI_VIDEO_PWR_MODE_LP = 1 -DSI_VIDEO_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_VIDEO_PULSE_MODE_OPT' -DSI_VIDEO_PULSE_MODE_OPT__enumvalues = { - 0: 'PULSE_MODE_OPT_NO_HSA', - 1: 'PULSE_MODE_OPT_SEND', -} -PULSE_MODE_OPT_NO_HSA = 0 -PULSE_MODE_OPT_SEND = 1 -DSI_VIDEO_PULSE_MODE_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RGB_SWAP' -DSI_RGB_SWAP__enumvalues = { - 0: 'DSI_SWAP_RGB', - 1: 'DSI_SWAP_RBG', - 2: 'DSI_SWAP_BGR', - 3: 'DSI_SWAP_BRG', - 4: 'DSI_SWAP_GRB', - 5: 'DSI_SWAP_GBR', -} -DSI_SWAP_RGB = 0 -DSI_SWAP_RBG = 1 -DSI_SWAP_BGR = 2 -DSI_SWAP_BRG = 3 -DSI_SWAP_GRB = 4 -DSI_SWAP_GBR = 5 -DSI_RGB_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CMD_PACKET_TYPE' -DSI_CMD_PACKET_TYPE__enumvalues = { - 0: 'DSI_CMD_PACKET_TYPE_SHORT', - 1: 'DSI_CMD_PACKET_TYPE_LONG', -} -DSI_CMD_PACKET_TYPE_SHORT = 0 -DSI_CMD_PACKET_TYPE_LONG = 1 -DSI_CMD_PACKET_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CMD_PWR_MODE' -DSI_CMD_PWR_MODE__enumvalues = { - 0: 'DSI_CMD_PWR_MODE_HS', - 1: 'DSI_CMD_PWR_MODE_LP', -} -DSI_CMD_PWR_MODE_HS = 0 -DSI_CMD_PWR_MODE_LP = 1 -DSI_CMD_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CMD_EMBEDDED_MODE' -DSI_CMD_EMBEDDED_MODE__enumvalues = { - 0: 'CMD_EMBEDDED_MODE_DISABLE', - 1: 'CMD_EMBEDDED_MODE_ENABLE', -} -CMD_EMBEDDED_MODE_DISABLE = 0 -CMD_EMBEDDED_MODE_ENABLE = 1 -DSI_CMD_EMBEDDED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CMD_ORDER' -DSI_CMD_ORDER__enumvalues = { - 0: 'DSI_CMD_ORDER_COMMAND_FIRST', - 1: 'DSI_CMD_ORDER_DATA_FIRST', -} -DSI_CMD_ORDER_COMMAND_FIRST = 0 -DSI_CMD_ORDER_DATA_FIRST = 1 -DSI_CMD_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DATA_BUFFER_ID' -DSI_DATA_BUFFER_ID__enumvalues = { - 0: 'DSI_DATA_BUFFER_OFFSET0', - 1: 'DSI_DATA_BUFFER_OFFSET1', -} -DSI_DATA_BUFFER_OFFSET0 = 0 -DSI_DATA_BUFFER_OFFSET1 = 1 -DSI_DATA_BUFFER_ID = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DWORD_BYTE_SWAP' -DSI_DWORD_BYTE_SWAP__enumvalues = { - 0: 'DWORD_BYTE_SWAP_NO_SWAP', - 1: 'DWORD_BYTE_SWAP_BYTE_SWAP', - 2: 'DWORD_BYTE_SWAP_WORD_SWAP', - 3: 'DWORD_BYTE_SWAP_BOTH_SWAP', -} -DWORD_BYTE_SWAP_NO_SWAP = 0 -DWORD_BYTE_SWAP_BYTE_SWAP = 1 -DWORD_BYTE_SWAP_WORD_SWAP = 2 -DWORD_BYTE_SWAP_BOTH_SWAP = 3 -DSI_DWORD_BYTE_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_INSERT_DCS_COMMAND' -DSI_INSERT_DCS_COMMAND__enumvalues = { - 0: 'DSI_INSERT_DCS_COMMAND_DISABLE', - 1: 'DSI_INSERT_DCS_COMMAND_ENABLE', -} -DSI_INSERT_DCS_COMMAND_DISABLE = 0 -DSI_INSERT_DCS_COMMAND_ENABLE = 1 -DSI_INSERT_DCS_COMMAND = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DMAFIFO_WRITE_WATERMARK' -DSI_DMAFIFO_WRITE_WATERMARK__enumvalues = { - 0: 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', - 1: 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', - 2: 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', - 3: 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', -} -DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0 -DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 1 -DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 2 -DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 3 -DSI_DMAFIFO_WRITE_WATERMARK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DMAFIFO_READ_WATERMARK' -DSI_DMAFIFO_READ_WATERMARK__enumvalues = { - 0: 'DSI_DMAFIFO_READ_WATERMARK_HALF', - 1: 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', - 2: 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', - 3: 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', -} -DSI_DMAFIFO_READ_WATERMARK_HALF = 0 -DSI_DMAFIFO_READ_WATERMARK_FOURTH = 1 -DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 2 -DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 3 -DSI_DMAFIFO_READ_WATERMARK = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_USE_DENG_LENGTH' -DSI_USE_DENG_LENGTH__enumvalues = { - 0: 'DSI_USE_DENG_LENGTH_DISABLE', - 1: 'DSI_USE_DENG_LENGTH_ENABLE', -} -DSI_USE_DENG_LENGTH_DISABLE = 0 -DSI_USE_DENG_LENGTH_ENABLE = 1 -DSI_USE_DENG_LENGTH = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_COMMAND_TRIGGER_MODE' -DSI_COMMAND_TRIGGER_MODE__enumvalues = { - 0: 'DSI_COMMAND_TRIGGER_MODE_AUTO', - 1: 'DSI_COMMAND_TRIGGER_MODE_MANUAL', -} -DSI_COMMAND_TRIGGER_MODE_AUTO = 0 -DSI_COMMAND_TRIGGER_MODE_MANUAL = 1 -DSI_COMMAND_TRIGGER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_COMMAND_TRIGGER_SEL' -DSI_COMMAND_TRIGGER_SEL__enumvalues = { - 0: 'DSI_COMMAND_TRIGGER_SEL_NONE', - 1: 'DSI_COMMAND_TRIGGER_SEL_CRTC', - 2: 'DSI_COMMAND_TRIGGER_SEL_TE', - 3: 'DSI_COMMAND_TRIGGER_SEL_HW', -} -DSI_COMMAND_TRIGGER_SEL_NONE = 0 -DSI_COMMAND_TRIGGER_SEL_CRTC = 1 -DSI_COMMAND_TRIGGER_SEL_TE = 2 -DSI_COMMAND_TRIGGER_SEL_HW = 3 -DSI_COMMAND_TRIGGER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_HW_SOURCE_SEL' -DSI_HW_SOURCE_SEL__enumvalues = { - 0: 'HW_SOURCE_SEL_NONE', - 1: 'HW_SOURCE_SEL_DSC_VUP', - 2: 'HW_SOURCE_SEL_DSC_VLP', - 3: 'HW_SOURCE_SEL_DSC_JPEG', -} -HW_SOURCE_SEL_NONE = 0 -HW_SOURCE_SEL_DSC_VUP = 1 -HW_SOURCE_SEL_DSC_VLP = 2 -HW_SOURCE_SEL_DSC_JPEG = 3 -DSI_HW_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_COMMAND_TRIGGER_ORDER' -DSI_COMMAND_TRIGGER_ORDER__enumvalues = { - 0: 'DSI_COMMAND_TRIGGER_ORDER_DMA', - 1: 'DSI_COMMAND_TRIGGER_ORDER_DENG', -} -DSI_COMMAND_TRIGGER_ORDER_DMA = 0 -DSI_COMMAND_TRIGGER_ORDER_DENG = 1 -DSI_COMMAND_TRIGGER_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_TE_SRC_SEL' -DSI_TE_SRC_SEL__enumvalues = { - 0: 'DSI_TE_SEL_LINK', - 1: 'DSI_TE_SEL_PIN', -} -DSI_TE_SEL_LINK = 0 -DSI_TE_SEL_PIN = 1 -DSI_TE_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_EXT_TE_MUX' -DSI_EXT_TE_MUX__enumvalues = { - 0: 'DSI_XT_TE_MUX_LCDD17', - 1: 'DSI_XT_TE_MUX_DCLK', - 2: 'DSI_XT_TE_MUX_SS', - 3: 'DSI_XT_TE_MUX_GCLK', - 4: 'DSI_XT_TE_MUX_GOE', - 5: 'DSI_XT_TE_MUX_DINV', - 6: 'DSI_XT_TE_MUX_FRAME', - 7: 'DSI_XT_TE_MUX_GPIO4', - 8: 'DSI_XT_TE_MUX_GPIO5', -} -DSI_XT_TE_MUX_LCDD17 = 0 -DSI_XT_TE_MUX_DCLK = 1 -DSI_XT_TE_MUX_SS = 2 -DSI_XT_TE_MUX_GCLK = 3 -DSI_XT_TE_MUX_GOE = 4 -DSI_XT_TE_MUX_DINV = 5 -DSI_XT_TE_MUX_FRAME = 6 -DSI_XT_TE_MUX_GPIO4 = 7 -DSI_XT_TE_MUX_GPIO5 = 8 -DSI_EXT_TE_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_EXT_TE_MODE' -DSI_EXT_TE_MODE__enumvalues = { - 0: 'DSI_EXT_TE_MODE_VSYNC_EDGE', - 1: 'DSI_EXT_TE_MODE_VSYNC_WIDTH', - 2: 'DSI_EXT_TE_MODE_HVSYNC_EDGE', - 3: 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', -} -DSI_EXT_TE_MODE_VSYNC_EDGE = 0 -DSI_EXT_TE_MODE_VSYNC_WIDTH = 1 -DSI_EXT_TE_MODE_HVSYNC_EDGE = 2 -DSI_EXT_TE_MODE_HVSYNC_WIDTH = 3 -DSI_EXT_TE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_EXT_RESET_POL' -DSI_EXT_RESET_POL__enumvalues = { - 0: 'DSI_EXT_RESET_POL_HIGH', - 1: 'DSI_EXT_RESET_POL_LOW', -} -DSI_EXT_RESET_POL_HIGH = 0 -DSI_EXT_RESET_POL_LOW = 1 -DSI_EXT_RESET_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_EXT_TE_POL' -DSI_EXT_TE_POL__enumvalues = { - 0: 'DSI_EXT_TE_POL_RISING', - 1: 'DSI_EXT_TE_POL_FALLING', -} -DSI_EXT_TE_POL_RISING = 0 -DSI_EXT_TE_POL_FALLING = 1 -DSI_EXT_TE_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RESET_PANEL' -DSI_RESET_PANEL__enumvalues = { - 0: 'DSI_RESET_PANEL_DEASSERT', - 1: 'DSI_RESET_PANEL_ASSERT', -} -DSI_RESET_PANEL_DEASSERT = 0 -DSI_RESET_PANEL_ASSERT = 1 -DSI_RESET_PANEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CRC_ENABLE' -DSI_CRC_ENABLE__enumvalues = { - 0: 'DSI_CRC_CAL_DISABLE', - 1: 'DSI_CRC_CAL_ENABLE', -} -DSI_CRC_CAL_DISABLE = 0 -DSI_CRC_CAL_ENABLE = 1 -DSI_CRC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_TX_EOT_APPEND' -DSI_TX_EOT_APPEND__enumvalues = { - 0: 'DSI_TX_EOT_APPEND_DISABLE', - 1: 'DSI_TX_EOT_APPEND_ENABLE', -} -DSI_TX_EOT_APPEND_DISABLE = 0 -DSI_TX_EOT_APPEND_ENABLE = 1 -DSI_TX_EOT_APPEND = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_RX_EOT_IGNORE' -DSI_RX_EOT_IGNORE__enumvalues = { - 0: 'DSI_RX_EOT_IGNORE_DISABLE', - 1: 'DSI_RX_EOT_IGNORE_ENABLE', -} -DSI_RX_EOT_IGNORE_DISABLE = 0 -DSI_RX_EOT_IGNORE_ENABLE = 1 -DSI_RX_EOT_IGNORE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_MIPI_BIST_RESET' -DSI_MIPI_BIST_RESET__enumvalues = { - 0: 'DSI_MIPI_BIST_RESET_DEASSERT', - 1: 'DSI_MIPI_BIST_RESET_ASSERT', -} -DSI_MIPI_BIST_RESET_DEASSERT = 0 -DSI_MIPI_BIST_RESET_ASSERT = 1 -DSI_MIPI_BIST_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_MIPI_BIST_VIDEO_FRMT' -DSI_MIPI_BIST_VIDEO_FRMT__enumvalues = { - 0: 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', - 1: 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', -} -DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0 -DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 1 -DSI_MIPI_BIST_VIDEO_FRMT = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_MIPI_BIST_START' -DSI_MIPI_BIST_START__enumvalues = { - 0: 'DSI_MIPI_BIST_START_DEASSERT', - 1: 'DSI_MIPI_BIST_START_ASSERT', -} -DSI_MIPI_BIST_START_DEASSERT = 0 -DSI_MIPI_BIST_START_ASSERT = 1 -DSI_MIPI_BIST_START = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DBG_CLK_SEL' -DSI_DBG_CLK_SEL__enumvalues = { - 0: 'DSI_TEST_CLK_SEL_DISPCLK_P', - 1: 'DSI_TEST_CLK_SEL_DISPCLK_G', - 2: 'DSI_TEST_CLK_SEL_DISPCLK_R', - 3: 'DSI_TEST_CLK_SEL_ESCCLK_G', - 4: 'DSI_TEST_CLK_SEL_BYTECLK_G', - 5: 'DSI_TEST_CLK_SEL_DSICLK_P', - 6: 'DSI_TEST_CLK_SEL_DSICLK_R', - 7: 'DSI_TEST_CLK_SEL_DSICLK_G', - 8: 'DSI_TEST_CLK_SEL_DSICLK_TRN', -} -DSI_TEST_CLK_SEL_DISPCLK_P = 0 -DSI_TEST_CLK_SEL_DISPCLK_G = 1 -DSI_TEST_CLK_SEL_DISPCLK_R = 2 -DSI_TEST_CLK_SEL_ESCCLK_G = 3 -DSI_TEST_CLK_SEL_BYTECLK_G = 4 -DSI_TEST_CLK_SEL_DSICLK_P = 5 -DSI_TEST_CLK_SEL_DSICLK_R = 6 -DSI_TEST_CLK_SEL_DSICLK_G = 7 -DSI_TEST_CLK_SEL_DSICLK_TRN = 8 -DSI_DBG_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL' -DSI_DENG_FIFO_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DSI_DENG_FIFO_LEVEL_OVERWRITE', - 1: 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', -} -DSI_DENG_FIFO_LEVEL_OVERWRITE = 0 -DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 1 -DSI_DENG_FIFO_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE' -DSI_DENG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', - 1: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', -} -DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0 -DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 1 -DSI_DENG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX' -DSI_DENG_FIFO_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', - 1: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', -} -DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0 -DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 1 -DSI_DENG_FIFO_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DENG_FIFO_START' -DSI_DENG_FIFO_START__enumvalues = { - 0: 'DSI_DENG_FIFO_START_DEASSERT', - 1: 'DSI_DENG_FIFO_START_ASSERT', -} -DSI_DENG_FIFO_START_DEASSERT = 0 -DSI_DENG_FIFO_START_ASSERT = 1 -DSI_DENG_FIFO_START = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_USE_CMDFIFO' -DSI_USE_CMDFIFO__enumvalues = { - 0: 'DSI_CMD_USE_DMAFIFO', - 1: 'DSI_CMD_USE_CMDFIFO', -} -DSI_CMD_USE_DMAFIFO = 0 -DSI_CMD_USE_CMDFIFO = 1 -DSI_USE_CMDFIFO = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_CRTC_FREEZE_TRIG' -DSI_CRTC_FREEZE_TRIG__enumvalues = { - 0: 'DSI_CRTC_FREEZE_TRIG_DEASSERT', - 1: 'DSI_CRTC_FREEZE_TRIG_ASSERT', -} -DSI_CRTC_FREEZE_TRIG_DEASSERT = 0 -DSI_CRTC_FREEZE_TRIG_ASSERT = 1 -DSI_CRTC_FREEZE_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_PERF_LATENCY_SEL' -DSI_PERF_LATENCY_SEL__enumvalues = { - 0: 'DSI_PERF_LATENCY_SEL_DATA_LANE0', - 1: 'DSI_PERF_LATENCY_SEL_DATA_LANE1', - 2: 'DSI_PERF_LATENCY_SEL_DATA_LANE2', - 3: 'DSI_PERF_LATENCY_SEL_DATA_LANE3', -} -DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0 -DSI_PERF_LATENCY_SEL_DATA_LANE1 = 1 -DSI_PERF_LATENCY_SEL_DATA_LANE2 = 2 -DSI_PERF_LATENCY_SEL_DATA_LANE3 = 3 -DSI_PERF_LATENCY_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DEBUG_DSICLK_SEL' -DSI_DEBUG_DSICLK_SEL__enumvalues = { - 0: 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', - 1: 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', - 2: 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', - 3: 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', - 4: 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', - 5: 'DSI_DEBUG_DSICLK_SEL_AFIFO', - 6: 'DSI_DEBUG_DSICLK_SEL_LANECTRL', -} -DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0 -DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 1 -DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 2 -DSI_DEBUG_DSICLK_SEL_CMDFIFO = 3 -DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 4 -DSI_DEBUG_DSICLK_SEL_AFIFO = 5 -DSI_DEBUG_DSICLK_SEL_LANECTRL = 6 -DSI_DEBUG_DSICLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSI_DEBUG_BYTECLK_SEL' -DSI_DEBUG_BYTECLK_SEL__enumvalues = { - 0: 'DSI_DEBUG_BYTECLK_SEL_AFIFO', - 1: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', - 2: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', - 3: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', - 4: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', - 5: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', - 6: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', - 7: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', - 8: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', - 9: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', - 10: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', - 11: 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', - 12: 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', - 13: 'DSI_DEBUG_BYTECLK_SEL_EOT', - 14: 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', -} -DSI_DEBUG_BYTECLK_SEL_AFIFO = 0 -DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 1 -DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 2 -DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 3 -DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 4 -DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 5 -DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 6 -DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 7 -DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 8 -DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 9 -DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 10 -DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 11 -DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 12 -DSI_DEBUG_BYTECLK_SEL_EOT = 13 -DSI_DEBUG_BYTECLK_SEL_LANECTRL = 14 -DSI_DEBUG_BYTECLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_HPD_SEL' -DCIOCHIP_HPD_SEL__enumvalues = { - 0: 'DCIOCHIP_HPD_SEL_ASYNC', - 1: 'DCIOCHIP_HPD_SEL_CLOCKED', -} -DCIOCHIP_HPD_SEL_ASYNC = 0 -DCIOCHIP_HPD_SEL_CLOCKED = 1 -DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PAD_MODE' -DCIOCHIP_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_PAD_MODE_DDC', - 1: 'DCIOCHIP_PAD_MODE_DP', -} -DCIOCHIP_PAD_MODE_DDC = 0 -DCIOCHIP_PAD_MODE_DP = 1 -DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' -DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', - 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', -} -DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 -DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 -DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_INVERT' -DCIOCHIP_INVERT__enumvalues = { - 0: 'DCIOCHIP_POL_NON_INVERT', - 1: 'DCIOCHIP_POL_INVERT', -} -DCIOCHIP_POL_NON_INVERT = 0 -DCIOCHIP_POL_INVERT = 1 -DCIOCHIP_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PD_EN' -DCIOCHIP_PD_EN__enumvalues = { - 0: 'DCIOCHIP_PD_EN_NOTALLOW', - 1: 'DCIOCHIP_PD_EN_ALLOW', -} -DCIOCHIP_PD_EN_NOTALLOW = 0 -DCIOCHIP_PD_EN_ALLOW = 1 -DCIOCHIP_PD_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' -DCIOCHIP_GPIO_MASK_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', -} -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 -DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK' -DCIOCHIP_MASK__enumvalues = { - 0: 'DCIOCHIP_MASK_DISABLE', - 1: 'DCIOCHIP_MASK_ENABLE', -} -DCIOCHIP_MASK_DISABLE = 0 -DCIOCHIP_MASK_ENABLE = 1 -DCIOCHIP_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' -DCIOCHIP_GPIO_I2C_MASK__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', - 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', -} -DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 -DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 -DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' -DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', - 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', -} -DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 -DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 -DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_I2C_EN' -DCIOCHIP_GPIO_I2C_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_I2C_DISABLE', - 1: 'DCIOCHIP_GPIO_I2C_ENABLE', -} -DCIOCHIP_GPIO_I2C_DISABLE = 0 -DCIOCHIP_GPIO_I2C_ENABLE = 1 -DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_4BIT' -DCIOCHIP_MASK_4BIT__enumvalues = { - 0: 'DCIOCHIP_MASK_4BIT_DISABLE', - 15: 'DCIOCHIP_MASK_4BIT_ENABLE', -} -DCIOCHIP_MASK_4BIT_DISABLE = 0 -DCIOCHIP_MASK_4BIT_ENABLE = 15 -DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_4BIT' -DCIOCHIP_ENABLE_4BIT__enumvalues = { - 0: 'DCIOCHIP_4BIT_DISABLE', - 15: 'DCIOCHIP_4BIT_ENABLE', -} -DCIOCHIP_4BIT_DISABLE = 0 -DCIOCHIP_4BIT_ENABLE = 15 -DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_5BIT' -DCIOCHIP_MASK_5BIT__enumvalues = { - 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', - 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', -} -DCIOCHIP_MASIK_5BIT_DISABLE = 0 -DCIOCHIP_MASIK_5BIT_ENABLE = 31 -DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_5BIT' -DCIOCHIP_ENABLE_5BIT__enumvalues = { - 0: 'DCIOCHIP_5BIT_DISABLE', - 31: 'DCIOCHIP_5BIT_ENABLE', -} -DCIOCHIP_5BIT_DISABLE = 0 -DCIOCHIP_5BIT_ENABLE = 31 -DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK_2BIT' -DCIOCHIP_MASK_2BIT__enumvalues = { - 0: 'DCIOCHIP_MASK_2BIT_DISABLE', - 3: 'DCIOCHIP_MASK_2BIT_ENABLE', -} -DCIOCHIP_MASK_2BIT_DISABLE = 0 -DCIOCHIP_MASK_2BIT_ENABLE = 3 -DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_ENABLE_2BIT' -DCIOCHIP_ENABLE_2BIT__enumvalues = { - 0: 'DCIOCHIP_2BIT_DISABLE', - 3: 'DCIOCHIP_2BIT_ENABLE', -} -DCIOCHIP_2BIT_DISABLE = 0 -DCIOCHIP_2BIT_ENABLE = 3 -DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' -DCIOCHIP_REF_27_SRC_SEL__enumvalues = { - 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', -} -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 -DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_DVO_VREFPON' -DCIOCHIP_DVO_VREFPON__enumvalues = { - 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', - 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', -} -DCIOCHIP_DVO_VREFPON_DISABLE = 0 -DCIOCHIP_DVO_VREFPON_ENABLE = 1 -DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_DVO_VREFSEL' -DCIOCHIP_DVO_VREFSEL__enumvalues = { - 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', - 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', -} -DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 -DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 -DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_SPDIF1_IMODE' -DCIOCHIP_SPDIF1_IMODE__enumvalues = { - 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', - 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', -} -DCIOCHIP_SPDIF1_IMODE_OE_A = 0 -DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 -DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' -DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', - 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', -} -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 -DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' -DCIOCHIP_AUX_SPIKESEL__enumvalues = { - 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', - 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', -} -DCIOCHIP_AUX_SPIKESEL_50NS = 0 -DCIOCHIP_AUX_SPIKESEL_10NS = 1 -DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' -DCIOCHIP_AUX_CSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', -} -DCIOCHIP_AUX_CSEL_DEC1P0 = 0 -DCIOCHIP_AUX_CSEL_DEC0P9 = 1 -DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' -DCIOCHIP_AUX_CSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_INC1P0', - 1: 'DCIOCHIP_AUX_CSEL_INC1P1', -} -DCIOCHIP_AUX_CSEL_INC1P0 = 0 -DCIOCHIP_AUX_CSEL_INC1P1 = 1 -DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' -DCIOCHIP_AUX_RSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', -} -DCIOCHIP_AUX_RSEL_DEC1P0 = 0 -DCIOCHIP_AUX_RSEL_DEC0P9 = 1 -DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' -DCIOCHIP_AUX_RSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_INC1P0', - 1: 'DCIOCHIP_AUX_RSEL_INC1P1', -} -DCIOCHIP_AUX_RSEL_INC1P0 = 0 -DCIOCHIP_AUX_RSEL_INC1P1 = 1 -DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_GLOBAL_CAPABILITIES' -AZ_GLOBAL_CAPABILITIES__enumvalues = { - 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', -} -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 -AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { - 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', - 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', -} -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' -GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { - 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 1: 'FLUSH_CONTROL_FLUSH_STARTED', -} -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 -FLUSH_CONTROL_FLUSH_STARTED = 1 -GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' -GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { - 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', -} -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 -GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_STATE_CHANGE_STATUS' -AZ_STATE_CHANGE_STATUS__enumvalues = { - 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', -} -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 -AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' -GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { - 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', -} -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 -GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_0_SYNCHRONIZATION' -STREAM_0_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_1_SYNCHRONIZATION' -STREAM_1_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_2_SYNCHRONIZATION' -STREAM_2_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_3_SYNCHRONIZATION' -STREAM_3_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_4_SYNCHRONIZATION' -STREAM_4_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_5_SYNCHRONIZATION' -STREAM_5_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_6_SYNCHRONIZATION' -STREAM_6_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_7_SYNCHRONIZATION' -STREAM_7_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_8_SYNCHRONIZATION' -STREAM_8_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_9_SYNCHRONIZATION' -STREAM_9_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_10_SYNCHRONIZATION' -STREAM_10_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_11_SYNCHRONIZATION' -STREAM_11_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_12_SYNCHRONIZATION' -STREAM_12_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_13_SYNCHRONIZATION' -STREAM_13_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_14_SYNCHRONIZATION' -STREAM_14_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_15_SYNCHRONIZATION' -STREAM_15_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'CORB_READ_POINTER_RESET' -CORB_READ_POINTER_RESET__enumvalues = { - 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', -} -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 -CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_CORB_SIZE' -AZ_CORB_SIZE__enumvalues = { - 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_CORB_SIZE_256ENTRIES', - 3: 'AZ_CORB_SIZE_RESERVED', -} -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 -AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 -AZ_CORB_SIZE_256ENTRIES = 2 -AZ_CORB_SIZE_RESERVED = 3 -AZ_CORB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' -AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { - 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', - 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', -} -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 -AZ_RIRB_WRITE_POINTER_DO_RESET = 1 -AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_SIZE' -AZ_RIRB_SIZE__enumvalues = { - 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_RIRB_SIZE_256ENTRIES', - 3: 'AZ_RIRB_SIZE_UNDEFINED', -} -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 -AZ_RIRB_SIZE_256ENTRIES = 2 -AZ_RIRB_SIZE_UNDEFINED = 3 -AZ_RIRB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum - -# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { - 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', -} -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { - 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', -} -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { - 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', -} -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE' -ENABLE__enumvalues = { - 0: 'DISABLE_THE_FEATURE', - 1: 'ENABLE_THE_FEATURE', -} -DISABLE_THE_FEATURE = 0 -ENABLE_THE_FEATURE = 1 -ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_CLOCK' -ENABLE_CLOCK__enumvalues = { - 0: 'DISABLE_THE_CLOCK', - 1: 'ENABLE_THE_CLOCK', -} -DISABLE_THE_CLOCK = 0 -ENABLE_THE_CLOCK = 1 -ENABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_VBI' -FORCE_VBI__enumvalues = { - 0: 'FORCE_VBI_LOW', - 1: 'FORCE_VBI_HIGH', -} -FORCE_VBI_LOW = 0 -FORCE_VBI_HIGH = 1 -FORCE_VBI = ctypes.c_uint32 # enum - -# values for enumeration 'OVERRIDE_CGTT_SCLK' -OVERRIDE_CGTT_SCLK__enumvalues = { - 0: 'OVERRIDE_CGTT_SCLK_NOOP', - 1: 'SET_OVERRIDE_CGTT_SCLK', -} -OVERRIDE_CGTT_SCLK_NOOP = 0 -SET_OVERRIDE_CGTT_SCLK = 1 -OVERRIDE_CGTT_SCLK = ctypes.c_uint32 # enum - -# values for enumeration 'CLEAR_SMU_INTR' -CLEAR_SMU_INTR__enumvalues = { - 0: 'SMU_INTR_STATUS_NOOP', - 1: 'SMU_INTR_STATUS_CLEAR', -} -SMU_INTR_STATUS_NOOP = 0 -SMU_INTR_STATUS_CLEAR = 1 -CLEAR_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'STATIC_SCREEN_SMU_INTR' -STATIC_SCREEN_SMU_INTR__enumvalues = { - 0: 'STATIC_SCREEN_SMU_INTR_NOOP', - 1: 'SET_STATIC_SCREEN_SMU_INTR', -} -STATIC_SCREEN_SMU_INTR_NOOP = 0 -SET_STATIC_SCREEN_SMU_INTR = 1 -STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'JITTER_REMOVE_DISABLE' -JITTER_REMOVE_DISABLE__enumvalues = { - 0: 'ENABLE_JITTER_REMOVAL', - 1: 'DISABLE_JITTER_REMOVAL', -} -ENABLE_JITTER_REMOVAL = 0 -DISABLE_JITTER_REMOVAL = 1 -JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_REF_SRC' -DS_REF_SRC__enumvalues = { - 0: 'DS_REF_IS_XTALIN', - 1: 'DS_REF_IS_EXT_GENLOCK', - 2: 'DS_REF_IS_PCIE', -} -DS_REF_IS_XTALIN = 0 -DS_REF_IS_EXT_GENLOCK = 1 -DS_REF_IS_PCIE = 2 -DS_REF_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING' -DISABLE_CLOCK_GATING__enumvalues = { - 0: 'CLOCK_GATING_ENABLED', - 1: 'CLOCK_GATING_DISABLED', -} -CLOCK_GATING_ENABLED = 0 -CLOCK_GATING_DISABLED = 1 -DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' -DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { - 0: 'CLOCK_GATING_ENABLED_IN_DCO', - 1: 'CLOCK_GATING_DISABLED_IN_DCO', -} -CLOCK_GATING_ENABLED_IN_DCO = 0 -CLOCK_GATING_DISABLED_IN_DCO = 1 -DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DEEP_COLOR_CNTL' -DCCG_DEEP_COLOR_CNTL__enumvalues = { - 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', - 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', - 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', -} -DCCG_DEEP_COLOR_DTO_DISABLE = 0 -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 -DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'REFCLK_CLOCK_EN' -REFCLK_CLOCK_EN__enumvalues = { - 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', - 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', -} -REFCLK_CLOCK_EN_XTALIN_CLK = 0 -REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 -REFCLK_CLOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'REFCLK_SRC_SEL' -REFCLK_SRC_SEL__enumvalues = { - 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', - 1: 'REFCLK_SRC_SEL_CPL_REFCLK', -} -REFCLK_SRC_SEL_PCIE_REFCLK = 0 -REFCLK_SRC_SEL_CPL_REFCLK = 1 -REFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPREFCLK_SRC_SEL' -DPREFCLK_SRC_SEL__enumvalues = { - 0: 'DPREFCLK_SRC_SEL_CK', - 1: 'DPREFCLK_SRC_SEL_P0PLL', - 2: 'DPREFCLK_SRC_SEL_P1PLL', - 3: 'DPREFCLK_SRC_SEL_P2PLL', - 4: 'DPREFCLK_SRC_SEL_P3PLL', -} -DPREFCLK_SRC_SEL_CK = 0 -DPREFCLK_SRC_SEL_P0PLL = 1 -DPREFCLK_SRC_SEL_P1PLL = 2 -DPREFCLK_SRC_SEL_P2PLL = 3 -DPREFCLK_SRC_SEL_P3PLL = 4 -DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_SEL' -XTAL_REF_SEL__enumvalues = { - 0: 'XTAL_REF_SEL_1X', - 1: 'XTAL_REF_SEL_2X', -} -XTAL_REF_SEL_1X = 0 -XTAL_REF_SEL_2X = 1 -XTAL_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' -XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', - 1: 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', -} -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 -XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 1 -XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', -} -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' -ALLOW_SR_ON_TRANS_REQ__enumvalues = { - 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', -} -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 -ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 -ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', -} -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' -PIPE_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', - 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', -} -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 -PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 -PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 -PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' -PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', - 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', - 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', -} -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 6 -PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' -PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', - 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', -} -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 -PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DTO_DS_DISABLE' -DP_DTO_DS_DISABLE__enumvalues = { - 0: 'DP_DTO_DESPREAD_DISABLE', - 1: 'DP_DTO_DESPREAD_ENABLE', -} -DP_DTO_DESPREAD_DISABLE = 0 -DP_DTO_DESPREAD_ENABLE = 1 -DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_ADD_PIXEL' -CRTC_ADD_PIXEL__enumvalues = { - 0: 'CRTC_ADD_PIXEL_NOOP', - 1: 'CRTC_ADD_PIXEL_FORCE', -} -CRTC_ADD_PIXEL_NOOP = 0 -CRTC_ADD_PIXEL_FORCE = 1 -CRTC_ADD_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRTC_DROP_PIXEL' -CRTC_DROP_PIXEL__enumvalues = { - 0: 'CRTC_DROP_PIXEL_NOOP', - 1: 'CRTC_DROP_PIXEL_FORCE', -} -CRTC_DROP_PIXEL_NOOP = 0 -CRTC_DROP_PIXEL_FORCE = 1 -CRTC_DROP_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_EN' -SYMCLK_FE_FORCE_EN__enumvalues = { - 0: 'SYMCLK_FE_FORCE_EN_DISABLE', - 1: 'SYMCLK_FE_FORCE_EN_ENABLE', -} -SYMCLK_FE_FORCE_EN_DISABLE = 0 -SYMCLK_FE_FORCE_EN_ENABLE = 1 -SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_SRC' -SYMCLK_FE_FORCE_SRC__enumvalues = { - 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', - 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', - 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', - 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', - 6: 'SYMCLK_FE_FORCE_SRC_UNIPHYG', -} -SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 -SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 -SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 -SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 -SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 -SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 -SYMCLK_FE_FORCE_SRC_UNIPHYG = 6 -SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_CLK_FORCE_EN' -DPDBG_CLK_FORCE_EN__enumvalues = { - 0: 'DPDBG_CLK_FORCE_EN_DISABLE', - 1: 'DPDBG_CLK_FORCE_EN_ENABLE', -} -DPDBG_CLK_FORCE_EN_DISABLE = 0 -DPDBG_CLK_FORCE_EN_ENABLE = 1 -DPDBG_CLK_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' -DVOACLK_COARSE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', -} -DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 -DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 -DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 -DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 -DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 -DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 -DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 -DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 -DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 -DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 -DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 -DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 -DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 -DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 -DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 -DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 -DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 -DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 -DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 -DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 -DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 -DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 -DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 -DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 -DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 -DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 -DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 -DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' -DVOACLK_FINE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', -} -DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 -DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 -DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 -DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 -DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKD_IN_PHASE' -DVOACLKD_IN_PHASE__enumvalues = { - 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_IN_PHASE' -DVOACLKC_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_IN_PHASE' -DVOACLKC_MVP_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { - 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', -} -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'MVP_CLK_SRC_SEL' -MVP_CLK_SRC_SEL__enumvalues = { - 0: 'MVP_CLK_SRC_SEL_RSRV', - 1: 'MVP_CLK_SRC_SEL_IO_1', - 2: 'MVP_CLK_SRC_SEL_IO_2', - 3: 'MVP_CLK_SRC_SEL_REFCLK', -} -MVP_CLK_SRC_SEL_RSRV = 0 -MVP_CLK_SRC_SEL_IO_1 = 1 -MVP_CLK_SRC_SEL_IO_2 = 2 -MVP_CLK_SRC_SEL_REFCLK = 3 -MVP_CLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' -DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', - 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', - 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', - 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', - 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', - 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', - 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', -} -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0 -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 1 -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 2 -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 3 -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 4 -DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 5 -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 -DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_SEL' -DCCG_AUDIO_DTO_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', - 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', -} -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 -DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' -DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', -} -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 -DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' -DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { - 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', -} -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 -DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_EN' -DCCG_DBG_EN__enumvalues = { - 0: 'DCCG_DBG_EN_DISABLE', - 1: 'DCCG_DBG_EN_ENABLE', -} -DCCG_DBG_EN_DISABLE = 0 -DCCG_DBG_EN_ENABLE = 1 -DCCG_DBG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_BLOCK_SEL' -DCCG_DBG_BLOCK_SEL__enumvalues = { - 0: 'DCCG_DBG_BLOCK_SEL_DCCG', - 1: 'DCCG_DBG_BLOCK_SEL_PMON', - 2: 'DCCG_DBG_BLOCK_SEL_PMON2', -} -DCCG_DBG_BLOCK_SEL_DCCG = 0 -DCCG_DBG_BLOCK_SEL_PMON = 1 -DCCG_DBG_BLOCK_SEL_PMON2 = 2 -DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' -DISPCLK_FREQ_RAMP_DONE__enumvalues = { - 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', - 1: 'DISPCLK_FREQ_RAMP_COMPLETED', -} -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 -DISPCLK_FREQ_RAMP_COMPLETED = 1 -DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_RESET' -DCCG_FIFO_ERRDET_RESET__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', - 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', -} -DCCG_FIFO_ERRDET_RESET_NOOP = 0 -DCCG_FIFO_ERRDET_RESET_FORCE = 1 -DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_STATE' -DCCG_FIFO_ERRDET_STATE__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_STATE_DETECTION', - 1: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', -} -DCCG_FIFO_ERRDET_STATE_DETECTION = 0 -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 1 -DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' -DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', - 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', -} -DCCG_FIFO_ERRDET_OVR_DISABLE = 0 -DCCG_FIFO_ERRDET_OVR_ENABLE = 1 -DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' -DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { - 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', -} -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 -DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' -DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { - 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', -} -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 -DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_RUN' -DCCG_PERF_RUN__enumvalues = { - 0: 'DCCG_PERF_RUN_NOOP', - 1: 'DCCG_PERF_RUN_START', -} -DCCG_PERF_RUN_NOOP = 0 -DCCG_PERF_RUN_START = 1 -DCCG_PERF_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_VSYNC' -DCCG_PERF_MODE_VSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_VSYNC_NOOP', - 1: 'DCCG_PERF_MODE_VSYNC_START', -} -DCCG_PERF_MODE_VSYNC_NOOP = 0 -DCCG_PERF_MODE_VSYNC_START = 1 -DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_HSYNC' -DCCG_PERF_MODE_HSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_HSYNC_NOOP', - 1: 'DCCG_PERF_MODE_HSYNC_START', -} -DCCG_PERF_MODE_HSYNC_NOOP = 0 -DCCG_PERF_MODE_HSYNC_START = 1 -DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_CRTC_SELECT' -DCCG_PERF_CRTC_SELECT__enumvalues = { - 0: 'DCCG_PERF_SEL_CRTC0', - 1: 'DCCG_PERF_SEL_CRTC1', - 2: 'DCCG_PERF_SEL_CRTC2', - 3: 'DCCG_PERF_SEL_CRTC3', - 4: 'DCCG_PERF_SEL_CRTC4', - 5: 'DCCG_PERF_SEL_CRTC5', -} -DCCG_PERF_SEL_CRTC0 = 0 -DCCG_PERF_SEL_CRTC1 = 1 -DCCG_PERF_SEL_CRTC2 = 2 -DCCG_PERF_SEL_CRTC3 = 3 -DCCG_PERF_SEL_CRTC4 = 4 -DCCG_PERF_SEL_CRTC5 = 5 -DCCG_PERF_CRTC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' -CLOCK_BRANCH_SOFT_RESET__enumvalues = { - 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', -} -CLOCK_BRANCH_SOFT_RESET_NOOP = 0 -CLOCK_BRANCH_SOFT_RESET_FORCE = 1 -CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'PLL_CFG_IF_SOFT_RESET' -PLL_CFG_IF_SOFT_RESET__enumvalues = { - 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', - 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', -} -PLL_CFG_IF_SOFT_RESET_NOOP = 0 -PLL_CFG_IF_SOFT_RESET_FORCE = 1 -PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_ENABLE_RST' -DVO_ENABLE_RST__enumvalues = { - 0: 'DVO_ENABLE_RST_DISABLE', - 1: 'DVO_ENABLE_RST_ENABLE', -} -DVO_ENABLE_RST_DISABLE = 0 -DVO_ENABLE_RST_ENABLE = 1 -DVO_ENABLE_RST = ctypes.c_uint32 # enum - -# values for enumeration 'LptNumPipes' -LptNumPipes__enumvalues = { - 0: 'LPT_NUM_PIPES_1CH', - 1: 'LPT_NUM_PIPES_2CH', - 2: 'LPT_NUM_PIPES_4CH', - 3: 'LPT_NUM_PIPES_8CH', -} -LPT_NUM_PIPES_1CH = 0 -LPT_NUM_PIPES_2CH = 1 -LPT_NUM_PIPES_4CH = 2 -LPT_NUM_PIPES_8CH = 3 -LptNumPipes = ctypes.c_uint32 # enum - -# values for enumeration 'LptNumBanks' -LptNumBanks__enumvalues = { - 0: 'LPT_NUM_BANKS_2BANK', - 1: 'LPT_NUM_BANKS_4BANK', - 2: 'LPT_NUM_BANKS_8BANK', - 3: 'LPT_NUM_BANKS_16BANK', - 4: 'LPT_NUM_BANKS_32BANK', -} -LPT_NUM_BANKS_2BANK = 0 -LPT_NUM_BANKS_4BANK = 1 -LPT_NUM_BANKS_8BANK = 2 -LPT_NUM_BANKS_16BANK = 3 -LPT_NUM_BANKS_32BANK = 4 -LptNumBanks = ctypes.c_uint32 # enum - -# values for enumeration 'OVERRIDE_CGTT_DCEFCLK' -OVERRIDE_CGTT_DCEFCLK__enumvalues = { - 0: 'OVERRIDE_CGTT_DCEFCLK_NOOP', - 1: 'SET_OVERRIDE_CGTT_DCEFCLK', -} -OVERRIDE_CGTT_DCEFCLK_NOOP = 0 -SET_OVERRIDE_CGTT_DCEFCLK = 1 -OVERRIDE_CGTT_DCEFCLK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICA_SEL' -DCIO_DC_GENERICA_SEL__enumvalues = { - 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', - 1: 'DCIO_GENERICA_SEL_STEREOSYNC', - 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', - 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', - 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', - 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', - 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', - 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', - 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', - 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', - 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 11: 'DCIO_GENERICA_SEL_SYNCEN', - 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', - 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', - 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', - 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', - 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', - 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', -} -DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 -DCIO_GENERICA_SEL_STEREOSYNC = 1 -DCIO_GENERICA_SEL_DACA_PIXCLK = 2 -DCIO_GENERICA_SEL_DACB_PIXCLK = 3 -DCIO_GENERICA_SEL_DVOA_CTL3 = 4 -DCIO_GENERICA_SEL_P1_PLLCLK = 5 -DCIO_GENERICA_SEL_P2_PLLCLK = 6 -DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 -DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 -DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 -DCIO_GENERICA_SEL_GENERICA_DCCG = 10 -DCIO_GENERICA_SEL_SYNCEN = 11 -DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 -DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 -DCIO_GENERICA_SEL_GENERICA_DPRX = 16 -DCIO_GENERICA_SEL_GENERICB_DPRX = 17 -DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', - 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', - 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', - 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', - 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', - 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', - 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', - 7: 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', - 8: 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', -} -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 -DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 -DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 -DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 -DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 -DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 -DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 -DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 7 -DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 8 -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_CLK', - 7: 'DCIO_UNIPHYLPA_FBDIV_CLK', - 8: 'DCIO_UNIPHYLPB_FBDIV_CLK', -} -DCIO_UNIPHYA_FBDIV_CLK = 0 -DCIO_UNIPHYB_FBDIV_CLK = 1 -DCIO_UNIPHYC_FBDIV_CLK = 2 -DCIO_UNIPHYD_FBDIV_CLK = 3 -DCIO_UNIPHYE_FBDIV_CLK = 4 -DCIO_UNIPHYF_FBDIV_CLK = 5 -DCIO_UNIPHYG_FBDIV_CLK = 6 -DCIO_UNIPHYLPA_FBDIV_CLK = 7 -DCIO_UNIPHYLPB_FBDIV_CLK = 8 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', - 7: 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', - 8: 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', -} -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 -DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 -DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 -DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 -DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 -DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 -DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 -DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 7 -DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 8 -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 7: 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', - 8: 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', -} -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 -DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 7 -DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 8 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICB_SEL' -DCIO_DC_GENERICB_SEL__enumvalues = { - 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', - 1: 'DCIO_GENERICB_SEL_STEREOSYNC', - 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', - 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', - 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', - 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', - 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', - 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', - 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', - 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', - 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 11: 'DCIO_GENERICB_SEL_SYNCEN', - 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', - 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', - 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', - 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', -} -DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 -DCIO_GENERICB_SEL_STEREOSYNC = 1 -DCIO_GENERICB_SEL_DACA_PIXCLK = 2 -DCIO_GENERICB_SEL_DACB_PIXCLK = 3 -DCIO_GENERICB_SEL_DVOA_CTL3 = 4 -DCIO_GENERICB_SEL_P1_PLLCLK = 5 -DCIO_GENERICB_SEL_P2_PLLCLK = 6 -DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 -DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 -DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 -DCIO_GENERICB_SEL_GENERICB_DCCG = 10 -DCIO_GENERICB_SEL_SYNCEN = 11 -DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 -DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 -DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_SEL' -DCIO_DC_PAD_EXTERN_SIG_SEL__enumvalues = { - 0: 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', - 1: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', - 2: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', - 3: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', - 4: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', - 5: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', - 6: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', - 7: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', - 8: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', - 9: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', - 10: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', - 11: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', - 12: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', - 13: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', - 14: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', - 15: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', -} -DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0 -DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 1 -DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 2 -DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 3 -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 4 -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 5 -DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 6 -DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 7 -DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 8 -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 9 -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 10 -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 11 -DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 12 -DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 13 -DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 14 -DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 15 -DCIO_DC_PAD_EXTERN_SIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS' -DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS__enumvalues = { - 0: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', - 1: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', - 2: 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', - 3: 'DCIO_MVP_PIXEL_SRC_STATUS_LB', -} -DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0 -DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 1 -DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 2 -DCIO_MVP_PIXEL_SRC_STATUS_LB = 3 -DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', - 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', -} -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', -} -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_VIP_DEBUG' -DCIO_DC_GPIO_VIP_DEBUG__enumvalues = { - 0: 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', - 1: 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', -} -DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0 -DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 1 -DCIO_DC_GPIO_VIP_DEBUG = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_MACRO_DEBUG' -DCIO_DC_GPIO_MACRO_DEBUG__enumvalues = { - 0: 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', - 1: 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', - 2: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', - 3: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', -} -DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0 -DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 1 -DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 2 -DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 3 -DCIO_DC_GPIO_MACRO_DEBUG = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL' -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__enumvalues = { - 0: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', - 1: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', -} -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0 -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 1 -DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN' -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN__enumvalues = { - 0: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', - 1: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', -} -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0 -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 1 -DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { - 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', - 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', -} -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' -DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { - 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', - 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', - 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', - 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', - 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', - 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', - 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', - 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', -} -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 -DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 -DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', -} -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 -DCIO_UNIPHY_CHANNEL_INVERTED = 1 -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { - 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', -} -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', -} -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' -DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { - 0: 'DCIO_VIP_MUX_EN_DVO', - 1: 'DCIO_VIP_MUX_EN_VIP', -} -DCIO_VIP_MUX_EN_DVO = 0 -DCIO_VIP_MUX_EN_VIP = 1 -DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' -DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { - 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', - 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', -} -DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 -DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 -DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' -DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { - 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', - 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', -} -DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 -DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 -DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' -DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { - 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', - 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', -} -DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 -DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 -DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' -DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { - 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', - 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', -} -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 -DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { - 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', - 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', -} -DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 -DCIO_LVTMA_SYNCEN_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { - 0: 'DCIO_LVTMA_DIGON_OFF', - 1: 'DCIO_LVTMA_DIGON_ON', -} -DCIO_LVTMA_DIGON_OFF = 0 -DCIO_LVTMA_DIGON_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { - 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', - 1: 'DCIO_LVTMA_DIGON_POL_INVERT', -} -DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 -DCIO_LVTMA_DIGON_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { - 0: 'DCIO_LVTMA_BLON_OFF', - 1: 'DCIO_LVTMA_BLON_ON', -} -DCIO_LVTMA_BLON_OFF = 0 -DCIO_LVTMA_BLON_ON = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { - 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', - 1: 'DCIO_LVTMA_BLON_POL_INVERT', -} -DCIO_LVTMA_BLON_POL_NON_INVERT = 0 -DCIO_LVTMA_BLON_POL_INVERT = 1 -DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' -DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { - 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', - 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', -} -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 -DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 -DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' -DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { - 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', - 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', -} -DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 -DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 -DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' -DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { - 0: 'DCIO_BL_PWM_DISABLE', - 1: 'DCIO_BL_PWM_ENABLE', -} -DCIO_BL_PWM_DISABLE = 0 -DCIO_BL_PWM_ENABLE = 1 -DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' -DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { - 0: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 1: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 2: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 3: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', -} -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 -DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 -DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { - 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', -} -DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 -DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { - 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', - 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', -} -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 -DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 -DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' -DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', - 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', -} -DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 -DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 -DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', -} -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 -DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', -} -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', -} -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 -DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', -} -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 -DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_SEL' -DCIO_GSL_SEL__enumvalues = { - 0: 'DCIO_GSL_SEL_GROUP_0', - 1: 'DCIO_GSL_SEL_GROUP_1', - 2: 'DCIO_GSL_SEL_GROUP_2', -} -DCIO_GSL_SEL_GROUP_0 = 0 -DCIO_GSL_SEL_GROUP_1 = 1 -DCIO_GSL_SEL_GROUP_2 = 2 -DCIO_GSL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' -DCIO_GENLK_CLK_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', - 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', -} -DCIO_GENLK_CLK_GSL_MASK_NO = 0 -DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 -DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 -DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' -DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', -} -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 -DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' -DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' -DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_VSYNC_SEL' -DCIO_GSL_VSYNC_SEL__enumvalues = { - 0: 'DCIO_GSL_VSYNC_SEL_PIPE0', - 1: 'DCIO_GSL_VSYNC_SEL_PIPE1', - 2: 'DCIO_GSL_VSYNC_SEL_PIPE2', - 3: 'DCIO_GSL_VSYNC_SEL_PIPE3', - 4: 'DCIO_GSL_VSYNC_SEL_PIPE4', - 5: 'DCIO_GSL_VSYNC_SEL_PIPE5', -} -DCIO_GSL_VSYNC_SEL_PIPE0 = 0 -DCIO_GSL_VSYNC_SEL_PIPE1 = 1 -DCIO_GSL_VSYNC_SEL_PIPE2 = 2 -DCIO_GSL_VSYNC_SEL_PIPE3 = 3 -DCIO_GSL_VSYNC_SEL_PIPE4 = 4 -DCIO_GSL_VSYNC_SEL_PIPE5 = 5 -DCIO_GSL_VSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL0_TIMING_SYNC_SEL' -DCIO_GSL0_TIMING_SYNC_SEL__enumvalues = { - 0: 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', - 1: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', - 3: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', -} -DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0 -DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 -DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 2 -DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 3 -DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 4 -DCIO_GSL0_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL0_GLOBAL_UNLOCK_SEL' -DCIO_GSL0_GLOBAL_UNLOCK_SEL__enumvalues = { - 0: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', - 1: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 3: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', -} -DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0 -DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 -DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 -DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 -DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 -DCIO_GSL0_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL1_TIMING_SYNC_SEL' -DCIO_GSL1_TIMING_SYNC_SEL__enumvalues = { - 0: 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', - 1: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', - 3: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', -} -DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0 -DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 -DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 2 -DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 3 -DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 4 -DCIO_GSL1_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL1_GLOBAL_UNLOCK_SEL' -DCIO_GSL1_GLOBAL_UNLOCK_SEL__enumvalues = { - 0: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', - 1: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 3: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', -} -DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0 -DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 -DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 -DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 -DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 -DCIO_GSL1_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL2_TIMING_SYNC_SEL' -DCIO_GSL2_TIMING_SYNC_SEL__enumvalues = { - 0: 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', - 1: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', - 3: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', -} -DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0 -DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 -DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 2 -DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 3 -DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 4 -DCIO_GSL2_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL2_GLOBAL_UNLOCK_SEL' -DCIO_GSL2_GLOBAL_UNLOCK_SEL__enumvalues = { - 0: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', - 1: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 2: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 3: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 4: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', -} -DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0 -DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 -DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 -DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 -DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 -DCIO_GSL2_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' -DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DCIO_GPU_TIMER_START_0_END_27', - 1: 'DCIO_GPU_TIMER_START_1_END_28', - 2: 'DCIO_GPU_TIMER_START_2_END_29', - 3: 'DCIO_GPU_TIMER_START_3_END_30', - 4: 'DCIO_GPU_TIMER_START_4_END_31', - 5: 'DCIO_GPU_TIMER_START_6_END_33', - 6: 'DCIO_GPU_TIMER_START_8_END_35', - 7: 'DCIO_GPU_TIMER_START_10_END_37', -} -DCIO_GPU_TIMER_START_0_END_27 = 0 -DCIO_GPU_TIMER_START_1_END_28 = 1 -DCIO_GPU_TIMER_START_2_END_29 = 2 -DCIO_GPU_TIMER_START_3_END_30 = 3 -DCIO_GPU_TIMER_START_4_END_31 = 4 -DCIO_GPU_TIMER_START_6_END_33 = 5 -DCIO_GPU_TIMER_START_8_END_35 = 6 -DCIO_GPU_TIMER_START_10_END_37 = 7 -DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { - 0: 'DCIO_TEST_CLK_SEL_DISPCLK', - 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', - 2: 'DCIO_TEST_CLK_SEL_SCLK', -} -DCIO_TEST_CLK_SEL_DISPCLK = 0 -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 -DCIO_TEST_CLK_SEL_SCLK = 2 -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { - 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', -} -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCO_DCFE_EXT_VSYNC_MUX' -DCIO_DCO_DCFE_EXT_VSYNC_MUX__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 1: 'DCIO_EXT_VSYNC_MUX_CRTC0', - 2: 'DCIO_EXT_VSYNC_MUX_CRTC1', - 3: 'DCIO_EXT_VSYNC_MUX_CRTC2', - 4: 'DCIO_EXT_VSYNC_MUX_CRTC3', - 5: 'DCIO_EXT_VSYNC_MUX_CRTC4', - 6: 'DCIO_EXT_VSYNC_MUX_CRTC5', - 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', -} -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 -DCIO_EXT_VSYNC_MUX_CRTC0 = 1 -DCIO_EXT_VSYNC_MUX_CRTC1 = 2 -DCIO_EXT_VSYNC_MUX_CRTC2 = 3 -DCIO_EXT_VSYNC_MUX_CRTC3 = 4 -DCIO_EXT_VSYNC_MUX_CRTC4 = 5 -DCIO_EXT_VSYNC_MUX_CRTC5 = 6 -DCIO_EXT_VSYNC_MUX_GENERICB = 7 -DCIO_DCO_DCFE_EXT_VSYNC_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCO_EXT_VSYNC_MASK' -DCIO_DCO_EXT_VSYNC_MASK__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MASK_NONE', - 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', - 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', - 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', - 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', - 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', - 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', - 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', -} -DCIO_EXT_VSYNC_MASK_NONE = 0 -DCIO_EXT_VSYNC_MASK_PIPE0 = 1 -DCIO_EXT_VSYNC_MASK_PIPE1 = 2 -DCIO_EXT_VSYNC_MASK_PIPE2 = 3 -DCIO_EXT_VSYNC_MASK_PIPE3 = 4 -DCIO_EXT_VSYNC_MASK_PIPE4 = 5 -DCIO_EXT_VSYNC_MASK_PIPE5 = 6 -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 -DCIO_DCO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DSYNC_SOFT_RESET' -DCIO_DSYNC_SOFT_RESET__enumvalues = { - 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', -} -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 -DCIO_DSYNC_SOFT_RESET_ASSERT = 1 -DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DACA_SOFT_RESET' -DCIO_DACA_SOFT_RESET__enumvalues = { - 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', - 1: 'DCIO_DACA_SOFT_RESET_ASSERT', -} -DCIO_DACA_SOFT_RESET_DEASSERT = 0 -DCIO_DACA_SOFT_RESET_ASSERT = 1 -DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' -DCIO_DCRXPHY_SOFT_RESET__enumvalues = { - 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', -} -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 -DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPHY_LANE_SEL' -DCIO_DPHY_LANE_SEL__enumvalues = { - 0: 'DCIO_DPHY_LANE_SEL_LANE0', - 1: 'DCIO_DPHY_LANE_SEL_LANE1', - 2: 'DCIO_DPHY_LANE_SEL_LANE2', - 3: 'DCIO_DPHY_LANE_SEL_LANE3', -} -DCIO_DPHY_LANE_SEL_LANE0 = 0 -DCIO_DPHY_LANE_SEL_LANE1 = 1 -DCIO_DPHY_LANE_SEL_LANE2 = 2 -DCIO_DPHY_LANE_SEL_LANE3 = 3 -DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' -DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', -} -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 -DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' -DCIO_DPCS_INTERRUPT_MASK__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_DISABLE', - 1: 'DCIO_DPCS_INTERRUPT_ENABLE', -} -DCIO_DPCS_INTERRUPT_DISABLE = 0 -DCIO_DPCS_INTERRUPT_ENABLE = 1 -DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' -DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', - 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', - 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', - 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', - 6: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', - 7: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', - 8: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', - 9: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', - 10: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', - 11: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', - 12: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 13: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 14: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', - 15: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', - 16: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', - 17: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', - 18: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', - 19: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', - 20: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', - 21: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', - 22: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', - 23: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', - 24: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 25: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 26: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', - 27: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', - 28: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', - 29: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', - 30: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', - 31: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', - 32: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', - 33: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', - 34: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', - 35: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', -} -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 2 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 3 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 4 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 5 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 6 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 7 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 8 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 9 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 10 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 11 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 12 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 13 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 14 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 15 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 16 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 17 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 18 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 19 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 20 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 21 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 22 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 23 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 24 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 25 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 26 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 27 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 28 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 29 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 30 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 31 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 32 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 33 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 34 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 35 -DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_IMPCAL_STEP_DELAY' -DCIO_IMPCAL_STEP_DELAY__enumvalues = { - 0: 'DCIO_IMPCAL_STEP_DELAY_1us', - 1: 'DCIO_IMPCAL_STEP_DELAY_2us', - 2: 'DCIO_IMPCAL_STEP_DELAY_3us', - 3: 'DCIO_IMPCAL_STEP_DELAY_4us', - 4: 'DCIO_IMPCAL_STEP_DELAY_5us', - 5: 'DCIO_IMPCAL_STEP_DELAY_6us', - 6: 'DCIO_IMPCAL_STEP_DELAY_7us', - 7: 'DCIO_IMPCAL_STEP_DELAY_8us', - 8: 'DCIO_IMPCAL_STEP_DELAY_9us', - 9: 'DCIO_IMPCAL_STEP_DELAY_10us', - 10: 'DCIO_IMPCAL_STEP_DELAY_11us', - 11: 'DCIO_IMPCAL_STEP_DELAY_12us', - 12: 'DCIO_IMPCAL_STEP_DELAY_13us', - 13: 'DCIO_IMPCAL_STEP_DELAY_14us', - 14: 'DCIO_IMPCAL_STEP_DELAY_15us', - 15: 'DCIO_IMPCAL_STEP_DELAY_16us', -} -DCIO_IMPCAL_STEP_DELAY_1us = 0 -DCIO_IMPCAL_STEP_DELAY_2us = 1 -DCIO_IMPCAL_STEP_DELAY_3us = 2 -DCIO_IMPCAL_STEP_DELAY_4us = 3 -DCIO_IMPCAL_STEP_DELAY_5us = 4 -DCIO_IMPCAL_STEP_DELAY_6us = 5 -DCIO_IMPCAL_STEP_DELAY_7us = 6 -DCIO_IMPCAL_STEP_DELAY_8us = 7 -DCIO_IMPCAL_STEP_DELAY_9us = 8 -DCIO_IMPCAL_STEP_DELAY_10us = 9 -DCIO_IMPCAL_STEP_DELAY_11us = 10 -DCIO_IMPCAL_STEP_DELAY_12us = 11 -DCIO_IMPCAL_STEP_DELAY_13us = 12 -DCIO_IMPCAL_STEP_DELAY_14us = 13 -DCIO_IMPCAL_STEP_DELAY_15us = 14 -DCIO_IMPCAL_STEP_DELAY_16us = 15 -DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' -DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { - 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', -} -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 -DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' -DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', - 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', - 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', -} -DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 -DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 -DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 -DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 3 -DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' -DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', - 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', -} -DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 -DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 -DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 -DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 -DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 -DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 -DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 -DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 -DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AOUT_EN' -AOUT_EN__enumvalues = { - 0: 'AOUT_DISABLE', - 1: 'AOUT_ENABLE', -} -AOUT_DISABLE = 0 -AOUT_ENABLE = 1 -AOUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AOUT_FIFO_START_ADDR' -AOUT_FIFO_START_ADDR__enumvalues = { - 0: 'AOUT_FIFO_START_ADDR_2', - 1: 'AOUT_FIFO_START_ADDR_3', -} -AOUT_FIFO_START_ADDR_2 = 0 -AOUT_FIFO_START_ADDR_3 = 1 -AOUT_FIFO_START_ADDR = ctypes.c_uint32 # enum - -# values for enumeration 'AOUT_CRC_TEST_EN' -AOUT_CRC_TEST_EN__enumvalues = { - 0: 'AOUT_CRC_DISABLE', - 1: 'AOUT_CRC_ENABLE', -} -AOUT_CRC_DISABLE = 0 -AOUT_CRC_ENABLE = 1 -AOUT_CRC_TEST_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AOUT_CRC_SOFT_RESET' -AOUT_CRC_SOFT_RESET__enumvalues = { - 0: 'AOUT_CRC_NO_RESET', - 1: 'AOUT_CRC_RESET', -} -AOUT_CRC_NO_RESET = 0 -AOUT_CRC_RESET = 1 -AOUT_CRC_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AOUT_CRC_CONT_EN' -AOUT_CRC_CONT_EN__enumvalues = { - 0: 'AOUT_CRC_ONE_SHOT', - 1: 'AOUT_CRC_CONT', -} -AOUT_CRC_ONE_SHOT = 0 -AOUT_CRC_CONT = 1 -AOUT_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'I2S_WORD_SIZE' -I2S_WORD_SIZE__enumvalues = { - 0: 'I2S_WORD_SIZE_32', - 1: 'I2S_WORD_SIZE_16', -} -I2S_WORD_SIZE_32 = 0 -I2S_WORD_SIZE_16 = 1 -I2S_WORD_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'I2S_SAMPLE_ALIGNMENT' -I2S_SAMPLE_ALIGNMENT__enumvalues = { - 0: 'I2S_SAMPLE_LEFT_ALIGNED', - 1: 'I2S_SAMPLE_RIGHT_ALIGNED', -} -I2S_SAMPLE_LEFT_ALIGNED = 0 -I2S_SAMPLE_RIGHT_ALIGNED = 1 -I2S_SAMPLE_ALIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'I2S_SAMPLE_BIT_ORDER' -I2S_SAMPLE_BIT_ORDER__enumvalues = { - 0: 'I2S_SAMPLE_BIT_ORDER_MSB', - 1: 'I2S_SAMPLE_BIT_ORDER_LSB', -} -I2S_SAMPLE_BIT_ORDER_MSB = 0 -I2S_SAMPLE_BIT_ORDER_LSB = 1 -I2S_SAMPLE_BIT_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'I2S_LRCLK_POLARITY' -I2S_LRCLK_POLARITY__enumvalues = { - 0: 'I2S_LRCLK_LOW_LEFT', - 1: 'I2S_LRCLK_HIGH_LEFT', -} -I2S_LRCLK_LOW_LEFT = 0 -I2S_LRCLK_HIGH_LEFT = 1 -I2S_LRCLK_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'I2S_WORD_ALIGNMENT' -I2S_WORD_ALIGNMENT__enumvalues = { - 0: 'I2S_WORD_ALTERNATE_ALIGNMENT', - 1: 'I2S_WORD_I2S_ALIGNMENT', -} -I2S_WORD_ALTERNATE_ALIGNMENT = 0 -I2S_WORD_I2S_ALIGNMENT = 1 -I2S_WORD_ALIGNMENT = ctypes.c_uint32 # enum - -# values for enumeration 'SPDIF_INVERT_EN' -SPDIF_INVERT_EN__enumvalues = { - 0: 'SPDIF_INVERT_DISABLE', - 1: 'SPDIF_INVERT_ENABLE', -} -SPDIF_INVERT_DISABLE = 0 -SPDIF_INVERT_ENABLE = 1 -SPDIF_INVERT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_EN' -DPDBG_EN__enumvalues = { - 0: 'DPDBG_DISABLE', - 1: 'DPDBG_ENABLE', -} -DPDBG_DISABLE = 0 -DPDBG_ENABLE = 1 -DPDBG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_INPUT_EN' -DPDBG_INPUT_EN__enumvalues = { - 0: 'DPDBG_INPUT_DISABLE', - 1: 'DPDBG_INPUT_ENABLE', -} -DPDBG_INPUT_DISABLE = 0 -DPDBG_INPUT_ENABLE = 1 -DPDBG_INPUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_ERROR_DETECTION_MODE' -DPDBG_ERROR_DETECTION_MODE__enumvalues = { - 0: 'DPDBG_ERROR_DETECTION_MODE_CSC', - 1: 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', -} -DPDBG_ERROR_DETECTION_MODE_CSC = 0 -DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 1 -DPDBG_ERROR_DETECTION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK' -DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK__enumvalues = { - 0: 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', - 1: 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', -} -DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0 -DPDBG_FIFO_OVERFLOW_INT_ENABLE = 1 -DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE' -DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE__enumvalues = { - 0: 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', - 1: 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', -} -DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0 -DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 1 -DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK' -DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK__enumvalues = { - 0: 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', - 1: 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', -} -DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0 -DPDBG_FIFO_OVERFLOW_INT_CLEAR = 1 -DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'PM_ASSERT_RESET' -PM_ASSERT_RESET__enumvalues = { - 0: 'PM_ASSERT_RESET_0', - 1: 'PM_ASSERT_RESET_1', -} -PM_ASSERT_RESET_0 = 0 -PM_ASSERT_RESET_1 = 1 -PM_ASSERT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DAC_MUX_SELECT' -DAC_MUX_SELECT__enumvalues = { - 0: 'DAC_MUX_SELECT_DACA', - 1: 'DAC_MUX_SELECT_DACB', -} -DAC_MUX_SELECT_DACA = 0 -DAC_MUX_SELECT_DACB = 1 -DAC_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DVO_MUX_SELECT' -TMDS_DVO_MUX_SELECT__enumvalues = { - 0: 'TMDS_DVO_MUX_SELECT_B', - 1: 'TMDS_DVO_MUX_SELECT_G', - 2: 'TMDS_DVO_MUX_SELECT_R', - 3: 'TMDS_DVO_MUX_SELECT_RESERVED', -} -TMDS_DVO_MUX_SELECT_B = 0 -TMDS_DVO_MUX_SELECT_G = 1 -TMDS_DVO_MUX_SELECT_R = 2 -TMDS_DVO_MUX_SELECT_RESERVED = 3 -TMDS_DVO_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DACA_SOFT_RESET' -DACA_SOFT_RESET__enumvalues = { - 0: 'DACA_SOFT_RESET_0', - 1: 'DACA_SOFT_RESET_1', -} -DACA_SOFT_RESET_0 = 0 -DACA_SOFT_RESET_1 = 1 -DACA_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'I2S0_SPDIF0_SOFT_RESET' -I2S0_SPDIF0_SOFT_RESET__enumvalues = { - 0: 'I2S0_SPDIF0_SOFT_RESET_0', - 1: 'I2S0_SPDIF0_SOFT_RESET_1', -} -I2S0_SPDIF0_SOFT_RESET_0 = 0 -I2S0_SPDIF0_SOFT_RESET_1 = 1 -I2S0_SPDIF0_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'I2S1_SOFT_RESET' -I2S1_SOFT_RESET__enumvalues = { - 0: 'I2S1_SOFT_RESET_0', - 1: 'I2S1_SOFT_RESET_1', -} -I2S1_SOFT_RESET_0 = 0 -I2S1_SOFT_RESET_1 = 1 -I2S1_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SPDIF1_SOFT_RESET' -SPDIF1_SOFT_RESET__enumvalues = { - 0: 'SPDIF1_SOFT_RESET_0', - 1: 'SPDIF1_SOFT_RESET_1', -} -SPDIF1_SOFT_RESET_0 = 0 -SPDIF1_SOFT_RESET_1 = 1 -SPDIF1_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DB_CLK_SOFT_RESET' -DB_CLK_SOFT_RESET__enumvalues = { - 0: 'DB_CLK_SOFT_RESET_0', - 1: 'DB_CLK_SOFT_RESET_1', -} -DB_CLK_SOFT_RESET_0 = 0 -DB_CLK_SOFT_RESET_1 = 1 -DB_CLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT0_SOFT_RESET' -FMT0_SOFT_RESET__enumvalues = { - 0: 'FMT0_SOFT_RESET_0', - 1: 'FMT0_SOFT_RESET_1', -} -FMT0_SOFT_RESET_0 = 0 -FMT0_SOFT_RESET_1 = 1 -FMT0_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT1_SOFT_RESET' -FMT1_SOFT_RESET__enumvalues = { - 0: 'FMT1_SOFT_RESET_0', - 1: 'FMT1_SOFT_RESET_1', -} -FMT1_SOFT_RESET_0 = 0 -FMT1_SOFT_RESET_1 = 1 -FMT1_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT2_SOFT_RESET' -FMT2_SOFT_RESET__enumvalues = { - 0: 'FMT2_SOFT_RESET_0', - 1: 'FMT2_SOFT_RESET_1', -} -FMT2_SOFT_RESET_0 = 0 -FMT2_SOFT_RESET_1 = 1 -FMT2_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT3_SOFT_RESET' -FMT3_SOFT_RESET__enumvalues = { - 0: 'FMT3_SOFT_RESET_0', - 1: 'FMT3_SOFT_RESET_1', -} -FMT3_SOFT_RESET_0 = 0 -FMT3_SOFT_RESET_1 = 1 -FMT3_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT4_SOFT_RESET' -FMT4_SOFT_RESET__enumvalues = { - 0: 'FMT4_SOFT_RESET_0', - 1: 'FMT4_SOFT_RESET_1', -} -FMT4_SOFT_RESET_0 = 0 -FMT4_SOFT_RESET_1 = 1 -FMT4_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'FMT5_SOFT_RESET' -FMT5_SOFT_RESET__enumvalues = { - 0: 'FMT5_SOFT_RESET_0', - 1: 'FMT5_SOFT_RESET_1', -} -FMT5_SOFT_RESET_0 = 0 -FMT5_SOFT_RESET_1 = 1 -FMT5_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'MVP_SOFT_RESET' -MVP_SOFT_RESET__enumvalues = { - 0: 'MVP_SOFT_RESET_0', - 1: 'MVP_SOFT_RESET_1', -} -MVP_SOFT_RESET_0 = 0 -MVP_SOFT_RESET_1 = 1 -MVP_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ABM_SOFT_RESET' -ABM_SOFT_RESET__enumvalues = { - 0: 'ABM_SOFT_RESET_0', - 1: 'ABM_SOFT_RESET_1', -} -ABM_SOFT_RESET_0 = 0 -ABM_SOFT_RESET_1 = 1 -ABM_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_SOFT_RESET' -DVO_SOFT_RESET__enumvalues = { - 0: 'DVO_SOFT_RESET_0', - 1: 'DVO_SOFT_RESET_1', -} -DVO_SOFT_RESET_0 = 0 -DVO_SOFT_RESET_1 = 1 -DVO_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGA_FE_SOFT_RESET' -DIGA_FE_SOFT_RESET__enumvalues = { - 0: 'DIGA_FE_SOFT_RESET_0', - 1: 'DIGA_FE_SOFT_RESET_1', -} -DIGA_FE_SOFT_RESET_0 = 0 -DIGA_FE_SOFT_RESET_1 = 1 -DIGA_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGA_BE_SOFT_RESET' -DIGA_BE_SOFT_RESET__enumvalues = { - 0: 'DIGA_BE_SOFT_RESET_0', - 1: 'DIGA_BE_SOFT_RESET_1', -} -DIGA_BE_SOFT_RESET_0 = 0 -DIGA_BE_SOFT_RESET_1 = 1 -DIGA_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGB_FE_SOFT_RESET' -DIGB_FE_SOFT_RESET__enumvalues = { - 0: 'DIGB_FE_SOFT_RESET_0', - 1: 'DIGB_FE_SOFT_RESET_1', -} -DIGB_FE_SOFT_RESET_0 = 0 -DIGB_FE_SOFT_RESET_1 = 1 -DIGB_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGB_BE_SOFT_RESET' -DIGB_BE_SOFT_RESET__enumvalues = { - 0: 'DIGB_BE_SOFT_RESET_0', - 1: 'DIGB_BE_SOFT_RESET_1', -} -DIGB_BE_SOFT_RESET_0 = 0 -DIGB_BE_SOFT_RESET_1 = 1 -DIGB_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGC_FE_SOFT_RESET' -DIGC_FE_SOFT_RESET__enumvalues = { - 0: 'DIGC_FE_SOFT_RESET_0', - 1: 'DIGC_FE_SOFT_RESET_1', -} -DIGC_FE_SOFT_RESET_0 = 0 -DIGC_FE_SOFT_RESET_1 = 1 -DIGC_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGC_BE_SOFT_RESET' -DIGC_BE_SOFT_RESET__enumvalues = { - 0: 'DIGC_BE_SOFT_RESET_0', - 1: 'DIGC_BE_SOFT_RESET_1', -} -DIGC_BE_SOFT_RESET_0 = 0 -DIGC_BE_SOFT_RESET_1 = 1 -DIGC_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGD_FE_SOFT_RESET' -DIGD_FE_SOFT_RESET__enumvalues = { - 0: 'DIGD_FE_SOFT_RESET_0', - 1: 'DIGD_FE_SOFT_RESET_1', -} -DIGD_FE_SOFT_RESET_0 = 0 -DIGD_FE_SOFT_RESET_1 = 1 -DIGD_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGD_BE_SOFT_RESET' -DIGD_BE_SOFT_RESET__enumvalues = { - 0: 'DIGD_BE_SOFT_RESET_0', - 1: 'DIGD_BE_SOFT_RESET_1', -} -DIGD_BE_SOFT_RESET_0 = 0 -DIGD_BE_SOFT_RESET_1 = 1 -DIGD_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGE_FE_SOFT_RESET' -DIGE_FE_SOFT_RESET__enumvalues = { - 0: 'DIGE_FE_SOFT_RESET_0', - 1: 'DIGE_FE_SOFT_RESET_1', -} -DIGE_FE_SOFT_RESET_0 = 0 -DIGE_FE_SOFT_RESET_1 = 1 -DIGE_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGE_BE_SOFT_RESET' -DIGE_BE_SOFT_RESET__enumvalues = { - 0: 'DIGE_BE_SOFT_RESET_0', - 1: 'DIGE_BE_SOFT_RESET_1', -} -DIGE_BE_SOFT_RESET_0 = 0 -DIGE_BE_SOFT_RESET_1 = 1 -DIGE_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGF_FE_SOFT_RESET' -DIGF_FE_SOFT_RESET__enumvalues = { - 0: 'DIGF_FE_SOFT_RESET_0', - 1: 'DIGF_FE_SOFT_RESET_1', -} -DIGF_FE_SOFT_RESET_0 = 0 -DIGF_FE_SOFT_RESET_1 = 1 -DIGF_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGF_BE_SOFT_RESET' -DIGF_BE_SOFT_RESET__enumvalues = { - 0: 'DIGF_BE_SOFT_RESET_0', - 1: 'DIGF_BE_SOFT_RESET_1', -} -DIGF_BE_SOFT_RESET_0 = 0 -DIGF_BE_SOFT_RESET_1 = 1 -DIGF_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGG_FE_SOFT_RESET' -DIGG_FE_SOFT_RESET__enumvalues = { - 0: 'DIGG_FE_SOFT_RESET_0', - 1: 'DIGG_FE_SOFT_RESET_1', -} -DIGG_FE_SOFT_RESET_0 = 0 -DIGG_FE_SOFT_RESET_1 = 1 -DIGG_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGG_BE_SOFT_RESET' -DIGG_BE_SOFT_RESET__enumvalues = { - 0: 'DIGG_BE_SOFT_RESET_0', - 1: 'DIGG_BE_SOFT_RESET_1', -} -DIGG_BE_SOFT_RESET_0 = 0 -DIGG_BE_SOFT_RESET_1 = 1 -DIGG_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DPDBG_SOFT_RESET' -DPDBG_SOFT_RESET__enumvalues = { - 0: 'DPDBG_SOFT_RESET_0', - 1: 'DPDBG_SOFT_RESET_1', -} -DPDBG_SOFT_RESET_0 = 0 -DPDBG_SOFT_RESET_1 = 1 -DPDBG_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGLPA_FE_SOFT_RESET' -DIGLPA_FE_SOFT_RESET__enumvalues = { - 0: 'DIGLPA_FE_SOFT_RESET_0', - 1: 'DIGLPA_FE_SOFT_RESET_1', -} -DIGLPA_FE_SOFT_RESET_0 = 0 -DIGLPA_FE_SOFT_RESET_1 = 1 -DIGLPA_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGLPA_BE_SOFT_RESET' -DIGLPA_BE_SOFT_RESET__enumvalues = { - 0: 'DIGLPA_BE_SOFT_RESET_0', - 1: 'DIGLPA_BE_SOFT_RESET_1', -} -DIGLPA_BE_SOFT_RESET_0 = 0 -DIGLPA_BE_SOFT_RESET_1 = 1 -DIGLPA_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGLPB_FE_SOFT_RESET' -DIGLPB_FE_SOFT_RESET__enumvalues = { - 0: 'DIGLPB_FE_SOFT_RESET_0', - 1: 'DIGLPB_FE_SOFT_RESET_1', -} -DIGLPB_FE_SOFT_RESET_0 = 0 -DIGLPB_FE_SOFT_RESET_1 = 1 -DIGLPB_FE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIGLPB_BE_SOFT_RESET' -DIGLPB_BE_SOFT_RESET__enumvalues = { - 0: 'DIGLPB_BE_SOFT_RESET_0', - 1: 'DIGLPB_BE_SOFT_RESET_1', -} -DIGLPB_BE_SOFT_RESET_0 = 0 -DIGLPB_BE_SOFT_RESET_1 = 1 -DIGLPB_BE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'GENERICA_STEREOSYNC_SEL' -GENERICA_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERICA_STEREOSYNC_SEL_D1', - 1: 'GENERICA_STEREOSYNC_SEL_D2', - 2: 'GENERICA_STEREOSYNC_SEL_D3', - 3: 'GENERICA_STEREOSYNC_SEL_D4', - 4: 'GENERICA_STEREOSYNC_SEL_D5', - 5: 'GENERICA_STEREOSYNC_SEL_D6', - 6: 'GENERICA_STEREOSYNC_SEL_RESERVED', -} -GENERICA_STEREOSYNC_SEL_D1 = 0 -GENERICA_STEREOSYNC_SEL_D2 = 1 -GENERICA_STEREOSYNC_SEL_D3 = 2 -GENERICA_STEREOSYNC_SEL_D4 = 3 -GENERICA_STEREOSYNC_SEL_D5 = 4 -GENERICA_STEREOSYNC_SEL_D6 = 5 -GENERICA_STEREOSYNC_SEL_RESERVED = 6 -GENERICA_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERICB_STEREOSYNC_SEL' -GENERICB_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERICB_STEREOSYNC_SEL_D1', - 1: 'GENERICB_STEREOSYNC_SEL_D2', - 2: 'GENERICB_STEREOSYNC_SEL_D3', - 3: 'GENERICB_STEREOSYNC_SEL_D4', - 4: 'GENERICB_STEREOSYNC_SEL_D5', - 5: 'GENERICB_STEREOSYNC_SEL_D6', - 6: 'GENERICB_STEREOSYNC_SEL_RESERVED', -} -GENERICB_STEREOSYNC_SEL_D1 = 0 -GENERICB_STEREOSYNC_SEL_D2 = 1 -GENERICB_STEREOSYNC_SEL_D3 = 2 -GENERICB_STEREOSYNC_SEL_D4 = 3 -GENERICB_STEREOSYNC_SEL_D5 = 4 -GENERICB_STEREOSYNC_SEL_D6 = 5 -GENERICB_STEREOSYNC_SEL_RESERVED = 6 -GENERICB_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCO_DBG_BLOCK_SEL' -DCO_DBG_BLOCK_SEL__enumvalues = { - 0: 'DCO_DBG_BLOCK_SEL_DCO', - 1: 'DCO_DBG_BLOCK_SEL_ABM', - 2: 'DCO_DBG_BLOCK_SEL_DVO', - 3: 'DCO_DBG_BLOCK_SEL_DAC', - 4: 'DCO_DBG_BLOCK_SEL_MVP', - 5: 'DCO_DBG_BLOCK_SEL_FMT0', - 6: 'DCO_DBG_BLOCK_SEL_FMT1', - 7: 'DCO_DBG_BLOCK_SEL_FMT2', - 8: 'DCO_DBG_BLOCK_SEL_FMT3', - 9: 'DCO_DBG_BLOCK_SEL_FMT4', - 10: 'DCO_DBG_BLOCK_SEL_FMT5', - 11: 'DCO_DBG_BLOCK_SEL_DIGFE_A', - 12: 'DCO_DBG_BLOCK_SEL_DIGFE_B', - 13: 'DCO_DBG_BLOCK_SEL_DIGFE_C', - 14: 'DCO_DBG_BLOCK_SEL_DIGFE_D', - 15: 'DCO_DBG_BLOCK_SEL_DIGFE_E', - 16: 'DCO_DBG_BLOCK_SEL_DIGFE_F', - 17: 'DCO_DBG_BLOCK_SEL_DIGFE_G', - 18: 'DCO_DBG_BLOCK_SEL_DIGA', - 19: 'DCO_DBG_BLOCK_SEL_DIGB', - 20: 'DCO_DBG_BLOCK_SEL_DIGC', - 21: 'DCO_DBG_BLOCK_SEL_DIGD', - 22: 'DCO_DBG_BLOCK_SEL_DIGE', - 23: 'DCO_DBG_BLOCK_SEL_DIGF', - 24: 'DCO_DBG_BLOCK_SEL_DIGG', - 25: 'DCO_DBG_BLOCK_SEL_DPFE_A', - 26: 'DCO_DBG_BLOCK_SEL_DPFE_B', - 27: 'DCO_DBG_BLOCK_SEL_DPFE_C', - 28: 'DCO_DBG_BLOCK_SEL_DPFE_D', - 29: 'DCO_DBG_BLOCK_SEL_DPFE_E', - 30: 'DCO_DBG_BLOCK_SEL_DPFE_F', - 31: 'DCO_DBG_BLOCK_SEL_DPFE_G', - 32: 'DCO_DBG_BLOCK_SEL_DPA', - 33: 'DCO_DBG_BLOCK_SEL_DPB', - 34: 'DCO_DBG_BLOCK_SEL_DPC', - 35: 'DCO_DBG_BLOCK_SEL_DPD', - 36: 'DCO_DBG_BLOCK_SEL_DPE', - 37: 'DCO_DBG_BLOCK_SEL_DPF', - 38: 'DCO_DBG_BLOCK_SEL_DPG', - 39: 'DCO_DBG_BLOCK_SEL_AUX0', - 40: 'DCO_DBG_BLOCK_SEL_AUX1', - 41: 'DCO_DBG_BLOCK_SEL_AUX2', - 42: 'DCO_DBG_BLOCK_SEL_AUX3', - 43: 'DCO_DBG_BLOCK_SEL_AUX4', - 44: 'DCO_DBG_BLOCK_SEL_AUX5', - 45: 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', - 46: 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', - 47: 'DCO_DBG_BLOCK_SEL_DIGLPFEA', - 48: 'DCO_DBG_BLOCK_SEL_DIGLPFEB', - 49: 'DCO_DBG_BLOCK_SEL_DIGLPA', - 50: 'DCO_DBG_BLOCK_SEL_DIGLPB', - 51: 'DCO_DBG_BLOCK_SEL_DPLPFEA', - 52: 'DCO_DBG_BLOCK_SEL_DPLPFEB', - 53: 'DCO_DBG_BLOCK_SEL_DPLPA', - 54: 'DCO_DBG_BLOCK_SEL_DPLPB', -} -DCO_DBG_BLOCK_SEL_DCO = 0 -DCO_DBG_BLOCK_SEL_ABM = 1 -DCO_DBG_BLOCK_SEL_DVO = 2 -DCO_DBG_BLOCK_SEL_DAC = 3 -DCO_DBG_BLOCK_SEL_MVP = 4 -DCO_DBG_BLOCK_SEL_FMT0 = 5 -DCO_DBG_BLOCK_SEL_FMT1 = 6 -DCO_DBG_BLOCK_SEL_FMT2 = 7 -DCO_DBG_BLOCK_SEL_FMT3 = 8 -DCO_DBG_BLOCK_SEL_FMT4 = 9 -DCO_DBG_BLOCK_SEL_FMT5 = 10 -DCO_DBG_BLOCK_SEL_DIGFE_A = 11 -DCO_DBG_BLOCK_SEL_DIGFE_B = 12 -DCO_DBG_BLOCK_SEL_DIGFE_C = 13 -DCO_DBG_BLOCK_SEL_DIGFE_D = 14 -DCO_DBG_BLOCK_SEL_DIGFE_E = 15 -DCO_DBG_BLOCK_SEL_DIGFE_F = 16 -DCO_DBG_BLOCK_SEL_DIGFE_G = 17 -DCO_DBG_BLOCK_SEL_DIGA = 18 -DCO_DBG_BLOCK_SEL_DIGB = 19 -DCO_DBG_BLOCK_SEL_DIGC = 20 -DCO_DBG_BLOCK_SEL_DIGD = 21 -DCO_DBG_BLOCK_SEL_DIGE = 22 -DCO_DBG_BLOCK_SEL_DIGF = 23 -DCO_DBG_BLOCK_SEL_DIGG = 24 -DCO_DBG_BLOCK_SEL_DPFE_A = 25 -DCO_DBG_BLOCK_SEL_DPFE_B = 26 -DCO_DBG_BLOCK_SEL_DPFE_C = 27 -DCO_DBG_BLOCK_SEL_DPFE_D = 28 -DCO_DBG_BLOCK_SEL_DPFE_E = 29 -DCO_DBG_BLOCK_SEL_DPFE_F = 30 -DCO_DBG_BLOCK_SEL_DPFE_G = 31 -DCO_DBG_BLOCK_SEL_DPA = 32 -DCO_DBG_BLOCK_SEL_DPB = 33 -DCO_DBG_BLOCK_SEL_DPC = 34 -DCO_DBG_BLOCK_SEL_DPD = 35 -DCO_DBG_BLOCK_SEL_DPE = 36 -DCO_DBG_BLOCK_SEL_DPF = 37 -DCO_DBG_BLOCK_SEL_DPG = 38 -DCO_DBG_BLOCK_SEL_AUX0 = 39 -DCO_DBG_BLOCK_SEL_AUX1 = 40 -DCO_DBG_BLOCK_SEL_AUX2 = 41 -DCO_DBG_BLOCK_SEL_AUX3 = 42 -DCO_DBG_BLOCK_SEL_AUX4 = 43 -DCO_DBG_BLOCK_SEL_AUX5 = 44 -DCO_DBG_BLOCK_SEL_PERFMON_DCO = 45 -DCO_DBG_BLOCK_SEL_AUDIO_OUT = 46 -DCO_DBG_BLOCK_SEL_DIGLPFEA = 47 -DCO_DBG_BLOCK_SEL_DIGLPFEB = 48 -DCO_DBG_BLOCK_SEL_DIGLPA = 49 -DCO_DBG_BLOCK_SEL_DIGLPB = 50 -DCO_DBG_BLOCK_SEL_DPLPFEA = 51 -DCO_DBG_BLOCK_SEL_DPLPFEB = 52 -DCO_DBG_BLOCK_SEL_DPLPA = 53 -DCO_DBG_BLOCK_SEL_DPLPB = 54 -DCO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE' -DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { - 0: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 1: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', -} -DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 -DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 -DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT420_MEMORY_SOURCE_SEL' -FMT420_MEMORY_SOURCE_SEL__enumvalues = { - 0: 'FMT420_MEMORY_SOURCE_SEL_FMT0', - 1: 'FMT420_MEMORY_SOURCE_SEL_FMT1', - 2: 'FMT420_MEMORY_SOURCE_SEL_FMT2', - 3: 'FMT420_MEMORY_SOURCE_SEL_FMT3', - 4: 'FMT420_MEMORY_SOURCE_SEL_FMT4', - 5: 'FMT420_MEMORY_SOURCE_SEL_FMT5', - 6: 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', -} -FMT420_MEMORY_SOURCE_SEL_FMT0 = 0 -FMT420_MEMORY_SOURCE_SEL_FMT1 = 1 -FMT420_MEMORY_SOURCE_SEL_FMT2 = 2 -FMT420_MEMORY_SOURCE_SEL_FMT3 = 3 -FMT420_MEMORY_SOURCE_SEL_FMT4 = 4 -FMT420_MEMORY_SOURCE_SEL_FMT5 = 5 -FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 6 -FMT420_MEMORY_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_GO' -DOUT_I2C_CONTROL_GO__enumvalues = { - 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 1: 'DOUT_I2C_CONTROL_START_TRANSFER', -} -DOUT_I2C_CONTROL_STOP_TRANSFER = 0 -DOUT_I2C_CONTROL_START_TRANSFER = 1 -DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' -DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', -} -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 -DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' -DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 1: 'DOUT_I2C_CONTROL__SEND_RESET', -} -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 -DOUT_I2C_CONTROL__SEND_RESET = 1 -DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' -DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', -} -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 -DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 -DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' -DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', - 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', - 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', - 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', - 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', - 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', - 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', -} -DOUT_I2C_CONTROL_SELECT_DDC1 = 0 -DOUT_I2C_CONTROL_SELECT_DDC2 = 1 -DOUT_I2C_CONTROL_SELECT_DDC3 = 2 -DOUT_I2C_CONTROL_SELECT_DDC4 = 3 -DOUT_I2C_CONTROL_SELECT_DDC5 = 4 -DOUT_I2C_CONTROL_SELECT_DDC6 = 5 -DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 -DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' -DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_TRANS0', - 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', -} -DOUT_I2C_CONTROL_TRANS0 = 0 -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 -DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' -DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', -} -DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 -DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 -DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' -DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', -} -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 -DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', -} -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' -DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', -} -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 -DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', -} -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', -} -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ACK' -DOUT_I2C_ACK__enumvalues = { - 0: 'DOUT_I2C_NO_ACK', - 1: 'DOUT_I2C_ACK_TO_CLEAN', -} -DOUT_I2C_NO_ACK = 0 -DOUT_I2C_ACK_TO_CLEAN = 1 -DOUT_I2C_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' -DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { - 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', -} -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 -DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', -} -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', -} -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' -DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { - 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', -} -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 -DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' -DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { - 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 1: 'DOUT_I2C_DATA__INDEX_WRITE', -} -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 -DOUT_I2C_DATA__INDEX_WRITE = 1 -DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', -} -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { - 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', -} -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'FBC_IDLE_MASK_MASK_BITS' -FBC_IDLE_MASK_MASK_BITS__enumvalues = { - 0: 'FBC_IDLE_MASK_DISP_REG_UPDATE', - 1: 'FBC_IDLE_MASK_RESERVED1', - 2: 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', - 3: 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', - 4: 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', - 5: 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', - 6: 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', - 7: 'FBC_IDLE_MASK_RESERVED7', - 8: 'FBC_IDLE_MASK_RESERVED8', - 9: 'FBC_IDLE_MASK_RESERVED9', - 10: 'FBC_IDLE_MASK_RESERVED10', - 11: 'FBC_IDLE_MASK_RESERVED11', - 12: 'FBC_IDLE_MASK_RESERVED12', - 13: 'FBC_IDLE_MASK_RESERVED13', - 14: 'FBC_IDLE_MASK_RESERVED14', - 15: 'FBC_IDLE_MASK_RESERVED15', - 16: 'FBC_IDLE_MASK_RESERVED16', - 17: 'FBC_IDLE_MASK_RESERVED17', - 18: 'FBC_IDLE_MASK_RESERVED18', - 19: 'FBC_IDLE_MASK_RESERVED19', - 20: 'FBC_IDLE_MASK_RESERVED20', - 21: 'FBC_IDLE_MASK_RESERVED21', - 22: 'FBC_IDLE_MASK_RESERVED22', - 23: 'FBC_IDLE_MASK_RESERVED23', - 24: 'FBC_IDLE_MASK_MC_HIT_REGION_0', - 25: 'FBC_IDLE_MASK_MC_HIT_REGION_1', - 26: 'FBC_IDLE_MASK_MC_HIT_REGION_2', - 27: 'FBC_IDLE_MASK_MC_HIT_REGION_3', - 28: 'FBC_IDLE_MASK_MC_WRITE', - 29: 'FBC_IDLE_MASK_RESERVED29', - 30: 'FBC_IDLE_MASK_RESERVED30', - 31: 'FBC_IDLE_MASK_RESERVED31', -} -FBC_IDLE_MASK_DISP_REG_UPDATE = 0 -FBC_IDLE_MASK_RESERVED1 = 1 -FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 2 -FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 3 -FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 4 -FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 5 -FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 6 -FBC_IDLE_MASK_RESERVED7 = 7 -FBC_IDLE_MASK_RESERVED8 = 8 -FBC_IDLE_MASK_RESERVED9 = 9 -FBC_IDLE_MASK_RESERVED10 = 10 -FBC_IDLE_MASK_RESERVED11 = 11 -FBC_IDLE_MASK_RESERVED12 = 12 -FBC_IDLE_MASK_RESERVED13 = 13 -FBC_IDLE_MASK_RESERVED14 = 14 -FBC_IDLE_MASK_RESERVED15 = 15 -FBC_IDLE_MASK_RESERVED16 = 16 -FBC_IDLE_MASK_RESERVED17 = 17 -FBC_IDLE_MASK_RESERVED18 = 18 -FBC_IDLE_MASK_RESERVED19 = 19 -FBC_IDLE_MASK_RESERVED20 = 20 -FBC_IDLE_MASK_RESERVED21 = 21 -FBC_IDLE_MASK_RESERVED22 = 22 -FBC_IDLE_MASK_RESERVED23 = 23 -FBC_IDLE_MASK_MC_HIT_REGION_0 = 24 -FBC_IDLE_MASK_MC_HIT_REGION_1 = 25 -FBC_IDLE_MASK_MC_HIT_REGION_2 = 26 -FBC_IDLE_MASK_MC_HIT_REGION_3 = 27 -FBC_IDLE_MASK_MC_WRITE = 28 -FBC_IDLE_MASK_RESERVED29 = 29 -FBC_IDLE_MASK_RESERVED30 = 30 -FBC_IDLE_MASK_RESERVED31 = 31 -FBC_IDLE_MASK_MASK_BITS = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' -DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { - 0: 'DPCSRX_BPHY_PCS_RX0_CLK', - 1: 'DPCSRX_BPHY_PCS_RX1_CLK', - 2: 'DPCSRX_BPHY_PCS_RX2_CLK', - 3: 'DPCSRX_BPHY_PCS_RX3_CLK', -} -DPCSRX_BPHY_PCS_RX0_CLK = 0 -DPCSRX_BPHY_PCS_RX1_CLK = 1 -DPCSRX_BPHY_PCS_RX2_CLK = 2 -DPCSRX_BPHY_PCS_RX3_CLK = 3 -DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSRX_DBG_CFGCLK_SEL' -DPCSRX_DBG_CFGCLK_SEL__enumvalues = { - 0: 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', - 1: 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', - 2: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', - 3: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', -} -DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 -DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 -DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 -DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 -DPCSRX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSRX_RX_SYMCLK_SEL' -DPCSRX_RX_SYMCLK_SEL__enumvalues = { - 0: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', - 1: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', - 2: 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', -} -DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0 -DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 1 -DPCSRX_DBG_RX_SYMCLK_SEL_INT = 2 -DPCSRX_RX_SYMCLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSTX_DBG_CFGCLK_SEL' -DPCSTX_DBG_CFGCLK_SEL__enumvalues = { - 0: 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', - 1: 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', - 2: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', - 3: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', -} -DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 -DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 -DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 -DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 -DPCSTX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSTX_TX_SYMCLK_SEL' -DPCSTX_TX_SYMCLK_SEL__enumvalues = { - 0: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', - 1: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', - 2: 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', -} -DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0 -DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 1 -DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 2 -DPCSTX_TX_SYMCLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPCSTX_TX_SYMCLK_DIV2_SEL' -DPCSTX_TX_SYMCLK_DIV2_SEL__enumvalues = { - 0: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', - 1: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', - 2: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', - 3: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', - 4: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', - 5: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', -} -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0 -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 1 -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 2 -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 3 -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 4 -DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 5 -DPCSTX_TX_SYMCLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceNumber' -SurfaceNumber__enumvalues = { - 0: 'NUMBER_UNORM', - 1: 'NUMBER_SNORM', - 2: 'NUMBER_USCALED', - 3: 'NUMBER_SSCALED', - 4: 'NUMBER_UINT', - 5: 'NUMBER_SINT', - 6: 'NUMBER_SRGB', - 7: 'NUMBER_FLOAT', -} -NUMBER_UNORM = 0 -NUMBER_SNORM = 1 -NUMBER_USCALED = 2 -NUMBER_SSCALED = 3 -NUMBER_UINT = 4 -NUMBER_SINT = 5 -NUMBER_SRGB = 6 -NUMBER_FLOAT = 7 -SurfaceNumber = ctypes.c_uint32 # enum - -# values for enumeration 'SurfaceSwap' -SurfaceSwap__enumvalues = { - 0: 'SWAP_STD', - 1: 'SWAP_ALT', - 2: 'SWAP_STD_REV', - 3: 'SWAP_ALT_REV', -} -SWAP_STD = 0 -SWAP_ALT = 1 -SWAP_STD_REV = 2 -SWAP_ALT_REV = 3 -SurfaceSwap = ctypes.c_uint32 # enum - -# values for enumeration 'CBMode' -CBMode__enumvalues = { - 0: 'CB_DISABLE', - 1: 'CB_NORMAL', - 2: 'CB_ELIMINATE_FAST_CLEAR', - 3: 'CB_RESOLVE', - 4: 'CB_DECOMPRESS', - 5: 'CB_FMASK_DECOMPRESS', - 6: 'CB_DCC_DECOMPRESS', -} -CB_DISABLE = 0 -CB_NORMAL = 1 -CB_ELIMINATE_FAST_CLEAR = 2 -CB_RESOLVE = 3 -CB_DECOMPRESS = 4 -CB_FMASK_DECOMPRESS = 5 -CB_DCC_DECOMPRESS = 6 -CBMode = ctypes.c_uint32 # enum - -# values for enumeration 'RoundMode' -RoundMode__enumvalues = { - 0: 'ROUND_BY_HALF', - 1: 'ROUND_TRUNCATE', -} -ROUND_BY_HALF = 0 -ROUND_TRUNCATE = 1 -RoundMode = ctypes.c_uint32 # enum - -# values for enumeration 'SourceFormat' -SourceFormat__enumvalues = { - 0: 'EXPORT_4C_32BPC', - 1: 'EXPORT_4C_16BPC', - 2: 'EXPORT_2C_32BPC_GR', - 3: 'EXPORT_2C_32BPC_AR', -} -EXPORT_4C_32BPC = 0 -EXPORT_4C_16BPC = 1 -EXPORT_2C_32BPC_GR = 2 -EXPORT_2C_32BPC_AR = 3 -SourceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOp' -BlendOp__enumvalues = { - 0: 'BLEND_ZERO', - 1: 'BLEND_ONE', - 2: 'BLEND_SRC_COLOR', - 3: 'BLEND_ONE_MINUS_SRC_COLOR', - 4: 'BLEND_SRC_ALPHA', - 5: 'BLEND_ONE_MINUS_SRC_ALPHA', - 6: 'BLEND_DST_ALPHA', - 7: 'BLEND_ONE_MINUS_DST_ALPHA', - 8: 'BLEND_DST_COLOR', - 9: 'BLEND_ONE_MINUS_DST_COLOR', - 10: 'BLEND_SRC_ALPHA_SATURATE', - 11: 'BLEND_BOTH_SRC_ALPHA', - 12: 'BLEND_BOTH_INV_SRC_ALPHA', - 13: 'BLEND_CONSTANT_COLOR', - 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', - 15: 'BLEND_SRC1_COLOR', - 16: 'BLEND_INV_SRC1_COLOR', - 17: 'BLEND_SRC1_ALPHA', - 18: 'BLEND_INV_SRC1_ALPHA', - 19: 'BLEND_CONSTANT_ALPHA', - 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', -} -BLEND_ZERO = 0 -BLEND_ONE = 1 -BLEND_SRC_COLOR = 2 -BLEND_ONE_MINUS_SRC_COLOR = 3 -BLEND_SRC_ALPHA = 4 -BLEND_ONE_MINUS_SRC_ALPHA = 5 -BLEND_DST_ALPHA = 6 -BLEND_ONE_MINUS_DST_ALPHA = 7 -BLEND_DST_COLOR = 8 -BLEND_ONE_MINUS_DST_COLOR = 9 -BLEND_SRC_ALPHA_SATURATE = 10 -BLEND_BOTH_SRC_ALPHA = 11 -BLEND_BOTH_INV_SRC_ALPHA = 12 -BLEND_CONSTANT_COLOR = 13 -BLEND_ONE_MINUS_CONSTANT_COLOR = 14 -BLEND_SRC1_COLOR = 15 -BLEND_INV_SRC1_COLOR = 16 -BLEND_SRC1_ALPHA = 17 -BLEND_INV_SRC1_ALPHA = 18 -BLEND_CONSTANT_ALPHA = 19 -BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 -BlendOp = ctypes.c_uint32 # enum -GL__ZERO = BLEND_ZERO # macro -GL__ONE = BLEND_ONE # macro -GL__SRC_COLOR = BLEND_SRC_COLOR # macro -GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro -GL__DST_COLOR = BLEND_DST_COLOR # macro -GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro -GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro -GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro -GL__DST_ALPHA = BLEND_DST_ALPHA # macro -GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro -GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro -GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro -GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro -GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro -GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro - -# values for enumeration 'CombFunc' -CombFunc__enumvalues = { - 0: 'COMB_DST_PLUS_SRC', - 1: 'COMB_SRC_MINUS_DST', - 2: 'COMB_MIN_DST_SRC', - 3: 'COMB_MAX_DST_SRC', - 4: 'COMB_DST_MINUS_SRC', -} -COMB_DST_PLUS_SRC = 0 -COMB_SRC_MINUS_DST = 1 -COMB_MIN_DST_SRC = 2 -COMB_MAX_DST_SRC = 3 -COMB_DST_MINUS_SRC = 4 -CombFunc = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOpt' -BlendOpt__enumvalues = { - 0: 'FORCE_OPT_AUTO', - 1: 'FORCE_OPT_DISABLE', - 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', - 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', - 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', -} -FORCE_OPT_AUTO = 0 -FORCE_OPT_DISABLE = 1 -FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 -FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 -BlendOpt = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskCode' -CmaskCode__enumvalues = { - 0: 'CMASK_CLR00_F0', - 1: 'CMASK_CLR00_F1', - 2: 'CMASK_CLR00_F2', - 3: 'CMASK_CLR00_FX', - 4: 'CMASK_CLR01_F0', - 5: 'CMASK_CLR01_F1', - 6: 'CMASK_CLR01_F2', - 7: 'CMASK_CLR01_FX', - 8: 'CMASK_CLR10_F0', - 9: 'CMASK_CLR10_F1', - 10: 'CMASK_CLR10_F2', - 11: 'CMASK_CLR10_FX', - 12: 'CMASK_CLR11_F0', - 13: 'CMASK_CLR11_F1', - 14: 'CMASK_CLR11_F2', - 15: 'CMASK_CLR11_FX', -} -CMASK_CLR00_F0 = 0 -CMASK_CLR00_F1 = 1 -CMASK_CLR00_F2 = 2 -CMASK_CLR00_FX = 3 -CMASK_CLR01_F0 = 4 -CMASK_CLR01_F1 = 5 -CMASK_CLR01_F2 = 6 -CMASK_CLR01_FX = 7 -CMASK_CLR10_F0 = 8 -CMASK_CLR10_F1 = 9 -CMASK_CLR10_F2 = 10 -CMASK_CLR10_FX = 11 -CMASK_CLR11_F0 = 12 -CMASK_CLR11_F1 = 13 -CMASK_CLR11_F2 = 14 -CMASK_CLR11_FX = 15 -CmaskCode = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskAddr' -CmaskAddr__enumvalues = { - 0: 'CMASK_ADDR_TILED', - 1: 'CMASK_ADDR_LINEAR', - 2: 'CMASK_ADDR_COMPATIBLE', -} -CMASK_ADDR_TILED = 0 -CMASK_ADDR_LINEAR = 1 -CMASK_ADDR_COMPATIBLE = 2 -CmaskAddr = ctypes.c_uint32 # enum - -# values for enumeration 'MemArbMode' -MemArbMode__enumvalues = { - 0: 'MEM_ARB_MODE_FIXED', - 1: 'MEM_ARB_MODE_AGE', - 2: 'MEM_ARB_MODE_WEIGHT', - 3: 'MEM_ARB_MODE_BOTH', -} -MEM_ARB_MODE_FIXED = 0 -MEM_ARB_MODE_AGE = 1 -MEM_ARB_MODE_WEIGHT = 2 -MEM_ARB_MODE_BOTH = 3 -MemArbMode = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfSel' -CBPerfSel__enumvalues = { - 0: 'CB_PERF_SEL_NONE', - 1: 'CB_PERF_SEL_BUSY', - 2: 'CB_PERF_SEL_CORE_SCLK_VLD', - 3: 'CB_PERF_SEL_REG_SCLK0_VLD', - 4: 'CB_PERF_SEL_REG_SCLK1_VLD', - 5: 'CB_PERF_SEL_DRAWN_QUAD', - 6: 'CB_PERF_SEL_DRAWN_PIXEL', - 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', - 8: 'CB_PERF_SEL_DRAWN_TILE', - 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', - 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', - 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', - 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', - 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', - 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', - 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', - 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', - 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', - 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', - 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', - 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', - 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', - 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', - 23: 'CB_PERF_SEL_LQUAD_NO_TILE', - 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', - 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', - 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', - 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', - 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', - 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', - 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', - 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', - 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', - 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', - 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', - 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', - 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', - 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', - 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', - 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', - 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', - 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', - 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', - 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', - 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', - 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', - 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', - 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', - 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', - 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', - 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', - 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', - 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', - 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', - 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', - 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', - 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', - 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', - 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', - 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', - 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', - 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', - 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', - 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', - 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', - 65: 'CB_PERF_SEL_CM_CACHE_HIT', - 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', - 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', - 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', - 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', - 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', - 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', - 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', - 75: 'CB_PERF_SEL_CM_CACHE_STALL', - 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', - 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', - 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', - 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', - 80: 'CB_PERF_SEL_FC_CACHE_HIT', - 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', - 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', - 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', - 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', - 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', - 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', - 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', - 90: 'CB_PERF_SEL_FC_CACHE_STALL', - 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', - 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', - 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', - 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', - 95: 'CB_PERF_SEL_CC_CACHE_HIT', - 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', - 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 105: 'CB_PERF_SEL_CC_CACHE_STALL', - 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', - 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 111: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', - 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', - 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', - 115: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', - 116: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', - 117: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', - 118: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 119: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', - 120: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', - 121: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', - 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', - 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', - 125: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', - 126: 'CB_PERF_SEL_CM_MC_READ_REQUEST', - 127: 'CB_PERF_SEL_FC_MC_READ_REQUEST', - 128: 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 129: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', - 130: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', - 131: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 132: 'CB_PERF_SEL_CM_TQ_FULL', - 133: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', - 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', - 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', - 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 137: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', - 138: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', - 139: 'CB_PERF_SEL_CC_SF_FULL', - 140: 'CB_PERF_SEL_CC_RB_FULL', - 141: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', - 142: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', - 143: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', - 144: 'CB_PERF_SEL_EVENT', - 145: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 146: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 147: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 148: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 149: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 150: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 151: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 152: 'CB_PERF_SEL_CC_SURFACE_SYNC', - 153: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', - 154: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', - 155: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', - 156: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', - 157: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', - 158: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', - 159: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', - 160: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', - 161: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', - 162: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 163: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', - 164: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', - 165: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 166: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 167: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 168: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 169: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 170: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 171: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 172: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', - 173: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', - 174: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', - 175: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', - 176: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', - 177: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', - 178: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', - 179: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', - 180: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', - 181: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', - 182: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', - 183: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', - 184: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', - 185: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', - 186: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', - 187: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', - 188: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', - 189: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', - 190: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', - 191: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', - 192: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', - 193: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', - 194: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', - 195: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', - 196: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', - 197: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', - 198: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', - 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', - 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', - 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', - 202: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', - 203: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', - 204: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', - 205: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', - 206: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', - 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', - 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', - 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', - 210: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', - 211: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', - 212: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', - 213: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 214: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 215: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', - 216: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 217: 'CB_PERF_SEL_DRAWN_BUSY', - 218: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', - 219: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', - 220: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', - 221: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', - 222: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', - 223: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', - 224: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', - 225: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', - 226: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', - 227: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', - 228: 'CB_PERF_SEL_FC_DOC_IS_STALLED', - 229: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', - 230: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', - 231: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', - 232: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', - 233: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', - 234: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', - 235: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', - 236: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', - 237: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', - 238: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', - 239: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', - 240: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', - 241: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', - 242: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', - 243: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', - 244: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', - 245: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 246: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 247: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 248: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', - 249: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', - 250: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', - 251: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', - 252: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', - 253: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', - 254: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', - 255: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 256: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', - 257: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', - 258: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', - 259: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', - 260: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', - 261: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', - 262: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', - 263: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', - 264: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', - 265: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', - 266: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', - 267: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', - 268: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', - 269: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 270: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', - 271: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', - 272: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', - 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', - 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', - 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', - 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', - 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', - 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', - 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', - 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', - 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', - 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', - 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', - 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', - 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', - 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', - 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', - 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', - 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', - 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', - 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', - 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', - 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', - 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', - 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', - 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', - 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', - 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', - 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', - 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', - 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', - 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', - 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', - 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', - 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', - 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', - 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', - 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', - 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', - 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', - 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', - 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', - 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', - 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', - 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', - 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', - 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', - 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', - 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', - 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', - 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', - 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', - 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', - 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', - 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', - 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', - 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', - 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', - 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', - 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', - 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', - 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', - 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', - 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', - 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', - 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', - 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', - 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', - 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', - 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', - 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', - 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', - 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', - 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', - 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', - 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', - 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', - 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', - 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', - 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', - 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', - 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', - 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', - 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', - 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', - 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', - 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', - 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', - 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', - 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', - 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', - 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', - 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', - 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', - 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', - 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', - 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', - 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', - 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', - 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', - 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', - 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', - 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', - 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', - 380: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', - 381: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', - 382: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', - 383: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', - 384: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', - 385: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', - 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', - 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', - 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', - 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', - 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', - 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', - 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', - 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', - 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', - 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', - 396: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 397: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 398: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 399: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', - 400: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', - 401: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', - 402: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', - 403: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', - 404: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', -} -CB_PERF_SEL_NONE = 0 -CB_PERF_SEL_BUSY = 1 -CB_PERF_SEL_CORE_SCLK_VLD = 2 -CB_PERF_SEL_REG_SCLK0_VLD = 3 -CB_PERF_SEL_REG_SCLK1_VLD = 4 -CB_PERF_SEL_DRAWN_QUAD = 5 -CB_PERF_SEL_DRAWN_PIXEL = 6 -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 -CB_PERF_SEL_DRAWN_TILE = 8 -CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 -CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 -CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 -CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 -CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 -CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 -CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 -CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 -CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 -CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 -CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 -CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 -CB_PERF_SEL_LQUAD_NO_TILE = 23 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 -CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 -CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 -CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 -CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 -CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 -CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 -CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 -CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 -CB_PERF_SEL_FOP_IN_VALID_READY = 40 -CB_PERF_SEL_FOP_IN_VALID_READYB = 41 -CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 -CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 -CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 -CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 -CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 -CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 -CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 -CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 -CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 -CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 -CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 -CB_PERF_SEL_CM_CACHE_HIT = 65 -CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 -CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 -CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 -CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 -CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 -CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 -CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 -CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 -CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 -CB_PERF_SEL_CM_CACHE_STALL = 75 -CB_PERF_SEL_CM_CACHE_FLUSH = 76 -CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 -CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 -CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 -CB_PERF_SEL_FC_CACHE_HIT = 80 -CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 -CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 -CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 -CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 -CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 -CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 -CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 -CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 -CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 -CB_PERF_SEL_FC_CACHE_STALL = 90 -CB_PERF_SEL_FC_CACHE_FLUSH = 91 -CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 -CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 -CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 -CB_PERF_SEL_CC_CACHE_HIT = 95 -CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 -CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 -CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 -CB_PERF_SEL_CC_CACHE_STALL = 105 -CB_PERF_SEL_CC_CACHE_FLUSH = 106 -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 111 -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 112 -CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 113 -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 114 -CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 115 -CB_PERF_SEL_CM_MC_WRITE_REQUEST = 116 -CB_PERF_SEL_FC_MC_WRITE_REQUEST = 117 -CB_PERF_SEL_CC_MC_WRITE_REQUEST = 118 -CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 119 -CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 121 -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 122 -CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 123 -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 124 -CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 125 -CB_PERF_SEL_CM_MC_READ_REQUEST = 126 -CB_PERF_SEL_FC_MC_READ_REQUEST = 127 -CB_PERF_SEL_CC_MC_READ_REQUEST = 128 -CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 129 -CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 130 -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 131 -CB_PERF_SEL_CM_TQ_FULL = 132 -CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 133 -CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 -CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 -CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 -CB_PERF_SEL_FOP_FMASK_RAW_STALL = 137 -CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 138 -CB_PERF_SEL_CC_SF_FULL = 139 -CB_PERF_SEL_CC_RB_FULL = 140 -CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 141 -CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 142 -CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 143 -CB_PERF_SEL_EVENT = 144 -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 145 -CB_PERF_SEL_EVENT_CONTEXT_DONE = 146 -CB_PERF_SEL_EVENT_CACHE_FLUSH = 147 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 148 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 149 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 150 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 151 -CB_PERF_SEL_CC_SURFACE_SYNC = 152 -CB_PERF_SEL_CMASK_READ_DATA_0xC = 153 -CB_PERF_SEL_CMASK_READ_DATA_0xD = 154 -CB_PERF_SEL_CMASK_READ_DATA_0xE = 155 -CB_PERF_SEL_CMASK_READ_DATA_0xF = 156 -CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 157 -CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 158 -CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 159 -CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 160 -CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 161 -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 162 -CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 163 -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 164 -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 165 -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 166 -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 167 -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 168 -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 169 -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 170 -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 171 -CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 172 -CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 173 -CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 174 -CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 175 -CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 176 -CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 177 -CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 178 -CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 179 -CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 180 -CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 181 -CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 182 -CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 183 -CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 184 -CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 185 -CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 186 -CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 187 -CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 188 -CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 189 -CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 190 -CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 191 -CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 192 -CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 193 -CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 194 -CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 195 -CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 196 -CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 197 -CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 198 -CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 199 -CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 200 -CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 201 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 202 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 203 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 204 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 205 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 206 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 207 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 208 -CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 209 -CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 210 -CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 211 -CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 212 -CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 213 -CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 214 -CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 215 -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 216 -CB_PERF_SEL_DRAWN_BUSY = 217 -CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 218 -CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 219 -CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 220 -CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 221 -CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 222 -CB_PERF_SEL_FC_SEQUENCER_CLEAR = 223 -CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 224 -CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 225 -CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 226 -CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 227 -CB_PERF_SEL_FC_DOC_IS_STALLED = 228 -CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 229 -CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 230 -CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 231 -CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 232 -CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 233 -CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 234 -CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 235 -CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 236 -CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 237 -CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 238 -CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 239 -CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 240 -CB_PERF_SEL_FC_DCC_CACHE_HIT = 241 -CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 242 -CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 243 -CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 244 -CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 245 -CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 246 -CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 247 -CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 248 -CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 249 -CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 250 -CB_PERF_SEL_FC_DCC_CACHE_STALL = 251 -CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 252 -CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 253 -CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 254 -CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 255 -CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 256 -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 257 -CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 258 -CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 259 -CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 260 -CB_PERF_SEL_CC_DCC_RDREQ_STALL = 261 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 262 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 263 -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 264 -CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 265 -CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 266 -CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 267 -CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 268 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 269 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 270 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 271 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 272 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 273 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 274 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 276 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 277 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 278 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 279 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 -CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 281 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 282 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 283 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 284 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 285 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 286 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 287 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 288 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 289 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 290 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 291 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 292 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 293 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 294 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 295 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 296 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 297 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 298 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 299 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 300 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 301 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 302 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 303 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 304 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 305 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 306 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 307 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 308 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 309 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 310 -CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 311 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 312 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 313 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 314 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 315 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 316 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 317 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 318 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 319 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 320 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 321 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 322 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 323 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 324 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 325 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 326 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 327 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 328 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 329 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 330 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 331 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 332 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 333 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 334 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 335 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 336 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 337 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 338 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 339 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 340 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 341 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 342 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 343 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 344 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 345 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 346 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 347 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 348 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 349 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 350 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 351 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 352 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 353 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 354 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 355 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 356 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 357 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 358 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 359 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 360 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 361 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 362 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 363 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 364 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 365 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 366 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 367 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 368 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 369 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 370 -CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 371 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 372 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 373 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 374 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 375 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 376 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 377 -CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 378 -CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 379 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 380 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 381 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 382 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 383 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 384 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 385 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 386 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 387 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 388 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 389 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 390 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 391 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 392 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 393 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 394 -CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 395 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 396 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 397 -CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 398 -CB_PERF_SEL_RBP_SPLIT_MICROTILE = 399 -CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 400 -CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 401 -CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 402 -CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 403 -CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 404 -CBPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfOpFilterSel' -CBPerfOpFilterSel__enumvalues = { - 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', -} -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 -CB_PERF_OP_FILTER_SEL_RESOLVE = 2 -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 -CBPerfOpFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfClearFilterSel' -CBPerfClearFilterSel__enumvalues = { - 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', -} -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 -CBPerfClearFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP_MASKS' -TC_OP_MASKS__enumvalues = { - 8: 'TC_OP_MASK_FLUSH_DENROM', - 32: 'TC_OP_MASK_64', - 64: 'TC_OP_MASK_NO_RTN', -} -TC_OP_MASK_FLUSH_DENROM = 8 -TC_OP_MASK_64 = 32 -TC_OP_MASK_NO_RTN = 64 -TC_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP' -TC_OP__enumvalues = { - 0: 'TC_OP_READ', - 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'TC_OP_ATOMIC_FMIN_RTN_32', - 3: 'TC_OP_ATOMIC_FMAX_RTN_32', - 4: 'TC_OP_RESERVED_FOP_RTN_32_0', - 5: 'TC_OP_RESERVED_FOP_RTN_32_1', - 6: 'TC_OP_RESERVED_FOP_RTN_32_2', - 7: 'TC_OP_ATOMIC_SWAP_RTN_32', - 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'TC_OP_PROBE_FILTER', - 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'TC_OP_ATOMIC_ADD_RTN_32', - 16: 'TC_OP_ATOMIC_SUB_RTN_32', - 17: 'TC_OP_ATOMIC_SMIN_RTN_32', - 18: 'TC_OP_ATOMIC_UMIN_RTN_32', - 19: 'TC_OP_ATOMIC_SMAX_RTN_32', - 20: 'TC_OP_ATOMIC_UMAX_RTN_32', - 21: 'TC_OP_ATOMIC_AND_RTN_32', - 22: 'TC_OP_ATOMIC_OR_RTN_32', - 23: 'TC_OP_ATOMIC_XOR_RTN_32', - 24: 'TC_OP_ATOMIC_INC_RTN_32', - 25: 'TC_OP_ATOMIC_DEC_RTN_32', - 26: 'TC_OP_WBINVL1_VOL', - 27: 'TC_OP_WBINVL1_SD', - 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 32: 'TC_OP_WRITE', - 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'TC_OP_ATOMIC_FMIN_RTN_64', - 35: 'TC_OP_ATOMIC_FMAX_RTN_64', - 36: 'TC_OP_RESERVED_FOP_RTN_64_0', - 37: 'TC_OP_RESERVED_FOP_RTN_64_1', - 38: 'TC_OP_RESERVED_FOP_RTN_64_2', - 39: 'TC_OP_ATOMIC_SWAP_RTN_64', - 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 44: 'TC_OP_WBINVL2_SD', - 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 47: 'TC_OP_ATOMIC_ADD_RTN_64', - 48: 'TC_OP_ATOMIC_SUB_RTN_64', - 49: 'TC_OP_ATOMIC_SMIN_RTN_64', - 50: 'TC_OP_ATOMIC_UMIN_RTN_64', - 51: 'TC_OP_ATOMIC_SMAX_RTN_64', - 52: 'TC_OP_ATOMIC_UMAX_RTN_64', - 53: 'TC_OP_ATOMIC_AND_RTN_64', - 54: 'TC_OP_ATOMIC_OR_RTN_64', - 55: 'TC_OP_ATOMIC_XOR_RTN_64', - 56: 'TC_OP_ATOMIC_INC_RTN_64', - 57: 'TC_OP_ATOMIC_DEC_RTN_64', - 58: 'TC_OP_WBL2_NC', - 59: 'TC_OP_WBL2_WC', - 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', - 64: 'TC_OP_WBINVL1', - 65: 'TC_OP_ATOMIC_FCMPSWAP_32', - 66: 'TC_OP_ATOMIC_FMIN_32', - 67: 'TC_OP_ATOMIC_FMAX_32', - 68: 'TC_OP_RESERVED_FOP_32_0', - 69: 'TC_OP_RESERVED_FOP_32_1', - 70: 'TC_OP_RESERVED_FOP_32_2', - 71: 'TC_OP_ATOMIC_SWAP_32', - 72: 'TC_OP_ATOMIC_CMPSWAP_32', - 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'TC_OP_INV_METADATA', - 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', - 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 79: 'TC_OP_ATOMIC_ADD_32', - 80: 'TC_OP_ATOMIC_SUB_32', - 81: 'TC_OP_ATOMIC_SMIN_32', - 82: 'TC_OP_ATOMIC_UMIN_32', - 83: 'TC_OP_ATOMIC_SMAX_32', - 84: 'TC_OP_ATOMIC_UMAX_32', - 85: 'TC_OP_ATOMIC_AND_32', - 86: 'TC_OP_ATOMIC_OR_32', - 87: 'TC_OP_ATOMIC_XOR_32', - 88: 'TC_OP_ATOMIC_INC_32', - 89: 'TC_OP_ATOMIC_DEC_32', - 90: 'TC_OP_INVL2_NC', - 91: 'TC_OP_NOP_RTN0', - 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', - 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', - 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', - 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', - 96: 'TC_OP_WBINVL2', - 97: 'TC_OP_ATOMIC_FCMPSWAP_64', - 98: 'TC_OP_ATOMIC_FMIN_64', - 99: 'TC_OP_ATOMIC_FMAX_64', - 100: 'TC_OP_RESERVED_FOP_64_0', - 101: 'TC_OP_RESERVED_FOP_64_1', - 102: 'TC_OP_RESERVED_FOP_64_2', - 103: 'TC_OP_ATOMIC_SWAP_64', - 104: 'TC_OP_ATOMIC_CMPSWAP_64', - 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 111: 'TC_OP_ATOMIC_ADD_64', - 112: 'TC_OP_ATOMIC_SUB_64', - 113: 'TC_OP_ATOMIC_SMIN_64', - 114: 'TC_OP_ATOMIC_UMIN_64', - 115: 'TC_OP_ATOMIC_SMAX_64', - 116: 'TC_OP_ATOMIC_UMAX_64', - 117: 'TC_OP_ATOMIC_AND_64', - 118: 'TC_OP_ATOMIC_OR_64', - 119: 'TC_OP_ATOMIC_XOR_64', - 120: 'TC_OP_ATOMIC_INC_64', - 121: 'TC_OP_ATOMIC_DEC_64', - 122: 'TC_OP_WBINVL2_NC', - 123: 'TC_OP_NOP_ACK', - 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', - 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', - 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', - 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', -} -TC_OP_READ = 0 -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -TC_OP_ATOMIC_FMIN_RTN_32 = 2 -TC_OP_ATOMIC_FMAX_RTN_32 = 3 -TC_OP_RESERVED_FOP_RTN_32_0 = 4 -TC_OP_RESERVED_FOP_RTN_32_1 = 5 -TC_OP_RESERVED_FOP_RTN_32_2 = 6 -TC_OP_ATOMIC_SWAP_RTN_32 = 7 -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -TC_OP_PROBE_FILTER = 12 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -TC_OP_ATOMIC_ADD_RTN_32 = 15 -TC_OP_ATOMIC_SUB_RTN_32 = 16 -TC_OP_ATOMIC_SMIN_RTN_32 = 17 -TC_OP_ATOMIC_UMIN_RTN_32 = 18 -TC_OP_ATOMIC_SMAX_RTN_32 = 19 -TC_OP_ATOMIC_UMAX_RTN_32 = 20 -TC_OP_ATOMIC_AND_RTN_32 = 21 -TC_OP_ATOMIC_OR_RTN_32 = 22 -TC_OP_ATOMIC_XOR_RTN_32 = 23 -TC_OP_ATOMIC_INC_RTN_32 = 24 -TC_OP_ATOMIC_DEC_RTN_32 = 25 -TC_OP_WBINVL1_VOL = 26 -TC_OP_WBINVL1_SD = 27 -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 -TC_OP_WRITE = 32 -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -TC_OP_ATOMIC_FMIN_RTN_64 = 34 -TC_OP_ATOMIC_FMAX_RTN_64 = 35 -TC_OP_RESERVED_FOP_RTN_64_0 = 36 -TC_OP_RESERVED_FOP_RTN_64_1 = 37 -TC_OP_RESERVED_FOP_RTN_64_2 = 38 -TC_OP_ATOMIC_SWAP_RTN_64 = 39 -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -TC_OP_WBINVL2_SD = 44 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 -TC_OP_ATOMIC_ADD_RTN_64 = 47 -TC_OP_ATOMIC_SUB_RTN_64 = 48 -TC_OP_ATOMIC_SMIN_RTN_64 = 49 -TC_OP_ATOMIC_UMIN_RTN_64 = 50 -TC_OP_ATOMIC_SMAX_RTN_64 = 51 -TC_OP_ATOMIC_UMAX_RTN_64 = 52 -TC_OP_ATOMIC_AND_RTN_64 = 53 -TC_OP_ATOMIC_OR_RTN_64 = 54 -TC_OP_ATOMIC_XOR_RTN_64 = 55 -TC_OP_ATOMIC_INC_RTN_64 = 56 -TC_OP_ATOMIC_DEC_RTN_64 = 57 -TC_OP_WBL2_NC = 58 -TC_OP_WBL2_WC = 59 -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 -TC_OP_WBINVL1 = 64 -TC_OP_ATOMIC_FCMPSWAP_32 = 65 -TC_OP_ATOMIC_FMIN_32 = 66 -TC_OP_ATOMIC_FMAX_32 = 67 -TC_OP_RESERVED_FOP_32_0 = 68 -TC_OP_RESERVED_FOP_32_1 = 69 -TC_OP_RESERVED_FOP_32_2 = 70 -TC_OP_ATOMIC_SWAP_32 = 71 -TC_OP_ATOMIC_CMPSWAP_32 = 72 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -TC_OP_INV_METADATA = 76 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 -TC_OP_ATOMIC_ADD_32 = 79 -TC_OP_ATOMIC_SUB_32 = 80 -TC_OP_ATOMIC_SMIN_32 = 81 -TC_OP_ATOMIC_UMIN_32 = 82 -TC_OP_ATOMIC_SMAX_32 = 83 -TC_OP_ATOMIC_UMAX_32 = 84 -TC_OP_ATOMIC_AND_32 = 85 -TC_OP_ATOMIC_OR_32 = 86 -TC_OP_ATOMIC_XOR_32 = 87 -TC_OP_ATOMIC_INC_32 = 88 -TC_OP_ATOMIC_DEC_32 = 89 -TC_OP_INVL2_NC = 90 -TC_OP_NOP_RTN0 = 91 -TC_OP_RESERVED_NON_FLOAT_32_1 = 92 -TC_OP_RESERVED_NON_FLOAT_32_2 = 93 -TC_OP_RESERVED_NON_FLOAT_32_3 = 94 -TC_OP_RESERVED_NON_FLOAT_32_4 = 95 -TC_OP_WBINVL2 = 96 -TC_OP_ATOMIC_FCMPSWAP_64 = 97 -TC_OP_ATOMIC_FMIN_64 = 98 -TC_OP_ATOMIC_FMAX_64 = 99 -TC_OP_RESERVED_FOP_64_0 = 100 -TC_OP_RESERVED_FOP_64_1 = 101 -TC_OP_RESERVED_FOP_64_2 = 102 -TC_OP_ATOMIC_SWAP_64 = 103 -TC_OP_ATOMIC_CMPSWAP_64 = 104 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 -TC_OP_ATOMIC_ADD_64 = 111 -TC_OP_ATOMIC_SUB_64 = 112 -TC_OP_ATOMIC_SMIN_64 = 113 -TC_OP_ATOMIC_UMIN_64 = 114 -TC_OP_ATOMIC_SMAX_64 = 115 -TC_OP_ATOMIC_UMAX_64 = 116 -TC_OP_ATOMIC_AND_64 = 117 -TC_OP_ATOMIC_OR_64 = 118 -TC_OP_ATOMIC_XOR_64 = 119 -TC_OP_ATOMIC_INC_64 = 120 -TC_OP_ATOMIC_DEC_64 = 121 -TC_OP_WBINVL2_NC = 122 -TC_OP_NOP_ACK = 123 -TC_OP_RESERVED_NON_FLOAT_64_1 = 124 -TC_OP_RESERVED_NON_FLOAT_64_2 = 125 -TC_OP_RESERVED_NON_FLOAT_64_3 = 126 -TC_OP_RESERVED_NON_FLOAT_64_4 = 127 -TC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'TC_CHUB_REQ_CREDITS_ENUM' -TC_CHUB_REQ_CREDITS_ENUM__enumvalues = { - 16: 'TC_CHUB_REQ_CREDITS', -} -TC_CHUB_REQ_CREDITS = 16 -TC_CHUB_REQ_CREDITS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CHUB_TC_RET_CREDITS_ENUM' -CHUB_TC_RET_CREDITS_ENUM__enumvalues = { - 32: 'CHUB_TC_RET_CREDITS', -} -CHUB_TC_RET_CREDITS = 32 -CHUB_TC_RET_CREDITS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TC_NACKS' -TC_NACKS__enumvalues = { - 0: 'TC_NACK_NO_FAULT', - 1: 'TC_NACK_PAGE_FAULT', - 2: 'TC_NACK_PROTECTION_FAULT', - 3: 'TC_NACK_DATA_ERROR', -} -TC_NACK_NO_FAULT = 0 -TC_NACK_PAGE_FAULT = 1 -TC_NACK_PROTECTION_FAULT = 2 -TC_NACK_DATA_ERROR = 3 -TC_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_EA_CID' -TC_EA_CID__enumvalues = { - 0: 'TC_EA_CID_RT', - 1: 'TC_EA_CID_FMASK', - 2: 'TC_EA_CID_DCC', - 3: 'TC_EA_CID_TCPMETA', - 4: 'TC_EA_CID_Z', - 5: 'TC_EA_CID_STENCIL', - 6: 'TC_EA_CID_HTILE', - 7: 'TC_EA_CID_MISC', - 8: 'TC_EA_CID_TCP', - 9: 'TC_EA_CID_SQC', - 10: 'TC_EA_CID_CPF', - 11: 'TC_EA_CID_CPG', - 12: 'TC_EA_CID_IA', - 13: 'TC_EA_CID_WD', - 14: 'TC_EA_CID_PA', - 15: 'TC_EA_CID_UTCL2_TPI', -} -TC_EA_CID_RT = 0 -TC_EA_CID_FMASK = 1 -TC_EA_CID_DCC = 2 -TC_EA_CID_TCPMETA = 3 -TC_EA_CID_Z = 4 -TC_EA_CID_STENCIL = 5 -TC_EA_CID_HTILE = 6 -TC_EA_CID_MISC = 7 -TC_EA_CID_TCP = 8 -TC_EA_CID_SQC = 9 -TC_EA_CID_CPF = 10 -TC_EA_CID_CPG = 11 -TC_EA_CID_IA = 12 -TC_EA_CID_WD = 13 -TC_EA_CID_PA = 14 -TC_EA_CID_UTCL2_TPI = 15 -TC_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SAMPLE_CNTL' -SPI_SAMPLE_CNTL__enumvalues = { - 0: 'CENTROIDS_ONLY', - 1: 'CENTERS_ONLY', - 2: 'CENTROIDS_AND_CENTERS', - 3: 'UNDEF', -} -CENTROIDS_ONLY = 0 -CENTERS_ONLY = 1 -CENTROIDS_AND_CENTERS = 2 -UNDEF = 3 -SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_FOG_MODE' -SPI_FOG_MODE__enumvalues = { - 0: 'SPI_FOG_NONE', - 1: 'SPI_FOG_EXP', - 2: 'SPI_FOG_EXP2', - 3: 'SPI_FOG_LINEAR', -} -SPI_FOG_NONE = 0 -SPI_FOG_EXP = 1 -SPI_FOG_EXP2 = 2 -SPI_FOG_LINEAR = 3 -SPI_FOG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' -SPI_PNT_SPRITE_OVERRIDE__enumvalues = { - 0: 'SPI_PNT_SPRITE_SEL_0', - 1: 'SPI_PNT_SPRITE_SEL_1', - 2: 'SPI_PNT_SPRITE_SEL_S', - 3: 'SPI_PNT_SPRITE_SEL_T', - 4: 'SPI_PNT_SPRITE_SEL_NONE', -} -SPI_PNT_SPRITE_SEL_0 = 0 -SPI_PNT_SPRITE_SEL_1 = 1 -SPI_PNT_SPRITE_SEL_S = 2 -SPI_PNT_SPRITE_SEL_T = 3 -SPI_PNT_SPRITE_SEL_NONE = 4 -SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PERFCNT_SEL' -SPI_PERFCNT_SEL__enumvalues = { - 0: 'SPI_PERF_VS_WINDOW_VALID', - 1: 'SPI_PERF_VS_BUSY', - 2: 'SPI_PERF_VS_FIRST_WAVE', - 3: 'SPI_PERF_VS_LAST_WAVE', - 4: 'SPI_PERF_VS_LSHS_DEALLOC', - 5: 'SPI_PERF_VS_PC_STALL', - 6: 'SPI_PERF_VS_POS0_STALL', - 7: 'SPI_PERF_VS_POS1_STALL', - 8: 'SPI_PERF_VS_CRAWLER_STALL', - 9: 'SPI_PERF_VS_EVENT_WAVE', - 10: 'SPI_PERF_VS_WAVE', - 11: 'SPI_PERF_VS_PERS_UPD_FULL0', - 12: 'SPI_PERF_VS_PERS_UPD_FULL1', - 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', - 14: 'SPI_PERF_VS_FIRST_SUBGRP', - 15: 'SPI_PERF_VS_LAST_SUBGRP', - 16: 'SPI_PERF_GS_WINDOW_VALID', - 17: 'SPI_PERF_GS_BUSY', - 18: 'SPI_PERF_GS_CRAWLER_STALL', - 19: 'SPI_PERF_GS_EVENT_WAVE', - 20: 'SPI_PERF_GS_WAVE', - 21: 'SPI_PERF_GS_PERS_UPD_FULL0', - 22: 'SPI_PERF_GS_PERS_UPD_FULL1', - 23: 'SPI_PERF_GS_FIRST_SUBGRP', - 24: 'SPI_PERF_GS_LAST_SUBGRP', - 25: 'SPI_PERF_ES_WINDOW_VALID', - 26: 'SPI_PERF_ES_BUSY', - 27: 'SPI_PERF_ES_CRAWLER_STALL', - 28: 'SPI_PERF_ES_FIRST_WAVE', - 29: 'SPI_PERF_ES_LAST_WAVE', - 30: 'SPI_PERF_ES_LSHS_DEALLOC', - 31: 'SPI_PERF_ES_EVENT_WAVE', - 32: 'SPI_PERF_ES_WAVE', - 33: 'SPI_PERF_ES_PERS_UPD_FULL0', - 34: 'SPI_PERF_ES_PERS_UPD_FULL1', - 35: 'SPI_PERF_ES_FIRST_SUBGRP', - 36: 'SPI_PERF_ES_LAST_SUBGRP', - 37: 'SPI_PERF_HS_WINDOW_VALID', - 38: 'SPI_PERF_HS_BUSY', - 39: 'SPI_PERF_HS_CRAWLER_STALL', - 40: 'SPI_PERF_HS_FIRST_WAVE', - 41: 'SPI_PERF_HS_LAST_WAVE', - 42: 'SPI_PERF_HS_LSHS_DEALLOC', - 43: 'SPI_PERF_HS_EVENT_WAVE', - 44: 'SPI_PERF_HS_WAVE', - 45: 'SPI_PERF_HS_PERS_UPD_FULL0', - 46: 'SPI_PERF_HS_PERS_UPD_FULL1', - 47: 'SPI_PERF_LS_WINDOW_VALID', - 48: 'SPI_PERF_LS_BUSY', - 49: 'SPI_PERF_LS_CRAWLER_STALL', - 50: 'SPI_PERF_LS_FIRST_WAVE', - 51: 'SPI_PERF_LS_LAST_WAVE', - 52: 'SPI_PERF_OFFCHIP_LDS_STALL_LS', - 53: 'SPI_PERF_LS_EVENT_WAVE', - 54: 'SPI_PERF_LS_WAVE', - 55: 'SPI_PERF_LS_PERS_UPD_FULL0', - 56: 'SPI_PERF_LS_PERS_UPD_FULL1', - 57: 'SPI_PERF_CSG_WINDOW_VALID', - 58: 'SPI_PERF_CSG_BUSY', - 59: 'SPI_PERF_CSG_NUM_THREADGROUPS', - 60: 'SPI_PERF_CSG_CRAWLER_STALL', - 61: 'SPI_PERF_CSG_EVENT_WAVE', - 62: 'SPI_PERF_CSG_WAVE', - 63: 'SPI_PERF_CSN_WINDOW_VALID', - 64: 'SPI_PERF_CSN_BUSY', - 65: 'SPI_PERF_CSN_NUM_THREADGROUPS', - 66: 'SPI_PERF_CSN_CRAWLER_STALL', - 67: 'SPI_PERF_CSN_EVENT_WAVE', - 68: 'SPI_PERF_CSN_WAVE', - 69: 'SPI_PERF_PS_CTL_WINDOW_VALID', - 70: 'SPI_PERF_PS_CTL_BUSY', - 71: 'SPI_PERF_PS_CTL_ACTIVE', - 72: 'SPI_PERF_PS_CTL_DEALLOC_BIN0', - 73: 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', - 74: 'SPI_PERF_PS_CTL_EVENT_WAVE', - 75: 'SPI_PERF_PS_CTL_WAVE', - 76: 'SPI_PERF_PS_CTL_OPT_WAVE', - 77: 'SPI_PERF_PS_CTL_PASS_BIN0', - 78: 'SPI_PERF_PS_CTL_PASS_BIN1', - 79: 'SPI_PERF_PS_CTL_FPOS_BIN2', - 80: 'SPI_PERF_PS_CTL_PRIM_BIN0', - 81: 'SPI_PERF_PS_CTL_PRIM_BIN1', - 82: 'SPI_PERF_PS_CTL_CNF_BIN2', - 83: 'SPI_PERF_PS_CTL_CNF_BIN3', - 84: 'SPI_PERF_PS_CTL_CRAWLER_STALL', - 85: 'SPI_PERF_PS_CTL_LDS_RES_FULL', - 86: 'SPI_PERF_PS_PERS_UPD_FULL0', - 87: 'SPI_PERF_PS_PERS_UPD_FULL1', - 88: 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 89: 'SPI_PERF_PIX_ALLOC_SCB_STALL', - 90: 'SPI_PERF_PIX_ALLOC_DB0_STALL', - 91: 'SPI_PERF_PIX_ALLOC_DB1_STALL', - 92: 'SPI_PERF_PIX_ALLOC_DB2_STALL', - 93: 'SPI_PERF_PIX_ALLOC_DB3_STALL', - 94: 'SPI_PERF_LDS0_PC_VALID', - 95: 'SPI_PERF_LDS1_PC_VALID', - 96: 'SPI_PERF_RA_PIPE_REQ_BIN2', - 97: 'SPI_PERF_RA_TASK_REQ_BIN3', - 98: 'SPI_PERF_RA_WR_CTL_FULL', - 99: 'SPI_PERF_RA_REQ_NO_ALLOC', - 100: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 101: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', - 102: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 103: 'SPI_PERF_RA_REQ_NO_ALLOC_ES', - 104: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 105: 'SPI_PERF_RA_REQ_NO_ALLOC_LS', - 106: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 107: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 108: 'SPI_PERF_RA_RES_STALL_PS', - 109: 'SPI_PERF_RA_RES_STALL_VS', - 110: 'SPI_PERF_RA_RES_STALL_GS', - 111: 'SPI_PERF_RA_RES_STALL_ES', - 112: 'SPI_PERF_RA_RES_STALL_HS', - 113: 'SPI_PERF_RA_RES_STALL_LS', - 114: 'SPI_PERF_RA_RES_STALL_CSG', - 115: 'SPI_PERF_RA_RES_STALL_CSN', - 116: 'SPI_PERF_RA_TMP_STALL_PS', - 117: 'SPI_PERF_RA_TMP_STALL_VS', - 118: 'SPI_PERF_RA_TMP_STALL_GS', - 119: 'SPI_PERF_RA_TMP_STALL_ES', - 120: 'SPI_PERF_RA_TMP_STALL_HS', - 121: 'SPI_PERF_RA_TMP_STALL_LS', - 122: 'SPI_PERF_RA_TMP_STALL_CSG', - 123: 'SPI_PERF_RA_TMP_STALL_CSN', - 124: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 125: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', - 126: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 127: 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', - 128: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 129: 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', - 130: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 131: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', - 132: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 133: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', - 134: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 135: 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', - 136: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 137: 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', - 138: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 139: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', - 140: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', - 141: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', - 142: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', - 143: 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', - 144: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', - 145: 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', - 146: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', - 147: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', - 148: 'SPI_PERF_RA_LDS_CU_FULL_PS', - 149: 'SPI_PERF_RA_LDS_CU_FULL_LS', - 150: 'SPI_PERF_RA_LDS_CU_FULL_ES', - 151: 'SPI_PERF_RA_LDS_CU_FULL_CSG', - 152: 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 153: 'SPI_PERF_RA_BAR_CU_FULL_HS', - 154: 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 155: 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 156: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 157: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 158: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', - 159: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 160: 'SPI_PERF_RA_WVLIM_STALL_PS', - 161: 'SPI_PERF_RA_WVLIM_STALL_VS', - 162: 'SPI_PERF_RA_WVLIM_STALL_GS', - 163: 'SPI_PERF_RA_WVLIM_STALL_ES', - 164: 'SPI_PERF_RA_WVLIM_STALL_HS', - 165: 'SPI_PERF_RA_WVLIM_STALL_LS', - 166: 'SPI_PERF_RA_WVLIM_STALL_CSG', - 167: 'SPI_PERF_RA_WVLIM_STALL_CSN', - 168: 'SPI_PERF_RA_PS_LOCK_NA', - 169: 'SPI_PERF_RA_VS_LOCK', - 170: 'SPI_PERF_RA_GS_LOCK', - 171: 'SPI_PERF_RA_ES_LOCK', - 172: 'SPI_PERF_RA_HS_LOCK', - 173: 'SPI_PERF_RA_LS_LOCK', - 174: 'SPI_PERF_RA_CSG_LOCK', - 175: 'SPI_PERF_RA_CSN_LOCK', - 176: 'SPI_PERF_RA_RSV_UPD', - 177: 'SPI_PERF_EXP_ARB_COL_CNT', - 178: 'SPI_PERF_EXP_ARB_PAR_CNT', - 179: 'SPI_PERF_EXP_ARB_POS_CNT', - 180: 'SPI_PERF_EXP_ARB_GDS_CNT', - 181: 'SPI_PERF_CLKGATE_BUSY_STALL', - 182: 'SPI_PERF_CLKGATE_ACTIVE_STALL', - 183: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', - 184: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', - 185: 'SPI_PERF_CLKGATE_CGTT_REG_ON', - 186: 'SPI_PERF_NUM_VS_POS_EXPORTS', - 187: 'SPI_PERF_NUM_VS_PARAM_EXPORTS', - 188: 'SPI_PERF_NUM_PS_COL_EXPORTS', - 189: 'SPI_PERF_ES_GRP_FIFO_FULL', - 190: 'SPI_PERF_GS_GRP_FIFO_FULL', - 191: 'SPI_PERF_HS_GRP_FIFO_FULL', - 192: 'SPI_PERF_LS_GRP_FIFO_FULL', - 193: 'SPI_PERF_VS_ALLOC_CNT', - 194: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', - 195: 'SPI_PERF_PC_ALLOC_CNT', - 196: 'SPI_PERF_PC_ALLOC_ACCUM', -} -SPI_PERF_VS_WINDOW_VALID = 0 -SPI_PERF_VS_BUSY = 1 -SPI_PERF_VS_FIRST_WAVE = 2 -SPI_PERF_VS_LAST_WAVE = 3 -SPI_PERF_VS_LSHS_DEALLOC = 4 -SPI_PERF_VS_PC_STALL = 5 -SPI_PERF_VS_POS0_STALL = 6 -SPI_PERF_VS_POS1_STALL = 7 -SPI_PERF_VS_CRAWLER_STALL = 8 -SPI_PERF_VS_EVENT_WAVE = 9 -SPI_PERF_VS_WAVE = 10 -SPI_PERF_VS_PERS_UPD_FULL0 = 11 -SPI_PERF_VS_PERS_UPD_FULL1 = 12 -SPI_PERF_VS_LATE_ALLOC_FULL = 13 -SPI_PERF_VS_FIRST_SUBGRP = 14 -SPI_PERF_VS_LAST_SUBGRP = 15 -SPI_PERF_GS_WINDOW_VALID = 16 -SPI_PERF_GS_BUSY = 17 -SPI_PERF_GS_CRAWLER_STALL = 18 -SPI_PERF_GS_EVENT_WAVE = 19 -SPI_PERF_GS_WAVE = 20 -SPI_PERF_GS_PERS_UPD_FULL0 = 21 -SPI_PERF_GS_PERS_UPD_FULL1 = 22 -SPI_PERF_GS_FIRST_SUBGRP = 23 -SPI_PERF_GS_LAST_SUBGRP = 24 -SPI_PERF_ES_WINDOW_VALID = 25 -SPI_PERF_ES_BUSY = 26 -SPI_PERF_ES_CRAWLER_STALL = 27 -SPI_PERF_ES_FIRST_WAVE = 28 -SPI_PERF_ES_LAST_WAVE = 29 -SPI_PERF_ES_LSHS_DEALLOC = 30 -SPI_PERF_ES_EVENT_WAVE = 31 -SPI_PERF_ES_WAVE = 32 -SPI_PERF_ES_PERS_UPD_FULL0 = 33 -SPI_PERF_ES_PERS_UPD_FULL1 = 34 -SPI_PERF_ES_FIRST_SUBGRP = 35 -SPI_PERF_ES_LAST_SUBGRP = 36 -SPI_PERF_HS_WINDOW_VALID = 37 -SPI_PERF_HS_BUSY = 38 -SPI_PERF_HS_CRAWLER_STALL = 39 -SPI_PERF_HS_FIRST_WAVE = 40 -SPI_PERF_HS_LAST_WAVE = 41 -SPI_PERF_HS_LSHS_DEALLOC = 42 -SPI_PERF_HS_EVENT_WAVE = 43 -SPI_PERF_HS_WAVE = 44 -SPI_PERF_HS_PERS_UPD_FULL0 = 45 -SPI_PERF_HS_PERS_UPD_FULL1 = 46 -SPI_PERF_LS_WINDOW_VALID = 47 -SPI_PERF_LS_BUSY = 48 -SPI_PERF_LS_CRAWLER_STALL = 49 -SPI_PERF_LS_FIRST_WAVE = 50 -SPI_PERF_LS_LAST_WAVE = 51 -SPI_PERF_OFFCHIP_LDS_STALL_LS = 52 -SPI_PERF_LS_EVENT_WAVE = 53 -SPI_PERF_LS_WAVE = 54 -SPI_PERF_LS_PERS_UPD_FULL0 = 55 -SPI_PERF_LS_PERS_UPD_FULL1 = 56 -SPI_PERF_CSG_WINDOW_VALID = 57 -SPI_PERF_CSG_BUSY = 58 -SPI_PERF_CSG_NUM_THREADGROUPS = 59 -SPI_PERF_CSG_CRAWLER_STALL = 60 -SPI_PERF_CSG_EVENT_WAVE = 61 -SPI_PERF_CSG_WAVE = 62 -SPI_PERF_CSN_WINDOW_VALID = 63 -SPI_PERF_CSN_BUSY = 64 -SPI_PERF_CSN_NUM_THREADGROUPS = 65 -SPI_PERF_CSN_CRAWLER_STALL = 66 -SPI_PERF_CSN_EVENT_WAVE = 67 -SPI_PERF_CSN_WAVE = 68 -SPI_PERF_PS_CTL_WINDOW_VALID = 69 -SPI_PERF_PS_CTL_BUSY = 70 -SPI_PERF_PS_CTL_ACTIVE = 71 -SPI_PERF_PS_CTL_DEALLOC_BIN0 = 72 -SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 73 -SPI_PERF_PS_CTL_EVENT_WAVE = 74 -SPI_PERF_PS_CTL_WAVE = 75 -SPI_PERF_PS_CTL_OPT_WAVE = 76 -SPI_PERF_PS_CTL_PASS_BIN0 = 77 -SPI_PERF_PS_CTL_PASS_BIN1 = 78 -SPI_PERF_PS_CTL_FPOS_BIN2 = 79 -SPI_PERF_PS_CTL_PRIM_BIN0 = 80 -SPI_PERF_PS_CTL_PRIM_BIN1 = 81 -SPI_PERF_PS_CTL_CNF_BIN2 = 82 -SPI_PERF_PS_CTL_CNF_BIN3 = 83 -SPI_PERF_PS_CTL_CRAWLER_STALL = 84 -SPI_PERF_PS_CTL_LDS_RES_FULL = 85 -SPI_PERF_PS_PERS_UPD_FULL0 = 86 -SPI_PERF_PS_PERS_UPD_FULL1 = 87 -SPI_PERF_PIX_ALLOC_PEND_CNT = 88 -SPI_PERF_PIX_ALLOC_SCB_STALL = 89 -SPI_PERF_PIX_ALLOC_DB0_STALL = 90 -SPI_PERF_PIX_ALLOC_DB1_STALL = 91 -SPI_PERF_PIX_ALLOC_DB2_STALL = 92 -SPI_PERF_PIX_ALLOC_DB3_STALL = 93 -SPI_PERF_LDS0_PC_VALID = 94 -SPI_PERF_LDS1_PC_VALID = 95 -SPI_PERF_RA_PIPE_REQ_BIN2 = 96 -SPI_PERF_RA_TASK_REQ_BIN3 = 97 -SPI_PERF_RA_WR_CTL_FULL = 98 -SPI_PERF_RA_REQ_NO_ALLOC = 99 -SPI_PERF_RA_REQ_NO_ALLOC_PS = 100 -SPI_PERF_RA_REQ_NO_ALLOC_VS = 101 -SPI_PERF_RA_REQ_NO_ALLOC_GS = 102 -SPI_PERF_RA_REQ_NO_ALLOC_ES = 103 -SPI_PERF_RA_REQ_NO_ALLOC_HS = 104 -SPI_PERF_RA_REQ_NO_ALLOC_LS = 105 -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 106 -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 107 -SPI_PERF_RA_RES_STALL_PS = 108 -SPI_PERF_RA_RES_STALL_VS = 109 -SPI_PERF_RA_RES_STALL_GS = 110 -SPI_PERF_RA_RES_STALL_ES = 111 -SPI_PERF_RA_RES_STALL_HS = 112 -SPI_PERF_RA_RES_STALL_LS = 113 -SPI_PERF_RA_RES_STALL_CSG = 114 -SPI_PERF_RA_RES_STALL_CSN = 115 -SPI_PERF_RA_TMP_STALL_PS = 116 -SPI_PERF_RA_TMP_STALL_VS = 117 -SPI_PERF_RA_TMP_STALL_GS = 118 -SPI_PERF_RA_TMP_STALL_ES = 119 -SPI_PERF_RA_TMP_STALL_HS = 120 -SPI_PERF_RA_TMP_STALL_LS = 121 -SPI_PERF_RA_TMP_STALL_CSG = 122 -SPI_PERF_RA_TMP_STALL_CSN = 123 -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 124 -SPI_PERF_RA_WAVE_SIMD_FULL_VS = 125 -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 126 -SPI_PERF_RA_WAVE_SIMD_FULL_ES = 127 -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 128 -SPI_PERF_RA_WAVE_SIMD_FULL_LS = 129 -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 130 -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 131 -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 132 -SPI_PERF_RA_VGPR_SIMD_FULL_VS = 133 -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 134 -SPI_PERF_RA_VGPR_SIMD_FULL_ES = 135 -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 136 -SPI_PERF_RA_VGPR_SIMD_FULL_LS = 137 -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 138 -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 139 -SPI_PERF_RA_SGPR_SIMD_FULL_PS = 140 -SPI_PERF_RA_SGPR_SIMD_FULL_VS = 141 -SPI_PERF_RA_SGPR_SIMD_FULL_GS = 142 -SPI_PERF_RA_SGPR_SIMD_FULL_ES = 143 -SPI_PERF_RA_SGPR_SIMD_FULL_HS = 144 -SPI_PERF_RA_SGPR_SIMD_FULL_LS = 145 -SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 146 -SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 147 -SPI_PERF_RA_LDS_CU_FULL_PS = 148 -SPI_PERF_RA_LDS_CU_FULL_LS = 149 -SPI_PERF_RA_LDS_CU_FULL_ES = 150 -SPI_PERF_RA_LDS_CU_FULL_CSG = 151 -SPI_PERF_RA_LDS_CU_FULL_CSN = 152 -SPI_PERF_RA_BAR_CU_FULL_HS = 153 -SPI_PERF_RA_BAR_CU_FULL_CSG = 154 -SPI_PERF_RA_BAR_CU_FULL_CSN = 155 -SPI_PERF_RA_BULKY_CU_FULL_CSG = 156 -SPI_PERF_RA_BULKY_CU_FULL_CSN = 157 -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 158 -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 159 -SPI_PERF_RA_WVLIM_STALL_PS = 160 -SPI_PERF_RA_WVLIM_STALL_VS = 161 -SPI_PERF_RA_WVLIM_STALL_GS = 162 -SPI_PERF_RA_WVLIM_STALL_ES = 163 -SPI_PERF_RA_WVLIM_STALL_HS = 164 -SPI_PERF_RA_WVLIM_STALL_LS = 165 -SPI_PERF_RA_WVLIM_STALL_CSG = 166 -SPI_PERF_RA_WVLIM_STALL_CSN = 167 -SPI_PERF_RA_PS_LOCK_NA = 168 -SPI_PERF_RA_VS_LOCK = 169 -SPI_PERF_RA_GS_LOCK = 170 -SPI_PERF_RA_ES_LOCK = 171 -SPI_PERF_RA_HS_LOCK = 172 -SPI_PERF_RA_LS_LOCK = 173 -SPI_PERF_RA_CSG_LOCK = 174 -SPI_PERF_RA_CSN_LOCK = 175 -SPI_PERF_RA_RSV_UPD = 176 -SPI_PERF_EXP_ARB_COL_CNT = 177 -SPI_PERF_EXP_ARB_PAR_CNT = 178 -SPI_PERF_EXP_ARB_POS_CNT = 179 -SPI_PERF_EXP_ARB_GDS_CNT = 180 -SPI_PERF_CLKGATE_BUSY_STALL = 181 -SPI_PERF_CLKGATE_ACTIVE_STALL = 182 -SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 183 -SPI_PERF_CLKGATE_CGTT_DYN_ON = 184 -SPI_PERF_CLKGATE_CGTT_REG_ON = 185 -SPI_PERF_NUM_VS_POS_EXPORTS = 186 -SPI_PERF_NUM_VS_PARAM_EXPORTS = 187 -SPI_PERF_NUM_PS_COL_EXPORTS = 188 -SPI_PERF_ES_GRP_FIFO_FULL = 189 -SPI_PERF_GS_GRP_FIFO_FULL = 190 -SPI_PERF_HS_GRP_FIFO_FULL = 191 -SPI_PERF_LS_GRP_FIFO_FULL = 192 -SPI_PERF_VS_ALLOC_CNT = 193 -SPI_PERF_VS_LATE_ALLOC_ACCUM = 194 -SPI_PERF_PC_ALLOC_CNT = 195 -SPI_PERF_PC_ALLOC_ACCUM = 196 -SPI_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_FORMAT' -SPI_SHADER_FORMAT__enumvalues = { - 0: 'SPI_SHADER_NONE', - 1: 'SPI_SHADER_1COMP', - 2: 'SPI_SHADER_2COMP', - 3: 'SPI_SHADER_4COMPRESS', - 4: 'SPI_SHADER_4COMP', -} -SPI_SHADER_NONE = 0 -SPI_SHADER_1COMP = 1 -SPI_SHADER_2COMP = 2 -SPI_SHADER_4COMPRESS = 3 -SPI_SHADER_4COMP = 4 -SPI_SHADER_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_EX_FORMAT' -SPI_SHADER_EX_FORMAT__enumvalues = { - 0: 'SPI_SHADER_ZERO', - 1: 'SPI_SHADER_32_R', - 2: 'SPI_SHADER_32_GR', - 3: 'SPI_SHADER_32_AR', - 4: 'SPI_SHADER_FP16_ABGR', - 5: 'SPI_SHADER_UNORM16_ABGR', - 6: 'SPI_SHADER_SNORM16_ABGR', - 7: 'SPI_SHADER_UINT16_ABGR', - 8: 'SPI_SHADER_SINT16_ABGR', - 9: 'SPI_SHADER_32_ABGR', -} -SPI_SHADER_ZERO = 0 -SPI_SHADER_32_R = 1 -SPI_SHADER_32_GR = 2 -SPI_SHADER_32_AR = 3 -SPI_SHADER_FP16_ABGR = 4 -SPI_SHADER_UNORM16_ABGR = 5 -SPI_SHADER_SNORM16_ABGR = 6 -SPI_SHADER_UINT16_ABGR = 7 -SPI_SHADER_SINT16_ABGR = 8 -SPI_SHADER_32_ABGR = 9 -SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_SM_MODE' -CLKGATE_SM_MODE__enumvalues = { - 0: 'ON_SEQ', - 1: 'OFF_SEQ', - 2: 'PROG_SEQ', - 3: 'READ_SEQ', - 4: 'SM_MODE_RESERVED', -} -ON_SEQ = 0 -OFF_SEQ = 1 -PROG_SEQ = 2 -READ_SEQ = 3 -SM_MODE_RESERVED = 4 -CLKGATE_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_BASE_MODE' -CLKGATE_BASE_MODE__enumvalues = { - 0: 'MULT_8', - 1: 'MULT_16', -} -MULT_8 = 0 -MULT_16 = 1 -CLKGATE_BASE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_CLAMP' -SQ_TEX_CLAMP__enumvalues = { - 0: 'SQ_TEX_WRAP', - 1: 'SQ_TEX_MIRROR', - 2: 'SQ_TEX_CLAMP_LAST_TEXEL', - 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 4: 'SQ_TEX_CLAMP_HALF_BORDER', - 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', - 6: 'SQ_TEX_CLAMP_BORDER', - 7: 'SQ_TEX_MIRROR_ONCE_BORDER', -} -SQ_TEX_WRAP = 0 -SQ_TEX_MIRROR = 1 -SQ_TEX_CLAMP_LAST_TEXEL = 2 -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 -SQ_TEX_CLAMP_HALF_BORDER = 4 -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 -SQ_TEX_CLAMP_BORDER = 6 -SQ_TEX_MIRROR_ONCE_BORDER = 7 -SQ_TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_XY_FILTER' -SQ_TEX_XY_FILTER__enumvalues = { - 0: 'SQ_TEX_XY_FILTER_POINT', - 1: 'SQ_TEX_XY_FILTER_BILINEAR', - 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', - 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', -} -SQ_TEX_XY_FILTER_POINT = 0 -SQ_TEX_XY_FILTER_BILINEAR = 1 -SQ_TEX_XY_FILTER_ANISO_POINT = 2 -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 -SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_Z_FILTER' -SQ_TEX_Z_FILTER__enumvalues = { - 0: 'SQ_TEX_Z_FILTER_NONE', - 1: 'SQ_TEX_Z_FILTER_POINT', - 2: 'SQ_TEX_Z_FILTER_LINEAR', -} -SQ_TEX_Z_FILTER_NONE = 0 -SQ_TEX_Z_FILTER_POINT = 1 -SQ_TEX_Z_FILTER_LINEAR = 2 -SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_MIP_FILTER' -SQ_TEX_MIP_FILTER__enumvalues = { - 0: 'SQ_TEX_MIP_FILTER_NONE', - 1: 'SQ_TEX_MIP_FILTER_POINT', - 2: 'SQ_TEX_MIP_FILTER_LINEAR', - 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', -} -SQ_TEX_MIP_FILTER_NONE = 0 -SQ_TEX_MIP_FILTER_POINT = 1 -SQ_TEX_MIP_FILTER_LINEAR = 2 -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 -SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_ANISO_RATIO' -SQ_TEX_ANISO_RATIO__enumvalues = { - 0: 'SQ_TEX_ANISO_RATIO_1', - 1: 'SQ_TEX_ANISO_RATIO_2', - 2: 'SQ_TEX_ANISO_RATIO_4', - 3: 'SQ_TEX_ANISO_RATIO_8', - 4: 'SQ_TEX_ANISO_RATIO_16', -} -SQ_TEX_ANISO_RATIO_1 = 0 -SQ_TEX_ANISO_RATIO_2 = 1 -SQ_TEX_ANISO_RATIO_4 = 2 -SQ_TEX_ANISO_RATIO_8 = 3 -SQ_TEX_ANISO_RATIO_16 = 4 -SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_DEPTH_COMPARE' -SQ_TEX_DEPTH_COMPARE__enumvalues = { - 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', - 1: 'SQ_TEX_DEPTH_COMPARE_LESS', - 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', - 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', - 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', - 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', - 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', -} -SQ_TEX_DEPTH_COMPARE_NEVER = 0 -SQ_TEX_DEPTH_COMPARE_LESS = 1 -SQ_TEX_DEPTH_COMPARE_EQUAL = 2 -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 -SQ_TEX_DEPTH_COMPARE_GREATER = 4 -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 -SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 -SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_BORDER_COLOR' -SQ_TEX_BORDER_COLOR__enumvalues = { - 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 3: 'SQ_TEX_BORDER_COLOR_REGISTER', -} -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 -SQ_TEX_BORDER_COLOR_REGISTER = 3 -SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_BUF_TYPE' -SQ_RSRC_BUF_TYPE__enumvalues = { - 0: 'SQ_RSRC_BUF', - 1: 'SQ_RSRC_BUF_RSVD_1', - 2: 'SQ_RSRC_BUF_RSVD_2', - 3: 'SQ_RSRC_BUF_RSVD_3', -} -SQ_RSRC_BUF = 0 -SQ_RSRC_BUF_RSVD_1 = 1 -SQ_RSRC_BUF_RSVD_2 = 2 -SQ_RSRC_BUF_RSVD_3 = 3 -SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_IMG_TYPE' -SQ_RSRC_IMG_TYPE__enumvalues = { - 0: 'SQ_RSRC_IMG_RSVD_0', - 1: 'SQ_RSRC_IMG_RSVD_1', - 2: 'SQ_RSRC_IMG_RSVD_2', - 3: 'SQ_RSRC_IMG_RSVD_3', - 4: 'SQ_RSRC_IMG_RSVD_4', - 5: 'SQ_RSRC_IMG_RSVD_5', - 6: 'SQ_RSRC_IMG_RSVD_6', - 7: 'SQ_RSRC_IMG_RSVD_7', - 8: 'SQ_RSRC_IMG_1D', - 9: 'SQ_RSRC_IMG_2D', - 10: 'SQ_RSRC_IMG_3D', - 11: 'SQ_RSRC_IMG_CUBE', - 12: 'SQ_RSRC_IMG_1D_ARRAY', - 13: 'SQ_RSRC_IMG_2D_ARRAY', - 14: 'SQ_RSRC_IMG_2D_MSAA', - 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', -} -SQ_RSRC_IMG_RSVD_0 = 0 -SQ_RSRC_IMG_RSVD_1 = 1 -SQ_RSRC_IMG_RSVD_2 = 2 -SQ_RSRC_IMG_RSVD_3 = 3 -SQ_RSRC_IMG_RSVD_4 = 4 -SQ_RSRC_IMG_RSVD_5 = 5 -SQ_RSRC_IMG_RSVD_6 = 6 -SQ_RSRC_IMG_RSVD_7 = 7 -SQ_RSRC_IMG_1D = 8 -SQ_RSRC_IMG_2D = 9 -SQ_RSRC_IMG_3D = 10 -SQ_RSRC_IMG_CUBE = 11 -SQ_RSRC_IMG_1D_ARRAY = 12 -SQ_RSRC_IMG_2D_ARRAY = 13 -SQ_RSRC_IMG_2D_MSAA = 14 -SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 -SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_FLAT_TYPE' -SQ_RSRC_FLAT_TYPE__enumvalues = { - 0: 'SQ_RSRC_FLAT_RSVD_0', - 1: 'SQ_RSRC_FLAT', - 2: 'SQ_RSRC_FLAT_RSVD_2', - 3: 'SQ_RSRC_FLAT_RSVD_3', -} -SQ_RSRC_FLAT_RSVD_0 = 0 -SQ_RSRC_FLAT = 1 -SQ_RSRC_FLAT_RSVD_2 = 2 -SQ_RSRC_FLAT_RSVD_3 = 3 -SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IMG_FILTER_TYPE' -SQ_IMG_FILTER_TYPE__enumvalues = { - 0: 'SQ_IMG_FILTER_MODE_BLEND', - 1: 'SQ_IMG_FILTER_MODE_MIN', - 2: 'SQ_IMG_FILTER_MODE_MAX', -} -SQ_IMG_FILTER_MODE_BLEND = 0 -SQ_IMG_FILTER_MODE_MIN = 1 -SQ_IMG_FILTER_MODE_MAX = 2 -SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_SEL_XYZW01' -SQ_SEL_XYZW01__enumvalues = { - 0: 'SQ_SEL_0', - 1: 'SQ_SEL_1', - 2: 'SQ_SEL_RESERVED_0', - 3: 'SQ_SEL_RESERVED_1', - 4: 'SQ_SEL_X', - 5: 'SQ_SEL_Y', - 6: 'SQ_SEL_Z', - 7: 'SQ_SEL_W', -} -SQ_SEL_0 = 0 -SQ_SEL_1 = 1 -SQ_SEL_RESERVED_0 = 2 -SQ_SEL_RESERVED_1 = 3 -SQ_SEL_X = 4 -SQ_SEL_Y = 5 -SQ_SEL_Z = 6 -SQ_SEL_W = 7 -SQ_SEL_XYZW01 = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_TYPE' -SQ_WAVE_TYPE__enumvalues = { - 0: 'SQ_WAVE_TYPE_PS', - 1: 'SQ_WAVE_TYPE_VS', - 2: 'SQ_WAVE_TYPE_GS', - 3: 'SQ_WAVE_TYPE_ES', - 4: 'SQ_WAVE_TYPE_HS', - 5: 'SQ_WAVE_TYPE_LS', - 6: 'SQ_WAVE_TYPE_CS', - 7: 'SQ_WAVE_TYPE_PS1', -} -SQ_WAVE_TYPE_PS = 0 -SQ_WAVE_TYPE_VS = 1 -SQ_WAVE_TYPE_GS = 2 -SQ_WAVE_TYPE_ES = 3 -SQ_WAVE_TYPE_HS = 4 -SQ_WAVE_TYPE_LS = 5 -SQ_WAVE_TYPE_CS = 6 -SQ_WAVE_TYPE_PS1 = 7 -SQ_WAVE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_TOKEN_TYPE' -SQ_THREAD_TRACE_TOKEN_TYPE__enumvalues = { - 0: 'SQ_THREAD_TRACE_TOKEN_MISC', - 1: 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', - 2: 'SQ_THREAD_TRACE_TOKEN_REG', - 3: 'SQ_THREAD_TRACE_TOKEN_WAVE_START', - 4: 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', - 5: 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', - 6: 'SQ_THREAD_TRACE_TOKEN_WAVE_END', - 7: 'SQ_THREAD_TRACE_TOKEN_EVENT', - 8: 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', - 9: 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', - 10: 'SQ_THREAD_TRACE_TOKEN_INST', - 11: 'SQ_THREAD_TRACE_TOKEN_INST_PC', - 12: 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', - 13: 'SQ_THREAD_TRACE_TOKEN_ISSUE', - 14: 'SQ_THREAD_TRACE_TOKEN_PERF', - 15: 'SQ_THREAD_TRACE_TOKEN_REG_CS', -} -SQ_THREAD_TRACE_TOKEN_MISC = 0 -SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 1 -SQ_THREAD_TRACE_TOKEN_REG = 2 -SQ_THREAD_TRACE_TOKEN_WAVE_START = 3 -SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 4 -SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 5 -SQ_THREAD_TRACE_TOKEN_WAVE_END = 6 -SQ_THREAD_TRACE_TOKEN_EVENT = 7 -SQ_THREAD_TRACE_TOKEN_EVENT_CS = 8 -SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 9 -SQ_THREAD_TRACE_TOKEN_INST = 10 -SQ_THREAD_TRACE_TOKEN_INST_PC = 11 -SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 12 -SQ_THREAD_TRACE_TOKEN_ISSUE = 13 -SQ_THREAD_TRACE_TOKEN_PERF = 14 -SQ_THREAD_TRACE_TOKEN_REG_CS = 15 -SQ_THREAD_TRACE_TOKEN_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE' -SQ_THREAD_TRACE_MISC_TOKEN_TYPE__enumvalues = { - 0: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', - 1: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', - 2: 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', - 3: 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', - 4: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', - 5: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', - 6: 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', - 7: 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', -} -SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0 -SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 1 -SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 2 -SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 3 -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 4 -SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 5 -SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 6 -SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 7 -SQ_THREAD_TRACE_MISC_TOKEN_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_INST_TYPE' -SQ_THREAD_TRACE_INST_TYPE__enumvalues = { - 0: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', - 1: 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', - 2: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', - 3: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', - 4: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', - 5: 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', - 6: 'SQ_THREAD_TRACE_INST_TYPE_LDS', - 7: 'SQ_THREAD_TRACE_INST_TYPE_PC', - 8: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', - 9: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', - 10: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', - 11: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', - 12: 'SQ_THREAD_TRACE_INST_TYPE_JUMP', - 13: 'SQ_THREAD_TRACE_INST_TYPE_NEXT', - 14: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', - 15: 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', - 16: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', - 17: 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', - 18: 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', - 19: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', - 20: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', - 21: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', - 22: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', - 23: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', - 24: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', - 25: 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', -} -SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0 -SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 1 -SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 2 -SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 3 -SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 4 -SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 5 -SQ_THREAD_TRACE_INST_TYPE_LDS = 6 -SQ_THREAD_TRACE_INST_TYPE_PC = 7 -SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 8 -SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 9 -SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 10 -SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 11 -SQ_THREAD_TRACE_INST_TYPE_JUMP = 12 -SQ_THREAD_TRACE_INST_TYPE_NEXT = 13 -SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 14 -SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 15 -SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 16 -SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 17 -SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 18 -SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 19 -SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 20 -SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 21 -SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 22 -SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 23 -SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 24 -SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 25 -SQ_THREAD_TRACE_INST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_REG_TYPE' -SQ_THREAD_TRACE_REG_TYPE__enumvalues = { - 0: 'SQ_THREAD_TRACE_REG_TYPE_EVENT', - 1: 'SQ_THREAD_TRACE_REG_TYPE_DRAW', - 2: 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', - 3: 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', - 4: 'SQ_THREAD_TRACE_REG_TYPE_MARKER', - 5: 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', - 6: 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', - 7: 'SQ_THREAD_TRACE_REG_TYPE_OTHER', -} -SQ_THREAD_TRACE_REG_TYPE_EVENT = 0 -SQ_THREAD_TRACE_REG_TYPE_DRAW = 1 -SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 2 -SQ_THREAD_TRACE_REG_TYPE_USERDATA = 3 -SQ_THREAD_TRACE_REG_TYPE_MARKER = 4 -SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 5 -SQ_THREAD_TRACE_REG_TYPE_SHDEC = 6 -SQ_THREAD_TRACE_REG_TYPE_OTHER = 7 -SQ_THREAD_TRACE_REG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_REG_OP' -SQ_THREAD_TRACE_REG_OP__enumvalues = { - 0: 'SQ_THREAD_TRACE_REG_OP_READ', - 1: 'SQ_THREAD_TRACE_REG_OP_WRITE', -} -SQ_THREAD_TRACE_REG_OP_READ = 0 -SQ_THREAD_TRACE_REG_OP_WRITE = 1 -SQ_THREAD_TRACE_REG_OP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_MODE_SEL' -SQ_THREAD_TRACE_MODE_SEL__enumvalues = { - 0: 'SQ_THREAD_TRACE_MODE_OFF', - 1: 'SQ_THREAD_TRACE_MODE_ON', -} -SQ_THREAD_TRACE_MODE_OFF = 0 -SQ_THREAD_TRACE_MODE_ON = 1 -SQ_THREAD_TRACE_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_CAPTURE_MODE' -SQ_THREAD_TRACE_CAPTURE_MODE__enumvalues = { - 0: 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', - 1: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', - 2: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', -} -SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0 -SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 1 -SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 2 -SQ_THREAD_TRACE_CAPTURE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_VM_ID_MASK' -SQ_THREAD_TRACE_VM_ID_MASK__enumvalues = { - 0: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', - 1: 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', - 2: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', -} -SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0 -SQ_THREAD_TRACE_VM_ID_MASK_ALL = 1 -SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 2 -SQ_THREAD_TRACE_VM_ID_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_WAVE_MASK' -SQ_THREAD_TRACE_WAVE_MASK__enumvalues = { - 0: 'SQ_THREAD_TRACE_WAVE_MASK_NONE', - 1: 'SQ_THREAD_TRACE_WAVE_MASK_ALL', -} -SQ_THREAD_TRACE_WAVE_MASK_NONE = 0 -SQ_THREAD_TRACE_WAVE_MASK_ALL = 1 -SQ_THREAD_TRACE_WAVE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_ISSUE' -SQ_THREAD_TRACE_ISSUE__enumvalues = { - 0: 'SQ_THREAD_TRACE_ISSUE_NULL', - 1: 'SQ_THREAD_TRACE_ISSUE_STALL', - 2: 'SQ_THREAD_TRACE_ISSUE_INST', - 3: 'SQ_THREAD_TRACE_ISSUE_IMMED', -} -SQ_THREAD_TRACE_ISSUE_NULL = 0 -SQ_THREAD_TRACE_ISSUE_STALL = 1 -SQ_THREAD_TRACE_ISSUE_INST = 2 -SQ_THREAD_TRACE_ISSUE_IMMED = 3 -SQ_THREAD_TRACE_ISSUE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_ISSUE_MASK' -SQ_THREAD_TRACE_ISSUE_MASK__enumvalues = { - 0: 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', - 1: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', - 2: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', - 3: 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', -} -SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0 -SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 1 -SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 2 -SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 3 -SQ_THREAD_TRACE_ISSUE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_PERF_SEL' -SQ_PERF_SEL__enumvalues = { - 0: 'SQ_PERF_SEL_NONE', - 1: 'SQ_PERF_SEL_ACCUM_PREV', - 2: 'SQ_PERF_SEL_CYCLES', - 3: 'SQ_PERF_SEL_BUSY_CYCLES', - 4: 'SQ_PERF_SEL_WAVES', - 5: 'SQ_PERF_SEL_LEVEL_WAVES', - 6: 'SQ_PERF_SEL_WAVES_EQ_64', - 7: 'SQ_PERF_SEL_WAVES_LT_64', - 8: 'SQ_PERF_SEL_WAVES_LT_48', - 9: 'SQ_PERF_SEL_WAVES_LT_32', - 10: 'SQ_PERF_SEL_WAVES_LT_16', - 11: 'SQ_PERF_SEL_WAVES_CU', - 12: 'SQ_PERF_SEL_LEVEL_WAVES_CU', - 13: 'SQ_PERF_SEL_BUSY_CU_CYCLES', - 14: 'SQ_PERF_SEL_ITEMS', - 15: 'SQ_PERF_SEL_QUADS', - 16: 'SQ_PERF_SEL_EVENTS', - 17: 'SQ_PERF_SEL_SURF_SYNCS', - 18: 'SQ_PERF_SEL_TTRACE_REQS', - 19: 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', - 20: 'SQ_PERF_SEL_TTRACE_STALL', - 21: 'SQ_PERF_SEL_MSG_CNTR', - 22: 'SQ_PERF_SEL_MSG_PERF', - 23: 'SQ_PERF_SEL_MSG_GSCNT', - 24: 'SQ_PERF_SEL_MSG_INTERRUPT', - 25: 'SQ_PERF_SEL_INSTS', - 26: 'SQ_PERF_SEL_INSTS_VALU', - 27: 'SQ_PERF_SEL_INSTS_VMEM_WR', - 28: 'SQ_PERF_SEL_INSTS_VMEM_RD', - 29: 'SQ_PERF_SEL_INSTS_VMEM', - 30: 'SQ_PERF_SEL_INSTS_SALU', - 31: 'SQ_PERF_SEL_INSTS_SMEM', - 32: 'SQ_PERF_SEL_INSTS_FLAT', - 33: 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', - 34: 'SQ_PERF_SEL_INSTS_LDS', - 35: 'SQ_PERF_SEL_INSTS_GDS', - 36: 'SQ_PERF_SEL_INSTS_EXP', - 37: 'SQ_PERF_SEL_INSTS_EXP_GDS', - 38: 'SQ_PERF_SEL_INSTS_BRANCH', - 39: 'SQ_PERF_SEL_INSTS_SENDMSG', - 40: 'SQ_PERF_SEL_INSTS_VSKIPPED', - 41: 'SQ_PERF_SEL_INST_LEVEL_VMEM', - 42: 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 43: 'SQ_PERF_SEL_INST_LEVEL_LDS', - 44: 'SQ_PERF_SEL_INST_LEVEL_GDS', - 45: 'SQ_PERF_SEL_INST_LEVEL_EXP', - 46: 'SQ_PERF_SEL_WAVE_CYCLES', - 47: 'SQ_PERF_SEL_WAVE_READY', - 48: 'SQ_PERF_SEL_WAIT_CNT_VM', - 49: 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 50: 'SQ_PERF_SEL_WAIT_CNT_EXP', - 51: 'SQ_PERF_SEL_WAIT_CNT_ANY', - 52: 'SQ_PERF_SEL_WAIT_BARRIER', - 53: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 54: 'SQ_PERF_SEL_WAIT_SLEEP', - 55: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', - 56: 'SQ_PERF_SEL_WAIT_OTHER', - 57: 'SQ_PERF_SEL_WAIT_ANY', - 58: 'SQ_PERF_SEL_WAIT_TTRACE', - 59: 'SQ_PERF_SEL_WAIT_IFETCH', - 60: 'SQ_PERF_SEL_WAIT_INST_ANY', - 61: 'SQ_PERF_SEL_WAIT_INST_VMEM', - 62: 'SQ_PERF_SEL_WAIT_INST_SCA', - 63: 'SQ_PERF_SEL_WAIT_INST_LDS', - 64: 'SQ_PERF_SEL_WAIT_INST_VALU', - 65: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', - 66: 'SQ_PERF_SEL_WAIT_INST_MISC', - 67: 'SQ_PERF_SEL_WAIT_INST_FLAT', - 68: 'SQ_PERF_SEL_ACTIVE_INST_ANY', - 69: 'SQ_PERF_SEL_ACTIVE_INST_VMEM', - 70: 'SQ_PERF_SEL_ACTIVE_INST_LDS', - 71: 'SQ_PERF_SEL_ACTIVE_INST_VALU', - 72: 'SQ_PERF_SEL_ACTIVE_INST_SCA', - 73: 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', - 74: 'SQ_PERF_SEL_ACTIVE_INST_MISC', - 75: 'SQ_PERF_SEL_ACTIVE_INST_FLAT', - 76: 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', - 77: 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', - 78: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', - 79: 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', - 80: 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', - 81: 'SQ_PERF_SEL_INST_CYCLES_EXP', - 82: 'SQ_PERF_SEL_INST_CYCLES_GDS', - 83: 'SQ_PERF_SEL_INST_CYCLES_SMEM', - 84: 'SQ_PERF_SEL_INST_CYCLES_SALU', - 85: 'SQ_PERF_SEL_THREAD_CYCLES_VALU', - 86: 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', - 87: 'SQ_PERF_SEL_IFETCH', - 88: 'SQ_PERF_SEL_IFETCH_LEVEL', - 89: 'SQ_PERF_SEL_CBRANCH_FORK', - 90: 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', - 91: 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', - 92: 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', - 93: 'SQ_PERF_SEL_LDS_BANK_CONFLICT', - 94: 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', - 95: 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', - 96: 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', - 97: 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', - 98: 'SQ_PERF_SEL_LDS_IDX_ACTIVE', - 99: 'SQ_PERF_SEL_VALU_DEP_STALL', - 100: 'SQ_PERF_SEL_VALU_STARVE', - 101: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 102: 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', - 103: 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', - 104: 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', - 105: 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', - 106: 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', - 107: 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', - 108: 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', - 109: 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', - 110: 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', - 111: 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', - 112: 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', - 113: 'SQ_PERF_SEL_SRC_CD_BUSY', - 114: 'SQ_PERF_SEL_PT_POWER_STALL', - 115: 'SQ_PERF_SEL_USER0', - 116: 'SQ_PERF_SEL_USER1', - 117: 'SQ_PERF_SEL_USER2', - 118: 'SQ_PERF_SEL_USER3', - 119: 'SQ_PERF_SEL_USER4', - 120: 'SQ_PERF_SEL_USER5', - 121: 'SQ_PERF_SEL_USER6', - 122: 'SQ_PERF_SEL_USER7', - 123: 'SQ_PERF_SEL_USER8', - 124: 'SQ_PERF_SEL_USER9', - 125: 'SQ_PERF_SEL_USER10', - 126: 'SQ_PERF_SEL_USER11', - 127: 'SQ_PERF_SEL_USER12', - 128: 'SQ_PERF_SEL_USER13', - 129: 'SQ_PERF_SEL_USER14', - 130: 'SQ_PERF_SEL_USER15', - 131: 'SQ_PERF_SEL_USER_LEVEL0', - 132: 'SQ_PERF_SEL_USER_LEVEL1', - 133: 'SQ_PERF_SEL_USER_LEVEL2', - 134: 'SQ_PERF_SEL_USER_LEVEL3', - 135: 'SQ_PERF_SEL_USER_LEVEL4', - 136: 'SQ_PERF_SEL_USER_LEVEL5', - 137: 'SQ_PERF_SEL_USER_LEVEL6', - 138: 'SQ_PERF_SEL_USER_LEVEL7', - 139: 'SQ_PERF_SEL_USER_LEVEL8', - 140: 'SQ_PERF_SEL_USER_LEVEL9', - 141: 'SQ_PERF_SEL_USER_LEVEL10', - 142: 'SQ_PERF_SEL_USER_LEVEL11', - 143: 'SQ_PERF_SEL_USER_LEVEL12', - 144: 'SQ_PERF_SEL_USER_LEVEL13', - 145: 'SQ_PERF_SEL_USER_LEVEL14', - 146: 'SQ_PERF_SEL_USER_LEVEL15', - 147: 'SQ_PERF_SEL_POWER_VALU', - 148: 'SQ_PERF_SEL_POWER_VALU0', - 149: 'SQ_PERF_SEL_POWER_VALU1', - 150: 'SQ_PERF_SEL_POWER_VALU2', - 151: 'SQ_PERF_SEL_POWER_GPR_RD', - 152: 'SQ_PERF_SEL_POWER_GPR_WR', - 153: 'SQ_PERF_SEL_POWER_LDS_BUSY', - 154: 'SQ_PERF_SEL_POWER_ALU_BUSY', - 155: 'SQ_PERF_SEL_POWER_TEX_BUSY', - 156: 'SQ_PERF_SEL_ACCUM_PREV_HIRES', - 157: 'SQ_PERF_SEL_WAVES_RESTORED', - 158: 'SQ_PERF_SEL_WAVES_SAVED', - 159: 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 160: 'SQ_PERF_SEL_ATC_INSTS_VMEM', - 161: 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', - 162: 'SQ_PERF_SEL_ATC_XNACK_FIRST', - 163: 'SQ_PERF_SEL_ATC_XNACK_ALL', - 164: 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', - 165: 'SQ_PERF_SEL_ATC_INSTS_SMEM', - 166: 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', - 167: 'SQ_PERF_SEL_IFETCH_XNACK', - 168: 'SQ_PERF_SEL_TLB_SHOOTDOWN', - 169: 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', - 170: 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', - 171: 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', - 172: 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', - 173: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', - 174: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', - 175: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', - 176: 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', - 177: 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', - 178: 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', - 179: 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', - 180: 'SQ_PERF_SEL_UTCL1_REQUEST', - 181: 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 182: 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 183: 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 184: 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', - 185: 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 186: 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 187: 'SQ_PERF_SEL_DUMMY_END', - 255: 'SQ_PERF_SEL_DUMMY_LAST', - 256: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', - 257: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 258: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', - 259: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', - 260: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 261: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', - 262: 'SQC_PERF_SEL_TC_REQ', - 263: 'SQC_PERF_SEL_TC_INST_REQ', - 264: 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 265: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', - 266: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', - 267: 'SQC_PERF_SEL_TC_STALL', - 268: 'SQC_PERF_SEL_TC_STARVE', - 269: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 270: 'SQC_PERF_SEL_ICACHE_REQ', - 271: 'SQC_PERF_SEL_ICACHE_HITS', - 272: 'SQC_PERF_SEL_ICACHE_MISSES', - 273: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 274: 'SQC_PERF_SEL_ICACHE_INVAL_INST', - 275: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 276: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 277: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 278: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 279: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', - 280: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 281: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', - 282: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 283: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 284: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', - 285: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 286: 'SQC_PERF_SEL_ICACHE_PREFETCH_1', - 287: 'SQC_PERF_SEL_ICACHE_PREFETCH_2', - 288: 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', - 289: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 290: 'SQC_PERF_SEL_DCACHE_REQ', - 291: 'SQC_PERF_SEL_DCACHE_HITS', - 292: 'SQC_PERF_SEL_DCACHE_MISSES', - 293: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 294: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 295: 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', - 296: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', - 297: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', - 298: 'SQC_PERF_SEL_DCACHE_ATOMIC', - 299: 'SQC_PERF_SEL_DCACHE_VOLATILE', - 300: 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 301: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 302: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', - 303: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', - 304: 'SQC_PERF_SEL_DCACHE_WB_INST', - 305: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', - 306: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', - 307: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', - 308: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 309: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 310: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 311: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 312: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 313: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', - 314: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', - 315: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', - 316: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', - 317: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', - 318: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', - 319: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 320: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 321: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', - 322: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 323: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 324: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 325: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 326: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 327: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 328: 'SQC_PERF_SEL_DCACHE_REQ_TIME', - 329: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', - 330: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', - 331: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', - 332: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 333: 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 334: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 335: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', - 336: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 337: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 338: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', - 339: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 340: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 341: 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', - 342: 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', - 343: 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', - 344: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', - 345: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', - 346: 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', - 347: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', - 348: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', - 349: 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', - 350: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', - 351: 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', - 352: 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', - 353: 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', - 354: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', - 355: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', - 356: 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', - 357: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', - 358: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', - 359: 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', - 360: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', - 361: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', - 362: 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', - 363: 'SQC_PERF_SEL_DUMMY_LAST', -} -SQ_PERF_SEL_NONE = 0 -SQ_PERF_SEL_ACCUM_PREV = 1 -SQ_PERF_SEL_CYCLES = 2 -SQ_PERF_SEL_BUSY_CYCLES = 3 -SQ_PERF_SEL_WAVES = 4 -SQ_PERF_SEL_LEVEL_WAVES = 5 -SQ_PERF_SEL_WAVES_EQ_64 = 6 -SQ_PERF_SEL_WAVES_LT_64 = 7 -SQ_PERF_SEL_WAVES_LT_48 = 8 -SQ_PERF_SEL_WAVES_LT_32 = 9 -SQ_PERF_SEL_WAVES_LT_16 = 10 -SQ_PERF_SEL_WAVES_CU = 11 -SQ_PERF_SEL_LEVEL_WAVES_CU = 12 -SQ_PERF_SEL_BUSY_CU_CYCLES = 13 -SQ_PERF_SEL_ITEMS = 14 -SQ_PERF_SEL_QUADS = 15 -SQ_PERF_SEL_EVENTS = 16 -SQ_PERF_SEL_SURF_SYNCS = 17 -SQ_PERF_SEL_TTRACE_REQS = 18 -SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 19 -SQ_PERF_SEL_TTRACE_STALL = 20 -SQ_PERF_SEL_MSG_CNTR = 21 -SQ_PERF_SEL_MSG_PERF = 22 -SQ_PERF_SEL_MSG_GSCNT = 23 -SQ_PERF_SEL_MSG_INTERRUPT = 24 -SQ_PERF_SEL_INSTS = 25 -SQ_PERF_SEL_INSTS_VALU = 26 -SQ_PERF_SEL_INSTS_VMEM_WR = 27 -SQ_PERF_SEL_INSTS_VMEM_RD = 28 -SQ_PERF_SEL_INSTS_VMEM = 29 -SQ_PERF_SEL_INSTS_SALU = 30 -SQ_PERF_SEL_INSTS_SMEM = 31 -SQ_PERF_SEL_INSTS_FLAT = 32 -SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 33 -SQ_PERF_SEL_INSTS_LDS = 34 -SQ_PERF_SEL_INSTS_GDS = 35 -SQ_PERF_SEL_INSTS_EXP = 36 -SQ_PERF_SEL_INSTS_EXP_GDS = 37 -SQ_PERF_SEL_INSTS_BRANCH = 38 -SQ_PERF_SEL_INSTS_SENDMSG = 39 -SQ_PERF_SEL_INSTS_VSKIPPED = 40 -SQ_PERF_SEL_INST_LEVEL_VMEM = 41 -SQ_PERF_SEL_INST_LEVEL_SMEM = 42 -SQ_PERF_SEL_INST_LEVEL_LDS = 43 -SQ_PERF_SEL_INST_LEVEL_GDS = 44 -SQ_PERF_SEL_INST_LEVEL_EXP = 45 -SQ_PERF_SEL_WAVE_CYCLES = 46 -SQ_PERF_SEL_WAVE_READY = 47 -SQ_PERF_SEL_WAIT_CNT_VM = 48 -SQ_PERF_SEL_WAIT_CNT_LGKM = 49 -SQ_PERF_SEL_WAIT_CNT_EXP = 50 -SQ_PERF_SEL_WAIT_CNT_ANY = 51 -SQ_PERF_SEL_WAIT_BARRIER = 52 -SQ_PERF_SEL_WAIT_EXP_ALLOC = 53 -SQ_PERF_SEL_WAIT_SLEEP = 54 -SQ_PERF_SEL_WAIT_SLEEP_XNACK = 55 -SQ_PERF_SEL_WAIT_OTHER = 56 -SQ_PERF_SEL_WAIT_ANY = 57 -SQ_PERF_SEL_WAIT_TTRACE = 58 -SQ_PERF_SEL_WAIT_IFETCH = 59 -SQ_PERF_SEL_WAIT_INST_ANY = 60 -SQ_PERF_SEL_WAIT_INST_VMEM = 61 -SQ_PERF_SEL_WAIT_INST_SCA = 62 -SQ_PERF_SEL_WAIT_INST_LDS = 63 -SQ_PERF_SEL_WAIT_INST_VALU = 64 -SQ_PERF_SEL_WAIT_INST_EXP_GDS = 65 -SQ_PERF_SEL_WAIT_INST_MISC = 66 -SQ_PERF_SEL_WAIT_INST_FLAT = 67 -SQ_PERF_SEL_ACTIVE_INST_ANY = 68 -SQ_PERF_SEL_ACTIVE_INST_VMEM = 69 -SQ_PERF_SEL_ACTIVE_INST_LDS = 70 -SQ_PERF_SEL_ACTIVE_INST_VALU = 71 -SQ_PERF_SEL_ACTIVE_INST_SCA = 72 -SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 73 -SQ_PERF_SEL_ACTIVE_INST_MISC = 74 -SQ_PERF_SEL_ACTIVE_INST_FLAT = 75 -SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 76 -SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 77 -SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 78 -SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 79 -SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 80 -SQ_PERF_SEL_INST_CYCLES_EXP = 81 -SQ_PERF_SEL_INST_CYCLES_GDS = 82 -SQ_PERF_SEL_INST_CYCLES_SMEM = 83 -SQ_PERF_SEL_INST_CYCLES_SALU = 84 -SQ_PERF_SEL_THREAD_CYCLES_VALU = 85 -SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 86 -SQ_PERF_SEL_IFETCH = 87 -SQ_PERF_SEL_IFETCH_LEVEL = 88 -SQ_PERF_SEL_CBRANCH_FORK = 89 -SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 90 -SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 91 -SQ_PERF_SEL_VALU_LDS_INTERP_OP = 92 -SQ_PERF_SEL_LDS_BANK_CONFLICT = 93 -SQ_PERF_SEL_LDS_ADDR_CONFLICT = 94 -SQ_PERF_SEL_LDS_UNALIGNED_STALL = 95 -SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 96 -SQ_PERF_SEL_LDS_ATOMIC_RETURN = 97 -SQ_PERF_SEL_LDS_IDX_ACTIVE = 98 -SQ_PERF_SEL_VALU_DEP_STALL = 99 -SQ_PERF_SEL_VALU_STARVE = 100 -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 101 -SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 102 -SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 103 -SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 104 -SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 105 -SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 106 -SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 107 -SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 108 -SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 109 -SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 110 -SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 111 -SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 112 -SQ_PERF_SEL_SRC_CD_BUSY = 113 -SQ_PERF_SEL_PT_POWER_STALL = 114 -SQ_PERF_SEL_USER0 = 115 -SQ_PERF_SEL_USER1 = 116 -SQ_PERF_SEL_USER2 = 117 -SQ_PERF_SEL_USER3 = 118 -SQ_PERF_SEL_USER4 = 119 -SQ_PERF_SEL_USER5 = 120 -SQ_PERF_SEL_USER6 = 121 -SQ_PERF_SEL_USER7 = 122 -SQ_PERF_SEL_USER8 = 123 -SQ_PERF_SEL_USER9 = 124 -SQ_PERF_SEL_USER10 = 125 -SQ_PERF_SEL_USER11 = 126 -SQ_PERF_SEL_USER12 = 127 -SQ_PERF_SEL_USER13 = 128 -SQ_PERF_SEL_USER14 = 129 -SQ_PERF_SEL_USER15 = 130 -SQ_PERF_SEL_USER_LEVEL0 = 131 -SQ_PERF_SEL_USER_LEVEL1 = 132 -SQ_PERF_SEL_USER_LEVEL2 = 133 -SQ_PERF_SEL_USER_LEVEL3 = 134 -SQ_PERF_SEL_USER_LEVEL4 = 135 -SQ_PERF_SEL_USER_LEVEL5 = 136 -SQ_PERF_SEL_USER_LEVEL6 = 137 -SQ_PERF_SEL_USER_LEVEL7 = 138 -SQ_PERF_SEL_USER_LEVEL8 = 139 -SQ_PERF_SEL_USER_LEVEL9 = 140 -SQ_PERF_SEL_USER_LEVEL10 = 141 -SQ_PERF_SEL_USER_LEVEL11 = 142 -SQ_PERF_SEL_USER_LEVEL12 = 143 -SQ_PERF_SEL_USER_LEVEL13 = 144 -SQ_PERF_SEL_USER_LEVEL14 = 145 -SQ_PERF_SEL_USER_LEVEL15 = 146 -SQ_PERF_SEL_POWER_VALU = 147 -SQ_PERF_SEL_POWER_VALU0 = 148 -SQ_PERF_SEL_POWER_VALU1 = 149 -SQ_PERF_SEL_POWER_VALU2 = 150 -SQ_PERF_SEL_POWER_GPR_RD = 151 -SQ_PERF_SEL_POWER_GPR_WR = 152 -SQ_PERF_SEL_POWER_LDS_BUSY = 153 -SQ_PERF_SEL_POWER_ALU_BUSY = 154 -SQ_PERF_SEL_POWER_TEX_BUSY = 155 -SQ_PERF_SEL_ACCUM_PREV_HIRES = 156 -SQ_PERF_SEL_WAVES_RESTORED = 157 -SQ_PERF_SEL_WAVES_SAVED = 158 -SQ_PERF_SEL_INSTS_SMEM_NORM = 159 -SQ_PERF_SEL_ATC_INSTS_VMEM = 160 -SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 161 -SQ_PERF_SEL_ATC_XNACK_FIRST = 162 -SQ_PERF_SEL_ATC_XNACK_ALL = 163 -SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 164 -SQ_PERF_SEL_ATC_INSTS_SMEM = 165 -SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 166 -SQ_PERF_SEL_IFETCH_XNACK = 167 -SQ_PERF_SEL_TLB_SHOOTDOWN = 168 -SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 169 -SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 170 -SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 171 -SQ_PERF_SEL_INSTS_VMEM_REPLAY = 172 -SQ_PERF_SEL_INSTS_SMEM_REPLAY = 173 -SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 174 -SQ_PERF_SEL_INSTS_FLAT_REPLAY = 175 -SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 176 -SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 177 -SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 178 -SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 179 -SQ_PERF_SEL_UTCL1_REQUEST = 180 -SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 181 -SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 182 -SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 183 -SQ_PERF_SEL_UTCL1_LFIFO_FULL = 184 -SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 185 -SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 186 -SQ_PERF_SEL_DUMMY_END = 187 -SQ_PERF_SEL_DUMMY_LAST = 255 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 256 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 257 -SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 258 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 259 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 260 -SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 261 -SQC_PERF_SEL_TC_REQ = 262 -SQC_PERF_SEL_TC_INST_REQ = 263 -SQC_PERF_SEL_TC_DATA_READ_REQ = 264 -SQC_PERF_SEL_TC_DATA_WRITE_REQ = 265 -SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 266 -SQC_PERF_SEL_TC_STALL = 267 -SQC_PERF_SEL_TC_STARVE = 268 -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 269 -SQC_PERF_SEL_ICACHE_REQ = 270 -SQC_PERF_SEL_ICACHE_HITS = 271 -SQC_PERF_SEL_ICACHE_MISSES = 272 -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 273 -SQC_PERF_SEL_ICACHE_INVAL_INST = 274 -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 275 -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 276 -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 277 -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 278 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 279 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 280 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 281 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 282 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 283 -SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 284 -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 285 -SQC_PERF_SEL_ICACHE_PREFETCH_1 = 286 -SQC_PERF_SEL_ICACHE_PREFETCH_2 = 287 -SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 288 -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 289 -SQC_PERF_SEL_DCACHE_REQ = 290 -SQC_PERF_SEL_DCACHE_HITS = 291 -SQC_PERF_SEL_DCACHE_MISSES = 292 -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 293 -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 294 -SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 295 -SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 296 -SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 297 -SQC_PERF_SEL_DCACHE_ATOMIC = 298 -SQC_PERF_SEL_DCACHE_VOLATILE = 299 -SQC_PERF_SEL_DCACHE_INVAL_INST = 300 -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 301 -SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 302 -SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 303 -SQC_PERF_SEL_DCACHE_WB_INST = 304 -SQC_PERF_SEL_DCACHE_WB_ASYNC = 305 -SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 306 -SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 307 -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 308 -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 309 -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 310 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 311 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 312 -SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 313 -SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 314 -SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 315 -SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 316 -SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 317 -SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 318 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 319 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 320 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 321 -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 322 -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 323 -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 324 -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 325 -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 326 -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 327 -SQC_PERF_SEL_DCACHE_REQ_TIME = 328 -SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 329 -SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 330 -SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 331 -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 332 -SQC_PERF_SEL_SQ_DCACHE_REQS = 333 -SQC_PERF_SEL_DCACHE_FLAT_REQ = 334 -SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 335 -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 336 -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 337 -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 338 -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 339 -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 340 -SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 341 -SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 342 -SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 343 -SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 344 -SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 345 -SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 346 -SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 347 -SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 348 -SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 349 -SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 350 -SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 351 -SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 352 -SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 353 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 354 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 355 -SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 356 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 357 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 358 -SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 359 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 360 -SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 361 -SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 362 -SQC_PERF_SEL_DUMMY_LAST = 363 -SQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_CAC_POWER_SEL' -SQ_CAC_POWER_SEL__enumvalues = { - 0: 'SQ_CAC_POWER_VALU', - 1: 'SQ_CAC_POWER_VALU0', - 2: 'SQ_CAC_POWER_VALU1', - 3: 'SQ_CAC_POWER_VALU2', - 4: 'SQ_CAC_POWER_GPR_RD', - 5: 'SQ_CAC_POWER_GPR_WR', - 6: 'SQ_CAC_POWER_LDS_BUSY', - 7: 'SQ_CAC_POWER_ALU_BUSY', - 8: 'SQ_CAC_POWER_TEX_BUSY', -} -SQ_CAC_POWER_VALU = 0 -SQ_CAC_POWER_VALU0 = 1 -SQ_CAC_POWER_VALU1 = 2 -SQ_CAC_POWER_VALU2 = 3 -SQ_CAC_POWER_GPR_RD = 4 -SQ_CAC_POWER_GPR_WR = 5 -SQ_CAC_POWER_LDS_BUSY = 6 -SQ_CAC_POWER_ALU_BUSY = 7 -SQ_CAC_POWER_TEX_BUSY = 8 -SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_CMD' -SQ_IND_CMD_CMD__enumvalues = { - 0: 'SQ_IND_CMD_CMD_NULL', - 1: 'SQ_IND_CMD_CMD_SETHALT', - 2: 'SQ_IND_CMD_CMD_SAVECTX', - 3: 'SQ_IND_CMD_CMD_KILL', - 4: 'SQ_IND_CMD_CMD_DEBUG', - 5: 'SQ_IND_CMD_CMD_TRAP', - 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 7: 'SQ_IND_CMD_CMD_SETFATALHALT', -} -SQ_IND_CMD_CMD_NULL = 0 -SQ_IND_CMD_CMD_SETHALT = 1 -SQ_IND_CMD_CMD_SAVECTX = 2 -SQ_IND_CMD_CMD_KILL = 3 -SQ_IND_CMD_CMD_DEBUG = 4 -SQ_IND_CMD_CMD_TRAP = 5 -SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 -SQ_IND_CMD_CMD_SETFATALHALT = 7 -SQ_IND_CMD_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_MODE' -SQ_IND_CMD_MODE__enumvalues = { - 0: 'SQ_IND_CMD_MODE_SINGLE', - 1: 'SQ_IND_CMD_MODE_BROADCAST', - 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', - 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', -} -SQ_IND_CMD_MODE_SINGLE = 0 -SQ_IND_CMD_MODE_BROADCAST = 1 -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 -SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 -SQ_IND_CMD_MODE_BROADCAST_ME = 4 -SQ_IND_CMD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_EDC_INFO_SOURCE' -SQ_EDC_INFO_SOURCE__enumvalues = { - 0: 'SQ_EDC_INFO_SOURCE_INVALID', - 1: 'SQ_EDC_INFO_SOURCE_INST', - 2: 'SQ_EDC_INFO_SOURCE_SGPR', - 3: 'SQ_EDC_INFO_SOURCE_VGPR', - 4: 'SQ_EDC_INFO_SOURCE_LDS', - 5: 'SQ_EDC_INFO_SOURCE_GDS', - 6: 'SQ_EDC_INFO_SOURCE_TA', -} -SQ_EDC_INFO_SOURCE_INVALID = 0 -SQ_EDC_INFO_SOURCE_INST = 1 -SQ_EDC_INFO_SOURCE_SGPR = 2 -SQ_EDC_INFO_SOURCE_VGPR = 3 -SQ_EDC_INFO_SOURCE_LDS = 4 -SQ_EDC_INFO_SOURCE_GDS = 5 -SQ_EDC_INFO_SOURCE_TA = 6 -SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_ROUND_MODE' -SQ_ROUND_MODE__enumvalues = { - 0: 'SQ_ROUND_NEAREST_EVEN', - 1: 'SQ_ROUND_PLUS_INFINITY', - 2: 'SQ_ROUND_MINUS_INFINITY', - 3: 'SQ_ROUND_TO_ZERO', -} -SQ_ROUND_NEAREST_EVEN = 0 -SQ_ROUND_PLUS_INFINITY = 1 -SQ_ROUND_MINUS_INFINITY = 2 -SQ_ROUND_TO_ZERO = 3 -SQ_ROUND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' -SQ_INTERRUPT_WORD_ENCODING__enumvalues = { - 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', - 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', - 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', -} -SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 -SQ_INTERRUPT_WORD_ENCODING_INST = 1 -SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 -SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_SQ_EXPORT_RAT_INST' -ENUM_SQ_EXPORT_RAT_INST__enumvalues = { - 0: 'SQ_EXPORT_RAT_INST_NOP', - 1: 'SQ_EXPORT_RAT_INST_STORE_TYPED', - 2: 'SQ_EXPORT_RAT_INST_STORE_RAW', - 3: 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', - 4: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', - 5: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', - 6: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', - 7: 'SQ_EXPORT_RAT_INST_ADD', - 8: 'SQ_EXPORT_RAT_INST_SUB', - 9: 'SQ_EXPORT_RAT_INST_RSUB', - 10: 'SQ_EXPORT_RAT_INST_MIN_INT', - 11: 'SQ_EXPORT_RAT_INST_MIN_UINT', - 12: 'SQ_EXPORT_RAT_INST_MAX_INT', - 13: 'SQ_EXPORT_RAT_INST_MAX_UINT', - 14: 'SQ_EXPORT_RAT_INST_AND', - 15: 'SQ_EXPORT_RAT_INST_OR', - 16: 'SQ_EXPORT_RAT_INST_XOR', - 17: 'SQ_EXPORT_RAT_INST_MSKOR', - 18: 'SQ_EXPORT_RAT_INST_INC_UINT', - 19: 'SQ_EXPORT_RAT_INST_DEC_UINT', - 20: 'SQ_EXPORT_RAT_INST_STORE_DWORD', - 21: 'SQ_EXPORT_RAT_INST_STORE_SHORT', - 22: 'SQ_EXPORT_RAT_INST_STORE_BYTE', - 32: 'SQ_EXPORT_RAT_INST_NOP_RTN', - 34: 'SQ_EXPORT_RAT_INST_XCHG_RTN', - 35: 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', - 36: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', - 37: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', - 38: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', - 39: 'SQ_EXPORT_RAT_INST_ADD_RTN', - 40: 'SQ_EXPORT_RAT_INST_SUB_RTN', - 41: 'SQ_EXPORT_RAT_INST_RSUB_RTN', - 42: 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', - 43: 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', - 44: 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', - 45: 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', - 46: 'SQ_EXPORT_RAT_INST_AND_RTN', - 47: 'SQ_EXPORT_RAT_INST_OR_RTN', - 48: 'SQ_EXPORT_RAT_INST_XOR_RTN', - 49: 'SQ_EXPORT_RAT_INST_MSKOR_RTN', - 50: 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', - 51: 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', -} -SQ_EXPORT_RAT_INST_NOP = 0 -SQ_EXPORT_RAT_INST_STORE_TYPED = 1 -SQ_EXPORT_RAT_INST_STORE_RAW = 2 -SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 3 -SQ_EXPORT_RAT_INST_CMPXCHG_INT = 4 -SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 5 -SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 6 -SQ_EXPORT_RAT_INST_ADD = 7 -SQ_EXPORT_RAT_INST_SUB = 8 -SQ_EXPORT_RAT_INST_RSUB = 9 -SQ_EXPORT_RAT_INST_MIN_INT = 10 -SQ_EXPORT_RAT_INST_MIN_UINT = 11 -SQ_EXPORT_RAT_INST_MAX_INT = 12 -SQ_EXPORT_RAT_INST_MAX_UINT = 13 -SQ_EXPORT_RAT_INST_AND = 14 -SQ_EXPORT_RAT_INST_OR = 15 -SQ_EXPORT_RAT_INST_XOR = 16 -SQ_EXPORT_RAT_INST_MSKOR = 17 -SQ_EXPORT_RAT_INST_INC_UINT = 18 -SQ_EXPORT_RAT_INST_DEC_UINT = 19 -SQ_EXPORT_RAT_INST_STORE_DWORD = 20 -SQ_EXPORT_RAT_INST_STORE_SHORT = 21 -SQ_EXPORT_RAT_INST_STORE_BYTE = 22 -SQ_EXPORT_RAT_INST_NOP_RTN = 32 -SQ_EXPORT_RAT_INST_XCHG_RTN = 34 -SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 35 -SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 36 -SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 37 -SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 38 -SQ_EXPORT_RAT_INST_ADD_RTN = 39 -SQ_EXPORT_RAT_INST_SUB_RTN = 40 -SQ_EXPORT_RAT_INST_RSUB_RTN = 41 -SQ_EXPORT_RAT_INST_MIN_INT_RTN = 42 -SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 43 -SQ_EXPORT_RAT_INST_MAX_INT_RTN = 44 -SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 45 -SQ_EXPORT_RAT_INST_AND_RTN = 46 -SQ_EXPORT_RAT_INST_OR_RTN = 47 -SQ_EXPORT_RAT_INST_XOR_RTN = 48 -SQ_EXPORT_RAT_INST_MSKOR_RTN = 49 -SQ_EXPORT_RAT_INST_INC_UINT_RTN = 50 -SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 51 -ENUM_SQ_EXPORT_RAT_INST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IBUF_ST' -SQ_IBUF_ST__enumvalues = { - 0: 'SQ_IBUF_IB_IDLE', - 1: 'SQ_IBUF_IB_INI_WAIT_GNT', - 2: 'SQ_IBUF_IB_INI_WAIT_DRET', - 3: 'SQ_IBUF_IB_LE_4DW', - 4: 'SQ_IBUF_IB_WAIT_DRET', - 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 6: 'SQ_IBUF_IB_DRET', - 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', -} -SQ_IBUF_IB_IDLE = 0 -SQ_IBUF_IB_INI_WAIT_GNT = 1 -SQ_IBUF_IB_INI_WAIT_DRET = 2 -SQ_IBUF_IB_LE_4DW = 3 -SQ_IBUF_IB_WAIT_DRET = 4 -SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 -SQ_IBUF_IB_DRET = 6 -SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 -SQ_IBUF_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_STR_ST' -SQ_INST_STR_ST__enumvalues = { - 0: 'SQ_INST_STR_IB_WAVE_NORML', - 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', - 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', - 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', - 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', -} -SQ_INST_STR_IB_WAVE_NORML = 0 -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 -SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 -SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 -SQ_INST_STR_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_IB_ECC_ST' -SQ_WAVE_IB_ECC_ST__enumvalues = { - 0: 'SQ_WAVE_IB_ECC_CLEAN', - 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 2: 'SQ_WAVE_IB_ECC_ERR_HALT', - 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', -} -SQ_WAVE_IB_ECC_CLEAN = 0 -SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 -SQ_WAVE_IB_ECC_ERR_HALT = 2 -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 -SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ADDRESS_MODE' -SH_MEM_ADDRESS_MODE__enumvalues = { - 0: 'SH_MEM_ADDRESS_MODE_64', - 1: 'SH_MEM_ADDRESS_MODE_32', -} -SH_MEM_ADDRESS_MODE_64 = 0 -SH_MEM_ADDRESS_MODE_32 = 1 -SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ALIGNMENT_MODE' -SH_MEM_ALIGNMENT_MODE__enumvalues = { - 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', - 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', - 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', -} -SH_MEM_ALIGNMENT_MODE_DWORD = 0 -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 -SH_MEM_ALIGNMENT_MODE_STRICT = 2 -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 -SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX' -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX__enumvalues = { - 24: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', - 25: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', -} -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 24 -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 25 -SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_LB_CTR_SEL_VALUES' -SQ_LB_CTR_SEL_VALUES__enumvalues = { - 0: 'SQ_LB_CTR_SEL_ALU_CYCLES', - 1: 'SQ_LB_CTR_SEL_ALU_STALLS', - 2: 'SQ_LB_CTR_SEL_TEX_CYCLES', - 3: 'SQ_LB_CTR_SEL_TEX_STALLS', - 4: 'SQ_LB_CTR_SEL_SALU_CYCLES', - 5: 'SQ_LB_CTR_SEL_SCALAR_STALLS', - 6: 'SQ_LB_CTR_SEL_SMEM_CYCLES', - 7: 'SQ_LB_CTR_SEL_ICACHE_STALLS', - 8: 'SQ_LB_CTR_SEL_DCACHE_STALLS', - 9: 'SQ_LB_CTR_SEL_RESERVED0', - 10: 'SQ_LB_CTR_SEL_RESERVED1', - 11: 'SQ_LB_CTR_SEL_RESERVED2', - 12: 'SQ_LB_CTR_SEL_RESERVED3', - 13: 'SQ_LB_CTR_SEL_RESERVED4', - 14: 'SQ_LB_CTR_SEL_RESERVED5', - 15: 'SQ_LB_CTR_SEL_RESERVED6', -} -SQ_LB_CTR_SEL_ALU_CYCLES = 0 -SQ_LB_CTR_SEL_ALU_STALLS = 1 -SQ_LB_CTR_SEL_TEX_CYCLES = 2 -SQ_LB_CTR_SEL_TEX_STALLS = 3 -SQ_LB_CTR_SEL_SALU_CYCLES = 4 -SQ_LB_CTR_SEL_SCALAR_STALLS = 5 -SQ_LB_CTR_SEL_SMEM_CYCLES = 6 -SQ_LB_CTR_SEL_ICACHE_STALLS = 7 -SQ_LB_CTR_SEL_DCACHE_STALLS = 8 -SQ_LB_CTR_SEL_RESERVED0 = 9 -SQ_LB_CTR_SEL_RESERVED1 = 10 -SQ_LB_CTR_SEL_RESERVED2 = 11 -SQ_LB_CTR_SEL_RESERVED3 = 12 -SQ_LB_CTR_SEL_RESERVED4 = 13 -SQ_LB_CTR_SEL_RESERVED5 = 14 -SQ_LB_CTR_SEL_RESERVED6 = 15 -SQ_LB_CTR_SEL_VALUES = ctypes.c_uint32 # enum - -# values for enumeration 'CSDATA_TYPE' -CSDATA_TYPE__enumvalues = { - 0: 'CSDATA_TYPE_TG', - 1: 'CSDATA_TYPE_STATE', - 2: 'CSDATA_TYPE_EVENT', - 3: 'CSDATA_TYPE_PRIVATE', -} -CSDATA_TYPE_TG = 0 -CSDATA_TYPE_STATE = 1 -CSDATA_TYPE_EVENT = 2 -CSDATA_TYPE_PRIVATE = 3 -CSDATA_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUT_PRIM_TYPE' -VGT_OUT_PRIM_TYPE__enumvalues = { - 0: 'VGT_OUT_POINT', - 1: 'VGT_OUT_LINE', - 2: 'VGT_OUT_TRI', - 3: 'VGT_OUT_RECT_V0', - 4: 'VGT_OUT_RECT_V1', - 5: 'VGT_OUT_RECT_V2', - 6: 'VGT_OUT_RECT_V3', - 7: 'VGT_OUT_2D_RECT', - 8: 'VGT_TE_QUAD', - 9: 'VGT_TE_PRIM_INDEX_LINE', - 10: 'VGT_TE_PRIM_INDEX_TRI', - 11: 'VGT_TE_PRIM_INDEX_QUAD', - 12: 'VGT_OUT_LINE_ADJ', - 13: 'VGT_OUT_TRI_ADJ', - 14: 'VGT_OUT_PATCH', -} -VGT_OUT_POINT = 0 -VGT_OUT_LINE = 1 -VGT_OUT_TRI = 2 -VGT_OUT_RECT_V0 = 3 -VGT_OUT_RECT_V1 = 4 -VGT_OUT_RECT_V2 = 5 -VGT_OUT_RECT_V3 = 6 -VGT_OUT_2D_RECT = 7 -VGT_TE_QUAD = 8 -VGT_TE_PRIM_INDEX_LINE = 9 -VGT_TE_PRIM_INDEX_TRI = 10 -VGT_TE_PRIM_INDEX_QUAD = 11 -VGT_OUT_LINE_ADJ = 12 -VGT_OUT_TRI_ADJ = 13 -VGT_OUT_PATCH = 14 -VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_PRIM_TYPE' -VGT_DI_PRIM_TYPE__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_2D_RECTANGLE', - 8: 'DI_PT_UNUSED_1', - 9: 'DI_PT_PATCH', - 10: 'DI_PT_LINELIST_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRILIST_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 14: 'DI_PT_UNUSED_3', - 15: 'DI_PT_UNUSED_4', - 16: 'DI_PT_TRI_WITH_WFLAGS', - 17: 'DI_PT_RECTLIST', - 18: 'DI_PT_LINELOOP', - 19: 'DI_PT_QUADLIST', - 20: 'DI_PT_QUADSTRIP', - 21: 'DI_PT_POLYGON', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_2D_RECTANGLE = 7 -DI_PT_UNUSED_1 = 8 -DI_PT_PATCH = 9 -DI_PT_LINELIST_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRILIST_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_UNUSED_3 = 14 -DI_PT_UNUSED_4 = 15 -DI_PT_TRI_WITH_WFLAGS = 16 -DI_PT_RECTLIST = 17 -DI_PT_LINELOOP = 18 -DI_PT_QUADLIST = 19 -DI_PT_QUADSTRIP = 20 -DI_PT_POLYGON = 21 -VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_SOURCE_SELECT' -VGT_DI_SOURCE_SELECT__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_RESERVED', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_RESERVED = 3 -VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' -VGT_DI_MAJOR_MODE_SELECT__enumvalues = { - 0: 'DI_MAJOR_MODE_0', - 1: 'DI_MAJOR_MODE_1', -} -DI_MAJOR_MODE_0 = 0 -DI_MAJOR_MODE_1 = 1 -VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_INDEX_SIZE' -VGT_DI_INDEX_SIZE__enumvalues = { - 0: 'DI_INDEX_SIZE_16_BIT', - 1: 'DI_INDEX_SIZE_32_BIT', - 2: 'DI_INDEX_SIZE_8_BIT', -} -DI_INDEX_SIZE_16_BIT = 0 -DI_INDEX_SIZE_32_BIT = 1 -DI_INDEX_SIZE_8_BIT = 2 -VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_EVENT_TYPE' -VGT_EVENT_TYPE__enumvalues = { - 0: 'Reserved_0x00', - 1: 'SAMPLE_STREAMOUTSTATS1', - 2: 'SAMPLE_STREAMOUTSTATS2', - 3: 'SAMPLE_STREAMOUTSTATS3', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'CS_PARTIAL_FLUSH', - 8: 'VGT_STREAMOUT_SYNC', - 9: 'Reserved_0x09', - 10: 'VGT_STREAMOUT_RESET', - 11: 'END_OF_PIPE_INCR_DE', - 12: 'END_OF_PIPE_IB_END', - 13: 'RST_PIX_CNT', - 14: 'BREAK_BATCH', - 15: 'VS_PARTIAL_FLUSH', - 16: 'PS_PARTIAL_FLUSH', - 17: 'FLUSH_HS_OUTPUT', - 18: 'FLUSH_DFSM', - 19: 'RESET_TO_LOWEST_VGT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'ZPASS_DONE', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 25: 'PIPELINESTAT_START', - 26: 'PIPELINESTAT_STOP', - 27: 'PERFCOUNTER_SAMPLE', - 28: 'Available_0x1c', - 29: 'Available_0x1d', - 30: 'SAMPLE_PIPELINESTAT', - 31: 'SO_VGTSTREAMOUT_FLUSH', - 32: 'SAMPLE_STREAMOUTSTATS', - 33: 'RESET_VTX_CNT', - 34: 'BLOCK_CONTEXT_DONE', - 35: 'CS_CONTEXT_DONE', - 36: 'VGT_FLUSH', - 37: 'TGID_ROLLOVER', - 38: 'SQ_NON_EVENT', - 39: 'SC_SEND_DB_VPZ', - 40: 'BOTTOM_OF_PIPE_TS', - 41: 'FLUSH_SX_TS', - 42: 'DB_CACHE_FLUSH_AND_INV', - 43: 'FLUSH_AND_INV_DB_DATA_TS', - 44: 'FLUSH_AND_INV_DB_META', - 45: 'FLUSH_AND_INV_CB_DATA_TS', - 46: 'FLUSH_AND_INV_CB_META', - 47: 'CS_DONE', - 48: 'PS_DONE', - 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', - 50: 'SX_CB_RAT_ACK_REQUEST', - 51: 'THREAD_TRACE_START', - 52: 'THREAD_TRACE_STOP', - 53: 'THREAD_TRACE_MARKER', - 54: 'THREAD_TRACE_FLUSH', - 55: 'THREAD_TRACE_FINISH', - 56: 'PIXEL_PIPE_STAT_CONTROL', - 57: 'PIXEL_PIPE_STAT_DUMP', - 58: 'PIXEL_PIPE_STAT_RESET', - 59: 'CONTEXT_SUSPEND', - 60: 'OFFCHIP_HS_DEALLOC', - 61: 'ENABLE_NGG_PIPELINE', - 62: 'ENABLE_LEGACY_PIPELINE', - 63: 'Reserved_0x3f', -} -Reserved_0x00 = 0 -SAMPLE_STREAMOUTSTATS1 = 1 -SAMPLE_STREAMOUTSTATS2 = 2 -SAMPLE_STREAMOUTSTATS3 = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -CS_PARTIAL_FLUSH = 7 -VGT_STREAMOUT_SYNC = 8 -Reserved_0x09 = 9 -VGT_STREAMOUT_RESET = 10 -END_OF_PIPE_INCR_DE = 11 -END_OF_PIPE_IB_END = 12 -RST_PIX_CNT = 13 -BREAK_BATCH = 14 -VS_PARTIAL_FLUSH = 15 -PS_PARTIAL_FLUSH = 16 -FLUSH_HS_OUTPUT = 17 -FLUSH_DFSM = 18 -RESET_TO_LOWEST_VGT = 19 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -ZPASS_DONE = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -PIPELINESTAT_START = 25 -PIPELINESTAT_STOP = 26 -PERFCOUNTER_SAMPLE = 27 -Available_0x1c = 28 -Available_0x1d = 29 -SAMPLE_PIPELINESTAT = 30 -SO_VGTSTREAMOUT_FLUSH = 31 -SAMPLE_STREAMOUTSTATS = 32 -RESET_VTX_CNT = 33 -BLOCK_CONTEXT_DONE = 34 -CS_CONTEXT_DONE = 35 -VGT_FLUSH = 36 -TGID_ROLLOVER = 37 -SQ_NON_EVENT = 38 -SC_SEND_DB_VPZ = 39 -BOTTOM_OF_PIPE_TS = 40 -FLUSH_SX_TS = 41 -DB_CACHE_FLUSH_AND_INV = 42 -FLUSH_AND_INV_DB_DATA_TS = 43 -FLUSH_AND_INV_DB_META = 44 -FLUSH_AND_INV_CB_DATA_TS = 45 -FLUSH_AND_INV_CB_META = 46 -CS_DONE = 47 -PS_DONE = 48 -FLUSH_AND_INV_CB_PIXEL_DATA = 49 -SX_CB_RAT_ACK_REQUEST = 50 -THREAD_TRACE_START = 51 -THREAD_TRACE_STOP = 52 -THREAD_TRACE_MARKER = 53 -THREAD_TRACE_FLUSH = 54 -THREAD_TRACE_FINISH = 55 -PIXEL_PIPE_STAT_CONTROL = 56 -PIXEL_PIPE_STAT_DUMP = 57 -PIXEL_PIPE_STAT_RESET = 58 -CONTEXT_SUSPEND = 59 -OFFCHIP_HS_DEALLOC = 60 -ENABLE_NGG_PIPELINE = 61 -ENABLE_LEGACY_PIPELINE = 62 -Reserved_0x3f = 63 -VGT_EVENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_SWAP_MODE' -VGT_DMA_SWAP_MODE__enumvalues = { - 0: 'VGT_DMA_SWAP_NONE', - 1: 'VGT_DMA_SWAP_16_BIT', - 2: 'VGT_DMA_SWAP_32_BIT', - 3: 'VGT_DMA_SWAP_WORD', -} -VGT_DMA_SWAP_NONE = 0 -VGT_DMA_SWAP_16_BIT = 1 -VGT_DMA_SWAP_32_BIT = 2 -VGT_DMA_SWAP_WORD = 3 -VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_INDEX_TYPE_MODE' -VGT_INDEX_TYPE_MODE__enumvalues = { - 0: 'VGT_INDEX_16', - 1: 'VGT_INDEX_32', - 2: 'VGT_INDEX_8', -} -VGT_INDEX_16 = 0 -VGT_INDEX_32 = 1 -VGT_INDEX_8 = 2 -VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_BUF_TYPE' -VGT_DMA_BUF_TYPE__enumvalues = { - 0: 'VGT_DMA_BUF_MEM', - 1: 'VGT_DMA_BUF_RING', - 2: 'VGT_DMA_BUF_SETUP', - 3: 'VGT_DMA_PTR_UPDATE', -} -VGT_DMA_BUF_MEM = 0 -VGT_DMA_BUF_RING = 1 -VGT_DMA_BUF_SETUP = 2 -VGT_DMA_PTR_UPDATE = 3 -VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUTPATH_SELECT' -VGT_OUTPATH_SELECT__enumvalues = { - 0: 'VGT_OUTPATH_VTX_REUSE', - 1: 'VGT_OUTPATH_TESS_EN', - 2: 'VGT_OUTPATH_PASSTHRU', - 3: 'VGT_OUTPATH_GS_BLOCK', - 4: 'VGT_OUTPATH_HS_BLOCK', - 5: 'VGT_OUTPATH_PRIM_GEN', -} -VGT_OUTPATH_VTX_REUSE = 0 -VGT_OUTPATH_TESS_EN = 1 -VGT_OUTPATH_PASSTHRU = 2 -VGT_OUTPATH_GS_BLOCK = 3 -VGT_OUTPATH_HS_BLOCK = 4 -VGT_OUTPATH_PRIM_GEN = 5 -VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GRP_PRIM_TYPE' -VGT_GRP_PRIM_TYPE__enumvalues = { - 0: 'VGT_GRP_3D_POINT', - 1: 'VGT_GRP_3D_LINE', - 2: 'VGT_GRP_3D_TRI', - 3: 'VGT_GRP_3D_RECT', - 4: 'VGT_GRP_3D_QUAD', - 5: 'VGT_GRP_2D_COPY_RECT_V0', - 6: 'VGT_GRP_2D_COPY_RECT_V1', - 7: 'VGT_GRP_2D_COPY_RECT_V2', - 8: 'VGT_GRP_2D_COPY_RECT_V3', - 9: 'VGT_GRP_2D_FILL_RECT', - 10: 'VGT_GRP_2D_LINE', - 11: 'VGT_GRP_2D_TRI', - 12: 'VGT_GRP_PRIM_INDEX_LINE', - 13: 'VGT_GRP_PRIM_INDEX_TRI', - 14: 'VGT_GRP_PRIM_INDEX_QUAD', - 15: 'VGT_GRP_3D_LINE_ADJ', - 16: 'VGT_GRP_3D_TRI_ADJ', - 17: 'VGT_GRP_3D_PATCH', - 18: 'VGT_GRP_2D_RECT', -} -VGT_GRP_3D_POINT = 0 -VGT_GRP_3D_LINE = 1 -VGT_GRP_3D_TRI = 2 -VGT_GRP_3D_RECT = 3 -VGT_GRP_3D_QUAD = 4 -VGT_GRP_2D_COPY_RECT_V0 = 5 -VGT_GRP_2D_COPY_RECT_V1 = 6 -VGT_GRP_2D_COPY_RECT_V2 = 7 -VGT_GRP_2D_COPY_RECT_V3 = 8 -VGT_GRP_2D_FILL_RECT = 9 -VGT_GRP_2D_LINE = 10 -VGT_GRP_2D_TRI = 11 -VGT_GRP_PRIM_INDEX_LINE = 12 -VGT_GRP_PRIM_INDEX_TRI = 13 -VGT_GRP_PRIM_INDEX_QUAD = 14 -VGT_GRP_3D_LINE_ADJ = 15 -VGT_GRP_3D_TRI_ADJ = 16 -VGT_GRP_3D_PATCH = 17 -VGT_GRP_2D_RECT = 18 -VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GRP_PRIM_ORDER' -VGT_GRP_PRIM_ORDER__enumvalues = { - 0: 'VGT_GRP_LIST', - 1: 'VGT_GRP_STRIP', - 2: 'VGT_GRP_FAN', - 3: 'VGT_GRP_LOOP', - 4: 'VGT_GRP_POLYGON', -} -VGT_GRP_LIST = 0 -VGT_GRP_STRIP = 1 -VGT_GRP_FAN = 2 -VGT_GRP_LOOP = 3 -VGT_GRP_POLYGON = 4 -VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GROUP_CONV_SEL' -VGT_GROUP_CONV_SEL__enumvalues = { - 0: 'VGT_GRP_INDEX_16', - 1: 'VGT_GRP_INDEX_32', - 2: 'VGT_GRP_UINT_16', - 3: 'VGT_GRP_UINT_32', - 4: 'VGT_GRP_SINT_16', - 5: 'VGT_GRP_SINT_32', - 6: 'VGT_GRP_FLOAT_32', - 7: 'VGT_GRP_AUTO_PRIM', - 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', -} -VGT_GRP_INDEX_16 = 0 -VGT_GRP_INDEX_32 = 1 -VGT_GRP_UINT_16 = 2 -VGT_GRP_UINT_32 = 3 -VGT_GRP_SINT_16 = 4 -VGT_GRP_SINT_32 = 5 -VGT_GRP_FLOAT_32 = 6 -VGT_GRP_AUTO_PRIM = 7 -VGT_GRP_FIX_1_23_TO_FLOAT = 8 -VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_MODE_TYPE' -VGT_GS_MODE_TYPE__enumvalues = { - 0: 'GS_OFF', - 1: 'GS_SCENARIO_A', - 2: 'GS_SCENARIO_B', - 3: 'GS_SCENARIO_G', - 4: 'GS_SCENARIO_C', - 5: 'SPRITE_EN', -} -GS_OFF = 0 -GS_SCENARIO_A = 1 -GS_SCENARIO_B = 2 -GS_SCENARIO_G = 3 -GS_SCENARIO_C = 4 -SPRITE_EN = 5 -VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_CUT_MODE' -VGT_GS_CUT_MODE__enumvalues = { - 0: 'GS_CUT_1024', - 1: 'GS_CUT_512', - 2: 'GS_CUT_256', - 3: 'GS_CUT_128', -} -GS_CUT_1024 = 0 -GS_CUT_512 = 1 -GS_CUT_256 = 2 -GS_CUT_128 = 3 -VGT_GS_CUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_OUTPRIM_TYPE' -VGT_GS_OUTPRIM_TYPE__enumvalues = { - 0: 'POINTLIST', - 1: 'LINESTRIP', - 2: 'TRISTRIP', - 3: 'RECTLIST', -} -POINTLIST = 0 -LINESTRIP = 1 -TRISTRIP = 2 -RECTLIST = 3 -VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_CACHE_INVALID_MODE' -VGT_CACHE_INVALID_MODE__enumvalues = { - 0: 'VC_ONLY', - 1: 'TC_ONLY', - 2: 'VC_AND_TC', -} -VC_ONLY = 0 -TC_ONLY = 1 -VC_AND_TC = 2 -VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TYPE' -VGT_TESS_TYPE__enumvalues = { - 0: 'TESS_ISOLINE', - 1: 'TESS_TRIANGLE', - 2: 'TESS_QUAD', -} -TESS_ISOLINE = 0 -TESS_TRIANGLE = 1 -TESS_QUAD = 2 -VGT_TESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_PARTITION' -VGT_TESS_PARTITION__enumvalues = { - 0: 'PART_INTEGER', - 1: 'PART_POW2', - 2: 'PART_FRAC_ODD', - 3: 'PART_FRAC_EVEN', -} -PART_INTEGER = 0 -PART_POW2 = 1 -PART_FRAC_ODD = 2 -PART_FRAC_EVEN = 3 -VGT_TESS_PARTITION = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TOPOLOGY' -VGT_TESS_TOPOLOGY__enumvalues = { - 0: 'OUTPUT_POINT', - 1: 'OUTPUT_LINE', - 2: 'OUTPUT_TRIANGLE_CW', - 3: 'OUTPUT_TRIANGLE_CCW', -} -OUTPUT_POINT = 0 -OUTPUT_LINE = 1 -OUTPUT_TRIANGLE_CW = 2 -OUTPUT_TRIANGLE_CCW = 3 -VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_RDREQ_POLICY' -VGT_RDREQ_POLICY__enumvalues = { - 0: 'VGT_POLICY_LRU', - 1: 'VGT_POLICY_STREAM', -} -VGT_POLICY_LRU = 0 -VGT_POLICY_STREAM = 1 -VGT_RDREQ_POLICY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DIST_MODE' -VGT_DIST_MODE__enumvalues = { - 0: 'NO_DIST', - 1: 'PATCHES', - 2: 'DONUTS', - 3: 'TRAPEZOIDS', -} -NO_DIST = 0 -PATCHES = 1 -DONUTS = 2 -TRAPEZOIDS = 3 -VGT_DIST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_LS_EN' -VGT_STAGES_LS_EN__enumvalues = { - 0: 'LS_STAGE_OFF', - 1: 'LS_STAGE_ON', - 2: 'CS_STAGE_ON', - 3: 'RESERVED_LS', -} -LS_STAGE_OFF = 0 -LS_STAGE_ON = 1 -CS_STAGE_ON = 2 -RESERVED_LS = 3 -VGT_STAGES_LS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_HS_EN' -VGT_STAGES_HS_EN__enumvalues = { - 0: 'HS_STAGE_OFF', - 1: 'HS_STAGE_ON', -} -HS_STAGE_OFF = 0 -HS_STAGE_ON = 1 -VGT_STAGES_HS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_ES_EN' -VGT_STAGES_ES_EN__enumvalues = { - 0: 'ES_STAGE_OFF', - 1: 'ES_STAGE_DS', - 2: 'ES_STAGE_REAL', - 3: 'RESERVED_ES', -} -ES_STAGE_OFF = 0 -ES_STAGE_DS = 1 -ES_STAGE_REAL = 2 -RESERVED_ES = 3 -VGT_STAGES_ES_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_GS_EN' -VGT_STAGES_GS_EN__enumvalues = { - 0: 'GS_STAGE_OFF', - 1: 'GS_STAGE_ON', -} -GS_STAGE_OFF = 0 -GS_STAGE_ON = 1 -VGT_STAGES_GS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_VS_EN' -VGT_STAGES_VS_EN__enumvalues = { - 0: 'VS_STAGE_REAL', - 1: 'VS_STAGE_DS', - 2: 'VS_STAGE_COPY_SHADER', - 3: 'RESERVED_VS', -} -VS_STAGE_REAL = 0 -VS_STAGE_DS = 1 -VS_STAGE_COPY_SHADER = 2 -RESERVED_VS = 3 -VGT_STAGES_VS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_PERFCOUNT_SELECT' -VGT_PERFCOUNT_SELECT__enumvalues = { - 0: 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', - 1: 'vgt_perf_VGT_SPI_ESVERT_VALID', - 2: 'vgt_perf_VGT_SPI_ESVERT_EOV', - 3: 'vgt_perf_VGT_SPI_ESVERT_STALLED', - 4: 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', - 5: 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', - 6: 'vgt_perf_VGT_SPI_ESVERT_STATIC', - 7: 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', - 8: 'vgt_perf_VGT_SPI_ESTHREAD_SEND', - 9: 'vgt_perf_VGT_SPI_GSPRIM_VALID', - 10: 'vgt_perf_VGT_SPI_GSPRIM_EOV', - 11: 'vgt_perf_VGT_SPI_GSPRIM_CONT', - 12: 'vgt_perf_VGT_SPI_GSPRIM_STALLED', - 13: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', - 14: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', - 15: 'vgt_perf_VGT_SPI_GSPRIM_STATIC', - 16: 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', - 17: 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', - 18: 'vgt_perf_VGT_SPI_GSTHREAD_SEND', - 19: 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', - 20: 'vgt_perf_VGT_SPI_VSVERT_SEND', - 21: 'vgt_perf_VGT_SPI_VSVERT_EOV', - 22: 'vgt_perf_VGT_SPI_VSVERT_STALLED', - 23: 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', - 24: 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', - 25: 'vgt_perf_VGT_SPI_VSVERT_STATIC', - 26: 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', - 27: 'vgt_perf_VGT_SPI_VSTHREAD_SEND', - 28: 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', - 29: 'vgt_perf_VGT_PA_CLIPV_SEND', - 30: 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', - 31: 'vgt_perf_VGT_PA_CLIPV_STALLED', - 32: 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', - 33: 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', - 34: 'vgt_perf_VGT_PA_CLIPV_STATIC', - 35: 'vgt_perf_VGT_PA_CLIPP_SEND', - 36: 'vgt_perf_VGT_PA_CLIPP_EOP', - 37: 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', - 38: 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', - 39: 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', - 40: 'vgt_perf_VGT_PA_CLIPP_STALLED', - 41: 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', - 42: 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', - 43: 'vgt_perf_VGT_PA_CLIPP_STATIC', - 44: 'vgt_perf_VGT_PA_CLIPS_SEND', - 45: 'vgt_perf_VGT_PA_CLIPS_STALLED', - 46: 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', - 47: 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', - 48: 'vgt_perf_VGT_PA_CLIPS_STATIC', - 49: 'vgt_perf_vsvert_ds_send', - 50: 'vgt_perf_vsvert_api_send', - 51: 'vgt_perf_hs_tif_stall', - 52: 'vgt_perf_hs_input_stall', - 53: 'vgt_perf_hs_interface_stall', - 54: 'vgt_perf_hs_tfm_stall', - 55: 'vgt_perf_te11_starved', - 56: 'vgt_perf_gs_event_stall', - 57: 'vgt_perf_vgt_pa_clipp_send_not_event', - 58: 'vgt_perf_vgt_pa_clipp_valid_prim', - 59: 'vgt_perf_reused_es_indices', - 60: 'vgt_perf_vs_cache_hits', - 61: 'vgt_perf_gs_cache_hits', - 62: 'vgt_perf_ds_cache_hits', - 63: 'vgt_perf_total_cache_hits', - 64: 'vgt_perf_vgt_busy', - 65: 'vgt_perf_vgt_gs_busy', - 66: 'vgt_perf_esvert_stalled_es_tbl', - 67: 'vgt_perf_esvert_stalled_gs_tbl', - 68: 'vgt_perf_esvert_stalled_gs_event', - 69: 'vgt_perf_esvert_stalled_gsprim', - 70: 'vgt_perf_gsprim_stalled_es_tbl', - 71: 'vgt_perf_gsprim_stalled_gs_tbl', - 72: 'vgt_perf_gsprim_stalled_gs_event', - 73: 'vgt_perf_gsprim_stalled_esvert', - 74: 'vgt_perf_esthread_stalled_es_rb_full', - 75: 'vgt_perf_esthread_stalled_spi_bp', - 76: 'vgt_perf_counters_avail_stalled', - 77: 'vgt_perf_gs_rb_space_avail_stalled', - 78: 'vgt_perf_gs_issue_rtr_stalled', - 79: 'vgt_perf_gsthread_stalled', - 80: 'vgt_perf_strmout_stalled', - 81: 'vgt_perf_wait_for_es_done_stalled', - 82: 'vgt_perf_cm_stalled_by_gog', - 83: 'vgt_perf_cm_reading_stalled', - 84: 'vgt_perf_cm_stalled_by_gsfetch_done', - 85: 'vgt_perf_gog_vs_tbl_stalled', - 86: 'vgt_perf_gog_out_indx_stalled', - 87: 'vgt_perf_gog_out_prim_stalled', - 88: 'vgt_perf_waveid_stalled', - 89: 'vgt_perf_gog_busy', - 90: 'vgt_perf_reused_vs_indices', - 91: 'vgt_perf_sclk_reg_vld_event', - 92: 'vgt_perf_vs_conflicting_indices', - 93: 'vgt_perf_sclk_core_vld_event', - 94: 'vgt_perf_hswave_stalled', - 95: 'vgt_perf_sclk_gs_vld_event', - 96: 'vgt_perf_VGT_SPI_LSVERT_VALID', - 97: 'vgt_perf_VGT_SPI_LSVERT_EOV', - 98: 'vgt_perf_VGT_SPI_LSVERT_STALLED', - 99: 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', - 100: 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', - 101: 'vgt_perf_VGT_SPI_LSVERT_STATIC', - 102: 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', - 103: 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', - 104: 'vgt_perf_VGT_SPI_LSWAVE_SEND', - 105: 'vgt_perf_VGT_SPI_HSVERT_VALID', - 106: 'vgt_perf_VGT_SPI_HSVERT_EOV', - 107: 'vgt_perf_VGT_SPI_HSVERT_STALLED', - 108: 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', - 109: 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', - 110: 'vgt_perf_VGT_SPI_HSVERT_STATIC', - 111: 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', - 112: 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', - 113: 'vgt_perf_VGT_SPI_HSWAVE_SEND', - 114: 'vgt_perf_ds_prims', - 115: 'vgt_perf_ds_RESERVED', - 116: 'vgt_perf_ls_thread_groups', - 117: 'vgt_perf_hs_thread_groups', - 118: 'vgt_perf_es_thread_groups', - 119: 'vgt_perf_vs_thread_groups', - 120: 'vgt_perf_ls_done_latency', - 121: 'vgt_perf_hs_done_latency', - 122: 'vgt_perf_es_done_latency', - 123: 'vgt_perf_gs_done_latency', - 124: 'vgt_perf_vgt_hs_busy', - 125: 'vgt_perf_vgt_te11_busy', - 126: 'vgt_perf_ls_flush', - 127: 'vgt_perf_hs_flush', - 128: 'vgt_perf_es_flush', - 129: 'vgt_perf_vgt_pa_clipp_eopg', - 130: 'vgt_perf_ls_done', - 131: 'vgt_perf_hs_done', - 132: 'vgt_perf_es_done', - 133: 'vgt_perf_gs_done', - 134: 'vgt_perf_vsfetch_done', - 135: 'vgt_perf_gs_done_received', - 136: 'vgt_perf_es_ring_high_water_mark', - 137: 'vgt_perf_gs_ring_high_water_mark', - 138: 'vgt_perf_vs_table_high_water_mark', - 139: 'vgt_perf_hs_tgs_active_high_water_mark', - 140: 'vgt_perf_pa_clipp_dealloc', - 141: 'vgt_perf_cut_mem_flush_stalled', - 142: 'vgt_perf_vsvert_work_received', - 143: 'vgt_perf_vgt_pa_clipp_starved_after_work', - 144: 'vgt_perf_te11_con_starved_after_work', - 145: 'vgt_perf_hs_waiting_on_ls_done_stall', - 146: 'vgt_spi_vsvert_valid', -} -vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0 -vgt_perf_VGT_SPI_ESVERT_VALID = 1 -vgt_perf_VGT_SPI_ESVERT_EOV = 2 -vgt_perf_VGT_SPI_ESVERT_STALLED = 3 -vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 4 -vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 5 -vgt_perf_VGT_SPI_ESVERT_STATIC = 6 -vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 7 -vgt_perf_VGT_SPI_ESTHREAD_SEND = 8 -vgt_perf_VGT_SPI_GSPRIM_VALID = 9 -vgt_perf_VGT_SPI_GSPRIM_EOV = 10 -vgt_perf_VGT_SPI_GSPRIM_CONT = 11 -vgt_perf_VGT_SPI_GSPRIM_STALLED = 12 -vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 13 -vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 14 -vgt_perf_VGT_SPI_GSPRIM_STATIC = 15 -vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 16 -vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 17 -vgt_perf_VGT_SPI_GSTHREAD_SEND = 18 -vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 19 -vgt_perf_VGT_SPI_VSVERT_SEND = 20 -vgt_perf_VGT_SPI_VSVERT_EOV = 21 -vgt_perf_VGT_SPI_VSVERT_STALLED = 22 -vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 23 -vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 24 -vgt_perf_VGT_SPI_VSVERT_STATIC = 25 -vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 26 -vgt_perf_VGT_SPI_VSTHREAD_SEND = 27 -vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 28 -vgt_perf_VGT_PA_CLIPV_SEND = 29 -vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 30 -vgt_perf_VGT_PA_CLIPV_STALLED = 31 -vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 32 -vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 33 -vgt_perf_VGT_PA_CLIPV_STATIC = 34 -vgt_perf_VGT_PA_CLIPP_SEND = 35 -vgt_perf_VGT_PA_CLIPP_EOP = 36 -vgt_perf_VGT_PA_CLIPP_IS_EVENT = 37 -vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 38 -vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 39 -vgt_perf_VGT_PA_CLIPP_STALLED = 40 -vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 41 -vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 42 -vgt_perf_VGT_PA_CLIPP_STATIC = 43 -vgt_perf_VGT_PA_CLIPS_SEND = 44 -vgt_perf_VGT_PA_CLIPS_STALLED = 45 -vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 46 -vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 47 -vgt_perf_VGT_PA_CLIPS_STATIC = 48 -vgt_perf_vsvert_ds_send = 49 -vgt_perf_vsvert_api_send = 50 -vgt_perf_hs_tif_stall = 51 -vgt_perf_hs_input_stall = 52 -vgt_perf_hs_interface_stall = 53 -vgt_perf_hs_tfm_stall = 54 -vgt_perf_te11_starved = 55 -vgt_perf_gs_event_stall = 56 -vgt_perf_vgt_pa_clipp_send_not_event = 57 -vgt_perf_vgt_pa_clipp_valid_prim = 58 -vgt_perf_reused_es_indices = 59 -vgt_perf_vs_cache_hits = 60 -vgt_perf_gs_cache_hits = 61 -vgt_perf_ds_cache_hits = 62 -vgt_perf_total_cache_hits = 63 -vgt_perf_vgt_busy = 64 -vgt_perf_vgt_gs_busy = 65 -vgt_perf_esvert_stalled_es_tbl = 66 -vgt_perf_esvert_stalled_gs_tbl = 67 -vgt_perf_esvert_stalled_gs_event = 68 -vgt_perf_esvert_stalled_gsprim = 69 -vgt_perf_gsprim_stalled_es_tbl = 70 -vgt_perf_gsprim_stalled_gs_tbl = 71 -vgt_perf_gsprim_stalled_gs_event = 72 -vgt_perf_gsprim_stalled_esvert = 73 -vgt_perf_esthread_stalled_es_rb_full = 74 -vgt_perf_esthread_stalled_spi_bp = 75 -vgt_perf_counters_avail_stalled = 76 -vgt_perf_gs_rb_space_avail_stalled = 77 -vgt_perf_gs_issue_rtr_stalled = 78 -vgt_perf_gsthread_stalled = 79 -vgt_perf_strmout_stalled = 80 -vgt_perf_wait_for_es_done_stalled = 81 -vgt_perf_cm_stalled_by_gog = 82 -vgt_perf_cm_reading_stalled = 83 -vgt_perf_cm_stalled_by_gsfetch_done = 84 -vgt_perf_gog_vs_tbl_stalled = 85 -vgt_perf_gog_out_indx_stalled = 86 -vgt_perf_gog_out_prim_stalled = 87 -vgt_perf_waveid_stalled = 88 -vgt_perf_gog_busy = 89 -vgt_perf_reused_vs_indices = 90 -vgt_perf_sclk_reg_vld_event = 91 -vgt_perf_vs_conflicting_indices = 92 -vgt_perf_sclk_core_vld_event = 93 -vgt_perf_hswave_stalled = 94 -vgt_perf_sclk_gs_vld_event = 95 -vgt_perf_VGT_SPI_LSVERT_VALID = 96 -vgt_perf_VGT_SPI_LSVERT_EOV = 97 -vgt_perf_VGT_SPI_LSVERT_STALLED = 98 -vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 99 -vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 100 -vgt_perf_VGT_SPI_LSVERT_STATIC = 101 -vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 102 -vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 103 -vgt_perf_VGT_SPI_LSWAVE_SEND = 104 -vgt_perf_VGT_SPI_HSVERT_VALID = 105 -vgt_perf_VGT_SPI_HSVERT_EOV = 106 -vgt_perf_VGT_SPI_HSVERT_STALLED = 107 -vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 108 -vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 109 -vgt_perf_VGT_SPI_HSVERT_STATIC = 110 -vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 111 -vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 112 -vgt_perf_VGT_SPI_HSWAVE_SEND = 113 -vgt_perf_ds_prims = 114 -vgt_perf_ds_RESERVED = 115 -vgt_perf_ls_thread_groups = 116 -vgt_perf_hs_thread_groups = 117 -vgt_perf_es_thread_groups = 118 -vgt_perf_vs_thread_groups = 119 -vgt_perf_ls_done_latency = 120 -vgt_perf_hs_done_latency = 121 -vgt_perf_es_done_latency = 122 -vgt_perf_gs_done_latency = 123 -vgt_perf_vgt_hs_busy = 124 -vgt_perf_vgt_te11_busy = 125 -vgt_perf_ls_flush = 126 -vgt_perf_hs_flush = 127 -vgt_perf_es_flush = 128 -vgt_perf_vgt_pa_clipp_eopg = 129 -vgt_perf_ls_done = 130 -vgt_perf_hs_done = 131 -vgt_perf_es_done = 132 -vgt_perf_gs_done = 133 -vgt_perf_vsfetch_done = 134 -vgt_perf_gs_done_received = 135 -vgt_perf_es_ring_high_water_mark = 136 -vgt_perf_gs_ring_high_water_mark = 137 -vgt_perf_vs_table_high_water_mark = 138 -vgt_perf_hs_tgs_active_high_water_mark = 139 -vgt_perf_pa_clipp_dealloc = 140 -vgt_perf_cut_mem_flush_stalled = 141 -vgt_perf_vsvert_work_received = 142 -vgt_perf_vgt_pa_clipp_starved_after_work = 143 -vgt_perf_te11_con_starved_after_work = 144 -vgt_perf_hs_waiting_on_ls_done_stall = 145 -vgt_spi_vsvert_valid = 146 -VGT_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'IA_PERFCOUNT_SELECT' -IA_PERFCOUNT_SELECT__enumvalues = { - 0: 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', - 1: 'ia_perf_dma_data_fifo_full', - 2: 'ia_perf_RESERVED1', - 3: 'ia_perf_RESERVED2', - 4: 'ia_perf_RESERVED3', - 5: 'ia_perf_RESERVED4', - 6: 'ia_perf_RESERVED5', - 7: 'ia_perf_MC_LAT_BIN_0', - 8: 'ia_perf_MC_LAT_BIN_1', - 9: 'ia_perf_MC_LAT_BIN_2', - 10: 'ia_perf_MC_LAT_BIN_3', - 11: 'ia_perf_MC_LAT_BIN_4', - 12: 'ia_perf_MC_LAT_BIN_5', - 13: 'ia_perf_MC_LAT_BIN_6', - 14: 'ia_perf_MC_LAT_BIN_7', - 15: 'ia_perf_ia_busy', - 16: 'ia_perf_ia_sclk_reg_vld_event', - 17: 'ia_perf_RESERVED6', - 18: 'ia_perf_ia_sclk_core_vld_event', - 19: 'ia_perf_RESERVED7', - 20: 'ia_perf_ia_dma_return', - 21: 'ia_perf_ia_stalled', - 22: 'ia_perf_shift_starved_pipe0_event', - 23: 'ia_perf_shift_starved_pipe1_event', -} -ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0 -ia_perf_dma_data_fifo_full = 1 -ia_perf_RESERVED1 = 2 -ia_perf_RESERVED2 = 3 -ia_perf_RESERVED3 = 4 -ia_perf_RESERVED4 = 5 -ia_perf_RESERVED5 = 6 -ia_perf_MC_LAT_BIN_0 = 7 -ia_perf_MC_LAT_BIN_1 = 8 -ia_perf_MC_LAT_BIN_2 = 9 -ia_perf_MC_LAT_BIN_3 = 10 -ia_perf_MC_LAT_BIN_4 = 11 -ia_perf_MC_LAT_BIN_5 = 12 -ia_perf_MC_LAT_BIN_6 = 13 -ia_perf_MC_LAT_BIN_7 = 14 -ia_perf_ia_busy = 15 -ia_perf_ia_sclk_reg_vld_event = 16 -ia_perf_RESERVED6 = 17 -ia_perf_ia_sclk_core_vld_event = 18 -ia_perf_RESERVED7 = 19 -ia_perf_ia_dma_return = 20 -ia_perf_ia_stalled = 21 -ia_perf_shift_starved_pipe0_event = 22 -ia_perf_shift_starved_pipe1_event = 23 -IA_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'WD_PERFCOUNT_SELECT' -WD_PERFCOUNT_SELECT__enumvalues = { - 0: 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', - 1: 'wd_perf_RBIU_DR_FIFO_STARVED', - 2: 'wd_perf_RBIU_DR_FIFO_STALLED', - 3: 'wd_perf_RBIU_DI_FIFO_STARVED', - 4: 'wd_perf_RBIU_DI_FIFO_STALLED', - 5: 'wd_perf_wd_busy', - 6: 'wd_perf_wd_sclk_reg_vld_event', - 7: 'wd_perf_wd_sclk_input_vld_event', - 8: 'wd_perf_wd_sclk_core_vld_event', - 9: 'wd_perf_wd_stalled', - 10: 'wd_perf_inside_tf_bin_0', - 11: 'wd_perf_inside_tf_bin_1', - 12: 'wd_perf_inside_tf_bin_2', - 13: 'wd_perf_inside_tf_bin_3', - 14: 'wd_perf_inside_tf_bin_4', - 15: 'wd_perf_inside_tf_bin_5', - 16: 'wd_perf_inside_tf_bin_6', - 17: 'wd_perf_inside_tf_bin_7', - 18: 'wd_perf_inside_tf_bin_8', - 19: 'wd_perf_tfreq_lat_bin_0', - 20: 'wd_perf_tfreq_lat_bin_1', - 21: 'wd_perf_tfreq_lat_bin_2', - 22: 'wd_perf_tfreq_lat_bin_3', - 23: 'wd_perf_tfreq_lat_bin_4', - 24: 'wd_perf_tfreq_lat_bin_5', - 25: 'wd_perf_tfreq_lat_bin_6', - 26: 'wd_perf_tfreq_lat_bin_7', - 27: 'wd_starved_on_hs_done', - 28: 'wd_perf_se0_hs_done_latency', - 29: 'wd_perf_se1_hs_done_latency', - 30: 'wd_perf_se2_hs_done_latency', - 31: 'wd_perf_se3_hs_done_latency', - 32: 'wd_perf_hs_done_se0', - 33: 'wd_perf_hs_done_se1', - 34: 'wd_perf_hs_done_se2', - 35: 'wd_perf_hs_done_se3', - 36: 'wd_perf_null_patches', -} -wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0 -wd_perf_RBIU_DR_FIFO_STARVED = 1 -wd_perf_RBIU_DR_FIFO_STALLED = 2 -wd_perf_RBIU_DI_FIFO_STARVED = 3 -wd_perf_RBIU_DI_FIFO_STALLED = 4 -wd_perf_wd_busy = 5 -wd_perf_wd_sclk_reg_vld_event = 6 -wd_perf_wd_sclk_input_vld_event = 7 -wd_perf_wd_sclk_core_vld_event = 8 -wd_perf_wd_stalled = 9 -wd_perf_inside_tf_bin_0 = 10 -wd_perf_inside_tf_bin_1 = 11 -wd_perf_inside_tf_bin_2 = 12 -wd_perf_inside_tf_bin_3 = 13 -wd_perf_inside_tf_bin_4 = 14 -wd_perf_inside_tf_bin_5 = 15 -wd_perf_inside_tf_bin_6 = 16 -wd_perf_inside_tf_bin_7 = 17 -wd_perf_inside_tf_bin_8 = 18 -wd_perf_tfreq_lat_bin_0 = 19 -wd_perf_tfreq_lat_bin_1 = 20 -wd_perf_tfreq_lat_bin_2 = 21 -wd_perf_tfreq_lat_bin_3 = 22 -wd_perf_tfreq_lat_bin_4 = 23 -wd_perf_tfreq_lat_bin_5 = 24 -wd_perf_tfreq_lat_bin_6 = 25 -wd_perf_tfreq_lat_bin_7 = 26 -wd_starved_on_hs_done = 27 -wd_perf_se0_hs_done_latency = 28 -wd_perf_se1_hs_done_latency = 29 -wd_perf_se2_hs_done_latency = 30 -wd_perf_se3_hs_done_latency = 31 -wd_perf_hs_done_se0 = 32 -wd_perf_hs_done_se1 = 33 -wd_perf_hs_done_se2 = 34 -wd_perf_hs_done_se3 = 35 -wd_perf_null_patches = 36 -WD_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_TYPE' -WD_IA_DRAW_TYPE__enumvalues = { - 0: 'WD_IA_DRAW_TYPE_DI_MM0', - 1: 'WD_IA_DRAW_TYPE_REG_XFER', - 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', - 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 4: 'WD_IA_DRAW_TYPE_MIN_INDX', - 5: 'WD_IA_DRAW_TYPE_MAX_INDX', - 6: 'WD_IA_DRAW_TYPE_INDX_OFF', - 7: 'WD_IA_DRAW_TYPE_IMM_DATA', -} -WD_IA_DRAW_TYPE_DI_MM0 = 0 -WD_IA_DRAW_TYPE_REG_XFER = 1 -WD_IA_DRAW_TYPE_EVENT_INIT = 2 -WD_IA_DRAW_TYPE_EVENT_ADDR = 3 -WD_IA_DRAW_TYPE_MIN_INDX = 4 -WD_IA_DRAW_TYPE_MAX_INDX = 5 -WD_IA_DRAW_TYPE_INDX_OFF = 6 -WD_IA_DRAW_TYPE_IMM_DATA = 7 -WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_REG_XFER' -WD_IA_DRAW_REG_XFER__enumvalues = { - 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', -} -WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 -WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_SOURCE' -WD_IA_DRAW_SOURCE__enumvalues = { - 0: 'WD_IA_DRAW_SOURCE_DMA', - 1: 'WD_IA_DRAW_SOURCE_IMMD', - 2: 'WD_IA_DRAW_SOURCE_AUTO', - 3: 'WD_IA_DRAW_SOURCE_OPAQ', -} -WD_IA_DRAW_SOURCE_DMA = 0 -WD_IA_DRAW_SOURCE_IMMD = 1 -WD_IA_DRAW_SOURCE_AUTO = 2 -WD_IA_DRAW_SOURCE_OPAQ = 3 -WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'GB_EDC_DED_MODE' -GB_EDC_DED_MODE__enumvalues = { - 0: 'GB_EDC_DED_MODE_LOG', - 1: 'GB_EDC_DED_MODE_HALT', - 2: 'GB_EDC_DED_MODE_INT_HALT', -} -GB_EDC_DED_MODE_LOG = 0 -GB_EDC_DED_MODE_HALT = 1 -GB_EDC_DED_MODE_INT_HALT = 2 -GB_EDC_DED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_ADDR_MODES' -TA_TC_ADDR_MODES__enumvalues = { - 0: 'TA_TC_ADDR_MODE_DEFAULT', - 1: 'TA_TC_ADDR_MODE_COMP0', - 2: 'TA_TC_ADDR_MODE_COMP1', - 3: 'TA_TC_ADDR_MODE_COMP2', - 4: 'TA_TC_ADDR_MODE_COMP3', - 5: 'TA_TC_ADDR_MODE_UNALIGNED', - 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', -} -TA_TC_ADDR_MODE_DEFAULT = 0 -TA_TC_ADDR_MODE_COMP0 = 1 -TA_TC_ADDR_MODE_COMP1 = 2 -TA_TC_ADDR_MODE_COMP2 = 3 -TA_TC_ADDR_MODE_COMP3 = 4 -TA_TC_ADDR_MODE_UNALIGNED = 5 -TA_TC_ADDR_MODE_BORDER_COLOR = 6 -TA_TC_ADDR_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_PERFCOUNT_SEL' -TA_PERFCOUNT_SEL__enumvalues = { - 0: 'TA_PERF_SEL_NULL', - 1: 'TA_PERF_SEL_sh_fifo_busy', - 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', - 3: 'TA_PERF_SEL_sh_fifo_addr_busy', - 4: 'TA_PERF_SEL_sh_fifo_data_busy', - 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', - 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', - 7: 'TA_PERF_SEL_gradient_busy', - 8: 'TA_PERF_SEL_gradient_fifo_busy', - 9: 'TA_PERF_SEL_lod_busy', - 10: 'TA_PERF_SEL_lod_fifo_busy', - 11: 'TA_PERF_SEL_addresser_busy', - 12: 'TA_PERF_SEL_addresser_fifo_busy', - 13: 'TA_PERF_SEL_aligner_busy', - 14: 'TA_PERF_SEL_write_path_busy', - 15: 'TA_PERF_SEL_ta_busy', - 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', - 17: 'TA_PERF_SEL_sp_ta_addr_cycles', - 18: 'TA_PERF_SEL_sp_ta_data_cycles', - 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', - 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', - 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', - 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', - 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', - 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', - 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', - 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', - 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', - 28: 'TA_PERF_SEL_RESERVED_28', - 29: 'TA_PERF_SEL_RESERVED_29', - 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', - 31: 'TA_PERF_SEL_sh_fifo_data_cycles', - 32: 'TA_PERF_SEL_total_wavefronts', - 33: 'TA_PERF_SEL_gradient_cycles', - 34: 'TA_PERF_SEL_walker_cycles', - 35: 'TA_PERF_SEL_aligner_cycles', - 36: 'TA_PERF_SEL_image_wavefronts', - 37: 'TA_PERF_SEL_image_read_wavefronts', - 38: 'TA_PERF_SEL_image_write_wavefronts', - 39: 'TA_PERF_SEL_image_atomic_wavefronts', - 40: 'TA_PERF_SEL_image_total_cycles', - 41: 'TA_PERF_SEL_RESERVED_41', - 42: 'TA_PERF_SEL_RESERVED_42', - 43: 'TA_PERF_SEL_RESERVED_43', - 44: 'TA_PERF_SEL_buffer_wavefronts', - 45: 'TA_PERF_SEL_buffer_read_wavefronts', - 46: 'TA_PERF_SEL_buffer_write_wavefronts', - 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', - 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', - 49: 'TA_PERF_SEL_buffer_total_cycles', - 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', - 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', - 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', - 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', - 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', - 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 58: 'TA_PERF_SEL_addresser_stalled_cycles', - 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 60: 'TA_PERF_SEL_aniso_stalled_cycles', - 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 62: 'TA_PERF_SEL_deriv_stalled_cycles', - 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 64: 'TA_PERF_SEL_color_1_cycle_pixels', - 65: 'TA_PERF_SEL_color_2_cycle_pixels', - 66: 'TA_PERF_SEL_color_3_cycle_pixels', - 67: 'TA_PERF_SEL_color_4_cycle_pixels', - 68: 'TA_PERF_SEL_mip_1_cycle_pixels', - 69: 'TA_PERF_SEL_mip_2_cycle_pixels', - 70: 'TA_PERF_SEL_vol_1_cycle_pixels', - 71: 'TA_PERF_SEL_vol_2_cycle_pixels', - 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', - 73: 'TA_PERF_SEL_mipmap_lod_0_samples', - 74: 'TA_PERF_SEL_mipmap_lod_1_samples', - 75: 'TA_PERF_SEL_mipmap_lod_2_samples', - 76: 'TA_PERF_SEL_mipmap_lod_3_samples', - 77: 'TA_PERF_SEL_mipmap_lod_4_samples', - 78: 'TA_PERF_SEL_mipmap_lod_5_samples', - 79: 'TA_PERF_SEL_mipmap_lod_6_samples', - 80: 'TA_PERF_SEL_mipmap_lod_7_samples', - 81: 'TA_PERF_SEL_mipmap_lod_8_samples', - 82: 'TA_PERF_SEL_mipmap_lod_9_samples', - 83: 'TA_PERF_SEL_mipmap_lod_10_samples', - 84: 'TA_PERF_SEL_mipmap_lod_11_samples', - 85: 'TA_PERF_SEL_mipmap_lod_12_samples', - 86: 'TA_PERF_SEL_mipmap_lod_13_samples', - 87: 'TA_PERF_SEL_mipmap_lod_14_samples', - 88: 'TA_PERF_SEL_mipmap_invalid_samples', - 89: 'TA_PERF_SEL_aniso_1_cycle_quads', - 90: 'TA_PERF_SEL_aniso_2_cycle_quads', - 91: 'TA_PERF_SEL_aniso_4_cycle_quads', - 92: 'TA_PERF_SEL_aniso_6_cycle_quads', - 93: 'TA_PERF_SEL_aniso_8_cycle_quads', - 94: 'TA_PERF_SEL_aniso_10_cycle_quads', - 95: 'TA_PERF_SEL_aniso_12_cycle_quads', - 96: 'TA_PERF_SEL_aniso_14_cycle_quads', - 97: 'TA_PERF_SEL_aniso_16_cycle_quads', - 98: 'TA_PERF_SEL_write_path_input_cycles', - 99: 'TA_PERF_SEL_write_path_output_cycles', - 100: 'TA_PERF_SEL_flat_wavefronts', - 101: 'TA_PERF_SEL_flat_read_wavefronts', - 102: 'TA_PERF_SEL_flat_write_wavefronts', - 103: 'TA_PERF_SEL_flat_atomic_wavefronts', - 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', - 105: 'TA_PERF_SEL_reg_sclk_vld', - 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', - 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', - 111: 'TA_PERF_SEL_xnack_on_phase0', - 112: 'TA_PERF_SEL_xnack_on_phase1', - 113: 'TA_PERF_SEL_xnack_on_phase2', - 114: 'TA_PERF_SEL_xnack_on_phase3', - 115: 'TA_PERF_SEL_first_xnack_on_phase0', - 116: 'TA_PERF_SEL_first_xnack_on_phase1', - 117: 'TA_PERF_SEL_first_xnack_on_phase2', - 118: 'TA_PERF_SEL_first_xnack_on_phase3', -} -TA_PERF_SEL_NULL = 0 -TA_PERF_SEL_sh_fifo_busy = 1 -TA_PERF_SEL_sh_fifo_cmd_busy = 2 -TA_PERF_SEL_sh_fifo_addr_busy = 3 -TA_PERF_SEL_sh_fifo_data_busy = 4 -TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 -TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 -TA_PERF_SEL_gradient_busy = 7 -TA_PERF_SEL_gradient_fifo_busy = 8 -TA_PERF_SEL_lod_busy = 9 -TA_PERF_SEL_lod_fifo_busy = 10 -TA_PERF_SEL_addresser_busy = 11 -TA_PERF_SEL_addresser_fifo_busy = 12 -TA_PERF_SEL_aligner_busy = 13 -TA_PERF_SEL_write_path_busy = 14 -TA_PERF_SEL_ta_busy = 15 -TA_PERF_SEL_sq_ta_cmd_cycles = 16 -TA_PERF_SEL_sp_ta_addr_cycles = 17 -TA_PERF_SEL_sp_ta_data_cycles = 18 -TA_PERF_SEL_ta_fa_data_state_cycles = 19 -TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 -TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 -TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 -TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 -TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 -TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 -TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 -TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 -TA_PERF_SEL_RESERVED_28 = 28 -TA_PERF_SEL_RESERVED_29 = 29 -TA_PERF_SEL_sh_fifo_addr_cycles = 30 -TA_PERF_SEL_sh_fifo_data_cycles = 31 -TA_PERF_SEL_total_wavefronts = 32 -TA_PERF_SEL_gradient_cycles = 33 -TA_PERF_SEL_walker_cycles = 34 -TA_PERF_SEL_aligner_cycles = 35 -TA_PERF_SEL_image_wavefronts = 36 -TA_PERF_SEL_image_read_wavefronts = 37 -TA_PERF_SEL_image_write_wavefronts = 38 -TA_PERF_SEL_image_atomic_wavefronts = 39 -TA_PERF_SEL_image_total_cycles = 40 -TA_PERF_SEL_RESERVED_41 = 41 -TA_PERF_SEL_RESERVED_42 = 42 -TA_PERF_SEL_RESERVED_43 = 43 -TA_PERF_SEL_buffer_wavefronts = 44 -TA_PERF_SEL_buffer_read_wavefronts = 45 -TA_PERF_SEL_buffer_write_wavefronts = 46 -TA_PERF_SEL_buffer_atomic_wavefronts = 47 -TA_PERF_SEL_buffer_coalescable_wavefronts = 48 -TA_PERF_SEL_buffer_total_cycles = 49 -TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 -TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 -TA_PERF_SEL_buffer_coalesced_read_cycles = 52 -TA_PERF_SEL_buffer_coalesced_write_cycles = 53 -TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 -TA_PERF_SEL_addr_stalled_by_td_cycles = 55 -TA_PERF_SEL_data_stalled_by_tc_cycles = 56 -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 -TA_PERF_SEL_addresser_stalled_cycles = 58 -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 -TA_PERF_SEL_aniso_stalled_cycles = 60 -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 -TA_PERF_SEL_deriv_stalled_cycles = 62 -TA_PERF_SEL_aniso_gt1_cycle_quads = 63 -TA_PERF_SEL_color_1_cycle_pixels = 64 -TA_PERF_SEL_color_2_cycle_pixels = 65 -TA_PERF_SEL_color_3_cycle_pixels = 66 -TA_PERF_SEL_color_4_cycle_pixels = 67 -TA_PERF_SEL_mip_1_cycle_pixels = 68 -TA_PERF_SEL_mip_2_cycle_pixels = 69 -TA_PERF_SEL_vol_1_cycle_pixels = 70 -TA_PERF_SEL_vol_2_cycle_pixels = 71 -TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 -TA_PERF_SEL_mipmap_lod_0_samples = 73 -TA_PERF_SEL_mipmap_lod_1_samples = 74 -TA_PERF_SEL_mipmap_lod_2_samples = 75 -TA_PERF_SEL_mipmap_lod_3_samples = 76 -TA_PERF_SEL_mipmap_lod_4_samples = 77 -TA_PERF_SEL_mipmap_lod_5_samples = 78 -TA_PERF_SEL_mipmap_lod_6_samples = 79 -TA_PERF_SEL_mipmap_lod_7_samples = 80 -TA_PERF_SEL_mipmap_lod_8_samples = 81 -TA_PERF_SEL_mipmap_lod_9_samples = 82 -TA_PERF_SEL_mipmap_lod_10_samples = 83 -TA_PERF_SEL_mipmap_lod_11_samples = 84 -TA_PERF_SEL_mipmap_lod_12_samples = 85 -TA_PERF_SEL_mipmap_lod_13_samples = 86 -TA_PERF_SEL_mipmap_lod_14_samples = 87 -TA_PERF_SEL_mipmap_invalid_samples = 88 -TA_PERF_SEL_aniso_1_cycle_quads = 89 -TA_PERF_SEL_aniso_2_cycle_quads = 90 -TA_PERF_SEL_aniso_4_cycle_quads = 91 -TA_PERF_SEL_aniso_6_cycle_quads = 92 -TA_PERF_SEL_aniso_8_cycle_quads = 93 -TA_PERF_SEL_aniso_10_cycle_quads = 94 -TA_PERF_SEL_aniso_12_cycle_quads = 95 -TA_PERF_SEL_aniso_14_cycle_quads = 96 -TA_PERF_SEL_aniso_16_cycle_quads = 97 -TA_PERF_SEL_write_path_input_cycles = 98 -TA_PERF_SEL_write_path_output_cycles = 99 -TA_PERF_SEL_flat_wavefronts = 100 -TA_PERF_SEL_flat_read_wavefronts = 101 -TA_PERF_SEL_flat_write_wavefronts = 102 -TA_PERF_SEL_flat_atomic_wavefronts = 103 -TA_PERF_SEL_flat_coalesceable_wavefronts = 104 -TA_PERF_SEL_reg_sclk_vld = 105 -TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 -TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 -TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 -TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 -TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 -TA_PERF_SEL_xnack_on_phase0 = 111 -TA_PERF_SEL_xnack_on_phase1 = 112 -TA_PERF_SEL_xnack_on_phase2 = 113 -TA_PERF_SEL_xnack_on_phase3 = 114 -TA_PERF_SEL_first_xnack_on_phase0 = 115 -TA_PERF_SEL_first_xnack_on_phase1 = 116 -TA_PERF_SEL_first_xnack_on_phase2 = 117 -TA_PERF_SEL_first_xnack_on_phase3 = 118 -TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TD_PERFCOUNT_SEL' -TD_PERFCOUNT_SEL__enumvalues = { - 0: 'TD_PERF_SEL_none', - 1: 'TD_PERF_SEL_td_busy', - 2: 'TD_PERF_SEL_input_busy', - 3: 'TD_PERF_SEL_output_busy', - 4: 'TD_PERF_SEL_lerp_busy', - 5: 'TD_PERF_SEL_reg_sclk_vld', - 6: 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 7: 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 8: 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 9: 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', - 10: 'TD_PERF_SEL_tc_td_fifo_full', - 11: 'TD_PERF_SEL_constant_state_full', - 12: 'TD_PERF_SEL_sample_state_full', - 13: 'TD_PERF_SEL_output_fifo_full', - 14: 'TD_PERF_SEL_RESERVED_14', - 15: 'TD_PERF_SEL_tc_stall', - 16: 'TD_PERF_SEL_pc_stall', - 17: 'TD_PERF_SEL_gds_stall', - 18: 'TD_PERF_SEL_RESERVED_18', - 19: 'TD_PERF_SEL_RESERVED_19', - 20: 'TD_PERF_SEL_gather4_wavefront', - 21: 'TD_PERF_SEL_gather4h_wavefront', - 22: 'TD_PERF_SEL_gather4h_packed_wavefront', - 23: 'TD_PERF_SEL_gather8h_packed_wavefront', - 24: 'TD_PERF_SEL_sample_c_wavefront', - 25: 'TD_PERF_SEL_load_wavefront', - 26: 'TD_PERF_SEL_atomic_wavefront', - 27: 'TD_PERF_SEL_store_wavefront', - 28: 'TD_PERF_SEL_ldfptr_wavefront', - 29: 'TD_PERF_SEL_d16_en_wavefront', - 30: 'TD_PERF_SEL_bypass_filter_wavefront', - 31: 'TD_PERF_SEL_min_max_filter_wavefront', - 32: 'TD_PERF_SEL_coalescable_wavefront', - 33: 'TD_PERF_SEL_coalesced_phase', - 34: 'TD_PERF_SEL_four_phase_wavefront', - 35: 'TD_PERF_SEL_eight_phase_wavefront', - 36: 'TD_PERF_SEL_sixteen_phase_wavefront', - 37: 'TD_PERF_SEL_four_phase_forward_wavefront', - 38: 'TD_PERF_SEL_write_ack_wavefront', - 39: 'TD_PERF_SEL_RESERVED_39', - 40: 'TD_PERF_SEL_user_defined_border', - 41: 'TD_PERF_SEL_white_border', - 42: 'TD_PERF_SEL_opaque_black_border', - 43: 'TD_PERF_SEL_RESERVED_43', - 44: 'TD_PERF_SEL_RESERVED_44', - 45: 'TD_PERF_SEL_nack', - 46: 'TD_PERF_SEL_td_sp_traffic', - 47: 'TD_PERF_SEL_consume_gds_traffic', - 48: 'TD_PERF_SEL_addresscmd_poison', - 49: 'TD_PERF_SEL_data_poison', - 50: 'TD_PERF_SEL_start_cycle_0', - 51: 'TD_PERF_SEL_start_cycle_1', - 52: 'TD_PERF_SEL_start_cycle_2', - 53: 'TD_PERF_SEL_start_cycle_3', - 54: 'TD_PERF_SEL_null_cycle_output', - 55: 'TD_PERF_SEL_d16_data_packed', - 56: 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', -} -TD_PERF_SEL_none = 0 -TD_PERF_SEL_td_busy = 1 -TD_PERF_SEL_input_busy = 2 -TD_PERF_SEL_output_busy = 3 -TD_PERF_SEL_lerp_busy = 4 -TD_PERF_SEL_reg_sclk_vld = 5 -TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 6 -TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 7 -TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 8 -TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 9 -TD_PERF_SEL_tc_td_fifo_full = 10 -TD_PERF_SEL_constant_state_full = 11 -TD_PERF_SEL_sample_state_full = 12 -TD_PERF_SEL_output_fifo_full = 13 -TD_PERF_SEL_RESERVED_14 = 14 -TD_PERF_SEL_tc_stall = 15 -TD_PERF_SEL_pc_stall = 16 -TD_PERF_SEL_gds_stall = 17 -TD_PERF_SEL_RESERVED_18 = 18 -TD_PERF_SEL_RESERVED_19 = 19 -TD_PERF_SEL_gather4_wavefront = 20 -TD_PERF_SEL_gather4h_wavefront = 21 -TD_PERF_SEL_gather4h_packed_wavefront = 22 -TD_PERF_SEL_gather8h_packed_wavefront = 23 -TD_PERF_SEL_sample_c_wavefront = 24 -TD_PERF_SEL_load_wavefront = 25 -TD_PERF_SEL_atomic_wavefront = 26 -TD_PERF_SEL_store_wavefront = 27 -TD_PERF_SEL_ldfptr_wavefront = 28 -TD_PERF_SEL_d16_en_wavefront = 29 -TD_PERF_SEL_bypass_filter_wavefront = 30 -TD_PERF_SEL_min_max_filter_wavefront = 31 -TD_PERF_SEL_coalescable_wavefront = 32 -TD_PERF_SEL_coalesced_phase = 33 -TD_PERF_SEL_four_phase_wavefront = 34 -TD_PERF_SEL_eight_phase_wavefront = 35 -TD_PERF_SEL_sixteen_phase_wavefront = 36 -TD_PERF_SEL_four_phase_forward_wavefront = 37 -TD_PERF_SEL_write_ack_wavefront = 38 -TD_PERF_SEL_RESERVED_39 = 39 -TD_PERF_SEL_user_defined_border = 40 -TD_PERF_SEL_white_border = 41 -TD_PERF_SEL_opaque_black_border = 42 -TD_PERF_SEL_RESERVED_43 = 43 -TD_PERF_SEL_RESERVED_44 = 44 -TD_PERF_SEL_nack = 45 -TD_PERF_SEL_td_sp_traffic = 46 -TD_PERF_SEL_consume_gds_traffic = 47 -TD_PERF_SEL_addresscmd_poison = 48 -TD_PERF_SEL_data_poison = 49 -TD_PERF_SEL_start_cycle_0 = 50 -TD_PERF_SEL_start_cycle_1 = 51 -TD_PERF_SEL_start_cycle_2 = 52 -TD_PERF_SEL_start_cycle_3 = 53 -TD_PERF_SEL_null_cycle_output = 54 -TD_PERF_SEL_d16_data_packed = 55 -TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 56 -TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_PERFCOUNT_SELECT' -TCP_PERFCOUNT_SELECT__enumvalues = { - 0: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', - 1: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', - 2: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', - 3: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', - 4: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', - 5: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', - 6: 'TCP_PERF_SEL_LOD_STALL_CYCLES', - 7: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', - 8: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', - 9: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', - 10: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', - 11: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', - 12: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', - 13: 'TCP_PERF_SEL_TCR_RDRET_STALL', - 14: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', - 15: 'TCP_PERF_SEL_HOLE_READ_STALL', - 16: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', - 17: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', - 18: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', - 19: 'TCP_PERF_SEL_TCP_LATENCY', - 20: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', - 21: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', - 22: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', - 23: 'TCP_PERF_SEL_TCC_READ_REQ', - 24: 'TCP_PERF_SEL_TCC_WRITE_REQ', - 25: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', - 26: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', - 27: 'TCP_PERF_SEL_TOTAL_LOCAL_READ', - 28: 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', - 29: 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', - 30: 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', - 31: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', - 32: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', - 33: 'TCP_PERF_SEL_TOTAL_WBINVL1', - 34: 'TCP_PERF_SEL_IMG_READ_FMT_1', - 35: 'TCP_PERF_SEL_IMG_READ_FMT_8', - 36: 'TCP_PERF_SEL_IMG_READ_FMT_16', - 37: 'TCP_PERF_SEL_IMG_READ_FMT_32', - 38: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', - 39: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', - 40: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', - 41: 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', - 42: 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', - 43: 'TCP_PERF_SEL_IMG_READ_FMT_96', - 44: 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', - 45: 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', - 46: 'TCP_PERF_SEL_IMG_READ_FMT_BC1', - 47: 'TCP_PERF_SEL_IMG_READ_FMT_BC2', - 48: 'TCP_PERF_SEL_IMG_READ_FMT_BC3', - 49: 'TCP_PERF_SEL_IMG_READ_FMT_BC4', - 50: 'TCP_PERF_SEL_IMG_READ_FMT_BC5', - 51: 'TCP_PERF_SEL_IMG_READ_FMT_BC6', - 52: 'TCP_PERF_SEL_IMG_READ_FMT_BC7', - 53: 'TCP_PERF_SEL_IMG_READ_FMT_I8', - 54: 'TCP_PERF_SEL_IMG_READ_FMT_I16', - 55: 'TCP_PERF_SEL_IMG_READ_FMT_I32', - 56: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', - 57: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', - 58: 'TCP_PERF_SEL_IMG_READ_FMT_D8', - 59: 'TCP_PERF_SEL_IMG_READ_FMT_D16', - 60: 'TCP_PERF_SEL_IMG_READ_FMT_D32', - 61: 'TCP_PERF_SEL_IMG_WRITE_FMT_8', - 62: 'TCP_PERF_SEL_IMG_WRITE_FMT_16', - 63: 'TCP_PERF_SEL_IMG_WRITE_FMT_32', - 64: 'TCP_PERF_SEL_IMG_WRITE_FMT_64', - 65: 'TCP_PERF_SEL_IMG_WRITE_FMT_128', - 66: 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', - 67: 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', - 68: 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', - 69: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', - 70: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', - 71: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', - 72: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', - 73: 'TCP_PERF_SEL_BUF_READ_FMT_8', - 74: 'TCP_PERF_SEL_BUF_READ_FMT_16', - 75: 'TCP_PERF_SEL_BUF_READ_FMT_32', - 76: 'TCP_PERF_SEL_BUF_WRITE_FMT_8', - 77: 'TCP_PERF_SEL_BUF_WRITE_FMT_16', - 78: 'TCP_PERF_SEL_BUF_WRITE_FMT_32', - 79: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', - 80: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', - 81: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', - 82: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', - 83: 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', - 84: 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', - 85: 'TCP_PERF_SEL_ARR_1D_THIN1', - 86: 'TCP_PERF_SEL_ARR_1D_THICK', - 87: 'TCP_PERF_SEL_ARR_2D_THIN1', - 88: 'TCP_PERF_SEL_ARR_2D_THICK', - 89: 'TCP_PERF_SEL_ARR_2D_XTHICK', - 90: 'TCP_PERF_SEL_ARR_3D_THIN1', - 91: 'TCP_PERF_SEL_ARR_3D_THICK', - 92: 'TCP_PERF_SEL_ARR_3D_XTHICK', - 93: 'TCP_PERF_SEL_DIM_1D', - 94: 'TCP_PERF_SEL_DIM_2D', - 95: 'TCP_PERF_SEL_DIM_3D', - 96: 'TCP_PERF_SEL_DIM_1D_ARRAY', - 97: 'TCP_PERF_SEL_DIM_2D_ARRAY', - 98: 'TCP_PERF_SEL_DIM_2D_MSAA', - 99: 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', - 100: 'TCP_PERF_SEL_DIM_CUBE_ARRAY', - 101: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', - 102: 'TCP_PERF_SEL_TA_TCP_STATE_READ', - 103: 'TCP_PERF_SEL_TAGRAM0_REQ', - 104: 'TCP_PERF_SEL_TAGRAM1_REQ', - 105: 'TCP_PERF_SEL_TAGRAM2_REQ', - 106: 'TCP_PERF_SEL_TAGRAM3_REQ', - 107: 'TCP_PERF_SEL_GATE_EN1', - 108: 'TCP_PERF_SEL_GATE_EN2', - 109: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', - 110: 'TCP_PERF_SEL_TCC_REQ', - 111: 'TCP_PERF_SEL_TCC_NON_READ_REQ', - 112: 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', - 113: 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', - 114: 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', - 115: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', - 116: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', - 117: 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', - 118: 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', - 119: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', - 120: 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', - 121: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', - 122: 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', - 123: 'TCP_PERF_SEL_TCC_ATOMIC_REQ', - 124: 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', - 125: 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', - 126: 'TCP_PERF_SEL_TOTAL_ACCESSES', - 127: 'TCP_PERF_SEL_TOTAL_READ', - 128: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', - 129: 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', - 130: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', - 131: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', - 132: 'TCP_PERF_SEL_TOTAL_NON_READ', - 133: 'TCP_PERF_SEL_TOTAL_WRITE', - 134: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', - 135: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', - 136: 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', - 137: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', - 138: 'TCP_PERF_SEL_DISPLAY_MICROTILING', - 139: 'TCP_PERF_SEL_THIN_MICROTILING', - 140: 'TCP_PERF_SEL_DEPTH_MICROTILING', - 141: 'TCP_PERF_SEL_ARR_PRT_THIN1', - 142: 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', - 143: 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', - 144: 'TCP_PERF_SEL_ARR_PRT_THICK', - 145: 'TCP_PERF_SEL_ARR_PRT_2D_THICK', - 146: 'TCP_PERF_SEL_ARR_PRT_3D_THICK', - 147: 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', - 148: 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', - 149: 'TCP_PERF_SEL_UNALIGNED', - 150: 'TCP_PERF_SEL_ROTATED_MICROTILING', - 151: 'TCP_PERF_SEL_THICK_MICROTILING', - 152: 'TCP_PERF_SEL_ATC', - 153: 'TCP_PERF_SEL_POWER_STALL', - 154: 'TCP_PERF_SEL_RESERVED_154', - 155: 'TCP_PERF_SEL_TCC_LRU_REQ', - 156: 'TCP_PERF_SEL_TCC_STREAM_REQ', - 157: 'TCP_PERF_SEL_TCC_NC_READ_REQ', - 158: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', - 159: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', - 160: 'TCP_PERF_SEL_TCC_UC_READ_REQ', - 161: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', - 162: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', - 163: 'TCP_PERF_SEL_TCC_CC_READ_REQ', - 164: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', - 165: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', - 166: 'TCP_PERF_SEL_TCC_DCC_REQ', - 167: 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', - 168: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 169: 'TCP_PERF_SEL_VOLATILE', - 170: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', - 171: 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', - 172: 'TCP_PERF_SEL_SHOOTDOWN', - 173: 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', - 174: 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', - 175: 'TCP_PERF_SEL_UTCL1_REQUEST', - 176: 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 177: 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 178: 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', - 179: 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 180: 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 181: 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', - 182: 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 183: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', - 184: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', - 185: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', - 186: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', - 187: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', - 188: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', - 189: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', - 190: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', - 191: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', - 192: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', - 193: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', - 194: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', - 195: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', -} -TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0 -TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 1 -TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 2 -TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 3 -TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 4 -TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 5 -TCP_PERF_SEL_LOD_STALL_CYCLES = 6 -TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 7 -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 8 -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 9 -TCP_PERF_SEL_ALLOC_STALL_CYCLES = 10 -TCP_PERF_SEL_LFIFO_STALL_CYCLES = 11 -TCP_PERF_SEL_RFIFO_STALL_CYCLES = 12 -TCP_PERF_SEL_TCR_RDRET_STALL = 13 -TCP_PERF_SEL_WRITE_CONFLICT_STALL = 14 -TCP_PERF_SEL_HOLE_READ_STALL = 15 -TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 16 -TCP_PERF_SEL_PENDING_STALL_CYCLES = 17 -TCP_PERF_SEL_READFIFO_STALL_CYCLES = 18 -TCP_PERF_SEL_TCP_LATENCY = 19 -TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 20 -TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 21 -TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 22 -TCP_PERF_SEL_TCC_READ_REQ = 23 -TCP_PERF_SEL_TCC_WRITE_REQ = 24 -TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 25 -TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 26 -TCP_PERF_SEL_TOTAL_LOCAL_READ = 27 -TCP_PERF_SEL_TOTAL_GLOBAL_READ = 28 -TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 29 -TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 30 -TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 31 -TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 32 -TCP_PERF_SEL_TOTAL_WBINVL1 = 33 -TCP_PERF_SEL_IMG_READ_FMT_1 = 34 -TCP_PERF_SEL_IMG_READ_FMT_8 = 35 -TCP_PERF_SEL_IMG_READ_FMT_16 = 36 -TCP_PERF_SEL_IMG_READ_FMT_32 = 37 -TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 38 -TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 39 -TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 40 -TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 41 -TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 42 -TCP_PERF_SEL_IMG_READ_FMT_96 = 43 -TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 44 -TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 45 -TCP_PERF_SEL_IMG_READ_FMT_BC1 = 46 -TCP_PERF_SEL_IMG_READ_FMT_BC2 = 47 -TCP_PERF_SEL_IMG_READ_FMT_BC3 = 48 -TCP_PERF_SEL_IMG_READ_FMT_BC4 = 49 -TCP_PERF_SEL_IMG_READ_FMT_BC5 = 50 -TCP_PERF_SEL_IMG_READ_FMT_BC6 = 51 -TCP_PERF_SEL_IMG_READ_FMT_BC7 = 52 -TCP_PERF_SEL_IMG_READ_FMT_I8 = 53 -TCP_PERF_SEL_IMG_READ_FMT_I16 = 54 -TCP_PERF_SEL_IMG_READ_FMT_I32 = 55 -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 56 -TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 57 -TCP_PERF_SEL_IMG_READ_FMT_D8 = 58 -TCP_PERF_SEL_IMG_READ_FMT_D16 = 59 -TCP_PERF_SEL_IMG_READ_FMT_D32 = 60 -TCP_PERF_SEL_IMG_WRITE_FMT_8 = 61 -TCP_PERF_SEL_IMG_WRITE_FMT_16 = 62 -TCP_PERF_SEL_IMG_WRITE_FMT_32 = 63 -TCP_PERF_SEL_IMG_WRITE_FMT_64 = 64 -TCP_PERF_SEL_IMG_WRITE_FMT_128 = 65 -TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 66 -TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 67 -TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 68 -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 69 -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 70 -TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 71 -TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 72 -TCP_PERF_SEL_BUF_READ_FMT_8 = 73 -TCP_PERF_SEL_BUF_READ_FMT_16 = 74 -TCP_PERF_SEL_BUF_READ_FMT_32 = 75 -TCP_PERF_SEL_BUF_WRITE_FMT_8 = 76 -TCP_PERF_SEL_BUF_WRITE_FMT_16 = 77 -TCP_PERF_SEL_BUF_WRITE_FMT_32 = 78 -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 79 -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 80 -TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 81 -TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 82 -TCP_PERF_SEL_ARR_LINEAR_GENERAL = 83 -TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 84 -TCP_PERF_SEL_ARR_1D_THIN1 = 85 -TCP_PERF_SEL_ARR_1D_THICK = 86 -TCP_PERF_SEL_ARR_2D_THIN1 = 87 -TCP_PERF_SEL_ARR_2D_THICK = 88 -TCP_PERF_SEL_ARR_2D_XTHICK = 89 -TCP_PERF_SEL_ARR_3D_THIN1 = 90 -TCP_PERF_SEL_ARR_3D_THICK = 91 -TCP_PERF_SEL_ARR_3D_XTHICK = 92 -TCP_PERF_SEL_DIM_1D = 93 -TCP_PERF_SEL_DIM_2D = 94 -TCP_PERF_SEL_DIM_3D = 95 -TCP_PERF_SEL_DIM_1D_ARRAY = 96 -TCP_PERF_SEL_DIM_2D_ARRAY = 97 -TCP_PERF_SEL_DIM_2D_MSAA = 98 -TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 99 -TCP_PERF_SEL_DIM_CUBE_ARRAY = 100 -TCP_PERF_SEL_CP_TCP_INVALIDATE = 101 -TCP_PERF_SEL_TA_TCP_STATE_READ = 102 -TCP_PERF_SEL_TAGRAM0_REQ = 103 -TCP_PERF_SEL_TAGRAM1_REQ = 104 -TCP_PERF_SEL_TAGRAM2_REQ = 105 -TCP_PERF_SEL_TAGRAM3_REQ = 106 -TCP_PERF_SEL_GATE_EN1 = 107 -TCP_PERF_SEL_GATE_EN2 = 108 -TCP_PERF_SEL_CORE_REG_SCLK_VLD = 109 -TCP_PERF_SEL_TCC_REQ = 110 -TCP_PERF_SEL_TCC_NON_READ_REQ = 111 -TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 112 -TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 113 -TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 114 -TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 115 -TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 116 -TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 117 -TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 118 -TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 119 -TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 120 -TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 121 -TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 122 -TCP_PERF_SEL_TCC_ATOMIC_REQ = 123 -TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 124 -TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 125 -TCP_PERF_SEL_TOTAL_ACCESSES = 126 -TCP_PERF_SEL_TOTAL_READ = 127 -TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 128 -TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 129 -TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 130 -TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 131 -TCP_PERF_SEL_TOTAL_NON_READ = 132 -TCP_PERF_SEL_TOTAL_WRITE = 133 -TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 134 -TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 135 -TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 136 -TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 137 -TCP_PERF_SEL_DISPLAY_MICROTILING = 138 -TCP_PERF_SEL_THIN_MICROTILING = 139 -TCP_PERF_SEL_DEPTH_MICROTILING = 140 -TCP_PERF_SEL_ARR_PRT_THIN1 = 141 -TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 142 -TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 143 -TCP_PERF_SEL_ARR_PRT_THICK = 144 -TCP_PERF_SEL_ARR_PRT_2D_THICK = 145 -TCP_PERF_SEL_ARR_PRT_3D_THICK = 146 -TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 147 -TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 148 -TCP_PERF_SEL_UNALIGNED = 149 -TCP_PERF_SEL_ROTATED_MICROTILING = 150 -TCP_PERF_SEL_THICK_MICROTILING = 151 -TCP_PERF_SEL_ATC = 152 -TCP_PERF_SEL_POWER_STALL = 153 -TCP_PERF_SEL_RESERVED_154 = 154 -TCP_PERF_SEL_TCC_LRU_REQ = 155 -TCP_PERF_SEL_TCC_STREAM_REQ = 156 -TCP_PERF_SEL_TCC_NC_READ_REQ = 157 -TCP_PERF_SEL_TCC_NC_WRITE_REQ = 158 -TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 159 -TCP_PERF_SEL_TCC_UC_READ_REQ = 160 -TCP_PERF_SEL_TCC_UC_WRITE_REQ = 161 -TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 162 -TCP_PERF_SEL_TCC_CC_READ_REQ = 163 -TCP_PERF_SEL_TCC_CC_WRITE_REQ = 164 -TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 165 -TCP_PERF_SEL_TCC_DCC_REQ = 166 -TCP_PERF_SEL_TCC_PHYSICAL_REQ = 167 -TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 168 -TCP_PERF_SEL_VOLATILE = 169 -TCP_PERF_SEL_TC_TA_XNACK_STALL = 170 -TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 171 -TCP_PERF_SEL_SHOOTDOWN = 172 -TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 173 -TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 174 -TCP_PERF_SEL_UTCL1_REQUEST = 175 -TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 176 -TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 177 -TCP_PERF_SEL_UTCL1_LFIFO_FULL = 178 -TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 179 -TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 180 -TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 181 -TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 182 -TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 183 -TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 184 -TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 185 -TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 186 -TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 187 -TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 188 -TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 189 -TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 190 -TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 191 -TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 192 -TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 193 -TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 194 -TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 195 -TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_POLICIES' -TCP_CACHE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_POLICY_MISS_LRU', - 1: 'TCP_CACHE_POLICY_MISS_EVICT', - 2: 'TCP_CACHE_POLICY_HIT_LRU', - 3: 'TCP_CACHE_POLICY_HIT_EVICT', -} -TCP_CACHE_POLICY_MISS_LRU = 0 -TCP_CACHE_POLICY_MISS_EVICT = 1 -TCP_CACHE_POLICY_HIT_LRU = 2 -TCP_CACHE_POLICY_HIT_EVICT = 3 -TCP_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_STORE_POLICIES' -TCP_CACHE_STORE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', - 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', -} -TCP_CACHE_STORE_POLICY_WT_LRU = 0 -TCP_CACHE_STORE_POLICY_WT_EVICT = 1 -TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WATCH_MODES' -TCP_WATCH_MODES__enumvalues = { - 0: 'TCP_WATCH_MODE_READ', - 1: 'TCP_WATCH_MODE_NONREAD', - 2: 'TCP_WATCH_MODE_ATOMIC', - 3: 'TCP_WATCH_MODE_ALL', -} -TCP_WATCH_MODE_READ = 0 -TCP_WATCH_MODE_NONREAD = 1 -TCP_WATCH_MODE_ATOMIC = 2 -TCP_WATCH_MODE_ALL = 3 -TCP_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_DATA_SEL' -TCP_DSM_DATA_SEL__enumvalues = { - 0: 'TCP_DSM_DISABLE', - 1: 'TCP_DSM_SEL0', - 2: 'TCP_DSM_SEL1', - 3: 'TCP_DSM_SEL_BOTH', -} -TCP_DSM_DISABLE = 0 -TCP_DSM_SEL0 = 1 -TCP_DSM_SEL1 = 2 -TCP_DSM_SEL_BOTH = 3 -TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_SINGLE_WRITE' -TCP_DSM_SINGLE_WRITE__enumvalues = { - 0: 'TCP_DSM_SINGLE_WRITE_DIS', - 1: 'TCP_DSM_SINGLE_WRITE_EN', -} -TCP_DSM_SINGLE_WRITE_DIS = 0 -TCP_DSM_SINGLE_WRITE_EN = 1 -TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_INJECT_SEL' -TCP_DSM_INJECT_SEL__enumvalues = { - 0: 'TCP_DSM_INJECT_SEL0', - 1: 'TCP_DSM_INJECT_SEL1', - 2: 'TCP_DSM_INJECT_SEL2', - 3: 'TCP_DSM_INJECT_SEL3', -} -TCP_DSM_INJECT_SEL0 = 0 -TCP_DSM_INJECT_SEL1 = 1 -TCP_DSM_INJECT_SEL2 = 2 -TCP_DSM_INJECT_SEL3 = 3 -TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_PERF_SEL' -TCC_PERF_SEL__enumvalues = { - 0: 'TCC_PERF_SEL_NONE', - 1: 'TCC_PERF_SEL_CYCLE', - 2: 'TCC_PERF_SEL_BUSY', - 3: 'TCC_PERF_SEL_REQ', - 4: 'TCC_PERF_SEL_STREAMING_REQ', - 5: 'TCC_PERF_SEL_EXE_REQ', - 6: 'TCC_PERF_SEL_COMPRESSED_REQ', - 7: 'TCC_PERF_SEL_COMPRESSED_0_REQ', - 8: 'TCC_PERF_SEL_METADATA_REQ', - 9: 'TCC_PERF_SEL_NC_VIRTUAL_REQ', - 10: 'TCC_PERF_SEL_UC_VIRTUAL_REQ', - 11: 'TCC_PERF_SEL_CC_PHYSICAL_REQ', - 12: 'TCC_PERF_SEL_PROBE', - 13: 'TCC_PERF_SEL_PROBE_ALL', - 14: 'TCC_PERF_SEL_READ', - 15: 'TCC_PERF_SEL_WRITE', - 16: 'TCC_PERF_SEL_ATOMIC', - 17: 'TCC_PERF_SEL_HIT', - 18: 'TCC_PERF_SEL_SECTOR_HIT', - 19: 'TCC_PERF_SEL_MISS', - 20: 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', - 21: 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', - 22: 'TCC_PERF_SEL_WRITEBACK', - 23: 'TCC_PERF_SEL_LATENCY_FIFO_FULL', - 24: 'TCC_PERF_SEL_SRC_FIFO_FULL', - 25: 'TCC_PERF_SEL_HOLE_FIFO_FULL', - 26: 'TCC_PERF_SEL_EA_WRREQ', - 27: 'TCC_PERF_SEL_EA_WRREQ_64B', - 28: 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 29: 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', - 30: 'TCC_PERF_SEL_EA_WRREQ_STALL', - 31: 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', - 32: 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 33: 'TCC_PERF_SEL_EA_WRREQ_LEVEL', - 34: 'TCC_PERF_SEL_EA_ATOMIC', - 35: 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', - 36: 'TCC_PERF_SEL_EA_RDREQ', - 37: 'TCC_PERF_SEL_EA_RDREQ_32B', - 38: 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', - 39: 'TCC_PERF_SEL_EA_RD_MDC_32B', - 40: 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', - 41: 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', - 42: 'TCC_PERF_SEL_EA_RDREQ_LEVEL', - 43: 'TCC_PERF_SEL_TAG_STALL', - 44: 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 45: 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 46: 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 47: 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 48: 'TCC_PERF_SEL_TAG_PROBE_STALL', - 49: 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', - 50: 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', - 51: 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 52: 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 53: 'TCC_PERF_SEL_BUBBLE', - 54: 'TCC_PERF_SEL_RETURN_ACK', - 55: 'TCC_PERF_SEL_RETURN_DATA', - 56: 'TCC_PERF_SEL_RETURN_HOLE', - 57: 'TCC_PERF_SEL_RETURN_ACK_HOLE', - 58: 'TCC_PERF_SEL_IB_REQ', - 59: 'TCC_PERF_SEL_IB_STALL', - 60: 'TCC_PERF_SEL_IB_TAG_STALL', - 61: 'TCC_PERF_SEL_IB_MDC_STALL', - 62: 'TCC_PERF_SEL_TCA_LEVEL', - 63: 'TCC_PERF_SEL_HOLE_LEVEL', - 64: 'TCC_PERF_SEL_NORMAL_WRITEBACK', - 65: 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', - 66: 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', - 67: 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', - 68: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', - 69: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', - 70: 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', - 71: 'TCC_PERF_SEL_NORMAL_EVICT', - 72: 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', - 73: 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', - 74: 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', - 75: 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', - 76: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', - 77: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', - 78: 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', - 79: 'TCC_PERF_SEL_PROBE_EVICT', - 80: 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', - 81: 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', - 82: 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', - 83: 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', - 84: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', - 85: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', - 86: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', - 87: 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', - 88: 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', - 89: 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', - 90: 'TCC_PERF_SEL_TC_OP_WBINVL2_START', - 91: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', - 92: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', - 93: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 94: 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', - 95: 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', - 96: 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', - 97: 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', - 98: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', - 99: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', - 100: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', - 101: 'TCC_PERF_SEL_MDC_REQ', - 102: 'TCC_PERF_SEL_MDC_LEVEL', - 103: 'TCC_PERF_SEL_MDC_TAG_HIT', - 104: 'TCC_PERF_SEL_MDC_SECTOR_HIT', - 105: 'TCC_PERF_SEL_MDC_SECTOR_MISS', - 106: 'TCC_PERF_SEL_MDC_TAG_STALL', - 107: 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 108: 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 109: 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 110: 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 111: 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', - 128: 'TCC_PERF_SEL_CLIENT0_REQ', - 129: 'TCC_PERF_SEL_CLIENT1_REQ', - 130: 'TCC_PERF_SEL_CLIENT2_REQ', - 131: 'TCC_PERF_SEL_CLIENT3_REQ', - 132: 'TCC_PERF_SEL_CLIENT4_REQ', - 133: 'TCC_PERF_SEL_CLIENT5_REQ', - 134: 'TCC_PERF_SEL_CLIENT6_REQ', - 135: 'TCC_PERF_SEL_CLIENT7_REQ', - 136: 'TCC_PERF_SEL_CLIENT8_REQ', - 137: 'TCC_PERF_SEL_CLIENT9_REQ', - 138: 'TCC_PERF_SEL_CLIENT10_REQ', - 139: 'TCC_PERF_SEL_CLIENT11_REQ', - 140: 'TCC_PERF_SEL_CLIENT12_REQ', - 141: 'TCC_PERF_SEL_CLIENT13_REQ', - 142: 'TCC_PERF_SEL_CLIENT14_REQ', - 143: 'TCC_PERF_SEL_CLIENT15_REQ', - 144: 'TCC_PERF_SEL_CLIENT16_REQ', - 145: 'TCC_PERF_SEL_CLIENT17_REQ', - 146: 'TCC_PERF_SEL_CLIENT18_REQ', - 147: 'TCC_PERF_SEL_CLIENT19_REQ', - 148: 'TCC_PERF_SEL_CLIENT20_REQ', - 149: 'TCC_PERF_SEL_CLIENT21_REQ', - 150: 'TCC_PERF_SEL_CLIENT22_REQ', - 151: 'TCC_PERF_SEL_CLIENT23_REQ', - 152: 'TCC_PERF_SEL_CLIENT24_REQ', - 153: 'TCC_PERF_SEL_CLIENT25_REQ', - 154: 'TCC_PERF_SEL_CLIENT26_REQ', - 155: 'TCC_PERF_SEL_CLIENT27_REQ', - 156: 'TCC_PERF_SEL_CLIENT28_REQ', - 157: 'TCC_PERF_SEL_CLIENT29_REQ', - 158: 'TCC_PERF_SEL_CLIENT30_REQ', - 159: 'TCC_PERF_SEL_CLIENT31_REQ', - 160: 'TCC_PERF_SEL_CLIENT32_REQ', - 161: 'TCC_PERF_SEL_CLIENT33_REQ', - 162: 'TCC_PERF_SEL_CLIENT34_REQ', - 163: 'TCC_PERF_SEL_CLIENT35_REQ', - 164: 'TCC_PERF_SEL_CLIENT36_REQ', - 165: 'TCC_PERF_SEL_CLIENT37_REQ', - 166: 'TCC_PERF_SEL_CLIENT38_REQ', - 167: 'TCC_PERF_SEL_CLIENT39_REQ', - 168: 'TCC_PERF_SEL_CLIENT40_REQ', - 169: 'TCC_PERF_SEL_CLIENT41_REQ', - 170: 'TCC_PERF_SEL_CLIENT42_REQ', - 171: 'TCC_PERF_SEL_CLIENT43_REQ', - 172: 'TCC_PERF_SEL_CLIENT44_REQ', - 173: 'TCC_PERF_SEL_CLIENT45_REQ', - 174: 'TCC_PERF_SEL_CLIENT46_REQ', - 175: 'TCC_PERF_SEL_CLIENT47_REQ', - 176: 'TCC_PERF_SEL_CLIENT48_REQ', - 177: 'TCC_PERF_SEL_CLIENT49_REQ', - 178: 'TCC_PERF_SEL_CLIENT50_REQ', - 179: 'TCC_PERF_SEL_CLIENT51_REQ', - 180: 'TCC_PERF_SEL_CLIENT52_REQ', - 181: 'TCC_PERF_SEL_CLIENT53_REQ', - 182: 'TCC_PERF_SEL_CLIENT54_REQ', - 183: 'TCC_PERF_SEL_CLIENT55_REQ', - 184: 'TCC_PERF_SEL_CLIENT56_REQ', - 185: 'TCC_PERF_SEL_CLIENT57_REQ', - 186: 'TCC_PERF_SEL_CLIENT58_REQ', - 187: 'TCC_PERF_SEL_CLIENT59_REQ', - 188: 'TCC_PERF_SEL_CLIENT60_REQ', - 189: 'TCC_PERF_SEL_CLIENT61_REQ', - 190: 'TCC_PERF_SEL_CLIENT62_REQ', - 191: 'TCC_PERF_SEL_CLIENT63_REQ', - 192: 'TCC_PERF_SEL_CLIENT64_REQ', - 193: 'TCC_PERF_SEL_CLIENT65_REQ', - 194: 'TCC_PERF_SEL_CLIENT66_REQ', - 195: 'TCC_PERF_SEL_CLIENT67_REQ', - 196: 'TCC_PERF_SEL_CLIENT68_REQ', - 197: 'TCC_PERF_SEL_CLIENT69_REQ', - 198: 'TCC_PERF_SEL_CLIENT70_REQ', - 199: 'TCC_PERF_SEL_CLIENT71_REQ', - 200: 'TCC_PERF_SEL_CLIENT72_REQ', - 201: 'TCC_PERF_SEL_CLIENT73_REQ', - 202: 'TCC_PERF_SEL_CLIENT74_REQ', - 203: 'TCC_PERF_SEL_CLIENT75_REQ', - 204: 'TCC_PERF_SEL_CLIENT76_REQ', - 205: 'TCC_PERF_SEL_CLIENT77_REQ', - 206: 'TCC_PERF_SEL_CLIENT78_REQ', - 207: 'TCC_PERF_SEL_CLIENT79_REQ', - 208: 'TCC_PERF_SEL_CLIENT80_REQ', - 209: 'TCC_PERF_SEL_CLIENT81_REQ', - 210: 'TCC_PERF_SEL_CLIENT82_REQ', - 211: 'TCC_PERF_SEL_CLIENT83_REQ', - 212: 'TCC_PERF_SEL_CLIENT84_REQ', - 213: 'TCC_PERF_SEL_CLIENT85_REQ', - 214: 'TCC_PERF_SEL_CLIENT86_REQ', - 215: 'TCC_PERF_SEL_CLIENT87_REQ', - 216: 'TCC_PERF_SEL_CLIENT88_REQ', - 217: 'TCC_PERF_SEL_CLIENT89_REQ', - 218: 'TCC_PERF_SEL_CLIENT90_REQ', - 219: 'TCC_PERF_SEL_CLIENT91_REQ', - 220: 'TCC_PERF_SEL_CLIENT92_REQ', - 221: 'TCC_PERF_SEL_CLIENT93_REQ', - 222: 'TCC_PERF_SEL_CLIENT94_REQ', - 223: 'TCC_PERF_SEL_CLIENT95_REQ', - 224: 'TCC_PERF_SEL_CLIENT96_REQ', - 225: 'TCC_PERF_SEL_CLIENT97_REQ', - 226: 'TCC_PERF_SEL_CLIENT98_REQ', - 227: 'TCC_PERF_SEL_CLIENT99_REQ', - 228: 'TCC_PERF_SEL_CLIENT100_REQ', - 229: 'TCC_PERF_SEL_CLIENT101_REQ', - 230: 'TCC_PERF_SEL_CLIENT102_REQ', - 231: 'TCC_PERF_SEL_CLIENT103_REQ', - 232: 'TCC_PERF_SEL_CLIENT104_REQ', - 233: 'TCC_PERF_SEL_CLIENT105_REQ', - 234: 'TCC_PERF_SEL_CLIENT106_REQ', - 235: 'TCC_PERF_SEL_CLIENT107_REQ', - 236: 'TCC_PERF_SEL_CLIENT108_REQ', - 237: 'TCC_PERF_SEL_CLIENT109_REQ', - 238: 'TCC_PERF_SEL_CLIENT110_REQ', - 239: 'TCC_PERF_SEL_CLIENT111_REQ', - 240: 'TCC_PERF_SEL_CLIENT112_REQ', - 241: 'TCC_PERF_SEL_CLIENT113_REQ', - 242: 'TCC_PERF_SEL_CLIENT114_REQ', - 243: 'TCC_PERF_SEL_CLIENT115_REQ', - 244: 'TCC_PERF_SEL_CLIENT116_REQ', - 245: 'TCC_PERF_SEL_CLIENT117_REQ', - 246: 'TCC_PERF_SEL_CLIENT118_REQ', - 247: 'TCC_PERF_SEL_CLIENT119_REQ', - 248: 'TCC_PERF_SEL_CLIENT120_REQ', - 249: 'TCC_PERF_SEL_CLIENT121_REQ', - 250: 'TCC_PERF_SEL_CLIENT122_REQ', - 251: 'TCC_PERF_SEL_CLIENT123_REQ', - 252: 'TCC_PERF_SEL_CLIENT124_REQ', - 253: 'TCC_PERF_SEL_CLIENT125_REQ', - 254: 'TCC_PERF_SEL_CLIENT126_REQ', - 255: 'TCC_PERF_SEL_CLIENT127_REQ', -} -TCC_PERF_SEL_NONE = 0 -TCC_PERF_SEL_CYCLE = 1 -TCC_PERF_SEL_BUSY = 2 -TCC_PERF_SEL_REQ = 3 -TCC_PERF_SEL_STREAMING_REQ = 4 -TCC_PERF_SEL_EXE_REQ = 5 -TCC_PERF_SEL_COMPRESSED_REQ = 6 -TCC_PERF_SEL_COMPRESSED_0_REQ = 7 -TCC_PERF_SEL_METADATA_REQ = 8 -TCC_PERF_SEL_NC_VIRTUAL_REQ = 9 -TCC_PERF_SEL_UC_VIRTUAL_REQ = 10 -TCC_PERF_SEL_CC_PHYSICAL_REQ = 11 -TCC_PERF_SEL_PROBE = 12 -TCC_PERF_SEL_PROBE_ALL = 13 -TCC_PERF_SEL_READ = 14 -TCC_PERF_SEL_WRITE = 15 -TCC_PERF_SEL_ATOMIC = 16 -TCC_PERF_SEL_HIT = 17 -TCC_PERF_SEL_SECTOR_HIT = 18 -TCC_PERF_SEL_MISS = 19 -TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 20 -TCC_PERF_SEL_FULLY_WRITTEN_HIT = 21 -TCC_PERF_SEL_WRITEBACK = 22 -TCC_PERF_SEL_LATENCY_FIFO_FULL = 23 -TCC_PERF_SEL_SRC_FIFO_FULL = 24 -TCC_PERF_SEL_HOLE_FIFO_FULL = 25 -TCC_PERF_SEL_EA_WRREQ = 26 -TCC_PERF_SEL_EA_WRREQ_64B = 27 -TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 28 -TCC_PERF_SEL_EA_WR_UNCACHED_32B = 29 -TCC_PERF_SEL_EA_WRREQ_STALL = 30 -TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 31 -TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 32 -TCC_PERF_SEL_EA_WRREQ_LEVEL = 33 -TCC_PERF_SEL_EA_ATOMIC = 34 -TCC_PERF_SEL_EA_ATOMIC_LEVEL = 35 -TCC_PERF_SEL_EA_RDREQ = 36 -TCC_PERF_SEL_EA_RDREQ_32B = 37 -TCC_PERF_SEL_EA_RD_UNCACHED_32B = 38 -TCC_PERF_SEL_EA_RD_MDC_32B = 39 -TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 40 -TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 41 -TCC_PERF_SEL_EA_RDREQ_LEVEL = 42 -TCC_PERF_SEL_TAG_STALL = 43 -TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 44 -TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 45 -TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 46 -TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 47 -TCC_PERF_SEL_TAG_PROBE_STALL = 48 -TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 49 -TCC_PERF_SEL_READ_RETURN_TIMEOUT = 50 -TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 51 -TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 52 -TCC_PERF_SEL_BUBBLE = 53 -TCC_PERF_SEL_RETURN_ACK = 54 -TCC_PERF_SEL_RETURN_DATA = 55 -TCC_PERF_SEL_RETURN_HOLE = 56 -TCC_PERF_SEL_RETURN_ACK_HOLE = 57 -TCC_PERF_SEL_IB_REQ = 58 -TCC_PERF_SEL_IB_STALL = 59 -TCC_PERF_SEL_IB_TAG_STALL = 60 -TCC_PERF_SEL_IB_MDC_STALL = 61 -TCC_PERF_SEL_TCA_LEVEL = 62 -TCC_PERF_SEL_HOLE_LEVEL = 63 -TCC_PERF_SEL_NORMAL_WRITEBACK = 64 -TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 65 -TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 66 -TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 67 -TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 68 -TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 69 -TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 70 -TCC_PERF_SEL_NORMAL_EVICT = 71 -TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 72 -TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 73 -TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 74 -TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 75 -TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 76 -TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 77 -TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 78 -TCC_PERF_SEL_PROBE_EVICT = 79 -TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 80 -TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 81 -TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 82 -TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 83 -TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 84 -TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 85 -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 86 -TCC_PERF_SEL_TC_OP_WBL2_NC_START = 87 -TCC_PERF_SEL_TC_OP_WBL2_WC_START = 88 -TCC_PERF_SEL_TC_OP_INVL2_NC_START = 89 -TCC_PERF_SEL_TC_OP_WBINVL2_START = 90 -TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 91 -TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 92 -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 93 -TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 94 -TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 95 -TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 96 -TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 97 -TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 98 -TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 99 -TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 100 -TCC_PERF_SEL_MDC_REQ = 101 -TCC_PERF_SEL_MDC_LEVEL = 102 -TCC_PERF_SEL_MDC_TAG_HIT = 103 -TCC_PERF_SEL_MDC_SECTOR_HIT = 104 -TCC_PERF_SEL_MDC_SECTOR_MISS = 105 -TCC_PERF_SEL_MDC_TAG_STALL = 106 -TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 107 -TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 108 -TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 109 -TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 110 -TCC_PERF_SEL_PROBE_FILTER_DISABLED = 111 -TCC_PERF_SEL_CLIENT0_REQ = 128 -TCC_PERF_SEL_CLIENT1_REQ = 129 -TCC_PERF_SEL_CLIENT2_REQ = 130 -TCC_PERF_SEL_CLIENT3_REQ = 131 -TCC_PERF_SEL_CLIENT4_REQ = 132 -TCC_PERF_SEL_CLIENT5_REQ = 133 -TCC_PERF_SEL_CLIENT6_REQ = 134 -TCC_PERF_SEL_CLIENT7_REQ = 135 -TCC_PERF_SEL_CLIENT8_REQ = 136 -TCC_PERF_SEL_CLIENT9_REQ = 137 -TCC_PERF_SEL_CLIENT10_REQ = 138 -TCC_PERF_SEL_CLIENT11_REQ = 139 -TCC_PERF_SEL_CLIENT12_REQ = 140 -TCC_PERF_SEL_CLIENT13_REQ = 141 -TCC_PERF_SEL_CLIENT14_REQ = 142 -TCC_PERF_SEL_CLIENT15_REQ = 143 -TCC_PERF_SEL_CLIENT16_REQ = 144 -TCC_PERF_SEL_CLIENT17_REQ = 145 -TCC_PERF_SEL_CLIENT18_REQ = 146 -TCC_PERF_SEL_CLIENT19_REQ = 147 -TCC_PERF_SEL_CLIENT20_REQ = 148 -TCC_PERF_SEL_CLIENT21_REQ = 149 -TCC_PERF_SEL_CLIENT22_REQ = 150 -TCC_PERF_SEL_CLIENT23_REQ = 151 -TCC_PERF_SEL_CLIENT24_REQ = 152 -TCC_PERF_SEL_CLIENT25_REQ = 153 -TCC_PERF_SEL_CLIENT26_REQ = 154 -TCC_PERF_SEL_CLIENT27_REQ = 155 -TCC_PERF_SEL_CLIENT28_REQ = 156 -TCC_PERF_SEL_CLIENT29_REQ = 157 -TCC_PERF_SEL_CLIENT30_REQ = 158 -TCC_PERF_SEL_CLIENT31_REQ = 159 -TCC_PERF_SEL_CLIENT32_REQ = 160 -TCC_PERF_SEL_CLIENT33_REQ = 161 -TCC_PERF_SEL_CLIENT34_REQ = 162 -TCC_PERF_SEL_CLIENT35_REQ = 163 -TCC_PERF_SEL_CLIENT36_REQ = 164 -TCC_PERF_SEL_CLIENT37_REQ = 165 -TCC_PERF_SEL_CLIENT38_REQ = 166 -TCC_PERF_SEL_CLIENT39_REQ = 167 -TCC_PERF_SEL_CLIENT40_REQ = 168 -TCC_PERF_SEL_CLIENT41_REQ = 169 -TCC_PERF_SEL_CLIENT42_REQ = 170 -TCC_PERF_SEL_CLIENT43_REQ = 171 -TCC_PERF_SEL_CLIENT44_REQ = 172 -TCC_PERF_SEL_CLIENT45_REQ = 173 -TCC_PERF_SEL_CLIENT46_REQ = 174 -TCC_PERF_SEL_CLIENT47_REQ = 175 -TCC_PERF_SEL_CLIENT48_REQ = 176 -TCC_PERF_SEL_CLIENT49_REQ = 177 -TCC_PERF_SEL_CLIENT50_REQ = 178 -TCC_PERF_SEL_CLIENT51_REQ = 179 -TCC_PERF_SEL_CLIENT52_REQ = 180 -TCC_PERF_SEL_CLIENT53_REQ = 181 -TCC_PERF_SEL_CLIENT54_REQ = 182 -TCC_PERF_SEL_CLIENT55_REQ = 183 -TCC_PERF_SEL_CLIENT56_REQ = 184 -TCC_PERF_SEL_CLIENT57_REQ = 185 -TCC_PERF_SEL_CLIENT58_REQ = 186 -TCC_PERF_SEL_CLIENT59_REQ = 187 -TCC_PERF_SEL_CLIENT60_REQ = 188 -TCC_PERF_SEL_CLIENT61_REQ = 189 -TCC_PERF_SEL_CLIENT62_REQ = 190 -TCC_PERF_SEL_CLIENT63_REQ = 191 -TCC_PERF_SEL_CLIENT64_REQ = 192 -TCC_PERF_SEL_CLIENT65_REQ = 193 -TCC_PERF_SEL_CLIENT66_REQ = 194 -TCC_PERF_SEL_CLIENT67_REQ = 195 -TCC_PERF_SEL_CLIENT68_REQ = 196 -TCC_PERF_SEL_CLIENT69_REQ = 197 -TCC_PERF_SEL_CLIENT70_REQ = 198 -TCC_PERF_SEL_CLIENT71_REQ = 199 -TCC_PERF_SEL_CLIENT72_REQ = 200 -TCC_PERF_SEL_CLIENT73_REQ = 201 -TCC_PERF_SEL_CLIENT74_REQ = 202 -TCC_PERF_SEL_CLIENT75_REQ = 203 -TCC_PERF_SEL_CLIENT76_REQ = 204 -TCC_PERF_SEL_CLIENT77_REQ = 205 -TCC_PERF_SEL_CLIENT78_REQ = 206 -TCC_PERF_SEL_CLIENT79_REQ = 207 -TCC_PERF_SEL_CLIENT80_REQ = 208 -TCC_PERF_SEL_CLIENT81_REQ = 209 -TCC_PERF_SEL_CLIENT82_REQ = 210 -TCC_PERF_SEL_CLIENT83_REQ = 211 -TCC_PERF_SEL_CLIENT84_REQ = 212 -TCC_PERF_SEL_CLIENT85_REQ = 213 -TCC_PERF_SEL_CLIENT86_REQ = 214 -TCC_PERF_SEL_CLIENT87_REQ = 215 -TCC_PERF_SEL_CLIENT88_REQ = 216 -TCC_PERF_SEL_CLIENT89_REQ = 217 -TCC_PERF_SEL_CLIENT90_REQ = 218 -TCC_PERF_SEL_CLIENT91_REQ = 219 -TCC_PERF_SEL_CLIENT92_REQ = 220 -TCC_PERF_SEL_CLIENT93_REQ = 221 -TCC_PERF_SEL_CLIENT94_REQ = 222 -TCC_PERF_SEL_CLIENT95_REQ = 223 -TCC_PERF_SEL_CLIENT96_REQ = 224 -TCC_PERF_SEL_CLIENT97_REQ = 225 -TCC_PERF_SEL_CLIENT98_REQ = 226 -TCC_PERF_SEL_CLIENT99_REQ = 227 -TCC_PERF_SEL_CLIENT100_REQ = 228 -TCC_PERF_SEL_CLIENT101_REQ = 229 -TCC_PERF_SEL_CLIENT102_REQ = 230 -TCC_PERF_SEL_CLIENT103_REQ = 231 -TCC_PERF_SEL_CLIENT104_REQ = 232 -TCC_PERF_SEL_CLIENT105_REQ = 233 -TCC_PERF_SEL_CLIENT106_REQ = 234 -TCC_PERF_SEL_CLIENT107_REQ = 235 -TCC_PERF_SEL_CLIENT108_REQ = 236 -TCC_PERF_SEL_CLIENT109_REQ = 237 -TCC_PERF_SEL_CLIENT110_REQ = 238 -TCC_PERF_SEL_CLIENT111_REQ = 239 -TCC_PERF_SEL_CLIENT112_REQ = 240 -TCC_PERF_SEL_CLIENT113_REQ = 241 -TCC_PERF_SEL_CLIENT114_REQ = 242 -TCC_PERF_SEL_CLIENT115_REQ = 243 -TCC_PERF_SEL_CLIENT116_REQ = 244 -TCC_PERF_SEL_CLIENT117_REQ = 245 -TCC_PERF_SEL_CLIENT118_REQ = 246 -TCC_PERF_SEL_CLIENT119_REQ = 247 -TCC_PERF_SEL_CLIENT120_REQ = 248 -TCC_PERF_SEL_CLIENT121_REQ = 249 -TCC_PERF_SEL_CLIENT122_REQ = 250 -TCC_PERF_SEL_CLIENT123_REQ = 251 -TCC_PERF_SEL_CLIENT124_REQ = 252 -TCC_PERF_SEL_CLIENT125_REQ = 253 -TCC_PERF_SEL_CLIENT126_REQ = 254 -TCC_PERF_SEL_CLIENT127_REQ = 255 -TCC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCA_PERF_SEL' -TCA_PERF_SEL__enumvalues = { - 0: 'TCA_PERF_SEL_NONE', - 1: 'TCA_PERF_SEL_CYCLE', - 2: 'TCA_PERF_SEL_BUSY', - 3: 'TCA_PERF_SEL_FORCED_HOLE_TCC0', - 4: 'TCA_PERF_SEL_FORCED_HOLE_TCC1', - 5: 'TCA_PERF_SEL_FORCED_HOLE_TCC2', - 6: 'TCA_PERF_SEL_FORCED_HOLE_TCC3', - 7: 'TCA_PERF_SEL_FORCED_HOLE_TCC4', - 8: 'TCA_PERF_SEL_FORCED_HOLE_TCC5', - 9: 'TCA_PERF_SEL_FORCED_HOLE_TCC6', - 10: 'TCA_PERF_SEL_FORCED_HOLE_TCC7', - 11: 'TCA_PERF_SEL_REQ_TCC0', - 12: 'TCA_PERF_SEL_REQ_TCC1', - 13: 'TCA_PERF_SEL_REQ_TCC2', - 14: 'TCA_PERF_SEL_REQ_TCC3', - 15: 'TCA_PERF_SEL_REQ_TCC4', - 16: 'TCA_PERF_SEL_REQ_TCC5', - 17: 'TCA_PERF_SEL_REQ_TCC6', - 18: 'TCA_PERF_SEL_REQ_TCC7', - 19: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', - 20: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', - 21: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', - 22: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', - 23: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', - 24: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', - 25: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', - 26: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', - 27: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', - 28: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', - 29: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', - 30: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', - 31: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', - 32: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', - 33: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', - 34: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', -} -TCA_PERF_SEL_NONE = 0 -TCA_PERF_SEL_CYCLE = 1 -TCA_PERF_SEL_BUSY = 2 -TCA_PERF_SEL_FORCED_HOLE_TCC0 = 3 -TCA_PERF_SEL_FORCED_HOLE_TCC1 = 4 -TCA_PERF_SEL_FORCED_HOLE_TCC2 = 5 -TCA_PERF_SEL_FORCED_HOLE_TCC3 = 6 -TCA_PERF_SEL_FORCED_HOLE_TCC4 = 7 -TCA_PERF_SEL_FORCED_HOLE_TCC5 = 8 -TCA_PERF_SEL_FORCED_HOLE_TCC6 = 9 -TCA_PERF_SEL_FORCED_HOLE_TCC7 = 10 -TCA_PERF_SEL_REQ_TCC0 = 11 -TCA_PERF_SEL_REQ_TCC1 = 12 -TCA_PERF_SEL_REQ_TCC2 = 13 -TCA_PERF_SEL_REQ_TCC3 = 14 -TCA_PERF_SEL_REQ_TCC4 = 15 -TCA_PERF_SEL_REQ_TCC5 = 16 -TCA_PERF_SEL_REQ_TCC6 = 17 -TCA_PERF_SEL_REQ_TCC7 = 18 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 19 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 20 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 21 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 22 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 23 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 24 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 25 -TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 26 -TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 27 -TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 28 -TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 29 -TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 30 -TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 31 -TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 32 -TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 33 -TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 34 -TCA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_PERF_SEL' -GRBM_PERF_SEL__enumvalues = { - 0: 'GRBM_PERF_SEL_COUNT', - 1: 'GRBM_PERF_SEL_USER_DEFINED', - 2: 'GRBM_PERF_SEL_GUI_ACTIVE', - 3: 'GRBM_PERF_SEL_CP_BUSY', - 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', - 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', - 6: 'GRBM_PERF_SEL_CB_BUSY', - 7: 'GRBM_PERF_SEL_DB_BUSY', - 8: 'GRBM_PERF_SEL_PA_BUSY', - 9: 'GRBM_PERF_SEL_SC_BUSY', - 10: 'GRBM_PERF_SEL_RESERVED_6', - 11: 'GRBM_PERF_SEL_SPI_BUSY', - 12: 'GRBM_PERF_SEL_SX_BUSY', - 13: 'GRBM_PERF_SEL_TA_BUSY', - 14: 'GRBM_PERF_SEL_CB_CLEAN', - 15: 'GRBM_PERF_SEL_DB_CLEAN', - 16: 'GRBM_PERF_SEL_RESERVED_5', - 17: 'GRBM_PERF_SEL_VGT_BUSY', - 18: 'GRBM_PERF_SEL_RESERVED_4', - 19: 'GRBM_PERF_SEL_RESERVED_3', - 20: 'GRBM_PERF_SEL_RESERVED_2', - 21: 'GRBM_PERF_SEL_RESERVED_1', - 22: 'GRBM_PERF_SEL_RESERVED_0', - 23: 'GRBM_PERF_SEL_IA_BUSY', - 24: 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', - 25: 'GRBM_PERF_SEL_GDS_BUSY', - 26: 'GRBM_PERF_SEL_BCI_BUSY', - 27: 'GRBM_PERF_SEL_RLC_BUSY', - 28: 'GRBM_PERF_SEL_TC_BUSY', - 29: 'GRBM_PERF_SEL_CPG_BUSY', - 30: 'GRBM_PERF_SEL_CPC_BUSY', - 31: 'GRBM_PERF_SEL_CPF_BUSY', - 32: 'GRBM_PERF_SEL_WD_BUSY', - 33: 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', - 34: 'GRBM_PERF_SEL_UTCL2_BUSY', - 35: 'GRBM_PERF_SEL_EA_BUSY', - 36: 'GRBM_PERF_SEL_RMI_BUSY', - 37: 'GRBM_PERF_SEL_CPAXI_BUSY', -} -GRBM_PERF_SEL_COUNT = 0 -GRBM_PERF_SEL_USER_DEFINED = 1 -GRBM_PERF_SEL_GUI_ACTIVE = 2 -GRBM_PERF_SEL_CP_BUSY = 3 -GRBM_PERF_SEL_CP_COHER_BUSY = 4 -GRBM_PERF_SEL_CP_DMA_BUSY = 5 -GRBM_PERF_SEL_CB_BUSY = 6 -GRBM_PERF_SEL_DB_BUSY = 7 -GRBM_PERF_SEL_PA_BUSY = 8 -GRBM_PERF_SEL_SC_BUSY = 9 -GRBM_PERF_SEL_RESERVED_6 = 10 -GRBM_PERF_SEL_SPI_BUSY = 11 -GRBM_PERF_SEL_SX_BUSY = 12 -GRBM_PERF_SEL_TA_BUSY = 13 -GRBM_PERF_SEL_CB_CLEAN = 14 -GRBM_PERF_SEL_DB_CLEAN = 15 -GRBM_PERF_SEL_RESERVED_5 = 16 -GRBM_PERF_SEL_VGT_BUSY = 17 -GRBM_PERF_SEL_RESERVED_4 = 18 -GRBM_PERF_SEL_RESERVED_3 = 19 -GRBM_PERF_SEL_RESERVED_2 = 20 -GRBM_PERF_SEL_RESERVED_1 = 21 -GRBM_PERF_SEL_RESERVED_0 = 22 -GRBM_PERF_SEL_IA_BUSY = 23 -GRBM_PERF_SEL_IA_NO_DMA_BUSY = 24 -GRBM_PERF_SEL_GDS_BUSY = 25 -GRBM_PERF_SEL_BCI_BUSY = 26 -GRBM_PERF_SEL_RLC_BUSY = 27 -GRBM_PERF_SEL_TC_BUSY = 28 -GRBM_PERF_SEL_CPG_BUSY = 29 -GRBM_PERF_SEL_CPC_BUSY = 30 -GRBM_PERF_SEL_CPF_BUSY = 31 -GRBM_PERF_SEL_WD_BUSY = 32 -GRBM_PERF_SEL_WD_NO_DMA_BUSY = 33 -GRBM_PERF_SEL_UTCL2_BUSY = 34 -GRBM_PERF_SEL_EA_BUSY = 35 -GRBM_PERF_SEL_RMI_BUSY = 36 -GRBM_PERF_SEL_CPAXI_BUSY = 37 -GRBM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE0_PERF_SEL' -GRBM_SE0_PERF_SEL__enumvalues = { - 0: 'GRBM_SE0_PERF_SEL_COUNT', - 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE0_PERF_SEL_VGT_BUSY', - 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', -} -GRBM_SE0_PERF_SEL_COUNT = 0 -GRBM_SE0_PERF_SEL_USER_DEFINED = 1 -GRBM_SE0_PERF_SEL_CB_BUSY = 2 -GRBM_SE0_PERF_SEL_DB_BUSY = 3 -GRBM_SE0_PERF_SEL_SC_BUSY = 4 -GRBM_SE0_PERF_SEL_RESERVED_1 = 5 -GRBM_SE0_PERF_SEL_SPI_BUSY = 6 -GRBM_SE0_PERF_SEL_SX_BUSY = 7 -GRBM_SE0_PERF_SEL_TA_BUSY = 8 -GRBM_SE0_PERF_SEL_CB_CLEAN = 9 -GRBM_SE0_PERF_SEL_DB_CLEAN = 10 -GRBM_SE0_PERF_SEL_RESERVED_0 = 11 -GRBM_SE0_PERF_SEL_PA_BUSY = 12 -GRBM_SE0_PERF_SEL_VGT_BUSY = 13 -GRBM_SE0_PERF_SEL_BCI_BUSY = 14 -GRBM_SE0_PERF_SEL_RMI_BUSY = 15 -GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE1_PERF_SEL' -GRBM_SE1_PERF_SEL__enumvalues = { - 0: 'GRBM_SE1_PERF_SEL_COUNT', - 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE1_PERF_SEL_VGT_BUSY', - 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', -} -GRBM_SE1_PERF_SEL_COUNT = 0 -GRBM_SE1_PERF_SEL_USER_DEFINED = 1 -GRBM_SE1_PERF_SEL_CB_BUSY = 2 -GRBM_SE1_PERF_SEL_DB_BUSY = 3 -GRBM_SE1_PERF_SEL_SC_BUSY = 4 -GRBM_SE1_PERF_SEL_RESERVED_1 = 5 -GRBM_SE1_PERF_SEL_SPI_BUSY = 6 -GRBM_SE1_PERF_SEL_SX_BUSY = 7 -GRBM_SE1_PERF_SEL_TA_BUSY = 8 -GRBM_SE1_PERF_SEL_CB_CLEAN = 9 -GRBM_SE1_PERF_SEL_DB_CLEAN = 10 -GRBM_SE1_PERF_SEL_RESERVED_0 = 11 -GRBM_SE1_PERF_SEL_PA_BUSY = 12 -GRBM_SE1_PERF_SEL_VGT_BUSY = 13 -GRBM_SE1_PERF_SEL_BCI_BUSY = 14 -GRBM_SE1_PERF_SEL_RMI_BUSY = 15 -GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE2_PERF_SEL' -GRBM_SE2_PERF_SEL__enumvalues = { - 0: 'GRBM_SE2_PERF_SEL_COUNT', - 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE2_PERF_SEL_VGT_BUSY', - 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', -} -GRBM_SE2_PERF_SEL_COUNT = 0 -GRBM_SE2_PERF_SEL_USER_DEFINED = 1 -GRBM_SE2_PERF_SEL_CB_BUSY = 2 -GRBM_SE2_PERF_SEL_DB_BUSY = 3 -GRBM_SE2_PERF_SEL_SC_BUSY = 4 -GRBM_SE2_PERF_SEL_RESERVED_1 = 5 -GRBM_SE2_PERF_SEL_SPI_BUSY = 6 -GRBM_SE2_PERF_SEL_SX_BUSY = 7 -GRBM_SE2_PERF_SEL_TA_BUSY = 8 -GRBM_SE2_PERF_SEL_CB_CLEAN = 9 -GRBM_SE2_PERF_SEL_DB_CLEAN = 10 -GRBM_SE2_PERF_SEL_RESERVED_0 = 11 -GRBM_SE2_PERF_SEL_PA_BUSY = 12 -GRBM_SE2_PERF_SEL_VGT_BUSY = 13 -GRBM_SE2_PERF_SEL_BCI_BUSY = 14 -GRBM_SE2_PERF_SEL_RMI_BUSY = 15 -GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE3_PERF_SEL' -GRBM_SE3_PERF_SEL__enumvalues = { - 0: 'GRBM_SE3_PERF_SEL_COUNT', - 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', - 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', - 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', - 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', - 13: 'GRBM_SE3_PERF_SEL_VGT_BUSY', - 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', -} -GRBM_SE3_PERF_SEL_COUNT = 0 -GRBM_SE3_PERF_SEL_USER_DEFINED = 1 -GRBM_SE3_PERF_SEL_CB_BUSY = 2 -GRBM_SE3_PERF_SEL_DB_BUSY = 3 -GRBM_SE3_PERF_SEL_SC_BUSY = 4 -GRBM_SE3_PERF_SEL_RESERVED_1 = 5 -GRBM_SE3_PERF_SEL_SPI_BUSY = 6 -GRBM_SE3_PERF_SEL_SX_BUSY = 7 -GRBM_SE3_PERF_SEL_TA_BUSY = 8 -GRBM_SE3_PERF_SEL_CB_CLEAN = 9 -GRBM_SE3_PERF_SEL_DB_CLEAN = 10 -GRBM_SE3_PERF_SEL_RESERVED_0 = 11 -GRBM_SE3_PERF_SEL_PA_BUSY = 12 -GRBM_SE3_PERF_SEL_VGT_BUSY = 13 -GRBM_SE3_PERF_SEL_BCI_BUSY = 14 -GRBM_SE3_PERF_SEL_RMI_BUSY = 15 -GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_RING_ID' -CP_RING_ID__enumvalues = { - 0: 'RINGID0', - 1: 'RINGID1', - 2: 'RINGID2', - 3: 'RINGID3', -} -RINGID0 = 0 -RINGID1 = 1 -RINGID2 = 2 -RINGID3 = 3 -CP_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PIPE_ID' -CP_PIPE_ID__enumvalues = { - 0: 'PIPE_ID0', - 1: 'PIPE_ID1', - 2: 'PIPE_ID2', - 3: 'PIPE_ID3', -} -PIPE_ID0 = 0 -PIPE_ID1 = 1 -PIPE_ID2 = 2 -PIPE_ID3 = 3 -CP_PIPE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ME_ID' -CP_ME_ID__enumvalues = { - 0: 'ME_ID0', - 1: 'ME_ID1', - 2: 'ME_ID2', - 3: 'ME_ID3', -} -ME_ID0 = 0 -ME_ID1 = 1 -ME_ID2 = 2 -ME_ID3 = 3 -CP_ME_ID = ctypes.c_uint32 # enum - -# values for enumeration 'SPM_PERFMON_STATE' -SPM_PERFMON_STATE__enumvalues = { - 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'STRM_PERFMON_STATE_START_COUNTING', - 2: 'STRM_PERFMON_STATE_STOP_COUNTING', - 3: 'STRM_PERFMON_STATE_RESERVED_3', - 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 -STRM_PERFMON_STATE_START_COUNTING = 1 -STRM_PERFMON_STATE_STOP_COUNTING = 2 -STRM_PERFMON_STATE_RESERVED_3 = 3 -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -SPM_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_STATE' -CP_PERFMON_STATE__enumvalues = { - 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'CP_PERFMON_STATE_START_COUNTING', - 2: 'CP_PERFMON_STATE_STOP_COUNTING', - 3: 'CP_PERFMON_STATE_RESERVED_3', - 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -CP_PERFMON_STATE_DISABLE_AND_RESET = 0 -CP_PERFMON_STATE_START_COUNTING = 1 -CP_PERFMON_STATE_STOP_COUNTING = 2 -CP_PERFMON_STATE_RESERVED_3 = 3 -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -CP_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_ENABLE_MODE' -CP_PERFMON_ENABLE_MODE__enumvalues = { - 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', - 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', -} -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 -CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNT_SEL' -CPG_PERFCOUNT_SEL__enumvalues = { - 0: 'CPG_PERF_SEL_ALWAYS_COUNT', - 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', - 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', - 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', - 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', - 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 34: 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', - 35: 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', - 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', - 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', -} -CPG_PERF_SEL_ALWAYS_COUNT = 0 -CPG_PERF_SEL_RBIU_FIFO_FULL = 1 -CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 -CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 -CPG_PERF_SEL_ME_PARSER_BUSY = 5 -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 -CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 -CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 -CPG_PERF_SEL_REGISTER_CLK_VALID = 33 -CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 34 -CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 35 -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 -CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNT_SEL' -CPF_PERFCOUNT_SEL__enumvalues = { - 0: 'CPF_PERF_SEL_ALWAYS_COUNT', - 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', - 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', - 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', - 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', - 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 15: 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', - 16: 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', - 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 19: 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 20: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', -} -CPF_PERF_SEL_ALWAYS_COUNT = 0 -CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 -CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 -CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 -CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 -CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 -CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 15 -CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 16 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 -CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 19 -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 20 -CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_PERFCOUNT_SEL' -CPC_PERFCOUNT_SEL__enumvalues = { - 0: 'CPC_PERF_SEL_ALWAYS_COUNT', - 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', - 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', - 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', - 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', - 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', - 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', - 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', -} -CPC_PERF_SEL_ALWAYS_COUNT = 0 -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 -CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 -CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 9 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 10 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 17 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 18 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 -CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' -CP_ALPHA_TAG_RAM_SEL__enumvalues = { - 0: 'CPG_TAG_RAM', - 1: 'CPC_TAG_RAM', - 2: 'CPF_TAG_RAM', - 3: 'RSV_TAG_RAM', -} -CPG_TAG_RAM = 0 -CPC_TAG_RAM = 1 -CPF_TAG_RAM = 2 -RSV_TAG_RAM = 3 -CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SX_BLEND_OPT' -SX_BLEND_OPT__enumvalues = { - 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', -} -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 -SX_BLEND_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_OPT_COMB_FCN' -SX_OPT_COMB_FCN__enumvalues = { - 0: 'OPT_COMB_NONE', - 1: 'OPT_COMB_ADD', - 2: 'OPT_COMB_SUBTRACT', - 3: 'OPT_COMB_MIN', - 4: 'OPT_COMB_MAX', - 5: 'OPT_COMB_REVSUBTRACT', - 6: 'OPT_COMB_BLEND_DISABLED', - 7: 'OPT_COMB_SAFE_ADD', -} -OPT_COMB_NONE = 0 -OPT_COMB_ADD = 1 -OPT_COMB_SUBTRACT = 2 -OPT_COMB_MIN = 3 -OPT_COMB_MAX = 4 -OPT_COMB_REVSUBTRACT = 5 -OPT_COMB_BLEND_DISABLED = 6 -OPT_COMB_SAFE_ADD = 7 -SX_OPT_COMB_FCN = ctypes.c_uint32 # enum - -# values for enumeration 'SX_DOWNCONVERT_FORMAT' -SX_DOWNCONVERT_FORMAT__enumvalues = { - 0: 'SX_RT_EXPORT_NO_CONVERSION', - 1: 'SX_RT_EXPORT_32_R', - 2: 'SX_RT_EXPORT_32_A', - 3: 'SX_RT_EXPORT_10_11_11', - 4: 'SX_RT_EXPORT_2_10_10_10', - 5: 'SX_RT_EXPORT_8_8_8_8', - 6: 'SX_RT_EXPORT_5_6_5', - 7: 'SX_RT_EXPORT_1_5_5_5', - 8: 'SX_RT_EXPORT_4_4_4_4', - 9: 'SX_RT_EXPORT_16_16_GR', - 10: 'SX_RT_EXPORT_16_16_AR', -} -SX_RT_EXPORT_NO_CONVERSION = 0 -SX_RT_EXPORT_32_R = 1 -SX_RT_EXPORT_32_A = 2 -SX_RT_EXPORT_10_11_11 = 3 -SX_RT_EXPORT_2_10_10_10 = 4 -SX_RT_EXPORT_8_8_8_8 = 5 -SX_RT_EXPORT_5_6_5 = 6 -SX_RT_EXPORT_1_5_5_5 = 7 -SX_RT_EXPORT_4_4_4_4 = 8 -SX_RT_EXPORT_16_16_GR = 9 -SX_RT_EXPORT_16_16_AR = 10 -SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_PERFCOUNTER_VALS' -SX_PERFCOUNTER_VALS__enumvalues = { - 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', - 1: 'SX_PERF_SEL_PA_REQ', - 2: 'SX_PERF_SEL_PA_POS', - 3: 'SX_PERF_SEL_CLOCK', - 4: 'SX_PERF_SEL_GATE_EN1', - 5: 'SX_PERF_SEL_GATE_EN2', - 6: 'SX_PERF_SEL_GATE_EN3', - 7: 'SX_PERF_SEL_GATE_EN4', - 8: 'SX_PERF_SEL_SH_POS_STARVE', - 9: 'SX_PERF_SEL_SH_COLOR_STARVE', - 10: 'SX_PERF_SEL_SH_POS_STALL', - 11: 'SX_PERF_SEL_SH_COLOR_STALL', - 12: 'SX_PERF_SEL_DB0_PIXELS', - 13: 'SX_PERF_SEL_DB0_HALF_QUADS', - 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', - 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', - 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', - 17: 'SX_PERF_SEL_DB1_PIXELS', - 18: 'SX_PERF_SEL_DB1_HALF_QUADS', - 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', - 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', - 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', - 22: 'SX_PERF_SEL_DB2_PIXELS', - 23: 'SX_PERF_SEL_DB2_HALF_QUADS', - 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', - 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', - 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', - 27: 'SX_PERF_SEL_DB3_PIXELS', - 28: 'SX_PERF_SEL_DB3_HALF_QUADS', - 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', - 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', - 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', - 32: 'SX_PERF_SEL_COL_BUSY', - 33: 'SX_PERF_SEL_POS_BUSY', - 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', - 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', - 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', - 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', - 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', - 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', - 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', - 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', - 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', - 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', - 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', - 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', - 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', - 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', - 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', - 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', - 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', - 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', - 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', - 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', - 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', - 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', - 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', - 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', - 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', - 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', - 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', - 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', - 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', - 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', - 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', - 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', - 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', - 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', - 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', - 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', - 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', - 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', - 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', - 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', - 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', - 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', - 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', - 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', - 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', - 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', - 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', - 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', - 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', - 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', - 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', - 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', - 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', - 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', - 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', - 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', - 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', - 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', - 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', - 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', - 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', - 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', - 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', - 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', - 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', - 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', - 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', - 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', - 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', - 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', - 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', - 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', - 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', - 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', - 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', - 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', - 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', - 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', - 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', - 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', - 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', - 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', - 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', - 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', - 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', - 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', - 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', - 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', - 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', - 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', - 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', - 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', - 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', - 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', - 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', - 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', - 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', - 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', - 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', - 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', - 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', - 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', - 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', - 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', - 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', - 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', - 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', - 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', - 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', - 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', - 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', - 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', - 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', - 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', - 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', - 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', - 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', - 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', - 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', - 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', - 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', - 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', - 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', - 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', - 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', - 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', - 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', - 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', - 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', - 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', - 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', - 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', - 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', - 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', - 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', - 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', - 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', - 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', - 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', - 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', - 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', - 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', - 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', - 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', - 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', - 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', - 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', - 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', - 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', - 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', - 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', - 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', - 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', - 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', - 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', - 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', - 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', - 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', - 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', - 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', - 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', - 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', - 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', - 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', -} -SX_PERF_SEL_PA_IDLE_CYCLES = 0 -SX_PERF_SEL_PA_REQ = 1 -SX_PERF_SEL_PA_POS = 2 -SX_PERF_SEL_CLOCK = 3 -SX_PERF_SEL_GATE_EN1 = 4 -SX_PERF_SEL_GATE_EN2 = 5 -SX_PERF_SEL_GATE_EN3 = 6 -SX_PERF_SEL_GATE_EN4 = 7 -SX_PERF_SEL_SH_POS_STARVE = 8 -SX_PERF_SEL_SH_COLOR_STARVE = 9 -SX_PERF_SEL_SH_POS_STALL = 10 -SX_PERF_SEL_SH_COLOR_STALL = 11 -SX_PERF_SEL_DB0_PIXELS = 12 -SX_PERF_SEL_DB0_HALF_QUADS = 13 -SX_PERF_SEL_DB0_PIXEL_STALL = 14 -SX_PERF_SEL_DB0_PIXEL_IDLE = 15 -SX_PERF_SEL_DB0_PRED_PIXELS = 16 -SX_PERF_SEL_DB1_PIXELS = 17 -SX_PERF_SEL_DB1_HALF_QUADS = 18 -SX_PERF_SEL_DB1_PIXEL_STALL = 19 -SX_PERF_SEL_DB1_PIXEL_IDLE = 20 -SX_PERF_SEL_DB1_PRED_PIXELS = 21 -SX_PERF_SEL_DB2_PIXELS = 22 -SX_PERF_SEL_DB2_HALF_QUADS = 23 -SX_PERF_SEL_DB2_PIXEL_STALL = 24 -SX_PERF_SEL_DB2_PIXEL_IDLE = 25 -SX_PERF_SEL_DB2_PRED_PIXELS = 26 -SX_PERF_SEL_DB3_PIXELS = 27 -SX_PERF_SEL_DB3_HALF_QUADS = 28 -SX_PERF_SEL_DB3_PIXEL_STALL = 29 -SX_PERF_SEL_DB3_PIXEL_IDLE = 30 -SX_PERF_SEL_DB3_PRED_PIXELS = 31 -SX_PERF_SEL_COL_BUSY = 32 -SX_PERF_SEL_POS_BUSY = 33 -SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 -SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 -SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 -SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 -SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 -SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 -SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 -SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 -SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 -SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 -SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 -SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 -SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 -SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 -SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 -SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 -SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 -SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 -SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 -SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 -SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 -SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 -SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 -SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 -SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 -SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 -SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 -SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 -SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 -SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 -SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 -SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 -SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 -SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 -SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 -SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 -SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 -SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 -SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 -SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 -SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 -SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 -SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 -SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 -SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 -SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 -SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 -SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 -SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 -SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 -SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 -SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 -SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 -SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 -SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 -SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 -SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 -SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 -SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 -SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 -SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 -SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 -SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 -SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 -SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 -SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 -SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 -SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 -SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 -SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 -SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 -SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 -SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 -SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 -SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 -SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 -SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 -SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 -SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 -SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 -SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 -SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 -SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 -SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 -SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 -SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 -SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 -SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 -SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 -SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 -SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 -SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 -SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 -SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 -SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 -SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 -SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 -SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 -SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 -SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 -SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 -SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 -SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 -SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 -SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 -SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 -SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 -SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 -SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 -SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 -SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 -SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 -SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 -SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 -SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 -SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 -SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 -SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 -SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 -SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 -SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 -SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 -SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 -SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 -SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 -SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 -SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 -SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 -SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 -SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 -SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 -SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 -SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 -SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 -SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 -SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 -SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 -SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 -SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 -SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 -SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 -SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 -SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 -SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 -SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 -SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 -SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 -SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 -SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 -SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 -SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 -SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 -SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 -SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 -SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 -SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 -SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 -SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 -SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 -SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 -SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 -SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 -SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 -SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 -SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum - -# values for enumeration 'ForceControl' -ForceControl__enumvalues = { - 0: 'FORCE_OFF', - 1: 'FORCE_ENABLE', - 2: 'FORCE_DISABLE', - 3: 'FORCE_RESERVED', -} -FORCE_OFF = 0 -FORCE_ENABLE = 1 -FORCE_DISABLE = 2 -FORCE_RESERVED = 3 -ForceControl = ctypes.c_uint32 # enum - -# values for enumeration 'ZSamplePosition' -ZSamplePosition__enumvalues = { - 0: 'Z_SAMPLE_CENTER', - 1: 'Z_SAMPLE_CENTROID', -} -Z_SAMPLE_CENTER = 0 -Z_SAMPLE_CENTROID = 1 -ZSamplePosition = ctypes.c_uint32 # enum - -# values for enumeration 'ZOrder' -ZOrder__enumvalues = { - 0: 'LATE_Z', - 1: 'EARLY_Z_THEN_LATE_Z', - 2: 'RE_Z', - 3: 'EARLY_Z_THEN_RE_Z', -} -LATE_Z = 0 -EARLY_Z_THEN_LATE_Z = 1 -RE_Z = 2 -EARLY_Z_THEN_RE_Z = 3 -ZOrder = ctypes.c_uint32 # enum - -# values for enumeration 'ZpassControl' -ZpassControl__enumvalues = { - 0: 'ZPASS_DISABLE', - 1: 'ZPASS_SAMPLES', - 2: 'ZPASS_PIXELS', -} -ZPASS_DISABLE = 0 -ZPASS_SAMPLES = 1 -ZPASS_PIXELS = 2 -ZpassControl = ctypes.c_uint32 # enum - -# values for enumeration 'ZModeForce' -ZModeForce__enumvalues = { - 0: 'NO_FORCE', - 1: 'FORCE_EARLY_Z', - 2: 'FORCE_LATE_Z', - 3: 'FORCE_RE_Z', -} -NO_FORCE = 0 -FORCE_EARLY_Z = 1 -FORCE_LATE_Z = 2 -FORCE_RE_Z = 3 -ZModeForce = ctypes.c_uint32 # enum - -# values for enumeration 'ZLimitSumm' -ZLimitSumm__enumvalues = { - 0: 'FORCE_SUMM_OFF', - 1: 'FORCE_SUMM_MINZ', - 2: 'FORCE_SUMM_MAXZ', - 3: 'FORCE_SUMM_BOTH', -} -FORCE_SUMM_OFF = 0 -FORCE_SUMM_MINZ = 1 -FORCE_SUMM_MAXZ = 2 -FORCE_SUMM_BOTH = 3 -ZLimitSumm = ctypes.c_uint32 # enum - -# values for enumeration 'CompareFrag' -CompareFrag__enumvalues = { - 0: 'FRAG_NEVER', - 1: 'FRAG_LESS', - 2: 'FRAG_EQUAL', - 3: 'FRAG_LEQUAL', - 4: 'FRAG_GREATER', - 5: 'FRAG_NOTEQUAL', - 6: 'FRAG_GEQUAL', - 7: 'FRAG_ALWAYS', -} -FRAG_NEVER = 0 -FRAG_LESS = 1 -FRAG_EQUAL = 2 -FRAG_LEQUAL = 3 -FRAG_GREATER = 4 -FRAG_NOTEQUAL = 5 -FRAG_GEQUAL = 6 -FRAG_ALWAYS = 7 -CompareFrag = ctypes.c_uint32 # enum - -# values for enumeration 'StencilOp' -StencilOp__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_ONES', - 3: 'STENCIL_REPLACE_TEST', - 4: 'STENCIL_REPLACE_OP', - 5: 'STENCIL_ADD_CLAMP', - 6: 'STENCIL_SUB_CLAMP', - 7: 'STENCIL_INVERT', - 8: 'STENCIL_ADD_WRAP', - 9: 'STENCIL_SUB_WRAP', - 10: 'STENCIL_AND', - 11: 'STENCIL_OR', - 12: 'STENCIL_XOR', - 13: 'STENCIL_NAND', - 14: 'STENCIL_NOR', - 15: 'STENCIL_XNOR', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_ONES = 2 -STENCIL_REPLACE_TEST = 3 -STENCIL_REPLACE_OP = 4 -STENCIL_ADD_CLAMP = 5 -STENCIL_SUB_CLAMP = 6 -STENCIL_INVERT = 7 -STENCIL_ADD_WRAP = 8 -STENCIL_SUB_WRAP = 9 -STENCIL_AND = 10 -STENCIL_OR = 11 -STENCIL_XOR = 12 -STENCIL_NAND = 13 -STENCIL_NOR = 14 -STENCIL_XNOR = 15 -StencilOp = ctypes.c_uint32 # enum - -# values for enumeration 'ConservativeZExport' -ConservativeZExport__enumvalues = { - 0: 'EXPORT_ANY_Z', - 1: 'EXPORT_LESS_THAN_Z', - 2: 'EXPORT_GREATER_THAN_Z', - 3: 'EXPORT_RESERVED', -} -EXPORT_ANY_Z = 0 -EXPORT_LESS_THAN_Z = 1 -EXPORT_GREATER_THAN_Z = 2 -EXPORT_RESERVED = 3 -ConservativeZExport = ctypes.c_uint32 # enum - -# values for enumeration 'DbPSLControl' -DbPSLControl__enumvalues = { - 0: 'PSLC_AUTO', - 1: 'PSLC_ON_HANG_ONLY', - 2: 'PSLC_ASAP', - 3: 'PSLC_COUNTDOWN', -} -PSLC_AUTO = 0 -PSLC_ON_HANG_ONLY = 1 -PSLC_ASAP = 2 -PSLC_COUNTDOWN = 3 -DbPSLControl = ctypes.c_uint32 # enum - -# values for enumeration 'DbPRTFaultBehavior' -DbPRTFaultBehavior__enumvalues = { - 0: 'FAULT_ZERO', - 1: 'FAULT_ONE', - 2: 'FAULT_FAIL', - 3: 'FAULT_PASS', -} -FAULT_ZERO = 0 -FAULT_ONE = 1 -FAULT_FAIL = 2 -FAULT_PASS = 3 -DbPRTFaultBehavior = ctypes.c_uint32 # enum - -# values for enumeration 'PerfCounter_Vals' -PerfCounter_Vals__enumvalues = { - 0: 'DB_PERF_SEL_SC_DB_tile_sends', - 1: 'DB_PERF_SEL_SC_DB_tile_busy', - 2: 'DB_PERF_SEL_SC_DB_tile_stalls', - 3: 'DB_PERF_SEL_SC_DB_tile_events', - 4: 'DB_PERF_SEL_SC_DB_tile_tiles', - 5: 'DB_PERF_SEL_SC_DB_tile_covered', - 6: 'DB_PERF_SEL_hiz_tc_read_starved', - 7: 'DB_PERF_SEL_hiz_tc_write_stall', - 8: 'DB_PERF_SEL_hiz_qtiles_culled', - 9: 'DB_PERF_SEL_his_qtiles_culled', - 10: 'DB_PERF_SEL_DB_SC_tile_sends', - 11: 'DB_PERF_SEL_DB_SC_tile_busy', - 12: 'DB_PERF_SEL_DB_SC_tile_stalls', - 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 14: 'DB_PERF_SEL_DB_SC_tile_tiles', - 15: 'DB_PERF_SEL_DB_SC_tile_culled', - 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', - 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 23: 'DB_PERF_SEL_SC_DB_quad_sends', - 24: 'DB_PERF_SEL_SC_DB_quad_busy', - 25: 'DB_PERF_SEL_SC_DB_quad_squads', - 26: 'DB_PERF_SEL_SC_DB_quad_tiles', - 27: 'DB_PERF_SEL_SC_DB_quad_pixels', - 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 29: 'DB_PERF_SEL_DB_SC_quad_sends', - 30: 'DB_PERF_SEL_DB_SC_quad_busy', - 31: 'DB_PERF_SEL_DB_SC_quad_stalls', - 32: 'DB_PERF_SEL_DB_SC_quad_tiles', - 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 34: 'DB_PERF_SEL_DB_CB_tile_sends', - 35: 'DB_PERF_SEL_DB_CB_tile_busy', - 36: 'DB_PERF_SEL_DB_CB_tile_stalls', - 37: 'DB_PERF_SEL_SX_DB_quad_sends', - 38: 'DB_PERF_SEL_SX_DB_quad_busy', - 39: 'DB_PERF_SEL_SX_DB_quad_stalls', - 40: 'DB_PERF_SEL_SX_DB_quad_quads', - 41: 'DB_PERF_SEL_SX_DB_quad_pixels', - 42: 'DB_PERF_SEL_SX_DB_quad_exports', - 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', - 44: 'DB_PERF_SEL_DB_CB_lquad_sends', - 45: 'DB_PERF_SEL_DB_CB_lquad_busy', - 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', - 47: 'DB_PERF_SEL_DB_CB_lquad_quads', - 48: 'DB_PERF_SEL_tile_rd_sends', - 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 50: 'DB_PERF_SEL_quad_rd_sends', - 51: 'DB_PERF_SEL_quad_rd_busy', - 52: 'DB_PERF_SEL_quad_rd_mi_stall', - 53: 'DB_PERF_SEL_quad_rd_rw_collision', - 54: 'DB_PERF_SEL_quad_rd_tag_stall', - 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', - 56: 'DB_PERF_SEL_quad_rd_panic', - 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 58: 'DB_PERF_SEL_quad_rdret_sends', - 59: 'DB_PERF_SEL_quad_rdret_busy', - 60: 'DB_PERF_SEL_tile_wr_sends', - 61: 'DB_PERF_SEL_tile_wr_acks', - 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 63: 'DB_PERF_SEL_quad_wr_sends', - 64: 'DB_PERF_SEL_quad_wr_busy', - 65: 'DB_PERF_SEL_quad_wr_mi_stall', - 66: 'DB_PERF_SEL_quad_wr_coherency_stall', - 67: 'DB_PERF_SEL_quad_wr_acks', - 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 69: 'DB_PERF_SEL_Tile_Cache_misses', - 70: 'DB_PERF_SEL_Tile_Cache_hits', - 71: 'DB_PERF_SEL_Tile_Cache_flushes', - 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', - 73: 'DB_PERF_SEL_Tile_Cache_starves', - 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 75: 'DB_PERF_SEL_tcp_dispatcher_reads', - 76: 'DB_PERF_SEL_tcp_prefetcher_reads', - 77: 'DB_PERF_SEL_tcp_preloader_reads', - 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', - 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', - 80: 'DB_PERF_SEL_tcp_preloader_flushes', - 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', - 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 95: 'DB_PERF_SEL_Stencil_Cache_misses', - 96: 'DB_PERF_SEL_Stencil_Cache_hits', - 97: 'DB_PERF_SEL_Stencil_Cache_flushes', - 98: 'DB_PERF_SEL_Stencil_Cache_starves', - 99: 'DB_PERF_SEL_Stencil_Cache_frees', - 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', - 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', - 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', - 108: 'DB_PERF_SEL_Z_Cache_frees', - 109: 'DB_PERF_SEL_Plane_Cache_misses', - 110: 'DB_PERF_SEL_Plane_Cache_hits', - 111: 'DB_PERF_SEL_Plane_Cache_flushes', - 112: 'DB_PERF_SEL_Plane_Cache_starves', - 113: 'DB_PERF_SEL_Plane_Cache_frees', - 114: 'DB_PERF_SEL_flush_expanded_stencil', - 115: 'DB_PERF_SEL_flush_compressed_stencil', - 116: 'DB_PERF_SEL_flush_single_stencil', - 117: 'DB_PERF_SEL_planes_flushed', - 118: 'DB_PERF_SEL_flush_1plane', - 119: 'DB_PERF_SEL_flush_2plane', - 120: 'DB_PERF_SEL_flush_3plane', - 121: 'DB_PERF_SEL_flush_4plane', - 122: 'DB_PERF_SEL_flush_5plane', - 123: 'DB_PERF_SEL_flush_6plane', - 124: 'DB_PERF_SEL_flush_7plane', - 125: 'DB_PERF_SEL_flush_8plane', - 126: 'DB_PERF_SEL_flush_9plane', - 127: 'DB_PERF_SEL_flush_10plane', - 128: 'DB_PERF_SEL_flush_11plane', - 129: 'DB_PERF_SEL_flush_12plane', - 130: 'DB_PERF_SEL_flush_13plane', - 131: 'DB_PERF_SEL_flush_14plane', - 132: 'DB_PERF_SEL_flush_15plane', - 133: 'DB_PERF_SEL_flush_16plane', - 134: 'DB_PERF_SEL_flush_expanded_z', - 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 137: 'DB_PERF_SEL_dk_tile_sends', - 138: 'DB_PERF_SEL_dk_tile_busy', - 139: 'DB_PERF_SEL_dk_tile_quad_starves', - 140: 'DB_PERF_SEL_dk_tile_stalls', - 141: 'DB_PERF_SEL_dk_squad_sends', - 142: 'DB_PERF_SEL_dk_squad_busy', - 143: 'DB_PERF_SEL_dk_squad_stalls', - 144: 'DB_PERF_SEL_Op_Pipe_Busy', - 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 146: 'DB_PERF_SEL_qc_busy', - 147: 'DB_PERF_SEL_qc_xfc', - 148: 'DB_PERF_SEL_qc_conflicts', - 149: 'DB_PERF_SEL_qc_full_stall', - 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', - 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', - 153: 'DB_PERF_SEL_tl_busy', - 154: 'DB_PERF_SEL_tl_dtc_read_starved', - 155: 'DB_PERF_SEL_tl_z_fetch_stall', - 156: 'DB_PERF_SEL_tl_stencil_stall', - 157: 'DB_PERF_SEL_tl_z_decompress_stall', - 158: 'DB_PERF_SEL_tl_stencil_locked_stall', - 159: 'DB_PERF_SEL_tl_events', - 160: 'DB_PERF_SEL_tl_summarize_squads', - 161: 'DB_PERF_SEL_tl_flush_expand_squads', - 162: 'DB_PERF_SEL_tl_expand_squads', - 163: 'DB_PERF_SEL_tl_preZ_squads', - 164: 'DB_PERF_SEL_tl_postZ_squads', - 165: 'DB_PERF_SEL_tl_preZ_noop_squads', - 166: 'DB_PERF_SEL_tl_postZ_noop_squads', - 167: 'DB_PERF_SEL_tl_tile_ops', - 168: 'DB_PERF_SEL_tl_in_xfc', - 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 170: 'DB_PERF_SEL_tl_in_fast_z_stall', - 171: 'DB_PERF_SEL_tl_out_xfc', - 172: 'DB_PERF_SEL_tl_out_squads', - 173: 'DB_PERF_SEL_zf_plane_multicycle', - 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', - 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', - 180: 'DB_PERF_SEL_ts_tc_update_stall', - 181: 'DB_PERF_SEL_sc_kick_start', - 182: 'DB_PERF_SEL_sc_kick_end', - 183: 'DB_PERF_SEL_clock_reg_active', - 184: 'DB_PERF_SEL_clock_main_active', - 185: 'DB_PERF_SEL_clock_mem_export_active', - 186: 'DB_PERF_SEL_esr_ps_out_busy', - 187: 'DB_PERF_SEL_esr_ps_lqf_busy', - 188: 'DB_PERF_SEL_esr_ps_lqf_stall', - 189: 'DB_PERF_SEL_etr_out_send', - 190: 'DB_PERF_SEL_etr_out_busy', - 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', - 193: 'DB_PERF_SEL_etr_out_esr_stall', - 194: 'DB_PERF_SEL_esr_ps_sqq_busy', - 195: 'DB_PERF_SEL_esr_ps_sqq_stall', - 196: 'DB_PERF_SEL_esr_eot_fwd_busy', - 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 198: 'DB_PERF_SEL_esr_eot_fwd_forward', - 199: 'DB_PERF_SEL_esr_sqq_zi_busy', - 200: 'DB_PERF_SEL_esr_sqq_zi_stall', - 201: 'DB_PERF_SEL_postzl_sq_pt_busy', - 202: 'DB_PERF_SEL_postzl_sq_pt_stall', - 203: 'DB_PERF_SEL_postzl_se_busy', - 204: 'DB_PERF_SEL_postzl_se_stall', - 205: 'DB_PERF_SEL_postzl_partial_launch', - 206: 'DB_PERF_SEL_postzl_full_launch', - 207: 'DB_PERF_SEL_postzl_partial_waiting', - 208: 'DB_PERF_SEL_postzl_tile_mem_stall', - 209: 'DB_PERF_SEL_postzl_tile_init_stall', - 210: 'DB_PEFF_SEL_prezl_tile_mem_stall', - 211: 'DB_PERF_SEL_prezl_tile_init_stall', - 212: 'DB_PERF_SEL_dtt_sm_clash_stall', - 213: 'DB_PERF_SEL_dtt_sm_slot_stall', - 214: 'DB_PERF_SEL_dtt_sm_miss_stall', - 215: 'DB_PERF_SEL_mi_rdreq_busy', - 216: 'DB_PERF_SEL_mi_rdreq_stall', - 217: 'DB_PERF_SEL_mi_wrreq_busy', - 218: 'DB_PERF_SEL_mi_wrreq_stall', - 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 220: 'DB_PERF_SEL_dkg_tile_rate_tile', - 221: 'DB_PERF_SEL_prezl_src_in_sends', - 222: 'DB_PERF_SEL_prezl_src_in_stall', - 223: 'DB_PERF_SEL_prezl_src_in_squads', - 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', - 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 227: 'DB_PERF_SEL_prezl_src_out_stall', - 228: 'DB_PERF_SEL_postzl_src_in_sends', - 229: 'DB_PERF_SEL_postzl_src_in_stall', - 230: 'DB_PERF_SEL_postzl_src_in_squads', - 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', - 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 234: 'DB_PERF_SEL_postzl_src_out_stall', - 235: 'DB_PERF_SEL_esr_ps_src_in_sends', - 236: 'DB_PERF_SEL_esr_ps_src_in_stall', - 237: 'DB_PERF_SEL_esr_ps_src_in_squads', - 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 242: 'DB_PERF_SEL_esr_ps_src_out_stall', - 243: 'DB_PERF_SEL_depth_bounds_qtiles_culled', - 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 246: 'DB_PERF_SEL_flush_compressed', - 247: 'DB_PERF_SEL_flush_plane_le4', - 248: 'DB_PERF_SEL_tiles_z_fully_summarized', - 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', - 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', - 256: 'DB_PERF_SEL_di_dt_stall', - 257: 'DB_PERF_SEL_DB_SC_quad_double_quad', - 258: 'DB_PERF_SEL_SX_DB_quad_export_quads', - 259: 'DB_PERF_SEL_SX_DB_quad_double_format', - 260: 'DB_PERF_SEL_SX_DB_quad_fast_format', - 261: 'DB_PERF_SEL_SX_DB_quad_slow_format', - 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', - 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', - 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', - 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 270: 'DB_PERF_SEL_DB_CB_rdret_ack', - 271: 'DB_PERF_SEL_DB_CB_rdret_nack', - 272: 'DB_PERF_SEL_DB_CB_wrret_ack', - 273: 'DB_PERF_SEL_DB_CB_wrret_nack', - 274: 'DB_PERF_SEL_DFSM_squads_in', - 275: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', - 276: 'DB_PERF_SEL_DFSM_quads_in', - 277: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', - 278: 'DB_PERF_SEL_DFSM_lit_pixels_in', - 279: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', - 280: 'DB_PERF_SEL_DFSM_lit_samples_in', - 281: 'DB_PERF_SEL_DFSM_lit_samples_out', - 282: 'DB_PERF_SEL_DFSM_cycles_above_watermark', - 283: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', - 284: 'DB_PERF_SEL_DFSM_stalled_by_downstream', - 285: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', - 286: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', - 287: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', - 288: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', -} -DB_PERF_SEL_SC_DB_tile_sends = 0 -DB_PERF_SEL_SC_DB_tile_busy = 1 -DB_PERF_SEL_SC_DB_tile_stalls = 2 -DB_PERF_SEL_SC_DB_tile_events = 3 -DB_PERF_SEL_SC_DB_tile_tiles = 4 -DB_PERF_SEL_SC_DB_tile_covered = 5 -DB_PERF_SEL_hiz_tc_read_starved = 6 -DB_PERF_SEL_hiz_tc_write_stall = 7 -DB_PERF_SEL_hiz_qtiles_culled = 8 -DB_PERF_SEL_his_qtiles_culled = 9 -DB_PERF_SEL_DB_SC_tile_sends = 10 -DB_PERF_SEL_DB_SC_tile_busy = 11 -DB_PERF_SEL_DB_SC_tile_stalls = 12 -DB_PERF_SEL_DB_SC_tile_df_stalls = 13 -DB_PERF_SEL_DB_SC_tile_tiles = 14 -DB_PERF_SEL_DB_SC_tile_culled = 15 -DB_PERF_SEL_DB_SC_tile_hier_kill = 16 -DB_PERF_SEL_DB_SC_tile_fast_ops = 17 -DB_PERF_SEL_DB_SC_tile_no_ops = 18 -DB_PERF_SEL_DB_SC_tile_tile_rate = 19 -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 -DB_PERF_SEL_SC_DB_quad_sends = 23 -DB_PERF_SEL_SC_DB_quad_busy = 24 -DB_PERF_SEL_SC_DB_quad_squads = 25 -DB_PERF_SEL_SC_DB_quad_tiles = 26 -DB_PERF_SEL_SC_DB_quad_pixels = 27 -DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 -DB_PERF_SEL_DB_SC_quad_sends = 29 -DB_PERF_SEL_DB_SC_quad_busy = 30 -DB_PERF_SEL_DB_SC_quad_stalls = 31 -DB_PERF_SEL_DB_SC_quad_tiles = 32 -DB_PERF_SEL_DB_SC_quad_lit_quad = 33 -DB_PERF_SEL_DB_CB_tile_sends = 34 -DB_PERF_SEL_DB_CB_tile_busy = 35 -DB_PERF_SEL_DB_CB_tile_stalls = 36 -DB_PERF_SEL_SX_DB_quad_sends = 37 -DB_PERF_SEL_SX_DB_quad_busy = 38 -DB_PERF_SEL_SX_DB_quad_stalls = 39 -DB_PERF_SEL_SX_DB_quad_quads = 40 -DB_PERF_SEL_SX_DB_quad_pixels = 41 -DB_PERF_SEL_SX_DB_quad_exports = 42 -DB_PERF_SEL_SH_quads_outstanding_sum = 43 -DB_PERF_SEL_DB_CB_lquad_sends = 44 -DB_PERF_SEL_DB_CB_lquad_busy = 45 -DB_PERF_SEL_DB_CB_lquad_stalls = 46 -DB_PERF_SEL_DB_CB_lquad_quads = 47 -DB_PERF_SEL_tile_rd_sends = 48 -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 -DB_PERF_SEL_quad_rd_sends = 50 -DB_PERF_SEL_quad_rd_busy = 51 -DB_PERF_SEL_quad_rd_mi_stall = 52 -DB_PERF_SEL_quad_rd_rw_collision = 53 -DB_PERF_SEL_quad_rd_tag_stall = 54 -DB_PERF_SEL_quad_rd_32byte_reqs = 55 -DB_PERF_SEL_quad_rd_panic = 56 -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 -DB_PERF_SEL_quad_rdret_sends = 58 -DB_PERF_SEL_quad_rdret_busy = 59 -DB_PERF_SEL_tile_wr_sends = 60 -DB_PERF_SEL_tile_wr_acks = 61 -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 -DB_PERF_SEL_quad_wr_sends = 63 -DB_PERF_SEL_quad_wr_busy = 64 -DB_PERF_SEL_quad_wr_mi_stall = 65 -DB_PERF_SEL_quad_wr_coherency_stall = 66 -DB_PERF_SEL_quad_wr_acks = 67 -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 -DB_PERF_SEL_Tile_Cache_misses = 69 -DB_PERF_SEL_Tile_Cache_hits = 70 -DB_PERF_SEL_Tile_Cache_flushes = 71 -DB_PERF_SEL_Tile_Cache_surface_stall = 72 -DB_PERF_SEL_Tile_Cache_starves = 73 -DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 -DB_PERF_SEL_tcp_dispatcher_reads = 75 -DB_PERF_SEL_tcp_prefetcher_reads = 76 -DB_PERF_SEL_tcp_preloader_reads = 77 -DB_PERF_SEL_tcp_dispatcher_flushes = 78 -DB_PERF_SEL_tcp_prefetcher_flushes = 79 -DB_PERF_SEL_tcp_preloader_flushes = 80 -DB_PERF_SEL_Depth_Tile_Cache_sends = 81 -DB_PERF_SEL_Depth_Tile_Cache_busy = 82 -DB_PERF_SEL_Depth_Tile_Cache_starves = 83 -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 -DB_PERF_SEL_Depth_Tile_Cache_misses = 86 -DB_PERF_SEL_Depth_Tile_Cache_hits = 87 -DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 -DB_PERF_SEL_Depth_Tile_Cache_event = 91 -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 -DB_PERF_SEL_Stencil_Cache_misses = 95 -DB_PERF_SEL_Stencil_Cache_hits = 96 -DB_PERF_SEL_Stencil_Cache_flushes = 97 -DB_PERF_SEL_Stencil_Cache_starves = 98 -DB_PERF_SEL_Stencil_Cache_frees = 99 -DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 -DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 -DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 -DB_PERF_SEL_Z_Cache_pmask_misses = 104 -DB_PERF_SEL_Z_Cache_pmask_hits = 105 -DB_PERF_SEL_Z_Cache_pmask_flushes = 106 -DB_PERF_SEL_Z_Cache_pmask_starves = 107 -DB_PERF_SEL_Z_Cache_frees = 108 -DB_PERF_SEL_Plane_Cache_misses = 109 -DB_PERF_SEL_Plane_Cache_hits = 110 -DB_PERF_SEL_Plane_Cache_flushes = 111 -DB_PERF_SEL_Plane_Cache_starves = 112 -DB_PERF_SEL_Plane_Cache_frees = 113 -DB_PERF_SEL_flush_expanded_stencil = 114 -DB_PERF_SEL_flush_compressed_stencil = 115 -DB_PERF_SEL_flush_single_stencil = 116 -DB_PERF_SEL_planes_flushed = 117 -DB_PERF_SEL_flush_1plane = 118 -DB_PERF_SEL_flush_2plane = 119 -DB_PERF_SEL_flush_3plane = 120 -DB_PERF_SEL_flush_4plane = 121 -DB_PERF_SEL_flush_5plane = 122 -DB_PERF_SEL_flush_6plane = 123 -DB_PERF_SEL_flush_7plane = 124 -DB_PERF_SEL_flush_8plane = 125 -DB_PERF_SEL_flush_9plane = 126 -DB_PERF_SEL_flush_10plane = 127 -DB_PERF_SEL_flush_11plane = 128 -DB_PERF_SEL_flush_12plane = 129 -DB_PERF_SEL_flush_13plane = 130 -DB_PERF_SEL_flush_14plane = 131 -DB_PERF_SEL_flush_15plane = 132 -DB_PERF_SEL_flush_16plane = 133 -DB_PERF_SEL_flush_expanded_z = 134 -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 -DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 -DB_PERF_SEL_dk_tile_sends = 137 -DB_PERF_SEL_dk_tile_busy = 138 -DB_PERF_SEL_dk_tile_quad_starves = 139 -DB_PERF_SEL_dk_tile_stalls = 140 -DB_PERF_SEL_dk_squad_sends = 141 -DB_PERF_SEL_dk_squad_busy = 142 -DB_PERF_SEL_dk_squad_stalls = 143 -DB_PERF_SEL_Op_Pipe_Busy = 144 -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 -DB_PERF_SEL_qc_busy = 146 -DB_PERF_SEL_qc_xfc = 147 -DB_PERF_SEL_qc_conflicts = 148 -DB_PERF_SEL_qc_full_stall = 149 -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 -DB_PERF_SEL_tsc_insert_summarize_stall = 152 -DB_PERF_SEL_tl_busy = 153 -DB_PERF_SEL_tl_dtc_read_starved = 154 -DB_PERF_SEL_tl_z_fetch_stall = 155 -DB_PERF_SEL_tl_stencil_stall = 156 -DB_PERF_SEL_tl_z_decompress_stall = 157 -DB_PERF_SEL_tl_stencil_locked_stall = 158 -DB_PERF_SEL_tl_events = 159 -DB_PERF_SEL_tl_summarize_squads = 160 -DB_PERF_SEL_tl_flush_expand_squads = 161 -DB_PERF_SEL_tl_expand_squads = 162 -DB_PERF_SEL_tl_preZ_squads = 163 -DB_PERF_SEL_tl_postZ_squads = 164 -DB_PERF_SEL_tl_preZ_noop_squads = 165 -DB_PERF_SEL_tl_postZ_noop_squads = 166 -DB_PERF_SEL_tl_tile_ops = 167 -DB_PERF_SEL_tl_in_xfc = 168 -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 -DB_PERF_SEL_tl_in_fast_z_stall = 170 -DB_PERF_SEL_tl_out_xfc = 171 -DB_PERF_SEL_tl_out_squads = 172 -DB_PERF_SEL_zf_plane_multicycle = 173 -DB_PERF_SEL_PostZ_Samples_passing_Z = 174 -DB_PERF_SEL_PostZ_Samples_failing_Z = 175 -DB_PERF_SEL_PostZ_Samples_failing_S = 176 -DB_PERF_SEL_PreZ_Samples_passing_Z = 177 -DB_PERF_SEL_PreZ_Samples_failing_Z = 178 -DB_PERF_SEL_PreZ_Samples_failing_S = 179 -DB_PERF_SEL_ts_tc_update_stall = 180 -DB_PERF_SEL_sc_kick_start = 181 -DB_PERF_SEL_sc_kick_end = 182 -DB_PERF_SEL_clock_reg_active = 183 -DB_PERF_SEL_clock_main_active = 184 -DB_PERF_SEL_clock_mem_export_active = 185 -DB_PERF_SEL_esr_ps_out_busy = 186 -DB_PERF_SEL_esr_ps_lqf_busy = 187 -DB_PERF_SEL_esr_ps_lqf_stall = 188 -DB_PERF_SEL_etr_out_send = 189 -DB_PERF_SEL_etr_out_busy = 190 -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 -DB_PERF_SEL_etr_out_cb_tile_stall = 192 -DB_PERF_SEL_etr_out_esr_stall = 193 -DB_PERF_SEL_esr_ps_sqq_busy = 194 -DB_PERF_SEL_esr_ps_sqq_stall = 195 -DB_PERF_SEL_esr_eot_fwd_busy = 196 -DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 -DB_PERF_SEL_esr_eot_fwd_forward = 198 -DB_PERF_SEL_esr_sqq_zi_busy = 199 -DB_PERF_SEL_esr_sqq_zi_stall = 200 -DB_PERF_SEL_postzl_sq_pt_busy = 201 -DB_PERF_SEL_postzl_sq_pt_stall = 202 -DB_PERF_SEL_postzl_se_busy = 203 -DB_PERF_SEL_postzl_se_stall = 204 -DB_PERF_SEL_postzl_partial_launch = 205 -DB_PERF_SEL_postzl_full_launch = 206 -DB_PERF_SEL_postzl_partial_waiting = 207 -DB_PERF_SEL_postzl_tile_mem_stall = 208 -DB_PERF_SEL_postzl_tile_init_stall = 209 -DB_PEFF_SEL_prezl_tile_mem_stall = 210 -DB_PERF_SEL_prezl_tile_init_stall = 211 -DB_PERF_SEL_dtt_sm_clash_stall = 212 -DB_PERF_SEL_dtt_sm_slot_stall = 213 -DB_PERF_SEL_dtt_sm_miss_stall = 214 -DB_PERF_SEL_mi_rdreq_busy = 215 -DB_PERF_SEL_mi_rdreq_stall = 216 -DB_PERF_SEL_mi_wrreq_busy = 217 -DB_PERF_SEL_mi_wrreq_stall = 218 -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 -DB_PERF_SEL_dkg_tile_rate_tile = 220 -DB_PERF_SEL_prezl_src_in_sends = 221 -DB_PERF_SEL_prezl_src_in_stall = 222 -DB_PERF_SEL_prezl_src_in_squads = 223 -DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 -DB_PERF_SEL_prezl_src_in_tile_rate = 225 -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 -DB_PERF_SEL_prezl_src_out_stall = 227 -DB_PERF_SEL_postzl_src_in_sends = 228 -DB_PERF_SEL_postzl_src_in_stall = 229 -DB_PERF_SEL_postzl_src_in_squads = 230 -DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 -DB_PERF_SEL_postzl_src_in_tile_rate = 232 -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 -DB_PERF_SEL_postzl_src_out_stall = 234 -DB_PERF_SEL_esr_ps_src_in_sends = 235 -DB_PERF_SEL_esr_ps_src_in_stall = 236 -DB_PERF_SEL_esr_ps_src_in_squads = 237 -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 -DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 -DB_PERF_SEL_esr_ps_src_out_stall = 242 -DB_PERF_SEL_depth_bounds_qtiles_culled = 243 -DB_PERF_SEL_PreZ_Samples_failing_DB = 244 -DB_PERF_SEL_PostZ_Samples_failing_DB = 245 -DB_PERF_SEL_flush_compressed = 246 -DB_PERF_SEL_flush_plane_le4 = 247 -DB_PERF_SEL_tiles_z_fully_summarized = 248 -DB_PERF_SEL_tiles_stencil_fully_summarized = 249 -DB_PERF_SEL_tiles_z_clear_on_expclear = 250 -DB_PERF_SEL_tiles_s_clear_on_expclear = 251 -DB_PERF_SEL_tiles_decomp_on_expclear = 252 -DB_PERF_SEL_tiles_compressed_to_decompressed = 253 -DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 -DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 -DB_PERF_SEL_di_dt_stall = 256 -DB_PERF_SEL_DB_SC_quad_double_quad = 257 -DB_PERF_SEL_SX_DB_quad_export_quads = 258 -DB_PERF_SEL_SX_DB_quad_double_format = 259 -DB_PERF_SEL_SX_DB_quad_fast_format = 260 -DB_PERF_SEL_SX_DB_quad_slow_format = 261 -DB_PERF_SEL_DB_CB_lquad_export_quads = 262 -DB_PERF_SEL_DB_CB_lquad_double_format = 263 -DB_PERF_SEL_DB_CB_lquad_fast_format = 264 -DB_PERF_SEL_DB_CB_lquad_slow_format = 265 -DB_PERF_SEL_CB_DB_rdreq_sends = 266 -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 -DB_PERF_SEL_CB_DB_wrreq_sends = 268 -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 -DB_PERF_SEL_DB_CB_rdret_ack = 270 -DB_PERF_SEL_DB_CB_rdret_nack = 271 -DB_PERF_SEL_DB_CB_wrret_ack = 272 -DB_PERF_SEL_DB_CB_wrret_nack = 273 -DB_PERF_SEL_DFSM_squads_in = 274 -DB_PERF_SEL_DFSM_full_cleared_squads_out = 275 -DB_PERF_SEL_DFSM_quads_in = 276 -DB_PERF_SEL_DFSM_fully_cleared_quads_out = 277 -DB_PERF_SEL_DFSM_lit_pixels_in = 278 -DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 279 -DB_PERF_SEL_DFSM_lit_samples_in = 280 -DB_PERF_SEL_DFSM_lit_samples_out = 281 -DB_PERF_SEL_DFSM_cycles_above_watermark = 282 -DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 283 -DB_PERF_SEL_DFSM_stalled_by_downstream = 284 -DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 285 -DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 286 -DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 287 -DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 288 -PerfCounter_Vals = ctypes.c_uint32 # enum - -# values for enumeration 'RingCounterControl' -RingCounterControl__enumvalues = { - 0: 'COUNTER_RING_SPLIT', - 1: 'COUNTER_RING_0', - 2: 'COUNTER_RING_1', -} -COUNTER_RING_SPLIT = 0 -COUNTER_RING_0 = 1 -COUNTER_RING_1 = 2 -RingCounterControl = ctypes.c_uint32 # enum - -# values for enumeration 'DbMemArbWatermarks' -DbMemArbWatermarks__enumvalues = { - 0: 'TRANSFERRED_64_BYTES', - 1: 'TRANSFERRED_128_BYTES', - 2: 'TRANSFERRED_256_BYTES', - 3: 'TRANSFERRED_512_BYTES', - 4: 'TRANSFERRED_1024_BYTES', - 5: 'TRANSFERRED_2048_BYTES', - 6: 'TRANSFERRED_4096_BYTES', - 7: 'TRANSFERRED_8192_BYTES', -} -TRANSFERRED_64_BYTES = 0 -TRANSFERRED_128_BYTES = 1 -TRANSFERRED_256_BYTES = 2 -TRANSFERRED_512_BYTES = 3 -TRANSFERRED_1024_BYTES = 4 -TRANSFERRED_2048_BYTES = 5 -TRANSFERRED_4096_BYTES = 6 -TRANSFERRED_8192_BYTES = 7 -DbMemArbWatermarks = ctypes.c_uint32 # enum - -# values for enumeration 'DFSMFlushEvents' -DFSMFlushEvents__enumvalues = { - 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', - 1: 'DB_FLUSH_AND_INV_DB_META', - 2: 'DB_CACHE_FLUSH', - 3: 'DB_CACHE_FLUSH_TS', - 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', - 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', -} -DB_FLUSH_AND_INV_DB_DATA_TS = 0 -DB_FLUSH_AND_INV_DB_META = 1 -DB_CACHE_FLUSH = 2 -DB_CACHE_FLUSH_TS = 3 -DB_CACHE_FLUSH_AND_INV_EVENT = 4 -DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 -DFSMFlushEvents = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeCounterId' -PixelPipeCounterId__enumvalues = { - 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', - 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', -} -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 -PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 -PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 -PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 -PixelPipeCounterId = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeStride' -PixelPipeStride__enumvalues = { - 0: 'PIXEL_PIPE_STRIDE_32_BITS', - 1: 'PIXEL_PIPE_STRIDE_64_BITS', - 2: 'PIXEL_PIPE_STRIDE_128_BITS', - 3: 'PIXEL_PIPE_STRIDE_256_BITS', -} -PIXEL_PIPE_STRIDE_32_BITS = 0 -PIXEL_PIPE_STRIDE_64_BITS = 1 -PIXEL_PIPE_STRIDE_128_BITS = 2 -PIXEL_PIPE_STRIDE_256_BITS = 3 -PixelPipeStride = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BORDER_COLOR_TYPE' -TEX_BORDER_COLOR_TYPE__enumvalues = { - 0: 'TEX_BorderColor_TransparentBlack', - 1: 'TEX_BorderColor_OpaqueBlack', - 2: 'TEX_BorderColor_OpaqueWhite', - 3: 'TEX_BorderColor_Register', -} -TEX_BorderColor_TransparentBlack = 0 -TEX_BorderColor_OpaqueBlack = 1 -TEX_BorderColor_OpaqueWhite = 2 -TEX_BorderColor_Register = 3 -TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CHROMA_KEY' -TEX_CHROMA_KEY__enumvalues = { - 0: 'TEX_ChromaKey_Disabled', - 1: 'TEX_ChromaKey_Kill', - 2: 'TEX_ChromaKey_Blend', - 3: 'TEX_ChromaKey_RESERVED_3', -} -TEX_ChromaKey_Disabled = 0 -TEX_ChromaKey_Kill = 1 -TEX_ChromaKey_Blend = 2 -TEX_ChromaKey_RESERVED_3 = 3 -TEX_CHROMA_KEY = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CLAMP' -TEX_CLAMP__enumvalues = { - 0: 'TEX_Clamp_Repeat', - 1: 'TEX_Clamp_Mirror', - 2: 'TEX_Clamp_ClampToLast', - 3: 'TEX_Clamp_MirrorOnceToLast', - 4: 'TEX_Clamp_ClampHalfToBorder', - 5: 'TEX_Clamp_MirrorOnceHalfToBorder', - 6: 'TEX_Clamp_ClampToBorder', - 7: 'TEX_Clamp_MirrorOnceToBorder', -} -TEX_Clamp_Repeat = 0 -TEX_Clamp_Mirror = 1 -TEX_Clamp_ClampToLast = 2 -TEX_Clamp_MirrorOnceToLast = 3 -TEX_Clamp_ClampHalfToBorder = 4 -TEX_Clamp_MirrorOnceHalfToBorder = 5 -TEX_Clamp_ClampToBorder = 6 -TEX_Clamp_MirrorOnceToBorder = 7 -TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_COORD_TYPE' -TEX_COORD_TYPE__enumvalues = { - 0: 'TEX_CoordType_Unnormalized', - 1: 'TEX_CoordType_Normalized', -} -TEX_CoordType_Unnormalized = 0 -TEX_CoordType_Normalized = 1 -TEX_COORD_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' -TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { - 0: 'TEX_DepthCompareFunction_Never', - 1: 'TEX_DepthCompareFunction_Less', - 2: 'TEX_DepthCompareFunction_Equal', - 3: 'TEX_DepthCompareFunction_LessEqual', - 4: 'TEX_DepthCompareFunction_Greater', - 5: 'TEX_DepthCompareFunction_NotEqual', - 6: 'TEX_DepthCompareFunction_GreaterEqual', - 7: 'TEX_DepthCompareFunction_Always', -} -TEX_DepthCompareFunction_Never = 0 -TEX_DepthCompareFunction_Less = 1 -TEX_DepthCompareFunction_Equal = 2 -TEX_DepthCompareFunction_LessEqual = 3 -TEX_DepthCompareFunction_Greater = 4 -TEX_DepthCompareFunction_NotEqual = 5 -TEX_DepthCompareFunction_GreaterEqual = 6 -TEX_DepthCompareFunction_Always = 7 -TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DIM' -TEX_DIM__enumvalues = { - 0: 'TEX_Dim_1D', - 1: 'TEX_Dim_2D', - 2: 'TEX_Dim_3D', - 3: 'TEX_Dim_CubeMap', - 4: 'TEX_Dim_1DArray', - 5: 'TEX_Dim_2DArray', - 6: 'TEX_Dim_2D_MSAA', - 7: 'TEX_Dim_2DArray_MSAA', -} -TEX_Dim_1D = 0 -TEX_Dim_2D = 1 -TEX_Dim_3D = 2 -TEX_Dim_CubeMap = 3 -TEX_Dim_1DArray = 4 -TEX_Dim_2DArray = 5 -TEX_Dim_2D_MSAA = 6 -TEX_Dim_2DArray_MSAA = 7 -TEX_DIM = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_FORMAT_COMP' -TEX_FORMAT_COMP__enumvalues = { - 0: 'TEX_FormatComp_Unsigned', - 1: 'TEX_FormatComp_Signed', - 2: 'TEX_FormatComp_UnsignedBiased', - 3: 'TEX_FormatComp_RESERVED_3', -} -TEX_FormatComp_Unsigned = 0 -TEX_FormatComp_Signed = 1 -TEX_FormatComp_UnsignedBiased = 2 -TEX_FormatComp_RESERVED_3 = 3 -TEX_FORMAT_COMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MAX_ANISO_RATIO' -TEX_MAX_ANISO_RATIO__enumvalues = { - 0: 'TEX_MaxAnisoRatio_1to1', - 1: 'TEX_MaxAnisoRatio_2to1', - 2: 'TEX_MaxAnisoRatio_4to1', - 3: 'TEX_MaxAnisoRatio_8to1', - 4: 'TEX_MaxAnisoRatio_16to1', - 5: 'TEX_MaxAnisoRatio_RESERVED_5', - 6: 'TEX_MaxAnisoRatio_RESERVED_6', - 7: 'TEX_MaxAnisoRatio_RESERVED_7', -} -TEX_MaxAnisoRatio_1to1 = 0 -TEX_MaxAnisoRatio_2to1 = 1 -TEX_MaxAnisoRatio_4to1 = 2 -TEX_MaxAnisoRatio_8to1 = 3 -TEX_MaxAnisoRatio_16to1 = 4 -TEX_MaxAnisoRatio_RESERVED_5 = 5 -TEX_MaxAnisoRatio_RESERVED_6 = 6 -TEX_MaxAnisoRatio_RESERVED_7 = 7 -TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MIP_FILTER' -TEX_MIP_FILTER__enumvalues = { - 0: 'TEX_MipFilter_None', - 1: 'TEX_MipFilter_Point', - 2: 'TEX_MipFilter_Linear', - 3: 'TEX_MipFilter_Point_Aniso_Adj', -} -TEX_MipFilter_None = 0 -TEX_MipFilter_Point = 1 -TEX_MipFilter_Linear = 2 -TEX_MipFilter_Point_Aniso_Adj = 3 -TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_REQUEST_SIZE' -TEX_REQUEST_SIZE__enumvalues = { - 0: 'TEX_RequestSize_32B', - 1: 'TEX_RequestSize_64B', - 2: 'TEX_RequestSize_128B', - 3: 'TEX_RequestSize_2X64B', -} -TEX_RequestSize_32B = 0 -TEX_RequestSize_64B = 1 -TEX_RequestSize_128B = 2 -TEX_RequestSize_2X64B = 3 -TEX_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_SAMPLER_TYPE' -TEX_SAMPLER_TYPE__enumvalues = { - 0: 'TEX_SamplerType_Invalid', - 1: 'TEX_SamplerType_Valid', -} -TEX_SamplerType_Invalid = 0 -TEX_SamplerType_Valid = 1 -TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_XY_FILTER' -TEX_XY_FILTER__enumvalues = { - 0: 'TEX_XYFilter_Point', - 1: 'TEX_XYFilter_Linear', - 2: 'TEX_XYFilter_AnisoPoint', - 3: 'TEX_XYFilter_AnisoLinear', -} -TEX_XYFilter_Point = 0 -TEX_XYFilter_Linear = 1 -TEX_XYFilter_AnisoPoint = 2 -TEX_XYFilter_AnisoLinear = 3 -TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_Z_FILTER' -TEX_Z_FILTER__enumvalues = { - 0: 'TEX_ZFilter_None', - 1: 'TEX_ZFilter_Point', - 2: 'TEX_ZFilter_Linear', - 3: 'TEX_ZFilter_RESERVED_3', -} -TEX_ZFilter_None = 0 -TEX_ZFilter_Point = 1 -TEX_ZFilter_Linear = 2 -TEX_ZFilter_RESERVED_3 = 3 -TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_CLAMP' -VTX_CLAMP__enumvalues = { - 0: 'VTX_Clamp_ClampToZero', - 1: 'VTX_Clamp_ClampToNAN', -} -VTX_Clamp_ClampToZero = 0 -VTX_Clamp_ClampToNAN = 1 -VTX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_FETCH_TYPE' -VTX_FETCH_TYPE__enumvalues = { - 0: 'VTX_FetchType_VertexData', - 1: 'VTX_FetchType_InstanceData', - 2: 'VTX_FetchType_NoIndexOffset', - 3: 'VTX_FetchType_RESERVED_3', -} -VTX_FetchType_VertexData = 0 -VTX_FetchType_InstanceData = 1 -VTX_FetchType_NoIndexOffset = 2 -VTX_FetchType_RESERVED_3 = 3 -VTX_FETCH_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_FORMAT_COMP_ALL' -VTX_FORMAT_COMP_ALL__enumvalues = { - 0: 'VTX_FormatCompAll_Unsigned', - 1: 'VTX_FormatCompAll_Signed', -} -VTX_FormatCompAll_Unsigned = 0 -VTX_FormatCompAll_Signed = 1 -VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'VTX_MEM_REQUEST_SIZE' -VTX_MEM_REQUEST_SIZE__enumvalues = { - 0: 'VTX_MemRequestSize_32B', - 1: 'VTX_MemRequestSize_64B', -} -VTX_MemRequestSize_32B = 0 -VTX_MemRequestSize_64B = 1 -VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_DATA_FORMAT' -TVX_DATA_FORMAT__enumvalues = { - 0: 'TVX_FMT_INVALID', - 1: 'TVX_FMT_8', - 2: 'TVX_FMT_4_4', - 3: 'TVX_FMT_3_3_2', - 4: 'TVX_FMT_RESERVED_4', - 5: 'TVX_FMT_16', - 6: 'TVX_FMT_16_FLOAT', - 7: 'TVX_FMT_8_8', - 8: 'TVX_FMT_5_6_5', - 9: 'TVX_FMT_6_5_5', - 10: 'TVX_FMT_1_5_5_5', - 11: 'TVX_FMT_4_4_4_4', - 12: 'TVX_FMT_5_5_5_1', - 13: 'TVX_FMT_32', - 14: 'TVX_FMT_32_FLOAT', - 15: 'TVX_FMT_16_16', - 16: 'TVX_FMT_16_16_FLOAT', - 17: 'TVX_FMT_8_24', - 18: 'TVX_FMT_8_24_FLOAT', - 19: 'TVX_FMT_24_8', - 20: 'TVX_FMT_24_8_FLOAT', - 21: 'TVX_FMT_10_11_11', - 22: 'TVX_FMT_10_11_11_FLOAT', - 23: 'TVX_FMT_11_11_10', - 24: 'TVX_FMT_11_11_10_FLOAT', - 25: 'TVX_FMT_2_10_10_10', - 26: 'TVX_FMT_8_8_8_8', - 27: 'TVX_FMT_10_10_10_2', - 28: 'TVX_FMT_X24_8_32_FLOAT', - 29: 'TVX_FMT_32_32', - 30: 'TVX_FMT_32_32_FLOAT', - 31: 'TVX_FMT_16_16_16_16', - 32: 'TVX_FMT_16_16_16_16_FLOAT', - 33: 'TVX_FMT_RESERVED_33', - 34: 'TVX_FMT_32_32_32_32', - 35: 'TVX_FMT_32_32_32_32_FLOAT', - 36: 'TVX_FMT_RESERVED_36', - 37: 'TVX_FMT_1', - 38: 'TVX_FMT_1_REVERSED', - 39: 'TVX_FMT_GB_GR', - 40: 'TVX_FMT_BG_RG', - 41: 'TVX_FMT_32_AS_8', - 42: 'TVX_FMT_32_AS_8_8', - 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', - 44: 'TVX_FMT_8_8_8', - 45: 'TVX_FMT_16_16_16', - 46: 'TVX_FMT_16_16_16_FLOAT', - 47: 'TVX_FMT_32_32_32', - 48: 'TVX_FMT_32_32_32_FLOAT', - 49: 'TVX_FMT_BC1', - 50: 'TVX_FMT_BC2', - 51: 'TVX_FMT_BC3', - 52: 'TVX_FMT_BC4', - 53: 'TVX_FMT_BC5', - 54: 'TVX_FMT_APC0', - 55: 'TVX_FMT_APC1', - 56: 'TVX_FMT_APC2', - 57: 'TVX_FMT_APC3', - 58: 'TVX_FMT_APC4', - 59: 'TVX_FMT_APC5', - 60: 'TVX_FMT_APC6', - 61: 'TVX_FMT_APC7', - 62: 'TVX_FMT_CTX1', - 63: 'TVX_FMT_RESERVED_63', -} -TVX_FMT_INVALID = 0 -TVX_FMT_8 = 1 -TVX_FMT_4_4 = 2 -TVX_FMT_3_3_2 = 3 -TVX_FMT_RESERVED_4 = 4 -TVX_FMT_16 = 5 -TVX_FMT_16_FLOAT = 6 -TVX_FMT_8_8 = 7 -TVX_FMT_5_6_5 = 8 -TVX_FMT_6_5_5 = 9 -TVX_FMT_1_5_5_5 = 10 -TVX_FMT_4_4_4_4 = 11 -TVX_FMT_5_5_5_1 = 12 -TVX_FMT_32 = 13 -TVX_FMT_32_FLOAT = 14 -TVX_FMT_16_16 = 15 -TVX_FMT_16_16_FLOAT = 16 -TVX_FMT_8_24 = 17 -TVX_FMT_8_24_FLOAT = 18 -TVX_FMT_24_8 = 19 -TVX_FMT_24_8_FLOAT = 20 -TVX_FMT_10_11_11 = 21 -TVX_FMT_10_11_11_FLOAT = 22 -TVX_FMT_11_11_10 = 23 -TVX_FMT_11_11_10_FLOAT = 24 -TVX_FMT_2_10_10_10 = 25 -TVX_FMT_8_8_8_8 = 26 -TVX_FMT_10_10_10_2 = 27 -TVX_FMT_X24_8_32_FLOAT = 28 -TVX_FMT_32_32 = 29 -TVX_FMT_32_32_FLOAT = 30 -TVX_FMT_16_16_16_16 = 31 -TVX_FMT_16_16_16_16_FLOAT = 32 -TVX_FMT_RESERVED_33 = 33 -TVX_FMT_32_32_32_32 = 34 -TVX_FMT_32_32_32_32_FLOAT = 35 -TVX_FMT_RESERVED_36 = 36 -TVX_FMT_1 = 37 -TVX_FMT_1_REVERSED = 38 -TVX_FMT_GB_GR = 39 -TVX_FMT_BG_RG = 40 -TVX_FMT_32_AS_8 = 41 -TVX_FMT_32_AS_8_8 = 42 -TVX_FMT_5_9_9_9_SHAREDEXP = 43 -TVX_FMT_8_8_8 = 44 -TVX_FMT_16_16_16 = 45 -TVX_FMT_16_16_16_FLOAT = 46 -TVX_FMT_32_32_32 = 47 -TVX_FMT_32_32_32_FLOAT = 48 -TVX_FMT_BC1 = 49 -TVX_FMT_BC2 = 50 -TVX_FMT_BC3 = 51 -TVX_FMT_BC4 = 52 -TVX_FMT_BC5 = 53 -TVX_FMT_APC0 = 54 -TVX_FMT_APC1 = 55 -TVX_FMT_APC2 = 56 -TVX_FMT_APC3 = 57 -TVX_FMT_APC4 = 58 -TVX_FMT_APC5 = 59 -TVX_FMT_APC6 = 60 -TVX_FMT_APC7 = 61 -TVX_FMT_CTX1 = 62 -TVX_FMT_RESERVED_63 = 63 -TVX_DATA_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_DST_SEL' -TVX_DST_SEL__enumvalues = { - 0: 'TVX_DstSel_X', - 1: 'TVX_DstSel_Y', - 2: 'TVX_DstSel_Z', - 3: 'TVX_DstSel_W', - 4: 'TVX_DstSel_0f', - 5: 'TVX_DstSel_1f', - 6: 'TVX_DstSel_RESERVED_6', - 7: 'TVX_DstSel_Mask', -} -TVX_DstSel_X = 0 -TVX_DstSel_Y = 1 -TVX_DstSel_Z = 2 -TVX_DstSel_W = 3 -TVX_DstSel_0f = 4 -TVX_DstSel_1f = 5 -TVX_DstSel_RESERVED_6 = 6 -TVX_DstSel_Mask = 7 -TVX_DST_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_ENDIAN_SWAP' -TVX_ENDIAN_SWAP__enumvalues = { - 0: 'TVX_EndianSwap_None', - 1: 'TVX_EndianSwap_8in16', - 2: 'TVX_EndianSwap_8in32', - 3: 'TVX_EndianSwap_8in64', -} -TVX_EndianSwap_None = 0 -TVX_EndianSwap_8in16 = 1 -TVX_EndianSwap_8in32 = 2 -TVX_EndianSwap_8in64 = 3 -TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_INST' -TVX_INST__enumvalues = { - 0: 'TVX_Inst_NormalVertexFetch', - 1: 'TVX_Inst_SemanticVertexFetch', - 2: 'TVX_Inst_RESERVED_2', - 3: 'TVX_Inst_LD', - 4: 'TVX_Inst_GetTextureResInfo', - 5: 'TVX_Inst_GetNumberOfSamples', - 6: 'TVX_Inst_GetLOD', - 7: 'TVX_Inst_GetGradientsH', - 8: 'TVX_Inst_GetGradientsV', - 9: 'TVX_Inst_SetTextureOffsets', - 10: 'TVX_Inst_KeepGradients', - 11: 'TVX_Inst_SetGradientsH', - 12: 'TVX_Inst_SetGradientsV', - 13: 'TVX_Inst_Pass', - 14: 'TVX_Inst_GetBufferResInfo', - 15: 'TVX_Inst_RESERVED_15', - 16: 'TVX_Inst_Sample', - 17: 'TVX_Inst_Sample_L', - 18: 'TVX_Inst_Sample_LB', - 19: 'TVX_Inst_Sample_LZ', - 20: 'TVX_Inst_Sample_G', - 21: 'TVX_Inst_Gather4', - 22: 'TVX_Inst_Sample_G_LB', - 23: 'TVX_Inst_Gather4_O', - 24: 'TVX_Inst_Sample_C', - 25: 'TVX_Inst_Sample_C_L', - 26: 'TVX_Inst_Sample_C_LB', - 27: 'TVX_Inst_Sample_C_LZ', - 28: 'TVX_Inst_Sample_C_G', - 29: 'TVX_Inst_Gather4_C', - 30: 'TVX_Inst_Sample_C_G_LB', - 31: 'TVX_Inst_Gather4_C_O', -} -TVX_Inst_NormalVertexFetch = 0 -TVX_Inst_SemanticVertexFetch = 1 -TVX_Inst_RESERVED_2 = 2 -TVX_Inst_LD = 3 -TVX_Inst_GetTextureResInfo = 4 -TVX_Inst_GetNumberOfSamples = 5 -TVX_Inst_GetLOD = 6 -TVX_Inst_GetGradientsH = 7 -TVX_Inst_GetGradientsV = 8 -TVX_Inst_SetTextureOffsets = 9 -TVX_Inst_KeepGradients = 10 -TVX_Inst_SetGradientsH = 11 -TVX_Inst_SetGradientsV = 12 -TVX_Inst_Pass = 13 -TVX_Inst_GetBufferResInfo = 14 -TVX_Inst_RESERVED_15 = 15 -TVX_Inst_Sample = 16 -TVX_Inst_Sample_L = 17 -TVX_Inst_Sample_LB = 18 -TVX_Inst_Sample_LZ = 19 -TVX_Inst_Sample_G = 20 -TVX_Inst_Gather4 = 21 -TVX_Inst_Sample_G_LB = 22 -TVX_Inst_Gather4_O = 23 -TVX_Inst_Sample_C = 24 -TVX_Inst_Sample_C_L = 25 -TVX_Inst_Sample_C_LB = 26 -TVX_Inst_Sample_C_LZ = 27 -TVX_Inst_Sample_C_G = 28 -TVX_Inst_Gather4_C = 29 -TVX_Inst_Sample_C_G_LB = 30 -TVX_Inst_Gather4_C_O = 31 -TVX_INST = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_NUM_FORMAT_ALL' -TVX_NUM_FORMAT_ALL__enumvalues = { - 0: 'TVX_NumFormatAll_Norm', - 1: 'TVX_NumFormatAll_Int', - 2: 'TVX_NumFormatAll_Scaled', - 3: 'TVX_NumFormatAll_RESERVED_3', -} -TVX_NumFormatAll_Norm = 0 -TVX_NumFormatAll_Int = 1 -TVX_NumFormatAll_Scaled = 2 -TVX_NumFormatAll_RESERVED_3 = 3 -TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_SRC_SEL' -TVX_SRC_SEL__enumvalues = { - 0: 'TVX_SrcSel_X', - 1: 'TVX_SrcSel_Y', - 2: 'TVX_SrcSel_Z', - 3: 'TVX_SrcSel_W', - 4: 'TVX_SrcSel_0f', - 5: 'TVX_SrcSel_1f', -} -TVX_SrcSel_X = 0 -TVX_SrcSel_Y = 1 -TVX_SrcSel_Z = 2 -TVX_SrcSel_W = 3 -TVX_SrcSel_0f = 4 -TVX_SrcSel_1f = 5 -TVX_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_SRF_MODE_ALL' -TVX_SRF_MODE_ALL__enumvalues = { - 0: 'TVX_SRFModeAll_ZCMO', - 1: 'TVX_SRFModeAll_NZ', -} -TVX_SRFModeAll_ZCMO = 0 -TVX_SRFModeAll_NZ = 1 -TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_TYPE' -TVX_TYPE__enumvalues = { - 0: 'TVX_Type_InvalidTextureResource', - 1: 'TVX_Type_InvalidVertexBuffer', - 2: 'TVX_Type_ValidTextureResource', - 3: 'TVX_Type_ValidVertexBuffer', -} -TVX_Type_InvalidTextureResource = 0 -TVX_Type_InvalidVertexBuffer = 1 -TVX_Type_ValidTextureResource = 2 -TVX_Type_ValidVertexBuffer = 3 -TVX_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SU_PERFCNT_SEL' -SU_PERFCNT_SEL__enumvalues = { - 0: 'PERF_PAPC_PASX_REQ', - 1: 'PERF_PAPC_PASX_DISABLE_PIPE', - 2: 'PERF_PAPC_PASX_FIRST_VECTOR', - 3: 'PERF_PAPC_PASX_SECOND_VECTOR', - 4: 'PERF_PAPC_PASX_FIRST_DEAD', - 5: 'PERF_PAPC_PASX_SECOND_DEAD', - 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 8: 'PERF_PAPC_PA_INPUT_PRIM', - 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', - 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 14: 'PERF_PAPC_CLPR_CULL_PRIM', - 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', - 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', - 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', - 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', - 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', - 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 39: 'PERF_PAPC_CLSM_NULL_PRIM', - 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', - 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', - 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', - 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', - 49: 'PERF_PAPC_SU_INPUT_PRIM', - 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', - 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 61: 'PERF_PAPC_SU_OUTPUT_PRIM', - 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', - 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', - 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 77: 'PERF_PAPC_PASX_REQ_IDLE', - 78: 'PERF_PAPC_PASX_REQ_BUSY', - 79: 'PERF_PAPC_PASX_REQ_STALLED', - 80: 'PERF_PAPC_PASX_REC_IDLE', - 81: 'PERF_PAPC_PASX_REC_BUSY', - 82: 'PERF_PAPC_PASX_REC_STARVED_SX', - 83: 'PERF_PAPC_PASX_REC_STALLED', - 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 86: 'PERF_PAPC_CCGSM_IDLE', - 87: 'PERF_PAPC_CCGSM_BUSY', - 88: 'PERF_PAPC_CCGSM_STALLED', - 89: 'PERF_PAPC_CLPRIM_IDLE', - 90: 'PERF_PAPC_CLPRIM_BUSY', - 91: 'PERF_PAPC_CLPRIM_STALLED', - 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 93: 'PERF_PAPC_CLIPSM_IDLE', - 94: 'PERF_PAPC_CLIPSM_BUSY', - 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', - 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 100: 'PERF_PAPC_CLIPGA_IDLE', - 101: 'PERF_PAPC_CLIPGA_BUSY', - 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 103: 'PERF_PAPC_CLIPGA_STALLED', - 104: 'PERF_PAPC_CLIP_IDLE', - 105: 'PERF_PAPC_CLIP_BUSY', - 106: 'PERF_PAPC_SU_IDLE', - 107: 'PERF_PAPC_SU_BUSY', - 108: 'PERF_PAPC_SU_STARVED_CLIP', - 109: 'PERF_PAPC_SU_STALLED_SC', - 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', - 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', - 112: 'PERF_PAPC_PA_REG_SCLK_VLD', - 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 114: 'PERF_PAPC_PASX_SE0_REQ', - 115: 'PERF_PAPC_PASX_SE1_REQ', - 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', - 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', - 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 131: 'PERF_PAPC_SU_SE0_STALLED_SC', - 132: 'PERF_PAPC_SU_SE1_STALLED_SC', - 133: 'PERF_PAPC_SU_SE01_STALLED_SC', - 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 135: 'PERF_PAPC_SU_CULLED_PRIM', - 136: 'PERF_PAPC_SU_OUTPUT_EOPG', - 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 151: 'PERF_PAPC_SU_SE2_STALLED_SC', - 152: 'PERF_PAPC_SU_SE3_STALLED_SC', -} -PERF_PAPC_PASX_REQ = 0 -PERF_PAPC_PASX_DISABLE_PIPE = 1 -PERF_PAPC_PASX_FIRST_VECTOR = 2 -PERF_PAPC_PASX_SECOND_VECTOR = 3 -PERF_PAPC_PASX_FIRST_DEAD = 4 -PERF_PAPC_PASX_SECOND_DEAD = 5 -PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 -PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 -PERF_PAPC_PA_INPUT_PRIM = 8 -PERF_PAPC_PA_INPUT_NULL_PRIM = 9 -PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 -PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 -PERF_PAPC_CLPR_CULL_PRIM = 14 -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 -PERF_PAPC_CLPR_VV_CULL_PRIM = 16 -PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 -PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 -PERF_PAPC_CLSM_NULL_PRIM = 39 -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 -PERF_PAPC_SU_INPUT_PRIM = 49 -PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 -PERF_PAPC_SU_INPUT_NULL_PRIM = 51 -PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 -PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 -PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 -PERF_PAPC_SU_OUTPUT_PRIM = 61 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 -PERF_PAPC_PASX_REQ_IDLE = 77 -PERF_PAPC_PASX_REQ_BUSY = 78 -PERF_PAPC_PASX_REQ_STALLED = 79 -PERF_PAPC_PASX_REC_IDLE = 80 -PERF_PAPC_PASX_REC_BUSY = 81 -PERF_PAPC_PASX_REC_STARVED_SX = 82 -PERF_PAPC_PASX_REC_STALLED = 83 -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 -PERF_PAPC_CCGSM_IDLE = 86 -PERF_PAPC_CCGSM_BUSY = 87 -PERF_PAPC_CCGSM_STALLED = 88 -PERF_PAPC_CLPRIM_IDLE = 89 -PERF_PAPC_CLPRIM_BUSY = 90 -PERF_PAPC_CLPRIM_STALLED = 91 -PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 -PERF_PAPC_CLIPSM_IDLE = 93 -PERF_PAPC_CLIPSM_BUSY = 94 -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 -PERF_PAPC_CLIPGA_IDLE = 100 -PERF_PAPC_CLIPGA_BUSY = 101 -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 -PERF_PAPC_CLIPGA_STALLED = 103 -PERF_PAPC_CLIP_IDLE = 104 -PERF_PAPC_CLIP_BUSY = 105 -PERF_PAPC_SU_IDLE = 106 -PERF_PAPC_SU_BUSY = 107 -PERF_PAPC_SU_STARVED_CLIP = 108 -PERF_PAPC_SU_STALLED_SC = 109 -PERF_PAPC_CL_DYN_SCLK_VLD = 110 -PERF_PAPC_SU_DYN_SCLK_VLD = 111 -PERF_PAPC_PA_REG_SCLK_VLD = 112 -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 -PERF_PAPC_PASX_SE0_REQ = 114 -PERF_PAPC_PASX_SE1_REQ = 115 -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 -PERF_PAPC_SU_SE0_STALLED_SC = 131 -PERF_PAPC_SU_SE1_STALLED_SC = 132 -PERF_PAPC_SU_SE01_STALLED_SC = 133 -PERF_PAPC_CLSM_CLIPPING_PRIM = 134 -PERF_PAPC_SU_CULLED_PRIM = 135 -PERF_PAPC_SU_OUTPUT_EOPG = 136 -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 -PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 -PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 -PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 -PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 -PERF_PAPC_SU_SE2_STALLED_SC = 151 -PERF_PAPC_SU_SE3_STALLED_SC = 152 -SU_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SC_PERFCNT_SEL' -SC_PERFCNT_SEL__enumvalues = { - 0: 'SC_SRPS_WINDOW_VALID', - 1: 'SC_PSSW_WINDOW_VALID', - 2: 'SC_TPQZ_WINDOW_VALID', - 3: 'SC_QZQP_WINDOW_VALID', - 4: 'SC_TRPK_WINDOW_VALID', - 5: 'SC_SRPS_WINDOW_VALID_BUSY', - 6: 'SC_PSSW_WINDOW_VALID_BUSY', - 7: 'SC_TPQZ_WINDOW_VALID_BUSY', - 8: 'SC_QZQP_WINDOW_VALID_BUSY', - 9: 'SC_TRPK_WINDOW_VALID_BUSY', - 10: 'SC_STARVED_BY_PA', - 11: 'SC_STALLED_BY_PRIMFIFO', - 12: 'SC_STALLED_BY_DB_TILE', - 13: 'SC_STARVED_BY_DB_TILE', - 14: 'SC_STALLED_BY_TILEORDERFIFO', - 15: 'SC_STALLED_BY_TILEFIFO', - 16: 'SC_STALLED_BY_DB_QUAD', - 17: 'SC_STARVED_BY_DB_QUAD', - 18: 'SC_STALLED_BY_QUADFIFO', - 19: 'SC_STALLED_BY_BCI', - 20: 'SC_STALLED_BY_SPI', - 21: 'SC_SCISSOR_DISCARD', - 22: 'SC_BB_DISCARD', - 23: 'SC_SUPERTILE_COUNT', - 24: 'SC_SUPERTILE_PER_PRIM_H0', - 25: 'SC_SUPERTILE_PER_PRIM_H1', - 26: 'SC_SUPERTILE_PER_PRIM_H2', - 27: 'SC_SUPERTILE_PER_PRIM_H3', - 28: 'SC_SUPERTILE_PER_PRIM_H4', - 29: 'SC_SUPERTILE_PER_PRIM_H5', - 30: 'SC_SUPERTILE_PER_PRIM_H6', - 31: 'SC_SUPERTILE_PER_PRIM_H7', - 32: 'SC_SUPERTILE_PER_PRIM_H8', - 33: 'SC_SUPERTILE_PER_PRIM_H9', - 34: 'SC_SUPERTILE_PER_PRIM_H10', - 35: 'SC_SUPERTILE_PER_PRIM_H11', - 36: 'SC_SUPERTILE_PER_PRIM_H12', - 37: 'SC_SUPERTILE_PER_PRIM_H13', - 38: 'SC_SUPERTILE_PER_PRIM_H14', - 39: 'SC_SUPERTILE_PER_PRIM_H15', - 40: 'SC_SUPERTILE_PER_PRIM_H16', - 41: 'SC_TILE_PER_PRIM_H0', - 42: 'SC_TILE_PER_PRIM_H1', - 43: 'SC_TILE_PER_PRIM_H2', - 44: 'SC_TILE_PER_PRIM_H3', - 45: 'SC_TILE_PER_PRIM_H4', - 46: 'SC_TILE_PER_PRIM_H5', - 47: 'SC_TILE_PER_PRIM_H6', - 48: 'SC_TILE_PER_PRIM_H7', - 49: 'SC_TILE_PER_PRIM_H8', - 50: 'SC_TILE_PER_PRIM_H9', - 51: 'SC_TILE_PER_PRIM_H10', - 52: 'SC_TILE_PER_PRIM_H11', - 53: 'SC_TILE_PER_PRIM_H12', - 54: 'SC_TILE_PER_PRIM_H13', - 55: 'SC_TILE_PER_PRIM_H14', - 56: 'SC_TILE_PER_PRIM_H15', - 57: 'SC_TILE_PER_PRIM_H16', - 58: 'SC_TILE_PER_SUPERTILE_H0', - 59: 'SC_TILE_PER_SUPERTILE_H1', - 60: 'SC_TILE_PER_SUPERTILE_H2', - 61: 'SC_TILE_PER_SUPERTILE_H3', - 62: 'SC_TILE_PER_SUPERTILE_H4', - 63: 'SC_TILE_PER_SUPERTILE_H5', - 64: 'SC_TILE_PER_SUPERTILE_H6', - 65: 'SC_TILE_PER_SUPERTILE_H7', - 66: 'SC_TILE_PER_SUPERTILE_H8', - 67: 'SC_TILE_PER_SUPERTILE_H9', - 68: 'SC_TILE_PER_SUPERTILE_H10', - 69: 'SC_TILE_PER_SUPERTILE_H11', - 70: 'SC_TILE_PER_SUPERTILE_H12', - 71: 'SC_TILE_PER_SUPERTILE_H13', - 72: 'SC_TILE_PER_SUPERTILE_H14', - 73: 'SC_TILE_PER_SUPERTILE_H15', - 74: 'SC_TILE_PER_SUPERTILE_H16', - 75: 'SC_TILE_PICKED_H1', - 76: 'SC_TILE_PICKED_H2', - 77: 'SC_TILE_PICKED_H3', - 78: 'SC_TILE_PICKED_H4', - 79: 'SC_QZ0_MULTI_GPU_TILE_DISCARD', - 80: 'SC_QZ1_MULTI_GPU_TILE_DISCARD', - 81: 'SC_QZ2_MULTI_GPU_TILE_DISCARD', - 82: 'SC_QZ3_MULTI_GPU_TILE_DISCARD', - 83: 'SC_QZ0_TILE_COUNT', - 84: 'SC_QZ1_TILE_COUNT', - 85: 'SC_QZ2_TILE_COUNT', - 86: 'SC_QZ3_TILE_COUNT', - 87: 'SC_QZ0_TILE_COVERED_COUNT', - 88: 'SC_QZ1_TILE_COVERED_COUNT', - 89: 'SC_QZ2_TILE_COVERED_COUNT', - 90: 'SC_QZ3_TILE_COVERED_COUNT', - 91: 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 92: 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 93: 'SC_QZ2_TILE_NOT_COVERED_COUNT', - 94: 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 95: 'SC_QZ0_QUAD_PER_TILE_H0', - 96: 'SC_QZ0_QUAD_PER_TILE_H1', - 97: 'SC_QZ0_QUAD_PER_TILE_H2', - 98: 'SC_QZ0_QUAD_PER_TILE_H3', - 99: 'SC_QZ0_QUAD_PER_TILE_H4', - 100: 'SC_QZ0_QUAD_PER_TILE_H5', - 101: 'SC_QZ0_QUAD_PER_TILE_H6', - 102: 'SC_QZ0_QUAD_PER_TILE_H7', - 103: 'SC_QZ0_QUAD_PER_TILE_H8', - 104: 'SC_QZ0_QUAD_PER_TILE_H9', - 105: 'SC_QZ0_QUAD_PER_TILE_H10', - 106: 'SC_QZ0_QUAD_PER_TILE_H11', - 107: 'SC_QZ0_QUAD_PER_TILE_H12', - 108: 'SC_QZ0_QUAD_PER_TILE_H13', - 109: 'SC_QZ0_QUAD_PER_TILE_H14', - 110: 'SC_QZ0_QUAD_PER_TILE_H15', - 111: 'SC_QZ0_QUAD_PER_TILE_H16', - 112: 'SC_QZ1_QUAD_PER_TILE_H0', - 113: 'SC_QZ1_QUAD_PER_TILE_H1', - 114: 'SC_QZ1_QUAD_PER_TILE_H2', - 115: 'SC_QZ1_QUAD_PER_TILE_H3', - 116: 'SC_QZ1_QUAD_PER_TILE_H4', - 117: 'SC_QZ1_QUAD_PER_TILE_H5', - 118: 'SC_QZ1_QUAD_PER_TILE_H6', - 119: 'SC_QZ1_QUAD_PER_TILE_H7', - 120: 'SC_QZ1_QUAD_PER_TILE_H8', - 121: 'SC_QZ1_QUAD_PER_TILE_H9', - 122: 'SC_QZ1_QUAD_PER_TILE_H10', - 123: 'SC_QZ1_QUAD_PER_TILE_H11', - 124: 'SC_QZ1_QUAD_PER_TILE_H12', - 125: 'SC_QZ1_QUAD_PER_TILE_H13', - 126: 'SC_QZ1_QUAD_PER_TILE_H14', - 127: 'SC_QZ1_QUAD_PER_TILE_H15', - 128: 'SC_QZ1_QUAD_PER_TILE_H16', - 129: 'SC_QZ2_QUAD_PER_TILE_H0', - 130: 'SC_QZ2_QUAD_PER_TILE_H1', - 131: 'SC_QZ2_QUAD_PER_TILE_H2', - 132: 'SC_QZ2_QUAD_PER_TILE_H3', - 133: 'SC_QZ2_QUAD_PER_TILE_H4', - 134: 'SC_QZ2_QUAD_PER_TILE_H5', - 135: 'SC_QZ2_QUAD_PER_TILE_H6', - 136: 'SC_QZ2_QUAD_PER_TILE_H7', - 137: 'SC_QZ2_QUAD_PER_TILE_H8', - 138: 'SC_QZ2_QUAD_PER_TILE_H9', - 139: 'SC_QZ2_QUAD_PER_TILE_H10', - 140: 'SC_QZ2_QUAD_PER_TILE_H11', - 141: 'SC_QZ2_QUAD_PER_TILE_H12', - 142: 'SC_QZ2_QUAD_PER_TILE_H13', - 143: 'SC_QZ2_QUAD_PER_TILE_H14', - 144: 'SC_QZ2_QUAD_PER_TILE_H15', - 145: 'SC_QZ2_QUAD_PER_TILE_H16', - 146: 'SC_QZ3_QUAD_PER_TILE_H0', - 147: 'SC_QZ3_QUAD_PER_TILE_H1', - 148: 'SC_QZ3_QUAD_PER_TILE_H2', - 149: 'SC_QZ3_QUAD_PER_TILE_H3', - 150: 'SC_QZ3_QUAD_PER_TILE_H4', - 151: 'SC_QZ3_QUAD_PER_TILE_H5', - 152: 'SC_QZ3_QUAD_PER_TILE_H6', - 153: 'SC_QZ3_QUAD_PER_TILE_H7', - 154: 'SC_QZ3_QUAD_PER_TILE_H8', - 155: 'SC_QZ3_QUAD_PER_TILE_H9', - 156: 'SC_QZ3_QUAD_PER_TILE_H10', - 157: 'SC_QZ3_QUAD_PER_TILE_H11', - 158: 'SC_QZ3_QUAD_PER_TILE_H12', - 159: 'SC_QZ3_QUAD_PER_TILE_H13', - 160: 'SC_QZ3_QUAD_PER_TILE_H14', - 161: 'SC_QZ3_QUAD_PER_TILE_H15', - 162: 'SC_QZ3_QUAD_PER_TILE_H16', - 163: 'SC_QZ0_QUAD_COUNT', - 164: 'SC_QZ1_QUAD_COUNT', - 165: 'SC_QZ2_QUAD_COUNT', - 166: 'SC_QZ3_QUAD_COUNT', - 167: 'SC_P0_HIZ_TILE_COUNT', - 168: 'SC_P1_HIZ_TILE_COUNT', - 169: 'SC_P2_HIZ_TILE_COUNT', - 170: 'SC_P3_HIZ_TILE_COUNT', - 171: 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 172: 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 173: 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 174: 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 175: 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 176: 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 177: 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 178: 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 179: 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 180: 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 181: 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 182: 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 183: 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 184: 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 185: 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 186: 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 187: 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 188: 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 189: 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 190: 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 191: 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 192: 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 193: 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 194: 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 195: 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 196: 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 197: 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 198: 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 199: 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 200: 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 201: 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 202: 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 203: 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 204: 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 205: 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 206: 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 207: 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 208: 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 209: 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 210: 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 211: 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 212: 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 213: 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 214: 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 215: 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 216: 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 217: 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 218: 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 219: 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 220: 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 221: 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 222: 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 223: 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 224: 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 225: 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 226: 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 227: 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 228: 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 229: 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 230: 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 231: 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 232: 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 233: 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 234: 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 235: 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 236: 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 237: 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 238: 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 239: 'SC_P0_HIZ_QUAD_COUNT', - 240: 'SC_P1_HIZ_QUAD_COUNT', - 241: 'SC_P2_HIZ_QUAD_COUNT', - 242: 'SC_P3_HIZ_QUAD_COUNT', - 243: 'SC_P0_DETAIL_QUAD_COUNT', - 244: 'SC_P1_DETAIL_QUAD_COUNT', - 245: 'SC_P2_DETAIL_QUAD_COUNT', - 246: 'SC_P3_DETAIL_QUAD_COUNT', - 247: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 248: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 249: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 250: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 251: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 252: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 253: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 254: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 255: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 256: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 257: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 258: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 259: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 260: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 261: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 262: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 263: 'SC_EARLYZ_QUAD_COUNT', - 264: 'SC_EARLYZ_QUAD_WITH_1_PIX', - 265: 'SC_EARLYZ_QUAD_WITH_2_PIX', - 266: 'SC_EARLYZ_QUAD_WITH_3_PIX', - 267: 'SC_EARLYZ_QUAD_WITH_4_PIX', - 268: 'SC_PKR_QUAD_PER_ROW_H1', - 269: 'SC_PKR_QUAD_PER_ROW_H2', - 270: 'SC_PKR_4X2_QUAD_SPLIT', - 271: 'SC_PKR_4X2_FILL_QUAD', - 272: 'SC_PKR_END_OF_VECTOR', - 273: 'SC_PKR_CONTROL_XFER', - 274: 'SC_PKR_DBHANG_FORCE_EOV', - 275: 'SC_REG_SCLK_BUSY', - 276: 'SC_GRP0_DYN_SCLK_BUSY', - 277: 'SC_GRP1_DYN_SCLK_BUSY', - 278: 'SC_GRP2_DYN_SCLK_BUSY', - 279: 'SC_GRP3_DYN_SCLK_BUSY', - 280: 'SC_GRP4_DYN_SCLK_BUSY', - 281: 'SC_PA0_SC_DATA_FIFO_RD', - 282: 'SC_PA0_SC_DATA_FIFO_WE', - 283: 'SC_PA1_SC_DATA_FIFO_RD', - 284: 'SC_PA1_SC_DATA_FIFO_WE', - 285: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 286: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', - 287: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 288: 'SC_PS_ARB_STALLED_FROM_BELOW', - 289: 'SC_PS_ARB_STARVED_FROM_ABOVE', - 290: 'SC_PS_ARB_SC_BUSY', - 291: 'SC_PS_ARB_PA_SC_BUSY', - 292: 'SC_PA2_SC_DATA_FIFO_RD', - 293: 'SC_PA2_SC_DATA_FIFO_WE', - 294: 'SC_PA3_SC_DATA_FIFO_RD', - 295: 'SC_PA3_SC_DATA_FIFO_WE', - 296: 'SC_PA_SC_DEALLOC_0_0_WE', - 297: 'SC_PA_SC_DEALLOC_0_1_WE', - 298: 'SC_PA_SC_DEALLOC_1_0_WE', - 299: 'SC_PA_SC_DEALLOC_1_1_WE', - 300: 'SC_PA_SC_DEALLOC_2_0_WE', - 301: 'SC_PA_SC_DEALLOC_2_1_WE', - 302: 'SC_PA_SC_DEALLOC_3_0_WE', - 303: 'SC_PA_SC_DEALLOC_3_1_WE', - 304: 'SC_PA0_SC_EOP_WE', - 305: 'SC_PA0_SC_EOPG_WE', - 306: 'SC_PA0_SC_EVENT_WE', - 307: 'SC_PA1_SC_EOP_WE', - 308: 'SC_PA1_SC_EOPG_WE', - 309: 'SC_PA1_SC_EVENT_WE', - 310: 'SC_PA2_SC_EOP_WE', - 311: 'SC_PA2_SC_EOPG_WE', - 312: 'SC_PA2_SC_EVENT_WE', - 313: 'SC_PA3_SC_EOP_WE', - 314: 'SC_PA3_SC_EOPG_WE', - 315: 'SC_PA3_SC_EVENT_WE', - 316: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 317: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 318: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 319: 'SC_PS_ARB_EOP_POP_SYNC_POP', - 320: 'SC_PS_ARB_EVENT_SYNC_POP', - 321: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', - 322: 'SC_PA0_SC_FPOV_WE', - 323: 'SC_PA1_SC_FPOV_WE', - 324: 'SC_PA2_SC_FPOV_WE', - 325: 'SC_PA3_SC_FPOV_WE', - 326: 'SC_PA0_SC_LPOV_WE', - 327: 'SC_PA1_SC_LPOV_WE', - 328: 'SC_PA2_SC_LPOV_WE', - 329: 'SC_PA3_SC_LPOV_WE', - 330: 'SC_SC_SPI_DEALLOC_0_0', - 331: 'SC_SC_SPI_DEALLOC_0_1', - 332: 'SC_SC_SPI_DEALLOC_0_2', - 333: 'SC_SC_SPI_DEALLOC_1_0', - 334: 'SC_SC_SPI_DEALLOC_1_1', - 335: 'SC_SC_SPI_DEALLOC_1_2', - 336: 'SC_SC_SPI_DEALLOC_2_0', - 337: 'SC_SC_SPI_DEALLOC_2_1', - 338: 'SC_SC_SPI_DEALLOC_2_2', - 339: 'SC_SC_SPI_DEALLOC_3_0', - 340: 'SC_SC_SPI_DEALLOC_3_1', - 341: 'SC_SC_SPI_DEALLOC_3_2', - 342: 'SC_SC_SPI_FPOV_0', - 343: 'SC_SC_SPI_FPOV_1', - 344: 'SC_SC_SPI_FPOV_2', - 345: 'SC_SC_SPI_FPOV_3', - 346: 'SC_SC_SPI_EVENT', - 347: 'SC_PS_TS_EVENT_FIFO_PUSH', - 348: 'SC_PS_TS_EVENT_FIFO_POP', - 349: 'SC_PS_CTX_DONE_FIFO_PUSH', - 350: 'SC_PS_CTX_DONE_FIFO_POP', - 351: 'SC_MULTICYCLE_BUBBLE_FREEZE', - 352: 'SC_EOP_SYNC_WINDOW', - 353: 'SC_PA0_SC_NULL_WE', - 354: 'SC_PA0_SC_NULL_DEALLOC_WE', - 355: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', - 356: 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 357: 'SC_PA0_SC_DEALLOC_0_RD', - 358: 'SC_PA0_SC_DEALLOC_1_RD', - 359: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', - 360: 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 361: 'SC_PA1_SC_DEALLOC_0_RD', - 362: 'SC_PA1_SC_DEALLOC_1_RD', - 363: 'SC_PA1_SC_NULL_WE', - 364: 'SC_PA1_SC_NULL_DEALLOC_WE', - 365: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', - 366: 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 367: 'SC_PA2_SC_DEALLOC_0_RD', - 368: 'SC_PA2_SC_DEALLOC_1_RD', - 369: 'SC_PA2_SC_NULL_WE', - 370: 'SC_PA2_SC_NULL_DEALLOC_WE', - 371: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', - 372: 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 373: 'SC_PA3_SC_DEALLOC_0_RD', - 374: 'SC_PA3_SC_DEALLOC_1_RD', - 375: 'SC_PA3_SC_NULL_WE', - 376: 'SC_PA3_SC_NULL_DEALLOC_WE', - 377: 'SC_PS_PA0_SC_FIFO_EMPTY', - 378: 'SC_PS_PA0_SC_FIFO_FULL', - 379: 'SC_PA0_PS_DATA_SEND', - 380: 'SC_PS_PA1_SC_FIFO_EMPTY', - 381: 'SC_PS_PA1_SC_FIFO_FULL', - 382: 'SC_PA1_PS_DATA_SEND', - 383: 'SC_PS_PA2_SC_FIFO_EMPTY', - 384: 'SC_PS_PA2_SC_FIFO_FULL', - 385: 'SC_PA2_PS_DATA_SEND', - 386: 'SC_PS_PA3_SC_FIFO_EMPTY', - 387: 'SC_PS_PA3_SC_FIFO_FULL', - 388: 'SC_PA3_PS_DATA_SEND', - 389: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', - 390: 'SC_BUSY_CNT_NOT_ZERO', - 391: 'SC_BM_BUSY', - 392: 'SC_BACKEND_BUSY', - 393: 'SC_SCF_SCB_INTERFACE_BUSY', - 394: 'SC_SCB_BUSY', - 395: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 396: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 397: 'SC_PBB_BIN_HIST_NUM_PRIMS', - 398: 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 399: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 400: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 401: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 402: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 403: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 404: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 405: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 406: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 407: 'SC_PBB_BUSY', - 408: 'SC_PBB_BUSY_AND_RTR', - 409: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 410: 'SC_PBB_NUM_BINS', - 411: 'SC_PBB_END_OF_BIN', - 412: 'SC_PBB_END_OF_BATCH', - 413: 'SC_PBB_PRIMBIN_PROCESSED', - 414: 'SC_PBB_PRIM_ADDED_TO_BATCH', - 415: 'SC_PBB_NONBINNED_PRIM', - 416: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', - 417: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 418: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 419: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 420: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 421: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 422: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 423: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 424: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 425: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 426: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 427: 'SC_POPS_INTRA_WAVE_OVERLAPS', - 428: 'SC_POPS_FORCE_EOV', - 429: 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', - 430: 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', -} -SC_SRPS_WINDOW_VALID = 0 -SC_PSSW_WINDOW_VALID = 1 -SC_TPQZ_WINDOW_VALID = 2 -SC_QZQP_WINDOW_VALID = 3 -SC_TRPK_WINDOW_VALID = 4 -SC_SRPS_WINDOW_VALID_BUSY = 5 -SC_PSSW_WINDOW_VALID_BUSY = 6 -SC_TPQZ_WINDOW_VALID_BUSY = 7 -SC_QZQP_WINDOW_VALID_BUSY = 8 -SC_TRPK_WINDOW_VALID_BUSY = 9 -SC_STARVED_BY_PA = 10 -SC_STALLED_BY_PRIMFIFO = 11 -SC_STALLED_BY_DB_TILE = 12 -SC_STARVED_BY_DB_TILE = 13 -SC_STALLED_BY_TILEORDERFIFO = 14 -SC_STALLED_BY_TILEFIFO = 15 -SC_STALLED_BY_DB_QUAD = 16 -SC_STARVED_BY_DB_QUAD = 17 -SC_STALLED_BY_QUADFIFO = 18 -SC_STALLED_BY_BCI = 19 -SC_STALLED_BY_SPI = 20 -SC_SCISSOR_DISCARD = 21 -SC_BB_DISCARD = 22 -SC_SUPERTILE_COUNT = 23 -SC_SUPERTILE_PER_PRIM_H0 = 24 -SC_SUPERTILE_PER_PRIM_H1 = 25 -SC_SUPERTILE_PER_PRIM_H2 = 26 -SC_SUPERTILE_PER_PRIM_H3 = 27 -SC_SUPERTILE_PER_PRIM_H4 = 28 -SC_SUPERTILE_PER_PRIM_H5 = 29 -SC_SUPERTILE_PER_PRIM_H6 = 30 -SC_SUPERTILE_PER_PRIM_H7 = 31 -SC_SUPERTILE_PER_PRIM_H8 = 32 -SC_SUPERTILE_PER_PRIM_H9 = 33 -SC_SUPERTILE_PER_PRIM_H10 = 34 -SC_SUPERTILE_PER_PRIM_H11 = 35 -SC_SUPERTILE_PER_PRIM_H12 = 36 -SC_SUPERTILE_PER_PRIM_H13 = 37 -SC_SUPERTILE_PER_PRIM_H14 = 38 -SC_SUPERTILE_PER_PRIM_H15 = 39 -SC_SUPERTILE_PER_PRIM_H16 = 40 -SC_TILE_PER_PRIM_H0 = 41 -SC_TILE_PER_PRIM_H1 = 42 -SC_TILE_PER_PRIM_H2 = 43 -SC_TILE_PER_PRIM_H3 = 44 -SC_TILE_PER_PRIM_H4 = 45 -SC_TILE_PER_PRIM_H5 = 46 -SC_TILE_PER_PRIM_H6 = 47 -SC_TILE_PER_PRIM_H7 = 48 -SC_TILE_PER_PRIM_H8 = 49 -SC_TILE_PER_PRIM_H9 = 50 -SC_TILE_PER_PRIM_H10 = 51 -SC_TILE_PER_PRIM_H11 = 52 -SC_TILE_PER_PRIM_H12 = 53 -SC_TILE_PER_PRIM_H13 = 54 -SC_TILE_PER_PRIM_H14 = 55 -SC_TILE_PER_PRIM_H15 = 56 -SC_TILE_PER_PRIM_H16 = 57 -SC_TILE_PER_SUPERTILE_H0 = 58 -SC_TILE_PER_SUPERTILE_H1 = 59 -SC_TILE_PER_SUPERTILE_H2 = 60 -SC_TILE_PER_SUPERTILE_H3 = 61 -SC_TILE_PER_SUPERTILE_H4 = 62 -SC_TILE_PER_SUPERTILE_H5 = 63 -SC_TILE_PER_SUPERTILE_H6 = 64 -SC_TILE_PER_SUPERTILE_H7 = 65 -SC_TILE_PER_SUPERTILE_H8 = 66 -SC_TILE_PER_SUPERTILE_H9 = 67 -SC_TILE_PER_SUPERTILE_H10 = 68 -SC_TILE_PER_SUPERTILE_H11 = 69 -SC_TILE_PER_SUPERTILE_H12 = 70 -SC_TILE_PER_SUPERTILE_H13 = 71 -SC_TILE_PER_SUPERTILE_H14 = 72 -SC_TILE_PER_SUPERTILE_H15 = 73 -SC_TILE_PER_SUPERTILE_H16 = 74 -SC_TILE_PICKED_H1 = 75 -SC_TILE_PICKED_H2 = 76 -SC_TILE_PICKED_H3 = 77 -SC_TILE_PICKED_H4 = 78 -SC_QZ0_MULTI_GPU_TILE_DISCARD = 79 -SC_QZ1_MULTI_GPU_TILE_DISCARD = 80 -SC_QZ2_MULTI_GPU_TILE_DISCARD = 81 -SC_QZ3_MULTI_GPU_TILE_DISCARD = 82 -SC_QZ0_TILE_COUNT = 83 -SC_QZ1_TILE_COUNT = 84 -SC_QZ2_TILE_COUNT = 85 -SC_QZ3_TILE_COUNT = 86 -SC_QZ0_TILE_COVERED_COUNT = 87 -SC_QZ1_TILE_COVERED_COUNT = 88 -SC_QZ2_TILE_COVERED_COUNT = 89 -SC_QZ3_TILE_COVERED_COUNT = 90 -SC_QZ0_TILE_NOT_COVERED_COUNT = 91 -SC_QZ1_TILE_NOT_COVERED_COUNT = 92 -SC_QZ2_TILE_NOT_COVERED_COUNT = 93 -SC_QZ3_TILE_NOT_COVERED_COUNT = 94 -SC_QZ0_QUAD_PER_TILE_H0 = 95 -SC_QZ0_QUAD_PER_TILE_H1 = 96 -SC_QZ0_QUAD_PER_TILE_H2 = 97 -SC_QZ0_QUAD_PER_TILE_H3 = 98 -SC_QZ0_QUAD_PER_TILE_H4 = 99 -SC_QZ0_QUAD_PER_TILE_H5 = 100 -SC_QZ0_QUAD_PER_TILE_H6 = 101 -SC_QZ0_QUAD_PER_TILE_H7 = 102 -SC_QZ0_QUAD_PER_TILE_H8 = 103 -SC_QZ0_QUAD_PER_TILE_H9 = 104 -SC_QZ0_QUAD_PER_TILE_H10 = 105 -SC_QZ0_QUAD_PER_TILE_H11 = 106 -SC_QZ0_QUAD_PER_TILE_H12 = 107 -SC_QZ0_QUAD_PER_TILE_H13 = 108 -SC_QZ0_QUAD_PER_TILE_H14 = 109 -SC_QZ0_QUAD_PER_TILE_H15 = 110 -SC_QZ0_QUAD_PER_TILE_H16 = 111 -SC_QZ1_QUAD_PER_TILE_H0 = 112 -SC_QZ1_QUAD_PER_TILE_H1 = 113 -SC_QZ1_QUAD_PER_TILE_H2 = 114 -SC_QZ1_QUAD_PER_TILE_H3 = 115 -SC_QZ1_QUAD_PER_TILE_H4 = 116 -SC_QZ1_QUAD_PER_TILE_H5 = 117 -SC_QZ1_QUAD_PER_TILE_H6 = 118 -SC_QZ1_QUAD_PER_TILE_H7 = 119 -SC_QZ1_QUAD_PER_TILE_H8 = 120 -SC_QZ1_QUAD_PER_TILE_H9 = 121 -SC_QZ1_QUAD_PER_TILE_H10 = 122 -SC_QZ1_QUAD_PER_TILE_H11 = 123 -SC_QZ1_QUAD_PER_TILE_H12 = 124 -SC_QZ1_QUAD_PER_TILE_H13 = 125 -SC_QZ1_QUAD_PER_TILE_H14 = 126 -SC_QZ1_QUAD_PER_TILE_H15 = 127 -SC_QZ1_QUAD_PER_TILE_H16 = 128 -SC_QZ2_QUAD_PER_TILE_H0 = 129 -SC_QZ2_QUAD_PER_TILE_H1 = 130 -SC_QZ2_QUAD_PER_TILE_H2 = 131 -SC_QZ2_QUAD_PER_TILE_H3 = 132 -SC_QZ2_QUAD_PER_TILE_H4 = 133 -SC_QZ2_QUAD_PER_TILE_H5 = 134 -SC_QZ2_QUAD_PER_TILE_H6 = 135 -SC_QZ2_QUAD_PER_TILE_H7 = 136 -SC_QZ2_QUAD_PER_TILE_H8 = 137 -SC_QZ2_QUAD_PER_TILE_H9 = 138 -SC_QZ2_QUAD_PER_TILE_H10 = 139 -SC_QZ2_QUAD_PER_TILE_H11 = 140 -SC_QZ2_QUAD_PER_TILE_H12 = 141 -SC_QZ2_QUAD_PER_TILE_H13 = 142 -SC_QZ2_QUAD_PER_TILE_H14 = 143 -SC_QZ2_QUAD_PER_TILE_H15 = 144 -SC_QZ2_QUAD_PER_TILE_H16 = 145 -SC_QZ3_QUAD_PER_TILE_H0 = 146 -SC_QZ3_QUAD_PER_TILE_H1 = 147 -SC_QZ3_QUAD_PER_TILE_H2 = 148 -SC_QZ3_QUAD_PER_TILE_H3 = 149 -SC_QZ3_QUAD_PER_TILE_H4 = 150 -SC_QZ3_QUAD_PER_TILE_H5 = 151 -SC_QZ3_QUAD_PER_TILE_H6 = 152 -SC_QZ3_QUAD_PER_TILE_H7 = 153 -SC_QZ3_QUAD_PER_TILE_H8 = 154 -SC_QZ3_QUAD_PER_TILE_H9 = 155 -SC_QZ3_QUAD_PER_TILE_H10 = 156 -SC_QZ3_QUAD_PER_TILE_H11 = 157 -SC_QZ3_QUAD_PER_TILE_H12 = 158 -SC_QZ3_QUAD_PER_TILE_H13 = 159 -SC_QZ3_QUAD_PER_TILE_H14 = 160 -SC_QZ3_QUAD_PER_TILE_H15 = 161 -SC_QZ3_QUAD_PER_TILE_H16 = 162 -SC_QZ0_QUAD_COUNT = 163 -SC_QZ1_QUAD_COUNT = 164 -SC_QZ2_QUAD_COUNT = 165 -SC_QZ3_QUAD_COUNT = 166 -SC_P0_HIZ_TILE_COUNT = 167 -SC_P1_HIZ_TILE_COUNT = 168 -SC_P2_HIZ_TILE_COUNT = 169 -SC_P3_HIZ_TILE_COUNT = 170 -SC_P0_HIZ_QUAD_PER_TILE_H0 = 171 -SC_P0_HIZ_QUAD_PER_TILE_H1 = 172 -SC_P0_HIZ_QUAD_PER_TILE_H2 = 173 -SC_P0_HIZ_QUAD_PER_TILE_H3 = 174 -SC_P0_HIZ_QUAD_PER_TILE_H4 = 175 -SC_P0_HIZ_QUAD_PER_TILE_H5 = 176 -SC_P0_HIZ_QUAD_PER_TILE_H6 = 177 -SC_P0_HIZ_QUAD_PER_TILE_H7 = 178 -SC_P0_HIZ_QUAD_PER_TILE_H8 = 179 -SC_P0_HIZ_QUAD_PER_TILE_H9 = 180 -SC_P0_HIZ_QUAD_PER_TILE_H10 = 181 -SC_P0_HIZ_QUAD_PER_TILE_H11 = 182 -SC_P0_HIZ_QUAD_PER_TILE_H12 = 183 -SC_P0_HIZ_QUAD_PER_TILE_H13 = 184 -SC_P0_HIZ_QUAD_PER_TILE_H14 = 185 -SC_P0_HIZ_QUAD_PER_TILE_H15 = 186 -SC_P0_HIZ_QUAD_PER_TILE_H16 = 187 -SC_P1_HIZ_QUAD_PER_TILE_H0 = 188 -SC_P1_HIZ_QUAD_PER_TILE_H1 = 189 -SC_P1_HIZ_QUAD_PER_TILE_H2 = 190 -SC_P1_HIZ_QUAD_PER_TILE_H3 = 191 -SC_P1_HIZ_QUAD_PER_TILE_H4 = 192 -SC_P1_HIZ_QUAD_PER_TILE_H5 = 193 -SC_P1_HIZ_QUAD_PER_TILE_H6 = 194 -SC_P1_HIZ_QUAD_PER_TILE_H7 = 195 -SC_P1_HIZ_QUAD_PER_TILE_H8 = 196 -SC_P1_HIZ_QUAD_PER_TILE_H9 = 197 -SC_P1_HIZ_QUAD_PER_TILE_H10 = 198 -SC_P1_HIZ_QUAD_PER_TILE_H11 = 199 -SC_P1_HIZ_QUAD_PER_TILE_H12 = 200 -SC_P1_HIZ_QUAD_PER_TILE_H13 = 201 -SC_P1_HIZ_QUAD_PER_TILE_H14 = 202 -SC_P1_HIZ_QUAD_PER_TILE_H15 = 203 -SC_P1_HIZ_QUAD_PER_TILE_H16 = 204 -SC_P2_HIZ_QUAD_PER_TILE_H0 = 205 -SC_P2_HIZ_QUAD_PER_TILE_H1 = 206 -SC_P2_HIZ_QUAD_PER_TILE_H2 = 207 -SC_P2_HIZ_QUAD_PER_TILE_H3 = 208 -SC_P2_HIZ_QUAD_PER_TILE_H4 = 209 -SC_P2_HIZ_QUAD_PER_TILE_H5 = 210 -SC_P2_HIZ_QUAD_PER_TILE_H6 = 211 -SC_P2_HIZ_QUAD_PER_TILE_H7 = 212 -SC_P2_HIZ_QUAD_PER_TILE_H8 = 213 -SC_P2_HIZ_QUAD_PER_TILE_H9 = 214 -SC_P2_HIZ_QUAD_PER_TILE_H10 = 215 -SC_P2_HIZ_QUAD_PER_TILE_H11 = 216 -SC_P2_HIZ_QUAD_PER_TILE_H12 = 217 -SC_P2_HIZ_QUAD_PER_TILE_H13 = 218 -SC_P2_HIZ_QUAD_PER_TILE_H14 = 219 -SC_P2_HIZ_QUAD_PER_TILE_H15 = 220 -SC_P2_HIZ_QUAD_PER_TILE_H16 = 221 -SC_P3_HIZ_QUAD_PER_TILE_H0 = 222 -SC_P3_HIZ_QUAD_PER_TILE_H1 = 223 -SC_P3_HIZ_QUAD_PER_TILE_H2 = 224 -SC_P3_HIZ_QUAD_PER_TILE_H3 = 225 -SC_P3_HIZ_QUAD_PER_TILE_H4 = 226 -SC_P3_HIZ_QUAD_PER_TILE_H5 = 227 -SC_P3_HIZ_QUAD_PER_TILE_H6 = 228 -SC_P3_HIZ_QUAD_PER_TILE_H7 = 229 -SC_P3_HIZ_QUAD_PER_TILE_H8 = 230 -SC_P3_HIZ_QUAD_PER_TILE_H9 = 231 -SC_P3_HIZ_QUAD_PER_TILE_H10 = 232 -SC_P3_HIZ_QUAD_PER_TILE_H11 = 233 -SC_P3_HIZ_QUAD_PER_TILE_H12 = 234 -SC_P3_HIZ_QUAD_PER_TILE_H13 = 235 -SC_P3_HIZ_QUAD_PER_TILE_H14 = 236 -SC_P3_HIZ_QUAD_PER_TILE_H15 = 237 -SC_P3_HIZ_QUAD_PER_TILE_H16 = 238 -SC_P0_HIZ_QUAD_COUNT = 239 -SC_P1_HIZ_QUAD_COUNT = 240 -SC_P2_HIZ_QUAD_COUNT = 241 -SC_P3_HIZ_QUAD_COUNT = 242 -SC_P0_DETAIL_QUAD_COUNT = 243 -SC_P1_DETAIL_QUAD_COUNT = 244 -SC_P2_DETAIL_QUAD_COUNT = 245 -SC_P3_DETAIL_QUAD_COUNT = 246 -SC_P0_DETAIL_QUAD_WITH_1_PIX = 247 -SC_P0_DETAIL_QUAD_WITH_2_PIX = 248 -SC_P0_DETAIL_QUAD_WITH_3_PIX = 249 -SC_P0_DETAIL_QUAD_WITH_4_PIX = 250 -SC_P1_DETAIL_QUAD_WITH_1_PIX = 251 -SC_P1_DETAIL_QUAD_WITH_2_PIX = 252 -SC_P1_DETAIL_QUAD_WITH_3_PIX = 253 -SC_P1_DETAIL_QUAD_WITH_4_PIX = 254 -SC_P2_DETAIL_QUAD_WITH_1_PIX = 255 -SC_P2_DETAIL_QUAD_WITH_2_PIX = 256 -SC_P2_DETAIL_QUAD_WITH_3_PIX = 257 -SC_P2_DETAIL_QUAD_WITH_4_PIX = 258 -SC_P3_DETAIL_QUAD_WITH_1_PIX = 259 -SC_P3_DETAIL_QUAD_WITH_2_PIX = 260 -SC_P3_DETAIL_QUAD_WITH_3_PIX = 261 -SC_P3_DETAIL_QUAD_WITH_4_PIX = 262 -SC_EARLYZ_QUAD_COUNT = 263 -SC_EARLYZ_QUAD_WITH_1_PIX = 264 -SC_EARLYZ_QUAD_WITH_2_PIX = 265 -SC_EARLYZ_QUAD_WITH_3_PIX = 266 -SC_EARLYZ_QUAD_WITH_4_PIX = 267 -SC_PKR_QUAD_PER_ROW_H1 = 268 -SC_PKR_QUAD_PER_ROW_H2 = 269 -SC_PKR_4X2_QUAD_SPLIT = 270 -SC_PKR_4X2_FILL_QUAD = 271 -SC_PKR_END_OF_VECTOR = 272 -SC_PKR_CONTROL_XFER = 273 -SC_PKR_DBHANG_FORCE_EOV = 274 -SC_REG_SCLK_BUSY = 275 -SC_GRP0_DYN_SCLK_BUSY = 276 -SC_GRP1_DYN_SCLK_BUSY = 277 -SC_GRP2_DYN_SCLK_BUSY = 278 -SC_GRP3_DYN_SCLK_BUSY = 279 -SC_GRP4_DYN_SCLK_BUSY = 280 -SC_PA0_SC_DATA_FIFO_RD = 281 -SC_PA0_SC_DATA_FIFO_WE = 282 -SC_PA1_SC_DATA_FIFO_RD = 283 -SC_PA1_SC_DATA_FIFO_WE = 284 -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 285 -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 286 -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 287 -SC_PS_ARB_STALLED_FROM_BELOW = 288 -SC_PS_ARB_STARVED_FROM_ABOVE = 289 -SC_PS_ARB_SC_BUSY = 290 -SC_PS_ARB_PA_SC_BUSY = 291 -SC_PA2_SC_DATA_FIFO_RD = 292 -SC_PA2_SC_DATA_FIFO_WE = 293 -SC_PA3_SC_DATA_FIFO_RD = 294 -SC_PA3_SC_DATA_FIFO_WE = 295 -SC_PA_SC_DEALLOC_0_0_WE = 296 -SC_PA_SC_DEALLOC_0_1_WE = 297 -SC_PA_SC_DEALLOC_1_0_WE = 298 -SC_PA_SC_DEALLOC_1_1_WE = 299 -SC_PA_SC_DEALLOC_2_0_WE = 300 -SC_PA_SC_DEALLOC_2_1_WE = 301 -SC_PA_SC_DEALLOC_3_0_WE = 302 -SC_PA_SC_DEALLOC_3_1_WE = 303 -SC_PA0_SC_EOP_WE = 304 -SC_PA0_SC_EOPG_WE = 305 -SC_PA0_SC_EVENT_WE = 306 -SC_PA1_SC_EOP_WE = 307 -SC_PA1_SC_EOPG_WE = 308 -SC_PA1_SC_EVENT_WE = 309 -SC_PA2_SC_EOP_WE = 310 -SC_PA2_SC_EOPG_WE = 311 -SC_PA2_SC_EVENT_WE = 312 -SC_PA3_SC_EOP_WE = 313 -SC_PA3_SC_EOPG_WE = 314 -SC_PA3_SC_EVENT_WE = 315 -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 316 -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 317 -SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 318 -SC_PS_ARB_EOP_POP_SYNC_POP = 319 -SC_PS_ARB_EVENT_SYNC_POP = 320 -SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 321 -SC_PA0_SC_FPOV_WE = 322 -SC_PA1_SC_FPOV_WE = 323 -SC_PA2_SC_FPOV_WE = 324 -SC_PA3_SC_FPOV_WE = 325 -SC_PA0_SC_LPOV_WE = 326 -SC_PA1_SC_LPOV_WE = 327 -SC_PA2_SC_LPOV_WE = 328 -SC_PA3_SC_LPOV_WE = 329 -SC_SC_SPI_DEALLOC_0_0 = 330 -SC_SC_SPI_DEALLOC_0_1 = 331 -SC_SC_SPI_DEALLOC_0_2 = 332 -SC_SC_SPI_DEALLOC_1_0 = 333 -SC_SC_SPI_DEALLOC_1_1 = 334 -SC_SC_SPI_DEALLOC_1_2 = 335 -SC_SC_SPI_DEALLOC_2_0 = 336 -SC_SC_SPI_DEALLOC_2_1 = 337 -SC_SC_SPI_DEALLOC_2_2 = 338 -SC_SC_SPI_DEALLOC_3_0 = 339 -SC_SC_SPI_DEALLOC_3_1 = 340 -SC_SC_SPI_DEALLOC_3_2 = 341 -SC_SC_SPI_FPOV_0 = 342 -SC_SC_SPI_FPOV_1 = 343 -SC_SC_SPI_FPOV_2 = 344 -SC_SC_SPI_FPOV_3 = 345 -SC_SC_SPI_EVENT = 346 -SC_PS_TS_EVENT_FIFO_PUSH = 347 -SC_PS_TS_EVENT_FIFO_POP = 348 -SC_PS_CTX_DONE_FIFO_PUSH = 349 -SC_PS_CTX_DONE_FIFO_POP = 350 -SC_MULTICYCLE_BUBBLE_FREEZE = 351 -SC_EOP_SYNC_WINDOW = 352 -SC_PA0_SC_NULL_WE = 353 -SC_PA0_SC_NULL_DEALLOC_WE = 354 -SC_PA0_SC_DATA_FIFO_EOPG_RD = 355 -SC_PA0_SC_DATA_FIFO_EOP_RD = 356 -SC_PA0_SC_DEALLOC_0_RD = 357 -SC_PA0_SC_DEALLOC_1_RD = 358 -SC_PA1_SC_DATA_FIFO_EOPG_RD = 359 -SC_PA1_SC_DATA_FIFO_EOP_RD = 360 -SC_PA1_SC_DEALLOC_0_RD = 361 -SC_PA1_SC_DEALLOC_1_RD = 362 -SC_PA1_SC_NULL_WE = 363 -SC_PA1_SC_NULL_DEALLOC_WE = 364 -SC_PA2_SC_DATA_FIFO_EOPG_RD = 365 -SC_PA2_SC_DATA_FIFO_EOP_RD = 366 -SC_PA2_SC_DEALLOC_0_RD = 367 -SC_PA2_SC_DEALLOC_1_RD = 368 -SC_PA2_SC_NULL_WE = 369 -SC_PA2_SC_NULL_DEALLOC_WE = 370 -SC_PA3_SC_DATA_FIFO_EOPG_RD = 371 -SC_PA3_SC_DATA_FIFO_EOP_RD = 372 -SC_PA3_SC_DEALLOC_0_RD = 373 -SC_PA3_SC_DEALLOC_1_RD = 374 -SC_PA3_SC_NULL_WE = 375 -SC_PA3_SC_NULL_DEALLOC_WE = 376 -SC_PS_PA0_SC_FIFO_EMPTY = 377 -SC_PS_PA0_SC_FIFO_FULL = 378 -SC_PA0_PS_DATA_SEND = 379 -SC_PS_PA1_SC_FIFO_EMPTY = 380 -SC_PS_PA1_SC_FIFO_FULL = 381 -SC_PA1_PS_DATA_SEND = 382 -SC_PS_PA2_SC_FIFO_EMPTY = 383 -SC_PS_PA2_SC_FIFO_FULL = 384 -SC_PA2_PS_DATA_SEND = 385 -SC_PS_PA3_SC_FIFO_EMPTY = 386 -SC_PS_PA3_SC_FIFO_FULL = 387 -SC_PA3_PS_DATA_SEND = 388 -SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 389 -SC_BUSY_CNT_NOT_ZERO = 390 -SC_BM_BUSY = 391 -SC_BACKEND_BUSY = 392 -SC_SCF_SCB_INTERFACE_BUSY = 393 -SC_SCB_BUSY = 394 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 395 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 396 -SC_PBB_BIN_HIST_NUM_PRIMS = 397 -SC_PBB_BATCH_HIST_NUM_PRIMS = 398 -SC_PBB_BIN_HIST_NUM_CONTEXTS = 399 -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 400 -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 401 -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 402 -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 403 -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 404 -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 405 -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 406 -SC_PBB_BUSY = 407 -SC_PBB_BUSY_AND_RTR = 408 -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 409 -SC_PBB_NUM_BINS = 410 -SC_PBB_END_OF_BIN = 411 -SC_PBB_END_OF_BATCH = 412 -SC_PBB_PRIMBIN_PROCESSED = 413 -SC_PBB_PRIM_ADDED_TO_BATCH = 414 -SC_PBB_NONBINNED_PRIM = 415 -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 416 -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 417 -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 418 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 419 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 420 -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 421 -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 422 -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 423 -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 424 -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 425 -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 426 -SC_POPS_INTRA_WAVE_OVERLAPS = 427 -SC_POPS_FORCE_EOV = 428 -SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 429 -SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 430 -SC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SePairXsel' -SePairXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 4: 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 -RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 4 -SePairXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairYsel' -SePairYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 4: 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 -RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 4 -SePairYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairMap' -SePairMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', - 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', - 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', - 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', -} -RASTER_CONFIG_SE_PAIR_MAP_0 = 0 -RASTER_CONFIG_SE_PAIR_MAP_1 = 1 -RASTER_CONFIG_SE_PAIR_MAP_2 = 2 -RASTER_CONFIG_SE_PAIR_MAP_3 = 3 -SePairMap = ctypes.c_uint32 # enum - -# values for enumeration 'SeXsel' -SeXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 4: 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', -} -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 -RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 4 -SeXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeYsel' -SeYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 4: 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', -} -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 -RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 4 -SeYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeMap' -SeMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_MAP_0', - 1: 'RASTER_CONFIG_SE_MAP_1', - 2: 'RASTER_CONFIG_SE_MAP_2', - 3: 'RASTER_CONFIG_SE_MAP_3', -} -RASTER_CONFIG_SE_MAP_0 = 0 -RASTER_CONFIG_SE_MAP_1 = 1 -RASTER_CONFIG_SE_MAP_2 = 2 -RASTER_CONFIG_SE_MAP_3 = 3 -SeMap = ctypes.c_uint32 # enum - -# values for enumeration 'ScXsel' -ScXsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 -ScXsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScYsel' -ScYsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 -ScYsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScMap' -ScMap__enumvalues = { - 0: 'RASTER_CONFIG_SC_MAP_0', - 1: 'RASTER_CONFIG_SC_MAP_1', - 2: 'RASTER_CONFIG_SC_MAP_2', - 3: 'RASTER_CONFIG_SC_MAP_3', -} -RASTER_CONFIG_SC_MAP_0 = 0 -RASTER_CONFIG_SC_MAP_1 = 1 -RASTER_CONFIG_SC_MAP_2 = 2 -RASTER_CONFIG_SC_MAP_3 = 3 -ScMap = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel2' -PkrXsel2__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL2_0', - 1: 'RASTER_CONFIG_PKR_XSEL2_1', - 2: 'RASTER_CONFIG_PKR_XSEL2_2', - 3: 'RASTER_CONFIG_PKR_XSEL2_3', -} -RASTER_CONFIG_PKR_XSEL2_0 = 0 -RASTER_CONFIG_PKR_XSEL2_1 = 1 -RASTER_CONFIG_PKR_XSEL2_2 = 2 -RASTER_CONFIG_PKR_XSEL2_3 = 3 -PkrXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel' -PkrXsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL_0', - 1: 'RASTER_CONFIG_PKR_XSEL_1', - 2: 'RASTER_CONFIG_PKR_XSEL_2', - 3: 'RASTER_CONFIG_PKR_XSEL_3', -} -RASTER_CONFIG_PKR_XSEL_0 = 0 -RASTER_CONFIG_PKR_XSEL_1 = 1 -RASTER_CONFIG_PKR_XSEL_2 = 2 -RASTER_CONFIG_PKR_XSEL_3 = 3 -PkrXsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrYsel' -PkrYsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_YSEL_0', - 1: 'RASTER_CONFIG_PKR_YSEL_1', - 2: 'RASTER_CONFIG_PKR_YSEL_2', - 3: 'RASTER_CONFIG_PKR_YSEL_3', -} -RASTER_CONFIG_PKR_YSEL_0 = 0 -RASTER_CONFIG_PKR_YSEL_1 = 1 -RASTER_CONFIG_PKR_YSEL_2 = 2 -RASTER_CONFIG_PKR_YSEL_3 = 3 -PkrYsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrMap' -PkrMap__enumvalues = { - 0: 'RASTER_CONFIG_PKR_MAP_0', - 1: 'RASTER_CONFIG_PKR_MAP_1', - 2: 'RASTER_CONFIG_PKR_MAP_2', - 3: 'RASTER_CONFIG_PKR_MAP_3', -} -RASTER_CONFIG_PKR_MAP_0 = 0 -RASTER_CONFIG_PKR_MAP_1 = 1 -RASTER_CONFIG_PKR_MAP_2 = 2 -RASTER_CONFIG_PKR_MAP_3 = 3 -PkrMap = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel' -RbXsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL_0', - 1: 'RASTER_CONFIG_RB_XSEL_1', -} -RASTER_CONFIG_RB_XSEL_0 = 0 -RASTER_CONFIG_RB_XSEL_1 = 1 -RbXsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbYsel' -RbYsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_YSEL_0', - 1: 'RASTER_CONFIG_RB_YSEL_1', -} -RASTER_CONFIG_RB_YSEL_0 = 0 -RASTER_CONFIG_RB_YSEL_1 = 1 -RbYsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel2' -RbXsel2__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL2_0', - 1: 'RASTER_CONFIG_RB_XSEL2_1', - 2: 'RASTER_CONFIG_RB_XSEL2_2', - 3: 'RASTER_CONFIG_RB_XSEL2_3', -} -RASTER_CONFIG_RB_XSEL2_0 = 0 -RASTER_CONFIG_RB_XSEL2_1 = 1 -RASTER_CONFIG_RB_XSEL2_2 = 2 -RASTER_CONFIG_RB_XSEL2_3 = 3 -RbXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'RbMap' -RbMap__enumvalues = { - 0: 'RASTER_CONFIG_RB_MAP_0', - 1: 'RASTER_CONFIG_RB_MAP_1', - 2: 'RASTER_CONFIG_RB_MAP_2', - 3: 'RASTER_CONFIG_RB_MAP_3', -} -RASTER_CONFIG_RB_MAP_0 = 0 -RASTER_CONFIG_RB_MAP_1 = 1 -RASTER_CONFIG_RB_MAP_2 = 2 -RASTER_CONFIG_RB_MAP_3 = 3 -RbMap = ctypes.c_uint32 # enum - -# values for enumeration 'BinningMode' -BinningMode__enumvalues = { - 0: 'BINNING_ALLOWED', - 1: 'FORCE_BINNING_ON', - 2: 'DISABLE_BINNING_USE_NEW_SC', - 3: 'DISABLE_BINNING_USE_LEGACY_SC', -} -BINNING_ALLOWED = 0 -FORCE_BINNING_ON = 1 -DISABLE_BINNING_USE_NEW_SC = 2 -DISABLE_BINNING_USE_LEGACY_SC = 3 -BinningMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinEventCntl' -BinEventCntl__enumvalues = { - 0: 'BINNER_BREAK_BATCH', - 1: 'BINNER_PIPELINE', - 2: 'BINNER_DROP_ASSERT', -} -BINNER_BREAK_BATCH = 0 -BINNER_PIPELINE = 1 -BINNER_DROP_ASSERT = 2 -BinEventCntl = ctypes.c_uint32 # enum - -# values for enumeration 'CovToShaderSel' -CovToShaderSel__enumvalues = { - 0: 'INPUT_COVERAGE', - 1: 'INPUT_INNER_COVERAGE', - 2: 'INPUT_DEPTH_COVERAGE', - 3: 'RAW', -} -INPUT_COVERAGE = 0 -INPUT_INNER_COVERAGE = 1 -INPUT_DEPTH_COVERAGE = 2 -RAW = 3 -CovToShaderSel = ctypes.c_uint32 # enum - -# values for enumeration 'RMIPerfSel' -RMIPerfSel__enumvalues = { - 0: 'RMI_PERF_SEL_NONE', - 1: 'RMI_PERF_SEL_BUSY', - 2: 'RMI_PERF_SEL_REG_CLK_VLD', - 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', - 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', - 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 6: 'RMI_PERF_SEL_PERF_WINDOW', - 7: 'RMI_PERF_SEL_EVENT_SEND', - 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', - 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', - 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', - 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', - 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', - 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', - 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', - 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', - 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', - 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', - 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', - 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', - 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', - 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', - 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', - 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', - 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', - 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', - 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', - 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', - 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', - 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', - 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', - 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', - 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', - 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', - 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', - 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', - 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', - 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', - 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', - 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', - 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', - 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', - 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', - 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', - 44: 'RMI_PERF_SEL_UTCL1_REQUEST', - 45: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 46: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 47: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', - 48: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 49: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 50: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 51: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', - 52: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', - 53: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', - 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', - 64: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 67: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 80: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 81: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', - 83: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 91: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 99: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 100: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 103: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 116: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 117: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 118: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 119: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 120: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 121: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 122: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 123: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 124: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 125: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 126: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 127: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', - 128: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 129: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 130: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 131: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 132: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 133: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 134: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 135: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 136: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 137: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 138: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 139: 'RMI_PERF_SEL_UTCL1_BUSY', - 140: 'RMI_PERF_SEL_RMI_UTC_REQ', - 141: 'RMI_PERF_SEL_RMI_UTC_BUSY', - 142: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', - 143: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', - 144: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', - 145: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', - 146: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', - 147: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', - 148: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', - 149: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', - 150: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', - 151: 'RMI_PERF_SEL_XNACK_FIFO_FULL', - 152: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', - 153: 'RMI_PERF_SEL_LAT_FIFO_FULL', - 154: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', - 155: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 156: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', - 157: 'RMI_PERF_SEL_PRT_FIFO_REQ', - 158: 'RMI_PERF_SEL_PRT_FIFO_BUSY', - 159: 'RMI_PERF_SEL_TCIW_REQ', - 160: 'RMI_PERF_SEL_TCIW_BUSY', - 161: 'RMI_PERF_SEL_SKID_FIFO_REQ', - 162: 'RMI_PERF_SEL_SKID_FIFO_BUSY', - 163: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', - 164: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', - 165: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', - 166: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', - 167: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', - 168: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', - 169: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', - 170: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', - 171: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 172: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 173: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 174: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 175: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', - 176: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', - 177: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', - 178: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', - 179: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', - 180: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', - 181: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', - 182: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', - 183: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', - 184: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', - 185: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', - 186: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', - 187: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', - 188: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', - 189: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', - 190: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', - 191: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', - 192: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', - 193: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', - 194: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', - 195: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', - 196: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', - 197: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', - 198: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', - 199: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', - 200: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', - 201: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', - 202: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', - 203: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', - 204: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', - 205: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', - 206: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', - 207: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', - 208: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', - 209: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', - 210: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', - 211: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', - 212: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', - 213: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', - 214: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', - 215: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', - 216: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', - 217: 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 218: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 219: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 220: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 221: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 222: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 223: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 224: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 225: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 226: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 227: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 228: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', - 229: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', - 230: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', - 231: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', -} -RMI_PERF_SEL_NONE = 0 -RMI_PERF_SEL_BUSY = 1 -RMI_PERF_SEL_REG_CLK_VLD = 2 -RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 -RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 -RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 -RMI_PERF_SEL_PERF_WINDOW = 6 -RMI_PERF_SEL_EVENT_SEND = 7 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 -RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 -RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 -RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 -RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 -RMI_PERF_SEL_UTCL1_REQUEST = 44 -RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 45 -RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 46 -RMI_PERF_SEL_UTCL1_LFIFO_FULL = 47 -RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 48 -RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 49 -RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 50 -RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 51 -RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 52 -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 53 -RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 54 -RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 55 -RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 56 -RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 57 -RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 58 -RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 59 -RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 60 -RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 61 -RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 62 -RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 63 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 64 -RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 65 -RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 66 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 67 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 68 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 69 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 70 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 71 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 72 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 73 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 74 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 75 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 76 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 77 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 78 -RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 79 -RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 80 -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 81 -RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 82 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 83 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 84 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 85 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 86 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 87 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 88 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 89 -RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 90 -RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 91 -RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 92 -RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 93 -RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 94 -RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 95 -RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 96 -RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 97 -RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 98 -RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 99 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 100 -RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 101 -RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 102 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 103 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 104 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 105 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 106 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 107 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 108 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 109 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 110 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 111 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 112 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 113 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 114 -RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 115 -RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 116 -RMI_PERF_SEL_RMI_TC_REQ_BUSY = 117 -RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 118 -RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 119 -RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 120 -RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 121 -RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 122 -RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 123 -RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 124 -RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 125 -RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 126 -RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 127 -RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 128 -RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 129 -RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 130 -RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 131 -RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 132 -RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 133 -RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 134 -RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 135 -RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 136 -RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 137 -RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 138 -RMI_PERF_SEL_UTCL1_BUSY = 139 -RMI_PERF_SEL_RMI_UTC_REQ = 140 -RMI_PERF_SEL_RMI_UTC_BUSY = 141 -RMI_PERF_SEL_UTCL1_UTCL2_REQ = 142 -RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 143 -RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 144 -RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 145 -RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 146 -RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 147 -RMI_PERF_SEL_LAT_FIFO_NUM_USED = 148 -RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 149 -RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 150 -RMI_PERF_SEL_XNACK_FIFO_FULL = 151 -RMI_PERF_SEL_XNACK_FIFO_BUSY = 152 -RMI_PERF_SEL_LAT_FIFO_FULL = 153 -RMI_PERF_SEL_SKID_FIFO_DEPTH = 154 -RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 155 -RMI_PERF_SEL_PRT_FIFO_NUM_USED = 156 -RMI_PERF_SEL_PRT_FIFO_REQ = 157 -RMI_PERF_SEL_PRT_FIFO_BUSY = 158 -RMI_PERF_SEL_TCIW_REQ = 159 -RMI_PERF_SEL_TCIW_BUSY = 160 -RMI_PERF_SEL_SKID_FIFO_REQ = 161 -RMI_PERF_SEL_SKID_FIFO_BUSY = 162 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 163 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 164 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 165 -RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 166 -RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 167 -RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 168 -RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 169 -RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 170 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 171 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 172 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 173 -RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 174 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 175 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 176 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 177 -RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 178 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 179 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 180 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 181 -RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 182 -RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 183 -RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 184 -RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 185 -RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 186 -RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 187 -RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 188 -RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 189 -RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 190 -RMI_PERF_SEL_UTC_POP_RTS_RTR = 191 -RMI_PERF_SEL_UTC_POP_RTSB_RTR = 192 -RMI_PERF_SEL_UTC_POP_RTS_RTRB = 193 -RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 194 -RMI_PERF_SEL_POP_XNACK_RTS_RTR = 195 -RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 196 -RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 197 -RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 198 -RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 199 -RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 200 -RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 201 -RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 202 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 203 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 204 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 205 -RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 206 -RMI_PERF_SEL_SKID_FIFO_IN_RTS = 207 -RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 208 -RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 209 -RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 210 -RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 211 -RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 212 -RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 213 -RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 214 -RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 215 -RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 216 -RMI_PERF_SEL_REORDER_FIFO_REQ = 217 -RMI_PERF_SEL_REORDER_FIFO_BUSY = 218 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 219 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 220 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 221 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 222 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 223 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 224 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 225 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 226 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 227 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 228 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 229 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 230 -RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 231 -RMIPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'IH_PERF_SEL' -IH_PERF_SEL__enumvalues = { - 0: 'IH_PERF_SEL_CYCLE', - 1: 'IH_PERF_SEL_IDLE', - 2: 'IH_PERF_SEL_INPUT_IDLE', - 3: 'IH_PERF_SEL_BUFFER_IDLE', - 4: 'IH_PERF_SEL_RB0_FULL', - 5: 'IH_PERF_SEL_RB0_OVERFLOW', - 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', - 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', - 9: 'IH_PERF_SEL_MC_WR_IDLE', - 10: 'IH_PERF_SEL_MC_WR_COUNT', - 11: 'IH_PERF_SEL_MC_WR_STALL', - 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', - 14: 'IH_PERF_SEL_BIF_LINE0_RISING', - 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', - 16: 'IH_PERF_SEL_RB1_FULL', - 17: 'IH_PERF_SEL_RB1_OVERFLOW', - 18: 'Reserved18', - 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', - 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', - 21: 'IH_PERF_SEL_RB2_FULL', - 22: 'IH_PERF_SEL_RB2_OVERFLOW', - 23: 'Reserved23', - 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', - 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', - 26: 'Reserved26', - 27: 'Reserved27', - 28: 'Reserved28', - 29: 'Reserved29', - 30: 'IH_PERF_SEL_RB0_FULL_VF0', - 31: 'IH_PERF_SEL_RB0_FULL_VF1', - 32: 'IH_PERF_SEL_RB0_FULL_VF2', - 33: 'IH_PERF_SEL_RB0_FULL_VF3', - 34: 'IH_PERF_SEL_RB0_FULL_VF4', - 35: 'IH_PERF_SEL_RB0_FULL_VF5', - 36: 'IH_PERF_SEL_RB0_FULL_VF6', - 37: 'IH_PERF_SEL_RB0_FULL_VF7', - 38: 'IH_PERF_SEL_RB0_FULL_VF8', - 39: 'IH_PERF_SEL_RB0_FULL_VF9', - 40: 'IH_PERF_SEL_RB0_FULL_VF10', - 41: 'IH_PERF_SEL_RB0_FULL_VF11', - 42: 'IH_PERF_SEL_RB0_FULL_VF12', - 43: 'IH_PERF_SEL_RB0_FULL_VF13', - 44: 'IH_PERF_SEL_RB0_FULL_VF14', - 45: 'IH_PERF_SEL_RB0_FULL_VF15', - 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', - 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', - 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', - 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', - 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', - 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', - 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', - 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', - 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', - 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 77: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', - 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', - 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', - 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', - 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', - 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 93: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', - 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', - 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', - 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', - 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', - 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', - 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 109: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', - 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 125: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 141: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 142: 'Reserved142', - 143: 'Reserved143', - 144: 'Reserved144', - 145: 'Reserved145', - 146: 'Reserved146', - 147: 'Reserved147', - 148: 'Reserved148', - 149: 'Reserved149', - 150: 'IH_PERF_SEL_CLIENT0_INT', - 151: 'IH_PERF_SEL_CLIENT1_INT', - 152: 'IH_PERF_SEL_CLIENT2_INT', - 153: 'IH_PERF_SEL_CLIENT3_INT', - 154: 'IH_PERF_SEL_CLIENT4_INT', - 155: 'IH_PERF_SEL_CLIENT5_INT', - 156: 'IH_PERF_SEL_CLIENT6_INT', - 157: 'IH_PERF_SEL_CLIENT7_INT', - 158: 'IH_PERF_SEL_CLIENT8_INT', - 159: 'IH_PERF_SEL_CLIENT9_INT', - 160: 'IH_PERF_SEL_CLIENT10_INT', - 161: 'IH_PERF_SEL_CLIENT11_INT', - 162: 'IH_PERF_SEL_CLIENT12_INT', - 163: 'IH_PERF_SEL_CLIENT13_INT', - 164: 'IH_PERF_SEL_CLIENT14_INT', - 165: 'IH_PERF_SEL_CLIENT15_INT', - 166: 'IH_PERF_SEL_CLIENT16_INT', - 167: 'IH_PERF_SEL_CLIENT17_INT', - 168: 'IH_PERF_SEL_CLIENT18_INT', - 169: 'IH_PERF_SEL_CLIENT19_INT', - 170: 'IH_PERF_SEL_CLIENT20_INT', - 171: 'IH_PERF_SEL_CLIENT21_INT', - 172: 'IH_PERF_SEL_CLIENT22_INT', - 173: 'IH_PERF_SEL_CLIENT23_INT', - 174: 'IH_PERF_SEL_CLIENT24_INT', - 175: 'IH_PERF_SEL_CLIENT25_INT', - 176: 'IH_PERF_SEL_CLIENT26_INT', - 177: 'IH_PERF_SEL_CLIENT27_INT', - 178: 'IH_PERF_SEL_CLIENT28_INT', - 179: 'IH_PERF_SEL_CLIENT29_INT', - 180: 'IH_PERF_SEL_CLIENT30_INT', - 181: 'IH_PERF_SEL_CLIENT31_INT', - 182: 'Reserved182', - 183: 'Reserved183', - 184: 'Reserved184', - 185: 'Reserved185', - 186: 'Reserved186', - 187: 'Reserved187', - 188: 'Reserved188', - 189: 'Reserved189', - 190: 'Reserved190', - 191: 'Reserved191', - 192: 'Reserved192', - 193: 'Reserved193', - 194: 'Reserved194', - 195: 'Reserved195', - 196: 'Reserved196', - 197: 'Reserved197', - 198: 'Reserved198', - 199: 'Reserved199', - 200: 'Reserved200', - 201: 'Reserved201', - 202: 'Reserved202', - 203: 'Reserved203', - 204: 'Reserved204', - 205: 'Reserved205', - 206: 'Reserved206', - 207: 'Reserved207', - 208: 'Reserved208', - 209: 'Reserved209', - 210: 'Reserved210', - 211: 'Reserved211', - 212: 'Reserved212', - 213: 'Reserved213', - 214: 'Reserved214', - 215: 'Reserved215', - 216: 'Reserved216', - 217: 'Reserved217', - 218: 'Reserved218', - 219: 'Reserved219', - 220: 'IH_PERF_SEL_RB1_FULL_VF0', - 221: 'IH_PERF_SEL_RB1_FULL_VF1', - 222: 'IH_PERF_SEL_RB1_FULL_VF2', - 223: 'IH_PERF_SEL_RB1_FULL_VF3', - 224: 'IH_PERF_SEL_RB1_FULL_VF4', - 225: 'IH_PERF_SEL_RB1_FULL_VF5', - 226: 'IH_PERF_SEL_RB1_FULL_VF6', - 227: 'IH_PERF_SEL_RB1_FULL_VF7', - 228: 'IH_PERF_SEL_RB1_FULL_VF8', - 229: 'IH_PERF_SEL_RB1_FULL_VF9', - 230: 'IH_PERF_SEL_RB1_FULL_VF10', - 231: 'IH_PERF_SEL_RB1_FULL_VF11', - 232: 'IH_PERF_SEL_RB1_FULL_VF12', - 233: 'IH_PERF_SEL_RB1_FULL_VF13', - 234: 'IH_PERF_SEL_RB1_FULL_VF14', - 235: 'IH_PERF_SEL_RB1_FULL_VF15', - 236: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', - 237: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 238: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', - 239: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 240: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 241: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 242: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 243: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 244: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 245: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 246: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', - 247: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 248: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', - 249: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 250: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', - 251: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 252: 'Reserved252', - 253: 'Reserved253', - 254: 'Reserved254', - 255: 'Reserved255', - 256: 'Reserved256', - 257: 'Reserved257', - 258: 'Reserved258', - 259: 'Reserved259', - 260: 'Reserved260', - 261: 'Reserved261', - 262: 'Reserved262', - 263: 'Reserved263', - 264: 'Reserved264', - 265: 'Reserved265', - 266: 'Reserved266', - 267: 'Reserved267', - 268: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', - 269: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 270: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 271: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', - 272: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 273: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', - 274: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 275: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', - 276: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 277: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', - 278: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 279: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 280: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 281: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 282: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 283: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', - 284: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 285: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 286: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 287: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', - 288: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 289: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', - 290: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 291: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', - 292: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 293: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', - 294: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 295: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 296: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 297: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 298: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 299: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', - 300: 'Reserved300', - 301: 'Reserved301', - 302: 'Reserved302', - 303: 'Reserved303', - 304: 'Reserved304', - 305: 'Reserved305', - 306: 'Reserved306', - 307: 'Reserved307', - 308: 'Reserved308', - 309: 'Reserved309', - 310: 'Reserved310', - 311: 'Reserved311', - 312: 'Reserved312', - 313: 'Reserved313', - 314: 'Reserved314', - 315: 'Reserved315', - 316: 'Reserved316', - 317: 'Reserved317', - 318: 'Reserved318', - 319: 'Reserved319', - 320: 'Reserved320', - 321: 'Reserved321', - 322: 'Reserved322', - 323: 'Reserved323', - 324: 'Reserved324', - 325: 'Reserved325', - 326: 'Reserved326', - 327: 'Reserved327', - 328: 'Reserved328', - 329: 'Reserved329', - 330: 'Reserved330', - 331: 'Reserved331', - 332: 'IH_PERF_SEL_RB2_FULL_VF0', - 333: 'IH_PERF_SEL_RB2_FULL_VF1', - 334: 'IH_PERF_SEL_RB2_FULL_VF2', - 335: 'IH_PERF_SEL_RB2_FULL_VF3', - 336: 'IH_PERF_SEL_RB2_FULL_VF4', - 337: 'IH_PERF_SEL_RB2_FULL_VF5', - 338: 'IH_PERF_SEL_RB2_FULL_VF6', - 339: 'IH_PERF_SEL_RB2_FULL_VF7', - 340: 'IH_PERF_SEL_RB2_FULL_VF8', - 341: 'IH_PERF_SEL_RB2_FULL_VF9', - 342: 'IH_PERF_SEL_RB2_FULL_VF10', - 343: 'IH_PERF_SEL_RB2_FULL_VF11', - 344: 'IH_PERF_SEL_RB2_FULL_VF12', - 345: 'IH_PERF_SEL_RB2_FULL_VF13', - 346: 'IH_PERF_SEL_RB2_FULL_VF14', - 347: 'IH_PERF_SEL_RB2_FULL_VF15', - 348: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', - 349: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 350: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', - 351: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 352: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 353: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 354: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 355: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 356: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 357: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 358: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', - 359: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 360: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', - 361: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 362: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', - 363: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 364: 'Reserved364', - 365: 'Reserved365', - 366: 'Reserved366', - 367: 'Reserved367', - 368: 'Reserved368', - 369: 'Reserved369', - 370: 'Reserved370', - 371: 'Reserved371', - 372: 'Reserved372', - 373: 'Reserved373', - 374: 'Reserved374', - 375: 'Reserved375', - 376: 'Reserved376', - 377: 'Reserved377', - 378: 'Reserved378', - 379: 'Reserved379', - 380: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', - 381: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 382: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 383: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', - 384: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 385: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', - 386: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 387: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', - 388: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 389: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', - 390: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 391: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 392: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 393: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 394: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 395: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', - 396: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 397: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 398: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 399: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', - 400: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 401: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', - 402: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 403: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', - 404: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 405: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', - 406: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 407: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 408: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 409: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 410: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 411: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', - 412: 'Reserved412', - 413: 'Reserved413', - 414: 'Reserved414', - 415: 'Reserved415', - 416: 'Reserved416', - 417: 'Reserved417', - 418: 'Reserved418', - 419: 'Reserved419', - 420: 'Reserved420', - 421: 'Reserved421', - 422: 'Reserved422', - 423: 'Reserved423', - 424: 'Reserved424', - 425: 'Reserved425', - 426: 'Reserved426', - 427: 'Reserved427', - 428: 'Reserved428', - 429: 'Reserved429', - 430: 'Reserved430', - 431: 'Reserved431', - 432: 'Reserved432', - 433: 'Reserved433', - 434: 'Reserved434', - 435: 'Reserved435', - 436: 'Reserved436', - 437: 'Reserved437', - 438: 'Reserved438', - 439: 'Reserved439', - 440: 'Reserved440', - 441: 'Reserved441', - 442: 'Reserved442', - 443: 'Reserved443', - 444: 'Reserved444', - 445: 'Reserved445', - 446: 'Reserved446', - 447: 'Reserved447', - 448: 'Reserved448', - 449: 'Reserved449', - 450: 'Reserved450', - 451: 'Reserved451', - 452: 'Reserved452', - 453: 'Reserved453', - 454: 'Reserved454', - 455: 'Reserved455', - 456: 'Reserved456', - 457: 'Reserved457', - 458: 'Reserved458', - 459: 'Reserved459', - 460: 'Reserved460', - 461: 'Reserved461', - 462: 'Reserved462', - 463: 'Reserved463', - 464: 'Reserved464', - 465: 'Reserved465', - 466: 'Reserved466', - 467: 'Reserved467', - 468: 'Reserved468', - 469: 'Reserved469', - 470: 'Reserved470', - 471: 'Reserved471', - 472: 'Reserved472', - 473: 'Reserved473', - 474: 'Reserved474', - 475: 'Reserved475', - 476: 'Reserved476', - 477: 'Reserved477', - 478: 'Reserved478', - 479: 'Reserved479', - 480: 'Reserved480', - 481: 'Reserved481', - 482: 'Reserved482', - 483: 'Reserved483', - 484: 'Reserved484', - 485: 'Reserved485', - 486: 'Reserved486', - 487: 'Reserved487', - 488: 'Reserved488', - 489: 'Reserved489', - 490: 'Reserved490', - 491: 'Reserved491', - 492: 'Reserved492', - 493: 'Reserved493', - 494: 'Reserved494', - 495: 'Reserved495', - 496: 'Reserved496', - 497: 'Reserved497', - 498: 'Reserved498', - 499: 'Reserved499', - 500: 'Reserved500', - 501: 'Reserved501', - 502: 'Reserved502', - 503: 'Reserved503', - 504: 'Reserved504', - 505: 'Reserved505', - 506: 'Reserved506', - 507: 'Reserved507', - 508: 'Reserved508', - 509: 'Reserved509', - 510: 'Reserved510', - 511: 'Reserved511', -} -IH_PERF_SEL_CYCLE = 0 -IH_PERF_SEL_IDLE = 1 -IH_PERF_SEL_INPUT_IDLE = 2 -IH_PERF_SEL_BUFFER_IDLE = 3 -IH_PERF_SEL_RB0_FULL = 4 -IH_PERF_SEL_RB0_OVERFLOW = 5 -IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 -IH_PERF_SEL_RB0_WPTR_WRAP = 7 -IH_PERF_SEL_RB0_RPTR_WRAP = 8 -IH_PERF_SEL_MC_WR_IDLE = 9 -IH_PERF_SEL_MC_WR_COUNT = 10 -IH_PERF_SEL_MC_WR_STALL = 11 -IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 -IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 -IH_PERF_SEL_BIF_LINE0_RISING = 14 -IH_PERF_SEL_BIF_LINE0_FALLING = 15 -IH_PERF_SEL_RB1_FULL = 16 -IH_PERF_SEL_RB1_OVERFLOW = 17 -Reserved18 = 18 -IH_PERF_SEL_RB1_WPTR_WRAP = 19 -IH_PERF_SEL_RB1_RPTR_WRAP = 20 -IH_PERF_SEL_RB2_FULL = 21 -IH_PERF_SEL_RB2_OVERFLOW = 22 -Reserved23 = 23 -IH_PERF_SEL_RB2_WPTR_WRAP = 24 -IH_PERF_SEL_RB2_RPTR_WRAP = 25 -Reserved26 = 26 -Reserved27 = 27 -Reserved28 = 28 -Reserved29 = 29 -IH_PERF_SEL_RB0_FULL_VF0 = 30 -IH_PERF_SEL_RB0_FULL_VF1 = 31 -IH_PERF_SEL_RB0_FULL_VF2 = 32 -IH_PERF_SEL_RB0_FULL_VF3 = 33 -IH_PERF_SEL_RB0_FULL_VF4 = 34 -IH_PERF_SEL_RB0_FULL_VF5 = 35 -IH_PERF_SEL_RB0_FULL_VF6 = 36 -IH_PERF_SEL_RB0_FULL_VF7 = 37 -IH_PERF_SEL_RB0_FULL_VF8 = 38 -IH_PERF_SEL_RB0_FULL_VF9 = 39 -IH_PERF_SEL_RB0_FULL_VF10 = 40 -IH_PERF_SEL_RB0_FULL_VF11 = 41 -IH_PERF_SEL_RB0_FULL_VF12 = 42 -IH_PERF_SEL_RB0_FULL_VF13 = 43 -IH_PERF_SEL_RB0_FULL_VF14 = 44 -IH_PERF_SEL_RB0_FULL_VF15 = 45 -IH_PERF_SEL_RB0_OVERFLOW_VF0 = 46 -IH_PERF_SEL_RB0_OVERFLOW_VF1 = 47 -IH_PERF_SEL_RB0_OVERFLOW_VF2 = 48 -IH_PERF_SEL_RB0_OVERFLOW_VF3 = 49 -IH_PERF_SEL_RB0_OVERFLOW_VF4 = 50 -IH_PERF_SEL_RB0_OVERFLOW_VF5 = 51 -IH_PERF_SEL_RB0_OVERFLOW_VF6 = 52 -IH_PERF_SEL_RB0_OVERFLOW_VF7 = 53 -IH_PERF_SEL_RB0_OVERFLOW_VF8 = 54 -IH_PERF_SEL_RB0_OVERFLOW_VF9 = 55 -IH_PERF_SEL_RB0_OVERFLOW_VF10 = 56 -IH_PERF_SEL_RB0_OVERFLOW_VF11 = 57 -IH_PERF_SEL_RB0_OVERFLOW_VF12 = 58 -IH_PERF_SEL_RB0_OVERFLOW_VF13 = 59 -IH_PERF_SEL_RB0_OVERFLOW_VF14 = 60 -IH_PERF_SEL_RB0_OVERFLOW_VF15 = 61 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 62 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 63 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 64 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 65 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 66 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 67 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 68 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 69 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 70 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 71 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 72 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 73 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 74 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 75 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 76 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 77 -IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 78 -IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 79 -IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 80 -IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 81 -IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 82 -IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 83 -IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 84 -IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 85 -IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 86 -IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 87 -IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 88 -IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 89 -IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 90 -IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 91 -IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 92 -IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 93 -IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 94 -IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 95 -IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 96 -IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 97 -IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 98 -IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 99 -IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 100 -IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 101 -IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 102 -IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 103 -IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 104 -IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 105 -IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 106 -IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 107 -IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 108 -IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 109 -IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 110 -IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 111 -IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 112 -IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 113 -IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 114 -IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 115 -IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 116 -IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 117 -IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 118 -IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 119 -IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 120 -IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 121 -IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 122 -IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 123 -IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 124 -IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 125 -IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 126 -IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 127 -IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 128 -IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 129 -IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 130 -IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 131 -IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 132 -IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 133 -IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 134 -IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 135 -IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 136 -IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 137 -IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 138 -IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 139 -IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 140 -IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 141 -Reserved142 = 142 -Reserved143 = 143 -Reserved144 = 144 -Reserved145 = 145 -Reserved146 = 146 -Reserved147 = 147 -Reserved148 = 148 -Reserved149 = 149 -IH_PERF_SEL_CLIENT0_INT = 150 -IH_PERF_SEL_CLIENT1_INT = 151 -IH_PERF_SEL_CLIENT2_INT = 152 -IH_PERF_SEL_CLIENT3_INT = 153 -IH_PERF_SEL_CLIENT4_INT = 154 -IH_PERF_SEL_CLIENT5_INT = 155 -IH_PERF_SEL_CLIENT6_INT = 156 -IH_PERF_SEL_CLIENT7_INT = 157 -IH_PERF_SEL_CLIENT8_INT = 158 -IH_PERF_SEL_CLIENT9_INT = 159 -IH_PERF_SEL_CLIENT10_INT = 160 -IH_PERF_SEL_CLIENT11_INT = 161 -IH_PERF_SEL_CLIENT12_INT = 162 -IH_PERF_SEL_CLIENT13_INT = 163 -IH_PERF_SEL_CLIENT14_INT = 164 -IH_PERF_SEL_CLIENT15_INT = 165 -IH_PERF_SEL_CLIENT16_INT = 166 -IH_PERF_SEL_CLIENT17_INT = 167 -IH_PERF_SEL_CLIENT18_INT = 168 -IH_PERF_SEL_CLIENT19_INT = 169 -IH_PERF_SEL_CLIENT20_INT = 170 -IH_PERF_SEL_CLIENT21_INT = 171 -IH_PERF_SEL_CLIENT22_INT = 172 -IH_PERF_SEL_CLIENT23_INT = 173 -IH_PERF_SEL_CLIENT24_INT = 174 -IH_PERF_SEL_CLIENT25_INT = 175 -IH_PERF_SEL_CLIENT26_INT = 176 -IH_PERF_SEL_CLIENT27_INT = 177 -IH_PERF_SEL_CLIENT28_INT = 178 -IH_PERF_SEL_CLIENT29_INT = 179 -IH_PERF_SEL_CLIENT30_INT = 180 -IH_PERF_SEL_CLIENT31_INT = 181 -Reserved182 = 182 -Reserved183 = 183 -Reserved184 = 184 -Reserved185 = 185 -Reserved186 = 186 -Reserved187 = 187 -Reserved188 = 188 -Reserved189 = 189 -Reserved190 = 190 -Reserved191 = 191 -Reserved192 = 192 -Reserved193 = 193 -Reserved194 = 194 -Reserved195 = 195 -Reserved196 = 196 -Reserved197 = 197 -Reserved198 = 198 -Reserved199 = 199 -Reserved200 = 200 -Reserved201 = 201 -Reserved202 = 202 -Reserved203 = 203 -Reserved204 = 204 -Reserved205 = 205 -Reserved206 = 206 -Reserved207 = 207 -Reserved208 = 208 -Reserved209 = 209 -Reserved210 = 210 -Reserved211 = 211 -Reserved212 = 212 -Reserved213 = 213 -Reserved214 = 214 -Reserved215 = 215 -Reserved216 = 216 -Reserved217 = 217 -Reserved218 = 218 -Reserved219 = 219 -IH_PERF_SEL_RB1_FULL_VF0 = 220 -IH_PERF_SEL_RB1_FULL_VF1 = 221 -IH_PERF_SEL_RB1_FULL_VF2 = 222 -IH_PERF_SEL_RB1_FULL_VF3 = 223 -IH_PERF_SEL_RB1_FULL_VF4 = 224 -IH_PERF_SEL_RB1_FULL_VF5 = 225 -IH_PERF_SEL_RB1_FULL_VF6 = 226 -IH_PERF_SEL_RB1_FULL_VF7 = 227 -IH_PERF_SEL_RB1_FULL_VF8 = 228 -IH_PERF_SEL_RB1_FULL_VF9 = 229 -IH_PERF_SEL_RB1_FULL_VF10 = 230 -IH_PERF_SEL_RB1_FULL_VF11 = 231 -IH_PERF_SEL_RB1_FULL_VF12 = 232 -IH_PERF_SEL_RB1_FULL_VF13 = 233 -IH_PERF_SEL_RB1_FULL_VF14 = 234 -IH_PERF_SEL_RB1_FULL_VF15 = 235 -IH_PERF_SEL_RB1_OVERFLOW_VF0 = 236 -IH_PERF_SEL_RB1_OVERFLOW_VF1 = 237 -IH_PERF_SEL_RB1_OVERFLOW_VF2 = 238 -IH_PERF_SEL_RB1_OVERFLOW_VF3 = 239 -IH_PERF_SEL_RB1_OVERFLOW_VF4 = 240 -IH_PERF_SEL_RB1_OVERFLOW_VF5 = 241 -IH_PERF_SEL_RB1_OVERFLOW_VF6 = 242 -IH_PERF_SEL_RB1_OVERFLOW_VF7 = 243 -IH_PERF_SEL_RB1_OVERFLOW_VF8 = 244 -IH_PERF_SEL_RB1_OVERFLOW_VF9 = 245 -IH_PERF_SEL_RB1_OVERFLOW_VF10 = 246 -IH_PERF_SEL_RB1_OVERFLOW_VF11 = 247 -IH_PERF_SEL_RB1_OVERFLOW_VF12 = 248 -IH_PERF_SEL_RB1_OVERFLOW_VF13 = 249 -IH_PERF_SEL_RB1_OVERFLOW_VF14 = 250 -IH_PERF_SEL_RB1_OVERFLOW_VF15 = 251 -Reserved252 = 252 -Reserved253 = 253 -Reserved254 = 254 -Reserved255 = 255 -Reserved256 = 256 -Reserved257 = 257 -Reserved258 = 258 -Reserved259 = 259 -Reserved260 = 260 -Reserved261 = 261 -Reserved262 = 262 -Reserved263 = 263 -Reserved264 = 264 -Reserved265 = 265 -Reserved266 = 266 -Reserved267 = 267 -IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 268 -IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 269 -IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 270 -IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 271 -IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 272 -IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 273 -IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 274 -IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 275 -IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 276 -IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 277 -IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 278 -IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 279 -IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 280 -IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 281 -IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 282 -IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 283 -IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 284 -IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 285 -IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 286 -IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 287 -IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 288 -IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 289 -IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 290 -IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 291 -IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 292 -IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 293 -IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 294 -IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 295 -IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 296 -IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 297 -IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 298 -IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 299 -Reserved300 = 300 -Reserved301 = 301 -Reserved302 = 302 -Reserved303 = 303 -Reserved304 = 304 -Reserved305 = 305 -Reserved306 = 306 -Reserved307 = 307 -Reserved308 = 308 -Reserved309 = 309 -Reserved310 = 310 -Reserved311 = 311 -Reserved312 = 312 -Reserved313 = 313 -Reserved314 = 314 -Reserved315 = 315 -Reserved316 = 316 -Reserved317 = 317 -Reserved318 = 318 -Reserved319 = 319 -Reserved320 = 320 -Reserved321 = 321 -Reserved322 = 322 -Reserved323 = 323 -Reserved324 = 324 -Reserved325 = 325 -Reserved326 = 326 -Reserved327 = 327 -Reserved328 = 328 -Reserved329 = 329 -Reserved330 = 330 -Reserved331 = 331 -IH_PERF_SEL_RB2_FULL_VF0 = 332 -IH_PERF_SEL_RB2_FULL_VF1 = 333 -IH_PERF_SEL_RB2_FULL_VF2 = 334 -IH_PERF_SEL_RB2_FULL_VF3 = 335 -IH_PERF_SEL_RB2_FULL_VF4 = 336 -IH_PERF_SEL_RB2_FULL_VF5 = 337 -IH_PERF_SEL_RB2_FULL_VF6 = 338 -IH_PERF_SEL_RB2_FULL_VF7 = 339 -IH_PERF_SEL_RB2_FULL_VF8 = 340 -IH_PERF_SEL_RB2_FULL_VF9 = 341 -IH_PERF_SEL_RB2_FULL_VF10 = 342 -IH_PERF_SEL_RB2_FULL_VF11 = 343 -IH_PERF_SEL_RB2_FULL_VF12 = 344 -IH_PERF_SEL_RB2_FULL_VF13 = 345 -IH_PERF_SEL_RB2_FULL_VF14 = 346 -IH_PERF_SEL_RB2_FULL_VF15 = 347 -IH_PERF_SEL_RB2_OVERFLOW_VF0 = 348 -IH_PERF_SEL_RB2_OVERFLOW_VF1 = 349 -IH_PERF_SEL_RB2_OVERFLOW_VF2 = 350 -IH_PERF_SEL_RB2_OVERFLOW_VF3 = 351 -IH_PERF_SEL_RB2_OVERFLOW_VF4 = 352 -IH_PERF_SEL_RB2_OVERFLOW_VF5 = 353 -IH_PERF_SEL_RB2_OVERFLOW_VF6 = 354 -IH_PERF_SEL_RB2_OVERFLOW_VF7 = 355 -IH_PERF_SEL_RB2_OVERFLOW_VF8 = 356 -IH_PERF_SEL_RB2_OVERFLOW_VF9 = 357 -IH_PERF_SEL_RB2_OVERFLOW_VF10 = 358 -IH_PERF_SEL_RB2_OVERFLOW_VF11 = 359 -IH_PERF_SEL_RB2_OVERFLOW_VF12 = 360 -IH_PERF_SEL_RB2_OVERFLOW_VF13 = 361 -IH_PERF_SEL_RB2_OVERFLOW_VF14 = 362 -IH_PERF_SEL_RB2_OVERFLOW_VF15 = 363 -Reserved364 = 364 -Reserved365 = 365 -Reserved366 = 366 -Reserved367 = 367 -Reserved368 = 368 -Reserved369 = 369 -Reserved370 = 370 -Reserved371 = 371 -Reserved372 = 372 -Reserved373 = 373 -Reserved374 = 374 -Reserved375 = 375 -Reserved376 = 376 -Reserved377 = 377 -Reserved378 = 378 -Reserved379 = 379 -IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 380 -IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 381 -IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 382 -IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 383 -IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 384 -IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 385 -IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 386 -IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 387 -IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 388 -IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 389 -IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 390 -IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 391 -IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 392 -IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 393 -IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 394 -IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 395 -IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 396 -IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 397 -IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 398 -IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 399 -IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 400 -IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 401 -IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 402 -IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 403 -IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 404 -IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 405 -IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 406 -IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 407 -IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 408 -IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 409 -IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 410 -IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 411 -Reserved412 = 412 -Reserved413 = 413 -Reserved414 = 414 -Reserved415 = 415 -Reserved416 = 416 -Reserved417 = 417 -Reserved418 = 418 -Reserved419 = 419 -Reserved420 = 420 -Reserved421 = 421 -Reserved422 = 422 -Reserved423 = 423 -Reserved424 = 424 -Reserved425 = 425 -Reserved426 = 426 -Reserved427 = 427 -Reserved428 = 428 -Reserved429 = 429 -Reserved430 = 430 -Reserved431 = 431 -Reserved432 = 432 -Reserved433 = 433 -Reserved434 = 434 -Reserved435 = 435 -Reserved436 = 436 -Reserved437 = 437 -Reserved438 = 438 -Reserved439 = 439 -Reserved440 = 440 -Reserved441 = 441 -Reserved442 = 442 -Reserved443 = 443 -Reserved444 = 444 -Reserved445 = 445 -Reserved446 = 446 -Reserved447 = 447 -Reserved448 = 448 -Reserved449 = 449 -Reserved450 = 450 -Reserved451 = 451 -Reserved452 = 452 -Reserved453 = 453 -Reserved454 = 454 -Reserved455 = 455 -Reserved456 = 456 -Reserved457 = 457 -Reserved458 = 458 -Reserved459 = 459 -Reserved460 = 460 -Reserved461 = 461 -Reserved462 = 462 -Reserved463 = 463 -Reserved464 = 464 -Reserved465 = 465 -Reserved466 = 466 -Reserved467 = 467 -Reserved468 = 468 -Reserved469 = 469 -Reserved470 = 470 -Reserved471 = 471 -Reserved472 = 472 -Reserved473 = 473 -Reserved474 = 474 -Reserved475 = 475 -Reserved476 = 476 -Reserved477 = 477 -Reserved478 = 478 -Reserved479 = 479 -Reserved480 = 480 -Reserved481 = 481 -Reserved482 = 482 -Reserved483 = 483 -Reserved484 = 484 -Reserved485 = 485 -Reserved486 = 486 -Reserved487 = 487 -Reserved488 = 488 -Reserved489 = 489 -Reserved490 = 490 -Reserved491 = 491 -Reserved492 = 492 -Reserved493 = 493 -Reserved494 = 494 -Reserved495 = 495 -Reserved496 = 496 -Reserved497 = 497 -Reserved498 = 498 -Reserved499 = 499 -Reserved500 = 500 -Reserved501 = 501 -Reserved502 = 502 -Reserved503 = 503 -Reserved504 = 504 -Reserved505 = 505 -Reserved506 = 506 -Reserved507 = 507 -Reserved508 = 508 -Reserved509 = 509 -Reserved510 = 510 -Reserved511 = 511 -IH_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SEM_PERF_SEL' -SEM_PERF_SEL__enumvalues = { - 0: 'SEM_PERF_SEL_CYCLE', - 1: 'SEM_PERF_SEL_IDLE', - 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', - 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', - 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', - 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', - 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', - 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', - 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', - 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', - 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', - 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', - 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', - 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', - 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', - 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 166: 'SEM_PERF_SEL_MC_RD_REQ', - 167: 'SEM_PERF_SEL_MC_RD_RET', - 168: 'SEM_PERF_SEL_MC_WR_REQ', - 169: 'SEM_PERF_SEL_MC_WR_RET', - 170: 'SEM_PERF_SEL_ATC_REQ', - 171: 'SEM_PERF_SEL_ATC_RET', - 172: 'SEM_PERF_SEL_ATC_XNACK', - 173: 'SEM_PERF_SEL_ATC_INVALIDATION', -} -SEM_PERF_SEL_CYCLE = 0 -SEM_PERF_SEL_IDLE = 1 -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 -SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 -SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 -SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 -SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 -SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 -SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 -SEM_PERF_SEL_UVD_REQ_WAIT = 22 -SEM_PERF_SEL_VCE0_REQ_WAIT = 23 -SEM_PERF_SEL_ACP_REQ_WAIT = 24 -SEM_PERF_SEL_ISP_REQ_WAIT = 25 -SEM_PERF_SEL_VCE1_REQ_WAIT = 26 -SEM_PERF_SEL_VP8_REQ_WAIT = 27 -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 -SEM_PERF_SEL_MC_RD_REQ = 166 -SEM_PERF_SEL_MC_RD_RET = 167 -SEM_PERF_SEL_MC_WR_REQ = 168 -SEM_PERF_SEL_MC_WR_RET = 169 -SEM_PERF_SEL_ATC_REQ = 170 -SEM_PERF_SEL_ATC_RET = 171 -SEM_PERF_SEL_ATC_XNACK = 172 -SEM_PERF_SEL_ATC_INVALIDATION = 173 -SEM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERF_SEL' -SDMA_PERF_SEL__enumvalues = { - 0: 'SDMA_PERF_SEL_CYCLE', - 1: 'SDMA_PERF_SEL_IDLE', - 2: 'SDMA_PERF_SEL_REG_IDLE', - 3: 'SDMA_PERF_SEL_RB_EMPTY', - 4: 'SDMA_PERF_SEL_RB_FULL', - 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERF_SEL_RB_RPTR_WB', - 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERF_SEL_RB_CMD_FULL', - 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERF_SEL_IB_CMD_FULL', - 13: 'SDMA_PERF_SEL_EX_IDLE', - 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERF_SEL_MC_WR_IDLE', - 17: 'SDMA_PERF_SEL_MC_WR_COUNT', - 18: 'SDMA_PERF_SEL_MC_RD_IDLE', - 19: 'SDMA_PERF_SEL_MC_RD_COUNT', - 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'SDMA_PERF_SEL_SEM_IDLE', - 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'SDMA_PERF_SEL_INT_IDLE', - 31: 'SDMA_PERF_SEL_INT_REQ_STALL', - 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'SDMA_PERF_SEL_NUM_PACKET', - 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'SDMA_PERF_SEL_CE_WR_IDLE', - 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'SDMA_PERF_SEL_CE_IN_IDLE', - 43: 'SDMA_PERF_SEL_CE_DST_IDLE', - 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'SDMA_PERF_SEL_CE_INFO_FULL', - 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'SDMA_PERF_SEL_CE_RD_STALL', - 52: 'SDMA_PERF_SEL_CE_WR_STALL', - 53: 'SDMA_PERF_SEL_GFX_SELECT', - 54: 'SDMA_PERF_SEL_RLC0_SELECT', - 55: 'SDMA_PERF_SEL_RLC1_SELECT', - 56: 'SDMA_PERF_SEL_PAGE_SELECT', - 57: 'SDMA_PERF_SEL_CTX_CHANGE', - 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'SDMA_PERF_SEL_DOORBELL', - 61: 'SDMA_PERF_SEL_RD_BA_RTR', - 62: 'SDMA_PERF_SEL_WR_BA_RTR', - 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERF_SEL_CE_L1_STALL', - 66: 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', - 67: 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 68: 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 69: 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 70: 'SDMA_PERF_SEL_ATCL2_RET_XNACK', - 71: 'SDMA_PERF_SEL_ATCL2_RET_ACK', - 72: 'SDMA_PERF_SEL_ATCL2_FREE', - 73: 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', - 74: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 75: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', - 76: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 77: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', - 78: 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', - 79: 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 80: 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 81: 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 82: 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 83: 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 84: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 85: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 86: 'SDMA_PERF_SEL_L1_WR_INV_EN', - 87: 'SDMA_PERF_SEL_L1_RD_INV_EN', - 88: 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 89: 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 90: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 91: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 92: 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 93: 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 94: 'SDMA_PERF_SEL_L1_INV_MIDDLE', - 254: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', - 255: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', -} -SDMA_PERF_SEL_CYCLE = 0 -SDMA_PERF_SEL_IDLE = 1 -SDMA_PERF_SEL_REG_IDLE = 2 -SDMA_PERF_SEL_RB_EMPTY = 3 -SDMA_PERF_SEL_RB_FULL = 4 -SDMA_PERF_SEL_RB_WPTR_WRAP = 5 -SDMA_PERF_SEL_RB_RPTR_WRAP = 6 -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERF_SEL_RB_RPTR_WB = 8 -SDMA_PERF_SEL_RB_CMD_IDLE = 9 -SDMA_PERF_SEL_RB_CMD_FULL = 10 -SDMA_PERF_SEL_IB_CMD_IDLE = 11 -SDMA_PERF_SEL_IB_CMD_FULL = 12 -SDMA_PERF_SEL_EX_IDLE = 13 -SDMA_PERF_SEL_SRBM_REG_SEND = 14 -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERF_SEL_MC_WR_IDLE = 16 -SDMA_PERF_SEL_MC_WR_COUNT = 17 -SDMA_PERF_SEL_MC_RD_IDLE = 18 -SDMA_PERF_SEL_MC_RD_COUNT = 19 -SDMA_PERF_SEL_MC_RD_RET_STALL = 20 -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -SDMA_PERF_SEL_SEM_IDLE = 24 -SDMA_PERF_SEL_SEM_REQ_STALL = 25 -SDMA_PERF_SEL_SEM_REQ_COUNT = 26 -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -SDMA_PERF_SEL_SEM_RESP_FAIL = 28 -SDMA_PERF_SEL_SEM_RESP_PASS = 29 -SDMA_PERF_SEL_INT_IDLE = 30 -SDMA_PERF_SEL_INT_REQ_STALL = 31 -SDMA_PERF_SEL_INT_REQ_COUNT = 32 -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -SDMA_PERF_SEL_INT_RESP_RETRY = 34 -SDMA_PERF_SEL_NUM_PACKET = 35 -SDMA_PERF_SEL_CE_WREQ_IDLE = 37 -SDMA_PERF_SEL_CE_WR_IDLE = 38 -SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -SDMA_PERF_SEL_CE_RREQ_IDLE = 40 -SDMA_PERF_SEL_CE_OUT_IDLE = 41 -SDMA_PERF_SEL_CE_IN_IDLE = 42 -SDMA_PERF_SEL_CE_DST_IDLE = 43 -SDMA_PERF_SEL_CE_AFIFO_FULL = 46 -SDMA_PERF_SEL_CE_INFO_FULL = 49 -SDMA_PERF_SEL_CE_INFO1_FULL = 50 -SDMA_PERF_SEL_CE_RD_STALL = 51 -SDMA_PERF_SEL_CE_WR_STALL = 52 -SDMA_PERF_SEL_GFX_SELECT = 53 -SDMA_PERF_SEL_RLC0_SELECT = 54 -SDMA_PERF_SEL_RLC1_SELECT = 55 -SDMA_PERF_SEL_PAGE_SELECT = 56 -SDMA_PERF_SEL_CTX_CHANGE = 57 -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -SDMA_PERF_SEL_DOORBELL = 60 -SDMA_PERF_SEL_RD_BA_RTR = 61 -SDMA_PERF_SEL_WR_BA_RTR = 62 -SDMA_PERF_SEL_F32_L1_WR_VLD = 63 -SDMA_PERF_SEL_CE_L1_WR_VLD = 64 -SDMA_PERF_SEL_CE_L1_STALL = 65 -SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 -SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 -SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 -SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 -SDMA_PERF_SEL_ATCL2_RET_XNACK = 70 -SDMA_PERF_SEL_ATCL2_RET_ACK = 71 -SDMA_PERF_SEL_ATCL2_FREE = 72 -SDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 -SDMA_PERF_SEL_DMA_L1_WR_SEND = 74 -SDMA_PERF_SEL_DMA_L1_RD_SEND = 75 -SDMA_PERF_SEL_DMA_MC_WR_SEND = 76 -SDMA_PERF_SEL_DMA_MC_RD_SEND = 77 -SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 -SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 -SDMA_PERF_SEL_L1_WRL2_IDLE = 80 -SDMA_PERF_SEL_L1_RDL2_IDLE = 81 -SDMA_PERF_SEL_L1_WRMC_IDLE = 82 -SDMA_PERF_SEL_L1_RDMC_IDLE = 83 -SDMA_PERF_SEL_L1_WR_INV_IDLE = 84 -SDMA_PERF_SEL_L1_RD_INV_IDLE = 85 -SDMA_PERF_SEL_L1_WR_INV_EN = 86 -SDMA_PERF_SEL_L1_RD_INV_EN = 87 -SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 -SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 -SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 -SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 -SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 -SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 -SDMA_PERF_SEL_L1_INV_MIDDLE = 94 -SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 254 -SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 255 -SDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_XDMA_LOCAL_SW_MODE' -ENUM_XDMA_LOCAL_SW_MODE__enumvalues = { - 2: 'XDMA_LOCAL_SW_MODE_SW_256B_D', - 10: 'XDMA_LOCAL_SW_MODE_SW_64KB_D', - 26: 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', -} -XDMA_LOCAL_SW_MODE_SW_256B_D = 2 -XDMA_LOCAL_SW_MODE_SW_64KB_D = 10 -XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 26 -ENUM_XDMA_LOCAL_SW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_XDMA_SLV_ALPHA_POSITION' -ENUM_XDMA_SLV_ALPHA_POSITION__enumvalues = { - 0: 'XDMA_SLV_ALPHA_POSITION_7_0', - 1: 'XDMA_SLV_ALPHA_POSITION_15_8', - 2: 'XDMA_SLV_ALPHA_POSITION_23_16', - 3: 'XDMA_SLV_ALPHA_POSITION_31_24', -} -XDMA_SLV_ALPHA_POSITION_7_0 = 0 -XDMA_SLV_ALPHA_POSITION_15_8 = 1 -XDMA_SLV_ALPHA_POSITION_23_16 = 2 -XDMA_SLV_ALPHA_POSITION_31_24 = 3 -ENUM_XDMA_SLV_ALPHA_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_XDMA_MSTR_ALPHA_POSITION' -ENUM_XDMA_MSTR_ALPHA_POSITION__enumvalues = { - 0: 'XDMA_MSTR_ALPHA_POSITION_7_0', - 1: 'XDMA_MSTR_ALPHA_POSITION_15_8', - 2: 'XDMA_MSTR_ALPHA_POSITION_23_16', - 3: 'XDMA_MSTR_ALPHA_POSITION_31_24', -} -XDMA_MSTR_ALPHA_POSITION_7_0 = 0 -XDMA_MSTR_ALPHA_POSITION_15_8 = 1 -XDMA_MSTR_ALPHA_POSITION_23_16 = 2 -XDMA_MSTR_ALPHA_POSITION_31_24 = 3 -ENUM_XDMA_MSTR_ALPHA_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL' -ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL__enumvalues = { - 0: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', - 1: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', - 2: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', - 3: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', - 4: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', - 5: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', -} -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0 -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 1 -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 2 -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 3 -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 4 -XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 5 -ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL = ctypes.c_uint32 # enum -__all__ = \ - ['ABGR_TO_A_BG_G_RB', 'ABM_SOFT_RESET', 'ABM_SOFT_RESET_0', - 'ABM_SOFT_RESET_1', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', - 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ADDR_CONFIG_16_BANK', - 'ADDR_CONFIG_16_PIPE', 'ADDR_CONFIG_1KB_ROW', - 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', - 'ADDR_CONFIG_1_LOWER_PIPES', - 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', - 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', - 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', - 'ADDR_CONFIG_2_LOWER_PIPES', - 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', - 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', - 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', - 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', - 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', - 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_8_BANK', - 'ADDR_CONFIG_8_GPU', 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', - 'ADDR_CONFIG_8_PIPE', 'ADDR_CONFIG_8_SHADER_ENGINE', - 'ADDR_CONFIG_BANK_INTERLEAVE_1', 'ADDR_CONFIG_BANK_INTERLEAVE_2', - 'ADDR_CONFIG_BANK_INTERLEAVE_4', 'ADDR_CONFIG_BANK_INTERLEAVE_8', - 'ADDR_CONFIG_DISABLE_SE', 'ADDR_CONFIG_ENABLE_SE', - 'ADDR_CONFIG_GPU_TILE_128', 'ADDR_CONFIG_GPU_TILE_16', - 'ADDR_CONFIG_GPU_TILE_32', 'ADDR_CONFIG_GPU_TILE_64', - 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', - 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', - 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', - 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', - 'ADDR_CONFIG_SE_TILE_32', 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', - 'ADDR_SURF_4_BANK', 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', - 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', - 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', - 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', - 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', - 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', - 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', - 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', - 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', - 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', - 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16_32x32_16x16', - 'ADDR_SURF_P16_32x32_8x16', 'ADDR_SURF_P2', - 'ADDR_SURF_P2_RESERVED0', 'ADDR_SURF_P2_RESERVED1', - 'ADDR_SURF_P2_RESERVED2', 'ADDR_SURF_P4_16x16', - 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', 'ADDR_SURF_P4_8x16', - 'ADDR_SURF_P8_16x16_8x16', 'ADDR_SURF_P8_16x32_16x16', - 'ADDR_SURF_P8_16x32_8x16', 'ADDR_SURF_P8_32x32_16x16', - 'ADDR_SURF_P8_32x32_16x32', 'ADDR_SURF_P8_32x32_8x16', - 'ADDR_SURF_P8_32x64_32x32', 'ADDR_SURF_P8_RESERVED0', - 'ADDR_SURF_ROTATED_MICRO_TILING', 'ADDR_SURF_SAMPLE_SPLIT_1', - 'ADDR_SURF_SAMPLE_SPLIT_2', 'ADDR_SURF_SAMPLE_SPLIT_4', - 'ADDR_SURF_SAMPLE_SPLIT_8', 'ADDR_SURF_THICK_MICRO_TILING', - 'ADDR_SURF_THIN_MICRO_TILING', 'ADDR_SURF_TILE_SPLIT_128B', - 'ADDR_SURF_TILE_SPLIT_1KB', 'ADDR_SURF_TILE_SPLIT_256B', - 'ADDR_SURF_TILE_SPLIT_2KB', 'ADDR_SURF_TILE_SPLIT_4KB', - 'ADDR_SURF_TILE_SPLIT_512B', 'ADDR_SURF_TILE_SPLIT_64B', - 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', - 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', - 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', - 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', - 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', - 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', - 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', - 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', - 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', - 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', - 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', - 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', - 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', - 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', - 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', - 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', - 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', - 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', - 'AFMT_INTERRUPT_STATUS_CHG_MASK', - 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', - 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', - 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', - 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', - 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', - 'AOUT_CRC_CONT', 'AOUT_CRC_CONT_EN', 'AOUT_CRC_DISABLE', - 'AOUT_CRC_ENABLE', 'AOUT_CRC_NO_RESET', 'AOUT_CRC_ONE_SHOT', - 'AOUT_CRC_RESET', 'AOUT_CRC_SOFT_RESET', 'AOUT_CRC_TEST_EN', - 'AOUT_DISABLE', 'AOUT_EN', 'AOUT_ENABLE', 'AOUT_FIFO_START_ADDR', - 'AOUT_FIFO_START_ADDR_2', 'AOUT_FIFO_START_ADDR_3', 'ARRAY_1D', - 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', 'ARRAY_2D', - 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', 'ARRAY_2D_COLOR', - 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', 'ARRAY_2D_TILED_THIN1', - 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', 'ARRAY_3D_SLICE', - 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', - 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', - 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', - 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', - 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', - 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', - 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', - 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', - 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', - 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', - 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', - 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', - 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', - 'AZ_RIRB_WRITE_POINTER_DO_RESET', - 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', - 'AZ_STATE_CHANGE_STATUS', - 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', - 'Available_0x1c', 'Available_0x1d', 'BGRA_TO_BG_G_RB_A', - 'BINNER_BREAK_BATCH', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', - 'BINNING_ALLOWED', 'BLEND_BOTH_INV_SRC_ALPHA', - 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', - 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', - 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', - 'BLEND_ONE_MINUS_CONSTANT_ALPHA', - 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', - 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', - 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', - 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', - 'BLEND_SRC_COLOR', 'BLEND_ZERO', - 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', - 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', - 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', - 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN', - 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', - 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', - 'BLNDV_CONTROL2_PTI_ENABLE', 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', - 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', - 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', - 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', - 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', - 'BLNDV_CONTROL_BLND_ALPHA_MODE', - 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', - 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', - 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', - 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN', - 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', - 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', - 'BLNDV_CONTROL_BLND_MODE', - 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', - 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', - 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', - 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', - 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE', - 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', - 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', - 'BLNDV_CONTROL_BLND_STEREO_POLARITY', - 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', - 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', - 'BLNDV_CONTROL_BLND_STEREO_TYPE', - 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', - 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', - 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', - 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', - 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT', - 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', - 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', - 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE', - 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', - 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE', - 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', - 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', - 'BLNDV_SM_CONTROL2_SM_MODE', - 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', - 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', - 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', - 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', - 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', - 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', - 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', - 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', - 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', - 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', - 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', - 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', - 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', - 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', - 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN', - 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', - 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', - 'BLND_CONTROL2_PTI_ENABLE', 'BLND_CONTROL2_PTI_ENABLE_FALSE', - 'BLND_CONTROL2_PTI_ENABLE_TRUE', - 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', - 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', - 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', - 'BLND_CONTROL_BLND_ALPHA_MODE', - 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', - 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', - 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', - 'BLND_CONTROL_BLND_FEEDTHROUGH_EN', - 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', - 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', 'BLND_CONTROL_BLND_MODE', - 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', - 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', - 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', - 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', - 'BLND_CONTROL_BLND_MULTIPLIED_MODE', - 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', - 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', - 'BLND_CONTROL_BLND_STEREO_POLARITY', - 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', - 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', - 'BLND_CONTROL_BLND_STEREO_TYPE', - 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', - 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', - 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', - 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', - 'BLND_DEBUG_BLND_CNV_MUX_SELECT', - 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', - 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', - 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE', - 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', - 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE', - 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', - 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', - 'BLND_SM_CONTROL2_SM_MODE', - 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', - 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', - 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', - 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', - 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', - 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', - 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', - 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', - 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', - 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', - 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', - 'BLOCK_CONTEXT_DONE', 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', - 'BUF_DATA_FORMAT', 'BUF_DATA_FORMAT_10_10_10_2', - 'BUF_DATA_FORMAT_10_11_11', 'BUF_DATA_FORMAT_11_11_10', - 'BUF_DATA_FORMAT_16', 'BUF_DATA_FORMAT_16_16', - 'BUF_DATA_FORMAT_16_16_16_16', 'BUF_DATA_FORMAT_2_10_10_10', - 'BUF_DATA_FORMAT_32', 'BUF_DATA_FORMAT_32_32', - 'BUF_DATA_FORMAT_32_32_32', 'BUF_DATA_FORMAT_32_32_32_32', - 'BUF_DATA_FORMAT_8', 'BUF_DATA_FORMAT_8_8', - 'BUF_DATA_FORMAT_8_8_8_8', 'BUF_DATA_FORMAT_INVALID', - 'BUF_DATA_FORMAT_RESERVED_15', 'BUF_NUM_FORMAT', - 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', - 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SSCALED', - 'BUF_NUM_FORMAT_UINT', 'BUF_NUM_FORMAT_UNORM', - 'BUF_NUM_FORMAT_UNORM_UINT', 'BUF_NUM_FORMAT_USCALED', - 'BankHeight', 'BankInterleaveSize', 'BankSwapBytes', 'BankTiling', - 'BankWidth', 'BankWidthHeight', 'BinEventCntl', 'BinningMode', - 'BlendOp', 'BlendOpt', 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', - 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CBMode', - 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', - 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', 'CB_DISABLE', - 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', 'CB_NORMAL', - 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', - 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', - 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', - 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', - 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', - 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', - 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', - 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', - 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', - 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', - 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', - 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', - 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', - 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', - 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', - 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', - 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', - 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', - 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', - 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', - 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', - 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', - 'CB_PERF_SEL_CMASK_READ_DATA_0xD', - 'CB_PERF_SEL_CMASK_READ_DATA_0xE', - 'CB_PERF_SEL_CMASK_READ_DATA_0xF', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', - 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', - 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', - 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', - 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', - 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CM_CACHE_TAG_MISS', - 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', - 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', - 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', - 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', - 'CB_PERF_SEL_CM_MC_READ_REQUEST', - 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', - 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', - 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', - 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', - 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', - 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', - 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', - 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', - 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', - 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', - 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', - 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', - 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_FC_CACHE_TAG_MISS', - 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', - 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', - 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', - 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', - 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', - 'CB_PERF_SEL_FC_DCC_CACHE_STALL', - 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', - 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', - 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', - 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', - 'CB_PERF_SEL_FC_DOC_IS_STALLED', - 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', - 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', - 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', - 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', - 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', - 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', - 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', - 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', - 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', - 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_READ_REQUEST', - 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', - 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', - 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', - 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', - 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', - 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', - 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', - 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', - 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', - 'CB_PERF_SEL_FOP_IN_VALIDB_READY', - 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', - 'CB_PERF_SEL_FOP_IN_VALID_READY', - 'CB_PERF_SEL_FOP_IN_VALID_READYB', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', - 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', - 'CB_PERF_SEL_LQUAD_NO_TILE', - 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', - 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', 'CB_PERF_SEL_NONE', - 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', - 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', - 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', - 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', - 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', - 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', - 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', - 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', - 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', - 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', - 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', - 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', - 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', - 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', - 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', - 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', - 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', - 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', - 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', - 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', - 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', - 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', - 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', - 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', - 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', - 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', - 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', - 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', - 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESOLVE', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', - 'CHUB_TC_RET_CREDITS', 'CHUB_TC_RET_CREDITS_ENUM', - 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', - 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', - 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLED', - 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_ENABLED', - 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', - 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', - 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', - 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', - 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', - 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', - 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', - 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', - 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', - 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', - 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', - 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', - 'CMASK_CLR11_FX', 'CMD_EMBEDDED_MODE_DISABLE', - 'CMD_EMBEDDED_MODE_ENABLE', 'CM_GLOBAL_PASSTHROUGH_DISBALE', - 'CM_GLOBAL_PASSTHROUGH_ENABLE', 'COEF_UPDATE_COMPLETE', - 'COEF_UPDATE_NOT_COMPLETE', 'COLOR_10_10_10_2', 'COLOR_10_11_11', - 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', - 'COLOR_1_5_5_5', 'COLOR_24_8', 'COLOR_2_10_10_10', - 'COLOR_2_10_10_10_6E4', 'COLOR_32', 'COLOR_32_32', - 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', 'COLOR_5_5_5_1', - 'COLOR_5_6_5', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', - 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_RESERVED_13', - 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', 'COLOR_RESERVED_24', - 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', 'COLOR_RESERVED_27', - 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', 'COLOR_RESERVED_30', - 'COLOR_X24_8_32_FLOAT', 'COL_MAN_DEGAMMA_MODE', - 'COL_MAN_DENORM_CLAMP_CONTROL', 'COL_MAN_DISABLE_MULTIPLE_UPDATE', - 'COL_MAN_GAMUT_REMAP_MODE', 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE', - 'COL_MAN_INPUTCSC_CONVERT', 'COL_MAN_INPUTCSC_MODE', - 'COL_MAN_INPUTCSC_TYPE', 'COL_MAN_INPUT_GAMMA_MODE', - 'COL_MAN_MULTIPLE_UPDATE', 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', - 'COL_MAN_OUTPUT_CSC_A', 'COL_MAN_OUTPUT_CSC_B', - 'COL_MAN_OUTPUT_CSC_BYPASS', 'COL_MAN_OUTPUT_CSC_MODE', - 'COL_MAN_OUTPUT_CSC_RGB', 'COL_MAN_OUTPUT_CSC_UNITY', - 'COL_MAN_OUTPUT_CSC_YCrCb601', 'COL_MAN_OUTPUT_CSC_YCrCb709', - 'COL_MAN_PRESCALE_MODE', 'COL_MAN_REGAMMA_MODE_A', - 'COL_MAN_REGAMMA_MODE_B', 'COL_MAN_REGAMMA_MODE_BYPASS', - 'COL_MAN_REGAMMA_MODE_CONTROL', 'COL_MAN_REGAMMA_MODE_ROM_A', - 'COL_MAN_REGAMMA_MODE_ROM_B', 'COL_MAN_UPDATE_LOCK', - 'COL_MAN_UPDATE_LOCKED', 'COL_MAN_UPDATE_UNLOCKED', - 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', - 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPONENT_DEPTH_10BPC', - 'COMPONENT_DEPTH_12BPC', 'COMPONENT_DEPTH_16BPC', - 'COMPONENT_DEPTH_6BPC', 'COMPONENT_DEPTH_8BPC', - 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', 'CONFIG_1KB_ROW_OPT', - 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', 'CONFIG_1_PIPE', - 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', 'CONFIG_2KB_ROW', - 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', 'CONFIG_2_PIPE', - 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', 'CONFIG_4KB_SPLIT', - 'CONFIG_4_BANK', 'CONFIG_4_PIPE', 'CONFIG_512B_GROUP', - 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', 'CONFIG_8KB_ROW_OPT', - 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', 'CONFIG_8_PIPE', - 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', - 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', - 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', - 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', - 'CORB_READ_POINTER_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', - 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_PERFCOUNT_SEL', - 'CPC_PERF_SEL_ALWAYS_COUNT', - 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', - 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', - 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', - 'CPF_PERFCOUNT_SEL', 'CPF_PERF_SEL_ALWAYS_COUNT', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', - 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', - 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', - 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', - 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', - 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', - 'CPG_PERFCOUNT_SEL', 'CPG_PERF_SEL_ALWAYS_COUNT', - 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', - 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', - 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 'CPG_PERF_SEL_ME_PARSER_BUSY', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', - 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', - 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', - 'CP_ALPHA_TAG_RAM_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', - 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', - 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', - 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', - 'CRTC_ADD_PIXEL', 'CRTC_ADD_PIXEL_FORCE', 'CRTC_ADD_PIXEL_NOOP', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', - 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', - 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL', - 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', - 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', - 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', - 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE', - 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', - 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', - 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', - 'CRTC_CONTROL_CRTC_MASTER_EN', - 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', - 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', - 'CRTC_CONTROL_CRTC_SOF_PULL_EN', - 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', - 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', - 'CRTC_CONTROL_CRTC_START_POINT_CNTL', - 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', - 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', - 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN', - 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', - 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', - 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN', - 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', - 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', - 'CRTC_CRC_CNTL_CRTC_CRC_EN', 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', - 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', - 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE', - 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', - 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', - 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', - 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE', - 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', - 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', - 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', - 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', - 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS', - 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', - 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', - 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', - 'CRTC_DROP_PIXEL', 'CRTC_DROP_PIXEL_FORCE', - 'CRTC_DROP_PIXEL_NOOP', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE', - 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', - 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', - 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', - 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', - 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN', - 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', - 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', - 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', - 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', - 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', - 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', - 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', - 'CRTC_HORZ_REPETITION_COUNT', 'CRTC_HORZ_REPETITION_COUNT_0', - 'CRTC_HORZ_REPETITION_COUNT_1', 'CRTC_HORZ_REPETITION_COUNT_10', - 'CRTC_HORZ_REPETITION_COUNT_11', 'CRTC_HORZ_REPETITION_COUNT_12', - 'CRTC_HORZ_REPETITION_COUNT_13', 'CRTC_HORZ_REPETITION_COUNT_14', - 'CRTC_HORZ_REPETITION_COUNT_15', 'CRTC_HORZ_REPETITION_COUNT_2', - 'CRTC_HORZ_REPETITION_COUNT_3', 'CRTC_HORZ_REPETITION_COUNT_4', - 'CRTC_HORZ_REPETITION_COUNT_5', 'CRTC_HORZ_REPETITION_COUNT_6', - 'CRTC_HORZ_REPETITION_COUNT_7', 'CRTC_HORZ_REPETITION_COUNT_8', - 'CRTC_HORZ_REPETITION_COUNT_9', 'CRTC_H_SYNC_A_POL', - 'CRTC_H_SYNC_A_POL_HIGH', 'CRTC_H_SYNC_A_POL_LOW', - 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL', - 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', - 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', - 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', - 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', - 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE', - 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', - 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE', - 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', - 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', - 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', - 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR', - 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', - 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', - 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR', - 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', - 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', - 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL', - 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', - 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR', - 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', - 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', - 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY', - 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', - 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', - 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN', - 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', - 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', - 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN', - 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', - 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', - 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY', - 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', - 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', - 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', - 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE', - 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', - 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', - 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', - 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', - 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', - 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', - 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', - 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK', - 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', - 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', - 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE', - 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', - 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', - 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR', - 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', - 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE', - 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', - 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', - 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR', - 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', - 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', - 'CRTC_V_SYNC_A_POL', 'CRTC_V_SYNC_A_POL_HIGH', - 'CRTC_V_SYNC_A_POL_LOW', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL', - 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', - 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', - 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN', - 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', - 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', - 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', - 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', - 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', - 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', - 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR', - 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', - 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', - 'CSDATA_ADDR_WIDTH', 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', - 'CSDATA_TYPE_EVENT', 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', - 'CSDATA_TYPE_TG', 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', - 'CS_DONE', 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CmaskAddr', - 'CmaskCode', 'CmaskMode', 'ColorArray', 'ColorFormat', - 'ColorTransform', 'CombFunc', 'CompareFrag', 'CompareRef', - 'ConservativeZExport', 'CovToShaderSel', 'DACA_SOFT_RESET', - 'DACA_SOFT_RESET_0', 'DACA_SOFT_RESET_1', 'DAC_MUX_SELECT', - 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', 'DB_CACHE_FLUSH', - 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', - 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', - 'DB_CLK_SOFT_RESET', 'DB_CLK_SOFT_RESET_0', 'DB_CLK_SOFT_RESET_1', - 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', - 'DB_PEFF_SEL_prezl_tile_mem_stall', - 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 'DB_PERF_SEL_CB_DB_rdreq_sends', - 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 'DB_PERF_SEL_CB_DB_wrreq_sends', 'DB_PERF_SEL_DB_CB_lquad_busy', - 'DB_PERF_SEL_DB_CB_lquad_double_format', - 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', - 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', - 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', - 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', - 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', - 'DB_PERF_SEL_DB_SC_quad_busy', - 'DB_PERF_SEL_DB_SC_quad_double_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad', 'DB_PERF_SEL_DB_SC_quad_sends', - 'DB_PERF_SEL_DB_SC_quad_stalls', 'DB_PERF_SEL_DB_SC_quad_tiles', - 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', - 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', - 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 'DB_PERF_SEL_DB_SC_tile_stalls', - 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_tiles', - 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', - 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', - 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', - 'DB_PERF_SEL_DFSM_cycles_above_watermark', - 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', - 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', - 'DB_PERF_SEL_DFSM_full_cleared_squads_out', - 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', - 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', - 'DB_PERF_SEL_DFSM_lit_pixels_in', - 'DB_PERF_SEL_DFSM_lit_samples_in', - 'DB_PERF_SEL_DFSM_lit_samples_out', 'DB_PERF_SEL_DFSM_quads_in', - 'DB_PERF_SEL_DFSM_squads_in', - 'DB_PERF_SEL_DFSM_stalled_by_downstream', - 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 'DB_PERF_SEL_Depth_Tile_Cache_event', - 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 'DB_PERF_SEL_Plane_Cache_flushes', - 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', - 'DB_PERF_SEL_Plane_Cache_misses', - 'DB_PERF_SEL_Plane_Cache_starves', - 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 'DB_PERF_SEL_PostZ_Samples_failing_S', - 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 'DB_PERF_SEL_PreZ_Samples_failing_S', - 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 'DB_PERF_SEL_SC_DB_quad_busy', - 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_sends', - 'DB_PERF_SEL_SC_DB_quad_squads', 'DB_PERF_SEL_SC_DB_quad_tiles', - 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', - 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', - 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', - 'DB_PERF_SEL_SH_quads_outstanding_sum', - 'DB_PERF_SEL_SX_DB_quad_busy', - 'DB_PERF_SEL_SX_DB_quad_double_format', - 'DB_PERF_SEL_SX_DB_quad_export_quads', - 'DB_PERF_SEL_SX_DB_quad_exports', - 'DB_PERF_SEL_SX_DB_quad_fast_format', - 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', - 'DB_PERF_SEL_SX_DB_quad_sends', - 'DB_PERF_SEL_SX_DB_quad_slow_format', - 'DB_PERF_SEL_SX_DB_quad_stalls', - 'DB_PERF_SEL_Stencil_Cache_flushes', - 'DB_PERF_SEL_Stencil_Cache_frees', - 'DB_PERF_SEL_Stencil_Cache_hits', - 'DB_PERF_SEL_Stencil_Cache_misses', - 'DB_PERF_SEL_Stencil_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', - 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_surface_stall', - 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 'DB_PERF_SEL_Z_Cache_pmask_hits', - 'DB_PERF_SEL_Z_Cache_pmask_misses', - 'DB_PERF_SEL_Z_Cache_pmask_starves', - 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 'DB_PERF_SEL_clock_main_active', - 'DB_PERF_SEL_clock_mem_export_active', - 'DB_PERF_SEL_clock_reg_active', - 'DB_PERF_SEL_depth_bounds_qtiles_culled', - 'DB_PERF_SEL_di_dt_stall', 'DB_PERF_SEL_dk_squad_busy', - 'DB_PERF_SEL_dk_squad_sends', 'DB_PERF_SEL_dk_squad_stalls', - 'DB_PERF_SEL_dk_tile_busy', 'DB_PERF_SEL_dk_tile_quad_starves', - 'DB_PERF_SEL_dk_tile_sends', 'DB_PERF_SEL_dk_tile_stalls', - 'DB_PERF_SEL_dkg_tile_rate_tile', - 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', - 'DB_PERF_SEL_dtt_sm_slot_stall', - 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', - 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', - 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', - 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', - 'DB_PERF_SEL_esr_ps_src_in_squads', - 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_stall', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', - 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', - 'DB_PERF_SEL_etr_out_cb_tile_stall', - 'DB_PERF_SEL_etr_out_esr_stall', - 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', - 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', - 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', - 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', - 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', - 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', - 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', - 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', - 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', - 'DB_PERF_SEL_flush_compressed_stencil', - 'DB_PERF_SEL_flush_expanded_stencil', - 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', - 'DB_PERF_SEL_flush_single_stencil', - 'DB_PERF_SEL_his_qtiles_culled', 'DB_PERF_SEL_hiz_qtiles_culled', - 'DB_PERF_SEL_hiz_tc_read_starved', - 'DB_PERF_SEL_hiz_tc_write_stall', - 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', - 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', - 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', - 'DB_PERF_SEL_postzl_partial_launch', - 'DB_PERF_SEL_postzl_partial_waiting', - 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', - 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', - 'DB_PERF_SEL_postzl_src_in_sends', - 'DB_PERF_SEL_postzl_src_in_squads', - 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 'DB_PERF_SEL_postzl_src_in_stall', - 'DB_PERF_SEL_postzl_src_in_tile_rate', - 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_postzl_src_out_stall', - 'DB_PERF_SEL_postzl_tile_init_stall', - 'DB_PERF_SEL_postzl_tile_mem_stall', - 'DB_PERF_SEL_prezl_src_in_sends', - 'DB_PERF_SEL_prezl_src_in_squads', - 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 'DB_PERF_SEL_prezl_src_in_stall', - 'DB_PERF_SEL_prezl_src_in_tile_rate', - 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_prezl_src_out_stall', - 'DB_PERF_SEL_prezl_tile_init_stall', 'DB_PERF_SEL_qc_busy', - 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', - 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', - 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', - 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', - 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', - 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', - 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', - 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', - 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', - 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', - 'DB_PERF_SEL_tcp_dispatcher_flushes', - 'DB_PERF_SEL_tcp_dispatcher_reads', - 'DB_PERF_SEL_tcp_prefetcher_flushes', - 'DB_PERF_SEL_tcp_prefetcher_reads', - 'DB_PERF_SEL_tcp_preloader_flushes', - 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', - 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', - 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 'DB_PERF_SEL_tiles_decomp_on_expclear', - 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', - 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', - 'DB_PERF_SEL_tl_expand_squads', - 'DB_PERF_SEL_tl_flush_expand_squads', - 'DB_PERF_SEL_tl_in_fast_z_stall', - 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', - 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', - 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', - 'DB_PERF_SEL_tl_preZ_squads', - 'DB_PERF_SEL_tl_stencil_locked_stall', - 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', - 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', - 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', - 'DB_PERF_SEL_tsc_insert_summarize_stall', - 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', - 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 'DCCG_AUDIO_DTO_USE_512FBR_DTO', - 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', - 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', - 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', - 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', - 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', - 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', - 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', - 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', - 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_CRTC_SELECT', - 'DCCG_PERF_MODE_HSYNC', 'DCCG_PERF_MODE_HSYNC_NOOP', - 'DCCG_PERF_MODE_HSYNC_START', 'DCCG_PERF_MODE_VSYNC', - 'DCCG_PERF_MODE_VSYNC_NOOP', 'DCCG_PERF_MODE_VSYNC_START', - 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', - 'DCCG_PERF_SEL_CRTC0', 'DCCG_PERF_SEL_CRTC1', - 'DCCG_PERF_SEL_CRTC2', 'DCCG_PERF_SEL_CRTC3', - 'DCCG_PERF_SEL_CRTC4', 'DCCG_PERF_SEL_CRTC5', 'DCC_CT_AUTO', - 'DCC_CT_NONE', 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', - 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', - 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', - 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', - 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_CSEL0P9', - 'DCIOCHIP_AUX_CSEL1P1', 'DCIOCHIP_AUX_CSEL_DEC0P9', - 'DCIOCHIP_AUX_CSEL_DEC1P0', 'DCIOCHIP_AUX_CSEL_INC1P0', - 'DCIOCHIP_AUX_CSEL_INC1P1', 'DCIOCHIP_AUX_FALLSLEWSEL', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_RSEL0P9', - 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', - 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', - 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', - 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', - 'DCIOCHIP_DVO_VREFPON', 'DCIOCHIP_DVO_VREFPON_DISABLE', - 'DCIOCHIP_DVO_VREFPON_ENABLE', 'DCIOCHIP_DVO_VREFSEL', - 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', 'DCIOCHIP_DVO_VREFSEL_ONCHIP', - 'DCIOCHIP_ENABLE_2BIT', 'DCIOCHIP_ENABLE_4BIT', - 'DCIOCHIP_ENABLE_5BIT', 'DCIOCHIP_GPIO_I2C_DISABLE', - 'DCIOCHIP_GPIO_I2C_DRIVE', 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', - 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', 'DCIOCHIP_GPIO_I2C_EN', - 'DCIOCHIP_GPIO_I2C_ENABLE', 'DCIOCHIP_GPIO_I2C_MASK', - 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', - 'DCIOCHIP_GPIO_MASK_EN', 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', - 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', - 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', - 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', - 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', - 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', - 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', - 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', - 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', - 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', - 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', - 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', - 'DCIOCHIP_REF_27_SRC_SEL', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', - 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', - 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', - 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', - 'DCIO_BL_PWM_CNTL_BL_PWM_EN', - 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', - 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', - 'DCIO_BL_PWM_FRACTIONAL_ENABLE', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', - 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', - 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', - 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', - 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', - 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', - 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', - 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', - 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', - 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', - 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', - 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 'DCIO_DCO_DCFE_EXT_VSYNC_MUX', 'DCIO_DCO_EXT_VSYNC_MASK', - 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', - 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', - 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', - 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', - 'DCIO_DC_GENERICB_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', - 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL', - 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', - 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', - 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN', - 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', - 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', - 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', - 'DCIO_DC_GPIO_MACRO_DEBUG', 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', - 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', - 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', - 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', - 'DCIO_DC_GPIO_VIP_DEBUG', 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', - 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', 'DCIO_DC_GPU_TIMER_READ_SELECT', - 'DCIO_DC_GPU_TIMER_START_POSITION', - 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS', - 'DCIO_DC_PAD_EXTERN_SIG_SEL', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', - 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', - 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', - 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', - 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', - 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', - 'DCIO_DPCS_INTERRUPT_TYPE', - 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', - 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', - 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', - 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', - 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', - 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', - 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', - 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', - 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', - 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', - 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_CRTC0', - 'DCIO_EXT_VSYNC_MUX_CRTC1', 'DCIO_EXT_VSYNC_MUX_CRTC2', - 'DCIO_EXT_VSYNC_MUX_CRTC3', 'DCIO_EXT_VSYNC_MUX_CRTC4', - 'DCIO_EXT_VSYNC_MUX_CRTC5', 'DCIO_EXT_VSYNC_MUX_GENERICB', - 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', - 'DCIO_GENERICA_SEL_DACA_PIXCLK', - 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', - 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', - 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', - 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', - 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 'DCIO_GENERICA_SEL_GENERICA_DPRX', - 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', - 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', - 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', - 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', - 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', - 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', - 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', - 'DCIO_GENERICB_SEL_DACA_PIXCLK', - 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', - 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', - 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', - 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', - 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', - 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', - 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', - 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', - 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', - 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', - 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', - 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', - 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', - 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', - 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', - 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', - 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', - 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', - 'DCIO_GSL0_TIMING_SYNC_SEL', - 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', - 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', - 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', - 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', - 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', - 'DCIO_GSL1_TIMING_SYNC_SEL', - 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', - 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', - 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', - 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', - 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', - 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', - 'DCIO_GSL2_TIMING_SYNC_SEL', - 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', - 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', - 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', - 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', - 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL_SEL', - 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', - 'DCIO_GSL_SEL_GROUP_2', 'DCIO_GSL_VSYNC_SEL', - 'DCIO_GSL_VSYNC_SEL_PIPE0', 'DCIO_GSL_VSYNC_SEL_PIPE1', - 'DCIO_GSL_VSYNC_SEL_PIPE2', 'DCIO_GSL_VSYNC_SEL_PIPE3', - 'DCIO_GSL_VSYNC_SEL_PIPE4', 'DCIO_GSL_VSYNC_SEL_PIPE5', - 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', - 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', - 'DCIO_IMPCAL_STEP_DELAY', 'DCIO_IMPCAL_STEP_DELAY_10us', - 'DCIO_IMPCAL_STEP_DELAY_11us', 'DCIO_IMPCAL_STEP_DELAY_12us', - 'DCIO_IMPCAL_STEP_DELAY_13us', 'DCIO_IMPCAL_STEP_DELAY_14us', - 'DCIO_IMPCAL_STEP_DELAY_15us', 'DCIO_IMPCAL_STEP_DELAY_16us', - 'DCIO_IMPCAL_STEP_DELAY_1us', 'DCIO_IMPCAL_STEP_DELAY_2us', - 'DCIO_IMPCAL_STEP_DELAY_3us', 'DCIO_IMPCAL_STEP_DELAY_4us', - 'DCIO_IMPCAL_STEP_DELAY_5us', 'DCIO_IMPCAL_STEP_DELAY_6us', - 'DCIO_IMPCAL_STEP_DELAY_7us', 'DCIO_IMPCAL_STEP_DELAY_8us', - 'DCIO_IMPCAL_STEP_DELAY_9us', 'DCIO_LVTMA_BLON_OFF', - 'DCIO_LVTMA_BLON_ON', 'DCIO_LVTMA_BLON_POL_INVERT', - 'DCIO_LVTMA_BLON_POL_NON_INVERT', 'DCIO_LVTMA_DIGON_OFF', - 'DCIO_LVTMA_DIGON_ON', 'DCIO_LVTMA_DIGON_POL_INVERT', - 'DCIO_LVTMA_DIGON_POL_NON_INVERT', - 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', - 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', - 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', - 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', - 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', - 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', - 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', - 'DCIO_LVTMA_SYNCEN_POL_INVERT', - 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', - 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', - 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', - 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', - 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', - 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', - 'DCIO_MVP_PIXEL_SRC_STATUS_LB', 'DCIO_SWAPLOCK_A_GSL_MASK', - 'DCIO_SWAPLOCK_A_GSL_MASK_NO', 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', - 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', - 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SCLK', - 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', - 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', - 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', - 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', - 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', - 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', - 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPA_FBDIV_CLK', - 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPB_FBDIV_CLK', - 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', - 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', - 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', - 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', - 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', - 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', - 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', - 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', - 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', - 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', - 'DCIO_VIP_MUX_EN_VIP', 'DCO_DBG_BLOCK_SEL', - 'DCO_DBG_BLOCK_SEL_ABM', 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', - 'DCO_DBG_BLOCK_SEL_AUX0', 'DCO_DBG_BLOCK_SEL_AUX1', - 'DCO_DBG_BLOCK_SEL_AUX2', 'DCO_DBG_BLOCK_SEL_AUX3', - 'DCO_DBG_BLOCK_SEL_AUX4', 'DCO_DBG_BLOCK_SEL_AUX5', - 'DCO_DBG_BLOCK_SEL_DAC', 'DCO_DBG_BLOCK_SEL_DCO', - 'DCO_DBG_BLOCK_SEL_DIGA', 'DCO_DBG_BLOCK_SEL_DIGB', - 'DCO_DBG_BLOCK_SEL_DIGC', 'DCO_DBG_BLOCK_SEL_DIGD', - 'DCO_DBG_BLOCK_SEL_DIGE', 'DCO_DBG_BLOCK_SEL_DIGF', - 'DCO_DBG_BLOCK_SEL_DIGFE_A', 'DCO_DBG_BLOCK_SEL_DIGFE_B', - 'DCO_DBG_BLOCK_SEL_DIGFE_C', 'DCO_DBG_BLOCK_SEL_DIGFE_D', - 'DCO_DBG_BLOCK_SEL_DIGFE_E', 'DCO_DBG_BLOCK_SEL_DIGFE_F', - 'DCO_DBG_BLOCK_SEL_DIGFE_G', 'DCO_DBG_BLOCK_SEL_DIGG', - 'DCO_DBG_BLOCK_SEL_DIGLPA', 'DCO_DBG_BLOCK_SEL_DIGLPB', - 'DCO_DBG_BLOCK_SEL_DIGLPFEA', 'DCO_DBG_BLOCK_SEL_DIGLPFEB', - 'DCO_DBG_BLOCK_SEL_DPA', 'DCO_DBG_BLOCK_SEL_DPB', - 'DCO_DBG_BLOCK_SEL_DPC', 'DCO_DBG_BLOCK_SEL_DPD', - 'DCO_DBG_BLOCK_SEL_DPE', 'DCO_DBG_BLOCK_SEL_DPF', - 'DCO_DBG_BLOCK_SEL_DPFE_A', 'DCO_DBG_BLOCK_SEL_DPFE_B', - 'DCO_DBG_BLOCK_SEL_DPFE_C', 'DCO_DBG_BLOCK_SEL_DPFE_D', - 'DCO_DBG_BLOCK_SEL_DPFE_E', 'DCO_DBG_BLOCK_SEL_DPFE_F', - 'DCO_DBG_BLOCK_SEL_DPFE_G', 'DCO_DBG_BLOCK_SEL_DPG', - 'DCO_DBG_BLOCK_SEL_DPLPA', 'DCO_DBG_BLOCK_SEL_DPLPB', - 'DCO_DBG_BLOCK_SEL_DPLPFEA', 'DCO_DBG_BLOCK_SEL_DPLPFEB', - 'DCO_DBG_BLOCK_SEL_DVO', 'DCO_DBG_BLOCK_SEL_FMT0', - 'DCO_DBG_BLOCK_SEL_FMT1', 'DCO_DBG_BLOCK_SEL_FMT2', - 'DCO_DBG_BLOCK_SEL_FMT3', 'DCO_DBG_BLOCK_SEL_FMT4', - 'DCO_DBG_BLOCK_SEL_FMT5', 'DCO_DBG_BLOCK_SEL_MVP', - 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', - 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE', - 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', - 'DCP_ALPHA_ROUND_TRUNC_MODE', 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', - 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', 'DCP_CRC_ENABLE', - 'DCP_CRC_ENABLE_FALSE', 'DCP_CRC_ENABLE_TRUE', 'DCP_CRC_LINE_SEL', - 'DCP_CRC_LINE_SEL_BOTH', 'DCP_CRC_LINE_SEL_EVEN', - 'DCP_CRC_LINE_SEL_ODD', 'DCP_CRC_LINE_SEL_RESERVED', - 'DCP_CRC_SOURCE_SEL', 'DCP_CRC_SOURCE_SEL_INPUT_H32', - 'DCP_CRC_SOURCE_SEL_INPUT_L32', 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', - 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', 'DCP_CUR2_INV_TRANS_CLAMP', - 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', - 'DCP_CURSOR_2X_MAGNIFY', 'DCP_CURSOR_2X_MAGNIFY_FALSE', - 'DCP_CURSOR_2X_MAGNIFY_TRUE', 'DCP_CURSOR_ALPHA_BLND_ENA', - 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', - 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', 'DCP_CURSOR_DEGAMMA_MODE', - 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', - 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', - 'DCP_CURSOR_DEGAMMA_MODE_ROMA', 'DCP_CURSOR_DEGAMMA_MODE_ROMB', - 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE', - 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', - 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_CURSOR_EN', - 'DCP_CURSOR_EN_FALSE', 'DCP_CURSOR_EN_TRUE', - 'DCP_CURSOR_FORCE_MC_ON', 'DCP_CURSOR_FORCE_MC_ON_FALSE', - 'DCP_CURSOR_FORCE_MC_ON_TRUE', - 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM', - 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', - 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', 'DCP_CURSOR_MODE', - 'DCP_CURSOR_MODE_24BPP_1BIT', - 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', - 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', - 'DCP_CURSOR_MODE_MONO_2BPP', 'DCP_CURSOR_STEREO_EN', - 'DCP_CURSOR_STEREO_EN_FALSE', 'DCP_CURSOR_STEREO_EN_TRUE', - 'DCP_CURSOR_STEREO_OFFSET_YNX', - 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', - 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', - 'DCP_CURSOR_UPDATE_LOCK', 'DCP_CURSOR_UPDATE_LOCK_FALSE', - 'DCP_CURSOR_UPDATE_LOCK_TRUE', 'DCP_CURSOR_UPDATE_PENDING', - 'DCP_CURSOR_UPDATE_PENDING_FALSE', - 'DCP_CURSOR_UPDATE_PENDING_TRUE', 'DCP_CURSOR_UPDATE_STEREO_MODE', - 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', - 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', - 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', - 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', - 'DCP_CURSOR_UPDATE_TAKEN', 'DCP_CURSOR_UPDATE_TAKEN_FALSE', - 'DCP_CURSOR_UPDATE_TAKEN_TRUE', 'DCP_CURSOR_URGENT_CONTROL', - 'DCP_CURSOR_URGENT_CONTROL_MODE_0', - 'DCP_CURSOR_URGENT_CONTROL_MODE_1', - 'DCP_CURSOR_URGENT_CONTROL_MODE_2', - 'DCP_CURSOR_URGENT_CONTROL_MODE_3', - 'DCP_CURSOR_URGENT_CONTROL_MODE_4', 'DCP_CUR_INV_TRANS_CLAMP', - 'DCP_CUR_INV_TRANS_CLAMP_FALSE', 'DCP_CUR_INV_TRANS_CLAMP_TRUE', - 'DCP_CUR_REQUEST_FILTER_DIS', 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', - 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', 'DCP_DC_LUT_AUTOFILL', - 'DCP_DC_LUT_AUTOFILL_DONE', 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', - 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', 'DCP_DC_LUT_AUTOFILL_FALSE', - 'DCP_DC_LUT_AUTOFILL_TRUE', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN', - 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', - 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', - 'DCP_DC_LUT_DATA_B_FORMAT', 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', - 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', - 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', - 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', 'DCP_DC_LUT_DATA_B_SIGNED_EN', - 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', - 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', - 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN', - 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', - 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', - 'DCP_DC_LUT_DATA_G_FORMAT', 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', - 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', - 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', - 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', 'DCP_DC_LUT_DATA_G_SIGNED_EN', - 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', - 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', - 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN', - 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', - 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', - 'DCP_DC_LUT_DATA_R_FORMAT', 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', - 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', - 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', - 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', 'DCP_DC_LUT_DATA_R_SIGNED_EN', - 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', - 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', 'DCP_DC_LUT_INC_B', - 'DCP_DC_LUT_INC_B_128', 'DCP_DC_LUT_INC_B_16', - 'DCP_DC_LUT_INC_B_2', 'DCP_DC_LUT_INC_B_256', - 'DCP_DC_LUT_INC_B_32', 'DCP_DC_LUT_INC_B_4', - 'DCP_DC_LUT_INC_B_512', 'DCP_DC_LUT_INC_B_64', - 'DCP_DC_LUT_INC_B_8', 'DCP_DC_LUT_INC_B_NA', 'DCP_DC_LUT_INC_G', - 'DCP_DC_LUT_INC_G_128', 'DCP_DC_LUT_INC_G_16', - 'DCP_DC_LUT_INC_G_2', 'DCP_DC_LUT_INC_G_256', - 'DCP_DC_LUT_INC_G_32', 'DCP_DC_LUT_INC_G_4', - 'DCP_DC_LUT_INC_G_512', 'DCP_DC_LUT_INC_G_64', - 'DCP_DC_LUT_INC_G_8', 'DCP_DC_LUT_INC_G_NA', 'DCP_DC_LUT_INC_R', - 'DCP_DC_LUT_INC_R_128', 'DCP_DC_LUT_INC_R_16', - 'DCP_DC_LUT_INC_R_2', 'DCP_DC_LUT_INC_R_256', - 'DCP_DC_LUT_INC_R_32', 'DCP_DC_LUT_INC_R_4', - 'DCP_DC_LUT_INC_R_512', 'DCP_DC_LUT_INC_R_64', - 'DCP_DC_LUT_INC_R_8', 'DCP_DC_LUT_INC_R_NA', 'DCP_DC_LUT_RW_MODE', - 'DCP_DC_LUT_RW_MODE_256_ENTRY', 'DCP_DC_LUT_RW_MODE_PWL', - 'DCP_DC_LUT_VGA_ACCESS_ENABLE', - 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', - 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', 'DCP_DENORM_14BIT_OUT', - 'DCP_DENORM_14BIT_OUT_FALSE', 'DCP_DENORM_14BIT_OUT_TRUE', - 'DCP_DENORM_MODE', 'DCP_DENORM_MODE_10BIT', - 'DCP_DENORM_MODE_11BIT', 'DCP_DENORM_MODE_12BIT', - 'DCP_DENORM_MODE_6BIT', 'DCP_DENORM_MODE_8BIT', - 'DCP_DENORM_MODE_RESERVED0', 'DCP_DENORM_MODE_RESERVED1', - 'DCP_DENORM_MODE_UNITY', 'DCP_FRAME_RANDOM_ENABLE', - 'DCP_FRAME_RANDOM_ENABLE_FALSE', 'DCP_FRAME_RANDOM_ENABLE_TRUE', - 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE', - 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', - 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', - 'DCP_GRPH_ALPHA_CROSSBAR', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', - 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', - 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', - 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', 'DCP_GRPH_BLUE_CROSSBAR', - 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', - 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', - 'DCP_GRPH_COLOR_EXPANSION_MODE', - 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', - 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', 'DCP_GRPH_DEGAMMA_MODE', - 'DCP_GRPH_DEGAMMA_MODE_BYPASS', 'DCP_GRPH_DEGAMMA_MODE_RESERVED', - 'DCP_GRPH_DEGAMMA_MODE_ROMA', 'DCP_GRPH_DEGAMMA_MODE_ROMB', - 'DCP_GRPH_DEPTH', 'DCP_GRPH_DEPTH_16BPP', 'DCP_GRPH_DEPTH_32BPP', - 'DCP_GRPH_DEPTH_64BPP', 'DCP_GRPH_DEPTH_8BPP', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', - 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', 'DCP_GRPH_DFQ_RESET', - 'DCP_GRPH_DFQ_RESET_ACK', 'DCP_GRPH_DFQ_RESET_ACK_FALSE', - 'DCP_GRPH_DFQ_RESET_ACK_TRUE', 'DCP_GRPH_DFQ_RESET_FALSE', - 'DCP_GRPH_DFQ_RESET_TRUE', 'DCP_GRPH_DFQ_SIZE', - 'DCP_GRPH_DFQ_SIZE_DEEP1', 'DCP_GRPH_DFQ_SIZE_DEEP2', - 'DCP_GRPH_DFQ_SIZE_DEEP3', 'DCP_GRPH_DFQ_SIZE_DEEP4', - 'DCP_GRPH_DFQ_SIZE_DEEP5', 'DCP_GRPH_DFQ_SIZE_DEEP6', - 'DCP_GRPH_DFQ_SIZE_DEEP7', 'DCP_GRPH_DFQ_SIZE_DEEP8', - 'DCP_GRPH_ENABLE', 'DCP_GRPH_ENABLE_FALSE', - 'DCP_GRPH_ENABLE_TRUE', 'DCP_GRPH_ENDIAN_SWAP', - 'DCP_GRPH_ENDIAN_SWAP_8IN16', 'DCP_GRPH_ENDIAN_SWAP_8IN32', - 'DCP_GRPH_ENDIAN_SWAP_8IN64', 'DCP_GRPH_ENDIAN_SWAP_NONE', - 'DCP_GRPH_FLIP_RATE', 'DCP_GRPH_FLIP_RATE_1FRAME', - 'DCP_GRPH_FLIP_RATE_2FRAME', 'DCP_GRPH_FLIP_RATE_3FRAME', - 'DCP_GRPH_FLIP_RATE_4FRAME', 'DCP_GRPH_FLIP_RATE_5FRAME', - 'DCP_GRPH_FLIP_RATE_6FRAME', 'DCP_GRPH_FLIP_RATE_7FRAME', - 'DCP_GRPH_FLIP_RATE_8FRAME', 'DCP_GRPH_FLIP_RATE_ENABLE', - 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', - 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', 'DCP_GRPH_FORMAT', - 'DCP_GRPH_FORMAT_16BPP', 'DCP_GRPH_FORMAT_32BPP', - 'DCP_GRPH_FORMAT_64BPP', 'DCP_GRPH_FORMAT_8BPP', - 'DCP_GRPH_GAMUT_REMAP_MODE', 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', - 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', - 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', - 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', 'DCP_GRPH_GREEN_CROSSBAR', - 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', - 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', - 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', - 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', 'DCP_GRPH_INPUT_GAMMA_MODE', - 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', - 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', 'DCP_GRPH_KEYER_ALPHA_SEL', - 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', - 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN', - 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', - 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', - 'DCP_GRPH_LUT_10BIT_BYPASS_EN', - 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', - 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', - 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', - 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', - 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', - 'DCP_GRPH_MODE_UPDATE_PENDING', - 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', - 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', 'DCP_GRPH_MODE_UPDATE_TAKEN', - 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', - 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', 'DCP_GRPH_NUM_BANKS', - 'DCP_GRPH_NUM_BANKS_16BANK', 'DCP_GRPH_NUM_BANKS_1BANK', - 'DCP_GRPH_NUM_BANKS_2BANK', 'DCP_GRPH_NUM_BANKS_4BANK', - 'DCP_GRPH_NUM_BANKS_8BANK', 'DCP_GRPH_NUM_PIPES', - 'DCP_GRPH_NUM_PIPES_1PIPE', 'DCP_GRPH_NUM_PIPES_2PIPE', - 'DCP_GRPH_NUM_PIPES_4PIPE', 'DCP_GRPH_NUM_PIPES_8PIPE', - 'DCP_GRPH_PFLIP_INT_CLEAR', 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', - 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', 'DCP_GRPH_PFLIP_INT_MASK', - 'DCP_GRPH_PFLIP_INT_MASK_FALSE', 'DCP_GRPH_PFLIP_INT_MASK_TRUE', - 'DCP_GRPH_PFLIP_INT_TYPE', 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', - 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', 'DCP_GRPH_PRESCALE_BYPASS', - 'DCP_GRPH_PRESCALE_BYPASS_FALSE', 'DCP_GRPH_PRESCALE_BYPASS_TRUE', - 'DCP_GRPH_PRESCALE_B_SIGN', 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', - 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_G_SIGN', - 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', - 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_R_SIGN', - 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', - 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_SELECT', - 'DCP_GRPH_PRESCALE_SELECT_FIXED', - 'DCP_GRPH_PRESCALE_SELECT_FLOATING', - 'DCP_GRPH_PRIMARY_DFQ_ENABLE', - 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', - 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', 'DCP_GRPH_RED_CROSSBAR', - 'DCP_GRPH_RED_CROSSBAR_FROM_A', 'DCP_GRPH_RED_CROSSBAR_FROM_B', - 'DCP_GRPH_RED_CROSSBAR_FROM_G', 'DCP_GRPH_RED_CROSSBAR_FROM_R', - 'DCP_GRPH_REGAMMA_MODE', 'DCP_GRPH_REGAMMA_MODE_BYPASS', - 'DCP_GRPH_REGAMMA_MODE_PROGA', 'DCP_GRPH_REGAMMA_MODE_PROGB', - 'DCP_GRPH_REGAMMA_MODE_SRGB', 'DCP_GRPH_REGAMMA_MODE_XVYCC', - 'DCP_GRPH_ROTATION_ANGLE', 'DCP_GRPH_ROTATION_ANGLE_0', - 'DCP_GRPH_ROTATION_ANGLE_180', 'DCP_GRPH_ROTATION_ANGLE_270', - 'DCP_GRPH_ROTATION_ANGLE_90', 'DCP_GRPH_SECONDARY_DFQ_ENABLE', - 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', - 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', - 'DCP_GRPH_STEREOSYNC_FLIP_EN', - 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', - 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', - 'DCP_GRPH_STEREOSYNC_FLIP_MODE', - 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', - 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', - 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', - 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', - 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE', - 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', - 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', - 'DCP_GRPH_SURFACE_COUNTER_EN', - 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', - 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', - 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED', - 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', - 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', - 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', - 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', - 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', - 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', - 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', - 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', - 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', - 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN', - 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', - 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', - 'DCP_GRPH_SURFACE_UPDATE_PENDING', - 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', - 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', - 'DCP_GRPH_SURFACE_UPDATE_TAKEN', - 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', - 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', - 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE', - 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', - 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', 'DCP_GRPH_SW_MODE', - 'DCP_GRPH_SW_MODE_0', 'DCP_GRPH_SW_MODE_2', 'DCP_GRPH_SW_MODE_22', - 'DCP_GRPH_SW_MODE_23', 'DCP_GRPH_SW_MODE_26', - 'DCP_GRPH_SW_MODE_27', 'DCP_GRPH_SW_MODE_3', - 'DCP_GRPH_SW_MODE_30', 'DCP_GRPH_SW_MODE_31', - 'DCP_GRPH_UPDATE_LOCK', 'DCP_GRPH_UPDATE_LOCK_FALSE', - 'DCP_GRPH_UPDATE_LOCK_TRUE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', - 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', - 'DCP_GRPH_XDMA_DRR_MODE_ENABLE', - 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', - 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', - 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', - 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR', - 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', - 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', - 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE', - 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', - 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', - 'DCP_GRPH_XDMA_SUPER_AA_EN', 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', - 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', 'DCP_GSL0_EN', - 'DCP_GSL0_EN_FALSE', 'DCP_GSL0_EN_TRUE', 'DCP_GSL1_EN', - 'DCP_GSL1_EN_FALSE', 'DCP_GSL1_EN_TRUE', 'DCP_GSL2_EN', - 'DCP_GSL2_EN_FALSE', 'DCP_GSL2_EN_TRUE', - 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING', - 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', - 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', 'DCP_GSL_MASTER_EN', - 'DCP_GSL_MASTER_EN_FALSE', 'DCP_GSL_MASTER_EN_TRUE', - 'DCP_GSL_SYNC_SOURCE', 'DCP_GSL_SYNC_SOURCE_FLIP', - 'DCP_GSL_SYNC_SOURCE_PHASE0', 'DCP_GSL_SYNC_SOURCE_PHASE1', - 'DCP_GSL_SYNC_SOURCE_RESET', - 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC', - 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', - 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', 'DCP_GSL_XDMA_GROUP', - 'DCP_GSL_XDMA_GROUP_HSYNC0', 'DCP_GSL_XDMA_GROUP_HSYNC1', - 'DCP_GSL_XDMA_GROUP_HSYNC2', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN', - 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', - 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', - 'DCP_GSL_XDMA_GROUP_VSYNC', 'DCP_HIGHPASS_RANDOM_ENABLE', - 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', - 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', 'DCP_INPUT_CSC_GRPH_MODE', - 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', - 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', - 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', - 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', 'DCP_KEY_MODE', - 'DCP_KEY_MODE_ALPHA0', 'DCP_KEY_MODE_ALPHA1', - 'DCP_KEY_MODE_IN_RANGE_ALPHA0', 'DCP_KEY_MODE_IN_RANGE_ALPHA1', - 'DCP_OUTPUT_CSC_GRPH_MODE', 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', - 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', - 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', - 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', - 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', - 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', - 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', - 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', 'DCP_OUT_ROUND_TRUNC_MODE', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', - 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', - 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', - 'DCP_RGB_RANDOM_ENABLE', 'DCP_RGB_RANDOM_ENABLE_FALSE', - 'DCP_RGB_RANDOM_ENABLE_TRUE', 'DCP_SPATIAL_DITHER_DEPTH', - 'DCP_SPATIAL_DITHER_DEPTH_24BPP', - 'DCP_SPATIAL_DITHER_DEPTH_30BPP', - 'DCP_SPATIAL_DITHER_DEPTH_36BPP', - 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', 'DCP_SPATIAL_DITHER_EN', - 'DCP_SPATIAL_DITHER_EN_FALSE', 'DCP_SPATIAL_DITHER_EN_TRUE', - 'DCP_SPATIAL_DITHER_MODE', 'DCP_SPATIAL_DITHER_MODE_BYPASS', - 'DCP_SPATIAL_DITHER_MODE_RESERVED', - 'DCP_SPATIAL_DITHER_MODE_ROMA', 'DCP_SPATIAL_DITHER_MODE_ROMB', - 'DCP_TEST_DEBUG_WRITE_EN', 'DCP_TEST_DEBUG_WRITE_EN_FALSE', - 'DCP_TEST_DEBUG_WRITE_EN_TRUE', 'DC_MEM_GLOBAL_PWR_REQ_DIS', - 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 'DEGAMMA_MODE_A', 'DEGAMMA_MODE_B', 'DEGAMMA_MODE_BYPASS', - 'DENORM_CLAMP_MODE_10', 'DENORM_CLAMP_MODE_12', - 'DENORM_CLAMP_MODE_8', 'DENORM_CLAMP_MODE_UNITY', 'DEPTH_16', - 'DEPTH_32_FLOAT', 'DEPTH_8_24', 'DEPTH_8_24_FLOAT', - 'DEPTH_INVALID', 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', - 'DEPTH_X8_24_FLOAT', 'DFSMFlushEvents', 'DIGA_BE_SOFT_RESET', - 'DIGA_BE_SOFT_RESET_0', 'DIGA_BE_SOFT_RESET_1', - 'DIGA_FE_SOFT_RESET', 'DIGA_FE_SOFT_RESET_0', - 'DIGA_FE_SOFT_RESET_1', 'DIGB_BE_SOFT_RESET', - 'DIGB_BE_SOFT_RESET_0', 'DIGB_BE_SOFT_RESET_1', - 'DIGB_FE_SOFT_RESET', 'DIGB_FE_SOFT_RESET_0', - 'DIGB_FE_SOFT_RESET_1', 'DIGC_BE_SOFT_RESET', - 'DIGC_BE_SOFT_RESET_0', 'DIGC_BE_SOFT_RESET_1', - 'DIGC_FE_SOFT_RESET', 'DIGC_FE_SOFT_RESET_0', - 'DIGC_FE_SOFT_RESET_1', 'DIGD_BE_SOFT_RESET', - 'DIGD_BE_SOFT_RESET_0', 'DIGD_BE_SOFT_RESET_1', - 'DIGD_FE_SOFT_RESET', 'DIGD_FE_SOFT_RESET_0', - 'DIGD_FE_SOFT_RESET_1', 'DIGE_BE_SOFT_RESET', - 'DIGE_BE_SOFT_RESET_0', 'DIGE_BE_SOFT_RESET_1', - 'DIGE_FE_SOFT_RESET', 'DIGE_FE_SOFT_RESET_0', - 'DIGE_FE_SOFT_RESET_1', 'DIGF_BE_SOFT_RESET', - 'DIGF_BE_SOFT_RESET_0', 'DIGF_BE_SOFT_RESET_1', - 'DIGF_FE_SOFT_RESET', 'DIGF_FE_SOFT_RESET_0', - 'DIGF_FE_SOFT_RESET_1', 'DIGG_BE_SOFT_RESET', - 'DIGG_BE_SOFT_RESET_0', 'DIGG_BE_SOFT_RESET_1', - 'DIGG_FE_SOFT_RESET', 'DIGG_FE_SOFT_RESET_0', - 'DIGG_FE_SOFT_RESET_1', 'DIGLPA_BE_SOFT_RESET', - 'DIGLPA_BE_SOFT_RESET_0', 'DIGLPA_BE_SOFT_RESET_1', - 'DIGLPA_FE_SOFT_RESET', 'DIGLPA_FE_SOFT_RESET_0', - 'DIGLPA_FE_SOFT_RESET_1', 'DIGLPB_BE_SOFT_RESET', - 'DIGLPB_BE_SOFT_RESET_0', 'DIGLPB_BE_SOFT_RESET_1', - 'DIGLPB_FE_SOFT_RESET', 'DIGLPB_FE_SOFT_RESET_0', - 'DIGLPB_FE_SOFT_RESET_1', 'DIG_10BIT_TEST_PATTERN', - 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', - 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', - 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', - 'DIG_BE_CNTL_MODE', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', - 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', - 'DIG_BE_SDVO_RESERVED', 'DIG_BE_TMDS_DVI_MODE', - 'DIG_BE_TMDS_HDMI_MODE', 'DIG_FE_CNTL_SOURCE_SELECT', - 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_FMT0', - 'DIG_FE_SOURCE_FROM_FMT1', 'DIG_FE_SOURCE_FROM_FMT2', - 'DIG_FE_SOURCE_FROM_FMT3', 'DIG_FE_SOURCE_FROM_FMT4', - 'DIG_FE_SOURCE_FROM_FMT5', 'DIG_FE_STEREOSYNC_FROM_FMT0', - 'DIG_FE_STEREOSYNC_FROM_FMT1', 'DIG_FE_STEREOSYNC_FROM_FMT2', - 'DIG_FE_STEREOSYNC_FROM_FMT3', 'DIG_FE_STEREOSYNC_FROM_FMT4', - 'DIG_FE_STEREOSYNC_FROM_FMT5', 'DIG_FIFO_ERROR_ACK', - 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', - 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', - 'DIG_FIFO_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', - 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', - 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', - 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', - 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', - 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', - 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', - 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', - 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', - 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', - 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', - 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', - 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', - 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', - 'DISPCLK_CHG_FWD_CORR_DISABLE', - 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', - 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', - 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DITHER_DIS', 'DITHER_EN', - 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', - 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', - 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', - 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', - 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', - 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', - 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', - 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DI_SRC_SEL_RESERVED', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', - 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', - 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_ABORT_XFER', - 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', - 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', - 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', - 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', - 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', - 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', - 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', - 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', - 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', - 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', - 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET', 'DOUT_I2C_DATA_INDEX_WRITE', - 'DOUT_I2C_DATA__INDEX_WRITE', 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', - 'DOUT_I2C_DDC_SPEED_THRESHOLD', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', - 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', - 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', - 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DOWNSCALE_PREFETCH_DIS', - 'DOWNSCALE_PREFETCH_EN', 'DPCSRX_BPHY_PCS_RX0_CLK', - 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', - 'DPCSRX_BPHY_PCS_RX3_CLK', 'DPCSRX_DBG_CFGCLK_SEL', - 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', - 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', - 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', - 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', - 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', - 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', - 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSRX_RX_SYMCLK_SEL', - 'DPCSTX_DBG_CFGCLK_SEL', 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', - 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', - 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', - 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', - 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', - 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', - 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', - 'DPCSTX_TX_SYMCLK_DIV2_SEL', 'DPCSTX_TX_SYMCLK_SEL', - 'DPDBG_CLK_FORCE_EN', 'DPDBG_CLK_FORCE_EN_DISABLE', - 'DPDBG_CLK_FORCE_EN_ENABLE', 'DPDBG_DISABLE', 'DPDBG_EN', - 'DPDBG_ENABLE', 'DPDBG_ERROR_DETECTION_MODE', - 'DPDBG_ERROR_DETECTION_MODE_CSC', - 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', - 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK', - 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK', - 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE', - 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', - 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', - 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', - 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', - 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', - 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', 'DPDBG_INPUT_DISABLE', - 'DPDBG_INPUT_EN', 'DPDBG_INPUT_ENABLE', 'DPDBG_SOFT_RESET', - 'DPDBG_SOFT_RESET_0', 'DPDBG_SOFT_RESET_1', 'DPHY_8B10B_CUR_DISP', - 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', - 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', - 'DPHY_8B10B_RESETET', - 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', - 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', - 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', - 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', - 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', - 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', - 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', - 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', - 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', - 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', - 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', - 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', - 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', - 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', - 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', - 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', - 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', - 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', - 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', - 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', - 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', - 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', - 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', - 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', - 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', - 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', - 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', - 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', - 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', - 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', - 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', - 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', - 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', - 'DPREFCLK_SRC_SEL_P3PLL', 'DPRX_SD_COMPONENT_DEPTH', - 'DPRX_SD_PIXEL_ENCODING', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', - 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', - 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', - 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', - 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_TEST_MODE', - 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 'DP_AUX_CONTROL_TEST_MODE_ENABLE', - 'DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', - 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', - 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', - 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', - 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', - 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', - 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', - 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', - 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', - 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 'DP_AUX_SW_CONTROL_LS_READ_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', - 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 'DP_COMPONENT_DEPTH', 'DP_COMPONENT_DEPTH_10BPC', - 'DP_COMPONENT_DEPTH_12BPC', 'DP_COMPONENT_DEPTH_16BPC_RESERVED', - 'DP_COMPONENT_DEPTH_6BPC', 'DP_COMPONENT_DEPTH_8BPC', - 'DP_COMPONENT_DEPTH_RESERVED', 'DP_DPHY_8B10B_EXT_DISP', - 'DP_DPHY_8B10B_EXT_DISP_ONE', 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', - 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', - 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', - 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', - 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', - 'DP_DTO_DS_DISABLE', 'DP_DYN_CEA_RANGE', 'DP_DYN_RANGE', - 'DP_DYN_VESA_RANGE', 'DP_EMBEDDED_PANEL', - 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', - 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', - 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_MSA_MISC0_OVERRIDE_ENABLE', - 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE', - 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', - 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', - 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', - 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', - 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', - 'DP_MSE_OUTPUT_DPDBG_DATA', 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', - 'DP_MSE_OUTPUT_DPDBG_DATA_EN', 'DP_MSE_SAT_UPDATE_ACT', - 'DP_MSE_SAT_UPDATE_NO_ACTION', - 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', - 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', - 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', - 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_RESERVED', - 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', - 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', - 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', - 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', - 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', - 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', - 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', - 'DP_SEC_GSP0_SEND', 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', - 'DP_SEC_TIMESTAMP_MODE', 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 'DP_STEER_OVERFLOW_ACK', 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', - 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', - 'DP_TOP_FIELD_ONLY', 'DP_TOP_PLUS_BOTTOM_FIELD', - 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', - 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', - 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_MSA_TOP_FIELD_MODE', - 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', 'DP_VID_M_DOUBLE_VALUE_EN', - 'DP_VID_M_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', - 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', - 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', - 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_STREAM_DISABLE_ACK', - 'DP_VID_STREAM_DISABLE_MASK', 'DP_VID_STREAM_DIS_DEFER', - 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', - 'DP_VID_TIMING_MODE', 'DP_VID_TIMING_MODE_ASYNC', - 'DP_VID_TIMING_MODE_SYNC', 'DP_VID_VBID_FIELD_POL', - 'DP_VID_VBID_FIELD_POL_INV', 'DP_VID_VBID_FIELD_POL_NORMAL', - 'DP_YCBCR_RANGE', 'DP_YCBCR_RANGE_BT601_5', - 'DP_YCBCR_RANGE_BT709_5', 'DSI_BIT_SWAP', 'DSI_BIT_SWAP_DISABLE', - 'DSI_BIT_SWAP_ENABLE', 'DSI_CLK_GATING', 'DSI_CLK_GATING_DISABLE', - 'DSI_CLK_GATING_ENABLE', 'DSI_CLOCK_LANE_DISABLE', - 'DSI_CLOCK_LANE_EN', 'DSI_CLOCK_LANE_ENABLE', - 'DSI_CLOCK_LANE_HS_FORCE_REQUEST', - 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', - 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', - 'DSI_CMD_EMBEDDED_MODE', 'DSI_CMD_MODE_DISABLE', - 'DSI_CMD_MODE_EN', 'DSI_CMD_MODE_ENABLE', 'DSI_CMD_ORDER', - 'DSI_CMD_ORDER_COMMAND_FIRST', 'DSI_CMD_ORDER_DATA_FIRST', - 'DSI_CMD_PACKET_TYPE', 'DSI_CMD_PACKET_TYPE_LONG', - 'DSI_CMD_PACKET_TYPE_SHORT', 'DSI_CMD_PWR_MODE', - 'DSI_CMD_PWR_MODE_HS', 'DSI_CMD_PWR_MODE_LP', - 'DSI_CMD_USE_CMDFIFO', 'DSI_CMD_USE_DMAFIFO', - 'DSI_COMMAND_DST_FORMAT_RGB111', 'DSI_COMMAND_DST_FORMAT_RGB332', - 'DSI_COMMAND_DST_FORMAT_RGB444', 'DSI_COMMAND_DST_FORMAT_RGB565', - 'DSI_COMMAND_DST_FORMAT_RGB666', 'DSI_COMMAND_DST_FORMAT_RGB888', - 'DSI_COMMAND_MODE_DST_FORMAT', 'DSI_COMMAND_MODE_SRC_FORMAT', - 'DSI_COMMAND_SRC_FORMAT_RGB332', 'DSI_COMMAND_SRC_FORMAT_RGB444', - 'DSI_COMMAND_SRC_FORMAT_RGB555', 'DSI_COMMAND_SRC_FORMAT_RGB565', - 'DSI_COMMAND_SRC_FORMAT_RGB888', 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', - 'DSI_COMMAND_TRIGGER_MODE', 'DSI_COMMAND_TRIGGER_MODE_AUTO', - 'DSI_COMMAND_TRIGGER_MODE_MANUAL', 'DSI_COMMAND_TRIGGER_ORDER', - 'DSI_COMMAND_TRIGGER_ORDER_DENG', 'DSI_COMMAND_TRIGGER_ORDER_DMA', - 'DSI_COMMAND_TRIGGER_SEL', 'DSI_COMMAND_TRIGGER_SEL_CRTC', - 'DSI_COMMAND_TRIGGER_SEL_HW', 'DSI_COMMAND_TRIGGER_SEL_NONE', - 'DSI_COMMAND_TRIGGER_SEL_TE', 'DSI_CONTROLLER_DISABLE', - 'DSI_CONTROLLER_EN', 'DSI_CONTROLLER_ENABLE', - 'DSI_CRC_CAL_DISABLE', 'DSI_CRC_CAL_ENABLE', 'DSI_CRC_ENABLE', - 'DSI_CRTC_FREEZE_TRIG', 'DSI_CRTC_FREEZE_TRIG_ASSERT', - 'DSI_CRTC_FREEZE_TRIG_DEASSERT', 'DSI_CRTC_SEL', - 'DSI_DATA_BUFFER_ID', 'DSI_DATA_BUFFER_OFFSET0', - 'DSI_DATA_BUFFER_OFFSET1', 'DSI_DATA_LANE0_DISABLE', - 'DSI_DATA_LANE0_EN', 'DSI_DATA_LANE0_ENABLE', - 'DSI_DATA_LANE1_DISABLE', 'DSI_DATA_LANE1_EN', - 'DSI_DATA_LANE1_ENABLE', 'DSI_DATA_LANE2_DISABLE', - 'DSI_DATA_LANE2_EN', 'DSI_DATA_LANE2_ENABLE', - 'DSI_DATA_LANE3_DISABLE', 'DSI_DATA_LANE3_EN', - 'DSI_DATA_LANE3_ENABLE', 'DSI_DBG_CLK_SEL', - 'DSI_DEBUG_BYTECLK_SEL', 'DSI_DEBUG_BYTECLK_SEL_AFIFO', - 'DSI_DEBUG_BYTECLK_SEL_EOT', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', - 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', - 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', - 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', - 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', - 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', - 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', - 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', - 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', - 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', - 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', - 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', - 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', 'DSI_DEBUG_DSICLK_SEL', - 'DSI_DEBUG_DSICLK_SEL_AFIFO', 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', - 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', - 'DSI_DEBUG_DSICLK_SEL_LANECTRL', - 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', - 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', - 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE', - 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', - 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', - 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX', - 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', - 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', - 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', - 'DSI_DENG_FIFO_LEVEL_OVERWRITE', 'DSI_DENG_FIFO_START', - 'DSI_DENG_FIFO_START_ASSERT', 'DSI_DENG_FIFO_START_DEASSERT', - 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL', 'DSI_DMAFIFO_READ_WATERMARK', - 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', - 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', - 'DSI_DMAFIFO_READ_WATERMARK_HALF', - 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', - 'DSI_DMAFIFO_WRITE_WATERMARK', - 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', - 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', - 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', - 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', 'DSI_DWORD_BYTE_SWAP', - 'DSI_EXT_RESET_POL', 'DSI_EXT_RESET_POL_HIGH', - 'DSI_EXT_RESET_POL_LOW', 'DSI_EXT_TE_MODE', - 'DSI_EXT_TE_MODE_HVSYNC_EDGE', 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', - 'DSI_EXT_TE_MODE_VSYNC_EDGE', 'DSI_EXT_TE_MODE_VSYNC_WIDTH', - 'DSI_EXT_TE_MUX', 'DSI_EXT_TE_POL', 'DSI_EXT_TE_POL_FALLING', - 'DSI_EXT_TE_POL_RISING', 'DSI_FLAG_CLEAR', 'DSI_FLAG_CLR', - 'DSI_FLAG_NO_CLEAR', 'DSI_GET_PIXEL_STREAM_FROM_FMT0', - 'DSI_GET_PIXEL_STREAM_FROM_FMT1', - 'DSI_GET_PIXEL_STREAM_FROM_FMT2', - 'DSI_GET_PIXEL_STREAM_FROM_FMT3', - 'DSI_GET_PIXEL_STREAM_FROM_FMT4', - 'DSI_GET_PIXEL_STREAM_FROM_FMT5', 'DSI_HW_SOURCE_SEL', - 'DSI_INSERT_DCS_COMMAND', 'DSI_INSERT_DCS_COMMAND_DISABLE', - 'DSI_INSERT_DCS_COMMAND_ENABLE', 'DSI_LANE_FORCE_TX_STOP', - 'DSI_LANE_FORCE_TX_STOP_ASSERT', - 'DSI_LANE_FORCE_TX_STOP_DEASSERT', 'DSI_LANE_ULPS_EXIT', - 'DSI_LANE_ULPS_EXIT_ASSERT', 'DSI_LANE_ULPS_EXIT_DEASSERT', - 'DSI_LANE_ULPS_REQUEST', 'DSI_LANE_ULPS_REQUEST_ASSERT', - 'DSI_LANE_ULPS_REQUEST_DEASSERT', 'DSI_MIPI_BIST_RESET', - 'DSI_MIPI_BIST_RESET_ASSERT', 'DSI_MIPI_BIST_RESET_DEASSERT', - 'DSI_MIPI_BIST_START', 'DSI_MIPI_BIST_START_ASSERT', - 'DSI_MIPI_BIST_START_DEASSERT', 'DSI_MIPI_BIST_VIDEO_FRMT', - 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', - 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', - 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', - 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', - 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', - 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', - 'DSI_PACKET_BYTE_MSB_LSB_FLIP', - 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', - 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', 'DSI_PERF_LATENCY_SEL', - 'DSI_PERF_LATENCY_SEL_DATA_LANE0', - 'DSI_PERF_LATENCY_SEL_DATA_LANE1', - 'DSI_PERF_LATENCY_SEL_DATA_LANE2', - 'DSI_PERF_LATENCY_SEL_DATA_LANE3', 'DSI_PHY_DATA_LANE0_DISABLE', - 'DSI_PHY_DATA_LANE0_EN', 'DSI_PHY_DATA_LANE0_ENABLE', - 'DSI_PHY_DATA_LANE1_DISABLE', 'DSI_PHY_DATA_LANE1_EN', - 'DSI_PHY_DATA_LANE1_ENABLE', 'DSI_PHY_DATA_LANE2_DISABLE', - 'DSI_PHY_DATA_LANE2_EN', 'DSI_PHY_DATA_LANE2_ENABLE', - 'DSI_PHY_DATA_LANE3_DISABLE', 'DSI_PHY_DATA_LANE3_EN', - 'DSI_PHY_DATA_LANE3_ENABLE', 'DSI_RESET_BYTECLK', - 'DSI_RESET_DISPCLK', 'DSI_RESET_DSICLK', 'DSI_RESET_ESCCLK', - 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', - 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', - 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', - 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', 'DSI_RESET_PANEL', - 'DSI_RESET_PANEL_ASSERT', 'DSI_RESET_PANEL_DEASSERT', - 'DSI_RGB_SWAP', 'DSI_RX_EOT_IGNORE', 'DSI_RX_EOT_IGNORE_DISABLE', - 'DSI_RX_EOT_IGNORE_ENABLE', 'DSI_SWAP_BGR', 'DSI_SWAP_BRG', - 'DSI_SWAP_GBR', 'DSI_SWAP_GRB', 'DSI_SWAP_RBG', 'DSI_SWAP_RGB', - 'DSI_TEST_CLK_SEL_BYTECLK_G', 'DSI_TEST_CLK_SEL_DISPCLK_G', - 'DSI_TEST_CLK_SEL_DISPCLK_P', 'DSI_TEST_CLK_SEL_DISPCLK_R', - 'DSI_TEST_CLK_SEL_DSICLK_G', 'DSI_TEST_CLK_SEL_DSICLK_P', - 'DSI_TEST_CLK_SEL_DSICLK_R', 'DSI_TEST_CLK_SEL_DSICLK_TRN', - 'DSI_TEST_CLK_SEL_ESCCLK_G', 'DSI_TE_SEL_LINK', 'DSI_TE_SEL_PIN', - 'DSI_TE_SRC_SEL', 'DSI_TRAFFIC_MODE_BURST', - 'DSI_TRAFFIC_MODE_RESERVED', 'DSI_TRAFFIC_MODE_SYNC_EVENTS', - 'DSI_TRAFFIC_MODE_SYNC_PULSES', 'DSI_TX_EOT_APPEND', - 'DSI_TX_EOT_APPEND_DISABLE', 'DSI_TX_EOT_APPEND_ENABLE', - 'DSI_USE_CMDFIFO', 'DSI_USE_DENG_LENGTH', - 'DSI_USE_DENG_LENGTH_DISABLE', 'DSI_USE_DENG_LENGTH_ENABLE', - 'DSI_VIDEO_BLLP_PWR_MODE', 'DSI_VIDEO_BLLP_PWR_MODE_HS', - 'DSI_VIDEO_BLLP_PWR_MODE_LP', 'DSI_VIDEO_DST_FORMAT_RGB565', - 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', - 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', - 'DSI_VIDEO_DST_FORMAT_RGB888', 'DSI_VIDEO_EOF_BLLP_PWR_MODE', - 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', - 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', 'DSI_VIDEO_MODE_DISABLE', - 'DSI_VIDEO_MODE_DST_FORMAT', 'DSI_VIDEO_MODE_EN', - 'DSI_VIDEO_MODE_ENABLE', 'DSI_VIDEO_PULSE_MODE_OPT', - 'DSI_VIDEO_PWR_MODE', 'DSI_VIDEO_PWR_MODE_HS', - 'DSI_VIDEO_PWR_MODE_LP', 'DSI_VIDEO_TRAFFIC_MODE', - 'DSI_XT_TE_MUX_DCLK', 'DSI_XT_TE_MUX_DINV', 'DSI_XT_TE_MUX_FRAME', - 'DSI_XT_TE_MUX_GCLK', 'DSI_XT_TE_MUX_GOE', 'DSI_XT_TE_MUX_GPIO4', - 'DSI_XT_TE_MUX_GPIO5', 'DSI_XT_TE_MUX_LCDD17', 'DSI_XT_TE_MUX_SS', - 'DSM_ENABLE_ERROR_INJECT', 'DSM_ENABLE_ERROR_INJECT_DOUBLE', - 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', - 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 'DSM_ENABLE_ERROR_INJECT_SINGLE', 'DSM_SELECT_INJECT_DELAY', - 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', - 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DS_REF_IS_EXT_GENLOCK', - 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', 'DS_REF_SRC', - 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', - 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', - 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', - 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', - 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', - 'DVO_SOFT_RESET', 'DVO_SOFT_RESET_0', 'DVO_SOFT_RESET_1', - 'DWORD_BYTE_SWAP_BOTH_SWAP', 'DWORD_BYTE_SWAP_BYTE_SWAP', - 'DWORD_BYTE_SWAP_NO_SWAP', 'DWORD_BYTE_SWAP_WORD_SWAP', - 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', - 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DYNAMIC_PIXEL_DEPTH_30BPP', 'DYNAMIC_PIXEL_DEPTH_36BPP', - 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', - 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', - 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', 'ENABLE', - 'ENABLE_CLOCK', 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', - 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', - 'ENABLE_THE_FEATURE', 'ENDIAN_8IN16', 'ENDIAN_8IN32', - 'ENDIAN_8IN64', 'ENDIAN_NONE', 'END_OF_PIPE_IB_END', - 'END_OF_PIPE_INCR_DE', 'ENUMS_GDS_PERFCOUNT_SELECT_H', - 'ENUM_NUM_SIMD_PER_CU', 'ENUM_SQ_EXPORT_RAT_INST', - 'ENUM_XDMA_LOCAL_SW_MODE', 'ENUM_XDMA_MSTR_ALPHA_POSITION', - 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL', - 'ENUM_XDMA_SLV_ALPHA_POSITION', 'ES_STAGE_DS', 'ES_STAGE_OFF', - 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', - 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', - 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', - 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', - 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', - 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', - 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', - 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', - 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', - 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', - 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', - 'FBC_IDLE_MASK_DISP_REG_UPDATE', - 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', - 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', - 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', - 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', - 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', - 'FBC_IDLE_MASK_MASK_BITS', 'FBC_IDLE_MASK_MC_HIT_REGION_0', - 'FBC_IDLE_MASK_MC_HIT_REGION_1', 'FBC_IDLE_MASK_MC_HIT_REGION_2', - 'FBC_IDLE_MASK_MC_HIT_REGION_3', 'FBC_IDLE_MASK_MC_WRITE', - 'FBC_IDLE_MASK_RESERVED1', 'FBC_IDLE_MASK_RESERVED10', - 'FBC_IDLE_MASK_RESERVED11', 'FBC_IDLE_MASK_RESERVED12', - 'FBC_IDLE_MASK_RESERVED13', 'FBC_IDLE_MASK_RESERVED14', - 'FBC_IDLE_MASK_RESERVED15', 'FBC_IDLE_MASK_RESERVED16', - 'FBC_IDLE_MASK_RESERVED17', 'FBC_IDLE_MASK_RESERVED18', - 'FBC_IDLE_MASK_RESERVED19', 'FBC_IDLE_MASK_RESERVED20', - 'FBC_IDLE_MASK_RESERVED21', 'FBC_IDLE_MASK_RESERVED22', - 'FBC_IDLE_MASK_RESERVED23', 'FBC_IDLE_MASK_RESERVED29', - 'FBC_IDLE_MASK_RESERVED30', 'FBC_IDLE_MASK_RESERVED31', - 'FBC_IDLE_MASK_RESERVED7', 'FBC_IDLE_MASK_RESERVED8', - 'FBC_IDLE_MASK_RESERVED9', 'FLUSH_AND_INV_CB_DATA_TS', - 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', - 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', - 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', - 'FLUSH_DFSM', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMT0_SOFT_RESET', - 'FMT0_SOFT_RESET_0', 'FMT0_SOFT_RESET_1', 'FMT1_SOFT_RESET', - 'FMT1_SOFT_RESET_0', 'FMT1_SOFT_RESET_1', 'FMT2_SOFT_RESET', - 'FMT2_SOFT_RESET_0', 'FMT2_SOFT_RESET_1', 'FMT3_SOFT_RESET', - 'FMT3_SOFT_RESET_0', 'FMT3_SOFT_RESET_1', - 'FMT420_MEMORY_SOURCE_SEL', 'FMT420_MEMORY_SOURCE_SEL_FMT0', - 'FMT420_MEMORY_SOURCE_SEL_FMT1', 'FMT420_MEMORY_SOURCE_SEL_FMT2', - 'FMT420_MEMORY_SOURCE_SEL_FMT3', 'FMT420_MEMORY_SOURCE_SEL_FMT4', - 'FMT420_MEMORY_SOURCE_SEL_FMT5', - 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', 'FMT4_SOFT_RESET', - 'FMT4_SOFT_RESET_0', 'FMT4_SOFT_RESET_1', 'FMT5_SOFT_RESET', - 'FMT5_SOFT_RESET_0', 'FMT5_SOFT_RESET_1', 'FMT_1', - 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', - 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', - 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', - 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', - 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', - 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', - 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', - 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', - 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', - 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', - 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', - 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', - 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', - 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', - 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 'FMT_CLAMP_CNTL_COLOR_FORMAT', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', - 'FMT_CONTROL_PIXEL_ENCODING', - 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', - 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 'FMT_CONTROL_SUBSAMPLING_MODE', - 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', - 'FMT_CONTROL_SUBSAMPLING_ORDER', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', - 'FMT_CRC_CNTL_CONT_EN', 'FMT_CRC_CNTL_CONT_EN_CONT', - 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', - 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', - 'FMT_CRC_CNTL_INCLUDE_OVERSCAN', - 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', - 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', - 'FMT_CRC_CNTL_INTERLACE_MODE', - 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', - 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', - 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', - 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', 'FMT_CRC_CNTL_ONLY_BLANKB', - 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', - 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', - 'FMT_CRC_CNTL_PSR_MODE_ENABLE', - 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', - 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', 'FMT_CTX1', - 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', - 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', - 'FMT_GB_GR', 'FMT_INVALID', 'FMT_RESERVED_33', 'FMT_RESERVED_36', - 'FMT_RESERVED_4', 'FMT_RESERVED_63', 'FMT_SPATIAL_DITHER_MODE', - 'FMT_SPATIAL_DITHER_MODE_0', 'FMT_SPATIAL_DITHER_MODE_1', - 'FMT_SPATIAL_DITHER_MODE_2', 'FMT_SPATIAL_DITHER_MODE_3', - 'FMT_STEREOSYNC_OVR_POL', 'FMT_STEREOSYNC_OVR_POL_INVERTED', - 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', - 'FMT_X24_8_32_FLOAT', 'FORCE_BINNING_ON', - 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', - 'FORCE_ENABLE', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', - 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', 'FORCE_OPT_AUTO', - 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', - 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', - 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', - 'FORCE_VBI', 'FORCE_VBI_HIGH', 'FORCE_VBI_LOW', 'FRAG_ALWAYS', - 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', 'FRAG_LEQUAL', - 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', 'ForceControl', - 'GAMUT_REMAP_MODE_1', 'GAMUT_REMAP_MODE_2', 'GAMUT_REMAP_MODE_3', - 'GAMUT_REMAP_MODE_BYPASS', 'GATCL1RequestType', - 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', - 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', - 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', - 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', - 'GB_TILING_CONFIG_TABLE_SIZE', 'GDS_PERFCOUNT_SELECT', - 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', - 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', - 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', - 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', - 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', - 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', - 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', - 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', - 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', - 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', - 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', - 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', - 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', - 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', - 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', - 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', - 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', - 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', - 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', - 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', - 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', - 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', - 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', - 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', - 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', - 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', - 'GDS_PERF_SEL_WR_COMP', 'GENERICA_STEREOSYNC_SEL', - 'GENERICA_STEREOSYNC_SEL_D1', 'GENERICA_STEREOSYNC_SEL_D2', - 'GENERICA_STEREOSYNC_SEL_D3', 'GENERICA_STEREOSYNC_SEL_D4', - 'GENERICA_STEREOSYNC_SEL_D5', 'GENERICA_STEREOSYNC_SEL_D6', - 'GENERICA_STEREOSYNC_SEL_RESERVED', 'GENERICB_STEREOSYNC_SEL', - 'GENERICB_STEREOSYNC_SEL_D1', 'GENERICB_STEREOSYNC_SEL_D2', - 'GENERICB_STEREOSYNC_SEL_D3', 'GENERICB_STEREOSYNC_SEL_D4', - 'GENERICB_STEREOSYNC_SEL_D5', 'GENERICB_STEREOSYNC_SEL_D6', - 'GENERICB_STEREOSYNC_SEL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', - 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', - 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', - 'GLOBAL_STATUS_FLUSH_STATUS', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', - 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', - 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', - 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', - 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', - 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', - 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', - 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', - 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', - 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', - 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', - 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', - 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', - 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', - 'GRBM_PERF_SEL_GUI_ACTIVE', 'GRBM_PERF_SEL_IA_BUSY', - 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', 'GRBM_PERF_SEL_PA_BUSY', - 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', - 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', - 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', - 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RLC_BUSY', - 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', - 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', - 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TC_BUSY', - 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL2_BUSY', - 'GRBM_PERF_SEL_VGT_BUSY', 'GRBM_PERF_SEL_WD_BUSY', - 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', 'GRBM_SE0_PERF_SEL', - 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', - 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', - 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 'GRBM_SE0_PERF_SEL_PA_BUSY', 'GRBM_SE0_PERF_SEL_RESERVED_0', - 'GRBM_SE0_PERF_SEL_RESERVED_1', 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', - 'GRBM_SE0_PERF_SEL_USER_DEFINED', 'GRBM_SE0_PERF_SEL_VGT_BUSY', - 'GRBM_SE1_PERF_SEL', 'GRBM_SE1_PERF_SEL_BCI_BUSY', - 'GRBM_SE1_PERF_SEL_CB_BUSY', 'GRBM_SE1_PERF_SEL_CB_CLEAN', - 'GRBM_SE1_PERF_SEL_COUNT', 'GRBM_SE1_PERF_SEL_DB_BUSY', - 'GRBM_SE1_PERF_SEL_DB_CLEAN', 'GRBM_SE1_PERF_SEL_PA_BUSY', - 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', - 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', - 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', - 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 'GRBM_SE1_PERF_SEL_VGT_BUSY', 'GRBM_SE2_PERF_SEL', - 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', - 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', - 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 'GRBM_SE2_PERF_SEL_PA_BUSY', 'GRBM_SE2_PERF_SEL_RESERVED_0', - 'GRBM_SE2_PERF_SEL_RESERVED_1', 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', - 'GRBM_SE2_PERF_SEL_USER_DEFINED', 'GRBM_SE2_PERF_SEL_VGT_BUSY', - 'GRBM_SE3_PERF_SEL', 'GRBM_SE3_PERF_SEL_BCI_BUSY', - 'GRBM_SE3_PERF_SEL_CB_BUSY', 'GRBM_SE3_PERF_SEL_CB_CLEAN', - 'GRBM_SE3_PERF_SEL_COUNT', 'GRBM_SE3_PERF_SEL_DB_BUSY', - 'GRBM_SE3_PERF_SEL_DB_CLEAN', 'GRBM_SE3_PERF_SEL_PA_BUSY', - 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', - 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', - 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', - 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 'GRBM_SE3_PERF_SEL_VGT_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', - 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', - 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', - 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', - 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', - 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', - 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', - 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', - 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', - 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', - 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', - 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', - 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', - 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', - 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', - 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', - 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', - 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', - 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', - 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', - 'HDMI_AUDIO_INFO_SEND', - 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'HDMI_AUDIO_SEND_MAX_PACKETS', 'HDMI_AVI_INFO_CONT', - 'HDMI_AVI_INFO_CONT_DISABLE', 'HDMI_AVI_INFO_CONT_ENABLE', - 'HDMI_AVI_INFO_NOT_SEND', 'HDMI_AVI_INFO_PKT_SEND', - 'HDMI_AVI_INFO_SEND', - 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', - 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', - 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 'HDMI_DEEP_COLOR_DEPTH_RESERVED', 'HDMI_DEFAULT_PAHSE', - 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', - 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', - 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', - 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', - 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', - 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', - 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', - 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', - 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', - 'HDMI_GC_SEND', 'HDMI_GENERIC0_CONT', - 'HDMI_GENERIC0_CONT_DISABLE', 'HDMI_GENERIC0_CONT_ENABLE', - 'HDMI_GENERIC0_NOT_SEND', 'HDMI_GENERIC0_PKT_SEND', - 'HDMI_GENERIC0_SEND', 'HDMI_GENERIC1_CONT', - 'HDMI_GENERIC1_CONT_DISABLE', 'HDMI_GENERIC1_CONT_ENABLE', - 'HDMI_GENERIC1_NOT_SEND', 'HDMI_GENERIC1_PKT_SEND', - 'HDMI_GENERIC1_SEND', 'HDMI_GENERIC2_CONT', - 'HDMI_GENERIC2_CONT_DISABLE', 'HDMI_GENERIC2_CONT_ENABLE', - 'HDMI_GENERIC2_NOT_SEND', 'HDMI_GENERIC2_PKT_SEND', - 'HDMI_GENERIC2_SEND', 'HDMI_GENERIC3_CONT', - 'HDMI_GENERIC3_CONT_DISABLE', 'HDMI_GENERIC3_CONT_ENABLE', - 'HDMI_GENERIC3_NOT_SEND', 'HDMI_GENERIC3_PKT_SEND', - 'HDMI_GENERIC3_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', - 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', - 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', - 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', - 'HDMI_MPEG_INFO_CONT', 'HDMI_MPEG_INFO_CONT_DISABLE', - 'HDMI_MPEG_INFO_CONT_ENABLE', 'HDMI_MPEG_INFO_NOT_SEND', - 'HDMI_MPEG_INFO_PKT_SEND', 'HDMI_MPEG_INFO_SEND', - 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', - 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', - 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', - 'HDMI_PACKING_PHASE_OVERRIDE', 'HDMI_PACKING_PHASE_SET_BY_HW', - 'HDMI_PACKING_PHASE_SET_BY_SW', 'HDMI_SEND_MAX_AUDIO_PACKETS', - 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', - 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', - 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', - 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', - 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_STAGE_OFF', 'HS_STAGE_ON', - 'HW_SOURCE_SEL_DSC_JPEG', 'HW_SOURCE_SEL_DSC_VLP', - 'HW_SOURCE_SEL_DSC_VUP', 'HW_SOURCE_SEL_NONE', - 'I2S0_SPDIF0_SOFT_RESET', 'I2S0_SPDIF0_SOFT_RESET_0', - 'I2S0_SPDIF0_SOFT_RESET_1', 'I2S1_SOFT_RESET', - 'I2S1_SOFT_RESET_0', 'I2S1_SOFT_RESET_1', 'I2S_LRCLK_HIGH_LEFT', - 'I2S_LRCLK_LOW_LEFT', 'I2S_LRCLK_POLARITY', - 'I2S_SAMPLE_ALIGNMENT', 'I2S_SAMPLE_BIT_ORDER', - 'I2S_SAMPLE_BIT_ORDER_LSB', 'I2S_SAMPLE_BIT_ORDER_MSB', - 'I2S_SAMPLE_LEFT_ALIGNED', 'I2S_SAMPLE_RIGHT_ALIGNED', - 'I2S_WORD_ALIGNMENT', 'I2S_WORD_ALTERNATE_ALIGNMENT', - 'I2S_WORD_I2S_ALIGNMENT', 'I2S_WORD_SIZE', 'I2S_WORD_SIZE_16', - 'I2S_WORD_SIZE_32', 'IA_PERFCOUNT_SELECT', - 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', - 'IH_PERF_SEL', 'IH_PERF_SEL_BIF_LINE0_FALLING', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 'IH_PERF_SEL_BIF_LINE0_RISING', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', 'IH_PERF_SEL_BUFFER_IDLE', - 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', - 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', - 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', - 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', - 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', - 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', - 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', - 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', - 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', - 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', - 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', - 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', - 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', - 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', - 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', - 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', - 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', - 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', - 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', - 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_VF0', - 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', - 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', - 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', - 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', - 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', - 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', - 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', - 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', - 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', - 'IH_PERF_SEL_RB1_FULL_VF0', 'IH_PERF_SEL_RB1_FULL_VF1', - 'IH_PERF_SEL_RB1_FULL_VF10', 'IH_PERF_SEL_RB1_FULL_VF11', - 'IH_PERF_SEL_RB1_FULL_VF12', 'IH_PERF_SEL_RB1_FULL_VF13', - 'IH_PERF_SEL_RB1_FULL_VF14', 'IH_PERF_SEL_RB1_FULL_VF15', - 'IH_PERF_SEL_RB1_FULL_VF2', 'IH_PERF_SEL_RB1_FULL_VF3', - 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', - 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', - 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', - 'IH_PERF_SEL_RB1_OVERFLOW', 'IH_PERF_SEL_RB1_OVERFLOW_VF0', - 'IH_PERF_SEL_RB1_OVERFLOW_VF1', 'IH_PERF_SEL_RB1_OVERFLOW_VF10', - 'IH_PERF_SEL_RB1_OVERFLOW_VF11', 'IH_PERF_SEL_RB1_OVERFLOW_VF12', - 'IH_PERF_SEL_RB1_OVERFLOW_VF13', 'IH_PERF_SEL_RB1_OVERFLOW_VF14', - 'IH_PERF_SEL_RB1_OVERFLOW_VF15', 'IH_PERF_SEL_RB1_OVERFLOW_VF2', - 'IH_PERF_SEL_RB1_OVERFLOW_VF3', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', - 'IH_PERF_SEL_RB2_FULL_VF0', 'IH_PERF_SEL_RB2_FULL_VF1', - 'IH_PERF_SEL_RB2_FULL_VF10', 'IH_PERF_SEL_RB2_FULL_VF11', - 'IH_PERF_SEL_RB2_FULL_VF12', 'IH_PERF_SEL_RB2_FULL_VF13', - 'IH_PERF_SEL_RB2_FULL_VF14', 'IH_PERF_SEL_RB2_FULL_VF15', - 'IH_PERF_SEL_RB2_FULL_VF2', 'IH_PERF_SEL_RB2_FULL_VF3', - 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', - 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', - 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', - 'IH_PERF_SEL_RB2_OVERFLOW', 'IH_PERF_SEL_RB2_OVERFLOW_VF0', - 'IH_PERF_SEL_RB2_OVERFLOW_VF1', 'IH_PERF_SEL_RB2_OVERFLOW_VF10', - 'IH_PERF_SEL_RB2_OVERFLOW_VF11', 'IH_PERF_SEL_RB2_OVERFLOW_VF12', - 'IH_PERF_SEL_RB2_OVERFLOW_VF13', 'IH_PERF_SEL_RB2_OVERFLOW_VF14', - 'IH_PERF_SEL_RB2_OVERFLOW_VF15', 'IH_PERF_SEL_RB2_OVERFLOW_VF2', - 'IH_PERF_SEL_RB2_OVERFLOW_VF3', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IMG_DATA_FORMAT', - 'IMG_DATA_FORMAT_10_10_10_2', 'IMG_DATA_FORMAT_10_11_11', - 'IMG_DATA_FORMAT_11_11_10', 'IMG_DATA_FORMAT_16', - 'IMG_DATA_FORMAT_16_16', 'IMG_DATA_FORMAT_16_16_16_16', - 'IMG_DATA_FORMAT_16_AS_16_16_16_16', - 'IMG_DATA_FORMAT_16_AS_32_32', - 'IMG_DATA_FORMAT_16_AS_32_32_32_32', 'IMG_DATA_FORMAT_1_5_5_5', - 'IMG_DATA_FORMAT_24_8', 'IMG_DATA_FORMAT_2_10_10_10', - 'IMG_DATA_FORMAT_32', 'IMG_DATA_FORMAT_32_32', - 'IMG_DATA_FORMAT_32_32_32', 'IMG_DATA_FORMAT_32_32_32_32', - 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', - 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', - 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', - 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', - 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', - 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', - 'IMG_DATA_FORMAT_8_AS_32', 'IMG_DATA_FORMAT_8_AS_32_32', - 'IMG_DATA_FORMAT_8_AS_8_8_8_8', 'IMG_DATA_FORMAT_ASTC_2D_HDR', - 'IMG_DATA_FORMAT_ASTC_2D_LDR', 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', - 'IMG_DATA_FORMAT_ASTC_3D_HDR', 'IMG_DATA_FORMAT_ASTC_3D_LDR', - 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', 'IMG_DATA_FORMAT_BC1', - 'IMG_DATA_FORMAT_BC2', 'IMG_DATA_FORMAT_BC3', - 'IMG_DATA_FORMAT_BC4', 'IMG_DATA_FORMAT_BC5', - 'IMG_DATA_FORMAT_BC6', 'IMG_DATA_FORMAT_BC7', - 'IMG_DATA_FORMAT_BG_RG', 'IMG_DATA_FORMAT_ETC2_R', - 'IMG_DATA_FORMAT_ETC2_RG', 'IMG_DATA_FORMAT_ETC2_RGB', - 'IMG_DATA_FORMAT_ETC2_RGBA', 'IMG_DATA_FORMAT_ETC2_RGBA1', - 'IMG_DATA_FORMAT_FMASK', 'IMG_DATA_FORMAT_GB_GR', - 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_N_IN_16', - 'IMG_DATA_FORMAT_N_IN_16_16', 'IMG_DATA_FORMAT_N_IN_16_16_16_16', - 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', - 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_29', - 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_56', - 'IMG_DATA_FORMAT_RESERVED_59', 'IMG_DATA_FORMAT_RESERVED_60', - 'IMG_DATA_FORMAT_X24_8_32', 'IMG_NUM_FORMAT', - 'IMG_NUM_FORMAT_ASTC_2D', 'IMG_NUM_FORMAT_ASTC_2D_10x10', - 'IMG_NUM_FORMAT_ASTC_2D_10x5', 'IMG_NUM_FORMAT_ASTC_2D_10x6', - 'IMG_NUM_FORMAT_ASTC_2D_10x8', 'IMG_NUM_FORMAT_ASTC_2D_12x10', - 'IMG_NUM_FORMAT_ASTC_2D_12x12', 'IMG_NUM_FORMAT_ASTC_2D_4x4', - 'IMG_NUM_FORMAT_ASTC_2D_5x4', 'IMG_NUM_FORMAT_ASTC_2D_5x5', - 'IMG_NUM_FORMAT_ASTC_2D_6x5', 'IMG_NUM_FORMAT_ASTC_2D_6x6', - 'IMG_NUM_FORMAT_ASTC_2D_8x5', 'IMG_NUM_FORMAT_ASTC_2D_8x6', - 'IMG_NUM_FORMAT_ASTC_2D_8x8', - 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', - 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', 'IMG_NUM_FORMAT_ASTC_3D', - 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', - 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', - 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', - 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', - 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', - 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', 'IMG_NUM_FORMAT_FLOAT', - 'IMG_NUM_FORMAT_FMASK', 'IMG_NUM_FORMAT_FMASK_16_16_1', - 'IMG_NUM_FORMAT_FMASK_16_8_2', 'IMG_NUM_FORMAT_FMASK_32_16_2', - 'IMG_NUM_FORMAT_FMASK_32_8_4', 'IMG_NUM_FORMAT_FMASK_32_8_8', - 'IMG_NUM_FORMAT_FMASK_64_16_4', 'IMG_NUM_FORMAT_FMASK_64_16_8', - 'IMG_NUM_FORMAT_FMASK_8_2_1', 'IMG_NUM_FORMAT_FMASK_8_2_2', - 'IMG_NUM_FORMAT_FMASK_8_4_1', 'IMG_NUM_FORMAT_FMASK_8_4_2', - 'IMG_NUM_FORMAT_FMASK_8_4_4', 'IMG_NUM_FORMAT_FMASK_8_8_1', - 'IMG_NUM_FORMAT_FMASK_RESERVED_13', - 'IMG_NUM_FORMAT_FMASK_RESERVED_14', - 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', - 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', - 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', - 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', - 'IMG_NUM_FORMAT_RESERVED_10', 'IMG_NUM_FORMAT_RESERVED_11', - 'IMG_NUM_FORMAT_RESERVED_12', 'IMG_NUM_FORMAT_RESERVED_13', - 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', - 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', - 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SRGB', - 'IMG_NUM_FORMAT_SSCALED', 'IMG_NUM_FORMAT_UINT', - 'IMG_NUM_FORMAT_UNORM', 'IMG_NUM_FORMAT_UNORM_UINT', - 'IMG_NUM_FORMAT_USCALED', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 'INGAMMA_MODE_BYPASS', 'INGAMMA_MODE_FIX', 'INGAMMA_MODE_FLOAT', - 'INPUTCSC_MODE_A', 'INPUTCSC_MODE_B', 'INPUTCSC_MODE_BYPASS', - 'INPUTCSC_MODE_UNITY', 'INPUTCSC_ROUND', 'INPUTCSC_TRUNCATE', - 'INPUTCSC_TYPE_10_2', 'INPUTCSC_TYPE_12_0', 'INPUTCSC_TYPE_8_4', - 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', - 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', - 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', - 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', - 'INTERLACE_SOURCE_INTERLEAVE', 'INTERLACE_SOURCE_PROGRESSIVE', - 'INTERLACE_SOURCE_STACK', 'INTERLEAVE_DIS', 'INTERLEAVE_EN', - 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', - 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', - 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', - 'LATE_Z', 'LBV_DITHER_EN', 'LBV_DOWNSCALE_PREFETCH_EN', - 'LBV_DYNAMIC_PIXEL_DEPTH', 'LBV_INTERLEAVE_EN', - 'LBV_MEMORY_CONFIG', 'LBV_PIXEL_DEPTH', 'LBV_PIXEL_EXPAN_MODE', - 'LBV_PIXEL_REDUCE_MODE', 'LBV_SYNC_DURATION', - 'LBV_SYNC_RESET_SEL2', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK', - 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', - 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', - 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK', - 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', - 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', - 'LB_DATA_FORMAT_ALPHA_DISABLE', 'LB_DATA_FORMAT_ALPHA_EN', - 'LB_DATA_FORMAT_ALPHA_ENABLE', - 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH', - 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', - 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', - 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', - 'LB_DATA_FORMAT_INTERLEAVE_EN', - 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', 'LB_DATA_FORMAT_PIXEL_DEPTH', - 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', - 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', - 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', - 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', - 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE', - 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', - 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', - 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE', - 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', - 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', - 'LB_DATA_FORMAT_REQUEST_MODE', - 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', - 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', - 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', - 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE', - 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', - 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', - 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK', - 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', - 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', - 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK', - 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', - 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', - 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', - 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', - 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', - 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE', - 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', - 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', - 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', - 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION', - 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', - 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', - 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', - 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', - 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', - 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN', - 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', - 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', - 'LB_VBLANK_STATUS_VBLANK_ACK', 'LB_VBLANK_STATUS_VBLANK_CLEAR', - 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE', - 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', - 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', - 'LB_VBLANK_STATUS_VBLANK_NORMAL', - 'LB_VLINE2_START_END_VLINE2_INV', - 'LB_VLINE2_START_END_VLINE2_INVERSE', - 'LB_VLINE2_START_END_VLINE2_NORMAL', - 'LB_VLINE2_STATUS_VLINE2_ACK', 'LB_VLINE2_STATUS_VLINE2_CLEAR', - 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE', - 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', - 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', - 'LB_VLINE2_STATUS_VLINE2_NORMAL', 'LB_VLINE_START_END_VLINE_INV', - 'LB_VLINE_START_END_VLINE_INVERSE', - 'LB_VLINE_START_END_VLINE_NORMAL', 'LB_VLINE_STATUS_VLINE_ACK', - 'LB_VLINE_STATUS_VLINE_CLEAR', - 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE', - 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', - 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', - 'LB_VLINE_STATUS_VLINE_NORMAL', 'LINESTRIP', - 'LPT_NUM_BANKS_16BANK', 'LPT_NUM_BANKS_2BANK', - 'LPT_NUM_BANKS_32BANK', 'LPT_NUM_BANKS_4BANK', - 'LPT_NUM_BANKS_8BANK', 'LPT_NUM_PIPES_1CH', 'LPT_NUM_PIPES_2CH', - 'LPT_NUM_PIPES_4CH', 'LPT_NUM_PIPES_8CH', 'LS_STAGE_OFF', - 'LS_STAGE_ON', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', - 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'LptNumBanks', 'LptNumPipes', - 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', 'MEMORY_CONFIG_0', - 'MEMORY_CONFIG_1', 'MEMORY_CONFIG_2', 'MEMORY_CONFIG_3', - 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', - 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', 'MEM_PWR_FORCE_CTRL', - 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', - 'ME_ID0', 'ME_ID1', 'ME_ID2', 'ME_ID3', - 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', - 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', - 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_ROTATED', - 'MICRO_TILE_MODE_STD_2D', 'MICRO_TILE_MODE_STD_3D', - 'MICRO_TILE_MODE_Z_2D', 'MICRO_TILE_MODE_Z_3D', - 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', - 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MSA_MISC0_OVERRIDE_DISABLE', 'MSA_MISC0_OVERRIDE_ENABLE', - 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', - 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', - 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', - 'MTYPE', 'MTYPE_CC', 'MTYPE_NC', 'MTYPE_RW', 'MTYPE_UC', - 'MTYPE_WC', 'MULT_16', 'MULT_8', 'MVP_CLK_SRC_SEL', - 'MVP_CLK_SRC_SEL_IO_1', 'MVP_CLK_SRC_SEL_IO_2', - 'MVP_CLK_SRC_SEL_REFCLK', 'MVP_CLK_SRC_SEL_RSRV', - 'MVP_SOFT_RESET', 'MVP_SOFT_RESET_0', 'MVP_SOFT_RESET_1', - 'MacroTileAspect', 'MemArbMode', 'MicroTileMode', - 'MultiGPUTileSize', 'NOT_SENT', 'NO_DIST', 'NO_FORCE', - 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', 'NUMBER_FLOAT', 'NUMBER_SINT', - 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', - 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_SIMD_PER_CU', - 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', - 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', - 'NumRbPerShaderEngine', 'NumShaderEngines', 'OFFCHIP_HS_DEALLOC', - 'OFF_SEQ', 'ON_SEQ', 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', - 'OPT_COMB_MAX', 'OPT_COMB_MIN', 'OPT_COMB_NONE', - 'OPT_COMB_REVSUBTRACT', 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', - 'OUTPUT_LINE', 'OUTPUT_POINT', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', - 'OVERRIDE_CGTT_DCEFCLK', 'OVERRIDE_CGTT_DCEFCLK_NOOP', - 'OVERRIDE_CGTT_SCLK', 'OVERRIDE_CGTT_SCLK_NOOP', 'PART_FRAC_EVEN', - 'PART_FRAC_ODD', 'PART_INTEGER', 'PART_POW2', 'PATCHES', - 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', - 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', - 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', - 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', - 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', - 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', - 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', - 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', - 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', - 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', - 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', - 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', - 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', - 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', - 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', - 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', - 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', - 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', - 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', - 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', - 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', - 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', - 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', - 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', - 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', - 'PERFCOUNTER_CNTOFF_START_DIS', - 'PERFCOUNTER_CNTOFF_START_DISABLE', - 'PERFCOUNTER_CNTOFF_START_ENABLE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', - 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', - 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', - 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', - 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', - 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', - 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_INC_MODE', - 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', - 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', - 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', - 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', - 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', - 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', - 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', - 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', - 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', - 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', - 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', - 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', - 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', - 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', - 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', - 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', - 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', - 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', - 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', - 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', - 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', - 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', - 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', - 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', - 'PERFMON_COUNTER_MODE_ACCUM', - 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 'PERFMON_COUNTER_MODE_DIRTY', - 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', - 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', - 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', - 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', - 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', - 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', - 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', - 'PERFMON_STATE_START', 'PERF_PAPC_CCGSM_BUSY', - 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', - 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', - 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', - 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', - 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', - 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', - 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', - 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', - 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', - 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', - 'PERF_PAPC_PASX_REC_STALLED', - 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', - 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', - 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', - 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', - 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', - 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', - 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', - 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', - 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', - 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE01_STALLED_SC', - 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE0_STALLED_SC', - 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE1_STALLED_SC', - 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE2_STALLED_SC', - 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', - 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 'PERSISTENT_SPACE_END', 'PERSISTENT_SPACE_START', - 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ID0', 'PIPE_ID1', - 'PIPE_ID2', 'PIPE_ID3', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', - 'PIPE_PIXEL_RATE_PLL_SOURCE', - 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', - 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', - 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIXEL_DEPTH_18BPP', - 'PIXEL_DEPTH_24BPP', 'PIXEL_DEPTH_30BPP', 'PIXEL_DEPTH_38BPP', - 'PIXEL_EXPAN_MODE_DYN_EXP', 'PIXEL_EXPAN_MODE_ZERO_EXP', - 'PIXEL_FORMAT_RGB_444', 'PIXEL_FORMAT_YCBCR_422', - 'PIXEL_FORMAT_YCBCR_444', 'PIXEL_FORMAT_Y_ONLY', - 'PIXEL_PIPE_OCCLUSION_COUNT_0', 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 'PIXEL_PIPE_OCCLUSION_COUNT_2', 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', - 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', - 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', - 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', - 'PIXEL_REDUCE_MODE_ROUNDING', 'PIXEL_REDUCE_MODE_TRUNCATION', - 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', - 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', - 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', - 'PRESCALE_MODE_BYPASS', 'PRESCALE_MODE_PROGRAM', - 'PRESCALE_MODE_UNITY', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', - 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', - 'PS_PARTIAL_FLUSH', 'PULSE_MODE_OPT_NO_HSA', - 'PULSE_MODE_OPT_SEND', 'PerfCounter_Vals', 'PipeConfig', - 'PipeInterleaveSize', 'PipeTiling', 'PixelPipeCounterId', - 'PixelPipeStride', 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', - 'QuadExportFormat', 'QuadExportFormatOld', - 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', - 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', - 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', - 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', - 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', - 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', - 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', - 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', - 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', - 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', - 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', - 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', - 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', - 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', - 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', - 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', - 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', - 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', - 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', - 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', - 'RASTER_CONFIG_SE_PAIR_MAP_3', - 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'READ_256_BITS', - 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', - 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', - 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', - 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REF_ALWAYS', 'REF_EQUAL', - 'REF_GEQUAL', 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', - 'REF_NEVER', 'REF_NOTEQUAL', 'RESERVED_ES', 'RESERVED_LS', - 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', - 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', - 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', - 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', - 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', - 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', - 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', - 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', - 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', - 'RMI_PERF_SEL_LAT_FIFO_FULL', - 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', - 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', 'RMI_PERF_SEL_NONE', - 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', - 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', - 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', - 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', - 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', - 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', - 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', - 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', - 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', - 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', - 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', - 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', - 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', - 'RMI_PERF_SEL_PRT_FIFO_REQ', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', - 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', - 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', - 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', - 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', - 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', - 'RMI_PERF_SEL_REORDER_FIFO_REQ', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', - 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', - 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', - 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', - 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', - 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', - 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', - 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', - 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', - 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', - 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', - 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', - 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', - 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', - 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', - 'RMI_PERF_SEL_TCIW_REQ', - 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', - 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', - 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', - 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', - 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', - 'RMI_PERF_SEL_UTCL1_REQUEST', - 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', - 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', - 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', - 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', - 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', - 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', - 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', - 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', - 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', - 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', - 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', - 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RST_PIX_CNT', 'RSV_TAG_RAM', - 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadSize', 'Reserved142', - 'Reserved143', 'Reserved144', 'Reserved145', 'Reserved146', - 'Reserved147', 'Reserved148', 'Reserved149', 'Reserved18', - 'Reserved182', 'Reserved183', 'Reserved184', 'Reserved185', - 'Reserved186', 'Reserved187', 'Reserved188', 'Reserved189', - 'Reserved190', 'Reserved191', 'Reserved192', 'Reserved193', - 'Reserved194', 'Reserved195', 'Reserved196', 'Reserved197', - 'Reserved198', 'Reserved199', 'Reserved200', 'Reserved201', - 'Reserved202', 'Reserved203', 'Reserved204', 'Reserved205', - 'Reserved206', 'Reserved207', 'Reserved208', 'Reserved209', - 'Reserved210', 'Reserved211', 'Reserved212', 'Reserved213', - 'Reserved214', 'Reserved215', 'Reserved216', 'Reserved217', - 'Reserved218', 'Reserved219', 'Reserved23', 'Reserved252', - 'Reserved253', 'Reserved254', 'Reserved255', 'Reserved256', - 'Reserved257', 'Reserved258', 'Reserved259', 'Reserved26', - 'Reserved260', 'Reserved261', 'Reserved262', 'Reserved263', - 'Reserved264', 'Reserved265', 'Reserved266', 'Reserved267', - 'Reserved27', 'Reserved28', 'Reserved29', 'Reserved300', - 'Reserved301', 'Reserved302', 'Reserved303', 'Reserved304', - 'Reserved305', 'Reserved306', 'Reserved307', 'Reserved308', - 'Reserved309', 'Reserved310', 'Reserved311', 'Reserved312', - 'Reserved313', 'Reserved314', 'Reserved315', 'Reserved316', - 'Reserved317', 'Reserved318', 'Reserved319', 'Reserved320', - 'Reserved321', 'Reserved322', 'Reserved323', 'Reserved324', - 'Reserved325', 'Reserved326', 'Reserved327', 'Reserved328', - 'Reserved329', 'Reserved330', 'Reserved331', 'Reserved364', - 'Reserved365', 'Reserved366', 'Reserved367', 'Reserved368', - 'Reserved369', 'Reserved370', 'Reserved371', 'Reserved372', - 'Reserved373', 'Reserved374', 'Reserved375', 'Reserved376', - 'Reserved377', 'Reserved378', 'Reserved379', 'Reserved412', - 'Reserved413', 'Reserved414', 'Reserved415', 'Reserved416', - 'Reserved417', 'Reserved418', 'Reserved419', 'Reserved420', - 'Reserved421', 'Reserved422', 'Reserved423', 'Reserved424', - 'Reserved425', 'Reserved426', 'Reserved427', 'Reserved428', - 'Reserved429', 'Reserved430', 'Reserved431', 'Reserved432', - 'Reserved433', 'Reserved434', 'Reserved435', 'Reserved436', - 'Reserved437', 'Reserved438', 'Reserved439', 'Reserved440', - 'Reserved441', 'Reserved442', 'Reserved443', 'Reserved444', - 'Reserved445', 'Reserved446', 'Reserved447', 'Reserved448', - 'Reserved449', 'Reserved450', 'Reserved451', 'Reserved452', - 'Reserved453', 'Reserved454', 'Reserved455', 'Reserved456', - 'Reserved457', 'Reserved458', 'Reserved459', 'Reserved460', - 'Reserved461', 'Reserved462', 'Reserved463', 'Reserved464', - 'Reserved465', 'Reserved466', 'Reserved467', 'Reserved468', - 'Reserved469', 'Reserved470', 'Reserved471', 'Reserved472', - 'Reserved473', 'Reserved474', 'Reserved475', 'Reserved476', - 'Reserved477', 'Reserved478', 'Reserved479', 'Reserved480', - 'Reserved481', 'Reserved482', 'Reserved483', 'Reserved484', - 'Reserved485', 'Reserved486', 'Reserved487', 'Reserved488', - 'Reserved489', 'Reserved490', 'Reserved491', 'Reserved492', - 'Reserved493', 'Reserved494', 'Reserved495', 'Reserved496', - 'Reserved497', 'Reserved498', 'Reserved499', 'Reserved500', - 'Reserved501', 'Reserved502', 'Reserved503', 'Reserved504', - 'Reserved505', 'Reserved506', 'Reserved507', 'Reserved508', - 'Reserved509', 'Reserved510', 'Reserved511', 'Reserved_0x00', - 'Reserved_0x09', 'Reserved_0x3f', 'RingCounterControl', - 'RoundMode', 'RowSize', 'RowTiling', 'SAMPLE_PIPELINESTAT', - 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', - 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', - 'SCLV_COEF_UPDATE_COMPLETE', 'SCLV_INTERLACE_SOURCE', - 'SCLV_MODE_RGB_BYPASS', 'SCLV_MODE_RGB_SCALING', 'SCLV_MODE_SEL', - 'SCLV_MODE_YCBCR_BYPASS', 'SCLV_MODE_YCBCR_SCALING', - 'SCLV_UPDATE_LOCK', 'SCL_ALU_DISABLE', 'SCL_ALU_DISABLED', - 'SCL_ALU_ENABLED', 'SCL_BOUNDARY_MODE', 'SCL_BOUNDARY_MODE_BLACK', - 'SCL_BOUNDARY_MODE_EDGE', 'SCL_BYPASS_MODE', - 'SCL_BYPASS_MODE_AC_AR', 'SCL_BYPASS_MODE_AC_NR', - 'SCL_BYPASS_MODE_MC_MR', 'SCL_BYPASS_MODE_RESERVED', - 'SCL_COEF_UPDATE_COMPLETE', 'SCL_COEF_UPDATE_COMPLETED', - 'SCL_COEF_UPDATE_NOT_COMPLETED', 'SCL_C_RAM_FILTER_TYPE', - 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', - 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', - 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', - 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', 'SCL_C_RAM_PHASE', - 'SCL_C_RAM_PHASE_0', 'SCL_C_RAM_PHASE_1', 'SCL_C_RAM_PHASE_2', - 'SCL_C_RAM_PHASE_3', 'SCL_C_RAM_PHASE_4', 'SCL_C_RAM_PHASE_5', - 'SCL_C_RAM_PHASE_6', 'SCL_C_RAM_PHASE_7', 'SCL_C_RAM_PHASE_8', - 'SCL_C_RAM_TAP_PAIR_ID0', 'SCL_C_RAM_TAP_PAIR_ID1', - 'SCL_C_RAM_TAP_PAIR_ID2', 'SCL_C_RAM_TAP_PAIR_ID3', - 'SCL_C_RAM_TAP_PAIR_ID4', 'SCL_C_RAM_TAP_PAIR_IDX', - 'SCL_EARLY_EOL_MOD', 'SCL_EARLY_EOL_MODE_CRTC', - 'SCL_EARLY_EOL_MODE_INTERNAL', 'SCL_HF_SHARP_DISABLE', - 'SCL_HF_SHARP_EN', 'SCL_HF_SHARP_ENABLE', - 'SCL_HF_SHARP_SCALE_FACTOR', 'SCL_HF_SHARP_SCALE_FACTOR_0', - 'SCL_HF_SHARP_SCALE_FACTOR_1', 'SCL_HF_SHARP_SCALE_FACTOR_2', - 'SCL_HF_SHARP_SCALE_FACTOR_3', 'SCL_HF_SHARP_SCALE_FACTOR_4', - 'SCL_HF_SHARP_SCALE_FACTOR_5', 'SCL_HF_SHARP_SCALE_FACTOR_6', - 'SCL_HF_SHARP_SCALE_FACTOR_7', - 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', - 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', 'SCL_HOST_CONFLICT_MASK', - 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', 'SCL_H_2TAP_HARDCODE_COEF_EN', - 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', - 'SCL_H_CALC_AUTO_RATIO_DISABLE', 'SCL_H_CALC_AUTO_RATIO_EN', - 'SCL_H_CALC_AUTO_RATIO_ENABLE', 'SCL_H_FILTER_PICK_NEAREST', - 'SCL_H_FILTER_PICK_NEAREST_DISABLE', - 'SCL_H_FILTER_PICK_NEAREST_ENABLE', - 'SCL_H_MANUAL_REPLICATE_FACTOR', - 'SCL_H_MANUAL_REPLICATE_FACTOR_1', - 'SCL_H_MANUAL_REPLICATE_FACTOR_10', - 'SCL_H_MANUAL_REPLICATE_FACTOR_11', - 'SCL_H_MANUAL_REPLICATE_FACTOR_12', - 'SCL_H_MANUAL_REPLICATE_FACTOR_13', - 'SCL_H_MANUAL_REPLICATE_FACTOR_14', - 'SCL_H_MANUAL_REPLICATE_FACTOR_15', - 'SCL_H_MANUAL_REPLICATE_FACTOR_16', - 'SCL_H_MANUAL_REPLICATE_FACTOR_2', - 'SCL_H_MANUAL_REPLICATE_FACTOR_3', - 'SCL_H_MANUAL_REPLICATE_FACTOR_4', - 'SCL_H_MANUAL_REPLICATE_FACTOR_5', - 'SCL_H_MANUAL_REPLICATE_FACTOR_6', - 'SCL_H_MANUAL_REPLICATE_FACTOR_7', - 'SCL_H_MANUAL_REPLICATE_FACTOR_8', - 'SCL_H_MANUAL_REPLICATE_FACTOR_9', 'SCL_H_NUM_OF_TAPS', - 'SCL_H_NUM_OF_TAPS_1', 'SCL_H_NUM_OF_TAPS_10', - 'SCL_H_NUM_OF_TAPS_2', 'SCL_H_NUM_OF_TAPS_4', - 'SCL_H_NUM_OF_TAPS_6', 'SCL_H_NUM_OF_TAPS_8', - 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', - 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', 'SCL_MODE_RGB_BYPASS', - 'SCL_MODE_RGB_SCALING', 'SCL_MODE_SEL', 'SCL_MODE_YCBCR_BYPASS', - 'SCL_MODE_YCBCR_SCALING', 'SCL_PSCL_DISABLE', 'SCL_PSCL_EN', - 'SCL_PSCL_ENANBLE', 'SCL_SCL_MODE_CHANGE_MASK', 'SCL_UPDATE_LOCK', - 'SCL_UPDATE_LOCKED', 'SCL_UPDATE_TAKEN', 'SCL_UPDATE_TAKEN_NO', - 'SCL_UPDATE_TAKEN_YES', 'SCL_UPDATE_UNLOCKED', - 'SCL_VF_SHARP_DISABLE', 'SCL_VF_SHARP_EN', 'SCL_VF_SHARP_ENABLE', - 'SCL_VF_SHARP_SCALE_FACTOR', 'SCL_VF_SHARP_SCALE_FACTOR_0', - 'SCL_VF_SHARP_SCALE_FACTOR_1', 'SCL_VF_SHARP_SCALE_FACTOR_2', - 'SCL_VF_SHARP_SCALE_FACTOR_3', 'SCL_VF_SHARP_SCALE_FACTOR_4', - 'SCL_VF_SHARP_SCALE_FACTOR_5', 'SCL_VF_SHARP_SCALE_FACTOR_6', - 'SCL_VF_SHARP_SCALE_FACTOR_7', 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', - 'SCL_V_2TAP_HARDCODE_COEF_EN', 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', - 'SCL_V_CALC_AUTO_RATIO_DISABLE', 'SCL_V_CALC_AUTO_RATIO_EN', - 'SCL_V_CALC_AUTO_RATIO_ENABLE', 'SCL_V_FILTER_PICK_NEAREST', - 'SCL_V_FILTER_PICK_NEAREST_DISABLE', - 'SCL_V_FILTER_PICK_NEAREST_ENABLE', - 'SCL_V_MANUAL_REPLICATE_FACTOR', - 'SCL_V_MANUAL_REPLICATE_FACTOR_1', - 'SCL_V_MANUAL_REPLICATE_FACTOR_10', - 'SCL_V_MANUAL_REPLICATE_FACTOR_11', - 'SCL_V_MANUAL_REPLICATE_FACTOR_12', - 'SCL_V_MANUAL_REPLICATE_FACTOR_13', - 'SCL_V_MANUAL_REPLICATE_FACTOR_14', - 'SCL_V_MANUAL_REPLICATE_FACTOR_15', - 'SCL_V_MANUAL_REPLICATE_FACTOR_16', - 'SCL_V_MANUAL_REPLICATE_FACTOR_2', - 'SCL_V_MANUAL_REPLICATE_FACTOR_3', - 'SCL_V_MANUAL_REPLICATE_FACTOR_4', - 'SCL_V_MANUAL_REPLICATE_FACTOR_5', - 'SCL_V_MANUAL_REPLICATE_FACTOR_6', - 'SCL_V_MANUAL_REPLICATE_FACTOR_7', - 'SCL_V_MANUAL_REPLICATE_FACTOR_8', - 'SCL_V_MANUAL_REPLICATE_FACTOR_9', 'SCL_V_NUM_OF_TAPS', - 'SCL_V_NUM_OF_TAPS_1', 'SCL_V_NUM_OF_TAPS_2', - 'SCL_V_NUM_OF_TAPS_3', 'SCL_V_NUM_OF_TAPS_4', - 'SCL_V_NUM_OF_TAPS_5', 'SCL_V_NUM_OF_TAPS_6', 'SC_BACKEND_BUSY', - 'SC_BB_DISCARD', 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', - 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_EARLYZ_QUAD_COUNT', - 'SC_EARLYZ_QUAD_WITH_1_PIX', 'SC_EARLYZ_QUAD_WITH_2_PIX', - 'SC_EARLYZ_QUAD_WITH_3_PIX', 'SC_EARLYZ_QUAD_WITH_4_PIX', - 'SC_EOP_SYNC_WINDOW', 'SC_GRP0_DYN_SCLK_BUSY', - 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', - 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', - 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', - 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', - 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', - 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', - 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_PS_DATA_SEND', - 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', - 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', - 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', - 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', - 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', - 'SC_PA1_PS_DATA_SEND', 'SC_PA1_SC_DATA_FIFO_EOPG_RD', - 'SC_PA1_SC_DATA_FIFO_EOP_RD', 'SC_PA1_SC_DATA_FIFO_RD', - 'SC_PA1_SC_DATA_FIFO_WE', 'SC_PA1_SC_DEALLOC_0_RD', - 'SC_PA1_SC_DEALLOC_1_RD', 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', - 'SC_PA1_SC_EVENT_WE', 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', - 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', - 'SC_PA2_PS_DATA_SEND', 'SC_PA2_SC_DATA_FIFO_EOPG_RD', - 'SC_PA2_SC_DATA_FIFO_EOP_RD', 'SC_PA2_SC_DATA_FIFO_RD', - 'SC_PA2_SC_DATA_FIFO_WE', 'SC_PA2_SC_DEALLOC_0_RD', - 'SC_PA2_SC_DEALLOC_1_RD', 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', - 'SC_PA2_SC_EVENT_WE', 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', - 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', - 'SC_PA3_PS_DATA_SEND', 'SC_PA3_SC_DATA_FIFO_EOPG_RD', - 'SC_PA3_SC_DATA_FIFO_EOP_RD', 'SC_PA3_SC_DATA_FIFO_RD', - 'SC_PA3_SC_DATA_FIFO_WE', 'SC_PA3_SC_DEALLOC_0_RD', - 'SC_PA3_SC_DEALLOC_1_RD', 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', - 'SC_PA3_SC_EVENT_WE', 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', - 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', - 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', - 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', - 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', - 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', - 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', 'SC_PBB_BUSY_AND_RTR', - 'SC_PBB_END_OF_BATCH', 'SC_PBB_END_OF_BIN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', - 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', - 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', - 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', - 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', - 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', - 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', - 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', - 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', - 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', - 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', - 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', - 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', - 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', - 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', - 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', - 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', - 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', - 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TS_EVENT_FIFO_POP', - 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_QZ0_MULTI_GPU_TILE_DISCARD', - 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', - 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', - 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', - 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', - 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', - 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', - 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', - 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', - 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', - 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', - 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_MULTI_GPU_TILE_DISCARD', - 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', - 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', - 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', - 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', - 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', - 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', - 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', - 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', - 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', - 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', - 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_MULTI_GPU_TILE_DISCARD', - 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', - 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', - 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', - 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', - 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', - 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', - 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', - 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', - 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', - 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', - 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_MULTI_GPU_TILE_DISCARD', - 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', - 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', - 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', - 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', - 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', - 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', - 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', - 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', - 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', - 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', - 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', - 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_SCB_BUSY', - 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', - 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', - 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', - 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', - 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', - 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', - 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', - 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', - 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', - 'SC_SEND_DB_VPZ', 'SC_SRPS_WINDOW_VALID', - 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', - 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', - 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', - 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', - 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', - 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 'SC_SUPERTILE_COUNT', 'SC_SUPERTILE_PER_PRIM_H0', - 'SC_SUPERTILE_PER_PRIM_H1', 'SC_SUPERTILE_PER_PRIM_H10', - 'SC_SUPERTILE_PER_PRIM_H11', 'SC_SUPERTILE_PER_PRIM_H12', - 'SC_SUPERTILE_PER_PRIM_H13', 'SC_SUPERTILE_PER_PRIM_H14', - 'SC_SUPERTILE_PER_PRIM_H15', 'SC_SUPERTILE_PER_PRIM_H16', - 'SC_SUPERTILE_PER_PRIM_H2', 'SC_SUPERTILE_PER_PRIM_H3', - 'SC_SUPERTILE_PER_PRIM_H4', 'SC_SUPERTILE_PER_PRIM_H5', - 'SC_SUPERTILE_PER_PRIM_H6', 'SC_SUPERTILE_PER_PRIM_H7', - 'SC_SUPERTILE_PER_PRIM_H8', 'SC_SUPERTILE_PER_PRIM_H9', - 'SC_TILE_PER_PRIM_H0', 'SC_TILE_PER_PRIM_H1', - 'SC_TILE_PER_PRIM_H10', 'SC_TILE_PER_PRIM_H11', - 'SC_TILE_PER_PRIM_H12', 'SC_TILE_PER_PRIM_H13', - 'SC_TILE_PER_PRIM_H14', 'SC_TILE_PER_PRIM_H15', - 'SC_TILE_PER_PRIM_H16', 'SC_TILE_PER_PRIM_H2', - 'SC_TILE_PER_PRIM_H3', 'SC_TILE_PER_PRIM_H4', - 'SC_TILE_PER_PRIM_H5', 'SC_TILE_PER_PRIM_H6', - 'SC_TILE_PER_PRIM_H7', 'SC_TILE_PER_PRIM_H8', - 'SC_TILE_PER_PRIM_H9', 'SC_TILE_PER_SUPERTILE_H0', - 'SC_TILE_PER_SUPERTILE_H1', 'SC_TILE_PER_SUPERTILE_H10', - 'SC_TILE_PER_SUPERTILE_H11', 'SC_TILE_PER_SUPERTILE_H12', - 'SC_TILE_PER_SUPERTILE_H13', 'SC_TILE_PER_SUPERTILE_H14', - 'SC_TILE_PER_SUPERTILE_H15', 'SC_TILE_PER_SUPERTILE_H16', - 'SC_TILE_PER_SUPERTILE_H2', 'SC_TILE_PER_SUPERTILE_H3', - 'SC_TILE_PER_SUPERTILE_H4', 'SC_TILE_PER_SUPERTILE_H5', - 'SC_TILE_PER_SUPERTILE_H6', 'SC_TILE_PER_SUPERTILE_H7', - 'SC_TILE_PER_SUPERTILE_H8', 'SC_TILE_PER_SUPERTILE_H9', - 'SC_TILE_PICKED_H1', 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', - 'SC_TILE_PICKED_H4', 'SC_TPQZ_WINDOW_VALID', - 'SC_TPQZ_WINDOW_VALID_BUSY', 'SC_TRPK_WINDOW_VALID', - 'SC_TRPK_WINDOW_VALID_BUSY', 'SDMA_PERF_SEL', - 'SDMA_PERF_SEL_ATCL2_FREE', 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 'SDMA_PERF_SEL_ATCL2_RET_ACK', 'SDMA_PERF_SEL_ATCL2_RET_XNACK', - 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_DST_IDLE', - 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', - 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_STALL', - 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', - 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', - 'SDMA_PERF_SEL_CTX_CHANGE', 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', - 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', - 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GFX_SELECT', - 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', - 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', - 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', - 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', - 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', 'SDMA_PERF_SEL_L1_INV_MIDDLE', - 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_EN', - 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', - 'SDMA_PERF_SEL_L1_WR_INV_EN', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', 'SDMA_PERF_SEL_MC_RD_COUNT', - 'SDMA_PERF_SEL_MC_RD_IDLE', 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', - 'SDMA_PERF_SEL_MC_WR_IDLE', - 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', - 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', - 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', - 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', - 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', - 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', - 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', - 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'SDMA_PERF_SEL_SEM_IDLE', - 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', - 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', - 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', - 'SDMA_PERF_SEL_WR_BA_RTR', 'SEC_GSP0_PRIORITY_HIGH', - 'SEC_GSP0_PRIORITY_LOW', 'SEM_ECC_ERROR', 'SEM_FAILED', - 'SEM_PASSED', 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', - 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', - 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', - 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', - 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', - 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', - 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', - 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', - 'SEM_TRANS_ERROR', 'SET_OVERRIDE_CGTT_DCEFCLK', - 'SET_OVERRIDE_CGTT_SCLK', 'SET_STATIC_SCREEN_SMU_INTR', - 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', - 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', - 'SH_MEM_ALIGNMENT_MODE_DWORD', - 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', - 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', - 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', - 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', - 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', - 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', - 'SM_MODE_RESERVED', 'SO_VGTSTREAMOUT_FLUSH', 'SPDIF1_SOFT_RESET', - 'SPDIF1_SOFT_RESET_0', 'SPDIF1_SOFT_RESET_1', - 'SPDIF_INVERT_DISABLE', 'SPDIF_INVERT_EN', 'SPDIF_INVERT_ENABLE', - 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', - 'SPI_FOG_NONE', 'SPI_PERFCNT_SEL', - 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', - 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', - 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', - 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', - 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', - 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', - 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', - 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', - 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ES_BUSY', - 'SPI_PERF_ES_CRAWLER_STALL', 'SPI_PERF_ES_EVENT_WAVE', - 'SPI_PERF_ES_FIRST_SUBGRP', 'SPI_PERF_ES_FIRST_WAVE', - 'SPI_PERF_ES_GRP_FIFO_FULL', 'SPI_PERF_ES_LAST_SUBGRP', - 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', - 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', - 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', - 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', - 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', - 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', - 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_FIRST_SUBGRP', - 'SPI_PERF_GS_GRP_FIFO_FULL', 'SPI_PERF_GS_LAST_SUBGRP', - 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', - 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', - 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', - 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', - 'SPI_PERF_HS_GRP_FIFO_FULL', 'SPI_PERF_HS_LAST_WAVE', - 'SPI_PERF_HS_LSHS_DEALLOC', 'SPI_PERF_HS_PERS_UPD_FULL0', - 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_WAVE', - 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS0_PC_VALID', - 'SPI_PERF_LDS1_PC_VALID', 'SPI_PERF_LS_BUSY', - 'SPI_PERF_LS_CRAWLER_STALL', 'SPI_PERF_LS_EVENT_WAVE', - 'SPI_PERF_LS_FIRST_WAVE', 'SPI_PERF_LS_GRP_FIFO_FULL', - 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_PERS_UPD_FULL0', - 'SPI_PERF_LS_PERS_UPD_FULL1', 'SPI_PERF_LS_WAVE', - 'SPI_PERF_LS_WINDOW_VALID', 'SPI_PERF_NUM_PS_COL_EXPORTS', - 'SPI_PERF_NUM_VS_PARAM_EXPORTS', 'SPI_PERF_NUM_VS_POS_EXPORTS', - 'SPI_PERF_OFFCHIP_LDS_STALL_LS', 'SPI_PERF_PC_ALLOC_ACCUM', - 'SPI_PERF_PC_ALLOC_CNT', 'SPI_PERF_PIX_ALLOC_DB0_STALL', - 'SPI_PERF_PIX_ALLOC_DB1_STALL', 'SPI_PERF_PIX_ALLOC_DB2_STALL', - 'SPI_PERF_PIX_ALLOC_DB3_STALL', 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 'SPI_PERF_PIX_ALLOC_SCB_STALL', 'SPI_PERF_PS_CTL_ACTIVE', - 'SPI_PERF_PS_CTL_BUSY', 'SPI_PERF_PS_CTL_CNF_BIN2', - 'SPI_PERF_PS_CTL_CNF_BIN3', 'SPI_PERF_PS_CTL_CRAWLER_STALL', - 'SPI_PERF_PS_CTL_DEALLOC_BIN0', 'SPI_PERF_PS_CTL_EVENT_WAVE', - 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', 'SPI_PERF_PS_CTL_FPOS_BIN2', - 'SPI_PERF_PS_CTL_LDS_RES_FULL', 'SPI_PERF_PS_CTL_OPT_WAVE', - 'SPI_PERF_PS_CTL_PASS_BIN0', 'SPI_PERF_PS_CTL_PASS_BIN1', - 'SPI_PERF_PS_CTL_PRIM_BIN0', 'SPI_PERF_PS_CTL_PRIM_BIN1', - 'SPI_PERF_PS_CTL_WAVE', 'SPI_PERF_PS_CTL_WINDOW_VALID', - 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', - 'SPI_PERF_RA_BAR_CU_FULL_CSG', 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 'SPI_PERF_RA_BULKY_CU_FULL_CSN', 'SPI_PERF_RA_CSG_LOCK', - 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_ES_LOCK', - 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', - 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', - 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_LS_LOCK', - 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PS_LOCK_NA', - 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_ES', - 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 'SPI_PERF_RA_REQ_NO_ALLOC_LS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', - 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_ES', - 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', - 'SPI_PERF_RA_RES_STALL_LS', 'SPI_PERF_RA_RES_STALL_PS', - 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', - 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', - 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', - 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', - 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', - 'SPI_PERF_RA_TMP_STALL_ES', 'SPI_PERF_RA_TMP_STALL_GS', - 'SPI_PERF_RA_TMP_STALL_HS', 'SPI_PERF_RA_TMP_STALL_LS', - 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', - 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', - 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', - 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', - 'SPI_PERF_RA_WVLIM_STALL_ES', 'SPI_PERF_RA_WVLIM_STALL_GS', - 'SPI_PERF_RA_WVLIM_STALL_HS', 'SPI_PERF_RA_WVLIM_STALL_LS', - 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', - 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', - 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', - 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', - 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', - 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', - 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_STALL', - 'SPI_PERF_VS_PERS_UPD_FULL0', 'SPI_PERF_VS_PERS_UPD_FULL1', - 'SPI_PERF_VS_POS0_STALL', 'SPI_PERF_VS_POS1_STALL', - 'SPI_PERF_VS_WAVE', 'SPI_PERF_VS_WINDOW_VALID', - 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', - 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', - 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', - 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', - 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', - 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', - 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', - 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', - 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', - 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', - 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', - 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', - 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', - 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', - 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', - 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', - 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', - 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', - 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', - 'SQC_PERF_SEL_DCACHE_HITS', 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', - 'SQC_PERF_SEL_DCACHE_MISSES', - 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', - 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', - 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', - 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', - 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_VOLATILE', 'SQC_PERF_SEL_DCACHE_WB_ASYNC', - 'SQC_PERF_SEL_DCACHE_WB_INST', - 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', - 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', - 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', - 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', - 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', - 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', - 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', - 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', - 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', - 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', - 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', - 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', - 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', - 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', - 'SQC_PERF_SEL_ICACHE_HITS', 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', - 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 'SQC_PERF_SEL_ICACHE_PREFETCH_1', - 'SQC_PERF_SEL_ICACHE_PREFETCH_2', - 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', - 'SQC_PERF_SEL_ICACHE_REQ', - 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', - 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', - 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', - 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', - 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', - 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQIND_GLOBAL_REGS_OFFSET', - 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', - 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', - 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', - 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', - 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', - 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', - 'SQPWRDEC_END', 'SQ_ATTR0', 'SQ_BUFFER_ATOMIC_ADD', - 'SQ_BUFFER_ATOMIC_ADD_X2', 'SQ_BUFFER_ATOMIC_AND', - 'SQ_BUFFER_ATOMIC_AND_X2', 'SQ_BUFFER_ATOMIC_CMPSWAP', - 'SQ_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_BUFFER_ATOMIC_DEC', - 'SQ_BUFFER_ATOMIC_DEC_X2', 'SQ_BUFFER_ATOMIC_INC', - 'SQ_BUFFER_ATOMIC_INC_X2', 'SQ_BUFFER_ATOMIC_OR', - 'SQ_BUFFER_ATOMIC_OR_X2', 'SQ_BUFFER_ATOMIC_SMAX', - 'SQ_BUFFER_ATOMIC_SMAX_X2', 'SQ_BUFFER_ATOMIC_SMIN', - 'SQ_BUFFER_ATOMIC_SMIN_X2', 'SQ_BUFFER_ATOMIC_SUB', - 'SQ_BUFFER_ATOMIC_SUB_X2', 'SQ_BUFFER_ATOMIC_SWAP', - 'SQ_BUFFER_ATOMIC_SWAP_X2', 'SQ_BUFFER_ATOMIC_UMAX', - 'SQ_BUFFER_ATOMIC_UMAX_X2', 'SQ_BUFFER_ATOMIC_UMIN', - 'SQ_BUFFER_ATOMIC_UMIN_X2', 'SQ_BUFFER_ATOMIC_XOR', - 'SQ_BUFFER_ATOMIC_XOR_X2', 'SQ_BUFFER_LOAD_DWORD', - 'SQ_BUFFER_LOAD_DWORDX2', 'SQ_BUFFER_LOAD_DWORDX3', - 'SQ_BUFFER_LOAD_DWORDX4', 'SQ_BUFFER_LOAD_FORMAT_D16_X', - 'SQ_BUFFER_LOAD_FORMAT_D16_XY', 'SQ_BUFFER_LOAD_FORMAT_D16_XYZ', - 'SQ_BUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_BUFFER_LOAD_FORMAT_X', - 'SQ_BUFFER_LOAD_FORMAT_XY', 'SQ_BUFFER_LOAD_FORMAT_XYZ', - 'SQ_BUFFER_LOAD_FORMAT_XYZW', 'SQ_BUFFER_LOAD_SBYTE', - 'SQ_BUFFER_LOAD_SSHORT', 'SQ_BUFFER_LOAD_UBYTE', - 'SQ_BUFFER_LOAD_USHORT', 'SQ_BUFFER_STORE_BYTE', - 'SQ_BUFFER_STORE_DWORD', 'SQ_BUFFER_STORE_DWORDX2', - 'SQ_BUFFER_STORE_DWORDX3', 'SQ_BUFFER_STORE_DWORDX4', - 'SQ_BUFFER_STORE_FORMAT_D16_X', 'SQ_BUFFER_STORE_FORMAT_D16_XY', - 'SQ_BUFFER_STORE_FORMAT_D16_XYZ', - 'SQ_BUFFER_STORE_FORMAT_D16_XYZW', 'SQ_BUFFER_STORE_FORMAT_X', - 'SQ_BUFFER_STORE_FORMAT_XY', 'SQ_BUFFER_STORE_FORMAT_XYZ', - 'SQ_BUFFER_STORE_FORMAT_XYZW', 'SQ_BUFFER_STORE_LDS_DWORD', - 'SQ_BUFFER_STORE_SHORT', 'SQ_BUFFER_WBINVL1', - 'SQ_BUFFER_WBINVL1_VOL', 'SQ_CAC_POWER_ALU_BUSY', - 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', - 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', - 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', - 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', - 'SQ_CHAN_W', 'SQ_CHAN_X', 'SQ_CHAN_Y', 'SQ_CHAN_Z', 'SQ_CNT1', - 'SQ_CNT2', 'SQ_CNT3', 'SQ_CNT4', 'SQ_DISPATCHER_GFX_CNT_PER_RING', - 'SQ_DISPATCHER_GFX_MIN', 'SQ_DPP_BOUND_OFF', 'SQ_DPP_BOUND_ZERO', - 'SQ_DPP_QUAD_PERM', 'SQ_DPP_ROW_BCAST15', 'SQ_DPP_ROW_BCAST31', - 'SQ_DPP_ROW_HALF_MIRROR', 'SQ_DPP_ROW_MIRROR', 'SQ_DPP_ROW_RR1', - 'SQ_DPP_ROW_RR10', 'SQ_DPP_ROW_RR11', 'SQ_DPP_ROW_RR12', - 'SQ_DPP_ROW_RR13', 'SQ_DPP_ROW_RR14', 'SQ_DPP_ROW_RR15', - 'SQ_DPP_ROW_RR2', 'SQ_DPP_ROW_RR3', 'SQ_DPP_ROW_RR4', - 'SQ_DPP_ROW_RR5', 'SQ_DPP_ROW_RR6', 'SQ_DPP_ROW_RR7', - 'SQ_DPP_ROW_RR8', 'SQ_DPP_ROW_RR9', 'SQ_DPP_ROW_SL1', - 'SQ_DPP_ROW_SL10', 'SQ_DPP_ROW_SL11', 'SQ_DPP_ROW_SL12', - 'SQ_DPP_ROW_SL13', 'SQ_DPP_ROW_SL14', 'SQ_DPP_ROW_SL15', - 'SQ_DPP_ROW_SL2', 'SQ_DPP_ROW_SL3', 'SQ_DPP_ROW_SL4', - 'SQ_DPP_ROW_SL5', 'SQ_DPP_ROW_SL6', 'SQ_DPP_ROW_SL7', - 'SQ_DPP_ROW_SL8', 'SQ_DPP_ROW_SL9', 'SQ_DPP_ROW_SR1', - 'SQ_DPP_ROW_SR10', 'SQ_DPP_ROW_SR11', 'SQ_DPP_ROW_SR12', - 'SQ_DPP_ROW_SR13', 'SQ_DPP_ROW_SR14', 'SQ_DPP_ROW_SR15', - 'SQ_DPP_ROW_SR2', 'SQ_DPP_ROW_SR3', 'SQ_DPP_ROW_SR4', - 'SQ_DPP_ROW_SR5', 'SQ_DPP_ROW_SR6', 'SQ_DPP_ROW_SR7', - 'SQ_DPP_ROW_SR8', 'SQ_DPP_ROW_SR9', 'SQ_DPP_WF_RL1', - 'SQ_DPP_WF_RR1', 'SQ_DPP_WF_SL1', 'SQ_DPP_WF_SR1', - 'SQ_DS_ADD_F32', 'SQ_DS_ADD_RTN_F32', 'SQ_DS_ADD_RTN_U32', - 'SQ_DS_ADD_RTN_U64', 'SQ_DS_ADD_SRC2_F32', 'SQ_DS_ADD_SRC2_U32', - 'SQ_DS_ADD_SRC2_U64', 'SQ_DS_ADD_U32', 'SQ_DS_ADD_U64', - 'SQ_DS_AND_B32', 'SQ_DS_AND_B64', 'SQ_DS_AND_RTN_B32', - 'SQ_DS_AND_RTN_B64', 'SQ_DS_AND_SRC2_B32', 'SQ_DS_AND_SRC2_B64', - 'SQ_DS_APPEND', 'SQ_DS_BPERMUTE_B32', 'SQ_DS_CMPST_B32', - 'SQ_DS_CMPST_B64', 'SQ_DS_CMPST_F32', 'SQ_DS_CMPST_F64', - 'SQ_DS_CMPST_RTN_B32', 'SQ_DS_CMPST_RTN_B64', - 'SQ_DS_CMPST_RTN_F32', 'SQ_DS_CMPST_RTN_F64', - 'SQ_DS_CONDXCHG32_RTN_B128', 'SQ_DS_CONDXCHG32_RTN_B64', - 'SQ_DS_CONSUME', 'SQ_DS_DEC_RTN_U32', 'SQ_DS_DEC_RTN_U64', - 'SQ_DS_DEC_SRC2_U32', 'SQ_DS_DEC_SRC2_U64', 'SQ_DS_DEC_U32', - 'SQ_DS_DEC_U64', 'SQ_DS_GWS_BARRIER', 'SQ_DS_GWS_INIT', - 'SQ_DS_GWS_SEMA_BR', 'SQ_DS_GWS_SEMA_P', - 'SQ_DS_GWS_SEMA_RELEASE_ALL', 'SQ_DS_GWS_SEMA_V', - 'SQ_DS_INC_RTN_U32', 'SQ_DS_INC_RTN_U64', 'SQ_DS_INC_SRC2_U32', - 'SQ_DS_INC_SRC2_U64', 'SQ_DS_INC_U32', 'SQ_DS_INC_U64', - 'SQ_DS_MAX_F32', 'SQ_DS_MAX_F64', 'SQ_DS_MAX_I32', - 'SQ_DS_MAX_I64', 'SQ_DS_MAX_RTN_F32', 'SQ_DS_MAX_RTN_F64', - 'SQ_DS_MAX_RTN_I32', 'SQ_DS_MAX_RTN_I64', 'SQ_DS_MAX_RTN_U32', - 'SQ_DS_MAX_RTN_U64', 'SQ_DS_MAX_SRC2_F32', 'SQ_DS_MAX_SRC2_F64', - 'SQ_DS_MAX_SRC2_I32', 'SQ_DS_MAX_SRC2_I64', 'SQ_DS_MAX_SRC2_U32', - 'SQ_DS_MAX_SRC2_U64', 'SQ_DS_MAX_U32', 'SQ_DS_MAX_U64', - 'SQ_DS_MIN_F32', 'SQ_DS_MIN_F64', 'SQ_DS_MIN_I32', - 'SQ_DS_MIN_I64', 'SQ_DS_MIN_RTN_F32', 'SQ_DS_MIN_RTN_F64', - 'SQ_DS_MIN_RTN_I32', 'SQ_DS_MIN_RTN_I64', 'SQ_DS_MIN_RTN_U32', - 'SQ_DS_MIN_RTN_U64', 'SQ_DS_MIN_SRC2_F32', 'SQ_DS_MIN_SRC2_F64', - 'SQ_DS_MIN_SRC2_I32', 'SQ_DS_MIN_SRC2_I64', 'SQ_DS_MIN_SRC2_U32', - 'SQ_DS_MIN_SRC2_U64', 'SQ_DS_MIN_U32', 'SQ_DS_MIN_U64', - 'SQ_DS_MSKOR_B32', 'SQ_DS_MSKOR_B64', 'SQ_DS_MSKOR_RTN_B32', - 'SQ_DS_MSKOR_RTN_B64', 'SQ_DS_NOP', 'SQ_DS_ORDERED_COUNT', - 'SQ_DS_OR_B32', 'SQ_DS_OR_B64', 'SQ_DS_OR_RTN_B32', - 'SQ_DS_OR_RTN_B64', 'SQ_DS_OR_SRC2_B32', 'SQ_DS_OR_SRC2_B64', - 'SQ_DS_PERMUTE_B32', 'SQ_DS_READ2ST64_B32', 'SQ_DS_READ2ST64_B64', - 'SQ_DS_READ2_B32', 'SQ_DS_READ2_B64', 'SQ_DS_READ_ADDTID_B32', - 'SQ_DS_READ_B128', 'SQ_DS_READ_B32', 'SQ_DS_READ_B64', - 'SQ_DS_READ_B96', 'SQ_DS_READ_I16', 'SQ_DS_READ_I8', - 'SQ_DS_READ_U16', 'SQ_DS_READ_U8', 'SQ_DS_RSUB_RTN_U32', - 'SQ_DS_RSUB_RTN_U64', 'SQ_DS_RSUB_SRC2_U32', - 'SQ_DS_RSUB_SRC2_U64', 'SQ_DS_RSUB_U32', 'SQ_DS_RSUB_U64', - 'SQ_DS_SUB_RTN_U32', 'SQ_DS_SUB_RTN_U64', 'SQ_DS_SUB_SRC2_U32', - 'SQ_DS_SUB_SRC2_U64', 'SQ_DS_SUB_U32', 'SQ_DS_SUB_U64', - 'SQ_DS_SWIZZLE_B32', 'SQ_DS_WRAP_RTN_B32', 'SQ_DS_WRITE2ST64_B32', - 'SQ_DS_WRITE2ST64_B64', 'SQ_DS_WRITE2_B32', 'SQ_DS_WRITE2_B64', - 'SQ_DS_WRITE_ADDTID_B32', 'SQ_DS_WRITE_B128', 'SQ_DS_WRITE_B16', - 'SQ_DS_WRITE_B32', 'SQ_DS_WRITE_B64', 'SQ_DS_WRITE_B8', - 'SQ_DS_WRITE_B96', 'SQ_DS_WRITE_SRC2_B32', 'SQ_DS_WRITE_SRC2_B64', - 'SQ_DS_WRXCHG2ST64_RTN_B32', 'SQ_DS_WRXCHG2ST64_RTN_B64', - 'SQ_DS_WRXCHG2_RTN_B32', 'SQ_DS_WRXCHG2_RTN_B64', - 'SQ_DS_WRXCHG_RTN_B32', 'SQ_DS_WRXCHG_RTN_B64', 'SQ_DS_XOR_B32', - 'SQ_DS_XOR_B64', 'SQ_DS_XOR_RTN_B32', 'SQ_DS_XOR_RTN_B64', - 'SQ_DS_XOR_SRC2_B32', 'SQ_DS_XOR_SRC2_B64', 'SQ_EDC_FUE_CNTL_LDS', - 'SQ_EDC_FUE_CNTL_SIMD0', 'SQ_EDC_FUE_CNTL_SIMD1', - 'SQ_EDC_FUE_CNTL_SIMD2', 'SQ_EDC_FUE_CNTL_SIMD3', - 'SQ_EDC_FUE_CNTL_SQ', 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', - 'SQ_EDC_FUE_CNTL_TD', 'SQ_EDC_INFO_SOURCE', - 'SQ_EDC_INFO_SOURCE_GDS', 'SQ_EDC_INFO_SOURCE_INST', - 'SQ_EDC_INFO_SOURCE_INVALID', 'SQ_EDC_INFO_SOURCE_LDS', - 'SQ_EDC_INFO_SOURCE_SGPR', 'SQ_EDC_INFO_SOURCE_TA', - 'SQ_EDC_INFO_SOURCE_VGPR', 'SQ_ENC_DS_BITS', 'SQ_ENC_DS_FIELD', - 'SQ_ENC_DS_MASK', 'SQ_ENC_EXP_BITS', 'SQ_ENC_EXP_FIELD', - 'SQ_ENC_EXP_MASK', 'SQ_ENC_FLAT_BITS', 'SQ_ENC_FLAT_FIELD', - 'SQ_ENC_FLAT_MASK', 'SQ_ENC_MIMG_BITS', 'SQ_ENC_MIMG_FIELD', - 'SQ_ENC_MIMG_MASK', 'SQ_ENC_MTBUF_BITS', 'SQ_ENC_MTBUF_FIELD', - 'SQ_ENC_MTBUF_MASK', 'SQ_ENC_MUBUF_BITS', 'SQ_ENC_MUBUF_FIELD', - 'SQ_ENC_MUBUF_MASK', 'SQ_ENC_SMEM_BITS', 'SQ_ENC_SMEM_FIELD', - 'SQ_ENC_SMEM_MASK', 'SQ_ENC_SOP1_BITS', 'SQ_ENC_SOP1_FIELD', - 'SQ_ENC_SOP1_MASK', 'SQ_ENC_SOP2_BITS', 'SQ_ENC_SOP2_FIELD', - 'SQ_ENC_SOP2_MASK', 'SQ_ENC_SOPC_BITS', 'SQ_ENC_SOPC_FIELD', - 'SQ_ENC_SOPC_MASK', 'SQ_ENC_SOPK_BITS', 'SQ_ENC_SOPK_FIELD', - 'SQ_ENC_SOPK_MASK', 'SQ_ENC_SOPP_BITS', 'SQ_ENC_SOPP_FIELD', - 'SQ_ENC_SOPP_MASK', 'SQ_ENC_VINTRP_BITS', 'SQ_ENC_VINTRP_FIELD', - 'SQ_ENC_VINTRP_MASK', 'SQ_ENC_VOP1_BITS', 'SQ_ENC_VOP1_FIELD', - 'SQ_ENC_VOP1_MASK', 'SQ_ENC_VOP2_BITS', 'SQ_ENC_VOP2_FIELD', - 'SQ_ENC_VOP2_MASK', 'SQ_ENC_VOP3P_BITS', 'SQ_ENC_VOP3P_FIELD', - 'SQ_ENC_VOP3P_MASK', 'SQ_ENC_VOP3_BITS', 'SQ_ENC_VOP3_FIELD', - 'SQ_ENC_VOP3_MASK', 'SQ_ENC_VOPC_BITS', 'SQ_ENC_VOPC_FIELD', - 'SQ_ENC_VOPC_MASK', 'SQ_EQ', 'SQ_EXEC_HI', 'SQ_EXEC_LO', 'SQ_EXP', - 'SQ_EXPORT_RAT_INST_ADD', 'SQ_EXPORT_RAT_INST_ADD_RTN', - 'SQ_EXPORT_RAT_INST_AND', 'SQ_EXPORT_RAT_INST_AND_RTN', - 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', - 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', - 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', - 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', - 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', - 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', - 'SQ_EXPORT_RAT_INST_DEC_UINT', 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', - 'SQ_EXPORT_RAT_INST_INC_UINT', 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', - 'SQ_EXPORT_RAT_INST_MAX_INT', 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', - 'SQ_EXPORT_RAT_INST_MAX_UINT', 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', - 'SQ_EXPORT_RAT_INST_MIN_INT', 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', - 'SQ_EXPORT_RAT_INST_MIN_UINT', 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', - 'SQ_EXPORT_RAT_INST_MSKOR', 'SQ_EXPORT_RAT_INST_MSKOR_RTN', - 'SQ_EXPORT_RAT_INST_NOP', 'SQ_EXPORT_RAT_INST_NOP_RTN', - 'SQ_EXPORT_RAT_INST_OR', 'SQ_EXPORT_RAT_INST_OR_RTN', - 'SQ_EXPORT_RAT_INST_RSUB', 'SQ_EXPORT_RAT_INST_RSUB_RTN', - 'SQ_EXPORT_RAT_INST_STORE_BYTE', 'SQ_EXPORT_RAT_INST_STORE_DWORD', - 'SQ_EXPORT_RAT_INST_STORE_RAW', - 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', - 'SQ_EXPORT_RAT_INST_STORE_SHORT', - 'SQ_EXPORT_RAT_INST_STORE_TYPED', 'SQ_EXPORT_RAT_INST_SUB', - 'SQ_EXPORT_RAT_INST_SUB_RTN', - 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', - 'SQ_EXPORT_RAT_INST_XCHG_RTN', 'SQ_EXPORT_RAT_INST_XOR', - 'SQ_EXPORT_RAT_INST_XOR_RTN', 'SQ_EXP_GDS0', 'SQ_EXP_MRT0', - 'SQ_EXP_MRTZ', 'SQ_EXP_NULL', 'SQ_EXP_NUM_GDS', 'SQ_EXP_NUM_MRT', - 'SQ_EXP_NUM_PARAM', 'SQ_EXP_NUM_POS', 'SQ_EXP_PARAM0', - 'SQ_EXP_POS0', 'SQ_EX_MODE_EXCP_ADDR_WATCH0', - 'SQ_EX_MODE_EXCP_DIV0', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', - 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', - 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', - 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', - 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', 'SQ_F', - 'SQ_FLAT', 'SQ_FLAT_ATOMIC_ADD', 'SQ_FLAT_ATOMIC_ADD_X2', - 'SQ_FLAT_ATOMIC_AND', 'SQ_FLAT_ATOMIC_AND_X2', - 'SQ_FLAT_ATOMIC_CMPSWAP', 'SQ_FLAT_ATOMIC_CMPSWAP_X2', - 'SQ_FLAT_ATOMIC_DEC', 'SQ_FLAT_ATOMIC_DEC_X2', - 'SQ_FLAT_ATOMIC_INC', 'SQ_FLAT_ATOMIC_INC_X2', - 'SQ_FLAT_ATOMIC_OR', 'SQ_FLAT_ATOMIC_OR_X2', - 'SQ_FLAT_ATOMIC_SMAX', 'SQ_FLAT_ATOMIC_SMAX_X2', - 'SQ_FLAT_ATOMIC_SMIN', 'SQ_FLAT_ATOMIC_SMIN_X2', - 'SQ_FLAT_ATOMIC_SUB', 'SQ_FLAT_ATOMIC_SUB_X2', - 'SQ_FLAT_ATOMIC_SWAP', 'SQ_FLAT_ATOMIC_SWAP_X2', - 'SQ_FLAT_ATOMIC_UMAX', 'SQ_FLAT_ATOMIC_UMAX_X2', - 'SQ_FLAT_ATOMIC_UMIN', 'SQ_FLAT_ATOMIC_UMIN_X2', - 'SQ_FLAT_ATOMIC_XOR', 'SQ_FLAT_ATOMIC_XOR_X2', - 'SQ_FLAT_LOAD_DWORD', 'SQ_FLAT_LOAD_DWORDX2', - 'SQ_FLAT_LOAD_DWORDX3', 'SQ_FLAT_LOAD_DWORDX4', - 'SQ_FLAT_LOAD_SBYTE', 'SQ_FLAT_LOAD_SSHORT', 'SQ_FLAT_LOAD_UBYTE', - 'SQ_FLAT_LOAD_USHORT', 'SQ_FLAT_SCRATCH_HI', 'SQ_FLAT_SCRATCH_LO', - 'SQ_FLAT_STORE_BYTE', 'SQ_FLAT_STORE_DWORD', - 'SQ_FLAT_STORE_DWORDX2', 'SQ_FLAT_STORE_DWORDX3', - 'SQ_FLAT_STORE_DWORDX4', 'SQ_FLAT_STORE_SHORT', 'SQ_GE', - 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', - 'SQ_GLOBAL', 'SQ_GLOBAL_ATOMIC_ADD', 'SQ_GLOBAL_ATOMIC_ADD_X2', - 'SQ_GLOBAL_ATOMIC_AND', 'SQ_GLOBAL_ATOMIC_AND_X2', - 'SQ_GLOBAL_ATOMIC_CMPSWAP', 'SQ_GLOBAL_ATOMIC_CMPSWAP_X2', - 'SQ_GLOBAL_ATOMIC_DEC', 'SQ_GLOBAL_ATOMIC_DEC_X2', - 'SQ_GLOBAL_ATOMIC_INC', 'SQ_GLOBAL_ATOMIC_INC_X2', - 'SQ_GLOBAL_ATOMIC_OR', 'SQ_GLOBAL_ATOMIC_OR_X2', - 'SQ_GLOBAL_ATOMIC_SMAX', 'SQ_GLOBAL_ATOMIC_SMAX_X2', - 'SQ_GLOBAL_ATOMIC_SMIN', 'SQ_GLOBAL_ATOMIC_SMIN_X2', - 'SQ_GLOBAL_ATOMIC_SUB', 'SQ_GLOBAL_ATOMIC_SUB_X2', - 'SQ_GLOBAL_ATOMIC_SWAP', 'SQ_GLOBAL_ATOMIC_SWAP_X2', - 'SQ_GLOBAL_ATOMIC_UMAX', 'SQ_GLOBAL_ATOMIC_UMAX_X2', - 'SQ_GLOBAL_ATOMIC_UMIN', 'SQ_GLOBAL_ATOMIC_UMIN_X2', - 'SQ_GLOBAL_ATOMIC_XOR', 'SQ_GLOBAL_ATOMIC_XOR_X2', - 'SQ_GLOBAL_LOAD_DWORD', 'SQ_GLOBAL_LOAD_DWORDX2', - 'SQ_GLOBAL_LOAD_DWORDX3', 'SQ_GLOBAL_LOAD_DWORDX4', - 'SQ_GLOBAL_LOAD_SBYTE', 'SQ_GLOBAL_LOAD_SSHORT', - 'SQ_GLOBAL_LOAD_UBYTE', 'SQ_GLOBAL_LOAD_USHORT', - 'SQ_GLOBAL_STORE_BYTE', 'SQ_GLOBAL_STORE_DWORD', - 'SQ_GLOBAL_STORE_DWORDX2', 'SQ_GLOBAL_STORE_DWORDX3', - 'SQ_GLOBAL_STORE_DWORDX4', 'SQ_GLOBAL_STORE_SHORT', - 'SQ_GS_OP_CUT', 'SQ_GS_OP_EMIT', 'SQ_GS_OP_EMIT_CUT', - 'SQ_GS_OP_NOP', 'SQ_GT', 'SQ_HWREG_ID_SHIFT', 'SQ_HWREG_ID_SIZE', - 'SQ_HWREG_OFFSET_SHIFT', 'SQ_HWREG_OFFSET_SIZE', - 'SQ_HWREG_SIZE_SHIFT', 'SQ_HWREG_SIZE_SIZE', 'SQ_HW_REG_FLUSH_IB', - 'SQ_HW_REG_GPR_ALLOC', 'SQ_HW_REG_HW_ID', 'SQ_HW_REG_IB_DBG0', - 'SQ_HW_REG_IB_DBG1', 'SQ_HW_REG_IB_STS', 'SQ_HW_REG_INST_DW0', - 'SQ_HW_REG_INST_DW1', 'SQ_HW_REG_LDS_ALLOC', 'SQ_HW_REG_MODE', - 'SQ_HW_REG_PC_HI', 'SQ_HW_REG_PC_LO', 'SQ_HW_REG_SH_MEM_BASES', - 'SQ_HW_REG_SQ_SHADER_TBA_HI', 'SQ_HW_REG_SQ_SHADER_TBA_LO', - 'SQ_HW_REG_SQ_SHADER_TMA_HI', 'SQ_HW_REG_SQ_SHADER_TMA_LO', - 'SQ_HW_REG_STATUS', 'SQ_HW_REG_TRAPSTS', 'SQ_IBUF_IB_DRET', - 'SQ_IBUF_IB_EMPTY_WAIT_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_GNT', - 'SQ_IBUF_IB_IDLE', 'SQ_IBUF_IB_INI_WAIT_DRET', - 'SQ_IBUF_IB_INI_WAIT_GNT', 'SQ_IBUF_IB_LE_4DW', - 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', 'SQ_IMAGE_ATOMIC_ADD', - 'SQ_IMAGE_ATOMIC_AND', 'SQ_IMAGE_ATOMIC_CMPSWAP', - 'SQ_IMAGE_ATOMIC_DEC', 'SQ_IMAGE_ATOMIC_INC', - 'SQ_IMAGE_ATOMIC_OR', 'SQ_IMAGE_ATOMIC_SMAX', - 'SQ_IMAGE_ATOMIC_SMIN', 'SQ_IMAGE_ATOMIC_SUB', - 'SQ_IMAGE_ATOMIC_SWAP', 'SQ_IMAGE_ATOMIC_UMAX', - 'SQ_IMAGE_ATOMIC_UMIN', 'SQ_IMAGE_ATOMIC_XOR', 'SQ_IMAGE_GATHER4', - 'SQ_IMAGE_GATHER4H', 'SQ_IMAGE_GATHER4H_PCK', - 'SQ_IMAGE_GATHER4_B', 'SQ_IMAGE_GATHER4_B_CL', - 'SQ_IMAGE_GATHER4_B_CL_O', 'SQ_IMAGE_GATHER4_B_O', - 'SQ_IMAGE_GATHER4_C', 'SQ_IMAGE_GATHER4_CL', - 'SQ_IMAGE_GATHER4_CL_O', 'SQ_IMAGE_GATHER4_C_B', - 'SQ_IMAGE_GATHER4_C_B_CL', 'SQ_IMAGE_GATHER4_C_B_CL_O', - 'SQ_IMAGE_GATHER4_C_B_O', 'SQ_IMAGE_GATHER4_C_CL', - 'SQ_IMAGE_GATHER4_C_CL_O', 'SQ_IMAGE_GATHER4_C_L', - 'SQ_IMAGE_GATHER4_C_LZ', 'SQ_IMAGE_GATHER4_C_LZ_O', - 'SQ_IMAGE_GATHER4_C_L_O', 'SQ_IMAGE_GATHER4_C_O', - 'SQ_IMAGE_GATHER4_L', 'SQ_IMAGE_GATHER4_LZ', - 'SQ_IMAGE_GATHER4_LZ_O', 'SQ_IMAGE_GATHER4_L_O', - 'SQ_IMAGE_GATHER4_O', 'SQ_IMAGE_GATHER8H_PCK', 'SQ_IMAGE_GET_LOD', - 'SQ_IMAGE_GET_RESINFO', 'SQ_IMAGE_LOAD', 'SQ_IMAGE_LOAD_MIP', - 'SQ_IMAGE_LOAD_MIP_PCK', 'SQ_IMAGE_LOAD_MIP_PCK_SGN', - 'SQ_IMAGE_LOAD_PCK', 'SQ_IMAGE_LOAD_PCK_SGN', 'SQ_IMAGE_RSRC256', - 'SQ_IMAGE_SAMPLE', 'SQ_IMAGE_SAMPLER', 'SQ_IMAGE_SAMPLE_B', - 'SQ_IMAGE_SAMPLE_B_CL', 'SQ_IMAGE_SAMPLE_B_CL_O', - 'SQ_IMAGE_SAMPLE_B_O', 'SQ_IMAGE_SAMPLE_C', 'SQ_IMAGE_SAMPLE_CD', - 'SQ_IMAGE_SAMPLE_CD_CL', 'SQ_IMAGE_SAMPLE_CD_CL_O', - 'SQ_IMAGE_SAMPLE_CD_O', 'SQ_IMAGE_SAMPLE_CL', - 'SQ_IMAGE_SAMPLE_CL_O', 'SQ_IMAGE_SAMPLE_C_B', - 'SQ_IMAGE_SAMPLE_C_B_CL', 'SQ_IMAGE_SAMPLE_C_B_CL_O', - 'SQ_IMAGE_SAMPLE_C_B_O', 'SQ_IMAGE_SAMPLE_C_CD', - 'SQ_IMAGE_SAMPLE_C_CD_CL', 'SQ_IMAGE_SAMPLE_C_CD_CL_O', - 'SQ_IMAGE_SAMPLE_C_CD_O', 'SQ_IMAGE_SAMPLE_C_CL', - 'SQ_IMAGE_SAMPLE_C_CL_O', 'SQ_IMAGE_SAMPLE_C_D', - 'SQ_IMAGE_SAMPLE_C_D_CL', 'SQ_IMAGE_SAMPLE_C_D_CL_O', - 'SQ_IMAGE_SAMPLE_C_D_O', 'SQ_IMAGE_SAMPLE_C_L', - 'SQ_IMAGE_SAMPLE_C_LZ', 'SQ_IMAGE_SAMPLE_C_LZ_O', - 'SQ_IMAGE_SAMPLE_C_L_O', 'SQ_IMAGE_SAMPLE_C_O', - 'SQ_IMAGE_SAMPLE_D', 'SQ_IMAGE_SAMPLE_D_CL', - 'SQ_IMAGE_SAMPLE_D_CL_O', 'SQ_IMAGE_SAMPLE_D_O', - 'SQ_IMAGE_SAMPLE_L', 'SQ_IMAGE_SAMPLE_LZ', 'SQ_IMAGE_SAMPLE_LZ_O', - 'SQ_IMAGE_SAMPLE_L_O', 'SQ_IMAGE_SAMPLE_O', 'SQ_IMAGE_STORE', - 'SQ_IMAGE_STORE_MIP', 'SQ_IMAGE_STORE_MIP_PCK', - 'SQ_IMAGE_STORE_PCK', 'SQ_IMG_FILTER_MODE_BLEND', - 'SQ_IMG_FILTER_MODE_MAX', 'SQ_IMG_FILTER_MODE_MIN', - 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', 'SQ_IND_CMD_CMD_DEBUG', - 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', - 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', - 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', - 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', - 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', - 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', - 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', - 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', - 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', - 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', - 'SQ_INTERRUPT_WORD_ENCODING_ERROR', - 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_L1', 'SQ_L10', 'SQ_L11', - 'SQ_L12', 'SQ_L13', 'SQ_L14', 'SQ_L15', 'SQ_L2', 'SQ_L3', 'SQ_L4', - 'SQ_L5', 'SQ_L6', 'SQ_L7', 'SQ_L8', 'SQ_L9', - 'SQ_LB_CTR_SEL_ALU_CYCLES', 'SQ_LB_CTR_SEL_ALU_STALLS', - 'SQ_LB_CTR_SEL_DCACHE_STALLS', 'SQ_LB_CTR_SEL_ICACHE_STALLS', - 'SQ_LB_CTR_SEL_RESERVED0', 'SQ_LB_CTR_SEL_RESERVED1', - 'SQ_LB_CTR_SEL_RESERVED2', 'SQ_LB_CTR_SEL_RESERVED3', - 'SQ_LB_CTR_SEL_RESERVED4', 'SQ_LB_CTR_SEL_RESERVED5', - 'SQ_LB_CTR_SEL_RESERVED6', 'SQ_LB_CTR_SEL_SALU_CYCLES', - 'SQ_LB_CTR_SEL_SCALAR_STALLS', 'SQ_LB_CTR_SEL_SMEM_CYCLES', - 'SQ_LB_CTR_SEL_TEX_CYCLES', 'SQ_LB_CTR_SEL_TEX_STALLS', - 'SQ_LB_CTR_SEL_VALUES', 'SQ_LE', 'SQ_LG', 'SQ_LT', 'SQ_M0', - 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', - 'SQ_MSG_EARLY_PRIM_DEALLOC', 'SQ_MSG_GS', 'SQ_MSG_GS_ALLOC_REQ', - 'SQ_MSG_GS_DONE', 'SQ_MSG_HALT_WAVES', 'SQ_MSG_INTERRUPT', - 'SQ_MSG_ORDERED_PS_DONE', 'SQ_MSG_SAVEWAVE', - 'SQ_MSG_STALL_WAVE_GEN', 'SQ_MSG_SYSMSG', 'SQ_NE', 'SQ_NEQ', - 'SQ_NGE', 'SQ_NGT', 'SQ_NLE', 'SQ_NLG', 'SQ_NLT', 'SQ_NON_EVENT', - 'SQ_NUM_ATTR', 'SQ_NUM_SGPR', 'SQ_NUM_TTMP', 'SQ_NUM_VGPR', - 'SQ_O', 'SQ_OMOD_D2', 'SQ_OMOD_M2', 'SQ_OMOD_M4', 'SQ_OMOD_OFF', - 'SQ_PARAM_P0', 'SQ_PARAM_P10', 'SQ_PARAM_P20', 'SQ_PERF_SEL', - 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_ACCUM_PREV_HIRES', - 'SQ_PERF_SEL_ACTIVE_INST_ANY', 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', - 'SQ_PERF_SEL_ACTIVE_INST_FLAT', 'SQ_PERF_SEL_ACTIVE_INST_LDS', - 'SQ_PERF_SEL_ACTIVE_INST_MISC', 'SQ_PERF_SEL_ACTIVE_INST_SCA', - 'SQ_PERF_SEL_ACTIVE_INST_VALU', 'SQ_PERF_SEL_ACTIVE_INST_VMEM', - 'SQ_PERF_SEL_ATC_INSTS_SMEM', 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', - 'SQ_PERF_SEL_ATC_INSTS_VMEM', 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', - 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', - 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', 'SQ_PERF_SEL_ATC_XNACK_ALL', - 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', 'SQ_PERF_SEL_ATC_XNACK_FIRST', - 'SQ_PERF_SEL_BUSY_CU_CYCLES', 'SQ_PERF_SEL_BUSY_CYCLES', - 'SQ_PERF_SEL_CBRANCH_FORK', 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', - 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', - 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', - 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', 'SQ_PERF_SEL_IFETCH', - 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_XNACK', - 'SQ_PERF_SEL_INSTS', 'SQ_PERF_SEL_INSTS_BRANCH', - 'SQ_PERF_SEL_INSTS_EXP', 'SQ_PERF_SEL_INSTS_EXP_GDS', - 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', - 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', - 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', - 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', - 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VALU', - 'SQ_PERF_SEL_INSTS_VMEM', 'SQ_PERF_SEL_INSTS_VMEM_RD', - 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', - 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VMEM_WR', - 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', 'SQ_PERF_SEL_INSTS_VSKIPPED', - 'SQ_PERF_SEL_INST_CYCLES_EXP', 'SQ_PERF_SEL_INST_CYCLES_GDS', - 'SQ_PERF_SEL_INST_CYCLES_SALU', 'SQ_PERF_SEL_INST_CYCLES_SMEM', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', 'SQ_PERF_SEL_INST_LEVEL_EXP', - 'SQ_PERF_SEL_INST_LEVEL_GDS', 'SQ_PERF_SEL_INST_LEVEL_LDS', - 'SQ_PERF_SEL_INST_LEVEL_SMEM', 'SQ_PERF_SEL_INST_LEVEL_VMEM', - 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', - 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', 'SQ_PERF_SEL_LDS_BANK_CONFLICT', - 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', - 'SQ_PERF_SEL_LDS_IDX_ACTIVE', 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', - 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', - 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', 'SQ_PERF_SEL_LEVEL_WAVES', - 'SQ_PERF_SEL_LEVEL_WAVES_CU', 'SQ_PERF_SEL_MSG_CNTR', - 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', - 'SQ_PERF_SEL_MSG_PERF', 'SQ_PERF_SEL_NONE', - 'SQ_PERF_SEL_POWER_ALU_BUSY', 'SQ_PERF_SEL_POWER_GPR_RD', - 'SQ_PERF_SEL_POWER_GPR_WR', 'SQ_PERF_SEL_POWER_LDS_BUSY', - 'SQ_PERF_SEL_POWER_TEX_BUSY', 'SQ_PERF_SEL_POWER_VALU', - 'SQ_PERF_SEL_POWER_VALU0', 'SQ_PERF_SEL_POWER_VALU1', - 'SQ_PERF_SEL_POWER_VALU2', 'SQ_PERF_SEL_PT_POWER_STALL', - 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_SRC_CD_BUSY', - 'SQ_PERF_SEL_SURF_SYNCS', 'SQ_PERF_SEL_THREAD_CYCLES_VALU', - 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', 'SQ_PERF_SEL_TLB_SHOOTDOWN', - 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', - 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', 'SQ_PERF_SEL_TTRACE_REQS', - 'SQ_PERF_SEL_TTRACE_STALL', 'SQ_PERF_SEL_USER0', - 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', - 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', - 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', - 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', - 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', - 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', - 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', - 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', - 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', - 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', - 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', - 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', - 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', - 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', - 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', 'SQ_PERF_SEL_UTCL1_REQUEST', - 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', - 'SQ_PERF_SEL_VALU_DEP_STALL', 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', - 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', - 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', 'SQ_PERF_SEL_VALU_STARVE', - 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', - 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', - 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', - 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', 'SQ_PERF_SEL_WAIT_ANY', - 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', - 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 'SQ_PERF_SEL_WAIT_CNT_VM', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', - 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', - 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_MISC', - 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_VALU', - 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', - 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', - 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVES', - 'SQ_PERF_SEL_WAVES_CU', 'SQ_PERF_SEL_WAVES_EQ_64', - 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', - 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', - 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', - 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', 'SQ_R1', - 'SQ_R10', 'SQ_R11', 'SQ_R12', 'SQ_R13', 'SQ_R14', 'SQ_R15', - 'SQ_R2', 'SQ_R3', 'SQ_R4', 'SQ_R5', 'SQ_R6', 'SQ_R7', 'SQ_R8', - 'SQ_R9', 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', - 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', - 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', - 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', - 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', - 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', - 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', - 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', - 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', - 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', - 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', - 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', - 'SQ_SCRATCH_LOAD_DWORD', 'SQ_SCRATCH_LOAD_DWORDX2', - 'SQ_SCRATCH_LOAD_DWORDX3', 'SQ_SCRATCH_LOAD_DWORDX4', - 'SQ_SCRATCH_LOAD_SBYTE', 'SQ_SCRATCH_LOAD_SSHORT', - 'SQ_SCRATCH_LOAD_UBYTE', 'SQ_SCRATCH_LOAD_USHORT', - 'SQ_SCRATCH_STORE_BYTE', 'SQ_SCRATCH_STORE_DWORD', - 'SQ_SCRATCH_STORE_DWORDX2', 'SQ_SCRATCH_STORE_DWORDX3', - 'SQ_SCRATCH_STORE_DWORDX4', 'SQ_SCRATCH_STORE_SHORT', - 'SQ_SDWA_BYTE_0', 'SQ_SDWA_BYTE_1', 'SQ_SDWA_BYTE_2', - 'SQ_SDWA_BYTE_3', 'SQ_SDWA_DWORD', 'SQ_SDWA_UNUSED_PAD', - 'SQ_SDWA_UNUSED_PRESERVE', 'SQ_SDWA_UNUSED_SEXT', - 'SQ_SDWA_WORD_0', 'SQ_SDWA_WORD_1', 'SQ_SEL_0', 'SQ_SEL_1', - 'SQ_SEL_RESERVED_0', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', - 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_SENDMSG_GSOP_SHIFT', - 'SQ_SENDMSG_GSOP_SIZE', 'SQ_SENDMSG_MSG_SHIFT', - 'SQ_SENDMSG_MSG_SIZE', 'SQ_SENDMSG_STREAMID_SHIFT', - 'SQ_SENDMSG_STREAMID_SIZE', 'SQ_SENDMSG_SYSTEM_SHIFT', - 'SQ_SENDMSG_SYSTEM_SIZE', 'SQ_SGPR0', 'SQ_SRC_0', 'SQ_SRC_0_5', - 'SQ_SRC_1', 'SQ_SRC_10_INT', 'SQ_SRC_11_INT', 'SQ_SRC_12_INT', - 'SQ_SRC_13_INT', 'SQ_SRC_14_INT', 'SQ_SRC_15_INT', - 'SQ_SRC_16_INT', 'SQ_SRC_17_INT', 'SQ_SRC_18_INT', - 'SQ_SRC_19_INT', 'SQ_SRC_1_INT', 'SQ_SRC_2', 'SQ_SRC_20_INT', - 'SQ_SRC_21_INT', 'SQ_SRC_22_INT', 'SQ_SRC_23_INT', - 'SQ_SRC_24_INT', 'SQ_SRC_25_INT', 'SQ_SRC_26_INT', - 'SQ_SRC_27_INT', 'SQ_SRC_28_INT', 'SQ_SRC_29_INT', 'SQ_SRC_2_INT', - 'SQ_SRC_30_INT', 'SQ_SRC_31_INT', 'SQ_SRC_32_INT', - 'SQ_SRC_33_INT', 'SQ_SRC_34_INT', 'SQ_SRC_35_INT', - 'SQ_SRC_36_INT', 'SQ_SRC_37_INT', 'SQ_SRC_38_INT', - 'SQ_SRC_39_INT', 'SQ_SRC_3_INT', 'SQ_SRC_4', 'SQ_SRC_40_INT', - 'SQ_SRC_41_INT', 'SQ_SRC_42_INT', 'SQ_SRC_43_INT', - 'SQ_SRC_44_INT', 'SQ_SRC_45_INT', 'SQ_SRC_46_INT', - 'SQ_SRC_47_INT', 'SQ_SRC_48_INT', 'SQ_SRC_49_INT', 'SQ_SRC_4_INT', - 'SQ_SRC_50_INT', 'SQ_SRC_51_INT', 'SQ_SRC_52_INT', - 'SQ_SRC_53_INT', 'SQ_SRC_54_INT', 'SQ_SRC_55_INT', - 'SQ_SRC_56_INT', 'SQ_SRC_57_INT', 'SQ_SRC_58_INT', - 'SQ_SRC_59_INT', 'SQ_SRC_5_INT', 'SQ_SRC_60_INT', 'SQ_SRC_61_INT', - 'SQ_SRC_62_INT', 'SQ_SRC_63_INT', 'SQ_SRC_64_INT', 'SQ_SRC_6_INT', - 'SQ_SRC_7_INT', 'SQ_SRC_8_INT', 'SQ_SRC_9_INT', 'SQ_SRC_DPP', - 'SQ_SRC_EXECZ', 'SQ_SRC_INV_2PI', 'SQ_SRC_LDS_DIRECT', - 'SQ_SRC_LITERAL', 'SQ_SRC_M_0_5', 'SQ_SRC_M_1', 'SQ_SRC_M_10_INT', - 'SQ_SRC_M_11_INT', 'SQ_SRC_M_12_INT', 'SQ_SRC_M_13_INT', - 'SQ_SRC_M_14_INT', 'SQ_SRC_M_15_INT', 'SQ_SRC_M_16_INT', - 'SQ_SRC_M_1_INT', 'SQ_SRC_M_2', 'SQ_SRC_M_2_INT', - 'SQ_SRC_M_3_INT', 'SQ_SRC_M_4', 'SQ_SRC_M_4_INT', - 'SQ_SRC_M_5_INT', 'SQ_SRC_M_6_INT', 'SQ_SRC_M_7_INT', - 'SQ_SRC_M_8_INT', 'SQ_SRC_M_9_INT', 'SQ_SRC_POPS_EXITING_WAVE_ID', - 'SQ_SRC_PRIVATE_BASE', 'SQ_SRC_PRIVATE_LIMIT', 'SQ_SRC_SCC', - 'SQ_SRC_SDWA', 'SQ_SRC_SHARED_BASE', 'SQ_SRC_SHARED_LIMIT', - 'SQ_SRC_VCCZ', 'SQ_SRC_VGPR0', 'SQ_SRC_VGPR_BIT', - 'SQ_SYSMSG_OP_ECC_ERR_INTERRUPT', 'SQ_SYSMSG_OP_HOST_TRAP_ACK', - 'SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT', - 'SQ_SYSMSG_OP_MEMVIOL_INTERRUPT', 'SQ_SYSMSG_OP_REG_RD', - 'SQ_SYSMSG_OP_TTRACE_PC', 'SQ_S_ABSDIFF_I32', 'SQ_S_ABS_I32', - 'SQ_S_ADDC_U32', 'SQ_S_ADDK_I32', 'SQ_S_ADD_I32', 'SQ_S_ADD_U32', - 'SQ_S_ANDN1_SAVEEXEC_B64', 'SQ_S_ANDN1_WREXEC_B64', - 'SQ_S_ANDN2_B32', 'SQ_S_ANDN2_B64', 'SQ_S_ANDN2_SAVEEXEC_B64', - 'SQ_S_ANDN2_WREXEC_B64', 'SQ_S_AND_B32', 'SQ_S_AND_B64', - 'SQ_S_AND_SAVEEXEC_B64', 'SQ_S_ASHR_I32', 'SQ_S_ASHR_I64', - 'SQ_S_ATC_PROBE', 'SQ_S_ATC_PROBE_BUFFER', 'SQ_S_ATOMIC_ADD', - 'SQ_S_ATOMIC_ADD_X2', 'SQ_S_ATOMIC_AND', 'SQ_S_ATOMIC_AND_X2', - 'SQ_S_ATOMIC_CMPSWAP', 'SQ_S_ATOMIC_CMPSWAP_X2', - 'SQ_S_ATOMIC_DEC', 'SQ_S_ATOMIC_DEC_X2', 'SQ_S_ATOMIC_INC', - 'SQ_S_ATOMIC_INC_X2', 'SQ_S_ATOMIC_OR', 'SQ_S_ATOMIC_OR_X2', - 'SQ_S_ATOMIC_SMAX', 'SQ_S_ATOMIC_SMAX_X2', 'SQ_S_ATOMIC_SMIN', - 'SQ_S_ATOMIC_SMIN_X2', 'SQ_S_ATOMIC_SUB', 'SQ_S_ATOMIC_SUB_X2', - 'SQ_S_ATOMIC_SWAP', 'SQ_S_ATOMIC_SWAP_X2', 'SQ_S_ATOMIC_UMAX', - 'SQ_S_ATOMIC_UMAX_X2', 'SQ_S_ATOMIC_UMIN', 'SQ_S_ATOMIC_UMIN_X2', - 'SQ_S_ATOMIC_XOR', 'SQ_S_ATOMIC_XOR_X2', 'SQ_S_BARRIER', - 'SQ_S_BCNT0_I32_B32', 'SQ_S_BCNT0_I32_B64', 'SQ_S_BCNT1_I32_B32', - 'SQ_S_BCNT1_I32_B64', 'SQ_S_BFE_I32', 'SQ_S_BFE_I64', - 'SQ_S_BFE_U32', 'SQ_S_BFE_U64', 'SQ_S_BFM_B32', 'SQ_S_BFM_B64', - 'SQ_S_BITCMP0_B32', 'SQ_S_BITCMP0_B64', 'SQ_S_BITCMP1_B32', - 'SQ_S_BITCMP1_B64', 'SQ_S_BITREPLICATE_B64_B32', - 'SQ_S_BITSET0_B32', 'SQ_S_BITSET0_B64', 'SQ_S_BITSET1_B32', - 'SQ_S_BITSET1_B64', 'SQ_S_BRANCH', 'SQ_S_BREV_B32', - 'SQ_S_BREV_B64', 'SQ_S_BUFFER_ATOMIC_ADD', - 'SQ_S_BUFFER_ATOMIC_ADD_X2', 'SQ_S_BUFFER_ATOMIC_AND', - 'SQ_S_BUFFER_ATOMIC_AND_X2', 'SQ_S_BUFFER_ATOMIC_CMPSWAP', - 'SQ_S_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_S_BUFFER_ATOMIC_DEC', - 'SQ_S_BUFFER_ATOMIC_DEC_X2', 'SQ_S_BUFFER_ATOMIC_INC', - 'SQ_S_BUFFER_ATOMIC_INC_X2', 'SQ_S_BUFFER_ATOMIC_OR', - 'SQ_S_BUFFER_ATOMIC_OR_X2', 'SQ_S_BUFFER_ATOMIC_SMAX', - 'SQ_S_BUFFER_ATOMIC_SMAX_X2', 'SQ_S_BUFFER_ATOMIC_SMIN', - 'SQ_S_BUFFER_ATOMIC_SMIN_X2', 'SQ_S_BUFFER_ATOMIC_SUB', - 'SQ_S_BUFFER_ATOMIC_SUB_X2', 'SQ_S_BUFFER_ATOMIC_SWAP', - 'SQ_S_BUFFER_ATOMIC_SWAP_X2', 'SQ_S_BUFFER_ATOMIC_UMAX', - 'SQ_S_BUFFER_ATOMIC_UMAX_X2', 'SQ_S_BUFFER_ATOMIC_UMIN', - 'SQ_S_BUFFER_ATOMIC_UMIN_X2', 'SQ_S_BUFFER_ATOMIC_XOR', - 'SQ_S_BUFFER_ATOMIC_XOR_X2', 'SQ_S_BUFFER_LOAD_DWORD', - 'SQ_S_BUFFER_LOAD_DWORDX16', 'SQ_S_BUFFER_LOAD_DWORDX2', - 'SQ_S_BUFFER_LOAD_DWORDX4', 'SQ_S_BUFFER_LOAD_DWORDX8', - 'SQ_S_BUFFER_STORE_DWORD', 'SQ_S_BUFFER_STORE_DWORDX2', - 'SQ_S_BUFFER_STORE_DWORDX4', 'SQ_S_CALL_B64', - 'SQ_S_CBRANCH_CDBGSYS', 'SQ_S_CBRANCH_CDBGSYS_AND_USER', - 'SQ_S_CBRANCH_CDBGSYS_OR_USER', 'SQ_S_CBRANCH_CDBGUSER', - 'SQ_S_CBRANCH_EXECNZ', 'SQ_S_CBRANCH_EXECZ', - 'SQ_S_CBRANCH_G_FORK', 'SQ_S_CBRANCH_I_FORK', 'SQ_S_CBRANCH_JOIN', - 'SQ_S_CBRANCH_SCC0', 'SQ_S_CBRANCH_SCC1', 'SQ_S_CBRANCH_VCCNZ', - 'SQ_S_CBRANCH_VCCZ', 'SQ_S_CMOVK_I32', 'SQ_S_CMOV_B32', - 'SQ_S_CMOV_B64', 'SQ_S_CMPK_EQ_I32', 'SQ_S_CMPK_EQ_U32', - 'SQ_S_CMPK_GE_I32', 'SQ_S_CMPK_GE_U32', 'SQ_S_CMPK_GT_I32', - 'SQ_S_CMPK_GT_U32', 'SQ_S_CMPK_LE_I32', 'SQ_S_CMPK_LE_U32', - 'SQ_S_CMPK_LG_I32', 'SQ_S_CMPK_LG_U32', 'SQ_S_CMPK_LT_I32', - 'SQ_S_CMPK_LT_U32', 'SQ_S_CMP_EQ_I32', 'SQ_S_CMP_EQ_U32', - 'SQ_S_CMP_EQ_U64', 'SQ_S_CMP_GE_I32', 'SQ_S_CMP_GE_U32', - 'SQ_S_CMP_GT_I32', 'SQ_S_CMP_GT_U32', 'SQ_S_CMP_LE_I32', - 'SQ_S_CMP_LE_U32', 'SQ_S_CMP_LG_I32', 'SQ_S_CMP_LG_U32', - 'SQ_S_CMP_LG_U64', 'SQ_S_CMP_LT_I32', 'SQ_S_CMP_LT_U32', - 'SQ_S_CSELECT_B32', 'SQ_S_CSELECT_B64', 'SQ_S_DCACHE_INV', - 'SQ_S_DCACHE_INV_VOL', 'SQ_S_DCACHE_WB', 'SQ_S_DCACHE_WB_VOL', - 'SQ_S_DECPERFLEVEL', 'SQ_S_ENDPGM', 'SQ_S_ENDPGM_ORDERED_PS_DONE', - 'SQ_S_ENDPGM_SAVED', 'SQ_S_FF0_I32_B32', 'SQ_S_FF0_I32_B64', - 'SQ_S_FF1_I32_B32', 'SQ_S_FF1_I32_B64', 'SQ_S_FLBIT_I32', - 'SQ_S_FLBIT_I32_B32', 'SQ_S_FLBIT_I32_B64', 'SQ_S_FLBIT_I32_I64', - 'SQ_S_GETPC_B64', 'SQ_S_GETREG_B32', 'SQ_S_GETREG_REGRD_B32', - 'SQ_S_ICACHE_INV', 'SQ_S_INCPERFLEVEL', 'SQ_S_LOAD_DWORD', - 'SQ_S_LOAD_DWORDX16', 'SQ_S_LOAD_DWORDX2', 'SQ_S_LOAD_DWORDX4', - 'SQ_S_LOAD_DWORDX8', 'SQ_S_LSHL1_ADD_U32', 'SQ_S_LSHL2_ADD_U32', - 'SQ_S_LSHL3_ADD_U32', 'SQ_S_LSHL4_ADD_U32', 'SQ_S_LSHL_B32', - 'SQ_S_LSHL_B64', 'SQ_S_LSHR_B32', 'SQ_S_LSHR_B64', 'SQ_S_MAX_I32', - 'SQ_S_MAX_U32', 'SQ_S_MEMREALTIME', 'SQ_S_MEMTIME', - 'SQ_S_MIN_I32', 'SQ_S_MIN_U32', 'SQ_S_MOVK_I32', - 'SQ_S_MOVRELD_B32', 'SQ_S_MOVRELD_B64', 'SQ_S_MOVRELS_B32', - 'SQ_S_MOVRELS_B64', 'SQ_S_MOV_B32', 'SQ_S_MOV_B64', - 'SQ_S_MOV_FED_B32', 'SQ_S_MOV_REGRD_B32', 'SQ_S_MULK_I32', - 'SQ_S_MUL_HI_I32', 'SQ_S_MUL_HI_U32', 'SQ_S_MUL_I32', - 'SQ_S_NAND_B32', 'SQ_S_NAND_B64', 'SQ_S_NAND_SAVEEXEC_B64', - 'SQ_S_NOP', 'SQ_S_NOR_B32', 'SQ_S_NOR_B64', - 'SQ_S_NOR_SAVEEXEC_B64', 'SQ_S_NOT_B32', 'SQ_S_NOT_B64', - 'SQ_S_ORN1_SAVEEXEC_B64', 'SQ_S_ORN2_B32', 'SQ_S_ORN2_B64', - 'SQ_S_ORN2_SAVEEXEC_B64', 'SQ_S_OR_B32', 'SQ_S_OR_B64', - 'SQ_S_OR_SAVEEXEC_B64', 'SQ_S_PACK_HH_B32_B16', - 'SQ_S_PACK_LH_B32_B16', 'SQ_S_PACK_LL_B32_B16', - 'SQ_S_QUADMASK_B32', 'SQ_S_QUADMASK_B64', 'SQ_S_RFE_B64', - 'SQ_S_RFE_RESTORE_B64', 'SQ_S_SCRATCH_LOAD_DWORD', - 'SQ_S_SCRATCH_LOAD_DWORDX2', 'SQ_S_SCRATCH_LOAD_DWORDX4', - 'SQ_S_SCRATCH_STORE_DWORD', 'SQ_S_SCRATCH_STORE_DWORDX2', - 'SQ_S_SCRATCH_STORE_DWORDX4', 'SQ_S_SENDMSG', 'SQ_S_SENDMSGHALT', - 'SQ_S_SETHALT', 'SQ_S_SETKILL', 'SQ_S_SETPC_B64', 'SQ_S_SETPRIO', - 'SQ_S_SETREG_B32', 'SQ_S_SETREG_IMM32_B32', 'SQ_S_SETVSKIP', - 'SQ_S_SET_GPR_IDX_IDX', 'SQ_S_SET_GPR_IDX_MODE', - 'SQ_S_SET_GPR_IDX_OFF', 'SQ_S_SET_GPR_IDX_ON', - 'SQ_S_SEXT_I32_I16', 'SQ_S_SEXT_I32_I8', 'SQ_S_SLEEP', - 'SQ_S_STORE_DWORD', 'SQ_S_STORE_DWORDX2', 'SQ_S_STORE_DWORDX4', - 'SQ_S_SUBB_U32', 'SQ_S_SUB_I32', 'SQ_S_SUB_U32', - 'SQ_S_SWAPPC_B64', 'SQ_S_TRAP', 'SQ_S_TTRACEDATA', 'SQ_S_WAITCNT', - 'SQ_S_WAKEUP', 'SQ_S_WQM_B32', 'SQ_S_WQM_B64', 'SQ_S_XNOR_B32', - 'SQ_S_XNOR_B64', 'SQ_S_XNOR_SAVEEXEC_B64', 'SQ_S_XOR_B32', - 'SQ_S_XOR_B64', 'SQ_S_XOR_SAVEEXEC_B64', 'SQ_T', - 'SQ_TBUFFER_LOAD_FORMAT_D16_X', 'SQ_TBUFFER_LOAD_FORMAT_D16_XY', - 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZ', - 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_TBUFFER_LOAD_FORMAT_X', - 'SQ_TBUFFER_LOAD_FORMAT_XY', 'SQ_TBUFFER_LOAD_FORMAT_XYZ', - 'SQ_TBUFFER_LOAD_FORMAT_XYZW', 'SQ_TBUFFER_STORE_FORMAT_D16_X', - 'SQ_TBUFFER_STORE_FORMAT_D16_XY', - 'SQ_TBUFFER_STORE_FORMAT_D16_XYZ', - 'SQ_TBUFFER_STORE_FORMAT_D16_XYZW', 'SQ_TBUFFER_STORE_FORMAT_X', - 'SQ_TBUFFER_STORE_FORMAT_XY', 'SQ_TBUFFER_STORE_FORMAT_XYZ', - 'SQ_TBUFFER_STORE_FORMAT_XYZW', 'SQ_TEX_ANISO_RATIO', - 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', - 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', - 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', - 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', - 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', - 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 'SQ_TEX_DEPTH_COMPARE_GREATER', - 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', - 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', - 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', - 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', - 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', - 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', - 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', - 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', - 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', - 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', - 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', - 'SQ_THREAD_TRACE_CAPTURE_MODE', - 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', - 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', - 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', - 'SQ_THREAD_TRACE_INST_TYPE', - 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', - 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', - 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', - 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', - 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', - 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', - 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', - 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', - 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', - 'SQ_THREAD_TRACE_INST_TYPE_JUMP', 'SQ_THREAD_TRACE_INST_TYPE_LDS', - 'SQ_THREAD_TRACE_INST_TYPE_NEXT', - 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', - 'SQ_THREAD_TRACE_INST_TYPE_PC', - 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', - 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', - 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', - 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', - 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', - 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', - 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', - 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', - 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', - 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', - 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', - 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', - 'SQ_THREAD_TRACE_ISSUE', 'SQ_THREAD_TRACE_ISSUE_IMMED', - 'SQ_THREAD_TRACE_ISSUE_INST', 'SQ_THREAD_TRACE_ISSUE_MASK', - 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', - 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', - 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', - 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', - 'SQ_THREAD_TRACE_ISSUE_NULL', 'SQ_THREAD_TRACE_ISSUE_STALL', - 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', - 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', - 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', - 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', - 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', - 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', - 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', - 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', - 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE', 'SQ_THREAD_TRACE_MODE_OFF', - 'SQ_THREAD_TRACE_MODE_ON', 'SQ_THREAD_TRACE_MODE_SEL', - 'SQ_THREAD_TRACE_REG_OP', 'SQ_THREAD_TRACE_REG_OP_READ', - 'SQ_THREAD_TRACE_REG_OP_WRITE', 'SQ_THREAD_TRACE_REG_TYPE', - 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', - 'SQ_THREAD_TRACE_REG_TYPE_DRAW', 'SQ_THREAD_TRACE_REG_TYPE_EVENT', - 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', - 'SQ_THREAD_TRACE_REG_TYPE_MARKER', - 'SQ_THREAD_TRACE_REG_TYPE_OTHER', - 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', - 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', 'SQ_THREAD_TRACE_TIME_UNIT', - 'SQ_THREAD_TRACE_TOKEN_EVENT', 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', - 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', 'SQ_THREAD_TRACE_TOKEN_INST', - 'SQ_THREAD_TRACE_TOKEN_INST_PC', - 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', - 'SQ_THREAD_TRACE_TOKEN_ISSUE', 'SQ_THREAD_TRACE_TOKEN_MISC', - 'SQ_THREAD_TRACE_TOKEN_PERF', 'SQ_THREAD_TRACE_TOKEN_REG', - 'SQ_THREAD_TRACE_TOKEN_REG_CS', - 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', - 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', 'SQ_THREAD_TRACE_TOKEN_TYPE', - 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', - 'SQ_THREAD_TRACE_TOKEN_WAVE_END', - 'SQ_THREAD_TRACE_TOKEN_WAVE_START', 'SQ_THREAD_TRACE_VM_ID_MASK', - 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', - 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', - 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', - 'SQ_THREAD_TRACE_WAVE_MASK', 'SQ_THREAD_TRACE_WAVE_MASK_ALL', - 'SQ_THREAD_TRACE_WAVE_MASK_NONE', - 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX', - 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', - 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', 'SQ_TRU', - 'SQ_TTMP0', 'SQ_TTMP1', 'SQ_TTMP10', 'SQ_TTMP11', 'SQ_TTMP12', - 'SQ_TTMP13', 'SQ_TTMP14', 'SQ_TTMP15', 'SQ_TTMP2', 'SQ_TTMP3', - 'SQ_TTMP4', 'SQ_TTMP5', 'SQ_TTMP6', 'SQ_TTMP7', 'SQ_TTMP8', - 'SQ_TTMP9', 'SQ_U', 'SQ_VCC_ALL', 'SQ_VCC_HI', 'SQ_VCC_LO', - 'SQ_VGPR0', 'SQ_V_ADD3_U32', 'SQ_V_ADDC_CO_U32', - 'SQ_V_ADD_CO_U32', 'SQ_V_ADD_F16', 'SQ_V_ADD_F32', 'SQ_V_ADD_F64', - 'SQ_V_ADD_I16', 'SQ_V_ADD_I32', 'SQ_V_ADD_LSHL_U32', - 'SQ_V_ADD_U16', 'SQ_V_ADD_U32', 'SQ_V_ALIGNBIT_B32', - 'SQ_V_ALIGNBYTE_B32', 'SQ_V_AND_B32', 'SQ_V_AND_OR_B32', - 'SQ_V_ASHRREV_I16', 'SQ_V_ASHRREV_I32', 'SQ_V_ASHRREV_I64', - 'SQ_V_BCNT_U32_B32', 'SQ_V_BFE_I32', 'SQ_V_BFE_U32', - 'SQ_V_BFI_B32', 'SQ_V_BFM_B32', 'SQ_V_BFREV_B32', 'SQ_V_CEIL_F16', - 'SQ_V_CEIL_F32', 'SQ_V_CEIL_F64', 'SQ_V_CLREXCP', - 'SQ_V_CMPX_CLASS_F16', 'SQ_V_CMPX_CLASS_F32', - 'SQ_V_CMPX_CLASS_F64', 'SQ_V_CMPX_EQ_F16', 'SQ_V_CMPX_EQ_F32', - 'SQ_V_CMPX_EQ_F64', 'SQ_V_CMPX_EQ_I16', 'SQ_V_CMPX_EQ_I32', - 'SQ_V_CMPX_EQ_I64', 'SQ_V_CMPX_EQ_U16', 'SQ_V_CMPX_EQ_U32', - 'SQ_V_CMPX_EQ_U64', 'SQ_V_CMPX_F_F16', 'SQ_V_CMPX_F_F32', - 'SQ_V_CMPX_F_F64', 'SQ_V_CMPX_F_I16', 'SQ_V_CMPX_F_I32', - 'SQ_V_CMPX_F_I64', 'SQ_V_CMPX_F_U16', 'SQ_V_CMPX_F_U32', - 'SQ_V_CMPX_F_U64', 'SQ_V_CMPX_GE_F16', 'SQ_V_CMPX_GE_F32', - 'SQ_V_CMPX_GE_F64', 'SQ_V_CMPX_GE_I16', 'SQ_V_CMPX_GE_I32', - 'SQ_V_CMPX_GE_I64', 'SQ_V_CMPX_GE_U16', 'SQ_V_CMPX_GE_U32', - 'SQ_V_CMPX_GE_U64', 'SQ_V_CMPX_GT_F16', 'SQ_V_CMPX_GT_F32', - 'SQ_V_CMPX_GT_F64', 'SQ_V_CMPX_GT_I16', 'SQ_V_CMPX_GT_I32', - 'SQ_V_CMPX_GT_I64', 'SQ_V_CMPX_GT_U16', 'SQ_V_CMPX_GT_U32', - 'SQ_V_CMPX_GT_U64', 'SQ_V_CMPX_LE_F16', 'SQ_V_CMPX_LE_F32', - 'SQ_V_CMPX_LE_F64', 'SQ_V_CMPX_LE_I16', 'SQ_V_CMPX_LE_I32', - 'SQ_V_CMPX_LE_I64', 'SQ_V_CMPX_LE_U16', 'SQ_V_CMPX_LE_U32', - 'SQ_V_CMPX_LE_U64', 'SQ_V_CMPX_LG_F16', 'SQ_V_CMPX_LG_F32', - 'SQ_V_CMPX_LG_F64', 'SQ_V_CMPX_LT_F16', 'SQ_V_CMPX_LT_F32', - 'SQ_V_CMPX_LT_F64', 'SQ_V_CMPX_LT_I16', 'SQ_V_CMPX_LT_I32', - 'SQ_V_CMPX_LT_I64', 'SQ_V_CMPX_LT_U16', 'SQ_V_CMPX_LT_U32', - 'SQ_V_CMPX_LT_U64', 'SQ_V_CMPX_NEQ_F16', 'SQ_V_CMPX_NEQ_F32', - 'SQ_V_CMPX_NEQ_F64', 'SQ_V_CMPX_NE_I16', 'SQ_V_CMPX_NE_I32', - 'SQ_V_CMPX_NE_I64', 'SQ_V_CMPX_NE_U16', 'SQ_V_CMPX_NE_U32', - 'SQ_V_CMPX_NE_U64', 'SQ_V_CMPX_NGE_F16', 'SQ_V_CMPX_NGE_F32', - 'SQ_V_CMPX_NGE_F64', 'SQ_V_CMPX_NGT_F16', 'SQ_V_CMPX_NGT_F32', - 'SQ_V_CMPX_NGT_F64', 'SQ_V_CMPX_NLE_F16', 'SQ_V_CMPX_NLE_F32', - 'SQ_V_CMPX_NLE_F64', 'SQ_V_CMPX_NLG_F16', 'SQ_V_CMPX_NLG_F32', - 'SQ_V_CMPX_NLG_F64', 'SQ_V_CMPX_NLT_F16', 'SQ_V_CMPX_NLT_F32', - 'SQ_V_CMPX_NLT_F64', 'SQ_V_CMPX_O_F16', 'SQ_V_CMPX_O_F32', - 'SQ_V_CMPX_O_F64', 'SQ_V_CMPX_TRU_F16', 'SQ_V_CMPX_TRU_F32', - 'SQ_V_CMPX_TRU_F64', 'SQ_V_CMPX_T_I16', 'SQ_V_CMPX_T_I32', - 'SQ_V_CMPX_T_I64', 'SQ_V_CMPX_T_U16', 'SQ_V_CMPX_T_U32', - 'SQ_V_CMPX_T_U64', 'SQ_V_CMPX_U_F16', 'SQ_V_CMPX_U_F32', - 'SQ_V_CMPX_U_F64', 'SQ_V_CMP_CLASS_F16', 'SQ_V_CMP_CLASS_F32', - 'SQ_V_CMP_CLASS_F64', 'SQ_V_CMP_EQ_F16', 'SQ_V_CMP_EQ_F32', - 'SQ_V_CMP_EQ_F64', 'SQ_V_CMP_EQ_I16', 'SQ_V_CMP_EQ_I32', - 'SQ_V_CMP_EQ_I64', 'SQ_V_CMP_EQ_U16', 'SQ_V_CMP_EQ_U32', - 'SQ_V_CMP_EQ_U64', 'SQ_V_CMP_F_F16', 'SQ_V_CMP_F_F32', - 'SQ_V_CMP_F_F64', 'SQ_V_CMP_F_I16', 'SQ_V_CMP_F_I32', - 'SQ_V_CMP_F_I64', 'SQ_V_CMP_F_U16', 'SQ_V_CMP_F_U32', - 'SQ_V_CMP_F_U64', 'SQ_V_CMP_GE_F16', 'SQ_V_CMP_GE_F32', - 'SQ_V_CMP_GE_F64', 'SQ_V_CMP_GE_I16', 'SQ_V_CMP_GE_I32', - 'SQ_V_CMP_GE_I64', 'SQ_V_CMP_GE_U16', 'SQ_V_CMP_GE_U32', - 'SQ_V_CMP_GE_U64', 'SQ_V_CMP_GT_F16', 'SQ_V_CMP_GT_F32', - 'SQ_V_CMP_GT_F64', 'SQ_V_CMP_GT_I16', 'SQ_V_CMP_GT_I32', - 'SQ_V_CMP_GT_I64', 'SQ_V_CMP_GT_U16', 'SQ_V_CMP_GT_U32', - 'SQ_V_CMP_GT_U64', 'SQ_V_CMP_LE_F16', 'SQ_V_CMP_LE_F32', - 'SQ_V_CMP_LE_F64', 'SQ_V_CMP_LE_I16', 'SQ_V_CMP_LE_I32', - 'SQ_V_CMP_LE_I64', 'SQ_V_CMP_LE_U16', 'SQ_V_CMP_LE_U32', - 'SQ_V_CMP_LE_U64', 'SQ_V_CMP_LG_F16', 'SQ_V_CMP_LG_F32', - 'SQ_V_CMP_LG_F64', 'SQ_V_CMP_LT_F16', 'SQ_V_CMP_LT_F32', - 'SQ_V_CMP_LT_F64', 'SQ_V_CMP_LT_I16', 'SQ_V_CMP_LT_I32', - 'SQ_V_CMP_LT_I64', 'SQ_V_CMP_LT_U16', 'SQ_V_CMP_LT_U32', - 'SQ_V_CMP_LT_U64', 'SQ_V_CMP_NEQ_F16', 'SQ_V_CMP_NEQ_F32', - 'SQ_V_CMP_NEQ_F64', 'SQ_V_CMP_NE_I16', 'SQ_V_CMP_NE_I32', - 'SQ_V_CMP_NE_I64', 'SQ_V_CMP_NE_U16', 'SQ_V_CMP_NE_U32', - 'SQ_V_CMP_NE_U64', 'SQ_V_CMP_NGE_F16', 'SQ_V_CMP_NGE_F32', - 'SQ_V_CMP_NGE_F64', 'SQ_V_CMP_NGT_F16', 'SQ_V_CMP_NGT_F32', - 'SQ_V_CMP_NGT_F64', 'SQ_V_CMP_NLE_F16', 'SQ_V_CMP_NLE_F32', - 'SQ_V_CMP_NLE_F64', 'SQ_V_CMP_NLG_F16', 'SQ_V_CMP_NLG_F32', - 'SQ_V_CMP_NLG_F64', 'SQ_V_CMP_NLT_F16', 'SQ_V_CMP_NLT_F32', - 'SQ_V_CMP_NLT_F64', 'SQ_V_CMP_O_F16', 'SQ_V_CMP_O_F32', - 'SQ_V_CMP_O_F64', 'SQ_V_CMP_TRU_F16', 'SQ_V_CMP_TRU_F32', - 'SQ_V_CMP_TRU_F64', 'SQ_V_CMP_T_I16', 'SQ_V_CMP_T_I32', - 'SQ_V_CMP_T_I64', 'SQ_V_CMP_T_U16', 'SQ_V_CMP_T_U32', - 'SQ_V_CMP_T_U64', 'SQ_V_CMP_U_F16', 'SQ_V_CMP_U_F32', - 'SQ_V_CMP_U_F64', 'SQ_V_CNDMASK_B32', 'SQ_V_COS_F16', - 'SQ_V_COS_F32', 'SQ_V_CUBEID_F32', 'SQ_V_CUBEMA_F32', - 'SQ_V_CUBESC_F32', 'SQ_V_CUBETC_F32', 'SQ_V_CVT_F16_F32', - 'SQ_V_CVT_F16_I16', 'SQ_V_CVT_F16_U16', 'SQ_V_CVT_F32_F16', - 'SQ_V_CVT_F32_F64', 'SQ_V_CVT_F32_I32', 'SQ_V_CVT_F32_U32', - 'SQ_V_CVT_F32_UBYTE0', 'SQ_V_CVT_F32_UBYTE1', - 'SQ_V_CVT_F32_UBYTE2', 'SQ_V_CVT_F32_UBYTE3', 'SQ_V_CVT_F64_F32', - 'SQ_V_CVT_F64_I32', 'SQ_V_CVT_F64_U32', 'SQ_V_CVT_FLR_I32_F32', - 'SQ_V_CVT_I16_F16', 'SQ_V_CVT_I32_F32', 'SQ_V_CVT_I32_F64', - 'SQ_V_CVT_NORM_I16_F16', 'SQ_V_CVT_NORM_U16_F16', - 'SQ_V_CVT_OFF_F32_I4', 'SQ_V_CVT_PKACCUM_U8_F32', - 'SQ_V_CVT_PKNORM_I16_F16', 'SQ_V_CVT_PKNORM_I16_F32', - 'SQ_V_CVT_PKNORM_U16_F16', 'SQ_V_CVT_PKNORM_U16_F32', - 'SQ_V_CVT_PKRTZ_F16_F32', 'SQ_V_CVT_PK_I16_I32', - 'SQ_V_CVT_PK_U16_U32', 'SQ_V_CVT_PK_U8_F32', - 'SQ_V_CVT_RPI_I32_F32', 'SQ_V_CVT_U16_F16', 'SQ_V_CVT_U32_F32', - 'SQ_V_CVT_U32_F64', 'SQ_V_DIV_FIXUP_F16', 'SQ_V_DIV_FIXUP_F32', - 'SQ_V_DIV_FIXUP_F64', 'SQ_V_DIV_FIXUP_LEGACY_F16', - 'SQ_V_DIV_FMAS_F32', 'SQ_V_DIV_FMAS_F64', 'SQ_V_DIV_SCALE_F32', - 'SQ_V_DIV_SCALE_F64', 'SQ_V_EXP_F16', 'SQ_V_EXP_F32', - 'SQ_V_EXP_LEGACY_F32', 'SQ_V_FFBH_I32', 'SQ_V_FFBH_U32', - 'SQ_V_FFBL_B32', 'SQ_V_FLOOR_F16', 'SQ_V_FLOOR_F32', - 'SQ_V_FLOOR_F64', 'SQ_V_FMA_F16', 'SQ_V_FMA_F32', 'SQ_V_FMA_F64', - 'SQ_V_FMA_LEGACY_F16', 'SQ_V_FRACT_F16', 'SQ_V_FRACT_F32', - 'SQ_V_FRACT_F64', 'SQ_V_FREXP_EXP_I16_F16', - 'SQ_V_FREXP_EXP_I32_F32', 'SQ_V_FREXP_EXP_I32_F64', - 'SQ_V_FREXP_MANT_F16', 'SQ_V_FREXP_MANT_F32', - 'SQ_V_FREXP_MANT_F64', 'SQ_V_INTERP_MOV_F32', - 'SQ_V_INTERP_P1LL_F16', 'SQ_V_INTERP_P1LV_F16', - 'SQ_V_INTERP_P1_F32', 'SQ_V_INTERP_P2_F16', 'SQ_V_INTERP_P2_F32', - 'SQ_V_INTERP_P2_LEGACY_F16', 'SQ_V_INTRP_COUNT', - 'SQ_V_INTRP_OFFSET', 'SQ_V_LDEXP_F16', 'SQ_V_LDEXP_F32', - 'SQ_V_LDEXP_F64', 'SQ_V_LERP_U8', 'SQ_V_LOG_F16', 'SQ_V_LOG_F32', - 'SQ_V_LOG_LEGACY_F32', 'SQ_V_LSHLREV_B16', 'SQ_V_LSHLREV_B32', - 'SQ_V_LSHLREV_B64', 'SQ_V_LSHL_ADD_U32', 'SQ_V_LSHL_OR_B32', - 'SQ_V_LSHRREV_B16', 'SQ_V_LSHRREV_B32', 'SQ_V_LSHRREV_B64', - 'SQ_V_MAC_F16', 'SQ_V_MAC_F32', 'SQ_V_MAC_LEGACY_F32', - 'SQ_V_MADAK_F16', 'SQ_V_MADAK_F32', 'SQ_V_MADMK_F16', - 'SQ_V_MADMK_F32', 'SQ_V_MAD_F16', 'SQ_V_MAD_F32', 'SQ_V_MAD_I16', - 'SQ_V_MAD_I32_I16', 'SQ_V_MAD_I32_I24', 'SQ_V_MAD_I64_I32', - 'SQ_V_MAD_LEGACY_F16', 'SQ_V_MAD_LEGACY_F32', - 'SQ_V_MAD_LEGACY_I16', 'SQ_V_MAD_LEGACY_U16', - 'SQ_V_MAD_MIXHI_F16', 'SQ_V_MAD_MIXLO_F16', 'SQ_V_MAD_MIX_F32', - 'SQ_V_MAD_U16', 'SQ_V_MAD_U32_U16', 'SQ_V_MAD_U32_U24', - 'SQ_V_MAD_U64_U32', 'SQ_V_MAX3_F16', 'SQ_V_MAX3_F32', - 'SQ_V_MAX3_I16', 'SQ_V_MAX3_I32', 'SQ_V_MAX3_U16', - 'SQ_V_MAX3_U32', 'SQ_V_MAX_F16', 'SQ_V_MAX_F32', 'SQ_V_MAX_F64', - 'SQ_V_MAX_I16', 'SQ_V_MAX_I32', 'SQ_V_MAX_U16', 'SQ_V_MAX_U32', - 'SQ_V_MBCNT_HI_U32_B32', 'SQ_V_MBCNT_LO_U32_B32', 'SQ_V_MED3_F16', - 'SQ_V_MED3_F32', 'SQ_V_MED3_I16', 'SQ_V_MED3_I32', - 'SQ_V_MED3_U16', 'SQ_V_MED3_U32', 'SQ_V_MIN3_F16', - 'SQ_V_MIN3_F32', 'SQ_V_MIN3_I16', 'SQ_V_MIN3_I32', - 'SQ_V_MIN3_U16', 'SQ_V_MIN3_U32', 'SQ_V_MIN_F16', 'SQ_V_MIN_F32', - 'SQ_V_MIN_F64', 'SQ_V_MIN_I16', 'SQ_V_MIN_I32', 'SQ_V_MIN_U16', - 'SQ_V_MIN_U32', 'SQ_V_MOV_B32', 'SQ_V_MOV_FED_B32', - 'SQ_V_MOV_PRSV_B32', 'SQ_V_MQSAD_PK_U16_U8', 'SQ_V_MQSAD_U32_U8', - 'SQ_V_MSAD_U8', 'SQ_V_MUL_F16', 'SQ_V_MUL_F32', 'SQ_V_MUL_F64', - 'SQ_V_MUL_HI_I32', 'SQ_V_MUL_HI_I32_I24', 'SQ_V_MUL_HI_U32', - 'SQ_V_MUL_HI_U32_U24', 'SQ_V_MUL_I32_I24', 'SQ_V_MUL_LEGACY_F32', - 'SQ_V_MUL_LO_U16', 'SQ_V_MUL_LO_U32', 'SQ_V_MUL_U32_U24', - 'SQ_V_NOP', 'SQ_V_NOT_B32', 'SQ_V_OP1_COUNT', 'SQ_V_OP1_OFFSET', - 'SQ_V_OP2_COUNT', 'SQ_V_OP2_OFFSET', 'SQ_V_OP3P_COUNT', - 'SQ_V_OP3P_OFFSET', 'SQ_V_OP3_2IN_COUNT', 'SQ_V_OP3_2IN_OFFSET', - 'SQ_V_OP3_3IN_COUNT', 'SQ_V_OP3_3IN_OFFSET', - 'SQ_V_OP3_INTRP_COUNT', 'SQ_V_OP3_INTRP_OFFSET', 'SQ_V_OPC_COUNT', - 'SQ_V_OPC_OFFSET', 'SQ_V_OR3_B32', 'SQ_V_OR_B32', - 'SQ_V_PACK_B32_F16', 'SQ_V_PERM_B32', 'SQ_V_PK_ADD_F16', - 'SQ_V_PK_ADD_I16', 'SQ_V_PK_ADD_U16', 'SQ_V_PK_ASHRREV_I16', - 'SQ_V_PK_LSHLREV_B16', 'SQ_V_PK_LSHRREV_B16', 'SQ_V_PK_MAD_F16', - 'SQ_V_PK_MAD_I16', 'SQ_V_PK_MAD_U16', 'SQ_V_PK_MAX_F16', - 'SQ_V_PK_MAX_I16', 'SQ_V_PK_MAX_U16', 'SQ_V_PK_MIN_F16', - 'SQ_V_PK_MIN_I16', 'SQ_V_PK_MIN_U16', 'SQ_V_PK_MUL_F16', - 'SQ_V_PK_MUL_LO_U16', 'SQ_V_PK_SUB_I16', 'SQ_V_PK_SUB_U16', - 'SQ_V_QSAD_PK_U16_U8', 'SQ_V_RCP_F16', 'SQ_V_RCP_F32', - 'SQ_V_RCP_F64', 'SQ_V_RCP_IFLAG_F32', 'SQ_V_READFIRSTLANE_B32', - 'SQ_V_READLANE_B32', 'SQ_V_READLANE_REGRD_B32', 'SQ_V_RNDNE_F16', - 'SQ_V_RNDNE_F32', 'SQ_V_RNDNE_F64', 'SQ_V_RSQ_F16', - 'SQ_V_RSQ_F32', 'SQ_V_RSQ_F64', 'SQ_V_SAD_HI_U8', 'SQ_V_SAD_U16', - 'SQ_V_SAD_U32', 'SQ_V_SAD_U8', 'SQ_V_SAT_PK_U8_I16', - 'SQ_V_SIN_F16', 'SQ_V_SIN_F32', 'SQ_V_SQRT_F16', 'SQ_V_SQRT_F32', - 'SQ_V_SQRT_F64', 'SQ_V_SUBBREV_CO_U32', 'SQ_V_SUBB_CO_U32', - 'SQ_V_SUBREV_CO_U32', 'SQ_V_SUBREV_F16', 'SQ_V_SUBREV_F32', - 'SQ_V_SUBREV_U16', 'SQ_V_SUBREV_U32', 'SQ_V_SUB_CO_U32', - 'SQ_V_SUB_F16', 'SQ_V_SUB_F32', 'SQ_V_SUB_I16', 'SQ_V_SUB_I32', - 'SQ_V_SUB_U16', 'SQ_V_SUB_U32', 'SQ_V_SWAP_B32', - 'SQ_V_TRIG_PREOP_F64', 'SQ_V_TRUNC_F16', 'SQ_V_TRUNC_F32', - 'SQ_V_TRUNC_F64', 'SQ_V_WRITELANE_B32', 'SQ_V_WRITELANE_IMM32', - 'SQ_V_XAD_U32', 'SQ_V_XOR_B32', 'SQ_WAITCNT_EXP_SHIFT', - 'SQ_WAITCNT_EXP_SIZE', 'SQ_WAITCNT_LGKM_SHIFT', - 'SQ_WAITCNT_LGKM_SIZE', 'SQ_WAITCNT_VM_SHIFT', - 'SQ_WAITCNT_VM_SIZE', 'SQ_WAVE_IB_ECC_CLEAN', - 'SQ_WAVE_IB_ECC_ERR_CONTINUE', 'SQ_WAVE_IB_ECC_ERR_HALT', - 'SQ_WAVE_IB_ECC_ST', 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', - 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_ES', - 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_LS', - 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', - 'SQ_WAVE_TYPE_VS', 'SQ_XLATE_VOP3_TO_VINTRP_COUNT', - 'SQ_XLATE_VOP3_TO_VINTRP_OFFSET', 'SQ_XLATE_VOP3_TO_VOP1_COUNT', - 'SQ_XLATE_VOP3_TO_VOP1_OFFSET', 'SQ_XLATE_VOP3_TO_VOP2_COUNT', - 'SQ_XLATE_VOP3_TO_VOP2_OFFSET', 'SQ_XLATE_VOP3_TO_VOP3P_COUNT', - 'SQ_XLATE_VOP3_TO_VOP3P_OFFSET', 'SQ_XLATE_VOP3_TO_VOPC_COUNT', - 'SQ_XLATE_VOP3_TO_VOPC_OFFSET', 'SQ_XNACK_MASK_HI', - 'SQ_XNACK_MASK_LO', 'STATIC_SCREEN_SMU_INTR', - 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', - 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', - 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', - 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', - 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', - 'STREAM_0_SYNCHRONIZATION', - 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_10_SYNCHRONIZATION', - 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION', - 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION', - 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION', - 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION', - 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION', - 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_1_SYNCHRONIZATION', - 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_2_SYNCHRONIZATION', - 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_3_SYNCHRONIZATION', - 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_4_SYNCHRONIZATION', - 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_5_SYNCHRONIZATION', - 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_6_SYNCHRONIZATION', - 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION', - 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION', - 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION', - 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'STRM_PERFMON_STATE_RESERVED_3', - 'STRM_PERFMON_STATE_START_COUNTING', - 'STRM_PERFMON_STATE_STOP_COUNTING', 'SU_PERFCNT_SEL', 'SWAP_ALT', - 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWIZZLE_MODE_ENUM', - 'SWIZZLE_TYPE_ENUM', 'SW_256B_D', 'SW_256B_R', 'SW_256B_S', - 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', 'SW_4KB_S', - 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', - 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_X', 'SW_64KB_S', - 'SW_64KB_S_X', 'SW_64KB_Z', 'SW_64KB_Z_X', 'SW_D', 'SW_L', - 'SW_LINEAR', 'SW_R', 'SW_RESERVED_12', 'SW_RESERVED_13', - 'SW_RESERVED_14', 'SW_RESERVED_15', 'SW_RESERVED_16', - 'SW_RESERVED_17', 'SW_RESERVED_18', 'SW_RESERVED_19', 'SW_S', - 'SW_VAR_D', 'SW_VAR_D_X', 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', - 'SW_VAR_S_X', 'SW_VAR_Z', 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', - 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', - 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', - 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', - 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', - 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', - 'SX_PERF_SEL_DB0_PRED_PIXELS', - 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', - 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', - 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', - 'SX_PERF_SEL_DB1_PRED_PIXELS', - 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', - 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', - 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', - 'SX_PERF_SEL_DB2_PRED_PIXELS', - 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', - 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', - 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', - 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', - 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_GATE_EN1', - 'SX_PERF_SEL_GATE_EN2', 'SX_PERF_SEL_GATE_EN3', - 'SX_PERF_SEL_GATE_EN4', 'SX_PERF_SEL_PA_IDLE_CYCLES', - 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', - 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_SH_COLOR_STALL', - 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_POS_STALL', - 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', - 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', - 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', - 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', - 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', - 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', - 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', - 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'SYMCLK_FE_FORCE_SRC_UNIPHYE', - 'SYMCLK_FE_FORCE_SRC_UNIPHYF', 'SYMCLK_FE_FORCE_SRC_UNIPHYG', - 'SYNC_DURATION_128', 'SYNC_DURATION_16', 'SYNC_DURATION_32', - 'SYNC_DURATION_64', 'SYNC_RESET_SEL2_VBLANK', - 'SYNC_RESET_SEL2_VSYNC', 'SampleSplit', 'SampleSplitBytes', - 'ScMap', 'ScXsel', 'ScYsel', 'SeEnable', 'SeMap', 'SePairMap', - 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', - 'ShaderEngineTileSize', 'SourceFormat', 'StencilFormat', - 'StencilOp', 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', - 'SurfaceNumber', 'SurfaceSwap', 'SurfaceTiling', - 'TA_PERFCOUNT_SEL', 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_28', - 'TA_PERF_SEL_RESERVED_29', 'TA_PERF_SEL_RESERVED_41', - 'TA_PERF_SEL_RESERVED_42', 'TA_PERF_SEL_RESERVED_43', - 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', - 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 'TA_PERF_SEL_addresser_stalled_cycles', - 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', - 'TA_PERF_SEL_aniso_10_cycle_quads', - 'TA_PERF_SEL_aniso_12_cycle_quads', - 'TA_PERF_SEL_aniso_14_cycle_quads', - 'TA_PERF_SEL_aniso_16_cycle_quads', - 'TA_PERF_SEL_aniso_1_cycle_quads', - 'TA_PERF_SEL_aniso_2_cycle_quads', - 'TA_PERF_SEL_aniso_4_cycle_quads', - 'TA_PERF_SEL_aniso_6_cycle_quads', - 'TA_PERF_SEL_aniso_8_cycle_quads', - 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 'TA_PERF_SEL_aniso_stalled_cycles', - 'TA_PERF_SEL_bilin_point_1_cycle_pixels', - 'TA_PERF_SEL_buffer_atomic_wavefronts', - 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', - 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', - 'TA_PERF_SEL_buffer_coalescable_wavefronts', - 'TA_PERF_SEL_buffer_coalesced_read_cycles', - 'TA_PERF_SEL_buffer_coalesced_write_cycles', - 'TA_PERF_SEL_buffer_read_wavefronts', - 'TA_PERF_SEL_buffer_total_cycles', - 'TA_PERF_SEL_buffer_wavefronts', - 'TA_PERF_SEL_buffer_write_wavefronts', - 'TA_PERF_SEL_color_1_cycle_pixels', - 'TA_PERF_SEL_color_2_cycle_pixels', - 'TA_PERF_SEL_color_3_cycle_pixels', - 'TA_PERF_SEL_color_4_cycle_pixels', - 'TA_PERF_SEL_data_stalled_by_tc_cycles', - 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 'TA_PERF_SEL_deriv_stalled_cycles', - 'TA_PERF_SEL_first_xnack_on_phase0', - 'TA_PERF_SEL_first_xnack_on_phase1', - 'TA_PERF_SEL_first_xnack_on_phase2', - 'TA_PERF_SEL_first_xnack_on_phase3', - 'TA_PERF_SEL_flat_atomic_wavefronts', - 'TA_PERF_SEL_flat_coalesceable_wavefronts', - 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', - 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', - 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', - 'TA_PERF_SEL_image_atomic_wavefronts', - 'TA_PERF_SEL_image_read_wavefronts', - 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', - 'TA_PERF_SEL_image_write_wavefronts', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', - 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', - 'TA_PERF_SEL_mip_2_cycle_pixels', - 'TA_PERF_SEL_mipmap_invalid_samples', - 'TA_PERF_SEL_mipmap_lod_0_samples', - 'TA_PERF_SEL_mipmap_lod_10_samples', - 'TA_PERF_SEL_mipmap_lod_11_samples', - 'TA_PERF_SEL_mipmap_lod_12_samples', - 'TA_PERF_SEL_mipmap_lod_13_samples', - 'TA_PERF_SEL_mipmap_lod_14_samples', - 'TA_PERF_SEL_mipmap_lod_1_samples', - 'TA_PERF_SEL_mipmap_lod_2_samples', - 'TA_PERF_SEL_mipmap_lod_3_samples', - 'TA_PERF_SEL_mipmap_lod_4_samples', - 'TA_PERF_SEL_mipmap_lod_5_samples', - 'TA_PERF_SEL_mipmap_lod_6_samples', - 'TA_PERF_SEL_mipmap_lod_7_samples', - 'TA_PERF_SEL_mipmap_lod_8_samples', - 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', - 'TA_PERF_SEL_sh_fifo_addr_busy', - 'TA_PERF_SEL_sh_fifo_addr_cycles', - 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', - 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', - 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', - 'TA_PERF_SEL_sh_fifo_data_busy', - 'TA_PERF_SEL_sh_fifo_data_cycles', - 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', - 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', - 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', - 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', - 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', - 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', - 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', - 'TA_PERF_SEL_ta_fa_data_state_cycles', - 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vol_1_cycle_pixels', - 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', - 'TA_PERF_SEL_write_path_busy', - 'TA_PERF_SEL_write_path_input_cycles', - 'TA_PERF_SEL_write_path_output_cycles', - 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', - 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', - 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', - 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', - 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', - 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', - 'TCA_PERF_SEL', 'TCA_PERF_SEL_BUSY', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', - 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', - 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', 'TCA_PERF_SEL_CYCLE', - 'TCA_PERF_SEL_FORCED_HOLE_TCC0', 'TCA_PERF_SEL_FORCED_HOLE_TCC1', - 'TCA_PERF_SEL_FORCED_HOLE_TCC2', 'TCA_PERF_SEL_FORCED_HOLE_TCC3', - 'TCA_PERF_SEL_FORCED_HOLE_TCC4', 'TCA_PERF_SEL_FORCED_HOLE_TCC5', - 'TCA_PERF_SEL_FORCED_HOLE_TCC6', 'TCA_PERF_SEL_FORCED_HOLE_TCC7', - 'TCA_PERF_SEL_NONE', 'TCA_PERF_SEL_REQ_TCC0', - 'TCA_PERF_SEL_REQ_TCC1', 'TCA_PERF_SEL_REQ_TCC2', - 'TCA_PERF_SEL_REQ_TCC3', 'TCA_PERF_SEL_REQ_TCC4', - 'TCA_PERF_SEL_REQ_TCC5', 'TCA_PERF_SEL_REQ_TCC6', - 'TCA_PERF_SEL_REQ_TCC7', 'TCC_CACHE_POLICIES', - 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_PERF_SEL', - 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', - 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', - 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', - 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', 'TCC_PERF_SEL_ATOMIC', - 'TCC_PERF_SEL_BUBBLE', 'TCC_PERF_SEL_BUSY', - 'TCC_PERF_SEL_CC_PHYSICAL_REQ', 'TCC_PERF_SEL_CLIENT0_REQ', - 'TCC_PERF_SEL_CLIENT100_REQ', 'TCC_PERF_SEL_CLIENT101_REQ', - 'TCC_PERF_SEL_CLIENT102_REQ', 'TCC_PERF_SEL_CLIENT103_REQ', - 'TCC_PERF_SEL_CLIENT104_REQ', 'TCC_PERF_SEL_CLIENT105_REQ', - 'TCC_PERF_SEL_CLIENT106_REQ', 'TCC_PERF_SEL_CLIENT107_REQ', - 'TCC_PERF_SEL_CLIENT108_REQ', 'TCC_PERF_SEL_CLIENT109_REQ', - 'TCC_PERF_SEL_CLIENT10_REQ', 'TCC_PERF_SEL_CLIENT110_REQ', - 'TCC_PERF_SEL_CLIENT111_REQ', 'TCC_PERF_SEL_CLIENT112_REQ', - 'TCC_PERF_SEL_CLIENT113_REQ', 'TCC_PERF_SEL_CLIENT114_REQ', - 'TCC_PERF_SEL_CLIENT115_REQ', 'TCC_PERF_SEL_CLIENT116_REQ', - 'TCC_PERF_SEL_CLIENT117_REQ', 'TCC_PERF_SEL_CLIENT118_REQ', - 'TCC_PERF_SEL_CLIENT119_REQ', 'TCC_PERF_SEL_CLIENT11_REQ', - 'TCC_PERF_SEL_CLIENT120_REQ', 'TCC_PERF_SEL_CLIENT121_REQ', - 'TCC_PERF_SEL_CLIENT122_REQ', 'TCC_PERF_SEL_CLIENT123_REQ', - 'TCC_PERF_SEL_CLIENT124_REQ', 'TCC_PERF_SEL_CLIENT125_REQ', - 'TCC_PERF_SEL_CLIENT126_REQ', 'TCC_PERF_SEL_CLIENT127_REQ', - 'TCC_PERF_SEL_CLIENT12_REQ', 'TCC_PERF_SEL_CLIENT13_REQ', - 'TCC_PERF_SEL_CLIENT14_REQ', 'TCC_PERF_SEL_CLIENT15_REQ', - 'TCC_PERF_SEL_CLIENT16_REQ', 'TCC_PERF_SEL_CLIENT17_REQ', - 'TCC_PERF_SEL_CLIENT18_REQ', 'TCC_PERF_SEL_CLIENT19_REQ', - 'TCC_PERF_SEL_CLIENT1_REQ', 'TCC_PERF_SEL_CLIENT20_REQ', - 'TCC_PERF_SEL_CLIENT21_REQ', 'TCC_PERF_SEL_CLIENT22_REQ', - 'TCC_PERF_SEL_CLIENT23_REQ', 'TCC_PERF_SEL_CLIENT24_REQ', - 'TCC_PERF_SEL_CLIENT25_REQ', 'TCC_PERF_SEL_CLIENT26_REQ', - 'TCC_PERF_SEL_CLIENT27_REQ', 'TCC_PERF_SEL_CLIENT28_REQ', - 'TCC_PERF_SEL_CLIENT29_REQ', 'TCC_PERF_SEL_CLIENT2_REQ', - 'TCC_PERF_SEL_CLIENT30_REQ', 'TCC_PERF_SEL_CLIENT31_REQ', - 'TCC_PERF_SEL_CLIENT32_REQ', 'TCC_PERF_SEL_CLIENT33_REQ', - 'TCC_PERF_SEL_CLIENT34_REQ', 'TCC_PERF_SEL_CLIENT35_REQ', - 'TCC_PERF_SEL_CLIENT36_REQ', 'TCC_PERF_SEL_CLIENT37_REQ', - 'TCC_PERF_SEL_CLIENT38_REQ', 'TCC_PERF_SEL_CLIENT39_REQ', - 'TCC_PERF_SEL_CLIENT3_REQ', 'TCC_PERF_SEL_CLIENT40_REQ', - 'TCC_PERF_SEL_CLIENT41_REQ', 'TCC_PERF_SEL_CLIENT42_REQ', - 'TCC_PERF_SEL_CLIENT43_REQ', 'TCC_PERF_SEL_CLIENT44_REQ', - 'TCC_PERF_SEL_CLIENT45_REQ', 'TCC_PERF_SEL_CLIENT46_REQ', - 'TCC_PERF_SEL_CLIENT47_REQ', 'TCC_PERF_SEL_CLIENT48_REQ', - 'TCC_PERF_SEL_CLIENT49_REQ', 'TCC_PERF_SEL_CLIENT4_REQ', - 'TCC_PERF_SEL_CLIENT50_REQ', 'TCC_PERF_SEL_CLIENT51_REQ', - 'TCC_PERF_SEL_CLIENT52_REQ', 'TCC_PERF_SEL_CLIENT53_REQ', - 'TCC_PERF_SEL_CLIENT54_REQ', 'TCC_PERF_SEL_CLIENT55_REQ', - 'TCC_PERF_SEL_CLIENT56_REQ', 'TCC_PERF_SEL_CLIENT57_REQ', - 'TCC_PERF_SEL_CLIENT58_REQ', 'TCC_PERF_SEL_CLIENT59_REQ', - 'TCC_PERF_SEL_CLIENT5_REQ', 'TCC_PERF_SEL_CLIENT60_REQ', - 'TCC_PERF_SEL_CLIENT61_REQ', 'TCC_PERF_SEL_CLIENT62_REQ', - 'TCC_PERF_SEL_CLIENT63_REQ', 'TCC_PERF_SEL_CLIENT64_REQ', - 'TCC_PERF_SEL_CLIENT65_REQ', 'TCC_PERF_SEL_CLIENT66_REQ', - 'TCC_PERF_SEL_CLIENT67_REQ', 'TCC_PERF_SEL_CLIENT68_REQ', - 'TCC_PERF_SEL_CLIENT69_REQ', 'TCC_PERF_SEL_CLIENT6_REQ', - 'TCC_PERF_SEL_CLIENT70_REQ', 'TCC_PERF_SEL_CLIENT71_REQ', - 'TCC_PERF_SEL_CLIENT72_REQ', 'TCC_PERF_SEL_CLIENT73_REQ', - 'TCC_PERF_SEL_CLIENT74_REQ', 'TCC_PERF_SEL_CLIENT75_REQ', - 'TCC_PERF_SEL_CLIENT76_REQ', 'TCC_PERF_SEL_CLIENT77_REQ', - 'TCC_PERF_SEL_CLIENT78_REQ', 'TCC_PERF_SEL_CLIENT79_REQ', - 'TCC_PERF_SEL_CLIENT7_REQ', 'TCC_PERF_SEL_CLIENT80_REQ', - 'TCC_PERF_SEL_CLIENT81_REQ', 'TCC_PERF_SEL_CLIENT82_REQ', - 'TCC_PERF_SEL_CLIENT83_REQ', 'TCC_PERF_SEL_CLIENT84_REQ', - 'TCC_PERF_SEL_CLIENT85_REQ', 'TCC_PERF_SEL_CLIENT86_REQ', - 'TCC_PERF_SEL_CLIENT87_REQ', 'TCC_PERF_SEL_CLIENT88_REQ', - 'TCC_PERF_SEL_CLIENT89_REQ', 'TCC_PERF_SEL_CLIENT8_REQ', - 'TCC_PERF_SEL_CLIENT90_REQ', 'TCC_PERF_SEL_CLIENT91_REQ', - 'TCC_PERF_SEL_CLIENT92_REQ', 'TCC_PERF_SEL_CLIENT93_REQ', - 'TCC_PERF_SEL_CLIENT94_REQ', 'TCC_PERF_SEL_CLIENT95_REQ', - 'TCC_PERF_SEL_CLIENT96_REQ', 'TCC_PERF_SEL_CLIENT97_REQ', - 'TCC_PERF_SEL_CLIENT98_REQ', 'TCC_PERF_SEL_CLIENT99_REQ', - 'TCC_PERF_SEL_CLIENT9_REQ', 'TCC_PERF_SEL_COMPRESSED_0_REQ', - 'TCC_PERF_SEL_COMPRESSED_REQ', 'TCC_PERF_SEL_CYCLE', - 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'TCC_PERF_SEL_EA_ATOMIC', - 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', 'TCC_PERF_SEL_EA_RDREQ', - 'TCC_PERF_SEL_EA_RDREQ_32B', 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', - 'TCC_PERF_SEL_EA_RDREQ_LEVEL', - 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', 'TCC_PERF_SEL_EA_RD_MDC_32B', - 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', 'TCC_PERF_SEL_EA_WRREQ', - 'TCC_PERF_SEL_EA_WRREQ_64B', 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', - 'TCC_PERF_SEL_EA_WRREQ_LEVEL', - 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 'TCC_PERF_SEL_EA_WRREQ_STALL', 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', - 'TCC_PERF_SEL_EXE_REQ', 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', - 'TCC_PERF_SEL_HIT', 'TCC_PERF_SEL_HOLE_FIFO_FULL', - 'TCC_PERF_SEL_HOLE_LEVEL', 'TCC_PERF_SEL_IB_MDC_STALL', - 'TCC_PERF_SEL_IB_REQ', 'TCC_PERF_SEL_IB_STALL', - 'TCC_PERF_SEL_IB_TAG_STALL', 'TCC_PERF_SEL_LATENCY_FIFO_FULL', - 'TCC_PERF_SEL_MDC_LEVEL', 'TCC_PERF_SEL_MDC_REQ', - 'TCC_PERF_SEL_MDC_SECTOR_HIT', 'TCC_PERF_SEL_MDC_SECTOR_MISS', - 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 'TCC_PERF_SEL_MDC_TAG_HIT', - 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 'TCC_PERF_SEL_MDC_TAG_STALL', - 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 'TCC_PERF_SEL_METADATA_REQ', 'TCC_PERF_SEL_MISS', - 'TCC_PERF_SEL_NC_VIRTUAL_REQ', 'TCC_PERF_SEL_NONE', - 'TCC_PERF_SEL_NORMAL_EVICT', 'TCC_PERF_SEL_NORMAL_WRITEBACK', - 'TCC_PERF_SEL_PROBE', 'TCC_PERF_SEL_PROBE_ALL', - 'TCC_PERF_SEL_PROBE_EVICT', 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', - 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 'TCC_PERF_SEL_READ', 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', 'TCC_PERF_SEL_REQ', - 'TCC_PERF_SEL_RETURN_ACK', 'TCC_PERF_SEL_RETURN_ACK_HOLE', - 'TCC_PERF_SEL_RETURN_DATA', 'TCC_PERF_SEL_RETURN_HOLE', - 'TCC_PERF_SEL_SECTOR_HIT', 'TCC_PERF_SEL_SRC_FIFO_FULL', - 'TCC_PERF_SEL_STREAMING_REQ', - 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', - 'TCC_PERF_SEL_TAG_PROBE_STALL', 'TCC_PERF_SEL_TAG_STALL', - 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 'TCC_PERF_SEL_TCA_LEVEL', 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', - 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', - 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', - 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', - 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', - 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', - 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', - 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', - 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', - 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', - 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', - 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', - 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', - 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', - 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', - 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', - 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', - 'TCC_PERF_SEL_TC_OP_WBINVL2_START', - 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', - 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', - 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', - 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', - 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', - 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', - 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', - 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', - 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', - 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', - 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', - 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 'TCC_PERF_SEL_UC_VIRTUAL_REQ', 'TCC_PERF_SEL_WRITE', - 'TCC_PERF_SEL_WRITEBACK', 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', - 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', - 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', - 'TCP_CACHE_STORE_POLICY_WT_EVICT', - 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', - 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', - 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', - 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', - 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', - 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', - 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', - 'TCP_PERF_SEL_ARR_1D_THICK', 'TCP_PERF_SEL_ARR_1D_THIN1', - 'TCP_PERF_SEL_ARR_2D_THICK', 'TCP_PERF_SEL_ARR_2D_THIN1', - 'TCP_PERF_SEL_ARR_2D_XTHICK', 'TCP_PERF_SEL_ARR_3D_THICK', - 'TCP_PERF_SEL_ARR_3D_THIN1', 'TCP_PERF_SEL_ARR_3D_XTHICK', - 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', - 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', - 'TCP_PERF_SEL_ARR_PRT_2D_THICK', 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', - 'TCP_PERF_SEL_ARR_PRT_3D_THICK', 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', - 'TCP_PERF_SEL_ARR_PRT_THICK', 'TCP_PERF_SEL_ARR_PRT_THIN1', - 'TCP_PERF_SEL_ATC', - 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', - 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', - 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', - 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', - 'TCP_PERF_SEL_BUF_READ_FMT_16', 'TCP_PERF_SEL_BUF_READ_FMT_32', - 'TCP_PERF_SEL_BUF_READ_FMT_8', 'TCP_PERF_SEL_BUF_WRITE_FMT_16', - 'TCP_PERF_SEL_BUF_WRITE_FMT_32', 'TCP_PERF_SEL_BUF_WRITE_FMT_8', - 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', - 'TCP_PERF_SEL_CP_TCP_INVALIDATE', - 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', - 'TCP_PERF_SEL_DEPTH_MICROTILING', 'TCP_PERF_SEL_DIM_1D', - 'TCP_PERF_SEL_DIM_1D_ARRAY', 'TCP_PERF_SEL_DIM_2D', - 'TCP_PERF_SEL_DIM_2D_ARRAY', 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', - 'TCP_PERF_SEL_DIM_2D_MSAA', 'TCP_PERF_SEL_DIM_3D', - 'TCP_PERF_SEL_DIM_CUBE_ARRAY', 'TCP_PERF_SEL_DISPLAY_MICROTILING', - 'TCP_PERF_SEL_GATE_EN1', 'TCP_PERF_SEL_GATE_EN2', - 'TCP_PERF_SEL_HOLE_READ_STALL', - 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', - 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', - 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', - 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', - 'TCP_PERF_SEL_IMG_READ_FMT_1', - 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', - 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', - 'TCP_PERF_SEL_IMG_READ_FMT_16', - 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', - 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', - 'TCP_PERF_SEL_IMG_READ_FMT_32', - 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', - 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', - 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', - 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', - 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', - 'TCP_PERF_SEL_IMG_READ_FMT_8', - 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', - 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', - 'TCP_PERF_SEL_IMG_READ_FMT_96', 'TCP_PERF_SEL_IMG_READ_FMT_BC1', - 'TCP_PERF_SEL_IMG_READ_FMT_BC2', 'TCP_PERF_SEL_IMG_READ_FMT_BC3', - 'TCP_PERF_SEL_IMG_READ_FMT_BC4', 'TCP_PERF_SEL_IMG_READ_FMT_BC5', - 'TCP_PERF_SEL_IMG_READ_FMT_BC6', 'TCP_PERF_SEL_IMG_READ_FMT_BC7', - 'TCP_PERF_SEL_IMG_READ_FMT_D16', 'TCP_PERF_SEL_IMG_READ_FMT_D32', - 'TCP_PERF_SEL_IMG_READ_FMT_D8', - 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', - 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', - 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', - 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', - 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', - 'TCP_PERF_SEL_IMG_READ_FMT_I16', 'TCP_PERF_SEL_IMG_READ_FMT_I32', - 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', - 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', - 'TCP_PERF_SEL_IMG_READ_FMT_I8', 'TCP_PERF_SEL_IMG_WRITE_FMT_128', - 'TCP_PERF_SEL_IMG_WRITE_FMT_16', - 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', - 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', - 'TCP_PERF_SEL_IMG_WRITE_FMT_32', 'TCP_PERF_SEL_IMG_WRITE_FMT_64', - 'TCP_PERF_SEL_IMG_WRITE_FMT_8', - 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', - 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', - 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', - 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', - 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', - 'TCP_PERF_SEL_LOD_STALL_CYCLES', - 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', - 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', - 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', - 'TCP_PERF_SEL_RESERVED_154', 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', - 'TCP_PERF_SEL_ROTATED_MICROTILING', 'TCP_PERF_SEL_SHOOTDOWN', - 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', 'TCP_PERF_SEL_TAGRAM0_REQ', - 'TCP_PERF_SEL_TAGRAM1_REQ', 'TCP_PERF_SEL_TAGRAM2_REQ', - 'TCP_PERF_SEL_TAGRAM3_REQ', - 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', - 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', - 'TCP_PERF_SEL_TA_TCP_STATE_READ', 'TCP_PERF_SEL_TCC_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', - 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', - 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', - 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', - 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', - 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', - 'TCP_PERF_SEL_TCC_DCC_REQ', 'TCP_PERF_SEL_TCC_LRU_REQ', - 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', - 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', - 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_NC_READ_REQ', - 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', 'TCP_PERF_SEL_TCC_NON_READ_REQ', - 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', 'TCP_PERF_SEL_TCC_READ_REQ', - 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', 'TCP_PERF_SEL_TCC_REQ', - 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', - 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', - 'TCP_PERF_SEL_TCC_WRITE_REQ', - 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', - 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', - 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', - 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', - 'TCP_PERF_SEL_TCR_RDRET_STALL', - 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', - 'TCP_PERF_SEL_TC_TA_XNACK_STALL', - 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', - 'TCP_PERF_SEL_THICK_MICROTILING', 'TCP_PERF_SEL_THIN_MICROTILING', - 'TCP_PERF_SEL_TOTAL_ACCESSES', - 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', - 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', - 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', - 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', - 'TCP_PERF_SEL_TOTAL_LOCAL_READ', 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', - 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', - 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', - 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', - 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', - 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', - 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', - 'TCP_PERF_SEL_TOTAL_WRITE', - 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', - 'TCP_PERF_SEL_UNALIGNED', 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', - 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', - 'TCP_PERF_SEL_UTCL1_REQUEST', - 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', - 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', - 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', - 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', - 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', - 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', - 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', - 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', 'TCP_PERF_SEL_VOLATILE', - 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', - 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', - 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', - 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', - 'TC_CHUB_REQ_CREDITS', 'TC_CHUB_REQ_CREDITS_ENUM', 'TC_EA_CID', - 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', - 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', - 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', - 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', - 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', - 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', - 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', - 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', - 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', - 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', - 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', - 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', - 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', - 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', - 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', - 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', - 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', - 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', - 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', - 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', - 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', - 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', - 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', - 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', - 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', - 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', - 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', - 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', - 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', - 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', - 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', - 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', - 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', - 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', - 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', - 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', - 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', - 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', - 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', - 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', - 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', - 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', - 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', - 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', - 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', - 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', - 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', - 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', - 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', - 'TD_PERF_SEL_RESERVED_14', 'TD_PERF_SEL_RESERVED_18', - 'TD_PERF_SEL_RESERVED_19', 'TD_PERF_SEL_RESERVED_39', - 'TD_PERF_SEL_RESERVED_43', 'TD_PERF_SEL_RESERVED_44', - 'TD_PERF_SEL_addresscmd_poison', 'TD_PERF_SEL_atomic_wavefront', - 'TD_PERF_SEL_bypass_filter_wavefront', - 'TD_PERF_SEL_coalescable_wavefront', - 'TD_PERF_SEL_coalesced_phase', 'TD_PERF_SEL_constant_state_full', - 'TD_PERF_SEL_consume_gds_traffic', 'TD_PERF_SEL_d16_data_packed', - 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', - 'TD_PERF_SEL_eight_phase_wavefront', - 'TD_PERF_SEL_four_phase_forward_wavefront', - 'TD_PERF_SEL_four_phase_wavefront', - 'TD_PERF_SEL_gather4_wavefront', - 'TD_PERF_SEL_gather4h_packed_wavefront', - 'TD_PERF_SEL_gather4h_wavefront', - 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_gds_stall', - 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_ldfptr_wavefront', - 'TD_PERF_SEL_lerp_busy', 'TD_PERF_SEL_load_wavefront', - 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', - 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', - 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', - 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', - 'TD_PERF_SEL_min_max_filter_wavefront', 'TD_PERF_SEL_nack', - 'TD_PERF_SEL_none', 'TD_PERF_SEL_null_cycle_output', - 'TD_PERF_SEL_opaque_black_border', 'TD_PERF_SEL_output_busy', - 'TD_PERF_SEL_output_fifo_full', 'TD_PERF_SEL_pc_stall', - 'TD_PERF_SEL_reg_sclk_vld', 'TD_PERF_SEL_sample_c_wavefront', - 'TD_PERF_SEL_sample_state_full', - 'TD_PERF_SEL_sixteen_phase_wavefront', - 'TD_PERF_SEL_start_cycle_0', 'TD_PERF_SEL_start_cycle_1', - 'TD_PERF_SEL_start_cycle_2', 'TD_PERF_SEL_start_cycle_3', - 'TD_PERF_SEL_store_wavefront', 'TD_PERF_SEL_tc_stall', - 'TD_PERF_SEL_tc_td_fifo_full', 'TD_PERF_SEL_td_busy', - 'TD_PERF_SEL_td_sp_traffic', - 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', - 'TD_PERF_SEL_user_defined_border', 'TD_PERF_SEL_white_border', - 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', - 'TESS_TRIANGLE', 'TEX_BORDER_COLOR_TYPE', - 'TEX_BorderColor_OpaqueBlack', 'TEX_BorderColor_OpaqueWhite', - 'TEX_BorderColor_Register', 'TEX_BorderColor_TransparentBlack', - 'TEX_CHROMA_KEY', 'TEX_CLAMP', 'TEX_COORD_TYPE', - 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', - 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', - 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', - 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', - 'TEX_Clamp_MirrorOnceHalfToBorder', - 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', - 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', - 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', - 'TEX_DIM', 'TEX_DepthCompareFunction_Always', - 'TEX_DepthCompareFunction_Equal', - 'TEX_DepthCompareFunction_Greater', - 'TEX_DepthCompareFunction_GreaterEqual', - 'TEX_DepthCompareFunction_Less', - 'TEX_DepthCompareFunction_LessEqual', - 'TEX_DepthCompareFunction_Never', - 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', - 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', - 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', - 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', - 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', - 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', - 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', - 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', - 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', - 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', - 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', - 'TEX_MipFilter_None', 'TEX_MipFilter_Point', - 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', - 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', - 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', - 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', - 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', - 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', - 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', - 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', - 'THREAD_TRACE_FINISH', 'THREAD_TRACE_FLUSH', - 'THREAD_TRACE_MARKER', 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', - 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', - 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', - 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', - 'TMDS_CTL0_DATA_MODULATION_BIT1', - 'TMDS_CTL0_DATA_MODULATION_BIT2', - 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', - 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', - 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', - 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', - 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', - 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', - 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', - 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', - 'TMDS_CTL1_DATA_MODULATION_BIT0', - 'TMDS_CTL1_DATA_MODULATION_BIT1', - 'TMDS_CTL1_DATA_MODULATION_BIT2', - 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', - 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', - 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', - 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', - 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', - 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', - 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', - 'TMDS_CTL2_DATA_MODULATION_BIT0', - 'TMDS_CTL2_DATA_MODULATION_BIT1', - 'TMDS_CTL2_DATA_MODULATION_BIT2', - 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', - 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', - 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', - 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', - 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', - 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', - 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', - 'TMDS_CTL3_DATA_MODULATION_BIT0', - 'TMDS_CTL3_DATA_MODULATION_BIT1', - 'TMDS_CTL3_DATA_MODULATION_BIT2', - 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', - 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', - 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', - 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', - 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', - 'TMDS_CTL3_PATTERN_OUT_ENABLE', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', - 'TMDS_DVO_MUX_SELECT', 'TMDS_DVO_MUX_SELECT_B', - 'TMDS_DVO_MUX_SELECT_G', 'TMDS_DVO_MUX_SELECT_R', - 'TMDS_DVO_MUX_SELECT_RESERVED', - 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', 'TMDS_PIXEL_ENCODING', - 'TMDS_PIXEL_ENCODING_422', 'TMDS_PIXEL_ENCODING_444_OR_420', - 'TMDS_REG_TEST_OUTPUTA_CNTLA', 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', - 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', - 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', - 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', - 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', - 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', - 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', - 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', - 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', - 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', - 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', - 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', - 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', - 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', - 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', - 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', - 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', - 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', - 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', - 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', - 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', - 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', - 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', - 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', - 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', - 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', - 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', - 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', - 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', - 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', - 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', - 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', - 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', - 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', - 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', - 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', - 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', - 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', - 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', - 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', - 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', - 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', - 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', - 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', - 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', - 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', - 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', - 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', - 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', - 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', - 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', - 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', - 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', - 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', - 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', - 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', - 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', - 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', - 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', - 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', - 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', - 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', - 'TVX_Type_ValidVertexBuffer', 'TileSplit', 'TileType', - 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', 'UNDEF', - 'UNP_ADDR_SURF_MACRO_ASPECT_1', 'UNP_ADDR_SURF_MACRO_ASPECT_2', - 'UNP_ADDR_SURF_MACRO_ASPECT_4', 'UNP_ADDR_SURF_MACRO_ASPECT_8', - 'UNP_ADDR_SURF_TILE_SPLIT_128B', 'UNP_ADDR_SURF_TILE_SPLIT_1KB', - 'UNP_ADDR_SURF_TILE_SPLIT_256B', 'UNP_ADDR_SURF_TILE_SPLIT_2KB', - 'UNP_ADDR_SURF_TILE_SPLIT_4KB', 'UNP_ADDR_SURF_TILE_SPLIT_512B', - 'UNP_ADDR_SURF_TILE_SPLIT_64B', 'UNP_BUFFER_MODE', - 'UNP_BUFFER_MODE_LUMA', 'UNP_BUFFER_MODE_LUMA_CHROMA', - 'UNP_CRC_LINE_SEL', 'UNP_CRC_LINE_SEL_EVEN_ONLY', - 'UNP_CRC_LINE_SEL_ODD_EVEN', 'UNP_CRC_LINE_SEL_ODD_ONLY', - 'UNP_CRC_LINE_SEL_RESERVED', 'UNP_CRC_SOURCE_SEL', - 'UNP_CRC_SOURCE_SEL_LOWER16', 'UNP_CRC_SOURCE_SEL_LOWER32', - 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', 'UNP_CRC_SOURCE_SEL_RESERVED', - 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', 'UNP_GRPH_16BPP', - 'UNP_GRPH_32BPP', 'UNP_GRPH_8BPP', - 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE', - 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', - 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', - 'UNP_GRPH_ADDR_SURF_16_BANK', 'UNP_GRPH_ADDR_SURF_2_BANK', - 'UNP_GRPH_ADDR_SURF_4_BANK', 'UNP_GRPH_ADDR_SURF_8_BANK', - 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', - 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', - 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', - 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', - 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', - 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', - 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', - 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', 'UNP_GRPH_BANK_HEIGHT', - 'UNP_GRPH_BANK_WIDTH', 'UNP_GRPH_BLUE_CROSSBAR', - 'UNP_GRPH_BLUE_CROSSBAR_A', 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', - 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', - 'UNP_GRPH_COLOR_EXPANSION_MODE', 'UNP_GRPH_DEPTH', - 'UNP_GRPH_DISABLED', 'UNP_GRPH_DYNAMIC_EXPANSION', 'UNP_GRPH_EN', - 'UNP_GRPH_ENABLED', 'UNP_GRPH_ENDIAN_SWAP', - 'UNP_GRPH_ENDIAN_SWAP_8IN16', 'UNP_GRPH_ENDIAN_SWAP_8IN32', - 'UNP_GRPH_ENDIAN_SWAP_8IN43', 'UNP_GRPH_ENDIAN_SWAP_NONE', - 'UNP_GRPH_GREEN_CROSSBAR', 'UNP_GRPH_MACRO_TILE_ASPECT', - 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', - 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', - 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', - 'UNP_GRPH_MODE_UPDATE_LOCKG', 'UNP_GRPH_NUM_BANKS', - 'UNP_GRPH_RED_CROSSBAR', 'UNP_GRPH_RED_CROSSBAR_A', - 'UNP_GRPH_RED_CROSSBAR_B_Cb', 'UNP_GRPH_RED_CROSSBAR_G_Y', - 'UNP_GRPH_RED_CROSSBAR_R_Cr', - 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', - 'UNP_GRPH_STACK_INTERLACE_FLIP_EN', - 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', - 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE', - 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', - 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', - 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', - 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', - 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', 'UNP_GRPH_STEREOSYNC_FLIP_EN', - 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', - 'UNP_GRPH_STEREOSYNC_FLIP_MODE', - 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', - 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', - 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', - 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', - 'UNP_GRPH_STEREOSYNC_SELECT_DIS', - 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE', - 'UNP_GRPH_STEREOSYNC_SELECT_EN', - 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', - 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', - 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', - 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', - 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', - 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', 'UNP_GRPH_TILE_SPLIT', - 'UNP_GRPH_UPDATE_LOCK_0', 'UNP_GRPH_UPDATE_LOCK_1', - 'UNP_GRPH_ZERO_EXPANSION', 'UNP_PIXEL_DROP', 'UNP_PIXEL_DROPPING', - 'UNP_PIXEL_NO_DROP', 'UNP_ROTATION_ANGLE', 'UNP_ROTATION_ANGLE_0', - 'UNP_ROTATION_ANGLE_0m', 'UNP_ROTATION_ANGLE_180', - 'UNP_ROTATION_ANGLE_180m', 'UNP_ROTATION_ANGLE_270', - 'UNP_ROTATION_ANGLE_270m', 'UNP_ROTATION_ANGLE_90', - 'UNP_ROTATION_ANGLE_90m', 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', - 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', - 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', - 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', 'UNP_VIDEO_FORMAT', - 'UNP_VIDEO_FORMAT0', 'UNP_VIDEO_FORMAT1', - 'UNP_VIDEO_FORMAT_YUV420_YCbCr', 'UNP_VIDEO_FORMAT_YUV420_YCrCb', - 'UNP_VIDEO_FORMAT_YUV422_CbY', 'UNP_VIDEO_FORMAT_YUV422_CrY', - 'UNP_VIDEO_FORMAT_YUV422_YCb', 'UNP_VIDEO_FORMAT_YUV422_YCr', - 'UPDATE_LOCKED', 'UPDATE_UNLOCKED', 'UTCL1FaultType', - 'UTCL1RequestType', 'UTCL1_TYPE_BYPASS', 'UTCL1_TYPE_NORMAL', - 'UTCL1_TYPE_SHOOTDOWN', 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', - 'UTCL1_XNACK_RETRY', 'UTCL1_XNACK_SUCCESS', 'VC_AND_TC', - 'VC_ONLY', 'VGT_CACHE_INVALID_MODE', 'VGT_DIST_MODE', - 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', - 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', - 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', - 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', - 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', - 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', - 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', - 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', - 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', - 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', - 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', - 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', - 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', - 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', - 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', - 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', - 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', - 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', - 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', - 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', - 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', - 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', - 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PASSTHRU', - 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', - 'VGT_OUTPATH_TESS_EN', 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', - 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', - 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', - 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', - 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', 'VGT_PERFCOUNT_SELECT', - 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', - 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', - 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', - 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', - 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', - 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', - 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', - 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', - 'VMID_SZ', 'VS_PARTIAL_FLUSH', 'VS_STAGE_COPY_SHADER', - 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTX_CLAMP', - 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', - 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', - 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', - 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', - 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', - 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', - 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', - 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', - 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', - 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', - 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', - 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', - 'WD_PERFCOUNT_SELECT', 'XDMA_LOCAL_SW_MODE_SW_256B_D', - 'XDMA_LOCAL_SW_MODE_SW_64KB_D', 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', - 'XDMA_MSTR_ALPHA_POSITION_15_8', 'XDMA_MSTR_ALPHA_POSITION_23_16', - 'XDMA_MSTR_ALPHA_POSITION_31_24', 'XDMA_MSTR_ALPHA_POSITION_7_0', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', - 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', - 'XDMA_SLV_ALPHA_POSITION_15_8', 'XDMA_SLV_ALPHA_POSITION_23_16', - 'XDMA_SLV_ALPHA_POSITION_31_24', 'XDMA_SLV_ALPHA_POSITION_7_0', - 'XTAL_REF_CLOCK_SOURCE_SEL', 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', - 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', - 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'ZFormat', 'ZLimitSumm', - 'ZModeForce', 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', - 'ZPASS_PIXELS', 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', - 'Z_24', 'Z_32_FLOAT', 'Z_INVALID', 'Z_SAMPLE_CENTER', - 'Z_SAMPLE_CENTROID', 'ZpassControl', '_vega10_ENUM_HEADER', - 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', 'ia_perf_MC_LAT_BIN_0', - 'ia_perf_MC_LAT_BIN_1', 'ia_perf_MC_LAT_BIN_2', - 'ia_perf_MC_LAT_BIN_3', 'ia_perf_MC_LAT_BIN_4', - 'ia_perf_MC_LAT_BIN_5', 'ia_perf_MC_LAT_BIN_6', - 'ia_perf_MC_LAT_BIN_7', 'ia_perf_RESERVED1', 'ia_perf_RESERVED2', - 'ia_perf_RESERVED3', 'ia_perf_RESERVED4', 'ia_perf_RESERVED5', - 'ia_perf_RESERVED6', 'ia_perf_RESERVED7', - 'ia_perf_dma_data_fifo_full', 'ia_perf_ia_busy', - 'ia_perf_ia_dma_return', 'ia_perf_ia_sclk_core_vld_event', - 'ia_perf_ia_sclk_reg_vld_event', 'ia_perf_ia_stalled', - 'ia_perf_shift_starved_pipe0_event', - 'ia_perf_shift_starved_pipe1_event', 'vgt_perf_VGT_PA_CLIPP_EOP', - 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', - 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', - 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', 'vgt_perf_VGT_PA_CLIPP_SEND', - 'vgt_perf_VGT_PA_CLIPP_STALLED', - 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', - 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', - 'vgt_perf_VGT_PA_CLIPP_STATIC', 'vgt_perf_VGT_PA_CLIPS_SEND', - 'vgt_perf_VGT_PA_CLIPS_STALLED', - 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', - 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', - 'vgt_perf_VGT_PA_CLIPS_STATIC', 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', - 'vgt_perf_VGT_PA_CLIPV_SEND', 'vgt_perf_VGT_PA_CLIPV_STALLED', - 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', - 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', - 'vgt_perf_VGT_PA_CLIPV_STATIC', - 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', - 'vgt_perf_VGT_SPI_ESTHREAD_SEND', 'vgt_perf_VGT_SPI_ESVERT_EOV', - 'vgt_perf_VGT_SPI_ESVERT_STALLED', - 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', - 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', - 'vgt_perf_VGT_SPI_ESVERT_STATIC', 'vgt_perf_VGT_SPI_ESVERT_VALID', - 'vgt_perf_VGT_SPI_GSPRIM_CONT', 'vgt_perf_VGT_SPI_GSPRIM_EOV', - 'vgt_perf_VGT_SPI_GSPRIM_STALLED', - 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', - 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', - 'vgt_perf_VGT_SPI_GSPRIM_STATIC', 'vgt_perf_VGT_SPI_GSPRIM_VALID', - 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', - 'vgt_perf_VGT_SPI_GSTHREAD_SEND', 'vgt_perf_VGT_SPI_HSVERT_EOV', - 'vgt_perf_VGT_SPI_HSVERT_STALLED', - 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', - 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', - 'vgt_perf_VGT_SPI_HSVERT_STATIC', 'vgt_perf_VGT_SPI_HSVERT_VALID', - 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', - 'vgt_perf_VGT_SPI_HSWAVE_SEND', 'vgt_perf_VGT_SPI_LSVERT_EOV', - 'vgt_perf_VGT_SPI_LSVERT_STALLED', - 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', - 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', - 'vgt_perf_VGT_SPI_LSVERT_STATIC', 'vgt_perf_VGT_SPI_LSVERT_VALID', - 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', - 'vgt_perf_VGT_SPI_LSWAVE_SEND', - 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', - 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', - 'vgt_perf_VGT_SPI_VSTHREAD_SEND', 'vgt_perf_VGT_SPI_VSVERT_EOV', - 'vgt_perf_VGT_SPI_VSVERT_SEND', 'vgt_perf_VGT_SPI_VSVERT_STALLED', - 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', - 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', - 'vgt_perf_VGT_SPI_VSVERT_STATIC', 'vgt_perf_cm_reading_stalled', - 'vgt_perf_cm_stalled_by_gog', - 'vgt_perf_cm_stalled_by_gsfetch_done', - 'vgt_perf_counters_avail_stalled', - 'vgt_perf_cut_mem_flush_stalled', 'vgt_perf_ds_RESERVED', - 'vgt_perf_ds_cache_hits', 'vgt_perf_ds_prims', 'vgt_perf_es_done', - 'vgt_perf_es_done_latency', 'vgt_perf_es_flush', - 'vgt_perf_es_ring_high_water_mark', 'vgt_perf_es_thread_groups', - 'vgt_perf_esthread_stalled_es_rb_full', - 'vgt_perf_esthread_stalled_spi_bp', - 'vgt_perf_esvert_stalled_es_tbl', - 'vgt_perf_esvert_stalled_gs_event', - 'vgt_perf_esvert_stalled_gs_tbl', - 'vgt_perf_esvert_stalled_gsprim', 'vgt_perf_gog_busy', - 'vgt_perf_gog_out_indx_stalled', 'vgt_perf_gog_out_prim_stalled', - 'vgt_perf_gog_vs_tbl_stalled', 'vgt_perf_gs_cache_hits', - 'vgt_perf_gs_done', 'vgt_perf_gs_done_latency', - 'vgt_perf_gs_done_received', 'vgt_perf_gs_event_stall', - 'vgt_perf_gs_issue_rtr_stalled', - 'vgt_perf_gs_rb_space_avail_stalled', - 'vgt_perf_gs_ring_high_water_mark', - 'vgt_perf_gsprim_stalled_es_tbl', - 'vgt_perf_gsprim_stalled_esvert', - 'vgt_perf_gsprim_stalled_gs_event', - 'vgt_perf_gsprim_stalled_gs_tbl', 'vgt_perf_gsthread_stalled', - 'vgt_perf_hs_done', 'vgt_perf_hs_done_latency', - 'vgt_perf_hs_flush', 'vgt_perf_hs_input_stall', - 'vgt_perf_hs_interface_stall', 'vgt_perf_hs_tfm_stall', - 'vgt_perf_hs_tgs_active_high_water_mark', - 'vgt_perf_hs_thread_groups', 'vgt_perf_hs_tif_stall', - 'vgt_perf_hs_waiting_on_ls_done_stall', 'vgt_perf_hswave_stalled', - 'vgt_perf_ls_done', 'vgt_perf_ls_done_latency', - 'vgt_perf_ls_flush', 'vgt_perf_ls_thread_groups', - 'vgt_perf_pa_clipp_dealloc', 'vgt_perf_reused_es_indices', - 'vgt_perf_reused_vs_indices', 'vgt_perf_sclk_core_vld_event', - 'vgt_perf_sclk_gs_vld_event', 'vgt_perf_sclk_reg_vld_event', - 'vgt_perf_strmout_stalled', - 'vgt_perf_te11_con_starved_after_work', 'vgt_perf_te11_starved', - 'vgt_perf_total_cache_hits', 'vgt_perf_vgt_busy', - 'vgt_perf_vgt_gs_busy', 'vgt_perf_vgt_hs_busy', - 'vgt_perf_vgt_pa_clipp_eopg', - 'vgt_perf_vgt_pa_clipp_send_not_event', - 'vgt_perf_vgt_pa_clipp_starved_after_work', - 'vgt_perf_vgt_pa_clipp_valid_prim', 'vgt_perf_vgt_te11_busy', - 'vgt_perf_vs_cache_hits', 'vgt_perf_vs_conflicting_indices', - 'vgt_perf_vs_table_high_water_mark', 'vgt_perf_vs_thread_groups', - 'vgt_perf_vsfetch_done', 'vgt_perf_vsvert_api_send', - 'vgt_perf_vsvert_ds_send', 'vgt_perf_vsvert_work_received', - 'vgt_perf_wait_for_es_done_stalled', 'vgt_perf_waveid_stalled', - 'vgt_spi_vsvert_valid', 'wd_perf_RBIU_DI_FIFO_STALLED', - 'wd_perf_RBIU_DI_FIFO_STARVED', 'wd_perf_RBIU_DR_FIFO_STALLED', - 'wd_perf_RBIU_DR_FIFO_STARVED', - 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', 'wd_perf_hs_done_se0', - 'wd_perf_hs_done_se1', 'wd_perf_hs_done_se2', - 'wd_perf_hs_done_se3', 'wd_perf_inside_tf_bin_0', - 'wd_perf_inside_tf_bin_1', 'wd_perf_inside_tf_bin_2', - 'wd_perf_inside_tf_bin_3', 'wd_perf_inside_tf_bin_4', - 'wd_perf_inside_tf_bin_5', 'wd_perf_inside_tf_bin_6', - 'wd_perf_inside_tf_bin_7', 'wd_perf_inside_tf_bin_8', - 'wd_perf_null_patches', 'wd_perf_se0_hs_done_latency', - 'wd_perf_se1_hs_done_latency', 'wd_perf_se2_hs_done_latency', - 'wd_perf_se3_hs_done_latency', 'wd_perf_tfreq_lat_bin_0', - 'wd_perf_tfreq_lat_bin_1', 'wd_perf_tfreq_lat_bin_2', - 'wd_perf_tfreq_lat_bin_3', 'wd_perf_tfreq_lat_bin_4', - 'wd_perf_tfreq_lat_bin_5', 'wd_perf_tfreq_lat_bin_6', - 'wd_perf_tfreq_lat_bin_7', 'wd_perf_wd_busy', - 'wd_perf_wd_sclk_core_vld_event', - 'wd_perf_wd_sclk_input_vld_event', - 'wd_perf_wd_sclk_reg_vld_event', 'wd_perf_wd_stalled', - 'wd_starved_on_hs_done'] diff --git a/tinygrad/tinygrad/runtime/autogen/amd_gpu.py b/tinygrad/tinygrad/runtime/autogen/amd_gpu.py deleted file mode 100644 index 9ea5e6d9..00000000 --- a/tinygrad/tinygrad/runtime/autogen/amd_gpu.py +++ /dev/null @@ -1,89131 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -NVD_H = True # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_INDIRECT_BUFFER_END = 0x17 # macro -PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro -PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro -PACKET3_COPY_DW = 0x3B # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_CP_DMA = 0x41 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_SURFACE_SYNC = 0x43 # macro -PACKET3_ME_INITIALIZE = 0x44 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_EVENT_WRITE_EOP = 0x47 # macro -PACKET3_EVENT_WRITE_EOS = 0x48 # macro -PACKET3_RELEASE_MEM = 0x49 # macro -def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro - return ((x)<<0) -def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro -PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro -PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro -PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro -PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro -PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro -PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro -PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro -PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro -PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro -def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro - return ((x)<<25) -PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro -def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro - return ((x)<<29) -def PACKET3_RELEASE_MEM_INT_SEL(x): # macro - return ((x)<<24) -def PACKET3_RELEASE_MEM_DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_CONTEXT_REG_RMW = 0x51 # macro -PACKET3_GFX_CNTX_UPDATE = 0x52 # macro -PACKET3_BLK_CNTX_UPDATE = 0x53 # macro -PACKET3_INCR_UPDT_STATE = 0x55 # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro - return ((x)<<0) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro - return ((x)<<2) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro - return ((x)<<6) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro - return ((x)<<7) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro - return ((x)<<8) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro - return ((x)<<9) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro - return ((x)<<10) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro - return ((x)<<11) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro - return ((x)<<13) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro - return ((x)<<14) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro - return ((x)<<16) -PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro -PACKET3_REWIND = 0x59 # macro -PACKET3_INTERRUPT = 0x5A # macro -PACKET3_GEN_PDEPTE = 0x5B # macro -PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro -PACKET3_PRIME_UTCL2 = 0x5D # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro -PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro -PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro -PACKET3_SET_SH_REG_DI = 0x72 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro -PACKET3_GFX_PIPE_LOCK = 0x75 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro -PACKET3_FORWARD_HEADER = 0x7C # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro -PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro -PACKET3_DISPATCH_DRAW = 0x8D # macro -PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro -PACKET3_GET_LOD_STATS = 0x8E # macro -PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro -PACKET3_WAIT_REG_MEM64 = 0x93 # macro -PACKET3_COND_PREEMPT = 0x94 # macro -PACKET3_HDP_FLUSH = 0x95 # macro -PACKET3_COPY_DATA_RB = 0x96 # macro -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -PACKET3_AQL_PACKET = 0x99 # macro -PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro -PACKET3_SET_SH_REG_INDEX = 0x9B # macro -PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro -PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro -PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro -PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_PROCESS = 0xA1 # macro -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_LIST = 0xA5 # macro -PACKET3_MAP_PROCESS_VM = 0xA6 # macro -PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro -def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro - return ((x)<<0) -PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro -F32_MES_PM4_PACKETS_H = True # macro -uint32_t = True # macro -int32_t = True # macro -PM4_MES_HEADER_DEFINED = True # macro -PM4_MEC_RELEASE_MEM_DEFINED = True # macro -PM4_MEC_WRITE_DATA_DEFINED = True # macro -class union_PM4_MES_TYPE_3_HEADER(Union): - pass - -class struct_PM4_MES_TYPE_3_HEADER_0(Structure): - pass - -struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False -struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('opcode', ctypes.c_uint32, 8), - ('count', ctypes.c_uint32, 14), - ('type', ctypes.c_uint32, 2), -] - -union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False -union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) -union_PM4_MES_TYPE_3_HEADER._fields_ = [ - ('_0', struct_PM4_MES_TYPE_3_HEADER_0), - ('u32All', ctypes.c_uint32), -] - - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 5: 'event_index__mec_release_mem__end_of_pipe', - 6: 'event_index__mec_release_mem__shader_done', -} -event_index__mec_release_mem__end_of_pipe = 5 -event_index__mec_release_mem__shader_done = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'cache_policy__mec_release_mem__lru', - 1: 'cache_policy__mec_release_mem__stream', -} -cache_policy__mec_release_mem__lru = 0 -cache_policy__mec_release_mem__stream = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'pq_exe_status__mec_release_mem__default', - 1: 'pq_exe_status__mec_release_mem__phase_update', -} -pq_exe_status__mec_release_mem__default = 0 -pq_exe_status__mec_release_mem__phase_update = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'dst_sel__mec_release_mem__memory_controller', - 1: 'dst_sel__mec_release_mem__tc_l2', - 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', - 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', -} -dst_sel__mec_release_mem__memory_controller = 0 -dst_sel__mec_release_mem__tc_l2 = 1 -dst_sel__mec_release_mem__queue_write_pointer_register = 2 -dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'int_sel__mec_release_mem__none', - 1: 'int_sel__mec_release_mem__send_interrupt_only', - 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', - 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', -} -int_sel__mec_release_mem__none = 0 -int_sel__mec_release_mem__send_interrupt_only = 1 -int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 -int_sel__mec_release_mem__send_data_after_write_confirm = 3 -int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'data_sel__mec_release_mem__none', - 1: 'data_sel__mec_release_mem__send_32_bit_low', - 2: 'data_sel__mec_release_mem__send_64_bit_data', - 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', - 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', -} -data_sel__mec_release_mem__none = 0 -data_sel__mec_release_mem__send_32_bit_low = 1 -data_sel__mec_release_mem__send_64_bit_data = 2 -data_sel__mec_release_mem__send_gpu_clock_counter = 3 -data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 -data_sel__mec_release_mem__store_gds_data_to_memory = 5 -c_uint32 = ctypes.c_uint32 # enum -class struct_pm4_mec_release_mem(Structure): - pass - -class union_pm4_mec_release_mem_0(Union): - pass - -union_pm4_mec_release_mem_0._pack_ = 1 # source:False -union_pm4_mec_release_mem_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_1(Union): - pass - -class struct_pm4_mec_release_mem_1_bitfields2(Structure): - pass - -struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ - ('event_type', ctypes.c_uint32, 6), - ('reserved1', ctypes.c_uint32, 2), - ('event_index', c_uint32, 4), - ('tcl1_vol_action_ena', ctypes.c_uint32, 1), - ('tc_vol_action_ena', ctypes.c_uint32, 1), - ('reserved2', ctypes.c_uint32, 1), - ('tc_wb_action_ena', ctypes.c_uint32, 1), - ('tcl1_action_ena', ctypes.c_uint32, 1), - ('tc_action_ena', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 1), - ('tc_nc_action_ena', ctypes.c_uint32, 1), - ('tc_wc_action_ena', ctypes.c_uint32, 1), - ('tc_md_action_ena', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 3), - ('cache_policy', c_uint32, 2), - ('reserved5', ctypes.c_uint32, 2), - ('pq_exe_status', c_uint32, 1), - ('reserved6', ctypes.c_uint32, 2), -] - -union_pm4_mec_release_mem_1._pack_ = 1 # source:False -union_pm4_mec_release_mem_1._fields_ = [ - ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_2(Union): - pass - -class struct_pm4_mec_release_mem_2_bitfields3(Structure): - pass - -struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ - ('reserved7', ctypes.c_uint32, 16), - ('dst_sel', c_uint32, 2), - ('reserved8', ctypes.c_uint32, 6), - ('int_sel', c_uint32, 3), - ('reserved9', ctypes.c_uint32, 2), - ('data_sel', c_uint32, 3), -] - -union_pm4_mec_release_mem_2._pack_ = 1 # source:False -union_pm4_mec_release_mem_2._fields_ = [ - ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_3(Union): - pass - -class struct_pm4_mec_release_mem_3_bitfields4(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ - ('reserved10', ctypes.c_uint32, 2), - ('address_lo_32b', ctypes.c_uint32, 30), -] - -class struct_pm4_mec_release_mem_3_bitfields4b(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ - ('reserved11', ctypes.c_uint32, 3), - ('address_lo_64b', ctypes.c_uint32, 29), -] - -union_pm4_mec_release_mem_3._pack_ = 1 # source:False -union_pm4_mec_release_mem_3._fields_ = [ - ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), - ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), - ('reserved12', ctypes.c_uint32), - ('ordinal4', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_4(Union): - pass - -union_pm4_mec_release_mem_4._pack_ = 1 # source:False -union_pm4_mec_release_mem_4._fields_ = [ - ('address_hi', ctypes.c_uint32), - ('reserved13', ctypes.c_uint32), - ('ordinal5', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_5(Union): - pass - -class struct_pm4_mec_release_mem_5_bitfields6c(Structure): - pass - -struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False -struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ - ('dw_offset', ctypes.c_uint32, 16), - ('num_dwords', ctypes.c_uint32, 16), -] - -union_pm4_mec_release_mem_5._pack_ = 1 # source:False -union_pm4_mec_release_mem_5._fields_ = [ - ('data_lo', ctypes.c_uint32), - ('cmp_data_lo', ctypes.c_uint32), - ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), - ('reserved14', ctypes.c_uint32), - ('ordinal6', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_6(Union): - pass - -union_pm4_mec_release_mem_6._pack_ = 1 # source:False -union_pm4_mec_release_mem_6._fields_ = [ - ('data_hi', ctypes.c_uint32), - ('cmp_data_hi', ctypes.c_uint32), - ('reserved15', ctypes.c_uint32), - ('reserved16', ctypes.c_uint32), - ('ordinal7', ctypes.c_uint32), -] - -struct_pm4_mec_release_mem._pack_ = 1 # source:False -struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) -struct_pm4_mec_release_mem._fields_ = [ - ('_0', union_pm4_mec_release_mem_0), - ('_1', union_pm4_mec_release_mem_1), - ('_2', union_pm4_mec_release_mem_2), - ('_3', union_pm4_mec_release_mem_3), - ('_4', union_pm4_mec_release_mem_4), - ('_5', union_pm4_mec_release_mem_5), - ('_6', union_pm4_mec_release_mem_6), - ('int_ctxid', ctypes.c_uint32), -] - - -# values for enumeration 'WRITE_DATA_dst_sel_enum' -WRITE_DATA_dst_sel_enum__enumvalues = { - 0: 'dst_sel___write_data__mem_mapped_register', - 2: 'dst_sel___write_data__tc_l2', - 3: 'dst_sel___write_data__gds', - 5: 'dst_sel___write_data__memory', - 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', -} -dst_sel___write_data__mem_mapped_register = 0 -dst_sel___write_data__tc_l2 = 2 -dst_sel___write_data__gds = 3 -dst_sel___write_data__memory = 5 -dst_sel___write_data__memory_mapped_adc_persistent_state = 6 -WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_addr_incr_enum' -WRITE_DATA_addr_incr_enum__enumvalues = { - 0: 'addr_incr___write_data__increment_address', - 1: 'addr_incr___write_data__do_not_increment_address', -} -addr_incr___write_data__increment_address = 0 -addr_incr___write_data__do_not_increment_address = 1 -WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_wr_confirm_enum' -WRITE_DATA_wr_confirm_enum__enumvalues = { - 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 1: 'wr_confirm___write_data__wait_for_write_confirmation', -} -wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 -wr_confirm___write_data__wait_for_write_confirmation = 1 -WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_cache_policy_enum' -WRITE_DATA_cache_policy_enum__enumvalues = { - 0: 'cache_policy___write_data__lru', - 1: 'cache_policy___write_data__stream', -} -cache_policy___write_data__lru = 0 -cache_policy___write_data__stream = 1 -WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum -class struct_pm4_mec_write_data_mmio(Structure): - pass - -class union_pm4_mec_write_data_mmio_0(Union): - pass - -union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_1(Union): - pass - -class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): - pass - -struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('dst_sel', ctypes.c_uint32, 4), - ('reserved2', ctypes.c_uint32, 4), - ('addr_incr', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 2), - ('resume_vf', ctypes.c_uint32, 1), - ('wr_confirm', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 4), - ('cache_policy', ctypes.c_uint32, 2), - ('reserved5', ctypes.c_uint32, 5), -] - -union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_1._fields_ = [ - ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_2(Union): - pass - -class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): - pass - -struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ - ('dst_mmreg_addr', ctypes.c_uint32, 18), - ('reserved6', ctypes.c_uint32, 14), -] - -union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_2._fields_ = [ - ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) -struct_pm4_mec_write_data_mmio._fields_ = [ - ('_0', union_pm4_mec_write_data_mmio_0), - ('_1', union_pm4_mec_write_data_mmio_1), - ('_2', union_pm4_mec_write_data_mmio_2), - ('reserved7', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', -} -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum -_soc21_ENUM_HEADER = True # macro -SQ_WAVE_TYPE_PS0 = 0x00000000 # macro -SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro -SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro -SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro -SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro -SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro -SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro -SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro -SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro -SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro -SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro -SQ_GFXDEC_BEGIN = 0x0000a000 # macro -SQ_GFXDEC_END = 0x0000c000 # macro -SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro -SQDEC_BEGIN = 0x00002300 # macro -SQDEC_END = 0x000023ff # macro -SQPERFSDEC_BEGIN = 0x0000d9c0 # macro -SQPERFSDEC_END = 0x0000da40 # macro -SQPERFDDEC_BEGIN = 0x0000d1c0 # macro -SQPERFDDEC_END = 0x0000d240 # macro -SQGFXUDEC_BEGIN = 0x0000c330 # macro -SQGFXUDEC_END = 0x0000c380 # macro -SQPWRDEC_BEGIN = 0x0000f08c # macro -SQPWRDEC_END = 0x0000f094 # macro -SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro -SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro -SQ_MAX_PGM_SGPRS = 0x00000068 # macro -SQ_MAX_PGM_VGPRS = 0x00000100 # macro -SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro -SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro -SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro -SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro -SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro -SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro -SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro -SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro -SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro -SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro -SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro -SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro -INST_ID_PRIV_START = 0x80000000 # macro -INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro -INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro -INST_ID_HW_TRAP = 0xfffffff2 # macro -INST_ID_KILL_SEQ = 0xfffffff3 # macro -INST_ID_SPI_WREXEC = 0xfffffff4 # macro -INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro -INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro -SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro -SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro -SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro -SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro -SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro -SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro -SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro -SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro -SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro -SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro -SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro -SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro -SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro -SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro -SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro -SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro -SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro -SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro -SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro -SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro -SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro -SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro -SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro -SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro -SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro -CSDATA_TYPE_WIDTH = 0x00000002 # macro -CSDATA_ADDR_WIDTH = 0x00000007 # macro -CSDATA_DATA_WIDTH = 0x00000020 # macro -CSCNTL_TYPE_WIDTH = 0x00000002 # macro -CSCNTL_ADDR_WIDTH = 0x00000007 # macro -CSCNTL_DATA_WIDTH = 0x00000020 # macro -GSTHREADID_SIZE = 0x00000002 # macro -GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro -GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro -SEM_ECC_ERROR = 0x00000000 # macro -SEM_TRANS_ERROR = 0x00000001 # macro -SEM_RESP_FAILED = 0x00000002 # macro -SEM_RESP_PASSED = 0x00000003 # macro -IQ_QUEUE_SLEEP = 0x00000000 # macro -IQ_OFFLOAD_RETRY = 0x00000001 # macro -IQ_SCH_WAVE_MSG = 0x00000002 # macro -IQ_SEM_REARM = 0x00000003 # macro -IQ_DEQUEUE_RETRY = 0x00000004 # macro -IQ_INTR_TYPE_PQ = 0x00000000 # macro -IQ_INTR_TYPE_IB = 0x00000001 # macro -IQ_INTR_TYPE_MQD = 0x00000002 # macro -VMID_SZ = 0x00000004 # macro -SRCID_RLC = 0x00000000 # macro -SRCID_RLCV = 0x00000006 # macro -SRCID_SECURE_CP = 0x00000007 # macro -SRCID_NONSECURE_CP = 0x00000001 # macro -SRCID_SECURE_CP_RCIU = 0x00000007 # macro -SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro -CONFIG_SPACE_START = 0x00002000 # macro -CONFIG_SPACE_END = 0x00009fff # macro -CONFIG_SPACE1_START = 0x00002000 # macro -CONFIG_SPACE1_END = 0x00002bff # macro -CONFIG_SPACE2_START = 0x00003000 # macro -CONFIG_SPACE2_END = 0x00009fff # macro -UCONFIG_SPACE_START = 0x0000c000 # macro -UCONFIG_SPACE_END = 0x0000ffff # macro -PERSISTENT_SPACE_START = 0x00002c00 # macro -PERSISTENT_SPACE_END = 0x00002fff # macro -CONTEXT_SPACE_START = 0x0000a000 # macro -CONTEXT_SPACE_END = 0x0000a3ff # macro -ROM_SIGNATURE = 0x0000aa55 # macro - -# values for enumeration 'DSM_DATA_SEL' -DSM_DATA_SEL__enumvalues = { - 0: 'DSM_DATA_SEL_DISABLE', - 1: 'DSM_DATA_SEL_0', - 2: 'DSM_DATA_SEL_1', - 3: 'DSM_DATA_SEL_BOTH', -} -DSM_DATA_SEL_DISABLE = 0 -DSM_DATA_SEL_0 = 1 -DSM_DATA_SEL_1 = 2 -DSM_DATA_SEL_BOTH = 3 -DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_ENABLE_ERROR_INJECT' -DSM_ENABLE_ERROR_INJECT__enumvalues = { - 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', -} -DSM_ENABLE_ERROR_INJECT_FED_IN = 0 -DSM_ENABLE_ERROR_INJECT_SINGLE = 1 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 -DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 -DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SELECT_INJECT_DELAY' -DSM_SELECT_INJECT_DELAY__enumvalues = { - 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', - 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', -} -DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 -DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 -DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DSM_SINGLE_WRITE' -DSM_SINGLE_WRITE__enumvalues = { - 0: 'DSM_SINGLE_WRITE_DIS', - 1: 'DSM_SINGLE_WRITE_EN', -} -DSM_SINGLE_WRITE_DIS = 0 -DSM_SINGLE_WRITE_EN = 1 -DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_NUM_SIMD_PER_CU' -ENUM_NUM_SIMD_PER_CU__enumvalues = { - 2: 'NUM_SIMD_PER_CU', -} -NUM_SIMD_PER_CU = 2 -ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum - -# values for enumeration 'GATCL1RequestType' -GATCL1RequestType__enumvalues = { - 0: 'GATCL1_TYPE_NORMAL', - 1: 'GATCL1_TYPE_SHOOTDOWN', - 2: 'GATCL1_TYPE_BYPASS', -} -GATCL1_TYPE_NORMAL = 0 -GATCL1_TYPE_SHOOTDOWN = 1 -GATCL1_TYPE_BYPASS = 2 -GATCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'GL0V_CACHE_POLICIES' -GL0V_CACHE_POLICIES__enumvalues = { - 0: 'GL0V_CACHE_POLICY_MISS_LRU', - 1: 'GL0V_CACHE_POLICY_MISS_EVICT', - 2: 'GL0V_CACHE_POLICY_HIT_LRU', - 3: 'GL0V_CACHE_POLICY_HIT_EVICT', -} -GL0V_CACHE_POLICY_MISS_LRU = 0 -GL0V_CACHE_POLICY_MISS_EVICT = 1 -GL0V_CACHE_POLICY_HIT_LRU = 2 -GL0V_CACHE_POLICY_HIT_EVICT = 3 -GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_POLICIES' -GL1_CACHE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_POLICY_MISS_LRU', - 1: 'GL1_CACHE_POLICY_MISS_EVICT', - 2: 'GL1_CACHE_POLICY_HIT_LRU', - 3: 'GL1_CACHE_POLICY_HIT_EVICT', -} -GL1_CACHE_POLICY_MISS_LRU = 0 -GL1_CACHE_POLICY_MISS_EVICT = 1 -GL1_CACHE_POLICY_HIT_LRU = 2 -GL1_CACHE_POLICY_HIT_EVICT = 3 -GL1_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL1_CACHE_STORE_POLICIES' -GL1_CACHE_STORE_POLICIES__enumvalues = { - 0: 'GL1_CACHE_STORE_POLICY_BYPASS', -} -GL1_CACHE_STORE_POLICY_BYPASS = 0 -GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_CACHE_POLICIES' -GL2_CACHE_POLICIES__enumvalues = { - 0: 'GL2_CACHE_POLICY_LRU', - 1: 'GL2_CACHE_POLICY_STREAM', - 2: 'GL2_CACHE_POLICY_NOA', - 3: 'GL2_CACHE_POLICY_BYPASS', -} -GL2_CACHE_POLICY_LRU = 0 -GL2_CACHE_POLICY_STREAM = 1 -GL2_CACHE_POLICY_NOA = 2 -GL2_CACHE_POLICY_BYPASS = 3 -GL2_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'Hdp_SurfaceEndian' -Hdp_SurfaceEndian__enumvalues = { - 0: 'HDP_ENDIAN_NONE', - 1: 'HDP_ENDIAN_8IN16', - 2: 'HDP_ENDIAN_8IN32', - 3: 'HDP_ENDIAN_8IN64', -} -HDP_ENDIAN_NONE = 0 -HDP_ENDIAN_8IN16 = 1 -HDP_ENDIAN_8IN32 = 2 -HDP_ENDIAN_8IN64 = 3 -Hdp_SurfaceEndian = ctypes.c_uint32 # enum - -# values for enumeration 'MTYPE' -MTYPE__enumvalues = { - 0: 'MTYPE_C_RW_US', - 1: 'MTYPE_RESERVED_1', - 2: 'MTYPE_C_RO_S', - 3: 'MTYPE_UC', - 4: 'MTYPE_C_RW_S', - 5: 'MTYPE_RESERVED_5', - 6: 'MTYPE_C_RO_US', - 7: 'MTYPE_RESERVED_7', -} -MTYPE_C_RW_US = 0 -MTYPE_RESERVED_1 = 1 -MTYPE_C_RO_S = 2 -MTYPE_UC = 3 -MTYPE_C_RW_S = 4 -MTYPE_RESERVED_5 = 5 -MTYPE_C_RO_US = 6 -MTYPE_RESERVED_7 = 7 -MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_COUNTER_MODE' -PERFMON_COUNTER_MODE__enumvalues = { - 0: 'PERFMON_COUNTER_MODE_ACCUM', - 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 2: 'PERFMON_COUNTER_MODE_MAX', - 3: 'PERFMON_COUNTER_MODE_DIRTY', - 4: 'PERFMON_COUNTER_MODE_SAMPLE', - 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 15: 'PERFMON_COUNTER_MODE_RESERVED', -} -PERFMON_COUNTER_MODE_ACCUM = 0 -PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 -PERFMON_COUNTER_MODE_MAX = 2 -PERFMON_COUNTER_MODE_DIRTY = 3 -PERFMON_COUNTER_MODE_SAMPLE = 4 -PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 -PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 -PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 -PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 -PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 -PERFMON_COUNTER_MODE_RESERVED = 15 -PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_SPM_MODE' -PERFMON_SPM_MODE__enumvalues = { - 0: 'PERFMON_SPM_MODE_OFF', - 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', - 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', - 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 5: 'PERFMON_SPM_MODE_RESERVED_5', - 6: 'PERFMON_SPM_MODE_RESERVED_6', - 7: 'PERFMON_SPM_MODE_RESERVED_7', - 8: 'PERFMON_SPM_MODE_TEST_MODE_0', - 9: 'PERFMON_SPM_MODE_TEST_MODE_1', - 10: 'PERFMON_SPM_MODE_TEST_MODE_2', -} -PERFMON_SPM_MODE_OFF = 0 -PERFMON_SPM_MODE_16BIT_CLAMP = 1 -PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 -PERFMON_SPM_MODE_32BIT_CLAMP = 3 -PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 -PERFMON_SPM_MODE_RESERVED_5 = 5 -PERFMON_SPM_MODE_RESERVED_6 = 6 -PERFMON_SPM_MODE_RESERVED_7 = 7 -PERFMON_SPM_MODE_TEST_MODE_0 = 8 -PERFMON_SPM_MODE_TEST_MODE_1 = 9 -PERFMON_SPM_MODE_TEST_MODE_2 = 10 -PERFMON_SPM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RMI_CID' -RMI_CID__enumvalues = { - 0: 'RMI_CID_CC', - 1: 'RMI_CID_FC', - 2: 'RMI_CID_CM', - 3: 'RMI_CID_DC', - 4: 'RMI_CID_Z', - 5: 'RMI_CID_S', - 6: 'RMI_CID_TILE', - 7: 'RMI_CID_ZPCPSD', -} -RMI_CID_CC = 0 -RMI_CID_FC = 1 -RMI_CID_CM = 2 -RMI_CID_DC = 3 -RMI_CID_Z = 4 -RMI_CID_S = 5 -RMI_CID_TILE = 6 -RMI_CID_ZPCPSD = 7 -RMI_CID = ctypes.c_uint32 # enum - -# values for enumeration 'ReadPolicy' -ReadPolicy__enumvalues = { - 0: 'CACHE_LRU_RD', - 1: 'CACHE_STREAM_RD', - 2: 'CACHE_NOA', - 3: 'RESERVED_RDPOLICY', -} -CACHE_LRU_RD = 0 -CACHE_STREAM_RD = 1 -CACHE_NOA = 2 -RESERVED_RDPOLICY = 3 -ReadPolicy = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERFMON_SEL' -SDMA_PERFMON_SEL__enumvalues = { - 0: 'SDMA_PERFMON_SEL_CYCLE', - 1: 'SDMA_PERFMON_SEL_IDLE', - 2: 'SDMA_PERFMON_SEL_REG_IDLE', - 3: 'SDMA_PERFMON_SEL_RB_EMPTY', - 4: 'SDMA_PERFMON_SEL_RB_FULL', - 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', - 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', - 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 13: 'SDMA_PERFMON_SEL_EX_IDLE', - 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', - 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', - 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', - 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', - 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 26: 'SDMA_PERFMON_SEL_SEM_IDLE', - 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 32: 'SDMA_PERFMON_SEL_INT_IDLE', - 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 37: 'SDMA_PERFMON_SEL_NUM_PACKET', - 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', - 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', - 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', - 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', - 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', - 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', - 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', - 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', - 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', - 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', - 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', - 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', - 55: 'SDMA_PERFMON_SEL_GFX_SELECT', - 56: 'SDMA_PERFMON_SEL_RLC0_SELECT', - 57: 'SDMA_PERFMON_SEL_RLC1_SELECT', - 58: 'SDMA_PERFMON_SEL_PAGE_SELECT', - 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', - 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', - 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 62: 'SDMA_PERFMON_SEL_DOORBELL', - 63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', - 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', - 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', - 95: 'SDMA_PERFMON_SEL_TLBI_SEND', - 96: 'SDMA_PERFMON_SEL_TLBI_RTN', - 97: 'SDMA_PERFMON_SEL_GCR_SEND', - 98: 'SDMA_PERFMON_SEL_GCR_RTN', - 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', -} -SDMA_PERFMON_SEL_CYCLE = 0 -SDMA_PERFMON_SEL_IDLE = 1 -SDMA_PERFMON_SEL_REG_IDLE = 2 -SDMA_PERFMON_SEL_RB_EMPTY = 3 -SDMA_PERFMON_SEL_RB_FULL = 4 -SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 -SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 -SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERFMON_SEL_RB_RPTR_WB = 8 -SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 -SDMA_PERFMON_SEL_RB_CMD_FULL = 10 -SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 -SDMA_PERFMON_SEL_IB_CMD_FULL = 12 -SDMA_PERFMON_SEL_EX_IDLE = 13 -SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 -SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERFMON_SEL_WR_BA_RTR = 16 -SDMA_PERFMON_SEL_MC_WR_IDLE = 17 -SDMA_PERFMON_SEL_MC_WR_COUNT = 18 -SDMA_PERFMON_SEL_RD_BA_RTR = 19 -SDMA_PERFMON_SEL_MC_RD_IDLE = 20 -SDMA_PERFMON_SEL_MC_RD_COUNT = 21 -SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 -SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 -SDMA_PERFMON_SEL_SEM_IDLE = 26 -SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 -SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 -SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 -SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 -SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 -SDMA_PERFMON_SEL_INT_IDLE = 32 -SDMA_PERFMON_SEL_INT_REQ_STALL = 33 -SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 -SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 -SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 -SDMA_PERFMON_SEL_NUM_PACKET = 37 -SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 -SDMA_PERFMON_SEL_CE_WR_IDLE = 40 -SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 -SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 -SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 -SDMA_PERFMON_SEL_CE_IN_IDLE = 44 -SDMA_PERFMON_SEL_CE_DST_IDLE = 45 -SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 -SDMA_PERFMON_SEL_CE_INFO_FULL = 51 -SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 -SDMA_PERFMON_SEL_CE_RD_STALL = 53 -SDMA_PERFMON_SEL_CE_WR_STALL = 54 -SDMA_PERFMON_SEL_GFX_SELECT = 55 -SDMA_PERFMON_SEL_RLC0_SELECT = 56 -SDMA_PERFMON_SEL_RLC1_SELECT = 57 -SDMA_PERFMON_SEL_PAGE_SELECT = 58 -SDMA_PERFMON_SEL_CTX_CHANGE = 59 -SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 -SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 -SDMA_PERFMON_SEL_DOORBELL = 62 -SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63 -SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 -SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 -SDMA_PERFMON_SEL_UTCL2_FREE = 73 -SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 -SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 -SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 -SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 -SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 -SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 -SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 -SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERFMON_SEL_META_REQ_SEND = 93 -SDMA_PERFMON_SEL_META_RTN_VLD = 94 -SDMA_PERFMON_SEL_TLBI_SEND = 95 -SDMA_PERFMON_SEL_TLBI_RTN = 96 -SDMA_PERFMON_SEL_GCR_SEND = 97 -SDMA_PERFMON_SEL_GCR_RTN = 98 -SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 -SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 -SDMA_PERFMON_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SDMA_PERF_SEL' -SDMA_PERF_SEL__enumvalues = { - 0: 'SDMA_PERF_SEL_CYCLE', - 1: 'SDMA_PERF_SEL_IDLE', - 2: 'SDMA_PERF_SEL_REG_IDLE', - 3: 'SDMA_PERF_SEL_RB_EMPTY', - 4: 'SDMA_PERF_SEL_RB_FULL', - 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'SDMA_PERF_SEL_RB_RPTR_WB', - 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'SDMA_PERF_SEL_RB_CMD_FULL', - 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'SDMA_PERF_SEL_IB_CMD_FULL', - 13: 'SDMA_PERF_SEL_EX_IDLE', - 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'SDMA_PERF_SEL_MC_WR_IDLE', - 17: 'SDMA_PERF_SEL_MC_WR_COUNT', - 18: 'SDMA_PERF_SEL_MC_RD_IDLE', - 19: 'SDMA_PERF_SEL_MC_RD_COUNT', - 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'SDMA_PERF_SEL_SEM_IDLE', - 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'SDMA_PERF_SEL_INT_IDLE', - 31: 'SDMA_PERF_SEL_INT_REQ_STALL', - 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'SDMA_PERF_SEL_NUM_PACKET', - 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'SDMA_PERF_SEL_CE_WR_IDLE', - 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'SDMA_PERF_SEL_CE_IN_IDLE', - 43: 'SDMA_PERF_SEL_CE_DST_IDLE', - 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'SDMA_PERF_SEL_CE_INFO_FULL', - 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'SDMA_PERF_SEL_CE_RD_STALL', - 52: 'SDMA_PERF_SEL_CE_WR_STALL', - 53: 'SDMA_PERF_SEL_GFX_SELECT', - 54: 'SDMA_PERF_SEL_RLC0_SELECT', - 55: 'SDMA_PERF_SEL_RLC1_SELECT', - 56: 'SDMA_PERF_SEL_PAGE_SELECT', - 57: 'SDMA_PERF_SEL_CTX_CHANGE', - 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'SDMA_PERF_SEL_DOORBELL', - 61: 'SDMA_PERF_SEL_RD_BA_RTR', - 62: 'SDMA_PERF_SEL_WR_BA_RTR', - 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', - 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 73: 'SDMA_PERF_SEL_UTCL2_FREE', - 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', - 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', - 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', - 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', - 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', - 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', - 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', - 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', - 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', - 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', - 93: 'SDMA_PERF_SEL_META_REQ_SEND', - 94: 'SDMA_PERF_SEL_META_RTN_VLD', - 95: 'SDMA_PERF_SEL_TLBI_SEND', - 96: 'SDMA_PERF_SEL_TLBI_RTN', - 97: 'SDMA_PERF_SEL_GCR_SEND', - 98: 'SDMA_PERF_SEL_GCR_RTN', - 99: 'SDMA_PERF_SEL_CGCG_FENCE', - 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', - 102: 'SDMA_PERF_SEL_F32_CH_WR_REQ', - 103: 'SDMA_PERF_SEL_F32_CH_WR_RET', - 104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', - 105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', - 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', - 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', - 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', - 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', - 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', - 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', - 115: 'SDMA_PERF_SEL_CMD_OP_START', - 116: 'SDMA_PERF_SEL_CMD_OP_END', - 117: 'SDMA_PERF_SEL_CE_BUSY', - 118: 'SDMA_PERF_SEL_CE_BUSY_START', - 119: 'SDMA_PERF_SEL_CE_BUSY_END', - 120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', - 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', - 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', -} -SDMA_PERF_SEL_CYCLE = 0 -SDMA_PERF_SEL_IDLE = 1 -SDMA_PERF_SEL_REG_IDLE = 2 -SDMA_PERF_SEL_RB_EMPTY = 3 -SDMA_PERF_SEL_RB_FULL = 4 -SDMA_PERF_SEL_RB_WPTR_WRAP = 5 -SDMA_PERF_SEL_RB_RPTR_WRAP = 6 -SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -SDMA_PERF_SEL_RB_RPTR_WB = 8 -SDMA_PERF_SEL_RB_CMD_IDLE = 9 -SDMA_PERF_SEL_RB_CMD_FULL = 10 -SDMA_PERF_SEL_IB_CMD_IDLE = 11 -SDMA_PERF_SEL_IB_CMD_FULL = 12 -SDMA_PERF_SEL_EX_IDLE = 13 -SDMA_PERF_SEL_SRBM_REG_SEND = 14 -SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -SDMA_PERF_SEL_MC_WR_IDLE = 16 -SDMA_PERF_SEL_MC_WR_COUNT = 17 -SDMA_PERF_SEL_MC_RD_IDLE = 18 -SDMA_PERF_SEL_MC_RD_COUNT = 19 -SDMA_PERF_SEL_MC_RD_RET_STALL = 20 -SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -SDMA_PERF_SEL_SEM_IDLE = 24 -SDMA_PERF_SEL_SEM_REQ_STALL = 25 -SDMA_PERF_SEL_SEM_REQ_COUNT = 26 -SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -SDMA_PERF_SEL_SEM_RESP_FAIL = 28 -SDMA_PERF_SEL_SEM_RESP_PASS = 29 -SDMA_PERF_SEL_INT_IDLE = 30 -SDMA_PERF_SEL_INT_REQ_STALL = 31 -SDMA_PERF_SEL_INT_REQ_COUNT = 32 -SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -SDMA_PERF_SEL_INT_RESP_RETRY = 34 -SDMA_PERF_SEL_NUM_PACKET = 35 -SDMA_PERF_SEL_CE_WREQ_IDLE = 37 -SDMA_PERF_SEL_CE_WR_IDLE = 38 -SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -SDMA_PERF_SEL_CE_RREQ_IDLE = 40 -SDMA_PERF_SEL_CE_OUT_IDLE = 41 -SDMA_PERF_SEL_CE_IN_IDLE = 42 -SDMA_PERF_SEL_CE_DST_IDLE = 43 -SDMA_PERF_SEL_CE_AFIFO_FULL = 46 -SDMA_PERF_SEL_CE_INFO_FULL = 49 -SDMA_PERF_SEL_CE_INFO1_FULL = 50 -SDMA_PERF_SEL_CE_RD_STALL = 51 -SDMA_PERF_SEL_CE_WR_STALL = 52 -SDMA_PERF_SEL_GFX_SELECT = 53 -SDMA_PERF_SEL_RLC0_SELECT = 54 -SDMA_PERF_SEL_RLC1_SELECT = 55 -SDMA_PERF_SEL_PAGE_SELECT = 56 -SDMA_PERF_SEL_CTX_CHANGE = 57 -SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -SDMA_PERF_SEL_DOORBELL = 60 -SDMA_PERF_SEL_RD_BA_RTR = 61 -SDMA_PERF_SEL_WR_BA_RTR = 62 -SDMA_PERF_SEL_F32_L1_WR_VLD = 63 -SDMA_PERF_SEL_CE_L1_WR_VLD = 64 -SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 -SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 -SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 -SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 -SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 -SDMA_PERF_SEL_UTCL2_RET_ACK = 72 -SDMA_PERF_SEL_UTCL2_FREE = 73 -SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 -SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 -SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 -SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 -SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 -SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 -SDMA_PERF_SEL_GPUVM_INV_LOW = 80 -SDMA_PERF_SEL_L1_WRL2_IDLE = 81 -SDMA_PERF_SEL_L1_RDL2_IDLE = 82 -SDMA_PERF_SEL_L1_WRMC_IDLE = 83 -SDMA_PERF_SEL_L1_RDMC_IDLE = 84 -SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 -SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 -SDMA_PERF_SEL_META_L2_REQ_SEND = 87 -SDMA_PERF_SEL_L2_META_RET_VLD = 88 -SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 -SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 -SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 -SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 -SDMA_PERF_SEL_META_REQ_SEND = 93 -SDMA_PERF_SEL_META_RTN_VLD = 94 -SDMA_PERF_SEL_TLBI_SEND = 95 -SDMA_PERF_SEL_TLBI_RTN = 96 -SDMA_PERF_SEL_GCR_SEND = 97 -SDMA_PERF_SEL_GCR_RTN = 98 -SDMA_PERF_SEL_CGCG_FENCE = 99 -SDMA_PERF_SEL_CE_CH_WR_REQ = 100 -SDMA_PERF_SEL_CE_CH_WR_RET = 101 -SDMA_PERF_SEL_F32_CH_WR_REQ = 102 -SDMA_PERF_SEL_F32_CH_WR_RET = 103 -SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104 -SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105 -SDMA_PERF_SEL_RB_CH_RD_REQ = 106 -SDMA_PERF_SEL_RB_CH_RD_RET = 107 -SDMA_PERF_SEL_IB_CH_RD_REQ = 108 -SDMA_PERF_SEL_IB_CH_RD_RET = 109 -SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 -SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 -SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 -SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 -SDMA_PERF_SEL_CMD_OP_MATCH = 114 -SDMA_PERF_SEL_CMD_OP_START = 115 -SDMA_PERF_SEL_CMD_OP_END = 116 -SDMA_PERF_SEL_CE_BUSY = 117 -SDMA_PERF_SEL_CE_BUSY_START = 118 -SDMA_PERF_SEL_CE_BUSY_END = 119 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121 -SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122 -SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 -SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 -SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 -SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 -SDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_CACHE_POLICIES' -TCC_CACHE_POLICIES__enumvalues = { - 0: 'TCC_CACHE_POLICY_LRU', - 1: 'TCC_CACHE_POLICY_STREAM', -} -TCC_CACHE_POLICY_LRU = 0 -TCC_CACHE_POLICY_STREAM = 1 -TCC_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCC_MTYPE' -TCC_MTYPE__enumvalues = { - 0: 'MTYPE_NC', - 1: 'MTYPE_WC', - 2: 'MTYPE_CC', -} -MTYPE_NC = 0 -MTYPE_WC = 1 -MTYPE_CC = 2 -TCC_MTYPE = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0FaultType' -UTCL0FaultType__enumvalues = { - 0: 'UTCL0_XNACK_SUCCESS', - 1: 'UTCL0_XNACK_RETRY', - 2: 'UTCL0_XNACK_PRT', - 3: 'UTCL0_XNACK_NO_RETRY', -} -UTCL0_XNACK_SUCCESS = 0 -UTCL0_XNACK_RETRY = 1 -UTCL0_XNACK_PRT = 2 -UTCL0_XNACK_NO_RETRY = 3 -UTCL0FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL0RequestType' -UTCL0RequestType__enumvalues = { - 0: 'UTCL0_TYPE_NORMAL', - 1: 'UTCL0_TYPE_SHOOTDOWN', - 2: 'UTCL0_TYPE_BYPASS', -} -UTCL0_TYPE_NORMAL = 0 -UTCL0_TYPE_SHOOTDOWN = 1 -UTCL0_TYPE_BYPASS = 2 -UTCL0RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1FaultType' -UTCL1FaultType__enumvalues = { - 0: 'UTCL1_XNACK_SUCCESS', - 1: 'UTCL1_XNACK_RETRY', - 2: 'UTCL1_XNACK_PRT', - 3: 'UTCL1_XNACK_NO_RETRY', -} -UTCL1_XNACK_SUCCESS = 0 -UTCL1_XNACK_RETRY = 1 -UTCL1_XNACK_PRT = 2 -UTCL1_XNACK_NO_RETRY = 3 -UTCL1FaultType = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1RequestType' -UTCL1RequestType__enumvalues = { - 0: 'UTCL1_TYPE_NORMAL', - 1: 'UTCL1_TYPE_SHOOTDOWN', - 2: 'UTCL1_TYPE_BYPASS', -} -UTCL1_TYPE_NORMAL = 0 -UTCL1_TYPE_SHOOTDOWN = 1 -UTCL1_TYPE_BYPASS = 2 -UTCL1RequestType = ctypes.c_uint32 # enum - -# values for enumeration 'VMEMCMD_RETURN_ORDER' -VMEMCMD_RETURN_ORDER__enumvalues = { - 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', - 1: 'VMEMCMD_RETURN_IN_ORDER', - 2: 'VMEMCMD_RETURN_IN_ORDER_READ', -} -VMEMCMD_RETURN_OUT_OF_ORDER = 0 -VMEMCMD_RETURN_IN_ORDER = 1 -VMEMCMD_RETURN_IN_ORDER_READ = 2 -VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'WritePolicy' -WritePolicy__enumvalues = { - 0: 'CACHE_LRU_WR', - 1: 'CACHE_STREAM', - 2: 'CACHE_NOA_WR', - 3: 'CACHE_BYPASS', -} -CACHE_LRU_WR = 0 -CACHE_STREAM = 1 -CACHE_NOA_WR = 2 -CACHE_BYPASS = 3 -WritePolicy = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_BYPASS' -CNVC_BYPASS__enumvalues = { - 0: 'CNVC_BYPASS_DISABLE', - 1: 'CNVC_BYPASS_EN', -} -CNVC_BYPASS_DISABLE = 0 -CNVC_BYPASS_EN = 1 -CNVC_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_COEF_FORMAT_ENUM' -CNVC_COEF_FORMAT_ENUM__enumvalues = { - 0: 'CNVC_FIX_S2_13', - 1: 'CNVC_FIX_S3_12', -} -CNVC_FIX_S2_13 = 0 -CNVC_FIX_S3_12 = 1 -CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_ENABLE' -CNVC_ENABLE__enumvalues = { - 0: 'CNVC_DIS', - 1: 'CNVC_EN', -} -CNVC_DIS = 0 -CNVC_EN = 1 -CNVC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CNVC_PENDING' -CNVC_PENDING__enumvalues = { - 0: 'CNVC_NOT_PENDING', - 1: 'CNVC_YES_PENDING', -} -CNVC_NOT_PENDING = 0 -CNVC_YES_PENDING = 1 -CNVC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'COLOR_KEYER_MODE' -COLOR_KEYER_MODE__enumvalues = { - 0: 'FORCE_00', - 1: 'FORCE_FF', - 2: 'RANGE_00', - 3: 'RANGE_FF', -} -FORCE_00 = 0 -FORCE_FF = 1 -RANGE_00 = 2 -RANGE_FF = 3 -COLOR_KEYER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DENORM_TRUNCATE' -DENORM_TRUNCATE__enumvalues = { - 0: 'CNVC_ROUND', - 1: 'CNVC_TRUNCATE', -} -CNVC_ROUND = 0 -CNVC_TRUNCATE = 1 -DENORM_TRUNCATE = ctypes.c_uint32 # enum - -# values for enumeration 'FORMAT_CROSSBAR' -FORMAT_CROSSBAR__enumvalues = { - 0: 'FORMAT_CROSSBAR_R', - 1: 'FORMAT_CROSSBAR_G', - 2: 'FORMAT_CROSSBAR_B', -} -FORMAT_CROSSBAR_R = 0 -FORMAT_CROSSBAR_G = 1 -FORMAT_CROSSBAR_B = 2 -FORMAT_CROSSBAR = ctypes.c_uint32 # enum - -# values for enumeration 'PIX_EXPAND_MODE' -PIX_EXPAND_MODE__enumvalues = { - 0: 'PIX_DYNAMIC_EXPANSION', - 1: 'PIX_ZERO_EXPANSION', -} -PIX_DYNAMIC_EXPANSION = 0 -PIX_ZERO_EXPANSION = 1 -PIX_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_CSC_MODE_ENUM' -PRE_CSC_MODE_ENUM__enumvalues = { - 0: 'PRE_CSC_BYPASS', - 1: 'PRE_CSC_SET_A', - 2: 'PRE_CSC_SET_B', -} -PRE_CSC_BYPASS = 0 -PRE_CSC_SET_A = 1 -PRE_CSC_SET_B = 2 -PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_MODE' -PRE_DEGAM_MODE__enumvalues = { - 0: 'PRE_DEGAM_BYPASS', - 1: 'PRE_DEGAM_ENABLE', -} -PRE_DEGAM_BYPASS = 0 -PRE_DEGAM_ENABLE = 1 -PRE_DEGAM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PRE_DEGAM_SELECT' -PRE_DEGAM_SELECT__enumvalues = { - 0: 'PRE_DEGAM_SRGB', - 1: 'PRE_DEGAM_GAMMA_22', - 2: 'PRE_DEGAM_GAMMA_24', - 3: 'PRE_DEGAM_GAMMA_26', - 4: 'PRE_DEGAM_BT2020', - 5: 'PRE_DEGAM_BT2100PQ', - 6: 'PRE_DEGAM_BT2100HLG', -} -PRE_DEGAM_SRGB = 0 -PRE_DEGAM_GAMMA_22 = 1 -PRE_DEGAM_GAMMA_24 = 2 -PRE_DEGAM_GAMMA_26 = 3 -PRE_DEGAM_BT2020 = 4 -PRE_DEGAM_BT2100PQ = 5 -PRE_DEGAM_BT2100HLG = 6 -PRE_DEGAM_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_PIXEL_FORMAT' -SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'ARGB1555', - 2: 'RGBA5551', - 3: 'RGB565', - 4: 'BGR565', - 5: 'ARGB4444', - 6: 'RGBA4444', - 8: 'ARGB8888', - 9: 'RGBA8888', - 10: 'ARGB2101010', - 11: 'RGBA1010102', - 12: 'AYCrCb8888', - 13: 'YCrCbA8888', - 14: 'ACrYCb8888', - 15: 'CrYCbA8888', - 16: 'ARGB16161616_10MSB', - 17: 'RGBA16161616_10MSB', - 18: 'ARGB16161616_10LSB', - 19: 'RGBA16161616_10LSB', - 20: 'ARGB16161616_12MSB', - 21: 'RGBA16161616_12MSB', - 22: 'ARGB16161616_12LSB', - 23: 'RGBA16161616_12LSB', - 24: 'ARGB16161616_FLOAT', - 25: 'RGBA16161616_FLOAT', - 26: 'ARGB16161616_UNORM', - 27: 'RGBA16161616_UNORM', - 28: 'ARGB16161616_SNORM', - 29: 'RGBA16161616_SNORM', - 32: 'AYCrCb16161616_10MSB', - 33: 'AYCrCb16161616_10LSB', - 34: 'YCrCbA16161616_10MSB', - 35: 'YCrCbA16161616_10LSB', - 36: 'ACrYCb16161616_10MSB', - 37: 'ACrYCb16161616_10LSB', - 38: 'CrYCbA16161616_10MSB', - 39: 'CrYCbA16161616_10LSB', - 40: 'AYCrCb16161616_12MSB', - 41: 'AYCrCb16161616_12LSB', - 42: 'YCrCbA16161616_12MSB', - 43: 'YCrCbA16161616_12LSB', - 44: 'ACrYCb16161616_12MSB', - 45: 'ACrYCb16161616_12LSB', - 46: 'CrYCbA16161616_12MSB', - 47: 'CrYCbA16161616_12LSB', - 64: 'Y8_CrCb88_420_PLANAR', - 65: 'Y8_CbCr88_420_PLANAR', - 66: 'Y10_CrCb1010_420_PLANAR', - 67: 'Y10_CbCr1010_420_PLANAR', - 68: 'Y12_CrCb1212_420_PLANAR', - 69: 'Y12_CbCr1212_420_PLANAR', - 72: 'YCrYCb8888_422_PACKED', - 73: 'YCbYCr8888_422_PACKED', - 74: 'CrYCbY8888_422_PACKED', - 75: 'CbYCrY8888_422_PACKED', - 76: 'YCrYCb10101010_422_PACKED', - 77: 'YCbYCr10101010_422_PACKED', - 78: 'CrYCbY10101010_422_PACKED', - 79: 'CbYCrY10101010_422_PACKED', - 80: 'YCrYCb12121212_422_PACKED', - 81: 'YCbYCr12121212_422_PACKED', - 82: 'CrYCbY12121212_422_PACKED', - 83: 'CbYCrY12121212_422_PACKED', - 112: 'RGB111110_FIX', - 113: 'BGR101111_FIX', - 114: 'ACrYCb2101010', - 115: 'CrYCbA1010102', - 116: 'RGBE', - 118: 'RGB111110_FLOAT', - 119: 'BGR101111_FLOAT', - 120: 'MONO_8', - 121: 'MONO_10MSB', - 122: 'MONO_10LSB', - 123: 'MONO_12MSB', - 124: 'MONO_12LSB', - 125: 'MONO_16', -} -ARGB1555 = 1 -RGBA5551 = 2 -RGB565 = 3 -BGR565 = 4 -ARGB4444 = 5 -RGBA4444 = 6 -ARGB8888 = 8 -RGBA8888 = 9 -ARGB2101010 = 10 -RGBA1010102 = 11 -AYCrCb8888 = 12 -YCrCbA8888 = 13 -ACrYCb8888 = 14 -CrYCbA8888 = 15 -ARGB16161616_10MSB = 16 -RGBA16161616_10MSB = 17 -ARGB16161616_10LSB = 18 -RGBA16161616_10LSB = 19 -ARGB16161616_12MSB = 20 -RGBA16161616_12MSB = 21 -ARGB16161616_12LSB = 22 -RGBA16161616_12LSB = 23 -ARGB16161616_FLOAT = 24 -RGBA16161616_FLOAT = 25 -ARGB16161616_UNORM = 26 -RGBA16161616_UNORM = 27 -ARGB16161616_SNORM = 28 -RGBA16161616_SNORM = 29 -AYCrCb16161616_10MSB = 32 -AYCrCb16161616_10LSB = 33 -YCrCbA16161616_10MSB = 34 -YCrCbA16161616_10LSB = 35 -ACrYCb16161616_10MSB = 36 -ACrYCb16161616_10LSB = 37 -CrYCbA16161616_10MSB = 38 -CrYCbA16161616_10LSB = 39 -AYCrCb16161616_12MSB = 40 -AYCrCb16161616_12LSB = 41 -YCrCbA16161616_12MSB = 42 -YCrCbA16161616_12LSB = 43 -ACrYCb16161616_12MSB = 44 -ACrYCb16161616_12LSB = 45 -CrYCbA16161616_12MSB = 46 -CrYCbA16161616_12LSB = 47 -Y8_CrCb88_420_PLANAR = 64 -Y8_CbCr88_420_PLANAR = 65 -Y10_CrCb1010_420_PLANAR = 66 -Y10_CbCr1010_420_PLANAR = 67 -Y12_CrCb1212_420_PLANAR = 68 -Y12_CbCr1212_420_PLANAR = 69 -YCrYCb8888_422_PACKED = 72 -YCbYCr8888_422_PACKED = 73 -CrYCbY8888_422_PACKED = 74 -CbYCrY8888_422_PACKED = 75 -YCrYCb10101010_422_PACKED = 76 -YCbYCr10101010_422_PACKED = 77 -CrYCbY10101010_422_PACKED = 78 -CbYCrY10101010_422_PACKED = 79 -YCrYCb12121212_422_PACKED = 80 -YCbYCr12121212_422_PACKED = 81 -CrYCbY12121212_422_PACKED = 82 -CbYCrY12121212_422_PACKED = 83 -RGB111110_FIX = 112 -BGR101111_FIX = 113 -ACrYCb2101010 = 114 -CrYCbA1010102 = 115 -RGBE = 116 -RGB111110_FLOAT = 118 -BGR101111_FLOAT = 119 -MONO_8 = 120 -MONO_10MSB = 121 -MONO_10LSB = 122 -MONO_12MSB = 123 -MONO_12LSB = 124 -MONO_16 = 125 -SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'XNORM' -XNORM__enumvalues = { - 0: 'XNORM_A', - 1: 'XNORM_B', -} -XNORM_A = 0 -XNORM_B = 1 -XNORM = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ENABLE' -CUR_ENABLE__enumvalues = { - 0: 'CUR_DIS', - 1: 'CUR_EN', -} -CUR_DIS = 0 -CUR_EN = 1 -CUR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_EXPAND_MODE' -CUR_EXPAND_MODE__enumvalues = { - 0: 'CUR_DYNAMIC_EXPANSION', - 1: 'CUR_ZERO_EXPANSION', -} -CUR_DYNAMIC_EXPANSION = 0 -CUR_ZERO_EXPANSION = 1 -CUR_EXPAND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_INV_CLAMP' -CUR_INV_CLAMP__enumvalues = { - 0: 'CUR_CLAMP_DIS', - 1: 'CUR_CLAMP_EN', -} -CUR_CLAMP_DIS = 0 -CUR_CLAMP_EN = 1 -CUR_INV_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_MODE' -CUR_MODE__enumvalues = { - 0: 'MONO_2BIT', - 1: 'COLOR_24BIT_1BIT_AND', - 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'COLOR_64BIT_FP_PREMULT', - 5: 'COLOR_64BIT_FP_UNPREMULT', -} -MONO_2BIT = 0 -COLOR_24BIT_1BIT_AND = 1 -COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -COLOR_64BIT_FP_PREMULT = 4 -COLOR_64BIT_FP_UNPREMULT = 5 -CUR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_PENDING' -CUR_PENDING__enumvalues = { - 0: 'CUR_NOT_PENDING', - 1: 'CUR_YES_PENDING', -} -CUR_NOT_PENDING = 0 -CUR_YES_PENDING = 1 -CUR_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CUR_ROM_EN' -CUR_ROM_EN__enumvalues = { - 0: 'CUR_FP_NO_ROM', - 1: 'CUR_FP_USE_ROM', -} -CUR_FP_NO_ROM = 0 -CUR_FP_USE_ROM = 1 -CUR_ROM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'COEF_RAM_SELECT_RD' -COEF_RAM_SELECT_RD__enumvalues = { - 0: 'COEF_RAM_SELECT_BACK', - 1: 'COEF_RAM_SELECT_CURRENT', -} -COEF_RAM_SELECT_BACK = 0 -COEF_RAM_SELECT_CURRENT = 1 -COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum - -# values for enumeration 'DSCL_MODE_SEL' -DSCL_MODE_SEL__enumvalues = { - 0: 'DSCL_MODE_SCALING_444_BYPASS', - 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', - 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', - 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', - 6: 'DSCL_MODE_DSCL_BYPASS', -} -DSCL_MODE_SCALING_444_BYPASS = 0 -DSCL_MODE_SCALING_444_RGB_ENABLE = 1 -DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 -DSCL_MODE_SCALING_YCBCR_ENABLE = 3 -DSCL_MODE_LUMA_SCALING_BYPASS = 4 -DSCL_MODE_CHROMA_SCALING_BYPASS = 5 -DSCL_MODE_DSCL_BYPASS = 6 -DSCL_MODE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LB_ALPHA_EN' -LB_ALPHA_EN__enumvalues = { - 0: 'LB_ALPHA_DISABLE', - 1: 'LB_ALPHA_ENABLE', -} -LB_ALPHA_DISABLE = 0 -LB_ALPHA_ENABLE = 1 -LB_ALPHA_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_INTERLEAVE_EN' -LB_INTERLEAVE_EN__enumvalues = { - 0: 'LB_INTERLEAVE_DISABLE', - 1: 'LB_INTERLEAVE_ENABLE', -} -LB_INTERLEAVE_DISABLE = 0 -LB_INTERLEAVE_ENABLE = 1 -LB_INTERLEAVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LB_MEMORY_CONFIG' -LB_MEMORY_CONFIG__enumvalues = { - 0: 'LB_MEMORY_CONFIG_0', - 1: 'LB_MEMORY_CONFIG_1', - 2: 'LB_MEMORY_CONFIG_2', - 3: 'LB_MEMORY_CONFIG_3', -} -LB_MEMORY_CONFIG_0 = 0 -LB_MEMORY_CONFIG_1 = 1 -LB_MEMORY_CONFIG_2 = 2 -LB_MEMORY_CONFIG_3 = 3 -LB_MEMORY_CONFIG = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_BYPASS_SEL' -OBUF_BYPASS_SEL__enumvalues = { - 0: 'OBUF_BYPASS_DIS', - 1: 'OBUF_BYPASS_EN', -} -OBUF_BYPASS_DIS = 0 -OBUF_BYPASS_EN = 1 -OBUF_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' -OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { - 0: 'OBUF_FULL_RECOUT', - 1: 'OBUF_HALF_RECOUT', -} -OBUF_FULL_RECOUT = 0 -OBUF_HALF_RECOUT = 1 -OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' -OBUF_USE_FULL_BUFFER_SEL__enumvalues = { - 0: 'OBUF_RECOUT', - 1: 'OBUF_FULL', -} -OBUF_RECOUT = 0 -OBUF_FULL = 1 -OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_2TAP_HARDCODE' -SCL_2TAP_HARDCODE__enumvalues = { - 0: 'SCL_COEF_2TAP_HARDCODE_OFF', - 1: 'SCL_COEF_2TAP_HARDCODE_ON', -} -SCL_COEF_2TAP_HARDCODE_OFF = 0 -SCL_COEF_2TAP_HARDCODE_ON = 1 -SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_ALPHA_COEF' -SCL_ALPHA_COEF__enumvalues = { - 0: 'SCL_ALPHA_COEF_FIRST', - 1: 'SCL_ALPHA_COEF_SECOND', -} -SCL_ALPHA_COEF_FIRST = 0 -SCL_ALPHA_COEF_SECOND = 1 -SCL_ALPHA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_AUTOCAL_MODE' -SCL_AUTOCAL_MODE__enumvalues = { - 0: 'AUTOCAL_MODE_OFF', - 1: 'AUTOCAL_MODE_AUTOSCALE', - 2: 'AUTOCAL_MODE_AUTOCENTER', - 3: 'AUTOCAL_MODE_AUTOREPLICATE', -} -AUTOCAL_MODE_OFF = 0 -AUTOCAL_MODE_AUTOSCALE = 1 -AUTOCAL_MODE_AUTOCENTER = 2 -AUTOCAL_MODE_AUTOREPLICATE = 3 -SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_BOUNDARY' -SCL_BOUNDARY__enumvalues = { - 0: 'SCL_BOUNDARY_EDGE', - 1: 'SCL_BOUNDARY_BLACK', -} -SCL_BOUNDARY_EDGE = 0 -SCL_BOUNDARY_BLACK = 1 -SCL_BOUNDARY = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_CHROMA_COEF' -SCL_CHROMA_COEF__enumvalues = { - 0: 'SCL_CHROMA_COEF_FIRST', - 1: 'SCL_CHROMA_COEF_SECOND', -} -SCL_CHROMA_COEF_FIRST = 0 -SCL_CHROMA_COEF_SECOND = 1 -SCL_CHROMA_COEF = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' -SCL_COEF_FILTER_TYPE_SEL__enumvalues = { - 0: 'SCL_COEF_LUMA_VERT_FILTER', - 1: 'SCL_COEF_LUMA_HORZ_FILTER', - 2: 'SCL_COEF_CHROMA_VERT_FILTER', - 3: 'SCL_COEF_CHROMA_HORZ_FILTER', -} -SCL_COEF_LUMA_VERT_FILTER = 0 -SCL_COEF_LUMA_HORZ_FILTER = 1 -SCL_COEF_CHROMA_VERT_FILTER = 2 -SCL_COEF_CHROMA_HORZ_FILTER = 3 -SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_COEF_RAM_SEL' -SCL_COEF_RAM_SEL__enumvalues = { - 0: 'SCL_COEF_RAM_SEL_0', - 1: 'SCL_COEF_RAM_SEL_1', -} -SCL_COEF_RAM_SEL_0 = 0 -SCL_COEF_RAM_SEL_1 = 1 -SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SCL_SHARP_EN' -SCL_SHARP_EN__enumvalues = { - 0: 'SCL_SHARP_DISABLE', - 1: 'SCL_SHARP_ENABLE', -} -SCL_SHARP_DISABLE = 0 -SCL_SHARP_ENABLE = 1 -SCL_SHARP_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_30BIT_ENUM' -CMC_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'CMC_3DLUT_36BIT', - 1: 'CMC_3DLUT_30BIT', -} -CMC_3DLUT_36BIT = 0 -CMC_3DLUT_30BIT = 1 -CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_RAM_SEL' -CMC_3DLUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAM0_ACCESS', - 1: 'CMC_RAM1_ACCESS', - 2: 'CMC_RAM2_ACCESS', - 3: 'CMC_RAM3_ACCESS', -} -CMC_RAM0_ACCESS = 0 -CMC_RAM1_ACCESS = 1 -CMC_RAM2_ACCESS = 2 -CMC_RAM3_ACCESS = 3 -CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_3DLUT_SIZE_ENUM' -CMC_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'CMC_3DLUT_17CUBE', - 1: 'CMC_3DLUT_9CUBE', -} -CMC_3DLUT_17CUBE = 0 -CMC_3DLUT_9CUBE = 1 -CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' -CMC_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'CMC_LUT_2CFG_NO_MEMORY', - 1: 'CMC_LUT_2CFG_MEMORY_A', - 2: 'CMC_LUT_2CFG_MEMORY_B', -} -CMC_LUT_2CFG_NO_MEMORY = 0 -CMC_LUT_2CFG_MEMORY_A = 1 -CMC_LUT_2CFG_MEMORY_B = 2 -CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_2_MODE_ENUM' -CMC_LUT_2_MODE_ENUM__enumvalues = { - 0: 'CMC_LUT_2_MODE_BYPASS', - 1: 'CMC_LUT_2_MODE_RAMA_LUT', - 2: 'CMC_LUT_2_MODE_RAMB_LUT', -} -CMC_LUT_2_MODE_BYPASS = 0 -CMC_LUT_2_MODE_RAMA_LUT = 1 -CMC_LUT_2_MODE_RAMB_LUT = 2 -CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_NUM_SEG' -CMC_LUT_NUM_SEG__enumvalues = { - 0: 'CMC_SEGMENTS_1', - 1: 'CMC_SEGMENTS_2', - 2: 'CMC_SEGMENTS_4', - 3: 'CMC_SEGMENTS_8', - 4: 'CMC_SEGMENTS_16', - 5: 'CMC_SEGMENTS_32', - 6: 'CMC_SEGMENTS_64', - 7: 'CMC_SEGMENTS_128', -} -CMC_SEGMENTS_1 = 0 -CMC_SEGMENTS_2 = 1 -CMC_SEGMENTS_4 = 2 -CMC_SEGMENTS_8 = 3 -CMC_SEGMENTS_16 = 4 -CMC_SEGMENTS_32 = 5 -CMC_SEGMENTS_64 = 6 -CMC_SEGMENTS_128 = 7 -CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CMC_LUT_RAM_SEL' -CMC_LUT_RAM_SEL__enumvalues = { - 0: 'CMC_RAMA_ACCESS', - 1: 'CMC_RAMB_ACCESS', -} -CMC_RAMA_ACCESS = 0 -CMC_RAMB_ACCESS = 1 -CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_BYPASS' -CM_BYPASS__enumvalues = { - 0: 'NON_BYPASS', - 1: 'BYPASS_EN', -} -NON_BYPASS = 0 -BYPASS_EN = 1 -CM_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'CM_COEF_FORMAT_ENUM' -CM_COEF_FORMAT_ENUM__enumvalues = { - 0: 'FIX_S2_13', - 1: 'FIX_S3_12', -} -FIX_S2_13 = 0 -FIX_S3_12 = 1 -CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_DATA_SIGNED' -CM_DATA_SIGNED__enumvalues = { - 0: 'UNSIGNED', - 1: 'SIGNED', -} -UNSIGNED = 0 -SIGNED = 1 -CM_DATA_SIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'CM_EN' -CM_EN__enumvalues = { - 0: 'CM_DISABLE', - 1: 'CM_ENABLE', -} -CM_DISABLE = 0 -CM_ENABLE = 1 -CM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' -CM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'BYPASS', - 1: 'RESERVED_1', - 2: 'RAM_LUT', - 3: 'RESERVED_3', -} -BYPASS = 0 -RESERVED_1 = 1 -RAM_LUT = 2 -RESERVED_3 = 3 -CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' -CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'ENABLE_PWL', - 1: 'DISABLE_PWL', -} -ENABLE_PWL = 0 -DISABLE_PWL = 1 -CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' -CM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'RAMA', - 1: 'RAMB', -} -RAMA = 0 -RAMB = 1 -CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' -CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'BYPASS_GAMUT', - 1: 'GAMUT_COEF', - 2: 'GAMUT_COEF_B', -} -BYPASS_GAMUT = 0 -GAMUT_COEF = 1 -GAMUT_COEF_B = 2 -CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_CONFIG_ENUM' -CM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'LUT_2CFG_NO_MEMORY', - 1: 'LUT_2CFG_MEMORY_A', - 2: 'LUT_2CFG_MEMORY_B', -} -LUT_2CFG_NO_MEMORY = 0 -LUT_2CFG_MEMORY_A = 1 -LUT_2CFG_MEMORY_B = 2 -CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_2_MODE_ENUM' -CM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'LUT_2_MODE_BYPASS', - 1: 'LUT_2_MODE_RAMA_LUT', - 2: 'LUT_2_MODE_RAMB_LUT', -} -LUT_2_MODE_BYPASS = 0 -LUT_2_MODE_RAMA_LUT = 1 -LUT_2_MODE_RAMB_LUT = 2 -CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_CONFIG_ENUM' -CM_LUT_4_CONFIG_ENUM__enumvalues = { - 0: 'LUT_4CFG_NO_MEMORY', - 1: 'LUT_4CFG_ROM_A', - 2: 'LUT_4CFG_ROM_B', - 3: 'LUT_4CFG_MEMORY_A', - 4: 'LUT_4CFG_MEMORY_B', -} -LUT_4CFG_NO_MEMORY = 0 -LUT_4CFG_ROM_A = 1 -LUT_4CFG_ROM_B = 2 -LUT_4CFG_MEMORY_A = 3 -LUT_4CFG_MEMORY_B = 4 -CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_4_MODE_ENUM' -CM_LUT_4_MODE_ENUM__enumvalues = { - 0: 'LUT_4_MODE_BYPASS', - 1: 'LUT_4_MODE_ROMA_LUT', - 2: 'LUT_4_MODE_ROMB_LUT', - 3: 'LUT_4_MODE_RAMA_LUT', - 4: 'LUT_4_MODE_RAMB_LUT', -} -LUT_4_MODE_BYPASS = 0 -LUT_4_MODE_ROMA_LUT = 1 -LUT_4_MODE_ROMB_LUT = 2 -LUT_4_MODE_RAMA_LUT = 3 -LUT_4_MODE_RAMB_LUT = 4 -CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_CONFIG_MODE' -CM_LUT_CONFIG_MODE__enumvalues = { - 0: 'DIFFERENT_RGB', - 1: 'ALL_USE_R', -} -DIFFERENT_RGB = 0 -ALL_USE_R = 1 -CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_NUM_SEG' -CM_LUT_NUM_SEG__enumvalues = { - 0: 'SEGMENTS_1', - 1: 'SEGMENTS_2', - 2: 'SEGMENTS_4', - 3: 'SEGMENTS_8', - 4: 'SEGMENTS_16', - 5: 'SEGMENTS_32', - 6: 'SEGMENTS_64', - 7: 'SEGMENTS_128', -} -SEGMENTS_1 = 0 -SEGMENTS_2 = 1 -SEGMENTS_4 = 2 -SEGMENTS_8 = 3 -SEGMENTS_16 = 4 -SEGMENTS_32 = 5 -SEGMENTS_64 = 6 -SEGMENTS_128 = 7 -CM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_RAM_SEL' -CM_LUT_RAM_SEL__enumvalues = { - 0: 'RAMA_ACCESS', - 1: 'RAMB_ACCESS', -} -RAMA_ACCESS = 0 -RAMB_ACCESS = 1 -CM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_COLOR_SEL' -CM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'BLUE_LUT', - 1: 'GREEN_LUT', - 2: 'RED_LUT', -} -BLUE_LUT = 0 -GREEN_LUT = 1 -RED_LUT = 2 -CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CM_LUT_READ_DBG' -CM_LUT_READ_DBG__enumvalues = { - 0: 'DISABLE_DEBUG', - 1: 'ENABLE_DEBUG', -} -DISABLE_DEBUG = 0 -ENABLE_DEBUG = 1 -CM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'CM_PENDING' -CM_PENDING__enumvalues = { - 0: 'CM_NOT_PENDING', - 1: 'CM_YES_PENDING', -} -CM_NOT_PENDING = 0 -CM_YES_PENDING = 1 -CM_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'CM_POST_CSC_MODE_ENUM' -CM_POST_CSC_MODE_ENUM__enumvalues = { - 0: 'BYPASS_POST_CSC', - 1: 'COEF_POST_CSC', - 2: 'COEF_POST_CSC_B', -} -BYPASS_POST_CSC = 0 -COEF_POST_CSC = 1 -COEF_POST_CSC_B = 2 -CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CM_WRITE_BASE_ONLY' -CM_WRITE_BASE_ONLY__enumvalues = { - 0: 'WRITE_BOTH', - 1: 'WRITE_BASE_ONLY', -} -WRITE_BOTH = 0 -WRITE_BASE_ONLY = 1 -CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_CUR_SEL' -CRC_CUR_SEL__enumvalues = { - 0: 'CRC_CUR_0', - 1: 'CRC_CUR_1', -} -CRC_CUR_0 = 0 -CRC_CUR_1 = 1 -CRC_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_INTERLACE_SEL' -CRC_INTERLACE_SEL__enumvalues = { - 0: 'CRC_INTERLACE_0', - 1: 'CRC_INTERLACE_1', - 2: 'CRC_INTERLACE_2', - 3: 'CRC_INTERLACE_3', -} -CRC_INTERLACE_0 = 0 -CRC_INTERLACE_1 = 1 -CRC_INTERLACE_2 = 2 -CRC_INTERLACE_3 = 3 -CRC_INTERLACE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_CUR_SEL' -CRC_IN_CUR_SEL__enumvalues = { - 0: 'CRC_IN_CUR_0', - 1: 'CRC_IN_CUR_1', - 2: 'CRC_IN_CUR_2', - 3: 'CRC_IN_CUR_3', -} -CRC_IN_CUR_0 = 0 -CRC_IN_CUR_1 = 1 -CRC_IN_CUR_2 = 2 -CRC_IN_CUR_3 = 3 -CRC_IN_CUR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_IN_PIX_SEL' -CRC_IN_PIX_SEL__enumvalues = { - 0: 'CRC_IN_PIX_0', - 1: 'CRC_IN_PIX_1', - 2: 'CRC_IN_PIX_2', - 3: 'CRC_IN_PIX_3', - 4: 'CRC_IN_PIX_4', - 5: 'CRC_IN_PIX_5', - 6: 'CRC_IN_PIX_6', - 7: 'CRC_IN_PIX_7', -} -CRC_IN_PIX_0 = 0 -CRC_IN_PIX_1 = 1 -CRC_IN_PIX_2 = 2 -CRC_IN_PIX_3 = 3 -CRC_IN_PIX_4 = 4 -CRC_IN_PIX_5 = 5 -CRC_IN_PIX_6 = 6 -CRC_IN_PIX_7 = 7 -CRC_IN_PIX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_SRC_SEL' -CRC_SRC_SEL__enumvalues = { - 0: 'CRC_SRC_0', - 1: 'CRC_SRC_1', - 2: 'CRC_SRC_2', - 3: 'CRC_SRC_3', -} -CRC_SRC_0 = 0 -CRC_SRC_1 = 1 -CRC_SRC_2 = 2 -CRC_SRC_3 = 3 -CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CRC_STEREO_SEL' -CRC_STEREO_SEL__enumvalues = { - 0: 'CRC_STEREO_0', - 1: 'CRC_STEREO_1', - 2: 'CRC_STEREO_2', - 3: 'CRC_STEREO_3', -} -CRC_STEREO_0 = 0 -CRC_STEREO_1 = 1 -CRC_STEREO_2 = 2 -CRC_STEREO_3 = 3 -CRC_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_SEL' -TEST_CLK_SEL__enumvalues = { - 0: 'TEST_CLK_SEL_0', - 1: 'TEST_CLK_SEL_1', - 2: 'TEST_CLK_SEL_2', - 3: 'TEST_CLK_SEL_3', - 4: 'TEST_CLK_SEL_4', - 5: 'TEST_CLK_SEL_5', - 6: 'TEST_CLK_SEL_6', - 7: 'TEST_CLK_SEL_7', -} -TEST_CLK_SEL_0 = 0 -TEST_CLK_SEL_1 = 1 -TEST_CLK_SEL_2 = 2 -TEST_CLK_SEL_3 = 3 -TEST_CLK_SEL_4 = 4 -TEST_CLK_SEL_5 = 5 -TEST_CLK_SEL_6 = 6 -TEST_CLK_SEL_7 = 7 -TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_ACTIVE' -PERFCOUNTER_ACTIVE__enumvalues = { - 0: 'PERFCOUNTER_IS_IDLE', - 1: 'PERFCOUNTER_IS_ACTIVE', -} -PERFCOUNTER_IS_IDLE = 0 -PERFCOUNTER_IS_ACTIVE = 1 -PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT0_STATE' -PERFCOUNTER_CNT0_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT0_STATE_RESET', - 1: 'PERFCOUNTER_CNT0_STATE_START', - 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT0_STATE_HW', -} -PERFCOUNTER_CNT0_STATE_RESET = 0 -PERFCOUNTER_CNT0_STATE_START = 1 -PERFCOUNTER_CNT0_STATE_FREEZE = 2 -PERFCOUNTER_CNT0_STATE_HW = 3 -PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT1_STATE' -PERFCOUNTER_CNT1_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT1_STATE_RESET', - 1: 'PERFCOUNTER_CNT1_STATE_START', - 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT1_STATE_HW', -} -PERFCOUNTER_CNT1_STATE_RESET = 0 -PERFCOUNTER_CNT1_STATE_START = 1 -PERFCOUNTER_CNT1_STATE_FREEZE = 2 -PERFCOUNTER_CNT1_STATE_HW = 3 -PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT2_STATE' -PERFCOUNTER_CNT2_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT2_STATE_RESET', - 1: 'PERFCOUNTER_CNT2_STATE_START', - 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT2_STATE_HW', -} -PERFCOUNTER_CNT2_STATE_RESET = 0 -PERFCOUNTER_CNT2_STATE_START = 1 -PERFCOUNTER_CNT2_STATE_FREEZE = 2 -PERFCOUNTER_CNT2_STATE_HW = 3 -PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT3_STATE' -PERFCOUNTER_CNT3_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT3_STATE_RESET', - 1: 'PERFCOUNTER_CNT3_STATE_START', - 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT3_STATE_HW', -} -PERFCOUNTER_CNT3_STATE_RESET = 0 -PERFCOUNTER_CNT3_STATE_START = 1 -PERFCOUNTER_CNT3_STATE_FREEZE = 2 -PERFCOUNTER_CNT3_STATE_HW = 3 -PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT4_STATE' -PERFCOUNTER_CNT4_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT4_STATE_RESET', - 1: 'PERFCOUNTER_CNT4_STATE_START', - 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT4_STATE_HW', -} -PERFCOUNTER_CNT4_STATE_RESET = 0 -PERFCOUNTER_CNT4_STATE_START = 1 -PERFCOUNTER_CNT4_STATE_FREEZE = 2 -PERFCOUNTER_CNT4_STATE_HW = 3 -PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT5_STATE' -PERFCOUNTER_CNT5_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT5_STATE_RESET', - 1: 'PERFCOUNTER_CNT5_STATE_START', - 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT5_STATE_HW', -} -PERFCOUNTER_CNT5_STATE_RESET = 0 -PERFCOUNTER_CNT5_STATE_START = 1 -PERFCOUNTER_CNT5_STATE_FREEZE = 2 -PERFCOUNTER_CNT5_STATE_HW = 3 -PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT6_STATE' -PERFCOUNTER_CNT6_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT6_STATE_RESET', - 1: 'PERFCOUNTER_CNT6_STATE_START', - 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT6_STATE_HW', -} -PERFCOUNTER_CNT6_STATE_RESET = 0 -PERFCOUNTER_CNT6_STATE_START = 1 -PERFCOUNTER_CNT6_STATE_FREEZE = 2 -PERFCOUNTER_CNT6_STATE_HW = 3 -PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNT7_STATE' -PERFCOUNTER_CNT7_STATE__enumvalues = { - 0: 'PERFCOUNTER_CNT7_STATE_RESET', - 1: 'PERFCOUNTER_CNT7_STATE_START', - 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', - 3: 'PERFCOUNTER_CNT7_STATE_HW', -} -PERFCOUNTER_CNT7_STATE_RESET = 0 -PERFCOUNTER_CNT7_STATE_START = 1 -PERFCOUNTER_CNT7_STATE_FREEZE = 2 -PERFCOUNTER_CNT7_STATE_HW = 3 -PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTL_SEL' -PERFCOUNTER_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_CNTL_SEL_0', - 1: 'PERFCOUNTER_CNTL_SEL_1', - 2: 'PERFCOUNTER_CNTL_SEL_2', - 3: 'PERFCOUNTER_CNTL_SEL_3', - 4: 'PERFCOUNTER_CNTL_SEL_4', - 5: 'PERFCOUNTER_CNTL_SEL_5', - 6: 'PERFCOUNTER_CNTL_SEL_6', - 7: 'PERFCOUNTER_CNTL_SEL_7', -} -PERFCOUNTER_CNTL_SEL_0 = 0 -PERFCOUNTER_CNTL_SEL_1 = 1 -PERFCOUNTER_CNTL_SEL_2 = 2 -PERFCOUNTER_CNTL_SEL_3 = 3 -PERFCOUNTER_CNTL_SEL_4 = 4 -PERFCOUNTER_CNTL_SEL_5 = 5 -PERFCOUNTER_CNTL_SEL_6 = 6 -PERFCOUNTER_CNTL_SEL_7 = 7 -PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' -PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { - 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', - 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', -} -PERFCOUNTER_CNTOFF_START_ENABLE = 0 -PERFCOUNTER_CNTOFF_START_DISABLE = 1 -PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' -PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { - 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', -} -PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 -PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 -PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 -PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_CVALUE_SEL' -PERFCOUNTER_CVALUE_SEL__enumvalues = { - 0: 'PERFCOUNTER_CVALUE_SEL_47_0', - 1: 'PERFCOUNTER_CVALUE_SEL_15_0', - 2: 'PERFCOUNTER_CVALUE_SEL_31_16', - 3: 'PERFCOUNTER_CVALUE_SEL_47_32', - 4: 'PERFCOUNTER_CVALUE_SEL_11_0', - 5: 'PERFCOUNTER_CVALUE_SEL_23_12', - 6: 'PERFCOUNTER_CVALUE_SEL_35_24', - 7: 'PERFCOUNTER_CVALUE_SEL_47_36', -} -PERFCOUNTER_CVALUE_SEL_47_0 = 0 -PERFCOUNTER_CVALUE_SEL_15_0 = 1 -PERFCOUNTER_CVALUE_SEL_31_16 = 2 -PERFCOUNTER_CVALUE_SEL_47_32 = 3 -PERFCOUNTER_CVALUE_SEL_11_0 = 4 -PERFCOUNTER_CVALUE_SEL_23_12 = 5 -PERFCOUNTER_CVALUE_SEL_35_24 = 6 -PERFCOUNTER_CVALUE_SEL_47_36 = 7 -PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' -PERFCOUNTER_HW_CNTL_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', - 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', -} -PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 -PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 -PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' -PERFCOUNTER_HW_STOP1_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP1_0', - 1: 'PERFCOUNTER_HW_STOP1_1', -} -PERFCOUNTER_HW_STOP1_0 = 0 -PERFCOUNTER_HW_STOP1_1 = 1 -PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' -PERFCOUNTER_HW_STOP2_SEL__enumvalues = { - 0: 'PERFCOUNTER_HW_STOP2_0', - 1: 'PERFCOUNTER_HW_STOP2_1', -} -PERFCOUNTER_HW_STOP2_0 = 0 -PERFCOUNTER_HW_STOP2_1 = 1 -PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INC_MODE' -PERFCOUNTER_INC_MODE__enumvalues = { - 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', - 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', - 2: 'PERFCOUNTER_INC_MODE_LSB', - 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', - 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', -} -PERFCOUNTER_INC_MODE_MULTI_BIT = 0 -PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 -PERFCOUNTER_INC_MODE_LSB = 2 -PERFCOUNTER_INC_MODE_POS_EDGE = 3 -PERFCOUNTER_INC_MODE_NEG_EDGE = 4 -PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_EN' -PERFCOUNTER_INT_EN__enumvalues = { - 0: 'PERFCOUNTER_INT_DISABLE', - 1: 'PERFCOUNTER_INT_ENABLE', -} -PERFCOUNTER_INT_DISABLE = 0 -PERFCOUNTER_INT_ENABLE = 1 -PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_INT_TYPE' -PERFCOUNTER_INT_TYPE__enumvalues = { - 0: 'PERFCOUNTER_INT_TYPE_LEVEL', - 1: 'PERFCOUNTER_INT_TYPE_PULSE', -} -PERFCOUNTER_INT_TYPE_LEVEL = 0 -PERFCOUNTER_INT_TYPE_PULSE = 1 -PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_OFF_MASK' -PERFCOUNTER_OFF_MASK__enumvalues = { - 0: 'PERFCOUNTER_OFF_MASK_DISABLE', - 1: 'PERFCOUNTER_OFF_MASK_ENABLE', -} -PERFCOUNTER_OFF_MASK_DISABLE = 0 -PERFCOUNTER_OFF_MASK_ENABLE = 1 -PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RESTART_EN' -PERFCOUNTER_RESTART_EN__enumvalues = { - 0: 'PERFCOUNTER_RESTART_DISABLE', - 1: 'PERFCOUNTER_RESTART_ENABLE', -} -PERFCOUNTER_RESTART_DISABLE = 0 -PERFCOUNTER_RESTART_ENABLE = 1 -PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_RUNEN_MODE' -PERFCOUNTER_RUNEN_MODE__enumvalues = { - 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', -} -PERFCOUNTER_RUNEN_MODE_LEVEL = 0 -PERFCOUNTER_RUNEN_MODE_EDGE = 1 -PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL0' -PERFCOUNTER_STATE_SEL0__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', -} -PERFCOUNTER_STATE_SEL0_GLOBAL = 0 -PERFCOUNTER_STATE_SEL0_LOCAL = 1 -PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL1' -PERFCOUNTER_STATE_SEL1__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', -} -PERFCOUNTER_STATE_SEL1_GLOBAL = 0 -PERFCOUNTER_STATE_SEL1_LOCAL = 1 -PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL2' -PERFCOUNTER_STATE_SEL2__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', -} -PERFCOUNTER_STATE_SEL2_GLOBAL = 0 -PERFCOUNTER_STATE_SEL2_LOCAL = 1 -PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL3' -PERFCOUNTER_STATE_SEL3__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', -} -PERFCOUNTER_STATE_SEL3_GLOBAL = 0 -PERFCOUNTER_STATE_SEL3_LOCAL = 1 -PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL4' -PERFCOUNTER_STATE_SEL4__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', -} -PERFCOUNTER_STATE_SEL4_GLOBAL = 0 -PERFCOUNTER_STATE_SEL4_LOCAL = 1 -PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL5' -PERFCOUNTER_STATE_SEL5__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', -} -PERFCOUNTER_STATE_SEL5_GLOBAL = 0 -PERFCOUNTER_STATE_SEL5_LOCAL = 1 -PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL6' -PERFCOUNTER_STATE_SEL6__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', -} -PERFCOUNTER_STATE_SEL6_GLOBAL = 0 -PERFCOUNTER_STATE_SEL6_LOCAL = 1 -PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFCOUNTER_STATE_SEL7' -PERFCOUNTER_STATE_SEL7__enumvalues = { - 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', - 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', -} -PERFCOUNTER_STATE_SEL7_GLOBAL = 0 -PERFCOUNTER_STATE_SEL7_LOCAL = 1 -PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_AND_OR' -PERFMON_CNTOFF_AND_OR__enumvalues = { - 0: 'PERFMON_CNTOFF_OR', - 1: 'PERFMON_CNTOFF_AND', -} -PERFMON_CNTOFF_OR = 0 -PERFMON_CNTOFF_AND = 1 -PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_EN' -PERFMON_CNTOFF_INT_EN__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_DISABLE', - 1: 'PERFMON_CNTOFF_INT_ENABLE', -} -PERFMON_CNTOFF_INT_DISABLE = 0 -PERFMON_CNTOFF_INT_ENABLE = 1 -PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' -PERFMON_CNTOFF_INT_TYPE__enumvalues = { - 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', - 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', -} -PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 -PERFMON_CNTOFF_INT_TYPE_PULSE = 1 -PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'PERFMON_STATE' -PERFMON_STATE__enumvalues = { - 0: 'PERFMON_STATE_RESET', - 1: 'PERFMON_STATE_START', - 2: 'PERFMON_STATE_FREEZE', - 3: 'PERFMON_STATE_HW', -} -PERFMON_STATE_RESET = 0 -PERFMON_STATE_START = 1 -PERFMON_STATE_FREEZE = 2 -PERFMON_STATE_HW = 3 -PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'BIGK_FRAGMENT_SIZE' -BIGK_FRAGMENT_SIZE__enumvalues = { - 0: 'VM_PG_SIZE_4KB', - 1: 'VM_PG_SIZE_8KB', - 2: 'VM_PG_SIZE_16KB', - 3: 'VM_PG_SIZE_32KB', - 4: 'VM_PG_SIZE_64KB', - 5: 'VM_PG_SIZE_128KB', - 6: 'VM_PG_SIZE_256KB', - 7: 'VM_PG_SIZE_512KB', - 8: 'VM_PG_SIZE_1024KB', - 9: 'VM_PG_SIZE_2048KB', -} -VM_PG_SIZE_4KB = 0 -VM_PG_SIZE_8KB = 1 -VM_PG_SIZE_16KB = 2 -VM_PG_SIZE_32KB = 3 -VM_PG_SIZE_64KB = 4 -VM_PG_SIZE_128KB = 5 -VM_PG_SIZE_256KB = 6 -VM_PG_SIZE_512KB = 7 -VM_PG_SIZE_1024KB = 8 -VM_PG_SIZE_2048KB = 9 -BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CHUNK_SIZE' -CHUNK_SIZE__enumvalues = { - 0: 'CHUNK_SIZE_1KB', - 1: 'CHUNK_SIZE_2KB', - 2: 'CHUNK_SIZE_4KB', - 3: 'CHUNK_SIZE_8KB', - 4: 'CHUNK_SIZE_16KB', - 5: 'CHUNK_SIZE_32KB', - 6: 'CHUNK_SIZE_64KB', -} -CHUNK_SIZE_1KB = 0 -CHUNK_SIZE_2KB = 1 -CHUNK_SIZE_4KB = 2 -CHUNK_SIZE_8KB = 3 -CHUNK_SIZE_16KB = 4 -CHUNK_SIZE_32KB = 5 -CHUNK_SIZE_64KB = 6 -CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'COMPAT_LEVEL' -COMPAT_LEVEL__enumvalues = { - 0: 'ADDR_GEN_ZERO', - 1: 'ADDR_GEN_ONE', - 2: 'ADDR_GEN_TWO', - 3: 'ADDR_RESERVED', -} -ADDR_GEN_ZERO = 0 -ADDR_GEN_ONE = 1 -ADDR_GEN_TWO = 2 -ADDR_RESERVED = 3 -COMPAT_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPTE_GROUP_SIZE' -DPTE_GROUP_SIZE__enumvalues = { - 0: 'DPTE_GROUP_SIZE_64B', - 1: 'DPTE_GROUP_SIZE_128B', - 2: 'DPTE_GROUP_SIZE_256B', - 3: 'DPTE_GROUP_SIZE_512B', - 4: 'DPTE_GROUP_SIZE_1024B', - 5: 'DPTE_GROUP_SIZE_2048B', -} -DPTE_GROUP_SIZE_64B = 0 -DPTE_GROUP_SIZE_128B = 1 -DPTE_GROUP_SIZE_256B = 2 -DPTE_GROUP_SIZE_512B = 3 -DPTE_GROUP_SIZE_1024B = 4 -DPTE_GROUP_SIZE_2048B = 5 -DPTE_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' -FORCE_ONE_ROW_FOR_FRAME__enumvalues = { - 0: 'FORCE_ONE_ROW_FOR_FRAME_0', - 1: 'FORCE_ONE_ROW_FOR_FRAME_1', -} -FORCE_ONE_ROW_FOR_FRAME_0 = 0 -FORCE_ONE_ROW_FOR_FRAME_1 = 1 -FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_BLANK_EN' -HUBP_BLANK_EN__enumvalues = { - 0: 'HUBP_BLANK_SW_DEASSERT', - 1: 'HUBP_BLANK_SW_ASSERT', -} -HUBP_BLANK_SW_DEASSERT = 0 -HUBP_BLANK_SW_ASSERT = 1 -HUBP_BLANK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_IN_BLANK' -HUBP_IN_BLANK__enumvalues = { - 0: 'HUBP_IN_ACTIVE', - 1: 'HUBP_IN_VBLANK', -} -HUBP_IN_ACTIVE = 0 -HUBP_IN_VBLANK = 1 -HUBP_IN_BLANK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' -HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { - 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', -} -HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 -HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 -HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 -HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 -HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' -HUBP_NO_OUTSTANDING_REQ__enumvalues = { - 0: 'OUTSTANDING_REQ', - 1: 'NO_OUTSTANDING_REQ', -} -OUTSTANDING_REQ = 0 -NO_OUTSTANDING_REQ = 1 -HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_SOFT_RESET' -HUBP_SOFT_RESET__enumvalues = { - 0: 'HUBP_SOFT_RESET_ON', - 1: 'HUBP_SOFT_RESET_OFF', -} -HUBP_SOFT_RESET_ON = 0 -HUBP_SOFT_RESET_OFF = 1 -HUBP_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_TTU_DISABLE' -HUBP_TTU_DISABLE__enumvalues = { - 0: 'HUBP_TTU_ENABLED', - 1: 'HUBP_TTU_DISABLED', -} -HUBP_TTU_ENABLED = 0 -HUBP_TTU_DISABLED = 1 -HUBP_TTU_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' -HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { - 0: 'VREADY_BEFORE_VSYNC', - 1: 'VREADY_AT_OR_AFTER_VSYNC', -} -VREADY_BEFORE_VSYNC = 0 -VREADY_AT_OR_AFTER_VSYNC = 1 -HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'HUBP_VTG_SEL' -HUBP_VTG_SEL__enumvalues = { - 0: 'VTG_SEL_0', - 1: 'VTG_SEL_1', - 2: 'VTG_SEL_2', - 3: 'VTG_SEL_3', - 4: 'VTG_SEL_4', - 5: 'VTG_SEL_5', -} -VTG_SEL_0 = 0 -VTG_SEL_1 = 1 -VTG_SEL_2 = 2 -VTG_SEL_3 = 3 -VTG_SEL_4 = 4 -VTG_SEL_5 = 5 -HUBP_VTG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'H_MIRROR_EN' -H_MIRROR_EN__enumvalues = { - 0: 'HW_MIRRORING_DISABLE', - 1: 'HW_MIRRORING_ENABLE', -} -HW_MIRRORING_DISABLE = 0 -HW_MIRRORING_ENABLE = 1 -H_MIRROR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'LEGACY_PIPE_INTERLEAVE' -LEGACY_PIPE_INTERLEAVE__enumvalues = { - 0: 'LEGACY_PIPE_INTERLEAVE_256B', - 1: 'LEGACY_PIPE_INTERLEAVE_512B', -} -LEGACY_PIPE_INTERLEAVE_256B = 0 -LEGACY_PIPE_INTERLEAVE_512B = 1 -LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum - -# values for enumeration 'META_CHUNK_SIZE' -META_CHUNK_SIZE__enumvalues = { - 0: 'META_CHUNK_SIZE_1KB', - 1: 'META_CHUNK_SIZE_2KB', - 2: 'META_CHUNK_SIZE_4KB', - 3: 'META_CHUNK_SIZE_8KB', -} -META_CHUNK_SIZE_1KB = 0 -META_CHUNK_SIZE_2KB = 1 -META_CHUNK_SIZE_4KB = 2 -META_CHUNK_SIZE_8KB = 3 -META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'META_LINEAR' -META_LINEAR__enumvalues = { - 0: 'META_SURF_TILED', - 1: 'META_SURF_LINEAR', -} -META_SURF_TILED = 0 -META_SURF_LINEAR = 1 -META_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_CHUNK_SIZE' -MIN_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_CHUNK_SIZE', - 1: 'MIN_CHUNK_SIZE_256B', - 2: 'MIN_CHUNK_SIZE_512B', - 3: 'MIN_CHUNK_SIZE_1024B', -} -NO_MIN_CHUNK_SIZE = 0 -MIN_CHUNK_SIZE_256B = 1 -MIN_CHUNK_SIZE_512B = 2 -MIN_CHUNK_SIZE_1024B = 3 -MIN_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'MIN_META_CHUNK_SIZE' -MIN_META_CHUNK_SIZE__enumvalues = { - 0: 'NO_MIN_META_CHUNK_SIZE', - 1: 'MIN_META_CHUNK_SIZE_64B', - 2: 'MIN_META_CHUNK_SIZE_128B', - 3: 'MIN_META_CHUNK_SIZE_256B', -} -NO_MIN_META_CHUNK_SIZE = 0 -MIN_META_CHUNK_SIZE_64B = 1 -MIN_META_CHUNK_SIZE_128B = 2 -MIN_META_CHUNK_SIZE_256B = 3 -MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_ALIGNED' -PIPE_ALIGNED__enumvalues = { - 0: 'PIPE_UNALIGNED_SURF', - 1: 'PIPE_ALIGNED_SURF', -} -PIPE_UNALIGNED_SURF = 0 -PIPE_ALIGNED_SURF = 1 -PIPE_ALIGNED = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_BUFFER_MODE' -PTE_BUFFER_MODE__enumvalues = { - 0: 'PTE_BUFFER_MODE_0', - 1: 'PTE_BUFFER_MODE_1', -} -PTE_BUFFER_MODE_0 = 0 -PTE_BUFFER_MODE_1 = 1 -PTE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' -PTE_ROW_HEIGHT_LINEAR__enumvalues = { - 0: 'PTE_ROW_HEIGHT_LINEAR_8L', - 1: 'PTE_ROW_HEIGHT_LINEAR_16L', - 2: 'PTE_ROW_HEIGHT_LINEAR_32L', - 3: 'PTE_ROW_HEIGHT_LINEAR_64L', - 4: 'PTE_ROW_HEIGHT_LINEAR_128L', - 5: 'PTE_ROW_HEIGHT_LINEAR_256L', - 6: 'PTE_ROW_HEIGHT_LINEAR_512L', - 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', -} -PTE_ROW_HEIGHT_LINEAR_8L = 0 -PTE_ROW_HEIGHT_LINEAR_16L = 1 -PTE_ROW_HEIGHT_LINEAR_32L = 2 -PTE_ROW_HEIGHT_LINEAR_64L = 3 -PTE_ROW_HEIGHT_LINEAR_128L = 4 -PTE_ROW_HEIGHT_LINEAR_256L = 5 -PTE_ROW_HEIGHT_LINEAR_512L = 6 -PTE_ROW_HEIGHT_LINEAR_1024L = 7 -PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum - -# values for enumeration 'ROTATION_ANGLE' -ROTATION_ANGLE__enumvalues = { - 0: 'ROTATE_0_DEGREES', - 1: 'ROTATE_90_DEGREES', - 2: 'ROTATE_180_DEGREES', - 3: 'ROTATE_270_DEGREES', -} -ROTATE_0_DEGREES = 0 -ROTATE_90_DEGREES = 1 -ROTATE_180_DEGREES = 2 -ROTATE_270_DEGREES = 3 -ROTATION_ANGLE = ctypes.c_uint32 # enum - -# values for enumeration 'SWATH_HEIGHT' -SWATH_HEIGHT__enumvalues = { - 0: 'SWATH_HEIGHT_1L', - 1: 'SWATH_HEIGHT_2L', - 2: 'SWATH_HEIGHT_4L', - 3: 'SWATH_HEIGHT_8L', - 4: 'SWATH_HEIGHT_16L', -} -SWATH_HEIGHT_1L = 0 -SWATH_HEIGHT_2L = 1 -SWATH_HEIGHT_4L = 2 -SWATH_HEIGHT_8L = 3 -SWATH_HEIGHT_16L = 4 -SWATH_HEIGHT = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_CURSOR' -USE_MALL_FOR_CURSOR__enumvalues = { - 0: 'USE_MALL_FOR_CURSOR_0', - 1: 'USE_MALL_FOR_CURSOR_1', -} -USE_MALL_FOR_CURSOR_0 = 0 -USE_MALL_FOR_CURSOR_1 = 1 -USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE' -USE_MALL_FOR_PSTATE_CHANGE__enumvalues = { - 0: 'USE_MALL_FOR_PSTATE_CHANGE_0', - 1: 'USE_MALL_FOR_PSTATE_CHANGE_1', -} -USE_MALL_FOR_PSTATE_CHANGE_0 = 0 -USE_MALL_FOR_PSTATE_CHANGE_1 = 1 -USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum - -# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN' -USE_MALL_FOR_STATIC_SCREEN__enumvalues = { - 0: 'USE_MALL_FOR_STATIC_SCREEN_0', - 1: 'USE_MALL_FOR_STATIC_SCREEN_1', -} -USE_MALL_FOR_STATIC_SCREEN_0 = 0 -USE_MALL_FOR_STATIC_SCREEN_1 = 1 -USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum - -# values for enumeration 'VMPG_SIZE' -VMPG_SIZE__enumvalues = { - 0: 'VMPG_SIZE_4KB', - 1: 'VMPG_SIZE_64KB', -} -VMPG_SIZE_4KB = 0 -VMPG_SIZE_64KB = 1 -VMPG_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VM_GROUP_SIZE' -VM_GROUP_SIZE__enumvalues = { - 0: 'VM_GROUP_SIZE_64B', - 1: 'VM_GROUP_SIZE_128B', - 2: 'VM_GROUP_SIZE_256B', - 3: 'VM_GROUP_SIZE_512B', - 4: 'VM_GROUP_SIZE_1024B', - 5: 'VM_GROUP_SIZE_2048B', -} -VM_GROUP_SIZE_64B = 0 -VM_GROUP_SIZE_128B = 1 -VM_GROUP_SIZE_256B = 2 -VM_GROUP_SIZE_512B = 3 -VM_GROUP_SIZE_1024B = 4 -VM_GROUP_SIZE_2048B = 5 -VM_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_MIN_FREE_ENTRIES' -DFQ_MIN_FREE_ENTRIES__enumvalues = { - 0: 'DFQ_MIN_FREE_ENTRIES_0', - 1: 'DFQ_MIN_FREE_ENTRIES_1', - 2: 'DFQ_MIN_FREE_ENTRIES_2', - 3: 'DFQ_MIN_FREE_ENTRIES_3', - 4: 'DFQ_MIN_FREE_ENTRIES_4', - 5: 'DFQ_MIN_FREE_ENTRIES_5', - 6: 'DFQ_MIN_FREE_ENTRIES_6', - 7: 'DFQ_MIN_FREE_ENTRIES_7', -} -DFQ_MIN_FREE_ENTRIES_0 = 0 -DFQ_MIN_FREE_ENTRIES_1 = 1 -DFQ_MIN_FREE_ENTRIES_2 = 2 -DFQ_MIN_FREE_ENTRIES_3 = 3 -DFQ_MIN_FREE_ENTRIES_4 = 4 -DFQ_MIN_FREE_ENTRIES_5 = 5 -DFQ_MIN_FREE_ENTRIES_6 = 6 -DFQ_MIN_FREE_ENTRIES_7 = 7 -DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_NUM_ENTRIES' -DFQ_NUM_ENTRIES__enumvalues = { - 0: 'DFQ_NUM_ENTRIES_0', - 1: 'DFQ_NUM_ENTRIES_1', - 2: 'DFQ_NUM_ENTRIES_2', - 3: 'DFQ_NUM_ENTRIES_3', - 4: 'DFQ_NUM_ENTRIES_4', - 5: 'DFQ_NUM_ENTRIES_5', - 6: 'DFQ_NUM_ENTRIES_6', - 7: 'DFQ_NUM_ENTRIES_7', - 8: 'DFQ_NUM_ENTRIES_8', -} -DFQ_NUM_ENTRIES_0 = 0 -DFQ_NUM_ENTRIES_1 = 1 -DFQ_NUM_ENTRIES_2 = 2 -DFQ_NUM_ENTRIES_3 = 3 -DFQ_NUM_ENTRIES_4 = 4 -DFQ_NUM_ENTRIES_5 = 5 -DFQ_NUM_ENTRIES_6 = 6 -DFQ_NUM_ENTRIES_7 = 7 -DFQ_NUM_ENTRIES_8 = 8 -DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum - -# values for enumeration 'DFQ_SIZE' -DFQ_SIZE__enumvalues = { - 0: 'DFQ_SIZE_0', - 1: 'DFQ_SIZE_1', - 2: 'DFQ_SIZE_2', - 3: 'DFQ_SIZE_3', - 4: 'DFQ_SIZE_4', - 5: 'DFQ_SIZE_5', - 6: 'DFQ_SIZE_6', - 7: 'DFQ_SIZE_7', -} -DFQ_SIZE_0 = 0 -DFQ_SIZE_1 = 1 -DFQ_SIZE_2 = 2 -DFQ_SIZE_3 = 3 -DFQ_SIZE_4 = 4 -DFQ_SIZE_5 = 5 -DFQ_SIZE_6 = 6 -DFQ_SIZE_7 = 7 -DFQ_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_VM_DONE' -DMDATA_VM_DONE__enumvalues = { - 0: 'DMDATA_VM_IS_NOT_DONE', - 1: 'DMDATA_VM_IS_DONE', -} -DMDATA_VM_IS_NOT_DONE = 0 -DMDATA_VM_IS_DONE = 1 -DMDATA_VM_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'EXPANSION_MODE' -EXPANSION_MODE__enumvalues = { - 0: 'EXPANSION_MODE_ZERO', - 1: 'EXPANSION_MODE_CONSERVATIVE', - 2: 'EXPANSION_MODE_OPTIMAL', -} -EXPANSION_MODE_ZERO = 0 -EXPANSION_MODE_CONSERVATIVE = 1 -EXPANSION_MODE_OPTIMAL = 2 -EXPANSION_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FLIP_RATE' -FLIP_RATE__enumvalues = { - 0: 'FLIP_RATE_0', - 1: 'FLIP_RATE_1', - 2: 'FLIP_RATE_2', - 3: 'FLIP_RATE_3', - 4: 'FLIP_RATE_4', - 5: 'FLIP_RATE_5', - 6: 'FLIP_RATE_6', - 7: 'FLIP_RATE_7', -} -FLIP_RATE_0 = 0 -FLIP_RATE_1 = 1 -FLIP_RATE_2 = 2 -FLIP_RATE_3 = 3 -FLIP_RATE_4 = 4 -FLIP_RATE_5 = 5 -FLIP_RATE_6 = 6 -FLIP_RATE_7 = 7 -FLIP_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'INT_MASK' -INT_MASK__enumvalues = { - 0: 'INT_DISABLED', - 1: 'INT_ENABLED', -} -INT_DISABLED = 0 -INT_ENABLED = 1 -INT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_IN_FLUSH_URGENT' -PIPE_IN_FLUSH_URGENT__enumvalues = { - 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', - 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', -} -PIPE_IN_FLUSH_URGENT_ENABLE = 0 -PIPE_IN_FLUSH_URGENT_DISABLE = 1 -PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' -PRQ_MRQ_FLUSH_URGENT__enumvalues = { - 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', - 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', -} -PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 -PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 -PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum - -# values for enumeration 'ROW_TTU_MODE' -ROW_TTU_MODE__enumvalues = { - 0: 'END_OF_ROW_MODE', - 1: 'WATERMARK_MODE', -} -END_OF_ROW_MODE = 0 -WATERMARK_MODE = 1 -ROW_TTU_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC' -SURFACE_DCC__enumvalues = { - 0: 'SURFACE_IS_NOT_DCC', - 1: 'SURFACE_IS_DCC', -} -SURFACE_IS_NOT_DCC = 0 -SURFACE_IS_DCC = 1 -SURFACE_DCC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_128B' -SURFACE_DCC_IND_128B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_128B', - 1: 'SURFACE_DCC_IS_IND_128B', -} -SURFACE_DCC_IS_NOT_IND_128B = 0 -SURFACE_DCC_IS_IND_128B = 1 -SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_64B' -SURFACE_DCC_IND_64B__enumvalues = { - 0: 'SURFACE_DCC_IS_NOT_IND_64B', - 1: 'SURFACE_DCC_IS_IND_64B', -} -SURFACE_DCC_IS_NOT_IND_64B = 0 -SURFACE_DCC_IS_IND_64B = 1 -SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_DCC_IND_BLK' -SURFACE_DCC_IND_BLK__enumvalues = { - 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', - 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', - 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', - 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', -} -SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 -SURFACE_DCC_BLOCK_IS_IND_64B = 1 -SURFACE_DCC_BLOCK_IS_IND_128B = 2 -SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 -SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' -SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', - 1: 'SURFACE_FLIP_AWAY_INT_PULSE', -} -SURFACE_FLIP_AWAY_INT_LEVEL = 0 -SURFACE_FLIP_AWAY_INT_PULSE = 1 -SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' -SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { - 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', - 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', -} -SURFACE_FLIP_EXEC_NORMAL_MODE = 0 -SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 -SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_INT_TYPE' -SURFACE_FLIP_INT_TYPE__enumvalues = { - 0: 'SURFACE_FLIP_INT_LEVEL', - 1: 'SURFACE_FLIP_INT_PULSE', -} -SURFACE_FLIP_INT_LEVEL = 0 -SURFACE_FLIP_INT_PULSE = 1 -SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' -SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { - 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', -} -SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 -SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 -SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' -SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { - 0: 'FLIP_ANY_FRAME', - 1: 'FLIP_LEFT_EYE', - 2: 'FLIP_RIGHT_EYE', - 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', -} -FLIP_ANY_FRAME = 0 -FLIP_LEFT_EYE = 1 -FLIP_RIGHT_EYE = 2 -SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 -SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' -SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', -} -SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 -SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 -SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' -SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { - 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', -} -SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 -SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 -SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_TYPE' -SURFACE_FLIP_TYPE__enumvalues = { - 0: 'SURFACE_V_FLIP', - 1: 'SURFACE_I_FLIP', -} -SURFACE_V_FLIP = 0 -SURFACE_I_FLIP = 1 -SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' -SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { - 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', - 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', -} -SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 -SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 -SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 -SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 -SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 -SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 -SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 -SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 -SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 -SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 -SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 -SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 -SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 -SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 -SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 -SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 -SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' -SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { - 0: 'SURFACE_INUSE_IS_LATCHED', - 1: 'SURFACE_INUSE_IS_NOT_LATCHED', -} -SURFACE_INUSE_IS_LATCHED = 0 -SURFACE_INUSE_IS_NOT_LATCHED = 1 -SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_TMZ' -SURFACE_TMZ__enumvalues = { - 0: 'SURFACE_IS_NOT_TMZ', - 1: 'SURFACE_IS_TMZ', -} -SURFACE_IS_NOT_TMZ = 0 -SURFACE_IS_TMZ = 1 -SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'SURFACE_UPDATE_LOCK' -SURFACE_UPDATE_LOCK__enumvalues = { - 0: 'SURFACE_UPDATE_IS_UNLOCKED', - 1: 'SURFACE_UPDATE_IS_LOCKED', -} -SURFACE_UPDATE_IS_UNLOCKED = 0 -SURFACE_UPDATE_IS_LOCKED = 1 -SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_ALPHA' -CROSSBAR_FOR_ALPHA__enumvalues = { - 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', - 1: 'Y_G_DATA_ONTO_ALPHA_PORT', - 2: 'CB_B_DATA_ONTO_ALPHA_PORT', - 3: 'CR_R_DATA_ONTO_ALPHA_PORT', -} -ALPHA_DATA_ONTO_ALPHA_PORT = 0 -Y_G_DATA_ONTO_ALPHA_PORT = 1 -CB_B_DATA_ONTO_ALPHA_PORT = 2 -CR_R_DATA_ONTO_ALPHA_PORT = 3 -CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CB_B' -CROSSBAR_FOR_CB_B__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CB_B_PORT', - 1: 'Y_G_DATA_ONTO_CB_B_PORT', - 2: 'CB_B_DATA_ONTO_CB_B_PORT', - 3: 'CR_R_DATA_ONTO_CB_B_PORT', -} -ALPHA_DATA_ONTO_CB_B_PORT = 0 -Y_G_DATA_ONTO_CB_B_PORT = 1 -CB_B_DATA_ONTO_CB_B_PORT = 2 -CR_R_DATA_ONTO_CB_B_PORT = 3 -CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_CR_R' -CROSSBAR_FOR_CR_R__enumvalues = { - 0: 'ALPHA_DATA_ONTO_CR_R_PORT', - 1: 'Y_G_DATA_ONTO_CR_R_PORT', - 2: 'CB_B_DATA_ONTO_CR_R_PORT', - 3: 'CR_R_DATA_ONTO_CR_R_PORT', -} -ALPHA_DATA_ONTO_CR_R_PORT = 0 -Y_G_DATA_ONTO_CR_R_PORT = 1 -CB_B_DATA_ONTO_CR_R_PORT = 2 -CR_R_DATA_ONTO_CR_R_PORT = 3 -CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum - -# values for enumeration 'CROSSBAR_FOR_Y_G' -CROSSBAR_FOR_Y_G__enumvalues = { - 0: 'ALPHA_DATA_ONTO_Y_G_PORT', - 1: 'Y_G_DATA_ONTO_Y_G_PORT', - 2: 'CB_B_DATA_ONTO_Y_G_PORT', - 3: 'CR_R_DATA_ONTO_Y_G_PORT', -} -ALPHA_DATA_ONTO_Y_G_PORT = 0 -Y_G_DATA_ONTO_Y_G_PORT = 1 -CB_B_DATA_ONTO_Y_G_PORT = 2 -CR_R_DATA_ONTO_Y_G_PORT = 3 -CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum - -# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' -DETILE_BUFFER_PACKER_ENABLE__enumvalues = { - 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', - 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', -} -DETILE_BUFFER_PACKER_IS_DISABLE = 0 -DETILE_BUFFER_PACKER_IS_ENABLE = 1 -DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_MODE' -MEM_PWR_DIS_MODE__enumvalues = { - 0: 'MEM_POWER_DIS_MODE_ENABLE', - 1: 'MEM_POWER_DIS_MODE_DISABLE', -} -MEM_POWER_DIS_MODE_ENABLE = 0 -MEM_POWER_DIS_MODE_DISABLE = 1 -MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_MODE' -MEM_PWR_FORCE_MODE__enumvalues = { - 0: 'MEM_POWER_FORCE_MODE_OFF', - 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', - 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', -} -MEM_POWER_FORCE_MODE_OFF = 0 -MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 -MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 -MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 -MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_STATUS' -MEM_PWR_STATUS__enumvalues = { - 0: 'MEM_POWER_STATUS_ON', - 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', - 2: 'MEM_POWER_STATUS_DEEP_SLEEP', - 3: 'MEM_POWER_STATUS_SHUT_DOWN', -} -MEM_POWER_STATUS_ON = 0 -MEM_POWER_STATUS_LIGHT_SLEEP = 1 -MEM_POWER_STATUS_DEEP_SLEEP = 2 -MEM_POWER_STATUS_SHUT_DOWN = 3 -MEM_PWR_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_MASK_MODE' -PIPE_INT_MASK_MODE__enumvalues = { - 0: 'PIPE_INT_MASK_MODE_DISABLE', - 1: 'PIPE_INT_MASK_MODE_ENABLE', -} -PIPE_INT_MASK_MODE_DISABLE = 0 -PIPE_INT_MASK_MODE_ENABLE = 1 -PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_INT_TYPE_MODE' -PIPE_INT_TYPE_MODE__enumvalues = { - 0: 'PIPE_INT_TYPE_MODE_DISABLE', - 1: 'PIPE_INT_TYPE_MODE_ENABLE', -} -PIPE_INT_TYPE_MODE_DISABLE = 0 -PIPE_INT_TYPE_MODE_ENABLE = 1 -PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', -} -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' -CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_2X_MAGNIFY' -CURSOR_2X_MAGNIFY__enumvalues = { - 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', - 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', -} -CURSOR_2X_MAGNIFY_IS_DISABLE = 0 -CURSOR_2X_MAGNIFY_IS_ENABLE = 1 -CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_ENABLE' -CURSOR_ENABLE__enumvalues = { - 0: 'CURSOR_IS_DISABLE', - 1: 'CURSOR_IS_ENABLE', -} -CURSOR_IS_DISABLE = 0 -CURSOR_IS_ENABLE = 1 -CURSOR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_LINES_PER_CHUNK' -CURSOR_LINES_PER_CHUNK__enumvalues = { - 0: 'CURSOR_LINE_PER_CHUNK_1', - 1: 'CURSOR_LINE_PER_CHUNK_2', - 2: 'CURSOR_LINE_PER_CHUNK_4', - 3: 'CURSOR_LINE_PER_CHUNK_8', - 4: 'CURSOR_LINE_PER_CHUNK_16', -} -CURSOR_LINE_PER_CHUNK_1 = 0 -CURSOR_LINE_PER_CHUNK_2 = 1 -CURSOR_LINE_PER_CHUNK_4 = 2 -CURSOR_LINE_PER_CHUNK_8 = 3 -CURSOR_LINE_PER_CHUNK_16 = 4 -CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_MODE' -CURSOR_MODE__enumvalues = { - 0: 'CURSOR_MONO_2BIT', - 1: 'CURSOR_COLOR_24BIT_1BIT_AND', - 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', - 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', -} -CURSOR_MONO_2BIT = 0 -CURSOR_COLOR_24BIT_1BIT_AND = 1 -CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 -CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 -CURSOR_COLOR_64BIT_FP_PREMULT = 4 -CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 -CURSOR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' -CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', -} -CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 -CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 -CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' -CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { - 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', -} -CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 -CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 -CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_PITCH' -CURSOR_PITCH__enumvalues = { - 0: 'CURSOR_PITCH_64_PIXELS', - 1: 'CURSOR_PITCH_128_PIXELS', - 2: 'CURSOR_PITCH_256_PIXELS', -} -CURSOR_PITCH_64_PIXELS = 0 -CURSOR_PITCH_128_PIXELS = 1 -CURSOR_PITCH_256_PIXELS = 2 -CURSOR_PITCH = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_REQ_MODE' -CURSOR_REQ_MODE__enumvalues = { - 0: 'CURSOR_REQUEST_NORMALLY', - 1: 'CURSOR_REQUEST_EARLY', -} -CURSOR_REQUEST_NORMALLY = 0 -CURSOR_REQUEST_EARLY = 1 -CURSOR_REQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SNOOP' -CURSOR_SNOOP__enumvalues = { - 0: 'CURSOR_IS_NOT_SNOOP', - 1: 'CURSOR_IS_SNOOP', -} -CURSOR_IS_NOT_SNOOP = 0 -CURSOR_IS_SNOOP = 1 -CURSOR_SNOOP = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_STEREO_EN' -CURSOR_STEREO_EN__enumvalues = { - 0: 'CURSOR_STEREO_IS_DISABLED', - 1: 'CURSOR_STEREO_IS_ENABLED', -} -CURSOR_STEREO_IS_DISABLED = 0 -CURSOR_STEREO_IS_ENABLED = 1 -CURSOR_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SURFACE_TMZ' -CURSOR_SURFACE_TMZ__enumvalues = { - 0: 'CURSOR_SURFACE_IS_NOT_TMZ', - 1: 'CURSOR_SURFACE_IS_TMZ', -} -CURSOR_SURFACE_IS_NOT_TMZ = 0 -CURSOR_SURFACE_IS_TMZ = 1 -CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_SYSTEM' -CURSOR_SYSTEM__enumvalues = { - 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', - 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', -} -CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 -CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 -CURSOR_SYSTEM = ctypes.c_uint32 # enum - -# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { - 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', -} -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 -CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_DONE' -DMDATA_DONE__enumvalues = { - 0: 'DMDATA_NOT_SENT_TO_DIG', - 1: 'DMDATA_SENT_TO_DIG', -} -DMDATA_NOT_SENT_TO_DIG = 0 -DMDATA_SENT_TO_DIG = 1 -DMDATA_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_MODE' -DMDATA_MODE__enumvalues = { - 0: 'DMDATA_SOFTWARE_UPDATE_MODE', - 1: 'DMDATA_HARDWARE_UPDATE_MODE', -} -DMDATA_SOFTWARE_UPDATE_MODE = 0 -DMDATA_HARDWARE_UPDATE_MODE = 1 -DMDATA_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_QOS_MODE' -DMDATA_QOS_MODE__enumvalues = { - 0: 'DMDATA_QOS_LEVEL_FROM_TTU', - 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', -} -DMDATA_QOS_LEVEL_FROM_TTU = 0 -DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 -DMDATA_QOS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_REPEAT' -DMDATA_REPEAT__enumvalues = { - 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', - 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', -} -DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 -DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 -DMDATA_REPEAT = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW' -DMDATA_UNDERFLOW__enumvalues = { - 0: 'DMDATA_NOT_UNDERFLOW', - 1: 'DMDATA_UNDERFLOWED', -} -DMDATA_NOT_UNDERFLOW = 0 -DMDATA_UNDERFLOWED = 1 -DMDATA_UNDERFLOW = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' -DMDATA_UNDERFLOW_CLEAR__enumvalues = { - 0: 'DMDATA_DONT_CLEAR', - 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', -} -DMDATA_DONT_CLEAR = 0 -DMDATA_CLEAR_UNDERFLOW_STATUS = 1 -DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'DMDATA_UPDATED' -DMDATA_UPDATED__enumvalues = { - 0: 'DMDATA_NOT_UPDATED', - 1: 'DMDATA_WAS_UPDATED', -} -DMDATA_NOT_UPDATED = 0 -DMDATA_WAS_UPDATED = 1 -DMDATA_UPDATED = ctypes.c_uint32 # enum - -# values for enumeration 'RESPONSE_STATUS' -RESPONSE_STATUS__enumvalues = { - 0: 'OKAY', - 1: 'EXOKAY', - 2: 'SLVERR', - 3: 'DECERR', - 4: 'EARLY', - 5: 'OKAY_NODATA', - 6: 'PROTVIOL', - 7: 'TRANSERR', - 8: 'CMPTO', - 12: 'CRS', -} -OKAY = 0 -EXOKAY = 1 -SLVERR = 2 -DECERR = 3 -EARLY = 4 -OKAY_NODATA = 5 -PROTVIOL = 6 -TRANSERR = 7 -CMPTO = 8 -CRS = 12 -RESPONSE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { - 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', -} -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 -DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 -DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' -DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', -} -DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 -DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 -DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' -DCHUBBUB_MEM_PWR_MODE__enumvalues = { - 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', - 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', -} -DCHUBBUB_MEM_POWER_MODE_OFF = 0 -DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 -DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 -DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 -DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' -MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' -MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' -MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { - 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', -} -MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 -MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 -MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' -MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { - 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', - 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', - 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', -} -MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 -MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 -MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 -MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 -MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' -MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { - 0: 'MPC_CRC_INTERLACE_MODE_TOP', - 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', - 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', -} -MPC_CRC_INTERLACE_MODE_TOP = 0 -MPC_CRC_INTERLACE_MODE_BOTTOM = 1 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 -MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_MODE' -MPC_CRC_CALC_MODE__enumvalues = { - 0: 'MPC_CRC_ONE_SHOT_MODE', - 1: 'MPC_CRC_CONTINUOUS_MODE', -} -MPC_CRC_ONE_SHOT_MODE = 0 -MPC_CRC_CONTINUOUS_MODE = 1 -MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' -MPC_CRC_CALC_STEREO_MODE__enumvalues = { - 0: 'MPC_CRC_STEREO_MODE_LEFT', - 1: 'MPC_CRC_STEREO_MODE_RIGHT', - 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', -} -MPC_CRC_STEREO_MODE_LEFT = 0 -MPC_CRC_STEREO_MODE_RIGHT = 1 -MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 -MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 -MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_CRC_SOURCE_SELECT' -MPC_CRC_SOURCE_SELECT__enumvalues = { - 0: 'MPC_CRC_SOURCE_SEL_DPP', - 1: 'MPC_CRC_SOURCE_SEL_OPP', - 2: 'MPC_CRC_SOURCE_SEL_DWB', - 3: 'MPC_CRC_SOURCE_SEL_OTHER', -} -MPC_CRC_SOURCE_SEL_DPP = 0 -MPC_CRC_SOURCE_SEL_OPP = 1 -MPC_CRC_SOURCE_SEL_DWB = 2 -MPC_CRC_SOURCE_SEL_OTHER = 3 -MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT' -MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', - 1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', - 2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', - 3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', -} -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2 -MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3 -MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT' -MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', - 1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', - 2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', - 3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES', -} -MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0 -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1 -MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2 -MPC_DEBUG_BUS2_DATA_SELECT_RES = 3 -MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT' -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', - 1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', - 2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', - 3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', - 4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', - 5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', - 6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', - 7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', -} -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7 -MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT' -MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = { - 0: 'MPC_DEBUG_BUS_MPCC_BYTE0', - 1: 'MPC_DEBUG_BUS_MPCC_BYTE1', - 2: 'MPC_DEBUG_BUS_MPCC_BYTE2', - 3: 'MPC_DEBUG_BUS_MPCC_BYTE3', -} -MPC_DEBUG_BUS_MPCC_BYTE0 = 0 -MPC_DEBUG_BUS_MPCC_BYTE1 = 1 -MPC_DEBUG_BUS_MPCC_BYTE2 = 2 -MPC_DEBUG_BUS_MPCC_BYTE3 = 3 -MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_COEF_FORMAT' -MPC_OCSC_COEF_FORMAT__enumvalues = { - 0: 'MPC_OCSC_COEF_FORMAT_S2_13', - 1: 'MPC_OCSC_COEF_FORMAT_S3_12', -} -MPC_OCSC_COEF_FORMAT_S2_13 = 0 -MPC_OCSC_COEF_FORMAT_S3_12 = 1 -MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', -} -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_CSC_MODE' -MPC_OUT_CSC_MODE__enumvalues = { - 0: 'MPC_OUT_CSC_MODE_0', - 1: 'MPC_OUT_CSC_MODE_1', - 2: 'MPC_OUT_CSC_MODE_2', - 3: 'MPC_OUT_CSC_MODE_RSV', -} -MPC_OUT_CSC_MODE_0 = 0 -MPC_OUT_CSC_MODE_1 = 1 -MPC_OUT_CSC_MODE_2 = 2 -MPC_OUT_CSC_MODE_RSV = 3 -MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { - 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', -} -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 -MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' -MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { - 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', -} -MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 -MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 -MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_BG_COLOR_BPC' -MPCC_BG_COLOR_BPC__enumvalues = { - 0: 'MPCC_BG_COLOR_BPC_8bit', - 1: 'MPCC_BG_COLOR_BPC_9bit', - 2: 'MPCC_BG_COLOR_BPC_10bit', - 3: 'MPCC_BG_COLOR_BPC_11bit', - 4: 'MPCC_BG_COLOR_BPC_12bit', -} -MPCC_BG_COLOR_BPC_8bit = 0 -MPCC_BG_COLOR_BPC_9bit = 1 -MPCC_BG_COLOR_BPC_10bit = 2 -MPCC_BG_COLOR_BPC_11bit = 3 -MPCC_BG_COLOR_BPC_12bit = 4 -MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', -} -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 -MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', -} -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 -MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', -} -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 -MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' -MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', -} -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 -MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_CONTROL_MPCC_MODE' -MPCC_CONTROL_MPCC_MODE__enumvalues = { - 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', -} -MPCC_CONTROL_MPCC_MODE_BYPASS = 0 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 -MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 -MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 -MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' -MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', -} -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 -MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', -} -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 -MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' -MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { - 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', -} -MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 -MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 -MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 -MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 -MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN' -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', -} -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' -MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'MPCC_GAMUT_REMAP_MODE_0', - 1: 'MPCC_GAMUT_REMAP_MODE_1', - 2: 'MPCC_GAMUT_REMAP_MODE_2', - 3: 'MPCC_GAMUT_REMAP_MODE_RSV', -} -MPCC_GAMUT_REMAP_MODE_0 = 0 -MPCC_GAMUT_REMAP_MODE_1 = 1 -MPCC_GAMUT_REMAP_MODE_2 = 2 -MPCC_GAMUT_REMAP_MODE_RSV = 3 -MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' -MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { - 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', -} -MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 -MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 -MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 -MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' -MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_OGAM_DIFFERENT_RGB', - 1: 'MPCC_OGAM_ALL_USE_R', -} -MPCC_OGAM_DIFFERENT_RGB = 0 -MPCC_OGAM_ALL_USE_R = 1 -MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' -MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_ENABLE_PWL', - 1: 'MPCC_OGAM_DISABLE_PWL', -} -MPCC_OGAM_ENABLE_PWL = 0 -MPCC_OGAM_DISABLE_PWL = 1 -MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', -} -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 -MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' -MPCC_OGAM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_OGAM_RAMA_ACCESS', - 1: 'MPCC_OGAM_RAMB_ACCESS', -} -MPCC_OGAM_RAMA_ACCESS = 0 -MPCC_OGAM_RAMB_ACCESS = 1 -MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' -MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_OGAM_BLUE_LUT', - 1: 'MPCC_OGAM_GREEN_LUT', - 2: 'MPCC_OGAM_RED_LUT', -} -MPCC_OGAM_BLUE_LUT = 0 -MPCC_OGAM_GREEN_LUT = 1 -MPCC_OGAM_RED_LUT = 2 -MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' -MPCC_OGAM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_OGAM_DISABLE_DEBUG', - 1: 'MPCC_OGAM_ENABLE_DEBUG', -} -MPCC_OGAM_DISABLE_DEBUG = 0 -MPCC_OGAM_ENABLE_DEBUG = 1 -MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' -MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_OGAM_RAMA', - 1: 'MPCC_OGAM_RAMB', -} -MPCC_OGAM_RAMA = 0 -MPCC_OGAM_RAMB = 1 -MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { - 0: 'MPCC_OGAM_MODE_0', - 1: 'MPCC_OGAM_MODE_RSV1', - 2: 'MPCC_OGAM_MODE_2', - 3: 'MPCC_OGAM_MODE_RSV', -} -MPCC_OGAM_MODE_0 = 0 -MPCC_OGAM_MODE_RSV1 = 1 -MPCC_OGAM_MODE_2 = 2 -MPCC_OGAM_MODE_RSV = 3 -MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_NUM_SEG' -MPCC_OGAM_NUM_SEG__enumvalues = { - 0: 'MPCC_OGAM_SEGMENTS_1', - 1: 'MPCC_OGAM_SEGMENTS_2', - 2: 'MPCC_OGAM_SEGMENTS_4', - 3: 'MPCC_OGAM_SEGMENTS_8', - 4: 'MPCC_OGAM_SEGMENTS_16', - 5: 'MPCC_OGAM_SEGMENTS_32', - 6: 'MPCC_OGAM_SEGMENTS_64', - 7: 'MPCC_OGAM_SEGMENTS_128', -} -MPCC_OGAM_SEGMENTS_1 = 0 -MPCC_OGAM_SEGMENTS_2 = 1 -MPCC_OGAM_SEGMENTS_4 = 2 -MPCC_OGAM_SEGMENTS_8 = 3 -MPCC_OGAM_SEGMENTS_16 = 4 -MPCC_OGAM_SEGMENTS_32 = 5 -MPCC_OGAM_SEGMENTS_64 = 6 -MPCC_OGAM_SEGMENTS_128 = 7 -MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { - 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', -} -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 -MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' -MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_36BIT', - 1: 'MPCC_MCM_3DLUT_30BIT', -} -MPCC_MCM_3DLUT_36BIT = 0 -MPCC_MCM_3DLUT_30BIT = 1 -MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' -MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_RAM0_ACCESS', - 1: 'MPCC_MCM_RAM1_ACCESS', - 2: 'MPCC_MCM_RAM2_ACCESS', - 3: 'MPCC_MCM_RAM3_ACCESS', -} -MPCC_MCM_RAM0_ACCESS = 0 -MPCC_MCM_RAM1_ACCESS = 1 -MPCC_MCM_RAM2_ACCESS = 2 -MPCC_MCM_RAM3_ACCESS = 3 -MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' -MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { - 0: 'MPCC_MCM_3DLUT_17CUBE', - 1: 'MPCC_MCM_3DLUT_9CUBE', -} -MPCC_MCM_3DLUT_17CUBE = 0 -MPCC_MCM_3DLUT_9CUBE = 1 -MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' -MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', - 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', - 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', -} -MPCC_MCM_GAMMA_LUT_BYPASS = 0 -MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 -MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 -MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 -MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', -} -MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 -MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 -MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' -MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { - 0: 'MPCC_MCM_GAMMA_LUT_RAMA', - 1: 'MPCC_MCM_GAMMA_LUT_RAMB', -} -MPCC_MCM_GAMMA_LUT_RAMA = 0 -MPCC_MCM_GAMMA_LUT_RAMB = 1 -MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' -MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { - 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', - 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', -} -MPCC_MCM_LUT_2_MODE_BYPASS = 0 -MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 -MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 -MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' -MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { - 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', - 1: 'MPCC_MCM_LUT_ALL_USE_R', -} -MPCC_MCM_LUT_DIFFERENT_RGB = 0 -MPCC_MCM_LUT_ALL_USE_R = 1 -MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' -MPCC_MCM_LUT_NUM_SEG__enumvalues = { - 0: 'MPCC_MCM_LUT_SEGMENTS_1', - 1: 'MPCC_MCM_LUT_SEGMENTS_2', - 2: 'MPCC_MCM_LUT_SEGMENTS_4', - 3: 'MPCC_MCM_LUT_SEGMENTS_8', - 4: 'MPCC_MCM_LUT_SEGMENTS_16', - 5: 'MPCC_MCM_LUT_SEGMENTS_32', - 6: 'MPCC_MCM_LUT_SEGMENTS_64', - 7: 'MPCC_MCM_LUT_SEGMENTS_128', -} -MPCC_MCM_LUT_SEGMENTS_1 = 0 -MPCC_MCM_LUT_SEGMENTS_2 = 1 -MPCC_MCM_LUT_SEGMENTS_4 = 2 -MPCC_MCM_LUT_SEGMENTS_8 = 3 -MPCC_MCM_LUT_SEGMENTS_16 = 4 -MPCC_MCM_LUT_SEGMENTS_32 = 5 -MPCC_MCM_LUT_SEGMENTS_64 = 6 -MPCC_MCM_LUT_SEGMENTS_128 = 7 -MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' -MPCC_MCM_LUT_RAM_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_RAMA_ACCESS', - 1: 'MPCC_MCM_LUT_RAMB_ACCESS', -} -MPCC_MCM_LUT_RAMA_ACCESS = 0 -MPCC_MCM_LUT_RAMB_ACCESS = 1 -MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' -MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { - 0: 'MPCC_MCM_LUT_BLUE_LUT', - 1: 'MPCC_MCM_LUT_GREEN_LUT', - 2: 'MPCC_MCM_LUT_RED_LUT', -} -MPCC_MCM_LUT_BLUE_LUT = 0 -MPCC_MCM_LUT_GREEN_LUT = 1 -MPCC_MCM_LUT_RED_LUT = 2 -MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_LUT_READ_DBG' -MPCC_MCM_LUT_READ_DBG__enumvalues = { - 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', - 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', -} -MPCC_MCM_LUT_DISABLE_DEBUG = 0 -MPCC_MCM_LUT_ENABLE_DEBUG = 1 -MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' -MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', - 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', - 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', -} -MPCC_MCM_MEM_PWR_FORCE_DIS = 0 -MPCC_MCM_MEM_PWR_FORCE_LS = 1 -MPCC_MCM_MEM_PWR_FORCE_DS = 2 -MPCC_MCM_MEM_PWR_FORCE_SD = 3 -MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' -MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'MPCC_MCM_MEM_PWR_STATE_ON', - 1: 'MPCC_MCM_MEM_PWR_STATE_LS', - 2: 'MPCC_MCM_MEM_PWR_STATE_DS', - 3: 'MPCC_MCM_MEM_PWR_STATE_SD', -} -MPCC_MCM_MEM_PWR_STATE_ON = 0 -MPCC_MCM_MEM_PWR_STATE_LS = 1 -MPCC_MCM_MEM_PWR_STATE_DS = 2 -MPCC_MCM_MEM_PWR_STATE_SD = 3 -MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_BIT_DEPTH' -ENUM_DPG_BIT_DEPTH__enumvalues = { - 0: 'ENUM_DPG_BIT_DEPTH_6BPC', - 1: 'ENUM_DPG_BIT_DEPTH_8BPC', - 2: 'ENUM_DPG_BIT_DEPTH_10BPC', - 3: 'ENUM_DPG_BIT_DEPTH_12BPC', -} -ENUM_DPG_BIT_DEPTH_6BPC = 0 -ENUM_DPG_BIT_DEPTH_8BPC = 1 -ENUM_DPG_BIT_DEPTH_10BPC = 2 -ENUM_DPG_BIT_DEPTH_12BPC = 3 -ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' -ENUM_DPG_DYNAMIC_RANGE__enumvalues = { - 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', - 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', -} -ENUM_DPG_DYNAMIC_RANGE_VESA = 0 -ENUM_DPG_DYNAMIC_RANGE_CEA = 1 -ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_EN' -ENUM_DPG_EN__enumvalues = { - 0: 'ENUM_DPG_DISABLE', - 1: 'ENUM_DPG_ENABLE', -} -ENUM_DPG_DISABLE = 0 -ENUM_DPG_ENABLE = 1 -ENUM_DPG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_FIELD_POLARITY' -ENUM_DPG_FIELD_POLARITY__enumvalues = { - 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', -} -ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 -ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 -ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DPG_MODE' -ENUM_DPG_MODE__enumvalues = { - 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 3: 'ENUM_DPG_MODE_VERTICAL_BAR', - 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', - 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', - 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', -} -ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 -ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 -ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 -ENUM_DPG_MODE_VERTICAL_BAR = 3 -ENUM_DPG_MODE_HORIZONTAL_BAR = 4 -ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 -ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 -ENUM_DPG_MODE_RGB_XR_BIAS = 7 -ENUM_DPG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_DIS_CTRL' -FMTMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', - 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', -} -FMTMEM_ENABLE_MEM_PWR_CTRL = 0 -FMTMEM_DISABLE_MEM_PWR_CTRL = 1 -FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' -FMTMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'FMTMEM_NO_FORCE_REQUEST', - 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', -} -FMTMEM_NO_FORCE_REQUEST = 0 -FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 -FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' -FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' -FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', -} -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 -FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' -FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', -} -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 -FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', -} -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 -FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { - 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', -} -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 -FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' -FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { - 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', -} -FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 -FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 -FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 -FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 -FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 -FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 -FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { - 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', -} -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 -FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' -FMT_CONTROL_PIXEL_ENCODING__enumvalues = { - 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', -} -FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 -FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 -FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 -FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 -FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' -FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', -} -FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 -FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 -FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 -FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 -FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' -FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { - 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', -} -FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 -FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 -FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' -FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { - 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', -} -FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 -FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 -FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 -FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 -FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_DYNAMIC_EXP_MODE' -FMT_DYNAMIC_EXP_MODE__enumvalues = { - 0: 'FMT_DYNAMIC_EXP_MODE_10to12', - 1: 'FMT_DYNAMIC_EXP_MODE_8to12', -} -FMT_DYNAMIC_EXP_MODE_10to12 = 0 -FMT_DYNAMIC_EXP_MODE_8to12 = 1 -FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' -FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', -} -FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 -FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 -FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_POWER_STATE_ENUM' -FMT_POWER_STATE_ENUM__enumvalues = { - 0: 'FMT_POWER_STATE_ENUM_ON', - 1: 'FMT_POWER_STATE_ENUM_LS', - 2: 'FMT_POWER_STATE_ENUM_DS', - 3: 'FMT_POWER_STATE_ENUM_SD', -} -FMT_POWER_STATE_ENUM_ON = 0 -FMT_POWER_STATE_ENUM_LS = 1 -FMT_POWER_STATE_ENUM_DS = 2 -FMT_POWER_STATE_ENUM_SD = 3 -FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' -FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { - 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', -} -FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 -FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 -FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', -} -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 -FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_SPATIAL_DITHER_MODE' -FMT_SPATIAL_DITHER_MODE__enumvalues = { - 0: 'FMT_SPATIAL_DITHER_MODE_0', - 1: 'FMT_SPATIAL_DITHER_MODE_1', - 2: 'FMT_SPATIAL_DITHER_MODE_2', - 3: 'FMT_SPATIAL_DITHER_MODE_3', -} -FMT_SPATIAL_DITHER_MODE_0 = 0 -FMT_SPATIAL_DITHER_MODE_1 = 1 -FMT_SPATIAL_DITHER_MODE_2 = 2 -FMT_SPATIAL_DITHER_MODE_3 = 3 -FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' -FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { - 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', -} -FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 -FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 -FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { - 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', -} -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 -FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum - -# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' -OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { - 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', -} -OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 -OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 -OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 -OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' -OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { - 0: 'OPP_PIPE_CLOCK_DISABLE', - 1: 'OPP_PIPE_CLOCK_ENABLE', -} -OPP_PIPE_CLOCK_DISABLE = 0 -OPP_PIPE_CLOCK_ENABLE = 1 -OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' -OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { - 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', -} -OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 -OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 -OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_CONT_EN' -OPP_PIPE_CRC_CONT_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', - 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', -} -OPP_PIPE_CRC_MODE_ONE_SHOT = 0 -OPP_PIPE_CRC_MODE_CONTINUOUS = 1 -OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_EN' -OPP_PIPE_CRC_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_DISABLE', - 1: 'OPP_PIPE_CRC_ENABLE', -} -OPP_PIPE_CRC_DISABLE = 0 -OPP_PIPE_CRC_ENABLE = 1 -OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' -OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', -} -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 -OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 -OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' -OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', - 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', -} -OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 -OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 -OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 -OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' -OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { - 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', -} -OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 -OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 -OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' -OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', -} -OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 -OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 -OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 -OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 -OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' -OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { - 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', -} -OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 -OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 -OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' -OPP_PIPE_CRC_STEREO_EN__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', -} -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 -OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 -OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' -OPP_PIPE_CRC_STEREO_MODE__enumvalues = { - 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', - 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', -} -OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 -OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 -OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 -OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL' -OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_ABM0', - 1: 'DEBUG_BUS_SELECT_ABM1', - 2: 'DEBUG_BUS_SELECT_ABM2', - 3: 'DEBUG_BUS_SELECT_ABM3', - 4: 'DEBUG_BUS_SELECT_ABM_RESERVED0', - 5: 'DEBUG_BUS_SELECT_ABM_RESERVED1', -} -DEBUG_BUS_SELECT_ABM0 = 0 -DEBUG_BUS_SELECT_ABM1 = 1 -DEBUG_BUS_SELECT_ABM2 = 2 -DEBUG_BUS_SELECT_ABM3 = 3 -DEBUG_BUS_SELECT_ABM_RESERVED0 = 4 -DEBUG_BUS_SELECT_ABM_RESERVED1 = 5 -OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL' -OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_DPG0', - 1: 'DEBUG_BUS_SELECT_DPG1', - 2: 'DEBUG_BUS_SELECT_DPG2', - 3: 'DEBUG_BUS_SELECT_DPG3', - 4: 'DEBUG_BUS_SELECT_DPG_RESERVED0', - 5: 'DEBUG_BUS_SELECT_DPG_RESERVED1', -} -DEBUG_BUS_SELECT_DPG0 = 0 -DEBUG_BUS_SELECT_DPG1 = 1 -DEBUG_BUS_SELECT_DPG2 = 2 -DEBUG_BUS_SELECT_DPG3 = 3 -DEBUG_BUS_SELECT_DPG_RESERVED0 = 4 -DEBUG_BUS_SELECT_DPG_RESERVED1 = 5 -OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL' -OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_FMT0', - 1: 'DEBUG_BUS_SELECT_FMT1', - 2: 'DEBUG_BUS_SELECT_FMT2', - 3: 'DEBUG_BUS_SELECT_FMT3', - 4: 'DEBUG_BUS_SELECT_FMT_RESERVED0', - 5: 'DEBUG_BUS_SELECT_FMT_RESERVED1', -} -DEBUG_BUS_SELECT_FMT0 = 0 -DEBUG_BUS_SELECT_FMT1 = 1 -DEBUG_BUS_SELECT_FMT2 = 2 -DEBUG_BUS_SELECT_FMT3 = 3 -DEBUG_BUS_SELECT_FMT_RESERVED0 = 4 -DEBUG_BUS_SELECT_FMT_RESERVED1 = 5 -OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL' -OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_OPPBUF0', - 1: 'DEBUG_BUS_SELECT_OPPBUF1', - 2: 'DEBUG_BUS_SELECT_OPPBUF2', - 3: 'DEBUG_BUS_SELECT_OPPBUF3', - 4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', - 5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', -} -DEBUG_BUS_SELECT_OPPBUF0 = 0 -DEBUG_BUS_SELECT_OPPBUF1 = 1 -DEBUG_BUS_SELECT_OPPBUF2 = 2 -DEBUG_BUS_SELECT_OPPBUF3 = 3 -DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4 -DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5 -OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL' -OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = { - 0: 'DEBUG_BUS_SELECT_OPP_PIPE0', - 1: 'DEBUG_BUS_SELECT_OPP_PIPE1', - 2: 'DEBUG_BUS_SELECT_OPP_PIPE2', - 3: 'DEBUG_BUS_SELECT_OPP_PIPE3', - 4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', - 5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', -} -DEBUG_BUS_SELECT_OPP_PIPE0 = 0 -DEBUG_BUS_SELECT_OPP_PIPE1 = 1 -DEBUG_BUS_SELECT_OPP_PIPE2 = 2 -DEBUG_BUS_SELECT_OPP_PIPE3 = 3 -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4 -DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5 -OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' -OPP_TEST_CLK_SEL_CONTROL__enumvalues = { - 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', - 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', - 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', - 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', - 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 6: 'OPP_TEST_CLK_SEL_RESERVED0', - 7: 'OPP_TEST_CLK_SEL_RESERVED1', - 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', - 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', - 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 12: 'OPP_TEST_CLK_SEL_RESERVED2', - 13: 'OPP_TEST_CLK_SEL_RESERVED3', -} -OPP_TEST_CLK_SEL_DISPCLK_P = 0 -OPP_TEST_CLK_SEL_DISPCLK_R = 1 -OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 -OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 -OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 -OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 -OPP_TEST_CLK_SEL_RESERVED0 = 6 -OPP_TEST_CLK_SEL_RESERVED1 = 7 -OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 -OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 -OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 -OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 -OPP_TEST_CLK_SEL_RESERVED2 = 12 -OPP_TEST_CLK_SEL_RESERVED3 = 13 -OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' -OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { - 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', - 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', -} -OPP_TOP_CLOCK_DISABLED_STATUS = 0 -OPP_TOP_CLOCK_ENABLED_STATUS = 1 -OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' -OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { - 0: 'OPP_TOP_CLOCK_GATING_ENABLED', - 1: 'OPP_TOP_CLOCK_GATING_DISABLED', -} -OPP_TOP_CLOCK_GATING_ENABLED = 0 -OPP_TOP_CLOCK_GATING_DISABLED = 1 -OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DSCRM_EN' -ENUM_DSCRM_EN__enumvalues = { - 0: 'ENUM_DSCRM_DISABLE', - 1: 'ENUM_DSCRM_ENABLE', -} -ENUM_DSCRM_DISABLE = 0 -ENUM_DSCRM_ENABLE = 1 -ENUM_DSCRM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', -} -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 -MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_LOCK_SEL' -MASTER_UPDATE_LOCK_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_SEL_0', - 1: 'MASTER_UPDATE_LOCK_SEL_1', - 2: 'MASTER_UPDATE_LOCK_SEL_2', - 3: 'MASTER_UPDATE_LOCK_SEL_3', - 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', -} -MASTER_UPDATE_LOCK_SEL_0 = 0 -MASTER_UPDATE_LOCK_SEL_1 = 1 -MASTER_UPDATE_LOCK_SEL_2 = 2 -MASTER_UPDATE_LOCK_SEL_3 = 3 -MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 -MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 -MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { - 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', -} -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 -MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { - 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', -} -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 -OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' -OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', -} -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 -OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', -} -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { - 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', -} -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 -OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' -OTG_CONTROL_OTG_MASTER_EN__enumvalues = { - 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', -} -OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 -OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 -OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' -OTG_CONTROL_OTG_OUT_MUX__enumvalues = { - 0: 'OTG_CONTROL_OTG_OUT_MUX_0', - 1: 'OTG_CONTROL_OTG_OUT_MUX_1', - 2: 'OTG_CONTROL_OTG_OUT_MUX_2', -} -OTG_CONTROL_OTG_OUT_MUX_0 = 0 -OTG_CONTROL_OTG_OUT_MUX_1 = 1 -OTG_CONTROL_OTG_OUT_MUX_2 = 2 -OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' -OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { - 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', -} -OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 -OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 -OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { - 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', -} -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 -OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' -OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' -OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' -OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', - 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', -} -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 -OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' -OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', -} -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 -OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', -} -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 -OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', -} -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 -OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { - 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', -} -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 -OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' -OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { - 0: 'OTG_DIG_UPDATE_VCOUNT_0', - 1: 'OTG_DIG_UPDATE_VCOUNT_1', -} -OTG_DIG_UPDATE_VCOUNT_0 = 0 -OTG_DIG_UPDATE_VCOUNT_1 = 1 -OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 -OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { - 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', -} -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 -OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { - 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', -} -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 -OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { - 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', -} -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 -OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { - 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', -} -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 -OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { - 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', -} -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 -OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { - 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', -} -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 -OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { - 0: 'DIG_UPDATE_EYE_SEL_BOTH', - 1: 'DIG_UPDATE_EYE_SEL_LEFT', - 2: 'DIG_UPDATE_EYE_SEL_RIGHT', -} -DIG_UPDATE_EYE_SEL_BOTH = 0 -DIG_UPDATE_EYE_SEL_LEFT = 1 -DIG_UPDATE_EYE_SEL_RIGHT = 2 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { - 0: 'DIG_UPDATE_FIELD_SEL_BOTH', - 1: 'DIG_UPDATE_FIELD_SEL_TOP', - 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', -} -DIG_UPDATE_FIELD_SEL_BOTH = 0 -DIG_UPDATE_FIELD_SEL_TOP = 1 -DIG_UPDATE_FIELD_SEL_BOTTOM = 2 -DIG_UPDATE_FIELD_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', -} -MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 -MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 -MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 -MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { - 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', -} -MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 -MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 -OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' -OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { - 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', - 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', -} -OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 -OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 -OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_GSL_MASTER_MODE' -OTG_GSL_MASTER_MODE__enumvalues = { - 0: 'OTG_GSL_MASTER_MODE_0', - 1: 'OTG_GSL_MASTER_MODE_1', - 2: 'OTG_GSL_MASTER_MODE_2', - 3: 'OTG_GSL_MASTER_MODE_3', -} -OTG_GSL_MASTER_MODE_0 = 0 -OTG_GSL_MASTER_MODE_1 = 1 -OTG_GSL_MASTER_MODE_2 = 2 -OTG_GSL_MASTER_MODE_3 = 3 -OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_HORZ_REPETITION_COUNT' -OTG_HORZ_REPETITION_COUNT__enumvalues = { - 0: 'OTG_HORZ_REPETITION_COUNT_0', - 1: 'OTG_HORZ_REPETITION_COUNT_1', - 2: 'OTG_HORZ_REPETITION_COUNT_2', - 3: 'OTG_HORZ_REPETITION_COUNT_3', - 4: 'OTG_HORZ_REPETITION_COUNT_4', - 5: 'OTG_HORZ_REPETITION_COUNT_5', - 6: 'OTG_HORZ_REPETITION_COUNT_6', - 7: 'OTG_HORZ_REPETITION_COUNT_7', - 8: 'OTG_HORZ_REPETITION_COUNT_8', - 9: 'OTG_HORZ_REPETITION_COUNT_9', - 10: 'OTG_HORZ_REPETITION_COUNT_10', - 11: 'OTG_HORZ_REPETITION_COUNT_11', - 12: 'OTG_HORZ_REPETITION_COUNT_12', - 13: 'OTG_HORZ_REPETITION_COUNT_13', - 14: 'OTG_HORZ_REPETITION_COUNT_14', - 15: 'OTG_HORZ_REPETITION_COUNT_15', -} -OTG_HORZ_REPETITION_COUNT_0 = 0 -OTG_HORZ_REPETITION_COUNT_1 = 1 -OTG_HORZ_REPETITION_COUNT_2 = 2 -OTG_HORZ_REPETITION_COUNT_3 = 3 -OTG_HORZ_REPETITION_COUNT_4 = 4 -OTG_HORZ_REPETITION_COUNT_5 = 5 -OTG_HORZ_REPETITION_COUNT_6 = 6 -OTG_HORZ_REPETITION_COUNT_7 = 7 -OTG_HORZ_REPETITION_COUNT_8 = 8 -OTG_HORZ_REPETITION_COUNT_9 = 9 -OTG_HORZ_REPETITION_COUNT_10 = 10 -OTG_HORZ_REPETITION_COUNT_11 = 11 -OTG_HORZ_REPETITION_COUNT_12 = 12 -OTG_HORZ_REPETITION_COUNT_13 = 13 -OTG_HORZ_REPETITION_COUNT_14 = 14 -OTG_HORZ_REPETITION_COUNT_15 = 15 -OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_SYNC_A_POL' -OTG_H_SYNC_A_POL__enumvalues = { - 0: 'OTG_H_SYNC_A_POL_HIGH', - 1: 'OTG_H_SYNC_A_POL_LOW', -} -OTG_H_SYNC_A_POL_HIGH = 0 -OTG_H_SYNC_A_POL_LOW = 1 -OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE' -OTG_H_TIMING_DIV_MODE__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', - 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', - 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', - 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', -} -OTG_H_TIMING_DIV_MODE_NO_DIV = 0 -OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 -OTG_H_TIMING_DIV_MODE_RESERVED = 2 -OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 -OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' -OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { - 0: 'OTG_H_TIMING_DIV_MODE_AUTO', - 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', -} -OTG_H_TIMING_DIV_MODE_AUTO = 0 -OTG_H_TIMING_DIV_MODE_NOAUTO = 1 -OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { - 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', -} -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 -OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { - 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', -} -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 -OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { - 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', -} -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 -OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' -OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', -} -OTG_MASTER_UPDATE_LOCK_DISABLE = 0 -OTG_MASTER_UPDATE_LOCK_ENABLE = 1 -OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' -OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', -} -OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 -OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 -OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { - 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', -} -OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 -OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 -OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { - 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', -} -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 -OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { - 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', -} -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 -OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { - 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', -} -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 -OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', -} -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 -OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' -OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', -} -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 -OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { - 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', -} -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 -OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', -} -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' -OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', -} -OTG_TRIGA_FREQUENCY_SELECT_0 = 0 -OTG_TRIGA_FREQUENCY_SELECT_1 = 1 -OTG_TRIGA_FREQUENCY_SELECT_2 = 2 -OTG_TRIGA_FREQUENCY_SELECT_3 = 3 -OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' -OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', -} -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', -} -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { - 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', -} -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 -OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' -OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { - 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', - 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', - 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', - 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', -} -OTG_TRIGB_FREQUENCY_SELECT_0 = 0 -OTG_TRIGB_FREQUENCY_SELECT_1 = 1 -OTG_TRIGB_FREQUENCY_SELECT_2 = 2 -OTG_TRIGB_FREQUENCY_SELECT_3 = 3 -OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' -OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { - 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', -} -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 -OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { - 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', -} -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 -OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', -} -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 -OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { - 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', -} -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 -OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', -} -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 -OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { - 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', -} -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 -OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { - 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', -} -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 -OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' -OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { - 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', -} -OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 -OTG_VUPDATE_BLOCK_DISABLE_ON = 1 -OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_A_POL' -OTG_V_SYNC_A_POL__enumvalues = { - 0: 'OTG_V_SYNC_A_POL_HIGH', - 1: 'OTG_V_SYNC_A_POL_LOW', -} -OTG_V_SYNC_A_POL_HIGH = 0 -OTG_V_SYNC_A_POL_LOW = 1 -OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_SYNC_MODE' -OTG_V_SYNC_MODE__enumvalues = { - 0: 'OTG_V_SYNC_MODE_HSYNC', - 1: 'OTG_V_SYNC_MODE_HBLANK', -} -OTG_V_SYNC_MODE_HSYNC = 0 -OTG_V_SYNC_MODE_HBLANK = 1 -OTG_V_SYNC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', -} -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 -OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', -} -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 -OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { - 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', -} -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 -OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { - 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', -} -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 -OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { - 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', -} -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 -OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_INT_TYPE' -DC_DMCUB_INT_TYPE__enumvalues = { - 0: 'INT_LEVEL', - 1: 'INT_PULSE', -} -INT_LEVEL = 0 -INT_PULSE = 1 -DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DC_DMCUB_TIMER_WINDOW' -DC_DMCUB_TIMER_WINDOW__enumvalues = { - 0: 'BITS_31_0', - 1: 'BITS_32_1', - 2: 'BITS_33_2', - 3: 'BITS_34_3', - 4: 'BITS_35_4', - 5: 'BITS_36_5', - 6: 'BITS_37_6', - 7: 'BITS_38_7', -} -BITS_31_0 = 0 -BITS_32_1 = 1 -BITS_33_2 = 2 -BITS_34_3 = 3 -BITS_35_4 = 4 -BITS_36_5 = 5 -BITS_37_6 = 6 -BITS_38_7 = 7 -DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'INVALID_REG_ACCESS_TYPE' -INVALID_REG_ACCESS_TYPE__enumvalues = { - 0: 'REG_UNALLOCATED_ADDR_WRITE', - 1: 'REG_UNALLOCATED_ADDR_READ', - 2: 'REG_VIRTUAL_WRITE', - 3: 'REG_VIRTUAL_READ', - 4: 'REG_SECURE_VIOLATE_WRITE', - 5: 'REG_SECURE_VIOLATE_READ', -} -REG_UNALLOCATED_ADDR_WRITE = 0 -REG_UNALLOCATED_ADDR_READ = 1 -REG_VIRTUAL_WRITE = 2 -REG_VIRTUAL_READ = 3 -REG_SECURE_VIOLATE_WRITE = 4 -REG_SECURE_VIOLATE_READ = 5 -INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' -DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 8: 'RESERVED_8', - 9: 'RESERVED_9', - 10: 'RESERVED_10', - 11: 'RESERVED_11', - 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 20: 'RESERVED_20', - 21: 'RESERVED_21', - 22: 'RESERVED_22', - 23: 'RESERVED_23', - 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 32: 'RESERVED_32', - 33: 'RESERVED_33', - 34: 'RESERVED_34', - 35: 'RESERVED_35', - 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 44: 'RESERVED_44', - 45: 'RESERVED_45', - 46: 'RESERVED_46', - 47: 'RESERVED_47', - 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 56: 'RESERVED_56', - 57: 'RESERVED_57', - 58: 'RESERVED_58', - 59: 'RESERVED_59', - 60: 'RESERVED_60', - 61: 'RESERVED_61', - 62: 'RESERVED_62', - 63: 'RESERVED_63', - 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 72: 'RESERVED_72', - 73: 'RESERVED_73', - 74: 'RESERVED_74', - 75: 'RESERVED_75', - 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 84: 'RESERVED_84', - 85: 'RESERVED_85', - 86: 'RESERVED_86', - 87: 'RESERVED_87', - 88: 'RESERVED_88', - 89: 'RESERVED_89', - 90: 'RESERVED_90', - 91: 'RESERVED_91', -} -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 -RESERVED_8 = 8 -RESERVED_9 = 9 -RESERVED_10 = 10 -RESERVED_11 = 11 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 -RESERVED_20 = 20 -RESERVED_21 = 21 -RESERVED_22 = 22 -RESERVED_23 = 23 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 -RESERVED_32 = 32 -RESERVED_33 = 33 -RESERVED_34 = 34 -RESERVED_35 = 35 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 -RESERVED_44 = 44 -RESERVED_45 = 45 -RESERVED_46 = 46 -RESERVED_47 = 47 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 -RESERVED_56 = 56 -RESERVED_57 = 57 -RESERVED_58 = 58 -RESERVED_59 = 59 -RESERVED_60 = 60 -RESERVED_61 = 61 -RESERVED_62 = 62 -RESERVED_63 = 63 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 -RESERVED_72 = 72 -RESERVED_73 = 73 -RESERVED_74 = 74 -RESERVED_75 = 75 -DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 -DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 -DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 -DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 -DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 -DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 -DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 -DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 -RESERVED_84 = 84 -RESERVED_85 = 85 -RESERVED_86 = 86 -RESERVED_87 = 87 -RESERVED_88 = 88 -RESERVED_89 = 89 -RESERVED_90 = 90 -RESERVED_91 = 91 -DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' -DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DMU_GPU_TIMER_START_0_END_27', - 1: 'DMU_GPU_TIMER_START_1_END_28', - 2: 'DMU_GPU_TIMER_START_2_END_29', - 3: 'DMU_GPU_TIMER_START_3_END_30', - 4: 'DMU_GPU_TIMER_START_4_END_31', - 5: 'DMU_GPU_TIMER_START_6_END_33', - 6: 'DMU_GPU_TIMER_START_8_END_35', - 7: 'DMU_GPU_TIMER_START_10_END_37', -} -DMU_GPU_TIMER_START_0_END_27 = 0 -DMU_GPU_TIMER_START_1_END_28 = 1 -DMU_GPU_TIMER_START_2_END_29 = 2 -DMU_GPU_TIMER_START_3_END_30 = 3 -DMU_GPU_TIMER_START_4_END_31 = 4 -DMU_GPU_TIMER_START_6_END_33 = 5 -DMU_GPU_TIMER_START_8_END_35 = 6 -DMU_GPU_TIMER_START_10_END_37 = 7 -DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_DEST' -IHC_INTERRUPT_DEST__enumvalues = { - 0: 'INTERRUPT_SENT_TO_IH', - 1: 'INTERRUPT_SENT_TO_DMCUB', -} -INTERRUPT_SENT_TO_IH = 0 -INTERRUPT_SENT_TO_DMCUB = 1 -IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum - -# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' -IHC_INTERRUPT_LINE_STATUS__enumvalues = { - 0: 'INTERRUPT_LINE_NOT_ASSERTED', - 1: 'INTERRUPT_LINE_ASSERTED', -} -INTERRUPT_LINE_NOT_ASSERTED = 0 -INTERRUPT_LINE_ASSERTED = 1 -IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' -DC_SMU_INTERRUPT_ENABLE__enumvalues = { - 0: 'DISABLE_THE_INTERRUPT', - 1: 'ENABLE_THE_INTERRUPT', -} -DISABLE_THE_INTERRUPT = 0 -ENABLE_THE_INTERRUPT = 1 -DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DMU_CLOCK_ON' -DMU_CLOCK_ON__enumvalues = { - 0: 'DMU_CLOCK_STATUS_ON', - 1: 'DMU_CLOCK_STATUS_OFF', -} -DMU_CLOCK_STATUS_ON = 0 -DMU_CLOCK_STATUS_OFF = 1 -DMU_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'SMU_INTR' -SMU_INTR__enumvalues = { - 0: 'SMU_MSG_INTR_NOOP', - 1: 'SET_SMU_MSG_INTR', -} -SMU_MSG_INTR_NOOP = 0 -SET_SMU_MSG_INTR = 1 -SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' -ALLOW_SR_ON_TRANS_REQ__enumvalues = { - 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', -} -ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 -ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 -ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'AMCLOCK_ENABLE' -AMCLOCK_ENABLE__enumvalues = { - 0: 'ENABLE_AMCLK0', - 1: 'ENABLE_AMCLK1', -} -ENABLE_AMCLK0 = 0 -ENABLE_AMCLK1 = 1 -AMCLOCK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'CLEAR_SMU_INTR' -CLEAR_SMU_INTR__enumvalues = { - 0: 'SMU_INTR_STATUS_NOOP', - 1: 'SMU_INTR_STATUS_CLEAR', -} -SMU_INTR_STATUS_NOOP = 0 -SMU_INTR_STATUS_CLEAR = 1 -CLEAR_SMU_INTR = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' -CLOCK_BRANCH_SOFT_RESET__enumvalues = { - 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', -} -CLOCK_BRANCH_SOFT_RESET_NOOP = 0 -CLOCK_BRANCH_SOFT_RESET_FORCE = 1 -CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' -DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', -} -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 -DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 -DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 -DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' -DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', -} -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 -DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 -DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_SEL' -DCCG_AUDIO_DTO_SEL__enumvalues = { - 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', - 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', -} -DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 -DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 -DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3 -DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' -DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { - 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', -} -DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 -DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 -DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_BLOCK_SEL' -DCCG_DBG_BLOCK_SEL__enumvalues = { - 0: 'DCCG_DBG_BLOCK_SEL_DCCG', - 1: 'DCCG_DBG_BLOCK_SEL_PMON', - 2: 'DCCG_DBG_BLOCK_SEL_PMON2', -} -DCCG_DBG_BLOCK_SEL_DCCG = 0 -DCCG_DBG_BLOCK_SEL_PMON = 1 -DCCG_DBG_BLOCK_SEL_PMON2 = 2 -DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DBG_EN' -DCCG_DBG_EN__enumvalues = { - 0: 'DCCG_DBG_EN_DISABLE', - 1: 'DCCG_DBG_EN_ENABLE', -} -DCCG_DBG_EN_DISABLE = 0 -DCCG_DBG_EN_ENABLE = 1 -DCCG_DBG_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_DEEP_COLOR_CNTL' -DCCG_DEEP_COLOR_CNTL__enumvalues = { - 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', - 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', - 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', -} -DCCG_DEEP_COLOR_DTO_DISABLE = 0 -DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 -DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 -DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 -DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' -DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', - 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', -} -DCCG_FIFO_ERRDET_OVR_DISABLE = 0 -DCCG_FIFO_ERRDET_OVR_ENABLE = 1 -DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_RESET' -DCCG_FIFO_ERRDET_RESET__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', - 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', -} -DCCG_FIFO_ERRDET_RESET_NOOP = 0 -DCCG_FIFO_ERRDET_RESET_FORCE = 1 -DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_FIFO_ERRDET_STATE' -DCCG_FIFO_ERRDET_STATE__enumvalues = { - 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', -} -DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 -DCCG_FIFO_ERRDET_STATE_DETECTION = 1 -DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_HSYNC' -DCCG_PERF_MODE_HSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_HSYNC_NOOP', - 1: 'DCCG_PERF_MODE_HSYNC_START', -} -DCCG_PERF_MODE_HSYNC_NOOP = 0 -DCCG_PERF_MODE_HSYNC_START = 1 -DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_MODE_VSYNC' -DCCG_PERF_MODE_VSYNC__enumvalues = { - 0: 'DCCG_PERF_MODE_VSYNC_NOOP', - 1: 'DCCG_PERF_MODE_VSYNC_START', -} -DCCG_PERF_MODE_VSYNC_NOOP = 0 -DCCG_PERF_MODE_VSYNC_START = 1 -DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_OTG_SELECT' -DCCG_PERF_OTG_SELECT__enumvalues = { - 0: 'DCCG_PERF_SEL_OTG0', - 1: 'DCCG_PERF_SEL_OTG1', - 2: 'DCCG_PERF_SEL_OTG2', - 3: 'DCCG_PERF_SEL_OTG3', - 4: 'DCCG_PERF_SEL_RESERVED', -} -DCCG_PERF_SEL_OTG0 = 0 -DCCG_PERF_SEL_OTG1 = 1 -DCCG_PERF_SEL_OTG2 = 2 -DCCG_PERF_SEL_OTG3 = 3 -DCCG_PERF_SEL_RESERVED = 4 -DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCCG_PERF_RUN' -DCCG_PERF_RUN__enumvalues = { - 0: 'DCCG_PERF_RUN_NOOP', - 1: 'DCCG_PERF_RUN_START', -} -DCCG_PERF_RUN_NOOP = 0 -DCCG_PERF_RUN_START = 1 -DCCG_PERF_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' -DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { - 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', -} -DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 -DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 -DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_FIFO_ERROR' -DIO_FIFO_ERROR__enumvalues = { - 0: 'DIO_FIFO_ERROR_00', - 1: 'DIO_FIFO_ERROR_01', - 2: 'DIO_FIFO_ERROR_10', - 3: 'DIO_FIFO_ERROR_11', -} -DIO_FIFO_ERROR_00 = 0 -DIO_FIFO_ERROR_01 = 1 -DIO_FIFO_ERROR_10 = 2 -DIO_FIFO_ERROR_11 = 3 -DIO_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING' -DISABLE_CLOCK_GATING__enumvalues = { - 0: 'CLOCK_GATING_ENABLED', - 1: 'CLOCK_GATING_DISABLED', -} -CLOCK_GATING_ENABLED = 0 -CLOCK_GATING_DISABLED = 1 -DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum - -# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' -DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { - 0: 'CLOCK_GATING_ENABLED_IN_DCO', - 1: 'CLOCK_GATING_DISABLED_IN_DCO', -} -CLOCK_GATING_ENABLED_IN_DCO = 0 -CLOCK_GATING_DISABLED_IN_DCO = 1 -DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' -DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { - 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', -} -DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 -DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 -DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' -DISPCLK_FREQ_RAMP_DONE__enumvalues = { - 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', - 1: 'DISPCLK_FREQ_RAMP_COMPLETED', -} -DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 -DISPCLK_FREQ_RAMP_COMPLETED = 1 -DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DPREFCLK_SRC_SEL' -DPREFCLK_SRC_SEL__enumvalues = { - 0: 'DPREFCLK_SRC_SEL_CK', - 1: 'DPREFCLK_SRC_SEL_P0PLL', - 2: 'DPREFCLK_SRC_SEL_P1PLL', - 3: 'DPREFCLK_SRC_SEL_P2PLL', -} -DPREFCLK_SRC_SEL_CK = 0 -DPREFCLK_SRC_SEL_P0PLL = 1 -DPREFCLK_SRC_SEL_P1PLL = 2 -DPREFCLK_SRC_SEL_P2PLL = 3 -DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DTO_DS_DISABLE' -DP_DTO_DS_DISABLE__enumvalues = { - 0: 'DP_DTO_DESPREAD_DISABLE', - 1: 'DP_DTO_DESPREAD_ENABLE', -} -DP_DTO_DESPREAD_DISABLE = 0 -DP_DTO_DESPREAD_ENABLE = 1 -DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_HW_CAL_ENABLE' -DS_HW_CAL_ENABLE__enumvalues = { - 0: 'DS_HW_CAL_DIS', - 1: 'DS_HW_CAL_EN', -} -DS_HW_CAL_DIS = 0 -DS_HW_CAL_EN = 1 -DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' -DS_JITTER_COUNT_SRC_SEL__enumvalues = { - 0: 'DS_JITTER_COUNT_SRC_SEL0', - 1: 'DS_JITTER_COUNT_SRC_SEL1', -} -DS_JITTER_COUNT_SRC_SEL0 = 0 -DS_JITTER_COUNT_SRC_SEL1 = 1 -DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DS_REF_SRC' -DS_REF_SRC__enumvalues = { - 0: 'DS_REF_IS_XTALIN', - 1: 'DS_REF_IS_EXT_GENLOCK', - 2: 'DS_REF_IS_PCIE', -} -DS_REF_IS_XTALIN = 0 -DS_REF_IS_EXT_GENLOCK = 1 -DS_REF_IS_PCIE = 2 -DS_REF_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_IN_PHASE' -DVOACLKC_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_IN_PHASE' -DVOACLKC_MVP_IN_PHASE__enumvalues = { - 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { - 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', -} -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 -DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLKD_IN_PHASE' -DVOACLKD_IN_PHASE__enumvalues = { - 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', -} -DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 -DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 -DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' -DVOACLK_COARSE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', -} -DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 -DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 -DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 -DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 -DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 -DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 -DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 -DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 -DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 -DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 -DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 -DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 -DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 -DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 -DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 -DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 -DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 -DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 -DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 -DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 -DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 -DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 -DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 -DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 -DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 -DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 -DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 -DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' -DVOACLK_FINE_SKEW_CNTL__enumvalues = { - 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', - 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', -} -DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 -DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 -DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 -DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 -DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 -DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 -DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 -DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 -DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'DVO_ENABLE_RST' -DVO_ENABLE_RST__enumvalues = { - 0: 'DVO_ENABLE_RST_DISABLE', - 1: 'DVO_ENABLE_RST_ENABLE', -} -DVO_ENABLE_RST_DISABLE = 0 -DVO_ENABLE_RST_ENABLE = 1 -DVO_ENABLE_RST = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE' -ENABLE__enumvalues = { - 0: 'DISABLE_THE_FEATURE', - 1: 'ENABLE_THE_FEATURE', -} -DISABLE_THE_FEATURE = 0 -ENABLE_THE_FEATURE = 1 -ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_CLOCK' -ENABLE_CLOCK__enumvalues = { - 0: 'ENABLE_THE_REFCLK', - 1: 'ENABLE_THE_FUNC_CLOCK', -} -ENABLE_THE_REFCLK = 0 -ENABLE_THE_FUNC_CLOCK = 1 -ENABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'FORCE_DISABLE_CLOCK' -FORCE_DISABLE_CLOCK__enumvalues = { - 0: 'NOT_FORCE_THE_CLOCK_DISABLED', - 1: 'FORCE_THE_CLOCK_DISABLED', -} -NOT_FORCE_THE_CLOCK_DISABLED = 0 -FORCE_THE_CLOCK_DISABLED = 1 -FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMICHARCLK_SRC_SEL' -HDMICHARCLK_SRC_SEL__enumvalues = { - 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', - 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', - 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', - 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', - 4: 'HDMICHARCLK_SRC_SEL_UNIPHYE', - 5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', -} -HDMICHARCLK_SRC_SEL_UNIPHYA = 0 -HDMICHARCLK_SRC_SEL_UNIPHYB = 1 -HDMICHARCLK_SRC_SEL_UNIPHYC = 2 -HDMICHARCLK_SRC_SEL_UNIPHYD = 3 -HDMICHARCLK_SRC_SEL_UNIPHYE = 4 -HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5 -HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS' -HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = { - 0: 'DTO_FORCE_NO_BYPASS', - 1: 'DTO_FORCE_BYPASS', -} -DTO_FORCE_NO_BYPASS = 0 -DTO_FORCE_BYPASS = 1 -HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'HDMISTREAMCLK_SRC_SEL' -HDMISTREAMCLK_SRC_SEL__enumvalues = { - 0: 'SEL_REFCLK0', - 1: 'SEL_DTBCLK0', - 2: 'SEL_DTBCLK1', -} -SEL_REFCLK0 = 0 -SEL_DTBCLK0 = 1 -SEL_DTBCLK1 = 2 -HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'JITTER_REMOVE_DISABLE' -JITTER_REMOVE_DISABLE__enumvalues = { - 0: 'ENABLE_JITTER_REMOVAL', - 1: 'DISABLE_JITTER_REMOVAL', -} -ENABLE_JITTER_REMOVAL = 0 -DISABLE_JITTER_REMOVAL = 1 -JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', -} -MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 -MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 -MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_ADD_PIXEL' -OTG_ADD_PIXEL__enumvalues = { - 0: 'OTG_ADD_PIXEL_NOOP', - 1: 'OTG_ADD_PIXEL_FORCE', -} -OTG_ADD_PIXEL_NOOP = 0 -OTG_ADD_PIXEL_FORCE = 1 -OTG_ADD_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'OTG_DROP_PIXEL' -OTG_DROP_PIXEL__enumvalues = { - 0: 'OTG_DROP_PIXEL_NOOP', - 1: 'OTG_DROP_PIXEL_FORCE', -} -OTG_DROP_PIXEL_NOOP = 0 -OTG_DROP_PIXEL_FORCE = 1 -OTG_DROP_PIXEL = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_EN' -PHYSYMCLK_FORCE_EN__enumvalues = { - 0: 'PHYSYMCLK_FORCE_EN_DISABLE', - 1: 'PHYSYMCLK_FORCE_EN_ENABLE', -} -PHYSYMCLK_FORCE_EN_DISABLE = 0 -PHYSYMCLK_FORCE_EN_ENABLE = 1 -PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' -PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { - 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', - 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', - 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', -} -PHYSYMCLK_FORCE_SRC_SYMCLK = 0 -PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 -PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 -PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' -PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', -} -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 -PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 -PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' -PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', - 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', -} -PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 -PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 -PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' -PIPE_PIXEL_RATE_SOURCE__enumvalues = { - 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', - 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', -} -PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 -PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 -PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 -PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'PLL_CFG_IF_SOFT_RESET' -PLL_CFG_IF_SOFT_RESET__enumvalues = { - 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', - 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', -} -PLL_CFG_IF_SOFT_RESET_NOOP = 0 -PLL_CFG_IF_SOFT_RESET_FORCE = 1 -PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_EN' -SYMCLK_FE_FORCE_EN__enumvalues = { - 0: 'SYMCLK_FE_FORCE_EN_DISABLE', - 1: 'SYMCLK_FE_FORCE_EN_ENABLE', -} -SYMCLK_FE_FORCE_EN_DISABLE = 0 -SYMCLK_FE_FORCE_EN_ENABLE = 1 -SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'SYMCLK_FE_FORCE_SRC' -SYMCLK_FE_FORCE_SRC__enumvalues = { - 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', - 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', - 4: 'SYMCLK_FE_FORCE_SRC_RESERVED', -} -SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 -SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 -SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 -SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 -SYMCLK_FE_FORCE_SRC_RESERVED = 4 -SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLK_DIV_SEL' -TEST_CLK_DIV_SEL__enumvalues = { - 0: 'NO_DIV', - 1: 'DIV_2', - 2: 'DIV_4', - 3: 'DIV_8', -} -NO_DIV = 0 -DIV_2 = 1 -DIV_4 = 2 -DIV_8 = 3 -TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_LATCH_MASK' -VSYNC_CNT_LATCH_MASK__enumvalues = { - 0: 'VSYNC_CNT_LATCH_MASK_0', - 1: 'VSYNC_CNT_LATCH_MASK_1', -} -VSYNC_CNT_LATCH_MASK_0 = 0 -VSYNC_CNT_LATCH_MASK_1 = 1 -VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'VSYNC_CNT_RESET_SEL' -VSYNC_CNT_RESET_SEL__enumvalues = { - 0: 'VSYNC_CNT_RESET_SEL_0', - 1: 'VSYNC_CNT_RESET_SEL_1', -} -VSYNC_CNT_RESET_SEL_0 = 0 -VSYNC_CNT_RESET_SEL_1 = 1 -VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' -XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { - 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', - 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', -} -XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 -XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 -XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'XTAL_REF_SEL' -XTAL_REF_SEL__enumvalues = { - 0: 'XTAL_REF_SEL_1X', - 1: 'XTAL_REF_SEL_2X', -} -XTAL_REF_SEL_1X = 0 -XTAL_REF_SEL_2X = 1 -XTAL_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_ACK' -HPD_INT_CONTROL_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_ACK_0', - 1: 'HPD_INT_CONTROL_ACK_1', -} -HPD_INT_CONTROL_ACK_0 = 0 -HPD_INT_CONTROL_ACK_1 = 1 -HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_POLARITY' -HPD_INT_CONTROL_POLARITY__enumvalues = { - 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', - 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', -} -HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 -HPD_INT_CONTROL_GEN_INT_ON_CON = 1 -HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' -HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { - 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', - 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', -} -HPD_INT_CONTROL_RX_INT_ACK_0 = 0 -HPD_INT_CONTROL_RX_INT_ACK_1 = 1 -HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_CUR_DISP' -DPHY_8B10B_CUR_DISP__enumvalues = { - 0: 'DPHY_8B10B_CUR_DISP_ZERO', - 1: 'DPHY_8B10B_CUR_DISP_ONE', -} -DPHY_8B10B_CUR_DISP_ZERO = 0 -DPHY_8B10B_CUR_DISP_ONE = 1 -DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_8B10B_RESET' -DPHY_8B10B_RESET__enumvalues = { - 0: 'DPHY_8B10B_NOT_RESET', - 1: 'DPHY_8B10B_RESETET', -} -DPHY_8B10B_NOT_RESET = 0 -DPHY_8B10B_RESETET = 1 -DPHY_8B10B_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' -DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', -} -DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 -DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' -DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { - 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', -} -DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 -DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 -DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE0' -DPHY_ATEST_SEL_LANE0__enumvalues = { - 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE0_REG_PATTERN', -} -DPHY_ATEST_LANE0_PRBS_PATTERN = 0 -DPHY_ATEST_LANE0_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE1' -DPHY_ATEST_SEL_LANE1__enumvalues = { - 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE1_REG_PATTERN', -} -DPHY_ATEST_LANE1_PRBS_PATTERN = 0 -DPHY_ATEST_LANE1_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE2' -DPHY_ATEST_SEL_LANE2__enumvalues = { - 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE2_REG_PATTERN', -} -DPHY_ATEST_LANE2_PRBS_PATTERN = 0 -DPHY_ATEST_LANE2_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_ATEST_SEL_LANE3' -DPHY_ATEST_SEL_LANE3__enumvalues = { - 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', - 1: 'DPHY_ATEST_LANE3_REG_PATTERN', -} -DPHY_ATEST_LANE3_PRBS_PATTERN = 0 -DPHY_ATEST_LANE3_REG_PATTERN = 1 -DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_BYPASS' -DPHY_BYPASS__enumvalues = { - 0: 'DPHY_8B10B_OUTPUT', - 1: 'DPHY_DBG_OUTPUT', -} -DPHY_8B10B_OUTPUT = 0 -DPHY_DBG_OUTPUT = 1 -DPHY_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_CONT_EN' -DPHY_CRC_CONT_EN__enumvalues = { - 0: 'DPHY_CRC_ONE_SHOT', - 1: 'DPHY_CRC_CONTINUOUS', -} -DPHY_CRC_ONE_SHOT = 0 -DPHY_CRC_CONTINUOUS = 1 -DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_EN' -DPHY_CRC_EN__enumvalues = { - 0: 'DPHY_CRC_DISABLED', - 1: 'DPHY_CRC_ENABLED', -} -DPHY_CRC_DISABLED = 0 -DPHY_CRC_ENABLED = 1 -DPHY_CRC_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_FIELD' -DPHY_CRC_FIELD__enumvalues = { - 0: 'DPHY_CRC_START_FROM_TOP_FIELD', - 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', -} -DPHY_CRC_START_FROM_TOP_FIELD = 0 -DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 -DPHY_CRC_FIELD = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' -DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { - 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', - 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', -} -DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 -DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 -DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_CRC_SEL' -DPHY_CRC_SEL__enumvalues = { - 0: 'DPHY_CRC_LANE0_SELECTED', - 1: 'DPHY_CRC_LANE1_SELECTED', - 2: 'DPHY_CRC_LANE2_SELECTED', - 3: 'DPHY_CRC_LANE3_SELECTED', -} -DPHY_CRC_LANE0_SELECTED = 0 -DPHY_CRC_LANE1_SELECTED = 1 -DPHY_CRC_LANE2_SELECTED = 2 -DPHY_CRC_LANE3_SELECTED = 3 -DPHY_CRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_ENABLE' -DPHY_FEC_ENABLE__enumvalues = { - 0: 'DPHY_FEC_DISABLED', - 1: 'DPHY_FEC_ENABLED', -} -DPHY_FEC_DISABLED = 0 -DPHY_FEC_ENABLED = 1 -DPHY_FEC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_FEC_READY' -DPHY_FEC_READY__enumvalues = { - 0: 'DPHY_FEC_READY_EN', - 1: 'DPHY_FEC_READY_DIS', -} -DPHY_FEC_READY_EN = 0 -DPHY_FEC_READY_DIS = 1 -DPHY_FEC_READY = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_LOAD_BS_COUNT_START' -DPHY_LOAD_BS_COUNT_START__enumvalues = { - 0: 'DPHY_LOAD_BS_COUNT_STARTED', - 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', -} -DPHY_LOAD_BS_COUNT_STARTED = 0 -DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 -DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_EN' -DPHY_PRBS_EN__enumvalues = { - 0: 'DPHY_PRBS_DISABLE', - 1: 'DPHY_PRBS_ENABLE', -} -DPHY_PRBS_DISABLE = 0 -DPHY_PRBS_ENABLE = 1 -DPHY_PRBS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_PRBS_SEL' -DPHY_PRBS_SEL__enumvalues = { - 0: 'DPHY_PRBS7_SELECTED', - 1: 'DPHY_PRBS23_SELECTED', - 2: 'DPHY_PRBS11_SELECTED', -} -DPHY_PRBS7_SELECTED = 0 -DPHY_PRBS23_SELECTED = 1 -DPHY_PRBS11_SELECTED = 2 -DPHY_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' -DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { - 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 1: 'DPHY_FAST_TRAINING_CAPABLE', -} -DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 -DPHY_FAST_TRAINING_CAPABLE = 1 -DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' -DPHY_SCRAMBLER_ADVANCE__enumvalues = { - 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', -} -DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 -DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 -DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_DIS' -DPHY_SCRAMBLER_DIS__enumvalues = { - 0: 'DPHY_SCR_ENABLED', - 1: 'DPHY_SCR_DISABLED', -} -DPHY_SCR_ENABLED = 0 -DPHY_SCR_DISABLED = 1 -DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_KCODE' -DPHY_SCRAMBLER_KCODE__enumvalues = { - 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', - 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', -} -DPHY_SCRAMBLER_KCODE_DISABLED = 0 -DPHY_SCRAMBLER_KCODE_ENABLED = 1 -DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SCRAMBLER_SEL' -DPHY_SCRAMBLER_SEL__enumvalues = { - 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', - 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', -} -DPHY_SCRAMBLER_SEL_LANE_DATA = 0 -DPHY_SCRAMBLER_SEL_DBG_DATA = 1 -DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SKEW_BYPASS' -DPHY_SKEW_BYPASS__enumvalues = { - 0: 'DPHY_WITH_SKEW', - 1: 'DPHY_NO_SKEW', -} -DPHY_WITH_SKEW = 0 -DPHY_NO_SKEW = 1 -DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { - 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', -} -DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 -DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_SW_FAST_TRAINING_START' -DPHY_SW_FAST_TRAINING_START__enumvalues = { - 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 1: 'DPHY_SW_FAST_TRAINING_STARTED', -} -DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 -DPHY_SW_FAST_TRAINING_STARTED = 1 -DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum - -# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' -DPHY_TRAINING_PATTERN_SEL__enumvalues = { - 0: 'DPHY_TRAINING_PATTERN_1', - 1: 'DPHY_TRAINING_PATTERN_2', - 2: 'DPHY_TRAINING_PATTERN_3', - 3: 'DPHY_TRAINING_PATTERN_4', -} -DPHY_TRAINING_PATTERN_1 = 0 -DPHY_TRAINING_PATTERN_2 = 1 -DPHY_TRAINING_PATTERN_3 = 2 -DPHY_TRAINING_PATTERN_4 = 3 -DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_COMPONENT_DEPTH' -DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_COMPONENT_DEPTH_6BPC', - 1: 'DP_COMPONENT_DEPTH_8BPC', - 2: 'DP_COMPONENT_DEPTH_10BPC', - 3: 'DP_COMPONENT_DEPTH_12BPC', - 4: 'DP_COMPONENT_DEPTH_16BPC', -} -DP_COMPONENT_DEPTH_6BPC = 0 -DP_COMPONENT_DEPTH_8BPC = 1 -DP_COMPONENT_DEPTH_10BPC = 2 -DP_COMPONENT_DEPTH_12BPC = 3 -DP_COMPONENT_DEPTH_16BPC = 4 -DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'DP_CP_ENCRYPTION_TYPE' -DP_CP_ENCRYPTION_TYPE__enumvalues = { - 0: 'DP_CP_ENCRYPTION_TYPE_0', - 1: 'DP_CP_ENCRYPTION_TYPE_1', -} -DP_CP_ENCRYPTION_TYPE_0 = 0 -DP_CP_ENCRYPTION_TYPE_1 = 1 -DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' -DP_DPHY_8B10B_EXT_DISP__enumvalues = { - 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', -} -DP_DPHY_8B10B_EXT_DISP_ZERO = 0 -DP_DPHY_8B10B_EXT_DISP_ONE = 1 -DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' -DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' -DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', -} -DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 -DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 -DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { - 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', -} -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 -DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' -DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { - 0: 'DP_DPHY_HBR2_PASS_THROUGH', - 1: 'DP_DPHY_HBR2_PATTERN_1', - 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', - 3: 'DP_DPHY_HBR2_PATTERN_3', - 6: 'DP_DPHY_HBR2_PATTERN_2_POS', -} -DP_DPHY_HBR2_PASS_THROUGH = 0 -DP_DPHY_HBR2_PATTERN_1 = 1 -DP_DPHY_HBR2_PATTERN_2_NEG = 2 -DP_DPHY_HBR2_PATTERN_3 = 3 -DP_DPHY_HBR2_PATTERN_2_POS = 6 -DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_DSC_MODE' -DP_DSC_MODE__enumvalues = { - 0: 'DP_DSC_DISABLE', - 1: 'DP_DSC_444_SIMPLE_422', - 2: 'DP_DSC_NATIVE_422_420', -} -DP_DSC_DISABLE = 0 -DP_DSC_444_SIMPLE_422 = 1 -DP_DSC_NATIVE_422_420 = 2 -DP_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_EMBEDDED_PANEL_MODE' -DP_EMBEDDED_PANEL_MODE__enumvalues = { - 0: 'DP_EXTERNAL_PANEL', - 1: 'DP_EMBEDDED_PANEL', -} -DP_EXTERNAL_PANEL = 0 -DP_EMBEDDED_PANEL = 1 -DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_COMPLETE' -DP_LINK_TRAINING_COMPLETE__enumvalues = { - 0: 'DP_LINK_TRAINING_NOT_COMPLETE', - 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', -} -DP_LINK_TRAINING_NOT_COMPLETE = 0 -DP_LINK_TRAINING_ALREADY_COMPLETE = 1 -DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' -DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { - 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', -} -DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 -DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 -DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_ML_PHY_SEQ_MODE' -DP_ML_PHY_SEQ_MODE__enumvalues = { - 0: 'DP_ML_PHY_SEQ_LINE_NUM', - 1: 'DP_ML_PHY_SEQ_IMMEDIATE', -} -DP_ML_PHY_SEQ_LINE_NUM = 0 -DP_ML_PHY_SEQ_IMMEDIATE = 1 -DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' -DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { - 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', - 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', -} -MSA_V_TIMING_OVERRIDE_DISABLED = 0 -MSA_V_TIMING_OVERRIDE_ENABLED = 1 -DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_BLANK_CODE' -DP_MSE_BLANK_CODE__enumvalues = { - 0: 'DP_MSE_BLANK_CODE_SF_FILLED', - 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', -} -DP_MSE_BLANK_CODE_SF_FILLED = 0 -DP_MSE_BLANK_CODE_ZERO_FILLED = 1 -DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_LINK_LINE' -DP_MSE_LINK_LINE__enumvalues = { - 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', - 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', - 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', - 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', -} -DP_MSE_LINK_LINE_32_MTP_LONG = 0 -DP_MSE_LINK_LINE_64_MTP_LONG = 1 -DP_MSE_LINK_LINE_128_MTP_LONG = 2 -DP_MSE_LINK_LINE_256_MTP_LONG = 3 -DP_MSE_LINK_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT0' -DP_MSE_SAT_ENCRYPT0__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT0_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT0_ENABLED', -} -DP_MSE_SAT_ENCRYPT0_DISABLED = 0 -DP_MSE_SAT_ENCRYPT0_ENABLED = 1 -DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT1' -DP_MSE_SAT_ENCRYPT1__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT1_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT1_ENABLED', -} -DP_MSE_SAT_ENCRYPT1_DISABLED = 0 -DP_MSE_SAT_ENCRYPT1_ENABLED = 1 -DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT2' -DP_MSE_SAT_ENCRYPT2__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT2_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT2_ENABLED', -} -DP_MSE_SAT_ENCRYPT2_DISABLED = 0 -DP_MSE_SAT_ENCRYPT2_ENABLED = 1 -DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT3' -DP_MSE_SAT_ENCRYPT3__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT3_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT3_ENABLED', -} -DP_MSE_SAT_ENCRYPT3_DISABLED = 0 -DP_MSE_SAT_ENCRYPT3_ENABLED = 1 -DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT4' -DP_MSE_SAT_ENCRYPT4__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT4_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT4_ENABLED', -} -DP_MSE_SAT_ENCRYPT4_DISABLED = 0 -DP_MSE_SAT_ENCRYPT4_ENABLED = 1 -DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_ENCRYPT5' -DP_MSE_SAT_ENCRYPT5__enumvalues = { - 0: 'DP_MSE_SAT_ENCRYPT5_DISABLED', - 1: 'DP_MSE_SAT_ENCRYPT5_ENABLED', -} -DP_MSE_SAT_ENCRYPT5_DISABLED = 0 -DP_MSE_SAT_ENCRYPT5_ENABLED = 1 -DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' -DP_MSE_SAT_UPDATE_ACT__enumvalues = { - 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', - 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', -} -DP_MSE_SAT_UPDATE_NO_ACTION = 0 -DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 -DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 -DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_TIMESTAMP_MODE' -DP_MSE_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', -} -DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 -DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 -DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSE_ZERO_ENCODER' -DP_MSE_ZERO_ENCODER__enumvalues = { - 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', - 1: 'DP_MSE_ZERO_FE_ENCODER', -} -DP_MSE_NOT_ZERO_FE_ENCODER = 0 -DP_MSE_ZERO_FE_ENCODER = 1 -DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' -DP_MSO_NUM_OF_SST_LINKS__enumvalues = { - 0: 'DP_MSO_ONE_SSTLINK', - 1: 'DP_MSO_TWO_SSTLINK', - 2: 'DP_MSO_FOUR_SSTLINK', -} -DP_MSO_ONE_SSTLINK = 0 -DP_MSO_TWO_SSTLINK = 1 -DP_MSO_FOUR_SSTLINK = 2 -DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_ENCODING' -DP_PIXEL_ENCODING__enumvalues = { - 0: 'DP_PIXEL_ENCODING_RGB444', - 1: 'DP_PIXEL_ENCODING_YCBCR422', - 2: 'DP_PIXEL_ENCODING_YCBCR444', - 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 4: 'DP_PIXEL_ENCODING_Y_ONLY', - 5: 'DP_PIXEL_ENCODING_YCBCR420', -} -DP_PIXEL_ENCODING_RGB444 = 0 -DP_PIXEL_ENCODING_YCBCR422 = 1 -DP_PIXEL_ENCODING_YCBCR444 = 2 -DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 -DP_PIXEL_ENCODING_Y_ONLY = 4 -DP_PIXEL_ENCODING_YCBCR420 = 5 -DP_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM' -DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = { - 0: 'DP_ONE_PIXEL_PER_CYCLE', - 1: 'DP_TWO_PIXEL_PER_CYCLE', -} -DP_ONE_PIXEL_PER_CYCLE = 0 -DP_TWO_PIXEL_PER_CYCLE = 1 -DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_ASP_PRIORITY' -DP_SEC_ASP_PRIORITY__enumvalues = { - 0: 'DP_SEC_ASP_LOW_PRIORITY', - 1: 'DP_SEC_ASP_HIGH_PRIORITY', -} -DP_SEC_ASP_LOW_PRIORITY = 0 -DP_SEC_ASP_HIGH_PRIORITY = 1 -DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_AUDIO_MUTE' -DP_SEC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', - 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', -} -DP_SEC_AUDIO_MUTE_HW_CTRL = 0 -DP_SEC_AUDIO_MUTE_SW_CTRL = 1 -DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_COLLISION_ACK' -DP_SEC_COLLISION_ACK__enumvalues = { - 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', - 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', -} -DP_SEC_COLLISION_ACK_NO_EFFECT = 0 -DP_SEC_COLLISION_ACK_CLR_FLAG = 1 -DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP0_PRIORITY' -DP_SEC_GSP0_PRIORITY__enumvalues = { - 0: 'SEC_GSP0_PRIORITY_LOW', - 1: 'SEC_GSP0_PRIORITY_HIGH', -} -SEC_GSP0_PRIORITY_LOW = 0 -SEC_GSP0_PRIORITY_HIGH = 1 -DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND' -DP_SEC_GSP_SEND__enumvalues = { - 0: 'NOT_SENT', - 1: 'FORCE_SENT', -} -NOT_SENT = 0 -FORCE_SENT = 1 -DP_SEC_GSP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' -DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { - 0: 'SEND_AT_LINK_NUMBER', - 1: 'SEND_AT_EARLIEST_TIME', -} -SEND_AT_LINK_NUMBER = 0 -SEND_AT_EARLIEST_TIME = 1 -DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_GSP_SEND_PPS' -DP_SEC_GSP_SEND_PPS__enumvalues = { - 0: 'SEND_NORMAL_PACKET', - 1: 'SEND_PPS_PACKET', -} -SEND_NORMAL_PACKET = 0 -SEND_PPS_PACKET = 1 -DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_LINE_REFERENCE' -DP_SEC_LINE_REFERENCE__enumvalues = { - 0: 'REFER_TO_DP_SOF', - 1: 'REFER_TO_OTG_SOF', -} -REFER_TO_DP_SOF = 0 -REFER_TO_OTG_SOF = 1 -DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SEC_TIMESTAMP_MODE' -DP_SEC_TIMESTAMP_MODE__enumvalues = { - 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', - 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', -} -DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 -DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 -DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_ACK' -DP_STEER_OVERFLOW_ACK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 -DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STEER_OVERFLOW_MASK' -DP_STEER_OVERFLOW_MASK__enumvalues = { - 0: 'DP_STEER_OVERFLOW_MASKED', - 1: 'DP_STEER_OVERFLOW_UNMASK', -} -DP_STEER_OVERFLOW_MASKED = 0 -DP_STEER_OVERFLOW_UNMASK = 1 -DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_SYNC_POLARITY' -DP_SYNC_POLARITY__enumvalues = { - 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', - 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', -} -DP_SYNC_POLARITY_ACTIVE_HIGH = 0 -DP_SYNC_POLARITY_ACTIVE_LOW = 1 -DP_SYNC_POLARITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_TU_OVERFLOW_ACK' -DP_TU_OVERFLOW_ACK__enumvalues = { - 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', - 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', -} -DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 -DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 -DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_UDI_LANES' -DP_UDI_LANES__enumvalues = { - 0: 'DP_UDI_1_LANE', - 1: 'DP_UDI_2_LANES', - 2: 'DP_UDI_LANES_RESERVED', - 3: 'DP_UDI_4_LANES', -} -DP_UDI_1_LANE = 0 -DP_UDI_2_LANES = 1 -DP_UDI_LANES_RESERVED = 2 -DP_UDI_4_LANES = 3 -DP_UDI_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' -DP_VID_ENHANCED_FRAME_MODE__enumvalues = { - 0: 'VID_NORMAL_FRAME_MODE', - 1: 'VID_ENHANCED_MODE', -} -VID_NORMAL_FRAME_MODE = 0 -VID_ENHANCED_MODE = 1 -DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' -DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { - 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', -} -DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 -DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 -DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_M_N_GEN_EN' -DP_VID_M_N_GEN_EN__enumvalues = { - 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', - 1: 'DP_VID_M_N_CALC_AUTO', -} -DP_VID_M_N_PROGRAMMED_VIA_REG = 0 -DP_VID_M_N_CALC_AUTO = 1 -DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_N_MUL' -DP_VID_N_MUL__enumvalues = { - 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', - 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', -} -DP_VID_M_1X_INPUT_PIXEL_RATE = 0 -DP_VID_M_2X_INPUT_PIXEL_RATE = 1 -DP_VID_M_4X_INPUT_PIXEL_RATE = 2 -DP_VID_M_8X_INPUT_PIXEL_RATE = 3 -DP_VID_N_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' -DP_VID_STREAM_DISABLE_ACK__enumvalues = { - 0: 'ID_STREAM_DISABLE_NO_ACK', - 1: 'ID_STREAM_DISABLE_ACKED', -} -ID_STREAM_DISABLE_NO_ACK = 0 -ID_STREAM_DISABLE_ACKED = 1 -DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' -DP_VID_STREAM_DISABLE_MASK__enumvalues = { - 0: 'VID_STREAM_DISABLE_MASKED', - 1: 'VID_STREAM_DISABLE_UNMASK', -} -VID_STREAM_DISABLE_MASKED = 0 -VID_STREAM_DISABLE_UNMASK = 1 -DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_STREAM_DIS_DEFER' -DP_VID_STREAM_DIS_DEFER__enumvalues = { - 0: 'DP_VID_STREAM_DIS_NO_DEFER', - 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', -} -DP_VID_STREAM_DIS_NO_DEFER = 0 -DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 -DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 -DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'DP_VID_VBID_FIELD_POL' -DP_VID_VBID_FIELD_POL__enumvalues = { - 0: 'DP_VID_VBID_FIELD_POL_NORMAL', - 1: 'DP_VID_VBID_FIELD_POL_INV', -} -DP_VID_VBID_FIELD_POL_NORMAL = 0 -DP_VID_VBID_FIELD_POL_INV = 1 -DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum - -# values for enumeration 'FEC_ACTIVE_STATUS' -FEC_ACTIVE_STATUS__enumvalues = { - 0: 'DPHY_FEC_NOT_ACTIVE', - 1: 'DPHY_FEC_ACTIVE', -} -DPHY_FEC_NOT_ACTIVE = 0 -DPHY_FEC_ACTIVE = 1 -FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' -DIG_BE_CNTL_HPD_SELECT__enumvalues = { - 0: 'DIG_BE_CNTL_HPD1', - 1: 'DIG_BE_CNTL_HPD2', - 2: 'DIG_BE_CNTL_HPD3', - 3: 'DIG_BE_CNTL_HPD4', - 4: 'DIG_BE_CNTL_HPD5', - 5: 'DIG_BE_CNTL_NO_HPD', -} -DIG_BE_CNTL_HPD1 = 0 -DIG_BE_CNTL_HPD2 = 1 -DIG_BE_CNTL_HPD3 = 2 -DIG_BE_CNTL_HPD4 = 3 -DIG_BE_CNTL_HPD5 = 4 -DIG_BE_CNTL_NO_HPD = 5 -DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_BE_CNTL_MODE' -DIG_BE_CNTL_MODE__enumvalues = { - 0: 'DIG_BE_DP_SST_MODE', - 1: 'DIG_BE_RESERVED1', - 2: 'DIG_BE_TMDS_DVI_MODE', - 3: 'DIG_BE_TMDS_HDMI_MODE', - 4: 'DIG_BE_RESERVED4', - 5: 'DIG_BE_DP_MST_MODE', - 6: 'DIG_BE_RESERVED2', - 7: 'DIG_BE_RESERVED3', -} -DIG_BE_DP_SST_MODE = 0 -DIG_BE_RESERVED1 = 1 -DIG_BE_TMDS_DVI_MODE = 2 -DIG_BE_TMDS_HDMI_MODE = 3 -DIG_BE_RESERVED4 = 4 -DIG_BE_DP_MST_MODE = 5 -DIG_BE_RESERVED2 = 6 -DIG_BE_RESERVED3 = 7 -DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' -DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_OFF', - 1: 'DIG_DIGITAL_BYPASS_ON', -} -DIG_DIGITAL_BYPASS_OFF = 0 -DIG_DIGITAL_BYPASS_ON = 1 -DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' -DIG_DIGITAL_BYPASS_SEL__enumvalues = { - 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', -} -DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 -DIG_DIGITAL_BYPASS_SEL_36BPP = 1 -DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 -DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 -DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 -DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 -DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 -DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' -DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { - 0: 'DIG_FE_SOURCE_FROM_OTG0', - 1: 'DIG_FE_SOURCE_FROM_OTG1', - 2: 'DIG_FE_SOURCE_FROM_OTG2', - 3: 'DIG_FE_SOURCE_FROM_OTG3', - 4: 'DIG_FE_SOURCE_RESERVED', -} -DIG_FE_SOURCE_FROM_OTG0 = 0 -DIG_FE_SOURCE_FROM_OTG1 = 1 -DIG_FE_SOURCE_FROM_OTG2 = 2 -DIG_FE_SOURCE_FROM_OTG3 = 3 -DIG_FE_SOURCE_RESERVED = 4 -DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' -DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { - 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', - 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', - 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', - 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', - 4: 'DIG_FE_STEREOSYNC_RESERVED', -} -DIG_FE_STEREOSYNC_FROM_OTG0 = 0 -DIG_FE_STEREOSYNC_FROM_OTG1 = 1 -DIG_FE_STEREOSYNC_FROM_OTG2 = 2 -DIG_FE_STEREOSYNC_FROM_OTG3 = 3 -DIG_FE_STEREOSYNC_RESERVED = 4 -DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', - 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', -} -DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 -DIG_FIFO_FORCE_RECOMP_MINMAX = 1 -DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { - 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', - 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', -} -DIG_FIFO_USE_OVERWRITE_LEVEL = 0 -DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 -DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' -DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { - 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', -} -DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 -DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 -DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE' -DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = { - 0: 'DIG_FIFO_1_PIX_PER_CYCLE', - 1: 'DIG_FIFO_2_PIX_PER_CYCLE', -} -DIG_FIFO_1_PIX_PER_CYCLE = 0 -DIG_FIFO_2_PIX_PER_CYCLE = 1 -DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DIG_FIFO_NO_ERROR_OCCURRED', - 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', - 2: 'DIG_FIFO_OVERFLOW_OCCURRED', -} -DIG_FIFO_NO_ERROR_OCCURRED = 0 -DIG_FIFO_UNDERFLOW_OCCURRED = 1 -DIG_FIFO_OVERFLOW_OCCURRED = 2 -DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' -DIG_FIFO_READ_CLOCK_SRC__enumvalues = { - 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', -} -DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 -DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 -DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_INPUT_PIXEL_SEL' -DIG_INPUT_PIXEL_SEL__enumvalues = { - 0: 'DIG_ALL_PIXEL', - 1: 'DIG_EVEN_PIXEL_ONLY', - 2: 'DIG_ODD_PIXEL_ONLY', -} -DIG_ALL_PIXEL = 0 -DIG_EVEN_PIXEL_ONLY = 1 -DIG_ODD_PIXEL_ONLY = 2 -DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' -DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_ON_LINK0', - 1: 'DIG_OUTPUT_CRC_ON_LINK1', -} -DIG_OUTPUT_CRC_ON_LINK0 = 0 -DIG_OUTPUT_CRC_ON_LINK1 = 1 -DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' -DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { - 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 2: 'DIG_OUTPUT_CRC_FOR_VBI', - 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', -} -DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 -DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 -DIG_OUTPUT_CRC_FOR_VBI = 2 -DIG_OUTPUT_CRC_FOR_AUDIO = 3 -DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' -DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', -} -DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 -DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 -DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_SL_PIXEL_GROUPING' -DIG_SL_PIXEL_GROUPING__enumvalues = { - 0: 'DIG_SINGLETON_PIXELS', - 1: 'DIG_PAIR_PIXELS', -} -DIG_SINGLETON_PIXELS = 0 -DIG_PAIR_PIXELS = 1 -DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' -DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', -} -DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 -DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 -DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { - 0: 'DIG_10BIT_TEST_PATTERN', - 1: 'DIG_ALTERNATING_TEST_PATTERN', -} -DIG_10BIT_TEST_PATTERN = 0 -DIG_ALTERNATING_TEST_PATTERN = 1 -DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_TEST_PATTERN_NORMAL', - 1: 'DIG_TEST_PATTERN_RANDOM', -} -DIG_TEST_PATTERN_NORMAL = 0 -DIG_TEST_PATTERN_RANDOM = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { - 0: 'DIG_RANDOM_PATTERN_ENABLED', - 1: 'DIG_RANDOM_PATTERN_RESETED', -} -DIG_RANDOM_PATTERN_ENABLED = 0 -DIG_RANDOM_PATTERN_RESETED = 1 -DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { - 0: 'DIG_IN_NORMAL_OPERATION', - 1: 'DIG_IN_DEBUG_MODE', -} -DIG_IN_NORMAL_OPERATION = 0 -DIG_IN_DEBUG_MODE = 1 -DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOLBY_VISION_ENABLE' -DOLBY_VISION_ENABLE__enumvalues = { - 0: 'DOLBY_VISION_DISABLED', - 1: 'DOLBY_VISION_ENABLED', -} -DOLBY_VISION_DISABLED = 0 -DOLBY_VISION_ENABLED = 1 -DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACP_SEND' -HDMI_ACP_SEND__enumvalues = { - 0: 'HDMI_ACP_NOT_SEND', - 1: 'HDMI_ACP_PKT_SEND', -} -HDMI_ACP_NOT_SEND = 0 -HDMI_ACP_PKT_SEND = 1 -HDMI_ACP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' -HDMI_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_CONT' -HDMI_ACR_CONT__enumvalues = { - 0: 'HDMI_ACR_CONT_DISABLE', - 1: 'HDMI_ACR_CONT_ENABLE', -} -HDMI_ACR_CONT_DISABLE = 0 -HDMI_ACR_CONT_ENABLE = 1 -HDMI_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_N_MULTIPLE' -HDMI_ACR_N_MULTIPLE__enumvalues = { - 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', - 1: 'HDMI_ACR_1_MULTIPLE', - 2: 'HDMI_ACR_2_MULTIPLE', - 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', - 4: 'HDMI_ACR_4_MULTIPLE', - 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', - 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', - 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', -} -HDMI_ACR_0_MULTIPLE_RESERVED = 0 -HDMI_ACR_1_MULTIPLE = 1 -HDMI_ACR_2_MULTIPLE = 2 -HDMI_ACR_3_MULTIPLE_RESERVED = 3 -HDMI_ACR_4_MULTIPLE = 4 -HDMI_ACR_5_MULTIPLE_RESERVED = 5 -HDMI_ACR_6_MULTIPLE_RESERVED = 6 -HDMI_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SELECT' -HDMI_ACR_SELECT__enumvalues = { - 0: 'HDMI_ACR_SELECT_HW', - 1: 'HDMI_ACR_SELECT_32K', - 2: 'HDMI_ACR_SELECT_44K', - 3: 'HDMI_ACR_SELECT_48K', -} -HDMI_ACR_SELECT_HW = 0 -HDMI_ACR_SELECT_32K = 1 -HDMI_ACR_SELECT_44K = 2 -HDMI_ACR_SELECT_48K = 3 -HDMI_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SEND' -HDMI_ACR_SEND__enumvalues = { - 0: 'HDMI_ACR_NOT_SEND', - 1: 'HDMI_ACR_PKT_SEND', -} -HDMI_ACR_NOT_SEND = 0 -HDMI_ACR_PKT_SEND = 1 -HDMI_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ACR_SOURCE' -HDMI_ACR_SOURCE__enumvalues = { - 0: 'HDMI_ACR_SOURCE_HW', - 1: 'HDMI_ACR_SOURCE_SW', -} -HDMI_ACR_SOURCE_HW = 0 -HDMI_ACR_SOURCE_SW = 1 -HDMI_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_DELAY_EN' -HDMI_AUDIO_DELAY_EN__enumvalues = { - 0: 'HDMI_AUDIO_DELAY_DISABLE', - 1: 'HDMI_AUDIO_DELAY_58CLK', - 2: 'HDMI_AUDIO_DELAY_56CLK', - 3: 'HDMI_AUDIO_DELAY_RESERVED', -} -HDMI_AUDIO_DELAY_DISABLE = 0 -HDMI_AUDIO_DELAY_58CLK = 1 -HDMI_AUDIO_DELAY_56CLK = 2 -HDMI_AUDIO_DELAY_RESERVED = 3 -HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_CONT' -HDMI_AUDIO_INFO_CONT__enumvalues = { - 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', - 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', -} -HDMI_AUDIO_INFO_CONT_DISABLE = 0 -HDMI_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_AUDIO_INFO_SEND' -HDMI_AUDIO_INFO_SEND__enumvalues = { - 0: 'HDMI_AUDIO_INFO_NOT_SEND', - 1: 'HDMI_AUDIO_INFO_PKT_SEND', -} -HDMI_AUDIO_INFO_NOT_SEND = 0 -HDMI_AUDIO_INFO_PKT_SEND = 1 -HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' -HDMI_CLOCK_CHANNEL_RATE__enumvalues = { - 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', -} -HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 -HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 -HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' -HDMI_DATA_SCRAMBLE_EN__enumvalues = { - 0: 'HDMI_DATA_SCRAMBLE_DISABLE', - 1: 'HDMI_DATA_SCRAMBLE_ENABLE', -} -HDMI_DATA_SCRAMBLE_DISABLE = 0 -HDMI_DATA_SCRAMBLE_ENABLE = 1 -HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' -HDMI_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', - 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', -} -HDMI_DEEP_COLOR_DEPTH_24BPP = 0 -HDMI_DEEP_COLOR_DEPTH_30BPP = 1 -HDMI_DEEP_COLOR_DEPTH_36BPP = 2 -HDMI_DEEP_COLOR_DEPTH_48BPP = 3 -HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_DEFAULT_PAHSE' -HDMI_DEFAULT_PAHSE__enumvalues = { - 0: 'HDMI_DEFAULT_PHASE_IS_0', - 1: 'HDMI_DEFAULT_PHASE_IS_1', -} -HDMI_DEFAULT_PHASE_IS_0 = 0 -HDMI_DEFAULT_PHASE_IS_1 = 1 -HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_ACK' -HDMI_ERROR_ACK__enumvalues = { - 0: 'HDMI_ERROR_ACK_INT', - 1: 'HDMI_ERROR_NOT_ACK', -} -HDMI_ERROR_ACK_INT = 0 -HDMI_ERROR_NOT_ACK = 1 -HDMI_ERROR_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ERROR_MASK' -HDMI_ERROR_MASK__enumvalues = { - 0: 'HDMI_ERROR_MASK_INT', - 1: 'HDMI_ERROR_NOT_MASK', -} -HDMI_ERROR_MASK_INT = 0 -HDMI_ERROR_NOT_MASK = 1 -HDMI_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE' -HDMI_GC_AVMUTE__enumvalues = { - 0: 'HDMI_GC_AVMUTE_SET', - 1: 'HDMI_GC_AVMUTE_UNSET', -} -HDMI_GC_AVMUTE_SET = 0 -HDMI_GC_AVMUTE_UNSET = 1 -HDMI_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_AVMUTE_CONT' -HDMI_GC_AVMUTE_CONT__enumvalues = { - 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', - 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', -} -HDMI_GC_AVMUTE_CONT_DISABLE = 0 -HDMI_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_CONT' -HDMI_GC_CONT__enumvalues = { - 0: 'HDMI_GC_CONT_DISABLE', - 1: 'HDMI_GC_CONT_ENABLE', -} -HDMI_GC_CONT_DISABLE = 0 -HDMI_GC_CONT_ENABLE = 1 -HDMI_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GC_SEND' -HDMI_GC_SEND__enumvalues = { - 0: 'HDMI_GC_NOT_SEND', - 1: 'HDMI_GC_PKT_SEND', -} -HDMI_GC_NOT_SEND = 0 -HDMI_GC_PKT_SEND = 1 -HDMI_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_CONT' -HDMI_GENERIC_CONT__enumvalues = { - 0: 'HDMI_GENERIC_CONT_DISABLE', - 1: 'HDMI_GENERIC_CONT_ENABLE', -} -HDMI_GENERIC_CONT_DISABLE = 0 -HDMI_GENERIC_CONT_ENABLE = 1 -HDMI_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_GENERIC_SEND' -HDMI_GENERIC_SEND__enumvalues = { - 0: 'HDMI_GENERIC_NOT_SEND', - 1: 'HDMI_GENERIC_PKT_SEND', -} -HDMI_GENERIC_NOT_SEND = 0 -HDMI_GENERIC_PKT_SEND = 1 -HDMI_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_CONT' -HDMI_ISRC_CONT__enumvalues = { - 0: 'HDMI_ISRC_CONT_DISABLE', - 1: 'HDMI_ISRC_CONT_ENABLE', -} -HDMI_ISRC_CONT_DISABLE = 0 -HDMI_ISRC_CONT_ENABLE = 1 -HDMI_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_ISRC_SEND' -HDMI_ISRC_SEND__enumvalues = { - 0: 'HDMI_ISRC_NOT_SEND', - 1: 'HDMI_ISRC_PKT_SEND', -} -HDMI_ISRC_NOT_SEND = 0 -HDMI_ISRC_PKT_SEND = 1 -HDMI_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_KEEPOUT_MODE' -HDMI_KEEPOUT_MODE__enumvalues = { - 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', -} -HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 -HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 -HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_METADATA_ENABLE' -HDMI_METADATA_ENABLE__enumvalues = { - 0: 'HDMI_METADATA_NOT_SEND', - 1: 'HDMI_METADATA_PKT_SEND', -} -HDMI_METADATA_NOT_SEND = 0 -HDMI_METADATA_PKT_SEND = 1 -HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_CONT' -HDMI_MPEG_INFO_CONT__enumvalues = { - 0: 'HDMI_MPEG_INFO_CONT_DISABLE', - 1: 'HDMI_MPEG_INFO_CONT_ENABLE', -} -HDMI_MPEG_INFO_CONT_DISABLE = 0 -HDMI_MPEG_INFO_CONT_ENABLE = 1 -HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_MPEG_INFO_SEND' -HDMI_MPEG_INFO_SEND__enumvalues = { - 0: 'HDMI_MPEG_INFO_NOT_SEND', - 1: 'HDMI_MPEG_INFO_PKT_SEND', -} -HDMI_MPEG_INFO_NOT_SEND = 0 -HDMI_MPEG_INFO_PKT_SEND = 1 -HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' -HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { - 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', - 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', -} -HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 -HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 -HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_NULL_SEND' -HDMI_NULL_SEND__enumvalues = { - 0: 'HDMI_NULL_NOT_SEND', - 1: 'HDMI_NULL_PKT_SEND', -} -HDMI_NULL_NOT_SEND = 0 -HDMI_NULL_PKT_SEND = 1 -HDMI_NULL_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_GEN_VERSION' -HDMI_PACKET_GEN_VERSION__enumvalues = { - 0: 'HDMI_PACKET_GEN_VERSION_OLD', - 1: 'HDMI_PACKET_GEN_VERSION_NEW', -} -HDMI_PACKET_GEN_VERSION_OLD = 0 -HDMI_PACKET_GEN_VERSION_NEW = 1 -HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' -HDMI_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'HDMI_PKT_LINE_REF_VSYNC', - 1: 'HDMI_PKT_LINE_REF_OTGSOF', -} -HDMI_PKT_LINE_REF_VSYNC = 0 -HDMI_PKT_LINE_REF_OTGSOF = 1 -HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' -HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { - 0: 'HDMI_PACKING_PHASE_SET_BY_HW', - 1: 'HDMI_PACKING_PHASE_SET_BY_SW', -} -HDMI_PACKING_PHASE_SET_BY_HW = 0 -HDMI_PACKING_PHASE_SET_BY_SW = 1 -HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { - 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', -} -LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 -LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 -LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_COLOR_FORMAT' -TMDS_COLOR_FORMAT__enumvalues = { - 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', - 3: 'TMDS_COLOR_FORMAT_RESERVED', -} -TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 -TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 -TMDS_COLOR_FORMAT_DUAL30BPP = 2 -TMDS_COLOR_FORMAT_RESERVED = 3 -TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_INVERT' -TMDS_CTL0_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL0_DATA_NORMAL', - 1: 'TMDS_CTL0_DATA_INVERT_EN', -} -TMDS_CTL0_DATA_NORMAL = 0 -TMDS_CTL0_DATA_INVERT_EN = 1 -TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_MODULATION' -TMDS_CTL0_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', -} -TMDS_CTL0_DATA_MODULATION_DISABLE = 0 -TMDS_CTL0_DATA_MODULATION_BIT0 = 1 -TMDS_CTL0_DATA_MODULATION_BIT1 = 2 -TMDS_CTL0_DATA_MODULATION_BIT2 = 3 -TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_DATA_SEL' -TMDS_CTL0_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', -} -TMDS_CTL0_DATA_SEL0_RESERVED = 0 -TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL0_DATA_SEL2_VSYNC = 2 -TMDS_CTL0_DATA_SEL3_RESERVED = 3 -TMDS_CTL0_DATA_SEL4_HSYNC = 4 -TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 -TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 -TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' -TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', -} -TMDS_CTL0_PATTERN_OUT_DISABLE = 0 -TMDS_CTL0_PATTERN_OUT_ENABLE = 1 -TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_INVERT' -TMDS_CTL1_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL1_DATA_NORMAL', - 1: 'TMDS_CTL1_DATA_INVERT_EN', -} -TMDS_CTL1_DATA_NORMAL = 0 -TMDS_CTL1_DATA_INVERT_EN = 1 -TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_MODULATION' -TMDS_CTL1_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', -} -TMDS_CTL1_DATA_MODULATION_DISABLE = 0 -TMDS_CTL1_DATA_MODULATION_BIT0 = 1 -TMDS_CTL1_DATA_MODULATION_BIT1 = 2 -TMDS_CTL1_DATA_MODULATION_BIT2 = 3 -TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_DATA_SEL' -TMDS_CTL1_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL1_DATA_SEL0_RESERVED = 0 -TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL1_DATA_SEL2_VSYNC = 2 -TMDS_CTL1_DATA_SEL3_RESERVED = 3 -TMDS_CTL1_DATA_SEL4_HSYNC = 4 -TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' -TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', -} -TMDS_CTL1_PATTERN_OUT_DISABLE = 0 -TMDS_CTL1_PATTERN_OUT_ENABLE = 1 -TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_INVERT' -TMDS_CTL2_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL2_DATA_NORMAL', - 1: 'TMDS_CTL2_DATA_INVERT_EN', -} -TMDS_CTL2_DATA_NORMAL = 0 -TMDS_CTL2_DATA_INVERT_EN = 1 -TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_MODULATION' -TMDS_CTL2_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', -} -TMDS_CTL2_DATA_MODULATION_DISABLE = 0 -TMDS_CTL2_DATA_MODULATION_BIT0 = 1 -TMDS_CTL2_DATA_MODULATION_BIT1 = 2 -TMDS_CTL2_DATA_MODULATION_BIT2 = 3 -TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_DATA_SEL' -TMDS_CTL2_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL2_DATA_SEL0_RESERVED = 0 -TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL2_DATA_SEL2_VSYNC = 2 -TMDS_CTL2_DATA_SEL3_RESERVED = 3 -TMDS_CTL2_DATA_SEL4_HSYNC = 4 -TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' -TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', -} -TMDS_CTL2_PATTERN_OUT_DISABLE = 0 -TMDS_CTL2_PATTERN_OUT_ENABLE = 1 -TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_INVERT' -TMDS_CTL3_DATA_INVERT__enumvalues = { - 0: 'TMDS_CTL3_DATA_NORMAL', - 1: 'TMDS_CTL3_DATA_INVERT_EN', -} -TMDS_CTL3_DATA_NORMAL = 0 -TMDS_CTL3_DATA_INVERT_EN = 1 -TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_MODULATION' -TMDS_CTL3_DATA_MODULATION__enumvalues = { - 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', - 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', - 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', - 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', -} -TMDS_CTL3_DATA_MODULATION_DISABLE = 0 -TMDS_CTL3_DATA_MODULATION_BIT0 = 1 -TMDS_CTL3_DATA_MODULATION_BIT1 = 2 -TMDS_CTL3_DATA_MODULATION_BIT2 = 3 -TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_DATA_SEL' -TMDS_CTL3_DATA_SEL__enumvalues = { - 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', - 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', - 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', - 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', - 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', - 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', -} -TMDS_CTL3_DATA_SEL0_RESERVED = 0 -TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 -TMDS_CTL3_DATA_SEL2_VSYNC = 2 -TMDS_CTL3_DATA_SEL3_RESERVED = 3 -TMDS_CTL3_DATA_SEL4_HSYNC = 4 -TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 -TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 -TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 -TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' -TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { - 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', - 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', -} -TMDS_CTL3_PATTERN_OUT_DISABLE = 0 -TMDS_CTL3_PATTERN_OUT_ENABLE = 1 -TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' -TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { - 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', -} -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 -TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_PIXEL_ENCODING' -TMDS_PIXEL_ENCODING__enumvalues = { - 0: 'TMDS_PIXEL_ENCODING_444_OR_420', - 1: 'TMDS_PIXEL_ENCODING_422', -} -TMDS_PIXEL_ENCODING_444_OR_420 = 0 -TMDS_PIXEL_ENCODING_422 = 1 -TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' -TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', -} -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 -TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 -TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 -TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' -TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { - 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', - 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', -} -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 -TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 -TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 -TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' -TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { - 0: 'TMDS_STEREOSYNC_CTL0', - 1: 'TMDS_STEREOSYNC_CTL1', - 2: 'TMDS_STEREOSYNC_CTL2', - 3: 'TMDS_STEREOSYNC_CTL3', -} -TMDS_STEREOSYNC_CTL0 = 0 -TMDS_STEREOSYNC_CTL1 = 1 -TMDS_STEREOSYNC_CTL2 = 2 -TMDS_STEREOSYNC_CTL3 = 3 -TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_SYNC_PHASE' -TMDS_SYNC_PHASE__enumvalues = { - 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', -} -TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TMDS_SYNC_PHASE_ON_FRAME_START = 1 -TMDS_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { - 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', -} -TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 -TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 -TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' -TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' -TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { - 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', -} -TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 -TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 -TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', -} -TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 -TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 -TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', -} -TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 -TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 -TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', -} -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 -TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 -TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', -} -TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 -TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 -TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 -TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { - 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', - 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', -} -TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 -TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 -TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { - 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', -} -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 -TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 -TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' -DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', -} -DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 -DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 -DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', -} -DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 -DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 -DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { - 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', -} -DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 -DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 -DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ARB_STATUS' -DP_AUX_ARB_STATUS__enumvalues = { - 0: 'DP_AUX_IDLE', - 1: 'DP_AUX_IN_USE_LS', - 2: 'DP_AUX_IN_USE_GTC', - 3: 'DP_AUX_IN_USE_SW', - 4: 'DP_AUX_IN_USE_PHYWAKE', -} -DP_AUX_IDLE = 0 -DP_AUX_IN_USE_LS = 1 -DP_AUX_IN_USE_GTC = 2 -DP_AUX_IN_USE_SW = 3 -DP_AUX_IN_USE_PHYWAKE = 4 -DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' -DP_AUX_CONTROL_HPD_SEL__enumvalues = { - 0: 'DP_AUX_CONTROL_HPD1_SELECTED', - 1: 'DP_AUX_CONTROL_HPD2_SELECTED', - 2: 'DP_AUX_CONTROL_HPD3_SELECTED', - 3: 'DP_AUX_CONTROL_HPD4_SELECTED', - 4: 'DP_AUX_CONTROL_HPD5_SELECTED', - 5: 'DP_AUX_CONTROL_NO_HPD_SELECTED', -} -DP_AUX_CONTROL_HPD1_SELECTED = 0 -DP_AUX_CONTROL_HPD2_SELECTED = 1 -DP_AUX_CONTROL_HPD3_SELECTED = 2 -DP_AUX_CONTROL_HPD4_SELECTED = 3 -DP_AUX_CONTROL_HPD5_SELECTED = 4 -DP_AUX_CONTROL_NO_HPD_SELECTED = 5 -DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' -DP_AUX_CONTROL_TEST_MODE__enumvalues = { - 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', -} -DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 -DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 -DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' -DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { - 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', - 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', -} -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 -ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 -DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', -} -DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 -DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 -DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', -} -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 -DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', -} -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 -DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { - 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', -} -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 -DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { - 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', -} -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 -DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { - 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', -} -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 -DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 -DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { - 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', -} -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 -DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' -DP_AUX_ERR_OCCURRED_ACK__enumvalues = { - 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 1: 'DP_AUX_ERR_OCCURRED__ACK', -} -DP_AUX_ERR_OCCURRED__NOT_ACK = 0 -DP_AUX_ERR_OCCURRED__ACK = 1 -DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', -} -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 -DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', -} -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 -DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', -} -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 -DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { - 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', -} -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 -DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_INT_ACK' -DP_AUX_INT_ACK__enumvalues = { - 0: 'DP_AUX_INT__NOT_ACK', - 1: 'DP_AUX_INT__ACK', -} -DP_AUX_INT__NOT_ACK = 0 -DP_AUX_INT__ACK = 1 -DP_AUX_INT_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_LS_UPDATE_ACK' -DP_AUX_LS_UPDATE_ACK__enumvalues = { - 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', - 1: 'DP_AUX_INT_LS_UPDATE_ACK', -} -DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 -DP_AUX_INT_LS_UPDATE_ACK = 1 -DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' -DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { - 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', -} -DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 -DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 -DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' -DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { - 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', - 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', -} -DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 -DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 -DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET' -DP_AUX_RESET__enumvalues = { - 0: 'DP_AUX_RESET_DEASSERTED', - 1: 'DP_AUX_RESET_ASSERTED', -} -DP_AUX_RESET_DEASSERTED = 0 -DP_AUX_RESET_ASSERTED = 1 -DP_AUX_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RESET_DONE' -DP_AUX_RESET_DONE__enumvalues = { - 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', - 1: 'DP_AUX_RESET_SEQUENCE_DONE', -} -DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 -DP_AUX_RESET_SEQUENCE_DONE = 1 -DP_AUX_RESET_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' -DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { - 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', - 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', -} -DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 -DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 -DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 -DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 -DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' -DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', -} -DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 -DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 -DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' -DP_AUX_SW_CONTROL_SW_GO__enumvalues = { - 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 1: 'DP_AUX_SW_CONTROL_SW__GO', -} -DP_AUX_SW_CONTROL_SW__NOT_GO = 0 -DP_AUX_SW_CONTROL_SW__GO = 1 -DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' -DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { - 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', - 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', - 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', -} -DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 -DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 -DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 -DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 -DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ACK' -DOUT_I2C_ACK__enumvalues = { - 0: 'DOUT_I2C_NO_ACK', - 1: 'DOUT_I2C_ACK_TO_CLEAN', -} -DOUT_I2C_NO_ACK = 0 -DOUT_I2C_ACK_TO_CLEAN = 1 -DOUT_I2C_ACK = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' -DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', -} -DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 -DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 -DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', -} -DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 -DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 -DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', -} -DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 -DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 -DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' -DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', -} -DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 -DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 -DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 -DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 -DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { - 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', -} -DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 -DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 -DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' -DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', -} -DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 -DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 -DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' -DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', - 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', - 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', - 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', - 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', - 5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', -} -DOUT_I2C_CONTROL_SELECT_DDC1 = 0 -DOUT_I2C_CONTROL_SELECT_DDC2 = 1 -DOUT_I2C_CONTROL_SELECT_DDC3 = 2 -DOUT_I2C_CONTROL_SELECT_DDC4 = 3 -DOUT_I2C_CONTROL_SELECT_DDC5 = 4 -DOUT_I2C_CONTROL_SELECT_DDCVGA = 5 -DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_GO' -DOUT_I2C_CONTROL_GO__enumvalues = { - 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 1: 'DOUT_I2C_CONTROL_START_TRANSFER', -} -DOUT_I2C_CONTROL_STOP_TRANSFER = 0 -DOUT_I2C_CONTROL_START_TRANSFER = 1 -DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' -DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 1: 'DOUT_I2C_CONTROL__SEND_RESET', -} -DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 -DOUT_I2C_CONTROL__SEND_RESET = 1 -DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' -DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { - 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', -} -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 -DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 -DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' -DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', -} -DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 -DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 -DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' -DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { - 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', -} -DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 -DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 -DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' -DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { - 0: 'DOUT_I2C_CONTROL_TRANS0', - 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', -} -DOUT_I2C_CONTROL_TRANS0 = 0 -DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 -DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 -DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' -DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { - 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 1: 'DOUT_I2C_DATA__INDEX_WRITE', -} -DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 -DOUT_I2C_DATA__INDEX_WRITE = 1 -DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', -} -DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 -DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 -DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', -} -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 -DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { - 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', -} -DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 -DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 -DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' -DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { - 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', -} -DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 -DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 -DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 -DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 -DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { - 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', -} -DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 -DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 -DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { - 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', -} -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 -DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' -DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { - 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', -} -DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 -DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 -DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_EN' -CLOCK_GATING_EN__enumvalues = { - 0: 'CLOCK_GATING_ENABLE', - 1: 'CLOCK_GATING_DISABLE', -} -CLOCK_GATING_ENABLE = 0 -CLOCK_GATING_DISABLE = 1 -CLOCK_GATING_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DAC_MUX_SELECT' -DAC_MUX_SELECT__enumvalues = { - 0: 'DAC_MUX_SELECT_DACA', - 1: 'DAC_MUX_SELECT_DACB', -} -DAC_MUX_SELECT_DACA = 0 -DAC_MUX_SELECT_DACB = 1 -DAC_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_DIS_CTRL' -DIOMEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', -} -DIOMEM_ENABLE_MEM_PWR_CTRL = 0 -DIOMEM_DISABLE_MEM_PWR_CTRL = 1 -DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' -DIOMEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQUEST', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', -} -DIOMEM_NO_FORCE_REQUEST = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 -DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' -DIOMEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'DIOMEM_NO_FORCE_REQ', - 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', -} -DIOMEM_NO_FORCE_REQ = 0 -DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 -DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL' -DIOMEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 -DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' -DIOMEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', -} -DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 -DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 -DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_DBG_BLOCK_SEL' -DIO_DBG_BLOCK_SEL__enumvalues = { - 0: 'DIO_DBG_BLOCK_SEL_DIO', - 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', - 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', - 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', - 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', - 15: 'DIO_DBG_BLOCK_SEL_DIGFE_E', - 18: 'DIO_DBG_BLOCK_SEL_DIGA', - 19: 'DIO_DBG_BLOCK_SEL_DIGB', - 20: 'DIO_DBG_BLOCK_SEL_DIGC', - 21: 'DIO_DBG_BLOCK_SEL_DIGD', - 22: 'DIO_DBG_BLOCK_SEL_DIGE', - 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', - 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', - 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', - 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', - 29: 'DIO_DBG_BLOCK_SEL_DPFE_E', - 32: 'DIO_DBG_BLOCK_SEL_DPA', - 33: 'DIO_DBG_BLOCK_SEL_DPB', - 34: 'DIO_DBG_BLOCK_SEL_DPC', - 35: 'DIO_DBG_BLOCK_SEL_DPD', - 36: 'DIO_DBG_BLOCK_SEL_DPE', - 39: 'DIO_DBG_BLOCK_SEL_AUX0', - 40: 'DIO_DBG_BLOCK_SEL_AUX1', - 41: 'DIO_DBG_BLOCK_SEL_AUX2', - 42: 'DIO_DBG_BLOCK_SEL_AUX3', - 43: 'DIO_DBG_BLOCK_SEL_AUX4', - 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', - 46: 'DIO_DBG_BLOCK_SEL_RESERVED', -} -DIO_DBG_BLOCK_SEL_DIO = 0 -DIO_DBG_BLOCK_SEL_DIGFE_A = 11 -DIO_DBG_BLOCK_SEL_DIGFE_B = 12 -DIO_DBG_BLOCK_SEL_DIGFE_C = 13 -DIO_DBG_BLOCK_SEL_DIGFE_D = 14 -DIO_DBG_BLOCK_SEL_DIGFE_E = 15 -DIO_DBG_BLOCK_SEL_DIGA = 18 -DIO_DBG_BLOCK_SEL_DIGB = 19 -DIO_DBG_BLOCK_SEL_DIGC = 20 -DIO_DBG_BLOCK_SEL_DIGD = 21 -DIO_DBG_BLOCK_SEL_DIGE = 22 -DIO_DBG_BLOCK_SEL_DPFE_A = 25 -DIO_DBG_BLOCK_SEL_DPFE_B = 26 -DIO_DBG_BLOCK_SEL_DPFE_C = 27 -DIO_DBG_BLOCK_SEL_DPFE_D = 28 -DIO_DBG_BLOCK_SEL_DPFE_E = 29 -DIO_DBG_BLOCK_SEL_DPA = 32 -DIO_DBG_BLOCK_SEL_DPB = 33 -DIO_DBG_BLOCK_SEL_DPC = 34 -DIO_DBG_BLOCK_SEL_DPD = 35 -DIO_DBG_BLOCK_SEL_DPE = 36 -DIO_DBG_BLOCK_SEL_AUX0 = 39 -DIO_DBG_BLOCK_SEL_AUX1 = 40 -DIO_DBG_BLOCK_SEL_AUX2 = 41 -DIO_DBG_BLOCK_SEL_AUX3 = 42 -DIO_DBG_BLOCK_SEL_AUX4 = 43 -DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 -DIO_DBG_BLOCK_SEL_RESERVED = 46 -DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { - 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', -} -DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 -DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 -DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { - 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', -} -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 -DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' -ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { - 0: 'ENUM_DCN_NOT_ACTIVE', - 1: 'ENUM_DCN_ACTIVE', -} -ENUM_DCN_NOT_ACTIVE = 0 -ENUM_DCN_ACTIVE = 1 -ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_STEREOSYNC_SEL' -GENERIC_STEREOSYNC_SEL__enumvalues = { - 0: 'GENERIC_STEREOSYNC_SEL_D1', - 1: 'GENERIC_STEREOSYNC_SEL_D2', - 2: 'GENERIC_STEREOSYNC_SEL_D3', - 3: 'GENERIC_STEREOSYNC_SEL_D4', - 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', -} -GENERIC_STEREOSYNC_SEL_D1 = 0 -GENERIC_STEREOSYNC_SEL_D2 = 1 -GENERIC_STEREOSYNC_SEL_D3 = 2 -GENERIC_STEREOSYNC_SEL_D4 = 3 -GENERIC_STEREOSYNC_SEL_RESERVED = 4 -GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PM_ASSERT_RESET' -PM_ASSERT_RESET__enumvalues = { - 0: 'PM_ASSERT_RESET_0', - 1: 'PM_ASSERT_RESET_1', -} -PM_ASSERT_RESET_0 = 0 -PM_ASSERT_RESET_1 = 1 -PM_ASSERT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'SOFT_RESET' -SOFT_RESET__enumvalues = { - 0: 'SOFT_RESET_0', - 1: 'SOFT_RESET_1', -} -SOFT_RESET_0 = 0 -SOFT_RESET_1 = 1 -SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'TMDS_MUX_SELECT' -TMDS_MUX_SELECT__enumvalues = { - 0: 'TMDS_MUX_SELECT_B', - 1: 'TMDS_MUX_SELECT_G', - 2: 'TMDS_MUX_SELECT_R', - 3: 'TMDS_MUX_SELECT_RESERVED', -} -TMDS_MUX_SELECT_B = 0 -TMDS_MUX_SELECT_G = 1 -TMDS_MUX_SELECT_R = 2 -TMDS_MUX_SELECT_RESERVED = 3 -TMDS_MUX_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_POWER_STATE_ENUM' -DME_MEM_POWER_STATE_ENUM__enumvalues = { - 0: 'DME_MEM_POWER_STATE_ENUM_ON', - 1: 'DME_MEM_POWER_STATE_ENUM_LS', - 2: 'DME_MEM_POWER_STATE_ENUM_DS', - 3: 'DME_MEM_POWER_STATE_ENUM_SD', -} -DME_MEM_POWER_STATE_ENUM_ON = 0 -DME_MEM_POWER_STATE_ENUM_LS = 1 -DME_MEM_POWER_STATE_ENUM_DS = 2 -DME_MEM_POWER_STATE_ENUM_SD = 3 -DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_DIS_CTRL' -DME_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', -} -DME_MEM_ENABLE_MEM_PWR_CTRL = 0 -DME_MEM_DISABLE_MEM_PWR_CTRL = 1 -DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' -DME_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'DME_MEM_NO_FORCE_REQUEST', - 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', -} -DME_MEM_NO_FORCE_REQUEST = 0 -DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_HUBP_SEL' -METADATA_HUBP_SEL__enumvalues = { - 0: 'METADATA_HUBP_SEL_0', - 1: 'METADATA_HUBP_SEL_1', - 2: 'METADATA_HUBP_SEL_2', - 3: 'METADATA_HUBP_SEL_3', - 4: 'METADATA_HUBP_SEL_RESERVED', -} -METADATA_HUBP_SEL_0 = 0 -METADATA_HUBP_SEL_1 = 1 -METADATA_HUBP_SEL_2 = 2 -METADATA_HUBP_SEL_3 = 3 -METADATA_HUBP_SEL_RESERVED = 4 -METADATA_HUBP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'METADATA_STREAM_TYPE_SEL' -METADATA_STREAM_TYPE_SEL__enumvalues = { - 0: 'METADATA_STREAM_DP', - 1: 'METADATA_STREAM_DVE', -} -METADATA_STREAM_DP = 0 -METADATA_STREAM_DVE = 1 -METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' -VPG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', -} -VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 -VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 -VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' -VPG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'VPG_MEM_NO_FORCE_REQ', - 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', -} -VPG_MEM_NO_FORCE_REQ = 0 -VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 -VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_ACP_TYPE' -AFMT_ACP_TYPE__enumvalues = { - 0: 'ACP_TYPE_GENERIC_AUDIO', - 1: 'ACP_TYPE_ICE60958_AUDIO', - 2: 'ACP_TYPE_DVD_AUDIO', - 3: 'ACP_TYPE_SUPER_AUDIO_CD', -} -ACP_TYPE_GENERIC_AUDIO = 0 -ACP_TYPE_ICE60958_AUDIO = 1 -ACP_TYPE_DVD_AUDIO = 2 -ACP_TYPE_SUPER_AUDIO_CD = 3 -AFMT_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' -AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'AFMT_AUDIO_CRC_CH0_SIG', - 1: 'AFMT_AUDIO_CRC_CH1_SIG', - 2: 'AFMT_AUDIO_CRC_CH2_SIG', - 3: 'AFMT_AUDIO_CRC_CH3_SIG', - 4: 'AFMT_AUDIO_CRC_CH4_SIG', - 5: 'AFMT_AUDIO_CRC_CH5_SIG', - 6: 'AFMT_AUDIO_CRC_CH6_SIG', - 7: 'AFMT_AUDIO_CRC_CH7_SIG', - 8: 'AFMT_AUDIO_CRC_RESERVED_8', - 9: 'AFMT_AUDIO_CRC_RESERVED_9', - 10: 'AFMT_AUDIO_CRC_RESERVED_10', - 11: 'AFMT_AUDIO_CRC_RESERVED_11', - 12: 'AFMT_AUDIO_CRC_RESERVED_12', - 13: 'AFMT_AUDIO_CRC_RESERVED_13', - 14: 'AFMT_AUDIO_CRC_RESERVED_14', - 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', -} -AFMT_AUDIO_CRC_CH0_SIG = 0 -AFMT_AUDIO_CRC_CH1_SIG = 1 -AFMT_AUDIO_CRC_CH2_SIG = 2 -AFMT_AUDIO_CRC_CH3_SIG = 3 -AFMT_AUDIO_CRC_CH4_SIG = 4 -AFMT_AUDIO_CRC_CH5_SIG = 5 -AFMT_AUDIO_CRC_CH6_SIG = 6 -AFMT_AUDIO_CRC_CH7_SIG = 7 -AFMT_AUDIO_CRC_RESERVED_8 = 8 -AFMT_AUDIO_CRC_RESERVED_9 = 9 -AFMT_AUDIO_CRC_RESERVED_10 = 10 -AFMT_AUDIO_CRC_RESERVED_11 = 11 -AFMT_AUDIO_CRC_RESERVED_12 = 12 -AFMT_AUDIO_CRC_RESERVED_13 = 13 -AFMT_AUDIO_CRC_RESERVED_14 = 14 -AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 -AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' -AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'AFMT_AUDIO_CRC_ONESHOT', - 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', -} -AFMT_AUDIO_CRC_ONESHOT = 0 -AFMT_AUDIO_CRC_AUTO_RESTART = 1 -AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' -AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { - 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', -} -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 -AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 -AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { - 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', -} -AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 -AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 -AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { - 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', -} -AFMT_AUDIO_PACKET_SENT_DISABLED = 0 -AFMT_AUDIO_PACKET_SENT_ENABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { - 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', -} -AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 -AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 -AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' -AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { - 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', -} -AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 -AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 -AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 -AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 -AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 -AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 -AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { - 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', -} -HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 -HDMI_SEND_MAX_AUDIO_PACKETS = 1 -AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 -AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' -AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { - 0: 'AFMT_INTERRUPT_DISABLE', - 1: 'AFMT_INTERRUPT_ENABLE', -} -AFMT_INTERRUPT_DISABLE = 0 -AFMT_INTERRUPT_ENABLE = 1 -AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' -AFMT_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', -} -AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 -AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 -AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' -AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'AFMT_MEM_NO_FORCE_REQUEST', - 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', -} -AFMT_MEM_NO_FORCE_REQUEST = 0 -AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' -AFMT_RAMP_CONTROL0_SIGN__enumvalues = { - 0: 'AFMT_RAMP_SIGNED', - 1: 'AFMT_RAMP_UNSIGNED', -} -AFMT_RAMP_SIGNED = 0 -AFMT_RAMP_UNSIGNED = 1 -AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', - 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', -} -AFMT_ACP_SOURCE_FROM_AZALIA = 0 -AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 -AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'AUDIO_LAYOUT_SELECT' -AUDIO_LAYOUT_SELECT__enumvalues = { - 0: 'AUDIO_LAYOUT_0', - 1: 'AUDIO_LAYOUT_1', -} -AUDIO_LAYOUT_0 = 0 -AUDIO_LAYOUT_1 = 1 -AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' -HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { - 0: 'HPO_TOP_CLOCK_GATING_EN', - 1: 'HPO_TOP_CLOCK_GATING_DIS', -} -HPO_TOP_CLOCK_GATING_EN = 0 -HPO_TOP_CLOCK_GATING_DIS = 1 -HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HPO_TOP_TEST_CLK_SEL' -HPO_TOP_TEST_CLK_SEL__enumvalues = { - 0: 'HPO_TOP_PERMANENT_DISPCLK', - 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', - 2: 'HPO_TOP_PERMANENT_SOCCLK', - 3: 'HPO_TOP_TEST_CLOCK_RESERVED', - 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', - 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', - 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', -} -HPO_TOP_PERMANENT_DISPCLK = 0 -HPO_TOP_REGISTER_GATED_DISPCLK = 1 -HPO_TOP_PERMANENT_SOCCLK = 2 -HPO_TOP_TEST_CLOCK_RESERVED = 3 -HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 -HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 -HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 -HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 -HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 -HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 -HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 -HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 -HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { - 0: 'DP_STREAM_MAPPER_LINK0', - 1: 'DP_STREAM_MAPPER_LINK1', - 2: 'DP_STREAM_MAPPER_RESERVED', -} -DP_STREAM_MAPPER_LINK0 = 0 -DP_STREAM_MAPPER_LINK1 = 1 -DP_STREAM_MAPPER_RESERVED = 2 -DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL' -HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DB_ENABLE', - 1: 'HDMI_STREAM_ENC_DB_DISABLE', -} -HDMI_STREAM_ENC_DB_ENABLE = 0 -HDMI_STREAM_ENC_DB_DISABLE = 1 -HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE' -HDMI_STREAM_ENC_DSC_MODE__enumvalues = { - 0: 'STREAM_DSC_DISABLE', - 1: 'STREAM_DSC_444_RGB', - 2: 'STREAM_DSC_NATIVE_422_420', -} -STREAM_DSC_DISABLE = 0 -STREAM_DSC_444_RGB = 1 -STREAM_DSC_NATIVE_422_420 = 2 -HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL' -HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DISABLE', - 1: 'HDMI_STREAM_ENC_ENABLE', -} -HDMI_STREAM_ENC_DISABLE = 0 -HDMI_STREAM_ENC_ENABLE = 1 -HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE' -HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = { - 0: 'STREAM_ODM_COMBINE_1_SEGMENT', - 1: 'STREAM_ODM_COMBINE_2_SEGMENT', - 2: 'STREAM_ODM_COMBINE_RESERVED', - 3: 'STREAM_ODM_COMBINE_4_SEGMENT', -} -STREAM_ODM_COMBINE_1_SEGMENT = 0 -STREAM_ODM_COMBINE_2_SEGMENT = 1 -STREAM_ODM_COMBINE_RESERVED = 2 -STREAM_ODM_COMBINE_4_SEGMENT = 3 -HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' -HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', - 1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', - 2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', -} -HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0 -HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1 -HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2 -HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT' -HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { - 0: 'HDMI_STREAM_ENC_HARDWARE', - 1: 'HDMI_STREAM_ENC_PROGRAMMABLE', -} -HDMI_STREAM_ENC_HARDWARE = 0 -HDMI_STREAM_ENC_PROGRAMMABLE = 1 -HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING' -HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'STREAM_PIXEL_ENCODING_444_RGB', - 1: 'STREAM_PIXEL_ENCODING_422', - 2: 'STREAM_PIXEL_ENCODING_420', -} -STREAM_PIXEL_ENCODING_444_RGB = 0 -STREAM_PIXEL_ENCODING_422 = 1 -STREAM_PIXEL_ENCODING_420 = 2 -HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL' -HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_DCCG', - 1: 'HDMI_STREAM_ENC_DISPLAY_PIPE', -} -HDMI_STREAM_ENC_DCCG = 0 -HDMI_STREAM_ENC_DISPLAY_PIPE = 1 -HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL' -HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = { - 0: 'HDMI_STREAM_ENC_NOT_RESET', - 1: 'HDMI_STREAM_ENC_RESET', -} -HDMI_STREAM_ENC_NOT_RESET = 0 -HDMI_STREAM_ENC_RESET = 1 -HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE' -HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = { - 0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', -} -HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 -HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 -HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM' -BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = { - 0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', - 1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', - 2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', - 3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', -} -BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0 -BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1 -BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2 -BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3 -BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_BORROW_MODE' -HDMI_BORROW_MODE__enumvalues = { - 0: 'TB_BORROW_MODE_NONE', - 1: 'TB_BORROW_MODE_ACTIVE', - 2: 'TB_BORROW_MODE_BLANK', - 3: 'TB_BORROW_MODE_RESERVED', -} -TB_BORROW_MODE_NONE = 0 -TB_BORROW_MODE_ACTIVE = 1 -TB_BORROW_MODE_BLANK = 2 -TB_BORROW_MODE_RESERVED = 3 -HDMI_BORROW_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACP_SEND' -HDMI_TB_ENC_ACP_SEND__enumvalues = { - 0: 'TB_ACP_NOT_SEND', - 1: 'TB_ACP_PKT_SEND', -} -TB_ACP_NOT_SEND = 0 -TB_ACP_PKT_SEND = 1 -HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY' -HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = { - 0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', -} -TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 -TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 -HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_CONT' -HDMI_TB_ENC_ACR_CONT__enumvalues = { - 0: 'TB_ACR_CONT_DISABLE', - 1: 'TB_ACR_CONT_ENABLE', -} -TB_ACR_CONT_DISABLE = 0 -TB_ACR_CONT_ENABLE = 1 -HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE' -HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = { - 0: 'TB_ACR_0_MULTIPLE_RESERVED', - 1: 'TB_ACR_1_MULTIPLE', - 2: 'TB_ACR_2_MULTIPLE', - 3: 'TB_ACR_3_MULTIPLE_RESERVED', - 4: 'TB_ACR_4_MULTIPLE', - 5: 'TB_ACR_5_MULTIPLE_RESERVED', - 6: 'TB_ACR_6_MULTIPLE_RESERVED', - 7: 'TB_ACR_7_MULTIPLE_RESERVED', -} -TB_ACR_0_MULTIPLE_RESERVED = 0 -TB_ACR_1_MULTIPLE = 1 -TB_ACR_2_MULTIPLE = 2 -TB_ACR_3_MULTIPLE_RESERVED = 3 -TB_ACR_4_MULTIPLE = 4 -TB_ACR_5_MULTIPLE_RESERVED = 5 -TB_ACR_6_MULTIPLE_RESERVED = 6 -TB_ACR_7_MULTIPLE_RESERVED = 7 -HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SELECT' -HDMI_TB_ENC_ACR_SELECT__enumvalues = { - 0: 'TB_ACR_SELECT_HW', - 1: 'TB_ACR_SELECT_32K', - 2: 'TB_ACR_SELECT_44K', - 3: 'TB_ACR_SELECT_48K', -} -TB_ACR_SELECT_HW = 0 -TB_ACR_SELECT_32K = 1 -TB_ACR_SELECT_44K = 2 -TB_ACR_SELECT_48K = 3 -HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SEND' -HDMI_TB_ENC_ACR_SEND__enumvalues = { - 0: 'TB_ACR_NOT_SEND', - 1: 'TB_ACR_PKT_SEND', -} -TB_ACR_NOT_SEND = 0 -TB_ACR_PKT_SEND = 1 -HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE' -HDMI_TB_ENC_ACR_SOURCE__enumvalues = { - 0: 'TB_ACR_SOURCE_HW', - 1: 'TB_ACR_SOURCE_SW', -} -TB_ACR_SOURCE_HW = 0 -TB_ACR_SOURCE_SW = 1 -HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT' -HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = { - 0: 'TB_AUDIO_INFO_CONT_DISABLE', - 1: 'TB_AUDIO_INFO_CONT_ENABLE', -} -TB_AUDIO_INFO_CONT_DISABLE = 0 -TB_AUDIO_INFO_CONT_ENABLE = 1 -HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND' -HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = { - 0: 'TB_AUDIO_INFO_NOT_SEND', - 1: 'TB_AUDIO_INFO_PKT_SEND', -} -TB_AUDIO_INFO_NOT_SEND = 0 -TB_AUDIO_INFO_PKT_SEND = 1 -HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL' -HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = { - 0: 'TB_CRC_TB_ENC_INPUT', - 1: 'TB_CRC_DSC_PACKER', - 2: 'TB_CRC_DEEP_COLOR_PACKER', - 3: 'TB_CRC_ENCRYPTOR_INPUT', -} -TB_CRC_TB_ENC_INPUT = 0 -TB_CRC_DSC_PACKER = 1 -TB_CRC_DEEP_COLOR_PACKER = 2 -TB_CRC_ENCRYPTOR_INPUT = 3 -HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_CRC_TYPE' -HDMI_TB_ENC_CRC_TYPE__enumvalues = { - 0: 'TB_CRC_ALL_TRIBYTES', - 1: 'TB_CRC_ACTIVE_TRIBYTES', - 2: 'TB_CRC_DATAISLAND_TRIBYTES', - 3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', -} -TB_CRC_ALL_TRIBYTES = 0 -TB_CRC_ACTIVE_TRIBYTES = 1 -TB_CRC_DATAISLAND_TRIBYTES = 2 -TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3 -HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH' -HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = { - 0: 'TB_DEEP_COLOR_DEPTH_24BPP', - 1: 'TB_DEEP_COLOR_DEPTH_30BPP', - 2: 'TB_DEEP_COLOR_DEPTH_36BPP', - 3: 'TB_DEEP_COLOR_DEPTH_RESERVED', -} -TB_DEEP_COLOR_DEPTH_24BPP = 0 -TB_DEEP_COLOR_DEPTH_30BPP = 1 -TB_DEEP_COLOR_DEPTH_36BPP = 2 -TB_DEEP_COLOR_DEPTH_RESERVED = 3 -HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE' -HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = { - 0: 'TB_DEFAULT_PHASE_IS_0', - 1: 'TB_DEFAULT_PHASE_IS_1', -} -TB_DEFAULT_PHASE_IS_0 = 0 -TB_DEFAULT_PHASE_IS_1 = 1 -HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_DSC_MODE' -HDMI_TB_ENC_DSC_MODE__enumvalues = { - 0: 'TB_DSC_DISABLE', - 1: 'TB_DSC_444_RGB', - 2: 'TB_DSC_NATIVE_422_420', -} -TB_DSC_DISABLE = 0 -TB_DSC_444_RGB = 1 -TB_DSC_NATIVE_422_420 = 2 -HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ENABLE' -HDMI_TB_ENC_ENABLE__enumvalues = { - 0: 'TB_DISABLE', - 1: 'TB_ENABLE', -} -TB_DISABLE = 0 -TB_ENABLE = 1 -HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE' -HDMI_TB_ENC_GC_AVMUTE__enumvalues = { - 0: 'TB_GC_AVMUTE_SET', - 1: 'TB_GC_AVMUTE_UNSET', -} -TB_GC_AVMUTE_SET = 0 -TB_GC_AVMUTE_UNSET = 1 -HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT' -HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = { - 0: 'TB_GC_AVMUTE_CONT_DISABLE', - 1: 'TB_GC_AVMUTE_CONT_ENABLE', -} -TB_GC_AVMUTE_CONT_DISABLE = 0 -TB_GC_AVMUTE_CONT_ENABLE = 1 -HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_CONT' -HDMI_TB_ENC_GC_CONT__enumvalues = { - 0: 'TB_GC_CONT_DISABLE', - 1: 'TB_GC_CONT_ENABLE', -} -TB_GC_CONT_DISABLE = 0 -TB_GC_CONT_ENABLE = 1 -HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GC_SEND' -HDMI_TB_ENC_GC_SEND__enumvalues = { - 0: 'TB_GC_NOT_SEND', - 1: 'TB_GC_PKT_SEND', -} -TB_GC_NOT_SEND = 0 -TB_GC_PKT_SEND = 1 -HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT' -HDMI_TB_ENC_GENERIC_CONT__enumvalues = { - 0: 'TB_GENERIC_CONT_DISABLE', - 1: 'TB_GENERIC_CONT_ENABLE', -} -TB_GENERIC_CONT_DISABLE = 0 -TB_GENERIC_CONT_ENABLE = 1 -HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN' -HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = { - 0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', - 1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', -} -HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0 -HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1 -HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND' -HDMI_TB_ENC_GENERIC_SEND__enumvalues = { - 0: 'TB_GENERIC_NOT_SEND', - 1: 'TB_GENERIC_PKT_SEND', -} -TB_GENERIC_NOT_SEND = 0 -TB_GENERIC_PKT_SEND = 1 -HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ISRC_CONT' -HDMI_TB_ENC_ISRC_CONT__enumvalues = { - 0: 'TB_ISRC_CONT_DISABLE', - 1: 'TB_ISRC_CONT_ENABLE', -} -TB_ISRC_CONT_DISABLE = 0 -TB_ISRC_CONT_ENABLE = 1 -HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_ISRC_SEND' -HDMI_TB_ENC_ISRC_SEND__enumvalues = { - 0: 'TB_ISRC_NOT_SEND', - 1: 'TB_ISRC_PKT_SEND', -} -TB_ISRC_NOT_SEND = 0 -TB_ISRC_PKT_SEND = 1 -HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE' -HDMI_TB_ENC_METADATA_ENABLE__enumvalues = { - 0: 'TB_METADATA_NOT_SEND', - 1: 'TB_METADATA_PKT_SEND', -} -TB_METADATA_NOT_SEND = 0 -TB_METADATA_PKT_SEND = 1 -HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE' -HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = { - 0: 'TB_PKT_LINE_REF_END_OF_ACTIVE', - 1: 'TB_PKT_LINE_REF_OTGSOF', -} -TB_PKT_LINE_REF_END_OF_ACTIVE = 0 -TB_PKT_LINE_REF_OTGSOF = 1 -HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING' -HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'TB_PIXEL_ENCODING_444_RGB', - 1: 'TB_PIXEL_ENCODING_422', - 2: 'TB_PIXEL_ENCODING_420', -} -TB_PIXEL_ENCODING_444_RGB = 0 -TB_PIXEL_ENCODING_422 = 1 -TB_PIXEL_ENCODING_420 = 2 -HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_RESET' -HDMI_TB_ENC_RESET__enumvalues = { - 0: 'TB_NOT_RESET', - 1: 'TB_RESET', -} -TB_NOT_RESET = 0 -TB_RESET = 1 -HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE' -HDMI_TB_ENC_SYNC_PHASE__enumvalues = { - 0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START', - 1: 'TB_SYNC_PHASE_ON_FRAME_START', -} -TB_NOT_SYNC_PHASE_ON_FRAME_START = 0 -TB_SYNC_PHASE_ON_FRAME_START = 1 -HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum - -# values for enumeration 'INPUT_FIFO_ERROR_TYPE' -INPUT_FIFO_ERROR_TYPE__enumvalues = { - 0: 'TB_NO_ERROR_OCCURRED', - 1: 'TB_OVERFLOW_OCCURRED', -} -TB_NO_ERROR_OCCURRED = 0 -TB_OVERFLOW_OCCURRED = 1 -INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { - 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', -} -DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 -DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 -DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 -DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { - 0: 'DP_STREAM_ENC_HARDWARE', - 1: 'DP_STREAM_ENC_PROGRAMMABLE', -} -DP_STREAM_ENC_HARDWARE = 0 -DP_STREAM_ENC_PROGRAMMABLE = 1 -DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' -DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_DCCG', - 1: 'DP_STREAM_ENC_DISPLAY_PIPE', -} -DP_STREAM_ENC_DCCG = 0 -DP_STREAM_ENC_DISPLAY_PIPE = 1 -DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' -DP_STREAM_ENC_RESET_CONTROL__enumvalues = { - 0: 'DP_STREAM_ENC_NOT_RESET', - 1: 'DP_STREAM_ENC_RESET', -} -DP_STREAM_ENC_NOT_RESET = 0 -DP_STREAM_ENC_RESET = 1 -DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' -DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { - 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', -} -DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 -DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 -DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' -ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', -} -DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 -DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 -ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { - 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', - 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', -} -DP_SYM32_ENC_ONE_SHOT_MODE = 0 -DP_SYM32_ENC_CONTINUOUS_MODE = 1 -ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' -ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { - 0: 'DP_SYM32_ENC_CRC_NOT_VALID', - 1: 'DP_SYM32_ENC_CRC_VALID', -} -DP_SYM32_ENC_CRC_NOT_VALID = 0 -DP_SYM32_ENC_CRC_VALID = 1 -ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { - 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', -} -DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 -DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 -DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 -DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 -ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' -ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { - 0: 'DP_SYM32_ENC_DISABLE', - 1: 'DP_SYM32_ENC_ENABLE', -} -DP_SYM32_ENC_DISABLE = 0 -DP_SYM32_ENC_ENABLE = 1 -ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', -} -DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 -DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 -ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', -} -DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 -DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 -ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', -} -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 -DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 -ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', -} -DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 -DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 -ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', -} -DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 -DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 -DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 -DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 -ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { - 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', - 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', -} -DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 -DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 -ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' -ENUM_DP_SYM32_ENC_PENDING__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_PENDING', - 1: 'DP_SYM32_ENC_PENDING', -} -DP_SYM32_ENC_NOT_PENDING = 0 -DP_SYM32_ENC_PENDING = 1 -ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { - 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', -} -DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 -DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 -DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { - 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', -} -DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 -DP_SYM32_ENC_COMPRESSED_FORMAT = 1 -ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { - 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', -} -DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 -DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 -DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 -DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 -ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' -ENUM_DP_SYM32_ENC_RESET__enumvalues = { - 0: 'DP_SYM32_ENC_NOT_RESET', - 1: 'DP_SYM32_ENC_RESET', -} -DP_SYM32_ENC_NOT_RESET = 0 -DP_SYM32_ENC_RESET = 1 -ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' -ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { - 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', -} -DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 -DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 -ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' -ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { - 0: 'DP_SYM32_ENC_DP_SOF', - 1: 'DP_SYM32_ENC_OTG_SOF', -} -DP_SYM32_ENC_DP_SOF = 0 -DP_SYM32_ENC_OTG_SOF = 1 -ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { - 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', - 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', -} -DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 -DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 -ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' -ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_END_LLCP', - 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', -} -DP_DPHY_SYM32_CRC_END_LLCP = 0 -DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_END_PS_ANY = 3 -ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' -ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_START_LLCP', - 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 4: 'DP_DPHY_SYM32_CRC_START_TP_START', -} -DP_DPHY_SYM32_CRC_START_LLCP = 0 -DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 -DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 -DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 -DP_DPHY_SYM32_CRC_START_TP_START = 4 -ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', -} -DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 -DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 -DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 -ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { - 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', -} -DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 -DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 -ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' -ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_DISABLE', - 1: 'DP_DPHY_SYM32_ENABLE', -} -DP_DPHY_SYM32_DISABLE = 0 -DP_DPHY_SYM32_ENABLE = 1 -ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE' -ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = { - 0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0', - 1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1', -} -DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0 -DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1 -ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' -ENUM_DP_DPHY_SYM32_MODE__enumvalues = { - 0: 'DP_DPHY_SYM32_LT_TPS1', - 1: 'DP_DPHY_SYM32_LT_TPS2', - 2: 'DP_DPHY_SYM32_ACTIVE', - 3: 'DP_DPHY_SYM32_TEST', -} -DP_DPHY_SYM32_LT_TPS1 = 0 -DP_DPHY_SYM32_LT_TPS2 = 1 -DP_DPHY_SYM32_ACTIVE = 2 -DP_DPHY_SYM32_TEST = 3 -ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' -ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { - 0: 'DP_DPHY_SYM32_1LANE', - 1: 'DP_DPHY_SYM32_2LANE', - 2: 'DP_DPHY_SYM32_RESERVED', - 3: 'DP_DPHY_SYM32_4LANE', -} -DP_DPHY_SYM32_1LANE = 0 -DP_DPHY_SYM32_2LANE = 1 -DP_DPHY_SYM32_RESERVED = 2 -DP_DPHY_SYM32_4LANE = 3 -ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', -} -DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 -DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 -ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' -ENUM_DP_DPHY_SYM32_RESET__enumvalues = { - 0: 'DP_DPHY_SYM32_NOT_RESET', - 1: 'DP_DPHY_SYM32_RESET', -} -DP_DPHY_SYM32_NOT_RESET = 0 -DP_DPHY_SYM32_RESET = 1 -ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' -ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', -} -DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 -DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 -ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' -ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', -} -DP_DPHY_SYM32_SAT_NO_UPDATE = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { - 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', -} -DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 -DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 -DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 -ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' -ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { - 0: 'DP_DPHY_SYM32_STATUS_IDLE', - 1: 'DP_DPHY_SYM32_STATUS_ENABLED', -} -DP_DPHY_SYM32_STATUS_IDLE = 0 -DP_DPHY_SYM32_STATUS_ENABLED = 1 -ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', -} -DP_DPHY_SYM32_STREAM_OVR_NONE = 0 -DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 -DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 -ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { - 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', - 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', -} -DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 -DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 -ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', -} -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 -DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 -ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' -ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { - 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', - 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', - 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', -} -DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 -DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 -DP_DPHY_SYM32_TP_SELECT_PRBS = 2 -DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 -DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 -ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' -APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { - 0: 'APG_AUDIO_CRC_CH0_SIG', - 1: 'APG_AUDIO_CRC_CH1_SIG', - 2: 'APG_AUDIO_CRC_CH2_SIG', - 3: 'APG_AUDIO_CRC_CH3_SIG', - 4: 'APG_AUDIO_CRC_CH4_SIG', - 5: 'APG_AUDIO_CRC_CH5_SIG', - 6: 'APG_AUDIO_CRC_CH6_SIG', - 7: 'APG_AUDIO_CRC_CH7_SIG', - 8: 'APG_AUDIO_CRC_RESERVED_8', - 9: 'APG_AUDIO_CRC_RESERVED_9', - 10: 'APG_AUDIO_CRC_RESERVED_10', - 11: 'APG_AUDIO_CRC_RESERVED_11', - 12: 'APG_AUDIO_CRC_RESERVED_12', - 13: 'APG_AUDIO_CRC_RESERVED_13', - 14: 'APG_AUDIO_CRC_RESERVED_14', - 15: 'APG_AUDIO_CRC_RESERVED_15', -} -APG_AUDIO_CRC_CH0_SIG = 0 -APG_AUDIO_CRC_CH1_SIG = 1 -APG_AUDIO_CRC_CH2_SIG = 2 -APG_AUDIO_CRC_CH3_SIG = 3 -APG_AUDIO_CRC_CH4_SIG = 4 -APG_AUDIO_CRC_CH5_SIG = 5 -APG_AUDIO_CRC_CH6_SIG = 6 -APG_AUDIO_CRC_CH7_SIG = 7 -APG_AUDIO_CRC_RESERVED_8 = 8 -APG_AUDIO_CRC_RESERVED_9 = 9 -APG_AUDIO_CRC_RESERVED_10 = 10 -APG_AUDIO_CRC_RESERVED_11 = 11 -APG_AUDIO_CRC_RESERVED_12 = 12 -APG_AUDIO_CRC_RESERVED_13 = 13 -APG_AUDIO_CRC_RESERVED_14 = 14 -APG_AUDIO_CRC_RESERVED_15 = 15 -APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' -APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { - 0: 'APG_AUDIO_CRC_ONESHOT', - 1: 'APG_AUDIO_CRC_CONTINUOUS', -} -APG_AUDIO_CRC_ONESHOT = 0 -APG_AUDIO_CRC_CONTINUOUS = 1 -APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_ACP_TYPE' -APG_DBG_ACP_TYPE__enumvalues = { - 0: 'APG_ACP_TYPE_GENERIC_AUDIO', - 1: 'APG_ACP_TYPE_ICE60958_AUDIO', - 2: 'APG_ACP_TYPE_DVD_AUDIO', - 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', -} -APG_ACP_TYPE_GENERIC_AUDIO = 0 -APG_ACP_TYPE_ICE60958_AUDIO = 1 -APG_ACP_TYPE_DVD_AUDIO = 2 -APG_ACP_TYPE_SUPER_AUDIO_CD = 3 -APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' -APG_DBG_AUDIO_DTO_BASE__enumvalues = { - 0: 'BASE_RATE_48KHZ', - 1: 'BASE_RATE_44P1KHZ', -} -BASE_RATE_48KHZ = 0 -BASE_RATE_44P1KHZ = 1 -APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' -APG_DBG_AUDIO_DTO_DIV__enumvalues = { - 0: 'DIVISOR_BY1', - 1: 'DIVISOR_BY2_RESERVED', - 2: 'DIVISOR_BY3', - 3: 'DIVISOR_BY4_RESERVED', - 4: 'DIVISOR_BY5_RESERVED', - 5: 'DIVISOR_BY6_RESERVED', - 6: 'DIVISOR_BY7_RESERVED', - 7: 'DIVISOR_BY8_RESERVED', -} -DIVISOR_BY1 = 0 -DIVISOR_BY2_RESERVED = 1 -DIVISOR_BY3 = 2 -DIVISOR_BY4_RESERVED = 3 -DIVISOR_BY5_RESERVED = 4 -DIVISOR_BY6_RESERVED = 5 -DIVISOR_BY7_RESERVED = 6 -DIVISOR_BY8_RESERVED = 7 -APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' -APG_DBG_AUDIO_DTO_MULTI__enumvalues = { - 0: 'MULTIPLE_BY1', - 1: 'MULTIPLE_BY2', - 2: 'MULTIPLE_BY3_RESERVED', - 3: 'MULTIPLE_BY4', - 4: 'MULTIPLE_RESERVED', -} -MULTIPLE_BY1 = 0 -MULTIPLE_BY2 = 1 -MULTIPLE_BY3_RESERVED = 2 -MULTIPLE_BY4 = 3 -MULTIPLE_RESERVED = 4 -APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DBG_MUX_SEL' -APG_DBG_MUX_SEL__enumvalues = { - 0: 'APG_FUNCTIONAL_MODE', - 1: 'APG_DEBUG_AUDIO_MODE', -} -APG_FUNCTIONAL_MODE = 0 -APG_DEBUG_AUDIO_MODE = 1 -APG_DBG_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { - 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', -} -APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 -APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_POWER_STATE' -APG_MEM_POWER_STATE__enumvalues = { - 0: 'APG_MEM_POWER_STATE_ON', - 1: 'APG_MEM_POWER_STATE_LS', - 2: 'APG_MEM_POWER_STATE_DS', - 3: 'APG_MEM_POWER_STATE_SD', -} -APG_MEM_POWER_STATE_ON = 0 -APG_MEM_POWER_STATE_LS = 1 -APG_MEM_POWER_STATE_DS = 2 -APG_MEM_POWER_STATE_SD = 3 -APG_MEM_POWER_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_DIS_CTRL' -APG_MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', -} -APG_MEM_ENABLE_MEM_PWR_CTRL = 0 -APG_MEM_DISABLE_MEM_PWR_CTRL = 1 -APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' -APG_MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'APG_MEM_NO_FORCE_REQUEST', - 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', -} -APG_MEM_NO_FORCE_REQUEST = 0 -APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 -APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 -APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 -APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' -APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { - 0: 'APG_ACP_SOURCE_NO_OVERRIDE', - 1: 'APG_ACP_OVERRIDE', -} -APG_ACP_SOURCE_NO_OVERRIDE = 0 -APG_ACP_OVERRIDE = 1 -APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { - 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', -} -APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 -APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 -APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'APG_RAMP_CONTROL_SIGN' -APG_RAMP_CONTROL_SIGN__enumvalues = { - 0: 'APG_RAMP_SIGNED', - 1: 'APG_RAMP_UNSIGNED', -} -APG_RAMP_SIGNED = 0 -APG_RAMP_UNSIGNED = 1 -APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { - 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', -} -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 -DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { - 0: 'DCIO_TEST_CLK_SEL_DISPCLK', - 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', - 2: 'DCIO_TEST_CLK_SEL_SOCCLK', -} -DCIO_TEST_CLK_SEL_DISPCLK = 0 -DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 -DCIO_TEST_CLK_SEL_SOCCLK = 2 -DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { - 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', -} -DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 -DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 -DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' -DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', - 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', -} -DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 -DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 -DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 -DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 -DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 -DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 -DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 -DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 -DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' -DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { - 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', - 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', - 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', -} -DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 -DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 -DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 -DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 -DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' -DCIO_DCRXPHY_SOFT_RESET__enumvalues = { - 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', - 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', -} -DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 -DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 -DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICA_SEL' -DCIO_DC_GENERICA_SEL__enumvalues = { - 1: 'DCIO_GENERICA_SEL_STEREOSYNC', - 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', - 11: 'DCIO_GENERICA_SEL_SYNCEN', -} -DCIO_GENERICA_SEL_STEREOSYNC = 1 -DCIO_GENERICA_SEL_GENERICA_DCCG = 10 -DCIO_GENERICA_SEL_SYNCEN = 11 -DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERICB_SEL' -DCIO_DC_GENERICB_SEL__enumvalues = { - 1: 'DCIO_GENERICB_SEL_STEREOSYNC', - 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 11: 'DCIO_GENERICB_SEL_SYNCEN', -} -DCIO_GENERICB_SEL_STEREOSYNC = 1 -DCIO_GENERICB_SEL_GENERICB_DCCG = 10 -DCIO_GENERICB_SEL_SYNCEN = 11 -DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', -} -DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 -DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 -DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 -DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 -DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 -DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 -DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_CLK', -} -DCIO_UNIPHYA_FBDIV_CLK = 0 -DCIO_UNIPHYB_FBDIV_CLK = 1 -DCIO_UNIPHYC_FBDIV_CLK = 2 -DCIO_UNIPHYD_FBDIV_CLK = 3 -DCIO_UNIPHYE_FBDIV_CLK = 4 -DCIO_UNIPHYF_FBDIV_CLK = 5 -DCIO_UNIPHYG_FBDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', - 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', - 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', - 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', - 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', - 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', -} -DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 -DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 -DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 -DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 -DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 -DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 -DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { - 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', - 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', - 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', - 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', - 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', - 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', - 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', -} -DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 -DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 -DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 -DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 -DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 -DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 -DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 -DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { - 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', - 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', -} -DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 -DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 -DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' -DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { - 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', -} -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 -DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 -DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 -DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' -DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { - 0: 'DCIO_GPU_TIMER_START_0_END_27', - 1: 'DCIO_GPU_TIMER_START_1_END_28', - 2: 'DCIO_GPU_TIMER_START_2_END_29', - 3: 'DCIO_GPU_TIMER_START_3_END_30', - 4: 'DCIO_GPU_TIMER_START_4_END_31', - 5: 'DCIO_GPU_TIMER_START_6_END_33', - 6: 'DCIO_GPU_TIMER_START_8_END_35', - 7: 'DCIO_GPU_TIMER_START_10_END_37', -} -DCIO_GPU_TIMER_START_0_END_27 = 0 -DCIO_GPU_TIMER_START_1_END_28 = 1 -DCIO_GPU_TIMER_START_2_END_29 = 2 -DCIO_GPU_TIMER_START_3_END_30 = 3 -DCIO_GPU_TIMER_START_4_END_31 = 4 -DCIO_GPU_TIMER_START_6_END_33 = 5 -DCIO_GPU_TIMER_START_8_END_35 = 6 -DCIO_GPU_TIMER_START_10_END_37 = 7 -DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', -} -DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 -DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 -DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 -DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { - 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', - 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', -} -DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 -DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 -DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 -DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 -DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' -DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MASK_NONE', - 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', - 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', - 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', - 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', - 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', - 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', - 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', -} -DCIO_EXT_VSYNC_MASK_NONE = 0 -DCIO_EXT_VSYNC_MASK_PIPE0 = 1 -DCIO_EXT_VSYNC_MASK_PIPE1 = 2 -DCIO_EXT_VSYNC_MASK_PIPE2 = 3 -DCIO_EXT_VSYNC_MASK_PIPE3 = 4 -DCIO_EXT_VSYNC_MASK_PIPE4 = 5 -DCIO_EXT_VSYNC_MASK_PIPE5 = 6 -DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 -DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' -DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { - 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 1: 'DCIO_EXT_VSYNC_MUX_OTG0', - 2: 'DCIO_EXT_VSYNC_MUX_OTG1', - 3: 'DCIO_EXT_VSYNC_MUX_OTG2', - 4: 'DCIO_EXT_VSYNC_MUX_OTG3', - 5: 'DCIO_EXT_VSYNC_MUX_OTG4', - 6: 'DCIO_EXT_VSYNC_MUX_OTG5', - 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', -} -DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 -DCIO_EXT_VSYNC_MUX_OTG0 = 1 -DCIO_EXT_VSYNC_MUX_OTG1 = 2 -DCIO_EXT_VSYNC_MUX_OTG2 = 3 -DCIO_EXT_VSYNC_MUX_OTG3 = 4 -DCIO_EXT_VSYNC_MUX_OTG4 = 5 -DCIO_EXT_VSYNC_MUX_OTG5 = 6 -DCIO_EXT_VSYNC_MUX_GENERICB = 7 -DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' -DCIO_DPCS_INTERRUPT_MASK__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_DISABLE', - 1: 'DCIO_DPCS_INTERRUPT_ENABLE', -} -DCIO_DPCS_INTERRUPT_DISABLE = 0 -DCIO_DPCS_INTERRUPT_ENABLE = 1 -DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' -DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { - 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', -} -DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 -DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 -DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_DSYNC_SOFT_RESET' -DCIO_DSYNC_SOFT_RESET__enumvalues = { - 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', -} -DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 -DCIO_DSYNC_SOFT_RESET_ASSERT = 1 -DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' -DCIO_GENLK_CLK_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', - 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', -} -DCIO_GENLK_CLK_GSL_MASK_NO = 0 -DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 -DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 -DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' -DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { - 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', -} -DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 -DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 -DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 -DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_GSL_SEL' -DCIO_GSL_SEL__enumvalues = { - 0: 'DCIO_GSL_SEL_GROUP_0', - 1: 'DCIO_GSL_SEL_GROUP_1', - 2: 'DCIO_GSL_SEL_GROUP_2', -} -DCIO_GSL_SEL_GROUP_0 = 0 -DCIO_GSL_SEL_GROUP_1 = 1 -DCIO_GSL_SEL_GROUP_2 = 2 -DCIO_GSL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' -DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { - 0: 'HPO_SRC0', - 1: 'HPO_SRC_RESERVED', -} -HPO_SRC0 = 0 -HPO_SRC_RESERVED = 1 -DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' -DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' -DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { - 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', - 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', - 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', -} -DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 -DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 -DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 -DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', -} -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 -DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' -DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { - 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', -} -DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 -DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 -DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { - 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', -} -DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 -DCIO_UNIPHY_CHANNEL_INVERTED = 1 -DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { - 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', - 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', -} -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 -DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 -DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' -DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { - 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', - 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', -} -DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 -DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 -DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' -DCIOCHIP_AUX_CSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', -} -DCIOCHIP_AUX_CSEL_DEC1P0 = 0 -DCIOCHIP_AUX_CSEL_DEC0P9 = 1 -DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' -DCIOCHIP_AUX_CSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_CSEL_INC1P0', - 1: 'DCIOCHIP_AUX_CSEL_INC1P1', -} -DCIOCHIP_AUX_CSEL_INC1P0 = 0 -DCIOCHIP_AUX_CSEL_INC1P1 = 1 -DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' -DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', - 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', -} -DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 -DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 -DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 -DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' -DCIOCHIP_AUX_HYS_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_HYS_TUNE_0', - 1: 'DCIOCHIP_AUX_HYS_TUNE_1', - 2: 'DCIOCHIP_AUX_HYS_TUNE_2', - 3: 'DCIOCHIP_AUX_HYS_TUNE_3', -} -DCIOCHIP_AUX_HYS_TUNE_0 = 0 -DCIOCHIP_AUX_HYS_TUNE_1 = 1 -DCIOCHIP_AUX_HYS_TUNE_2 = 2 -DCIOCHIP_AUX_HYS_TUNE_3 = 3 -DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' -DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', - 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', -} -DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 -DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 -DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 -DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 -DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' -DCIOCHIP_AUX_RSEL0P9__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', - 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', -} -DCIOCHIP_AUX_RSEL_DEC1P0 = 0 -DCIOCHIP_AUX_RSEL_DEC0P9 = 1 -DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' -DCIOCHIP_AUX_RSEL1P1__enumvalues = { - 0: 'DCIOCHIP_AUX_RSEL_INC1P0', - 1: 'DCIOCHIP_AUX_RSEL_INC1P1', -} -DCIOCHIP_AUX_RSEL_INC1P0 = 0 -DCIOCHIP_AUX_RSEL_INC1P1 = 1 -DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' -DCIOCHIP_AUX_SPIKESEL__enumvalues = { - 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', - 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', -} -DCIOCHIP_AUX_SPIKESEL_50NS = 0 -DCIOCHIP_AUX_SPIKESEL_10NS = 1 -DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' -DCIOCHIP_AUX_VOD_TUNE__enumvalues = { - 0: 'DCIOCHIP_AUX_VOD_TUNE_0', - 1: 'DCIOCHIP_AUX_VOD_TUNE_1', - 2: 'DCIOCHIP_AUX_VOD_TUNE_2', - 3: 'DCIOCHIP_AUX_VOD_TUNE_3', -} -DCIOCHIP_AUX_VOD_TUNE_0 = 0 -DCIOCHIP_AUX_VOD_TUNE_1 = 1 -DCIOCHIP_AUX_VOD_TUNE_2 = 2 -DCIOCHIP_AUX_VOD_TUNE_3 = 3 -DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' -DCIOCHIP_GPIO_MASK_EN__enumvalues = { - 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', -} -DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 -DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 -DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_HPD_SEL' -DCIOCHIP_HPD_SEL__enumvalues = { - 0: 'DCIOCHIP_HPD_SEL_ASYNC', - 1: 'DCIOCHIP_HPD_SEL_CLOCKED', -} -DCIOCHIP_HPD_SEL_ASYNC = 0 -DCIOCHIP_HPD_SEL_CLOCKED = 1 -DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_COMPSEL' -DCIOCHIP_I2C_COMPSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_REC_SCHMIT', - 1: 'DCIOCHIP_I2C_REC_COMPARATOR', -} -DCIOCHIP_I2C_REC_SCHMIT = 0 -DCIOCHIP_I2C_REC_COMPARATOR = 1 -DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' -DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { - 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', - 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', - 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', -} -DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 -DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 -DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 -DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 -DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' -DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { - 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', - 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', -} -DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 -DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 -DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 -DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 -DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' -DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { - 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', - 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', -} -DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 -DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 -DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_INVERT' -DCIOCHIP_INVERT__enumvalues = { - 0: 'DCIOCHIP_POL_NON_INVERT', - 1: 'DCIOCHIP_POL_INVERT', -} -DCIOCHIP_POL_NON_INVERT = 0 -DCIOCHIP_POL_INVERT = 1 -DCIOCHIP_INVERT = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_MASK' -DCIOCHIP_MASK__enumvalues = { - 0: 'DCIOCHIP_MASK_DISABLE', - 1: 'DCIOCHIP_MASK_ENABLE', -} -DCIOCHIP_MASK_DISABLE = 0 -DCIOCHIP_MASK_ENABLE = 1 -DCIOCHIP_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PAD_MODE' -DCIOCHIP_PAD_MODE__enumvalues = { - 0: 'DCIOCHIP_PAD_MODE_DDC', - 1: 'DCIOCHIP_PAD_MODE_DP', -} -DCIOCHIP_PAD_MODE_DDC = 0 -DCIOCHIP_PAD_MODE_DP = 1 -DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_PD_EN' -DCIOCHIP_PD_EN__enumvalues = { - 0: 'DCIOCHIP_PD_EN_NOTALLOW', - 1: 'DCIOCHIP_PD_EN_ALLOW', -} -DCIOCHIP_PD_EN_NOTALLOW = 0 -DCIOCHIP_PD_EN_ALLOW = 1 -DCIOCHIP_PD_EN = ctypes.c_uint32 # enum - -# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' -DCIOCHIP_REF_27_SRC_SEL__enumvalues = { - 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', -} -DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 -DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 -DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 -DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', -} -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 -PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', -} -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 -PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 -PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { - 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', -} -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 -PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 -PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_DISABLE', - 1: 'PWRSEQ_BL_PWM_ENABLE', -} -PWRSEQ_BL_PWM_DISABLE = 0 -PWRSEQ_BL_PWM_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', -} -PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 -PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 -PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', -} -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 -PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', -} -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 -PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' -PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { - 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', -} -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 -PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_GPIO_MASK_EN' -PWRSEQ_GPIO_MASK_EN__enumvalues = { - 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', -} -PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 -PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 -PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_OFF', - 1: 'PWRSEQ_PANEL_BLON_ON', -} -PWRSEQ_PANEL_BLON_OFF = 0 -PWRSEQ_PANEL_BLON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', -} -PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_BLON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_OFF', - 1: 'PWRSEQ_PANEL_DIGON_ON', -} -PWRSEQ_PANEL_DIGON_OFF = 0 -PWRSEQ_PANEL_DIGON_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', -} -PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 -PWRSEQ_PANEL_DIGON_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { - 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', -} -PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 -PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { - 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', -} -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 -PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 -PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { - 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', -} -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 -PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 -PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_CORB_SIZE' -AZ_CORB_SIZE__enumvalues = { - 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_CORB_SIZE_256ENTRIES', - 3: 'AZ_CORB_SIZE_RESERVED', -} -AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 -AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 -AZ_CORB_SIZE_256ENTRIES = 2 -AZ_CORB_SIZE_RESERVED = 3 -AZ_CORB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_GLOBAL_CAPABILITIES' -AZ_GLOBAL_CAPABILITIES__enumvalues = { - 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', -} -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 -AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 -AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_SIZE' -AZ_RIRB_SIZE__enumvalues = { - 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', - 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', - 2: 'AZ_RIRB_SIZE_256ENTRIES', - 3: 'AZ_RIRB_SIZE_UNDEFINED', -} -AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 -AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 -AZ_RIRB_SIZE_256ENTRIES = 2 -AZ_RIRB_SIZE_UNDEFINED = 3 -AZ_RIRB_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' -AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { - 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', - 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', -} -AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 -AZ_RIRB_WRITE_POINTER_DO_RESET = 1 -AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_STATE_CHANGE_STATUS' -AZ_STATE_CHANGE_STATUS__enumvalues = { - 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', -} -AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 -AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 -AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'CORB_READ_POINTER_RESET' -CORB_READ_POINTER_RESET__enumvalues = { - 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', -} -CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 -CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 -CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { - 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', -} -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 -DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { - 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', -} -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 -GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { - 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', - 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', -} -ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 -ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 -GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' -GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { - 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', -} -CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 -CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 -GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' -GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { - 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 1: 'FLUSH_CONTROL_FLUSH_STARTED', -} -FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 -FLUSH_CONTROL_FLUSH_STARTED = 1 -GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' -GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { - 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', -} -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 -GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 -GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum - -# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { - 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', -} -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 -IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { - 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', -} -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 -RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_0_SYNCHRONIZATION' -STREAM_0_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_10_SYNCHRONIZATION' -STREAM_10_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_11_SYNCHRONIZATION' -STREAM_11_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_12_SYNCHRONIZATION' -STREAM_12_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_13_SYNCHRONIZATION' -STREAM_13_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_14_SYNCHRONIZATION' -STREAM_14_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_15_SYNCHRONIZATION' -STREAM_15_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_1_SYNCHRONIZATION' -STREAM_1_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_2_SYNCHRONIZATION' -STREAM_2_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_3_SYNCHRONIZATION' -STREAM_3_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', -} -STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 -STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 -STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_4_SYNCHRONIZATION' -STREAM_4_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_5_SYNCHRONIZATION' -STREAM_5_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_6_SYNCHRONIZATION' -STREAM_6_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_7_SYNCHRONIZATION' -STREAM_7_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_8_SYNCHRONIZATION' -STREAM_8_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'STREAM_9_SYNCHRONIZATION' -STREAM_9_SYNCHRONIZATION__enumvalues = { - 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', -} -STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 -STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 -STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { - 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', -} -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 -AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', -} -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 -AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { - 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', -} -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 -AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_DIS_CTRL' -MEM_PWR_DIS_CTRL__enumvalues = { - 0: 'ENABLE_MEM_PWR_CTRL', - 1: 'DISABLE_MEM_PWR_CTRL', -} -ENABLE_MEM_PWR_CTRL = 0 -DISABLE_MEM_PWR_CTRL = 1 -MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL' -MEM_PWR_FORCE_CTRL__enumvalues = { - 0: 'NO_FORCE_REQUEST', - 1: 'FORCE_LIGHT_SLEEP_REQUEST', - 2: 'FORCE_DEEP_SLEEP_REQUEST', - 3: 'FORCE_SHUT_DOWN_REQUEST', -} -NO_FORCE_REQUEST = 0 -FORCE_LIGHT_SLEEP_REQUEST = 1 -FORCE_DEEP_SLEEP_REQUEST = 2 -FORCE_SHUT_DOWN_REQUEST = 3 -MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_FORCE_CTRL2' -MEM_PWR_FORCE_CTRL2__enumvalues = { - 0: 'NO_FORCE_REQ', - 1: 'FORCE_LIGHT_SLEEP_REQ', -} -NO_FORCE_REQ = 0 -FORCE_LIGHT_SLEEP_REQ = 1 -MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL' -MEM_PWR_SEL_CTRL__enumvalues = { - 0: 'DYNAMIC_SHUT_DOWN_ENABLE', - 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', - 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', -} -DYNAMIC_SHUT_DOWN_ENABLE = 0 -DYNAMIC_DEEP_SLEEP_ENABLE = 1 -DYNAMIC_LIGHT_SLEEP_ENABLE = 2 -MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'MEM_PWR_SEL_CTRL2' -MEM_PWR_SEL_CTRL2__enumvalues = { - 0: 'DYNAMIC_DEEP_SLEEP_EN', - 1: 'DYNAMIC_LIGHT_SLEEP_EN', -} -DYNAMIC_DEEP_SLEEP_EN = 0 -DYNAMIC_LIGHT_SLEEP_EN = 1 -MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { - 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', -} -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 -CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', -} -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { - 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', -} -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 -AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { - 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', -} -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 -AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' -AZ_LATENCY_COUNTER_CONTROL__enumvalues = { - 0: 'AZ_LATENCY_COUNTER_NO_RESET', - 1: 'AZ_LATENCY_COUNTER_RESET_DONE', -} -AZ_LATENCY_COUNTER_NO_RESET = 0 -AZ_LATENCY_COUNTER_RESET_DONE = 1 -AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', -} -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 -OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum - -# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { - 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', -} -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 -OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', -} -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 -AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', -} -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 -AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum - -# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { - 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', -} -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 -AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' -DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' -DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', -} -DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 -DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' -DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { - 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', -} -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 -DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 -DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ENABLE_ENUM' -DSCC_ENABLE_ENUM__enumvalues = { - 0: 'DSCC_ENABLE_ENUM_DISABLED', - 1: 'DSCC_ENABLE_ENUM_ENABLED', -} -DSCC_ENABLE_ENUM_DISABLED = 0 -DSCC_ENABLE_ENUM_ENABLED = 1 -DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_ICH_RESET_ENUM' -DSCC_ICH_RESET_ENUM__enumvalues = { - 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', -} -DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 -DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 -DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 -DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 -DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' -DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { - 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', -} -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 -DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 -DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' -DSCC_MEM_PWR_DIS_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', - 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', -} -DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 -DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 -DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' -DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', -} -DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 -DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 -DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'POWER_STATE_ENUM' -POWER_STATE_ENUM__enumvalues = { - 0: 'POWER_STATE_ENUM_ON', - 1: 'POWER_STATE_ENUM_LS', - 2: 'POWER_STATE_ENUM_DS', - 3: 'POWER_STATE_ENUM_SD', -} -POWER_STATE_ENUM_ON = 0 -POWER_STATE_ENUM_LS = 1 -POWER_STATE_ENUM_DS = 2 -POWER_STATE_ENUM_SD = 3 -POWER_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' -DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { - 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', -} -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 -DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 -DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_ENABLE_ENUM' -DSCCIF_ENABLE_ENUM__enumvalues = { - 0: 'DSCCIF_ENABLE_ENUM_DISABLED', - 1: 'DSCCIF_ENABLE_ENUM_ENABLED', -} -DSCCIF_ENABLE_ENUM_DISABLED = 0 -DSCCIF_ENABLE_ENUM_ENABLED = 1 -DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' -DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { - 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', -} -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 -DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' -CLOCK_GATING_DISABLE_ENUM__enumvalues = { - 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', - 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', -} -CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 -CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 -CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'ENABLE_ENUM' -ENABLE_ENUM__enumvalues = { - 0: 'ENABLE_ENUM_DISABLED', - 1: 'ENABLE_ENUM_ENABLED', -} -ENABLE_ENUM_DISABLED = 0 -ENABLE_ENUM_ENABLED = 1 -ENABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' -TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { - 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', -} -TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 -TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 -TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 -TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 -TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 -TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 -TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_CONT_EN_ENUM' -DWB_CRC_CONT_EN_ENUM__enumvalues = { - 0: 'DWB_CRC_CONT_EN_ONE_SHOT', - 1: 'DWB_CRC_CONT_EN_CONT', -} -DWB_CRC_CONT_EN_ONE_SHOT = 0 -DWB_CRC_CONT_EN_CONT = 1 -DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' -DWB_CRC_SRC_SEL_ENUM__enumvalues = { - 0: 'DWB_CRC_SRC_SEL_DWB_IN', - 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', - 2: 'DWB_CRC_SRC_SEL_DWB_OUT', -} -DWB_CRC_SRC_SEL_DWB_IN = 0 -DWB_CRC_SRC_SEL_OGAM_OUT = 1 -DWB_CRC_SRC_SEL_DWB_OUT = 2 -DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' -DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', - 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', -} -DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 -DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 -DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' -DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { - 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', - 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', -} -DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 -DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 -DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 -DWB_DATA_OVERFLOW_TYPE_VREADY = 3 -DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_DEBUG_SEL_ENUM' -DWB_DEBUG_SEL_ENUM__enumvalues = { - 0: 'DWB_DEBUG_SEL_FC', - 1: 'DWB_DEBUG_SEL_RESERVED', - 2: 'DWB_DEBUG_SEL_DWBCP', - 3: 'DWB_DEBUG_SEL_PERFMON', -} -DWB_DEBUG_SEL_FC = 0 -DWB_DEBUG_SEL_RESERVED = 1 -DWB_DEBUG_SEL_DWBCP = 2 -DWB_DEBUG_SEL_PERFMON = 3 -DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' -DWB_MEM_PWR_FORCE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_FORCE_DIS', - 1: 'DWB_MEM_PWR_FORCE_LS', - 2: 'DWB_MEM_PWR_FORCE_DS', - 3: 'DWB_MEM_PWR_FORCE_SD', -} -DWB_MEM_PWR_FORCE_DIS = 0 -DWB_MEM_PWR_FORCE_LS = 1 -DWB_MEM_PWR_FORCE_DS = 2 -DWB_MEM_PWR_FORCE_SD = 3 -DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' -DWB_MEM_PWR_STATE_ENUM__enumvalues = { - 0: 'DWB_MEM_PWR_STATE_ON', - 1: 'DWB_MEM_PWR_STATE_LS', - 2: 'DWB_MEM_PWR_STATE_DS', - 3: 'DWB_MEM_PWR_STATE_SD', -} -DWB_MEM_PWR_STATE_ON = 0 -DWB_MEM_PWR_STATE_LS = 1 -DWB_MEM_PWR_STATE_DS = 2 -DWB_MEM_PWR_STATE_SD = 3 -DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' -DWB_TEST_CLK_SEL_ENUM__enumvalues = { - 0: 'DWB_TEST_CLK_SEL_R', - 1: 'DWB_TEST_CLK_SEL_G', - 2: 'DWB_TEST_CLK_SEL_P', -} -DWB_TEST_CLK_SEL_R = 0 -DWB_TEST_CLK_SEL_G = 1 -DWB_TEST_CLK_SEL_P = 2 -DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_EYE_SELECTION_ENUM' -FC_EYE_SELECTION_ENUM__enumvalues = { - 0: 'FC_EYE_SELECTION_STEREO_DIS', - 1: 'FC_EYE_SELECTION_LEFT_EYE', - 2: 'FC_EYE_SELECTION_RIGHT_EYE', -} -FC_EYE_SELECTION_STEREO_DIS = 0 -FC_EYE_SELECTION_LEFT_EYE = 1 -FC_EYE_SELECTION_RIGHT_EYE = 2 -FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' -FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { - 0: 'FC_FRAME_CAPTURE_RATE_FULL', - 1: 'FC_FRAME_CAPTURE_RATE_HALF', - 2: 'FC_FRAME_CAPTURE_RATE_THIRD', - 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', -} -FC_FRAME_CAPTURE_RATE_FULL = 0 -FC_FRAME_CAPTURE_RATE_HALF = 1 -FC_FRAME_CAPTURE_RATE_THIRD = 2 -FC_FRAME_CAPTURE_RATE_QUARTER = 3 -FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' -FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { - 0: 'FC_STEREO_EYE_POLARITY_LEFT', - 1: 'FC_STEREO_EYE_POLARITY_RIGHT', -} -FC_STEREO_EYE_POLARITY_LEFT = 0 -FC_STEREO_EYE_POLARITY_RIGHT = 1 -FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', -} -DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 -DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 -DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' -DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { - 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', - 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', - 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', - 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', -} -DWB_GAMUT_REMAP_MODE_BYPASS = 0 -DWB_GAMUT_REMAP_MODE_COEF_A = 1 -DWB_GAMUT_REMAP_MODE_COEF_B = 2 -DWB_GAMUT_REMAP_MODE_RESERVED = 3 -DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_LUT_NUM_SEG' -DWB_LUT_NUM_SEG__enumvalues = { - 0: 'DWB_SEGMENTS_1', - 1: 'DWB_SEGMENTS_2', - 2: 'DWB_SEGMENTS_4', - 3: 'DWB_SEGMENTS_8', - 4: 'DWB_SEGMENTS_16', - 5: 'DWB_SEGMENTS_32', - 6: 'DWB_SEGMENTS_64', - 7: 'DWB_SEGMENTS_128', -} -DWB_SEGMENTS_1 = 0 -DWB_SEGMENTS_2 = 1 -DWB_SEGMENTS_4 = 2 -DWB_SEGMENTS_8 = 3 -DWB_SEGMENTS_16 = 4 -DWB_SEGMENTS_32 = 5 -DWB_SEGMENTS_64 = 6 -DWB_SEGMENTS_128 = 7 -DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' -DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', - 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', -} -DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 -DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 -DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' -DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', - 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', -} -DWB_OGAM_LUT_HOST_SEL_RAMA = 0 -DWB_OGAM_LUT_HOST_SEL_RAMB = 1 -DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', - 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', -} -DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 -DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 -DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 -DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 -DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' -DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { - 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', - 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', -} -DWB_OGAM_LUT_READ_DBG_DISABLE = 0 -DWB_OGAM_LUT_READ_DBG_ENABLE = 1 -DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_MODE_ENUM' -DWB_OGAM_MODE_ENUM__enumvalues = { - 0: 'DWB_OGAM_MODE_BYPASS', - 1: 'DWB_OGAM_MODE_RESERVED', - 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', -} -DWB_OGAM_MODE_BYPASS = 0 -DWB_OGAM_MODE_RESERVED = 1 -DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 -DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' -DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { - 0: 'DWB_OGAM_PWL_DISABLE_FALSE', - 1: 'DWB_OGAM_PWL_DISABLE_TRUE', -} -DWB_OGAM_PWL_DISABLE_FALSE = 0 -DWB_OGAM_PWL_DISABLE_TRUE = 1 -DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'DWB_OGAM_SELECT_ENUM' -DWB_OGAM_SELECT_ENUM__enumvalues = { - 0: 'DWB_OGAM_SELECT_A', - 1: 'DWB_OGAM_SELECT_B', -} -DWB_OGAM_SELECT_A = 0 -DWB_OGAM_SELECT_B = 1 -DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN' -RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = { - 0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', - 1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', -} -RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0 -RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = { - 0: 'RDPCSPIPE_APBCLK_DISABLE', - 1: 'RDPCSPIPE_APBCLK_ENABLE', -} -RDPCSPIPE_APBCLK_DISABLE = 0 -RDPCSPIPE_APBCLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_PIPE_CLK_CLOCK_OFF', - 1: 'RDPCS_PIPE_CLK_CLOCK_ON', -} -RDPCS_PIPE_CLK_CLOCK_OFF = 0 -RDPCS_PIPE_CLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = { - 0: 'RDPCS_PIPE_CLK_DISABLE', - 1: 'RDPCS_PIPE_CLK_ENABLE', -} -RDPCS_PIPE_CLK_DISABLE = 0 -RDPCS_PIPE_CLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = { - 0: 'RDPCS_PIPE_CLK_GATE_ENABLE', - 1: 'RDPCS_PIPE_CLK_GATE_DISABLE', -} -RDPCS_PIPE_CLK_GATE_ENABLE = 0 -RDPCS_PIPE_CLK_GATE_DISABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = { - 0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', - 1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', -} -RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0 -RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { - 0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', - 1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', -} -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0 -RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_DISABLE', - 1: 'RDPCSPIPE_SRAMCLK_ENABLE', -} -RDPCSPIPE_SRAMCLK_DISABLE = 0 -RDPCSPIPE_SRAMCLK_ENABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', - 1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', -} -RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0 -RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { - 0: 'RDPCSPIPE_SRAMCLK_NOT_PASS', - 1: 'RDPCSPIPE_SRAMCLK_PASS', -} -RDPCSPIPE_SRAMCLK_NOT_PASS = 0 -RDPCSPIPE_SRAMCLK_PASS = 1 -RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN' -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = { - 0: 'RDPCS_PIPE_FIFO_DISABLE', - 1: 'RDPCS_PIPE_FIFO_ENABLE', -} -RDPCS_PIPE_FIFO_DISABLE = 0 -RDPCS_PIPE_FIFO_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN' -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = { - 0: 'RDPCS_PIPE_FIFO_LANE_DISABLE', - 1: 'RDPCS_PIPE_FIFO_LANE_ENABLE', -} -RDPCS_PIPE_FIFO_LANE_DISABLE = 0 -RDPCS_PIPE_FIFO_LANE_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET' -RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = { - 0: 'RDPCS_PIPE_SOFT_RESET_DISABLE', - 1: 'RDPCS_PIPE_SOFT_RESET_ENABLE', -} -RDPCS_PIPE_SOFT_RESET_DISABLE = 0 -RDPCS_PIPE_SOFT_RESET_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET' -RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { - 0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', - 1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', -} -RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0 -RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1 -RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK' -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', - 1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', -} -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0 -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1 -RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL' -RDPCSPIPE_DBG_OCLA_SEL__enumvalues = { - 0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', - 1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', - 2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', - 3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', - 4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', - 5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', - 6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', - 7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', -} -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6 -RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7 -RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_ENC_TYPE' -RDPCSPIPE_ENC_TYPE__enumvalues = { - 0: 'HDMI_TMDS_OR_DP_8B10B', - 1: 'HDMI_FRL', - 2: 'DP_128B132B', -} -HDMI_TMDS_OR_DP_8B10B = 0 -HDMI_FRL = 1 -DP_128B132B = 2 -RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_FIFO_EMPTY' -RDPCSPIPE_FIFO_EMPTY__enumvalues = { - 0: 'RDPCSPIPE_FIFO_NOT_EMPTY', - 1: 'RDPCSPIPE_FIFO_IS_EMPTY', -} -RDPCSPIPE_FIFO_NOT_EMPTY = 0 -RDPCSPIPE_FIFO_IS_EMPTY = 1 -RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_FIFO_FULL' -RDPCSPIPE_FIFO_FULL__enumvalues = { - 0: 'RDPCSPIPE_FIFO_NOT_FULL', - 1: 'RDPCSPIPE_FIFO_IS_FULL', -} -RDPCSPIPE_FIFO_NOT_FULL = 0 -RDPCSPIPE_FIFO_IS_FULL = 1 -RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = { - 0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', - 1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', -} -RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0 -RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { - 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', - 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', -} -RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0 -RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', -} -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 -RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { - 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', - 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', -} -RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0 -RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { - 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', -} -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 -RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', -} -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0 -RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { - 0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', - 1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', -} -RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0 -RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1 -RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK' -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = { - 0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', - 1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', -} -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0 -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1 -RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PACK_MODE' -RDPCSPIPE_PACK_MODE__enumvalues = { - 0: 'TIGHT_PACK', - 1: 'LOOSE_PACK', -} -TIGHT_PACK = 0 -LOOSE_PACK = 1 -RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { - 0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', - 1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', -} -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0 -RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { - 0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', - 1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', -} -RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0 -RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE' -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { - 0: 'RDPCSPIPE_PHY_REF_RANGE_0', - 1: 'RDPCSPIPE_PHY_REF_RANGE_1', - 2: 'RDPCSPIPE_PHY_REF_RANGE_2', - 3: 'RDPCSPIPE_PHY_REF_RANGE_3', - 4: 'RDPCSPIPE_PHY_REF_RANGE_4', - 5: 'RDPCSPIPE_PHY_REF_RANGE_5', - 6: 'RDPCSPIPE_PHY_REF_RANGE_6', - 7: 'RDPCSPIPE_PHY_REF_RANGE_7', -} -RDPCSPIPE_PHY_REF_RANGE_0 = 0 -RDPCSPIPE_PHY_REF_RANGE_1 = 1 -RDPCSPIPE_PHY_REF_RANGE_2 = 2 -RDPCSPIPE_PHY_REF_RANGE_3 = 3 -RDPCSPIPE_PHY_REF_RANGE_4 = 4 -RDPCSPIPE_PHY_REF_RANGE_5 = 5 -RDPCSPIPE_PHY_REF_RANGE_6 = 6 -RDPCSPIPE_PHY_REF_RANGE_7 = 7 -RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { - 0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', - 1: 'RDPCSPIPE_SRAM_EXT_LD_DONE', -} -RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0 -RDPCSPIPE_SRAM_EXT_LD_DONE = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { - 0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE', - 1: 'RDPCSPIPE_SRAM_INIT_DONE', -} -RDPCSPIPE_SRAM_INIT_NOT_DONE = 0 -RDPCSPIPE_SRAM_INIT_DONE = 1 -RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', - 1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', - 2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', - 3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', - 4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', -} -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 -RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', -} -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 -RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 -RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' -RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', - 1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', - 2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', - 3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', - 4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', - 5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', - 6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', - 7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', -} -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 -RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 -RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' -RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', - 1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', - 2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', - 3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', - 4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', - 5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', - 6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', - 7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', -} -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6 -RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7 -RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', -} -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 -RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_RATE', - 1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', - 2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', -} -RDPCSPIPE_PHY_DP_TX_RATE = 0 -RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1 -RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { - 0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', - 1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', - 2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', - 3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', -} -RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0 -RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1 -RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2 -RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3 -RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' -RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { - 0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', - 1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', - 2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', - 3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', -} -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0 -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1 -RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2 -RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3 -RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH' -RDPCSPIPE_PHY_IF_WIDTH__enumvalues = { - 0: 'PHY_IF_WIDTH_10BIT', - 1: 'PHY_IF_WIDTH_20BIT', - 2: 'PHY_IF_WIDTH_40BIT', - 3: 'PHY_IF_WIDTH_80BIT', -} -PHY_IF_WIDTH_10BIT = 0 -PHY_IF_WIDTH_20BIT = 1 -PHY_IF_WIDTH_40BIT = 2 -PHY_IF_WIDTH_80BIT = 3 -RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_RATE' -RDPCSPIPE_PHY_RATE__enumvalues = { - 0: 'PHY_DP_RATE_1P62', - 1: 'PHY_DP_RATE_2P7', - 2: 'PHY_DP_RATE_5P4', - 3: 'PHY_DP_RATE_8P1', - 4: 'PHY_DP_RATE_2P16', - 5: 'PHY_DP_RATE_2P43', - 6: 'PHY_DP_RATE_3P24', - 7: 'PHY_DP_RATE_4P32', - 8: 'PHY_DP_RATE_10P', - 9: 'PHY_DP_RATE_13P5', - 10: 'PHY_DP_RATE_20P', - 15: 'PHY_CUSTOM_RATE', -} -PHY_DP_RATE_1P62 = 0 -PHY_DP_RATE_2P7 = 1 -PHY_DP_RATE_5P4 = 2 -PHY_DP_RATE_8P1 = 3 -PHY_DP_RATE_2P16 = 4 -PHY_DP_RATE_2P43 = 5 -PHY_DP_RATE_3P24 = 6 -PHY_DP_RATE_4P32 = 7 -PHY_DP_RATE_10P = 8 -PHY_DP_RATE_13P5 = 9 -PHY_DP_RATE_20P = 10 -PHY_CUSTOM_RATE = 15 -RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN' -RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = { - 0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', - 1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', -} -RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0 -RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1 -RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL' -RDPCSPIPE_TEST_CLK_SEL__enumvalues = { - 0: 'RDPCSPIPE_TEST_CLK_SEL_NONE', - 1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', - 2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', - 7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', - 8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', - 16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', - 17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', -} -RDPCSPIPE_TEST_CLK_SEL_NONE = 0 -RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 -RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 -RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6 -RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7 -RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 -RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 -RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 -RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 -RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 -RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 -RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 -RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15 -RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16 -RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17 -RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB' -RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { - 0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', - 1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', -} -RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0 -RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1 -RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { - 0: 'RDPCSPIPE_MEM_PWR_NO_FORCE', - 1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', - 2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', - 3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', -} -RDPCSPIPE_MEM_PWR_NO_FORCE = 0 -RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1 -RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2 -RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3 -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum - -# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { - 0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', - 1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', -} -RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0 -RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 -RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 -RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 -RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' -RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { - 0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', - 1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', -} -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0 -RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1 -RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum - -# values for enumeration 'GDS_PERFCOUNT_SELECT' -GDS_PERFCOUNT_SELECT__enumvalues = { - 0: 'GDS_PERF_SEL_WR_COMP', - 1: 'GDS_PERF_SEL_WBUF_WR', - 2: 'GDS_PERF_SEL_SE0_NORET', - 3: 'GDS_PERF_SEL_SE0_RET', - 4: 'GDS_PERF_SEL_SE0_ORD_CNT', - 5: 'GDS_PERF_SEL_SE0_2COMP_REQ', - 6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', - 7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', - 8: 'GDS_PERF_SEL_SE0_GDS_WR_OP', - 9: 'GDS_PERF_SEL_SE0_GDS_RD_OP', - 10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', - 11: 'GDS_PERF_SEL_SE0_GDS_REL_OP', - 12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', - 13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', - 14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', - 15: 'GDS_PERF_SEL_SE1_NORET', - 16: 'GDS_PERF_SEL_SE1_RET', - 17: 'GDS_PERF_SEL_SE1_ORD_CNT', - 18: 'GDS_PERF_SEL_SE1_2COMP_REQ', - 19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', - 20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', - 21: 'GDS_PERF_SEL_SE1_GDS_WR_OP', - 22: 'GDS_PERF_SEL_SE1_GDS_RD_OP', - 23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', - 24: 'GDS_PERF_SEL_SE1_GDS_REL_OP', - 25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', - 26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', - 27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', - 28: 'GDS_PERF_SEL_SE2_NORET', - 29: 'GDS_PERF_SEL_SE2_RET', - 30: 'GDS_PERF_SEL_SE2_ORD_CNT', - 31: 'GDS_PERF_SEL_SE2_2COMP_REQ', - 32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', - 33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', - 34: 'GDS_PERF_SEL_SE2_GDS_WR_OP', - 35: 'GDS_PERF_SEL_SE2_GDS_RD_OP', - 36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', - 37: 'GDS_PERF_SEL_SE2_GDS_REL_OP', - 38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', - 39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', - 40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', - 41: 'GDS_PERF_SEL_SE3_NORET', - 42: 'GDS_PERF_SEL_SE3_RET', - 43: 'GDS_PERF_SEL_SE3_ORD_CNT', - 44: 'GDS_PERF_SEL_SE3_2COMP_REQ', - 45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', - 46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', - 47: 'GDS_PERF_SEL_SE3_GDS_WR_OP', - 48: 'GDS_PERF_SEL_SE3_GDS_RD_OP', - 49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', - 50: 'GDS_PERF_SEL_SE3_GDS_REL_OP', - 51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', - 52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', - 53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', - 54: 'GDS_PERF_SEL_SE4_NORET', - 55: 'GDS_PERF_SEL_SE4_RET', - 56: 'GDS_PERF_SEL_SE4_ORD_CNT', - 57: 'GDS_PERF_SEL_SE4_2COMP_REQ', - 58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', - 59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', - 60: 'GDS_PERF_SEL_SE4_GDS_WR_OP', - 61: 'GDS_PERF_SEL_SE4_GDS_RD_OP', - 62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', - 63: 'GDS_PERF_SEL_SE4_GDS_REL_OP', - 64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', - 65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', - 66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', - 67: 'GDS_PERF_SEL_SE5_NORET', - 68: 'GDS_PERF_SEL_SE5_RET', - 69: 'GDS_PERF_SEL_SE5_ORD_CNT', - 70: 'GDS_PERF_SEL_SE5_2COMP_REQ', - 71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', - 72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', - 73: 'GDS_PERF_SEL_SE5_GDS_WR_OP', - 74: 'GDS_PERF_SEL_SE5_GDS_RD_OP', - 75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', - 76: 'GDS_PERF_SEL_SE5_GDS_REL_OP', - 77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', - 78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', - 79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', - 80: 'GDS_PERF_SEL_SE6_NORET', - 81: 'GDS_PERF_SEL_SE6_RET', - 82: 'GDS_PERF_SEL_SE6_ORD_CNT', - 83: 'GDS_PERF_SEL_SE6_2COMP_REQ', - 84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', - 85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', - 86: 'GDS_PERF_SEL_SE6_GDS_WR_OP', - 87: 'GDS_PERF_SEL_SE6_GDS_RD_OP', - 88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', - 89: 'GDS_PERF_SEL_SE6_GDS_REL_OP', - 90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', - 91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', - 92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', - 93: 'GDS_PERF_SEL_SE7_NORET', - 94: 'GDS_PERF_SEL_SE7_RET', - 95: 'GDS_PERF_SEL_SE7_ORD_CNT', - 96: 'GDS_PERF_SEL_SE7_2COMP_REQ', - 97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', - 98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', - 99: 'GDS_PERF_SEL_SE7_GDS_WR_OP', - 100: 'GDS_PERF_SEL_SE7_GDS_RD_OP', - 101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', - 102: 'GDS_PERF_SEL_SE7_GDS_REL_OP', - 103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', - 104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', - 105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', - 106: 'GDS_PERF_SEL_GWS_RELEASED', - 107: 'GDS_PERF_SEL_GWS_BYPASS', -} -GDS_PERF_SEL_WR_COMP = 0 -GDS_PERF_SEL_WBUF_WR = 1 -GDS_PERF_SEL_SE0_NORET = 2 -GDS_PERF_SEL_SE0_RET = 3 -GDS_PERF_SEL_SE0_ORD_CNT = 4 -GDS_PERF_SEL_SE0_2COMP_REQ = 5 -GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6 -GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7 -GDS_PERF_SEL_SE0_GDS_WR_OP = 8 -GDS_PERF_SEL_SE0_GDS_RD_OP = 9 -GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10 -GDS_PERF_SEL_SE0_GDS_REL_OP = 11 -GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12 -GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13 -GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14 -GDS_PERF_SEL_SE1_NORET = 15 -GDS_PERF_SEL_SE1_RET = 16 -GDS_PERF_SEL_SE1_ORD_CNT = 17 -GDS_PERF_SEL_SE1_2COMP_REQ = 18 -GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19 -GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20 -GDS_PERF_SEL_SE1_GDS_WR_OP = 21 -GDS_PERF_SEL_SE1_GDS_RD_OP = 22 -GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23 -GDS_PERF_SEL_SE1_GDS_REL_OP = 24 -GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25 -GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26 -GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27 -GDS_PERF_SEL_SE2_NORET = 28 -GDS_PERF_SEL_SE2_RET = 29 -GDS_PERF_SEL_SE2_ORD_CNT = 30 -GDS_PERF_SEL_SE2_2COMP_REQ = 31 -GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32 -GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33 -GDS_PERF_SEL_SE2_GDS_WR_OP = 34 -GDS_PERF_SEL_SE2_GDS_RD_OP = 35 -GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36 -GDS_PERF_SEL_SE2_GDS_REL_OP = 37 -GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38 -GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39 -GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40 -GDS_PERF_SEL_SE3_NORET = 41 -GDS_PERF_SEL_SE3_RET = 42 -GDS_PERF_SEL_SE3_ORD_CNT = 43 -GDS_PERF_SEL_SE3_2COMP_REQ = 44 -GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45 -GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46 -GDS_PERF_SEL_SE3_GDS_WR_OP = 47 -GDS_PERF_SEL_SE3_GDS_RD_OP = 48 -GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49 -GDS_PERF_SEL_SE3_GDS_REL_OP = 50 -GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51 -GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52 -GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53 -GDS_PERF_SEL_SE4_NORET = 54 -GDS_PERF_SEL_SE4_RET = 55 -GDS_PERF_SEL_SE4_ORD_CNT = 56 -GDS_PERF_SEL_SE4_2COMP_REQ = 57 -GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58 -GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59 -GDS_PERF_SEL_SE4_GDS_WR_OP = 60 -GDS_PERF_SEL_SE4_GDS_RD_OP = 61 -GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62 -GDS_PERF_SEL_SE4_GDS_REL_OP = 63 -GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64 -GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65 -GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66 -GDS_PERF_SEL_SE5_NORET = 67 -GDS_PERF_SEL_SE5_RET = 68 -GDS_PERF_SEL_SE5_ORD_CNT = 69 -GDS_PERF_SEL_SE5_2COMP_REQ = 70 -GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71 -GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72 -GDS_PERF_SEL_SE5_GDS_WR_OP = 73 -GDS_PERF_SEL_SE5_GDS_RD_OP = 74 -GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75 -GDS_PERF_SEL_SE5_GDS_REL_OP = 76 -GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77 -GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78 -GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79 -GDS_PERF_SEL_SE6_NORET = 80 -GDS_PERF_SEL_SE6_RET = 81 -GDS_PERF_SEL_SE6_ORD_CNT = 82 -GDS_PERF_SEL_SE6_2COMP_REQ = 83 -GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84 -GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85 -GDS_PERF_SEL_SE6_GDS_WR_OP = 86 -GDS_PERF_SEL_SE6_GDS_RD_OP = 87 -GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88 -GDS_PERF_SEL_SE6_GDS_REL_OP = 89 -GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90 -GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91 -GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92 -GDS_PERF_SEL_SE7_NORET = 93 -GDS_PERF_SEL_SE7_RET = 94 -GDS_PERF_SEL_SE7_ORD_CNT = 95 -GDS_PERF_SEL_SE7_2COMP_REQ = 96 -GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97 -GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98 -GDS_PERF_SEL_SE7_GDS_WR_OP = 99 -GDS_PERF_SEL_SE7_GDS_RD_OP = 100 -GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101 -GDS_PERF_SEL_SE7_GDS_REL_OP = 102 -GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103 -GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104 -GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105 -GDS_PERF_SEL_GWS_RELEASED = 106 -GDS_PERF_SEL_GWS_BYPASS = 107 -GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'BlendOp' -BlendOp__enumvalues = { - 0: 'BLEND_ZERO', - 1: 'BLEND_ONE', - 2: 'BLEND_SRC_COLOR', - 3: 'BLEND_ONE_MINUS_SRC_COLOR', - 4: 'BLEND_SRC_ALPHA', - 5: 'BLEND_ONE_MINUS_SRC_ALPHA', - 6: 'BLEND_DST_ALPHA', - 7: 'BLEND_ONE_MINUS_DST_ALPHA', - 8: 'BLEND_DST_COLOR', - 9: 'BLEND_ONE_MINUS_DST_COLOR', - 10: 'BLEND_SRC_ALPHA_SATURATE', - 11: 'BLEND_CONSTANT_COLOR', - 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', - 13: 'BLEND_SRC1_COLOR', - 14: 'BLEND_INV_SRC1_COLOR', - 15: 'BLEND_SRC1_ALPHA', - 16: 'BLEND_INV_SRC1_ALPHA', - 17: 'BLEND_CONSTANT_ALPHA', - 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', -} -BLEND_ZERO = 0 -BLEND_ONE = 1 -BLEND_SRC_COLOR = 2 -BLEND_ONE_MINUS_SRC_COLOR = 3 -BLEND_SRC_ALPHA = 4 -BLEND_ONE_MINUS_SRC_ALPHA = 5 -BLEND_DST_ALPHA = 6 -BLEND_ONE_MINUS_DST_ALPHA = 7 -BLEND_DST_COLOR = 8 -BLEND_ONE_MINUS_DST_COLOR = 9 -BLEND_SRC_ALPHA_SATURATE = 10 -BLEND_CONSTANT_COLOR = 11 -BLEND_ONE_MINUS_CONSTANT_COLOR = 12 -BLEND_SRC1_COLOR = 13 -BLEND_INV_SRC1_COLOR = 14 -BLEND_SRC1_ALPHA = 15 -BLEND_INV_SRC1_ALPHA = 16 -BLEND_CONSTANT_ALPHA = 17 -BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 -BlendOp = ctypes.c_uint32 # enum -GL__ZERO = BLEND_ZERO # macro -GL__ONE = BLEND_ONE # macro -GL__SRC_COLOR = BLEND_SRC_COLOR # macro -GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro -GL__DST_COLOR = BLEND_DST_COLOR # macro -GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro -GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro -GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro -GL__DST_ALPHA = BLEND_DST_ALPHA # macro -GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro -GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro -GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro -GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro -GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro -GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro - -# values for enumeration 'BlendOpt' -BlendOpt__enumvalues = { - 0: 'FORCE_OPT_AUTO', - 1: 'FORCE_OPT_DISABLE', - 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', - 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', - 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', -} -FORCE_OPT_AUTO = 0 -FORCE_OPT_DISABLE = 1 -FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 -FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 -FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 -FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 -FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 -FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 -BlendOpt = ctypes.c_uint32 # enum - -# values for enumeration 'CBMode' -CBMode__enumvalues = { - 0: 'CB_DISABLE', - 1: 'CB_NORMAL', - 2: 'CB_ELIMINATE_FAST_CLEAR', - 3: 'CB_DCC_DECOMPRESS', - 4: 'CB_RESERVED', -} -CB_DISABLE = 0 -CB_NORMAL = 1 -CB_ELIMINATE_FAST_CLEAR = 2 -CB_DCC_DECOMPRESS = 3 -CB_RESERVED = 4 -CBMode = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfClearFilterSel' -CBPerfClearFilterSel__enumvalues = { - 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', -} -CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 -CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 -CBPerfClearFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfOpFilterSel' -CBPerfOpFilterSel__enumvalues = { - 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', -} -CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 -CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 -CB_PERF_OP_FILTER_SEL_RESOLVE = 2 -CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 -CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 -CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 -CBPerfOpFilterSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBPerfSel' -CBPerfSel__enumvalues = { - 0: 'CB_PERF_SEL_NONE', - 1: 'CB_PERF_SEL_DRAWN_PIXEL', - 2: 'CB_PERF_SEL_DRAWN_QUAD', - 3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', - 4: 'CB_PERF_SEL_DRAWN_TILE', - 5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', - 6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD', - 7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', - 8: 'CB_PERF_SEL_FILTER_DRAWN_TILE', - 9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', - 10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', - 11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', - 12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', - 13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 15: 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', - 19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 21: 'CB_PERF_SEL_RESERVED_21', - 22: 'CB_PERF_SEL_RESERVED_22', - 23: 'CB_PERF_SEL_RESERVED_23', - 24: 'CB_PERF_SEL_RESERVED_24', - 25: 'CB_PERF_SEL_RESERVED_25', - 26: 'CB_PERF_SEL_RESERVED_26', - 27: 'CB_PERF_SEL_RESERVED_27', - 28: 'CB_PERF_SEL_RESERVED_28', - 29: 'CB_PERF_SEL_RESERVED_29', - 30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', - 31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', - 32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', - 33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', - 34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', - 35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', - 36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', - 37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', - 38: 'CB_PERF_SEL_RESERVED_38', - 39: 'CB_PERF_SEL_RESERVED_39', - 40: 'CB_PERF_SEL_RESERVED_40', - 41: 'CB_PERF_SEL_RESERVED_41', - 42: 'CB_PERF_SEL_RESERVED_42', - 43: 'CB_PERF_SEL_RESERVED_43', - 44: 'CB_PERF_SEL_RESERVED_44', - 45: 'CB_PERF_SEL_RESERVED_45', - 46: 'CB_PERF_SEL_RESERVED_46', - 47: 'CB_PERF_SEL_RESERVED_47', - 48: 'CB_PERF_SEL_RESERVED_48', - 49: 'CB_PERF_SEL_RESERVED_49', - 50: 'CB_PERF_SEL_STATIC_CLOCK_EN', - 51: 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 52: 'CB_PERF_SEL_BLEND_CLOCK_EN', - 53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 55: 'CB_PERF_SEL_GRBM_CLOCK_EN', - 56: 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 65: 'CB_PERF_SEL_RESERVED_65', - 66: 'CB_PERF_SEL_RESERVED_66', - 67: 'CB_PERF_SEL_RESERVED_67', - 68: 'CB_PERF_SEL_RESERVED_68', - 69: 'CB_PERF_SEL_RESERVED_69', - 70: 'CB_PERF_SEL_RESERVED_70', - 71: 'CB_PERF_SEL_RESERVED_71', - 72: 'CB_PERF_SEL_RESERVED_72', - 73: 'CB_PERF_SEL_RESERVED_73', - 74: 'CB_PERF_SEL_RESERVED_74', - 75: 'CB_PERF_SEL_RESERVED_75', - 76: 'CB_PERF_SEL_RESERVED_76', - 77: 'CB_PERF_SEL_RESERVED_77', - 78: 'CB_PERF_SEL_RESERVED_78', - 79: 'CB_PERF_SEL_RESERVED_79', - 80: 'CB_PERF_SEL_RESERVED_80', - 81: 'CB_PERF_SEL_RESERVED_81', - 82: 'CB_PERF_SEL_RESERVED_82', - 83: 'CB_PERF_SEL_RESERVED_83', - 84: 'CB_PERF_SEL_RESERVED_84', - 85: 'CB_PERF_SEL_RESERVED_85', - 86: 'CB_PERF_SEL_RESERVED_86', - 87: 'CB_PERF_SEL_RESERVED_87', - 88: 'CB_PERF_SEL_RESERVED_88', - 89: 'CB_PERF_SEL_RESERVED_89', - 90: 'CB_PERF_SEL_RESERVED_90', - 91: 'CB_PERF_SEL_RESERVED_91', - 92: 'CB_PERF_SEL_RESERVED_92', - 93: 'CB_PERF_SEL_RESERVED_93', - 94: 'CB_PERF_SEL_RESERVED_94', - 95: 'CB_PERF_SEL_RESERVED_95', - 96: 'CB_PERF_SEL_RESERVED_96', - 97: 'CB_PERF_SEL_RESERVED_97', - 98: 'CB_PERF_SEL_RESERVED_98', - 99: 'CB_PERF_SEL_RESERVED_99', - 100: 'CB_PERF_SEL_CC_TAG_HIT', - 101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', - 103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 111: 'CB_PERF_SEL_CC_CACHE_STALL', - 112: 'CB_PERF_SEL_CC_CACHE_FLUSH', - 113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 118: 'CB_PERF_SEL_RESERVED_118', - 119: 'CB_PERF_SEL_RESERVED_119', - 120: 'CB_PERF_SEL_RESERVED_120', - 121: 'CB_PERF_SEL_RESERVED_121', - 122: 'CB_PERF_SEL_RESERVED_122', - 123: 'CB_PERF_SEL_RESERVED_123', - 124: 'CB_PERF_SEL_RESERVED_124', - 125: 'CB_PERF_SEL_RESERVED_125', - 126: 'CB_PERF_SEL_RESERVED_126', - 127: 'CB_PERF_SEL_RESERVED_127', - 128: 'CB_PERF_SEL_RESERVED_128', - 129: 'CB_PERF_SEL_RESERVED_129', - 130: 'CB_PERF_SEL_RESERVED_130', - 131: 'CB_PERF_SEL_RESERVED_131', - 132: 'CB_PERF_SEL_RESERVED_132', - 133: 'CB_PERF_SEL_RESERVED_133', - 134: 'CB_PERF_SEL_RESERVED_134', - 135: 'CB_PERF_SEL_RESERVED_135', - 136: 'CB_PERF_SEL_RESERVED_136', - 137: 'CB_PERF_SEL_RESERVED_137', - 138: 'CB_PERF_SEL_RESERVED_138', - 139: 'CB_PERF_SEL_RESERVED_139', - 140: 'CB_PERF_SEL_RESERVED_140', - 141: 'CB_PERF_SEL_RESERVED_141', - 142: 'CB_PERF_SEL_RESERVED_142', - 143: 'CB_PERF_SEL_RESERVED_143', - 144: 'CB_PERF_SEL_RESERVED_144', - 145: 'CB_PERF_SEL_RESERVED_145', - 146: 'CB_PERF_SEL_RESERVED_146', - 147: 'CB_PERF_SEL_RESERVED_147', - 148: 'CB_PERF_SEL_RESERVED_148', - 149: 'CB_PERF_SEL_RESERVED_149', - 150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', - 151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', - 152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', - 153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', - 154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', - 158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', - 159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', - 160: 'CB_PERF_SEL_DCC_CACHE_STALL', - 161: 'CB_PERF_SEL_DCC_CACHE_FLUSH', - 162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', - 163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', - 165: 'CB_PERF_SEL_RESERVED_165', - 166: 'CB_PERF_SEL_RESERVED_166', - 167: 'CB_PERF_SEL_RESERVED_167', - 168: 'CB_PERF_SEL_RESERVED_168', - 169: 'CB_PERF_SEL_RESERVED_169', - 170: 'CB_PERF_SEL_RESERVED_170', - 171: 'CB_PERF_SEL_RESERVED_171', - 172: 'CB_PERF_SEL_RESERVED_172', - 173: 'CB_PERF_SEL_RESERVED_173', - 174: 'CB_PERF_SEL_RESERVED_174', - 175: 'CB_PERF_SEL_RESERVED_175', - 176: 'CB_PERF_SEL_RESERVED_176', - 177: 'CB_PERF_SEL_RESERVED_177', - 178: 'CB_PERF_SEL_RESERVED_178', - 179: 'CB_PERF_SEL_RESERVED_179', - 180: 'CB_PERF_SEL_RESERVED_180', - 181: 'CB_PERF_SEL_RESERVED_181', - 182: 'CB_PERF_SEL_RESERVED_182', - 183: 'CB_PERF_SEL_RESERVED_183', - 184: 'CB_PERF_SEL_RESERVED_184', - 185: 'CB_PERF_SEL_RESERVED_185', - 186: 'CB_PERF_SEL_RESERVED_186', - 187: 'CB_PERF_SEL_RESERVED_187', - 188: 'CB_PERF_SEL_RESERVED_188', - 189: 'CB_PERF_SEL_RESERVED_189', - 190: 'CB_PERF_SEL_RESERVED_190', - 191: 'CB_PERF_SEL_RESERVED_191', - 192: 'CB_PERF_SEL_RESERVED_192', - 193: 'CB_PERF_SEL_RESERVED_193', - 194: 'CB_PERF_SEL_RESERVED_194', - 195: 'CB_PERF_SEL_RESERVED_195', - 196: 'CB_PERF_SEL_RESERVED_196', - 197: 'CB_PERF_SEL_RESERVED_197', - 198: 'CB_PERF_SEL_RESERVED_198', - 199: 'CB_PERF_SEL_RESERVED_199', - 200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 205: 'CB_PERF_SEL_RESERVED_205', - 206: 'CB_PERF_SEL_RESERVED_206', - 207: 'CB_PERF_SEL_RESERVED_207', - 208: 'CB_PERF_SEL_RESERVED_208', - 209: 'CB_PERF_SEL_RESERVED_209', - 210: 'CB_PERF_SEL_RESERVED_210', - 211: 'CB_PERF_SEL_RESERVED_211', - 212: 'CB_PERF_SEL_RESERVED_212', - 213: 'CB_PERF_SEL_RESERVED_213', - 214: 'CB_PERF_SEL_RESERVED_214', - 215: 'CB_PERF_SEL_RESERVED_215', - 216: 'CB_PERF_SEL_RESERVED_216', - 217: 'CB_PERF_SEL_RESERVED_217', - 218: 'CB_PERF_SEL_RESERVED_218', - 219: 'CB_PERF_SEL_RESERVED_219', - 220: 'CB_PERF_SEL_RESERVED_220', - 221: 'CB_PERF_SEL_RESERVED_221', - 222: 'CB_PERF_SEL_RESERVED_222', - 223: 'CB_PERF_SEL_RESERVED_223', - 224: 'CB_PERF_SEL_RESERVED_224', - 225: 'CB_PERF_SEL_RESERVED_225', - 226: 'CB_PERF_SEL_RESERVED_226', - 227: 'CB_PERF_SEL_RESERVED_227', - 228: 'CB_PERF_SEL_RESERVED_228', - 229: 'CB_PERF_SEL_RESERVED_229', - 230: 'CB_PERF_SEL_RESERVED_230', - 231: 'CB_PERF_SEL_RESERVED_231', - 232: 'CB_PERF_SEL_RESERVED_232', - 233: 'CB_PERF_SEL_RESERVED_233', - 234: 'CB_PERF_SEL_RESERVED_234', - 235: 'CB_PERF_SEL_RESERVED_235', - 236: 'CB_PERF_SEL_RESERVED_236', - 237: 'CB_PERF_SEL_RESERVED_237', - 238: 'CB_PERF_SEL_RESERVED_238', - 239: 'CB_PERF_SEL_RESERVED_239', - 240: 'CB_PERF_SEL_RESERVED_240', - 241: 'CB_PERF_SEL_RESERVED_241', - 242: 'CB_PERF_SEL_RESERVED_242', - 243: 'CB_PERF_SEL_RESERVED_243', - 244: 'CB_PERF_SEL_RESERVED_244', - 245: 'CB_PERF_SEL_RESERVED_245', - 246: 'CB_PERF_SEL_RESERVED_246', - 247: 'CB_PERF_SEL_RESERVED_247', - 248: 'CB_PERF_SEL_RESERVED_248', - 249: 'CB_PERF_SEL_RESERVED_249', - 250: 'CB_PERF_SEL_EVENT', - 251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 258: 'CB_PERF_SEL_CC_SURFACE_SYNC', - 259: 'CB_PERF_SEL_RESERVED_259', - 260: 'CB_PERF_SEL_RESERVED_260', - 261: 'CB_PERF_SEL_RESERVED_261', - 262: 'CB_PERF_SEL_RESERVED_262', - 263: 'CB_PERF_SEL_RESERVED_263', - 264: 'CB_PERF_SEL_RESERVED_264', - 265: 'CB_PERF_SEL_RESERVED_265', - 266: 'CB_PERF_SEL_RESERVED_266', - 267: 'CB_PERF_SEL_RESERVED_267', - 268: 'CB_PERF_SEL_RESERVED_268', - 269: 'CB_PERF_SEL_RESERVED_269', - 270: 'CB_PERF_SEL_RESERVED_270', - 271: 'CB_PERF_SEL_RESERVED_271', - 272: 'CB_PERF_SEL_RESERVED_272', - 273: 'CB_PERF_SEL_RESERVED_273', - 274: 'CB_PERF_SEL_RESERVED_274', - 275: 'CB_PERF_SEL_RESERVED_275', - 276: 'CB_PERF_SEL_RESERVED_276', - 277: 'CB_PERF_SEL_RESERVED_277', - 278: 'CB_PERF_SEL_RESERVED_278', - 279: 'CB_PERF_SEL_RESERVED_279', - 280: 'CB_PERF_SEL_RESERVED_280', - 281: 'CB_PERF_SEL_RESERVED_281', - 282: 'CB_PERF_SEL_RESERVED_282', - 283: 'CB_PERF_SEL_RESERVED_283', - 284: 'CB_PERF_SEL_RESERVED_284', - 285: 'CB_PERF_SEL_RESERVED_285', - 286: 'CB_PERF_SEL_RESERVED_286', - 287: 'CB_PERF_SEL_RESERVED_287', - 288: 'CB_PERF_SEL_RESERVED_288', - 289: 'CB_PERF_SEL_RESERVED_289', - 290: 'CB_PERF_SEL_RESERVED_290', - 291: 'CB_PERF_SEL_RESERVED_291', - 292: 'CB_PERF_SEL_RESERVED_292', - 293: 'CB_PERF_SEL_RESERVED_293', - 294: 'CB_PERF_SEL_RESERVED_294', - 295: 'CB_PERF_SEL_RESERVED_295', - 296: 'CB_PERF_SEL_RESERVED_296', - 297: 'CB_PERF_SEL_RESERVED_297', - 298: 'CB_PERF_SEL_RESERVED_298', - 299: 'CB_PERF_SEL_RESERVED_299', - 300: 'CB_PERF_SEL_NACK_CC_READ', - 301: 'CB_PERF_SEL_NACK_CC_WRITE', - 302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 303: 'CB_PERF_SEL_RESERVED_303', - 304: 'CB_PERF_SEL_RESERVED_304', - 305: 'CB_PERF_SEL_RESERVED_305', - 306: 'CB_PERF_SEL_RESERVED_306', - 307: 'CB_PERF_SEL_RESERVED_307', - 308: 'CB_PERF_SEL_RESERVED_308', - 309: 'CB_PERF_SEL_RESERVED_309', - 310: 'CB_PERF_SEL_RESERVED_310', - 311: 'CB_PERF_SEL_RESERVED_311', - 312: 'CB_PERF_SEL_RESERVED_312', - 313: 'CB_PERF_SEL_RESERVED_313', - 314: 'CB_PERF_SEL_RESERVED_314', - 315: 'CB_PERF_SEL_RESERVED_315', - 316: 'CB_PERF_SEL_RESERVED_316', - 317: 'CB_PERF_SEL_RESERVED_317', - 318: 'CB_PERF_SEL_RESERVED_318', - 319: 'CB_PERF_SEL_RESERVED_319', - 320: 'CB_PERF_SEL_RESERVED_320', - 321: 'CB_PERF_SEL_RESERVED_321', - 322: 'CB_PERF_SEL_RESERVED_322', - 323: 'CB_PERF_SEL_RESERVED_323', - 324: 'CB_PERF_SEL_RESERVED_324', - 325: 'CB_PERF_SEL_RESERVED_325', - 326: 'CB_PERF_SEL_RESERVED_326', - 327: 'CB_PERF_SEL_RESERVED_327', - 328: 'CB_PERF_SEL_RESERVED_328', - 329: 'CB_PERF_SEL_RESERVED_329', - 330: 'CB_PERF_SEL_RESERVED_330', - 331: 'CB_PERF_SEL_RESERVED_331', - 332: 'CB_PERF_SEL_RESERVED_332', - 333: 'CB_PERF_SEL_RESERVED_333', - 334: 'CB_PERF_SEL_RESERVED_334', - 335: 'CB_PERF_SEL_RESERVED_335', - 336: 'CB_PERF_SEL_RESERVED_336', - 337: 'CB_PERF_SEL_RESERVED_337', - 338: 'CB_PERF_SEL_RESERVED_338', - 339: 'CB_PERF_SEL_RESERVED_339', - 340: 'CB_PERF_SEL_RESERVED_340', - 341: 'CB_PERF_SEL_RESERVED_341', - 342: 'CB_PERF_SEL_RESERVED_342', - 343: 'CB_PERF_SEL_RESERVED_343', - 344: 'CB_PERF_SEL_RESERVED_344', - 345: 'CB_PERF_SEL_RESERVED_345', - 346: 'CB_PERF_SEL_RESERVED_346', - 347: 'CB_PERF_SEL_RESERVED_347', - 348: 'CB_PERF_SEL_RESERVED_348', - 349: 'CB_PERF_SEL_RESERVED_349', - 350: 'CB_PERF_SEL_RESERVED_350', - 351: 'CB_PERF_SEL_RESERVED_351', - 352: 'CB_PERF_SEL_RESERVED_352', - 353: 'CB_PERF_SEL_RESERVED_353', - 354: 'CB_PERF_SEL_RESERVED_354', - 355: 'CB_PERF_SEL_RESERVED_355', - 356: 'CB_PERF_SEL_RESERVED_356', - 357: 'CB_PERF_SEL_RESERVED_357', - 358: 'CB_PERF_SEL_RESERVED_358', - 359: 'CB_PERF_SEL_RESERVED_359', - 360: 'CB_PERF_SEL_RESERVED_360', - 361: 'CB_PERF_SEL_RESERVED_361', - 362: 'CB_PERF_SEL_RESERVED_362', - 363: 'CB_PERF_SEL_RESERVED_363', - 364: 'CB_PERF_SEL_RESERVED_364', - 365: 'CB_PERF_SEL_RESERVED_365', - 366: 'CB_PERF_SEL_RESERVED_366', - 367: 'CB_PERF_SEL_RESERVED_367', - 368: 'CB_PERF_SEL_RESERVED_368', - 369: 'CB_PERF_SEL_RESERVED_369', - 370: 'CB_PERF_SEL_RESERVED_370', - 371: 'CB_PERF_SEL_RESERVED_371', - 372: 'CB_PERF_SEL_RESERVED_372', - 373: 'CB_PERF_SEL_RESERVED_373', - 374: 'CB_PERF_SEL_RESERVED_374', - 375: 'CB_PERF_SEL_RESERVED_375', - 376: 'CB_PERF_SEL_RESERVED_376', - 377: 'CB_PERF_SEL_RESERVED_377', - 378: 'CB_PERF_SEL_RESERVED_378', - 379: 'CB_PERF_SEL_RESERVED_379', - 380: 'CB_PERF_SEL_RESERVED_380', - 381: 'CB_PERF_SEL_RESERVED_381', - 382: 'CB_PERF_SEL_RESERVED_382', - 383: 'CB_PERF_SEL_RESERVED_383', - 384: 'CB_PERF_SEL_RESERVED_384', - 385: 'CB_PERF_SEL_RESERVED_385', - 386: 'CB_PERF_SEL_RESERVED_386', - 387: 'CB_PERF_SEL_RESERVED_387', - 388: 'CB_PERF_SEL_RESERVED_388', - 389: 'CB_PERF_SEL_RESERVED_389', - 390: 'CB_PERF_SEL_RESERVED_390', - 391: 'CB_PERF_SEL_RESERVED_391', - 392: 'CB_PERF_SEL_RESERVED_392', - 393: 'CB_PERF_SEL_RESERVED_393', - 394: 'CB_PERF_SEL_RESERVED_394', - 395: 'CB_PERF_SEL_RESERVED_395', - 396: 'CB_PERF_SEL_RESERVED_396', - 397: 'CB_PERF_SEL_RESERVED_397', - 398: 'CB_PERF_SEL_RESERVED_398', - 399: 'CB_PERF_SEL_RESERVED_399', - 400: 'CB_PERF_SEL_RESERVED_400', - 401: 'CB_PERF_SEL_RESERVED_401', - 402: 'CB_PERF_SEL_RESERVED_402', - 403: 'CB_PERF_SEL_RESERVED_403', - 404: 'CB_PERF_SEL_RESERVED_404', - 405: 'CB_PERF_SEL_RESERVED_405', - 406: 'CB_PERF_SEL_RESERVED_406', - 407: 'CB_PERF_SEL_RESERVED_407', - 408: 'CB_PERF_SEL_RESERVED_408', - 409: 'CB_PERF_SEL_RESERVED_409', - 410: 'CB_PERF_SEL_RESERVED_410', - 411: 'CB_PERF_SEL_RESERVED_411', - 412: 'CB_PERF_SEL_RESERVED_412', - 413: 'CB_PERF_SEL_RESERVED_413', - 414: 'CB_PERF_SEL_RESERVED_414', - 415: 'CB_PERF_SEL_RESERVED_415', - 416: 'CB_PERF_SEL_RESERVED_416', - 417: 'CB_PERF_SEL_RESERVED_417', - 418: 'CB_PERF_SEL_RESERVED_418', - 419: 'CB_PERF_SEL_RESERVED_419', - 420: 'CB_PERF_SEL_RESERVED_420', - 421: 'CB_PERF_SEL_RESERVED_421', - 422: 'CB_PERF_SEL_RESERVED_422', - 423: 'CB_PERF_SEL_RESERVED_423', - 424: 'CB_PERF_SEL_RESERVED_424', - 425: 'CB_PERF_SEL_RESERVED_425', - 426: 'CB_PERF_SEL_RESERVED_426', - 427: 'CB_PERF_SEL_RESERVED_427', - 428: 'CB_PERF_SEL_RESERVED_428', - 429: 'CB_PERF_SEL_RESERVED_429', - 430: 'CB_PERF_SEL_RESERVED_430', - 431: 'CB_PERF_SEL_RESERVED_431', - 432: 'CB_PERF_SEL_RESERVED_432', - 433: 'CB_PERF_SEL_RESERVED_433', - 434: 'CB_PERF_SEL_RESERVED_434', - 435: 'CB_PERF_SEL_RESERVED_435', - 436: 'CB_PERF_SEL_RESERVED_436', - 437: 'CB_PERF_SEL_RESERVED_437', - 438: 'CB_PERF_SEL_RESERVED_438', - 439: 'CB_PERF_SEL_RESERVED_439', - 440: 'CB_PERF_SEL_RESERVED_440', - 441: 'CB_PERF_SEL_RESERVED_441', - 442: 'CB_PERF_SEL_RESERVED_442', - 443: 'CB_PERF_SEL_RESERVED_443', - 444: 'CB_PERF_SEL_RESERVED_444', - 445: 'CB_PERF_SEL_RESERVED_445', - 446: 'CB_PERF_SEL_RESERVED_446', - 447: 'CB_PERF_SEL_RESERVED_447', - 448: 'CB_PERF_SEL_RESERVED_448', - 449: 'CB_PERF_SEL_RESERVED_449', - 450: 'CB_PERF_SEL_RESERVED_450', - 451: 'CB_PERF_SEL_RESERVED_451', - 452: 'CB_PERF_SEL_RESERVED_452', - 453: 'CB_PERF_SEL_RESERVED_453', - 454: 'CB_PERF_SEL_RESERVED_454', - 455: 'CB_PERF_SEL_RESERVED_455', - 456: 'CB_PERF_SEL_RESERVED_456', - 457: 'CB_PERF_SEL_RESERVED_457', - 458: 'CB_PERF_SEL_RESERVED_458', - 459: 'CB_PERF_SEL_RESERVED_459', - 460: 'CB_PERF_SEL_RESERVED_460', - 461: 'CB_PERF_SEL_RESERVED_461', - 462: 'CB_PERF_SEL_RESERVED_462', - 463: 'CB_PERF_SEL_RESERVED_463', - 464: 'CB_PERF_SEL_RESERVED_464', - 465: 'CB_PERF_SEL_RESERVED_465', -} -CB_PERF_SEL_NONE = 0 -CB_PERF_SEL_DRAWN_PIXEL = 1 -CB_PERF_SEL_DRAWN_QUAD = 2 -CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3 -CB_PERF_SEL_DRAWN_TILE = 4 -CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5 -CB_PERF_SEL_FILTER_DRAWN_QUAD = 6 -CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7 -CB_PERF_SEL_FILTER_DRAWN_TILE = 8 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9 -CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10 -CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11 -CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12 -CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13 -CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14 -CB_PERF_SEL_CC_MC_READ_REQUEST = 15 -CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17 -CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19 -CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20 -CB_PERF_SEL_RESERVED_21 = 21 -CB_PERF_SEL_RESERVED_22 = 22 -CB_PERF_SEL_RESERVED_23 = 23 -CB_PERF_SEL_RESERVED_24 = 24 -CB_PERF_SEL_RESERVED_25 = 25 -CB_PERF_SEL_RESERVED_26 = 26 -CB_PERF_SEL_RESERVED_27 = 27 -CB_PERF_SEL_RESERVED_28 = 28 -CB_PERF_SEL_RESERVED_29 = 29 -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30 -CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31 -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32 -CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33 -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34 -CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35 -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36 -CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37 -CB_PERF_SEL_RESERVED_38 = 38 -CB_PERF_SEL_RESERVED_39 = 39 -CB_PERF_SEL_RESERVED_40 = 40 -CB_PERF_SEL_RESERVED_41 = 41 -CB_PERF_SEL_RESERVED_42 = 42 -CB_PERF_SEL_RESERVED_43 = 43 -CB_PERF_SEL_RESERVED_44 = 44 -CB_PERF_SEL_RESERVED_45 = 45 -CB_PERF_SEL_RESERVED_46 = 46 -CB_PERF_SEL_RESERVED_47 = 47 -CB_PERF_SEL_RESERVED_48 = 48 -CB_PERF_SEL_RESERVED_49 = 49 -CB_PERF_SEL_STATIC_CLOCK_EN = 50 -CB_PERF_SEL_PERFMON_CLOCK_EN = 51 -CB_PERF_SEL_BLEND_CLOCK_EN = 52 -CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53 -CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54 -CB_PERF_SEL_GRBM_CLOCK_EN = 55 -CB_PERF_SEL_MEMARB_CLOCK_EN = 56 -CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57 -CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58 -CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59 -CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60 -CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61 -CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62 -CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63 -CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64 -CB_PERF_SEL_RESERVED_65 = 65 -CB_PERF_SEL_RESERVED_66 = 66 -CB_PERF_SEL_RESERVED_67 = 67 -CB_PERF_SEL_RESERVED_68 = 68 -CB_PERF_SEL_RESERVED_69 = 69 -CB_PERF_SEL_RESERVED_70 = 70 -CB_PERF_SEL_RESERVED_71 = 71 -CB_PERF_SEL_RESERVED_72 = 72 -CB_PERF_SEL_RESERVED_73 = 73 -CB_PERF_SEL_RESERVED_74 = 74 -CB_PERF_SEL_RESERVED_75 = 75 -CB_PERF_SEL_RESERVED_76 = 76 -CB_PERF_SEL_RESERVED_77 = 77 -CB_PERF_SEL_RESERVED_78 = 78 -CB_PERF_SEL_RESERVED_79 = 79 -CB_PERF_SEL_RESERVED_80 = 80 -CB_PERF_SEL_RESERVED_81 = 81 -CB_PERF_SEL_RESERVED_82 = 82 -CB_PERF_SEL_RESERVED_83 = 83 -CB_PERF_SEL_RESERVED_84 = 84 -CB_PERF_SEL_RESERVED_85 = 85 -CB_PERF_SEL_RESERVED_86 = 86 -CB_PERF_SEL_RESERVED_87 = 87 -CB_PERF_SEL_RESERVED_88 = 88 -CB_PERF_SEL_RESERVED_89 = 89 -CB_PERF_SEL_RESERVED_90 = 90 -CB_PERF_SEL_RESERVED_91 = 91 -CB_PERF_SEL_RESERVED_92 = 92 -CB_PERF_SEL_RESERVED_93 = 93 -CB_PERF_SEL_RESERVED_94 = 94 -CB_PERF_SEL_RESERVED_95 = 95 -CB_PERF_SEL_RESERVED_96 = 96 -CB_PERF_SEL_RESERVED_97 = 97 -CB_PERF_SEL_RESERVED_98 = 98 -CB_PERF_SEL_RESERVED_99 = 99 -CB_PERF_SEL_CC_TAG_HIT = 100 -CB_PERF_SEL_CC_CACHE_TAG_MISS = 101 -CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102 -CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103 -CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104 -CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105 -CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106 -CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107 -CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108 -CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109 -CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110 -CB_PERF_SEL_CC_CACHE_STALL = 111 -CB_PERF_SEL_CC_CACHE_FLUSH = 112 -CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113 -CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114 -CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115 -CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116 -CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117 -CB_PERF_SEL_RESERVED_118 = 118 -CB_PERF_SEL_RESERVED_119 = 119 -CB_PERF_SEL_RESERVED_120 = 120 -CB_PERF_SEL_RESERVED_121 = 121 -CB_PERF_SEL_RESERVED_122 = 122 -CB_PERF_SEL_RESERVED_123 = 123 -CB_PERF_SEL_RESERVED_124 = 124 -CB_PERF_SEL_RESERVED_125 = 125 -CB_PERF_SEL_RESERVED_126 = 126 -CB_PERF_SEL_RESERVED_127 = 127 -CB_PERF_SEL_RESERVED_128 = 128 -CB_PERF_SEL_RESERVED_129 = 129 -CB_PERF_SEL_RESERVED_130 = 130 -CB_PERF_SEL_RESERVED_131 = 131 -CB_PERF_SEL_RESERVED_132 = 132 -CB_PERF_SEL_RESERVED_133 = 133 -CB_PERF_SEL_RESERVED_134 = 134 -CB_PERF_SEL_RESERVED_135 = 135 -CB_PERF_SEL_RESERVED_136 = 136 -CB_PERF_SEL_RESERVED_137 = 137 -CB_PERF_SEL_RESERVED_138 = 138 -CB_PERF_SEL_RESERVED_139 = 139 -CB_PERF_SEL_RESERVED_140 = 140 -CB_PERF_SEL_RESERVED_141 = 141 -CB_PERF_SEL_RESERVED_142 = 142 -CB_PERF_SEL_RESERVED_143 = 143 -CB_PERF_SEL_RESERVED_144 = 144 -CB_PERF_SEL_RESERVED_145 = 145 -CB_PERF_SEL_RESERVED_146 = 146 -CB_PERF_SEL_RESERVED_147 = 147 -CB_PERF_SEL_RESERVED_148 = 148 -CB_PERF_SEL_RESERVED_149 = 149 -CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150 -CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151 -CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152 -CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153 -CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154 -CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155 -CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156 -CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157 -CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158 -CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159 -CB_PERF_SEL_DCC_CACHE_STALL = 160 -CB_PERF_SEL_DCC_CACHE_FLUSH = 161 -CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162 -CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163 -CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164 -CB_PERF_SEL_RESERVED_165 = 165 -CB_PERF_SEL_RESERVED_166 = 166 -CB_PERF_SEL_RESERVED_167 = 167 -CB_PERF_SEL_RESERVED_168 = 168 -CB_PERF_SEL_RESERVED_169 = 169 -CB_PERF_SEL_RESERVED_170 = 170 -CB_PERF_SEL_RESERVED_171 = 171 -CB_PERF_SEL_RESERVED_172 = 172 -CB_PERF_SEL_RESERVED_173 = 173 -CB_PERF_SEL_RESERVED_174 = 174 -CB_PERF_SEL_RESERVED_175 = 175 -CB_PERF_SEL_RESERVED_176 = 176 -CB_PERF_SEL_RESERVED_177 = 177 -CB_PERF_SEL_RESERVED_178 = 178 -CB_PERF_SEL_RESERVED_179 = 179 -CB_PERF_SEL_RESERVED_180 = 180 -CB_PERF_SEL_RESERVED_181 = 181 -CB_PERF_SEL_RESERVED_182 = 182 -CB_PERF_SEL_RESERVED_183 = 183 -CB_PERF_SEL_RESERVED_184 = 184 -CB_PERF_SEL_RESERVED_185 = 185 -CB_PERF_SEL_RESERVED_186 = 186 -CB_PERF_SEL_RESERVED_187 = 187 -CB_PERF_SEL_RESERVED_188 = 188 -CB_PERF_SEL_RESERVED_189 = 189 -CB_PERF_SEL_RESERVED_190 = 190 -CB_PERF_SEL_RESERVED_191 = 191 -CB_PERF_SEL_RESERVED_192 = 192 -CB_PERF_SEL_RESERVED_193 = 193 -CB_PERF_SEL_RESERVED_194 = 194 -CB_PERF_SEL_RESERVED_195 = 195 -CB_PERF_SEL_RESERVED_196 = 196 -CB_PERF_SEL_RESERVED_197 = 197 -CB_PERF_SEL_RESERVED_198 = 198 -CB_PERF_SEL_RESERVED_199 = 199 -CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200 -CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201 -CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202 -CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203 -CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204 -CB_PERF_SEL_RESERVED_205 = 205 -CB_PERF_SEL_RESERVED_206 = 206 -CB_PERF_SEL_RESERVED_207 = 207 -CB_PERF_SEL_RESERVED_208 = 208 -CB_PERF_SEL_RESERVED_209 = 209 -CB_PERF_SEL_RESERVED_210 = 210 -CB_PERF_SEL_RESERVED_211 = 211 -CB_PERF_SEL_RESERVED_212 = 212 -CB_PERF_SEL_RESERVED_213 = 213 -CB_PERF_SEL_RESERVED_214 = 214 -CB_PERF_SEL_RESERVED_215 = 215 -CB_PERF_SEL_RESERVED_216 = 216 -CB_PERF_SEL_RESERVED_217 = 217 -CB_PERF_SEL_RESERVED_218 = 218 -CB_PERF_SEL_RESERVED_219 = 219 -CB_PERF_SEL_RESERVED_220 = 220 -CB_PERF_SEL_RESERVED_221 = 221 -CB_PERF_SEL_RESERVED_222 = 222 -CB_PERF_SEL_RESERVED_223 = 223 -CB_PERF_SEL_RESERVED_224 = 224 -CB_PERF_SEL_RESERVED_225 = 225 -CB_PERF_SEL_RESERVED_226 = 226 -CB_PERF_SEL_RESERVED_227 = 227 -CB_PERF_SEL_RESERVED_228 = 228 -CB_PERF_SEL_RESERVED_229 = 229 -CB_PERF_SEL_RESERVED_230 = 230 -CB_PERF_SEL_RESERVED_231 = 231 -CB_PERF_SEL_RESERVED_232 = 232 -CB_PERF_SEL_RESERVED_233 = 233 -CB_PERF_SEL_RESERVED_234 = 234 -CB_PERF_SEL_RESERVED_235 = 235 -CB_PERF_SEL_RESERVED_236 = 236 -CB_PERF_SEL_RESERVED_237 = 237 -CB_PERF_SEL_RESERVED_238 = 238 -CB_PERF_SEL_RESERVED_239 = 239 -CB_PERF_SEL_RESERVED_240 = 240 -CB_PERF_SEL_RESERVED_241 = 241 -CB_PERF_SEL_RESERVED_242 = 242 -CB_PERF_SEL_RESERVED_243 = 243 -CB_PERF_SEL_RESERVED_244 = 244 -CB_PERF_SEL_RESERVED_245 = 245 -CB_PERF_SEL_RESERVED_246 = 246 -CB_PERF_SEL_RESERVED_247 = 247 -CB_PERF_SEL_RESERVED_248 = 248 -CB_PERF_SEL_RESERVED_249 = 249 -CB_PERF_SEL_EVENT = 250 -CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251 -CB_PERF_SEL_EVENT_CONTEXT_DONE = 252 -CB_PERF_SEL_EVENT_CACHE_FLUSH = 253 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254 -CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256 -CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257 -CB_PERF_SEL_CC_SURFACE_SYNC = 258 -CB_PERF_SEL_RESERVED_259 = 259 -CB_PERF_SEL_RESERVED_260 = 260 -CB_PERF_SEL_RESERVED_261 = 261 -CB_PERF_SEL_RESERVED_262 = 262 -CB_PERF_SEL_RESERVED_263 = 263 -CB_PERF_SEL_RESERVED_264 = 264 -CB_PERF_SEL_RESERVED_265 = 265 -CB_PERF_SEL_RESERVED_266 = 266 -CB_PERF_SEL_RESERVED_267 = 267 -CB_PERF_SEL_RESERVED_268 = 268 -CB_PERF_SEL_RESERVED_269 = 269 -CB_PERF_SEL_RESERVED_270 = 270 -CB_PERF_SEL_RESERVED_271 = 271 -CB_PERF_SEL_RESERVED_272 = 272 -CB_PERF_SEL_RESERVED_273 = 273 -CB_PERF_SEL_RESERVED_274 = 274 -CB_PERF_SEL_RESERVED_275 = 275 -CB_PERF_SEL_RESERVED_276 = 276 -CB_PERF_SEL_RESERVED_277 = 277 -CB_PERF_SEL_RESERVED_278 = 278 -CB_PERF_SEL_RESERVED_279 = 279 -CB_PERF_SEL_RESERVED_280 = 280 -CB_PERF_SEL_RESERVED_281 = 281 -CB_PERF_SEL_RESERVED_282 = 282 -CB_PERF_SEL_RESERVED_283 = 283 -CB_PERF_SEL_RESERVED_284 = 284 -CB_PERF_SEL_RESERVED_285 = 285 -CB_PERF_SEL_RESERVED_286 = 286 -CB_PERF_SEL_RESERVED_287 = 287 -CB_PERF_SEL_RESERVED_288 = 288 -CB_PERF_SEL_RESERVED_289 = 289 -CB_PERF_SEL_RESERVED_290 = 290 -CB_PERF_SEL_RESERVED_291 = 291 -CB_PERF_SEL_RESERVED_292 = 292 -CB_PERF_SEL_RESERVED_293 = 293 -CB_PERF_SEL_RESERVED_294 = 294 -CB_PERF_SEL_RESERVED_295 = 295 -CB_PERF_SEL_RESERVED_296 = 296 -CB_PERF_SEL_RESERVED_297 = 297 -CB_PERF_SEL_RESERVED_298 = 298 -CB_PERF_SEL_RESERVED_299 = 299 -CB_PERF_SEL_NACK_CC_READ = 300 -CB_PERF_SEL_NACK_CC_WRITE = 301 -CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302 -CB_PERF_SEL_RESERVED_303 = 303 -CB_PERF_SEL_RESERVED_304 = 304 -CB_PERF_SEL_RESERVED_305 = 305 -CB_PERF_SEL_RESERVED_306 = 306 -CB_PERF_SEL_RESERVED_307 = 307 -CB_PERF_SEL_RESERVED_308 = 308 -CB_PERF_SEL_RESERVED_309 = 309 -CB_PERF_SEL_RESERVED_310 = 310 -CB_PERF_SEL_RESERVED_311 = 311 -CB_PERF_SEL_RESERVED_312 = 312 -CB_PERF_SEL_RESERVED_313 = 313 -CB_PERF_SEL_RESERVED_314 = 314 -CB_PERF_SEL_RESERVED_315 = 315 -CB_PERF_SEL_RESERVED_316 = 316 -CB_PERF_SEL_RESERVED_317 = 317 -CB_PERF_SEL_RESERVED_318 = 318 -CB_PERF_SEL_RESERVED_319 = 319 -CB_PERF_SEL_RESERVED_320 = 320 -CB_PERF_SEL_RESERVED_321 = 321 -CB_PERF_SEL_RESERVED_322 = 322 -CB_PERF_SEL_RESERVED_323 = 323 -CB_PERF_SEL_RESERVED_324 = 324 -CB_PERF_SEL_RESERVED_325 = 325 -CB_PERF_SEL_RESERVED_326 = 326 -CB_PERF_SEL_RESERVED_327 = 327 -CB_PERF_SEL_RESERVED_328 = 328 -CB_PERF_SEL_RESERVED_329 = 329 -CB_PERF_SEL_RESERVED_330 = 330 -CB_PERF_SEL_RESERVED_331 = 331 -CB_PERF_SEL_RESERVED_332 = 332 -CB_PERF_SEL_RESERVED_333 = 333 -CB_PERF_SEL_RESERVED_334 = 334 -CB_PERF_SEL_RESERVED_335 = 335 -CB_PERF_SEL_RESERVED_336 = 336 -CB_PERF_SEL_RESERVED_337 = 337 -CB_PERF_SEL_RESERVED_338 = 338 -CB_PERF_SEL_RESERVED_339 = 339 -CB_PERF_SEL_RESERVED_340 = 340 -CB_PERF_SEL_RESERVED_341 = 341 -CB_PERF_SEL_RESERVED_342 = 342 -CB_PERF_SEL_RESERVED_343 = 343 -CB_PERF_SEL_RESERVED_344 = 344 -CB_PERF_SEL_RESERVED_345 = 345 -CB_PERF_SEL_RESERVED_346 = 346 -CB_PERF_SEL_RESERVED_347 = 347 -CB_PERF_SEL_RESERVED_348 = 348 -CB_PERF_SEL_RESERVED_349 = 349 -CB_PERF_SEL_RESERVED_350 = 350 -CB_PERF_SEL_RESERVED_351 = 351 -CB_PERF_SEL_RESERVED_352 = 352 -CB_PERF_SEL_RESERVED_353 = 353 -CB_PERF_SEL_RESERVED_354 = 354 -CB_PERF_SEL_RESERVED_355 = 355 -CB_PERF_SEL_RESERVED_356 = 356 -CB_PERF_SEL_RESERVED_357 = 357 -CB_PERF_SEL_RESERVED_358 = 358 -CB_PERF_SEL_RESERVED_359 = 359 -CB_PERF_SEL_RESERVED_360 = 360 -CB_PERF_SEL_RESERVED_361 = 361 -CB_PERF_SEL_RESERVED_362 = 362 -CB_PERF_SEL_RESERVED_363 = 363 -CB_PERF_SEL_RESERVED_364 = 364 -CB_PERF_SEL_RESERVED_365 = 365 -CB_PERF_SEL_RESERVED_366 = 366 -CB_PERF_SEL_RESERVED_367 = 367 -CB_PERF_SEL_RESERVED_368 = 368 -CB_PERF_SEL_RESERVED_369 = 369 -CB_PERF_SEL_RESERVED_370 = 370 -CB_PERF_SEL_RESERVED_371 = 371 -CB_PERF_SEL_RESERVED_372 = 372 -CB_PERF_SEL_RESERVED_373 = 373 -CB_PERF_SEL_RESERVED_374 = 374 -CB_PERF_SEL_RESERVED_375 = 375 -CB_PERF_SEL_RESERVED_376 = 376 -CB_PERF_SEL_RESERVED_377 = 377 -CB_PERF_SEL_RESERVED_378 = 378 -CB_PERF_SEL_RESERVED_379 = 379 -CB_PERF_SEL_RESERVED_380 = 380 -CB_PERF_SEL_RESERVED_381 = 381 -CB_PERF_SEL_RESERVED_382 = 382 -CB_PERF_SEL_RESERVED_383 = 383 -CB_PERF_SEL_RESERVED_384 = 384 -CB_PERF_SEL_RESERVED_385 = 385 -CB_PERF_SEL_RESERVED_386 = 386 -CB_PERF_SEL_RESERVED_387 = 387 -CB_PERF_SEL_RESERVED_388 = 388 -CB_PERF_SEL_RESERVED_389 = 389 -CB_PERF_SEL_RESERVED_390 = 390 -CB_PERF_SEL_RESERVED_391 = 391 -CB_PERF_SEL_RESERVED_392 = 392 -CB_PERF_SEL_RESERVED_393 = 393 -CB_PERF_SEL_RESERVED_394 = 394 -CB_PERF_SEL_RESERVED_395 = 395 -CB_PERF_SEL_RESERVED_396 = 396 -CB_PERF_SEL_RESERVED_397 = 397 -CB_PERF_SEL_RESERVED_398 = 398 -CB_PERF_SEL_RESERVED_399 = 399 -CB_PERF_SEL_RESERVED_400 = 400 -CB_PERF_SEL_RESERVED_401 = 401 -CB_PERF_SEL_RESERVED_402 = 402 -CB_PERF_SEL_RESERVED_403 = 403 -CB_PERF_SEL_RESERVED_404 = 404 -CB_PERF_SEL_RESERVED_405 = 405 -CB_PERF_SEL_RESERVED_406 = 406 -CB_PERF_SEL_RESERVED_407 = 407 -CB_PERF_SEL_RESERVED_408 = 408 -CB_PERF_SEL_RESERVED_409 = 409 -CB_PERF_SEL_RESERVED_410 = 410 -CB_PERF_SEL_RESERVED_411 = 411 -CB_PERF_SEL_RESERVED_412 = 412 -CB_PERF_SEL_RESERVED_413 = 413 -CB_PERF_SEL_RESERVED_414 = 414 -CB_PERF_SEL_RESERVED_415 = 415 -CB_PERF_SEL_RESERVED_416 = 416 -CB_PERF_SEL_RESERVED_417 = 417 -CB_PERF_SEL_RESERVED_418 = 418 -CB_PERF_SEL_RESERVED_419 = 419 -CB_PERF_SEL_RESERVED_420 = 420 -CB_PERF_SEL_RESERVED_421 = 421 -CB_PERF_SEL_RESERVED_422 = 422 -CB_PERF_SEL_RESERVED_423 = 423 -CB_PERF_SEL_RESERVED_424 = 424 -CB_PERF_SEL_RESERVED_425 = 425 -CB_PERF_SEL_RESERVED_426 = 426 -CB_PERF_SEL_RESERVED_427 = 427 -CB_PERF_SEL_RESERVED_428 = 428 -CB_PERF_SEL_RESERVED_429 = 429 -CB_PERF_SEL_RESERVED_430 = 430 -CB_PERF_SEL_RESERVED_431 = 431 -CB_PERF_SEL_RESERVED_432 = 432 -CB_PERF_SEL_RESERVED_433 = 433 -CB_PERF_SEL_RESERVED_434 = 434 -CB_PERF_SEL_RESERVED_435 = 435 -CB_PERF_SEL_RESERVED_436 = 436 -CB_PERF_SEL_RESERVED_437 = 437 -CB_PERF_SEL_RESERVED_438 = 438 -CB_PERF_SEL_RESERVED_439 = 439 -CB_PERF_SEL_RESERVED_440 = 440 -CB_PERF_SEL_RESERVED_441 = 441 -CB_PERF_SEL_RESERVED_442 = 442 -CB_PERF_SEL_RESERVED_443 = 443 -CB_PERF_SEL_RESERVED_444 = 444 -CB_PERF_SEL_RESERVED_445 = 445 -CB_PERF_SEL_RESERVED_446 = 446 -CB_PERF_SEL_RESERVED_447 = 447 -CB_PERF_SEL_RESERVED_448 = 448 -CB_PERF_SEL_RESERVED_449 = 449 -CB_PERF_SEL_RESERVED_450 = 450 -CB_PERF_SEL_RESERVED_451 = 451 -CB_PERF_SEL_RESERVED_452 = 452 -CB_PERF_SEL_RESERVED_453 = 453 -CB_PERF_SEL_RESERVED_454 = 454 -CB_PERF_SEL_RESERVED_455 = 455 -CB_PERF_SEL_RESERVED_456 = 456 -CB_PERF_SEL_RESERVED_457 = 457 -CB_PERF_SEL_RESERVED_458 = 458 -CB_PERF_SEL_RESERVED_459 = 459 -CB_PERF_SEL_RESERVED_460 = 460 -CB_PERF_SEL_RESERVED_461 = 461 -CB_PERF_SEL_RESERVED_462 = 462 -CB_PERF_SEL_RESERVED_463 = 463 -CB_PERF_SEL_RESERVED_464 = 464 -CB_PERF_SEL_RESERVED_465 = 465 -CBPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'CBRamList' -CBRamList__enumvalues = { - 0: 'CB_DCG_CCC_CAS_TAG_ARRAY', - 1: 'CB_DCG_CCC_CAS_FRAG_PTR', - 2: 'CB_DCG_CCC_CAS_COLOR_PTR', - 3: 'CB_DCG_CCC_CAS_SURF_PARAM', - 4: 'CB_DCG_CCC_CAS_KEYID', - 5: 'CB_DCG_BACKEND_RDLAT_FIFO', - 6: 'CB_DCG_FRONTEND_RDLAT_FIFO', - 7: 'CB_DCG_SRC_FIFO', - 8: 'CB_DCG_COLOR_STORE', - 9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE', - 10: 'CB_DCG_FMASK_CACHE_STORE', - 11: 'CB_DCG_READ_SKID_FIFO', - 12: 'CB_DCG_QUAD_PTR_FIFO', - 13: 'CB_DCG_OUTPUT_FIFO', - 14: 'CB_DCG_DCC_CACHE', - 15: 'CB_DCG_DCC_DIRTY_BITS', - 16: 'CB_DCG_QBLOCK_ALLOC', -} -CB_DCG_CCC_CAS_TAG_ARRAY = 0 -CB_DCG_CCC_CAS_FRAG_PTR = 1 -CB_DCG_CCC_CAS_COLOR_PTR = 2 -CB_DCG_CCC_CAS_SURF_PARAM = 3 -CB_DCG_CCC_CAS_KEYID = 4 -CB_DCG_BACKEND_RDLAT_FIFO = 5 -CB_DCG_FRONTEND_RDLAT_FIFO = 6 -CB_DCG_SRC_FIFO = 7 -CB_DCG_COLOR_STORE = 8 -CB_DCG_COLOR_STORE_DIRTY_BYTE = 9 -CB_DCG_FMASK_CACHE_STORE = 10 -CB_DCG_READ_SKID_FIFO = 11 -CB_DCG_QUAD_PTR_FIFO = 12 -CB_DCG_OUTPUT_FIFO = 13 -CB_DCG_DCC_CACHE = 14 -CB_DCG_DCC_DIRTY_BITS = 15 -CB_DCG_QBLOCK_ALLOC = 16 -CBRamList = ctypes.c_uint32 # enum - -# values for enumeration 'CmaskCode' -CmaskCode__enumvalues = { - 0: 'CMASK_CLR00_F0', - 1: 'CMASK_CLR00_F1', - 2: 'CMASK_CLR00_F2', - 3: 'CMASK_CLR00_FX', - 4: 'CMASK_CLR01_F0', - 5: 'CMASK_CLR01_F1', - 6: 'CMASK_CLR01_F2', - 7: 'CMASK_CLR01_FX', - 8: 'CMASK_CLR10_F0', - 9: 'CMASK_CLR10_F1', - 10: 'CMASK_CLR10_F2', - 11: 'CMASK_CLR10_FX', - 12: 'CMASK_CLR11_F0', - 13: 'CMASK_CLR11_F1', - 14: 'CMASK_CLR11_F2', - 15: 'CMASK_CLR11_FX', -} -CMASK_CLR00_F0 = 0 -CMASK_CLR00_F1 = 1 -CMASK_CLR00_F2 = 2 -CMASK_CLR00_FX = 3 -CMASK_CLR01_F0 = 4 -CMASK_CLR01_F1 = 5 -CMASK_CLR01_F2 = 6 -CMASK_CLR01_FX = 7 -CMASK_CLR10_F0 = 8 -CMASK_CLR10_F1 = 9 -CMASK_CLR10_F2 = 10 -CMASK_CLR10_FX = 11 -CMASK_CLR11_F0 = 12 -CMASK_CLR11_F1 = 13 -CMASK_CLR11_F2 = 14 -CMASK_CLR11_FX = 15 -CmaskCode = ctypes.c_uint32 # enum - -# values for enumeration 'CombFunc' -CombFunc__enumvalues = { - 0: 'COMB_DST_PLUS_SRC', - 1: 'COMB_SRC_MINUS_DST', - 2: 'COMB_MIN_DST_SRC', - 3: 'COMB_MAX_DST_SRC', - 4: 'COMB_DST_MINUS_SRC', -} -COMB_DST_PLUS_SRC = 0 -COMB_SRC_MINUS_DST = 1 -COMB_MIN_DST_SRC = 2 -COMB_MAX_DST_SRC = 3 -COMB_DST_MINUS_SRC = 4 -CombFunc = ctypes.c_uint32 # enum - -# values for enumeration 'MemArbMode' -MemArbMode__enumvalues = { - 0: 'MEM_ARB_MODE_FIXED', - 1: 'MEM_ARB_MODE_AGE', - 2: 'MEM_ARB_MODE_WEIGHT', - 3: 'MEM_ARB_MODE_BOTH', -} -MEM_ARB_MODE_FIXED = 0 -MEM_ARB_MODE_AGE = 1 -MEM_ARB_MODE_WEIGHT = 2 -MEM_ARB_MODE_BOTH = 3 -MemArbMode = ctypes.c_uint32 # enum - -# values for enumeration 'SourceFormat' -SourceFormat__enumvalues = { - 0: 'EXPORT_4C_32BPC', - 1: 'EXPORT_4C_16BPC', - 2: 'EXPORT_2C_32BPC_GR', - 3: 'EXPORT_2C_32BPC_AR', -} -EXPORT_4C_32BPC = 0 -EXPORT_4C_16BPC = 1 -EXPORT_2C_32BPC_GR = 2 -EXPORT_2C_32BPC_AR = 3 -SourceFormat = ctypes.c_uint32 # enum - -# values for enumeration 'BinEventCntl' -BinEventCntl__enumvalues = { - 0: 'BINNER_BREAK_BATCH', - 1: 'BINNER_PIPELINE', - 2: 'BINNER_DROP', - 3: 'BINNER_PIPELINE_BREAK', -} -BINNER_BREAK_BATCH = 0 -BINNER_PIPELINE = 1 -BINNER_DROP = 2 -BINNER_PIPELINE_BREAK = 3 -BinEventCntl = ctypes.c_uint32 # enum - -# values for enumeration 'BinMapMode' -BinMapMode__enumvalues = { - 0: 'BIN_MAP_MODE_NONE', - 1: 'BIN_MAP_MODE_RTA_INDEX', - 2: 'BIN_MAP_MODE_POPS', -} -BIN_MAP_MODE_NONE = 0 -BIN_MAP_MODE_RTA_INDEX = 1 -BIN_MAP_MODE_POPS = 2 -BinMapMode = ctypes.c_uint32 # enum - -# values for enumeration 'BinSizeExtend' -BinSizeExtend__enumvalues = { - 0: 'BIN_SIZE_32_PIXELS', - 1: 'BIN_SIZE_64_PIXELS', - 2: 'BIN_SIZE_128_PIXELS', - 3: 'BIN_SIZE_256_PIXELS', - 4: 'BIN_SIZE_512_PIXELS', -} -BIN_SIZE_32_PIXELS = 0 -BIN_SIZE_64_PIXELS = 1 -BIN_SIZE_128_PIXELS = 2 -BIN_SIZE_256_PIXELS = 3 -BIN_SIZE_512_PIXELS = 4 -BinSizeExtend = ctypes.c_uint32 # enum - -# values for enumeration 'BinningMode' -BinningMode__enumvalues = { - 0: 'BINNING_ALLOWED', - 1: 'FORCE_BINNING_ON', - 2: 'DISABLE_BINNING_USE_NEW_SC', - 3: 'DISABLE_BINNING_USE_LEGACY_SC', -} -BINNING_ALLOWED = 0 -FORCE_BINNING_ON = 1 -DISABLE_BINNING_USE_NEW_SC = 2 -DISABLE_BINNING_USE_LEGACY_SC = 3 -BinningMode = ctypes.c_uint32 # enum - -# values for enumeration 'CovToShaderSel' -CovToShaderSel__enumvalues = { - 0: 'INPUT_COVERAGE', - 1: 'INPUT_INNER_COVERAGE', - 2: 'INPUT_DEPTH_COVERAGE', - 3: 'RAW', -} -INPUT_COVERAGE = 0 -INPUT_INNER_COVERAGE = 1 -INPUT_DEPTH_COVERAGE = 2 -RAW = 3 -CovToShaderSel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrMap' -PkrMap__enumvalues = { - 0: 'RASTER_CONFIG_PKR_MAP_0', - 1: 'RASTER_CONFIG_PKR_MAP_1', - 2: 'RASTER_CONFIG_PKR_MAP_2', - 3: 'RASTER_CONFIG_PKR_MAP_3', -} -RASTER_CONFIG_PKR_MAP_0 = 0 -RASTER_CONFIG_PKR_MAP_1 = 1 -RASTER_CONFIG_PKR_MAP_2 = 2 -RASTER_CONFIG_PKR_MAP_3 = 3 -PkrMap = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel' -PkrXsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL_0', - 1: 'RASTER_CONFIG_PKR_XSEL_1', - 2: 'RASTER_CONFIG_PKR_XSEL_2', - 3: 'RASTER_CONFIG_PKR_XSEL_3', -} -RASTER_CONFIG_PKR_XSEL_0 = 0 -RASTER_CONFIG_PKR_XSEL_1 = 1 -RASTER_CONFIG_PKR_XSEL_2 = 2 -RASTER_CONFIG_PKR_XSEL_3 = 3 -PkrXsel = ctypes.c_uint32 # enum - -# values for enumeration 'PkrXsel2' -PkrXsel2__enumvalues = { - 0: 'RASTER_CONFIG_PKR_XSEL2_0', - 1: 'RASTER_CONFIG_PKR_XSEL2_1', - 2: 'RASTER_CONFIG_PKR_XSEL2_2', - 3: 'RASTER_CONFIG_PKR_XSEL2_3', -} -RASTER_CONFIG_PKR_XSEL2_0 = 0 -RASTER_CONFIG_PKR_XSEL2_1 = 1 -RASTER_CONFIG_PKR_XSEL2_2 = 2 -RASTER_CONFIG_PKR_XSEL2_3 = 3 -PkrXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'PkrYsel' -PkrYsel__enumvalues = { - 0: 'RASTER_CONFIG_PKR_YSEL_0', - 1: 'RASTER_CONFIG_PKR_YSEL_1', - 2: 'RASTER_CONFIG_PKR_YSEL_2', - 3: 'RASTER_CONFIG_PKR_YSEL_3', -} -RASTER_CONFIG_PKR_YSEL_0 = 0 -RASTER_CONFIG_PKR_YSEL_1 = 1 -RASTER_CONFIG_PKR_YSEL_2 = 2 -RASTER_CONFIG_PKR_YSEL_3 = 3 -PkrYsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbMap' -RbMap__enumvalues = { - 0: 'RASTER_CONFIG_RB_MAP_0', - 1: 'RASTER_CONFIG_RB_MAP_1', - 2: 'RASTER_CONFIG_RB_MAP_2', - 3: 'RASTER_CONFIG_RB_MAP_3', -} -RASTER_CONFIG_RB_MAP_0 = 0 -RASTER_CONFIG_RB_MAP_1 = 1 -RASTER_CONFIG_RB_MAP_2 = 2 -RASTER_CONFIG_RB_MAP_3 = 3 -RbMap = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel' -RbXsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL_0', - 1: 'RASTER_CONFIG_RB_XSEL_1', -} -RASTER_CONFIG_RB_XSEL_0 = 0 -RASTER_CONFIG_RB_XSEL_1 = 1 -RbXsel = ctypes.c_uint32 # enum - -# values for enumeration 'RbXsel2' -RbXsel2__enumvalues = { - 0: 'RASTER_CONFIG_RB_XSEL2_0', - 1: 'RASTER_CONFIG_RB_XSEL2_1', - 2: 'RASTER_CONFIG_RB_XSEL2_2', - 3: 'RASTER_CONFIG_RB_XSEL2_3', -} -RASTER_CONFIG_RB_XSEL2_0 = 0 -RASTER_CONFIG_RB_XSEL2_1 = 1 -RASTER_CONFIG_RB_XSEL2_2 = 2 -RASTER_CONFIG_RB_XSEL2_3 = 3 -RbXsel2 = ctypes.c_uint32 # enum - -# values for enumeration 'RbYsel' -RbYsel__enumvalues = { - 0: 'RASTER_CONFIG_RB_YSEL_0', - 1: 'RASTER_CONFIG_RB_YSEL_1', -} -RASTER_CONFIG_RB_YSEL_0 = 0 -RASTER_CONFIG_RB_YSEL_1 = 1 -RbYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SC_PERFCNT_SEL' -SC_PERFCNT_SEL__enumvalues = { - 0: 'SC_SRPS_WINDOW_VALID', - 1: 'SC_PSSW_WINDOW_VALID', - 2: 'SC_TPQZ_WINDOW_VALID', - 3: 'SC_QZQP_WINDOW_VALID', - 4: 'SC_TRPK_WINDOW_VALID', - 5: 'SC_SRPS_WINDOW_VALID_BUSY', - 6: 'SC_PSSW_WINDOW_VALID_BUSY', - 7: 'SC_TPQZ_WINDOW_VALID_BUSY', - 8: 'SC_QZQP_WINDOW_VALID_BUSY', - 9: 'SC_TRPK_WINDOW_VALID_BUSY', - 10: 'SC_STARVED_BY_PA', - 11: 'SC_STALLED_BY_PRIMFIFO', - 12: 'SC_STALLED_BY_DB_TILE', - 13: 'SC_STARVED_BY_DB_TILE', - 14: 'SC_STALLED_BY_TILEORDERFIFO', - 15: 'SC_STALLED_BY_TILEFIFO', - 16: 'SC_STALLED_BY_DB_QUAD', - 17: 'SC_STARVED_BY_DB_QUAD', - 18: 'SC_STALLED_BY_QUADFIFO', - 19: 'SC_STALLED_BY_BCI', - 20: 'SC_STALLED_BY_SPI', - 21: 'SC_SCISSOR_DISCARD', - 22: 'SC_BB_DISCARD', - 23: 'SC_SUPERTILE_COUNT', - 24: 'SC_SUPERTILE_PER_PRIM_H0', - 25: 'SC_SUPERTILE_PER_PRIM_H1', - 26: 'SC_SUPERTILE_PER_PRIM_H2', - 27: 'SC_SUPERTILE_PER_PRIM_H3', - 28: 'SC_SUPERTILE_PER_PRIM_H4', - 29: 'SC_SUPERTILE_PER_PRIM_H5', - 30: 'SC_SUPERTILE_PER_PRIM_H6', - 31: 'SC_SUPERTILE_PER_PRIM_H7', - 32: 'SC_SUPERTILE_PER_PRIM_H8', - 33: 'SC_SUPERTILE_PER_PRIM_H9', - 34: 'SC_SUPERTILE_PER_PRIM_H10', - 35: 'SC_SUPERTILE_PER_PRIM_H11', - 36: 'SC_SUPERTILE_PER_PRIM_H12', - 37: 'SC_SUPERTILE_PER_PRIM_H13', - 38: 'SC_SUPERTILE_PER_PRIM_H14', - 39: 'SC_SUPERTILE_PER_PRIM_H15', - 40: 'SC_SUPERTILE_PER_PRIM_H16', - 41: 'SC_TILE_PER_PRIM_H0', - 42: 'SC_TILE_PER_PRIM_H1', - 43: 'SC_TILE_PER_PRIM_H2', - 44: 'SC_TILE_PER_PRIM_H3', - 45: 'SC_TILE_PER_PRIM_H4', - 46: 'SC_TILE_PER_PRIM_H5', - 47: 'SC_TILE_PER_PRIM_H6', - 48: 'SC_TILE_PER_PRIM_H7', - 49: 'SC_TILE_PER_PRIM_H8', - 50: 'SC_TILE_PER_PRIM_H9', - 51: 'SC_TILE_PER_PRIM_H10', - 52: 'SC_TILE_PER_PRIM_H11', - 53: 'SC_TILE_PER_PRIM_H12', - 54: 'SC_TILE_PER_PRIM_H13', - 55: 'SC_TILE_PER_PRIM_H14', - 56: 'SC_TILE_PER_PRIM_H15', - 57: 'SC_TILE_PER_PRIM_H16', - 58: 'SC_TILE_PER_SUPERTILE_H0', - 59: 'SC_TILE_PER_SUPERTILE_H1', - 60: 'SC_TILE_PER_SUPERTILE_H2', - 61: 'SC_TILE_PER_SUPERTILE_H3', - 62: 'SC_TILE_PER_SUPERTILE_H4', - 63: 'SC_TILE_PER_SUPERTILE_H5', - 64: 'SC_TILE_PER_SUPERTILE_H6', - 65: 'SC_TILE_PER_SUPERTILE_H7', - 66: 'SC_TILE_PER_SUPERTILE_H8', - 67: 'SC_TILE_PER_SUPERTILE_H9', - 68: 'SC_TILE_PER_SUPERTILE_H10', - 69: 'SC_TILE_PER_SUPERTILE_H11', - 70: 'SC_TILE_PER_SUPERTILE_H12', - 71: 'SC_TILE_PER_SUPERTILE_H13', - 72: 'SC_TILE_PER_SUPERTILE_H14', - 73: 'SC_TILE_PER_SUPERTILE_H15', - 74: 'SC_TILE_PER_SUPERTILE_H16', - 75: 'SC_TILE_PICKED_H1', - 76: 'SC_TILE_PICKED_H2', - 77: 'SC_TILE_PICKED_H3', - 78: 'SC_TILE_PICKED_H4', - 79: 'SC_QZ0_TILE_COUNT', - 80: 'SC_QZ1_TILE_COUNT', - 81: 'SC_QZ2_TILE_COUNT', - 82: 'SC_QZ3_TILE_COUNT', - 83: 'SC_QZ0_TILE_COVERED_COUNT', - 84: 'SC_QZ1_TILE_COVERED_COUNT', - 85: 'SC_QZ2_TILE_COVERED_COUNT', - 86: 'SC_QZ3_TILE_COVERED_COUNT', - 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', - 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', - 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 91: 'SC_QZ0_QUAD_PER_TILE_H0', - 92: 'SC_QZ0_QUAD_PER_TILE_H1', - 93: 'SC_QZ0_QUAD_PER_TILE_H2', - 94: 'SC_QZ0_QUAD_PER_TILE_H3', - 95: 'SC_QZ0_QUAD_PER_TILE_H4', - 96: 'SC_QZ0_QUAD_PER_TILE_H5', - 97: 'SC_QZ0_QUAD_PER_TILE_H6', - 98: 'SC_QZ0_QUAD_PER_TILE_H7', - 99: 'SC_QZ0_QUAD_PER_TILE_H8', - 100: 'SC_QZ0_QUAD_PER_TILE_H9', - 101: 'SC_QZ0_QUAD_PER_TILE_H10', - 102: 'SC_QZ0_QUAD_PER_TILE_H11', - 103: 'SC_QZ0_QUAD_PER_TILE_H12', - 104: 'SC_QZ0_QUAD_PER_TILE_H13', - 105: 'SC_QZ0_QUAD_PER_TILE_H14', - 106: 'SC_QZ0_QUAD_PER_TILE_H15', - 107: 'SC_QZ0_QUAD_PER_TILE_H16', - 108: 'SC_QZ1_QUAD_PER_TILE_H0', - 109: 'SC_QZ1_QUAD_PER_TILE_H1', - 110: 'SC_QZ1_QUAD_PER_TILE_H2', - 111: 'SC_QZ1_QUAD_PER_TILE_H3', - 112: 'SC_QZ1_QUAD_PER_TILE_H4', - 113: 'SC_QZ1_QUAD_PER_TILE_H5', - 114: 'SC_QZ1_QUAD_PER_TILE_H6', - 115: 'SC_QZ1_QUAD_PER_TILE_H7', - 116: 'SC_QZ1_QUAD_PER_TILE_H8', - 117: 'SC_QZ1_QUAD_PER_TILE_H9', - 118: 'SC_QZ1_QUAD_PER_TILE_H10', - 119: 'SC_QZ1_QUAD_PER_TILE_H11', - 120: 'SC_QZ1_QUAD_PER_TILE_H12', - 121: 'SC_QZ1_QUAD_PER_TILE_H13', - 122: 'SC_QZ1_QUAD_PER_TILE_H14', - 123: 'SC_QZ1_QUAD_PER_TILE_H15', - 124: 'SC_QZ1_QUAD_PER_TILE_H16', - 125: 'SC_QZ2_QUAD_PER_TILE_H0', - 126: 'SC_QZ2_QUAD_PER_TILE_H1', - 127: 'SC_QZ2_QUAD_PER_TILE_H2', - 128: 'SC_QZ2_QUAD_PER_TILE_H3', - 129: 'SC_QZ2_QUAD_PER_TILE_H4', - 130: 'SC_QZ2_QUAD_PER_TILE_H5', - 131: 'SC_QZ2_QUAD_PER_TILE_H6', - 132: 'SC_QZ2_QUAD_PER_TILE_H7', - 133: 'SC_QZ2_QUAD_PER_TILE_H8', - 134: 'SC_QZ2_QUAD_PER_TILE_H9', - 135: 'SC_QZ2_QUAD_PER_TILE_H10', - 136: 'SC_QZ2_QUAD_PER_TILE_H11', - 137: 'SC_QZ2_QUAD_PER_TILE_H12', - 138: 'SC_QZ2_QUAD_PER_TILE_H13', - 139: 'SC_QZ2_QUAD_PER_TILE_H14', - 140: 'SC_QZ2_QUAD_PER_TILE_H15', - 141: 'SC_QZ2_QUAD_PER_TILE_H16', - 142: 'SC_QZ3_QUAD_PER_TILE_H0', - 143: 'SC_QZ3_QUAD_PER_TILE_H1', - 144: 'SC_QZ3_QUAD_PER_TILE_H2', - 145: 'SC_QZ3_QUAD_PER_TILE_H3', - 146: 'SC_QZ3_QUAD_PER_TILE_H4', - 147: 'SC_QZ3_QUAD_PER_TILE_H5', - 148: 'SC_QZ3_QUAD_PER_TILE_H6', - 149: 'SC_QZ3_QUAD_PER_TILE_H7', - 150: 'SC_QZ3_QUAD_PER_TILE_H8', - 151: 'SC_QZ3_QUAD_PER_TILE_H9', - 152: 'SC_QZ3_QUAD_PER_TILE_H10', - 153: 'SC_QZ3_QUAD_PER_TILE_H11', - 154: 'SC_QZ3_QUAD_PER_TILE_H12', - 155: 'SC_QZ3_QUAD_PER_TILE_H13', - 156: 'SC_QZ3_QUAD_PER_TILE_H14', - 157: 'SC_QZ3_QUAD_PER_TILE_H15', - 158: 'SC_QZ3_QUAD_PER_TILE_H16', - 159: 'SC_QZ0_QUAD_COUNT', - 160: 'SC_QZ1_QUAD_COUNT', - 161: 'SC_QZ2_QUAD_COUNT', - 162: 'SC_QZ3_QUAD_COUNT', - 163: 'SC_P0_HIZ_TILE_COUNT', - 164: 'SC_P1_HIZ_TILE_COUNT', - 165: 'SC_P2_HIZ_TILE_COUNT', - 166: 'SC_P3_HIZ_TILE_COUNT', - 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', - 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', - 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', - 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', - 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', - 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', - 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', - 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', - 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', - 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', - 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', - 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', - 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', - 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', - 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', - 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', - 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', - 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', - 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', - 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', - 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', - 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', - 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', - 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', - 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', - 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', - 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', - 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', - 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', - 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', - 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', - 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', - 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', - 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', - 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', - 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', - 235: 'SC_P0_HIZ_QUAD_COUNT', - 236: 'SC_P1_HIZ_QUAD_COUNT', - 237: 'SC_P2_HIZ_QUAD_COUNT', - 238: 'SC_P3_HIZ_QUAD_COUNT', - 239: 'SC_P0_DETAIL_QUAD_COUNT', - 240: 'SC_P1_DETAIL_QUAD_COUNT', - 241: 'SC_P2_DETAIL_QUAD_COUNT', - 242: 'SC_P3_DETAIL_QUAD_COUNT', - 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', - 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', - 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', - 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', - 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', - 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', - 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', - 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', - 259: 'SC_EARLYZ_QUAD_COUNT', - 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', - 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', - 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', - 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', - 264: 'SC_PKR_QUAD_PER_ROW_H1', - 265: 'SC_PKR_QUAD_PER_ROW_H2', - 266: 'SC_PKR_4X2_QUAD_SPLIT', - 267: 'SC_PKR_4X2_FILL_QUAD', - 268: 'SC_PKR_END_OF_VECTOR', - 269: 'SC_PKR_CONTROL_XFER', - 270: 'SC_PKR_DBHANG_FORCE_EOV', - 271: 'SC_REG_SCLK_BUSY', - 272: 'SC_GRP0_DYN_SCLK_BUSY', - 273: 'SC_GRP1_DYN_SCLK_BUSY', - 274: 'SC_GRP2_DYN_SCLK_BUSY', - 275: 'SC_GRP3_DYN_SCLK_BUSY', - 276: 'SC_GRP4_DYN_SCLK_BUSY', - 277: 'SC_PA0_SC_DATA_FIFO_RD', - 278: 'SC_PA0_SC_DATA_FIFO_WE', - 279: 'SC_PA1_SC_DATA_FIFO_RD', - 280: 'SC_PA1_SC_DATA_FIFO_WE', - 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', - 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 284: 'SC_PS_ARB_STALLED_FROM_BELOW', - 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', - 286: 'SC_PS_ARB_SC_BUSY', - 287: 'SC_PS_ARB_PA_SC_BUSY', - 288: 'SC_PA2_SC_DATA_FIFO_RD', - 289: 'SC_PA2_SC_DATA_FIFO_WE', - 290: 'SC_PA3_SC_DATA_FIFO_RD', - 291: 'SC_PA3_SC_DATA_FIFO_WE', - 292: 'SC_PA_SC_DEALLOC_0_0_WE', - 293: 'SC_PA_SC_DEALLOC_0_1_WE', - 294: 'SC_PA_SC_DEALLOC_1_0_WE', - 295: 'SC_PA_SC_DEALLOC_1_1_WE', - 296: 'SC_PA_SC_DEALLOC_2_0_WE', - 297: 'SC_PA_SC_DEALLOC_2_1_WE', - 298: 'SC_PA_SC_DEALLOC_3_0_WE', - 299: 'SC_PA_SC_DEALLOC_3_1_WE', - 300: 'SC_PA0_SC_EOP_WE', - 301: 'SC_PA0_SC_EOPG_WE', - 302: 'SC_PA0_SC_EVENT_WE', - 303: 'SC_PA1_SC_EOP_WE', - 304: 'SC_PA1_SC_EOPG_WE', - 305: 'SC_PA1_SC_EVENT_WE', - 306: 'SC_PA2_SC_EOP_WE', - 307: 'SC_PA2_SC_EOPG_WE', - 308: 'SC_PA2_SC_EVENT_WE', - 309: 'SC_PA3_SC_EOP_WE', - 310: 'SC_PA3_SC_EOPG_WE', - 311: 'SC_PA3_SC_EVENT_WE', - 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', - 316: 'SC_PS_ARB_EVENT_SYNC_POP', - 317: 'SC_PS_ENG_MULTICYCLE_BUBBLE', - 318: 'SC_PA0_SC_FPOV_WE', - 319: 'SC_PA1_SC_FPOV_WE', - 320: 'SC_PA2_SC_FPOV_WE', - 321: 'SC_PA3_SC_FPOV_WE', - 322: 'SC_PA0_SC_LPOV_WE', - 323: 'SC_PA1_SC_LPOV_WE', - 324: 'SC_PA2_SC_LPOV_WE', - 325: 'SC_PA3_SC_LPOV_WE', - 326: 'SC_SPI_DEALLOC_0_0', - 327: 'SC_SPI_DEALLOC_0_1', - 328: 'SC_SPI_DEALLOC_0_2', - 329: 'SC_SPI_DEALLOC_1_0', - 330: 'SC_SPI_DEALLOC_1_1', - 331: 'SC_SPI_DEALLOC_1_2', - 332: 'SC_SPI_DEALLOC_2_0', - 333: 'SC_SPI_DEALLOC_2_1', - 334: 'SC_SPI_DEALLOC_2_2', - 335: 'SC_SPI_DEALLOC_3_0', - 336: 'SC_SPI_DEALLOC_3_1', - 337: 'SC_SPI_DEALLOC_3_2', - 338: 'SC_SPI_FPOV_0', - 339: 'SC_SPI_FPOV_1', - 340: 'SC_SPI_FPOV_2', - 341: 'SC_SPI_FPOV_3', - 342: 'SC_SPI_EVENT', - 343: 'SC_PS_TS_EVENT_FIFO_PUSH', - 344: 'SC_PS_TS_EVENT_FIFO_POP', - 345: 'SC_PS_CTX_DONE_FIFO_PUSH', - 346: 'SC_PS_CTX_DONE_FIFO_POP', - 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', - 348: 'SC_EOP_SYNC_WINDOW', - 349: 'SC_PA0_SC_NULL_WE', - 350: 'SC_PA0_SC_NULL_DEALLOC_WE', - 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', - 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 353: 'SC_PA0_SC_DEALLOC_0_RD', - 354: 'SC_PA0_SC_DEALLOC_1_RD', - 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', - 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 357: 'SC_PA1_SC_DEALLOC_0_RD', - 358: 'SC_PA1_SC_DEALLOC_1_RD', - 359: 'SC_PA1_SC_NULL_WE', - 360: 'SC_PA1_SC_NULL_DEALLOC_WE', - 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', - 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 363: 'SC_PA2_SC_DEALLOC_0_RD', - 364: 'SC_PA2_SC_DEALLOC_1_RD', - 365: 'SC_PA2_SC_NULL_WE', - 366: 'SC_PA2_SC_NULL_DEALLOC_WE', - 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', - 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 369: 'SC_PA3_SC_DEALLOC_0_RD', - 370: 'SC_PA3_SC_DEALLOC_1_RD', - 371: 'SC_PA3_SC_NULL_WE', - 372: 'SC_PA3_SC_NULL_DEALLOC_WE', - 373: 'SC_PS_PA0_SC_FIFO_EMPTY', - 374: 'SC_PS_PA0_SC_FIFO_FULL', - 375: 'SC_RESERVED_0', - 376: 'SC_PS_PA1_SC_FIFO_EMPTY', - 377: 'SC_PS_PA1_SC_FIFO_FULL', - 378: 'SC_RESERVED_1', - 379: 'SC_PS_PA2_SC_FIFO_EMPTY', - 380: 'SC_PS_PA2_SC_FIFO_FULL', - 381: 'SC_RESERVED_2', - 382: 'SC_PS_PA3_SC_FIFO_EMPTY', - 383: 'SC_PS_PA3_SC_FIFO_FULL', - 384: 'SC_RESERVED_3', - 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', - 386: 'SC_BUSY_CNT_NOT_ZERO', - 387: 'SC_BM_BUSY', - 388: 'SC_BACKEND_BUSY', - 389: 'SC_SCF_SCB_INTERFACE_BUSY', - 390: 'SC_SCB_BUSY', - 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', - 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 403: 'SC_PBB_BUSY', - 404: 'SC_PBB_BUSY_AND_NO_SENDS', - 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 406: 'SC_PBB_NUM_BINS', - 407: 'SC_PBB_END_OF_BIN', - 408: 'SC_PBB_END_OF_BATCH', - 409: 'SC_PBB_PRIMBIN_PROCESSED', - 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', - 411: 'SC_PBB_NONBINNED_PRIM', - 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', - 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', - 424: 'SC_POPS_FORCE_EOV', - 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 428: 'SC_FULL_FULL_QUAD', - 429: 'SC_FULL_HALF_QUAD', - 430: 'SC_FULL_QTR_QUAD', - 431: 'SC_HALF_FULL_QUAD', - 432: 'SC_HALF_HALF_QUAD', - 433: 'SC_HALF_QTR_QUAD', - 434: 'SC_QTR_FULL_QUAD', - 435: 'SC_QTR_HALF_QUAD', - 436: 'SC_QTR_QTR_QUAD', - 437: 'SC_GRP5_DYN_SCLK_BUSY', - 438: 'SC_GRP6_DYN_SCLK_BUSY', - 439: 'SC_GRP7_DYN_SCLK_BUSY', - 440: 'SC_GRP8_DYN_SCLK_BUSY', - 441: 'SC_GRP9_DYN_SCLK_BUSY', - 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', - 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 444: 'SC_PK_BUSY', - 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', - 446: 'SC_PK_DEALLOC_WAVE_BREAK', - 447: 'SC_SPI_SEND', - 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 449: 'SC_SPI_CREDIT_AT_MAX', - 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 451: 'SC_BCI_SEND', - 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 453: 'SC_BCI_CREDIT_AT_MAX', - 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 455: 'SC_SPIBC_FULL_FREEZE', - 456: 'SC_PW_BM_PASS_EMPTY_PRIM', - 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 475: 'SC_DB0_TILE_INTERFACE_BUSY', - 476: 'SC_DB0_TILE_INTERFACE_SEND', - 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 483: 'SC_DB1_TILE_INTERFACE_BUSY', - 484: 'SC_DB1_TILE_INTERFACE_SEND', - 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 491: 'SC_BACKEND_PRIM_FIFO_FULL', - 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 503: 'SC_STALLED_BY_DB0_TILEFIFO', - 504: 'SC_DB0_QUAD_INTF_SEND', - 505: 'SC_DB0_QUAD_INTF_BUSY', - 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', - 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', - 508: 'SC_DB0_QUAD_INTF_IDLE', - 509: 'SC_DB1_QUAD_INTF_SEND', - 510: 'SC_STALLED_BY_DB1_TILEFIFO', - 511: 'SC_DB1_QUAD_INTF_BUSY', - 512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB', - 513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', - 514: 'SC_DB1_QUAD_INTF_IDLE', - 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', - 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', - 517: 'SC_FSR_WALKED', - 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', - 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 522: 'SC_DB0_TILE_MASK_FIFO_FULL', - 523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', - 524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 525: 'SC_DB1_TILE_MASK_FIFO_FULL', - 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 529: 'SC_PS_PM_PFF_PW_FULL', - 530: 'SC_PS_PM_ZFF_PW_FULL', - 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', - 533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', - 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', - 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', - 569: 'SC_PBB_RESERVED', - 570: 'SC_BM_BE0_STALLED', - 571: 'SC_BM_BE1_STALLED', - 572: 'SC_BM_BE2_STALLED', - 573: 'SC_BM_BE3_STALLED', - 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', -} -SC_SRPS_WINDOW_VALID = 0 -SC_PSSW_WINDOW_VALID = 1 -SC_TPQZ_WINDOW_VALID = 2 -SC_QZQP_WINDOW_VALID = 3 -SC_TRPK_WINDOW_VALID = 4 -SC_SRPS_WINDOW_VALID_BUSY = 5 -SC_PSSW_WINDOW_VALID_BUSY = 6 -SC_TPQZ_WINDOW_VALID_BUSY = 7 -SC_QZQP_WINDOW_VALID_BUSY = 8 -SC_TRPK_WINDOW_VALID_BUSY = 9 -SC_STARVED_BY_PA = 10 -SC_STALLED_BY_PRIMFIFO = 11 -SC_STALLED_BY_DB_TILE = 12 -SC_STARVED_BY_DB_TILE = 13 -SC_STALLED_BY_TILEORDERFIFO = 14 -SC_STALLED_BY_TILEFIFO = 15 -SC_STALLED_BY_DB_QUAD = 16 -SC_STARVED_BY_DB_QUAD = 17 -SC_STALLED_BY_QUADFIFO = 18 -SC_STALLED_BY_BCI = 19 -SC_STALLED_BY_SPI = 20 -SC_SCISSOR_DISCARD = 21 -SC_BB_DISCARD = 22 -SC_SUPERTILE_COUNT = 23 -SC_SUPERTILE_PER_PRIM_H0 = 24 -SC_SUPERTILE_PER_PRIM_H1 = 25 -SC_SUPERTILE_PER_PRIM_H2 = 26 -SC_SUPERTILE_PER_PRIM_H3 = 27 -SC_SUPERTILE_PER_PRIM_H4 = 28 -SC_SUPERTILE_PER_PRIM_H5 = 29 -SC_SUPERTILE_PER_PRIM_H6 = 30 -SC_SUPERTILE_PER_PRIM_H7 = 31 -SC_SUPERTILE_PER_PRIM_H8 = 32 -SC_SUPERTILE_PER_PRIM_H9 = 33 -SC_SUPERTILE_PER_PRIM_H10 = 34 -SC_SUPERTILE_PER_PRIM_H11 = 35 -SC_SUPERTILE_PER_PRIM_H12 = 36 -SC_SUPERTILE_PER_PRIM_H13 = 37 -SC_SUPERTILE_PER_PRIM_H14 = 38 -SC_SUPERTILE_PER_PRIM_H15 = 39 -SC_SUPERTILE_PER_PRIM_H16 = 40 -SC_TILE_PER_PRIM_H0 = 41 -SC_TILE_PER_PRIM_H1 = 42 -SC_TILE_PER_PRIM_H2 = 43 -SC_TILE_PER_PRIM_H3 = 44 -SC_TILE_PER_PRIM_H4 = 45 -SC_TILE_PER_PRIM_H5 = 46 -SC_TILE_PER_PRIM_H6 = 47 -SC_TILE_PER_PRIM_H7 = 48 -SC_TILE_PER_PRIM_H8 = 49 -SC_TILE_PER_PRIM_H9 = 50 -SC_TILE_PER_PRIM_H10 = 51 -SC_TILE_PER_PRIM_H11 = 52 -SC_TILE_PER_PRIM_H12 = 53 -SC_TILE_PER_PRIM_H13 = 54 -SC_TILE_PER_PRIM_H14 = 55 -SC_TILE_PER_PRIM_H15 = 56 -SC_TILE_PER_PRIM_H16 = 57 -SC_TILE_PER_SUPERTILE_H0 = 58 -SC_TILE_PER_SUPERTILE_H1 = 59 -SC_TILE_PER_SUPERTILE_H2 = 60 -SC_TILE_PER_SUPERTILE_H3 = 61 -SC_TILE_PER_SUPERTILE_H4 = 62 -SC_TILE_PER_SUPERTILE_H5 = 63 -SC_TILE_PER_SUPERTILE_H6 = 64 -SC_TILE_PER_SUPERTILE_H7 = 65 -SC_TILE_PER_SUPERTILE_H8 = 66 -SC_TILE_PER_SUPERTILE_H9 = 67 -SC_TILE_PER_SUPERTILE_H10 = 68 -SC_TILE_PER_SUPERTILE_H11 = 69 -SC_TILE_PER_SUPERTILE_H12 = 70 -SC_TILE_PER_SUPERTILE_H13 = 71 -SC_TILE_PER_SUPERTILE_H14 = 72 -SC_TILE_PER_SUPERTILE_H15 = 73 -SC_TILE_PER_SUPERTILE_H16 = 74 -SC_TILE_PICKED_H1 = 75 -SC_TILE_PICKED_H2 = 76 -SC_TILE_PICKED_H3 = 77 -SC_TILE_PICKED_H4 = 78 -SC_QZ0_TILE_COUNT = 79 -SC_QZ1_TILE_COUNT = 80 -SC_QZ2_TILE_COUNT = 81 -SC_QZ3_TILE_COUNT = 82 -SC_QZ0_TILE_COVERED_COUNT = 83 -SC_QZ1_TILE_COVERED_COUNT = 84 -SC_QZ2_TILE_COVERED_COUNT = 85 -SC_QZ3_TILE_COVERED_COUNT = 86 -SC_QZ0_TILE_NOT_COVERED_COUNT = 87 -SC_QZ1_TILE_NOT_COVERED_COUNT = 88 -SC_QZ2_TILE_NOT_COVERED_COUNT = 89 -SC_QZ3_TILE_NOT_COVERED_COUNT = 90 -SC_QZ0_QUAD_PER_TILE_H0 = 91 -SC_QZ0_QUAD_PER_TILE_H1 = 92 -SC_QZ0_QUAD_PER_TILE_H2 = 93 -SC_QZ0_QUAD_PER_TILE_H3 = 94 -SC_QZ0_QUAD_PER_TILE_H4 = 95 -SC_QZ0_QUAD_PER_TILE_H5 = 96 -SC_QZ0_QUAD_PER_TILE_H6 = 97 -SC_QZ0_QUAD_PER_TILE_H7 = 98 -SC_QZ0_QUAD_PER_TILE_H8 = 99 -SC_QZ0_QUAD_PER_TILE_H9 = 100 -SC_QZ0_QUAD_PER_TILE_H10 = 101 -SC_QZ0_QUAD_PER_TILE_H11 = 102 -SC_QZ0_QUAD_PER_TILE_H12 = 103 -SC_QZ0_QUAD_PER_TILE_H13 = 104 -SC_QZ0_QUAD_PER_TILE_H14 = 105 -SC_QZ0_QUAD_PER_TILE_H15 = 106 -SC_QZ0_QUAD_PER_TILE_H16 = 107 -SC_QZ1_QUAD_PER_TILE_H0 = 108 -SC_QZ1_QUAD_PER_TILE_H1 = 109 -SC_QZ1_QUAD_PER_TILE_H2 = 110 -SC_QZ1_QUAD_PER_TILE_H3 = 111 -SC_QZ1_QUAD_PER_TILE_H4 = 112 -SC_QZ1_QUAD_PER_TILE_H5 = 113 -SC_QZ1_QUAD_PER_TILE_H6 = 114 -SC_QZ1_QUAD_PER_TILE_H7 = 115 -SC_QZ1_QUAD_PER_TILE_H8 = 116 -SC_QZ1_QUAD_PER_TILE_H9 = 117 -SC_QZ1_QUAD_PER_TILE_H10 = 118 -SC_QZ1_QUAD_PER_TILE_H11 = 119 -SC_QZ1_QUAD_PER_TILE_H12 = 120 -SC_QZ1_QUAD_PER_TILE_H13 = 121 -SC_QZ1_QUAD_PER_TILE_H14 = 122 -SC_QZ1_QUAD_PER_TILE_H15 = 123 -SC_QZ1_QUAD_PER_TILE_H16 = 124 -SC_QZ2_QUAD_PER_TILE_H0 = 125 -SC_QZ2_QUAD_PER_TILE_H1 = 126 -SC_QZ2_QUAD_PER_TILE_H2 = 127 -SC_QZ2_QUAD_PER_TILE_H3 = 128 -SC_QZ2_QUAD_PER_TILE_H4 = 129 -SC_QZ2_QUAD_PER_TILE_H5 = 130 -SC_QZ2_QUAD_PER_TILE_H6 = 131 -SC_QZ2_QUAD_PER_TILE_H7 = 132 -SC_QZ2_QUAD_PER_TILE_H8 = 133 -SC_QZ2_QUAD_PER_TILE_H9 = 134 -SC_QZ2_QUAD_PER_TILE_H10 = 135 -SC_QZ2_QUAD_PER_TILE_H11 = 136 -SC_QZ2_QUAD_PER_TILE_H12 = 137 -SC_QZ2_QUAD_PER_TILE_H13 = 138 -SC_QZ2_QUAD_PER_TILE_H14 = 139 -SC_QZ2_QUAD_PER_TILE_H15 = 140 -SC_QZ2_QUAD_PER_TILE_H16 = 141 -SC_QZ3_QUAD_PER_TILE_H0 = 142 -SC_QZ3_QUAD_PER_TILE_H1 = 143 -SC_QZ3_QUAD_PER_TILE_H2 = 144 -SC_QZ3_QUAD_PER_TILE_H3 = 145 -SC_QZ3_QUAD_PER_TILE_H4 = 146 -SC_QZ3_QUAD_PER_TILE_H5 = 147 -SC_QZ3_QUAD_PER_TILE_H6 = 148 -SC_QZ3_QUAD_PER_TILE_H7 = 149 -SC_QZ3_QUAD_PER_TILE_H8 = 150 -SC_QZ3_QUAD_PER_TILE_H9 = 151 -SC_QZ3_QUAD_PER_TILE_H10 = 152 -SC_QZ3_QUAD_PER_TILE_H11 = 153 -SC_QZ3_QUAD_PER_TILE_H12 = 154 -SC_QZ3_QUAD_PER_TILE_H13 = 155 -SC_QZ3_QUAD_PER_TILE_H14 = 156 -SC_QZ3_QUAD_PER_TILE_H15 = 157 -SC_QZ3_QUAD_PER_TILE_H16 = 158 -SC_QZ0_QUAD_COUNT = 159 -SC_QZ1_QUAD_COUNT = 160 -SC_QZ2_QUAD_COUNT = 161 -SC_QZ3_QUAD_COUNT = 162 -SC_P0_HIZ_TILE_COUNT = 163 -SC_P1_HIZ_TILE_COUNT = 164 -SC_P2_HIZ_TILE_COUNT = 165 -SC_P3_HIZ_TILE_COUNT = 166 -SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 -SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 -SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 -SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 -SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 -SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 -SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 -SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 -SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 -SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 -SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 -SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 -SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 -SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 -SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 -SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 -SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 -SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 -SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 -SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 -SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 -SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 -SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 -SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 -SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 -SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 -SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 -SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 -SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 -SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 -SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 -SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 -SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 -SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 -SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 -SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 -SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 -SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 -SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 -SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 -SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 -SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 -SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 -SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 -SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 -SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 -SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 -SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 -SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 -SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 -SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 -SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 -SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 -SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 -SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 -SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 -SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 -SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 -SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 -SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 -SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 -SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 -SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 -SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 -SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 -SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 -SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 -SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 -SC_P0_HIZ_QUAD_COUNT = 235 -SC_P1_HIZ_QUAD_COUNT = 236 -SC_P2_HIZ_QUAD_COUNT = 237 -SC_P3_HIZ_QUAD_COUNT = 238 -SC_P0_DETAIL_QUAD_COUNT = 239 -SC_P1_DETAIL_QUAD_COUNT = 240 -SC_P2_DETAIL_QUAD_COUNT = 241 -SC_P3_DETAIL_QUAD_COUNT = 242 -SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 -SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 -SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 -SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 -SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 -SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 -SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 -SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 -SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 -SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 -SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 -SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 -SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 -SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 -SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 -SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 -SC_EARLYZ_QUAD_COUNT = 259 -SC_EARLYZ_QUAD_WITH_1_PIX = 260 -SC_EARLYZ_QUAD_WITH_2_PIX = 261 -SC_EARLYZ_QUAD_WITH_3_PIX = 262 -SC_EARLYZ_QUAD_WITH_4_PIX = 263 -SC_PKR_QUAD_PER_ROW_H1 = 264 -SC_PKR_QUAD_PER_ROW_H2 = 265 -SC_PKR_4X2_QUAD_SPLIT = 266 -SC_PKR_4X2_FILL_QUAD = 267 -SC_PKR_END_OF_VECTOR = 268 -SC_PKR_CONTROL_XFER = 269 -SC_PKR_DBHANG_FORCE_EOV = 270 -SC_REG_SCLK_BUSY = 271 -SC_GRP0_DYN_SCLK_BUSY = 272 -SC_GRP1_DYN_SCLK_BUSY = 273 -SC_GRP2_DYN_SCLK_BUSY = 274 -SC_GRP3_DYN_SCLK_BUSY = 275 -SC_GRP4_DYN_SCLK_BUSY = 276 -SC_PA0_SC_DATA_FIFO_RD = 277 -SC_PA0_SC_DATA_FIFO_WE = 278 -SC_PA1_SC_DATA_FIFO_RD = 279 -SC_PA1_SC_DATA_FIFO_WE = 280 -SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 -SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 -SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 -SC_PS_ARB_STALLED_FROM_BELOW = 284 -SC_PS_ARB_STARVED_FROM_ABOVE = 285 -SC_PS_ARB_SC_BUSY = 286 -SC_PS_ARB_PA_SC_BUSY = 287 -SC_PA2_SC_DATA_FIFO_RD = 288 -SC_PA2_SC_DATA_FIFO_WE = 289 -SC_PA3_SC_DATA_FIFO_RD = 290 -SC_PA3_SC_DATA_FIFO_WE = 291 -SC_PA_SC_DEALLOC_0_0_WE = 292 -SC_PA_SC_DEALLOC_0_1_WE = 293 -SC_PA_SC_DEALLOC_1_0_WE = 294 -SC_PA_SC_DEALLOC_1_1_WE = 295 -SC_PA_SC_DEALLOC_2_0_WE = 296 -SC_PA_SC_DEALLOC_2_1_WE = 297 -SC_PA_SC_DEALLOC_3_0_WE = 298 -SC_PA_SC_DEALLOC_3_1_WE = 299 -SC_PA0_SC_EOP_WE = 300 -SC_PA0_SC_EOPG_WE = 301 -SC_PA0_SC_EVENT_WE = 302 -SC_PA1_SC_EOP_WE = 303 -SC_PA1_SC_EOPG_WE = 304 -SC_PA1_SC_EVENT_WE = 305 -SC_PA2_SC_EOP_WE = 306 -SC_PA2_SC_EOPG_WE = 307 -SC_PA2_SC_EVENT_WE = 308 -SC_PA3_SC_EOP_WE = 309 -SC_PA3_SC_EOPG_WE = 310 -SC_PA3_SC_EVENT_WE = 311 -SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 -SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 -SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 -SC_PS_ARB_EOP_POP_SYNC_POP = 315 -SC_PS_ARB_EVENT_SYNC_POP = 316 -SC_PS_ENG_MULTICYCLE_BUBBLE = 317 -SC_PA0_SC_FPOV_WE = 318 -SC_PA1_SC_FPOV_WE = 319 -SC_PA2_SC_FPOV_WE = 320 -SC_PA3_SC_FPOV_WE = 321 -SC_PA0_SC_LPOV_WE = 322 -SC_PA1_SC_LPOV_WE = 323 -SC_PA2_SC_LPOV_WE = 324 -SC_PA3_SC_LPOV_WE = 325 -SC_SPI_DEALLOC_0_0 = 326 -SC_SPI_DEALLOC_0_1 = 327 -SC_SPI_DEALLOC_0_2 = 328 -SC_SPI_DEALLOC_1_0 = 329 -SC_SPI_DEALLOC_1_1 = 330 -SC_SPI_DEALLOC_1_2 = 331 -SC_SPI_DEALLOC_2_0 = 332 -SC_SPI_DEALLOC_2_1 = 333 -SC_SPI_DEALLOC_2_2 = 334 -SC_SPI_DEALLOC_3_0 = 335 -SC_SPI_DEALLOC_3_1 = 336 -SC_SPI_DEALLOC_3_2 = 337 -SC_SPI_FPOV_0 = 338 -SC_SPI_FPOV_1 = 339 -SC_SPI_FPOV_2 = 340 -SC_SPI_FPOV_3 = 341 -SC_SPI_EVENT = 342 -SC_PS_TS_EVENT_FIFO_PUSH = 343 -SC_PS_TS_EVENT_FIFO_POP = 344 -SC_PS_CTX_DONE_FIFO_PUSH = 345 -SC_PS_CTX_DONE_FIFO_POP = 346 -SC_MULTICYCLE_BUBBLE_FREEZE = 347 -SC_EOP_SYNC_WINDOW = 348 -SC_PA0_SC_NULL_WE = 349 -SC_PA0_SC_NULL_DEALLOC_WE = 350 -SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 -SC_PA0_SC_DATA_FIFO_EOP_RD = 352 -SC_PA0_SC_DEALLOC_0_RD = 353 -SC_PA0_SC_DEALLOC_1_RD = 354 -SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 -SC_PA1_SC_DATA_FIFO_EOP_RD = 356 -SC_PA1_SC_DEALLOC_0_RD = 357 -SC_PA1_SC_DEALLOC_1_RD = 358 -SC_PA1_SC_NULL_WE = 359 -SC_PA1_SC_NULL_DEALLOC_WE = 360 -SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 -SC_PA2_SC_DATA_FIFO_EOP_RD = 362 -SC_PA2_SC_DEALLOC_0_RD = 363 -SC_PA2_SC_DEALLOC_1_RD = 364 -SC_PA2_SC_NULL_WE = 365 -SC_PA2_SC_NULL_DEALLOC_WE = 366 -SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 -SC_PA3_SC_DATA_FIFO_EOP_RD = 368 -SC_PA3_SC_DEALLOC_0_RD = 369 -SC_PA3_SC_DEALLOC_1_RD = 370 -SC_PA3_SC_NULL_WE = 371 -SC_PA3_SC_NULL_DEALLOC_WE = 372 -SC_PS_PA0_SC_FIFO_EMPTY = 373 -SC_PS_PA0_SC_FIFO_FULL = 374 -SC_RESERVED_0 = 375 -SC_PS_PA1_SC_FIFO_EMPTY = 376 -SC_PS_PA1_SC_FIFO_FULL = 377 -SC_RESERVED_1 = 378 -SC_PS_PA2_SC_FIFO_EMPTY = 379 -SC_PS_PA2_SC_FIFO_FULL = 380 -SC_RESERVED_2 = 381 -SC_PS_PA3_SC_FIFO_EMPTY = 382 -SC_PS_PA3_SC_FIFO_FULL = 383 -SC_RESERVED_3 = 384 -SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 -SC_BUSY_CNT_NOT_ZERO = 386 -SC_BM_BUSY = 387 -SC_BACKEND_BUSY = 388 -SC_SCF_SCB_INTERFACE_BUSY = 389 -SC_SCB_BUSY = 390 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 -SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 -SC_PBB_BIN_HIST_NUM_PRIMS = 393 -SC_PBB_BATCH_HIST_NUM_PRIMS = 394 -SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 -SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 -SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 -SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 -SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 -SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 -SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 -SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 -SC_PBB_BUSY = 403 -SC_PBB_BUSY_AND_NO_SENDS = 404 -SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 -SC_PBB_NUM_BINS = 406 -SC_PBB_END_OF_BIN = 407 -SC_PBB_END_OF_BATCH = 408 -SC_PBB_PRIMBIN_PROCESSED = 409 -SC_PBB_PRIM_ADDED_TO_BATCH = 410 -SC_PBB_NONBINNED_PRIM = 411 -SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 -SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 -SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 -SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 -SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 -SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 -SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 -SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 -SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 -SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 -SC_POPS_INTRA_WAVE_OVERLAPS = 423 -SC_POPS_FORCE_EOV = 424 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 -SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 -SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 -SC_FULL_FULL_QUAD = 428 -SC_FULL_HALF_QUAD = 429 -SC_FULL_QTR_QUAD = 430 -SC_HALF_FULL_QUAD = 431 -SC_HALF_HALF_QUAD = 432 -SC_HALF_QTR_QUAD = 433 -SC_QTR_FULL_QUAD = 434 -SC_QTR_HALF_QUAD = 435 -SC_QTR_QTR_QUAD = 436 -SC_GRP5_DYN_SCLK_BUSY = 437 -SC_GRP6_DYN_SCLK_BUSY = 438 -SC_GRP7_DYN_SCLK_BUSY = 439 -SC_GRP8_DYN_SCLK_BUSY = 440 -SC_GRP9_DYN_SCLK_BUSY = 441 -SC_PS_TO_BE_SCLK_GATE_STALL = 442 -SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 -SC_PK_BUSY = 444 -SC_PK_MAX_DEALLOC_FORCE_EOV = 445 -SC_PK_DEALLOC_WAVE_BREAK = 446 -SC_SPI_SEND = 447 -SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 -SC_SPI_CREDIT_AT_MAX = 449 -SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 -SC_BCI_SEND = 451 -SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 -SC_BCI_CREDIT_AT_MAX = 453 -SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 -SC_SPIBC_FULL_FREEZE = 455 -SC_PW_BM_PASS_EMPTY_PRIM = 456 -SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 -SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 -SC_DB0_TILE_INTERFACE_BUSY = 475 -SC_DB0_TILE_INTERFACE_SEND = 476 -SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 -SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 -SC_DB0_TILE_INTERFACE_SEND_SOP = 479 -SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 -SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 -SC_DB1_TILE_INTERFACE_BUSY = 483 -SC_DB1_TILE_INTERFACE_SEND = 484 -SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 -SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 -SC_DB1_TILE_INTERFACE_SEND_SOP = 487 -SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 -SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 -SC_BACKEND_PRIM_FIFO_FULL = 491 -SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 -SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 -SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 -SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 -SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 -SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 -SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 -SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 -SC_STALLED_BY_DB0_TILEFIFO = 503 -SC_DB0_QUAD_INTF_SEND = 504 -SC_DB0_QUAD_INTF_BUSY = 505 -SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 -SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 -SC_DB0_QUAD_INTF_IDLE = 508 -SC_DB1_QUAD_INTF_SEND = 509 -SC_STALLED_BY_DB1_TILEFIFO = 510 -SC_DB1_QUAD_INTF_BUSY = 511 -SC_DB1_QUAD_INTF_STALLED_BY_DB = 512 -SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513 -SC_DB1_QUAD_INTF_IDLE = 514 -SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 -SC_PKR_WAVE_BREAK_FULL_TILE = 516 -SC_FSR_WALKED = 517 -SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 -SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 -SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 -SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 -SC_DB0_TILE_MASK_FIFO_FULL = 522 -SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523 -SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524 -SC_DB1_TILE_MASK_FIFO_FULL = 525 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 -SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 -SC_PS_PM_PFF_PW_FULL = 529 -SC_PS_PM_ZFF_PW_FULL = 530 -SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 -SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532 -SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533 -SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534 -SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 -SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 -SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 -SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 -SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539 -SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 -SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 -SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 -SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 -SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 -SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 -SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 -SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547 -SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 -SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 -SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 -SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 -SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 -SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 -SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 -SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 -SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 -SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 -SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 -SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 -SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 -SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 -SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 -SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 -SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 -SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 -SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 -SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 -SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568 -SC_PBB_RESERVED = 569 -SC_BM_BE0_STALLED = 570 -SC_BM_BE1_STALLED = 571 -SC_BM_BE2_STALLED = 572 -SC_BM_BE3_STALLED = 573 -SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 -SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 -SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 -SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 -SC_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'ScMap' -ScMap__enumvalues = { - 0: 'RASTER_CONFIG_SC_MAP_0', - 1: 'RASTER_CONFIG_SC_MAP_1', - 2: 'RASTER_CONFIG_SC_MAP_2', - 3: 'RASTER_CONFIG_SC_MAP_3', -} -RASTER_CONFIG_SC_MAP_0 = 0 -RASTER_CONFIG_SC_MAP_1 = 1 -RASTER_CONFIG_SC_MAP_2 = 2 -RASTER_CONFIG_SC_MAP_3 = 3 -ScMap = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMode' -ScUncertaintyRegionMode__enumvalues = { - 0: 'SC_HALF_LSB', - 1: 'SC_LSB_ONE_SIDED', - 2: 'SC_LSB_TWO_SIDED', -} -SC_HALF_LSB = 0 -SC_LSB_ONE_SIDED = 1 -SC_LSB_TWO_SIDED = 2 -ScUncertaintyRegionMode = ctypes.c_uint32 # enum - -# values for enumeration 'ScUncertaintyRegionMult' -ScUncertaintyRegionMult__enumvalues = { - 0: 'SC_UR_1X', - 1: 'SC_UR_2X', - 2: 'SC_UR_4X', - 3: 'SC_UR_8X', -} -SC_UR_1X = 0 -SC_UR_2X = 1 -SC_UR_4X = 2 -SC_UR_8X = 3 -ScUncertaintyRegionMult = ctypes.c_uint32 # enum - -# values for enumeration 'ScXsel' -ScXsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 -ScXsel = ctypes.c_uint32 # enum - -# values for enumeration 'ScYsel' -ScYsel__enumvalues = { - 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 -ScYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeMap' -SeMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_MAP_0', - 1: 'RASTER_CONFIG_SE_MAP_1', - 2: 'RASTER_CONFIG_SE_MAP_2', - 3: 'RASTER_CONFIG_SE_MAP_3', -} -RASTER_CONFIG_SE_MAP_0 = 0 -RASTER_CONFIG_SE_MAP_1 = 1 -RASTER_CONFIG_SE_MAP_2 = 2 -RASTER_CONFIG_SE_MAP_3 = 3 -SeMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairMap' -SePairMap__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', - 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', - 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', - 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', -} -RASTER_CONFIG_SE_PAIR_MAP_0 = 0 -RASTER_CONFIG_SE_PAIR_MAP_1 = 1 -RASTER_CONFIG_SE_PAIR_MAP_2 = 2 -RASTER_CONFIG_SE_PAIR_MAP_3 = 3 -SePairMap = ctypes.c_uint32 # enum - -# values for enumeration 'SePairXsel' -SePairXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 -SePairXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SePairYsel' -SePairYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 -SePairYsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeXsel' -SeXsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 -SeXsel = ctypes.c_uint32 # enum - -# values for enumeration 'SeYsel' -SeYsel__enumvalues = { - 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', - 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', -} -RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 -RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 -RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 -RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 -SeYsel = ctypes.c_uint32 # enum - -# values for enumeration 'VRSCombinerModeSC' -VRSCombinerModeSC__enumvalues = { - 0: 'SC_VRS_COMB_MODE_PASSTHRU', - 1: 'SC_VRS_COMB_MODE_OVERRIDE', - 2: 'SC_VRS_COMB_MODE_MIN', - 3: 'SC_VRS_COMB_MODE_MAX', - 4: 'SC_VRS_COMB_MODE_SATURATE', -} -SC_VRS_COMB_MODE_PASSTHRU = 0 -SC_VRS_COMB_MODE_OVERRIDE = 1 -SC_VRS_COMB_MODE_MIN = 2 -SC_VRS_COMB_MODE_MAX = 3 -SC_VRS_COMB_MODE_SATURATE = 4 -VRSCombinerModeSC = ctypes.c_uint32 # enum - -# values for enumeration 'VRSrate' -VRSrate__enumvalues = { - 0: 'VRS_SHADING_RATE_1X1', - 1: 'VRS_SHADING_RATE_1X2', - 2: 'VRS_SHADING_RATE_UNDEFINED0', - 3: 'VRS_SHADING_RATE_UNDEFINED1', - 4: 'VRS_SHADING_RATE_2X1', - 5: 'VRS_SHADING_RATE_2X2', - 6: 'VRS_SHADING_RATE_2X4', - 7: 'VRS_SHADING_RATE_UNDEFINED2', - 8: 'VRS_SHADING_RATE_UNDEFINED3', - 9: 'VRS_SHADING_RATE_4X2', - 10: 'VRS_SHADING_RATE_4X4', - 11: 'VRS_SHADING_RATE_UNDEFINED4', - 12: 'VRS_SHADING_RATE_16X_SSAA', - 13: 'VRS_SHADING_RATE_8X_SSAA', - 14: 'VRS_SHADING_RATE_4X_SSAA', - 15: 'VRS_SHADING_RATE_2X_SSAA', -} -VRS_SHADING_RATE_1X1 = 0 -VRS_SHADING_RATE_1X2 = 1 -VRS_SHADING_RATE_UNDEFINED0 = 2 -VRS_SHADING_RATE_UNDEFINED1 = 3 -VRS_SHADING_RATE_2X1 = 4 -VRS_SHADING_RATE_2X2 = 5 -VRS_SHADING_RATE_2X4 = 6 -VRS_SHADING_RATE_UNDEFINED2 = 7 -VRS_SHADING_RATE_UNDEFINED3 = 8 -VRS_SHADING_RATE_4X2 = 9 -VRS_SHADING_RATE_4X4 = 10 -VRS_SHADING_RATE_UNDEFINED4 = 11 -VRS_SHADING_RATE_16X_SSAA = 12 -VRS_SHADING_RATE_8X_SSAA = 13 -VRS_SHADING_RATE_4X_SSAA = 14 -VRS_SHADING_RATE_2X_SSAA = 15 -VRSrate = ctypes.c_uint32 # enum - -# values for enumeration 'TC_EA_CID' -TC_EA_CID__enumvalues = { - 0: 'TC_EA_CID_RT', - 1: 'TC_EA_CID_FMASK', - 2: 'TC_EA_CID_DCC', - 3: 'TC_EA_CID_TCPMETA', - 4: 'TC_EA_CID_Z', - 5: 'TC_EA_CID_STENCIL', - 6: 'TC_EA_CID_HTILE', - 7: 'TC_EA_CID_MISC', - 8: 'TC_EA_CID_TCP', - 9: 'TC_EA_CID_SQC', - 10: 'TC_EA_CID_CPF', - 11: 'TC_EA_CID_CPG', - 12: 'TC_EA_CID_IA', - 13: 'TC_EA_CID_WD', - 14: 'TC_EA_CID_PA', - 15: 'TC_EA_CID_UTCL2_TPI', -} -TC_EA_CID_RT = 0 -TC_EA_CID_FMASK = 1 -TC_EA_CID_DCC = 2 -TC_EA_CID_TCPMETA = 3 -TC_EA_CID_Z = 4 -TC_EA_CID_STENCIL = 5 -TC_EA_CID_HTILE = 6 -TC_EA_CID_MISC = 7 -TC_EA_CID_TCP = 8 -TC_EA_CID_SQC = 9 -TC_EA_CID_CPF = 10 -TC_EA_CID_CPG = 11 -TC_EA_CID_IA = 12 -TC_EA_CID_WD = 13 -TC_EA_CID_PA = 14 -TC_EA_CID_UTCL2_TPI = 15 -TC_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'TC_NACKS' -TC_NACKS__enumvalues = { - 0: 'TC_NACK_NO_FAULT', - 1: 'TC_NACK_PAGE_FAULT', - 2: 'TC_NACK_PROTECTION_FAULT', - 3: 'TC_NACK_DATA_ERROR', -} -TC_NACK_NO_FAULT = 0 -TC_NACK_PAGE_FAULT = 1 -TC_NACK_PROTECTION_FAULT = 2 -TC_NACK_DATA_ERROR = 3 -TC_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP' -TC_OP__enumvalues = { - 0: 'TC_OP_READ', - 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'TC_OP_ATOMIC_FMIN_RTN_32', - 3: 'TC_OP_ATOMIC_FMAX_RTN_32', - 4: 'TC_OP_RESERVED_FOP_RTN_32_0', - 5: 'TC_OP_RESERVED_FADD_RTN_32', - 6: 'TC_OP_RESERVED_FOP_RTN_32_2', - 7: 'TC_OP_ATOMIC_SWAP_RTN_32', - 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'TC_OP_PROBE_FILTER', - 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'TC_OP_ATOMIC_ADD_RTN_32', - 16: 'TC_OP_ATOMIC_SUB_RTN_32', - 17: 'TC_OP_ATOMIC_SMIN_RTN_32', - 18: 'TC_OP_ATOMIC_UMIN_RTN_32', - 19: 'TC_OP_ATOMIC_SMAX_RTN_32', - 20: 'TC_OP_ATOMIC_UMAX_RTN_32', - 21: 'TC_OP_ATOMIC_AND_RTN_32', - 22: 'TC_OP_ATOMIC_OR_RTN_32', - 23: 'TC_OP_ATOMIC_XOR_RTN_32', - 24: 'TC_OP_ATOMIC_INC_RTN_32', - 25: 'TC_OP_ATOMIC_DEC_RTN_32', - 26: 'TC_OP_WBINVL1_VOL', - 27: 'TC_OP_WBINVL1_SD', - 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 32: 'TC_OP_WRITE', - 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'TC_OP_ATOMIC_FMIN_RTN_64', - 35: 'TC_OP_ATOMIC_FMAX_RTN_64', - 36: 'TC_OP_RESERVED_FOP_RTN_64_0', - 37: 'TC_OP_RESERVED_FOP_RTN_64_1', - 38: 'TC_OP_RESERVED_FOP_RTN_64_2', - 39: 'TC_OP_ATOMIC_SWAP_RTN_64', - 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 44: 'TC_OP_WBINVL2_SD', - 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 47: 'TC_OP_ATOMIC_ADD_RTN_64', - 48: 'TC_OP_ATOMIC_SUB_RTN_64', - 49: 'TC_OP_ATOMIC_SMIN_RTN_64', - 50: 'TC_OP_ATOMIC_UMIN_RTN_64', - 51: 'TC_OP_ATOMIC_SMAX_RTN_64', - 52: 'TC_OP_ATOMIC_UMAX_RTN_64', - 53: 'TC_OP_ATOMIC_AND_RTN_64', - 54: 'TC_OP_ATOMIC_OR_RTN_64', - 55: 'TC_OP_ATOMIC_XOR_RTN_64', - 56: 'TC_OP_ATOMIC_INC_RTN_64', - 57: 'TC_OP_ATOMIC_DEC_RTN_64', - 58: 'TC_OP_WBL2_NC', - 59: 'TC_OP_WBL2_WC', - 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', - 64: 'TC_OP_WBINVL1', - 65: 'TC_OP_ATOMIC_FCMPSWAP_32', - 66: 'TC_OP_ATOMIC_FMIN_32', - 67: 'TC_OP_ATOMIC_FMAX_32', - 68: 'TC_OP_RESERVED_FOP_32_0', - 69: 'TC_OP_RESERVED_FADD_32', - 70: 'TC_OP_RESERVED_FOP_32_2', - 71: 'TC_OP_ATOMIC_SWAP_32', - 72: 'TC_OP_ATOMIC_CMPSWAP_32', - 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'TC_OP_INV_METADATA', - 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 79: 'TC_OP_ATOMIC_ADD_32', - 80: 'TC_OP_ATOMIC_SUB_32', - 81: 'TC_OP_ATOMIC_SMIN_32', - 82: 'TC_OP_ATOMIC_UMIN_32', - 83: 'TC_OP_ATOMIC_SMAX_32', - 84: 'TC_OP_ATOMIC_UMAX_32', - 85: 'TC_OP_ATOMIC_AND_32', - 86: 'TC_OP_ATOMIC_OR_32', - 87: 'TC_OP_ATOMIC_XOR_32', - 88: 'TC_OP_ATOMIC_INC_32', - 89: 'TC_OP_ATOMIC_DEC_32', - 90: 'TC_OP_INVL2_NC', - 91: 'TC_OP_NOP_RTN0', - 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', - 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', - 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', - 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', - 96: 'TC_OP_WBINVL2', - 97: 'TC_OP_ATOMIC_FCMPSWAP_64', - 98: 'TC_OP_ATOMIC_FMIN_64', - 99: 'TC_OP_ATOMIC_FMAX_64', - 100: 'TC_OP_RESERVED_FOP_64_0', - 101: 'TC_OP_RESERVED_FOP_64_1', - 102: 'TC_OP_RESERVED_FOP_64_2', - 103: 'TC_OP_ATOMIC_SWAP_64', - 104: 'TC_OP_ATOMIC_CMPSWAP_64', - 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 111: 'TC_OP_ATOMIC_ADD_64', - 112: 'TC_OP_ATOMIC_SUB_64', - 113: 'TC_OP_ATOMIC_SMIN_64', - 114: 'TC_OP_ATOMIC_UMIN_64', - 115: 'TC_OP_ATOMIC_SMAX_64', - 116: 'TC_OP_ATOMIC_UMAX_64', - 117: 'TC_OP_ATOMIC_AND_64', - 118: 'TC_OP_ATOMIC_OR_64', - 119: 'TC_OP_ATOMIC_XOR_64', - 120: 'TC_OP_ATOMIC_INC_64', - 121: 'TC_OP_ATOMIC_DEC_64', - 122: 'TC_OP_WBINVL2_NC', - 123: 'TC_OP_NOP_ACK', - 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', - 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', - 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', - 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', -} -TC_OP_READ = 0 -TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -TC_OP_ATOMIC_FMIN_RTN_32 = 2 -TC_OP_ATOMIC_FMAX_RTN_32 = 3 -TC_OP_RESERVED_FOP_RTN_32_0 = 4 -TC_OP_RESERVED_FADD_RTN_32 = 5 -TC_OP_RESERVED_FOP_RTN_32_2 = 6 -TC_OP_ATOMIC_SWAP_RTN_32 = 7 -TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -TC_OP_PROBE_FILTER = 12 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -TC_OP_ATOMIC_ADD_RTN_32 = 15 -TC_OP_ATOMIC_SUB_RTN_32 = 16 -TC_OP_ATOMIC_SMIN_RTN_32 = 17 -TC_OP_ATOMIC_UMIN_RTN_32 = 18 -TC_OP_ATOMIC_SMAX_RTN_32 = 19 -TC_OP_ATOMIC_UMAX_RTN_32 = 20 -TC_OP_ATOMIC_AND_RTN_32 = 21 -TC_OP_ATOMIC_OR_RTN_32 = 22 -TC_OP_ATOMIC_XOR_RTN_32 = 23 -TC_OP_ATOMIC_INC_RTN_32 = 24 -TC_OP_ATOMIC_DEC_RTN_32 = 25 -TC_OP_WBINVL1_VOL = 26 -TC_OP_WBINVL1_SD = 27 -TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 -TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 -TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 -TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 -TC_OP_WRITE = 32 -TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -TC_OP_ATOMIC_FMIN_RTN_64 = 34 -TC_OP_ATOMIC_FMAX_RTN_64 = 35 -TC_OP_RESERVED_FOP_RTN_64_0 = 36 -TC_OP_RESERVED_FOP_RTN_64_1 = 37 -TC_OP_RESERVED_FOP_RTN_64_2 = 38 -TC_OP_ATOMIC_SWAP_RTN_64 = 39 -TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -TC_OP_WBINVL2_SD = 44 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 -TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 -TC_OP_ATOMIC_ADD_RTN_64 = 47 -TC_OP_ATOMIC_SUB_RTN_64 = 48 -TC_OP_ATOMIC_SMIN_RTN_64 = 49 -TC_OP_ATOMIC_UMIN_RTN_64 = 50 -TC_OP_ATOMIC_SMAX_RTN_64 = 51 -TC_OP_ATOMIC_UMAX_RTN_64 = 52 -TC_OP_ATOMIC_AND_RTN_64 = 53 -TC_OP_ATOMIC_OR_RTN_64 = 54 -TC_OP_ATOMIC_XOR_RTN_64 = 55 -TC_OP_ATOMIC_INC_RTN_64 = 56 -TC_OP_ATOMIC_DEC_RTN_64 = 57 -TC_OP_WBL2_NC = 58 -TC_OP_WBL2_WC = 59 -TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 -TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 -TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 -TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 -TC_OP_WBINVL1 = 64 -TC_OP_ATOMIC_FCMPSWAP_32 = 65 -TC_OP_ATOMIC_FMIN_32 = 66 -TC_OP_ATOMIC_FMAX_32 = 67 -TC_OP_RESERVED_FOP_32_0 = 68 -TC_OP_RESERVED_FADD_32 = 69 -TC_OP_RESERVED_FOP_32_2 = 70 -TC_OP_ATOMIC_SWAP_32 = 71 -TC_OP_ATOMIC_CMPSWAP_32 = 72 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -TC_OP_INV_METADATA = 76 -TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 -TC_OP_ATOMIC_ADD_32 = 79 -TC_OP_ATOMIC_SUB_32 = 80 -TC_OP_ATOMIC_SMIN_32 = 81 -TC_OP_ATOMIC_UMIN_32 = 82 -TC_OP_ATOMIC_SMAX_32 = 83 -TC_OP_ATOMIC_UMAX_32 = 84 -TC_OP_ATOMIC_AND_32 = 85 -TC_OP_ATOMIC_OR_32 = 86 -TC_OP_ATOMIC_XOR_32 = 87 -TC_OP_ATOMIC_INC_32 = 88 -TC_OP_ATOMIC_DEC_32 = 89 -TC_OP_INVL2_NC = 90 -TC_OP_NOP_RTN0 = 91 -TC_OP_RESERVED_NON_FLOAT_32_1 = 92 -TC_OP_RESERVED_NON_FLOAT_32_2 = 93 -TC_OP_RESERVED_NON_FLOAT_32_3 = 94 -TC_OP_RESERVED_NON_FLOAT_32_4 = 95 -TC_OP_WBINVL2 = 96 -TC_OP_ATOMIC_FCMPSWAP_64 = 97 -TC_OP_ATOMIC_FMIN_64 = 98 -TC_OP_ATOMIC_FMAX_64 = 99 -TC_OP_RESERVED_FOP_64_0 = 100 -TC_OP_RESERVED_FOP_64_1 = 101 -TC_OP_RESERVED_FOP_64_2 = 102 -TC_OP_ATOMIC_SWAP_64 = 103 -TC_OP_ATOMIC_CMPSWAP_64 = 104 -TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 -TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 -TC_OP_ATOMIC_ADD_64 = 111 -TC_OP_ATOMIC_SUB_64 = 112 -TC_OP_ATOMIC_SMIN_64 = 113 -TC_OP_ATOMIC_UMIN_64 = 114 -TC_OP_ATOMIC_SMAX_64 = 115 -TC_OP_ATOMIC_UMAX_64 = 116 -TC_OP_ATOMIC_AND_64 = 117 -TC_OP_ATOMIC_OR_64 = 118 -TC_OP_ATOMIC_XOR_64 = 119 -TC_OP_ATOMIC_INC_64 = 120 -TC_OP_ATOMIC_DEC_64 = 121 -TC_OP_WBINVL2_NC = 122 -TC_OP_NOP_ACK = 123 -TC_OP_RESERVED_NON_FLOAT_64_1 = 124 -TC_OP_RESERVED_NON_FLOAT_64_2 = 125 -TC_OP_RESERVED_NON_FLOAT_64_3 = 126 -TC_OP_RESERVED_NON_FLOAT_64_4 = 127 -TC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'TC_OP_MASKS' -TC_OP_MASKS__enumvalues = { - 8: 'TC_OP_MASK_FLUSH_DENROM', - 32: 'TC_OP_MASK_64', - 64: 'TC_OP_MASK_NO_RTN', -} -TC_OP_MASK_FLUSH_DENROM = 8 -TC_OP_MASK_64 = 32 -TC_OP_MASK_NO_RTN = 64 -TC_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_EA_CID' -GL2_EA_CID__enumvalues = { - 0: 'GL2_EA_CID_CLIENT', - 1: 'GL2_EA_CID_SDMA', - 2: 'GL2_EA_CID_RLC', - 3: 'GL2_EA_CID_SQC', - 4: 'GL2_EA_CID_CP', - 5: 'GL2_EA_CID_CPDMA', - 6: 'GL2_EA_CID_UTCL2', - 7: 'GL2_EA_CID_RT', - 8: 'GL2_EA_CID_FMASK', - 9: 'GL2_EA_CID_DCC', - 10: 'GL2_EA_CID_Z_STENCIL', - 11: 'GL2_EA_CID_ZPCPSD', - 12: 'GL2_EA_CID_HTILE', - 13: 'GL2_EA_CID_MES', - 15: 'GL2_EA_CID_TCPMETA', -} -GL2_EA_CID_CLIENT = 0 -GL2_EA_CID_SDMA = 1 -GL2_EA_CID_RLC = 2 -GL2_EA_CID_SQC = 3 -GL2_EA_CID_CP = 4 -GL2_EA_CID_CPDMA = 5 -GL2_EA_CID_UTCL2 = 6 -GL2_EA_CID_RT = 7 -GL2_EA_CID_FMASK = 8 -GL2_EA_CID_DCC = 9 -GL2_EA_CID_Z_STENCIL = 10 -GL2_EA_CID_ZPCPSD = 11 -GL2_EA_CID_HTILE = 12 -GL2_EA_CID_MES = 13 -GL2_EA_CID_TCPMETA = 15 -GL2_EA_CID = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_NACKS' -GL2_NACKS__enumvalues = { - 0: 'GL2_NACK_NO_FAULT', - 1: 'GL2_NACK_PAGE_FAULT', - 2: 'GL2_NACK_PROTECTION_FAULT', - 3: 'GL2_NACK_DATA_ERROR', -} -GL2_NACK_NO_FAULT = 0 -GL2_NACK_PAGE_FAULT = 1 -GL2_NACK_PROTECTION_FAULT = 2 -GL2_NACK_DATA_ERROR = 3 -GL2_NACKS = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP' -GL2_OP__enumvalues = { - 0: 'GL2_OP_READ', - 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', - 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', - 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', - 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', - 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', - 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 12: 'GL2_OP_PROBE_FILTER', - 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 15: 'GL2_OP_ATOMIC_ADD_RTN_32', - 16: 'GL2_OP_ATOMIC_SUB_RTN_32', - 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', - 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', - 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', - 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', - 21: 'GL2_OP_ATOMIC_AND_RTN_32', - 22: 'GL2_OP_ATOMIC_OR_RTN_32', - 23: 'GL2_OP_ATOMIC_XOR_RTN_32', - 24: 'GL2_OP_ATOMIC_INC_RTN_32', - 25: 'GL2_OP_ATOMIC_DEC_RTN_32', - 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 32: 'GL2_OP_WRITE', - 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', - 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', - 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', - 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 47: 'GL2_OP_ATOMIC_ADD_RTN_64', - 48: 'GL2_OP_ATOMIC_SUB_RTN_64', - 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', - 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', - 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', - 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', - 53: 'GL2_OP_ATOMIC_AND_RTN_64', - 54: 'GL2_OP_ATOMIC_OR_RTN_64', - 55: 'GL2_OP_ATOMIC_XOR_RTN_64', - 56: 'GL2_OP_ATOMIC_INC_RTN_64', - 57: 'GL2_OP_ATOMIC_DEC_RTN_64', - 64: 'GL2_OP_GL1_INV', - 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', - 66: 'GL2_OP_ATOMIC_FMIN_32', - 67: 'GL2_OP_ATOMIC_FMAX_32', - 71: 'GL2_OP_ATOMIC_SWAP_32', - 72: 'GL2_OP_ATOMIC_CMPSWAP_32', - 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 76: 'GL2_OP_ATOMIC_UMIN_8', - 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 79: 'GL2_OP_ATOMIC_ADD_32', - 80: 'GL2_OP_ATOMIC_SUB_32', - 81: 'GL2_OP_ATOMIC_SMIN_32', - 82: 'GL2_OP_ATOMIC_UMIN_32', - 83: 'GL2_OP_ATOMIC_SMAX_32', - 84: 'GL2_OP_ATOMIC_UMAX_32', - 85: 'GL2_OP_ATOMIC_AND_32', - 86: 'GL2_OP_ATOMIC_OR_32', - 87: 'GL2_OP_ATOMIC_XOR_32', - 88: 'GL2_OP_ATOMIC_INC_32', - 89: 'GL2_OP_ATOMIC_DEC_32', - 91: 'GL2_OP_NOP_RTN0', - 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', - 98: 'GL2_OP_ATOMIC_FMIN_64', - 99: 'GL2_OP_ATOMIC_FMAX_64', - 103: 'GL2_OP_ATOMIC_SWAP_64', - 104: 'GL2_OP_ATOMIC_CMPSWAP_64', - 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 111: 'GL2_OP_ATOMIC_ADD_64', - 112: 'GL2_OP_ATOMIC_SUB_64', - 113: 'GL2_OP_ATOMIC_SMIN_64', - 114: 'GL2_OP_ATOMIC_UMIN_64', - 115: 'GL2_OP_ATOMIC_SMAX_64', - 116: 'GL2_OP_ATOMIC_UMAX_64', - 117: 'GL2_OP_ATOMIC_AND_64', - 118: 'GL2_OP_ATOMIC_OR_64', - 119: 'GL2_OP_ATOMIC_XOR_64', - 120: 'GL2_OP_ATOMIC_INC_64', - 121: 'GL2_OP_ATOMIC_DEC_64', - 122: 'GL2_OP_ATOMIC_UMAX_8', - 123: 'GL2_OP_NOP_ACK', -} -GL2_OP_READ = 0 -GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 -GL2_OP_ATOMIC_FMIN_RTN_32 = 2 -GL2_OP_ATOMIC_FMAX_RTN_32 = 3 -GL2_OP_ATOMIC_SWAP_RTN_32 = 7 -GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 -GL2_OP_PROBE_FILTER = 12 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 -GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 -GL2_OP_ATOMIC_ADD_RTN_32 = 15 -GL2_OP_ATOMIC_SUB_RTN_32 = 16 -GL2_OP_ATOMIC_SMIN_RTN_32 = 17 -GL2_OP_ATOMIC_UMIN_RTN_32 = 18 -GL2_OP_ATOMIC_SMAX_RTN_32 = 19 -GL2_OP_ATOMIC_UMAX_RTN_32 = 20 -GL2_OP_ATOMIC_AND_RTN_32 = 21 -GL2_OP_ATOMIC_OR_RTN_32 = 22 -GL2_OP_ATOMIC_XOR_RTN_32 = 23 -GL2_OP_ATOMIC_INC_RTN_32 = 24 -GL2_OP_ATOMIC_DEC_RTN_32 = 25 -GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 -GL2_OP_WRITE = 32 -GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 -GL2_OP_ATOMIC_FMIN_RTN_64 = 34 -GL2_OP_ATOMIC_FMAX_RTN_64 = 35 -GL2_OP_ATOMIC_SWAP_RTN_64 = 39 -GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 -GL2_OP_ATOMIC_ADD_RTN_64 = 47 -GL2_OP_ATOMIC_SUB_RTN_64 = 48 -GL2_OP_ATOMIC_SMIN_RTN_64 = 49 -GL2_OP_ATOMIC_UMIN_RTN_64 = 50 -GL2_OP_ATOMIC_SMAX_RTN_64 = 51 -GL2_OP_ATOMIC_UMAX_RTN_64 = 52 -GL2_OP_ATOMIC_AND_RTN_64 = 53 -GL2_OP_ATOMIC_OR_RTN_64 = 54 -GL2_OP_ATOMIC_XOR_RTN_64 = 55 -GL2_OP_ATOMIC_INC_RTN_64 = 56 -GL2_OP_ATOMIC_DEC_RTN_64 = 57 -GL2_OP_GL1_INV = 64 -GL2_OP_ATOMIC_FCMPSWAP_32 = 65 -GL2_OP_ATOMIC_FMIN_32 = 66 -GL2_OP_ATOMIC_FMAX_32 = 67 -GL2_OP_ATOMIC_SWAP_32 = 71 -GL2_OP_ATOMIC_CMPSWAP_32 = 72 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 -GL2_OP_ATOMIC_UMIN_8 = 76 -GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 -GL2_OP_ATOMIC_ADD_32 = 79 -GL2_OP_ATOMIC_SUB_32 = 80 -GL2_OP_ATOMIC_SMIN_32 = 81 -GL2_OP_ATOMIC_UMIN_32 = 82 -GL2_OP_ATOMIC_SMAX_32 = 83 -GL2_OP_ATOMIC_UMAX_32 = 84 -GL2_OP_ATOMIC_AND_32 = 85 -GL2_OP_ATOMIC_OR_32 = 86 -GL2_OP_ATOMIC_XOR_32 = 87 -GL2_OP_ATOMIC_INC_32 = 88 -GL2_OP_ATOMIC_DEC_32 = 89 -GL2_OP_NOP_RTN0 = 91 -GL2_OP_ATOMIC_FCMPSWAP_64 = 97 -GL2_OP_ATOMIC_FMIN_64 = 98 -GL2_OP_ATOMIC_FMAX_64 = 99 -GL2_OP_ATOMIC_SWAP_64 = 103 -GL2_OP_ATOMIC_CMPSWAP_64 = 104 -GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 -GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 -GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 -GL2_OP_ATOMIC_ADD_64 = 111 -GL2_OP_ATOMIC_SUB_64 = 112 -GL2_OP_ATOMIC_SMIN_64 = 113 -GL2_OP_ATOMIC_UMIN_64 = 114 -GL2_OP_ATOMIC_SMAX_64 = 115 -GL2_OP_ATOMIC_UMAX_64 = 116 -GL2_OP_ATOMIC_AND_64 = 117 -GL2_OP_ATOMIC_OR_64 = 118 -GL2_OP_ATOMIC_XOR_64 = 119 -GL2_OP_ATOMIC_INC_64 = 120 -GL2_OP_ATOMIC_DEC_64 = 121 -GL2_OP_ATOMIC_UMAX_8 = 122 -GL2_OP_NOP_ACK = 123 -GL2_OP = ctypes.c_uint32 # enum - -# values for enumeration 'GL2_OP_MASKS' -GL2_OP_MASKS__enumvalues = { - 8: 'GL2_OP_MASK_FLUSH_DENROM', - 32: 'GL2_OP_MASK_64', - 64: 'GL2_OP_MASK_NO_RTN', -} -GL2_OP_MASK_FLUSH_DENROM = 8 -GL2_OP_MASK_64 = 32 -GL2_OP_MASK_NO_RTN = 64 -GL2_OP_MASKS = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_DOORBELL_MODE' -RLC_DOORBELL_MODE__enumvalues = { - 0: 'RLC_DOORBELL_MODE_DISABLE', - 1: 'RLC_DOORBELL_MODE_ENABLE', - 2: 'RLC_DOORBELL_MODE_ENABLE_PF', - 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', -} -RLC_DOORBELL_MODE_DISABLE = 0 -RLC_DOORBELL_MODE_ENABLE = 1 -RLC_DOORBELL_MODE_ENABLE_PF = 2 -RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 -RLC_DOORBELL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFCOUNTER_SEL' -RLC_PERFCOUNTER_SEL__enumvalues = { - 0: 'RLC_PERF_SEL_POWER_FEATURE_0', - 1: 'RLC_PERF_SEL_POWER_FEATURE_1', - 2: 'RLC_PERF_SEL_CP_INTERRUPT', - 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', - 4: 'RLC_PERF_SEL_SPM_INTERRUPT', - 5: 'RLC_PERF_SEL_IH_INTERRUPT', - 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', -} -RLC_PERF_SEL_POWER_FEATURE_0 = 0 -RLC_PERF_SEL_POWER_FEATURE_1 = 1 -RLC_PERF_SEL_CP_INTERRUPT = 2 -RLC_PERF_SEL_GRBM_INTERRUPT = 3 -RLC_PERF_SEL_SPM_INTERRUPT = 4 -RLC_PERF_SEL_IH_INTERRUPT = 5 -RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 -RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'RLC_PERFMON_STATE' -RLC_PERFMON_STATE__enumvalues = { - 0: 'RLC_PERFMON_STATE_RESET', - 1: 'RLC_PERFMON_STATE_ENABLE', - 2: 'RLC_PERFMON_STATE_DISABLE', - 3: 'RLC_PERFMON_STATE_RESERVED_3', - 4: 'RLC_PERFMON_STATE_RESERVED_4', - 5: 'RLC_PERFMON_STATE_RESERVED_5', - 6: 'RLC_PERFMON_STATE_RESERVED_6', - 7: 'RLC_PERFMON_STATE_ROLLOVER', -} -RLC_PERFMON_STATE_RESET = 0 -RLC_PERFMON_STATE_ENABLE = 1 -RLC_PERFMON_STATE_DISABLE = 2 -RLC_PERFMON_STATE_RESERVED_3 = 3 -RLC_PERFMON_STATE_RESERVED_4 = 4 -RLC_PERFMON_STATE_RESERVED_5 = 5 -RLC_PERFMON_STATE_RESERVED_6 = 6 -RLC_PERFMON_STATE_ROLLOVER = 7 -RLC_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'RSPM_CMD' -RSPM_CMD__enumvalues = { - 0: 'RSPM_CMD_INVALID', - 1: 'RSPM_CMD_IDLE', - 2: 'RSPM_CMD_CALIBRATE', - 3: 'RSPM_CMD_SPM_RESET', - 4: 'RSPM_CMD_SPM_START', - 5: 'RSPM_CMD_SPM_STOP', - 6: 'RSPM_CMD_PERF_RESET', - 7: 'RSPM_CMD_PERF_SAMPLE', - 8: 'RSPM_CMD_PROF_START', - 9: 'RSPM_CMD_PROF_STOP', - 10: 'RSPM_CMD_FORCE_SAMPLE', -} -RSPM_CMD_INVALID = 0 -RSPM_CMD_IDLE = 1 -RSPM_CMD_CALIBRATE = 2 -RSPM_CMD_SPM_RESET = 3 -RSPM_CMD_SPM_START = 4 -RSPM_CMD_SPM_STOP = 5 -RSPM_CMD_PERF_RESET = 6 -RSPM_CMD_PERF_SAMPLE = 7 -RSPM_CMD_PROF_START = 8 -RSPM_CMD_PROF_STOP = 9 -RSPM_CMD_FORCE_SAMPLE = 10 -RSPM_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_BASE_MODE' -CLKGATE_BASE_MODE__enumvalues = { - 0: 'MULT_8', - 1: 'MULT_16', -} -MULT_8 = 0 -MULT_16 = 1 -CLKGATE_BASE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CLKGATE_SM_MODE' -CLKGATE_SM_MODE__enumvalues = { - 0: 'ON_SEQ', - 1: 'OFF_SEQ', - 2: 'PROG_SEQ', - 3: 'READ_SEQ', - 4: 'SM_MODE_RESERVED', -} -ON_SEQ = 0 -OFF_SEQ = 1 -PROG_SEQ = 2 -READ_SEQ = 3 -SM_MODE_RESERVED = 4 -CLKGATE_SM_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_FOG_MODE' -SPI_FOG_MODE__enumvalues = { - 0: 'SPI_FOG_NONE', - 1: 'SPI_FOG_EXP', - 2: 'SPI_FOG_EXP2', - 3: 'SPI_FOG_LINEAR', -} -SPI_FOG_NONE = 0 -SPI_FOG_EXP = 1 -SPI_FOG_EXP2 = 2 -SPI_FOG_LINEAR = 3 -SPI_FOG_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_LB_WAVES_SELECT' -SPI_LB_WAVES_SELECT__enumvalues = { - 0: 'HS_GS', - 1: 'PS', - 2: 'CS_NA', - 3: 'SPI_LB_WAVES_RSVD', -} -HS_GS = 0 -PS = 1 -CS_NA = 2 -SPI_LB_WAVES_RSVD = 3 -SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PERFCNT_SEL' -SPI_PERFCNT_SEL__enumvalues = { - 1: 'SPI_PERF_GS_WINDOW_VALID', - 2: 'SPI_PERF_GS_BUSY', - 3: 'SPI_PERF_GS_CRAWLER_STALL', - 4: 'SPI_PERF_GS_EVENT_WAVE', - 5: 'SPI_PERF_GS_WAVE', - 6: 'SPI_PERF_GS_PERS_UPD_FULL0', - 7: 'SPI_PERF_GS_PERS_UPD_FULL1', - 8: 'SPI_PERF_GS_FIRST_SUBGRP', - 9: 'SPI_PERF_GS_HS_DEALLOC', - 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 11: 'SPI_PERF_GS_POS0_STALL', - 12: 'SPI_PERF_GS_POS1_STALL', - 13: 'SPI_PERF_GS_INDX0_STALL', - 14: 'SPI_PERF_GS_INDX1_STALL', - 15: 'SPI_PERF_GS_PWS_STALL', - 21: 'SPI_PERF_HS_WINDOW_VALID', - 22: 'SPI_PERF_HS_BUSY', - 23: 'SPI_PERF_HS_CRAWLER_STALL', - 24: 'SPI_PERF_HS_FIRST_WAVE', - 25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', - 26: 'SPI_PERF_HS_EVENT_WAVE', - 27: 'SPI_PERF_HS_WAVE', - 28: 'SPI_PERF_HS_PERS_UPD_FULL0', - 29: 'SPI_PERF_HS_PERS_UPD_FULL1', - 30: 'SPI_PERF_HS_PWS_STALL', - 37: 'SPI_PERF_CSGN_WINDOW_VALID', - 38: 'SPI_PERF_CSGN_BUSY', - 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', - 40: 'SPI_PERF_CSGN_CRAWLER_STALL', - 41: 'SPI_PERF_CSGN_EVENT_WAVE', - 42: 'SPI_PERF_CSGN_WAVE', - 43: 'SPI_PERF_CSGN_PWS_STALL', - 44: 'SPI_PERF_CSN_WINDOW_VALID', - 45: 'SPI_PERF_CSN_BUSY', - 46: 'SPI_PERF_CSN_NUM_THREADGROUPS', - 47: 'SPI_PERF_CSN_CRAWLER_STALL', - 48: 'SPI_PERF_CSN_EVENT_WAVE', - 49: 'SPI_PERF_CSN_WAVE', - 53: 'SPI_PERF_PS0_WINDOW_VALID', - 54: 'SPI_PERF_PS1_WINDOW_VALID', - 55: 'SPI_PERF_PS2_WINDOW_VALID', - 56: 'SPI_PERF_PS3_WINDOW_VALID', - 57: 'SPI_PERF_PS0_BUSY', - 58: 'SPI_PERF_PS1_BUSY', - 59: 'SPI_PERF_PS2_BUSY', - 60: 'SPI_PERF_PS3_BUSY', - 61: 'SPI_PERF_PS0_ACTIVE', - 62: 'SPI_PERF_PS1_ACTIVE', - 63: 'SPI_PERF_PS2_ACTIVE', - 64: 'SPI_PERF_PS3_ACTIVE', - 65: 'SPI_PERF_PS0_DEALLOC', - 66: 'SPI_PERF_PS1_DEALLOC', - 67: 'SPI_PERF_PS2_DEALLOC', - 68: 'SPI_PERF_PS3_DEALLOC', - 69: 'SPI_PERF_PS0_EVENT_WAVE', - 70: 'SPI_PERF_PS1_EVENT_WAVE', - 71: 'SPI_PERF_PS2_EVENT_WAVE', - 72: 'SPI_PERF_PS3_EVENT_WAVE', - 73: 'SPI_PERF_PS0_WAVE', - 74: 'SPI_PERF_PS1_WAVE', - 75: 'SPI_PERF_PS2_WAVE', - 76: 'SPI_PERF_PS3_WAVE', - 77: 'SPI_PERF_PS0_OPT_WAVE', - 78: 'SPI_PERF_PS1_OPT_WAVE', - 79: 'SPI_PERF_PS2_OPT_WAVE', - 80: 'SPI_PERF_PS3_OPT_WAVE', - 81: 'SPI_PERF_PS0_PRIM_BIN0', - 82: 'SPI_PERF_PS1_PRIM_BIN0', - 83: 'SPI_PERF_PS2_PRIM_BIN0', - 84: 'SPI_PERF_PS3_PRIM_BIN0', - 85: 'SPI_PERF_PS0_PRIM_BIN1', - 86: 'SPI_PERF_PS1_PRIM_BIN1', - 87: 'SPI_PERF_PS2_PRIM_BIN1', - 88: 'SPI_PERF_PS3_PRIM_BIN1', - 89: 'SPI_PERF_PS0_CRAWLER_STALL', - 90: 'SPI_PERF_PS1_CRAWLER_STALL', - 91: 'SPI_PERF_PS2_CRAWLER_STALL', - 92: 'SPI_PERF_PS3_CRAWLER_STALL', - 93: 'SPI_PERF_PS_PERS_UPD_FULL0', - 94: 'SPI_PERF_PS_PERS_UPD_FULL1', - 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', - 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', - 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', - 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', - 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', - 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', - 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', - 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', - 107: 'SPI_PERF_PS_PWS_STALL', - 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', - 142: 'SPI_PERF_RA_TASK_REQ_BIN3', - 143: 'SPI_PERF_RA_WR_CTL_FULL', - 144: 'SPI_PERF_RA_REQ_NO_ALLOC', - 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', - 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', - 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', - 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 150: 'SPI_PERF_RA_RES_STALL_PS', - 151: 'SPI_PERF_RA_RES_STALL_GS', - 152: 'SPI_PERF_RA_RES_STALL_HS', - 153: 'SPI_PERF_RA_RES_STALL_CSG', - 154: 'SPI_PERF_RA_RES_STALL_CSN', - 155: 'SPI_PERF_RA_TMP_STALL_PS', - 156: 'SPI_PERF_RA_TMP_STALL_GS', - 157: 'SPI_PERF_RA_TMP_STALL_HS', - 158: 'SPI_PERF_RA_TMP_STALL_CSG', - 159: 'SPI_PERF_RA_TMP_STALL_CSN', - 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', - 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', - 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', - 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', - 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', - 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', - 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', - 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', - 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 175: 'SPI_PERF_RA_BAR_CU_FULL_HS', - 176: 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 177: 'SPI_PERF_RA_BAR_CU_FULL_CSN', - 178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', - 179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', - 181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 182: 'SPI_PERF_RA_WVLIM_STALL_PS', - 183: 'SPI_PERF_RA_WVLIM_STALL_GS', - 184: 'SPI_PERF_RA_WVLIM_STALL_HS', - 185: 'SPI_PERF_RA_WVLIM_STALL_CSG', - 186: 'SPI_PERF_RA_WVLIM_STALL_CSN', - 187: 'SPI_PERF_RA_GS_LOCK', - 188: 'SPI_PERF_RA_HS_LOCK', - 189: 'SPI_PERF_RA_CSG_LOCK', - 190: 'SPI_PERF_RA_CSN_LOCK', - 191: 'SPI_PERF_RA_RSV_UPD', - 192: 'SPI_PERF_RA_PRE_ALLOC_STALL', - 193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', - 195: 'SPI_PERF_RA_WVALLOC_STALL', - 196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', - 200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 216: 'SPI_PERF_EXP_ARB_COL_CNT', - 217: 'SPI_PERF_EXP_ARB_POS_CNT', - 218: 'SPI_PERF_EXP_ARB_GDS_CNT', - 219: 'SPI_PERF_EXP_ARB_IDX_CNT', - 220: 'SPI_PERF_EXP_WITH_CONFLICT', - 221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 222: 'SPI_PERF_GS_EXP_DONE', - 223: 'SPI_PERF_PS_EXP_DONE', - 224: 'SPI_PERF_PS_EXP_ARB_CONFLICT', - 225: 'SPI_PERF_PS_EXP_ALLOC', - 226: 'SPI_PERF_PS0_WAVEID_STARVED', - 227: 'SPI_PERF_PS1_WAVEID_STARVED', - 228: 'SPI_PERF_PS2_WAVEID_STARVED', - 229: 'SPI_PERF_PS3_WAVEID_STARVED', - 230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', - 232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', - 233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', - 234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', - 254: 'SPI_PERF_EXPORT_SCB0_STALL', - 255: 'SPI_PERF_EXPORT_SCB1_STALL', - 256: 'SPI_PERF_EXPORT_SCB2_STALL', - 257: 'SPI_PERF_EXPORT_SCB3_STALL', - 258: 'SPI_PERF_EXPORT_DB0_STALL', - 259: 'SPI_PERF_EXPORT_DB1_STALL', - 260: 'SPI_PERF_EXPORT_DB2_STALL', - 261: 'SPI_PERF_EXPORT_DB3_STALL', - 262: 'SPI_PERF_EXPORT_DB4_STALL', - 263: 'SPI_PERF_EXPORT_DB5_STALL', - 264: 'SPI_PERF_EXPORT_DB6_STALL', - 265: 'SPI_PERF_EXPORT_DB7_STALL', - 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', - 268: 'SPI_PERF_SWC_PS_WR', - 269: 'SPI_PERF_SWC_GS_WR', - 270: 'SPI_PERF_SWC_HS_WR', - 271: 'SPI_PERF_SWC_CSGN_WR', - 272: 'SPI_PERF_SWC_CSN_WR', - 273: 'SPI_PERF_VWC_PS_WR', - 274: 'SPI_PERF_VWC_ES_WR', - 275: 'SPI_PERF_VWC_GS_WR', - 276: 'SPI_PERF_VWC_LS_WR', - 277: 'SPI_PERF_VWC_HS_WR', - 278: 'SPI_PERF_VWC_CSGN_WR', - 279: 'SPI_PERF_VWC_CSN_WR', - 280: 'SPI_PERF_EXP_THROT_UPSTEP', - 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', - 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 283: 'SPI_PERF_BUSY', -} -SPI_PERF_GS_WINDOW_VALID = 1 -SPI_PERF_GS_BUSY = 2 -SPI_PERF_GS_CRAWLER_STALL = 3 -SPI_PERF_GS_EVENT_WAVE = 4 -SPI_PERF_GS_WAVE = 5 -SPI_PERF_GS_PERS_UPD_FULL0 = 6 -SPI_PERF_GS_PERS_UPD_FULL1 = 7 -SPI_PERF_GS_FIRST_SUBGRP = 8 -SPI_PERF_GS_HS_DEALLOC = 9 -SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 -SPI_PERF_GS_POS0_STALL = 11 -SPI_PERF_GS_POS1_STALL = 12 -SPI_PERF_GS_INDX0_STALL = 13 -SPI_PERF_GS_INDX1_STALL = 14 -SPI_PERF_GS_PWS_STALL = 15 -SPI_PERF_HS_WINDOW_VALID = 21 -SPI_PERF_HS_BUSY = 22 -SPI_PERF_HS_CRAWLER_STALL = 23 -SPI_PERF_HS_FIRST_WAVE = 24 -SPI_PERF_HS_OFFCHIP_LDS_STALL = 25 -SPI_PERF_HS_EVENT_WAVE = 26 -SPI_PERF_HS_WAVE = 27 -SPI_PERF_HS_PERS_UPD_FULL0 = 28 -SPI_PERF_HS_PERS_UPD_FULL1 = 29 -SPI_PERF_HS_PWS_STALL = 30 -SPI_PERF_CSGN_WINDOW_VALID = 37 -SPI_PERF_CSGN_BUSY = 38 -SPI_PERF_CSGN_NUM_THREADGROUPS = 39 -SPI_PERF_CSGN_CRAWLER_STALL = 40 -SPI_PERF_CSGN_EVENT_WAVE = 41 -SPI_PERF_CSGN_WAVE = 42 -SPI_PERF_CSGN_PWS_STALL = 43 -SPI_PERF_CSN_WINDOW_VALID = 44 -SPI_PERF_CSN_BUSY = 45 -SPI_PERF_CSN_NUM_THREADGROUPS = 46 -SPI_PERF_CSN_CRAWLER_STALL = 47 -SPI_PERF_CSN_EVENT_WAVE = 48 -SPI_PERF_CSN_WAVE = 49 -SPI_PERF_PS0_WINDOW_VALID = 53 -SPI_PERF_PS1_WINDOW_VALID = 54 -SPI_PERF_PS2_WINDOW_VALID = 55 -SPI_PERF_PS3_WINDOW_VALID = 56 -SPI_PERF_PS0_BUSY = 57 -SPI_PERF_PS1_BUSY = 58 -SPI_PERF_PS2_BUSY = 59 -SPI_PERF_PS3_BUSY = 60 -SPI_PERF_PS0_ACTIVE = 61 -SPI_PERF_PS1_ACTIVE = 62 -SPI_PERF_PS2_ACTIVE = 63 -SPI_PERF_PS3_ACTIVE = 64 -SPI_PERF_PS0_DEALLOC = 65 -SPI_PERF_PS1_DEALLOC = 66 -SPI_PERF_PS2_DEALLOC = 67 -SPI_PERF_PS3_DEALLOC = 68 -SPI_PERF_PS0_EVENT_WAVE = 69 -SPI_PERF_PS1_EVENT_WAVE = 70 -SPI_PERF_PS2_EVENT_WAVE = 71 -SPI_PERF_PS3_EVENT_WAVE = 72 -SPI_PERF_PS0_WAVE = 73 -SPI_PERF_PS1_WAVE = 74 -SPI_PERF_PS2_WAVE = 75 -SPI_PERF_PS3_WAVE = 76 -SPI_PERF_PS0_OPT_WAVE = 77 -SPI_PERF_PS1_OPT_WAVE = 78 -SPI_PERF_PS2_OPT_WAVE = 79 -SPI_PERF_PS3_OPT_WAVE = 80 -SPI_PERF_PS0_PRIM_BIN0 = 81 -SPI_PERF_PS1_PRIM_BIN0 = 82 -SPI_PERF_PS2_PRIM_BIN0 = 83 -SPI_PERF_PS3_PRIM_BIN0 = 84 -SPI_PERF_PS0_PRIM_BIN1 = 85 -SPI_PERF_PS1_PRIM_BIN1 = 86 -SPI_PERF_PS2_PRIM_BIN1 = 87 -SPI_PERF_PS3_PRIM_BIN1 = 88 -SPI_PERF_PS0_CRAWLER_STALL = 89 -SPI_PERF_PS1_CRAWLER_STALL = 90 -SPI_PERF_PS2_CRAWLER_STALL = 91 -SPI_PERF_PS3_CRAWLER_STALL = 92 -SPI_PERF_PS_PERS_UPD_FULL0 = 93 -SPI_PERF_PS_PERS_UPD_FULL1 = 94 -SPI_PERF_PS0_2_WAVE_GROUPS = 95 -SPI_PERF_PS1_2_WAVE_GROUPS = 96 -SPI_PERF_PS2_2_WAVE_GROUPS = 97 -SPI_PERF_PS3_2_WAVE_GROUPS = 98 -SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 -SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 -SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 -SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 -SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 -SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 -SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 -SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 -SPI_PERF_PS_PWS_STALL = 107 -SPI_PERF_RA_PIPE_REQ_BIN2 = 141 -SPI_PERF_RA_TASK_REQ_BIN3 = 142 -SPI_PERF_RA_WR_CTL_FULL = 143 -SPI_PERF_RA_REQ_NO_ALLOC = 144 -SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 -SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 -SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 -SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 -SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 -SPI_PERF_RA_RES_STALL_PS = 150 -SPI_PERF_RA_RES_STALL_GS = 151 -SPI_PERF_RA_RES_STALL_HS = 152 -SPI_PERF_RA_RES_STALL_CSG = 153 -SPI_PERF_RA_RES_STALL_CSN = 154 -SPI_PERF_RA_TMP_STALL_PS = 155 -SPI_PERF_RA_TMP_STALL_GS = 156 -SPI_PERF_RA_TMP_STALL_HS = 157 -SPI_PERF_RA_TMP_STALL_CSG = 158 -SPI_PERF_RA_TMP_STALL_CSN = 159 -SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 -SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 -SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 -SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 -SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 -SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 -SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 -SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 -SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 -SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 -SPI_PERF_RA_LDS_CU_FULL_PS = 170 -SPI_PERF_RA_LDS_CU_FULL_HS = 171 -SPI_PERF_RA_LDS_CU_FULL_GS = 172 -SPI_PERF_RA_LDS_CU_FULL_CSG = 173 -SPI_PERF_RA_LDS_CU_FULL_CSN = 174 -SPI_PERF_RA_BAR_CU_FULL_HS = 175 -SPI_PERF_RA_BAR_CU_FULL_CSG = 176 -SPI_PERF_RA_BAR_CU_FULL_CSN = 177 -SPI_PERF_RA_BULKY_CU_FULL_CSG = 178 -SPI_PERF_RA_BULKY_CU_FULL_CSN = 179 -SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180 -SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181 -SPI_PERF_RA_WVLIM_STALL_PS = 182 -SPI_PERF_RA_WVLIM_STALL_GS = 183 -SPI_PERF_RA_WVLIM_STALL_HS = 184 -SPI_PERF_RA_WVLIM_STALL_CSG = 185 -SPI_PERF_RA_WVLIM_STALL_CSN = 186 -SPI_PERF_RA_GS_LOCK = 187 -SPI_PERF_RA_HS_LOCK = 188 -SPI_PERF_RA_CSG_LOCK = 189 -SPI_PERF_RA_CSN_LOCK = 190 -SPI_PERF_RA_RSV_UPD = 191 -SPI_PERF_RA_PRE_ALLOC_STALL = 192 -SPI_PERF_RA_GFX_UNDER_TUNNEL = 193 -SPI_PERF_RA_CSC_UNDER_TUNNEL = 194 -SPI_PERF_RA_WVALLOC_STALL = 195 -SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196 -SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197 -SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198 -SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199 -SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200 -SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201 -SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202 -SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203 -SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204 -SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205 -SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206 -SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211 -SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212 -SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213 -SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214 -SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215 -SPI_PERF_EXP_ARB_COL_CNT = 216 -SPI_PERF_EXP_ARB_POS_CNT = 217 -SPI_PERF_EXP_ARB_GDS_CNT = 218 -SPI_PERF_EXP_ARB_IDX_CNT = 219 -SPI_PERF_EXP_WITH_CONFLICT = 220 -SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221 -SPI_PERF_GS_EXP_DONE = 222 -SPI_PERF_PS_EXP_DONE = 223 -SPI_PERF_PS_EXP_ARB_CONFLICT = 224 -SPI_PERF_PS_EXP_ALLOC = 225 -SPI_PERF_PS0_WAVEID_STARVED = 226 -SPI_PERF_PS1_WAVEID_STARVED = 227 -SPI_PERF_PS2_WAVEID_STARVED = 228 -SPI_PERF_PS3_WAVEID_STARVED = 229 -SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230 -SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231 -SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232 -SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233 -SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234 -SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235 -SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236 -SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237 -SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238 -SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239 -SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240 -SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241 -SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242 -SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243 -SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244 -SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245 -SPI_PERF_NUM_EXPGRANT_EXPORTS = 246 -SPI_PERF_PIX_ALLOC_PEND_CNT = 253 -SPI_PERF_EXPORT_SCB0_STALL = 254 -SPI_PERF_EXPORT_SCB1_STALL = 255 -SPI_PERF_EXPORT_SCB2_STALL = 256 -SPI_PERF_EXPORT_SCB3_STALL = 257 -SPI_PERF_EXPORT_DB0_STALL = 258 -SPI_PERF_EXPORT_DB1_STALL = 259 -SPI_PERF_EXPORT_DB2_STALL = 260 -SPI_PERF_EXPORT_DB3_STALL = 261 -SPI_PERF_EXPORT_DB4_STALL = 262 -SPI_PERF_EXPORT_DB5_STALL = 263 -SPI_PERF_EXPORT_DB6_STALL = 264 -SPI_PERF_EXPORT_DB7_STALL = 265 -SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 -SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 -SPI_PERF_SWC_PS_WR = 268 -SPI_PERF_SWC_GS_WR = 269 -SPI_PERF_SWC_HS_WR = 270 -SPI_PERF_SWC_CSGN_WR = 271 -SPI_PERF_SWC_CSN_WR = 272 -SPI_PERF_VWC_PS_WR = 273 -SPI_PERF_VWC_ES_WR = 274 -SPI_PERF_VWC_GS_WR = 275 -SPI_PERF_VWC_LS_WR = 276 -SPI_PERF_VWC_HS_WR = 277 -SPI_PERF_VWC_CSGN_WR = 278 -SPI_PERF_VWC_CSN_WR = 279 -SPI_PERF_EXP_THROT_UPSTEP = 280 -SPI_PERF_EXP_THROT_DOWNSTEP = 281 -SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 -SPI_PERF_BUSY = 283 -SPI_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' -SPI_PNT_SPRITE_OVERRIDE__enumvalues = { - 0: 'SPI_PNT_SPRITE_SEL_0', - 1: 'SPI_PNT_SPRITE_SEL_1', - 2: 'SPI_PNT_SPRITE_SEL_S', - 3: 'SPI_PNT_SPRITE_SEL_T', - 4: 'SPI_PNT_SPRITE_SEL_NONE', -} -SPI_PNT_SPRITE_SEL_0 = 0 -SPI_PNT_SPRITE_SEL_1 = 1 -SPI_PNT_SPRITE_SEL_S = 2 -SPI_PNT_SPRITE_SEL_T = 3 -SPI_PNT_SPRITE_SEL_NONE = 4 -SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' -SPI_PS_LDS_GROUP_SIZE__enumvalues = { - 0: 'SPI_PS_LDS_GROUP_1', - 1: 'SPI_PS_LDS_GROUP_2', - 2: 'SPI_PS_LDS_GROUP_4', -} -SPI_PS_LDS_GROUP_1 = 0 -SPI_PS_LDS_GROUP_2 = 1 -SPI_PS_LDS_GROUP_4 = 2 -SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SAMPLE_CNTL' -SPI_SAMPLE_CNTL__enumvalues = { - 0: 'CENTROIDS_ONLY', - 1: 'CENTERS_ONLY', - 2: 'CENTROIDS_AND_CENTERS', - 3: 'UNDEF', -} -CENTROIDS_ONLY = 0 -CENTERS_ONLY = 1 -CENTROIDS_AND_CENTERS = 2 -UNDEF = 3 -SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_EX_FORMAT' -SPI_SHADER_EX_FORMAT__enumvalues = { - 0: 'SPI_SHADER_ZERO', - 1: 'SPI_SHADER_32_R', - 2: 'SPI_SHADER_32_GR', - 3: 'SPI_SHADER_32_AR', - 4: 'SPI_SHADER_FP16_ABGR', - 5: 'SPI_SHADER_UNORM16_ABGR', - 6: 'SPI_SHADER_SNORM16_ABGR', - 7: 'SPI_SHADER_UINT16_ABGR', - 8: 'SPI_SHADER_SINT16_ABGR', - 9: 'SPI_SHADER_32_ABGR', -} -SPI_SHADER_ZERO = 0 -SPI_SHADER_32_R = 1 -SPI_SHADER_32_GR = 2 -SPI_SHADER_32_AR = 3 -SPI_SHADER_FP16_ABGR = 4 -SPI_SHADER_UNORM16_ABGR = 5 -SPI_SHADER_SNORM16_ABGR = 6 -SPI_SHADER_UINT16_ABGR = 7 -SPI_SHADER_SINT16_ABGR = 8 -SPI_SHADER_32_ABGR = 9 -SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SPI_SHADER_FORMAT' -SPI_SHADER_FORMAT__enumvalues = { - 0: 'SPI_SHADER_NONE', - 1: 'SPI_SHADER_1COMP', - 2: 'SPI_SHADER_2COMP', - 3: 'SPI_SHADER_4COMPRESS', - 4: 'SPI_SHADER_4COMP', -} -SPI_SHADER_NONE = 0 -SPI_SHADER_1COMP = 1 -SPI_SHADER_2COMP = 2 -SPI_SHADER_4COMPRESS = 3 -SPI_SHADER_4COMP = 4 -SPI_SHADER_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ADDRESS_MODE' -SH_MEM_ADDRESS_MODE__enumvalues = { - 0: 'SH_MEM_ADDRESS_MODE_64', - 1: 'SH_MEM_ADDRESS_MODE_32', -} -SH_MEM_ADDRESS_MODE_64 = 0 -SH_MEM_ADDRESS_MODE_32 = 1 -SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SH_MEM_ALIGNMENT_MODE' -SH_MEM_ALIGNMENT_MODE__enumvalues = { - 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', - 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', - 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', -} -SH_MEM_ALIGNMENT_MODE_DWORD = 0 -SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 -SH_MEM_ALIGNMENT_MODE_STRICT = 2 -SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 -SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQG_PERF_SEL' -SQG_PERF_SEL__enumvalues = { - 0: 'SQG_PERF_SEL_NONE', - 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', - 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', - 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', - 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 6: 'SQG_PERF_SEL_TTRACE_REQS', - 7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 8: 'SQG_PERF_SEL_TTRACE_STALL', - 9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', - 10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', - 11: 'SQG_PERF_SEL_EVENTS', - 12: 'SQG_PERF_SEL_WAVES_RESTORED', - 13: 'SQG_PERF_SEL_WAVES_SAVED', - 14: 'SQG_PERF_SEL_ACCUM_PREV', - 15: 'SQG_PERF_SEL_CYCLES', - 16: 'SQG_PERF_SEL_BUSY_CYCLES', - 17: 'SQG_PERF_SEL_WAVE_CYCLES', - 18: 'SQG_PERF_SEL_MSG', - 19: 'SQG_PERF_SEL_MSG_INTERRUPT', - 20: 'SQG_PERF_SEL_WAVES', - 21: 'SQG_PERF_SEL_WAVES_32', - 22: 'SQG_PERF_SEL_WAVES_64', - 23: 'SQG_PERF_SEL_LEVEL_WAVES', - 24: 'SQG_PERF_SEL_ITEMS', - 25: 'SQG_PERF_SEL_WAVE32_ITEMS', - 26: 'SQG_PERF_SEL_WAVE64_ITEMS', - 27: 'SQG_PERF_SEL_PS_QUADS', - 28: 'SQG_PERF_SEL_WAVES_EQ_64', - 29: 'SQG_PERF_SEL_WAVES_EQ_32', - 30: 'SQG_PERF_SEL_WAVES_LT_64', - 31: 'SQG_PERF_SEL_WAVES_LT_48', - 32: 'SQG_PERF_SEL_WAVES_LT_32', - 33: 'SQG_PERF_SEL_WAVES_LT_16', - 34: 'SQG_PERF_SEL_DUMMY_LAST', -} -SQG_PERF_SEL_NONE = 0 -SQG_PERF_SEL_MSG_BUS_BUSY = 1 -SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 -SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 -SQG_PERF_SEL_EXP_BUS0_BUSY = 4 -SQG_PERF_SEL_EXP_BUS1_BUSY = 5 -SQG_PERF_SEL_TTRACE_REQS = 6 -SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7 -SQG_PERF_SEL_TTRACE_STALL = 8 -SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9 -SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10 -SQG_PERF_SEL_EVENTS = 11 -SQG_PERF_SEL_WAVES_RESTORED = 12 -SQG_PERF_SEL_WAVES_SAVED = 13 -SQG_PERF_SEL_ACCUM_PREV = 14 -SQG_PERF_SEL_CYCLES = 15 -SQG_PERF_SEL_BUSY_CYCLES = 16 -SQG_PERF_SEL_WAVE_CYCLES = 17 -SQG_PERF_SEL_MSG = 18 -SQG_PERF_SEL_MSG_INTERRUPT = 19 -SQG_PERF_SEL_WAVES = 20 -SQG_PERF_SEL_WAVES_32 = 21 -SQG_PERF_SEL_WAVES_64 = 22 -SQG_PERF_SEL_LEVEL_WAVES = 23 -SQG_PERF_SEL_ITEMS = 24 -SQG_PERF_SEL_WAVE32_ITEMS = 25 -SQG_PERF_SEL_WAVE64_ITEMS = 26 -SQG_PERF_SEL_PS_QUADS = 27 -SQG_PERF_SEL_WAVES_EQ_64 = 28 -SQG_PERF_SEL_WAVES_EQ_32 = 29 -SQG_PERF_SEL_WAVES_LT_64 = 30 -SQG_PERF_SEL_WAVES_LT_48 = 31 -SQG_PERF_SEL_WAVES_LT_32 = 32 -SQG_PERF_SEL_WAVES_LT_16 = 33 -SQG_PERF_SEL_DUMMY_LAST = 34 -SQG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_CAC_POWER_SEL' -SQ_CAC_POWER_SEL__enumvalues = { - 0: 'SQ_CAC_POWER_VALU', - 1: 'SQ_CAC_POWER_VALU0', - 2: 'SQ_CAC_POWER_VALU1', - 3: 'SQ_CAC_POWER_VALU2', - 4: 'SQ_CAC_POWER_GPR_RD', - 5: 'SQ_CAC_POWER_GPR_WR', - 6: 'SQ_CAC_POWER_LDS_BUSY', - 7: 'SQ_CAC_POWER_ALU_BUSY', - 8: 'SQ_CAC_POWER_TEX_BUSY', -} -SQ_CAC_POWER_VALU = 0 -SQ_CAC_POWER_VALU0 = 1 -SQ_CAC_POWER_VALU1 = 2 -SQ_CAC_POWER_VALU2 = 3 -SQ_CAC_POWER_GPR_RD = 4 -SQ_CAC_POWER_GPR_WR = 5 -SQ_CAC_POWER_LDS_BUSY = 6 -SQ_CAC_POWER_ALU_BUSY = 7 -SQ_CAC_POWER_TEX_BUSY = 8 -SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_EDC_INFO_SOURCE' -SQ_EDC_INFO_SOURCE__enumvalues = { - 0: 'SQ_EDC_INFO_SOURCE_INVALID', - 1: 'SQ_EDC_INFO_SOURCE_INST', - 2: 'SQ_EDC_INFO_SOURCE_SGPR', - 3: 'SQ_EDC_INFO_SOURCE_VGPR', - 4: 'SQ_EDC_INFO_SOURCE_LDS', - 5: 'SQ_EDC_INFO_SOURCE_GDS', - 6: 'SQ_EDC_INFO_SOURCE_TA', -} -SQ_EDC_INFO_SOURCE_INVALID = 0 -SQ_EDC_INFO_SOURCE_INST = 1 -SQ_EDC_INFO_SOURCE_SGPR = 2 -SQ_EDC_INFO_SOURCE_VGPR = 3 -SQ_EDC_INFO_SOURCE_LDS = 4 -SQ_EDC_INFO_SOURCE_GDS = 5 -SQ_EDC_INFO_SOURCE_TA = 6 -SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IBUF_ST' -SQ_IBUF_ST__enumvalues = { - 0: 'SQ_IBUF_IB_IDLE', - 1: 'SQ_IBUF_IB_INI_WAIT_GNT', - 2: 'SQ_IBUF_IB_INI_WAIT_DRET', - 3: 'SQ_IBUF_IB_LE_4DW', - 4: 'SQ_IBUF_IB_WAIT_DRET', - 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 6: 'SQ_IBUF_IB_DRET', - 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', -} -SQ_IBUF_IB_IDLE = 0 -SQ_IBUF_IB_INI_WAIT_GNT = 1 -SQ_IBUF_IB_INI_WAIT_DRET = 2 -SQ_IBUF_IB_LE_4DW = 3 -SQ_IBUF_IB_WAIT_DRET = 4 -SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 -SQ_IBUF_IB_DRET = 6 -SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 -SQ_IBUF_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IMG_FILTER_TYPE' -SQ_IMG_FILTER_TYPE__enumvalues = { - 0: 'SQ_IMG_FILTER_MODE_BLEND', - 1: 'SQ_IMG_FILTER_MODE_MIN', - 2: 'SQ_IMG_FILTER_MODE_MAX', -} -SQ_IMG_FILTER_MODE_BLEND = 0 -SQ_IMG_FILTER_MODE_MIN = 1 -SQ_IMG_FILTER_MODE_MAX = 2 -SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_CMD' -SQ_IND_CMD_CMD__enumvalues = { - 0: 'SQ_IND_CMD_CMD_NULL', - 1: 'SQ_IND_CMD_CMD_SETHALT', - 2: 'SQ_IND_CMD_CMD_SAVECTX', - 3: 'SQ_IND_CMD_CMD_KILL', - 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', - 5: 'SQ_IND_CMD_CMD_TRAP', - 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 7: 'SQ_IND_CMD_CMD_SETFATALHALT', - 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', -} -SQ_IND_CMD_CMD_NULL = 0 -SQ_IND_CMD_CMD_SETHALT = 1 -SQ_IND_CMD_CMD_SAVECTX = 2 -SQ_IND_CMD_CMD_KILL = 3 -SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 -SQ_IND_CMD_CMD_TRAP = 5 -SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 -SQ_IND_CMD_CMD_SETFATALHALT = 7 -SQ_IND_CMD_CMD_SINGLE_STEP = 8 -SQ_IND_CMD_CMD = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_IND_CMD_MODE' -SQ_IND_CMD_MODE__enumvalues = { - 0: 'SQ_IND_CMD_MODE_SINGLE', - 1: 'SQ_IND_CMD_MODE_BROADCAST', - 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', - 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', -} -SQ_IND_CMD_MODE_SINGLE = 0 -SQ_IND_CMD_MODE_BROADCAST = 1 -SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 -SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 -SQ_IND_CMD_MODE_BROADCAST_ME = 4 -SQ_IND_CMD_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_STR_ST' -SQ_INST_STR_ST__enumvalues = { - 0: 'SQ_INST_STR_IB_WAVE_NORML', - 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', - 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', -} -SQ_INST_STR_IB_WAVE_NORML = 0 -SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 -SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 -SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 -SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 -SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 -SQ_INST_STR_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_INST_TYPE' -SQ_INST_TYPE__enumvalues = { - 0: 'SQ_INST_TYPE_VALU', - 1: 'SQ_INST_TYPE_SCALAR', - 2: 'SQ_INST_TYPE_TEX', - 3: 'SQ_INST_TYPE_LDS', - 4: 'SQ_INST_TYPE_LDS_DIRECT', - 5: 'SQ_INST_TYPE_EXP', - 6: 'SQ_INST_TYPE_MSG', - 7: 'SQ_INST_TYPE_BARRIER', - 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', - 9: 'SQ_INST_TYPE_BRANCH_TAKEN', - 10: 'SQ_INST_TYPE_JUMP', - 11: 'SQ_INST_TYPE_OTHER', - 12: 'SQ_INST_TYPE_NONE', -} -SQ_INST_TYPE_VALU = 0 -SQ_INST_TYPE_SCALAR = 1 -SQ_INST_TYPE_TEX = 2 -SQ_INST_TYPE_LDS = 3 -SQ_INST_TYPE_LDS_DIRECT = 4 -SQ_INST_TYPE_EXP = 5 -SQ_INST_TYPE_MSG = 6 -SQ_INST_TYPE_BARRIER = 7 -SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 -SQ_INST_TYPE_BRANCH_TAKEN = 9 -SQ_INST_TYPE_JUMP = 10 -SQ_INST_TYPE_OTHER = 11 -SQ_INST_TYPE_NONE = 12 -SQ_INST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_LLC_CTL' -SQ_LLC_CTL__enumvalues = { - 0: 'SQ_LLC_0', - 1: 'SQ_LLC_1', - 2: 'SQ_LLC_RSVD_2', - 3: 'SQ_LLC_BYPASS', -} -SQ_LLC_0 = 0 -SQ_LLC_1 = 1 -SQ_LLC_RSVD_2 = 2 -SQ_LLC_BYPASS = 3 -SQ_LLC_CTL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_NO_INST_ISSUE' -SQ_NO_INST_ISSUE__enumvalues = { - 0: 'SQ_NO_INST_ISSUE_NO_INSTS', - 1: 'SQ_NO_INST_ISSUE_ALU_DEP', - 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', - 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', - 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', - 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', - 6: 'SQ_NO_INST_ISSUE_OTHER', -} -SQ_NO_INST_ISSUE_NO_INSTS = 0 -SQ_NO_INST_ISSUE_ALU_DEP = 1 -SQ_NO_INST_ISSUE_S_WAITCNT = 2 -SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 -SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 -SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 -SQ_NO_INST_ISSUE_OTHER = 6 -SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_OOB_SELECT' -SQ_OOB_SELECT__enumvalues = { - 0: 'SQ_OOB_INDEX_AND_OFFSET', - 1: 'SQ_OOB_INDEX_ONLY', - 2: 'SQ_OOB_NUM_RECORDS_0', - 3: 'SQ_OOB_COMPLETE', -} -SQ_OOB_INDEX_AND_OFFSET = 0 -SQ_OOB_INDEX_ONLY = 1 -SQ_OOB_NUM_RECORDS_0 = 2 -SQ_OOB_COMPLETE = 3 -SQ_OOB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_PERF_SEL' -SQ_PERF_SEL__enumvalues = { - 0: 'SQ_PERF_SEL_NONE', - 1: 'SQ_PERF_SEL_ACCUM_PREV', - 2: 'SQ_PERF_SEL_CYCLES', - 3: 'SQ_PERF_SEL_BUSY_CYCLES', - 4: 'SQ_PERF_SEL_WAVES', - 5: 'SQ_PERF_SEL_WAVES_32', - 6: 'SQ_PERF_SEL_WAVES_64', - 7: 'SQ_PERF_SEL_LEVEL_WAVES', - 8: 'SQ_PERF_SEL_ITEMS', - 9: 'SQ_PERF_SEL_WAVE32_ITEMS', - 10: 'SQ_PERF_SEL_WAVE64_ITEMS', - 11: 'SQ_PERF_SEL_PS_QUADS', - 12: 'SQ_PERF_SEL_EVENTS', - 13: 'SQ_PERF_SEL_WAVES_EQ_32', - 14: 'SQ_PERF_SEL_WAVES_EQ_64', - 15: 'SQ_PERF_SEL_WAVES_LT_64', - 16: 'SQ_PERF_SEL_WAVES_LT_48', - 17: 'SQ_PERF_SEL_WAVES_LT_32', - 18: 'SQ_PERF_SEL_WAVES_LT_16', - 19: 'SQ_PERF_SEL_WAVES_RESTORED', - 20: 'SQ_PERF_SEL_WAVES_SAVED', - 21: 'SQ_PERF_SEL_MSG', - 22: 'SQ_PERF_SEL_MSG_INTERRUPT', - 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 24: 'SQ_PERF_SEL_WAVE_CYCLES', - 25: 'SQ_PERF_SEL_WAVE_READY', - 26: 'SQ_PERF_SEL_WAIT_INST_ANY', - 27: 'SQ_PERF_SEL_WAIT_INST_VALU', - 28: 'SQ_PERF_SEL_WAIT_INST_SCA', - 29: 'SQ_PERF_SEL_WAIT_INST_LDS', - 30: 'SQ_PERF_SEL_WAIT_INST_TEX', - 31: 'SQ_PERF_SEL_WAIT_INST_FLAT', - 32: 'SQ_PERF_SEL_WAIT_INST_VMEM', - 33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', - 34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', - 35: 'SQ_PERF_SEL_WAIT_ANY', - 36: 'SQ_PERF_SEL_WAIT_CNT_ANY', - 37: 'SQ_PERF_SEL_WAIT_CNT_VMVS', - 38: 'SQ_PERF_SEL_WAIT_CNT_LGKM', - 39: 'SQ_PERF_SEL_WAIT_CNT_EXP', - 40: 'SQ_PERF_SEL_WAIT_TTRACE', - 41: 'SQ_PERF_SEL_WAIT_IFETCH', - 42: 'SQ_PERF_SEL_WAIT_BARRIER', - 43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', - 44: 'SQ_PERF_SEL_WAIT_SLEEP', - 45: 'SQ_PERF_SEL_WAIT_DELAY_ALU', - 46: 'SQ_PERF_SEL_WAIT_DEPCTR', - 47: 'SQ_PERF_SEL_WAIT_OTHER', - 48: 'SQ_PERF_SEL_INSTS_ALL', - 49: 'SQ_PERF_SEL_INSTS_BRANCH', - 50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', - 53: 'SQ_PERF_SEL_INSTS_EXP_GDS', - 54: 'SQ_PERF_SEL_INSTS_GDS', - 55: 'SQ_PERF_SEL_INSTS_EXP', - 56: 'SQ_PERF_SEL_INSTS_FLAT', - 57: 'SQ_PERF_SEL_INSTS_LDS', - 58: 'SQ_PERF_SEL_INSTS_SALU', - 59: 'SQ_PERF_SEL_INSTS_SMEM', - 60: 'SQ_PERF_SEL_INSTS_SMEM_NORM', - 61: 'SQ_PERF_SEL_INSTS_SENDMSG', - 62: 'SQ_PERF_SEL_INSTS_VALU', - 63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 65: 'SQ_PERF_SEL_INSTS_TEX', - 66: 'SQ_PERF_SEL_INSTS_TEX_LOAD', - 67: 'SQ_PERF_SEL_INSTS_TEX_STORE', - 68: 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 69: 'SQ_PERF_SEL_INSTS_INTERNAL', - 70: 'SQ_PERF_SEL_INSTS_WAVE32', - 71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', - 72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', - 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', - 81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 82: 'SQ_PERF_SEL_WAVE32_INSTS', - 83: 'SQ_PERF_SEL_WAVE64_INSTS', - 84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 86: 'SQ_PERF_SEL_INST_LEVEL_EXP', - 87: 'SQ_PERF_SEL_INST_LEVEL_GDS', - 88: 'SQ_PERF_SEL_INST_LEVEL_LDS', - 89: 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', - 92: 'SQ_PERF_SEL_IFETCH_REQS', - 93: 'SQ_PERF_SEL_IFETCH_LEVEL', - 94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 95: 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 99: 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 103: 'SQ_PERF_SEL_INST_CYCLES_VALU', - 104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 106: 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 109: 'SQ_PERF_SEL_INST_CYCLES_LDS', - 110: 'SQ_PERF_SEL_INST_CYCLES_TEX', - 111: 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', - 113: 'SQ_PERF_SEL_INST_CYCLES_EXP', - 114: 'SQ_PERF_SEL_INST_CYCLES_GDS', - 115: 'SQ_PERF_SEL_VALU_STARVE', - 116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', - 120: 'SQ_PERF_SEL_VMEM_BUS_STALL', - 121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 127: 'SQ_PERF_SEL_SALU_PIPE_STALL', - 128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 129: 'SQ_PERF_SEL_MSG_BUS_BUSY', - 130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', - 131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', - 132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 133: 'SQ_PERF_SEL_EXP_BUS0_BUSY', - 134: 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', - 136: 'SQ_PERF_SEL_USER0', - 137: 'SQ_PERF_SEL_USER1', - 138: 'SQ_PERF_SEL_USER2', - 139: 'SQ_PERF_SEL_USER3', - 140: 'SQ_PERF_SEL_USER4', - 141: 'SQ_PERF_SEL_USER5', - 142: 'SQ_PERF_SEL_USER6', - 143: 'SQ_PERF_SEL_USER7', - 144: 'SQ_PERF_SEL_USER8', - 145: 'SQ_PERF_SEL_USER9', - 146: 'SQ_PERF_SEL_USER10', - 147: 'SQ_PERF_SEL_USER11', - 148: 'SQ_PERF_SEL_USER12', - 149: 'SQ_PERF_SEL_USER13', - 150: 'SQ_PERF_SEL_USER14', - 151: 'SQ_PERF_SEL_USER15', - 152: 'SQ_PERF_SEL_USER_LEVEL0', - 153: 'SQ_PERF_SEL_USER_LEVEL1', - 154: 'SQ_PERF_SEL_USER_LEVEL2', - 155: 'SQ_PERF_SEL_USER_LEVEL3', - 156: 'SQ_PERF_SEL_USER_LEVEL4', - 157: 'SQ_PERF_SEL_USER_LEVEL5', - 158: 'SQ_PERF_SEL_USER_LEVEL6', - 159: 'SQ_PERF_SEL_USER_LEVEL7', - 160: 'SQ_PERF_SEL_USER_LEVEL8', - 161: 'SQ_PERF_SEL_USER_LEVEL9', - 162: 'SQ_PERF_SEL_USER_LEVEL10', - 163: 'SQ_PERF_SEL_USER_LEVEL11', - 164: 'SQ_PERF_SEL_USER_LEVEL12', - 165: 'SQ_PERF_SEL_USER_LEVEL13', - 166: 'SQ_PERF_SEL_USER_LEVEL14', - 167: 'SQ_PERF_SEL_USER_LEVEL15', - 168: 'SQ_PERF_SEL_VALU_RETURN_SDST', - 169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 170: 'SQ_PERF_SEL_INSTS_VALU_TRANS', - 171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', - 173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', - 174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', - 176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', - 177: 'SQ_PERF_SEL_OVERFLOW_PREV', - 178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', - 179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', - 181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 182: 'SQ_PERF_SEL_INSTS_VALU_DP', - 183: 'SQ_PERF_SEL_SP_CONST_CYCLES', - 184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', - 185: 'SQ_PERF_SEL_ITEMS_VALU', - 186: 'SQ_PERF_SEL_ITEMS_MAX_VALU', - 187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 188: 'SQ_PERF_SEL_DUMMY_END', - 255: 'SQ_PERF_SEL_DUMMY_LAST', - 256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', - 259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 262: 'SQC_PERF_SEL_LDS_ADDR_STALL', - 263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', - 264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', - 268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 269: 'SQC_PERF_SEL_ICACHE_REQ', - 270: 'SQC_PERF_SEL_ICACHE_HITS', - 271: 'SQC_PERF_SEL_ICACHE_MISSES', - 272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', - 273: 'SQC_PERF_SEL_ICACHE_INVAL_INST', - 274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', - 278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 282: 'SQC_PERF_SEL_TC_REQ', - 283: 'SQC_PERF_SEL_TC_INST_REQ', - 284: 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 285: 'SQC_PERF_SEL_TC_STALL', - 286: 'SQC_PERF_SEL_TC_STARVE', - 287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 293: 'SQC_PERF_SEL_DCACHE_REQ', - 294: 'SQC_PERF_SEL_DCACHE_HITS', - 295: 'SQC_PERF_SEL_DCACHE_MISSES', - 296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', - 297: 'SQC_PERF_SEL_DCACHE_INVAL_INST', - 298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 312: 'SQC_PERF_SEL_SQ_DCACHE_REQS', - 313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', - 314: 'SQC_PERF_SEL_TD_VGPR_BUSY', - 315: 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 317: 'SQC_PERF_SEL_ICACHE_GCR', - 318: 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 319: 'SQC_PERF_SEL_DCACHE_GCR', - 320: 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', - 322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', - 323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 324: 'SQC_PERF_SEL_DUMMY_LAST', - 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', - 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', - 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', - 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', - 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 474: 'SP_PERF_SEL_VALU_OPERAND', - 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', - 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', - 480: 'SP_PERF_SEL_VALU_STALL', - 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 487: 'SP_PERF_SEL_VGPR_VMEM_RD', - 488: 'SP_PERF_SEL_VGPR_EXP_RD', - 489: 'SP_PERF_SEL_VGPR_SPI_WR', - 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', - 491: 'SP_PERF_SEL_VGPR_WR', - 492: 'SP_PERF_SEL_VGPR_RD', - 493: 'SP_PERF_SEL_DUMMY_LAST', - 511: 'SQ_PERF_SEL_NONE2', -} -SQ_PERF_SEL_NONE = 0 -SQ_PERF_SEL_ACCUM_PREV = 1 -SQ_PERF_SEL_CYCLES = 2 -SQ_PERF_SEL_BUSY_CYCLES = 3 -SQ_PERF_SEL_WAVES = 4 -SQ_PERF_SEL_WAVES_32 = 5 -SQ_PERF_SEL_WAVES_64 = 6 -SQ_PERF_SEL_LEVEL_WAVES = 7 -SQ_PERF_SEL_ITEMS = 8 -SQ_PERF_SEL_WAVE32_ITEMS = 9 -SQ_PERF_SEL_WAVE64_ITEMS = 10 -SQ_PERF_SEL_PS_QUADS = 11 -SQ_PERF_SEL_EVENTS = 12 -SQ_PERF_SEL_WAVES_EQ_32 = 13 -SQ_PERF_SEL_WAVES_EQ_64 = 14 -SQ_PERF_SEL_WAVES_LT_64 = 15 -SQ_PERF_SEL_WAVES_LT_48 = 16 -SQ_PERF_SEL_WAVES_LT_32 = 17 -SQ_PERF_SEL_WAVES_LT_16 = 18 -SQ_PERF_SEL_WAVES_RESTORED = 19 -SQ_PERF_SEL_WAVES_SAVED = 20 -SQ_PERF_SEL_MSG = 21 -SQ_PERF_SEL_MSG_INTERRUPT = 22 -SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 -SQ_PERF_SEL_WAVE_CYCLES = 24 -SQ_PERF_SEL_WAVE_READY = 25 -SQ_PERF_SEL_WAIT_INST_ANY = 26 -SQ_PERF_SEL_WAIT_INST_VALU = 27 -SQ_PERF_SEL_WAIT_INST_SCA = 28 -SQ_PERF_SEL_WAIT_INST_LDS = 29 -SQ_PERF_SEL_WAIT_INST_TEX = 30 -SQ_PERF_SEL_WAIT_INST_FLAT = 31 -SQ_PERF_SEL_WAIT_INST_VMEM = 32 -SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33 -SQ_PERF_SEL_WAIT_INST_BR_MSG = 34 -SQ_PERF_SEL_WAIT_ANY = 35 -SQ_PERF_SEL_WAIT_CNT_ANY = 36 -SQ_PERF_SEL_WAIT_CNT_VMVS = 37 -SQ_PERF_SEL_WAIT_CNT_LGKM = 38 -SQ_PERF_SEL_WAIT_CNT_EXP = 39 -SQ_PERF_SEL_WAIT_TTRACE = 40 -SQ_PERF_SEL_WAIT_IFETCH = 41 -SQ_PERF_SEL_WAIT_BARRIER = 42 -SQ_PERF_SEL_WAIT_EXP_ALLOC = 43 -SQ_PERF_SEL_WAIT_SLEEP = 44 -SQ_PERF_SEL_WAIT_DELAY_ALU = 45 -SQ_PERF_SEL_WAIT_DEPCTR = 46 -SQ_PERF_SEL_WAIT_OTHER = 47 -SQ_PERF_SEL_INSTS_ALL = 48 -SQ_PERF_SEL_INSTS_BRANCH = 49 -SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51 -SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52 -SQ_PERF_SEL_INSTS_EXP_GDS = 53 -SQ_PERF_SEL_INSTS_GDS = 54 -SQ_PERF_SEL_INSTS_EXP = 55 -SQ_PERF_SEL_INSTS_FLAT = 56 -SQ_PERF_SEL_INSTS_LDS = 57 -SQ_PERF_SEL_INSTS_SALU = 58 -SQ_PERF_SEL_INSTS_SMEM = 59 -SQ_PERF_SEL_INSTS_SMEM_NORM = 60 -SQ_PERF_SEL_INSTS_SENDMSG = 61 -SQ_PERF_SEL_INSTS_VALU = 62 -SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63 -SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64 -SQ_PERF_SEL_INSTS_TEX = 65 -SQ_PERF_SEL_INSTS_TEX_LOAD = 66 -SQ_PERF_SEL_INSTS_TEX_STORE = 67 -SQ_PERF_SEL_INSTS_DELAY_ALU = 68 -SQ_PERF_SEL_INSTS_INTERNAL = 69 -SQ_PERF_SEL_INSTS_WAVE32 = 70 -SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71 -SQ_PERF_SEL_INSTS_WAVE32_LDS = 72 -SQ_PERF_SEL_INSTS_WAVE32_VALU = 73 -SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74 -SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75 -SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76 -SQ_PERF_SEL_INSTS_WAVE32_TEX = 77 -SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78 -SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79 -SQ_PERF_SEL_ITEM_CYCLES_VALU = 80 -SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81 -SQ_PERF_SEL_WAVE32_INSTS = 82 -SQ_PERF_SEL_WAVE64_INSTS = 83 -SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84 -SQ_PERF_SEL_WAVE64_HALF_SKIP = 85 -SQ_PERF_SEL_INST_LEVEL_EXP = 86 -SQ_PERF_SEL_INST_LEVEL_GDS = 87 -SQ_PERF_SEL_INST_LEVEL_LDS = 88 -SQ_PERF_SEL_INST_LEVEL_SMEM = 89 -SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90 -SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91 -SQ_PERF_SEL_IFETCH_REQS = 92 -SQ_PERF_SEL_IFETCH_LEVEL = 93 -SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94 -SQ_PERF_SEL_VALU_SGATHER_STALL = 95 -SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96 -SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97 -SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98 -SQ_PERF_SEL_SALU_SGATHER_STALL = 99 -SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100 -SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101 -SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102 -SQ_PERF_SEL_INST_CYCLES_VALU = 103 -SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104 -SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105 -SQ_PERF_SEL_INST_CYCLES_VMEM = 106 -SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107 -SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108 -SQ_PERF_SEL_INST_CYCLES_LDS = 109 -SQ_PERF_SEL_INST_CYCLES_TEX = 110 -SQ_PERF_SEL_INST_CYCLES_FLAT = 111 -SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112 -SQ_PERF_SEL_INST_CYCLES_EXP = 113 -SQ_PERF_SEL_INST_CYCLES_GDS = 114 -SQ_PERF_SEL_VALU_STARVE = 115 -SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116 -SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117 -SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118 -SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119 -SQ_PERF_SEL_VMEM_BUS_STALL = 120 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121 -SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123 -SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124 -SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125 -SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126 -SQ_PERF_SEL_SALU_PIPE_STALL = 127 -SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128 -SQ_PERF_SEL_MSG_BUS_BUSY = 129 -SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130 -SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131 -SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132 -SQ_PERF_SEL_EXP_BUS0_BUSY = 133 -SQ_PERF_SEL_EXP_BUS1_BUSY = 134 -SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135 -SQ_PERF_SEL_USER0 = 136 -SQ_PERF_SEL_USER1 = 137 -SQ_PERF_SEL_USER2 = 138 -SQ_PERF_SEL_USER3 = 139 -SQ_PERF_SEL_USER4 = 140 -SQ_PERF_SEL_USER5 = 141 -SQ_PERF_SEL_USER6 = 142 -SQ_PERF_SEL_USER7 = 143 -SQ_PERF_SEL_USER8 = 144 -SQ_PERF_SEL_USER9 = 145 -SQ_PERF_SEL_USER10 = 146 -SQ_PERF_SEL_USER11 = 147 -SQ_PERF_SEL_USER12 = 148 -SQ_PERF_SEL_USER13 = 149 -SQ_PERF_SEL_USER14 = 150 -SQ_PERF_SEL_USER15 = 151 -SQ_PERF_SEL_USER_LEVEL0 = 152 -SQ_PERF_SEL_USER_LEVEL1 = 153 -SQ_PERF_SEL_USER_LEVEL2 = 154 -SQ_PERF_SEL_USER_LEVEL3 = 155 -SQ_PERF_SEL_USER_LEVEL4 = 156 -SQ_PERF_SEL_USER_LEVEL5 = 157 -SQ_PERF_SEL_USER_LEVEL6 = 158 -SQ_PERF_SEL_USER_LEVEL7 = 159 -SQ_PERF_SEL_USER_LEVEL8 = 160 -SQ_PERF_SEL_USER_LEVEL9 = 161 -SQ_PERF_SEL_USER_LEVEL10 = 162 -SQ_PERF_SEL_USER_LEVEL11 = 163 -SQ_PERF_SEL_USER_LEVEL12 = 164 -SQ_PERF_SEL_USER_LEVEL13 = 165 -SQ_PERF_SEL_USER_LEVEL14 = 166 -SQ_PERF_SEL_USER_LEVEL15 = 167 -SQ_PERF_SEL_VALU_RETURN_SDST = 168 -SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169 -SQ_PERF_SEL_INSTS_VALU_TRANS = 170 -SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171 -SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172 -SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173 -SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174 -SQ_PERF_SEL_INSTS_VALU_VINTERP = 175 -SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176 -SQ_PERF_SEL_OVERFLOW_PREV = 177 -SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178 -SQ_PERF_SEL_INSTS_VALU_1_PASS = 179 -SQ_PERF_SEL_INSTS_VALU_2_PASS = 180 -SQ_PERF_SEL_INSTS_VALU_4_PASS = 181 -SQ_PERF_SEL_INSTS_VALU_DP = 182 -SQ_PERF_SEL_SP_CONST_CYCLES = 183 -SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184 -SQ_PERF_SEL_ITEMS_VALU = 185 -SQ_PERF_SEL_ITEMS_MAX_VALU = 186 -SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187 -SQ_PERF_SEL_DUMMY_END = 188 -SQ_PERF_SEL_DUMMY_LAST = 255 -SQC_PERF_SEL_LDS_BANK_CONFLICT = 256 -SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257 -SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258 -SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259 -SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260 -SQC_PERF_SEL_LDS_IDX_ACTIVE = 261 -SQC_PERF_SEL_LDS_ADDR_STALL = 262 -SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263 -SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264 -SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265 -SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266 -SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267 -SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268 -SQC_PERF_SEL_ICACHE_REQ = 269 -SQC_PERF_SEL_ICACHE_HITS = 270 -SQC_PERF_SEL_ICACHE_MISSES = 271 -SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272 -SQC_PERF_SEL_ICACHE_INVAL_INST = 273 -SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274 -SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275 -SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276 -SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277 -SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278 -SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279 -SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280 -SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281 -SQC_PERF_SEL_TC_REQ = 282 -SQC_PERF_SEL_TC_INST_REQ = 283 -SQC_PERF_SEL_TC_DATA_READ_REQ = 284 -SQC_PERF_SEL_TC_STALL = 285 -SQC_PERF_SEL_TC_STARVE = 286 -SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287 -SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288 -SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289 -SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290 -SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291 -SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292 -SQC_PERF_SEL_DCACHE_REQ = 293 -SQC_PERF_SEL_DCACHE_HITS = 294 -SQC_PERF_SEL_DCACHE_MISSES = 295 -SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296 -SQC_PERF_SEL_DCACHE_INVAL_INST = 297 -SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298 -SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299 -SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300 -SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301 -SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302 -SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303 -SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304 -SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305 -SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306 -SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307 -SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308 -SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309 -SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310 -SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311 -SQC_PERF_SEL_SQ_DCACHE_REQS = 312 -SQC_PERF_SEL_DCACHE_FLAT_REQ = 313 -SQC_PERF_SEL_TD_VGPR_BUSY = 314 -SQC_PERF_SEL_LDS_VGPR_BUSY = 315 -SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316 -SQC_PERF_SEL_ICACHE_GCR = 317 -SQC_PERF_SEL_ICACHE_GCR_HITS = 318 -SQC_PERF_SEL_DCACHE_GCR = 319 -SQC_PERF_SEL_DCACHE_GCR_HITS = 320 -SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321 -SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322 -SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323 -SQC_PERF_SEL_DUMMY_LAST = 324 -SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 -SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 -SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 -SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 -SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 -SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 -SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 -SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 -SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 -SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 -SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 -SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 -SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 -SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 -SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 -SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 -SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 -SP_PERF_SEL_VALU_OPERAND = 474 -SP_PERF_SEL_VALU_VGPR_OPERAND = 475 -SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 -SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 -SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 -SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 -SP_PERF_SEL_VALU_STALL = 480 -SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 -SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 -SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 -SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 -SP_PERF_SEL_VALU_STALL_DST_STALL = 485 -SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 -SP_PERF_SEL_VGPR_VMEM_RD = 487 -SP_PERF_SEL_VGPR_EXP_RD = 488 -SP_PERF_SEL_VGPR_SPI_WR = 489 -SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 -SP_PERF_SEL_VGPR_WR = 491 -SP_PERF_SEL_VGPR_RD = 492 -SP_PERF_SEL_DUMMY_LAST = 493 -SQ_PERF_SEL_NONE2 = 511 -SQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_ROUND_MODE' -SQ_ROUND_MODE__enumvalues = { - 0: 'SQ_ROUND_NEAREST_EVEN', - 1: 'SQ_ROUND_PLUS_INFINITY', - 2: 'SQ_ROUND_MINUS_INFINITY', - 3: 'SQ_ROUND_TO_ZERO', -} -SQ_ROUND_NEAREST_EVEN = 0 -SQ_ROUND_PLUS_INFINITY = 1 -SQ_ROUND_MINUS_INFINITY = 2 -SQ_ROUND_TO_ZERO = 3 -SQ_ROUND_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_BUF_TYPE' -SQ_RSRC_BUF_TYPE__enumvalues = { - 0: 'SQ_RSRC_BUF', - 1: 'SQ_RSRC_BUF_RSVD_1', - 2: 'SQ_RSRC_BUF_RSVD_2', - 3: 'SQ_RSRC_BUF_RSVD_3', -} -SQ_RSRC_BUF = 0 -SQ_RSRC_BUF_RSVD_1 = 1 -SQ_RSRC_BUF_RSVD_2 = 2 -SQ_RSRC_BUF_RSVD_3 = 3 -SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_FLAT_TYPE' -SQ_RSRC_FLAT_TYPE__enumvalues = { - 0: 'SQ_RSRC_FLAT_RSVD_0', - 1: 'SQ_RSRC_FLAT', - 2: 'SQ_RSRC_FLAT_RSVD_2', - 3: 'SQ_RSRC_FLAT_RSVD_3', -} -SQ_RSRC_FLAT_RSVD_0 = 0 -SQ_RSRC_FLAT = 1 -SQ_RSRC_FLAT_RSVD_2 = 2 -SQ_RSRC_FLAT_RSVD_3 = 3 -SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_RSRC_IMG_TYPE' -SQ_RSRC_IMG_TYPE__enumvalues = { - 0: 'SQ_RSRC_IMG_RSVD_0', - 1: 'SQ_RSRC_IMG_RSVD_1', - 2: 'SQ_RSRC_IMG_RSVD_2', - 3: 'SQ_RSRC_IMG_RSVD_3', - 4: 'SQ_RSRC_IMG_RSVD_4', - 5: 'SQ_RSRC_IMG_RSVD_5', - 6: 'SQ_RSRC_IMG_RSVD_6', - 7: 'SQ_RSRC_IMG_RSVD_7', - 8: 'SQ_RSRC_IMG_1D', - 9: 'SQ_RSRC_IMG_2D', - 10: 'SQ_RSRC_IMG_3D', - 11: 'SQ_RSRC_IMG_CUBE', - 12: 'SQ_RSRC_IMG_1D_ARRAY', - 13: 'SQ_RSRC_IMG_2D_ARRAY', - 14: 'SQ_RSRC_IMG_2D_MSAA', - 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', -} -SQ_RSRC_IMG_RSVD_0 = 0 -SQ_RSRC_IMG_RSVD_1 = 1 -SQ_RSRC_IMG_RSVD_2 = 2 -SQ_RSRC_IMG_RSVD_3 = 3 -SQ_RSRC_IMG_RSVD_4 = 4 -SQ_RSRC_IMG_RSVD_5 = 5 -SQ_RSRC_IMG_RSVD_6 = 6 -SQ_RSRC_IMG_RSVD_7 = 7 -SQ_RSRC_IMG_1D = 8 -SQ_RSRC_IMG_2D = 9 -SQ_RSRC_IMG_3D = 10 -SQ_RSRC_IMG_CUBE = 11 -SQ_RSRC_IMG_1D_ARRAY = 12 -SQ_RSRC_IMG_2D_ARRAY = 13 -SQ_RSRC_IMG_2D_MSAA = 14 -SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 -SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_SEL_XYZW01' -SQ_SEL_XYZW01__enumvalues = { - 0: 'SQ_SEL_0', - 1: 'SQ_SEL_1', - 2: 'SQ_SEL_N_BC_1', - 3: 'SQ_SEL_RESERVED_1', - 4: 'SQ_SEL_X', - 5: 'SQ_SEL_Y', - 6: 'SQ_SEL_Z', - 7: 'SQ_SEL_W', -} -SQ_SEL_0 = 0 -SQ_SEL_1 = 1 -SQ_SEL_N_BC_1 = 2 -SQ_SEL_RESERVED_1 = 3 -SQ_SEL_X = 4 -SQ_SEL_Y = 5 -SQ_SEL_Z = 6 -SQ_SEL_W = 7 -SQ_SEL_XYZW01 = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_ANISO_RATIO' -SQ_TEX_ANISO_RATIO__enumvalues = { - 0: 'SQ_TEX_ANISO_RATIO_1', - 1: 'SQ_TEX_ANISO_RATIO_2', - 2: 'SQ_TEX_ANISO_RATIO_4', - 3: 'SQ_TEX_ANISO_RATIO_8', - 4: 'SQ_TEX_ANISO_RATIO_16', -} -SQ_TEX_ANISO_RATIO_1 = 0 -SQ_TEX_ANISO_RATIO_2 = 1 -SQ_TEX_ANISO_RATIO_4 = 2 -SQ_TEX_ANISO_RATIO_8 = 3 -SQ_TEX_ANISO_RATIO_16 = 4 -SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_BORDER_COLOR' -SQ_TEX_BORDER_COLOR__enumvalues = { - 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 3: 'SQ_TEX_BORDER_COLOR_REGISTER', -} -SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 -SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 -SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 -SQ_TEX_BORDER_COLOR_REGISTER = 3 -SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_CLAMP' -SQ_TEX_CLAMP__enumvalues = { - 0: 'SQ_TEX_WRAP', - 1: 'SQ_TEX_MIRROR', - 2: 'SQ_TEX_CLAMP_LAST_TEXEL', - 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 4: 'SQ_TEX_CLAMP_HALF_BORDER', - 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', - 6: 'SQ_TEX_CLAMP_BORDER', - 7: 'SQ_TEX_MIRROR_ONCE_BORDER', -} -SQ_TEX_WRAP = 0 -SQ_TEX_MIRROR = 1 -SQ_TEX_CLAMP_LAST_TEXEL = 2 -SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 -SQ_TEX_CLAMP_HALF_BORDER = 4 -SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 -SQ_TEX_CLAMP_BORDER = 6 -SQ_TEX_MIRROR_ONCE_BORDER = 7 -SQ_TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_DEPTH_COMPARE' -SQ_TEX_DEPTH_COMPARE__enumvalues = { - 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', - 1: 'SQ_TEX_DEPTH_COMPARE_LESS', - 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', - 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', - 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', - 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', - 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', -} -SQ_TEX_DEPTH_COMPARE_NEVER = 0 -SQ_TEX_DEPTH_COMPARE_LESS = 1 -SQ_TEX_DEPTH_COMPARE_EQUAL = 2 -SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 -SQ_TEX_DEPTH_COMPARE_GREATER = 4 -SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 -SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 -SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 -SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_MIP_FILTER' -SQ_TEX_MIP_FILTER__enumvalues = { - 0: 'SQ_TEX_MIP_FILTER_NONE', - 1: 'SQ_TEX_MIP_FILTER_POINT', - 2: 'SQ_TEX_MIP_FILTER_LINEAR', - 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', -} -SQ_TEX_MIP_FILTER_NONE = 0 -SQ_TEX_MIP_FILTER_POINT = 1 -SQ_TEX_MIP_FILTER_LINEAR = 2 -SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 -SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_XY_FILTER' -SQ_TEX_XY_FILTER__enumvalues = { - 0: 'SQ_TEX_XY_FILTER_POINT', - 1: 'SQ_TEX_XY_FILTER_BILINEAR', - 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', - 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', -} -SQ_TEX_XY_FILTER_POINT = 0 -SQ_TEX_XY_FILTER_BILINEAR = 1 -SQ_TEX_XY_FILTER_ANISO_POINT = 2 -SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 -SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TEX_Z_FILTER' -SQ_TEX_Z_FILTER__enumvalues = { - 0: 'SQ_TEX_Z_FILTER_NONE', - 1: 'SQ_TEX_Z_FILTER_POINT', - 2: 'SQ_TEX_Z_FILTER_LINEAR', -} -SQ_TEX_Z_FILTER_NONE = 0 -SQ_TEX_Z_FILTER_POINT = 1 -SQ_TEX_Z_FILTER_LINEAR = 2 -SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_MODE' -SQ_TT_MODE__enumvalues = { - 0: 'SQ_TT_MODE_OFF', - 1: 'SQ_TT_MODE_ON', - 2: 'SQ_TT_MODE_GLOBAL', - 3: 'SQ_TT_MODE_DETAIL', -} -SQ_TT_MODE_OFF = 0 -SQ_TT_MODE_ON = 1 -SQ_TT_MODE_GLOBAL = 2 -SQ_TT_MODE_DETAIL = 3 -SQ_TT_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_RT_FREQ' -SQ_TT_RT_FREQ__enumvalues = { - 0: 'SQ_TT_RT_FREQ_NEVER', - 1: 'SQ_TT_RT_FREQ_1024_CLK', - 2: 'SQ_TT_RT_FREQ_4096_CLK', -} -SQ_TT_RT_FREQ_NEVER = 0 -SQ_TT_RT_FREQ_1024_CLK = 1 -SQ_TT_RT_FREQ_4096_CLK = 2 -SQ_TT_RT_FREQ = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' -SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { - 1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', - 2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', -} -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1 -SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2 -SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', - 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', -} -SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0 -SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1 -SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE' -SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = { - 1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', - 2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', - 4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', -} -SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1 -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2 -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4 -SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', - 1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', - 2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', -} -SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0 -SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1 -SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2 -SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' -SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { - 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', - 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', - 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', - 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', - 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', - 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', - 64: 'SQ_TT_TOKEN_MASK_ALL_BIT', - 128: 'SQ_TT_TOKEN_MASK_RSVD_BIT', -} -SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 -SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 -SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 -SQ_TT_TOKEN_MASK_COMP_BIT = 8 -SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 -SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 -SQ_TT_TOKEN_MASK_ALL_BIT = 64 -SQ_TT_TOKEN_MASK_RSVD_BIT = 128 -SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', - 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', - 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', - 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', - 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', - 6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT', - 7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', -} -SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 -SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 -SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 -SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 -SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 -SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 -SQ_TT_TOKEN_MASK_ALL_SHIFT = 6 -SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7 -SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', - 4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', - 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', -} -SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 -SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 -SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 -SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 -SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4 -SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 -SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 -SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 -SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 -SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 -SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 -SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 -SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_UTIL_TIMER' -SQ_TT_UTIL_TIMER__enumvalues = { - 0: 'SQ_TT_UTIL_TIMER_100_CLK', - 1: 'SQ_TT_UTIL_TIMER_250_CLK', -} -SQ_TT_UTIL_TIMER_100_CLK = 0 -SQ_TT_UTIL_TIMER_250_CLK = 1 -SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WAVESTART_MODE' -SQ_TT_WAVESTART_MODE__enumvalues = { - 0: 'SQ_TT_WAVESTART_MODE_SHORT', - 1: 'SQ_TT_WAVESTART_MODE_ALLOC', - 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', -} -SQ_TT_WAVESTART_MODE_SHORT = 0 -SQ_TT_WAVESTART_MODE_ALLOC = 1 -SQ_TT_WAVESTART_MODE_PBB_ID = 2 -SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE' -SQ_TT_WTYPE_INCLUDE__enumvalues = { - 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', - 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', - 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', - 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', -} -SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 -SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2 -SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 -SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8 -SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 -SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32 -SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 -SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' -SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { - 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', - 1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', - 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', - 3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', - 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', - 5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', - 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', -} -SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 -SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1 -SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 -SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3 -SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 -SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5 -SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 -SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WATCH_MODES' -SQ_WATCH_MODES__enumvalues = { - 0: 'SQ_WATCH_MODE_READ', - 1: 'SQ_WATCH_MODE_NONREAD', - 2: 'SQ_WATCH_MODE_ATOMIC', - 3: 'SQ_WATCH_MODE_ALL', -} -SQ_WATCH_MODE_READ = 0 -SQ_WATCH_MODE_NONREAD = 1 -SQ_WATCH_MODE_ATOMIC = 2 -SQ_WATCH_MODE_ALL = 3 -SQ_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' -SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { - 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', - 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', - 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', -} -SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 -SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 -SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 -SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 -SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_IB_ECC_ST' -SQ_WAVE_IB_ECC_ST__enumvalues = { - 0: 'SQ_WAVE_IB_ECC_CLEAN', - 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 2: 'SQ_WAVE_IB_ECC_ERR_HALT', - 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', -} -SQ_WAVE_IB_ECC_CLEAN = 0 -SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 -SQ_WAVE_IB_ECC_ERR_HALT = 2 -SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 -SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_SCHED_MODES' -SQ_WAVE_SCHED_MODES__enumvalues = { - 0: 'SQ_WAVE_SCHED_MODE_NORMAL', - 1: 'SQ_WAVE_SCHED_MODE_EXPERT', - 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', -} -SQ_WAVE_SCHED_MODE_NORMAL = 0 -SQ_WAVE_SCHED_MODE_EXPERT = 1 -SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 -SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'SQ_WAVE_TYPE' -SQ_WAVE_TYPE__enumvalues = { - 0: 'SQ_WAVE_TYPE_PS', - 1: 'SQ_WAVE_TYPE_RSVD0', - 2: 'SQ_WAVE_TYPE_GS', - 3: 'SQ_WAVE_TYPE_RSVD1', - 4: 'SQ_WAVE_TYPE_HS', - 5: 'SQ_WAVE_TYPE_RSVD2', - 6: 'SQ_WAVE_TYPE_CS', - 7: 'SQ_WAVE_TYPE_PS1', - 8: 'SQ_WAVE_TYPE_PS2', - 9: 'SQ_WAVE_TYPE_PS3', -} -SQ_WAVE_TYPE_PS = 0 -SQ_WAVE_TYPE_RSVD0 = 1 -SQ_WAVE_TYPE_GS = 2 -SQ_WAVE_TYPE_RSVD1 = 3 -SQ_WAVE_TYPE_HS = 4 -SQ_WAVE_TYPE_RSVD2 = 5 -SQ_WAVE_TYPE_CS = 6 -SQ_WAVE_TYPE_PS1 = 7 -SQ_WAVE_TYPE_PS2 = 8 -SQ_WAVE_TYPE_PS3 = 9 -SQ_WAVE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSCNTL_TYPE' -CSCNTL_TYPE__enumvalues = { - 0: 'CSCNTL_TYPE_TG', - 1: 'CSCNTL_TYPE_STATE', - 2: 'CSCNTL_TYPE_EVENT', - 3: 'CSCNTL_TYPE_PRIVATE', -} -CSCNTL_TYPE_TG = 0 -CSCNTL_TYPE_STATE = 1 -CSCNTL_TYPE_EVENT = 2 -CSCNTL_TYPE_PRIVATE = 3 -CSCNTL_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'CSDATA_TYPE' -CSDATA_TYPE__enumvalues = { - 0: 'CSDATA_TYPE_TG', - 1: 'CSDATA_TYPE_STATE', - 2: 'CSDATA_TYPE_EVENT', - 3: 'CSDATA_TYPE_PRIVATE', -} -CSDATA_TYPE_TG = 0 -CSDATA_TYPE_STATE = 1 -CSDATA_TYPE_EVENT = 2 -CSDATA_TYPE_PRIVATE = 3 -CSDATA_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GE1_PERFCOUNT_SELECT' -GE1_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge1_assembler_busy', - 1: 'ge1_assembler_stalled', - 2: 'ge1_dma_busy', - 3: 'ge1_dma_lat_bin_0', - 4: 'ge1_dma_lat_bin_1', - 5: 'ge1_dma_lat_bin_2', - 6: 'ge1_dma_lat_bin_3', - 7: 'ge1_dma_lat_bin_4', - 8: 'ge1_dma_lat_bin_5', - 9: 'ge1_dma_lat_bin_6', - 10: 'ge1_dma_lat_bin_7', - 11: 'ge1_dma_return_cl0', - 12: 'ge1_dma_return_cl1', - 13: 'ge1_dma_utcl1_consecutive_retry_event', - 14: 'ge1_dma_utcl1_request_event', - 15: 'ge1_dma_utcl1_retry_event', - 16: 'ge1_dma_utcl1_stall_event', - 17: 'ge1_dma_utcl1_stall_utcl2_event', - 18: 'ge1_dma_utcl1_translation_hit_event', - 19: 'ge1_dma_utcl1_translation_miss_event', - 20: 'ge1_assembler_dma_starved', - 21: 'ge1_rbiu_di_fifo_stalled_p0', - 22: 'ge1_rbiu_di_fifo_starved_p0', - 23: 'ge1_rbiu_dr_fifo_stalled_p0', - 24: 'ge1_rbiu_dr_fifo_starved_p0', - 25: 'ge1_sclk_reg_vld', - 26: 'ge1_stat_busy', - 27: 'ge1_stat_no_dma_busy', - 28: 'ge1_pipe0_to_pipe1', - 29: 'ge1_pipe1_to_pipe0', - 30: 'ge1_dma_return_size_cl0', - 31: 'ge1_dma_return_size_cl1', - 32: 'ge1_small_draws_one_instance', - 33: 'ge1_sclk_input_vld', - 34: 'ge1_prim_group_limit_hit', - 35: 'ge1_unopt_multi_instance_draws', - 36: 'ge1_rbiu_di_fifo_stalled_p1', - 37: 'ge1_rbiu_di_fifo_starved_p1', - 38: 'ge1_rbiu_dr_fifo_stalled_p1', - 39: 'ge1_rbiu_dr_fifo_starved_p1', -} -ge1_assembler_busy = 0 -ge1_assembler_stalled = 1 -ge1_dma_busy = 2 -ge1_dma_lat_bin_0 = 3 -ge1_dma_lat_bin_1 = 4 -ge1_dma_lat_bin_2 = 5 -ge1_dma_lat_bin_3 = 6 -ge1_dma_lat_bin_4 = 7 -ge1_dma_lat_bin_5 = 8 -ge1_dma_lat_bin_6 = 9 -ge1_dma_lat_bin_7 = 10 -ge1_dma_return_cl0 = 11 -ge1_dma_return_cl1 = 12 -ge1_dma_utcl1_consecutive_retry_event = 13 -ge1_dma_utcl1_request_event = 14 -ge1_dma_utcl1_retry_event = 15 -ge1_dma_utcl1_stall_event = 16 -ge1_dma_utcl1_stall_utcl2_event = 17 -ge1_dma_utcl1_translation_hit_event = 18 -ge1_dma_utcl1_translation_miss_event = 19 -ge1_assembler_dma_starved = 20 -ge1_rbiu_di_fifo_stalled_p0 = 21 -ge1_rbiu_di_fifo_starved_p0 = 22 -ge1_rbiu_dr_fifo_stalled_p0 = 23 -ge1_rbiu_dr_fifo_starved_p0 = 24 -ge1_sclk_reg_vld = 25 -ge1_stat_busy = 26 -ge1_stat_no_dma_busy = 27 -ge1_pipe0_to_pipe1 = 28 -ge1_pipe1_to_pipe0 = 29 -ge1_dma_return_size_cl0 = 30 -ge1_dma_return_size_cl1 = 31 -ge1_small_draws_one_instance = 32 -ge1_sclk_input_vld = 33 -ge1_prim_group_limit_hit = 34 -ge1_unopt_multi_instance_draws = 35 -ge1_rbiu_di_fifo_stalled_p1 = 36 -ge1_rbiu_di_fifo_starved_p1 = 37 -ge1_rbiu_dr_fifo_stalled_p1 = 38 -ge1_rbiu_dr_fifo_starved_p1 = 39 -GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' -GE2_DIST_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_dist_hs_done', - 1: 'ge_dist_hs_done_latency_se0', - 2: 'ge_dist_hs_done_latency_se1', - 3: 'ge_dist_hs_done_latency_se2', - 4: 'ge_dist_hs_done_latency_se3', - 5: 'ge_dist_hs_done_latency_se4', - 6: 'ge_dist_hs_done_latency_se5', - 7: 'ge_dist_hs_done_latency_se6', - 8: 'ge_dist_hs_done_latency_se7', - 9: 'ge_dist_inside_tf_bin_0', - 10: 'ge_dist_inside_tf_bin_1', - 11: 'ge_dist_inside_tf_bin_2', - 12: 'ge_dist_inside_tf_bin_3', - 13: 'ge_dist_inside_tf_bin_4', - 14: 'ge_dist_inside_tf_bin_5', - 15: 'ge_dist_inside_tf_bin_6', - 16: 'ge_dist_inside_tf_bin_7', - 17: 'ge_dist_inside_tf_bin_8', - 18: 'ge_dist_null_patch', - 19: 'ge_dist_sclk_core_vld', - 20: 'ge_dist_sclk_wd_te11_vld', - 21: 'ge_dist_tfreq_lat_bin_0', - 22: 'ge_dist_tfreq_lat_bin_1', - 23: 'ge_dist_tfreq_lat_bin_2', - 24: 'ge_dist_tfreq_lat_bin_3', - 25: 'ge_dist_tfreq_lat_bin_4', - 26: 'ge_dist_tfreq_lat_bin_5', - 27: 'ge_dist_tfreq_lat_bin_6', - 28: 'ge_dist_tfreq_lat_bin_7', - 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 30: 'ge_dist_tfreq_utcl1_request_event', - 31: 'ge_dist_tfreq_utcl1_retry_event', - 32: 'ge_dist_tfreq_utcl1_stall_event', - 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 34: 'ge_dist_tfreq_utcl1_translation_hit_event', - 35: 'ge_dist_tfreq_utcl1_translation_miss_event', - 36: 'ge_dist_vs_pc_stall', - 37: 'ge_dist_pc_feorder_fifo_full', - 38: 'ge_dist_pc_ge_manager_busy', - 39: 'ge_dist_pc_req_stall_se0', - 40: 'ge_dist_pc_req_stall_se1', - 41: 'ge_dist_pc_req_stall_se2', - 42: 'ge_dist_pc_req_stall_se3', - 43: 'ge_dist_pc_req_stall_se4', - 44: 'ge_dist_pc_req_stall_se5', - 45: 'ge_dist_pc_req_stall_se6', - 46: 'ge_dist_pc_req_stall_se7', - 47: 'ge_dist_pc_space_zero', - 48: 'ge_dist_sclk_input_vld', - 49: 'ge_dist_reserved', - 50: 'ge_dist_wd_te11_busy', - 51: 'ge_dist_te11_starved', - 52: 'ge_dist_switch_mode_stall', - 53: 'ge_all_tf_eq', - 54: 'ge_all_tf2', - 55: 'ge_all_tf3', - 56: 'ge_all_tf4', - 57: 'ge_all_tf5', - 58: 'ge_all_tf6', - 59: 'ge_se0_te11_starved_on_hs_done', - 60: 'ge_se1_te11_starved_on_hs_done', - 61: 'ge_se2_te11_starved_on_hs_done', - 62: 'ge_se3_te11_starved_on_hs_done', - 63: 'ge_se4_te11_starved_on_hs_done', - 64: 'ge_se5_te11_starved_on_hs_done', - 65: 'ge_se6_te11_starved_on_hs_done', - 66: 'ge_se7_te11_starved_on_hs_done', - 67: 'ge_dist_op_fifo_full_starve', - 68: 'ge_dist_hs_done_se0', - 69: 'ge_dist_hs_done_se1', - 70: 'ge_dist_hs_done_se2', - 71: 'ge_dist_hs_done_se3', - 72: 'ge_dist_hs_done_se4', - 73: 'ge_dist_hs_done_se5', - 74: 'ge_dist_hs_done_se6', - 75: 'ge_dist_hs_done_se7', - 76: 'ge_dist_hs_done_latency', - 77: 'ge_dist_distributer_busy', - 78: 'ge_tf_ret_data_stalling_hs_done', - 79: 'ge_num_of_no_dist_patches', - 80: 'ge_num_of_donut_dist_patches', - 81: 'ge_num_of_patch_dist_patches', - 82: 'ge_num_of_se_switches_due_to_patch_accum', - 83: 'ge_num_of_se_switches_due_to_donut', - 84: 'ge_num_of_se_switches_due_to_trap', - 85: 'ge_num_of_hs_alloc_events', - 86: 'ge_agm_gcr_req', - 87: 'ge_agm_gcr_tag_stall', - 88: 'ge_agm_gcr_crd_stall', - 89: 'ge_agm_gcr_stall', - 90: 'ge_agm_gcr_latency', - 91: 'ge_distclk_vld', -} -ge_dist_hs_done = 0 -ge_dist_hs_done_latency_se0 = 1 -ge_dist_hs_done_latency_se1 = 2 -ge_dist_hs_done_latency_se2 = 3 -ge_dist_hs_done_latency_se3 = 4 -ge_dist_hs_done_latency_se4 = 5 -ge_dist_hs_done_latency_se5 = 6 -ge_dist_hs_done_latency_se6 = 7 -ge_dist_hs_done_latency_se7 = 8 -ge_dist_inside_tf_bin_0 = 9 -ge_dist_inside_tf_bin_1 = 10 -ge_dist_inside_tf_bin_2 = 11 -ge_dist_inside_tf_bin_3 = 12 -ge_dist_inside_tf_bin_4 = 13 -ge_dist_inside_tf_bin_5 = 14 -ge_dist_inside_tf_bin_6 = 15 -ge_dist_inside_tf_bin_7 = 16 -ge_dist_inside_tf_bin_8 = 17 -ge_dist_null_patch = 18 -ge_dist_sclk_core_vld = 19 -ge_dist_sclk_wd_te11_vld = 20 -ge_dist_tfreq_lat_bin_0 = 21 -ge_dist_tfreq_lat_bin_1 = 22 -ge_dist_tfreq_lat_bin_2 = 23 -ge_dist_tfreq_lat_bin_3 = 24 -ge_dist_tfreq_lat_bin_4 = 25 -ge_dist_tfreq_lat_bin_5 = 26 -ge_dist_tfreq_lat_bin_6 = 27 -ge_dist_tfreq_lat_bin_7 = 28 -ge_dist_tfreq_utcl1_consecutive_retry_event = 29 -ge_dist_tfreq_utcl1_request_event = 30 -ge_dist_tfreq_utcl1_retry_event = 31 -ge_dist_tfreq_utcl1_stall_event = 32 -ge_dist_tfreq_utcl1_stall_utcl2_event = 33 -ge_dist_tfreq_utcl1_translation_hit_event = 34 -ge_dist_tfreq_utcl1_translation_miss_event = 35 -ge_dist_vs_pc_stall = 36 -ge_dist_pc_feorder_fifo_full = 37 -ge_dist_pc_ge_manager_busy = 38 -ge_dist_pc_req_stall_se0 = 39 -ge_dist_pc_req_stall_se1 = 40 -ge_dist_pc_req_stall_se2 = 41 -ge_dist_pc_req_stall_se3 = 42 -ge_dist_pc_req_stall_se4 = 43 -ge_dist_pc_req_stall_se5 = 44 -ge_dist_pc_req_stall_se6 = 45 -ge_dist_pc_req_stall_se7 = 46 -ge_dist_pc_space_zero = 47 -ge_dist_sclk_input_vld = 48 -ge_dist_reserved = 49 -ge_dist_wd_te11_busy = 50 -ge_dist_te11_starved = 51 -ge_dist_switch_mode_stall = 52 -ge_all_tf_eq = 53 -ge_all_tf2 = 54 -ge_all_tf3 = 55 -ge_all_tf4 = 56 -ge_all_tf5 = 57 -ge_all_tf6 = 58 -ge_se0_te11_starved_on_hs_done = 59 -ge_se1_te11_starved_on_hs_done = 60 -ge_se2_te11_starved_on_hs_done = 61 -ge_se3_te11_starved_on_hs_done = 62 -ge_se4_te11_starved_on_hs_done = 63 -ge_se5_te11_starved_on_hs_done = 64 -ge_se6_te11_starved_on_hs_done = 65 -ge_se7_te11_starved_on_hs_done = 66 -ge_dist_op_fifo_full_starve = 67 -ge_dist_hs_done_se0 = 68 -ge_dist_hs_done_se1 = 69 -ge_dist_hs_done_se2 = 70 -ge_dist_hs_done_se3 = 71 -ge_dist_hs_done_se4 = 72 -ge_dist_hs_done_se5 = 73 -ge_dist_hs_done_se6 = 74 -ge_dist_hs_done_se7 = 75 -ge_dist_hs_done_latency = 76 -ge_dist_distributer_busy = 77 -ge_tf_ret_data_stalling_hs_done = 78 -ge_num_of_no_dist_patches = 79 -ge_num_of_donut_dist_patches = 80 -ge_num_of_patch_dist_patches = 81 -ge_num_of_se_switches_due_to_patch_accum = 82 -ge_num_of_se_switches_due_to_donut = 83 -ge_num_of_se_switches_due_to_trap = 84 -ge_num_of_hs_alloc_events = 85 -ge_agm_gcr_req = 86 -ge_agm_gcr_tag_stall = 87 -ge_agm_gcr_crd_stall = 88 -ge_agm_gcr_stall = 89 -ge_agm_gcr_latency = 90 -ge_distclk_vld = 91 -GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' -GE2_SE_PERFCOUNT_SELECT__enumvalues = { - 0: 'ge_se_ds_prims', - 1: 'ge_se_es_thread_groups', - 2: 'ge_se_esvert_stalled_gsprim', - 3: 'ge_se_hs_tfm_stall', - 4: 'ge_se_hs_tgs_active_high_water_mark', - 5: 'ge_se_hs_thread_groups', - 6: 'ge_se_reused_es_indices', - 7: 'ge_se_sclk_ngg_vld', - 8: 'ge_se_sclk_te11_vld', - 9: 'ge_se_spi_esvert_eov', - 10: 'ge_se_spi_esvert_stalled', - 11: 'ge_se_spi_esvert_starved_busy', - 12: 'ge_se_spi_esvert_valid', - 13: 'ge_se_spi_gsprim_cont', - 14: 'ge_se_spi_gsprim_eov', - 15: 'ge_se_spi_gsprim_stalled', - 16: 'ge_se_spi_gsprim_starved_busy', - 17: 'ge_se_spi_gsprim_valid', - 18: 'ge_se_spi_gssubgrp_is_event', - 19: 'ge_se_spi_gssubgrp_send', - 20: 'ge_se_spi_hsvert_eov', - 21: 'ge_se_spi_hsvert_stalled', - 22: 'ge_se_spi_hsvert_starved_busy', - 23: 'ge_se_spi_hsvert_valid', - 24: 'ge_se_spi_hswave_is_event', - 25: 'ge_se_spi_hswave_send', - 26: 'ge_se_spi_lsvert_eov', - 27: 'ge_se_spi_lsvert_stalled', - 28: 'ge_se_spi_lsvert_starved_busy', - 29: 'ge_se_spi_lsvert_valid', - 30: 'ge_se_spi_hsvert_fifo_full_stall', - 31: 'ge_se_spi_tgrp_fifo_stall', - 32: 'ge_spi_hsgrp_spi_stall', - 33: 'ge_se_spi_gssubgrp_event_window_active', - 34: 'ge_se_hs_input_stall', - 35: 'ge_se_sending_vert_or_prim', - 36: 'ge_se_sclk_input_vld', - 37: 'ge_spi_lswave_fifo_full_stall', - 38: 'ge_spi_hswave_fifo_full_stall', - 39: 'ge_hs_tif_stall', - 40: 'ge_csb_spi_bp', - 41: 'ge_ngg_starving_for_pc_grant', - 42: 'ge_pa0_csb_eop', - 43: 'ge_pa1_csb_eop', - 44: 'ge_ngg_starved_idle', - 45: 'ge_gsprim_send', - 46: 'ge_esvert_send', - 47: 'ge_ngg_starved_after_work', - 48: 'ge_ngg_subgrp_fifo_stall', - 49: 'ge_ngg_ord_id_req_stall', - 50: 'ge_ngg_indx_bus_stall', - 51: 'ge_hs_stall_tfmm_fifo_full', - 52: 'ge_gs_issue_rtr_stalled', - 53: 'ge_gsprim_stalled_esvert', - 54: 'ge_gsthread_stalled', - 55: 'ge_te11_stall_prim_funnel', - 56: 'ge_te11_stall_vert_funnel', - 57: 'ge_ngg_attr_grp_alloc', - 58: 'ge_ngg_attr_discard_alloc', - 59: 'ge_ngg_pc_space_not_avail', - 60: 'ge_ngg_agm_req_stall', - 61: 'ge_ngg_spi_esvert_partial_eov', - 62: 'ge_ngg_spi_gsprim_partial_eov', - 63: 'ge_spi_gsgrp_valid', - 64: 'ge_ngg_attr_grp_latency', - 65: 'ge_ngg_reuse_prim_limit_hit', - 66: 'ge_ngg_reuse_vert_limit_hit', - 67: 'ge_te11_con_stall', - 68: 'ge_te11_compactor_starved', - 69: 'ge_ngg_stall_tess_off_tess_on', - 70: 'ge_ngg_stall_tess_on_tess_off', -} -ge_se_ds_prims = 0 -ge_se_es_thread_groups = 1 -ge_se_esvert_stalled_gsprim = 2 -ge_se_hs_tfm_stall = 3 -ge_se_hs_tgs_active_high_water_mark = 4 -ge_se_hs_thread_groups = 5 -ge_se_reused_es_indices = 6 -ge_se_sclk_ngg_vld = 7 -ge_se_sclk_te11_vld = 8 -ge_se_spi_esvert_eov = 9 -ge_se_spi_esvert_stalled = 10 -ge_se_spi_esvert_starved_busy = 11 -ge_se_spi_esvert_valid = 12 -ge_se_spi_gsprim_cont = 13 -ge_se_spi_gsprim_eov = 14 -ge_se_spi_gsprim_stalled = 15 -ge_se_spi_gsprim_starved_busy = 16 -ge_se_spi_gsprim_valid = 17 -ge_se_spi_gssubgrp_is_event = 18 -ge_se_spi_gssubgrp_send = 19 -ge_se_spi_hsvert_eov = 20 -ge_se_spi_hsvert_stalled = 21 -ge_se_spi_hsvert_starved_busy = 22 -ge_se_spi_hsvert_valid = 23 -ge_se_spi_hswave_is_event = 24 -ge_se_spi_hswave_send = 25 -ge_se_spi_lsvert_eov = 26 -ge_se_spi_lsvert_stalled = 27 -ge_se_spi_lsvert_starved_busy = 28 -ge_se_spi_lsvert_valid = 29 -ge_se_spi_hsvert_fifo_full_stall = 30 -ge_se_spi_tgrp_fifo_stall = 31 -ge_spi_hsgrp_spi_stall = 32 -ge_se_spi_gssubgrp_event_window_active = 33 -ge_se_hs_input_stall = 34 -ge_se_sending_vert_or_prim = 35 -ge_se_sclk_input_vld = 36 -ge_spi_lswave_fifo_full_stall = 37 -ge_spi_hswave_fifo_full_stall = 38 -ge_hs_tif_stall = 39 -ge_csb_spi_bp = 40 -ge_ngg_starving_for_pc_grant = 41 -ge_pa0_csb_eop = 42 -ge_pa1_csb_eop = 43 -ge_ngg_starved_idle = 44 -ge_gsprim_send = 45 -ge_esvert_send = 46 -ge_ngg_starved_after_work = 47 -ge_ngg_subgrp_fifo_stall = 48 -ge_ngg_ord_id_req_stall = 49 -ge_ngg_indx_bus_stall = 50 -ge_hs_stall_tfmm_fifo_full = 51 -ge_gs_issue_rtr_stalled = 52 -ge_gsprim_stalled_esvert = 53 -ge_gsthread_stalled = 54 -ge_te11_stall_prim_funnel = 55 -ge_te11_stall_vert_funnel = 56 -ge_ngg_attr_grp_alloc = 57 -ge_ngg_attr_discard_alloc = 58 -ge_ngg_pc_space_not_avail = 59 -ge_ngg_agm_req_stall = 60 -ge_ngg_spi_esvert_partial_eov = 61 -ge_ngg_spi_gsprim_partial_eov = 62 -ge_spi_gsgrp_valid = 63 -ge_ngg_attr_grp_latency = 64 -ge_ngg_reuse_prim_limit_hit = 65 -ge_ngg_reuse_vert_limit_hit = 66 -ge_te11_con_stall = 67 -ge_te11_compactor_starved = 68 -ge_ngg_stall_tess_off_tess_on = 69 -ge_ngg_stall_tess_on_tess_off = 70 -GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ONE' -VGT_DETECT_ONE__enumvalues = { - 0: 'ENABLE_TF1_OPT', - 1: 'DISABLE_TF1_OPT', -} -ENABLE_TF1_OPT = 0 -DISABLE_TF1_OPT = 1 -VGT_DETECT_ONE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DETECT_ZERO' -VGT_DETECT_ZERO__enumvalues = { - 0: 'ENABLE_TF0_OPT', - 1: 'DISABLE_TF0_OPT', -} -ENABLE_TF0_OPT = 0 -DISABLE_TF0_OPT = 1 -VGT_DETECT_ZERO = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DIST_MODE' -VGT_DIST_MODE__enumvalues = { - 0: 'NO_DIST', - 1: 'PATCHES', - 2: 'DONUTS', - 3: 'TRAPEZOIDS', -} -NO_DIST = 0 -PATCHES = 1 -DONUTS = 2 -TRAPEZOIDS = 3 -VGT_DIST_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_INDEX_SIZE' -VGT_DI_INDEX_SIZE__enumvalues = { - 0: 'DI_INDEX_SIZE_16_BIT', - 1: 'DI_INDEX_SIZE_32_BIT', - 2: 'DI_INDEX_SIZE_8_BIT', -} -DI_INDEX_SIZE_16_BIT = 0 -DI_INDEX_SIZE_32_BIT = 1 -DI_INDEX_SIZE_8_BIT = 2 -VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' -VGT_DI_MAJOR_MODE_SELECT__enumvalues = { - 0: 'DI_MAJOR_MODE_0', - 1: 'DI_MAJOR_MODE_1', -} -DI_MAJOR_MODE_0 = 0 -DI_MAJOR_MODE_1 = 1 -VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_PRIM_TYPE' -VGT_DI_PRIM_TYPE__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_2D_RECTANGLE', - 8: 'DI_PT_UNUSED_1', - 9: 'DI_PT_PATCH', - 10: 'DI_PT_LINELIST_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRILIST_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 14: 'DI_PT_UNUSED_3', - 15: 'DI_PT_UNUSED_4', - 16: 'DI_PT_UNUSED_5', - 17: 'DI_PT_RECTLIST', - 18: 'DI_PT_LINELOOP', - 19: 'DI_PT_QUADLIST', - 20: 'DI_PT_QUADSTRIP', - 21: 'DI_PT_POLYGON', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_2D_RECTANGLE = 7 -DI_PT_UNUSED_1 = 8 -DI_PT_PATCH = 9 -DI_PT_LINELIST_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRILIST_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_UNUSED_3 = 14 -DI_PT_UNUSED_4 = 15 -DI_PT_UNUSED_5 = 16 -DI_PT_RECTLIST = 17 -DI_PT_LINELOOP = 18 -DI_PT_QUADLIST = 19 -DI_PT_QUADSTRIP = 20 -DI_PT_POLYGON = 21 -VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DI_SOURCE_SELECT' -VGT_DI_SOURCE_SELECT__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_RESERVED', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_RESERVED = 3 -VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_BUF_TYPE' -VGT_DMA_BUF_TYPE__enumvalues = { - 0: 'VGT_DMA_BUF_MEM', - 1: 'VGT_DMA_BUF_RING', - 2: 'VGT_DMA_BUF_SETUP', - 3: 'VGT_DMA_PTR_UPDATE', -} -VGT_DMA_BUF_MEM = 0 -VGT_DMA_BUF_RING = 1 -VGT_DMA_BUF_SETUP = 2 -VGT_DMA_PTR_UPDATE = 3 -VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_DMA_SWAP_MODE' -VGT_DMA_SWAP_MODE__enumvalues = { - 0: 'VGT_DMA_SWAP_NONE', - 1: 'VGT_DMA_SWAP_16_BIT', - 2: 'VGT_DMA_SWAP_32_BIT', - 3: 'VGT_DMA_SWAP_WORD', -} -VGT_DMA_SWAP_NONE = 0 -VGT_DMA_SWAP_16_BIT = 1 -VGT_DMA_SWAP_32_BIT = 2 -VGT_DMA_SWAP_WORD = 3 -VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_EVENT_TYPE' -VGT_EVENT_TYPE__enumvalues = { - 0: 'Reserved_0x00', - 1: 'SAMPLE_STREAMOUTSTATS1', - 2: 'SAMPLE_STREAMOUTSTATS2', - 3: 'SAMPLE_STREAMOUTSTATS3', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'CS_PARTIAL_FLUSH', - 8: 'VGT_STREAMOUT_SYNC', - 9: 'Reserved_0x09', - 10: 'VGT_STREAMOUT_RESET', - 11: 'END_OF_PIPE_INCR_DE', - 12: 'END_OF_PIPE_IB_END', - 13: 'RST_PIX_CNT', - 14: 'BREAK_BATCH', - 15: 'VS_PARTIAL_FLUSH', - 16: 'PS_PARTIAL_FLUSH', - 17: 'FLUSH_HS_OUTPUT', - 18: 'FLUSH_DFSM', - 19: 'RESET_TO_LOWEST_VGT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'WAIT_SYNC', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 25: 'PIPELINESTAT_START', - 26: 'PIPELINESTAT_STOP', - 27: 'PERFCOUNTER_SAMPLE', - 28: 'FLUSH_ES_OUTPUT', - 29: 'BIN_CONF_OVERRIDE_CHECK', - 30: 'SAMPLE_PIPELINESTAT', - 31: 'SO_VGTSTREAMOUT_FLUSH', - 32: 'SAMPLE_STREAMOUTSTATS', - 33: 'RESET_VTX_CNT', - 34: 'BLOCK_CONTEXT_DONE', - 35: 'CS_CONTEXT_DONE', - 36: 'VGT_FLUSH', - 37: 'TGID_ROLLOVER', - 38: 'SQ_NON_EVENT', - 39: 'SC_SEND_DB_VPZ', - 40: 'BOTTOM_OF_PIPE_TS', - 41: 'FLUSH_SX_TS', - 42: 'DB_CACHE_FLUSH_AND_INV', - 43: 'FLUSH_AND_INV_DB_DATA_TS', - 44: 'FLUSH_AND_INV_DB_META', - 45: 'FLUSH_AND_INV_CB_DATA_TS', - 46: 'FLUSH_AND_INV_CB_META', - 47: 'CS_DONE', - 48: 'PS_DONE', - 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', - 50: 'SX_CB_RAT_ACK_REQUEST', - 51: 'THREAD_TRACE_START', - 52: 'THREAD_TRACE_STOP', - 53: 'THREAD_TRACE_MARKER', - 54: 'THREAD_TRACE_DRAW', - 55: 'THREAD_TRACE_FINISH', - 56: 'PIXEL_PIPE_STAT_CONTROL', - 57: 'PIXEL_PIPE_STAT_DUMP', - 58: 'PIXEL_PIPE_STAT_RESET', - 59: 'CONTEXT_SUSPEND', - 60: 'OFFCHIP_HS_DEALLOC', - 61: 'ENABLE_NGG_PIPELINE', - 62: 'ENABLE_LEGACY_PIPELINE', - 63: 'DRAW_DONE', -} -Reserved_0x00 = 0 -SAMPLE_STREAMOUTSTATS1 = 1 -SAMPLE_STREAMOUTSTATS2 = 2 -SAMPLE_STREAMOUTSTATS3 = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -CS_PARTIAL_FLUSH = 7 -VGT_STREAMOUT_SYNC = 8 -Reserved_0x09 = 9 -VGT_STREAMOUT_RESET = 10 -END_OF_PIPE_INCR_DE = 11 -END_OF_PIPE_IB_END = 12 -RST_PIX_CNT = 13 -BREAK_BATCH = 14 -VS_PARTIAL_FLUSH = 15 -PS_PARTIAL_FLUSH = 16 -FLUSH_HS_OUTPUT = 17 -FLUSH_DFSM = 18 -RESET_TO_LOWEST_VGT = 19 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -WAIT_SYNC = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -PIPELINESTAT_START = 25 -PIPELINESTAT_STOP = 26 -PERFCOUNTER_SAMPLE = 27 -FLUSH_ES_OUTPUT = 28 -BIN_CONF_OVERRIDE_CHECK = 29 -SAMPLE_PIPELINESTAT = 30 -SO_VGTSTREAMOUT_FLUSH = 31 -SAMPLE_STREAMOUTSTATS = 32 -RESET_VTX_CNT = 33 -BLOCK_CONTEXT_DONE = 34 -CS_CONTEXT_DONE = 35 -VGT_FLUSH = 36 -TGID_ROLLOVER = 37 -SQ_NON_EVENT = 38 -SC_SEND_DB_VPZ = 39 -BOTTOM_OF_PIPE_TS = 40 -FLUSH_SX_TS = 41 -DB_CACHE_FLUSH_AND_INV = 42 -FLUSH_AND_INV_DB_DATA_TS = 43 -FLUSH_AND_INV_DB_META = 44 -FLUSH_AND_INV_CB_DATA_TS = 45 -FLUSH_AND_INV_CB_META = 46 -CS_DONE = 47 -PS_DONE = 48 -FLUSH_AND_INV_CB_PIXEL_DATA = 49 -SX_CB_RAT_ACK_REQUEST = 50 -THREAD_TRACE_START = 51 -THREAD_TRACE_STOP = 52 -THREAD_TRACE_MARKER = 53 -THREAD_TRACE_DRAW = 54 -THREAD_TRACE_FINISH = 55 -PIXEL_PIPE_STAT_CONTROL = 56 -PIXEL_PIPE_STAT_DUMP = 57 -PIXEL_PIPE_STAT_RESET = 58 -CONTEXT_SUSPEND = 59 -OFFCHIP_HS_DEALLOC = 60 -ENABLE_NGG_PIPELINE = 61 -ENABLE_LEGACY_PIPELINE = 62 -DRAW_DONE = 63 -VGT_EVENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GROUP_CONV_SEL' -VGT_GROUP_CONV_SEL__enumvalues = { - 0: 'VGT_GRP_INDEX_16', - 1: 'VGT_GRP_INDEX_32', - 2: 'VGT_GRP_UINT_16', - 3: 'VGT_GRP_UINT_32', - 4: 'VGT_GRP_SINT_16', - 5: 'VGT_GRP_SINT_32', - 6: 'VGT_GRP_FLOAT_32', - 7: 'VGT_GRP_AUTO_PRIM', - 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', -} -VGT_GRP_INDEX_16 = 0 -VGT_GRP_INDEX_32 = 1 -VGT_GRP_UINT_16 = 2 -VGT_GRP_UINT_32 = 3 -VGT_GRP_SINT_16 = 4 -VGT_GRP_SINT_32 = 5 -VGT_GRP_FLOAT_32 = 6 -VGT_GRP_AUTO_PRIM = 7 -VGT_GRP_FIX_1_23_TO_FLOAT = 8 -VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_MODE_TYPE' -VGT_GS_MODE_TYPE__enumvalues = { - 0: 'GS_OFF', - 1: 'GS_SCENARIO_A', - 2: 'GS_SCENARIO_B', - 3: 'GS_SCENARIO_G', - 4: 'GS_SCENARIO_C', - 5: 'SPRITE_EN', -} -GS_OFF = 0 -GS_SCENARIO_A = 1 -GS_SCENARIO_B = 2 -GS_SCENARIO_G = 3 -GS_SCENARIO_C = 4 -SPRITE_EN = 5 -VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_GS_OUTPRIM_TYPE' -VGT_GS_OUTPRIM_TYPE__enumvalues = { - 0: 'POINTLIST', - 1: 'LINESTRIP', - 2: 'TRISTRIP', - 3: 'RECT_2D', - 4: 'RECTLIST', -} -POINTLIST = 0 -LINESTRIP = 1 -TRISTRIP = 2 -RECT_2D = 3 -RECTLIST = 4 -VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_INDEX_TYPE_MODE' -VGT_INDEX_TYPE_MODE__enumvalues = { - 0: 'VGT_INDEX_16', - 1: 'VGT_INDEX_32', - 2: 'VGT_INDEX_8', -} -VGT_INDEX_16 = 0 -VGT_INDEX_32 = 1 -VGT_INDEX_8 = 2 -VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUTPATH_SELECT' -VGT_OUTPATH_SELECT__enumvalues = { - 0: 'VGT_OUTPATH_VTX_REUSE', - 1: 'VGT_OUTPATH_GS_BLOCK', - 2: 'VGT_OUTPATH_HS_BLOCK', - 3: 'VGT_OUTPATH_PRIM_GEN', - 4: 'VGT_OUTPATH_TE_PRIM_GEN', - 5: 'VGT_OUTPATH_TE_GS_BLOCK', - 6: 'VGT_OUTPATH_TE_OUTPUT', -} -VGT_OUTPATH_VTX_REUSE = 0 -VGT_OUTPATH_GS_BLOCK = 1 -VGT_OUTPATH_HS_BLOCK = 2 -VGT_OUTPATH_PRIM_GEN = 3 -VGT_OUTPATH_TE_PRIM_GEN = 4 -VGT_OUTPATH_TE_GS_BLOCK = 5 -VGT_OUTPATH_TE_OUTPUT = 6 -VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_OUT_PRIM_TYPE' -VGT_OUT_PRIM_TYPE__enumvalues = { - 0: 'VGT_OUT_POINT', - 1: 'VGT_OUT_LINE', - 2: 'VGT_OUT_TRI', - 3: 'VGT_OUT_RECT_V0', - 4: 'VGT_OUT_RECT_V1', - 5: 'VGT_OUT_RECT_V2', - 6: 'VGT_OUT_RECT_V3', - 7: 'VGT_OUT_2D_RECT', - 8: 'VGT_TE_QUAD', - 9: 'VGT_TE_PRIM_INDEX_LINE', - 10: 'VGT_TE_PRIM_INDEX_TRI', - 11: 'VGT_TE_PRIM_INDEX_QUAD', - 12: 'VGT_OUT_LINE_ADJ', - 13: 'VGT_OUT_TRI_ADJ', - 14: 'VGT_OUT_PATCH', -} -VGT_OUT_POINT = 0 -VGT_OUT_LINE = 1 -VGT_OUT_TRI = 2 -VGT_OUT_RECT_V0 = 3 -VGT_OUT_RECT_V1 = 4 -VGT_OUT_RECT_V2 = 5 -VGT_OUT_RECT_V3 = 6 -VGT_OUT_2D_RECT = 7 -VGT_TE_QUAD = 8 -VGT_TE_PRIM_INDEX_LINE = 9 -VGT_TE_PRIM_INDEX_TRI = 10 -VGT_TE_PRIM_INDEX_QUAD = 11 -VGT_OUT_LINE_ADJ = 12 -VGT_OUT_TRI_ADJ = 13 -VGT_OUT_PATCH = 14 -VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_RDREQ_POLICY' -VGT_RDREQ_POLICY__enumvalues = { - 0: 'VGT_POLICY_LRU', - 1: 'VGT_POLICY_STREAM', - 2: 'VGT_POLICY_BYPASS', -} -VGT_POLICY_LRU = 0 -VGT_POLICY_STREAM = 1 -VGT_POLICY_BYPASS = 2 -VGT_RDREQ_POLICY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_ES_EN' -VGT_STAGES_ES_EN__enumvalues = { - 0: 'ES_STAGE_OFF', - 1: 'ES_STAGE_DS', - 2: 'ES_STAGE_REAL', - 3: 'RESERVED_ES', -} -ES_STAGE_OFF = 0 -ES_STAGE_DS = 1 -ES_STAGE_REAL = 2 -RESERVED_ES = 3 -VGT_STAGES_ES_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_GS_EN' -VGT_STAGES_GS_EN__enumvalues = { - 0: 'GS_STAGE_OFF', - 1: 'GS_STAGE_ON', -} -GS_STAGE_OFF = 0 -GS_STAGE_ON = 1 -VGT_STAGES_GS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_HS_EN' -VGT_STAGES_HS_EN__enumvalues = { - 0: 'HS_STAGE_OFF', - 1: 'HS_STAGE_ON', -} -HS_STAGE_OFF = 0 -HS_STAGE_ON = 1 -VGT_STAGES_HS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_LS_EN' -VGT_STAGES_LS_EN__enumvalues = { - 0: 'LS_STAGE_OFF', - 1: 'LS_STAGE_ON', - 2: 'CS_STAGE_ON', - 3: 'RESERVED_LS', -} -LS_STAGE_OFF = 0 -LS_STAGE_ON = 1 -CS_STAGE_ON = 2 -RESERVED_LS = 3 -VGT_STAGES_LS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_STAGES_VS_EN' -VGT_STAGES_VS_EN__enumvalues = { - 0: 'VS_STAGE_REAL', - 1: 'VS_STAGE_DS', - 2: 'VS_STAGE_COPY_SHADER', - 3: 'RESERVED_VS', -} -VS_STAGE_REAL = 0 -VS_STAGE_DS = 1 -VS_STAGE_COPY_SHADER = 2 -RESERVED_VS = 3 -VGT_STAGES_VS_EN = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_PARTITION' -VGT_TESS_PARTITION__enumvalues = { - 0: 'PART_INTEGER', - 1: 'PART_POW2', - 2: 'PART_FRAC_ODD', - 3: 'PART_FRAC_EVEN', -} -PART_INTEGER = 0 -PART_POW2 = 1 -PART_FRAC_ODD = 2 -PART_FRAC_EVEN = 3 -VGT_TESS_PARTITION = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TOPOLOGY' -VGT_TESS_TOPOLOGY__enumvalues = { - 0: 'OUTPUT_POINT', - 1: 'OUTPUT_LINE', - 2: 'OUTPUT_TRIANGLE_CW', - 3: 'OUTPUT_TRIANGLE_CCW', -} -OUTPUT_POINT = 0 -OUTPUT_LINE = 1 -OUTPUT_TRIANGLE_CW = 2 -OUTPUT_TRIANGLE_CCW = 3 -VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum - -# values for enumeration 'VGT_TESS_TYPE' -VGT_TESS_TYPE__enumvalues = { - 0: 'TESS_ISOLINE', - 1: 'TESS_TRIANGLE', - 2: 'TESS_QUAD', -} -TESS_ISOLINE = 0 -TESS_TRIANGLE = 1 -TESS_QUAD = 2 -VGT_TESS_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_REG_XFER' -WD_IA_DRAW_REG_XFER__enumvalues = { - 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', -} -WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 -WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 -WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 -WD_IA_DRAW_REG_XFER_GE_CNTL = 3 -WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5 -WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6 -WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7 -WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8 -WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_SOURCE' -WD_IA_DRAW_SOURCE__enumvalues = { - 0: 'WD_IA_DRAW_SOURCE_DMA', - 1: 'WD_IA_DRAW_SOURCE_IMMD', - 2: 'WD_IA_DRAW_SOURCE_AUTO', - 3: 'WD_IA_DRAW_SOURCE_OPAQ', -} -WD_IA_DRAW_SOURCE_DMA = 0 -WD_IA_DRAW_SOURCE_IMMD = 1 -WD_IA_DRAW_SOURCE_AUTO = 2 -WD_IA_DRAW_SOURCE_OPAQ = 3 -WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum - -# values for enumeration 'WD_IA_DRAW_TYPE' -WD_IA_DRAW_TYPE__enumvalues = { - 0: 'WD_IA_DRAW_TYPE_DI_MM0', - 1: 'WD_IA_DRAW_TYPE_REG_XFER', - 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', - 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 4: 'WD_IA_DRAW_TYPE_MIN_INDX', - 5: 'WD_IA_DRAW_TYPE_MAX_INDX', - 6: 'WD_IA_DRAW_TYPE_INDX_OFF', - 7: 'WD_IA_DRAW_TYPE_IMM_DATA', -} -WD_IA_DRAW_TYPE_DI_MM0 = 0 -WD_IA_DRAW_TYPE_REG_XFER = 1 -WD_IA_DRAW_TYPE_EVENT_INIT = 2 -WD_IA_DRAW_TYPE_EVENT_ADDR = 3 -WD_IA_DRAW_TYPE_MIN_INDX = 4 -WD_IA_DRAW_TYPE_MAX_INDX = 5 -WD_IA_DRAW_TYPE_INDX_OFF = 6 -WD_IA_DRAW_TYPE_IMM_DATA = 7 -WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'GB_EDC_DED_MODE' -GB_EDC_DED_MODE__enumvalues = { - 0: 'GB_EDC_DED_MODE_LOG', - 1: 'GB_EDC_DED_MODE_HALT', - 2: 'GB_EDC_DED_MODE_INT_HALT', -} -GB_EDC_DED_MODE_LOG = 0 -GB_EDC_DED_MODE_HALT = 1 -GB_EDC_DED_MODE_INT_HALT = 2 -GB_EDC_DED_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CHA_PERF_SEL' -CHA_PERF_SEL__enumvalues = { - 0: 'CHA_PERF_SEL_BUSY', - 1: 'CHA_PERF_SEL_STALL_CHC0', - 2: 'CHA_PERF_SEL_STALL_CHC1', - 3: 'CHA_PERF_SEL_STALL_CHC2', - 4: 'CHA_PERF_SEL_STALL_CHC3', - 5: 'CHA_PERF_SEL_STALL_CHC4', - 6: 'CHA_PERF_SEL_STALL_CHC5', - 7: 'CHA_PERF_SEL_REQUEST_CHC0', - 8: 'CHA_PERF_SEL_REQUEST_CHC1', - 9: 'CHA_PERF_SEL_REQUEST_CHC2', - 10: 'CHA_PERF_SEL_REQUEST_CHC3', - 11: 'CHA_PERF_SEL_REQUEST_CHC4', - 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', - 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', - 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', - 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', - 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', - 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', - 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 32: 'CHA_PERF_SEL_ARB_REQUESTS', - 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', - 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', - 39: 'CHA_PERF_SEL_CYCLE', -} -CHA_PERF_SEL_BUSY = 0 -CHA_PERF_SEL_STALL_CHC0 = 1 -CHA_PERF_SEL_STALL_CHC1 = 2 -CHA_PERF_SEL_STALL_CHC2 = 3 -CHA_PERF_SEL_STALL_CHC3 = 4 -CHA_PERF_SEL_STALL_CHC4 = 5 -CHA_PERF_SEL_STALL_CHC5 = 6 -CHA_PERF_SEL_REQUEST_CHC0 = 7 -CHA_PERF_SEL_REQUEST_CHC1 = 8 -CHA_PERF_SEL_REQUEST_CHC2 = 9 -CHA_PERF_SEL_REQUEST_CHC3 = 10 -CHA_PERF_SEL_REQUEST_CHC4 = 11 -CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 -CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 -CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 -CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 -CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 -CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 -CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 -CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 -CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 -CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 -CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 -CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 -CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 -CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 -CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 -CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 -CHA_PERF_SEL_ARB_REQUESTS = 32 -CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 -CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 -CHA_PERF_SEL_CYCLE = 39 -CHA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHCG_PERF_SEL' -CHCG_PERF_SEL__enumvalues = { - 0: 'CHCG_PERF_SEL_CYCLE', - 1: 'CHCG_PERF_SEL_BUSY', - 2: 'CHCG_PERF_SEL_STARVE', - 3: 'CHCG_PERF_SEL_ARB_RET_LEVEL', - 4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'CHCG_PERF_SEL_REQ', - 7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'CHCG_PERF_SEL_REQ_NOP_ACK', - 10: 'CHCG_PERF_SEL_REQ_NOP_RTN0', - 11: 'CHCG_PERF_SEL_REQ_READ', - 12: 'CHCG_PERF_SEL_REQ_READ_128B', - 13: 'CHCG_PERF_SEL_REQ_READ_32B', - 14: 'CHCG_PERF_SEL_REQ_READ_64B', - 15: 'CHCG_PERF_SEL_REQ_WRITE', - 16: 'CHCG_PERF_SEL_REQ_WRITE_32B', - 17: 'CHCG_PERF_SEL_REQ_WRITE_64B', - 18: 'CHCG_PERF_SEL_STALL_GUS_GL1', - 19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL', - 20: 'CHCG_PERF_SEL_REQ_CLIENT0', - 21: 'CHCG_PERF_SEL_REQ_CLIENT1', - 22: 'CHCG_PERF_SEL_REQ_CLIENT2', - 23: 'CHCG_PERF_SEL_REQ_CLIENT3', - 24: 'CHCG_PERF_SEL_REQ_CLIENT4', - 25: 'CHCG_PERF_SEL_REQ_CLIENT5', - 26: 'CHCG_PERF_SEL_REQ_CLIENT6', - 27: 'CHCG_PERF_SEL_REQ_CLIENT7', - 28: 'CHCG_PERF_SEL_REQ_CLIENT8', - 29: 'CHCG_PERF_SEL_REQ_CLIENT9', - 30: 'CHCG_PERF_SEL_REQ_CLIENT10', - 31: 'CHCG_PERF_SEL_REQ_CLIENT11', - 32: 'CHCG_PERF_SEL_REQ_CLIENT12', - 33: 'CHCG_PERF_SEL_REQ_CLIENT13', - 34: 'CHCG_PERF_SEL_REQ_CLIENT14', - 35: 'CHCG_PERF_SEL_REQ_CLIENT15', - 36: 'CHCG_PERF_SEL_REQ_CLIENT16', - 37: 'CHCG_PERF_SEL_REQ_CLIENT17', - 38: 'CHCG_PERF_SEL_REQ_CLIENT18', - 39: 'CHCG_PERF_SEL_REQ_CLIENT19', - 40: 'CHCG_PERF_SEL_REQ_CLIENT20', - 41: 'CHCG_PERF_SEL_REQ_CLIENT21', - 42: 'CHCG_PERF_SEL_REQ_CLIENT22', - 43: 'CHCG_PERF_SEL_REQ_CLIENT23', -} -CHCG_PERF_SEL_CYCLE = 0 -CHCG_PERF_SEL_BUSY = 1 -CHCG_PERF_SEL_STARVE = 2 -CHCG_PERF_SEL_ARB_RET_LEVEL = 3 -CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -CHCG_PERF_SEL_REQ = 6 -CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -CHCG_PERF_SEL_REQ_NOP_ACK = 9 -CHCG_PERF_SEL_REQ_NOP_RTN0 = 10 -CHCG_PERF_SEL_REQ_READ = 11 -CHCG_PERF_SEL_REQ_READ_128B = 12 -CHCG_PERF_SEL_REQ_READ_32B = 13 -CHCG_PERF_SEL_REQ_READ_64B = 14 -CHCG_PERF_SEL_REQ_WRITE = 15 -CHCG_PERF_SEL_REQ_WRITE_32B = 16 -CHCG_PERF_SEL_REQ_WRITE_64B = 17 -CHCG_PERF_SEL_STALL_GUS_GL1 = 18 -CHCG_PERF_SEL_STALL_BUFFER_FULL = 19 -CHCG_PERF_SEL_REQ_CLIENT0 = 20 -CHCG_PERF_SEL_REQ_CLIENT1 = 21 -CHCG_PERF_SEL_REQ_CLIENT2 = 22 -CHCG_PERF_SEL_REQ_CLIENT3 = 23 -CHCG_PERF_SEL_REQ_CLIENT4 = 24 -CHCG_PERF_SEL_REQ_CLIENT5 = 25 -CHCG_PERF_SEL_REQ_CLIENT6 = 26 -CHCG_PERF_SEL_REQ_CLIENT7 = 27 -CHCG_PERF_SEL_REQ_CLIENT8 = 28 -CHCG_PERF_SEL_REQ_CLIENT9 = 29 -CHCG_PERF_SEL_REQ_CLIENT10 = 30 -CHCG_PERF_SEL_REQ_CLIENT11 = 31 -CHCG_PERF_SEL_REQ_CLIENT12 = 32 -CHCG_PERF_SEL_REQ_CLIENT13 = 33 -CHCG_PERF_SEL_REQ_CLIENT14 = 34 -CHCG_PERF_SEL_REQ_CLIENT15 = 35 -CHCG_PERF_SEL_REQ_CLIENT16 = 36 -CHCG_PERF_SEL_REQ_CLIENT17 = 37 -CHCG_PERF_SEL_REQ_CLIENT18 = 38 -CHCG_PERF_SEL_REQ_CLIENT19 = 39 -CHCG_PERF_SEL_REQ_CLIENT20 = 40 -CHCG_PERF_SEL_REQ_CLIENT21 = 41 -CHCG_PERF_SEL_REQ_CLIENT22 = 42 -CHCG_PERF_SEL_REQ_CLIENT23 = 43 -CHCG_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CHC_PERF_SEL' -CHC_PERF_SEL__enumvalues = { - 0: 'CHC_PERF_SEL_CYCLE', - 1: 'CHC_PERF_SEL_BUSY', - 2: 'CHC_PERF_SEL_STARVE', - 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', - 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 6: 'CHC_PERF_SEL_REQ', - 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', - 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 9: 'CHC_PERF_SEL_REQ_NOP_ACK', - 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', - 11: 'CHC_PERF_SEL_REQ_READ', - 12: 'CHC_PERF_SEL_REQ_READ_128B', - 13: 'CHC_PERF_SEL_REQ_READ_32B', - 14: 'CHC_PERF_SEL_REQ_READ_64B', - 15: 'CHC_PERF_SEL_REQ_WRITE', - 16: 'CHC_PERF_SEL_REQ_WRITE_32B', - 17: 'CHC_PERF_SEL_REQ_WRITE_64B', - 18: 'CHC_PERF_SEL_STALL_GL2_GL1', - 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', - 20: 'CHC_PERF_SEL_REQ_CLIENT0', - 21: 'CHC_PERF_SEL_REQ_CLIENT1', - 22: 'CHC_PERF_SEL_REQ_CLIENT2', - 23: 'CHC_PERF_SEL_REQ_CLIENT3', - 24: 'CHC_PERF_SEL_REQ_CLIENT4', - 25: 'CHC_PERF_SEL_REQ_CLIENT5', - 26: 'CHC_PERF_SEL_REQ_CLIENT6', - 27: 'CHC_PERF_SEL_REQ_CLIENT7', - 28: 'CHC_PERF_SEL_REQ_CLIENT8', - 29: 'CHC_PERF_SEL_REQ_CLIENT9', - 30: 'CHC_PERF_SEL_REQ_CLIENT10', - 31: 'CHC_PERF_SEL_REQ_CLIENT11', - 32: 'CHC_PERF_SEL_REQ_CLIENT12', - 33: 'CHC_PERF_SEL_REQ_CLIENT13', - 34: 'CHC_PERF_SEL_REQ_CLIENT14', - 35: 'CHC_PERF_SEL_REQ_CLIENT15', - 36: 'CHC_PERF_SEL_REQ_CLIENT16', - 37: 'CHC_PERF_SEL_REQ_CLIENT17', - 38: 'CHC_PERF_SEL_REQ_CLIENT18', - 39: 'CHC_PERF_SEL_REQ_CLIENT19', - 40: 'CHC_PERF_SEL_REQ_CLIENT20', - 41: 'CHC_PERF_SEL_REQ_CLIENT21', - 42: 'CHC_PERF_SEL_REQ_CLIENT22', - 43: 'CHC_PERF_SEL_REQ_CLIENT23', -} -CHC_PERF_SEL_CYCLE = 0 -CHC_PERF_SEL_BUSY = 1 -CHC_PERF_SEL_STARVE = 2 -CHC_PERF_SEL_ARB_RET_LEVEL = 3 -CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 -CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 -CHC_PERF_SEL_REQ = 6 -CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 -CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 -CHC_PERF_SEL_REQ_NOP_ACK = 9 -CHC_PERF_SEL_REQ_NOP_RTN0 = 10 -CHC_PERF_SEL_REQ_READ = 11 -CHC_PERF_SEL_REQ_READ_128B = 12 -CHC_PERF_SEL_REQ_READ_32B = 13 -CHC_PERF_SEL_REQ_READ_64B = 14 -CHC_PERF_SEL_REQ_WRITE = 15 -CHC_PERF_SEL_REQ_WRITE_32B = 16 -CHC_PERF_SEL_REQ_WRITE_64B = 17 -CHC_PERF_SEL_STALL_GL2_GL1 = 18 -CHC_PERF_SEL_STALL_BUFFER_FULL = 19 -CHC_PERF_SEL_REQ_CLIENT0 = 20 -CHC_PERF_SEL_REQ_CLIENT1 = 21 -CHC_PERF_SEL_REQ_CLIENT2 = 22 -CHC_PERF_SEL_REQ_CLIENT3 = 23 -CHC_PERF_SEL_REQ_CLIENT4 = 24 -CHC_PERF_SEL_REQ_CLIENT5 = 25 -CHC_PERF_SEL_REQ_CLIENT6 = 26 -CHC_PERF_SEL_REQ_CLIENT7 = 27 -CHC_PERF_SEL_REQ_CLIENT8 = 28 -CHC_PERF_SEL_REQ_CLIENT9 = 29 -CHC_PERF_SEL_REQ_CLIENT10 = 30 -CHC_PERF_SEL_REQ_CLIENT11 = 31 -CHC_PERF_SEL_REQ_CLIENT12 = 32 -CHC_PERF_SEL_REQ_CLIENT13 = 33 -CHC_PERF_SEL_REQ_CLIENT14 = 34 -CHC_PERF_SEL_REQ_CLIENT15 = 35 -CHC_PERF_SEL_REQ_CLIENT16 = 36 -CHC_PERF_SEL_REQ_CLIENT17 = 37 -CHC_PERF_SEL_REQ_CLIENT18 = 38 -CHC_PERF_SEL_REQ_CLIENT19 = 39 -CHC_PERF_SEL_REQ_CLIENT20 = 40 -CHC_PERF_SEL_REQ_CLIENT21 = 41 -CHC_PERF_SEL_REQ_CLIENT22 = 42 -CHC_PERF_SEL_REQ_CLIENT23 = 43 -CHC_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1A_PERF_SEL' -GL1A_PERF_SEL__enumvalues = { - 0: 'GL1A_PERF_SEL_BUSY', - 1: 'GL1A_PERF_SEL_STALL_GL1C0', - 2: 'GL1A_PERF_SEL_STALL_GL1C1', - 3: 'GL1A_PERF_SEL_STALL_GL1C2', - 4: 'GL1A_PERF_SEL_STALL_GL1C3', - 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', - 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', - 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', - 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', - 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', - 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', - 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', - 17: 'GL1A_PERF_SEL_ARB_REQUESTS', - 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 23: 'GL1A_PERF_SEL_CYCLE', -} -GL1A_PERF_SEL_BUSY = 0 -GL1A_PERF_SEL_STALL_GL1C0 = 1 -GL1A_PERF_SEL_STALL_GL1C1 = 2 -GL1A_PERF_SEL_STALL_GL1C2 = 3 -GL1A_PERF_SEL_STALL_GL1C3 = 4 -GL1A_PERF_SEL_REQUEST_GL1C0 = 5 -GL1A_PERF_SEL_REQUEST_GL1C1 = 6 -GL1A_PERF_SEL_REQUEST_GL1C2 = 7 -GL1A_PERF_SEL_REQUEST_GL1C3 = 8 -GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 -GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 -GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 -GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 -GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 -GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 -GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 -GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 -GL1A_PERF_SEL_ARB_REQUESTS = 17 -GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 -GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 -GL1A_PERF_SEL_CYCLE = 23 -GL1A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1C_PERF_SEL' -GL1C_PERF_SEL__enumvalues = { - 0: 'GL1C_PERF_SEL_CYCLE', - 1: 'GL1C_PERF_SEL_BUSY', - 2: 'GL1C_PERF_SEL_STARVE', - 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 4: 'GL1C_PERF_SEL_GL2_REQ_READ', - 5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B', - 6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B', - 7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B', - 8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 9: 'GL1C_PERF_SEL_GL2_REQ_WRITE', - 10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', - 11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', - 12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', - 13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', - 14: 'GL1C_PERF_SEL_REQ', - 15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', - 16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 17: 'GL1C_PERF_SEL_REQ_SHADER_INV', - 18: 'GL1C_PERF_SEL_REQ_MISS', - 19: 'GL1C_PERF_SEL_REQ_NOP_ACK', - 20: 'GL1C_PERF_SEL_REQ_NOP_RTN0', - 21: 'GL1C_PERF_SEL_REQ_READ', - 22: 'GL1C_PERF_SEL_REQ_READ_128B', - 23: 'GL1C_PERF_SEL_REQ_READ_32B', - 24: 'GL1C_PERF_SEL_REQ_READ_64B', - 25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', - 26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', - 27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', - 28: 'GL1C_PERF_SEL_REQ_WRITE', - 29: 'GL1C_PERF_SEL_REQ_WRITE_32B', - 30: 'GL1C_PERF_SEL_REQ_WRITE_64B', - 31: 'GL1C_PERF_SEL_STALL_GL2_GL1', - 32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL', - 33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', - 34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', - 35: 'GL1C_PERF_SEL_STALL_GCR_INV', - 36: 'GL1C_PERF_SEL_STALL_VM', - 37: 'GL1C_PERF_SEL_REQ_CLIENT0', - 38: 'GL1C_PERF_SEL_REQ_CLIENT1', - 39: 'GL1C_PERF_SEL_REQ_CLIENT2', - 40: 'GL1C_PERF_SEL_REQ_CLIENT3', - 41: 'GL1C_PERF_SEL_REQ_CLIENT4', - 42: 'GL1C_PERF_SEL_REQ_CLIENT5', - 43: 'GL1C_PERF_SEL_REQ_CLIENT6', - 44: 'GL1C_PERF_SEL_REQ_CLIENT7', - 45: 'GL1C_PERF_SEL_REQ_CLIENT8', - 46: 'GL1C_PERF_SEL_REQ_CLIENT9', - 47: 'GL1C_PERF_SEL_REQ_CLIENT10', - 48: 'GL1C_PERF_SEL_REQ_CLIENT11', - 49: 'GL1C_PERF_SEL_REQ_CLIENT12', - 50: 'GL1C_PERF_SEL_REQ_CLIENT13', - 51: 'GL1C_PERF_SEL_REQ_CLIENT14', - 52: 'GL1C_PERF_SEL_REQ_CLIENT15', - 53: 'GL1C_PERF_SEL_REQ_CLIENT16', - 54: 'GL1C_PERF_SEL_REQ_CLIENT17', - 55: 'GL1C_PERF_SEL_REQ_CLIENT18', - 56: 'GL1C_PERF_SEL_REQ_CLIENT19', - 57: 'GL1C_PERF_SEL_REQ_CLIENT20', - 58: 'GL1C_PERF_SEL_REQ_CLIENT21', - 59: 'GL1C_PERF_SEL_REQ_CLIENT22', - 60: 'GL1C_PERF_SEL_REQ_CLIENT23', - 61: 'GL1C_PERF_SEL_REQ_CLIENT24', - 62: 'GL1C_PERF_SEL_REQ_CLIENT25', - 63: 'GL1C_PERF_SEL_REQ_CLIENT26', - 64: 'GL1C_PERF_SEL_REQ_CLIENT27', - 65: 'GL1C_PERF_SEL_UTCL0_REQUEST', - 66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', -} -GL1C_PERF_SEL_CYCLE = 0 -GL1C_PERF_SEL_BUSY = 1 -GL1C_PERF_SEL_STARVE = 2 -GL1C_PERF_SEL_ARB_RET_LEVEL = 3 -GL1C_PERF_SEL_GL2_REQ_READ = 4 -GL1C_PERF_SEL_GL2_REQ_READ_128B = 5 -GL1C_PERF_SEL_GL2_REQ_READ_32B = 6 -GL1C_PERF_SEL_GL2_REQ_READ_64B = 7 -GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8 -GL1C_PERF_SEL_GL2_REQ_WRITE = 9 -GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10 -GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11 -GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12 -GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13 -GL1C_PERF_SEL_REQ = 14 -GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15 -GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16 -GL1C_PERF_SEL_REQ_SHADER_INV = 17 -GL1C_PERF_SEL_REQ_MISS = 18 -GL1C_PERF_SEL_REQ_NOP_ACK = 19 -GL1C_PERF_SEL_REQ_NOP_RTN0 = 20 -GL1C_PERF_SEL_REQ_READ = 21 -GL1C_PERF_SEL_REQ_READ_128B = 22 -GL1C_PERF_SEL_REQ_READ_32B = 23 -GL1C_PERF_SEL_REQ_READ_64B = 24 -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25 -GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26 -GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27 -GL1C_PERF_SEL_REQ_WRITE = 28 -GL1C_PERF_SEL_REQ_WRITE_32B = 29 -GL1C_PERF_SEL_REQ_WRITE_64B = 30 -GL1C_PERF_SEL_STALL_GL2_GL1 = 31 -GL1C_PERF_SEL_STALL_LFIFO_FULL = 32 -GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33 -GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34 -GL1C_PERF_SEL_STALL_GCR_INV = 35 -GL1C_PERF_SEL_STALL_VM = 36 -GL1C_PERF_SEL_REQ_CLIENT0 = 37 -GL1C_PERF_SEL_REQ_CLIENT1 = 38 -GL1C_PERF_SEL_REQ_CLIENT2 = 39 -GL1C_PERF_SEL_REQ_CLIENT3 = 40 -GL1C_PERF_SEL_REQ_CLIENT4 = 41 -GL1C_PERF_SEL_REQ_CLIENT5 = 42 -GL1C_PERF_SEL_REQ_CLIENT6 = 43 -GL1C_PERF_SEL_REQ_CLIENT7 = 44 -GL1C_PERF_SEL_REQ_CLIENT8 = 45 -GL1C_PERF_SEL_REQ_CLIENT9 = 46 -GL1C_PERF_SEL_REQ_CLIENT10 = 47 -GL1C_PERF_SEL_REQ_CLIENT11 = 48 -GL1C_PERF_SEL_REQ_CLIENT12 = 49 -GL1C_PERF_SEL_REQ_CLIENT13 = 50 -GL1C_PERF_SEL_REQ_CLIENT14 = 51 -GL1C_PERF_SEL_REQ_CLIENT15 = 52 -GL1C_PERF_SEL_REQ_CLIENT16 = 53 -GL1C_PERF_SEL_REQ_CLIENT17 = 54 -GL1C_PERF_SEL_REQ_CLIENT18 = 55 -GL1C_PERF_SEL_REQ_CLIENT19 = 56 -GL1C_PERF_SEL_REQ_CLIENT20 = 57 -GL1C_PERF_SEL_REQ_CLIENT21 = 58 -GL1C_PERF_SEL_REQ_CLIENT22 = 59 -GL1C_PERF_SEL_REQ_CLIENT23 = 60 -GL1C_PERF_SEL_REQ_CLIENT24 = 61 -GL1C_PERF_SEL_REQ_CLIENT25 = 62 -GL1C_PERF_SEL_REQ_CLIENT26 = 63 -GL1C_PERF_SEL_REQ_CLIENT27 = 64 -GL1C_PERF_SEL_UTCL0_REQUEST = 65 -GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66 -GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67 -GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68 -GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69 -GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70 -GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71 -GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72 -GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73 -GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74 -GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75 -GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76 -GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77 -GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78 -GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79 -GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82 -GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83 -GL1C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL1H_REQ_PERF_SEL' -GL1H_REQ_PERF_SEL__enumvalues = { - 0: 'GL1H_REQ_PERF_SEL_BUSY', - 1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0', - 2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1', - 3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', - 4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', - 5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', - 6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', - 7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', - 8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', - 9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', - 10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', - 11: 'GL1H_REQ_PERF_SEL_CYCLE', -} -GL1H_REQ_PERF_SEL_BUSY = 0 -GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1 -GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2 -GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3 -GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4 -GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5 -GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6 -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7 -GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8 -GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9 -GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10 -GL1H_REQ_PERF_SEL_CYCLE = 11 -GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TA_PERFCOUNT_SEL' -TA_PERFCOUNT_SEL__enumvalues = { - 0: 'TA_PERF_SEL_NULL', - 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 7: 'TA_PERF_SEL_gradient_busy', - 8: 'TA_PERF_SEL_gradient_fifo_busy', - 9: 'TA_PERF_SEL_lod_busy', - 10: 'TA_PERF_SEL_lod_fifo_busy', - 11: 'TA_PERF_SEL_addresser_busy', - 12: 'TA_PERF_SEL_addresser_fifo_busy', - 13: 'TA_PERF_SEL_aligner_busy', - 14: 'TA_PERF_SEL_write_path_busy', - 15: 'TA_PERF_SEL_ta_busy', - 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', - 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', - 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', - 32: 'TA_PERF_SEL_total_wavefronts', - 33: 'TA_PERF_SEL_gradient_cycles', - 34: 'TA_PERF_SEL_walker_cycles', - 35: 'TA_PERF_SEL_aligner_cycles', - 36: 'TA_PERF_SEL_image_wavefronts', - 37: 'TA_PERF_SEL_image_read_wavefronts', - 38: 'TA_PERF_SEL_image_store_wavefronts', - 39: 'TA_PERF_SEL_image_atomic_wavefronts', - 40: 'TA_PERF_SEL_image_sampler_total_cycles', - 41: 'TA_PERF_SEL_image_nosampler_total_cycles', - 42: 'TA_PERF_SEL_flat_total_cycles', - 43: 'TA_PERF_SEL_bvh_total_cycles', - 44: 'TA_PERF_SEL_buffer_wavefronts', - 45: 'TA_PERF_SEL_buffer_load_wavefronts', - 46: 'TA_PERF_SEL_buffer_store_wavefronts', - 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', - 49: 'TA_PERF_SEL_buffer_total_cycles', - 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 52: 'TA_PERF_SEL_buffer_has_index_instructions', - 53: 'TA_PERF_SEL_buffer_has_offset_instructions', - 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 56: 'TA_PERF_SEL_image_sampler_wavefronts', - 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 58: 'TA_PERF_SEL_addresser_stalled_cycles', - 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 60: 'TA_PERF_SEL_aniso_stalled_cycles', - 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 62: 'TA_PERF_SEL_deriv_stalled_cycles', - 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 64: 'TA_PERF_SEL_color_1_cycle_quads', - 65: 'TA_PERF_SEL_color_2_cycle_quads', - 66: 'TA_PERF_SEL_color_3_cycle_quads', - 68: 'TA_PERF_SEL_mip_1_cycle_quads', - 69: 'TA_PERF_SEL_mip_2_cycle_quads', - 70: 'TA_PERF_SEL_vol_1_cycle_quads', - 71: 'TA_PERF_SEL_vol_2_cycle_quads', - 72: 'TA_PERF_SEL_sampler_op_quads', - 73: 'TA_PERF_SEL_mipmap_lod_0_samples', - 74: 'TA_PERF_SEL_mipmap_lod_1_samples', - 75: 'TA_PERF_SEL_mipmap_lod_2_samples', - 76: 'TA_PERF_SEL_mipmap_lod_3_samples', - 77: 'TA_PERF_SEL_mipmap_lod_4_samples', - 78: 'TA_PERF_SEL_mipmap_lod_5_samples', - 79: 'TA_PERF_SEL_mipmap_lod_6_samples', - 80: 'TA_PERF_SEL_mipmap_lod_7_samples', - 81: 'TA_PERF_SEL_mipmap_lod_8_samples', - 82: 'TA_PERF_SEL_mipmap_lod_9_samples', - 83: 'TA_PERF_SEL_mipmap_lod_10_samples', - 84: 'TA_PERF_SEL_mipmap_lod_11_samples', - 85: 'TA_PERF_SEL_mipmap_lod_12_samples', - 86: 'TA_PERF_SEL_mipmap_lod_13_samples', - 87: 'TA_PERF_SEL_mipmap_lod_14_samples', - 88: 'TA_PERF_SEL_mipmap_invalid_samples', - 89: 'TA_PERF_SEL_aniso_1_cycle_quads', - 90: 'TA_PERF_SEL_aniso_2_cycle_quads', - 91: 'TA_PERF_SEL_aniso_4_cycle_quads', - 92: 'TA_PERF_SEL_aniso_6_cycle_quads', - 93: 'TA_PERF_SEL_aniso_8_cycle_quads', - 94: 'TA_PERF_SEL_aniso_10_cycle_quads', - 95: 'TA_PERF_SEL_aniso_12_cycle_quads', - 96: 'TA_PERF_SEL_aniso_14_cycle_quads', - 97: 'TA_PERF_SEL_aniso_16_cycle_quads', - 98: 'TA_PERF_SEL_store_write_data_input_cycles', - 99: 'TA_PERF_SEL_store_write_data_output_cycles', - 100: 'TA_PERF_SEL_flat_wavefronts', - 101: 'TA_PERF_SEL_flat_load_wavefronts', - 102: 'TA_PERF_SEL_flat_store_wavefronts', - 103: 'TA_PERF_SEL_flat_atomic_wavefronts', - 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 105: 'TA_PERF_SEL_register_clk_valid_cycles', - 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', - 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 117: 'TA_PERF_SEL_store_has_x_instructions', - 118: 'TA_PERF_SEL_store_has_y_instructions', - 119: 'TA_PERF_SEL_store_has_z_instructions', - 120: 'TA_PERF_SEL_store_has_w_instructions', - 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 128: 'TA_PERF_SEL_in_busy', - 129: 'TA_PERF_SEL_in_fifos_busy', - 130: 'TA_PERF_SEL_in_cfifo_busy', - 131: 'TA_PERF_SEL_in_qfifo_busy', - 132: 'TA_PERF_SEL_in_wfifo_busy', - 133: 'TA_PERF_SEL_in_rfifo_busy', - 134: 'TA_PERF_SEL_bf_busy', - 135: 'TA_PERF_SEL_ns_busy', - 136: 'TA_PERF_SEL_smp_busy_ns_idle', - 137: 'TA_PERF_SEL_smp_idle_ns_busy', - 144: 'TA_PERF_SEL_vmemcmd_cycles', - 145: 'TA_PERF_SEL_vmemreq_cycles', - 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', - 150: 'TA_PERF_SEL_in_addr_cycles', - 151: 'TA_PERF_SEL_in_data_cycles', - 154: 'TA_PERF_SEL_latency_ram_weights_written_cycles', - 155: 'TA_PERF_SEL_latency_ram_ws_required_quads', - 156: 'TA_PERF_SEL_latency_ram_whv_required_quads', - 157: 'TA_PERF_SEL_latency_ram_ws_required_instructions', - 158: 'TA_PERF_SEL_latency_ram_whv_required_instructions', - 159: 'TA_PERF_SEL_latency_ram_ref_required_instructions', - 160: 'TA_PERF_SEL_point_sampled_quads', - 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', - 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', - 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri', - 177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri', - 178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri', - 179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', - 180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', - 181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', - 182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', - 183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', - 184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', - 185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', - 186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', - 187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', - 188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', - 189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', - 190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', - 191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', - 192: 'TA_PERF_SEL_image_sampler_1_op_burst', - 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 196: 'TA_PERF_SEL_image_linked_1_op_burst', - 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', - 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', - 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', - 200: 'TA_PERF_SEL_image_bvh_1_op_burst', - 201: 'TA_PERF_SEL_image_bvh_2to3_op_burst', - 202: 'TA_PERF_SEL_image_bvh_4to7_op_burst', - 203: 'TA_PERF_SEL_image_bvh_ge8_op_burst', - 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', - 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', - 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 212: 'TA_PERF_SEL_write_1_op_burst', - 213: 'TA_PERF_SEL_write_2to3_op_burst', - 214: 'TA_PERF_SEL_write_4to31_op_burst', - 215: 'TA_PERF_SEL_write_ge32_op_burst', - 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', - 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', - 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', - 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', - 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', - 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', - 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', - 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', -} -TA_PERF_SEL_NULL = 0 -TA_PERF_SEL_image_sampler_has_offset_instructions = 1 -TA_PERF_SEL_image_sampler_has_bias_instructions = 2 -TA_PERF_SEL_image_sampler_has_reference_instructions = 3 -TA_PERF_SEL_image_sampler_has_ds_instructions = 4 -TA_PERF_SEL_image_sampler_has_dt_instructions = 5 -TA_PERF_SEL_image_sampler_has_dr_instructions = 6 -TA_PERF_SEL_gradient_busy = 7 -TA_PERF_SEL_gradient_fifo_busy = 8 -TA_PERF_SEL_lod_busy = 9 -TA_PERF_SEL_lod_fifo_busy = 10 -TA_PERF_SEL_addresser_busy = 11 -TA_PERF_SEL_addresser_fifo_busy = 12 -TA_PERF_SEL_aligner_busy = 13 -TA_PERF_SEL_write_path_busy = 14 -TA_PERF_SEL_ta_busy = 15 -TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 -TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 -TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 -TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 -TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 -TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 -TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 -TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 -TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 -TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 -TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 -TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 -TA_PERF_SEL_image_sampler_has_t_instructions = 28 -TA_PERF_SEL_image_sampler_has_r_instructions = 29 -TA_PERF_SEL_image_sampler_has_q_instructions = 30 -TA_PERF_SEL_total_wavefronts = 32 -TA_PERF_SEL_gradient_cycles = 33 -TA_PERF_SEL_walker_cycles = 34 -TA_PERF_SEL_aligner_cycles = 35 -TA_PERF_SEL_image_wavefronts = 36 -TA_PERF_SEL_image_read_wavefronts = 37 -TA_PERF_SEL_image_store_wavefronts = 38 -TA_PERF_SEL_image_atomic_wavefronts = 39 -TA_PERF_SEL_image_sampler_total_cycles = 40 -TA_PERF_SEL_image_nosampler_total_cycles = 41 -TA_PERF_SEL_flat_total_cycles = 42 -TA_PERF_SEL_bvh_total_cycles = 43 -TA_PERF_SEL_buffer_wavefronts = 44 -TA_PERF_SEL_buffer_load_wavefronts = 45 -TA_PERF_SEL_buffer_store_wavefronts = 46 -TA_PERF_SEL_buffer_atomic_wavefronts = 47 -TA_PERF_SEL_buffer_total_cycles = 49 -TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 -TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 -TA_PERF_SEL_buffer_has_index_instructions = 52 -TA_PERF_SEL_buffer_has_offset_instructions = 53 -TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 -TA_PERF_SEL_addr_stalled_by_td_cycles = 55 -TA_PERF_SEL_image_sampler_wavefronts = 56 -TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 -TA_PERF_SEL_addresser_stalled_cycles = 58 -TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 -TA_PERF_SEL_aniso_stalled_cycles = 60 -TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 -TA_PERF_SEL_deriv_stalled_cycles = 62 -TA_PERF_SEL_aniso_gt1_cycle_quads = 63 -TA_PERF_SEL_color_1_cycle_quads = 64 -TA_PERF_SEL_color_2_cycle_quads = 65 -TA_PERF_SEL_color_3_cycle_quads = 66 -TA_PERF_SEL_mip_1_cycle_quads = 68 -TA_PERF_SEL_mip_2_cycle_quads = 69 -TA_PERF_SEL_vol_1_cycle_quads = 70 -TA_PERF_SEL_vol_2_cycle_quads = 71 -TA_PERF_SEL_sampler_op_quads = 72 -TA_PERF_SEL_mipmap_lod_0_samples = 73 -TA_PERF_SEL_mipmap_lod_1_samples = 74 -TA_PERF_SEL_mipmap_lod_2_samples = 75 -TA_PERF_SEL_mipmap_lod_3_samples = 76 -TA_PERF_SEL_mipmap_lod_4_samples = 77 -TA_PERF_SEL_mipmap_lod_5_samples = 78 -TA_PERF_SEL_mipmap_lod_6_samples = 79 -TA_PERF_SEL_mipmap_lod_7_samples = 80 -TA_PERF_SEL_mipmap_lod_8_samples = 81 -TA_PERF_SEL_mipmap_lod_9_samples = 82 -TA_PERF_SEL_mipmap_lod_10_samples = 83 -TA_PERF_SEL_mipmap_lod_11_samples = 84 -TA_PERF_SEL_mipmap_lod_12_samples = 85 -TA_PERF_SEL_mipmap_lod_13_samples = 86 -TA_PERF_SEL_mipmap_lod_14_samples = 87 -TA_PERF_SEL_mipmap_invalid_samples = 88 -TA_PERF_SEL_aniso_1_cycle_quads = 89 -TA_PERF_SEL_aniso_2_cycle_quads = 90 -TA_PERF_SEL_aniso_4_cycle_quads = 91 -TA_PERF_SEL_aniso_6_cycle_quads = 92 -TA_PERF_SEL_aniso_8_cycle_quads = 93 -TA_PERF_SEL_aniso_10_cycle_quads = 94 -TA_PERF_SEL_aniso_12_cycle_quads = 95 -TA_PERF_SEL_aniso_14_cycle_quads = 96 -TA_PERF_SEL_aniso_16_cycle_quads = 97 -TA_PERF_SEL_store_write_data_input_cycles = 98 -TA_PERF_SEL_store_write_data_output_cycles = 99 -TA_PERF_SEL_flat_wavefronts = 100 -TA_PERF_SEL_flat_load_wavefronts = 101 -TA_PERF_SEL_flat_store_wavefronts = 102 -TA_PERF_SEL_flat_atomic_wavefronts = 103 -TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 -TA_PERF_SEL_register_clk_valid_cycles = 105 -TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 -TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 -TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108 -TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 -TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 -TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 -TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 -TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 -TA_PERF_SEL_store_has_x_instructions = 117 -TA_PERF_SEL_store_has_y_instructions = 118 -TA_PERF_SEL_store_has_z_instructions = 119 -TA_PERF_SEL_store_has_w_instructions = 120 -TA_PERF_SEL_image_nosampler_has_t_instructions = 121 -TA_PERF_SEL_image_nosampler_has_r_instructions = 122 -TA_PERF_SEL_image_nosampler_has_q_instructions = 123 -TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 -TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 -TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 -TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 -TA_PERF_SEL_in_busy = 128 -TA_PERF_SEL_in_fifos_busy = 129 -TA_PERF_SEL_in_cfifo_busy = 130 -TA_PERF_SEL_in_qfifo_busy = 131 -TA_PERF_SEL_in_wfifo_busy = 132 -TA_PERF_SEL_in_rfifo_busy = 133 -TA_PERF_SEL_bf_busy = 134 -TA_PERF_SEL_ns_busy = 135 -TA_PERF_SEL_smp_busy_ns_idle = 136 -TA_PERF_SEL_smp_idle_ns_busy = 137 -TA_PERF_SEL_vmemcmd_cycles = 144 -TA_PERF_SEL_vmemreq_cycles = 145 -TA_PERF_SEL_in_waiting_on_req_cycles = 146 -TA_PERF_SEL_in_addr_cycles = 150 -TA_PERF_SEL_in_data_cycles = 151 -TA_PERF_SEL_latency_ram_weights_written_cycles = 154 -TA_PERF_SEL_latency_ram_ws_required_quads = 155 -TA_PERF_SEL_latency_ram_whv_required_quads = 156 -TA_PERF_SEL_latency_ram_ws_required_instructions = 157 -TA_PERF_SEL_latency_ram_whv_required_instructions = 158 -TA_PERF_SEL_latency_ram_ref_required_instructions = 159 -TA_PERF_SEL_point_sampled_quads = 160 -TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 -TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 -TA_PERF_SEL_atomic_write_data_input_cycles = 164 -TA_PERF_SEL_atomic_write_data_output_cycles = 165 -TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 -TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 -TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 -TA_PERF_SEL_num_of_bvh_valid_first_tri = 176 -TA_PERF_SEL_num_of_bvh_valid_second_tri = 177 -TA_PERF_SEL_num_of_bvh_valid_third_tri = 178 -TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179 -TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180 -TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181 -TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182 -TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183 -TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184 -TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185 -TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186 -TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187 -TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188 -TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189 -TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190 -TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191 -TA_PERF_SEL_image_sampler_1_op_burst = 192 -TA_PERF_SEL_image_sampler_2to3_op_burst = 193 -TA_PERF_SEL_image_sampler_4to7_op_burst = 194 -TA_PERF_SEL_image_sampler_ge8_op_burst = 195 -TA_PERF_SEL_image_linked_1_op_burst = 196 -TA_PERF_SEL_image_linked_2to3_op_burst = 197 -TA_PERF_SEL_image_linked_4to7_op_burst = 198 -TA_PERF_SEL_image_linked_ge8_op_burst = 199 -TA_PERF_SEL_image_bvh_1_op_burst = 200 -TA_PERF_SEL_image_bvh_2to3_op_burst = 201 -TA_PERF_SEL_image_bvh_4to7_op_burst = 202 -TA_PERF_SEL_image_bvh_ge8_op_burst = 203 -TA_PERF_SEL_image_nosampler_1_op_burst = 204 -TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 -TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 -TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 -TA_PERF_SEL_buffer_flat_1_op_burst = 208 -TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 -TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 -TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 -TA_PERF_SEL_write_1_op_burst = 212 -TA_PERF_SEL_write_2to3_op_burst = 213 -TA_PERF_SEL_write_4to31_op_burst = 214 -TA_PERF_SEL_write_ge32_op_burst = 215 -TA_PERF_SEL_ibubble_1_cycle_burst = 216 -TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 -TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 -TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 -TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 -TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 -TA_PERF_SEL_sampler_clk_valid_cycles = 224 -TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 -TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 -TA_PERF_SEL_write_data_clk_valid_cycles = 227 -TA_PERF_SEL_gradient_clk_valid_cycles = 228 -TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 -TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 -TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 -TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 -TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 -TA_PERF_SEL_aligner_clk_valid_cycles = 234 -TA_PERF_SEL_tcreq_clk_valid_cycles = 235 -TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BC_SWIZZLE' -TEX_BC_SWIZZLE__enumvalues = { - 0: 'TEX_BC_Swizzle_XYZW', - 1: 'TEX_BC_Swizzle_XWYZ', - 2: 'TEX_BC_Swizzle_WZYX', - 3: 'TEX_BC_Swizzle_WXYZ', - 4: 'TEX_BC_Swizzle_ZYXW', - 5: 'TEX_BC_Swizzle_YXWZ', -} -TEX_BC_Swizzle_XYZW = 0 -TEX_BC_Swizzle_XWYZ = 1 -TEX_BC_Swizzle_WZYX = 2 -TEX_BC_Swizzle_WXYZ = 3 -TEX_BC_Swizzle_ZYXW = 4 -TEX_BC_Swizzle_YXWZ = 5 -TEX_BC_SWIZZLE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_BORDER_COLOR_TYPE' -TEX_BORDER_COLOR_TYPE__enumvalues = { - 0: 'TEX_BorderColor_TransparentBlack', - 1: 'TEX_BorderColor_OpaqueBlack', - 2: 'TEX_BorderColor_OpaqueWhite', - 3: 'TEX_BorderColor_Register', -} -TEX_BorderColor_TransparentBlack = 0 -TEX_BorderColor_OpaqueBlack = 1 -TEX_BorderColor_OpaqueWhite = 2 -TEX_BorderColor_Register = 3 -TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CHROMA_KEY' -TEX_CHROMA_KEY__enumvalues = { - 0: 'TEX_ChromaKey_Disabled', - 1: 'TEX_ChromaKey_Kill', - 2: 'TEX_ChromaKey_Blend', - 3: 'TEX_ChromaKey_RESERVED_3', -} -TEX_ChromaKey_Disabled = 0 -TEX_ChromaKey_Kill = 1 -TEX_ChromaKey_Blend = 2 -TEX_ChromaKey_RESERVED_3 = 3 -TEX_CHROMA_KEY = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_CLAMP' -TEX_CLAMP__enumvalues = { - 0: 'TEX_Clamp_Repeat', - 1: 'TEX_Clamp_Mirror', - 2: 'TEX_Clamp_ClampToLast', - 3: 'TEX_Clamp_MirrorOnceToLast', - 4: 'TEX_Clamp_ClampHalfToBorder', - 5: 'TEX_Clamp_MirrorOnceHalfToBorder', - 6: 'TEX_Clamp_ClampToBorder', - 7: 'TEX_Clamp_MirrorOnceToBorder', -} -TEX_Clamp_Repeat = 0 -TEX_Clamp_Mirror = 1 -TEX_Clamp_ClampToLast = 2 -TEX_Clamp_MirrorOnceToLast = 3 -TEX_Clamp_ClampHalfToBorder = 4 -TEX_Clamp_MirrorOnceHalfToBorder = 5 -TEX_Clamp_ClampToBorder = 6 -TEX_Clamp_MirrorOnceToBorder = 7 -TEX_CLAMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_COORD_TYPE' -TEX_COORD_TYPE__enumvalues = { - 0: 'TEX_CoordType_Unnormalized', - 1: 'TEX_CoordType_Normalized', -} -TEX_CoordType_Unnormalized = 0 -TEX_CoordType_Normalized = 1 -TEX_COORD_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' -TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { - 0: 'TEX_DepthCompareFunction_Never', - 1: 'TEX_DepthCompareFunction_Less', - 2: 'TEX_DepthCompareFunction_Equal', - 3: 'TEX_DepthCompareFunction_LessEqual', - 4: 'TEX_DepthCompareFunction_Greater', - 5: 'TEX_DepthCompareFunction_NotEqual', - 6: 'TEX_DepthCompareFunction_GreaterEqual', - 7: 'TEX_DepthCompareFunction_Always', -} -TEX_DepthCompareFunction_Never = 0 -TEX_DepthCompareFunction_Less = 1 -TEX_DepthCompareFunction_Equal = 2 -TEX_DepthCompareFunction_LessEqual = 3 -TEX_DepthCompareFunction_Greater = 4 -TEX_DepthCompareFunction_NotEqual = 5 -TEX_DepthCompareFunction_GreaterEqual = 6 -TEX_DepthCompareFunction_Always = 7 -TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_FORMAT_COMP' -TEX_FORMAT_COMP__enumvalues = { - 0: 'TEX_FormatComp_Unsigned', - 1: 'TEX_FormatComp_Signed', - 2: 'TEX_FormatComp_UnsignedBiased', - 3: 'TEX_FormatComp_RESERVED_3', -} -TEX_FormatComp_Unsigned = 0 -TEX_FormatComp_Signed = 1 -TEX_FormatComp_UnsignedBiased = 2 -TEX_FormatComp_RESERVED_3 = 3 -TEX_FORMAT_COMP = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MAX_ANISO_RATIO' -TEX_MAX_ANISO_RATIO__enumvalues = { - 0: 'TEX_MaxAnisoRatio_1to1', - 1: 'TEX_MaxAnisoRatio_2to1', - 2: 'TEX_MaxAnisoRatio_4to1', - 3: 'TEX_MaxAnisoRatio_8to1', - 4: 'TEX_MaxAnisoRatio_16to1', - 5: 'TEX_MaxAnisoRatio_RESERVED_5', - 6: 'TEX_MaxAnisoRatio_RESERVED_6', - 7: 'TEX_MaxAnisoRatio_RESERVED_7', -} -TEX_MaxAnisoRatio_1to1 = 0 -TEX_MaxAnisoRatio_2to1 = 1 -TEX_MaxAnisoRatio_4to1 = 2 -TEX_MaxAnisoRatio_8to1 = 3 -TEX_MaxAnisoRatio_16to1 = 4 -TEX_MaxAnisoRatio_RESERVED_5 = 5 -TEX_MaxAnisoRatio_RESERVED_6 = 6 -TEX_MaxAnisoRatio_RESERVED_7 = 7 -TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_MIP_FILTER' -TEX_MIP_FILTER__enumvalues = { - 0: 'TEX_MipFilter_None', - 1: 'TEX_MipFilter_Point', - 2: 'TEX_MipFilter_Linear', - 3: 'TEX_MipFilter_Point_Aniso_Adj', -} -TEX_MipFilter_None = 0 -TEX_MipFilter_Point = 1 -TEX_MipFilter_Linear = 2 -TEX_MipFilter_Point_Aniso_Adj = 3 -TEX_MIP_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_REQUEST_SIZE' -TEX_REQUEST_SIZE__enumvalues = { - 0: 'TEX_RequestSize_32B', - 1: 'TEX_RequestSize_64B', - 2: 'TEX_RequestSize_128B', - 3: 'TEX_RequestSize_2X64B', -} -TEX_RequestSize_32B = 0 -TEX_RequestSize_64B = 1 -TEX_RequestSize_128B = 2 -TEX_RequestSize_2X64B = 3 -TEX_REQUEST_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_SAMPLER_TYPE' -TEX_SAMPLER_TYPE__enumvalues = { - 0: 'TEX_SamplerType_Invalid', - 1: 'TEX_SamplerType_Valid', -} -TEX_SamplerType_Invalid = 0 -TEX_SamplerType_Valid = 1 -TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_XY_FILTER' -TEX_XY_FILTER__enumvalues = { - 0: 'TEX_XYFilter_Point', - 1: 'TEX_XYFilter_Linear', - 2: 'TEX_XYFilter_AnisoPoint', - 3: 'TEX_XYFilter_AnisoLinear', -} -TEX_XYFilter_Point = 0 -TEX_XYFilter_Linear = 1 -TEX_XYFilter_AnisoPoint = 2 -TEX_XYFilter_AnisoLinear = 3 -TEX_XY_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TEX_Z_FILTER' -TEX_Z_FILTER__enumvalues = { - 0: 'TEX_ZFilter_None', - 1: 'TEX_ZFilter_Point', - 2: 'TEX_ZFilter_Linear', - 3: 'TEX_ZFilter_RESERVED_3', -} -TEX_ZFilter_None = 0 -TEX_ZFilter_Point = 1 -TEX_ZFilter_Linear = 2 -TEX_ZFilter_RESERVED_3 = 3 -TEX_Z_FILTER = ctypes.c_uint32 # enum - -# values for enumeration 'TVX_TYPE' -TVX_TYPE__enumvalues = { - 0: 'TVX_Type_InvalidTextureResource', - 1: 'TVX_Type_InvalidVertexBuffer', - 2: 'TVX_Type_ValidTextureResource', - 3: 'TVX_Type_ValidVertexBuffer', -} -TVX_Type_InvalidTextureResource = 0 -TVX_Type_InvalidVertexBuffer = 1 -TVX_Type_ValidTextureResource = 2 -TVX_Type_ValidVertexBuffer = 3 -TVX_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_ADDR_MODES' -TA_TC_ADDR_MODES__enumvalues = { - 0: 'TA_TC_ADDR_MODE_DEFAULT', - 1: 'TA_TC_ADDR_MODE_COMP0', - 2: 'TA_TC_ADDR_MODE_COMP1', - 3: 'TA_TC_ADDR_MODE_COMP2', - 4: 'TA_TC_ADDR_MODE_COMP3', - 5: 'TA_TC_ADDR_MODE_UNALIGNED', - 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', -} -TA_TC_ADDR_MODE_DEFAULT = 0 -TA_TC_ADDR_MODE_COMP0 = 1 -TA_TC_ADDR_MODE_COMP1 = 2 -TA_TC_ADDR_MODE_COMP2 = 3 -TA_TC_ADDR_MODE_COMP3 = 4 -TA_TC_ADDR_MODE_UNALIGNED = 5 -TA_TC_ADDR_MODE_BORDER_COLOR = 6 -TA_TC_ADDR_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TA_TC_REQ_MODES' -TA_TC_REQ_MODES__enumvalues = { - 0: 'TA_TC_REQ_MODE_BORDER', - 1: 'TA_TC_REQ_MODE_TEX2', - 2: 'TA_TC_REQ_MODE_TEX1', - 3: 'TA_TC_REQ_MODE_TEX0', - 4: 'TA_TC_REQ_MODE_NORMAL', - 5: 'TA_TC_REQ_MODE_DWORD', - 6: 'TA_TC_REQ_MODE_BYTE', - 7: 'TA_TC_REQ_MODE_BYTE_NV', -} -TA_TC_REQ_MODE_BORDER = 0 -TA_TC_REQ_MODE_TEX2 = 1 -TA_TC_REQ_MODE_TEX1 = 2 -TA_TC_REQ_MODE_TEX0 = 3 -TA_TC_REQ_MODE_NORMAL = 4 -TA_TC_REQ_MODE_DWORD = 5 -TA_TC_REQ_MODE_BYTE = 6 -TA_TC_REQ_MODE_BYTE_NV = 7 -TA_TC_REQ_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_POLICIES' -TCP_CACHE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_POLICY_MISS_LRU', - 1: 'TCP_CACHE_POLICY_MISS_EVICT', - 2: 'TCP_CACHE_POLICY_HIT_LRU', - 3: 'TCP_CACHE_POLICY_HIT_EVICT', -} -TCP_CACHE_POLICY_MISS_LRU = 0 -TCP_CACHE_POLICY_MISS_EVICT = 1 -TCP_CACHE_POLICY_HIT_LRU = 2 -TCP_CACHE_POLICY_HIT_EVICT = 3 -TCP_CACHE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_CACHE_STORE_POLICIES' -TCP_CACHE_STORE_POLICIES__enumvalues = { - 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', - 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', -} -TCP_CACHE_STORE_POLICY_WT_LRU = 0 -TCP_CACHE_STORE_POLICY_WT_EVICT = 1 -TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_DATA_SEL' -TCP_DSM_DATA_SEL__enumvalues = { - 0: 'TCP_DSM_DISABLE', - 1: 'TCP_DSM_SEL0', - 2: 'TCP_DSM_SEL1', - 3: 'TCP_DSM_SEL_BOTH', -} -TCP_DSM_DISABLE = 0 -TCP_DSM_SEL0 = 1 -TCP_DSM_SEL1 = 2 -TCP_DSM_SEL_BOTH = 3 -TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_INJECT_SEL' -TCP_DSM_INJECT_SEL__enumvalues = { - 0: 'TCP_DSM_INJECT_SEL0', - 1: 'TCP_DSM_INJECT_SEL1', - 2: 'TCP_DSM_INJECT_SEL2', - 3: 'TCP_DSM_INJECT_SEL3', -} -TCP_DSM_INJECT_SEL0 = 0 -TCP_DSM_INJECT_SEL1 = 1 -TCP_DSM_INJECT_SEL2 = 2 -TCP_DSM_INJECT_SEL3 = 3 -TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_DSM_SINGLE_WRITE' -TCP_DSM_SINGLE_WRITE__enumvalues = { - 0: 'TCP_DSM_SINGLE_WRITE_DIS', - 1: 'TCP_DSM_SINGLE_WRITE_EN', -} -TCP_DSM_SINGLE_WRITE_DIS = 0 -TCP_DSM_SINGLE_WRITE_EN = 1 -TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_OPCODE_TYPE' -TCP_OPCODE_TYPE__enumvalues = { - 0: 'TCP_OPCODE_READ', - 1: 'TCP_OPCODE_WRITE', - 2: 'TCP_OPCODE_ATOMIC', - 3: 'TCP_OPCODE_INV', - 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', - 5: 'TCP_OPCODE_SAMPLER', - 6: 'TCP_OPCODE_LOAD', - 7: 'TCP_OPCODE_GATHERH', -} -TCP_OPCODE_READ = 0 -TCP_OPCODE_WRITE = 1 -TCP_OPCODE_ATOMIC = 2 -TCP_OPCODE_INV = 3 -TCP_OPCODE_ATOMIC_CMPSWAP = 4 -TCP_OPCODE_SAMPLER = 5 -TCP_OPCODE_LOAD = 6 -TCP_OPCODE_GATHERH = 7 -TCP_OPCODE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_PERFCOUNT_SELECT' -TCP_PERFCOUNT_SELECT__enumvalues = { - 0: 'TCP_PERF_SEL_GATE_EN1', - 1: 'TCP_PERF_SEL_GATE_EN2', - 2: 'TCP_PERF_SEL_TA_REQ', - 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', - 4: 'TCP_PERF_SEL_TA_REQ_READ', - 5: 'TCP_PERF_SEL_TA_REQ_WRITE', - 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', - 9: 'TCP_PERF_SEL_REQ', - 10: 'TCP_PERF_SEL_REQ_READ', - 11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', - 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 14: 'TCP_PERF_SEL_REQ_WRITE', - 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', - 17: 'TCP_PERF_SEL_REQ_NON_READ', - 18: 'TCP_PERF_SEL_REQ_MISS', - 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', - 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', - 31: 'TCP_PERF_SEL_GL1_REQ_READ', - 32: 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 33: 'TCP_PERF_SEL_GL1_REQ_READ_64B', - 34: 'TCP_PERF_SEL_GL1_REQ_WRITE', - 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 37: 'TCP_PERF_SEL_GL1_READ_LATENCY', - 38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', - 39: 'TCP_PERF_SEL_TCP_LATENCY', - 40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', - 42: 'TCP_PERF_SEL_DATA_FIFO_STALL', - 43: 'TCP_PERF_SEL_LOD_STALL', - 44: 'TCP_PERF_SEL_POWER_STALL', - 45: 'TCP_PERF_SEL_ALLOC_STALL', - 46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', - 48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', - 49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 50: 'TCP_PERF_SEL_LFIFO_STALL', - 51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 55: 'TCP_PERF_SEL_GL1_PENDING_STALL', - 56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', - 57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', - 58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', - 59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 62: 'TCP_PERF_SEL_TD_TCP_STALL', -} -TCP_PERF_SEL_GATE_EN1 = 0 -TCP_PERF_SEL_GATE_EN2 = 1 -TCP_PERF_SEL_TA_REQ = 2 -TCP_PERF_SEL_TA_REQ_STATE_READ = 3 -TCP_PERF_SEL_TA_REQ_READ = 4 -TCP_PERF_SEL_TA_REQ_WRITE = 5 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 -TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 -TCP_PERF_SEL_TA_REQ_GL0_INV = 8 -TCP_PERF_SEL_REQ = 9 -TCP_PERF_SEL_REQ_READ = 10 -TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11 -TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 -TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 -TCP_PERF_SEL_REQ_WRITE = 14 -TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 -TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16 -TCP_PERF_SEL_REQ_NON_READ = 17 -TCP_PERF_SEL_REQ_MISS = 18 -TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19 -TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20 -TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21 -TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22 -TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23 -TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24 -TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25 -TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26 -TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27 -TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28 -TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29 -TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30 -TCP_PERF_SEL_GL1_REQ_READ = 31 -TCP_PERF_SEL_GL1_REQ_READ_128B = 32 -TCP_PERF_SEL_GL1_REQ_READ_64B = 33 -TCP_PERF_SEL_GL1_REQ_WRITE = 34 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35 -TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36 -TCP_PERF_SEL_GL1_READ_LATENCY = 37 -TCP_PERF_SEL_GL1_WRITE_LATENCY = 38 -TCP_PERF_SEL_TCP_LATENCY = 39 -TCP_PERF_SEL_TCP_TA_REQ_STALL = 40 -TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41 -TCP_PERF_SEL_DATA_FIFO_STALL = 42 -TCP_PERF_SEL_LOD_STALL = 43 -TCP_PERF_SEL_POWER_STALL = 44 -TCP_PERF_SEL_ALLOC_STALL = 45 -TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46 -TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47 -TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48 -TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49 -TCP_PERF_SEL_LFIFO_STALL = 50 -TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51 -TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52 -TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53 -TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54 -TCP_PERF_SEL_GL1_PENDING_STALL = 55 -TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56 -TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57 -TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58 -TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59 -TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60 -TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61 -TCP_PERF_SEL_TD_TCP_STALL = 62 -TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'TCP_WATCH_MODES' -TCP_WATCH_MODES__enumvalues = { - 0: 'TCP_WATCH_MODE_READ', - 1: 'TCP_WATCH_MODE_NONREAD', - 2: 'TCP_WATCH_MODE_ATOMIC', - 3: 'TCP_WATCH_MODE_ALL', -} -TCP_WATCH_MODE_READ = 0 -TCP_WATCH_MODE_NONREAD = 1 -TCP_WATCH_MODE_ATOMIC = 2 -TCP_WATCH_MODE_ALL = 3 -TCP_WATCH_MODES = ctypes.c_uint32 # enum - -# values for enumeration 'TD_PERFCOUNT_SEL' -TD_PERFCOUNT_SEL__enumvalues = { - 0: 'TD_PERF_SEL_none', - 1: 'TD_PERF_SEL_td_busy', - 2: 'TD_PERF_SEL_input_busy', - 3: 'TD_PERF_SEL_sampler_lerp_busy', - 4: 'TD_PERF_SEL_sampler_out_busy', - 5: 'TD_PERF_SEL_nofilter_busy', - 6: 'TD_PERF_SEL_ray_tracing_bvh4_busy', - 7: 'TD_PERF_SEL_sampler_core_sclk_en', - 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', - 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', - 12: 'TD_PERF_SEL_sampler_accum_sclk_en', - 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 15: 'TD_PERF_SEL_sampler_out_sclk_en', - 16: 'TD_PERF_SEL_nofilter_sclk_en', - 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', - 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', - 22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', - 23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', - 24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', - 25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', - 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', - 30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', - 31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', - 32: 'TD_PERF_SEL_core_state_ram_max_cnt', - 33: 'TD_PERF_SEL_core_state_rams_read', - 34: 'TD_PERF_SEL_weight_data_rams_read', - 35: 'TD_PERF_SEL_reference_data_rams_read', - 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', - 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', - 38: 'TD_PERF_SEL_tc_td_data_fifo_full', - 39: 'TD_PERF_SEL_input_state_fifo_full', - 40: 'TD_PERF_SEL_ta_data_stall', - 41: 'TD_PERF_SEL_tc_data_stall', - 42: 'TD_PERF_SEL_tc_ram_stall', - 43: 'TD_PERF_SEL_lds_stall', - 44: 'TD_PERF_SEL_sampler_pkr_full', - 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 46: 'TD_PERF_SEL_nofilter_pkr_full', - 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', - 49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', - 50: 'TD_PERF_SEL_gather4_instr', - 51: 'TD_PERF_SEL_gather4h_instr', - 54: 'TD_PERF_SEL_sample_instr', - 55: 'TD_PERF_SEL_sample_c_instr', - 56: 'TD_PERF_SEL_load_instr', - 57: 'TD_PERF_SEL_ldfptr_instr', - 58: 'TD_PERF_SEL_write_ack_instr', - 59: 'TD_PERF_SEL_d16_en_instr', - 60: 'TD_PERF_SEL_bypassLerp_instr', - 61: 'TD_PERF_SEL_min_max_filter_instr', - 62: 'TD_PERF_SEL_one_comp_return_instr', - 63: 'TD_PERF_SEL_two_comp_return_instr', - 64: 'TD_PERF_SEL_three_comp_return_instr', - 65: 'TD_PERF_SEL_four_comp_return_instr', - 66: 'TD_PERF_SEL_user_defined_border', - 67: 'TD_PERF_SEL_white_border', - 68: 'TD_PERF_SEL_opaque_black_border', - 69: 'TD_PERF_SEL_lod_warn_from_ta', - 70: 'TD_PERF_SEL_instruction_dest_is_lds', - 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 75: 'TD_PERF_SEL_out_of_order_instr', - 76: 'TD_PERF_SEL_total_num_instr', - 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 78: 'TD_PERF_SEL_total_num_sampler_instr', - 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 80: 'TD_PERF_SEL_total_num_nofilter_instr', - 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', - 83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', - 84: 'TD_PERF_SEL_mixmode_instr', - 85: 'TD_PERF_SEL_mixmode_resource', - 86: 'TD_PERF_SEL_status_packet', - 87: 'TD_PERF_SEL_address_cmd_poison', - 88: 'TD_PERF_SEL_data_poison', - 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 91: 'TD_PERF_SEL_done_scoreboard_not_empty', - 92: 'TD_PERF_SEL_done_scoreboard_is_full', - 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', - 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', - 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 99: 'TD_PERF_SEL_msaa_load_instr', - 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 101: 'TD_PERF_SEL_blend_prt_with_prt_default_1', - 102: 'TD_PERF_SEL_resmap_instr', - 103: 'TD_PERF_SEL_prt_ack_instr', - 104: 'TD_PERF_SEL_resmap_with_volume_filtering', - 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', - 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', - 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', - 108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', - 109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', - 110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', - 111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', - 112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', - 113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', - 114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', - 115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', - 116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', - 117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', - 118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', - 119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', - 120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', - 121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', - 122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', - 123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', - 124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', - 125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', - 126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', - 127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', - 128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', - 129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', - 130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', - 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 136: 'TD_PERF_SEL_burst_bin_sampler_1', - 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', - 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', - 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', - 140: 'TD_PERF_SEL_burst_bin_gather_1', - 141: 'TD_PERF_SEL_burst_bin_gather_2to8', - 142: 'TD_PERF_SEL_burst_bin_gather_9to16', - 143: 'TD_PERF_SEL_burst_bin_gather_gt16', - 144: 'TD_PERF_SEL_burst_bin_nofilter_1', - 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 149: 'TD_PERF_SEL_burst_bin_bvh4_1', - 150: 'TD_PERF_SEL_burst_bin_bvh4_2to8', - 151: 'TD_PERF_SEL_burst_bin_bvh4_9to16', - 152: 'TD_PERF_SEL_burst_bin_bvh4_gt16', - 153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', - 154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', - 155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', - 156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', - 157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', - 158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', - 159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', - 160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', - 161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', - 162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', - 163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', - 164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', - 165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', - 166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', - 167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', - 168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', - 169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', - 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 181: 'TD_PERF_SEL_sampler_lerp0_active', - 182: 'TD_PERF_SEL_sampler_lerp1_active', - 183: 'TD_PERF_SEL_sampler_lerp2_active', - 184: 'TD_PERF_SEL_sampler_lerp3_active', - 185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', - 186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', -} -TD_PERF_SEL_none = 0 -TD_PERF_SEL_td_busy = 1 -TD_PERF_SEL_input_busy = 2 -TD_PERF_SEL_sampler_lerp_busy = 3 -TD_PERF_SEL_sampler_out_busy = 4 -TD_PERF_SEL_nofilter_busy = 5 -TD_PERF_SEL_ray_tracing_bvh4_busy = 6 -TD_PERF_SEL_sampler_core_sclk_en = 7 -TD_PERF_SEL_sampler_preformatter_sclk_en = 8 -TD_PERF_SEL_sampler_bilerp_sclk_en = 9 -TD_PERF_SEL_sampler_bypass_sclk_en = 10 -TD_PERF_SEL_sampler_minmax_sclk_en = 11 -TD_PERF_SEL_sampler_accum_sclk_en = 12 -TD_PERF_SEL_sampler_format_flt_sclk_en = 13 -TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 -TD_PERF_SEL_sampler_out_sclk_en = 15 -TD_PERF_SEL_nofilter_sclk_en = 16 -TD_PERF_SEL_nofilter_d32_sclk_en = 17 -TD_PERF_SEL_nofilter_d16_sclk_en = 18 -TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22 -TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23 -TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24 -TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25 -TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 -TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 -TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 -TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29 -TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30 -TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31 -TD_PERF_SEL_core_state_ram_max_cnt = 32 -TD_PERF_SEL_core_state_rams_read = 33 -TD_PERF_SEL_weight_data_rams_read = 34 -TD_PERF_SEL_reference_data_rams_read = 35 -TD_PERF_SEL_tc_td_ram_fifo_full = 36 -TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 -TD_PERF_SEL_tc_td_data_fifo_full = 38 -TD_PERF_SEL_input_state_fifo_full = 39 -TD_PERF_SEL_ta_data_stall = 40 -TD_PERF_SEL_tc_data_stall = 41 -TD_PERF_SEL_tc_ram_stall = 42 -TD_PERF_SEL_lds_stall = 43 -TD_PERF_SEL_sampler_pkr_full = 44 -TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 -TD_PERF_SEL_nofilter_pkr_full = 46 -TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 -TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48 -TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49 -TD_PERF_SEL_gather4_instr = 50 -TD_PERF_SEL_gather4h_instr = 51 -TD_PERF_SEL_sample_instr = 54 -TD_PERF_SEL_sample_c_instr = 55 -TD_PERF_SEL_load_instr = 56 -TD_PERF_SEL_ldfptr_instr = 57 -TD_PERF_SEL_write_ack_instr = 58 -TD_PERF_SEL_d16_en_instr = 59 -TD_PERF_SEL_bypassLerp_instr = 60 -TD_PERF_SEL_min_max_filter_instr = 61 -TD_PERF_SEL_one_comp_return_instr = 62 -TD_PERF_SEL_two_comp_return_instr = 63 -TD_PERF_SEL_three_comp_return_instr = 64 -TD_PERF_SEL_four_comp_return_instr = 65 -TD_PERF_SEL_user_defined_border = 66 -TD_PERF_SEL_white_border = 67 -TD_PERF_SEL_opaque_black_border = 68 -TD_PERF_SEL_lod_warn_from_ta = 69 -TD_PERF_SEL_instruction_dest_is_lds = 70 -TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 -TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 -TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 -TD_PERF_SEL_out_of_order_instr = 75 -TD_PERF_SEL_total_num_instr = 76 -TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 -TD_PERF_SEL_total_num_sampler_instr = 78 -TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 -TD_PERF_SEL_total_num_nofilter_instr = 80 -TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82 -TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83 -TD_PERF_SEL_mixmode_instr = 84 -TD_PERF_SEL_mixmode_resource = 85 -TD_PERF_SEL_status_packet = 86 -TD_PERF_SEL_address_cmd_poison = 87 -TD_PERF_SEL_data_poison = 88 -TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 -TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 -TD_PERF_SEL_done_scoreboard_not_empty = 91 -TD_PERF_SEL_done_scoreboard_is_full = 92 -TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 -TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 -TD_PERF_SEL_nofilter_formatters_turned_on = 95 -TD_PERF_SEL_nofilter_insert_extra_comps = 96 -TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 -TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 -TD_PERF_SEL_msaa_load_instr = 99 -TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 -TD_PERF_SEL_blend_prt_with_prt_default_1 = 101 -TD_PERF_SEL_resmap_instr = 102 -TD_PERF_SEL_prt_ack_instr = 103 -TD_PERF_SEL_resmap_with_volume_filtering = 104 -TD_PERF_SEL_resmap_with_aniso_filtering = 105 -TD_PERF_SEL_resmap_with_no_more_filtering = 106 -TD_PERF_SEL_resmap_with_cubemap_corner = 107 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114 -TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115 -TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116 -TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117 -TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118 -TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119 -TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120 -TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121 -TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122 -TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123 -TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124 -TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126 -TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127 -TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129 -TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130 -TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 -TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 -TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 -TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 -TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 -TD_PERF_SEL_burst_bin_sampler_1 = 136 -TD_PERF_SEL_burst_bin_sampler_2to8 = 137 -TD_PERF_SEL_burst_bin_sampler_9to16 = 138 -TD_PERF_SEL_burst_bin_sampler_gt16 = 139 -TD_PERF_SEL_burst_bin_gather_1 = 140 -TD_PERF_SEL_burst_bin_gather_2to8 = 141 -TD_PERF_SEL_burst_bin_gather_9to16 = 142 -TD_PERF_SEL_burst_bin_gather_gt16 = 143 -TD_PERF_SEL_burst_bin_nofilter_1 = 144 -TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 -TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 -TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 -TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 -TD_PERF_SEL_burst_bin_bvh4_1 = 149 -TD_PERF_SEL_burst_bin_bvh4_2to8 = 150 -TD_PERF_SEL_burst_bin_bvh4_9to16 = 151 -TD_PERF_SEL_burst_bin_bvh4_gt16 = 152 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156 -TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160 -TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164 -TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168 -TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 -TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 -TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 -TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 -TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 -TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 -TD_PERF_SEL_preempting_nofilter_max_cnt = 180 -TD_PERF_SEL_sampler_lerp0_active = 181 -TD_PERF_SEL_sampler_lerp1_active = 182 -TD_PERF_SEL_sampler_lerp2_active = 183 -TD_PERF_SEL_sampler_lerp3_active = 184 -TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185 -TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186 -TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187 -TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188 -TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189 -TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190 -TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191 -TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192 -TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2A_PERF_SEL' -GL2A_PERF_SEL__enumvalues = { - 0: 'GL2A_PERF_SEL_NONE', - 1: 'GL2A_PERF_SEL_CYCLE', - 2: 'GL2A_PERF_SEL_BUSY', - 3: 'GL2A_PERF_SEL_REQ_GL2C0', - 4: 'GL2A_PERF_SEL_REQ_GL2C1', - 5: 'GL2A_PERF_SEL_REQ_GL2C2', - 6: 'GL2A_PERF_SEL_REQ_GL2C3', - 7: 'GL2A_PERF_SEL_REQ_GL2C4', - 8: 'GL2A_PERF_SEL_REQ_GL2C5', - 9: 'GL2A_PERF_SEL_REQ_GL2C6', - 10: 'GL2A_PERF_SEL_REQ_GL2C7', - 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', - 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', - 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', - 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', - 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', - 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', - 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', - 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', - 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', - 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', - 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', - 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', - 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 43: 'GL2A_PERF_SEL_RTN_CLIENT0', - 44: 'GL2A_PERF_SEL_RTN_CLIENT1', - 45: 'GL2A_PERF_SEL_RTN_CLIENT2', - 46: 'GL2A_PERF_SEL_RTN_CLIENT3', - 47: 'GL2A_PERF_SEL_RTN_CLIENT4', - 48: 'GL2A_PERF_SEL_RTN_CLIENT5', - 49: 'GL2A_PERF_SEL_RTN_CLIENT6', - 50: 'GL2A_PERF_SEL_RTN_CLIENT7', - 51: 'GL2A_PERF_SEL_RTN_CLIENT8', - 52: 'GL2A_PERF_SEL_RTN_CLIENT9', - 53: 'GL2A_PERF_SEL_RTN_CLIENT10', - 54: 'GL2A_PERF_SEL_RTN_CLIENT11', - 55: 'GL2A_PERF_SEL_RTN_CLIENT12', - 56: 'GL2A_PERF_SEL_RTN_CLIENT13', - 57: 'GL2A_PERF_SEL_RTN_CLIENT14', - 58: 'GL2A_PERF_SEL_RTN_CLIENT15', - 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', -} -GL2A_PERF_SEL_NONE = 0 -GL2A_PERF_SEL_CYCLE = 1 -GL2A_PERF_SEL_BUSY = 2 -GL2A_PERF_SEL_REQ_GL2C0 = 3 -GL2A_PERF_SEL_REQ_GL2C1 = 4 -GL2A_PERF_SEL_REQ_GL2C2 = 5 -GL2A_PERF_SEL_REQ_GL2C3 = 6 -GL2A_PERF_SEL_REQ_GL2C4 = 7 -GL2A_PERF_SEL_REQ_GL2C5 = 8 -GL2A_PERF_SEL_REQ_GL2C6 = 9 -GL2A_PERF_SEL_REQ_GL2C7 = 10 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 -GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 -GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 -GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 -GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 -GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 -GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 -GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 -GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 -GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 -GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 -GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 -GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 -GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 -GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 -GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 -GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 -GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 -GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 -GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 -GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 -GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 -GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 -GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 -GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 -GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 -GL2A_PERF_SEL_RTN_CLIENT0 = 43 -GL2A_PERF_SEL_RTN_CLIENT1 = 44 -GL2A_PERF_SEL_RTN_CLIENT2 = 45 -GL2A_PERF_SEL_RTN_CLIENT3 = 46 -GL2A_PERF_SEL_RTN_CLIENT4 = 47 -GL2A_PERF_SEL_RTN_CLIENT5 = 48 -GL2A_PERF_SEL_RTN_CLIENT6 = 49 -GL2A_PERF_SEL_RTN_CLIENT7 = 50 -GL2A_PERF_SEL_RTN_CLIENT8 = 51 -GL2A_PERF_SEL_RTN_CLIENT9 = 52 -GL2A_PERF_SEL_RTN_CLIENT10 = 53 -GL2A_PERF_SEL_RTN_CLIENT11 = 54 -GL2A_PERF_SEL_RTN_CLIENT12 = 55 -GL2A_PERF_SEL_RTN_CLIENT13 = 56 -GL2A_PERF_SEL_RTN_CLIENT14 = 57 -GL2A_PERF_SEL_RTN_CLIENT15 = 58 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 -GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 -GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 -GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 -GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 -GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 -GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 -GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 -GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 -GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 -GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 -GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 -GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 -GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 -GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 -GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 -GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 -GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 -GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 -GL2A_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GL2C_PERF_SEL' -GL2C_PERF_SEL__enumvalues = { - 0: 'GL2C_PERF_SEL_NONE', - 1: 'GL2C_PERF_SEL_CYCLE', - 2: 'GL2C_PERF_SEL_BUSY', - 3: 'GL2C_PERF_SEL_REQ', - 4: 'GL2C_PERF_SEL_VOL_REQ', - 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', - 6: 'GL2C_PERF_SEL_READ', - 7: 'GL2C_PERF_SEL_WRITE', - 8: 'GL2C_PERF_SEL_ATOMIC', - 9: 'GL2C_PERF_SEL_NOP_ACK', - 10: 'GL2C_PERF_SEL_NOP_RTN0', - 11: 'GL2C_PERF_SEL_PROBE', - 12: 'GL2C_PERF_SEL_PROBE_ALL', - 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', - 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', - 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', - 16: 'GL2C_PERF_SEL_CLIENT0_REQ', - 17: 'GL2C_PERF_SEL_CLIENT1_REQ', - 18: 'GL2C_PERF_SEL_CLIENT2_REQ', - 19: 'GL2C_PERF_SEL_CLIENT3_REQ', - 20: 'GL2C_PERF_SEL_CLIENT4_REQ', - 21: 'GL2C_PERF_SEL_CLIENT5_REQ', - 22: 'GL2C_PERF_SEL_CLIENT6_REQ', - 23: 'GL2C_PERF_SEL_CLIENT7_REQ', - 24: 'GL2C_PERF_SEL_CLIENT8_REQ', - 25: 'GL2C_PERF_SEL_CLIENT9_REQ', - 26: 'GL2C_PERF_SEL_CLIENT10_REQ', - 27: 'GL2C_PERF_SEL_CLIENT11_REQ', - 28: 'GL2C_PERF_SEL_CLIENT12_REQ', - 29: 'GL2C_PERF_SEL_CLIENT13_REQ', - 30: 'GL2C_PERF_SEL_CLIENT14_REQ', - 31: 'GL2C_PERF_SEL_CLIENT15_REQ', - 32: 'GL2C_PERF_SEL_C_RW_S_REQ', - 33: 'GL2C_PERF_SEL_C_RW_US_REQ', - 34: 'GL2C_PERF_SEL_C_RO_S_REQ', - 35: 'GL2C_PERF_SEL_C_RO_US_REQ', - 36: 'GL2C_PERF_SEL_UC_REQ', - 37: 'GL2C_PERF_SEL_LRU_REQ', - 38: 'GL2C_PERF_SEL_STREAM_REQ', - 39: 'GL2C_PERF_SEL_BYPASS_REQ', - 40: 'GL2C_PERF_SEL_NOA_REQ', - 41: 'GL2C_PERF_SEL_SHARED_REQ', - 42: 'GL2C_PERF_SEL_HIT', - 43: 'GL2C_PERF_SEL_MISS', - 44: 'GL2C_PERF_SEL_FULL_HIT', - 45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', - 46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', - 48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', - 49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', - 50: 'GL2C_PERF_SEL_UNCACHED_WRITE', - 51: 'GL2C_PERF_SEL_WRITEBACK', - 52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 53: 'GL2C_PERF_SEL_EVICT', - 54: 'GL2C_PERF_SEL_NORMAL_EVICT', - 55: 'GL2C_PERF_SEL_PROBE_EVICT', - 56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', - 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', - 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 73: 'GL2C_PERF_SEL_READ_32_REQ', - 74: 'GL2C_PERF_SEL_READ_64_REQ', - 75: 'GL2C_PERF_SEL_READ_128_REQ', - 76: 'GL2C_PERF_SEL_WRITE_32_REQ', - 77: 'GL2C_PERF_SEL_WRITE_64_REQ', - 78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 83: 'GL2C_PERF_SEL_MC_WRREQ', - 84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', - 85: 'GL2C_PERF_SEL_EA_WRREQ_64B', - 86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', - 88: 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', - 93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', - 94: 'GL2C_PERF_SEL_EA_ATOMIC', - 95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', - 96: 'GL2C_PERF_SEL_MC_RDREQ', - 97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', - 98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 99: 'GL2C_PERF_SEL_EA_RDREQ_32B', - 100: 'GL2C_PERF_SEL_EA_RDREQ_64B', - 101: 'GL2C_PERF_SEL_EA_RDREQ_96B', - 102: 'GL2C_PERF_SEL_EA_RDREQ_128B', - 103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 104: 'GL2C_PERF_SEL_EA_RD_MDC_32B', - 105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', - 110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', - 111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 114: 'GL2C_PERF_SEL_ONION_READ', - 115: 'GL2C_PERF_SEL_ONION_WRITE', - 116: 'GL2C_PERF_SEL_IO_READ', - 117: 'GL2C_PERF_SEL_IO_WRITE', - 118: 'GL2C_PERF_SEL_GARLIC_READ', - 119: 'GL2C_PERF_SEL_GARLIC_WRITE', - 120: 'GL2C_PERF_SEL_EA_OUTSTANDING', - 121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 122: 'GL2C_PERF_SEL_SRC_FIFO_FULL', - 123: 'GL2C_PERF_SEL_TAG_STALL', - 124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 128: 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', - 132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', - 133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 135: 'GL2C_PERF_SEL_BUBBLE', - 136: 'GL2C_PERF_SEL_IB_REQ', - 137: 'GL2C_PERF_SEL_IB_STALL', - 138: 'GL2C_PERF_SEL_IB_TAG_STALL', - 139: 'GL2C_PERF_SEL_IB_CM_STALL', - 140: 'GL2C_PERF_SEL_RETURN_ACK', - 141: 'GL2C_PERF_SEL_RETURN_DATA', - 142: 'GL2C_PERF_SEL_EA_RDRET_NACK', - 143: 'GL2C_PERF_SEL_EA_WRRET_NACK', - 144: 'GL2C_PERF_SEL_GL2A_LEVEL', - 145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 149: 'GL2C_PERF_SEL_GCR_INV', - 150: 'GL2C_PERF_SEL_GCR_WB', - 151: 'GL2C_PERF_SEL_GCR_DISCARD', - 152: 'GL2C_PERF_SEL_GCR_RANGE', - 153: 'GL2C_PERF_SEL_GCR_ALL', - 154: 'GL2C_PERF_SEL_GCR_VOL', - 155: 'GL2C_PERF_SEL_GCR_UNSHARED', - 156: 'GL2C_PERF_SEL_GCR_MDC_INV', - 157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', - 161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', - 162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', - 164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', - 172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', - 174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 176: 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 177: 'GL2C_PERF_SEL_MDC_INV_METADATA', - 178: 'GL2C_PERF_SEL_MDC_REQ', - 179: 'GL2C_PERF_SEL_MDC_LEVEL', - 180: 'GL2C_PERF_SEL_MDC_TAG_HIT', - 181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 183: 'GL2C_PERF_SEL_MDC_TAG_STALL', - 184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', - 188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', - 192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', - 194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', - 196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', - 207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', - 217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', - 219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', - 223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', - 230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', - 232: 'GL2C_PERF_SEL_CM_NOOP_REQ', - 233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', - 239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 242: 'GL2C_PERF_SEL_CM_RVF_FULL', - 243: 'GL2C_PERF_SEL_CM_SDR_FULL', - 244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 245: 'GL2C_PERF_SEL_CM_DCC_STALL', - 246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC', - 247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', - 248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', - 249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', - 250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', - 251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', - 252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', - 253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', - 254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', -} -GL2C_PERF_SEL_NONE = 0 -GL2C_PERF_SEL_CYCLE = 1 -GL2C_PERF_SEL_BUSY = 2 -GL2C_PERF_SEL_REQ = 3 -GL2C_PERF_SEL_VOL_REQ = 4 -GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 -GL2C_PERF_SEL_READ = 6 -GL2C_PERF_SEL_WRITE = 7 -GL2C_PERF_SEL_ATOMIC = 8 -GL2C_PERF_SEL_NOP_ACK = 9 -GL2C_PERF_SEL_NOP_RTN0 = 10 -GL2C_PERF_SEL_PROBE = 11 -GL2C_PERF_SEL_PROBE_ALL = 12 -GL2C_PERF_SEL_INTERNAL_PROBE = 13 -GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 -GL2C_PERF_SEL_METADATA_READ_REQ = 15 -GL2C_PERF_SEL_CLIENT0_REQ = 16 -GL2C_PERF_SEL_CLIENT1_REQ = 17 -GL2C_PERF_SEL_CLIENT2_REQ = 18 -GL2C_PERF_SEL_CLIENT3_REQ = 19 -GL2C_PERF_SEL_CLIENT4_REQ = 20 -GL2C_PERF_SEL_CLIENT5_REQ = 21 -GL2C_PERF_SEL_CLIENT6_REQ = 22 -GL2C_PERF_SEL_CLIENT7_REQ = 23 -GL2C_PERF_SEL_CLIENT8_REQ = 24 -GL2C_PERF_SEL_CLIENT9_REQ = 25 -GL2C_PERF_SEL_CLIENT10_REQ = 26 -GL2C_PERF_SEL_CLIENT11_REQ = 27 -GL2C_PERF_SEL_CLIENT12_REQ = 28 -GL2C_PERF_SEL_CLIENT13_REQ = 29 -GL2C_PERF_SEL_CLIENT14_REQ = 30 -GL2C_PERF_SEL_CLIENT15_REQ = 31 -GL2C_PERF_SEL_C_RW_S_REQ = 32 -GL2C_PERF_SEL_C_RW_US_REQ = 33 -GL2C_PERF_SEL_C_RO_S_REQ = 34 -GL2C_PERF_SEL_C_RO_US_REQ = 35 -GL2C_PERF_SEL_UC_REQ = 36 -GL2C_PERF_SEL_LRU_REQ = 37 -GL2C_PERF_SEL_STREAM_REQ = 38 -GL2C_PERF_SEL_BYPASS_REQ = 39 -GL2C_PERF_SEL_NOA_REQ = 40 -GL2C_PERF_SEL_SHARED_REQ = 41 -GL2C_PERF_SEL_HIT = 42 -GL2C_PERF_SEL_MISS = 43 -GL2C_PERF_SEL_FULL_HIT = 44 -GL2C_PERF_SEL_PARTIAL_32B_HIT = 45 -GL2C_PERF_SEL_PARTIAL_64B_HIT = 46 -GL2C_PERF_SEL_PARTIAL_96B_HIT = 47 -GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48 -GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49 -GL2C_PERF_SEL_UNCACHED_WRITE = 50 -GL2C_PERF_SEL_WRITEBACK = 51 -GL2C_PERF_SEL_NORMAL_WRITEBACK = 52 -GL2C_PERF_SEL_EVICT = 53 -GL2C_PERF_SEL_NORMAL_EVICT = 54 -GL2C_PERF_SEL_PROBE_EVICT = 55 -GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72 -GL2C_PERF_SEL_READ_32_REQ = 73 -GL2C_PERF_SEL_READ_64_REQ = 74 -GL2C_PERF_SEL_READ_128_REQ = 75 -GL2C_PERF_SEL_WRITE_32_REQ = 76 -GL2C_PERF_SEL_WRITE_64_REQ = 77 -GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78 -GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79 -GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80 -GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81 -GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82 -GL2C_PERF_SEL_MC_WRREQ = 83 -GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84 -GL2C_PERF_SEL_EA_WRREQ_64B = 85 -GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86 -GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87 -GL2C_PERF_SEL_MC_WRREQ_STALL = 88 -GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89 -GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90 -GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91 -GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92 -GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93 -GL2C_PERF_SEL_EA_ATOMIC = 94 -GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95 -GL2C_PERF_SEL_MC_RDREQ = 96 -GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97 -GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98 -GL2C_PERF_SEL_EA_RDREQ_32B = 99 -GL2C_PERF_SEL_EA_RDREQ_64B = 100 -GL2C_PERF_SEL_EA_RDREQ_96B = 101 -GL2C_PERF_SEL_EA_RDREQ_128B = 102 -GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103 -GL2C_PERF_SEL_EA_RD_MDC_32B = 104 -GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105 -GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106 -GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107 -GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108 -GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109 -GL2C_PERF_SEL_EA_RDREQ_DRAM = 110 -GL2C_PERF_SEL_EA_WRREQ_DRAM = 111 -GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112 -GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113 -GL2C_PERF_SEL_ONION_READ = 114 -GL2C_PERF_SEL_ONION_WRITE = 115 -GL2C_PERF_SEL_IO_READ = 116 -GL2C_PERF_SEL_IO_WRITE = 117 -GL2C_PERF_SEL_GARLIC_READ = 118 -GL2C_PERF_SEL_GARLIC_WRITE = 119 -GL2C_PERF_SEL_EA_OUTSTANDING = 120 -GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121 -GL2C_PERF_SEL_SRC_FIFO_FULL = 122 -GL2C_PERF_SEL_TAG_STALL = 123 -GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124 -GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125 -GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126 -GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127 -GL2C_PERF_SEL_TAG_PROBE_STALL = 128 -GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129 -GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130 -GL2C_PERF_SEL_TAG_READ_DST_STALL = 131 -GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132 -GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133 -GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134 -GL2C_PERF_SEL_BUBBLE = 135 -GL2C_PERF_SEL_IB_REQ = 136 -GL2C_PERF_SEL_IB_STALL = 137 -GL2C_PERF_SEL_IB_TAG_STALL = 138 -GL2C_PERF_SEL_IB_CM_STALL = 139 -GL2C_PERF_SEL_RETURN_ACK = 140 -GL2C_PERF_SEL_RETURN_DATA = 141 -GL2C_PERF_SEL_EA_RDRET_NACK = 142 -GL2C_PERF_SEL_EA_WRRET_NACK = 143 -GL2C_PERF_SEL_GL2A_LEVEL = 144 -GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145 -GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147 -GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148 -GL2C_PERF_SEL_GCR_INV = 149 -GL2C_PERF_SEL_GCR_WB = 150 -GL2C_PERF_SEL_GCR_DISCARD = 151 -GL2C_PERF_SEL_GCR_RANGE = 152 -GL2C_PERF_SEL_GCR_ALL = 153 -GL2C_PERF_SEL_GCR_VOL = 154 -GL2C_PERF_SEL_GCR_UNSHARED = 155 -GL2C_PERF_SEL_GCR_MDC_INV = 156 -GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157 -GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158 -GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159 -GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160 -GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161 -GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162 -GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163 -GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164 -GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166 -GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167 -GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168 -GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169 -GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170 -GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171 -GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172 -GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173 -GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174 -GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175 -GL2C_PERF_SEL_GCR_WBINVL2_START = 176 -GL2C_PERF_SEL_MDC_INV_METADATA = 177 -GL2C_PERF_SEL_MDC_REQ = 178 -GL2C_PERF_SEL_MDC_LEVEL = 179 -GL2C_PERF_SEL_MDC_TAG_HIT = 180 -GL2C_PERF_SEL_MDC_SECTOR_HIT = 181 -GL2C_PERF_SEL_MDC_SECTOR_MISS = 182 -GL2C_PERF_SEL_MDC_TAG_STALL = 183 -GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184 -GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185 -GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186 -GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187 -GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188 -GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189 -GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190 -GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191 -GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192 -GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193 -GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194 -GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195 -GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196 -GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197 -GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198 -GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199 -GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200 -GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201 -GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202 -GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203 -GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204 -GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205 -GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206 -GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207 -GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208 -GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209 -GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210 -GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211 -GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212 -GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213 -GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214 -GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215 -GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216 -GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217 -GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218 -GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220 -GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221 -GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222 -GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224 -GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225 -GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226 -GL2C_PERF_SEL_CM_COMP_READ_REQ = 227 -GL2C_PERF_SEL_CM_READ_BACK_REQ = 228 -GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229 -GL2C_PERF_SEL_CM_WR_ACK_REQ = 230 -GL2C_PERF_SEL_CM_NO_ACK_REQ = 231 -GL2C_PERF_SEL_CM_NOOP_REQ = 232 -GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233 -GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234 -GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235 -GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236 -GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237 -GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238 -GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239 -GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240 -GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241 -GL2C_PERF_SEL_CM_RVF_FULL = 242 -GL2C_PERF_SEL_CM_SDR_FULL = 243 -GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244 -GL2C_PERF_SEL_CM_DCC_STALL = 245 -GL2C_PERF_SEL_CM_DCC_IN_XFC = 246 -GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247 -GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248 -GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249 -GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250 -GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251 -GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252 -GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256 -GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257 -GL2C_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_PERF_SEL' -GRBM_PERF_SEL__enumvalues = { - 0: 'GRBM_PERF_SEL_COUNT', - 1: 'GRBM_PERF_SEL_USER_DEFINED', - 2: 'GRBM_PERF_SEL_GUI_ACTIVE', - 3: 'GRBM_PERF_SEL_CP_BUSY', - 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', - 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', - 6: 'GRBM_PERF_SEL_CB_BUSY', - 7: 'GRBM_PERF_SEL_DB_BUSY', - 8: 'GRBM_PERF_SEL_PA_BUSY', - 9: 'GRBM_PERF_SEL_SC_BUSY', - 11: 'GRBM_PERF_SEL_SPI_BUSY', - 12: 'GRBM_PERF_SEL_SX_BUSY', - 13: 'GRBM_PERF_SEL_TA_BUSY', - 14: 'GRBM_PERF_SEL_CB_CLEAN', - 15: 'GRBM_PERF_SEL_DB_CLEAN', - 25: 'GRBM_PERF_SEL_GDS_BUSY', - 26: 'GRBM_PERF_SEL_BCI_BUSY', - 27: 'GRBM_PERF_SEL_RLC_BUSY', - 28: 'GRBM_PERF_SEL_TCP_BUSY', - 29: 'GRBM_PERF_SEL_CPG_BUSY', - 30: 'GRBM_PERF_SEL_CPC_BUSY', - 31: 'GRBM_PERF_SEL_CPF_BUSY', - 32: 'GRBM_PERF_SEL_GE_BUSY', - 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 34: 'GRBM_PERF_SEL_UTCL2_BUSY', - 35: 'GRBM_PERF_SEL_EA_BUSY', - 36: 'GRBM_PERF_SEL_RMI_BUSY', - 37: 'GRBM_PERF_SEL_CPAXI_BUSY', - 39: 'GRBM_PERF_SEL_UTCL1_BUSY', - 40: 'GRBM_PERF_SEL_GL2CC_BUSY', - 41: 'GRBM_PERF_SEL_SDMA_BUSY', - 42: 'GRBM_PERF_SEL_CH_BUSY', - 43: 'GRBM_PERF_SEL_PH_BUSY', - 44: 'GRBM_PERF_SEL_PMM_BUSY', - 45: 'GRBM_PERF_SEL_GUS_BUSY', - 46: 'GRBM_PERF_SEL_GL1CC_BUSY', - 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 48: 'GRBM_PERF_SEL_GL1H_BUSY', - 49: 'GRBM_PERF_SEL_PC_BUSY', -} -GRBM_PERF_SEL_COUNT = 0 -GRBM_PERF_SEL_USER_DEFINED = 1 -GRBM_PERF_SEL_GUI_ACTIVE = 2 -GRBM_PERF_SEL_CP_BUSY = 3 -GRBM_PERF_SEL_CP_COHER_BUSY = 4 -GRBM_PERF_SEL_CP_DMA_BUSY = 5 -GRBM_PERF_SEL_CB_BUSY = 6 -GRBM_PERF_SEL_DB_BUSY = 7 -GRBM_PERF_SEL_PA_BUSY = 8 -GRBM_PERF_SEL_SC_BUSY = 9 -GRBM_PERF_SEL_SPI_BUSY = 11 -GRBM_PERF_SEL_SX_BUSY = 12 -GRBM_PERF_SEL_TA_BUSY = 13 -GRBM_PERF_SEL_CB_CLEAN = 14 -GRBM_PERF_SEL_DB_CLEAN = 15 -GRBM_PERF_SEL_GDS_BUSY = 25 -GRBM_PERF_SEL_BCI_BUSY = 26 -GRBM_PERF_SEL_RLC_BUSY = 27 -GRBM_PERF_SEL_TCP_BUSY = 28 -GRBM_PERF_SEL_CPG_BUSY = 29 -GRBM_PERF_SEL_CPC_BUSY = 30 -GRBM_PERF_SEL_CPF_BUSY = 31 -GRBM_PERF_SEL_GE_BUSY = 32 -GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 -GRBM_PERF_SEL_UTCL2_BUSY = 34 -GRBM_PERF_SEL_EA_BUSY = 35 -GRBM_PERF_SEL_RMI_BUSY = 36 -GRBM_PERF_SEL_CPAXI_BUSY = 37 -GRBM_PERF_SEL_UTCL1_BUSY = 39 -GRBM_PERF_SEL_GL2CC_BUSY = 40 -GRBM_PERF_SEL_SDMA_BUSY = 41 -GRBM_PERF_SEL_CH_BUSY = 42 -GRBM_PERF_SEL_PH_BUSY = 43 -GRBM_PERF_SEL_PMM_BUSY = 44 -GRBM_PERF_SEL_GUS_BUSY = 45 -GRBM_PERF_SEL_GL1CC_BUSY = 46 -GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 -GRBM_PERF_SEL_GL1H_BUSY = 48 -GRBM_PERF_SEL_PC_BUSY = 49 -GRBM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE0_PERF_SEL' -GRBM_SE0_PERF_SEL__enumvalues = { - 0: 'GRBM_SE0_PERF_SEL_COUNT', - 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE0_PERF_SEL_PC_BUSY', -} -GRBM_SE0_PERF_SEL_COUNT = 0 -GRBM_SE0_PERF_SEL_USER_DEFINED = 1 -GRBM_SE0_PERF_SEL_CB_BUSY = 2 -GRBM_SE0_PERF_SEL_DB_BUSY = 3 -GRBM_SE0_PERF_SEL_SC_BUSY = 4 -GRBM_SE0_PERF_SEL_SPI_BUSY = 6 -GRBM_SE0_PERF_SEL_SX_BUSY = 7 -GRBM_SE0_PERF_SEL_TA_BUSY = 8 -GRBM_SE0_PERF_SEL_CB_CLEAN = 9 -GRBM_SE0_PERF_SEL_DB_CLEAN = 10 -GRBM_SE0_PERF_SEL_PA_BUSY = 12 -GRBM_SE0_PERF_SEL_BCI_BUSY = 14 -GRBM_SE0_PERF_SEL_RMI_BUSY = 15 -GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE0_PERF_SEL_TCP_BUSY = 17 -GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE0_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE0_PERF_SEL_PC_BUSY = 20 -GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE1_PERF_SEL' -GRBM_SE1_PERF_SEL__enumvalues = { - 0: 'GRBM_SE1_PERF_SEL_COUNT', - 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE1_PERF_SEL_PC_BUSY', -} -GRBM_SE1_PERF_SEL_COUNT = 0 -GRBM_SE1_PERF_SEL_USER_DEFINED = 1 -GRBM_SE1_PERF_SEL_CB_BUSY = 2 -GRBM_SE1_PERF_SEL_DB_BUSY = 3 -GRBM_SE1_PERF_SEL_SC_BUSY = 4 -GRBM_SE1_PERF_SEL_SPI_BUSY = 6 -GRBM_SE1_PERF_SEL_SX_BUSY = 7 -GRBM_SE1_PERF_SEL_TA_BUSY = 8 -GRBM_SE1_PERF_SEL_CB_CLEAN = 9 -GRBM_SE1_PERF_SEL_DB_CLEAN = 10 -GRBM_SE1_PERF_SEL_PA_BUSY = 12 -GRBM_SE1_PERF_SEL_BCI_BUSY = 14 -GRBM_SE1_PERF_SEL_RMI_BUSY = 15 -GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE1_PERF_SEL_TCP_BUSY = 17 -GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE1_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE1_PERF_SEL_PC_BUSY = 20 -GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE2_PERF_SEL' -GRBM_SE2_PERF_SEL__enumvalues = { - 0: 'GRBM_SE2_PERF_SEL_COUNT', - 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE2_PERF_SEL_PC_BUSY', -} -GRBM_SE2_PERF_SEL_COUNT = 0 -GRBM_SE2_PERF_SEL_USER_DEFINED = 1 -GRBM_SE2_PERF_SEL_CB_BUSY = 2 -GRBM_SE2_PERF_SEL_DB_BUSY = 3 -GRBM_SE2_PERF_SEL_SC_BUSY = 4 -GRBM_SE2_PERF_SEL_SPI_BUSY = 6 -GRBM_SE2_PERF_SEL_SX_BUSY = 7 -GRBM_SE2_PERF_SEL_TA_BUSY = 8 -GRBM_SE2_PERF_SEL_CB_CLEAN = 9 -GRBM_SE2_PERF_SEL_DB_CLEAN = 10 -GRBM_SE2_PERF_SEL_PA_BUSY = 12 -GRBM_SE2_PERF_SEL_BCI_BUSY = 14 -GRBM_SE2_PERF_SEL_RMI_BUSY = 15 -GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE2_PERF_SEL_TCP_BUSY = 17 -GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE2_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE2_PERF_SEL_PC_BUSY = 20 -GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE3_PERF_SEL' -GRBM_SE3_PERF_SEL__enumvalues = { - 0: 'GRBM_SE3_PERF_SEL_COUNT', - 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE3_PERF_SEL_PC_BUSY', -} -GRBM_SE3_PERF_SEL_COUNT = 0 -GRBM_SE3_PERF_SEL_USER_DEFINED = 1 -GRBM_SE3_PERF_SEL_CB_BUSY = 2 -GRBM_SE3_PERF_SEL_DB_BUSY = 3 -GRBM_SE3_PERF_SEL_SC_BUSY = 4 -GRBM_SE3_PERF_SEL_SPI_BUSY = 6 -GRBM_SE3_PERF_SEL_SX_BUSY = 7 -GRBM_SE3_PERF_SEL_TA_BUSY = 8 -GRBM_SE3_PERF_SEL_CB_CLEAN = 9 -GRBM_SE3_PERF_SEL_DB_CLEAN = 10 -GRBM_SE3_PERF_SEL_PA_BUSY = 12 -GRBM_SE3_PERF_SEL_BCI_BUSY = 14 -GRBM_SE3_PERF_SEL_RMI_BUSY = 15 -GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE3_PERF_SEL_TCP_BUSY = 17 -GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE3_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE3_PERF_SEL_PC_BUSY = 20 -GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE4_PERF_SEL' -GRBM_SE4_PERF_SEL__enumvalues = { - 0: 'GRBM_SE4_PERF_SEL_COUNT', - 1: 'GRBM_SE4_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE4_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE4_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE4_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE4_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE4_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE4_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE4_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE4_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE4_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE4_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE4_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE4_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE4_PERF_SEL_PC_BUSY', -} -GRBM_SE4_PERF_SEL_COUNT = 0 -GRBM_SE4_PERF_SEL_USER_DEFINED = 1 -GRBM_SE4_PERF_SEL_CB_BUSY = 2 -GRBM_SE4_PERF_SEL_DB_BUSY = 3 -GRBM_SE4_PERF_SEL_SC_BUSY = 4 -GRBM_SE4_PERF_SEL_SPI_BUSY = 6 -GRBM_SE4_PERF_SEL_SX_BUSY = 7 -GRBM_SE4_PERF_SEL_TA_BUSY = 8 -GRBM_SE4_PERF_SEL_CB_CLEAN = 9 -GRBM_SE4_PERF_SEL_DB_CLEAN = 10 -GRBM_SE4_PERF_SEL_PA_BUSY = 12 -GRBM_SE4_PERF_SEL_BCI_BUSY = 14 -GRBM_SE4_PERF_SEL_RMI_BUSY = 15 -GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE4_PERF_SEL_TCP_BUSY = 17 -GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE4_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE4_PERF_SEL_PC_BUSY = 20 -GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE5_PERF_SEL' -GRBM_SE5_PERF_SEL__enumvalues = { - 0: 'GRBM_SE5_PERF_SEL_COUNT', - 1: 'GRBM_SE5_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE5_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE5_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE5_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE5_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE5_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE5_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE5_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE5_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE5_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE5_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE5_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE5_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE5_PERF_SEL_PC_BUSY', -} -GRBM_SE5_PERF_SEL_COUNT = 0 -GRBM_SE5_PERF_SEL_USER_DEFINED = 1 -GRBM_SE5_PERF_SEL_CB_BUSY = 2 -GRBM_SE5_PERF_SEL_DB_BUSY = 3 -GRBM_SE5_PERF_SEL_SC_BUSY = 4 -GRBM_SE5_PERF_SEL_SPI_BUSY = 6 -GRBM_SE5_PERF_SEL_SX_BUSY = 7 -GRBM_SE5_PERF_SEL_TA_BUSY = 8 -GRBM_SE5_PERF_SEL_CB_CLEAN = 9 -GRBM_SE5_PERF_SEL_DB_CLEAN = 10 -GRBM_SE5_PERF_SEL_PA_BUSY = 12 -GRBM_SE5_PERF_SEL_BCI_BUSY = 14 -GRBM_SE5_PERF_SEL_RMI_BUSY = 15 -GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE5_PERF_SEL_TCP_BUSY = 17 -GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE5_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE5_PERF_SEL_PC_BUSY = 20 -GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE6_PERF_SEL' -GRBM_SE6_PERF_SEL__enumvalues = { - 0: 'GRBM_SE6_PERF_SEL_COUNT', - 1: 'GRBM_SE6_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE6_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE6_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE6_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE6_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE6_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE6_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE6_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE6_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE6_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE6_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE6_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE6_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE6_PERF_SEL_PC_BUSY', -} -GRBM_SE6_PERF_SEL_COUNT = 0 -GRBM_SE6_PERF_SEL_USER_DEFINED = 1 -GRBM_SE6_PERF_SEL_CB_BUSY = 2 -GRBM_SE6_PERF_SEL_DB_BUSY = 3 -GRBM_SE6_PERF_SEL_SC_BUSY = 4 -GRBM_SE6_PERF_SEL_SPI_BUSY = 6 -GRBM_SE6_PERF_SEL_SX_BUSY = 7 -GRBM_SE6_PERF_SEL_TA_BUSY = 8 -GRBM_SE6_PERF_SEL_CB_CLEAN = 9 -GRBM_SE6_PERF_SEL_DB_CLEAN = 10 -GRBM_SE6_PERF_SEL_PA_BUSY = 12 -GRBM_SE6_PERF_SEL_BCI_BUSY = 14 -GRBM_SE6_PERF_SEL_RMI_BUSY = 15 -GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE6_PERF_SEL_TCP_BUSY = 17 -GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE6_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE6_PERF_SEL_PC_BUSY = 20 -GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'GRBM_SE7_PERF_SEL' -GRBM_SE7_PERF_SEL__enumvalues = { - 0: 'GRBM_SE7_PERF_SEL_COUNT', - 1: 'GRBM_SE7_PERF_SEL_USER_DEFINED', - 2: 'GRBM_SE7_PERF_SEL_CB_BUSY', - 3: 'GRBM_SE7_PERF_SEL_DB_BUSY', - 4: 'GRBM_SE7_PERF_SEL_SC_BUSY', - 6: 'GRBM_SE7_PERF_SEL_SPI_BUSY', - 7: 'GRBM_SE7_PERF_SEL_SX_BUSY', - 8: 'GRBM_SE7_PERF_SEL_TA_BUSY', - 9: 'GRBM_SE7_PERF_SEL_CB_CLEAN', - 10: 'GRBM_SE7_PERF_SEL_DB_CLEAN', - 12: 'GRBM_SE7_PERF_SEL_PA_BUSY', - 14: 'GRBM_SE7_PERF_SEL_BCI_BUSY', - 15: 'GRBM_SE7_PERF_SEL_RMI_BUSY', - 16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', - 17: 'GRBM_SE7_PERF_SEL_TCP_BUSY', - 18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', - 19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY', - 20: 'GRBM_SE7_PERF_SEL_PC_BUSY', -} -GRBM_SE7_PERF_SEL_COUNT = 0 -GRBM_SE7_PERF_SEL_USER_DEFINED = 1 -GRBM_SE7_PERF_SEL_CB_BUSY = 2 -GRBM_SE7_PERF_SEL_DB_BUSY = 3 -GRBM_SE7_PERF_SEL_SC_BUSY = 4 -GRBM_SE7_PERF_SEL_SPI_BUSY = 6 -GRBM_SE7_PERF_SEL_SX_BUSY = 7 -GRBM_SE7_PERF_SEL_TA_BUSY = 8 -GRBM_SE7_PERF_SEL_CB_CLEAN = 9 -GRBM_SE7_PERF_SEL_DB_CLEAN = 10 -GRBM_SE7_PERF_SEL_PA_BUSY = 12 -GRBM_SE7_PERF_SEL_BCI_BUSY = 14 -GRBM_SE7_PERF_SEL_RMI_BUSY = 15 -GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16 -GRBM_SE7_PERF_SEL_TCP_BUSY = 17 -GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18 -GRBM_SE7_PERF_SEL_GL1H_BUSY = 19 -GRBM_SE7_PERF_SEL_PC_BUSY = 20 -GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PIPE_COMPAT_LEVEL' -PIPE_COMPAT_LEVEL__enumvalues = { - 0: 'GEN_ZERO', - 1: 'GEN_ONE', - 2: 'GEN_TWO', - 3: 'GEN_RESERVED', -} -GEN_ZERO = 0 -GEN_ONE = 1 -GEN_TWO = 2 -GEN_RESERVED = 3 -PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_LATENCY_STATS_SEL' -CPC_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', -} -CPC_LATENCY_STATS_SEL_XACK_MAX = 0 -CPC_LATENCY_STATS_SEL_XACK_MIN = 1 -CPC_LATENCY_STATS_SEL_XACK_LAST = 2 -CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 -CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 -CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 -CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPC_PERFCOUNT_SEL' -CPC_PERFCOUNT_SEL__enumvalues = { - 0: 'CPC_PERF_SEL_ALWAYS_COUNT', - 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', - 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', - 27: 'CPC_PERF_SEL_CPC_STAT_STALL', - 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', - 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', - 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', - 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', - 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', - 45: 'CPC_PERF_SEL_MES_THREAD0', - 46: 'CPC_PERF_SEL_MES_THREAD1', -} -CPC_PERF_SEL_ALWAYS_COUNT = 0 -CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 -CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 -CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 -CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 -CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 -CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 -CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 -CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 -CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 -CPC_PERF_SEL_CPC_STAT_BUSY = 25 -CPC_PERF_SEL_CPC_STAT_IDLE = 26 -CPC_PERF_SEL_CPC_STAT_STALL = 27 -CPC_PERF_SEL_CPC_TCIU_BUSY = 28 -CPC_PERF_SEL_CPC_TCIU_IDLE = 29 -CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 -CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 -CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 -CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 -CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 -CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 -CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 -CPC_PERF_SEL_CPC_GCRIU_STALL = 37 -CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 -CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 -CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 -CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 -CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 -CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 -CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 -CPC_PERF_SEL_MES_THREAD0 = 45 -CPC_PERF_SEL_MES_THREAD1 = 46 -CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_LATENCY_STATS_SEL' -CPF_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', - 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', - 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', - 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', -} -CPF_LATENCY_STATS_SEL_XACK_MAX = 0 -CPF_LATENCY_STATS_SEL_XACK_MIN = 1 -CPF_LATENCY_STATS_SEL_XACK_LAST = 2 -CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPF_LATENCY_STATS_SEL_READ_MAX = 6 -CPF_LATENCY_STATS_SEL_READ_MIN = 7 -CPF_LATENCY_STATS_SEL_READ_LAST = 8 -CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 -CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 -CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 -CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' -CPF_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPF_PERFWINDOW_SEL_CSF', - 1: 'CPF_PERFWINDOW_SEL_HQD1', - 2: 'CPF_PERFWINDOW_SEL_HQD2', - 3: 'CPF_PERFWINDOW_SEL_RDMA', - 4: 'CPF_PERFWINDOW_SEL_RWPP', -} -CPF_PERFWINDOW_SEL_CSF = 0 -CPF_PERFWINDOW_SEL_HQD1 = 1 -CPF_PERFWINDOW_SEL_HQD2 = 2 -CPF_PERFWINDOW_SEL_RDMA = 3 -CPF_PERFWINDOW_SEL_RWPP = 4 -CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_PERFCOUNT_SEL' -CPF_PERFCOUNT_SEL__enumvalues = { - 0: 'CPF_PERF_SEL_ALWAYS_COUNT', - 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', - 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', - 26: 'CPF_PERF_SEL_CPF_STAT_STALL', - 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', - 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', - 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', - 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', - 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', - 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', - 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', -} -CPF_PERF_SEL_ALWAYS_COUNT = 0 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 -CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 -CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 -CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 -CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 -CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 -CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 -CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 -CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 -CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 -CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 -CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 -CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 -CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 -CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 -CPF_PERF_SEL_CPF_STAT_BUSY = 24 -CPF_PERF_SEL_CPF_STAT_IDLE = 25 -CPF_PERF_SEL_CPF_STAT_STALL = 26 -CPF_PERF_SEL_CPF_TCIU_BUSY = 27 -CPF_PERF_SEL_CPF_TCIU_IDLE = 28 -CPF_PERF_SEL_CPF_TCIU_STALL = 29 -CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 -CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 -CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 -CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 -CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 -CPF_PERF_SEL_CPF_GCRIU_STALL = 35 -CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 -CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 -CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 -CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 -CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 -CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 -CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 -CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' -CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { - 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', - 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', - 2: 'CPF_SCRATCH_REG_ATOMIC_OR', - 3: 'CPF_SCRATCH_REG_ATOMIC_AND', - 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', - 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', - 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', - 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', -} -CPF_SCRATCH_REG_ATOMIC_ADD = 0 -CPF_SCRATCH_REG_ATOMIC_SUB = 1 -CPF_SCRATCH_REG_ATOMIC_OR = 2 -CPF_SCRATCH_REG_ATOMIC_AND = 3 -CPF_SCRATCH_REG_ATOMIC_NOT = 4 -CPF_SCRATCH_REG_ATOMIC_MIN = 5 -CPF_SCRATCH_REG_ATOMIC_MAX = 6 -CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 -CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_LATENCY_STATS_SEL' -CPG_LATENCY_STATS_SEL__enumvalues = { - 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', - 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', - 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', - 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', - 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', -} -CPG_LATENCY_STATS_SEL_XACK_MAX = 0 -CPG_LATENCY_STATS_SEL_XACK_MIN = 1 -CPG_LATENCY_STATS_SEL_XACK_LAST = 2 -CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 -CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 -CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 -CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 -CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 -CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 -CPG_LATENCY_STATS_SEL_READ_MAX = 9 -CPG_LATENCY_STATS_SEL_READ_MIN = 10 -CPG_LATENCY_STATS_SEL_READ_LAST = 11 -CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 -CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 -CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 -CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 -CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 -CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 -CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' -CPG_PERFCOUNTWINDOW_SEL__enumvalues = { - 0: 'CPG_PERFWINDOW_SEL_PFP', - 1: 'CPG_PERFWINDOW_SEL_ME', - 2: 'CPG_PERFWINDOW_SEL_CE', - 3: 'CPG_PERFWINDOW_SEL_MES', - 4: 'CPG_PERFWINDOW_SEL_MEC1', - 5: 'CPG_PERFWINDOW_SEL_MEC2', - 6: 'CPG_PERFWINDOW_SEL_DFY', - 7: 'CPG_PERFWINDOW_SEL_DMA', - 8: 'CPG_PERFWINDOW_SEL_SHADOW', - 9: 'CPG_PERFWINDOW_SEL_RB', - 10: 'CPG_PERFWINDOW_SEL_CEDMA', - 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', - 13: 'CPG_PERFWINDOW_SEL_PQ1', - 14: 'CPG_PERFWINDOW_SEL_PQ2', - 15: 'CPG_PERFWINDOW_SEL_PQ3', - 16: 'CPG_PERFWINDOW_SEL_MEMWR', - 17: 'CPG_PERFWINDOW_SEL_MEMRD', - 18: 'CPG_PERFWINDOW_SEL_VGT0', - 19: 'CPG_PERFWINDOW_SEL_VGT1', - 20: 'CPG_PERFWINDOW_SEL_APPEND', - 21: 'CPG_PERFWINDOW_SEL_QURD', - 22: 'CPG_PERFWINDOW_SEL_DDID', - 23: 'CPG_PERFWINDOW_SEL_SR', - 24: 'CPG_PERFWINDOW_SEL_QU_EOP', - 25: 'CPG_PERFWINDOW_SEL_QU_STRM', - 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', - 27: 'CPG_PERFWINDOW_SEL_RESERVED1', - 28: 'CPG_PERFWINDOW_SEL_CPC_IC', - 29: 'CPG_PERFWINDOW_SEL_RESERVED2', - 30: 'CPG_PERFWINDOW_SEL_CPG_IC', -} -CPG_PERFWINDOW_SEL_PFP = 0 -CPG_PERFWINDOW_SEL_ME = 1 -CPG_PERFWINDOW_SEL_CE = 2 -CPG_PERFWINDOW_SEL_MES = 3 -CPG_PERFWINDOW_SEL_MEC1 = 4 -CPG_PERFWINDOW_SEL_MEC2 = 5 -CPG_PERFWINDOW_SEL_DFY = 6 -CPG_PERFWINDOW_SEL_DMA = 7 -CPG_PERFWINDOW_SEL_SHADOW = 8 -CPG_PERFWINDOW_SEL_RB = 9 -CPG_PERFWINDOW_SEL_CEDMA = 10 -CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 -CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 -CPG_PERFWINDOW_SEL_PQ1 = 13 -CPG_PERFWINDOW_SEL_PQ2 = 14 -CPG_PERFWINDOW_SEL_PQ3 = 15 -CPG_PERFWINDOW_SEL_MEMWR = 16 -CPG_PERFWINDOW_SEL_MEMRD = 17 -CPG_PERFWINDOW_SEL_VGT0 = 18 -CPG_PERFWINDOW_SEL_VGT1 = 19 -CPG_PERFWINDOW_SEL_APPEND = 20 -CPG_PERFWINDOW_SEL_QURD = 21 -CPG_PERFWINDOW_SEL_DDID = 22 -CPG_PERFWINDOW_SEL_SR = 23 -CPG_PERFWINDOW_SEL_QU_EOP = 24 -CPG_PERFWINDOW_SEL_QU_STRM = 25 -CPG_PERFWINDOW_SEL_QU_PIPE = 26 -CPG_PERFWINDOW_SEL_RESERVED1 = 27 -CPG_PERFWINDOW_SEL_CPC_IC = 28 -CPG_PERFWINDOW_SEL_RESERVED2 = 29 -CPG_PERFWINDOW_SEL_CPG_IC = 30 -CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CPG_PERFCOUNT_SEL' -CPG_PERFCOUNT_SEL__enumvalues = { - 0: 'CPG_PERF_SEL_ALWAYS_COUNT', - 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', - 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', - 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', - 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', - 53: 'CPG_PERF_SEL_CPG_STAT_STALL', - 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', - 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', - 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', - 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', - 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', - 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', - 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', - 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 78: 'CPG_PERF_SEL_DMA_BUSY', - 79: 'CPG_PERF_SEL_DMA_STARVED', - 80: 'CPG_PERF_SEL_DMA_STALLED', - 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', - 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', - 84: 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 85: 'CPG_PERF_SEL_ME_PWS_STALLED1', -} -CPG_PERF_SEL_ALWAYS_COUNT = 0 -CPG_PERF_SEL_RBIU_FIFO_FULL = 1 -CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 -CPG_PERF_SEL_ME_PARSER_BUSY = 5 -CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 -CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 -CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 -CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 -CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 -CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 -CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 -CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 -CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 -CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 -CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 -CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 -CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 -CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 -CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 -CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 -CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 -CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 -CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 -CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 -CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 -CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 -CPG_PERF_SEL_REGISTER_CLK_VALID = 33 -CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 -CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 -CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 -CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 -CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 -CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 -CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 -CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 -CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 -CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 -CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 -CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 -CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 -CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 -CPG_PERF_SEL_CPG_STAT_BUSY = 51 -CPG_PERF_SEL_CPG_STAT_IDLE = 52 -CPG_PERF_SEL_CPG_STAT_STALL = 53 -CPG_PERF_SEL_CPG_TCIU_BUSY = 54 -CPG_PERF_SEL_CPG_TCIU_IDLE = 55 -CPG_PERF_SEL_CPG_TCIU_STALL = 56 -CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 -CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 -CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 -CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 -CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 -CPG_PERF_SEL_CPG_GCRIU_STALL = 62 -CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 -CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 -CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 -CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 -CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 -CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 -CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 -CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 -CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 -CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 -CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 -CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 -CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 -CPG_PERF_SEL_DMA_BUSY = 78 -CPG_PERF_SEL_DMA_STARVED = 79 -CPG_PERF_SEL_DMA_STALLED = 80 -CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 -CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 -CPG_PERF_SEL_ME_PWS_STALLED0 = 83 -CPG_PERF_SEL_PFP_PWS_STALLED1 = 84 -CPG_PERF_SEL_ME_PWS_STALLED1 = 85 -CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' -CP_ALPHA_TAG_RAM_SEL__enumvalues = { - 0: 'CPG_TAG_RAM', - 1: 'CPC_TAG_RAM', - 2: 'CPF_TAG_RAM', - 3: 'RSV_TAG_RAM', -} -CPG_TAG_RAM = 0 -CPC_TAG_RAM = 1 -CPF_TAG_RAM = 2 -RSV_TAG_RAM = 3 -CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_MODE' -CP_DDID_CNTL_MODE__enumvalues = { - 0: 'STALL', - 1: 'OVERRUN', -} -STALL = 0 -OVERRUN = 1 -CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_SIZE' -CP_DDID_CNTL_SIZE__enumvalues = { - 0: 'SIZE_8K', - 1: 'SIZE_16K', -} -SIZE_8K = 0 -SIZE_16K = 1 -CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_DDID_CNTL_VMID_SEL' -CP_DDID_CNTL_VMID_SEL__enumvalues = { - 0: 'DDID_VMID_PIPE', - 1: 'DDID_VMID_CNTL', -} -DDID_VMID_PIPE = 0 -DDID_VMID_CNTL = 1 -CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'CP_ME_ID' -CP_ME_ID__enumvalues = { - 0: 'ME_ID0', - 1: 'ME_ID1', - 2: 'ME_ID2', - 3: 'ME_ID3', -} -ME_ID0 = 0 -ME_ID1 = 1 -ME_ID2 = 2 -ME_ID3 = 3 -CP_ME_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_ENABLE_MODE' -CP_PERFMON_ENABLE_MODE__enumvalues = { - 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', - 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', -} -CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 -CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 -CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 -CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PERFMON_STATE' -CP_PERFMON_STATE__enumvalues = { - 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'CP_PERFMON_STATE_START_COUNTING', - 2: 'CP_PERFMON_STATE_STOP_COUNTING', - 3: 'CP_PERFMON_STATE_RESERVED_3', - 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -CP_PERFMON_STATE_DISABLE_AND_RESET = 0 -CP_PERFMON_STATE_START_COUNTING = 1 -CP_PERFMON_STATE_STOP_COUNTING = 2 -CP_PERFMON_STATE_RESERVED_3 = 3 -CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -CP_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'CP_PIPE_ID' -CP_PIPE_ID__enumvalues = { - 0: 'PIPE_ID0', - 1: 'PIPE_ID1', - 2: 'PIPE_ID2', - 3: 'PIPE_ID3', -} -PIPE_ID0 = 0 -PIPE_ID1 = 1 -PIPE_ID2 = 2 -PIPE_ID3 = 3 -CP_PIPE_ID = ctypes.c_uint32 # enum - -# values for enumeration 'CP_RING_ID' -CP_RING_ID__enumvalues = { - 0: 'RINGID0', - 1: 'RINGID1', - 2: 'RINGID2', - 3: 'RINGID3', -} -RINGID0 = 0 -RINGID1 = 1 -RINGID2 = 2 -RINGID3 = 3 -CP_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'SPM_PERFMON_STATE' -SPM_PERFMON_STATE__enumvalues = { - 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 1: 'STRM_PERFMON_STATE_START_COUNTING', - 2: 'STRM_PERFMON_STATE_STOP_COUNTING', - 3: 'STRM_PERFMON_STATE_RESERVED_3', - 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', -} -STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 -STRM_PERFMON_STATE_START_COUNTING = 1 -STRM_PERFMON_STATE_STOP_COUNTING = 2 -STRM_PERFMON_STATE_RESERVED_3 = 3 -STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 -STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 -SPM_PERFMON_STATE = ctypes.c_uint32 # enum - -# values for enumeration 'SX_BLEND_OPT' -SX_BLEND_OPT__enumvalues = { - 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', -} -BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 -BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 -BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 -BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 -BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 -BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 -BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 -BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 -SX_BLEND_OPT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_DOWNCONVERT_FORMAT' -SX_DOWNCONVERT_FORMAT__enumvalues = { - 0: 'SX_RT_EXPORT_NO_CONVERSION', - 1: 'SX_RT_EXPORT_32_R', - 2: 'SX_RT_EXPORT_32_A', - 3: 'SX_RT_EXPORT_10_11_11', - 4: 'SX_RT_EXPORT_2_10_10_10', - 5: 'SX_RT_EXPORT_8_8_8_8', - 6: 'SX_RT_EXPORT_5_6_5', - 7: 'SX_RT_EXPORT_1_5_5_5', - 8: 'SX_RT_EXPORT_4_4_4_4', - 9: 'SX_RT_EXPORT_16_16_GR', - 10: 'SX_RT_EXPORT_16_16_AR', - 11: 'SX_RT_EXPORT_9_9_9_E5', - 12: 'SX_RT_EXPORT_2_10_10_10_7E3', - 13: 'SX_RT_EXPORT_2_10_10_10_6E4', -} -SX_RT_EXPORT_NO_CONVERSION = 0 -SX_RT_EXPORT_32_R = 1 -SX_RT_EXPORT_32_A = 2 -SX_RT_EXPORT_10_11_11 = 3 -SX_RT_EXPORT_2_10_10_10 = 4 -SX_RT_EXPORT_8_8_8_8 = 5 -SX_RT_EXPORT_5_6_5 = 6 -SX_RT_EXPORT_1_5_5_5 = 7 -SX_RT_EXPORT_4_4_4_4 = 8 -SX_RT_EXPORT_16_16_GR = 9 -SX_RT_EXPORT_16_16_AR = 10 -SX_RT_EXPORT_9_9_9_E5 = 11 -SX_RT_EXPORT_2_10_10_10_7E3 = 12 -SX_RT_EXPORT_2_10_10_10_6E4 = 13 -SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum - -# values for enumeration 'SX_OPT_COMB_FCN' -SX_OPT_COMB_FCN__enumvalues = { - 0: 'OPT_COMB_NONE', - 1: 'OPT_COMB_ADD', - 2: 'OPT_COMB_SUBTRACT', - 3: 'OPT_COMB_MIN', - 4: 'OPT_COMB_MAX', - 5: 'OPT_COMB_REVSUBTRACT', - 6: 'OPT_COMB_BLEND_DISABLED', - 7: 'OPT_COMB_SAFE_ADD', -} -OPT_COMB_NONE = 0 -OPT_COMB_ADD = 1 -OPT_COMB_SUBTRACT = 2 -OPT_COMB_MIN = 3 -OPT_COMB_MAX = 4 -OPT_COMB_REVSUBTRACT = 5 -OPT_COMB_BLEND_DISABLED = 6 -OPT_COMB_SAFE_ADD = 7 -SX_OPT_COMB_FCN = ctypes.c_uint32 # enum - -# values for enumeration 'SX_PERFCOUNTER_VALS' -SX_PERFCOUNTER_VALS__enumvalues = { - 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', - 1: 'SX_PERF_SEL_PA_REQ', - 2: 'SX_PERF_SEL_PA_POS', - 3: 'SX_PERF_SEL_CLOCK', - 4: 'SX_PERF_SEL_GATE_EN1', - 5: 'SX_PERF_SEL_GATE_EN2', - 6: 'SX_PERF_SEL_GATE_EN3', - 7: 'SX_PERF_SEL_GATE_EN4', - 8: 'SX_PERF_SEL_SH_POS_STARVE', - 9: 'SX_PERF_SEL_SH_COLOR_STARVE', - 10: 'SX_PERF_SEL_SH_POS_STALL', - 11: 'SX_PERF_SEL_SH_COLOR_STALL', - 12: 'SX_PERF_SEL_DB0_PIXELS', - 13: 'SX_PERF_SEL_DB0_HALF_QUADS', - 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', - 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', - 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', - 17: 'SX_PERF_SEL_DB1_PIXELS', - 18: 'SX_PERF_SEL_DB1_HALF_QUADS', - 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', - 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', - 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', - 22: 'SX_PERF_SEL_DB2_PIXELS', - 23: 'SX_PERF_SEL_DB2_HALF_QUADS', - 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', - 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', - 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', - 27: 'SX_PERF_SEL_DB3_PIXELS', - 28: 'SX_PERF_SEL_DB3_HALF_QUADS', - 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', - 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', - 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', - 32: 'SX_PERF_SEL_COL_BUSY', - 33: 'SX_PERF_SEL_POS_BUSY', - 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', - 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', - 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', - 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', - 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 54: 'SX_PERF_SEL_PA_REQ_LATENCY', - 55: 'SX_PERF_SEL_POS_SCBD_STALL', - 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', - 57: 'SX_PERF_SEL_GATE_EN5', - 58: 'SX_PERF_SEL_GATE_EN6', - 59: 'SX_PERF_SEL_DB0_SIZE', - 60: 'SX_PERF_SEL_DB1_SIZE', - 61: 'SX_PERF_SEL_DB2_SIZE', - 62: 'SX_PERF_SEL_DB3_SIZE', - 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', - 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 65: 'SX_PERF_SEL_IDX_REQ', - 66: 'SX_PERF_SEL_IDX_RET', - 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', - 68: 'SX_PERF_SEL_IDX_SCBD_STALL', - 69: 'SX_PERF_SEL_GATE_EN7', - 70: 'SX_PERF_SEL_GATE_EN8', - 71: 'SX_PERF_SEL_SH_IDX_STARVE', - 72: 'SX_PERF_SEL_IDX_BUSY', - 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', - 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', - 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', - 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', - 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', - 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', - 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', - 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', - 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', -} -SX_PERF_SEL_PA_IDLE_CYCLES = 0 -SX_PERF_SEL_PA_REQ = 1 -SX_PERF_SEL_PA_POS = 2 -SX_PERF_SEL_CLOCK = 3 -SX_PERF_SEL_GATE_EN1 = 4 -SX_PERF_SEL_GATE_EN2 = 5 -SX_PERF_SEL_GATE_EN3 = 6 -SX_PERF_SEL_GATE_EN4 = 7 -SX_PERF_SEL_SH_POS_STARVE = 8 -SX_PERF_SEL_SH_COLOR_STARVE = 9 -SX_PERF_SEL_SH_POS_STALL = 10 -SX_PERF_SEL_SH_COLOR_STALL = 11 -SX_PERF_SEL_DB0_PIXELS = 12 -SX_PERF_SEL_DB0_HALF_QUADS = 13 -SX_PERF_SEL_DB0_PIXEL_STALL = 14 -SX_PERF_SEL_DB0_PIXEL_IDLE = 15 -SX_PERF_SEL_DB0_PRED_PIXELS = 16 -SX_PERF_SEL_DB1_PIXELS = 17 -SX_PERF_SEL_DB1_HALF_QUADS = 18 -SX_PERF_SEL_DB1_PIXEL_STALL = 19 -SX_PERF_SEL_DB1_PIXEL_IDLE = 20 -SX_PERF_SEL_DB1_PRED_PIXELS = 21 -SX_PERF_SEL_DB2_PIXELS = 22 -SX_PERF_SEL_DB2_HALF_QUADS = 23 -SX_PERF_SEL_DB2_PIXEL_STALL = 24 -SX_PERF_SEL_DB2_PIXEL_IDLE = 25 -SX_PERF_SEL_DB2_PRED_PIXELS = 26 -SX_PERF_SEL_DB3_PIXELS = 27 -SX_PERF_SEL_DB3_HALF_QUADS = 28 -SX_PERF_SEL_DB3_PIXEL_STALL = 29 -SX_PERF_SEL_DB3_PIXEL_IDLE = 30 -SX_PERF_SEL_DB3_PRED_PIXELS = 31 -SX_PERF_SEL_COL_BUSY = 32 -SX_PERF_SEL_POS_BUSY = 33 -SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 -SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 -SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 -SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 -SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 -SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 -SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 -SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 -SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 -SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 -SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 -SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 -SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 -SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 -SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 -SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 -SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 -SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 -SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 -SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 -SX_PERF_SEL_PA_REQ_LATENCY = 54 -SX_PERF_SEL_POS_SCBD_STALL = 55 -SX_PERF_SEL_CLOCK_DROP_STALL = 56 -SX_PERF_SEL_GATE_EN5 = 57 -SX_PERF_SEL_GATE_EN6 = 58 -SX_PERF_SEL_DB0_SIZE = 59 -SX_PERF_SEL_DB1_SIZE = 60 -SX_PERF_SEL_DB2_SIZE = 61 -SX_PERF_SEL_DB3_SIZE = 62 -SX_PERF_SEL_IDX_STALL_CYCLES = 63 -SX_PERF_SEL_IDX_IDLE_CYCLES = 64 -SX_PERF_SEL_IDX_REQ = 65 -SX_PERF_SEL_IDX_RET = 66 -SX_PERF_SEL_IDX_REQ_LATENCY = 67 -SX_PERF_SEL_IDX_SCBD_STALL = 68 -SX_PERF_SEL_GATE_EN7 = 69 -SX_PERF_SEL_GATE_EN8 = 70 -SX_PERF_SEL_SH_IDX_STARVE = 71 -SX_PERF_SEL_IDX_BUSY = 72 -SX_PERF_SEL_PA_POS_BANK_CONF = 73 -SX_PERF_SEL_DB0_END_OF_WAVE = 74 -SX_PERF_SEL_DB0_4X2_DISCARD = 75 -SX_PERF_SEL_DB1_END_OF_WAVE = 76 -SX_PERF_SEL_DB1_4X2_DISCARD = 77 -SX_PERF_SEL_DB2_END_OF_WAVE = 78 -SX_PERF_SEL_DB2_4X2_DISCARD = 79 -SX_PERF_SEL_DB3_END_OF_WAVE = 80 -SX_PERF_SEL_DB3_4X2_DISCARD = 81 -SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum - -# values for enumeration 'CompareFrag' -CompareFrag__enumvalues = { - 0: 'FRAG_NEVER', - 1: 'FRAG_LESS', - 2: 'FRAG_EQUAL', - 3: 'FRAG_LEQUAL', - 4: 'FRAG_GREATER', - 5: 'FRAG_NOTEQUAL', - 6: 'FRAG_GEQUAL', - 7: 'FRAG_ALWAYS', -} -FRAG_NEVER = 0 -FRAG_LESS = 1 -FRAG_EQUAL = 2 -FRAG_LEQUAL = 3 -FRAG_GREATER = 4 -FRAG_NOTEQUAL = 5 -FRAG_GEQUAL = 6 -FRAG_ALWAYS = 7 -CompareFrag = ctypes.c_uint32 # enum - -# values for enumeration 'ConservativeZExport' -ConservativeZExport__enumvalues = { - 0: 'EXPORT_ANY_Z', - 1: 'EXPORT_LESS_THAN_Z', - 2: 'EXPORT_GREATER_THAN_Z', - 3: 'EXPORT_RESERVED', -} -EXPORT_ANY_Z = 0 -EXPORT_LESS_THAN_Z = 1 -EXPORT_GREATER_THAN_Z = 2 -EXPORT_RESERVED = 3 -ConservativeZExport = ctypes.c_uint32 # enum - -# values for enumeration 'DFSMFlushEvents' -DFSMFlushEvents__enumvalues = { - 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', - 1: 'DB_FLUSH_AND_INV_DB_META', - 2: 'DB_CACHE_FLUSH', - 3: 'DB_CACHE_FLUSH_TS', - 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', - 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', - 6: 'DB_VPORT_CHANGED_EVENT', - 7: 'DB_CONTEXT_DONE_EVENT', - 8: 'DB_BREAK_BATCH_EVENT', - 9: 'DB_INVOKE_CHANGE_EVENT', - 10: 'DB_CONTEXT_SUSPEND_EVENT', -} -DB_FLUSH_AND_INV_DB_DATA_TS = 0 -DB_FLUSH_AND_INV_DB_META = 1 -DB_CACHE_FLUSH = 2 -DB_CACHE_FLUSH_TS = 3 -DB_CACHE_FLUSH_AND_INV_EVENT = 4 -DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 -DB_VPORT_CHANGED_EVENT = 6 -DB_CONTEXT_DONE_EVENT = 7 -DB_BREAK_BATCH_EVENT = 8 -DB_INVOKE_CHANGE_EVENT = 9 -DB_CONTEXT_SUSPEND_EVENT = 10 -DFSMFlushEvents = ctypes.c_uint32 # enum - -# values for enumeration 'DbMemArbWatermarks' -DbMemArbWatermarks__enumvalues = { - 0: 'TRANSFERRED_64_BYTES', - 1: 'TRANSFERRED_128_BYTES', - 2: 'TRANSFERRED_256_BYTES', - 3: 'TRANSFERRED_512_BYTES', - 4: 'TRANSFERRED_1024_BYTES', - 5: 'TRANSFERRED_2048_BYTES', - 6: 'TRANSFERRED_4096_BYTES', - 7: 'TRANSFERRED_8192_BYTES', -} -TRANSFERRED_64_BYTES = 0 -TRANSFERRED_128_BYTES = 1 -TRANSFERRED_256_BYTES = 2 -TRANSFERRED_512_BYTES = 3 -TRANSFERRED_1024_BYTES = 4 -TRANSFERRED_2048_BYTES = 5 -TRANSFERRED_4096_BYTES = 6 -TRANSFERRED_8192_BYTES = 7 -DbMemArbWatermarks = ctypes.c_uint32 # enum - -# values for enumeration 'DbPRTFaultBehavior' -DbPRTFaultBehavior__enumvalues = { - 0: 'FAULT_ZERO', - 1: 'FAULT_ONE', - 2: 'FAULT_FAIL', - 3: 'FAULT_PASS', -} -FAULT_ZERO = 0 -FAULT_ONE = 1 -FAULT_FAIL = 2 -FAULT_PASS = 3 -DbPRTFaultBehavior = ctypes.c_uint32 # enum - -# values for enumeration 'DbPSLControl' -DbPSLControl__enumvalues = { - 0: 'PSLC_AUTO', - 1: 'PSLC_ON_HANG_ONLY', - 2: 'PSLC_ASAP', - 3: 'PSLC_COUNTDOWN', -} -PSLC_AUTO = 0 -PSLC_ON_HANG_ONLY = 1 -PSLC_ASAP = 2 -PSLC_COUNTDOWN = 3 -DbPSLControl = ctypes.c_uint32 # enum - -# values for enumeration 'ForceControl' -ForceControl__enumvalues = { - 0: 'FORCE_OFF', - 1: 'FORCE_ENABLE', - 2: 'FORCE_DISABLE', - 3: 'FORCE_RESERVED', -} -FORCE_OFF = 0 -FORCE_ENABLE = 1 -FORCE_DISABLE = 2 -FORCE_RESERVED = 3 -ForceControl = ctypes.c_uint32 # enum - -# values for enumeration 'OreoMode' -OreoMode__enumvalues = { - 0: 'OMODE_BLEND', - 1: 'OMODE_O_THEN_B', - 2: 'OMODE_P_THEN_O_THEN_B', - 3: 'OMODE_RESERVED_3', -} -OMODE_BLEND = 0 -OMODE_O_THEN_B = 1 -OMODE_P_THEN_O_THEN_B = 2 -OMODE_RESERVED_3 = 3 -OreoMode = ctypes.c_uint32 # enum - -# values for enumeration 'PerfCounter_Vals' -PerfCounter_Vals__enumvalues = { - 0: 'DB_PERF_SEL_SC_DB_tile_sends', - 1: 'DB_PERF_SEL_SC_DB_tile_busy', - 2: 'DB_PERF_SEL_SC_DB_tile_stalls', - 3: 'DB_PERF_SEL_SC_DB_tile_events', - 4: 'DB_PERF_SEL_SC_DB_tile_tiles', - 5: 'DB_PERF_SEL_SC_DB_tile_covered', - 6: 'DB_PERF_SEL_hiz_tc_read_starved', - 7: 'DB_PERF_SEL_hiz_tc_write_stall', - 8: 'DB_PERF_SEL_hiz_tile_culled', - 9: 'DB_PERF_SEL_his_tile_culled', - 10: 'DB_PERF_SEL_DB_SC_tile_sends', - 11: 'DB_PERF_SEL_DB_SC_tile_busy', - 12: 'DB_PERF_SEL_DB_SC_tile_stalls', - 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 14: 'DB_PERF_SEL_DB_SC_tile_tiles', - 15: 'DB_PERF_SEL_DB_SC_tile_culled', - 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', - 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 23: 'DB_PERF_SEL_SC_DB_quad_sends', - 24: 'DB_PERF_SEL_SC_DB_quad_busy', - 25: 'DB_PERF_SEL_SC_DB_quad_squads', - 26: 'DB_PERF_SEL_SC_DB_quad_tiles', - 27: 'DB_PERF_SEL_SC_DB_quad_pixels', - 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 29: 'DB_PERF_SEL_DB_SC_quad_sends', - 30: 'DB_PERF_SEL_DB_SC_quad_busy', - 31: 'DB_PERF_SEL_DB_SC_quad_stalls', - 32: 'DB_PERF_SEL_DB_SC_quad_tiles', - 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 34: 'DB_PERF_SEL_DB_CB_tile_sends', - 35: 'DB_PERF_SEL_DB_CB_tile_busy', - 36: 'DB_PERF_SEL_DB_CB_tile_stalls', - 37: 'DB_PERF_SEL_SX_DB_quad_sends', - 38: 'DB_PERF_SEL_SX_DB_quad_busy', - 39: 'DB_PERF_SEL_SX_DB_quad_stalls', - 40: 'DB_PERF_SEL_SX_DB_quad_quads', - 41: 'DB_PERF_SEL_SX_DB_quad_pixels', - 42: 'DB_PERF_SEL_SX_DB_quad_exports', - 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', - 44: 'DB_PERF_SEL_DB_CB_lquad_sends', - 45: 'DB_PERF_SEL_DB_CB_lquad_busy', - 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', - 47: 'DB_PERF_SEL_DB_CB_lquad_quads', - 48: 'DB_PERF_SEL_tile_rd_sends', - 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 50: 'DB_PERF_SEL_quad_rd_sends', - 51: 'DB_PERF_SEL_quad_rd_busy', - 52: 'DB_PERF_SEL_quad_rd_mi_stall', - 53: 'DB_PERF_SEL_quad_rd_rw_collision', - 54: 'DB_PERF_SEL_quad_rd_tag_stall', - 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', - 56: 'DB_PERF_SEL_quad_rd_panic', - 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 58: 'DB_PERF_SEL_quad_rdret_sends', - 59: 'DB_PERF_SEL_quad_rdret_busy', - 60: 'DB_PERF_SEL_tile_wr_sends', - 61: 'DB_PERF_SEL_tile_wr_acks', - 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 63: 'DB_PERF_SEL_quad_wr_sends', - 64: 'DB_PERF_SEL_quad_wr_busy', - 65: 'DB_PERF_SEL_quad_wr_mi_stall', - 66: 'DB_PERF_SEL_quad_wr_coherency_stall', - 67: 'DB_PERF_SEL_quad_wr_acks', - 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 69: 'DB_PERF_SEL_Tile_Cache_misses', - 70: 'DB_PERF_SEL_Tile_Cache_hits', - 71: 'DB_PERF_SEL_Tile_Cache_flushes', - 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', - 73: 'DB_PERF_SEL_Tile_Cache_starves', - 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 75: 'DB_PERF_SEL_tcp_dispatcher_reads', - 76: 'DB_PERF_SEL_tcp_prefetcher_reads', - 77: 'DB_PERF_SEL_tcp_preloader_reads', - 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', - 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', - 80: 'DB_PERF_SEL_tcp_preloader_flushes', - 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', - 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 95: 'DB_PERF_SEL_Stencil_Cache_misses', - 96: 'DB_PERF_SEL_Stencil_Cache_hits', - 97: 'DB_PERF_SEL_Stencil_Cache_flushes', - 98: 'DB_PERF_SEL_Stencil_Cache_starves', - 99: 'DB_PERF_SEL_Stencil_Cache_frees', - 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', - 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', - 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', - 108: 'DB_PERF_SEL_Z_Cache_frees', - 109: 'DB_PERF_SEL_Plane_Cache_misses', - 110: 'DB_PERF_SEL_Plane_Cache_hits', - 111: 'DB_PERF_SEL_Plane_Cache_flushes', - 112: 'DB_PERF_SEL_Plane_Cache_starves', - 113: 'DB_PERF_SEL_Plane_Cache_frees', - 114: 'DB_PERF_SEL_flush_expanded_stencil', - 115: 'DB_PERF_SEL_flush_compressed_stencil', - 116: 'DB_PERF_SEL_flush_single_stencil', - 117: 'DB_PERF_SEL_planes_flushed', - 118: 'DB_PERF_SEL_flush_1plane', - 119: 'DB_PERF_SEL_flush_2plane', - 120: 'DB_PERF_SEL_flush_3plane', - 121: 'DB_PERF_SEL_flush_4plane', - 122: 'DB_PERF_SEL_flush_5plane', - 123: 'DB_PERF_SEL_flush_6plane', - 124: 'DB_PERF_SEL_flush_7plane', - 125: 'DB_PERF_SEL_flush_8plane', - 126: 'DB_PERF_SEL_flush_9plane', - 127: 'DB_PERF_SEL_flush_10plane', - 128: 'DB_PERF_SEL_flush_11plane', - 129: 'DB_PERF_SEL_flush_12plane', - 130: 'DB_PERF_SEL_flush_13plane', - 131: 'DB_PERF_SEL_flush_14plane', - 132: 'DB_PERF_SEL_flush_15plane', - 133: 'DB_PERF_SEL_flush_16plane', - 134: 'DB_PERF_SEL_flush_expanded_z', - 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 137: 'DB_PERF_SEL_dk_tile_sends', - 138: 'DB_PERF_SEL_dk_tile_busy', - 139: 'DB_PERF_SEL_dk_tile_quad_starves', - 140: 'DB_PERF_SEL_dk_tile_stalls', - 141: 'DB_PERF_SEL_dk_squad_sends', - 142: 'DB_PERF_SEL_dk_squad_busy', - 143: 'DB_PERF_SEL_dk_squad_stalls', - 144: 'DB_PERF_SEL_Op_Pipe_Busy', - 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 146: 'DB_PERF_SEL_qc_busy', - 147: 'DB_PERF_SEL_qc_xfc', - 148: 'DB_PERF_SEL_qc_conflicts', - 149: 'DB_PERF_SEL_qc_full_stall', - 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', - 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', - 153: 'DB_PERF_SEL_tl_busy', - 154: 'DB_PERF_SEL_tl_dtc_read_starved', - 155: 'DB_PERF_SEL_tl_z_fetch_stall', - 156: 'DB_PERF_SEL_tl_stencil_stall', - 157: 'DB_PERF_SEL_tl_z_decompress_stall', - 158: 'DB_PERF_SEL_tl_stencil_locked_stall', - 159: 'DB_PERF_SEL_tl_events', - 160: 'DB_PERF_SEL_tl_summarize_squads', - 161: 'DB_PERF_SEL_tl_flush_expand_squads', - 162: 'DB_PERF_SEL_tl_expand_squads', - 163: 'DB_PERF_SEL_tl_preZ_squads', - 164: 'DB_PERF_SEL_tl_postZ_squads', - 165: 'DB_PERF_SEL_tl_preZ_noop_squads', - 166: 'DB_PERF_SEL_tl_postZ_noop_squads', - 167: 'DB_PERF_SEL_tl_tile_ops', - 168: 'DB_PERF_SEL_tl_in_xfc', - 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 170: 'DB_PERF_SEL_tl_in_fast_z_stall', - 171: 'DB_PERF_SEL_tl_out_xfc', - 172: 'DB_PERF_SEL_tl_out_squads', - 173: 'DB_PERF_SEL_zf_plane_multicycle', - 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', - 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', - 180: 'DB_PERF_SEL_ts_tc_update_stall', - 181: 'DB_PERF_SEL_sc_kick_start', - 182: 'DB_PERF_SEL_sc_kick_end', - 183: 'DB_PERF_SEL_clock_reg_active', - 184: 'DB_PERF_SEL_clock_main_active', - 185: 'DB_PERF_SEL_clock_mem_export_active', - 186: 'DB_PERF_SEL_esr_ps_out_busy', - 187: 'DB_PERF_SEL_esr_ps_lqf_busy', - 188: 'DB_PERF_SEL_esr_ps_lqf_stall', - 189: 'DB_PERF_SEL_etr_out_send', - 190: 'DB_PERF_SEL_etr_out_busy', - 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', - 193: 'DB_PERF_SEL_etr_out_esr_stall', - 194: 'DB_PERF_SEL_esr_ps_vic_busy', - 195: 'DB_PERF_SEL_esr_ps_vic_stall', - 196: 'DB_PERF_SEL_esr_eot_fwd_busy', - 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 198: 'DB_PERF_SEL_esr_eot_fwd_forward', - 199: 'DB_PERF_SEL_esr_sqq_zi_busy', - 200: 'DB_PERF_SEL_esr_sqq_zi_stall', - 201: 'DB_PERF_SEL_postzl_sq_pt_busy', - 202: 'DB_PERF_SEL_postzl_sq_pt_stall', - 203: 'DB_PERF_SEL_postzl_se_busy', - 204: 'DB_PERF_SEL_postzl_se_stall', - 205: 'DB_PERF_SEL_postzl_partial_launch', - 206: 'DB_PERF_SEL_postzl_full_launch', - 207: 'DB_PERF_SEL_postzl_partial_waiting', - 208: 'DB_PERF_SEL_postzl_tile_mem_stall', - 209: 'DB_PERF_SEL_postzl_tile_init_stall', - 210: 'DB_PERF_SEL_prezl_tile_mem_stall', - 211: 'DB_PERF_SEL_prezl_tile_init_stall', - 212: 'DB_PERF_SEL_dtt_sm_clash_stall', - 213: 'DB_PERF_SEL_dtt_sm_slot_stall', - 214: 'DB_PERF_SEL_dtt_sm_miss_stall', - 215: 'DB_PERF_SEL_mi_rdreq_busy', - 216: 'DB_PERF_SEL_mi_rdreq_stall', - 217: 'DB_PERF_SEL_mi_wrreq_busy', - 218: 'DB_PERF_SEL_mi_wrreq_stall', - 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 220: 'DB_PERF_SEL_dkg_tile_rate_tile', - 221: 'DB_PERF_SEL_prezl_src_in_sends', - 222: 'DB_PERF_SEL_prezl_src_in_stall', - 223: 'DB_PERF_SEL_prezl_src_in_squads', - 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', - 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 227: 'DB_PERF_SEL_prezl_src_out_stall', - 228: 'DB_PERF_SEL_postzl_src_in_sends', - 229: 'DB_PERF_SEL_postzl_src_in_stall', - 230: 'DB_PERF_SEL_postzl_src_in_squads', - 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', - 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 234: 'DB_PERF_SEL_postzl_src_out_stall', - 235: 'DB_PERF_SEL_esr_ps_src_in_sends', - 236: 'DB_PERF_SEL_esr_ps_src_in_stall', - 237: 'DB_PERF_SEL_esr_ps_src_in_squads', - 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 242: 'DB_PERF_SEL_esr_ps_src_out_stall', - 243: 'DB_PERF_SEL_depth_bounds_tile_culled', - 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 246: 'DB_PERF_SEL_flush_compressed', - 247: 'DB_PERF_SEL_flush_plane_le4', - 248: 'DB_PERF_SEL_tiles_z_fully_summarized', - 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', - 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', - 256: 'DB_PERF_SEL_di_dt_stall', - 257: 'Spare_257', - 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', - 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', - 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', - 261: 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 262: 'DB_PERF_SEL_DB_CB_lquad_double_format', - 263: 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 264: 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', - 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', - 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 269: 'DB_PERF_SEL_DB_CB_rdret_ack', - 270: 'DB_PERF_SEL_DB_CB_rdret_nack', - 271: 'DB_PERF_SEL_DB_CB_wrret_ack', - 272: 'DB_PERF_SEL_DB_CB_wrret_nack', - 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 277: 'DB_PERF_SEL_unmapped_z_tile_culled', - 278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 287: 'DB_PERF_SEL_DB_CB_context_dones', - 288: 'DB_PERF_SEL_DB_CB_eop_dones', - 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 292: 'DB_PERF_SEL_SC_DB_tile_backface', - 293: 'DB_PERF_SEL_SC_DB_quad_quads', - 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', - 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', - 300: 'DB_PERF_SEL_SX_DB_quad_double_format', - 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', - 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', - 303: 'DB_PERF_SEL_quad_rd_sends_unc', - 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', - 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', - 311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', - 312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', - 313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', - 314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', - 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', - 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 329: 'DB_PERF_SEL_esr_vic_sqq_busy', - 330: 'DB_PERF_SEL_esr_vic_sqq_stall', - 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 344: 'DB_PERF_SEL_ts_events_pws_enable', - 345: 'DB_PERF_SEL_ps_events_pws_enable', - 346: 'DB_PERF_SEL_cs_events_pws_enable', - 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', -} -DB_PERF_SEL_SC_DB_tile_sends = 0 -DB_PERF_SEL_SC_DB_tile_busy = 1 -DB_PERF_SEL_SC_DB_tile_stalls = 2 -DB_PERF_SEL_SC_DB_tile_events = 3 -DB_PERF_SEL_SC_DB_tile_tiles = 4 -DB_PERF_SEL_SC_DB_tile_covered = 5 -DB_PERF_SEL_hiz_tc_read_starved = 6 -DB_PERF_SEL_hiz_tc_write_stall = 7 -DB_PERF_SEL_hiz_tile_culled = 8 -DB_PERF_SEL_his_tile_culled = 9 -DB_PERF_SEL_DB_SC_tile_sends = 10 -DB_PERF_SEL_DB_SC_tile_busy = 11 -DB_PERF_SEL_DB_SC_tile_stalls = 12 -DB_PERF_SEL_DB_SC_tile_df_stalls = 13 -DB_PERF_SEL_DB_SC_tile_tiles = 14 -DB_PERF_SEL_DB_SC_tile_culled = 15 -DB_PERF_SEL_DB_SC_tile_hier_kill = 16 -DB_PERF_SEL_DB_SC_tile_fast_ops = 17 -DB_PERF_SEL_DB_SC_tile_no_ops = 18 -DB_PERF_SEL_DB_SC_tile_tile_rate = 19 -DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 -DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 -DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 -DB_PERF_SEL_SC_DB_quad_sends = 23 -DB_PERF_SEL_SC_DB_quad_busy = 24 -DB_PERF_SEL_SC_DB_quad_squads = 25 -DB_PERF_SEL_SC_DB_quad_tiles = 26 -DB_PERF_SEL_SC_DB_quad_pixels = 27 -DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 -DB_PERF_SEL_DB_SC_quad_sends = 29 -DB_PERF_SEL_DB_SC_quad_busy = 30 -DB_PERF_SEL_DB_SC_quad_stalls = 31 -DB_PERF_SEL_DB_SC_quad_tiles = 32 -DB_PERF_SEL_DB_SC_quad_lit_quad = 33 -DB_PERF_SEL_DB_CB_tile_sends = 34 -DB_PERF_SEL_DB_CB_tile_busy = 35 -DB_PERF_SEL_DB_CB_tile_stalls = 36 -DB_PERF_SEL_SX_DB_quad_sends = 37 -DB_PERF_SEL_SX_DB_quad_busy = 38 -DB_PERF_SEL_SX_DB_quad_stalls = 39 -DB_PERF_SEL_SX_DB_quad_quads = 40 -DB_PERF_SEL_SX_DB_quad_pixels = 41 -DB_PERF_SEL_SX_DB_quad_exports = 42 -DB_PERF_SEL_SH_quads_outstanding_sum = 43 -DB_PERF_SEL_DB_CB_lquad_sends = 44 -DB_PERF_SEL_DB_CB_lquad_busy = 45 -DB_PERF_SEL_DB_CB_lquad_stalls = 46 -DB_PERF_SEL_DB_CB_lquad_quads = 47 -DB_PERF_SEL_tile_rd_sends = 48 -DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 -DB_PERF_SEL_quad_rd_sends = 50 -DB_PERF_SEL_quad_rd_busy = 51 -DB_PERF_SEL_quad_rd_mi_stall = 52 -DB_PERF_SEL_quad_rd_rw_collision = 53 -DB_PERF_SEL_quad_rd_tag_stall = 54 -DB_PERF_SEL_quad_rd_32byte_reqs = 55 -DB_PERF_SEL_quad_rd_panic = 56 -DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 -DB_PERF_SEL_quad_rdret_sends = 58 -DB_PERF_SEL_quad_rdret_busy = 59 -DB_PERF_SEL_tile_wr_sends = 60 -DB_PERF_SEL_tile_wr_acks = 61 -DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 -DB_PERF_SEL_quad_wr_sends = 63 -DB_PERF_SEL_quad_wr_busy = 64 -DB_PERF_SEL_quad_wr_mi_stall = 65 -DB_PERF_SEL_quad_wr_coherency_stall = 66 -DB_PERF_SEL_quad_wr_acks = 67 -DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 -DB_PERF_SEL_Tile_Cache_misses = 69 -DB_PERF_SEL_Tile_Cache_hits = 70 -DB_PERF_SEL_Tile_Cache_flushes = 71 -DB_PERF_SEL_Tile_Cache_surface_stall = 72 -DB_PERF_SEL_Tile_Cache_starves = 73 -DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 -DB_PERF_SEL_tcp_dispatcher_reads = 75 -DB_PERF_SEL_tcp_prefetcher_reads = 76 -DB_PERF_SEL_tcp_preloader_reads = 77 -DB_PERF_SEL_tcp_dispatcher_flushes = 78 -DB_PERF_SEL_tcp_prefetcher_flushes = 79 -DB_PERF_SEL_tcp_preloader_flushes = 80 -DB_PERF_SEL_Depth_Tile_Cache_sends = 81 -DB_PERF_SEL_Depth_Tile_Cache_busy = 82 -DB_PERF_SEL_Depth_Tile_Cache_starves = 83 -DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 -DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 -DB_PERF_SEL_Depth_Tile_Cache_misses = 86 -DB_PERF_SEL_Depth_Tile_Cache_hits = 87 -DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 -DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 -DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 -DB_PERF_SEL_Depth_Tile_Cache_event = 91 -DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 -DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 -DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 -DB_PERF_SEL_Stencil_Cache_misses = 95 -DB_PERF_SEL_Stencil_Cache_hits = 96 -DB_PERF_SEL_Stencil_Cache_flushes = 97 -DB_PERF_SEL_Stencil_Cache_starves = 98 -DB_PERF_SEL_Stencil_Cache_frees = 99 -DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 -DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 -DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 -DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 -DB_PERF_SEL_Z_Cache_pmask_misses = 104 -DB_PERF_SEL_Z_Cache_pmask_hits = 105 -DB_PERF_SEL_Z_Cache_pmask_flushes = 106 -DB_PERF_SEL_Z_Cache_pmask_starves = 107 -DB_PERF_SEL_Z_Cache_frees = 108 -DB_PERF_SEL_Plane_Cache_misses = 109 -DB_PERF_SEL_Plane_Cache_hits = 110 -DB_PERF_SEL_Plane_Cache_flushes = 111 -DB_PERF_SEL_Plane_Cache_starves = 112 -DB_PERF_SEL_Plane_Cache_frees = 113 -DB_PERF_SEL_flush_expanded_stencil = 114 -DB_PERF_SEL_flush_compressed_stencil = 115 -DB_PERF_SEL_flush_single_stencil = 116 -DB_PERF_SEL_planes_flushed = 117 -DB_PERF_SEL_flush_1plane = 118 -DB_PERF_SEL_flush_2plane = 119 -DB_PERF_SEL_flush_3plane = 120 -DB_PERF_SEL_flush_4plane = 121 -DB_PERF_SEL_flush_5plane = 122 -DB_PERF_SEL_flush_6plane = 123 -DB_PERF_SEL_flush_7plane = 124 -DB_PERF_SEL_flush_8plane = 125 -DB_PERF_SEL_flush_9plane = 126 -DB_PERF_SEL_flush_10plane = 127 -DB_PERF_SEL_flush_11plane = 128 -DB_PERF_SEL_flush_12plane = 129 -DB_PERF_SEL_flush_13plane = 130 -DB_PERF_SEL_flush_14plane = 131 -DB_PERF_SEL_flush_15plane = 132 -DB_PERF_SEL_flush_16plane = 133 -DB_PERF_SEL_flush_expanded_z = 134 -DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 -DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 -DB_PERF_SEL_dk_tile_sends = 137 -DB_PERF_SEL_dk_tile_busy = 138 -DB_PERF_SEL_dk_tile_quad_starves = 139 -DB_PERF_SEL_dk_tile_stalls = 140 -DB_PERF_SEL_dk_squad_sends = 141 -DB_PERF_SEL_dk_squad_busy = 142 -DB_PERF_SEL_dk_squad_stalls = 143 -DB_PERF_SEL_Op_Pipe_Busy = 144 -DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 -DB_PERF_SEL_qc_busy = 146 -DB_PERF_SEL_qc_xfc = 147 -DB_PERF_SEL_qc_conflicts = 148 -DB_PERF_SEL_qc_full_stall = 149 -DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 -DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 -DB_PERF_SEL_tsc_insert_summarize_stall = 152 -DB_PERF_SEL_tl_busy = 153 -DB_PERF_SEL_tl_dtc_read_starved = 154 -DB_PERF_SEL_tl_z_fetch_stall = 155 -DB_PERF_SEL_tl_stencil_stall = 156 -DB_PERF_SEL_tl_z_decompress_stall = 157 -DB_PERF_SEL_tl_stencil_locked_stall = 158 -DB_PERF_SEL_tl_events = 159 -DB_PERF_SEL_tl_summarize_squads = 160 -DB_PERF_SEL_tl_flush_expand_squads = 161 -DB_PERF_SEL_tl_expand_squads = 162 -DB_PERF_SEL_tl_preZ_squads = 163 -DB_PERF_SEL_tl_postZ_squads = 164 -DB_PERF_SEL_tl_preZ_noop_squads = 165 -DB_PERF_SEL_tl_postZ_noop_squads = 166 -DB_PERF_SEL_tl_tile_ops = 167 -DB_PERF_SEL_tl_in_xfc = 168 -DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 -DB_PERF_SEL_tl_in_fast_z_stall = 170 -DB_PERF_SEL_tl_out_xfc = 171 -DB_PERF_SEL_tl_out_squads = 172 -DB_PERF_SEL_zf_plane_multicycle = 173 -DB_PERF_SEL_PostZ_Samples_passing_Z = 174 -DB_PERF_SEL_PostZ_Samples_failing_Z = 175 -DB_PERF_SEL_PostZ_Samples_failing_S = 176 -DB_PERF_SEL_PreZ_Samples_passing_Z = 177 -DB_PERF_SEL_PreZ_Samples_failing_Z = 178 -DB_PERF_SEL_PreZ_Samples_failing_S = 179 -DB_PERF_SEL_ts_tc_update_stall = 180 -DB_PERF_SEL_sc_kick_start = 181 -DB_PERF_SEL_sc_kick_end = 182 -DB_PERF_SEL_clock_reg_active = 183 -DB_PERF_SEL_clock_main_active = 184 -DB_PERF_SEL_clock_mem_export_active = 185 -DB_PERF_SEL_esr_ps_out_busy = 186 -DB_PERF_SEL_esr_ps_lqf_busy = 187 -DB_PERF_SEL_esr_ps_lqf_stall = 188 -DB_PERF_SEL_etr_out_send = 189 -DB_PERF_SEL_etr_out_busy = 190 -DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 -DB_PERF_SEL_etr_out_cb_tile_stall = 192 -DB_PERF_SEL_etr_out_esr_stall = 193 -DB_PERF_SEL_esr_ps_vic_busy = 194 -DB_PERF_SEL_esr_ps_vic_stall = 195 -DB_PERF_SEL_esr_eot_fwd_busy = 196 -DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 -DB_PERF_SEL_esr_eot_fwd_forward = 198 -DB_PERF_SEL_esr_sqq_zi_busy = 199 -DB_PERF_SEL_esr_sqq_zi_stall = 200 -DB_PERF_SEL_postzl_sq_pt_busy = 201 -DB_PERF_SEL_postzl_sq_pt_stall = 202 -DB_PERF_SEL_postzl_se_busy = 203 -DB_PERF_SEL_postzl_se_stall = 204 -DB_PERF_SEL_postzl_partial_launch = 205 -DB_PERF_SEL_postzl_full_launch = 206 -DB_PERF_SEL_postzl_partial_waiting = 207 -DB_PERF_SEL_postzl_tile_mem_stall = 208 -DB_PERF_SEL_postzl_tile_init_stall = 209 -DB_PERF_SEL_prezl_tile_mem_stall = 210 -DB_PERF_SEL_prezl_tile_init_stall = 211 -DB_PERF_SEL_dtt_sm_clash_stall = 212 -DB_PERF_SEL_dtt_sm_slot_stall = 213 -DB_PERF_SEL_dtt_sm_miss_stall = 214 -DB_PERF_SEL_mi_rdreq_busy = 215 -DB_PERF_SEL_mi_rdreq_stall = 216 -DB_PERF_SEL_mi_wrreq_busy = 217 -DB_PERF_SEL_mi_wrreq_stall = 218 -DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 -DB_PERF_SEL_dkg_tile_rate_tile = 220 -DB_PERF_SEL_prezl_src_in_sends = 221 -DB_PERF_SEL_prezl_src_in_stall = 222 -DB_PERF_SEL_prezl_src_in_squads = 223 -DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 -DB_PERF_SEL_prezl_src_in_tile_rate = 225 -DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 -DB_PERF_SEL_prezl_src_out_stall = 227 -DB_PERF_SEL_postzl_src_in_sends = 228 -DB_PERF_SEL_postzl_src_in_stall = 229 -DB_PERF_SEL_postzl_src_in_squads = 230 -DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 -DB_PERF_SEL_postzl_src_in_tile_rate = 232 -DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 -DB_PERF_SEL_postzl_src_out_stall = 234 -DB_PERF_SEL_esr_ps_src_in_sends = 235 -DB_PERF_SEL_esr_ps_src_in_stall = 236 -DB_PERF_SEL_esr_ps_src_in_squads = 237 -DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 -DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 -DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 -DB_PERF_SEL_esr_ps_src_out_stall = 242 -DB_PERF_SEL_depth_bounds_tile_culled = 243 -DB_PERF_SEL_PreZ_Samples_failing_DB = 244 -DB_PERF_SEL_PostZ_Samples_failing_DB = 245 -DB_PERF_SEL_flush_compressed = 246 -DB_PERF_SEL_flush_plane_le4 = 247 -DB_PERF_SEL_tiles_z_fully_summarized = 248 -DB_PERF_SEL_tiles_stencil_fully_summarized = 249 -DB_PERF_SEL_tiles_z_clear_on_expclear = 250 -DB_PERF_SEL_tiles_s_clear_on_expclear = 251 -DB_PERF_SEL_tiles_decomp_on_expclear = 252 -DB_PERF_SEL_tiles_compressed_to_decompressed = 253 -DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 -DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 -DB_PERF_SEL_di_dt_stall = 256 -Spare_257 = 257 -DB_PERF_SEL_DB_SC_s_tile_rate = 258 -DB_PERF_SEL_DB_SC_c_tile_rate = 259 -DB_PERF_SEL_DB_SC_z_tile_rate = 260 -DB_PERF_SEL_DB_CB_lquad_export_quads = 261 -DB_PERF_SEL_DB_CB_lquad_double_format = 262 -DB_PERF_SEL_DB_CB_lquad_fast_format = 263 -DB_PERF_SEL_DB_CB_lquad_slow_format = 264 -DB_PERF_SEL_CB_DB_rdreq_sends = 265 -DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 -DB_PERF_SEL_CB_DB_wrreq_sends = 267 -DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 -DB_PERF_SEL_DB_CB_rdret_ack = 269 -DB_PERF_SEL_DB_CB_rdret_nack = 270 -DB_PERF_SEL_DB_CB_wrret_ack = 271 -DB_PERF_SEL_DB_CB_wrret_nack = 272 -DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 -DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 -DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 -DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 -DB_PERF_SEL_unmapped_z_tile_culled = 277 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 -DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 -DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280 -DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281 -DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284 -DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285 -DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286 -DB_PERF_SEL_DB_CB_context_dones = 287 -DB_PERF_SEL_DB_CB_eop_dones = 288 -DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 -DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 -DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 -DB_PERF_SEL_SC_DB_tile_backface = 292 -DB_PERF_SEL_SC_DB_quad_quads = 293 -DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 -DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 -DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 -DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 -DB_PERF_SEL_DB_SC_quad_double_quad = 298 -DB_PERF_SEL_SX_DB_quad_export_quads = 299 -DB_PERF_SEL_SX_DB_quad_double_format = 300 -DB_PERF_SEL_SX_DB_quad_fast_format = 301 -DB_PERF_SEL_SX_DB_quad_slow_format = 302 -DB_PERF_SEL_quad_rd_sends_unc = 303 -DB_PERF_SEL_quad_rd_mi_stall_unc = 304 -DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 -DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 -DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 -DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 -DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 -DB_PERF_SEL_noz_waiting_for_postz_done = 310 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313 -DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314 -DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 -DB_PERF_SEL_RMI_rd_z_32byte_req = 316 -DB_PERF_SEL_RMI_rd_s_32byte_req = 317 -DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 -DB_PERF_SEL_RMI_wr_z_32byte_req = 319 -DB_PERF_SEL_RMI_wr_s_32byte_req = 320 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 -DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 -DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 -DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 -DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 -DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 -DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 -DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 -DB_PERF_SEL_esr_vic_sqq_busy = 329 -DB_PERF_SEL_esr_vic_sqq_stall = 330 -DB_PERF_SEL_esr_psi_vic_tile_rate = 331 -DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 -DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 -DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 -DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 -DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 -DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 -DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 -DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 -DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 -DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 -DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 -DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 -DB_PERF_SEL_ts_events_pws_enable = 344 -DB_PERF_SEL_ps_events_pws_enable = 345 -DB_PERF_SEL_cs_events_pws_enable = 346 -DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 -DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 -PerfCounter_Vals = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeCounterId' -PixelPipeCounterId__enumvalues = { - 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', - 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', - 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', - 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', -} -PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 -PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 -PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 -PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 -PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 -PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 -PixelPipeCounterId = ctypes.c_uint32 # enum - -# values for enumeration 'PixelPipeStride' -PixelPipeStride__enumvalues = { - 0: 'PIXEL_PIPE_STRIDE_32_BITS', - 1: 'PIXEL_PIPE_STRIDE_64_BITS', - 2: 'PIXEL_PIPE_STRIDE_128_BITS', - 3: 'PIXEL_PIPE_STRIDE_256_BITS', -} -PIXEL_PIPE_STRIDE_32_BITS = 0 -PIXEL_PIPE_STRIDE_64_BITS = 1 -PIXEL_PIPE_STRIDE_128_BITS = 2 -PIXEL_PIPE_STRIDE_256_BITS = 3 -PixelPipeStride = ctypes.c_uint32 # enum - -# values for enumeration 'RingCounterControl' -RingCounterControl__enumvalues = { - 0: 'COUNTER_RING_SPLIT', - 1: 'COUNTER_RING_0', - 2: 'COUNTER_RING_1', -} -COUNTER_RING_SPLIT = 0 -COUNTER_RING_0 = 1 -COUNTER_RING_1 = 2 -RingCounterControl = ctypes.c_uint32 # enum - -# values for enumeration 'StencilOp' -StencilOp__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_ONES', - 3: 'STENCIL_REPLACE_TEST', - 4: 'STENCIL_REPLACE_OP', - 5: 'STENCIL_ADD_CLAMP', - 6: 'STENCIL_SUB_CLAMP', - 7: 'STENCIL_INVERT', - 8: 'STENCIL_ADD_WRAP', - 9: 'STENCIL_SUB_WRAP', - 10: 'STENCIL_AND', - 11: 'STENCIL_OR', - 12: 'STENCIL_XOR', - 13: 'STENCIL_NAND', - 14: 'STENCIL_NOR', - 15: 'STENCIL_XNOR', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_ONES = 2 -STENCIL_REPLACE_TEST = 3 -STENCIL_REPLACE_OP = 4 -STENCIL_ADD_CLAMP = 5 -STENCIL_SUB_CLAMP = 6 -STENCIL_INVERT = 7 -STENCIL_ADD_WRAP = 8 -STENCIL_SUB_WRAP = 9 -STENCIL_AND = 10 -STENCIL_OR = 11 -STENCIL_XOR = 12 -STENCIL_NAND = 13 -STENCIL_NOR = 14 -STENCIL_XNOR = 15 -StencilOp = ctypes.c_uint32 # enum - -# values for enumeration 'ZLimitSumm' -ZLimitSumm__enumvalues = { - 0: 'FORCE_SUMM_OFF', - 1: 'FORCE_SUMM_MINZ', - 2: 'FORCE_SUMM_MAXZ', - 3: 'FORCE_SUMM_BOTH', -} -FORCE_SUMM_OFF = 0 -FORCE_SUMM_MINZ = 1 -FORCE_SUMM_MAXZ = 2 -FORCE_SUMM_BOTH = 3 -ZLimitSumm = ctypes.c_uint32 # enum - -# values for enumeration 'ZModeForce' -ZModeForce__enumvalues = { - 0: 'NO_FORCE', - 1: 'FORCE_EARLY_Z', - 2: 'FORCE_LATE_Z', - 3: 'FORCE_RE_Z', -} -NO_FORCE = 0 -FORCE_EARLY_Z = 1 -FORCE_LATE_Z = 2 -FORCE_RE_Z = 3 -ZModeForce = ctypes.c_uint32 # enum - -# values for enumeration 'ZOrder' -ZOrder__enumvalues = { - 0: 'LATE_Z', - 1: 'EARLY_Z_THEN_LATE_Z', - 2: 'RE_Z', - 3: 'EARLY_Z_THEN_RE_Z', -} -LATE_Z = 0 -EARLY_Z_THEN_LATE_Z = 1 -RE_Z = 2 -EARLY_Z_THEN_RE_Z = 3 -ZOrder = ctypes.c_uint32 # enum - -# values for enumeration 'ZSamplePosition' -ZSamplePosition__enumvalues = { - 0: 'Z_SAMPLE_CENTER', - 1: 'Z_SAMPLE_CENTROID', -} -Z_SAMPLE_CENTER = 0 -Z_SAMPLE_CENTROID = 1 -ZSamplePosition = ctypes.c_uint32 # enum - -# values for enumeration 'ZpassControl' -ZpassControl__enumvalues = { - 0: 'ZPASS_DISABLE', - 1: 'ZPASS_SAMPLES', - 2: 'ZPASS_PIXELS', -} -ZPASS_DISABLE = 0 -ZPASS_SAMPLES = 1 -ZPASS_PIXELS = 2 -ZpassControl = ctypes.c_uint32 # enum - -# values for enumeration 'SU_PERFCNT_SEL' -SU_PERFCNT_SEL__enumvalues = { - 0: 'PERF_PAPC_PASX_REQ', - 1: 'PERF_PAPC_PASX_DISABLE_PIPE', - 2: 'PERF_PAPC_PASX_FIRST_VECTOR', - 3: 'PERF_PAPC_PASX_SECOND_VECTOR', - 4: 'PERF_PAPC_PASX_FIRST_DEAD', - 5: 'PERF_PAPC_PASX_SECOND_DEAD', - 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 8: 'PERF_PAPC_PA_INPUT_PRIM', - 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', - 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 14: 'PERF_PAPC_CLPR_CULL_PRIM', - 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', - 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', - 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', - 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', - 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', - 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 39: 'PERF_PAPC_CLSM_NULL_PRIM', - 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', - 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', - 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', - 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', - 49: 'PERF_PAPC_SU_INPUT_PRIM', - 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', - 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 61: 'PERF_PAPC_SU_OUTPUT_PRIM', - 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', - 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', - 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 77: 'PERF_PAPC_PASX_REQ_IDLE', - 78: 'PERF_PAPC_PASX_REQ_BUSY', - 79: 'PERF_PAPC_PASX_REQ_STALLED', - 80: 'PERF_PAPC_PASX_REC_IDLE', - 81: 'PERF_PAPC_PASX_REC_BUSY', - 82: 'PERF_PAPC_PASX_REC_STARVED_SX', - 83: 'PERF_PAPC_PASX_REC_STALLED', - 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 86: 'PERF_PAPC_CCGSM_IDLE', - 87: 'PERF_PAPC_CCGSM_BUSY', - 88: 'PERF_PAPC_CCGSM_STALLED', - 89: 'PERF_PAPC_CLPRIM_IDLE', - 90: 'PERF_PAPC_CLPRIM_BUSY', - 91: 'PERF_PAPC_CLPRIM_STALLED', - 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 93: 'PERF_PAPC_CLIPSM_IDLE', - 94: 'PERF_PAPC_CLIPSM_BUSY', - 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', - 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 100: 'PERF_PAPC_CLIPGA_IDLE', - 101: 'PERF_PAPC_CLIPGA_BUSY', - 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 103: 'PERF_PAPC_CLIPGA_STALLED', - 104: 'PERF_PAPC_CLIP_IDLE', - 105: 'PERF_PAPC_CLIP_BUSY', - 106: 'PERF_PAPC_SU_IDLE', - 107: 'PERF_PAPC_SU_BUSY', - 108: 'PERF_PAPC_SU_STARVED_CLIP', - 109: 'PERF_PAPC_SU_STALLED_SC', - 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', - 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', - 112: 'PERF_PAPC_PA_REG_SCLK_VLD', - 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 114: 'PERF_PAPC_PASX_SE0_REQ', - 115: 'PERF_PAPC_PASX_SE1_REQ', - 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', - 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', - 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 131: 'PERF_PAPC_SU_SE0_STALLED_SC', - 132: 'PERF_PAPC_SU_SE1_STALLED_SC', - 133: 'PERF_PAPC_SU_SE01_STALLED_SC', - 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 135: 'PERF_PAPC_SU_CULLED_PRIM', - 136: 'PERF_PAPC_SU_OUTPUT_EOPG', - 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 151: 'PERF_PAPC_SU_SE2_STALLED_SC', - 152: 'PERF_PAPC_SU_SE3_STALLED_SC', - 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', - 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', - 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', - 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', - 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', - 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', - 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', - 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 179: 'PERF_PA_VERTEX_FIFO_FULL', - 180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', - 182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', - 185: 'PERF_PA_PIPE0_SWITCHED_GEN', - 186: 'PERF_PA_PIPE1_SWITCHED_GEN', - 188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', - 193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', - 196: 'PERF_ENGG_CSB_NULL_SUBGROUP', - 197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 198: 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', - 200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', - 202: 'PERF_ENGG_CSB_DELAY_BIN00', - 203: 'PERF_ENGG_CSB_DELAY_BIN01', - 204: 'PERF_ENGG_CSB_DELAY_BIN02', - 205: 'PERF_ENGG_CSB_DELAY_BIN03', - 206: 'PERF_ENGG_CSB_DELAY_BIN04', - 207: 'PERF_ENGG_CSB_DELAY_BIN05', - 208: 'PERF_ENGG_CSB_DELAY_BIN06', - 209: 'PERF_ENGG_CSB_DELAY_BIN07', - 210: 'PERF_ENGG_CSB_DELAY_BIN08', - 211: 'PERF_ENGG_CSB_DELAY_BIN09', - 212: 'PERF_ENGG_CSB_DELAY_BIN10', - 213: 'PERF_ENGG_CSB_DELAY_BIN11', - 214: 'PERF_ENGG_CSB_DELAY_BIN12', - 215: 'PERF_ENGG_CSB_DELAY_BIN13', - 216: 'PERF_ENGG_CSB_DELAY_BIN14', - 217: 'PERF_ENGG_CSB_DELAY_BIN15', - 218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00', - 219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01', - 220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02', - 221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03', - 222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04', - 223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05', - 224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06', - 225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07', - 226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08', - 227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09', - 228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10', - 229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', - 231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', - 232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', - 233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', - 234: 'PERF_ENGG_INDEX_REQ_STARVED', - 235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', - 259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', - 260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', - 261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', - 262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', - 263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 269: 'PERF_ENGG_POS_REQ_STARVED', - 270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 271: 'PERF_ENGG_BUSY', - 272: 'PERF_CLIPSM_CULL_PRIMS_CNT', - 273: 'PERF_PH_SEND_1_SC', - 274: 'PERF_PH_SEND_2_SC', - 275: 'PERF_PH_SEND_3_SC', - 276: 'PERF_PH_SEND_4_SC', - 277: 'PERF_OUTPUT_PRIM_1_SC', - 278: 'PERF_OUTPUT_PRIM_2_SC', - 279: 'PERF_OUTPUT_PRIM_3_SC', - 280: 'PERF_OUTPUT_PRIM_4_SC', -} -PERF_PAPC_PASX_REQ = 0 -PERF_PAPC_PASX_DISABLE_PIPE = 1 -PERF_PAPC_PASX_FIRST_VECTOR = 2 -PERF_PAPC_PASX_SECOND_VECTOR = 3 -PERF_PAPC_PASX_FIRST_DEAD = 4 -PERF_PAPC_PASX_SECOND_DEAD = 5 -PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 -PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 -PERF_PAPC_PA_INPUT_PRIM = 8 -PERF_PAPC_PA_INPUT_NULL_PRIM = 9 -PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 -PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 -PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 -PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 -PERF_PAPC_CLPR_CULL_PRIM = 14 -PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 -PERF_PAPC_CLPR_VV_CULL_PRIM = 16 -PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 -PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 -PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 -PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 -PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 -PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 -PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 -PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 -PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 -PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 -PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 -PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 -PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 -PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 -PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 -PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 -PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 -PERF_PAPC_CLSM_NULL_PRIM = 39 -PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 -PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 -PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 -PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 -PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 -PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 -PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 -PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 -PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 -PERF_PAPC_SU_INPUT_PRIM = 49 -PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 -PERF_PAPC_SU_INPUT_NULL_PRIM = 51 -PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 -PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 -PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 -PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 -PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 -PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 -PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 -PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 -PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 -PERF_PAPC_SU_OUTPUT_PRIM = 61 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 -PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 -PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 -PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 -PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 -PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 -PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 -PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 -PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 -PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 -PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 -PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 -PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 -PERF_PAPC_PASX_REQ_IDLE = 77 -PERF_PAPC_PASX_REQ_BUSY = 78 -PERF_PAPC_PASX_REQ_STALLED = 79 -PERF_PAPC_PASX_REC_IDLE = 80 -PERF_PAPC_PASX_REC_BUSY = 81 -PERF_PAPC_PASX_REC_STARVED_SX = 82 -PERF_PAPC_PASX_REC_STALLED = 83 -PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 -PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 -PERF_PAPC_CCGSM_IDLE = 86 -PERF_PAPC_CCGSM_BUSY = 87 -PERF_PAPC_CCGSM_STALLED = 88 -PERF_PAPC_CLPRIM_IDLE = 89 -PERF_PAPC_CLPRIM_BUSY = 90 -PERF_PAPC_CLPRIM_STALLED = 91 -PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 -PERF_PAPC_CLIPSM_IDLE = 93 -PERF_PAPC_CLIPSM_BUSY = 94 -PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 -PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 -PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 -PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 -PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 -PERF_PAPC_CLIPGA_IDLE = 100 -PERF_PAPC_CLIPGA_BUSY = 101 -PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 -PERF_PAPC_CLIPGA_STALLED = 103 -PERF_PAPC_CLIP_IDLE = 104 -PERF_PAPC_CLIP_BUSY = 105 -PERF_PAPC_SU_IDLE = 106 -PERF_PAPC_SU_BUSY = 107 -PERF_PAPC_SU_STARVED_CLIP = 108 -PERF_PAPC_SU_STALLED_SC = 109 -PERF_PAPC_CL_DYN_SCLK_VLD = 110 -PERF_PAPC_SU_DYN_SCLK_VLD = 111 -PERF_PAPC_PA_REG_SCLK_VLD = 112 -PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 -PERF_PAPC_PASX_SE0_REQ = 114 -PERF_PAPC_PASX_SE1_REQ = 115 -PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 -PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 -PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 -PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 -PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 -PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 -PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 -PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 -PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 -PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 -PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 -PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 -PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 -PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 -PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 -PERF_PAPC_SU_SE0_STALLED_SC = 131 -PERF_PAPC_SU_SE1_STALLED_SC = 132 -PERF_PAPC_SU_SE01_STALLED_SC = 133 -PERF_PAPC_CLSM_CLIPPING_PRIM = 134 -PERF_PAPC_SU_CULLED_PRIM = 135 -PERF_PAPC_SU_OUTPUT_EOPG = 136 -PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 -PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 -PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 -PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 -PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 -PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 -PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 -PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 -PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 -PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 -PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 -PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 -PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 -PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 -PERF_PAPC_SU_SE2_STALLED_SC = 151 -PERF_PAPC_SU_SE3_STALLED_SC = 152 -PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 -PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 -PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 -PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 -PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 -PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 -PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 -PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 -PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 -PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 -PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 -PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 -PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 -PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 -PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 -PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 -PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170 -PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171 -PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172 -PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173 -PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174 -PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175 -PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176 -PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177 -PERF_PA_VERTEX_FIFO_FULL = 179 -PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180 -PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182 -PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183 -PERF_PA_PIPE0_SWITCHED_GEN = 185 -PERF_PA_PIPE1_SWITCHED_GEN = 186 -PERF_ENGG_CSB_MACHINE_IS_STARVED = 188 -PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189 -PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190 -PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191 -PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192 -PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193 -PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194 -PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195 -PERF_ENGG_CSB_NULL_SUBGROUP = 196 -PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197 -PERF_ENGG_CSB_GE_MEMORY_FULL = 198 -PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199 -PERF_ENGG_CSB_SPI_MEMORY_FULL = 200 -PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201 -PERF_ENGG_CSB_DELAY_BIN00 = 202 -PERF_ENGG_CSB_DELAY_BIN01 = 203 -PERF_ENGG_CSB_DELAY_BIN02 = 204 -PERF_ENGG_CSB_DELAY_BIN03 = 205 -PERF_ENGG_CSB_DELAY_BIN04 = 206 -PERF_ENGG_CSB_DELAY_BIN05 = 207 -PERF_ENGG_CSB_DELAY_BIN06 = 208 -PERF_ENGG_CSB_DELAY_BIN07 = 209 -PERF_ENGG_CSB_DELAY_BIN08 = 210 -PERF_ENGG_CSB_DELAY_BIN09 = 211 -PERF_ENGG_CSB_DELAY_BIN10 = 212 -PERF_ENGG_CSB_DELAY_BIN11 = 213 -PERF_ENGG_CSB_DELAY_BIN12 = 214 -PERF_ENGG_CSB_DELAY_BIN13 = 215 -PERF_ENGG_CSB_DELAY_BIN14 = 216 -PERF_ENGG_CSB_DELAY_BIN15 = 217 -PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218 -PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219 -PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220 -PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221 -PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222 -PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223 -PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224 -PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225 -PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226 -PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227 -PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228 -PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229 -PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230 -PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231 -PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232 -PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233 -PERF_ENGG_INDEX_REQ_STARVED = 234 -PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235 -PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236 -PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238 -PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239 -PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241 -PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243 -PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244 -PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245 -PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246 -PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261 -PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263 -PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265 -PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267 -PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268 -PERF_ENGG_POS_REQ_STARVED = 269 -PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270 -PERF_ENGG_BUSY = 271 -PERF_CLIPSM_CULL_PRIMS_CNT = 272 -PERF_PH_SEND_1_SC = 273 -PERF_PH_SEND_2_SC = 274 -PERF_PH_SEND_3_SC = 275 -PERF_PH_SEND_4_SC = 276 -PERF_OUTPUT_PRIM_1_SC = 277 -PERF_OUTPUT_PRIM_2_SC = 278 -PERF_OUTPUT_PRIM_3_SC = 279 -PERF_OUTPUT_PRIM_4_SC = 280 -SU_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PH_PERFCNT_SEL' -PH_PERFCNT_SEL__enumvalues = { - 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 8: 'PH_PERF_SEL_SC0_ARB_BUSY', - 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 16: 'PH_PERF_SEL_SC0_SEND', - 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', - 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', - 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', - 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE', - 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', - 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', - 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', - 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', - 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', - 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', - 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE', - 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', - 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', - 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', - 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', - 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', - 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', - 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE', - 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', - 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', - 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', - 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', - 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', - 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', - 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE', - 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', - 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', - 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', - 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', - 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', - 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', - 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE', - 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', - 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', - 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', - 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', - 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', - 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', - 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE', - 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', - 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', - 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', - 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', - 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', - 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', - 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE', - 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', - 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', - 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', - 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', - 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', - 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', - 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE', - 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', - 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', - 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', - 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 128: 'PH_PERF_SEL_SC1_ARB_BUSY', - 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 136: 'PH_PERF_SEL_SC1_SEND', - 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', - 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', - 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', - 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE', - 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', - 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', - 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', - 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', - 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', - 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', - 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE', - 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', - 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', - 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', - 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', - 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', - 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', - 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE', - 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', - 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', - 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', - 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', - 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', - 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', - 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE', - 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', - 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', - 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', - 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', - 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', - 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', - 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE', - 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', - 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', - 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', - 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', - 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', - 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', - 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE', - 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', - 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', - 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', - 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', - 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', - 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', - 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE', - 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', - 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', - 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', - 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', - 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', - 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', - 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE', - 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', - 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', - 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', - 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 248: 'PH_PERF_SEL_SC2_ARB_BUSY', - 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 256: 'PH_PERF_SEL_SC2_SEND', - 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', - 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', - 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', - 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE', - 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', - 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', - 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', - 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', - 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', - 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', - 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE', - 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', - 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', - 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', - 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', - 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', - 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', - 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE', - 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', - 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', - 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', - 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', - 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', - 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', - 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE', - 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', - 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', - 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', - 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', - 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', - 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', - 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE', - 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', - 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', - 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', - 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', - 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', - 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', - 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE', - 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', - 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', - 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', - 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', - 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', - 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', - 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE', - 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', - 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', - 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', - 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', - 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', - 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', - 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE', - 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', - 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', - 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', - 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 368: 'PH_PERF_SEL_SC3_ARB_BUSY', - 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 376: 'PH_PERF_SEL_SC3_SEND', - 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', - 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', - 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', - 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE', - 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', - 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', - 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', - 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', - 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', - 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', - 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE', - 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', - 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', - 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', - 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', - 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', - 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', - 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE', - 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', - 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', - 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', - 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', - 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', - 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', - 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE', - 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', - 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', - 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', - 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', - 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', - 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', - 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE', - 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', - 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', - 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', - 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', - 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', - 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', - 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE', - 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', - 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', - 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', - 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', - 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', - 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', - 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE', - 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', - 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', - 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', - 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', - 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', - 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', - 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE', - 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', - 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', - 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', - 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 488: 'PH_PERF_SEL_SC4_ARB_BUSY', - 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 496: 'PH_PERF_SEL_SC4_SEND', - 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', - 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', - 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', - 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE', - 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', - 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', - 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', - 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', - 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', - 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', - 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE', - 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', - 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', - 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', - 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', - 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', - 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', - 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE', - 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', - 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', - 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', - 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', - 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', - 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', - 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE', - 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', - 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', - 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', - 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', - 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', - 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', - 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE', - 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', - 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', - 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', - 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', - 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', - 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', - 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE', - 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', - 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', - 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', - 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', - 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', - 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', - 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE', - 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', - 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', - 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', - 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', - 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', - 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', - 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE', - 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', - 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', - 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', - 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 608: 'PH_PERF_SEL_SC5_ARB_BUSY', - 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 616: 'PH_PERF_SEL_SC5_SEND', - 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', - 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', - 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', - 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE', - 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', - 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', - 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', - 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', - 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', - 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', - 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE', - 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', - 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', - 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', - 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', - 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', - 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', - 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE', - 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', - 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', - 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', - 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', - 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', - 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', - 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE', - 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', - 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', - 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', - 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', - 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', - 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', - 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE', - 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', - 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', - 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', - 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', - 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', - 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', - 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE', - 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', - 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', - 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', - 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', - 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', - 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', - 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE', - 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', - 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', - 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', - 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', - 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', - 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', - 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE', - 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', - 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', - 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', - 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 728: 'PH_PERF_SEL_SC6_ARB_BUSY', - 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 736: 'PH_PERF_SEL_SC6_SEND', - 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', - 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', - 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', - 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE', - 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', - 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', - 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', - 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', - 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', - 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', - 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE', - 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', - 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', - 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', - 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', - 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', - 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', - 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE', - 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', - 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', - 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', - 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', - 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', - 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', - 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE', - 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', - 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', - 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', - 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', - 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', - 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', - 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE', - 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', - 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', - 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', - 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', - 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', - 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', - 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE', - 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', - 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', - 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', - 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', - 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', - 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', - 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE', - 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', - 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', - 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', - 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', - 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', - 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', - 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE', - 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', - 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', - 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', - 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 848: 'PH_PERF_SEL_SC7_ARB_BUSY', - 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 856: 'PH_PERF_SEL_SC7_SEND', - 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', - 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', - 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', - 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE', - 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', - 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', - 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', - 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', - 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', - 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', - 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE', - 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', - 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', - 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', - 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', - 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', - 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', - 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE', - 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', - 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', - 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', - 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', - 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', - 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', - 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE', - 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', - 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', - 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', - 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', - 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', - 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', - 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE', - 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', - 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', - 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', - 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', - 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', - 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', - 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE', - 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', - 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', - 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', - 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', - 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', - 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', - 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE', - 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', - 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', - 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', - 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', - 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', - 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', - 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE', - 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', - 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', - 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', - 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 992: 'PH_PERF_SC0_FIFO_STATUS_0', - 993: 'PH_PERF_SC0_FIFO_STATUS_1', - 994: 'PH_PERF_SC0_FIFO_STATUS_2', - 995: 'PH_PERF_SC0_FIFO_STATUS_3', - 996: 'PH_PERF_SC1_FIFO_STATUS_0', - 997: 'PH_PERF_SC1_FIFO_STATUS_1', - 998: 'PH_PERF_SC1_FIFO_STATUS_2', - 999: 'PH_PERF_SC1_FIFO_STATUS_3', - 1000: 'PH_PERF_SC2_FIFO_STATUS_0', - 1001: 'PH_PERF_SC2_FIFO_STATUS_1', - 1002: 'PH_PERF_SC2_FIFO_STATUS_2', - 1003: 'PH_PERF_SC2_FIFO_STATUS_3', - 1004: 'PH_PERF_SC3_FIFO_STATUS_0', - 1005: 'PH_PERF_SC3_FIFO_STATUS_1', - 1006: 'PH_PERF_SC3_FIFO_STATUS_2', - 1007: 'PH_PERF_SC3_FIFO_STATUS_3', - 1008: 'PH_PERF_SC4_FIFO_STATUS_0', - 1009: 'PH_PERF_SC4_FIFO_STATUS_1', - 1010: 'PH_PERF_SC4_FIFO_STATUS_2', - 1011: 'PH_PERF_SC4_FIFO_STATUS_3', - 1012: 'PH_PERF_SC5_FIFO_STATUS_0', - 1013: 'PH_PERF_SC5_FIFO_STATUS_1', - 1014: 'PH_PERF_SC5_FIFO_STATUS_2', - 1015: 'PH_PERF_SC5_FIFO_STATUS_3', - 1016: 'PH_PERF_SC6_FIFO_STATUS_0', - 1017: 'PH_PERF_SC6_FIFO_STATUS_1', - 1018: 'PH_PERF_SC6_FIFO_STATUS_2', - 1019: 'PH_PERF_SC6_FIFO_STATUS_3', - 1020: 'PH_PERF_SC7_FIFO_STATUS_0', - 1021: 'PH_PERF_SC7_FIFO_STATUS_1', - 1022: 'PH_PERF_SC7_FIFO_STATUS_2', - 1023: 'PH_PERF_SC7_FIFO_STATUS_3', -} -PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 -PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 -PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 -PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 -PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 -PH_PERF_SEL_SC0_ARB_BUSY = 8 -PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 -PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 -PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 -PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 -PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 -PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 -PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 -PH_PERF_SEL_SC0_SEND = 16 -PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 -PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 -PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 -PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 -PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 -PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 -PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 -PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 -PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 -PH_PERF_SEL_SC0_PA0_NULL_WE = 28 -PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 -PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 -PH_PERF_SEL_SC0_PA0_LPOV_WE = 31 -PH_PERF_SEL_SC0_PA0_EOP_WE = 32 -PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 -PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 -PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 -PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 -PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 -PH_PERF_SEL_SC0_PA1_NULL_WE = 40 -PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 -PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 -PH_PERF_SEL_SC0_PA1_LPOV_WE = 43 -PH_PERF_SEL_SC0_PA1_EOP_WE = 44 -PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 -PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 -PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 -PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 -PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 -PH_PERF_SEL_SC0_PA2_NULL_WE = 52 -PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 -PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 -PH_PERF_SEL_SC0_PA2_LPOV_WE = 55 -PH_PERF_SEL_SC0_PA2_EOP_WE = 56 -PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 -PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 -PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 -PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 -PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 -PH_PERF_SEL_SC0_PA3_NULL_WE = 64 -PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 -PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 -PH_PERF_SEL_SC0_PA3_LPOV_WE = 67 -PH_PERF_SEL_SC0_PA3_EOP_WE = 68 -PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 -PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 -PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 -PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 -PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 -PH_PERF_SEL_SC0_PA4_NULL_WE = 76 -PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 -PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 -PH_PERF_SEL_SC0_PA4_LPOV_WE = 79 -PH_PERF_SEL_SC0_PA4_EOP_WE = 80 -PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 -PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 -PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 -PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 -PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 -PH_PERF_SEL_SC0_PA5_NULL_WE = 88 -PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 -PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 -PH_PERF_SEL_SC0_PA5_LPOV_WE = 91 -PH_PERF_SEL_SC0_PA5_EOP_WE = 92 -PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 -PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 -PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 -PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 -PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 -PH_PERF_SEL_SC0_PA6_NULL_WE = 100 -PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 -PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 -PH_PERF_SEL_SC0_PA6_LPOV_WE = 103 -PH_PERF_SEL_SC0_PA6_EOP_WE = 104 -PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 -PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 -PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 -PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 -PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 -PH_PERF_SEL_SC0_PA7_NULL_WE = 112 -PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 -PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 -PH_PERF_SEL_SC0_PA7_LPOV_WE = 115 -PH_PERF_SEL_SC0_PA7_EOP_WE = 116 -PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 -PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 -PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119 -PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 -PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 -PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 -PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 -PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 -PH_PERF_SEL_SC1_ARB_BUSY = 128 -PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 -PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 -PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 -PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 -PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 -PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 -PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 -PH_PERF_SEL_SC1_SEND = 136 -PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 -PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 -PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 -PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 -PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 -PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 -PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 -PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 -PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 -PH_PERF_SEL_SC1_PA0_NULL_WE = 148 -PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 -PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 -PH_PERF_SEL_SC1_PA0_LPOV_WE = 151 -PH_PERF_SEL_SC1_PA0_EOP_WE = 152 -PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 -PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 -PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 -PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 -PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 -PH_PERF_SEL_SC1_PA1_NULL_WE = 160 -PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 -PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 -PH_PERF_SEL_SC1_PA1_LPOV_WE = 163 -PH_PERF_SEL_SC1_PA1_EOP_WE = 164 -PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 -PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 -PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 -PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 -PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 -PH_PERF_SEL_SC1_PA2_NULL_WE = 172 -PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 -PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 -PH_PERF_SEL_SC1_PA2_LPOV_WE = 175 -PH_PERF_SEL_SC1_PA2_EOP_WE = 176 -PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 -PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 -PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 -PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 -PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 -PH_PERF_SEL_SC1_PA3_NULL_WE = 184 -PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 -PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 -PH_PERF_SEL_SC1_PA3_LPOV_WE = 187 -PH_PERF_SEL_SC1_PA3_EOP_WE = 188 -PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 -PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 -PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 -PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 -PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 -PH_PERF_SEL_SC1_PA4_NULL_WE = 196 -PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 -PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 -PH_PERF_SEL_SC1_PA4_LPOV_WE = 199 -PH_PERF_SEL_SC1_PA4_EOP_WE = 200 -PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 -PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 -PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 -PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 -PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 -PH_PERF_SEL_SC1_PA5_NULL_WE = 208 -PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 -PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 -PH_PERF_SEL_SC1_PA5_LPOV_WE = 211 -PH_PERF_SEL_SC1_PA5_EOP_WE = 212 -PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 -PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 -PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 -PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 -PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 -PH_PERF_SEL_SC1_PA6_NULL_WE = 220 -PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 -PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 -PH_PERF_SEL_SC1_PA6_LPOV_WE = 223 -PH_PERF_SEL_SC1_PA6_EOP_WE = 224 -PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 -PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 -PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 -PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 -PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 -PH_PERF_SEL_SC1_PA7_NULL_WE = 232 -PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 -PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 -PH_PERF_SEL_SC1_PA7_LPOV_WE = 235 -PH_PERF_SEL_SC1_PA7_EOP_WE = 236 -PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 -PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 -PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239 -PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 -PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 -PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 -PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 -PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 -PH_PERF_SEL_SC2_ARB_BUSY = 248 -PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 -PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 -PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 -PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 -PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 -PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 -PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 -PH_PERF_SEL_SC2_SEND = 256 -PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 -PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 -PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 -PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 -PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 -PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 -PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 -PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 -PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 -PH_PERF_SEL_SC2_PA0_NULL_WE = 268 -PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 -PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 -PH_PERF_SEL_SC2_PA0_LPOV_WE = 271 -PH_PERF_SEL_SC2_PA0_EOP_WE = 272 -PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 -PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 -PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 -PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 -PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 -PH_PERF_SEL_SC2_PA1_NULL_WE = 280 -PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 -PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 -PH_PERF_SEL_SC2_PA1_LPOV_WE = 283 -PH_PERF_SEL_SC2_PA1_EOP_WE = 284 -PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 -PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 -PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 -PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 -PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 -PH_PERF_SEL_SC2_PA2_NULL_WE = 292 -PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 -PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 -PH_PERF_SEL_SC2_PA2_LPOV_WE = 295 -PH_PERF_SEL_SC2_PA2_EOP_WE = 296 -PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 -PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 -PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 -PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 -PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 -PH_PERF_SEL_SC2_PA3_NULL_WE = 304 -PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 -PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 -PH_PERF_SEL_SC2_PA3_LPOV_WE = 307 -PH_PERF_SEL_SC2_PA3_EOP_WE = 308 -PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 -PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 -PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 -PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 -PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 -PH_PERF_SEL_SC2_PA4_NULL_WE = 316 -PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 -PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 -PH_PERF_SEL_SC2_PA4_LPOV_WE = 319 -PH_PERF_SEL_SC2_PA4_EOP_WE = 320 -PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 -PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 -PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 -PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 -PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 -PH_PERF_SEL_SC2_PA5_NULL_WE = 328 -PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 -PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 -PH_PERF_SEL_SC2_PA5_LPOV_WE = 331 -PH_PERF_SEL_SC2_PA5_EOP_WE = 332 -PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 -PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 -PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 -PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 -PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 -PH_PERF_SEL_SC2_PA6_NULL_WE = 340 -PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 -PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 -PH_PERF_SEL_SC2_PA6_LPOV_WE = 343 -PH_PERF_SEL_SC2_PA6_EOP_WE = 344 -PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 -PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 -PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 -PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 -PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 -PH_PERF_SEL_SC2_PA7_NULL_WE = 352 -PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 -PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 -PH_PERF_SEL_SC2_PA7_LPOV_WE = 355 -PH_PERF_SEL_SC2_PA7_EOP_WE = 356 -PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 -PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 -PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359 -PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 -PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 -PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 -PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 -PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 -PH_PERF_SEL_SC3_ARB_BUSY = 368 -PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 -PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 -PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 -PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 -PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 -PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 -PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 -PH_PERF_SEL_SC3_SEND = 376 -PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 -PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 -PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 -PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 -PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 -PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 -PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 -PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 -PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 -PH_PERF_SEL_SC3_PA0_NULL_WE = 388 -PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 -PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 -PH_PERF_SEL_SC3_PA0_LPOV_WE = 391 -PH_PERF_SEL_SC3_PA0_EOP_WE = 392 -PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 -PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 -PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 -PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 -PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 -PH_PERF_SEL_SC3_PA1_NULL_WE = 400 -PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 -PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 -PH_PERF_SEL_SC3_PA1_LPOV_WE = 403 -PH_PERF_SEL_SC3_PA1_EOP_WE = 404 -PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 -PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 -PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 -PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 -PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 -PH_PERF_SEL_SC3_PA2_NULL_WE = 412 -PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 -PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 -PH_PERF_SEL_SC3_PA2_LPOV_WE = 415 -PH_PERF_SEL_SC3_PA2_EOP_WE = 416 -PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 -PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 -PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 -PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 -PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 -PH_PERF_SEL_SC3_PA3_NULL_WE = 424 -PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 -PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 -PH_PERF_SEL_SC3_PA3_LPOV_WE = 427 -PH_PERF_SEL_SC3_PA3_EOP_WE = 428 -PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 -PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 -PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 -PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 -PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 -PH_PERF_SEL_SC3_PA4_NULL_WE = 436 -PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 -PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 -PH_PERF_SEL_SC3_PA4_LPOV_WE = 439 -PH_PERF_SEL_SC3_PA4_EOP_WE = 440 -PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 -PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 -PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 -PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 -PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 -PH_PERF_SEL_SC3_PA5_NULL_WE = 448 -PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 -PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 -PH_PERF_SEL_SC3_PA5_LPOV_WE = 451 -PH_PERF_SEL_SC3_PA5_EOP_WE = 452 -PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 -PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 -PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 -PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 -PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 -PH_PERF_SEL_SC3_PA6_NULL_WE = 460 -PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 -PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 -PH_PERF_SEL_SC3_PA6_LPOV_WE = 463 -PH_PERF_SEL_SC3_PA6_EOP_WE = 464 -PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 -PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 -PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 -PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 -PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 -PH_PERF_SEL_SC3_PA7_NULL_WE = 472 -PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 -PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 -PH_PERF_SEL_SC3_PA7_LPOV_WE = 475 -PH_PERF_SEL_SC3_PA7_EOP_WE = 476 -PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 -PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 -PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479 -PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 -PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 -PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 -PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 -PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 -PH_PERF_SEL_SC4_ARB_BUSY = 488 -PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 -PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 -PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 -PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 -PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 -PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 -PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 -PH_PERF_SEL_SC4_SEND = 496 -PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 -PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 -PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 -PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 -PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 -PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 -PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 -PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 -PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 -PH_PERF_SEL_SC4_PA0_NULL_WE = 508 -PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 -PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 -PH_PERF_SEL_SC4_PA0_LPOV_WE = 511 -PH_PERF_SEL_SC4_PA0_EOP_WE = 512 -PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 -PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 -PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 -PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 -PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 -PH_PERF_SEL_SC4_PA1_NULL_WE = 520 -PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 -PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 -PH_PERF_SEL_SC4_PA1_LPOV_WE = 523 -PH_PERF_SEL_SC4_PA1_EOP_WE = 524 -PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 -PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 -PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 -PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 -PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 -PH_PERF_SEL_SC4_PA2_NULL_WE = 532 -PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 -PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 -PH_PERF_SEL_SC4_PA2_LPOV_WE = 535 -PH_PERF_SEL_SC4_PA2_EOP_WE = 536 -PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 -PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 -PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 -PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 -PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 -PH_PERF_SEL_SC4_PA3_NULL_WE = 544 -PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 -PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 -PH_PERF_SEL_SC4_PA3_LPOV_WE = 547 -PH_PERF_SEL_SC4_PA3_EOP_WE = 548 -PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 -PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 -PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 -PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 -PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 -PH_PERF_SEL_SC4_PA4_NULL_WE = 556 -PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 -PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 -PH_PERF_SEL_SC4_PA4_LPOV_WE = 559 -PH_PERF_SEL_SC4_PA4_EOP_WE = 560 -PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 -PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 -PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 -PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 -PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 -PH_PERF_SEL_SC4_PA5_NULL_WE = 568 -PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 -PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 -PH_PERF_SEL_SC4_PA5_LPOV_WE = 571 -PH_PERF_SEL_SC4_PA5_EOP_WE = 572 -PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 -PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 -PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 -PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 -PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 -PH_PERF_SEL_SC4_PA6_NULL_WE = 580 -PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 -PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 -PH_PERF_SEL_SC4_PA6_LPOV_WE = 583 -PH_PERF_SEL_SC4_PA6_EOP_WE = 584 -PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 -PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 -PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 -PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 -PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 -PH_PERF_SEL_SC4_PA7_NULL_WE = 592 -PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 -PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 -PH_PERF_SEL_SC4_PA7_LPOV_WE = 595 -PH_PERF_SEL_SC4_PA7_EOP_WE = 596 -PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 -PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 -PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599 -PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 -PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 -PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 -PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 -PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 -PH_PERF_SEL_SC5_ARB_BUSY = 608 -PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 -PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 -PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 -PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 -PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 -PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 -PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 -PH_PERF_SEL_SC5_SEND = 616 -PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 -PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 -PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 -PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 -PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 -PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 -PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 -PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 -PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 -PH_PERF_SEL_SC5_PA0_NULL_WE = 628 -PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 -PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 -PH_PERF_SEL_SC5_PA0_LPOV_WE = 631 -PH_PERF_SEL_SC5_PA0_EOP_WE = 632 -PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 -PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 -PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 -PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 -PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 -PH_PERF_SEL_SC5_PA1_NULL_WE = 640 -PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 -PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 -PH_PERF_SEL_SC5_PA1_LPOV_WE = 643 -PH_PERF_SEL_SC5_PA1_EOP_WE = 644 -PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 -PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 -PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 -PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 -PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 -PH_PERF_SEL_SC5_PA2_NULL_WE = 652 -PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 -PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 -PH_PERF_SEL_SC5_PA2_LPOV_WE = 655 -PH_PERF_SEL_SC5_PA2_EOP_WE = 656 -PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 -PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 -PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 -PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 -PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 -PH_PERF_SEL_SC5_PA3_NULL_WE = 664 -PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 -PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 -PH_PERF_SEL_SC5_PA3_LPOV_WE = 667 -PH_PERF_SEL_SC5_PA3_EOP_WE = 668 -PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 -PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 -PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 -PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 -PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 -PH_PERF_SEL_SC5_PA4_NULL_WE = 676 -PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 -PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 -PH_PERF_SEL_SC5_PA4_LPOV_WE = 679 -PH_PERF_SEL_SC5_PA4_EOP_WE = 680 -PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 -PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 -PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 -PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 -PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 -PH_PERF_SEL_SC5_PA5_NULL_WE = 688 -PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 -PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 -PH_PERF_SEL_SC5_PA5_LPOV_WE = 691 -PH_PERF_SEL_SC5_PA5_EOP_WE = 692 -PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 -PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 -PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 -PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 -PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 -PH_PERF_SEL_SC5_PA6_NULL_WE = 700 -PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 -PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 -PH_PERF_SEL_SC5_PA6_LPOV_WE = 703 -PH_PERF_SEL_SC5_PA6_EOP_WE = 704 -PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 -PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 -PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 -PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 -PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 -PH_PERF_SEL_SC5_PA7_NULL_WE = 712 -PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 -PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 -PH_PERF_SEL_SC5_PA7_LPOV_WE = 715 -PH_PERF_SEL_SC5_PA7_EOP_WE = 716 -PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 -PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 -PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719 -PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 -PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 -PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 -PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 -PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 -PH_PERF_SEL_SC6_ARB_BUSY = 728 -PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 -PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 -PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 -PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 -PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 -PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 -PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 -PH_PERF_SEL_SC6_SEND = 736 -PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 -PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 -PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 -PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 -PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 -PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 -PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 -PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 -PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 -PH_PERF_SEL_SC6_PA0_NULL_WE = 748 -PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 -PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 -PH_PERF_SEL_SC6_PA0_LPOV_WE = 751 -PH_PERF_SEL_SC6_PA0_EOP_WE = 752 -PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 -PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 -PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 -PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 -PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 -PH_PERF_SEL_SC6_PA1_NULL_WE = 760 -PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 -PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 -PH_PERF_SEL_SC6_PA1_LPOV_WE = 763 -PH_PERF_SEL_SC6_PA1_EOP_WE = 764 -PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 -PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 -PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 -PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 -PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 -PH_PERF_SEL_SC6_PA2_NULL_WE = 772 -PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 -PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 -PH_PERF_SEL_SC6_PA2_LPOV_WE = 775 -PH_PERF_SEL_SC6_PA2_EOP_WE = 776 -PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 -PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 -PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 -PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 -PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 -PH_PERF_SEL_SC6_PA3_NULL_WE = 784 -PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 -PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 -PH_PERF_SEL_SC6_PA3_LPOV_WE = 787 -PH_PERF_SEL_SC6_PA3_EOP_WE = 788 -PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 -PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 -PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 -PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 -PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 -PH_PERF_SEL_SC6_PA4_NULL_WE = 796 -PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 -PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 -PH_PERF_SEL_SC6_PA4_LPOV_WE = 799 -PH_PERF_SEL_SC6_PA4_EOP_WE = 800 -PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 -PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 -PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 -PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 -PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 -PH_PERF_SEL_SC6_PA5_NULL_WE = 808 -PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 -PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 -PH_PERF_SEL_SC6_PA5_LPOV_WE = 811 -PH_PERF_SEL_SC6_PA5_EOP_WE = 812 -PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 -PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 -PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 -PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 -PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 -PH_PERF_SEL_SC6_PA6_NULL_WE = 820 -PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 -PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 -PH_PERF_SEL_SC6_PA6_LPOV_WE = 823 -PH_PERF_SEL_SC6_PA6_EOP_WE = 824 -PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 -PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 -PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 -PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 -PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 -PH_PERF_SEL_SC6_PA7_NULL_WE = 832 -PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 -PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 -PH_PERF_SEL_SC6_PA7_LPOV_WE = 835 -PH_PERF_SEL_SC6_PA7_EOP_WE = 836 -PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 -PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 -PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839 -PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 -PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 -PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 -PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 -PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 -PH_PERF_SEL_SC7_ARB_BUSY = 848 -PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 -PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 -PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 -PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 -PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 -PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 -PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 -PH_PERF_SEL_SC7_SEND = 856 -PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 -PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 -PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 -PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 -PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 -PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 -PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 -PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 -PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 -PH_PERF_SEL_SC7_PA0_NULL_WE = 868 -PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 -PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 -PH_PERF_SEL_SC7_PA0_LPOV_WE = 871 -PH_PERF_SEL_SC7_PA0_EOP_WE = 872 -PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 -PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 -PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 -PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 -PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 -PH_PERF_SEL_SC7_PA1_NULL_WE = 880 -PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 -PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 -PH_PERF_SEL_SC7_PA1_LPOV_WE = 883 -PH_PERF_SEL_SC7_PA1_EOP_WE = 884 -PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 -PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 -PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 -PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 -PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 -PH_PERF_SEL_SC7_PA2_NULL_WE = 892 -PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 -PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 -PH_PERF_SEL_SC7_PA2_LPOV_WE = 895 -PH_PERF_SEL_SC7_PA2_EOP_WE = 896 -PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 -PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 -PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 -PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 -PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 -PH_PERF_SEL_SC7_PA3_NULL_WE = 904 -PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 -PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 -PH_PERF_SEL_SC7_PA3_LPOV_WE = 907 -PH_PERF_SEL_SC7_PA3_EOP_WE = 908 -PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 -PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 -PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 -PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 -PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 -PH_PERF_SEL_SC7_PA4_NULL_WE = 916 -PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 -PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 -PH_PERF_SEL_SC7_PA4_LPOV_WE = 919 -PH_PERF_SEL_SC7_PA4_EOP_WE = 920 -PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 -PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 -PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 -PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 -PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 -PH_PERF_SEL_SC7_PA5_NULL_WE = 928 -PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 -PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 -PH_PERF_SEL_SC7_PA5_LPOV_WE = 931 -PH_PERF_SEL_SC7_PA5_EOP_WE = 932 -PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 -PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 -PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 -PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 -PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 -PH_PERF_SEL_SC7_PA6_NULL_WE = 940 -PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 -PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 -PH_PERF_SEL_SC7_PA6_LPOV_WE = 943 -PH_PERF_SEL_SC7_PA6_EOP_WE = 944 -PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 -PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 -PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 -PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 -PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 -PH_PERF_SEL_SC7_PA7_NULL_WE = 952 -PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 -PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 -PH_PERF_SEL_SC7_PA7_LPOV_WE = 955 -PH_PERF_SEL_SC7_PA7_EOP_WE = 956 -PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 -PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 -PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959 -PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 -PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 -PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 -PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 -PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 -PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 -PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 -PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 -PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 -PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 -PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 -PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 -PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 -PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 -PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 -PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 -PH_PERF_SC0_FIFO_STATUS_0 = 992 -PH_PERF_SC0_FIFO_STATUS_1 = 993 -PH_PERF_SC0_FIFO_STATUS_2 = 994 -PH_PERF_SC0_FIFO_STATUS_3 = 995 -PH_PERF_SC1_FIFO_STATUS_0 = 996 -PH_PERF_SC1_FIFO_STATUS_1 = 997 -PH_PERF_SC1_FIFO_STATUS_2 = 998 -PH_PERF_SC1_FIFO_STATUS_3 = 999 -PH_PERF_SC2_FIFO_STATUS_0 = 1000 -PH_PERF_SC2_FIFO_STATUS_1 = 1001 -PH_PERF_SC2_FIFO_STATUS_2 = 1002 -PH_PERF_SC2_FIFO_STATUS_3 = 1003 -PH_PERF_SC3_FIFO_STATUS_0 = 1004 -PH_PERF_SC3_FIFO_STATUS_1 = 1005 -PH_PERF_SC3_FIFO_STATUS_2 = 1006 -PH_PERF_SC3_FIFO_STATUS_3 = 1007 -PH_PERF_SC4_FIFO_STATUS_0 = 1008 -PH_PERF_SC4_FIFO_STATUS_1 = 1009 -PH_PERF_SC4_FIFO_STATUS_2 = 1010 -PH_PERF_SC4_FIFO_STATUS_3 = 1011 -PH_PERF_SC5_FIFO_STATUS_0 = 1012 -PH_PERF_SC5_FIFO_STATUS_1 = 1013 -PH_PERF_SC5_FIFO_STATUS_2 = 1014 -PH_PERF_SC5_FIFO_STATUS_3 = 1015 -PH_PERF_SC6_FIFO_STATUS_0 = 1016 -PH_PERF_SC6_FIFO_STATUS_1 = 1017 -PH_PERF_SC6_FIFO_STATUS_2 = 1018 -PH_PERF_SC6_FIFO_STATUS_3 = 1019 -PH_PERF_SC7_FIFO_STATUS_0 = 1020 -PH_PERF_SC7_FIFO_STATUS_1 = 1021 -PH_PERF_SC7_FIFO_STATUS_2 = 1022 -PH_PERF_SC7_FIFO_STATUS_3 = 1023 -PH_PERFCNT_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'PhSPIstatusMode' -PhSPIstatusMode__enumvalues = { - 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 2: 'PH_SPI_MODE_DISABLED', -} -PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 -PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 -PH_SPI_MODE_DISABLED = 2 -PhSPIstatusMode = ctypes.c_uint32 # enum - -# values for enumeration 'RMIPerfSel' -RMIPerfSel__enumvalues = { - 0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', - 1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', -} -RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0 -RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1 -RMIPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'GCRPerfSel' -GCRPerfSel__enumvalues = { - 0: 'GCR_PERF_SEL_NONE', - 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', - 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', - 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', - 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', - 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 33: 'GCR_PERF_SEL_CPC_ALL_REQ', - 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', - 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', - 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', - 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', - 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 47: 'GCR_PERF_SEL_CPC_TCP_REQ', - 48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 49: 'GCR_PERF_SEL_CPG_ALL_REQ', - 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', - 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', - 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', - 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', - 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 63: 'GCR_PERF_SEL_CPG_TCP_REQ', - 64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', - 65: 'GCR_PERF_SEL_CPF_ALL_REQ', - 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', - 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', - 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', - 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', - 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 79: 'GCR_PERF_SEL_CPF_TCP_REQ', - 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 81: 'GCR_PERF_SEL_VIRT_REQ', - 82: 'GCR_PERF_SEL_PHY_REQ', - 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 85: 'GCR_PERF_SEL_ALL_REQ', - 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 89: 'GCR_PERF_SEL_UTCL2_REQ', - 90: 'GCR_PERF_SEL_UTCL2_RET', - 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 94: 'GCR_PERF_SEL_RLC_ALL_REQ', - 95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', - 96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', - 101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 105: 'GCR_PERF_SEL_RLC_METADATA_REQ', - 106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', - 107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 108: 'GCR_PERF_SEL_RLC_TCP_REQ', - 109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', - 110: 'GCR_PERF_SEL_PM_ALL_REQ', - 111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', - 112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', - 117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 121: 'GCR_PERF_SEL_PM_METADATA_REQ', - 122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', - 123: 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 124: 'GCR_PERF_SEL_PM_TCP_REQ', - 125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', - 126: 'GCR_PERF_SEL_PIO_ALL_REQ', - 127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', - 128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', - 133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 137: 'GCR_PERF_SEL_PIO_METADATA_REQ', - 138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', - 139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 140: 'GCR_PERF_SEL_PIO_TCP_REQ', - 141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', -} -GCR_PERF_SEL_NONE = 0 -GCR_PERF_SEL_SDMA0_ALL_REQ = 1 -GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 -GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 -GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 -GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 -GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 -GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 -GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 -GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 -GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 -GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 -GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 -GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 -GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 -GCR_PERF_SEL_SDMA0_TCP_REQ = 15 -GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 -GCR_PERF_SEL_SDMA1_ALL_REQ = 17 -GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 -GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 -GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 -GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 -GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 -GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 -GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 -GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 -GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 -GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 -GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 -GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 -GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 -GCR_PERF_SEL_SDMA1_TCP_REQ = 31 -GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 -GCR_PERF_SEL_CPC_ALL_REQ = 33 -GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 -GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 -GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 -GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 -GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 -GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 -GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 -GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 -GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 -GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 -GCR_PERF_SEL_CPC_METADATA_REQ = 44 -GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 -GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 -GCR_PERF_SEL_CPC_TCP_REQ = 47 -GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48 -GCR_PERF_SEL_CPG_ALL_REQ = 49 -GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 -GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 -GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 -GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 -GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 -GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 -GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 -GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 -GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 -GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 -GCR_PERF_SEL_CPG_METADATA_REQ = 60 -GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 -GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 -GCR_PERF_SEL_CPG_TCP_REQ = 63 -GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64 -GCR_PERF_SEL_CPF_ALL_REQ = 65 -GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 -GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 -GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 -GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 -GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 -GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 -GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 -GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 -GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 -GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 -GCR_PERF_SEL_CPF_METADATA_REQ = 76 -GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 -GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 -GCR_PERF_SEL_CPF_TCP_REQ = 79 -GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 -GCR_PERF_SEL_VIRT_REQ = 81 -GCR_PERF_SEL_PHY_REQ = 82 -GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 -GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 -GCR_PERF_SEL_ALL_REQ = 85 -GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 -GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 -GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 -GCR_PERF_SEL_UTCL2_REQ = 89 -GCR_PERF_SEL_UTCL2_RET = 90 -GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 -GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 -GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 -GCR_PERF_SEL_RLC_ALL_REQ = 94 -GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95 -GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96 -GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97 -GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98 -GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99 -GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100 -GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101 -GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102 -GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103 -GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104 -GCR_PERF_SEL_RLC_METADATA_REQ = 105 -GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106 -GCR_PERF_SEL_RLC_SQC_INST_REQ = 107 -GCR_PERF_SEL_RLC_TCP_REQ = 108 -GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109 -GCR_PERF_SEL_PM_ALL_REQ = 110 -GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111 -GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112 -GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113 -GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114 -GCR_PERF_SEL_PM_GL2_ALL_REQ = 115 -GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116 -GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117 -GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118 -GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119 -GCR_PERF_SEL_PM_GL1_ALL_REQ = 120 -GCR_PERF_SEL_PM_METADATA_REQ = 121 -GCR_PERF_SEL_PM_SQC_DATA_REQ = 122 -GCR_PERF_SEL_PM_SQC_INST_REQ = 123 -GCR_PERF_SEL_PM_TCP_REQ = 124 -GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125 -GCR_PERF_SEL_PIO_ALL_REQ = 126 -GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127 -GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128 -GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129 -GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130 -GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131 -GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132 -GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133 -GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134 -GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135 -GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136 -GCR_PERF_SEL_PIO_METADATA_REQ = 137 -GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138 -GCR_PERF_SEL_PIO_SQC_INST_REQ = 139 -GCR_PERF_SEL_PIO_TCP_REQ = 140 -GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141 -GCRPerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'UTCL1PerfSel' -UTCL1PerfSel__enumvalues = { - 0: 'UTCL1_PERF_SEL_NONE', - 1: 'UTCL1_PERF_SEL_REQS', - 2: 'UTCL1_PERF_SEL_HITS', - 3: 'UTCL1_PERF_SEL_MISSES', - 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', - 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 6: 'UTCL1_PERF_SEL_UTCL2_REQS', - 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', - 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', - 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', - 13: 'UTCL1_PERF_SEL_RTNS', - 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', - 15: 'UTCL1_PERF_SEL_BYPASS_REQS', - 16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 19: 'UTCL1_PERF_SEL_CP_INVREQS', - 20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 21: 'UTCL1_PERF_SEL_RANGE_INVREQS', - 22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', -} -UTCL1_PERF_SEL_NONE = 0 -UTCL1_PERF_SEL_REQS = 1 -UTCL1_PERF_SEL_HITS = 2 -UTCL1_PERF_SEL_MISSES = 3 -UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 -UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 -UTCL1_PERF_SEL_UTCL2_REQS = 6 -UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 -UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 -UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 -UTCL1_PERF_SEL_STALL_MH_FULL = 10 -UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 -UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 -UTCL1_PERF_SEL_RTNS = 13 -UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 -UTCL1_PERF_SEL_BYPASS_REQS = 15 -UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16 -UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17 -UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18 -UTCL1_PERF_SEL_CP_INVREQS = 19 -UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20 -UTCL1_PERF_SEL_RANGE_INVREQS = 21 -UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22 -UTCL1PerfSel = ctypes.c_uint32 # enum - -# values for enumeration 'IH_CLIENT_TYPE' -IH_CLIENT_TYPE__enumvalues = { - 0: 'IH_GFX_VMID_CLIENT', - 1: 'IH_MM_VMID_CLIENT', - 2: 'IH_MULTI_VMID_CLIENT', - 3: 'IH_CLIENT_TYPE_RESERVED', -} -IH_GFX_VMID_CLIENT = 0 -IH_MM_VMID_CLIENT = 1 -IH_MULTI_VMID_CLIENT = 2 -IH_CLIENT_TYPE_RESERVED = 3 -IH_CLIENT_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'IH_INTERFACE_TYPE' -IH_INTERFACE_TYPE__enumvalues = { - 0: 'IH_LEGACY_INTERFACE', - 1: 'IH_REGISTER_WRITE_INTERFACE', -} -IH_LEGACY_INTERFACE = 0 -IH_REGISTER_WRITE_INTERFACE = 1 -IH_INTERFACE_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'IH_PERF_SEL' -IH_PERF_SEL__enumvalues = { - 0: 'IH_PERF_SEL_CYCLE', - 1: 'IH_PERF_SEL_IDLE', - 2: 'IH_PERF_SEL_INPUT_IDLE', - 3: 'IH_PERF_SEL_BUFFER_IDLE', - 4: 'IH_PERF_SEL_RB0_FULL', - 5: 'IH_PERF_SEL_RB0_OVERFLOW', - 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', - 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', - 9: 'IH_PERF_SEL_MC_WR_IDLE', - 10: 'IH_PERF_SEL_MC_WR_COUNT', - 11: 'IH_PERF_SEL_MC_WR_STALL', - 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', - 14: 'IH_PERF_SEL_BIF_LINE0_RISING', - 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', - 16: 'IH_PERF_SEL_RB1_FULL', - 17: 'IH_PERF_SEL_RB1_OVERFLOW', - 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', - 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', - 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', - 21: 'IH_PERF_SEL_RB2_FULL', - 22: 'IH_PERF_SEL_RB2_OVERFLOW', - 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', - 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', - 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', - 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 27: 'IH_PERF_SEL_SELF_IV_VALID', - 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', - 29: 'IH_PERF_SEL_RB0_FULL_VF0', - 30: 'IH_PERF_SEL_RB0_FULL_VF1', - 31: 'IH_PERF_SEL_RB0_FULL_VF2', - 32: 'IH_PERF_SEL_RB0_FULL_VF3', - 33: 'IH_PERF_SEL_RB0_FULL_VF4', - 34: 'IH_PERF_SEL_RB0_FULL_VF5', - 35: 'IH_PERF_SEL_RB0_FULL_VF6', - 36: 'IH_PERF_SEL_RB0_FULL_VF7', - 37: 'IH_PERF_SEL_RB0_FULL_VF8', - 38: 'IH_PERF_SEL_RB0_FULL_VF9', - 39: 'IH_PERF_SEL_RB0_FULL_VF10', - 40: 'IH_PERF_SEL_RB0_FULL_VF11', - 41: 'IH_PERF_SEL_RB0_FULL_VF12', - 42: 'IH_PERF_SEL_RB0_FULL_VF13', - 43: 'IH_PERF_SEL_RB0_FULL_VF14', - 44: 'IH_PERF_SEL_RB0_FULL_VF15', - 45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', - 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', - 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', - 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', - 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', - 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', - 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', - 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', - 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', - 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', - 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', - 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', - 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', - 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', - 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', - 93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', - 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', - 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', - 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', - 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', - 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', - 109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 141: 'IH_PERF_SEL_CLIENT0_INT', - 142: 'IH_PERF_SEL_CLIENT1_INT', - 143: 'IH_PERF_SEL_CLIENT2_INT', - 144: 'IH_PERF_SEL_CLIENT3_INT', - 145: 'IH_PERF_SEL_CLIENT4_INT', - 146: 'IH_PERF_SEL_CLIENT5_INT', - 147: 'IH_PERF_SEL_CLIENT6_INT', - 148: 'IH_PERF_SEL_CLIENT7_INT', - 149: 'IH_PERF_SEL_CLIENT8_INT', - 150: 'IH_PERF_SEL_CLIENT9_INT', - 151: 'IH_PERF_SEL_CLIENT10_INT', - 152: 'IH_PERF_SEL_CLIENT11_INT', - 153: 'IH_PERF_SEL_CLIENT12_INT', - 154: 'IH_PERF_SEL_CLIENT13_INT', - 155: 'IH_PERF_SEL_CLIENT14_INT', - 156: 'IH_PERF_SEL_CLIENT15_INT', - 157: 'IH_PERF_SEL_CLIENT16_INT', - 158: 'IH_PERF_SEL_CLIENT17_INT', - 159: 'IH_PERF_SEL_CLIENT18_INT', - 160: 'IH_PERF_SEL_CLIENT19_INT', - 161: 'IH_PERF_SEL_CLIENT20_INT', - 162: 'IH_PERF_SEL_CLIENT21_INT', - 163: 'IH_PERF_SEL_CLIENT22_INT', - 164: 'IH_PERF_SEL_CLIENT23_INT', - 165: 'IH_PERF_SEL_CLIENT24_INT', - 166: 'IH_PERF_SEL_CLIENT25_INT', - 167: 'IH_PERF_SEL_CLIENT26_INT', - 168: 'IH_PERF_SEL_CLIENT27_INT', - 169: 'IH_PERF_SEL_CLIENT28_INT', - 170: 'IH_PERF_SEL_CLIENT29_INT', - 171: 'IH_PERF_SEL_CLIENT30_INT', - 172: 'IH_PERF_SEL_CLIENT31_INT', - 173: 'IH_PERF_SEL_RB1_FULL_VF0', - 174: 'IH_PERF_SEL_RB1_FULL_VF1', - 175: 'IH_PERF_SEL_RB1_FULL_VF2', - 176: 'IH_PERF_SEL_RB1_FULL_VF3', - 177: 'IH_PERF_SEL_RB1_FULL_VF4', - 178: 'IH_PERF_SEL_RB1_FULL_VF5', - 179: 'IH_PERF_SEL_RB1_FULL_VF6', - 180: 'IH_PERF_SEL_RB1_FULL_VF7', - 181: 'IH_PERF_SEL_RB1_FULL_VF8', - 182: 'IH_PERF_SEL_RB1_FULL_VF9', - 183: 'IH_PERF_SEL_RB1_FULL_VF10', - 184: 'IH_PERF_SEL_RB1_FULL_VF11', - 185: 'IH_PERF_SEL_RB1_FULL_VF12', - 186: 'IH_PERF_SEL_RB1_FULL_VF13', - 187: 'IH_PERF_SEL_RB1_FULL_VF14', - 188: 'IH_PERF_SEL_RB1_FULL_VF15', - 189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', - 190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', - 192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', - 194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', - 196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', - 198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', - 200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', - 202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', - 204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', - 206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', - 209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', - 211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', - 213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', - 215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', - 221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', - 223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', - 225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', - 227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', - 229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', - 231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', - 237: 'IH_PERF_SEL_RB2_FULL_VF0', - 238: 'IH_PERF_SEL_RB2_FULL_VF1', - 239: 'IH_PERF_SEL_RB2_FULL_VF2', - 240: 'IH_PERF_SEL_RB2_FULL_VF3', - 241: 'IH_PERF_SEL_RB2_FULL_VF4', - 242: 'IH_PERF_SEL_RB2_FULL_VF5', - 243: 'IH_PERF_SEL_RB2_FULL_VF6', - 244: 'IH_PERF_SEL_RB2_FULL_VF7', - 245: 'IH_PERF_SEL_RB2_FULL_VF8', - 246: 'IH_PERF_SEL_RB2_FULL_VF9', - 247: 'IH_PERF_SEL_RB2_FULL_VF10', - 248: 'IH_PERF_SEL_RB2_FULL_VF11', - 249: 'IH_PERF_SEL_RB2_FULL_VF12', - 250: 'IH_PERF_SEL_RB2_FULL_VF13', - 251: 'IH_PERF_SEL_RB2_FULL_VF14', - 252: 'IH_PERF_SEL_RB2_FULL_VF15', - 253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', - 254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', - 256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', - 258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', - 260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', - 262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', - 264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', - 266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', - 268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', - 270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', - 273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', - 275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', - 277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', - 279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', - 285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', - 287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', - 289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', - 291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', - 293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', - 295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', - 301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', - 312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', - 329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', - 346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 352: 'IH_PERF_SEL_RB0_LOAD_RPTR', - 353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', - 354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', - 355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', - 357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', - 359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', - 361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', - 363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', - 369: 'IH_PERF_SEL_RB1_LOAD_RPTR', - 370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', - 371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', - 372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', - 374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', - 376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', - 378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', - 380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', - 386: 'IH_PERF_SEL_RB2_LOAD_RPTR', - 387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', - 388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', - 389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', - 391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', - 393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', - 395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', - 397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', -} -IH_PERF_SEL_CYCLE = 0 -IH_PERF_SEL_IDLE = 1 -IH_PERF_SEL_INPUT_IDLE = 2 -IH_PERF_SEL_BUFFER_IDLE = 3 -IH_PERF_SEL_RB0_FULL = 4 -IH_PERF_SEL_RB0_OVERFLOW = 5 -IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 -IH_PERF_SEL_RB0_WPTR_WRAP = 7 -IH_PERF_SEL_RB0_RPTR_WRAP = 8 -IH_PERF_SEL_MC_WR_IDLE = 9 -IH_PERF_SEL_MC_WR_COUNT = 10 -IH_PERF_SEL_MC_WR_STALL = 11 -IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 -IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 -IH_PERF_SEL_BIF_LINE0_RISING = 14 -IH_PERF_SEL_BIF_LINE0_FALLING = 15 -IH_PERF_SEL_RB1_FULL = 16 -IH_PERF_SEL_RB1_OVERFLOW = 17 -IH_PERF_SEL_COOKIE_REC_ERROR = 18 -IH_PERF_SEL_RB1_WPTR_WRAP = 19 -IH_PERF_SEL_RB1_RPTR_WRAP = 20 -IH_PERF_SEL_RB2_FULL = 21 -IH_PERF_SEL_RB2_OVERFLOW = 22 -IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 -IH_PERF_SEL_RB2_WPTR_WRAP = 24 -IH_PERF_SEL_RB2_RPTR_WRAP = 25 -IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 -IH_PERF_SEL_SELF_IV_VALID = 27 -IH_PERF_SEL_BUFFER_FIFO_FULL = 28 -IH_PERF_SEL_RB0_FULL_VF0 = 29 -IH_PERF_SEL_RB0_FULL_VF1 = 30 -IH_PERF_SEL_RB0_FULL_VF2 = 31 -IH_PERF_SEL_RB0_FULL_VF3 = 32 -IH_PERF_SEL_RB0_FULL_VF4 = 33 -IH_PERF_SEL_RB0_FULL_VF5 = 34 -IH_PERF_SEL_RB0_FULL_VF6 = 35 -IH_PERF_SEL_RB0_FULL_VF7 = 36 -IH_PERF_SEL_RB0_FULL_VF8 = 37 -IH_PERF_SEL_RB0_FULL_VF9 = 38 -IH_PERF_SEL_RB0_FULL_VF10 = 39 -IH_PERF_SEL_RB0_FULL_VF11 = 40 -IH_PERF_SEL_RB0_FULL_VF12 = 41 -IH_PERF_SEL_RB0_FULL_VF13 = 42 -IH_PERF_SEL_RB0_FULL_VF14 = 43 -IH_PERF_SEL_RB0_FULL_VF15 = 44 -IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45 -IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46 -IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47 -IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48 -IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49 -IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50 -IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51 -IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52 -IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53 -IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54 -IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55 -IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56 -IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57 -IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58 -IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59 -IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75 -IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76 -IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77 -IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78 -IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79 -IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80 -IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81 -IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82 -IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83 -IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84 -IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85 -IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86 -IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87 -IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88 -IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89 -IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90 -IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91 -IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92 -IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93 -IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94 -IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95 -IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96 -IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97 -IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98 -IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99 -IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100 -IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101 -IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102 -IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103 -IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104 -IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105 -IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106 -IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107 -IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108 -IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109 -IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110 -IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111 -IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112 -IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113 -IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114 -IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115 -IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116 -IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117 -IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118 -IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119 -IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120 -IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121 -IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122 -IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123 -IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124 -IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125 -IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126 -IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127 -IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128 -IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129 -IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130 -IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131 -IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132 -IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133 -IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134 -IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135 -IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136 -IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137 -IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138 -IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139 -IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140 -IH_PERF_SEL_CLIENT0_INT = 141 -IH_PERF_SEL_CLIENT1_INT = 142 -IH_PERF_SEL_CLIENT2_INT = 143 -IH_PERF_SEL_CLIENT3_INT = 144 -IH_PERF_SEL_CLIENT4_INT = 145 -IH_PERF_SEL_CLIENT5_INT = 146 -IH_PERF_SEL_CLIENT6_INT = 147 -IH_PERF_SEL_CLIENT7_INT = 148 -IH_PERF_SEL_CLIENT8_INT = 149 -IH_PERF_SEL_CLIENT9_INT = 150 -IH_PERF_SEL_CLIENT10_INT = 151 -IH_PERF_SEL_CLIENT11_INT = 152 -IH_PERF_SEL_CLIENT12_INT = 153 -IH_PERF_SEL_CLIENT13_INT = 154 -IH_PERF_SEL_CLIENT14_INT = 155 -IH_PERF_SEL_CLIENT15_INT = 156 -IH_PERF_SEL_CLIENT16_INT = 157 -IH_PERF_SEL_CLIENT17_INT = 158 -IH_PERF_SEL_CLIENT18_INT = 159 -IH_PERF_SEL_CLIENT19_INT = 160 -IH_PERF_SEL_CLIENT20_INT = 161 -IH_PERF_SEL_CLIENT21_INT = 162 -IH_PERF_SEL_CLIENT22_INT = 163 -IH_PERF_SEL_CLIENT23_INT = 164 -IH_PERF_SEL_CLIENT24_INT = 165 -IH_PERF_SEL_CLIENT25_INT = 166 -IH_PERF_SEL_CLIENT26_INT = 167 -IH_PERF_SEL_CLIENT27_INT = 168 -IH_PERF_SEL_CLIENT28_INT = 169 -IH_PERF_SEL_CLIENT29_INT = 170 -IH_PERF_SEL_CLIENT30_INT = 171 -IH_PERF_SEL_CLIENT31_INT = 172 -IH_PERF_SEL_RB1_FULL_VF0 = 173 -IH_PERF_SEL_RB1_FULL_VF1 = 174 -IH_PERF_SEL_RB1_FULL_VF2 = 175 -IH_PERF_SEL_RB1_FULL_VF3 = 176 -IH_PERF_SEL_RB1_FULL_VF4 = 177 -IH_PERF_SEL_RB1_FULL_VF5 = 178 -IH_PERF_SEL_RB1_FULL_VF6 = 179 -IH_PERF_SEL_RB1_FULL_VF7 = 180 -IH_PERF_SEL_RB1_FULL_VF8 = 181 -IH_PERF_SEL_RB1_FULL_VF9 = 182 -IH_PERF_SEL_RB1_FULL_VF10 = 183 -IH_PERF_SEL_RB1_FULL_VF11 = 184 -IH_PERF_SEL_RB1_FULL_VF12 = 185 -IH_PERF_SEL_RB1_FULL_VF13 = 186 -IH_PERF_SEL_RB1_FULL_VF14 = 187 -IH_PERF_SEL_RB1_FULL_VF15 = 188 -IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189 -IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190 -IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191 -IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192 -IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193 -IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194 -IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195 -IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196 -IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197 -IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198 -IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199 -IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200 -IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201 -IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202 -IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203 -IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204 -IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205 -IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206 -IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207 -IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208 -IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209 -IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210 -IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211 -IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212 -IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213 -IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214 -IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215 -IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216 -IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217 -IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218 -IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219 -IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220 -IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221 -IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222 -IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223 -IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224 -IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225 -IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226 -IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227 -IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228 -IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229 -IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230 -IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231 -IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232 -IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233 -IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234 -IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235 -IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236 -IH_PERF_SEL_RB2_FULL_VF0 = 237 -IH_PERF_SEL_RB2_FULL_VF1 = 238 -IH_PERF_SEL_RB2_FULL_VF2 = 239 -IH_PERF_SEL_RB2_FULL_VF3 = 240 -IH_PERF_SEL_RB2_FULL_VF4 = 241 -IH_PERF_SEL_RB2_FULL_VF5 = 242 -IH_PERF_SEL_RB2_FULL_VF6 = 243 -IH_PERF_SEL_RB2_FULL_VF7 = 244 -IH_PERF_SEL_RB2_FULL_VF8 = 245 -IH_PERF_SEL_RB2_FULL_VF9 = 246 -IH_PERF_SEL_RB2_FULL_VF10 = 247 -IH_PERF_SEL_RB2_FULL_VF11 = 248 -IH_PERF_SEL_RB2_FULL_VF12 = 249 -IH_PERF_SEL_RB2_FULL_VF13 = 250 -IH_PERF_SEL_RB2_FULL_VF14 = 251 -IH_PERF_SEL_RB2_FULL_VF15 = 252 -IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253 -IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254 -IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255 -IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256 -IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257 -IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258 -IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259 -IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260 -IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261 -IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262 -IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263 -IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264 -IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265 -IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266 -IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267 -IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268 -IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269 -IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270 -IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271 -IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272 -IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273 -IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274 -IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275 -IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276 -IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277 -IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278 -IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279 -IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280 -IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281 -IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282 -IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283 -IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284 -IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285 -IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286 -IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287 -IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288 -IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289 -IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290 -IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291 -IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292 -IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293 -IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294 -IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295 -IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296 -IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297 -IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298 -IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299 -IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316 -IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333 -IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350 -IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351 -IH_PERF_SEL_RB0_LOAD_RPTR = 352 -IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353 -IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354 -IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355 -IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356 -IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357 -IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358 -IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359 -IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360 -IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361 -IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362 -IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363 -IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364 -IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365 -IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366 -IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367 -IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368 -IH_PERF_SEL_RB1_LOAD_RPTR = 369 -IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370 -IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371 -IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372 -IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373 -IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374 -IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375 -IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376 -IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377 -IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378 -IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379 -IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380 -IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381 -IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382 -IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383 -IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384 -IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385 -IH_PERF_SEL_RB2_LOAD_RPTR = 386 -IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387 -IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388 -IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389 -IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390 -IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391 -IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392 -IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393 -IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394 -IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395 -IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396 -IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397 -IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398 -IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399 -IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400 -IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401 -IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402 -IH_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'IH_RING_ID' -IH_RING_ID__enumvalues = { - 0: 'IH_RING_ID_INTERRUPT', - 1: 'IH_RING_ID_REQUEST', - 2: 'IH_RING_ID_TRANSLATION', - 3: 'IH_RING_ID_RESERVED', -} -IH_RING_ID_INTERRUPT = 0 -IH_RING_ID_REQUEST = 1 -IH_RING_ID_TRANSLATION = 2 -IH_RING_ID_RESERVED = 3 -IH_RING_ID = ctypes.c_uint32 # enum - -# values for enumeration 'IH_VF_RB_SELECT' -IH_VF_RB_SELECT__enumvalues = { - 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 1: 'IH_VF_RB_SELECT_IH_FCN_ID', - 2: 'IH_VF_RB_SELECT_PF', - 3: 'IH_VF_RB_SELECT_RESERVED', -} -IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 -IH_VF_RB_SELECT_IH_FCN_ID = 1 -IH_VF_RB_SELECT_PF = 2 -IH_VF_RB_SELECT_RESERVED = 3 -IH_VF_RB_SELECT = ctypes.c_uint32 # enum - -# values for enumeration 'SEM_PERF_SEL' -SEM_PERF_SEL__enumvalues = { - 0: 'SEM_PERF_SEL_CYCLE', - 1: 'SEM_PERF_SEL_IDLE', - 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', - 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', - 4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', - 5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', - 6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', - 7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', - 8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', - 9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', - 10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', - 11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', - 12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', - 13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', - 14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', - 15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT', - 26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT', - 27: 'SEM_PERF_SEL_UVD_REQ_WAIT', - 28: 'SEM_PERF_SEL_UVD1_REQ_WAIT', - 29: 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 30: 'SEM_PERF_SEL_ACP_REQ_WAIT', - 31: 'SEM_PERF_SEL_ISP_REQ_WAIT', - 32: 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 33: 'SEM_PERF_SEL_VP8_REQ_WAIT', - 34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 172: 'SEM_PERF_SEL_MC_RD_REQ', - 173: 'SEM_PERF_SEL_MC_RD_RET', - 174: 'SEM_PERF_SEL_MC_WR_REQ', - 175: 'SEM_PERF_SEL_MC_WR_RET', - 176: 'SEM_PERF_SEL_ATC_REQ', - 177: 'SEM_PERF_SEL_ATC_RET', - 178: 'SEM_PERF_SEL_ATC_XNACK', - 179: 'SEM_PERF_SEL_ATC_INVALIDATION', - 180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', -} -SEM_PERF_SEL_CYCLE = 0 -SEM_PERF_SEL_IDLE = 1 -SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 -SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 -SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4 -SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5 -SEM_PERF_SEL_UVD_REQ_SIGNAL = 6 -SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7 -SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8 -SEM_PERF_SEL_ACP_REQ_SIGNAL = 9 -SEM_PERF_SEL_ISP_REQ_SIGNAL = 10 -SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11 -SEM_PERF_SEL_VP8_REQ_SIGNAL = 12 -SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13 -SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22 -SEM_PERF_SEL_SDMA0_REQ_WAIT = 23 -SEM_PERF_SEL_SDMA1_REQ_WAIT = 24 -SEM_PERF_SEL_SDMA2_REQ_WAIT = 25 -SEM_PERF_SEL_SDMA3_REQ_WAIT = 26 -SEM_PERF_SEL_UVD_REQ_WAIT = 27 -SEM_PERF_SEL_UVD1_REQ_WAIT = 28 -SEM_PERF_SEL_VCE0_REQ_WAIT = 29 -SEM_PERF_SEL_ACP_REQ_WAIT = 30 -SEM_PERF_SEL_ISP_REQ_WAIT = 31 -SEM_PERF_SEL_VCE1_REQ_WAIT = 32 -SEM_PERF_SEL_VP8_REQ_WAIT = 33 -SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34 -SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35 -SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36 -SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37 -SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38 -SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39 -SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40 -SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41 -SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42 -SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43 -SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44 -SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45 -SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46 -SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47 -SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48 -SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49 -SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50 -SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51 -SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52 -SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53 -SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54 -SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55 -SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56 -SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57 -SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58 -SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59 -SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60 -SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61 -SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62 -SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63 -SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64 -SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65 -SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66 -SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67 -SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68 -SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69 -SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70 -SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71 -SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72 -SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73 -SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74 -SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75 -SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76 -SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77 -SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78 -SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79 -SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80 -SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81 -SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82 -SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83 -SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84 -SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85 -SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86 -SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87 -SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88 -SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89 -SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90 -SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91 -SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92 -SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93 -SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94 -SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95 -SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96 -SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97 -SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98 -SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99 -SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100 -SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101 -SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102 -SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103 -SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104 -SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105 -SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106 -SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107 -SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108 -SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109 -SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110 -SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111 -SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112 -SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113 -SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114 -SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115 -SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116 -SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117 -SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118 -SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119 -SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120 -SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121 -SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122 -SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123 -SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124 -SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125 -SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126 -SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127 -SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128 -SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129 -SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130 -SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131 -SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132 -SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133 -SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134 -SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135 -SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136 -SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137 -SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138 -SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139 -SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140 -SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141 -SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142 -SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143 -SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144 -SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145 -SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146 -SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147 -SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148 -SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149 -SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150 -SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151 -SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152 -SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153 -SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154 -SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155 -SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156 -SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157 -SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158 -SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159 -SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160 -SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161 -SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162 -SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163 -SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164 -SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165 -SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166 -SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167 -SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168 -SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169 -SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170 -SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171 -SEM_PERF_SEL_MC_RD_REQ = 172 -SEM_PERF_SEL_MC_RD_RET = 173 -SEM_PERF_SEL_MC_WR_REQ = 174 -SEM_PERF_SEL_MC_WR_RET = 175 -SEM_PERF_SEL_ATC_REQ = 176 -SEM_PERF_SEL_ATC_RET = 177 -SEM_PERF_SEL_ATC_XNACK = 178 -SEM_PERF_SEL_ATC_INVALIDATION = 179 -SEM_PERF_SEL_ATC_VM_INVALIDATION = 180 -SEM_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'LSDMA_PERF_SEL' -LSDMA_PERF_SEL__enumvalues = { - 0: 'LSDMA_PERF_SEL_CYCLE', - 1: 'LSDMA_PERF_SEL_IDLE', - 2: 'LSDMA_PERF_SEL_REG_IDLE', - 3: 'LSDMA_PERF_SEL_RB_EMPTY', - 4: 'LSDMA_PERF_SEL_RB_FULL', - 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', - 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', - 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', - 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', - 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', - 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', - 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', - 13: 'LSDMA_PERF_SEL_EX_IDLE', - 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', - 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', - 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', - 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', - 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', - 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 24: 'LSDMA_PERF_SEL_SEM_IDLE', - 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', - 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', - 30: 'LSDMA_PERF_SEL_INT_IDLE', - 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', - 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 35: 'LSDMA_PERF_SEL_NUM_PACKET', - 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', - 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', - 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', - 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', - 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', - 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', - 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', - 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', - 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 51: 'LSDMA_PERF_SEL_CE_RD_STALL', - 52: 'LSDMA_PERF_SEL_CE_WR_STALL', - 53: 'LSDMA_PERF_SEL_GFX_SELECT', - 54: 'LSDMA_PERF_SEL_RLC0_SELECT', - 55: 'LSDMA_PERF_SEL_RLC1_SELECT', - 56: 'LSDMA_PERF_SEL_PAGE_SELECT', - 57: 'LSDMA_PERF_SEL_CTX_CHANGE', - 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', - 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 60: 'LSDMA_PERF_SEL_DOORBELL', - 61: 'LSDMA_PERF_SEL_RD_BA_RTR', - 62: 'LSDMA_PERF_SEL_WR_BA_RTR', - 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 65: 'LSDMA_PERF_SEL_CE_L1_STALL', - 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', - 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', - 72: 'LSDMA_PERF_SEL_ATCL2_FREE', - 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', - 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', - 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', - 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', - 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', - 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', - 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', - 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', - 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', - 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', - 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', - 110: 'LSDMA_PERF_SEL_CMD_OP_START', - 111: 'LSDMA_PERF_SEL_CMD_OP_END', - 112: 'LSDMA_PERF_SEL_CE_BUSY', - 113: 'LSDMA_PERF_SEL_CE_BUSY_START', - 114: 'LSDMA_PERF_SEL_CE_BUSY_END', - 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 122: 'LSDMA_PERF_SEL_DRAM_ECC', - 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', -} -LSDMA_PERF_SEL_CYCLE = 0 -LSDMA_PERF_SEL_IDLE = 1 -LSDMA_PERF_SEL_REG_IDLE = 2 -LSDMA_PERF_SEL_RB_EMPTY = 3 -LSDMA_PERF_SEL_RB_FULL = 4 -LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 -LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 -LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 -LSDMA_PERF_SEL_RB_RPTR_WB = 8 -LSDMA_PERF_SEL_RB_CMD_IDLE = 9 -LSDMA_PERF_SEL_RB_CMD_FULL = 10 -LSDMA_PERF_SEL_IB_CMD_IDLE = 11 -LSDMA_PERF_SEL_IB_CMD_FULL = 12 -LSDMA_PERF_SEL_EX_IDLE = 13 -LSDMA_PERF_SEL_SRBM_REG_SEND = 14 -LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 -LSDMA_PERF_SEL_MC_WR_IDLE = 16 -LSDMA_PERF_SEL_MC_WR_COUNT = 17 -LSDMA_PERF_SEL_MC_RD_IDLE = 18 -LSDMA_PERF_SEL_MC_RD_COUNT = 19 -LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 -LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 -LSDMA_PERF_SEL_SEM_IDLE = 24 -LSDMA_PERF_SEL_SEM_REQ_STALL = 25 -LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 -LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 -LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 -LSDMA_PERF_SEL_SEM_RESP_PASS = 29 -LSDMA_PERF_SEL_INT_IDLE = 30 -LSDMA_PERF_SEL_INT_REQ_STALL = 31 -LSDMA_PERF_SEL_INT_REQ_COUNT = 32 -LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 -LSDMA_PERF_SEL_INT_RESP_RETRY = 34 -LSDMA_PERF_SEL_NUM_PACKET = 35 -LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 -LSDMA_PERF_SEL_CE_WR_IDLE = 38 -LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 -LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 -LSDMA_PERF_SEL_CE_OUT_IDLE = 41 -LSDMA_PERF_SEL_CE_IN_IDLE = 42 -LSDMA_PERF_SEL_CE_DST_IDLE = 43 -LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 -LSDMA_PERF_SEL_CE_INFO_FULL = 49 -LSDMA_PERF_SEL_CE_INFO1_FULL = 50 -LSDMA_PERF_SEL_CE_RD_STALL = 51 -LSDMA_PERF_SEL_CE_WR_STALL = 52 -LSDMA_PERF_SEL_GFX_SELECT = 53 -LSDMA_PERF_SEL_RLC0_SELECT = 54 -LSDMA_PERF_SEL_RLC1_SELECT = 55 -LSDMA_PERF_SEL_PAGE_SELECT = 56 -LSDMA_PERF_SEL_CTX_CHANGE = 57 -LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 -LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 -LSDMA_PERF_SEL_DOORBELL = 60 -LSDMA_PERF_SEL_RD_BA_RTR = 61 -LSDMA_PERF_SEL_WR_BA_RTR = 62 -LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 -LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 -LSDMA_PERF_SEL_CE_L1_STALL = 65 -LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 -LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 -LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 -LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 -LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 -LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 -LSDMA_PERF_SEL_ATCL2_FREE = 72 -LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 -LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 -LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 -LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 -LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 -LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 -LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 -LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 -LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 -LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 -LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 -LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 -LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 -LSDMA_PERF_SEL_L1_WR_INV_EN = 86 -LSDMA_PERF_SEL_L1_RD_INV_EN = 87 -LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 -LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 -LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 -LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 -LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 -LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 -LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 -LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 -LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 -LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 -LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 -LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 -LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 -LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 -LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 -LSDMA_PERF_SEL_CMD_OP_MATCH = 109 -LSDMA_PERF_SEL_CMD_OP_START = 110 -LSDMA_PERF_SEL_CMD_OP_END = 111 -LSDMA_PERF_SEL_CE_BUSY = 112 -LSDMA_PERF_SEL_CE_BUSY_START = 113 -LSDMA_PERF_SEL_CE_BUSY_END = 114 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 -LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 -LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 -LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 -LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 -LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 -LSDMA_PERF_SEL_DRAM_ECC = 122 -LSDMA_PERF_SEL_NACK_GEN_ERR = 123 -LSDMA_PERF_SEL = ctypes.c_uint32 # enum - -# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' -EFC_SURFACE_PIXEL_FORMAT__enumvalues = { - 1: 'EFC_ARGB1555', - 2: 'EFC_RGBA5551', - 3: 'EFC_RGB565', - 4: 'EFC_BGR565', - 5: 'EFC_ARGB4444', - 6: 'EFC_RGBA4444', - 8: 'EFC_ARGB8888', - 9: 'EFC_RGBA8888', - 10: 'EFC_ARGB2101010', - 11: 'EFC_RGBA1010102', - 12: 'EFC_AYCrCb8888', - 13: 'EFC_YCrCbA8888', - 14: 'EFC_ACrYCb8888', - 15: 'EFC_CrYCbA8888', - 16: 'EFC_ARGB16161616_10MSB', - 17: 'EFC_RGBA16161616_10MSB', - 18: 'EFC_ARGB16161616_10LSB', - 19: 'EFC_RGBA16161616_10LSB', - 20: 'EFC_ARGB16161616_12MSB', - 21: 'EFC_RGBA16161616_12MSB', - 22: 'EFC_ARGB16161616_12LSB', - 23: 'EFC_RGBA16161616_12LSB', - 24: 'EFC_ARGB16161616_FLOAT', - 25: 'EFC_RGBA16161616_FLOAT', - 26: 'EFC_ARGB16161616_UNORM', - 27: 'EFC_RGBA16161616_UNORM', - 28: 'EFC_ARGB16161616_SNORM', - 29: 'EFC_RGBA16161616_SNORM', - 32: 'EFC_AYCrCb16161616_10MSB', - 33: 'EFC_AYCrCb16161616_10LSB', - 34: 'EFC_YCrCbA16161616_10MSB', - 35: 'EFC_YCrCbA16161616_10LSB', - 36: 'EFC_ACrYCb16161616_10MSB', - 37: 'EFC_ACrYCb16161616_10LSB', - 38: 'EFC_CrYCbA16161616_10MSB', - 39: 'EFC_CrYCbA16161616_10LSB', - 40: 'EFC_AYCrCb16161616_12MSB', - 41: 'EFC_AYCrCb16161616_12LSB', - 42: 'EFC_YCrCbA16161616_12MSB', - 43: 'EFC_YCrCbA16161616_12LSB', - 44: 'EFC_ACrYCb16161616_12MSB', - 45: 'EFC_ACrYCb16161616_12LSB', - 46: 'EFC_CrYCbA16161616_12MSB', - 47: 'EFC_CrYCbA16161616_12LSB', - 64: 'EFC_Y8_CrCb88_420_PLANAR', - 65: 'EFC_Y8_CbCr88_420_PLANAR', - 66: 'EFC_Y10_CrCb1010_420_PLANAR', - 67: 'EFC_Y10_CbCr1010_420_PLANAR', - 68: 'EFC_Y12_CrCb1212_420_PLANAR', - 69: 'EFC_Y12_CbCr1212_420_PLANAR', - 72: 'EFC_YCrYCb8888_422_PACKED', - 73: 'EFC_YCbYCr8888_422_PACKED', - 74: 'EFC_CrYCbY8888_422_PACKED', - 75: 'EFC_CbYCrY8888_422_PACKED', - 76: 'EFC_YCrYCb10101010_422_PACKED', - 77: 'EFC_YCbYCr10101010_422_PACKED', - 78: 'EFC_CrYCbY10101010_422_PACKED', - 79: 'EFC_CbYCrY10101010_422_PACKED', - 80: 'EFC_YCrYCb12121212_422_PACKED', - 81: 'EFC_YCbYCr12121212_422_PACKED', - 82: 'EFC_CrYCbY12121212_422_PACKED', - 83: 'EFC_CbYCrY12121212_422_PACKED', - 112: 'EFC_RGB111110_FIX', - 113: 'EFC_BGR101111_FIX', - 114: 'EFC_ACrYCb2101010', - 115: 'EFC_CrYCbA1010102', - 118: 'EFC_RGB111110_FLOAT', - 119: 'EFC_BGR101111_FLOAT', - 120: 'EFC_MONO_8', - 121: 'EFC_MONO_10MSB', - 122: 'EFC_MONO_10LSB', - 123: 'EFC_MONO_12MSB', - 124: 'EFC_MONO_12LSB', - 125: 'EFC_MONO_16', -} -EFC_ARGB1555 = 1 -EFC_RGBA5551 = 2 -EFC_RGB565 = 3 -EFC_BGR565 = 4 -EFC_ARGB4444 = 5 -EFC_RGBA4444 = 6 -EFC_ARGB8888 = 8 -EFC_RGBA8888 = 9 -EFC_ARGB2101010 = 10 -EFC_RGBA1010102 = 11 -EFC_AYCrCb8888 = 12 -EFC_YCrCbA8888 = 13 -EFC_ACrYCb8888 = 14 -EFC_CrYCbA8888 = 15 -EFC_ARGB16161616_10MSB = 16 -EFC_RGBA16161616_10MSB = 17 -EFC_ARGB16161616_10LSB = 18 -EFC_RGBA16161616_10LSB = 19 -EFC_ARGB16161616_12MSB = 20 -EFC_RGBA16161616_12MSB = 21 -EFC_ARGB16161616_12LSB = 22 -EFC_RGBA16161616_12LSB = 23 -EFC_ARGB16161616_FLOAT = 24 -EFC_RGBA16161616_FLOAT = 25 -EFC_ARGB16161616_UNORM = 26 -EFC_RGBA16161616_UNORM = 27 -EFC_ARGB16161616_SNORM = 28 -EFC_RGBA16161616_SNORM = 29 -EFC_AYCrCb16161616_10MSB = 32 -EFC_AYCrCb16161616_10LSB = 33 -EFC_YCrCbA16161616_10MSB = 34 -EFC_YCrCbA16161616_10LSB = 35 -EFC_ACrYCb16161616_10MSB = 36 -EFC_ACrYCb16161616_10LSB = 37 -EFC_CrYCbA16161616_10MSB = 38 -EFC_CrYCbA16161616_10LSB = 39 -EFC_AYCrCb16161616_12MSB = 40 -EFC_AYCrCb16161616_12LSB = 41 -EFC_YCrCbA16161616_12MSB = 42 -EFC_YCrCbA16161616_12LSB = 43 -EFC_ACrYCb16161616_12MSB = 44 -EFC_ACrYCb16161616_12LSB = 45 -EFC_CrYCbA16161616_12MSB = 46 -EFC_CrYCbA16161616_12LSB = 47 -EFC_Y8_CrCb88_420_PLANAR = 64 -EFC_Y8_CbCr88_420_PLANAR = 65 -EFC_Y10_CrCb1010_420_PLANAR = 66 -EFC_Y10_CbCr1010_420_PLANAR = 67 -EFC_Y12_CrCb1212_420_PLANAR = 68 -EFC_Y12_CbCr1212_420_PLANAR = 69 -EFC_YCrYCb8888_422_PACKED = 72 -EFC_YCbYCr8888_422_PACKED = 73 -EFC_CrYCbY8888_422_PACKED = 74 -EFC_CbYCrY8888_422_PACKED = 75 -EFC_YCrYCb10101010_422_PACKED = 76 -EFC_YCbYCr10101010_422_PACKED = 77 -EFC_CrYCbY10101010_422_PACKED = 78 -EFC_CbYCrY10101010_422_PACKED = 79 -EFC_YCrYCb12121212_422_PACKED = 80 -EFC_YCbYCr12121212_422_PACKED = 81 -EFC_CrYCbY12121212_422_PACKED = 82 -EFC_CbYCrY12121212_422_PACKED = 83 -EFC_RGB111110_FIX = 112 -EFC_BGR101111_FIX = 113 -EFC_ACrYCb2101010 = 114 -EFC_CrYCbA1010102 = 115 -EFC_RGB111110_FLOAT = 118 -EFC_BGR101111_FLOAT = 119 -EFC_MONO_8 = 120 -EFC_MONO_10MSB = 121 -EFC_MONO_10LSB = 122 -EFC_MONO_12MSB = 123 -EFC_MONO_12LSB = 124 -EFC_MONO_16 = 125 -EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum -__SDMA_V6_0_0_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_GPUVM_INV = 16 # macro -SDMA_OP_GCR_REQ = 17 # macro -SDMA_OP_DUMMY_TRAP = 32 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 # macro -SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro -SDMA_SUBOP_COPY_TILED_BC = 17 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_WRITE_TILED_BC = 17 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_MEM_INCR = 1 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -SDMA_SUBOP_VM_INVALIDATION = 4 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_GCR_RANGE_IS_PA = (1<<18) # macro -def SDMA_GCR_SEQ(x): # macro - return (((x)&0x3)<<16) -SDMA_GCR_GL2_WB = (1<<15) # macro -SDMA_GCR_GL2_INV = (1<<14) # macro -SDMA_GCR_GL2_DISCARD = (1<<13) # macro -def SDMA_GCR_GL2_RANGE(x): # macro - return (((x)&0x3)<<11) -SDMA_GCR_GL2_US = (1<<10) # macro -SDMA_GCR_GL1_INV = (1<<9) # macro -SDMA_GCR_GLV_INV = (1<<8) # macro -SDMA_GCR_GLK_INV = (1<<7) # macro -SDMA_GCR_GLK_WB = (1<<6) # macro -SDMA_GCR_GLM_INV = (1<<5) # macro -SDMA_GCR_GLM_WB = (1<<4) # macro -def SDMA_GCR_GL1_RANGE(x): # macro - return (((x)&0x3)<<2) -def SDMA_GCR_GLI_INV(x): # macro - return (((x)&0x3)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x): # macro - return (((x)&0x000000FF)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_T2T_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<22) -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro -SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro -def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_MEM_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_MEM_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro - return (((x)&0x0000001F)<<24) -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro - return (((x)&0x000001FF)<<23) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_FENCE_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro -def SDMA_PKT_FENCE_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro -def SDMA_PKT_FENCE_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_FENCE_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_FENCE_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_FENCE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_FENCE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COND_EXE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_ATOMIC_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro - return (((x)&0x00000001)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro - return (((x)&0x7FFFFFFF)<<1) -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro - return (((x)&0x0000003F)<<0) -SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro -def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_HEADER_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x): # macro - return (((x)&0x00000007)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x): # macro - return (((x)&0x00000007)<<5) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x): # macro - return (((x)&0x00000007)<<10) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x): # macro - return (((x)&0x00000007)<<15) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -_gc_11_0_0_OFFSET_HEADER = True # macro -regSDMA0_DEC_START = 0x0000 # macro -regSDMA0_DEC_START_BASE_IDX = 0 # macro -regSDMA0_F32_MISC_CNTL = 0x000b # macro -regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro -regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro -regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -regSDMA0_POWER_CNTL = 0x001a # macro -regSDMA0_POWER_CNTL_BASE_IDX = 0 # macro -regSDMA0_CNTL = 0x001c # macro -regSDMA0_CNTL_BASE_IDX = 0 # macro -regSDMA0_CHICKEN_BITS = 0x001d # macro -regSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro -regSDMA0_GB_ADDR_CONFIG = 0x001e # macro -regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -regSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro -regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regSDMA0_RB_RPTR_FETCH = 0x0020 # macro -regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro -regSDMA0_RB_RPTR_FETCH_HI = 0x0021 # macro -regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 # macro -regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -regSDMA0_IB_OFFSET_FETCH = 0x0023 # macro -regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -regSDMA0_PROGRAM = 0x0024 # macro -regSDMA0_PROGRAM_BASE_IDX = 0 # macro -regSDMA0_STATUS_REG = 0x0025 # macro -regSDMA0_STATUS_REG_BASE_IDX = 0 # macro -regSDMA0_STATUS1_REG = 0x0026 # macro -regSDMA0_STATUS1_REG_BASE_IDX = 0 # macro -regSDMA0_CNTL1 = 0x0027 # macro -regSDMA0_CNTL1_BASE_IDX = 0 # macro -regSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro -regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -regSDMA0_UCODE_CHECKSUM = 0x0029 # macro -regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro -regSDMA0_FREEZE = 0x002b # macro -regSDMA0_FREEZE_BASE_IDX = 0 # macro -regSDMA0_PROCESS_QUANTUM0 = 0x002c # macro -regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 # macro -regSDMA0_PROCESS_QUANTUM1 = 0x002d # macro -regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 # macro -regSDMA0_WATCHDOG_CNTL = 0x002e # macro -regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE_STATUS0 = 0x002f # macro -regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 # macro -regSDMA0_EDC_CONFIG = 0x0032 # macro -regSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro -regSDMA0_BA_THRESHOLD = 0x0033 # macro -regSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro -regSDMA0_ID = 0x0034 # macro -regSDMA0_ID_BASE_IDX = 0 # macro -regSDMA0_VERSION = 0x0035 # macro -regSDMA0_VERSION_BASE_IDX = 0 # macro -regSDMA0_EDC_COUNTER = 0x0036 # macro -regSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro -regSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro -regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -regSDMA0_STATUS2_REG = 0x0038 # macro -regSDMA0_STATUS2_REG_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_CNTL = 0x0039 # macro -regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_PREOP_LO = 0x003a # macro -regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_PREOP_HI = 0x003b # macro -regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -regSDMA0_UTCL1_CNTL = 0x003c # macro -regSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WATERMK = 0x003d # macro -regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro -regSDMA0_UTCL1_TIMEOUT = 0x003e # macro -regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -regSDMA0_UTCL1_PAGE = 0x003f # macro -regSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_STATUS = 0x0040 # macro -regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_STATUS = 0x0041 # macro -regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV0 = 0x0042 # macro -regSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV1 = 0x0043 # macro -regSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV2 = 0x0044 # macro -regSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_XNACK0 = 0x0045 # macro -regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_XNACK1 = 0x0046 # macro -regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_XNACK0 = 0x0047 # macro -regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_XNACK1 = 0x0048 # macro -regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -regSDMA0_RELAX_ORDERING_LUT = 0x004a # macro -regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -regSDMA0_CHICKEN_BITS_2 = 0x004b # macro -regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro -regSDMA0_STATUS3_REG = 0x004c # macro -regSDMA0_STATUS3_REG_BASE_IDX = 0 # macro -regSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro -regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro -regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_QUANTUM = 0x004f # macro -regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 # macro -regSDMA0_ERROR_LOG = 0x0050 # macro -regSDMA0_ERROR_LOG_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro -regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro -regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro -regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro -regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -regSDMA0_F32_COUNTER = 0x0055 # macro -regSDMA0_F32_COUNTER_BASE_IDX = 0 # macro -regSDMA0_CRD_CNTL = 0x005b # macro -regSDMA0_CRD_CNTL_BASE_IDX = 0 # macro -regSDMA0_RLC_CGCG_CTRL = 0x005c # macro -regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 # macro -regSDMA0_AQL_STATUS = 0x005f # macro -regSDMA0_AQL_STATUS_BASE_IDX = 0 # macro -regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro -regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro -regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -regSDMA0_TLBI_GCR_CNTL = 0x0062 # macro -regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -regSDMA0_TILING_CONFIG = 0x0063 # macro -regSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro -regSDMA0_INT_STATUS = 0x0070 # macro -regSDMA0_INT_STATUS_BASE_IDX = 0 # macro -regSDMA0_HOLE_ADDR_LO = 0x0072 # macro -regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_HOLE_ADDR_HI = 0x0073 # macro -regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_CLOCK_GATING_STATUS = 0x0075 # macro -regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro -regSDMA0_STATUS4_REG = 0x0076 # macro -regSDMA0_STATUS4_REG_BASE_IDX = 0 # macro -regSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro -regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -regSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro -regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -regSDMA0_TIMESTAMP_CNTL = 0x0079 # macro -regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -regSDMA0_STATUS5_REG = 0x007a # macro -regSDMA0_STATUS5_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE_RESET_REQ = 0x007b # macro -regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -regSDMA0_STATUS6_REG = 0x007c # macro -regSDMA0_STATUS6_REG_BASE_IDX = 0 # macro -regSDMA0_UCODE1_CHECKSUM = 0x007d # macro -regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 # macro -regSDMA0_CE_CTRL = 0x007e # macro -regSDMA0_CE_CTRL_BASE_IDX = 0 # macro -regSDMA0_FED_STATUS = 0x007f # macro -regSDMA0_FED_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_CNTL = 0x0080 # macro -regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_BASE = 0x0081 # macro -regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 # macro -regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR = 0x0083 # macro -regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 # macro -regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR = 0x0085 # macro -regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 # macro -regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_CNTL = 0x008a # macro -regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_RPTR = 0x008b # macro -regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_OFFSET = 0x008c # macro -regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_BASE_LO = 0x008d # macro -regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_BASE_HI = 0x008e # macro -regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_SIZE = 0x008f # macro -regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 # macro -regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 # macro -regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL = 0x0092 # macro -regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 # macro -regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab # macro -regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac # macro -regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad # macro -regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae # macro -regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af # macro -regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_PREEMPT = 0x00b0 # macro -regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 # macro -regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 # macro -regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 # macro -regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 # macro -regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 # macro -regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 # macro -regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 # macro -regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 # macro -regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 # macro -regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 # macro -regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 # macro -regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 # macro -regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 # macro -regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca # macro -regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb # macro -regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_CNTL = 0x00d8 # macro -regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_BASE = 0x00d9 # macro -regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_BASE_HI = 0x00da # macro -regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR = 0x00db # macro -regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc # macro -regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR = 0x00dd # macro -regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de # macro -regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_CNTL = 0x00e2 # macro -regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_RPTR = 0x00e3 # macro -regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 # macro -regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 # macro -regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 # macro -regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_SIZE = 0x00e7 # macro -regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 # macro -regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 # macro -regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL = 0x00ea # macro -regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 # macro -regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 # macro -regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 # macro -regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 # macro -regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 # macro -regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 # macro -regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_PREEMPT = 0x0108 # macro -regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DUMMY_REG = 0x0109 # macro -regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c # macro -regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d # macro -regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_PREEMPT = 0x010e # macro -regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 # macro -regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 # macro -regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a # macro -regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b # macro -regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c # macro -regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d # macro -regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e # macro -regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f # macro -regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 # macro -regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 # macro -regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 # macro -regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 # macro -regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_CNTL = 0x0130 # macro -regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_BASE = 0x0131 # macro -regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 # macro -regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR = 0x0133 # macro -regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 # macro -regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR = 0x0135 # macro -regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 # macro -regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_CNTL = 0x013a # macro -regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_RPTR = 0x013b # macro -regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_OFFSET = 0x013c # macro -regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_BASE_LO = 0x013d # macro -regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_BASE_HI = 0x013e # macro -regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_SIZE = 0x013f # macro -regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 # macro -regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 # macro -regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL = 0x0142 # macro -regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 # macro -regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b # macro -regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c # macro -regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d # macro -regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e # macro -regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f # macro -regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_PREEMPT = 0x0160 # macro -regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DUMMY_REG = 0x0161 # macro -regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 # macro -regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 # macro -regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 # macro -regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 # macro -regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 # macro -regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 # macro -regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 # macro -regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 # macro -regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 # macro -regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 # macro -regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 # macro -regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 # macro -regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 # macro -regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a # macro -regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b # macro -regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_CNTL = 0x0188 # macro -regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_BASE = 0x0189 # macro -regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_BASE_HI = 0x018a # macro -regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR = 0x018b # macro -regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c # macro -regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR = 0x018d # macro -regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e # macro -regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_CNTL = 0x0192 # macro -regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_RPTR = 0x0193 # macro -regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_OFFSET = 0x0194 # macro -regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 # macro -regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 # macro -regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_SIZE = 0x0197 # macro -regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 # macro -regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 # macro -regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL = 0x019a # macro -regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 # macro -regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 # macro -regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 # macro -regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 # macro -regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 # macro -regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 # macro -regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_PREEMPT = 0x01b8 # macro -regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 # macro -regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc # macro -regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd # macro -regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_PREEMPT = 0x01be # macro -regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 # macro -regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 # macro -regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca # macro -regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb # macro -regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc # macro -regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd # macro -regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce # macro -regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf # macro -regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 # macro -regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 # macro -regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 # macro -regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_CNTL = 0x01e0 # macro -regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_BASE = 0x01e1 # macro -regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 # macro -regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR = 0x01e3 # macro -regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 # macro -regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR = 0x01e5 # macro -regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 # macro -regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_CNTL = 0x01ea # macro -regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_RPTR = 0x01eb # macro -regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_OFFSET = 0x01ec # macro -regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed # macro -regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee # macro -regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_SIZE = 0x01ef # macro -regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 # macro -regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 # macro -regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL = 0x01f2 # macro -regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 # macro -regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b # macro -regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c # macro -regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d # macro -regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e # macro -regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f # macro -regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_PREEMPT = 0x0210 # macro -regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DUMMY_REG = 0x0211 # macro -regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 # macro -regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 # macro -regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 # macro -regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 # macro -regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 # macro -regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 # macro -regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 # macro -regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 # macro -regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 # macro -regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 # macro -regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 # macro -regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 # macro -regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 # macro -regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a # macro -regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b # macro -regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_CNTL = 0x0238 # macro -regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_BASE = 0x0239 # macro -regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_BASE_HI = 0x023a # macro -regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR = 0x023b # macro -regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c # macro -regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR = 0x023d # macro -regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e # macro -regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_CNTL = 0x0242 # macro -regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_RPTR = 0x0243 # macro -regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_OFFSET = 0x0244 # macro -regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 # macro -regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 # macro -regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_SIZE = 0x0247 # macro -regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 # macro -regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 # macro -regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL = 0x024a # macro -regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 # macro -regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 # macro -regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 # macro -regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 # macro -regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 # macro -regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 # macro -regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_PREEMPT = 0x0268 # macro -regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DUMMY_REG = 0x0269 # macro -regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c # macro -regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d # macro -regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_PREEMPT = 0x026e # macro -regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 # macro -regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 # macro -regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a # macro -regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b # macro -regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c # macro -regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d # macro -regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e # macro -regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f # macro -regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 # macro -regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 # macro -regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 # macro -regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 # macro -regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_CNTL = 0x0290 # macro -regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_BASE = 0x0291 # macro -regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 # macro -regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR = 0x0293 # macro -regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 # macro -regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR = 0x0295 # macro -regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 # macro -regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_CNTL = 0x029a # macro -regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_RPTR = 0x029b # macro -regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_OFFSET = 0x029c # macro -regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_BASE_LO = 0x029d # macro -regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_BASE_HI = 0x029e # macro -regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_SIZE = 0x029f # macro -regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 # macro -regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 # macro -regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL = 0x02a2 # macro -regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 # macro -regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb # macro -regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc # macro -regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd # macro -regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be # macro -regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf # macro -regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_PREEMPT = 0x02c0 # macro -regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 # macro -regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 # macro -regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 # macro -regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 # macro -regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 # macro -regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 # macro -regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 # macro -regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 # macro -regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 # macro -regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 # macro -regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 # macro -regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 # macro -regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 # macro -regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da # macro -regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db # macro -regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_CNTL = 0x02e8 # macro -regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_BASE = 0x02e9 # macro -regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea # macro -regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR = 0x02eb # macro -regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec # macro -regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR = 0x02ed # macro -regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee # macro -regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_CNTL = 0x02f2 # macro -regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_RPTR = 0x02f3 # macro -regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 # macro -regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 # macro -regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 # macro -regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_SIZE = 0x02f7 # macro -regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 # macro -regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 # macro -regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL = 0x02fa # macro -regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 # macro -regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 # macro -regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 # macro -regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 # macro -regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 # macro -regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 # macro -regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_PREEMPT = 0x0318 # macro -regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DUMMY_REG = 0x0319 # macro -regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c # macro -regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d # macro -regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_PREEMPT = 0x031e # macro -regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 # macro -regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 # macro -regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a # macro -regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b # macro -regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c # macro -regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d # macro -regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e # macro -regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f # macro -regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 # macro -regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 # macro -regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 # macro -regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 # macro -regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_DEC_START = 0x0600 # macro -regSDMA1_DEC_START_BASE_IDX = 0 # macro -regSDMA1_F32_MISC_CNTL = 0x060b # macro -regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro -regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro -regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -regSDMA1_POWER_CNTL = 0x061a # macro -regSDMA1_POWER_CNTL_BASE_IDX = 0 # macro -regSDMA1_CNTL = 0x061c # macro -regSDMA1_CNTL_BASE_IDX = 0 # macro -regSDMA1_CHICKEN_BITS = 0x061d # macro -regSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro -regSDMA1_GB_ADDR_CONFIG = 0x061e # macro -regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -regSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro -regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regSDMA1_RB_RPTR_FETCH = 0x0620 # macro -regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro -regSDMA1_RB_RPTR_FETCH_HI = 0x0621 # macro -regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 # macro -regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -regSDMA1_IB_OFFSET_FETCH = 0x0623 # macro -regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -regSDMA1_PROGRAM = 0x0624 # macro -regSDMA1_PROGRAM_BASE_IDX = 0 # macro -regSDMA1_STATUS_REG = 0x0625 # macro -regSDMA1_STATUS_REG_BASE_IDX = 0 # macro -regSDMA1_STATUS1_REG = 0x0626 # macro -regSDMA1_STATUS1_REG_BASE_IDX = 0 # macro -regSDMA1_CNTL1 = 0x0627 # macro -regSDMA1_CNTL1_BASE_IDX = 0 # macro -regSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro -regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -regSDMA1_UCODE_CHECKSUM = 0x0629 # macro -regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro -regSDMA1_FREEZE = 0x062b # macro -regSDMA1_FREEZE_BASE_IDX = 0 # macro -regSDMA1_PROCESS_QUANTUM0 = 0x062c # macro -regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 # macro -regSDMA1_PROCESS_QUANTUM1 = 0x062d # macro -regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 # macro -regSDMA1_WATCHDOG_CNTL = 0x062e # macro -regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE_STATUS0 = 0x062f # macro -regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 # macro -regSDMA1_EDC_CONFIG = 0x0632 # macro -regSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro -regSDMA1_BA_THRESHOLD = 0x0633 # macro -regSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro -regSDMA1_ID = 0x0634 # macro -regSDMA1_ID_BASE_IDX = 0 # macro -regSDMA1_VERSION = 0x0635 # macro -regSDMA1_VERSION_BASE_IDX = 0 # macro -regSDMA1_EDC_COUNTER = 0x0636 # macro -regSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro -regSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro -regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -regSDMA1_STATUS2_REG = 0x0638 # macro -regSDMA1_STATUS2_REG_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_CNTL = 0x0639 # macro -regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_PREOP_LO = 0x063a # macro -regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_PREOP_HI = 0x063b # macro -regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -regSDMA1_UTCL1_CNTL = 0x063c # macro -regSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WATERMK = 0x063d # macro -regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro -regSDMA1_UTCL1_TIMEOUT = 0x063e # macro -regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -regSDMA1_UTCL1_PAGE = 0x063f # macro -regSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_STATUS = 0x0640 # macro -regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_STATUS = 0x0641 # macro -regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV0 = 0x0642 # macro -regSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV1 = 0x0643 # macro -regSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV2 = 0x0644 # macro -regSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_XNACK0 = 0x0645 # macro -regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_XNACK1 = 0x0646 # macro -regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_XNACK0 = 0x0647 # macro -regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_XNACK1 = 0x0648 # macro -regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -regSDMA1_RELAX_ORDERING_LUT = 0x064a # macro -regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -regSDMA1_CHICKEN_BITS_2 = 0x064b # macro -regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro -regSDMA1_STATUS3_REG = 0x064c # macro -regSDMA1_STATUS3_REG_BASE_IDX = 0 # macro -regSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro -regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro -regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_QUANTUM = 0x064f # macro -regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 # macro -regSDMA1_ERROR_LOG = 0x0650 # macro -regSDMA1_ERROR_LOG_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro -regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro -regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro -regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro -regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -regSDMA1_F32_COUNTER = 0x0655 # macro -regSDMA1_F32_COUNTER_BASE_IDX = 0 # macro -regSDMA1_CRD_CNTL = 0x065b # macro -regSDMA1_CRD_CNTL_BASE_IDX = 0 # macro -regSDMA1_RLC_CGCG_CTRL = 0x065c # macro -regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 # macro -regSDMA1_AQL_STATUS = 0x065f # macro -regSDMA1_AQL_STATUS_BASE_IDX = 0 # macro -regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro -regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro -regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -regSDMA1_TLBI_GCR_CNTL = 0x0662 # macro -regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -regSDMA1_TILING_CONFIG = 0x0663 # macro -regSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro -regSDMA1_INT_STATUS = 0x0670 # macro -regSDMA1_INT_STATUS_BASE_IDX = 0 # macro -regSDMA1_HOLE_ADDR_LO = 0x0672 # macro -regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_HOLE_ADDR_HI = 0x0673 # macro -regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_CLOCK_GATING_STATUS = 0x0675 # macro -regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro -regSDMA1_STATUS4_REG = 0x0676 # macro -regSDMA1_STATUS4_REG_BASE_IDX = 0 # macro -regSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro -regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -regSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro -regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -regSDMA1_TIMESTAMP_CNTL = 0x0679 # macro -regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -regSDMA1_STATUS5_REG = 0x067a # macro -regSDMA1_STATUS5_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE_RESET_REQ = 0x067b # macro -regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -regSDMA1_STATUS6_REG = 0x067c # macro -regSDMA1_STATUS6_REG_BASE_IDX = 0 # macro -regSDMA1_UCODE1_CHECKSUM = 0x067d # macro -regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 # macro -regSDMA1_CE_CTRL = 0x067e # macro -regSDMA1_CE_CTRL_BASE_IDX = 0 # macro -regSDMA1_FED_STATUS = 0x067f # macro -regSDMA1_FED_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_CNTL = 0x0680 # macro -regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_BASE = 0x0681 # macro -regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 # macro -regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR = 0x0683 # macro -regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 # macro -regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR = 0x0685 # macro -regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 # macro -regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_CNTL = 0x068a # macro -regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_RPTR = 0x068b # macro -regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_OFFSET = 0x068c # macro -regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_BASE_LO = 0x068d # macro -regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_BASE_HI = 0x068e # macro -regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_SIZE = 0x068f # macro -regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 # macro -regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 # macro -regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL = 0x0692 # macro -regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 # macro -regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab # macro -regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac # macro -regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad # macro -regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae # macro -regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af # macro -regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_PREEMPT = 0x06b0 # macro -regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 # macro -regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 # macro -regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 # macro -regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 # macro -regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 # macro -regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 # macro -regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 # macro -regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 # macro -regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 # macro -regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 # macro -regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 # macro -regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 # macro -regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 # macro -regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca # macro -regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb # macro -regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_CNTL = 0x06d8 # macro -regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_BASE = 0x06d9 # macro -regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_BASE_HI = 0x06da # macro -regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR = 0x06db # macro -regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc # macro -regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR = 0x06dd # macro -regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de # macro -regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_CNTL = 0x06e2 # macro -regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_RPTR = 0x06e3 # macro -regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 # macro -regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 # macro -regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 # macro -regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_SIZE = 0x06e7 # macro -regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 # macro -regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 # macro -regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL = 0x06ea # macro -regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 # macro -regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 # macro -regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 # macro -regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 # macro -regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 # macro -regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 # macro -regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_PREEMPT = 0x0708 # macro -regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DUMMY_REG = 0x0709 # macro -regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c # macro -regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d # macro -regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_PREEMPT = 0x070e # macro -regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 # macro -regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 # macro -regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a # macro -regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b # macro -regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c # macro -regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d # macro -regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e # macro -regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f # macro -regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 # macro -regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 # macro -regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 # macro -regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 # macro -regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_CNTL = 0x0730 # macro -regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_BASE = 0x0731 # macro -regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 # macro -regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR = 0x0733 # macro -regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 # macro -regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR = 0x0735 # macro -regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 # macro -regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_CNTL = 0x073a # macro -regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_RPTR = 0x073b # macro -regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_OFFSET = 0x073c # macro -regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_BASE_LO = 0x073d # macro -regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_BASE_HI = 0x073e # macro -regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_SIZE = 0x073f # macro -regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 # macro -regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 # macro -regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL = 0x0742 # macro -regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 # macro -regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b # macro -regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c # macro -regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d # macro -regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e # macro -regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f # macro -regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_PREEMPT = 0x0760 # macro -regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DUMMY_REG = 0x0761 # macro -regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 # macro -regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 # macro -regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 # macro -regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 # macro -regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 # macro -regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 # macro -regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 # macro -regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 # macro -regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 # macro -regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 # macro -regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 # macro -regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 # macro -regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 # macro -regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a # macro -regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b # macro -regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_CNTL = 0x0788 # macro -regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_BASE = 0x0789 # macro -regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_BASE_HI = 0x078a # macro -regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR = 0x078b # macro -regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c # macro -regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR = 0x078d # macro -regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e # macro -regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_CNTL = 0x0792 # macro -regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_RPTR = 0x0793 # macro -regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_OFFSET = 0x0794 # macro -regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 # macro -regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 # macro -regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_SIZE = 0x0797 # macro -regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 # macro -regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 # macro -regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL = 0x079a # macro -regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 # macro -regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 # macro -regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 # macro -regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 # macro -regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 # macro -regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 # macro -regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_PREEMPT = 0x07b8 # macro -regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 # macro -regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc # macro -regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd # macro -regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_PREEMPT = 0x07be # macro -regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 # macro -regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 # macro -regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca # macro -regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb # macro -regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc # macro -regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd # macro -regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce # macro -regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf # macro -regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 # macro -regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 # macro -regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 # macro -regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_CNTL = 0x07e0 # macro -regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_BASE = 0x07e1 # macro -regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 # macro -regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR = 0x07e3 # macro -regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 # macro -regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR = 0x07e5 # macro -regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 # macro -regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_CNTL = 0x07ea # macro -regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_RPTR = 0x07eb # macro -regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_OFFSET = 0x07ec # macro -regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed # macro -regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee # macro -regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_SIZE = 0x07ef # macro -regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 # macro -regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 # macro -regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL = 0x07f2 # macro -regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 # macro -regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b # macro -regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c # macro -regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d # macro -regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e # macro -regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f # macro -regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_PREEMPT = 0x0810 # macro -regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DUMMY_REG = 0x0811 # macro -regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 # macro -regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 # macro -regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 # macro -regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 # macro -regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 # macro -regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 # macro -regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 # macro -regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 # macro -regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 # macro -regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 # macro -regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 # macro -regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 # macro -regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 # macro -regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a # macro -regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b # macro -regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_CNTL = 0x0838 # macro -regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_BASE = 0x0839 # macro -regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_BASE_HI = 0x083a # macro -regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR = 0x083b # macro -regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c # macro -regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR = 0x083d # macro -regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e # macro -regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_CNTL = 0x0842 # macro -regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_RPTR = 0x0843 # macro -regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_OFFSET = 0x0844 # macro -regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 # macro -regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 # macro -regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_SIZE = 0x0847 # macro -regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 # macro -regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 # macro -regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL = 0x084a # macro -regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 # macro -regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 # macro -regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 # macro -regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 # macro -regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 # macro -regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 # macro -regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_PREEMPT = 0x0868 # macro -regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DUMMY_REG = 0x0869 # macro -regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c # macro -regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d # macro -regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_PREEMPT = 0x086e # macro -regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 # macro -regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 # macro -regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a # macro -regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b # macro -regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c # macro -regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d # macro -regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e # macro -regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f # macro -regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 # macro -regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 # macro -regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 # macro -regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 # macro -regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_CNTL = 0x0890 # macro -regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_BASE = 0x0891 # macro -regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 # macro -regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR = 0x0893 # macro -regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 # macro -regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR = 0x0895 # macro -regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 # macro -regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_CNTL = 0x089a # macro -regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_RPTR = 0x089b # macro -regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_OFFSET = 0x089c # macro -regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_BASE_LO = 0x089d # macro -regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_BASE_HI = 0x089e # macro -regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_SIZE = 0x089f # macro -regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 # macro -regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 # macro -regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL = 0x08a2 # macro -regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 # macro -regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb # macro -regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc # macro -regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd # macro -regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be # macro -regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf # macro -regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_PREEMPT = 0x08c0 # macro -regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 # macro -regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 # macro -regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 # macro -regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 # macro -regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 # macro -regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 # macro -regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 # macro -regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 # macro -regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 # macro -regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 # macro -regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 # macro -regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 # macro -regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 # macro -regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da # macro -regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db # macro -regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_CNTL = 0x08e8 # macro -regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_BASE = 0x08e9 # macro -regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea # macro -regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR = 0x08eb # macro -regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec # macro -regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR = 0x08ed # macro -regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee # macro -regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_CNTL = 0x08f2 # macro -regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_RPTR = 0x08f3 # macro -regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 # macro -regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 # macro -regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 # macro -regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_SIZE = 0x08f7 # macro -regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 # macro -regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 # macro -regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL = 0x08fa # macro -regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 # macro -regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 # macro -regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 # macro -regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 # macro -regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 # macro -regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 # macro -regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_PREEMPT = 0x0918 # macro -regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DUMMY_REG = 0x0919 # macro -regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c # macro -regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d # macro -regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_PREEMPT = 0x091e # macro -regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 # macro -regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 # macro -regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a # macro -regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b # macro -regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c # macro -regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d # macro -regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e # macro -regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f # macro -regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 # macro -regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 # macro -regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 # macro -regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 # macro -regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_UCODE_ADDR = 0x5880 # macro -regSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA0_UCODE_DATA = 0x5881 # macro -regSDMA0_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 # macro -regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro -regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 # macro -regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA0_BROADCAST_UCODE_DATA = 0x5887 # macro -regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA0_F32_CNTL = 0x589a # macro -regSDMA0_F32_CNTL_BASE_IDX = 1 # macro -regSDMA1_UCODE_ADDR = 0x58a0 # macro -regSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA1_UCODE_DATA = 0x58a1 # macro -regSDMA1_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 # macro -regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro -regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 # macro -regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 # macro -regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA1_F32_CNTL = 0x58ba # macro -regSDMA1_F32_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro -regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro -regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro -regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro -regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro -regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro -regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro -regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro -regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro -regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro -regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro -regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro -regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro -regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro -regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro -regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro -regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro -regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro -regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_LO = 0x3662 # macro -regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_HI = 0x3663 # macro -regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_LO = 0x3664 # macro -regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_HI = 0x3665 # macro -regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro -regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro -regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_LO = 0x366e # macro -regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_HI = 0x366f # macro -regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_LO = 0x3670 # macro -regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_HI = 0x3671 # macro -regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGRBM_CNTL = 0x0da0 # macro -regGRBM_CNTL_BASE_IDX = 0 # macro -regGRBM_SKEW_CNTL = 0x0da1 # macro -regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro -regGRBM_STATUS2 = 0x0da2 # macro -regGRBM_STATUS2_BASE_IDX = 0 # macro -regGRBM_PWR_CNTL = 0x0da3 # macro -regGRBM_PWR_CNTL_BASE_IDX = 0 # macro -regGRBM_STATUS = 0x0da4 # macro -regGRBM_STATUS_BASE_IDX = 0 # macro -regGRBM_STATUS_SE0 = 0x0da5 # macro -regGRBM_STATUS_SE0_BASE_IDX = 0 # macro -regGRBM_STATUS_SE1 = 0x0da6 # macro -regGRBM_STATUS_SE1_BASE_IDX = 0 # macro -regGRBM_STATUS3 = 0x0da7 # macro -regGRBM_STATUS3_BASE_IDX = 0 # macro -regGRBM_SOFT_RESET = 0x0da8 # macro -regGRBM_SOFT_RESET_BASE_IDX = 0 # macro -regGRBM_GFX_CLKEN_CNTL = 0x0dac # macro -regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro -regGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro -regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro -regGRBM_STATUS_SE2 = 0x0dae # macro -regGRBM_STATUS_SE2_BASE_IDX = 0 # macro -regGRBM_STATUS_SE3 = 0x0daf # macro -regGRBM_STATUS_SE3_BASE_IDX = 0 # macro -regGRBM_STATUS_SE4 = 0x0db0 # macro -regGRBM_STATUS_SE4_BASE_IDX = 0 # macro -regGRBM_STATUS_SE5 = 0x0db1 # macro -regGRBM_STATUS_SE5_BASE_IDX = 0 # macro -regGRBM_READ_ERROR = 0x0db6 # macro -regGRBM_READ_ERROR_BASE_IDX = 0 # macro -regGRBM_READ_ERROR2 = 0x0db7 # macro -regGRBM_READ_ERROR2_BASE_IDX = 0 # macro -regGRBM_INT_CNTL = 0x0db8 # macro -regGRBM_INT_CNTL_BASE_IDX = 0 # macro -regGRBM_TRAP_OP = 0x0db9 # macro -regGRBM_TRAP_OP_BASE_IDX = 0 # macro -regGRBM_TRAP_ADDR = 0x0dba # macro -regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro -regGRBM_TRAP_ADDR_MSK = 0x0dbb # macro -regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro -regGRBM_TRAP_WD = 0x0dbc # macro -regGRBM_TRAP_WD_BASE_IDX = 0 # macro -regGRBM_TRAP_WD_MSK = 0x0dbd # macro -regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro -regGRBM_DSM_BYPASS = 0x0dbe # macro -regGRBM_DSM_BYPASS_BASE_IDX = 0 # macro -regGRBM_WRITE_ERROR = 0x0dbf # macro -regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro -regGRBM_CHIP_REVISION = 0x0dc1 # macro -regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro -regGRBM_IH_CREDIT = 0x0dc4 # macro -regGRBM_IH_CREDIT_BASE_IDX = 0 # macro -regGRBM_PWR_CNTL2 = 0x0dc5 # macro -regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro -regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro -regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro -regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro -regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro -regGRBM_INVALID_PIPE = 0x0dc9 # macro -regGRBM_INVALID_PIPE_BASE_IDX = 0 # macro -regGRBM_FENCE_RANGE0 = 0x0dca # macro -regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro -regGRBM_FENCE_RANGE1 = 0x0dcb # macro -regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG0 = 0x0de0 # macro -regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG1 = 0x0de1 # macro -regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG2 = 0x0de2 # macro -regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG3 = 0x0de3 # macro -regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG4 = 0x0de4 # macro -regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG5 = 0x0de5 # macro -regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG6 = 0x0de6 # macro -regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG7 = 0x0de7 # macro -regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro -regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro -regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro -regCP_CPC_DEBUG_CNTL = 0x0e20 # macro -regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro -regCP_CPC_DEBUG_DATA = 0x0e21 # macro -regCP_CPC_DEBUG_DATA_BASE_IDX = 0 # macro -regCP_CPC_STATUS = 0x0e24 # macro -regCP_CPC_STATUS_BASE_IDX = 0 # macro -regCP_CPC_BUSY_STAT = 0x0e25 # macro -regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro -regCP_CPC_STALLED_STAT1 = 0x0e26 # macro -regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_CPF_STATUS = 0x0e27 # macro -regCP_CPF_STATUS_BASE_IDX = 0 # macro -regCP_CPF_BUSY_STAT = 0x0e28 # macro -regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro -regCP_CPF_STALLED_STAT1 = 0x0e29 # macro -regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_CPC_BUSY_STAT2 = 0x0e2a # macro -regCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro -regCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro -regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro -regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -regCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro -regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro -regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_CPC_SCRATCH_INDEX = 0x0e30 # macro -regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro -regCP_CPC_SCRATCH_DATA = 0x0e31 # macro -regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro -regCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro -regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_CPF_BUSY_STAT2 = 0x0e33 # macro -regCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro -regCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro -regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro -regCP_STALLED_STAT3 = 0x0f3c # macro -regCP_STALLED_STAT3_BASE_IDX = 0 # macro -regCP_STALLED_STAT1 = 0x0f3d # macro -regCP_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_STALLED_STAT2 = 0x0f3e # macro -regCP_STALLED_STAT2_BASE_IDX = 0 # macro -regCP_BUSY_STAT = 0x0f3f # macro -regCP_BUSY_STAT_BASE_IDX = 0 # macro -regCP_STAT = 0x0f40 # macro -regCP_STAT_BASE_IDX = 0 # macro -regCP_ME_HEADER_DUMP = 0x0f41 # macro -regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_PFP_HEADER_DUMP = 0x0f42 # macro -regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_GRBM_FREE_COUNT = 0x0f43 # macro -regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_PFP_INSTR_PNTR = 0x0f45 # macro -regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_ME_INSTR_PNTR = 0x0f46 # macro -regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_MEC1_INSTR_PNTR = 0x0f48 # macro -regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_MEC2_INSTR_PNTR = 0x0f49 # macro -regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_CSF_STAT = 0x0f54 # macro -regCP_CSF_STAT_BASE_IDX = 0 # macro -regCP_CNTX_STAT = 0x0f58 # macro -regCP_CNTX_STAT_BASE_IDX = 0 # macro -regCP_ME_PREEMPTION = 0x0f59 # macro -regCP_ME_PREEMPTION_BASE_IDX = 0 # macro -regCP_RB1_RPTR = 0x0f5f # macro -regCP_RB1_RPTR_BASE_IDX = 0 # macro -regCP_RB0_RPTR = 0x0f60 # macro -regCP_RB0_RPTR_BASE_IDX = 0 # macro -regCP_RB_RPTR = 0x0f60 # macro -regCP_RB_RPTR_BASE_IDX = 0 # macro -regCP_RB_WPTR_DELAY = 0x0f61 # macro -regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro -regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -regCP_ROQ1_THRESHOLDS = 0x0f75 # macro -regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ2_THRESHOLDS = 0x0f76 # macro -regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro -regCP_STQ_THRESHOLDS = 0x0f77 # macro -regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro -regCP_MEQ_THRESHOLDS = 0x0f79 # macro -regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ_AVAIL = 0x0f7a # macro -regCP_ROQ_AVAIL_BASE_IDX = 0 # macro -regCP_STQ_AVAIL = 0x0f7b # macro -regCP_STQ_AVAIL_BASE_IDX = 0 # macro -regCP_ROQ2_AVAIL = 0x0f7c # macro -regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro -regCP_MEQ_AVAIL = 0x0f7d # macro -regCP_MEQ_AVAIL_BASE_IDX = 0 # macro -regCP_CMD_INDEX = 0x0f7e # macro -regCP_CMD_INDEX_BASE_IDX = 0 # macro -regCP_CMD_DATA = 0x0f7f # macro -regCP_CMD_DATA_BASE_IDX = 0 # macro -regCP_ROQ_RB_STAT = 0x0f80 # macro -regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro -regCP_ROQ_IB1_STAT = 0x0f81 # macro -regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro -regCP_ROQ_IB2_STAT = 0x0f82 # macro -regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro -regCP_STQ_STAT = 0x0f83 # macro -regCP_STQ_STAT_BASE_IDX = 0 # macro -regCP_STQ_WR_STAT = 0x0f84 # macro -regCP_STQ_WR_STAT_BASE_IDX = 0 # macro -regCP_MEQ_STAT = 0x0f85 # macro -regCP_MEQ_STAT_BASE_IDX = 0 # macro -regCP_ROQ3_THRESHOLDS = 0x0f8c # macro -regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ_DB_STAT = 0x0f8d # macro -regCP_ROQ_DB_STAT_BASE_IDX = 0 # macro -regCP_DEBUG_CNTL = 0x0f98 # macro -regCP_DEBUG_CNTL_BASE_IDX = 0 # macro -regCP_DEBUG_DATA = 0x0f99 # macro -regCP_DEBUG_DATA_BASE_IDX = 0 # macro -regCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro -regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro -regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro -regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro -regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_MC_LAT_CNTL = 0x0fd6 # macro -regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro -regIA_UTCL1_STATUS_2 = 0x0fd7 # macro -regIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro -regWD_CNTL_STATUS = 0x0fdf # macro -regWD_CNTL_STATUS_BASE_IDX = 0 # macro -regCC_GC_PRIM_CONFIG = 0x0fe0 # macro -regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro -regWD_QOS = 0x0fe2 # macro -regWD_QOS_BASE_IDX = 0 # macro -regWD_UTCL1_CNTL = 0x0fe3 # macro -regWD_UTCL1_CNTL_BASE_IDX = 0 # macro -regWD_UTCL1_STATUS = 0x0fe4 # macro -regWD_UTCL1_STATUS_BASE_IDX = 0 # macro -regIA_UTCL1_CNTL = 0x0fe6 # macro -regIA_UTCL1_CNTL_BASE_IDX = 0 # macro -regIA_UTCL1_STATUS = 0x0fe7 # macro -regIA_UTCL1_STATUS_BASE_IDX = 0 # macro -regCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro -regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro -regGE_RATE_CNTL_1 = 0x0ff4 # macro -regGE_RATE_CNTL_1_BASE_IDX = 0 # macro -regGE_RATE_CNTL_2 = 0x0ff5 # macro -regGE_RATE_CNTL_2_BASE_IDX = 0 # macro -regVGT_SYS_CONFIG = 0x1003 # macro -regVGT_SYS_CONFIG_BASE_IDX = 0 # macro -regGE_PRIV_CONTROL = 0x1004 # macro -regGE_PRIV_CONTROL_BASE_IDX = 0 # macro -regGE_STATUS = 0x1005 # macro -regGE_STATUS_BASE_IDX = 0 # macro -regVGT_GS_MAX_WAVE_ID = 0x1009 # macro -regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro -regGFX_PIPE_CONTROL = 0x100d # macro -regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro -regCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro -regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro -regGE2_SE_CNTL_STATUS = 0x1011 # macro -regGE2_SE_CNTL_STATUS_BASE_IDX = 0 # macro -regGE_SPI_IF_SAFE_REG = 0x1018 # macro -regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 # macro -regGE_PA_IF_SAFE_REG = 0x1019 # macro -regGE_PA_IF_SAFE_REG_BASE_IDX = 0 # macro -regPA_CL_CNTL_STATUS = 0x1024 # macro -regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro -regPA_CL_ENHANCE = 0x1025 # macro -regPA_CL_ENHANCE_BASE_IDX = 0 # macro -regPA_SU_CNTL_STATUS = 0x1034 # macro -regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro -regPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro -regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro -regSQ_CONFIG = 0x10a0 # macro -regSQ_CONFIG_BASE_IDX = 0 # macro -regSQC_CONFIG = 0x10a1 # macro -regSQC_CONFIG_BASE_IDX = 0 # macro -regLDS_CONFIG = 0x10a2 # macro -regLDS_CONFIG_BASE_IDX = 0 # macro -regSQ_RANDOM_WAVE_PRI = 0x10a3 # macro -regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro -regSQG_STATUS = 0x10a4 # macro -regSQG_STATUS_BASE_IDX = 0 # macro -regSQ_FIFO_SIZES = 0x10a5 # macro -regSQ_FIFO_SIZES_BASE_IDX = 0 # macro -regSQ_DSM_CNTL = 0x10a6 # macro -regSQ_DSM_CNTL_BASE_IDX = 0 # macro -regSQ_DSM_CNTL2 = 0x10a7 # macro -regSQ_DSM_CNTL2_BASE_IDX = 0 # macro -regSP_CONFIG = 0x10ab # macro -regSP_CONFIG_BASE_IDX = 0 # macro -regSQ_ARB_CONFIG = 0x10ac # macro -regSQ_ARB_CONFIG_BASE_IDX = 0 # macro -regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 # macro -regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 # macro -regSQG_GL1H_STATUS = 0x10b9 # macro -regSQG_GL1H_STATUS_BASE_IDX = 0 # macro -regSQG_CONFIG = 0x10ba # macro -regSQG_CONFIG_BASE_IDX = 0 # macro -regSQ_PERF_SNAPSHOT_CTRL = 0x10bb # macro -regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro -regCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro -regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro -regSQ_INTERRUPT_AUTO_MASK = 0x10be # macro -regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro -regSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro -regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro -regSQ_WATCH0_ADDR_H = 0x10d0 # macro -regSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH0_ADDR_L = 0x10d1 # macro -regSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH0_CNTL = 0x10d2 # macro -regSQ_WATCH0_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH1_ADDR_H = 0x10d3 # macro -regSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH1_ADDR_L = 0x10d4 # macro -regSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH1_CNTL = 0x10d5 # macro -regSQ_WATCH1_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH2_ADDR_H = 0x10d6 # macro -regSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH2_ADDR_L = 0x10d7 # macro -regSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH2_CNTL = 0x10d8 # macro -regSQ_WATCH2_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH3_ADDR_H = 0x10d9 # macro -regSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH3_ADDR_L = 0x10da # macro -regSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH3_CNTL = 0x10db # macro -regSQ_WATCH3_CNTL_BASE_IDX = 0 # macro -regSQ_IND_INDEX = 0x1118 # macro -regSQ_IND_INDEX_BASE_IDX = 0 # macro -regSQ_IND_DATA = 0x1119 # macro -regSQ_IND_DATA_BASE_IDX = 0 # macro -regSQ_CMD = 0x111b # macro -regSQ_CMD_BASE_IDX = 0 # macro -regSX_DEBUG_1 = 0x11b8 # macro -regSX_DEBUG_1_BASE_IDX = 0 # macro -regSPI_PS_MAX_WAVE_ID = 0x11da # macro -regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro -regSPI_GFX_CNTL = 0x11dc # macro -regSPI_GFX_CNTL_BASE_IDX = 0 # macro -regSPI_DSM_CNTL = 0x11e3 # macro -regSPI_DSM_CNTL_BASE_IDX = 0 # macro -regSPI_DSM_CNTL2 = 0x11e4 # macro -regSPI_DSM_CNTL2_BASE_IDX = 0 # macro -regSPI_EDC_CNT = 0x11e5 # macro -regSPI_EDC_CNT_BASE_IDX = 0 # macro -regSPI_CONFIG_PS_CU_EN = 0x11f2 # macro -regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_CNTL = 0x124a # macro -regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro -regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro -regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro -regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro -regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro -regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro -regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro -regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro -regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro -regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro -regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro -regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro -regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro -regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro -regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro -regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro -regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro -regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro -regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro -regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro -regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro -regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro -regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro -regSPI_LB_CTR_CTRL = 0x1274 # macro -regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro -regSPI_LB_WGP_MASK = 0x1275 # macro -regSPI_LB_WGP_MASK_BASE_IDX = 0 # macro -regSPI_LB_DATA_REG = 0x1276 # macro -regSPI_LB_DATA_REG_BASE_IDX = 0 # macro -regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro -regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro -regSPI_GDS_CREDITS = 0x1278 # macro -regSPI_GDS_CREDITS_BASE_IDX = 0 # macro -regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro -regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro -regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro -regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro -regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro -regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro -regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro -regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro -regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro -regSPI_LB_DATA_WAVES = 0x1284 # macro -regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro -regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro -regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro -regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro -regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro -regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro -regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro -regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro -regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro -regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro -regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -regTD_STATUS = 0x12c6 # macro -regTD_STATUS_BASE_IDX = 0 # macro -regTD_DSM_CNTL = 0x12cf # macro -regTD_DSM_CNTL_BASE_IDX = 0 # macro -regTD_DSM_CNTL2 = 0x12d0 # macro -regTD_DSM_CNTL2_BASE_IDX = 0 # macro -regTD_SCRATCH = 0x12d3 # macro -regTD_SCRATCH_BASE_IDX = 0 # macro -regTA_CNTL = 0x12e1 # macro -regTA_CNTL_BASE_IDX = 0 # macro -regTA_CNTL_AUX = 0x12e2 # macro -regTA_CNTL_AUX_BASE_IDX = 0 # macro -regTA_CNTL2 = 0x12e5 # macro -regTA_CNTL2_BASE_IDX = 0 # macro -regTA_STATUS = 0x12e8 # macro -regTA_STATUS_BASE_IDX = 0 # macro -regTA_SCRATCH = 0x1304 # macro -regTA_SCRATCH_BASE_IDX = 0 # macro -regGDS_CONFIG = 0x1360 # macro -regGDS_CONFIG_BASE_IDX = 0 # macro -regGDS_CNTL_STATUS = 0x1361 # macro -regGDS_CNTL_STATUS_BASE_IDX = 0 # macro -regGDS_ENHANCE = 0x1362 # macro -regGDS_ENHANCE_BASE_IDX = 0 # macro -regGDS_PROTECTION_FAULT = 0x1363 # macro -regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro -regGDS_VM_PROTECTION_FAULT = 0x1364 # macro -regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro -regGDS_EDC_CNT = 0x1365 # macro -regGDS_EDC_CNT_BASE_IDX = 0 # macro -regGDS_EDC_GRBM_CNT = 0x1366 # macro -regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro -regGDS_EDC_OA_DED = 0x1367 # macro -regGDS_EDC_OA_DED_BASE_IDX = 0 # macro -regGDS_DSM_CNTL = 0x136a # macro -regGDS_DSM_CNTL_BASE_IDX = 0 # macro -regGDS_EDC_OA_PHY_CNT = 0x136b # macro -regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro -regGDS_EDC_OA_PIPE_CNT = 0x136c # macro -regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro -regGDS_DSM_CNTL2 = 0x136d # macro -regGDS_DSM_CNTL2_BASE_IDX = 0 # macro -regDB_DEBUG = 0x13ac # macro -regDB_DEBUG_BASE_IDX = 0 # macro -regDB_DEBUG2 = 0x13ad # macro -regDB_DEBUG2_BASE_IDX = 0 # macro -regDB_DEBUG3 = 0x13ae # macro -regDB_DEBUG3_BASE_IDX = 0 # macro -regDB_DEBUG4 = 0x13af # macro -regDB_DEBUG4_BASE_IDX = 0 # macro -regDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro -regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro -regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro -regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro -regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_CREDIT_LIMIT = 0x13b4 # macro -regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro -regDB_WATERMARKS = 0x13b5 # macro -regDB_WATERMARKS_BASE_IDX = 0 # macro -regDB_SUBTILE_CONTROL = 0x13b6 # macro -regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro -regDB_FREE_CACHELINES = 0x13b7 # macro -regDB_FREE_CACHELINES_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH1 = 0x13b8 # macro -regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH2 = 0x13b9 # macro -regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro -regDB_LAST_OF_BURST_CONFIG = 0x13ba # macro -regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro -regDB_RING_CONTROL = 0x13bb # macro -regDB_RING_CONTROL_BASE_IDX = 0 # macro -regDB_MEM_ARB_WATERMARKS = 0x13bc # macro -regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH3 = 0x13bd # macro -regDB_FIFO_DEPTH3_BASE_IDX = 0 # macro -regDB_DEBUG6 = 0x13be # macro -regDB_DEBUG6_BASE_IDX = 0 # macro -regDB_EXCEPTION_CONTROL = 0x13bf # macro -regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro -regDB_DEBUG7 = 0x13d0 # macro -regDB_DEBUG7_BASE_IDX = 0 # macro -regDB_DEBUG5 = 0x13d1 # macro -regDB_DEBUG5_BASE_IDX = 0 # macro -regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro -regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro -regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro -regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH4 = 0x13d9 # macro -regDB_FIFO_DEPTH4_BASE_IDX = 0 # macro -regCC_RB_REDUNDANCY = 0x13dc # macro -regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro -regCC_RB_BACKEND_DISABLE = 0x13dd # macro -regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro -regGB_ADDR_CONFIG = 0x13de # macro -regGB_ADDR_CONFIG_BASE_IDX = 0 # macro -regGB_BACKEND_MAP = 0x13df # macro -regGB_BACKEND_MAP_BASE_IDX = 0 # macro -regGB_GPU_ID = 0x13e0 # macro -regGB_GPU_ID_BASE_IDX = 0 # macro -regCC_RB_DAISY_CHAIN = 0x13e1 # macro -regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro -regGB_ADDR_CONFIG_READ = 0x13e2 # macro -regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regCB_HW_CONTROL_4 = 0x1422 # macro -regCB_HW_CONTROL_4_BASE_IDX = 0 # macro -regCB_HW_CONTROL_3 = 0x1423 # macro -regCB_HW_CONTROL_3_BASE_IDX = 0 # macro -regCB_HW_CONTROL = 0x1424 # macro -regCB_HW_CONTROL_BASE_IDX = 0 # macro -regCB_HW_CONTROL_1 = 0x1425 # macro -regCB_HW_CONTROL_1_BASE_IDX = 0 # macro -regCB_HW_CONTROL_2 = 0x1426 # macro -regCB_HW_CONTROL_2_BASE_IDX = 0 # macro -regCB_DCC_CONFIG = 0x1427 # macro -regCB_DCC_CONFIG_BASE_IDX = 0 # macro -regCB_HW_MEM_ARBITER_RD = 0x1428 # macro -regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro -regCB_HW_MEM_ARBITER_WR = 0x1429 # macro -regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro -regCB_FGCG_SRAM_OVERRIDE = 0x142a # macro -regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 # macro -regCB_DCC_CONFIG2 = 0x142b # macro -regCB_DCC_CONFIG2_BASE_IDX = 0 # macro -regCHICKEN_BITS = 0x142d # macro -regCHICKEN_BITS_BASE_IDX = 0 # macro -regCB_CACHE_EVICT_POINTS = 0x142e # macro -regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro -regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro -regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_LAZY = 0x17a6 # macro -regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_LAZY = 0x17a7 # macro -regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro -regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro -regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro -regGCEA_DRAM_PAGE_BURST = 0x17aa # macro -regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro -regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro -regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro -regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro -regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro -regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro -regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro -regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro -regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro -regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro -regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro -regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro -regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro -regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro -regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro -regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro -regGCEA_IO_GROUP_BURST = 0x1883 # macro -regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_AGE = 0x1884 # macro -regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_AGE = 0x1885 # macro -regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro -regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro -regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_FIXED = 0x1888 # macro -regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_FIXED = 0x1889 # macro -regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_URGENCY = 0x188a # macro -regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_URGENCY = 0x188b # macro -regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro -regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro -regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro -regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro -regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro -regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro -regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro -regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro -regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_SDP_ARB_FINAL = 0x1896 # macro -regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro -regGCEA_SDP_IO_PRIORITY = 0x1899 # macro -regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro -regGCEA_SDP_CREDITS = 0x189a # macro -regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro -regGCEA_SDP_TAG_RESERVE0 = 0x189b # macro -regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro -regGCEA_SDP_TAG_RESERVE1 = 0x189c # macro -regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro -regGCEA_SDP_VCC_RESERVE0 = 0x189d # macro -regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro -regGCEA_SDP_VCC_RESERVE1 = 0x189e # macro -regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro -regGCEA_MISC = 0x14a2 # macro -regGCEA_MISC_BASE_IDX = 0 # macro -regGCEA_LATENCY_SAMPLING = 0x14a3 # macro -regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro -regGCEA_MAM_CTRL2 = 0x14a9 # macro -regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro -regGCEA_MAM_CTRL = 0x14ab # macro -regGCEA_MAM_CTRL_BASE_IDX = 0 # macro -regGCEA_EDC_CNT = 0x14b2 # macro -regGCEA_EDC_CNT_BASE_IDX = 0 # macro -regGCEA_EDC_CNT2 = 0x14b3 # macro -regGCEA_EDC_CNT2_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL = 0x14b4 # macro -regGCEA_DSM_CNTL_BASE_IDX = 0 # macro -regGCEA_DSM_CNTLA = 0x14b5 # macro -regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro -regGCEA_DSM_CNTLB = 0x14b6 # macro -regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2 = 0x14b7 # macro -regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2A = 0x14b8 # macro -regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2B = 0x14b9 # macro -regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro -regGCEA_GL2C_XBR_CREDITS = 0x14ba # macro -regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro -regGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro -regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro -regGCEA_PROBE_CNTL = 0x14bc # macro -regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro -regGCEA_PROBE_MAP = 0x14bd # macro -regGCEA_PROBE_MAP_BASE_IDX = 0 # macro -regGCEA_ERR_STATUS = 0x14be # macro -regGCEA_ERR_STATUS_BASE_IDX = 0 # macro -regGCEA_MISC2 = 0x14bf # macro -regGCEA_MISC2_BASE_IDX = 0 # macro -regGCEA_RRET_MEM_RESERVE = 0x1518 # macro -regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro -regGCEA_EDC_CNT3 = 0x151a # macro -regGCEA_EDC_CNT3_BASE_IDX = 0 # macro -regGCEA_SDP_ENABLE = 0x151e # macro -regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro -regSPI_PQEV_CTRL = 0x14c0 # macro -regSPI_PQEV_CTRL_BASE_IDX = 0 # macro -regSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro -regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro -regRMI_GENERAL_CNTL = 0x1880 # macro -regRMI_GENERAL_CNTL_BASE_IDX = 1 # macro -regRMI_GENERAL_CNTL1 = 0x1881 # macro -regRMI_GENERAL_CNTL1_BASE_IDX = 1 # macro -regRMI_GENERAL_STATUS = 0x1882 # macro -regRMI_GENERAL_STATUS_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS0 = 0x1883 # macro -regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS1 = 0x1884 # macro -regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS2 = 0x1885 # macro -regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS3 = 0x1886 # macro -regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 # macro -regRMI_XBAR_CONFIG = 0x1887 # macro -regRMI_XBAR_CONFIG_BASE_IDX = 1 # macro -regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 # macro -regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 # macro -regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 # macro -regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 # macro -regRMI_DEMUX_CNTL = 0x188a # macro -regRMI_DEMUX_CNTL_BASE_IDX = 1 # macro -regRMI_UTCL1_CNTL1 = 0x188b # macro -regRMI_UTCL1_CNTL1_BASE_IDX = 1 # macro -regRMI_UTCL1_CNTL2 = 0x188c # macro -regRMI_UTCL1_CNTL2_BASE_IDX = 1 # macro -regRMI_UTC_UNIT_CONFIG = 0x188d # macro -regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 # macro -regRMI_TCIW_FORMATTER0_CNTL = 0x188e # macro -regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 # macro -regRMI_TCIW_FORMATTER1_CNTL = 0x188f # macro -regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_CNTL = 0x1890 # macro -regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS0 = 0x1891 # macro -regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS1 = 0x1892 # macro -regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS2 = 0x1893 # macro -regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 # macro -regRMI_XBAR_ARBITER_CONFIG = 0x1894 # macro -regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 # macro -regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 # macro -regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 # macro -regRMI_CLOCK_CNTRL = 0x1896 # macro -regRMI_CLOCK_CNTRL_BASE_IDX = 1 # macro -regRMI_UTCL1_STATUS = 0x1897 # macro -regRMI_UTCL1_STATUS_BASE_IDX = 1 # macro -regRMI_RB_GLX_CID_MAP = 0x1898 # macro -regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 # macro -regRMI_SPARE = 0x189f # macro -regRMI_SPARE_BASE_IDX = 1 # macro -regRMI_SPARE_1 = 0x18a0 # macro -regRMI_SPARE_1_BASE_IDX = 1 # macro -regRMI_SPARE_2 = 0x18a1 # macro -regRMI_SPARE_2_BASE_IDX = 1 # macro -regCC_RMI_REDUNDANCY = 0x18a2 # macro -regCC_RMI_REDUNDANCY_BASE_IDX = 1 # macro -regGCR_PIO_CNTL = 0x1580 # macro -regGCR_PIO_CNTL_BASE_IDX = 0 # macro -regGCR_PIO_DATA = 0x1581 # macro -regGCR_PIO_DATA_BASE_IDX = 0 # macro -regPMM_CNTL = 0x1582 # macro -regPMM_CNTL_BASE_IDX = 0 # macro -regPMM_STATUS = 0x1583 # macro -regPMM_STATUS_BASE_IDX = 0 # macro -regUTCL1_CTRL_1 = 0x158c # macro -regUTCL1_CTRL_1_BASE_IDX = 0 # macro -regUTCL1_ALOG = 0x158f # macro -regUTCL1_ALOG_BASE_IDX = 0 # macro -regUTCL1_STATUS = 0x1594 # macro -regUTCL1_STATUS_BASE_IDX = 0 # macro -regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 # macro -regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro -regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 # macro -regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 # macro -regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -regGCMC_VM_FB_OFFSET = 0x15a7 # macro -regGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro -regGCMC_VM_STEERING = 0x15aa # macro -regGCMC_VM_STEERING_BASE_IDX = 0 # macro -regGCMC_MEM_POWER_LS = 0x15ac # macro -regGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_APT_CNTL = 0x15b1 # macro -regGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro -regGCUTCL2_ICG_CTRL = 0x15b5 # macro -regGCUTCL2_ICG_CTRL_BASE_IDX = 0 # macro -regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 # macro -regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro -regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 # macro -regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro -regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 # macro -regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro -regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb # macro -regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro -regGCVM_L2_CNTL = 0x15bc # macro -regGCVM_L2_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_CNTL2 = 0x15bd # macro -regGCVM_L2_CNTL2_BASE_IDX = 0 # macro -regGCVM_L2_CNTL3 = 0x15be # macro -regGCVM_L2_CNTL3_BASE_IDX = 0 # macro -regGCVM_L2_STATUS = 0x15bf # macro -regGCVM_L2_STATUS_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro -regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_CNTL = 0x15c3 # macro -regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro -regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CNTL4 = 0x15d4 # macro -regGCVM_L2_CNTL4_BASE_IDX = 0 # macro -regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro -regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro -regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro -regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_ICG_CTRL = 0x15d9 # macro -regGCVM_L2_ICG_CTRL_BASE_IDX = 0 # macro -regGCVM_L2_CNTL5 = 0x15da # macro -regGCVM_L2_CNTL5_BASE_IDX = 0 # macro -regGCVM_L2_GCR_CNTL = 0x15db # macro -regGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro -regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc # macro -regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro -regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd # macro -regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de # macro -regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro -regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df # macro -regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 # macro -regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro -regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 # macro -regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 # macro -regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 # macro -regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro -regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed # macro -regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro -regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee # macro -regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro -regGCMC_VM_FB_LOCATION_BASE = 0x1678 # macro -regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro -regGCMC_VM_FB_LOCATION_TOP = 0x1679 # macro -regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro -regGCMC_VM_AGP_TOP = 0x167a # macro -regGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro -regGCMC_VM_AGP_BOT = 0x167b # macro -regGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro -regGCMC_VM_AGP_BASE = 0x167c # macro -regGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d # macro -regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e # macro -regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro -regGCMC_VM_MX_L1_TLB_CNTL = 0x167f # macro -regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_CNTL = 0x1688 # macro -regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_CNTL = 0x1689 # macro -regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_CNTL = 0x168a # macro -regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_CNTL = 0x168b # macro -regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_CNTL = 0x168c # macro -regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_CNTL = 0x168d # macro -regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_CNTL = 0x168e # macro -regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_CNTL = 0x168f # macro -regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_CNTL = 0x1690 # macro -regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_CNTL = 0x1691 # macro -regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_CNTL = 0x1692 # macro -regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_CNTL = 0x1693 # macro -regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_CNTL = 0x1694 # macro -regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_CNTL = 0x1695 # macro -regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_CNTL = 0x1696 # macro -regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_CNTL = 0x1697 # macro -regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXTS_DISABLE = 0x1698 # macro -regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_SEM = 0x1699 # macro -regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_SEM = 0x169a # macro -regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_SEM = 0x169b # macro -regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_SEM = 0x169c # macro -regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_SEM = 0x169d # macro -regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_SEM = 0x169e # macro -regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_SEM = 0x169f # macro -regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 # macro -regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 # macro -regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 # macro -regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 # macro -regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 # macro -regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 # macro -regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 # macro -regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 # macro -regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 # macro -regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 # macro -regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_SEM = 0x16aa # macro -regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_REQ = 0x16ab # macro -regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_REQ = 0x16ac # macro -regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_REQ = 0x16ad # macro -regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_REQ = 0x16ae # macro -regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_REQ = 0x16af # macro -regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 # macro -regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 # macro -regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 # macro -regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 # macro -regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 # macro -regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 # macro -regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 # macro -regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 # macro -regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 # macro -regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 # macro -regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_REQ = 0x16ba # macro -regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_REQ = 0x16bb # macro -regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_REQ = 0x16bc # macro -regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ACK = 0x16bd # macro -regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ACK = 0x16be # macro -regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ACK = 0x16bf # macro -regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 # macro -regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 # macro -regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 # macro -regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 # macro -regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 # macro -regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 # macro -regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 # macro -regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 # macro -regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 # macro -regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 # macro -regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ACK = 0x16ca # macro -regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ACK = 0x16cb # macro -regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ACK = 0x16cc # macro -regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ACK = 0x16cd # macro -regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ACK = 0x16ce # macro -regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 # macro -regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 # macro -regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 # macro -regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 # macro -regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 # macro -regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 # macro -regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 # macro -regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a # macro -regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b # macro -regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c # macro -regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d # macro -regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e # macro -regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f # macro -regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 # macro -regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 # macro -regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 # macro -regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 # macro -regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 # macro -regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 # macro -regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 # macro -regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 # macro -regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 # macro -regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 # macro -regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_LO = 0x34e6 # macro -regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_HI = 0x34e7 # macro -regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 # macro -regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 # macro -regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 # macro -regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 # macro -regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 # macro -regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 # macro -regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 # macro -regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 # macro -regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 # macro -regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 # macro -regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 # macro -regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 # macro -regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 # macro -regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 # macro -regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 # macro -regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 # macro -regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a # macro -regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b # macro -regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c # macro -regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d # macro -regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro -regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro -regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro -regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro -regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro -regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro -regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro -regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 # macro -regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 # macro -regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 # macro -regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a # macro -regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b # macro -regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c # macro -regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d # macro -regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e # macro -regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f # macro -regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 # macro -regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 # macro -regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 # macro -regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 # macro -regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 # macro -regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 # macro -regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 # macro -regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 # macro -regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 # macro -regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 # macro -regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a # macro -regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b # macro -regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c # macro -regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d # macro -regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e # macro -regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f # macro -regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 # macro -regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 # macro -regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 # macro -regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 # macro -regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 # macro -regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 # macro -regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 # macro -regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 # macro -regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 # macro -regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 # macro -regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a # macro -regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b # macro -regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c # macro -regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d # macro -regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e # macro -regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f # macro -regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 # macro -regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 # macro -regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 # macro -regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 # macro -regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 # macro -regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 # macro -regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 # macro -regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 # macro -regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 # macro -regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 # macro -regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a # macro -regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b # macro -regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c # macro -regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d # macro -regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e # macro -regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f # macro -regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 # macro -regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 # macro -regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 # macro -regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 # macro -regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 # macro -regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 # macro -regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 # macro -regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 # macro -regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 # macro -regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 # macro -regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a # macro -regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b # macro -regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c # macro -regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d # macro -regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e # macro -regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f # macro -regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 # macro -regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 # macro -regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 # macro -regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 # macro -regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 # macro -regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 # macro -regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 # macro -regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 # macro -regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 # macro -regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 # macro -regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a # macro -regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b # macro -regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c # macro -regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d # macro -regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e # macro -regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f # macro -regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 # macro -regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 # macro -regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 # macro -regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 # macro -regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 # macro -regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 # macro -regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 # macro -regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 # macro -regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 # macro -regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 # macro -regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa # macro -regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab # macro -regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac # macro -regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead # macro -regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae # macro -regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf # macro -regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 # macro -regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 # macro -regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 # macro -regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 # macro -regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 # macro -regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 # macro -regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 # macro -regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 # macro -regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 # macro -regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 # macro -regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 # macro -regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 # macro -regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro -regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro -regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro -regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_PS = 0x19a8 # macro -regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_PS = 0x19a9 # macro -regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro -regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro -regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro -regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro -regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro -regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro -regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro -regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro -regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro -regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro -regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro -regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro -regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro -regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro -regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro -regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro -regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro -regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro -regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro -regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro -regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro -regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro -regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro -regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro -regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro -regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro -regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro -regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro -regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro -regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro -regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro -regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro -regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro -regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro -regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro -regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro -regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro -regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro -regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro -regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro -regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro -regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro -regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro -regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro -regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_GS = 0x1a28 # macro -regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_GS = 0x1a29 # macro -regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro -regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro -regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro -regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro -regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro -regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro -regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro -regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro -regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro -regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro -regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro -regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro -regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro -regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro -regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro -regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro -regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro -regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro -regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro -regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro -regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro -regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro -regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro -regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro -regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro -regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro -regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro -regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro -regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro -regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro -regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro -regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro -regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro -regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro -regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro -regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c # macro -regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 # macro -regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d # macro -regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro -regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro -regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro -regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro -regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro -regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_ES = 0x1a68 # macro -regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_ES = 0x1a69 # macro -regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro -regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro -regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro -regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro -regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro -regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro -regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro -regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro -regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro -regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro -regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro -regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro -regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro -regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro -regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro -regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro -regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro -regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro -regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro -regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro -regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro -regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro -regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro -regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro -regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro -regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro -regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro -regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro -regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro -regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro -regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro -regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro -regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro -regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro -regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro -regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro -regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro -regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro -regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro -regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro -regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro -regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro -regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro -regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro -regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro -regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro -regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro -regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro -regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro -regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro -regCOMPUTE_DIM_X = 0x1ba1 # macro -regCOMPUTE_DIM_X_BASE_IDX = 0 # macro -regCOMPUTE_DIM_Y = 0x1ba2 # macro -regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro -regCOMPUTE_DIM_Z = 0x1ba3 # macro -regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro -regCOMPUTE_START_X = 0x1ba4 # macro -regCOMPUTE_START_X_BASE_IDX = 0 # macro -regCOMPUTE_START_Y = 0x1ba5 # macro -regCOMPUTE_START_Y_BASE_IDX = 0 # macro -regCOMPUTE_START_Z = 0x1ba6 # macro -regCOMPUTE_START_Z_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro -regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro -regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro -regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro -regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro -regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro -regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_PGM_LO = 0x1bac # macro -regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro -regCOMPUTE_PGM_HI = 0x1bad # macro -regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro -regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro -regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro -regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro -regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro -regCOMPUTE_VMID = 0x1bb4 # macro -regCOMPUTE_VMID_BASE_IDX = 0 # macro -regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro -regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro -regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro -regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro -regCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro -regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro -regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro -regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_X = 0x1bbb # macro -regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_Y = 0x1bbc # macro -regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_Z = 0x1bbd # macro -regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro -regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro -regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_MISC_RESERVED = 0x1bbf # macro -regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_ID = 0x1bc0 # macro -regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro -regCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro -regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro -regCOMPUTE_REQ_CTRL = 0x1bc2 # macro -regCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro -regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro -regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro -regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro -regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro -regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro -regCOMPUTE_DDID_INDEX = 0x1bc9 # macro -regCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro -regCOMPUTE_SHADER_CHKSUM = 0x1bca # macro -regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf # macro -regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 # macro -regCOMPUTE_RELAUNCH = 0x1bd0 # macro -regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro -regCOMPUTE_RELAUNCH2 = 0x1bd3 # macro -regCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_0 = 0x1be0 # macro -regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_1 = 0x1be1 # macro -regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_2 = 0x1be2 # macro -regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_3 = 0x1be3 # macro -regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_4 = 0x1be4 # macro -regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_5 = 0x1be5 # macro -regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_6 = 0x1be6 # macro -regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_7 = 0x1be7 # macro -regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_8 = 0x1be8 # macro -regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_9 = 0x1be9 # macro -regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_10 = 0x1bea # macro -regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_11 = 0x1beb # macro -regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_12 = 0x1bec # macro -regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_13 = 0x1bed # macro -regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_14 = 0x1bee # macro -regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_15 = 0x1bef # macro -regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro -regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_END = 0x1c1e # macro -regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro -regCOMPUTE_NOWHERE = 0x1c1f # macro -regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro -regSH_RESERVED_REG0 = 0x1c20 # macro -regSH_RESERVED_REG0_BASE_IDX = 0 # macro -regSH_RESERVED_REG1 = 0x1c21 # macro -regSH_RESERVED_REG1_BASE_IDX = 0 # macro -regCP_CU_MASK_ADDR_LO = 0x1dd2 # macro -regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 # macro -regCP_CU_MASK_ADDR_HI = 0x1dd3 # macro -regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 # macro -regCP_CU_MASK_CNTL = 0x1dd4 # macro -regCP_CU_MASK_CNTL_BASE_IDX = 0 # macro -regCP_EOPQ_WAIT_TIME = 0x1dd5 # macro -regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro -regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro -regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro -regCPC_INT_INFO = 0x1dd7 # macro -regCPC_INT_INFO_BASE_IDX = 0 # macro -regCP_VIRT_STATUS = 0x1dd8 # macro -regCP_VIRT_STATUS_BASE_IDX = 0 # macro -regCPC_INT_ADDR = 0x1dd9 # macro -regCPC_INT_ADDR_BASE_IDX = 0 # macro -regCPC_INT_PASID = 0x1dda # macro -regCPC_INT_PASID_BASE_IDX = 0 # macro -regCP_GFX_ERROR = 0x1ddb # macro -regCP_GFX_ERROR_BASE_IDX = 0 # macro -regCPG_UTCL1_CNTL = 0x1ddc # macro -regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro -regCPC_UTCL1_CNTL = 0x1ddd # macro -regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro -regCPF_UTCL1_CNTL = 0x1dde # macro -regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro -regCP_AQL_SMM_STATUS = 0x1ddf # macro -regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro -regCP_RB0_BASE = 0x1de0 # macro -regCP_RB0_BASE_BASE_IDX = 0 # macro -regCP_RB_BASE = 0x1de0 # macro -regCP_RB_BASE_BASE_IDX = 0 # macro -regCP_RB0_CNTL = 0x1de1 # macro -regCP_RB0_CNTL_BASE_IDX = 0 # macro -regCP_RB_CNTL = 0x1de1 # macro -regCP_RB_CNTL_BASE_IDX = 0 # macro -regCP_RB_RPTR_WR = 0x1de2 # macro -regCP_RB_RPTR_WR_BASE_IDX = 0 # macro -regCP_RB0_RPTR_ADDR = 0x1de3 # macro -regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB_RPTR_ADDR = 0x1de3 # macro -regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro -regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_RPTR_ADDR_HI = 0x1de4 # macro -regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB0_BUFSZ_MASK = 0x1de5 # macro -regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_RB_BUFSZ_MASK = 0x1de5 # macro -regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_INT_CNTL = 0x1de9 # macro -regCP_INT_CNTL_BASE_IDX = 0 # macro -regCP_INT_STATUS = 0x1dea # macro -regCP_INT_STATUS_BASE_IDX = 0 # macro -regCP_DEVICE_ID = 0x1deb # macro -regCP_DEVICE_ID_BASE_IDX = 0 # macro -regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro -regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_RING_PRIORITY_CNTS = 0x1dec # macro -regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME0_PIPE0_PRIORITY = 0x1ded # macro -regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_RING0_PRIORITY = 0x1ded # macro -regCP_RING0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME0_PIPE1_PRIORITY = 0x1dee # macro -regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_RING1_PRIORITY = 0x1dee # macro -regCP_RING1_PRIORITY_BASE_IDX = 0 # macro -regCP_FATAL_ERROR = 0x1df0 # macro -regCP_FATAL_ERROR_BASE_IDX = 0 # macro -regCP_RB_VMID = 0x1df1 # macro -regCP_RB_VMID_BASE_IDX = 0 # macro -regCP_ME0_PIPE0_VMID = 0x1df2 # macro -regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro -regCP_ME0_PIPE1_VMID = 0x1df3 # macro -regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro -regCP_RB0_WPTR = 0x1df4 # macro -regCP_RB0_WPTR_BASE_IDX = 0 # macro -regCP_RB_WPTR = 0x1df4 # macro -regCP_RB_WPTR_BASE_IDX = 0 # macro -regCP_RB0_WPTR_HI = 0x1df5 # macro -regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro -regCP_RB_WPTR_HI = 0x1df5 # macro -regCP_RB_WPTR_HI_BASE_IDX = 0 # macro -regCP_RB1_WPTR = 0x1df6 # macro -regCP_RB1_WPTR_BASE_IDX = 0 # macro -regCP_RB1_WPTR_HI = 0x1df7 # macro -regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro -regCP_PROCESS_QUANTUM = 0x1df9 # macro -regCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro -regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro -regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro -regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro -regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -regCPG_UTCL1_ERROR = 0x1dfe # macro -regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro -regCPC_UTCL1_ERROR = 0x1dff # macro -regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro -regCP_RB1_BASE = 0x1e00 # macro -regCP_RB1_BASE_BASE_IDX = 0 # macro -regCP_RB1_CNTL = 0x1e01 # macro -regCP_RB1_CNTL_BASE_IDX = 0 # macro -regCP_RB1_RPTR_ADDR = 0x1e02 # macro -regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro -regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB1_BUFSZ_MASK = 0x1e04 # macro -regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_INT_CNTL_RING0 = 0x1e0a # macro -regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro -regCP_INT_CNTL_RING1 = 0x1e0b # macro -regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro -regCP_INT_STATUS_RING0 = 0x1e0d # macro -regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro -regCP_INT_STATUS_RING1 = 0x1e0e # macro -regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro -regCP_ME_F32_INTERRUPT = 0x1e13 # macro -regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_PFP_F32_INTERRUPT = 0x1e14 # macro -regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_MEC1_F32_INTERRUPT = 0x1e16 # macro -regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_MEC2_F32_INTERRUPT = 0x1e17 # macro -regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_PWR_CNTL = 0x1e18 # macro -regCP_PWR_CNTL_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro -regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro -regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro -regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro -regGB_EDC_MODE = 0x1e1e # macro -regGB_EDC_MODE_BASE_IDX = 0 # macro -regCP_DEBUG = 0x1e1f # macro -regCP_DEBUG_BASE_IDX = 0 # macro -regCP_CPC_DEBUG = 0x1e21 # macro -regCP_CPC_DEBUG_BASE_IDX = 0 # macro -regCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro -regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro -regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro -regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro -regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro -regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro -regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro -regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro -regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro -regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro -regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro -regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro -regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro -regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro -regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro -regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro -regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro -regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro -regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -regCP_GFX_QUEUE_INDEX = 0x1e37 # macro -regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro -regCC_GC_EDC_CONFIG = 0x1e38 # macro -regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro -regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro -regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro -regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro -regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro -regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro -regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro -regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro -regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro -regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro -regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro -regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro -regCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro -regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_ME_PRGRM_CNTR_START = 0x1e45 # macro -regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro -regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro -regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro -regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_ME_INTR_ROUTINE_START = 0x1e4a # macro -regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro -regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro -regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_CONTEXT_CNTL = 0x1e4d # macro -regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro -regCP_MAX_CONTEXT = 0x1e4e # macro -regCP_MAX_CONTEXT_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME1 = 0x1e4f # macro -regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME2 = 0x1e50 # macro -regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro -regCP_RB0_BASE_HI = 0x1e51 # macro -regCP_RB0_BASE_HI_BASE_IDX = 0 # macro -regCP_RB1_BASE_HI = 0x1e52 # macro -regCP_RB1_BASE_HI_BASE_IDX = 0 # macro -regCP_VMID_RESET = 0x1e53 # macro -regCP_VMID_RESET_BASE_IDX = 0 # macro -regCPC_INT_CNTL = 0x1e54 # macro -regCPC_INT_CNTL_BASE_IDX = 0 # macro -regCPC_INT_STATUS = 0x1e55 # macro -regCPC_INT_STATUS_BASE_IDX = 0 # macro -regCP_VMID_PREEMPT = 0x1e56 # macro -regCP_VMID_PREEMPT_BASE_IDX = 0 # macro -regCPC_INT_CNTX_ID = 0x1e57 # macro -regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro -regCP_PQ_STATUS = 0x1e58 # macro -regCP_PQ_STATUS_BASE_IDX = 0 # macro -regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 # macro -regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro -regCP_MAX_DRAW_COUNT = 0x1e5c # macro -regCP_MAX_DRAW_COUNT_BASE_IDX = 0 # macro -regCP_MEC1_F32_INT_DIS = 0x1e5d # macro -regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro -regCP_MEC2_F32_INT_DIS = 0x1e5e # macro -regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro -regCP_VMID_STATUS = 0x1e5f # macro -regCP_VMID_STATUS_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro -regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro -regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro -regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro -regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro -regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -regCPC_OS_PIPES = 0x1e67 # macro -regCPC_OS_PIPES_BASE_IDX = 0 # macro -regCP_SUSPEND_RESUME_REQ = 0x1e68 # macro -regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro -regCP_SUSPEND_CNTL = 0x1e69 # macro -regCP_SUSPEND_CNTL_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME3 = 0x1e6a # macro -regCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro -regCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro -regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCP_DDID_BASE_ADDR_LO = 0x1e6b # macro -regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro -regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_DDID_BASE_ADDR_HI = 0x1e6c # macro -regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCPC_DDID_CNTL = 0x1e6d # macro -regCPC_DDID_CNTL_BASE_IDX = 0 # macro -regCP_DDID_CNTL = 0x1e6d # macro -regCP_DDID_CNTL_BASE_IDX = 0 # macro -regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro -regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -regCP_GFX_DDID_WPTR = 0x1e6f # macro -regCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro -regCP_GFX_DDID_RPTR = 0x1e70 # macro -regCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro -regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro -regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -regCP_GFX_HPD_STATUS0 = 0x1e72 # macro -regCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro -regCP_GFX_HPD_CONTROL0 = 0x1e73 # macro -regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro -regCP_GFX_INDEX_MUTEX = 0x1e78 # macro -regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro -regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 # macro -regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro -regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a # macro -regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro -regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b # macro -regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro -regCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro -regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro -regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro -regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_ACTIVE = 0x1e80 # macro -regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro -regCP_GFX_HQD_VMID = 0x1e81 # macro -regCP_GFX_HQD_VMID_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro -regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUANTUM = 0x1e85 # macro -regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro -regCP_GFX_HQD_BASE = 0x1e86 # macro -regCP_GFX_HQD_BASE_BASE_IDX = 0 # macro -regCP_GFX_HQD_BASE_HI = 0x1e87 # macro -regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR = 0x1e88 # macro -regCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro -regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro -regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro -regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro -regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_CONTROL = 0x1e8d # macro -regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro -regCP_GFX_HQD_OFFSET = 0x1e8e # macro -regCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro -regCP_GFX_HQD_CNTL = 0x1e8f # macro -regCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro -regCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro -regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_WPTR = 0x1e91 # macro -regCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_WPTR_HI = 0x1e92 # macro -regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro -regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -regCP_GFX_HQD_MAPPED = 0x1e94 # macro -regCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro -regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro -regCP_GFX_HQD_IQ_TIMER = 0x1e96 # macro -regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 # macro -regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro -regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro -regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -regCP_GFX_MQD_CONTROL = 0x1e9a # macro -regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_GFX_CONTROL = 0x1e9f # macro -regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_GFX_STATUS = 0x1ea0 # macro -regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro -regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro -regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_MASK = 0x1ec2 # macro -regCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_CNTL = 0x1ec3 # macro -regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro -regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro -regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_MASK = 0x1ec6 # macro -regCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_CNTL = 0x1ec7 # macro -regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro -regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro -regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_MASK = 0x1eca # macro -regCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_CNTL = 0x1ecb # macro -regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro -regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro -regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_MASK = 0x1ece # macro -regCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_CNTL = 0x1ecf # macro -regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro -regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro -regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT = 0x1ed2 # macro -regCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro -regCP_PFP_JT_STAT = 0x1ed3 # macro -regCP_PFP_JT_STAT_BASE_IDX = 0 # macro -regCP_MEC_JT_STAT = 0x1ed5 # macro -regCP_MEC_JT_STAT_BASE_IDX = 0 # macro -regCP_CPC_BUSY_HYSTERESIS = 0x1edb # macro -regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 # macro -regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc # macro -regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro -regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd # macro -regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro -regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede # macro -regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro -regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf # macro -regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_CLEAR = 0x1f28 # macro -regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro -regCP_RB0_ACTIVE = 0x1f40 # macro -regCP_RB0_ACTIVE_BASE_IDX = 0 # macro -regCP_RB_ACTIVE = 0x1f40 # macro -regCP_RB_ACTIVE_BASE_IDX = 0 # macro -regCP_RB1_ACTIVE = 0x1f41 # macro -regCP_RB1_ACTIVE_BASE_IDX = 0 # macro -regCP_RB_STATUS = 0x1f43 # macro -regCP_RB_STATUS_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_INDEX = 0x1f44 # macro -regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro -regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro -regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro -regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro -regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro -regCP_SDMA_DMA_DONE = 0x1f4e # macro -regCP_SDMA_DMA_DONE_BASE_IDX = 0 # macro -regCP_PFP_SDMA_CS = 0x1f4f # macro -regCP_PFP_SDMA_CS_BASE_IDX = 0 # macro -regCP_ME_SDMA_CS = 0x1f50 # macro -regCP_ME_SDMA_CS_BASE_IDX = 0 # macro -regCPF_GCR_CNTL = 0x1f53 # macro -regCPF_GCR_CNTL_BASE_IDX = 0 # macro -regCPG_UTCL1_STATUS = 0x1f54 # macro -regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro -regCPC_UTCL1_STATUS = 0x1f55 # macro -regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro -regCPF_UTCL1_STATUS = 0x1f56 # macro -regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro -regCP_SD_CNTL = 0x1f57 # macro -regCP_SD_CNTL_BASE_IDX = 0 # macro -regCP_SOFT_RESET_CNTL = 0x1f59 # macro -regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro -regCP_CPC_GFX_CNTL = 0x1f5a # macro -regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro -regSPI_ARB_PRIORITY = 0x1f60 # macro -regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro -regSPI_ARB_CYCLES_0 = 0x1f61 # macro -regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro -regSPI_ARB_CYCLES_1 = 0x1f62 # macro -regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro -regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro -regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro -regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro -regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro -regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro -regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d # macro -regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e # macro -regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f # macro -regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 # macro -regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro -regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 # macro -regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro -regSPI_GDBG_PER_VMID_CNTL = 0x1f72 # macro -regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro -regSPI_COMPUTE_QUEUE_RESET = 0x1f73 # macro -regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro -regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 # macro -regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_CNTL = 0x1fa3 # macro -regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_ERROR = 0x1fa7 # macro -regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro -regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro -regCP_MQD_BASE_ADDR = 0x1fa9 # macro -regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro -regCP_MQD_BASE_ADDR_HI = 0x1faa # macro -regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_ACTIVE = 0x1fab # macro -regCP_HQD_ACTIVE_BASE_IDX = 0 # macro -regCP_HQD_VMID = 0x1fac # macro -regCP_HQD_VMID_BASE_IDX = 0 # macro -regCP_HQD_PERSISTENT_STATE = 0x1fad # macro -regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro -regCP_HQD_PIPE_PRIORITY = 0x1fae # macro -regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro -regCP_HQD_QUEUE_PRIORITY = 0x1faf # macro -regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -regCP_HQD_QUANTUM = 0x1fb0 # macro -regCP_HQD_QUANTUM_BASE_IDX = 0 # macro -regCP_HQD_PQ_BASE = 0x1fb1 # macro -regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro -regCP_HQD_PQ_BASE_HI = 0x1fb2 # macro -regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR = 0x1fb3 # macro -regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro -regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_PQ_CONTROL = 0x1fba # macro -regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_IB_BASE_ADDR = 0x1fbb # macro -regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro -regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro -regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_IB_RPTR = 0x1fbd # macro -regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro -regCP_HQD_IB_CONTROL = 0x1fbe # macro -regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_IQ_TIMER = 0x1fbf # macro -regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro -regCP_HQD_IQ_RPTR = 0x1fc0 # macro -regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro -regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro -regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -regCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro -regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro -regCP_HQD_OFFLOAD = 0x1fc2 # macro -regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro -regCP_HQD_SEMA_CMD = 0x1fc3 # macro -regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro -regCP_HQD_MSG_TYPE = 0x1fc4 # macro -regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro -regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro -regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro -regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro -regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro -regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro -regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro -regCP_HQD_HQ_STATUS0 = 0x1fc9 # macro -regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -regCP_HQD_HQ_CONTROL0 = 0x1fca # macro -regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -regCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro -regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro -regCP_MQD_CONTROL = 0x1fcb # macro -regCP_MQD_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_HQ_STATUS1 = 0x1fcc # macro -regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro -regCP_HQD_HQ_CONTROL1 = 0x1fcd # macro -regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro -regCP_HQD_EOP_BASE_ADDR = 0x1fce # macro -regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro -regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro -regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_EOP_CONTROL = 0x1fd0 # macro -regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_EOP_RPTR = 0x1fd1 # macro -regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro -regCP_HQD_EOP_WPTR = 0x1fd2 # macro -regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro -regCP_HQD_EOP_EVENTS = 0x1fd3 # macro -regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro -regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro -regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro -regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -regCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro -regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro -regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro -regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro -regCP_HQD_ERROR = 0x1fdc # macro -regCP_HQD_ERROR_BASE_IDX = 0 # macro -regCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro -regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro -regCP_HQD_AQL_CONTROL = 0x1fde # macro -regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_LO = 0x1fdf # macro -regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro -regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro -regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro -regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro -regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_DDID_RPTR = 0x1fe4 # macro -regCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro -regCP_HQD_DDID_WPTR = 0x1fe5 # macro -regCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro -regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro -regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro -regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -regCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro -regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro -regTCP_WATCH0_ADDR_H = 0x2048 # macro -regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH0_ADDR_L = 0x2049 # macro -regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH0_CNTL = 0x204a # macro -regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH1_ADDR_H = 0x204b # macro -regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH1_ADDR_L = 0x204c # macro -regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH1_CNTL = 0x204d # macro -regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH2_ADDR_H = 0x204e # macro -regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH2_ADDR_L = 0x204f # macro -regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH2_CNTL = 0x2050 # macro -regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH3_ADDR_H = 0x2051 # macro -regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH3_ADDR_L = 0x2052 # macro -regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH3_CNTL = 0x2053 # macro -regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro -regGDS_VMID0_BASE = 0x20a0 # macro -regGDS_VMID0_BASE_BASE_IDX = 0 # macro -regGDS_VMID0_SIZE = 0x20a1 # macro -regGDS_VMID0_SIZE_BASE_IDX = 0 # macro -regGDS_VMID1_BASE = 0x20a2 # macro -regGDS_VMID1_BASE_BASE_IDX = 0 # macro -regGDS_VMID1_SIZE = 0x20a3 # macro -regGDS_VMID1_SIZE_BASE_IDX = 0 # macro -regGDS_VMID2_BASE = 0x20a4 # macro -regGDS_VMID2_BASE_BASE_IDX = 0 # macro -regGDS_VMID2_SIZE = 0x20a5 # macro -regGDS_VMID2_SIZE_BASE_IDX = 0 # macro -regGDS_VMID3_BASE = 0x20a6 # macro -regGDS_VMID3_BASE_BASE_IDX = 0 # macro -regGDS_VMID3_SIZE = 0x20a7 # macro -regGDS_VMID3_SIZE_BASE_IDX = 0 # macro -regGDS_VMID4_BASE = 0x20a8 # macro -regGDS_VMID4_BASE_BASE_IDX = 0 # macro -regGDS_VMID4_SIZE = 0x20a9 # macro -regGDS_VMID4_SIZE_BASE_IDX = 0 # macro -regGDS_VMID5_BASE = 0x20aa # macro -regGDS_VMID5_BASE_BASE_IDX = 0 # macro -regGDS_VMID5_SIZE = 0x20ab # macro -regGDS_VMID5_SIZE_BASE_IDX = 0 # macro -regGDS_VMID6_BASE = 0x20ac # macro -regGDS_VMID6_BASE_BASE_IDX = 0 # macro -regGDS_VMID6_SIZE = 0x20ad # macro -regGDS_VMID6_SIZE_BASE_IDX = 0 # macro -regGDS_VMID7_BASE = 0x20ae # macro -regGDS_VMID7_BASE_BASE_IDX = 0 # macro -regGDS_VMID7_SIZE = 0x20af # macro -regGDS_VMID7_SIZE_BASE_IDX = 0 # macro -regGDS_VMID8_BASE = 0x20b0 # macro -regGDS_VMID8_BASE_BASE_IDX = 0 # macro -regGDS_VMID8_SIZE = 0x20b1 # macro -regGDS_VMID8_SIZE_BASE_IDX = 0 # macro -regGDS_VMID9_BASE = 0x20b2 # macro -regGDS_VMID9_BASE_BASE_IDX = 0 # macro -regGDS_VMID9_SIZE = 0x20b3 # macro -regGDS_VMID9_SIZE_BASE_IDX = 0 # macro -regGDS_VMID10_BASE = 0x20b4 # macro -regGDS_VMID10_BASE_BASE_IDX = 0 # macro -regGDS_VMID10_SIZE = 0x20b5 # macro -regGDS_VMID10_SIZE_BASE_IDX = 0 # macro -regGDS_VMID11_BASE = 0x20b6 # macro -regGDS_VMID11_BASE_BASE_IDX = 0 # macro -regGDS_VMID11_SIZE = 0x20b7 # macro -regGDS_VMID11_SIZE_BASE_IDX = 0 # macro -regGDS_VMID12_BASE = 0x20b8 # macro -regGDS_VMID12_BASE_BASE_IDX = 0 # macro -regGDS_VMID12_SIZE = 0x20b9 # macro -regGDS_VMID12_SIZE_BASE_IDX = 0 # macro -regGDS_VMID13_BASE = 0x20ba # macro -regGDS_VMID13_BASE_BASE_IDX = 0 # macro -regGDS_VMID13_SIZE = 0x20bb # macro -regGDS_VMID13_SIZE_BASE_IDX = 0 # macro -regGDS_VMID14_BASE = 0x20bc # macro -regGDS_VMID14_BASE_BASE_IDX = 0 # macro -regGDS_VMID14_SIZE = 0x20bd # macro -regGDS_VMID14_SIZE_BASE_IDX = 0 # macro -regGDS_VMID15_BASE = 0x20be # macro -regGDS_VMID15_BASE_BASE_IDX = 0 # macro -regGDS_VMID15_SIZE = 0x20bf # macro -regGDS_VMID15_SIZE_BASE_IDX = 0 # macro -regGDS_GWS_VMID0 = 0x20c0 # macro -regGDS_GWS_VMID0_BASE_IDX = 0 # macro -regGDS_GWS_VMID1 = 0x20c1 # macro -regGDS_GWS_VMID1_BASE_IDX = 0 # macro -regGDS_GWS_VMID2 = 0x20c2 # macro -regGDS_GWS_VMID2_BASE_IDX = 0 # macro -regGDS_GWS_VMID3 = 0x20c3 # macro -regGDS_GWS_VMID3_BASE_IDX = 0 # macro -regGDS_GWS_VMID4 = 0x20c4 # macro -regGDS_GWS_VMID4_BASE_IDX = 0 # macro -regGDS_GWS_VMID5 = 0x20c5 # macro -regGDS_GWS_VMID5_BASE_IDX = 0 # macro -regGDS_GWS_VMID6 = 0x20c6 # macro -regGDS_GWS_VMID6_BASE_IDX = 0 # macro -regGDS_GWS_VMID7 = 0x20c7 # macro -regGDS_GWS_VMID7_BASE_IDX = 0 # macro -regGDS_GWS_VMID8 = 0x20c8 # macro -regGDS_GWS_VMID8_BASE_IDX = 0 # macro -regGDS_GWS_VMID9 = 0x20c9 # macro -regGDS_GWS_VMID9_BASE_IDX = 0 # macro -regGDS_GWS_VMID10 = 0x20ca # macro -regGDS_GWS_VMID10_BASE_IDX = 0 # macro -regGDS_GWS_VMID11 = 0x20cb # macro -regGDS_GWS_VMID11_BASE_IDX = 0 # macro -regGDS_GWS_VMID12 = 0x20cc # macro -regGDS_GWS_VMID12_BASE_IDX = 0 # macro -regGDS_GWS_VMID13 = 0x20cd # macro -regGDS_GWS_VMID13_BASE_IDX = 0 # macro -regGDS_GWS_VMID14 = 0x20ce # macro -regGDS_GWS_VMID14_BASE_IDX = 0 # macro -regGDS_GWS_VMID15 = 0x20cf # macro -regGDS_GWS_VMID15_BASE_IDX = 0 # macro -regGDS_OA_VMID0 = 0x20d0 # macro -regGDS_OA_VMID0_BASE_IDX = 0 # macro -regGDS_OA_VMID1 = 0x20d1 # macro -regGDS_OA_VMID1_BASE_IDX = 0 # macro -regGDS_OA_VMID2 = 0x20d2 # macro -regGDS_OA_VMID2_BASE_IDX = 0 # macro -regGDS_OA_VMID3 = 0x20d3 # macro -regGDS_OA_VMID3_BASE_IDX = 0 # macro -regGDS_OA_VMID4 = 0x20d4 # macro -regGDS_OA_VMID4_BASE_IDX = 0 # macro -regGDS_OA_VMID5 = 0x20d5 # macro -regGDS_OA_VMID5_BASE_IDX = 0 # macro -regGDS_OA_VMID6 = 0x20d6 # macro -regGDS_OA_VMID6_BASE_IDX = 0 # macro -regGDS_OA_VMID7 = 0x20d7 # macro -regGDS_OA_VMID7_BASE_IDX = 0 # macro -regGDS_OA_VMID8 = 0x20d8 # macro -regGDS_OA_VMID8_BASE_IDX = 0 # macro -regGDS_OA_VMID9 = 0x20d9 # macro -regGDS_OA_VMID9_BASE_IDX = 0 # macro -regGDS_OA_VMID10 = 0x20da # macro -regGDS_OA_VMID10_BASE_IDX = 0 # macro -regGDS_OA_VMID11 = 0x20db # macro -regGDS_OA_VMID11_BASE_IDX = 0 # macro -regGDS_OA_VMID12 = 0x20dc # macro -regGDS_OA_VMID12_BASE_IDX = 0 # macro -regGDS_OA_VMID13 = 0x20dd # macro -regGDS_OA_VMID13_BASE_IDX = 0 # macro -regGDS_OA_VMID14 = 0x20de # macro -regGDS_OA_VMID14_BASE_IDX = 0 # macro -regGDS_OA_VMID15 = 0x20df # macro -regGDS_OA_VMID15_BASE_IDX = 0 # macro -regGDS_GWS_RESET0 = 0x20e4 # macro -regGDS_GWS_RESET0_BASE_IDX = 0 # macro -regGDS_GWS_RESET1 = 0x20e5 # macro -regGDS_GWS_RESET1_BASE_IDX = 0 # macro -regGDS_GWS_RESOURCE_RESET = 0x20e6 # macro -regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro -regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro -regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro -regGDS_OA_RESET_MASK = 0x20e9 # macro -regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro -regGDS_OA_RESET = 0x20ea # macro -regGDS_OA_RESET_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_STATUS = 0x20ed # macro -regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT0 = 0x20ee # macro -regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT1 = 0x20ef # macro -regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT2 = 0x20f0 # macro -regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT3 = 0x20f1 # macro -regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_GFX_CTXSW_STATUS = 0x20f2 # macro -regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT0 = 0x20f7 # macro -regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT1 = 0x20f8 # macro -regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT2 = 0x20f9 # macro -regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT3 = 0x20fa # macro -regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_IDX = 0x20fb # macro -regGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT0 = 0x2117 # macro -regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT1 = 0x2118 # macro -regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT2 = 0x2119 # macro -regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT3 = 0x211a # macro -regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_MEMORY_CLEAN = 0x211f # macro -regGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro -regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro -regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro -regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro -regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro -regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro -regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro -regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro -regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro -regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_FIXED = 0x2c08 # macro -regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_FIXED = 0x2c09 # macro -regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro -regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro -regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro -regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro -regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro -regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro -regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro -regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro -regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro -regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro -regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro -regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro -regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro -regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro -regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro -regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro -regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro -regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro -regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro -regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro -regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro -regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro -regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro -regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro -regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUEUING = 0x2c22 # macro -regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_FIXED = 0x2c23 # macro -regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro -regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro -regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro -regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro -regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro -regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro -regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro -regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro -regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro -regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro -regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro -regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro -regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro -regGUS_IO_GROUP_BURST = 0x2c30 # macro -regGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro -regGUS_DRAM_GROUP_BURST = 0x2c31 # macro -regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro -regGUS_SDP_ARB_FINAL = 0x2c32 # macro -regGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro -regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro -regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro -regGUS_SDP_CREDITS = 0x2c34 # macro -regGUS_SDP_CREDITS_BASE_IDX = 1 # macro -regGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro -regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro -regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro -regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro -regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro -regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro -regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_REQ_CNTL = 0x2c3b # macro -regGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro -regGUS_MISC = 0x2c3c # macro -regGUS_MISC_BASE_IDX = 1 # macro -regGUS_LATENCY_SAMPLING = 0x2c3d # macro -regGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro -regGUS_ERR_STATUS = 0x2c3e # macro -regGUS_ERR_STATUS_BASE_IDX = 1 # macro -regGUS_MISC2 = 0x2c3f # macro -regGUS_MISC2_BASE_IDX = 1 # macro -regGUS_SDP_ENABLE = 0x2c45 # macro -regGUS_SDP_ENABLE_BASE_IDX = 1 # macro -regGUS_L1_CH0_CMD_IN = 0x2c46 # macro -regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_CMD_OUT = 0x2c47 # macro -regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_IN = 0x2c48 # macro -regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_OUT = 0x2c49 # macro -regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro -regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro -regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_CMD_IN = 0x2c4c # macro -regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_CMD_OUT = 0x2c4d # macro -regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_IN = 0x2c4e # macro -regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_OUT = 0x2c4f # macro -regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro -regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro -regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_CMD_IN = 0x2c52 # macro -regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_CMD_OUT = 0x2c53 # macro -regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_IN = 0x2c54 # macro -regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_OUT = 0x2c55 # macro -regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro -regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro -regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_CMD_IN = 0x2c58 # macro -regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_CMD_OUT = 0x2c59 # macro -regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_IN = 0x2c5a # macro -regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_OUT = 0x2c5b # macro -regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro -regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro -regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_CMD_IN = 0x2c5e # macro -regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_CMD_OUT = 0x2c5f # macro -regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_IN = 0x2c60 # macro -regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_OUT = 0x2c61 # macro -regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro -regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro -regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_CMD_IN = 0x2c64 # macro -regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_CMD_OUT = 0x2c65 # macro -regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_IN = 0x2c66 # macro -regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_OUT = 0x2c67 # macro -regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro -regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro -regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_MISC3 = 0x2c6a # macro -regGUS_MISC3_BASE_IDX = 1 # macro -regGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro -regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro -regDB_RENDER_CONTROL = 0x0000 # macro -regDB_RENDER_CONTROL_BASE_IDX = 1 # macro -regDB_COUNT_CONTROL = 0x0001 # macro -regDB_COUNT_CONTROL_BASE_IDX = 1 # macro -regDB_DEPTH_VIEW = 0x0002 # macro -regDB_DEPTH_VIEW_BASE_IDX = 1 # macro -regDB_RENDER_OVERRIDE = 0x0003 # macro -regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro -regDB_RENDER_OVERRIDE2 = 0x0004 # macro -regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro -regDB_HTILE_DATA_BASE = 0x0005 # macro -regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro -regDB_DEPTH_SIZE_XY = 0x0007 # macro -regDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro -regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro -regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro -regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro -regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro -regDB_STENCIL_CLEAR = 0x000a # macro -regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro -regDB_DEPTH_CLEAR = 0x000b # macro -regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro -regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro -regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro -regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro -regDB_RESERVED_REG_2 = 0x000f # macro -regDB_RESERVED_REG_2_BASE_IDX = 1 # macro -regDB_Z_INFO = 0x0010 # macro -regDB_Z_INFO_BASE_IDX = 1 # macro -regDB_STENCIL_INFO = 0x0011 # macro -regDB_STENCIL_INFO_BASE_IDX = 1 # macro -regDB_Z_READ_BASE = 0x0012 # macro -regDB_Z_READ_BASE_BASE_IDX = 1 # macro -regDB_STENCIL_READ_BASE = 0x0013 # macro -regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro -regDB_Z_WRITE_BASE = 0x0014 # macro -regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro -regDB_STENCIL_WRITE_BASE = 0x0015 # macro -regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro -regDB_RESERVED_REG_1 = 0x0016 # macro -regDB_RESERVED_REG_1_BASE_IDX = 1 # macro -regDB_RESERVED_REG_3 = 0x0017 # macro -regDB_RESERVED_REG_3_BASE_IDX = 1 # macro -regDB_Z_READ_BASE_HI = 0x001a # macro -regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro -regDB_STENCIL_READ_BASE_HI = 0x001b # macro -regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro -regDB_Z_WRITE_BASE_HI = 0x001c # macro -regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro -regDB_STENCIL_WRITE_BASE_HI = 0x001d # macro -regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro -regDB_HTILE_DATA_BASE_HI = 0x001e # macro -regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro -regDB_RMI_L2_CACHE_CONTROL = 0x001f # macro -regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro -regTA_BC_BASE_ADDR = 0x0020 # macro -regTA_BC_BASE_ADDR_BASE_IDX = 1 # macro -regTA_BC_BASE_ADDR_HI = 0x0021 # macro -regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_0 = 0x007a # macro -regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_1 = 0x007b # macro -regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_2 = 0x007c # macro -regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_3 = 0x007d # macro -regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_2 = 0x007e # macro -regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_3 = 0x007f # macro -regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro -regPA_SC_WINDOW_OFFSET = 0x0080 # macro -regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro -regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro -regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro -regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_RULE = 0x0083 # macro -regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_0_TL = 0x0084 # macro -regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_0_BR = 0x0085 # macro -regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_1_TL = 0x0086 # macro -regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_1_BR = 0x0087 # macro -regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_2_TL = 0x0088 # macro -regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_2_BR = 0x0089 # macro -regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_3_TL = 0x008a # macro -regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_3_BR = 0x008b # macro -regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro -regPA_SC_EDGERULE = 0x008c # macro -regPA_SC_EDGERULE_BASE_IDX = 1 # macro -regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro -regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro -regCB_TARGET_MASK = 0x008e # macro -regCB_TARGET_MASK_BASE_IDX = 1 # macro -regCB_SHADER_MASK = 0x008f # macro -regCB_SHADER_MASK_BASE_IDX = 1 # macro -regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro -regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro -regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_0 = 0x0092 # macro -regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_1 = 0x0093 # macro -regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro -regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro -regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro -regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro -regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro -regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro -regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro -regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro -regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro -regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro -regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro -regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro -regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro -regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro -regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro -regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro -regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro -regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro -regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro -regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro -regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro -regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro -regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro -regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro -regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro -regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro -regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro -regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro -regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro -regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro -regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro -regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro -regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro -regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro -regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro -regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro -regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro -regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro -regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro -regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro -regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro -regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro -regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_5 = 0x00be # macro -regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro -regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro -regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro -regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro -regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro -regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro -regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro -regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro -regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro -regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro -regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro -regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro -regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro -regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro -regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro -regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro -regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro -regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro -regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro -regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro -regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro -regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro -regPA_SC_RASTER_CONFIG = 0x00d4 # macro -regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro -regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro -regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro -regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro -regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro -regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro -regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro -regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro -regCP_PIPEID = 0x00d9 # macro -regCP_PIPEID_BASE_IDX = 1 # macro -regCP_RINGID = 0x00d9 # macro -regCP_RINGID_BASE_IDX = 1 # macro -regCP_VMID = 0x00da # macro -regCP_VMID_BASE_IDX = 1 # macro -regCONTEXT_RESERVED_REG0 = 0x00db # macro -regCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro -regCONTEXT_RESERVED_REG1 = 0x00dc # macro -regCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro -regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 # macro -regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 # macro -regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 # macro -regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_BASE = 0x00fc # macro -regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_BASE_EXT = 0x00fd # macro -regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_SIZE_XY = 0x00fe # macro -regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 # macro -regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro -regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro -regCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro -regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND_RED = 0x0105 # macro -regCB_BLEND_RED_BASE_IDX = 1 # macro -regCB_BLEND_GREEN = 0x0106 # macro -regCB_BLEND_GREEN_BASE_IDX = 1 # macro -regCB_BLEND_BLUE = 0x0107 # macro -regCB_BLEND_BLUE_BASE_IDX = 1 # macro -regCB_BLEND_ALPHA = 0x0108 # macro -regCB_BLEND_ALPHA_BASE_IDX = 1 # macro -regCB_FDCC_CONTROL = 0x0109 # macro -regCB_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COVERAGE_OUT_CONTROL = 0x010a # macro -regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro -regDB_STENCIL_CONTROL = 0x010b # macro -regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro -regDB_STENCILREFMASK = 0x010c # macro -regDB_STENCILREFMASK_BASE_IDX = 1 # macro -regDB_STENCILREFMASK_BF = 0x010d # macro -regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE = 0x010f # macro -regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET = 0x0110 # macro -regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE = 0x0111 # macro -regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET = 0x0112 # macro -regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE = 0x0113 # macro -regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET = 0x0114 # macro -regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro -regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro -regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro -regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro -regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro -regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro -regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_2 = 0x011b # macro -regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro -regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_2 = 0x011d # macro -regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro -regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro -regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro -regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro -regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro -regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro -regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro -regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro -regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro -regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro -regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro -regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro -regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro -regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro -regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro -regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_5 = 0x012d # macro -regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro -regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_5 = 0x012f # macro -regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro -regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro -regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro -regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro -regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro -regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro -regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro -regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro -regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro -regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro -regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro -regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_7 = 0x013b # macro -regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro -regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro -regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro -regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_8 = 0x013f # macro -regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro -regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro -regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro -regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro -regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro -regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro -regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro -regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro -regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro -regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro -regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro -regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_10 = 0x014b # macro -regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro -regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_10 = 0x014d # macro -regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro -regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro -regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro -regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro -regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro -regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro -regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro -regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro -regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro -regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro -regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro -regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro -regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro -regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro -regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro -regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_13 = 0x015d # macro -regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro -regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_13 = 0x015f # macro -regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro -regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro -regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro -regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro -regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro -regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro -regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro -regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro -regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro -regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro -regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro -regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_15 = 0x016b # macro -regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro -regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro -regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro -regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_UCP_0_X = 0x016f # macro -regPA_CL_UCP_0_X_BASE_IDX = 1 # macro -regPA_CL_UCP_0_Y = 0x0170 # macro -regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_0_Z = 0x0171 # macro -regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_0_W = 0x0172 # macro -regPA_CL_UCP_0_W_BASE_IDX = 1 # macro -regPA_CL_UCP_1_X = 0x0173 # macro -regPA_CL_UCP_1_X_BASE_IDX = 1 # macro -regPA_CL_UCP_1_Y = 0x0174 # macro -regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_1_Z = 0x0175 # macro -regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_1_W = 0x0176 # macro -regPA_CL_UCP_1_W_BASE_IDX = 1 # macro -regPA_CL_UCP_2_X = 0x0177 # macro -regPA_CL_UCP_2_X_BASE_IDX = 1 # macro -regPA_CL_UCP_2_Y = 0x0178 # macro -regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_2_Z = 0x0179 # macro -regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_2_W = 0x017a # macro -regPA_CL_UCP_2_W_BASE_IDX = 1 # macro -regPA_CL_UCP_3_X = 0x017b # macro -regPA_CL_UCP_3_X_BASE_IDX = 1 # macro -regPA_CL_UCP_3_Y = 0x017c # macro -regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_3_Z = 0x017d # macro -regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_3_W = 0x017e # macro -regPA_CL_UCP_3_W_BASE_IDX = 1 # macro -regPA_CL_UCP_4_X = 0x017f # macro -regPA_CL_UCP_4_X_BASE_IDX = 1 # macro -regPA_CL_UCP_4_Y = 0x0180 # macro -regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_4_Z = 0x0181 # macro -regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_4_W = 0x0182 # macro -regPA_CL_UCP_4_W_BASE_IDX = 1 # macro -regPA_CL_UCP_5_X = 0x0183 # macro -regPA_CL_UCP_5_X_BASE_IDX = 1 # macro -regPA_CL_UCP_5_Y = 0x0184 # macro -regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_5_Z = 0x0185 # macro -regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_5_W = 0x0186 # macro -regPA_CL_UCP_5_W_BASE_IDX = 1 # macro -regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro -regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro -regPA_RATE_CNTL = 0x0188 # macro -regPA_RATE_CNTL_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro -regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro -regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro -regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro -regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro -regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro -regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro -regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro -regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro -regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_9 = 0x019a # macro -regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_10 = 0x019b # macro -regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_11 = 0x019c # macro -regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_12 = 0x019d # macro -regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_13 = 0x019e # macro -regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_14 = 0x019f # macro -regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro -regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro -regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro -regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro -regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro -regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro -regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro -regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro -regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro -regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro -regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro -regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro -regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro -regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro -regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro -regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_30 = 0x01af # macro -regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro -regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro -regSPI_VS_OUT_CONFIG = 0x01b1 # macro -regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro -regSPI_PS_INPUT_ENA = 0x01b3 # macro -regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro -regSPI_PS_INPUT_ADDR = 0x01b4 # macro -regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro -regSPI_INTERP_CONTROL_0 = 0x01b5 # macro -regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro -regSPI_PS_IN_CONTROL = 0x01b6 # macro -regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro -regSPI_BARYC_CNTL = 0x01b8 # macro -regSPI_BARYC_CNTL_BASE_IDX = 1 # macro -regSPI_TMPRING_SIZE = 0x01ba # macro -regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro -regSPI_GFX_SCRATCH_BASE_LO = 0x01bb # macro -regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regSPI_GFX_SCRATCH_BASE_HI = 0x01bc # macro -regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regSPI_SHADER_IDX_FORMAT = 0x01c2 # macro -regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_POS_FORMAT = 0x01c3 # macro -regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_Z_FORMAT = 0x01c4 # macro -regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_COL_FORMAT = 0x01c5 # macro -regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro -regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro -regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro -regSX_PS_DOWNCONVERT = 0x01d5 # macro -regSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro -regSX_BLEND_OPT_EPSILON = 0x01d6 # macro -regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro -regSX_BLEND_OPT_CONTROL = 0x01d7 # macro -regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro -regSX_MRT0_BLEND_OPT = 0x01d8 # macro -regSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT1_BLEND_OPT = 0x01d9 # macro -regSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT2_BLEND_OPT = 0x01da # macro -regSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT3_BLEND_OPT = 0x01db # macro -regSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT4_BLEND_OPT = 0x01dc # macro -regSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT5_BLEND_OPT = 0x01dd # macro -regSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT6_BLEND_OPT = 0x01de # macro -regSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT7_BLEND_OPT = 0x01df # macro -regSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro -regCB_BLEND0_CONTROL = 0x01e0 # macro -regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND1_CONTROL = 0x01e1 # macro -regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND2_CONTROL = 0x01e2 # macro -regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND3_CONTROL = 0x01e3 # macro -regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND4_CONTROL = 0x01e4 # macro -regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND5_CONTROL = 0x01e5 # macro -regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND6_CONTROL = 0x01e6 # macro -regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND7_CONTROL = 0x01e7 # macro -regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro -regGFX_COPY_STATE = 0x01f4 # macro -regGFX_COPY_STATE_BASE_IDX = 1 # macro -regPA_CL_POINT_X_RAD = 0x01f5 # macro -regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro -regPA_CL_POINT_Y_RAD = 0x01f6 # macro -regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro -regPA_CL_POINT_SIZE = 0x01f7 # macro -regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro -regPA_CL_POINT_CULL_RAD = 0x01f8 # macro -regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro -regVGT_DMA_BASE_HI = 0x01f9 # macro -regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro -regVGT_DMA_BASE = 0x01fa # macro -regVGT_DMA_BASE_BASE_IDX = 1 # macro -regVGT_DRAW_INITIATOR = 0x01fc # macro -regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro -regVGT_EVENT_ADDRESS_REG = 0x01fe # macro -regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro -regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro -regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro -regDB_DEPTH_CONTROL = 0x0200 # macro -regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro -regDB_EQAA = 0x0201 # macro -regDB_EQAA_BASE_IDX = 1 # macro -regCB_COLOR_CONTROL = 0x0202 # macro -regCB_COLOR_CONTROL_BASE_IDX = 1 # macro -regDB_SHADER_CONTROL = 0x0203 # macro -regDB_SHADER_CONTROL_BASE_IDX = 1 # macro -regPA_CL_CLIP_CNTL = 0x0204 # macro -regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro -regPA_SU_SC_MODE_CNTL = 0x0205 # macro -regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro -regPA_CL_VTE_CNTL = 0x0206 # macro -regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro -regPA_CL_VS_OUT_CNTL = 0x0207 # macro -regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro -regPA_CL_NANINF_CNTL = 0x0208 # macro -regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro -regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro -regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro -regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro -regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro -regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -regPA_CL_NGG_CNTL = 0x020e # macro -regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro -regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro -regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -regPA_STEREO_CNTL = 0x0210 # macro -regPA_STEREO_CNTL_BASE_IDX = 1 # macro -regPA_STATE_STEREO_X = 0x0211 # macro -regPA_STATE_STEREO_X_BASE_IDX = 1 # macro -regPA_CL_VRS_CNTL = 0x0212 # macro -regPA_CL_VRS_CNTL_BASE_IDX = 1 # macro -regPA_SU_POINT_SIZE = 0x0280 # macro -regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro -regPA_SU_POINT_MINMAX = 0x0281 # macro -regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro -regPA_SU_LINE_CNTL = 0x0282 # macro -regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro -regPA_SC_LINE_STIPPLE = 0x0283 # macro -regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro -regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro -regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro -regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro -regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro -regPA_SC_MODE_CNTL_0 = 0x0292 # macro -regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_MODE_CNTL_1 = 0x0293 # macro -regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro -regVGT_ENHANCE = 0x0294 # macro -regVGT_ENHANCE_BASE_IDX = 1 # macro -regIA_ENHANCE = 0x029c # macro -regIA_ENHANCE_BASE_IDX = 1 # macro -regVGT_DMA_SIZE = 0x029d # macro -regVGT_DMA_SIZE_BASE_IDX = 1 # macro -regVGT_DMA_MAX_SIZE = 0x029e # macro -regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro -regVGT_DMA_INDEX_TYPE = 0x029f # macro -regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro -regWD_ENHANCE = 0x02a0 # macro -regWD_ENHANCE_BASE_IDX = 1 # macro -regVGT_PRIMITIVEID_EN = 0x02a1 # macro -regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro -regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro -regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro -regVGT_PRIMITIVEID_RESET = 0x02a3 # macro -regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro -regVGT_EVENT_INITIATOR = 0x02a4 # macro -regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro -regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro -regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro -regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro -regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro -regVGT_REUSE_OFF = 0x02ad # macro -regVGT_REUSE_OFF_BASE_IDX = 1 # macro -regDB_HTILE_SURFACE = 0x02af # macro -regDB_HTILE_SURFACE_BASE_IDX = 1 # macro -regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro -regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro -regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro -regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro -regDB_PRELOAD_CONTROL = 0x02b2 # macro -regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro -regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro -regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro -regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro -regVGT_GS_MAX_VERT_OUT = 0x02ce # macro -regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro -regGE_NGG_SUBGRP_CNTL = 0x02d3 # macro -regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro -regVGT_TESS_DISTRIBUTION = 0x02d4 # macro -regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro -regVGT_SHADER_STAGES_EN = 0x02d5 # macro -regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro -regVGT_LS_HS_CONFIG = 0x02d6 # macro -regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro -regVGT_TF_PARAM = 0x02db # macro -regVGT_TF_PARAM_BASE_IDX = 1 # macro -regDB_ALPHA_TO_MASK = 0x02dc # macro -regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro -regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro -regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro -regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro -regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro -regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro -regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro -regVGT_GS_INSTANCE_CNT = 0x02e4 # macro -regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro -regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro -regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro -regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro -regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro -regPA_SC_LINE_CNTL = 0x02f7 # macro -regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro -regPA_SC_AA_CONFIG = 0x02f8 # macro -regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro -regPA_SU_VTX_CNTL = 0x02f9 # macro -regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro -regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro -regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro -regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro -regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro -regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro -regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro -regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro -regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro -regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro -regPA_SC_SHADER_CONTROL = 0x0310 # macro -regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_0 = 0x0311 # macro -regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_1 = 0x0312 # macro -regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro -regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -regPA_SC_NGG_MODE_CNTL = 0x0314 # macro -regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_2 = 0x0315 # macro -regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 # macro -regCB_COLOR0_BASE = 0x0318 # macro -regCB_COLOR0_BASE_BASE_IDX = 1 # macro -regCB_COLOR0_VIEW = 0x031b # macro -regCB_COLOR0_VIEW_BASE_IDX = 1 # macro -regCB_COLOR0_INFO = 0x031c # macro -regCB_COLOR0_INFO_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB = 0x031d # macro -regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR0_FDCC_CONTROL = 0x031e # macro -regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR0_DCC_BASE = 0x0325 # macro -regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR1_BASE = 0x0327 # macro -regCB_COLOR1_BASE_BASE_IDX = 1 # macro -regCB_COLOR1_VIEW = 0x032a # macro -regCB_COLOR1_VIEW_BASE_IDX = 1 # macro -regCB_COLOR1_INFO = 0x032b # macro -regCB_COLOR1_INFO_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB = 0x032c # macro -regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR1_FDCC_CONTROL = 0x032d # macro -regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR1_DCC_BASE = 0x0334 # macro -regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR2_BASE = 0x0336 # macro -regCB_COLOR2_BASE_BASE_IDX = 1 # macro -regCB_COLOR2_VIEW = 0x0339 # macro -regCB_COLOR2_VIEW_BASE_IDX = 1 # macro -regCB_COLOR2_INFO = 0x033a # macro -regCB_COLOR2_INFO_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB = 0x033b # macro -regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR2_FDCC_CONTROL = 0x033c # macro -regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR2_DCC_BASE = 0x0343 # macro -regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR3_BASE = 0x0345 # macro -regCB_COLOR3_BASE_BASE_IDX = 1 # macro -regCB_COLOR3_VIEW = 0x0348 # macro -regCB_COLOR3_VIEW_BASE_IDX = 1 # macro -regCB_COLOR3_INFO = 0x0349 # macro -regCB_COLOR3_INFO_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB = 0x034a # macro -regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR3_FDCC_CONTROL = 0x034b # macro -regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR3_DCC_BASE = 0x0352 # macro -regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR4_BASE = 0x0354 # macro -regCB_COLOR4_BASE_BASE_IDX = 1 # macro -regCB_COLOR4_VIEW = 0x0357 # macro -regCB_COLOR4_VIEW_BASE_IDX = 1 # macro -regCB_COLOR4_INFO = 0x0358 # macro -regCB_COLOR4_INFO_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB = 0x0359 # macro -regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR4_FDCC_CONTROL = 0x035a # macro -regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR4_DCC_BASE = 0x0361 # macro -regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR5_BASE = 0x0363 # macro -regCB_COLOR5_BASE_BASE_IDX = 1 # macro -regCB_COLOR5_VIEW = 0x0366 # macro -regCB_COLOR5_VIEW_BASE_IDX = 1 # macro -regCB_COLOR5_INFO = 0x0367 # macro -regCB_COLOR5_INFO_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB = 0x0368 # macro -regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR5_FDCC_CONTROL = 0x0369 # macro -regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR5_DCC_BASE = 0x0370 # macro -regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR6_BASE = 0x0372 # macro -regCB_COLOR6_BASE_BASE_IDX = 1 # macro -regCB_COLOR6_VIEW = 0x0375 # macro -regCB_COLOR6_VIEW_BASE_IDX = 1 # macro -regCB_COLOR6_INFO = 0x0376 # macro -regCB_COLOR6_INFO_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB = 0x0377 # macro -regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR6_FDCC_CONTROL = 0x0378 # macro -regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR6_DCC_BASE = 0x037f # macro -regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR7_BASE = 0x0381 # macro -regCB_COLOR7_BASE_BASE_IDX = 1 # macro -regCB_COLOR7_VIEW = 0x0384 # macro -regCB_COLOR7_VIEW_BASE_IDX = 1 # macro -regCB_COLOR7_INFO = 0x0385 # macro -regCB_COLOR7_INFO_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB = 0x0386 # macro -regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR7_FDCC_CONTROL = 0x0387 # macro -regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR7_DCC_BASE = 0x038e # macro -regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR0_BASE_EXT = 0x0390 # macro -regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR1_BASE_EXT = 0x0391 # macro -regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR2_BASE_EXT = 0x0392 # macro -regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR3_BASE_EXT = 0x0393 # macro -regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR4_BASE_EXT = 0x0394 # macro -regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR5_BASE_EXT = 0x0395 # macro -regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR6_BASE_EXT = 0x0396 # macro -regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR7_BASE_EXT = 0x0397 # macro -regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro -regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro -regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro -regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro -regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro -regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro -regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro -regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR7_DCC_BASE_EXT = 0x03af # macro -regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB2 = 0x03b0 # macro -regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB2 = 0x03b1 # macro -regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB2 = 0x03b2 # macro -regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB2 = 0x03b3 # macro -regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB2 = 0x03b4 # macro -regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB2 = 0x03b5 # macro -regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB2 = 0x03b6 # macro -regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB2 = 0x03b7 # macro -regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB3 = 0x03b8 # macro -regCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB3 = 0x03b9 # macro -regCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB3 = 0x03ba # macro -regCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB3 = 0x03bb # macro -regCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB3 = 0x03bc # macro -regCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB3 = 0x03bd # macro -regCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB3 = 0x03be # macro -regCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB3 = 0x03bf # macro -regCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro -regCONFIG_RESERVED_REG0 = 0x0800 # macro -regCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro -regCONFIG_RESERVED_REG1 = 0x0801 # macro -regCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro -regCP_MEC_CNTL = 0x0802 # macro -regCP_MEC_CNTL_BASE_IDX = 1 # macro -regCP_ME_CNTL = 0x0803 # macro -regCP_ME_CNTL_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL = 0x0900 # macro -regGRBM_GFX_CNTL_BASE_IDX = 1 # macro -regGRBM_NOWHERE = 0x0901 # macro -regGRBM_NOWHERE_BASE_IDX = 1 # macro -regPA_SC_VRS_SURFACE_CNTL = 0x0940 # macro -regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 # macro -regPA_SC_ENHANCE = 0x0941 # macro -regPA_SC_ENHANCE_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_1 = 0x0942 # macro -regPA_SC_ENHANCE_1_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_2 = 0x0943 # macro -regPA_SC_ENHANCE_2_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_3 = 0x0944 # macro -regPA_SC_ENHANCE_3_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 # macro -regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 # macro -regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 # macro -regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 # macro -regPA_SC_DSM_CNTL = 0x0948 # macro -regPA_SC_DSM_CNTL_BASE_IDX = 1 # macro -regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 # macro -regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 # macro -regPA_SC_FIFO_SIZE = 0x094a # macro -regPA_SC_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_SC_IF_FIFO_SIZE = 0x094b # macro -regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c # macro -regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 # macro -regPA_SC_ATM_CNTL = 0x094d # macro -regPA_SC_ATM_CNTL_BASE_IDX = 1 # macro -regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e # macro -regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 # macro -regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f # macro -regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 # macro -regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 # macro -regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 # macro -regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 # macro -regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 # macro -regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 # macro -regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 # macro -regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 # macro -regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 # macro -regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 # macro -regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b # macro -regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d # macro -regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_PH_INTERFACE_FIFO_SIZE = 0x095e # macro -regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_PH_ENHANCE = 0x095f # macro -regPA_PH_ENHANCE_BASE_IDX = 1 # macro -regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 # macro -regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 # macro -regSQ_RUNTIME_CONFIG = 0x09e0 # macro -regSQ_RUNTIME_CONFIG_BASE_IDX = 1 # macro -regSQ_DEBUG_STS_GLOBAL = 0x09e1 # macro -regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 # macro -regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 # macro -regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 # macro -regSH_MEM_BASES = 0x09e3 # macro -regSH_MEM_BASES_BASE_IDX = 1 # macro -regSH_MEM_CONFIG = 0x09e4 # macro -regSH_MEM_CONFIG_BASE_IDX = 1 # macro -regSQ_DEBUG = 0x09e5 # macro -regSQ_DEBUG_BASE_IDX = 1 # macro -regSQ_SHADER_TBA_LO = 0x09e6 # macro -regSQ_SHADER_TBA_LO_BASE_IDX = 1 # macro -regSQ_SHADER_TBA_HI = 0x09e7 # macro -regSQ_SHADER_TBA_HI_BASE_IDX = 1 # macro -regSQ_SHADER_TMA_LO = 0x09e8 # macro -regSQ_SHADER_TMA_LO_BASE_IDX = 1 # macro -regSQ_SHADER_TMA_HI = 0x09e9 # macro -regSQ_SHADER_TMA_HI_BASE_IDX = 1 # macro -regCP_DEBUG_2 = 0x1800 # macro -regCP_DEBUG_2_BASE_IDX = 1 # macro -regCP_FETCHER_SOURCE = 0x1801 # macro -regCP_FETCHER_SOURCE_BASE_IDX = 1 # macro -regCP_HPD_MES_ROQ_OFFSETS = 0x1821 # macro -regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 # macro -regCP_HPD_ROQ_OFFSETS = 0x1821 # macro -regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 # macro -regCP_HPD_STATUS0 = 0x1822 # macro -regCP_HPD_STATUS0_BASE_IDX = 1 # macro -regDIDT_INDEX_AUTO_INCR_EN = 0x1900 # macro -regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 # macro -regDIDT_EDC_CTRL = 0x1901 # macro -regDIDT_EDC_CTRL_BASE_IDX = 1 # macro -regDIDT_EDC_THROTTLE_CTRL = 0x1902 # macro -regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 # macro -regDIDT_EDC_THRESHOLD = 0x1903 # macro -regDIDT_EDC_THRESHOLD_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 # macro -regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 # macro -regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 # macro -regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_7 = 0x1907 # macro -regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 # macro -regDIDT_EDC_STATUS = 0x1908 # macro -regDIDT_EDC_STATUS_BASE_IDX = 1 # macro -regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 # macro -regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 # macro -regDIDT_EDC_OVERFLOW = 0x190a # macro -regDIDT_EDC_OVERFLOW_BASE_IDX = 1 # macro -regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b # macro -regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro -regDIDT_IND_INDEX = 0x190c # macro -regDIDT_IND_INDEX_BASE_IDX = 1 # macro -regDIDT_IND_DATA = 0x190d # macro -regDIDT_IND_DATA_BASE_IDX = 1 # macro -regSPI_GDBG_WAVE_CNTL = 0x1943 # macro -regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 # macro -regSPI_GDBG_TRAP_CONFIG = 0x1944 # macro -regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 # macro -regSPI_GDBG_WAVE_CNTL3 = 0x1945 # macro -regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 # macro -regSPI_ARB_CNTL_0 = 0x1949 # macro -regSPI_ARB_CNTL_0_BASE_IDX = 1 # macro -regSPI_FEATURE_CTRL = 0x194a # macro -regSPI_FEATURE_CTRL_BASE_IDX = 1 # macro -regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b # macro -regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 # macro -regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e # macro -regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 # macro -regTCP_INVALIDATE = 0x19a0 # macro -regTCP_INVALIDATE_BASE_IDX = 1 # macro -regTCP_STATUS = 0x19a1 # macro -regTCP_STATUS_BASE_IDX = 1 # macro -regTCP_CNTL = 0x19a2 # macro -regTCP_CNTL_BASE_IDX = 1 # macro -regTCP_CNTL2 = 0x19a3 # macro -regTCP_CNTL2_BASE_IDX = 1 # macro -regTCP_DEBUG_INDEX = 0x19a5 # macro -regTCP_DEBUG_INDEX_BASE_IDX = 1 # macro -regTCP_DEBUG_DATA = 0x19a6 # macro -regTCP_DEBUG_DATA_BASE_IDX = 1 # macro -regGDS_ENHANCE2 = 0x19b0 # macro -regGDS_ENHANCE2_BASE_IDX = 1 # macro -regGDS_OA_CGPG_RESTORE = 0x19b1 # macro -regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 # macro -regUTCL1_CTRL_0 = 0x1980 # macro -regUTCL1_CTRL_0_BASE_IDX = 1 # macro -regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 # macro -regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 # macro -regUTCL1_CTRL_2 = 0x1985 # macro -regUTCL1_CTRL_2_BASE_IDX = 1 # macro -regUTCL1_FIFO_SIZING = 0x1986 # macro -regUTCL1_FIFO_SIZING_BASE_IDX = 1 # macro -regGCRD_SA0_TARGETS_DISABLE = 0x1987 # macro -regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 # macro -regGCRD_SA1_TARGETS_DISABLE = 0x1989 # macro -regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 # macro -regGCRD_CREDIT_SAFE = 0x198a # macro -regGCRD_CREDIT_SAFE_BASE_IDX = 1 # macro -regGCR_GENERAL_CNTL = 0x1990 # macro -regGCR_GENERAL_CNTL_BASE_IDX = 1 # macro -regGCR_CMD_STATUS = 0x1992 # macro -regGCR_CMD_STATUS_BASE_IDX = 1 # macro -regGCR_SPARE = 0x1993 # macro -regGCR_SPARE_BASE_IDX = 1 # macro -regPMM_CNTL2 = 0x1999 # macro -regPMM_CNTL2_BASE_IDX = 1 # macro -regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 # macro -regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 # macro -regGC_CAC_CTRL_1 = 0x1ad0 # macro -regGC_CAC_CTRL_1_BASE_IDX = 1 # macro -regGC_CAC_CTRL_2 = 0x1ad1 # macro -regGC_CAC_CTRL_2_BASE_IDX = 1 # macro -regGC_CAC_AGGR_LOWER = 0x1ad2 # macro -regGC_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regGC_CAC_AGGR_UPPER = 0x1ad3 # macro -regGC_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_LOWER = 0x1ad4 # macro -regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_UPPER = 0x1ad5 # macro -regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_LOWER = 0x1ad6 # macro -regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_UPPER = 0x1ad7 # macro -regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_LOWER = 0x1ad8 # macro -regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_UPPER = 0x1ad9 # macro -regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_LOWER = 0x1ada # macro -regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_UPPER = 0x1adb # macro -regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_LOWER = 0x1adc # macro -regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_UPPER = 0x1add # macro -regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_LOWER = 0x1ade # macro -regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_UPPER = 0x1adf # macro -regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 # macro -regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 # macro -regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 # macro -regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 # macro -regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 # macro -regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 # macro -regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea # macro -regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regGC_EDC_CTRL = 0x1aed # macro -regGC_EDC_CTRL_BASE_IDX = 1 # macro -regGC_EDC_THRESHOLD = 0x1aee # macro -regGC_EDC_THRESHOLD_BASE_IDX = 1 # macro -regGC_EDC_STRETCH_CTRL = 0x1aef # macro -regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 # macro -regGC_EDC_STRETCH_THRESHOLD = 0x1af0 # macro -regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 # macro -regEDC_HYSTERESIS_CNTL = 0x1af1 # macro -regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro -regGC_THROTTLE_CTRL = 0x1af2 # macro -regGC_THROTTLE_CTRL_BASE_IDX = 1 # macro -regGC_THROTTLE_CTRL1 = 0x1af3 # macro -regGC_THROTTLE_CTRL1_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_CTRL = 0x1af4 # macro -regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 # macro -regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_1_2 = 0x1af6 # macro -regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_3_4 = 0x1af7 # macro -regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_5_6 = 0x1af8 # macro -regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_7 = 0x1af9 # macro -regPCC_STALL_PATTERN_7_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_1_2 = 0x1afa # macro -regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_3_4 = 0x1afb # macro -regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_5_6 = 0x1afc # macro -regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_7 = 0x1afd # macro -regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_CTRL = 0x1afe # macro -regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_1_2 = 0x1aff # macro -regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_3_4 = 0x1b00 # macro -regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_5_6 = 0x1b01 # macro -regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_7 = 0x1b02 # macro -regDIDT_STALL_PATTERN_7_BASE_IDX = 1 # macro -regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 # macro -regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 # macro -regEDC_STRETCH_PERF_COUNTER = 0x1b04 # macro -regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 # macro -regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 # macro -regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 # macro -regGC_EDC_STATUS = 0x1b07 # macro -regGC_EDC_STATUS_BASE_IDX = 1 # macro -regGC_EDC_OVERFLOW = 0x1b08 # macro -regGC_EDC_OVERFLOW_BASE_IDX = 1 # macro -regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 # macro -regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro -regGC_THROTTLE_STATUS = 0x1b0a # macro -regGC_THROTTLE_STATUS_BASE_IDX = 1 # macro -regEDC_PERF_COUNTER = 0x1b0b # macro -regEDC_PERF_COUNTER_BASE_IDX = 1 # macro -regPCC_PERF_COUNTER = 0x1b0c # macro -regPCC_PERF_COUNTER_BASE_IDX = 1 # macro -regPWRBRK_PERF_COUNTER = 0x1b0d # macro -regPWRBRK_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_HYSTERESIS_STAT = 0x1b0e # macro -regEDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CP_0 = 0x1b10 # macro -regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CP_1 = 0x1b11 # macro -regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_0 = 0x1b12 # macro -regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_1 = 0x1b13 # macro -regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_2 = 0x1b14 # macro -regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a # macro -regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b # macro -regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c # macro -regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_0 = 0x1b20 # macro -regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_1 = 0x1b21 # macro -regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_2 = 0x1b22 # macro -regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_0 = 0x1b23 # macro -regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_1 = 0x1b24 # macro -regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_2 = 0x1b25 # macro -regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_3 = 0x1b26 # macro -regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_4 = 0x1b27 # macro -regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_5 = 0x1b28 # macro -regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_6 = 0x1b29 # macro -regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PMM_0 = 0x1b2e # macro -regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f # macro -regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 # macro -regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 # macro -regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_0 = 0x1b32 # macro -regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_1 = 0x1b33 # macro -regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_2 = 0x1b34 # macro -regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_3 = 0x1b35 # macro -regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 # macro -regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 # macro -regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 # macro -regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 # macro -regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a # macro -regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b # macro -regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CHC_0 = 0x1b3c # macro -regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CHC_1 = 0x1b3d # macro -regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GUS_0 = 0x1b3e # macro -regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GUS_1 = 0x1b3f # macro -regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_RLC_0 = 0x1b40 # macro -regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 # macro -regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 # macro -regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 # macro -regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 # macro -regGC_CAC_IND_INDEX = 0x1b58 # macro -regGC_CAC_IND_INDEX_BASE_IDX = 1 # macro -regGC_CAC_IND_DATA = 0x1b59 # macro -regGC_CAC_IND_DATA_BASE_IDX = 1 # macro -regSE_CAC_CTRL_1 = 0x1b70 # macro -regSE_CAC_CTRL_1_BASE_IDX = 1 # macro -regSE_CAC_CTRL_2 = 0x1b71 # macro -regSE_CAC_CTRL_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TA_0 = 0x1b72 # macro -regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_0 = 0x1b73 # macro -regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_1 = 0x1b74 # macro -regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_2 = 0x1b75 # macro -regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_3 = 0x1b76 # macro -regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_4 = 0x1b77 # macro -regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_5 = 0x1b78 # macro -regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_0 = 0x1b79 # macro -regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_1 = 0x1b7a # macro -regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_2 = 0x1b7b # macro -regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_3 = 0x1b7c # macro -regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_0 = 0x1b7d # macro -regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_1 = 0x1b7e # macro -regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_2 = 0x1b7f # macro -regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SP_0 = 0x1b80 # macro -regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SP_1 = 0x1b81 # macro -regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_0 = 0x1b82 # macro -regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_1 = 0x1b83 # macro -regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_2 = 0x1b84 # macro -regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_3 = 0x1b85 # macro -regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQC_0 = 0x1b87 # macro -regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQC_1 = 0x1b88 # macro -regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CU_0 = 0x1b89 # macro -regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_BCI_0 = 0x1b8a # macro -regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_0 = 0x1b8b # macro -regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_1 = 0x1b8c # macro -regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_2 = 0x1b8d # macro -regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_3 = 0x1b8e # macro -regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_4 = 0x1b8f # macro -regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_5 = 0x1b90 # macro -regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_6 = 0x1b91 # macro -regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_7 = 0x1b92 # macro -regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_8 = 0x1b93 # macro -regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_9 = 0x1b94 # macro -regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_10 = 0x1b95 # macro -regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_11 = 0x1b96 # macro -regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_0 = 0x1b97 # macro -regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_1 = 0x1b98 # macro -regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_2 = 0x1b99 # macro -regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_3 = 0x1b9a # macro -regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_4 = 0x1b9b # macro -regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_RMI_0 = 0x1b9c # macro -regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_RMI_1 = 0x1b9d # macro -regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SX_0 = 0x1b9e # macro -regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f # macro -regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 # macro -regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 # macro -regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 # macro -regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 # macro -regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 # macro -regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 # macro -regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 # macro -regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PC_0 = 0x1ba7 # macro -regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_0 = 0x1ba8 # macro -regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_1 = 0x1ba9 # macro -regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_2 = 0x1baa # macro -regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_3 = 0x1bab # macro -regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_0 = 0x1bac # macro -regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_1 = 0x1bad # macro -regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_2 = 0x1bae # macro -regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_3 = 0x1baf # macro -regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 # macro -regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 # macro -regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 # macro -regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 # macro -regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE_CAC_IND_INDEX = 0x1bce # macro -regSE_CAC_IND_INDEX_BASE_IDX = 1 # macro -regSE_CAC_IND_DATA = 0x1bcf # macro -regSE_CAC_IND_DATA_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 # macro -regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 # macro -regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 # macro -regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 # macro -regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 # macro -regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 # macro -regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 # macro -regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 # macro -regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 # macro -regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 # macro -regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a # macro -regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b # macro -regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c # macro -regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d # macro -regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e # macro -regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f # macro -regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 # macro -regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 # macro -regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 # macro -regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 # macro -regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 # macro -regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 # macro -regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 # macro -regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 # macro -regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 # macro -regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 # macro -regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a # macro -regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b # macro -regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c # macro -regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d # macro -regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e # macro -regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f # macro -regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 # macro -regCP_EOP_DONE_ADDR_LO = 0x2000 # macro -regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro -regCP_EOP_DONE_ADDR_HI = 0x2001 # macro -regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_LO = 0x2002 # macro -regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_HI = 0x2003 # macro -regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro -regCP_EOP_LAST_FENCE_LO = 0x2004 # macro -regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro -regCP_EOP_LAST_FENCE_HI = 0x2005 # macro -regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro -regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro -regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro -regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro -regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro -regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro -regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro -regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro -regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro -regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro -regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro -regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro -regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro -regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro -regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro -regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro -regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro -regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro -regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro -regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro -regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro -regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PA_CPRIM_COUNT_LO = 0x202a # macro -regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_CPRIM_COUNT_HI = 0x202b # macro -regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro -regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro -regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro -regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro -regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro -regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro -regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro -regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_ASINVOC_COUNT_LO = 0x2032 # macro -regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_ASINVOC_COUNT_HI = 0x2033 # macro -regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PIPE_STATS_CONTROL = 0x203d # macro -regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro -regSCRATCH_REG0 = 0x2040 # macro -regSCRATCH_REG0_BASE_IDX = 1 # macro -regSCRATCH_REG1 = 0x2041 # macro -regSCRATCH_REG1_BASE_IDX = 1 # macro -regSCRATCH_REG2 = 0x2042 # macro -regSCRATCH_REG2_BASE_IDX = 1 # macro -regSCRATCH_REG3 = 0x2043 # macro -regSCRATCH_REG3_BASE_IDX = 1 # macro -regSCRATCH_REG4 = 0x2044 # macro -regSCRATCH_REG4_BASE_IDX = 1 # macro -regSCRATCH_REG5 = 0x2045 # macro -regSCRATCH_REG5_BASE_IDX = 1 # macro -regSCRATCH_REG6 = 0x2046 # macro -regSCRATCH_REG6_BASE_IDX = 1 # macro -regSCRATCH_REG7 = 0x2047 # macro -regSCRATCH_REG7_BASE_IDX = 1 # macro -regSCRATCH_REG_ATOMIC = 0x2048 # macro -regSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro -regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro -regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro -regCP_APPEND_DDID_CNT = 0x204b # macro -regCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro -regCP_APPEND_DATA_HI = 0x204c # macro -regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro -regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro -regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro -regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro -regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro -regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_APPEND_ADDR_LO = 0x2058 # macro -regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro -regCP_APPEND_ADDR_HI = 0x2059 # macro -regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro -regCP_APPEND_DATA = 0x205a # macro -regCP_APPEND_DATA_BASE_IDX = 1 # macro -regCP_APPEND_DATA_LO = 0x205a # macro -regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE = 0x205b # macro -regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro -regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE = 0x205c # macro -regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro -regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro -regCP_ATOMIC_PREOP_LO = 0x205d # macro -regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro -regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_ATOMIC_PREOP_HI = 0x205e # macro -regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro -regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_MC_WADDR_LO = 0x2069 # macro -regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro -regCP_ME_MC_WADDR_HI = 0x206a # macro -regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro -regCP_ME_MC_WDATA_LO = 0x206b # macro -regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro -regCP_ME_MC_WDATA_HI = 0x206c # macro -regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro -regCP_ME_MC_RADDR_LO = 0x206d # macro -regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro -regCP_ME_MC_RADDR_HI = 0x206e # macro -regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro -regCP_SEM_WAIT_TIMER = 0x206f # macro -regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro -regCP_SIG_SEM_ADDR_LO = 0x2070 # macro -regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro -regCP_SIG_SEM_ADDR_HI = 0x2071 # macro -regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro -regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro -regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro -regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro -regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro -regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro -regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_CONTROL = 0x2077 # macro -regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro -regCP_DMA_ME_CONTROL = 0x2078 # macro -regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro -regCP_DMA_ME_SRC_ADDR = 0x2080 # macro -regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro -regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro -regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_ME_DST_ADDR = 0x2082 # macro -regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro -regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro -regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_ME_COMMAND = 0x2084 # macro -regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro -regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro -regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro -regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro -regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_DST_ADDR = 0x2087 # macro -regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro -regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro -regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_COMMAND = 0x2089 # macro -regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro -regCP_DMA_CNTL = 0x208a # macro -regCP_DMA_CNTL_BASE_IDX = 1 # macro -regCP_DMA_READ_TAGS = 0x208b # macro -regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro -regCP_PFP_IB_CONTROL = 0x208d # macro -regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro -regCP_PFP_LOAD_CONTROL = 0x208e # macro -regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro -regCP_SCRATCH_INDEX = 0x208f # macro -regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro -regCP_SCRATCH_DATA = 0x2090 # macro -regCP_SCRATCH_DATA_BASE_IDX = 1 # macro -regCP_RB_OFFSET = 0x2091 # macro -regCP_RB_OFFSET_BASE_IDX = 1 # macro -regCP_IB2_OFFSET = 0x2093 # macro -regCP_IB2_OFFSET_BASE_IDX = 1 # macro -regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro -regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro -regCP_IB2_PREAMBLE_END = 0x2097 # macro -regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro -regCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro -regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro -regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro -regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro -regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro -regCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro -regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro -regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro -regUCONFIG_RESERVED_REG0 = 0x20a2 # macro -regUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro -regUCONFIG_RESERVED_REG1 = 0x20a3 # macro -regUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro -regCP_PA_MSPRIM_COUNT_LO = 0x20a4 # macro -regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_MSPRIM_COUNT_HI = 0x20a5 # macro -regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_GE_MSINVOC_COUNT_LO = 0x20a6 # macro -regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_GE_MSINVOC_COUNT_HI = 0x20a7 # macro -regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_IB1_CMD_BUFSZ = 0x20c0 # macro -regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_IB2_CMD_BUFSZ = 0x20c1 # macro -regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_ST_CMD_BUFSZ = 0x20c2 # macro -regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_IB1_BASE_LO = 0x20cc # macro -regCP_IB1_BASE_LO_BASE_IDX = 1 # macro -regCP_IB1_BASE_HI = 0x20cd # macro -regCP_IB1_BASE_HI_BASE_IDX = 1 # macro -regCP_IB1_BUFSZ = 0x20ce # macro -regCP_IB1_BUFSZ_BASE_IDX = 1 # macro -regCP_IB2_BASE_LO = 0x20cf # macro -regCP_IB2_BASE_LO_BASE_IDX = 1 # macro -regCP_IB2_BASE_HI = 0x20d0 # macro -regCP_IB2_BASE_HI_BASE_IDX = 1 # macro -regCP_IB2_BUFSZ = 0x20d1 # macro -regCP_IB2_BUFSZ_BASE_IDX = 1 # macro -regCP_ST_BASE_LO = 0x20d2 # macro -regCP_ST_BASE_LO_BASE_IDX = 1 # macro -regCP_ST_BASE_HI = 0x20d3 # macro -regCP_ST_BASE_HI_BASE_IDX = 1 # macro -regCP_ST_BUFSZ = 0x20d4 # macro -regCP_ST_BUFSZ_BASE_IDX = 1 # macro -regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro -regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro -regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro -regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro -regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro -regCP_DB_BASE_LO = 0x20d8 # macro -regCP_DB_BASE_LO_BASE_IDX = 1 # macro -regCP_DB_BASE_HI = 0x20d9 # macro -regCP_DB_BASE_HI_BASE_IDX = 1 # macro -regCP_DB_BUFSZ = 0x20da # macro -regCP_DB_BUFSZ_BASE_IDX = 1 # macro -regCP_DB_CMD_BUFSZ = 0x20db # macro -regCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_PFP_COMPLETION_STATUS = 0x20ec # macro -regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro -regCP_PRED_NOT_VISIBLE = 0x20ee # macro -regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro -regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro -regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro -regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro -regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro -regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro -regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro -regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro -regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro -regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro -regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro -regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro -regCP_INDEX_BASE_ADDR = 0x20f8 # macro -regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro -regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro -regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCP_INDEX_TYPE = 0x20fa # macro -regCP_INDEX_TYPE_BASE_IDX = 1 # macro -regCP_GDS_BKUP_ADDR = 0x20fb # macro -regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro -regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro -regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro -regCP_SAMPLE_STATUS = 0x20fd # macro -regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro -regCP_ME_COHER_CNTL = 0x20fe # macro -regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro -regCP_ME_COHER_SIZE = 0x20ff # macro -regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro -regCP_ME_COHER_SIZE_HI = 0x2100 # macro -regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro -regCP_ME_COHER_BASE = 0x2101 # macro -regCP_ME_COHER_BASE_BASE_IDX = 1 # macro -regCP_ME_COHER_BASE_HI = 0x2102 # macro -regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro -regCP_ME_COHER_STATUS = 0x2103 # macro -regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro -regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro -regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro -regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro -regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX = 0x2200 # macro -regGRBM_GFX_INDEX_BASE_IDX = 1 # macro -regVGT_PRIMITIVE_TYPE = 0x2242 # macro -regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro -regVGT_INDEX_TYPE = 0x2243 # macro -regVGT_INDEX_TYPE_BASE_IDX = 1 # macro -regGE_MIN_VTX_INDX = 0x2249 # macro -regGE_MIN_VTX_INDX_BASE_IDX = 1 # macro -regGE_INDX_OFFSET = 0x224a # macro -regGE_INDX_OFFSET_BASE_IDX = 1 # macro -regGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro -regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro -regVGT_NUM_INDICES = 0x224c # macro -regVGT_NUM_INDICES_BASE_IDX = 1 # macro -regVGT_NUM_INSTANCES = 0x224d # macro -regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro -regVGT_TF_RING_SIZE = 0x224e # macro -regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro -regVGT_HS_OFFCHIP_PARAM = 0x224f # macro -regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro -regVGT_TF_MEMORY_BASE = 0x2250 # macro -regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro -regGE_MAX_VTX_INDX = 0x2259 # macro -regGE_MAX_VTX_INDX_BASE_IDX = 1 # macro -regVGT_INSTANCE_BASE_ID = 0x225a # macro -regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro -regGE_CNTL = 0x225b # macro -regGE_CNTL_BASE_IDX = 1 # macro -regGE_USER_VGPR1 = 0x225c # macro -regGE_USER_VGPR1_BASE_IDX = 1 # macro -regGE_USER_VGPR2 = 0x225d # macro -regGE_USER_VGPR2_BASE_IDX = 1 # macro -regGE_USER_VGPR3 = 0x225e # macro -regGE_USER_VGPR3_BASE_IDX = 1 # macro -regGE_STEREO_CNTL = 0x225f # macro -regGE_STEREO_CNTL_BASE_IDX = 1 # macro -regGE_PC_ALLOC = 0x2260 # macro -regGE_PC_ALLOC_BASE_IDX = 1 # macro -regVGT_TF_MEMORY_BASE_HI = 0x2261 # macro -regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro -regGE_USER_VGPR_EN = 0x2262 # macro -regGE_USER_VGPR_EN_BASE_IDX = 1 # macro -regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 # macro -regVGT_GS_OUT_PRIM_TYPE = 0x2266 # macro -regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro -regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro -regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro -regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro -regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro -regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro -regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro -regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro -regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro -regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro -regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro -regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro -regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro -regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro -regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro -regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro -regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro -regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro -regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro -regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro -regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro -regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro -regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro -regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro -regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro -regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro -regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro -regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro -regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro -regSQC_CACHES = 0x2348 # macro -regSQC_CACHES_BASE_IDX = 1 # macro -regTA_CS_BC_BASE_ADDR = 0x2380 # macro -regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro -regTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro -regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro -regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro -regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro -regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro -regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro -regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro -regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro -regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro -regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro -regGDS_RD_ADDR = 0x2400 # macro -regGDS_RD_ADDR_BASE_IDX = 1 # macro -regGDS_RD_DATA = 0x2401 # macro -regGDS_RD_DATA_BASE_IDX = 1 # macro -regGDS_RD_BURST_ADDR = 0x2402 # macro -regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro -regGDS_RD_BURST_COUNT = 0x2403 # macro -regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro -regGDS_RD_BURST_DATA = 0x2404 # macro -regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro -regGDS_WR_ADDR = 0x2405 # macro -regGDS_WR_ADDR_BASE_IDX = 1 # macro -regGDS_WR_DATA = 0x2406 # macro -regGDS_WR_DATA_BASE_IDX = 1 # macro -regGDS_WR_BURST_ADDR = 0x2407 # macro -regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro -regGDS_WR_BURST_DATA = 0x2408 # macro -regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro -regGDS_WRITE_COMPLETE = 0x2409 # macro -regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro -regGDS_ATOM_CNTL = 0x240a # macro -regGDS_ATOM_CNTL_BASE_IDX = 1 # macro -regGDS_ATOM_COMPLETE = 0x240b # macro -regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro -regGDS_ATOM_BASE = 0x240c # macro -regGDS_ATOM_BASE_BASE_IDX = 1 # macro -regGDS_ATOM_SIZE = 0x240d # macro -regGDS_ATOM_SIZE_BASE_IDX = 1 # macro -regGDS_ATOM_OFFSET0 = 0x240e # macro -regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro -regGDS_ATOM_OFFSET1 = 0x240f # macro -regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro -regGDS_ATOM_DST = 0x2410 # macro -regGDS_ATOM_DST_BASE_IDX = 1 # macro -regGDS_ATOM_OP = 0x2411 # macro -regGDS_ATOM_OP_BASE_IDX = 1 # macro -regGDS_ATOM_SRC0 = 0x2412 # macro -regGDS_ATOM_SRC0_BASE_IDX = 1 # macro -regGDS_ATOM_SRC0_U = 0x2413 # macro -regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro -regGDS_ATOM_SRC1 = 0x2414 # macro -regGDS_ATOM_SRC1_BASE_IDX = 1 # macro -regGDS_ATOM_SRC1_U = 0x2415 # macro -regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro -regGDS_ATOM_READ0 = 0x2416 # macro -regGDS_ATOM_READ0_BASE_IDX = 1 # macro -regGDS_ATOM_READ0_U = 0x2417 # macro -regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro -regGDS_ATOM_READ1 = 0x2418 # macro -regGDS_ATOM_READ1_BASE_IDX = 1 # macro -regGDS_ATOM_READ1_U = 0x2419 # macro -regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE_CNTL = 0x241a # macro -regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE = 0x241b # macro -regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE_CNT = 0x241c # macro -regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro -regGDS_OA_CNTL = 0x241d # macro -regGDS_OA_CNTL_BASE_IDX = 1 # macro -regGDS_OA_COUNTER = 0x241e # macro -regGDS_OA_COUNTER_BASE_IDX = 1 # macro -regGDS_OA_ADDRESS = 0x241f # macro -regGDS_OA_ADDRESS_BASE_IDX = 1 # macro -regGDS_OA_INCDEC = 0x2420 # macro -regGDS_OA_INCDEC_BASE_IDX = 1 # macro -regGDS_OA_RING_SIZE = 0x2421 # macro -regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 # macro -regGDS_GS_0 = 0x2426 # macro -regGDS_GS_0_BASE_IDX = 1 # macro -regGDS_GS_1 = 0x2427 # macro -regGDS_GS_1_BASE_IDX = 1 # macro -regGDS_GS_2 = 0x2428 # macro -regGDS_GS_2_BASE_IDX = 1 # macro -regGDS_GS_3 = 0x2429 # macro -regGDS_GS_3_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL = 0x2440 # macro -regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL_1 = 0x2441 # macro -regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL_2 = 0x2442 # macro -regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro -regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro -regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro -regSPI_GS_THROTTLE_CNTL1 = 0x2444 # macro -regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 # macro -regSPI_GS_THROTTLE_CNTL2 = 0x2445 # macro -regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 # macro -regSPI_ATTRIBUTE_RING_BASE = 0x2446 # macro -regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 # macro -regSPI_ATTRIBUTE_RING_SIZE = 0x2447 # macro -regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 # macro -regCP_MES_PRGRM_CNTR_START = 0x2800 # macro -regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro -regCP_MES_INTR_ROUTINE_START = 0x2801 # macro -regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro -regCP_MES_MTVEC_LO = 0x2801 # macro -regCP_MES_MTVEC_LO_BASE_IDX = 1 # macro -regCP_MES_INTR_ROUTINE_START_HI = 0x2802 # macro -regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 # macro -regCP_MES_MTVEC_HI = 0x2802 # macro -regCP_MES_MTVEC_HI_BASE_IDX = 1 # macro -regCP_MES_CNTL = 0x2807 # macro -regCP_MES_CNTL_BASE_IDX = 1 # macro -regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro -regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro -regCP_MES_PIPE0_PRIORITY = 0x2809 # macro -regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE1_PRIORITY = 0x280a # macro -regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE2_PRIORITY = 0x280b # macro -regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE3_PRIORITY = 0x280c # macro -regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_HEADER_DUMP = 0x280d # macro -regCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro -regCP_MES_MIE_LO = 0x280e # macro -regCP_MES_MIE_LO_BASE_IDX = 1 # macro -regCP_MES_MIE_HI = 0x280f # macro -regCP_MES_MIE_HI_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT = 0x2810 # macro -regCP_MES_INTERRUPT_BASE_IDX = 1 # macro -regCP_MES_SCRATCH_INDEX = 0x2811 # macro -regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro -regCP_MES_SCRATCH_DATA = 0x2812 # macro -regCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro -regCP_MES_INSTR_PNTR = 0x2813 # macro -regCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MES_MSCRATCH_HI = 0x2814 # macro -regCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro -regCP_MES_MSCRATCH_LO = 0x2815 # macro -regCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro -regCP_MES_MSTATUS_LO = 0x2816 # macro -regCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro -regCP_MES_MSTATUS_HI = 0x2817 # macro -regCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro -regCP_MES_MEPC_LO = 0x2818 # macro -regCP_MES_MEPC_LO_BASE_IDX = 1 # macro -regCP_MES_MEPC_HI = 0x2819 # macro -regCP_MES_MEPC_HI_BASE_IDX = 1 # macro -regCP_MES_MCAUSE_LO = 0x281a # macro -regCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro -regCP_MES_MCAUSE_HI = 0x281b # macro -regCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro -regCP_MES_MBADADDR_LO = 0x281c # macro -regCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro -regCP_MES_MBADADDR_HI = 0x281d # macro -regCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro -regCP_MES_MIP_LO = 0x281e # macro -regCP_MES_MIP_LO_BASE_IDX = 1 # macro -regCP_MES_MIP_HI = 0x281f # macro -regCP_MES_MIP_HI_BASE_IDX = 1 # macro -regCP_MES_IC_OP_CNTL = 0x2820 # macro -regCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MES_MCYCLE_LO = 0x2826 # macro -regCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro -regCP_MES_MCYCLE_HI = 0x2827 # macro -regCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro -regCP_MES_MTIME_LO = 0x2828 # macro -regCP_MES_MTIME_LO_BASE_IDX = 1 # macro -regCP_MES_MTIME_HI = 0x2829 # macro -regCP_MES_MTIME_HI_BASE_IDX = 1 # macro -regCP_MES_MINSTRET_LO = 0x282a # macro -regCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro -regCP_MES_MINSTRET_HI = 0x282b # macro -regCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro -regCP_MES_MISA_LO = 0x282c # macro -regCP_MES_MISA_LO_BASE_IDX = 1 # macro -regCP_MES_MISA_HI = 0x282d # macro -regCP_MES_MISA_HI_BASE_IDX = 1 # macro -regCP_MES_MVENDORID_LO = 0x282e # macro -regCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro -regCP_MES_MVENDORID_HI = 0x282f # macro -regCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro -regCP_MES_MARCHID_LO = 0x2830 # macro -regCP_MES_MARCHID_LO_BASE_IDX = 1 # macro -regCP_MES_MARCHID_HI = 0x2831 # macro -regCP_MES_MARCHID_HI_BASE_IDX = 1 # macro -regCP_MES_MIMPID_LO = 0x2832 # macro -regCP_MES_MIMPID_LO_BASE_IDX = 1 # macro -regCP_MES_MIMPID_HI = 0x2833 # macro -regCP_MES_MIMPID_HI_BASE_IDX = 1 # macro -regCP_MES_MHARTID_LO = 0x2834 # macro -regCP_MES_MHARTID_LO_BASE_IDX = 1 # macro -regCP_MES_MHARTID_HI = 0x2835 # macro -regCP_MES_MHARTID_HI_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_CNTL = 0x2836 # macro -regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_OP_CNTL = 0x2837 # macro -regCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MES_MTIMECMP_LO = 0x2838 # macro -regCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro -regCP_MES_MTIMECMP_HI = 0x2839 # macro -regCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro -regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro -regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro -regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro -regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL1 = 0x283c # macro -regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL2 = 0x283d # macro -regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL3 = 0x283e # macro -regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL4 = 0x283f # macro -regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro -regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro -regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro -regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 # macro -regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MES_GP0_LO = 0x2843 # macro -regCP_MES_GP0_LO_BASE_IDX = 1 # macro -regCP_MES_GP0_HI = 0x2844 # macro -regCP_MES_GP0_HI_BASE_IDX = 1 # macro -regCP_MES_GP1_LO = 0x2845 # macro -regCP_MES_GP1_LO_BASE_IDX = 1 # macro -regCP_MES_GP1_HI = 0x2846 # macro -regCP_MES_GP1_HI_BASE_IDX = 1 # macro -regCP_MES_GP2_LO = 0x2847 # macro -regCP_MES_GP2_LO_BASE_IDX = 1 # macro -regCP_MES_GP2_HI = 0x2848 # macro -regCP_MES_GP2_HI_BASE_IDX = 1 # macro -regCP_MES_GP3_LO = 0x2849 # macro -regCP_MES_GP3_LO_BASE_IDX = 1 # macro -regCP_MES_GP3_HI = 0x284a # macro -regCP_MES_GP3_HI_BASE_IDX = 1 # macro -regCP_MES_GP4_LO = 0x284b # macro -regCP_MES_GP4_LO_BASE_IDX = 1 # macro -regCP_MES_GP4_HI = 0x284c # macro -regCP_MES_GP4_HI_BASE_IDX = 1 # macro -regCP_MES_GP5_LO = 0x284d # macro -regCP_MES_GP5_LO_BASE_IDX = 1 # macro -regCP_MES_GP5_HI = 0x284e # macro -regCP_MES_GP5_HI_BASE_IDX = 1 # macro -regCP_MES_GP6_LO = 0x284f # macro -regCP_MES_GP6_LO_BASE_IDX = 1 # macro -regCP_MES_GP6_HI = 0x2850 # macro -regCP_MES_GP6_HI_BASE_IDX = 1 # macro -regCP_MES_GP7_LO = 0x2851 # macro -regCP_MES_GP7_LO_BASE_IDX = 1 # macro -regCP_MES_GP7_HI = 0x2852 # macro -regCP_MES_GP7_HI_BASE_IDX = 1 # macro -regCP_MES_GP8_LO = 0x2853 # macro -regCP_MES_GP8_LO_BASE_IDX = 1 # macro -regCP_MES_GP8_HI = 0x2854 # macro -regCP_MES_GP8_HI_BASE_IDX = 1 # macro -regCP_MES_GP9_LO = 0x2855 # macro -regCP_MES_GP9_LO_BASE_IDX = 1 # macro -regCP_MES_GP9_HI = 0x2856 # macro -regCP_MES_GP9_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_BASE0_LO = 0x2883 # macro -regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_BASE0_HI = 0x2884 # macro -regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_MASK0_LO = 0x2885 # macro -regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_MASK0_HI = 0x2886 # macro -regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_APERTURE = 0x2887 # macro -regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 # macro -regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 # macro -regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a # macro -regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b # macro -regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_APERTURE = 0x288c # macro -regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d # macro -regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e # macro -regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f # macro -regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_PERFCOUNT_CNTL = 0x2899 # macro -regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro -regCP_MES_PENDING_INTERRUPT = 0x289a # macro -regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro -regCP_MES_PRGRM_CNTR_START_HI = 0x289d # macro -regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_16 = 0x289f # macro -regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_17 = 0x28a0 # macro -regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_18 = 0x28a1 # macro -regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_19 = 0x28a2 # macro -regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_20 = 0x28a3 # macro -regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_21 = 0x28a4 # macro -regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_22 = 0x28a5 # macro -regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_23 = 0x28a6 # macro -regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_24 = 0x28a7 # macro -regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_25 = 0x28a8 # macro -regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_26 = 0x28a9 # macro -regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_27 = 0x28aa # macro -regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_28 = 0x28ab # macro -regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_29 = 0x28ac # macro -regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_30 = 0x28ad # macro -regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_31 = 0x28ae # macro -regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_BASE = 0x28af # macro -regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_MASK = 0x28b0 # macro -regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_CNTL = 0x28b1 # macro -regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_BASE = 0x28b2 # macro -regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_MASK = 0x28b3 # macro -regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_CNTL = 0x28b4 # macro -regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_BASE = 0x28b5 # macro -regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_MASK = 0x28b6 # macro -regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_CNTL = 0x28b7 # macro -regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_BASE = 0x28b8 # macro -regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_MASK = 0x28b9 # macro -regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_CNTL = 0x28ba # macro -regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_BASE = 0x28bb # macro -regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_MASK = 0x28bc # macro -regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_CNTL = 0x28bd # macro -regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_BASE = 0x28be # macro -regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_MASK = 0x28bf # macro -regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_CNTL = 0x28c0 # macro -regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_BASE = 0x28c1 # macro -regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_MASK = 0x28c2 # macro -regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_CNTL = 0x28c3 # macro -regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_BASE = 0x28c4 # macro -regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_MASK = 0x28c5 # macro -regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_CNTL = 0x28c6 # macro -regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_BASE = 0x28c7 # macro -regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_MASK = 0x28c8 # macro -regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_CNTL = 0x28c9 # macro -regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_BASE = 0x28ca # macro -regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_MASK = 0x28cb # macro -regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_CNTL = 0x28cc # macro -regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_BASE = 0x28cd # macro -regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_MASK = 0x28ce # macro -regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_CNTL = 0x28cf # macro -regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_BASE = 0x28d0 # macro -regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_MASK = 0x28d1 # macro -regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_CNTL = 0x28d2 # macro -regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_BASE = 0x28d3 # macro -regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_MASK = 0x28d4 # macro -regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_CNTL = 0x28d5 # macro -regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_BASE = 0x28d6 # macro -regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_MASK = 0x28d7 # macro -regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_CNTL = 0x28d8 # macro -regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_BASE = 0x28d9 # macro -regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_MASK = 0x28da # macro -regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_CNTL = 0x28db # macro -regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_BASE = 0x28dc # macro -regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_MASK = 0x28dd # macro -regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_CNTL = 0x28de # macro -regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 # macro -regCP_MEC_MTVEC_LO = 0x2901 # macro -regCP_MEC_MTVEC_LO_BASE_IDX = 1 # macro -regCP_MEC_MTVEC_HI = 0x2902 # macro -regCP_MEC_MTVEC_HI_BASE_IDX = 1 # macro -regCP_MEC_ISA_CNTL = 0x2903 # macro -regCP_MEC_ISA_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_CNTL = 0x2904 # macro -regCP_MEC_RS64_CNTL_BASE_IDX = 1 # macro -regCP_MEC_MIE_LO = 0x2905 # macro -regCP_MEC_MIE_LO_BASE_IDX = 1 # macro -regCP_MEC_MIE_HI = 0x2906 # macro -regCP_MEC_MIE_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT = 0x2907 # macro -regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 # macro -regCP_MEC_RS64_INSTR_PNTR = 0x2908 # macro -regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MEC_MIP_LO = 0x2909 # macro -regCP_MEC_MIP_LO_BASE_IDX = 1 # macro -regCP_MEC_MIP_HI = 0x290a # macro -regCP_MEC_MIP_HI_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_CNTL = 0x290b # macro -regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_OP_CNTL = 0x290c # macro -regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MEC_MTIMECMP_LO = 0x290d # macro -regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 # macro -regCP_MEC_MTIMECMP_HI = 0x290e # macro -regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 # macro -regCP_MEC_GP0_LO = 0x2910 # macro -regCP_MEC_GP0_LO_BASE_IDX = 1 # macro -regCP_MEC_GP0_HI = 0x2911 # macro -regCP_MEC_GP0_HI_BASE_IDX = 1 # macro -regCP_MEC_GP1_LO = 0x2912 # macro -regCP_MEC_GP1_LO_BASE_IDX = 1 # macro -regCP_MEC_GP1_HI = 0x2913 # macro -regCP_MEC_GP1_HI_BASE_IDX = 1 # macro -regCP_MEC_GP2_LO = 0x2914 # macro -regCP_MEC_GP2_LO_BASE_IDX = 1 # macro -regCP_MEC_GP2_HI = 0x2915 # macro -regCP_MEC_GP2_HI_BASE_IDX = 1 # macro -regCP_MEC_GP3_LO = 0x2916 # macro -regCP_MEC_GP3_LO_BASE_IDX = 1 # macro -regCP_MEC_GP3_HI = 0x2917 # macro -regCP_MEC_GP3_HI_BASE_IDX = 1 # macro -regCP_MEC_GP4_LO = 0x2918 # macro -regCP_MEC_GP4_LO_BASE_IDX = 1 # macro -regCP_MEC_GP4_HI = 0x2919 # macro -regCP_MEC_GP4_HI_BASE_IDX = 1 # macro -regCP_MEC_GP5_LO = 0x291a # macro -regCP_MEC_GP5_LO_BASE_IDX = 1 # macro -regCP_MEC_GP5_HI = 0x291b # macro -regCP_MEC_GP5_HI_BASE_IDX = 1 # macro -regCP_MEC_GP6_LO = 0x291c # macro -regCP_MEC_GP6_LO_BASE_IDX = 1 # macro -regCP_MEC_GP6_HI = 0x291d # macro -regCP_MEC_GP6_HI_BASE_IDX = 1 # macro -regCP_MEC_GP7_LO = 0x291e # macro -regCP_MEC_GP7_LO_BASE_IDX = 1 # macro -regCP_MEC_GP7_HI = 0x291f # macro -regCP_MEC_GP7_HI_BASE_IDX = 1 # macro -regCP_MEC_GP8_LO = 0x2920 # macro -regCP_MEC_GP8_LO_BASE_IDX = 1 # macro -regCP_MEC_GP8_HI = 0x2921 # macro -regCP_MEC_GP8_HI_BASE_IDX = 1 # macro -regCP_MEC_GP9_LO = 0x2922 # macro -regCP_MEC_GP9_LO_BASE_IDX = 1 # macro -regCP_MEC_GP9_HI = 0x2923 # macro -regCP_MEC_GP9_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_BASE0_LO = 0x2927 # macro -regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_BASE0_HI = 0x2928 # macro -regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_MASK0_LO = 0x2929 # macro -regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_MASK0_HI = 0x292a # macro -regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_APERTURE = 0x292b # macro -regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c # macro -regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d # macro -regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e # macro -regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f # macro -regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 # macro -regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 # macro -regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 # macro -regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 # macro -regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a # macro -regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b # macro -regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c # macro -regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d # macro -regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e # macro -regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f # macro -regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 # macro -regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 # macro -regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 # macro -regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 # macro -regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 # macro -regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 # macro -regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 # macro -regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 # macro -regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 # macro -regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 # macro -regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_BASE = 0x294a # macro -regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_MASK = 0x294b # macro -regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_CNTL = 0x294c # macro -regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_BASE = 0x294d # macro -regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_MASK = 0x294e # macro -regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_CNTL = 0x294f # macro -regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_BASE = 0x2950 # macro -regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_MASK = 0x2951 # macro -regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_CNTL = 0x2952 # macro -regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_BASE = 0x2953 # macro -regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_MASK = 0x2954 # macro -regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_CNTL = 0x2955 # macro -regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_BASE = 0x2956 # macro -regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_MASK = 0x2957 # macro -regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_CNTL = 0x2958 # macro -regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_BASE = 0x2959 # macro -regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_MASK = 0x295a # macro -regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_CNTL = 0x295b # macro -regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_BASE = 0x295c # macro -regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_MASK = 0x295d # macro -regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_CNTL = 0x295e # macro -regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_BASE = 0x295f # macro -regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_MASK = 0x2960 # macro -regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_CNTL = 0x2961 # macro -regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_BASE = 0x2962 # macro -regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_MASK = 0x2963 # macro -regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_CNTL = 0x2964 # macro -regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_BASE = 0x2965 # macro -regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_MASK = 0x2966 # macro -regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_CNTL = 0x2967 # macro -regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_BASE = 0x2968 # macro -regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_MASK = 0x2969 # macro -regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_CNTL = 0x296a # macro -regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_BASE = 0x296b # macro -regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_MASK = 0x296c # macro -regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_CNTL = 0x296d # macro -regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_BASE = 0x296e # macro -regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_MASK = 0x296f # macro -regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_CNTL = 0x2970 # macro -regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_BASE = 0x2971 # macro -regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_MASK = 0x2972 # macro -regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_CNTL = 0x2973 # macro -regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_BASE = 0x2974 # macro -regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_MASK = 0x2975 # macro -regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_CNTL = 0x2976 # macro -regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_BASE = 0x2977 # macro -regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_MASK = 0x2978 # macro -regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_CNTL = 0x2979 # macro -regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro -regCP_CPC_IC_OP_CNTL = 0x297a # macro -regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_GFX_CNTL = 0x2a00 # macro -regCP_GFX_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTERRUPT0 = 0x2a01 # macro -regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTR_EN0 = 0x2a02 # macro -regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTR_EN1 = 0x2a03 # macro -regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 # macro -regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 # macro -regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a # macro -regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b # macro -regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c # macro -regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d # macro -regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e # macro -regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 # macro -regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a # macro -regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b # macro -regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_LO0 = 0x2a1c # macro -regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_LO1 = 0x2a1d # macro -regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_HI0 = 0x2a1e # macro -regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_HI1 = 0x2a1f # macro -regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 # macro -regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 # macro -regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 # macro -regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 # macro -regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_LO0 = 0x2a24 # macro -regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_LO1 = 0x2a25 # macro -regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_HI0 = 0x2a26 # macro -regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_HI1 = 0x2a27 # macro -regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_LO0 = 0x2a28 # macro -regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_LO1 = 0x2a29 # macro -regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_HI0 = 0x2a2a # macro -regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_HI1 = 0x2a2b # macro -regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_LO0 = 0x2a2c # macro -regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_LO1 = 0x2a2d # macro -regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_HI0 = 0x2a2e # macro -regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_HI1 = 0x2a2f # macro -regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_LO0 = 0x2a30 # macro -regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_LO1 = 0x2a31 # macro -regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_HI0 = 0x2a32 # macro -regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_HI1 = 0x2a33 # macro -regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_LO0 = 0x2a34 # macro -regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_LO1 = 0x2a35 # macro -regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_HI0 = 0x2a36 # macro -regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_HI1 = 0x2a37 # macro -regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_LO0 = 0x2a38 # macro -regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_LO1 = 0x2a39 # macro -regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_HI0 = 0x2a3a # macro -regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_HI1 = 0x2a3b # macro -regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP6_LO = 0x2a3c # macro -regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP6_HI = 0x2a3d # macro -regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP7_LO = 0x2a3e # macro -regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP7_HI = 0x2a3f # macro -regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP8_LO = 0x2a40 # macro -regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP8_HI = 0x2a41 # macro -regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP9_LO = 0x2a42 # macro -regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP9_HI = 0x2a43 # macro -regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 # macro -regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 # macro -regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 # macro -regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 # macro -regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 # macro -regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 # macro -regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a # macro -regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c # macro -regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d # macro -regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f # macro -regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b # macro -regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c # macro -regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e # macro -regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f # macro -regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a # macro -regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b # macro -regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d # macro -regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e # macro -regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a # macro -regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c # macro -regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d # macro -regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f # macro -regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b # macro -regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c # macro -regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e # macro -regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f # macro -regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a # macro -regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b # macro -regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d # macro -regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e # macro -regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTERRUPT1 = 0x2aac # macro -regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 # macro -regGL1_DRAM_BURST_MASK = 0x2d02 # macro -regGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro -regGL1_ARB_STATUS = 0x2d03 # macro -regGL1_ARB_STATUS_BASE_IDX = 1 # macro -regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 # macro -regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro -regGL1C_STATUS = 0x2d41 # macro -regGL1C_STATUS_BASE_IDX = 1 # macro -regGL1C_UTCL0_CNTL1 = 0x2d42 # macro -regGL1C_UTCL0_CNTL1_BASE_IDX = 1 # macro -regGL1C_UTCL0_CNTL2 = 0x2d43 # macro -regGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro -regGL1C_UTCL0_STATUS = 0x2d44 # macro -regGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro -regGL1C_UTCL0_RETRY = 0x2d45 # macro -regGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro -regCH_ARB_CTRL = 0x2d80 # macro -regCH_ARB_CTRL_BASE_IDX = 1 # macro -regCH_DRAM_BURST_MASK = 0x2d82 # macro -regCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro -regCH_ARB_STATUS = 0x2d83 # macro -regCH_ARB_STATUS_BASE_IDX = 1 # macro -regCH_DRAM_BURST_CTRL = 0x2d84 # macro -regCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro -regCHA_CHC_CREDITS = 0x2d88 # macro -regCHA_CHC_CREDITS_BASE_IDX = 1 # macro -regCHA_CLIENT_FREE_DELAY = 0x2d89 # macro -regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro -regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c # macro -regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro -regCH_VC5_ENABLE = 0x2d94 # macro -regCH_VC5_ENABLE_BASE_IDX = 1 # macro -regCHC_CTRL = 0x2dc0 # macro -regCHC_CTRL_BASE_IDX = 1 # macro -regCHC_STATUS = 0x2dc1 # macro -regCHC_STATUS_BASE_IDX = 1 # macro -regCHCG_CTRL = 0x2dc2 # macro -regCHCG_CTRL_BASE_IDX = 1 # macro -regCHCG_STATUS = 0x2dc3 # macro -regCHCG_STATUS_BASE_IDX = 1 # macro -regGL2C_CTRL = 0x2e00 # macro -regGL2C_CTRL_BASE_IDX = 1 # macro -regGL2C_CTRL2 = 0x2e01 # macro -regGL2C_CTRL2_BASE_IDX = 1 # macro -regGL2C_ADDR_MATCH_MASK = 0x2e03 # macro -regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -regGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro -regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -regGL2C_WBINVL2 = 0x2e05 # macro -regGL2C_WBINVL2_BASE_IDX = 1 # macro -regGL2C_SOFT_RESET = 0x2e06 # macro -regGL2C_SOFT_RESET_BASE_IDX = 1 # macro -regGL2C_CM_CTRL0 = 0x2e07 # macro -regGL2C_CM_CTRL0_BASE_IDX = 1 # macro -regGL2C_CM_CTRL1 = 0x2e08 # macro -regGL2C_CM_CTRL1_BASE_IDX = 1 # macro -regGL2C_CM_STALL = 0x2e09 # macro -regGL2C_CM_STALL_BASE_IDX = 1 # macro -regGL2C_CTRL3 = 0x2e0c # macro -regGL2C_CTRL3_BASE_IDX = 1 # macro -regGL2C_LB_CTR_CTRL = 0x2e0d # macro -regGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro -regGL2C_LB_DATA0 = 0x2e0e # macro -regGL2C_LB_DATA0_BASE_IDX = 1 # macro -regGL2C_LB_DATA1 = 0x2e0f # macro -regGL2C_LB_DATA1_BASE_IDX = 1 # macro -regGL2C_LB_DATA2 = 0x2e10 # macro -regGL2C_LB_DATA2_BASE_IDX = 1 # macro -regGL2C_LB_DATA3 = 0x2e11 # macro -regGL2C_LB_DATA3_BASE_IDX = 1 # macro -regGL2C_LB_CTR_SEL0 = 0x2e12 # macro -regGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro -regGL2C_LB_CTR_SEL1 = 0x2e13 # macro -regGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro -regGL2C_CTRL4 = 0x2e17 # macro -regGL2C_CTRL4_BASE_IDX = 1 # macro -regGL2C_DISCARD_STALL_CTRL = 0x2e18 # macro -regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro -regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_MASK = 0x2e21 # macro -regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro -regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -regGL2A_PRIORITY_CTRL = 0x2e23 # macro -regGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro -regGL2A_RESP_THROTTLE_CTRL = 0x2e2a # macro -regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 # macro -regGL1H_ARB_CTRL = 0x2e40 # macro -regGL1H_ARB_CTRL_BASE_IDX = 1 # macro -regGL1H_GL1_CREDITS = 0x2e41 # macro -regGL1H_GL1_CREDITS_BASE_IDX = 1 # macro -regGL1H_BURST_MASK = 0x2e42 # macro -regGL1H_BURST_MASK_BASE_IDX = 1 # macro -regGL1H_BURST_CTRL = 0x2e43 # macro -regGL1H_BURST_CTRL_BASE_IDX = 1 # macro -regGL1H_ARB_STATUS = 0x2e44 # macro -regGL1H_ARB_STATUS_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_LO = 0x3000 # macro -regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_HI = 0x3001 # macro -regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_LO = 0x3002 # macro -regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_HI = 0x3003 # macro -regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_LO = 0x3004 # macro -regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_HI = 0x3005 # macro -regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_LO = 0x3006 # macro -regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_HI = 0x3007 # macro -regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_LO = 0x3008 # macro -regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_HI = 0x3009 # macro -regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_LO = 0x300a # macro -regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_HI = 0x300b # macro -regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPF_LATENCY_STATS_DATA = 0x300c # macro -regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regCPG_LATENCY_STATS_DATA = 0x300d # macro -regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regCPC_LATENCY_STATS_DATA = 0x300e # macro -regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_LO = 0x3040 # macro -regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_HI = 0x3041 # macro -regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_LO = 0x3043 # macro -regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_HI = 0x3044 # macro -regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro -regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro -regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro -regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro -regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro -regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro -regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro -regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro -regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_LO = 0x304d # macro -regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_HI = 0x304e # macro -regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_LO = 0x304f # macro -regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_HI = 0x3050 # macro -regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_LO = 0x3051 # macro -regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_HI = 0x3052 # macro -regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_LO = 0x30a4 # macro -regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_HI = 0x30a5 # macro -regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_LO = 0x30a6 # macro -regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_HI = 0x30a7 # macro -regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_LO = 0x30a8 # macro -regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_HI = 0x30a9 # macro -regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_LO = 0x30aa # macro -regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_HI = 0x30ab # macro -regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro -regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro -regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro -regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro -regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro -regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro -regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro -regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro -regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro -regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro -regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro -regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro -regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro -regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro -regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro -regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro -regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro -regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro -regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro -regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro -regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro -regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro -regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro -regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro -regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro -regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro -regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro -regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro -regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro -regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro -regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro -regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro -regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro -regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro -regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_LO = 0x314a # macro -regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_HI = 0x314b # macro -regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_LO = 0x314c # macro -regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_HI = 0x314d # macro -regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_LO = 0x314e # macro -regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_HI = 0x314f # macro -regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_HI = 0x3180 # macro -regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_LO = 0x3181 # macro -regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_HI = 0x3182 # macro -regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_LO = 0x3183 # macro -regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_HI = 0x3184 # macro -regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_LO = 0x3185 # macro -regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_HI = 0x3186 # macro -regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_LO = 0x3187 # macro -regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_HI = 0x3188 # macro -regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_LO = 0x3189 # macro -regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_HI = 0x318a # macro -regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_LO = 0x318b # macro -regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_HI = 0x318c # macro -regPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_LO = 0x318d # macro -regPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_HI = 0x318e # macro -regPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_LO = 0x318f # macro -regPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_HI = 0x3190 # macro -regPC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_LO = 0x3191 # macro -regPC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_HI = 0x3192 # macro -regPC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_LO = 0x3193 # macro -regPC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER0_LO = 0x31c0 # macro -regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER1_LO = 0x31c2 # macro -regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER2_LO = 0x31c4 # macro -regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER3_LO = 0x31c6 # macro -regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER4_LO = 0x31c8 # macro -regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER5_LO = 0x31ca # macro -regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER6_LO = 0x31cc # macro -regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER7_LO = 0x31ce # macro -regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_LO = 0x31e4 # macro -regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_HI = 0x31e5 # macro -regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_LO = 0x31e6 # macro -regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_HI = 0x31e7 # macro -regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_LO = 0x31e8 # macro -regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_HI = 0x31e9 # macro -regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_LO = 0x31ea # macro -regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_HI = 0x31eb # macro -regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_LO = 0x31ec # macro -regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_HI = 0x31ed # macro -regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_LO = 0x31ee # macro -regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_HI = 0x31ef # macro -regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_LO = 0x31f0 # macro -regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_HI = 0x31f1 # macro -regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_LO = 0x31f2 # macro -regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_HI = 0x31f3 # macro -regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_LO = 0x3240 # macro -regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_HI = 0x3241 # macro -regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_LO = 0x3242 # macro -regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_HI = 0x3243 # macro -regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_LO = 0x3244 # macro -regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_HI = 0x3245 # macro -regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_LO = 0x3246 # macro -regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_HI = 0x3247 # macro -regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_LO = 0x3260 # macro -regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_HI = 0x3261 # macro -regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_LO = 0x3262 # macro -regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_HI = 0x3263 # macro -regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_LO = 0x3280 # macro -regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_HI = 0x3281 # macro -regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_LO = 0x3282 # macro -regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_HI = 0x3283 # macro -regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_LO = 0x3284 # macro -regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_HI = 0x3285 # macro -regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_LO = 0x3286 # macro -regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_HI = 0x3287 # macro -regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_LO = 0x32c0 # macro -regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_HI = 0x32c1 # macro -regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_LO = 0x32c2 # macro -regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_HI = 0x32c3 # macro -regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_LO = 0x3300 # macro -regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_HI = 0x3301 # macro -regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_LO = 0x3302 # macro -regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_HI = 0x3303 # macro -regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_LO = 0x3340 # macro -regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_HI = 0x3341 # macro -regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_LO = 0x3342 # macro -regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_HI = 0x3343 # macro -regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_LO = 0x3344 # macro -regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_HI = 0x3345 # macro -regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_LO = 0x3346 # macro -regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_HI = 0x3347 # macro -regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER = 0x3348 # macro -regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER2 = 0x3349 # macro -regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER_EN = 0x334a # macro -regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_LO = 0x3380 # macro -regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_HI = 0x3381 # macro -regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_LO = 0x3382 # macro -regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_HI = 0x3383 # macro -regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_LO = 0x3384 # macro -regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_HI = 0x3385 # macro -regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_LO = 0x3386 # macro -regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_HI = 0x3387 # macro -regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_LO = 0x3390 # macro -regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_HI = 0x3391 # macro -regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_LO = 0x3392 # macro -regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_HI = 0x3393 # macro -regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_LO = 0x3394 # macro -regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_HI = 0x3395 # macro -regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_LO = 0x3396 # macro -regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_HI = 0x3397 # macro -regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_LO = 0x33a0 # macro -regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_HI = 0x33a1 # macro -regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_LO = 0x33a2 # macro -regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_HI = 0x33a3 # macro -regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_LO = 0x33a4 # macro -regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_HI = 0x33a5 # macro -regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_LO = 0x33a6 # macro -regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_HI = 0x33a7 # macro -regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_LO = 0x33c0 # macro -regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_HI = 0x33c1 # macro -regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_LO = 0x33c2 # macro -regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_HI = 0x33c3 # macro -regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_LO = 0x33c4 # macro -regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_HI = 0x33c5 # macro -regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_LO = 0x33c6 # macro -regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_HI = 0x33c7 # macro -regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_LO = 0x33c8 # macro -regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_HI = 0x33c9 # macro -regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_LO = 0x33ca # macro -regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_HI = 0x33cb # macro -regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_LO = 0x33cc # macro -regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_HI = 0x33cd # macro -regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_LO = 0x33ce # macro -regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_HI = 0x33cf # macro -regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_LO = 0x3406 # macro -regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_HI = 0x3407 # macro -regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_LO = 0x3408 # macro -regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_HI = 0x3409 # macro -regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_LO = 0x340a # macro -regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_HI = 0x340b # macro -regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_LO = 0x340c # macro -regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_HI = 0x340d # macro -regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_LO = 0x3440 # macro -regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_HI = 0x3441 # macro -regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_LO = 0x3442 # macro -regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_HI = 0x3443 # macro -regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_LO = 0x3444 # macro -regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_HI = 0x3445 # macro -regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_LO = 0x3446 # macro -regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_HI = 0x3447 # macro -regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_LO = 0x3480 # macro -regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_HI = 0x3481 # macro -regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_LO = 0x3482 # macro -regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_HI = 0x3483 # macro -regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_LO = 0x34c0 # macro -regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_HI = 0x34c1 # macro -regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_LO = 0x34c2 # macro -regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_HI = 0x34c3 # macro -regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_LO = 0x34c4 # macro -regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_HI = 0x34c5 # macro -regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_LO = 0x34c6 # macro -regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_HI = 0x34c7 # macro -regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_LO = 0x3520 # macro -regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_HI = 0x3521 # macro -regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_LO = 0x3522 # macro -regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_HI = 0x3523 # macro -regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_LO = 0x3580 # macro -regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_HI = 0x3581 # macro -regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_LO = 0x3582 # macro -regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_HI = 0x3583 # macro -regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_LO = 0x3584 # macro -regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_HI = 0x3585 # macro -regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_LO = 0x3586 # macro -regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_HI = 0x3587 # macro -regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_LO = 0x3588 # macro -regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_HI = 0x3589 # macro -regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_LO = 0x358a # macro -regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_HI = 0x358b # macro -regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_LO = 0x358c # macro -regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_HI = 0x358d # macro -regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_LO = 0x358e # macro -regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_HI = 0x358f # macro -regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_LO = 0x35a0 # macro -regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_HI = 0x35a1 # macro -regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_LO = 0x35a2 # macro -regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_HI = 0x35a3 # macro -regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_LO = 0x35a4 # macro -regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_HI = 0x35a5 # macro -regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_LO = 0x35a6 # macro -regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_HI = 0x35a7 # macro -regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_LO = 0x35c0 # macro -regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_HI = 0x35c1 # macro -regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_LO = 0x35c2 # macro -regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_HI = 0x35c3 # macro -regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_LO = 0x35c4 # macro -regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_HI = 0x35c5 # macro -regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_LO = 0x35c6 # macro -regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_HI = 0x35c7 # macro -regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_LO = 0x35d0 # macro -regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_HI = 0x35d1 # macro -regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_LO = 0x35d2 # macro -regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_HI = 0x35d3 # macro -regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_LO = 0x35d4 # macro -regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_HI = 0x35d5 # macro -regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_LO = 0x35d6 # macro -regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_HI = 0x35d7 # macro -regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_LO = 0x3600 # macro -regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_HI = 0x3601 # macro -regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_LO = 0x3602 # macro -regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_HI = 0x3603 # macro -regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_LO = 0x3604 # macro -regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_HI = 0x3605 # macro -regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_LO = 0x3606 # macro -regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_HI = 0x3607 # macro -regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_LO = 0x3640 # macro -regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_HI = 0x3641 # macro -regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_LO = 0x3642 # macro -regGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_HI = 0x3643 # macro -regGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro -regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro -regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro -regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro -regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro -regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro -regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro -regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro -regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCP_PERFMON_CNTL = 0x3808 # macro -regCP_PERFMON_CNTL_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro -regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro -regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro -regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCPF_LATENCY_STATS_SELECT = 0x380c # macro -regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPG_LATENCY_STATS_SELECT = 0x380d # macro -regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPC_LATENCY_STATS_SELECT = 0x380e # macro -regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f # macro -regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCP_DRAW_OBJECT = 0x3810 # macro -regCP_DRAW_OBJECT_BASE_IDX = 1 # macro -regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro -regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro -regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_HI = 0x3813 # macro -regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_LO = 0x3814 # macro -regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_CNTL = 0x3815 # macro -regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro -regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro -regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro -regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro -regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro -regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro -regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 # macro -regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 # macro -regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 # macro -regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro -regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro -regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro -regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro -regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro -regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro -regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro -regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro -regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_SELECT = 0x38aa # macro -regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro -regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro -regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro -regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro -regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro -regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro -regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro -regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro -regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro -regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro -regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro -regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro -regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro -regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro -regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro -regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro -regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro -regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro -regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro -regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro -regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro -regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro -regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro -regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro -regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro -regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro -regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro -regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro -regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro -regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro -regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro -regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro -regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro -regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro -regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro -regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro -regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro -regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro -regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro -regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro -regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro -regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro -regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro -regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER_BINS = 0x398a # macro -regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_SELECT = 0x398c # macro -regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_SELECT = 0x398d # macro -regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_SELECT = 0x398e # macro -regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_SELECT = 0x398f # macro -regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_SELECT1 = 0x3990 # macro -regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_SELECT1 = 0x3991 # macro -regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_SELECT1 = 0x3992 # macro -regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_SELECT1 = 0x3993 # macro -regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro -regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro -regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro -regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro -regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro -regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro -regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro -regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro -regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro -regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro -regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro -regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro -regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro -regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro -regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro -regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro -regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_SELECT = 0x39d0 # macro -regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_SELECT = 0x39d1 # macro -regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_SELECT = 0x39d2 # macro -regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_SELECT = 0x39d3 # macro -regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_SELECT = 0x39d4 # macro -regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_SELECT = 0x39d5 # macro -regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_SELECT = 0x39d6 # macro -regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_SELECT = 0x39d7 # macro -regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER_CTRL = 0x39d8 # macro -regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER_CTRL2 = 0x39da # macro -regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro -regSQG_PERF_SAMPLE_FINISH = 0x39db # macro -regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro -regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro -regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 # macro -regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 # macro -regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea # macro -regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb # macro -regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_CTRL = 0x39ec # macro -regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_MASK = 0x39ed # macro -regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee # macro -regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_WPTR = 0x39ef # macro -regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_STATUS = 0x39f4 # macro -regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_STATUS2 = 0x39f5 # macro -regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 # macro -regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 # macro -regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 # macro -regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 # macro -regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa # macro -regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro -regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro -regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro -regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro -regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro -regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro -regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro -regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro -regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro -regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro -regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro -regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro -regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro -regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro -regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro -regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro -regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro -regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro -regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro -regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro -regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro -regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro -regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro -regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro -regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro -regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro -regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro -regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro -regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro -regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro -regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro -regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro -regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro -regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro -regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro -regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro -regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro -regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro -regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro -regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro -regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro -regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro -regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro -regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro -regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro -regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro -regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro -regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro -regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro -regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro -regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro -regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro -regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro -regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro -regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro -regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro -regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro -regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro -regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro -regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER_FILTER = 0x3c00 # macro -regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro -regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro -regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro -regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro -regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro -regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro -regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro -regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro -regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro -regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro -regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro -regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro -regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro -regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro -regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro -regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro -regRLC_SPM_RING_WRPTR = 0x3c84 # macro -regRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro -regRLC_SPM_RING_RDPTR = 0x3c85 # macro -regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro -regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro -regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 # macro -regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 # macro -regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 # macro -regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a # macro -regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b # macro -regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 # macro -regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 # macro -regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 # macro -regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_STATUS = 0x3c99 # macro -regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRL = 0x3c9a # macro -regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_MODE = 0x3c9b # macro -regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro -regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro -regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro -regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f # macro -regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro -regRLC_SPM_PAUSE = 0x3ca2 # macro -regRLC_SPM_PAUSE_BASE_IDX = 1 # macro -regRLC_SPM_STATUS = 0x3ca3 # macro -regRLC_SPM_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 # macro -regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 # macro -regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_MODE = 0x3cad # macro -regRLC_SPM_MODE_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae # macro -regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf # macro -regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_OP = 0x3cb0 # macro -regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_RET_DATA = 0x3cb1 # macro -regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_RET_OP = 0x3cb2 # macro -regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 # macro -regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 # macro -regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 # macro -regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_CMD = 0x3cb8 # macro -regRLC_SPM_RSPM_CMD_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 # macro -regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 # macro -regRLC_SPM_SPARE = 0x3cbf # macro -regRLC_SPM_SPARE_BASE_IDX = 1 # macro -regRLC_PERFMON_CNTL = 0x3cc0 # macro -regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro -regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro -regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro -regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro -regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro -regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro -regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro -regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro -regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro -regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro -regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro -regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro -regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro -regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro -regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro -regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro -regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro -regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro -regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro -regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro -regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro -regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro -regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro -regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro -regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro -regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro -regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro -regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro -regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro -regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 # macro -regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 # macro -regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 # macro -regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 # macro -regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro -regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro -regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro -regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro -regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro -regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 # macro -regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 # macro -regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 # macro -regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 # macro -regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 # macro -regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro -regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro -regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro -regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro -regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro -regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro -regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro -regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_MODE = 0x3e02 # macro -regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER0_CFG = 0x3e03 # macro -regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER1_CFG = 0x3e04 # macro -regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro -regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regGRTAVFS_GENERAL_0 = 0x4b02 # macro -regGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro -regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro -regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro -regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro -regGRTAVFS_TARG_FREQ = 0x4b06 # macro -regGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro -regGRTAVFS_TARG_VOLT = 0x4b07 # macro -regGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro -regGRTAVFS_SOFT_RESET = 0x4b0c # macro -regGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro -regGRTAVFS_PSM_CNTL = 0x4b0d # macro -regGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_CLK_CNTL = 0x4b0e # macro -regGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 # macro -regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 # macro -regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regGRTAVFS_SE_GENERAL_0 = 0x4b42 # macro -regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 # macro -regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 # macro -regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 # macro -regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro -regGRTAVFS_SE_TARG_FREQ = 0x4b46 # macro -regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 # macro -regGRTAVFS_SE_TARG_VOLT = 0x4b47 # macro -regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 # macro -regGRTAVFS_SE_SOFT_RESET = 0x4b4c # macro -regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 # macro -regGRTAVFS_SE_PSM_CNTL = 0x4b4d # macro -regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_SE_CLK_CNTL = 0x4b4e # macro -regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 # macro -regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro -regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_PFP_UCODE_ADDR = 0x5814 # macro -regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro -regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -regCP_PFP_UCODE_DATA = 0x5815 # macro -regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro -regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_ME_RAM_RADDR = 0x5816 # macro -regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro -regCP_ME_RAM_WADDR = 0x5816 # macro -regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro -regCP_HYP_ME_UCODE_DATA = 0x5817 # macro -regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro -regCP_ME_RAM_DATA = 0x5817 # macro -regCP_ME_RAM_DATA_BASE_IDX = 1 # macro -regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro -regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro -regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro -regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro -regCP_MEC_ME1_UCODE_DATA = 0x581b # macro -regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro -regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro -regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro -regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro -regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro -regCP_MEC_ME2_UCODE_DATA = 0x581d # macro -regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_LO = 0x5840 # macro -regCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_HI = 0x5841 # macro -regCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_CNTL = 0x5842 # macro -regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_PFP_IC_OP_CNTL = 0x5843 # macro -regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_LO = 0x5844 # macro -regCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_HI = 0x5845 # macro -regCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_CNTL = 0x5846 # macro -regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_ME_IC_OP_CNTL = 0x5847 # macro -regCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_LO = 0x584c # macro -regCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_HI = 0x584d # macro -regCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_CNTL = 0x584e # macro -regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_LO = 0x5850 # macro -regCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_MIBASE_LO = 0x5850 # macro -regCP_MES_MIBASE_LO_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_HI = 0x5851 # macro -regCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_MIBASE_HI = 0x5851 # macro -regCP_MES_MIBASE_HI_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_CNTL = 0x5852 # macro -regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_LO = 0x5854 # macro -regCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_MDBASE_LO = 0x5854 # macro -regCP_MES_MDBASE_LO_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_HI = 0x5855 # macro -regCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_MDBASE_HI = 0x5855 # macro -regCP_MES_MDBASE_HI_BASE_IDX = 1 # macro -regCP_MES_MIBOUND_LO = 0x585b # macro -regCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_MES_MIBOUND_HI = 0x585c # macro -regCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MES_MDBOUND_LO = 0x585d # macro -regCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro -regCP_MES_MDBOUND_HI = 0x585e # macro -regCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE0_LO = 0x5863 # macro -regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE1_LO = 0x5864 # macro -regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE0_HI = 0x5865 # macro -regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE1_HI = 0x5866 # macro -regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIBOUND_LO = 0x586c # macro -regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIBOUND_HI = 0x586d # macro -regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_LO = 0x5870 # macro -regCP_MEC_DC_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_MDBASE_LO = 0x5870 # macro -regCP_MEC_MDBASE_LO_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_HI = 0x5871 # macro -regCP_MEC_DC_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_MDBASE_HI = 0x5871 # macro -regCP_MEC_MDBASE_HI_BASE_IDX = 1 # macro -regCP_MEC_MIBOUND_LO = 0x5872 # macro -regCP_MEC_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_MEC_MIBOUND_HI = 0x5873 # macro -regCP_MEC_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MEC_MDBOUND_LO = 0x5874 # macro -regCP_MEC_MDBOUND_LO_BASE_IDX = 1 # macro -regCP_MEC_MDBOUND_HI = 0x5875 # macro -regCP_MEC_MDBOUND_HI_BASE_IDX = 1 # macro -regRLC_CNTL = 0x4c00 # macro -regRLC_CNTL_BASE_IDX = 1 # macro -regRLC_F32_UCODE_VERSION = 0x4c03 # macro -regRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro -regRLC_STAT = 0x4c04 # macro -regRLC_STAT_BASE_IDX = 1 # macro -regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro -regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro -regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro -regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro -regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro -regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro -regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_3 = 0x4c11 # macro -regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_4 = 0x4c12 # macro -regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_CTRL = 0x4c13 # macro -regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_STAT = 0x4c14 # macro -regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro -regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro -regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro -regRLC_INT_STAT = 0x4c18 # macro -regRLC_INT_STAT_BASE_IDX = 1 # macro -regRLC_MGCG_CTRL = 0x4c1a # macro -regRLC_MGCG_CTRL_BASE_IDX = 1 # macro -regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro -regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro -regRLC_PG_DELAY_2 = 0x4c1f # macro -regRLC_PG_DELAY_2_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro -regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro -regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro -regRLC_UCODE_CNTL = 0x4c27 # macro -regRLC_UCODE_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_RESET = 0x4c28 # macro -regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro -regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro -regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro -regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro -regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b # macro -regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro -regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro -regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro -regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro -regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_CTRL = 0x4c34 # macro -regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_STAT = 0x4c35 # macro -regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro -regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro -regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro -regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro -regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro -regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro -regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro -regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro -regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro -regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro -regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro -regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_32 = 0x4c42 # macro -regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro -regRLC_PG_CNTL = 0x4c43 # macro -regRLC_PG_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro -regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro -regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro -regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro -regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro -regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro -regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro -regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro -regRLC_DYN_PG_STATUS = 0x4c4b # macro -regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro -regRLC_DYN_PG_REQUEST = 0x4c4c # macro -regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro -regRLC_PG_DELAY = 0x4c4d # macro -regRLC_PG_DELAY_BASE_IDX = 1 # macro -regRLC_WGP_STATUS = 0x4c4e # macro -regRLC_WGP_STATUS_BASE_IDX = 1 # macro -regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro -regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro -regRLC_MAX_PG_WGP = 0x4c54 # macro -regRLC_MAX_PG_WGP_BASE_IDX = 1 # macro -regRLC_AUTO_PG_CTRL = 0x4c55 # macro -regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro -regRLC_SERDES_RD_INDEX = 0x4c59 # macro -regRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro -regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro -regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro -regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_3 = 0x4c5d # macro -regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro -regRLC_SERDES_MASK = 0x4c5e # macro -regRLC_SERDES_MASK_BASE_IDX = 1 # macro -regRLC_SERDES_CTRL = 0x4c5f # macro -regRLC_SERDES_CTRL_BASE_IDX = 1 # macro -regRLC_SERDES_DATA = 0x4c60 # macro -regRLC_SERDES_DATA_BASE_IDX = 1 # macro -regRLC_SERDES_BUSY = 0x4c61 # macro -regRLC_SERDES_BUSY_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_0 = 0x4c63 # macro -regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_1 = 0x4c64 # macro -regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_2 = 0x4c65 # macro -regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_3 = 0x4c66 # macro -regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_4 = 0x4c67 # macro -regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_5 = 0x4c68 # macro -regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_6 = 0x4c69 # macro -regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_7 = 0x4c6a # macro -regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro -regRLC_STATIC_PG_STATUS = 0x4c6e # macro -regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_16 = 0x4c76 # macro -regRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro -regRLC_PG_DELAY_3 = 0x4c78 # macro -regRLC_PG_DELAY_3_BASE_IDX = 1 # macro -regRLC_GPR_REG1 = 0x4c79 # macro -regRLC_GPR_REG1_BASE_IDX = 1 # macro -regRLC_GPR_REG2 = 0x4c7a # macro -regRLC_GPR_REG2_BASE_IDX = 1 # macro -regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro -regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro -regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro -regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro -regRLC_SRM_CNTL = 0x4c80 # macro -regRLC_SRM_CNTL_BASE_IDX = 1 # macro -regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro -regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro -regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro -regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro -regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro -regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro -regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro -regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro -regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro -regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro -regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro -regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro -regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro -regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro -regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro -regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro -regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro -regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro -regRLC_SRM_STAT = 0x4c9b # macro -regRLC_SRM_STAT_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_8 = 0x4cad # macro -regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_9 = 0x4cae # macro -regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_10 = 0x4caf # macro -regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_11 = 0x4cb0 # macro -regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_12 = 0x4cb1 # macro -regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro -regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro -regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro -regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro -regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro -regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro -regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro -regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro -regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro -regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro -regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro -regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro -regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro -regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro -regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro -regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro -regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro -regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_0 = 0x4cc7 # macro -regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_1 = 0x4cc8 # macro -regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_2 = 0x4cc9 # macro -regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_3 = 0x4cca # macro -regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro -regRLC_PACE_INT_STAT = 0x4ccc # macro -regRLC_PACE_INT_STAT_BASE_IDX = 1 # macro -regRLC_UTCL1_STATUS = 0x4cd4 # macro -regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_0 = 0x4cd5 # macro -regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_1 = 0x4cd6 # macro -regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_2 = 0x4cd7 # macro -regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_3 = 0x4cd8 # macro -regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro -regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro -regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_13 = 0x4cdd # macro -regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_14 = 0x4cde # macro -regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_15 = 0x4cdf # macro -regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro -regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro -regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro -regRLC_PACE_INT_DISABLE = 0x4ced # macro -regRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro -regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro -regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro -regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro -regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro -regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro -regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro -regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro -regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro -regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro -regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro -regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb # macro -regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc # macro -regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro -regRLC_RLCV_SPARE_INT = 0x4d00 # macro -regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_INT_0 = 0x4d04 # macro -regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_INT_1 = 0x4d05 # macro -regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_CTRL = 0x4d06 # macro -regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_SMU_CLK_REQ = 0x4d08 # macro -regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro -regRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro -regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro -regRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro -regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro -regRLC_SPARE = 0x4d0b # macro -regRLC_SPARE_BASE_IDX = 1 # macro -regRLC_SPP_CTRL = 0x4d0c # macro -regRLC_SPP_CTRL_BASE_IDX = 1 # macro -regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro -regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro -regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro -regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro -regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro -regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro -regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro -regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro -regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro -regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro -regRLC_SPP_PROF_INFO_1 = 0x4d18 # macro -regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro -regRLC_SPP_PROF_INFO_2 = 0x4d19 # macro -regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro -regRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro -regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro -regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro -regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro -regRLC_SPP_STATUS = 0x4d1c # macro -regRLC_SPP_STATUS_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_0 = 0x4d1d # macro -regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_1 = 0x4d1e # macro -regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_2 = 0x4d1f # macro -regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_3 = 0x4d20 # macro -regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro -regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro -regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro -regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro -regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro -regRLC_SPP_PBB_INFO = 0x4d23 # macro -regRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro -regRLC_SPP_RESET = 0x4d24 # macro -regRLC_SPP_RESET_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro -regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro -regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro -regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro -regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro -regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro -regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro -regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro -regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro -regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro -regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro -regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_CAC_MASK_CNTL = 0x4d45 # macro -regRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 # macro -regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 # macro -regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a # macro -regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b # macro -regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c # macro -regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d # macro -regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 # macro -regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 # macro -regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 # macro -regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 # macro -regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 # macro -regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 # macro -regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 # macro -regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 # macro -regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a # macro -regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b # macro -regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c # macro -regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d # macro -regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e # macro -regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 # macro -regRLC_GFX_IH_ARBITER_STAT = 0x4d5f # macro -regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 # macro -regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 # macro -regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 # macro -regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 # macro -regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 # macro -regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 # macro -regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 # macro -regRLC_LX6_CNTL = 0x4d80 # macro -regRLC_LX6_CNTL_BASE_IDX = 1 # macro -regRLC_XT_CORE_STATUS = 0x4dd4 # macro -regRLC_XT_CORE_STATUS_BASE_IDX = 1 # macro -regRLC_XT_CORE_INTERRUPT = 0x4dd5 # macro -regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 # macro -regRLC_XT_CORE_FAULT_INFO = 0x4dd6 # macro -regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 # macro -regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 # macro -regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 # macro -regRLC_XT_CORE_RESERVED = 0x4dd8 # macro -regRLC_XT_CORE_RESERVED_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_FORCE = 0x4dd9 # macro -regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_CLEAR = 0x4dda # macro -regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb # macro -regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc # macro -regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro -regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro -regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro -regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro -regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro -regRLC_SPP_CAM_ADDR = 0x4de8 # macro -regRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_CAM_DATA = 0x4de9 # macro -regRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro -regRLC_SPP_CAM_EXT_ADDR = 0x4dea # macro -regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_CAM_EXT_DATA = 0x4deb # macro -regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_RANGE = 0x4df5 # macro -regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_CNTL = 0x4df6 # macro -regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_STAT = 0x4df7 # macro -regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro -regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro -regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro -regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro -regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro -regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro -regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro -regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro -regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_MEM_SLP_CNTL = 0x4e00 # macro -regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro -regSMU_RLC_RESPONSE = 0x4e01 # macro -regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro -regRLC_RLCV_SAFE_MODE = 0x4e02 # macro -regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_SMU_SAFE_MODE = 0x4e03 # macro -regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_RLCV_COMMAND = 0x4e04 # macro -regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE = 0x4e05 # macro -regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE_1 = 0x4e06 # macro -regRLC_SMU_MESSAGE_1_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE_2 = 0x4e07 # macro -regRLC_SMU_MESSAGE_2_BASE_IDX = 1 # macro -regRLC_SRM_GPM_COMMAND = 0x4e08 # macro -regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro -regRLC_SRM_GPM_ABORT = 0x4e09 # macro -regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro -regRLC_SMU_COMMAND = 0x4e0a # macro -regRLC_SMU_COMMAND_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_1 = 0x4e0b # macro -regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_2 = 0x4e0c # macro -regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_3 = 0x4e0d # macro -regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_4 = 0x4e0e # macro -regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_5 = 0x4e0f # macro -regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 # macro -regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 # macro -regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 # macro -regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 # macro -regRLC_IMU_MISC = 0x4e16 # macro -regRLC_IMU_MISC_BASE_IDX = 1 # macro -regRLC_IMU_RESET_VECTOR = 0x4e17 # macro -regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_START = 0x4e60 # macro -regRLC_RLCS_DEC_START_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro -regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro -regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro -regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro -regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro -regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro -regRLC_RLCS_CGCG_REQUEST = 0x4e66 # macro -regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro -regRLC_RLCS_CGCG_STATUS = 0x4e67 # macro -regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_SOC_DS_CNTL = 0x4e68 # macro -regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_DS_CNTL = 0x4e69 # macro -regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a # macro -regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_STAT = 0x4e6b # macro -regRLC_GPM_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_STAT = 0x4e6b # macro -regRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c # macro -regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro -regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d # macro -regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e # macro -regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f # macro -regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 # macro -regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 # macro -regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_STAT_2 = 0x4e72 # macro -regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 # macro -regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro -regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 # macro -regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_PG_CHANGE_READ = 0x4e75 # macro -regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro -regRLC_RLCS_IH_SEMAPHORE = 0x4e76 # macro -regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro -regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 # macro -regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro -regRLC_RLCS_WGP_STATUS = 0x4e78 # macro -regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_WGP_READ = 0x4e79 # macro -regRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a # macro -regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b # macro -regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c # macro -regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d # macro -regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_CTRL = 0x4e7e # macro -regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f # macro -regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 # macro -regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_RLCS_DSM_TRIG = 0x4e81 # macro -regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 # macro -regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 # macro -regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_0 = 0x4e88 # macro -regRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_1 = 0x4e89 # macro -regRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_2 = 0x4e8a # macro -regRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_3 = 0x4e8b # macro -regRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_4 = 0x4e8c # macro -regRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_5 = 0x4e8d # macro -regRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_6 = 0x4e8e # macro -regRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_7 = 0x4e8f # macro -regRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_8 = 0x4e90 # macro -regRLC_RLCS_GENERAL_8_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_9 = 0x4e91 # macro -regRLC_RLCS_GENERAL_9_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_10 = 0x4e92 # macro -regRLC_RLCS_GENERAL_10_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_11 = 0x4e93 # macro -regRLC_RLCS_GENERAL_11_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_12 = 0x4e94 # macro -regRLC_RLCS_GENERAL_12_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_13 = 0x4e95 # macro -regRLC_RLCS_GENERAL_13_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_14 = 0x4e96 # macro -regRLC_RLCS_GENERAL_14_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_15 = 0x4e97 # macro -regRLC_RLCS_GENERAL_15_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_16 = 0x4e98 # macro -regRLC_RLCS_GENERAL_16_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro -regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro -regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro -regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro -regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 # macro -regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro -regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca # macro -regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd # macro -regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_EDC_INT_CNTL = 0x4ece # macro -regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf # macro -regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro -regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 # macro -regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 # macro -regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 # macro -regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 # macro -regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_0 = 0x4ed4 # macro -regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_1 = 0x4ed5 # macro -regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_2 = 0x4ed6 # macro -regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_3 = 0x4ed7 # macro -regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_STATUS = 0x4ed8 # macro -regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 # macro -regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro -regRLC_RLCS_UTCL2_CNTL = 0x4eda # macro -regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb # macro -regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc # macro -regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd # macro -regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede # macro -regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf # macro -regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 # macro -regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 # macro -regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 # macro -regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 # macro -regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 # macro -regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 # macro -regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 # macro -regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 # macro -regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea # macro -regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb # macro -regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec # macro -regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed # macro -regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee # macro -regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef # macro -regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 # macro -regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 # macro -regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 # macro -regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 # macro -regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 # macro -regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 # macro -regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 # macro -regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 # macro -regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 # macro -regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_RM_CNTL = 0x4efa # macro -regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_END = 0x4fff # macro -regRLC_RLCS_DEC_END_BASE_IDX = 1 # macro -regRLC_SAFE_MODE = 0x0980 # macro -regRLC_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_SPM_SAMPLE_CNT = 0x0981 # macro -regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro -regRLC_SPM_MC_CNTL = 0x0982 # macro -regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_INT_CNTL = 0x0983 # macro -regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_INT_STATUS = 0x0984 # macro -regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_INT_INFO_1 = 0x0985 # macro -regRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_SPM_INT_INFO_2 = 0x0986 # macro -regRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_CSIB_ADDR_LO = 0x0987 # macro -regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro -regRLC_CSIB_ADDR_HI = 0x0988 # macro -regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro -regRLC_CSIB_LENGTH = 0x0989 # macro -regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro -regRLC_CP_SCHEDULERS = 0x098a # macro -regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro -regRLC_CP_EOF_INT = 0x098b # macro -regRLC_CP_EOF_INT_BASE_IDX = 1 # macro -regRLC_CP_EOF_INT_CNT = 0x098c # macro -regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro -regRLC_SPARE_INT_0 = 0x098d # macro -regRLC_SPARE_INT_0_BASE_IDX = 1 # macro -regRLC_SPARE_INT_1 = 0x098e # macro -regRLC_SPARE_INT_1_BASE_IDX = 1 # macro -regRLC_SPARE_INT_2 = 0x098f # macro -regRLC_SPARE_INT_2_BASE_IDX = 1 # macro -regRLC_PACE_SPARE_INT = 0x0990 # macro -regRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro -regRLC_PACE_SPARE_INT_1 = 0x0991 # macro -regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro -regRLC_RLCV_SPARE_INT_1 = 0x0992 # macro -regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro -regCGTS_TCC_DISABLE = 0x5006 # macro -regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro -regCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro -regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_PA_CLK_CTRL = 0x5088 # macro -regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL0 = 0x5089 # macro -regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL1 = 0x508a # macro -regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL2 = 0x508b # macro -regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro -regCGTT_SQG_CLK_CTRL = 0x508d # macro -regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_ALU_CLK_CTRL = 0x508e # macro -regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_TEX_CLK_CTRL = 0x508f # macro -regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_LDS_CLK_CTRL = 0x5090 # macro -regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro -regICG_SP_CLK_CTRL = 0x5093 # macro -regICG_SP_CLK_CTRL_BASE_IDX = 1 # macro -regTA_CGTT_CTRL = 0x509d # macro -regTA_CGTT_CTRL_BASE_IDX = 1 # macro -regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro -regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro -regCB_CGTT_SCLK_CTRL = 0x50a8 # macro -regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CP_CLK_CTRL = 0x50b0 # macro -regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CPF_CLK_CTRL = 0x50b1 # macro -regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CPC_CLK_CTRL = 0x50b2 # macro -regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_RLC_CLK_CTRL = 0x50b5 # macro -regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL3 = 0x50bc # macro -regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL4 = 0x50bd # macro -regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 # macro -regGCEA_ICG_CTRL = 0x50c4 # macro -regGCEA_ICG_CTRL_BASE_IDX = 1 # macro -regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 # macro -regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regGL1H_ICG_CTRL = 0x50e8 # macro -regGL1H_ICG_CTRL_BASE_IDX = 1 # macro -regCHI_CHR_MGCG_OVERRIDE = 0x50e9 # macro -regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regICG_GL1C_CLK_CTRL = 0x50ec # macro -regICG_GL1C_CLK_CTRL_BASE_IDX = 1 # macro -regICG_GL1A_CTRL = 0x50f0 # macro -regICG_GL1A_CTRL_BASE_IDX = 1 # macro -regICG_CHA_CTRL = 0x50f1 # macro -regICG_CHA_CTRL_BASE_IDX = 1 # macro -regGUS_ICG_CTRL = 0x50f4 # macro -regGUS_ICG_CTRL_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL0 = 0x50f8 # macro -regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL1 = 0x50f9 # macro -regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL2 = 0x50fa # macro -regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL3 = 0x50fb # macro -regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro -regGFX_ICG_GL2C_CTRL = 0x50fc # macro -regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 # macro -regGFX_ICG_GL2C_CTRL1 = 0x50fd # macro -regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 # macro -regICG_LDS_CLK_CTRL = 0x5114 # macro -regICG_LDS_CLK_CTRL_BASE_IDX = 1 # macro -regICG_CHC_CLK_CTRL = 0x5140 # macro -regICG_CHC_CLK_CTRL_BASE_IDX = 1 # macro -regICG_CHCG_CLK_CTRL = 0x5144 # macro -regICG_CHCG_CLK_CTRL_BASE_IDX = 1 # macro -regGFX_PIPE_PRIORITY = 0x587f # macro -regGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro -regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro -regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro -regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro -regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro -regGC_IH_COOKIE_0_PTR = 0x5a07 # macro -regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro -regGRBM_SE_REMAP_CNTL = 0x5a08 # macro -regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro -regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro -regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro -regRLC_SDMA0_STATUS = 0x5b18 # macro -regRLC_SDMA0_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA1_STATUS = 0x5b19 # macro -regRLC_SDMA1_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA2_STATUS = 0x5b1a # macro -regRLC_SDMA2_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA3_STATUS = 0x5b1b # macro -regRLC_SDMA3_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA0_BUSY_STATUS = 0x5b1c # macro -regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA1_BUSY_STATUS = 0x5b1d # macro -regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA2_BUSY_STATUS = 0x5b1e # macro -regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA3_BUSY_STATUS = 0x5b1f # macro -regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro -regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro -regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_INT_1 = 0x5b26 # macro -regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_CTRL = 0x5b27 # macro -regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_STAT = 0x5b28 # macro -regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro -regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro -regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro -regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro -regRLC_BUSY_CLK_CNTL = 0x5b30 # macro -regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro -regRLC_CLK_CNTL = 0x5b31 # macro -regRLC_CLK_CNTL_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_STAT = 0x5b33 # macro -regRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro -regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro -regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro -regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro -regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro -regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro -regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro -regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro -regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro -regRLC_PACE_INT_FORCE = 0x5b3d # macro -regRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro -regRLC_PACE_INT_CLEAR = 0x5b3e # macro -regRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro -regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro -regRLC_IH_COOKIE = 0x5b41 # macro -regRLC_IH_COOKIE_BASE_IDX = 1 # macro -regRLC_IH_COOKIE_CNTL = 0x5b42 # macro -regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro -regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro -regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro -regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro -regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro -regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro -regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro -regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 # macro -regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_UCODE_DATA = 0x5b49 # macro -regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro -regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b # macro -regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro -regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro -regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro -regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 # macro -regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 # macro -regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro -regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro -regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro -regRLC_GPM_UCODE_ADDR = 0x5b60 # macro -regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_UCODE_DATA = 0x5b61 # macro -regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPM_IRAM_ADDR = 0x5b62 # macro -regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_IRAM_DATA = 0x5b63 # macro -regRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_RLCP_IRAM_ADDR = 0x5b64 # macro -regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_RLCP_IRAM_DATA = 0x5b65 # macro -regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_RLCV_IRAM_ADDR = 0x5b66 # macro -regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_RLCV_IRAM_DATA = 0x5b67 # macro -regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_LX6_DRAM_ADDR = 0x5b68 # macro -regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 # macro -regRLC_LX6_DRAM_DATA = 0x5b69 # macro -regRLC_LX6_DRAM_DATA_BASE_IDX = 1 # macro -regRLC_LX6_IRAM_ADDR = 0x5b6a # macro -regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_LX6_IRAM_DATA = 0x5b6b # macro -regRLC_LX6_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_PACE_UCODE_ADDR = 0x5b6c # macro -regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_PACE_UCODE_DATA = 0x5b6d # macro -regRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPM_SCRATCH_ADDR = 0x5b6e # macro -regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_SCRATCH_DATA = 0x5b6f # macro -regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_SRM_DRAM_ADDR = 0x5b71 # macro -regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro -regRLC_SRM_DRAM_DATA = 0x5b72 # macro -regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro -regRLC_SRM_ARAM_ADDR = 0x5b73 # macro -regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SRM_ARAM_DATA = 0x5b74 # macro -regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro -regRLC_PACE_SCRATCH_ADDR = 0x5b77 # macro -regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_PACE_SCRATCH_DATA = 0x5b78 # macro -regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_GTS_OFFSET_LSB = 0x5b79 # macro -regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro -regRLC_GTS_OFFSET_MSB = 0x5b7a # macro -regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_0 = 0x5b80 # macro -regGL2_PIPE_STEER_0_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_1 = 0x5b81 # macro -regGL2_PIPE_STEER_1_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_2 = 0x5b82 # macro -regGL2_PIPE_STEER_2_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_3 = 0x5b83 # macro -regGL2_PIPE_STEER_3_BASE_IDX = 1 # macro -regGL1_PIPE_STEER = 0x5b84 # macro -regGL1_PIPE_STEER_BASE_IDX = 1 # macro -regCH_PIPE_STEER = 0x5b88 # macro -regCH_PIPE_STEER_BASE_IDX = 1 # macro -regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 # macro -regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 # macro -regGC_USER_PRIM_CONFIG = 0x5b91 # macro -regGC_USER_PRIM_CONFIG_BASE_IDX = 1 # macro -regGC_USER_SA_UNIT_DISABLE = 0x5b92 # macro -regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 # macro -regGC_USER_RB_REDUNDANCY = 0x5b93 # macro -regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 # macro -regGC_USER_RB_BACKEND_DISABLE = 0x5b94 # macro -regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 # macro -regGC_USER_RMI_REDUNDANCY = 0x5b95 # macro -regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 # macro -regCGTS_USER_TCC_DISABLE = 0x5b96 # macro -regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro -regGC_USER_SHADER_RATE_CONFIG = 0x5b97 # macro -regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro -regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro -regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro -regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro -regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro -regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro -regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro -regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro -regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro -regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro -regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro -regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro -regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro -regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro -regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro -regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro -regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro -regCP_MES_DM_INDEX_ADDR = 0x5c00 # macro -regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_MES_DM_INDEX_DATA = 0x5c01 # macro -regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCP_MEC_DM_INDEX_ADDR = 0x5c02 # macro -regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_MEC_DM_INDEX_DATA = 0x5c03 # macro -regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 # macro -regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 # macro -regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCPG_PSP_DEBUG = 0x5c10 # macro -regCPG_PSP_DEBUG_BASE_IDX = 1 # macro -regCPC_PSP_DEBUG = 0x5c11 # macro -regCPC_PSP_DEBUG_BASE_IDX = 1 # macro -regGRBM_SEC_CNTL = 0x5e0d # macro -regGRBM_SEC_CNTL_BASE_IDX = 1 # macro -regGRBM_CAM_INDEX = 0x5e10 # macro -regGRBM_CAM_INDEX_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_INDEX = 0x5e10 # macro -regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro -regGRBM_CAM_DATA = 0x5e11 # macro -regGRBM_CAM_DATA_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_DATA = 0x5e11 # macro -regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro -regGRBM_CAM_DATA_UPPER = 0x5e12 # macro -regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 # macro -regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro -regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 # macro -regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_0 = 0x4000 # macro -regGFX_IMU_C2PMSG_0_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_1 = 0x4001 # macro -regGFX_IMU_C2PMSG_1_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_2 = 0x4002 # macro -regGFX_IMU_C2PMSG_2_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_3 = 0x4003 # macro -regGFX_IMU_C2PMSG_3_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_4 = 0x4004 # macro -regGFX_IMU_C2PMSG_4_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_5 = 0x4005 # macro -regGFX_IMU_C2PMSG_5_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_6 = 0x4006 # macro -regGFX_IMU_C2PMSG_6_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_7 = 0x4007 # macro -regGFX_IMU_C2PMSG_7_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_8 = 0x4008 # macro -regGFX_IMU_C2PMSG_8_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_9 = 0x4009 # macro -regGFX_IMU_C2PMSG_9_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_10 = 0x400a # macro -regGFX_IMU_C2PMSG_10_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_11 = 0x400b # macro -regGFX_IMU_C2PMSG_11_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_12 = 0x400c # macro -regGFX_IMU_C2PMSG_12_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_13 = 0x400d # macro -regGFX_IMU_C2PMSG_13_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_14 = 0x400e # macro -regGFX_IMU_C2PMSG_14_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_15 = 0x400f # macro -regGFX_IMU_C2PMSG_15_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_16 = 0x4010 # macro -regGFX_IMU_C2PMSG_16_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_17 = 0x4011 # macro -regGFX_IMU_C2PMSG_17_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_18 = 0x4012 # macro -regGFX_IMU_C2PMSG_18_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_19 = 0x4013 # macro -regGFX_IMU_C2PMSG_19_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_20 = 0x4014 # macro -regGFX_IMU_C2PMSG_20_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_21 = 0x4015 # macro -regGFX_IMU_C2PMSG_21_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_22 = 0x4016 # macro -regGFX_IMU_C2PMSG_22_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_23 = 0x4017 # macro -regGFX_IMU_C2PMSG_23_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_24 = 0x4018 # macro -regGFX_IMU_C2PMSG_24_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_25 = 0x4019 # macro -regGFX_IMU_C2PMSG_25_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_26 = 0x401a # macro -regGFX_IMU_C2PMSG_26_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_27 = 0x401b # macro -regGFX_IMU_C2PMSG_27_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_28 = 0x401c # macro -regGFX_IMU_C2PMSG_28_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_29 = 0x401d # macro -regGFX_IMU_C2PMSG_29_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_30 = 0x401e # macro -regGFX_IMU_C2PMSG_30_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_31 = 0x401f # macro -regGFX_IMU_C2PMSG_31_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_32 = 0x4020 # macro -regGFX_IMU_C2PMSG_32_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_33 = 0x4021 # macro -regGFX_IMU_C2PMSG_33_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_34 = 0x4022 # macro -regGFX_IMU_C2PMSG_34_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_35 = 0x4023 # macro -regGFX_IMU_C2PMSG_35_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_36 = 0x4024 # macro -regGFX_IMU_C2PMSG_36_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_37 = 0x4025 # macro -regGFX_IMU_C2PMSG_37_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_38 = 0x4026 # macro -regGFX_IMU_C2PMSG_38_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_39 = 0x4027 # macro -regGFX_IMU_C2PMSG_39_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_40 = 0x4028 # macro -regGFX_IMU_C2PMSG_40_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_41 = 0x4029 # macro -regGFX_IMU_C2PMSG_41_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_42 = 0x402a # macro -regGFX_IMU_C2PMSG_42_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_43 = 0x402b # macro -regGFX_IMU_C2PMSG_43_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_44 = 0x402c # macro -regGFX_IMU_C2PMSG_44_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_45 = 0x402d # macro -regGFX_IMU_C2PMSG_45_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_46 = 0x402e # macro -regGFX_IMU_C2PMSG_46_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_47 = 0x402f # macro -regGFX_IMU_C2PMSG_47_BASE_IDX = 1 # macro -regGFX_IMU_MSG_FLAGS = 0x403f # macro -regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 # macro -regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_MP1_MUTEX = 0x4043 # macro -regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_4 = 0x4046 # macro -regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_3 = 0x4047 # macro -regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_2 = 0x4048 # macro -regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_1 = 0x4049 # macro -regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_0 = 0x404a # macro -regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 # macro -regGFX_IMU_RLC_CMD = 0x404b # macro -regGFX_IMU_RLC_CMD_BASE_IDX = 1 # macro -regGFX_IMU_RLC_MUTEX = 0x404c # macro -regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_MSG_STATUS = 0x404f # macro -regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 # macro -regRLC_GFX_IMU_DATA_0 = 0x4052 # macro -regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 # macro -regRLC_GFX_IMU_CMD = 0x4053 # macro -regRLC_GFX_IMU_CMD_BASE_IDX = 1 # macro -regGFX_IMU_RLC_STATUS = 0x4054 # macro -regGFX_IMU_RLC_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_STATUS = 0x4055 # macro -regGFX_IMU_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_SOC_DATA = 0x4059 # macro -regGFX_IMU_SOC_DATA_BASE_IDX = 1 # macro -regGFX_IMU_SOC_ADDR = 0x405a # macro -regGFX_IMU_SOC_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_SOC_REQ = 0x405b # macro -regGFX_IMU_SOC_REQ_BASE_IDX = 1 # macro -regGFX_IMU_VF_CTRL = 0x405c # macro -regGFX_IMU_VF_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY = 0x4060 # macro -regGFX_IMU_TELEMETRY_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY_DATA = 0x4061 # macro -regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 # macro -regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_0 = 0x4068 # macro -regGFX_IMU_SCRATCH_0_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_1 = 0x4069 # macro -regGFX_IMU_SCRATCH_1_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_2 = 0x406a # macro -regGFX_IMU_SCRATCH_2_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_3 = 0x406b # macro -regGFX_IMU_SCRATCH_3_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_4 = 0x406c # macro -regGFX_IMU_SCRATCH_4_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_5 = 0x406d # macro -regGFX_IMU_SCRATCH_5_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_6 = 0x406e # macro -regGFX_IMU_SCRATCH_6_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_7 = 0x406f # macro -regGFX_IMU_SCRATCH_7_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_8 = 0x4070 # macro -regGFX_IMU_SCRATCH_8_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_9 = 0x4071 # macro -regGFX_IMU_SCRATCH_9_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_10 = 0x4072 # macro -regGFX_IMU_SCRATCH_10_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_11 = 0x4073 # macro -regGFX_IMU_SCRATCH_11_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_12 = 0x4074 # macro -regGFX_IMU_SCRATCH_12_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_13 = 0x4075 # macro -regGFX_IMU_SCRATCH_13_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_14 = 0x4076 # macro -regGFX_IMU_SCRATCH_14_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_15 = 0x4077 # macro -regGFX_IMU_SCRATCH_15_BASE_IDX = 1 # macro -regGFX_IMU_FW_GTS_LO = 0x4078 # macro -regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 # macro -regGFX_IMU_FW_GTS_HI = 0x4079 # macro -regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 # macro -regGFX_IMU_GTS_OFFSET_LO = 0x407a # macro -regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 # macro -regGFX_IMU_GTS_OFFSET_HI = 0x407b # macro -regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 # macro -regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c # macro -regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 # macro -regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d # macro -regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 # macro -regGFX_IMU_CORE_INT_STATUS = 0x407f # macro -regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_MASK = 0x4080 # macro -regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_LVL = 0x4081 # macro -regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_EDGE = 0x4082 # macro -regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_0 = 0x4083 # macro -regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_1 = 0x4084 # macro -regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_2 = 0x4085 # macro -regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_3 = 0x4086 # macro -regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_4 = 0x4087 # macro -regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_5 = 0x4088 # macro -regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_6 = 0x4089 # macro -regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_7 = 0x408a # macro -regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_STATUS = 0x408b # macro -regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INTR = 0x408c # macro -regGFX_IMU_PIC_INTR_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INTR_ID = 0x408d # macro -regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_1 = 0x4090 # macro -regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_2 = 0x4091 # macro -regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_3 = 0x4092 # macro -regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 # macro -regGFX_IMU_IH_STATUS = 0x4093 # macro -regGFX_IMU_IH_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_FUSESTRAP = 0x4094 # macro -regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 # macro -regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c # macro -regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_CLK_CTRL = 0x409d # macro -regGFX_IMU_CLK_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_DOORBELL_CONTROL = 0x409e # macro -regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_CG_CTRL = 0x40a0 # macro -regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 # macro -regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 # macro -regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 # macro -regGFX_IMU_RLC_OVERRIDE = 0x40a3 # macro -regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 # macro -regGFX_IMU_DPM_CONTROL = 0x40a8 # macro -regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 # macro -regGFX_IMU_DPM_ACC = 0x40a9 # macro -regGFX_IMU_DPM_ACC_BASE_IDX = 1 # macro -regGFX_IMU_DPM_REF_COUNTER = 0x40aa # macro -regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_INDEX = 0x40ac # macro -regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad # macro -regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae # macro -regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_DATA = 0x40af # macro -regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_CTRL = 0x40b0 # macro -regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_LOG_INIT = 0x40b1 # macro -regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 # macro -regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_PROGRAM_CTR = 0x40b5 # macro -regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 # macro -regGFX_IMU_CORE_CTRL = 0x40b6 # macro -regGFX_IMU_CORE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_CORE_STATUS = 0x40b7 # macro -regGFX_IMU_CORE_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PWROKRAW = 0x40b8 # macro -regGFX_IMU_PWROKRAW_BASE_IDX = 1 # macro -regGFX_IMU_PWROK = 0x40b9 # macro -regGFX_IMU_PWROK_BASE_IDX = 1 # macro -regGFX_IMU_GAP_PWROK = 0x40ba # macro -regGFX_IMU_GAP_PWROK_BASE_IDX = 1 # macro -regGFX_IMU_RESETn = 0x40bb # macro -regGFX_IMU_RESETn_BASE_IDX = 1 # macro -regGFX_IMU_GFX_RESET_CTRL = 0x40bc # macro -regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_AEB_OVERRIDE = 0x40bd # macro -regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 # macro -regGFX_IMU_VDCI_RESET_CTRL = 0x40be # macro -regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_GFX_ISO_CTRL = 0x40bf # macro -regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CTRL0 = 0x40c0 # macro -regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CTRL1 = 0x40c1 # macro -regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 # macro -regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 # macro -regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP0 = 0x40c4 # macro -regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP1 = 0x40c5 # macro -regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP3 = 0x40c7 # macro -regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_VALUE = 0x40c8 # macro -regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CTRL0 = 0x40c9 # macro -regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CTRL1 = 0x40ca # macro -regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb # macro -regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc # macro -regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP0 = 0x40cd # macro -regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP1 = 0x40ce # macro -regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP3 = 0x40d0 # macro -regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_VALUE = 0x40d1 # macro -regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CTRL0 = 0x40d2 # macro -regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CTRL1 = 0x40d3 # macro -regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 # macro -regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 # macro -regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP0 = 0x40d6 # macro -regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP1 = 0x40d7 # macro -regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP3 = 0x40d9 # macro -regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_VALUE = 0x40da # macro -regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_FUSE_CTRL = 0x40e0 # macro -regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_D_RAM_ADDR = 0x40fc # macro -regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_D_RAM_DATA = 0x40fd # macro -regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 # macro -regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff # macro -regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 # macro -regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 # macro -regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro -regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_I_RAM_DATA = 0x5f91 # macro -regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro -ixGC_CAC_ID = 0x0020 # macro -ixGC_CAC_CNTL = 0x0021 # macro -ixGC_CAC_ACC_CP0 = 0x0115 # macro -ixGC_CAC_ACC_CP1 = 0x0116 # macro -ixGC_CAC_ACC_CP2 = 0x0117 # macro -ixGC_CAC_ACC_EA0 = 0x016c # macro -ixGC_CAC_ACC_EA1 = 0x016d # macro -ixGC_CAC_ACC_EA2 = 0x016e # macro -ixGC_CAC_ACC_EA3 = 0x016f # macro -ixGC_CAC_ACC_EA4 = 0x0170 # macro -ixGC_CAC_ACC_EA5 = 0x0171 # macro -ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0177 # macro -ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x0178 # macro -ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x0179 # macro -ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x017a # macro -ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x017b # macro -ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x017c # macro -ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x017d # macro -ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x017e # macro -ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x017f # macro -ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0180 # macro -ixGC_CAC_ACC_UTCL2_VML20 = 0x0181 # macro -ixGC_CAC_ACC_UTCL2_VML21 = 0x0182 # macro -ixGC_CAC_ACC_UTCL2_VML22 = 0x0183 # macro -ixGC_CAC_ACC_UTCL2_VML23 = 0x0184 # macro -ixGC_CAC_ACC_UTCL2_VML24 = 0x0185 # macro -ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0186 # macro -ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0187 # macro -ixGC_CAC_ACC_UTCL2_WALKER2 = 0x0188 # macro -ixGC_CAC_ACC_UTCL2_WALKER3 = 0x0189 # macro -ixGC_CAC_ACC_UTCL2_WALKER4 = 0x018a # macro -ixGC_CAC_ACC_GDS0 = 0x0122 # macro -ixGC_CAC_ACC_GDS1 = 0x0123 # macro -ixGC_CAC_ACC_GDS2 = 0x0124 # macro -ixGC_CAC_ACC_GDS3 = 0x0125 # macro -ixGC_CAC_ACC_GDS4 = 0x0126 # macro -ixGC_CAC_ACC_GE0 = 0x0190 # macro -ixGC_CAC_ACC_GE1 = 0x0191 # macro -ixGC_CAC_ACC_GE2 = 0x0192 # macro -ixGC_CAC_ACC_GE3 = 0x0193 # macro -ixGC_CAC_ACC_GE4 = 0x0194 # macro -ixGC_CAC_ACC_GE5 = 0x0195 # macro -ixGC_CAC_ACC_GE6 = 0x0196 # macro -ixGC_CAC_ACC_GE7 = 0x0197 # macro -ixGC_CAC_ACC_GE8 = 0x0198 # macro -ixGC_CAC_ACC_GE9 = 0x0199 # macro -ixGC_CAC_ACC_GE10 = 0x019a # macro -ixGC_CAC_ACC_GE11 = 0x019b # macro -ixGC_CAC_ACC_GE12 = 0x019c # macro -ixGC_CAC_ACC_GE13 = 0x019d # macro -ixGC_CAC_ACC_GE14 = 0x019e # macro -ixGC_CAC_ACC_GE15 = 0x019f # macro -ixGC_CAC_ACC_GE16 = 0x01a0 # macro -ixGC_CAC_ACC_GE17 = 0x01a1 # macro -ixGC_CAC_ACC_GE18 = 0x01a2 # macro -ixGC_CAC_ACC_GE19 = 0x01a3 # macro -ixGC_CAC_ACC_GE20 = 0x01a4 # macro -ixGC_CAC_ACC_PMM0 = 0x01a5 # macro -ixGC_CAC_ACC_GL2C0 = 0x01a6 # macro -ixGC_CAC_ACC_GL2C1 = 0x01a7 # macro -ixGC_CAC_ACC_GL2C2 = 0x01a8 # macro -ixGC_CAC_ACC_GL2C3 = 0x01a9 # macro -ixGC_CAC_ACC_GL2C4 = 0x01aa # macro -ixGC_CAC_ACC_PH0 = 0x01ae # macro -ixGC_CAC_ACC_PH1 = 0x01af # macro -ixGC_CAC_ACC_PH2 = 0x01b0 # macro -ixGC_CAC_ACC_PH3 = 0x01b1 # macro -ixGC_CAC_ACC_PH4 = 0x01b2 # macro -ixGC_CAC_ACC_PH5 = 0x01b3 # macro -ixGC_CAC_ACC_PH6 = 0x01b4 # macro -ixGC_CAC_ACC_PH7 = 0x01b5 # macro -ixGC_CAC_ACC_SDMA0 = 0x01b6 # macro -ixGC_CAC_ACC_SDMA1 = 0x01b7 # macro -ixGC_CAC_ACC_SDMA2 = 0x01b8 # macro -ixGC_CAC_ACC_SDMA3 = 0x01b9 # macro -ixGC_CAC_ACC_SDMA4 = 0x01ba # macro -ixGC_CAC_ACC_SDMA5 = 0x01bb # macro -ixGC_CAC_ACC_SDMA6 = 0x01bc # macro -ixGC_CAC_ACC_SDMA7 = 0x01bd # macro -ixGC_CAC_ACC_SDMA8 = 0x01be # macro -ixGC_CAC_ACC_SDMA9 = 0x01bf # macro -ixGC_CAC_ACC_SDMA10 = 0x01c0 # macro -ixGC_CAC_ACC_SDMA11 = 0x01c1 # macro -ixGC_CAC_ACC_CHC0 = 0x018d # macro -ixGC_CAC_ACC_CHC1 = 0x018e # macro -ixGC_CAC_ACC_CHC2 = 0x018f # macro -ixGC_CAC_ACC_GUS0 = 0x01ab # macro -ixGC_CAC_ACC_GUS1 = 0x01ac # macro -ixGC_CAC_ACC_GUS2 = 0x01ad # macro -ixGC_CAC_ACC_RLC0 = 0x01d0 # macro -ixRELEASE_TO_STALL_LUT_1_8 = 0x0230 # macro -ixRELEASE_TO_STALL_LUT_9_16 = 0x0231 # macro -ixRELEASE_TO_STALL_LUT_17_20 = 0x0232 # macro -ixSTALL_TO_RELEASE_LUT_1_4 = 0x0233 # macro -ixSTALL_TO_RELEASE_LUT_5_7 = 0x0234 # macro -ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0235 # macro -ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0236 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0237 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0238 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0239 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x023a # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x023b # macro -ixFIXED_PATTERN_PERF_COUNTER_1 = 0x023c # macro -ixFIXED_PATTERN_PERF_COUNTER_2 = 0x023d # macro -ixFIXED_PATTERN_PERF_COUNTER_3 = 0x023e # macro -ixFIXED_PATTERN_PERF_COUNTER_4 = 0x023f # macro -ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0240 # macro -ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0241 # macro -ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0242 # macro -ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0243 # macro -ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0244 # macro -ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0245 # macro -ixHW_LUT_UPDATE_STATUS = 0x0246 # macro -ixSE_CAC_ID = 0x0000 # macro -ixSE_CAC_CNTL = 0x0001 # macro -ixRTAVFS_REG0 = 0x0000 # macro -ixRTAVFS_REG1 = 0x0001 # macro -ixRTAVFS_REG2 = 0x0002 # macro -ixRTAVFS_REG3 = 0x0003 # macro -ixRTAVFS_REG4 = 0x0004 # macro -ixRTAVFS_REG5 = 0x0005 # macro -ixRTAVFS_REG6 = 0x0006 # macro -ixRTAVFS_REG7 = 0x0007 # macro -ixRTAVFS_REG8 = 0x0008 # macro -ixRTAVFS_REG9 = 0x0009 # macro -ixRTAVFS_REG10 = 0x000a # macro -ixRTAVFS_REG11 = 0x000b # macro -ixRTAVFS_REG12 = 0x000c # macro -ixRTAVFS_REG13 = 0x000d # macro -ixRTAVFS_REG14 = 0x000e # macro -ixRTAVFS_REG15 = 0x000f # macro -ixRTAVFS_REG16 = 0x0010 # macro -ixRTAVFS_REG17 = 0x0011 # macro -ixRTAVFS_REG18 = 0x0012 # macro -ixRTAVFS_REG19 = 0x0013 # macro -ixRTAVFS_REG20 = 0x0014 # macro -ixRTAVFS_REG21 = 0x0015 # macro -ixRTAVFS_REG22 = 0x0016 # macro -ixRTAVFS_REG23 = 0x0017 # macro -ixRTAVFS_REG24 = 0x0018 # macro -ixRTAVFS_REG25 = 0x0019 # macro -ixRTAVFS_REG26 = 0x001a # macro -ixRTAVFS_REG27 = 0x001b # macro -ixRTAVFS_REG28 = 0x001c # macro -ixRTAVFS_REG29 = 0x001d # macro -ixRTAVFS_REG30 = 0x001e # macro -ixRTAVFS_REG31 = 0x001f # macro -ixRTAVFS_REG32 = 0x0020 # macro -ixRTAVFS_REG33 = 0x0021 # macro -ixRTAVFS_REG34 = 0x0022 # macro -ixRTAVFS_REG35 = 0x0023 # macro -ixRTAVFS_REG36 = 0x0024 # macro -ixRTAVFS_REG37 = 0x0025 # macro -ixRTAVFS_REG38 = 0x0026 # macro -ixRTAVFS_REG39 = 0x0027 # macro -ixRTAVFS_REG40 = 0x0028 # macro -ixRTAVFS_REG41 = 0x0029 # macro -ixRTAVFS_REG42 = 0x002a # macro -ixRTAVFS_REG43 = 0x002b # macro -ixRTAVFS_REG44 = 0x002c # macro -ixRTAVFS_REG45 = 0x002d # macro -ixRTAVFS_REG46 = 0x002e # macro -ixRTAVFS_REG47 = 0x002f # macro -ixRTAVFS_REG48 = 0x0030 # macro -ixRTAVFS_REG49 = 0x0031 # macro -ixRTAVFS_REG50 = 0x0032 # macro -ixRTAVFS_REG51 = 0x0033 # macro -ixRTAVFS_REG52 = 0x0034 # macro -ixRTAVFS_REG53 = 0x0035 # macro -ixRTAVFS_REG54 = 0x0036 # macro -ixRTAVFS_REG55 = 0x0037 # macro -ixRTAVFS_REG56 = 0x0038 # macro -ixRTAVFS_REG57 = 0x0039 # macro -ixRTAVFS_REG58 = 0x003a # macro -ixRTAVFS_REG59 = 0x003b # macro -ixRTAVFS_REG60 = 0x003c # macro -ixRTAVFS_REG61 = 0x003d # macro -ixRTAVFS_REG62 = 0x003e # macro -ixRTAVFS_REG63 = 0x003f # macro -ixRTAVFS_REG64 = 0x0040 # macro -ixRTAVFS_REG65 = 0x0041 # macro -ixRTAVFS_REG66 = 0x0042 # macro -ixRTAVFS_REG67 = 0x0043 # macro -ixRTAVFS_REG68 = 0x0044 # macro -ixRTAVFS_REG69 = 0x0045 # macro -ixRTAVFS_REG70 = 0x0046 # macro -ixRTAVFS_REG71 = 0x0047 # macro -ixRTAVFS_REG72 = 0x0048 # macro -ixRTAVFS_REG73 = 0x0049 # macro -ixRTAVFS_REG74 = 0x004a # macro -ixRTAVFS_REG75 = 0x004b # macro -ixRTAVFS_REG76 = 0x004c # macro -ixRTAVFS_REG77 = 0x004d # macro -ixRTAVFS_REG78 = 0x004e # macro -ixRTAVFS_REG79 = 0x004f # macro -ixRTAVFS_REG80 = 0x0050 # macro -ixRTAVFS_REG81 = 0x0051 # macro -ixRTAVFS_REG82 = 0x0052 # macro -ixRTAVFS_REG83 = 0x0053 # macro -ixRTAVFS_REG84 = 0x0054 # macro -ixRTAVFS_REG85 = 0x0055 # macro -ixRTAVFS_REG86 = 0x0056 # macro -ixRTAVFS_REG87 = 0x0057 # macro -ixRTAVFS_REG88 = 0x0058 # macro -ixRTAVFS_REG89 = 0x0059 # macro -ixRTAVFS_REG90 = 0x005a # macro -ixRTAVFS_REG91 = 0x005b # macro -ixRTAVFS_REG92 = 0x005c # macro -ixRTAVFS_REG93 = 0x005d # macro -ixRTAVFS_REG94 = 0x005e # macro -ixRTAVFS_REG95 = 0x005f # macro -ixRTAVFS_REG96 = 0x0060 # macro -ixRTAVFS_REG97 = 0x0061 # macro -ixRTAVFS_REG98 = 0x0062 # macro -ixRTAVFS_REG99 = 0x0063 # macro -ixRTAVFS_REG100 = 0x0064 # macro -ixRTAVFS_REG101 = 0x0065 # macro -ixRTAVFS_REG102 = 0x0066 # macro -ixRTAVFS_REG103 = 0x0067 # macro -ixRTAVFS_REG104 = 0x0068 # macro -ixRTAVFS_REG105 = 0x0069 # macro -ixRTAVFS_REG106 = 0x006a # macro -ixRTAVFS_REG107 = 0x006b # macro -ixRTAVFS_REG108 = 0x006c # macro -ixRTAVFS_REG109 = 0x006d # macro -ixRTAVFS_REG110 = 0x006e # macro -ixRTAVFS_REG111 = 0x006f # macro -ixRTAVFS_REG112 = 0x0070 # macro -ixRTAVFS_REG113 = 0x0071 # macro -ixRTAVFS_REG114 = 0x0072 # macro -ixRTAVFS_REG115 = 0x0073 # macro -ixRTAVFS_REG116 = 0x0074 # macro -ixRTAVFS_REG117 = 0x0075 # macro -ixRTAVFS_REG118 = 0x0076 # macro -ixRTAVFS_REG119 = 0x0077 # macro -ixRTAVFS_REG120 = 0x0078 # macro -ixRTAVFS_REG121 = 0x0079 # macro -ixRTAVFS_REG122 = 0x007a # macro -ixRTAVFS_REG123 = 0x007b # macro -ixRTAVFS_REG124 = 0x007c # macro -ixRTAVFS_REG125 = 0x007d # macro -ixRTAVFS_REG126 = 0x007e # macro -ixRTAVFS_REG127 = 0x007f # macro -ixRTAVFS_REG128 = 0x0080 # macro -ixRTAVFS_REG129 = 0x0081 # macro -ixRTAVFS_REG130 = 0x0082 # macro -ixRTAVFS_REG131 = 0x0083 # macro -ixRTAVFS_REG132 = 0x0084 # macro -ixRTAVFS_REG133 = 0x0085 # macro -ixRTAVFS_REG134 = 0x0086 # macro -ixRTAVFS_REG135 = 0x0087 # macro -ixRTAVFS_REG136 = 0x0088 # macro -ixRTAVFS_REG137 = 0x0089 # macro -ixRTAVFS_REG138 = 0x008a # macro -ixRTAVFS_REG139 = 0x008b # macro -ixRTAVFS_REG140 = 0x008c # macro -ixRTAVFS_REG141 = 0x008d # macro -ixRTAVFS_REG142 = 0x008e # macro -ixRTAVFS_REG143 = 0x008f # macro -ixRTAVFS_REG144 = 0x0090 # macro -ixRTAVFS_REG145 = 0x0091 # macro -ixRTAVFS_REG146 = 0x0092 # macro -ixRTAVFS_REG147 = 0x0093 # macro -ixRTAVFS_REG148 = 0x0094 # macro -ixRTAVFS_REG149 = 0x0095 # macro -ixRTAVFS_REG150 = 0x0096 # macro -ixRTAVFS_REG151 = 0x0097 # macro -ixRTAVFS_REG152 = 0x0098 # macro -ixRTAVFS_REG153 = 0x0099 # macro -ixRTAVFS_REG154 = 0x009a # macro -ixRTAVFS_REG155 = 0x009b # macro -ixRTAVFS_REG156 = 0x009c # macro -ixRTAVFS_REG157 = 0x009d # macro -ixRTAVFS_REG158 = 0x009e # macro -ixRTAVFS_REG159 = 0x009f # macro -ixRTAVFS_REG160 = 0x00a0 # macro -ixRTAVFS_REG161 = 0x00a1 # macro -ixRTAVFS_REG162 = 0x00a2 # macro -ixRTAVFS_REG163 = 0x00a3 # macro -ixRTAVFS_REG164 = 0x00a4 # macro -ixRTAVFS_REG165 = 0x00a5 # macro -ixRTAVFS_REG166 = 0x00a6 # macro -ixRTAVFS_REG167 = 0x00a7 # macro -ixRTAVFS_REG168 = 0x00a8 # macro -ixRTAVFS_REG169 = 0x00a9 # macro -ixRTAVFS_REG170 = 0x00aa # macro -ixRTAVFS_REG171 = 0x00ab # macro -ixRTAVFS_REG172 = 0x00ac # macro -ixRTAVFS_REG173 = 0x00ad # macro -ixRTAVFS_REG174 = 0x00ae # macro -ixRTAVFS_REG175 = 0x00af # macro -ixRTAVFS_REG176 = 0x00b0 # macro -ixRTAVFS_REG177 = 0x00b1 # macro -ixRTAVFS_REG178 = 0x00b2 # macro -ixRTAVFS_REG179 = 0x00b3 # macro -ixRTAVFS_REG180 = 0x00b4 # macro -ixRTAVFS_REG181 = 0x00b5 # macro -ixRTAVFS_REG182 = 0x00b6 # macro -ixRTAVFS_REG183 = 0x00b7 # macro -ixRTAVFS_REG184 = 0x00b8 # macro -ixRTAVFS_REG185 = 0x00b9 # macro -ixRTAVFS_REG186 = 0x00ba # macro -ixRTAVFS_REG187 = 0x00bb # macro -ixRTAVFS_REG188 = 0x00bc # macro -ixRTAVFS_REG189 = 0x00bd # macro -ixRTAVFS_REG190 = 0x00be # macro -ixRTAVFS_REG191 = 0x00bf # macro -ixRTAVFS_REG192 = 0x00c0 # macro -ixRTAVFS_REG193 = 0x00c1 # macro -ixRTAVFS_REG194 = 0x00c2 # macro -ixSQ_DEBUG_STS_LOCAL = 0x0008 # macro -ixSQ_DEBUG_CTRL_LOCAL = 0x0009 # macro -ixSQ_WAVE_ACTIVE = 0x000a # macro -ixSQ_WAVE_VALID_AND_IDLE = 0x000b # macro -ixSQ_WAVE_MODE = 0x0101 # macro -ixSQ_WAVE_STATUS = 0x0102 # macro -ixSQ_WAVE_TRAPSTS = 0x0103 # macro -ixSQ_WAVE_GPR_ALLOC = 0x0105 # macro -ixSQ_WAVE_LDS_ALLOC = 0x0106 # macro -ixSQ_WAVE_IB_STS = 0x0107 # macro -ixSQ_WAVE_PC_LO = 0x0108 # macro -ixSQ_WAVE_PC_HI = 0x0109 # macro -ixSQ_WAVE_IB_DBG1 = 0x010d # macro -ixSQ_WAVE_FLUSH_IB = 0x010e # macro -ixSQ_WAVE_FLAT_SCRATCH_LO = 0x0114 # macro -ixSQ_WAVE_FLAT_SCRATCH_HI = 0x0115 # macro -ixSQ_WAVE_HW_ID1 = 0x0117 # macro -ixSQ_WAVE_HW_ID2 = 0x0118 # macro -ixSQ_WAVE_POPS_PACKER = 0x0119 # macro -ixSQ_WAVE_SCHED_MODE = 0x011a # macro -ixSQ_WAVE_IB_STS2 = 0x011c # macro -ixSQ_WAVE_SHADER_CYCLES = 0x011d # macro -ixSQ_WAVE_TTMP0 = 0x026c # macro -ixSQ_WAVE_TTMP1 = 0x026d # macro -ixSQ_WAVE_TTMP3 = 0x026f # macro -ixSQ_WAVE_TTMP4 = 0x0270 # macro -ixSQ_WAVE_TTMP5 = 0x0271 # macro -ixSQ_WAVE_TTMP6 = 0x0272 # macro -ixSQ_WAVE_TTMP7 = 0x0273 # macro -ixSQ_WAVE_TTMP8 = 0x0274 # macro -ixSQ_WAVE_TTMP9 = 0x0275 # macro -ixSQ_WAVE_TTMP10 = 0x0276 # macro -ixSQ_WAVE_TTMP11 = 0x0277 # macro -ixSQ_WAVE_TTMP12 = 0x0278 # macro -ixSQ_WAVE_TTMP13 = 0x0279 # macro -ixSQ_WAVE_TTMP14 = 0x027a # macro -ixSQ_WAVE_TTMP15 = 0x027b # macro -ixSQ_WAVE_M0 = 0x027c # macro -ixSQ_WAVE_EXEC_LO = 0x027e # macro -ixSQ_WAVE_EXEC_HI = 0x027f # macro -_gc_10_3_0_OFFSET_HEADER = True # macro -mmSQ_DEBUG_STS_GLOBAL = 0x10A9 # macro -mmSQ_DEBUG_STS_GLOBAL_BASE_IDX = 0 # macro -mmSQ_DEBUG_STS_GLOBAL2 = 0x10B0 # macro -mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 0 # macro -mmSQ_DEBUG = 0x10B1 # macro -mmSQ_DEBUG_BASE_IDX = 0 # macro -mmSDMA0_DEC_START = 0x0000 # macro -mmSDMA0_DEC_START_BASE_IDX = 0 # macro -mmSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro -mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -mmSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro -mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -mmSDMA0_PG_CNTL = 0x0016 # macro -mmSDMA0_PG_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PG_CTX_LO = 0x0017 # macro -mmSDMA0_PG_CTX_LO_BASE_IDX = 0 # macro -mmSDMA0_PG_CTX_HI = 0x0018 # macro -mmSDMA0_PG_CTX_HI_BASE_IDX = 0 # macro -mmSDMA0_PG_CTX_CNTL = 0x0019 # macro -mmSDMA0_PG_CTX_CNTL_BASE_IDX = 0 # macro -mmSDMA0_POWER_CNTL = 0x001a # macro -mmSDMA0_POWER_CNTL_BASE_IDX = 0 # macro -mmSDMA0_CLK_CTRL = 0x001b # macro -mmSDMA0_CLK_CTRL_BASE_IDX = 0 # macro -mmSDMA0_CNTL = 0x001c # macro -mmSDMA0_CNTL_BASE_IDX = 0 # macro -mmSDMA0_CHICKEN_BITS = 0x001d # macro -mmSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro -mmSDMA0_GB_ADDR_CONFIG = 0x001e # macro -mmSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -mmSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro -mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -mmSDMA0_RB_RPTR_FETCH_HI = 0x0020 # macro -mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro -mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RB_RPTR_FETCH = 0x0022 # macro -mmSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro -mmSDMA0_IB_OFFSET_FETCH = 0x0023 # macro -mmSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -mmSDMA0_PROGRAM = 0x0024 # macro -mmSDMA0_PROGRAM_BASE_IDX = 0 # macro -mmSDMA0_STATUS_REG = 0x0025 # macro -mmSDMA0_STATUS_REG_BASE_IDX = 0 # macro -mmSDMA0_STATUS1_REG = 0x0026 # macro -mmSDMA0_STATUS1_REG_BASE_IDX = 0 # macro -mmSDMA0_RD_BURST_CNTL = 0x0027 # macro -mmSDMA0_RD_BURST_CNTL_BASE_IDX = 0 # macro -mmSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro -mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -mmSDMA0_UCODE_CHECKSUM = 0x0029 # macro -mmSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro -mmSDMA0_F32_CNTL = 0x002a # macro -mmSDMA0_F32_CNTL_BASE_IDX = 0 # macro -mmSDMA0_FREEZE = 0x002b # macro -mmSDMA0_FREEZE_BASE_IDX = 0 # macro -mmSDMA0_PHASE0_QUANTUM = 0x002c # macro -mmSDMA0_PHASE0_QUANTUM_BASE_IDX = 0 # macro -mmSDMA0_PHASE1_QUANTUM = 0x002d # macro -mmSDMA0_PHASE1_QUANTUM_BASE_IDX = 0 # macro -mmSDMA0_EDC_CONFIG = 0x0032 # macro -mmSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro -mmSDMA0_BA_THRESHOLD = 0x0033 # macro -mmSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro -mmSDMA0_ID = 0x0034 # macro -mmSDMA0_ID_BASE_IDX = 0 # macro -mmSDMA0_VERSION = 0x0035 # macro -mmSDMA0_VERSION_BASE_IDX = 0 # macro -mmSDMA0_EDC_COUNTER = 0x0036 # macro -mmSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro -mmSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro -mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -mmSDMA0_STATUS2_REG = 0x0038 # macro -mmSDMA0_STATUS2_REG_BASE_IDX = 0 # macro -mmSDMA0_ATOMIC_CNTL = 0x0039 # macro -mmSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro -mmSDMA0_ATOMIC_PREOP_LO = 0x003a # macro -mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -mmSDMA0_ATOMIC_PREOP_HI = 0x003b # macro -mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_CNTL = 0x003c # macro -mmSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_WATERMK = 0x003d # macro -mmSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_RD_STATUS = 0x003e # macro -mmSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_WR_STATUS = 0x003f # macro -mmSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_INV0 = 0x0040 # macro -mmSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_INV1 = 0x0041 # macro -mmSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_INV2 = 0x0042 # macro -mmSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_RD_XNACK0 = 0x0043 # macro -mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_RD_XNACK1 = 0x0044 # macro -mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_WR_XNACK0 = 0x0045 # macro -mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_WR_XNACK1 = 0x0046 # macro -mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_TIMEOUT = 0x0047 # macro -mmSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -mmSDMA0_UTCL1_PAGE = 0x0048 # macro -mmSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro -mmSDMA0_RELAX_ORDERING_LUT = 0x004a # macro -mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -mmSDMA0_CHICKEN_BITS_2 = 0x004b # macro -mmSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro -mmSDMA0_STATUS3_REG = 0x004c # macro -mmSDMA0_STATUS3_REG_BASE_IDX = 0 # macro -mmSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro -mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro -mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_PHASE2_QUANTUM = 0x004f # macro -mmSDMA0_PHASE2_QUANTUM_BASE_IDX = 0 # macro -mmSDMA0_ERROR_LOG = 0x0050 # macro -mmSDMA0_ERROR_LOG_BASE_IDX = 0 # macro -mmSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro -mmSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -mmSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro -mmSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -mmSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro -mmSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -mmSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro -mmSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -mmSDMA0_F32_COUNTER = 0x0055 # macro -mmSDMA0_F32_COUNTER_BASE_IDX = 0 # macro -mmSDMA0_CRD_CNTL = 0x005b # macro -mmSDMA0_CRD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_AQL_STATUS = 0x005f # macro -mmSDMA0_AQL_STATUS_BASE_IDX = 0 # macro -mmSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro -mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -mmSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro -mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -mmSDMA0_TLBI_GCR_CNTL = 0x0062 # macro -mmSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -mmSDMA0_TILING_CONFIG = 0x0063 # macro -mmSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro -mmSDMA0_INT_STATUS = 0x0070 # macro -mmSDMA0_INT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_HOLE_ADDR_LO = 0x0072 # macro -mmSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_HOLE_ADDR_HI = 0x0073 # macro -mmSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_CLOCK_GATING_REG = 0x0075 # macro -mmSDMA0_CLOCK_GATING_REG_BASE_IDX = 0 # macro -mmSDMA0_STATUS4_REG = 0x0076 # macro -mmSDMA0_STATUS4_REG_BASE_IDX = 0 # macro -mmSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro -mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -mmSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro -mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -mmSDMA0_TIMESTAMP_CNTL = 0x0079 # macro -mmSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_STATUS5_REG = 0x007a # macro -mmSDMA0_STATUS5_REG_BASE_IDX = 0 # macro -mmSDMA0_QUEUE_RESET_REQ = 0x007b # macro -mmSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_CNTL = 0x0080 # macro -mmSDMA0_GFX_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_BASE = 0x0081 # macro -mmSDMA0_GFX_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_BASE_HI = 0x0082 # macro -mmSDMA0_GFX_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_RPTR = 0x0083 # macro -mmSDMA0_GFX_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_RPTR_HI = 0x0084 # macro -mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_WPTR = 0x0085 # macro -mmSDMA0_GFX_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_WPTR_HI = 0x0086 # macro -mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro -mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro -mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro -mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_CNTL = 0x008a # macro -mmSDMA0_GFX_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_RPTR = 0x008b # macro -mmSDMA0_GFX_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_OFFSET = 0x008c # macro -mmSDMA0_GFX_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_BASE_LO = 0x008d # macro -mmSDMA0_GFX_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_BASE_HI = 0x008e # macro -mmSDMA0_GFX_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_SIZE = 0x008f # macro -mmSDMA0_GFX_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_GFX_SKIP_CNTL = 0x0090 # macro -mmSDMA0_GFX_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_CONTEXT_STATUS = 0x0091 # macro -mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_GFX_DOORBELL = 0x0092 # macro -mmSDMA0_GFX_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_GFX_CONTEXT_CNTL = 0x0093 # macro -mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_STATUS = 0x00a8 # macro -mmSDMA0_GFX_STATUS_BASE_IDX = 0 # macro -mmSDMA0_GFX_DOORBELL_LOG = 0x00a9 # macro -mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_GFX_WATERMARK = 0x00aa # macro -mmSDMA0_GFX_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_GFX_DOORBELL_OFFSET = 0x00ab # macro -mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_GFX_CSA_ADDR_LO = 0x00ac # macro -mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_GFX_CSA_ADDR_HI = 0x00ad # macro -mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_IB_SUB_REMAIN = 0x00af # macro -mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_GFX_PREEMPT = 0x00b0 # macro -mmSDMA0_GFX_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_GFX_DUMMY_REG = 0x00b1 # macro -mmSDMA0_GFX_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro -mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro -mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_GFX_RB_AQL_CNTL = 0x00b4 # macro -mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro -mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA0 = 0x00c0 # macro -mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA1 = 0x00c1 # macro -mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA2 = 0x00c2 # macro -mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA3 = 0x00c3 # macro -mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA4 = 0x00c4 # macro -mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA5 = 0x00c5 # macro -mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA6 = 0x00c6 # macro -mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA7 = 0x00c7 # macro -mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA8 = 0x00c8 # macro -mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA9 = 0x00c9 # macro -mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_DATA10 = 0x00ca # macro -mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_GFX_MIDCMD_CNTL = 0x00cb # macro -mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_CNTL = 0x00d8 # macro -mmSDMA0_PAGE_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_BASE = 0x00d9 # macro -mmSDMA0_PAGE_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_BASE_HI = 0x00da # macro -mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_RPTR = 0x00db # macro -mmSDMA0_PAGE_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_RPTR_HI = 0x00dc # macro -mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_WPTR = 0x00dd # macro -mmSDMA0_PAGE_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_WPTR_HI = 0x00de # macro -mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro -mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro -mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro -mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_CNTL = 0x00e2 # macro -mmSDMA0_PAGE_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_RPTR = 0x00e3 # macro -mmSDMA0_PAGE_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_OFFSET = 0x00e4 # macro -mmSDMA0_PAGE_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_BASE_LO = 0x00e5 # macro -mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_BASE_HI = 0x00e6 # macro -mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_SIZE = 0x00e7 # macro -mmSDMA0_PAGE_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_PAGE_SKIP_CNTL = 0x00e8 # macro -mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_CONTEXT_STATUS = 0x00e9 # macro -mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_PAGE_DOORBELL = 0x00ea # macro -mmSDMA0_PAGE_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_STATUS = 0x0100 # macro -mmSDMA0_PAGE_STATUS_BASE_IDX = 0 # macro -mmSDMA0_PAGE_DOORBELL_LOG = 0x0101 # macro -mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_PAGE_WATERMARK = 0x0102 # macro -mmSDMA0_PAGE_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_PAGE_DOORBELL_OFFSET = 0x0103 # macro -mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_PAGE_CSA_ADDR_LO = 0x0104 # macro -mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_PAGE_CSA_ADDR_HI = 0x0105 # macro -mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_IB_SUB_REMAIN = 0x0107 # macro -mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_PAGE_PREEMPT = 0x0108 # macro -mmSDMA0_PAGE_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_PAGE_DUMMY_REG = 0x0109 # macro -mmSDMA0_PAGE_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro -mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro -mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_PAGE_RB_AQL_CNTL = 0x010c # macro -mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MINOR_PTR_UPDATE = 0x010d # macro -mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA0 = 0x0118 # macro -mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA1 = 0x0119 # macro -mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA2 = 0x011a # macro -mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA3 = 0x011b # macro -mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA4 = 0x011c # macro -mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA5 = 0x011d # macro -mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA6 = 0x011e # macro -mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA7 = 0x011f # macro -mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA8 = 0x0120 # macro -mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA9 = 0x0121 # macro -mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_DATA10 = 0x0122 # macro -mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_PAGE_MIDCMD_CNTL = 0x0123 # macro -mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_CNTL = 0x0130 # macro -mmSDMA0_RLC0_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_BASE = 0x0131 # macro -mmSDMA0_RLC0_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_BASE_HI = 0x0132 # macro -mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_RPTR = 0x0133 # macro -mmSDMA0_RLC0_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_RPTR_HI = 0x0134 # macro -mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_WPTR = 0x0135 # macro -mmSDMA0_RLC0_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_WPTR_HI = 0x0136 # macro -mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro -mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro -mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_CNTL = 0x013a # macro -mmSDMA0_RLC0_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_RPTR = 0x013b # macro -mmSDMA0_RLC0_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_OFFSET = 0x013c # macro -mmSDMA0_RLC0_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_BASE_LO = 0x013d # macro -mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_BASE_HI = 0x013e # macro -mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_SIZE = 0x013f # macro -mmSDMA0_RLC0_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC0_SKIP_CNTL = 0x0140 # macro -mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_CONTEXT_STATUS = 0x0141 # macro -mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC0_DOORBELL = 0x0142 # macro -mmSDMA0_RLC0_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_STATUS = 0x0158 # macro -mmSDMA0_RLC0_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC0_DOORBELL_LOG = 0x0159 # macro -mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC0_WATERMARK = 0x015a # macro -mmSDMA0_RLC0_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC0_DOORBELL_OFFSET = 0x015b # macro -mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC0_CSA_ADDR_LO = 0x015c # macro -mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC0_CSA_ADDR_HI = 0x015d # macro -mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_IB_SUB_REMAIN = 0x015f # macro -mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC0_PREEMPT = 0x0160 # macro -mmSDMA0_RLC0_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC0_DUMMY_REG = 0x0161 # macro -mmSDMA0_RLC0_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro -mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC0_RB_AQL_CNTL = 0x0164 # macro -mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro -mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA0 = 0x0170 # macro -mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA1 = 0x0171 # macro -mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA2 = 0x0172 # macro -mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA3 = 0x0173 # macro -mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA4 = 0x0174 # macro -mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA5 = 0x0175 # macro -mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA6 = 0x0176 # macro -mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA7 = 0x0177 # macro -mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA8 = 0x0178 # macro -mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA9 = 0x0179 # macro -mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_DATA10 = 0x017a # macro -mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC0_MIDCMD_CNTL = 0x017b # macro -mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_CNTL = 0x0188 # macro -mmSDMA0_RLC1_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_BASE = 0x0189 # macro -mmSDMA0_RLC1_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_BASE_HI = 0x018a # macro -mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_RPTR = 0x018b # macro -mmSDMA0_RLC1_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_RPTR_HI = 0x018c # macro -mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_WPTR = 0x018d # macro -mmSDMA0_RLC1_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_WPTR_HI = 0x018e # macro -mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro -mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro -mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro -mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_CNTL = 0x0192 # macro -mmSDMA0_RLC1_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_RPTR = 0x0193 # macro -mmSDMA0_RLC1_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_OFFSET = 0x0194 # macro -mmSDMA0_RLC1_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_BASE_LO = 0x0195 # macro -mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_BASE_HI = 0x0196 # macro -mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_SIZE = 0x0197 # macro -mmSDMA0_RLC1_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC1_SKIP_CNTL = 0x0198 # macro -mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_CONTEXT_STATUS = 0x0199 # macro -mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC1_DOORBELL = 0x019a # macro -mmSDMA0_RLC1_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_STATUS = 0x01b0 # macro -mmSDMA0_RLC1_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC1_DOORBELL_LOG = 0x01b1 # macro -mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC1_WATERMARK = 0x01b2 # macro -mmSDMA0_RLC1_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC1_DOORBELL_OFFSET = 0x01b3 # macro -mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC1_CSA_ADDR_LO = 0x01b4 # macro -mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC1_CSA_ADDR_HI = 0x01b5 # macro -mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_IB_SUB_REMAIN = 0x01b7 # macro -mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC1_PREEMPT = 0x01b8 # macro -mmSDMA0_RLC1_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC1_DUMMY_REG = 0x01b9 # macro -mmSDMA0_RLC1_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro -mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro -mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC1_RB_AQL_CNTL = 0x01bc # macro -mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro -mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA0 = 0x01c8 # macro -mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA1 = 0x01c9 # macro -mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA2 = 0x01ca # macro -mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA3 = 0x01cb # macro -mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA4 = 0x01cc # macro -mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA5 = 0x01cd # macro -mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA6 = 0x01ce # macro -mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA7 = 0x01cf # macro -mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA8 = 0x01d0 # macro -mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA9 = 0x01d1 # macro -mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_DATA10 = 0x01d2 # macro -mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC1_MIDCMD_CNTL = 0x01d3 # macro -mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_CNTL = 0x01e0 # macro -mmSDMA0_RLC2_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_BASE = 0x01e1 # macro -mmSDMA0_RLC2_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_BASE_HI = 0x01e2 # macro -mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_RPTR = 0x01e3 # macro -mmSDMA0_RLC2_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_RPTR_HI = 0x01e4 # macro -mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_WPTR = 0x01e5 # macro -mmSDMA0_RLC2_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_WPTR_HI = 0x01e6 # macro -mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro -mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro -mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_CNTL = 0x01ea # macro -mmSDMA0_RLC2_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_RPTR = 0x01eb # macro -mmSDMA0_RLC2_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_OFFSET = 0x01ec # macro -mmSDMA0_RLC2_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_BASE_LO = 0x01ed # macro -mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_BASE_HI = 0x01ee # macro -mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_SIZE = 0x01ef # macro -mmSDMA0_RLC2_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC2_SKIP_CNTL = 0x01f0 # macro -mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_CONTEXT_STATUS = 0x01f1 # macro -mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC2_DOORBELL = 0x01f2 # macro -mmSDMA0_RLC2_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_STATUS = 0x0208 # macro -mmSDMA0_RLC2_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC2_DOORBELL_LOG = 0x0209 # macro -mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC2_WATERMARK = 0x020a # macro -mmSDMA0_RLC2_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC2_DOORBELL_OFFSET = 0x020b # macro -mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC2_CSA_ADDR_LO = 0x020c # macro -mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC2_CSA_ADDR_HI = 0x020d # macro -mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_IB_SUB_REMAIN = 0x020f # macro -mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC2_PREEMPT = 0x0210 # macro -mmSDMA0_RLC2_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC2_DUMMY_REG = 0x0211 # macro -mmSDMA0_RLC2_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro -mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC2_RB_AQL_CNTL = 0x0214 # macro -mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro -mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA0 = 0x0220 # macro -mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA1 = 0x0221 # macro -mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA2 = 0x0222 # macro -mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA3 = 0x0223 # macro -mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA4 = 0x0224 # macro -mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA5 = 0x0225 # macro -mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA6 = 0x0226 # macro -mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA7 = 0x0227 # macro -mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA8 = 0x0228 # macro -mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA9 = 0x0229 # macro -mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_DATA10 = 0x022a # macro -mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC2_MIDCMD_CNTL = 0x022b # macro -mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_CNTL = 0x0238 # macro -mmSDMA0_RLC3_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_BASE = 0x0239 # macro -mmSDMA0_RLC3_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_BASE_HI = 0x023a # macro -mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_RPTR = 0x023b # macro -mmSDMA0_RLC3_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_RPTR_HI = 0x023c # macro -mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_WPTR = 0x023d # macro -mmSDMA0_RLC3_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_WPTR_HI = 0x023e # macro -mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro -mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro -mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro -mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_CNTL = 0x0242 # macro -mmSDMA0_RLC3_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_RPTR = 0x0243 # macro -mmSDMA0_RLC3_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_OFFSET = 0x0244 # macro -mmSDMA0_RLC3_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_BASE_LO = 0x0245 # macro -mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_BASE_HI = 0x0246 # macro -mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_SIZE = 0x0247 # macro -mmSDMA0_RLC3_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC3_SKIP_CNTL = 0x0248 # macro -mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_CONTEXT_STATUS = 0x0249 # macro -mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC3_DOORBELL = 0x024a # macro -mmSDMA0_RLC3_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_STATUS = 0x0260 # macro -mmSDMA0_RLC3_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC3_DOORBELL_LOG = 0x0261 # macro -mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC3_WATERMARK = 0x0262 # macro -mmSDMA0_RLC3_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC3_DOORBELL_OFFSET = 0x0263 # macro -mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC3_CSA_ADDR_LO = 0x0264 # macro -mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC3_CSA_ADDR_HI = 0x0265 # macro -mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_IB_SUB_REMAIN = 0x0267 # macro -mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC3_PREEMPT = 0x0268 # macro -mmSDMA0_RLC3_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC3_DUMMY_REG = 0x0269 # macro -mmSDMA0_RLC3_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro -mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro -mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC3_RB_AQL_CNTL = 0x026c # macro -mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MINOR_PTR_UPDATE = 0x026d # macro -mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA0 = 0x0278 # macro -mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA1 = 0x0279 # macro -mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA2 = 0x027a # macro -mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA3 = 0x027b # macro -mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA4 = 0x027c # macro -mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA5 = 0x027d # macro -mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA6 = 0x027e # macro -mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA7 = 0x027f # macro -mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA8 = 0x0280 # macro -mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA9 = 0x0281 # macro -mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_DATA10 = 0x0282 # macro -mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC3_MIDCMD_CNTL = 0x0283 # macro -mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_CNTL = 0x0290 # macro -mmSDMA0_RLC4_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_BASE = 0x0291 # macro -mmSDMA0_RLC4_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_BASE_HI = 0x0292 # macro -mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_RPTR = 0x0293 # macro -mmSDMA0_RLC4_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_RPTR_HI = 0x0294 # macro -mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_WPTR = 0x0295 # macro -mmSDMA0_RLC4_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_WPTR_HI = 0x0296 # macro -mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro -mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro -mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_CNTL = 0x029a # macro -mmSDMA0_RLC4_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_RPTR = 0x029b # macro -mmSDMA0_RLC4_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_OFFSET = 0x029c # macro -mmSDMA0_RLC4_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_BASE_LO = 0x029d # macro -mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_BASE_HI = 0x029e # macro -mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_SIZE = 0x029f # macro -mmSDMA0_RLC4_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC4_SKIP_CNTL = 0x02a0 # macro -mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_CONTEXT_STATUS = 0x02a1 # macro -mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC4_DOORBELL = 0x02a2 # macro -mmSDMA0_RLC4_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_STATUS = 0x02b8 # macro -mmSDMA0_RLC4_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC4_DOORBELL_LOG = 0x02b9 # macro -mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC4_WATERMARK = 0x02ba # macro -mmSDMA0_RLC4_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC4_DOORBELL_OFFSET = 0x02bb # macro -mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC4_CSA_ADDR_LO = 0x02bc # macro -mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC4_CSA_ADDR_HI = 0x02bd # macro -mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_IB_SUB_REMAIN = 0x02bf # macro -mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC4_PREEMPT = 0x02c0 # macro -mmSDMA0_RLC4_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC4_DUMMY_REG = 0x02c1 # macro -mmSDMA0_RLC4_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro -mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC4_RB_AQL_CNTL = 0x02c4 # macro -mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro -mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA0 = 0x02d0 # macro -mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA1 = 0x02d1 # macro -mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA2 = 0x02d2 # macro -mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA3 = 0x02d3 # macro -mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA4 = 0x02d4 # macro -mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA5 = 0x02d5 # macro -mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA6 = 0x02d6 # macro -mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA7 = 0x02d7 # macro -mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA8 = 0x02d8 # macro -mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA9 = 0x02d9 # macro -mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_DATA10 = 0x02da # macro -mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC4_MIDCMD_CNTL = 0x02db # macro -mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_CNTL = 0x02e8 # macro -mmSDMA0_RLC5_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_BASE = 0x02e9 # macro -mmSDMA0_RLC5_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_BASE_HI = 0x02ea # macro -mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_RPTR = 0x02eb # macro -mmSDMA0_RLC5_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_RPTR_HI = 0x02ec # macro -mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_WPTR = 0x02ed # macro -mmSDMA0_RLC5_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_WPTR_HI = 0x02ee # macro -mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro -mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro -mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro -mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_CNTL = 0x02f2 # macro -mmSDMA0_RLC5_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_RPTR = 0x02f3 # macro -mmSDMA0_RLC5_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_OFFSET = 0x02f4 # macro -mmSDMA0_RLC5_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_BASE_LO = 0x02f5 # macro -mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_BASE_HI = 0x02f6 # macro -mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_SIZE = 0x02f7 # macro -mmSDMA0_RLC5_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC5_SKIP_CNTL = 0x02f8 # macro -mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_CONTEXT_STATUS = 0x02f9 # macro -mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC5_DOORBELL = 0x02fa # macro -mmSDMA0_RLC5_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_STATUS = 0x0310 # macro -mmSDMA0_RLC5_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC5_DOORBELL_LOG = 0x0311 # macro -mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC5_WATERMARK = 0x0312 # macro -mmSDMA0_RLC5_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC5_DOORBELL_OFFSET = 0x0313 # macro -mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC5_CSA_ADDR_LO = 0x0314 # macro -mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC5_CSA_ADDR_HI = 0x0315 # macro -mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_IB_SUB_REMAIN = 0x0317 # macro -mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC5_PREEMPT = 0x0318 # macro -mmSDMA0_RLC5_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC5_DUMMY_REG = 0x0319 # macro -mmSDMA0_RLC5_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro -mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro -mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC5_RB_AQL_CNTL = 0x031c # macro -mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MINOR_PTR_UPDATE = 0x031d # macro -mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA0 = 0x0328 # macro -mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA1 = 0x0329 # macro -mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA2 = 0x032a # macro -mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA3 = 0x032b # macro -mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA4 = 0x032c # macro -mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA5 = 0x032d # macro -mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA6 = 0x032e # macro -mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA7 = 0x032f # macro -mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA8 = 0x0330 # macro -mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA9 = 0x0331 # macro -mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_DATA10 = 0x0332 # macro -mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC5_MIDCMD_CNTL = 0x0333 # macro -mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_CNTL = 0x0340 # macro -mmSDMA0_RLC6_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_BASE = 0x0341 # macro -mmSDMA0_RLC6_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_BASE_HI = 0x0342 # macro -mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_RPTR = 0x0343 # macro -mmSDMA0_RLC6_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_RPTR_HI = 0x0344 # macro -mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_WPTR = 0x0345 # macro -mmSDMA0_RLC6_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_WPTR_HI = 0x0346 # macro -mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro -mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro -mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_CNTL = 0x034a # macro -mmSDMA0_RLC6_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_RPTR = 0x034b # macro -mmSDMA0_RLC6_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_OFFSET = 0x034c # macro -mmSDMA0_RLC6_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_BASE_LO = 0x034d # macro -mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_BASE_HI = 0x034e # macro -mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_SIZE = 0x034f # macro -mmSDMA0_RLC6_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC6_SKIP_CNTL = 0x0350 # macro -mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_CONTEXT_STATUS = 0x0351 # macro -mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC6_DOORBELL = 0x0352 # macro -mmSDMA0_RLC6_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_STATUS = 0x0368 # macro -mmSDMA0_RLC6_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC6_DOORBELL_LOG = 0x0369 # macro -mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC6_WATERMARK = 0x036a # macro -mmSDMA0_RLC6_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC6_DOORBELL_OFFSET = 0x036b # macro -mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC6_CSA_ADDR_LO = 0x036c # macro -mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC6_CSA_ADDR_HI = 0x036d # macro -mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_IB_SUB_REMAIN = 0x036f # macro -mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC6_PREEMPT = 0x0370 # macro -mmSDMA0_RLC6_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC6_DUMMY_REG = 0x0371 # macro -mmSDMA0_RLC6_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro -mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC6_RB_AQL_CNTL = 0x0374 # macro -mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro -mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA0 = 0x0380 # macro -mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA1 = 0x0381 # macro -mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA2 = 0x0382 # macro -mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA3 = 0x0383 # macro -mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA4 = 0x0384 # macro -mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA5 = 0x0385 # macro -mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA6 = 0x0386 # macro -mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA7 = 0x0387 # macro -mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA8 = 0x0388 # macro -mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA9 = 0x0389 # macro -mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_DATA10 = 0x038a # macro -mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC6_MIDCMD_CNTL = 0x038b # macro -mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_CNTL = 0x0398 # macro -mmSDMA0_RLC7_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_BASE = 0x0399 # macro -mmSDMA0_RLC7_RB_BASE_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_BASE_HI = 0x039a # macro -mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_RPTR = 0x039b # macro -mmSDMA0_RLC7_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_RPTR_HI = 0x039c # macro -mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_WPTR = 0x039d # macro -mmSDMA0_RLC7_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_WPTR_HI = 0x039e # macro -mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro -mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro -mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro -mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_CNTL = 0x03a2 # macro -mmSDMA0_RLC7_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_RPTR = 0x03a3 # macro -mmSDMA0_RLC7_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_OFFSET = 0x03a4 # macro -mmSDMA0_RLC7_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_BASE_LO = 0x03a5 # macro -mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_BASE_HI = 0x03a6 # macro -mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_SIZE = 0x03a7 # macro -mmSDMA0_RLC7_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA0_RLC7_SKIP_CNTL = 0x03a8 # macro -mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_CONTEXT_STATUS = 0x03a9 # macro -mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC7_DOORBELL = 0x03aa # macro -mmSDMA0_RLC7_DOORBELL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_STATUS = 0x03c0 # macro -mmSDMA0_RLC7_STATUS_BASE_IDX = 0 # macro -mmSDMA0_RLC7_DOORBELL_LOG = 0x03c1 # macro -mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA0_RLC7_WATERMARK = 0x03c2 # macro -mmSDMA0_RLC7_WATERMARK_BASE_IDX = 0 # macro -mmSDMA0_RLC7_DOORBELL_OFFSET = 0x03c3 # macro -mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA0_RLC7_CSA_ADDR_LO = 0x03c4 # macro -mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC7_CSA_ADDR_HI = 0x03c5 # macro -mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_IB_SUB_REMAIN = 0x03c7 # macro -mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA0_RLC7_PREEMPT = 0x03c8 # macro -mmSDMA0_RLC7_PREEMPT_BASE_IDX = 0 # macro -mmSDMA0_RLC7_DUMMY_REG = 0x03c9 # macro -mmSDMA0_RLC7_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro -mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro -mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA0_RLC7_RB_AQL_CNTL = 0x03cc # macro -mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro -mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA0 = 0x03d8 # macro -mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA1 = 0x03d9 # macro -mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA2 = 0x03da # macro -mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA3 = 0x03db # macro -mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA4 = 0x03dc # macro -mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA5 = 0x03dd # macro -mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA6 = 0x03de # macro -mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA7 = 0x03df # macro -mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA8 = 0x03e0 # macro -mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA9 = 0x03e1 # macro -mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_DATA10 = 0x03e2 # macro -mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA0_RLC7_MIDCMD_CNTL = 0x03e3 # macro -mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_DEC_START = 0x0600 # macro -mmSDMA1_DEC_START_BASE_IDX = 0 # macro -mmSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro -mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -mmSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro -mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -mmSDMA1_PG_CNTL = 0x0616 # macro -mmSDMA1_PG_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PG_CTX_LO = 0x0617 # macro -mmSDMA1_PG_CTX_LO_BASE_IDX = 0 # macro -mmSDMA1_PG_CTX_HI = 0x0618 # macro -mmSDMA1_PG_CTX_HI_BASE_IDX = 0 # macro -mmSDMA1_PG_CTX_CNTL = 0x0619 # macro -mmSDMA1_PG_CTX_CNTL_BASE_IDX = 0 # macro -mmSDMA1_POWER_CNTL = 0x061a # macro -mmSDMA1_POWER_CNTL_BASE_IDX = 0 # macro -mmSDMA1_CLK_CTRL = 0x061b # macro -mmSDMA1_CLK_CTRL_BASE_IDX = 0 # macro -mmSDMA1_CNTL = 0x061c # macro -mmSDMA1_CNTL_BASE_IDX = 0 # macro -mmSDMA1_CHICKEN_BITS = 0x061d # macro -mmSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro -mmSDMA1_GB_ADDR_CONFIG = 0x061e # macro -mmSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -mmSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro -mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -mmSDMA1_RB_RPTR_FETCH_HI = 0x0620 # macro -mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0621 # macro -mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RB_RPTR_FETCH = 0x0622 # macro -mmSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro -mmSDMA1_IB_OFFSET_FETCH = 0x0623 # macro -mmSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -mmSDMA1_PROGRAM = 0x0624 # macro -mmSDMA1_PROGRAM_BASE_IDX = 0 # macro -mmSDMA1_STATUS_REG = 0x0625 # macro -mmSDMA1_STATUS_REG_BASE_IDX = 0 # macro -mmSDMA1_STATUS1_REG = 0x0626 # macro -mmSDMA1_STATUS1_REG_BASE_IDX = 0 # macro -mmSDMA1_RD_BURST_CNTL = 0x0627 # macro -mmSDMA1_RD_BURST_CNTL_BASE_IDX = 0 # macro -mmSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro -mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -mmSDMA1_UCODE_CHECKSUM = 0x0629 # macro -mmSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro -mmSDMA1_F32_CNTL = 0x062a # macro -mmSDMA1_F32_CNTL_BASE_IDX = 0 # macro -mmSDMA1_FREEZE = 0x062b # macro -mmSDMA1_FREEZE_BASE_IDX = 0 # macro -mmSDMA1_PHASE0_QUANTUM = 0x062c # macro -mmSDMA1_PHASE0_QUANTUM_BASE_IDX = 0 # macro -mmSDMA1_PHASE1_QUANTUM = 0x062d # macro -mmSDMA1_PHASE1_QUANTUM_BASE_IDX = 0 # macro -mmSDMA1_EDC_CONFIG = 0x0632 # macro -mmSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro -mmSDMA1_BA_THRESHOLD = 0x0633 # macro -mmSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro -mmSDMA1_ID = 0x0634 # macro -mmSDMA1_ID_BASE_IDX = 0 # macro -mmSDMA1_VERSION = 0x0635 # macro -mmSDMA1_VERSION_BASE_IDX = 0 # macro -mmSDMA1_EDC_COUNTER = 0x0636 # macro -mmSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro -mmSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro -mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -mmSDMA1_STATUS2_REG = 0x0638 # macro -mmSDMA1_STATUS2_REG_BASE_IDX = 0 # macro -mmSDMA1_ATOMIC_CNTL = 0x0639 # macro -mmSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro -mmSDMA1_ATOMIC_PREOP_LO = 0x063a # macro -mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -mmSDMA1_ATOMIC_PREOP_HI = 0x063b # macro -mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_CNTL = 0x063c # macro -mmSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_WATERMK = 0x063d # macro -mmSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_RD_STATUS = 0x063e # macro -mmSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_WR_STATUS = 0x063f # macro -mmSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_INV0 = 0x0640 # macro -mmSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_INV1 = 0x0641 # macro -mmSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_INV2 = 0x0642 # macro -mmSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_RD_XNACK0 = 0x0643 # macro -mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_RD_XNACK1 = 0x0644 # macro -mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_WR_XNACK0 = 0x0645 # macro -mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_WR_XNACK1 = 0x0646 # macro -mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_TIMEOUT = 0x0647 # macro -mmSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -mmSDMA1_UTCL1_PAGE = 0x0648 # macro -mmSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro -mmSDMA1_RELAX_ORDERING_LUT = 0x064a # macro -mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -mmSDMA1_CHICKEN_BITS_2 = 0x064b # macro -mmSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro -mmSDMA1_STATUS3_REG = 0x064c # macro -mmSDMA1_STATUS3_REG_BASE_IDX = 0 # macro -mmSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro -mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro -mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_PHASE2_QUANTUM = 0x064f # macro -mmSDMA1_PHASE2_QUANTUM_BASE_IDX = 0 # macro -mmSDMA1_ERROR_LOG = 0x0650 # macro -mmSDMA1_ERROR_LOG_BASE_IDX = 0 # macro -mmSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro -mmSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -mmSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro -mmSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -mmSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro -mmSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -mmSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro -mmSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -mmSDMA1_F32_COUNTER = 0x0655 # macro -mmSDMA1_F32_COUNTER_BASE_IDX = 0 # macro -mmSDMA1_CRD_CNTL = 0x065b # macro -mmSDMA1_CRD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_AQL_STATUS = 0x065f # macro -mmSDMA1_AQL_STATUS_BASE_IDX = 0 # macro -mmSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro -mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -mmSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro -mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -mmSDMA1_TLBI_GCR_CNTL = 0x0662 # macro -mmSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -mmSDMA1_TILING_CONFIG = 0x0663 # macro -mmSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro -mmSDMA1_INT_STATUS = 0x0670 # macro -mmSDMA1_INT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_HOLE_ADDR_LO = 0x0672 # macro -mmSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_HOLE_ADDR_HI = 0x0673 # macro -mmSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_CLOCK_GATING_REG = 0x0675 # macro -mmSDMA1_CLOCK_GATING_REG_BASE_IDX = 0 # macro -mmSDMA1_STATUS4_REG = 0x0676 # macro -mmSDMA1_STATUS4_REG_BASE_IDX = 0 # macro -mmSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro -mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -mmSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro -mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -mmSDMA1_TIMESTAMP_CNTL = 0x0679 # macro -mmSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_STATUS5_REG = 0x067a # macro -mmSDMA1_STATUS5_REG_BASE_IDX = 0 # macro -mmSDMA1_QUEUE_RESET_REQ = 0x067b # macro -mmSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_CNTL = 0x0680 # macro -mmSDMA1_GFX_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_BASE = 0x0681 # macro -mmSDMA1_GFX_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_BASE_HI = 0x0682 # macro -mmSDMA1_GFX_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_RPTR = 0x0683 # macro -mmSDMA1_GFX_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_RPTR_HI = 0x0684 # macro -mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_WPTR = 0x0685 # macro -mmSDMA1_GFX_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_WPTR_HI = 0x0686 # macro -mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_WPTR_POLL_CNTL = 0x0687 # macro -mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_RPTR_ADDR_HI = 0x0688 # macro -mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_RPTR_ADDR_LO = 0x0689 # macro -mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_CNTL = 0x068a # macro -mmSDMA1_GFX_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_RPTR = 0x068b # macro -mmSDMA1_GFX_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_OFFSET = 0x068c # macro -mmSDMA1_GFX_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_BASE_LO = 0x068d # macro -mmSDMA1_GFX_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_BASE_HI = 0x068e # macro -mmSDMA1_GFX_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_SIZE = 0x068f # macro -mmSDMA1_GFX_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_GFX_SKIP_CNTL = 0x0690 # macro -mmSDMA1_GFX_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_CONTEXT_STATUS = 0x0691 # macro -mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_GFX_DOORBELL = 0x0692 # macro -mmSDMA1_GFX_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_GFX_CONTEXT_CNTL = 0x0693 # macro -mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_STATUS = 0x06a8 # macro -mmSDMA1_GFX_STATUS_BASE_IDX = 0 # macro -mmSDMA1_GFX_DOORBELL_LOG = 0x06a9 # macro -mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_GFX_WATERMARK = 0x06aa # macro -mmSDMA1_GFX_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_GFX_DOORBELL_OFFSET = 0x06ab # macro -mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_GFX_CSA_ADDR_LO = 0x06ac # macro -mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_GFX_CSA_ADDR_HI = 0x06ad # macro -mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_IB_SUB_REMAIN = 0x06af # macro -mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_GFX_PREEMPT = 0x06b0 # macro -mmSDMA1_GFX_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_GFX_DUMMY_REG = 0x06b1 # macro -mmSDMA1_GFX_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro -mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro -mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_GFX_RB_AQL_CNTL = 0x06b4 # macro -mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_GFX_MINOR_PTR_UPDATE = 0x06b5 # macro -mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA0 = 0x06c0 # macro -mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA1 = 0x06c1 # macro -mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA2 = 0x06c2 # macro -mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA3 = 0x06c3 # macro -mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA4 = 0x06c4 # macro -mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA5 = 0x06c5 # macro -mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA6 = 0x06c6 # macro -mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA7 = 0x06c7 # macro -mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA8 = 0x06c8 # macro -mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA9 = 0x06c9 # macro -mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_DATA10 = 0x06ca # macro -mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_GFX_MIDCMD_CNTL = 0x06cb # macro -mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_CNTL = 0x06d8 # macro -mmSDMA1_PAGE_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_BASE = 0x06d9 # macro -mmSDMA1_PAGE_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_BASE_HI = 0x06da # macro -mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_RPTR = 0x06db # macro -mmSDMA1_PAGE_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_RPTR_HI = 0x06dc # macro -mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_WPTR = 0x06dd # macro -mmSDMA1_PAGE_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_WPTR_HI = 0x06de # macro -mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_WPTR_POLL_CNTL = 0x06df # macro -mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_RPTR_ADDR_HI = 0x06e0 # macro -mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_RPTR_ADDR_LO = 0x06e1 # macro -mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_CNTL = 0x06e2 # macro -mmSDMA1_PAGE_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_RPTR = 0x06e3 # macro -mmSDMA1_PAGE_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_OFFSET = 0x06e4 # macro -mmSDMA1_PAGE_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_BASE_LO = 0x06e5 # macro -mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_BASE_HI = 0x06e6 # macro -mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_SIZE = 0x06e7 # macro -mmSDMA1_PAGE_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_PAGE_SKIP_CNTL = 0x06e8 # macro -mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_CONTEXT_STATUS = 0x06e9 # macro -mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_PAGE_DOORBELL = 0x06ea # macro -mmSDMA1_PAGE_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_STATUS = 0x0700 # macro -mmSDMA1_PAGE_STATUS_BASE_IDX = 0 # macro -mmSDMA1_PAGE_DOORBELL_LOG = 0x0701 # macro -mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_PAGE_WATERMARK = 0x0702 # macro -mmSDMA1_PAGE_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_PAGE_DOORBELL_OFFSET = 0x0703 # macro -mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_PAGE_CSA_ADDR_LO = 0x0704 # macro -mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_PAGE_CSA_ADDR_HI = 0x0705 # macro -mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_IB_SUB_REMAIN = 0x0707 # macro -mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_PAGE_PREEMPT = 0x0708 # macro -mmSDMA1_PAGE_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_PAGE_DUMMY_REG = 0x0709 # macro -mmSDMA1_PAGE_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI = 0x070a # macro -mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO = 0x070b # macro -mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_PAGE_RB_AQL_CNTL = 0x070c # macro -mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MINOR_PTR_UPDATE = 0x070d # macro -mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA0 = 0x0718 # macro -mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA1 = 0x0719 # macro -mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA2 = 0x071a # macro -mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA3 = 0x071b # macro -mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA4 = 0x071c # macro -mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA5 = 0x071d # macro -mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA6 = 0x071e # macro -mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA7 = 0x071f # macro -mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA8 = 0x0720 # macro -mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA9 = 0x0721 # macro -mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_DATA10 = 0x0722 # macro -mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_PAGE_MIDCMD_CNTL = 0x0723 # macro -mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_CNTL = 0x0730 # macro -mmSDMA1_RLC0_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_BASE = 0x0731 # macro -mmSDMA1_RLC0_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_BASE_HI = 0x0732 # macro -mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_RPTR = 0x0733 # macro -mmSDMA1_RLC0_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_RPTR_HI = 0x0734 # macro -mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_WPTR = 0x0735 # macro -mmSDMA1_RLC0_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_WPTR_HI = 0x0736 # macro -mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_CNTL = 0x0737 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_RPTR_ADDR_HI = 0x0738 # macro -mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_RPTR_ADDR_LO = 0x0739 # macro -mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_CNTL = 0x073a # macro -mmSDMA1_RLC0_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_RPTR = 0x073b # macro -mmSDMA1_RLC0_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_OFFSET = 0x073c # macro -mmSDMA1_RLC0_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_BASE_LO = 0x073d # macro -mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_BASE_HI = 0x073e # macro -mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_SIZE = 0x073f # macro -mmSDMA1_RLC0_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC0_SKIP_CNTL = 0x0740 # macro -mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_CONTEXT_STATUS = 0x0741 # macro -mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC0_DOORBELL = 0x0742 # macro -mmSDMA1_RLC0_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_STATUS = 0x0758 # macro -mmSDMA1_RLC0_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC0_DOORBELL_LOG = 0x0759 # macro -mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC0_WATERMARK = 0x075a # macro -mmSDMA1_RLC0_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC0_DOORBELL_OFFSET = 0x075b # macro -mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC0_CSA_ADDR_LO = 0x075c # macro -mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC0_CSA_ADDR_HI = 0x075d # macro -mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_IB_SUB_REMAIN = 0x075f # macro -mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC0_PREEMPT = 0x0760 # macro -mmSDMA1_RLC0_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC0_DUMMY_REG = 0x0761 # macro -mmSDMA1_RLC0_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro -mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC0_RB_AQL_CNTL = 0x0764 # macro -mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MINOR_PTR_UPDATE = 0x0765 # macro -mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA0 = 0x0770 # macro -mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA1 = 0x0771 # macro -mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA2 = 0x0772 # macro -mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA3 = 0x0773 # macro -mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA4 = 0x0774 # macro -mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA5 = 0x0775 # macro -mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA6 = 0x0776 # macro -mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA7 = 0x0777 # macro -mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA8 = 0x0778 # macro -mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA9 = 0x0779 # macro -mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_DATA10 = 0x077a # macro -mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC0_MIDCMD_CNTL = 0x077b # macro -mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_CNTL = 0x0788 # macro -mmSDMA1_RLC1_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_BASE = 0x0789 # macro -mmSDMA1_RLC1_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_BASE_HI = 0x078a # macro -mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_RPTR = 0x078b # macro -mmSDMA1_RLC1_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_RPTR_HI = 0x078c # macro -mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_WPTR = 0x078d # macro -mmSDMA1_RLC1_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_WPTR_HI = 0x078e # macro -mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_WPTR_POLL_CNTL = 0x078f # macro -mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_RPTR_ADDR_HI = 0x0790 # macro -mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_RPTR_ADDR_LO = 0x0791 # macro -mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_CNTL = 0x0792 # macro -mmSDMA1_RLC1_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_RPTR = 0x0793 # macro -mmSDMA1_RLC1_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_OFFSET = 0x0794 # macro -mmSDMA1_RLC1_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_BASE_LO = 0x0795 # macro -mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_BASE_HI = 0x0796 # macro -mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_SIZE = 0x0797 # macro -mmSDMA1_RLC1_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC1_SKIP_CNTL = 0x0798 # macro -mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_CONTEXT_STATUS = 0x0799 # macro -mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC1_DOORBELL = 0x079a # macro -mmSDMA1_RLC1_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_STATUS = 0x07b0 # macro -mmSDMA1_RLC1_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC1_DOORBELL_LOG = 0x07b1 # macro -mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC1_WATERMARK = 0x07b2 # macro -mmSDMA1_RLC1_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC1_DOORBELL_OFFSET = 0x07b3 # macro -mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC1_CSA_ADDR_LO = 0x07b4 # macro -mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC1_CSA_ADDR_HI = 0x07b5 # macro -mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_IB_SUB_REMAIN = 0x07b7 # macro -mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC1_PREEMPT = 0x07b8 # macro -mmSDMA1_RLC1_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC1_DUMMY_REG = 0x07b9 # macro -mmSDMA1_RLC1_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro -mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro -mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC1_RB_AQL_CNTL = 0x07bc # macro -mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MINOR_PTR_UPDATE = 0x07bd # macro -mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA0 = 0x07c8 # macro -mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA1 = 0x07c9 # macro -mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA2 = 0x07ca # macro -mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA3 = 0x07cb # macro -mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA4 = 0x07cc # macro -mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA5 = 0x07cd # macro -mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA6 = 0x07ce # macro -mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA7 = 0x07cf # macro -mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA8 = 0x07d0 # macro -mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA9 = 0x07d1 # macro -mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_DATA10 = 0x07d2 # macro -mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC1_MIDCMD_CNTL = 0x07d3 # macro -mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_CNTL = 0x07e0 # macro -mmSDMA1_RLC2_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_BASE = 0x07e1 # macro -mmSDMA1_RLC2_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_BASE_HI = 0x07e2 # macro -mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_RPTR = 0x07e3 # macro -mmSDMA1_RLC2_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_RPTR_HI = 0x07e4 # macro -mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_WPTR = 0x07e5 # macro -mmSDMA1_RLC2_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_WPTR_HI = 0x07e6 # macro -mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_CNTL = 0x07e7 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_RPTR_ADDR_HI = 0x07e8 # macro -mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_RPTR_ADDR_LO = 0x07e9 # macro -mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_CNTL = 0x07ea # macro -mmSDMA1_RLC2_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_RPTR = 0x07eb # macro -mmSDMA1_RLC2_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_OFFSET = 0x07ec # macro -mmSDMA1_RLC2_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_BASE_LO = 0x07ed # macro -mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_BASE_HI = 0x07ee # macro -mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_SIZE = 0x07ef # macro -mmSDMA1_RLC2_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC2_SKIP_CNTL = 0x07f0 # macro -mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_CONTEXT_STATUS = 0x07f1 # macro -mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC2_DOORBELL = 0x07f2 # macro -mmSDMA1_RLC2_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_STATUS = 0x0808 # macro -mmSDMA1_RLC2_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC2_DOORBELL_LOG = 0x0809 # macro -mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC2_WATERMARK = 0x080a # macro -mmSDMA1_RLC2_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC2_DOORBELL_OFFSET = 0x080b # macro -mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC2_CSA_ADDR_LO = 0x080c # macro -mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC2_CSA_ADDR_HI = 0x080d # macro -mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_IB_SUB_REMAIN = 0x080f # macro -mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC2_PREEMPT = 0x0810 # macro -mmSDMA1_RLC2_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC2_DUMMY_REG = 0x0811 # macro -mmSDMA1_RLC2_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro -mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC2_RB_AQL_CNTL = 0x0814 # macro -mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MINOR_PTR_UPDATE = 0x0815 # macro -mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA0 = 0x0820 # macro -mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA1 = 0x0821 # macro -mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA2 = 0x0822 # macro -mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA3 = 0x0823 # macro -mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA4 = 0x0824 # macro -mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA5 = 0x0825 # macro -mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA6 = 0x0826 # macro -mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA7 = 0x0827 # macro -mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA8 = 0x0828 # macro -mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA9 = 0x0829 # macro -mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_DATA10 = 0x082a # macro -mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC2_MIDCMD_CNTL = 0x082b # macro -mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_CNTL = 0x0838 # macro -mmSDMA1_RLC3_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_BASE = 0x0839 # macro -mmSDMA1_RLC3_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_BASE_HI = 0x083a # macro -mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_RPTR = 0x083b # macro -mmSDMA1_RLC3_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_RPTR_HI = 0x083c # macro -mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_WPTR = 0x083d # macro -mmSDMA1_RLC3_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_WPTR_HI = 0x083e # macro -mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_WPTR_POLL_CNTL = 0x083f # macro -mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_RPTR_ADDR_HI = 0x0840 # macro -mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_RPTR_ADDR_LO = 0x0841 # macro -mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_CNTL = 0x0842 # macro -mmSDMA1_RLC3_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_RPTR = 0x0843 # macro -mmSDMA1_RLC3_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_OFFSET = 0x0844 # macro -mmSDMA1_RLC3_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_BASE_LO = 0x0845 # macro -mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_BASE_HI = 0x0846 # macro -mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_SIZE = 0x0847 # macro -mmSDMA1_RLC3_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC3_SKIP_CNTL = 0x0848 # macro -mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_CONTEXT_STATUS = 0x0849 # macro -mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC3_DOORBELL = 0x084a # macro -mmSDMA1_RLC3_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_STATUS = 0x0860 # macro -mmSDMA1_RLC3_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC3_DOORBELL_LOG = 0x0861 # macro -mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC3_WATERMARK = 0x0862 # macro -mmSDMA1_RLC3_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC3_DOORBELL_OFFSET = 0x0863 # macro -mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC3_CSA_ADDR_LO = 0x0864 # macro -mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC3_CSA_ADDR_HI = 0x0865 # macro -mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_IB_SUB_REMAIN = 0x0867 # macro -mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC3_PREEMPT = 0x0868 # macro -mmSDMA1_RLC3_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC3_DUMMY_REG = 0x0869 # macro -mmSDMA1_RLC3_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI = 0x086a # macro -mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO = 0x086b # macro -mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC3_RB_AQL_CNTL = 0x086c # macro -mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MINOR_PTR_UPDATE = 0x086d # macro -mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA0 = 0x0878 # macro -mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA1 = 0x0879 # macro -mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA2 = 0x087a # macro -mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA3 = 0x087b # macro -mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA4 = 0x087c # macro -mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA5 = 0x087d # macro -mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA6 = 0x087e # macro -mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA7 = 0x087f # macro -mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA8 = 0x0880 # macro -mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA9 = 0x0881 # macro -mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_DATA10 = 0x0882 # macro -mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC3_MIDCMD_CNTL = 0x0883 # macro -mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_CNTL = 0x0890 # macro -mmSDMA1_RLC4_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_BASE = 0x0891 # macro -mmSDMA1_RLC4_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_BASE_HI = 0x0892 # macro -mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_RPTR = 0x0893 # macro -mmSDMA1_RLC4_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_RPTR_HI = 0x0894 # macro -mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_WPTR = 0x0895 # macro -mmSDMA1_RLC4_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_WPTR_HI = 0x0896 # macro -mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_CNTL = 0x0897 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_RPTR_ADDR_HI = 0x0898 # macro -mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_RPTR_ADDR_LO = 0x0899 # macro -mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_CNTL = 0x089a # macro -mmSDMA1_RLC4_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_RPTR = 0x089b # macro -mmSDMA1_RLC4_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_OFFSET = 0x089c # macro -mmSDMA1_RLC4_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_BASE_LO = 0x089d # macro -mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_BASE_HI = 0x089e # macro -mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_SIZE = 0x089f # macro -mmSDMA1_RLC4_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC4_SKIP_CNTL = 0x08a0 # macro -mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_CONTEXT_STATUS = 0x08a1 # macro -mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC4_DOORBELL = 0x08a2 # macro -mmSDMA1_RLC4_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_STATUS = 0x08b8 # macro -mmSDMA1_RLC4_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC4_DOORBELL_LOG = 0x08b9 # macro -mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC4_WATERMARK = 0x08ba # macro -mmSDMA1_RLC4_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC4_DOORBELL_OFFSET = 0x08bb # macro -mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC4_CSA_ADDR_LO = 0x08bc # macro -mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC4_CSA_ADDR_HI = 0x08bd # macro -mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_IB_SUB_REMAIN = 0x08bf # macro -mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC4_PREEMPT = 0x08c0 # macro -mmSDMA1_RLC4_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC4_DUMMY_REG = 0x08c1 # macro -mmSDMA1_RLC4_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro -mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC4_RB_AQL_CNTL = 0x08c4 # macro -mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MINOR_PTR_UPDATE = 0x08c5 # macro -mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA0 = 0x08d0 # macro -mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA1 = 0x08d1 # macro -mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA2 = 0x08d2 # macro -mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA3 = 0x08d3 # macro -mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA4 = 0x08d4 # macro -mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA5 = 0x08d5 # macro -mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA6 = 0x08d6 # macro -mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA7 = 0x08d7 # macro -mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA8 = 0x08d8 # macro -mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA9 = 0x08d9 # macro -mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_DATA10 = 0x08da # macro -mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC4_MIDCMD_CNTL = 0x08db # macro -mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_CNTL = 0x08e8 # macro -mmSDMA1_RLC5_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_BASE = 0x08e9 # macro -mmSDMA1_RLC5_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_BASE_HI = 0x08ea # macro -mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_RPTR = 0x08eb # macro -mmSDMA1_RLC5_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_RPTR_HI = 0x08ec # macro -mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_WPTR = 0x08ed # macro -mmSDMA1_RLC5_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_WPTR_HI = 0x08ee # macro -mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_WPTR_POLL_CNTL = 0x08ef # macro -mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_RPTR_ADDR_HI = 0x08f0 # macro -mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_RPTR_ADDR_LO = 0x08f1 # macro -mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_CNTL = 0x08f2 # macro -mmSDMA1_RLC5_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_RPTR = 0x08f3 # macro -mmSDMA1_RLC5_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_OFFSET = 0x08f4 # macro -mmSDMA1_RLC5_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_BASE_LO = 0x08f5 # macro -mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_BASE_HI = 0x08f6 # macro -mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_SIZE = 0x08f7 # macro -mmSDMA1_RLC5_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC5_SKIP_CNTL = 0x08f8 # macro -mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_CONTEXT_STATUS = 0x08f9 # macro -mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC5_DOORBELL = 0x08fa # macro -mmSDMA1_RLC5_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_STATUS = 0x0910 # macro -mmSDMA1_RLC5_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC5_DOORBELL_LOG = 0x0911 # macro -mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC5_WATERMARK = 0x0912 # macro -mmSDMA1_RLC5_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC5_DOORBELL_OFFSET = 0x0913 # macro -mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC5_CSA_ADDR_LO = 0x0914 # macro -mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC5_CSA_ADDR_HI = 0x0915 # macro -mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_IB_SUB_REMAIN = 0x0917 # macro -mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC5_PREEMPT = 0x0918 # macro -mmSDMA1_RLC5_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC5_DUMMY_REG = 0x0919 # macro -mmSDMA1_RLC5_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI = 0x091a # macro -mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO = 0x091b # macro -mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC5_RB_AQL_CNTL = 0x091c # macro -mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MINOR_PTR_UPDATE = 0x091d # macro -mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA0 = 0x0928 # macro -mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA1 = 0x0929 # macro -mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA2 = 0x092a # macro -mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA3 = 0x092b # macro -mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA4 = 0x092c # macro -mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA5 = 0x092d # macro -mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA6 = 0x092e # macro -mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA7 = 0x092f # macro -mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA8 = 0x0930 # macro -mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA9 = 0x0931 # macro -mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_DATA10 = 0x0932 # macro -mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC5_MIDCMD_CNTL = 0x0933 # macro -mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_CNTL = 0x0940 # macro -mmSDMA1_RLC6_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_BASE = 0x0941 # macro -mmSDMA1_RLC6_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_BASE_HI = 0x0942 # macro -mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_RPTR = 0x0943 # macro -mmSDMA1_RLC6_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_RPTR_HI = 0x0944 # macro -mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_WPTR = 0x0945 # macro -mmSDMA1_RLC6_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_WPTR_HI = 0x0946 # macro -mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_CNTL = 0x0947 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_RPTR_ADDR_HI = 0x0948 # macro -mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_RPTR_ADDR_LO = 0x0949 # macro -mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_CNTL = 0x094a # macro -mmSDMA1_RLC6_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_RPTR = 0x094b # macro -mmSDMA1_RLC6_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_OFFSET = 0x094c # macro -mmSDMA1_RLC6_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_BASE_LO = 0x094d # macro -mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_BASE_HI = 0x094e # macro -mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_SIZE = 0x094f # macro -mmSDMA1_RLC6_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC6_SKIP_CNTL = 0x0950 # macro -mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_CONTEXT_STATUS = 0x0951 # macro -mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC6_DOORBELL = 0x0952 # macro -mmSDMA1_RLC6_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_STATUS = 0x0968 # macro -mmSDMA1_RLC6_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC6_DOORBELL_LOG = 0x0969 # macro -mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC6_WATERMARK = 0x096a # macro -mmSDMA1_RLC6_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC6_DOORBELL_OFFSET = 0x096b # macro -mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC6_CSA_ADDR_LO = 0x096c # macro -mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC6_CSA_ADDR_HI = 0x096d # macro -mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_IB_SUB_REMAIN = 0x096f # macro -mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC6_PREEMPT = 0x0970 # macro -mmSDMA1_RLC6_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC6_DUMMY_REG = 0x0971 # macro -mmSDMA1_RLC6_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0972 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0973 # macro -mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC6_RB_AQL_CNTL = 0x0974 # macro -mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MINOR_PTR_UPDATE = 0x0975 # macro -mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA0 = 0x0980 # macro -mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA1 = 0x0981 # macro -mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA2 = 0x0982 # macro -mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA3 = 0x0983 # macro -mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA4 = 0x0984 # macro -mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA5 = 0x0985 # macro -mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA6 = 0x0986 # macro -mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA7 = 0x0987 # macro -mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA8 = 0x0988 # macro -mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA9 = 0x0989 # macro -mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_DATA10 = 0x098a # macro -mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC6_MIDCMD_CNTL = 0x098b # macro -mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_CNTL = 0x0998 # macro -mmSDMA1_RLC7_RB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_BASE = 0x0999 # macro -mmSDMA1_RLC7_RB_BASE_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_BASE_HI = 0x099a # macro -mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_RPTR = 0x099b # macro -mmSDMA1_RLC7_RB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_RPTR_HI = 0x099c # macro -mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_WPTR = 0x099d # macro -mmSDMA1_RLC7_RB_WPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_WPTR_HI = 0x099e # macro -mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_WPTR_POLL_CNTL = 0x099f # macro -mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_RPTR_ADDR_HI = 0x09a0 # macro -mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_RPTR_ADDR_LO = 0x09a1 # macro -mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_CNTL = 0x09a2 # macro -mmSDMA1_RLC7_IB_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_RPTR = 0x09a3 # macro -mmSDMA1_RLC7_IB_RPTR_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_OFFSET = 0x09a4 # macro -mmSDMA1_RLC7_IB_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_BASE_LO = 0x09a5 # macro -mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_BASE_HI = 0x09a6 # macro -mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_SIZE = 0x09a7 # macro -mmSDMA1_RLC7_IB_SIZE_BASE_IDX = 0 # macro -mmSDMA1_RLC7_SKIP_CNTL = 0x09a8 # macro -mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_CONTEXT_STATUS = 0x09a9 # macro -mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC7_DOORBELL = 0x09aa # macro -mmSDMA1_RLC7_DOORBELL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_STATUS = 0x09c0 # macro -mmSDMA1_RLC7_STATUS_BASE_IDX = 0 # macro -mmSDMA1_RLC7_DOORBELL_LOG = 0x09c1 # macro -mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro -mmSDMA1_RLC7_WATERMARK = 0x09c2 # macro -mmSDMA1_RLC7_WATERMARK_BASE_IDX = 0 # macro -mmSDMA1_RLC7_DOORBELL_OFFSET = 0x09c3 # macro -mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -mmSDMA1_RLC7_CSA_ADDR_LO = 0x09c4 # macro -mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC7_CSA_ADDR_HI = 0x09c5 # macro -mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_IB_SUB_REMAIN = 0x09c7 # macro -mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -mmSDMA1_RLC7_PREEMPT = 0x09c8 # macro -mmSDMA1_RLC7_PREEMPT_BASE_IDX = 0 # macro -mmSDMA1_RLC7_DUMMY_REG = 0x09c9 # macro -mmSDMA1_RLC7_DUMMY_REG_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI = 0x09ca # macro -mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO = 0x09cb # macro -mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmSDMA1_RLC7_RB_AQL_CNTL = 0x09cc # macro -mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MINOR_PTR_UPDATE = 0x09cd # macro -mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA0 = 0x09d8 # macro -mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA1 = 0x09d9 # macro -mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA2 = 0x09da # macro -mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA3 = 0x09db # macro -mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA4 = 0x09dc # macro -mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA5 = 0x09dd # macro -mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA6 = 0x09de # macro -mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA7 = 0x09df # macro -mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA8 = 0x09e0 # macro -mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA9 = 0x09e1 # macro -mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_DATA10 = 0x09e2 # macro -mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro -mmSDMA1_RLC7_MIDCMD_CNTL = 0x09e3 # macro -mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro -mmGRBM_CNTL = 0x0da0 # macro -mmGRBM_CNTL_BASE_IDX = 0 # macro -mmGRBM_SKEW_CNTL = 0x0da1 # macro -mmGRBM_SKEW_CNTL_BASE_IDX = 0 # macro -mmGRBM_STATUS2 = 0x0da2 # macro -mmGRBM_STATUS2_BASE_IDX = 0 # macro -mmGRBM_PWR_CNTL = 0x0da3 # macro -mmGRBM_PWR_CNTL_BASE_IDX = 0 # macro -mmGRBM_STATUS = 0x0da4 # macro -mmGRBM_STATUS_BASE_IDX = 0 # macro -mmGRBM_STATUS_SE0 = 0x0da5 # macro -mmGRBM_STATUS_SE0_BASE_IDX = 0 # macro -mmGRBM_STATUS_SE1 = 0x0da6 # macro -mmGRBM_STATUS_SE1_BASE_IDX = 0 # macro -mmGRBM_STATUS3 = 0x0da7 # macro -mmGRBM_STATUS3_BASE_IDX = 0 # macro -mmGRBM_SOFT_RESET = 0x0da8 # macro -mmGRBM_SOFT_RESET_BASE_IDX = 0 # macro -mmGRBM_GFX_CLKEN_CNTL = 0x0dac # macro -mmGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro -mmGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro -mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro -mmGRBM_STATUS_SE2 = 0x0dae # macro -mmGRBM_STATUS_SE2_BASE_IDX = 0 # macro -mmGRBM_STATUS_SE3 = 0x0daf # macro -mmGRBM_STATUS_SE3_BASE_IDX = 0 # macro -mmGRBM_READ_ERROR = 0x0db6 # macro -mmGRBM_READ_ERROR_BASE_IDX = 0 # macro -mmGRBM_READ_ERROR2 = 0x0db7 # macro -mmGRBM_READ_ERROR2_BASE_IDX = 0 # macro -mmGRBM_INT_CNTL = 0x0db8 # macro -mmGRBM_INT_CNTL_BASE_IDX = 0 # macro -mmGRBM_TRAP_OP = 0x0db9 # macro -mmGRBM_TRAP_OP_BASE_IDX = 0 # macro -mmGRBM_TRAP_ADDR = 0x0dba # macro -mmGRBM_TRAP_ADDR_BASE_IDX = 0 # macro -mmGRBM_TRAP_ADDR_MSK = 0x0dbb # macro -mmGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro -mmGRBM_TRAP_WD = 0x0dbc # macro -mmGRBM_TRAP_WD_BASE_IDX = 0 # macro -mmGRBM_TRAP_WD_MSK = 0x0dbd # macro -mmGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro -mmGRBM_DSM_BYPASS = 0x0dbe # macro -mmGRBM_DSM_BYPASS_BASE_IDX = 0 # macro -mmGRBM_WRITE_ERROR = 0x0dbf # macro -mmGRBM_WRITE_ERROR_BASE_IDX = 0 # macro -mmGRBM_CHIP_REVISION = 0x0dc1 # macro -mmGRBM_CHIP_REVISION_BASE_IDX = 0 # macro -mmGRBM_GFX_CNTL = 0x0dc2 # macro -mmGRBM_GFX_CNTL_BASE_IDX = 0 # macro -mmGRBM_IH_CREDIT = 0x0dc4 # macro -mmGRBM_IH_CREDIT_BASE_IDX = 0 # macro -mmGRBM_PWR_CNTL2 = 0x0dc5 # macro -mmGRBM_PWR_CNTL2_BASE_IDX = 0 # macro -mmGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro -mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro -mmGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro -mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro -mmGRBM_FENCE_RANGE0 = 0x0dca # macro -mmGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro -mmGRBM_FENCE_RANGE1 = 0x0dcb # macro -mmGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro -mmGRBM_NOWHERE = 0x0ddf # macro -mmGRBM_NOWHERE_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG0 = 0x0de0 # macro -mmGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG1 = 0x0de1 # macro -mmGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG2 = 0x0de2 # macro -mmGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG3 = 0x0de3 # macro -mmGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG4 = 0x0de4 # macro -mmGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG5 = 0x0de5 # macro -mmGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG6 = 0x0de6 # macro -mmGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro -mmGRBM_SCRATCH_REG7 = 0x0de7 # macro -mmGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro -mmVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro -mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro -mmCP_CPC_STATUS = 0x0e24 # macro -mmCP_CPC_STATUS_BASE_IDX = 0 # macro -mmCP_CPC_BUSY_STAT = 0x0e25 # macro -mmCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro -mmCP_CPC_STALLED_STAT1 = 0x0e26 # macro -mmCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro -mmCP_CPF_STATUS = 0x0e27 # macro -mmCP_CPF_STATUS_BASE_IDX = 0 # macro -mmCP_CPF_BUSY_STAT = 0x0e28 # macro -mmCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro -mmCP_CPF_STALLED_STAT1 = 0x0e29 # macro -mmCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro -mmCP_CPC_BUSY_STAT2 = 0x0e2a # macro -mmCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro -mmCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro -mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -mmCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro -mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -mmCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro -mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro -mmCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro -mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro -mmCP_CPC_SCRATCH_INDEX = 0x0e30 # macro -mmCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro -mmCP_CPC_SCRATCH_DATA = 0x0e31 # macro -mmCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro -mmCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro -mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -mmCP_CPF_BUSY_STAT2 = 0x0e33 # macro -mmCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro -mmCONFIG_RESERVED_REG0 = 0x0e34 # macro -mmCONFIG_RESERVED_REG0_BASE_IDX = 0 # macro -mmCONFIG_RESERVED_REG1 = 0x0e35 # macro -mmCONFIG_RESERVED_REG1_BASE_IDX = 0 # macro -mmCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro -mmCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro -mmCP_CE_COMPARE_COUNT = 0x0e60 # macro -mmCP_CE_COMPARE_COUNT_BASE_IDX = 0 # macro -mmCP_CE_DE_COUNT = 0x0e61 # macro -mmCP_CE_DE_COUNT_BASE_IDX = 0 # macro -mmCP_DE_CE_COUNT = 0x0e62 # macro -mmCP_DE_CE_COUNT_BASE_IDX = 0 # macro -mmCP_DE_LAST_INVAL_COUNT = 0x0e63 # macro -mmCP_DE_LAST_INVAL_COUNT_BASE_IDX = 0 # macro -mmCP_DE_DE_COUNT = 0x0e64 # macro -mmCP_DE_DE_COUNT_BASE_IDX = 0 # macro -mmCP_STALLED_STAT3 = 0x0f3c # macro -mmCP_STALLED_STAT3_BASE_IDX = 0 # macro -mmCP_STALLED_STAT1 = 0x0f3d # macro -mmCP_STALLED_STAT1_BASE_IDX = 0 # macro -mmCP_STALLED_STAT2 = 0x0f3e # macro -mmCP_STALLED_STAT2_BASE_IDX = 0 # macro -mmCP_BUSY_STAT = 0x0f3f # macro -mmCP_BUSY_STAT_BASE_IDX = 0 # macro -mmCP_STAT = 0x0f40 # macro -mmCP_STAT_BASE_IDX = 0 # macro -mmCP_ME_HEADER_DUMP = 0x0f41 # macro -mmCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro -mmCP_PFP_HEADER_DUMP = 0x0f42 # macro -mmCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro -mmCP_GRBM_FREE_COUNT = 0x0f43 # macro -mmCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -mmCP_CE_HEADER_DUMP = 0x0f44 # macro -mmCP_CE_HEADER_DUMP_BASE_IDX = 0 # macro -mmCP_PFP_INSTR_PNTR = 0x0f45 # macro -mmCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro -mmCP_ME_INSTR_PNTR = 0x0f46 # macro -mmCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro -mmCP_CE_INSTR_PNTR = 0x0f47 # macro -mmCP_CE_INSTR_PNTR_BASE_IDX = 0 # macro -mmCP_MEC1_INSTR_PNTR = 0x0f48 # macro -mmCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro -mmCP_MEC2_INSTR_PNTR = 0x0f49 # macro -mmCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro -mmCP_CSF_STAT = 0x0f54 # macro -mmCP_CSF_STAT_BASE_IDX = 0 # macro -mmCP_MEC_CNTL = 0x0f55 # macro -mmCP_MEC_CNTL_BASE_IDX = 0 # macro -mmCP_ME_CNTL = 0x0f56 # macro -mmCP_ME_CNTL_BASE_IDX = 0 # macro -mmCP_CNTX_STAT = 0x0f58 # macro -mmCP_CNTX_STAT_BASE_IDX = 0 # macro -mmCP_ME_PREEMPTION = 0x0f59 # macro -mmCP_ME_PREEMPTION_BASE_IDX = 0 # macro -mmCP_ROQ_THRESHOLDS = 0x0f5c # macro -mmCP_ROQ_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_MEQ_STQ_THRESHOLD = 0x0f5d # macro -mmCP_MEQ_STQ_THRESHOLD_BASE_IDX = 0 # macro -mmCP_RB2_RPTR = 0x0f5e # macro -mmCP_RB2_RPTR_BASE_IDX = 0 # macro -mmCP_RB1_RPTR = 0x0f5f # macro -mmCP_RB1_RPTR_BASE_IDX = 0 # macro -mmCP_RB0_RPTR = 0x0f60 # macro -mmCP_RB0_RPTR_BASE_IDX = 0 # macro -mmCP_RB_RPTR = 0x0f60 # macro -mmCP_RB_RPTR_BASE_IDX = 0 # macro -mmCP_RB_WPTR_DELAY = 0x0f61 # macro -mmCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro -mmCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro -mmCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmCP_ROQ1_THRESHOLDS = 0x0f75 # macro -mmCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_ROQ2_THRESHOLDS = 0x0f76 # macro -mmCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_STQ_THRESHOLDS = 0x0f77 # macro -mmCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_QUEUE_THRESHOLDS = 0x0f78 # macro -mmCP_QUEUE_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_MEQ_THRESHOLDS = 0x0f79 # macro -mmCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_ROQ_AVAIL = 0x0f7a # macro -mmCP_ROQ_AVAIL_BASE_IDX = 0 # macro -mmCP_STQ_AVAIL = 0x0f7b # macro -mmCP_STQ_AVAIL_BASE_IDX = 0 # macro -mmCP_ROQ2_AVAIL = 0x0f7c # macro -mmCP_ROQ2_AVAIL_BASE_IDX = 0 # macro -mmCP_MEQ_AVAIL = 0x0f7d # macro -mmCP_MEQ_AVAIL_BASE_IDX = 0 # macro -mmCP_CMD_INDEX = 0x0f7e # macro -mmCP_CMD_INDEX_BASE_IDX = 0 # macro -mmCP_CMD_DATA = 0x0f7f # macro -mmCP_CMD_DATA_BASE_IDX = 0 # macro -mmCP_ROQ_RB_STAT = 0x0f80 # macro -mmCP_ROQ_RB_STAT_BASE_IDX = 0 # macro -mmCP_ROQ_IB1_STAT = 0x0f81 # macro -mmCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro -mmCP_ROQ_IB2_STAT = 0x0f82 # macro -mmCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro -mmCP_STQ_STAT = 0x0f83 # macro -mmCP_STQ_STAT_BASE_IDX = 0 # macro -mmCP_STQ_WR_STAT = 0x0f84 # macro -mmCP_STQ_WR_STAT_BASE_IDX = 0 # macro -mmCP_MEQ_STAT = 0x0f85 # macro -mmCP_MEQ_STAT_BASE_IDX = 0 # macro -mmCP_CEQ1_AVAIL = 0x0f86 # macro -mmCP_CEQ1_AVAIL_BASE_IDX = 0 # macro -mmCP_CEQ2_AVAIL = 0x0f87 # macro -mmCP_CEQ2_AVAIL_BASE_IDX = 0 # macro -mmCP_CE_ROQ_RB_STAT = 0x0f88 # macro -mmCP_CE_ROQ_RB_STAT_BASE_IDX = 0 # macro -mmCP_CE_ROQ_IB1_STAT = 0x0f89 # macro -mmCP_CE_ROQ_IB1_STAT_BASE_IDX = 0 # macro -mmCP_CE_ROQ_IB2_STAT = 0x0f8a # macro -mmCP_CE_ROQ_IB2_STAT_BASE_IDX = 0 # macro -mmCP_CE_ROQ_DB_STAT = 0x0f8b # macro -mmCP_CE_ROQ_DB_STAT_BASE_IDX = 0 # macro -mmCP_ROQ3_THRESHOLDS = 0x0f8c # macro -mmCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro -mmCP_ROQ_DB_STAT = 0x0f8d # macro -mmCP_ROQ_DB_STAT_BASE_IDX = 0 # macro -mmCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro -mmCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -mmVGT_CACHE_INVALIDATION = 0x0fc0 # macro -mmVGT_CACHE_INVALIDATION_BASE_IDX = 0 # macro -mmVGT_ESGS_RING_SIZE = 0x0fc1 # macro -mmVGT_ESGS_RING_SIZE_BASE_IDX = 0 # macro -mmVGT_GSVS_RING_SIZE = 0x0fc2 # macro -mmVGT_GSVS_RING_SIZE_BASE_IDX = 0 # macro -mmVGT_TF_RING_SIZE = 0x0fc3 # macro -mmVGT_TF_RING_SIZE_BASE_IDX = 0 # macro -mmVGT_HS_OFFCHIP_PARAM = 0x0fc4 # macro -mmVGT_HS_OFFCHIP_PARAM_BASE_IDX = 0 # macro -mmVGT_TF_MEMORY_BASE = 0x0fc5 # macro -mmVGT_TF_MEMORY_BASE_BASE_IDX = 0 # macro -mmVGT_TF_MEMORY_BASE_HI = 0x0fc6 # macro -mmVGT_TF_MEMORY_BASE_HI_BASE_IDX = 0 # macro -mmVGT_VTX_VECT_EJECT_REG = 0x0fcc # macro -mmVGT_VTX_VECT_EJECT_REG_BASE_IDX = 0 # macro -mmVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro -mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro -mmVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro -mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro -mmVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro -mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro -mmVGT_LAST_COPY_STATE = 0x0fd0 # macro -mmVGT_LAST_COPY_STATE_BASE_IDX = 0 # macro -mmVGT_FIFO_DEPTHS = 0x0fd4 # macro -mmVGT_FIFO_DEPTHS_BASE_IDX = 0 # macro -mmVGT_GS_VERTEX_REUSE = 0x0fd5 # macro -mmVGT_GS_VERTEX_REUSE_BASE_IDX = 0 # macro -mmVGT_MC_LAT_CNTL = 0x0fd6 # macro -mmVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro -mmIA_UTCL1_STATUS_2 = 0x0fd7 # macro -mmIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro -mmWD_CNTL_STATUS = 0x0fdf # macro -mmWD_CNTL_STATUS_BASE_IDX = 0 # macro -mmCC_GC_PRIM_CONFIG = 0x0fe0 # macro -mmCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro -mmGC_USER_PRIM_CONFIG = 0x0fe1 # macro -mmGC_USER_PRIM_CONFIG_BASE_IDX = 0 # macro -mmWD_QOS = 0x0fe2 # macro -mmWD_QOS_BASE_IDX = 0 # macro -mmWD_UTCL1_CNTL = 0x0fe3 # macro -mmWD_UTCL1_CNTL_BASE_IDX = 0 # macro -mmWD_UTCL1_STATUS = 0x0fe4 # macro -mmWD_UTCL1_STATUS_BASE_IDX = 0 # macro -mmGE_PC_CNTL = 0x0fe5 # macro -mmGE_PC_CNTL_BASE_IDX = 0 # macro -mmIA_UTCL1_CNTL = 0x0fe6 # macro -mmIA_UTCL1_CNTL_BASE_IDX = 0 # macro -mmIA_UTCL1_STATUS = 0x0fe7 # macro -mmIA_UTCL1_STATUS_BASE_IDX = 0 # macro -mmCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro -mmCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro -mmGC_USER_SA_UNIT_DISABLE = 0x0fea # macro -mmGC_USER_SA_UNIT_DISABLE_BASE_IDX = 0 # macro -mmVGT_SYS_CONFIG = 0x1003 # macro -mmVGT_SYS_CONFIG_BASE_IDX = 0 # macro -mmGE_PRIV_CONTROL = 0x1004 # macro -mmGE_PRIV_CONTROL_BASE_IDX = 0 # macro -mmGE_STATUS = 0x1005 # macro -mmGE_STATUS_BASE_IDX = 0 # macro -mmVGT_VS_MAX_WAVE_ID = 0x1008 # macro -mmVGT_VS_MAX_WAVE_ID_BASE_IDX = 0 # macro -mmVGT_GS_MAX_WAVE_ID = 0x1009 # macro -mmVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro -mmCC_GC_SHADER_ARRAY_CONFIG_GEN1 = 0x100a # macro -mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX = 0 # macro -mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 = 0x100b # macro -mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX = 0 # macro -mmGFX_PIPE_CONTROL = 0x100d # macro -mmGFX_PIPE_CONTROL_BASE_IDX = 0 # macro -mmCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro -mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro -mmGC_USER_SHADER_ARRAY_CONFIG = 0x1010 # macro -mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro -mmVGT_DMA_PRIMITIVE_TYPE = 0x1011 # macro -mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX = 0 # macro -mmVGT_DMA_CONTROL = 0x1012 # macro -mmVGT_DMA_CONTROL_BASE_IDX = 0 # macro -mmVGT_DMA_LS_HS_CONFIG = 0x1013 # macro -mmVGT_DMA_LS_HS_CONFIG_BASE_IDX = 0 # macro -mmVGT_STRMOUT_DELAY = 0x1015 # macro -mmVGT_STRMOUT_DELAY_BASE_IDX = 0 # macro -mmWD_BUF_RESOURCE_1 = 0x1016 # macro -mmWD_BUF_RESOURCE_1_BASE_IDX = 0 # macro -mmWD_BUF_RESOURCE_2 = 0x1017 # macro -mmWD_BUF_RESOURCE_2_BASE_IDX = 0 # macro -mmPA_CL_CNTL_STATUS = 0x1024 # macro -mmPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro -mmPA_CL_ENHANCE = 0x1025 # macro -mmPA_CL_ENHANCE_BASE_IDX = 0 # macro -mmPA_SU_CNTL_STATUS = 0x1034 # macro -mmPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro -mmPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro -mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro -mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x1060 # macro -mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro -mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x1061 # macro -mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro -mmPA_SC_TRAP_SCREEN_HV_LOCK = 0x1062 # macro -mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro -mmPA_SC_FORCE_EOV_MAX_CNTS = 0x1069 # macro -mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 0 # macro -mmPA_SC_BINNER_EVENT_CNTL_0 = 0x106c # macro -mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 0 # macro -mmPA_SC_BINNER_EVENT_CNTL_1 = 0x106d # macro -mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 0 # macro -mmPA_SC_BINNER_EVENT_CNTL_2 = 0x106e # macro -mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 0 # macro -mmPA_SC_BINNER_EVENT_CNTL_3 = 0x106f # macro -mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 0 # macro -mmPA_SC_BINNER_TIMEOUT_COUNTER = 0x1070 # macro -mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 0 # macro -mmPA_SC_BINNER_PERF_CNTL_0 = 0x1071 # macro -mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 0 # macro -mmPA_SC_BINNER_PERF_CNTL_1 = 0x1072 # macro -mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 0 # macro -mmPA_SC_BINNER_PERF_CNTL_2 = 0x1073 # macro -mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 0 # macro -mmPA_SC_BINNER_PERF_CNTL_3 = 0x1074 # macro -mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 0 # macro -mmPA_SC_ENHANCE_2 = 0x107c # macro -mmPA_SC_ENHANCE_2_BASE_IDX = 0 # macro -mmPA_SC_ENHANCE_INTERNAL = 0x107d # macro -mmPA_SC_ENHANCE_INTERNAL_BASE_IDX = 0 # macro -mmPA_SC_BINNER_CNTL_OVERRIDE = 0x107e # macro -mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 0 # macro -mmPA_SC_PBB_OVERRIDE_FLAG = 0x107f # macro -mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 0 # macro -mmPA_PH_INTERFACE_FIFO_SIZE = 0x1080 # macro -mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 0 # macro -mmPA_PH_ENHANCE = 0x1081 # macro -mmPA_PH_ENHANCE_BASE_IDX = 0 # macro -mmPA_SC_BC_WAVE_BREAK = 0x1084 # macro -mmPA_SC_BC_WAVE_BREAK_BASE_IDX = 0 # macro -mmPA_SC_ENHANCE_3 = 0x1085 # macro -mmPA_SC_ENHANCE_3_BASE_IDX = 0 # macro -mmPA_SC_FIFO_SIZE = 0x1093 # macro -mmPA_SC_FIFO_SIZE_BASE_IDX = 0 # macro -mmPA_SC_IF_FIFO_SIZE = 0x1095 # macro -mmPA_SC_IF_FIFO_SIZE_BASE_IDX = 0 # macro -mmPA_SC_PKR_WAVE_TABLE_CNTL = 0x1098 # macro -mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 0 # macro -mmPA_SIDEBAND_REQUEST_DELAYS = 0x109b # macro -mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX = 0 # macro -mmPA_SC_ENHANCE = 0x109c # macro -mmPA_SC_ENHANCE_BASE_IDX = 0 # macro -mmPA_SC_ENHANCE_1 = 0x109d # macro -mmPA_SC_ENHANCE_1_BASE_IDX = 0 # macro -mmPA_SC_DSM_CNTL = 0x109e # macro -mmPA_SC_DSM_CNTL_BASE_IDX = 0 # macro -mmPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x109f # macro -mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 0 # macro -mmSQ_CONFIG = 0x10a0 # macro -mmSQ_CONFIG_BASE_IDX = 0 # macro -mmSQC_CONFIG = 0x10a1 # macro -mmSQC_CONFIG_BASE_IDX = 0 # macro -mmLDS_CONFIG = 0x10a2 # macro -mmLDS_CONFIG_BASE_IDX = 0 # macro -mmSQ_RANDOM_WAVE_PRI = 0x10a3 # macro -mmSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro -mmSQG_STATUS = 0x10a4 # macro -mmSQG_STATUS_BASE_IDX = 0 # macro -mmSQ_FIFO_SIZES = 0x10a5 # macro -mmSQ_FIFO_SIZES_BASE_IDX = 0 # macro -mmSQ_DSM_CNTL = 0x10a6 # macro -mmSQ_DSM_CNTL_BASE_IDX = 0 # macro -mmSQ_DSM_CNTL2 = 0x10a7 # macro -mmSQ_DSM_CNTL2_BASE_IDX = 0 # macro -mmSQ_RUNTIME_CONFIG = 0x10a8 # macro -mmSQ_RUNTIME_CONFIG_BASE_IDX = 0 # macro -mmSH_MEM_BASES = 0x10aa # macro -mmSH_MEM_BASES_BASE_IDX = 0 # macro -mmSP_CONFIG = 0x10ab # macro -mmSP_CONFIG_BASE_IDX = 0 # macro -mmSQ_ARB_CONFIG = 0x10ac # macro -mmSQ_ARB_CONFIG_BASE_IDX = 0 # macro -mmSH_MEM_CONFIG = 0x10ad # macro -mmSH_MEM_CONFIG_BASE_IDX = 0 # macro -mmSQ_SHADER_TBA_LO = 0x10b2 # macro -mmSQ_SHADER_TBA_LO_BASE_IDX = 0 # macro -mmSQ_SHADER_TBA_HI = 0x10b3 # macro -mmSQ_SHADER_TBA_HI_BASE_IDX = 0 # macro -mmSQ_SHADER_TMA_LO = 0x10b4 # macro -mmSQ_SHADER_TMA_LO_BASE_IDX = 0 # macro -mmSQ_SHADER_TMA_HI = 0x10b5 # macro -mmSQ_SHADER_TMA_HI_BASE_IDX = 0 # macro -mmSQG_UTCL0_CNTL1 = 0x10b7 # macro -mmSQG_UTCL0_CNTL1_BASE_IDX = 0 # macro -mmSQG_UTCL0_CNTL2 = 0x10b8 # macro -mmSQG_UTCL0_CNTL2_BASE_IDX = 0 # macro -mmSQG_UTCL0_STATUS = 0x10b9 # macro -mmSQG_UTCL0_STATUS_BASE_IDX = 0 # macro -mmSQG_CONFIG = 0x10ba # macro -mmSQG_CONFIG_BASE_IDX = 0 # macro -mmCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro -mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro -mmGC_USER_SHADER_RATE_CONFIG = 0x10bd # macro -mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro -mmSQ_INTERRUPT_AUTO_MASK = 0x10be # macro -mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro -mmSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro -mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro -mmSQ_WATCH0_ADDR_H = 0x10d0 # macro -mmSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro -mmSQ_WATCH0_ADDR_L = 0x10d1 # macro -mmSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro -mmSQ_WATCH0_CNTL = 0x10d2 # macro -mmSQ_WATCH0_CNTL_BASE_IDX = 0 # macro -mmSQ_WATCH1_ADDR_H = 0x10d3 # macro -mmSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro -mmSQ_WATCH1_ADDR_L = 0x10d4 # macro -mmSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro -mmSQ_WATCH1_CNTL = 0x10d5 # macro -mmSQ_WATCH1_CNTL_BASE_IDX = 0 # macro -mmSQ_WATCH2_ADDR_H = 0x10d6 # macro -mmSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro -mmSQ_WATCH2_ADDR_L = 0x10d7 # macro -mmSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro -mmSQ_WATCH2_CNTL = 0x10d8 # macro -mmSQ_WATCH2_CNTL_BASE_IDX = 0 # macro -mmSQ_WATCH3_ADDR_H = 0x10d9 # macro -mmSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro -mmSQ_WATCH3_ADDR_L = 0x10da # macro -mmSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro -mmSQ_WATCH3_CNTL = 0x10db # macro -mmSQ_WATCH3_CNTL_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_BUF0_BASE = 0x10e0 # macro -mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_BUF0_SIZE = 0x10e1 # macro -mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_BUF1_BASE = 0x10e2 # macro -mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_BUF1_SIZE = 0x10e3 # macro -mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_WPTR = 0x10e4 # macro -mmSQ_THREAD_TRACE_WPTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_MASK = 0x10e5 # macro -mmSQ_THREAD_TRACE_MASK_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_TOKEN_MASK = 0x10e6 # macro -mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_CTRL = 0x10e7 # macro -mmSQ_THREAD_TRACE_CTRL_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_STATUS = 0x10e8 # macro -mmSQ_THREAD_TRACE_STATUS_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_DROPPED_CNTR = 0x10e9 # macro -mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x10eb # macro -mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x10ec # macro -mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x10ed # macro -mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x10ee # macro -mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 0 # macro -mmSQ_THREAD_TRACE_STATUS2 = 0x10ef # macro -mmSQ_THREAD_TRACE_STATUS2_BASE_IDX = 0 # macro -mmSQ_IND_INDEX = 0x1118 # macro -mmSQ_IND_INDEX_BASE_IDX = 0 # macro -mmSQ_IND_DATA = 0x1119 # macro -mmSQ_IND_DATA_BASE_IDX = 0 # macro -mmSQ_CMD = 0x111b # macro -mmSQ_CMD_BASE_IDX = 0 # macro -mmSQ_TIME_HI = 0x111c # macro -mmSQ_TIME_HI_BASE_IDX = 0 # macro -mmSQ_TIME_LO = 0x111d # macro -mmSQ_TIME_LO_BASE_IDX = 0 # macro -mmSQ_LB_CTR_CTRL = 0x1138 # macro -mmSQ_LB_CTR_CTRL_BASE_IDX = 0 # macro -mmSQ_LB_DATA0 = 0x1139 # macro -mmSQ_LB_DATA0_BASE_IDX = 0 # macro -mmSQ_LB_DATA1 = 0x113a # macro -mmSQ_LB_DATA1_BASE_IDX = 0 # macro -mmSQ_LB_DATA2 = 0x113b # macro -mmSQ_LB_DATA2_BASE_IDX = 0 # macro -mmSQ_LB_DATA3 = 0x113c # macro -mmSQ_LB_DATA3_BASE_IDX = 0 # macro -mmSQ_LB_CTR_SEL0 = 0x113d # macro -mmSQ_LB_CTR_SEL0_BASE_IDX = 0 # macro -mmSQ_LB_CTR_SEL1 = 0x113e # macro -mmSQ_LB_CTR_SEL1_BASE_IDX = 0 # macro -mmSQ_EDC_CNT = 0x1146 # macro -mmSQ_EDC_CNT_BASE_IDX = 0 # macro -mmSQ_EDC_FUE_CNTL = 0x1147 # macro -mmSQ_EDC_FUE_CNTL_BASE_IDX = 0 # macro -mmSQ_WREXEC_EXEC_HI = 0x1151 # macro -mmSQ_WREXEC_EXEC_HI_BASE_IDX = 0 # macro -mmSQ_WREXEC_EXEC_LO = 0x1151 # macro -mmSQ_WREXEC_EXEC_LO_BASE_IDX = 0 # macro -mmSQC_ICACHE_UTCL0_CNTL1 = 0x1173 # macro -mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro -mmSQC_ICACHE_UTCL0_CNTL2 = 0x1174 # macro -mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro -mmSQC_DCACHE_UTCL0_CNTL1 = 0x1175 # macro -mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro -mmSQC_DCACHE_UTCL0_CNTL2 = 0x1176 # macro -mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro -mmSQC_ICACHE_UTCL0_STATUS = 0x1177 # macro -mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX = 0 # macro -mmSQC_DCACHE_UTCL0_STATUS = 0x1178 # macro -mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX = 0 # macro -mmSX_DEBUG_1 = 0x11b8 # macro -mmSX_DEBUG_1_BASE_IDX = 0 # macro -mmSPI_PS_MAX_WAVE_ID = 0x11da # macro -mmSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro -mmSPI_START_PHASE = 0x11db # macro -mmSPI_START_PHASE_BASE_IDX = 0 # macro -mmSPI_GFX_CNTL = 0x11dc # macro -mmSPI_GFX_CNTL_BASE_IDX = 0 # macro -mmSPI_DSM_CNTL = 0x11e3 # macro -mmSPI_DSM_CNTL_BASE_IDX = 0 # macro -mmSPI_DSM_CNTL2 = 0x11e4 # macro -mmSPI_DSM_CNTL2_BASE_IDX = 0 # macro -mmSPI_EDC_CNT = 0x11e5 # macro -mmSPI_EDC_CNT_BASE_IDX = 0 # macro -mmSPI_USER_ACCUM_VMID_CNTL = 0x11eb # macro -mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro -mmSPI_CONFIG_CNTL = 0x11ec # macro -mmSPI_CONFIG_CNTL_BASE_IDX = 0 # macro -mmSPI_WAVE_LIMIT_CNTL = 0x11ed # macro -mmSPI_WAVE_LIMIT_CNTL_BASE_IDX = 0 # macro -mmSPI_CONFIG_CNTL_2 = 0x11ee # macro -mmSPI_CONFIG_CNTL_2_BASE_IDX = 0 # macro -mmSPI_CONFIG_CNTL_1 = 0x11ef # macro -mmSPI_CONFIG_CNTL_1_BASE_IDX = 0 # macro -mmSPI_CONFIG_PS_CU_EN = 0x11f2 # macro -mmSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_CNTL = 0x124a # macro -mmSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro -mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro -mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro -mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro -mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro -mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro -mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro -mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_1 = 0x1256 # macro -mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro -mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro -mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro -mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro -mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_8 = 0x125d # macro -mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro -mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro -mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro -mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro -mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro -mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro -mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro -mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro -mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro -mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro -mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro -mmSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro -mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro -mmSPI_LB_CTR_CTRL = 0x1274 # macro -mmSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro -mmSPI_LB_WGP_MASK = 0x1275 # macro -mmSPI_LB_WGP_MASK_BASE_IDX = 0 # macro -mmSPI_LB_DATA_REG = 0x1276 # macro -mmSPI_LB_DATA_REG_BASE_IDX = 0 # macro -mmSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro -mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro -mmSPI_GDS_CREDITS = 0x1278 # macro -mmSPI_GDS_CREDITS_BASE_IDX = 0 # macro -mmSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro -mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro -mmSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro -mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro -mmSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro -mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro -mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro -mmSPI_LB_DATA_WAVES = 0x1284 # macro -mmSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro -mmSPI_LB_DATA_PERWGP_WAVE_HSGS = 0x1285 # macro -mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX = 0 # macro -mmSPI_LB_DATA_PERWGP_WAVE_VSPS = 0x1286 # macro -mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX = 0 # macro -mmSPI_LB_DATA_PERWGP_WAVE_CS = 0x1287 # macro -mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX = 0 # macro -mmSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro -mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -mmSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro -mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -mmSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro -mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -mmSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro -mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -mmSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro -mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -mmSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro -mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -mmSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro -mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -mmSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro -mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -mmSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro -mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -mmSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro -mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -mmTD_STATUS = 0x12c6 # macro -mmTD_STATUS_BASE_IDX = 0 # macro -mmTD_DSM_CNTL = 0x12cf # macro -mmTD_DSM_CNTL_BASE_IDX = 0 # macro -mmTD_DSM_CNTL2 = 0x12d0 # macro -mmTD_DSM_CNTL2_BASE_IDX = 0 # macro -mmTD_SCRATCH = 0x12d3 # macro -mmTD_SCRATCH_BASE_IDX = 0 # macro -mmTA_CNTL = 0x12e1 # macro -mmTA_CNTL_BASE_IDX = 0 # macro -mmTA_RESERVED_010C = 0x12e3 # macro -mmTA_RESERVED_010C_BASE_IDX = 0 # macro -mmTA_STATUS = 0x12e8 # macro -mmTA_STATUS_BASE_IDX = 0 # macro -mmTA_SCRATCH = 0x1304 # macro -mmTA_SCRATCH_BASE_IDX = 0 # macro -mmGDS_CONFIG = 0x1360 # macro -mmGDS_CONFIG_BASE_IDX = 0 # macro -mmGDS_CNTL_STATUS = 0x1361 # macro -mmGDS_CNTL_STATUS_BASE_IDX = 0 # macro -mmGDS_ENHANCE = 0x1362 # macro -mmGDS_ENHANCE_BASE_IDX = 0 # macro -mmGDS_PROTECTION_FAULT = 0x1363 # macro -mmGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro -mmGDS_VM_PROTECTION_FAULT = 0x1364 # macro -mmGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro -mmGDS_EDC_CNT = 0x1365 # macro -mmGDS_EDC_CNT_BASE_IDX = 0 # macro -mmGDS_EDC_GRBM_CNT = 0x1366 # macro -mmGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro -mmGDS_EDC_OA_DED = 0x1367 # macro -mmGDS_EDC_OA_DED_BASE_IDX = 0 # macro -mmGDS_DSM_CNTL = 0x136a # macro -mmGDS_DSM_CNTL_BASE_IDX = 0 # macro -mmGDS_EDC_OA_PHY_CNT = 0x136b # macro -mmGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro -mmGDS_EDC_OA_PIPE_CNT = 0x136c # macro -mmGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro -mmGDS_DSM_CNTL2 = 0x136d # macro -mmGDS_DSM_CNTL2_BASE_IDX = 0 # macro -mmGDS_WD_GDS_CSB = 0x136e # macro -mmGDS_WD_GDS_CSB_BASE_IDX = 0 # macro -mmDB_DEBUG = 0x13ac # macro -mmDB_DEBUG_BASE_IDX = 0 # macro -mmDB_DEBUG2 = 0x13ad # macro -mmDB_DEBUG2_BASE_IDX = 0 # macro -mmDB_DEBUG3 = 0x13ae # macro -mmDB_DEBUG3_BASE_IDX = 0 # macro -mmDB_DEBUG4 = 0x13af # macro -mmDB_DEBUG4_BASE_IDX = 0 # macro -mmDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro -mmDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -mmDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro -mmDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -mmDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro -mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -mmDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro -mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -mmDB_CREDIT_LIMIT = 0x13b4 # macro -mmDB_CREDIT_LIMIT_BASE_IDX = 0 # macro -mmDB_WATERMARKS = 0x13b5 # macro -mmDB_WATERMARKS_BASE_IDX = 0 # macro -mmDB_SUBTILE_CONTROL = 0x13b6 # macro -mmDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro -mmDB_FREE_CACHELINES = 0x13b7 # macro -mmDB_FREE_CACHELINES_BASE_IDX = 0 # macro -mmDB_FIFO_DEPTH1 = 0x13b8 # macro -mmDB_FIFO_DEPTH1_BASE_IDX = 0 # macro -mmDB_FIFO_DEPTH2 = 0x13b9 # macro -mmDB_FIFO_DEPTH2_BASE_IDX = 0 # macro -mmDB_LAST_OF_BURST_CONFIG = 0x13ba # macro -mmDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro -mmDB_RING_CONTROL = 0x13bb # macro -mmDB_RING_CONTROL_BASE_IDX = 0 # macro -mmDB_MEM_ARB_WATERMARKS = 0x13bc # macro -mmDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro -mmDB_FIFO_DEPTH3 = 0x13bd # macro -mmDB_FIFO_DEPTH3_BASE_IDX = 0 # macro -mmDB_RMI_BC_GL2_CACHE_CONTROL = 0x13be # macro -mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro -mmDB_EXCEPTION_CONTROL = 0x13bf # macro -mmDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro -mmDB_DFSM_CONFIG = 0x13d0 # macro -mmDB_DFSM_CONFIG_BASE_IDX = 0 # macro -mmDB_DEBUG5 = 0x13d1 # macro -mmDB_DEBUG5_BASE_IDX = 0 # macro -mmDB_DFSM_TILES_IN_FLIGHT = 0x13d2 # macro -mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX = 0 # macro -mmDB_DFSM_PRIMS_IN_FLIGHT = 0x13d3 # macro -mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX = 0 # macro -mmDB_DFSM_WATCHDOG = 0x13d4 # macro -mmDB_DFSM_WATCHDOG_BASE_IDX = 0 # macro -mmDB_DFSM_FLUSH_ENABLE = 0x13d5 # macro -mmDB_DFSM_FLUSH_ENABLE_BASE_IDX = 0 # macro -mmDB_DFSM_FLUSH_AUX_EVENT = 0x13d6 # macro -mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX = 0 # macro -mmDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro -mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro -mmDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro -mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro -mmCC_RB_REDUNDANCY = 0x13dc # macro -mmCC_RB_REDUNDANCY_BASE_IDX = 0 # macro -mmCC_RB_BACKEND_DISABLE = 0x13dd # macro -mmCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro -mmGB_ADDR_CONFIG = 0x13de # macro -mmGB_ADDR_CONFIG_BASE_IDX = 0 # macro -mmGB_BACKEND_MAP = 0x13df # macro -mmGB_BACKEND_MAP_BASE_IDX = 0 # macro -mmGB_GPU_ID = 0x13e0 # macro -mmGB_GPU_ID_BASE_IDX = 0 # macro -mmCC_RB_DAISY_CHAIN = 0x13e1 # macro -mmCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro -mmGB_ADDR_CONFIG_READ = 0x13e2 # macro -mmGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -mmCB_HW_CONTROL_4 = 0x1422 # macro -mmCB_HW_CONTROL_4_BASE_IDX = 0 # macro -mmCB_HW_CONTROL_3 = 0x1423 # macro -mmCB_HW_CONTROL_3_BASE_IDX = 0 # macro -mmCB_HW_CONTROL = 0x1424 # macro -mmCB_HW_CONTROL_BASE_IDX = 0 # macro -mmCB_HW_CONTROL_1 = 0x1425 # macro -mmCB_HW_CONTROL_1_BASE_IDX = 0 # macro -mmCB_HW_CONTROL_2 = 0x1426 # macro -mmCB_HW_CONTROL_2_BASE_IDX = 0 # macro -mmCB_DCC_CONFIG = 0x1427 # macro -mmCB_DCC_CONFIG_BASE_IDX = 0 # macro -mmCB_HW_MEM_ARBITER_RD = 0x1428 # macro -mmCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro -mmCB_HW_MEM_ARBITER_WR = 0x1429 # macro -mmCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro -mmCB_RMI_BC_GL2_CACHE_CONTROL = 0x142a # macro -mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro -mmCB_STUTTER_CONTROL_CMASK_RDLAT = 0x142b # macro -mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX = 0 # macro -mmCB_STUTTER_CONTROL_FMASK_RDLAT = 0x142c # macro -mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX = 0 # macro -mmCB_STUTTER_CONTROL_COLOR_RDLAT = 0x142d # macro -mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX = 0 # macro -mmCB_CACHE_EVICT_POINTS = 0x142e # macro -mmCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro -mmGC_USER_RB_REDUNDANCY = 0x147e # macro -mmGC_USER_RB_REDUNDANCY_BASE_IDX = 0 # macro -mmGC_USER_RB_BACKEND_DISABLE = 0x147f # macro -mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro -mmGCEA_MISC = 0x14a2 # macro -mmGCEA_MISC_BASE_IDX = 0 # macro -mmGCEA_LATENCY_SAMPLING = 0x14a3 # macro -mmGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTL = 0x14b4 # macro -mmGCEA_DSM_CNTL_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTLA = 0x14b5 # macro -mmGCEA_DSM_CNTLA_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTLB = 0x14b6 # macro -mmGCEA_DSM_CNTLB_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTL2 = 0x14b7 # macro -mmGCEA_DSM_CNTL2_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTL2A = 0x14b8 # macro -mmGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro -mmGCEA_DSM_CNTL2B = 0x14b9 # macro -mmGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro -mmGCEA_GL2C_XBR_CREDITS = 0x14ba # macro -mmGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro -mmGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro -mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro -mmGCEA_PROBE_CNTL = 0x14bc # macro -mmGCEA_PROBE_CNTL_BASE_IDX = 0 # macro -mmGCEA_PROBE_MAP = 0x14bd # macro -mmGCEA_PROBE_MAP_BASE_IDX = 0 # macro -mmGCEA_ERR_STATUS = 0x14be # macro -mmGCEA_ERR_STATUS_BASE_IDX = 0 # macro -mmGCEA_MISC2 = 0x14bf # macro -mmGCEA_MISC2_BASE_IDX = 0 # macro -mmSPI_PQEV_CTRL = 0x14c0 # macro -mmSPI_PQEV_CTRL_BASE_IDX = 0 # macro -mmSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro -mmSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro -mmGCEA_RRET_MEM_RESERVE = 0x1518 # macro -mmGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro -mmRMI_GENERAL_CNTL = 0x1520 # macro -mmRMI_GENERAL_CNTL_BASE_IDX = 0 # macro -mmRMI_GENERAL_CNTL1 = 0x1521 # macro -mmRMI_GENERAL_CNTL1_BASE_IDX = 0 # macro -mmRMI_GENERAL_STATUS = 0x1522 # macro -mmRMI_GENERAL_STATUS_BASE_IDX = 0 # macro -mmRMI_SUBBLOCK_STATUS0 = 0x1523 # macro -mmRMI_SUBBLOCK_STATUS0_BASE_IDX = 0 # macro -mmRMI_SUBBLOCK_STATUS1 = 0x1524 # macro -mmRMI_SUBBLOCK_STATUS1_BASE_IDX = 0 # macro -mmRMI_SUBBLOCK_STATUS2 = 0x1525 # macro -mmRMI_SUBBLOCK_STATUS2_BASE_IDX = 0 # macro -mmRMI_SUBBLOCK_STATUS3 = 0x1526 # macro -mmRMI_SUBBLOCK_STATUS3_BASE_IDX = 0 # macro -mmRMI_XBAR_CONFIG = 0x1527 # macro -mmRMI_XBAR_CONFIG_BASE_IDX = 0 # macro -mmRMI_PROBE_POP_LOGIC_CNTL = 0x1528 # macro -mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 0 # macro -mmRMI_UTC_XNACK_N_MISC_CNTL = 0x1529 # macro -mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 0 # macro -mmRMI_DEMUX_CNTL = 0x152a # macro -mmRMI_DEMUX_CNTL_BASE_IDX = 0 # macro -mmRMI_UTCL1_CNTL1 = 0x152b # macro -mmRMI_UTCL1_CNTL1_BASE_IDX = 0 # macro -mmRMI_UTCL1_CNTL2 = 0x152c # macro -mmRMI_UTCL1_CNTL2_BASE_IDX = 0 # macro -mmRMI_UTC_UNIT_CONFIG = 0x152d # macro -mmRMI_UTC_UNIT_CONFIG_BASE_IDX = 0 # macro -mmRMI_TCIW_FORMATTER0_CNTL = 0x152e # macro -mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 0 # macro -mmRMI_TCIW_FORMATTER1_CNTL = 0x152f # macro -mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 0 # macro -mmRMI_SCOREBOARD_CNTL = 0x1530 # macro -mmRMI_SCOREBOARD_CNTL_BASE_IDX = 0 # macro -mmRMI_SCOREBOARD_STATUS0 = 0x1531 # macro -mmRMI_SCOREBOARD_STATUS0_BASE_IDX = 0 # macro -mmRMI_SCOREBOARD_STATUS1 = 0x1532 # macro -mmRMI_SCOREBOARD_STATUS1_BASE_IDX = 0 # macro -mmRMI_SCOREBOARD_STATUS2 = 0x1533 # macro -mmRMI_SCOREBOARD_STATUS2_BASE_IDX = 0 # macro -mmRMI_XBAR_ARBITER_CONFIG = 0x1534 # macro -mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 0 # macro -mmRMI_XBAR_ARBITER_CONFIG_1 = 0x1535 # macro -mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 0 # macro -mmRMI_CLOCK_CNTRL = 0x1536 # macro -mmRMI_CLOCK_CNTRL_BASE_IDX = 0 # macro -mmRMI_UTCL1_STATUS = 0x1537 # macro -mmRMI_UTCL1_STATUS_BASE_IDX = 0 # macro -mmRMI_RB_GLX_CID_MAP = 0x1538 # macro -mmRMI_RB_GLX_CID_MAP_BASE_IDX = 0 # macro -mmRMI_SPARE = 0x153f # macro -mmRMI_SPARE_BASE_IDX = 0 # macro -mmRMI_SPARE_1 = 0x1540 # macro -mmRMI_SPARE_1_BASE_IDX = 0 # macro -mmRMI_SPARE_2 = 0x1541 # macro -mmRMI_SPARE_2_BASE_IDX = 0 # macro -mmCC_RMI_REDUNDANCY = 0x1542 # macro -mmCC_RMI_REDUNDANCY_BASE_IDX = 0 # macro -mmGC_USER_RMI_REDUNDANCY = 0x1543 # macro -mmGC_USER_RMI_REDUNDANCY_BASE_IDX = 0 # macro -mmGCR_GENERAL_CNTL = 0x1580 # macro -mmGCR_GENERAL_CNTL_BASE_IDX = 0 # macro -mmGCR_CMD_STATUS = 0x1582 # macro -mmGCR_CMD_STATUS_BASE_IDX = 0 # macro -mmGCR_SPARE = 0x1583 # macro -mmGCR_SPARE_BASE_IDX = 0 # macro -mmPMM_GENERAL_CNTL = 0x1585 # macro -mmPMM_GENERAL_CNTL_BASE_IDX = 0 # macro -mmGCR_PIO_CNTL = 0x1586 # macro -mmGCR_PIO_CNTL_BASE_IDX = 0 # macro -mmGCR_PIO_DATA = 0x1587 # macro -mmGCR_PIO_DATA_BASE_IDX = 0 # macro -mmUTCL1_CTRL = 0x1588 # macro -mmUTCL1_CTRL_BASE_IDX = 0 # macro -mmUTCL1_ALOG = 0x1589 # macro -mmUTCL1_ALOG_BASE_IDX = 0 # macro -mmUTCL1_UTCL0_INVREQ_DISABLE = 0x158a # macro -mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 0 # macro -mmGCRD_SA_TARGETS_DISABLE = 0x158b # macro -mmGCRD_SA_TARGETS_DISABLE_BASE_IDX = 0 # macro -mmUTCL1_STATUS = 0x158c # macro -mmUTCL1_STATUS_BASE_IDX = 0 # macro -mmGCVM_L2_CNTL = 0x15bc # macro -mmGCVM_L2_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_CNTL2 = 0x15bd # macro -mmGCVM_L2_CNTL2_BASE_IDX = 0 # macro -mmGCVM_L2_CNTL3 = 0x15be # macro -mmGCVM_L2_CNTL3_BASE_IDX = 0 # macro -mmGCVM_L2_STATUS = 0x15bf # macro -mmGCVM_L2_STATUS_BASE_IDX = 0 # macro -mmGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro -mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro -mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro -mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro -mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_CNTL = 0x15c3 # macro -mmGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro -mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro -mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro -mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro -mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro -mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro -mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro -mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro -mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro -mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_DEBUG = 0x15cd # macro -mmGCVM_DEBUG_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro -mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro -mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro -mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro -mmGCVM_L2_CNTL4 = 0x15d4 # macro -mmGCVM_L2_CNTL4_BASE_IDX = 0 # macro -mmGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro -mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro -mmGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro -mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro -mmGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro -mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro -mmGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro -mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_IH_LOG_CNTL = 0x15d9 # macro -mmGCVM_L2_IH_LOG_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_CNTL5 = 0x15dc # macro -mmGCVM_L2_CNTL5_BASE_IDX = 0 # macro -mmGCVM_L2_GCR_CNTL = 0x15dd # macro -mmGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro -mmGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15de # macro -mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro -mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15df # macro -mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -mmGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15e0 # macro -mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro -mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15e1 # macro -mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -mmGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e3 # macro -mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro -mmGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e4 # macro -mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_CNTL = 0x15fc # macro -mmGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_CNTL = 0x15fd # macro -mmGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_CNTL = 0x15fe # macro -mmGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_CNTL = 0x15ff # macro -mmGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_CNTL = 0x1600 # macro -mmGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_CNTL = 0x1601 # macro -mmGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_CNTL = 0x1602 # macro -mmGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_CNTL = 0x1603 # macro -mmGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_CNTL = 0x1604 # macro -mmGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_CNTL = 0x1605 # macro -mmGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_CNTL = 0x1606 # macro -mmGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_CNTL = 0x1607 # macro -mmGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_CNTL = 0x1608 # macro -mmGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_CNTL = 0x1609 # macro -mmGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_CNTL = 0x160a # macro -mmGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_CNTL = 0x160b # macro -mmGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro -mmGCVM_CONTEXTS_DISABLE = 0x160c # macro -mmGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG0_SEM = 0x160d # macro -mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG1_SEM = 0x160e # macro -mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG2_SEM = 0x160f # macro -mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG3_SEM = 0x1610 # macro -mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG4_SEM = 0x1611 # macro -mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG5_SEM = 0x1612 # macro -mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG6_SEM = 0x1613 # macro -mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG7_SEM = 0x1614 # macro -mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG8_SEM = 0x1615 # macro -mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG9_SEM = 0x1616 # macro -mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG10_SEM = 0x1617 # macro -mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG11_SEM = 0x1618 # macro -mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG12_SEM = 0x1619 # macro -mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG13_SEM = 0x161a # macro -mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG14_SEM = 0x161b # macro -mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG15_SEM = 0x161c # macro -mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG16_SEM = 0x161d # macro -mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG17_SEM = 0x161e # macro -mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG0_REQ = 0x161f # macro -mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG1_REQ = 0x1620 # macro -mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG2_REQ = 0x1621 # macro -mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG3_REQ = 0x1622 # macro -mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG4_REQ = 0x1623 # macro -mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG5_REQ = 0x1624 # macro -mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG6_REQ = 0x1625 # macro -mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG7_REQ = 0x1626 # macro -mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG8_REQ = 0x1627 # macro -mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG9_REQ = 0x1628 # macro -mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG10_REQ = 0x1629 # macro -mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG11_REQ = 0x162a # macro -mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG12_REQ = 0x162b # macro -mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG13_REQ = 0x162c # macro -mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG14_REQ = 0x162d # macro -mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG15_REQ = 0x162e # macro -mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG16_REQ = 0x162f # macro -mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG17_REQ = 0x1630 # macro -mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG0_ACK = 0x1631 # macro -mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG1_ACK = 0x1632 # macro -mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG2_ACK = 0x1633 # macro -mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG3_ACK = 0x1634 # macro -mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG4_ACK = 0x1635 # macro -mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG5_ACK = 0x1636 # macro -mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG6_ACK = 0x1637 # macro -mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG7_ACK = 0x1638 # macro -mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG8_ACK = 0x1639 # macro -mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG9_ACK = 0x163a # macro -mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG10_ACK = 0x163b # macro -mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG11_ACK = 0x163c # macro -mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG12_ACK = 0x163d # macro -mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG13_ACK = 0x163e # macro -mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG14_ACK = 0x163f # macro -mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG15_ACK = 0x1640 # macro -mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG16_ACK = 0x1641 # macro -mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG17_ACK = 0x1642 # macro -mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x1643 # macro -mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x1644 # macro -mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x1645 # macro -mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x1646 # macro -mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x1647 # macro -mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x1648 # macro -mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x1649 # macro -mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x164a # macro -mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x164b # macro -mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x164c # macro -mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x164d # macro -mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x164e # macro -mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x164f # macro -mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x1650 # macro -mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x1651 # macro -mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x1652 # macro -mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x1653 # macro -mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x1654 # macro -mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x1655 # macro -mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x1656 # macro -mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x1657 # macro -mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x1658 # macro -mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x1659 # macro -mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x165a # macro -mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x165b # macro -mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x165c # macro -mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x165d # macro -mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x165e # macro -mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x165f # macro -mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x1660 # macro -mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x1661 # macro -mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x1662 # macro -mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x1663 # macro -mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x1664 # macro -mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x1665 # macro -mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x1666 # macro -mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x1667 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x1668 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x1669 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x166a # macro -mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x166b # macro -mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x166c # macro -mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x166d # macro -mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x166e # macro -mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x166f # macro -mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x1670 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x1671 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x1672 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x1673 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1674 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1675 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1676 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1677 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1678 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1679 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x167a # macro -mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x167b # macro -mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x167c # macro -mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x167d # macro -mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x167e # macro -mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x167f # macro -mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x1680 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x1681 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x1682 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x1683 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1684 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1685 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1686 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1687 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1688 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1689 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x168a # macro -mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x168b # macro -mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x168c # macro -mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x168d # macro -mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x168e # macro -mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x168f # macro -mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x1690 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x1691 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x1692 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x1693 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1694 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1695 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1696 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1697 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1698 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1699 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x169a # macro -mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x169b # macro -mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x169c # macro -mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x169d # macro -mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x169e # macro -mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x169f # macro -mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x16a0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x16a1 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x16a2 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x16a3 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x16a4 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x16a5 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x16a6 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x16a7 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x16a8 # macro -mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x16a9 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x16aa # macro -mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x16ab # macro -mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x16ac # macro -mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x16ad # macro -mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x16ae # macro -mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x16af # macro -mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x16b0 # macro -mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x16b1 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x16b2 # macro -mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x16b3 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x16b4 # macro -mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x16b5 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x16b6 # macro -mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x16b7 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x16b8 # macro -mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x16b9 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x16ba # macro -mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x16bb # macro -mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x16bc # macro -mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x16bd # macro -mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x16be # macro -mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x16bf # macro -mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x16c0 # macro -mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x16c1 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x16c2 # macro -mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x16c3 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x16c4 # macro -mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x16c5 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x16c6 # macro -mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c7 # macro -mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c8 # macro -mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c9 # macro -mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ca # macro -mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cb # macro -mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cc # macro -mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cd # macro -mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ce # macro -mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cf # macro -mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d0 # macro -mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d1 # macro -mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d2 # macro -mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d3 # macro -mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d4 # macro -mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d5 # macro -mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d6 # macro -mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d7 # macro -mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -mmGCMC_VM_NB_MMIOBASE = 0x16e0 # macro -mmGCMC_VM_NB_MMIOBASE_BASE_IDX = 0 # macro -mmGCMC_VM_NB_MMIOLIMIT = 0x16e1 # macro -mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX = 0 # macro -mmGCMC_VM_NB_PCI_CTRL = 0x16e2 # macro -mmGCMC_VM_NB_PCI_CTRL_BASE_IDX = 0 # macro -mmGCMC_VM_NB_PCI_ARB = 0x16e3 # macro -mmGCMC_VM_NB_PCI_ARB_BASE_IDX = 0 # macro -mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x16e4 # macro -mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro -mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x16e5 # macro -mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x16e6 # macro -mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -mmGCMC_VM_FB_OFFSET = 0x16e7 # macro -mmGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro -mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x16e8 # macro -mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro -mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x16e9 # macro -mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro -mmGCMC_VM_STEERING = 0x16ea # macro -mmGCMC_VM_STEERING_BASE_IDX = 0 # macro -mmGCMC_SHARED_VIRT_RESET_REQ = 0x16eb # macro -mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX = 0 # macro -mmGCMC_MEM_POWER_LS = 0x16ec # macro -mmGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro -mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x16ed # macro -mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro -mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x16ee # macro -mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro -mmGCMC_VM_APT_CNTL = 0x16ef # macro -mmGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL = 0x16f0 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_START = 0x16f1 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX = 0 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_END = 0x16f2 # macro -mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX = 0 # macro -mmGCMC_SHARED_ACTIVE_FCN_ID = 0x16f4 # macro -mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX = 0 # macro -mmGCMC_SHARED_VIRT_RESET_REQ2 = 0x16f5 # macro -mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX = 0 # macro -mmGCMC_VM_XGMI_LFB_CNTL = 0x16f7 # macro -mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX = 0 # macro -mmGCMC_VM_XGMI_LFB_SIZE = 0x16f8 # macro -mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX = 0 # macro -mmGCMC_VM_FB_NOALLOC_CNTL = 0x16f9 # macro -mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro -mmGCUTCL2_HARVEST_BYPASS_GROUPS = 0x16fa # macro -mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro -mmGCMC_VM_FB_LOCATION_BASE = 0x16fc # macro -mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro -mmGCMC_VM_FB_LOCATION_TOP = 0x16fd # macro -mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro -mmGCMC_VM_AGP_TOP = 0x16fe # macro -mmGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro -mmGCMC_VM_AGP_BOT = 0x16ff # macro -mmGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro -mmGCMC_VM_AGP_BASE = 0x1700 # macro -mmGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro -mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x1701 # macro -mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro -mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x1702 # macro -mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro -mmGCMC_VM_MX_L1_TLB_CNTL = 0x1703 # macro -mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro -mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro -mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro -mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro -mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro -mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro -mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_LAZY = 0x17a6 # macro -mmGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_LAZY = 0x17a7 # macro -mmGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro -mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro -mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro -mmGCEA_DRAM_PAGE_BURST = 0x17aa # macro -mmGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro -mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro -mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro -mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro -mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro -mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro -mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro -mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro -mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro -mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro -mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -mmGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro -mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -mmGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro -mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -mmGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro -mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -mmGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro -mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -mmGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro -mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro -mmGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro -mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro -mmGCEA_IO_GROUP_BURST = 0x1883 # macro -mmGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_AGE = 0x1884 # macro -mmGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_AGE = 0x1885 # macro -mmGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro -mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro -mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_FIXED = 0x1888 # macro -mmGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_FIXED = 0x1889 # macro -mmGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_URGENCY = 0x188a # macro -mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_URGENCY = 0x188b # macro -mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro -mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro -mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro -mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro -mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -mmGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro -mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro -mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -mmTCP_INVALIDATE = 0x18a0 # macro -mmTCP_INVALIDATE_BASE_IDX = 0 # macro -mmTCP_STATUS = 0x18a1 # macro -mmTCP_STATUS_BASE_IDX = 0 # macro -mmTCP_EDC_CNT = 0x18b7 # macro -mmTCP_EDC_CNT_BASE_IDX = 0 # macro -mmTCI_STATUS = 0x1901 # macro -mmTCI_STATUS_BASE_IDX = 0 # macro -mmTCI_CNTL_1 = 0x1902 # macro -mmTCI_CNTL_1_BASE_IDX = 0 # macro -mmTCI_CNTL_2 = 0x1903 # macro -mmTCI_CNTL_2_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro -mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro -mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro -mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_PS = 0x19a8 # macro -mmSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_PS = 0x19a9 # macro -mmSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro -mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro -mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro -mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro -mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro -mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro -mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro -mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro -mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro -mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro -mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro -mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro -mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro -mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro -mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro -mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro -mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro -mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro -mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro -mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro -mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro -mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro -mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro -mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro -mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro -mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro -mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro -mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro -mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro -mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro -mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro -mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro -mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro -mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro -mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro -mmSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro -mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro -mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro -mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro -mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro -mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC4_VS = 0x19e1 # macro -mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_CHKSUM_VS = 0x19e5 # macro -mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC3_VS = 0x19e6 # macro -mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_LATE_ALLOC_VS = 0x19e7 # macro -mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_VS = 0x19e8 # macro -mmSPI_SHADER_PGM_LO_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_VS = 0x19e9 # macro -mmSPI_SHADER_PGM_HI_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC1_VS = 0x19ea # macro -mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC2_VS = 0x19eb # macro -mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_0 = 0x19ec # macro -mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_1 = 0x19ed # macro -mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_2 = 0x19ee # macro -mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_3 = 0x19ef # macro -mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_4 = 0x19f0 # macro -mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_5 = 0x19f1 # macro -mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_6 = 0x19f2 # macro -mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_7 = 0x19f3 # macro -mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_8 = 0x19f4 # macro -mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_9 = 0x19f5 # macro -mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_10 = 0x19f6 # macro -mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_11 = 0x19f7 # macro -mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_12 = 0x19f8 # macro -mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_13 = 0x19f9 # macro -mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_14 = 0x19fa # macro -mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_15 = 0x19fb # macro -mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_16 = 0x19fc # macro -mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_17 = 0x19fd # macro -mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_18 = 0x19fe # macro -mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_19 = 0x19ff # macro -mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_20 = 0x1a00 # macro -mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_21 = 0x1a01 # macro -mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_22 = 0x1a02 # macro -mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_23 = 0x1a03 # macro -mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_24 = 0x1a04 # macro -mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_25 = 0x1a05 # macro -mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_26 = 0x1a06 # macro -mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_27 = 0x1a07 # macro -mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_28 = 0x1a08 # macro -mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_29 = 0x1a09 # macro -mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_30 = 0x1a0a # macro -mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_VS_31 = 0x1a0b # macro -mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX = 0 # macro -mmSPI_SHADER_REQ_CTRL_VS = 0x1a10 # macro -mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_VS_0 = 0x1a12 # macro -mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_VS_1 = 0x1a13 # macro -mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_VS_2 = 0x1a14 # macro -mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_VS_3 = 0x1a15 # macro -mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC2_GS_VS = 0x1a1b # macro -mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro -mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro -mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro -mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro -mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro -mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro -mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro -mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_GS = 0x1a28 # macro -mmSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_GS = 0x1a29 # macro -mmSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro -mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro -mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro -mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro -mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro -mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro -mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro -mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro -mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro -mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro -mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro -mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro -mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro -mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro -mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro -mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro -mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro -mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro -mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro -mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro -mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro -mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro -mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro -mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro -mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro -mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro -mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro -mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro -mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro -mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro -mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro -mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro -mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro -mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro -mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro -mmSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro -mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro -mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_ES = 0x1a68 # macro -mmSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_ES = 0x1a69 # macro -mmSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro -mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro -mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro -mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro -mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro -mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro -mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro -mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro -mmSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro -mmSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro -mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro -mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro -mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro -mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro -mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro -mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro -mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro -mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro -mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro -mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro -mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro -mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro -mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro -mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro -mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro -mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro -mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro -mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro -mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro -mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro -mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro -mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro -mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro -mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro -mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro -mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro -mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro -mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro -mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro -mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro -mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro -mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro -mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro -mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro -mmSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro -mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro -mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro -mmSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro -mmSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro -mmSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro -mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro -mmCOMPUTE_DIM_X = 0x1ba1 # macro -mmCOMPUTE_DIM_X_BASE_IDX = 0 # macro -mmCOMPUTE_DIM_Y = 0x1ba2 # macro -mmCOMPUTE_DIM_Y_BASE_IDX = 0 # macro -mmCOMPUTE_DIM_Z = 0x1ba3 # macro -mmCOMPUTE_DIM_Z_BASE_IDX = 0 # macro -mmCOMPUTE_START_X = 0x1ba4 # macro -mmCOMPUTE_START_X_BASE_IDX = 0 # macro -mmCOMPUTE_START_Y = 0x1ba5 # macro -mmCOMPUTE_START_Y_BASE_IDX = 0 # macro -mmCOMPUTE_START_Z = 0x1ba6 # macro -mmCOMPUTE_START_Z_BASE_IDX = 0 # macro -mmCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro -mmCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro -mmCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro -mmCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro -mmCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro -mmCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro -mmCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro -mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro -mmCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro -mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro -mmCOMPUTE_PGM_LO = 0x1bac # macro -mmCOMPUTE_PGM_LO_BASE_IDX = 0 # macro -mmCOMPUTE_PGM_HI = 0x1bad # macro -mmCOMPUTE_PGM_HI_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro -mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro -mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro -mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro -mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro -mmCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro -mmCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro -mmCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro -mmCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro -mmCOMPUTE_VMID = 0x1bb4 # macro -mmCOMPUTE_VMID_BASE_IDX = 0 # macro -mmCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro -mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro -mmCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro -mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro -mmCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro -mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro -mmCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro -mmCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro -mmCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro -mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro -mmCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro -mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro -mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro -mmCOMPUTE_RESTART_X = 0x1bbb # macro -mmCOMPUTE_RESTART_X_BASE_IDX = 0 # macro -mmCOMPUTE_RESTART_Y = 0x1bbc # macro -mmCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro -mmCOMPUTE_RESTART_Z = 0x1bbd # macro -mmCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro -mmCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro -mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro -mmCOMPUTE_MISC_RESERVED = 0x1bbf # macro -mmCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_ID = 0x1bc0 # macro -mmCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro -mmCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro -mmCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro -mmCOMPUTE_REQ_CTRL = 0x1bc2 # macro -mmCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro -mmCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro -mmCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro -mmCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro -mmCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro -mmCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro -mmCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro -mmCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro -mmCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro -mmCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro -mmCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro -mmCOMPUTE_DDID_INDEX = 0x1bc9 # macro -mmCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro -mmCOMPUTE_SHADER_CHKSUM = 0x1bca # macro -mmCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro -mmCOMPUTE_RELAUNCH = 0x1bcb # macro -mmCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro -mmCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bcc # macro -mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro -mmCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bcd # macro -mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro -mmCOMPUTE_RELAUNCH2 = 0x1bce # macro -mmCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_0 = 0x1be0 # macro -mmCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_1 = 0x1be1 # macro -mmCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_2 = 0x1be2 # macro -mmCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_3 = 0x1be3 # macro -mmCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_4 = 0x1be4 # macro -mmCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_5 = 0x1be5 # macro -mmCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_6 = 0x1be6 # macro -mmCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_7 = 0x1be7 # macro -mmCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_8 = 0x1be8 # macro -mmCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_9 = 0x1be9 # macro -mmCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_10 = 0x1bea # macro -mmCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_11 = 0x1beb # macro -mmCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_12 = 0x1bec # macro -mmCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_13 = 0x1bed # macro -mmCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_14 = 0x1bee # macro -mmCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro -mmCOMPUTE_USER_DATA_15 = 0x1bef # macro -mmCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro -mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro -mmCOMPUTE_DISPATCH_END = 0x1c1e # macro -mmCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro -mmCOMPUTE_NOWHERE = 0x1c1f # macro -mmCOMPUTE_NOWHERE_BASE_IDX = 0 # macro -mmSH_RESERVED_REG0 = 0x1c20 # macro -mmSH_RESERVED_REG0_BASE_IDX = 0 # macro -mmSH_RESERVED_REG1 = 0x1c21 # macro -mmSH_RESERVED_REG1_BASE_IDX = 0 # macro -mmCP_EOPQ_WAIT_TIME = 0x1dd5 # macro -mmCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro -mmCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro -mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro -mmCPC_INT_INFO = 0x1dd7 # macro -mmCPC_INT_INFO_BASE_IDX = 0 # macro -mmCP_VIRT_STATUS = 0x1dd8 # macro -mmCP_VIRT_STATUS_BASE_IDX = 0 # macro -mmCPC_INT_ADDR = 0x1dd9 # macro -mmCPC_INT_ADDR_BASE_IDX = 0 # macro -mmCPC_INT_PASID = 0x1dda # macro -mmCPC_INT_PASID_BASE_IDX = 0 # macro -mmCP_GFX_ERROR = 0x1ddb # macro -mmCP_GFX_ERROR_BASE_IDX = 0 # macro -mmCPG_UTCL1_CNTL = 0x1ddc # macro -mmCPG_UTCL1_CNTL_BASE_IDX = 0 # macro -mmCPC_UTCL1_CNTL = 0x1ddd # macro -mmCPC_UTCL1_CNTL_BASE_IDX = 0 # macro -mmCPF_UTCL1_CNTL = 0x1dde # macro -mmCPF_UTCL1_CNTL_BASE_IDX = 0 # macro -mmCP_AQL_SMM_STATUS = 0x1ddf # macro -mmCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro -mmCP_RB0_BASE = 0x1de0 # macro -mmCP_RB0_BASE_BASE_IDX = 0 # macro -mmCP_RB_BASE = 0x1de0 # macro -mmCP_RB_BASE_BASE_IDX = 0 # macro -mmCP_RB0_CNTL = 0x1de1 # macro -mmCP_RB0_CNTL_BASE_IDX = 0 # macro -mmCP_RB_CNTL = 0x1de1 # macro -mmCP_RB_CNTL_BASE_IDX = 0 # macro -mmCP_RB_RPTR_WR = 0x1de2 # macro -mmCP_RB_RPTR_WR_BASE_IDX = 0 # macro -mmCP_RB0_RPTR_ADDR = 0x1de3 # macro -mmCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_RB_RPTR_ADDR = 0x1de3 # macro -mmCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro -mmCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_RB_RPTR_ADDR_HI = 0x1de4 # macro -mmCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_RB0_BUFSZ_MASK = 0x1de5 # macro -mmCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro -mmCP_RB_BUFSZ_MASK = 0x1de5 # macro -mmCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro -mmCP_INT_CNTL = 0x1de9 # macro -mmCP_INT_CNTL_BASE_IDX = 0 # macro -mmCP_INT_STATUS = 0x1dea # macro -mmCP_INT_STATUS_BASE_IDX = 0 # macro -mmCP_DEVICE_ID = 0x1deb # macro -mmCP_DEVICE_ID_BASE_IDX = 0 # macro -mmCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro -mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -mmCP_RING_PRIORITY_CNTS = 0x1dec # macro -mmCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro -mmCP_ME0_PIPE0_PRIORITY = 0x1ded # macro -mmCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro -mmCP_RING0_PRIORITY = 0x1ded # macro -mmCP_RING0_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME0_PIPE1_PRIORITY = 0x1dee # macro -mmCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro -mmCP_RING1_PRIORITY = 0x1dee # macro -mmCP_RING1_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME0_PIPE2_PRIORITY = 0x1def # macro -mmCP_ME0_PIPE2_PRIORITY_BASE_IDX = 0 # macro -mmCP_RING2_PRIORITY = 0x1def # macro -mmCP_RING2_PRIORITY_BASE_IDX = 0 # macro -mmCP_FATAL_ERROR = 0x1df0 # macro -mmCP_FATAL_ERROR_BASE_IDX = 0 # macro -mmCP_RB_VMID = 0x1df1 # macro -mmCP_RB_VMID_BASE_IDX = 0 # macro -mmCP_ME0_PIPE0_VMID = 0x1df2 # macro -mmCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro -mmCP_ME0_PIPE1_VMID = 0x1df3 # macro -mmCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro -mmCP_RB0_WPTR = 0x1df4 # macro -mmCP_RB0_WPTR_BASE_IDX = 0 # macro -mmCP_RB_WPTR = 0x1df4 # macro -mmCP_RB_WPTR_BASE_IDX = 0 # macro -mmCP_RB0_WPTR_HI = 0x1df5 # macro -mmCP_RB0_WPTR_HI_BASE_IDX = 0 # macro -mmCP_RB_WPTR_HI = 0x1df5 # macro -mmCP_RB_WPTR_HI_BASE_IDX = 0 # macro -mmCP_RB1_WPTR = 0x1df6 # macro -mmCP_RB1_WPTR_BASE_IDX = 0 # macro -mmCP_RB1_WPTR_HI = 0x1df7 # macro -mmCP_RB1_WPTR_HI_BASE_IDX = 0 # macro -mmCP_RB2_WPTR = 0x1df8 # macro -mmCP_RB2_WPTR_BASE_IDX = 0 # macro -mmCP_PROCESS_QUANTUM = 0x1df9 # macro -mmCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro -mmCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro -mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -mmCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro -mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -mmCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro -mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -mmCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro -mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -mmCPG_UTCL1_ERROR = 0x1dfe # macro -mmCPG_UTCL1_ERROR_BASE_IDX = 0 # macro -mmCPC_UTCL1_ERROR = 0x1dff # macro -mmCPC_UTCL1_ERROR_BASE_IDX = 0 # macro -mmCP_RB1_BASE = 0x1e00 # macro -mmCP_RB1_BASE_BASE_IDX = 0 # macro -mmCP_RB1_CNTL = 0x1e01 # macro -mmCP_RB1_CNTL_BASE_IDX = 0 # macro -mmCP_RB1_RPTR_ADDR = 0x1e02 # macro -mmCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro -mmCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_RB1_BUFSZ_MASK = 0x1e04 # macro -mmCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro -mmCP_RB2_BASE = 0x1e05 # macro -mmCP_RB2_BASE_BASE_IDX = 0 # macro -mmCP_RB2_CNTL = 0x1e06 # macro -mmCP_RB2_CNTL_BASE_IDX = 0 # macro -mmCP_RB2_RPTR_ADDR = 0x1e07 # macro -mmCP_RB2_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_RB2_RPTR_ADDR_HI = 0x1e08 # macro -mmCP_RB2_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_INT_CNTL_RING0 = 0x1e0a # macro -mmCP_INT_CNTL_RING0_BASE_IDX = 0 # macro -mmCP_INT_CNTL_RING1 = 0x1e0b # macro -mmCP_INT_CNTL_RING1_BASE_IDX = 0 # macro -mmCP_INT_CNTL_RING2 = 0x1e0c # macro -mmCP_INT_CNTL_RING2_BASE_IDX = 0 # macro -mmCP_INT_STATUS_RING0 = 0x1e0d # macro -mmCP_INT_STATUS_RING0_BASE_IDX = 0 # macro -mmCP_INT_STATUS_RING1 = 0x1e0e # macro -mmCP_INT_STATUS_RING1_BASE_IDX = 0 # macro -mmCP_INT_STATUS_RING2 = 0x1e0f # macro -mmCP_INT_STATUS_RING2_BASE_IDX = 0 # macro -mmCP_ME_F32_INTERRUPT = 0x1e13 # macro -mmCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro -mmCP_PFP_F32_INTERRUPT = 0x1e14 # macro -mmCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro -mmCP_CE_F32_INTERRUPT = 0x1e15 # macro -mmCP_CE_F32_INTERRUPT_BASE_IDX = 0 # macro -mmCP_MEC1_F32_INTERRUPT = 0x1e16 # macro -mmCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro -mmCP_MEC2_F32_INTERRUPT = 0x1e17 # macro -mmCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro -mmCP_PWR_CNTL = 0x1e18 # macro -mmCP_PWR_CNTL_BASE_IDX = 0 # macro -mmCP_MEM_SLP_CNTL = 0x1e19 # macro -mmCP_MEM_SLP_CNTL_BASE_IDX = 0 # macro -mmCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro -mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro -mmCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro -mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro -mmCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro -mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro -mmCP_ECC_FIRSTOCCURRENCE_RING2 = 0x1e1d # macro -mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX = 0 # macro -mmGB_EDC_MODE = 0x1e1e # macro -mmGB_EDC_MODE_BASE_IDX = 0 # macro -mmCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro -mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -mmCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro -mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro -mmCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro -mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro -mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro -mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro -mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro -mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro -mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro -mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro -mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -mmCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro -mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro -mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro -mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro -mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro -mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro -mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro -mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -mmCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro -mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -mmCP_GFX_QUEUE_INDEX = 0x1e37 # macro -mmCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro -mmCC_GC_EDC_CONFIG = 0x1e38 # macro -mmCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro -mmCP_ME1_INT_STAT_DEBUG = 0x1e35 # macro -mmCP_ME1_INT_STAT_DEBUG_BASE_IDX = 0 # macro -mmCP_ME2_INT_STAT_DEBUG = 0x1e36 # macro -mmCP_ME2_INT_STAT_DEBUG_BASE_IDX = 0 # macro -mmCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro -mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -mmCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro -mmCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro -mmCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro -mmCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro -mmCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro -mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -mmCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro -mmCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro -mmCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro -mmCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro -mmCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro -mmCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro -mmCP_CE_PRGRM_CNTR_START = 0x1e43 # macro -mmCP_CE_PRGRM_CNTR_START_BASE_IDX = 0 # macro -mmCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro -mmCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro -mmCP_ME_PRGRM_CNTR_START = 0x1e45 # macro -mmCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro -mmCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro -mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro -mmCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro -mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro -mmCP_CE_INTR_ROUTINE_START = 0x1e48 # macro -mmCP_CE_INTR_ROUTINE_START_BASE_IDX = 0 # macro -mmCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro -mmCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro -mmCP_ME_INTR_ROUTINE_START = 0x1e4a # macro -mmCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro -mmCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro -mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro -mmCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro -mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro -mmCP_CONTEXT_CNTL = 0x1e4d # macro -mmCP_CONTEXT_CNTL_BASE_IDX = 0 # macro -mmCP_MAX_CONTEXT = 0x1e4e # macro -mmCP_MAX_CONTEXT_BASE_IDX = 0 # macro -mmCP_IQ_WAIT_TIME1 = 0x1e4f # macro -mmCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro -mmCP_IQ_WAIT_TIME2 = 0x1e50 # macro -mmCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro -mmCP_RB0_BASE_HI = 0x1e51 # macro -mmCP_RB0_BASE_HI_BASE_IDX = 0 # macro -mmCP_RB1_BASE_HI = 0x1e52 # macro -mmCP_RB1_BASE_HI_BASE_IDX = 0 # macro -mmCP_VMID_RESET = 0x1e53 # macro -mmCP_VMID_RESET_BASE_IDX = 0 # macro -mmCPC_INT_CNTL = 0x1e54 # macro -mmCPC_INT_CNTL_BASE_IDX = 0 # macro -mmCPC_INT_STATUS = 0x1e55 # macro -mmCPC_INT_STATUS_BASE_IDX = 0 # macro -mmCP_VMID_PREEMPT = 0x1e56 # macro -mmCP_VMID_PREEMPT_BASE_IDX = 0 # macro -mmCPC_INT_CNTX_ID = 0x1e57 # macro -mmCPC_INT_CNTX_ID_BASE_IDX = 0 # macro -mmCP_PQ_STATUS = 0x1e58 # macro -mmCP_PQ_STATUS_BASE_IDX = 0 # macro -mmCP_MEC1_F32_INT_DIS = 0x1e5d # macro -mmCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro -mmCP_MEC2_F32_INT_DIS = 0x1e5e # macro -mmCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro -mmCP_VMID_STATUS = 0x1e5f # macro -mmCP_VMID_STATUS_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro -mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro -mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro -mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro -mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro -mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -mmCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro -mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -mmCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro -mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -mmCPC_OS_PIPES = 0x1e67 # macro -mmCPC_OS_PIPES_BASE_IDX = 0 # macro -mmCP_SUSPEND_RESUME_REQ = 0x1e68 # macro -mmCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro -mmCP_SUSPEND_CNTL = 0x1e69 # macro -mmCP_SUSPEND_CNTL_BASE_IDX = 0 # macro -mmCP_IQ_WAIT_TIME3 = 0x1e6a # macro -mmCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro -mmCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro -mmCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DDID_BASE_ADDR_LO = 0x1e6b # macro -mmCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -mmCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro -mmCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DDID_BASE_ADDR_HI = 0x1e6c # macro -mmCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCPC_DDID_CNTL = 0x1e6d # macro -mmCPC_DDID_CNTL_BASE_IDX = 0 # macro -mmCP_DDID_CNTL = 0x1e6d # macro -mmCP_DDID_CNTL_BASE_IDX = 0 # macro -mmCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro -mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -mmCP_GFX_DDID_WPTR = 0x1e6f # macro -mmCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro -mmCP_GFX_DDID_RPTR = 0x1e70 # macro -mmCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro -mmCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro -mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -mmCP_GFX_HPD_STATUS0 = 0x1e72 # macro -mmCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro -mmCP_GFX_HPD_CONTROL0 = 0x1e73 # macro -mmCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro -mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro -mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro -mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro -mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro -mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro -mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro -mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro -mmCP_GFX_INDEX_MUTEX = 0x1e78 # macro -mmCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro -mmCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro -mmCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro -mmCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro -mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_ACTIVE = 0x1e80 # macro -mmCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro -mmCP_GFX_HQD_VMID = 0x1e81 # macro -mmCP_GFX_HQD_VMID_BASE_IDX = 0 # macro -mmCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro -mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -mmCP_GFX_HQD_QUANTUM = 0x1e85 # macro -mmCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro -mmCP_GFX_HQD_BASE = 0x1e86 # macro -mmCP_GFX_HQD_BASE_BASE_IDX = 0 # macro -mmCP_GFX_HQD_BASE_HI = 0x1e87 # macro -mmCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_RPTR = 0x1e88 # macro -mmCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro -mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro -mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro -mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro -mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmCP_RB_DOORBELL_CONTROL = 0x1e8d # macro -mmCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro -mmCP_GFX_HQD_OFFSET = 0x1e8e # macro -mmCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CNTL = 0x1e8f # macro -mmCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro -mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_WPTR = 0x1e91 # macro -mmCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_WPTR_HI = 0x1e92 # macro -mmCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro -mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -mmCP_GFX_HQD_MAPPED = 0x1e94 # macro -mmCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro -mmCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro -mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro -mmCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro -mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -mmCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro -mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -mmCP_GFX_MQD_CONTROL = 0x1e9a # macro -mmCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_GFX_CONTROL = 0x1e9f # macro -mmCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_GFX_STATUS = 0x1ea0 # macro -mmCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_RPTR_WR = 0x1ea1 # macro -mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_BASE = 0x1ea2 # macro -mmCP_GFX_HQD_CE_BASE_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_BASE_HI = 0x1ea3 # macro -mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_RPTR = 0x1ea4 # macro -mmCP_GFX_HQD_CE_RPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_RPTR_ADDR = 0x1ea5 # macro -mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_RPTR_ADDR_HI = 0x1ea6 # macro -mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO = 0x1ea7 # macro -mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI = 0x1ea8 # macro -mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_OFFSET = 0x1ea9 # macro -mmCP_GFX_HQD_CE_OFFSET_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_CNTL = 0x1eaa # macro -mmCP_GFX_HQD_CE_CNTL_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_CSMD_RPTR = 0x1eab # macro -mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_WPTR = 0x1eac # macro -mmCP_GFX_HQD_CE_WPTR_BASE_IDX = 0 # macro -mmCP_GFX_HQD_CE_WPTR_HI = 0x1ead # macro -mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX = 0 # macro -mmCP_CE_DOORBELL_CONTROL = 0x1eae # macro -mmCP_CE_DOORBELL_CONTROL_BASE_IDX = 0 # macro -mmCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro -mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro -mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DMA_WATCH0_MASK = 0x1ec2 # macro -mmCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro -mmCP_DMA_WATCH0_CNTL = 0x1ec3 # macro -mmCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro -mmCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro -mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro -mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DMA_WATCH1_MASK = 0x1ec6 # macro -mmCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro -mmCP_DMA_WATCH1_CNTL = 0x1ec7 # macro -mmCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro -mmCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro -mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro -mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DMA_WATCH2_MASK = 0x1eca # macro -mmCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro -mmCP_DMA_WATCH2_CNTL = 0x1ecb # macro -mmCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro -mmCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro -mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro -mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DMA_WATCH3_MASK = 0x1ece # macro -mmCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro -mmCP_DMA_WATCH3_CNTL = 0x1ecf # macro -mmCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro -mmCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro -mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro -mmCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro -mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro -mmCP_DMA_WATCH_STAT = 0x1ed2 # macro -mmCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro -mmCP_PFP_JT_STAT = 0x1ed3 # macro -mmCP_PFP_JT_STAT_BASE_IDX = 0 # macro -mmCP_CE_JT_STAT = 0x1ed4 # macro -mmCP_CE_JT_STAT_BASE_IDX = 0 # macro -mmCP_MEC_JT_STAT = 0x1ed5 # macro -mmCP_MEC_JT_STAT_BASE_IDX = 0 # macro -mmCP_FETCHER_SOURCE = 0x1f1e # macro -mmCP_FETCHER_SOURCE_BASE_IDX = 0 # macro -mmCP_CE_CS_PARTITION_INDEX = 0x1f1f # macro -mmCP_CE_CS_PARTITION_INDEX_BASE_IDX = 0 # macro -mmCP_RB_DOORBELL_CLEAR = 0x1f28 # macro -mmCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro -mmCP_RB0_ACTIVE = 0x1f40 # macro -mmCP_RB0_ACTIVE_BASE_IDX = 0 # macro -mmCP_RB_ACTIVE = 0x1f40 # macro -mmCP_RB_ACTIVE_BASE_IDX = 0 # macro -mmCP_RB1_ACTIVE = 0x1f41 # macro -mmCP_RB1_ACTIVE_BASE_IDX = 0 # macro -mmCP_RB_STATUS = 0x1f43 # macro -mmCP_RB_STATUS_BASE_IDX = 0 # macro -mmCPG_RCIU_CAM_INDEX = 0x1f44 # macro -mmCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro -mmCPG_RCIU_CAM_DATA = 0x1f45 # macro -mmCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro -mmCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro -mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro -mmCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro -mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro -mmCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro -mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro -mmCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro -mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro -mmCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro -mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro -mmCPF_GCR_CNTL = 0x1f53 # macro -mmCPF_GCR_CNTL_BASE_IDX = 0 # macro -mmCPG_UTCL1_STATUS = 0x1f54 # macro -mmCPG_UTCL1_STATUS_BASE_IDX = 0 # macro -mmCPC_UTCL1_STATUS = 0x1f55 # macro -mmCPC_UTCL1_STATUS_BASE_IDX = 0 # macro -mmCPF_UTCL1_STATUS = 0x1f56 # macro -mmCPF_UTCL1_STATUS_BASE_IDX = 0 # macro -mmCP_SD_CNTL = 0x1f57 # macro -mmCP_SD_CNTL_BASE_IDX = 0 # macro -mmCP_SOFT_RESET_CNTL = 0x1f59 # macro -mmCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro -mmCP_CPC_GFX_CNTL = 0x1f5a # macro -mmCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro -mmSPI_ARB_PRIORITY = 0x1f60 # macro -mmSPI_ARB_PRIORITY_BASE_IDX = 0 # macro -mmSPI_ARB_CYCLES_0 = 0x1f61 # macro -mmSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro -mmSPI_ARB_CYCLES_1 = 0x1f62 # macro -mmSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro -mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro -mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro -mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro -mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro -mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro -mmSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro -mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro -mmSPI_GDBG_WAVE_CNTL = 0x1f71 # macro -mmSPI_GDBG_WAVE_CNTL_BASE_IDX = 0 # macro -mmSPI_GDBG_TRAP_CONFIG = 0x1f72 # macro -mmSPI_GDBG_TRAP_CONFIG_BASE_IDX = 0 # macro -mmSPI_GDBG_TRAP_MASK = 0x1f73 # macro -mmSPI_GDBG_TRAP_MASK_BASE_IDX = 0 # macro -mmSPI_GDBG_WAVE_CNTL2 = 0x1f74 # macro -mmSPI_GDBG_WAVE_CNTL2_BASE_IDX = 0 # macro -mmSPI_GDBG_WAVE_CNTL3 = 0x1f75 # macro -mmSPI_GDBG_WAVE_CNTL3_BASE_IDX = 0 # macro -mmSPI_GDBG_TRAP_DATA0 = 0x1f78 # macro -mmSPI_GDBG_TRAP_DATA0_BASE_IDX = 0 # macro -mmSPI_GDBG_TRAP_DATA1 = 0x1f79 # macro -mmSPI_GDBG_TRAP_DATA1_BASE_IDX = 0 # macro -mmSPI_COMPUTE_QUEUE_RESET = 0x1f7b # macro -mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_0 = 0x1f7c # macro -mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_1 = 0x1f7d # macro -mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_2 = 0x1f7e # macro -mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_3 = 0x1f7f # macro -mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_4 = 0x1f80 # macro -mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_5 = 0x1f81 # macro -mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_6 = 0x1f82 # macro -mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_7 = 0x1f83 # macro -mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_8 = 0x1f84 # macro -mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_CU_9 = 0x1f85 # macro -mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1f86 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1f87 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1f88 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1f89 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1f8a # macro -mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1f8b # macro -mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1f8c # macro -mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1f8d # macro -mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1f8e # macro -mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 0 # macro -mmSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1f8f # macro -mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 0 # macro -mmSPI_COMPUTE_WF_CTX_SAVE = 0x1f9c # macro -mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro -mmSPI_ARB_CNTL_0 = 0x1f9d # macro -mmSPI_ARB_CNTL_0_BASE_IDX = 0 # macro -mmSPI_FEATURE_CTRL = 0x1f9e # macro -mmSPI_FEATURE_CTRL_BASE_IDX = 0 # macro -mmSPI_SHADER_RSRC_LIMIT_CTRL = 0x1f9f # macro -mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 0 # macro -mmCP_HPD_MES_ROQ_OFFSETS = 0x1fa4 # macro -mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 0 # macro -mmCP_HPD_ROQ_OFFSETS = 0x1fa4 # macro -mmCP_HPD_ROQ_OFFSETS_BASE_IDX = 0 # macro -mmCP_HPD_STATUS0 = 0x1fa5 # macro -mmCP_HPD_STATUS0_BASE_IDX = 0 # macro -mmCP_HPD_UTCL1_CNTL = 0x1fa6 # macro -mmCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro -mmCP_HPD_UTCL1_ERROR = 0x1fa7 # macro -mmCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro -mmCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro -mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro -mmCP_MQD_BASE_ADDR = 0x1fa9 # macro -mmCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro -mmCP_MQD_BASE_ADDR_HI = 0x1faa # macro -mmCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_ACTIVE = 0x1fab # macro -mmCP_HQD_ACTIVE_BASE_IDX = 0 # macro -mmCP_HQD_VMID = 0x1fac # macro -mmCP_HQD_VMID_BASE_IDX = 0 # macro -mmCP_HQD_PERSISTENT_STATE = 0x1fad # macro -mmCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro -mmCP_HQD_PIPE_PRIORITY = 0x1fae # macro -mmCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro -mmCP_HQD_QUEUE_PRIORITY = 0x1faf # macro -mmCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -mmCP_HQD_QUANTUM = 0x1fb0 # macro -mmCP_HQD_QUANTUM_BASE_IDX = 0 # macro -mmCP_HQD_PQ_BASE = 0x1fb1 # macro -mmCP_HQD_PQ_BASE_BASE_IDX = 0 # macro -mmCP_HQD_PQ_BASE_HI = 0x1fb2 # macro -mmCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro -mmCP_HQD_PQ_RPTR = 0x1fb3 # macro -mmCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro -mmCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro -mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro -mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro -mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro -mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro -mmCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro -mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro -mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_PQ_CONTROL = 0x1fba # macro -mmCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_IB_BASE_ADDR = 0x1fbb # macro -mmCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro -mmCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro -mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_IB_RPTR = 0x1fbd # macro -mmCP_HQD_IB_RPTR_BASE_IDX = 0 # macro -mmCP_HQD_IB_CONTROL = 0x1fbe # macro -mmCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_IQ_TIMER = 0x1fbf # macro -mmCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro -mmCP_HQD_IQ_RPTR = 0x1fc0 # macro -mmCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro -mmCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro -mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -mmCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro -mmCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro -mmCP_HQD_OFFLOAD = 0x1fc2 # macro -mmCP_HQD_OFFLOAD_BASE_IDX = 0 # macro -mmCP_HQD_SEMA_CMD = 0x1fc3 # macro -mmCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro -mmCP_HQD_MSG_TYPE = 0x1fc4 # macro -mmCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro -mmCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro -mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro -mmCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro -mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro -mmCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro -mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro -mmCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro -mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro -mmCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro -mmCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro -mmCP_HQD_HQ_STATUS0 = 0x1fc9 # macro -mmCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -mmCP_HQD_HQ_CONTROL0 = 0x1fca # macro -mmCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -mmCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro -mmCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro -mmCP_MQD_CONTROL = 0x1fcb # macro -mmCP_MQD_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_HQ_STATUS1 = 0x1fcc # macro -mmCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro -mmCP_HQD_HQ_CONTROL1 = 0x1fcd # macro -mmCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro -mmCP_HQD_EOP_BASE_ADDR = 0x1fce # macro -mmCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro -mmCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro -mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_EOP_CONTROL = 0x1fd0 # macro -mmCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_EOP_RPTR = 0x1fd1 # macro -mmCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro -mmCP_HQD_EOP_WPTR = 0x1fd2 # macro -mmCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro -mmCP_HQD_EOP_EVENTS = 0x1fd3 # macro -mmCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro -mmCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro -mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -mmCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro -mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -mmCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro -mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro -mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -mmCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro -mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -mmCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro -mmCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro -mmCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro -mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -mmCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro -mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro -mmCP_HQD_ERROR = 0x1fdc # macro -mmCP_HQD_ERROR_BASE_IDX = 0 # macro -mmCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro -mmCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro -mmCP_HQD_AQL_CONTROL = 0x1fde # macro -mmCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro -mmCP_HQD_PQ_WPTR_LO = 0x1fdf # macro -mmCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro -mmCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro -mmCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro -mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro -mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro -mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro -mmCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro -mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -mmCP_HQD_DDID_RPTR = 0x1fe4 # macro -mmCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro -mmCP_HQD_DDID_WPTR = 0x1fe5 # macro -mmCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro -mmCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro -mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -mmCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro -mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -mmCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro -mmCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro -mmDIDT_IND_INDEX = 0x2020 # macro -mmDIDT_IND_INDEX_BASE_IDX = 0 # macro -mmDIDT_IND_DATA = 0x2021 # macro -mmDIDT_IND_DATA_BASE_IDX = 0 # macro -mmDIDT_INDEX_AUTO_INCR_EN = 0x2022 # macro -mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 0 # macro -mmGC_CAC_CTRL_1 = 0x2024 # macro -mmGC_CAC_CTRL_1_BASE_IDX = 0 # macro -mmGC_CAC_CTRL_2 = 0x2025 # macro -mmGC_CAC_CTRL_2_BASE_IDX = 0 # macro -mmGC_CAC_AGGR_LOWER = 0x2026 # macro -mmGC_CAC_AGGR_LOWER_BASE_IDX = 0 # macro -mmGC_CAC_AGGR_UPPER = 0x2027 # macro -mmGC_CAC_AGGR_UPPER_BASE_IDX = 0 # macro -mmGC_CAC_SOFT_CTRL = 0x202a # macro -mmGC_CAC_SOFT_CTRL_BASE_IDX = 0 # macro -mmGC_EDC_CTRL = 0x202b # macro -mmGC_EDC_CTRL_BASE_IDX = 0 # macro -mmGC_EDC_THRESHOLD = 0x202c # macro -mmGC_EDC_THRESHOLD_BASE_IDX = 0 # macro -mmGC_EDC_STATUS = 0x202d # macro -mmGC_EDC_STATUS_BASE_IDX = 0 # macro -mmGC_EDC_OVERFLOW = 0x202e # macro -mmGC_EDC_OVERFLOW_BASE_IDX = 0 # macro -mmGC_EDC_ROLLING_POWER_DELTA = 0x202f # macro -mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 0 # macro -mmGC_THROTTLE_CTRL = 0x2030 # macro -mmGC_THROTTLE_CTRL_BASE_IDX = 0 # macro -mmGC_THROTTLE_CTRL1 = 0x2031 # macro -mmGC_THROTTLE_CTRL1_BASE_IDX = 0 # macro -mmGC_THROTTLE_STATUS = 0x2032 # macro -mmGC_THROTTLE_STATUS_BASE_IDX = 0 # macro -mmEDC_PERF_COUNTER = 0x2033 # macro -mmEDC_PERF_COUNTER_BASE_IDX = 0 # macro -mmPCC_PERF_COUNTER = 0x2034 # macro -mmPCC_PERF_COUNTER_BASE_IDX = 0 # macro -mmPWRBRK_PERF_COUNTER = 0x2035 # macro -mmPWRBRK_PERF_COUNTER_BASE_IDX = 0 # macro -mmGC_EDC_STRETCH_CTRL = 0x2036 # macro -mmGC_EDC_STRETCH_CTRL_BASE_IDX = 0 # macro -mmGC_EDC_STRETCH_THRESHOLD = 0x2037 # macro -mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 0 # macro -mmEDC_HYSTERESIS_CNTL = 0x2038 # macro -mmEDC_HYSTERESIS_CNTL_BASE_IDX = 0 # macro -mmEDC_HYSTERESIS_STAT = 0x2039 # macro -mmEDC_HYSTERESIS_STAT_BASE_IDX = 0 # macro -mmGC_CAC_IND_INDEX = 0x203c # macro -mmGC_CAC_IND_INDEX_BASE_IDX = 0 # macro -mmGC_CAC_IND_DATA = 0x203d # macro -mmGC_CAC_IND_DATA_BASE_IDX = 0 # macro -mmSE_CAC_IND_INDEX = 0x203e # macro -mmSE_CAC_IND_INDEX_BASE_IDX = 0 # macro -mmSE_CAC_IND_DATA = 0x203f # macro -mmSE_CAC_IND_DATA_BASE_IDX = 0 # macro -mmTCP_WATCH0_ADDR_H = 0x2040 # macro -mmTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro -mmTCP_WATCH0_ADDR_L = 0x2041 # macro -mmTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro -mmTCP_WATCH0_CNTL = 0x2042 # macro -mmTCP_WATCH0_CNTL_BASE_IDX = 0 # macro -mmTCP_WATCH1_ADDR_H = 0x2043 # macro -mmTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro -mmTCP_WATCH1_ADDR_L = 0x2044 # macro -mmTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro -mmTCP_WATCH1_CNTL = 0x2045 # macro -mmTCP_WATCH1_CNTL_BASE_IDX = 0 # macro -mmTCP_WATCH2_ADDR_H = 0x2046 # macro -mmTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro -mmTCP_WATCH2_ADDR_L = 0x2047 # macro -mmTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro -mmTCP_WATCH2_CNTL = 0x2048 # macro -mmTCP_WATCH2_CNTL_BASE_IDX = 0 # macro -mmTCP_WATCH3_ADDR_H = 0x2049 # macro -mmTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro -mmTCP_WATCH3_ADDR_L = 0x204a # macro -mmTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro -mmTCP_WATCH3_CNTL = 0x204b # macro -mmTCP_WATCH3_CNTL_BASE_IDX = 0 # macro -mmTCP_PERFCOUNTER_FILTER = 0x2059 # macro -mmTCP_PERFCOUNTER_FILTER_BASE_IDX = 0 # macro -mmTCP_PERFCOUNTER_FILTER_EN = 0x205a # macro -mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 0 # macro -mmTCP_PERFCOUNTER_FILTER2 = 0x205b # macro -mmTCP_PERFCOUNTER_FILTER2_BASE_IDX = 0 # macro -mmGDS_VMID0_BASE = 0x20a0 # macro -mmGDS_VMID0_BASE_BASE_IDX = 0 # macro -mmGDS_VMID0_SIZE = 0x20a1 # macro -mmGDS_VMID0_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID1_BASE = 0x20a2 # macro -mmGDS_VMID1_BASE_BASE_IDX = 0 # macro -mmGDS_VMID1_SIZE = 0x20a3 # macro -mmGDS_VMID1_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID2_BASE = 0x20a4 # macro -mmGDS_VMID2_BASE_BASE_IDX = 0 # macro -mmGDS_VMID2_SIZE = 0x20a5 # macro -mmGDS_VMID2_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID3_BASE = 0x20a6 # macro -mmGDS_VMID3_BASE_BASE_IDX = 0 # macro -mmGDS_VMID3_SIZE = 0x20a7 # macro -mmGDS_VMID3_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID4_BASE = 0x20a8 # macro -mmGDS_VMID4_BASE_BASE_IDX = 0 # macro -mmGDS_VMID4_SIZE = 0x20a9 # macro -mmGDS_VMID4_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID5_BASE = 0x20aa # macro -mmGDS_VMID5_BASE_BASE_IDX = 0 # macro -mmGDS_VMID5_SIZE = 0x20ab # macro -mmGDS_VMID5_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID6_BASE = 0x20ac # macro -mmGDS_VMID6_BASE_BASE_IDX = 0 # macro -mmGDS_VMID6_SIZE = 0x20ad # macro -mmGDS_VMID6_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID7_BASE = 0x20ae # macro -mmGDS_VMID7_BASE_BASE_IDX = 0 # macro -mmGDS_VMID7_SIZE = 0x20af # macro -mmGDS_VMID7_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID8_BASE = 0x20b0 # macro -mmGDS_VMID8_BASE_BASE_IDX = 0 # macro -mmGDS_VMID8_SIZE = 0x20b1 # macro -mmGDS_VMID8_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID9_BASE = 0x20b2 # macro -mmGDS_VMID9_BASE_BASE_IDX = 0 # macro -mmGDS_VMID9_SIZE = 0x20b3 # macro -mmGDS_VMID9_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID10_BASE = 0x20b4 # macro -mmGDS_VMID10_BASE_BASE_IDX = 0 # macro -mmGDS_VMID10_SIZE = 0x20b5 # macro -mmGDS_VMID10_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID11_BASE = 0x20b6 # macro -mmGDS_VMID11_BASE_BASE_IDX = 0 # macro -mmGDS_VMID11_SIZE = 0x20b7 # macro -mmGDS_VMID11_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID12_BASE = 0x20b8 # macro -mmGDS_VMID12_BASE_BASE_IDX = 0 # macro -mmGDS_VMID12_SIZE = 0x20b9 # macro -mmGDS_VMID12_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID13_BASE = 0x20ba # macro -mmGDS_VMID13_BASE_BASE_IDX = 0 # macro -mmGDS_VMID13_SIZE = 0x20bb # macro -mmGDS_VMID13_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID14_BASE = 0x20bc # macro -mmGDS_VMID14_BASE_BASE_IDX = 0 # macro -mmGDS_VMID14_SIZE = 0x20bd # macro -mmGDS_VMID14_SIZE_BASE_IDX = 0 # macro -mmGDS_VMID15_BASE = 0x20be # macro -mmGDS_VMID15_BASE_BASE_IDX = 0 # macro -mmGDS_VMID15_SIZE = 0x20bf # macro -mmGDS_VMID15_SIZE_BASE_IDX = 0 # macro -mmGDS_GWS_VMID0 = 0x20c0 # macro -mmGDS_GWS_VMID0_BASE_IDX = 0 # macro -mmGDS_GWS_VMID1 = 0x20c1 # macro -mmGDS_GWS_VMID1_BASE_IDX = 0 # macro -mmGDS_GWS_VMID2 = 0x20c2 # macro -mmGDS_GWS_VMID2_BASE_IDX = 0 # macro -mmGDS_GWS_VMID3 = 0x20c3 # macro -mmGDS_GWS_VMID3_BASE_IDX = 0 # macro -mmGDS_GWS_VMID4 = 0x20c4 # macro -mmGDS_GWS_VMID4_BASE_IDX = 0 # macro -mmGDS_GWS_VMID5 = 0x20c5 # macro -mmGDS_GWS_VMID5_BASE_IDX = 0 # macro -mmGDS_GWS_VMID6 = 0x20c6 # macro -mmGDS_GWS_VMID6_BASE_IDX = 0 # macro -mmGDS_GWS_VMID7 = 0x20c7 # macro -mmGDS_GWS_VMID7_BASE_IDX = 0 # macro -mmGDS_GWS_VMID8 = 0x20c8 # macro -mmGDS_GWS_VMID8_BASE_IDX = 0 # macro -mmGDS_GWS_VMID9 = 0x20c9 # macro -mmGDS_GWS_VMID9_BASE_IDX = 0 # macro -mmGDS_GWS_VMID10 = 0x20ca # macro -mmGDS_GWS_VMID10_BASE_IDX = 0 # macro -mmGDS_GWS_VMID11 = 0x20cb # macro -mmGDS_GWS_VMID11_BASE_IDX = 0 # macro -mmGDS_GWS_VMID12 = 0x20cc # macro -mmGDS_GWS_VMID12_BASE_IDX = 0 # macro -mmGDS_GWS_VMID13 = 0x20cd # macro -mmGDS_GWS_VMID13_BASE_IDX = 0 # macro -mmGDS_GWS_VMID14 = 0x20ce # macro -mmGDS_GWS_VMID14_BASE_IDX = 0 # macro -mmGDS_GWS_VMID15 = 0x20cf # macro -mmGDS_GWS_VMID15_BASE_IDX = 0 # macro -mmGDS_OA_VMID0 = 0x20d0 # macro -mmGDS_OA_VMID0_BASE_IDX = 0 # macro -mmGDS_OA_VMID1 = 0x20d1 # macro -mmGDS_OA_VMID1_BASE_IDX = 0 # macro -mmGDS_OA_VMID2 = 0x20d2 # macro -mmGDS_OA_VMID2_BASE_IDX = 0 # macro -mmGDS_OA_VMID3 = 0x20d3 # macro -mmGDS_OA_VMID3_BASE_IDX = 0 # macro -mmGDS_OA_VMID4 = 0x20d4 # macro -mmGDS_OA_VMID4_BASE_IDX = 0 # macro -mmGDS_OA_VMID5 = 0x20d5 # macro -mmGDS_OA_VMID5_BASE_IDX = 0 # macro -mmGDS_OA_VMID6 = 0x20d6 # macro -mmGDS_OA_VMID6_BASE_IDX = 0 # macro -mmGDS_OA_VMID7 = 0x20d7 # macro -mmGDS_OA_VMID7_BASE_IDX = 0 # macro -mmGDS_OA_VMID8 = 0x20d8 # macro -mmGDS_OA_VMID8_BASE_IDX = 0 # macro -mmGDS_OA_VMID9 = 0x20d9 # macro -mmGDS_OA_VMID9_BASE_IDX = 0 # macro -mmGDS_OA_VMID10 = 0x20da # macro -mmGDS_OA_VMID10_BASE_IDX = 0 # macro -mmGDS_OA_VMID11 = 0x20db # macro -mmGDS_OA_VMID11_BASE_IDX = 0 # macro -mmGDS_OA_VMID12 = 0x20dc # macro -mmGDS_OA_VMID12_BASE_IDX = 0 # macro -mmGDS_OA_VMID13 = 0x20dd # macro -mmGDS_OA_VMID13_BASE_IDX = 0 # macro -mmGDS_OA_VMID14 = 0x20de # macro -mmGDS_OA_VMID14_BASE_IDX = 0 # macro -mmGDS_OA_VMID15 = 0x20df # macro -mmGDS_OA_VMID15_BASE_IDX = 0 # macro -mmGDS_GWS_RESET0 = 0x20e4 # macro -mmGDS_GWS_RESET0_BASE_IDX = 0 # macro -mmGDS_GWS_RESET1 = 0x20e5 # macro -mmGDS_GWS_RESET1_BASE_IDX = 0 # macro -mmGDS_GWS_RESOURCE_RESET = 0x20e6 # macro -mmGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro -mmGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro -mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro -mmGDS_OA_RESET_MASK = 0x20e9 # macro -mmGDS_OA_RESET_MASK_BASE_IDX = 0 # macro -mmGDS_OA_RESET = 0x20ea # macro -mmGDS_OA_RESET_BASE_IDX = 0 # macro -mmGDS_ENHANCE2 = 0x20eb # macro -mmGDS_ENHANCE2_BASE_IDX = 0 # macro -mmGDS_OA_CGPG_RESTORE = 0x20ec # macro -mmGDS_OA_CGPG_RESTORE_BASE_IDX = 0 # macro -mmGDS_CS_CTXSW_STATUS = 0x20ed # macro -mmGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro -mmGDS_CS_CTXSW_CNT0 = 0x20ee # macro -mmGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro -mmGDS_CS_CTXSW_CNT1 = 0x20ef # macro -mmGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro -mmGDS_CS_CTXSW_CNT2 = 0x20f0 # macro -mmGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro -mmGDS_CS_CTXSW_CNT3 = 0x20f1 # macro -mmGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro -mmGDS_GFX_CTXSW_STATUS = 0x20f2 # macro -mmGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro -mmGDS_VS_CTXSW_CNT0 = 0x20f3 # macro -mmGDS_VS_CTXSW_CNT0_BASE_IDX = 0 # macro -mmGDS_VS_CTXSW_CNT1 = 0x20f4 # macro -mmGDS_VS_CTXSW_CNT1_BASE_IDX = 0 # macro -mmGDS_VS_CTXSW_CNT2 = 0x20f5 # macro -mmGDS_VS_CTXSW_CNT2_BASE_IDX = 0 # macro -mmGDS_VS_CTXSW_CNT3 = 0x20f6 # macro -mmGDS_VS_CTXSW_CNT3_BASE_IDX = 0 # macro -mmGDS_PS_CTXSW_CNT0 = 0x20f7 # macro -mmGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro -mmGDS_PS_CTXSW_CNT1 = 0x20f8 # macro -mmGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro -mmGDS_PS_CTXSW_CNT2 = 0x20f9 # macro -mmGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro -mmGDS_PS_CTXSW_CNT3 = 0x20fa # macro -mmGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro -mmGDS_PS_CTXSW_IDX = 0x20fb # macro -mmGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro -mmGDS_GS_CTXSW_CNT0 = 0x2117 # macro -mmGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro -mmGDS_GS_CTXSW_CNT1 = 0x2118 # macro -mmGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro -mmGDS_GS_CTXSW_CNT2 = 0x2119 # macro -mmGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro -mmGDS_GS_CTXSW_CNT3 = 0x211a # macro -mmGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro -mmGDS_MEMORY_CLEAN = 0x211f # macro -mmGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro -mmDB_RENDER_CONTROL = 0x0000 # macro -mmDB_RENDER_CONTROL_BASE_IDX = 1 # macro -mmDB_COUNT_CONTROL = 0x0001 # macro -mmDB_COUNT_CONTROL_BASE_IDX = 1 # macro -mmDB_DEPTH_VIEW = 0x0002 # macro -mmDB_DEPTH_VIEW_BASE_IDX = 1 # macro -mmDB_RENDER_OVERRIDE = 0x0003 # macro -mmDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro -mmDB_RENDER_OVERRIDE2 = 0x0004 # macro -mmDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro -mmDB_HTILE_DATA_BASE = 0x0005 # macro -mmDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro -mmDB_DEPTH_SIZE_XY = 0x0007 # macro -mmDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro -mmDB_DEPTH_BOUNDS_MIN = 0x0008 # macro -mmDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro -mmDB_DEPTH_BOUNDS_MAX = 0x0009 # macro -mmDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro -mmDB_STENCIL_CLEAR = 0x000a # macro -mmDB_STENCIL_CLEAR_BASE_IDX = 1 # macro -mmDB_DEPTH_CLEAR = 0x000b # macro -mmDB_DEPTH_CLEAR_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro -mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro -mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro -mmDB_DFSM_CONTROL = 0x000e # macro -mmDB_DFSM_CONTROL_BASE_IDX = 1 # macro -mmDB_RESERVED_REG_2 = 0x000f # macro -mmDB_RESERVED_REG_2_BASE_IDX = 1 # macro -mmDB_Z_INFO = 0x0010 # macro -mmDB_Z_INFO_BASE_IDX = 1 # macro -mmDB_STENCIL_INFO = 0x0011 # macro -mmDB_STENCIL_INFO_BASE_IDX = 1 # macro -mmDB_Z_READ_BASE = 0x0012 # macro -mmDB_Z_READ_BASE_BASE_IDX = 1 # macro -mmDB_STENCIL_READ_BASE = 0x0013 # macro -mmDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro -mmDB_Z_WRITE_BASE = 0x0014 # macro -mmDB_Z_WRITE_BASE_BASE_IDX = 1 # macro -mmDB_STENCIL_WRITE_BASE = 0x0015 # macro -mmDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro -mmDB_RESERVED_REG_1 = 0x0016 # macro -mmDB_RESERVED_REG_1_BASE_IDX = 1 # macro -mmDB_RESERVED_REG_3 = 0x0017 # macro -mmDB_RESERVED_REG_3_BASE_IDX = 1 # macro -mmDB_VRS_OVERRIDE_CNTL = 0x0019 # macro -mmDB_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro -mmDB_Z_READ_BASE_HI = 0x001a # macro -mmDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro -mmDB_STENCIL_READ_BASE_HI = 0x001b # macro -mmDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro -mmDB_Z_WRITE_BASE_HI = 0x001c # macro -mmDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro -mmDB_STENCIL_WRITE_BASE_HI = 0x001d # macro -mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro -mmDB_HTILE_DATA_BASE_HI = 0x001e # macro -mmDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro -mmDB_RMI_L2_CACHE_CONTROL = 0x001f # macro -mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro -mmTA_BC_BASE_ADDR = 0x0020 # macro -mmTA_BC_BASE_ADDR_BASE_IDX = 1 # macro -mmTA_BC_BASE_ADDR_HI = 0x0021 # macro -mmTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_HI_0 = 0x007a # macro -mmCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_HI_1 = 0x007b # macro -mmCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_HI_2 = 0x007c # macro -mmCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_HI_3 = 0x007d # macro -mmCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_2 = 0x007e # macro -mmCOHER_DEST_BASE_2_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_3 = 0x007f # macro -mmCOHER_DEST_BASE_3_BASE_IDX = 1 # macro -mmPA_SC_WINDOW_OFFSET = 0x0080 # macro -mmPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro -mmPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro -mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro -mmPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro -mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_RULE = 0x0083 # macro -mmPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_0_TL = 0x0084 # macro -mmPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_0_BR = 0x0085 # macro -mmPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_1_TL = 0x0086 # macro -mmPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_1_BR = 0x0087 # macro -mmPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_2_TL = 0x0088 # macro -mmPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_2_BR = 0x0089 # macro -mmPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_3_TL = 0x008a # macro -mmPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro -mmPA_SC_CLIPRECT_3_BR = 0x008b # macro -mmPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro -mmPA_SC_EDGERULE = 0x008c # macro -mmPA_SC_EDGERULE_BASE_IDX = 1 # macro -mmPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro -mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro -mmCB_TARGET_MASK = 0x008e # macro -mmCB_TARGET_MASK_BASE_IDX = 1 # macro -mmCB_SHADER_MASK = 0x008f # macro -mmCB_SHADER_MASK_BASE_IDX = 1 # macro -mmPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro -mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro -mmPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro -mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_0 = 0x0092 # macro -mmCOHER_DEST_BASE_0_BASE_IDX = 1 # macro -mmCOHER_DEST_BASE_1 = 0x0093 # macro -mmCOHER_DEST_BASE_1_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro -mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro -mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro -mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro -mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro -mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro -mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro -mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro -mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro -mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro -mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro -mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro -mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro -mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro -mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro -mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro -mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro -mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro -mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro -mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro -mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro -mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro -mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro -mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro -mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro -mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro -mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro -mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro -mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro -mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro -mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro -mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro -mmPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro -mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro -mmPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro -mmPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro -mmPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro -mmPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro -mmPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro -mmPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_3 = 0x00ba # macro -mmPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_3 = 0x00bb # macro -mmPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_4 = 0x00bc # macro -mmPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_4 = 0x00bd # macro -mmPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_5 = 0x00be # macro -mmPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_5 = 0x00bf # macro -mmPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro -mmPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro -mmPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro -mmPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro -mmPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro -mmPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro -mmPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro -mmPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro -mmPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro -mmPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro -mmPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_11 = 0x00ca # macro -mmPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_11 = 0x00cb # macro -mmPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_12 = 0x00cc # macro -mmPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_12 = 0x00cd # macro -mmPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_13 = 0x00ce # macro -mmPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_13 = 0x00cf # macro -mmPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro -mmPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro -mmPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro -mmPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro -mmPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro -mmPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro -mmPA_SC_RASTER_CONFIG = 0x00d4 # macro -mmPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro -mmPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro -mmPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro -mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro -mmPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro -mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro -mmCP_PERFMON_CNTX_CNTL = 0x00d8 # macro -mmCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro -mmCP_PIPEID = 0x00d9 # macro -mmCP_PIPEID_BASE_IDX = 1 # macro -mmCP_RINGID = 0x00d9 # macro -mmCP_RINGID_BASE_IDX = 1 # macro -mmCP_VMID = 0x00da # macro -mmCP_VMID_BASE_IDX = 1 # macro -mmCONTEXT_RESERVED_REG0 = 0x00db # macro -mmCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro -mmCONTEXT_RESERVED_REG1 = 0x00dc # macro -mmCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro -mmVGT_MAX_VTX_INDX = 0x0100 # macro -mmVGT_MAX_VTX_INDX_BASE_IDX = 1 # macro -mmVGT_MIN_VTX_INDX = 0x0101 # macro -mmVGT_MIN_VTX_INDX_BASE_IDX = 1 # macro -mmVGT_INDX_OFFSET = 0x0102 # macro -mmVGT_INDX_OFFSET_BASE_IDX = 1 # macro -mmVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro -mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro -mmCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro -mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND_RED = 0x0105 # macro -mmCB_BLEND_RED_BASE_IDX = 1 # macro -mmCB_BLEND_GREEN = 0x0106 # macro -mmCB_BLEND_GREEN_BASE_IDX = 1 # macro -mmCB_BLEND_BLUE = 0x0107 # macro -mmCB_BLEND_BLUE_BASE_IDX = 1 # macro -mmCB_BLEND_ALPHA = 0x0108 # macro -mmCB_BLEND_ALPHA_BASE_IDX = 1 # macro -mmCB_DCC_CONTROL = 0x0109 # macro -mmCB_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COVERAGE_OUT_CONTROL = 0x010a # macro -mmCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro -mmDB_STENCIL_CONTROL = 0x010b # macro -mmDB_STENCIL_CONTROL_BASE_IDX = 1 # macro -mmDB_STENCILREFMASK = 0x010c # macro -mmDB_STENCILREFMASK_BASE_IDX = 1 # macro -mmDB_STENCILREFMASK_BF = 0x010d # macro -mmDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE = 0x010f # macro -mmPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET = 0x0110 # macro -mmPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE = 0x0111 # macro -mmPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET = 0x0112 # macro -mmPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE = 0x0113 # macro -mmPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET = 0x0114 # macro -mmPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_1 = 0x0115 # macro -mmPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro -mmPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_1 = 0x0117 # macro -mmPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro -mmPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro -mmPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro -mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_2 = 0x011b # macro -mmPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_2 = 0x011c # macro -mmPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_2 = 0x011d # macro -mmPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_2 = 0x011e # macro -mmPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_2 = 0x011f # macro -mmPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro -mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_3 = 0x0121 # macro -mmPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro -mmPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_3 = 0x0123 # macro -mmPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro -mmPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro -mmPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro -mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_4 = 0x0127 # macro -mmPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro -mmPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_4 = 0x0129 # macro -mmPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_4 = 0x012a # macro -mmPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_4 = 0x012b # macro -mmPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro -mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_5 = 0x012d # macro -mmPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_5 = 0x012e # macro -mmPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_5 = 0x012f # macro -mmPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro -mmPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro -mmPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro -mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_6 = 0x0133 # macro -mmPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro -mmPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_6 = 0x0135 # macro -mmPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro -mmPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro -mmPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro -mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_7 = 0x0139 # macro -mmPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_7 = 0x013a # macro -mmPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_7 = 0x013b # macro -mmPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_7 = 0x013c # macro -mmPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_7 = 0x013d # macro -mmPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro -mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_8 = 0x013f # macro -mmPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro -mmPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_8 = 0x0141 # macro -mmPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro -mmPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro -mmPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro -mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_9 = 0x0145 # macro -mmPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro -mmPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_9 = 0x0147 # macro -mmPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro -mmPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro -mmPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro -mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_10 = 0x014b # macro -mmPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_10 = 0x014c # macro -mmPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_10 = 0x014d # macro -mmPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_10 = 0x014e # macro -mmPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_10 = 0x014f # macro -mmPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro -mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_11 = 0x0151 # macro -mmPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro -mmPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_11 = 0x0153 # macro -mmPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro -mmPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro -mmPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro -mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_12 = 0x0157 # macro -mmPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro -mmPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_12 = 0x0159 # macro -mmPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_12 = 0x015a # macro -mmPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_12 = 0x015b # macro -mmPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro -mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_13 = 0x015d # macro -mmPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_13 = 0x015e # macro -mmPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_13 = 0x015f # macro -mmPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro -mmPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro -mmPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro -mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_14 = 0x0163 # macro -mmPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro -mmPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_14 = 0x0165 # macro -mmPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro -mmPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro -mmPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro -mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XSCALE_15 = 0x0169 # macro -mmPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro -mmPA_CL_VPORT_XOFFSET_15 = 0x016a # macro -mmPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YSCALE_15 = 0x016b # macro -mmPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro -mmPA_CL_VPORT_YOFFSET_15 = 0x016c # macro -mmPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZSCALE_15 = 0x016d # macro -mmPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro -mmPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro -mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro -mmPA_CL_UCP_0_X = 0x016f # macro -mmPA_CL_UCP_0_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_0_Y = 0x0170 # macro -mmPA_CL_UCP_0_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_0_Z = 0x0171 # macro -mmPA_CL_UCP_0_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_0_W = 0x0172 # macro -mmPA_CL_UCP_0_W_BASE_IDX = 1 # macro -mmPA_CL_UCP_1_X = 0x0173 # macro -mmPA_CL_UCP_1_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_1_Y = 0x0174 # macro -mmPA_CL_UCP_1_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_1_Z = 0x0175 # macro -mmPA_CL_UCP_1_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_1_W = 0x0176 # macro -mmPA_CL_UCP_1_W_BASE_IDX = 1 # macro -mmPA_CL_UCP_2_X = 0x0177 # macro -mmPA_CL_UCP_2_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_2_Y = 0x0178 # macro -mmPA_CL_UCP_2_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_2_Z = 0x0179 # macro -mmPA_CL_UCP_2_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_2_W = 0x017a # macro -mmPA_CL_UCP_2_W_BASE_IDX = 1 # macro -mmPA_CL_UCP_3_X = 0x017b # macro -mmPA_CL_UCP_3_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_3_Y = 0x017c # macro -mmPA_CL_UCP_3_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_3_Z = 0x017d # macro -mmPA_CL_UCP_3_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_3_W = 0x017e # macro -mmPA_CL_UCP_3_W_BASE_IDX = 1 # macro -mmPA_CL_UCP_4_X = 0x017f # macro -mmPA_CL_UCP_4_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_4_Y = 0x0180 # macro -mmPA_CL_UCP_4_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_4_Z = 0x0181 # macro -mmPA_CL_UCP_4_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_4_W = 0x0182 # macro -mmPA_CL_UCP_4_W_BASE_IDX = 1 # macro -mmPA_CL_UCP_5_X = 0x0183 # macro -mmPA_CL_UCP_5_X_BASE_IDX = 1 # macro -mmPA_CL_UCP_5_Y = 0x0184 # macro -mmPA_CL_UCP_5_Y_BASE_IDX = 1 # macro -mmPA_CL_UCP_5_Z = 0x0185 # macro -mmPA_CL_UCP_5_Z_BASE_IDX = 1 # macro -mmPA_CL_UCP_5_W = 0x0186 # macro -mmPA_CL_UCP_5_W_BASE_IDX = 1 # macro -mmPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro -mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_0 = 0x0191 # macro -mmSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_1 = 0x0192 # macro -mmSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_2 = 0x0193 # macro -mmSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_3 = 0x0194 # macro -mmSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_4 = 0x0195 # macro -mmSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_5 = 0x0196 # macro -mmSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_6 = 0x0197 # macro -mmSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_7 = 0x0198 # macro -mmSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_8 = 0x0199 # macro -mmSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_9 = 0x019a # macro -mmSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_10 = 0x019b # macro -mmSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_11 = 0x019c # macro -mmSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_12 = 0x019d # macro -mmSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_13 = 0x019e # macro -mmSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_14 = 0x019f # macro -mmSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro -mmSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro -mmSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro -mmSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro -mmSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro -mmSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro -mmSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro -mmSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro -mmSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro -mmSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro -mmSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_25 = 0x01aa # macro -mmSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_26 = 0x01ab # macro -mmSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_27 = 0x01ac # macro -mmSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_28 = 0x01ad # macro -mmSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_29 = 0x01ae # macro -mmSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_30 = 0x01af # macro -mmSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro -mmSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro -mmSPI_VS_OUT_CONFIG = 0x01b1 # macro -mmSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_ENA = 0x01b3 # macro -mmSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro -mmSPI_PS_INPUT_ADDR = 0x01b4 # macro -mmSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro -mmSPI_INTERP_CONTROL_0 = 0x01b5 # macro -mmSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro -mmSPI_PS_IN_CONTROL = 0x01b6 # macro -mmSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro -mmSPI_BARYC_CNTL = 0x01b8 # macro -mmSPI_BARYC_CNTL_BASE_IDX = 1 # macro -mmSPI_TMPRING_SIZE = 0x01ba # macro -mmSPI_TMPRING_SIZE_BASE_IDX = 1 # macro -mmSPI_SHADER_IDX_FORMAT = 0x01c2 # macro -mmSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro -mmSPI_SHADER_POS_FORMAT = 0x01c3 # macro -mmSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro -mmSPI_SHADER_Z_FORMAT = 0x01c4 # macro -mmSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro -mmSPI_SHADER_COL_FORMAT = 0x01c5 # macro -mmSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro -mmSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro -mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro -mmSX_PS_DOWNCONVERT = 0x01d5 # macro -mmSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro -mmSX_BLEND_OPT_EPSILON = 0x01d6 # macro -mmSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro -mmSX_BLEND_OPT_CONTROL = 0x01d7 # macro -mmSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro -mmSX_MRT0_BLEND_OPT = 0x01d8 # macro -mmSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT1_BLEND_OPT = 0x01d9 # macro -mmSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT2_BLEND_OPT = 0x01da # macro -mmSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT3_BLEND_OPT = 0x01db # macro -mmSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT4_BLEND_OPT = 0x01dc # macro -mmSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT5_BLEND_OPT = 0x01dd # macro -mmSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT6_BLEND_OPT = 0x01de # macro -mmSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro -mmSX_MRT7_BLEND_OPT = 0x01df # macro -mmSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro -mmCB_BLEND0_CONTROL = 0x01e0 # macro -mmCB_BLEND0_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND1_CONTROL = 0x01e1 # macro -mmCB_BLEND1_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND2_CONTROL = 0x01e2 # macro -mmCB_BLEND2_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND3_CONTROL = 0x01e3 # macro -mmCB_BLEND3_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND4_CONTROL = 0x01e4 # macro -mmCB_BLEND4_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND5_CONTROL = 0x01e5 # macro -mmCB_BLEND5_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND6_CONTROL = 0x01e6 # macro -mmCB_BLEND6_CONTROL_BASE_IDX = 1 # macro -mmCB_BLEND7_CONTROL = 0x01e7 # macro -mmCB_BLEND7_CONTROL_BASE_IDX = 1 # macro -mmCS_COPY_STATE = 0x01f3 # macro -mmCS_COPY_STATE_BASE_IDX = 1 # macro -mmGFX_COPY_STATE = 0x01f4 # macro -mmGFX_COPY_STATE_BASE_IDX = 1 # macro -mmPA_CL_POINT_X_RAD = 0x01f5 # macro -mmPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro -mmPA_CL_POINT_Y_RAD = 0x01f6 # macro -mmPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro -mmPA_CL_POINT_SIZE = 0x01f7 # macro -mmPA_CL_POINT_SIZE_BASE_IDX = 1 # macro -mmPA_CL_POINT_CULL_RAD = 0x01f8 # macro -mmPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro -mmVGT_DMA_BASE_HI = 0x01f9 # macro -mmVGT_DMA_BASE_HI_BASE_IDX = 1 # macro -mmVGT_DMA_BASE = 0x01fa # macro -mmVGT_DMA_BASE_BASE_IDX = 1 # macro -mmVGT_DRAW_INITIATOR = 0x01fc # macro -mmVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro -mmVGT_IMMED_DATA = 0x01fd # macro -mmVGT_IMMED_DATA_BASE_IDX = 1 # macro -mmVGT_EVENT_ADDRESS_REG = 0x01fe # macro -mmVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro -mmGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro -mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro -mmDB_DEPTH_CONTROL = 0x0200 # macro -mmDB_DEPTH_CONTROL_BASE_IDX = 1 # macro -mmDB_EQAA = 0x0201 # macro -mmDB_EQAA_BASE_IDX = 1 # macro -mmCB_COLOR_CONTROL = 0x0202 # macro -mmCB_COLOR_CONTROL_BASE_IDX = 1 # macro -mmDB_SHADER_CONTROL = 0x0203 # macro -mmDB_SHADER_CONTROL_BASE_IDX = 1 # macro -mmPA_CL_CLIP_CNTL = 0x0204 # macro -mmPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro -mmPA_SU_SC_MODE_CNTL = 0x0205 # macro -mmPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro -mmPA_CL_VTE_CNTL = 0x0206 # macro -mmPA_CL_VTE_CNTL_BASE_IDX = 1 # macro -mmPA_CL_VS_OUT_CNTL = 0x0207 # macro -mmPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro -mmPA_CL_NANINF_CNTL = 0x0208 # macro -mmPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro -mmPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro -mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro -mmPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro -mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro -mmPA_SU_PRIM_FILTER_CNTL = 0x020b # macro -mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -mmPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro -mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -mmPA_CL_NGG_CNTL = 0x020e # macro -mmPA_CL_NGG_CNTL_BASE_IDX = 1 # macro -mmPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro -mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -mmPA_STEREO_CNTL = 0x0210 # macro -mmPA_STEREO_CNTL_BASE_IDX = 1 # macro -mmPA_STATE_STEREO_X = 0x0211 # macro -mmPA_STATE_STEREO_X_BASE_IDX = 1 # macro -mmPA_CL_VRS_CNTL = 0x0212 # macro -mmPA_CL_VRS_CNTL_BASE_IDX = 1 # macro -mmPA_SU_POINT_SIZE = 0x0280 # macro -mmPA_SU_POINT_SIZE_BASE_IDX = 1 # macro -mmPA_SU_POINT_MINMAX = 0x0281 # macro -mmPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro -mmPA_SU_LINE_CNTL = 0x0282 # macro -mmPA_SU_LINE_CNTL_BASE_IDX = 1 # macro -mmPA_SC_LINE_STIPPLE = 0x0283 # macro -mmPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro -mmVGT_OUTPUT_PATH_CNTL = 0x0284 # macro -mmVGT_OUTPUT_PATH_CNTL_BASE_IDX = 1 # macro -mmVGT_HOS_CNTL = 0x0285 # macro -mmVGT_HOS_CNTL_BASE_IDX = 1 # macro -mmVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro -mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro -mmVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro -mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro -mmVGT_HOS_REUSE_DEPTH = 0x0288 # macro -mmVGT_HOS_REUSE_DEPTH_BASE_IDX = 1 # macro -mmVGT_GROUP_PRIM_TYPE = 0x0289 # macro -mmVGT_GROUP_PRIM_TYPE_BASE_IDX = 1 # macro -mmVGT_GROUP_FIRST_DECR = 0x028a # macro -mmVGT_GROUP_FIRST_DECR_BASE_IDX = 1 # macro -mmVGT_GROUP_DECR = 0x028b # macro -mmVGT_GROUP_DECR_BASE_IDX = 1 # macro -mmVGT_GROUP_VECT_0_CNTL = 0x028c # macro -mmVGT_GROUP_VECT_0_CNTL_BASE_IDX = 1 # macro -mmVGT_GROUP_VECT_1_CNTL = 0x028d # macro -mmVGT_GROUP_VECT_1_CNTL_BASE_IDX = 1 # macro -mmVGT_GROUP_VECT_0_FMT_CNTL = 0x028e # macro -mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX = 1 # macro -mmVGT_GROUP_VECT_1_FMT_CNTL = 0x028f # macro -mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX = 1 # macro -mmVGT_GS_MODE = 0x0290 # macro -mmVGT_GS_MODE_BASE_IDX = 1 # macro -mmVGT_GS_ONCHIP_CNTL = 0x0291 # macro -mmVGT_GS_ONCHIP_CNTL_BASE_IDX = 1 # macro -mmPA_SC_MODE_CNTL_0 = 0x0292 # macro -mmPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro -mmPA_SC_MODE_CNTL_1 = 0x0293 # macro -mmPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro -mmVGT_ENHANCE = 0x0294 # macro -mmVGT_ENHANCE_BASE_IDX = 1 # macro -mmVGT_GS_PER_ES = 0x0295 # macro -mmVGT_GS_PER_ES_BASE_IDX = 1 # macro -mmVGT_ES_PER_GS = 0x0296 # macro -mmVGT_ES_PER_GS_BASE_IDX = 1 # macro -mmVGT_GS_PER_VS = 0x0297 # macro -mmVGT_GS_PER_VS_BASE_IDX = 1 # macro -mmVGT_GSVS_RING_OFFSET_1 = 0x0298 # macro -mmVGT_GSVS_RING_OFFSET_1_BASE_IDX = 1 # macro -mmVGT_GSVS_RING_OFFSET_2 = 0x0299 # macro -mmVGT_GSVS_RING_OFFSET_2_BASE_IDX = 1 # macro -mmVGT_GSVS_RING_OFFSET_3 = 0x029a # macro -mmVGT_GSVS_RING_OFFSET_3_BASE_IDX = 1 # macro -mmVGT_GS_OUT_PRIM_TYPE = 0x029b # macro -mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro -mmIA_ENHANCE = 0x029c # macro -mmIA_ENHANCE_BASE_IDX = 1 # macro -mmVGT_DMA_SIZE = 0x029d # macro -mmVGT_DMA_SIZE_BASE_IDX = 1 # macro -mmVGT_DMA_MAX_SIZE = 0x029e # macro -mmVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro -mmVGT_DMA_INDEX_TYPE = 0x029f # macro -mmVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro -mmWD_ENHANCE = 0x02a0 # macro -mmWD_ENHANCE_BASE_IDX = 1 # macro -mmVGT_PRIMITIVEID_EN = 0x02a1 # macro -mmVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro -mmVGT_DMA_NUM_INSTANCES = 0x02a2 # macro -mmVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro -mmVGT_PRIMITIVEID_RESET = 0x02a3 # macro -mmVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro -mmVGT_EVENT_INITIATOR = 0x02a4 # macro -mmVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro -mmVGT_MULTI_PRIM_IB_RESET_EN = 0x02a5 # macro -mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro -mmVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro -mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro -mmVGT_INSTANCE_STEP_RATE_0 = 0x02a8 # macro -mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX = 1 # macro -mmVGT_INSTANCE_STEP_RATE_1 = 0x02a9 # macro -mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX = 1 # macro -mmIA_MULTI_VGT_PARAM = 0x02aa # macro -mmIA_MULTI_VGT_PARAM_BASE_IDX = 1 # macro -mmVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro -mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro -mmVGT_GSVS_RING_ITEMSIZE = 0x02ac # macro -mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX = 1 # macro -mmVGT_REUSE_OFF = 0x02ad # macro -mmVGT_REUSE_OFF_BASE_IDX = 1 # macro -mmVGT_VTX_CNT_EN = 0x02ae # macro -mmVGT_VTX_CNT_EN_BASE_IDX = 1 # macro -mmDB_HTILE_SURFACE = 0x02af # macro -mmDB_HTILE_SURFACE_BASE_IDX = 1 # macro -mmDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro -mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro -mmDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro -mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro -mmDB_PRELOAD_CONTROL = 0x02b2 # macro -mmDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_SIZE_0 = 0x02b4 # macro -mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX = 1 # macro -mmVGT_STRMOUT_VTX_STRIDE_0 = 0x02b5 # macro -mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_0 = 0x02b7 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_SIZE_1 = 0x02b8 # macro -mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX = 1 # macro -mmVGT_STRMOUT_VTX_STRIDE_1 = 0x02b9 # macro -mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_1 = 0x02bb # macro -mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_SIZE_2 = 0x02bc # macro -mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX = 1 # macro -mmVGT_STRMOUT_VTX_STRIDE_2 = 0x02bd # macro -mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_2 = 0x02bf # macro -mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_SIZE_3 = 0x02c0 # macro -mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX = 1 # macro -mmVGT_STRMOUT_VTX_STRIDE_3 = 0x02c1 # macro -mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_3 = 0x02c3 # macro -mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX = 1 # macro -mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro -mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro -mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro -mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro -mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro -mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro -mmVGT_GS_MAX_VERT_OUT = 0x02ce # macro -mmVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro -mmGE_NGG_SUBGRP_CNTL = 0x02d3 # macro -mmGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro -mmVGT_TESS_DISTRIBUTION = 0x02d4 # macro -mmVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro -mmVGT_SHADER_STAGES_EN = 0x02d5 # macro -mmVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro -mmVGT_LS_HS_CONFIG = 0x02d6 # macro -mmVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro -mmVGT_GS_VERT_ITEMSIZE = 0x02d7 # macro -mmVGT_GS_VERT_ITEMSIZE_BASE_IDX = 1 # macro -mmVGT_GS_VERT_ITEMSIZE_1 = 0x02d8 # macro -mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX = 1 # macro -mmVGT_GS_VERT_ITEMSIZE_2 = 0x02d9 # macro -mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX = 1 # macro -mmVGT_GS_VERT_ITEMSIZE_3 = 0x02da # macro -mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX = 1 # macro -mmVGT_TF_PARAM = 0x02db # macro -mmVGT_TF_PARAM_BASE_IDX = 1 # macro -mmDB_ALPHA_TO_MASK = 0x02dc # macro -mmDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro -mmVGT_DISPATCH_DRAW_INDEX = 0x02dd # macro -mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro -mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro -mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro -mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro -mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro -mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro -mmPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro -mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro -mmVGT_GS_INSTANCE_CNT = 0x02e4 # macro -mmVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro -mmVGT_STRMOUT_CONFIG = 0x02e5 # macro -mmVGT_STRMOUT_CONFIG_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_CONFIG = 0x02e6 # macro -mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX = 1 # macro -mmVGT_DMA_EVENT_INITIATOR = 0x02e7 # macro -mmVGT_DMA_EVENT_INITIATOR_BASE_IDX = 1 # macro -mmPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro -mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro -mmPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro -mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro -mmPA_SC_LINE_CNTL = 0x02f7 # macro -mmPA_SC_LINE_CNTL_BASE_IDX = 1 # macro -mmPA_SC_AA_CONFIG = 0x02f8 # macro -mmPA_SC_AA_CONFIG_BASE_IDX = 1 # macro -mmPA_SU_VTX_CNTL = 0x02f9 # macro -mmPA_SU_VTX_CNTL_BASE_IDX = 1 # macro -mmPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro -mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro -mmPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro -mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro -mmPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro -mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro -mmPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro -mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro -mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro -mmPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro -mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro -mmPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro -mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro -mmPA_SC_SHADER_CONTROL = 0x0310 # macro -mmPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro -mmPA_SC_BINNER_CNTL_0 = 0x0311 # macro -mmPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro -mmPA_SC_BINNER_CNTL_1 = 0x0312 # macro -mmPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro -mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro -mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -mmPA_SC_NGG_MODE_CNTL = 0x0314 # macro -mmPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro -mmVGT_VERTEX_REUSE_BLOCK_CNTL = 0x0316 # macro -mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX = 1 # macro -mmVGT_OUT_DEALLOC_CNTL = 0x0317 # macro -mmVGT_OUT_DEALLOC_CNTL_BASE_IDX = 1 # macro -mmCB_COLOR0_BASE = 0x0318 # macro -mmCB_COLOR0_BASE_BASE_IDX = 1 # macro -mmCB_COLOR0_PITCH = 0x0319 # macro -mmCB_COLOR0_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR0_SLICE = 0x031a # macro -mmCB_COLOR0_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR0_VIEW = 0x031b # macro -mmCB_COLOR0_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR0_INFO = 0x031c # macro -mmCB_COLOR0_INFO_BASE_IDX = 1 # macro -mmCB_COLOR0_ATTRIB = 0x031d # macro -mmCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR0_DCC_CONTROL = 0x031e # macro -mmCB_COLOR0_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR0_CMASK = 0x031f # macro -mmCB_COLOR0_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR0_CMASK_SLICE = 0x0320 # macro -mmCB_COLOR0_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR0_FMASK = 0x0321 # macro -mmCB_COLOR0_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR0_FMASK_SLICE = 0x0322 # macro -mmCB_COLOR0_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR0_CLEAR_WORD0 = 0x0323 # macro -mmCB_COLOR0_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR0_CLEAR_WORD1 = 0x0324 # macro -mmCB_COLOR0_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR0_DCC_BASE = 0x0325 # macro -mmCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR1_BASE = 0x0327 # macro -mmCB_COLOR1_BASE_BASE_IDX = 1 # macro -mmCB_COLOR1_PITCH = 0x0328 # macro -mmCB_COLOR1_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR1_SLICE = 0x0329 # macro -mmCB_COLOR1_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR1_VIEW = 0x032a # macro -mmCB_COLOR1_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR1_INFO = 0x032b # macro -mmCB_COLOR1_INFO_BASE_IDX = 1 # macro -mmCB_COLOR1_ATTRIB = 0x032c # macro -mmCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR1_DCC_CONTROL = 0x032d # macro -mmCB_COLOR1_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR1_CMASK = 0x032e # macro -mmCB_COLOR1_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR1_CMASK_SLICE = 0x032f # macro -mmCB_COLOR1_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR1_FMASK = 0x0330 # macro -mmCB_COLOR1_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR1_FMASK_SLICE = 0x0331 # macro -mmCB_COLOR1_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR1_CLEAR_WORD0 = 0x0332 # macro -mmCB_COLOR1_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR1_CLEAR_WORD1 = 0x0333 # macro -mmCB_COLOR1_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR1_DCC_BASE = 0x0334 # macro -mmCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR2_BASE = 0x0336 # macro -mmCB_COLOR2_BASE_BASE_IDX = 1 # macro -mmCB_COLOR2_PITCH = 0x0337 # macro -mmCB_COLOR2_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR2_SLICE = 0x0338 # macro -mmCB_COLOR2_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR2_VIEW = 0x0339 # macro -mmCB_COLOR2_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR2_INFO = 0x033a # macro -mmCB_COLOR2_INFO_BASE_IDX = 1 # macro -mmCB_COLOR2_ATTRIB = 0x033b # macro -mmCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR2_DCC_CONTROL = 0x033c # macro -mmCB_COLOR2_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR2_CMASK = 0x033d # macro -mmCB_COLOR2_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR2_CMASK_SLICE = 0x033e # macro -mmCB_COLOR2_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR2_FMASK = 0x033f # macro -mmCB_COLOR2_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR2_FMASK_SLICE = 0x0340 # macro -mmCB_COLOR2_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR2_CLEAR_WORD0 = 0x0341 # macro -mmCB_COLOR2_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR2_CLEAR_WORD1 = 0x0342 # macro -mmCB_COLOR2_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR2_DCC_BASE = 0x0343 # macro -mmCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR3_BASE = 0x0345 # macro -mmCB_COLOR3_BASE_BASE_IDX = 1 # macro -mmCB_COLOR3_PITCH = 0x0346 # macro -mmCB_COLOR3_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR3_SLICE = 0x0347 # macro -mmCB_COLOR3_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR3_VIEW = 0x0348 # macro -mmCB_COLOR3_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR3_INFO = 0x0349 # macro -mmCB_COLOR3_INFO_BASE_IDX = 1 # macro -mmCB_COLOR3_ATTRIB = 0x034a # macro -mmCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR3_DCC_CONTROL = 0x034b # macro -mmCB_COLOR3_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR3_CMASK = 0x034c # macro -mmCB_COLOR3_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR3_CMASK_SLICE = 0x034d # macro -mmCB_COLOR3_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR3_FMASK = 0x034e # macro -mmCB_COLOR3_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR3_FMASK_SLICE = 0x034f # macro -mmCB_COLOR3_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR3_CLEAR_WORD0 = 0x0350 # macro -mmCB_COLOR3_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR3_CLEAR_WORD1 = 0x0351 # macro -mmCB_COLOR3_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR3_DCC_BASE = 0x0352 # macro -mmCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR4_BASE = 0x0354 # macro -mmCB_COLOR4_BASE_BASE_IDX = 1 # macro -mmCB_COLOR4_PITCH = 0x0355 # macro -mmCB_COLOR4_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR4_SLICE = 0x0356 # macro -mmCB_COLOR4_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR4_VIEW = 0x0357 # macro -mmCB_COLOR4_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR4_INFO = 0x0358 # macro -mmCB_COLOR4_INFO_BASE_IDX = 1 # macro -mmCB_COLOR4_ATTRIB = 0x0359 # macro -mmCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR4_DCC_CONTROL = 0x035a # macro -mmCB_COLOR4_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR4_CMASK = 0x035b # macro -mmCB_COLOR4_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR4_CMASK_SLICE = 0x035c # macro -mmCB_COLOR4_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR4_FMASK = 0x035d # macro -mmCB_COLOR4_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR4_FMASK_SLICE = 0x035e # macro -mmCB_COLOR4_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR4_CLEAR_WORD0 = 0x035f # macro -mmCB_COLOR4_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR4_CLEAR_WORD1 = 0x0360 # macro -mmCB_COLOR4_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR4_DCC_BASE = 0x0361 # macro -mmCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR5_BASE = 0x0363 # macro -mmCB_COLOR5_BASE_BASE_IDX = 1 # macro -mmCB_COLOR5_PITCH = 0x0364 # macro -mmCB_COLOR5_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR5_SLICE = 0x0365 # macro -mmCB_COLOR5_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR5_VIEW = 0x0366 # macro -mmCB_COLOR5_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR5_INFO = 0x0367 # macro -mmCB_COLOR5_INFO_BASE_IDX = 1 # macro -mmCB_COLOR5_ATTRIB = 0x0368 # macro -mmCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR5_DCC_CONTROL = 0x0369 # macro -mmCB_COLOR5_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR5_CMASK = 0x036a # macro -mmCB_COLOR5_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR5_CMASK_SLICE = 0x036b # macro -mmCB_COLOR5_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR5_FMASK = 0x036c # macro -mmCB_COLOR5_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR5_FMASK_SLICE = 0x036d # macro -mmCB_COLOR5_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR5_CLEAR_WORD0 = 0x036e # macro -mmCB_COLOR5_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR5_CLEAR_WORD1 = 0x036f # macro -mmCB_COLOR5_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR5_DCC_BASE = 0x0370 # macro -mmCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR6_BASE = 0x0372 # macro -mmCB_COLOR6_BASE_BASE_IDX = 1 # macro -mmCB_COLOR6_PITCH = 0x0373 # macro -mmCB_COLOR6_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR6_SLICE = 0x0374 # macro -mmCB_COLOR6_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR6_VIEW = 0x0375 # macro -mmCB_COLOR6_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR6_INFO = 0x0376 # macro -mmCB_COLOR6_INFO_BASE_IDX = 1 # macro -mmCB_COLOR6_ATTRIB = 0x0377 # macro -mmCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR6_DCC_CONTROL = 0x0378 # macro -mmCB_COLOR6_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR6_CMASK = 0x0379 # macro -mmCB_COLOR6_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR6_CMASK_SLICE = 0x037a # macro -mmCB_COLOR6_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR6_FMASK = 0x037b # macro -mmCB_COLOR6_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR6_FMASK_SLICE = 0x037c # macro -mmCB_COLOR6_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR6_CLEAR_WORD0 = 0x037d # macro -mmCB_COLOR6_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR6_CLEAR_WORD1 = 0x037e # macro -mmCB_COLOR6_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR6_DCC_BASE = 0x037f # macro -mmCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR7_BASE = 0x0381 # macro -mmCB_COLOR7_BASE_BASE_IDX = 1 # macro -mmCB_COLOR7_PITCH = 0x0382 # macro -mmCB_COLOR7_PITCH_BASE_IDX = 1 # macro -mmCB_COLOR7_SLICE = 0x0383 # macro -mmCB_COLOR7_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR7_VIEW = 0x0384 # macro -mmCB_COLOR7_VIEW_BASE_IDX = 1 # macro -mmCB_COLOR7_INFO = 0x0385 # macro -mmCB_COLOR7_INFO_BASE_IDX = 1 # macro -mmCB_COLOR7_ATTRIB = 0x0386 # macro -mmCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro -mmCB_COLOR7_DCC_CONTROL = 0x0387 # macro -mmCB_COLOR7_DCC_CONTROL_BASE_IDX = 1 # macro -mmCB_COLOR7_CMASK = 0x0388 # macro -mmCB_COLOR7_CMASK_BASE_IDX = 1 # macro -mmCB_COLOR7_CMASK_SLICE = 0x0389 # macro -mmCB_COLOR7_CMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR7_FMASK = 0x038a # macro -mmCB_COLOR7_FMASK_BASE_IDX = 1 # macro -mmCB_COLOR7_FMASK_SLICE = 0x038b # macro -mmCB_COLOR7_FMASK_SLICE_BASE_IDX = 1 # macro -mmCB_COLOR7_CLEAR_WORD0 = 0x038c # macro -mmCB_COLOR7_CLEAR_WORD0_BASE_IDX = 1 # macro -mmCB_COLOR7_CLEAR_WORD1 = 0x038d # macro -mmCB_COLOR7_CLEAR_WORD1_BASE_IDX = 1 # macro -mmCB_COLOR7_DCC_BASE = 0x038e # macro -mmCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro -mmCB_COLOR0_BASE_EXT = 0x0390 # macro -mmCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR1_BASE_EXT = 0x0391 # macro -mmCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR2_BASE_EXT = 0x0392 # macro -mmCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR3_BASE_EXT = 0x0393 # macro -mmCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR4_BASE_EXT = 0x0394 # macro -mmCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR5_BASE_EXT = 0x0395 # macro -mmCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR6_BASE_EXT = 0x0396 # macro -mmCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR7_BASE_EXT = 0x0397 # macro -mmCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR0_CMASK_BASE_EXT = 0x0398 # macro -mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR1_CMASK_BASE_EXT = 0x0399 # macro -mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR2_CMASK_BASE_EXT = 0x039a # macro -mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR3_CMASK_BASE_EXT = 0x039b # macro -mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR4_CMASK_BASE_EXT = 0x039c # macro -mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR5_CMASK_BASE_EXT = 0x039d # macro -mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR6_CMASK_BASE_EXT = 0x039e # macro -mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR7_CMASK_BASE_EXT = 0x039f # macro -mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR0_FMASK_BASE_EXT = 0x03a0 # macro -mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR1_FMASK_BASE_EXT = 0x03a1 # macro -mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR2_FMASK_BASE_EXT = 0x03a2 # macro -mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR3_FMASK_BASE_EXT = 0x03a3 # macro -mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR4_FMASK_BASE_EXT = 0x03a4 # macro -mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR5_FMASK_BASE_EXT = 0x03a5 # macro -mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR6_FMASK_BASE_EXT = 0x03a6 # macro -mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR7_FMASK_BASE_EXT = 0x03a7 # macro -mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro -mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro -mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro -mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro -mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro -mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro -mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro -mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR7_DCC_BASE_EXT = 0x03af # macro -mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro -mmCB_COLOR0_ATTRIB2 = 0x03b0 # macro -mmCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR1_ATTRIB2 = 0x03b1 # macro -mmCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR2_ATTRIB2 = 0x03b2 # macro -mmCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR3_ATTRIB2 = 0x03b3 # macro -mmCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR4_ATTRIB2 = 0x03b4 # macro -mmCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR5_ATTRIB2 = 0x03b5 # macro -mmCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR6_ATTRIB2 = 0x03b6 # macro -mmCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR7_ATTRIB2 = 0x03b7 # macro -mmCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro -mmCB_COLOR0_ATTRIB3 = 0x03b8 # macro -mmCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR1_ATTRIB3 = 0x03b9 # macro -mmCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR2_ATTRIB3 = 0x03ba # macro -mmCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR3_ATTRIB3 = 0x03bb # macro -mmCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR4_ATTRIB3 = 0x03bc # macro -mmCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR5_ATTRIB3 = 0x03bd # macro -mmCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR6_ATTRIB3 = 0x03be # macro -mmCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro -mmCB_COLOR7_ATTRIB3 = 0x03bf # macro -mmCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro -mmCP_EOP_DONE_ADDR_LO = 0x2000 # macro -mmCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro -mmCP_EOP_DONE_ADDR_HI = 0x2001 # macro -mmCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro -mmCP_EOP_DONE_DATA_LO = 0x2002 # macro -mmCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro -mmCP_EOP_DONE_DATA_HI = 0x2003 # macro -mmCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro -mmCP_EOP_LAST_FENCE_LO = 0x2004 # macro -mmCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro -mmCP_EOP_LAST_FENCE_HI = 0x2005 # macro -mmCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro -mmCP_STREAM_OUT_ADDR_LO = 0x2006 # macro -mmCP_STREAM_OUT_ADDR_LO_BASE_IDX = 1 # macro -mmCP_STREAM_OUT_ADDR_HI = 0x2007 # macro -mmCP_STREAM_OUT_ADDR_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT0_LO = 0x2008 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT0_HI = 0x2009 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT0_LO = 0x200a # macro -mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT0_HI = 0x200b # macro -mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT1_LO = 0x200c # macro -mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT1_HI = 0x200d # macro -mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT1_LO = 0x200e # macro -mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT1_HI = 0x200f # macro -mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT2_LO = 0x2010 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT2_HI = 0x2011 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT2_LO = 0x2012 # macro -mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT2_HI = 0x2013 # macro -mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT3_LO = 0x2014 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT3_HI = 0x2015 # macro -mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT3_LO = 0x2016 # macro -mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX = 1 # macro -mmCP_NUM_PRIM_NEEDED_COUNT3_HI = 0x2017 # macro -mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX = 1 # macro -mmCP_PIPE_STATS_ADDR_LO = 0x2018 # macro -mmCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro -mmCP_PIPE_STATS_ADDR_HI = 0x2019 # macro -mmCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro -mmCP_VGT_IAVERT_COUNT_LO = 0x201a # macro -mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_IAVERT_COUNT_HI = 0x201b # macro -mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro -mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro -mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro -mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro -mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro -mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro -mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro -mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro -mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro -mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro -mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro -mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro -mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_PA_CINVOC_COUNT_LO = 0x2028 # macro -mmCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_PA_CINVOC_COUNT_HI = 0x2029 # macro -mmCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_PA_CPRIM_COUNT_LO = 0x202a # macro -mmCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro -mmCP_PA_CPRIM_COUNT_HI = 0x202b # macro -mmCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro -mmCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro -mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro -mmCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro -mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro -mmCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro -mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro -mmCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro -mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro -mmCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro -mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro -mmCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro -mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro -mmCP_PIPE_STATS_CONTROL = 0x203d # macro -mmCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro -mmCP_STREAM_OUT_CONTROL = 0x203e # macro -mmCP_STREAM_OUT_CONTROL_BASE_IDX = 1 # macro -mmCP_STRMOUT_CNTL = 0x203f # macro -mmCP_STRMOUT_CNTL_BASE_IDX = 1 # macro -mmSCRATCH_REG0 = 0x2040 # macro -mmSCRATCH_REG0_BASE_IDX = 1 # macro -mmSCRATCH_REG1 = 0x2041 # macro -mmSCRATCH_REG1_BASE_IDX = 1 # macro -mmSCRATCH_REG2 = 0x2042 # macro -mmSCRATCH_REG2_BASE_IDX = 1 # macro -mmSCRATCH_REG3 = 0x2043 # macro -mmSCRATCH_REG3_BASE_IDX = 1 # macro -mmSCRATCH_REG4 = 0x2044 # macro -mmSCRATCH_REG4_BASE_IDX = 1 # macro -mmSCRATCH_REG5 = 0x2045 # macro -mmSCRATCH_REG5_BASE_IDX = 1 # macro -mmSCRATCH_REG6 = 0x2046 # macro -mmSCRATCH_REG6_BASE_IDX = 1 # macro -mmSCRATCH_REG7 = 0x2047 # macro -mmSCRATCH_REG7_BASE_IDX = 1 # macro -mmSCRATCH_REG_ATOMIC = 0x2048 # macro -mmSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro -mmSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro -mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro -mmCP_APPEND_DDID_CNT = 0x204b # macro -mmCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro -mmCP_APPEND_DATA_HI = 0x204c # macro -mmCP_APPEND_DATA_HI_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro -mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro -mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro -mmSCRATCH_UMSK = 0x2050 # macro -mmSCRATCH_UMSK_BASE_IDX = 1 # macro -mmSCRATCH_ADDR = 0x2051 # macro -mmSCRATCH_ADDR_BASE_IDX = 1 # macro -mmCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro -mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -mmCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro -mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -mmCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro -mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -mmCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro -mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -mmCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro -mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -mmCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro -mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -mmCP_APPEND_ADDR_LO = 0x2058 # macro -mmCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro -mmCP_APPEND_ADDR_HI = 0x2059 # macro -mmCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro -mmCP_APPEND_DATA = 0x205a # macro -mmCP_APPEND_DATA_BASE_IDX = 1 # macro -mmCP_APPEND_DATA_LO = 0x205a # macro -mmCP_APPEND_DATA_LO_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_CS_FENCE = 0x205b # macro -mmCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro -mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_PS_FENCE = 0x205c # macro -mmCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro -mmCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro -mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro -mmCP_ATOMIC_PREOP_LO = 0x205d # macro -mmCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -mmCP_ME_ATOMIC_PREOP_LO = 0x205d # macro -mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -mmCP_ATOMIC_PREOP_HI = 0x205e # macro -mmCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -mmCP_ME_ATOMIC_PREOP_HI = 0x205e # macro -mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -mmCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -mmCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -mmCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -mmCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -mmCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -mmCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -mmCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -mmCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -mmCP_ME_MC_WADDR_LO = 0x2069 # macro -mmCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro -mmCP_ME_MC_WADDR_HI = 0x206a # macro -mmCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro -mmCP_ME_MC_WDATA_LO = 0x206b # macro -mmCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro -mmCP_ME_MC_WDATA_HI = 0x206c # macro -mmCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro -mmCP_ME_MC_RADDR_LO = 0x206d # macro -mmCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro -mmCP_ME_MC_RADDR_HI = 0x206e # macro -mmCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro -mmCP_SEM_WAIT_TIMER = 0x206f # macro -mmCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro -mmCP_SIG_SEM_ADDR_LO = 0x2070 # macro -mmCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro -mmCP_SIG_SEM_ADDR_HI = 0x2071 # macro -mmCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro -mmCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro -mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro -mmCP_WAIT_SEM_ADDR_LO = 0x2075 # macro -mmCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro -mmCP_WAIT_SEM_ADDR_HI = 0x2076 # macro -mmCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_PFP_CONTROL = 0x2077 # macro -mmCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro -mmCP_DMA_ME_CONTROL = 0x2078 # macro -mmCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro -mmCP_COHER_BASE_HI = 0x2079 # macro -mmCP_COHER_BASE_HI_BASE_IDX = 1 # macro -mmCP_COHER_START_DELAY = 0x207b # macro -mmCP_COHER_START_DELAY_BASE_IDX = 1 # macro -mmCP_COHER_CNTL = 0x207c # macro -mmCP_COHER_CNTL_BASE_IDX = 1 # macro -mmCP_COHER_SIZE = 0x207d # macro -mmCP_COHER_SIZE_BASE_IDX = 1 # macro -mmCP_COHER_BASE = 0x207e # macro -mmCP_COHER_BASE_BASE_IDX = 1 # macro -mmCP_COHER_STATUS = 0x207f # macro -mmCP_COHER_STATUS_BASE_IDX = 1 # macro -mmCP_DMA_ME_SRC_ADDR = 0x2080 # macro -mmCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro -mmCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro -mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_ME_DST_ADDR = 0x2082 # macro -mmCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro -mmCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro -mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_ME_COMMAND = 0x2084 # macro -mmCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro -mmCP_DMA_PFP_SRC_ADDR = 0x2085 # macro -mmCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro -mmCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro -mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_PFP_DST_ADDR = 0x2087 # macro -mmCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro -mmCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro -mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_PFP_COMMAND = 0x2089 # macro -mmCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro -mmCP_DMA_CNTL = 0x208a # macro -mmCP_DMA_CNTL_BASE_IDX = 1 # macro -mmCP_DMA_READ_TAGS = 0x208b # macro -mmCP_DMA_READ_TAGS_BASE_IDX = 1 # macro -mmCP_COHER_SIZE_HI = 0x208c # macro -mmCP_COHER_SIZE_HI_BASE_IDX = 1 # macro -mmCP_PFP_IB_CONTROL = 0x208d # macro -mmCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro -mmCP_PFP_LOAD_CONTROL = 0x208e # macro -mmCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro -mmCP_SCRATCH_INDEX = 0x208f # macro -mmCP_SCRATCH_INDEX_BASE_IDX = 1 # macro -mmCP_SCRATCH_DATA = 0x2090 # macro -mmCP_SCRATCH_DATA_BASE_IDX = 1 # macro -mmCP_RB_OFFSET = 0x2091 # macro -mmCP_RB_OFFSET_BASE_IDX = 1 # macro -mmCP_IB2_OFFSET = 0x2093 # macro -mmCP_IB2_OFFSET_BASE_IDX = 1 # macro -mmCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro -mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro -mmCP_IB2_PREAMBLE_END = 0x2097 # macro -mmCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro -mmCP_CE_IB1_OFFSET = 0x2098 # macro -mmCP_CE_IB1_OFFSET_BASE_IDX = 1 # macro -mmCP_CE_IB2_OFFSET = 0x2099 # macro -mmCP_CE_IB2_OFFSET_BASE_IDX = 1 # macro -mmCP_CE_COUNTER = 0x209a # macro -mmCP_CE_COUNTER_BASE_IDX = 1 # macro -mmCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro -mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro -mmCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro -mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro -mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro -mmCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro -mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro -mmCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro -mmCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro -mmCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro -mmCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro -mmUCONFIG_RESERVED_REG0 = 0x20a2 # macro -mmUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro -mmUCONFIG_RESERVED_REG1 = 0x20a3 # macro -mmUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro -mmCP_CE_ATOMIC_PREOP_LO = 0x20a8 # macro -mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -mmCP_CE_ATOMIC_PREOP_HI = 0x20a9 # macro -mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -mmCP_CE_GDS_ATOMIC0_PREOP_LO = 0x20aa # macro -mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -mmCP_CE_GDS_ATOMIC0_PREOP_HI = 0x20ab # macro -mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -mmCP_CE_GDS_ATOMIC1_PREOP_LO = 0x20ac # macro -mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -mmCP_CE_GDS_ATOMIC1_PREOP_HI = 0x20ad # macro -mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -mmCP_CE_INIT_CMD_BUFSZ = 0x20bd # macro -mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_IB1_CMD_BUFSZ = 0x20be # macro -mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_IB2_CMD_BUFSZ = 0x20bf # macro -mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_IB2_CMD_BUFSZ = 0x20c1 # macro -mmCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_ST_CMD_BUFSZ = 0x20c2 # macro -mmCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_INIT_BASE_LO = 0x20c3 # macro -mmCP_CE_INIT_BASE_LO_BASE_IDX = 1 # macro -mmCP_CE_INIT_BASE_HI = 0x20c4 # macro -mmCP_CE_INIT_BASE_HI_BASE_IDX = 1 # macro -mmCP_CE_INIT_BUFSZ = 0x20c5 # macro -mmCP_CE_INIT_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_IB1_BASE_LO = 0x20c6 # macro -mmCP_CE_IB1_BASE_LO_BASE_IDX = 1 # macro -mmCP_CE_IB1_BASE_HI = 0x20c7 # macro -mmCP_CE_IB1_BASE_HI_BASE_IDX = 1 # macro -mmCP_CE_IB1_BUFSZ = 0x20c8 # macro -mmCP_CE_IB1_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_IB2_BASE_LO = 0x20c9 # macro -mmCP_CE_IB2_BASE_LO_BASE_IDX = 1 # macro -mmCP_CE_IB2_BASE_HI = 0x20ca # macro -mmCP_CE_IB2_BASE_HI_BASE_IDX = 1 # macro -mmCP_CE_IB2_BUFSZ = 0x20cb # macro -mmCP_CE_IB2_BUFSZ_BASE_IDX = 1 # macro -mmCP_IB1_BASE_LO = 0x20cc # macro -mmCP_IB1_BASE_LO_BASE_IDX = 1 # macro -mmCP_IB1_BASE_HI = 0x20cd # macro -mmCP_IB1_BASE_HI_BASE_IDX = 1 # macro -mmCP_IB1_BUFSZ = 0x20ce # macro -mmCP_IB1_BUFSZ_BASE_IDX = 1 # macro -mmCP_IB2_BASE_LO = 0x20cf # macro -mmCP_IB2_BASE_LO_BASE_IDX = 1 # macro -mmCP_IB2_BASE_HI = 0x20d0 # macro -mmCP_IB2_BASE_HI_BASE_IDX = 1 # macro -mmCP_IB2_BUFSZ = 0x20d1 # macro -mmCP_IB2_BUFSZ_BASE_IDX = 1 # macro -mmCP_ST_BASE_LO = 0x20d2 # macro -mmCP_ST_BASE_LO_BASE_IDX = 1 # macro -mmCP_ST_BASE_HI = 0x20d3 # macro -mmCP_ST_BASE_HI_BASE_IDX = 1 # macro -mmCP_ST_BUFSZ = 0x20d4 # macro -mmCP_ST_BUFSZ_BASE_IDX = 1 # macro -mmCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro -mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro -mmCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro -mmCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro -mmCP_EOP_DONE_CNTX_ID = 0x20d7 # macro -mmCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro -mmCP_DB_BASE_LO = 0x20d8 # macro -mmCP_DB_BASE_LO_BASE_IDX = 1 # macro -mmCP_DB_BASE_HI = 0x20d9 # macro -mmCP_DB_BASE_HI_BASE_IDX = 1 # macro -mmCP_DB_BUFSZ = 0x20da # macro -mmCP_DB_BUFSZ_BASE_IDX = 1 # macro -mmCP_DB_CMD_BUFSZ = 0x20db # macro -mmCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_DB_BASE_LO = 0x20dc # macro -mmCP_CE_DB_BASE_LO_BASE_IDX = 1 # macro -mmCP_CE_DB_BASE_HI = 0x20dd # macro -mmCP_CE_DB_BASE_HI_BASE_IDX = 1 # macro -mmCP_CE_DB_BUFSZ = 0x20de # macro -mmCP_CE_DB_BUFSZ_BASE_IDX = 1 # macro -mmCP_CE_DB_CMD_BUFSZ = 0x20df # macro -mmCP_CE_DB_CMD_BUFSZ_BASE_IDX = 1 # macro -mmCP_PFP_COMPLETION_STATUS = 0x20ec # macro -mmCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro -mmCP_CE_COMPLETION_STATUS = 0x20ed # macro -mmCP_CE_COMPLETION_STATUS_BASE_IDX = 1 # macro -mmCP_PRED_NOT_VISIBLE = 0x20ee # macro -mmCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro -mmCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro -mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro -mmCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro -mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro -mmCP_CE_METADATA_BASE_ADDR = 0x20f2 # macro -mmCP_CE_METADATA_BASE_ADDR_BASE_IDX = 1 # macro -mmCP_CE_METADATA_BASE_ADDR_HI = 0x20f3 # macro -mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro -mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro -mmCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro -mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro -mmCP_DISPATCH_INDR_ADDR = 0x20f6 # macro -mmCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro -mmCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro -mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro -mmCP_INDEX_BASE_ADDR = 0x20f8 # macro -mmCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro -mmCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro -mmCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro -mmCP_INDEX_TYPE = 0x20fa # macro -mmCP_INDEX_TYPE_BASE_IDX = 1 # macro -mmCP_GDS_BKUP_ADDR = 0x20fb # macro -mmCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro -mmCP_GDS_BKUP_ADDR_HI = 0x20fc # macro -mmCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro -mmCP_SAMPLE_STATUS = 0x20fd # macro -mmCP_SAMPLE_STATUS_BASE_IDX = 1 # macro -mmCP_ME_COHER_CNTL = 0x20fe # macro -mmCP_ME_COHER_CNTL_BASE_IDX = 1 # macro -mmCP_ME_COHER_SIZE = 0x20ff # macro -mmCP_ME_COHER_SIZE_BASE_IDX = 1 # macro -mmCP_ME_COHER_SIZE_HI = 0x2100 # macro -mmCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro -mmCP_ME_COHER_BASE = 0x2101 # macro -mmCP_ME_COHER_BASE_BASE_IDX = 1 # macro -mmCP_ME_COHER_BASE_HI = 0x2102 # macro -mmCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro -mmCP_ME_COHER_STATUS = 0x2103 # macro -mmCP_ME_COHER_STATUS_BASE_IDX = 1 # macro -mmRLC_GPM_PERF_COUNT_0 = 0x2140 # macro -mmRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro -mmRLC_GPM_PERF_COUNT_1 = 0x2141 # macro -mmRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro -mmGRBM_GFX_INDEX = 0x2200 # macro -mmGRBM_GFX_INDEX_BASE_IDX = 1 # macro -mmVGT_ESGS_RING_SIZE_UMD = 0x2240 # macro -mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX = 1 # macro -mmVGT_GSVS_RING_SIZE_UMD = 0x2241 # macro -mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX = 1 # macro -mmVGT_PRIMITIVE_TYPE = 0x2242 # macro -mmVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro -mmVGT_INDEX_TYPE = 0x2243 # macro -mmVGT_INDEX_TYPE_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x2244 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x2245 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x2246 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX = 1 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x2247 # macro -mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX = 1 # macro -mmGE_MIN_VTX_INDX = 0x2249 # macro -mmGE_MIN_VTX_INDX_BASE_IDX = 1 # macro -mmGE_INDX_OFFSET = 0x224a # macro -mmGE_INDX_OFFSET_BASE_IDX = 1 # macro -mmGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro -mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro -mmVGT_NUM_INDICES = 0x224c # macro -mmVGT_NUM_INDICES_BASE_IDX = 1 # macro -mmVGT_NUM_INSTANCES = 0x224d # macro -mmVGT_NUM_INSTANCES_BASE_IDX = 1 # macro -mmVGT_TF_RING_SIZE_UMD = 0x224e # macro -mmVGT_TF_RING_SIZE_UMD_BASE_IDX = 1 # macro -mmVGT_HS_OFFCHIP_PARAM_UMD = 0x224f # macro -mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX = 1 # macro -mmVGT_TF_MEMORY_BASE_UMD = 0x2250 # macro -mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX = 1 # macro -mmGE_DMA_FIRST_INDEX = 0x2251 # macro -mmGE_DMA_FIRST_INDEX_BASE_IDX = 1 # macro -mmWD_POS_BUF_BASE = 0x2252 # macro -mmWD_POS_BUF_BASE_BASE_IDX = 1 # macro -mmWD_POS_BUF_BASE_HI = 0x2253 # macro -mmWD_POS_BUF_BASE_HI_BASE_IDX = 1 # macro -mmWD_CNTL_SB_BUF_BASE = 0x2254 # macro -mmWD_CNTL_SB_BUF_BASE_BASE_IDX = 1 # macro -mmWD_CNTL_SB_BUF_BASE_HI = 0x2255 # macro -mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX = 1 # macro -mmWD_INDEX_BUF_BASE = 0x2256 # macro -mmWD_INDEX_BUF_BASE_BASE_IDX = 1 # macro -mmWD_INDEX_BUF_BASE_HI = 0x2257 # macro -mmWD_INDEX_BUF_BASE_HI_BASE_IDX = 1 # macro -mmIA_MULTI_VGT_PARAM_PIPED = 0x2258 # macro -mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX = 1 # macro -mmGE_MAX_VTX_INDX = 0x2259 # macro -mmGE_MAX_VTX_INDX_BASE_IDX = 1 # macro -mmVGT_INSTANCE_BASE_ID = 0x225a # macro -mmVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro -mmGE_CNTL = 0x225b # macro -mmGE_CNTL_BASE_IDX = 1 # macro -mmGE_USER_VGPR1 = 0x225c # macro -mmGE_USER_VGPR1_BASE_IDX = 1 # macro -mmGE_USER_VGPR2 = 0x225d # macro -mmGE_USER_VGPR2_BASE_IDX = 1 # macro -mmGE_USER_VGPR3 = 0x225e # macro -mmGE_USER_VGPR3_BASE_IDX = 1 # macro -mmGE_STEREO_CNTL = 0x225f # macro -mmGE_STEREO_CNTL_BASE_IDX = 1 # macro -mmGE_PC_ALLOC = 0x2260 # macro -mmGE_PC_ALLOC_BASE_IDX = 1 # macro -mmVGT_TF_MEMORY_BASE_HI_UMD = 0x2261 # macro -mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX = 1 # macro -mmGE_USER_VGPR_EN = 0x2262 # macro -mmGE_USER_VGPR_EN_BASE_IDX = 1 # macro -mmPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro -mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro -mmPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro -mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro -mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro -mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro -mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro -mmPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro -mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro -mmPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro -mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -mmPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro -mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -mmPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro -mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro -mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -mmPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro -mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -mmPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro -mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -mmPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro -mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -mmPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro -mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro -mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -mmPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro -mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -mmPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro -mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -mmPA_SC_TRAP_SCREEN_H = 0x22b1 # macro -mmPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro -mmPA_SC_TRAP_SCREEN_V = 0x22b2 # macro -mmPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro -mmPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro -mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -mmPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro -mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro -mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro -mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro -mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro -mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro -mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro -mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro -mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro -mmSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro -mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro -mmSQC_CACHES = 0x2348 # macro -mmSQC_CACHES_BASE_IDX = 1 # macro -mmTA_CS_BC_BASE_ADDR = 0x2380 # macro -mmTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro -mmTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro -mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro -mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro -mmDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro -mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro -mmDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro -mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro -mmDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro -mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro -mmDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro -mmDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro -mmDB_ZPASS_COUNT_LOW = 0x23fe # macro -mmDB_ZPASS_COUNT_LOW_BASE_IDX = 1 # macro -mmDB_ZPASS_COUNT_HI = 0x23ff # macro -mmDB_ZPASS_COUNT_HI_BASE_IDX = 1 # macro -mmGDS_RD_ADDR = 0x2400 # macro -mmGDS_RD_ADDR_BASE_IDX = 1 # macro -mmGDS_RD_DATA = 0x2401 # macro -mmGDS_RD_DATA_BASE_IDX = 1 # macro -mmGDS_RD_BURST_ADDR = 0x2402 # macro -mmGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro -mmGDS_RD_BURST_COUNT = 0x2403 # macro -mmGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro -mmGDS_RD_BURST_DATA = 0x2404 # macro -mmGDS_RD_BURST_DATA_BASE_IDX = 1 # macro -mmGDS_WR_ADDR = 0x2405 # macro -mmGDS_WR_ADDR_BASE_IDX = 1 # macro -mmGDS_WR_DATA = 0x2406 # macro -mmGDS_WR_DATA_BASE_IDX = 1 # macro -mmGDS_WR_BURST_ADDR = 0x2407 # macro -mmGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro -mmGDS_WR_BURST_DATA = 0x2408 # macro -mmGDS_WR_BURST_DATA_BASE_IDX = 1 # macro -mmGDS_WRITE_COMPLETE = 0x2409 # macro -mmGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro -mmGDS_ATOM_CNTL = 0x240a # macro -mmGDS_ATOM_CNTL_BASE_IDX = 1 # macro -mmGDS_ATOM_COMPLETE = 0x240b # macro -mmGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro -mmGDS_ATOM_BASE = 0x240c # macro -mmGDS_ATOM_BASE_BASE_IDX = 1 # macro -mmGDS_ATOM_SIZE = 0x240d # macro -mmGDS_ATOM_SIZE_BASE_IDX = 1 # macro -mmGDS_ATOM_OFFSET0 = 0x240e # macro -mmGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro -mmGDS_ATOM_OFFSET1 = 0x240f # macro -mmGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro -mmGDS_ATOM_DST = 0x2410 # macro -mmGDS_ATOM_DST_BASE_IDX = 1 # macro -mmGDS_ATOM_OP = 0x2411 # macro -mmGDS_ATOM_OP_BASE_IDX = 1 # macro -mmGDS_ATOM_SRC0 = 0x2412 # macro -mmGDS_ATOM_SRC0_BASE_IDX = 1 # macro -mmGDS_ATOM_SRC0_U = 0x2413 # macro -mmGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro -mmGDS_ATOM_SRC1 = 0x2414 # macro -mmGDS_ATOM_SRC1_BASE_IDX = 1 # macro -mmGDS_ATOM_SRC1_U = 0x2415 # macro -mmGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro -mmGDS_ATOM_READ0 = 0x2416 # macro -mmGDS_ATOM_READ0_BASE_IDX = 1 # macro -mmGDS_ATOM_READ0_U = 0x2417 # macro -mmGDS_ATOM_READ0_U_BASE_IDX = 1 # macro -mmGDS_ATOM_READ1 = 0x2418 # macro -mmGDS_ATOM_READ1_BASE_IDX = 1 # macro -mmGDS_ATOM_READ1_U = 0x2419 # macro -mmGDS_ATOM_READ1_U_BASE_IDX = 1 # macro -mmGDS_GWS_RESOURCE_CNTL = 0x241a # macro -mmGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro -mmGDS_GWS_RESOURCE = 0x241b # macro -mmGDS_GWS_RESOURCE_BASE_IDX = 1 # macro -mmGDS_GWS_RESOURCE_CNT = 0x241c # macro -mmGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro -mmGDS_OA_CNTL = 0x241d # macro -mmGDS_OA_CNTL_BASE_IDX = 1 # macro -mmGDS_OA_COUNTER = 0x241e # macro -mmGDS_OA_COUNTER_BASE_IDX = 1 # macro -mmGDS_OA_ADDRESS = 0x241f # macro -mmGDS_OA_ADDRESS_BASE_IDX = 1 # macro -mmGDS_OA_INCDEC = 0x2420 # macro -mmGDS_OA_INCDEC_BASE_IDX = 1 # macro -mmGDS_OA_RING_SIZE = 0x2421 # macro -mmGDS_OA_RING_SIZE_BASE_IDX = 1 # macro -mmSPI_CONFIG_CNTL_REMAP = 0x2440 # macro -mmSPI_CONFIG_CNTL_REMAP_BASE_IDX = 1 # macro -mmSPI_CONFIG_CNTL_1_REMAP = 0x2441 # macro -mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX = 1 # macro -mmSPI_CONFIG_CNTL_2_REMAP = 0x2442 # macro -mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX = 1 # macro -mmSPI_WAVE_LIMIT_CNTL_REMAP = 0x2443 # macro -mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX = 1 # macro -mmCP_MES_PRGRM_CNTR_START = 0x2800 # macro -mmCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro -mmCP_MES_INTR_ROUTINE_START = 0x2801 # macro -mmCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro -mmCP_MES_MTVEC_LO = 0x2801 # macro -mmCP_MES_MTVEC_LO_BASE_IDX = 1 # macro -mmCP_MES_MTVEC_HI = 0x2802 # macro -mmCP_MES_MTVEC_HI_BASE_IDX = 1 # macro -mmCP_MES_CNTL = 0x2807 # macro -mmCP_MES_CNTL_BASE_IDX = 1 # macro -mmCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro -mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro -mmCP_MES_PIPE0_PRIORITY = 0x2809 # macro -mmCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro -mmCP_MES_PIPE1_PRIORITY = 0x280a # macro -mmCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro -mmCP_MES_PIPE2_PRIORITY = 0x280b # macro -mmCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro -mmCP_MES_PIPE3_PRIORITY = 0x280c # macro -mmCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro -mmCP_MES_HEADER_DUMP = 0x280d # macro -mmCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro -mmCP_MES_MIE_LO = 0x280e # macro -mmCP_MES_MIE_LO_BASE_IDX = 1 # macro -mmCP_MES_MIE_HI = 0x280f # macro -mmCP_MES_MIE_HI_BASE_IDX = 1 # macro -mmCP_MES_INTERRUPT = 0x2810 # macro -mmCP_MES_INTERRUPT_BASE_IDX = 1 # macro -mmCP_MES_SCRATCH_INDEX = 0x2811 # macro -mmCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro -mmCP_MES_SCRATCH_DATA = 0x2812 # macro -mmCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro -mmCP_MES_INSTR_PNTR = 0x2813 # macro -mmCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro -mmCP_MES_MSCRATCH_HI = 0x2814 # macro -mmCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro -mmCP_MES_MSCRATCH_LO = 0x2815 # macro -mmCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro -mmCP_MES_MSTATUS_LO = 0x2816 # macro -mmCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro -mmCP_MES_MSTATUS_HI = 0x2817 # macro -mmCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro -mmCP_MES_MEPC_LO = 0x2818 # macro -mmCP_MES_MEPC_LO_BASE_IDX = 1 # macro -mmCP_MES_MEPC_HI = 0x2819 # macro -mmCP_MES_MEPC_HI_BASE_IDX = 1 # macro -mmCP_MES_MCAUSE_LO = 0x281a # macro -mmCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro -mmCP_MES_MCAUSE_HI = 0x281b # macro -mmCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro -mmCP_MES_MBADADDR_LO = 0x281c # macro -mmCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro -mmCP_MES_MBADADDR_HI = 0x281d # macro -mmCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro -mmCP_MES_MIP_LO = 0x281e # macro -mmCP_MES_MIP_LO_BASE_IDX = 1 # macro -mmCP_MES_MIP_HI = 0x281f # macro -mmCP_MES_MIP_HI_BASE_IDX = 1 # macro -mmCP_MES_IC_OP_CNTL = 0x2820 # macro -mmCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_MES_MCYCLE_LO = 0x2826 # macro -mmCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro -mmCP_MES_MCYCLE_HI = 0x2827 # macro -mmCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro -mmCP_MES_MTIME_LO = 0x2828 # macro -mmCP_MES_MTIME_LO_BASE_IDX = 1 # macro -mmCP_MES_MTIME_HI = 0x2829 # macro -mmCP_MES_MTIME_HI_BASE_IDX = 1 # macro -mmCP_MES_MINSTRET_LO = 0x282a # macro -mmCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro -mmCP_MES_MINSTRET_HI = 0x282b # macro -mmCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro -mmCP_MES_MISA_LO = 0x282c # macro -mmCP_MES_MISA_LO_BASE_IDX = 1 # macro -mmCP_MES_MISA_HI = 0x282d # macro -mmCP_MES_MISA_HI_BASE_IDX = 1 # macro -mmCP_MES_MVENDORID_LO = 0x282e # macro -mmCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro -mmCP_MES_MVENDORID_HI = 0x282f # macro -mmCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro -mmCP_MES_MARCHID_LO = 0x2830 # macro -mmCP_MES_MARCHID_LO_BASE_IDX = 1 # macro -mmCP_MES_MARCHID_HI = 0x2831 # macro -mmCP_MES_MARCHID_HI_BASE_IDX = 1 # macro -mmCP_MES_MIMPID_LO = 0x2832 # macro -mmCP_MES_MIMPID_LO_BASE_IDX = 1 # macro -mmCP_MES_MIMPID_HI = 0x2833 # macro -mmCP_MES_MIMPID_HI_BASE_IDX = 1 # macro -mmCP_MES_MHARTID_LO = 0x2834 # macro -mmCP_MES_MHARTID_LO_BASE_IDX = 1 # macro -mmCP_MES_MHARTID_HI = 0x2835 # macro -mmCP_MES_MHARTID_HI_BASE_IDX = 1 # macro -mmCP_MES_DC_BASE_CNTL = 0x2836 # macro -mmCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_MES_DC_OP_CNTL = 0x2837 # macro -mmCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_MES_MTIMECMP_LO = 0x2838 # macro -mmCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro -mmCP_MES_MTIMECMP_HI = 0x2839 # macro -mmCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro -mmCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro -mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro -mmCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro -mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL1 = 0x283c # macro -mmCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL2 = 0x283d # macro -mmCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL3 = 0x283e # macro -mmCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL4 = 0x283f # macro -mmCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro -mmCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro -mmCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro -mmCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro -mmCP_MES_GP0_LO = 0x2843 # macro -mmCP_MES_GP0_LO_BASE_IDX = 1 # macro -mmCP_MES_GP0_HI = 0x2844 # macro -mmCP_MES_GP0_HI_BASE_IDX = 1 # macro -mmCP_MES_GP1_LO = 0x2845 # macro -mmCP_MES_GP1_LO_BASE_IDX = 1 # macro -mmCP_MES_GP1_HI = 0x2846 # macro -mmCP_MES_GP1_HI_BASE_IDX = 1 # macro -mmCP_MES_GP2_LO = 0x2847 # macro -mmCP_MES_GP2_LO_BASE_IDX = 1 # macro -mmCP_MES_GP2_HI = 0x2848 # macro -mmCP_MES_GP2_HI_BASE_IDX = 1 # macro -mmCP_MES_GP3_LO = 0x2849 # macro -mmCP_MES_GP3_LO_BASE_IDX = 1 # macro -mmCP_MES_GP3_HI = 0x284a # macro -mmCP_MES_GP3_HI_BASE_IDX = 1 # macro -mmCP_MES_GP4_LO = 0x284b # macro -mmCP_MES_GP4_LO_BASE_IDX = 1 # macro -mmCP_MES_GP4_HI = 0x284c # macro -mmCP_MES_GP4_HI_BASE_IDX = 1 # macro -mmCP_MES_GP5_LO = 0x284d # macro -mmCP_MES_GP5_LO_BASE_IDX = 1 # macro -mmCP_MES_GP5_HI = 0x284e # macro -mmCP_MES_GP5_HI_BASE_IDX = 1 # macro -mmCP_MES_GP6_LO = 0x284f # macro -mmCP_MES_GP6_LO_BASE_IDX = 1 # macro -mmCP_MES_GP6_HI = 0x2850 # macro -mmCP_MES_GP6_HI_BASE_IDX = 1 # macro -mmCP_MES_GP7_LO = 0x2851 # macro -mmCP_MES_GP7_LO_BASE_IDX = 1 # macro -mmCP_MES_GP7_HI = 0x2852 # macro -mmCP_MES_GP7_HI_BASE_IDX = 1 # macro -mmCP_MES_GP8_LO = 0x2853 # macro -mmCP_MES_GP8_LO_BASE_IDX = 1 # macro -mmCP_MES_GP8_HI = 0x2854 # macro -mmCP_MES_GP8_HI_BASE_IDX = 1 # macro -mmCP_MES_GP9_LO = 0x2855 # macro -mmCP_MES_GP9_LO_BASE_IDX = 1 # macro -mmCP_MES_GP9_HI = 0x2856 # macro -mmCP_MES_GP9_HI_BASE_IDX = 1 # macro -mmCP_MES_DM_INDEX_ADDR = 0x2880 # macro -mmCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro -mmCP_MES_DM_INDEX_DATA = 0x2881 # macro -mmCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro -mmCP_MES_PERFCOUNT_CNTL = 0x2899 # macro -mmCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro -mmCP_MES_PENDING_INTERRUPT = 0x289a # macro -mmCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro -mmGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro -mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro -mmGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro -mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro -mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro -mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro -mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro -mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro -mmGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro -mmGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_FIXED = 0x2c08 # macro -mmGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_FIXED = 0x2c09 # macro -mmGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro -mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro -mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro -mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro -mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro -mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro -mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro -mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro -mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro -mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro -mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro -mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro -mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro -mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro -mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro -mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro -mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -mmGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro -mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -mmGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro -mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro -mmGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro -mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro -mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro -mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUEUING = 0x2c22 # macro -mmGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_FIXED = 0x2c23 # macro -mmGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro -mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro -mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro -mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro -mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro -mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro -mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro -mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro -mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro -mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro -mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro -mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -mmGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro -mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro -mmGUS_IO_GROUP_BURST = 0x2c30 # macro -mmGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro -mmGUS_DRAM_GROUP_BURST = 0x2c31 # macro -mmGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro -mmGUS_SDP_ARB_FINAL = 0x2c32 # macro -mmGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro -mmGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro -mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro -mmGUS_SDP_CREDITS = 0x2c34 # macro -mmGUS_SDP_CREDITS_BASE_IDX = 1 # macro -mmGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro -mmGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro -mmGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro -mmGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro -mmGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro -mmGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro -mmGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro -mmGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro -mmGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro -mmGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro -mmGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro -mmGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro -mmGUS_SDP_REQ_CNTL = 0x2c3b # macro -mmGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro -mmGUS_MISC = 0x2c3c # macro -mmGUS_MISC_BASE_IDX = 1 # macro -mmGUS_LATENCY_SAMPLING = 0x2c3d # macro -mmGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro -mmGUS_ERR_STATUS = 0x2c3e # macro -mmGUS_ERR_STATUS_BASE_IDX = 1 # macro -mmGUS_MISC2 = 0x2c3f # macro -mmGUS_MISC2_BASE_IDX = 1 # macro -mmGUS_SDP_ENABLE = 0x2c45 # macro -mmGUS_SDP_ENABLE_BASE_IDX = 1 # macro -mmGUS_L1_CH0_CMD_IN = 0x2c46 # macro -mmGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH0_CMD_OUT = 0x2c47 # macro -mmGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_CH0_DATA_IN = 0x2c48 # macro -mmGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH0_DATA_OUT = 0x2c49 # macro -mmGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro -mmGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro -mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_L1_CH1_CMD_IN = 0x2c4c # macro -mmGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH1_CMD_OUT = 0x2c4d # macro -mmGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_CH1_DATA_IN = 0x2c4e # macro -mmGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH1_DATA_OUT = 0x2c4f # macro -mmGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro -mmGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro -mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA0_CMD_IN = 0x2c52 # macro -mmGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA0_CMD_OUT = 0x2c53 # macro -mmGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA0_DATA_IN = 0x2c54 # macro -mmGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA0_DATA_OUT = 0x2c55 # macro -mmGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro -mmGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro -mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA1_CMD_IN = 0x2c58 # macro -mmGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA1_CMD_OUT = 0x2c59 # macro -mmGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA1_DATA_IN = 0x2c5a # macro -mmGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA1_DATA_OUT = 0x2c5b # macro -mmGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro -mmGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro -mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA2_CMD_IN = 0x2c5e # macro -mmGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA2_CMD_OUT = 0x2c5f # macro -mmGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA2_DATA_IN = 0x2c60 # macro -mmGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA2_DATA_OUT = 0x2c61 # macro -mmGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro -mmGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro -mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA3_CMD_IN = 0x2c64 # macro -mmGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA3_CMD_OUT = 0x2c65 # macro -mmGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA3_DATA_IN = 0x2c66 # macro -mmGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA3_DATA_OUT = 0x2c67 # macro -mmGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro -mmGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro -mmGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro -mmGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro -mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro -mmGUS_MISC3 = 0x2c6a # macro -mmGUS_MISC3_BASE_IDX = 1 # macro -mmGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro -mmGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro -mmGL1_DRAM_BURST_MASK = 0x2d02 # macro -mmGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro -mmGL1_ARB_STATUS = 0x2d03 # macro -mmGL1_ARB_STATUS_BASE_IDX = 1 # macro -mmGL1_PIPE_STEER = 0x2d10 # macro -mmGL1_PIPE_STEER_BASE_IDX = 1 # macro -mmGL1C_STATUS = 0x2d41 # macro -mmGL1C_STATUS_BASE_IDX = 1 # macro -mmGL1C_UTCL0_CNTL2 = 0x2d43 # macro -mmGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro -mmGL1C_UTCL0_STATUS = 0x2d44 # macro -mmGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro -mmGL1C_UTCL0_RETRY = 0x2d45 # macro -mmGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro -mmCH_ARB_CTRL = 0x2d80 # macro -mmCH_ARB_CTRL_BASE_IDX = 1 # macro -mmCH_DRAM_BURST_MASK = 0x2d82 # macro -mmCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro -mmCH_ARB_STATUS = 0x2d83 # macro -mmCH_ARB_STATUS_BASE_IDX = 1 # macro -mmCH_DRAM_BURST_CTRL = 0x2d84 # macro -mmCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro -mmCHA_CHC_CREDITS = 0x2d88 # macro -mmCHA_CHC_CREDITS_BASE_IDX = 1 # macro -mmCHA_CLIENT_FREE_DELAY = 0x2d89 # macro -mmCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro -mmCH_PIPE_STEER = 0x2d90 # macro -mmCH_PIPE_STEER_BASE_IDX = 1 # macro -mmCH_VC5_ENABLE = 0x2d94 # macro -mmCH_VC5_ENABLE_BASE_IDX = 1 # macro -mmCHC_CTRL = 0x2dc0 # macro -mmCHC_CTRL_BASE_IDX = 1 # macro -mmCHC_STATUS = 0x2dc1 # macro -mmCHC_STATUS_BASE_IDX = 1 # macro -mmCHCG_CTRL = 0x2dc2 # macro -mmCHCG_CTRL_BASE_IDX = 1 # macro -mmCHCG_STATUS = 0x2dc3 # macro -mmCHCG_STATUS_BASE_IDX = 1 # macro -mmGL2C_CTRL = 0x2e00 # macro -mmGL2C_CTRL_BASE_IDX = 1 # macro -mmGL2C_CTRL2 = 0x2e01 # macro -mmGL2C_CTRL2_BASE_IDX = 1 # macro -mmGL2C_ADDR_MATCH_MASK = 0x2e03 # macro -mmGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -mmGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro -mmGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -mmGL2C_WBINVL2 = 0x2e05 # macro -mmGL2C_WBINVL2_BASE_IDX = 1 # macro -mmGL2C_SOFT_RESET = 0x2e06 # macro -mmGL2C_SOFT_RESET_BASE_IDX = 1 # macro -mmGL2C_CM_CTRL0 = 0x2e07 # macro -mmGL2C_CM_CTRL0_BASE_IDX = 1 # macro -mmGL2C_CM_CTRL1 = 0x2e08 # macro -mmGL2C_CM_CTRL1_BASE_IDX = 1 # macro -mmGL2C_CM_STALL = 0x2e09 # macro -mmGL2C_CM_STALL_BASE_IDX = 1 # macro -mmGL2C_MDC_PF_FLAG_CTRL = 0x2e0a # macro -mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX = 1 # macro -mmGL2C_LB_CTR_CTRL = 0x2e0d # macro -mmGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro -mmGL2C_LB_DATA0 = 0x2e0e # macro -mmGL2C_LB_DATA0_BASE_IDX = 1 # macro -mmGL2C_LB_DATA1 = 0x2e0f # macro -mmGL2C_LB_DATA1_BASE_IDX = 1 # macro -mmGL2C_LB_DATA2 = 0x2e10 # macro -mmGL2C_LB_DATA2_BASE_IDX = 1 # macro -mmGL2C_LB_DATA3 = 0x2e11 # macro -mmGL2C_LB_DATA3_BASE_IDX = 1 # macro -mmGL2C_LB_CTR_SEL0 = 0x2e12 # macro -mmGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro -mmGL2C_LB_CTR_SEL1 = 0x2e13 # macro -mmGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro -mmGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro -mmGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro -mmGL2A_ADDR_MATCH_MASK = 0x2e21 # macro -mmGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -mmGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro -mmGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -mmGL2A_PRIORITY_CTRL = 0x2e23 # macro -mmGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro -mmGL2_PIPE_STEER_0 = 0x2e25 # macro -mmGL2_PIPE_STEER_0_BASE_IDX = 1 # macro -mmGL2_PIPE_STEER_1 = 0x2e26 # macro -mmGL2_PIPE_STEER_1_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER1_LO = 0x3000 # macro -mmCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER1_HI = 0x3001 # macro -mmCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER0_LO = 0x3002 # macro -mmCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER0_HI = 0x3003 # macro -mmCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER1_LO = 0x3004 # macro -mmCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER1_HI = 0x3005 # macro -mmCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER0_LO = 0x3006 # macro -mmCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER0_HI = 0x3007 # macro -mmCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER1_LO = 0x3008 # macro -mmCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER1_HI = 0x3009 # macro -mmCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER0_LO = 0x300a # macro -mmCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER0_HI = 0x300b # macro -mmCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCPF_LATENCY_STATS_DATA = 0x300c # macro -mmCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -mmCPG_LATENCY_STATS_DATA = 0x300d # macro -mmCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -mmCPC_LATENCY_STATS_DATA = 0x300e # macro -mmCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER0_LO = 0x3040 # macro -mmGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER0_HI = 0x3041 # macro -mmGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER1_LO = 0x3043 # macro -mmGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER1_HI = 0x3044 # macro -mmGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro -mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro -mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro -mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro -mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro -mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro -mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro -mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro -mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER0_LO = 0x30a4 # macro -mmGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER0_HI = 0x30a5 # macro -mmGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER1_LO = 0x30a6 # macro -mmGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER1_HI = 0x30a7 # macro -mmGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER2_LO = 0x30a8 # macro -mmGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER2_HI = 0x30a9 # macro -mmGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER3_LO = 0x30aa # macro -mmGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER3_HI = 0x30ab # macro -mmGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro -mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro -mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro -mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro -mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro -mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro -mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro -mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro -mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro -mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro -mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro -mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro -mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro -mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro -mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro -mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro -mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER0_LO = 0x3100 # macro -mmPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER0_HI = 0x3101 # macro -mmPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER1_LO = 0x3102 # macro -mmPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER1_HI = 0x3103 # macro -mmPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER2_LO = 0x3104 # macro -mmPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER2_HI = 0x3105 # macro -mmPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER3_LO = 0x3106 # macro -mmPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER3_HI = 0x3107 # macro -mmPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER0_LO = 0x3140 # macro -mmPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER0_HI = 0x3141 # macro -mmPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER1_LO = 0x3142 # macro -mmPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER1_HI = 0x3143 # macro -mmPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER2_LO = 0x3144 # macro -mmPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER2_HI = 0x3145 # macro -mmPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER3_LO = 0x3146 # macro -mmPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER3_HI = 0x3147 # macro -mmPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER4_LO = 0x3148 # macro -mmPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER4_HI = 0x3149 # macro -mmPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER5_LO = 0x314a # macro -mmPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER5_HI = 0x314b # macro -mmPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER6_LO = 0x314c # macro -mmPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER6_HI = 0x314d # macro -mmPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER7_LO = 0x314e # macro -mmPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER7_HI = 0x314f # macro -mmPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER0_HI = 0x3180 # macro -mmSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER0_LO = 0x3181 # macro -mmSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER1_HI = 0x3182 # macro -mmSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER1_LO = 0x3183 # macro -mmSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER2_HI = 0x3184 # macro -mmSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER2_LO = 0x3185 # macro -mmSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER3_HI = 0x3186 # macro -mmSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER3_LO = 0x3187 # macro -mmSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER4_HI = 0x3188 # macro -mmSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER4_LO = 0x3189 # macro -mmSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER5_HI = 0x318a # macro -mmSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER5_LO = 0x318b # macro -mmSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER0_LO = 0x31c0 # macro -mmSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER0_HI = 0x31c1 # macro -mmSQ_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER1_LO = 0x31c2 # macro -mmSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER1_HI = 0x31c3 # macro -mmSQ_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER2_LO = 0x31c4 # macro -mmSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER2_HI = 0x31c5 # macro -mmSQ_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER3_LO = 0x31c6 # macro -mmSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER3_HI = 0x31c7 # macro -mmSQ_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER4_LO = 0x31c8 # macro -mmSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER4_HI = 0x31c9 # macro -mmSQ_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER5_LO = 0x31ca # macro -mmSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER5_HI = 0x31cb # macro -mmSQ_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER6_LO = 0x31cc # macro -mmSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER6_HI = 0x31cd # macro -mmSQ_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER7_LO = 0x31ce # macro -mmSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER7_HI = 0x31cf # macro -mmSQ_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER8_LO = 0x31d0 # macro -mmSQ_PERFCOUNTER8_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER8_HI = 0x31d1 # macro -mmSQ_PERFCOUNTER8_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER9_LO = 0x31d2 # macro -mmSQ_PERFCOUNTER9_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER9_HI = 0x31d3 # macro -mmSQ_PERFCOUNTER9_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER10_LO = 0x31d4 # macro -mmSQ_PERFCOUNTER10_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER10_HI = 0x31d5 # macro -mmSQ_PERFCOUNTER10_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER11_LO = 0x31d6 # macro -mmSQ_PERFCOUNTER11_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER11_HI = 0x31d7 # macro -mmSQ_PERFCOUNTER11_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER12_LO = 0x31d8 # macro -mmSQ_PERFCOUNTER12_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER12_HI = 0x31d9 # macro -mmSQ_PERFCOUNTER12_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER13_LO = 0x31da # macro -mmSQ_PERFCOUNTER13_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER13_HI = 0x31db # macro -mmSQ_PERFCOUNTER13_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER14_LO = 0x31dc # macro -mmSQ_PERFCOUNTER14_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER14_HI = 0x31dd # macro -mmSQ_PERFCOUNTER14_HI_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER15_LO = 0x31de # macro -mmSQ_PERFCOUNTER15_LO_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER15_HI = 0x31df # macro -mmSQ_PERFCOUNTER15_HI_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER0_LO = 0x3240 # macro -mmSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER0_HI = 0x3241 # macro -mmSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER1_LO = 0x3242 # macro -mmSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER1_HI = 0x3243 # macro -mmSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER2_LO = 0x3244 # macro -mmSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER2_HI = 0x3245 # macro -mmSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER3_LO = 0x3246 # macro -mmSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER3_HI = 0x3247 # macro -mmSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER2_LO = 0x3260 # macro -mmGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER2_HI = 0x3261 # macro -mmGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER_LO = 0x3262 # macro -mmGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER_HI = 0x3263 # macro -mmGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER0_LO = 0x3280 # macro -mmGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER0_HI = 0x3281 # macro -mmGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER1_LO = 0x3282 # macro -mmGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER1_HI = 0x3283 # macro -mmGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER2_LO = 0x3284 # macro -mmGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER2_HI = 0x3285 # macro -mmGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER3_LO = 0x3286 # macro -mmGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER3_HI = 0x3287 # macro -mmGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER0_LO = 0x32c0 # macro -mmTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER0_HI = 0x32c1 # macro -mmTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER1_LO = 0x32c2 # macro -mmTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER1_HI = 0x32c3 # macro -mmTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER0_LO = 0x3300 # macro -mmTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER0_HI = 0x3301 # macro -mmTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER1_LO = 0x3302 # macro -mmTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER1_HI = 0x3303 # macro -mmTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER0_LO = 0x3340 # macro -mmTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER0_HI = 0x3341 # macro -mmTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER1_LO = 0x3342 # macro -mmTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER1_HI = 0x3343 # macro -mmTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER2_LO = 0x3344 # macro -mmTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER2_HI = 0x3345 # macro -mmTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER3_LO = 0x3346 # macro -mmTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER3_HI = 0x3347 # macro -mmTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER0_LO = 0x3380 # macro -mmGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER0_HI = 0x3381 # macro -mmGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER1_LO = 0x3382 # macro -mmGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER1_HI = 0x3383 # macro -mmGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER2_LO = 0x3384 # macro -mmGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER2_HI = 0x3385 # macro -mmGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER3_LO = 0x3386 # macro -mmGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER3_HI = 0x3387 # macro -mmGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER0_LO = 0x3390 # macro -mmGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER0_HI = 0x3391 # macro -mmGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER1_LO = 0x3392 # macro -mmGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER1_HI = 0x3393 # macro -mmGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER2_LO = 0x3394 # macro -mmGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER2_HI = 0x3395 # macro -mmGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER3_LO = 0x3396 # macro -mmGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER3_HI = 0x3397 # macro -mmGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER0_LO = 0x33a0 # macro -mmGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER0_HI = 0x33a1 # macro -mmGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER1_LO = 0x33a2 # macro -mmGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER1_HI = 0x33a3 # macro -mmGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER2_LO = 0x33a4 # macro -mmGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER2_HI = 0x33a5 # macro -mmGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER3_LO = 0x33a6 # macro -mmGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER3_HI = 0x33a7 # macro -mmGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER0_LO = 0x33c0 # macro -mmCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER0_HI = 0x33c1 # macro -mmCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER1_LO = 0x33c2 # macro -mmCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER1_HI = 0x33c3 # macro -mmCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER2_LO = 0x33c4 # macro -mmCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER2_HI = 0x33c5 # macro -mmCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER3_LO = 0x33c6 # macro -mmCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER3_HI = 0x33c7 # macro -mmCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER0_LO = 0x33c8 # macro -mmCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER0_HI = 0x33c9 # macro -mmCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER1_LO = 0x33ca # macro -mmCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER1_HI = 0x33cb # macro -mmCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER2_LO = 0x33cc # macro -mmCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER2_HI = 0x33cd # macro -mmCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER3_LO = 0x33ce # macro -mmCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER3_HI = 0x33cf # macro -mmCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER0_LO = 0x3406 # macro -mmCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER0_HI = 0x3407 # macro -mmCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER1_LO = 0x3408 # macro -mmCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER1_HI = 0x3409 # macro -mmCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER2_LO = 0x340a # macro -mmCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER2_HI = 0x340b # macro -mmCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER3_LO = 0x340c # macro -mmCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER3_HI = 0x340d # macro -mmCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER0_LO = 0x3440 # macro -mmDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER0_HI = 0x3441 # macro -mmDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER1_LO = 0x3442 # macro -mmDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER1_HI = 0x3443 # macro -mmDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER2_LO = 0x3444 # macro -mmDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER2_HI = 0x3445 # macro -mmDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER3_LO = 0x3446 # macro -mmDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER3_HI = 0x3447 # macro -mmDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER0_LO = 0x3480 # macro -mmRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER0_HI = 0x3481 # macro -mmRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER1_LO = 0x3482 # macro -mmRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER1_HI = 0x3483 # macro -mmRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER0_LO = 0x34c0 # macro -mmRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER0_HI = 0x34c1 # macro -mmRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER1_LO = 0x34c2 # macro -mmRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER1_HI = 0x34c3 # macro -mmRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER2_LO = 0x34c4 # macro -mmRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER2_HI = 0x34c5 # macro -mmRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER3_LO = 0x34c6 # macro -mmRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER3_HI = 0x34c7 # macro -mmRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER0_LO = 0x351c # macro -mmUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER0_HI = 0x351d # macro -mmUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER1_LO = 0x351e # macro -mmUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER1_HI = 0x351f # macro -mmUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER0_LO = 0x3520 # macro -mmGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER0_HI = 0x3521 # macro -mmGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER1_LO = 0x3522 # macro -mmGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER1_HI = 0x3523 # macro -mmGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER0_LO = 0x3580 # macro -mmPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER0_HI = 0x3581 # macro -mmPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER1_LO = 0x3582 # macro -mmPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER1_HI = 0x3583 # macro -mmPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER2_LO = 0x3584 # macro -mmPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER2_HI = 0x3585 # macro -mmPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER3_LO = 0x3586 # macro -mmPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER3_HI = 0x3587 # macro -mmPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER4_LO = 0x3588 # macro -mmPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER4_HI = 0x3589 # macro -mmPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER5_LO = 0x358a # macro -mmPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER5_HI = 0x358b # macro -mmPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER6_LO = 0x358c # macro -mmPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER6_HI = 0x358d # macro -mmPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER7_LO = 0x358e # macro -mmPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER7_HI = 0x358f # macro -mmPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER0_LO = 0x35c0 # macro -mmGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER0_HI = 0x35c1 # macro -mmGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER1_LO = 0x35c2 # macro -mmGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER1_HI = 0x35c3 # macro -mmGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER2_LO = 0x35c4 # macro -mmGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER2_HI = 0x35c5 # macro -mmGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER3_LO = 0x35c6 # macro -mmGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER3_HI = 0x35c7 # macro -mmGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER0_LO = 0x3600 # macro -mmCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER0_HI = 0x3601 # macro -mmCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER1_LO = 0x3602 # macro -mmCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER1_HI = 0x3603 # macro -mmCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER2_LO = 0x3604 # macro -mmCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER2_HI = 0x3605 # macro -mmCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER3_LO = 0x3606 # macro -mmCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER3_HI = 0x3607 # macro -mmCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER2_LO = 0x3640 # macro -mmGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER2_HI = 0x3641 # macro -mmGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER_LO = 0x3642 # macro -mmGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER_HI = 0x3643 # macro -mmGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER_LO = 0x34e8 # macro -mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER_HI = 0x34e9 # macro -mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER_LO = 0x34ea # macro -mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER_HI = 0x34eb # macro -mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_0_LO = 0x34f8 # macro -mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_1_LO = 0x34f9 # macro -mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_0_HI = 0x34fa # macro -mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_1_HI = 0x34fb # macro -mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER0_LO = 0x3662 # macro -mmSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER0_HI = 0x3663 # macro -mmSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER1_LO = 0x3664 # macro -mmSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER1_HI = 0x3665 # macro -mmSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro -mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro -mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER0_LO = 0x366e # macro -mmSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER0_HI = 0x366f # macro -mmSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER1_LO = 0x3670 # macro -mmSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER1_HI = 0x3671 # macro -mmSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_PERFCOUNTER_LO = 0x3678 # macro -mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_PERFCOUNTER_HI = 0x3679 # macro -mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER0_LO = 0x367a # macro -mmSDMA2_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER0_HI = 0x367b # macro -mmSDMA2_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER1_LO = 0x367c # macro -mmSDMA2_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER1_HI = 0x367d # macro -mmSDMA2_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_LO = 0x3684 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_HI = 0x3685 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER0_LO = 0x3686 # macro -mmSDMA3_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER0_HI = 0x3687 # macro -mmSDMA3_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER1_LO = 0x3688 # macro -mmSDMA3_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER1_HI = 0x3689 # macro -mmSDMA3_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER1_SELECT = 0x3800 # macro -mmCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro -mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCPG_PERFCOUNTER0_SELECT = 0x3802 # macro -mmCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER1_SELECT = 0x3803 # macro -mmCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro -mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER1_SELECT = 0x3805 # macro -mmCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro -mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCPF_PERFCOUNTER0_SELECT = 0x3807 # macro -mmCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCP_PERFMON_CNTL = 0x3808 # macro -mmCP_PERFMON_CNTL_BASE_IDX = 1 # macro -mmCPC_PERFCOUNTER0_SELECT = 0x3809 # macro -mmCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro -mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -mmCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro -mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -mmCPF_LATENCY_STATS_SELECT = 0x380c # macro -mmCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -mmCPG_LATENCY_STATS_SELECT = 0x380d # macro -mmCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -mmCPC_LATENCY_STATS_SELECT = 0x380e # macro -mmCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -mmCP_DRAW_OBJECT = 0x3810 # macro -mmCP_DRAW_OBJECT_BASE_IDX = 1 # macro -mmCP_DRAW_OBJECT_COUNTER = 0x3811 # macro -mmCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro -mmCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro -mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro -mmCP_DRAW_WINDOW_HI = 0x3813 # macro -mmCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro -mmCP_DRAW_WINDOW_LO = 0x3814 # macro -mmCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro -mmCP_DRAW_WINDOW_CNTL = 0x3815 # macro -mmCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro -mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro -mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro -mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -mmGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro -mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -mmGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro -mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -mmGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro -mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro -mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro -mmGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro -mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro -mmGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro -mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro -mmGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro -mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro -mmGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro -mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER3_SELECT = 0x38aa # macro -mmGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro -mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro -mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro -mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro -mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro -mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro -mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro -mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro -mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro -mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro -mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro -mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro -mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro -mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro -mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro -mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro -mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro -mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro -mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro -mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro -mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro -mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro -mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro -mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro -mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro -mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro -mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro -mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro -mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro -mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro -mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro -mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro -mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro -mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -mmPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro -mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER0_SELECT = 0x3980 # macro -mmSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER1_SELECT = 0x3981 # macro -mmSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER2_SELECT = 0x3982 # macro -mmSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER3_SELECT = 0x3983 # macro -mmSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro -mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro -mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro -mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro -mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER4_SELECT = 0x3988 # macro -mmSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER5_SELECT = 0x3989 # macro -mmSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -mmSPI_PERFCOUNTER_BINS = 0x398a # macro -mmSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro -mmSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro -mmSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro -mmSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro -mmSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro -mmSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro -mmSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro -mmSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro -mmSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro -mmSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro -mmSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER10_SELECT = 0x39ca # macro -mmSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER11_SELECT = 0x39cb # macro -mmSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER12_SELECT = 0x39cc # macro -mmSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER13_SELECT = 0x39cd # macro -mmSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER14_SELECT = 0x39ce # macro -mmSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER15_SELECT = 0x39cf # macro -mmSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER_CTRL = 0x39e0 # macro -mmSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro -mmSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro -mmSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro -mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro -mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro -mmGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro -mmGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro -mmGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro -mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER0_SELECT = 0x3a40 # macro -mmSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER1_SELECT = 0x3a41 # macro -mmSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER2_SELECT = 0x3a42 # macro -mmSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER3_SELECT = 0x3a43 # macro -mmSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro -mmSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro -mmSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro -mmGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro -mmGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro -mmGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro -mmGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro -mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro -mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro -mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro -mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro -mmTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro -mmTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro -mmTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER0_SELECT = 0x3b00 # macro -mmTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro -mmTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmTD_PERFCOUNTER1_SELECT = 0x3b02 # macro -mmTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro -mmTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro -mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro -mmTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro -mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro -mmTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro -mmTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro -mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro -mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro -mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro -mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro -mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro -mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro -mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro -mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro -mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro -mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro -mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro -mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro -mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro -mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro -mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro -mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro -mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro -mmCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro -mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro -mmCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro -mmCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro -mmCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro -mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro -mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro -mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro -mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro -mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER_FILTER = 0x3c00 # macro -mmCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER0_SELECT = 0x3c01 # macro -mmCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro -mmCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER1_SELECT = 0x3c03 # macro -mmCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER2_SELECT = 0x3c04 # macro -mmCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmCB_PERFCOUNTER3_SELECT = 0x3c05 # macro -mmCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER0_SELECT = 0x3c40 # macro -mmDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro -mmDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER1_SELECT = 0x3c42 # macro -mmDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro -mmDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER2_SELECT = 0x3c44 # macro -mmDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmDB_PERFCOUNTER3_SELECT = 0x3c46 # macro -mmDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_CNTL = 0x3c80 # macro -mmRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro -mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro -mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro -mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c84 # macro -mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_RING_RDPTR = 0x3c85 # macro -mmRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro -mmRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro -mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro -mmRLC_SPM_SE_MUXSEL_ADDR = 0x3c87 # macro -mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_SE_MUXSEL_DATA = 0x3c88 # macro -mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c89 # macro -mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c8a # macro -mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_DESER_START_SKEW = 0x3c8b # macro -mmRLC_SPM_DESER_START_SKEW_BASE_IDX = 1 # macro -mmRLC_SPM_GLOBALS_SAMPLE_SKEW = 0x3c8c # macro -mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX = 1 # macro -mmRLC_SPM_GLOBALS_MUXSEL_SKEW = 0x3c8d # macro -mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX = 1 # macro -mmRLC_SPM_SE_SAMPLE_SKEW = 0x3c8e # macro -mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX = 1 # macro -mmRLC_SPM_SE_MUXSEL_SKEW = 0x3c8f # macro -mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX = 1 # macro -mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR = 0x3c90 # macro -mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA = 0x3c91 # macro -mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR = 0x3c92 # macro -mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA = 0x3c93 # macro -mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_RING_WRPTR = 0x3c94 # macro -mmRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c95 # macro -mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_DATARAM_DATA = 0x3c96 # macro -mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c97 # macro -mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c98 # macro -mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_STATUS = 0x3c99 # macro -mmRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_CTRL = 0x3c9a # macro -mmRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_MODE = 0x3c9b # macro -mmRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro -mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro -mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro -mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE = 0x3c9f # macro -mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE = 0x3ca0 # macro -mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_VIRT_CTRL = 0x3ca1 # macro -mmRLC_SPM_VIRT_CTRL_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE = 0x3ca2 # macro -mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_VIRT_STATUS = 0x3ca3 # macro -mmRLC_SPM_VIRT_STATUS_BASE_IDX = 1 # macro -mmRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca4 # macro -mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro -mmRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca5 # macro -mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE = 0x3ca6 # macro -mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET = 0x3ca7 # macro -mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro -mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET = 0x3ca8 # macro -mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3ca9 # macro -mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3caa # macro -mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3cab # macro -mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro -mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE = 0x3cac # macro -mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro -mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3cad # macro -mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro -mmRLC_PERFMON_CNTL = 0x3cc0 # macro -mmRLC_PERFMON_CNTL_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro -mmRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro -mmRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro -mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro -mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro -mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro -mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro -mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro -mmRLC_PERFMON_CLK_CNTL = 0x3ce4 # macro -mmRLC_PERFMON_CLK_CNTL_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro -mmRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro -mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro -mmRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro -mmRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro -mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro -mmRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmRMI_PERF_COUNTER_CNTL = 0x3d06 # macro -mmRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro -mmGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro -mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro -mmGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER0_SELECT = 0x3d63 # macro -mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmUTCL1_PERFCOUNTER1_SELECT = 0x3d64 # macro -mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro -mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro -mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro -mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro -mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro -mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro -mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro -mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro -mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro -mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro -mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro -mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro -mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro -mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro -mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro -mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro -mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro -mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro -mmCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro -mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro -mmCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro -mmCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro -mmCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro -mmGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro -mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER2_MODE = 0x3e02 # macro -mmGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER0_CFG = 0x3e03 # macro -mmGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER1_CFG = 0x3e04 # macro -mmGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro -mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d2c # macro -mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d2d # macro -mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d2e # macro -mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d2f # macro -mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d30 # macro -mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d31 # macro -mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d32 # macro -mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d33 # macro -mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro -mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d34 # macro -mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER0_CFG = 0x3d35 # macro -mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER1_CFG = 0x3d36 # macro -mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER2_CFG = 0x3d37 # macro -mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER3_CFG = 0x3d38 # macro -mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -mmGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d39 # macro -mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_0_SELECT = 0x3d3c # macro -mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_1_SELECT = 0x3d3d # macro -mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d3e # macro -mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d3f # macro -mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_0_MODE = 0x3d40 # macro -mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro -mmGCVML2_PERFCOUNTER2_1_MODE = 0x3d41 # macro -mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro -mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro -mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro -mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro -mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro -mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro -mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro -mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro -mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro -mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro -mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro -mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro -mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro -mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro -mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro -mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro -mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_PERFCOUNTER0_CFG = 0x3e38 # macro -mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_PERFCOUNTER1_CFG = 0x3e39 # macro -mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e3a # macro -mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmSDMA2_PERFCNT_MISC_CNTL = 0x3e3b # macro -mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER0_SELECT = 0x3e3c # macro -mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER0_SELECT1 = 0x3e3d # macro -mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER1_SELECT = 0x3e3e # macro -mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSDMA2_PERFCOUNTER1_SELECT1 = 0x3e3f # macro -mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_PERFCOUNTER0_CFG = 0x3e44 # macro -mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_PERFCOUNTER1_CFG = 0x3e45 # macro -mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e46 # macro -mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -mmSDMA3_PERFCNT_MISC_CNTL = 0x3e47 # macro -mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER0_SELECT = 0x3e48 # macro -mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER0_SELECT1 = 0x3e49 # macro -mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER1_SELECT = 0x3e4a # macro -mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -mmSDMA3_PERFCOUNTER1_SELECT1 = 0x3e4b # macro -mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -mmGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -mmRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -mmGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -mmRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -mmGRTAVFS_GENERAL_0 = 0x4b02 # macro -mmGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro -mmGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro -mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro -mmGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro -mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro -mmGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro -mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro -mmGRTAVFS_TARG_FREQ = 0x4b06 # macro -mmGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro -mmGRTAVFS_TARG_VOLT = 0x4b07 # macro -mmGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro -mmGRTAVFS_SOFT_RESET = 0x4b0f # macro -mmGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro -mmGRTAVFS_PSM_CNTL = 0x4b10 # macro -mmGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro -mmGRTAVFS_CLK_CNTL = 0x4b11 # macro -mmGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro -mmRLC_CNTL = 0x4c00 # macro -mmRLC_CNTL_BASE_IDX = 1 # macro -mmRLC_F32_UCODE_VERSION = 0x4c03 # macro -mmRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro -mmRLC_STAT = 0x4c04 # macro -mmRLC_STAT_BASE_IDX = 1 # macro -mmRLC_MEM_SLP_CNTL = 0x4c06 # macro -mmRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro -mmSMU_RLC_RESPONSE = 0x4c07 # macro -mmSMU_RLC_RESPONSE_BASE_IDX = 1 # macro -mmRLC_RLCV_SAFE_MODE = 0x4c08 # macro -mmRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro -mmRLC_SMU_SAFE_MODE = 0x4c09 # macro -mmRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro -mmRLC_RLCV_COMMAND = 0x4c0a # macro -mmRLC_RLCV_COMMAND_BASE_IDX = 1 # macro -mmRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro -mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro -mmRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro -mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_INT_0 = 0x4c0e # macro -mmRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_INT_1 = 0x4c0f # macro -mmRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_INT_2 = 0x4c10 # macro -mmRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_CTRL = 0x4c11 # macro -mmRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_MAX_1 = 0x4c12 # macro -mmRLC_LB_CNTR_MAX_1_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_STAT = 0x4c13 # macro -mmRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_INT_3 = 0x4c15 # macro -mmRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro -mmRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro -mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -mmRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro -mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro -mmRLC_INT_STAT = 0x4c18 # macro -mmRLC_INT_STAT_BASE_IDX = 1 # macro -mmRLC_LB_CNTL = 0x4c19 # macro -mmRLC_LB_CNTL_BASE_IDX = 1 # macro -mmRLC_MGCG_CTRL = 0x4c1a # macro -mmRLC_MGCG_CTRL_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_INIT_1 = 0x4c1b # macro -mmRLC_LB_CNTR_INIT_1_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_1 = 0x4c1c # macro -mmRLC_LB_CNTR_1_BASE_IDX = 1 # macro -mmRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro -mmRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro -mmRLC_PG_DELAY_2 = 0x4c1f # macro -mmRLC_PG_DELAY_2_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro -mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro -mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro -mmRLC_UCODE_CNTL = 0x4c27 # macro -mmRLC_UCODE_CNTL_BASE_IDX = 1 # macro -mmRLC_GPM_THREAD_RESET = 0x4c28 # macro -mmRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro -mmRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro -mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro -mmRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro -mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_INIT_2 = 0x4c2b # macro -mmRLC_LB_CNTR_INIT_2_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_MAX_2 = 0x4c2c # macro -mmRLC_LB_CNTR_MAX_2_BASE_IDX = 1 # macro -mmRLC_LB_CONFIG_5 = 0x4c2e # macro -mmRLC_LB_CONFIG_5_BASE_IDX = 1 # macro -mmRLC_GPM_TIMER_INT_4 = 0x4c2f # macro -mmRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro -mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro -mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro -mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro -mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_CTRL = 0x4c34 # macro -mmRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro -mmRLC_CLK_COUNT_STAT = 0x4c35 # macro -mmRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro -mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro -mmRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro -mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro -mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro -mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro -mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro -mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro -mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro -mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro -mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro -mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_32 = 0x4c42 # macro -mmRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro -mmRLC_PG_CNTL = 0x4c43 # macro -mmRLC_PG_CNTL_BASE_IDX = 1 # macro -mmRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro -mmRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro -mmRLC_GPM_THREAD_ENABLE = 0x4c45 # macro -mmRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro -mmRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro -mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro -mmRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro -mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro -mmRLC_CGCG_CGLS_CTRL = 0x4c49 # macro -mmRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro -mmRLC_CGCG_RAMP_CTRL = 0x4c4a # macro -mmRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro -mmRLC_DYN_PG_STATUS = 0x4c4b # macro -mmRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro -mmRLC_DYN_PG_REQUEST = 0x4c4c # macro -mmRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro -mmRLC_PG_DELAY = 0x4c4d # macro -mmRLC_PG_DELAY_BASE_IDX = 1 # macro -mmRLC_WGP_STATUS = 0x4c4e # macro -mmRLC_WGP_STATUS_BASE_IDX = 1 # macro -mmRLC_LB_INIT_WGP_MASK = 0x4c4f # macro -mmRLC_LB_INIT_WGP_MASK_BASE_IDX = 1 # macro -mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK = 0x4c50 # macro -mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX = 1 # macro -mmRLC_LB_PARAMS = 0x4c51 # macro -mmRLC_LB_PARAMS_BASE_IDX = 1 # macro -mmRLC_LB_DELAY = 0x4c52 # macro -mmRLC_LB_DELAY_BASE_IDX = 1 # macro -mmRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro -mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro -mmRLC_MAX_PG_WGP = 0x4c54 # macro -mmRLC_MAX_PG_WGP_BASE_IDX = 1 # macro -mmRLC_AUTO_PG_CTRL = 0x4c55 # macro -mmRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro -mmRLC_SMU_GRBM_REG_SAVE_CTRL = 0x4c56 # macro -mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX = 1 # macro -mmRLC_SERDES_RD_INDEX = 0x4c59 # macro -mmRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro -mmRLC_SERDES_RD_DATA_0 = 0x4c5a # macro -mmRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro -mmRLC_SERDES_RD_DATA_1 = 0x4c5b # macro -mmRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro -mmRLC_SERDES_RD_DATA_2 = 0x4c5c # macro -mmRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro -mmRLC_SERDES_RD_DATA_3 = 0x4c5d # macro -mmRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro -mmRLC_SERDES_MASK = 0x4c5e # macro -mmRLC_SERDES_MASK_BASE_IDX = 1 # macro -mmRLC_SERDES_CTRL = 0x4c5f # macro -mmRLC_SERDES_CTRL_BASE_IDX = 1 # macro -mmRLC_SERDES_DATA = 0x4c60 # macro -mmRLC_SERDES_DATA_BASE_IDX = 1 # macro -mmRLC_SERDES_BUSY = 0x4c61 # macro -mmRLC_SERDES_BUSY_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_0 = 0x4c63 # macro -mmRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_1 = 0x4c64 # macro -mmRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_2 = 0x4c65 # macro -mmRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_3 = 0x4c66 # macro -mmRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_4 = 0x4c67 # macro -mmRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_5 = 0x4c68 # macro -mmRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_6 = 0x4c69 # macro -mmRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_7 = 0x4c6a # macro -mmRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro -mmRLC_STATIC_PG_STATUS = 0x4c6e # macro -mmRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro -mmRLC_SPM_INT_INFO_1 = 0x4c6f # macro -mmRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro -mmRLC_SPM_INT_INFO_2 = 0x4c70 # macro -mmRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro -mmRLC_SPM_MC_CNTL = 0x4c71 # macro -mmRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro -mmRLC_SPM_INT_CNTL = 0x4c72 # macro -mmRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro -mmRLC_SPM_INT_STATUS = 0x4c73 # macro -mmRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro -mmRLC_SMU_MESSAGE = 0x4c76 # macro -mmRLC_SMU_MESSAGE_BASE_IDX = 1 # macro -mmRLC_GPM_LOG_SIZE = 0x4c77 # macro -mmRLC_GPM_LOG_SIZE_BASE_IDX = 1 # macro -mmRLC_PG_DELAY_3 = 0x4c78 # macro -mmRLC_PG_DELAY_3_BASE_IDX = 1 # macro -mmRLC_GPR_REG1 = 0x4c79 # macro -mmRLC_GPR_REG1_BASE_IDX = 1 # macro -mmRLC_GPR_REG2 = 0x4c7a # macro -mmRLC_GPR_REG2_BASE_IDX = 1 # macro -mmRLC_GPM_LOG_CONT = 0x4c7b # macro -mmRLC_GPM_LOG_CONT_BASE_IDX = 1 # macro -mmRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro -mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro -mmRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro -mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -mmRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro -mmRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro -mmRLC_SRM_CNTL = 0x4c80 # macro -mmRLC_SRM_CNTL_BASE_IDX = 1 # macro -mmRLC_SRM_GPM_COMMAND = 0x4c87 # macro -mmRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro -mmRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro -mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro -mmRLC_SRM_RLCV_COMMAND = 0x4c89 # macro -mmRLC_SRM_RLCV_COMMAND_BASE_IDX = 1 # macro -mmRLC_SRM_RLCV_COMMAND_STATUS = 0x4c8a # macro -mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro -mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro -mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro -mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro -mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro -mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro -mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro -mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro -mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro -mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro -mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro -mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro -mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro -mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro -mmRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro -mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro -mmRLC_SRM_STAT = 0x4c9b # macro -mmRLC_SRM_STAT_BASE_IDX = 1 # macro -mmRLC_SRM_GPM_ABORT = 0x4c9c # macro -mmRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro -mmRLC_SPARE_INT_2 = 0x4c9d # macro -mmRLC_SPARE_INT_2_BASE_IDX = 1 # macro -mmRLC_RLCV_SPARE_INT_1 = 0x4c9e # macro -mmRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro -mmRLC_PACE_SPARE_INT_1 = 0x4c9f # macro -mmRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro -mmRLC_SAFE_MODE = 0x4ca0 # macro -mmRLC_SAFE_MODE_BASE_IDX = 1 # macro -mmRLC_CP_SCHEDULERS = 0x4ca1 # macro -mmRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro -mmRLC_CSIB_ADDR_LO = 0x4ca2 # macro -mmRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro -mmRLC_CSIB_ADDR_HI = 0x4ca3 # macro -mmRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro -mmRLC_CSIB_LENGTH = 0x4ca4 # macro -mmRLC_CSIB_LENGTH_BASE_IDX = 1 # macro -mmRLC_SPARE_INT_0 = 0x4ca5 # macro -mmRLC_SPARE_INT_0_BASE_IDX = 1 # macro -mmRLC_CP_EOF_INT_CNT = 0x4ca6 # macro -mmRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro -mmRLC_CP_EOF_INT = 0x4ca7 # macro -mmRLC_CP_EOF_INT_BASE_IDX = 1 # macro -mmRLC_SMU_COMMAND = 0x4ca9 # macro -mmRLC_SMU_COMMAND_BASE_IDX = 1 # macro -mmRLC_SMU_ARGUMENT_1 = 0x4cab # macro -mmRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro -mmRLC_SMU_ARGUMENT_2 = 0x4cac # macro -mmRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_8 = 0x4cad # macro -mmRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_9 = 0x4cae # macro -mmRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_10 = 0x4caf # macro -mmRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_11 = 0x4cb0 # macro -mmRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_12 = 0x4cb1 # macro -mmRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro -mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro -mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro -mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro -mmRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro -mmRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro -mmRLC_UTCL1_STATUS_2 = 0x4cb6 # macro -mmRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro -mmRLC_LB_CONFIG_2 = 0x4cb8 # macro -mmRLC_LB_CONFIG_2_BASE_IDX = 1 # macro -mmRLC_LB_CONFIG_3 = 0x4cb9 # macro -mmRLC_LB_CONFIG_3_BASE_IDX = 1 # macro -mmRLC_LB_CONFIG_4 = 0x4cba # macro -mmRLC_LB_CONFIG_4_BASE_IDX = 1 # macro -mmRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro -mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro -mmRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro -mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro -mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro -mmRLC_LB_CONFIG_1 = 0x4cbf # macro -mmRLC_LB_CONFIG_1_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro -mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro -mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro -mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro -mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro -mmRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro -mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro -mmRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro -mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro -mmRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro -mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro -mmRLC_SEMAPHORE_0 = 0x4cc7 # macro -mmRLC_SEMAPHORE_0_BASE_IDX = 1 # macro -mmRLC_SEMAPHORE_1 = 0x4cc8 # macro -mmRLC_SEMAPHORE_1_BASE_IDX = 1 # macro -mmRLC_PACE_INT_STAT = 0x4ccc # macro -mmRLC_PACE_INT_STAT_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_CNTL = 0x4ccd # macro -mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_TRIG = 0x4cce # macro -mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_ADDR_LSB = 0x4ccf # macro -mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_ADDR_MSB = 0x4cd0 # macro -mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_SIZE_LSB = 0x4cd1 # macro -mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX = 1 # macro -mmRLC_PREWALKER_UTCL1_SIZE_MSB = 0x4cd2 # macro -mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX = 1 # macro -mmRLC_UTCL1_STATUS = 0x4cd4 # macro -mmRLC_UTCL1_STATUS_BASE_IDX = 1 # macro -mmRLC_R2I_CNTL_0 = 0x4cd5 # macro -mmRLC_R2I_CNTL_0_BASE_IDX = 1 # macro -mmRLC_R2I_CNTL_1 = 0x4cd6 # macro -mmRLC_R2I_CNTL_1_BASE_IDX = 1 # macro -mmRLC_R2I_CNTL_2 = 0x4cd7 # macro -mmRLC_R2I_CNTL_2_BASE_IDX = 1 # macro -mmRLC_R2I_CNTL_3 = 0x4cd8 # macro -mmRLC_R2I_CNTL_3_BASE_IDX = 1 # macro -mmRLC_LB_WGP_STAT = 0x4cda # macro -mmRLC_LB_WGP_STAT_BASE_IDX = 1 # macro -mmRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro -mmRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_13 = 0x4cdd # macro -mmRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_14 = 0x4cde # macro -mmRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_15 = 0x4cdf # macro -mmRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro -mmRLC_SPARE_INT_1 = 0x4ce0 # macro -mmRLC_SPARE_INT_1_BASE_IDX = 1 # macro -mmRLC_SEMAPHORE_2 = 0x4ce3 # macro -mmRLC_SEMAPHORE_2_BASE_IDX = 1 # macro -mmRLC_SEMAPHORE_3 = 0x4ce4 # macro -mmRLC_SEMAPHORE_3_BASE_IDX = 1 # macro -mmRLC_SMU_ARGUMENT_3 = 0x4ce5 # macro -mmRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro -mmRLC_SMU_ARGUMENT_4 = 0x4ce6 # macro -mmRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4ce8 # macro -mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4ce9 # macro -mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro -mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro -mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro -mmRLC_PACE_INT_DISABLE = 0x4ced # macro -mmRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro -mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro -mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro -mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro -mmRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro -mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro -mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro -mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro -mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro -mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro -mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro -mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro -mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCV_SPARE_INT = 0x4d00 # macro -mmRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro -mmRLC_PACE_TIMER_INT_0 = 0x4d04 # macro -mmRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro -mmRLC_PACE_TIMER_CTRL = 0x4d05 # macro -mmRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro -mmRLC_PACE_TIMER_INT_1 = 0x4d06 # macro -mmRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro -mmRLC_PACE_SPARE_INT = 0x4d07 # macro -mmRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro -mmRLC_SMU_CLK_REQ = 0x4d08 # macro -mmRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro -mmRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro -mmRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro -mmRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro -mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro -mmRLC_CLK_STATUS = 0x4d0b # macro -mmRLC_CLK_STATUS_BASE_IDX = 1 # macro -mmRLC_SPP_CTRL = 0x4d0c # macro -mmRLC_SPP_CTRL_BASE_IDX = 1 # macro -mmRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro -mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro -mmRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro -mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro -mmRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro -mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro -mmRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro -mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro -mmRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro -mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro -mmRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro -mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro -mmRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro -mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro -mmRLC_GPM_GENERAL_16 = 0x4d14 # macro -mmRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro -mmRLC_SPP_PROF_INFO_1 = 0x4d18 # macro -mmRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro -mmRLC_SPP_PROF_INFO_2 = 0x4d19 # macro -mmRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro -mmRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro -mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro -mmRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro -mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro -mmRLC_SPP_STATUS = 0x4d1c # macro -mmRLC_SPP_STATUS_BASE_IDX = 1 # macro -mmRLC_SPP_PVT_STAT_0 = 0x4d1d # macro -mmRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro -mmRLC_SPP_PVT_STAT_1 = 0x4d1e # macro -mmRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro -mmRLC_SPP_PVT_STAT_2 = 0x4d1f # macro -mmRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro -mmRLC_SPP_PVT_STAT_3 = 0x4d20 # macro -mmRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro -mmRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro -mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro -mmRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro -mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro -mmRLC_SPP_PBB_INFO = 0x4d23 # macro -mmRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro -mmRLC_SPP_RESET = 0x4d24 # macro -mmRLC_SPP_RESET_BASE_IDX = 1 # macro -mmRLC_SPM_SAMPLE_CNT = 0x4d25 # macro -mmRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro -mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro -mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro -mmRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro -mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro -mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro -mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro -mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro -mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro -mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro -mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -mmRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro -mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -mmRLC_PCC_STRETCH_HYSTERESIS_CNTL = 0x4d44 # macro -mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX = 1 # macro -mmRLC_CAC_MASK_CNTL = 0x4d45 # macro -mmRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro -mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro -mmRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro -mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro -mmRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro -mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro -mmRLC_LB_CNTR_2 = 0x4de7 # macro -mmRLC_LB_CNTR_2_BASE_IDX = 1 # macro -mmRLC_CPAXI_DOORBELL_MON_CTRL = 0x4df1 # macro -mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX = 1 # macro -mmRLC_CPAXI_DOORBELL_MON_STAT = 0x4df2 # macro -mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX = 1 # macro -mmRLC_CPAXI_DOORBELL_MON_DATA_LSB = 0x4df3 # macro -mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX = 1 # macro -mmRLC_CPAXI_DOORBELL_MON_DATA_MSB = 0x4df4 # macro -mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_RANGE = 0x4df5 # macro -mmRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_CNTL = 0x4df6 # macro -mmRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_STAT = 0x4df7 # macro -mmRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro -mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro -mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro -mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro -mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro -mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro -mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro -mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -mmRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro -mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -mmRLC_SPP_CAM_ADDR = 0x4e00 # macro -mmRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SPP_CAM_DATA = 0x4e01 # macro -mmRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro -mmRLC_SPP_CAM_EXT_ADDR = 0x4e02 # macro -mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro -mmRLC_SPP_CAM_EXT_DATA = 0x4e03 # macro -mmRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro -mmRLC_PACE_SCRATCH_ADDR = 0x4e04 # macro -mmRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro -mmRLC_PACE_SCRATCH_DATA = 0x4e05 # macro -mmRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro -mmRLC_RLCS_DEC_START = 0x4e60 # macro -mmRLC_RLCS_DEC_START_BASE_IDX = 1 # macro -mmRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro -mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro -mmRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro -mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro -mmRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro -mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro -mmRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro -mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro -mmRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro -mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_6 = 0x4e66 # macro -mmRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_7 = 0x4e67 # macro -mmRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro -mmRLC_RLCS_CGCG_REQUEST = 0x4e68 # macro -mmRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro -mmRLC_RLCS_CGCG_STATUS = 0x4e69 # macro -mmRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_SMU_GFXCLK_STATUS = 0x4e6a # macro -mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_SMU_GFXCLK_CONTROL = 0x4e6b # macro -mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX = 1 # macro -mmRLC_RLCS_SOC_DS_CNTL = 0x4e6c # macro -mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_GFX_DS_CNTL = 0x4e6d # macro -mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro -mmRLC_GPM_STAT = 0x4e6e # macro -mmRLC_GPM_STAT_BASE_IDX = 1 # macro -mmRLC_RLCS_GPM_STAT = 0x4e6e # macro -mmRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro -mmRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6f # macro -mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro -mmRLC_RLCS_DIDT_FORCE_STALL = 0x4e70 # macro -mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro -mmRLC_RLCS_IOV_CMD_STATUS = 0x4e71 # macro -mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e72 # macro -mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro -mmRLC_RLCS_IOV_SCH_BLOCK = 0x4e73 # macro -mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -mmRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e74 # macro -mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_GPM_STAT_2 = 0x4e75 # macro -mmRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro -mmRLC_RLCS_GRBM_SOFT_RESET = 0x4e76 # macro -mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro -mmRLC_RLCS_PG_CHANGE_STATUS = 0x4e77 # macro -mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_PG_CHANGE_READ = 0x4e78 # macro -mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro -mmRLC_RLCS_LB_STATUS = 0x4e79 # macro -mmRLC_RLCS_LB_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_LB_READ = 0x4e7a # macro -mmRLC_RLCS_LB_READ_BASE_IDX = 1 # macro -mmRLC_RLCS_LB_CONTROL = 0x4e7b # macro -mmRLC_RLCS_LB_CONTROL_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_SEMAPHORE = 0x4e7c # macro -mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e7d # macro -mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_CTRL_1 = 0x4e7e # macro -mmRLC_RLCS_IH_CTRL_1_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_CTRL_2 = 0x4e7f # macro -mmRLC_RLCS_IH_CTRL_2_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_CTRL_3 = 0x4e80 # macro -mmRLC_RLCS_IH_CTRL_3_BASE_IDX = 1 # macro -mmRLC_RLCS_IH_STATUS = 0x4e81 # macro -mmRLC_RLCS_IH_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_WGP_STATUS = 0x4e82 # macro -mmRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_WGP_READ = 0x4e83 # macro -mmRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro -mmRLC_RLCS_CP_INT_CTRL_1 = 0x4e84 # macro -mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro -mmRLC_RLCS_CP_INT_CTRL_2 = 0x4e85 # macro -mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro -mmRLC_RLCS_CP_INT_INFO_1 = 0x4e86 # macro -mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro -mmRLC_RLCS_CP_INT_INFO_2 = 0x4e87 # macro -mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro -mmRLC_RLCS_SPM_INT_CTRL = 0x4e88 # macro -mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro -mmRLC_RLCS_SPM_INT_INFO_1 = 0x4e89 # macro -mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro -mmRLC_RLCS_SPM_INT_INFO_2 = 0x4e8a # macro -mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro -mmRLC_RLCS_DSM_TRIG = 0x4e8b # macro -mmRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro -mmRLC_RLCS_BOOTLOAD_STATUS = 0x4e8d # macro -mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro -mmRLC_RLCS_POWER_BRAKE_CNTL = 0x4e8e # macro -mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_0 = 0x4e8f # macro -mmRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_1 = 0x4e90 # macro -mmRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_2 = 0x4e91 # macro -mmRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_3 = 0x4e92 # macro -mmRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_4 = 0x4e93 # macro -mmRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro -mmRLC_RLCS_GENERAL_5 = 0x4e94 # macro -mmRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro -mmRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4ec1 # macro -mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro -mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4ec2 # macro -mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_CMP_IDLE_CNTL = 0x4ec3 # macro -mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4ec4 # macro -mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro -mmRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro -mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro -mmRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro -mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro -mmRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro -mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro -mmRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro -mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro -mmRLC_RLCS_SPM_SQTT_MODE = 0x4ee0 # macro -mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro -mmRLC_RLCS_CP_DMA_SRCID_OVER = 0x4ee4 # macro -mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro -mmRLC_RLCS_UTCL2_CNTL = 0x4ee6 # macro -mmRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL = 0x4ee8 # macro -mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX = 1 # macro -mmRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4eec # macro -mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro -mmRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4eed # macro -mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro -mmRLC_RLCS_SMUIO_VIDCHG_CTRL = 0x4eee # macro -mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro -mmRLC_RLCS_EDC_INT_CNTL = 0x4eef # macro -mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_KMD_LOG_CNTL1 = 0x4ef1 # macro -mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro -mmRLC_RLCS_KMD_LOG_CNTL2 = 0x4ef2 # macro -mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro -mmRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ef3 # macro -mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -mmRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ef4 # macro -mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -mmRLC_RLCS_SRM_SRCID_CNTL = 0x4efd # macro -mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro -mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4f03 # macro -mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro -mmRLC_RLCS_DEC_END = 0x4fff # macro -mmRLC_RLCS_DEC_END_BASE_IDX = 1 # macro -mmCGTS_RD_CTRL_REG = 0x5004 # macro -mmCGTS_RD_CTRL_REG_BASE_IDX = 1 # macro -mmCGTS_RD_REG = 0x5005 # macro -mmCGTS_RD_REG_BASE_IDX = 1 # macro -mmCGTS_TCC_DISABLE = 0x5006 # macro -mmCGTS_TCC_DISABLE_BASE_IDX = 1 # macro -mmCGTS_USER_TCC_DISABLE = 0x5007 # macro -mmCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro -mmCGTS_STATUS_REG = 0x5008 # macro -mmCGTS_STATUS_REG_BASE_IDX = 1 # macro -mmCGTT_SPI_CGTSSM_CLK_CTRL = 0x5009 # macro -mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SPI_PS_CLK_CTRL = 0x507d # macro -mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SPIS_CLK_CTRL = 0x507e # macro -mmCGTT_SPIS_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SPI_CLK_CTRL = 0x5080 # macro -mmCGTT_SPI_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_PC_CLK_CTRL = 0x5081 # macro -mmCGTT_PC_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_BCI_CLK_CTRL = 0x5082 # macro -mmCGTT_BCI_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_VGT_CLK_CTRL = 0x5084 # macro -mmCGTT_VGT_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_IA_CLK_CTRL = 0x5085 # macro -mmCGTT_IA_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_WD_CLK_CTRL = 0x5086 # macro -mmCGTT_WD_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro -mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_PA_CLK_CTRL = 0x5088 # macro -mmCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SC_CLK_CTRL0 = 0x5089 # macro -mmCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro -mmCGTT_SC_CLK_CTRL1 = 0x508a # macro -mmCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro -mmCGTT_SC_CLK_CTRL2 = 0x508b # macro -mmCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro -mmCGTT_SQ_CLK_CTRL = 0x508c # macro -mmCGTT_SQ_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SQG_CLK_CTRL = 0x508d # macro -mmCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro -mmSQ_ALU_CLK_CTRL = 0x508e # macro -mmSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro -mmSQ_TEX_CLK_CTRL = 0x508f # macro -mmSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro -mmSQ_LDS_CLK_CTRL = 0x5090 # macro -mmSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_SX_CLK_CTRL0 = 0x5094 # macro -mmCGTT_SX_CLK_CTRL0_BASE_IDX = 1 # macro -mmCGTT_SX_CLK_CTRL1 = 0x5095 # macro -mmCGTT_SX_CLK_CTRL1_BASE_IDX = 1 # macro -mmCGTT_SX_CLK_CTRL2 = 0x5096 # macro -mmCGTT_SX_CLK_CTRL2_BASE_IDX = 1 # macro -mmCGTT_SX_CLK_CTRL3 = 0x5097 # macro -mmCGTT_SX_CLK_CTRL3_BASE_IDX = 1 # macro -mmCGTT_SX_CLK_CTRL4 = 0x5098 # macro -mmCGTT_SX_CLK_CTRL4_BASE_IDX = 1 # macro -mmTD_CGTT_CTRL = 0x509c # macro -mmTD_CGTT_CTRL_BASE_IDX = 1 # macro -mmTA_CGTT_CTRL = 0x509d # macro -mmTA_CGTT_CTRL_BASE_IDX = 1 # macro -mmCGTT_TCPI_CLK_CTRL = 0x5109 # macro -mmCGTT_TCPI_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_GDS_CLK_CTRL = 0x50a0 # macro -mmCGTT_GDS_CLK_CTRL_BASE_IDX = 1 # macro -mmDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro -mmDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro -mmCB_CGTT_SCLK_CTRL = 0x50a8 # macro -mmCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -mmGL2C_CGTT_SCLK_CTRL = 0x50fc # macro -mmGL2C_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -mmGL2A_CGTT_SCLK_CTRL = 0x50ac # macro -mmGL2A_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -mmGL2A_CGTT_SCLK_CTRL_1 = 0x50ad # macro -mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX = 1 # macro -mmCGTT_CP_CLK_CTRL = 0x50b0 # macro -mmCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_CPF_CLK_CTRL = 0x50b1 # macro -mmCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_CPC_CLK_CTRL = 0x50b2 # macro -mmCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_RLC_CLK_CTRL = 0x50b5 # macro -mmCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro -mmRLC_GFX_RM_CNTL = 0x50b6 # macro -mmRLC_GFX_RM_CNTL_BASE_IDX = 1 # macro -mmRMI_CGTT_SCLK_CTRL = 0x50c0 # macro -mmRMI_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_TCPF_CLK_CTRL = 0x5111 # macro -mmCGTT_TCPF_CLK_CTRL_BASE_IDX = 1 # macro -mmGCR_CGTT_SCLK_CTRL = 0x50c2 # macro -mmGCR_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -mmUTCL1_CGTT_CLK_CTRL = 0x50c3 # macro -mmUTCL1_CGTT_CLK_CTRL_BASE_IDX = 1 # macro -mmGCEA_CGTT_CLK_CTRL = 0x50c4 # macro -mmGCEA_CGTT_CLK_CTRL_BASE_IDX = 1 # macro -mmSE_CAC_CGTT_CLK_CTRL = 0x50d0 # macro -mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro -mmGC_CAC_CGTT_CLK_CTRL = 0x50d8 # macro -mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro -mmGRBM_CGTT_CLK_CNTL = 0x50e0 # macro -mmGRBM_CGTT_CLK_CNTL_BASE_IDX = 1 # macro -mmGUS_CGTT_CLK_CTRL = 0x50f4 # macro -mmGUS_CGTT_CLK_CTRL_BASE_IDX = 1 # macro -mmCGTT_PH_CLK_CTRL0 = 0x50f8 # macro -mmCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro -mmCGTT_PH_CLK_CTRL1 = 0x50f9 # macro -mmCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro -mmCGTT_PH_CLK_CTRL2 = 0x50fa # macro -mmCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro -mmCGTT_PH_CLK_CTRL3 = 0x50fb # macro -mmCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro -mmCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro -mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_PFP_UCODE_ADDR = 0x5814 # macro -mmCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_HYP_PFP_UCODE_DATA = 0x5815 # macro -mmCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_PFP_UCODE_DATA = 0x5815 # macro -mmCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_HYP_ME_UCODE_ADDR = 0x5816 # macro -mmCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_ME_RAM_RADDR = 0x5816 # macro -mmCP_ME_RAM_RADDR_BASE_IDX = 1 # macro -mmCP_ME_RAM_WADDR = 0x5816 # macro -mmCP_ME_RAM_WADDR_BASE_IDX = 1 # macro -mmCP_HYP_ME_UCODE_DATA = 0x5817 # macro -mmCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_ME_RAM_DATA = 0x5817 # macro -mmCP_ME_RAM_DATA_BASE_IDX = 1 # macro -mmCP_CE_UCODE_ADDR = 0x5818 # macro -mmCP_CE_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_HYP_CE_UCODE_ADDR = 0x5818 # macro -mmCP_HYP_CE_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_CE_UCODE_DATA = 0x5819 # macro -mmCP_CE_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_HYP_CE_UCODE_DATA = 0x5819 # macro -mmCP_HYP_CE_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro -mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_MEC_ME1_UCODE_ADDR = 0x581a # macro -mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_HYP_MEC1_UCODE_DATA = 0x581b # macro -mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_MEC_ME1_UCODE_DATA = 0x581b # macro -mmCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro -mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_MEC_ME2_UCODE_ADDR = 0x581c # macro -mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro -mmCP_HYP_MEC2_UCODE_DATA = 0x581d # macro -mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_MEC_ME2_UCODE_DATA = 0x581d # macro -mmCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro -mmCP_PFP_IC_BASE_LO = 0x5840 # macro -mmCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro -mmCP_PFP_IC_BASE_HI = 0x5841 # macro -mmCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro -mmCP_PFP_IC_BASE_CNTL = 0x5842 # macro -mmCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_PFP_IC_OP_CNTL = 0x5843 # macro -mmCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_ME_IC_BASE_LO = 0x5844 # macro -mmCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro -mmCP_ME_IC_BASE_HI = 0x5845 # macro -mmCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro -mmCP_ME_IC_BASE_CNTL = 0x5846 # macro -mmCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_ME_IC_OP_CNTL = 0x5847 # macro -mmCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_CE_IC_BASE_LO = 0x5848 # macro -mmCP_CE_IC_BASE_LO_BASE_IDX = 1 # macro -mmCP_CE_IC_BASE_HI = 0x5849 # macro -mmCP_CE_IC_BASE_HI_BASE_IDX = 1 # macro -mmCP_CE_IC_BASE_CNTL = 0x584a # macro -mmCP_CE_IC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_CE_IC_OP_CNTL = 0x584b # macro -mmCP_CE_IC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_CPC_IC_BASE_LO = 0x584c # macro -mmCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro -mmCP_CPC_IC_BASE_HI = 0x584d # macro -mmCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro -mmCP_CPC_IC_BASE_CNTL = 0x584e # macro -mmCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_CPC_IC_OP_CNTL = 0x584f # macro -mmCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro -mmCP_MES_IC_BASE_LO = 0x5850 # macro -mmCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro -mmCP_MES_MIBASE_LO = 0x5850 # macro -mmCP_MES_MIBASE_LO_BASE_IDX = 1 # macro -mmCP_MES_IC_BASE_HI = 0x5851 # macro -mmCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro -mmCP_MES_MIBASE_HI = 0x5851 # macro -mmCP_MES_MIBASE_HI_BASE_IDX = 1 # macro -mmCP_MES_IC_BASE_CNTL = 0x5852 # macro -mmCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro -mmCP_MES_DC_BASE_LO = 0x5854 # macro -mmCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro -mmCP_MES_MDBASE_LO = 0x5854 # macro -mmCP_MES_MDBASE_LO_BASE_IDX = 1 # macro -mmCP_MES_DC_BASE_HI = 0x5855 # macro -mmCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro -mmCP_MES_MDBASE_HI = 0x5855 # macro -mmCP_MES_MDBASE_HI_BASE_IDX = 1 # macro -mmCP_MES_LOCAL_BASE0_LO = 0x5856 # macro -mmCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -mmCP_MES_LOCAL_BASE0_HI = 0x5857 # macro -mmCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -mmCP_MES_LOCAL_MASK0_LO = 0x5858 # macro -mmCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -mmCP_MES_LOCAL_MASK0_HI = 0x5859 # macro -mmCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -mmCP_MES_LOCAL_APERTURE = 0x585a # macro -mmCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro -mmCP_MES_MIBOUND_LO = 0x585b # macro -mmCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro -mmCP_MES_MIBOUND_HI = 0x585c # macro -mmCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro -mmCP_MES_MDBOUND_LO = 0x585d # macro -mmCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro -mmCP_MES_MDBOUND_HI = 0x585e # macro -mmCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro -mmGFX_PIPE_PRIORITY = 0x587f # macro -mmGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro -mmGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro -mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro -mmGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro -mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro -mmGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro -mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro -mmGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro -mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro -mmGRBM_CAM_INDEX = 0x5a04 # macro -mmGRBM_CAM_INDEX_BASE_IDX = 1 # macro -mmGRBM_HYP_CAM_INDEX = 0x5a04 # macro -mmGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro -mmGRBM_CAM_DATA = 0x5a05 # macro -mmGRBM_CAM_DATA_BASE_IDX = 1 # macro -mmGRBM_HYP_CAM_DATA = 0x5a05 # macro -mmGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro -mmGRBM_CAM_DATA_UPPER = 0x5a06 # macro -mmGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro -mmGRBM_HYP_CAM_DATA_UPPER = 0x5a06 # macro -mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro -mmGC_IH_COOKIE_0_PTR = 0x5a07 # macro -mmGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro -mmGRBM_SE_REMAP_CNTL = 0x5a08 # macro -mmGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro -mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro -mmRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro -mmRLC_SDMA0_STATUS = 0x5b12 # macro -mmRLC_SDMA0_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA1_STATUS = 0x5b13 # macro -mmRLC_SDMA1_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA2_STATUS = 0x5b14 # macro -mmRLC_SDMA2_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA3_STATUS = 0x5b15 # macro -mmRLC_SDMA3_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA0_BUSY_STATUS = 0x5b16 # macro -mmRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA1_BUSY_STATUS = 0x5b17 # macro -mmRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA2_BUSY_STATUS = 0x5b18 # macro -mmRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_SDMA3_BUSY_STATUS = 0x5b19 # macro -mmRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro -mmRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro -mmRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro -mmRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro -mmRLC_RLCV_TIMER_CTRL = 0x5b26 # macro -mmRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro -mmRLC_RLCV_TIMER_STAT = 0x5b27 # macro -mmRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro -mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VF_MASK = 0x5b2d # macro -mmRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro -mmRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro -mmRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro -mmRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro -mmRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro -mmRLC_BUSY_CLK_CNTL = 0x5b30 # macro -mmRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro -mmRLC_CLK_CNTL = 0x5b31 # macro -mmRLC_CLK_CNTL_BASE_IDX = 1 # macro -mmRLC_PACE_TIMER_STAT = 0x5b33 # macro -mmRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro -mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro -mmRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro -mmRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro -mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCH_0 = 0x5b38 # macro -mmRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_ACTIVE_FCN_ID = 0x5b39 # macro -mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCH_3 = 0x5b3a # macro -mmRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCH_1 = 0x5b3b # macro -mmRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCH_2 = 0x5b3c # macro -mmRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro -mmRLC_PACE_INT_FORCE = 0x5b3d # macro -mmRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro -mmRLC_PACE_INT_CLEAR = 0x5b3e # macro -mmRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_INT_STAT = 0x5b3f # macro -mmRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro -mmRLC_RLCV_TIMER_INT_1 = 0x5b40 # macro -mmRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro -mmRLC_IH_COOKIE = 0x5b41 # macro -mmRLC_IH_COOKIE_BASE_IDX = 1 # macro -mmRLC_IH_COOKIE_CNTL = 0x5b42 # macro -mmRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro -mmRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro -mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro -mmRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro -mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro -mmRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro -mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro -mmRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_F32_RESET = 0x5b47 # macro -mmRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro -mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_VIRT_RESET_REQ = 0x5b4c # macro -mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro -mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro -mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro -mmRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro -mmRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro -mmRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro -mmRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro -mmRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro -mmRLC_HYP_RESET_VECTOR = 0x5b54 # macro -mmRLC_HYP_RESET_VECTOR_BASE_IDX = 1 # macro -mmRLC_HYP_BOOTLOAD_SIZE = 0x5b5c # macro -mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX = 1 # macro -mmRLC_HYP_BOOTLOAD_ADDR_LO = 0x5b5d # macro -mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro -mmRLC_HYP_BOOTLOAD_ADDR_HI = 0x5b5e # macro -mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro -mmRLC_GPM_IRAM_ADDR = 0x5b5f # macro -mmRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro -mmRLC_GPM_IRAM_DATA = 0x5b60 # macro -mmRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro -mmRLC_GPM_UCODE_ADDR = 0x5b61 # macro -mmRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro -mmRLC_GPM_UCODE_DATA = 0x5b62 # macro -mmRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro -mmRLC_PACE_UCODE_ADDR = 0x5b63 # macro -mmRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro -mmRLC_PACE_UCODE_DATA = 0x5b64 # macro -mmRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_UCODE_ADDR = 0x5b65 # macro -mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_UCODE_DATA = 0x5b66 # macro -mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCRATCH_ADDR = 0x5b67 # macro -mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SCRATCH_DATA = 0x5b68 # macro -mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro -mmRLC_RLCV_IRAM_ADDR = 0x5b69 # macro -mmRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro -mmRLC_RLCV_IRAM_DATA = 0x5b6a # macro -mmRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro -mmRLC_RLCP_IRAM_ADDR = 0x5b6b # macro -mmRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro -mmRLC_RLCP_IRAM_DATA = 0x5b6c # macro -mmRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro -mmRLC_SRM_DRAM_ADDR = 0x5b71 # macro -mmRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SRM_DRAM_DATA = 0x5b72 # macro -mmRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro -mmRLC_SRM_ARAM_ADDR = 0x5b73 # macro -mmRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro -mmRLC_SRM_ARAM_DATA = 0x5b74 # macro -mmRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro -mmRLC_GPM_SCRATCH_ADDR = 0x5b75 # macro -mmRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro -mmRLC_GPM_SCRATCH_DATA = 0x5b76 # macro -mmRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro -mmRLC_GTS_OFFSET_LSB = 0x5b79 # macro -mmRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro -mmRLC_GTS_OFFSET_MSB = 0x5b7a # macro -mmRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro -mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro -mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro -mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro -mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro -mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro -mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro -mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro -mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro -mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro -mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro -mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro -mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro -mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro -mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro -mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro -mmRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro -mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro -mmSDMA0_UCODE_ADDR = 0x5880 # macro -mmSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro -mmSDMA0_UCODE_DATA = 0x5881 # macro -mmSDMA0_UCODE_DATA_BASE_IDX = 1 # macro -mmSDMA0_VM_CTX_LO = 0x5882 # macro -mmSDMA0_VM_CTX_LO_BASE_IDX = 1 # macro -mmSDMA0_VM_CTX_HI = 0x5883 # macro -mmSDMA0_VM_CTX_HI_BASE_IDX = 1 # macro -mmSDMA0_ACTIVE_FCN_ID = 0x5884 # macro -mmSDMA0_ACTIVE_FCN_ID_BASE_IDX = 1 # macro -mmSDMA0_VM_CTX_CNTL = 0x5885 # macro -mmSDMA0_VM_CTX_CNTL_BASE_IDX = 1 # macro -mmSDMA0_VIRT_RESET_REQ = 0x5886 # macro -mmSDMA0_VIRT_RESET_REQ_BASE_IDX = 1 # macro -mmSDMA0_VF_ENABLE = 0x5887 # macro -mmSDMA0_VF_ENABLE_BASE_IDX = 1 # macro -mmSDMA0_CONTEXT_REG_TYPE0 = 0x5888 # macro -mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA0_CONTEXT_REG_TYPE1 = 0x5889 # macro -mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA0_CONTEXT_REG_TYPE2 = 0x588a # macro -mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA0_CONTEXT_REG_TYPE3 = 0x588b # macro -mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA0_PUB_REG_TYPE0 = 0x588c # macro -mmSDMA0_PUB_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA0_PUB_REG_TYPE1 = 0x588d # macro -mmSDMA0_PUB_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA0_PUB_REG_TYPE2 = 0x588e # macro -mmSDMA0_PUB_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA0_PUB_REG_TYPE3 = 0x588f # macro -mmSDMA0_PUB_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA0_VM_CNTL = 0x5893 # macro -mmSDMA0_VM_CNTL_BASE_IDX = 1 # macro -mmSDMA0_BROADCAST_UCODE_ADDR = 0x589c # macro -mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro -mmSDMA0_BROADCAST_UCODE_DATA = 0x589d # macro -mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro -mmSDMA1_UCODE_ADDR = 0x58a0 # macro -mmSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro -mmSDMA1_UCODE_DATA = 0x58a1 # macro -mmSDMA1_UCODE_DATA_BASE_IDX = 1 # macro -mmSDMA1_VM_CTX_LO = 0x58a2 # macro -mmSDMA1_VM_CTX_LO_BASE_IDX = 1 # macro -mmSDMA1_VM_CTX_HI = 0x58a3 # macro -mmSDMA1_VM_CTX_HI_BASE_IDX = 1 # macro -mmSDMA1_ACTIVE_FCN_ID = 0x58a4 # macro -mmSDMA1_ACTIVE_FCN_ID_BASE_IDX = 1 # macro -mmSDMA1_VM_CTX_CNTL = 0x58a5 # macro -mmSDMA1_VM_CTX_CNTL_BASE_IDX = 1 # macro -mmSDMA1_VIRT_RESET_REQ = 0x58a6 # macro -mmSDMA1_VIRT_RESET_REQ_BASE_IDX = 1 # macro -mmSDMA1_VF_ENABLE = 0x58a7 # macro -mmSDMA1_VF_ENABLE_BASE_IDX = 1 # macro -mmSDMA1_CONTEXT_REG_TYPE0 = 0x58a8 # macro -mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA1_CONTEXT_REG_TYPE1 = 0x58a9 # macro -mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA1_CONTEXT_REG_TYPE2 = 0x58aa # macro -mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA1_CONTEXT_REG_TYPE3 = 0x58ab # macro -mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA1_PUB_REG_TYPE0 = 0x58ac # macro -mmSDMA1_PUB_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA1_PUB_REG_TYPE1 = 0x58ad # macro -mmSDMA1_PUB_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA1_PUB_REG_TYPE2 = 0x58ae # macro -mmSDMA1_PUB_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA1_PUB_REG_TYPE3 = 0x58af # macro -mmSDMA1_PUB_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA1_VM_CNTL = 0x58b3 # macro -mmSDMA1_VM_CNTL_BASE_IDX = 1 # macro -mmSDMA2_UCODE_ADDR = 0x58c0 # macro -mmSDMA2_UCODE_ADDR_BASE_IDX = 1 # macro -mmSDMA2_UCODE_DATA = 0x58c1 # macro -mmSDMA2_UCODE_DATA_BASE_IDX = 1 # macro -mmSDMA2_VM_CTX_LO = 0x58c2 # macro -mmSDMA2_VM_CTX_LO_BASE_IDX = 1 # macro -mmSDMA2_VM_CTX_HI = 0x58c3 # macro -mmSDMA2_VM_CTX_HI_BASE_IDX = 1 # macro -mmSDMA2_ACTIVE_FCN_ID = 0x58c4 # macro -mmSDMA2_ACTIVE_FCN_ID_BASE_IDX = 1 # macro -mmSDMA2_VM_CTX_CNTL = 0x58c5 # macro -mmSDMA2_VM_CTX_CNTL_BASE_IDX = 1 # macro -mmSDMA2_VIRT_RESET_REQ = 0x58c6 # macro -mmSDMA2_VIRT_RESET_REQ_BASE_IDX = 1 # macro -mmSDMA2_VF_ENABLE = 0x58c7 # macro -mmSDMA2_VF_ENABLE_BASE_IDX = 1 # macro -mmSDMA2_CONTEXT_REG_TYPE0 = 0x58c8 # macro -mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA2_CONTEXT_REG_TYPE1 = 0x58c9 # macro -mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA2_CONTEXT_REG_TYPE2 = 0x58ca # macro -mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA2_CONTEXT_REG_TYPE3 = 0x58cb # macro -mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA2_PUB_REG_TYPE0 = 0x58cc # macro -mmSDMA2_PUB_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA2_PUB_REG_TYPE1 = 0x58cd # macro -mmSDMA2_PUB_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA2_PUB_REG_TYPE2 = 0x58ce # macro -mmSDMA2_PUB_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA2_PUB_REG_TYPE3 = 0x58cf # macro -mmSDMA2_PUB_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA2_VM_CNTL = 0x58d3 # macro -mmSDMA2_VM_CNTL_BASE_IDX = 1 # macro -mmSDMA3_UCODE_ADDR = 0x58e0 # macro -mmSDMA3_UCODE_ADDR_BASE_IDX = 1 # macro -mmSDMA3_UCODE_DATA = 0x58e1 # macro -mmSDMA3_UCODE_DATA_BASE_IDX = 1 # macro -mmSDMA3_VM_CTX_LO = 0x58e2 # macro -mmSDMA3_VM_CTX_LO_BASE_IDX = 1 # macro -mmSDMA3_VM_CTX_HI = 0x58e3 # macro -mmSDMA3_VM_CTX_HI_BASE_IDX = 1 # macro -mmSDMA3_ACTIVE_FCN_ID = 0x58e4 # macro -mmSDMA3_ACTIVE_FCN_ID_BASE_IDX = 1 # macro -mmSDMA3_VM_CTX_CNTL = 0x58e5 # macro -mmSDMA3_VM_CTX_CNTL_BASE_IDX = 1 # macro -mmSDMA3_VIRT_RESET_REQ = 0x58e6 # macro -mmSDMA3_VIRT_RESET_REQ_BASE_IDX = 1 # macro -mmSDMA3_VF_ENABLE = 0x58e7 # macro -mmSDMA3_VF_ENABLE_BASE_IDX = 1 # macro -mmSDMA3_CONTEXT_REG_TYPE0 = 0x58e8 # macro -mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA3_CONTEXT_REG_TYPE1 = 0x58e9 # macro -mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA3_CONTEXT_REG_TYPE2 = 0x58ea # macro -mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA3_CONTEXT_REG_TYPE3 = 0x58eb # macro -mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA3_PUB_REG_TYPE0 = 0x58ec # macro -mmSDMA3_PUB_REG_TYPE0_BASE_IDX = 1 # macro -mmSDMA3_PUB_REG_TYPE1 = 0x58ed # macro -mmSDMA3_PUB_REG_TYPE1_BASE_IDX = 1 # macro -mmSDMA3_PUB_REG_TYPE2 = 0x58ee # macro -mmSDMA3_PUB_REG_TYPE2_BASE_IDX = 1 # macro -mmSDMA3_PUB_REG_TYPE3 = 0x58ef # macro -mmSDMA3_PUB_REG_TYPE3_BASE_IDX = 1 # macro -mmSDMA3_VM_CNTL = 0x58f3 # macro -mmSDMA3_VM_CNTL_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF16 = 0x5a90 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF17 = 0x5a91 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF18 = 0x5a92 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF19 = 0x5a93 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF20 = 0x5a94 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF21 = 0x5a95 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF22 = 0x5a96 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF23 = 0x5a97 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF24 = 0x5a98 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF25 = 0x5a99 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF26 = 0x5a9a # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF27 = 0x5a9b # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF28 = 0x5a9c # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF29 = 0x5a9d # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF30 = 0x5a9e # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX = 1 # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF31 = 0x5a9f # macro -mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX = 1 # macro -mmGCVM_IOMMU_MMIO_CNTRL_1 = 0x5aa0 # macro -mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_LO_0 = 0x5aa1 # macro -mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_LO_1 = 0x5aa2 # macro -mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_LO_2 = 0x5aa3 # macro -mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_LO_3 = 0x5aa4 # macro -mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_HI_0 = 0x5aa5 # macro -mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_HI_1 = 0x5aa6 # macro -mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_HI_2 = 0x5aa7 # macro -mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_BASE_HI_3 = 0x5aa8 # macro -mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_LO_0 = 0x5aa9 # macro -mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_LO_1 = 0x5aaa # macro -mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_LO_2 = 0x5aab # macro -mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_LO_3 = 0x5aac # macro -mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_HI_0 = 0x5aad # macro -mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_HI_1 = 0x5aae # macro -mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_HI_2 = 0x5aaf # macro -mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_RELOC_HI_3 = 0x5ab0 # macro -mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_LO_0 = 0x5ab1 # macro -mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_LO_1 = 0x5ab2 # macro -mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_LO_2 = 0x5ab3 # macro -mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_LO_3 = 0x5ab4 # macro -mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_HI_0 = 0x5ab5 # macro -mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_HI_1 = 0x5ab6 # macro -mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_HI_2 = 0x5ab7 # macro -mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro -mmGCMC_VM_MARC_LEN_HI_3 = 0x5ab8 # macro -mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro -mmGCVM_IOMMU_CONTROL_REGISTER = 0x5ab9 # macro -mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX = 1 # macro -mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER = 0x5aba # macro -mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX = 1 # macro -mmGCMC_VM_XGMI_GPUIOV_ENABLE = 0x5abb # macro -mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX = 1 # macro -mmCPG_PSP_DEBUG = 0x5c10 # macro -mmCPG_PSP_DEBUG_BASE_IDX = 1 # macro -mmCPC_PSP_DEBUG = 0x5c11 # macro -mmCPC_PSP_DEBUG_BASE_IDX = 1 # macro -mmGRBM_SEC_CNTL = 0x5e0d # macro -mmGRBM_SEC_CNTL_BASE_IDX = 1 # macro -mmRLC_FWL_FIRST_VIOL_ADDR = 0x5f12 # macro -mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro -mmRLC_SRM_FWL_FIRST_VIOL_ADDR = 0x5f3d # macro -mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL0 = 0x5dc0 # macro -mmGCVM_L2_ID_CTRL0_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL1 = 0x5dc1 # macro -mmGCVM_L2_ID_CTRL1_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL2 = 0x5dc2 # macro -mmGCVM_L2_ID_CTRL2_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL3 = 0x5dc3 # macro -mmGCVM_L2_ID_CTRL3_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL4 = 0x5dc4 # macro -mmGCVM_L2_ID_CTRL4_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL5 = 0x5dc5 # macro -mmGCVM_L2_ID_CTRL5_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL6 = 0x5dc6 # macro -mmGCVM_L2_ID_CTRL6_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL7 = 0x5dc7 # macro -mmGCVM_L2_ID_CTRL7_BASE_IDX = 1 # macro -mmGCVM_L2_ID_CTRL_HI = 0x5dc8 # macro -mmGCVM_L2_ID_CTRL_HI_BASE_IDX = 1 # macro -mmGCVM_L2_ID_STATUS = 0x5dc9 # macro -mmGCVM_L2_ID_STATUS_BASE_IDX = 1 # macro -mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5dcb # macro -mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro -mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE = 0x5dcd # macro -mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX = 1 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x5dce # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 1 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x5dcf # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 1 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x5dd0 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 1 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x5dd1 # macro -mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 1 # macro -mmSDMA2_DEC_START = 0x0000 # macro -mmSDMA2_DEC_START_BASE_IDX = 2 # macro -mmSDMA2_GLOBAL_TIMESTAMP_LO = 0x000f # macro -mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro -mmSDMA2_GLOBAL_TIMESTAMP_HI = 0x0010 # macro -mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro -mmSDMA2_PG_CNTL = 0x0016 # macro -mmSDMA2_PG_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PG_CTX_LO = 0x0017 # macro -mmSDMA2_PG_CTX_LO_BASE_IDX = 2 # macro -mmSDMA2_PG_CTX_HI = 0x0018 # macro -mmSDMA2_PG_CTX_HI_BASE_IDX = 2 # macro -mmSDMA2_PG_CTX_CNTL = 0x0019 # macro -mmSDMA2_PG_CTX_CNTL_BASE_IDX = 2 # macro -mmSDMA2_POWER_CNTL = 0x001a # macro -mmSDMA2_POWER_CNTL_BASE_IDX = 2 # macro -mmSDMA2_CLK_CTRL = 0x001b # macro -mmSDMA2_CLK_CTRL_BASE_IDX = 2 # macro -mmSDMA2_CNTL = 0x001c # macro -mmSDMA2_CNTL_BASE_IDX = 2 # macro -mmSDMA2_CHICKEN_BITS = 0x001d # macro -mmSDMA2_CHICKEN_BITS_BASE_IDX = 2 # macro -mmSDMA2_GB_ADDR_CONFIG = 0x001e # macro -mmSDMA2_GB_ADDR_CONFIG_BASE_IDX = 2 # macro -mmSDMA2_GB_ADDR_CONFIG_READ = 0x001f # macro -mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro -mmSDMA2_RB_RPTR_FETCH_HI = 0x0020 # macro -mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro -mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro -mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RB_RPTR_FETCH = 0x0022 # macro -mmSDMA2_RB_RPTR_FETCH_BASE_IDX = 2 # macro -mmSDMA2_IB_OFFSET_FETCH = 0x0023 # macro -mmSDMA2_IB_OFFSET_FETCH_BASE_IDX = 2 # macro -mmSDMA2_PROGRAM = 0x0024 # macro -mmSDMA2_PROGRAM_BASE_IDX = 2 # macro -mmSDMA2_STATUS_REG = 0x0025 # macro -mmSDMA2_STATUS_REG_BASE_IDX = 2 # macro -mmSDMA2_STATUS1_REG = 0x0026 # macro -mmSDMA2_STATUS1_REG_BASE_IDX = 2 # macro -mmSDMA2_RD_BURST_CNTL = 0x0027 # macro -mmSDMA2_RD_BURST_CNTL_BASE_IDX = 2 # macro -mmSDMA2_HBM_PAGE_CONFIG = 0x0028 # macro -mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro -mmSDMA2_UCODE_CHECKSUM = 0x0029 # macro -mmSDMA2_UCODE_CHECKSUM_BASE_IDX = 2 # macro -mmSDMA2_F32_CNTL = 0x002a # macro -mmSDMA2_F32_CNTL_BASE_IDX = 2 # macro -mmSDMA2_FREEZE = 0x002b # macro -mmSDMA2_FREEZE_BASE_IDX = 2 # macro -mmSDMA2_PHASE0_QUANTUM = 0x002c # macro -mmSDMA2_PHASE0_QUANTUM_BASE_IDX = 2 # macro -mmSDMA2_PHASE1_QUANTUM = 0x002d # macro -mmSDMA2_PHASE1_QUANTUM_BASE_IDX = 2 # macro -mmSDMA2_EDC_CONFIG = 0x0032 # macro -mmSDMA2_EDC_CONFIG_BASE_IDX = 2 # macro -mmSDMA2_BA_THRESHOLD = 0x0033 # macro -mmSDMA2_BA_THRESHOLD_BASE_IDX = 2 # macro -mmSDMA2_ID = 0x0034 # macro -mmSDMA2_ID_BASE_IDX = 2 # macro -mmSDMA2_VERSION = 0x0035 # macro -mmSDMA2_VERSION_BASE_IDX = 2 # macro -mmSDMA2_EDC_COUNTER = 0x0036 # macro -mmSDMA2_EDC_COUNTER_BASE_IDX = 2 # macro -mmSDMA2_EDC_COUNTER_CLEAR = 0x0037 # macro -mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro -mmSDMA2_STATUS2_REG = 0x0038 # macro -mmSDMA2_STATUS2_REG_BASE_IDX = 2 # macro -mmSDMA2_ATOMIC_CNTL = 0x0039 # macro -mmSDMA2_ATOMIC_CNTL_BASE_IDX = 2 # macro -mmSDMA2_ATOMIC_PREOP_LO = 0x003a # macro -mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro -mmSDMA2_ATOMIC_PREOP_HI = 0x003b # macro -mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_CNTL = 0x003c # macro -mmSDMA2_UTCL1_CNTL_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_WATERMK = 0x003d # macro -mmSDMA2_UTCL1_WATERMK_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_RD_STATUS = 0x003e # macro -mmSDMA2_UTCL1_RD_STATUS_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_WR_STATUS = 0x003f # macro -mmSDMA2_UTCL1_WR_STATUS_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_INV0 = 0x0040 # macro -mmSDMA2_UTCL1_INV0_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_INV1 = 0x0041 # macro -mmSDMA2_UTCL1_INV1_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_INV2 = 0x0042 # macro -mmSDMA2_UTCL1_INV2_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_RD_XNACK0 = 0x0043 # macro -mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_RD_XNACK1 = 0x0044 # macro -mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_WR_XNACK0 = 0x0045 # macro -mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_WR_XNACK1 = 0x0046 # macro -mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_TIMEOUT = 0x0047 # macro -mmSDMA2_UTCL1_TIMEOUT_BASE_IDX = 2 # macro -mmSDMA2_UTCL1_PAGE = 0x0048 # macro -mmSDMA2_UTCL1_PAGE_BASE_IDX = 2 # macro -mmSDMA2_RELAX_ORDERING_LUT = 0x004a # macro -mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro -mmSDMA2_CHICKEN_BITS_2 = 0x004b # macro -mmSDMA2_CHICKEN_BITS_2_BASE_IDX = 2 # macro -mmSDMA2_STATUS3_REG = 0x004c # macro -mmSDMA2_STATUS3_REG_BASE_IDX = 2 # macro -mmSDMA2_PHYSICAL_ADDR_LO = 0x004d # macro -mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_PHYSICAL_ADDR_HI = 0x004e # macro -mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_PHASE2_QUANTUM = 0x004f # macro -mmSDMA2_PHASE2_QUANTUM_BASE_IDX = 2 # macro -mmSDMA2_ERROR_LOG = 0x0050 # macro -mmSDMA2_ERROR_LOG_BASE_IDX = 2 # macro -mmSDMA2_PUB_DUMMY_REG0 = 0x0051 # macro -mmSDMA2_PUB_DUMMY_REG0_BASE_IDX = 2 # macro -mmSDMA2_PUB_DUMMY_REG1 = 0x0052 # macro -mmSDMA2_PUB_DUMMY_REG1_BASE_IDX = 2 # macro -mmSDMA2_PUB_DUMMY_REG2 = 0x0053 # macro -mmSDMA2_PUB_DUMMY_REG2_BASE_IDX = 2 # macro -mmSDMA2_PUB_DUMMY_REG3 = 0x0054 # macro -mmSDMA2_PUB_DUMMY_REG3_BASE_IDX = 2 # macro -mmSDMA2_F32_COUNTER = 0x0055 # macro -mmSDMA2_F32_COUNTER_BASE_IDX = 2 # macro -mmSDMA2_CRD_CNTL = 0x005b # macro -mmSDMA2_CRD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_AQL_STATUS = 0x005f # macro -mmSDMA2_AQL_STATUS_BASE_IDX = 2 # macro -mmSDMA2_EA_DBIT_ADDR_DATA = 0x0060 # macro -mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro -mmSDMA2_EA_DBIT_ADDR_INDEX = 0x0061 # macro -mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro -mmSDMA2_TLBI_GCR_CNTL = 0x0062 # macro -mmSDMA2_TLBI_GCR_CNTL_BASE_IDX = 2 # macro -mmSDMA2_TILING_CONFIG = 0x0063 # macro -mmSDMA2_TILING_CONFIG_BASE_IDX = 2 # macro -mmSDMA2_INT_STATUS = 0x0070 # macro -mmSDMA2_INT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_HOLE_ADDR_LO = 0x0072 # macro -mmSDMA2_HOLE_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_HOLE_ADDR_HI = 0x0073 # macro -mmSDMA2_HOLE_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_CLOCK_GATING_REG = 0x0075 # macro -mmSDMA2_CLOCK_GATING_REG_BASE_IDX = 2 # macro -mmSDMA2_STATUS4_REG = 0x0076 # macro -mmSDMA2_STATUS4_REG_BASE_IDX = 2 # macro -mmSDMA2_SCRATCH_RAM_DATA = 0x0077 # macro -mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro -mmSDMA2_SCRATCH_RAM_ADDR = 0x0078 # macro -mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro -mmSDMA2_TIMESTAMP_CNTL = 0x0079 # macro -mmSDMA2_TIMESTAMP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_STATUS5_REG = 0x007a # macro -mmSDMA2_STATUS5_REG_BASE_IDX = 2 # macro -mmSDMA2_QUEUE_RESET_REQ = 0x007b # macro -mmSDMA2_QUEUE_RESET_REQ_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_CNTL = 0x0080 # macro -mmSDMA2_GFX_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_BASE = 0x0081 # macro -mmSDMA2_GFX_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_BASE_HI = 0x0082 # macro -mmSDMA2_GFX_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_RPTR = 0x0083 # macro -mmSDMA2_GFX_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_RPTR_HI = 0x0084 # macro -mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_WPTR = 0x0085 # macro -mmSDMA2_GFX_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_WPTR_HI = 0x0086 # macro -mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro -mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro -mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro -mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_CNTL = 0x008a # macro -mmSDMA2_GFX_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_RPTR = 0x008b # macro -mmSDMA2_GFX_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_OFFSET = 0x008c # macro -mmSDMA2_GFX_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_BASE_LO = 0x008d # macro -mmSDMA2_GFX_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_BASE_HI = 0x008e # macro -mmSDMA2_GFX_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_SIZE = 0x008f # macro -mmSDMA2_GFX_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_GFX_SKIP_CNTL = 0x0090 # macro -mmSDMA2_GFX_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_CONTEXT_STATUS = 0x0091 # macro -mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_GFX_DOORBELL = 0x0092 # macro -mmSDMA2_GFX_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_GFX_CONTEXT_CNTL = 0x0093 # macro -mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_STATUS = 0x00a8 # macro -mmSDMA2_GFX_STATUS_BASE_IDX = 2 # macro -mmSDMA2_GFX_DOORBELL_LOG = 0x00a9 # macro -mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_GFX_WATERMARK = 0x00aa # macro -mmSDMA2_GFX_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_GFX_DOORBELL_OFFSET = 0x00ab # macro -mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_GFX_CSA_ADDR_LO = 0x00ac # macro -mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_GFX_CSA_ADDR_HI = 0x00ad # macro -mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_IB_SUB_REMAIN = 0x00af # macro -mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_GFX_PREEMPT = 0x00b0 # macro -mmSDMA2_GFX_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_GFX_DUMMY_REG = 0x00b1 # macro -mmSDMA2_GFX_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro -mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro -mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_GFX_RB_AQL_CNTL = 0x00b4 # macro -mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro -mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA0 = 0x00c0 # macro -mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA1 = 0x00c1 # macro -mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA2 = 0x00c2 # macro -mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA3 = 0x00c3 # macro -mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA4 = 0x00c4 # macro -mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA5 = 0x00c5 # macro -mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA6 = 0x00c6 # macro -mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA7 = 0x00c7 # macro -mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA8 = 0x00c8 # macro -mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA9 = 0x00c9 # macro -mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_DATA10 = 0x00ca # macro -mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_GFX_MIDCMD_CNTL = 0x00cb # macro -mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_CNTL = 0x00d8 # macro -mmSDMA2_PAGE_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_BASE = 0x00d9 # macro -mmSDMA2_PAGE_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_BASE_HI = 0x00da # macro -mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_RPTR = 0x00db # macro -mmSDMA2_PAGE_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_RPTR_HI = 0x00dc # macro -mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_WPTR = 0x00dd # macro -mmSDMA2_PAGE_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_WPTR_HI = 0x00de # macro -mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro -mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro -mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro -mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_CNTL = 0x00e2 # macro -mmSDMA2_PAGE_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_RPTR = 0x00e3 # macro -mmSDMA2_PAGE_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_OFFSET = 0x00e4 # macro -mmSDMA2_PAGE_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_BASE_LO = 0x00e5 # macro -mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_BASE_HI = 0x00e6 # macro -mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_SIZE = 0x00e7 # macro -mmSDMA2_PAGE_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_PAGE_SKIP_CNTL = 0x00e8 # macro -mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_CONTEXT_STATUS = 0x00e9 # macro -mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_PAGE_DOORBELL = 0x00ea # macro -mmSDMA2_PAGE_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_STATUS = 0x0100 # macro -mmSDMA2_PAGE_STATUS_BASE_IDX = 2 # macro -mmSDMA2_PAGE_DOORBELL_LOG = 0x0101 # macro -mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_PAGE_WATERMARK = 0x0102 # macro -mmSDMA2_PAGE_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_PAGE_DOORBELL_OFFSET = 0x0103 # macro -mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_PAGE_CSA_ADDR_LO = 0x0104 # macro -mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_PAGE_CSA_ADDR_HI = 0x0105 # macro -mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_IB_SUB_REMAIN = 0x0107 # macro -mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_PAGE_PREEMPT = 0x0108 # macro -mmSDMA2_PAGE_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_PAGE_DUMMY_REG = 0x0109 # macro -mmSDMA2_PAGE_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro -mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro -mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_PAGE_RB_AQL_CNTL = 0x010c # macro -mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MINOR_PTR_UPDATE = 0x010d # macro -mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA0 = 0x0118 # macro -mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA1 = 0x0119 # macro -mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA2 = 0x011a # macro -mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA3 = 0x011b # macro -mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA4 = 0x011c # macro -mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA5 = 0x011d # macro -mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA6 = 0x011e # macro -mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA7 = 0x011f # macro -mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA8 = 0x0120 # macro -mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA9 = 0x0121 # macro -mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_DATA10 = 0x0122 # macro -mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_PAGE_MIDCMD_CNTL = 0x0123 # macro -mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_CNTL = 0x0130 # macro -mmSDMA2_RLC0_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_BASE = 0x0131 # macro -mmSDMA2_RLC0_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_BASE_HI = 0x0132 # macro -mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_RPTR = 0x0133 # macro -mmSDMA2_RLC0_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_RPTR_HI = 0x0134 # macro -mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_WPTR = 0x0135 # macro -mmSDMA2_RLC0_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_WPTR_HI = 0x0136 # macro -mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro -mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro -mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_CNTL = 0x013a # macro -mmSDMA2_RLC0_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_RPTR = 0x013b # macro -mmSDMA2_RLC0_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_OFFSET = 0x013c # macro -mmSDMA2_RLC0_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_BASE_LO = 0x013d # macro -mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_BASE_HI = 0x013e # macro -mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_SIZE = 0x013f # macro -mmSDMA2_RLC0_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC0_SKIP_CNTL = 0x0140 # macro -mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_CONTEXT_STATUS = 0x0141 # macro -mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC0_DOORBELL = 0x0142 # macro -mmSDMA2_RLC0_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_STATUS = 0x0158 # macro -mmSDMA2_RLC0_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC0_DOORBELL_LOG = 0x0159 # macro -mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC0_WATERMARK = 0x015a # macro -mmSDMA2_RLC0_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC0_DOORBELL_OFFSET = 0x015b # macro -mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC0_CSA_ADDR_LO = 0x015c # macro -mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC0_CSA_ADDR_HI = 0x015d # macro -mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_IB_SUB_REMAIN = 0x015f # macro -mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC0_PREEMPT = 0x0160 # macro -mmSDMA2_RLC0_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC0_DUMMY_REG = 0x0161 # macro -mmSDMA2_RLC0_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro -mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC0_RB_AQL_CNTL = 0x0164 # macro -mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro -mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA0 = 0x0170 # macro -mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA1 = 0x0171 # macro -mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA2 = 0x0172 # macro -mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA3 = 0x0173 # macro -mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA4 = 0x0174 # macro -mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA5 = 0x0175 # macro -mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA6 = 0x0176 # macro -mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA7 = 0x0177 # macro -mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA8 = 0x0178 # macro -mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA9 = 0x0179 # macro -mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_DATA10 = 0x017a # macro -mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC0_MIDCMD_CNTL = 0x017b # macro -mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_CNTL = 0x0188 # macro -mmSDMA2_RLC1_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_BASE = 0x0189 # macro -mmSDMA2_RLC1_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_BASE_HI = 0x018a # macro -mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_RPTR = 0x018b # macro -mmSDMA2_RLC1_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_RPTR_HI = 0x018c # macro -mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_WPTR = 0x018d # macro -mmSDMA2_RLC1_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_WPTR_HI = 0x018e # macro -mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro -mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro -mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro -mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_CNTL = 0x0192 # macro -mmSDMA2_RLC1_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_RPTR = 0x0193 # macro -mmSDMA2_RLC1_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_OFFSET = 0x0194 # macro -mmSDMA2_RLC1_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_BASE_LO = 0x0195 # macro -mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_BASE_HI = 0x0196 # macro -mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_SIZE = 0x0197 # macro -mmSDMA2_RLC1_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC1_SKIP_CNTL = 0x0198 # macro -mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_CONTEXT_STATUS = 0x0199 # macro -mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC1_DOORBELL = 0x019a # macro -mmSDMA2_RLC1_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_STATUS = 0x01b0 # macro -mmSDMA2_RLC1_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC1_DOORBELL_LOG = 0x01b1 # macro -mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC1_WATERMARK = 0x01b2 # macro -mmSDMA2_RLC1_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC1_DOORBELL_OFFSET = 0x01b3 # macro -mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC1_CSA_ADDR_LO = 0x01b4 # macro -mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC1_CSA_ADDR_HI = 0x01b5 # macro -mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_IB_SUB_REMAIN = 0x01b7 # macro -mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC1_PREEMPT = 0x01b8 # macro -mmSDMA2_RLC1_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC1_DUMMY_REG = 0x01b9 # macro -mmSDMA2_RLC1_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro -mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro -mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC1_RB_AQL_CNTL = 0x01bc # macro -mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro -mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA0 = 0x01c8 # macro -mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA1 = 0x01c9 # macro -mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA2 = 0x01ca # macro -mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA3 = 0x01cb # macro -mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA4 = 0x01cc # macro -mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA5 = 0x01cd # macro -mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA6 = 0x01ce # macro -mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA7 = 0x01cf # macro -mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA8 = 0x01d0 # macro -mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA9 = 0x01d1 # macro -mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_DATA10 = 0x01d2 # macro -mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC1_MIDCMD_CNTL = 0x01d3 # macro -mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_CNTL = 0x01e0 # macro -mmSDMA2_RLC2_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_BASE = 0x01e1 # macro -mmSDMA2_RLC2_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_BASE_HI = 0x01e2 # macro -mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_RPTR = 0x01e3 # macro -mmSDMA2_RLC2_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_RPTR_HI = 0x01e4 # macro -mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_WPTR = 0x01e5 # macro -mmSDMA2_RLC2_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_WPTR_HI = 0x01e6 # macro -mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro -mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro -mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_CNTL = 0x01ea # macro -mmSDMA2_RLC2_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_RPTR = 0x01eb # macro -mmSDMA2_RLC2_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_OFFSET = 0x01ec # macro -mmSDMA2_RLC2_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_BASE_LO = 0x01ed # macro -mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_BASE_HI = 0x01ee # macro -mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_SIZE = 0x01ef # macro -mmSDMA2_RLC2_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC2_SKIP_CNTL = 0x01f0 # macro -mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_CONTEXT_STATUS = 0x01f1 # macro -mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC2_DOORBELL = 0x01f2 # macro -mmSDMA2_RLC2_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_STATUS = 0x0208 # macro -mmSDMA2_RLC2_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC2_DOORBELL_LOG = 0x0209 # macro -mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC2_WATERMARK = 0x020a # macro -mmSDMA2_RLC2_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC2_DOORBELL_OFFSET = 0x020b # macro -mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC2_CSA_ADDR_LO = 0x020c # macro -mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC2_CSA_ADDR_HI = 0x020d # macro -mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_IB_SUB_REMAIN = 0x020f # macro -mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC2_PREEMPT = 0x0210 # macro -mmSDMA2_RLC2_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC2_DUMMY_REG = 0x0211 # macro -mmSDMA2_RLC2_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro -mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC2_RB_AQL_CNTL = 0x0214 # macro -mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro -mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA0 = 0x0220 # macro -mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA1 = 0x0221 # macro -mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA2 = 0x0222 # macro -mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA3 = 0x0223 # macro -mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA4 = 0x0224 # macro -mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA5 = 0x0225 # macro -mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA6 = 0x0226 # macro -mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA7 = 0x0227 # macro -mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA8 = 0x0228 # macro -mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA9 = 0x0229 # macro -mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_DATA10 = 0x022a # macro -mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC2_MIDCMD_CNTL = 0x022b # macro -mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_CNTL = 0x0238 # macro -mmSDMA2_RLC3_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_BASE = 0x0239 # macro -mmSDMA2_RLC3_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_BASE_HI = 0x023a # macro -mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_RPTR = 0x023b # macro -mmSDMA2_RLC3_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_RPTR_HI = 0x023c # macro -mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_WPTR = 0x023d # macro -mmSDMA2_RLC3_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_WPTR_HI = 0x023e # macro -mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro -mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro -mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro -mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_CNTL = 0x0242 # macro -mmSDMA2_RLC3_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_RPTR = 0x0243 # macro -mmSDMA2_RLC3_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_OFFSET = 0x0244 # macro -mmSDMA2_RLC3_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_BASE_LO = 0x0245 # macro -mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_BASE_HI = 0x0246 # macro -mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_SIZE = 0x0247 # macro -mmSDMA2_RLC3_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC3_SKIP_CNTL = 0x0248 # macro -mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_CONTEXT_STATUS = 0x0249 # macro -mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC3_DOORBELL = 0x024a # macro -mmSDMA2_RLC3_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_STATUS = 0x0260 # macro -mmSDMA2_RLC3_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC3_DOORBELL_LOG = 0x0261 # macro -mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC3_WATERMARK = 0x0262 # macro -mmSDMA2_RLC3_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC3_DOORBELL_OFFSET = 0x0263 # macro -mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC3_CSA_ADDR_LO = 0x0264 # macro -mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC3_CSA_ADDR_HI = 0x0265 # macro -mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_IB_SUB_REMAIN = 0x0267 # macro -mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC3_PREEMPT = 0x0268 # macro -mmSDMA2_RLC3_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC3_DUMMY_REG = 0x0269 # macro -mmSDMA2_RLC3_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro -mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro -mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC3_RB_AQL_CNTL = 0x026c # macro -mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MINOR_PTR_UPDATE = 0x026d # macro -mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA0 = 0x0278 # macro -mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA1 = 0x0279 # macro -mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA2 = 0x027a # macro -mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA3 = 0x027b # macro -mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA4 = 0x027c # macro -mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA5 = 0x027d # macro -mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA6 = 0x027e # macro -mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA7 = 0x027f # macro -mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA8 = 0x0280 # macro -mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA9 = 0x0281 # macro -mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_DATA10 = 0x0282 # macro -mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC3_MIDCMD_CNTL = 0x0283 # macro -mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_CNTL = 0x0290 # macro -mmSDMA2_RLC4_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_BASE = 0x0291 # macro -mmSDMA2_RLC4_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_BASE_HI = 0x0292 # macro -mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_RPTR = 0x0293 # macro -mmSDMA2_RLC4_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_RPTR_HI = 0x0294 # macro -mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_WPTR = 0x0295 # macro -mmSDMA2_RLC4_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_WPTR_HI = 0x0296 # macro -mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro -mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro -mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_CNTL = 0x029a # macro -mmSDMA2_RLC4_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_RPTR = 0x029b # macro -mmSDMA2_RLC4_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_OFFSET = 0x029c # macro -mmSDMA2_RLC4_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_BASE_LO = 0x029d # macro -mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_BASE_HI = 0x029e # macro -mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_SIZE = 0x029f # macro -mmSDMA2_RLC4_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC4_SKIP_CNTL = 0x02a0 # macro -mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_CONTEXT_STATUS = 0x02a1 # macro -mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC4_DOORBELL = 0x02a2 # macro -mmSDMA2_RLC4_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_STATUS = 0x02b8 # macro -mmSDMA2_RLC4_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC4_DOORBELL_LOG = 0x02b9 # macro -mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC4_WATERMARK = 0x02ba # macro -mmSDMA2_RLC4_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC4_DOORBELL_OFFSET = 0x02bb # macro -mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC4_CSA_ADDR_LO = 0x02bc # macro -mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC4_CSA_ADDR_HI = 0x02bd # macro -mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_IB_SUB_REMAIN = 0x02bf # macro -mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC4_PREEMPT = 0x02c0 # macro -mmSDMA2_RLC4_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC4_DUMMY_REG = 0x02c1 # macro -mmSDMA2_RLC4_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro -mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC4_RB_AQL_CNTL = 0x02c4 # macro -mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro -mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA0 = 0x02d0 # macro -mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA1 = 0x02d1 # macro -mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA2 = 0x02d2 # macro -mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA3 = 0x02d3 # macro -mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA4 = 0x02d4 # macro -mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA5 = 0x02d5 # macro -mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA6 = 0x02d6 # macro -mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA7 = 0x02d7 # macro -mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA8 = 0x02d8 # macro -mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA9 = 0x02d9 # macro -mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_DATA10 = 0x02da # macro -mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC4_MIDCMD_CNTL = 0x02db # macro -mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_CNTL = 0x02e8 # macro -mmSDMA2_RLC5_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_BASE = 0x02e9 # macro -mmSDMA2_RLC5_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_BASE_HI = 0x02ea # macro -mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_RPTR = 0x02eb # macro -mmSDMA2_RLC5_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_RPTR_HI = 0x02ec # macro -mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_WPTR = 0x02ed # macro -mmSDMA2_RLC5_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_WPTR_HI = 0x02ee # macro -mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro -mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro -mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro -mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_CNTL = 0x02f2 # macro -mmSDMA2_RLC5_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_RPTR = 0x02f3 # macro -mmSDMA2_RLC5_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_OFFSET = 0x02f4 # macro -mmSDMA2_RLC5_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_BASE_LO = 0x02f5 # macro -mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_BASE_HI = 0x02f6 # macro -mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_SIZE = 0x02f7 # macro -mmSDMA2_RLC5_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC5_SKIP_CNTL = 0x02f8 # macro -mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_CONTEXT_STATUS = 0x02f9 # macro -mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC5_DOORBELL = 0x02fa # macro -mmSDMA2_RLC5_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_STATUS = 0x0310 # macro -mmSDMA2_RLC5_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC5_DOORBELL_LOG = 0x0311 # macro -mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC5_WATERMARK = 0x0312 # macro -mmSDMA2_RLC5_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC5_DOORBELL_OFFSET = 0x0313 # macro -mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC5_CSA_ADDR_LO = 0x0314 # macro -mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC5_CSA_ADDR_HI = 0x0315 # macro -mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_IB_SUB_REMAIN = 0x0317 # macro -mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC5_PREEMPT = 0x0318 # macro -mmSDMA2_RLC5_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC5_DUMMY_REG = 0x0319 # macro -mmSDMA2_RLC5_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro -mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro -mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC5_RB_AQL_CNTL = 0x031c # macro -mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MINOR_PTR_UPDATE = 0x031d # macro -mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA0 = 0x0328 # macro -mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA1 = 0x0329 # macro -mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA2 = 0x032a # macro -mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA3 = 0x032b # macro -mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA4 = 0x032c # macro -mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA5 = 0x032d # macro -mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA6 = 0x032e # macro -mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA7 = 0x032f # macro -mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA8 = 0x0330 # macro -mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA9 = 0x0331 # macro -mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_DATA10 = 0x0332 # macro -mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC5_MIDCMD_CNTL = 0x0333 # macro -mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_CNTL = 0x0340 # macro -mmSDMA2_RLC6_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_BASE = 0x0341 # macro -mmSDMA2_RLC6_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_BASE_HI = 0x0342 # macro -mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_RPTR = 0x0343 # macro -mmSDMA2_RLC6_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_RPTR_HI = 0x0344 # macro -mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_WPTR = 0x0345 # macro -mmSDMA2_RLC6_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_WPTR_HI = 0x0346 # macro -mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro -mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro -mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_CNTL = 0x034a # macro -mmSDMA2_RLC6_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_RPTR = 0x034b # macro -mmSDMA2_RLC6_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_OFFSET = 0x034c # macro -mmSDMA2_RLC6_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_BASE_LO = 0x034d # macro -mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_BASE_HI = 0x034e # macro -mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_SIZE = 0x034f # macro -mmSDMA2_RLC6_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC6_SKIP_CNTL = 0x0350 # macro -mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_CONTEXT_STATUS = 0x0351 # macro -mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC6_DOORBELL = 0x0352 # macro -mmSDMA2_RLC6_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_STATUS = 0x0368 # macro -mmSDMA2_RLC6_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC6_DOORBELL_LOG = 0x0369 # macro -mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC6_WATERMARK = 0x036a # macro -mmSDMA2_RLC6_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC6_DOORBELL_OFFSET = 0x036b # macro -mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC6_CSA_ADDR_LO = 0x036c # macro -mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC6_CSA_ADDR_HI = 0x036d # macro -mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_IB_SUB_REMAIN = 0x036f # macro -mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC6_PREEMPT = 0x0370 # macro -mmSDMA2_RLC6_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC6_DUMMY_REG = 0x0371 # macro -mmSDMA2_RLC6_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro -mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC6_RB_AQL_CNTL = 0x0374 # macro -mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro -mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA0 = 0x0380 # macro -mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA1 = 0x0381 # macro -mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA2 = 0x0382 # macro -mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA3 = 0x0383 # macro -mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA4 = 0x0384 # macro -mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA5 = 0x0385 # macro -mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA6 = 0x0386 # macro -mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA7 = 0x0387 # macro -mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA8 = 0x0388 # macro -mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA9 = 0x0389 # macro -mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_DATA10 = 0x038a # macro -mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC6_MIDCMD_CNTL = 0x038b # macro -mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_CNTL = 0x0398 # macro -mmSDMA2_RLC7_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_BASE = 0x0399 # macro -mmSDMA2_RLC7_RB_BASE_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_BASE_HI = 0x039a # macro -mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_RPTR = 0x039b # macro -mmSDMA2_RLC7_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_RPTR_HI = 0x039c # macro -mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_WPTR = 0x039d # macro -mmSDMA2_RLC7_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_WPTR_HI = 0x039e # macro -mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro -mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro -mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro -mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_CNTL = 0x03a2 # macro -mmSDMA2_RLC7_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_RPTR = 0x03a3 # macro -mmSDMA2_RLC7_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_OFFSET = 0x03a4 # macro -mmSDMA2_RLC7_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_BASE_LO = 0x03a5 # macro -mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_BASE_HI = 0x03a6 # macro -mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_SIZE = 0x03a7 # macro -mmSDMA2_RLC7_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA2_RLC7_SKIP_CNTL = 0x03a8 # macro -mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_CONTEXT_STATUS = 0x03a9 # macro -mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC7_DOORBELL = 0x03aa # macro -mmSDMA2_RLC7_DOORBELL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_STATUS = 0x03c0 # macro -mmSDMA2_RLC7_STATUS_BASE_IDX = 2 # macro -mmSDMA2_RLC7_DOORBELL_LOG = 0x03c1 # macro -mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA2_RLC7_WATERMARK = 0x03c2 # macro -mmSDMA2_RLC7_WATERMARK_BASE_IDX = 2 # macro -mmSDMA2_RLC7_DOORBELL_OFFSET = 0x03c3 # macro -mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA2_RLC7_CSA_ADDR_LO = 0x03c4 # macro -mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC7_CSA_ADDR_HI = 0x03c5 # macro -mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_IB_SUB_REMAIN = 0x03c7 # macro -mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA2_RLC7_PREEMPT = 0x03c8 # macro -mmSDMA2_RLC7_PREEMPT_BASE_IDX = 2 # macro -mmSDMA2_RLC7_DUMMY_REG = 0x03c9 # macro -mmSDMA2_RLC7_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro -mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro -mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA2_RLC7_RB_AQL_CNTL = 0x03cc # macro -mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro -mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA0 = 0x03d8 # macro -mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA1 = 0x03d9 # macro -mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA2 = 0x03da # macro -mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA3 = 0x03db # macro -mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA4 = 0x03dc # macro -mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA5 = 0x03dd # macro -mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA6 = 0x03de # macro -mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA7 = 0x03df # macro -mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA8 = 0x03e0 # macro -mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA9 = 0x03e1 # macro -mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_DATA10 = 0x03e2 # macro -mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA2_RLC7_MIDCMD_CNTL = 0x03e3 # macro -mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_DEC_START = 0x0400 # macro -mmSDMA3_DEC_START_BASE_IDX = 2 # macro -mmSDMA3_GLOBAL_TIMESTAMP_LO = 0x040f # macro -mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro -mmSDMA3_GLOBAL_TIMESTAMP_HI = 0x0410 # macro -mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro -mmSDMA3_PG_CNTL = 0x0416 # macro -mmSDMA3_PG_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PG_CTX_LO = 0x0417 # macro -mmSDMA3_PG_CTX_LO_BASE_IDX = 2 # macro -mmSDMA3_PG_CTX_HI = 0x0418 # macro -mmSDMA3_PG_CTX_HI_BASE_IDX = 2 # macro -mmSDMA3_PG_CTX_CNTL = 0x0419 # macro -mmSDMA3_PG_CTX_CNTL_BASE_IDX = 2 # macro -mmSDMA3_POWER_CNTL = 0x041a # macro -mmSDMA3_POWER_CNTL_BASE_IDX = 2 # macro -mmSDMA3_CLK_CTRL = 0x041b # macro -mmSDMA3_CLK_CTRL_BASE_IDX = 2 # macro -mmSDMA3_CNTL = 0x041c # macro -mmSDMA3_CNTL_BASE_IDX = 2 # macro -mmSDMA3_CHICKEN_BITS = 0x041d # macro -mmSDMA3_CHICKEN_BITS_BASE_IDX = 2 # macro -mmSDMA3_GB_ADDR_CONFIG = 0x041e # macro -mmSDMA3_GB_ADDR_CONFIG_BASE_IDX = 2 # macro -mmSDMA3_GB_ADDR_CONFIG_READ = 0x041f # macro -mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro -mmSDMA3_RB_RPTR_FETCH_HI = 0x0420 # macro -mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro -mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL = 0x0421 # macro -mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RB_RPTR_FETCH = 0x0422 # macro -mmSDMA3_RB_RPTR_FETCH_BASE_IDX = 2 # macro -mmSDMA3_IB_OFFSET_FETCH = 0x0423 # macro -mmSDMA3_IB_OFFSET_FETCH_BASE_IDX = 2 # macro -mmSDMA3_PROGRAM = 0x0424 # macro -mmSDMA3_PROGRAM_BASE_IDX = 2 # macro -mmSDMA3_STATUS_REG = 0x0425 # macro -mmSDMA3_STATUS_REG_BASE_IDX = 2 # macro -mmSDMA3_STATUS1_REG = 0x0426 # macro -mmSDMA3_STATUS1_REG_BASE_IDX = 2 # macro -mmSDMA3_RD_BURST_CNTL = 0x0427 # macro -mmSDMA3_RD_BURST_CNTL_BASE_IDX = 2 # macro -mmSDMA3_HBM_PAGE_CONFIG = 0x0428 # macro -mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro -mmSDMA3_UCODE_CHECKSUM = 0x0429 # macro -mmSDMA3_UCODE_CHECKSUM_BASE_IDX = 2 # macro -mmSDMA3_F32_CNTL = 0x042a # macro -mmSDMA3_F32_CNTL_BASE_IDX = 2 # macro -mmSDMA3_FREEZE = 0x042b # macro -mmSDMA3_FREEZE_BASE_IDX = 2 # macro -mmSDMA3_PHASE0_QUANTUM = 0x042c # macro -mmSDMA3_PHASE0_QUANTUM_BASE_IDX = 2 # macro -mmSDMA3_PHASE1_QUANTUM = 0x042d # macro -mmSDMA3_PHASE1_QUANTUM_BASE_IDX = 2 # macro -mmSDMA3_EDC_CONFIG = 0x0432 # macro -mmSDMA3_EDC_CONFIG_BASE_IDX = 2 # macro -mmSDMA3_BA_THRESHOLD = 0x0433 # macro -mmSDMA3_BA_THRESHOLD_BASE_IDX = 2 # macro -mmSDMA3_ID = 0x0434 # macro -mmSDMA3_ID_BASE_IDX = 2 # macro -mmSDMA3_VERSION = 0x0435 # macro -mmSDMA3_VERSION_BASE_IDX = 2 # macro -mmSDMA3_EDC_COUNTER = 0x0436 # macro -mmSDMA3_EDC_COUNTER_BASE_IDX = 2 # macro -mmSDMA3_EDC_COUNTER_CLEAR = 0x0437 # macro -mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro -mmSDMA3_STATUS2_REG = 0x0438 # macro -mmSDMA3_STATUS2_REG_BASE_IDX = 2 # macro -mmSDMA3_ATOMIC_CNTL = 0x0439 # macro -mmSDMA3_ATOMIC_CNTL_BASE_IDX = 2 # macro -mmSDMA3_ATOMIC_PREOP_LO = 0x043a # macro -mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro -mmSDMA3_ATOMIC_PREOP_HI = 0x043b # macro -mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_CNTL = 0x043c # macro -mmSDMA3_UTCL1_CNTL_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_WATERMK = 0x043d # macro -mmSDMA3_UTCL1_WATERMK_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_RD_STATUS = 0x043e # macro -mmSDMA3_UTCL1_RD_STATUS_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_WR_STATUS = 0x043f # macro -mmSDMA3_UTCL1_WR_STATUS_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_INV0 = 0x0440 # macro -mmSDMA3_UTCL1_INV0_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_INV1 = 0x0441 # macro -mmSDMA3_UTCL1_INV1_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_INV2 = 0x0442 # macro -mmSDMA3_UTCL1_INV2_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_RD_XNACK0 = 0x0443 # macro -mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_RD_XNACK1 = 0x0444 # macro -mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_WR_XNACK0 = 0x0445 # macro -mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_WR_XNACK1 = 0x0446 # macro -mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_TIMEOUT = 0x0447 # macro -mmSDMA3_UTCL1_TIMEOUT_BASE_IDX = 2 # macro -mmSDMA3_UTCL1_PAGE = 0x0448 # macro -mmSDMA3_UTCL1_PAGE_BASE_IDX = 2 # macro -mmSDMA3_RELAX_ORDERING_LUT = 0x044a # macro -mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro -mmSDMA3_CHICKEN_BITS_2 = 0x044b # macro -mmSDMA3_CHICKEN_BITS_2_BASE_IDX = 2 # macro -mmSDMA3_STATUS3_REG = 0x044c # macro -mmSDMA3_STATUS3_REG_BASE_IDX = 2 # macro -mmSDMA3_PHYSICAL_ADDR_LO = 0x044d # macro -mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_PHYSICAL_ADDR_HI = 0x044e # macro -mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_PHASE2_QUANTUM = 0x044f # macro -mmSDMA3_PHASE2_QUANTUM_BASE_IDX = 2 # macro -mmSDMA3_ERROR_LOG = 0x0450 # macro -mmSDMA3_ERROR_LOG_BASE_IDX = 2 # macro -mmSDMA3_PUB_DUMMY_REG0 = 0x0451 # macro -mmSDMA3_PUB_DUMMY_REG0_BASE_IDX = 2 # macro -mmSDMA3_PUB_DUMMY_REG1 = 0x0452 # macro -mmSDMA3_PUB_DUMMY_REG1_BASE_IDX = 2 # macro -mmSDMA3_PUB_DUMMY_REG2 = 0x0453 # macro -mmSDMA3_PUB_DUMMY_REG2_BASE_IDX = 2 # macro -mmSDMA3_PUB_DUMMY_REG3 = 0x0454 # macro -mmSDMA3_PUB_DUMMY_REG3_BASE_IDX = 2 # macro -mmSDMA3_F32_COUNTER = 0x0455 # macro -mmSDMA3_F32_COUNTER_BASE_IDX = 2 # macro -mmSDMA3_CRD_CNTL = 0x045b # macro -mmSDMA3_CRD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_AQL_STATUS = 0x045f # macro -mmSDMA3_AQL_STATUS_BASE_IDX = 2 # macro -mmSDMA3_EA_DBIT_ADDR_DATA = 0x0460 # macro -mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro -mmSDMA3_EA_DBIT_ADDR_INDEX = 0x0461 # macro -mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro -mmSDMA3_TLBI_GCR_CNTL = 0x0462 # macro -mmSDMA3_TLBI_GCR_CNTL_BASE_IDX = 2 # macro -mmSDMA3_TILING_CONFIG = 0x0463 # macro -mmSDMA3_TILING_CONFIG_BASE_IDX = 2 # macro -mmSDMA3_INT_STATUS = 0x0470 # macro -mmSDMA3_INT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_HOLE_ADDR_LO = 0x0472 # macro -mmSDMA3_HOLE_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_HOLE_ADDR_HI = 0x0473 # macro -mmSDMA3_HOLE_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_CLOCK_GATING_REG = 0x0475 # macro -mmSDMA3_CLOCK_GATING_REG_BASE_IDX = 2 # macro -mmSDMA3_STATUS4_REG = 0x0476 # macro -mmSDMA3_STATUS4_REG_BASE_IDX = 2 # macro -mmSDMA3_SCRATCH_RAM_DATA = 0x0477 # macro -mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro -mmSDMA3_SCRATCH_RAM_ADDR = 0x0478 # macro -mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro -mmSDMA3_TIMESTAMP_CNTL = 0x0479 # macro -mmSDMA3_TIMESTAMP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_STATUS5_REG = 0x047a # macro -mmSDMA3_STATUS5_REG_BASE_IDX = 2 # macro -mmSDMA3_QUEUE_RESET_REQ = 0x047b # macro -mmSDMA3_QUEUE_RESET_REQ_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_CNTL = 0x0480 # macro -mmSDMA3_GFX_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_BASE = 0x0481 # macro -mmSDMA3_GFX_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_BASE_HI = 0x0482 # macro -mmSDMA3_GFX_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_RPTR = 0x0483 # macro -mmSDMA3_GFX_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_RPTR_HI = 0x0484 # macro -mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_WPTR = 0x0485 # macro -mmSDMA3_GFX_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_WPTR_HI = 0x0486 # macro -mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_WPTR_POLL_CNTL = 0x0487 # macro -mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_RPTR_ADDR_HI = 0x0488 # macro -mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_RPTR_ADDR_LO = 0x0489 # macro -mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_CNTL = 0x048a # macro -mmSDMA3_GFX_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_RPTR = 0x048b # macro -mmSDMA3_GFX_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_OFFSET = 0x048c # macro -mmSDMA3_GFX_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_BASE_LO = 0x048d # macro -mmSDMA3_GFX_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_BASE_HI = 0x048e # macro -mmSDMA3_GFX_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_SIZE = 0x048f # macro -mmSDMA3_GFX_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_GFX_SKIP_CNTL = 0x0490 # macro -mmSDMA3_GFX_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_CONTEXT_STATUS = 0x0491 # macro -mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_GFX_DOORBELL = 0x0492 # macro -mmSDMA3_GFX_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_GFX_CONTEXT_CNTL = 0x0493 # macro -mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_STATUS = 0x04a8 # macro -mmSDMA3_GFX_STATUS_BASE_IDX = 2 # macro -mmSDMA3_GFX_DOORBELL_LOG = 0x04a9 # macro -mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_GFX_WATERMARK = 0x04aa # macro -mmSDMA3_GFX_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_GFX_DOORBELL_OFFSET = 0x04ab # macro -mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_GFX_CSA_ADDR_LO = 0x04ac # macro -mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_GFX_CSA_ADDR_HI = 0x04ad # macro -mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_IB_SUB_REMAIN = 0x04af # macro -mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_GFX_PREEMPT = 0x04b0 # macro -mmSDMA3_GFX_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_GFX_DUMMY_REG = 0x04b1 # macro -mmSDMA3_GFX_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI = 0x04b2 # macro -mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO = 0x04b3 # macro -mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_GFX_RB_AQL_CNTL = 0x04b4 # macro -mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_GFX_MINOR_PTR_UPDATE = 0x04b5 # macro -mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA0 = 0x04c0 # macro -mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA1 = 0x04c1 # macro -mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA2 = 0x04c2 # macro -mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA3 = 0x04c3 # macro -mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA4 = 0x04c4 # macro -mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA5 = 0x04c5 # macro -mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA6 = 0x04c6 # macro -mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA7 = 0x04c7 # macro -mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA8 = 0x04c8 # macro -mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA9 = 0x04c9 # macro -mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_DATA10 = 0x04ca # macro -mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_GFX_MIDCMD_CNTL = 0x04cb # macro -mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_CNTL = 0x04d8 # macro -mmSDMA3_PAGE_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_BASE = 0x04d9 # macro -mmSDMA3_PAGE_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_BASE_HI = 0x04da # macro -mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_RPTR = 0x04db # macro -mmSDMA3_PAGE_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_RPTR_HI = 0x04dc # macro -mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_WPTR = 0x04dd # macro -mmSDMA3_PAGE_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_WPTR_HI = 0x04de # macro -mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_WPTR_POLL_CNTL = 0x04df # macro -mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_RPTR_ADDR_HI = 0x04e0 # macro -mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_RPTR_ADDR_LO = 0x04e1 # macro -mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_CNTL = 0x04e2 # macro -mmSDMA3_PAGE_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_RPTR = 0x04e3 # macro -mmSDMA3_PAGE_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_OFFSET = 0x04e4 # macro -mmSDMA3_PAGE_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_BASE_LO = 0x04e5 # macro -mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_BASE_HI = 0x04e6 # macro -mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_SIZE = 0x04e7 # macro -mmSDMA3_PAGE_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_PAGE_SKIP_CNTL = 0x04e8 # macro -mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_CONTEXT_STATUS = 0x04e9 # macro -mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_PAGE_DOORBELL = 0x04ea # macro -mmSDMA3_PAGE_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_STATUS = 0x0500 # macro -mmSDMA3_PAGE_STATUS_BASE_IDX = 2 # macro -mmSDMA3_PAGE_DOORBELL_LOG = 0x0501 # macro -mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_PAGE_WATERMARK = 0x0502 # macro -mmSDMA3_PAGE_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_PAGE_DOORBELL_OFFSET = 0x0503 # macro -mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_PAGE_CSA_ADDR_LO = 0x0504 # macro -mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_PAGE_CSA_ADDR_HI = 0x0505 # macro -mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_IB_SUB_REMAIN = 0x0507 # macro -mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_PAGE_PREEMPT = 0x0508 # macro -mmSDMA3_PAGE_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_PAGE_DUMMY_REG = 0x0509 # macro -mmSDMA3_PAGE_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI = 0x050a # macro -mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO = 0x050b # macro -mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_PAGE_RB_AQL_CNTL = 0x050c # macro -mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MINOR_PTR_UPDATE = 0x050d # macro -mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA0 = 0x0518 # macro -mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA1 = 0x0519 # macro -mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA2 = 0x051a # macro -mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA3 = 0x051b # macro -mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA4 = 0x051c # macro -mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA5 = 0x051d # macro -mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA6 = 0x051e # macro -mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA7 = 0x051f # macro -mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA8 = 0x0520 # macro -mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA9 = 0x0521 # macro -mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_DATA10 = 0x0522 # macro -mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_PAGE_MIDCMD_CNTL = 0x0523 # macro -mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_CNTL = 0x0530 # macro -mmSDMA3_RLC0_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_BASE = 0x0531 # macro -mmSDMA3_RLC0_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_BASE_HI = 0x0532 # macro -mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_RPTR = 0x0533 # macro -mmSDMA3_RLC0_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_RPTR_HI = 0x0534 # macro -mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_WPTR = 0x0535 # macro -mmSDMA3_RLC0_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_WPTR_HI = 0x0536 # macro -mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_CNTL = 0x0537 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_RPTR_ADDR_HI = 0x0538 # macro -mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_RPTR_ADDR_LO = 0x0539 # macro -mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_CNTL = 0x053a # macro -mmSDMA3_RLC0_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_RPTR = 0x053b # macro -mmSDMA3_RLC0_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_OFFSET = 0x053c # macro -mmSDMA3_RLC0_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_BASE_LO = 0x053d # macro -mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_BASE_HI = 0x053e # macro -mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_SIZE = 0x053f # macro -mmSDMA3_RLC0_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC0_SKIP_CNTL = 0x0540 # macro -mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_CONTEXT_STATUS = 0x0541 # macro -mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC0_DOORBELL = 0x0542 # macro -mmSDMA3_RLC0_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_STATUS = 0x0558 # macro -mmSDMA3_RLC0_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC0_DOORBELL_LOG = 0x0559 # macro -mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC0_WATERMARK = 0x055a # macro -mmSDMA3_RLC0_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC0_DOORBELL_OFFSET = 0x055b # macro -mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC0_CSA_ADDR_LO = 0x055c # macro -mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC0_CSA_ADDR_HI = 0x055d # macro -mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_IB_SUB_REMAIN = 0x055f # macro -mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC0_PREEMPT = 0x0560 # macro -mmSDMA3_RLC0_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC0_DUMMY_REG = 0x0561 # macro -mmSDMA3_RLC0_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0562 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0563 # macro -mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC0_RB_AQL_CNTL = 0x0564 # macro -mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MINOR_PTR_UPDATE = 0x0565 # macro -mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA0 = 0x0570 # macro -mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA1 = 0x0571 # macro -mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA2 = 0x0572 # macro -mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA3 = 0x0573 # macro -mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA4 = 0x0574 # macro -mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA5 = 0x0575 # macro -mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA6 = 0x0576 # macro -mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA7 = 0x0577 # macro -mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA8 = 0x0578 # macro -mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA9 = 0x0579 # macro -mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_DATA10 = 0x057a # macro -mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC0_MIDCMD_CNTL = 0x057b # macro -mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_CNTL = 0x0588 # macro -mmSDMA3_RLC1_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_BASE = 0x0589 # macro -mmSDMA3_RLC1_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_BASE_HI = 0x058a # macro -mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_RPTR = 0x058b # macro -mmSDMA3_RLC1_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_RPTR_HI = 0x058c # macro -mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_WPTR = 0x058d # macro -mmSDMA3_RLC1_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_WPTR_HI = 0x058e # macro -mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_WPTR_POLL_CNTL = 0x058f # macro -mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_RPTR_ADDR_HI = 0x0590 # macro -mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_RPTR_ADDR_LO = 0x0591 # macro -mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_CNTL = 0x0592 # macro -mmSDMA3_RLC1_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_RPTR = 0x0593 # macro -mmSDMA3_RLC1_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_OFFSET = 0x0594 # macro -mmSDMA3_RLC1_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_BASE_LO = 0x0595 # macro -mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_BASE_HI = 0x0596 # macro -mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_SIZE = 0x0597 # macro -mmSDMA3_RLC1_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC1_SKIP_CNTL = 0x0598 # macro -mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_CONTEXT_STATUS = 0x0599 # macro -mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC1_DOORBELL = 0x059a # macro -mmSDMA3_RLC1_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_STATUS = 0x05b0 # macro -mmSDMA3_RLC1_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC1_DOORBELL_LOG = 0x05b1 # macro -mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC1_WATERMARK = 0x05b2 # macro -mmSDMA3_RLC1_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC1_DOORBELL_OFFSET = 0x05b3 # macro -mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC1_CSA_ADDR_LO = 0x05b4 # macro -mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC1_CSA_ADDR_HI = 0x05b5 # macro -mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_IB_SUB_REMAIN = 0x05b7 # macro -mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC1_PREEMPT = 0x05b8 # macro -mmSDMA3_RLC1_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC1_DUMMY_REG = 0x05b9 # macro -mmSDMA3_RLC1_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI = 0x05ba # macro -mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO = 0x05bb # macro -mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC1_RB_AQL_CNTL = 0x05bc # macro -mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MINOR_PTR_UPDATE = 0x05bd # macro -mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA0 = 0x05c8 # macro -mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA1 = 0x05c9 # macro -mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA2 = 0x05ca # macro -mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA3 = 0x05cb # macro -mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA4 = 0x05cc # macro -mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA5 = 0x05cd # macro -mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA6 = 0x05ce # macro -mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA7 = 0x05cf # macro -mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA8 = 0x05d0 # macro -mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA9 = 0x05d1 # macro -mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_DATA10 = 0x05d2 # macro -mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC1_MIDCMD_CNTL = 0x05d3 # macro -mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_CNTL = 0x05e0 # macro -mmSDMA3_RLC2_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_BASE = 0x05e1 # macro -mmSDMA3_RLC2_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_BASE_HI = 0x05e2 # macro -mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_RPTR = 0x05e3 # macro -mmSDMA3_RLC2_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_RPTR_HI = 0x05e4 # macro -mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_WPTR = 0x05e5 # macro -mmSDMA3_RLC2_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_WPTR_HI = 0x05e6 # macro -mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_CNTL = 0x05e7 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_RPTR_ADDR_HI = 0x05e8 # macro -mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_RPTR_ADDR_LO = 0x05e9 # macro -mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_CNTL = 0x05ea # macro -mmSDMA3_RLC2_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_RPTR = 0x05eb # macro -mmSDMA3_RLC2_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_OFFSET = 0x05ec # macro -mmSDMA3_RLC2_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_BASE_LO = 0x05ed # macro -mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_BASE_HI = 0x05ee # macro -mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_SIZE = 0x05ef # macro -mmSDMA3_RLC2_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC2_SKIP_CNTL = 0x05f0 # macro -mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_CONTEXT_STATUS = 0x05f1 # macro -mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC2_DOORBELL = 0x05f2 # macro -mmSDMA3_RLC2_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_STATUS = 0x0608 # macro -mmSDMA3_RLC2_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC2_DOORBELL_LOG = 0x0609 # macro -mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC2_WATERMARK = 0x060a # macro -mmSDMA3_RLC2_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC2_DOORBELL_OFFSET = 0x060b # macro -mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC2_CSA_ADDR_LO = 0x060c # macro -mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC2_CSA_ADDR_HI = 0x060d # macro -mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_IB_SUB_REMAIN = 0x060f # macro -mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC2_PREEMPT = 0x0610 # macro -mmSDMA3_RLC2_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC2_DUMMY_REG = 0x0611 # macro -mmSDMA3_RLC2_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0612 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0613 # macro -mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC2_RB_AQL_CNTL = 0x0614 # macro -mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MINOR_PTR_UPDATE = 0x0615 # macro -mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA0 = 0x0620 # macro -mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA1 = 0x0621 # macro -mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA2 = 0x0622 # macro -mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA3 = 0x0623 # macro -mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA4 = 0x0624 # macro -mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA5 = 0x0625 # macro -mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA6 = 0x0626 # macro -mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA7 = 0x0627 # macro -mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA8 = 0x0628 # macro -mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA9 = 0x0629 # macro -mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_DATA10 = 0x062a # macro -mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC2_MIDCMD_CNTL = 0x062b # macro -mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_CNTL = 0x0638 # macro -mmSDMA3_RLC3_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_BASE = 0x0639 # macro -mmSDMA3_RLC3_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_BASE_HI = 0x063a # macro -mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_RPTR = 0x063b # macro -mmSDMA3_RLC3_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_RPTR_HI = 0x063c # macro -mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_WPTR = 0x063d # macro -mmSDMA3_RLC3_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_WPTR_HI = 0x063e # macro -mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_WPTR_POLL_CNTL = 0x063f # macro -mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_RPTR_ADDR_HI = 0x0640 # macro -mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_RPTR_ADDR_LO = 0x0641 # macro -mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_CNTL = 0x0642 # macro -mmSDMA3_RLC3_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_RPTR = 0x0643 # macro -mmSDMA3_RLC3_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_OFFSET = 0x0644 # macro -mmSDMA3_RLC3_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_BASE_LO = 0x0645 # macro -mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_BASE_HI = 0x0646 # macro -mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_SIZE = 0x0647 # macro -mmSDMA3_RLC3_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC3_SKIP_CNTL = 0x0648 # macro -mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_CONTEXT_STATUS = 0x0649 # macro -mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC3_DOORBELL = 0x064a # macro -mmSDMA3_RLC3_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_STATUS = 0x0660 # macro -mmSDMA3_RLC3_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC3_DOORBELL_LOG = 0x0661 # macro -mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC3_WATERMARK = 0x0662 # macro -mmSDMA3_RLC3_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC3_DOORBELL_OFFSET = 0x0663 # macro -mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC3_CSA_ADDR_LO = 0x0664 # macro -mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC3_CSA_ADDR_HI = 0x0665 # macro -mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_IB_SUB_REMAIN = 0x0667 # macro -mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC3_PREEMPT = 0x0668 # macro -mmSDMA3_RLC3_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC3_DUMMY_REG = 0x0669 # macro -mmSDMA3_RLC3_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI = 0x066a # macro -mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO = 0x066b # macro -mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC3_RB_AQL_CNTL = 0x066c # macro -mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MINOR_PTR_UPDATE = 0x066d # macro -mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA0 = 0x0678 # macro -mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA1 = 0x0679 # macro -mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA2 = 0x067a # macro -mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA3 = 0x067b # macro -mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA4 = 0x067c # macro -mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA5 = 0x067d # macro -mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA6 = 0x067e # macro -mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA7 = 0x067f # macro -mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA8 = 0x0680 # macro -mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA9 = 0x0681 # macro -mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_DATA10 = 0x0682 # macro -mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC3_MIDCMD_CNTL = 0x0683 # macro -mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_CNTL = 0x0690 # macro -mmSDMA3_RLC4_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_BASE = 0x0691 # macro -mmSDMA3_RLC4_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_BASE_HI = 0x0692 # macro -mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_RPTR = 0x0693 # macro -mmSDMA3_RLC4_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_RPTR_HI = 0x0694 # macro -mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_WPTR = 0x0695 # macro -mmSDMA3_RLC4_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_WPTR_HI = 0x0696 # macro -mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_CNTL = 0x0697 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_RPTR_ADDR_HI = 0x0698 # macro -mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_RPTR_ADDR_LO = 0x0699 # macro -mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_CNTL = 0x069a # macro -mmSDMA3_RLC4_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_RPTR = 0x069b # macro -mmSDMA3_RLC4_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_OFFSET = 0x069c # macro -mmSDMA3_RLC4_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_BASE_LO = 0x069d # macro -mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_BASE_HI = 0x069e # macro -mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_SIZE = 0x069f # macro -mmSDMA3_RLC4_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC4_SKIP_CNTL = 0x06a0 # macro -mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_CONTEXT_STATUS = 0x06a1 # macro -mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC4_DOORBELL = 0x06a2 # macro -mmSDMA3_RLC4_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_STATUS = 0x06b8 # macro -mmSDMA3_RLC4_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC4_DOORBELL_LOG = 0x06b9 # macro -mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC4_WATERMARK = 0x06ba # macro -mmSDMA3_RLC4_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC4_DOORBELL_OFFSET = 0x06bb # macro -mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC4_CSA_ADDR_LO = 0x06bc # macro -mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC4_CSA_ADDR_HI = 0x06bd # macro -mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_IB_SUB_REMAIN = 0x06bf # macro -mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC4_PREEMPT = 0x06c0 # macro -mmSDMA3_RLC4_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC4_DUMMY_REG = 0x06c1 # macro -mmSDMA3_RLC4_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI = 0x06c2 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO = 0x06c3 # macro -mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC4_RB_AQL_CNTL = 0x06c4 # macro -mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MINOR_PTR_UPDATE = 0x06c5 # macro -mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA0 = 0x06d0 # macro -mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA1 = 0x06d1 # macro -mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA2 = 0x06d2 # macro -mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA3 = 0x06d3 # macro -mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA4 = 0x06d4 # macro -mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA5 = 0x06d5 # macro -mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA6 = 0x06d6 # macro -mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA7 = 0x06d7 # macro -mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA8 = 0x06d8 # macro -mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA9 = 0x06d9 # macro -mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_DATA10 = 0x06da # macro -mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC4_MIDCMD_CNTL = 0x06db # macro -mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_CNTL = 0x06e8 # macro -mmSDMA3_RLC5_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_BASE = 0x06e9 # macro -mmSDMA3_RLC5_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_BASE_HI = 0x06ea # macro -mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_RPTR = 0x06eb # macro -mmSDMA3_RLC5_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_RPTR_HI = 0x06ec # macro -mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_WPTR = 0x06ed # macro -mmSDMA3_RLC5_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_WPTR_HI = 0x06ee # macro -mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_WPTR_POLL_CNTL = 0x06ef # macro -mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_RPTR_ADDR_HI = 0x06f0 # macro -mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_RPTR_ADDR_LO = 0x06f1 # macro -mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_CNTL = 0x06f2 # macro -mmSDMA3_RLC5_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_RPTR = 0x06f3 # macro -mmSDMA3_RLC5_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_OFFSET = 0x06f4 # macro -mmSDMA3_RLC5_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_BASE_LO = 0x06f5 # macro -mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_BASE_HI = 0x06f6 # macro -mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_SIZE = 0x06f7 # macro -mmSDMA3_RLC5_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC5_SKIP_CNTL = 0x06f8 # macro -mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_CONTEXT_STATUS = 0x06f9 # macro -mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC5_DOORBELL = 0x06fa # macro -mmSDMA3_RLC5_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_STATUS = 0x0710 # macro -mmSDMA3_RLC5_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC5_DOORBELL_LOG = 0x0711 # macro -mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC5_WATERMARK = 0x0712 # macro -mmSDMA3_RLC5_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC5_DOORBELL_OFFSET = 0x0713 # macro -mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC5_CSA_ADDR_LO = 0x0714 # macro -mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC5_CSA_ADDR_HI = 0x0715 # macro -mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_IB_SUB_REMAIN = 0x0717 # macro -mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC5_PREEMPT = 0x0718 # macro -mmSDMA3_RLC5_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC5_DUMMY_REG = 0x0719 # macro -mmSDMA3_RLC5_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI = 0x071a # macro -mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO = 0x071b # macro -mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC5_RB_AQL_CNTL = 0x071c # macro -mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MINOR_PTR_UPDATE = 0x071d # macro -mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA0 = 0x0728 # macro -mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA1 = 0x0729 # macro -mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA2 = 0x072a # macro -mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA3 = 0x072b # macro -mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA4 = 0x072c # macro -mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA5 = 0x072d # macro -mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA6 = 0x072e # macro -mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA7 = 0x072f # macro -mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA8 = 0x0730 # macro -mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA9 = 0x0731 # macro -mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_DATA10 = 0x0732 # macro -mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC5_MIDCMD_CNTL = 0x0733 # macro -mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_CNTL = 0x0740 # macro -mmSDMA3_RLC6_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_BASE = 0x0741 # macro -mmSDMA3_RLC6_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_BASE_HI = 0x0742 # macro -mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_RPTR = 0x0743 # macro -mmSDMA3_RLC6_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_RPTR_HI = 0x0744 # macro -mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_WPTR = 0x0745 # macro -mmSDMA3_RLC6_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_WPTR_HI = 0x0746 # macro -mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_CNTL = 0x0747 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_RPTR_ADDR_HI = 0x0748 # macro -mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_RPTR_ADDR_LO = 0x0749 # macro -mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_CNTL = 0x074a # macro -mmSDMA3_RLC6_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_RPTR = 0x074b # macro -mmSDMA3_RLC6_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_OFFSET = 0x074c # macro -mmSDMA3_RLC6_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_BASE_LO = 0x074d # macro -mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_BASE_HI = 0x074e # macro -mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_SIZE = 0x074f # macro -mmSDMA3_RLC6_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC6_SKIP_CNTL = 0x0750 # macro -mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_CONTEXT_STATUS = 0x0751 # macro -mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC6_DOORBELL = 0x0752 # macro -mmSDMA3_RLC6_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_STATUS = 0x0768 # macro -mmSDMA3_RLC6_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC6_DOORBELL_LOG = 0x0769 # macro -mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC6_WATERMARK = 0x076a # macro -mmSDMA3_RLC6_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC6_DOORBELL_OFFSET = 0x076b # macro -mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC6_CSA_ADDR_LO = 0x076c # macro -mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC6_CSA_ADDR_HI = 0x076d # macro -mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_IB_SUB_REMAIN = 0x076f # macro -mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC6_PREEMPT = 0x0770 # macro -mmSDMA3_RLC6_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC6_DUMMY_REG = 0x0771 # macro -mmSDMA3_RLC6_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0772 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0773 # macro -mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC6_RB_AQL_CNTL = 0x0774 # macro -mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MINOR_PTR_UPDATE = 0x0775 # macro -mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA0 = 0x0780 # macro -mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA1 = 0x0781 # macro -mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA2 = 0x0782 # macro -mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA3 = 0x0783 # macro -mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA4 = 0x0784 # macro -mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA5 = 0x0785 # macro -mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA6 = 0x0786 # macro -mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA7 = 0x0787 # macro -mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA8 = 0x0788 # macro -mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA9 = 0x0789 # macro -mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_DATA10 = 0x078a # macro -mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC6_MIDCMD_CNTL = 0x078b # macro -mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_CNTL = 0x0798 # macro -mmSDMA3_RLC7_RB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_BASE = 0x0799 # macro -mmSDMA3_RLC7_RB_BASE_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_BASE_HI = 0x079a # macro -mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_RPTR = 0x079b # macro -mmSDMA3_RLC7_RB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_RPTR_HI = 0x079c # macro -mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_WPTR = 0x079d # macro -mmSDMA3_RLC7_RB_WPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_WPTR_HI = 0x079e # macro -mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_WPTR_POLL_CNTL = 0x079f # macro -mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_RPTR_ADDR_HI = 0x07a0 # macro -mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_RPTR_ADDR_LO = 0x07a1 # macro -mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_CNTL = 0x07a2 # macro -mmSDMA3_RLC7_IB_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_RPTR = 0x07a3 # macro -mmSDMA3_RLC7_IB_RPTR_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_OFFSET = 0x07a4 # macro -mmSDMA3_RLC7_IB_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_BASE_LO = 0x07a5 # macro -mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_BASE_HI = 0x07a6 # macro -mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_SIZE = 0x07a7 # macro -mmSDMA3_RLC7_IB_SIZE_BASE_IDX = 2 # macro -mmSDMA3_RLC7_SKIP_CNTL = 0x07a8 # macro -mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_CONTEXT_STATUS = 0x07a9 # macro -mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC7_DOORBELL = 0x07aa # macro -mmSDMA3_RLC7_DOORBELL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_STATUS = 0x07c0 # macro -mmSDMA3_RLC7_STATUS_BASE_IDX = 2 # macro -mmSDMA3_RLC7_DOORBELL_LOG = 0x07c1 # macro -mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro -mmSDMA3_RLC7_WATERMARK = 0x07c2 # macro -mmSDMA3_RLC7_WATERMARK_BASE_IDX = 2 # macro -mmSDMA3_RLC7_DOORBELL_OFFSET = 0x07c3 # macro -mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro -mmSDMA3_RLC7_CSA_ADDR_LO = 0x07c4 # macro -mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC7_CSA_ADDR_HI = 0x07c5 # macro -mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_IB_SUB_REMAIN = 0x07c7 # macro -mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro -mmSDMA3_RLC7_PREEMPT = 0x07c8 # macro -mmSDMA3_RLC7_PREEMPT_BASE_IDX = 2 # macro -mmSDMA3_RLC7_DUMMY_REG = 0x07c9 # macro -mmSDMA3_RLC7_DUMMY_REG_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI = 0x07ca # macro -mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO = 0x07cb # macro -mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro -mmSDMA3_RLC7_RB_AQL_CNTL = 0x07cc # macro -mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MINOR_PTR_UPDATE = 0x07cd # macro -mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA0 = 0x07d8 # macro -mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA1 = 0x07d9 # macro -mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA2 = 0x07da # macro -mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA3 = 0x07db # macro -mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA4 = 0x07dc # macro -mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA5 = 0x07dd # macro -mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA6 = 0x07de # macro -mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA7 = 0x07df # macro -mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA8 = 0x07e0 # macro -mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA9 = 0x07e1 # macro -mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_DATA10 = 0x07e2 # macro -mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro -mmSDMA3_RLC7_MIDCMD_CNTL = 0x07e3 # macro -mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro -ixPCC_STALL_PATTERN_CTRL = 0x0000 # macro -ixPWRBRK_STALL_PATTERN_CTRL = 0x0001 # macro -ixPCC_STALL_PATTERN_1_2 = 0x0006 # macro -ixPCC_STALL_PATTERN_3_4 = 0x0007 # macro -ixPCC_STALL_PATTERN_5_6 = 0x0008 # macro -ixPCC_STALL_PATTERN_7 = 0x0009 # macro -ixPWRBRK_STALL_PATTERN_1_2 = 0x000a # macro -ixPWRBRK_STALL_PATTERN_3_4 = 0x000b # macro -ixPWRBRK_STALL_PATTERN_5_6 = 0x000c # macro -ixPWRBRK_STALL_PATTERN_7 = 0x000d # macro -ixPCC_PWRBRK_HYSTERESIS_CTRL = 0x000e # macro -ixEDC_STRETCH_PERF_COUNTER = 0x000f # macro -ixEDC_UNSTRETCH_PERF_COUNTER = 0x0010 # macro -ixEDC_STRETCH_NUM_PERF_COUNTER = 0x0011 # macro -ixGC_CAC_OVR_SEL = 0x0022 # macro -ixGC_CAC_OVR_VAL = 0x0023 # macro -ixGC_CAC_WEIGHT_BCI_0 = 0x0024 # macro -ixGC_CAC_WEIGHT_CB_0 = 0x0025 # macro -ixGC_CAC_WEIGHT_CB_1 = 0x0026 # macro -ixGC_CAC_WEIGHT_CB_2 = 0x0027 # macro -ixGC_CAC_WEIGHT_CB_3 = 0x0028 # macro -ixGC_CAC_WEIGHT_CB_4 = 0x0029 # macro -ixGC_CAC_WEIGHT_CP_0 = 0x002a # macro -ixGC_CAC_WEIGHT_CP_1 = 0x002b # macro -ixGC_CAC_WEIGHT_DB_0 = 0x002c # macro -ixGC_CAC_WEIGHT_DB_1 = 0x002d # macro -ixGC_CAC_WEIGHT_DB_2 = 0x002e # macro -ixGC_CAC_WEIGHT_DB_3 = 0x002f # macro -ixGC_CAC_WEIGHT_DB_4 = 0x0030 # macro -ixGC_CAC_WEIGHT_GDS_0 = 0x0031 # macro -ixGC_CAC_WEIGHT_GDS_1 = 0x0032 # macro -ixGC_CAC_WEIGHT_GDS_2 = 0x0033 # macro -ixGC_CAC_WEIGHT_LDS_0 = 0x0034 # macro -ixGC_CAC_WEIGHT_LDS_1 = 0x0035 # macro -ixGC_CAC_WEIGHT_LDS_2 = 0x0036 # macro -ixGC_CAC_WEIGHT_LDS_3 = 0x0037 # macro -ixGC_CAC_WEIGHT_LDS_4 = 0x0038 # macro -ixGC_CAC_WEIGHT_PA_0 = 0x0039 # macro -ixGC_CAC_WEIGHT_PA_1 = 0x003a # macro -ixGC_CAC_WEIGHT_PA_2 = 0x003b # macro -ixGC_CAC_WEIGHT_PA_3 = 0x003c # macro -ixGC_CAC_WEIGHT_PC_0 = 0x003d # macro -ixGC_CAC_WEIGHT_SC_0 = 0x003e # macro -ixGC_CAC_WEIGHT_SC_1 = 0x003f # macro -ixGC_CAC_WEIGHT_SC_2 = 0x0040 # macro -ixGC_CAC_WEIGHT_SC_3 = 0x0041 # macro -ixGC_CAC_WEIGHT_SPI_0 = 0x0042 # macro -ixGC_CAC_WEIGHT_SPI_1 = 0x0043 # macro -ixGC_CAC_WEIGHT_SPI_2 = 0x0044 # macro -ixGC_CAC_WEIGHT_SQ_0 = 0x0045 # macro -ixGC_CAC_WEIGHT_SQ_1 = 0x0046 # macro -ixGC_CAC_WEIGHT_SQ_2 = 0x0047 # macro -ixGC_CAC_WEIGHT_SQ_3 = 0x0048 # macro -ixGC_CAC_WEIGHT_SX_0 = 0x0049 # macro -ixGC_CAC_WEIGHT_SXRB_0 = 0x004a # macro -ixGC_CAC_WEIGHT_TA_0 = 0x004b # macro -ixGC_CAC_WEIGHT_TCP_0 = 0x004c # macro -ixGC_CAC_WEIGHT_TCP_1 = 0x004d # macro -ixGC_CAC_WEIGHT_TCP_2 = 0x004e # macro -ixGC_CAC_WEIGHT_TCP_3 = 0x004f # macro -ixGC_CAC_WEIGHT_TD_0 = 0x0050 # macro -ixGC_CAC_WEIGHT_TD_1 = 0x0051 # macro -ixGC_CAC_WEIGHT_TD_2 = 0x0052 # macro -ixGC_CAC_WEIGHT_TD_3 = 0x0053 # macro -ixGC_CAC_WEIGHT_TD_4 = 0x0054 # macro -ixGC_CAC_WEIGHT_TD_5 = 0x0055 # macro -ixGC_CAC_WEIGHT_RMI_0 = 0x0056 # macro -ixGC_CAC_WEIGHT_RMI_1 = 0x0057 # macro -ixGC_CAC_WEIGHT_EA_0 = 0x0058 # macro -ixGC_CAC_WEIGHT_EA_1 = 0x0059 # macro -ixGC_CAC_WEIGHT_EA_2 = 0x005a # macro -ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 = 0x005b # macro -ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 = 0x005c # macro -ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 = 0x005d # macro -ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x005e # macro -ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x005f # macro -ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x0060 # macro -ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x0061 # macro -ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x0062 # macro -ixGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x0063 # macro -ixGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x0064 # macro -ixGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x0065 # macro -ixGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x0066 # macro -ixGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x0067 # macro -ixGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x0068 # macro -ixGC_CAC_WEIGHT_CU_0 = 0x0069 # macro -ixGC_CAC_WEIGHT_UTCL1_0 = 0x006a # macro -ixGC_CAC_WEIGHT_GE_0 = 0x006b # macro -ixGC_CAC_WEIGHT_GE_1 = 0x006c # macro -ixGC_CAC_WEIGHT_GE_2 = 0x006d # macro -ixGC_CAC_WEIGHT_GE_3 = 0x006e # macro -ixGC_CAC_WEIGHT_GE_4 = 0x006f # macro -ixGC_CAC_WEIGHT_GE_5 = 0x0070 # macro -ixGC_CAC_WEIGHT_GE_6 = 0x0071 # macro -ixGC_CAC_WEIGHT_GE_7 = 0x0072 # macro -ixGC_CAC_WEIGHT_GE_8 = 0x0073 # macro -ixGC_CAC_WEIGHT_GE_9 = 0x0074 # macro -ixGC_CAC_WEIGHT_GE_10 = 0x0075 # macro -ixGC_CAC_WEIGHT_PMM_0 = 0x0076 # macro -ixGC_CAC_WEIGHT_GL2C_0 = 0x0077 # macro -ixGC_CAC_WEIGHT_GL2C_1 = 0x0078 # macro -ixGC_CAC_WEIGHT_GL2C_2 = 0x0079 # macro -ixGC_CAC_WEIGHT_GUS_0 = 0x007a # macro -ixGC_CAC_WEIGHT_GUS_1 = 0x007b # macro -ixGC_CAC_WEIGHT_PH_0 = 0x007c # macro -ixGC_CAC_WEIGHT_PH_1 = 0x007d # macro -ixGC_CAC_WEIGHT_PH_2 = 0x007e # macro -ixGC_CAC_WEIGHT_PH_3 = 0x007f # macro -ixGC_CAC_WEIGHT_SDMA_0 = 0x0080 # macro -ixGC_CAC_WEIGHT_SDMA_1 = 0x0081 # macro -ixGC_CAC_WEIGHT_SDMA_2 = 0x0082 # macro -ixGC_CAC_WEIGHT_SDMA_3 = 0x0083 # macro -ixGC_CAC_WEIGHT_SDMA_4 = 0x0084 # macro -ixGC_CAC_WEIGHT_SDMA_5 = 0x0085 # macro -ixGC_CAC_WEIGHT_SP_0 = 0x0086 # macro -ixGC_CAC_WEIGHT_SP_1 = 0x0087 # macro -ixGC_CAC_WEIGHT_GL1C_0 = 0x0088 # macro -ixGC_CAC_WEIGHT_GL1C_1 = 0x0089 # macro -ixGC_CAC_WEIGHT_GL1C_2 = 0x008a # macro -ixGC_CAC_WEIGHT_CHC_0 = 0x008b # macro -ixGC_CAC_WEIGHT_CHC_1 = 0x008c # macro -ixGC_CAC_WEIGHT_SQC_0 = 0x008d # macro -ixGC_CAC_WEIGHT_SQC_1 = 0x008e # macro -ixGC_CAC_WEIGHT_RLC_0 = 0x008f # macro -ixGC_CAC_ACC_LDS0 = 0x0100 # macro -ixGC_CAC_ACC_LDS1 = 0x0101 # macro -ixGC_CAC_ACC_LDS2 = 0x0102 # macro -ixGC_CAC_ACC_LDS3 = 0x0103 # macro -ixGC_CAC_ACC_LDS4 = 0x0104 # macro -ixGC_CAC_ACC_LDS5 = 0x0105 # macro -ixGC_CAC_ACC_LDS6 = 0x0106 # macro -ixGC_CAC_ACC_LDS7 = 0x0107 # macro -ixGC_CAC_ACC_LDS8 = 0x0108 # macro -ixGC_CAC_ACC_BCI0 = 0x0109 # macro -ixGC_CAC_ACC_BCI1 = 0x010a # macro -ixGC_CAC_ACC_CB0 = 0x010b # macro -ixGC_CAC_ACC_CB1 = 0x010c # macro -ixGC_CAC_ACC_CB2 = 0x010d # macro -ixGC_CAC_ACC_CB3 = 0x010e # macro -ixGC_CAC_ACC_CB4 = 0x010f # macro -ixGC_CAC_ACC_CB5 = 0x0110 # macro -ixGC_CAC_ACC_CB6 = 0x0111 # macro -ixGC_CAC_ACC_CB7 = 0x0112 # macro -ixGC_CAC_ACC_CB8 = 0x0113 # macro -ixGC_CAC_ACC_CB9 = 0x0114 # macro -ixGC_CAC_ACC_DB0 = 0x0118 # macro -ixGC_CAC_ACC_DB1 = 0x0119 # macro -ixGC_CAC_ACC_DB2 = 0x011a # macro -ixGC_CAC_ACC_DB3 = 0x011b # macro -ixGC_CAC_ACC_DB4 = 0x011c # macro -ixGC_CAC_ACC_DB5 = 0x011d # macro -ixGC_CAC_ACC_DB6 = 0x011e # macro -ixGC_CAC_ACC_DB7 = 0x011f # macro -ixGC_CAC_ACC_DB8 = 0x0120 # macro -ixGC_CAC_ACC_DB9 = 0x0121 # macro -ixGC_CAC_ACC_GDS5 = 0x0127 # macro -ixGC_CAC_ACC_GDS6 = 0x0128 # macro -ixGC_CAC_ACC_PA0 = 0x0129 # macro -ixGC_CAC_ACC_PA1 = 0x012a # macro -ixGC_CAC_ACC_PA2 = 0x012b # macro -ixGC_CAC_ACC_PA3 = 0x012c # macro -ixGC_CAC_ACC_PA4 = 0x012d # macro -ixGC_CAC_ACC_PA5 = 0x012e # macro -ixGC_CAC_ACC_PA6 = 0x012f # macro -ixGC_CAC_ACC_PA7 = 0x0130 # macro -ixGC_CAC_ACC_PC0 = 0x0131 # macro -ixGC_CAC_ACC_SC0 = 0x0132 # macro -ixGC_CAC_ACC_SC1 = 0x0133 # macro -ixGC_CAC_ACC_SC2 = 0x0134 # macro -ixGC_CAC_ACC_SC3 = 0x0135 # macro -ixGC_CAC_ACC_SC4 = 0x0136 # macro -ixGC_CAC_ACC_SC5 = 0x0137 # macro -ixGC_CAC_ACC_SC6 = 0x0138 # macro -ixGC_CAC_ACC_SC7 = 0x0139 # macro -ixGC_CAC_ACC_SPI0 = 0x013a # macro -ixGC_CAC_ACC_SPI1 = 0x013b # macro -ixGC_CAC_ACC_SPI2 = 0x013c # macro -ixGC_CAC_ACC_SPI3 = 0x013d # macro -ixGC_CAC_ACC_SPI4 = 0x013e # macro -ixGC_CAC_ACC_SPI5 = 0x013f # macro -ixGC_CAC_ACC_SQ0_LOWER = 0x0140 # macro -ixGC_CAC_ACC_SQ0_UPPER = 0x0141 # macro -ixGC_CAC_ACC_SQ1_LOWER = 0x0142 # macro -ixGC_CAC_ACC_SQ1_UPPER = 0x0143 # macro -ixGC_CAC_ACC_SQ2_LOWER = 0x0144 # macro -ixGC_CAC_ACC_SQ2_UPPER = 0x0145 # macro -ixGC_CAC_ACC_SQ3_LOWER = 0x0146 # macro -ixGC_CAC_ACC_SQ3_UPPER = 0x0147 # macro -ixGC_CAC_ACC_SQ4_LOWER = 0x0148 # macro -ixGC_CAC_ACC_SQ4_UPPER = 0x0149 # macro -ixGC_CAC_ACC_SQ5_LOWER = 0x014a # macro -ixGC_CAC_ACC_SQ5_UPPER = 0x014b # macro -ixGC_CAC_ACC_SQ6_LOWER = 0x014c # macro -ixGC_CAC_ACC_SQ6_UPPER = 0x014d # macro -ixGC_CAC_ACC_SQ7_LOWER = 0x014e # macro -ixGC_CAC_ACC_SQ7_UPPER = 0x014f # macro -ixGC_CAC_ACC_SQ8_LOWER = 0x0150 # macro -ixGC_CAC_ACC_SQ8_UPPER = 0x0151 # macro -ixGC_CAC_ACC_SX0 = 0x0152 # macro -ixGC_CAC_ACC_SXRB0 = 0x0153 # macro -ixGC_CAC_ACC_TA0 = 0x0154 # macro -ixGC_CAC_ACC_TCP0 = 0x0155 # macro -ixGC_CAC_ACC_TCP1 = 0x0156 # macro -ixGC_CAC_ACC_TCP2 = 0x0157 # macro -ixGC_CAC_ACC_TCP3 = 0x0158 # macro -ixGC_CAC_ACC_TCP4 = 0x0159 # macro -ixGC_CAC_ACC_TCP5 = 0x015a # macro -ixGC_CAC_ACC_TCP6 = 0x015b # macro -ixGC_CAC_ACC_TCP7 = 0x015c # macro -ixGC_CAC_ACC_TD0 = 0x015d # macro -ixGC_CAC_ACC_TD1 = 0x015e # macro -ixGC_CAC_ACC_TD2 = 0x015f # macro -ixGC_CAC_ACC_TD3 = 0x0160 # macro -ixGC_CAC_ACC_TD4 = 0x0161 # macro -ixGC_CAC_ACC_TD5 = 0x0162 # macro -ixGC_CAC_ACC_TD6 = 0x0163 # macro -ixGC_CAC_ACC_TD7 = 0x0164 # macro -ixGC_CAC_ACC_TD8 = 0x0165 # macro -ixGC_CAC_ACC_TD9 = 0x0166 # macro -ixGC_CAC_ACC_TD10 = 0x0167 # macro -ixGC_CAC_ACC_RMI0 = 0x0168 # macro -ixGC_CAC_ACC_RMI1 = 0x0169 # macro -ixGC_CAC_ACC_RMI2 = 0x016a # macro -ixGC_CAC_ACC_RMI3 = 0x016b # macro -ixGC_CAC_ACC_UTCL2_ATCL20 = 0x0172 # macro -ixGC_CAC_ACC_UTCL2_ATCL21 = 0x0173 # macro -ixGC_CAC_ACC_UTCL2_ATCL22 = 0x0174 # macro -ixGC_CAC_ACC_UTCL2_ATCL23 = 0x0175 # macro -ixGC_CAC_ACC_UTCL2_ATCL24 = 0x0176 # macro -ixGC_CAC_ACC_CU0 = 0x018b # macro -ixGC_CAC_ACC_UTCL10 = 0x018c # macro -ixGC_CAC_ACC_SP0_LOWER = 0x01c2 # macro -ixGC_CAC_ACC_SP0_UPPER = 0x01c3 # macro -ixGC_CAC_ACC_SP1_LOWER = 0x01c4 # macro -ixGC_CAC_ACC_SP1_UPPER = 0x01c5 # macro -ixGC_CAC_ACC_SP2_LOWER = 0x01c6 # macro -ixGC_CAC_ACC_SP2_UPPER = 0x01c7 # macro -ixGC_CAC_ACC_GL1C0 = 0x01c8 # macro -ixGC_CAC_ACC_GL1C1 = 0x01c9 # macro -ixGC_CAC_ACC_GL1C2 = 0x01ca # macro -ixGC_CAC_ACC_GL1C3 = 0x01cb # macro -ixGC_CAC_ACC_GL1C4 = 0x01cc # macro -ixGC_CAC_ACC_SQC0 = 0x01cd # macro -ixGC_CAC_ACC_SQC1 = 0x01ce # macro -ixGC_CAC_ACC_SQC2 = 0x01cf # macro -ixGC_CAC_OVRD_BCI = 0x0200 # macro -ixGC_CAC_OVRD_CB = 0x0201 # macro -ixGC_CAC_OVRD_CP = 0x0203 # macro -ixGC_CAC_OVRD_DB = 0x0204 # macro -ixGC_CAC_OVRD_GDS = 0x0206 # macro -ixGC_CAC_OVRD_LDS = 0x0207 # macro -ixGC_CAC_OVRD_PA = 0x0208 # macro -ixGC_CAC_OVRD_PC = 0x0209 # macro -ixGC_CAC_OVRD_SC = 0x020a # macro -ixGC_CAC_OVRD_SPI = 0x020b # macro -ixGC_CAC_OVRD_CU = 0x020c # macro -ixGC_CAC_OVRD_SQ = 0x020d # macro -ixGC_CAC_OVRD_SX = 0x020e # macro -ixGC_CAC_OVRD_SXRB = 0x020f # macro -ixGC_CAC_OVRD_TA = 0x0210 # macro -ixGC_CAC_OVRD_TCP = 0x0211 # macro -ixGC_CAC_OVRD_TD = 0x0212 # macro -ixGC_CAC_OVRD_RMI = 0x0213 # macro -ixGC_CAC_OVRD_EA = 0x0214 # macro -ixGC_CAC_OVRD_UTCL2_ATCL2 = 0x0215 # macro -ixGC_CAC_OVRD_UTCL2_ROUTER = 0x0216 # macro -ixGC_CAC_OVRD_UTCL2_VML2 = 0x0217 # macro -ixGC_CAC_OVRD_UTCL2_WALKER = 0x0218 # macro -ixGC_CAC_OVRD_SP = 0x0219 # macro -ixGC_CAC_OVRD_UTCL1 = 0x021a # macro -ixGC_CAC_OVRD_CHC = 0x021b # macro -ixGC_CAC_OVRD_GE = 0x021c # macro -ixGC_CAC_OVRD_PMM = 0x021d # macro -ixGC_CAC_OVRD_GL2C = 0x021e # macro -ixGC_CAC_OVRD_GUS = 0x021f # macro -ixGC_CAC_OVRD_PH = 0x0220 # macro -ixGC_CAC_OVRD_SDMA = 0x0221 # macro -ixGC_CAC_OVRD_GL1C = 0x0222 # macro -ixGC_CAC_OVRD_SQC = 0x0223 # macro -ixGC_CAC_OVRD_RLC = 0x0224 # macro -ixGC_CAC_OVRD_GE_HI = 0x0225 # macro -ixSE_CAC_OVR_SEL = 0x0002 # macro -ixSE_CAC_OVR_VAL = 0x0003 # macro -ixGLB_CPG_SAMPLEDELAY = 0x0000 # macro -ixGLB_CPC_SAMPLEDELAY = 0x0001 # macro -ixGLB_CPF_SAMPLEDELAY = 0x0002 # macro -ixGLB_GDS_SAMPLEDELAY = 0x0003 # macro -ixGLB_GCR_SAMPLEDELAY = 0x0004 # macro -ixGLB_PH_SAMPLEDELAY = 0x0005 # macro -ixGLB_GE1_SAMPLEDELAY = 0x0006 # macro -ixGLB_GE2DIST_SAMPLEDELAY = 0x0007 # macro -ixGLB_GUS_SAMPLEDELAY = 0x0008 # macro -ixGLB_CHA_SAMPLEDELAY = 0x0009 # macro -ixGLB_CHCG_SAMPLEDELAY = 0x000a # macro -ixGLB_ATCL2_SAMPLEDELAY = 0x000b # macro -ixGLB_VML2_SAMPLEDELAY = 0x000c # macro -ixGLB_SDMA0_SAMPLEDELAY = 0x000d # macro -ixGLB_SDMA1_SAMPLEDELAY = 0x000e # macro -ixGLB_SDMA2_SAMPLEDELAY = 0x000f # macro -ixGLB_SDMA3_SAMPLEDELAY = 0x0010 # macro -ixGLB_GL2A0_SAMPLEDELAY = 0x0011 # macro -ixGLB_GL2A1_SAMPLEDELAY = 0x0012 # macro -ixGLB_GL2A2_SAMPLEDELAY = 0x0013 # macro -ixGLB_GL2A3_SAMPLEDELAY = 0x0014 # macro -ixGLB_GL2C0_SAMPLEDELAY = 0x0015 # macro -ixGLB_GL2C1_SAMPLEDELAY = 0x0016 # macro -ixGLB_GL2C2_SAMPLEDELAY = 0x0017 # macro -ixGLB_GL2C3_SAMPLEDELAY = 0x0018 # macro -ixGLB_GL2C4_SAMPLEDELAY = 0x0019 # macro -ixGLB_GL2C5_SAMPLEDELAY = 0x001a # macro -ixGLB_GL2C6_SAMPLEDELAY = 0x001b # macro -ixGLB_GL2C7_SAMPLEDELAY = 0x001c # macro -ixGLB_GL2C8_SAMPLEDELAY = 0x001d # macro -ixGLB_GL2C9_SAMPLEDELAY = 0x001e # macro -ixGLB_GL2C10_SAMPLEDELAY = 0x001f # macro -ixGLB_GL2C11_SAMPLEDELAY = 0x0020 # macro -ixGLB_GL2C12_SAMPLEDELAY = 0x0021 # macro -ixGLB_GL2C13_SAMPLEDELAY = 0x0022 # macro -ixGLB_GL2C14_SAMPLEDELAY = 0x0023 # macro -ixGLB_GL2C15_SAMPLEDELAY = 0x0024 # macro -ixGLB_EA0_SAMPLEDELAY = 0x0025 # macro -ixGLB_EA1_SAMPLEDELAY = 0x0026 # macro -ixGLB_EA2_SAMPLEDELAY = 0x0027 # macro -ixGLB_EA3_SAMPLEDELAY = 0x0028 # macro -ixGLB_EA4_SAMPLEDELAY = 0x0029 # macro -ixGLB_EA5_SAMPLEDELAY = 0x002a # macro -ixGLB_EA6_SAMPLEDELAY = 0x002b # macro -ixGLB_EA7_SAMPLEDELAY = 0x002c # macro -ixGLB_EA8_SAMPLEDELAY = 0x002d # macro -ixGLB_EA9_SAMPLEDELAY = 0x002e # macro -ixGLB_EA10_SAMPLEDELAY = 0x002f # macro -ixGLB_EA11_SAMPLEDELAY = 0x0030 # macro -ixGLB_EA12_SAMPLEDELAY = 0x0031 # macro -ixGLB_EA13_SAMPLEDELAY = 0x0032 # macro -ixGLB_EA14_SAMPLEDELAY = 0x0033 # macro -ixGLB_EA15_SAMPLEDELAY = 0x0034 # macro -ixGLB_CHC0_SAMPLEDELAY = 0x0035 # macro -ixGLB_CHC1_SAMPLEDELAY = 0x0036 # macro -ixGLB_CHC2_SAMPLEDELAY = 0x0037 # macro -ixGLB_CHC3_SAMPLEDELAY = 0x0038 # macro -ixGLB_GE2SE0_SAMPLEDELAY = 0x0039 # macro -ixGLB_GE2SE1_SAMPLEDELAY = 0x003a # macro -ixGLB_GE2SE2_SAMPLEDELAY = 0x003b # macro -ixGLB_GE2SE3_SAMPLEDELAY = 0x003c # macro -ixSE_SPI_SAMPLEDELAY = 0x0000 # macro -ixSE_SQG_SAMPLEDELAY = 0x0001 # macro -ixSE_CBR_SAMPLEDELAY = 0x0002 # macro -ixSE_DBR_SAMPLEDELAY = 0x0003 # macro -ixSE_PA_SAMPLEDELAY = 0x0004 # macro -ixSE_SA0SX_SAMPLEDELAY = 0x0005 # macro -ixSE_SA0GL1A_SAMPLEDELAY = 0x0006 # macro -ixSE_SA0GL1CG_SAMPLEDELAY = 0x0007 # macro -ixSE_SA0CB0_SAMPLEDELAY = 0x0008 # macro -ixSE_SA0CB1_SAMPLEDELAY = 0x0009 # macro -ixSE_SA0DB0_SAMPLEDELAY = 0x000a # macro -ixSE_SA0DB1_SAMPLEDELAY = 0x000b # macro -ixSE_SA0SC0_SAMPLEDELAY = 0x000c # macro -ixSE_SA0SC1_SAMPLEDELAY = 0x000d # macro -ixSE_SA0RMI0_SAMPLEDELAY = 0x000e # macro -ixSE_SA0RMI1_SAMPLEDELAY = 0x000f # macro -ixSE_SA0GL1C0_SAMPLEDELAY = 0x0010 # macro -ixSE_SA0GL1C1_SAMPLEDELAY = 0x0011 # macro -ixSE_SA0GL1C2_SAMPLEDELAY = 0x0012 # macro -ixSE_SA0GL1C3_SAMPLEDELAY = 0x0013 # macro -ixSE_SA0WGP00TA0_SAMPLEDELAY = 0x0014 # macro -ixSE_SA0WGP00TA1_SAMPLEDELAY = 0x0015 # macro -ixSE_SA0WGP00TD0_SAMPLEDELAY = 0x0016 # macro -ixSE_SA0WGP00TD1_SAMPLEDELAY = 0x0017 # macro -ixSE_SA0WGP00TCP0_SAMPLEDELAY = 0x0018 # macro -ixSE_SA0WGP00TCP1_SAMPLEDELAY = 0x0019 # macro -ixSE_SA0WGP01TA0_SAMPLEDELAY = 0x001a # macro -ixSE_SA0WGP01TA1_SAMPLEDELAY = 0x001b # macro -ixSE_SA0WGP01TD0_SAMPLEDELAY = 0x001c # macro -ixSE_SA0WGP01TD1_SAMPLEDELAY = 0x001d # macro -ixSE_SA0WGP01TCP0_SAMPLEDELAY = 0x001e # macro -ixSE_SA0WGP01TCP1_SAMPLEDELAY = 0x001f # macro -ixSE_SA0WGP02TA0_SAMPLEDELAY = 0x0020 # macro -ixSE_SA0WGP02TA1_SAMPLEDELAY = 0x0021 # macro -ixSE_SA0WGP02TD0_SAMPLEDELAY = 0x0022 # macro -ixSE_SA0WGP02TD1_SAMPLEDELAY = 0x0023 # macro -ixSE_SA0WGP02TCP0_SAMPLEDELAY = 0x0024 # macro -ixSE_SA0WGP02TCP1_SAMPLEDELAY = 0x0025 # macro -ixSE_SA0WGP03TA0_SAMPLEDELAY = 0x0026 # macro -ixSE_SA0WGP03TA1_SAMPLEDELAY = 0x0027 # macro -ixSE_SA0WGP03TD0_SAMPLEDELAY = 0x0028 # macro -ixSE_SA0WGP03TD1_SAMPLEDELAY = 0x0029 # macro -ixSE_SA0WGP03TCP0_SAMPLEDELAY = 0x002a # macro -ixSE_SA0WGP03TCP1_SAMPLEDELAY = 0x002b # macro -ixSE_SA0WGP04TA0_SAMPLEDELAY = 0x002c # macro -ixSE_SA0WGP04TA1_SAMPLEDELAY = 0x002d # macro -ixSE_SA0WGP04TD0_SAMPLEDELAY = 0x002e # macro -ixSE_SA0WGP04TD1_SAMPLEDELAY = 0x002f # macro -ixSE_SA0WGP04TCP0_SAMPLEDELAY = 0x0030 # macro -ixSE_SA0WGP04TCP1_SAMPLEDELAY = 0x0031 # macro -ixSE_SA1SX_SAMPLEDELAY = 0x0032 # macro -ixSE_SA1GL1A_SAMPLEDELAY = 0x0033 # macro -ixSE_SA1GL1CG_SAMPLEDELAY = 0x0034 # macro -ixSE_SA1CB0_SAMPLEDELAY = 0x0035 # macro -ixSE_SA1CB1_SAMPLEDELAY = 0x0036 # macro -ixSE_SA1DB0_SAMPLEDELAY = 0x0037 # macro -ixSE_SA1DB1_SAMPLEDELAY = 0x0038 # macro -ixSE_SA1SC0_SAMPLEDELAY = 0x0039 # macro -ixSE_SA1SC1_SAMPLEDELAY = 0x003a # macro -ixSE_SA1RMI0_SAMPLEDELAY = 0x003b # macro -ixSE_SA1RMI1_SAMPLEDELAY = 0x003c # macro -ixSE_SA1GL1C0_SAMPLEDELAY = 0x003d # macro -ixSE_SA1GL1C1_SAMPLEDELAY = 0x003e # macro -ixSE_SA1GL1C2_SAMPLEDELAY = 0x003f # macro -ixSE_SA1GL1C3_SAMPLEDELAY = 0x0040 # macro -ixSE_SA1WGP00TA0_SAMPLEDELAY = 0x0041 # macro -ixSE_SA1WGP00TA1_SAMPLEDELAY = 0x0042 # macro -ixSE_SA1WGP00TD0_SAMPLEDELAY = 0x0043 # macro -ixSE_SA1WGP00TD1_SAMPLEDELAY = 0x0044 # macro -ixSE_SA1WGP00TCP0_SAMPLEDELAY = 0x0045 # macro -ixSE_SA1WGP00TCP1_SAMPLEDELAY = 0x0046 # macro -ixSE_SA1WGP01TA0_SAMPLEDELAY = 0x0047 # macro -ixSE_SA1WGP01TA1_SAMPLEDELAY = 0x0048 # macro -ixSE_SA1WGP01TD0_SAMPLEDELAY = 0x0049 # macro -ixSE_SA1WGP01TD1_SAMPLEDELAY = 0x004a # macro -ixSE_SA1WGP01TCP0_SAMPLEDELAY = 0x004b # macro -ixSE_SA1WGP01TCP1_SAMPLEDELAY = 0x004c # macro -ixSE_SA1WGP02TA0_SAMPLEDELAY = 0x004d # macro -ixSE_SA1WGP02TA1_SAMPLEDELAY = 0x004e # macro -ixSE_SA1WGP02TD0_SAMPLEDELAY = 0x004f # macro -ixSE_SA1WGP02TD1_SAMPLEDELAY = 0x0050 # macro -ixSE_SA1WGP02TCP0_SAMPLEDELAY = 0x0051 # macro -ixSE_SA1WGP02TCP1_SAMPLEDELAY = 0x0052 # macro -ixSE_SA1WGP03TA0_SAMPLEDELAY = 0x0053 # macro -ixSE_SA1WGP03TA1_SAMPLEDELAY = 0x0054 # macro -ixSE_SA1WGP03TD0_SAMPLEDELAY = 0x0055 # macro -ixSE_SA1WGP03TD1_SAMPLEDELAY = 0x0056 # macro -ixSE_SA1WGP03TCP0_SAMPLEDELAY = 0x0057 # macro -ixSE_SA1WGP03TCP1_SAMPLEDELAY = 0x0058 # macro -ixSE_SA1WGP04TA0_SAMPLEDELAY = 0x0059 # macro -ixSE_SA1WGP04TA1_SAMPLEDELAY = 0x005a # macro -ixSE_SA1WGP04TD0_SAMPLEDELAY = 0x005b # macro -ixSE_SA1WGP04TD1_SAMPLEDELAY = 0x005c # macro -ixSE_SA1WGP04TCP0_SAMPLEDELAY = 0x005d # macro -ixSE_SA1WGP04TCP1_SAMPLEDELAY = 0x005e # macro -ixSA_WGP_BLK_ID = 0x0000 # macro -ixSQ_WAVE_HW_ID_LEGACY = 0x0104 # macro -ixSQ_WAVE_INST_DW0 = 0x010a # macro -ixSQ_WAVE_VGPR_OFFSET = 0x011b # macro -ixSQ_WAVE_TTMP2 = 0x026e # macro -ixSQ_INTERRUPT_WORD_AUTO = 0x20c0 # macro -ixSQ_INTERRUPT_WORD_ERROR = 0x20c0 # macro -ixSQ_INTERRUPT_WORD_WAVE = 0x20c0 # macro -ixDIDT_SQ_CTRL0 = 0x0000 # macro -ixDIDT_SQ_CTRL1 = 0x0001 # macro -ixDIDT_SQ_CTRL2 = 0x0002 # macro -ixDIDT_SQ_CTRL_OCP = 0x0003 # macro -ixDIDT_SQ_STALL_CTRL = 0x0004 # macro -ixDIDT_SQ_TUNING_CTRL = 0x0005 # macro -ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL = 0x0006 # macro -ixDIDT_SQ_CTRL3 = 0x0007 # macro -ixDIDT_SQ_STALL_PATTERN_1_2 = 0x0008 # macro -ixDIDT_SQ_STALL_PATTERN_3_4 = 0x0009 # macro -ixDIDT_SQ_STALL_PATTERN_5_6 = 0x000a # macro -ixDIDT_SQ_STALL_PATTERN_7 = 0x000b # macro -ixDIDT_SQ_MPD_SCALE_FACTOR = 0x000c # macro -ixDIDT_SQ_STALL_RELEASE_CNTL0 = 0x000d # macro -ixDIDT_SQ_STALL_RELEASE_CNTL1 = 0x000e # macro -ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS = 0x000f # macro -ixDIDT_SQ_WEIGHT0_3 = 0x0010 # macro -ixDIDT_SQ_WEIGHT4_7 = 0x0011 # macro -ixDIDT_SQ_WEIGHT8_11 = 0x0012 # macro -ixDIDT_SQ_EDC_CTRL = 0x0013 # macro -ixDIDT_SQ_EDC_THRESHOLD = 0x0014 # macro -ixDIDT_SQ_EDC_STALL_PATTERN_1_2 = 0x0015 # macro -ixDIDT_SQ_EDC_STALL_PATTERN_3_4 = 0x0016 # macro -ixDIDT_SQ_EDC_STALL_PATTERN_5_6 = 0x0017 # macro -ixDIDT_SQ_EDC_STALL_PATTERN_7 = 0x0018 # macro -ixDIDT_SQ_EDC_TIMER_PERIOD = 0x0019 # macro -ixDIDT_SQ_THROTTLE_CTRL = 0x001a # macro -ixDIDT_SQ_EDC_STALL_DELAY_1 = 0x001b # macro -ixDIDT_SQ_EDC_STALL_DELAY_2 = 0x001c # macro -ixDIDT_SQ_EDC_STALL_DELAY_3 = 0x001d # macro -ixDIDT_SQ_EDC_STATUS = 0x001f # macro -ixDIDT_SQ_EDC_OVERFLOW = 0x0020 # macro -ixDIDT_SQ_EDC_ROLLING_POWER_DELTA = 0x0021 # macro -ixDIDT_SQ_EDC_PCC_PERF_COUNTER = 0x0022 # macro -ixDIDT_DB_CTRL0 = 0x0030 # macro -ixDIDT_DB_CTRL1 = 0x0031 # macro -ixDIDT_DB_CTRL2 = 0x0032 # macro -ixDIDT_DB_CTRL_OCP = 0x0033 # macro -ixDIDT_DB_STALL_CTRL = 0x0034 # macro -ixDIDT_DB_TUNING_CTRL = 0x0035 # macro -ixDIDT_DB_STALL_AUTO_RELEASE_CTRL = 0x0036 # macro -ixDIDT_DB_CTRL3 = 0x0037 # macro -ixDIDT_DB_STALL_PATTERN_1_2 = 0x0038 # macro -ixDIDT_DB_STALL_PATTERN_3_4 = 0x0039 # macro -ixDIDT_DB_STALL_PATTERN_5_6 = 0x003a # macro -ixDIDT_DB_STALL_PATTERN_7 = 0x003b # macro -ixDIDT_DB_MPD_SCALE_FACTOR = 0x003c # macro -ixDIDT_DB_STALL_RELEASE_CNTL0 = 0x003d # macro -ixDIDT_DB_STALL_RELEASE_CNTL1 = 0x003e # macro -ixDIDT_DB_STALL_RELEASE_CNTL_STATUS = 0x003f # macro -ixDIDT_DB_WEIGHT0_3 = 0x0040 # macro -ixDIDT_DB_WEIGHT4_7 = 0x0041 # macro -ixDIDT_DB_WEIGHT8_11 = 0x0042 # macro -ixDIDT_DB_EDC_CTRL = 0x0043 # macro -ixDIDT_DB_EDC_THRESHOLD = 0x0044 # macro -ixDIDT_DB_EDC_STALL_PATTERN_1_2 = 0x0045 # macro -ixDIDT_DB_EDC_STALL_PATTERN_3_4 = 0x0046 # macro -ixDIDT_DB_EDC_STALL_PATTERN_5_6 = 0x0047 # macro -ixDIDT_DB_EDC_STALL_PATTERN_7 = 0x0048 # macro -ixDIDT_DB_EDC_TIMER_PERIOD = 0x0049 # macro -ixDIDT_DB_THROTTLE_CTRL = 0x004a # macro -ixDIDT_DB_EDC_STALL_DELAY_1 = 0x004b # macro -ixDIDT_DB_EDC_STATUS = 0x004f # macro -ixDIDT_DB_EDC_OVERFLOW = 0x0050 # macro -ixDIDT_DB_EDC_ROLLING_POWER_DELTA = 0x0051 # macro -ixDIDT_DB_EDC_PCC_PERF_COUNTER = 0x0052 # macro -ixDIDT_TD_CTRL0 = 0x0060 # macro -ixDIDT_TD_CTRL1 = 0x0061 # macro -ixDIDT_TD_CTRL2 = 0x0062 # macro -ixDIDT_TD_CTRL_OCP = 0x0063 # macro -ixDIDT_TD_STALL_CTRL = 0x0064 # macro -ixDIDT_TD_TUNING_CTRL = 0x0065 # macro -ixDIDT_TD_STALL_AUTO_RELEASE_CTRL = 0x0066 # macro -ixDIDT_TD_CTRL3 = 0x0067 # macro -ixDIDT_TD_STALL_PATTERN_1_2 = 0x0068 # macro -ixDIDT_TD_STALL_PATTERN_3_4 = 0x0069 # macro -ixDIDT_TD_STALL_PATTERN_5_6 = 0x006a # macro -ixDIDT_TD_STALL_PATTERN_7 = 0x006b # macro -ixDIDT_TD_MPD_SCALE_FACTOR = 0x006c # macro -ixDIDT_TD_STALL_RELEASE_CNTL0 = 0x006d # macro -ixDIDT_TD_STALL_RELEASE_CNTL1 = 0x006e # macro -ixDIDT_TD_STALL_RELEASE_CNTL_STATUS = 0x006f # macro -ixDIDT_TD_WEIGHT0_3 = 0x0070 # macro -ixDIDT_TD_WEIGHT4_7 = 0x0071 # macro -ixDIDT_TD_WEIGHT8_11 = 0x0072 # macro -ixDIDT_TD_EDC_CTRL = 0x0073 # macro -ixDIDT_TD_EDC_THRESHOLD = 0x0074 # macro -ixDIDT_TD_EDC_STALL_PATTERN_1_2 = 0x0075 # macro -ixDIDT_TD_EDC_STALL_PATTERN_3_4 = 0x0076 # macro -ixDIDT_TD_EDC_STALL_PATTERN_5_6 = 0x0077 # macro -ixDIDT_TD_EDC_STALL_PATTERN_7 = 0x0078 # macro -ixDIDT_TD_EDC_TIMER_PERIOD = 0x0079 # macro -ixDIDT_TD_THROTTLE_CTRL = 0x007a # macro -ixDIDT_TD_EDC_STALL_DELAY_1 = 0x007b # macro -ixDIDT_TD_EDC_STALL_DELAY_2 = 0x007c # macro -ixDIDT_TD_EDC_STALL_DELAY_3 = 0x007d # macro -ixDIDT_TD_EDC_STATUS = 0x007f # macro -ixDIDT_TD_EDC_OVERFLOW = 0x0080 # macro -ixDIDT_TD_EDC_ROLLING_POWER_DELTA = 0x0081 # macro -ixDIDT_TD_EDC_PCC_PERF_COUNTER = 0x0082 # macro -ixDIDT_TCP_CTRL0 = 0x0090 # macro -ixDIDT_TCP_CTRL1 = 0x0091 # macro -ixDIDT_TCP_CTRL2 = 0x0092 # macro -ixDIDT_TCP_CTRL_OCP = 0x0093 # macro -ixDIDT_TCP_STALL_CTRL = 0x0094 # macro -ixDIDT_TCP_TUNING_CTRL = 0x0095 # macro -ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL = 0x0096 # macro -ixDIDT_TCP_CTRL3 = 0x0097 # macro -ixDIDT_TCP_STALL_PATTERN_1_2 = 0x0098 # macro -ixDIDT_TCP_STALL_PATTERN_3_4 = 0x0099 # macro -ixDIDT_TCP_STALL_PATTERN_5_6 = 0x009a # macro -ixDIDT_TCP_STALL_PATTERN_7 = 0x009b # macro -ixDIDT_TCP_MPD_SCALE_FACTOR = 0x009c # macro -ixDIDT_TCP_STALL_RELEASE_CNTL0 = 0x009d # macro -ixDIDT_TCP_STALL_RELEASE_CNTL1 = 0x009e # macro -ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS = 0x009f # macro -ixDIDT_TCP_WEIGHT0_3 = 0x00a0 # macro -ixDIDT_TCP_WEIGHT4_7 = 0x00a1 # macro -ixDIDT_TCP_WEIGHT8_11 = 0x00a2 # macro -ixDIDT_TCP_EDC_CTRL = 0x00a3 # macro -ixDIDT_TCP_EDC_THRESHOLD = 0x00a4 # macro -ixDIDT_TCP_EDC_STALL_PATTERN_1_2 = 0x00a5 # macro -ixDIDT_TCP_EDC_STALL_PATTERN_3_4 = 0x00a6 # macro -ixDIDT_TCP_EDC_STALL_PATTERN_5_6 = 0x00a7 # macro -ixDIDT_TCP_EDC_STALL_PATTERN_7 = 0x00a8 # macro -ixDIDT_TCP_EDC_TIMER_PERIOD = 0x00a9 # macro -ixDIDT_TCP_THROTTLE_CTRL = 0x00aa # macro -ixDIDT_TCP_EDC_STALL_DELAY_1 = 0x00ab # macro -ixDIDT_TCP_EDC_STALL_DELAY_2 = 0x00ac # macro -ixDIDT_TCP_EDC_STALL_DELAY_3 = 0x00ad # macro -ixDIDT_TCP_EDC_STATUS = 0x00af # macro -ixDIDT_TCP_EDC_OVERFLOW = 0x00b0 # macro -ixDIDT_TCP_EDC_ROLLING_POWER_DELTA = 0x00b1 # macro -ixDIDT_TCP_EDC_PCC_PERF_COUNTER = 0x00b2 # macro -ixDIDT_SQ_STALL_EVENT_COUNTER = 0x00c0 # macro -ixDIDT_DB_STALL_EVENT_COUNTER = 0x00c1 # macro -ixDIDT_TD_STALL_EVENT_COUNTER = 0x00c2 # macro -ixDIDT_TCP_STALL_EVENT_COUNTER = 0x00c3 # macro -_sienna_cichlid_ip_offset_HEADER = True # macro -MAX_INSTANCE = 7 # macro -MAX_SEGMENT = 5 # macro -ATHUB_BASE__INST0_SEG0 = 0x00000C00 # macro -ATHUB_BASE__INST0_SEG1 = 0x02408C00 # macro -ATHUB_BASE__INST0_SEG2 = 0 # macro -ATHUB_BASE__INST0_SEG3 = 0 # macro -ATHUB_BASE__INST0_SEG4 = 0 # macro -ATHUB_BASE__INST1_SEG0 = 0 # macro -ATHUB_BASE__INST1_SEG1 = 0 # macro -ATHUB_BASE__INST1_SEG2 = 0 # macro -ATHUB_BASE__INST1_SEG3 = 0 # macro -ATHUB_BASE__INST1_SEG4 = 0 # macro -ATHUB_BASE__INST2_SEG0 = 0 # macro -ATHUB_BASE__INST2_SEG1 = 0 # macro -ATHUB_BASE__INST2_SEG2 = 0 # macro -ATHUB_BASE__INST2_SEG3 = 0 # macro -ATHUB_BASE__INST2_SEG4 = 0 # macro -ATHUB_BASE__INST3_SEG0 = 0 # macro -ATHUB_BASE__INST3_SEG1 = 0 # macro -ATHUB_BASE__INST3_SEG2 = 0 # macro -ATHUB_BASE__INST3_SEG3 = 0 # macro -ATHUB_BASE__INST3_SEG4 = 0 # macro -ATHUB_BASE__INST4_SEG0 = 0 # macro -ATHUB_BASE__INST4_SEG1 = 0 # macro -ATHUB_BASE__INST4_SEG2 = 0 # macro -ATHUB_BASE__INST4_SEG3 = 0 # macro -ATHUB_BASE__INST4_SEG4 = 0 # macro -ATHUB_BASE__INST5_SEG0 = 0 # macro -ATHUB_BASE__INST5_SEG1 = 0 # macro -ATHUB_BASE__INST5_SEG2 = 0 # macro -ATHUB_BASE__INST5_SEG3 = 0 # macro -ATHUB_BASE__INST5_SEG4 = 0 # macro -ATHUB_BASE__INST6_SEG0 = 0 # macro -ATHUB_BASE__INST6_SEG1 = 0 # macro -ATHUB_BASE__INST6_SEG2 = 0 # macro -ATHUB_BASE__INST6_SEG3 = 0 # macro -ATHUB_BASE__INST6_SEG4 = 0 # macro -CLK_BASE__INST0_SEG0 = 0x00016C00 # macro -CLK_BASE__INST0_SEG1 = 0x02401800 # macro -CLK_BASE__INST0_SEG2 = 0 # macro -CLK_BASE__INST0_SEG3 = 0 # macro -CLK_BASE__INST0_SEG4 = 0 # macro -CLK_BASE__INST1_SEG0 = 0x00016E00 # macro -CLK_BASE__INST1_SEG1 = 0x02401C00 # macro -CLK_BASE__INST1_SEG2 = 0 # macro -CLK_BASE__INST1_SEG3 = 0 # macro -CLK_BASE__INST1_SEG4 = 0 # macro -CLK_BASE__INST2_SEG0 = 0x00017000 # macro -CLK_BASE__INST2_SEG1 = 0x02402000 # macro -CLK_BASE__INST2_SEG2 = 0 # macro -CLK_BASE__INST2_SEG3 = 0 # macro -CLK_BASE__INST2_SEG4 = 0 # macro -CLK_BASE__INST3_SEG0 = 0x00017200 # macro -CLK_BASE__INST3_SEG1 = 0x02402400 # macro -CLK_BASE__INST3_SEG2 = 0 # macro -CLK_BASE__INST3_SEG3 = 0 # macro -CLK_BASE__INST3_SEG4 = 0 # macro -CLK_BASE__INST4_SEG0 = 0x0001B000 # macro -CLK_BASE__INST4_SEG1 = 0x0242D800 # macro -CLK_BASE__INST4_SEG2 = 0 # macro -CLK_BASE__INST4_SEG3 = 0 # macro -CLK_BASE__INST4_SEG4 = 0 # macro -CLK_BASE__INST5_SEG0 = 0x0001B200 # macro -CLK_BASE__INST5_SEG1 = 0x0242DC00 # macro -CLK_BASE__INST5_SEG2 = 0 # macro -CLK_BASE__INST5_SEG3 = 0 # macro -CLK_BASE__INST5_SEG4 = 0 # macro -CLK_BASE__INST6_SEG0 = 0x0001B400 # macro -CLK_BASE__INST6_SEG1 = 0x0242E000 # macro -CLK_BASE__INST6_SEG2 = 0 # macro -CLK_BASE__INST6_SEG3 = 0 # macro -CLK_BASE__INST6_SEG4 = 0 # macro -DF_BASE__INST0_SEG0 = 0x00007000 # macro -DF_BASE__INST0_SEG1 = 0x0240B800 # macro -DF_BASE__INST0_SEG2 = 0 # macro -DF_BASE__INST0_SEG3 = 0 # macro -DF_BASE__INST0_SEG4 = 0 # macro -DF_BASE__INST1_SEG0 = 0 # macro -DF_BASE__INST1_SEG1 = 0 # macro -DF_BASE__INST1_SEG2 = 0 # macro -DF_BASE__INST1_SEG3 = 0 # macro -DF_BASE__INST1_SEG4 = 0 # macro -DF_BASE__INST2_SEG0 = 0 # macro -DF_BASE__INST2_SEG1 = 0 # macro -DF_BASE__INST2_SEG2 = 0 # macro -DF_BASE__INST2_SEG3 = 0 # macro -DF_BASE__INST2_SEG4 = 0 # macro -DF_BASE__INST3_SEG0 = 0 # macro -DF_BASE__INST3_SEG1 = 0 # macro -DF_BASE__INST3_SEG2 = 0 # macro -DF_BASE__INST3_SEG3 = 0 # macro -DF_BASE__INST3_SEG4 = 0 # macro -DF_BASE__INST4_SEG0 = 0 # macro -DF_BASE__INST4_SEG1 = 0 # macro -DF_BASE__INST4_SEG2 = 0 # macro -DF_BASE__INST4_SEG3 = 0 # macro -DF_BASE__INST4_SEG4 = 0 # macro -DF_BASE__INST5_SEG0 = 0 # macro -DF_BASE__INST5_SEG1 = 0 # macro -DF_BASE__INST5_SEG2 = 0 # macro -DF_BASE__INST5_SEG3 = 0 # macro -DF_BASE__INST5_SEG4 = 0 # macro -DF_BASE__INST6_SEG0 = 0 # macro -DF_BASE__INST6_SEG1 = 0 # macro -DF_BASE__INST6_SEG2 = 0 # macro -DF_BASE__INST6_SEG3 = 0 # macro -DF_BASE__INST6_SEG4 = 0 # macro -DIO_BASE__INST0_SEG0 = 0x02404000 # macro -DIO_BASE__INST0_SEG1 = 0 # macro -DIO_BASE__INST0_SEG2 = 0 # macro -DIO_BASE__INST0_SEG3 = 0 # macro -DIO_BASE__INST0_SEG4 = 0 # macro -DIO_BASE__INST1_SEG0 = 0 # macro -DIO_BASE__INST1_SEG1 = 0 # macro -DIO_BASE__INST1_SEG2 = 0 # macro -DIO_BASE__INST1_SEG3 = 0 # macro -DIO_BASE__INST1_SEG4 = 0 # macro -DIO_BASE__INST2_SEG0 = 0 # macro -DIO_BASE__INST2_SEG1 = 0 # macro -DIO_BASE__INST2_SEG2 = 0 # macro -DIO_BASE__INST2_SEG3 = 0 # macro -DIO_BASE__INST2_SEG4 = 0 # macro -DIO_BASE__INST3_SEG0 = 0 # macro -DIO_BASE__INST3_SEG1 = 0 # macro -DIO_BASE__INST3_SEG2 = 0 # macro -DIO_BASE__INST3_SEG3 = 0 # macro -DIO_BASE__INST3_SEG4 = 0 # macro -DIO_BASE__INST4_SEG0 = 0 # macro -DIO_BASE__INST4_SEG1 = 0 # macro -DIO_BASE__INST4_SEG2 = 0 # macro -DIO_BASE__INST4_SEG3 = 0 # macro -DIO_BASE__INST4_SEG4 = 0 # macro -DIO_BASE__INST5_SEG0 = 0 # macro -DIO_BASE__INST5_SEG1 = 0 # macro -DIO_BASE__INST5_SEG2 = 0 # macro -DIO_BASE__INST5_SEG3 = 0 # macro -DIO_BASE__INST5_SEG4 = 0 # macro -DIO_BASE__INST6_SEG0 = 0 # macro -DIO_BASE__INST6_SEG1 = 0 # macro -DIO_BASE__INST6_SEG2 = 0 # macro -DIO_BASE__INST6_SEG3 = 0 # macro -DIO_BASE__INST6_SEG4 = 0 # macro -DCN_BASE__INST0_SEG0 = 0x00000012 # macro -DCN_BASE__INST0_SEG1 = 0x000000C0 # macro -DCN_BASE__INST0_SEG2 = 0x000034C0 # macro -DCN_BASE__INST0_SEG3 = 0x00009000 # macro -DCN_BASE__INST0_SEG4 = 0x02403C00 # macro -DCN_BASE__INST1_SEG0 = 0 # macro -DCN_BASE__INST1_SEG1 = 0 # macro -DCN_BASE__INST1_SEG2 = 0 # macro -DCN_BASE__INST1_SEG3 = 0 # macro -DCN_BASE__INST1_SEG4 = 0 # macro -DCN_BASE__INST2_SEG0 = 0 # macro -DCN_BASE__INST2_SEG1 = 0 # macro -DCN_BASE__INST2_SEG2 = 0 # macro -DCN_BASE__INST2_SEG3 = 0 # macro -DCN_BASE__INST2_SEG4 = 0 # macro -DCN_BASE__INST3_SEG0 = 0 # macro -DCN_BASE__INST3_SEG1 = 0 # macro -DCN_BASE__INST3_SEG2 = 0 # macro -DCN_BASE__INST3_SEG3 = 0 # macro -DCN_BASE__INST3_SEG4 = 0 # macro -DCN_BASE__INST4_SEG0 = 0 # macro -DCN_BASE__INST4_SEG1 = 0 # macro -DCN_BASE__INST4_SEG2 = 0 # macro -DCN_BASE__INST4_SEG3 = 0 # macro -DCN_BASE__INST4_SEG4 = 0 # macro -DCN_BASE__INST5_SEG0 = 0 # macro -DCN_BASE__INST5_SEG1 = 0 # macro -DCN_BASE__INST5_SEG2 = 0 # macro -DCN_BASE__INST5_SEG3 = 0 # macro -DCN_BASE__INST5_SEG4 = 0 # macro -DCN_BASE__INST6_SEG0 = 0 # macro -DCN_BASE__INST6_SEG1 = 0 # macro -DCN_BASE__INST6_SEG2 = 0 # macro -DCN_BASE__INST6_SEG3 = 0 # macro -DCN_BASE__INST6_SEG4 = 0 # macro -DPCS_BASE__INST0_SEG0 = 0x00000012 # macro -DPCS_BASE__INST0_SEG1 = 0x000000C0 # macro -DPCS_BASE__INST0_SEG2 = 0x000034C0 # macro -DPCS_BASE__INST0_SEG3 = 0x00009000 # macro -DPCS_BASE__INST0_SEG4 = 0x02403C00 # macro -DPCS_BASE__INST1_SEG0 = 0 # macro -DPCS_BASE__INST1_SEG1 = 0 # macro -DPCS_BASE__INST1_SEG2 = 0 # macro -DPCS_BASE__INST1_SEG3 = 0 # macro -DPCS_BASE__INST1_SEG4 = 0 # macro -DPCS_BASE__INST2_SEG0 = 0 # macro -DPCS_BASE__INST2_SEG1 = 0 # macro -DPCS_BASE__INST2_SEG2 = 0 # macro -DPCS_BASE__INST2_SEG3 = 0 # macro -DPCS_BASE__INST2_SEG4 = 0 # macro -DPCS_BASE__INST3_SEG0 = 0 # macro -DPCS_BASE__INST3_SEG1 = 0 # macro -DPCS_BASE__INST3_SEG2 = 0 # macro -DPCS_BASE__INST3_SEG3 = 0 # macro -DPCS_BASE__INST3_SEG4 = 0 # macro -DPCS_BASE__INST4_SEG0 = 0 # macro -DPCS_BASE__INST4_SEG1 = 0 # macro -DPCS_BASE__INST4_SEG2 = 0 # macro -DPCS_BASE__INST4_SEG3 = 0 # macro -DPCS_BASE__INST4_SEG4 = 0 # macro -DPCS_BASE__INST5_SEG0 = 0 # macro -DPCS_BASE__INST5_SEG1 = 0 # macro -DPCS_BASE__INST5_SEG2 = 0 # macro -DPCS_BASE__INST5_SEG3 = 0 # macro -DPCS_BASE__INST5_SEG4 = 0 # macro -DPCS_BASE__INST6_SEG0 = 0 # macro -DPCS_BASE__INST6_SEG1 = 0 # macro -DPCS_BASE__INST6_SEG2 = 0 # macro -DPCS_BASE__INST6_SEG3 = 0 # macro -DPCS_BASE__INST6_SEG4 = 0 # macro -FUSE_BASE__INST0_SEG0 = 0x00017400 # macro -FUSE_BASE__INST0_SEG1 = 0x02401400 # macro -FUSE_BASE__INST0_SEG2 = 0 # macro -FUSE_BASE__INST0_SEG3 = 0 # macro -FUSE_BASE__INST0_SEG4 = 0 # macro -FUSE_BASE__INST1_SEG0 = 0 # macro -FUSE_BASE__INST1_SEG1 = 0 # macro -FUSE_BASE__INST1_SEG2 = 0 # macro -FUSE_BASE__INST1_SEG3 = 0 # macro -FUSE_BASE__INST1_SEG4 = 0 # macro -FUSE_BASE__INST2_SEG0 = 0 # macro -FUSE_BASE__INST2_SEG1 = 0 # macro -FUSE_BASE__INST2_SEG2 = 0 # macro -FUSE_BASE__INST2_SEG3 = 0 # macro -FUSE_BASE__INST2_SEG4 = 0 # macro -FUSE_BASE__INST3_SEG0 = 0 # macro -FUSE_BASE__INST3_SEG1 = 0 # macro -FUSE_BASE__INST3_SEG2 = 0 # macro -FUSE_BASE__INST3_SEG3 = 0 # macro -FUSE_BASE__INST3_SEG4 = 0 # macro -FUSE_BASE__INST4_SEG0 = 0 # macro -FUSE_BASE__INST4_SEG1 = 0 # macro -FUSE_BASE__INST4_SEG2 = 0 # macro -FUSE_BASE__INST4_SEG3 = 0 # macro -FUSE_BASE__INST4_SEG4 = 0 # macro -FUSE_BASE__INST5_SEG0 = 0 # macro -FUSE_BASE__INST5_SEG1 = 0 # macro -FUSE_BASE__INST5_SEG2 = 0 # macro -FUSE_BASE__INST5_SEG3 = 0 # macro -FUSE_BASE__INST5_SEG4 = 0 # macro -FUSE_BASE__INST6_SEG0 = 0 # macro -FUSE_BASE__INST6_SEG1 = 0 # macro -FUSE_BASE__INST6_SEG2 = 0 # macro -FUSE_BASE__INST6_SEG3 = 0 # macro -FUSE_BASE__INST6_SEG4 = 0 # macro -GC_BASE__INST0_SEG0 = 0x00001260 # macro -GC_BASE__INST0_SEG1 = 0x0000A000 # macro -GC_BASE__INST0_SEG2 = 0x0001C000 # macro -GC_BASE__INST0_SEG3 = 0x02402C00 # macro -GC_BASE__INST0_SEG4 = 0 # macro -GC_BASE__INST1_SEG0 = 0 # macro -GC_BASE__INST1_SEG1 = 0 # macro -GC_BASE__INST1_SEG2 = 0 # macro -GC_BASE__INST1_SEG3 = 0 # macro -GC_BASE__INST1_SEG4 = 0 # macro -GC_BASE__INST2_SEG0 = 0 # macro -GC_BASE__INST2_SEG1 = 0 # macro -GC_BASE__INST2_SEG2 = 0 # macro -GC_BASE__INST2_SEG3 = 0 # macro -GC_BASE__INST2_SEG4 = 0 # macro -GC_BASE__INST3_SEG0 = 0 # macro -GC_BASE__INST3_SEG1 = 0 # macro -GC_BASE__INST3_SEG2 = 0 # macro -GC_BASE__INST3_SEG3 = 0 # macro -GC_BASE__INST3_SEG4 = 0 # macro -GC_BASE__INST4_SEG0 = 0 # macro -GC_BASE__INST4_SEG1 = 0 # macro -GC_BASE__INST4_SEG2 = 0 # macro -GC_BASE__INST4_SEG3 = 0 # macro -GC_BASE__INST4_SEG4 = 0 # macro -GC_BASE__INST5_SEG0 = 0 # macro -GC_BASE__INST5_SEG1 = 0 # macro -GC_BASE__INST5_SEG2 = 0 # macro -GC_BASE__INST5_SEG3 = 0 # macro -GC_BASE__INST5_SEG4 = 0 # macro -GC_BASE__INST6_SEG0 = 0 # macro -GC_BASE__INST6_SEG1 = 0 # macro -GC_BASE__INST6_SEG2 = 0 # macro -GC_BASE__INST6_SEG3 = 0 # macro -GC_BASE__INST6_SEG4 = 0 # macro -HDA_BASE__INST0_SEG0 = 0x004C0000 # macro -HDA_BASE__INST0_SEG1 = 0x02404800 # macro -HDA_BASE__INST0_SEG2 = 0 # macro -HDA_BASE__INST0_SEG3 = 0 # macro -HDA_BASE__INST0_SEG4 = 0 # macro -HDA_BASE__INST1_SEG0 = 0 # macro -HDA_BASE__INST1_SEG1 = 0 # macro -HDA_BASE__INST1_SEG2 = 0 # macro -HDA_BASE__INST1_SEG3 = 0 # macro -HDA_BASE__INST1_SEG4 = 0 # macro -HDA_BASE__INST2_SEG0 = 0 # macro -HDA_BASE__INST2_SEG1 = 0 # macro -HDA_BASE__INST2_SEG2 = 0 # macro -HDA_BASE__INST2_SEG3 = 0 # macro -HDA_BASE__INST2_SEG4 = 0 # macro -HDA_BASE__INST3_SEG0 = 0 # macro -HDA_BASE__INST3_SEG1 = 0 # macro -HDA_BASE__INST3_SEG2 = 0 # macro -HDA_BASE__INST3_SEG3 = 0 # macro -HDA_BASE__INST3_SEG4 = 0 # macro -HDA_BASE__INST4_SEG0 = 0 # macro -HDA_BASE__INST4_SEG1 = 0 # macro -HDA_BASE__INST4_SEG2 = 0 # macro -HDA_BASE__INST4_SEG3 = 0 # macro -HDA_BASE__INST4_SEG4 = 0 # macro -HDA_BASE__INST5_SEG0 = 0 # macro -HDA_BASE__INST5_SEG1 = 0 # macro -HDA_BASE__INST5_SEG2 = 0 # macro -HDA_BASE__INST5_SEG3 = 0 # macro -HDA_BASE__INST5_SEG4 = 0 # macro -HDA_BASE__INST6_SEG0 = 0 # macro -HDA_BASE__INST6_SEG1 = 0 # macro -HDA_BASE__INST6_SEG2 = 0 # macro -HDA_BASE__INST6_SEG3 = 0 # macro -HDA_BASE__INST6_SEG4 = 0 # macro -HDP_BASE__INST0_SEG0 = 0x00000F20 # macro -HDP_BASE__INST0_SEG1 = 0x0240A400 # macro -HDP_BASE__INST0_SEG2 = 0 # macro -HDP_BASE__INST0_SEG3 = 0 # macro -HDP_BASE__INST0_SEG4 = 0 # macro -HDP_BASE__INST1_SEG0 = 0 # macro -HDP_BASE__INST1_SEG1 = 0 # macro -HDP_BASE__INST1_SEG2 = 0 # macro -HDP_BASE__INST1_SEG3 = 0 # macro -HDP_BASE__INST1_SEG4 = 0 # macro -HDP_BASE__INST2_SEG0 = 0 # macro -HDP_BASE__INST2_SEG1 = 0 # macro -HDP_BASE__INST2_SEG2 = 0 # macro -HDP_BASE__INST2_SEG3 = 0 # macro -HDP_BASE__INST2_SEG4 = 0 # macro -HDP_BASE__INST3_SEG0 = 0 # macro -HDP_BASE__INST3_SEG1 = 0 # macro -HDP_BASE__INST3_SEG2 = 0 # macro -HDP_BASE__INST3_SEG3 = 0 # macro -HDP_BASE__INST3_SEG4 = 0 # macro -HDP_BASE__INST4_SEG0 = 0 # macro -HDP_BASE__INST4_SEG1 = 0 # macro -HDP_BASE__INST4_SEG2 = 0 # macro -HDP_BASE__INST4_SEG3 = 0 # macro -HDP_BASE__INST4_SEG4 = 0 # macro -HDP_BASE__INST5_SEG0 = 0 # macro -HDP_BASE__INST5_SEG1 = 0 # macro -HDP_BASE__INST5_SEG2 = 0 # macro -HDP_BASE__INST5_SEG3 = 0 # macro -HDP_BASE__INST5_SEG4 = 0 # macro -HDP_BASE__INST6_SEG0 = 0 # macro -HDP_BASE__INST6_SEG1 = 0 # macro -HDP_BASE__INST6_SEG2 = 0 # macro -HDP_BASE__INST6_SEG3 = 0 # macro -HDP_BASE__INST6_SEG4 = 0 # macro -MMHUB_BASE__INST0_SEG0 = 0x0001A000 # macro -MMHUB_BASE__INST0_SEG1 = 0x02408800 # macro -MMHUB_BASE__INST0_SEG2 = 0 # macro -MMHUB_BASE__INST0_SEG3 = 0 # macro -MMHUB_BASE__INST0_SEG4 = 0 # macro -MMHUB_BASE__INST1_SEG0 = 0 # macro -MMHUB_BASE__INST1_SEG1 = 0 # macro -MMHUB_BASE__INST1_SEG2 = 0 # macro -MMHUB_BASE__INST1_SEG3 = 0 # macro -MMHUB_BASE__INST1_SEG4 = 0 # macro -MMHUB_BASE__INST2_SEG0 = 0 # macro -MMHUB_BASE__INST2_SEG1 = 0 # macro -MMHUB_BASE__INST2_SEG2 = 0 # macro -MMHUB_BASE__INST2_SEG3 = 0 # macro -MMHUB_BASE__INST2_SEG4 = 0 # macro -MMHUB_BASE__INST3_SEG0 = 0 # macro -MMHUB_BASE__INST3_SEG1 = 0 # macro -MMHUB_BASE__INST3_SEG2 = 0 # macro -MMHUB_BASE__INST3_SEG3 = 0 # macro -MMHUB_BASE__INST3_SEG4 = 0 # macro -MMHUB_BASE__INST4_SEG0 = 0 # macro -MMHUB_BASE__INST4_SEG1 = 0 # macro -MMHUB_BASE__INST4_SEG2 = 0 # macro -MMHUB_BASE__INST4_SEG3 = 0 # macro -MMHUB_BASE__INST4_SEG4 = 0 # macro -MMHUB_BASE__INST5_SEG0 = 0 # macro -MMHUB_BASE__INST5_SEG1 = 0 # macro -MMHUB_BASE__INST5_SEG2 = 0 # macro -MMHUB_BASE__INST5_SEG3 = 0 # macro -MMHUB_BASE__INST5_SEG4 = 0 # macro -MMHUB_BASE__INST6_SEG0 = 0 # macro -MMHUB_BASE__INST6_SEG1 = 0 # macro -MMHUB_BASE__INST6_SEG2 = 0 # macro -MMHUB_BASE__INST6_SEG3 = 0 # macro -MMHUB_BASE__INST6_SEG4 = 0 # macro -MP0_BASE__INST0_SEG0 = 0x00016000 # macro -MP0_BASE__INST0_SEG1 = 0x00DC0000 # macro -MP0_BASE__INST0_SEG2 = 0x00E00000 # macro -MP0_BASE__INST0_SEG3 = 0x00E40000 # macro -MP0_BASE__INST0_SEG4 = 0x0243FC00 # macro -MP0_BASE__INST1_SEG0 = 0 # macro -MP0_BASE__INST1_SEG1 = 0 # macro -MP0_BASE__INST1_SEG2 = 0 # macro -MP0_BASE__INST1_SEG3 = 0 # macro -MP0_BASE__INST1_SEG4 = 0 # macro -MP0_BASE__INST2_SEG0 = 0 # macro -MP0_BASE__INST2_SEG1 = 0 # macro -MP0_BASE__INST2_SEG2 = 0 # macro -MP0_BASE__INST2_SEG3 = 0 # macro -MP0_BASE__INST2_SEG4 = 0 # macro -MP0_BASE__INST3_SEG0 = 0 # macro -MP0_BASE__INST3_SEG1 = 0 # macro -MP0_BASE__INST3_SEG2 = 0 # macro -MP0_BASE__INST3_SEG3 = 0 # macro -MP0_BASE__INST3_SEG4 = 0 # macro -MP0_BASE__INST4_SEG0 = 0 # macro -MP0_BASE__INST4_SEG1 = 0 # macro -MP0_BASE__INST4_SEG2 = 0 # macro -MP0_BASE__INST4_SEG3 = 0 # macro -MP0_BASE__INST4_SEG4 = 0 # macro -MP0_BASE__INST5_SEG0 = 0 # macro -MP0_BASE__INST5_SEG1 = 0 # macro -MP0_BASE__INST5_SEG2 = 0 # macro -MP0_BASE__INST5_SEG3 = 0 # macro -MP0_BASE__INST5_SEG4 = 0 # macro -MP0_BASE__INST6_SEG0 = 0 # macro -MP0_BASE__INST6_SEG1 = 0 # macro -MP0_BASE__INST6_SEG2 = 0 # macro -MP0_BASE__INST6_SEG3 = 0 # macro -MP0_BASE__INST6_SEG4 = 0 # macro -MP1_BASE__INST0_SEG0 = 0x00016000 # macro -MP1_BASE__INST0_SEG1 = 0x00DC0000 # macro -MP1_BASE__INST0_SEG2 = 0x00E00000 # macro -MP1_BASE__INST0_SEG3 = 0x00E40000 # macro -MP1_BASE__INST0_SEG4 = 0x0243FC00 # macro -MP1_BASE__INST1_SEG0 = 0 # macro -MP1_BASE__INST1_SEG1 = 0 # macro -MP1_BASE__INST1_SEG2 = 0 # macro -MP1_BASE__INST1_SEG3 = 0 # macro -MP1_BASE__INST1_SEG4 = 0 # macro -MP1_BASE__INST2_SEG0 = 0 # macro -MP1_BASE__INST2_SEG1 = 0 # macro -MP1_BASE__INST2_SEG2 = 0 # macro -MP1_BASE__INST2_SEG3 = 0 # macro -MP1_BASE__INST2_SEG4 = 0 # macro -MP1_BASE__INST3_SEG0 = 0 # macro -MP1_BASE__INST3_SEG1 = 0 # macro -MP1_BASE__INST3_SEG2 = 0 # macro -MP1_BASE__INST3_SEG3 = 0 # macro -MP1_BASE__INST3_SEG4 = 0 # macro -MP1_BASE__INST4_SEG0 = 0 # macro -MP1_BASE__INST4_SEG1 = 0 # macro -MP1_BASE__INST4_SEG2 = 0 # macro -MP1_BASE__INST4_SEG3 = 0 # macro -MP1_BASE__INST4_SEG4 = 0 # macro -MP1_BASE__INST5_SEG0 = 0 # macro -MP1_BASE__INST5_SEG1 = 0 # macro -MP1_BASE__INST5_SEG2 = 0 # macro -MP1_BASE__INST5_SEG3 = 0 # macro -MP1_BASE__INST5_SEG4 = 0 # macro -MP1_BASE__INST6_SEG0 = 0 # macro -MP1_BASE__INST6_SEG1 = 0 # macro -MP1_BASE__INST6_SEG2 = 0 # macro -MP1_BASE__INST6_SEG3 = 0 # macro -MP1_BASE__INST6_SEG4 = 0 # macro -NBIO_BASE__INST0_SEG0 = 0x00000000 # macro -NBIO_BASE__INST0_SEG1 = 0x00000014 # macro -NBIO_BASE__INST0_SEG2 = 0x00000D20 # macro -NBIO_BASE__INST0_SEG3 = 0x00010400 # macro -NBIO_BASE__INST0_SEG4 = 0x0241B000 # macro -NBIO_BASE__INST1_SEG0 = 0 # macro -NBIO_BASE__INST1_SEG1 = 0 # macro -NBIO_BASE__INST1_SEG2 = 0 # macro -NBIO_BASE__INST1_SEG3 = 0 # macro -NBIO_BASE__INST1_SEG4 = 0 # macro -NBIO_BASE__INST2_SEG0 = 0 # macro -NBIO_BASE__INST2_SEG1 = 0 # macro -NBIO_BASE__INST2_SEG2 = 0 # macro -NBIO_BASE__INST2_SEG3 = 0 # macro -NBIO_BASE__INST2_SEG4 = 0 # macro -NBIO_BASE__INST3_SEG0 = 0 # macro -NBIO_BASE__INST3_SEG1 = 0 # macro -NBIO_BASE__INST3_SEG2 = 0 # macro -NBIO_BASE__INST3_SEG3 = 0 # macro -NBIO_BASE__INST3_SEG4 = 0 # macro -NBIO_BASE__INST4_SEG0 = 0 # macro -NBIO_BASE__INST4_SEG1 = 0 # macro -NBIO_BASE__INST4_SEG2 = 0 # macro -NBIO_BASE__INST4_SEG3 = 0 # macro -NBIO_BASE__INST4_SEG4 = 0 # macro -NBIO_BASE__INST5_SEG0 = 0 # macro -NBIO_BASE__INST5_SEG1 = 0 # macro -NBIO_BASE__INST5_SEG2 = 0 # macro -NBIO_BASE__INST5_SEG3 = 0 # macro -NBIO_BASE__INST5_SEG4 = 0 # macro -NBIO_BASE__INST6_SEG0 = 0 # macro -NBIO_BASE__INST6_SEG1 = 0 # macro -NBIO_BASE__INST6_SEG2 = 0 # macro -NBIO_BASE__INST6_SEG3 = 0 # macro -NBIO_BASE__INST6_SEG4 = 0 # macro -OSSSYS_BASE__INST0_SEG0 = 0x000010A0 # macro -OSSSYS_BASE__INST0_SEG1 = 0x0240A000 # macro -OSSSYS_BASE__INST0_SEG2 = 0 # macro -OSSSYS_BASE__INST0_SEG3 = 0 # macro -OSSSYS_BASE__INST0_SEG4 = 0 # macro -OSSSYS_BASE__INST1_SEG0 = 0 # macro -OSSSYS_BASE__INST1_SEG1 = 0 # macro -OSSSYS_BASE__INST1_SEG2 = 0 # macro -OSSSYS_BASE__INST1_SEG3 = 0 # macro -OSSSYS_BASE__INST1_SEG4 = 0 # macro -OSSSYS_BASE__INST2_SEG0 = 0 # macro -OSSSYS_BASE__INST2_SEG1 = 0 # macro -OSSSYS_BASE__INST2_SEG2 = 0 # macro -OSSSYS_BASE__INST2_SEG3 = 0 # macro -OSSSYS_BASE__INST2_SEG4 = 0 # macro -OSSSYS_BASE__INST3_SEG0 = 0 # macro -OSSSYS_BASE__INST3_SEG1 = 0 # macro -OSSSYS_BASE__INST3_SEG2 = 0 # macro -OSSSYS_BASE__INST3_SEG3 = 0 # macro -OSSSYS_BASE__INST3_SEG4 = 0 # macro -OSSSYS_BASE__INST4_SEG0 = 0 # macro -OSSSYS_BASE__INST4_SEG1 = 0 # macro -OSSSYS_BASE__INST4_SEG2 = 0 # macro -OSSSYS_BASE__INST4_SEG3 = 0 # macro -OSSSYS_BASE__INST4_SEG4 = 0 # macro -OSSSYS_BASE__INST5_SEG0 = 0 # macro -OSSSYS_BASE__INST5_SEG1 = 0 # macro -OSSSYS_BASE__INST5_SEG2 = 0 # macro -OSSSYS_BASE__INST5_SEG3 = 0 # macro -OSSSYS_BASE__INST5_SEG4 = 0 # macro -OSSSYS_BASE__INST6_SEG0 = 0 # macro -OSSSYS_BASE__INST6_SEG1 = 0 # macro -OSSSYS_BASE__INST6_SEG2 = 0 # macro -OSSSYS_BASE__INST6_SEG3 = 0 # macro -OSSSYS_BASE__INST6_SEG4 = 0 # macro -PCIE0_BASE__INST0_SEG0 = 0x00000000 # macro -PCIE0_BASE__INST0_SEG1 = 0x00000014 # macro -PCIE0_BASE__INST0_SEG2 = 0x00000D20 # macro -PCIE0_BASE__INST0_SEG3 = 0x00010400 # macro -PCIE0_BASE__INST0_SEG4 = 0x0241B000 # macro -PCIE0_BASE__INST1_SEG0 = 0 # macro -PCIE0_BASE__INST1_SEG1 = 0 # macro -PCIE0_BASE__INST1_SEG2 = 0 # macro -PCIE0_BASE__INST1_SEG3 = 0 # macro -PCIE0_BASE__INST1_SEG4 = 0 # macro -PCIE0_BASE__INST2_SEG0 = 0 # macro -PCIE0_BASE__INST2_SEG1 = 0 # macro -PCIE0_BASE__INST2_SEG2 = 0 # macro -PCIE0_BASE__INST2_SEG3 = 0 # macro -PCIE0_BASE__INST2_SEG4 = 0 # macro -PCIE0_BASE__INST3_SEG0 = 0 # macro -PCIE0_BASE__INST3_SEG1 = 0 # macro -PCIE0_BASE__INST3_SEG2 = 0 # macro -PCIE0_BASE__INST3_SEG3 = 0 # macro -PCIE0_BASE__INST3_SEG4 = 0 # macro -PCIE0_BASE__INST4_SEG0 = 0 # macro -PCIE0_BASE__INST4_SEG1 = 0 # macro -PCIE0_BASE__INST4_SEG2 = 0 # macro -PCIE0_BASE__INST4_SEG3 = 0 # macro -PCIE0_BASE__INST4_SEG4 = 0 # macro -PCIE0_BASE__INST5_SEG0 = 0 # macro -PCIE0_BASE__INST5_SEG1 = 0 # macro -PCIE0_BASE__INST5_SEG2 = 0 # macro -PCIE0_BASE__INST5_SEG3 = 0 # macro -PCIE0_BASE__INST5_SEG4 = 0 # macro -PCIE0_BASE__INST6_SEG0 = 0 # macro -PCIE0_BASE__INST6_SEG1 = 0 # macro -PCIE0_BASE__INST6_SEG2 = 0 # macro -PCIE0_BASE__INST6_SEG3 = 0 # macro -PCIE0_BASE__INST6_SEG4 = 0 # macro -SDMA0_BASE__INST0_SEG0 = 0x00001260 # macro -SDMA0_BASE__INST0_SEG1 = 0x0000A000 # macro -SDMA0_BASE__INST0_SEG2 = 0x0001C000 # macro -SDMA0_BASE__INST0_SEG3 = 0x02402C00 # macro -SDMA0_BASE__INST0_SEG4 = 0 # macro -SDMA0_BASE__INST1_SEG0 = 0 # macro -SDMA0_BASE__INST1_SEG1 = 0 # macro -SDMA0_BASE__INST1_SEG2 = 0 # macro -SDMA0_BASE__INST1_SEG3 = 0 # macro -SDMA0_BASE__INST1_SEG4 = 0 # macro -SDMA0_BASE__INST2_SEG0 = 0 # macro -SDMA0_BASE__INST2_SEG1 = 0 # macro -SDMA0_BASE__INST2_SEG2 = 0 # macro -SDMA0_BASE__INST2_SEG3 = 0 # macro -SDMA0_BASE__INST2_SEG4 = 0 # macro -SDMA0_BASE__INST3_SEG0 = 0 # macro -SDMA0_BASE__INST3_SEG1 = 0 # macro -SDMA0_BASE__INST3_SEG2 = 0 # macro -SDMA0_BASE__INST3_SEG3 = 0 # macro -SDMA0_BASE__INST3_SEG4 = 0 # macro -SDMA0_BASE__INST4_SEG0 = 0 # macro -SDMA0_BASE__INST4_SEG1 = 0 # macro -SDMA0_BASE__INST4_SEG2 = 0 # macro -SDMA0_BASE__INST4_SEG3 = 0 # macro -SDMA0_BASE__INST4_SEG4 = 0 # macro -SDMA0_BASE__INST5_SEG0 = 0 # macro -SDMA0_BASE__INST5_SEG1 = 0 # macro -SDMA0_BASE__INST5_SEG2 = 0 # macro -SDMA0_BASE__INST5_SEG3 = 0 # macro -SDMA0_BASE__INST5_SEG4 = 0 # macro -SDMA0_BASE__INST6_SEG0 = 0 # macro -SDMA0_BASE__INST6_SEG1 = 0 # macro -SDMA0_BASE__INST6_SEG2 = 0 # macro -SDMA0_BASE__INST6_SEG3 = 0 # macro -SDMA0_BASE__INST6_SEG4 = 0 # macro -SDMA1_BASE__INST0_SEG0 = 0x00001260 # macro -SDMA1_BASE__INST0_SEG1 = 0x0000A000 # macro -SDMA1_BASE__INST0_SEG2 = 0x0001C000 # macro -SDMA1_BASE__INST0_SEG3 = 0x02402C00 # macro -SDMA1_BASE__INST0_SEG4 = 0 # macro -SDMA1_BASE__INST1_SEG0 = 0 # macro -SDMA1_BASE__INST1_SEG1 = 0 # macro -SDMA1_BASE__INST1_SEG2 = 0 # macro -SDMA1_BASE__INST1_SEG3 = 0 # macro -SDMA1_BASE__INST1_SEG4 = 0 # macro -SDMA1_BASE__INST2_SEG0 = 0 # macro -SDMA1_BASE__INST2_SEG1 = 0 # macro -SDMA1_BASE__INST2_SEG2 = 0 # macro -SDMA1_BASE__INST2_SEG3 = 0 # macro -SDMA1_BASE__INST2_SEG4 = 0 # macro -SDMA1_BASE__INST3_SEG0 = 0 # macro -SDMA1_BASE__INST3_SEG1 = 0 # macro -SDMA1_BASE__INST3_SEG2 = 0 # macro -SDMA1_BASE__INST3_SEG3 = 0 # macro -SDMA1_BASE__INST3_SEG4 = 0 # macro -SDMA1_BASE__INST4_SEG0 = 0 # macro -SDMA1_BASE__INST4_SEG1 = 0 # macro -SDMA1_BASE__INST4_SEG2 = 0 # macro -SDMA1_BASE__INST4_SEG3 = 0 # macro -SDMA1_BASE__INST4_SEG4 = 0 # macro -SDMA1_BASE__INST5_SEG0 = 0 # macro -SDMA1_BASE__INST5_SEG1 = 0 # macro -SDMA1_BASE__INST5_SEG2 = 0 # macro -SDMA1_BASE__INST5_SEG3 = 0 # macro -SDMA1_BASE__INST5_SEG4 = 0 # macro -SDMA1_BASE__INST6_SEG0 = 0 # macro -SDMA1_BASE__INST6_SEG1 = 0 # macro -SDMA1_BASE__INST6_SEG2 = 0 # macro -SDMA1_BASE__INST6_SEG3 = 0 # macro -SDMA1_BASE__INST6_SEG4 = 0 # macro -SMUIO_BASE__INST0_SEG0 = 0x00016800 # macro -SMUIO_BASE__INST0_SEG1 = 0x00016A00 # macro -SMUIO_BASE__INST0_SEG2 = 0x00440000 # macro -SMUIO_BASE__INST0_SEG3 = 0x02401000 # macro -SMUIO_BASE__INST0_SEG4 = 0 # macro -SMUIO_BASE__INST1_SEG0 = 0 # macro -SMUIO_BASE__INST1_SEG1 = 0 # macro -SMUIO_BASE__INST1_SEG2 = 0 # macro -SMUIO_BASE__INST1_SEG3 = 0 # macro -SMUIO_BASE__INST1_SEG4 = 0 # macro -SMUIO_BASE__INST2_SEG0 = 0 # macro -SMUIO_BASE__INST2_SEG1 = 0 # macro -SMUIO_BASE__INST2_SEG2 = 0 # macro -SMUIO_BASE__INST2_SEG3 = 0 # macro -SMUIO_BASE__INST2_SEG4 = 0 # macro -SMUIO_BASE__INST3_SEG0 = 0 # macro -SMUIO_BASE__INST3_SEG1 = 0 # macro -SMUIO_BASE__INST3_SEG2 = 0 # macro -SMUIO_BASE__INST3_SEG3 = 0 # macro -SMUIO_BASE__INST3_SEG4 = 0 # macro -SMUIO_BASE__INST4_SEG0 = 0 # macro -SMUIO_BASE__INST4_SEG1 = 0 # macro -SMUIO_BASE__INST4_SEG2 = 0 # macro -SMUIO_BASE__INST4_SEG3 = 0 # macro -SMUIO_BASE__INST4_SEG4 = 0 # macro -SMUIO_BASE__INST5_SEG0 = 0 # macro -SMUIO_BASE__INST5_SEG1 = 0 # macro -SMUIO_BASE__INST5_SEG2 = 0 # macro -SMUIO_BASE__INST5_SEG3 = 0 # macro -SMUIO_BASE__INST5_SEG4 = 0 # macro -SMUIO_BASE__INST6_SEG0 = 0 # macro -SMUIO_BASE__INST6_SEG1 = 0 # macro -SMUIO_BASE__INST6_SEG2 = 0 # macro -SMUIO_BASE__INST6_SEG3 = 0 # macro -SMUIO_BASE__INST6_SEG4 = 0 # macro -THM_BASE__INST0_SEG0 = 0x00016600 # macro -THM_BASE__INST0_SEG1 = 0x02400C00 # macro -THM_BASE__INST0_SEG2 = 0 # macro -THM_BASE__INST0_SEG3 = 0 # macro -THM_BASE__INST0_SEG4 = 0 # macro -THM_BASE__INST1_SEG0 = 0 # macro -THM_BASE__INST1_SEG1 = 0 # macro -THM_BASE__INST1_SEG2 = 0 # macro -THM_BASE__INST1_SEG3 = 0 # macro -THM_BASE__INST1_SEG4 = 0 # macro -THM_BASE__INST2_SEG0 = 0 # macro -THM_BASE__INST2_SEG1 = 0 # macro -THM_BASE__INST2_SEG2 = 0 # macro -THM_BASE__INST2_SEG3 = 0 # macro -THM_BASE__INST2_SEG4 = 0 # macro -THM_BASE__INST3_SEG0 = 0 # macro -THM_BASE__INST3_SEG1 = 0 # macro -THM_BASE__INST3_SEG2 = 0 # macro -THM_BASE__INST3_SEG3 = 0 # macro -THM_BASE__INST3_SEG4 = 0 # macro -THM_BASE__INST4_SEG0 = 0 # macro -THM_BASE__INST4_SEG1 = 0 # macro -THM_BASE__INST4_SEG2 = 0 # macro -THM_BASE__INST4_SEG3 = 0 # macro -THM_BASE__INST4_SEG4 = 0 # macro -THM_BASE__INST5_SEG0 = 0 # macro -THM_BASE__INST5_SEG1 = 0 # macro -THM_BASE__INST5_SEG2 = 0 # macro -THM_BASE__INST5_SEG3 = 0 # macro -THM_BASE__INST5_SEG4 = 0 # macro -THM_BASE__INST6_SEG0 = 0 # macro -THM_BASE__INST6_SEG1 = 0 # macro -THM_BASE__INST6_SEG2 = 0 # macro -THM_BASE__INST6_SEG3 = 0 # macro -THM_BASE__INST6_SEG4 = 0 # macro -UMC_BASE__INST0_SEG0 = 0x00014000 # macro -UMC_BASE__INST0_SEG1 = 0x02425800 # macro -UMC_BASE__INST0_SEG2 = 0 # macro -UMC_BASE__INST0_SEG3 = 0 # macro -UMC_BASE__INST0_SEG4 = 0 # macro -UMC_BASE__INST1_SEG0 = 0x00054000 # macro -UMC_BASE__INST1_SEG1 = 0x02425C00 # macro -UMC_BASE__INST1_SEG2 = 0 # macro -UMC_BASE__INST1_SEG3 = 0 # macro -UMC_BASE__INST1_SEG4 = 0 # macro -UMC_BASE__INST2_SEG0 = 0x00094000 # macro -UMC_BASE__INST2_SEG1 = 0x02426000 # macro -UMC_BASE__INST2_SEG2 = 0 # macro -UMC_BASE__INST2_SEG3 = 0 # macro -UMC_BASE__INST2_SEG4 = 0 # macro -UMC_BASE__INST3_SEG0 = 0x000D4000 # macro -UMC_BASE__INST3_SEG1 = 0x02426400 # macro -UMC_BASE__INST3_SEG2 = 0 # macro -UMC_BASE__INST3_SEG3 = 0 # macro -UMC_BASE__INST3_SEG4 = 0 # macro -UMC_BASE__INST4_SEG0 = 0x00114000 # macro -UMC_BASE__INST4_SEG1 = 0x02426800 # macro -UMC_BASE__INST4_SEG2 = 0 # macro -UMC_BASE__INST4_SEG3 = 0 # macro -UMC_BASE__INST4_SEG4 = 0 # macro -UMC_BASE__INST5_SEG0 = 0x00154000 # macro -UMC_BASE__INST5_SEG1 = 0x02426C00 # macro -UMC_BASE__INST5_SEG2 = 0 # macro -UMC_BASE__INST5_SEG3 = 0 # macro -UMC_BASE__INST5_SEG4 = 0 # macro -UMC_BASE__INST6_SEG0 = 0x00194000 # macro -UMC_BASE__INST6_SEG1 = 0x02427000 # macro -UMC_BASE__INST6_SEG2 = 0 # macro -UMC_BASE__INST6_SEG3 = 0 # macro -UMC_BASE__INST6_SEG4 = 0 # macro -USB0_BASE__INST0_SEG0 = 0x0242A800 # macro -USB0_BASE__INST0_SEG1 = 0x05B00000 # macro -USB0_BASE__INST0_SEG2 = 0 # macro -USB0_BASE__INST0_SEG3 = 0 # macro -USB0_BASE__INST0_SEG4 = 0 # macro -USB0_BASE__INST1_SEG0 = 0 # macro -USB0_BASE__INST1_SEG1 = 0 # macro -USB0_BASE__INST1_SEG2 = 0 # macro -USB0_BASE__INST1_SEG3 = 0 # macro -USB0_BASE__INST1_SEG4 = 0 # macro -USB0_BASE__INST2_SEG0 = 0 # macro -USB0_BASE__INST2_SEG1 = 0 # macro -USB0_BASE__INST2_SEG2 = 0 # macro -USB0_BASE__INST2_SEG3 = 0 # macro -USB0_BASE__INST2_SEG4 = 0 # macro -USB0_BASE__INST3_SEG0 = 0 # macro -USB0_BASE__INST3_SEG1 = 0 # macro -USB0_BASE__INST3_SEG2 = 0 # macro -USB0_BASE__INST3_SEG3 = 0 # macro -USB0_BASE__INST3_SEG4 = 0 # macro -USB0_BASE__INST4_SEG0 = 0 # macro -USB0_BASE__INST4_SEG1 = 0 # macro -USB0_BASE__INST4_SEG2 = 0 # macro -USB0_BASE__INST4_SEG3 = 0 # macro -USB0_BASE__INST4_SEG4 = 0 # macro -USB0_BASE__INST5_SEG0 = 0 # macro -USB0_BASE__INST5_SEG1 = 0 # macro -USB0_BASE__INST5_SEG2 = 0 # macro -USB0_BASE__INST5_SEG3 = 0 # macro -USB0_BASE__INST5_SEG4 = 0 # macro -USB0_BASE__INST6_SEG0 = 0 # macro -USB0_BASE__INST6_SEG1 = 0 # macro -USB0_BASE__INST6_SEG2 = 0 # macro -USB0_BASE__INST6_SEG3 = 0 # macro -USB0_BASE__INST6_SEG4 = 0 # macro -VCN_BASE__INST0_SEG0 = 0x00007800 # macro -VCN_BASE__INST0_SEG1 = 0x00007E00 # macro -VCN_BASE__INST0_SEG2 = 0x02403000 # macro -VCN_BASE__INST0_SEG3 = 0 # macro -VCN_BASE__INST0_SEG4 = 0 # macro -VCN_BASE__INST1_SEG0 = 0x00007B00 # macro -VCN_BASE__INST1_SEG1 = 0x00012000 # macro -VCN_BASE__INST1_SEG2 = 0x02445000 # macro -VCN_BASE__INST1_SEG3 = 0 # macro -VCN_BASE__INST1_SEG4 = 0 # macro -VCN_BASE__INST2_SEG0 = 0 # macro -VCN_BASE__INST2_SEG1 = 0 # macro -VCN_BASE__INST2_SEG2 = 0 # macro -VCN_BASE__INST2_SEG3 = 0 # macro -VCN_BASE__INST2_SEG4 = 0 # macro -VCN_BASE__INST3_SEG0 = 0 # macro -VCN_BASE__INST3_SEG1 = 0 # macro -VCN_BASE__INST3_SEG2 = 0 # macro -VCN_BASE__INST3_SEG3 = 0 # macro -VCN_BASE__INST3_SEG4 = 0 # macro -VCN_BASE__INST4_SEG0 = 0 # macro -VCN_BASE__INST4_SEG1 = 0 # macro -VCN_BASE__INST4_SEG2 = 0 # macro -VCN_BASE__INST4_SEG3 = 0 # macro -VCN_BASE__INST4_SEG4 = 0 # macro -VCN_BASE__INST5_SEG0 = 0 # macro -VCN_BASE__INST5_SEG1 = 0 # macro -VCN_BASE__INST5_SEG2 = 0 # macro -VCN_BASE__INST5_SEG3 = 0 # macro -VCN_BASE__INST5_SEG4 = 0 # macro -VCN_BASE__INST6_SEG0 = 0 # macro -VCN_BASE__INST6_SEG1 = 0 # macro -VCN_BASE__INST6_SEG2 = 0 # macro -VCN_BASE__INST6_SEG3 = 0 # macro -VCN_BASE__INST6_SEG4 = 0 # macro -class struct_IP_BASE_INSTANCE(Structure): - pass - -struct_IP_BASE_INSTANCE._pack_ = 1 # source:False -struct_IP_BASE_INSTANCE._fields_ = [ - ('segment', ctypes.c_uint32 * 5), -] - -class struct_IP_BASE(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instance', struct_IP_BASE_INSTANCE * 7), - ] - -__maybe_unused = struct_IP_BASE # Variable struct_IP_BASE -ATHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE -CLK_BASE = struct_IP_BASE # Variable struct_IP_BASE -DF_BASE = struct_IP_BASE # Variable struct_IP_BASE -DIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -DCN_BASE = struct_IP_BASE # Variable struct_IP_BASE -DPCS_BASE = struct_IP_BASE # Variable struct_IP_BASE -FUSE_BASE = struct_IP_BASE # Variable struct_IP_BASE -GC_BASE = struct_IP_BASE # Variable struct_IP_BASE -HDA_BASE = struct_IP_BASE # Variable struct_IP_BASE -HDP_BASE = struct_IP_BASE # Variable struct_IP_BASE -MMHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE -MP0_BASE = struct_IP_BASE # Variable struct_IP_BASE -MP1_BASE = struct_IP_BASE # Variable struct_IP_BASE -NBIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -OSSSYS_BASE = struct_IP_BASE # Variable struct_IP_BASE -PCIE0_BASE = struct_IP_BASE # Variable struct_IP_BASE -SDMA0_BASE = struct_IP_BASE # Variable struct_IP_BASE -SDMA1_BASE = struct_IP_BASE # Variable struct_IP_BASE -SMUIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -THM_BASE = struct_IP_BASE # Variable struct_IP_BASE -UMC_BASE = struct_IP_BASE # Variable struct_IP_BASE -USB0_BASE = struct_IP_BASE # Variable struct_IP_BASE -VCN_BASE = struct_IP_BASE # Variable struct_IP_BASE -__all__ = \ - ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', - 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', - 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', - 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', - 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', - 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', - 'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', 'ADDR_RESERVED', - 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', - 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', - 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', - 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', - 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', - 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', - 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', - 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', - 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', - 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', - 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', - 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', - 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', - 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', - 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', - 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', - 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', - 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', - 'AFMT_AUDIO_PACKET_SENT_DISABLED', - 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', - 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', - 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', - 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', - 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', - 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', - 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', - 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', - 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', - 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', - 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', - 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', - 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', - 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', - 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', - 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', - 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', - 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', - 'ALPHA_DATA_ONTO_Y_G_PORT', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', - 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', - 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', - 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', - 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', - 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', - 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', - 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', - 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', - 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', - 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', - 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', - 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', - 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', - 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', - 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', - 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', - 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', - 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', - 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', - 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', - 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', - 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', - 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', - 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', - 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', - 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', - 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', - 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', - 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', - 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', - 'ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1', - 'ATHUB_BASE__INST0_SEG2', 'ATHUB_BASE__INST0_SEG3', - 'ATHUB_BASE__INST0_SEG4', 'ATHUB_BASE__INST1_SEG0', - 'ATHUB_BASE__INST1_SEG1', 'ATHUB_BASE__INST1_SEG2', - 'ATHUB_BASE__INST1_SEG3', 'ATHUB_BASE__INST1_SEG4', - 'ATHUB_BASE__INST2_SEG0', 'ATHUB_BASE__INST2_SEG1', - 'ATHUB_BASE__INST2_SEG2', 'ATHUB_BASE__INST2_SEG3', - 'ATHUB_BASE__INST2_SEG4', 'ATHUB_BASE__INST3_SEG0', - 'ATHUB_BASE__INST3_SEG1', 'ATHUB_BASE__INST3_SEG2', - 'ATHUB_BASE__INST3_SEG3', 'ATHUB_BASE__INST3_SEG4', - 'ATHUB_BASE__INST4_SEG0', 'ATHUB_BASE__INST4_SEG1', - 'ATHUB_BASE__INST4_SEG2', 'ATHUB_BASE__INST4_SEG3', - 'ATHUB_BASE__INST4_SEG4', 'ATHUB_BASE__INST5_SEG0', - 'ATHUB_BASE__INST5_SEG1', 'ATHUB_BASE__INST5_SEG2', - 'ATHUB_BASE__INST5_SEG3', 'ATHUB_BASE__INST5_SEG4', - 'ATHUB_BASE__INST6_SEG0', 'ATHUB_BASE__INST6_SEG1', - 'ATHUB_BASE__INST6_SEG2', 'ATHUB_BASE__INST6_SEG3', - 'ATHUB_BASE__INST6_SEG4', 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', - 'AUDIO_LAYOUT_SELECT', 'AUTOCAL_MODE_AUTOCENTER', - 'AUTOCAL_MODE_AUTOREPLICATE', 'AUTOCAL_MODE_AUTOSCALE', - 'AUTOCAL_MODE_OFF', 'AYCrCb16161616_10LSB', - 'AYCrCb16161616_10MSB', 'AYCrCb16161616_12LSB', - 'AYCrCb16161616_12MSB', 'AYCrCb8888', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', - 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', - 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', - 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', - 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', - 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', - 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', - 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', - 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', - 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', - 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', - 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', - 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', - 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', - 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', - 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', - 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', - 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', - 'AZ_RIRB_WRITE_POINTER_DO_RESET', - 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', - 'AZ_STATE_CHANGE_STATUS', - 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', - 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', - 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', - 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', - 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', - 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', - 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', - 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', - 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', - 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', - 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', - 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', - 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', - 'BLEND_ONE_MINUS_CONSTANT_ALPHA', - 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', - 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', - 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', - 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', - 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', - 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', - 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', - 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', - 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', - 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', - 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS', - 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT', - 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', - 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', - 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', - 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', - 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA', - 'CACHE_NOA_WR', 'CACHE_STREAM', 'CACHE_STREAM_RD', 'CBMode', - 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', - 'CBRamList', 'CB_B_DATA_ONTO_ALPHA_PORT', - 'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT', - 'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', - 'CB_DCG_BACKEND_RDLAT_FIFO', 'CB_DCG_CCC_CAS_COLOR_PTR', - 'CB_DCG_CCC_CAS_FRAG_PTR', 'CB_DCG_CCC_CAS_KEYID', - 'CB_DCG_CCC_CAS_SURF_PARAM', 'CB_DCG_CCC_CAS_TAG_ARRAY', - 'CB_DCG_COLOR_STORE', 'CB_DCG_COLOR_STORE_DIRTY_BYTE', - 'CB_DCG_DCC_CACHE', 'CB_DCG_DCC_DIRTY_BITS', - 'CB_DCG_FMASK_CACHE_STORE', 'CB_DCG_FRONTEND_RDLAT_FIFO', - 'CB_DCG_OUTPUT_FIFO', 'CB_DCG_QBLOCK_ALLOC', - 'CB_DCG_QUAD_PTR_FIFO', 'CB_DCG_READ_SKID_FIFO', - 'CB_DCG_SRC_FIFO', 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', - 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', - 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', - 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', - 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', - 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', - 'CB_PERF_OP_FILTER_SEL_RESOLVE', - 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', - 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', - 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', - 'CB_PERF_SEL_BLEND_CLOCK_EN', - 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', - 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', - 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', - 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', - 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', - 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', - 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', - 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_CC_CACHE_FLUSH', - 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', - 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', - 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', - 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_CC_CACHE_TAG_MISS', - 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', - 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', - 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', - 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', - 'CB_PERF_SEL_CC_MC_READ_REQUEST', - 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', - 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', - 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT', - 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', - 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', - 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', - 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', - 'CB_PERF_SEL_DCC_CACHE_FLUSH', - 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', - 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', - 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', - 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', - 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', - 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', - 'CB_PERF_SEL_DCC_CACHE_STALL', - 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', - 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', - 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', - 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', - 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', - 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', - 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', - 'CB_PERF_SEL_EVENT_CONTEXT_DONE', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', - 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', - 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', - 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD', - 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', - 'CB_PERF_SEL_FILTER_DRAWN_TILE', - 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', - 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', - 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', - 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', - 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN', - 'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119', - 'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121', - 'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123', - 'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125', - 'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127', - 'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129', - 'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131', - 'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133', - 'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135', - 'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137', - 'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139', - 'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141', - 'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143', - 'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145', - 'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147', - 'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149', - 'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166', - 'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168', - 'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170', - 'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172', - 'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174', - 'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176', - 'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178', - 'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180', - 'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182', - 'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184', - 'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186', - 'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188', - 'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190', - 'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192', - 'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194', - 'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196', - 'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198', - 'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205', - 'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207', - 'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209', - 'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210', - 'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212', - 'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214', - 'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216', - 'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218', - 'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22', - 'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221', - 'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223', - 'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225', - 'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227', - 'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229', - 'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230', - 'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232', - 'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234', - 'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236', - 'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238', - 'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24', - 'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241', - 'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243', - 'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245', - 'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247', - 'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249', - 'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259', - 'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260', - 'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262', - 'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264', - 'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266', - 'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268', - 'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27', - 'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271', - 'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273', - 'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275', - 'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277', - 'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279', - 'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280', - 'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282', - 'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284', - 'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286', - 'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288', - 'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29', - 'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291', - 'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293', - 'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295', - 'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297', - 'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299', - 'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304', - 'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306', - 'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308', - 'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310', - 'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312', - 'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314', - 'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316', - 'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318', - 'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320', - 'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322', - 'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324', - 'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326', - 'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328', - 'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330', - 'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332', - 'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334', - 'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336', - 'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338', - 'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340', - 'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342', - 'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344', - 'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346', - 'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348', - 'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350', - 'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352', - 'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354', - 'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356', - 'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358', - 'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360', - 'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362', - 'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364', - 'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366', - 'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368', - 'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370', - 'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372', - 'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374', - 'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376', - 'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378', - 'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38', - 'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381', - 'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383', - 'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385', - 'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387', - 'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389', - 'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390', - 'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392', - 'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394', - 'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396', - 'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398', - 'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40', - 'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401', - 'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403', - 'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405', - 'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407', - 'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409', - 'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410', - 'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412', - 'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414', - 'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416', - 'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418', - 'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42', - 'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421', - 'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423', - 'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425', - 'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427', - 'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429', - 'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430', - 'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432', - 'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434', - 'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436', - 'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438', - 'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44', - 'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441', - 'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443', - 'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445', - 'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447', - 'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449', - 'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450', - 'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452', - 'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454', - 'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456', - 'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458', - 'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46', - 'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461', - 'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463', - 'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465', - 'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48', - 'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65', - 'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67', - 'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69', - 'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71', - 'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73', - 'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75', - 'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77', - 'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79', - 'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81', - 'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83', - 'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85', - 'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87', - 'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89', - 'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91', - 'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93', - 'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95', - 'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97', - 'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99', - 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', - 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', - 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', - 'CE_PARTITION_BASE', 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', - 'CHA_PERF_SEL_BUSY', 'CHA_PERF_SEL_CYCLE', - 'CHA_PERF_SEL_IO_32B_WDS_CHC0', 'CHA_PERF_SEL_IO_32B_WDS_CHC1', - 'CHA_PERF_SEL_IO_32B_WDS_CHC2', 'CHA_PERF_SEL_IO_32B_WDS_CHC3', - 'CHA_PERF_SEL_IO_32B_WDS_CHC4', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', - 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', - 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', - 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', - 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', - 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0', - 'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2', - 'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4', - 'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', - 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', - 'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY', - 'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', - 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ', - 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0', - 'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10', - 'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12', - 'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14', - 'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16', - 'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18', - 'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2', - 'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21', - 'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23', - 'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4', - 'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6', - 'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8', - 'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK', - 'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ', - 'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B', - 'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE', - 'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B', - 'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1', - 'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL', - 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', - 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', - 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', - 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', - 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', - 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', - 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', - 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', - 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', - 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', - 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', - 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', - 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', - 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', - 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', - 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', - 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', - 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', - 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', - 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', - 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', - 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', - 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', - 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', - 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', - 'CLK_BASE', 'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1', - 'CLK_BASE__INST0_SEG2', 'CLK_BASE__INST0_SEG3', - 'CLK_BASE__INST0_SEG4', 'CLK_BASE__INST1_SEG0', - 'CLK_BASE__INST1_SEG1', 'CLK_BASE__INST1_SEG2', - 'CLK_BASE__INST1_SEG3', 'CLK_BASE__INST1_SEG4', - 'CLK_BASE__INST2_SEG0', 'CLK_BASE__INST2_SEG1', - 'CLK_BASE__INST2_SEG2', 'CLK_BASE__INST2_SEG3', - 'CLK_BASE__INST2_SEG4', 'CLK_BASE__INST3_SEG0', - 'CLK_BASE__INST3_SEG1', 'CLK_BASE__INST3_SEG2', - 'CLK_BASE__INST3_SEG3', 'CLK_BASE__INST3_SEG4', - 'CLK_BASE__INST4_SEG0', 'CLK_BASE__INST4_SEG1', - 'CLK_BASE__INST4_SEG2', 'CLK_BASE__INST4_SEG3', - 'CLK_BASE__INST4_SEG4', 'CLK_BASE__INST5_SEG0', - 'CLK_BASE__INST5_SEG1', 'CLK_BASE__INST5_SEG2', - 'CLK_BASE__INST5_SEG3', 'CLK_BASE__INST5_SEG4', - 'CLK_BASE__INST6_SEG0', 'CLK_BASE__INST6_SEG1', - 'CLK_BASE__INST6_SEG2', 'CLK_BASE__INST6_SEG3', - 'CLK_BASE__INST6_SEG4', 'CLOCK_BRANCH_SOFT_RESET', - 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', - 'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED', - 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM', - 'CLOCK_GATING_DISABLE_ENUM_DISABLED', - 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', - 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', - 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', - 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', - 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', - 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', - 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', - 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', - 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', - 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', - 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', - 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', - 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', - 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', - 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', - 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', - 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', - 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', - 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', - 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', - 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', - 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', - 'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM', - 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', - 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', - 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL', - 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING', - 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY', - 'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE', - 'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN', - 'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12', - 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE', - 'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B', - 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', - 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', - 'COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', - 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE', - 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', - 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL', - 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', - 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', - 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', - 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', - 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', - 'CORB_READ_POINTER_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', - 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', - 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', - 'CPC_LATENCY_STATS_SEL_INVAL_LAST', - 'CPC_LATENCY_STATS_SEL_INVAL_MAX', - 'CPC_LATENCY_STATS_SEL_INVAL_MIN', - 'CPC_LATENCY_STATS_SEL_XACK_LAST', - 'CPC_LATENCY_STATS_SEL_XACK_MAX', - 'CPC_LATENCY_STATS_SEL_XACK_MIN', - 'CPC_LATENCY_STATS_SEL_XNACK_LAST', - 'CPC_LATENCY_STATS_SEL_XNACK_MAX', - 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', - 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', - 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', - 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', - 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', - 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', - 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', - 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', - 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', - 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', - 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', - 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', - 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0', - 'CPC_PERF_SEL_MES_THREAD1', - 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', - 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', - 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', - 'CPF_LATENCY_STATS_SEL_INVAL_MAX', - 'CPF_LATENCY_STATS_SEL_INVAL_MIN', - 'CPF_LATENCY_STATS_SEL_READ_LAST', - 'CPF_LATENCY_STATS_SEL_READ_MAX', - 'CPF_LATENCY_STATS_SEL_READ_MIN', - 'CPF_LATENCY_STATS_SEL_XACK_LAST', - 'CPF_LATENCY_STATS_SEL_XACK_MAX', - 'CPF_LATENCY_STATS_SEL_XACK_MIN', - 'CPF_LATENCY_STATS_SEL_XNACK_LAST', - 'CPF_LATENCY_STATS_SEL_XNACK_MAX', - 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', - 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', - 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', - 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', - 'CPF_PERF_SEL_ALWAYS_COUNT', - 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', - 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', - 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', - 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', - 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', - 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', - 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', - 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', - 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', - 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', - 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', - 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', - 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', - 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', - 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', - 'CPF_PERF_SEL_GRBM_DWORDS_SENT', - 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', - 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', - 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', - 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', - 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', - 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', - 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', - 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', - 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', - 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', - 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', - 'CPG_LATENCY_STATS_SEL_INVAL_LAST', - 'CPG_LATENCY_STATS_SEL_INVAL_MAX', - 'CPG_LATENCY_STATS_SEL_INVAL_MIN', - 'CPG_LATENCY_STATS_SEL_READ_LAST', - 'CPG_LATENCY_STATS_SEL_READ_MAX', - 'CPG_LATENCY_STATS_SEL_READ_MIN', - 'CPG_LATENCY_STATS_SEL_WRITE_LAST', - 'CPG_LATENCY_STATS_SEL_WRITE_MAX', - 'CPG_LATENCY_STATS_SEL_WRITE_MIN', - 'CPG_LATENCY_STATS_SEL_XACK_LAST', - 'CPG_LATENCY_STATS_SEL_XACK_MAX', - 'CPG_LATENCY_STATS_SEL_XACK_MIN', - 'CPG_LATENCY_STATS_SEL_XNACK_LAST', - 'CPG_LATENCY_STATS_SEL_XNACK_MAX', - 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', - 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', - 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', - 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', - 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', - 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', - 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', - 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', - 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', - 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', - 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', - 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', - 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', - 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', - 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', - 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', - 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', - 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', - 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', - 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', - 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', - 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', - 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', - 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', - 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', - 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', - 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', - 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', - 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', - 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', - 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', - 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', - 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', - 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', - 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', - 'CPG_PERF_SEL_DMA_BUSY', - 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', - 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', - 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', - 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', - 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', - 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', - 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', - 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', - 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', - 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', - 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', - 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', - 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', - 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', - 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', - 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', - 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', - 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', - 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', - 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', - 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', - 'CPG_PERF_SEL_RBIU_FIFO_FULL', - 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', - 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', - 'CPG_PERF_SEL_REGISTER_CLK_VALID', - 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', - 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', - 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', - 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', - 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', - 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', - 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', - 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PACKET2', - 'CP_PERFMON_ENABLE_MODE', 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', - 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', - 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', - 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'CP_PERFMON_STATE_DISABLE_AND_RESET', - 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', - 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', - 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', - 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', - 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', - 'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', - 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', - 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', - 'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', - 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', - 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', - 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', - 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', - 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', - 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', - 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', - 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', - 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', - 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', - 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', - 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', - 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', - 'CURSOR_COLOR_24BIT_1BIT_AND', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', - 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', - 'CURSOR_COLOR_64BIT_FP_PREMULT', - 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', - 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', - 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', - 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', - 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', - 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', - 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', - 'CURSOR_MODE', 'CURSOR_MONO_2BIT', - 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_EN', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', - 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', - 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', - 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', - 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', - 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', - 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', - 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', - 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', - 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', - 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', - 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', - 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', - 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', - 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', - 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', - 'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag', - 'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102', - 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', - 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', - 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', - 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', - 'DAC_MUX_SELECT_DACB', 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', - 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', - 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', - 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', - 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', - 'DB_INVOKE_CHANGE_EVENT', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', - 'DB_PERF_SEL_CB_DB_rdreq_sends', - 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', - 'DB_PERF_SEL_CB_DB_wrreq_sends', - 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', - 'DB_PERF_SEL_DB_CB_lquad_busy', - 'DB_PERF_SEL_DB_CB_lquad_double_format', - 'DB_PERF_SEL_DB_CB_lquad_export_quads', - 'DB_PERF_SEL_DB_CB_lquad_fast_format', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', - 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', - 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', - 'DB_PERF_SEL_DB_CB_lquad_quads', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', - 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', - 'DB_PERF_SEL_DB_CB_lquad_sends', - 'DB_PERF_SEL_DB_CB_lquad_slow_format', - 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', - 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', - 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', - 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', - 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', - 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', - 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', - 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', - 'DB_PERF_SEL_DB_SC_quad_double_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', - 'DB_PERF_SEL_DB_SC_quad_lit_quad', - 'DB_PERF_SEL_DB_SC_quad_noz_tiles', - 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', - 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', - 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', - 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', - 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', - 'DB_PERF_SEL_DB_SC_tile_df_stalls', - 'DB_PERF_SEL_DB_SC_tile_fast_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', - 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', - 'DB_PERF_SEL_DB_SC_tile_hier_kill', - 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', - 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', - 'DB_PERF_SEL_DB_SC_tile_stalls', - 'DB_PERF_SEL_DB_SC_tile_tile_rate', - 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', - 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', - 'DB_PERF_SEL_Depth_Tile_Cache_busy', - 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', - 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', - 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', - 'DB_PERF_SEL_Depth_Tile_Cache_event', - 'DB_PERF_SEL_Depth_Tile_Cache_flushes', - 'DB_PERF_SEL_Depth_Tile_Cache_hits', - 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Depth_Tile_Cache_misses', - 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', - 'DB_PERF_SEL_Depth_Tile_Cache_sends', - 'DB_PERF_SEL_Depth_Tile_Cache_starves', - 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', - 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', - 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', - 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', - 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', - 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', - 'DB_PERF_SEL_Plane_Cache_flushes', - 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', - 'DB_PERF_SEL_Plane_Cache_misses', - 'DB_PERF_SEL_Plane_Cache_starves', - 'DB_PERF_SEL_PostZ_Samples_failing_DB', - 'DB_PERF_SEL_PostZ_Samples_failing_S', - 'DB_PERF_SEL_PostZ_Samples_failing_Z', - 'DB_PERF_SEL_PostZ_Samples_passing_Z', - 'DB_PERF_SEL_PreZ_Samples_failing_DB', - 'DB_PERF_SEL_PreZ_Samples_failing_S', - 'DB_PERF_SEL_PreZ_Samples_failing_Z', - 'DB_PERF_SEL_PreZ_Samples_passing_Z', - 'DB_PERF_SEL_RMI_rd_s_32byte_req', - 'DB_PERF_SEL_RMI_rd_s_32byte_ret', - 'DB_PERF_SEL_RMI_rd_tile_32byte_req', - 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', - 'DB_PERF_SEL_RMI_rd_z_32byte_req', - 'DB_PERF_SEL_RMI_rd_z_32byte_ret', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', - 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', - 'DB_PERF_SEL_RMI_wr_s_32byte_ack', - 'DB_PERF_SEL_RMI_wr_s_32byte_req', - 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', - 'DB_PERF_SEL_RMI_wr_tile_32byte_req', - 'DB_PERF_SEL_RMI_wr_z_32byte_ack', - 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', - 'DB_PERF_SEL_SC_DB_quad_killed_tiles', - 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', - 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', - 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', - 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', - 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', - 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', - 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', - 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', - 'DB_PERF_SEL_SH_quads_outstanding_sum', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', - 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', - 'DB_PERF_SEL_SX_DB_quad_busy', - 'DB_PERF_SEL_SX_DB_quad_double_format', - 'DB_PERF_SEL_SX_DB_quad_export_quads', - 'DB_PERF_SEL_SX_DB_quad_exports', - 'DB_PERF_SEL_SX_DB_quad_fast_format', - 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', - 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', - 'DB_PERF_SEL_SX_DB_quad_sends', - 'DB_PERF_SEL_SX_DB_quad_slow_format', - 'DB_PERF_SEL_SX_DB_quad_stalls', - 'DB_PERF_SEL_Stencil_Cache_flushes', - 'DB_PERF_SEL_Stencil_Cache_frees', - 'DB_PERF_SEL_Stencil_Cache_hits', - 'DB_PERF_SEL_Stencil_Cache_misses', - 'DB_PERF_SEL_Stencil_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', - 'DB_PERF_SEL_Tile_Cache_mem_return_starve', - 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', - 'DB_PERF_SEL_Tile_Cache_surface_stall', - 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', - 'DB_PERF_SEL_Z_Cache_pmask_hits', - 'DB_PERF_SEL_Z_Cache_pmask_misses', - 'DB_PERF_SEL_Z_Cache_pmask_starves', - 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', - 'DB_PERF_SEL_Z_Cache_separate_Z_hits', - 'DB_PERF_SEL_Z_Cache_separate_Z_misses', - 'DB_PERF_SEL_Z_Cache_separate_Z_starves', - 'DB_PERF_SEL_clock_main_active', - 'DB_PERF_SEL_clock_mem_export_active', - 'DB_PERF_SEL_clock_reg_active', - 'DB_PERF_SEL_cs_events_pws_enable', - 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', - 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', - 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', - 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', - 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', - 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', - 'DB_PERF_SEL_dtt_sm_slot_stall', - 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', - 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', - 'DB_PERF_SEL_esr_eot_fwd_holding_squad', - 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', - 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', - 'DB_PERF_SEL_esr_ps_src_in_squads', - 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_stall', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', - 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', - 'DB_PERF_SEL_esr_ps_vic_stall', - 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', - 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', - 'DB_PERF_SEL_esr_psi_vic_tile_rate', - 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', - 'DB_PERF_SEL_esr_vic_footprint_match_1x2', - 'DB_PERF_SEL_esr_vic_footprint_match_2x1', - 'DB_PERF_SEL_esr_vic_footprint_match_2x2', - 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', - 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', - 'DB_PERF_SEL_etr_out_esr_stall', - 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', - 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', - 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', - 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', - 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', - 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', - 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', - 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', - 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', - 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', - 'DB_PERF_SEL_flush_compressed_stencil', - 'DB_PERF_SEL_flush_expanded_stencil', - 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', - 'DB_PERF_SEL_flush_single_stencil', - 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', - 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', - 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', - 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', - 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', - 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', - 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', - 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', - 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', - 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', - 'DB_PERF_SEL_noz_waiting_for_postz_done', - 'DB_PERF_SEL_planes_flushed', - 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_postzl_full_launch', - 'DB_PERF_SEL_postzl_partial_launch', - 'DB_PERF_SEL_postzl_partial_waiting', - 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', - 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', - 'DB_PERF_SEL_postzl_src_in_sends', - 'DB_PERF_SEL_postzl_src_in_squads', - 'DB_PERF_SEL_postzl_src_in_squads_unrolled', - 'DB_PERF_SEL_postzl_src_in_stall', - 'DB_PERF_SEL_postzl_src_in_tile_rate', - 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_postzl_src_out_stall', - 'DB_PERF_SEL_postzl_tile_init_stall', - 'DB_PERF_SEL_postzl_tile_mem_stall', - 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', - 'DB_PERF_SEL_prezl_src_in_sends', - 'DB_PERF_SEL_prezl_src_in_squads', - 'DB_PERF_SEL_prezl_src_in_squads_unrolled', - 'DB_PERF_SEL_prezl_src_in_stall', - 'DB_PERF_SEL_prezl_src_in_tile_rate', - 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', - 'DB_PERF_SEL_prezl_src_out_stall', - 'DB_PERF_SEL_prezl_tile_init_stall', - 'DB_PERF_SEL_prezl_tile_mem_stall', - 'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy', - 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', - 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', - 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', - 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', - 'DB_PERF_SEL_quad_rd_mi_stall', - 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', - 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', - 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', - 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', - 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', - 'DB_PERF_SEL_quad_wr_coherency_stall', - 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', - 'DB_PERF_SEL_reZ_waiting_for_postZ_done', - 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', - 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', - 'DB_PERF_SEL_tcp_dispatcher_flushes', - 'DB_PERF_SEL_tcp_dispatcher_reads', - 'DB_PERF_SEL_tcp_prefetcher_flushes', - 'DB_PERF_SEL_tcp_prefetcher_reads', - 'DB_PERF_SEL_tcp_preloader_flushes', - 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', - 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', - 'DB_PERF_SEL_tiles_compressed_to_decompressed', - 'DB_PERF_SEL_tiles_decomp_on_expclear', - 'DB_PERF_SEL_tiles_s_clear_on_expclear', - 'DB_PERF_SEL_tiles_stencil_fully_summarized', - 'DB_PERF_SEL_tiles_z_clear_on_expclear', - 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', - 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', - 'DB_PERF_SEL_tl_expand_squads', - 'DB_PERF_SEL_tl_flush_expand_squads', - 'DB_PERF_SEL_tl_in_fast_z_stall', - 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', - 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', - 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', - 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', - 'DB_PERF_SEL_tl_preZ_squads', - 'DB_PERF_SEL_tl_stencil_locked_stall', - 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', - 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', - 'DB_PERF_SEL_tl_z_fetch_stall', - 'DB_PERF_SEL_ts_events_pws_enable', - 'DB_PERF_SEL_ts_tc_update_stall', - 'DB_PERF_SEL_tsc_insert_summarize_stall', - 'DB_PERF_SEL_unmapped_z_tile_culled', - 'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT', - 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', - 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', - 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', - 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', - 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', - 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', - 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', - 'DCCG_AUDIO_DTO_USE_512FBR_DTO', - 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', - 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', - 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', - 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', - 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', - 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', - 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', - 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', - 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', - 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', - 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', - 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', - 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', - 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', - 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', - 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', - 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', - 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', - 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', - 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', - 'DCHUBBUB_MEM_POWER_MODE_OFF', - 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', - 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', - 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', - 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', - 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', - 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', - 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', - 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', - 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', - 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', - 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', - 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', - 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', - 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', - 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', - 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', - 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', - 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', - 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', - 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', - 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', - 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', - 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', - 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', - 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', - 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', - 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', - 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', - 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', - 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', - 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', - 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', - 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', - 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', - 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', - 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', - 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', - 'DCIOCHIP_REF_27_SRC_SEL', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', - 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', - 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', - 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', - 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', - 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', - 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', - 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', - 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', - 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', - 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', - 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', - 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', - 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', - 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', - 'DCIO_DC_GENERICB_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', - 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', - 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', - 'DCIO_DC_GPU_TIMER_READ_SELECT', - 'DCIO_DC_GPU_TIMER_START_POSITION', - 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', - 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', - 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', - 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', - 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', - 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', - 'DCIO_DPCS_INTERRUPT_TYPE', - 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', - 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', - 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', - 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', - 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', - 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', - 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', - 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', - 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', - 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0', - 'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2', - 'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4', - 'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', - 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC', - 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG', - 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', - 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', - 'DCIO_GENLK_CLK_GSL_MASK_STEREO', - 'DCIO_GENLK_CLK_GSL_MASK_TIMING', - 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', - 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', - 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', - 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', - 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', - 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', - 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', - 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', - 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', - 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', - 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', - 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', - 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', - 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', - 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL', - 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', - 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', - 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', - 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', - 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', - 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', - 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', - 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', - 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', - 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', - 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', - 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', - 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', - 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', - 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', - 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', - 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', - 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', - 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', - 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', - 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DCN_BASE', - 'DCN_BASE__INST0_SEG0', 'DCN_BASE__INST0_SEG1', - 'DCN_BASE__INST0_SEG2', 'DCN_BASE__INST0_SEG3', - 'DCN_BASE__INST0_SEG4', 'DCN_BASE__INST1_SEG0', - 'DCN_BASE__INST1_SEG1', 'DCN_BASE__INST1_SEG2', - 'DCN_BASE__INST1_SEG3', 'DCN_BASE__INST1_SEG4', - 'DCN_BASE__INST2_SEG0', 'DCN_BASE__INST2_SEG1', - 'DCN_BASE__INST2_SEG2', 'DCN_BASE__INST2_SEG3', - 'DCN_BASE__INST2_SEG4', 'DCN_BASE__INST3_SEG0', - 'DCN_BASE__INST3_SEG1', 'DCN_BASE__INST3_SEG2', - 'DCN_BASE__INST3_SEG3', 'DCN_BASE__INST3_SEG4', - 'DCN_BASE__INST4_SEG0', 'DCN_BASE__INST4_SEG1', - 'DCN_BASE__INST4_SEG2', 'DCN_BASE__INST4_SEG3', - 'DCN_BASE__INST4_SEG4', 'DCN_BASE__INST5_SEG0', - 'DCN_BASE__INST5_SEG1', 'DCN_BASE__INST5_SEG2', - 'DCN_BASE__INST5_SEG3', 'DCN_BASE__INST5_SEG4', - 'DCN_BASE__INST6_SEG0', 'DCN_BASE__INST6_SEG1', - 'DCN_BASE__INST6_SEG2', 'DCN_BASE__INST6_SEG3', - 'DCN_BASE__INST6_SEG4', 'DC_DMCUB_INT_TYPE', - 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', - 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', - 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', - 'DEBUG_BUS_SELECT_ABM0', 'DEBUG_BUS_SELECT_ABM1', - 'DEBUG_BUS_SELECT_ABM2', 'DEBUG_BUS_SELECT_ABM3', - 'DEBUG_BUS_SELECT_ABM_RESERVED0', - 'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0', - 'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2', - 'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0', - 'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0', - 'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2', - 'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0', - 'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0', - 'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2', - 'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', - 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0', - 'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2', - 'DEBUG_BUS_SELECT_OPP_PIPE3', - 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', - 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR', - 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', - 'DETILE_BUFFER_PACKER_IS_DISABLE', - 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', - 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', - 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', - 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', - 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', - 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', - 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', - 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', - 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', - 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', - 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DF_BASE', - 'DF_BASE__INST0_SEG0', 'DF_BASE__INST0_SEG1', - 'DF_BASE__INST0_SEG2', 'DF_BASE__INST0_SEG3', - 'DF_BASE__INST0_SEG4', 'DF_BASE__INST1_SEG0', - 'DF_BASE__INST1_SEG1', 'DF_BASE__INST1_SEG2', - 'DF_BASE__INST1_SEG3', 'DF_BASE__INST1_SEG4', - 'DF_BASE__INST2_SEG0', 'DF_BASE__INST2_SEG1', - 'DF_BASE__INST2_SEG2', 'DF_BASE__INST2_SEG3', - 'DF_BASE__INST2_SEG4', 'DF_BASE__INST3_SEG0', - 'DF_BASE__INST3_SEG1', 'DF_BASE__INST3_SEG2', - 'DF_BASE__INST3_SEG3', 'DF_BASE__INST3_SEG4', - 'DF_BASE__INST4_SEG0', 'DF_BASE__INST4_SEG1', - 'DF_BASE__INST4_SEG2', 'DF_BASE__INST4_SEG3', - 'DF_BASE__INST4_SEG4', 'DF_BASE__INST5_SEG0', - 'DF_BASE__INST5_SEG1', 'DF_BASE__INST5_SEG2', - 'DF_BASE__INST5_SEG3', 'DF_BASE__INST5_SEG4', - 'DF_BASE__INST6_SEG0', 'DF_BASE__INST6_SEG1', - 'DF_BASE__INST6_SEG2', 'DF_BASE__INST6_SEG3', - 'DF_BASE__INST6_SEG4', 'DIFFERENT_RGB', 'DIG_10BIT_TEST_PATTERN', - 'DIG_ALL_PIXEL', 'DIG_ALTERNATING_TEST_PATTERN', - 'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', - 'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT', - 'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', - 'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', - 'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', - 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', - 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', - 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', - 'DIG_DIGITAL_BYPASS_SEL_36BPP', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', - 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', - 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', - 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', - 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', - 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', - 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED', - 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', - 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', - 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE', - 'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', - 'DIG_FIFO_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', - 'DIG_FIFO_FORCE_RECOMP_MINMAX', - 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', - 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', - 'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED', - 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', - 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', - 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', - 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL', - 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', - 'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', - 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', - 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', - 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', - 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS', - 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', - 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS', - 'DIG_SL_PIXEL_GROUPING', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', - 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', - 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', - 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', - 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', - 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', - 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', - 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', - 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', - 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', - 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', - 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', - 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', - 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', - 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', - 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', - 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_BASE', - 'DIO_BASE__INST0_SEG0', 'DIO_BASE__INST0_SEG1', - 'DIO_BASE__INST0_SEG2', 'DIO_BASE__INST0_SEG3', - 'DIO_BASE__INST0_SEG4', 'DIO_BASE__INST1_SEG0', - 'DIO_BASE__INST1_SEG1', 'DIO_BASE__INST1_SEG2', - 'DIO_BASE__INST1_SEG3', 'DIO_BASE__INST1_SEG4', - 'DIO_BASE__INST2_SEG0', 'DIO_BASE__INST2_SEG1', - 'DIO_BASE__INST2_SEG2', 'DIO_BASE__INST2_SEG3', - 'DIO_BASE__INST2_SEG4', 'DIO_BASE__INST3_SEG0', - 'DIO_BASE__INST3_SEG1', 'DIO_BASE__INST3_SEG2', - 'DIO_BASE__INST3_SEG3', 'DIO_BASE__INST3_SEG4', - 'DIO_BASE__INST4_SEG0', 'DIO_BASE__INST4_SEG1', - 'DIO_BASE__INST4_SEG2', 'DIO_BASE__INST4_SEG3', - 'DIO_BASE__INST4_SEG4', 'DIO_BASE__INST5_SEG0', - 'DIO_BASE__INST5_SEG1', 'DIO_BASE__INST5_SEG2', - 'DIO_BASE__INST5_SEG3', 'DIO_BASE__INST5_SEG4', - 'DIO_BASE__INST6_SEG0', 'DIO_BASE__INST6_SEG1', - 'DIO_BASE__INST6_SEG2', 'DIO_BASE__INST6_SEG3', - 'DIO_BASE__INST6_SEG4', 'DIO_DBG_BLOCK_SEL', - 'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1', - 'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3', - 'DIO_DBG_BLOCK_SEL_AUX4', 'DIO_DBG_BLOCK_SEL_DIGA', - 'DIO_DBG_BLOCK_SEL_DIGB', 'DIO_DBG_BLOCK_SEL_DIGC', - 'DIO_DBG_BLOCK_SEL_DIGD', 'DIO_DBG_BLOCK_SEL_DIGE', - 'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B', - 'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D', - 'DIO_DBG_BLOCK_SEL_DIGFE_E', 'DIO_DBG_BLOCK_SEL_DIO', - 'DIO_DBG_BLOCK_SEL_DPA', 'DIO_DBG_BLOCK_SEL_DPB', - 'DIO_DBG_BLOCK_SEL_DPC', 'DIO_DBG_BLOCK_SEL_DPD', - 'DIO_DBG_BLOCK_SEL_DPE', 'DIO_DBG_BLOCK_SEL_DPFE_A', - 'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C', - 'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_DPFE_E', - 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', 'DIO_DBG_BLOCK_SEL_RESERVED', - 'DIO_FIFO_ERROR', 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', - 'DIO_FIFO_ERROR_10', 'DIO_FIFO_ERROR_11', - 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', - 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', - 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', - 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', - 'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', - 'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', - 'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT', - 'DISPCLK_CHG_FWD_CORR_DISABLE', - 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', - 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', - 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', - 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', - 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', - 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', - 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', - 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', - 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', - 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', - 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', - 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', - 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', - 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', - 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DI_SRC_SEL_RESERVED', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', - 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', - 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', - 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', - 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', - 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', - 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', - 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', - 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', - 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', - 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', - 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', - 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', - 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', - 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', - 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', - 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', - 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', - 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', - 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', - 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', - 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', - 'DMU_DC_GPU_TIMER_START_POSITION', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', - 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', - 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', - 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', - 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', - 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', - 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', - 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', - 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', - 'DOUT_I2C_ACK_TO_CLEAN', - 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_ABORT_XFER', - 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', - 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', - 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', - 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', - 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', - 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', - 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', - 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', - 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', - 'DOUT_I2C_CONTROL_NORMAL_DEBUG', - 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', - 'DOUT_I2C_CONTROL_RESET_SW_STATUS', - 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', - 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', - 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', - 'DOUT_I2C_CONTROL_SEND_RESET', - 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', - 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', - 'DOUT_I2C_CONTROL_STOP_TRANSFER', - 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', - 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', - 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', - 'DOUT_I2C_CONTROL__NOT_SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', - 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', - 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', - 'DOUT_I2C_DATA__NOT_INDEX_WRITE', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', - 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', - 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', - 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', - 'DOUT_I2C_DDC_SPEED_THRESHOLD', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', - 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', - 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', - 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', - 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', - 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', - 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', - 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCS_BASE', - 'DPCS_BASE__INST0_SEG0', 'DPCS_BASE__INST0_SEG1', - 'DPCS_BASE__INST0_SEG2', 'DPCS_BASE__INST0_SEG3', - 'DPCS_BASE__INST0_SEG4', 'DPCS_BASE__INST1_SEG0', - 'DPCS_BASE__INST1_SEG1', 'DPCS_BASE__INST1_SEG2', - 'DPCS_BASE__INST1_SEG3', 'DPCS_BASE__INST1_SEG4', - 'DPCS_BASE__INST2_SEG0', 'DPCS_BASE__INST2_SEG1', - 'DPCS_BASE__INST2_SEG2', 'DPCS_BASE__INST2_SEG3', - 'DPCS_BASE__INST2_SEG4', 'DPCS_BASE__INST3_SEG0', - 'DPCS_BASE__INST3_SEG1', 'DPCS_BASE__INST3_SEG2', - 'DPCS_BASE__INST3_SEG3', 'DPCS_BASE__INST3_SEG4', - 'DPCS_BASE__INST4_SEG0', 'DPCS_BASE__INST4_SEG1', - 'DPCS_BASE__INST4_SEG2', 'DPCS_BASE__INST4_SEG3', - 'DPCS_BASE__INST4_SEG4', 'DPCS_BASE__INST5_SEG0', - 'DPCS_BASE__INST5_SEG1', 'DPCS_BASE__INST5_SEG2', - 'DPCS_BASE__INST5_SEG3', 'DPCS_BASE__INST5_SEG4', - 'DPCS_BASE__INST6_SEG0', 'DPCS_BASE__INST6_SEG1', - 'DPCS_BASE__INST6_SEG2', 'DPCS_BASE__INST6_SEG3', - 'DPCS_BASE__INST6_SEG4', 'DPHY_8B10B_CUR_DISP', - 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', - 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', - 'DPHY_8B10B_RESETET', - 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', - 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', - 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', - 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', - 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', - 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', - 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', - 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', - 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', - 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', - 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', - 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', - 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', - 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', - 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', - 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', - 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', - 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', - 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', - 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', - 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', - 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', - 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', - 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', - 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', - 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', - 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', - 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', - 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', - 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', - 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', - 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', - 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', - 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', - 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', - 'DPHY_SW_FAST_TRAINING_NOT_STARTED', - 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', - 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', - 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', - 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', - 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', - 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', - 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', - 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', - 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', - 'DPTE_GROUP_SIZE_64B', 'DP_128B132B', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', - 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', - 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', - 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', - 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', - 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', - 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', - 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', - 'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE', - 'DP_AUX_CONTROL_TEST_MODE_DISABLE', - 'DP_AUX_CONTROL_TEST_MODE_ENABLE', - 'DP_AUX_DEFINITE_ERR_REACHED_ACK', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', - 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', - 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', - 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', - 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', - 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', - 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', - 'DP_AUX_ERR_OCCURRED__NOT_ACK', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', - 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', - 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', - 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', - 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', - 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', - 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', - 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', - 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', - 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', - 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', - 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', - 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', - 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', - 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', - 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', - 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', - 'DP_AUX_SW_CONTROL_LS_READ_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', - 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', - 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', - 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', - 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', - 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', - 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', - 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', - 'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE', - 'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1', - 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', - 'DP_DPHY_8B10B_EXT_DISP_ZERO', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', - 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', - 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', - 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', - 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', - 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', - 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', - 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', - 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', - 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', - 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_LLCP', - 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', - 'DP_DPHY_SYM32_CRC_START_PS_ONLY', - 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', - 'DP_DPHY_SYM32_CRC_START_TP_START', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', - 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', - 'DP_DPHY_SYM32_CRC_USE_END_EVENT', - 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', - 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0', - 'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1', - 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', - 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', - 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', - 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', - 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_NO_UPDATE', - 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', - 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', - 'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE', - 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', - 'DP_DPHY_SYM32_STREAM_OVR_NONE', - 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', - 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', - 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', - 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', - 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', - 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422', - 'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420', - 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', - 'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL', - 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', - 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', - 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', - 'DP_LINK_TRAINING_SWITCH_TO_IDLE', - 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', - 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', - 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', - 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', - 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', - 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', - 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', - 'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED', - 'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1', - 'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED', - 'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED', - 'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3', - 'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED', - 'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED', - 'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5', - 'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED', - 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', - 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', - 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', - 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', - 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', - 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', - 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', - 'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING', - 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', - 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', - 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', - 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM', - 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', - 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', - 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', - 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', - 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', - 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', - 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', - 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', - 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', - 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', - 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', - 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', - 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', - 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', - 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', - 'DP_STREAM_ENC_NO_ERROR_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_OCCURRED', - 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', - 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', - 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', - 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', - 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', - 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', - 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', - 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', - 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', - 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', - 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', - 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', - 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', - 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', - 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', - 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', - 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', - 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', - 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', - 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', - 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', - 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', - 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', - 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', - 'DP_SYM32_ENC_PENDING', - 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', - 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', - 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', - 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', - 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', - 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', - 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', - 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', - 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', - 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', - 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', - 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', - 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', - 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE', - 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', - 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', - 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', - 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', - 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', - 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', - 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', - 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', - 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', - 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', - 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', - 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', - 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', - 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', - 'DSCCIF_BITS_PER_COMPONENT_ENUM', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', - 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', - 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', - 'DSCC_BITS_PER_COMPONENT_ENUM', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', - 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', - 'DSCC_DSC_VERSION_MAJOR_ENUM', - 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', - 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', - 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', - 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', - 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', - 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', - 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', - 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', - 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', - 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', - 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', - 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', - 'DSCL_MODE_SCALING_444_RGB_ENABLE', - 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', - 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', - 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', - 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', - 'DSM_ENABLE_ERROR_INJECT_FED_IN', - 'DSM_ENABLE_ERROR_INJECT_SINGLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', - 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', - 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', - 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', - 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', - 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', - 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', - 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', - 'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS', - 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', - 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', - 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', - 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', - 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', - 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', - 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', - 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', - 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', - 'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM', - 'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN', - 'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM', - 'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0', - 'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', - 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', - 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', - 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', - 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', - 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', - 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', - 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', - 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', - 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', - 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', - 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', - 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', - 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', - 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', - 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', - 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', - 'DWB_OGAM_LUT_READ_COLOR_SEL_B', - 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', - 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', - 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', - 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', - 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', - 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', - 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', - 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', - 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', - 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', - 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', - 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', - 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', - 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', - 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', - 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', - 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', - 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', - 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', - 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', - 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', - 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', - 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', - 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', - 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', - 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', - 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', - 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', - 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', - 'EFC_BGR101111_FLOAT', 'EFC_BGR565', - 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', - 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', - 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', - 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', - 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', - 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', - 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', - 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', - 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', - 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', - 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', - 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', - 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', - 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', - 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', - 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', - 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', - 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', - 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', - 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', - 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', - 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', - 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', - 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', - 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', - 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', - 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', - 'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT', - 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', - 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', - 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', - 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', - 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', - 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', - 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', - 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', - 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', - 'ENUM_DPG_FIELD_POLARITY', - 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', - 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', - 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', - 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', - 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', - 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', - 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', - 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', - 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', - 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', - 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE', - 'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES', - 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', - 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', - 'ENUM_DP_DPHY_SYM32_STATUS', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', - 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', - 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', - 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', - 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', - 'ENUM_DP_SYM32_ENC_CRC_VALID', - 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', - 'ENUM_DP_SYM32_ENC_ENABLE', - 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', - 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', - 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', - 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', - 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', - 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', - 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', - 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', - 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', - 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', - 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE', - 'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU', - 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY', - 'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE', - 'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO', - 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC', - 'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', - 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'F32_MES_PM4_PACKETS_H', - 'FAULT_FAIL', 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', - 'FC_EYE_SELECTION_ENUM', 'FC_EYE_SELECTION_LEFT_EYE', - 'FC_EYE_SELECTION_RIGHT_EYE', 'FC_EYE_SELECTION_STEREO_DIS', - 'FC_FRAME_CAPTURE_RATE_ENUM', 'FC_FRAME_CAPTURE_RATE_FULL', - 'FC_FRAME_CAPTURE_RATE_HALF', 'FC_FRAME_CAPTURE_RATE_QUARTER', - 'FC_FRAME_CAPTURE_RATE_THIRD', 'FC_STEREO_EYE_POLARITY_ENUM', - 'FC_STEREO_EYE_POLARITY_LEFT', 'FC_STEREO_EYE_POLARITY_RIGHT', - 'FEC_ACTIVE_STATUS', 'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME', - 'FLIP_LEFT_EYE', 'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1', - 'FLIP_RATE_2', 'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5', - 'FLIP_RATE_6', 'FLIP_RATE_7', 'FLIP_RIGHT_EYE', - 'FLUSH_AND_INV_CB_DATA_TS', 'FLUSH_AND_INV_CB_META', - 'FLUSH_AND_INV_CB_PIXEL_DATA', 'FLUSH_AND_INV_DB_DATA_TS', - 'FLUSH_AND_INV_DB_META', 'FLUSH_CONTROL_FLUSH_NOT_STARTED', - 'FLUSH_CONTROL_FLUSH_STARTED', 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', - 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMTMEM_DISABLE_MEM_PWR_CTRL', - 'FMTMEM_ENABLE_MEM_PWR_CTRL', 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', - 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', - 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', - 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', - 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', - 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', - 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', - 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', - 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', - 'FMT_CLAMP_CNTL_COLOR_FORMAT', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', - 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', - 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', - 'FMT_CONTROL_PIXEL_ENCODING', - 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', - 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', - 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', - 'FMT_CONTROL_SUBSAMPLING_MODE', - 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', - 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', - 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', - 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', - 'FMT_CONTROL_SUBSAMPLING_ORDER', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', - 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', - 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', - 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', - 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', - 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', - 'FMT_FRAME_RANDOM_ENABLE_CONTROL', - 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', - 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', - 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', - 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', - 'FMT_RGB_RANDOM_ENABLE_CONTROL', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', - 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', - 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', - 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', - 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', - 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', - 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', - 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', - 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', - 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', - 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', - 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', - 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', - 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', - 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', - 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', - 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', - 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', - 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', - 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', - 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', - 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', - 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', - 'FRAME_TMZ', 'FUSE_BASE', 'FUSE_BASE__INST0_SEG0', - 'FUSE_BASE__INST0_SEG1', 'FUSE_BASE__INST0_SEG2', - 'FUSE_BASE__INST0_SEG3', 'FUSE_BASE__INST0_SEG4', - 'FUSE_BASE__INST1_SEG0', 'FUSE_BASE__INST1_SEG1', - 'FUSE_BASE__INST1_SEG2', 'FUSE_BASE__INST1_SEG3', - 'FUSE_BASE__INST1_SEG4', 'FUSE_BASE__INST2_SEG0', - 'FUSE_BASE__INST2_SEG1', 'FUSE_BASE__INST2_SEG2', - 'FUSE_BASE__INST2_SEG3', 'FUSE_BASE__INST2_SEG4', - 'FUSE_BASE__INST3_SEG0', 'FUSE_BASE__INST3_SEG1', - 'FUSE_BASE__INST3_SEG2', 'FUSE_BASE__INST3_SEG3', - 'FUSE_BASE__INST3_SEG4', 'FUSE_BASE__INST4_SEG0', - 'FUSE_BASE__INST4_SEG1', 'FUSE_BASE__INST4_SEG2', - 'FUSE_BASE__INST4_SEG3', 'FUSE_BASE__INST4_SEG4', - 'FUSE_BASE__INST5_SEG0', 'FUSE_BASE__INST5_SEG1', - 'FUSE_BASE__INST5_SEG2', 'FUSE_BASE__INST5_SEG3', - 'FUSE_BASE__INST5_SEG4', 'FUSE_BASE__INST6_SEG0', - 'FUSE_BASE__INST6_SEG1', 'FUSE_BASE__INST6_SEG2', - 'FUSE_BASE__INST6_SEG3', 'FUSE_BASE__INST6_SEG4', 'ForceControl', - 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', - 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', - 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', - 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', - 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', - 'GB_TILING_CONFIG_TABLE_SIZE', 'GCRPerfSel', - 'GCR_PERF_SEL_ALL_REQ', - 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', - 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', - 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', - 'GCR_PERF_SEL_CPC_TCP_REQ', - 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', - 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', - 'GCR_PERF_SEL_CPF_TCP_REQ', - 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', - 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', - 'GCR_PERF_SEL_CPG_TCP_REQ', - 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', - 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', - 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', - 'GCR_PERF_SEL_PIO_TCP_REQ', - 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', - 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', - 'GCR_PERF_SEL_PM_TCP_REQ', - 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', - 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', - 'GCR_PERF_SEL_RLC_TCP_REQ', - 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA0_METADATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', - 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', - 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', - 'GCR_PERF_SEL_SDMA1_METADATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', - 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', - 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', - 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_FILTERED_RET', - 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', - 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', - 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', - 'GCR_PERF_SEL_VIRT_REQ', 'GC_BASE', 'GC_BASE__INST0_SEG0', - 'GC_BASE__INST0_SEG1', 'GC_BASE__INST0_SEG2', - 'GC_BASE__INST0_SEG3', 'GC_BASE__INST0_SEG4', - 'GC_BASE__INST1_SEG0', 'GC_BASE__INST1_SEG1', - 'GC_BASE__INST1_SEG2', 'GC_BASE__INST1_SEG3', - 'GC_BASE__INST1_SEG4', 'GC_BASE__INST2_SEG0', - 'GC_BASE__INST2_SEG1', 'GC_BASE__INST2_SEG2', - 'GC_BASE__INST2_SEG3', 'GC_BASE__INST2_SEG4', - 'GC_BASE__INST3_SEG0', 'GC_BASE__INST3_SEG1', - 'GC_BASE__INST3_SEG2', 'GC_BASE__INST3_SEG3', - 'GC_BASE__INST3_SEG4', 'GC_BASE__INST4_SEG0', - 'GC_BASE__INST4_SEG1', 'GC_BASE__INST4_SEG2', - 'GC_BASE__INST4_SEG3', 'GC_BASE__INST4_SEG4', - 'GC_BASE__INST5_SEG0', 'GC_BASE__INST5_SEG1', - 'GC_BASE__INST5_SEG2', 'GC_BASE__INST5_SEG3', - 'GC_BASE__INST5_SEG4', 'GC_BASE__INST6_SEG0', - 'GC_BASE__INST6_SEG1', 'GC_BASE__INST6_SEG2', - 'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4', - 'GDS_PERFCOUNT_SELECT', 'GDS_PERF_SEL_GWS_BYPASS', - 'GDS_PERF_SEL_GWS_RELEASED', 'GDS_PERF_SEL_SE0_2COMP_REQ', - 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', - 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE0_GDS_RD_OP', - 'GDS_PERF_SEL_SE0_GDS_REL_OP', 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP', - 'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT', - 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET', - 'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP', - 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP', - 'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT', - 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET', - 'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP', - 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP', - 'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT', - 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET', - 'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP', - 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP', - 'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT', - 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET', - 'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP', - 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP', - 'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT', - 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET', - 'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP', - 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP', - 'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT', - 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET', - 'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP', - 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP', - 'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT', - 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET', - 'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', - 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', - 'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP', - 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', - 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP', - 'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT', - 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET', - 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', - 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', - 'GE2_SE_PERFCOUNT_SELECT', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', - 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', - 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', - 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', - 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', - 'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO', - 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', - 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', - 'GL0V_CACHE_POLICY_MISS_LRU', 'GL1A_PERF_SEL', - 'GL1A_PERF_SEL_ARB_REQUESTS', 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', - 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', - 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', - 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', - 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', - 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', - 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', - 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', - 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', - 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', - 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', - 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', - 'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B', - 'GL1C_PERF_SEL_GL2_REQ_READ_32B', - 'GL1C_PERF_SEL_GL2_REQ_READ_64B', - 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', - 'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', - 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', - 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', - 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', - 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', - 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', - 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', - 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', - 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', - 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', - 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', - 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', - 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', - 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', - 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', - 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', - 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', - 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS', - 'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0', - 'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B', - 'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B', - 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', - 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', - 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', - 'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE', - 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', - 'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1', - 'GL1C_PERF_SEL_STALL_LFIFO_FULL', - 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', - 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', - 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', - 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', - 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', - 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', - 'GL1C_PERF_SEL_UTCL0_REQUEST', - 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', - 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', - 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', - 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', - 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', - 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', - 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', - 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', - 'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', - 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', - 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY', - 'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', - 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', - 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', - 'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1', - 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', - 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES', - 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', - 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', - 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', - 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', - 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', - 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', - 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', - 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', - 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', - 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', - 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', - 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', - 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', - 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', - 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', - 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', - 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', - 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', - 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', - 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', - 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', - 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', - 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', - 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', - 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', - 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', - 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', - 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', - 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', - 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', - 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', - 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', - 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', - 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', - 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', - 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', - 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', - 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', - 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', - 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', - 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', - 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', - 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', - 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', - 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', - 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', - 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', - 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', - 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', - 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', - 'GL2C_PERF_SEL_CM_COMP_READ_REQ', - 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', - 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', - 'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', - 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', - 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', - 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', - 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', - 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', - 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', - 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', - 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', - 'GL2C_PERF_SEL_CM_WR_ACK_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', - 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', - 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', - 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', - 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', - 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', - 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', - 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', - 'GL2C_PERF_SEL_EA_RDRET_NACK', - 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', - 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', - 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', - 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', - 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', - 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', - 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', - 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', - 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', - 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', - 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', - 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', - 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', - 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', - 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', - 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', - 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', - 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', - 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', - 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', - 'GL2C_PERF_SEL_GCR_WBINVL2_START', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', - 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', - 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', - 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', - 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', - 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', - 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', - 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', - 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', - 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', - 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', - 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', - 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', - 'GL2C_PERF_SEL_MDC_SECTOR_MISS', - 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_MDC_TAG_HIT', - 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', - 'GL2C_PERF_SEL_MDC_TAG_STALL', - 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', - 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', - 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', - 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', - 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', - 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', - 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', - 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', - 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', - 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', - 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', - 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', - 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', - 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', - 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', - 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', - 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', - 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', - 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', - 'GL2C_PERF_SEL_TAG_PROBE_STALL', - 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', - 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', - 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', - 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', - 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', - 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', - 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', - 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', - 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', - 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', - 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', - 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES', - 'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', - 'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2', - 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS', - 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', - 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', - 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', - 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', - 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', - 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', - 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', - 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', - 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', - 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', - 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', - 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', - 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', - 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', - 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', - 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', - 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', - 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', - 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', - 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', - 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', - 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', - 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', - 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', - 'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32', - 'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32', - 'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8', - 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', - 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', - 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', - 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', - 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', - 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', - 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', - 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', - 'GLOBAL_STATUS_FLUSH_STATUS', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', - 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', - 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', - 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', - 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', - 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', - 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', - 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', - 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', - 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', - 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', - 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', - 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', - 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', - 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', - 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', - 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', - 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', - 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY', - 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', - 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', - 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY', - 'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY', - 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', - 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', - 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', - 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', - 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', - 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', - 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', - 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', - 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', - 'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY', - 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', - 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', - 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', - 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', - 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', - 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', - 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', - 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY', - 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY', - 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', - 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', - 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY', - 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', - 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', - 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', - 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', - 'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY', - 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', - 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', - 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', - 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', - 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', - 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', - 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', - 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY', - 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY', - 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', - 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', - 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY', - 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY', - 'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN', - 'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY', - 'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY', - 'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY', - 'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY', - 'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY', - 'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED', - 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL', - 'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY', - 'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT', - 'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN', - 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY', - 'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY', - 'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY', - 'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY', - 'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY', - 'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', - 'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY', - 'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN', - 'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY', - 'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', - 'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY', - 'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY', - 'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY', - 'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY', - 'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED', - 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL', - 'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY', - 'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT', - 'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN', - 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY', - 'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY', - 'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY', - 'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY', - 'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY', - 'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', - 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', - 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', - 'GS_STAGE_ON', 'HDA_BASE', 'HDA_BASE__INST0_SEG0', - 'HDA_BASE__INST0_SEG1', 'HDA_BASE__INST0_SEG2', - 'HDA_BASE__INST0_SEG3', 'HDA_BASE__INST0_SEG4', - 'HDA_BASE__INST1_SEG0', 'HDA_BASE__INST1_SEG1', - 'HDA_BASE__INST1_SEG2', 'HDA_BASE__INST1_SEG3', - 'HDA_BASE__INST1_SEG4', 'HDA_BASE__INST2_SEG0', - 'HDA_BASE__INST2_SEG1', 'HDA_BASE__INST2_SEG2', - 'HDA_BASE__INST2_SEG3', 'HDA_BASE__INST2_SEG4', - 'HDA_BASE__INST3_SEG0', 'HDA_BASE__INST3_SEG1', - 'HDA_BASE__INST3_SEG2', 'HDA_BASE__INST3_SEG3', - 'HDA_BASE__INST3_SEG4', 'HDA_BASE__INST4_SEG0', - 'HDA_BASE__INST4_SEG1', 'HDA_BASE__INST4_SEG2', - 'HDA_BASE__INST4_SEG3', 'HDA_BASE__INST4_SEG4', - 'HDA_BASE__INST5_SEG0', 'HDA_BASE__INST5_SEG1', - 'HDA_BASE__INST5_SEG2', 'HDA_BASE__INST5_SEG3', - 'HDA_BASE__INST5_SEG4', 'HDA_BASE__INST6_SEG0', - 'HDA_BASE__INST6_SEG1', 'HDA_BASE__INST6_SEG2', - 'HDA_BASE__INST6_SEG3', 'HDA_BASE__INST6_SEG4', - 'HDMICHARCLK_SRC_SEL', 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', - 'HDMICHARCLK_SRC_SEL_UNIPHYA', 'HDMICHARCLK_SRC_SEL_UNIPHYB', - 'HDMICHARCLK_SRC_SEL_UNIPHYC', 'HDMICHARCLK_SRC_SEL_UNIPHYD', - 'HDMICHARCLK_SRC_SEL_UNIPHYE', 'HDMISTREAMCLK_DTO_FORCE_DIS', - 'HDMISTREAMCLK_SRC_SEL', 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', - 'HDMI_ACP_SEND', 'HDMI_ACR_0_MULTIPLE_RESERVED', - 'HDMI_ACR_1_MULTIPLE', 'HDMI_ACR_2_MULTIPLE', - 'HDMI_ACR_3_MULTIPLE_RESERVED', 'HDMI_ACR_4_MULTIPLE', - 'HDMI_ACR_5_MULTIPLE_RESERVED', 'HDMI_ACR_6_MULTIPLE_RESERVED', - 'HDMI_ACR_7_MULTIPLE_RESERVED', 'HDMI_ACR_AUDIO_PRIORITY', - 'HDMI_ACR_CONT', 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', - 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', - 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', - 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', - 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', - 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', - 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', - 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', - 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', - 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', - 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', - 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', - 'HDMI_AUDIO_INFO_SEND', - 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', - 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', - 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', - 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', - 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', - 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', - 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', - 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', - 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', - 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', - 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL', - 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', - 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', - 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', - 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', - 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', - 'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE', - 'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND', - 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', - 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', - 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', - 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', - 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', - 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', - 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', - 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', - 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', - 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', - 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', - 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', - 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', - 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', - 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', - 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', - 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE', - 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE', - 'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE', - 'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE', - 'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL', - 'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET', - 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', - 'HDMI_STREAM_ENC_ODM_COMBINE_MODE', - 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', - 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', - 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT', - 'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE', - 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET', - 'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE', - 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', - 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', - 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND', - 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT', - 'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT', - 'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE', - 'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND', - 'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE', - 'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE', - 'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE', - 'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT', - 'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND', - 'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', - 'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', - 'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT', - 'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE', - 'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING', - 'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE', - 'HDMI_TMDS_OR_DP_8B10B', 'HDP_BASE', 'HDP_BASE__INST0_SEG0', - 'HDP_BASE__INST0_SEG1', 'HDP_BASE__INST0_SEG2', - 'HDP_BASE__INST0_SEG3', 'HDP_BASE__INST0_SEG4', - 'HDP_BASE__INST1_SEG0', 'HDP_BASE__INST1_SEG1', - 'HDP_BASE__INST1_SEG2', 'HDP_BASE__INST1_SEG3', - 'HDP_BASE__INST1_SEG4', 'HDP_BASE__INST2_SEG0', - 'HDP_BASE__INST2_SEG1', 'HDP_BASE__INST2_SEG2', - 'HDP_BASE__INST2_SEG3', 'HDP_BASE__INST2_SEG4', - 'HDP_BASE__INST3_SEG0', 'HDP_BASE__INST3_SEG1', - 'HDP_BASE__INST3_SEG2', 'HDP_BASE__INST3_SEG3', - 'HDP_BASE__INST3_SEG4', 'HDP_BASE__INST4_SEG0', - 'HDP_BASE__INST4_SEG1', 'HDP_BASE__INST4_SEG2', - 'HDP_BASE__INST4_SEG3', 'HDP_BASE__INST4_SEG4', - 'HDP_BASE__INST5_SEG0', 'HDP_BASE__INST5_SEG1', - 'HDP_BASE__INST5_SEG2', 'HDP_BASE__INST5_SEG3', - 'HDP_BASE__INST5_SEG4', 'HDP_BASE__INST6_SEG0', - 'HDP_BASE__INST6_SEG1', 'HDP_BASE__INST6_SEG2', - 'HDP_BASE__INST6_SEG3', 'HDP_BASE__INST6_SEG4', - 'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', - 'HDP_ENDIAN_NONE', 'HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', - 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', - 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', - 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', - 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', - 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', - 'HPO_TOP_CLOCK_GATING_EN', - 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', - 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', - 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', - 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', - 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', - 'HPO_TOP_REGISTER_GATED_DISPCLK', - 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', - 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', - 'HPO_TOP_TEST_CLOCK_RESERVED', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'HS_GS', 'HS_STAGE_OFF', - 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', - 'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', - 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', - 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', - 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', - 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', - 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', - 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', - 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', - 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', - 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', - 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', - 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', - 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', - 'IH_PERF_SEL_BIF_LINE0_FALLING', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', - 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', - 'IH_PERF_SEL_BIF_LINE0_RISING', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', - 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', - 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', - 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', - 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', - 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', - 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', - 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', - 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', - 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', - 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', - 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', - 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', - 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', - 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', - 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', - 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', - 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', - 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', - 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', - 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', - 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', - 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', - 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', - 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', - 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', - 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', - 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', - 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', - 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', - 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', - 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', - 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', - 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', - 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', - 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', - 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', - 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', - 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', - 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', - 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', - 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', - 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', - 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', - 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', - 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', - 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', - 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', - 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', - 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', - 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', - 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', - 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', - 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', - 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', - 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', - 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', - 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', - 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', - 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', - 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', - 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', - 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', - 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', - 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', - 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', - 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', - 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', - 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', - 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', - 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', - 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', - 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', - 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', - 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', - 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', - 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', - 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', - 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', - 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', - 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', - 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', - 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', - 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', - 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', - 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', - 'IH_VF_RB_SELECT_RESERVED', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', - 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', - 'INDIRECT_BUFFER_VALID', 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', - 'INPUT_FIFO_ERROR_TYPE', 'INPUT_INNER_COVERAGE', - 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', - 'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', - 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', - 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', - 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', - 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', - 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', - 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', - 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', - 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', - 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', - 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', - 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0', - 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3', - 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', - 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK', - 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', - 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', - 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', - 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', - 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', - 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', - 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', - 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', - 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', - 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', - 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', - 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', - 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', - 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', - 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', - 'LSDMA_PERF_SEL_CTX_CHANGE', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', - 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', - 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', - 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', - 'LSDMA_PERF_SEL_EX_IDLE', - 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'LSDMA_PERF_SEL_F32_L1_WR_VLD', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', - 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', - 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', - 'LSDMA_PERF_SEL_INT_REQ_STALL', - 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'LSDMA_PERF_SEL_INT_RESP_RETRY', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', - 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', - 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', - 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', - 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', - 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', - 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', - 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', - 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', - 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', - 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', - 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', - 'LSDMA_PERF_SEL_MC_WR_IDLE', - 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', - 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', - 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', - 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', - 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', - 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', - 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', - 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', - 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', - 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', - 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', - 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', - 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', - 'LSDMA_PERF_SEL_SEM_RESP_FAIL', - 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', - 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', - 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', - 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', - 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', - 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', - 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', - 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', - 'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT', - 'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', - 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', - 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', - 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', - 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', - 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', - 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', - 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', - 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', - 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', - 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', - 'MASTER_UPDATE_LOCK_SEL_RESERVED5', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', - 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', - 'MAX_INSTANCE', 'MAX_SEGMENT', 'MEM_ARB_MODE_AGE', - 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', - 'MEM_POWER_DIS_MODE_DISABLE', 'MEM_POWER_DIS_MODE_ENABLE', - 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', - 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', - 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', - 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', - 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', - 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', - 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', - 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', - 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', - 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', - 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', - 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', - 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', - 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', - 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', - 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', - 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', - 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', - 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', - 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', - 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', - 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', - 'MIN_META_CHUNK_SIZE_64B', 'MMHUB_BASE', 'MMHUB_BASE__INST0_SEG0', - 'MMHUB_BASE__INST0_SEG1', 'MMHUB_BASE__INST0_SEG2', - 'MMHUB_BASE__INST0_SEG3', 'MMHUB_BASE__INST0_SEG4', - 'MMHUB_BASE__INST1_SEG0', 'MMHUB_BASE__INST1_SEG1', - 'MMHUB_BASE__INST1_SEG2', 'MMHUB_BASE__INST1_SEG3', - 'MMHUB_BASE__INST1_SEG4', 'MMHUB_BASE__INST2_SEG0', - 'MMHUB_BASE__INST2_SEG1', 'MMHUB_BASE__INST2_SEG2', - 'MMHUB_BASE__INST2_SEG3', 'MMHUB_BASE__INST2_SEG4', - 'MMHUB_BASE__INST3_SEG0', 'MMHUB_BASE__INST3_SEG1', - 'MMHUB_BASE__INST3_SEG2', 'MMHUB_BASE__INST3_SEG3', - 'MMHUB_BASE__INST3_SEG4', 'MMHUB_BASE__INST4_SEG0', - 'MMHUB_BASE__INST4_SEG1', 'MMHUB_BASE__INST4_SEG2', - 'MMHUB_BASE__INST4_SEG3', 'MMHUB_BASE__INST4_SEG4', - 'MMHUB_BASE__INST5_SEG0', 'MMHUB_BASE__INST5_SEG1', - 'MMHUB_BASE__INST5_SEG2', 'MMHUB_BASE__INST5_SEG3', - 'MMHUB_BASE__INST5_SEG4', 'MMHUB_BASE__INST6_SEG0', - 'MMHUB_BASE__INST6_SEG1', 'MMHUB_BASE__INST6_SEG2', - 'MMHUB_BASE__INST6_SEG3', 'MMHUB_BASE__INST6_SEG4', 'MONO_10LSB', - 'MONO_10MSB', 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', - 'MONO_8', 'MP0_BASE', 'MP0_BASE__INST0_SEG0', - 'MP0_BASE__INST0_SEG1', 'MP0_BASE__INST0_SEG2', - 'MP0_BASE__INST0_SEG3', 'MP0_BASE__INST0_SEG4', - 'MP0_BASE__INST1_SEG0', 'MP0_BASE__INST1_SEG1', - 'MP0_BASE__INST1_SEG2', 'MP0_BASE__INST1_SEG3', - 'MP0_BASE__INST1_SEG4', 'MP0_BASE__INST2_SEG0', - 'MP0_BASE__INST2_SEG1', 'MP0_BASE__INST2_SEG2', - 'MP0_BASE__INST2_SEG3', 'MP0_BASE__INST2_SEG4', - 'MP0_BASE__INST3_SEG0', 'MP0_BASE__INST3_SEG1', - 'MP0_BASE__INST3_SEG2', 'MP0_BASE__INST3_SEG3', - 'MP0_BASE__INST3_SEG4', 'MP0_BASE__INST4_SEG0', - 'MP0_BASE__INST4_SEG1', 'MP0_BASE__INST4_SEG2', - 'MP0_BASE__INST4_SEG3', 'MP0_BASE__INST4_SEG4', - 'MP0_BASE__INST5_SEG0', 'MP0_BASE__INST5_SEG1', - 'MP0_BASE__INST5_SEG2', 'MP0_BASE__INST5_SEG3', - 'MP0_BASE__INST5_SEG4', 'MP0_BASE__INST6_SEG0', - 'MP0_BASE__INST6_SEG1', 'MP0_BASE__INST6_SEG2', - 'MP0_BASE__INST6_SEG3', 'MP0_BASE__INST6_SEG4', 'MP1_BASE', - 'MP1_BASE__INST0_SEG0', 'MP1_BASE__INST0_SEG1', - 'MP1_BASE__INST0_SEG2', 'MP1_BASE__INST0_SEG3', - 'MP1_BASE__INST0_SEG4', 'MP1_BASE__INST1_SEG0', - 'MP1_BASE__INST1_SEG1', 'MP1_BASE__INST1_SEG2', - 'MP1_BASE__INST1_SEG3', 'MP1_BASE__INST1_SEG4', - 'MP1_BASE__INST2_SEG0', 'MP1_BASE__INST2_SEG1', - 'MP1_BASE__INST2_SEG2', 'MP1_BASE__INST2_SEG3', - 'MP1_BASE__INST2_SEG4', 'MP1_BASE__INST3_SEG0', - 'MP1_BASE__INST3_SEG1', 'MP1_BASE__INST3_SEG2', - 'MP1_BASE__INST3_SEG3', 'MP1_BASE__INST3_SEG4', - 'MP1_BASE__INST4_SEG0', 'MP1_BASE__INST4_SEG1', - 'MP1_BASE__INST4_SEG2', 'MP1_BASE__INST4_SEG3', - 'MP1_BASE__INST4_SEG4', 'MP1_BASE__INST5_SEG0', - 'MP1_BASE__INST5_SEG1', 'MP1_BASE__INST5_SEG2', - 'MP1_BASE__INST5_SEG3', 'MP1_BASE__INST5_SEG4', - 'MP1_BASE__INST6_SEG0', 'MP1_BASE__INST6_SEG1', - 'MP1_BASE__INST6_SEG2', 'MP1_BASE__INST6_SEG3', - 'MP1_BASE__INST6_SEG4', 'MPCC_BG_COLOR_BPC', - 'MPCC_BG_COLOR_BPC_10bit', 'MPCC_BG_COLOR_BPC_11bit', - 'MPCC_BG_COLOR_BPC_12bit', 'MPCC_BG_COLOR_BPC_8bit', - 'MPCC_BG_COLOR_BPC_9bit', 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', - 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', - 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', - 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', - 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', - 'MPCC_CONTROL_MPCC_MODE_BYPASS', - 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', - 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', - 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', - 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', - 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', - 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', - 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', - 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', - 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', - 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', - 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', - 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', - 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', - 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', - 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS', - 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', - 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', - 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', - 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', - 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', - 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', - 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', - 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', - 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', - 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', - 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', - 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', - 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', - 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', - 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', - 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', - 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', - 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', - 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', - 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', - 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', - 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', - 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', - 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', - 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', - 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', - 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', - 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', - 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', - 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', - 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', - 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', - 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', - 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', - 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', - 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', - 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', - 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', - 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', - 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', - 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', - 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', - 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', - 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', - 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', - 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', - 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', - 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', - 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', - 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', - 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', - 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', - 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', - 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', - 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', - 'MPC_DEBUG_BUS1_DATA_SELECT', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', - 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', - 'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', - 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', - 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', - 'MPC_DEBUG_BUS2_DATA_SELECT_RES', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', - 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', - 'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1', - 'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3', - 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT', - 'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', - 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', - 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', - 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', - 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', - 'MPC_OUT_RATE_CONTROL_DISABLE_SET', - 'MPC_OUT_RATE_CONTROL_SET_DISABLE', - 'MPC_OUT_RATE_CONTROL_SET_ENABLE', - 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', - 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', - 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', - 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', - 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', - 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', - 'MemArbMode', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0', - 'NBIO_BASE__INST0_SEG1', 'NBIO_BASE__INST0_SEG2', - 'NBIO_BASE__INST0_SEG3', 'NBIO_BASE__INST0_SEG4', - 'NBIO_BASE__INST1_SEG0', 'NBIO_BASE__INST1_SEG1', - 'NBIO_BASE__INST1_SEG2', 'NBIO_BASE__INST1_SEG3', - 'NBIO_BASE__INST1_SEG4', 'NBIO_BASE__INST2_SEG0', - 'NBIO_BASE__INST2_SEG1', 'NBIO_BASE__INST2_SEG2', - 'NBIO_BASE__INST2_SEG3', 'NBIO_BASE__INST2_SEG4', - 'NBIO_BASE__INST3_SEG0', 'NBIO_BASE__INST3_SEG1', - 'NBIO_BASE__INST3_SEG2', 'NBIO_BASE__INST3_SEG3', - 'NBIO_BASE__INST3_SEG4', 'NBIO_BASE__INST4_SEG0', - 'NBIO_BASE__INST4_SEG1', 'NBIO_BASE__INST4_SEG2', - 'NBIO_BASE__INST4_SEG3', 'NBIO_BASE__INST4_SEG4', - 'NBIO_BASE__INST5_SEG0', 'NBIO_BASE__INST5_SEG1', - 'NBIO_BASE__INST5_SEG2', 'NBIO_BASE__INST5_SEG3', - 'NBIO_BASE__INST5_SEG4', 'NBIO_BASE__INST6_SEG0', - 'NBIO_BASE__INST6_SEG1', 'NBIO_BASE__INST6_SEG2', - 'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NON_BYPASS', - 'NOT_FORCE_THE_CLOCK_DISABLED', 'NOT_SENT', 'NO_DIST', 'NO_DIV', - 'NO_FORCE', 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', - 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', - 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'NVD_H', - 'OBUF_BYPASS_DIS', 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', - 'OBUF_FULL', 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', - 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', - 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', - 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', - 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', - 'OPPBUF_DISPLAY_SEGMENTATION', - 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', - 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', - 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL', - 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL', - 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL', - 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL', - 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE', - 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', - 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', - 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', - 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', - 'OPP_PIPE_CRC_INTERLACE_MODE', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', - 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', - 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', - 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', - 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', - 'OPP_PIPE_CRC_PIXEL_SELECT', - 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', - 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', - 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', - 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', - 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', - 'OPP_PIPE_CRC_STEREO_MODE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', - 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', - 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', - 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', - 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', - 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', - 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', - 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', - 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', - 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', - 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', - 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', - 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', - 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', - 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', - 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', - 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', 'OSSSYS_BASE', - 'OSSSYS_BASE__INST0_SEG0', 'OSSSYS_BASE__INST0_SEG1', - 'OSSSYS_BASE__INST0_SEG2', 'OSSSYS_BASE__INST0_SEG3', - 'OSSSYS_BASE__INST0_SEG4', 'OSSSYS_BASE__INST1_SEG0', - 'OSSSYS_BASE__INST1_SEG1', 'OSSSYS_BASE__INST1_SEG2', - 'OSSSYS_BASE__INST1_SEG3', 'OSSSYS_BASE__INST1_SEG4', - 'OSSSYS_BASE__INST2_SEG0', 'OSSSYS_BASE__INST2_SEG1', - 'OSSSYS_BASE__INST2_SEG2', 'OSSSYS_BASE__INST2_SEG3', - 'OSSSYS_BASE__INST2_SEG4', 'OSSSYS_BASE__INST3_SEG0', - 'OSSSYS_BASE__INST3_SEG1', 'OSSSYS_BASE__INST3_SEG2', - 'OSSSYS_BASE__INST3_SEG3', 'OSSSYS_BASE__INST3_SEG4', - 'OSSSYS_BASE__INST4_SEG0', 'OSSSYS_BASE__INST4_SEG1', - 'OSSSYS_BASE__INST4_SEG2', 'OSSSYS_BASE__INST4_SEG3', - 'OSSSYS_BASE__INST4_SEG4', 'OSSSYS_BASE__INST5_SEG0', - 'OSSSYS_BASE__INST5_SEG1', 'OSSSYS_BASE__INST5_SEG2', - 'OSSSYS_BASE__INST5_SEG3', 'OSSSYS_BASE__INST5_SEG4', - 'OSSSYS_BASE__INST6_SEG0', 'OSSSYS_BASE__INST6_SEG1', - 'OSSSYS_BASE__INST6_SEG2', 'OSSSYS_BASE__INST6_SEG3', - 'OSSSYS_BASE__INST6_SEG4', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', - 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', - 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', - 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', - 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', - 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', - 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', - 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', - 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', - 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', - 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', - 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', - 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', - 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', - 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', - 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', - 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', - 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', - 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', - 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', - 'OTG_DIG_UPDATE_VCOUNT_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', - 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', - 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', - 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', - 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', - 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', - 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', - 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', - 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', - 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', - 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', - 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', - 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', - 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', - 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', - 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', - 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', - 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', - 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', - 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', - 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', - 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', - 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', - 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', - 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', - 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', - 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', - 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', - 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', - 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', - 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', - 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', - 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', - 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', - 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', - 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', - 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', - 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', - 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', - 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', - 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', - 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', - 'OTG_TRIGA_FREQUENCY_SELECT_3', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', - 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', - 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', - 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', - 'OTG_TRIGB_FREQUENCY_SELECT_3', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', - 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', - 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', - 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', - 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', - 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', - 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', - 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', - 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', - 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', - 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', - 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', - 'OTG_V_SYNC_MODE_HSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', - 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', - 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', - 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', - 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', - 'OUTPUT_LINE', 'OUTPUT_POINT', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', - 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', - 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', - 'OVERRUN', 'OreoMode', 'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT', - 'PACKET3_ACQUIRE_MEM', 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', - 'PACKET3_AQL_PACKET', 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', - 'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE', - 'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER', - 'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA', - 'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA', - 'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW', - 'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE', - 'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT', - 'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC', - 'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT', - 'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS', - 'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST', - 'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT', - 'PACKET3_DRAW_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE', - 'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS', - 'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL', - 'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS', - 'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK', - 'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER', - 'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE', - 'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE', - 'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE', - 'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST', - 'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END', - 'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV', - 'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG', - 'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG', - 'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG', - 'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM', - 'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE', - 'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', - 'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE', - 'PACKET3_RELEASE_MEM_GCR_GL1_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD', - 'PACKET3_RELEASE_MEM_GCR_GL2_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_RANGE', - 'PACKET3_RELEASE_MEM_GCR_GL2_US', - 'PACKET3_RELEASE_MEM_GCR_GL2_WB', - 'PACKET3_RELEASE_MEM_GCR_GLM_INV', - 'PACKET3_RELEASE_MEM_GCR_GLM_WB', - 'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ', - 'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ', - 'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL', - 'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT', - 'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE', - 'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END', - 'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG', - 'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE', - 'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM', - 'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG', - 'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI', - 'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START', - 'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER', - 'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER', - 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM', - 'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1', - 'PACKET_TYPE2', 'PACKET_TYPE3', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', - 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PCIE0_BASE', - 'PCIE0_BASE__INST0_SEG0', 'PCIE0_BASE__INST0_SEG1', - 'PCIE0_BASE__INST0_SEG2', 'PCIE0_BASE__INST0_SEG3', - 'PCIE0_BASE__INST0_SEG4', 'PCIE0_BASE__INST1_SEG0', - 'PCIE0_BASE__INST1_SEG1', 'PCIE0_BASE__INST1_SEG2', - 'PCIE0_BASE__INST1_SEG3', 'PCIE0_BASE__INST1_SEG4', - 'PCIE0_BASE__INST2_SEG0', 'PCIE0_BASE__INST2_SEG1', - 'PCIE0_BASE__INST2_SEG2', 'PCIE0_BASE__INST2_SEG3', - 'PCIE0_BASE__INST2_SEG4', 'PCIE0_BASE__INST3_SEG0', - 'PCIE0_BASE__INST3_SEG1', 'PCIE0_BASE__INST3_SEG2', - 'PCIE0_BASE__INST3_SEG3', 'PCIE0_BASE__INST3_SEG4', - 'PCIE0_BASE__INST4_SEG0', 'PCIE0_BASE__INST4_SEG1', - 'PCIE0_BASE__INST4_SEG2', 'PCIE0_BASE__INST4_SEG3', - 'PCIE0_BASE__INST4_SEG4', 'PCIE0_BASE__INST5_SEG0', - 'PCIE0_BASE__INST5_SEG1', 'PCIE0_BASE__INST5_SEG2', - 'PCIE0_BASE__INST5_SEG3', 'PCIE0_BASE__INST5_SEG4', - 'PCIE0_BASE__INST6_SEG0', 'PCIE0_BASE__INST6_SEG1', - 'PCIE0_BASE__INST6_SEG2', 'PCIE0_BASE__INST6_SEG3', - 'PCIE0_BASE__INST6_SEG4', 'PERFCOUNTER_ACTIVE', - 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', - 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', - 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', - 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', - 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', - 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', - 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', - 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', - 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', - 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', - 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', - 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', - 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', - 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', - 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', - 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', - 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', - 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', - 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', - 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', - 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', - 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', - 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', - 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', - 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', - 'PERFCOUNTER_CNTOFF_START_DISABLE', - 'PERFCOUNTER_CNTOFF_START_ENABLE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', - 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', - 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', - 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', - 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', - 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', - 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', - 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', - 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', - 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', - 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', - 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', - 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', - 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', - 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', - 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', - 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', - 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', - 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', - 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', - 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', - 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', - 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', - 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', - 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', - 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', - 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', - 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', - 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', - 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', - 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', - 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', - 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', - 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', - 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', - 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', - 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', - 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', - 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', - 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', - 'PERFMON_COUNTER_MODE_ACCUM', - 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', - 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', - 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', - 'PERFMON_COUNTER_MODE_DIRTY', - 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', - 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', - 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', - 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', - 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', - 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', - 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', - 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', - 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', - 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', - 'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00', - 'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02', - 'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04', - 'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06', - 'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08', - 'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10', - 'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12', - 'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14', - 'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', - 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', - 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', - 'PERF_ENGG_CSB_MACHINE_IS_STARVED', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', - 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', - 'PERF_ENGG_CSB_NULL_SUBGROUP', - 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00', - 'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02', - 'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04', - 'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06', - 'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08', - 'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10', - 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', - 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', - 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', - 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', - 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', - 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', - 'PERF_ENGG_INDEX_REQ_STARVED', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', - 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', - 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', - 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', - 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', - 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', - 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', - 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', - 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', - 'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY', - 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', - 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', - 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', - 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', - 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', - 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', - 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', - 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', - 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', - 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', - 'PERF_PAPC_CLPRIM_STARVED_CCGSM', - 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', - 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', - 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', - 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', - 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', - 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', - 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', - 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', - 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', - 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', - 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', - 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', - 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', - 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', - 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', - 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', - 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', - 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', - 'PERF_PAPC_PASX_REC_STALLED', - 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', - 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', - 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', - 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', - 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', - 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', - 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', - 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', - 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', - 'PERF_PAPC_PASX_VTX_NAN_DISCARD', - 'PERF_PAPC_PA_INPUT_END_OF_PACKET', - 'PERF_PAPC_PA_INPUT_EVENT_FLAG', - 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', - 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', - 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', - 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', - 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', - 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', - 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', - 'PERF_PAPC_SU_INPUT_PRIM_DUAL', - 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', - 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', - 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', - 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', - 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', - 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', - 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', - 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', - 'PERF_PAPC_SU_POLYMODE_BACK_CULL', - 'PERF_PAPC_SU_POLYMODE_FACE_CULL', - 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', - 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', - 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE01_STALLED_SC', - 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE0_STALLED_SC', - 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', - 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE1_STALLED_SC', - 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE2_STALLED_SC', - 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', - 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', - 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', - 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', - 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', - 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', - 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', - 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', - 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN', - 'PERF_PA_PIPE1_SWITCHED_GEN', - 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', - 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', - 'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', - 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', - 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', - 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', - 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', - 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', - 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', - 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', - 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', - 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', - 'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN', - 'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE', - 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', - 'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK', - 'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5', - 'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16', - 'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24', - 'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1', - 'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT', - 'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL', - 'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1', - 'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3', - 'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1', - 'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3', - 'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1', - 'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3', - 'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1', - 'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3', - 'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1', - 'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3', - 'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1', - 'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3', - 'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1', - 'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3', - 'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1', - 'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3', - 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_BUSY', - 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE', - 'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', - 'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE', - 'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', - 'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE', - 'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', - 'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE', - 'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', - 'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE', - 'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', - 'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE', - 'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', - 'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE', - 'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', - 'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE', - 'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', - 'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE', - 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC1_ARB_BUSY', - 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE', - 'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', - 'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE', - 'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', - 'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE', - 'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', - 'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE', - 'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', - 'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE', - 'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', - 'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE', - 'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', - 'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE', - 'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', - 'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE', - 'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', - 'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE', - 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC2_ARB_BUSY', - 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE', - 'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', - 'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE', - 'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', - 'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE', - 'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', - 'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE', - 'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', - 'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE', - 'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', - 'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE', - 'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', - 'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE', - 'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', - 'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE', - 'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', - 'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE', - 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC3_ARB_BUSY', - 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE', - 'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', - 'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE', - 'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', - 'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE', - 'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', - 'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE', - 'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', - 'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE', - 'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', - 'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE', - 'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', - 'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE', - 'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', - 'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE', - 'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', - 'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE', - 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC4_ARB_BUSY', - 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE', - 'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', - 'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE', - 'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', - 'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE', - 'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', - 'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE', - 'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', - 'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE', - 'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', - 'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE', - 'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', - 'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE', - 'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', - 'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE', - 'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', - 'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE', - 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC5_ARB_BUSY', - 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE', - 'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', - 'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE', - 'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', - 'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE', - 'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', - 'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE', - 'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', - 'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE', - 'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', - 'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE', - 'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', - 'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE', - 'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', - 'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE', - 'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', - 'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE', - 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC6_ARB_BUSY', - 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE', - 'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', - 'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE', - 'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', - 'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE', - 'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', - 'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE', - 'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', - 'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE', - 'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', - 'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE', - 'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', - 'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE', - 'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', - 'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE', - 'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', - 'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE', - 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', - 'PH_PERF_SEL_SC7_ARB_BUSY', - 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', - 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', - 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', - 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', - 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', - 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', - 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', - 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', - 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', - 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE', - 'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', - 'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE', - 'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', - 'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE', - 'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', - 'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE', - 'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', - 'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE', - 'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', - 'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE', - 'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', - 'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE', - 'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', - 'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', - 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', - 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', - 'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE', - 'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', - 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', - 'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE', - 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', - 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', - 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', - 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', - 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', - 'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1', - 'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE', - 'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE', - 'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE', - 'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT', - 'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', - 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', - 'PIPE_PIXEL_RATE_PLL_SOURCE', - 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', - 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', - 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', - 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', - 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', - 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', - 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', - 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', - 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', - 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', - 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', - 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', - 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', - 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', - 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM4_MEC_RELEASE_MEM_DEFINED', - 'PM4_MEC_WRITE_DATA_DEFINED', 'PM4_MES_HEADER_DEFINED', - 'PM_ASSERT_RESET', 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', - 'POINTLIST', 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', - 'POWER_STATE_ENUM_LS', 'POWER_STATE_ENUM_ON', - 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', 'PRE_CSC_MODE_ENUM', - 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', 'PRE_DEGAM_BT2020', - 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', 'PRE_DEGAM_BYPASS', - 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', 'PRE_DEGAM_GAMMA_24', - 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', 'PRE_DEGAM_SELECT', - 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', 'PRQ_MRQ_FLUSH_URGENT', - 'PRQ_MRQ_FLUSH_URGENT_DISABLE', 'PRQ_MRQ_FLUSH_URGENT_ENABLE', - 'PS', 'PSLC_ASAP', 'PSLC_AUTO', 'PSLC_COUNTDOWN', - 'PSLC_ON_HANG_ONLY', 'PS_DONE', 'PS_PARTIAL_FLUSH', - 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', 'PTE_BUFFER_MODE_1', - 'PTE_ROW_HEIGHT_LINEAR', 'PTE_ROW_HEIGHT_LINEAR_1024L', - 'PTE_ROW_HEIGHT_LINEAR_128L', 'PTE_ROW_HEIGHT_LINEAR_16L', - 'PTE_ROW_HEIGHT_LINEAR_256L', 'PTE_ROW_HEIGHT_LINEAR_32L', - 'PTE_ROW_HEIGHT_LINEAR_512L', 'PTE_ROW_HEIGHT_LINEAR_64L', - 'PTE_ROW_HEIGHT_LINEAR_8L', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', - 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', - 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', - 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', - 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', - 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', - 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', - 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', - 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', - 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', - 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', - 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', - 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', - 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', - 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', - 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', - 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', - 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', - 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', - 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', - 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', - 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', - 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', - 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', - 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', - 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', - 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', - 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', - 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', - 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', - 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', - 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', - 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', - 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', - 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', - 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', - 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', - 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', - 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', - 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', - 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', - 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', - 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', - 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', - 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', - 'RASTER_CONFIG_SE_PAIR_MAP_3', - 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', - 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', - 'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE', - 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', - 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', - 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', - 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN', - 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET', - 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', - 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', - 'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', - 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', - 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', - 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', - 'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', - 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY', - 'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY', - 'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY', - 'RDPCSPIPE_FIFO_NOT_FULL', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK', - 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', - 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', - 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', - 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', - 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', - 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', - 'RDPCSPIPE_MEM_PWR_NO_FORCE', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', - 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', - 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', - 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', - 'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', - 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', - 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', - 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', - 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', - 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', - 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', - 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', - 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', - 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', - 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', - 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', - 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', - 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', - 'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', - 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', - 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', - 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', - 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', - 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', - 'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE', - 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', - 'RDPCSPIPE_PHY_REF_ALT_CLK_EN', - 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0', - 'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2', - 'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4', - 'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6', - 'RDPCSPIPE_PHY_REF_RANGE_7', - 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', - 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', - 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', - 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', - 'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE', - 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', - 'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS', - 'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', - 'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE', - 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', - 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', - 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', - 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL', - 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_NONE', - 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', - 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', - 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', - 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', - 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', - 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF', - 'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE', - 'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE', - 'RDPCS_PIPE_CLK_GATE_ENABLE', - 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB', - 'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE', - 'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE', - 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', - 'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE', - 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', - 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ', - 'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF', - 'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ', - 'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ', - 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', - 'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11', - 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23', - 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34', - 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46', - 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58', - 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', - 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74', - 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85', - 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89', - 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES', - 'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS', - 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z', - 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', - 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', - 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', - 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', - 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', - 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', - 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', - 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', - 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', - 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', - 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', - 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', - 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', - 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', - 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', - 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', - 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', - 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', - 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', - 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', - 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE', - 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', - 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', - 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', - 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', - 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', - 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', - 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', - 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', - 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', - 'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09', - 'RingCounterControl', 'SAMPLE_PIPELINESTAT', - 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', - 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', - 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST', - 'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', - 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', - 'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND', - 'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON', - 'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER', - 'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER', - 'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL', - 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE', - 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SC_BACKEND_BUSY', - 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', - 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', - 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', - 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', - 'SC_BM_MULTI_ACCUM_1_BE_STALLED', - 'SC_BM_MULTI_ACCUM_2_BE_STALLED', - 'SC_BM_MULTI_ACCUM_3_BE_STALLED', - 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', - 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY', - 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE', - 'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB', - 'SC_DB0_TILE_INTERFACE_BUSY', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', - 'SC_DB0_TILE_INTERFACE_SEND_SOP', - 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_DB0_TILE_MASK_FIFO_FULL', - 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', - 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', - 'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND', - 'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', - 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', - 'SC_DB1_TILE_INTERFACE_SEND_SOP', - 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', - 'SC_DB1_TILE_MASK_FIFO_FULL', - 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', - 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', - 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', - 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', - 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', - 'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', - 'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY', - 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', - 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', - 'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY', - 'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY', - 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', - 'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', - 'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE', - 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', - 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', - 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', - 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', - 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', - 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', - 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', - 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', - 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', - 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', - 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', - 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', - 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', - 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', - 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', - 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', - 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', - 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', - 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', - 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', - 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', - 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', - 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', - 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', - 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', - 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', - 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', - 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', - 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', - 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', - 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', - 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', - 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', - 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', - 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', - 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', - 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', - 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', - 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', - 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', - 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', - 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', - 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', - 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', - 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', - 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', - 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', - 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', - 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', - 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', - 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', - 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', - 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', - 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', - 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', - 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', - 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', - 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', - 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', - 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', - 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', - 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', - 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', - 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', - 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', - 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', - 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', - 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', - 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', - 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', - 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', - 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', - 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', - 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', - 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', - 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', - 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', - 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', - 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', - 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', - 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', - 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', - 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', - 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', - 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', - 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', - 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BATCH_HIST_NUM_PRIMS', - 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', - 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', - 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', - 'SC_PBB_BIN_HIST_NUM_CONTEXTS', - 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', - 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', - 'SC_PBB_BUSY_AND_NO_SENDS', - 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', - 'SC_PBB_END_OF_BIN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', - 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', - 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', - 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', - 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', - 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', - 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', - 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', - 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', - 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', - 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', - 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', - 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', - 'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', - 'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK', - 'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', - 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', - 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', - 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', - 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', - 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', - 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', - 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', - 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', - 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', - 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', - 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', - 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', - 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', - 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', - 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', - 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', - 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', - 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', - 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', - 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', - 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', - 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', - 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', - 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE', - 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', - 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', - 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', - 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', - 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', - 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', - 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', - 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM', - 'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', - 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', - 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', - 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', - 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', - 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', - 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', - 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', - 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', - 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', - 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', - 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT', - 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', - 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', - 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', - 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', - 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', - 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', - 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', - 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', - 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', - 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', - 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', - 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', - 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', - 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', - 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', - 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', - 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', - 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', - 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', - 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', - 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT', - 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', - 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', - 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', - 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', - 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', - 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', - 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', - 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', - 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', - 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', - 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', - 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1', - 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', - 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', - 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', - 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', - 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0', - 'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0', - 'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0', - 'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0', - 'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT', - 'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2', - 'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID', - 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', - 'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO', - 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', - 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', - 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', - 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', - 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', - 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', - 'SC_SUPERTILE_COUNT', - 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', - 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', - 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', - 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', - 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', - 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', - 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', - 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', - 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', - 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', - 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', - 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', - 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', - 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', - 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', - 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', - 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', - 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', - 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', - 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', - 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', - 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', - 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', - 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', - 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', - 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', - 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', - 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', - 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', - 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', - 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX', - 'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE', - 'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE', - 'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0', 'SDMA0_BASE__INST0_SEG1', - 'SDMA0_BASE__INST0_SEG2', 'SDMA0_BASE__INST0_SEG3', - 'SDMA0_BASE__INST0_SEG4', 'SDMA0_BASE__INST1_SEG0', - 'SDMA0_BASE__INST1_SEG1', 'SDMA0_BASE__INST1_SEG2', - 'SDMA0_BASE__INST1_SEG3', 'SDMA0_BASE__INST1_SEG4', - 'SDMA0_BASE__INST2_SEG0', 'SDMA0_BASE__INST2_SEG1', - 'SDMA0_BASE__INST2_SEG2', 'SDMA0_BASE__INST2_SEG3', - 'SDMA0_BASE__INST2_SEG4', 'SDMA0_BASE__INST3_SEG0', - 'SDMA0_BASE__INST3_SEG1', 'SDMA0_BASE__INST3_SEG2', - 'SDMA0_BASE__INST3_SEG3', 'SDMA0_BASE__INST3_SEG4', - 'SDMA0_BASE__INST4_SEG0', 'SDMA0_BASE__INST4_SEG1', - 'SDMA0_BASE__INST4_SEG2', 'SDMA0_BASE__INST4_SEG3', - 'SDMA0_BASE__INST4_SEG4', 'SDMA0_BASE__INST5_SEG0', - 'SDMA0_BASE__INST5_SEG1', 'SDMA0_BASE__INST5_SEG2', - 'SDMA0_BASE__INST5_SEG3', 'SDMA0_BASE__INST5_SEG4', - 'SDMA0_BASE__INST6_SEG0', 'SDMA0_BASE__INST6_SEG1', - 'SDMA0_BASE__INST6_SEG2', 'SDMA0_BASE__INST6_SEG3', - 'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE', 'SDMA1_BASE__INST0_SEG0', - 'SDMA1_BASE__INST0_SEG1', 'SDMA1_BASE__INST0_SEG2', - 'SDMA1_BASE__INST0_SEG3', 'SDMA1_BASE__INST0_SEG4', - 'SDMA1_BASE__INST1_SEG0', 'SDMA1_BASE__INST1_SEG1', - 'SDMA1_BASE__INST1_SEG2', 'SDMA1_BASE__INST1_SEG3', - 'SDMA1_BASE__INST1_SEG4', 'SDMA1_BASE__INST2_SEG0', - 'SDMA1_BASE__INST2_SEG1', 'SDMA1_BASE__INST2_SEG2', - 'SDMA1_BASE__INST2_SEG3', 'SDMA1_BASE__INST2_SEG4', - 'SDMA1_BASE__INST3_SEG0', 'SDMA1_BASE__INST3_SEG1', - 'SDMA1_BASE__INST3_SEG2', 'SDMA1_BASE__INST3_SEG3', - 'SDMA1_BASE__INST3_SEG4', 'SDMA1_BASE__INST4_SEG0', - 'SDMA1_BASE__INST4_SEG1', 'SDMA1_BASE__INST4_SEG2', - 'SDMA1_BASE__INST4_SEG3', 'SDMA1_BASE__INST4_SEG4', - 'SDMA1_BASE__INST5_SEG0', 'SDMA1_BASE__INST5_SEG1', - 'SDMA1_BASE__INST5_SEG2', 'SDMA1_BASE__INST5_SEG3', - 'SDMA1_BASE__INST5_SEG4', 'SDMA1_BASE__INST6_SEG0', - 'SDMA1_BASE__INST6_SEG1', 'SDMA1_BASE__INST6_SEG2', - 'SDMA1_BASE__INST6_SEG3', 'SDMA1_BASE__INST6_SEG4', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', - 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', - 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', - 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', - 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', - 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', - 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', - 'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', - 'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL', - 'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE', - 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE', - 'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', - 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', - 'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL', - 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', - 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', - 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', - 'SDMA_PERFMON_SEL_EX_IDLE', - 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN', - 'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT', - 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', - 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', - 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', - 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', - 'SDMA_PERFMON_SEL_INT_REQ_STALL', - 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERFMON_SEL_INT_RESP_RETRY', - 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', - 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', - 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', - 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', - 'SDMA_PERFMON_SEL_L2_META_RET_VLD', - 'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', - 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', - 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', - 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', - 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT', - 'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE', - 'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL', - 'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', - 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', - 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', - 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT', - 'SDMA_PERFMON_SEL_RLC1_SELECT', - 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', - 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', - 'SDMA_PERFMON_SEL_SEM_REQ_STALL', - 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', - 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERFMON_SEL_SEM_RESP_PASS', - 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', - 'SDMA_PERFMON_SEL_TLBI_SEND', - 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', - 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', - 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', - 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', - 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', - 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', - 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', - 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', - 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', - 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', - 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', - 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', - 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', - 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', - 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', - 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', - 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', - 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', - 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', - 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', - 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', - 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', - 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', - 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', - 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', - 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', - 'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET', - 'SDMA_PERF_SEL_F32_L1_WR_VLD', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', - 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', - 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', - 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH', - 'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ', - 'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL', - 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', - 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', - 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', - 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', - 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', - 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', - 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', - 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', - 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', - 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', - 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', - 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', - 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', - 'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET', - 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', - 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', - 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', - 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', - 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', - 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', - 'SDMA_PERF_SEL_SDMA_CPF_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', - 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', - 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', - 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', - 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', - 'SDMA_PERF_SEL_SEM_RESP_FAIL', - 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', - 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', - 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', - 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', - 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', - 'SDMA_PERF_SEL_UTCL2_RET_XNACK', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', - 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', - 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', - 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', - 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', - 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_mask', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_offset', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_shift', - 'SDMA_PKT_ATOMIC_HEADER_cpv_mask', - 'SDMA_PKT_ATOMIC_HEADER_cpv_offset', - 'SDMA_PKT_ATOMIC_HEADER_cpv_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_mask', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_offset', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_shift', - 'SDMA_PKT_COND_EXE_HEADER_cpv_mask', - 'SDMA_PKT_COND_EXE_HEADER_cpv_offset', - 'SDMA_PKT_COND_EXE_HEADER_cpv_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_mask', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_offset', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', - 'SDMA_PKT_FENCE_HEADER_cpv_mask', - 'SDMA_PKT_FENCE_HEADER_cpv_offset', - 'SDMA_PKT_FENCE_HEADER_cpv_shift', - 'SDMA_PKT_FENCE_HEADER_gcc_mask', - 'SDMA_PKT_FENCE_HEADER_gcc_offset', - 'SDMA_PKT_FENCE_HEADER_gcc_shift', - 'SDMA_PKT_FENCE_HEADER_gpa_mask', - 'SDMA_PKT_FENCE_HEADER_gpa_offset', - 'SDMA_PKT_FENCE_HEADER_gpa_shift', - 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', - 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', - 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', - 'SDMA_PKT_FENCE_HEADER_llc_policy_mask', - 'SDMA_PKT_FENCE_HEADER_llc_policy_offset', - 'SDMA_PKT_FENCE_HEADER_llc_policy_shift', - 'SDMA_PKT_FENCE_HEADER_mtype_mask', - 'SDMA_PKT_FENCE_HEADER_mtype_offset', - 'SDMA_PKT_FENCE_HEADER_mtype_shift', - 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_snp_mask', - 'SDMA_PKT_FENCE_HEADER_snp_offset', - 'SDMA_PKT_FENCE_HEADER_snp_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', - 'SDMA_PKT_FENCE_HEADER_sys_mask', - 'SDMA_PKT_FENCE_HEADER_sys_offset', - 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_GCR_REQ_HEADER_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_op_shift', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', - 'SDMA_PKT_HDP_FLUSH', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_priv_mask', - 'SDMA_PKT_INDIRECT_HEADER_priv_offset', - 'SDMA_PKT_INDIRECT_HEADER_priv_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_mask', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_offset', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_shift', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_op_shift', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_mask', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_offset', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_shift', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_mask', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_offset', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', - 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_MEM_INCR', 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', - 'SDMA_SUBOP_POLL_MEM_VERIFY', 'SDMA_SUBOP_POLL_REG_WRITE_MEM', - 'SDMA_SUBOP_PTEPDE_COPY', 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', - 'SDMA_SUBOP_PTEPDE_GEN', 'SDMA_SUBOP_PTEPDE_RMW', - 'SDMA_SUBOP_TIMESTAMP_GET', 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', - 'SDMA_SUBOP_TIMESTAMP_SET', 'SDMA_SUBOP_USER_GCR', - 'SDMA_SUBOP_VM_INVALIDATION', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', 'SDMA_SUBOP_WRITE_TILED_BC', - 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', - 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', - 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK0', - 'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', 'SEM_PERF_SEL', - 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT', - 'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ', - 'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_VM_INVALIDATION', - 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', - 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', - 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', - 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', - 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', - 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', - 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', - 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', - 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', - 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', - 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT', - 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT', - 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT', - 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', - 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', - 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', - 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', - 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', - 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', - 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', - 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', - 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', - 'SH_MEM_ALIGNMENT_MODE_DWORD', - 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', - 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', - 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', - 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', - 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', - 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', - 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', - 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', - 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', - 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', - 'SLVERR', 'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0', - 'SMUIO_BASE__INST0_SEG1', 'SMUIO_BASE__INST0_SEG2', - 'SMUIO_BASE__INST0_SEG3', 'SMUIO_BASE__INST0_SEG4', - 'SMUIO_BASE__INST1_SEG0', 'SMUIO_BASE__INST1_SEG1', - 'SMUIO_BASE__INST1_SEG2', 'SMUIO_BASE__INST1_SEG3', - 'SMUIO_BASE__INST1_SEG4', 'SMUIO_BASE__INST2_SEG0', - 'SMUIO_BASE__INST2_SEG1', 'SMUIO_BASE__INST2_SEG2', - 'SMUIO_BASE__INST2_SEG3', 'SMUIO_BASE__INST2_SEG4', - 'SMUIO_BASE__INST3_SEG0', 'SMUIO_BASE__INST3_SEG1', - 'SMUIO_BASE__INST3_SEG2', 'SMUIO_BASE__INST3_SEG3', - 'SMUIO_BASE__INST3_SEG4', 'SMUIO_BASE__INST4_SEG0', - 'SMUIO_BASE__INST4_SEG1', 'SMUIO_BASE__INST4_SEG2', - 'SMUIO_BASE__INST4_SEG3', 'SMUIO_BASE__INST4_SEG4', - 'SMUIO_BASE__INST5_SEG0', 'SMUIO_BASE__INST5_SEG1', - 'SMUIO_BASE__INST5_SEG2', 'SMUIO_BASE__INST5_SEG3', - 'SMUIO_BASE__INST5_SEG4', 'SMUIO_BASE__INST6_SEG0', - 'SMUIO_BASE__INST6_SEG1', 'SMUIO_BASE__INST6_SEG2', - 'SMUIO_BASE__INST6_SEG3', 'SMUIO_BASE__INST6_SEG4', 'SMU_INTR', - 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', - 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', 'SOFT_RESET', - 'SOFT_RESET_0', 'SOFT_RESET_1', 'SO_VGTSTREAMOUT_FLUSH', - 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', - 'SPI_FOG_NONE', 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', - 'SPI_PERFCNT_SEL', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', - 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', - 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', - 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID', - 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', - 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', - 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', - 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', - 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', - 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', - 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', - 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', - 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', - 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', - 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', - 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', - 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', - 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', - 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', - 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE', - 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC', - 'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL', - 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', - 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', - 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', - 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', - 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', - 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', - 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', - 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', - 'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0', - 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', - 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', - 'SPI_PERF_NUM_EXPGRANT_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', - 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', - 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', - 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', - 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', - 'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', - 'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0', - 'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE', - 'SPI_PERF_PS0_WAVEID_STARVED', - 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID', - 'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE', - 'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL', - 'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE', - 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE', - 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', - 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', - 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID', - 'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE', - 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL', - 'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE', - 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE', - 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', - 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', - 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID', - 'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE', - 'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL', - 'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE', - 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE', - 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', - 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', - 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', - 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID', - 'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT', - 'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0', - 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', - 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', - 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', - 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', - 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', - 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', - 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', - 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', - 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', - 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', - 'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC', - 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', - 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', - 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG', - 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', - 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', - 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3', - 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', - 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', - 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', - 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', - 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', - 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', - 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', - 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', - 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', - 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', - 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', - 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR', - 'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', - 'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR', - 'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', - 'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', - 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', - 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', - 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', - 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', - 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', - 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', - 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', - 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', - 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', - 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', - 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', - 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', - 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', - 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', - 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', - 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', - 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', - 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', - 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', - 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', - 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', - 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_OPERAND', - 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', - 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', - 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', - 'SP_PERF_SEL_VALU_STALL_DST_STALL', - 'SP_PERF_SEL_VALU_STALL_SDST_FWD', - 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', - 'SP_PERF_SEL_VALU_STALL_VDST_FWD', - 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', - 'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD', - 'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR', - 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD', - 'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', - 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', - 'SQC_PERF_SEL_DCACHE_GCR_HITS', - 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', - 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', - 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', - 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ', - 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', - 'SQC_PERF_SEL_DCACHE_REQ_READ_1', - 'SQC_PERF_SEL_DCACHE_REQ_READ_16', - 'SQC_PERF_SEL_DCACHE_REQ_READ_2', - 'SQC_PERF_SEL_DCACHE_REQ_READ_4', - 'SQC_PERF_SEL_DCACHE_REQ_READ_8', - 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', - 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', - 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', - 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', - 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', - 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', - 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', - 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', - 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', - 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', - 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', - 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', - 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', - 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', - 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', - 'SQC_PERF_SEL_LDS_BANK_CONFLICT', - 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', - 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', - 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', - 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', - 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', - 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', - 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', - 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', - 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', - 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', - 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', - 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', - 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', - 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', - 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', - 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', - 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', - 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG', - 'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT', - 'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS', - 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', - 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', - 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS', - 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', - 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', - 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', - 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', - 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', - 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED', - 'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES', - 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', - 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', - 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', - 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', - 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', - 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', - 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', - 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', - 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', - 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', - 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', - 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', - 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', - 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', - 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', - 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', - 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', - 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', - 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', - 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', - 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', - 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', - 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', - 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', - 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', - 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', - 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', - 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', - 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', - 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', - 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', - 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', - 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', - 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', - 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', - 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', - 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', - 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', - 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', - 'SQ_IND_CMD_MODE_BROADCAST_PIPE', - 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', - 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', - 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', - 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', - 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', - 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', - 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', - 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', - 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', - 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', - 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1', - 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', - 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', - 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', - 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN', - 'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER', - 'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT', - 'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', - 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', - 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', - 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', - 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', - 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', - 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', - 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', - 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', - 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH', - 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', - 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', - 'SQ_PERF_SEL_INSTS_DELAY_ALU', - 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', - 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', - 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL', - 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', - 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU', - 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', - 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX', - 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE', - 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', - 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', - 'SQ_PERF_SEL_INSTS_VALU_DP', - 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', - 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', - 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', - 'SQ_PERF_SEL_INSTS_VALU_VINTERP', - 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', - 'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', - 'SQ_PERF_SEL_INSTS_WAVE32_LDS', - 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', - 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', - 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', - 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS', - 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', - 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', - 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', - 'SQ_PERF_SEL_INST_CYCLES_VMEM', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', - 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', - 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', - 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', - 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', - 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', - 'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU', - 'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', - 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', - 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', - 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', - 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', - 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', - 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', - 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', - 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', - 'SQ_PERF_SEL_SP_CONST_CYCLES', - 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', - 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', - 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', - 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', - 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', - 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', - 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', - 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', - 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', - 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', - 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', - 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', - 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', - 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', - 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', - 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', - 'SQ_PERF_SEL_VALU_RETURN_SDST', - 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', - 'SQ_PERF_SEL_VALU_SGATHER_STALL', - 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', - 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', - 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', - 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', - 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', - 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', - 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS', - 'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR', - 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', - 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG', - 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', - 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA', - 'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU', - 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', - 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE', - 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', - 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', - 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', - 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', - 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', - 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', - 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', - 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', - 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', - 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', - 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', - 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', - 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', - 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', - 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', - 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', - 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', - 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', - 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', - 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', - 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', - 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1', - 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', - 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO', - 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', - 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', - 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', - 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', - 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', - 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', - 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', - 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', - 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', - 'SQ_TEX_DEPTH_COMPARE_GREATER', - 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', - 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', - 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', - 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', - 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', - 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', - 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', - 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', - 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', - 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', - 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', - 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', - 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', - 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', - 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', - 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE', - 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', - 'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', - 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', - 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', - 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', - 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', - 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ', - 'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK', - 'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', - 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', - 'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT', - 'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT', - 'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', - 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', - 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', - 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT', - 'SQ_TT_TOKEN_MASK_REG_EXCLUDE', - 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE', - 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT', - 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT', - 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT', - 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', - 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', - 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', - 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', - 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', - 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', - 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', - 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', - 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', - 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', - 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', - 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', - 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', - 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', - 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', - 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', - 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', - 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', - 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', - 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', - 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', - 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', - 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', - 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', - 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', - 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', - 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', - 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', - 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', - 'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', - 'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP', - 'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV', - 'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'STALL', - 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', - 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', - 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', - 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', - 'STREAM_0_SYNCHRONIZATION', - 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_10_SYNCHRONIZATION', - 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION', - 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION', - 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION', - 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION', - 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION', - 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_1_SYNCHRONIZATION', - 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_2_SYNCHRONIZATION', - 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_3_SYNCHRONIZATION', - 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', - 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', - 'STREAM_4_SYNCHRONIZATION', - 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION', - 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION', - 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION', - 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION', - 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION', - 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', - 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', - 'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE', - 'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT', - 'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT', - 'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420', - 'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB', - 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET', - 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', - 'STRM_PERFMON_STATE_RESERVED_3', - 'STRM_PERFMON_STATE_START_COUNTING', - 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', - 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', - 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', - 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', - 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', - 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', - 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', - 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', - 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', - 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', - 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', - 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', - 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', - 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', - 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLE', - 'SURFACE_FLIP_STEREO_SELECT_DISABLED', - 'SURFACE_FLIP_STEREO_SELECT_ENABLED', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', - 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', - 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', - 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', - 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', - 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', - 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', - 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', - 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', - 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', - 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', - 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', - 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', - 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', - 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', - 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', - 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', - 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', - 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', - 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', - 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', - 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', - 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', - 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', - 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', - 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', - 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', - 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', - 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', - 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', - 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', - 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', - 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', - 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', - 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', - 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', - 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', - 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', - 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', - 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', - 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', - 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', - 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', - 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', - 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', - 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', - 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', - 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', - 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', - 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', - 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', - 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', - 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', - 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', - 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', - 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', - 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', - 'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', - 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', - 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'ScMap', 'ScUncertaintyRegionMode', - 'ScUncertaintyRegionMult', 'ScXsel', 'ScYsel', 'SeMap', - 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', - 'SourceFormat', 'Spare_257', 'StencilOp', 'TA_PERFCOUNT_SEL', - 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', - 'TA_PERF_SEL_addr_stalled_by_td_cycles', - 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', - 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', - 'TA_PERF_SEL_addresser_stalled_cycles', - 'TA_PERF_SEL_aligner_busy', - 'TA_PERF_SEL_aligner_clk_valid_cycles', - 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', - 'TA_PERF_SEL_aniso_12_cycle_quads', - 'TA_PERF_SEL_aniso_14_cycle_quads', - 'TA_PERF_SEL_aniso_16_cycle_quads', - 'TA_PERF_SEL_aniso_1_cycle_quads', - 'TA_PERF_SEL_aniso_2_cycle_quads', - 'TA_PERF_SEL_aniso_4_cycle_quads', - 'TA_PERF_SEL_aniso_6_cycle_quads', - 'TA_PERF_SEL_aniso_8_cycle_quads', - 'TA_PERF_SEL_aniso_gt1_cycle_quads', - 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', - 'TA_PERF_SEL_aniso_stalled_cycles', - 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_atomic_write_data_input_cycles', - 'TA_PERF_SEL_atomic_write_data_output_cycles', - 'TA_PERF_SEL_bf_busy', - 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_buffer_atomic_wavefronts', - 'TA_PERF_SEL_buffer_flat_1_op_burst', - 'TA_PERF_SEL_buffer_flat_2to3_op_burst', - 'TA_PERF_SEL_buffer_flat_4to31_op_burst', - 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', - 'TA_PERF_SEL_buffer_flat_ge32_op_burst', - 'TA_PERF_SEL_buffer_has_index_instructions', - 'TA_PERF_SEL_buffer_has_offset_instructions', - 'TA_PERF_SEL_buffer_load_wavefronts', - 'TA_PERF_SEL_buffer_store_wavefronts', - 'TA_PERF_SEL_buffer_total_cycles', - 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles', - 'TA_PERF_SEL_color_1_cycle_quads', - 'TA_PERF_SEL_color_2_cycle_quads', - 'TA_PERF_SEL_color_3_cycle_quads', - 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', - 'TA_PERF_SEL_deriv_stalled_cycles', - 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_flat_atomic_wavefronts', - 'TA_PERF_SEL_flat_load_wavefronts', - 'TA_PERF_SEL_flat_store_wavefronts', - 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', - 'TA_PERF_SEL_gradient_busy', - 'TA_PERF_SEL_gradient_clk_valid_cycles', - 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', - 'TA_PERF_SEL_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', - 'TA_PERF_SEL_ibubble_16to31_cycle_burst', - 'TA_PERF_SEL_ibubble_1_cycle_burst', - 'TA_PERF_SEL_ibubble_2to3_cycle_burst', - 'TA_PERF_SEL_ibubble_32to63_cycle_burst', - 'TA_PERF_SEL_ibubble_4to15_cycle_burst', - 'TA_PERF_SEL_ibubble_ge64_cycle_burst', - 'TA_PERF_SEL_image_atomic_wavefronts', - 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_1_op_burst', - 'TA_PERF_SEL_image_bvh_2to3_op_burst', - 'TA_PERF_SEL_image_bvh_4to7_op_burst', - 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', - 'TA_PERF_SEL_image_bvh_ge8_op_burst', - 'TA_PERF_SEL_image_linked_1_op_burst', - 'TA_PERF_SEL_image_linked_2to3_op_burst', - 'TA_PERF_SEL_image_linked_4to7_op_burst', - 'TA_PERF_SEL_image_linked_ge8_op_burst', - 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_1_op_burst', - 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_2to3_op_burst', - 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', - 'TA_PERF_SEL_image_nosampler_4to31_op_burst', - 'TA_PERF_SEL_image_nosampler_ge32_op_burst', - 'TA_PERF_SEL_image_nosampler_has_q_instructions', - 'TA_PERF_SEL_image_nosampler_has_r_instructions', - 'TA_PERF_SEL_image_nosampler_has_t_instructions', - 'TA_PERF_SEL_image_nosampler_total_cycles', - 'TA_PERF_SEL_image_read_wavefronts', - 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_1_op_burst', - 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_2to3_op_burst', - 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_4to7_op_burst', - 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', - 'TA_PERF_SEL_image_sampler_ge8_op_burst', - 'TA_PERF_SEL_image_sampler_has_bias_instructions', - 'TA_PERF_SEL_image_sampler_has_dr_instructions', - 'TA_PERF_SEL_image_sampler_has_ds_instructions', - 'TA_PERF_SEL_image_sampler_has_dt_instructions', - 'TA_PERF_SEL_image_sampler_has_offset_instructions', - 'TA_PERF_SEL_image_sampler_has_q_instructions', - 'TA_PERF_SEL_image_sampler_has_r_instructions', - 'TA_PERF_SEL_image_sampler_has_reference_instructions', - 'TA_PERF_SEL_image_sampler_has_t_instructions', - 'TA_PERF_SEL_image_sampler_total_cycles', - 'TA_PERF_SEL_image_sampler_wavefronts', - 'TA_PERF_SEL_image_store_wavefronts', - 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', - 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', - 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', - 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', - 'TA_PERF_SEL_in_waiting_on_req_cycles', - 'TA_PERF_SEL_in_wfifo_busy', - 'TA_PERF_SEL_latency_ram_ref_required_instructions', - 'TA_PERF_SEL_latency_ram_weights_written_cycles', - 'TA_PERF_SEL_latency_ram_whv_required_instructions', - 'TA_PERF_SEL_latency_ram_whv_required_quads', - 'TA_PERF_SEL_latency_ram_ws_required_instructions', - 'TA_PERF_SEL_latency_ram_ws_required_quads', - 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', - 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', - 'TA_PERF_SEL_mip_2_cycle_quads', - 'TA_PERF_SEL_mipmap_invalid_samples', - 'TA_PERF_SEL_mipmap_lod_0_samples', - 'TA_PERF_SEL_mipmap_lod_10_samples', - 'TA_PERF_SEL_mipmap_lod_11_samples', - 'TA_PERF_SEL_mipmap_lod_12_samples', - 'TA_PERF_SEL_mipmap_lod_13_samples', - 'TA_PERF_SEL_mipmap_lod_14_samples', - 'TA_PERF_SEL_mipmap_lod_1_samples', - 'TA_PERF_SEL_mipmap_lod_2_samples', - 'TA_PERF_SEL_mipmap_lod_3_samples', - 'TA_PERF_SEL_mipmap_lod_4_samples', - 'TA_PERF_SEL_mipmap_lod_5_samples', - 'TA_PERF_SEL_mipmap_lod_6_samples', - 'TA_PERF_SEL_mipmap_lod_7_samples', - 'TA_PERF_SEL_mipmap_lod_8_samples', - 'TA_PERF_SEL_mipmap_lod_9_samples', - 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', - 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', - 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', - 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', - 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', - 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', - 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', - 'TA_PERF_SEL_num_of_bvh_valid_first_tri', - 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', - 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', - 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', - 'TA_PERF_SEL_num_of_bvh_valid_second_tri', - 'TA_PERF_SEL_num_of_bvh_valid_third_tri', - 'TA_PERF_SEL_num_unlit_nodes_ta_opt', - 'TA_PERF_SEL_point_sampled_quads', - 'TA_PERF_SEL_register_clk_valid_cycles', - 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', - 'TA_PERF_SEL_sampler_clk_valid_cycles', - 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', - 'TA_PERF_SEL_smp_idle_ns_busy', - 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', - 'TA_PERF_SEL_store_has_w_instructions', - 'TA_PERF_SEL_store_has_x_instructions', - 'TA_PERF_SEL_store_has_y_instructions', - 'TA_PERF_SEL_store_has_z_instructions', - 'TA_PERF_SEL_store_write_data_input_cycles', - 'TA_PERF_SEL_store_write_data_output_cycles', - 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', - 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', - 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', - 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', - 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', - 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', - 'TA_PERF_SEL_write_4to31_op_burst', - 'TA_PERF_SEL_write_data_clk_valid_cycles', - 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', - 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', - 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', - 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', - 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', - 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', - 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', - 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', - 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TB_ACP_NOT_SEND', - 'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED', - 'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE', - 'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE', - 'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED', - 'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE', - 'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND', - 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND', - 'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K', - 'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW', - 'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE', - 'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND', - 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', - 'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK', - 'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED', - 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES', - 'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES', - 'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER', - 'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT', - 'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP', - 'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED', - 'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE', - 'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420', - 'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE', - 'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET', - 'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE', - 'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE', - 'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND', - 'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE', - 'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND', - 'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET', - 'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED', - 'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420', - 'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB', - 'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF', - 'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES', - 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', - 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', - 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', - 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', - 'TCP_CACHE_STORE_POLICY_WT_EVICT', - 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', - 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', - 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', - 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', - 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', - 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', - 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', - 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', - 'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', - 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', - 'TCP_PERF_SEL_ALLOC_STALL', - 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', - 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', - 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', - 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', - 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', - 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', - 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', - 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', - 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', - 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', - 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', - 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL', - 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', - 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', - 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', - 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', - 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', - 'TCP_PERF_SEL_REQ_READ_HIT_LRU', - 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', - 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE', - 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', - 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', - 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', - 'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ', - 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', - 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY', - 'TCP_PERF_SEL_TCP_TA_REQ_STALL', - 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', - 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', - 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', - 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', - 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', - 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', - 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', - 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', - 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', - 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', - 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', - 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', - 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', - 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', - 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', - 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', - 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', - 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', - 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', - 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', - 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', - 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', - 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', - 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', - 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', - 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', - 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', - 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', - 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', - 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', - 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', - 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', - 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', - 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', - 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', - 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', - 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', - 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', - 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', - 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', - 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', - 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', - 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', - 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', - 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', - 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', - 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', - 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', - 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', - 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', - 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', - 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', - 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', - 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', - 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', - 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', - 'TC_OP_RESERVED_NON_FLOAT_64_4', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', - 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', - 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', - 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', - 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', - 'TD_PERF_SEL_address_cmd_poison', - 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', - 'TD_PERF_SEL_blend_prt_with_prt_default_0', - 'TD_PERF_SEL_blend_prt_with_prt_default_1', - 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', - 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', - 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', - 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', - 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', - 'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', - 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', - 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', - 'TD_PERF_SEL_burst_bin_gather_1', - 'TD_PERF_SEL_burst_bin_gather_2to8', - 'TD_PERF_SEL_burst_bin_gather_9to16', - 'TD_PERF_SEL_burst_bin_gather_gt16', - 'TD_PERF_SEL_burst_bin_nofilter_1', - 'TD_PERF_SEL_burst_bin_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', - 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', - 'TD_PERF_SEL_burst_bin_sampler_1', - 'TD_PERF_SEL_burst_bin_sampler_2to8', - 'TD_PERF_SEL_burst_bin_sampler_9to16', - 'TD_PERF_SEL_burst_bin_sampler_gt16', - 'TD_PERF_SEL_bypassLerp_instr', - 'TD_PERF_SEL_core_state_ram_max_cnt', - 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', - 'TD_PERF_SEL_data_poison', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', - 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', - 'TD_PERF_SEL_done_scoreboard_is_full', - 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', - 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', - 'TD_PERF_SEL_done_scoreboard_not_empty', - 'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr', - 'TD_PERF_SEL_gather4h_instr', - 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', - 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', - 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr', - 'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr', - 'TD_PERF_SEL_lod_warn_from_ta', - 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', - 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', - 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_nofilter_busy', - 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', - 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', - 'TD_PERF_SEL_nofilter_d16_sclk_en', - 'TD_PERF_SEL_nofilter_d32_sclk_en', - 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', - 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', - 'TD_PERF_SEL_nofilter_formatters_turned_on', - 'TD_PERF_SEL_nofilter_insert_extra_comps', - 'TD_PERF_SEL_nofilter_pkr_full', - 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', - 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', - 'TD_PERF_SEL_nofilter_sclk_en', - 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', - 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', - 'TD_PERF_SEL_one_comp_return_instr', - 'TD_PERF_SEL_opaque_black_border', - 'TD_PERF_SEL_out_of_order_instr', - 'TD_PERF_SEL_preempting_nofilter_max_cnt', - 'TD_PERF_SEL_prt_ack_instr', - 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', - 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', - 'TD_PERF_SEL_ray_tracing_bvh4_busy', - 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', - 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', - 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', - 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', - 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', - 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', - 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', - 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', - 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', - 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', - 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', - 'TD_PERF_SEL_reference_data_rams_read', - 'TD_PERF_SEL_resmap_instr', - 'TD_PERF_SEL_resmap_with_aniso_filtering', - 'TD_PERF_SEL_resmap_with_cubemap_corner', - 'TD_PERF_SEL_resmap_with_no_more_filtering', - 'TD_PERF_SEL_resmap_with_volume_filtering', - 'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr', - 'TD_PERF_SEL_sampler_accum_sclk_en', - 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', - 'TD_PERF_SEL_sampler_bilerp_sclk_en', - 'TD_PERF_SEL_sampler_bypass_sclk_en', - 'TD_PERF_SEL_sampler_core_sclk_en', - 'TD_PERF_SEL_sampler_format_flt_sclk_en', - 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', - 'TD_PERF_SEL_sampler_lerp0_active', - 'TD_PERF_SEL_sampler_lerp1_active', - 'TD_PERF_SEL_sampler_lerp2_active', - 'TD_PERF_SEL_sampler_lerp3_active', - 'TD_PERF_SEL_sampler_lerp_busy', - 'TD_PERF_SEL_sampler_minmax_sclk_en', - 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', - 'TD_PERF_SEL_sampler_pkr_full', - 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', - 'TD_PERF_SEL_sampler_preformatter_sclk_en', - 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', - 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', - 'TD_PERF_SEL_tc_td_data_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_full', - 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', - 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', - 'TD_PERF_SEL_three_comp_return_instr', - 'TD_PERF_SEL_total_num_instr', - 'TD_PERF_SEL_total_num_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_nofilter_instr', - 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', - 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', - 'TD_PERF_SEL_total_num_sampler_instr', - 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', - 'TD_PERF_SEL_two_comp_return_instr', - 'TD_PERF_SEL_user_defined_border', - 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', - 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', - 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', - 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', - 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', - 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', - 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', - 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', - 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', - 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', - 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', - 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', - 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', - 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', - 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', - 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', - 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', - 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', - 'TEX_Clamp_MirrorOnceHalfToBorder', - 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', - 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', - 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', - 'TEX_DepthCompareFunction_Always', - 'TEX_DepthCompareFunction_Equal', - 'TEX_DepthCompareFunction_Greater', - 'TEX_DepthCompareFunction_GreaterEqual', - 'TEX_DepthCompareFunction_Less', - 'TEX_DepthCompareFunction_LessEqual', - 'TEX_DepthCompareFunction_Never', - 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', - 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', - 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', - 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', - 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', - 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', - 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', - 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', - 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', - 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', - 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', - 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', - 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', - 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', - 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', - 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', - 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', - 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', - 'THM_BASE', 'THM_BASE__INST0_SEG0', 'THM_BASE__INST0_SEG1', - 'THM_BASE__INST0_SEG2', 'THM_BASE__INST0_SEG3', - 'THM_BASE__INST0_SEG4', 'THM_BASE__INST1_SEG0', - 'THM_BASE__INST1_SEG1', 'THM_BASE__INST1_SEG2', - 'THM_BASE__INST1_SEG3', 'THM_BASE__INST1_SEG4', - 'THM_BASE__INST2_SEG0', 'THM_BASE__INST2_SEG1', - 'THM_BASE__INST2_SEG2', 'THM_BASE__INST2_SEG3', - 'THM_BASE__INST2_SEG4', 'THM_BASE__INST3_SEG0', - 'THM_BASE__INST3_SEG1', 'THM_BASE__INST3_SEG2', - 'THM_BASE__INST3_SEG3', 'THM_BASE__INST3_SEG4', - 'THM_BASE__INST4_SEG0', 'THM_BASE__INST4_SEG1', - 'THM_BASE__INST4_SEG2', 'THM_BASE__INST4_SEG3', - 'THM_BASE__INST4_SEG4', 'THM_BASE__INST5_SEG0', - 'THM_BASE__INST5_SEG1', 'THM_BASE__INST5_SEG2', - 'THM_BASE__INST5_SEG3', 'THM_BASE__INST5_SEG4', - 'THM_BASE__INST6_SEG0', 'THM_BASE__INST6_SEG1', - 'THM_BASE__INST6_SEG2', 'THM_BASE__INST6_SEG3', - 'THM_BASE__INST6_SEG4', 'THREAD_TRACE_DRAW', - 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', - 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK', - 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', - 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', - 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', - 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', - 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', - 'TMDS_CTL0_DATA_MODULATION_BIT1', - 'TMDS_CTL0_DATA_MODULATION_BIT2', - 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', - 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', - 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', - 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', - 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', - 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', - 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', - 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', - 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', - 'TMDS_CTL1_DATA_MODULATION_BIT0', - 'TMDS_CTL1_DATA_MODULATION_BIT1', - 'TMDS_CTL1_DATA_MODULATION_BIT2', - 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', - 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', - 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', - 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', - 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', - 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', - 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', - 'TMDS_CTL2_DATA_MODULATION_BIT0', - 'TMDS_CTL2_DATA_MODULATION_BIT1', - 'TMDS_CTL2_DATA_MODULATION_BIT2', - 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', - 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', - 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', - 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', - 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', - 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', - 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', - 'TMDS_CTL3_DATA_MODULATION_BIT0', - 'TMDS_CTL3_DATA_MODULATION_BIT1', - 'TMDS_CTL3_DATA_MODULATION_BIT2', - 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', - 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', - 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', - 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', - 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', - 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', - 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', - 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', - 'TMDS_CTL3_PATTERN_OUT_ENABLE', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', - 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', - 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', - 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', - 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', - 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', - 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', - 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', - 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', - 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', - 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', - 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', - 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', - 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', - 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', - 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', - 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', - 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', - 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', - 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', - 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', - 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', - 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', - 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', - 'TMDS_TRANSMITTER_PLLSEL_BY_HW', - 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', - 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', - 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', - 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', - 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', - 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', - 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', - 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', - 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', - 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', - 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', - 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', - 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', - 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', - 'UCONFIG_SPACE_START', 'UMC_BASE', 'UMC_BASE__INST0_SEG0', - 'UMC_BASE__INST0_SEG1', 'UMC_BASE__INST0_SEG2', - 'UMC_BASE__INST0_SEG3', 'UMC_BASE__INST0_SEG4', - 'UMC_BASE__INST1_SEG0', 'UMC_BASE__INST1_SEG1', - 'UMC_BASE__INST1_SEG2', 'UMC_BASE__INST1_SEG3', - 'UMC_BASE__INST1_SEG4', 'UMC_BASE__INST2_SEG0', - 'UMC_BASE__INST2_SEG1', 'UMC_BASE__INST2_SEG2', - 'UMC_BASE__INST2_SEG3', 'UMC_BASE__INST2_SEG4', - 'UMC_BASE__INST3_SEG0', 'UMC_BASE__INST3_SEG1', - 'UMC_BASE__INST3_SEG2', 'UMC_BASE__INST3_SEG3', - 'UMC_BASE__INST3_SEG4', 'UMC_BASE__INST4_SEG0', - 'UMC_BASE__INST4_SEG1', 'UMC_BASE__INST4_SEG2', - 'UMC_BASE__INST4_SEG3', 'UMC_BASE__INST4_SEG4', - 'UMC_BASE__INST5_SEG0', 'UMC_BASE__INST5_SEG1', - 'UMC_BASE__INST5_SEG2', 'UMC_BASE__INST5_SEG3', - 'UMC_BASE__INST5_SEG4', 'UMC_BASE__INST6_SEG0', - 'UMC_BASE__INST6_SEG1', 'UMC_BASE__INST6_SEG2', - 'UMC_BASE__INST6_SEG3', 'UMC_BASE__INST6_SEG4', 'UNDEF', - 'UNSIGNED', 'USB0_BASE', 'USB0_BASE__INST0_SEG0', - 'USB0_BASE__INST0_SEG1', 'USB0_BASE__INST0_SEG2', - 'USB0_BASE__INST0_SEG3', 'USB0_BASE__INST0_SEG4', - 'USB0_BASE__INST1_SEG0', 'USB0_BASE__INST1_SEG1', - 'USB0_BASE__INST1_SEG2', 'USB0_BASE__INST1_SEG3', - 'USB0_BASE__INST1_SEG4', 'USB0_BASE__INST2_SEG0', - 'USB0_BASE__INST2_SEG1', 'USB0_BASE__INST2_SEG2', - 'USB0_BASE__INST2_SEG3', 'USB0_BASE__INST2_SEG4', - 'USB0_BASE__INST3_SEG0', 'USB0_BASE__INST3_SEG1', - 'USB0_BASE__INST3_SEG2', 'USB0_BASE__INST3_SEG3', - 'USB0_BASE__INST3_SEG4', 'USB0_BASE__INST4_SEG0', - 'USB0_BASE__INST4_SEG1', 'USB0_BASE__INST4_SEG2', - 'USB0_BASE__INST4_SEG3', 'USB0_BASE__INST4_SEG4', - 'USB0_BASE__INST5_SEG0', 'USB0_BASE__INST5_SEG1', - 'USB0_BASE__INST5_SEG2', 'USB0_BASE__INST5_SEG3', - 'USB0_BASE__INST5_SEG4', 'USB0_BASE__INST6_SEG0', - 'USB0_BASE__INST6_SEG1', 'USB0_BASE__INST6_SEG2', - 'USB0_BASE__INST6_SEG3', 'USB0_BASE__INST6_SEG4', - 'USE_MALL_FOR_CURSOR', 'USE_MALL_FOR_CURSOR_0', - 'USE_MALL_FOR_CURSOR_1', 'USE_MALL_FOR_PSTATE_CHANGE', - 'USE_MALL_FOR_PSTATE_CHANGE_0', 'USE_MALL_FOR_PSTATE_CHANGE_1', - 'USE_MALL_FOR_STATIC_SCREEN', 'USE_MALL_FOR_STATIC_SCREEN_0', - 'USE_MALL_FOR_STATIC_SCREEN_1', 'UTCL0FaultType', - 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL', - 'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', - 'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', - 'UTCL1PerfSel', 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', - 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS', - 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', - 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', - 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', - 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', - 'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS', - 'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS', - 'UTCL1_PERF_SEL_STALL_MH_FULL', - 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS', - 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', - 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', - 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', - 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', - 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', - 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', - 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', - 'UTCL1_XNACK_SUCCESS', 'VCN_BASE', 'VCN_BASE__INST0_SEG0', - 'VCN_BASE__INST0_SEG1', 'VCN_BASE__INST0_SEG2', - 'VCN_BASE__INST0_SEG3', 'VCN_BASE__INST0_SEG4', - 'VCN_BASE__INST1_SEG0', 'VCN_BASE__INST1_SEG1', - 'VCN_BASE__INST1_SEG2', 'VCN_BASE__INST1_SEG3', - 'VCN_BASE__INST1_SEG4', 'VCN_BASE__INST2_SEG0', - 'VCN_BASE__INST2_SEG1', 'VCN_BASE__INST2_SEG2', - 'VCN_BASE__INST2_SEG3', 'VCN_BASE__INST2_SEG4', - 'VCN_BASE__INST3_SEG0', 'VCN_BASE__INST3_SEG1', - 'VCN_BASE__INST3_SEG2', 'VCN_BASE__INST3_SEG3', - 'VCN_BASE__INST3_SEG4', 'VCN_BASE__INST4_SEG0', - 'VCN_BASE__INST4_SEG1', 'VCN_BASE__INST4_SEG2', - 'VCN_BASE__INST4_SEG3', 'VCN_BASE__INST4_SEG4', - 'VCN_BASE__INST5_SEG0', 'VCN_BASE__INST5_SEG1', - 'VCN_BASE__INST5_SEG2', 'VCN_BASE__INST5_SEG3', - 'VCN_BASE__INST5_SEG4', 'VCN_BASE__INST6_SEG0', - 'VCN_BASE__INST6_SEG1', 'VCN_BASE__INST6_SEG2', - 'VCN_BASE__INST6_SEG3', 'VCN_BASE__INST6_SEG4', 'VGT_DETECT_ONE', - 'VGT_DETECT_ZERO', 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', - 'VGT_DI_MAJOR_MODE_SELECT', 'VGT_DI_PRIM_TYPE', - 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', - 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', - 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', - 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', - 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', - 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', - 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', - 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', - 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', - 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', - 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', - 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', - 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', - 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', - 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', - 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', - 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', - 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', - 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', - 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', - 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', - 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', - 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', - 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', - 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', - 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', - 'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ', - 'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', - 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE', - 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', - 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', - 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB', - 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB', - 'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB', - 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB', - 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', - 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', - 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', - 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', - 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', - 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', - 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', - 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', - 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', - 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', - 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', - 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', - 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', - 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', - 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', - 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', - 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', - 'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', - 'VTG_SEL_5', 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', - 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', - 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', - 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', - 'WD_IA_DRAW_REG_XFER_GE_CNTL', - 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', - 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', - 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', - 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', - 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', - 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', - 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', - 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', - 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', - 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', - 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', - 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WRITE_DATA_addr_incr_enum', - 'WRITE_DATA_cache_policy_enum', 'WRITE_DATA_dst_sel_enum', - 'WRITE_DATA_wr_confirm_enum', 'WR_CONFIRM', 'WR_ONE_ADDR', - 'WritePolicy', 'XNORM', 'XNORM_A', 'XNORM_B', - 'XTAL_REF_CLOCK_SOURCE_SEL', - 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', - 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', - 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', - 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', - 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', - 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', - 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', - 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', - 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', - 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', - 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', - 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', - 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', - 'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', - 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', - 'ZpassControl', '__SDMA_V6_0_0_PKT_OPEN_H_', '__maybe_unused', - '_gc_10_3_0_OFFSET_HEADER', '_gc_11_0_0_OFFSET_HEADER', - '_sienna_cichlid_ip_offset_HEADER', '_soc21_ENUM_HEADER', - 'addr_incr___write_data__do_not_increment_address', - 'addr_incr___write_data__increment_address', - 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', - 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', - 'cache_policy___write_data__lru', - 'cache_policy___write_data__stream', - 'cache_policy__mec_release_mem__lru', - 'cache_policy__mec_release_mem__stream', - 'data_sel__mec_release_mem__none', - 'data_sel__mec_release_mem__send_32_bit_low', - 'data_sel__mec_release_mem__send_64_bit_data', - 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 'data_sel__mec_release_mem__send_gpu_clock_counter', - 'data_sel__mec_release_mem__store_gds_data_to_memory', - 'dst_sel___write_data__gds', - 'dst_sel___write_data__mem_mapped_register', - 'dst_sel___write_data__memory', - 'dst_sel___write_data__memory_mapped_adc_persistent_state', - 'dst_sel___write_data__tc_l2', - 'dst_sel__mec_release_mem__memory_controller', - 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', - 'dst_sel__mec_release_mem__queue_write_pointer_register', - 'dst_sel__mec_release_mem__tc_l2', - 'event_index__mec_release_mem__end_of_pipe', - 'event_index__mec_release_mem__shader_done', 'ge1_assembler_busy', - 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', - 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', - 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', - 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', - 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', - 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', - 'ge1_dma_utcl1_consecutive_retry_event', - 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', - 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', - 'ge1_dma_utcl1_translation_hit_event', - 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', - 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', - 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', - 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', - 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', - 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', - 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', - 'ge1_small_draws_one_instance', 'ge1_stat_busy', - 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', - 'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req', - 'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2', - 'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6', - 'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy', - 'ge_dist_hs_done', 'ge_dist_hs_done_latency', - 'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1', - 'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3', - 'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5', - 'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7', - 'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1', - 'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3', - 'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5', - 'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7', - 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', - 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', - 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', - 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', - 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', - 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', - 'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0', - 'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2', - 'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4', - 'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6', - 'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero', - 'ge_dist_reserved', 'ge_dist_sclk_core_vld', - 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', - 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', - 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', - 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', - 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', - 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', - 'ge_dist_tfreq_utcl1_consecutive_retry_event', - 'ge_dist_tfreq_utcl1_request_event', - 'ge_dist_tfreq_utcl1_retry_event', - 'ge_dist_tfreq_utcl1_stall_event', - 'ge_dist_tfreq_utcl1_stall_utcl2_event', - 'ge_dist_tfreq_utcl1_translation_hit_event', - 'ge_dist_tfreq_utcl1_translation_miss_event', - 'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld', - 'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', - 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', - 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', - 'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc', - 'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency', - 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', - 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', - 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', - 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', - 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', - 'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant', - 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', - 'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches', - 'ge_num_of_patch_dist_patches', - 'ge_num_of_se_switches_due_to_donut', - 'ge_num_of_se_switches_due_to_patch_accum', - 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', - 'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done', - 'ge_se1_te11_starved_on_hs_done', - 'ge_se2_te11_starved_on_hs_done', - 'ge_se3_te11_starved_on_hs_done', - 'ge_se4_te11_starved_on_hs_done', - 'ge_se5_te11_starved_on_hs_done', - 'ge_se6_te11_starved_on_hs_done', - 'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims', - 'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim', - 'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall', - 'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups', - 'ge_se_reused_es_indices', 'ge_se_sclk_input_vld', - 'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld', - 'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov', - 'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy', - 'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont', - 'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled', - 'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid', - 'ge_se_spi_gssubgrp_event_window_active', - 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', - 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', - 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', - 'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event', - 'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov', - 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', - 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', - 'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall', - 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall', - 'ge_te11_compactor_starved', 'ge_te11_con_stall', - 'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel', - 'ge_tf_ret_data_stalling_hs_done', 'hdp_flush_cmd', 'int32_t', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', - 'int_sel__mec_release_mem__none', - 'int_sel__mec_release_mem__send_data_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_only', - 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 'ixDIDT_DB_CTRL0', 'ixDIDT_DB_CTRL1', 'ixDIDT_DB_CTRL2', - 'ixDIDT_DB_CTRL3', 'ixDIDT_DB_CTRL_OCP', 'ixDIDT_DB_EDC_CTRL', - 'ixDIDT_DB_EDC_OVERFLOW', 'ixDIDT_DB_EDC_PCC_PERF_COUNTER', - 'ixDIDT_DB_EDC_ROLLING_POWER_DELTA', - 'ixDIDT_DB_EDC_STALL_DELAY_1', 'ixDIDT_DB_EDC_STALL_PATTERN_1_2', - 'ixDIDT_DB_EDC_STALL_PATTERN_3_4', - 'ixDIDT_DB_EDC_STALL_PATTERN_5_6', - 'ixDIDT_DB_EDC_STALL_PATTERN_7', 'ixDIDT_DB_EDC_STATUS', - 'ixDIDT_DB_EDC_THRESHOLD', 'ixDIDT_DB_EDC_TIMER_PERIOD', - 'ixDIDT_DB_MPD_SCALE_FACTOR', 'ixDIDT_DB_STALL_AUTO_RELEASE_CTRL', - 'ixDIDT_DB_STALL_CTRL', 'ixDIDT_DB_STALL_EVENT_COUNTER', - 'ixDIDT_DB_STALL_PATTERN_1_2', 'ixDIDT_DB_STALL_PATTERN_3_4', - 'ixDIDT_DB_STALL_PATTERN_5_6', 'ixDIDT_DB_STALL_PATTERN_7', - 'ixDIDT_DB_STALL_RELEASE_CNTL0', 'ixDIDT_DB_STALL_RELEASE_CNTL1', - 'ixDIDT_DB_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_DB_THROTTLE_CTRL', - 'ixDIDT_DB_TUNING_CTRL', 'ixDIDT_DB_WEIGHT0_3', - 'ixDIDT_DB_WEIGHT4_7', 'ixDIDT_DB_WEIGHT8_11', 'ixDIDT_SQ_CTRL0', - 'ixDIDT_SQ_CTRL1', 'ixDIDT_SQ_CTRL2', 'ixDIDT_SQ_CTRL3', - 'ixDIDT_SQ_CTRL_OCP', 'ixDIDT_SQ_EDC_CTRL', - 'ixDIDT_SQ_EDC_OVERFLOW', 'ixDIDT_SQ_EDC_PCC_PERF_COUNTER', - 'ixDIDT_SQ_EDC_ROLLING_POWER_DELTA', - 'ixDIDT_SQ_EDC_STALL_DELAY_1', 'ixDIDT_SQ_EDC_STALL_DELAY_2', - 'ixDIDT_SQ_EDC_STALL_DELAY_3', 'ixDIDT_SQ_EDC_STALL_PATTERN_1_2', - 'ixDIDT_SQ_EDC_STALL_PATTERN_3_4', - 'ixDIDT_SQ_EDC_STALL_PATTERN_5_6', - 'ixDIDT_SQ_EDC_STALL_PATTERN_7', 'ixDIDT_SQ_EDC_STATUS', - 'ixDIDT_SQ_EDC_THRESHOLD', 'ixDIDT_SQ_EDC_TIMER_PERIOD', - 'ixDIDT_SQ_MPD_SCALE_FACTOR', 'ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL', - 'ixDIDT_SQ_STALL_CTRL', 'ixDIDT_SQ_STALL_EVENT_COUNTER', - 'ixDIDT_SQ_STALL_PATTERN_1_2', 'ixDIDT_SQ_STALL_PATTERN_3_4', - 'ixDIDT_SQ_STALL_PATTERN_5_6', 'ixDIDT_SQ_STALL_PATTERN_7', - 'ixDIDT_SQ_STALL_RELEASE_CNTL0', 'ixDIDT_SQ_STALL_RELEASE_CNTL1', - 'ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_SQ_THROTTLE_CTRL', - 'ixDIDT_SQ_TUNING_CTRL', 'ixDIDT_SQ_WEIGHT0_3', - 'ixDIDT_SQ_WEIGHT4_7', 'ixDIDT_SQ_WEIGHT8_11', 'ixDIDT_TCP_CTRL0', - 'ixDIDT_TCP_CTRL1', 'ixDIDT_TCP_CTRL2', 'ixDIDT_TCP_CTRL3', - 'ixDIDT_TCP_CTRL_OCP', 'ixDIDT_TCP_EDC_CTRL', - 'ixDIDT_TCP_EDC_OVERFLOW', 'ixDIDT_TCP_EDC_PCC_PERF_COUNTER', - 'ixDIDT_TCP_EDC_ROLLING_POWER_DELTA', - 'ixDIDT_TCP_EDC_STALL_DELAY_1', 'ixDIDT_TCP_EDC_STALL_DELAY_2', - 'ixDIDT_TCP_EDC_STALL_DELAY_3', - 'ixDIDT_TCP_EDC_STALL_PATTERN_1_2', - 'ixDIDT_TCP_EDC_STALL_PATTERN_3_4', - 'ixDIDT_TCP_EDC_STALL_PATTERN_5_6', - 'ixDIDT_TCP_EDC_STALL_PATTERN_7', 'ixDIDT_TCP_EDC_STATUS', - 'ixDIDT_TCP_EDC_THRESHOLD', 'ixDIDT_TCP_EDC_TIMER_PERIOD', - 'ixDIDT_TCP_MPD_SCALE_FACTOR', - 'ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL', 'ixDIDT_TCP_STALL_CTRL', - 'ixDIDT_TCP_STALL_EVENT_COUNTER', 'ixDIDT_TCP_STALL_PATTERN_1_2', - 'ixDIDT_TCP_STALL_PATTERN_3_4', 'ixDIDT_TCP_STALL_PATTERN_5_6', - 'ixDIDT_TCP_STALL_PATTERN_7', 'ixDIDT_TCP_STALL_RELEASE_CNTL0', - 'ixDIDT_TCP_STALL_RELEASE_CNTL1', - 'ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS', - 'ixDIDT_TCP_THROTTLE_CTRL', 'ixDIDT_TCP_TUNING_CTRL', - 'ixDIDT_TCP_WEIGHT0_3', 'ixDIDT_TCP_WEIGHT4_7', - 'ixDIDT_TCP_WEIGHT8_11', 'ixDIDT_TD_CTRL0', 'ixDIDT_TD_CTRL1', - 'ixDIDT_TD_CTRL2', 'ixDIDT_TD_CTRL3', 'ixDIDT_TD_CTRL_OCP', - 'ixDIDT_TD_EDC_CTRL', 'ixDIDT_TD_EDC_OVERFLOW', - 'ixDIDT_TD_EDC_PCC_PERF_COUNTER', - 'ixDIDT_TD_EDC_ROLLING_POWER_DELTA', - 'ixDIDT_TD_EDC_STALL_DELAY_1', 'ixDIDT_TD_EDC_STALL_DELAY_2', - 'ixDIDT_TD_EDC_STALL_DELAY_3', 'ixDIDT_TD_EDC_STALL_PATTERN_1_2', - 'ixDIDT_TD_EDC_STALL_PATTERN_3_4', - 'ixDIDT_TD_EDC_STALL_PATTERN_5_6', - 'ixDIDT_TD_EDC_STALL_PATTERN_7', 'ixDIDT_TD_EDC_STATUS', - 'ixDIDT_TD_EDC_THRESHOLD', 'ixDIDT_TD_EDC_TIMER_PERIOD', - 'ixDIDT_TD_MPD_SCALE_FACTOR', 'ixDIDT_TD_STALL_AUTO_RELEASE_CTRL', - 'ixDIDT_TD_STALL_CTRL', 'ixDIDT_TD_STALL_EVENT_COUNTER', - 'ixDIDT_TD_STALL_PATTERN_1_2', 'ixDIDT_TD_STALL_PATTERN_3_4', - 'ixDIDT_TD_STALL_PATTERN_5_6', 'ixDIDT_TD_STALL_PATTERN_7', - 'ixDIDT_TD_STALL_RELEASE_CNTL0', 'ixDIDT_TD_STALL_RELEASE_CNTL1', - 'ixDIDT_TD_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_TD_THROTTLE_CTRL', - 'ixDIDT_TD_TUNING_CTRL', 'ixDIDT_TD_WEIGHT0_3', - 'ixDIDT_TD_WEIGHT4_7', 'ixDIDT_TD_WEIGHT8_11', - 'ixEDC_STRETCH_NUM_PERF_COUNTER', 'ixEDC_STRETCH_PERF_COUNTER', - 'ixEDC_UNSTRETCH_PERF_COUNTER', 'ixFIXED_PATTERN_PERF_COUNTER_1', - 'ixFIXED_PATTERN_PERF_COUNTER_10', - 'ixFIXED_PATTERN_PERF_COUNTER_2', - 'ixFIXED_PATTERN_PERF_COUNTER_3', - 'ixFIXED_PATTERN_PERF_COUNTER_4', - 'ixFIXED_PATTERN_PERF_COUNTER_5', - 'ixFIXED_PATTERN_PERF_COUNTER_6', - 'ixFIXED_PATTERN_PERF_COUNTER_7', - 'ixFIXED_PATTERN_PERF_COUNTER_8', - 'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_BCI0', - 'ixGC_CAC_ACC_BCI1', 'ixGC_CAC_ACC_CB0', 'ixGC_CAC_ACC_CB1', - 'ixGC_CAC_ACC_CB2', 'ixGC_CAC_ACC_CB3', 'ixGC_CAC_ACC_CB4', - 'ixGC_CAC_ACC_CB5', 'ixGC_CAC_ACC_CB6', 'ixGC_CAC_ACC_CB7', - 'ixGC_CAC_ACC_CB8', 'ixGC_CAC_ACC_CB9', 'ixGC_CAC_ACC_CHC0', - 'ixGC_CAC_ACC_CHC1', 'ixGC_CAC_ACC_CHC2', 'ixGC_CAC_ACC_CP0', - 'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_CU0', - 'ixGC_CAC_ACC_DB0', 'ixGC_CAC_ACC_DB1', 'ixGC_CAC_ACC_DB2', - 'ixGC_CAC_ACC_DB3', 'ixGC_CAC_ACC_DB4', 'ixGC_CAC_ACC_DB5', - 'ixGC_CAC_ACC_DB6', 'ixGC_CAC_ACC_DB7', 'ixGC_CAC_ACC_DB8', - 'ixGC_CAC_ACC_DB9', 'ixGC_CAC_ACC_EA0', 'ixGC_CAC_ACC_EA1', - 'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3', 'ixGC_CAC_ACC_EA4', - 'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0', 'ixGC_CAC_ACC_GDS1', - 'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3', 'ixGC_CAC_ACC_GDS4', - 'ixGC_CAC_ACC_GDS5', 'ixGC_CAC_ACC_GDS6', 'ixGC_CAC_ACC_GE0', - 'ixGC_CAC_ACC_GE1', 'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11', - 'ixGC_CAC_ACC_GE12', 'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14', - 'ixGC_CAC_ACC_GE15', 'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17', - 'ixGC_CAC_ACC_GE18', 'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2', - 'ixGC_CAC_ACC_GE20', 'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4', - 'ixGC_CAC_ACC_GE5', 'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7', - 'ixGC_CAC_ACC_GE8', 'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL1C0', - 'ixGC_CAC_ACC_GL1C1', 'ixGC_CAC_ACC_GL1C2', 'ixGC_CAC_ACC_GL1C3', - 'ixGC_CAC_ACC_GL1C4', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1', - 'ixGC_CAC_ACC_GL2C2', 'ixGC_CAC_ACC_GL2C3', 'ixGC_CAC_ACC_GL2C4', - 'ixGC_CAC_ACC_GUS0', 'ixGC_CAC_ACC_GUS1', 'ixGC_CAC_ACC_GUS2', - 'ixGC_CAC_ACC_LDS0', 'ixGC_CAC_ACC_LDS1', 'ixGC_CAC_ACC_LDS2', - 'ixGC_CAC_ACC_LDS3', 'ixGC_CAC_ACC_LDS4', 'ixGC_CAC_ACC_LDS5', - 'ixGC_CAC_ACC_LDS6', 'ixGC_CAC_ACC_LDS7', 'ixGC_CAC_ACC_LDS8', - 'ixGC_CAC_ACC_PA0', 'ixGC_CAC_ACC_PA1', 'ixGC_CAC_ACC_PA2', - 'ixGC_CAC_ACC_PA3', 'ixGC_CAC_ACC_PA4', 'ixGC_CAC_ACC_PA5', - 'ixGC_CAC_ACC_PA6', 'ixGC_CAC_ACC_PA7', 'ixGC_CAC_ACC_PC0', - 'ixGC_CAC_ACC_PH0', 'ixGC_CAC_ACC_PH1', 'ixGC_CAC_ACC_PH2', - 'ixGC_CAC_ACC_PH3', 'ixGC_CAC_ACC_PH4', 'ixGC_CAC_ACC_PH5', - 'ixGC_CAC_ACC_PH6', 'ixGC_CAC_ACC_PH7', 'ixGC_CAC_ACC_PMM0', - 'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_RMI0', 'ixGC_CAC_ACC_RMI1', - 'ixGC_CAC_ACC_RMI2', 'ixGC_CAC_ACC_RMI3', 'ixGC_CAC_ACC_SC0', - 'ixGC_CAC_ACC_SC1', 'ixGC_CAC_ACC_SC2', 'ixGC_CAC_ACC_SC3', - 'ixGC_CAC_ACC_SC4', 'ixGC_CAC_ACC_SC5', 'ixGC_CAC_ACC_SC6', - 'ixGC_CAC_ACC_SC7', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1', - 'ixGC_CAC_ACC_SDMA10', 'ixGC_CAC_ACC_SDMA11', - 'ixGC_CAC_ACC_SDMA2', 'ixGC_CAC_ACC_SDMA3', 'ixGC_CAC_ACC_SDMA4', - 'ixGC_CAC_ACC_SDMA5', 'ixGC_CAC_ACC_SDMA6', 'ixGC_CAC_ACC_SDMA7', - 'ixGC_CAC_ACC_SDMA8', 'ixGC_CAC_ACC_SDMA9', - 'ixGC_CAC_ACC_SP0_LOWER', 'ixGC_CAC_ACC_SP0_UPPER', - 'ixGC_CAC_ACC_SP1_LOWER', 'ixGC_CAC_ACC_SP1_UPPER', - 'ixGC_CAC_ACC_SP2_LOWER', 'ixGC_CAC_ACC_SP2_UPPER', - 'ixGC_CAC_ACC_SPI0', 'ixGC_CAC_ACC_SPI1', 'ixGC_CAC_ACC_SPI2', - 'ixGC_CAC_ACC_SPI3', 'ixGC_CAC_ACC_SPI4', 'ixGC_CAC_ACC_SPI5', - 'ixGC_CAC_ACC_SQ0_LOWER', 'ixGC_CAC_ACC_SQ0_UPPER', - 'ixGC_CAC_ACC_SQ1_LOWER', 'ixGC_CAC_ACC_SQ1_UPPER', - 'ixGC_CAC_ACC_SQ2_LOWER', 'ixGC_CAC_ACC_SQ2_UPPER', - 'ixGC_CAC_ACC_SQ3_LOWER', 'ixGC_CAC_ACC_SQ3_UPPER', - 'ixGC_CAC_ACC_SQ4_LOWER', 'ixGC_CAC_ACC_SQ4_UPPER', - 'ixGC_CAC_ACC_SQ5_LOWER', 'ixGC_CAC_ACC_SQ5_UPPER', - 'ixGC_CAC_ACC_SQ6_LOWER', 'ixGC_CAC_ACC_SQ6_UPPER', - 'ixGC_CAC_ACC_SQ7_LOWER', 'ixGC_CAC_ACC_SQ7_UPPER', - 'ixGC_CAC_ACC_SQ8_LOWER', 'ixGC_CAC_ACC_SQ8_UPPER', - 'ixGC_CAC_ACC_SQC0', 'ixGC_CAC_ACC_SQC1', 'ixGC_CAC_ACC_SQC2', - 'ixGC_CAC_ACC_SX0', 'ixGC_CAC_ACC_SXRB0', 'ixGC_CAC_ACC_TA0', - 'ixGC_CAC_ACC_TCP0', 'ixGC_CAC_ACC_TCP1', 'ixGC_CAC_ACC_TCP2', - 'ixGC_CAC_ACC_TCP3', 'ixGC_CAC_ACC_TCP4', 'ixGC_CAC_ACC_TCP5', - 'ixGC_CAC_ACC_TCP6', 'ixGC_CAC_ACC_TCP7', 'ixGC_CAC_ACC_TD0', - 'ixGC_CAC_ACC_TD1', 'ixGC_CAC_ACC_TD10', 'ixGC_CAC_ACC_TD2', - 'ixGC_CAC_ACC_TD3', 'ixGC_CAC_ACC_TD4', 'ixGC_CAC_ACC_TD5', - 'ixGC_CAC_ACC_TD6', 'ixGC_CAC_ACC_TD7', 'ixGC_CAC_ACC_TD8', - 'ixGC_CAC_ACC_TD9', 'ixGC_CAC_ACC_UTCL10', - 'ixGC_CAC_ACC_UTCL2_ATCL20', 'ixGC_CAC_ACC_UTCL2_ATCL21', - 'ixGC_CAC_ACC_UTCL2_ATCL22', 'ixGC_CAC_ACC_UTCL2_ATCL23', - 'ixGC_CAC_ACC_UTCL2_ATCL24', 'ixGC_CAC_ACC_UTCL2_ROUTER0', - 'ixGC_CAC_ACC_UTCL2_ROUTER1', 'ixGC_CAC_ACC_UTCL2_ROUTER2', - 'ixGC_CAC_ACC_UTCL2_ROUTER3', 'ixGC_CAC_ACC_UTCL2_ROUTER4', - 'ixGC_CAC_ACC_UTCL2_ROUTER5', 'ixGC_CAC_ACC_UTCL2_ROUTER6', - 'ixGC_CAC_ACC_UTCL2_ROUTER7', 'ixGC_CAC_ACC_UTCL2_ROUTER8', - 'ixGC_CAC_ACC_UTCL2_ROUTER9', 'ixGC_CAC_ACC_UTCL2_VML20', - 'ixGC_CAC_ACC_UTCL2_VML21', 'ixGC_CAC_ACC_UTCL2_VML22', - 'ixGC_CAC_ACC_UTCL2_VML23', 'ixGC_CAC_ACC_UTCL2_VML24', - 'ixGC_CAC_ACC_UTCL2_WALKER0', 'ixGC_CAC_ACC_UTCL2_WALKER1', - 'ixGC_CAC_ACC_UTCL2_WALKER2', 'ixGC_CAC_ACC_UTCL2_WALKER3', - 'ixGC_CAC_ACC_UTCL2_WALKER4', 'ixGC_CAC_CNTL', 'ixGC_CAC_ID', - 'ixGC_CAC_OVRD_BCI', 'ixGC_CAC_OVRD_CB', 'ixGC_CAC_OVRD_CHC', - 'ixGC_CAC_OVRD_CP', 'ixGC_CAC_OVRD_CU', 'ixGC_CAC_OVRD_DB', - 'ixGC_CAC_OVRD_EA', 'ixGC_CAC_OVRD_GDS', 'ixGC_CAC_OVRD_GE', - 'ixGC_CAC_OVRD_GE_HI', 'ixGC_CAC_OVRD_GL1C', 'ixGC_CAC_OVRD_GL2C', - 'ixGC_CAC_OVRD_GUS', 'ixGC_CAC_OVRD_LDS', 'ixGC_CAC_OVRD_PA', - 'ixGC_CAC_OVRD_PC', 'ixGC_CAC_OVRD_PH', 'ixGC_CAC_OVRD_PMM', - 'ixGC_CAC_OVRD_RLC', 'ixGC_CAC_OVRD_RMI', 'ixGC_CAC_OVRD_SC', - 'ixGC_CAC_OVRD_SDMA', 'ixGC_CAC_OVRD_SP', 'ixGC_CAC_OVRD_SPI', - 'ixGC_CAC_OVRD_SQ', 'ixGC_CAC_OVRD_SQC', 'ixGC_CAC_OVRD_SX', - 'ixGC_CAC_OVRD_SXRB', 'ixGC_CAC_OVRD_TA', 'ixGC_CAC_OVRD_TCP', - 'ixGC_CAC_OVRD_TD', 'ixGC_CAC_OVRD_UTCL1', - 'ixGC_CAC_OVRD_UTCL2_ATCL2', 'ixGC_CAC_OVRD_UTCL2_ROUTER', - 'ixGC_CAC_OVRD_UTCL2_VML2', 'ixGC_CAC_OVRD_UTCL2_WALKER', - 'ixGC_CAC_OVR_SEL', 'ixGC_CAC_OVR_VAL', 'ixGC_CAC_WEIGHT_BCI_0', - 'ixGC_CAC_WEIGHT_CB_0', 'ixGC_CAC_WEIGHT_CB_1', - 'ixGC_CAC_WEIGHT_CB_2', 'ixGC_CAC_WEIGHT_CB_3', - 'ixGC_CAC_WEIGHT_CB_4', 'ixGC_CAC_WEIGHT_CHC_0', - 'ixGC_CAC_WEIGHT_CHC_1', 'ixGC_CAC_WEIGHT_CP_0', - 'ixGC_CAC_WEIGHT_CP_1', 'ixGC_CAC_WEIGHT_CU_0', - 'ixGC_CAC_WEIGHT_DB_0', 'ixGC_CAC_WEIGHT_DB_1', - 'ixGC_CAC_WEIGHT_DB_2', 'ixGC_CAC_WEIGHT_DB_3', - 'ixGC_CAC_WEIGHT_DB_4', 'ixGC_CAC_WEIGHT_EA_0', - 'ixGC_CAC_WEIGHT_EA_1', 'ixGC_CAC_WEIGHT_EA_2', - 'ixGC_CAC_WEIGHT_GDS_0', 'ixGC_CAC_WEIGHT_GDS_1', - 'ixGC_CAC_WEIGHT_GDS_2', 'ixGC_CAC_WEIGHT_GE_0', - 'ixGC_CAC_WEIGHT_GE_1', 'ixGC_CAC_WEIGHT_GE_10', - 'ixGC_CAC_WEIGHT_GE_2', 'ixGC_CAC_WEIGHT_GE_3', - 'ixGC_CAC_WEIGHT_GE_4', 'ixGC_CAC_WEIGHT_GE_5', - 'ixGC_CAC_WEIGHT_GE_6', 'ixGC_CAC_WEIGHT_GE_7', - 'ixGC_CAC_WEIGHT_GE_8', 'ixGC_CAC_WEIGHT_GE_9', - 'ixGC_CAC_WEIGHT_GL1C_0', 'ixGC_CAC_WEIGHT_GL1C_1', - 'ixGC_CAC_WEIGHT_GL1C_2', 'ixGC_CAC_WEIGHT_GL2C_0', - 'ixGC_CAC_WEIGHT_GL2C_1', 'ixGC_CAC_WEIGHT_GL2C_2', - 'ixGC_CAC_WEIGHT_GUS_0', 'ixGC_CAC_WEIGHT_GUS_1', - 'ixGC_CAC_WEIGHT_LDS_0', 'ixGC_CAC_WEIGHT_LDS_1', - 'ixGC_CAC_WEIGHT_LDS_2', 'ixGC_CAC_WEIGHT_LDS_3', - 'ixGC_CAC_WEIGHT_LDS_4', 'ixGC_CAC_WEIGHT_PA_0', - 'ixGC_CAC_WEIGHT_PA_1', 'ixGC_CAC_WEIGHT_PA_2', - 'ixGC_CAC_WEIGHT_PA_3', 'ixGC_CAC_WEIGHT_PC_0', - 'ixGC_CAC_WEIGHT_PH_0', 'ixGC_CAC_WEIGHT_PH_1', - 'ixGC_CAC_WEIGHT_PH_2', 'ixGC_CAC_WEIGHT_PH_3', - 'ixGC_CAC_WEIGHT_PMM_0', 'ixGC_CAC_WEIGHT_RLC_0', - 'ixGC_CAC_WEIGHT_RMI_0', 'ixGC_CAC_WEIGHT_RMI_1', - 'ixGC_CAC_WEIGHT_SC_0', 'ixGC_CAC_WEIGHT_SC_1', - 'ixGC_CAC_WEIGHT_SC_2', 'ixGC_CAC_WEIGHT_SC_3', - 'ixGC_CAC_WEIGHT_SDMA_0', 'ixGC_CAC_WEIGHT_SDMA_1', - 'ixGC_CAC_WEIGHT_SDMA_2', 'ixGC_CAC_WEIGHT_SDMA_3', - 'ixGC_CAC_WEIGHT_SDMA_4', 'ixGC_CAC_WEIGHT_SDMA_5', - 'ixGC_CAC_WEIGHT_SPI_0', 'ixGC_CAC_WEIGHT_SPI_1', - 'ixGC_CAC_WEIGHT_SPI_2', 'ixGC_CAC_WEIGHT_SP_0', - 'ixGC_CAC_WEIGHT_SP_1', 'ixGC_CAC_WEIGHT_SQC_0', - 'ixGC_CAC_WEIGHT_SQC_1', 'ixGC_CAC_WEIGHT_SQ_0', - 'ixGC_CAC_WEIGHT_SQ_1', 'ixGC_CAC_WEIGHT_SQ_2', - 'ixGC_CAC_WEIGHT_SQ_3', 'ixGC_CAC_WEIGHT_SXRB_0', - 'ixGC_CAC_WEIGHT_SX_0', 'ixGC_CAC_WEIGHT_TA_0', - 'ixGC_CAC_WEIGHT_TCP_0', 'ixGC_CAC_WEIGHT_TCP_1', - 'ixGC_CAC_WEIGHT_TCP_2', 'ixGC_CAC_WEIGHT_TCP_3', - 'ixGC_CAC_WEIGHT_TD_0', 'ixGC_CAC_WEIGHT_TD_1', - 'ixGC_CAC_WEIGHT_TD_2', 'ixGC_CAC_WEIGHT_TD_3', - 'ixGC_CAC_WEIGHT_TD_4', 'ixGC_CAC_WEIGHT_TD_5', - 'ixGC_CAC_WEIGHT_UTCL1_0', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_0', - 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_1', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_2', - 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_0', - 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_1', - 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_2', - 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_3', - 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_4', 'ixGC_CAC_WEIGHT_UTCL2_VML2_0', - 'ixGC_CAC_WEIGHT_UTCL2_VML2_1', 'ixGC_CAC_WEIGHT_UTCL2_VML2_2', - 'ixGC_CAC_WEIGHT_UTCL2_WALKER_0', - 'ixGC_CAC_WEIGHT_UTCL2_WALKER_1', - 'ixGC_CAC_WEIGHT_UTCL2_WALKER_2', 'ixGLB_ATCL2_SAMPLEDELAY', - 'ixGLB_CHA_SAMPLEDELAY', 'ixGLB_CHC0_SAMPLEDELAY', - 'ixGLB_CHC1_SAMPLEDELAY', 'ixGLB_CHC2_SAMPLEDELAY', - 'ixGLB_CHC3_SAMPLEDELAY', 'ixGLB_CHCG_SAMPLEDELAY', - 'ixGLB_CPC_SAMPLEDELAY', 'ixGLB_CPF_SAMPLEDELAY', - 'ixGLB_CPG_SAMPLEDELAY', 'ixGLB_EA0_SAMPLEDELAY', - 'ixGLB_EA10_SAMPLEDELAY', 'ixGLB_EA11_SAMPLEDELAY', - 'ixGLB_EA12_SAMPLEDELAY', 'ixGLB_EA13_SAMPLEDELAY', - 'ixGLB_EA14_SAMPLEDELAY', 'ixGLB_EA15_SAMPLEDELAY', - 'ixGLB_EA1_SAMPLEDELAY', 'ixGLB_EA2_SAMPLEDELAY', - 'ixGLB_EA3_SAMPLEDELAY', 'ixGLB_EA4_SAMPLEDELAY', - 'ixGLB_EA5_SAMPLEDELAY', 'ixGLB_EA6_SAMPLEDELAY', - 'ixGLB_EA7_SAMPLEDELAY', 'ixGLB_EA8_SAMPLEDELAY', - 'ixGLB_EA9_SAMPLEDELAY', 'ixGLB_GCR_SAMPLEDELAY', - 'ixGLB_GDS_SAMPLEDELAY', 'ixGLB_GE1_SAMPLEDELAY', - 'ixGLB_GE2DIST_SAMPLEDELAY', 'ixGLB_GE2SE0_SAMPLEDELAY', - 'ixGLB_GE2SE1_SAMPLEDELAY', 'ixGLB_GE2SE2_SAMPLEDELAY', - 'ixGLB_GE2SE3_SAMPLEDELAY', 'ixGLB_GL2A0_SAMPLEDELAY', - 'ixGLB_GL2A1_SAMPLEDELAY', 'ixGLB_GL2A2_SAMPLEDELAY', - 'ixGLB_GL2A3_SAMPLEDELAY', 'ixGLB_GL2C0_SAMPLEDELAY', - 'ixGLB_GL2C10_SAMPLEDELAY', 'ixGLB_GL2C11_SAMPLEDELAY', - 'ixGLB_GL2C12_SAMPLEDELAY', 'ixGLB_GL2C13_SAMPLEDELAY', - 'ixGLB_GL2C14_SAMPLEDELAY', 'ixGLB_GL2C15_SAMPLEDELAY', - 'ixGLB_GL2C1_SAMPLEDELAY', 'ixGLB_GL2C2_SAMPLEDELAY', - 'ixGLB_GL2C3_SAMPLEDELAY', 'ixGLB_GL2C4_SAMPLEDELAY', - 'ixGLB_GL2C5_SAMPLEDELAY', 'ixGLB_GL2C6_SAMPLEDELAY', - 'ixGLB_GL2C7_SAMPLEDELAY', 'ixGLB_GL2C8_SAMPLEDELAY', - 'ixGLB_GL2C9_SAMPLEDELAY', 'ixGLB_GUS_SAMPLEDELAY', - 'ixGLB_PH_SAMPLEDELAY', 'ixGLB_SDMA0_SAMPLEDELAY', - 'ixGLB_SDMA1_SAMPLEDELAY', 'ixGLB_SDMA2_SAMPLEDELAY', - 'ixGLB_SDMA3_SAMPLEDELAY', 'ixGLB_VML2_SAMPLEDELAY', - 'ixHW_LUT_UPDATE_STATUS', 'ixPCC_PWRBRK_HYSTERESIS_CTRL', - 'ixPCC_STALL_PATTERN_1_2', 'ixPCC_STALL_PATTERN_3_4', - 'ixPCC_STALL_PATTERN_5_6', 'ixPCC_STALL_PATTERN_7', - 'ixPCC_STALL_PATTERN_CTRL', 'ixPWRBRK_RELEASE_TO_STALL_LUT_17_20', - 'ixPWRBRK_RELEASE_TO_STALL_LUT_1_8', - 'ixPWRBRK_RELEASE_TO_STALL_LUT_9_16', - 'ixPWRBRK_STALL_PATTERN_1_2', 'ixPWRBRK_STALL_PATTERN_3_4', - 'ixPWRBRK_STALL_PATTERN_5_6', 'ixPWRBRK_STALL_PATTERN_7', - 'ixPWRBRK_STALL_PATTERN_CTRL', - 'ixPWRBRK_STALL_TO_RELEASE_LUT_1_4', - 'ixPWRBRK_STALL_TO_RELEASE_LUT_5_7', - 'ixRELEASE_TO_STALL_LUT_17_20', 'ixRELEASE_TO_STALL_LUT_1_8', - 'ixRELEASE_TO_STALL_LUT_9_16', 'ixRTAVFS_REG0', 'ixRTAVFS_REG1', - 'ixRTAVFS_REG10', 'ixRTAVFS_REG100', 'ixRTAVFS_REG101', - 'ixRTAVFS_REG102', 'ixRTAVFS_REG103', 'ixRTAVFS_REG104', - 'ixRTAVFS_REG105', 'ixRTAVFS_REG106', 'ixRTAVFS_REG107', - 'ixRTAVFS_REG108', 'ixRTAVFS_REG109', 'ixRTAVFS_REG11', - 'ixRTAVFS_REG110', 'ixRTAVFS_REG111', 'ixRTAVFS_REG112', - 'ixRTAVFS_REG113', 'ixRTAVFS_REG114', 'ixRTAVFS_REG115', - 'ixRTAVFS_REG116', 'ixRTAVFS_REG117', 'ixRTAVFS_REG118', - 'ixRTAVFS_REG119', 'ixRTAVFS_REG12', 'ixRTAVFS_REG120', - 'ixRTAVFS_REG121', 'ixRTAVFS_REG122', 'ixRTAVFS_REG123', - 'ixRTAVFS_REG124', 'ixRTAVFS_REG125', 'ixRTAVFS_REG126', - 'ixRTAVFS_REG127', 'ixRTAVFS_REG128', 'ixRTAVFS_REG129', - 'ixRTAVFS_REG13', 'ixRTAVFS_REG130', 'ixRTAVFS_REG131', - 'ixRTAVFS_REG132', 'ixRTAVFS_REG133', 'ixRTAVFS_REG134', - 'ixRTAVFS_REG135', 'ixRTAVFS_REG136', 'ixRTAVFS_REG137', - 'ixRTAVFS_REG138', 'ixRTAVFS_REG139', 'ixRTAVFS_REG14', - 'ixRTAVFS_REG140', 'ixRTAVFS_REG141', 'ixRTAVFS_REG142', - 'ixRTAVFS_REG143', 'ixRTAVFS_REG144', 'ixRTAVFS_REG145', - 'ixRTAVFS_REG146', 'ixRTAVFS_REG147', 'ixRTAVFS_REG148', - 'ixRTAVFS_REG149', 'ixRTAVFS_REG15', 'ixRTAVFS_REG150', - 'ixRTAVFS_REG151', 'ixRTAVFS_REG152', 'ixRTAVFS_REG153', - 'ixRTAVFS_REG154', 'ixRTAVFS_REG155', 'ixRTAVFS_REG156', - 'ixRTAVFS_REG157', 'ixRTAVFS_REG158', 'ixRTAVFS_REG159', - 'ixRTAVFS_REG16', 'ixRTAVFS_REG160', 'ixRTAVFS_REG161', - 'ixRTAVFS_REG162', 'ixRTAVFS_REG163', 'ixRTAVFS_REG164', - 'ixRTAVFS_REG165', 'ixRTAVFS_REG166', 'ixRTAVFS_REG167', - 'ixRTAVFS_REG168', 'ixRTAVFS_REG169', 'ixRTAVFS_REG17', - 'ixRTAVFS_REG170', 'ixRTAVFS_REG171', 'ixRTAVFS_REG172', - 'ixRTAVFS_REG173', 'ixRTAVFS_REG174', 'ixRTAVFS_REG175', - 'ixRTAVFS_REG176', 'ixRTAVFS_REG177', 'ixRTAVFS_REG178', - 'ixRTAVFS_REG179', 'ixRTAVFS_REG18', 'ixRTAVFS_REG180', - 'ixRTAVFS_REG181', 'ixRTAVFS_REG182', 'ixRTAVFS_REG183', - 'ixRTAVFS_REG184', 'ixRTAVFS_REG185', 'ixRTAVFS_REG186', - 'ixRTAVFS_REG187', 'ixRTAVFS_REG188', 'ixRTAVFS_REG189', - 'ixRTAVFS_REG19', 'ixRTAVFS_REG190', 'ixRTAVFS_REG191', - 'ixRTAVFS_REG192', 'ixRTAVFS_REG193', 'ixRTAVFS_REG194', - 'ixRTAVFS_REG2', 'ixRTAVFS_REG20', 'ixRTAVFS_REG21', - 'ixRTAVFS_REG22', 'ixRTAVFS_REG23', 'ixRTAVFS_REG24', - 'ixRTAVFS_REG25', 'ixRTAVFS_REG26', 'ixRTAVFS_REG27', - 'ixRTAVFS_REG28', 'ixRTAVFS_REG29', 'ixRTAVFS_REG3', - 'ixRTAVFS_REG30', 'ixRTAVFS_REG31', 'ixRTAVFS_REG32', - 'ixRTAVFS_REG33', 'ixRTAVFS_REG34', 'ixRTAVFS_REG35', - 'ixRTAVFS_REG36', 'ixRTAVFS_REG37', 'ixRTAVFS_REG38', - 'ixRTAVFS_REG39', 'ixRTAVFS_REG4', 'ixRTAVFS_REG40', - 'ixRTAVFS_REG41', 'ixRTAVFS_REG42', 'ixRTAVFS_REG43', - 'ixRTAVFS_REG44', 'ixRTAVFS_REG45', 'ixRTAVFS_REG46', - 'ixRTAVFS_REG47', 'ixRTAVFS_REG48', 'ixRTAVFS_REG49', - 'ixRTAVFS_REG5', 'ixRTAVFS_REG50', 'ixRTAVFS_REG51', - 'ixRTAVFS_REG52', 'ixRTAVFS_REG53', 'ixRTAVFS_REG54', - 'ixRTAVFS_REG55', 'ixRTAVFS_REG56', 'ixRTAVFS_REG57', - 'ixRTAVFS_REG58', 'ixRTAVFS_REG59', 'ixRTAVFS_REG6', - 'ixRTAVFS_REG60', 'ixRTAVFS_REG61', 'ixRTAVFS_REG62', - 'ixRTAVFS_REG63', 'ixRTAVFS_REG64', 'ixRTAVFS_REG65', - 'ixRTAVFS_REG66', 'ixRTAVFS_REG67', 'ixRTAVFS_REG68', - 'ixRTAVFS_REG69', 'ixRTAVFS_REG7', 'ixRTAVFS_REG70', - 'ixRTAVFS_REG71', 'ixRTAVFS_REG72', 'ixRTAVFS_REG73', - 'ixRTAVFS_REG74', 'ixRTAVFS_REG75', 'ixRTAVFS_REG76', - 'ixRTAVFS_REG77', 'ixRTAVFS_REG78', 'ixRTAVFS_REG79', - 'ixRTAVFS_REG8', 'ixRTAVFS_REG80', 'ixRTAVFS_REG81', - 'ixRTAVFS_REG82', 'ixRTAVFS_REG83', 'ixRTAVFS_REG84', - 'ixRTAVFS_REG85', 'ixRTAVFS_REG86', 'ixRTAVFS_REG87', - 'ixRTAVFS_REG88', 'ixRTAVFS_REG89', 'ixRTAVFS_REG9', - 'ixRTAVFS_REG90', 'ixRTAVFS_REG91', 'ixRTAVFS_REG92', - 'ixRTAVFS_REG93', 'ixRTAVFS_REG94', 'ixRTAVFS_REG95', - 'ixRTAVFS_REG96', 'ixRTAVFS_REG97', 'ixRTAVFS_REG98', - 'ixRTAVFS_REG99', 'ixSA_WGP_BLK_ID', 'ixSE_CAC_CNTL', - 'ixSE_CAC_ID', 'ixSE_CAC_OVR_SEL', 'ixSE_CAC_OVR_VAL', - 'ixSE_CBR_SAMPLEDELAY', 'ixSE_DBR_SAMPLEDELAY', - 'ixSE_PA_SAMPLEDELAY', 'ixSE_SA0CB0_SAMPLEDELAY', - 'ixSE_SA0CB1_SAMPLEDELAY', 'ixSE_SA0DB0_SAMPLEDELAY', - 'ixSE_SA0DB1_SAMPLEDELAY', 'ixSE_SA0GL1A_SAMPLEDELAY', - 'ixSE_SA0GL1C0_SAMPLEDELAY', 'ixSE_SA0GL1C1_SAMPLEDELAY', - 'ixSE_SA0GL1C2_SAMPLEDELAY', 'ixSE_SA0GL1C3_SAMPLEDELAY', - 'ixSE_SA0GL1CG_SAMPLEDELAY', 'ixSE_SA0RMI0_SAMPLEDELAY', - 'ixSE_SA0RMI1_SAMPLEDELAY', 'ixSE_SA0SC0_SAMPLEDELAY', - 'ixSE_SA0SC1_SAMPLEDELAY', 'ixSE_SA0SX_SAMPLEDELAY', - 'ixSE_SA0WGP00TA0_SAMPLEDELAY', 'ixSE_SA0WGP00TA1_SAMPLEDELAY', - 'ixSE_SA0WGP00TCP0_SAMPLEDELAY', 'ixSE_SA0WGP00TCP1_SAMPLEDELAY', - 'ixSE_SA0WGP00TD0_SAMPLEDELAY', 'ixSE_SA0WGP00TD1_SAMPLEDELAY', - 'ixSE_SA0WGP01TA0_SAMPLEDELAY', 'ixSE_SA0WGP01TA1_SAMPLEDELAY', - 'ixSE_SA0WGP01TCP0_SAMPLEDELAY', 'ixSE_SA0WGP01TCP1_SAMPLEDELAY', - 'ixSE_SA0WGP01TD0_SAMPLEDELAY', 'ixSE_SA0WGP01TD1_SAMPLEDELAY', - 'ixSE_SA0WGP02TA0_SAMPLEDELAY', 'ixSE_SA0WGP02TA1_SAMPLEDELAY', - 'ixSE_SA0WGP02TCP0_SAMPLEDELAY', 'ixSE_SA0WGP02TCP1_SAMPLEDELAY', - 'ixSE_SA0WGP02TD0_SAMPLEDELAY', 'ixSE_SA0WGP02TD1_SAMPLEDELAY', - 'ixSE_SA0WGP03TA0_SAMPLEDELAY', 'ixSE_SA0WGP03TA1_SAMPLEDELAY', - 'ixSE_SA0WGP03TCP0_SAMPLEDELAY', 'ixSE_SA0WGP03TCP1_SAMPLEDELAY', - 'ixSE_SA0WGP03TD0_SAMPLEDELAY', 'ixSE_SA0WGP03TD1_SAMPLEDELAY', - 'ixSE_SA0WGP04TA0_SAMPLEDELAY', 'ixSE_SA0WGP04TA1_SAMPLEDELAY', - 'ixSE_SA0WGP04TCP0_SAMPLEDELAY', 'ixSE_SA0WGP04TCP1_SAMPLEDELAY', - 'ixSE_SA0WGP04TD0_SAMPLEDELAY', 'ixSE_SA0WGP04TD1_SAMPLEDELAY', - 'ixSE_SA1CB0_SAMPLEDELAY', 'ixSE_SA1CB1_SAMPLEDELAY', - 'ixSE_SA1DB0_SAMPLEDELAY', 'ixSE_SA1DB1_SAMPLEDELAY', - 'ixSE_SA1GL1A_SAMPLEDELAY', 'ixSE_SA1GL1C0_SAMPLEDELAY', - 'ixSE_SA1GL1C1_SAMPLEDELAY', 'ixSE_SA1GL1C2_SAMPLEDELAY', - 'ixSE_SA1GL1C3_SAMPLEDELAY', 'ixSE_SA1GL1CG_SAMPLEDELAY', - 'ixSE_SA1RMI0_SAMPLEDELAY', 'ixSE_SA1RMI1_SAMPLEDELAY', - 'ixSE_SA1SC0_SAMPLEDELAY', 'ixSE_SA1SC1_SAMPLEDELAY', - 'ixSE_SA1SX_SAMPLEDELAY', 'ixSE_SA1WGP00TA0_SAMPLEDELAY', - 'ixSE_SA1WGP00TA1_SAMPLEDELAY', 'ixSE_SA1WGP00TCP0_SAMPLEDELAY', - 'ixSE_SA1WGP00TCP1_SAMPLEDELAY', 'ixSE_SA1WGP00TD0_SAMPLEDELAY', - 'ixSE_SA1WGP00TD1_SAMPLEDELAY', 'ixSE_SA1WGP01TA0_SAMPLEDELAY', - 'ixSE_SA1WGP01TA1_SAMPLEDELAY', 'ixSE_SA1WGP01TCP0_SAMPLEDELAY', - 'ixSE_SA1WGP01TCP1_SAMPLEDELAY', 'ixSE_SA1WGP01TD0_SAMPLEDELAY', - 'ixSE_SA1WGP01TD1_SAMPLEDELAY', 'ixSE_SA1WGP02TA0_SAMPLEDELAY', - 'ixSE_SA1WGP02TA1_SAMPLEDELAY', 'ixSE_SA1WGP02TCP0_SAMPLEDELAY', - 'ixSE_SA1WGP02TCP1_SAMPLEDELAY', 'ixSE_SA1WGP02TD0_SAMPLEDELAY', - 'ixSE_SA1WGP02TD1_SAMPLEDELAY', 'ixSE_SA1WGP03TA0_SAMPLEDELAY', - 'ixSE_SA1WGP03TA1_SAMPLEDELAY', 'ixSE_SA1WGP03TCP0_SAMPLEDELAY', - 'ixSE_SA1WGP03TCP1_SAMPLEDELAY', 'ixSE_SA1WGP03TD0_SAMPLEDELAY', - 'ixSE_SA1WGP03TD1_SAMPLEDELAY', 'ixSE_SA1WGP04TA0_SAMPLEDELAY', - 'ixSE_SA1WGP04TA1_SAMPLEDELAY', 'ixSE_SA1WGP04TCP0_SAMPLEDELAY', - 'ixSE_SA1WGP04TCP1_SAMPLEDELAY', 'ixSE_SA1WGP04TD0_SAMPLEDELAY', - 'ixSE_SA1WGP04TD1_SAMPLEDELAY', 'ixSE_SPI_SAMPLEDELAY', - 'ixSE_SQG_SAMPLEDELAY', 'ixSQ_DEBUG_CTRL_LOCAL', - 'ixSQ_DEBUG_STS_LOCAL', 'ixSQ_INTERRUPT_WORD_AUTO', - 'ixSQ_INTERRUPT_WORD_ERROR', 'ixSQ_INTERRUPT_WORD_WAVE', - 'ixSQ_WAVE_ACTIVE', 'ixSQ_WAVE_EXEC_HI', 'ixSQ_WAVE_EXEC_LO', - 'ixSQ_WAVE_FLAT_SCRATCH_HI', 'ixSQ_WAVE_FLAT_SCRATCH_LO', - 'ixSQ_WAVE_FLUSH_IB', 'ixSQ_WAVE_GPR_ALLOC', 'ixSQ_WAVE_HW_ID1', - 'ixSQ_WAVE_HW_ID2', 'ixSQ_WAVE_HW_ID_LEGACY', 'ixSQ_WAVE_IB_DBG1', - 'ixSQ_WAVE_IB_STS', 'ixSQ_WAVE_IB_STS2', 'ixSQ_WAVE_INST_DW0', - 'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0', 'ixSQ_WAVE_MODE', - 'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO', 'ixSQ_WAVE_POPS_PACKER', - 'ixSQ_WAVE_SCHED_MODE', 'ixSQ_WAVE_SHADER_CYCLES', - 'ixSQ_WAVE_STATUS', 'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0', - 'ixSQ_WAVE_TTMP1', 'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11', - 'ixSQ_WAVE_TTMP12', 'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14', - 'ixSQ_WAVE_TTMP15', 'ixSQ_WAVE_TTMP2', 'ixSQ_WAVE_TTMP3', - 'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5', 'ixSQ_WAVE_TTMP6', - 'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8', 'ixSQ_WAVE_TTMP9', - 'ixSQ_WAVE_VALID_AND_IDLE', 'ixSQ_WAVE_VGPR_OFFSET', - 'ixSTALL_TO_PWRBRK_LUT_1_4', 'ixSTALL_TO_PWRBRK_LUT_5_7', - 'ixSTALL_TO_RELEASE_LUT_1_4', 'ixSTALL_TO_RELEASE_LUT_5_7', - 'mmCB_BLEND0_CONTROL', 'mmCB_BLEND0_CONTROL_BASE_IDX', - 'mmCB_BLEND1_CONTROL', 'mmCB_BLEND1_CONTROL_BASE_IDX', - 'mmCB_BLEND2_CONTROL', 'mmCB_BLEND2_CONTROL_BASE_IDX', - 'mmCB_BLEND3_CONTROL', 'mmCB_BLEND3_CONTROL_BASE_IDX', - 'mmCB_BLEND4_CONTROL', 'mmCB_BLEND4_CONTROL_BASE_IDX', - 'mmCB_BLEND5_CONTROL', 'mmCB_BLEND5_CONTROL_BASE_IDX', - 'mmCB_BLEND6_CONTROL', 'mmCB_BLEND6_CONTROL_BASE_IDX', - 'mmCB_BLEND7_CONTROL', 'mmCB_BLEND7_CONTROL_BASE_IDX', - 'mmCB_BLEND_ALPHA', 'mmCB_BLEND_ALPHA_BASE_IDX', - 'mmCB_BLEND_BLUE', 'mmCB_BLEND_BLUE_BASE_IDX', 'mmCB_BLEND_GREEN', - 'mmCB_BLEND_GREEN_BASE_IDX', 'mmCB_BLEND_RED', - 'mmCB_BLEND_RED_BASE_IDX', 'mmCB_CACHE_EVICT_POINTS', - 'mmCB_CACHE_EVICT_POINTS_BASE_IDX', 'mmCB_CGTT_SCLK_CTRL', - 'mmCB_CGTT_SCLK_CTRL_BASE_IDX', 'mmCB_COLOR0_ATTRIB', - 'mmCB_COLOR0_ATTRIB2', 'mmCB_COLOR0_ATTRIB2_BASE_IDX', - 'mmCB_COLOR0_ATTRIB3', 'mmCB_COLOR0_ATTRIB3_BASE_IDX', - 'mmCB_COLOR0_ATTRIB_BASE_IDX', 'mmCB_COLOR0_BASE', - 'mmCB_COLOR0_BASE_BASE_IDX', 'mmCB_COLOR0_BASE_EXT', - 'mmCB_COLOR0_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD0', - 'mmCB_COLOR0_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD1', - 'mmCB_COLOR0_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR0_CMASK', - 'mmCB_COLOR0_CMASK_BASE_EXT', - 'mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR0_CMASK_BASE_IDX', 'mmCB_COLOR0_CMASK_SLICE', - 'mmCB_COLOR0_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE', - 'mmCB_COLOR0_DCC_BASE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE_EXT', - 'mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_DCC_CONTROL', - 'mmCB_COLOR0_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR0_FMASK', - 'mmCB_COLOR0_FMASK_BASE_EXT', - 'mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR0_FMASK_BASE_IDX', 'mmCB_COLOR0_FMASK_SLICE', - 'mmCB_COLOR0_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_INFO', - 'mmCB_COLOR0_INFO_BASE_IDX', 'mmCB_COLOR0_PITCH', - 'mmCB_COLOR0_PITCH_BASE_IDX', 'mmCB_COLOR0_SLICE', - 'mmCB_COLOR0_SLICE_BASE_IDX', 'mmCB_COLOR0_VIEW', - 'mmCB_COLOR0_VIEW_BASE_IDX', 'mmCB_COLOR1_ATTRIB', - 'mmCB_COLOR1_ATTRIB2', 'mmCB_COLOR1_ATTRIB2_BASE_IDX', - 'mmCB_COLOR1_ATTRIB3', 'mmCB_COLOR1_ATTRIB3_BASE_IDX', - 'mmCB_COLOR1_ATTRIB_BASE_IDX', 'mmCB_COLOR1_BASE', - 'mmCB_COLOR1_BASE_BASE_IDX', 'mmCB_COLOR1_BASE_EXT', - 'mmCB_COLOR1_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD0', - 'mmCB_COLOR1_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD1', - 'mmCB_COLOR1_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR1_CMASK', - 'mmCB_COLOR1_CMASK_BASE_EXT', - 'mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR1_CMASK_BASE_IDX', 'mmCB_COLOR1_CMASK_SLICE', - 'mmCB_COLOR1_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE', - 'mmCB_COLOR1_DCC_BASE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE_EXT', - 'mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_DCC_CONTROL', - 'mmCB_COLOR1_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR1_FMASK', - 'mmCB_COLOR1_FMASK_BASE_EXT', - 'mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR1_FMASK_BASE_IDX', 'mmCB_COLOR1_FMASK_SLICE', - 'mmCB_COLOR1_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_INFO', - 'mmCB_COLOR1_INFO_BASE_IDX', 'mmCB_COLOR1_PITCH', - 'mmCB_COLOR1_PITCH_BASE_IDX', 'mmCB_COLOR1_SLICE', - 'mmCB_COLOR1_SLICE_BASE_IDX', 'mmCB_COLOR1_VIEW', - 'mmCB_COLOR1_VIEW_BASE_IDX', 'mmCB_COLOR2_ATTRIB', - 'mmCB_COLOR2_ATTRIB2', 'mmCB_COLOR2_ATTRIB2_BASE_IDX', - 'mmCB_COLOR2_ATTRIB3', 'mmCB_COLOR2_ATTRIB3_BASE_IDX', - 'mmCB_COLOR2_ATTRIB_BASE_IDX', 'mmCB_COLOR2_BASE', - 'mmCB_COLOR2_BASE_BASE_IDX', 'mmCB_COLOR2_BASE_EXT', - 'mmCB_COLOR2_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD0', - 'mmCB_COLOR2_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD1', - 'mmCB_COLOR2_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR2_CMASK', - 'mmCB_COLOR2_CMASK_BASE_EXT', - 'mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR2_CMASK_BASE_IDX', 'mmCB_COLOR2_CMASK_SLICE', - 'mmCB_COLOR2_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE', - 'mmCB_COLOR2_DCC_BASE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE_EXT', - 'mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_DCC_CONTROL', - 'mmCB_COLOR2_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR2_FMASK', - 'mmCB_COLOR2_FMASK_BASE_EXT', - 'mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR2_FMASK_BASE_IDX', 'mmCB_COLOR2_FMASK_SLICE', - 'mmCB_COLOR2_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_INFO', - 'mmCB_COLOR2_INFO_BASE_IDX', 'mmCB_COLOR2_PITCH', - 'mmCB_COLOR2_PITCH_BASE_IDX', 'mmCB_COLOR2_SLICE', - 'mmCB_COLOR2_SLICE_BASE_IDX', 'mmCB_COLOR2_VIEW', - 'mmCB_COLOR2_VIEW_BASE_IDX', 'mmCB_COLOR3_ATTRIB', - 'mmCB_COLOR3_ATTRIB2', 'mmCB_COLOR3_ATTRIB2_BASE_IDX', - 'mmCB_COLOR3_ATTRIB3', 'mmCB_COLOR3_ATTRIB3_BASE_IDX', - 'mmCB_COLOR3_ATTRIB_BASE_IDX', 'mmCB_COLOR3_BASE', - 'mmCB_COLOR3_BASE_BASE_IDX', 'mmCB_COLOR3_BASE_EXT', - 'mmCB_COLOR3_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD0', - 'mmCB_COLOR3_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD1', - 'mmCB_COLOR3_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR3_CMASK', - 'mmCB_COLOR3_CMASK_BASE_EXT', - 'mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR3_CMASK_BASE_IDX', 'mmCB_COLOR3_CMASK_SLICE', - 'mmCB_COLOR3_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE', - 'mmCB_COLOR3_DCC_BASE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE_EXT', - 'mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_DCC_CONTROL', - 'mmCB_COLOR3_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR3_FMASK', - 'mmCB_COLOR3_FMASK_BASE_EXT', - 'mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR3_FMASK_BASE_IDX', 'mmCB_COLOR3_FMASK_SLICE', - 'mmCB_COLOR3_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_INFO', - 'mmCB_COLOR3_INFO_BASE_IDX', 'mmCB_COLOR3_PITCH', - 'mmCB_COLOR3_PITCH_BASE_IDX', 'mmCB_COLOR3_SLICE', - 'mmCB_COLOR3_SLICE_BASE_IDX', 'mmCB_COLOR3_VIEW', - 'mmCB_COLOR3_VIEW_BASE_IDX', 'mmCB_COLOR4_ATTRIB', - 'mmCB_COLOR4_ATTRIB2', 'mmCB_COLOR4_ATTRIB2_BASE_IDX', - 'mmCB_COLOR4_ATTRIB3', 'mmCB_COLOR4_ATTRIB3_BASE_IDX', - 'mmCB_COLOR4_ATTRIB_BASE_IDX', 'mmCB_COLOR4_BASE', - 'mmCB_COLOR4_BASE_BASE_IDX', 'mmCB_COLOR4_BASE_EXT', - 'mmCB_COLOR4_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD0', - 'mmCB_COLOR4_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD1', - 'mmCB_COLOR4_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR4_CMASK', - 'mmCB_COLOR4_CMASK_BASE_EXT', - 'mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR4_CMASK_BASE_IDX', 'mmCB_COLOR4_CMASK_SLICE', - 'mmCB_COLOR4_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE', - 'mmCB_COLOR4_DCC_BASE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE_EXT', - 'mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_DCC_CONTROL', - 'mmCB_COLOR4_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR4_FMASK', - 'mmCB_COLOR4_FMASK_BASE_EXT', - 'mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR4_FMASK_BASE_IDX', 'mmCB_COLOR4_FMASK_SLICE', - 'mmCB_COLOR4_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_INFO', - 'mmCB_COLOR4_INFO_BASE_IDX', 'mmCB_COLOR4_PITCH', - 'mmCB_COLOR4_PITCH_BASE_IDX', 'mmCB_COLOR4_SLICE', - 'mmCB_COLOR4_SLICE_BASE_IDX', 'mmCB_COLOR4_VIEW', - 'mmCB_COLOR4_VIEW_BASE_IDX', 'mmCB_COLOR5_ATTRIB', - 'mmCB_COLOR5_ATTRIB2', 'mmCB_COLOR5_ATTRIB2_BASE_IDX', - 'mmCB_COLOR5_ATTRIB3', 'mmCB_COLOR5_ATTRIB3_BASE_IDX', - 'mmCB_COLOR5_ATTRIB_BASE_IDX', 'mmCB_COLOR5_BASE', - 'mmCB_COLOR5_BASE_BASE_IDX', 'mmCB_COLOR5_BASE_EXT', - 'mmCB_COLOR5_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD0', - 'mmCB_COLOR5_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD1', - 'mmCB_COLOR5_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR5_CMASK', - 'mmCB_COLOR5_CMASK_BASE_EXT', - 'mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR5_CMASK_BASE_IDX', 'mmCB_COLOR5_CMASK_SLICE', - 'mmCB_COLOR5_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE', - 'mmCB_COLOR5_DCC_BASE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE_EXT', - 'mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_DCC_CONTROL', - 'mmCB_COLOR5_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR5_FMASK', - 'mmCB_COLOR5_FMASK_BASE_EXT', - 'mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR5_FMASK_BASE_IDX', 'mmCB_COLOR5_FMASK_SLICE', - 'mmCB_COLOR5_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_INFO', - 'mmCB_COLOR5_INFO_BASE_IDX', 'mmCB_COLOR5_PITCH', - 'mmCB_COLOR5_PITCH_BASE_IDX', 'mmCB_COLOR5_SLICE', - 'mmCB_COLOR5_SLICE_BASE_IDX', 'mmCB_COLOR5_VIEW', - 'mmCB_COLOR5_VIEW_BASE_IDX', 'mmCB_COLOR6_ATTRIB', - 'mmCB_COLOR6_ATTRIB2', 'mmCB_COLOR6_ATTRIB2_BASE_IDX', - 'mmCB_COLOR6_ATTRIB3', 'mmCB_COLOR6_ATTRIB3_BASE_IDX', - 'mmCB_COLOR6_ATTRIB_BASE_IDX', 'mmCB_COLOR6_BASE', - 'mmCB_COLOR6_BASE_BASE_IDX', 'mmCB_COLOR6_BASE_EXT', - 'mmCB_COLOR6_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD0', - 'mmCB_COLOR6_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD1', - 'mmCB_COLOR6_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR6_CMASK', - 'mmCB_COLOR6_CMASK_BASE_EXT', - 'mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR6_CMASK_BASE_IDX', 'mmCB_COLOR6_CMASK_SLICE', - 'mmCB_COLOR6_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE', - 'mmCB_COLOR6_DCC_BASE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE_EXT', - 'mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_DCC_CONTROL', - 'mmCB_COLOR6_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR6_FMASK', - 'mmCB_COLOR6_FMASK_BASE_EXT', - 'mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR6_FMASK_BASE_IDX', 'mmCB_COLOR6_FMASK_SLICE', - 'mmCB_COLOR6_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_INFO', - 'mmCB_COLOR6_INFO_BASE_IDX', 'mmCB_COLOR6_PITCH', - 'mmCB_COLOR6_PITCH_BASE_IDX', 'mmCB_COLOR6_SLICE', - 'mmCB_COLOR6_SLICE_BASE_IDX', 'mmCB_COLOR6_VIEW', - 'mmCB_COLOR6_VIEW_BASE_IDX', 'mmCB_COLOR7_ATTRIB', - 'mmCB_COLOR7_ATTRIB2', 'mmCB_COLOR7_ATTRIB2_BASE_IDX', - 'mmCB_COLOR7_ATTRIB3', 'mmCB_COLOR7_ATTRIB3_BASE_IDX', - 'mmCB_COLOR7_ATTRIB_BASE_IDX', 'mmCB_COLOR7_BASE', - 'mmCB_COLOR7_BASE_BASE_IDX', 'mmCB_COLOR7_BASE_EXT', - 'mmCB_COLOR7_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD0', - 'mmCB_COLOR7_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD1', - 'mmCB_COLOR7_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR7_CMASK', - 'mmCB_COLOR7_CMASK_BASE_EXT', - 'mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR7_CMASK_BASE_IDX', 'mmCB_COLOR7_CMASK_SLICE', - 'mmCB_COLOR7_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE', - 'mmCB_COLOR7_DCC_BASE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE_EXT', - 'mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_DCC_CONTROL', - 'mmCB_COLOR7_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR7_FMASK', - 'mmCB_COLOR7_FMASK_BASE_EXT', - 'mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX', - 'mmCB_COLOR7_FMASK_BASE_IDX', 'mmCB_COLOR7_FMASK_SLICE', - 'mmCB_COLOR7_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_INFO', - 'mmCB_COLOR7_INFO_BASE_IDX', 'mmCB_COLOR7_PITCH', - 'mmCB_COLOR7_PITCH_BASE_IDX', 'mmCB_COLOR7_SLICE', - 'mmCB_COLOR7_SLICE_BASE_IDX', 'mmCB_COLOR7_VIEW', - 'mmCB_COLOR7_VIEW_BASE_IDX', 'mmCB_COLOR_CONTROL', - 'mmCB_COLOR_CONTROL_BASE_IDX', 'mmCB_COVERAGE_OUT_CONTROL', - 'mmCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'mmCB_DCC_CONFIG', - 'mmCB_DCC_CONFIG_BASE_IDX', 'mmCB_DCC_CONTROL', - 'mmCB_DCC_CONTROL_BASE_IDX', 'mmCB_HW_CONTROL', - 'mmCB_HW_CONTROL_1', 'mmCB_HW_CONTROL_1_BASE_IDX', - 'mmCB_HW_CONTROL_2', 'mmCB_HW_CONTROL_2_BASE_IDX', - 'mmCB_HW_CONTROL_3', 'mmCB_HW_CONTROL_3_BASE_IDX', - 'mmCB_HW_CONTROL_4', 'mmCB_HW_CONTROL_4_BASE_IDX', - 'mmCB_HW_CONTROL_BASE_IDX', 'mmCB_HW_MEM_ARBITER_RD', - 'mmCB_HW_MEM_ARBITER_RD_BASE_IDX', 'mmCB_HW_MEM_ARBITER_WR', - 'mmCB_HW_MEM_ARBITER_WR_BASE_IDX', 'mmCB_PERFCOUNTER0_HI', - 'mmCB_PERFCOUNTER0_HI_BASE_IDX', 'mmCB_PERFCOUNTER0_LO', - 'mmCB_PERFCOUNTER0_LO_BASE_IDX', 'mmCB_PERFCOUNTER0_SELECT', - 'mmCB_PERFCOUNTER0_SELECT1', 'mmCB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER1_HI', - 'mmCB_PERFCOUNTER1_HI_BASE_IDX', 'mmCB_PERFCOUNTER1_LO', - 'mmCB_PERFCOUNTER1_LO_BASE_IDX', 'mmCB_PERFCOUNTER1_SELECT', - 'mmCB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER2_HI', - 'mmCB_PERFCOUNTER2_HI_BASE_IDX', 'mmCB_PERFCOUNTER2_LO', - 'mmCB_PERFCOUNTER2_LO_BASE_IDX', 'mmCB_PERFCOUNTER2_SELECT', - 'mmCB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER3_HI', - 'mmCB_PERFCOUNTER3_HI_BASE_IDX', 'mmCB_PERFCOUNTER3_LO', - 'mmCB_PERFCOUNTER3_LO_BASE_IDX', 'mmCB_PERFCOUNTER3_SELECT', - 'mmCB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER_FILTER', - 'mmCB_PERFCOUNTER_FILTER_BASE_IDX', - 'mmCB_RMI_BC_GL2_CACHE_CONTROL', - 'mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX', - 'mmCB_RMI_GL2_CACHE_CONTROL', - 'mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'mmCB_SHADER_MASK', - 'mmCB_SHADER_MASK_BASE_IDX', 'mmCB_STUTTER_CONTROL_CMASK_RDLAT', - 'mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX', - 'mmCB_STUTTER_CONTROL_COLOR_RDLAT', - 'mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX', - 'mmCB_STUTTER_CONTROL_FMASK_RDLAT', - 'mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX', 'mmCB_TARGET_MASK', - 'mmCB_TARGET_MASK_BASE_IDX', 'mmCC_GC_EDC_CONFIG', - 'mmCC_GC_EDC_CONFIG_BASE_IDX', 'mmCC_GC_PRIM_CONFIG', - 'mmCC_GC_PRIM_CONFIG_BASE_IDX', 'mmCC_GC_SA_UNIT_DISABLE', - 'mmCC_GC_SA_UNIT_DISABLE_BASE_IDX', 'mmCC_GC_SHADER_ARRAY_CONFIG', - 'mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', - 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0', - 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX', - 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1', - 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX', - 'mmCC_GC_SHADER_RATE_CONFIG', - 'mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX', 'mmCC_RB_BACKEND_DISABLE', - 'mmCC_RB_BACKEND_DISABLE_BASE_IDX', 'mmCC_RB_DAISY_CHAIN', - 'mmCC_RB_DAISY_CHAIN_BASE_IDX', 'mmCC_RB_REDUNDANCY', - 'mmCC_RB_REDUNDANCY_BASE_IDX', 'mmCC_RMI_REDUNDANCY', - 'mmCC_RMI_REDUNDANCY_BASE_IDX', 'mmCGTS_RD_CTRL_REG', - 'mmCGTS_RD_CTRL_REG_BASE_IDX', 'mmCGTS_RD_REG', - 'mmCGTS_RD_REG_BASE_IDX', 'mmCGTS_STATUS_REG', - 'mmCGTS_STATUS_REG_BASE_IDX', 'mmCGTS_TCC_DISABLE', - 'mmCGTS_TCC_DISABLE_BASE_IDX', 'mmCGTS_USER_TCC_DISABLE', - 'mmCGTS_USER_TCC_DISABLE_BASE_IDX', 'mmCGTT_BCI_CLK_CTRL', - 'mmCGTT_BCI_CLK_CTRL_BASE_IDX', 'mmCGTT_CPC_CLK_CTRL', - 'mmCGTT_CPC_CLK_CTRL_BASE_IDX', 'mmCGTT_CPF_CLK_CTRL', - 'mmCGTT_CPF_CLK_CTRL_BASE_IDX', 'mmCGTT_CP_CLK_CTRL', - 'mmCGTT_CP_CLK_CTRL_BASE_IDX', 'mmCGTT_GDS_CLK_CTRL', - 'mmCGTT_GDS_CLK_CTRL_BASE_IDX', 'mmCGTT_GS_NGG_CLK_CTRL', - 'mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX', 'mmCGTT_IA_CLK_CTRL', - 'mmCGTT_IA_CLK_CTRL_BASE_IDX', 'mmCGTT_PA_CLK_CTRL', - 'mmCGTT_PA_CLK_CTRL_BASE_IDX', 'mmCGTT_PC_CLK_CTRL', - 'mmCGTT_PC_CLK_CTRL_BASE_IDX', 'mmCGTT_PH_CLK_CTRL0', - 'mmCGTT_PH_CLK_CTRL0_BASE_IDX', 'mmCGTT_PH_CLK_CTRL1', - 'mmCGTT_PH_CLK_CTRL1_BASE_IDX', 'mmCGTT_PH_CLK_CTRL2', - 'mmCGTT_PH_CLK_CTRL2_BASE_IDX', 'mmCGTT_PH_CLK_CTRL3', - 'mmCGTT_PH_CLK_CTRL3_BASE_IDX', 'mmCGTT_RLC_CLK_CTRL', - 'mmCGTT_RLC_CLK_CTRL_BASE_IDX', 'mmCGTT_SC_CLK_CTRL0', - 'mmCGTT_SC_CLK_CTRL0_BASE_IDX', 'mmCGTT_SC_CLK_CTRL1', - 'mmCGTT_SC_CLK_CTRL1_BASE_IDX', 'mmCGTT_SC_CLK_CTRL2', - 'mmCGTT_SC_CLK_CTRL2_BASE_IDX', 'mmCGTT_SPIS_CLK_CTRL', - 'mmCGTT_SPIS_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CGTSSM_CLK_CTRL', - 'mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CLK_CTRL', - 'mmCGTT_SPI_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_PS_CLK_CTRL', - 'mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX', 'mmCGTT_SQG_CLK_CTRL', - 'mmCGTT_SQG_CLK_CTRL_BASE_IDX', 'mmCGTT_SQ_CLK_CTRL', - 'mmCGTT_SQ_CLK_CTRL_BASE_IDX', 'mmCGTT_SX_CLK_CTRL0', - 'mmCGTT_SX_CLK_CTRL0_BASE_IDX', 'mmCGTT_SX_CLK_CTRL1', - 'mmCGTT_SX_CLK_CTRL1_BASE_IDX', 'mmCGTT_SX_CLK_CTRL2', - 'mmCGTT_SX_CLK_CTRL2_BASE_IDX', 'mmCGTT_SX_CLK_CTRL3', - 'mmCGTT_SX_CLK_CTRL3_BASE_IDX', 'mmCGTT_SX_CLK_CTRL4', - 'mmCGTT_SX_CLK_CTRL4_BASE_IDX', 'mmCGTT_TCPF_CLK_CTRL', - 'mmCGTT_TCPF_CLK_CTRL_BASE_IDX', 'mmCGTT_TCPI_CLK_CTRL', - 'mmCGTT_TCPI_CLK_CTRL_BASE_IDX', 'mmCGTT_VGT_CLK_CTRL', - 'mmCGTT_VGT_CLK_CTRL_BASE_IDX', 'mmCGTT_WD_CLK_CTRL', - 'mmCGTT_WD_CLK_CTRL_BASE_IDX', 'mmCHA_CHC_CREDITS', - 'mmCHA_CHC_CREDITS_BASE_IDX', 'mmCHA_CLIENT_FREE_DELAY', - 'mmCHA_CLIENT_FREE_DELAY_BASE_IDX', 'mmCHA_PERFCOUNTER0_HI', - 'mmCHA_PERFCOUNTER0_HI_BASE_IDX', 'mmCHA_PERFCOUNTER0_LO', - 'mmCHA_PERFCOUNTER0_LO_BASE_IDX', 'mmCHA_PERFCOUNTER0_SELECT', - 'mmCHA_PERFCOUNTER0_SELECT1', - 'mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER1_HI', - 'mmCHA_PERFCOUNTER1_HI_BASE_IDX', 'mmCHA_PERFCOUNTER1_LO', - 'mmCHA_PERFCOUNTER1_LO_BASE_IDX', 'mmCHA_PERFCOUNTER1_SELECT', - 'mmCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER2_HI', - 'mmCHA_PERFCOUNTER2_HI_BASE_IDX', 'mmCHA_PERFCOUNTER2_LO', - 'mmCHA_PERFCOUNTER2_LO_BASE_IDX', 'mmCHA_PERFCOUNTER2_SELECT', - 'mmCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER3_HI', - 'mmCHA_PERFCOUNTER3_HI_BASE_IDX', 'mmCHA_PERFCOUNTER3_LO', - 'mmCHA_PERFCOUNTER3_LO_BASE_IDX', 'mmCHA_PERFCOUNTER3_SELECT', - 'mmCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_CTRL', - 'mmCHCG_CTRL_BASE_IDX', 'mmCHCG_PERFCOUNTER0_HI', - 'mmCHCG_PERFCOUNTER0_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER0_LO', - 'mmCHCG_PERFCOUNTER0_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER0_SELECT', - 'mmCHCG_PERFCOUNTER0_SELECT1', - 'mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER1_HI', - 'mmCHCG_PERFCOUNTER1_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER1_LO', - 'mmCHCG_PERFCOUNTER1_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER1_SELECT', - 'mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER2_HI', - 'mmCHCG_PERFCOUNTER2_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER2_LO', - 'mmCHCG_PERFCOUNTER2_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER2_SELECT', - 'mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER3_HI', - 'mmCHCG_PERFCOUNTER3_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER3_LO', - 'mmCHCG_PERFCOUNTER3_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER3_SELECT', - 'mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_STATUS', - 'mmCHCG_STATUS_BASE_IDX', 'mmCHC_CTRL', 'mmCHC_CTRL_BASE_IDX', - 'mmCHC_PERFCOUNTER0_HI', 'mmCHC_PERFCOUNTER0_HI_BASE_IDX', - 'mmCHC_PERFCOUNTER0_LO', 'mmCHC_PERFCOUNTER0_LO_BASE_IDX', - 'mmCHC_PERFCOUNTER0_SELECT', 'mmCHC_PERFCOUNTER0_SELECT1', - 'mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER1_HI', - 'mmCHC_PERFCOUNTER1_HI_BASE_IDX', 'mmCHC_PERFCOUNTER1_LO', - 'mmCHC_PERFCOUNTER1_LO_BASE_IDX', 'mmCHC_PERFCOUNTER1_SELECT', - 'mmCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER2_HI', - 'mmCHC_PERFCOUNTER2_HI_BASE_IDX', 'mmCHC_PERFCOUNTER2_LO', - 'mmCHC_PERFCOUNTER2_LO_BASE_IDX', 'mmCHC_PERFCOUNTER2_SELECT', - 'mmCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER3_HI', - 'mmCHC_PERFCOUNTER3_HI_BASE_IDX', 'mmCHC_PERFCOUNTER3_LO', - 'mmCHC_PERFCOUNTER3_LO_BASE_IDX', 'mmCHC_PERFCOUNTER3_SELECT', - 'mmCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHC_STATUS', - 'mmCHC_STATUS_BASE_IDX', 'mmCH_ARB_CTRL', - 'mmCH_ARB_CTRL_BASE_IDX', 'mmCH_ARB_STATUS', - 'mmCH_ARB_STATUS_BASE_IDX', 'mmCH_DRAM_BURST_CTRL', - 'mmCH_DRAM_BURST_CTRL_BASE_IDX', 'mmCH_DRAM_BURST_MASK', - 'mmCH_DRAM_BURST_MASK_BASE_IDX', 'mmCH_PIPE_STEER', - 'mmCH_PIPE_STEER_BASE_IDX', 'mmCH_VC5_ENABLE', - 'mmCH_VC5_ENABLE_BASE_IDX', 'mmCOHER_DEST_BASE_0', - 'mmCOHER_DEST_BASE_0_BASE_IDX', 'mmCOHER_DEST_BASE_1', - 'mmCOHER_DEST_BASE_1_BASE_IDX', 'mmCOHER_DEST_BASE_2', - 'mmCOHER_DEST_BASE_2_BASE_IDX', 'mmCOHER_DEST_BASE_3', - 'mmCOHER_DEST_BASE_3_BASE_IDX', 'mmCOHER_DEST_BASE_HI_0', - 'mmCOHER_DEST_BASE_HI_0_BASE_IDX', 'mmCOHER_DEST_BASE_HI_1', - 'mmCOHER_DEST_BASE_HI_1_BASE_IDX', 'mmCOHER_DEST_BASE_HI_2', - 'mmCOHER_DEST_BASE_HI_2_BASE_IDX', 'mmCOHER_DEST_BASE_HI_3', - 'mmCOHER_DEST_BASE_HI_3_BASE_IDX', 'mmCOMPUTE_DDID_INDEX', - 'mmCOMPUTE_DDID_INDEX_BASE_IDX', 'mmCOMPUTE_DESTINATION_EN_SE0', - 'mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX', - 'mmCOMPUTE_DESTINATION_EN_SE1', - 'mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX', - 'mmCOMPUTE_DESTINATION_EN_SE2', - 'mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX', - 'mmCOMPUTE_DESTINATION_EN_SE3', - 'mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'mmCOMPUTE_DIM_X', - 'mmCOMPUTE_DIM_X_BASE_IDX', 'mmCOMPUTE_DIM_Y', - 'mmCOMPUTE_DIM_Y_BASE_IDX', 'mmCOMPUTE_DIM_Z', - 'mmCOMPUTE_DIM_Z_BASE_IDX', 'mmCOMPUTE_DISPATCH_END', - 'mmCOMPUTE_DISPATCH_END_BASE_IDX', 'mmCOMPUTE_DISPATCH_ID', - 'mmCOMPUTE_DISPATCH_ID_BASE_IDX', 'mmCOMPUTE_DISPATCH_INITIATOR', - 'mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', - 'mmCOMPUTE_DISPATCH_PKT_ADDR_HI', - 'mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', - 'mmCOMPUTE_DISPATCH_PKT_ADDR_LO', - 'mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', - 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI', - 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', - 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO', - 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', - 'mmCOMPUTE_DISPATCH_TUNNEL', 'mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', - 'mmCOMPUTE_MISC_RESERVED', 'mmCOMPUTE_MISC_RESERVED_BASE_IDX', - 'mmCOMPUTE_NOWHERE', 'mmCOMPUTE_NOWHERE_BASE_IDX', - 'mmCOMPUTE_NUM_THREAD_X', 'mmCOMPUTE_NUM_THREAD_X_BASE_IDX', - 'mmCOMPUTE_NUM_THREAD_Y', 'mmCOMPUTE_NUM_THREAD_Y_BASE_IDX', - 'mmCOMPUTE_NUM_THREAD_Z', 'mmCOMPUTE_NUM_THREAD_Z_BASE_IDX', - 'mmCOMPUTE_PERFCOUNT_ENABLE', - 'mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'mmCOMPUTE_PGM_HI', - 'mmCOMPUTE_PGM_HI_BASE_IDX', 'mmCOMPUTE_PGM_LO', - 'mmCOMPUTE_PGM_LO_BASE_IDX', 'mmCOMPUTE_PGM_RSRC1', - 'mmCOMPUTE_PGM_RSRC1_BASE_IDX', 'mmCOMPUTE_PGM_RSRC2', - 'mmCOMPUTE_PGM_RSRC2_BASE_IDX', 'mmCOMPUTE_PGM_RSRC3', - 'mmCOMPUTE_PGM_RSRC3_BASE_IDX', 'mmCOMPUTE_PIPELINESTAT_ENABLE', - 'mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'mmCOMPUTE_RELAUNCH', - 'mmCOMPUTE_RELAUNCH2', 'mmCOMPUTE_RELAUNCH2_BASE_IDX', - 'mmCOMPUTE_RELAUNCH_BASE_IDX', 'mmCOMPUTE_REQ_CTRL', - 'mmCOMPUTE_REQ_CTRL_BASE_IDX', 'mmCOMPUTE_RESOURCE_LIMITS', - 'mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'mmCOMPUTE_RESTART_X', - 'mmCOMPUTE_RESTART_X_BASE_IDX', 'mmCOMPUTE_RESTART_Y', - 'mmCOMPUTE_RESTART_Y_BASE_IDX', 'mmCOMPUTE_RESTART_Z', - 'mmCOMPUTE_RESTART_Z_BASE_IDX', 'mmCOMPUTE_SHADER_CHKSUM', - 'mmCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'mmCOMPUTE_START_X', - 'mmCOMPUTE_START_X_BASE_IDX', 'mmCOMPUTE_START_Y', - 'mmCOMPUTE_START_Y_BASE_IDX', 'mmCOMPUTE_START_Z', - 'mmCOMPUTE_START_Z_BASE_IDX', 'mmCOMPUTE_STATIC_THREAD_MGMT_SE0', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE1', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE2', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE3', - 'mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', - 'mmCOMPUTE_THREADGROUP_ID', 'mmCOMPUTE_THREADGROUP_ID_BASE_IDX', - 'mmCOMPUTE_THREAD_TRACE_ENABLE', - 'mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', - 'mmCOMPUTE_TMPRING_SIZE', 'mmCOMPUTE_TMPRING_SIZE_BASE_IDX', - 'mmCOMPUTE_USER_ACCUM_0', 'mmCOMPUTE_USER_ACCUM_0_BASE_IDX', - 'mmCOMPUTE_USER_ACCUM_1', 'mmCOMPUTE_USER_ACCUM_1_BASE_IDX', - 'mmCOMPUTE_USER_ACCUM_2', 'mmCOMPUTE_USER_ACCUM_2_BASE_IDX', - 'mmCOMPUTE_USER_ACCUM_3', 'mmCOMPUTE_USER_ACCUM_3_BASE_IDX', - 'mmCOMPUTE_USER_DATA_0', 'mmCOMPUTE_USER_DATA_0_BASE_IDX', - 'mmCOMPUTE_USER_DATA_1', 'mmCOMPUTE_USER_DATA_10', - 'mmCOMPUTE_USER_DATA_10_BASE_IDX', 'mmCOMPUTE_USER_DATA_11', - 'mmCOMPUTE_USER_DATA_11_BASE_IDX', 'mmCOMPUTE_USER_DATA_12', - 'mmCOMPUTE_USER_DATA_12_BASE_IDX', 'mmCOMPUTE_USER_DATA_13', - 'mmCOMPUTE_USER_DATA_13_BASE_IDX', 'mmCOMPUTE_USER_DATA_14', - 'mmCOMPUTE_USER_DATA_14_BASE_IDX', 'mmCOMPUTE_USER_DATA_15', - 'mmCOMPUTE_USER_DATA_15_BASE_IDX', - 'mmCOMPUTE_USER_DATA_1_BASE_IDX', 'mmCOMPUTE_USER_DATA_2', - 'mmCOMPUTE_USER_DATA_2_BASE_IDX', 'mmCOMPUTE_USER_DATA_3', - 'mmCOMPUTE_USER_DATA_3_BASE_IDX', 'mmCOMPUTE_USER_DATA_4', - 'mmCOMPUTE_USER_DATA_4_BASE_IDX', 'mmCOMPUTE_USER_DATA_5', - 'mmCOMPUTE_USER_DATA_5_BASE_IDX', 'mmCOMPUTE_USER_DATA_6', - 'mmCOMPUTE_USER_DATA_6_BASE_IDX', 'mmCOMPUTE_USER_DATA_7', - 'mmCOMPUTE_USER_DATA_7_BASE_IDX', 'mmCOMPUTE_USER_DATA_8', - 'mmCOMPUTE_USER_DATA_8_BASE_IDX', 'mmCOMPUTE_USER_DATA_9', - 'mmCOMPUTE_USER_DATA_9_BASE_IDX', 'mmCOMPUTE_VMID', - 'mmCOMPUTE_VMID_BASE_IDX', 'mmCOMPUTE_WAVE_RESTORE_ADDR_HI', - 'mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', - 'mmCOMPUTE_WAVE_RESTORE_ADDR_LO', - 'mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', - 'mmCONFIG_RESERVED_REG0', 'mmCONFIG_RESERVED_REG0_BASE_IDX', - 'mmCONFIG_RESERVED_REG1', 'mmCONFIG_RESERVED_REG1_BASE_IDX', - 'mmCONTEXT_RESERVED_REG0', 'mmCONTEXT_RESERVED_REG0_BASE_IDX', - 'mmCONTEXT_RESERVED_REG1', 'mmCONTEXT_RESERVED_REG1_BASE_IDX', - 'mmCPC_DDID_BASE_ADDR_HI', 'mmCPC_DDID_BASE_ADDR_HI_BASE_IDX', - 'mmCPC_DDID_BASE_ADDR_LO', 'mmCPC_DDID_BASE_ADDR_LO_BASE_IDX', - 'mmCPC_DDID_CNTL', 'mmCPC_DDID_CNTL_BASE_IDX', 'mmCPC_INT_ADDR', - 'mmCPC_INT_ADDR_BASE_IDX', 'mmCPC_INT_CNTL', - 'mmCPC_INT_CNTL_BASE_IDX', 'mmCPC_INT_CNTX_ID', - 'mmCPC_INT_CNTX_ID_BASE_IDX', 'mmCPC_INT_INFO', - 'mmCPC_INT_INFO_BASE_IDX', 'mmCPC_INT_PASID', - 'mmCPC_INT_PASID_BASE_IDX', 'mmCPC_INT_STATUS', - 'mmCPC_INT_STATUS_BASE_IDX', 'mmCPC_LATENCY_STATS_DATA', - 'mmCPC_LATENCY_STATS_DATA_BASE_IDX', 'mmCPC_LATENCY_STATS_SELECT', - 'mmCPC_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPC_OS_PIPES', - 'mmCPC_OS_PIPES_BASE_IDX', 'mmCPC_PERFCOUNTER0_HI', - 'mmCPC_PERFCOUNTER0_HI_BASE_IDX', 'mmCPC_PERFCOUNTER0_LO', - 'mmCPC_PERFCOUNTER0_LO_BASE_IDX', 'mmCPC_PERFCOUNTER0_SELECT', - 'mmCPC_PERFCOUNTER0_SELECT1', - 'mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPC_PERFCOUNTER1_HI', - 'mmCPC_PERFCOUNTER1_HI_BASE_IDX', 'mmCPC_PERFCOUNTER1_LO', - 'mmCPC_PERFCOUNTER1_LO_BASE_IDX', 'mmCPC_PERFCOUNTER1_SELECT', - 'mmCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPC_PSP_DEBUG', - 'mmCPC_PSP_DEBUG_BASE_IDX', 'mmCPC_SUSPEND_CNTL_STACK_OFFSET', - 'mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'mmCPC_SUSPEND_CNTL_STACK_SIZE', - 'mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX', - 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI', - 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO', - 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'mmCPC_SUSPEND_CTX_SAVE_CONTROL', - 'mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX', - 'mmCPC_SUSPEND_CTX_SAVE_SIZE', - 'mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX', - 'mmCPC_SUSPEND_WG_STATE_OFFSET', - 'mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCPC_UTCL1_CNTL', - 'mmCPC_UTCL1_CNTL_BASE_IDX', 'mmCPC_UTCL1_ERROR', - 'mmCPC_UTCL1_ERROR_BASE_IDX', 'mmCPC_UTCL1_STATUS', - 'mmCPC_UTCL1_STATUS_BASE_IDX', 'mmCPF_GCR_CNTL', - 'mmCPF_GCR_CNTL_BASE_IDX', 'mmCPF_LATENCY_STATS_DATA', - 'mmCPF_LATENCY_STATS_DATA_BASE_IDX', 'mmCPF_LATENCY_STATS_SELECT', - 'mmCPF_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER0_HI', - 'mmCPF_PERFCOUNTER0_HI_BASE_IDX', 'mmCPF_PERFCOUNTER0_LO', - 'mmCPF_PERFCOUNTER0_LO_BASE_IDX', 'mmCPF_PERFCOUNTER0_SELECT', - 'mmCPF_PERFCOUNTER0_SELECT1', - 'mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER1_HI', - 'mmCPF_PERFCOUNTER1_HI_BASE_IDX', 'mmCPF_PERFCOUNTER1_LO', - 'mmCPF_PERFCOUNTER1_LO_BASE_IDX', 'mmCPF_PERFCOUNTER1_SELECT', - 'mmCPF_PERFCOUNTER1_SELECT_BASE_IDX', - 'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT', - 'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'mmCPF_UTCL1_CNTL', 'mmCPF_UTCL1_CNTL_BASE_IDX', - 'mmCPF_UTCL1_STATUS', 'mmCPF_UTCL1_STATUS_BASE_IDX', - 'mmCPG_LATENCY_STATS_DATA', 'mmCPG_LATENCY_STATS_DATA_BASE_IDX', - 'mmCPG_LATENCY_STATS_SELECT', - 'mmCPG_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER0_HI', - 'mmCPG_PERFCOUNTER0_HI_BASE_IDX', 'mmCPG_PERFCOUNTER0_LO', - 'mmCPG_PERFCOUNTER0_LO_BASE_IDX', 'mmCPG_PERFCOUNTER0_SELECT', - 'mmCPG_PERFCOUNTER0_SELECT1', - 'mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER1_HI', - 'mmCPG_PERFCOUNTER1_HI_BASE_IDX', 'mmCPG_PERFCOUNTER1_LO', - 'mmCPG_PERFCOUNTER1_LO_BASE_IDX', 'mmCPG_PERFCOUNTER1_SELECT', - 'mmCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPG_PSP_DEBUG', - 'mmCPG_PSP_DEBUG_BASE_IDX', 'mmCPG_RCIU_CAM_DATA', - 'mmCPG_RCIU_CAM_DATA_BASE_IDX', 'mmCPG_RCIU_CAM_DATA_PHASE0', - 'mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX', - 'mmCPG_RCIU_CAM_DATA_PHASE1', - 'mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX', - 'mmCPG_RCIU_CAM_DATA_PHASE2', - 'mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'mmCPG_RCIU_CAM_INDEX', - 'mmCPG_RCIU_CAM_INDEX_BASE_IDX', - 'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT', - 'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'mmCPG_UTCL1_CNTL', 'mmCPG_UTCL1_CNTL_BASE_IDX', - 'mmCPG_UTCL1_ERROR', 'mmCPG_UTCL1_ERROR_BASE_IDX', - 'mmCPG_UTCL1_STATUS', 'mmCPG_UTCL1_STATUS_BASE_IDX', - 'mmCP_APPEND_ADDR_HI', 'mmCP_APPEND_ADDR_HI_BASE_IDX', - 'mmCP_APPEND_ADDR_LO', 'mmCP_APPEND_ADDR_LO_BASE_IDX', - 'mmCP_APPEND_CMD_ADDR_HI', 'mmCP_APPEND_CMD_ADDR_HI_BASE_IDX', - 'mmCP_APPEND_CMD_ADDR_LO', 'mmCP_APPEND_CMD_ADDR_LO_BASE_IDX', - 'mmCP_APPEND_DATA', 'mmCP_APPEND_DATA_BASE_IDX', - 'mmCP_APPEND_DATA_HI', 'mmCP_APPEND_DATA_HI_BASE_IDX', - 'mmCP_APPEND_DATA_LO', 'mmCP_APPEND_DATA_LO_BASE_IDX', - 'mmCP_APPEND_DDID_CNT', 'mmCP_APPEND_DDID_CNT_BASE_IDX', - 'mmCP_APPEND_LAST_CS_FENCE', 'mmCP_APPEND_LAST_CS_FENCE_BASE_IDX', - 'mmCP_APPEND_LAST_CS_FENCE_HI', - 'mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', - 'mmCP_APPEND_LAST_CS_FENCE_LO', - 'mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', - 'mmCP_APPEND_LAST_PS_FENCE', 'mmCP_APPEND_LAST_PS_FENCE_BASE_IDX', - 'mmCP_APPEND_LAST_PS_FENCE_HI', - 'mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', - 'mmCP_APPEND_LAST_PS_FENCE_LO', - 'mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'mmCP_AQL_SMM_STATUS', - 'mmCP_AQL_SMM_STATUS_BASE_IDX', 'mmCP_ATOMIC_PREOP_HI', - 'mmCP_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_ATOMIC_PREOP_LO', - 'mmCP_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_BUSY_STAT', - 'mmCP_BUSY_STAT_BASE_IDX', 'mmCP_CEQ1_AVAIL', - 'mmCP_CEQ1_AVAIL_BASE_IDX', 'mmCP_CEQ2_AVAIL', - 'mmCP_CEQ2_AVAIL_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_HI', - 'mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_LO', - 'mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_CE_COMPARE_COUNT', - 'mmCP_CE_COMPARE_COUNT_BASE_IDX', 'mmCP_CE_COMPLETION_STATUS', - 'mmCP_CE_COMPLETION_STATUS_BASE_IDX', 'mmCP_CE_COUNTER', - 'mmCP_CE_COUNTER_BASE_IDX', 'mmCP_CE_CS_PARTITION_INDEX', - 'mmCP_CE_CS_PARTITION_INDEX_BASE_IDX', 'mmCP_CE_DB_BASE_HI', - 'mmCP_CE_DB_BASE_HI_BASE_IDX', 'mmCP_CE_DB_BASE_LO', - 'mmCP_CE_DB_BASE_LO_BASE_IDX', 'mmCP_CE_DB_BUFSZ', - 'mmCP_CE_DB_BUFSZ_BASE_IDX', 'mmCP_CE_DB_CMD_BUFSZ', - 'mmCP_CE_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_DE_COUNT', - 'mmCP_CE_DE_COUNT_BASE_IDX', 'mmCP_CE_DOORBELL_CONTROL', - 'mmCP_CE_DOORBELL_CONTROL_BASE_IDX', 'mmCP_CE_F32_INTERRUPT', - 'mmCP_CE_F32_INTERRUPT_BASE_IDX', 'mmCP_CE_GDS_ATOMIC0_PREOP_HI', - 'mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'mmCP_CE_GDS_ATOMIC0_PREOP_LO', - 'mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'mmCP_CE_GDS_ATOMIC1_PREOP_HI', - 'mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'mmCP_CE_GDS_ATOMIC1_PREOP_LO', - 'mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_CE_HEADER_DUMP', - 'mmCP_CE_HEADER_DUMP_BASE_IDX', 'mmCP_CE_IB1_BASE_HI', - 'mmCP_CE_IB1_BASE_HI_BASE_IDX', 'mmCP_CE_IB1_BASE_LO', - 'mmCP_CE_IB1_BASE_LO_BASE_IDX', 'mmCP_CE_IB1_BUFSZ', - 'mmCP_CE_IB1_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_CMD_BUFSZ', - 'mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_OFFSET', - 'mmCP_CE_IB1_OFFSET_BASE_IDX', 'mmCP_CE_IB2_BASE_HI', - 'mmCP_CE_IB2_BASE_HI_BASE_IDX', 'mmCP_CE_IB2_BASE_LO', - 'mmCP_CE_IB2_BASE_LO_BASE_IDX', 'mmCP_CE_IB2_BUFSZ', - 'mmCP_CE_IB2_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_CMD_BUFSZ', - 'mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_OFFSET', - 'mmCP_CE_IB2_OFFSET_BASE_IDX', 'mmCP_CE_IC_BASE_CNTL', - 'mmCP_CE_IC_BASE_CNTL_BASE_IDX', 'mmCP_CE_IC_BASE_HI', - 'mmCP_CE_IC_BASE_HI_BASE_IDX', 'mmCP_CE_IC_BASE_LO', - 'mmCP_CE_IC_BASE_LO_BASE_IDX', 'mmCP_CE_IC_OP_CNTL', - 'mmCP_CE_IC_OP_CNTL_BASE_IDX', 'mmCP_CE_INIT_BASE_HI', - 'mmCP_CE_INIT_BASE_HI_BASE_IDX', 'mmCP_CE_INIT_BASE_LO', - 'mmCP_CE_INIT_BASE_LO_BASE_IDX', 'mmCP_CE_INIT_BUFSZ', - 'mmCP_CE_INIT_BUFSZ_BASE_IDX', 'mmCP_CE_INIT_CMD_BUFSZ', - 'mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_INSTR_PNTR', - 'mmCP_CE_INSTR_PNTR_BASE_IDX', 'mmCP_CE_INTR_ROUTINE_START', - 'mmCP_CE_INTR_ROUTINE_START_BASE_IDX', 'mmCP_CE_JT_STAT', - 'mmCP_CE_JT_STAT_BASE_IDX', 'mmCP_CE_METADATA_BASE_ADDR', - 'mmCP_CE_METADATA_BASE_ADDR_BASE_IDX', - 'mmCP_CE_METADATA_BASE_ADDR_HI', - 'mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX', - 'mmCP_CE_PRGRM_CNTR_START', 'mmCP_CE_PRGRM_CNTR_START_BASE_IDX', - 'mmCP_CE_ROQ_DB_STAT', 'mmCP_CE_ROQ_DB_STAT_BASE_IDX', - 'mmCP_CE_ROQ_IB1_STAT', 'mmCP_CE_ROQ_IB1_STAT_BASE_IDX', - 'mmCP_CE_ROQ_IB2_STAT', 'mmCP_CE_ROQ_IB2_STAT_BASE_IDX', - 'mmCP_CE_ROQ_RB_STAT', 'mmCP_CE_ROQ_RB_STAT_BASE_IDX', - 'mmCP_CE_UCODE_ADDR', 'mmCP_CE_UCODE_ADDR_BASE_IDX', - 'mmCP_CE_UCODE_DATA', 'mmCP_CE_UCODE_DATA_BASE_IDX', - 'mmCP_CMD_DATA', 'mmCP_CMD_DATA_BASE_IDX', 'mmCP_CMD_INDEX', - 'mmCP_CMD_INDEX_BASE_IDX', 'mmCP_CNTX_STAT', - 'mmCP_CNTX_STAT_BASE_IDX', 'mmCP_COHER_BASE', - 'mmCP_COHER_BASE_BASE_IDX', 'mmCP_COHER_BASE_HI', - 'mmCP_COHER_BASE_HI_BASE_IDX', 'mmCP_COHER_CNTL', - 'mmCP_COHER_CNTL_BASE_IDX', 'mmCP_COHER_SIZE', - 'mmCP_COHER_SIZE_BASE_IDX', 'mmCP_COHER_SIZE_HI', - 'mmCP_COHER_SIZE_HI_BASE_IDX', 'mmCP_COHER_START_DELAY', - 'mmCP_COHER_START_DELAY_BASE_IDX', 'mmCP_COHER_STATUS', - 'mmCP_COHER_STATUS_BASE_IDX', 'mmCP_CONTEXT_CNTL', - 'mmCP_CONTEXT_CNTL_BASE_IDX', 'mmCP_CPC_BUSY_STAT', - 'mmCP_CPC_BUSY_STAT2', 'mmCP_CPC_BUSY_STAT2_BASE_IDX', - 'mmCP_CPC_BUSY_STAT_BASE_IDX', 'mmCP_CPC_GFX_CNTL', - 'mmCP_CPC_GFX_CNTL_BASE_IDX', 'mmCP_CPC_GRBM_FREE_COUNT', - 'mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPC_HALT_HYST_COUNT', - 'mmCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'mmCP_CPC_IC_BASE_CNTL', - 'mmCP_CPC_IC_BASE_CNTL_BASE_IDX', 'mmCP_CPC_IC_BASE_HI', - 'mmCP_CPC_IC_BASE_HI_BASE_IDX', 'mmCP_CPC_IC_BASE_LO', - 'mmCP_CPC_IC_BASE_LO_BASE_IDX', 'mmCP_CPC_IC_OP_CNTL', - 'mmCP_CPC_IC_OP_CNTL_BASE_IDX', 'mmCP_CPC_MGCG_SYNC_CNTL', - 'mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', - 'mmCP_CPC_PRIV_VIOLATION_ADDR', - 'mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_CPC_SCRATCH_DATA', - 'mmCP_CPC_SCRATCH_DATA_BASE_IDX', 'mmCP_CPC_SCRATCH_INDEX', - 'mmCP_CPC_SCRATCH_INDEX_BASE_IDX', 'mmCP_CPC_STALLED_STAT1', - 'mmCP_CPC_STALLED_STAT1_BASE_IDX', 'mmCP_CPC_STATUS', - 'mmCP_CPC_STATUS_BASE_IDX', 'mmCP_CPF_BUSY_STAT', - 'mmCP_CPF_BUSY_STAT2', 'mmCP_CPF_BUSY_STAT2_BASE_IDX', - 'mmCP_CPF_BUSY_STAT_BASE_IDX', 'mmCP_CPF_GRBM_FREE_COUNT', - 'mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPF_STALLED_STAT1', - 'mmCP_CPF_STALLED_STAT1_BASE_IDX', 'mmCP_CPF_STATUS', - 'mmCP_CPF_STATUS_BASE_IDX', 'mmCP_CSF_STAT', - 'mmCP_CSF_STAT_BASE_IDX', 'mmCP_DB_BASE_HI', - 'mmCP_DB_BASE_HI_BASE_IDX', 'mmCP_DB_BASE_LO', - 'mmCP_DB_BASE_LO_BASE_IDX', 'mmCP_DB_BUFSZ', - 'mmCP_DB_BUFSZ_BASE_IDX', 'mmCP_DB_CMD_BUFSZ', - 'mmCP_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_DDID_BASE_ADDR_HI', - 'mmCP_DDID_BASE_ADDR_HI_BASE_IDX', 'mmCP_DDID_BASE_ADDR_LO', - 'mmCP_DDID_BASE_ADDR_LO_BASE_IDX', 'mmCP_DDID_CNTL', - 'mmCP_DDID_CNTL_BASE_IDX', 'mmCP_DEVICE_ID', - 'mmCP_DEVICE_ID_BASE_IDX', 'mmCP_DE_CE_COUNT', - 'mmCP_DE_CE_COUNT_BASE_IDX', 'mmCP_DE_DE_COUNT', - 'mmCP_DE_DE_COUNT_BASE_IDX', 'mmCP_DE_LAST_INVAL_COUNT', - 'mmCP_DE_LAST_INVAL_COUNT_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR', - 'mmCP_DISPATCH_INDR_ADDR_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR_HI', - 'mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'mmCP_DMA_CNTL', - 'mmCP_DMA_CNTL_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_HI', - 'mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_LO', - 'mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_ME_COMMAND', - 'mmCP_DMA_ME_COMMAND_BASE_IDX', 'mmCP_DMA_ME_CONTROL', - 'mmCP_DMA_ME_CONTROL_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR', - 'mmCP_DMA_ME_DST_ADDR_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR_HI', - 'mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR', - 'mmCP_DMA_ME_SRC_ADDR_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR_HI', - 'mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_HI', - 'mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_LO', - 'mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_PFP_COMMAND', - 'mmCP_DMA_PFP_COMMAND_BASE_IDX', 'mmCP_DMA_PFP_CONTROL', - 'mmCP_DMA_PFP_CONTROL_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR', - 'mmCP_DMA_PFP_DST_ADDR_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR_HI', - 'mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR', - 'mmCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR_HI', - 'mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_READ_TAGS', - 'mmCP_DMA_READ_TAGS_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_HI', - 'mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_LO', - 'mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH0_CNTL', - 'mmCP_DMA_WATCH0_CNTL_BASE_IDX', 'mmCP_DMA_WATCH0_MASK', - 'mmCP_DMA_WATCH0_MASK_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_HI', - 'mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_LO', - 'mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH1_CNTL', - 'mmCP_DMA_WATCH1_CNTL_BASE_IDX', 'mmCP_DMA_WATCH1_MASK', - 'mmCP_DMA_WATCH1_MASK_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_HI', - 'mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_LO', - 'mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH2_CNTL', - 'mmCP_DMA_WATCH2_CNTL_BASE_IDX', 'mmCP_DMA_WATCH2_MASK', - 'mmCP_DMA_WATCH2_MASK_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_HI', - 'mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_LO', - 'mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH3_CNTL', - 'mmCP_DMA_WATCH3_CNTL_BASE_IDX', 'mmCP_DMA_WATCH3_MASK', - 'mmCP_DMA_WATCH3_MASK_BASE_IDX', 'mmCP_DMA_WATCH_STAT', - 'mmCP_DMA_WATCH_STAT_ADDR_HI', - 'mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX', - 'mmCP_DMA_WATCH_STAT_ADDR_LO', - 'mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX', - 'mmCP_DMA_WATCH_STAT_BASE_IDX', 'mmCP_DRAW_INDX_INDR_ADDR', - 'mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX', - 'mmCP_DRAW_INDX_INDR_ADDR_HI', - 'mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'mmCP_DRAW_OBJECT', - 'mmCP_DRAW_OBJECT_BASE_IDX', 'mmCP_DRAW_OBJECT_COUNTER', - 'mmCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'mmCP_DRAW_WINDOW_CNTL', - 'mmCP_DRAW_WINDOW_CNTL_BASE_IDX', 'mmCP_DRAW_WINDOW_HI', - 'mmCP_DRAW_WINDOW_HI_BASE_IDX', 'mmCP_DRAW_WINDOW_LO', - 'mmCP_DRAW_WINDOW_LO_BASE_IDX', 'mmCP_DRAW_WINDOW_MASK_HI', - 'mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'mmCP_ECC_FIRSTOCCURRENCE', - 'mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX', - 'mmCP_ECC_FIRSTOCCURRENCE_RING0', - 'mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', - 'mmCP_ECC_FIRSTOCCURRENCE_RING1', - 'mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', - 'mmCP_ECC_FIRSTOCCURRENCE_RING2', - 'mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX', 'mmCP_EOPQ_WAIT_TIME', - 'mmCP_EOPQ_WAIT_TIME_BASE_IDX', 'mmCP_EOP_DONE_ADDR_HI', - 'mmCP_EOP_DONE_ADDR_HI_BASE_IDX', 'mmCP_EOP_DONE_ADDR_LO', - 'mmCP_EOP_DONE_ADDR_LO_BASE_IDX', 'mmCP_EOP_DONE_CNTX_ID', - 'mmCP_EOP_DONE_CNTX_ID_BASE_IDX', 'mmCP_EOP_DONE_DATA_CNTL', - 'mmCP_EOP_DONE_DATA_CNTL_BASE_IDX', 'mmCP_EOP_DONE_DATA_HI', - 'mmCP_EOP_DONE_DATA_HI_BASE_IDX', 'mmCP_EOP_DONE_DATA_LO', - 'mmCP_EOP_DONE_DATA_LO_BASE_IDX', 'mmCP_EOP_DONE_EVENT_CNTL', - 'mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX', 'mmCP_EOP_LAST_FENCE_HI', - 'mmCP_EOP_LAST_FENCE_HI_BASE_IDX', 'mmCP_EOP_LAST_FENCE_LO', - 'mmCP_EOP_LAST_FENCE_LO_BASE_IDX', 'mmCP_FATAL_ERROR', - 'mmCP_FATAL_ERROR_BASE_IDX', 'mmCP_FETCHER_SOURCE', - 'mmCP_FETCHER_SOURCE_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_HI', - 'mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_LO', - 'mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_HI', - 'mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_LO', - 'mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_GDS_BKUP_ADDR', - 'mmCP_GDS_BKUP_ADDR_BASE_IDX', 'mmCP_GDS_BKUP_ADDR_HI', - 'mmCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'mmCP_GFX_DDID_DELTA_RPT_COUNT', - 'mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'mmCP_GFX_DDID_INFLIGHT_COUNT', - 'mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_GFX_DDID_RPTR', - 'mmCP_GFX_DDID_RPTR_BASE_IDX', 'mmCP_GFX_DDID_WPTR', - 'mmCP_GFX_DDID_WPTR_BASE_IDX', 'mmCP_GFX_ERROR', - 'mmCP_GFX_ERROR_BASE_IDX', 'mmCP_GFX_HPD_CONTROL0', - 'mmCP_GFX_HPD_CONTROL0_BASE_IDX', - 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI', - 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX', - 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO', - 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX', - 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI', - 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX', - 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO', - 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX', - 'mmCP_GFX_HPD_STATUS0', 'mmCP_GFX_HPD_STATUS0_BASE_IDX', - 'mmCP_GFX_HQD_ACTIVE', 'mmCP_GFX_HQD_ACTIVE_BASE_IDX', - 'mmCP_GFX_HQD_BASE', 'mmCP_GFX_HQD_BASE_BASE_IDX', - 'mmCP_GFX_HQD_BASE_HI', 'mmCP_GFX_HQD_BASE_HI_BASE_IDX', - 'mmCP_GFX_HQD_CE_BASE', 'mmCP_GFX_HQD_CE_BASE_BASE_IDX', - 'mmCP_GFX_HQD_CE_BASE_HI', 'mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX', - 'mmCP_GFX_HQD_CE_CNTL', 'mmCP_GFX_HQD_CE_CNTL_BASE_IDX', - 'mmCP_GFX_HQD_CE_CSMD_RPTR', 'mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX', - 'mmCP_GFX_HQD_CE_OFFSET', 'mmCP_GFX_HQD_CE_OFFSET_BASE_IDX', - 'mmCP_GFX_HQD_CE_RPTR', 'mmCP_GFX_HQD_CE_RPTR_ADDR', - 'mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX', - 'mmCP_GFX_HQD_CE_RPTR_ADDR_HI', - 'mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX', - 'mmCP_GFX_HQD_CE_RPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_RPTR_WR', - 'mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR', - 'mmCP_GFX_HQD_CE_WPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR_HI', - 'mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX', - 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI', - 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO', - 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX', 'mmCP_GFX_HQD_CNTL', - 'mmCP_GFX_HQD_CNTL_BASE_IDX', 'mmCP_GFX_HQD_CSMD_RPTR', - 'mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_DEQUEUE_REQUEST', - 'mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX', - 'mmCP_GFX_HQD_HQ_CONTROL0', 'mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX', - 'mmCP_GFX_HQD_HQ_STATUS0', 'mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX', - 'mmCP_GFX_HQD_MAPPED', 'mmCP_GFX_HQD_MAPPED_BASE_IDX', - 'mmCP_GFX_HQD_OFFSET', 'mmCP_GFX_HQD_OFFSET_BASE_IDX', - 'mmCP_GFX_HQD_QUANTUM', 'mmCP_GFX_HQD_QUANTUM_BASE_IDX', - 'mmCP_GFX_HQD_QUEUE_PRIORITY', - 'mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX', - 'mmCP_GFX_HQD_QUE_MGR_CONTROL', - 'mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'mmCP_GFX_HQD_RPTR', - 'mmCP_GFX_HQD_RPTR_ADDR', 'mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX', - 'mmCP_GFX_HQD_RPTR_ADDR_HI', 'mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX', - 'mmCP_GFX_HQD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_VMID', - 'mmCP_GFX_HQD_VMID_BASE_IDX', 'mmCP_GFX_HQD_WPTR', - 'mmCP_GFX_HQD_WPTR_BASE_IDX', 'mmCP_GFX_HQD_WPTR_HI', - 'mmCP_GFX_HQD_WPTR_HI_BASE_IDX', 'mmCP_GFX_INDEX_MUTEX', - 'mmCP_GFX_INDEX_MUTEX_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR', - 'mmCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR_HI', - 'mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_GFX_MQD_CONTROL', - 'mmCP_GFX_MQD_CONTROL_BASE_IDX', 'mmCP_GFX_QUEUE_INDEX', - 'mmCP_GFX_QUEUE_INDEX_BASE_IDX', 'mmCP_GPU_TIMESTAMP_OFFSET_HI', - 'mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX', - 'mmCP_GPU_TIMESTAMP_OFFSET_LO', - 'mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'mmCP_GRBM_FREE_COUNT', - 'mmCP_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_HPD_MES_ROQ_OFFSETS', - 'mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_ROQ_OFFSETS', - 'mmCP_HPD_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_STATUS0', - 'mmCP_HPD_STATUS0_BASE_IDX', 'mmCP_HPD_UTCL1_CNTL', - 'mmCP_HPD_UTCL1_CNTL_BASE_IDX', 'mmCP_HPD_UTCL1_ERROR', - 'mmCP_HPD_UTCL1_ERROR_ADDR', 'mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', - 'mmCP_HPD_UTCL1_ERROR_BASE_IDX', 'mmCP_HQD_ACTIVE', - 'mmCP_HQD_ACTIVE_BASE_IDX', 'mmCP_HQD_AQL_CONTROL', - 'mmCP_HQD_AQL_CONTROL_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_HI', - 'mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_LO', - 'mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_HI', - 'mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_LO', - 'mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', - 'mmCP_HQD_CNTL_STACK_OFFSET', - 'mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', 'mmCP_HQD_CNTL_STACK_SIZE', - 'mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX', - 'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI', - 'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO', - 'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'mmCP_HQD_CTX_SAVE_CONTROL', 'mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', - 'mmCP_HQD_CTX_SAVE_SIZE', 'mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX', - 'mmCP_HQD_DDID_DELTA_RPT_COUNT', - 'mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'mmCP_HQD_DDID_INFLIGHT_COUNT', - 'mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_HQD_DDID_RPTR', - 'mmCP_HQD_DDID_RPTR_BASE_IDX', 'mmCP_HQD_DDID_WPTR', - 'mmCP_HQD_DDID_WPTR_BASE_IDX', 'mmCP_HQD_DEQUEUE_REQUEST', - 'mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'mmCP_HQD_DEQUEUE_STATUS', - 'mmCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'mmCP_HQD_DMA_OFFLOAD', - 'mmCP_HQD_DMA_OFFLOAD_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR', - 'mmCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR_HI', - 'mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_EOP_CONTROL', - 'mmCP_HQD_EOP_CONTROL_BASE_IDX', 'mmCP_HQD_EOP_EVENTS', - 'mmCP_HQD_EOP_EVENTS_BASE_IDX', 'mmCP_HQD_EOP_RPTR', - 'mmCP_HQD_EOP_RPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR', - 'mmCP_HQD_EOP_WPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR_MEM', - 'mmCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'mmCP_HQD_ERROR', - 'mmCP_HQD_ERROR_BASE_IDX', 'mmCP_HQD_GDS_RESOURCE_STATE', - 'mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'mmCP_HQD_GFX_CONTROL', - 'mmCP_HQD_GFX_CONTROL_BASE_IDX', 'mmCP_HQD_GFX_STATUS', - 'mmCP_HQD_GFX_STATUS_BASE_IDX', 'mmCP_HQD_HQ_CONTROL0', - 'mmCP_HQD_HQ_CONTROL0_BASE_IDX', 'mmCP_HQD_HQ_CONTROL1', - 'mmCP_HQD_HQ_CONTROL1_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER0', - 'mmCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER1', - 'mmCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'mmCP_HQD_HQ_STATUS0', - 'mmCP_HQD_HQ_STATUS0_BASE_IDX', 'mmCP_HQD_HQ_STATUS1', - 'mmCP_HQD_HQ_STATUS1_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR', - 'mmCP_HQD_IB_BASE_ADDR_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR_HI', - 'mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_IB_CONTROL', - 'mmCP_HQD_IB_CONTROL_BASE_IDX', 'mmCP_HQD_IB_RPTR', - 'mmCP_HQD_IB_RPTR_BASE_IDX', 'mmCP_HQD_IQ_RPTR', - 'mmCP_HQD_IQ_RPTR_BASE_IDX', 'mmCP_HQD_IQ_TIMER', - 'mmCP_HQD_IQ_TIMER_BASE_IDX', 'mmCP_HQD_MSG_TYPE', - 'mmCP_HQD_MSG_TYPE_BASE_IDX', 'mmCP_HQD_OFFLOAD', - 'mmCP_HQD_OFFLOAD_BASE_IDX', 'mmCP_HQD_PERSISTENT_STATE', - 'mmCP_HQD_PERSISTENT_STATE_BASE_IDX', 'mmCP_HQD_PIPE_PRIORITY', - 'mmCP_HQD_PIPE_PRIORITY_BASE_IDX', 'mmCP_HQD_PQ_BASE', - 'mmCP_HQD_PQ_BASE_BASE_IDX', 'mmCP_HQD_PQ_BASE_HI', - 'mmCP_HQD_PQ_BASE_HI_BASE_IDX', 'mmCP_HQD_PQ_CONTROL', - 'mmCP_HQD_PQ_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_DOORBELL_CONTROL', - 'mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_RPTR', - 'mmCP_HQD_PQ_RPTR_BASE_IDX', 'mmCP_HQD_PQ_RPTR_REPORT_ADDR', - 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', - 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI', - 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_HI', - 'mmCP_HQD_PQ_WPTR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_LO', - 'mmCP_HQD_PQ_WPTR_LO_BASE_IDX', 'mmCP_HQD_PQ_WPTR_POLL_ADDR', - 'mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', - 'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI', - 'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'mmCP_HQD_QUANTUM', - 'mmCP_HQD_QUANTUM_BASE_IDX', 'mmCP_HQD_QUEUE_PRIORITY', - 'mmCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'mmCP_HQD_SEMA_CMD', - 'mmCP_HQD_SEMA_CMD_BASE_IDX', - 'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT', - 'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX', - 'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET', - 'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'mmCP_HQD_SUSPEND_WG_STATE_OFFSET', - 'mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HQD_VMID', - 'mmCP_HQD_VMID_BASE_IDX', 'mmCP_HQD_WG_STATE_OFFSET', - 'mmCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HYP_CE_UCODE_ADDR', - 'mmCP_HYP_CE_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_CE_UCODE_DATA', - 'mmCP_HYP_CE_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_ADDR', - 'mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_DATA', - 'mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_ADDR', - 'mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_DATA', - 'mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'mmCP_HYP_ME_UCODE_ADDR', - 'mmCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_ME_UCODE_DATA', - 'mmCP_HYP_ME_UCODE_DATA_BASE_IDX', 'mmCP_HYP_PFP_UCODE_ADDR', - 'mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_PFP_UCODE_DATA', - 'mmCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'mmCP_IB1_BASE_HI', - 'mmCP_IB1_BASE_HI_BASE_IDX', 'mmCP_IB1_BASE_LO', - 'mmCP_IB1_BASE_LO_BASE_IDX', 'mmCP_IB1_BUFSZ', - 'mmCP_IB1_BUFSZ_BASE_IDX', 'mmCP_IB2_BASE_HI', - 'mmCP_IB2_BASE_HI_BASE_IDX', 'mmCP_IB2_BASE_LO', - 'mmCP_IB2_BASE_LO_BASE_IDX', 'mmCP_IB2_BUFSZ', - 'mmCP_IB2_BUFSZ_BASE_IDX', 'mmCP_IB2_CMD_BUFSZ', - 'mmCP_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_IB2_OFFSET', - 'mmCP_IB2_OFFSET_BASE_IDX', 'mmCP_IB2_PREAMBLE_BEGIN', - 'mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'mmCP_IB2_PREAMBLE_END', - 'mmCP_IB2_PREAMBLE_END_BASE_IDX', 'mmCP_INDEX_BASE_ADDR', - 'mmCP_INDEX_BASE_ADDR_BASE_IDX', 'mmCP_INDEX_BASE_ADDR_HI', - 'mmCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'mmCP_INDEX_TYPE', - 'mmCP_INDEX_TYPE_BASE_IDX', 'mmCP_INT_CNTL', - 'mmCP_INT_CNTL_BASE_IDX', 'mmCP_INT_CNTL_RING0', - 'mmCP_INT_CNTL_RING0_BASE_IDX', 'mmCP_INT_CNTL_RING1', - 'mmCP_INT_CNTL_RING1_BASE_IDX', 'mmCP_INT_CNTL_RING2', - 'mmCP_INT_CNTL_RING2_BASE_IDX', 'mmCP_INT_STATUS', - 'mmCP_INT_STATUS_BASE_IDX', 'mmCP_INT_STATUS_RING0', - 'mmCP_INT_STATUS_RING0_BASE_IDX', 'mmCP_INT_STATUS_RING1', - 'mmCP_INT_STATUS_RING1_BASE_IDX', 'mmCP_INT_STATUS_RING2', - 'mmCP_INT_STATUS_RING2_BASE_IDX', 'mmCP_IQ_WAIT_TIME1', - 'mmCP_IQ_WAIT_TIME1_BASE_IDX', 'mmCP_IQ_WAIT_TIME2', - 'mmCP_IQ_WAIT_TIME2_BASE_IDX', 'mmCP_IQ_WAIT_TIME3', - 'mmCP_IQ_WAIT_TIME3_BASE_IDX', 'mmCP_MAX_CONTEXT', - 'mmCP_MAX_CONTEXT_BASE_IDX', 'mmCP_ME0_PIPE0_PRIORITY', - 'mmCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE0_VMID', - 'mmCP_ME0_PIPE0_VMID_BASE_IDX', 'mmCP_ME0_PIPE1_PRIORITY', - 'mmCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE1_VMID', - 'mmCP_ME0_PIPE1_VMID_BASE_IDX', 'mmCP_ME0_PIPE2_PRIORITY', - 'mmCP_ME0_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE_PRIORITY_CNTS', - 'mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME1_INT_STAT_DEBUG', - 'mmCP_ME1_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME1_PIPE0_INT_CNTL', - 'mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE0_INT_STATUS', - 'mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE0_PRIORITY', - 'mmCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE1_INT_CNTL', - 'mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE1_INT_STATUS', - 'mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE1_PRIORITY', - 'mmCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE2_INT_CNTL', - 'mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE2_INT_STATUS', - 'mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE2_PRIORITY', - 'mmCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE3_INT_CNTL', - 'mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE3_INT_STATUS', - 'mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE3_PRIORITY', - 'mmCP_ME1_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE_PRIORITY_CNTS', - 'mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME2_INT_STAT_DEBUG', - 'mmCP_ME2_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME2_PIPE0_INT_CNTL', - 'mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE0_INT_STATUS', - 'mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE0_PRIORITY', - 'mmCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE1_INT_CNTL', - 'mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE1_INT_STATUS', - 'mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE1_PRIORITY', - 'mmCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE2_INT_CNTL', - 'mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE2_INT_STATUS', - 'mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE2_PRIORITY', - 'mmCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE3_INT_CNTL', - 'mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE3_INT_STATUS', - 'mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE3_PRIORITY', - 'mmCP_ME2_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE_PRIORITY_CNTS', - 'mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_MEC1_F32_INTERRUPT', - 'mmCP_MEC1_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC1_F32_INT_DIS', - 'mmCP_MEC1_F32_INT_DIS_BASE_IDX', 'mmCP_MEC1_INSTR_PNTR', - 'mmCP_MEC1_INSTR_PNTR_BASE_IDX', 'mmCP_MEC1_INTR_ROUTINE_START', - 'mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX', - 'mmCP_MEC1_PRGRM_CNTR_START', - 'mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC2_F32_INTERRUPT', - 'mmCP_MEC2_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC2_F32_INT_DIS', - 'mmCP_MEC2_F32_INT_DIS_BASE_IDX', 'mmCP_MEC2_INSTR_PNTR', - 'mmCP_MEC2_INSTR_PNTR_BASE_IDX', 'mmCP_MEC2_INTR_ROUTINE_START', - 'mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX', - 'mmCP_MEC2_PRGRM_CNTR_START', - 'mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC_CNTL', - 'mmCP_MEC_CNTL_BASE_IDX', 'mmCP_MEC_DOORBELL_RANGE_LOWER', - 'mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', - 'mmCP_MEC_DOORBELL_RANGE_UPPER', - 'mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_MEC_JT_STAT', - 'mmCP_MEC_JT_STAT_BASE_IDX', 'mmCP_MEC_ME1_HEADER_DUMP', - 'mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME1_UCODE_ADDR', - 'mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME1_UCODE_DATA', - 'mmCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'mmCP_MEC_ME2_HEADER_DUMP', - 'mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME2_UCODE_ADDR', - 'mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME2_UCODE_DATA', - 'mmCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'mmCP_MEM_SLP_CNTL', - 'mmCP_MEM_SLP_CNTL_BASE_IDX', 'mmCP_MEQ_AVAIL', - 'mmCP_MEQ_AVAIL_BASE_IDX', 'mmCP_MEQ_STAT', - 'mmCP_MEQ_STAT_BASE_IDX', 'mmCP_MEQ_STQ_THRESHOLD', - 'mmCP_MEQ_STQ_THRESHOLD_BASE_IDX', 'mmCP_MEQ_THRESHOLDS', - 'mmCP_MEQ_THRESHOLDS_BASE_IDX', 'mmCP_MES_CNTL', - 'mmCP_MES_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_CNTL', - 'mmCP_MES_DC_BASE_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_HI', - 'mmCP_MES_DC_BASE_HI_BASE_IDX', 'mmCP_MES_DC_BASE_LO', - 'mmCP_MES_DC_BASE_LO_BASE_IDX', 'mmCP_MES_DC_OP_CNTL', - 'mmCP_MES_DC_OP_CNTL_BASE_IDX', 'mmCP_MES_DM_INDEX_ADDR', - 'mmCP_MES_DM_INDEX_ADDR_BASE_IDX', 'mmCP_MES_DM_INDEX_DATA', - 'mmCP_MES_DM_INDEX_DATA_BASE_IDX', 'mmCP_MES_DOORBELL_CONTROL1', - 'mmCP_MES_DOORBELL_CONTROL1_BASE_IDX', - 'mmCP_MES_DOORBELL_CONTROL2', - 'mmCP_MES_DOORBELL_CONTROL2_BASE_IDX', - 'mmCP_MES_DOORBELL_CONTROL3', - 'mmCP_MES_DOORBELL_CONTROL3_BASE_IDX', - 'mmCP_MES_DOORBELL_CONTROL4', - 'mmCP_MES_DOORBELL_CONTROL4_BASE_IDX', - 'mmCP_MES_DOORBELL_CONTROL5', - 'mmCP_MES_DOORBELL_CONTROL5_BASE_IDX', - 'mmCP_MES_DOORBELL_CONTROL6', - 'mmCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'mmCP_MES_GP0_HI', - 'mmCP_MES_GP0_HI_BASE_IDX', 'mmCP_MES_GP0_LO', - 'mmCP_MES_GP0_LO_BASE_IDX', 'mmCP_MES_GP1_HI', - 'mmCP_MES_GP1_HI_BASE_IDX', 'mmCP_MES_GP1_LO', - 'mmCP_MES_GP1_LO_BASE_IDX', 'mmCP_MES_GP2_HI', - 'mmCP_MES_GP2_HI_BASE_IDX', 'mmCP_MES_GP2_LO', - 'mmCP_MES_GP2_LO_BASE_IDX', 'mmCP_MES_GP3_HI', - 'mmCP_MES_GP3_HI_BASE_IDX', 'mmCP_MES_GP3_LO', - 'mmCP_MES_GP3_LO_BASE_IDX', 'mmCP_MES_GP4_HI', - 'mmCP_MES_GP4_HI_BASE_IDX', 'mmCP_MES_GP4_LO', - 'mmCP_MES_GP4_LO_BASE_IDX', 'mmCP_MES_GP5_HI', - 'mmCP_MES_GP5_HI_BASE_IDX', 'mmCP_MES_GP5_LO', - 'mmCP_MES_GP5_LO_BASE_IDX', 'mmCP_MES_GP6_HI', - 'mmCP_MES_GP6_HI_BASE_IDX', 'mmCP_MES_GP6_LO', - 'mmCP_MES_GP6_LO_BASE_IDX', 'mmCP_MES_GP7_HI', - 'mmCP_MES_GP7_HI_BASE_IDX', 'mmCP_MES_GP7_LO', - 'mmCP_MES_GP7_LO_BASE_IDX', 'mmCP_MES_GP8_HI', - 'mmCP_MES_GP8_HI_BASE_IDX', 'mmCP_MES_GP8_LO', - 'mmCP_MES_GP8_LO_BASE_IDX', 'mmCP_MES_GP9_HI', - 'mmCP_MES_GP9_HI_BASE_IDX', 'mmCP_MES_GP9_LO', - 'mmCP_MES_GP9_LO_BASE_IDX', 'mmCP_MES_HEADER_DUMP', - 'mmCP_MES_HEADER_DUMP_BASE_IDX', 'mmCP_MES_IC_BASE_CNTL', - 'mmCP_MES_IC_BASE_CNTL_BASE_IDX', 'mmCP_MES_IC_BASE_HI', - 'mmCP_MES_IC_BASE_HI_BASE_IDX', 'mmCP_MES_IC_BASE_LO', - 'mmCP_MES_IC_BASE_LO_BASE_IDX', 'mmCP_MES_IC_OP_CNTL', - 'mmCP_MES_IC_OP_CNTL_BASE_IDX', 'mmCP_MES_INSTR_PNTR', - 'mmCP_MES_INSTR_PNTR_BASE_IDX', 'mmCP_MES_INTERRUPT', - 'mmCP_MES_INTERRUPT_BASE_IDX', 'mmCP_MES_INTR_ROUTINE_START', - 'mmCP_MES_INTR_ROUTINE_START_BASE_IDX', 'mmCP_MES_LOCAL_APERTURE', - 'mmCP_MES_LOCAL_APERTURE_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_HI', - 'mmCP_MES_LOCAL_BASE0_HI_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_LO', - 'mmCP_MES_LOCAL_BASE0_LO_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_HI', - 'mmCP_MES_LOCAL_MASK0_HI_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_LO', - 'mmCP_MES_LOCAL_MASK0_LO_BASE_IDX', 'mmCP_MES_MARCHID_HI', - 'mmCP_MES_MARCHID_HI_BASE_IDX', 'mmCP_MES_MARCHID_LO', - 'mmCP_MES_MARCHID_LO_BASE_IDX', 'mmCP_MES_MBADADDR_HI', - 'mmCP_MES_MBADADDR_HI_BASE_IDX', 'mmCP_MES_MBADADDR_LO', - 'mmCP_MES_MBADADDR_LO_BASE_IDX', 'mmCP_MES_MCAUSE_HI', - 'mmCP_MES_MCAUSE_HI_BASE_IDX', 'mmCP_MES_MCAUSE_LO', - 'mmCP_MES_MCAUSE_LO_BASE_IDX', 'mmCP_MES_MCYCLE_HI', - 'mmCP_MES_MCYCLE_HI_BASE_IDX', 'mmCP_MES_MCYCLE_LO', - 'mmCP_MES_MCYCLE_LO_BASE_IDX', 'mmCP_MES_MDBASE_HI', - 'mmCP_MES_MDBASE_HI_BASE_IDX', 'mmCP_MES_MDBASE_LO', - 'mmCP_MES_MDBASE_LO_BASE_IDX', 'mmCP_MES_MDBOUND_HI', - 'mmCP_MES_MDBOUND_HI_BASE_IDX', 'mmCP_MES_MDBOUND_LO', - 'mmCP_MES_MDBOUND_LO_BASE_IDX', 'mmCP_MES_MEPC_HI', - 'mmCP_MES_MEPC_HI_BASE_IDX', 'mmCP_MES_MEPC_LO', - 'mmCP_MES_MEPC_LO_BASE_IDX', 'mmCP_MES_MHARTID_HI', - 'mmCP_MES_MHARTID_HI_BASE_IDX', 'mmCP_MES_MHARTID_LO', - 'mmCP_MES_MHARTID_LO_BASE_IDX', 'mmCP_MES_MIBASE_HI', - 'mmCP_MES_MIBASE_HI_BASE_IDX', 'mmCP_MES_MIBASE_LO', - 'mmCP_MES_MIBASE_LO_BASE_IDX', 'mmCP_MES_MIBOUND_HI', - 'mmCP_MES_MIBOUND_HI_BASE_IDX', 'mmCP_MES_MIBOUND_LO', - 'mmCP_MES_MIBOUND_LO_BASE_IDX', 'mmCP_MES_MIE_HI', - 'mmCP_MES_MIE_HI_BASE_IDX', 'mmCP_MES_MIE_LO', - 'mmCP_MES_MIE_LO_BASE_IDX', 'mmCP_MES_MIMPID_HI', - 'mmCP_MES_MIMPID_HI_BASE_IDX', 'mmCP_MES_MIMPID_LO', - 'mmCP_MES_MIMPID_LO_BASE_IDX', 'mmCP_MES_MINSTRET_HI', - 'mmCP_MES_MINSTRET_HI_BASE_IDX', 'mmCP_MES_MINSTRET_LO', - 'mmCP_MES_MINSTRET_LO_BASE_IDX', 'mmCP_MES_MIP_HI', - 'mmCP_MES_MIP_HI_BASE_IDX', 'mmCP_MES_MIP_LO', - 'mmCP_MES_MIP_LO_BASE_IDX', 'mmCP_MES_MISA_HI', - 'mmCP_MES_MISA_HI_BASE_IDX', 'mmCP_MES_MISA_LO', - 'mmCP_MES_MISA_LO_BASE_IDX', 'mmCP_MES_MSCRATCH_HI', - 'mmCP_MES_MSCRATCH_HI_BASE_IDX', 'mmCP_MES_MSCRATCH_LO', - 'mmCP_MES_MSCRATCH_LO_BASE_IDX', 'mmCP_MES_MSTATUS_HI', - 'mmCP_MES_MSTATUS_HI_BASE_IDX', 'mmCP_MES_MSTATUS_LO', - 'mmCP_MES_MSTATUS_LO_BASE_IDX', 'mmCP_MES_MTIMECMP_HI', - 'mmCP_MES_MTIMECMP_HI_BASE_IDX', 'mmCP_MES_MTIMECMP_LO', - 'mmCP_MES_MTIMECMP_LO_BASE_IDX', 'mmCP_MES_MTIME_HI', - 'mmCP_MES_MTIME_HI_BASE_IDX', 'mmCP_MES_MTIME_LO', - 'mmCP_MES_MTIME_LO_BASE_IDX', 'mmCP_MES_MTVEC_HI', - 'mmCP_MES_MTVEC_HI_BASE_IDX', 'mmCP_MES_MTVEC_LO', - 'mmCP_MES_MTVEC_LO_BASE_IDX', 'mmCP_MES_MVENDORID_HI', - 'mmCP_MES_MVENDORID_HI_BASE_IDX', 'mmCP_MES_MVENDORID_LO', - 'mmCP_MES_MVENDORID_LO_BASE_IDX', 'mmCP_MES_PENDING_INTERRUPT', - 'mmCP_MES_PENDING_INTERRUPT_BASE_IDX', 'mmCP_MES_PERFCOUNT_CNTL', - 'mmCP_MES_PERFCOUNT_CNTL_BASE_IDX', 'mmCP_MES_PIPE0_PRIORITY', - 'mmCP_MES_PIPE0_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE1_PRIORITY', - 'mmCP_MES_PIPE1_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE2_PRIORITY', - 'mmCP_MES_PIPE2_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE3_PRIORITY', - 'mmCP_MES_PIPE3_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE_PRIORITY_CNTS', - 'mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX', - 'mmCP_MES_PRGRM_CNTR_START', 'mmCP_MES_PRGRM_CNTR_START_BASE_IDX', - 'mmCP_MES_PROCESS_QUANTUM_PIPE0', - 'mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX', - 'mmCP_MES_PROCESS_QUANTUM_PIPE1', - 'mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX', - 'mmCP_MES_SCRATCH_DATA', 'mmCP_MES_SCRATCH_DATA_BASE_IDX', - 'mmCP_MES_SCRATCH_INDEX', 'mmCP_MES_SCRATCH_INDEX_BASE_IDX', - 'mmCP_ME_ATOMIC_PREOP_HI', 'mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX', - 'mmCP_ME_ATOMIC_PREOP_LO', 'mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX', - 'mmCP_ME_CNTL', 'mmCP_ME_CNTL_BASE_IDX', 'mmCP_ME_COHER_BASE', - 'mmCP_ME_COHER_BASE_BASE_IDX', 'mmCP_ME_COHER_BASE_HI', - 'mmCP_ME_COHER_BASE_HI_BASE_IDX', 'mmCP_ME_COHER_CNTL', - 'mmCP_ME_COHER_CNTL_BASE_IDX', 'mmCP_ME_COHER_SIZE', - 'mmCP_ME_COHER_SIZE_BASE_IDX', 'mmCP_ME_COHER_SIZE_HI', - 'mmCP_ME_COHER_SIZE_HI_BASE_IDX', 'mmCP_ME_COHER_STATUS', - 'mmCP_ME_COHER_STATUS_BASE_IDX', 'mmCP_ME_F32_INTERRUPT', - 'mmCP_ME_F32_INTERRUPT_BASE_IDX', 'mmCP_ME_GDS_ATOMIC0_PREOP_HI', - 'mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'mmCP_ME_GDS_ATOMIC0_PREOP_LO', - 'mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'mmCP_ME_GDS_ATOMIC1_PREOP_HI', - 'mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'mmCP_ME_GDS_ATOMIC1_PREOP_LO', - 'mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_ME_HEADER_DUMP', - 'mmCP_ME_HEADER_DUMP_BASE_IDX', 'mmCP_ME_IC_BASE_CNTL', - 'mmCP_ME_IC_BASE_CNTL_BASE_IDX', 'mmCP_ME_IC_BASE_HI', - 'mmCP_ME_IC_BASE_HI_BASE_IDX', 'mmCP_ME_IC_BASE_LO', - 'mmCP_ME_IC_BASE_LO_BASE_IDX', 'mmCP_ME_IC_OP_CNTL', - 'mmCP_ME_IC_OP_CNTL_BASE_IDX', 'mmCP_ME_INSTR_PNTR', - 'mmCP_ME_INSTR_PNTR_BASE_IDX', 'mmCP_ME_INTR_ROUTINE_START', - 'mmCP_ME_INTR_ROUTINE_START_BASE_IDX', 'mmCP_ME_MC_RADDR_HI', - 'mmCP_ME_MC_RADDR_HI_BASE_IDX', 'mmCP_ME_MC_RADDR_LO', - 'mmCP_ME_MC_RADDR_LO_BASE_IDX', 'mmCP_ME_MC_WADDR_HI', - 'mmCP_ME_MC_WADDR_HI_BASE_IDX', 'mmCP_ME_MC_WADDR_LO', - 'mmCP_ME_MC_WADDR_LO_BASE_IDX', 'mmCP_ME_MC_WDATA_HI', - 'mmCP_ME_MC_WDATA_HI_BASE_IDX', 'mmCP_ME_MC_WDATA_LO', - 'mmCP_ME_MC_WDATA_LO_BASE_IDX', 'mmCP_ME_PREEMPTION', - 'mmCP_ME_PREEMPTION_BASE_IDX', 'mmCP_ME_PRGRM_CNTR_START', - 'mmCP_ME_PRGRM_CNTR_START_BASE_IDX', 'mmCP_ME_RAM_DATA', - 'mmCP_ME_RAM_DATA_BASE_IDX', 'mmCP_ME_RAM_RADDR', - 'mmCP_ME_RAM_RADDR_BASE_IDX', 'mmCP_ME_RAM_WADDR', - 'mmCP_ME_RAM_WADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR', - 'mmCP_MQD_BASE_ADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR_HI', - 'mmCP_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_MQD_CONTROL', - 'mmCP_MQD_CONTROL_BASE_IDX', 'mmCP_NUM_PRIM_NEEDED_COUNT0_HI', - 'mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT0_LO', - 'mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT1_HI', - 'mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT1_LO', - 'mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT2_HI', - 'mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT2_LO', - 'mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT3_HI', - 'mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX', - 'mmCP_NUM_PRIM_NEEDED_COUNT3_LO', - 'mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI', - 'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO', - 'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI', - 'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO', - 'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI', - 'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO', - 'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI', - 'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX', - 'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO', - 'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX', - 'mmCP_PA_CINVOC_COUNT_HI', 'mmCP_PA_CINVOC_COUNT_HI_BASE_IDX', - 'mmCP_PA_CINVOC_COUNT_LO', 'mmCP_PA_CINVOC_COUNT_LO_BASE_IDX', - 'mmCP_PA_CPRIM_COUNT_HI', 'mmCP_PA_CPRIM_COUNT_HI_BASE_IDX', - 'mmCP_PA_CPRIM_COUNT_LO', 'mmCP_PA_CPRIM_COUNT_LO_BASE_IDX', - 'mmCP_PERFMON_CNTL', 'mmCP_PERFMON_CNTL_BASE_IDX', - 'mmCP_PERFMON_CNTX_CNTL', 'mmCP_PERFMON_CNTX_CNTL_BASE_IDX', - 'mmCP_PFP_ATOMIC_PREOP_HI', 'mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', - 'mmCP_PFP_ATOMIC_PREOP_LO', 'mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', - 'mmCP_PFP_COMPLETION_STATUS', - 'mmCP_PFP_COMPLETION_STATUS_BASE_IDX', 'mmCP_PFP_F32_INTERRUPT', - 'mmCP_PFP_F32_INTERRUPT_BASE_IDX', - 'mmCP_PFP_GDS_ATOMIC0_PREOP_HI', - 'mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'mmCP_PFP_GDS_ATOMIC0_PREOP_LO', - 'mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'mmCP_PFP_GDS_ATOMIC1_PREOP_HI', - 'mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'mmCP_PFP_GDS_ATOMIC1_PREOP_LO', - 'mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_PFP_HEADER_DUMP', - 'mmCP_PFP_HEADER_DUMP_BASE_IDX', 'mmCP_PFP_IB_CONTROL', - 'mmCP_PFP_IB_CONTROL_BASE_IDX', 'mmCP_PFP_IC_BASE_CNTL', - 'mmCP_PFP_IC_BASE_CNTL_BASE_IDX', 'mmCP_PFP_IC_BASE_HI', - 'mmCP_PFP_IC_BASE_HI_BASE_IDX', 'mmCP_PFP_IC_BASE_LO', - 'mmCP_PFP_IC_BASE_LO_BASE_IDX', 'mmCP_PFP_IC_OP_CNTL', - 'mmCP_PFP_IC_OP_CNTL_BASE_IDX', 'mmCP_PFP_INSTR_PNTR', - 'mmCP_PFP_INSTR_PNTR_BASE_IDX', 'mmCP_PFP_INTR_ROUTINE_START', - 'mmCP_PFP_INTR_ROUTINE_START_BASE_IDX', 'mmCP_PFP_JT_STAT', - 'mmCP_PFP_JT_STAT_BASE_IDX', 'mmCP_PFP_LOAD_CONTROL', - 'mmCP_PFP_LOAD_CONTROL_BASE_IDX', 'mmCP_PFP_METADATA_BASE_ADDR', - 'mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX', - 'mmCP_PFP_METADATA_BASE_ADDR_HI', - 'mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', - 'mmCP_PFP_PRGRM_CNTR_START', 'mmCP_PFP_PRGRM_CNTR_START_BASE_IDX', - 'mmCP_PFP_UCODE_ADDR', 'mmCP_PFP_UCODE_ADDR_BASE_IDX', - 'mmCP_PFP_UCODE_DATA', 'mmCP_PFP_UCODE_DATA_BASE_IDX', - 'mmCP_PIPEID', 'mmCP_PIPEID_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_HI', - 'mmCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_LO', - 'mmCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'mmCP_PIPE_STATS_CONTROL', - 'mmCP_PIPE_STATS_CONTROL_BASE_IDX', 'mmCP_PQ_STATUS', - 'mmCP_PQ_STATUS_BASE_IDX', 'mmCP_PQ_WPTR_POLL_CNTL', - 'mmCP_PQ_WPTR_POLL_CNTL1', 'mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', - 'mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'mmCP_PRED_NOT_VISIBLE', - 'mmCP_PRED_NOT_VISIBLE_BASE_IDX', 'mmCP_PRIV_VIOLATION_ADDR', - 'mmCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_PROCESS_QUANTUM', - 'mmCP_PROCESS_QUANTUM_BASE_IDX', 'mmCP_PWR_CNTL', - 'mmCP_PWR_CNTL_BASE_IDX', 'mmCP_QUEUE_THRESHOLDS', - 'mmCP_QUEUE_THRESHOLDS_BASE_IDX', 'mmCP_RB0_ACTIVE', - 'mmCP_RB0_ACTIVE_BASE_IDX', 'mmCP_RB0_BASE', - 'mmCP_RB0_BASE_BASE_IDX', 'mmCP_RB0_BASE_HI', - 'mmCP_RB0_BASE_HI_BASE_IDX', 'mmCP_RB0_BUFSZ_MASK', - 'mmCP_RB0_BUFSZ_MASK_BASE_IDX', 'mmCP_RB0_CNTL', - 'mmCP_RB0_CNTL_BASE_IDX', 'mmCP_RB0_RPTR', 'mmCP_RB0_RPTR_ADDR', - 'mmCP_RB0_RPTR_ADDR_BASE_IDX', 'mmCP_RB0_RPTR_ADDR_HI', - 'mmCP_RB0_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB0_RPTR_BASE_IDX', - 'mmCP_RB0_WPTR', 'mmCP_RB0_WPTR_BASE_IDX', 'mmCP_RB0_WPTR_HI', - 'mmCP_RB0_WPTR_HI_BASE_IDX', 'mmCP_RB1_ACTIVE', - 'mmCP_RB1_ACTIVE_BASE_IDX', 'mmCP_RB1_BASE', - 'mmCP_RB1_BASE_BASE_IDX', 'mmCP_RB1_BASE_HI', - 'mmCP_RB1_BASE_HI_BASE_IDX', 'mmCP_RB1_BUFSZ_MASK', - 'mmCP_RB1_BUFSZ_MASK_BASE_IDX', 'mmCP_RB1_CNTL', - 'mmCP_RB1_CNTL_BASE_IDX', 'mmCP_RB1_RPTR', 'mmCP_RB1_RPTR_ADDR', - 'mmCP_RB1_RPTR_ADDR_BASE_IDX', 'mmCP_RB1_RPTR_ADDR_HI', - 'mmCP_RB1_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB1_RPTR_BASE_IDX', - 'mmCP_RB1_WPTR', 'mmCP_RB1_WPTR_BASE_IDX', 'mmCP_RB1_WPTR_HI', - 'mmCP_RB1_WPTR_HI_BASE_IDX', 'mmCP_RB2_BASE', - 'mmCP_RB2_BASE_BASE_IDX', 'mmCP_RB2_CNTL', - 'mmCP_RB2_CNTL_BASE_IDX', 'mmCP_RB2_RPTR', 'mmCP_RB2_RPTR_ADDR', - 'mmCP_RB2_RPTR_ADDR_BASE_IDX', 'mmCP_RB2_RPTR_ADDR_HI', - 'mmCP_RB2_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB2_RPTR_BASE_IDX', - 'mmCP_RB2_WPTR', 'mmCP_RB2_WPTR_BASE_IDX', 'mmCP_RB_ACTIVE', - 'mmCP_RB_ACTIVE_BASE_IDX', 'mmCP_RB_BASE', - 'mmCP_RB_BASE_BASE_IDX', 'mmCP_RB_BUFSZ_MASK', - 'mmCP_RB_BUFSZ_MASK_BASE_IDX', 'mmCP_RB_CNTL', - 'mmCP_RB_CNTL_BASE_IDX', 'mmCP_RB_DOORBELL_CLEAR', - 'mmCP_RB_DOORBELL_CLEAR_BASE_IDX', 'mmCP_RB_DOORBELL_CONTROL', - 'mmCP_RB_DOORBELL_CONTROL_BASE_IDX', - 'mmCP_RB_DOORBELL_RANGE_LOWER', - 'mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', - 'mmCP_RB_DOORBELL_RANGE_UPPER', - 'mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_RB_OFFSET', - 'mmCP_RB_OFFSET_BASE_IDX', 'mmCP_RB_RPTR', 'mmCP_RB_RPTR_ADDR', - 'mmCP_RB_RPTR_ADDR_BASE_IDX', 'mmCP_RB_RPTR_ADDR_HI', - 'mmCP_RB_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB_RPTR_BASE_IDX', - 'mmCP_RB_RPTR_WR', 'mmCP_RB_RPTR_WR_BASE_IDX', 'mmCP_RB_STATUS', - 'mmCP_RB_STATUS_BASE_IDX', 'mmCP_RB_VMID', - 'mmCP_RB_VMID_BASE_IDX', 'mmCP_RB_WPTR', 'mmCP_RB_WPTR_BASE_IDX', - 'mmCP_RB_WPTR_DELAY', 'mmCP_RB_WPTR_DELAY_BASE_IDX', - 'mmCP_RB_WPTR_HI', 'mmCP_RB_WPTR_HI_BASE_IDX', - 'mmCP_RB_WPTR_POLL_ADDR_HI', 'mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmCP_RB_WPTR_POLL_ADDR_LO', 'mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmCP_RB_WPTR_POLL_CNTL', 'mmCP_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmCP_RING0_PRIORITY', 'mmCP_RING0_PRIORITY_BASE_IDX', - 'mmCP_RING1_PRIORITY', 'mmCP_RING1_PRIORITY_BASE_IDX', - 'mmCP_RING2_PRIORITY', 'mmCP_RING2_PRIORITY_BASE_IDX', - 'mmCP_RINGID', 'mmCP_RINGID_BASE_IDX', 'mmCP_RING_PRIORITY_CNTS', - 'mmCP_RING_PRIORITY_CNTS_BASE_IDX', 'mmCP_ROQ1_THRESHOLDS', - 'mmCP_ROQ1_THRESHOLDS_BASE_IDX', 'mmCP_ROQ2_AVAIL', - 'mmCP_ROQ2_AVAIL_BASE_IDX', 'mmCP_ROQ2_THRESHOLDS', - 'mmCP_ROQ2_THRESHOLDS_BASE_IDX', 'mmCP_ROQ3_THRESHOLDS', - 'mmCP_ROQ3_THRESHOLDS_BASE_IDX', 'mmCP_ROQ_AVAIL', - 'mmCP_ROQ_AVAIL_BASE_IDX', 'mmCP_ROQ_DB_STAT', - 'mmCP_ROQ_DB_STAT_BASE_IDX', 'mmCP_ROQ_IB1_STAT', - 'mmCP_ROQ_IB1_STAT_BASE_IDX', 'mmCP_ROQ_IB2_STAT', - 'mmCP_ROQ_IB2_STAT_BASE_IDX', 'mmCP_ROQ_RB_STAT', - 'mmCP_ROQ_RB_STAT_BASE_IDX', 'mmCP_ROQ_THRESHOLDS', - 'mmCP_ROQ_THRESHOLDS_BASE_IDX', 'mmCP_SAMPLE_STATUS', - 'mmCP_SAMPLE_STATUS_BASE_IDX', 'mmCP_SCRATCH_DATA', - 'mmCP_SCRATCH_DATA_BASE_IDX', 'mmCP_SCRATCH_INDEX', - 'mmCP_SCRATCH_INDEX_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_HI', - 'mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_LO', - 'mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_HI', - 'mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_LO', - 'mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'mmCP_SD_CNTL', - 'mmCP_SD_CNTL_BASE_IDX', 'mmCP_SEM_WAIT_TIMER', - 'mmCP_SEM_WAIT_TIMER_BASE_IDX', 'mmCP_SIG_SEM_ADDR_HI', - 'mmCP_SIG_SEM_ADDR_HI_BASE_IDX', 'mmCP_SIG_SEM_ADDR_LO', - 'mmCP_SIG_SEM_ADDR_LO_BASE_IDX', 'mmCP_SOFT_RESET_CNTL', - 'mmCP_SOFT_RESET_CNTL_BASE_IDX', 'mmCP_STALLED_STAT1', - 'mmCP_STALLED_STAT1_BASE_IDX', 'mmCP_STALLED_STAT2', - 'mmCP_STALLED_STAT2_BASE_IDX', 'mmCP_STALLED_STAT3', - 'mmCP_STALLED_STAT3_BASE_IDX', 'mmCP_STAT', 'mmCP_STAT_BASE_IDX', - 'mmCP_STQ_AVAIL', 'mmCP_STQ_AVAIL_BASE_IDX', 'mmCP_STQ_STAT', - 'mmCP_STQ_STAT_BASE_IDX', 'mmCP_STQ_THRESHOLDS', - 'mmCP_STQ_THRESHOLDS_BASE_IDX', 'mmCP_STQ_WR_STAT', - 'mmCP_STQ_WR_STAT_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_HI', - 'mmCP_STREAM_OUT_ADDR_HI_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_LO', - 'mmCP_STREAM_OUT_ADDR_LO_BASE_IDX', 'mmCP_STREAM_OUT_CONTROL', - 'mmCP_STREAM_OUT_CONTROL_BASE_IDX', 'mmCP_STRMOUT_CNTL', - 'mmCP_STRMOUT_CNTL_BASE_IDX', 'mmCP_ST_BASE_HI', - 'mmCP_ST_BASE_HI_BASE_IDX', 'mmCP_ST_BASE_LO', - 'mmCP_ST_BASE_LO_BASE_IDX', 'mmCP_ST_BUFSZ', - 'mmCP_ST_BUFSZ_BASE_IDX', 'mmCP_ST_CMD_BUFSZ', - 'mmCP_ST_CMD_BUFSZ_BASE_IDX', 'mmCP_SUSPEND_CNTL', - 'mmCP_SUSPEND_CNTL_BASE_IDX', 'mmCP_SUSPEND_RESUME_REQ', - 'mmCP_SUSPEND_RESUME_REQ_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_HI', - 'mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_LO', - 'mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_HI', - 'mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_LO', - 'mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_HI', - 'mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_LO', - 'mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_HI', - 'mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_LO', - 'mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_HI', - 'mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_LO', - 'mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_HI', - 'mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_LO', - 'mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_HI', - 'mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_LO', - 'mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_HI', - 'mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_LO', - 'mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VIRT_STATUS', - 'mmCP_VIRT_STATUS_BASE_IDX', 'mmCP_VMID', 'mmCP_VMID_BASE_IDX', - 'mmCP_VMID_PREEMPT', 'mmCP_VMID_PREEMPT_BASE_IDX', - 'mmCP_VMID_RESET', 'mmCP_VMID_RESET_BASE_IDX', 'mmCP_VMID_STATUS', - 'mmCP_VMID_STATUS_BASE_IDX', 'mmCP_WAIT_REG_MEM_TIMEOUT', - 'mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_HI', - 'mmCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_LO', - 'mmCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'mmCS_COPY_STATE', - 'mmCS_COPY_STATE_BASE_IDX', 'mmDB_ALPHA_TO_MASK', - 'mmDB_ALPHA_TO_MASK_BASE_IDX', 'mmDB_CGTT_CLK_CTRL_0', - 'mmDB_CGTT_CLK_CTRL_0_BASE_IDX', 'mmDB_COUNT_CONTROL', - 'mmDB_COUNT_CONTROL_BASE_IDX', 'mmDB_CREDIT_LIMIT', - 'mmDB_CREDIT_LIMIT_BASE_IDX', 'mmDB_DEBUG', 'mmDB_DEBUG2', - 'mmDB_DEBUG2_BASE_IDX', 'mmDB_DEBUG3', 'mmDB_DEBUG3_BASE_IDX', - 'mmDB_DEBUG4', 'mmDB_DEBUG4_BASE_IDX', 'mmDB_DEBUG5', - 'mmDB_DEBUG5_BASE_IDX', 'mmDB_DEBUG_BASE_IDX', - 'mmDB_DEPTH_BOUNDS_MAX', 'mmDB_DEPTH_BOUNDS_MAX_BASE_IDX', - 'mmDB_DEPTH_BOUNDS_MIN', 'mmDB_DEPTH_BOUNDS_MIN_BASE_IDX', - 'mmDB_DEPTH_CLEAR', 'mmDB_DEPTH_CLEAR_BASE_IDX', - 'mmDB_DEPTH_CONTROL', 'mmDB_DEPTH_CONTROL_BASE_IDX', - 'mmDB_DEPTH_SIZE_XY', 'mmDB_DEPTH_SIZE_XY_BASE_IDX', - 'mmDB_DEPTH_VIEW', 'mmDB_DEPTH_VIEW_BASE_IDX', 'mmDB_DFSM_CONFIG', - 'mmDB_DFSM_CONFIG_BASE_IDX', 'mmDB_DFSM_CONTROL', - 'mmDB_DFSM_CONTROL_BASE_IDX', 'mmDB_DFSM_FLUSH_AUX_EVENT', - 'mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX', 'mmDB_DFSM_FLUSH_ENABLE', - 'mmDB_DFSM_FLUSH_ENABLE_BASE_IDX', 'mmDB_DFSM_PRIMS_IN_FLIGHT', - 'mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_TILES_IN_FLIGHT', - 'mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_WATCHDOG', - 'mmDB_DFSM_WATCHDOG_BASE_IDX', 'mmDB_EQAA', 'mmDB_EQAA_BASE_IDX', - 'mmDB_EQUAD_STUTTER_CONTROL', - 'mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX', - 'mmDB_ETILE_STUTTER_CONTROL', - 'mmDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_EXCEPTION_CONTROL', - 'mmDB_EXCEPTION_CONTROL_BASE_IDX', - 'mmDB_FGCG_INTERFACES_CLK_CTRL', - 'mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX', - 'mmDB_FGCG_SRAMS_CLK_CTRL', 'mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX', - 'mmDB_FIFO_DEPTH1', 'mmDB_FIFO_DEPTH1_BASE_IDX', - 'mmDB_FIFO_DEPTH2', 'mmDB_FIFO_DEPTH2_BASE_IDX', - 'mmDB_FIFO_DEPTH3', 'mmDB_FIFO_DEPTH3_BASE_IDX', - 'mmDB_FREE_CACHELINES', 'mmDB_FREE_CACHELINES_BASE_IDX', - 'mmDB_HTILE_DATA_BASE', 'mmDB_HTILE_DATA_BASE_BASE_IDX', - 'mmDB_HTILE_DATA_BASE_HI', 'mmDB_HTILE_DATA_BASE_HI_BASE_IDX', - 'mmDB_HTILE_SURFACE', 'mmDB_HTILE_SURFACE_BASE_IDX', - 'mmDB_LAST_OF_BURST_CONFIG', 'mmDB_LAST_OF_BURST_CONFIG_BASE_IDX', - 'mmDB_LQUAD_STUTTER_CONTROL', - 'mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX', - 'mmDB_LTILE_STUTTER_CONTROL', - 'mmDB_LTILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_MEM_ARB_WATERMARKS', - 'mmDB_MEM_ARB_WATERMARKS_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_HI', - 'mmDB_OCCLUSION_COUNT0_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_LOW', - 'mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_HI', - 'mmDB_OCCLUSION_COUNT1_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_LOW', - 'mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_HI', - 'mmDB_OCCLUSION_COUNT2_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_LOW', - 'mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_HI', - 'mmDB_OCCLUSION_COUNT3_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_LOW', - 'mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'mmDB_PERFCOUNTER0_HI', - 'mmDB_PERFCOUNTER0_HI_BASE_IDX', 'mmDB_PERFCOUNTER0_LO', - 'mmDB_PERFCOUNTER0_LO_BASE_IDX', 'mmDB_PERFCOUNTER0_SELECT', - 'mmDB_PERFCOUNTER0_SELECT1', 'mmDB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmDB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER1_HI', - 'mmDB_PERFCOUNTER1_HI_BASE_IDX', 'mmDB_PERFCOUNTER1_LO', - 'mmDB_PERFCOUNTER1_LO_BASE_IDX', 'mmDB_PERFCOUNTER1_SELECT', - 'mmDB_PERFCOUNTER1_SELECT1', 'mmDB_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmDB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER2_HI', - 'mmDB_PERFCOUNTER2_HI_BASE_IDX', 'mmDB_PERFCOUNTER2_LO', - 'mmDB_PERFCOUNTER2_LO_BASE_IDX', 'mmDB_PERFCOUNTER2_SELECT', - 'mmDB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER3_HI', - 'mmDB_PERFCOUNTER3_HI_BASE_IDX', 'mmDB_PERFCOUNTER3_LO', - 'mmDB_PERFCOUNTER3_LO_BASE_IDX', 'mmDB_PERFCOUNTER3_SELECT', - 'mmDB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmDB_PRELOAD_CONTROL', - 'mmDB_PRELOAD_CONTROL_BASE_IDX', 'mmDB_RENDER_CONTROL', - 'mmDB_RENDER_CONTROL_BASE_IDX', 'mmDB_RENDER_OVERRIDE', - 'mmDB_RENDER_OVERRIDE2', 'mmDB_RENDER_OVERRIDE2_BASE_IDX', - 'mmDB_RENDER_OVERRIDE_BASE_IDX', 'mmDB_RESERVED_REG_1', - 'mmDB_RESERVED_REG_1_BASE_IDX', 'mmDB_RESERVED_REG_2', - 'mmDB_RESERVED_REG_2_BASE_IDX', 'mmDB_RESERVED_REG_3', - 'mmDB_RESERVED_REG_3_BASE_IDX', 'mmDB_RING_CONTROL', - 'mmDB_RING_CONTROL_BASE_IDX', 'mmDB_RMI_BC_GL2_CACHE_CONTROL', - 'mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX', - 'mmDB_RMI_L2_CACHE_CONTROL', 'mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX', - 'mmDB_SHADER_CONTROL', 'mmDB_SHADER_CONTROL_BASE_IDX', - 'mmDB_SRESULTS_COMPARE_STATE0', - 'mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX', - 'mmDB_SRESULTS_COMPARE_STATE1', - 'mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'mmDB_STENCILREFMASK', - 'mmDB_STENCILREFMASK_BASE_IDX', 'mmDB_STENCILREFMASK_BF', - 'mmDB_STENCILREFMASK_BF_BASE_IDX', 'mmDB_STENCIL_CLEAR', - 'mmDB_STENCIL_CLEAR_BASE_IDX', 'mmDB_STENCIL_CONTROL', - 'mmDB_STENCIL_CONTROL_BASE_IDX', 'mmDB_STENCIL_INFO', - 'mmDB_STENCIL_INFO_BASE_IDX', 'mmDB_STENCIL_READ_BASE', - 'mmDB_STENCIL_READ_BASE_BASE_IDX', 'mmDB_STENCIL_READ_BASE_HI', - 'mmDB_STENCIL_READ_BASE_HI_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE', - 'mmDB_STENCIL_WRITE_BASE_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE_HI', - 'mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'mmDB_SUBTILE_CONTROL', - 'mmDB_SUBTILE_CONTROL_BASE_IDX', 'mmDB_VRS_OVERRIDE_CNTL', - 'mmDB_VRS_OVERRIDE_CNTL_BASE_IDX', 'mmDB_WATERMARKS', - 'mmDB_WATERMARKS_BASE_IDX', 'mmDB_ZPASS_COUNT_HI', - 'mmDB_ZPASS_COUNT_HI_BASE_IDX', 'mmDB_ZPASS_COUNT_LOW', - 'mmDB_ZPASS_COUNT_LOW_BASE_IDX', 'mmDB_Z_INFO', - 'mmDB_Z_INFO_BASE_IDX', 'mmDB_Z_READ_BASE', - 'mmDB_Z_READ_BASE_BASE_IDX', 'mmDB_Z_READ_BASE_HI', - 'mmDB_Z_READ_BASE_HI_BASE_IDX', 'mmDB_Z_WRITE_BASE', - 'mmDB_Z_WRITE_BASE_BASE_IDX', 'mmDB_Z_WRITE_BASE_HI', - 'mmDB_Z_WRITE_BASE_HI_BASE_IDX', 'mmDIDT_INDEX_AUTO_INCR_EN', - 'mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'mmDIDT_IND_DATA', - 'mmDIDT_IND_DATA_BASE_IDX', 'mmDIDT_IND_INDEX', - 'mmDIDT_IND_INDEX_BASE_IDX', 'mmEDC_HYSTERESIS_CNTL', - 'mmEDC_HYSTERESIS_CNTL_BASE_IDX', 'mmEDC_HYSTERESIS_STAT', - 'mmEDC_HYSTERESIS_STAT_BASE_IDX', 'mmEDC_PERF_COUNTER', - 'mmEDC_PERF_COUNTER_BASE_IDX', 'mmGB_ADDR_CONFIG', - 'mmGB_ADDR_CONFIG_BASE_IDX', 'mmGB_ADDR_CONFIG_READ', - 'mmGB_ADDR_CONFIG_READ_BASE_IDX', 'mmGB_BACKEND_MAP', - 'mmGB_BACKEND_MAP_BASE_IDX', 'mmGB_EDC_MODE', - 'mmGB_EDC_MODE_BASE_IDX', 'mmGB_GPU_ID', 'mmGB_GPU_ID_BASE_IDX', - 'mmGCEA_CGTT_CLK_CTRL', 'mmGCEA_CGTT_CLK_CTRL_BASE_IDX', - 'mmGCEA_DRAM_PAGE_BURST', 'mmGCEA_DRAM_PAGE_BURST_BASE_IDX', - 'mmGCEA_DRAM_RD_CAM_CNTL', 'mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', - 'mmGCEA_DRAM_RD_CLI2GRP_MAP0', - 'mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', - 'mmGCEA_DRAM_RD_CLI2GRP_MAP1', - 'mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', - 'mmGCEA_DRAM_RD_GRP2VC_MAP', 'mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', - 'mmGCEA_DRAM_RD_LAZY', 'mmGCEA_DRAM_RD_LAZY_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_AGE', 'mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_FIXED', 'mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI1', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI2', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI3', - 'mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_QUEUING', - 'mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', - 'mmGCEA_DRAM_RD_PRI_URGENCY', - 'mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', 'mmGCEA_DRAM_WR_CAM_CNTL', - 'mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', 'mmGCEA_DRAM_WR_CLI2GRP_MAP0', - 'mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', - 'mmGCEA_DRAM_WR_CLI2GRP_MAP1', - 'mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', - 'mmGCEA_DRAM_WR_GRP2VC_MAP', 'mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', - 'mmGCEA_DRAM_WR_LAZY', 'mmGCEA_DRAM_WR_LAZY_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_AGE', 'mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_FIXED', 'mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI1', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI2', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI3', - 'mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_QUEUING', - 'mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', - 'mmGCEA_DRAM_WR_PRI_URGENCY', - 'mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'mmGCEA_DSM_CNTL', - 'mmGCEA_DSM_CNTL2', 'mmGCEA_DSM_CNTL2A', - 'mmGCEA_DSM_CNTL2A_BASE_IDX', 'mmGCEA_DSM_CNTL2B', - 'mmGCEA_DSM_CNTL2B_BASE_IDX', 'mmGCEA_DSM_CNTL2_BASE_IDX', - 'mmGCEA_DSM_CNTLA', 'mmGCEA_DSM_CNTLA_BASE_IDX', - 'mmGCEA_DSM_CNTLB', 'mmGCEA_DSM_CNTLB_BASE_IDX', - 'mmGCEA_DSM_CNTL_BASE_IDX', 'mmGCEA_ERR_STATUS', - 'mmGCEA_ERR_STATUS_BASE_IDX', 'mmGCEA_GL2C_XBR_CREDITS', - 'mmGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'mmGCEA_GL2C_XBR_MAXBURST', - 'mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'mmGCEA_IO_GROUP_BURST', - 'mmGCEA_IO_GROUP_BURST_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP0', - 'mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP1', - 'mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', - 'mmGCEA_IO_RD_COMBINE_FLUSH', - 'mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_RD_PRI_AGE', - 'mmGCEA_IO_RD_PRI_AGE_BASE_IDX', 'mmGCEA_IO_RD_PRI_FIXED', - 'mmGCEA_IO_RD_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_RD_PRI_QUANT_PRI1', - 'mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'mmGCEA_IO_RD_PRI_QUANT_PRI2', - 'mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'mmGCEA_IO_RD_PRI_QUANT_PRI3', - 'mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'mmGCEA_IO_RD_PRI_QUEUING', 'mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX', - 'mmGCEA_IO_RD_PRI_URGENCY', 'mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX', - 'mmGCEA_IO_RD_PRI_URGENCY_MASKING', - 'mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', - 'mmGCEA_IO_WR_CLI2GRP_MAP0', 'mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', - 'mmGCEA_IO_WR_CLI2GRP_MAP1', 'mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', - 'mmGCEA_IO_WR_COMBINE_FLUSH', - 'mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_WR_PRI_AGE', - 'mmGCEA_IO_WR_PRI_AGE_BASE_IDX', 'mmGCEA_IO_WR_PRI_FIXED', - 'mmGCEA_IO_WR_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_WR_PRI_QUANT_PRI1', - 'mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'mmGCEA_IO_WR_PRI_QUANT_PRI2', - 'mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'mmGCEA_IO_WR_PRI_QUANT_PRI3', - 'mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'mmGCEA_IO_WR_PRI_QUEUING', 'mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX', - 'mmGCEA_IO_WR_PRI_URGENCY', 'mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX', - 'mmGCEA_IO_WR_PRI_URGENCY_MASKING', - 'mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', - 'mmGCEA_LATENCY_SAMPLING', 'mmGCEA_LATENCY_SAMPLING_BASE_IDX', - 'mmGCEA_MISC', 'mmGCEA_MISC2', 'mmGCEA_MISC2_BASE_IDX', - 'mmGCEA_MISC_BASE_IDX', 'mmGCEA_PERFCOUNTER0_CFG', - 'mmGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER1_CFG', - 'mmGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER2_HI', - 'mmGCEA_PERFCOUNTER2_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER2_LO', - 'mmGCEA_PERFCOUNTER2_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER2_MODE', - 'mmGCEA_PERFCOUNTER2_MODE_BASE_IDX', 'mmGCEA_PERFCOUNTER2_SELECT', - 'mmGCEA_PERFCOUNTER2_SELECT1', - 'mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGCEA_PERFCOUNTER_HI', - 'mmGCEA_PERFCOUNTER_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER_LO', - 'mmGCEA_PERFCOUNTER_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER_RSLT_CNTL', - 'mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGCEA_PROBE_CNTL', - 'mmGCEA_PROBE_CNTL_BASE_IDX', 'mmGCEA_PROBE_MAP', - 'mmGCEA_PROBE_MAP_BASE_IDX', 'mmGCEA_RRET_MEM_RESERVE', - 'mmGCEA_RRET_MEM_RESERVE_BASE_IDX', 'mmGCMC_MEM_POWER_LS', - 'mmGCMC_MEM_POWER_LS_BASE_IDX', 'mmGCMC_SHARED_ACTIVE_FCN_ID', - 'mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX', - 'mmGCMC_SHARED_VIRT_RESET_REQ', 'mmGCMC_SHARED_VIRT_RESET_REQ2', - 'mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX', - 'mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX', 'mmGCMC_VM_AGP_BASE', - 'mmGCMC_VM_AGP_BASE_BASE_IDX', 'mmGCMC_VM_AGP_BOT', - 'mmGCMC_VM_AGP_BOT_BASE_IDX', 'mmGCMC_VM_AGP_TOP', - 'mmGCMC_VM_AGP_TOP_BASE_IDX', 'mmGCMC_VM_APT_CNTL', - 'mmGCMC_VM_APT_CNTL_BASE_IDX', - 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END', - 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', - 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START', - 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', - 'mmGCMC_VM_FB_LOCATION_BASE', - 'mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX', - 'mmGCMC_VM_FB_LOCATION_TOP', 'mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX', - 'mmGCMC_VM_FB_NOALLOC_CNTL', 'mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', - 'mmGCMC_VM_FB_OFFSET', 'mmGCMC_VM_FB_OFFSET_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF0', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF1', 'mmGCMC_VM_FB_SIZE_OFFSET_VF10', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF11', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF12', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF13', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF14', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF15', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF16', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF17', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF18', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF19', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF2', 'mmGCMC_VM_FB_SIZE_OFFSET_VF20', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF21', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF22', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF23', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF24', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF25', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF26', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF27', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF28', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF29', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF3', 'mmGCMC_VM_FB_SIZE_OFFSET_VF30', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF31', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF4', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF5', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF6', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF7', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF8', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF9', - 'mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER0_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER1_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER2_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER3_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER4_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER5_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER6_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER7_CFG', - 'mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER_HI', - 'mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER_LO', - 'mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', - 'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL', - 'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_END', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_START', - 'mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_HI_0', 'mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_HI_1', 'mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_HI_2', 'mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_HI_3', 'mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_LO_0', 'mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_LO_1', 'mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_LO_2', 'mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX', - 'mmGCMC_VM_MARC_BASE_LO_3', 'mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_HI_0', 'mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_HI_1', 'mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_HI_2', 'mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_HI_3', 'mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_LO_0', 'mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_LO_1', 'mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_LO_2', 'mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX', - 'mmGCMC_VM_MARC_LEN_LO_3', 'mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_HI_0', 'mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_HI_1', 'mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_HI_2', 'mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_HI_3', 'mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_LO_0', 'mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_LO_1', 'mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_LO_2', 'mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX', - 'mmGCMC_VM_MARC_RELOC_LO_3', 'mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX', - 'mmGCMC_VM_MX_L1_TLB_CNTL', 'mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX', - 'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2', - 'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', - 'mmGCMC_VM_NB_MMIOBASE', 'mmGCMC_VM_NB_MMIOBASE_BASE_IDX', - 'mmGCMC_VM_NB_MMIOLIMIT', 'mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX', - 'mmGCMC_VM_NB_PCI_ARB', 'mmGCMC_VM_NB_PCI_ARB_BASE_IDX', - 'mmGCMC_VM_NB_PCI_CTRL', 'mmGCMC_VM_NB_PCI_CTRL_BASE_IDX', - 'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1', - 'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', - 'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2', - 'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', 'mmGCMC_VM_STEERING', - 'mmGCMC_VM_STEERING_BASE_IDX', - 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', - 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', - 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', - 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', - 'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR', - 'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', - 'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR', - 'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', - 'mmGCMC_VM_XGMI_GPUIOV_ENABLE', - 'mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX', - 'mmGCMC_VM_XGMI_LFB_CNTL', 'mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX', - 'mmGCMC_VM_XGMI_LFB_SIZE', 'mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX', - 'mmGCRD_SA_TARGETS_DISABLE', 'mmGCRD_SA_TARGETS_DISABLE_BASE_IDX', - 'mmGCR_CGTT_SCLK_CTRL', 'mmGCR_CGTT_SCLK_CTRL_BASE_IDX', - 'mmGCR_CMD_STATUS', 'mmGCR_CMD_STATUS_BASE_IDX', - 'mmGCR_GENERAL_CNTL', 'mmGCR_GENERAL_CNTL_BASE_IDX', - 'mmGCR_PERFCOUNTER0_HI', 'mmGCR_PERFCOUNTER0_HI_BASE_IDX', - 'mmGCR_PERFCOUNTER0_LO', 'mmGCR_PERFCOUNTER0_LO_BASE_IDX', - 'mmGCR_PERFCOUNTER0_SELECT', 'mmGCR_PERFCOUNTER0_SELECT1', - 'mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGCR_PERFCOUNTER1_HI', - 'mmGCR_PERFCOUNTER1_HI_BASE_IDX', 'mmGCR_PERFCOUNTER1_LO', - 'mmGCR_PERFCOUNTER1_LO_BASE_IDX', 'mmGCR_PERFCOUNTER1_SELECT', - 'mmGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGCR_PIO_CNTL', - 'mmGCR_PIO_CNTL_BASE_IDX', 'mmGCR_PIO_DATA', - 'mmGCR_PIO_DATA_BASE_IDX', 'mmGCR_SPARE', 'mmGCR_SPARE_BASE_IDX', - 'mmGCUTCL2_HARVEST_BYPASS_GROUPS', - 'mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', - 'mmGCUTCL2_PERFCOUNTER0_CFG', - 'mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX', - 'mmGCUTCL2_PERFCOUNTER1_CFG', - 'mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX', - 'mmGCUTCL2_PERFCOUNTER2_CFG', - 'mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX', - 'mmGCUTCL2_PERFCOUNTER3_CFG', - 'mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_HI', - 'mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_LO', - 'mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX', - 'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL', - 'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID', - 'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', - 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_0_HI', - 'mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_0_LO', - 'mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_0_MODE', - 'mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_0_SELECT', - 'mmGCVML2_PERFCOUNTER2_0_SELECT1', - 'mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_1_HI', - 'mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_1_LO', - 'mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_1_MODE', - 'mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_1_SELECT', - 'mmGCVML2_PERFCOUNTER2_1_SELECT1', - 'mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX', - 'mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX', - 'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT', - 'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'mmGCVML2_WALKER_MACRO_THROTTLE_TIME', - 'mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX', - 'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT', - 'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'mmGCVML2_WALKER_MICRO_THROTTLE_TIME', - 'mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX', - 'mmGCVM_CONTEXT0_CNTL', 'mmGCVM_CONTEXT0_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT10_CNTL', 'mmGCVM_CONTEXT10_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT11_CNTL', 'mmGCVM_CONTEXT11_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT12_CNTL', 'mmGCVM_CONTEXT12_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT13_CNTL', 'mmGCVM_CONTEXT13_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT14_CNTL', 'mmGCVM_CONTEXT14_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT15_CNTL', 'mmGCVM_CONTEXT15_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT1_CNTL', 'mmGCVM_CONTEXT1_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT2_CNTL', 'mmGCVM_CONTEXT2_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT3_CNTL', 'mmGCVM_CONTEXT3_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT4_CNTL', 'mmGCVM_CONTEXT4_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT5_CNTL', 'mmGCVM_CONTEXT5_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT6_CNTL', 'mmGCVM_CONTEXT6_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT7_CNTL', 'mmGCVM_CONTEXT7_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT8_CNTL', 'mmGCVM_CONTEXT8_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT9_CNTL', 'mmGCVM_CONTEXT9_CNTL_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', - 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'mmGCVM_CONTEXTS_DISABLE', 'mmGCVM_CONTEXTS_DISABLE_BASE_IDX', - 'mmGCVM_DEBUG', 'mmGCVM_DEBUG_BASE_IDX', - 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32', - 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', - 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32', - 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', - 'mmGCVM_DUMMY_PAGE_FAULT_CNTL', - 'mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_CNTL', - 'mmGCVM_INVALIDATE_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_ENG0_ACK', - 'mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG0_REQ', - 'mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG0_SEM', - 'mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG10_ACK', - 'mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG10_REQ', - 'mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG10_SEM', - 'mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG11_ACK', - 'mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG11_REQ', - 'mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG11_SEM', - 'mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG12_ACK', - 'mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG12_REQ', - 'mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG12_SEM', - 'mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG13_ACK', - 'mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG13_REQ', - 'mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG13_SEM', - 'mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG14_ACK', - 'mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG14_REQ', - 'mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG14_SEM', - 'mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG15_ACK', - 'mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG15_REQ', - 'mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG15_SEM', - 'mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG16_ACK', - 'mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG16_REQ', - 'mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG16_SEM', - 'mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG17_ACK', - 'mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG17_REQ', - 'mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG17_SEM', - 'mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG1_ACK', - 'mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG1_REQ', - 'mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG1_SEM', - 'mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG2_ACK', - 'mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG2_REQ', - 'mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG2_SEM', - 'mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG3_ACK', - 'mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG3_REQ', - 'mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG3_SEM', - 'mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG4_ACK', - 'mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG4_REQ', - 'mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG4_SEM', - 'mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG5_ACK', - 'mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG5_REQ', - 'mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG5_SEM', - 'mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG6_ACK', - 'mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG6_REQ', - 'mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG6_SEM', - 'mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG7_ACK', - 'mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG7_REQ', - 'mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG7_SEM', - 'mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG8_ACK', - 'mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG8_REQ', - 'mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG8_SEM', - 'mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG9_ACK', - 'mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', - 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', - 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG9_REQ', - 'mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX', - 'mmGCVM_INVALIDATE_ENG9_SEM', - 'mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX', - 'mmGCVM_IOMMU_CONTROL_REGISTER', - 'mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX', - 'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE', - 'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX', - 'mmGCVM_IOMMU_MMIO_CNTRL_1', 'mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX', - 'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER', - 'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX', - 'mmGCVM_L2_BANK_SELECT_RESERVED_CID', - 'mmGCVM_L2_BANK_SELECT_RESERVED_CID2', - 'mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', - 'mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', - 'mmGCVM_L2_CACHE_PARITY_CNTL', - 'mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', 'mmGCVM_L2_CNTL', - 'mmGCVM_L2_CNTL2', 'mmGCVM_L2_CNTL2_BASE_IDX', 'mmGCVM_L2_CNTL3', - 'mmGCVM_L2_CNTL3_BASE_IDX', 'mmGCVM_L2_CNTL4', - 'mmGCVM_L2_CNTL4_BASE_IDX', 'mmGCVM_L2_CNTL5', - 'mmGCVM_L2_CNTL5_BASE_IDX', 'mmGCVM_L2_CNTL_BASE_IDX', - 'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', - 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', - 'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', - 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', - 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', - 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', - 'mmGCVM_L2_GCR_CNTL', 'mmGCVM_L2_GCR_CNTL_BASE_IDX', - 'mmGCVM_L2_ID_CTRL0', 'mmGCVM_L2_ID_CTRL0_BASE_IDX', - 'mmGCVM_L2_ID_CTRL1', 'mmGCVM_L2_ID_CTRL1_BASE_IDX', - 'mmGCVM_L2_ID_CTRL2', 'mmGCVM_L2_ID_CTRL2_BASE_IDX', - 'mmGCVM_L2_ID_CTRL3', 'mmGCVM_L2_ID_CTRL3_BASE_IDX', - 'mmGCVM_L2_ID_CTRL4', 'mmGCVM_L2_ID_CTRL4_BASE_IDX', - 'mmGCVM_L2_ID_CTRL5', 'mmGCVM_L2_ID_CTRL5_BASE_IDX', - 'mmGCVM_L2_ID_CTRL6', 'mmGCVM_L2_ID_CTRL6_BASE_IDX', - 'mmGCVM_L2_ID_CTRL7', 'mmGCVM_L2_ID_CTRL7_BASE_IDX', - 'mmGCVM_L2_ID_CTRL_HI', 'mmGCVM_L2_ID_CTRL_HI_BASE_IDX', - 'mmGCVM_L2_ID_STATUS', 'mmGCVM_L2_ID_STATUS_BASE_IDX', - 'mmGCVM_L2_IH_LOG_CNTL', 'mmGCVM_L2_IH_LOG_CNTL_BASE_IDX', - 'mmGCVM_L2_MM_GROUP_RT_CLASSES', - 'mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', - 'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32', - 'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32', - 'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_CNTL', - 'mmGCVM_L2_PROTECTION_FAULT_CNTL2', - 'mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', - 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', - 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3', - 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4', - 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', - 'mmGCVM_L2_PROTECTION_FAULT_STATUS', - 'mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', - 'mmGCVM_L2_PTE_CACHE_DUMP_CNTL', - 'mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', - 'mmGCVM_L2_PTE_CACHE_DUMP_READ', - 'mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'mmGCVM_L2_STATUS', - 'mmGCVM_L2_STATUS_BASE_IDX', 'mmGC_CAC_AGGR_LOWER', - 'mmGC_CAC_AGGR_LOWER_BASE_IDX', 'mmGC_CAC_AGGR_UPPER', - 'mmGC_CAC_AGGR_UPPER_BASE_IDX', 'mmGC_CAC_CGTT_CLK_CTRL', - 'mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX', 'mmGC_CAC_CTRL_1', - 'mmGC_CAC_CTRL_1_BASE_IDX', 'mmGC_CAC_CTRL_2', - 'mmGC_CAC_CTRL_2_BASE_IDX', 'mmGC_CAC_IND_DATA', - 'mmGC_CAC_IND_DATA_BASE_IDX', 'mmGC_CAC_IND_INDEX', - 'mmGC_CAC_IND_INDEX_BASE_IDX', 'mmGC_CAC_SOFT_CTRL', - 'mmGC_CAC_SOFT_CTRL_BASE_IDX', 'mmGC_EDC_CTRL', - 'mmGC_EDC_CTRL_BASE_IDX', 'mmGC_EDC_OVERFLOW', - 'mmGC_EDC_OVERFLOW_BASE_IDX', 'mmGC_EDC_ROLLING_POWER_DELTA', - 'mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'mmGC_EDC_STATUS', - 'mmGC_EDC_STATUS_BASE_IDX', 'mmGC_EDC_STRETCH_CTRL', - 'mmGC_EDC_STRETCH_CTRL_BASE_IDX', 'mmGC_EDC_STRETCH_THRESHOLD', - 'mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'mmGC_EDC_THRESHOLD', - 'mmGC_EDC_THRESHOLD_BASE_IDX', 'mmGC_IH_COOKIE_0_PTR', - 'mmGC_IH_COOKIE_0_PTR_BASE_IDX', 'mmGC_THROTTLE_CTRL', - 'mmGC_THROTTLE_CTRL1', 'mmGC_THROTTLE_CTRL1_BASE_IDX', - 'mmGC_THROTTLE_CTRL_BASE_IDX', 'mmGC_THROTTLE_STATUS', - 'mmGC_THROTTLE_STATUS_BASE_IDX', 'mmGC_USER_PRIM_CONFIG', - 'mmGC_USER_PRIM_CONFIG_BASE_IDX', 'mmGC_USER_RB_BACKEND_DISABLE', - 'mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX', - 'mmGC_USER_RB_REDUNDANCY', 'mmGC_USER_RB_REDUNDANCY_BASE_IDX', - 'mmGC_USER_RMI_REDUNDANCY', 'mmGC_USER_RMI_REDUNDANCY_BASE_IDX', - 'mmGC_USER_SA_UNIT_DISABLE', 'mmGC_USER_SA_UNIT_DISABLE_BASE_IDX', - 'mmGC_USER_SHADER_ARRAY_CONFIG', - 'mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', - 'mmGC_USER_SHADER_RATE_CONFIG', - 'mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'mmGDS_ATOM_BASE', - 'mmGDS_ATOM_BASE_BASE_IDX', 'mmGDS_ATOM_CNTL', - 'mmGDS_ATOM_CNTL_BASE_IDX', 'mmGDS_ATOM_COMPLETE', - 'mmGDS_ATOM_COMPLETE_BASE_IDX', 'mmGDS_ATOM_DST', - 'mmGDS_ATOM_DST_BASE_IDX', 'mmGDS_ATOM_OFFSET0', - 'mmGDS_ATOM_OFFSET0_BASE_IDX', 'mmGDS_ATOM_OFFSET1', - 'mmGDS_ATOM_OFFSET1_BASE_IDX', 'mmGDS_ATOM_OP', - 'mmGDS_ATOM_OP_BASE_IDX', 'mmGDS_ATOM_READ0', - 'mmGDS_ATOM_READ0_BASE_IDX', 'mmGDS_ATOM_READ0_U', - 'mmGDS_ATOM_READ0_U_BASE_IDX', 'mmGDS_ATOM_READ1', - 'mmGDS_ATOM_READ1_BASE_IDX', 'mmGDS_ATOM_READ1_U', - 'mmGDS_ATOM_READ1_U_BASE_IDX', 'mmGDS_ATOM_SIZE', - 'mmGDS_ATOM_SIZE_BASE_IDX', 'mmGDS_ATOM_SRC0', - 'mmGDS_ATOM_SRC0_BASE_IDX', 'mmGDS_ATOM_SRC0_U', - 'mmGDS_ATOM_SRC0_U_BASE_IDX', 'mmGDS_ATOM_SRC1', - 'mmGDS_ATOM_SRC1_BASE_IDX', 'mmGDS_ATOM_SRC1_U', - 'mmGDS_ATOM_SRC1_U_BASE_IDX', 'mmGDS_CNTL_STATUS', - 'mmGDS_CNTL_STATUS_BASE_IDX', 'mmGDS_COMPUTE_MAX_WAVE_ID', - 'mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'mmGDS_CONFIG', - 'mmGDS_CONFIG_BASE_IDX', 'mmGDS_CS_CTXSW_CNT0', - 'mmGDS_CS_CTXSW_CNT0_BASE_IDX', 'mmGDS_CS_CTXSW_CNT1', - 'mmGDS_CS_CTXSW_CNT1_BASE_IDX', 'mmGDS_CS_CTXSW_CNT2', - 'mmGDS_CS_CTXSW_CNT2_BASE_IDX', 'mmGDS_CS_CTXSW_CNT3', - 'mmGDS_CS_CTXSW_CNT3_BASE_IDX', 'mmGDS_CS_CTXSW_STATUS', - 'mmGDS_CS_CTXSW_STATUS_BASE_IDX', 'mmGDS_DSM_CNTL', - 'mmGDS_DSM_CNTL2', 'mmGDS_DSM_CNTL2_BASE_IDX', - 'mmGDS_DSM_CNTL_BASE_IDX', 'mmGDS_EDC_CNT', - 'mmGDS_EDC_CNT_BASE_IDX', 'mmGDS_EDC_GRBM_CNT', - 'mmGDS_EDC_GRBM_CNT_BASE_IDX', 'mmGDS_EDC_OA_DED', - 'mmGDS_EDC_OA_DED_BASE_IDX', 'mmGDS_EDC_OA_PHY_CNT', - 'mmGDS_EDC_OA_PHY_CNT_BASE_IDX', 'mmGDS_EDC_OA_PIPE_CNT', - 'mmGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'mmGDS_ENHANCE', - 'mmGDS_ENHANCE2', 'mmGDS_ENHANCE2_BASE_IDX', - 'mmGDS_ENHANCE_BASE_IDX', 'mmGDS_GFX_CTXSW_STATUS', - 'mmGDS_GFX_CTXSW_STATUS_BASE_IDX', 'mmGDS_GS_CTXSW_CNT0', - 'mmGDS_GS_CTXSW_CNT0_BASE_IDX', 'mmGDS_GS_CTXSW_CNT1', - 'mmGDS_GS_CTXSW_CNT1_BASE_IDX', 'mmGDS_GS_CTXSW_CNT2', - 'mmGDS_GS_CTXSW_CNT2_BASE_IDX', 'mmGDS_GS_CTXSW_CNT3', - 'mmGDS_GS_CTXSW_CNT3_BASE_IDX', 'mmGDS_GWS_RESET0', - 'mmGDS_GWS_RESET0_BASE_IDX', 'mmGDS_GWS_RESET1', - 'mmGDS_GWS_RESET1_BASE_IDX', 'mmGDS_GWS_RESOURCE', - 'mmGDS_GWS_RESOURCE_BASE_IDX', 'mmGDS_GWS_RESOURCE_CNT', - 'mmGDS_GWS_RESOURCE_CNTL', 'mmGDS_GWS_RESOURCE_CNTL_BASE_IDX', - 'mmGDS_GWS_RESOURCE_CNT_BASE_IDX', 'mmGDS_GWS_RESOURCE_RESET', - 'mmGDS_GWS_RESOURCE_RESET_BASE_IDX', 'mmGDS_GWS_VMID0', - 'mmGDS_GWS_VMID0_BASE_IDX', 'mmGDS_GWS_VMID1', 'mmGDS_GWS_VMID10', - 'mmGDS_GWS_VMID10_BASE_IDX', 'mmGDS_GWS_VMID11', - 'mmGDS_GWS_VMID11_BASE_IDX', 'mmGDS_GWS_VMID12', - 'mmGDS_GWS_VMID12_BASE_IDX', 'mmGDS_GWS_VMID13', - 'mmGDS_GWS_VMID13_BASE_IDX', 'mmGDS_GWS_VMID14', - 'mmGDS_GWS_VMID14_BASE_IDX', 'mmGDS_GWS_VMID15', - 'mmGDS_GWS_VMID15_BASE_IDX', 'mmGDS_GWS_VMID1_BASE_IDX', - 'mmGDS_GWS_VMID2', 'mmGDS_GWS_VMID2_BASE_IDX', 'mmGDS_GWS_VMID3', - 'mmGDS_GWS_VMID3_BASE_IDX', 'mmGDS_GWS_VMID4', - 'mmGDS_GWS_VMID4_BASE_IDX', 'mmGDS_GWS_VMID5', - 'mmGDS_GWS_VMID5_BASE_IDX', 'mmGDS_GWS_VMID6', - 'mmGDS_GWS_VMID6_BASE_IDX', 'mmGDS_GWS_VMID7', - 'mmGDS_GWS_VMID7_BASE_IDX', 'mmGDS_GWS_VMID8', - 'mmGDS_GWS_VMID8_BASE_IDX', 'mmGDS_GWS_VMID9', - 'mmGDS_GWS_VMID9_BASE_IDX', 'mmGDS_MEMORY_CLEAN', - 'mmGDS_MEMORY_CLEAN_BASE_IDX', 'mmGDS_OA_ADDRESS', - 'mmGDS_OA_ADDRESS_BASE_IDX', 'mmGDS_OA_CGPG_RESTORE', - 'mmGDS_OA_CGPG_RESTORE_BASE_IDX', 'mmGDS_OA_CNTL', - 'mmGDS_OA_CNTL_BASE_IDX', 'mmGDS_OA_COUNTER', - 'mmGDS_OA_COUNTER_BASE_IDX', 'mmGDS_OA_INCDEC', - 'mmGDS_OA_INCDEC_BASE_IDX', 'mmGDS_OA_RESET', - 'mmGDS_OA_RESET_BASE_IDX', 'mmGDS_OA_RESET_MASK', - 'mmGDS_OA_RESET_MASK_BASE_IDX', 'mmGDS_OA_RING_SIZE', - 'mmGDS_OA_RING_SIZE_BASE_IDX', 'mmGDS_OA_VMID0', - 'mmGDS_OA_VMID0_BASE_IDX', 'mmGDS_OA_VMID1', 'mmGDS_OA_VMID10', - 'mmGDS_OA_VMID10_BASE_IDX', 'mmGDS_OA_VMID11', - 'mmGDS_OA_VMID11_BASE_IDX', 'mmGDS_OA_VMID12', - 'mmGDS_OA_VMID12_BASE_IDX', 'mmGDS_OA_VMID13', - 'mmGDS_OA_VMID13_BASE_IDX', 'mmGDS_OA_VMID14', - 'mmGDS_OA_VMID14_BASE_IDX', 'mmGDS_OA_VMID15', - 'mmGDS_OA_VMID15_BASE_IDX', 'mmGDS_OA_VMID1_BASE_IDX', - 'mmGDS_OA_VMID2', 'mmGDS_OA_VMID2_BASE_IDX', 'mmGDS_OA_VMID3', - 'mmGDS_OA_VMID3_BASE_IDX', 'mmGDS_OA_VMID4', - 'mmGDS_OA_VMID4_BASE_IDX', 'mmGDS_OA_VMID5', - 'mmGDS_OA_VMID5_BASE_IDX', 'mmGDS_OA_VMID6', - 'mmGDS_OA_VMID6_BASE_IDX', 'mmGDS_OA_VMID7', - 'mmGDS_OA_VMID7_BASE_IDX', 'mmGDS_OA_VMID8', - 'mmGDS_OA_VMID8_BASE_IDX', 'mmGDS_OA_VMID9', - 'mmGDS_OA_VMID9_BASE_IDX', 'mmGDS_PERFCOUNTER0_HI', - 'mmGDS_PERFCOUNTER0_HI_BASE_IDX', 'mmGDS_PERFCOUNTER0_LO', - 'mmGDS_PERFCOUNTER0_LO_BASE_IDX', 'mmGDS_PERFCOUNTER0_SELECT', - 'mmGDS_PERFCOUNTER0_SELECT1', - 'mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER1_HI', - 'mmGDS_PERFCOUNTER1_HI_BASE_IDX', 'mmGDS_PERFCOUNTER1_LO', - 'mmGDS_PERFCOUNTER1_LO_BASE_IDX', 'mmGDS_PERFCOUNTER1_SELECT', - 'mmGDS_PERFCOUNTER1_SELECT1', - 'mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER2_HI', - 'mmGDS_PERFCOUNTER2_HI_BASE_IDX', 'mmGDS_PERFCOUNTER2_LO', - 'mmGDS_PERFCOUNTER2_LO_BASE_IDX', 'mmGDS_PERFCOUNTER2_SELECT', - 'mmGDS_PERFCOUNTER2_SELECT1', - 'mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER3_HI', - 'mmGDS_PERFCOUNTER3_HI_BASE_IDX', 'mmGDS_PERFCOUNTER3_LO', - 'mmGDS_PERFCOUNTER3_LO_BASE_IDX', 'mmGDS_PERFCOUNTER3_SELECT', - 'mmGDS_PERFCOUNTER3_SELECT1', - 'mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGDS_PROTECTION_FAULT', - 'mmGDS_PROTECTION_FAULT_BASE_IDX', 'mmGDS_PS_CTXSW_CNT0', - 'mmGDS_PS_CTXSW_CNT0_BASE_IDX', 'mmGDS_PS_CTXSW_CNT1', - 'mmGDS_PS_CTXSW_CNT1_BASE_IDX', 'mmGDS_PS_CTXSW_CNT2', - 'mmGDS_PS_CTXSW_CNT2_BASE_IDX', 'mmGDS_PS_CTXSW_CNT3', - 'mmGDS_PS_CTXSW_CNT3_BASE_IDX', 'mmGDS_PS_CTXSW_IDX', - 'mmGDS_PS_CTXSW_IDX_BASE_IDX', 'mmGDS_RD_ADDR', - 'mmGDS_RD_ADDR_BASE_IDX', 'mmGDS_RD_BURST_ADDR', - 'mmGDS_RD_BURST_ADDR_BASE_IDX', 'mmGDS_RD_BURST_COUNT', - 'mmGDS_RD_BURST_COUNT_BASE_IDX', 'mmGDS_RD_BURST_DATA', - 'mmGDS_RD_BURST_DATA_BASE_IDX', 'mmGDS_RD_DATA', - 'mmGDS_RD_DATA_BASE_IDX', 'mmGDS_VMID0_BASE', - 'mmGDS_VMID0_BASE_BASE_IDX', 'mmGDS_VMID0_SIZE', - 'mmGDS_VMID0_SIZE_BASE_IDX', 'mmGDS_VMID10_BASE', - 'mmGDS_VMID10_BASE_BASE_IDX', 'mmGDS_VMID10_SIZE', - 'mmGDS_VMID10_SIZE_BASE_IDX', 'mmGDS_VMID11_BASE', - 'mmGDS_VMID11_BASE_BASE_IDX', 'mmGDS_VMID11_SIZE', - 'mmGDS_VMID11_SIZE_BASE_IDX', 'mmGDS_VMID12_BASE', - 'mmGDS_VMID12_BASE_BASE_IDX', 'mmGDS_VMID12_SIZE', - 'mmGDS_VMID12_SIZE_BASE_IDX', 'mmGDS_VMID13_BASE', - 'mmGDS_VMID13_BASE_BASE_IDX', 'mmGDS_VMID13_SIZE', - 'mmGDS_VMID13_SIZE_BASE_IDX', 'mmGDS_VMID14_BASE', - 'mmGDS_VMID14_BASE_BASE_IDX', 'mmGDS_VMID14_SIZE', - 'mmGDS_VMID14_SIZE_BASE_IDX', 'mmGDS_VMID15_BASE', - 'mmGDS_VMID15_BASE_BASE_IDX', 'mmGDS_VMID15_SIZE', - 'mmGDS_VMID15_SIZE_BASE_IDX', 'mmGDS_VMID1_BASE', - 'mmGDS_VMID1_BASE_BASE_IDX', 'mmGDS_VMID1_SIZE', - 'mmGDS_VMID1_SIZE_BASE_IDX', 'mmGDS_VMID2_BASE', - 'mmGDS_VMID2_BASE_BASE_IDX', 'mmGDS_VMID2_SIZE', - 'mmGDS_VMID2_SIZE_BASE_IDX', 'mmGDS_VMID3_BASE', - 'mmGDS_VMID3_BASE_BASE_IDX', 'mmGDS_VMID3_SIZE', - 'mmGDS_VMID3_SIZE_BASE_IDX', 'mmGDS_VMID4_BASE', - 'mmGDS_VMID4_BASE_BASE_IDX', 'mmGDS_VMID4_SIZE', - 'mmGDS_VMID4_SIZE_BASE_IDX', 'mmGDS_VMID5_BASE', - 'mmGDS_VMID5_BASE_BASE_IDX', 'mmGDS_VMID5_SIZE', - 'mmGDS_VMID5_SIZE_BASE_IDX', 'mmGDS_VMID6_BASE', - 'mmGDS_VMID6_BASE_BASE_IDX', 'mmGDS_VMID6_SIZE', - 'mmGDS_VMID6_SIZE_BASE_IDX', 'mmGDS_VMID7_BASE', - 'mmGDS_VMID7_BASE_BASE_IDX', 'mmGDS_VMID7_SIZE', - 'mmGDS_VMID7_SIZE_BASE_IDX', 'mmGDS_VMID8_BASE', - 'mmGDS_VMID8_BASE_BASE_IDX', 'mmGDS_VMID8_SIZE', - 'mmGDS_VMID8_SIZE_BASE_IDX', 'mmGDS_VMID9_BASE', - 'mmGDS_VMID9_BASE_BASE_IDX', 'mmGDS_VMID9_SIZE', - 'mmGDS_VMID9_SIZE_BASE_IDX', 'mmGDS_VM_PROTECTION_FAULT', - 'mmGDS_VM_PROTECTION_FAULT_BASE_IDX', 'mmGDS_VS_CTXSW_CNT0', - 'mmGDS_VS_CTXSW_CNT0_BASE_IDX', 'mmGDS_VS_CTXSW_CNT1', - 'mmGDS_VS_CTXSW_CNT1_BASE_IDX', 'mmGDS_VS_CTXSW_CNT2', - 'mmGDS_VS_CTXSW_CNT2_BASE_IDX', 'mmGDS_VS_CTXSW_CNT3', - 'mmGDS_VS_CTXSW_CNT3_BASE_IDX', 'mmGDS_WD_GDS_CSB', - 'mmGDS_WD_GDS_CSB_BASE_IDX', 'mmGDS_WRITE_COMPLETE', - 'mmGDS_WRITE_COMPLETE_BASE_IDX', 'mmGDS_WR_ADDR', - 'mmGDS_WR_ADDR_BASE_IDX', 'mmGDS_WR_BURST_ADDR', - 'mmGDS_WR_BURST_ADDR_BASE_IDX', 'mmGDS_WR_BURST_DATA', - 'mmGDS_WR_BURST_DATA_BASE_IDX', 'mmGDS_WR_DATA', - 'mmGDS_WR_DATA_BASE_IDX', 'mmGE1_PERFCOUNTER0_HI', - 'mmGE1_PERFCOUNTER0_HI_BASE_IDX', 'mmGE1_PERFCOUNTER0_LO', - 'mmGE1_PERFCOUNTER0_LO_BASE_IDX', 'mmGE1_PERFCOUNTER0_SELECT', - 'mmGE1_PERFCOUNTER0_SELECT1', - 'mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER1_HI', - 'mmGE1_PERFCOUNTER1_HI_BASE_IDX', 'mmGE1_PERFCOUNTER1_LO', - 'mmGE1_PERFCOUNTER1_LO_BASE_IDX', 'mmGE1_PERFCOUNTER1_SELECT', - 'mmGE1_PERFCOUNTER1_SELECT1', - 'mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER2_HI', - 'mmGE1_PERFCOUNTER2_HI_BASE_IDX', 'mmGE1_PERFCOUNTER2_LO', - 'mmGE1_PERFCOUNTER2_LO_BASE_IDX', 'mmGE1_PERFCOUNTER2_SELECT', - 'mmGE1_PERFCOUNTER2_SELECT1', - 'mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER3_HI', - 'mmGE1_PERFCOUNTER3_HI_BASE_IDX', 'mmGE1_PERFCOUNTER3_LO', - 'mmGE1_PERFCOUNTER3_LO_BASE_IDX', 'mmGE1_PERFCOUNTER3_SELECT', - 'mmGE1_PERFCOUNTER3_SELECT1', - 'mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmGE1_PERFCOUNTER3_SELECT_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER0_HI', - 'mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER0_LO', - 'mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER0_SELECT', - 'mmGE2_DIST_PERFCOUNTER0_SELECT1', - 'mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER1_HI', - 'mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER1_LO', - 'mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER1_SELECT', - 'mmGE2_DIST_PERFCOUNTER1_SELECT1', - 'mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER2_HI', - 'mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER2_LO', - 'mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER2_SELECT', - 'mmGE2_DIST_PERFCOUNTER2_SELECT1', - 'mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER3_HI', - 'mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER3_LO', - 'mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER3_SELECT', - 'mmGE2_DIST_PERFCOUNTER3_SELECT1', - 'mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER0_HI', 'mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER0_LO', 'mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER0_SELECT', 'mmGE2_SE_PERFCOUNTER0_SELECT1', - 'mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER1_HI', 'mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER1_LO', 'mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER1_SELECT', 'mmGE2_SE_PERFCOUNTER1_SELECT1', - 'mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER2_HI', 'mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER2_LO', 'mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER2_SELECT', 'mmGE2_SE_PERFCOUNTER2_SELECT1', - 'mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER3_HI', 'mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER3_LO', 'mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER3_SELECT', 'mmGE2_SE_PERFCOUNTER3_SELECT1', - 'mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGE_CNTL', - 'mmGE_CNTL_BASE_IDX', 'mmGE_DMA_FIRST_INDEX', - 'mmGE_DMA_FIRST_INDEX_BASE_IDX', 'mmGE_INDX_OFFSET', - 'mmGE_INDX_OFFSET_BASE_IDX', 'mmGE_MAX_OUTPUT_PER_SUBGROUP', - 'mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'mmGE_MAX_VTX_INDX', - 'mmGE_MAX_VTX_INDX_BASE_IDX', 'mmGE_MIN_VTX_INDX', - 'mmGE_MIN_VTX_INDX_BASE_IDX', 'mmGE_MULTI_PRIM_IB_RESET_EN', - 'mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'mmGE_NGG_SUBGRP_CNTL', - 'mmGE_NGG_SUBGRP_CNTL_BASE_IDX', 'mmGE_PC_ALLOC', - 'mmGE_PC_ALLOC_BASE_IDX', 'mmGE_PC_CNTL', 'mmGE_PC_CNTL_BASE_IDX', - 'mmGE_PRIV_CONTROL', 'mmGE_PRIV_CONTROL_BASE_IDX', 'mmGE_STATUS', - 'mmGE_STATUS_BASE_IDX', 'mmGE_STEREO_CNTL', - 'mmGE_STEREO_CNTL_BASE_IDX', 'mmGE_USER_VGPR1', - 'mmGE_USER_VGPR1_BASE_IDX', 'mmGE_USER_VGPR2', - 'mmGE_USER_VGPR2_BASE_IDX', 'mmGE_USER_VGPR3', - 'mmGE_USER_VGPR3_BASE_IDX', 'mmGE_USER_VGPR_EN', - 'mmGE_USER_VGPR_EN_BASE_IDX', 'mmGFX_COPY_STATE', - 'mmGFX_COPY_STATE_BASE_IDX', 'mmGFX_PIPE_CONTROL', - 'mmGFX_PIPE_CONTROL_BASE_IDX', 'mmGFX_PIPE_PRIORITY', - 'mmGFX_PIPE_PRIORITY_BASE_IDX', 'mmGL1A_PERFCOUNTER0_HI', - 'mmGL1A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER0_LO', - 'mmGL1A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER0_SELECT', - 'mmGL1A_PERFCOUNTER0_SELECT1', - 'mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER1_HI', - 'mmGL1A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER1_LO', - 'mmGL1A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER1_SELECT', - 'mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER2_HI', - 'mmGL1A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER2_LO', - 'mmGL1A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER2_SELECT', - 'mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER3_HI', - 'mmGL1A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER3_LO', - 'mmGL1A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER3_SELECT', - 'mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER0_HI', - 'mmGL1C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER0_LO', - 'mmGL1C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER0_SELECT', - 'mmGL1C_PERFCOUNTER0_SELECT1', - 'mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER1_HI', - 'mmGL1C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER1_LO', - 'mmGL1C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER1_SELECT', - 'mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER2_HI', - 'mmGL1C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER2_LO', - 'mmGL1C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER2_SELECT', - 'mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER3_HI', - 'mmGL1C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER3_LO', - 'mmGL1C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER3_SELECT', - 'mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_STATUS', - 'mmGL1C_STATUS_BASE_IDX', 'mmGL1C_UTCL0_CNTL2', - 'mmGL1C_UTCL0_CNTL2_BASE_IDX', 'mmGL1C_UTCL0_RETRY', - 'mmGL1C_UTCL0_RETRY_BASE_IDX', 'mmGL1C_UTCL0_STATUS', - 'mmGL1C_UTCL0_STATUS_BASE_IDX', 'mmGL1_ARB_STATUS', - 'mmGL1_ARB_STATUS_BASE_IDX', 'mmGL1_DRAM_BURST_MASK', - 'mmGL1_DRAM_BURST_MASK_BASE_IDX', 'mmGL1_PIPE_STEER', - 'mmGL1_PIPE_STEER_BASE_IDX', 'mmGL2A_ADDR_MATCH_CTRL', - 'mmGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'mmGL2A_ADDR_MATCH_MASK', - 'mmGL2A_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2A_ADDR_MATCH_SIZE', - 'mmGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2A_CGTT_SCLK_CTRL', - 'mmGL2A_CGTT_SCLK_CTRL_1', 'mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX', - 'mmGL2A_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2A_PERFCOUNTER0_HI', - 'mmGL2A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER0_LO', - 'mmGL2A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER0_SELECT', - 'mmGL2A_PERFCOUNTER0_SELECT1', - 'mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER1_HI', - 'mmGL2A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER1_LO', - 'mmGL2A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER1_SELECT', - 'mmGL2A_PERFCOUNTER1_SELECT1', - 'mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER2_HI', - 'mmGL2A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER2_LO', - 'mmGL2A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER2_SELECT', - 'mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER3_HI', - 'mmGL2A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER3_LO', - 'mmGL2A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER3_SELECT', - 'mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2A_PRIORITY_CTRL', - 'mmGL2A_PRIORITY_CTRL_BASE_IDX', 'mmGL2C_ADDR_MATCH_MASK', - 'mmGL2C_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2C_ADDR_MATCH_SIZE', - 'mmGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2C_CGTT_SCLK_CTRL', - 'mmGL2C_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2C_CM_CTRL0', - 'mmGL2C_CM_CTRL0_BASE_IDX', 'mmGL2C_CM_CTRL1', - 'mmGL2C_CM_CTRL1_BASE_IDX', 'mmGL2C_CM_STALL', - 'mmGL2C_CM_STALL_BASE_IDX', 'mmGL2C_CTRL', 'mmGL2C_CTRL2', - 'mmGL2C_CTRL2_BASE_IDX', 'mmGL2C_CTRL_BASE_IDX', - 'mmGL2C_LB_CTR_CTRL', 'mmGL2C_LB_CTR_CTRL_BASE_IDX', - 'mmGL2C_LB_CTR_SEL0', 'mmGL2C_LB_CTR_SEL0_BASE_IDX', - 'mmGL2C_LB_CTR_SEL1', 'mmGL2C_LB_CTR_SEL1_BASE_IDX', - 'mmGL2C_LB_DATA0', 'mmGL2C_LB_DATA0_BASE_IDX', 'mmGL2C_LB_DATA1', - 'mmGL2C_LB_DATA1_BASE_IDX', 'mmGL2C_LB_DATA2', - 'mmGL2C_LB_DATA2_BASE_IDX', 'mmGL2C_LB_DATA3', - 'mmGL2C_LB_DATA3_BASE_IDX', 'mmGL2C_MDC_PF_FLAG_CTRL', - 'mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX', 'mmGL2C_PERFCOUNTER0_HI', - 'mmGL2C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER0_LO', - 'mmGL2C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER0_SELECT', - 'mmGL2C_PERFCOUNTER0_SELECT1', - 'mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER1_HI', - 'mmGL2C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER1_LO', - 'mmGL2C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER1_SELECT', - 'mmGL2C_PERFCOUNTER1_SELECT1', - 'mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER2_HI', - 'mmGL2C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER2_LO', - 'mmGL2C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER2_SELECT', - 'mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER3_HI', - 'mmGL2C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER3_LO', - 'mmGL2C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER3_SELECT', - 'mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2C_SOFT_RESET', - 'mmGL2C_SOFT_RESET_BASE_IDX', 'mmGL2C_WBINVL2', - 'mmGL2C_WBINVL2_BASE_IDX', 'mmGL2_PIPE_STEER_0', - 'mmGL2_PIPE_STEER_0_BASE_IDX', 'mmGL2_PIPE_STEER_1', - 'mmGL2_PIPE_STEER_1_BASE_IDX', 'mmGRBM_CAM_DATA', - 'mmGRBM_CAM_DATA_BASE_IDX', 'mmGRBM_CAM_DATA_UPPER', - 'mmGRBM_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_CAM_INDEX', - 'mmGRBM_CAM_INDEX_BASE_IDX', 'mmGRBM_CGTT_CLK_CNTL', - 'mmGRBM_CGTT_CLK_CNTL_BASE_IDX', 'mmGRBM_CHIP_REVISION', - 'mmGRBM_CHIP_REVISION_BASE_IDX', 'mmGRBM_CNTL', - 'mmGRBM_CNTL_BASE_IDX', 'mmGRBM_DSM_BYPASS', - 'mmGRBM_DSM_BYPASS_BASE_IDX', 'mmGRBM_FENCE_RANGE0', - 'mmGRBM_FENCE_RANGE0_BASE_IDX', 'mmGRBM_FENCE_RANGE1', - 'mmGRBM_FENCE_RANGE1_BASE_IDX', 'mmGRBM_GFX_CLKEN_CNTL', - 'mmGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL', - 'mmGRBM_GFX_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_DATA', - 'mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_SELECT', - 'mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'mmGRBM_GFX_INDEX', - 'mmGRBM_GFX_INDEX_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_DATA', - 'mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_SELECT', - 'mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'mmGRBM_HYP_CAM_DATA', - 'mmGRBM_HYP_CAM_DATA_BASE_IDX', 'mmGRBM_HYP_CAM_DATA_UPPER', - 'mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_HYP_CAM_INDEX', - 'mmGRBM_HYP_CAM_INDEX_BASE_IDX', 'mmGRBM_IH_CREDIT', - 'mmGRBM_IH_CREDIT_BASE_IDX', 'mmGRBM_INT_CNTL', - 'mmGRBM_INT_CNTL_BASE_IDX', 'mmGRBM_NOWHERE', - 'mmGRBM_NOWHERE_BASE_IDX', 'mmGRBM_PERFCOUNTER0_HI', - 'mmGRBM_PERFCOUNTER0_HI_BASE_IDX', 'mmGRBM_PERFCOUNTER0_LO', - 'mmGRBM_PERFCOUNTER0_LO_BASE_IDX', 'mmGRBM_PERFCOUNTER0_SELECT', - 'mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX', - 'mmGRBM_PERFCOUNTER0_SELECT_HI', - 'mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX', - 'mmGRBM_PERFCOUNTER1_HI', 'mmGRBM_PERFCOUNTER1_HI_BASE_IDX', - 'mmGRBM_PERFCOUNTER1_LO', 'mmGRBM_PERFCOUNTER1_LO_BASE_IDX', - 'mmGRBM_PERFCOUNTER1_SELECT', - 'mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX', - 'mmGRBM_PERFCOUNTER1_SELECT_HI', - 'mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'mmGRBM_PWR_CNTL', - 'mmGRBM_PWR_CNTL2', 'mmGRBM_PWR_CNTL2_BASE_IDX', - 'mmGRBM_PWR_CNTL_BASE_IDX', 'mmGRBM_READ_ERROR', - 'mmGRBM_READ_ERROR2', 'mmGRBM_READ_ERROR2_BASE_IDX', - 'mmGRBM_READ_ERROR_BASE_IDX', 'mmGRBM_SCRATCH_REG0', - 'mmGRBM_SCRATCH_REG0_BASE_IDX', 'mmGRBM_SCRATCH_REG1', - 'mmGRBM_SCRATCH_REG1_BASE_IDX', 'mmGRBM_SCRATCH_REG2', - 'mmGRBM_SCRATCH_REG2_BASE_IDX', 'mmGRBM_SCRATCH_REG3', - 'mmGRBM_SCRATCH_REG3_BASE_IDX', 'mmGRBM_SCRATCH_REG4', - 'mmGRBM_SCRATCH_REG4_BASE_IDX', 'mmGRBM_SCRATCH_REG5', - 'mmGRBM_SCRATCH_REG5_BASE_IDX', 'mmGRBM_SCRATCH_REG6', - 'mmGRBM_SCRATCH_REG6_BASE_IDX', 'mmGRBM_SCRATCH_REG7', - 'mmGRBM_SCRATCH_REG7_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_HI', - 'mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_LO', - 'mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', - 'mmGRBM_SE0_PERFCOUNTER_SELECT', - 'mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', - 'mmGRBM_SE1_PERFCOUNTER_HI', 'mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', - 'mmGRBM_SE1_PERFCOUNTER_LO', 'mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', - 'mmGRBM_SE1_PERFCOUNTER_SELECT', - 'mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', - 'mmGRBM_SE2_PERFCOUNTER_HI', 'mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', - 'mmGRBM_SE2_PERFCOUNTER_LO', 'mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', - 'mmGRBM_SE2_PERFCOUNTER_SELECT', - 'mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', - 'mmGRBM_SE3_PERFCOUNTER_HI', 'mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', - 'mmGRBM_SE3_PERFCOUNTER_LO', 'mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', - 'mmGRBM_SE3_PERFCOUNTER_SELECT', - 'mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', 'mmGRBM_SEC_CNTL', - 'mmGRBM_SEC_CNTL_BASE_IDX', 'mmGRBM_SE_REMAP_CNTL', - 'mmGRBM_SE_REMAP_CNTL_BASE_IDX', 'mmGRBM_SKEW_CNTL', - 'mmGRBM_SKEW_CNTL_BASE_IDX', 'mmGRBM_SOFT_RESET', - 'mmGRBM_SOFT_RESET_BASE_IDX', 'mmGRBM_STATUS', 'mmGRBM_STATUS2', - 'mmGRBM_STATUS2_BASE_IDX', 'mmGRBM_STATUS3', - 'mmGRBM_STATUS3_BASE_IDX', 'mmGRBM_STATUS_BASE_IDX', - 'mmGRBM_STATUS_SE0', 'mmGRBM_STATUS_SE0_BASE_IDX', - 'mmGRBM_STATUS_SE1', 'mmGRBM_STATUS_SE1_BASE_IDX', - 'mmGRBM_STATUS_SE2', 'mmGRBM_STATUS_SE2_BASE_IDX', - 'mmGRBM_STATUS_SE3', 'mmGRBM_STATUS_SE3_BASE_IDX', - 'mmGRBM_TRAP_ADDR', 'mmGRBM_TRAP_ADDR_BASE_IDX', - 'mmGRBM_TRAP_ADDR_MSK', 'mmGRBM_TRAP_ADDR_MSK_BASE_IDX', - 'mmGRBM_TRAP_OP', 'mmGRBM_TRAP_OP_BASE_IDX', 'mmGRBM_TRAP_WD', - 'mmGRBM_TRAP_WD_BASE_IDX', 'mmGRBM_TRAP_WD_MSK', - 'mmGRBM_TRAP_WD_MSK_BASE_IDX', 'mmGRBM_UTCL2_INVAL_RANGE_END', - 'mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', - 'mmGRBM_UTCL2_INVAL_RANGE_START', - 'mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', - 'mmGRBM_WAIT_IDLE_CLOCKS', 'mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', - 'mmGRBM_WRITE_ERROR', 'mmGRBM_WRITE_ERROR_BASE_IDX', - 'mmGRTAVFS_CLK_CNTL', 'mmGRTAVFS_CLK_CNTL_BASE_IDX', - 'mmGRTAVFS_GENERAL_0', 'mmGRTAVFS_GENERAL_0_BASE_IDX', - 'mmGRTAVFS_PSM_CNTL', 'mmGRTAVFS_PSM_CNTL_BASE_IDX', - 'mmGRTAVFS_RTAVFS_RD_DATA', 'mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX', - 'mmGRTAVFS_RTAVFS_REG_ADDR', 'mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', - 'mmGRTAVFS_RTAVFS_REG_CTRL', 'mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX', - 'mmGRTAVFS_RTAVFS_REG_STATUS', - 'mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX', - 'mmGRTAVFS_RTAVFS_WR_DATA', 'mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX', - 'mmGRTAVFS_SOFT_RESET', 'mmGRTAVFS_SOFT_RESET_BASE_IDX', - 'mmGRTAVFS_TARG_FREQ', 'mmGRTAVFS_TARG_FREQ_BASE_IDX', - 'mmGRTAVFS_TARG_VOLT', 'mmGRTAVFS_TARG_VOLT_BASE_IDX', - 'mmGUS_CGTT_CLK_CTRL', 'mmGUS_CGTT_CLK_CTRL_BASE_IDX', - 'mmGUS_DRAM_COMBINE_FLUSH', 'mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX', - 'mmGUS_DRAM_COMBINE_RD_WR_EN', - 'mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', 'mmGUS_DRAM_GROUP_BURST', - 'mmGUS_DRAM_GROUP_BURST_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_COEFF', - 'mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_RATE', - 'mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX', 'mmGUS_DRAM_PRI_FIXED', - 'mmGUS_DRAM_PRI_FIXED_BASE_IDX', 'mmGUS_DRAM_PRI_QUANT1_PRI1', - 'mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT1_PRI2', - 'mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT1_PRI3', - 'mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT1_PRI4', - 'mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT1_PRI5', - 'mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT_PRI1', 'mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT_PRI2', 'mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT_PRI3', 'mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT_PRI4', 'mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX', - 'mmGUS_DRAM_PRI_QUANT_PRI5', 'mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', - 'mmGUS_DRAM_PRI_QUEUING', 'mmGUS_DRAM_PRI_QUEUING_BASE_IDX', - 'mmGUS_DRAM_PRI_URGENCY_COEFF', - 'mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX', - 'mmGUS_DRAM_PRI_URGENCY_MODE', - 'mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_ERR_STATUS', - 'mmGUS_ERR_STATUS_BASE_IDX', 'mmGUS_IO_GROUP_BURST', - 'mmGUS_IO_GROUP_BURST_BASE_IDX', 'mmGUS_IO_RD_COMBINE_FLUSH', - 'mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_COEFF', - 'mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_RATE', - 'mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', 'mmGUS_IO_RD_PRI_FIXED', - 'mmGUS_IO_RD_PRI_FIXED_BASE_IDX', 'mmGUS_IO_RD_PRI_QUANT1_PRI1', - 'mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT1_PRI2', - 'mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT1_PRI3', - 'mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT1_PRI4', - 'mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT_PRI1', - 'mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT_PRI2', - 'mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT_PRI3', - 'mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'mmGUS_IO_RD_PRI_QUANT_PRI4', - 'mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_RD_PRI_QUEUING', - 'mmGUS_IO_RD_PRI_QUEUING_BASE_IDX', - 'mmGUS_IO_RD_PRI_URGENCY_COEFF', - 'mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX', - 'mmGUS_IO_RD_PRI_URGENCY_MODE', - 'mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX', - 'mmGUS_IO_WR_COMBINE_FLUSH', 'mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX', - 'mmGUS_IO_WR_PRI_AGE_COEFF', 'mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX', - 'mmGUS_IO_WR_PRI_AGE_RATE', 'mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX', - 'mmGUS_IO_WR_PRI_FIXED', 'mmGUS_IO_WR_PRI_FIXED_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT1_PRI1', - 'mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT1_PRI2', - 'mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT1_PRI3', - 'mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT1_PRI4', - 'mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT_PRI1', - 'mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT_PRI2', - 'mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT_PRI3', - 'mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'mmGUS_IO_WR_PRI_QUANT_PRI4', - 'mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_WR_PRI_QUEUING', - 'mmGUS_IO_WR_PRI_QUEUING_BASE_IDX', - 'mmGUS_IO_WR_PRI_URGENCY_COEFF', - 'mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX', - 'mmGUS_IO_WR_PRI_URGENCY_MODE', - 'mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_L1_CH0_CMD_IN', - 'mmGUS_L1_CH0_CMD_IN_BASE_IDX', 'mmGUS_L1_CH0_CMD_OUT', - 'mmGUS_L1_CH0_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_IN', - 'mmGUS_L1_CH0_DATA_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_OUT', - 'mmGUS_L1_CH0_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_IN', - 'mmGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_OUT', - 'mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_CH1_CMD_IN', - 'mmGUS_L1_CH1_CMD_IN_BASE_IDX', 'mmGUS_L1_CH1_CMD_OUT', - 'mmGUS_L1_CH1_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_IN', - 'mmGUS_L1_CH1_DATA_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_OUT', - 'mmGUS_L1_CH1_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_IN', - 'mmGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_OUT', - 'mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA0_CMD_IN', - 'mmGUS_L1_SA0_CMD_IN_BASE_IDX', 'mmGUS_L1_SA0_CMD_OUT', - 'mmGUS_L1_SA0_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_IN', - 'mmGUS_L1_SA0_DATA_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_OUT', - 'mmGUS_L1_SA0_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_IN', - 'mmGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_OUT', - 'mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA1_CMD_IN', - 'mmGUS_L1_SA1_CMD_IN_BASE_IDX', 'mmGUS_L1_SA1_CMD_OUT', - 'mmGUS_L1_SA1_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_IN', - 'mmGUS_L1_SA1_DATA_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_OUT', - 'mmGUS_L1_SA1_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_IN', - 'mmGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_OUT', - 'mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA2_CMD_IN', - 'mmGUS_L1_SA2_CMD_IN_BASE_IDX', 'mmGUS_L1_SA2_CMD_OUT', - 'mmGUS_L1_SA2_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_IN', - 'mmGUS_L1_SA2_DATA_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_OUT', - 'mmGUS_L1_SA2_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_IN', - 'mmGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_OUT', - 'mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA3_CMD_IN', - 'mmGUS_L1_SA3_CMD_IN_BASE_IDX', 'mmGUS_L1_SA3_CMD_OUT', - 'mmGUS_L1_SA3_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_IN', - 'mmGUS_L1_SA3_DATA_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_OUT', - 'mmGUS_L1_SA3_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_IN', - 'mmGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_OUT', - 'mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'mmGUS_LATENCY_SAMPLING', - 'mmGUS_LATENCY_SAMPLING_BASE_IDX', 'mmGUS_MISC', 'mmGUS_MISC2', - 'mmGUS_MISC2_BASE_IDX', 'mmGUS_MISC3', 'mmGUS_MISC3_BASE_IDX', - 'mmGUS_MISC_BASE_IDX', 'mmGUS_PERFCOUNTER0_CFG', - 'mmGUS_PERFCOUNTER0_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER1_CFG', - 'mmGUS_PERFCOUNTER1_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER2_HI', - 'mmGUS_PERFCOUNTER2_HI_BASE_IDX', 'mmGUS_PERFCOUNTER2_LO', - 'mmGUS_PERFCOUNTER2_LO_BASE_IDX', 'mmGUS_PERFCOUNTER2_MODE', - 'mmGUS_PERFCOUNTER2_MODE_BASE_IDX', 'mmGUS_PERFCOUNTER2_SELECT', - 'mmGUS_PERFCOUNTER2_SELECT1', - 'mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGUS_PERFCOUNTER_HI', - 'mmGUS_PERFCOUNTER_HI_BASE_IDX', 'mmGUS_PERFCOUNTER_LO', - 'mmGUS_PERFCOUNTER_LO_BASE_IDX', 'mmGUS_PERFCOUNTER_RSLT_CNTL', - 'mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGUS_SDP_ARB_FINAL', - 'mmGUS_SDP_ARB_FINAL_BASE_IDX', 'mmGUS_SDP_CREDITS', - 'mmGUS_SDP_CREDITS_BASE_IDX', 'mmGUS_SDP_ENABLE', - 'mmGUS_SDP_ENABLE_BASE_IDX', 'mmGUS_SDP_QOS_VC_PRIORITY', - 'mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'mmGUS_SDP_REQ_CNTL', - 'mmGUS_SDP_REQ_CNTL_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE0', - 'mmGUS_SDP_TAG_RESERVE0_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE1', - 'mmGUS_SDP_TAG_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE0', - 'mmGUS_SDP_VCC_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE1', - 'mmGUS_SDP_VCC_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE0', - 'mmGUS_SDP_VCD_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE1', - 'mmGUS_SDP_VCD_RESERVE1_BASE_IDX', 'mmGUS_WRRSP_FIFO_CNTL', - 'mmGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'mmIA_ENHANCE', - 'mmIA_ENHANCE_BASE_IDX', 'mmIA_MULTI_VGT_PARAM', - 'mmIA_MULTI_VGT_PARAM_BASE_IDX', 'mmIA_MULTI_VGT_PARAM_PIPED', - 'mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX', 'mmIA_UTCL1_CNTL', - 'mmIA_UTCL1_CNTL_BASE_IDX', 'mmIA_UTCL1_STATUS', - 'mmIA_UTCL1_STATUS_2', 'mmIA_UTCL1_STATUS_2_BASE_IDX', - 'mmIA_UTCL1_STATUS_BASE_IDX', 'mmLDS_CONFIG', - 'mmLDS_CONFIG_BASE_IDX', 'mmPA_CL_CLIP_CNTL', - 'mmPA_CL_CLIP_CNTL_BASE_IDX', 'mmPA_CL_CNTL_STATUS', - 'mmPA_CL_CNTL_STATUS_BASE_IDX', 'mmPA_CL_ENHANCE', - 'mmPA_CL_ENHANCE_BASE_IDX', 'mmPA_CL_GB_HORZ_CLIP_ADJ', - 'mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_HORZ_DISC_ADJ', - 'mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_CLIP_ADJ', - 'mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_DISC_ADJ', - 'mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'mmPA_CL_NANINF_CNTL', - 'mmPA_CL_NANINF_CNTL_BASE_IDX', 'mmPA_CL_NGG_CNTL', - 'mmPA_CL_NGG_CNTL_BASE_IDX', 'mmPA_CL_POINT_CULL_RAD', - 'mmPA_CL_POINT_CULL_RAD_BASE_IDX', 'mmPA_CL_POINT_SIZE', - 'mmPA_CL_POINT_SIZE_BASE_IDX', 'mmPA_CL_POINT_X_RAD', - 'mmPA_CL_POINT_X_RAD_BASE_IDX', 'mmPA_CL_POINT_Y_RAD', - 'mmPA_CL_POINT_Y_RAD_BASE_IDX', 'mmPA_CL_PROG_NEAR_CLIP_Z', - 'mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'mmPA_CL_UCP_0_W', - 'mmPA_CL_UCP_0_W_BASE_IDX', 'mmPA_CL_UCP_0_X', - 'mmPA_CL_UCP_0_X_BASE_IDX', 'mmPA_CL_UCP_0_Y', - 'mmPA_CL_UCP_0_Y_BASE_IDX', 'mmPA_CL_UCP_0_Z', - 'mmPA_CL_UCP_0_Z_BASE_IDX', 'mmPA_CL_UCP_1_W', - 'mmPA_CL_UCP_1_W_BASE_IDX', 'mmPA_CL_UCP_1_X', - 'mmPA_CL_UCP_1_X_BASE_IDX', 'mmPA_CL_UCP_1_Y', - 'mmPA_CL_UCP_1_Y_BASE_IDX', 'mmPA_CL_UCP_1_Z', - 'mmPA_CL_UCP_1_Z_BASE_IDX', 'mmPA_CL_UCP_2_W', - 'mmPA_CL_UCP_2_W_BASE_IDX', 'mmPA_CL_UCP_2_X', - 'mmPA_CL_UCP_2_X_BASE_IDX', 'mmPA_CL_UCP_2_Y', - 'mmPA_CL_UCP_2_Y_BASE_IDX', 'mmPA_CL_UCP_2_Z', - 'mmPA_CL_UCP_2_Z_BASE_IDX', 'mmPA_CL_UCP_3_W', - 'mmPA_CL_UCP_3_W_BASE_IDX', 'mmPA_CL_UCP_3_X', - 'mmPA_CL_UCP_3_X_BASE_IDX', 'mmPA_CL_UCP_3_Y', - 'mmPA_CL_UCP_3_Y_BASE_IDX', 'mmPA_CL_UCP_3_Z', - 'mmPA_CL_UCP_3_Z_BASE_IDX', 'mmPA_CL_UCP_4_W', - 'mmPA_CL_UCP_4_W_BASE_IDX', 'mmPA_CL_UCP_4_X', - 'mmPA_CL_UCP_4_X_BASE_IDX', 'mmPA_CL_UCP_4_Y', - 'mmPA_CL_UCP_4_Y_BASE_IDX', 'mmPA_CL_UCP_4_Z', - 'mmPA_CL_UCP_4_Z_BASE_IDX', 'mmPA_CL_UCP_5_W', - 'mmPA_CL_UCP_5_W_BASE_IDX', 'mmPA_CL_UCP_5_X', - 'mmPA_CL_UCP_5_X_BASE_IDX', 'mmPA_CL_UCP_5_Y', - 'mmPA_CL_UCP_5_Y_BASE_IDX', 'mmPA_CL_UCP_5_Z', - 'mmPA_CL_UCP_5_Z_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET', - 'mmPA_CL_VPORT_XOFFSET_1', 'mmPA_CL_VPORT_XOFFSET_10', - 'mmPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_11', - 'mmPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_12', - 'mmPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_13', - 'mmPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_14', - 'mmPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_15', - 'mmPA_CL_VPORT_XOFFSET_15_BASE_IDX', - 'mmPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_2', - 'mmPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_3', - 'mmPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_4', - 'mmPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_5', - 'mmPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_6', - 'mmPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_7', - 'mmPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_8', - 'mmPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_9', - 'mmPA_CL_VPORT_XOFFSET_9_BASE_IDX', - 'mmPA_CL_VPORT_XOFFSET_BASE_IDX', 'mmPA_CL_VPORT_XSCALE', - 'mmPA_CL_VPORT_XSCALE_1', 'mmPA_CL_VPORT_XSCALE_10', - 'mmPA_CL_VPORT_XSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_11', - 'mmPA_CL_VPORT_XSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_12', - 'mmPA_CL_VPORT_XSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_13', - 'mmPA_CL_VPORT_XSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_14', - 'mmPA_CL_VPORT_XSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_15', - 'mmPA_CL_VPORT_XSCALE_15_BASE_IDX', - 'mmPA_CL_VPORT_XSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_2', - 'mmPA_CL_VPORT_XSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_3', - 'mmPA_CL_VPORT_XSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_4', - 'mmPA_CL_VPORT_XSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_5', - 'mmPA_CL_VPORT_XSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_6', - 'mmPA_CL_VPORT_XSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_7', - 'mmPA_CL_VPORT_XSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_8', - 'mmPA_CL_VPORT_XSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_9', - 'mmPA_CL_VPORT_XSCALE_9_BASE_IDX', - 'mmPA_CL_VPORT_XSCALE_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET', - 'mmPA_CL_VPORT_YOFFSET_1', 'mmPA_CL_VPORT_YOFFSET_10', - 'mmPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_11', - 'mmPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_12', - 'mmPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_13', - 'mmPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_14', - 'mmPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_15', - 'mmPA_CL_VPORT_YOFFSET_15_BASE_IDX', - 'mmPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_2', - 'mmPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_3', - 'mmPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_4', - 'mmPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_5', - 'mmPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_6', - 'mmPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_7', - 'mmPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_8', - 'mmPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_9', - 'mmPA_CL_VPORT_YOFFSET_9_BASE_IDX', - 'mmPA_CL_VPORT_YOFFSET_BASE_IDX', 'mmPA_CL_VPORT_YSCALE', - 'mmPA_CL_VPORT_YSCALE_1', 'mmPA_CL_VPORT_YSCALE_10', - 'mmPA_CL_VPORT_YSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_11', - 'mmPA_CL_VPORT_YSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_12', - 'mmPA_CL_VPORT_YSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_13', - 'mmPA_CL_VPORT_YSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_14', - 'mmPA_CL_VPORT_YSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_15', - 'mmPA_CL_VPORT_YSCALE_15_BASE_IDX', - 'mmPA_CL_VPORT_YSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_2', - 'mmPA_CL_VPORT_YSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_3', - 'mmPA_CL_VPORT_YSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_4', - 'mmPA_CL_VPORT_YSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_5', - 'mmPA_CL_VPORT_YSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_6', - 'mmPA_CL_VPORT_YSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_7', - 'mmPA_CL_VPORT_YSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_8', - 'mmPA_CL_VPORT_YSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_9', - 'mmPA_CL_VPORT_YSCALE_9_BASE_IDX', - 'mmPA_CL_VPORT_YSCALE_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET', - 'mmPA_CL_VPORT_ZOFFSET_1', 'mmPA_CL_VPORT_ZOFFSET_10', - 'mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_11', - 'mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_12', - 'mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_13', - 'mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_14', - 'mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_15', - 'mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX', - 'mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_2', - 'mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_3', - 'mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_4', - 'mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_5', - 'mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_6', - 'mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_7', - 'mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_8', - 'mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_9', - 'mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX', - 'mmPA_CL_VPORT_ZOFFSET_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE', - 'mmPA_CL_VPORT_ZSCALE_1', 'mmPA_CL_VPORT_ZSCALE_10', - 'mmPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_11', - 'mmPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_12', - 'mmPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_13', - 'mmPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_14', - 'mmPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_15', - 'mmPA_CL_VPORT_ZSCALE_15_BASE_IDX', - 'mmPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_2', - 'mmPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_3', - 'mmPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_4', - 'mmPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_5', - 'mmPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_6', - 'mmPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_7', - 'mmPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_8', - 'mmPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_9', - 'mmPA_CL_VPORT_ZSCALE_9_BASE_IDX', - 'mmPA_CL_VPORT_ZSCALE_BASE_IDX', 'mmPA_CL_VRS_CNTL', - 'mmPA_CL_VRS_CNTL_BASE_IDX', 'mmPA_CL_VS_OUT_CNTL', - 'mmPA_CL_VS_OUT_CNTL_BASE_IDX', 'mmPA_CL_VTE_CNTL', - 'mmPA_CL_VTE_CNTL_BASE_IDX', 'mmPA_PH_ENHANCE', - 'mmPA_PH_ENHANCE_BASE_IDX', 'mmPA_PH_INTERFACE_FIFO_SIZE', - 'mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_HI', - 'mmPA_PH_PERFCOUNTER0_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_LO', - 'mmPA_PH_PERFCOUNTER0_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_SELECT', - 'mmPA_PH_PERFCOUNTER0_SELECT1', - 'mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_HI', - 'mmPA_PH_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_LO', - 'mmPA_PH_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_SELECT', - 'mmPA_PH_PERFCOUNTER1_SELECT1', - 'mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_HI', - 'mmPA_PH_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_LO', - 'mmPA_PH_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_SELECT', - 'mmPA_PH_PERFCOUNTER2_SELECT1', - 'mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_HI', - 'mmPA_PH_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_LO', - 'mmPA_PH_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_SELECT', - 'mmPA_PH_PERFCOUNTER3_SELECT1', - 'mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_HI', - 'mmPA_PH_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_LO', - 'mmPA_PH_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_SELECT', - 'mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_HI', - 'mmPA_PH_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_LO', - 'mmPA_PH_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_SELECT', - 'mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_HI', - 'mmPA_PH_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_LO', - 'mmPA_PH_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_SELECT', - 'mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_HI', - 'mmPA_PH_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_LO', - 'mmPA_PH_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_SELECT', - 'mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'mmPA_SC_AA_CONFIG', - 'mmPA_SC_AA_CONFIG_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y0_X1Y0', - 'mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y1_X1Y1', - 'mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', - 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', - 'mmPA_SC_BC_WAVE_BREAK', 'mmPA_SC_BC_WAVE_BREAK_BASE_IDX', - 'mmPA_SC_BINNER_CNTL_0', 'mmPA_SC_BINNER_CNTL_0_BASE_IDX', - 'mmPA_SC_BINNER_CNTL_1', 'mmPA_SC_BINNER_CNTL_1_BASE_IDX', - 'mmPA_SC_BINNER_CNTL_OVERRIDE', - 'mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX', - 'mmPA_SC_BINNER_EVENT_CNTL_0', - 'mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', - 'mmPA_SC_BINNER_EVENT_CNTL_1', - 'mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', - 'mmPA_SC_BINNER_EVENT_CNTL_2', - 'mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', - 'mmPA_SC_BINNER_EVENT_CNTL_3', - 'mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', - 'mmPA_SC_BINNER_PERF_CNTL_0', - 'mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', - 'mmPA_SC_BINNER_PERF_CNTL_1', - 'mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', - 'mmPA_SC_BINNER_PERF_CNTL_2', - 'mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', - 'mmPA_SC_BINNER_PERF_CNTL_3', - 'mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', - 'mmPA_SC_BINNER_TIMEOUT_COUNTER', - 'mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', - 'mmPA_SC_CENTROID_PRIORITY_0', - 'mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX', - 'mmPA_SC_CENTROID_PRIORITY_1', - 'mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'mmPA_SC_CLIPRECT_0_BR', - 'mmPA_SC_CLIPRECT_0_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_0_TL', - 'mmPA_SC_CLIPRECT_0_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_1_BR', - 'mmPA_SC_CLIPRECT_1_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_1_TL', - 'mmPA_SC_CLIPRECT_1_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_2_BR', - 'mmPA_SC_CLIPRECT_2_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_2_TL', - 'mmPA_SC_CLIPRECT_2_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_3_BR', - 'mmPA_SC_CLIPRECT_3_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_3_TL', - 'mmPA_SC_CLIPRECT_3_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_RULE', - 'mmPA_SC_CLIPRECT_RULE_BASE_IDX', - 'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', - 'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', - 'mmPA_SC_DSM_CNTL', 'mmPA_SC_DSM_CNTL_BASE_IDX', - 'mmPA_SC_EDGERULE', 'mmPA_SC_EDGERULE_BASE_IDX', - 'mmPA_SC_ENHANCE', 'mmPA_SC_ENHANCE_1', - 'mmPA_SC_ENHANCE_1_BASE_IDX', 'mmPA_SC_ENHANCE_2', - 'mmPA_SC_ENHANCE_2_BASE_IDX', 'mmPA_SC_ENHANCE_3', - 'mmPA_SC_ENHANCE_3_BASE_IDX', 'mmPA_SC_ENHANCE_BASE_IDX', - 'mmPA_SC_ENHANCE_INTERNAL', 'mmPA_SC_ENHANCE_INTERNAL_BASE_IDX', - 'mmPA_SC_FIFO_DEPTH_CNTL', 'mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', - 'mmPA_SC_FIFO_SIZE', 'mmPA_SC_FIFO_SIZE_BASE_IDX', - 'mmPA_SC_FORCE_EOV_MAX_CNTS', - 'mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', - 'mmPA_SC_GENERIC_SCISSOR_BR', - 'mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', - 'mmPA_SC_GENERIC_SCISSOR_TL', - 'mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_COUNT', - 'mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_H', 'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN', - 'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', - 'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', - 'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'mmPA_SC_HP3D_TRAP_SCREEN_V', - 'mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'mmPA_SC_IF_FIFO_SIZE', - 'mmPA_SC_IF_FIFO_SIZE_BASE_IDX', 'mmPA_SC_LINE_CNTL', - 'mmPA_SC_LINE_CNTL_BASE_IDX', 'mmPA_SC_LINE_STIPPLE', - 'mmPA_SC_LINE_STIPPLE_BASE_IDX', 'mmPA_SC_LINE_STIPPLE_STATE', - 'mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'mmPA_SC_MODE_CNTL_0', - 'mmPA_SC_MODE_CNTL_0_BASE_IDX', 'mmPA_SC_MODE_CNTL_1', - 'mmPA_SC_MODE_CNTL_1_BASE_IDX', 'mmPA_SC_NGG_MODE_CNTL', - 'mmPA_SC_NGG_MODE_CNTL_BASE_IDX', 'mmPA_SC_P3D_TRAP_SCREEN_COUNT', - 'mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'mmPA_SC_P3D_TRAP_SCREEN_H', 'mmPA_SC_P3D_TRAP_SCREEN_HV_EN', - 'mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK', - 'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', - 'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', - 'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'mmPA_SC_P3D_TRAP_SCREEN_V', 'mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', - 'mmPA_SC_PBB_OVERRIDE_FLAG', 'mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', - 'mmPA_SC_PERFCOUNTER0_HI', 'mmPA_SC_PERFCOUNTER0_HI_BASE_IDX', - 'mmPA_SC_PERFCOUNTER0_LO', 'mmPA_SC_PERFCOUNTER0_LO_BASE_IDX', - 'mmPA_SC_PERFCOUNTER0_SELECT', 'mmPA_SC_PERFCOUNTER0_SELECT1', - 'mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_HI', - 'mmPA_SC_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_LO', - 'mmPA_SC_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_SELECT', - 'mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_HI', - 'mmPA_SC_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_LO', - 'mmPA_SC_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_SELECT', - 'mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_HI', - 'mmPA_SC_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_LO', - 'mmPA_SC_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_SELECT', - 'mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_HI', - 'mmPA_SC_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_LO', - 'mmPA_SC_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_SELECT', - 'mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_HI', - 'mmPA_SC_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_LO', - 'mmPA_SC_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_SELECT', - 'mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_HI', - 'mmPA_SC_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_LO', - 'mmPA_SC_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_SELECT', - 'mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_HI', - 'mmPA_SC_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_LO', - 'mmPA_SC_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_SELECT', - 'mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', - 'mmPA_SC_PKR_WAVE_TABLE_CNTL', - 'mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'mmPA_SC_RASTER_CONFIG', - 'mmPA_SC_RASTER_CONFIG_1', 'mmPA_SC_RASTER_CONFIG_1_BASE_IDX', - 'mmPA_SC_RASTER_CONFIG_BASE_IDX', 'mmPA_SC_SCREEN_EXTENT_CONTROL', - 'mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', - 'mmPA_SC_SCREEN_EXTENT_MAX_0', - 'mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', - 'mmPA_SC_SCREEN_EXTENT_MAX_1', - 'mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', - 'mmPA_SC_SCREEN_EXTENT_MIN_0', - 'mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', - 'mmPA_SC_SCREEN_EXTENT_MIN_1', - 'mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', - 'mmPA_SC_SCREEN_SCISSOR_BR', 'mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', - 'mmPA_SC_SCREEN_SCISSOR_TL', 'mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', - 'mmPA_SC_SHADER_CONTROL', 'mmPA_SC_SHADER_CONTROL_BASE_IDX', - 'mmPA_SC_TILE_STEERING_CREST_OVERRIDE', - 'mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', - 'mmPA_SC_TILE_STEERING_OVERRIDE', - 'mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_COUNT', 'mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_H', 'mmPA_SC_TRAP_SCREEN_HV_EN', - 'mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_HV_LOCK', - 'mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_H_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_OCCURRENCE', - 'mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'mmPA_SC_TRAP_SCREEN_V', 'mmPA_SC_TRAP_SCREEN_V_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_0_BR', - 'mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_0_TL', - 'mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_10_BR', - 'mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_10_TL', - 'mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_11_BR', - 'mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_11_TL', - 'mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_12_BR', - 'mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_12_TL', - 'mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_13_BR', - 'mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_13_TL', - 'mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_14_BR', - 'mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_14_TL', - 'mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_15_BR', - 'mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_15_TL', - 'mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_1_BR', - 'mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_1_TL', - 'mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_2_BR', - 'mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_2_TL', - 'mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_3_BR', - 'mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_3_TL', - 'mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_4_BR', - 'mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_4_TL', - 'mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_5_BR', - 'mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_5_TL', - 'mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_6_BR', - 'mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_6_TL', - 'mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_7_BR', - 'mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_7_TL', - 'mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_8_BR', - 'mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_8_TL', - 'mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_9_BR', - 'mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', - 'mmPA_SC_VPORT_SCISSOR_9_TL', - 'mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_0', - 'mmPA_SC_VPORT_ZMAX_0_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_1', - 'mmPA_SC_VPORT_ZMAX_10', 'mmPA_SC_VPORT_ZMAX_10_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_11', 'mmPA_SC_VPORT_ZMAX_11_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_12', 'mmPA_SC_VPORT_ZMAX_12_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_13', 'mmPA_SC_VPORT_ZMAX_13_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_14', 'mmPA_SC_VPORT_ZMAX_14_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_15', 'mmPA_SC_VPORT_ZMAX_15_BASE_IDX', - 'mmPA_SC_VPORT_ZMAX_1_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_2', - 'mmPA_SC_VPORT_ZMAX_2_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_3', - 'mmPA_SC_VPORT_ZMAX_3_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_4', - 'mmPA_SC_VPORT_ZMAX_4_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_5', - 'mmPA_SC_VPORT_ZMAX_5_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_6', - 'mmPA_SC_VPORT_ZMAX_6_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_7', - 'mmPA_SC_VPORT_ZMAX_7_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_8', - 'mmPA_SC_VPORT_ZMAX_8_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_9', - 'mmPA_SC_VPORT_ZMAX_9_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_0', - 'mmPA_SC_VPORT_ZMIN_0_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_1', - 'mmPA_SC_VPORT_ZMIN_10', 'mmPA_SC_VPORT_ZMIN_10_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_11', 'mmPA_SC_VPORT_ZMIN_11_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_12', 'mmPA_SC_VPORT_ZMIN_12_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_13', 'mmPA_SC_VPORT_ZMIN_13_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_14', 'mmPA_SC_VPORT_ZMIN_14_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_15', 'mmPA_SC_VPORT_ZMIN_15_BASE_IDX', - 'mmPA_SC_VPORT_ZMIN_1_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_2', - 'mmPA_SC_VPORT_ZMIN_2_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_3', - 'mmPA_SC_VPORT_ZMIN_3_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_4', - 'mmPA_SC_VPORT_ZMIN_4_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_5', - 'mmPA_SC_VPORT_ZMIN_5_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_6', - 'mmPA_SC_VPORT_ZMIN_6_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_7', - 'mmPA_SC_VPORT_ZMIN_7_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_8', - 'mmPA_SC_VPORT_ZMIN_8_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_9', - 'mmPA_SC_VPORT_ZMIN_9_BASE_IDX', 'mmPA_SC_WINDOW_OFFSET', - 'mmPA_SC_WINDOW_OFFSET_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_BR', - 'mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_TL', - 'mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', - 'mmPA_SIDEBAND_REQUEST_DELAYS', - 'mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX', 'mmPA_STATE_STEREO_X', - 'mmPA_STATE_STEREO_X_BASE_IDX', 'mmPA_STEREO_CNTL', - 'mmPA_STEREO_CNTL_BASE_IDX', 'mmPA_SU_CNTL_STATUS', - 'mmPA_SU_CNTL_STATUS_BASE_IDX', 'mmPA_SU_HARDWARE_SCREEN_OFFSET', - 'mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'mmPA_SU_LINE_CNTL', - 'mmPA_SU_LINE_CNTL_BASE_IDX', 'mmPA_SU_LINE_STIPPLE_CNTL', - 'mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', - 'mmPA_SU_LINE_STIPPLE_SCALE', - 'mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', - 'mmPA_SU_LINE_STIPPLE_VALUE', - 'mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', - 'mmPA_SU_OVER_RASTERIZATION_CNTL', - 'mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', - 'mmPA_SU_PERFCOUNTER0_HI', 'mmPA_SU_PERFCOUNTER0_HI_BASE_IDX', - 'mmPA_SU_PERFCOUNTER0_LO', 'mmPA_SU_PERFCOUNTER0_LO_BASE_IDX', - 'mmPA_SU_PERFCOUNTER0_SELECT', 'mmPA_SU_PERFCOUNTER0_SELECT1', - 'mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_HI', - 'mmPA_SU_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_LO', - 'mmPA_SU_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_SELECT', - 'mmPA_SU_PERFCOUNTER1_SELECT1', - 'mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_HI', - 'mmPA_SU_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_LO', - 'mmPA_SU_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_SELECT', - 'mmPA_SU_PERFCOUNTER2_SELECT1', - 'mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_HI', - 'mmPA_SU_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_LO', - 'mmPA_SU_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_SELECT', - 'mmPA_SU_PERFCOUNTER3_SELECT1', - 'mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SU_POINT_MINMAX', - 'mmPA_SU_POINT_MINMAX_BASE_IDX', 'mmPA_SU_POINT_SIZE', - 'mmPA_SU_POINT_SIZE_BASE_IDX', 'mmPA_SU_POLY_OFFSET_BACK_OFFSET', - 'mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', - 'mmPA_SU_POLY_OFFSET_BACK_SCALE', - 'mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', - 'mmPA_SU_POLY_OFFSET_CLAMP', 'mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', - 'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL', - 'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', - 'mmPA_SU_POLY_OFFSET_FRONT_OFFSET', - 'mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', - 'mmPA_SU_POLY_OFFSET_FRONT_SCALE', - 'mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', - 'mmPA_SU_PRIM_FILTER_CNTL', 'mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX', - 'mmPA_SU_SC_MODE_CNTL', 'mmPA_SU_SC_MODE_CNTL_BASE_IDX', - 'mmPA_SU_SMALL_PRIM_FILTER_CNTL', - 'mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'mmPA_SU_VTX_CNTL', - 'mmPA_SU_VTX_CNTL_BASE_IDX', 'mmPCC_PERF_COUNTER', - 'mmPCC_PERF_COUNTER_BASE_IDX', 'mmPMM_GENERAL_CNTL', - 'mmPMM_GENERAL_CNTL_BASE_IDX', 'mmPWRBRK_PERF_COUNTER', - 'mmPWRBRK_PERF_COUNTER_BASE_IDX', 'mmRLC_AUTO_PG_CTRL', - 'mmRLC_AUTO_PG_CTRL_BASE_IDX', 'mmRLC_BUSY_CLK_CNTL', - 'mmRLC_BUSY_CLK_CNTL_BASE_IDX', 'mmRLC_CAC_MASK_CNTL', - 'mmRLC_CAC_MASK_CNTL_BASE_IDX', 'mmRLC_CAPTURE_GPU_CLOCK_COUNT', - 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1', - 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', - 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2', - 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', - 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', 'mmRLC_CGCG_CGLS_CTRL', - 'mmRLC_CGCG_CGLS_CTRL_3D', 'mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX', - 'mmRLC_CGCG_CGLS_CTRL_BASE_IDX', 'mmRLC_CGCG_RAMP_CTRL', - 'mmRLC_CGCG_RAMP_CTRL_3D', 'mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX', - 'mmRLC_CGCG_RAMP_CTRL_BASE_IDX', 'mmRLC_CGTT_MGCG_OVERRIDE', - 'mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'mmRLC_CLK_CNTL', - 'mmRLC_CLK_CNTL_BASE_IDX', 'mmRLC_CLK_COUNT_CTRL', - 'mmRLC_CLK_COUNT_CTRL_BASE_IDX', 'mmRLC_CLK_COUNT_GFXCLK_LSB', - 'mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', - 'mmRLC_CLK_COUNT_GFXCLK_MSB', - 'mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', - 'mmRLC_CLK_COUNT_REFCLK_LSB', - 'mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', - 'mmRLC_CLK_COUNT_REFCLK_MSB', - 'mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'mmRLC_CLK_COUNT_STAT', - 'mmRLC_CLK_COUNT_STAT_BASE_IDX', 'mmRLC_CLK_STATUS', - 'mmRLC_CLK_STATUS_BASE_IDX', 'mmRLC_CNTL', 'mmRLC_CNTL_BASE_IDX', - 'mmRLC_CPAXI_DOORBELL_MON_CTRL', - 'mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX', - 'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB', - 'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX', - 'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB', - 'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX', - 'mmRLC_CPAXI_DOORBELL_MON_STAT', - 'mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX', 'mmRLC_CP_EOF_INT', - 'mmRLC_CP_EOF_INT_BASE_IDX', 'mmRLC_CP_EOF_INT_CNT', - 'mmRLC_CP_EOF_INT_CNT_BASE_IDX', 'mmRLC_CP_SCHEDULERS', - 'mmRLC_CP_SCHEDULERS_BASE_IDX', 'mmRLC_CP_STAT_INVAL_CTRL', - 'mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'mmRLC_CP_STAT_INVAL_STAT', - 'mmRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'mmRLC_CSIB_ADDR_HI', - 'mmRLC_CSIB_ADDR_HI_BASE_IDX', 'mmRLC_CSIB_ADDR_LO', - 'mmRLC_CSIB_ADDR_LO_BASE_IDX', 'mmRLC_CSIB_LENGTH', - 'mmRLC_CSIB_LENGTH_BASE_IDX', 'mmRLC_DYN_PG_REQUEST', - 'mmRLC_DYN_PG_REQUEST_BASE_IDX', 'mmRLC_DYN_PG_STATUS', - 'mmRLC_DYN_PG_STATUS_BASE_IDX', 'mmRLC_F32_UCODE_VERSION', - 'mmRLC_F32_UCODE_VERSION_BASE_IDX', 'mmRLC_FWL_FIRST_VIOL_ADDR', - 'mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_GFX_RM_CNTL', - 'mmRLC_GFX_RM_CNTL_BASE_IDX', 'mmRLC_GPM_CP_DMA_COMPLETE_T0', - 'mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', - 'mmRLC_GPM_CP_DMA_COMPLETE_T1', - 'mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'mmRLC_GPM_GENERAL_0', - 'mmRLC_GPM_GENERAL_0_BASE_IDX', 'mmRLC_GPM_GENERAL_1', - 'mmRLC_GPM_GENERAL_10', 'mmRLC_GPM_GENERAL_10_BASE_IDX', - 'mmRLC_GPM_GENERAL_11', 'mmRLC_GPM_GENERAL_11_BASE_IDX', - 'mmRLC_GPM_GENERAL_12', 'mmRLC_GPM_GENERAL_12_BASE_IDX', - 'mmRLC_GPM_GENERAL_13', 'mmRLC_GPM_GENERAL_13_BASE_IDX', - 'mmRLC_GPM_GENERAL_14', 'mmRLC_GPM_GENERAL_14_BASE_IDX', - 'mmRLC_GPM_GENERAL_15', 'mmRLC_GPM_GENERAL_15_BASE_IDX', - 'mmRLC_GPM_GENERAL_16', 'mmRLC_GPM_GENERAL_16_BASE_IDX', - 'mmRLC_GPM_GENERAL_1_BASE_IDX', 'mmRLC_GPM_GENERAL_2', - 'mmRLC_GPM_GENERAL_2_BASE_IDX', 'mmRLC_GPM_GENERAL_3', - 'mmRLC_GPM_GENERAL_3_BASE_IDX', 'mmRLC_GPM_GENERAL_4', - 'mmRLC_GPM_GENERAL_4_BASE_IDX', 'mmRLC_GPM_GENERAL_5', - 'mmRLC_GPM_GENERAL_5_BASE_IDX', 'mmRLC_GPM_GENERAL_6', - 'mmRLC_GPM_GENERAL_6_BASE_IDX', 'mmRLC_GPM_GENERAL_7', - 'mmRLC_GPM_GENERAL_7_BASE_IDX', 'mmRLC_GPM_GENERAL_8', - 'mmRLC_GPM_GENERAL_8_BASE_IDX', 'mmRLC_GPM_GENERAL_9', - 'mmRLC_GPM_GENERAL_9_BASE_IDX', 'mmRLC_GPM_INT_DISABLE_TH0', - 'mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'mmRLC_GPM_INT_FORCE_TH0', - 'mmRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'mmRLC_GPM_INT_STAT_TH0', - 'mmRLC_GPM_INT_STAT_TH0_BASE_IDX', 'mmRLC_GPM_IRAM_ADDR', - 'mmRLC_GPM_IRAM_ADDR_BASE_IDX', 'mmRLC_GPM_IRAM_DATA', - 'mmRLC_GPM_IRAM_DATA_BASE_IDX', 'mmRLC_GPM_LEGACY_INT_CLEAR', - 'mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX', - 'mmRLC_GPM_LEGACY_INT_DISABLE', - 'mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'mmRLC_GPM_LEGACY_INT_STAT', 'mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX', - 'mmRLC_GPM_LOG_CONT', 'mmRLC_GPM_LOG_CONT_BASE_IDX', - 'mmRLC_GPM_LOG_SIZE', 'mmRLC_GPM_LOG_SIZE_BASE_IDX', - 'mmRLC_GPM_PERF_COUNT_0', 'mmRLC_GPM_PERF_COUNT_0_BASE_IDX', - 'mmRLC_GPM_PERF_COUNT_1', 'mmRLC_GPM_PERF_COUNT_1_BASE_IDX', - 'mmRLC_GPM_SCRATCH_ADDR', 'mmRLC_GPM_SCRATCH_ADDR_BASE_IDX', - 'mmRLC_GPM_SCRATCH_DATA', 'mmRLC_GPM_SCRATCH_DATA_BASE_IDX', - 'mmRLC_GPM_STAT', 'mmRLC_GPM_STAT_BASE_IDX', - 'mmRLC_GPM_THREAD_ENABLE', 'mmRLC_GPM_THREAD_ENABLE_BASE_IDX', - 'mmRLC_GPM_THREAD_PRIORITY', 'mmRLC_GPM_THREAD_PRIORITY_BASE_IDX', - 'mmRLC_GPM_THREAD_RESET', 'mmRLC_GPM_THREAD_RESET_BASE_IDX', - 'mmRLC_GPM_TIMER_CTRL', 'mmRLC_GPM_TIMER_CTRL_BASE_IDX', - 'mmRLC_GPM_TIMER_INT_0', 'mmRLC_GPM_TIMER_INT_0_BASE_IDX', - 'mmRLC_GPM_TIMER_INT_1', 'mmRLC_GPM_TIMER_INT_1_BASE_IDX', - 'mmRLC_GPM_TIMER_INT_2', 'mmRLC_GPM_TIMER_INT_2_BASE_IDX', - 'mmRLC_GPM_TIMER_INT_3', 'mmRLC_GPM_TIMER_INT_3_BASE_IDX', - 'mmRLC_GPM_TIMER_INT_4', 'mmRLC_GPM_TIMER_INT_4_BASE_IDX', - 'mmRLC_GPM_TIMER_STAT', 'mmRLC_GPM_TIMER_STAT_BASE_IDX', - 'mmRLC_GPM_UCODE_ADDR', 'mmRLC_GPM_UCODE_ADDR_BASE_IDX', - 'mmRLC_GPM_UCODE_DATA', 'mmRLC_GPM_UCODE_DATA_BASE_IDX', - 'mmRLC_GPM_UTCL1_CNTL_0', 'mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX', - 'mmRLC_GPM_UTCL1_CNTL_1', 'mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX', - 'mmRLC_GPM_UTCL1_CNTL_2', 'mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH0_ERROR_1', - 'mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH0_ERROR_2', - 'mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH1_ERROR_1', - 'mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH1_ERROR_2', - 'mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH2_ERROR_1', - 'mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', - 'mmRLC_GPM_UTCL1_TH2_ERROR_2', - 'mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'mmRLC_GPR_REG1', - 'mmRLC_GPR_REG1_BASE_IDX', 'mmRLC_GPR_REG2', - 'mmRLC_GPR_REG2_BASE_IDX', 'mmRLC_GPU_CLOCK_32', - 'mmRLC_GPU_CLOCK_32_BASE_IDX', 'mmRLC_GPU_CLOCK_32_RES_SEL', - 'mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_LSB', 'mmRLC_GPU_CLOCK_COUNT_LSB_1', - 'mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_LSB_2', - 'mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', 'mmRLC_GPU_CLOCK_COUNT_MSB', - 'mmRLC_GPU_CLOCK_COUNT_MSB_1', - 'mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_MSB_2', - 'mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_SPM_LSB', - 'mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX', - 'mmRLC_GPU_CLOCK_COUNT_SPM_MSB', - 'mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX', - 'mmRLC_GPU_IOV_ACTIVE_FCN_ID', - 'mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG1', - 'mmRLC_GPU_IOV_CFG_REG1_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG2', - 'mmRLC_GPU_IOV_CFG_REG2_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG6', - 'mmRLC_GPU_IOV_CFG_REG6_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG8', - 'mmRLC_GPU_IOV_CFG_REG8_BASE_IDX', 'mmRLC_GPU_IOV_F32_CNTL', - 'mmRLC_GPU_IOV_F32_CNTL_BASE_IDX', 'mmRLC_GPU_IOV_F32_RESET', - 'mmRLC_GPU_IOV_F32_RESET_BASE_IDX', 'mmRLC_GPU_IOV_INT_DISABLE', - 'mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'mmRLC_GPU_IOV_INT_FORCE', - 'mmRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'mmRLC_GPU_IOV_INT_STAT', - 'mmRLC_GPU_IOV_INT_STAT_BASE_IDX', 'mmRLC_GPU_IOV_PERF_CNT_CNTL', - 'mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', - 'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR', - 'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', - 'mmRLC_GPU_IOV_PERF_CNT_RD_DATA', - 'mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', - 'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR', - 'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', - 'mmRLC_GPU_IOV_PERF_CNT_WR_DATA', - 'mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', - 'mmRLC_GPU_IOV_RLC_RESPONSE', - 'mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_SCH_0', - 'mmRLC_GPU_IOV_SCH_0_BASE_IDX', 'mmRLC_GPU_IOV_SCH_1', - 'mmRLC_GPU_IOV_SCH_1_BASE_IDX', 'mmRLC_GPU_IOV_SCH_2', - 'mmRLC_GPU_IOV_SCH_2_BASE_IDX', 'mmRLC_GPU_IOV_SCH_3', - 'mmRLC_GPU_IOV_SCH_3_BASE_IDX', 'mmRLC_GPU_IOV_SCH_BLOCK', - 'mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', 'mmRLC_GPU_IOV_SCRATCH_ADDR', - 'mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', - 'mmRLC_GPU_IOV_SCRATCH_DATA', - 'mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA0_STATUS', - 'mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA1_STATUS', - 'mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA2_STATUS', - 'mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA3_STATUS', - 'mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA4_STATUS', - 'mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA5_STATUS', - 'mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA6_STATUS', - 'mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS', - 'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SDMA7_STATUS', - 'mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_SMU_RESPONSE', - 'mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_ADDR', - 'mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_DATA', - 'mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', - 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', - 'mmRLC_GPU_IOV_VF_ENABLE', 'mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX', - 'mmRLC_GPU_IOV_VF_MASK', 'mmRLC_GPU_IOV_VF_MASK_BASE_IDX', - 'mmRLC_GPU_IOV_VIRT_RESET_REQ', - 'mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX', - 'mmRLC_GPU_IOV_VM_BUSY_STATUS', - 'mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'mmRLC_GTS_OFFSET_LSB', - 'mmRLC_GTS_OFFSET_LSB_BASE_IDX', 'mmRLC_GTS_OFFSET_MSB', - 'mmRLC_GTS_OFFSET_MSB_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_ADDR_HI', - 'mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX', - 'mmRLC_HYP_BOOTLOAD_ADDR_LO', - 'mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_SIZE', - 'mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX', 'mmRLC_HYP_RESET_VECTOR', - 'mmRLC_HYP_RESET_VECTOR_BASE_IDX', 'mmRLC_HYP_RLCG_UCODE_CHKSUM', - 'mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX', - 'mmRLC_HYP_RLCP_UCODE_CHKSUM', - 'mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX', - 'mmRLC_HYP_RLCV_UCODE_CHKSUM', - 'mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_0', - 'mmRLC_HYP_SEMAPHORE_0_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_1', - 'mmRLC_HYP_SEMAPHORE_1_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_2', - 'mmRLC_HYP_SEMAPHORE_2_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_3', - 'mmRLC_HYP_SEMAPHORE_3_BASE_IDX', 'mmRLC_IH_COOKIE', - 'mmRLC_IH_COOKIE_BASE_IDX', 'mmRLC_IH_COOKIE_CNTL', - 'mmRLC_IH_COOKIE_CNTL_BASE_IDX', 'mmRLC_INT_STAT', - 'mmRLC_INT_STAT_BASE_IDX', 'mmRLC_JUMP_TABLE_RESTORE', - 'mmRLC_JUMP_TABLE_RESTORE_BASE_IDX', - 'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK', - 'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX', 'mmRLC_LB_CNTL', - 'mmRLC_LB_CNTL_BASE_IDX', 'mmRLC_LB_CNTR_1', - 'mmRLC_LB_CNTR_1_BASE_IDX', 'mmRLC_LB_CNTR_2', - 'mmRLC_LB_CNTR_2_BASE_IDX', 'mmRLC_LB_CNTR_INIT_1', - 'mmRLC_LB_CNTR_INIT_1_BASE_IDX', 'mmRLC_LB_CNTR_INIT_2', - 'mmRLC_LB_CNTR_INIT_2_BASE_IDX', 'mmRLC_LB_CNTR_MAX_1', - 'mmRLC_LB_CNTR_MAX_1_BASE_IDX', 'mmRLC_LB_CNTR_MAX_2', - 'mmRLC_LB_CNTR_MAX_2_BASE_IDX', 'mmRLC_LB_CONFIG_1', - 'mmRLC_LB_CONFIG_1_BASE_IDX', 'mmRLC_LB_CONFIG_2', - 'mmRLC_LB_CONFIG_2_BASE_IDX', 'mmRLC_LB_CONFIG_3', - 'mmRLC_LB_CONFIG_3_BASE_IDX', 'mmRLC_LB_CONFIG_4', - 'mmRLC_LB_CONFIG_4_BASE_IDX', 'mmRLC_LB_CONFIG_5', - 'mmRLC_LB_CONFIG_5_BASE_IDX', 'mmRLC_LB_DELAY', - 'mmRLC_LB_DELAY_BASE_IDX', 'mmRLC_LB_INIT_WGP_MASK', - 'mmRLC_LB_INIT_WGP_MASK_BASE_IDX', 'mmRLC_LB_PARAMS', - 'mmRLC_LB_PARAMS_BASE_IDX', 'mmRLC_LB_WGP_STAT', - 'mmRLC_LB_WGP_STAT_BASE_IDX', 'mmRLC_MAX_PG_WGP', - 'mmRLC_MAX_PG_WGP_BASE_IDX', 'mmRLC_MEM_SLP_CNTL', - 'mmRLC_MEM_SLP_CNTL_BASE_IDX', 'mmRLC_MGCG_CTRL', - 'mmRLC_MGCG_CTRL_BASE_IDX', 'mmRLC_PACE_INT_CLEAR', - 'mmRLC_PACE_INT_CLEAR_BASE_IDX', 'mmRLC_PACE_INT_DISABLE', - 'mmRLC_PACE_INT_DISABLE_BASE_IDX', 'mmRLC_PACE_INT_FORCE', - 'mmRLC_PACE_INT_FORCE_BASE_IDX', 'mmRLC_PACE_INT_STAT', - 'mmRLC_PACE_INT_STAT_BASE_IDX', 'mmRLC_PACE_SCRATCH_ADDR', - 'mmRLC_PACE_SCRATCH_ADDR_BASE_IDX', 'mmRLC_PACE_SCRATCH_DATA', - 'mmRLC_PACE_SCRATCH_DATA_BASE_IDX', 'mmRLC_PACE_SPARE_INT', - 'mmRLC_PACE_SPARE_INT_1', 'mmRLC_PACE_SPARE_INT_1_BASE_IDX', - 'mmRLC_PACE_SPARE_INT_BASE_IDX', 'mmRLC_PACE_TIMER_CTRL', - 'mmRLC_PACE_TIMER_CTRL_BASE_IDX', 'mmRLC_PACE_TIMER_INT_0', - 'mmRLC_PACE_TIMER_INT_0_BASE_IDX', 'mmRLC_PACE_TIMER_INT_1', - 'mmRLC_PACE_TIMER_INT_1_BASE_IDX', 'mmRLC_PACE_TIMER_STAT', - 'mmRLC_PACE_TIMER_STAT_BASE_IDX', 'mmRLC_PACE_UCODE_ADDR', - 'mmRLC_PACE_UCODE_ADDR_BASE_IDX', 'mmRLC_PACE_UCODE_DATA', - 'mmRLC_PACE_UCODE_DATA_BASE_IDX', - 'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL', - 'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX', - 'mmRLC_PERFCOUNTER0_HI', 'mmRLC_PERFCOUNTER0_HI_BASE_IDX', - 'mmRLC_PERFCOUNTER0_LO', 'mmRLC_PERFCOUNTER0_LO_BASE_IDX', - 'mmRLC_PERFCOUNTER0_SELECT', 'mmRLC_PERFCOUNTER0_SELECT_BASE_IDX', - 'mmRLC_PERFCOUNTER1_HI', 'mmRLC_PERFCOUNTER1_HI_BASE_IDX', - 'mmRLC_PERFCOUNTER1_LO', 'mmRLC_PERFCOUNTER1_LO_BASE_IDX', - 'mmRLC_PERFCOUNTER1_SELECT', 'mmRLC_PERFCOUNTER1_SELECT_BASE_IDX', - 'mmRLC_PERFMON_CLK_CNTL', 'mmRLC_PERFMON_CLK_CNTL_BASE_IDX', - 'mmRLC_PERFMON_CNTL', 'mmRLC_PERFMON_CNTL_BASE_IDX', - 'mmRLC_PG_ALWAYS_ON_WGP_MASK', - 'mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'mmRLC_PG_CNTL', - 'mmRLC_PG_CNTL_BASE_IDX', 'mmRLC_PG_DELAY', 'mmRLC_PG_DELAY_2', - 'mmRLC_PG_DELAY_2_BASE_IDX', 'mmRLC_PG_DELAY_3', - 'mmRLC_PG_DELAY_3_BASE_IDX', 'mmRLC_PG_DELAY_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_ADDR_LSB', - 'mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_ADDR_MSB', - 'mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_CNTL', - 'mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_SIZE_LSB', - 'mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_SIZE_MSB', - 'mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX', - 'mmRLC_PREWALKER_UTCL1_TRIG', - 'mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX', 'mmRLC_R2I_CNTL_0', - 'mmRLC_R2I_CNTL_0_BASE_IDX', 'mmRLC_R2I_CNTL_1', - 'mmRLC_R2I_CNTL_1_BASE_IDX', 'mmRLC_R2I_CNTL_2', - 'mmRLC_R2I_CNTL_2_BASE_IDX', 'mmRLC_R2I_CNTL_3', - 'mmRLC_R2I_CNTL_3_BASE_IDX', 'mmRLC_REFCLOCK_TIMESTAMP_LSB', - 'mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', - 'mmRLC_REFCLOCK_TIMESTAMP_MSB', - 'mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_0_DATA_HI', - 'mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_0_DATA_LO', - 'mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_1_DATA_HI', - 'mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_1_DATA_LO', - 'mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_2_DATA_HI', - 'mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_2_DATA_LO', - 'mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_3_DATA_HI', - 'mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_3_DATA_LO', - 'mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_CNTL', 'mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_RANGE', 'mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX', - 'mmRLC_RLCG_DOORBELL_STAT', 'mmRLC_RLCG_DOORBELL_STAT_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_0_DATA_HI', - 'mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_0_DATA_LO', - 'mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_1_DATA_HI', - 'mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_1_DATA_LO', - 'mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_2_DATA_HI', - 'mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_2_DATA_LO', - 'mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_3_DATA_HI', - 'mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_3_DATA_LO', - 'mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_CNTL', 'mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_RANGE', 'mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX', - 'mmRLC_RLCP_DOORBELL_STAT', 'mmRLC_RLCP_DOORBELL_STAT_BASE_IDX', - 'mmRLC_RLCP_IRAM_ADDR', 'mmRLC_RLCP_IRAM_ADDR_BASE_IDX', - 'mmRLC_RLCP_IRAM_DATA', 'mmRLC_RLCP_IRAM_DATA_BASE_IDX', - 'mmRLC_RLCS_ABORTED_PD_SEQUENCE', - 'mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX', - 'mmRLC_RLCS_AUXILIARY_REG_1', - 'mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX', - 'mmRLC_RLCS_AUXILIARY_REG_2', - 'mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX', - 'mmRLC_RLCS_AUXILIARY_REG_3', - 'mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX', - 'mmRLC_RLCS_AUXILIARY_REG_4', - 'mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX', - 'mmRLC_RLCS_BOOTLOAD_ID_STATUS1', - 'mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX', - 'mmRLC_RLCS_BOOTLOAD_ID_STATUS2', - 'mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX', - 'mmRLC_RLCS_BOOTLOAD_STATUS', - 'mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', 'mmRLC_RLCS_CGCG_REQUEST', - 'mmRLC_RLCS_CGCG_REQUEST_BASE_IDX', 'mmRLC_RLCS_CGCG_STATUS', - 'mmRLC_RLCS_CGCG_STATUS_BASE_IDX', 'mmRLC_RLCS_CMP_IDLE_CNTL', - 'mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX', - 'mmRLC_RLCS_CP_DMA_SRCID_OVER', - 'mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX', - 'mmRLC_RLCS_CP_INT_CTRL_1', 'mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX', - 'mmRLC_RLCS_CP_INT_CTRL_2', 'mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX', - 'mmRLC_RLCS_CP_INT_INFO_1', 'mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX', - 'mmRLC_RLCS_CP_INT_INFO_2', 'mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX', - 'mmRLC_RLCS_DEC_DUMP_ADDR', 'mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX', - 'mmRLC_RLCS_DEC_END', 'mmRLC_RLCS_DEC_END_BASE_IDX', - 'mmRLC_RLCS_DEC_START', 'mmRLC_RLCS_DEC_START_BASE_IDX', - 'mmRLC_RLCS_DIDT_FORCE_STALL', - 'mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'mmRLC_RLCS_DSM_TRIG', - 'mmRLC_RLCS_DSM_TRIG_BASE_IDX', 'mmRLC_RLCS_EDC_INT_CNTL', - 'mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX', 'mmRLC_RLCS_EXCEPTION_REG_1', - 'mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX', - 'mmRLC_RLCS_EXCEPTION_REG_2', - 'mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX', - 'mmRLC_RLCS_EXCEPTION_REG_3', - 'mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX', - 'mmRLC_RLCS_EXCEPTION_REG_4', - 'mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_0', - 'mmRLC_RLCS_GENERAL_0_BASE_IDX', 'mmRLC_RLCS_GENERAL_1', - 'mmRLC_RLCS_GENERAL_1_BASE_IDX', 'mmRLC_RLCS_GENERAL_2', - 'mmRLC_RLCS_GENERAL_2_BASE_IDX', 'mmRLC_RLCS_GENERAL_3', - 'mmRLC_RLCS_GENERAL_3_BASE_IDX', 'mmRLC_RLCS_GENERAL_4', - 'mmRLC_RLCS_GENERAL_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_5', - 'mmRLC_RLCS_GENERAL_5_BASE_IDX', 'mmRLC_RLCS_GENERAL_6', - 'mmRLC_RLCS_GENERAL_6_BASE_IDX', 'mmRLC_RLCS_GENERAL_7', - 'mmRLC_RLCS_GENERAL_7_BASE_IDX', 'mmRLC_RLCS_GFX_DS_CNTL', - 'mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX', - 'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE', - 'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'mmRLC_RLCS_GPM_LEGACY_INT_STAT', - 'mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', 'mmRLC_RLCS_GPM_STAT', - 'mmRLC_RLCS_GPM_STAT_2', 'mmRLC_RLCS_GPM_STAT_2_BASE_IDX', - 'mmRLC_RLCS_GPM_STAT_BASE_IDX', - 'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL', - 'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX', - 'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT', - 'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX', - 'mmRLC_RLCS_GRBM_SOFT_RESET', - 'mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX', - 'mmRLC_RLCS_IH_COOKIE_SEMAPHORE', - 'mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_1', - 'mmRLC_RLCS_IH_CTRL_1_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_2', - 'mmRLC_RLCS_IH_CTRL_2_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_3', - 'mmRLC_RLCS_IH_CTRL_3_BASE_IDX', 'mmRLC_RLCS_IH_SEMAPHORE', - 'mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_STATUS', - 'mmRLC_RLCS_IH_STATUS_BASE_IDX', 'mmRLC_RLCS_IOV_CMD_STATUS', - 'mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX', - 'mmRLC_RLCS_IOV_CNTX_LOC_SIZE', - 'mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX', - 'mmRLC_RLCS_IOV_SCH_BLOCK', 'mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX', - 'mmRLC_RLCS_IOV_VM_BUSY_STATUS', - 'mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX', - 'mmRLC_RLCS_KMD_LOG_CNTL1', 'mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX', - 'mmRLC_RLCS_KMD_LOG_CNTL2', 'mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX', - 'mmRLC_RLCS_LB_CONTROL', 'mmRLC_RLCS_LB_CONTROL_BASE_IDX', - 'mmRLC_RLCS_LB_READ', 'mmRLC_RLCS_LB_READ_BASE_IDX', - 'mmRLC_RLCS_LB_STATUS', 'mmRLC_RLCS_LB_STATUS_BASE_IDX', - 'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL', - 'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX', - 'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE', - 'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX', - 'mmRLC_RLCS_PG_CHANGE_READ', 'mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX', - 'mmRLC_RLCS_PG_CHANGE_STATUS', - 'mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX', - 'mmRLC_RLCS_POWER_BRAKE_CNTL', - 'mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX', - 'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1', - 'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX', - 'mmRLC_RLCS_SMUIO_VIDCHG_CTRL', - 'mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX', - 'mmRLC_RLCS_SMU_GFXCLK_CONTROL', - 'mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX', - 'mmRLC_RLCS_SMU_GFXCLK_STATUS', - 'mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX', 'mmRLC_RLCS_SOC_DS_CNTL', - 'mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_CTRL', - 'mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_1', - 'mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_2', - 'mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_RLCS_SPM_SQTT_MODE', - 'mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', 'mmRLC_RLCS_SRM_SRCID_CNTL', - 'mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'mmRLC_RLCS_UTCL2_CNTL', - 'mmRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'mmRLC_RLCS_WGP_READ', - 'mmRLC_RLCS_WGP_READ_BASE_IDX', 'mmRLC_RLCS_WGP_STATUS', - 'mmRLC_RLCS_WGP_STATUS_BASE_IDX', 'mmRLC_RLCV_COMMAND', - 'mmRLC_RLCV_COMMAND_BASE_IDX', 'mmRLC_RLCV_DOORBELL_0_DATA_HI', - 'mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_0_DATA_LO', - 'mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_1_DATA_HI', - 'mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_1_DATA_LO', - 'mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_2_DATA_HI', - 'mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_2_DATA_LO', - 'mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_3_DATA_HI', - 'mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_3_DATA_LO', - 'mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_CNTL', 'mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_RANGE', 'mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX', - 'mmRLC_RLCV_DOORBELL_STAT', 'mmRLC_RLCV_DOORBELL_STAT_BASE_IDX', - 'mmRLC_RLCV_IRAM_ADDR', 'mmRLC_RLCV_IRAM_ADDR_BASE_IDX', - 'mmRLC_RLCV_IRAM_DATA', 'mmRLC_RLCV_IRAM_DATA_BASE_IDX', - 'mmRLC_RLCV_SAFE_MODE', 'mmRLC_RLCV_SAFE_MODE_BASE_IDX', - 'mmRLC_RLCV_SPARE_INT', 'mmRLC_RLCV_SPARE_INT_1', - 'mmRLC_RLCV_SPARE_INT_1_BASE_IDX', - 'mmRLC_RLCV_SPARE_INT_BASE_IDX', 'mmRLC_RLCV_TIMER_CTRL', - 'mmRLC_RLCV_TIMER_CTRL_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_0', - 'mmRLC_RLCV_TIMER_INT_0_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_1', - 'mmRLC_RLCV_TIMER_INT_1_BASE_IDX', 'mmRLC_RLCV_TIMER_STAT', - 'mmRLC_RLCV_TIMER_STAT_BASE_IDX', 'mmRLC_SAFE_MODE', - 'mmRLC_SAFE_MODE_BASE_IDX', 'mmRLC_SDMA0_BUSY_STATUS', - 'mmRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA0_STATUS', - 'mmRLC_SDMA0_STATUS_BASE_IDX', 'mmRLC_SDMA1_BUSY_STATUS', - 'mmRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA1_STATUS', - 'mmRLC_SDMA1_STATUS_BASE_IDX', 'mmRLC_SDMA2_BUSY_STATUS', - 'mmRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA2_STATUS', - 'mmRLC_SDMA2_STATUS_BASE_IDX', 'mmRLC_SDMA3_BUSY_STATUS', - 'mmRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA3_STATUS', - 'mmRLC_SDMA3_STATUS_BASE_IDX', 'mmRLC_SEMAPHORE_0', - 'mmRLC_SEMAPHORE_0_BASE_IDX', 'mmRLC_SEMAPHORE_1', - 'mmRLC_SEMAPHORE_1_BASE_IDX', 'mmRLC_SEMAPHORE_2', - 'mmRLC_SEMAPHORE_2_BASE_IDX', 'mmRLC_SEMAPHORE_3', - 'mmRLC_SEMAPHORE_3_BASE_IDX', 'mmRLC_SERDES_BUSY', - 'mmRLC_SERDES_BUSY_BASE_IDX', 'mmRLC_SERDES_CTRL', - 'mmRLC_SERDES_CTRL_BASE_IDX', 'mmRLC_SERDES_DATA', - 'mmRLC_SERDES_DATA_BASE_IDX', 'mmRLC_SERDES_MASK', - 'mmRLC_SERDES_MASK_BASE_IDX', 'mmRLC_SERDES_RD_DATA_0', - 'mmRLC_SERDES_RD_DATA_0_BASE_IDX', 'mmRLC_SERDES_RD_DATA_1', - 'mmRLC_SERDES_RD_DATA_1_BASE_IDX', 'mmRLC_SERDES_RD_DATA_2', - 'mmRLC_SERDES_RD_DATA_2_BASE_IDX', 'mmRLC_SERDES_RD_DATA_3', - 'mmRLC_SERDES_RD_DATA_3_BASE_IDX', 'mmRLC_SERDES_RD_INDEX', - 'mmRLC_SERDES_RD_INDEX_BASE_IDX', 'mmRLC_SMU_ARGUMENT_1', - 'mmRLC_SMU_ARGUMENT_1_BASE_IDX', 'mmRLC_SMU_ARGUMENT_2', - 'mmRLC_SMU_ARGUMENT_2_BASE_IDX', 'mmRLC_SMU_ARGUMENT_3', - 'mmRLC_SMU_ARGUMENT_3_BASE_IDX', 'mmRLC_SMU_ARGUMENT_4', - 'mmRLC_SMU_ARGUMENT_4_BASE_IDX', 'mmRLC_SMU_CLK_REQ', - 'mmRLC_SMU_CLK_REQ_BASE_IDX', 'mmRLC_SMU_COMMAND', - 'mmRLC_SMU_COMMAND_BASE_IDX', 'mmRLC_SMU_GRBM_REG_SAVE_CTRL', - 'mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX', 'mmRLC_SMU_MESSAGE', - 'mmRLC_SMU_MESSAGE_BASE_IDX', 'mmRLC_SMU_SAFE_MODE', - 'mmRLC_SMU_SAFE_MODE_BASE_IDX', 'mmRLC_SPARE_INT_0', - 'mmRLC_SPARE_INT_0_BASE_IDX', 'mmRLC_SPARE_INT_1', - 'mmRLC_SPARE_INT_1_BASE_IDX', 'mmRLC_SPARE_INT_2', - 'mmRLC_SPARE_INT_2_BASE_IDX', 'mmRLC_SPM_ACCUM_CTRL', - 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR', - 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX', - 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET', - 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX', - 'mmRLC_SPM_ACCUM_CTRLRAM_DATA', - 'mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX', - 'mmRLC_SPM_ACCUM_CTRL_BASE_IDX', - 'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS', - 'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX', - 'mmRLC_SPM_ACCUM_DATARAM_ADDR', - 'mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX', - 'mmRLC_SPM_ACCUM_DATARAM_DATA', - 'mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX', - 'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT', - 'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX', - 'mmRLC_SPM_ACCUM_MODE', 'mmRLC_SPM_ACCUM_MODE_BASE_IDX', - 'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED', - 'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX', - 'mmRLC_SPM_ACCUM_STATUS', 'mmRLC_SPM_ACCUM_STATUS_BASE_IDX', - 'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR', - 'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX', - 'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA', - 'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX', - 'mmRLC_SPM_ACCUM_THRESHOLD', 'mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX', - 'mmRLC_SPM_DESER_START_SKEW', - 'mmRLC_SPM_DESER_START_SKEW_BASE_IDX', - 'mmRLC_SPM_GFXCLOCK_HIGHCOUNT', - 'mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX', - 'mmRLC_SPM_GFXCLOCK_LOWCOUNT', - 'mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX', - 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR', - 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX', - 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA', - 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX', - 'mmRLC_SPM_GLOBALS_MUXSEL_SKEW', - 'mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX', - 'mmRLC_SPM_GLOBALS_SAMPLE_SKEW', - 'mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX', - 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR', - 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', - 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET', - 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX', - 'mmRLC_SPM_GLOBAL_MUXSEL_DATA', - 'mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'mmRLC_SPM_INT_CNTL', - 'mmRLC_SPM_INT_CNTL_BASE_IDX', 'mmRLC_SPM_INT_INFO_1', - 'mmRLC_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_SPM_INT_INFO_2', - 'mmRLC_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_SPM_INT_STATUS', - 'mmRLC_SPM_INT_STATUS_BASE_IDX', 'mmRLC_SPM_MC_CNTL', - 'mmRLC_SPM_MC_CNTL_BASE_IDX', 'mmRLC_SPM_PERFMON_CNTL', - 'mmRLC_SPM_PERFMON_CNTL_BASE_IDX', - 'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_RING_BASE_HI', - 'mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', - 'mmRLC_SPM_PERFMON_RING_BASE_LO', - 'mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', - 'mmRLC_SPM_PERFMON_RING_SIZE', - 'mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE', - 'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX', - 'mmRLC_SPM_RING_RDPTR', 'mmRLC_SPM_RING_RDPTR_BASE_IDX', - 'mmRLC_SPM_RING_WRPTR', 'mmRLC_SPM_RING_WRPTR_BASE_IDX', - 'mmRLC_SPM_SAMPLE_CNT', 'mmRLC_SPM_SAMPLE_CNT_BASE_IDX', - 'mmRLC_SPM_SEGMENT_THRESHOLD', - 'mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', - 'mmRLC_SPM_SE_MUXSEL_ADDR', 'mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', - 'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET', - 'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX', - 'mmRLC_SPM_SE_MUXSEL_DATA', 'mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', - 'mmRLC_SPM_SE_MUXSEL_SKEW', 'mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX', - 'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR', - 'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX', - 'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA', - 'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX', - 'mmRLC_SPM_SE_SAMPLE_SKEW', 'mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX', - 'mmRLC_SPM_THREAD_TRACE_CTRL', - 'mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'mmRLC_SPM_UTCL1_CNTL', - 'mmRLC_SPM_UTCL1_CNTL_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_1', - 'mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_2', - 'mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'mmRLC_SPM_VIRT_CTRL', - 'mmRLC_SPM_VIRT_CTRL_BASE_IDX', 'mmRLC_SPM_VIRT_STATUS', - 'mmRLC_SPM_VIRT_STATUS_BASE_IDX', 'mmRLC_SPP_CAM_ADDR', - 'mmRLC_SPP_CAM_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_DATA', - 'mmRLC_SPP_CAM_DATA_BASE_IDX', 'mmRLC_SPP_CAM_EXT_ADDR', - 'mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_EXT_DATA', - 'mmRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'mmRLC_SPP_CTRL', - 'mmRLC_SPP_CTRL_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID', - 'mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID_VALID', - 'mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX', - 'mmRLC_SPP_INFLIGHT_RD_ADDR', - 'mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX', - 'mmRLC_SPP_INFLIGHT_RD_DATA', - 'mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'mmRLC_SPP_PBB_INFO', - 'mmRLC_SPP_PBB_INFO_BASE_IDX', 'mmRLC_SPP_PROF_INFO_1', - 'mmRLC_SPP_PROF_INFO_1_BASE_IDX', 'mmRLC_SPP_PROF_INFO_2', - 'mmRLC_SPP_PROF_INFO_2_BASE_IDX', 'mmRLC_SPP_PVT_LEVEL_MAX', - 'mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'mmRLC_SPP_PVT_STAT_0', - 'mmRLC_SPP_PVT_STAT_0_BASE_IDX', 'mmRLC_SPP_PVT_STAT_1', - 'mmRLC_SPP_PVT_STAT_1_BASE_IDX', 'mmRLC_SPP_PVT_STAT_2', - 'mmRLC_SPP_PVT_STAT_2_BASE_IDX', 'mmRLC_SPP_PVT_STAT_3', - 'mmRLC_SPP_PVT_STAT_3_BASE_IDX', 'mmRLC_SPP_RESET', - 'mmRLC_SPP_RESET_BASE_IDX', 'mmRLC_SPP_SHADER_PROFILE_EN', - 'mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX', - 'mmRLC_SPP_SSF_CAPTURE_EN', 'mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX', - 'mmRLC_SPP_SSF_THRESHOLD_0', 'mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX', - 'mmRLC_SPP_SSF_THRESHOLD_1', 'mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX', - 'mmRLC_SPP_SSF_THRESHOLD_2', 'mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX', - 'mmRLC_SPP_STALL_STATE_UPDATE', - 'mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'mmRLC_SPP_STATUS', - 'mmRLC_SPP_STATUS_BASE_IDX', 'mmRLC_SRM_ARAM_ADDR', - 'mmRLC_SRM_ARAM_ADDR_BASE_IDX', 'mmRLC_SRM_ARAM_DATA', - 'mmRLC_SRM_ARAM_DATA_BASE_IDX', 'mmRLC_SRM_CNTL', - 'mmRLC_SRM_CNTL_BASE_IDX', 'mmRLC_SRM_DRAM_ADDR', - 'mmRLC_SRM_DRAM_ADDR_BASE_IDX', 'mmRLC_SRM_DRAM_DATA', - 'mmRLC_SRM_DRAM_DATA_BASE_IDX', 'mmRLC_SRM_FWL_FIRST_VIOL_ADDR', - 'mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_SRM_GPM_ABORT', - 'mmRLC_SRM_GPM_ABORT_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND', - 'mmRLC_SRM_GPM_COMMAND_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND_STATUS', - 'mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_0', - 'mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_1', - 'mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_2', - 'mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_3', - 'mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_4', - 'mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_5', - 'mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_6', - 'mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_ADDR_7', - 'mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_0', - 'mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_1', - 'mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_2', - 'mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_3', - 'mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_4', - 'mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_5', - 'mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_6', - 'mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', - 'mmRLC_SRM_INDEX_CNTL_DATA_7', - 'mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'mmRLC_SRM_RLCV_COMMAND', - 'mmRLC_SRM_RLCV_COMMAND_BASE_IDX', - 'mmRLC_SRM_RLCV_COMMAND_STATUS', - 'mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX', 'mmRLC_SRM_STAT', - 'mmRLC_SRM_STAT_BASE_IDX', 'mmRLC_STAT', 'mmRLC_STATIC_PG_STATUS', - 'mmRLC_STATIC_PG_STATUS_BASE_IDX', 'mmRLC_STAT_BASE_IDX', - 'mmRLC_UCODE_CNTL', 'mmRLC_UCODE_CNTL_BASE_IDX', - 'mmRLC_UTCL1_STATUS', 'mmRLC_UTCL1_STATUS_2', - 'mmRLC_UTCL1_STATUS_2_BASE_IDX', 'mmRLC_UTCL1_STATUS_BASE_IDX', - 'mmRLC_WGP_STATUS', 'mmRLC_WGP_STATUS_BASE_IDX', - 'mmRLC_XT_DOORBELL_0_DATA_HI', - 'mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX', - 'mmRLC_XT_DOORBELL_0_DATA_LO', - 'mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX', - 'mmRLC_XT_DOORBELL_1_DATA_HI', - 'mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX', - 'mmRLC_XT_DOORBELL_1_DATA_LO', - 'mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX', - 'mmRLC_XT_DOORBELL_2_DATA_HI', - 'mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX', - 'mmRLC_XT_DOORBELL_2_DATA_LO', - 'mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX', - 'mmRLC_XT_DOORBELL_3_DATA_HI', - 'mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX', - 'mmRLC_XT_DOORBELL_3_DATA_LO', - 'mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', 'mmRLC_XT_DOORBELL_CNTL', - 'mmRLC_XT_DOORBELL_CNTL_BASE_IDX', 'mmRLC_XT_DOORBELL_RANGE', - 'mmRLC_XT_DOORBELL_RANGE_BASE_IDX', 'mmRLC_XT_DOORBELL_STAT', - 'mmRLC_XT_DOORBELL_STAT_BASE_IDX', 'mmRMI_CGTT_SCLK_CTRL', - 'mmRMI_CGTT_SCLK_CTRL_BASE_IDX', 'mmRMI_CLOCK_CNTRL', - 'mmRMI_CLOCK_CNTRL_BASE_IDX', 'mmRMI_DEMUX_CNTL', - 'mmRMI_DEMUX_CNTL_BASE_IDX', 'mmRMI_GENERAL_CNTL', - 'mmRMI_GENERAL_CNTL1', 'mmRMI_GENERAL_CNTL1_BASE_IDX', - 'mmRMI_GENERAL_CNTL_BASE_IDX', 'mmRMI_GENERAL_STATUS', - 'mmRMI_GENERAL_STATUS_BASE_IDX', 'mmRMI_PERFCOUNTER0_HI', - 'mmRMI_PERFCOUNTER0_HI_BASE_IDX', 'mmRMI_PERFCOUNTER0_LO', - 'mmRMI_PERFCOUNTER0_LO_BASE_IDX', 'mmRMI_PERFCOUNTER0_SELECT', - 'mmRMI_PERFCOUNTER0_SELECT1', - 'mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER1_HI', - 'mmRMI_PERFCOUNTER1_HI_BASE_IDX', 'mmRMI_PERFCOUNTER1_LO', - 'mmRMI_PERFCOUNTER1_LO_BASE_IDX', 'mmRMI_PERFCOUNTER1_SELECT', - 'mmRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER2_HI', - 'mmRMI_PERFCOUNTER2_HI_BASE_IDX', 'mmRMI_PERFCOUNTER2_LO', - 'mmRMI_PERFCOUNTER2_LO_BASE_IDX', 'mmRMI_PERFCOUNTER2_SELECT', - 'mmRMI_PERFCOUNTER2_SELECT1', - 'mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER3_HI', - 'mmRMI_PERFCOUNTER3_HI_BASE_IDX', 'mmRMI_PERFCOUNTER3_LO', - 'mmRMI_PERFCOUNTER3_LO_BASE_IDX', 'mmRMI_PERFCOUNTER3_SELECT', - 'mmRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmRMI_PERF_COUNTER_CNTL', - 'mmRMI_PERF_COUNTER_CNTL_BASE_IDX', 'mmRMI_PROBE_POP_LOGIC_CNTL', - 'mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'mmRMI_RB_GLX_CID_MAP', - 'mmRMI_RB_GLX_CID_MAP_BASE_IDX', 'mmRMI_SCOREBOARD_CNTL', - 'mmRMI_SCOREBOARD_CNTL_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS0', - 'mmRMI_SCOREBOARD_STATUS0_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS1', - 'mmRMI_SCOREBOARD_STATUS1_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS2', - 'mmRMI_SCOREBOARD_STATUS2_BASE_IDX', 'mmRMI_SPARE', - 'mmRMI_SPARE_1', 'mmRMI_SPARE_1_BASE_IDX', 'mmRMI_SPARE_2', - 'mmRMI_SPARE_2_BASE_IDX', 'mmRMI_SPARE_BASE_IDX', - 'mmRMI_SUBBLOCK_STATUS0', 'mmRMI_SUBBLOCK_STATUS0_BASE_IDX', - 'mmRMI_SUBBLOCK_STATUS1', 'mmRMI_SUBBLOCK_STATUS1_BASE_IDX', - 'mmRMI_SUBBLOCK_STATUS2', 'mmRMI_SUBBLOCK_STATUS2_BASE_IDX', - 'mmRMI_SUBBLOCK_STATUS3', 'mmRMI_SUBBLOCK_STATUS3_BASE_IDX', - 'mmRMI_TCIW_FORMATTER0_CNTL', - 'mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', - 'mmRMI_TCIW_FORMATTER1_CNTL', - 'mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'mmRMI_UTCL1_CNTL1', - 'mmRMI_UTCL1_CNTL1_BASE_IDX', 'mmRMI_UTCL1_CNTL2', - 'mmRMI_UTCL1_CNTL2_BASE_IDX', 'mmRMI_UTCL1_STATUS', - 'mmRMI_UTCL1_STATUS_BASE_IDX', 'mmRMI_UTC_UNIT_CONFIG', - 'mmRMI_UTC_UNIT_CONFIG_BASE_IDX', 'mmRMI_UTC_XNACK_N_MISC_CNTL', - 'mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', - 'mmRMI_XBAR_ARBITER_CONFIG', 'mmRMI_XBAR_ARBITER_CONFIG_1', - 'mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', - 'mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'mmRMI_XBAR_CONFIG', - 'mmRMI_XBAR_CONFIG_BASE_IDX', 'mmRTAVFS_RTAVFS_REG_ADDR', - 'mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'mmRTAVFS_RTAVFS_WR_DATA', - 'mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'mmSCRATCH_ADDR', - 'mmSCRATCH_ADDR_BASE_IDX', 'mmSCRATCH_REG0', - 'mmSCRATCH_REG0_BASE_IDX', 'mmSCRATCH_REG1', - 'mmSCRATCH_REG1_BASE_IDX', 'mmSCRATCH_REG2', - 'mmSCRATCH_REG2_BASE_IDX', 'mmSCRATCH_REG3', - 'mmSCRATCH_REG3_BASE_IDX', 'mmSCRATCH_REG4', - 'mmSCRATCH_REG4_BASE_IDX', 'mmSCRATCH_REG5', - 'mmSCRATCH_REG5_BASE_IDX', 'mmSCRATCH_REG6', - 'mmSCRATCH_REG6_BASE_IDX', 'mmSCRATCH_REG7', - 'mmSCRATCH_REG7_BASE_IDX', 'mmSCRATCH_REG_ATOMIC', - 'mmSCRATCH_REG_ATOMIC_BASE_IDX', 'mmSCRATCH_REG_CMPSWAP_ATOMIC', - 'mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'mmSCRATCH_UMSK', - 'mmSCRATCH_UMSK_BASE_IDX', 'mmSDMA0_ACTIVE_FCN_ID', - 'mmSDMA0_ACTIVE_FCN_ID_BASE_IDX', 'mmSDMA0_AQL_STATUS', - 'mmSDMA0_AQL_STATUS_BASE_IDX', 'mmSDMA0_ATOMIC_CNTL', - 'mmSDMA0_ATOMIC_CNTL_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_HI', - 'mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_LO', - 'mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'mmSDMA0_BA_THRESHOLD', - 'mmSDMA0_BA_THRESHOLD_BASE_IDX', 'mmSDMA0_BROADCAST_UCODE_ADDR', - 'mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX', - 'mmSDMA0_BROADCAST_UCODE_DATA', - 'mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'mmSDMA0_CHICKEN_BITS', - 'mmSDMA0_CHICKEN_BITS_2', 'mmSDMA0_CHICKEN_BITS_2_BASE_IDX', - 'mmSDMA0_CHICKEN_BITS_BASE_IDX', 'mmSDMA0_CLK_CTRL', - 'mmSDMA0_CLK_CTRL_BASE_IDX', 'mmSDMA0_CLOCK_GATING_REG', - 'mmSDMA0_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA0_CNTL', - 'mmSDMA0_CNTL_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE0', - 'mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE1', - 'mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE2', - 'mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE3', - 'mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA0_CRD_CNTL', - 'mmSDMA0_CRD_CNTL_BASE_IDX', 'mmSDMA0_DEC_START', - 'mmSDMA0_DEC_START_BASE_IDX', 'mmSDMA0_EA_DBIT_ADDR_DATA', - 'mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX', - 'mmSDMA0_EA_DBIT_ADDR_INDEX', - 'mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA0_EDC_CONFIG', - 'mmSDMA0_EDC_CONFIG_BASE_IDX', 'mmSDMA0_EDC_COUNTER', - 'mmSDMA0_EDC_COUNTER_BASE_IDX', 'mmSDMA0_EDC_COUNTER_CLEAR', - 'mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA0_ERROR_LOG', - 'mmSDMA0_ERROR_LOG_BASE_IDX', 'mmSDMA0_F32_CNTL', - 'mmSDMA0_F32_CNTL_BASE_IDX', 'mmSDMA0_F32_COUNTER', - 'mmSDMA0_F32_COUNTER_BASE_IDX', 'mmSDMA0_FREEZE', - 'mmSDMA0_FREEZE_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG', - 'mmSDMA0_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG_READ', - 'mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX', - 'mmSDMA0_GFX_CONTEXT_CNTL', 'mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX', - 'mmSDMA0_GFX_CONTEXT_STATUS', - 'mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_HI', - 'mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_LO', - 'mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA0_GFX_DOORBELL', - 'mmSDMA0_GFX_DOORBELL_BASE_IDX', 'mmSDMA0_GFX_DOORBELL_LOG', - 'mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_GFX_DOORBELL_OFFSET', - 'mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_GFX_DUMMY_REG', - 'mmSDMA0_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_HI', - 'mmSDMA0_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_LO', - 'mmSDMA0_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA0_GFX_IB_CNTL', - 'mmSDMA0_GFX_IB_CNTL_BASE_IDX', 'mmSDMA0_GFX_IB_OFFSET', - 'mmSDMA0_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA0_GFX_IB_RPTR', - 'mmSDMA0_GFX_IB_RPTR_BASE_IDX', 'mmSDMA0_GFX_IB_SIZE', - 'mmSDMA0_GFX_IB_SIZE_BASE_IDX', 'mmSDMA0_GFX_IB_SUB_REMAIN', - 'mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_CNTL', - 'mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA0', - 'mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA1', - 'mmSDMA0_GFX_MIDCMD_DATA10', 'mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA2', - 'mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA3', - 'mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA4', - 'mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA5', - 'mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA6', - 'mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA7', - 'mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA8', - 'mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA9', - 'mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_GFX_MINOR_PTR_UPDATE', - 'mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_GFX_PREEMPT', - 'mmSDMA0_GFX_PREEMPT_BASE_IDX', 'mmSDMA0_GFX_RB_AQL_CNTL', - 'mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_BASE', - 'mmSDMA0_GFX_RB_BASE_BASE_IDX', 'mmSDMA0_GFX_RB_BASE_HI', - 'mmSDMA0_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_RB_CNTL', - 'mmSDMA0_GFX_RB_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR', - 'mmSDMA0_GFX_RB_RPTR_ADDR_HI', - 'mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_GFX_RB_RPTR_ADDR_LO', - 'mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_GFX_RB_RPTR_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR_HI', - 'mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR', - 'mmSDMA0_GFX_RB_WPTR_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR_HI', - 'mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_GFX_RB_WPTR_POLL_CNTL', - 'mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA0_GFX_SKIP_CNTL', - 'mmSDMA0_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA0_GFX_STATUS', - 'mmSDMA0_GFX_STATUS_BASE_IDX', 'mmSDMA0_GFX_WATERMARK', - 'mmSDMA0_GFX_WATERMARK_BASE_IDX', 'mmSDMA0_GLOBAL_TIMESTAMP_HI', - 'mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'mmSDMA0_GLOBAL_TIMESTAMP_LO', - 'mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA0_HBM_PAGE_CONFIG', - 'mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA0_HOLE_ADDR_HI', - 'mmSDMA0_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA0_HOLE_ADDR_LO', - 'mmSDMA0_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA0_IB_OFFSET_FETCH', - 'mmSDMA0_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA0_ID', - 'mmSDMA0_ID_BASE_IDX', 'mmSDMA0_INT_STATUS', - 'mmSDMA0_INT_STATUS_BASE_IDX', 'mmSDMA0_PAGE_CONTEXT_STATUS', - 'mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_PAGE_CSA_ADDR_HI', 'mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_PAGE_CSA_ADDR_LO', 'mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_PAGE_DOORBELL', 'mmSDMA0_PAGE_DOORBELL_BASE_IDX', - 'mmSDMA0_PAGE_DOORBELL_LOG', 'mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_PAGE_DOORBELL_OFFSET', - 'mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_DUMMY_REG', - 'mmSDMA0_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_HI', - 'mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_LO', - 'mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA0_PAGE_IB_CNTL', - 'mmSDMA0_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_IB_OFFSET', - 'mmSDMA0_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_IB_RPTR', - 'mmSDMA0_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_IB_SIZE', - 'mmSDMA0_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA0_PAGE_IB_SUB_REMAIN', - 'mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_CNTL', - 'mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA0', - 'mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA1', - 'mmSDMA0_PAGE_MIDCMD_DATA10', - 'mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA2', - 'mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA3', - 'mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA4', - 'mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA5', - 'mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA6', - 'mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA7', - 'mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA8', - 'mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA9', - 'mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_PAGE_MINOR_PTR_UPDATE', - 'mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_PAGE_PREEMPT', - 'mmSDMA0_PAGE_PREEMPT_BASE_IDX', 'mmSDMA0_PAGE_RB_AQL_CNTL', - 'mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE', - 'mmSDMA0_PAGE_RB_BASE_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE_HI', - 'mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_CNTL', - 'mmSDMA0_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR', - 'mmSDMA0_PAGE_RB_RPTR_ADDR_HI', - 'mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_PAGE_RB_RPTR_ADDR_LO', - 'mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR_HI', - 'mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR', - 'mmSDMA0_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR_HI', - 'mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL', - 'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_PAGE_SKIP_CNTL', 'mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_PAGE_STATUS', 'mmSDMA0_PAGE_STATUS_BASE_IDX', - 'mmSDMA0_PAGE_WATERMARK', 'mmSDMA0_PAGE_WATERMARK_BASE_IDX', - 'mmSDMA0_PERFCNT_MISC_CNTL', 'mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX', - 'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG', - 'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG', - 'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'mmSDMA0_PERFCNT_PERFCOUNTER_HI', - 'mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'mmSDMA0_PERFCNT_PERFCOUNTER_LO', - 'mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmSDMA0_PERFCOUNTER0_HI', 'mmSDMA0_PERFCOUNTER0_HI_BASE_IDX', - 'mmSDMA0_PERFCOUNTER0_LO', 'mmSDMA0_PERFCOUNTER0_LO_BASE_IDX', - 'mmSDMA0_PERFCOUNTER0_SELECT', 'mmSDMA0_PERFCOUNTER0_SELECT1', - 'mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_HI', - 'mmSDMA0_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_LO', - 'mmSDMA0_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_SELECT', - 'mmSDMA0_PERFCOUNTER1_SELECT1', - 'mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA0_PG_CNTL', - 'mmSDMA0_PG_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_CNTL', - 'mmSDMA0_PG_CTX_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_HI', - 'mmSDMA0_PG_CTX_HI_BASE_IDX', 'mmSDMA0_PG_CTX_LO', - 'mmSDMA0_PG_CTX_LO_BASE_IDX', 'mmSDMA0_PHASE0_QUANTUM', - 'mmSDMA0_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE1_QUANTUM', - 'mmSDMA0_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE2_QUANTUM', - 'mmSDMA0_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_HI', - 'mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_LO', - 'mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA0_POWER_CNTL', - 'mmSDMA0_POWER_CNTL_BASE_IDX', 'mmSDMA0_PROGRAM', - 'mmSDMA0_PROGRAM_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG0', - 'mmSDMA0_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG1', - 'mmSDMA0_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG2', - 'mmSDMA0_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG3', - 'mmSDMA0_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE0', - 'mmSDMA0_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE1', - 'mmSDMA0_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE2', - 'mmSDMA0_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE3', - 'mmSDMA0_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA0_QUEUE_RESET_REQ', - 'mmSDMA0_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH', - 'mmSDMA0_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH_HI', - 'mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA0_RD_BURST_CNTL', - 'mmSDMA0_RD_BURST_CNTL_BASE_IDX', 'mmSDMA0_RELAX_ORDERING_LUT', - 'mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX', - 'mmSDMA0_RLC0_CONTEXT_STATUS', - 'mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC0_CSA_ADDR_HI', 'mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC0_CSA_ADDR_LO', 'mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC0_DOORBELL', 'mmSDMA0_RLC0_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC0_DOORBELL_LOG', 'mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC0_DOORBELL_OFFSET', - 'mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_DUMMY_REG', - 'mmSDMA0_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_HI', - 'mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_LO', - 'mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC0_IB_CNTL', - 'mmSDMA0_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_IB_OFFSET', - 'mmSDMA0_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_IB_RPTR', - 'mmSDMA0_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_IB_SIZE', - 'mmSDMA0_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC0_IB_SUB_REMAIN', - 'mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_CNTL', - 'mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA0', - 'mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA1', - 'mmSDMA0_RLC0_MIDCMD_DATA10', - 'mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA2', - 'mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA3', - 'mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA4', - 'mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA5', - 'mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA6', - 'mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA7', - 'mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA8', - 'mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA9', - 'mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC0_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC0_PREEMPT', - 'mmSDMA0_RLC0_PREEMPT_BASE_IDX', 'mmSDMA0_RLC0_RB_AQL_CNTL', - 'mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE', - 'mmSDMA0_RLC0_RB_BASE_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE_HI', - 'mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_CNTL', - 'mmSDMA0_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR', - 'mmSDMA0_RLC0_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC0_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR_HI', - 'mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR', - 'mmSDMA0_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR_HI', - 'mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC0_SKIP_CNTL', 'mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC0_STATUS', 'mmSDMA0_RLC0_STATUS_BASE_IDX', - 'mmSDMA0_RLC0_WATERMARK', 'mmSDMA0_RLC0_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC1_CONTEXT_STATUS', - 'mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC1_CSA_ADDR_HI', 'mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC1_CSA_ADDR_LO', 'mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC1_DOORBELL', 'mmSDMA0_RLC1_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC1_DOORBELL_LOG', 'mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC1_DOORBELL_OFFSET', - 'mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_DUMMY_REG', - 'mmSDMA0_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_HI', - 'mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_LO', - 'mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC1_IB_CNTL', - 'mmSDMA0_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_IB_OFFSET', - 'mmSDMA0_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_IB_RPTR', - 'mmSDMA0_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_IB_SIZE', - 'mmSDMA0_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC1_IB_SUB_REMAIN', - 'mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_CNTL', - 'mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA0', - 'mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA1', - 'mmSDMA0_RLC1_MIDCMD_DATA10', - 'mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA2', - 'mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA3', - 'mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA4', - 'mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA5', - 'mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA6', - 'mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA7', - 'mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA8', - 'mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA9', - 'mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC1_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC1_PREEMPT', - 'mmSDMA0_RLC1_PREEMPT_BASE_IDX', 'mmSDMA0_RLC1_RB_AQL_CNTL', - 'mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE', - 'mmSDMA0_RLC1_RB_BASE_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE_HI', - 'mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_CNTL', - 'mmSDMA0_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR', - 'mmSDMA0_RLC1_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC1_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR_HI', - 'mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR', - 'mmSDMA0_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR_HI', - 'mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC1_SKIP_CNTL', 'mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC1_STATUS', 'mmSDMA0_RLC1_STATUS_BASE_IDX', - 'mmSDMA0_RLC1_WATERMARK', 'mmSDMA0_RLC1_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC2_CONTEXT_STATUS', - 'mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC2_CSA_ADDR_HI', 'mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC2_CSA_ADDR_LO', 'mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC2_DOORBELL', 'mmSDMA0_RLC2_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC2_DOORBELL_LOG', 'mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC2_DOORBELL_OFFSET', - 'mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_DUMMY_REG', - 'mmSDMA0_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_HI', - 'mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_LO', - 'mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC2_IB_CNTL', - 'mmSDMA0_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_IB_OFFSET', - 'mmSDMA0_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_IB_RPTR', - 'mmSDMA0_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_IB_SIZE', - 'mmSDMA0_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC2_IB_SUB_REMAIN', - 'mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_CNTL', - 'mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA0', - 'mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA1', - 'mmSDMA0_RLC2_MIDCMD_DATA10', - 'mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA2', - 'mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA3', - 'mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA4', - 'mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA5', - 'mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA6', - 'mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA7', - 'mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA8', - 'mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA9', - 'mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC2_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC2_PREEMPT', - 'mmSDMA0_RLC2_PREEMPT_BASE_IDX', 'mmSDMA0_RLC2_RB_AQL_CNTL', - 'mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE', - 'mmSDMA0_RLC2_RB_BASE_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE_HI', - 'mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_CNTL', - 'mmSDMA0_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR', - 'mmSDMA0_RLC2_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC2_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR_HI', - 'mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR', - 'mmSDMA0_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR_HI', - 'mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC2_SKIP_CNTL', 'mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC2_STATUS', 'mmSDMA0_RLC2_STATUS_BASE_IDX', - 'mmSDMA0_RLC2_WATERMARK', 'mmSDMA0_RLC2_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC3_CONTEXT_STATUS', - 'mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC3_CSA_ADDR_HI', 'mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC3_CSA_ADDR_LO', 'mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC3_DOORBELL', 'mmSDMA0_RLC3_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC3_DOORBELL_LOG', 'mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC3_DOORBELL_OFFSET', - 'mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_DUMMY_REG', - 'mmSDMA0_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_HI', - 'mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_LO', - 'mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC3_IB_CNTL', - 'mmSDMA0_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_IB_OFFSET', - 'mmSDMA0_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_IB_RPTR', - 'mmSDMA0_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_IB_SIZE', - 'mmSDMA0_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC3_IB_SUB_REMAIN', - 'mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_CNTL', - 'mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA0', - 'mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA1', - 'mmSDMA0_RLC3_MIDCMD_DATA10', - 'mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA2', - 'mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA3', - 'mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA4', - 'mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA5', - 'mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA6', - 'mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA7', - 'mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA8', - 'mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA9', - 'mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC3_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC3_PREEMPT', - 'mmSDMA0_RLC3_PREEMPT_BASE_IDX', 'mmSDMA0_RLC3_RB_AQL_CNTL', - 'mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE', - 'mmSDMA0_RLC3_RB_BASE_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE_HI', - 'mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_CNTL', - 'mmSDMA0_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR', - 'mmSDMA0_RLC3_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC3_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR_HI', - 'mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR', - 'mmSDMA0_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR_HI', - 'mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC3_SKIP_CNTL', 'mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC3_STATUS', 'mmSDMA0_RLC3_STATUS_BASE_IDX', - 'mmSDMA0_RLC3_WATERMARK', 'mmSDMA0_RLC3_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC4_CONTEXT_STATUS', - 'mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC4_CSA_ADDR_HI', 'mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC4_CSA_ADDR_LO', 'mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC4_DOORBELL', 'mmSDMA0_RLC4_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC4_DOORBELL_LOG', 'mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC4_DOORBELL_OFFSET', - 'mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_DUMMY_REG', - 'mmSDMA0_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_HI', - 'mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_LO', - 'mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC4_IB_CNTL', - 'mmSDMA0_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_IB_OFFSET', - 'mmSDMA0_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_IB_RPTR', - 'mmSDMA0_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_IB_SIZE', - 'mmSDMA0_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC4_IB_SUB_REMAIN', - 'mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_CNTL', - 'mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA0', - 'mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA1', - 'mmSDMA0_RLC4_MIDCMD_DATA10', - 'mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA2', - 'mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA3', - 'mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA4', - 'mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA5', - 'mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA6', - 'mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA7', - 'mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA8', - 'mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA9', - 'mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC4_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC4_PREEMPT', - 'mmSDMA0_RLC4_PREEMPT_BASE_IDX', 'mmSDMA0_RLC4_RB_AQL_CNTL', - 'mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE', - 'mmSDMA0_RLC4_RB_BASE_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE_HI', - 'mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_CNTL', - 'mmSDMA0_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR', - 'mmSDMA0_RLC4_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC4_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR_HI', - 'mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR', - 'mmSDMA0_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR_HI', - 'mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC4_SKIP_CNTL', 'mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC4_STATUS', 'mmSDMA0_RLC4_STATUS_BASE_IDX', - 'mmSDMA0_RLC4_WATERMARK', 'mmSDMA0_RLC4_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC5_CONTEXT_STATUS', - 'mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC5_CSA_ADDR_HI', 'mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC5_CSA_ADDR_LO', 'mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC5_DOORBELL', 'mmSDMA0_RLC5_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC5_DOORBELL_LOG', 'mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC5_DOORBELL_OFFSET', - 'mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_DUMMY_REG', - 'mmSDMA0_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_HI', - 'mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_LO', - 'mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC5_IB_CNTL', - 'mmSDMA0_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_IB_OFFSET', - 'mmSDMA0_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_IB_RPTR', - 'mmSDMA0_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_IB_SIZE', - 'mmSDMA0_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC5_IB_SUB_REMAIN', - 'mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_CNTL', - 'mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA0', - 'mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA1', - 'mmSDMA0_RLC5_MIDCMD_DATA10', - 'mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA2', - 'mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA3', - 'mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA4', - 'mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA5', - 'mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA6', - 'mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA7', - 'mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA8', - 'mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA9', - 'mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC5_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC5_PREEMPT', - 'mmSDMA0_RLC5_PREEMPT_BASE_IDX', 'mmSDMA0_RLC5_RB_AQL_CNTL', - 'mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE', - 'mmSDMA0_RLC5_RB_BASE_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE_HI', - 'mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_CNTL', - 'mmSDMA0_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR', - 'mmSDMA0_RLC5_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC5_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR_HI', - 'mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR', - 'mmSDMA0_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR_HI', - 'mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC5_SKIP_CNTL', 'mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC5_STATUS', 'mmSDMA0_RLC5_STATUS_BASE_IDX', - 'mmSDMA0_RLC5_WATERMARK', 'mmSDMA0_RLC5_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC6_CONTEXT_STATUS', - 'mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC6_CSA_ADDR_HI', 'mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC6_CSA_ADDR_LO', 'mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC6_DOORBELL', 'mmSDMA0_RLC6_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC6_DOORBELL_LOG', 'mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC6_DOORBELL_OFFSET', - 'mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_DUMMY_REG', - 'mmSDMA0_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_HI', - 'mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_LO', - 'mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC6_IB_CNTL', - 'mmSDMA0_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_IB_OFFSET', - 'mmSDMA0_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_IB_RPTR', - 'mmSDMA0_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_IB_SIZE', - 'mmSDMA0_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC6_IB_SUB_REMAIN', - 'mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_CNTL', - 'mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA0', - 'mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA1', - 'mmSDMA0_RLC6_MIDCMD_DATA10', - 'mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA2', - 'mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA3', - 'mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA4', - 'mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA5', - 'mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA6', - 'mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA7', - 'mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA8', - 'mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA9', - 'mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC6_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC6_PREEMPT', - 'mmSDMA0_RLC6_PREEMPT_BASE_IDX', 'mmSDMA0_RLC6_RB_AQL_CNTL', - 'mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE', - 'mmSDMA0_RLC6_RB_BASE_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE_HI', - 'mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_CNTL', - 'mmSDMA0_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR', - 'mmSDMA0_RLC6_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC6_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR_HI', - 'mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR', - 'mmSDMA0_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR_HI', - 'mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC6_SKIP_CNTL', 'mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC6_STATUS', 'mmSDMA0_RLC6_STATUS_BASE_IDX', - 'mmSDMA0_RLC6_WATERMARK', 'mmSDMA0_RLC6_WATERMARK_BASE_IDX', - 'mmSDMA0_RLC7_CONTEXT_STATUS', - 'mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA0_RLC7_CSA_ADDR_HI', 'mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC7_CSA_ADDR_LO', 'mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC7_DOORBELL', 'mmSDMA0_RLC7_DOORBELL_BASE_IDX', - 'mmSDMA0_RLC7_DOORBELL_LOG', 'mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX', - 'mmSDMA0_RLC7_DOORBELL_OFFSET', - 'mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_DUMMY_REG', - 'mmSDMA0_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_HI', - 'mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_LO', - 'mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC7_IB_CNTL', - 'mmSDMA0_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_IB_OFFSET', - 'mmSDMA0_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_IB_RPTR', - 'mmSDMA0_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_IB_SIZE', - 'mmSDMA0_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC7_IB_SUB_REMAIN', - 'mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_CNTL', - 'mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA0', - 'mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA1', - 'mmSDMA0_RLC7_MIDCMD_DATA10', - 'mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA2', - 'mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA3', - 'mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA4', - 'mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA5', - 'mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA6', - 'mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA7', - 'mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA8', - 'mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA9', - 'mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA0_RLC7_MINOR_PTR_UPDATE', - 'mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC7_PREEMPT', - 'mmSDMA0_RLC7_PREEMPT_BASE_IDX', 'mmSDMA0_RLC7_RB_AQL_CNTL', - 'mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE', - 'mmSDMA0_RLC7_RB_BASE_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE_HI', - 'mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_CNTL', - 'mmSDMA0_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR', - 'mmSDMA0_RLC7_RB_RPTR_ADDR_HI', - 'mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC7_RB_RPTR_ADDR_LO', - 'mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR_HI', - 'mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR', - 'mmSDMA0_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR_HI', - 'mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX', - 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL', - 'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA0_RLC7_SKIP_CNTL', 'mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX', - 'mmSDMA0_RLC7_STATUS', 'mmSDMA0_RLC7_STATUS_BASE_IDX', - 'mmSDMA0_RLC7_WATERMARK', 'mmSDMA0_RLC7_WATERMARK_BASE_IDX', - 'mmSDMA0_SCRATCH_RAM_ADDR', 'mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', - 'mmSDMA0_SCRATCH_RAM_DATA', 'mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX', - 'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL', - 'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'mmSDMA0_STATUS1_REG', 'mmSDMA0_STATUS1_REG_BASE_IDX', - 'mmSDMA0_STATUS2_REG', 'mmSDMA0_STATUS2_REG_BASE_IDX', - 'mmSDMA0_STATUS3_REG', 'mmSDMA0_STATUS3_REG_BASE_IDX', - 'mmSDMA0_STATUS4_REG', 'mmSDMA0_STATUS4_REG_BASE_IDX', - 'mmSDMA0_STATUS5_REG', 'mmSDMA0_STATUS5_REG_BASE_IDX', - 'mmSDMA0_STATUS_REG', 'mmSDMA0_STATUS_REG_BASE_IDX', - 'mmSDMA0_TILING_CONFIG', 'mmSDMA0_TILING_CONFIG_BASE_IDX', - 'mmSDMA0_TIMESTAMP_CNTL', 'mmSDMA0_TIMESTAMP_CNTL_BASE_IDX', - 'mmSDMA0_TLBI_GCR_CNTL', 'mmSDMA0_TLBI_GCR_CNTL_BASE_IDX', - 'mmSDMA0_UCODE_ADDR', 'mmSDMA0_UCODE_ADDR_BASE_IDX', - 'mmSDMA0_UCODE_CHECKSUM', 'mmSDMA0_UCODE_CHECKSUM_BASE_IDX', - 'mmSDMA0_UCODE_DATA', 'mmSDMA0_UCODE_DATA_BASE_IDX', - 'mmSDMA0_UTCL1_CNTL', 'mmSDMA0_UTCL1_CNTL_BASE_IDX', - 'mmSDMA0_UTCL1_INV0', 'mmSDMA0_UTCL1_INV0_BASE_IDX', - 'mmSDMA0_UTCL1_INV1', 'mmSDMA0_UTCL1_INV1_BASE_IDX', - 'mmSDMA0_UTCL1_INV2', 'mmSDMA0_UTCL1_INV2_BASE_IDX', - 'mmSDMA0_UTCL1_PAGE', 'mmSDMA0_UTCL1_PAGE_BASE_IDX', - 'mmSDMA0_UTCL1_RD_STATUS', 'mmSDMA0_UTCL1_RD_STATUS_BASE_IDX', - 'mmSDMA0_UTCL1_RD_XNACK0', 'mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX', - 'mmSDMA0_UTCL1_RD_XNACK1', 'mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX', - 'mmSDMA0_UTCL1_TIMEOUT', 'mmSDMA0_UTCL1_TIMEOUT_BASE_IDX', - 'mmSDMA0_UTCL1_WATERMK', 'mmSDMA0_UTCL1_WATERMK_BASE_IDX', - 'mmSDMA0_UTCL1_WR_STATUS', 'mmSDMA0_UTCL1_WR_STATUS_BASE_IDX', - 'mmSDMA0_UTCL1_WR_XNACK0', 'mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX', - 'mmSDMA0_UTCL1_WR_XNACK1', 'mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX', - 'mmSDMA0_VERSION', 'mmSDMA0_VERSION_BASE_IDX', - 'mmSDMA0_VF_ENABLE', 'mmSDMA0_VF_ENABLE_BASE_IDX', - 'mmSDMA0_VIRT_RESET_REQ', 'mmSDMA0_VIRT_RESET_REQ_BASE_IDX', - 'mmSDMA0_VM_CNTL', 'mmSDMA0_VM_CNTL_BASE_IDX', - 'mmSDMA0_VM_CTX_CNTL', 'mmSDMA0_VM_CTX_CNTL_BASE_IDX', - 'mmSDMA0_VM_CTX_HI', 'mmSDMA0_VM_CTX_HI_BASE_IDX', - 'mmSDMA0_VM_CTX_LO', 'mmSDMA0_VM_CTX_LO_BASE_IDX', - 'mmSDMA1_ACTIVE_FCN_ID', 'mmSDMA1_ACTIVE_FCN_ID_BASE_IDX', - 'mmSDMA1_AQL_STATUS', 'mmSDMA1_AQL_STATUS_BASE_IDX', - 'mmSDMA1_ATOMIC_CNTL', 'mmSDMA1_ATOMIC_CNTL_BASE_IDX', - 'mmSDMA1_ATOMIC_PREOP_HI', 'mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX', - 'mmSDMA1_ATOMIC_PREOP_LO', 'mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX', - 'mmSDMA1_BA_THRESHOLD', 'mmSDMA1_BA_THRESHOLD_BASE_IDX', - 'mmSDMA1_CHICKEN_BITS', 'mmSDMA1_CHICKEN_BITS_2', - 'mmSDMA1_CHICKEN_BITS_2_BASE_IDX', - 'mmSDMA1_CHICKEN_BITS_BASE_IDX', 'mmSDMA1_CLK_CTRL', - 'mmSDMA1_CLK_CTRL_BASE_IDX', 'mmSDMA1_CLOCK_GATING_REG', - 'mmSDMA1_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA1_CNTL', - 'mmSDMA1_CNTL_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE0', - 'mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE1', - 'mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE2', - 'mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE3', - 'mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA1_CRD_CNTL', - 'mmSDMA1_CRD_CNTL_BASE_IDX', 'mmSDMA1_DEC_START', - 'mmSDMA1_DEC_START_BASE_IDX', 'mmSDMA1_EA_DBIT_ADDR_DATA', - 'mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX', - 'mmSDMA1_EA_DBIT_ADDR_INDEX', - 'mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA1_EDC_CONFIG', - 'mmSDMA1_EDC_CONFIG_BASE_IDX', 'mmSDMA1_EDC_COUNTER', - 'mmSDMA1_EDC_COUNTER_BASE_IDX', 'mmSDMA1_EDC_COUNTER_CLEAR', - 'mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA1_ERROR_LOG', - 'mmSDMA1_ERROR_LOG_BASE_IDX', 'mmSDMA1_F32_CNTL', - 'mmSDMA1_F32_CNTL_BASE_IDX', 'mmSDMA1_F32_COUNTER', - 'mmSDMA1_F32_COUNTER_BASE_IDX', 'mmSDMA1_FREEZE', - 'mmSDMA1_FREEZE_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG', - 'mmSDMA1_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG_READ', - 'mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX', - 'mmSDMA1_GFX_CONTEXT_CNTL', 'mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX', - 'mmSDMA1_GFX_CONTEXT_STATUS', - 'mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_HI', - 'mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_LO', - 'mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA1_GFX_DOORBELL', - 'mmSDMA1_GFX_DOORBELL_BASE_IDX', 'mmSDMA1_GFX_DOORBELL_LOG', - 'mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_GFX_DOORBELL_OFFSET', - 'mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_GFX_DUMMY_REG', - 'mmSDMA1_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_HI', - 'mmSDMA1_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_LO', - 'mmSDMA1_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA1_GFX_IB_CNTL', - 'mmSDMA1_GFX_IB_CNTL_BASE_IDX', 'mmSDMA1_GFX_IB_OFFSET', - 'mmSDMA1_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA1_GFX_IB_RPTR', - 'mmSDMA1_GFX_IB_RPTR_BASE_IDX', 'mmSDMA1_GFX_IB_SIZE', - 'mmSDMA1_GFX_IB_SIZE_BASE_IDX', 'mmSDMA1_GFX_IB_SUB_REMAIN', - 'mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_CNTL', - 'mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA0', - 'mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA1', - 'mmSDMA1_GFX_MIDCMD_DATA10', 'mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA2', - 'mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA3', - 'mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA4', - 'mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA5', - 'mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA6', - 'mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA7', - 'mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA8', - 'mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA9', - 'mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_GFX_MINOR_PTR_UPDATE', - 'mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_GFX_PREEMPT', - 'mmSDMA1_GFX_PREEMPT_BASE_IDX', 'mmSDMA1_GFX_RB_AQL_CNTL', - 'mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_BASE', - 'mmSDMA1_GFX_RB_BASE_BASE_IDX', 'mmSDMA1_GFX_RB_BASE_HI', - 'mmSDMA1_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_RB_CNTL', - 'mmSDMA1_GFX_RB_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR', - 'mmSDMA1_GFX_RB_RPTR_ADDR_HI', - 'mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_GFX_RB_RPTR_ADDR_LO', - 'mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_GFX_RB_RPTR_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR_HI', - 'mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR', - 'mmSDMA1_GFX_RB_WPTR_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR_HI', - 'mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_GFX_RB_WPTR_POLL_CNTL', - 'mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA1_GFX_SKIP_CNTL', - 'mmSDMA1_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA1_GFX_STATUS', - 'mmSDMA1_GFX_STATUS_BASE_IDX', 'mmSDMA1_GFX_WATERMARK', - 'mmSDMA1_GFX_WATERMARK_BASE_IDX', 'mmSDMA1_GLOBAL_TIMESTAMP_HI', - 'mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'mmSDMA1_GLOBAL_TIMESTAMP_LO', - 'mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA1_HBM_PAGE_CONFIG', - 'mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA1_HOLE_ADDR_HI', - 'mmSDMA1_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA1_HOLE_ADDR_LO', - 'mmSDMA1_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA1_IB_OFFSET_FETCH', - 'mmSDMA1_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA1_ID', - 'mmSDMA1_ID_BASE_IDX', 'mmSDMA1_INT_STATUS', - 'mmSDMA1_INT_STATUS_BASE_IDX', 'mmSDMA1_PAGE_CONTEXT_STATUS', - 'mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_PAGE_CSA_ADDR_HI', 'mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_PAGE_CSA_ADDR_LO', 'mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_PAGE_DOORBELL', 'mmSDMA1_PAGE_DOORBELL_BASE_IDX', - 'mmSDMA1_PAGE_DOORBELL_LOG', 'mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_PAGE_DOORBELL_OFFSET', - 'mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_DUMMY_REG', - 'mmSDMA1_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_HI', - 'mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_LO', - 'mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA1_PAGE_IB_CNTL', - 'mmSDMA1_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_IB_OFFSET', - 'mmSDMA1_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_IB_RPTR', - 'mmSDMA1_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_IB_SIZE', - 'mmSDMA1_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA1_PAGE_IB_SUB_REMAIN', - 'mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_CNTL', - 'mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA0', - 'mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA1', - 'mmSDMA1_PAGE_MIDCMD_DATA10', - 'mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA2', - 'mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA3', - 'mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA4', - 'mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA5', - 'mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA6', - 'mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA7', - 'mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA8', - 'mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA9', - 'mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_PAGE_MINOR_PTR_UPDATE', - 'mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_PAGE_PREEMPT', - 'mmSDMA1_PAGE_PREEMPT_BASE_IDX', 'mmSDMA1_PAGE_RB_AQL_CNTL', - 'mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE', - 'mmSDMA1_PAGE_RB_BASE_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE_HI', - 'mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_CNTL', - 'mmSDMA1_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR', - 'mmSDMA1_PAGE_RB_RPTR_ADDR_HI', - 'mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_PAGE_RB_RPTR_ADDR_LO', - 'mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR_HI', - 'mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR', - 'mmSDMA1_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR_HI', - 'mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL', - 'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_PAGE_SKIP_CNTL', 'mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_PAGE_STATUS', 'mmSDMA1_PAGE_STATUS_BASE_IDX', - 'mmSDMA1_PAGE_WATERMARK', 'mmSDMA1_PAGE_WATERMARK_BASE_IDX', - 'mmSDMA1_PERFCNT_MISC_CNTL', 'mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX', - 'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG', - 'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG', - 'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'mmSDMA1_PERFCNT_PERFCOUNTER_HI', - 'mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'mmSDMA1_PERFCNT_PERFCOUNTER_LO', - 'mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmSDMA1_PERFCOUNTER0_HI', 'mmSDMA1_PERFCOUNTER0_HI_BASE_IDX', - 'mmSDMA1_PERFCOUNTER0_LO', 'mmSDMA1_PERFCOUNTER0_LO_BASE_IDX', - 'mmSDMA1_PERFCOUNTER0_SELECT', 'mmSDMA1_PERFCOUNTER0_SELECT1', - 'mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_HI', - 'mmSDMA1_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_LO', - 'mmSDMA1_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_SELECT', - 'mmSDMA1_PERFCOUNTER1_SELECT1', - 'mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA1_PG_CNTL', - 'mmSDMA1_PG_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_CNTL', - 'mmSDMA1_PG_CTX_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_HI', - 'mmSDMA1_PG_CTX_HI_BASE_IDX', 'mmSDMA1_PG_CTX_LO', - 'mmSDMA1_PG_CTX_LO_BASE_IDX', 'mmSDMA1_PHASE0_QUANTUM', - 'mmSDMA1_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE1_QUANTUM', - 'mmSDMA1_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE2_QUANTUM', - 'mmSDMA1_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_HI', - 'mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_LO', - 'mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA1_POWER_CNTL', - 'mmSDMA1_POWER_CNTL_BASE_IDX', 'mmSDMA1_PROGRAM', - 'mmSDMA1_PROGRAM_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG0', - 'mmSDMA1_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG1', - 'mmSDMA1_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG2', - 'mmSDMA1_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG3', - 'mmSDMA1_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE0', - 'mmSDMA1_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE1', - 'mmSDMA1_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE2', - 'mmSDMA1_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE3', - 'mmSDMA1_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA1_QUEUE_RESET_REQ', - 'mmSDMA1_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH', - 'mmSDMA1_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH_HI', - 'mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA1_RD_BURST_CNTL', - 'mmSDMA1_RD_BURST_CNTL_BASE_IDX', 'mmSDMA1_RELAX_ORDERING_LUT', - 'mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX', - 'mmSDMA1_RLC0_CONTEXT_STATUS', - 'mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC0_CSA_ADDR_HI', 'mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC0_CSA_ADDR_LO', 'mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC0_DOORBELL', 'mmSDMA1_RLC0_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC0_DOORBELL_LOG', 'mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC0_DOORBELL_OFFSET', - 'mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_DUMMY_REG', - 'mmSDMA1_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_HI', - 'mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_LO', - 'mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC0_IB_CNTL', - 'mmSDMA1_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_IB_OFFSET', - 'mmSDMA1_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_IB_RPTR', - 'mmSDMA1_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_IB_SIZE', - 'mmSDMA1_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC0_IB_SUB_REMAIN', - 'mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_CNTL', - 'mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA0', - 'mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA1', - 'mmSDMA1_RLC0_MIDCMD_DATA10', - 'mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA2', - 'mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA3', - 'mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA4', - 'mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA5', - 'mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA6', - 'mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA7', - 'mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA8', - 'mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA9', - 'mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC0_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC0_PREEMPT', - 'mmSDMA1_RLC0_PREEMPT_BASE_IDX', 'mmSDMA1_RLC0_RB_AQL_CNTL', - 'mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE', - 'mmSDMA1_RLC0_RB_BASE_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE_HI', - 'mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_CNTL', - 'mmSDMA1_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR', - 'mmSDMA1_RLC0_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC0_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR_HI', - 'mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR', - 'mmSDMA1_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR_HI', - 'mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC0_SKIP_CNTL', 'mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC0_STATUS', 'mmSDMA1_RLC0_STATUS_BASE_IDX', - 'mmSDMA1_RLC0_WATERMARK', 'mmSDMA1_RLC0_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC1_CONTEXT_STATUS', - 'mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC1_CSA_ADDR_HI', 'mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC1_CSA_ADDR_LO', 'mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC1_DOORBELL', 'mmSDMA1_RLC1_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC1_DOORBELL_LOG', 'mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC1_DOORBELL_OFFSET', - 'mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_DUMMY_REG', - 'mmSDMA1_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_HI', - 'mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_LO', - 'mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC1_IB_CNTL', - 'mmSDMA1_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_IB_OFFSET', - 'mmSDMA1_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_IB_RPTR', - 'mmSDMA1_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_IB_SIZE', - 'mmSDMA1_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC1_IB_SUB_REMAIN', - 'mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_CNTL', - 'mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA0', - 'mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA1', - 'mmSDMA1_RLC1_MIDCMD_DATA10', - 'mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA2', - 'mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA3', - 'mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA4', - 'mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA5', - 'mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA6', - 'mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA7', - 'mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA8', - 'mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA9', - 'mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC1_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC1_PREEMPT', - 'mmSDMA1_RLC1_PREEMPT_BASE_IDX', 'mmSDMA1_RLC1_RB_AQL_CNTL', - 'mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE', - 'mmSDMA1_RLC1_RB_BASE_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE_HI', - 'mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_CNTL', - 'mmSDMA1_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR', - 'mmSDMA1_RLC1_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC1_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR_HI', - 'mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR', - 'mmSDMA1_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR_HI', - 'mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC1_SKIP_CNTL', 'mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC1_STATUS', 'mmSDMA1_RLC1_STATUS_BASE_IDX', - 'mmSDMA1_RLC1_WATERMARK', 'mmSDMA1_RLC1_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC2_CONTEXT_STATUS', - 'mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC2_CSA_ADDR_HI', 'mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC2_CSA_ADDR_LO', 'mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC2_DOORBELL', 'mmSDMA1_RLC2_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC2_DOORBELL_LOG', 'mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC2_DOORBELL_OFFSET', - 'mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_DUMMY_REG', - 'mmSDMA1_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_HI', - 'mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_LO', - 'mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC2_IB_CNTL', - 'mmSDMA1_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_IB_OFFSET', - 'mmSDMA1_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_IB_RPTR', - 'mmSDMA1_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_IB_SIZE', - 'mmSDMA1_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC2_IB_SUB_REMAIN', - 'mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_CNTL', - 'mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA0', - 'mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA1', - 'mmSDMA1_RLC2_MIDCMD_DATA10', - 'mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA2', - 'mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA3', - 'mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA4', - 'mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA5', - 'mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA6', - 'mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA7', - 'mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA8', - 'mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA9', - 'mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC2_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC2_PREEMPT', - 'mmSDMA1_RLC2_PREEMPT_BASE_IDX', 'mmSDMA1_RLC2_RB_AQL_CNTL', - 'mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE', - 'mmSDMA1_RLC2_RB_BASE_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE_HI', - 'mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_CNTL', - 'mmSDMA1_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR', - 'mmSDMA1_RLC2_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC2_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR_HI', - 'mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR', - 'mmSDMA1_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR_HI', - 'mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC2_SKIP_CNTL', 'mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC2_STATUS', 'mmSDMA1_RLC2_STATUS_BASE_IDX', - 'mmSDMA1_RLC2_WATERMARK', 'mmSDMA1_RLC2_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC3_CONTEXT_STATUS', - 'mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC3_CSA_ADDR_HI', 'mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC3_CSA_ADDR_LO', 'mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC3_DOORBELL', 'mmSDMA1_RLC3_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC3_DOORBELL_LOG', 'mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC3_DOORBELL_OFFSET', - 'mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_DUMMY_REG', - 'mmSDMA1_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_HI', - 'mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_LO', - 'mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC3_IB_CNTL', - 'mmSDMA1_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_IB_OFFSET', - 'mmSDMA1_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_IB_RPTR', - 'mmSDMA1_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_IB_SIZE', - 'mmSDMA1_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC3_IB_SUB_REMAIN', - 'mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_CNTL', - 'mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA0', - 'mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA1', - 'mmSDMA1_RLC3_MIDCMD_DATA10', - 'mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA2', - 'mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA3', - 'mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA4', - 'mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA5', - 'mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA6', - 'mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA7', - 'mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA8', - 'mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA9', - 'mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC3_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC3_PREEMPT', - 'mmSDMA1_RLC3_PREEMPT_BASE_IDX', 'mmSDMA1_RLC3_RB_AQL_CNTL', - 'mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE', - 'mmSDMA1_RLC3_RB_BASE_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE_HI', - 'mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_CNTL', - 'mmSDMA1_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR', - 'mmSDMA1_RLC3_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC3_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR_HI', - 'mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR', - 'mmSDMA1_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR_HI', - 'mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC3_SKIP_CNTL', 'mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC3_STATUS', 'mmSDMA1_RLC3_STATUS_BASE_IDX', - 'mmSDMA1_RLC3_WATERMARK', 'mmSDMA1_RLC3_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC4_CONTEXT_STATUS', - 'mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC4_CSA_ADDR_HI', 'mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC4_CSA_ADDR_LO', 'mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC4_DOORBELL', 'mmSDMA1_RLC4_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC4_DOORBELL_LOG', 'mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC4_DOORBELL_OFFSET', - 'mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_DUMMY_REG', - 'mmSDMA1_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_HI', - 'mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_LO', - 'mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC4_IB_CNTL', - 'mmSDMA1_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_IB_OFFSET', - 'mmSDMA1_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_IB_RPTR', - 'mmSDMA1_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_IB_SIZE', - 'mmSDMA1_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC4_IB_SUB_REMAIN', - 'mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_CNTL', - 'mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA0', - 'mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA1', - 'mmSDMA1_RLC4_MIDCMD_DATA10', - 'mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA2', - 'mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA3', - 'mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA4', - 'mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA5', - 'mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA6', - 'mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA7', - 'mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA8', - 'mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA9', - 'mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC4_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC4_PREEMPT', - 'mmSDMA1_RLC4_PREEMPT_BASE_IDX', 'mmSDMA1_RLC4_RB_AQL_CNTL', - 'mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE', - 'mmSDMA1_RLC4_RB_BASE_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE_HI', - 'mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_CNTL', - 'mmSDMA1_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR', - 'mmSDMA1_RLC4_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC4_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR_HI', - 'mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR', - 'mmSDMA1_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR_HI', - 'mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC4_SKIP_CNTL', 'mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC4_STATUS', 'mmSDMA1_RLC4_STATUS_BASE_IDX', - 'mmSDMA1_RLC4_WATERMARK', 'mmSDMA1_RLC4_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC5_CONTEXT_STATUS', - 'mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC5_CSA_ADDR_HI', 'mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC5_CSA_ADDR_LO', 'mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC5_DOORBELL', 'mmSDMA1_RLC5_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC5_DOORBELL_LOG', 'mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC5_DOORBELL_OFFSET', - 'mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_DUMMY_REG', - 'mmSDMA1_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_HI', - 'mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_LO', - 'mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC5_IB_CNTL', - 'mmSDMA1_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_IB_OFFSET', - 'mmSDMA1_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_IB_RPTR', - 'mmSDMA1_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_IB_SIZE', - 'mmSDMA1_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC5_IB_SUB_REMAIN', - 'mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_CNTL', - 'mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA0', - 'mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA1', - 'mmSDMA1_RLC5_MIDCMD_DATA10', - 'mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA2', - 'mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA3', - 'mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA4', - 'mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA5', - 'mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA6', - 'mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA7', - 'mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA8', - 'mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA9', - 'mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC5_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC5_PREEMPT', - 'mmSDMA1_RLC5_PREEMPT_BASE_IDX', 'mmSDMA1_RLC5_RB_AQL_CNTL', - 'mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE', - 'mmSDMA1_RLC5_RB_BASE_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE_HI', - 'mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_CNTL', - 'mmSDMA1_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR', - 'mmSDMA1_RLC5_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC5_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR_HI', - 'mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR', - 'mmSDMA1_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR_HI', - 'mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC5_SKIP_CNTL', 'mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC5_STATUS', 'mmSDMA1_RLC5_STATUS_BASE_IDX', - 'mmSDMA1_RLC5_WATERMARK', 'mmSDMA1_RLC5_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC6_CONTEXT_STATUS', - 'mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC6_CSA_ADDR_HI', 'mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC6_CSA_ADDR_LO', 'mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC6_DOORBELL', 'mmSDMA1_RLC6_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC6_DOORBELL_LOG', 'mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC6_DOORBELL_OFFSET', - 'mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_DUMMY_REG', - 'mmSDMA1_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_HI', - 'mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_LO', - 'mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC6_IB_CNTL', - 'mmSDMA1_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_IB_OFFSET', - 'mmSDMA1_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_IB_RPTR', - 'mmSDMA1_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_IB_SIZE', - 'mmSDMA1_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC6_IB_SUB_REMAIN', - 'mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_CNTL', - 'mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA0', - 'mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA1', - 'mmSDMA1_RLC6_MIDCMD_DATA10', - 'mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA2', - 'mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA3', - 'mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA4', - 'mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA5', - 'mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA6', - 'mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA7', - 'mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA8', - 'mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA9', - 'mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC6_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC6_PREEMPT', - 'mmSDMA1_RLC6_PREEMPT_BASE_IDX', 'mmSDMA1_RLC6_RB_AQL_CNTL', - 'mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE', - 'mmSDMA1_RLC6_RB_BASE_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE_HI', - 'mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_CNTL', - 'mmSDMA1_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR', - 'mmSDMA1_RLC6_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC6_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR_HI', - 'mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR', - 'mmSDMA1_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR_HI', - 'mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC6_SKIP_CNTL', 'mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC6_STATUS', 'mmSDMA1_RLC6_STATUS_BASE_IDX', - 'mmSDMA1_RLC6_WATERMARK', 'mmSDMA1_RLC6_WATERMARK_BASE_IDX', - 'mmSDMA1_RLC7_CONTEXT_STATUS', - 'mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA1_RLC7_CSA_ADDR_HI', 'mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC7_CSA_ADDR_LO', 'mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC7_DOORBELL', 'mmSDMA1_RLC7_DOORBELL_BASE_IDX', - 'mmSDMA1_RLC7_DOORBELL_LOG', 'mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX', - 'mmSDMA1_RLC7_DOORBELL_OFFSET', - 'mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_DUMMY_REG', - 'mmSDMA1_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_HI', - 'mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_LO', - 'mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC7_IB_CNTL', - 'mmSDMA1_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_IB_OFFSET', - 'mmSDMA1_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_IB_RPTR', - 'mmSDMA1_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_IB_SIZE', - 'mmSDMA1_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC7_IB_SUB_REMAIN', - 'mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_CNTL', - 'mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA0', - 'mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA1', - 'mmSDMA1_RLC7_MIDCMD_DATA10', - 'mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA2', - 'mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA3', - 'mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA4', - 'mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA5', - 'mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA6', - 'mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA7', - 'mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA8', - 'mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA9', - 'mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA1_RLC7_MINOR_PTR_UPDATE', - 'mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC7_PREEMPT', - 'mmSDMA1_RLC7_PREEMPT_BASE_IDX', 'mmSDMA1_RLC7_RB_AQL_CNTL', - 'mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE', - 'mmSDMA1_RLC7_RB_BASE_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE_HI', - 'mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_CNTL', - 'mmSDMA1_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR', - 'mmSDMA1_RLC7_RB_RPTR_ADDR_HI', - 'mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC7_RB_RPTR_ADDR_LO', - 'mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR_HI', - 'mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR', - 'mmSDMA1_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR_HI', - 'mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX', - 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL', - 'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA1_RLC7_SKIP_CNTL', 'mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX', - 'mmSDMA1_RLC7_STATUS', 'mmSDMA1_RLC7_STATUS_BASE_IDX', - 'mmSDMA1_RLC7_WATERMARK', 'mmSDMA1_RLC7_WATERMARK_BASE_IDX', - 'mmSDMA1_SCRATCH_RAM_ADDR', 'mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', - 'mmSDMA1_SCRATCH_RAM_DATA', 'mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX', - 'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL', - 'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'mmSDMA1_STATUS1_REG', 'mmSDMA1_STATUS1_REG_BASE_IDX', - 'mmSDMA1_STATUS2_REG', 'mmSDMA1_STATUS2_REG_BASE_IDX', - 'mmSDMA1_STATUS3_REG', 'mmSDMA1_STATUS3_REG_BASE_IDX', - 'mmSDMA1_STATUS4_REG', 'mmSDMA1_STATUS4_REG_BASE_IDX', - 'mmSDMA1_STATUS5_REG', 'mmSDMA1_STATUS5_REG_BASE_IDX', - 'mmSDMA1_STATUS_REG', 'mmSDMA1_STATUS_REG_BASE_IDX', - 'mmSDMA1_TILING_CONFIG', 'mmSDMA1_TILING_CONFIG_BASE_IDX', - 'mmSDMA1_TIMESTAMP_CNTL', 'mmSDMA1_TIMESTAMP_CNTL_BASE_IDX', - 'mmSDMA1_TLBI_GCR_CNTL', 'mmSDMA1_TLBI_GCR_CNTL_BASE_IDX', - 'mmSDMA1_UCODE_ADDR', 'mmSDMA1_UCODE_ADDR_BASE_IDX', - 'mmSDMA1_UCODE_CHECKSUM', 'mmSDMA1_UCODE_CHECKSUM_BASE_IDX', - 'mmSDMA1_UCODE_DATA', 'mmSDMA1_UCODE_DATA_BASE_IDX', - 'mmSDMA1_UTCL1_CNTL', 'mmSDMA1_UTCL1_CNTL_BASE_IDX', - 'mmSDMA1_UTCL1_INV0', 'mmSDMA1_UTCL1_INV0_BASE_IDX', - 'mmSDMA1_UTCL1_INV1', 'mmSDMA1_UTCL1_INV1_BASE_IDX', - 'mmSDMA1_UTCL1_INV2', 'mmSDMA1_UTCL1_INV2_BASE_IDX', - 'mmSDMA1_UTCL1_PAGE', 'mmSDMA1_UTCL1_PAGE_BASE_IDX', - 'mmSDMA1_UTCL1_RD_STATUS', 'mmSDMA1_UTCL1_RD_STATUS_BASE_IDX', - 'mmSDMA1_UTCL1_RD_XNACK0', 'mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX', - 'mmSDMA1_UTCL1_RD_XNACK1', 'mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX', - 'mmSDMA1_UTCL1_TIMEOUT', 'mmSDMA1_UTCL1_TIMEOUT_BASE_IDX', - 'mmSDMA1_UTCL1_WATERMK', 'mmSDMA1_UTCL1_WATERMK_BASE_IDX', - 'mmSDMA1_UTCL1_WR_STATUS', 'mmSDMA1_UTCL1_WR_STATUS_BASE_IDX', - 'mmSDMA1_UTCL1_WR_XNACK0', 'mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX', - 'mmSDMA1_UTCL1_WR_XNACK1', 'mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX', - 'mmSDMA1_VERSION', 'mmSDMA1_VERSION_BASE_IDX', - 'mmSDMA1_VF_ENABLE', 'mmSDMA1_VF_ENABLE_BASE_IDX', - 'mmSDMA1_VIRT_RESET_REQ', 'mmSDMA1_VIRT_RESET_REQ_BASE_IDX', - 'mmSDMA1_VM_CNTL', 'mmSDMA1_VM_CNTL_BASE_IDX', - 'mmSDMA1_VM_CTX_CNTL', 'mmSDMA1_VM_CTX_CNTL_BASE_IDX', - 'mmSDMA1_VM_CTX_HI', 'mmSDMA1_VM_CTX_HI_BASE_IDX', - 'mmSDMA1_VM_CTX_LO', 'mmSDMA1_VM_CTX_LO_BASE_IDX', - 'mmSDMA2_ACTIVE_FCN_ID', 'mmSDMA2_ACTIVE_FCN_ID_BASE_IDX', - 'mmSDMA2_AQL_STATUS', 'mmSDMA2_AQL_STATUS_BASE_IDX', - 'mmSDMA2_ATOMIC_CNTL', 'mmSDMA2_ATOMIC_CNTL_BASE_IDX', - 'mmSDMA2_ATOMIC_PREOP_HI', 'mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX', - 'mmSDMA2_ATOMIC_PREOP_LO', 'mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX', - 'mmSDMA2_BA_THRESHOLD', 'mmSDMA2_BA_THRESHOLD_BASE_IDX', - 'mmSDMA2_CHICKEN_BITS', 'mmSDMA2_CHICKEN_BITS_2', - 'mmSDMA2_CHICKEN_BITS_2_BASE_IDX', - 'mmSDMA2_CHICKEN_BITS_BASE_IDX', 'mmSDMA2_CLK_CTRL', - 'mmSDMA2_CLK_CTRL_BASE_IDX', 'mmSDMA2_CLOCK_GATING_REG', - 'mmSDMA2_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA2_CNTL', - 'mmSDMA2_CNTL_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE0', - 'mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE1', - 'mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE2', - 'mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE3', - 'mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA2_CRD_CNTL', - 'mmSDMA2_CRD_CNTL_BASE_IDX', 'mmSDMA2_DEC_START', - 'mmSDMA2_DEC_START_BASE_IDX', 'mmSDMA2_EA_DBIT_ADDR_DATA', - 'mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX', - 'mmSDMA2_EA_DBIT_ADDR_INDEX', - 'mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA2_EDC_CONFIG', - 'mmSDMA2_EDC_CONFIG_BASE_IDX', 'mmSDMA2_EDC_COUNTER', - 'mmSDMA2_EDC_COUNTER_BASE_IDX', 'mmSDMA2_EDC_COUNTER_CLEAR', - 'mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA2_ERROR_LOG', - 'mmSDMA2_ERROR_LOG_BASE_IDX', 'mmSDMA2_F32_CNTL', - 'mmSDMA2_F32_CNTL_BASE_IDX', 'mmSDMA2_F32_COUNTER', - 'mmSDMA2_F32_COUNTER_BASE_IDX', 'mmSDMA2_FREEZE', - 'mmSDMA2_FREEZE_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG', - 'mmSDMA2_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG_READ', - 'mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX', - 'mmSDMA2_GFX_CONTEXT_CNTL', 'mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX', - 'mmSDMA2_GFX_CONTEXT_STATUS', - 'mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_HI', - 'mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_LO', - 'mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA2_GFX_DOORBELL', - 'mmSDMA2_GFX_DOORBELL_BASE_IDX', 'mmSDMA2_GFX_DOORBELL_LOG', - 'mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_GFX_DOORBELL_OFFSET', - 'mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_GFX_DUMMY_REG', - 'mmSDMA2_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_HI', - 'mmSDMA2_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_LO', - 'mmSDMA2_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA2_GFX_IB_CNTL', - 'mmSDMA2_GFX_IB_CNTL_BASE_IDX', 'mmSDMA2_GFX_IB_OFFSET', - 'mmSDMA2_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA2_GFX_IB_RPTR', - 'mmSDMA2_GFX_IB_RPTR_BASE_IDX', 'mmSDMA2_GFX_IB_SIZE', - 'mmSDMA2_GFX_IB_SIZE_BASE_IDX', 'mmSDMA2_GFX_IB_SUB_REMAIN', - 'mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_CNTL', - 'mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA0', - 'mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA1', - 'mmSDMA2_GFX_MIDCMD_DATA10', 'mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA2', - 'mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA3', - 'mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA4', - 'mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA5', - 'mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA6', - 'mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA7', - 'mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA8', - 'mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA9', - 'mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_GFX_MINOR_PTR_UPDATE', - 'mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_GFX_PREEMPT', - 'mmSDMA2_GFX_PREEMPT_BASE_IDX', 'mmSDMA2_GFX_RB_AQL_CNTL', - 'mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_BASE', - 'mmSDMA2_GFX_RB_BASE_BASE_IDX', 'mmSDMA2_GFX_RB_BASE_HI', - 'mmSDMA2_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_RB_CNTL', - 'mmSDMA2_GFX_RB_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR', - 'mmSDMA2_GFX_RB_RPTR_ADDR_HI', - 'mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_GFX_RB_RPTR_ADDR_LO', - 'mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_GFX_RB_RPTR_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR_HI', - 'mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR', - 'mmSDMA2_GFX_RB_WPTR_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR_HI', - 'mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_GFX_RB_WPTR_POLL_CNTL', - 'mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA2_GFX_SKIP_CNTL', - 'mmSDMA2_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA2_GFX_STATUS', - 'mmSDMA2_GFX_STATUS_BASE_IDX', 'mmSDMA2_GFX_WATERMARK', - 'mmSDMA2_GFX_WATERMARK_BASE_IDX', 'mmSDMA2_GLOBAL_TIMESTAMP_HI', - 'mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'mmSDMA2_GLOBAL_TIMESTAMP_LO', - 'mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA2_HBM_PAGE_CONFIG', - 'mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA2_HOLE_ADDR_HI', - 'mmSDMA2_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA2_HOLE_ADDR_LO', - 'mmSDMA2_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA2_IB_OFFSET_FETCH', - 'mmSDMA2_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA2_ID', - 'mmSDMA2_ID_BASE_IDX', 'mmSDMA2_INT_STATUS', - 'mmSDMA2_INT_STATUS_BASE_IDX', 'mmSDMA2_PAGE_CONTEXT_STATUS', - 'mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_PAGE_CSA_ADDR_HI', 'mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_PAGE_CSA_ADDR_LO', 'mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_PAGE_DOORBELL', 'mmSDMA2_PAGE_DOORBELL_BASE_IDX', - 'mmSDMA2_PAGE_DOORBELL_LOG', 'mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_PAGE_DOORBELL_OFFSET', - 'mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_DUMMY_REG', - 'mmSDMA2_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_HI', - 'mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_LO', - 'mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA2_PAGE_IB_CNTL', - 'mmSDMA2_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_IB_OFFSET', - 'mmSDMA2_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_IB_RPTR', - 'mmSDMA2_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_IB_SIZE', - 'mmSDMA2_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA2_PAGE_IB_SUB_REMAIN', - 'mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_CNTL', - 'mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA0', - 'mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA1', - 'mmSDMA2_PAGE_MIDCMD_DATA10', - 'mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA2', - 'mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA3', - 'mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA4', - 'mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA5', - 'mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA6', - 'mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA7', - 'mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA8', - 'mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA9', - 'mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_PAGE_MINOR_PTR_UPDATE', - 'mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_PAGE_PREEMPT', - 'mmSDMA2_PAGE_PREEMPT_BASE_IDX', 'mmSDMA2_PAGE_RB_AQL_CNTL', - 'mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE', - 'mmSDMA2_PAGE_RB_BASE_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE_HI', - 'mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_CNTL', - 'mmSDMA2_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR', - 'mmSDMA2_PAGE_RB_RPTR_ADDR_HI', - 'mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_PAGE_RB_RPTR_ADDR_LO', - 'mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR_HI', - 'mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR', - 'mmSDMA2_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR_HI', - 'mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL', - 'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_PAGE_SKIP_CNTL', 'mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_PAGE_STATUS', 'mmSDMA2_PAGE_STATUS_BASE_IDX', - 'mmSDMA2_PAGE_WATERMARK', 'mmSDMA2_PAGE_WATERMARK_BASE_IDX', - 'mmSDMA2_PERFCNT_MISC_CNTL', 'mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX', - 'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG', - 'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG', - 'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'mmSDMA2_PERFCNT_PERFCOUNTER_HI', - 'mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'mmSDMA2_PERFCNT_PERFCOUNTER_LO', - 'mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmSDMA2_PERFCOUNTER0_HI', 'mmSDMA2_PERFCOUNTER0_HI_BASE_IDX', - 'mmSDMA2_PERFCOUNTER0_LO', 'mmSDMA2_PERFCOUNTER0_LO_BASE_IDX', - 'mmSDMA2_PERFCOUNTER0_SELECT', 'mmSDMA2_PERFCOUNTER0_SELECT1', - 'mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_HI', - 'mmSDMA2_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_LO', - 'mmSDMA2_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_SELECT', - 'mmSDMA2_PERFCOUNTER1_SELECT1', - 'mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA2_PG_CNTL', - 'mmSDMA2_PG_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_CNTL', - 'mmSDMA2_PG_CTX_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_HI', - 'mmSDMA2_PG_CTX_HI_BASE_IDX', 'mmSDMA2_PG_CTX_LO', - 'mmSDMA2_PG_CTX_LO_BASE_IDX', 'mmSDMA2_PHASE0_QUANTUM', - 'mmSDMA2_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE1_QUANTUM', - 'mmSDMA2_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE2_QUANTUM', - 'mmSDMA2_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_HI', - 'mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_LO', - 'mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA2_POWER_CNTL', - 'mmSDMA2_POWER_CNTL_BASE_IDX', 'mmSDMA2_PROGRAM', - 'mmSDMA2_PROGRAM_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG0', - 'mmSDMA2_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG1', - 'mmSDMA2_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG2', - 'mmSDMA2_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG3', - 'mmSDMA2_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE0', - 'mmSDMA2_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE1', - 'mmSDMA2_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE2', - 'mmSDMA2_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE3', - 'mmSDMA2_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA2_QUEUE_RESET_REQ', - 'mmSDMA2_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH', - 'mmSDMA2_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH_HI', - 'mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA2_RD_BURST_CNTL', - 'mmSDMA2_RD_BURST_CNTL_BASE_IDX', 'mmSDMA2_RELAX_ORDERING_LUT', - 'mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX', - 'mmSDMA2_RLC0_CONTEXT_STATUS', - 'mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC0_CSA_ADDR_HI', 'mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC0_CSA_ADDR_LO', 'mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC0_DOORBELL', 'mmSDMA2_RLC0_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC0_DOORBELL_LOG', 'mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC0_DOORBELL_OFFSET', - 'mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_DUMMY_REG', - 'mmSDMA2_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_HI', - 'mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_LO', - 'mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC0_IB_CNTL', - 'mmSDMA2_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_IB_OFFSET', - 'mmSDMA2_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_IB_RPTR', - 'mmSDMA2_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_IB_SIZE', - 'mmSDMA2_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC0_IB_SUB_REMAIN', - 'mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_CNTL', - 'mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA0', - 'mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA1', - 'mmSDMA2_RLC0_MIDCMD_DATA10', - 'mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA2', - 'mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA3', - 'mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA4', - 'mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA5', - 'mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA6', - 'mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA7', - 'mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA8', - 'mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA9', - 'mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC0_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC0_PREEMPT', - 'mmSDMA2_RLC0_PREEMPT_BASE_IDX', 'mmSDMA2_RLC0_RB_AQL_CNTL', - 'mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE', - 'mmSDMA2_RLC0_RB_BASE_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE_HI', - 'mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_CNTL', - 'mmSDMA2_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR', - 'mmSDMA2_RLC0_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC0_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR_HI', - 'mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR', - 'mmSDMA2_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR_HI', - 'mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC0_SKIP_CNTL', 'mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC0_STATUS', 'mmSDMA2_RLC0_STATUS_BASE_IDX', - 'mmSDMA2_RLC0_WATERMARK', 'mmSDMA2_RLC0_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC1_CONTEXT_STATUS', - 'mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC1_CSA_ADDR_HI', 'mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC1_CSA_ADDR_LO', 'mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC1_DOORBELL', 'mmSDMA2_RLC1_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC1_DOORBELL_LOG', 'mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC1_DOORBELL_OFFSET', - 'mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_DUMMY_REG', - 'mmSDMA2_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_HI', - 'mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_LO', - 'mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC1_IB_CNTL', - 'mmSDMA2_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_IB_OFFSET', - 'mmSDMA2_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_IB_RPTR', - 'mmSDMA2_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_IB_SIZE', - 'mmSDMA2_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC1_IB_SUB_REMAIN', - 'mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_CNTL', - 'mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA0', - 'mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA1', - 'mmSDMA2_RLC1_MIDCMD_DATA10', - 'mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA2', - 'mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA3', - 'mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA4', - 'mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA5', - 'mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA6', - 'mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA7', - 'mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA8', - 'mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA9', - 'mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC1_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC1_PREEMPT', - 'mmSDMA2_RLC1_PREEMPT_BASE_IDX', 'mmSDMA2_RLC1_RB_AQL_CNTL', - 'mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE', - 'mmSDMA2_RLC1_RB_BASE_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE_HI', - 'mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_CNTL', - 'mmSDMA2_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR', - 'mmSDMA2_RLC1_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC1_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR_HI', - 'mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR', - 'mmSDMA2_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR_HI', - 'mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC1_SKIP_CNTL', 'mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC1_STATUS', 'mmSDMA2_RLC1_STATUS_BASE_IDX', - 'mmSDMA2_RLC1_WATERMARK', 'mmSDMA2_RLC1_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC2_CONTEXT_STATUS', - 'mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC2_CSA_ADDR_HI', 'mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC2_CSA_ADDR_LO', 'mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC2_DOORBELL', 'mmSDMA2_RLC2_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC2_DOORBELL_LOG', 'mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC2_DOORBELL_OFFSET', - 'mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_DUMMY_REG', - 'mmSDMA2_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_HI', - 'mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_LO', - 'mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC2_IB_CNTL', - 'mmSDMA2_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_IB_OFFSET', - 'mmSDMA2_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_IB_RPTR', - 'mmSDMA2_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_IB_SIZE', - 'mmSDMA2_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC2_IB_SUB_REMAIN', - 'mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_CNTL', - 'mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA0', - 'mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA1', - 'mmSDMA2_RLC2_MIDCMD_DATA10', - 'mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA2', - 'mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA3', - 'mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA4', - 'mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA5', - 'mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA6', - 'mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA7', - 'mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA8', - 'mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA9', - 'mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC2_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC2_PREEMPT', - 'mmSDMA2_RLC2_PREEMPT_BASE_IDX', 'mmSDMA2_RLC2_RB_AQL_CNTL', - 'mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE', - 'mmSDMA2_RLC2_RB_BASE_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE_HI', - 'mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_CNTL', - 'mmSDMA2_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR', - 'mmSDMA2_RLC2_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC2_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR_HI', - 'mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR', - 'mmSDMA2_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR_HI', - 'mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC2_SKIP_CNTL', 'mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC2_STATUS', 'mmSDMA2_RLC2_STATUS_BASE_IDX', - 'mmSDMA2_RLC2_WATERMARK', 'mmSDMA2_RLC2_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC3_CONTEXT_STATUS', - 'mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC3_CSA_ADDR_HI', 'mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC3_CSA_ADDR_LO', 'mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC3_DOORBELL', 'mmSDMA2_RLC3_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC3_DOORBELL_LOG', 'mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC3_DOORBELL_OFFSET', - 'mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_DUMMY_REG', - 'mmSDMA2_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_HI', - 'mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_LO', - 'mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC3_IB_CNTL', - 'mmSDMA2_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_IB_OFFSET', - 'mmSDMA2_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_IB_RPTR', - 'mmSDMA2_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_IB_SIZE', - 'mmSDMA2_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC3_IB_SUB_REMAIN', - 'mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_CNTL', - 'mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA0', - 'mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA1', - 'mmSDMA2_RLC3_MIDCMD_DATA10', - 'mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA2', - 'mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA3', - 'mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA4', - 'mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA5', - 'mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA6', - 'mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA7', - 'mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA8', - 'mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA9', - 'mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC3_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC3_PREEMPT', - 'mmSDMA2_RLC3_PREEMPT_BASE_IDX', 'mmSDMA2_RLC3_RB_AQL_CNTL', - 'mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE', - 'mmSDMA2_RLC3_RB_BASE_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE_HI', - 'mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_CNTL', - 'mmSDMA2_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR', - 'mmSDMA2_RLC3_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC3_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR_HI', - 'mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR', - 'mmSDMA2_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR_HI', - 'mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC3_SKIP_CNTL', 'mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC3_STATUS', 'mmSDMA2_RLC3_STATUS_BASE_IDX', - 'mmSDMA2_RLC3_WATERMARK', 'mmSDMA2_RLC3_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC4_CONTEXT_STATUS', - 'mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC4_CSA_ADDR_HI', 'mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC4_CSA_ADDR_LO', 'mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC4_DOORBELL', 'mmSDMA2_RLC4_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC4_DOORBELL_LOG', 'mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC4_DOORBELL_OFFSET', - 'mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_DUMMY_REG', - 'mmSDMA2_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_HI', - 'mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_LO', - 'mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC4_IB_CNTL', - 'mmSDMA2_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_IB_OFFSET', - 'mmSDMA2_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_IB_RPTR', - 'mmSDMA2_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_IB_SIZE', - 'mmSDMA2_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC4_IB_SUB_REMAIN', - 'mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_CNTL', - 'mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA0', - 'mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA1', - 'mmSDMA2_RLC4_MIDCMD_DATA10', - 'mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA2', - 'mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA3', - 'mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA4', - 'mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA5', - 'mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA6', - 'mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA7', - 'mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA8', - 'mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA9', - 'mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC4_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC4_PREEMPT', - 'mmSDMA2_RLC4_PREEMPT_BASE_IDX', 'mmSDMA2_RLC4_RB_AQL_CNTL', - 'mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE', - 'mmSDMA2_RLC4_RB_BASE_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE_HI', - 'mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_CNTL', - 'mmSDMA2_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR', - 'mmSDMA2_RLC4_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC4_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR_HI', - 'mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR', - 'mmSDMA2_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR_HI', - 'mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC4_SKIP_CNTL', 'mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC4_STATUS', 'mmSDMA2_RLC4_STATUS_BASE_IDX', - 'mmSDMA2_RLC4_WATERMARK', 'mmSDMA2_RLC4_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC5_CONTEXT_STATUS', - 'mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC5_CSA_ADDR_HI', 'mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC5_CSA_ADDR_LO', 'mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC5_DOORBELL', 'mmSDMA2_RLC5_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC5_DOORBELL_LOG', 'mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC5_DOORBELL_OFFSET', - 'mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_DUMMY_REG', - 'mmSDMA2_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_HI', - 'mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_LO', - 'mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC5_IB_CNTL', - 'mmSDMA2_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_IB_OFFSET', - 'mmSDMA2_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_IB_RPTR', - 'mmSDMA2_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_IB_SIZE', - 'mmSDMA2_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC5_IB_SUB_REMAIN', - 'mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_CNTL', - 'mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA0', - 'mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA1', - 'mmSDMA2_RLC5_MIDCMD_DATA10', - 'mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA2', - 'mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA3', - 'mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA4', - 'mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA5', - 'mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA6', - 'mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA7', - 'mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA8', - 'mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA9', - 'mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC5_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC5_PREEMPT', - 'mmSDMA2_RLC5_PREEMPT_BASE_IDX', 'mmSDMA2_RLC5_RB_AQL_CNTL', - 'mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE', - 'mmSDMA2_RLC5_RB_BASE_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE_HI', - 'mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_CNTL', - 'mmSDMA2_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR', - 'mmSDMA2_RLC5_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC5_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR_HI', - 'mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR', - 'mmSDMA2_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR_HI', - 'mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC5_SKIP_CNTL', 'mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC5_STATUS', 'mmSDMA2_RLC5_STATUS_BASE_IDX', - 'mmSDMA2_RLC5_WATERMARK', 'mmSDMA2_RLC5_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC6_CONTEXT_STATUS', - 'mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC6_CSA_ADDR_HI', 'mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC6_CSA_ADDR_LO', 'mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC6_DOORBELL', 'mmSDMA2_RLC6_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC6_DOORBELL_LOG', 'mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC6_DOORBELL_OFFSET', - 'mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_DUMMY_REG', - 'mmSDMA2_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_HI', - 'mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_LO', - 'mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC6_IB_CNTL', - 'mmSDMA2_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_IB_OFFSET', - 'mmSDMA2_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_IB_RPTR', - 'mmSDMA2_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_IB_SIZE', - 'mmSDMA2_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC6_IB_SUB_REMAIN', - 'mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_CNTL', - 'mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA0', - 'mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA1', - 'mmSDMA2_RLC6_MIDCMD_DATA10', - 'mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA2', - 'mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA3', - 'mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA4', - 'mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA5', - 'mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA6', - 'mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA7', - 'mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA8', - 'mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA9', - 'mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC6_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC6_PREEMPT', - 'mmSDMA2_RLC6_PREEMPT_BASE_IDX', 'mmSDMA2_RLC6_RB_AQL_CNTL', - 'mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE', - 'mmSDMA2_RLC6_RB_BASE_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE_HI', - 'mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_CNTL', - 'mmSDMA2_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR', - 'mmSDMA2_RLC6_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC6_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR_HI', - 'mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR', - 'mmSDMA2_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR_HI', - 'mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC6_SKIP_CNTL', 'mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC6_STATUS', 'mmSDMA2_RLC6_STATUS_BASE_IDX', - 'mmSDMA2_RLC6_WATERMARK', 'mmSDMA2_RLC6_WATERMARK_BASE_IDX', - 'mmSDMA2_RLC7_CONTEXT_STATUS', - 'mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA2_RLC7_CSA_ADDR_HI', 'mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC7_CSA_ADDR_LO', 'mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC7_DOORBELL', 'mmSDMA2_RLC7_DOORBELL_BASE_IDX', - 'mmSDMA2_RLC7_DOORBELL_LOG', 'mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX', - 'mmSDMA2_RLC7_DOORBELL_OFFSET', - 'mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_DUMMY_REG', - 'mmSDMA2_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_HI', - 'mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_LO', - 'mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC7_IB_CNTL', - 'mmSDMA2_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_IB_OFFSET', - 'mmSDMA2_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_IB_RPTR', - 'mmSDMA2_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_IB_SIZE', - 'mmSDMA2_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC7_IB_SUB_REMAIN', - 'mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_CNTL', - 'mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA0', - 'mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA1', - 'mmSDMA2_RLC7_MIDCMD_DATA10', - 'mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA2', - 'mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA3', - 'mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA4', - 'mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA5', - 'mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA6', - 'mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA7', - 'mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA8', - 'mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA9', - 'mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA2_RLC7_MINOR_PTR_UPDATE', - 'mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC7_PREEMPT', - 'mmSDMA2_RLC7_PREEMPT_BASE_IDX', 'mmSDMA2_RLC7_RB_AQL_CNTL', - 'mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE', - 'mmSDMA2_RLC7_RB_BASE_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE_HI', - 'mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_CNTL', - 'mmSDMA2_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR', - 'mmSDMA2_RLC7_RB_RPTR_ADDR_HI', - 'mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC7_RB_RPTR_ADDR_LO', - 'mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR_HI', - 'mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR', - 'mmSDMA2_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR_HI', - 'mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX', - 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL', - 'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA2_RLC7_SKIP_CNTL', 'mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX', - 'mmSDMA2_RLC7_STATUS', 'mmSDMA2_RLC7_STATUS_BASE_IDX', - 'mmSDMA2_RLC7_WATERMARK', 'mmSDMA2_RLC7_WATERMARK_BASE_IDX', - 'mmSDMA2_SCRATCH_RAM_ADDR', 'mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX', - 'mmSDMA2_SCRATCH_RAM_DATA', 'mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX', - 'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL', - 'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'mmSDMA2_STATUS1_REG', 'mmSDMA2_STATUS1_REG_BASE_IDX', - 'mmSDMA2_STATUS2_REG', 'mmSDMA2_STATUS2_REG_BASE_IDX', - 'mmSDMA2_STATUS3_REG', 'mmSDMA2_STATUS3_REG_BASE_IDX', - 'mmSDMA2_STATUS4_REG', 'mmSDMA2_STATUS4_REG_BASE_IDX', - 'mmSDMA2_STATUS5_REG', 'mmSDMA2_STATUS5_REG_BASE_IDX', - 'mmSDMA2_STATUS_REG', 'mmSDMA2_STATUS_REG_BASE_IDX', - 'mmSDMA2_TILING_CONFIG', 'mmSDMA2_TILING_CONFIG_BASE_IDX', - 'mmSDMA2_TIMESTAMP_CNTL', 'mmSDMA2_TIMESTAMP_CNTL_BASE_IDX', - 'mmSDMA2_TLBI_GCR_CNTL', 'mmSDMA2_TLBI_GCR_CNTL_BASE_IDX', - 'mmSDMA2_UCODE_ADDR', 'mmSDMA2_UCODE_ADDR_BASE_IDX', - 'mmSDMA2_UCODE_CHECKSUM', 'mmSDMA2_UCODE_CHECKSUM_BASE_IDX', - 'mmSDMA2_UCODE_DATA', 'mmSDMA2_UCODE_DATA_BASE_IDX', - 'mmSDMA2_UTCL1_CNTL', 'mmSDMA2_UTCL1_CNTL_BASE_IDX', - 'mmSDMA2_UTCL1_INV0', 'mmSDMA2_UTCL1_INV0_BASE_IDX', - 'mmSDMA2_UTCL1_INV1', 'mmSDMA2_UTCL1_INV1_BASE_IDX', - 'mmSDMA2_UTCL1_INV2', 'mmSDMA2_UTCL1_INV2_BASE_IDX', - 'mmSDMA2_UTCL1_PAGE', 'mmSDMA2_UTCL1_PAGE_BASE_IDX', - 'mmSDMA2_UTCL1_RD_STATUS', 'mmSDMA2_UTCL1_RD_STATUS_BASE_IDX', - 'mmSDMA2_UTCL1_RD_XNACK0', 'mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX', - 'mmSDMA2_UTCL1_RD_XNACK1', 'mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX', - 'mmSDMA2_UTCL1_TIMEOUT', 'mmSDMA2_UTCL1_TIMEOUT_BASE_IDX', - 'mmSDMA2_UTCL1_WATERMK', 'mmSDMA2_UTCL1_WATERMK_BASE_IDX', - 'mmSDMA2_UTCL1_WR_STATUS', 'mmSDMA2_UTCL1_WR_STATUS_BASE_IDX', - 'mmSDMA2_UTCL1_WR_XNACK0', 'mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX', - 'mmSDMA2_UTCL1_WR_XNACK1', 'mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX', - 'mmSDMA2_VERSION', 'mmSDMA2_VERSION_BASE_IDX', - 'mmSDMA2_VF_ENABLE', 'mmSDMA2_VF_ENABLE_BASE_IDX', - 'mmSDMA2_VIRT_RESET_REQ', 'mmSDMA2_VIRT_RESET_REQ_BASE_IDX', - 'mmSDMA2_VM_CNTL', 'mmSDMA2_VM_CNTL_BASE_IDX', - 'mmSDMA2_VM_CTX_CNTL', 'mmSDMA2_VM_CTX_CNTL_BASE_IDX', - 'mmSDMA2_VM_CTX_HI', 'mmSDMA2_VM_CTX_HI_BASE_IDX', - 'mmSDMA2_VM_CTX_LO', 'mmSDMA2_VM_CTX_LO_BASE_IDX', - 'mmSDMA3_ACTIVE_FCN_ID', 'mmSDMA3_ACTIVE_FCN_ID_BASE_IDX', - 'mmSDMA3_AQL_STATUS', 'mmSDMA3_AQL_STATUS_BASE_IDX', - 'mmSDMA3_ATOMIC_CNTL', 'mmSDMA3_ATOMIC_CNTL_BASE_IDX', - 'mmSDMA3_ATOMIC_PREOP_HI', 'mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX', - 'mmSDMA3_ATOMIC_PREOP_LO', 'mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX', - 'mmSDMA3_BA_THRESHOLD', 'mmSDMA3_BA_THRESHOLD_BASE_IDX', - 'mmSDMA3_CHICKEN_BITS', 'mmSDMA3_CHICKEN_BITS_2', - 'mmSDMA3_CHICKEN_BITS_2_BASE_IDX', - 'mmSDMA3_CHICKEN_BITS_BASE_IDX', 'mmSDMA3_CLK_CTRL', - 'mmSDMA3_CLK_CTRL_BASE_IDX', 'mmSDMA3_CLOCK_GATING_REG', - 'mmSDMA3_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA3_CNTL', - 'mmSDMA3_CNTL_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE0', - 'mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE1', - 'mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE2', - 'mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE3', - 'mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA3_CRD_CNTL', - 'mmSDMA3_CRD_CNTL_BASE_IDX', 'mmSDMA3_DEC_START', - 'mmSDMA3_DEC_START_BASE_IDX', 'mmSDMA3_EA_DBIT_ADDR_DATA', - 'mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX', - 'mmSDMA3_EA_DBIT_ADDR_INDEX', - 'mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA3_EDC_CONFIG', - 'mmSDMA3_EDC_CONFIG_BASE_IDX', 'mmSDMA3_EDC_COUNTER', - 'mmSDMA3_EDC_COUNTER_BASE_IDX', 'mmSDMA3_EDC_COUNTER_CLEAR', - 'mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA3_ERROR_LOG', - 'mmSDMA3_ERROR_LOG_BASE_IDX', 'mmSDMA3_F32_CNTL', - 'mmSDMA3_F32_CNTL_BASE_IDX', 'mmSDMA3_F32_COUNTER', - 'mmSDMA3_F32_COUNTER_BASE_IDX', 'mmSDMA3_FREEZE', - 'mmSDMA3_FREEZE_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG', - 'mmSDMA3_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG_READ', - 'mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX', - 'mmSDMA3_GFX_CONTEXT_CNTL', 'mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX', - 'mmSDMA3_GFX_CONTEXT_STATUS', - 'mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_HI', - 'mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_LO', - 'mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA3_GFX_DOORBELL', - 'mmSDMA3_GFX_DOORBELL_BASE_IDX', 'mmSDMA3_GFX_DOORBELL_LOG', - 'mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_GFX_DOORBELL_OFFSET', - 'mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_GFX_DUMMY_REG', - 'mmSDMA3_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_HI', - 'mmSDMA3_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_LO', - 'mmSDMA3_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA3_GFX_IB_CNTL', - 'mmSDMA3_GFX_IB_CNTL_BASE_IDX', 'mmSDMA3_GFX_IB_OFFSET', - 'mmSDMA3_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA3_GFX_IB_RPTR', - 'mmSDMA3_GFX_IB_RPTR_BASE_IDX', 'mmSDMA3_GFX_IB_SIZE', - 'mmSDMA3_GFX_IB_SIZE_BASE_IDX', 'mmSDMA3_GFX_IB_SUB_REMAIN', - 'mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_CNTL', - 'mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA0', - 'mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA1', - 'mmSDMA3_GFX_MIDCMD_DATA10', 'mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA2', - 'mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA3', - 'mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA4', - 'mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA5', - 'mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA6', - 'mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA7', - 'mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA8', - 'mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA9', - 'mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_GFX_MINOR_PTR_UPDATE', - 'mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_GFX_PREEMPT', - 'mmSDMA3_GFX_PREEMPT_BASE_IDX', 'mmSDMA3_GFX_RB_AQL_CNTL', - 'mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_BASE', - 'mmSDMA3_GFX_RB_BASE_BASE_IDX', 'mmSDMA3_GFX_RB_BASE_HI', - 'mmSDMA3_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_RB_CNTL', - 'mmSDMA3_GFX_RB_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR', - 'mmSDMA3_GFX_RB_RPTR_ADDR_HI', - 'mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_GFX_RB_RPTR_ADDR_LO', - 'mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_GFX_RB_RPTR_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR_HI', - 'mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR', - 'mmSDMA3_GFX_RB_WPTR_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR_HI', - 'mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_GFX_RB_WPTR_POLL_CNTL', - 'mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA3_GFX_SKIP_CNTL', - 'mmSDMA3_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA3_GFX_STATUS', - 'mmSDMA3_GFX_STATUS_BASE_IDX', 'mmSDMA3_GFX_WATERMARK', - 'mmSDMA3_GFX_WATERMARK_BASE_IDX', 'mmSDMA3_GLOBAL_TIMESTAMP_HI', - 'mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'mmSDMA3_GLOBAL_TIMESTAMP_LO', - 'mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA3_HBM_PAGE_CONFIG', - 'mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA3_HOLE_ADDR_HI', - 'mmSDMA3_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA3_HOLE_ADDR_LO', - 'mmSDMA3_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA3_IB_OFFSET_FETCH', - 'mmSDMA3_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA3_ID', - 'mmSDMA3_ID_BASE_IDX', 'mmSDMA3_INT_STATUS', - 'mmSDMA3_INT_STATUS_BASE_IDX', 'mmSDMA3_PAGE_CONTEXT_STATUS', - 'mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_PAGE_CSA_ADDR_HI', 'mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_PAGE_CSA_ADDR_LO', 'mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_PAGE_DOORBELL', 'mmSDMA3_PAGE_DOORBELL_BASE_IDX', - 'mmSDMA3_PAGE_DOORBELL_LOG', 'mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_PAGE_DOORBELL_OFFSET', - 'mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_DUMMY_REG', - 'mmSDMA3_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_HI', - 'mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_LO', - 'mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA3_PAGE_IB_CNTL', - 'mmSDMA3_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_IB_OFFSET', - 'mmSDMA3_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_IB_RPTR', - 'mmSDMA3_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_IB_SIZE', - 'mmSDMA3_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA3_PAGE_IB_SUB_REMAIN', - 'mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_CNTL', - 'mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA0', - 'mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA1', - 'mmSDMA3_PAGE_MIDCMD_DATA10', - 'mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA2', - 'mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA3', - 'mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA4', - 'mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA5', - 'mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA6', - 'mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA7', - 'mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA8', - 'mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA9', - 'mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_PAGE_MINOR_PTR_UPDATE', - 'mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_PAGE_PREEMPT', - 'mmSDMA3_PAGE_PREEMPT_BASE_IDX', 'mmSDMA3_PAGE_RB_AQL_CNTL', - 'mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE', - 'mmSDMA3_PAGE_RB_BASE_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE_HI', - 'mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_CNTL', - 'mmSDMA3_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR', - 'mmSDMA3_PAGE_RB_RPTR_ADDR_HI', - 'mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_PAGE_RB_RPTR_ADDR_LO', - 'mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR_HI', - 'mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR', - 'mmSDMA3_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR_HI', - 'mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL', - 'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_PAGE_SKIP_CNTL', 'mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_PAGE_STATUS', 'mmSDMA3_PAGE_STATUS_BASE_IDX', - 'mmSDMA3_PAGE_WATERMARK', 'mmSDMA3_PAGE_WATERMARK_BASE_IDX', - 'mmSDMA3_PERFCNT_MISC_CNTL', 'mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX', - 'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG', - 'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG', - 'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'mmSDMA3_PERFCNT_PERFCOUNTER_HI', - 'mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'mmSDMA3_PERFCNT_PERFCOUNTER_LO', - 'mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'mmSDMA3_PERFCOUNTER0_HI', 'mmSDMA3_PERFCOUNTER0_HI_BASE_IDX', - 'mmSDMA3_PERFCOUNTER0_LO', 'mmSDMA3_PERFCOUNTER0_LO_BASE_IDX', - 'mmSDMA3_PERFCOUNTER0_SELECT', 'mmSDMA3_PERFCOUNTER0_SELECT1', - 'mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_HI', - 'mmSDMA3_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_LO', - 'mmSDMA3_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_SELECT', - 'mmSDMA3_PERFCOUNTER1_SELECT1', - 'mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA3_PG_CNTL', - 'mmSDMA3_PG_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_CNTL', - 'mmSDMA3_PG_CTX_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_HI', - 'mmSDMA3_PG_CTX_HI_BASE_IDX', 'mmSDMA3_PG_CTX_LO', - 'mmSDMA3_PG_CTX_LO_BASE_IDX', 'mmSDMA3_PHASE0_QUANTUM', - 'mmSDMA3_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE1_QUANTUM', - 'mmSDMA3_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE2_QUANTUM', - 'mmSDMA3_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_HI', - 'mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_LO', - 'mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA3_POWER_CNTL', - 'mmSDMA3_POWER_CNTL_BASE_IDX', 'mmSDMA3_PROGRAM', - 'mmSDMA3_PROGRAM_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG0', - 'mmSDMA3_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG1', - 'mmSDMA3_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG2', - 'mmSDMA3_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG3', - 'mmSDMA3_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE0', - 'mmSDMA3_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE1', - 'mmSDMA3_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE2', - 'mmSDMA3_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE3', - 'mmSDMA3_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA3_QUEUE_RESET_REQ', - 'mmSDMA3_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH', - 'mmSDMA3_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH_HI', - 'mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA3_RD_BURST_CNTL', - 'mmSDMA3_RD_BURST_CNTL_BASE_IDX', 'mmSDMA3_RELAX_ORDERING_LUT', - 'mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX', - 'mmSDMA3_RLC0_CONTEXT_STATUS', - 'mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC0_CSA_ADDR_HI', 'mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC0_CSA_ADDR_LO', 'mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC0_DOORBELL', 'mmSDMA3_RLC0_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC0_DOORBELL_LOG', 'mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC0_DOORBELL_OFFSET', - 'mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_DUMMY_REG', - 'mmSDMA3_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_HI', - 'mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_LO', - 'mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC0_IB_CNTL', - 'mmSDMA3_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_IB_OFFSET', - 'mmSDMA3_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_IB_RPTR', - 'mmSDMA3_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_IB_SIZE', - 'mmSDMA3_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC0_IB_SUB_REMAIN', - 'mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_CNTL', - 'mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA0', - 'mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA1', - 'mmSDMA3_RLC0_MIDCMD_DATA10', - 'mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA2', - 'mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA3', - 'mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA4', - 'mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA5', - 'mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA6', - 'mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA7', - 'mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA8', - 'mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA9', - 'mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC0_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC0_PREEMPT', - 'mmSDMA3_RLC0_PREEMPT_BASE_IDX', 'mmSDMA3_RLC0_RB_AQL_CNTL', - 'mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE', - 'mmSDMA3_RLC0_RB_BASE_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE_HI', - 'mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_CNTL', - 'mmSDMA3_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR', - 'mmSDMA3_RLC0_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC0_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR_HI', - 'mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR', - 'mmSDMA3_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR_HI', - 'mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC0_SKIP_CNTL', 'mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC0_STATUS', 'mmSDMA3_RLC0_STATUS_BASE_IDX', - 'mmSDMA3_RLC0_WATERMARK', 'mmSDMA3_RLC0_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC1_CONTEXT_STATUS', - 'mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC1_CSA_ADDR_HI', 'mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC1_CSA_ADDR_LO', 'mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC1_DOORBELL', 'mmSDMA3_RLC1_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC1_DOORBELL_LOG', 'mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC1_DOORBELL_OFFSET', - 'mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_DUMMY_REG', - 'mmSDMA3_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_HI', - 'mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_LO', - 'mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC1_IB_CNTL', - 'mmSDMA3_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_IB_OFFSET', - 'mmSDMA3_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_IB_RPTR', - 'mmSDMA3_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_IB_SIZE', - 'mmSDMA3_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC1_IB_SUB_REMAIN', - 'mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_CNTL', - 'mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA0', - 'mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA1', - 'mmSDMA3_RLC1_MIDCMD_DATA10', - 'mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA2', - 'mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA3', - 'mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA4', - 'mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA5', - 'mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA6', - 'mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA7', - 'mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA8', - 'mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA9', - 'mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC1_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC1_PREEMPT', - 'mmSDMA3_RLC1_PREEMPT_BASE_IDX', 'mmSDMA3_RLC1_RB_AQL_CNTL', - 'mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE', - 'mmSDMA3_RLC1_RB_BASE_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE_HI', - 'mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_CNTL', - 'mmSDMA3_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR', - 'mmSDMA3_RLC1_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC1_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR_HI', - 'mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR', - 'mmSDMA3_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR_HI', - 'mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC1_SKIP_CNTL', 'mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC1_STATUS', 'mmSDMA3_RLC1_STATUS_BASE_IDX', - 'mmSDMA3_RLC1_WATERMARK', 'mmSDMA3_RLC1_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC2_CONTEXT_STATUS', - 'mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC2_CSA_ADDR_HI', 'mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC2_CSA_ADDR_LO', 'mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC2_DOORBELL', 'mmSDMA3_RLC2_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC2_DOORBELL_LOG', 'mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC2_DOORBELL_OFFSET', - 'mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_DUMMY_REG', - 'mmSDMA3_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_HI', - 'mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_LO', - 'mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC2_IB_CNTL', - 'mmSDMA3_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_IB_OFFSET', - 'mmSDMA3_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_IB_RPTR', - 'mmSDMA3_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_IB_SIZE', - 'mmSDMA3_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC2_IB_SUB_REMAIN', - 'mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_CNTL', - 'mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA0', - 'mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA1', - 'mmSDMA3_RLC2_MIDCMD_DATA10', - 'mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA2', - 'mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA3', - 'mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA4', - 'mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA5', - 'mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA6', - 'mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA7', - 'mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA8', - 'mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA9', - 'mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC2_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC2_PREEMPT', - 'mmSDMA3_RLC2_PREEMPT_BASE_IDX', 'mmSDMA3_RLC2_RB_AQL_CNTL', - 'mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE', - 'mmSDMA3_RLC2_RB_BASE_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE_HI', - 'mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_CNTL', - 'mmSDMA3_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR', - 'mmSDMA3_RLC2_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC2_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR_HI', - 'mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR', - 'mmSDMA3_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR_HI', - 'mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC2_SKIP_CNTL', 'mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC2_STATUS', 'mmSDMA3_RLC2_STATUS_BASE_IDX', - 'mmSDMA3_RLC2_WATERMARK', 'mmSDMA3_RLC2_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC3_CONTEXT_STATUS', - 'mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC3_CSA_ADDR_HI', 'mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC3_CSA_ADDR_LO', 'mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC3_DOORBELL', 'mmSDMA3_RLC3_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC3_DOORBELL_LOG', 'mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC3_DOORBELL_OFFSET', - 'mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_DUMMY_REG', - 'mmSDMA3_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_HI', - 'mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_LO', - 'mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC3_IB_CNTL', - 'mmSDMA3_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_IB_OFFSET', - 'mmSDMA3_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_IB_RPTR', - 'mmSDMA3_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_IB_SIZE', - 'mmSDMA3_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC3_IB_SUB_REMAIN', - 'mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_CNTL', - 'mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA0', - 'mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA1', - 'mmSDMA3_RLC3_MIDCMD_DATA10', - 'mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA2', - 'mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA3', - 'mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA4', - 'mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA5', - 'mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA6', - 'mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA7', - 'mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA8', - 'mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA9', - 'mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC3_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC3_PREEMPT', - 'mmSDMA3_RLC3_PREEMPT_BASE_IDX', 'mmSDMA3_RLC3_RB_AQL_CNTL', - 'mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE', - 'mmSDMA3_RLC3_RB_BASE_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE_HI', - 'mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_CNTL', - 'mmSDMA3_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR', - 'mmSDMA3_RLC3_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC3_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR_HI', - 'mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR', - 'mmSDMA3_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR_HI', - 'mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC3_SKIP_CNTL', 'mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC3_STATUS', 'mmSDMA3_RLC3_STATUS_BASE_IDX', - 'mmSDMA3_RLC3_WATERMARK', 'mmSDMA3_RLC3_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC4_CONTEXT_STATUS', - 'mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC4_CSA_ADDR_HI', 'mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC4_CSA_ADDR_LO', 'mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC4_DOORBELL', 'mmSDMA3_RLC4_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC4_DOORBELL_LOG', 'mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC4_DOORBELL_OFFSET', - 'mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_DUMMY_REG', - 'mmSDMA3_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_HI', - 'mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_LO', - 'mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC4_IB_CNTL', - 'mmSDMA3_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_IB_OFFSET', - 'mmSDMA3_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_IB_RPTR', - 'mmSDMA3_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_IB_SIZE', - 'mmSDMA3_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC4_IB_SUB_REMAIN', - 'mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_CNTL', - 'mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA0', - 'mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA1', - 'mmSDMA3_RLC4_MIDCMD_DATA10', - 'mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA2', - 'mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA3', - 'mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA4', - 'mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA5', - 'mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA6', - 'mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA7', - 'mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA8', - 'mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA9', - 'mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC4_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC4_PREEMPT', - 'mmSDMA3_RLC4_PREEMPT_BASE_IDX', 'mmSDMA3_RLC4_RB_AQL_CNTL', - 'mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE', - 'mmSDMA3_RLC4_RB_BASE_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE_HI', - 'mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_CNTL', - 'mmSDMA3_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR', - 'mmSDMA3_RLC4_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC4_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR_HI', - 'mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR', - 'mmSDMA3_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR_HI', - 'mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC4_SKIP_CNTL', 'mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC4_STATUS', 'mmSDMA3_RLC4_STATUS_BASE_IDX', - 'mmSDMA3_RLC4_WATERMARK', 'mmSDMA3_RLC4_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC5_CONTEXT_STATUS', - 'mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC5_CSA_ADDR_HI', 'mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC5_CSA_ADDR_LO', 'mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC5_DOORBELL', 'mmSDMA3_RLC5_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC5_DOORBELL_LOG', 'mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC5_DOORBELL_OFFSET', - 'mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_DUMMY_REG', - 'mmSDMA3_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_HI', - 'mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_LO', - 'mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC5_IB_CNTL', - 'mmSDMA3_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_IB_OFFSET', - 'mmSDMA3_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_IB_RPTR', - 'mmSDMA3_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_IB_SIZE', - 'mmSDMA3_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC5_IB_SUB_REMAIN', - 'mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_CNTL', - 'mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA0', - 'mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA1', - 'mmSDMA3_RLC5_MIDCMD_DATA10', - 'mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA2', - 'mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA3', - 'mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA4', - 'mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA5', - 'mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA6', - 'mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA7', - 'mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA8', - 'mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA9', - 'mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC5_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC5_PREEMPT', - 'mmSDMA3_RLC5_PREEMPT_BASE_IDX', 'mmSDMA3_RLC5_RB_AQL_CNTL', - 'mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE', - 'mmSDMA3_RLC5_RB_BASE_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE_HI', - 'mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_CNTL', - 'mmSDMA3_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR', - 'mmSDMA3_RLC5_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC5_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR_HI', - 'mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR', - 'mmSDMA3_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR_HI', - 'mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC5_SKIP_CNTL', 'mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC5_STATUS', 'mmSDMA3_RLC5_STATUS_BASE_IDX', - 'mmSDMA3_RLC5_WATERMARK', 'mmSDMA3_RLC5_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC6_CONTEXT_STATUS', - 'mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC6_CSA_ADDR_HI', 'mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC6_CSA_ADDR_LO', 'mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC6_DOORBELL', 'mmSDMA3_RLC6_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC6_DOORBELL_LOG', 'mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC6_DOORBELL_OFFSET', - 'mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_DUMMY_REG', - 'mmSDMA3_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_HI', - 'mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_LO', - 'mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC6_IB_CNTL', - 'mmSDMA3_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_IB_OFFSET', - 'mmSDMA3_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_IB_RPTR', - 'mmSDMA3_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_IB_SIZE', - 'mmSDMA3_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC6_IB_SUB_REMAIN', - 'mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_CNTL', - 'mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA0', - 'mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA1', - 'mmSDMA3_RLC6_MIDCMD_DATA10', - 'mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA2', - 'mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA3', - 'mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA4', - 'mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA5', - 'mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA6', - 'mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA7', - 'mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA8', - 'mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA9', - 'mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC6_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC6_PREEMPT', - 'mmSDMA3_RLC6_PREEMPT_BASE_IDX', 'mmSDMA3_RLC6_RB_AQL_CNTL', - 'mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE', - 'mmSDMA3_RLC6_RB_BASE_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE_HI', - 'mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_CNTL', - 'mmSDMA3_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR', - 'mmSDMA3_RLC6_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC6_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR_HI', - 'mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR', - 'mmSDMA3_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR_HI', - 'mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC6_SKIP_CNTL', 'mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC6_STATUS', 'mmSDMA3_RLC6_STATUS_BASE_IDX', - 'mmSDMA3_RLC6_WATERMARK', 'mmSDMA3_RLC6_WATERMARK_BASE_IDX', - 'mmSDMA3_RLC7_CONTEXT_STATUS', - 'mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX', - 'mmSDMA3_RLC7_CSA_ADDR_HI', 'mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC7_CSA_ADDR_LO', 'mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC7_DOORBELL', 'mmSDMA3_RLC7_DOORBELL_BASE_IDX', - 'mmSDMA3_RLC7_DOORBELL_LOG', 'mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX', - 'mmSDMA3_RLC7_DOORBELL_OFFSET', - 'mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_DUMMY_REG', - 'mmSDMA3_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_HI', - 'mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_LO', - 'mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC7_IB_CNTL', - 'mmSDMA3_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_IB_OFFSET', - 'mmSDMA3_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_IB_RPTR', - 'mmSDMA3_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_IB_SIZE', - 'mmSDMA3_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC7_IB_SUB_REMAIN', - 'mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_CNTL', - 'mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA0', - 'mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA1', - 'mmSDMA3_RLC7_MIDCMD_DATA10', - 'mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX', - 'mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA2', - 'mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA3', - 'mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA4', - 'mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA5', - 'mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA6', - 'mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA7', - 'mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA8', - 'mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA9', - 'mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX', - 'mmSDMA3_RLC7_MINOR_PTR_UPDATE', - 'mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC7_PREEMPT', - 'mmSDMA3_RLC7_PREEMPT_BASE_IDX', 'mmSDMA3_RLC7_RB_AQL_CNTL', - 'mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE', - 'mmSDMA3_RLC7_RB_BASE_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE_HI', - 'mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_CNTL', - 'mmSDMA3_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR', - 'mmSDMA3_RLC7_RB_RPTR_ADDR_HI', - 'mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC7_RB_RPTR_ADDR_LO', - 'mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR_HI', - 'mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR', - 'mmSDMA3_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR_HI', - 'mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX', - 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI', - 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO', - 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL', - 'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', - 'mmSDMA3_RLC7_SKIP_CNTL', 'mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX', - 'mmSDMA3_RLC7_STATUS', 'mmSDMA3_RLC7_STATUS_BASE_IDX', - 'mmSDMA3_RLC7_WATERMARK', 'mmSDMA3_RLC7_WATERMARK_BASE_IDX', - 'mmSDMA3_SCRATCH_RAM_ADDR', 'mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX', - 'mmSDMA3_SCRATCH_RAM_DATA', 'mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX', - 'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL', - 'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'mmSDMA3_STATUS1_REG', 'mmSDMA3_STATUS1_REG_BASE_IDX', - 'mmSDMA3_STATUS2_REG', 'mmSDMA3_STATUS2_REG_BASE_IDX', - 'mmSDMA3_STATUS3_REG', 'mmSDMA3_STATUS3_REG_BASE_IDX', - 'mmSDMA3_STATUS4_REG', 'mmSDMA3_STATUS4_REG_BASE_IDX', - 'mmSDMA3_STATUS5_REG', 'mmSDMA3_STATUS5_REG_BASE_IDX', - 'mmSDMA3_STATUS_REG', 'mmSDMA3_STATUS_REG_BASE_IDX', - 'mmSDMA3_TILING_CONFIG', 'mmSDMA3_TILING_CONFIG_BASE_IDX', - 'mmSDMA3_TIMESTAMP_CNTL', 'mmSDMA3_TIMESTAMP_CNTL_BASE_IDX', - 'mmSDMA3_TLBI_GCR_CNTL', 'mmSDMA3_TLBI_GCR_CNTL_BASE_IDX', - 'mmSDMA3_UCODE_ADDR', 'mmSDMA3_UCODE_ADDR_BASE_IDX', - 'mmSDMA3_UCODE_CHECKSUM', 'mmSDMA3_UCODE_CHECKSUM_BASE_IDX', - 'mmSDMA3_UCODE_DATA', 'mmSDMA3_UCODE_DATA_BASE_IDX', - 'mmSDMA3_UTCL1_CNTL', 'mmSDMA3_UTCL1_CNTL_BASE_IDX', - 'mmSDMA3_UTCL1_INV0', 'mmSDMA3_UTCL1_INV0_BASE_IDX', - 'mmSDMA3_UTCL1_INV1', 'mmSDMA3_UTCL1_INV1_BASE_IDX', - 'mmSDMA3_UTCL1_INV2', 'mmSDMA3_UTCL1_INV2_BASE_IDX', - 'mmSDMA3_UTCL1_PAGE', 'mmSDMA3_UTCL1_PAGE_BASE_IDX', - 'mmSDMA3_UTCL1_RD_STATUS', 'mmSDMA3_UTCL1_RD_STATUS_BASE_IDX', - 'mmSDMA3_UTCL1_RD_XNACK0', 'mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX', - 'mmSDMA3_UTCL1_RD_XNACK1', 'mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX', - 'mmSDMA3_UTCL1_TIMEOUT', 'mmSDMA3_UTCL1_TIMEOUT_BASE_IDX', - 'mmSDMA3_UTCL1_WATERMK', 'mmSDMA3_UTCL1_WATERMK_BASE_IDX', - 'mmSDMA3_UTCL1_WR_STATUS', 'mmSDMA3_UTCL1_WR_STATUS_BASE_IDX', - 'mmSDMA3_UTCL1_WR_XNACK0', 'mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX', - 'mmSDMA3_UTCL1_WR_XNACK1', 'mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX', - 'mmSDMA3_VERSION', 'mmSDMA3_VERSION_BASE_IDX', - 'mmSDMA3_VF_ENABLE', 'mmSDMA3_VF_ENABLE_BASE_IDX', - 'mmSDMA3_VIRT_RESET_REQ', 'mmSDMA3_VIRT_RESET_REQ_BASE_IDX', - 'mmSDMA3_VM_CNTL', 'mmSDMA3_VM_CNTL_BASE_IDX', - 'mmSDMA3_VM_CTX_CNTL', 'mmSDMA3_VM_CTX_CNTL_BASE_IDX', - 'mmSDMA3_VM_CTX_HI', 'mmSDMA3_VM_CTX_HI_BASE_IDX', - 'mmSDMA3_VM_CTX_LO', 'mmSDMA3_VM_CTX_LO_BASE_IDX', - 'mmSE_CAC_CGTT_CLK_CTRL', 'mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX', - 'mmSE_CAC_IND_DATA', 'mmSE_CAC_IND_DATA_BASE_IDX', - 'mmSE_CAC_IND_INDEX', 'mmSE_CAC_IND_INDEX_BASE_IDX', - 'mmSH_MEM_BASES', 'mmSH_MEM_BASES_BASE_IDX', 'mmSH_MEM_CONFIG', - 'mmSH_MEM_CONFIG_BASE_IDX', 'mmSH_RESERVED_REG0', - 'mmSH_RESERVED_REG0_BASE_IDX', 'mmSH_RESERVED_REG1', - 'mmSH_RESERVED_REG1_BASE_IDX', 'mmSMU_RLC_RESPONSE', - 'mmSMU_RLC_RESPONSE_BASE_IDX', 'mmSPI_ARB_CNTL_0', - 'mmSPI_ARB_CNTL_0_BASE_IDX', 'mmSPI_ARB_CYCLES_0', - 'mmSPI_ARB_CYCLES_0_BASE_IDX', 'mmSPI_ARB_CYCLES_1', - 'mmSPI_ARB_CYCLES_1_BASE_IDX', 'mmSPI_ARB_PRIORITY', - 'mmSPI_ARB_PRIORITY_BASE_IDX', 'mmSPI_BARYC_CNTL', - 'mmSPI_BARYC_CNTL_BASE_IDX', 'mmSPI_COMPUTE_QUEUE_RESET', - 'mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX', 'mmSPI_COMPUTE_WF_CTX_SAVE', - 'mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', 'mmSPI_CONFIG_CNTL', - 'mmSPI_CONFIG_CNTL_1', 'mmSPI_CONFIG_CNTL_1_BASE_IDX', - 'mmSPI_CONFIG_CNTL_1_REMAP', 'mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX', - 'mmSPI_CONFIG_CNTL_2', 'mmSPI_CONFIG_CNTL_2_BASE_IDX', - 'mmSPI_CONFIG_CNTL_2_REMAP', 'mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX', - 'mmSPI_CONFIG_CNTL_BASE_IDX', 'mmSPI_CONFIG_CNTL_REMAP', - 'mmSPI_CONFIG_CNTL_REMAP_BASE_IDX', 'mmSPI_CONFIG_PS_CU_EN', - 'mmSPI_CONFIG_PS_CU_EN_BASE_IDX', 'mmSPI_CSQ_WF_ACTIVE_COUNT_0', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_1', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_2', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_3', - 'mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', - 'mmSPI_CSQ_WF_ACTIVE_STATUS', - 'mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'mmSPI_DSM_CNTL', - 'mmSPI_DSM_CNTL2', 'mmSPI_DSM_CNTL2_BASE_IDX', - 'mmSPI_DSM_CNTL_BASE_IDX', 'mmSPI_EDC_CNT', - 'mmSPI_EDC_CNT_BASE_IDX', 'mmSPI_EXP_THROTTLE_CTRL', - 'mmSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'mmSPI_FEATURE_CTRL', - 'mmSPI_FEATURE_CTRL_BASE_IDX', 'mmSPI_GDBG_TRAP_CONFIG', - 'mmSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA0', - 'mmSPI_GDBG_TRAP_DATA0_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA1', - 'mmSPI_GDBG_TRAP_DATA1_BASE_IDX', 'mmSPI_GDBG_TRAP_MASK', - 'mmSPI_GDBG_TRAP_MASK_BASE_IDX', 'mmSPI_GDBG_WAVE_CNTL', - 'mmSPI_GDBG_WAVE_CNTL2', 'mmSPI_GDBG_WAVE_CNTL2_BASE_IDX', - 'mmSPI_GDBG_WAVE_CNTL3', 'mmSPI_GDBG_WAVE_CNTL3_BASE_IDX', - 'mmSPI_GDBG_WAVE_CNTL_BASE_IDX', 'mmSPI_GDS_CREDITS', - 'mmSPI_GDS_CREDITS_BASE_IDX', 'mmSPI_GFX_CNTL', - 'mmSPI_GFX_CNTL_BASE_IDX', 'mmSPI_INTERP_CONTROL_0', - 'mmSPI_INTERP_CONTROL_0_BASE_IDX', 'mmSPI_LB_CTR_CTRL', - 'mmSPI_LB_CTR_CTRL_BASE_IDX', 'mmSPI_LB_DATA_PERWGP_WAVE_CS', - 'mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX', - 'mmSPI_LB_DATA_PERWGP_WAVE_HSGS', - 'mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX', - 'mmSPI_LB_DATA_PERWGP_WAVE_VSPS', - 'mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX', 'mmSPI_LB_DATA_REG', - 'mmSPI_LB_DATA_REG_BASE_IDX', 'mmSPI_LB_DATA_WAVES', - 'mmSPI_LB_DATA_WAVES_BASE_IDX', 'mmSPI_LB_WGP_MASK', - 'mmSPI_LB_WGP_MASK_BASE_IDX', 'mmSPI_P0_TRAP_SCREEN_GPR_MIN', - 'mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'mmSPI_P0_TRAP_SCREEN_PSBA_HI', - 'mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'mmSPI_P0_TRAP_SCREEN_PSBA_LO', - 'mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'mmSPI_P0_TRAP_SCREEN_PSMA_HI', - 'mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'mmSPI_P0_TRAP_SCREEN_PSMA_LO', - 'mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', - 'mmSPI_P1_TRAP_SCREEN_GPR_MIN', - 'mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'mmSPI_P1_TRAP_SCREEN_PSBA_HI', - 'mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'mmSPI_P1_TRAP_SCREEN_PSBA_LO', - 'mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'mmSPI_P1_TRAP_SCREEN_PSMA_HI', - 'mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'mmSPI_P1_TRAP_SCREEN_PSMA_LO', - 'mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_HI', - 'mmSPI_PERFCOUNTER0_HI_BASE_IDX', 'mmSPI_PERFCOUNTER0_LO', - 'mmSPI_PERFCOUNTER0_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_SELECT', - 'mmSPI_PERFCOUNTER0_SELECT1', - 'mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER1_HI', - 'mmSPI_PERFCOUNTER1_HI_BASE_IDX', 'mmSPI_PERFCOUNTER1_LO', - 'mmSPI_PERFCOUNTER1_LO_BASE_IDX', 'mmSPI_PERFCOUNTER1_SELECT', - 'mmSPI_PERFCOUNTER1_SELECT1', - 'mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER2_HI', - 'mmSPI_PERFCOUNTER2_HI_BASE_IDX', 'mmSPI_PERFCOUNTER2_LO', - 'mmSPI_PERFCOUNTER2_LO_BASE_IDX', 'mmSPI_PERFCOUNTER2_SELECT', - 'mmSPI_PERFCOUNTER2_SELECT1', - 'mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'mmSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER3_HI', - 'mmSPI_PERFCOUNTER3_HI_BASE_IDX', 'mmSPI_PERFCOUNTER3_LO', - 'mmSPI_PERFCOUNTER3_LO_BASE_IDX', 'mmSPI_PERFCOUNTER3_SELECT', - 'mmSPI_PERFCOUNTER3_SELECT1', - 'mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX', - 'mmSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER4_HI', - 'mmSPI_PERFCOUNTER4_HI_BASE_IDX', 'mmSPI_PERFCOUNTER4_LO', - 'mmSPI_PERFCOUNTER4_LO_BASE_IDX', 'mmSPI_PERFCOUNTER4_SELECT', - 'mmSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER5_HI', - 'mmSPI_PERFCOUNTER5_HI_BASE_IDX', 'mmSPI_PERFCOUNTER5_LO', - 'mmSPI_PERFCOUNTER5_LO_BASE_IDX', 'mmSPI_PERFCOUNTER5_SELECT', - 'mmSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER_BINS', - 'mmSPI_PERFCOUNTER_BINS_BASE_IDX', - 'mmSPI_PG_ENABLE_STATIC_WGP_MASK', - 'mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'mmSPI_PQEV_CTRL', - 'mmSPI_PQEV_CTRL_BASE_IDX', 'mmSPI_PS_INPUT_ADDR', - 'mmSPI_PS_INPUT_ADDR_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_0', - 'mmSPI_PS_INPUT_CNTL_0_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_1', - 'mmSPI_PS_INPUT_CNTL_10', 'mmSPI_PS_INPUT_CNTL_10_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_11', 'mmSPI_PS_INPUT_CNTL_11_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_12', 'mmSPI_PS_INPUT_CNTL_12_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_13', 'mmSPI_PS_INPUT_CNTL_13_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_14', 'mmSPI_PS_INPUT_CNTL_14_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_15', 'mmSPI_PS_INPUT_CNTL_15_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_16', 'mmSPI_PS_INPUT_CNTL_16_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_17', 'mmSPI_PS_INPUT_CNTL_17_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_18', 'mmSPI_PS_INPUT_CNTL_18_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_19', 'mmSPI_PS_INPUT_CNTL_19_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_1_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_2', - 'mmSPI_PS_INPUT_CNTL_20', 'mmSPI_PS_INPUT_CNTL_20_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_21', 'mmSPI_PS_INPUT_CNTL_21_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_22', 'mmSPI_PS_INPUT_CNTL_22_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_23', 'mmSPI_PS_INPUT_CNTL_23_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_24', 'mmSPI_PS_INPUT_CNTL_24_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_25', 'mmSPI_PS_INPUT_CNTL_25_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_26', 'mmSPI_PS_INPUT_CNTL_26_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_27', 'mmSPI_PS_INPUT_CNTL_27_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_28', 'mmSPI_PS_INPUT_CNTL_28_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_29', 'mmSPI_PS_INPUT_CNTL_29_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_2_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_3', - 'mmSPI_PS_INPUT_CNTL_30', 'mmSPI_PS_INPUT_CNTL_30_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_31', 'mmSPI_PS_INPUT_CNTL_31_BASE_IDX', - 'mmSPI_PS_INPUT_CNTL_3_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_4', - 'mmSPI_PS_INPUT_CNTL_4_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_5', - 'mmSPI_PS_INPUT_CNTL_5_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_6', - 'mmSPI_PS_INPUT_CNTL_6_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_7', - 'mmSPI_PS_INPUT_CNTL_7_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_8', - 'mmSPI_PS_INPUT_CNTL_8_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_9', - 'mmSPI_PS_INPUT_CNTL_9_BASE_IDX', 'mmSPI_PS_INPUT_ENA', - 'mmSPI_PS_INPUT_ENA_BASE_IDX', 'mmSPI_PS_IN_CONTROL', - 'mmSPI_PS_IN_CONTROL_BASE_IDX', 'mmSPI_PS_MAX_WAVE_ID', - 'mmSPI_PS_MAX_WAVE_ID_BASE_IDX', 'mmSPI_RESOURCE_RESERVE_CU_0', - 'mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_1', - 'mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_2', - 'mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_3', - 'mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_4', - 'mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_5', - 'mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_6', - 'mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_7', - 'mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_8', - 'mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_CU_9', - 'mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_0', - 'mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_1', - 'mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_2', - 'mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_3', - 'mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_4', - 'mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_5', - 'mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_6', - 'mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_7', - 'mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_8', - 'mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', - 'mmSPI_RESOURCE_RESERVE_EN_CU_9', - 'mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', - 'mmSPI_SHADER_COL_FORMAT', 'mmSPI_SHADER_COL_FORMAT_BASE_IDX', - 'mmSPI_SHADER_IDX_FORMAT', 'mmSPI_SHADER_IDX_FORMAT_BASE_IDX', - 'mmSPI_SHADER_LATE_ALLOC_VS', - 'mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX', - 'mmSPI_SHADER_PGM_CHKSUM_GS', - 'mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX', - 'mmSPI_SHADER_PGM_CHKSUM_HS', - 'mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX', - 'mmSPI_SHADER_PGM_CHKSUM_PS', - 'mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', - 'mmSPI_SHADER_PGM_CHKSUM_VS', - 'mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES', - 'mmSPI_SHADER_PGM_HI_ES_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES_GS', - 'mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_GS', - 'mmSPI_SHADER_PGM_HI_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_HS', - 'mmSPI_SHADER_PGM_HI_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS', - 'mmSPI_SHADER_PGM_HI_LS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS_HS', - 'mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_PS', - 'mmSPI_SHADER_PGM_HI_PS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_VS', - 'mmSPI_SHADER_PGM_HI_VS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES', - 'mmSPI_SHADER_PGM_LO_ES_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES_GS', - 'mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_GS', - 'mmSPI_SHADER_PGM_LO_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_HS', - 'mmSPI_SHADER_PGM_LO_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS', - 'mmSPI_SHADER_PGM_LO_LS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS_HS', - 'mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_PS', - 'mmSPI_SHADER_PGM_LO_PS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_VS', - 'mmSPI_SHADER_PGM_LO_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_GS', - 'mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_HS', - 'mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_PS', - 'mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_VS', - 'mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC2_GS', - 'mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC2_GS_VS', - 'mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC2_HS', 'mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC2_PS', 'mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC2_VS', 'mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC3_GS', 'mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC3_HS', 'mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC3_PS', 'mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC3_VS', 'mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC4_GS', 'mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC4_HS', 'mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC4_PS', 'mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', - 'mmSPI_SHADER_PGM_RSRC4_VS', 'mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX', - 'mmSPI_SHADER_POS_FORMAT', 'mmSPI_SHADER_POS_FORMAT_BASE_IDX', - 'mmSPI_SHADER_REQ_CTRL_ESGS', - 'mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX', - 'mmSPI_SHADER_REQ_CTRL_LSHS', - 'mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_PS', - 'mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_VS', - 'mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX', - 'mmSPI_SHADER_RSRC_LIMIT_CTRL', - 'mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_ESGS_0', - 'mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_ESGS_1', - 'mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_ESGS_2', - 'mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_ESGS_3', - 'mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_LSHS_0', - 'mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_LSHS_1', - 'mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_LSHS_2', - 'mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_LSHS_3', - 'mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_PS_0', - 'mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_PS_1', - 'mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_PS_2', - 'mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_PS_3', - 'mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_VS_0', - 'mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_VS_1', - 'mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_VS_2', - 'mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX', - 'mmSPI_SHADER_USER_ACCUM_VS_3', - 'mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_ADDR_HI_GS', - 'mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_ADDR_HI_HS', - 'mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_ADDR_LO_GS', - 'mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_ADDR_LO_HS', - 'mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_0', - 'mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_1', 'mmSPI_SHADER_USER_DATA_GS_10', - 'mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_11', - 'mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_12', - 'mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_13', - 'mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_14', - 'mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_15', - 'mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_16', - 'mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_17', - 'mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_18', - 'mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_19', - 'mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_2', 'mmSPI_SHADER_USER_DATA_GS_20', - 'mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_21', - 'mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_22', - 'mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_23', - 'mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_24', - 'mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_25', - 'mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_26', - 'mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_27', - 'mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_28', - 'mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_29', - 'mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_3', 'mmSPI_SHADER_USER_DATA_GS_30', - 'mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_31', - 'mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_4', - 'mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_5', - 'mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_6', - 'mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_7', - 'mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_8', - 'mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_GS_9', - 'mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_0', - 'mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_1', 'mmSPI_SHADER_USER_DATA_HS_10', - 'mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_11', - 'mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_12', - 'mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_13', - 'mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_14', - 'mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_15', - 'mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_16', - 'mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_17', - 'mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_18', - 'mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_19', - 'mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_2', 'mmSPI_SHADER_USER_DATA_HS_20', - 'mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_21', - 'mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_22', - 'mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_23', - 'mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_24', - 'mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_25', - 'mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_26', - 'mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_27', - 'mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_28', - 'mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_29', - 'mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_3', 'mmSPI_SHADER_USER_DATA_HS_30', - 'mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_31', - 'mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_4', - 'mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_5', - 'mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_6', - 'mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_7', - 'mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_8', - 'mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_HS_9', - 'mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_0', - 'mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_1', 'mmSPI_SHADER_USER_DATA_PS_10', - 'mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_11', - 'mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_12', - 'mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_13', - 'mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_14', - 'mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_15', - 'mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_16', - 'mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_17', - 'mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_18', - 'mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_19', - 'mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_2', 'mmSPI_SHADER_USER_DATA_PS_20', - 'mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_21', - 'mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_22', - 'mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_23', - 'mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_24', - 'mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_25', - 'mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_26', - 'mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_27', - 'mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_28', - 'mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_29', - 'mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_3', 'mmSPI_SHADER_USER_DATA_PS_30', - 'mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_31', - 'mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_4', - 'mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_5', - 'mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_6', - 'mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_7', - 'mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_8', - 'mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_PS_9', - 'mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_0', - 'mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_1', 'mmSPI_SHADER_USER_DATA_VS_10', - 'mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_11', - 'mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_12', - 'mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_13', - 'mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_14', - 'mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_15', - 'mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_16', - 'mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_17', - 'mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_18', - 'mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_19', - 'mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_2', 'mmSPI_SHADER_USER_DATA_VS_20', - 'mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_21', - 'mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_22', - 'mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_23', - 'mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_24', - 'mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_25', - 'mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_26', - 'mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_27', - 'mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_28', - 'mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_29', - 'mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_3', 'mmSPI_SHADER_USER_DATA_VS_30', - 'mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_31', - 'mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_4', - 'mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_5', - 'mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_6', - 'mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_7', - 'mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_8', - 'mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX', - 'mmSPI_SHADER_USER_DATA_VS_9', - 'mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX', 'mmSPI_SHADER_Z_FORMAT', - 'mmSPI_SHADER_Z_FORMAT_BASE_IDX', 'mmSPI_START_PHASE', - 'mmSPI_START_PHASE_BASE_IDX', 'mmSPI_SX_EXPORT_BUFFER_SIZES', - 'mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', - 'mmSPI_SX_SCOREBOARD_BUFFER_SIZES', - 'mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', 'mmSPI_TMPRING_SIZE', - 'mmSPI_TMPRING_SIZE_BASE_IDX', 'mmSPI_USER_ACCUM_VMID_CNTL', - 'mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'mmSPI_VS_OUT_CONFIG', - 'mmSPI_VS_OUT_CONFIG_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL', - 'mmSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL_REMAP', - 'mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_CS0', - 'mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_CS1', - 'mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_CS2', - 'mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_CS3', - 'mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_GFX', - 'mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', - 'mmSPI_WCL_PIPE_PERCENT_HP3D', - 'mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', 'mmSPI_WF_LIFETIME_CNTL', - 'mmSPI_WF_LIFETIME_CNTL_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_0', - 'mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_1', - 'mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_2', - 'mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_3', - 'mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_4', - 'mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_5', - 'mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_0', - 'mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_1', 'mmSPI_WF_LIFETIME_STATUS_11', - 'mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_13', - 'mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_14', - 'mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_15', - 'mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_16', - 'mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_17', - 'mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_18', - 'mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_19', - 'mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_2', 'mmSPI_WF_LIFETIME_STATUS_20', - 'mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_21', - 'mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_4', - 'mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_6', - 'mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_7', - 'mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_8', - 'mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX', - 'mmSPI_WF_LIFETIME_STATUS_9', - 'mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'mmSP_CONFIG', - 'mmSP_CONFIG_BASE_IDX', 'mmSQC_CACHES', 'mmSQC_CACHES_BASE_IDX', - 'mmSQC_CONFIG', 'mmSQC_CONFIG_BASE_IDX', - 'mmSQC_DCACHE_UTCL0_CNTL1', 'mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX', - 'mmSQC_DCACHE_UTCL0_CNTL2', 'mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX', - 'mmSQC_DCACHE_UTCL0_STATUS', 'mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX', - 'mmSQC_ICACHE_UTCL0_CNTL1', 'mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX', - 'mmSQC_ICACHE_UTCL0_CNTL2', 'mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX', - 'mmSQC_ICACHE_UTCL0_STATUS', 'mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX', - 'mmSQG_CONFIG', 'mmSQG_CONFIG_BASE_IDX', 'mmSQG_STATUS', - 'mmSQG_STATUS_BASE_IDX', 'mmSQG_UTCL0_CNTL1', - 'mmSQG_UTCL0_CNTL1_BASE_IDX', 'mmSQG_UTCL0_CNTL2', - 'mmSQG_UTCL0_CNTL2_BASE_IDX', 'mmSQG_UTCL0_STATUS', - 'mmSQG_UTCL0_STATUS_BASE_IDX', 'mmSQ_ALU_CLK_CTRL', - 'mmSQ_ALU_CLK_CTRL_BASE_IDX', 'mmSQ_ARB_CONFIG', - 'mmSQ_ARB_CONFIG_BASE_IDX', 'mmSQ_CMD', 'mmSQ_CMD_BASE_IDX', - 'mmSQ_CONFIG', 'mmSQ_CONFIG_BASE_IDX', 'mmSQ_DEBUG', - 'mmSQ_DEBUG_BASE_IDX', 'mmSQ_DEBUG_STS_GLOBAL', - 'mmSQ_DEBUG_STS_GLOBAL2', 'mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX', - 'mmSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'mmSQ_DSM_CNTL', - 'mmSQ_DSM_CNTL2', 'mmSQ_DSM_CNTL2_BASE_IDX', - 'mmSQ_DSM_CNTL_BASE_IDX', 'mmSQ_EDC_CNT', 'mmSQ_EDC_CNT_BASE_IDX', - 'mmSQ_EDC_FUE_CNTL', 'mmSQ_EDC_FUE_CNTL_BASE_IDX', - 'mmSQ_FIFO_SIZES', 'mmSQ_FIFO_SIZES_BASE_IDX', 'mmSQ_IND_DATA', - 'mmSQ_IND_DATA_BASE_IDX', 'mmSQ_IND_INDEX', - 'mmSQ_IND_INDEX_BASE_IDX', 'mmSQ_INTERRUPT_AUTO_MASK', - 'mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'mmSQ_INTERRUPT_MSG_CTRL', - 'mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'mmSQ_LB_CTR_CTRL', - 'mmSQ_LB_CTR_CTRL_BASE_IDX', 'mmSQ_LB_CTR_SEL0', - 'mmSQ_LB_CTR_SEL0_BASE_IDX', 'mmSQ_LB_CTR_SEL1', - 'mmSQ_LB_CTR_SEL1_BASE_IDX', 'mmSQ_LB_DATA0', - 'mmSQ_LB_DATA0_BASE_IDX', 'mmSQ_LB_DATA1', - 'mmSQ_LB_DATA1_BASE_IDX', 'mmSQ_LB_DATA2', - 'mmSQ_LB_DATA2_BASE_IDX', 'mmSQ_LB_DATA3', - 'mmSQ_LB_DATA3_BASE_IDX', 'mmSQ_LDS_CLK_CTRL', - 'mmSQ_LDS_CLK_CTRL_BASE_IDX', 'mmSQ_PERFCOUNTER0_HI', - 'mmSQ_PERFCOUNTER0_HI_BASE_IDX', 'mmSQ_PERFCOUNTER0_LO', - 'mmSQ_PERFCOUNTER0_LO_BASE_IDX', 'mmSQ_PERFCOUNTER0_SELECT', - 'mmSQ_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER10_HI', - 'mmSQ_PERFCOUNTER10_HI_BASE_IDX', 'mmSQ_PERFCOUNTER10_LO', - 'mmSQ_PERFCOUNTER10_LO_BASE_IDX', 'mmSQ_PERFCOUNTER10_SELECT', - 'mmSQ_PERFCOUNTER10_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER11_HI', - 'mmSQ_PERFCOUNTER11_HI_BASE_IDX', 'mmSQ_PERFCOUNTER11_LO', - 'mmSQ_PERFCOUNTER11_LO_BASE_IDX', 'mmSQ_PERFCOUNTER11_SELECT', - 'mmSQ_PERFCOUNTER11_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER12_HI', - 'mmSQ_PERFCOUNTER12_HI_BASE_IDX', 'mmSQ_PERFCOUNTER12_LO', - 'mmSQ_PERFCOUNTER12_LO_BASE_IDX', 'mmSQ_PERFCOUNTER12_SELECT', - 'mmSQ_PERFCOUNTER12_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER13_HI', - 'mmSQ_PERFCOUNTER13_HI_BASE_IDX', 'mmSQ_PERFCOUNTER13_LO', - 'mmSQ_PERFCOUNTER13_LO_BASE_IDX', 'mmSQ_PERFCOUNTER13_SELECT', - 'mmSQ_PERFCOUNTER13_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER14_HI', - 'mmSQ_PERFCOUNTER14_HI_BASE_IDX', 'mmSQ_PERFCOUNTER14_LO', - 'mmSQ_PERFCOUNTER14_LO_BASE_IDX', 'mmSQ_PERFCOUNTER14_SELECT', - 'mmSQ_PERFCOUNTER14_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER15_HI', - 'mmSQ_PERFCOUNTER15_HI_BASE_IDX', 'mmSQ_PERFCOUNTER15_LO', - 'mmSQ_PERFCOUNTER15_LO_BASE_IDX', 'mmSQ_PERFCOUNTER15_SELECT', - 'mmSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER1_HI', - 'mmSQ_PERFCOUNTER1_HI_BASE_IDX', 'mmSQ_PERFCOUNTER1_LO', - 'mmSQ_PERFCOUNTER1_LO_BASE_IDX', 'mmSQ_PERFCOUNTER1_SELECT', - 'mmSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER2_HI', - 'mmSQ_PERFCOUNTER2_HI_BASE_IDX', 'mmSQ_PERFCOUNTER2_LO', - 'mmSQ_PERFCOUNTER2_LO_BASE_IDX', 'mmSQ_PERFCOUNTER2_SELECT', - 'mmSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER3_HI', - 'mmSQ_PERFCOUNTER3_HI_BASE_IDX', 'mmSQ_PERFCOUNTER3_LO', - 'mmSQ_PERFCOUNTER3_LO_BASE_IDX', 'mmSQ_PERFCOUNTER3_SELECT', - 'mmSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER4_HI', - 'mmSQ_PERFCOUNTER4_HI_BASE_IDX', 'mmSQ_PERFCOUNTER4_LO', - 'mmSQ_PERFCOUNTER4_LO_BASE_IDX', 'mmSQ_PERFCOUNTER4_SELECT', - 'mmSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER5_HI', - 'mmSQ_PERFCOUNTER5_HI_BASE_IDX', 'mmSQ_PERFCOUNTER5_LO', - 'mmSQ_PERFCOUNTER5_LO_BASE_IDX', 'mmSQ_PERFCOUNTER5_SELECT', - 'mmSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER6_HI', - 'mmSQ_PERFCOUNTER6_HI_BASE_IDX', 'mmSQ_PERFCOUNTER6_LO', - 'mmSQ_PERFCOUNTER6_LO_BASE_IDX', 'mmSQ_PERFCOUNTER6_SELECT', - 'mmSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER7_HI', - 'mmSQ_PERFCOUNTER7_HI_BASE_IDX', 'mmSQ_PERFCOUNTER7_LO', - 'mmSQ_PERFCOUNTER7_LO_BASE_IDX', 'mmSQ_PERFCOUNTER7_SELECT', - 'mmSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER8_HI', - 'mmSQ_PERFCOUNTER8_HI_BASE_IDX', 'mmSQ_PERFCOUNTER8_LO', - 'mmSQ_PERFCOUNTER8_LO_BASE_IDX', 'mmSQ_PERFCOUNTER8_SELECT', - 'mmSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER9_HI', - 'mmSQ_PERFCOUNTER9_HI_BASE_IDX', 'mmSQ_PERFCOUNTER9_LO', - 'mmSQ_PERFCOUNTER9_LO_BASE_IDX', 'mmSQ_PERFCOUNTER9_SELECT', - 'mmSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER_CTRL', - 'mmSQ_PERFCOUNTER_CTRL2', 'mmSQ_PERFCOUNTER_CTRL2_BASE_IDX', - 'mmSQ_PERFCOUNTER_CTRL_BASE_IDX', 'mmSQ_RANDOM_WAVE_PRI', - 'mmSQ_RANDOM_WAVE_PRI_BASE_IDX', 'mmSQ_RUNTIME_CONFIG', - 'mmSQ_RUNTIME_CONFIG_BASE_IDX', 'mmSQ_SHADER_TBA_HI', - 'mmSQ_SHADER_TBA_HI_BASE_IDX', 'mmSQ_SHADER_TBA_LO', - 'mmSQ_SHADER_TBA_LO_BASE_IDX', 'mmSQ_SHADER_TMA_HI', - 'mmSQ_SHADER_TMA_HI_BASE_IDX', 'mmSQ_SHADER_TMA_LO', - 'mmSQ_SHADER_TMA_LO_BASE_IDX', 'mmSQ_TEX_CLK_CTRL', - 'mmSQ_TEX_CLK_CTRL_BASE_IDX', 'mmSQ_THREAD_TRACE_BUF0_BASE', - 'mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX', - 'mmSQ_THREAD_TRACE_BUF0_SIZE', - 'mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX', - 'mmSQ_THREAD_TRACE_BUF1_BASE', - 'mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX', - 'mmSQ_THREAD_TRACE_BUF1_SIZE', - 'mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', 'mmSQ_THREAD_TRACE_CTRL', - 'mmSQ_THREAD_TRACE_CTRL_BASE_IDX', - 'mmSQ_THREAD_TRACE_DROPPED_CNTR', - 'mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX', - 'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR', - 'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX', - 'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR', - 'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX', - 'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR', - 'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX', - 'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR', - 'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX', - 'mmSQ_THREAD_TRACE_MASK', 'mmSQ_THREAD_TRACE_MASK_BASE_IDX', - 'mmSQ_THREAD_TRACE_STATUS', 'mmSQ_THREAD_TRACE_STATUS2', - 'mmSQ_THREAD_TRACE_STATUS2_BASE_IDX', - 'mmSQ_THREAD_TRACE_STATUS_BASE_IDX', - 'mmSQ_THREAD_TRACE_TOKEN_MASK', - 'mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_0', - 'mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_1', - 'mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_2', - 'mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_3', - 'mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_4', - 'mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_5', - 'mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_6', - 'mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX', - 'mmSQ_THREAD_TRACE_USERDATA_7', - 'mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', 'mmSQ_THREAD_TRACE_WPTR', - 'mmSQ_THREAD_TRACE_WPTR_BASE_IDX', 'mmSQ_TIME_HI', - 'mmSQ_TIME_HI_BASE_IDX', 'mmSQ_TIME_LO', 'mmSQ_TIME_LO_BASE_IDX', - 'mmSQ_WATCH0_ADDR_H', 'mmSQ_WATCH0_ADDR_H_BASE_IDX', - 'mmSQ_WATCH0_ADDR_L', 'mmSQ_WATCH0_ADDR_L_BASE_IDX', - 'mmSQ_WATCH0_CNTL', 'mmSQ_WATCH0_CNTL_BASE_IDX', - 'mmSQ_WATCH1_ADDR_H', 'mmSQ_WATCH1_ADDR_H_BASE_IDX', - 'mmSQ_WATCH1_ADDR_L', 'mmSQ_WATCH1_ADDR_L_BASE_IDX', - 'mmSQ_WATCH1_CNTL', 'mmSQ_WATCH1_CNTL_BASE_IDX', - 'mmSQ_WATCH2_ADDR_H', 'mmSQ_WATCH2_ADDR_H_BASE_IDX', - 'mmSQ_WATCH2_ADDR_L', 'mmSQ_WATCH2_ADDR_L_BASE_IDX', - 'mmSQ_WATCH2_CNTL', 'mmSQ_WATCH2_CNTL_BASE_IDX', - 'mmSQ_WATCH3_ADDR_H', 'mmSQ_WATCH3_ADDR_H_BASE_IDX', - 'mmSQ_WATCH3_ADDR_L', 'mmSQ_WATCH3_ADDR_L_BASE_IDX', - 'mmSQ_WATCH3_CNTL', 'mmSQ_WATCH3_CNTL_BASE_IDX', - 'mmSQ_WREXEC_EXEC_HI', 'mmSQ_WREXEC_EXEC_HI_BASE_IDX', - 'mmSQ_WREXEC_EXEC_LO', 'mmSQ_WREXEC_EXEC_LO_BASE_IDX', - 'mmSX_BLEND_OPT_CONTROL', 'mmSX_BLEND_OPT_CONTROL_BASE_IDX', - 'mmSX_BLEND_OPT_EPSILON', 'mmSX_BLEND_OPT_EPSILON_BASE_IDX', - 'mmSX_DEBUG_1', 'mmSX_DEBUG_1_BASE_IDX', 'mmSX_MRT0_BLEND_OPT', - 'mmSX_MRT0_BLEND_OPT_BASE_IDX', 'mmSX_MRT1_BLEND_OPT', - 'mmSX_MRT1_BLEND_OPT_BASE_IDX', 'mmSX_MRT2_BLEND_OPT', - 'mmSX_MRT2_BLEND_OPT_BASE_IDX', 'mmSX_MRT3_BLEND_OPT', - 'mmSX_MRT3_BLEND_OPT_BASE_IDX', 'mmSX_MRT4_BLEND_OPT', - 'mmSX_MRT4_BLEND_OPT_BASE_IDX', 'mmSX_MRT5_BLEND_OPT', - 'mmSX_MRT5_BLEND_OPT_BASE_IDX', 'mmSX_MRT6_BLEND_OPT', - 'mmSX_MRT6_BLEND_OPT_BASE_IDX', 'mmSX_MRT7_BLEND_OPT', - 'mmSX_MRT7_BLEND_OPT_BASE_IDX', 'mmSX_PERFCOUNTER0_HI', - 'mmSX_PERFCOUNTER0_HI_BASE_IDX', 'mmSX_PERFCOUNTER0_LO', - 'mmSX_PERFCOUNTER0_LO_BASE_IDX', 'mmSX_PERFCOUNTER0_SELECT', - 'mmSX_PERFCOUNTER0_SELECT1', 'mmSX_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmSX_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER1_HI', - 'mmSX_PERFCOUNTER1_HI_BASE_IDX', 'mmSX_PERFCOUNTER1_LO', - 'mmSX_PERFCOUNTER1_LO_BASE_IDX', 'mmSX_PERFCOUNTER1_SELECT', - 'mmSX_PERFCOUNTER1_SELECT1', 'mmSX_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmSX_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER2_HI', - 'mmSX_PERFCOUNTER2_HI_BASE_IDX', 'mmSX_PERFCOUNTER2_LO', - 'mmSX_PERFCOUNTER2_LO_BASE_IDX', 'mmSX_PERFCOUNTER2_SELECT', - 'mmSX_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER3_HI', - 'mmSX_PERFCOUNTER3_HI_BASE_IDX', 'mmSX_PERFCOUNTER3_LO', - 'mmSX_PERFCOUNTER3_LO_BASE_IDX', 'mmSX_PERFCOUNTER3_SELECT', - 'mmSX_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSX_PS_DOWNCONVERT', - 'mmSX_PS_DOWNCONVERT_BASE_IDX', 'mmSX_PS_DOWNCONVERT_CONTROL', - 'mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'mmTA_BC_BASE_ADDR', - 'mmTA_BC_BASE_ADDR_BASE_IDX', 'mmTA_BC_BASE_ADDR_HI', - 'mmTA_BC_BASE_ADDR_HI_BASE_IDX', 'mmTA_CGTT_CTRL', - 'mmTA_CGTT_CTRL_BASE_IDX', 'mmTA_CNTL', 'mmTA_CNTL_BASE_IDX', - 'mmTA_CS_BC_BASE_ADDR', 'mmTA_CS_BC_BASE_ADDR_BASE_IDX', - 'mmTA_CS_BC_BASE_ADDR_HI', 'mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX', - 'mmTA_PERFCOUNTER0_HI', 'mmTA_PERFCOUNTER0_HI_BASE_IDX', - 'mmTA_PERFCOUNTER0_LO', 'mmTA_PERFCOUNTER0_LO_BASE_IDX', - 'mmTA_PERFCOUNTER0_SELECT', 'mmTA_PERFCOUNTER0_SELECT1', - 'mmTA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmTA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTA_PERFCOUNTER1_HI', - 'mmTA_PERFCOUNTER1_HI_BASE_IDX', 'mmTA_PERFCOUNTER1_LO', - 'mmTA_PERFCOUNTER1_LO_BASE_IDX', 'mmTA_PERFCOUNTER1_SELECT', - 'mmTA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTA_RESERVED_010C', - 'mmTA_RESERVED_010C_BASE_IDX', 'mmTA_SCRATCH', - 'mmTA_SCRATCH_BASE_IDX', 'mmTA_STATUS', 'mmTA_STATUS_BASE_IDX', - 'mmTCI_CNTL_1', 'mmTCI_CNTL_1_BASE_IDX', 'mmTCI_CNTL_2', - 'mmTCI_CNTL_2_BASE_IDX', 'mmTCI_STATUS', 'mmTCI_STATUS_BASE_IDX', - 'mmTCP_EDC_CNT', 'mmTCP_EDC_CNT_BASE_IDX', 'mmTCP_INVALIDATE', - 'mmTCP_INVALIDATE_BASE_IDX', 'mmTCP_PERFCOUNTER0_HI', - 'mmTCP_PERFCOUNTER0_HI_BASE_IDX', 'mmTCP_PERFCOUNTER0_LO', - 'mmTCP_PERFCOUNTER0_LO_BASE_IDX', 'mmTCP_PERFCOUNTER0_SELECT', - 'mmTCP_PERFCOUNTER0_SELECT1', - 'mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER1_HI', - 'mmTCP_PERFCOUNTER1_HI_BASE_IDX', 'mmTCP_PERFCOUNTER1_LO', - 'mmTCP_PERFCOUNTER1_LO_BASE_IDX', 'mmTCP_PERFCOUNTER1_SELECT', - 'mmTCP_PERFCOUNTER1_SELECT1', - 'mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX', - 'mmTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER2_HI', - 'mmTCP_PERFCOUNTER2_HI_BASE_IDX', 'mmTCP_PERFCOUNTER2_LO', - 'mmTCP_PERFCOUNTER2_LO_BASE_IDX', 'mmTCP_PERFCOUNTER2_SELECT', - 'mmTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER3_HI', - 'mmTCP_PERFCOUNTER3_HI_BASE_IDX', 'mmTCP_PERFCOUNTER3_LO', - 'mmTCP_PERFCOUNTER3_LO_BASE_IDX', 'mmTCP_PERFCOUNTER3_SELECT', - 'mmTCP_PERFCOUNTER3_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER_FILTER', - 'mmTCP_PERFCOUNTER_FILTER2', 'mmTCP_PERFCOUNTER_FILTER2_BASE_IDX', - 'mmTCP_PERFCOUNTER_FILTER_BASE_IDX', - 'mmTCP_PERFCOUNTER_FILTER_EN', - 'mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'mmTCP_STATUS', - 'mmTCP_STATUS_BASE_IDX', 'mmTCP_WATCH0_ADDR_H', - 'mmTCP_WATCH0_ADDR_H_BASE_IDX', 'mmTCP_WATCH0_ADDR_L', - 'mmTCP_WATCH0_ADDR_L_BASE_IDX', 'mmTCP_WATCH0_CNTL', - 'mmTCP_WATCH0_CNTL_BASE_IDX', 'mmTCP_WATCH1_ADDR_H', - 'mmTCP_WATCH1_ADDR_H_BASE_IDX', 'mmTCP_WATCH1_ADDR_L', - 'mmTCP_WATCH1_ADDR_L_BASE_IDX', 'mmTCP_WATCH1_CNTL', - 'mmTCP_WATCH1_CNTL_BASE_IDX', 'mmTCP_WATCH2_ADDR_H', - 'mmTCP_WATCH2_ADDR_H_BASE_IDX', 'mmTCP_WATCH2_ADDR_L', - 'mmTCP_WATCH2_ADDR_L_BASE_IDX', 'mmTCP_WATCH2_CNTL', - 'mmTCP_WATCH2_CNTL_BASE_IDX', 'mmTCP_WATCH3_ADDR_H', - 'mmTCP_WATCH3_ADDR_H_BASE_IDX', 'mmTCP_WATCH3_ADDR_L', - 'mmTCP_WATCH3_ADDR_L_BASE_IDX', 'mmTCP_WATCH3_CNTL', - 'mmTCP_WATCH3_CNTL_BASE_IDX', 'mmTD_CGTT_CTRL', - 'mmTD_CGTT_CTRL_BASE_IDX', 'mmTD_DSM_CNTL', 'mmTD_DSM_CNTL2', - 'mmTD_DSM_CNTL2_BASE_IDX', 'mmTD_DSM_CNTL_BASE_IDX', - 'mmTD_PERFCOUNTER0_HI', 'mmTD_PERFCOUNTER0_HI_BASE_IDX', - 'mmTD_PERFCOUNTER0_LO', 'mmTD_PERFCOUNTER0_LO_BASE_IDX', - 'mmTD_PERFCOUNTER0_SELECT', 'mmTD_PERFCOUNTER0_SELECT1', - 'mmTD_PERFCOUNTER0_SELECT1_BASE_IDX', - 'mmTD_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTD_PERFCOUNTER1_HI', - 'mmTD_PERFCOUNTER1_HI_BASE_IDX', 'mmTD_PERFCOUNTER1_LO', - 'mmTD_PERFCOUNTER1_LO_BASE_IDX', 'mmTD_PERFCOUNTER1_SELECT', - 'mmTD_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTD_SCRATCH', - 'mmTD_SCRATCH_BASE_IDX', 'mmTD_STATUS', 'mmTD_STATUS_BASE_IDX', - 'mmUCONFIG_RESERVED_REG0', 'mmUCONFIG_RESERVED_REG0_BASE_IDX', - 'mmUCONFIG_RESERVED_REG1', 'mmUCONFIG_RESERVED_REG1_BASE_IDX', - 'mmUTCL1_ALOG', 'mmUTCL1_ALOG_BASE_IDX', 'mmUTCL1_CGTT_CLK_CTRL', - 'mmUTCL1_CGTT_CLK_CTRL_BASE_IDX', 'mmUTCL1_CTRL', - 'mmUTCL1_CTRL_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_HI', - 'mmUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_LO', - 'mmUTCL1_PERFCOUNTER0_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_SELECT', - 'mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_HI', - 'mmUTCL1_PERFCOUNTER1_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_LO', - 'mmUTCL1_PERFCOUNTER1_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_SELECT', - 'mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmUTCL1_STATUS', - 'mmUTCL1_STATUS_BASE_IDX', 'mmUTCL1_UTCL0_INVREQ_DISABLE', - 'mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', - 'mmVGT_CACHE_INVALIDATION', 'mmVGT_CACHE_INVALIDATION_BASE_IDX', - 'mmVGT_DISPATCH_DRAW_INDEX', 'mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX', - 'mmVGT_DMA_BASE', 'mmVGT_DMA_BASE_BASE_IDX', 'mmVGT_DMA_BASE_HI', - 'mmVGT_DMA_BASE_HI_BASE_IDX', 'mmVGT_DMA_CONTROL', - 'mmVGT_DMA_CONTROL_BASE_IDX', 'mmVGT_DMA_DATA_FIFO_DEPTH', - 'mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_EVENT_INITIATOR', - 'mmVGT_DMA_EVENT_INITIATOR_BASE_IDX', 'mmVGT_DMA_INDEX_TYPE', - 'mmVGT_DMA_INDEX_TYPE_BASE_IDX', 'mmVGT_DMA_LS_HS_CONFIG', - 'mmVGT_DMA_LS_HS_CONFIG_BASE_IDX', 'mmVGT_DMA_MAX_SIZE', - 'mmVGT_DMA_MAX_SIZE_BASE_IDX', 'mmVGT_DMA_NUM_INSTANCES', - 'mmVGT_DMA_NUM_INSTANCES_BASE_IDX', 'mmVGT_DMA_PRIMITIVE_TYPE', - 'mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_DMA_REQ_FIFO_DEPTH', - 'mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_SIZE', - 'mmVGT_DMA_SIZE_BASE_IDX', 'mmVGT_DRAW_INITIATOR', - 'mmVGT_DRAW_INITIATOR_BASE_IDX', 'mmVGT_DRAW_INIT_FIFO_DEPTH', - 'mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', 'mmVGT_DRAW_PAYLOAD_CNTL', - 'mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', 'mmVGT_ENHANCE', - 'mmVGT_ENHANCE_BASE_IDX', 'mmVGT_ESGS_RING_ITEMSIZE', - 'mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE', - 'mmVGT_ESGS_RING_SIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE_UMD', - 'mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX', 'mmVGT_ES_PER_GS', - 'mmVGT_ES_PER_GS_BASE_IDX', 'mmVGT_EVENT_ADDRESS_REG', - 'mmVGT_EVENT_ADDRESS_REG_BASE_IDX', 'mmVGT_EVENT_INITIATOR', - 'mmVGT_EVENT_INITIATOR_BASE_IDX', 'mmVGT_FIFO_DEPTHS', - 'mmVGT_FIFO_DEPTHS_BASE_IDX', 'mmVGT_GROUP_DECR', - 'mmVGT_GROUP_DECR_BASE_IDX', 'mmVGT_GROUP_FIRST_DECR', - 'mmVGT_GROUP_FIRST_DECR_BASE_IDX', 'mmVGT_GROUP_PRIM_TYPE', - 'mmVGT_GROUP_PRIM_TYPE_BASE_IDX', 'mmVGT_GROUP_VECT_0_CNTL', - 'mmVGT_GROUP_VECT_0_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_0_FMT_CNTL', - 'mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_CNTL', - 'mmVGT_GROUP_VECT_1_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_FMT_CNTL', - 'mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX', - 'mmVGT_GSVS_RING_ITEMSIZE', 'mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX', - 'mmVGT_GSVS_RING_OFFSET_1', 'mmVGT_GSVS_RING_OFFSET_1_BASE_IDX', - 'mmVGT_GSVS_RING_OFFSET_2', 'mmVGT_GSVS_RING_OFFSET_2_BASE_IDX', - 'mmVGT_GSVS_RING_OFFSET_3', 'mmVGT_GSVS_RING_OFFSET_3_BASE_IDX', - 'mmVGT_GSVS_RING_SIZE', 'mmVGT_GSVS_RING_SIZE_BASE_IDX', - 'mmVGT_GSVS_RING_SIZE_UMD', 'mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX', - 'mmVGT_GS_INSTANCE_CNT', 'mmVGT_GS_INSTANCE_CNT_BASE_IDX', - 'mmVGT_GS_MAX_VERT_OUT', 'mmVGT_GS_MAX_VERT_OUT_BASE_IDX', - 'mmVGT_GS_MAX_WAVE_ID', 'mmVGT_GS_MAX_WAVE_ID_BASE_IDX', - 'mmVGT_GS_MODE', 'mmVGT_GS_MODE_BASE_IDX', 'mmVGT_GS_ONCHIP_CNTL', - 'mmVGT_GS_ONCHIP_CNTL_BASE_IDX', 'mmVGT_GS_OUT_PRIM_TYPE', - 'mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX', 'mmVGT_GS_PER_ES', - 'mmVGT_GS_PER_ES_BASE_IDX', 'mmVGT_GS_PER_VS', - 'mmVGT_GS_PER_VS_BASE_IDX', 'mmVGT_GS_VERTEX_REUSE', - 'mmVGT_GS_VERTEX_REUSE_BASE_IDX', 'mmVGT_GS_VERT_ITEMSIZE', - 'mmVGT_GS_VERT_ITEMSIZE_1', 'mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX', - 'mmVGT_GS_VERT_ITEMSIZE_2', 'mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX', - 'mmVGT_GS_VERT_ITEMSIZE_3', 'mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX', - 'mmVGT_GS_VERT_ITEMSIZE_BASE_IDX', 'mmVGT_HOS_CNTL', - 'mmVGT_HOS_CNTL_BASE_IDX', 'mmVGT_HOS_MAX_TESS_LEVEL', - 'mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_MIN_TESS_LEVEL', - 'mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_REUSE_DEPTH', - 'mmVGT_HOS_REUSE_DEPTH_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM', - 'mmVGT_HS_OFFCHIP_PARAM_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM_UMD', - 'mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX', 'mmVGT_IMMED_DATA', - 'mmVGT_IMMED_DATA_BASE_IDX', 'mmVGT_INDEX_TYPE', - 'mmVGT_INDEX_TYPE_BASE_IDX', 'mmVGT_INDX_OFFSET', - 'mmVGT_INDX_OFFSET_BASE_IDX', 'mmVGT_INSTANCE_BASE_ID', - 'mmVGT_INSTANCE_BASE_ID_BASE_IDX', 'mmVGT_INSTANCE_STEP_RATE_0', - 'mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX', - 'mmVGT_INSTANCE_STEP_RATE_1', - 'mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX', 'mmVGT_LAST_COPY_STATE', - 'mmVGT_LAST_COPY_STATE_BASE_IDX', 'mmVGT_LS_HS_CONFIG', - 'mmVGT_LS_HS_CONFIG_BASE_IDX', 'mmVGT_MAX_VTX_INDX', - 'mmVGT_MAX_VTX_INDX_BASE_IDX', 'mmVGT_MC_LAT_CNTL', - 'mmVGT_MC_LAT_CNTL_BASE_IDX', 'mmVGT_MIN_VTX_INDX', - 'mmVGT_MIN_VTX_INDX_BASE_IDX', 'mmVGT_MULTI_PRIM_IB_RESET_EN', - 'mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX', - 'mmVGT_MULTI_PRIM_IB_RESET_INDX', - 'mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'mmVGT_NUM_INDICES', - 'mmVGT_NUM_INDICES_BASE_IDX', 'mmVGT_NUM_INSTANCES', - 'mmVGT_NUM_INSTANCES_BASE_IDX', 'mmVGT_OUTPUT_PATH_CNTL', - 'mmVGT_OUTPUT_PATH_CNTL_BASE_IDX', 'mmVGT_OUT_DEALLOC_CNTL', - 'mmVGT_OUT_DEALLOC_CNTL_BASE_IDX', 'mmVGT_PRIMITIVEID_EN', - 'mmVGT_PRIMITIVEID_EN_BASE_IDX', 'mmVGT_PRIMITIVEID_RESET', - 'mmVGT_PRIMITIVEID_RESET_BASE_IDX', 'mmVGT_PRIMITIVE_TYPE', - 'mmVGT_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_REUSE_OFF', - 'mmVGT_REUSE_OFF_BASE_IDX', 'mmVGT_SHADER_STAGES_EN', - 'mmVGT_SHADER_STAGES_EN_BASE_IDX', 'mmVGT_STRMOUT_BUFFER_CONFIG', - 'mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3', - 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_OFFSET_0', - 'mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_OFFSET_1', - 'mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_OFFSET_2', - 'mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_OFFSET_3', - 'mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_SIZE_0', - 'mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_SIZE_1', - 'mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_SIZE_2', - 'mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX', - 'mmVGT_STRMOUT_BUFFER_SIZE_3', - 'mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX', 'mmVGT_STRMOUT_CONFIG', - 'mmVGT_STRMOUT_CONFIG_BASE_IDX', 'mmVGT_STRMOUT_DELAY', - 'mmVGT_STRMOUT_DELAY_BASE_IDX', - 'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', - 'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', - 'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET', - 'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', - 'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', - 'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', - 'mmVGT_STRMOUT_VTX_STRIDE_0', - 'mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX', - 'mmVGT_STRMOUT_VTX_STRIDE_1', - 'mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX', - 'mmVGT_STRMOUT_VTX_STRIDE_2', - 'mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX', - 'mmVGT_STRMOUT_VTX_STRIDE_3', - 'mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX', 'mmVGT_SYS_CONFIG', - 'mmVGT_SYS_CONFIG_BASE_IDX', 'mmVGT_TESS_DISTRIBUTION', - 'mmVGT_TESS_DISTRIBUTION_BASE_IDX', 'mmVGT_TF_MEMORY_BASE', - 'mmVGT_TF_MEMORY_BASE_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI', - 'mmVGT_TF_MEMORY_BASE_HI_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI_UMD', - 'mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX', - 'mmVGT_TF_MEMORY_BASE_UMD', 'mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX', - 'mmVGT_TF_PARAM', 'mmVGT_TF_PARAM_BASE_IDX', 'mmVGT_TF_RING_SIZE', - 'mmVGT_TF_RING_SIZE_BASE_IDX', 'mmVGT_TF_RING_SIZE_UMD', - 'mmVGT_TF_RING_SIZE_UMD_BASE_IDX', - 'mmVGT_VERTEX_REUSE_BLOCK_CNTL', - 'mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX', 'mmVGT_VS_MAX_WAVE_ID', - 'mmVGT_VS_MAX_WAVE_ID_BASE_IDX', 'mmVGT_VTX_CNT_EN', - 'mmVGT_VTX_CNT_EN_BASE_IDX', 'mmVGT_VTX_VECT_EJECT_REG', - 'mmVGT_VTX_VECT_EJECT_REG_BASE_IDX', - 'mmVIOLATION_DATA_ASYNC_VF_PROG', - 'mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'mmWD_BUF_RESOURCE_1', - 'mmWD_BUF_RESOURCE_1_BASE_IDX', 'mmWD_BUF_RESOURCE_2', - 'mmWD_BUF_RESOURCE_2_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE', - 'mmWD_CNTL_SB_BUF_BASE_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE_HI', - 'mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX', 'mmWD_CNTL_STATUS', - 'mmWD_CNTL_STATUS_BASE_IDX', 'mmWD_ENHANCE', - 'mmWD_ENHANCE_BASE_IDX', 'mmWD_INDEX_BUF_BASE', - 'mmWD_INDEX_BUF_BASE_BASE_IDX', 'mmWD_INDEX_BUF_BASE_HI', - 'mmWD_INDEX_BUF_BASE_HI_BASE_IDX', 'mmWD_POS_BUF_BASE', - 'mmWD_POS_BUF_BASE_BASE_IDX', 'mmWD_POS_BUF_BASE_HI', - 'mmWD_POS_BUF_BASE_HI_BASE_IDX', 'mmWD_QOS', 'mmWD_QOS_BASE_IDX', - 'mmWD_UTCL1_CNTL', 'mmWD_UTCL1_CNTL_BASE_IDX', - 'mmWD_UTCL1_STATUS', 'mmWD_UTCL1_STATUS_BASE_IDX', - 'pq_exe_status__mec_release_mem__default', - 'pq_exe_status__mec_release_mem__phase_update', - 'regCB_BLEND0_CONTROL', 'regCB_BLEND0_CONTROL_BASE_IDX', - 'regCB_BLEND1_CONTROL', 'regCB_BLEND1_CONTROL_BASE_IDX', - 'regCB_BLEND2_CONTROL', 'regCB_BLEND2_CONTROL_BASE_IDX', - 'regCB_BLEND3_CONTROL', 'regCB_BLEND3_CONTROL_BASE_IDX', - 'regCB_BLEND4_CONTROL', 'regCB_BLEND4_CONTROL_BASE_IDX', - 'regCB_BLEND5_CONTROL', 'regCB_BLEND5_CONTROL_BASE_IDX', - 'regCB_BLEND6_CONTROL', 'regCB_BLEND6_CONTROL_BASE_IDX', - 'regCB_BLEND7_CONTROL', 'regCB_BLEND7_CONTROL_BASE_IDX', - 'regCB_BLEND_ALPHA', 'regCB_BLEND_ALPHA_BASE_IDX', - 'regCB_BLEND_BLUE', 'regCB_BLEND_BLUE_BASE_IDX', - 'regCB_BLEND_GREEN', 'regCB_BLEND_GREEN_BASE_IDX', - 'regCB_BLEND_RED', 'regCB_BLEND_RED_BASE_IDX', - 'regCB_CACHE_EVICT_POINTS', 'regCB_CACHE_EVICT_POINTS_BASE_IDX', - 'regCB_CGTT_SCLK_CTRL', 'regCB_CGTT_SCLK_CTRL_BASE_IDX', - 'regCB_COLOR0_ATTRIB', 'regCB_COLOR0_ATTRIB2', - 'regCB_COLOR0_ATTRIB2_BASE_IDX', 'regCB_COLOR0_ATTRIB3', - 'regCB_COLOR0_ATTRIB3_BASE_IDX', 'regCB_COLOR0_ATTRIB_BASE_IDX', - 'regCB_COLOR0_BASE', 'regCB_COLOR0_BASE_BASE_IDX', - 'regCB_COLOR0_BASE_EXT', 'regCB_COLOR0_BASE_EXT_BASE_IDX', - 'regCB_COLOR0_DCC_BASE', 'regCB_COLOR0_DCC_BASE_BASE_IDX', - 'regCB_COLOR0_DCC_BASE_EXT', 'regCB_COLOR0_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR0_FDCC_CONTROL', 'regCB_COLOR0_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR0_INFO', 'regCB_COLOR0_INFO_BASE_IDX', - 'regCB_COLOR0_VIEW', 'regCB_COLOR0_VIEW_BASE_IDX', - 'regCB_COLOR1_ATTRIB', 'regCB_COLOR1_ATTRIB2', - 'regCB_COLOR1_ATTRIB2_BASE_IDX', 'regCB_COLOR1_ATTRIB3', - 'regCB_COLOR1_ATTRIB3_BASE_IDX', 'regCB_COLOR1_ATTRIB_BASE_IDX', - 'regCB_COLOR1_BASE', 'regCB_COLOR1_BASE_BASE_IDX', - 'regCB_COLOR1_BASE_EXT', 'regCB_COLOR1_BASE_EXT_BASE_IDX', - 'regCB_COLOR1_DCC_BASE', 'regCB_COLOR1_DCC_BASE_BASE_IDX', - 'regCB_COLOR1_DCC_BASE_EXT', 'regCB_COLOR1_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR1_FDCC_CONTROL', 'regCB_COLOR1_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR1_INFO', 'regCB_COLOR1_INFO_BASE_IDX', - 'regCB_COLOR1_VIEW', 'regCB_COLOR1_VIEW_BASE_IDX', - 'regCB_COLOR2_ATTRIB', 'regCB_COLOR2_ATTRIB2', - 'regCB_COLOR2_ATTRIB2_BASE_IDX', 'regCB_COLOR2_ATTRIB3', - 'regCB_COLOR2_ATTRIB3_BASE_IDX', 'regCB_COLOR2_ATTRIB_BASE_IDX', - 'regCB_COLOR2_BASE', 'regCB_COLOR2_BASE_BASE_IDX', - 'regCB_COLOR2_BASE_EXT', 'regCB_COLOR2_BASE_EXT_BASE_IDX', - 'regCB_COLOR2_DCC_BASE', 'regCB_COLOR2_DCC_BASE_BASE_IDX', - 'regCB_COLOR2_DCC_BASE_EXT', 'regCB_COLOR2_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR2_FDCC_CONTROL', 'regCB_COLOR2_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR2_INFO', 'regCB_COLOR2_INFO_BASE_IDX', - 'regCB_COLOR2_VIEW', 'regCB_COLOR2_VIEW_BASE_IDX', - 'regCB_COLOR3_ATTRIB', 'regCB_COLOR3_ATTRIB2', - 'regCB_COLOR3_ATTRIB2_BASE_IDX', 'regCB_COLOR3_ATTRIB3', - 'regCB_COLOR3_ATTRIB3_BASE_IDX', 'regCB_COLOR3_ATTRIB_BASE_IDX', - 'regCB_COLOR3_BASE', 'regCB_COLOR3_BASE_BASE_IDX', - 'regCB_COLOR3_BASE_EXT', 'regCB_COLOR3_BASE_EXT_BASE_IDX', - 'regCB_COLOR3_DCC_BASE', 'regCB_COLOR3_DCC_BASE_BASE_IDX', - 'regCB_COLOR3_DCC_BASE_EXT', 'regCB_COLOR3_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR3_FDCC_CONTROL', 'regCB_COLOR3_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR3_INFO', 'regCB_COLOR3_INFO_BASE_IDX', - 'regCB_COLOR3_VIEW', 'regCB_COLOR3_VIEW_BASE_IDX', - 'regCB_COLOR4_ATTRIB', 'regCB_COLOR4_ATTRIB2', - 'regCB_COLOR4_ATTRIB2_BASE_IDX', 'regCB_COLOR4_ATTRIB3', - 'regCB_COLOR4_ATTRIB3_BASE_IDX', 'regCB_COLOR4_ATTRIB_BASE_IDX', - 'regCB_COLOR4_BASE', 'regCB_COLOR4_BASE_BASE_IDX', - 'regCB_COLOR4_BASE_EXT', 'regCB_COLOR4_BASE_EXT_BASE_IDX', - 'regCB_COLOR4_DCC_BASE', 'regCB_COLOR4_DCC_BASE_BASE_IDX', - 'regCB_COLOR4_DCC_BASE_EXT', 'regCB_COLOR4_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR4_FDCC_CONTROL', 'regCB_COLOR4_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR4_INFO', 'regCB_COLOR4_INFO_BASE_IDX', - 'regCB_COLOR4_VIEW', 'regCB_COLOR4_VIEW_BASE_IDX', - 'regCB_COLOR5_ATTRIB', 'regCB_COLOR5_ATTRIB2', - 'regCB_COLOR5_ATTRIB2_BASE_IDX', 'regCB_COLOR5_ATTRIB3', - 'regCB_COLOR5_ATTRIB3_BASE_IDX', 'regCB_COLOR5_ATTRIB_BASE_IDX', - 'regCB_COLOR5_BASE', 'regCB_COLOR5_BASE_BASE_IDX', - 'regCB_COLOR5_BASE_EXT', 'regCB_COLOR5_BASE_EXT_BASE_IDX', - 'regCB_COLOR5_DCC_BASE', 'regCB_COLOR5_DCC_BASE_BASE_IDX', - 'regCB_COLOR5_DCC_BASE_EXT', 'regCB_COLOR5_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR5_FDCC_CONTROL', 'regCB_COLOR5_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR5_INFO', 'regCB_COLOR5_INFO_BASE_IDX', - 'regCB_COLOR5_VIEW', 'regCB_COLOR5_VIEW_BASE_IDX', - 'regCB_COLOR6_ATTRIB', 'regCB_COLOR6_ATTRIB2', - 'regCB_COLOR6_ATTRIB2_BASE_IDX', 'regCB_COLOR6_ATTRIB3', - 'regCB_COLOR6_ATTRIB3_BASE_IDX', 'regCB_COLOR6_ATTRIB_BASE_IDX', - 'regCB_COLOR6_BASE', 'regCB_COLOR6_BASE_BASE_IDX', - 'regCB_COLOR6_BASE_EXT', 'regCB_COLOR6_BASE_EXT_BASE_IDX', - 'regCB_COLOR6_DCC_BASE', 'regCB_COLOR6_DCC_BASE_BASE_IDX', - 'regCB_COLOR6_DCC_BASE_EXT', 'regCB_COLOR6_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR6_FDCC_CONTROL', 'regCB_COLOR6_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR6_INFO', 'regCB_COLOR6_INFO_BASE_IDX', - 'regCB_COLOR6_VIEW', 'regCB_COLOR6_VIEW_BASE_IDX', - 'regCB_COLOR7_ATTRIB', 'regCB_COLOR7_ATTRIB2', - 'regCB_COLOR7_ATTRIB2_BASE_IDX', 'regCB_COLOR7_ATTRIB3', - 'regCB_COLOR7_ATTRIB3_BASE_IDX', 'regCB_COLOR7_ATTRIB_BASE_IDX', - 'regCB_COLOR7_BASE', 'regCB_COLOR7_BASE_BASE_IDX', - 'regCB_COLOR7_BASE_EXT', 'regCB_COLOR7_BASE_EXT_BASE_IDX', - 'regCB_COLOR7_DCC_BASE', 'regCB_COLOR7_DCC_BASE_BASE_IDX', - 'regCB_COLOR7_DCC_BASE_EXT', 'regCB_COLOR7_DCC_BASE_EXT_BASE_IDX', - 'regCB_COLOR7_FDCC_CONTROL', 'regCB_COLOR7_FDCC_CONTROL_BASE_IDX', - 'regCB_COLOR7_INFO', 'regCB_COLOR7_INFO_BASE_IDX', - 'regCB_COLOR7_VIEW', 'regCB_COLOR7_VIEW_BASE_IDX', - 'regCB_COLOR_CONTROL', 'regCB_COLOR_CONTROL_BASE_IDX', - 'regCB_COVERAGE_OUT_CONTROL', - 'regCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'regCB_DCC_CONFIG', - 'regCB_DCC_CONFIG2', 'regCB_DCC_CONFIG2_BASE_IDX', - 'regCB_DCC_CONFIG_BASE_IDX', 'regCB_FDCC_CONTROL', - 'regCB_FDCC_CONTROL_BASE_IDX', 'regCB_FGCG_SRAM_OVERRIDE', - 'regCB_FGCG_SRAM_OVERRIDE_BASE_IDX', 'regCB_HW_CONTROL', - 'regCB_HW_CONTROL_1', 'regCB_HW_CONTROL_1_BASE_IDX', - 'regCB_HW_CONTROL_2', 'regCB_HW_CONTROL_2_BASE_IDX', - 'regCB_HW_CONTROL_3', 'regCB_HW_CONTROL_3_BASE_IDX', - 'regCB_HW_CONTROL_4', 'regCB_HW_CONTROL_4_BASE_IDX', - 'regCB_HW_CONTROL_BASE_IDX', 'regCB_HW_MEM_ARBITER_RD', - 'regCB_HW_MEM_ARBITER_RD_BASE_IDX', 'regCB_HW_MEM_ARBITER_WR', - 'regCB_HW_MEM_ARBITER_WR_BASE_IDX', 'regCB_PERFCOUNTER0_HI', - 'regCB_PERFCOUNTER0_HI_BASE_IDX', 'regCB_PERFCOUNTER0_LO', - 'regCB_PERFCOUNTER0_LO_BASE_IDX', 'regCB_PERFCOUNTER0_SELECT', - 'regCB_PERFCOUNTER0_SELECT1', - 'regCB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCB_PERFCOUNTER0_SELECT_BASE_IDX', 'regCB_PERFCOUNTER1_HI', - 'regCB_PERFCOUNTER1_HI_BASE_IDX', 'regCB_PERFCOUNTER1_LO', - 'regCB_PERFCOUNTER1_LO_BASE_IDX', 'regCB_PERFCOUNTER1_SELECT', - 'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI', - 'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO', - 'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT', - 'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI', - 'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO', - 'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT', - 'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER', - 'regCB_PERFCOUNTER_FILTER_BASE_IDX', - 'regCB_RMI_GL2_CACHE_CONTROL', - 'regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'regCB_SHADER_MASK', - 'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK', - 'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG', - 'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG', - 'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SA_UNIT_DISABLE', - 'regCC_GC_SA_UNIT_DISABLE_BASE_IDX', - 'regCC_GC_SHADER_ARRAY_CONFIG', - 'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', - 'regCC_GC_SHADER_RATE_CONFIG', - 'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX', - 'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX', - 'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX', - 'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX', - 'regCC_RMI_REDUNDANCY', 'regCC_RMI_REDUNDANCY_BASE_IDX', - 'regCGTS_TCC_DISABLE', 'regCGTS_TCC_DISABLE_BASE_IDX', - 'regCGTS_USER_TCC_DISABLE', 'regCGTS_USER_TCC_DISABLE_BASE_IDX', - 'regCGTT_CPC_CLK_CTRL', 'regCGTT_CPC_CLK_CTRL_BASE_IDX', - 'regCGTT_CPF_CLK_CTRL', 'regCGTT_CPF_CLK_CTRL_BASE_IDX', - 'regCGTT_CP_CLK_CTRL', 'regCGTT_CP_CLK_CTRL_BASE_IDX', - 'regCGTT_GS_NGG_CLK_CTRL', 'regCGTT_GS_NGG_CLK_CTRL_BASE_IDX', - 'regCGTT_PA_CLK_CTRL', 'regCGTT_PA_CLK_CTRL_BASE_IDX', - 'regCGTT_PH_CLK_CTRL0', 'regCGTT_PH_CLK_CTRL0_BASE_IDX', - 'regCGTT_PH_CLK_CTRL1', 'regCGTT_PH_CLK_CTRL1_BASE_IDX', - 'regCGTT_PH_CLK_CTRL2', 'regCGTT_PH_CLK_CTRL2_BASE_IDX', - 'regCGTT_PH_CLK_CTRL3', 'regCGTT_PH_CLK_CTRL3_BASE_IDX', - 'regCGTT_RLC_CLK_CTRL', 'regCGTT_RLC_CLK_CTRL_BASE_IDX', - 'regCGTT_SC_CLK_CTRL0', 'regCGTT_SC_CLK_CTRL0_BASE_IDX', - 'regCGTT_SC_CLK_CTRL1', 'regCGTT_SC_CLK_CTRL1_BASE_IDX', - 'regCGTT_SC_CLK_CTRL2', 'regCGTT_SC_CLK_CTRL2_BASE_IDX', - 'regCGTT_SC_CLK_CTRL3', 'regCGTT_SC_CLK_CTRL3_BASE_IDX', - 'regCGTT_SC_CLK_CTRL4', 'regCGTT_SC_CLK_CTRL4_BASE_IDX', - 'regCGTT_SQG_CLK_CTRL', 'regCGTT_SQG_CLK_CTRL_BASE_IDX', - 'regCHA_CHC_CREDITS', 'regCHA_CHC_CREDITS_BASE_IDX', - 'regCHA_CLIENT_FREE_DELAY', 'regCHA_CLIENT_FREE_DELAY_BASE_IDX', - 'regCHA_PERFCOUNTER0_HI', 'regCHA_PERFCOUNTER0_HI_BASE_IDX', - 'regCHA_PERFCOUNTER0_LO', 'regCHA_PERFCOUNTER0_LO_BASE_IDX', - 'regCHA_PERFCOUNTER0_SELECT', 'regCHA_PERFCOUNTER0_SELECT1', - 'regCHA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER1_HI', - 'regCHA_PERFCOUNTER1_HI_BASE_IDX', 'regCHA_PERFCOUNTER1_LO', - 'regCHA_PERFCOUNTER1_LO_BASE_IDX', 'regCHA_PERFCOUNTER1_SELECT', - 'regCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER2_HI', - 'regCHA_PERFCOUNTER2_HI_BASE_IDX', 'regCHA_PERFCOUNTER2_LO', - 'regCHA_PERFCOUNTER2_LO_BASE_IDX', 'regCHA_PERFCOUNTER2_SELECT', - 'regCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER3_HI', - 'regCHA_PERFCOUNTER3_HI_BASE_IDX', 'regCHA_PERFCOUNTER3_LO', - 'regCHA_PERFCOUNTER3_LO_BASE_IDX', 'regCHA_PERFCOUNTER3_SELECT', - 'regCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_CTRL', - 'regCHCG_CTRL_BASE_IDX', 'regCHCG_PERFCOUNTER0_HI', - 'regCHCG_PERFCOUNTER0_HI_BASE_IDX', 'regCHCG_PERFCOUNTER0_LO', - 'regCHCG_PERFCOUNTER0_LO_BASE_IDX', 'regCHCG_PERFCOUNTER0_SELECT', - 'regCHCG_PERFCOUNTER0_SELECT1', - 'regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER1_HI', - 'regCHCG_PERFCOUNTER1_HI_BASE_IDX', 'regCHCG_PERFCOUNTER1_LO', - 'regCHCG_PERFCOUNTER1_LO_BASE_IDX', 'regCHCG_PERFCOUNTER1_SELECT', - 'regCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER2_HI', - 'regCHCG_PERFCOUNTER2_HI_BASE_IDX', 'regCHCG_PERFCOUNTER2_LO', - 'regCHCG_PERFCOUNTER2_LO_BASE_IDX', 'regCHCG_PERFCOUNTER2_SELECT', - 'regCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER3_HI', - 'regCHCG_PERFCOUNTER3_HI_BASE_IDX', 'regCHCG_PERFCOUNTER3_LO', - 'regCHCG_PERFCOUNTER3_LO_BASE_IDX', 'regCHCG_PERFCOUNTER3_SELECT', - 'regCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_STATUS', - 'regCHCG_STATUS_BASE_IDX', 'regCHC_CTRL', 'regCHC_CTRL_BASE_IDX', - 'regCHC_PERFCOUNTER0_HI', 'regCHC_PERFCOUNTER0_HI_BASE_IDX', - 'regCHC_PERFCOUNTER0_LO', 'regCHC_PERFCOUNTER0_LO_BASE_IDX', - 'regCHC_PERFCOUNTER0_SELECT', 'regCHC_PERFCOUNTER0_SELECT1', - 'regCHC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER1_HI', - 'regCHC_PERFCOUNTER1_HI_BASE_IDX', 'regCHC_PERFCOUNTER1_LO', - 'regCHC_PERFCOUNTER1_LO_BASE_IDX', 'regCHC_PERFCOUNTER1_SELECT', - 'regCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER2_HI', - 'regCHC_PERFCOUNTER2_HI_BASE_IDX', 'regCHC_PERFCOUNTER2_LO', - 'regCHC_PERFCOUNTER2_LO_BASE_IDX', 'regCHC_PERFCOUNTER2_SELECT', - 'regCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER3_HI', - 'regCHC_PERFCOUNTER3_HI_BASE_IDX', 'regCHC_PERFCOUNTER3_LO', - 'regCHC_PERFCOUNTER3_LO_BASE_IDX', 'regCHC_PERFCOUNTER3_SELECT', - 'regCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHC_STATUS', - 'regCHC_STATUS_BASE_IDX', 'regCHICKEN_BITS', - 'regCHICKEN_BITS_BASE_IDX', 'regCHI_CHR_MGCG_OVERRIDE', - 'regCHI_CHR_MGCG_OVERRIDE_BASE_IDX', - 'regCHI_CHR_REP_FGCG_OVERRIDE', - 'regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX', 'regCH_ARB_CTRL', - 'regCH_ARB_CTRL_BASE_IDX', 'regCH_ARB_STATUS', - 'regCH_ARB_STATUS_BASE_IDX', 'regCH_DRAM_BURST_CTRL', - 'regCH_DRAM_BURST_CTRL_BASE_IDX', 'regCH_DRAM_BURST_MASK', - 'regCH_DRAM_BURST_MASK_BASE_IDX', 'regCH_PIPE_STEER', - 'regCH_PIPE_STEER_BASE_IDX', 'regCH_VC5_ENABLE', - 'regCH_VC5_ENABLE_BASE_IDX', 'regCOHER_DEST_BASE_0', - 'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1', - 'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2', - 'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3', - 'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0', - 'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1', - 'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2', - 'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3', - 'regCOHER_DEST_BASE_HI_3_BASE_IDX', 'regCOMPUTE_DDID_INDEX', - 'regCOMPUTE_DDID_INDEX_BASE_IDX', 'regCOMPUTE_DESTINATION_EN_SE0', - 'regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE1', - 'regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE2', - 'regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE3', - 'regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'regCOMPUTE_DIM_X', - 'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y', - 'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z', - 'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END', - 'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID', - 'regCOMPUTE_DISPATCH_ID_BASE_IDX', - 'regCOMPUTE_DISPATCH_INITIATOR', - 'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', - 'regCOMPUTE_DISPATCH_INTERLEAVE', - 'regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX', - 'regCOMPUTE_DISPATCH_PKT_ADDR_HI', - 'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', - 'regCOMPUTE_DISPATCH_PKT_ADDR_LO', - 'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', - 'regCOMPUTE_DISPATCH_TUNNEL', - 'regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', 'regCOMPUTE_MISC_RESERVED', - 'regCOMPUTE_MISC_RESERVED_BASE_IDX', 'regCOMPUTE_NOWHERE', - 'regCOMPUTE_NOWHERE_BASE_IDX', 'regCOMPUTE_NUM_THREAD_X', - 'regCOMPUTE_NUM_THREAD_X_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Y', - 'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Z', - 'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', 'regCOMPUTE_PERFCOUNT_ENABLE', - 'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI', - 'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO', - 'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1', - 'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2', - 'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3', - 'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE', - 'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH', - 'regCOMPUTE_RELAUNCH2', 'regCOMPUTE_RELAUNCH2_BASE_IDX', - 'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_REQ_CTRL', - 'regCOMPUTE_REQ_CTRL_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS', - 'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X', - 'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y', - 'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z', - 'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM', - 'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X', - 'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y', - 'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z', - 'regCOMPUTE_START_Z_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE0', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE1', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE2', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE3', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE4', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE5', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE6', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE7', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX', - 'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX', - 'regCOMPUTE_THREAD_TRACE_ENABLE', - 'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', - 'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_0', 'regCOMPUTE_USER_ACCUM_0_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_1', 'regCOMPUTE_USER_ACCUM_1_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_2', 'regCOMPUTE_USER_ACCUM_2_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_3', 'regCOMPUTE_USER_ACCUM_3_BASE_IDX', - 'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX', - 'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10', - 'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11', - 'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12', - 'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13', - 'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14', - 'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15', - 'regCOMPUTE_USER_DATA_15_BASE_IDX', - 'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2', - 'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3', - 'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4', - 'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5', - 'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6', - 'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7', - 'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8', - 'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9', - 'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID', - 'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI', - 'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', - 'regCOMPUTE_WAVE_RESTORE_ADDR_LO', - 'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', - 'regCONFIG_RESERVED_REG0', 'regCONFIG_RESERVED_REG0_BASE_IDX', - 'regCONFIG_RESERVED_REG1', 'regCONFIG_RESERVED_REG1_BASE_IDX', - 'regCONTEXT_RESERVED_REG0', 'regCONTEXT_RESERVED_REG0_BASE_IDX', - 'regCONTEXT_RESERVED_REG1', 'regCONTEXT_RESERVED_REG1_BASE_IDX', - 'regCPC_DDID_BASE_ADDR_HI', 'regCPC_DDID_BASE_ADDR_HI_BASE_IDX', - 'regCPC_DDID_BASE_ADDR_LO', 'regCPC_DDID_BASE_ADDR_LO_BASE_IDX', - 'regCPC_DDID_CNTL', 'regCPC_DDID_CNTL_BASE_IDX', - 'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL', - 'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID', - 'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO', - 'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID', - 'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS', - 'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA', - 'regCPC_LATENCY_STATS_DATA_BASE_IDX', - 'regCPC_LATENCY_STATS_SELECT', - 'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_OS_PIPES', - 'regCPC_OS_PIPES_BASE_IDX', 'regCPC_PERFCOUNTER0_HI', - 'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO', - 'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT', - 'regCPC_PERFCOUNTER0_SELECT1', - 'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI', - 'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO', - 'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT', - 'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG', - 'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_SUSPEND_CNTL_STACK_OFFSET', - 'regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'regCPC_SUSPEND_CNTL_STACK_SIZE', - 'regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_CONTROL', - 'regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_SIZE', - 'regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX', - 'regCPC_SUSPEND_WG_STATE_OFFSET', - 'regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', - 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPC_UTCL1_CNTL', 'regCPC_UTCL1_CNTL_BASE_IDX', - 'regCPC_UTCL1_ERROR', 'regCPC_UTCL1_ERROR_BASE_IDX', - 'regCPC_UTCL1_STATUS', 'regCPC_UTCL1_STATUS_BASE_IDX', - 'regCPF_GCR_CNTL', 'regCPF_GCR_CNTL_BASE_IDX', - 'regCPF_LATENCY_STATS_DATA', 'regCPF_LATENCY_STATS_DATA_BASE_IDX', - 'regCPF_LATENCY_STATS_SELECT', - 'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI', - 'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO', - 'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT', - 'regCPF_PERFCOUNTER0_SELECT1', - 'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI', - 'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO', - 'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT', - 'regCPF_PERFCOUNTER1_SELECT_BASE_IDX', - 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX', - 'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX', - 'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX', - 'regCPG_LATENCY_STATS_SELECT', - 'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI', - 'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO', - 'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT', - 'regCPG_PERFCOUNTER0_SELECT1', - 'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI', - 'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO', - 'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT', - 'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG', - 'regCPG_PSP_DEBUG_BASE_IDX', 'regCPG_RCIU_CAM_DATA', - 'regCPG_RCIU_CAM_DATA_BASE_IDX', 'regCPG_RCIU_CAM_DATA_PHASE0', - 'regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX', - 'regCPG_RCIU_CAM_DATA_PHASE1', - 'regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX', - 'regCPG_RCIU_CAM_DATA_PHASE2', - 'regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'regCPG_RCIU_CAM_INDEX', - 'regCPG_RCIU_CAM_INDEX_BASE_IDX', - 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX', - 'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX', - 'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX', - 'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX', - 'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX', - 'regCP_APPEND_CMD_ADDR_HI', 'regCP_APPEND_CMD_ADDR_HI_BASE_IDX', - 'regCP_APPEND_CMD_ADDR_LO', 'regCP_APPEND_CMD_ADDR_LO_BASE_IDX', - 'regCP_APPEND_DATA', 'regCP_APPEND_DATA_BASE_IDX', - 'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX', - 'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX', - 'regCP_APPEND_DDID_CNT', 'regCP_APPEND_DDID_CNT_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE', - 'regCP_APPEND_LAST_CS_FENCE_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE_HI', - 'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE_LO', - 'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE', - 'regCP_APPEND_LAST_PS_FENCE_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE_HI', - 'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE_LO', - 'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS', - 'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI', - 'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO', - 'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT', - 'regCP_BUSY_STAT_BASE_IDX', 'regCP_CMD_DATA', - 'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX', - 'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT', - 'regCP_CNTX_STAT_BASE_IDX', 'regCP_CONTEXT_CNTL', - 'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_HYSTERESIS', - 'regCP_CPC_BUSY_HYSTERESIS_BASE_IDX', 'regCP_CPC_BUSY_STAT', - 'regCP_CPC_BUSY_STAT2', 'regCP_CPC_BUSY_STAT2_BASE_IDX', - 'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG', - 'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL', - 'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DEBUG_DATA', - 'regCP_CPC_DEBUG_DATA_BASE_IDX', 'regCP_CPC_GFX_CNTL', - 'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT', - 'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT', - 'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL', - 'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI', - 'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO', - 'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL', - 'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL', - 'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', - 'regCP_CPC_PRIV_VIOLATION_ADDR', - 'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', - 'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX', - 'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX', - 'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX', - 'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX', - 'regCP_CPF_BUSY_HYSTERESIS1', - 'regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX', - 'regCP_CPF_BUSY_HYSTERESIS2', - 'regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CPF_BUSY_STAT', - 'regCP_CPF_BUSY_STAT2', 'regCP_CPF_BUSY_STAT2_BASE_IDX', - 'regCP_CPF_BUSY_STAT_BASE_IDX', 'regCP_CPF_GRBM_FREE_COUNT', - 'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPF_STALLED_STAT1', - 'regCP_CPF_STALLED_STAT1_BASE_IDX', 'regCP_CPF_STATUS', - 'regCP_CPF_STATUS_BASE_IDX', 'regCP_CPG_BUSY_HYSTERESIS1', - 'regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX', - 'regCP_CPG_BUSY_HYSTERESIS2', - 'regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CSF_STAT', - 'regCP_CSF_STAT_BASE_IDX', 'regCP_CU_MASK_ADDR_HI', - 'regCP_CU_MASK_ADDR_HI_BASE_IDX', 'regCP_CU_MASK_ADDR_LO', - 'regCP_CU_MASK_ADDR_LO_BASE_IDX', 'regCP_CU_MASK_CNTL', - 'regCP_CU_MASK_CNTL_BASE_IDX', 'regCP_DB_BASE_HI', - 'regCP_DB_BASE_HI_BASE_IDX', 'regCP_DB_BASE_LO', - 'regCP_DB_BASE_LO_BASE_IDX', 'regCP_DB_BUFSZ', - 'regCP_DB_BUFSZ_BASE_IDX', 'regCP_DB_CMD_BUFSZ', - 'regCP_DB_CMD_BUFSZ_BASE_IDX', 'regCP_DDID_BASE_ADDR_HI', - 'regCP_DDID_BASE_ADDR_HI_BASE_IDX', 'regCP_DDID_BASE_ADDR_LO', - 'regCP_DDID_BASE_ADDR_LO_BASE_IDX', 'regCP_DDID_CNTL', - 'regCP_DDID_CNTL_BASE_IDX', 'regCP_DEBUG', 'regCP_DEBUG_2', - 'regCP_DEBUG_2_BASE_IDX', 'regCP_DEBUG_BASE_IDX', - 'regCP_DEBUG_CNTL', 'regCP_DEBUG_CNTL_BASE_IDX', - 'regCP_DEBUG_DATA', 'regCP_DEBUG_DATA_BASE_IDX', - 'regCP_DEVICE_ID', 'regCP_DEVICE_ID_BASE_IDX', - 'regCP_DISPATCH_INDR_ADDR', 'regCP_DISPATCH_INDR_ADDR_BASE_IDX', - 'regCP_DISPATCH_INDR_ADDR_HI', - 'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL', - 'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_HI', - 'regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_LO', - 'regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_ME_COMMAND', - 'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL', - 'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR', - 'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI', - 'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR', - 'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI', - 'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_HI', - 'regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_LO', - 'regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_PFP_COMMAND', - 'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL', - 'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR', - 'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI', - 'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR', - 'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI', - 'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS', - 'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_HI', - 'regCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_LO', - 'regCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH0_CNTL', - 'regCP_DMA_WATCH0_CNTL_BASE_IDX', 'regCP_DMA_WATCH0_MASK', - 'regCP_DMA_WATCH0_MASK_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_HI', - 'regCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_LO', - 'regCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH1_CNTL', - 'regCP_DMA_WATCH1_CNTL_BASE_IDX', 'regCP_DMA_WATCH1_MASK', - 'regCP_DMA_WATCH1_MASK_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_HI', - 'regCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_LO', - 'regCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH2_CNTL', - 'regCP_DMA_WATCH2_CNTL_BASE_IDX', 'regCP_DMA_WATCH2_MASK', - 'regCP_DMA_WATCH2_MASK_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_HI', - 'regCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_LO', - 'regCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH3_CNTL', - 'regCP_DMA_WATCH3_CNTL_BASE_IDX', 'regCP_DMA_WATCH3_MASK', - 'regCP_DMA_WATCH3_MASK_BASE_IDX', 'regCP_DMA_WATCH_STAT', - 'regCP_DMA_WATCH_STAT_ADDR_HI', - 'regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX', - 'regCP_DMA_WATCH_STAT_ADDR_LO', - 'regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX', - 'regCP_DMA_WATCH_STAT_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR', - 'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX', - 'regCP_DRAW_INDX_INDR_ADDR_HI', - 'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT', - 'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER', - 'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL', - 'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI', - 'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO', - 'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI', - 'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'regCP_ECC_FIRSTOCCURRENCE', - 'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX', - 'regCP_ECC_FIRSTOCCURRENCE_RING0', - 'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', - 'regCP_ECC_FIRSTOCCURRENCE_RING1', - 'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', - 'regCP_EOPQ_WAIT_TIME', 'regCP_EOPQ_WAIT_TIME_BASE_IDX', - 'regCP_EOP_DONE_ADDR_HI', 'regCP_EOP_DONE_ADDR_HI_BASE_IDX', - 'regCP_EOP_DONE_ADDR_LO', 'regCP_EOP_DONE_ADDR_LO_BASE_IDX', - 'regCP_EOP_DONE_CNTX_ID', 'regCP_EOP_DONE_CNTX_ID_BASE_IDX', - 'regCP_EOP_DONE_DATA_CNTL', 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX', - 'regCP_EOP_DONE_DATA_HI', 'regCP_EOP_DONE_DATA_HI_BASE_IDX', - 'regCP_EOP_DONE_DATA_LO', 'regCP_EOP_DONE_DATA_LO_BASE_IDX', - 'regCP_EOP_DONE_EVENT_CNTL', 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX', - 'regCP_EOP_LAST_FENCE_HI', 'regCP_EOP_LAST_FENCE_HI_BASE_IDX', - 'regCP_EOP_LAST_FENCE_LO', 'regCP_EOP_LAST_FENCE_LO_BASE_IDX', - 'regCP_FATAL_ERROR', 'regCP_FATAL_ERROR_BASE_IDX', - 'regCP_FETCHER_SOURCE', 'regCP_FETCHER_SOURCE_BASE_IDX', - 'regCP_GDS_ATOMIC0_PREOP_HI', - 'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_GDS_ATOMIC0_PREOP_LO', - 'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_GDS_ATOMIC1_PREOP_HI', - 'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_GDS_ATOMIC1_PREOP_LO', - 'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR', - 'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI', - 'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_HI', - 'regCP_GE_MSINVOC_COUNT_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_LO', - 'regCP_GE_MSINVOC_COUNT_LO_BASE_IDX', 'regCP_GFX_CNTL', - 'regCP_GFX_CNTL_BASE_IDX', 'regCP_GFX_DDID_DELTA_RPT_COUNT', - 'regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'regCP_GFX_DDID_INFLIGHT_COUNT', - 'regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_GFX_DDID_RPTR', - 'regCP_GFX_DDID_RPTR_BASE_IDX', 'regCP_GFX_DDID_WPTR', - 'regCP_GFX_DDID_WPTR_BASE_IDX', 'regCP_GFX_ERROR', - 'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_HPD_CONTROL0', - 'regCP_GFX_HPD_CONTROL0_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX', - 'regCP_GFX_HPD_STATUS0', 'regCP_GFX_HPD_STATUS0_BASE_IDX', - 'regCP_GFX_HQD_ACTIVE', 'regCP_GFX_HQD_ACTIVE_BASE_IDX', - 'regCP_GFX_HQD_BASE', 'regCP_GFX_HQD_BASE_BASE_IDX', - 'regCP_GFX_HQD_BASE_HI', 'regCP_GFX_HQD_BASE_HI_BASE_IDX', - 'regCP_GFX_HQD_CNTL', 'regCP_GFX_HQD_CNTL_BASE_IDX', - 'regCP_GFX_HQD_CSMD_RPTR', 'regCP_GFX_HQD_CSMD_RPTR_BASE_IDX', - 'regCP_GFX_HQD_DEQUEUE_REQUEST', - 'regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX', - 'regCP_GFX_HQD_HQ_CONTROL0', 'regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX', - 'regCP_GFX_HQD_HQ_STATUS0', 'regCP_GFX_HQD_HQ_STATUS0_BASE_IDX', - 'regCP_GFX_HQD_IQ_TIMER', 'regCP_GFX_HQD_IQ_TIMER_BASE_IDX', - 'regCP_GFX_HQD_MAPPED', 'regCP_GFX_HQD_MAPPED_BASE_IDX', - 'regCP_GFX_HQD_OFFSET', 'regCP_GFX_HQD_OFFSET_BASE_IDX', - 'regCP_GFX_HQD_QUANTUM', 'regCP_GFX_HQD_QUANTUM_BASE_IDX', - 'regCP_GFX_HQD_QUEUE_PRIORITY', - 'regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX', - 'regCP_GFX_HQD_QUE_MGR_CONTROL', - 'regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'regCP_GFX_HQD_RPTR', - 'regCP_GFX_HQD_RPTR_ADDR', 'regCP_GFX_HQD_RPTR_ADDR_BASE_IDX', - 'regCP_GFX_HQD_RPTR_ADDR_HI', - 'regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX', - 'regCP_GFX_HQD_RPTR_BASE_IDX', 'regCP_GFX_HQD_VMID', - 'regCP_GFX_HQD_VMID_BASE_IDX', 'regCP_GFX_HQD_WPTR', - 'regCP_GFX_HQD_WPTR_BASE_IDX', 'regCP_GFX_HQD_WPTR_HI', - 'regCP_GFX_HQD_WPTR_HI_BASE_IDX', 'regCP_GFX_INDEX_MUTEX', - 'regCP_GFX_INDEX_MUTEX_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR', - 'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI', - 'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL', - 'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GFX_QUEUE_INDEX', - 'regCP_GFX_QUEUE_INDEX_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_BASE0', - 'regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_BASE1', - 'regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_MASK0', - 'regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_MASK1', - 'regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_BASE0', - 'regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_BASE1', - 'regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_MASK0', - 'regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_MASK1', - 'regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_BASE0', - 'regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_BASE1', - 'regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_MASK0', - 'regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_MASK1', - 'regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_BASE0', - 'regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_BASE1', - 'regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_MASK0', - 'regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_MASK1', - 'regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_BASE0', - 'regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_BASE1', - 'regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_MASK0', - 'regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_MASK1', - 'regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_BASE0', - 'regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_BASE1', - 'regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_MASK0', - 'regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_MASK1', - 'regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_BASE0', - 'regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_BASE1', - 'regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_MASK0', - 'regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_MASK1', - 'regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_BASE0', - 'regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_BASE1', - 'regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_MASK0', - 'regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_MASK1', - 'regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_BASE0', - 'regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_BASE1', - 'regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_MASK0', - 'regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_MASK1', - 'regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_BASE0', - 'regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_BASE1', - 'regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_MASK0', - 'regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_MASK1', - 'regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_BASE0', - 'regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_BASE1', - 'regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_MASK0', - 'regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_MASK1', - 'regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_BASE0', - 'regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_BASE1', - 'regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_MASK0', - 'regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_MASK1', - 'regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_BASE0', - 'regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_BASE1', - 'regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_MASK0', - 'regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_MASK1', - 'regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_BASE0', - 'regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_BASE1', - 'regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_MASK0', - 'regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_MASK1', - 'regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_BASE0', - 'regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_BASE1', - 'regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_MASK0', - 'regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_MASK1', - 'regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_BASE0', - 'regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_BASE1', - 'regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_MASK0', - 'regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_MASK1', - 'regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE0_HI', - 'regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE0_LO', - 'regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE1_HI', - 'regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE1_LO', - 'regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE_CNTL', - 'regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX', - 'regCP_GFX_RS64_DC_OP_CNTL', 'regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX', - 'regCP_GFX_RS64_DM_INDEX_ADDR', - 'regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX', - 'regCP_GFX_RS64_DM_INDEX_DATA', - 'regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX', 'regCP_GFX_RS64_GP0_HI0', - 'regCP_GFX_RS64_GP0_HI0_BASE_IDX', 'regCP_GFX_RS64_GP0_HI1', - 'regCP_GFX_RS64_GP0_HI1_BASE_IDX', 'regCP_GFX_RS64_GP0_LO0', - 'regCP_GFX_RS64_GP0_LO0_BASE_IDX', 'regCP_GFX_RS64_GP0_LO1', - 'regCP_GFX_RS64_GP0_LO1_BASE_IDX', 'regCP_GFX_RS64_GP1_HI0', - 'regCP_GFX_RS64_GP1_HI0_BASE_IDX', 'regCP_GFX_RS64_GP1_HI1', - 'regCP_GFX_RS64_GP1_HI1_BASE_IDX', 'regCP_GFX_RS64_GP1_LO0', - 'regCP_GFX_RS64_GP1_LO0_BASE_IDX', 'regCP_GFX_RS64_GP1_LO1', - 'regCP_GFX_RS64_GP1_LO1_BASE_IDX', 'regCP_GFX_RS64_GP2_HI0', - 'regCP_GFX_RS64_GP2_HI0_BASE_IDX', 'regCP_GFX_RS64_GP2_HI1', - 'regCP_GFX_RS64_GP2_HI1_BASE_IDX', 'regCP_GFX_RS64_GP2_LO0', - 'regCP_GFX_RS64_GP2_LO0_BASE_IDX', 'regCP_GFX_RS64_GP2_LO1', - 'regCP_GFX_RS64_GP2_LO1_BASE_IDX', 'regCP_GFX_RS64_GP3_HI0', - 'regCP_GFX_RS64_GP3_HI0_BASE_IDX', 'regCP_GFX_RS64_GP3_HI1', - 'regCP_GFX_RS64_GP3_HI1_BASE_IDX', 'regCP_GFX_RS64_GP3_LO0', - 'regCP_GFX_RS64_GP3_LO0_BASE_IDX', 'regCP_GFX_RS64_GP3_LO1', - 'regCP_GFX_RS64_GP3_LO1_BASE_IDX', 'regCP_GFX_RS64_GP4_HI0', - 'regCP_GFX_RS64_GP4_HI0_BASE_IDX', 'regCP_GFX_RS64_GP4_HI1', - 'regCP_GFX_RS64_GP4_HI1_BASE_IDX', 'regCP_GFX_RS64_GP4_LO0', - 'regCP_GFX_RS64_GP4_LO0_BASE_IDX', 'regCP_GFX_RS64_GP4_LO1', - 'regCP_GFX_RS64_GP4_LO1_BASE_IDX', 'regCP_GFX_RS64_GP5_HI0', - 'regCP_GFX_RS64_GP5_HI0_BASE_IDX', 'regCP_GFX_RS64_GP5_HI1', - 'regCP_GFX_RS64_GP5_HI1_BASE_IDX', 'regCP_GFX_RS64_GP5_LO0', - 'regCP_GFX_RS64_GP5_LO0_BASE_IDX', 'regCP_GFX_RS64_GP5_LO1', - 'regCP_GFX_RS64_GP5_LO1_BASE_IDX', 'regCP_GFX_RS64_GP6_HI', - 'regCP_GFX_RS64_GP6_HI_BASE_IDX', 'regCP_GFX_RS64_GP6_LO', - 'regCP_GFX_RS64_GP6_LO_BASE_IDX', 'regCP_GFX_RS64_GP7_HI', - 'regCP_GFX_RS64_GP7_HI_BASE_IDX', 'regCP_GFX_RS64_GP7_LO', - 'regCP_GFX_RS64_GP7_LO_BASE_IDX', 'regCP_GFX_RS64_GP8_HI', - 'regCP_GFX_RS64_GP8_HI_BASE_IDX', 'regCP_GFX_RS64_GP8_LO', - 'regCP_GFX_RS64_GP8_LO_BASE_IDX', 'regCP_GFX_RS64_GP9_HI', - 'regCP_GFX_RS64_GP9_HI_BASE_IDX', 'regCP_GFX_RS64_GP9_LO', - 'regCP_GFX_RS64_GP9_LO_BASE_IDX', 'regCP_GFX_RS64_INSTR_PNTR0', - 'regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX', - 'regCP_GFX_RS64_INSTR_PNTR1', - 'regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX', - 'regCP_GFX_RS64_INTERRUPT0', 'regCP_GFX_RS64_INTERRUPT0_BASE_IDX', - 'regCP_GFX_RS64_INTERRUPT1', 'regCP_GFX_RS64_INTERRUPT1_BASE_IDX', - 'regCP_GFX_RS64_INTR_EN0', 'regCP_GFX_RS64_INTR_EN0_BASE_IDX', - 'regCP_GFX_RS64_INTR_EN1', 'regCP_GFX_RS64_INTR_EN1_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_APERTURE', - 'regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_BASE0_HI', - 'regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_BASE0_LO', - 'regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE', - 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_MASK0_HI', - 'regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_MASK0_LO', - 'regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE', - 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX', - 'regCP_GFX_RS64_MIBOUND_HI', 'regCP_GFX_RS64_MIBOUND_HI_BASE_IDX', - 'regCP_GFX_RS64_MIBOUND_LO', 'regCP_GFX_RS64_MIBOUND_LO_BASE_IDX', - 'regCP_GFX_RS64_MIP_HI0', 'regCP_GFX_RS64_MIP_HI0_BASE_IDX', - 'regCP_GFX_RS64_MIP_HI1', 'regCP_GFX_RS64_MIP_HI1_BASE_IDX', - 'regCP_GFX_RS64_MIP_LO0', 'regCP_GFX_RS64_MIP_LO0_BASE_IDX', - 'regCP_GFX_RS64_MIP_LO1', 'regCP_GFX_RS64_MIP_LO1_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_HI0', - 'regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_HI1', - 'regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_LO0', - 'regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_LO1', - 'regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX', - 'regCP_GFX_RS64_PENDING_INTERRUPT0', - 'regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX', - 'regCP_GFX_RS64_PENDING_INTERRUPT1', - 'regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX', - 'regCP_GFX_RS64_PERFCOUNT_CNTL0', - 'regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_PERFCOUNT_CNTL1', - 'regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX', - 'regCP_GPU_TIMESTAMP_OFFSET_HI', - 'regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX', - 'regCP_GPU_TIMESTAMP_OFFSET_LO', - 'regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'regCP_GRBM_FREE_COUNT', - 'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_MES_ROQ_OFFSETS', - 'regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS', - 'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0', - 'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL', - 'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR', - 'regCP_HPD_UTCL1_ERROR_ADDR', - 'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', - 'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE', - 'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL', - 'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_ATOMIC0_PREOP_HI', - 'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_HQD_ATOMIC0_PREOP_LO', - 'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_HQD_ATOMIC1_PREOP_HI', - 'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_HQD_ATOMIC1_PREOP_LO', - 'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', - 'regCP_HQD_CNTL_STACK_OFFSET', - 'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', - 'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'regCP_HQD_CTX_SAVE_CONTROL', - 'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE', - 'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX', - 'regCP_HQD_DDID_DELTA_RPT_COUNT', - 'regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'regCP_HQD_DDID_INFLIGHT_COUNT', - 'regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_HQD_DDID_RPTR', - 'regCP_HQD_DDID_RPTR_BASE_IDX', 'regCP_HQD_DDID_WPTR', - 'regCP_HQD_DDID_WPTR_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST', - 'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DEQUEUE_STATUS', - 'regCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD', - 'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR', - 'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI', - 'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL', - 'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS', - 'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR', - 'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR', - 'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM', - 'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR', - 'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE', - 'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL', - 'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS', - 'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0', - 'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1', - 'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0', - 'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1', - 'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0', - 'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1', - 'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR', - 'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI', - 'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL', - 'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR', - 'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR', - 'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER', - 'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE', - 'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD', - 'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE', - 'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY', - 'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE', - 'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI', - 'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL', - 'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL', - 'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR', - 'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', - 'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX', - 'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX', - 'regCP_HQD_PQ_WPTR_POLL_ADDR', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM', - 'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY', - 'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD', - 'regCP_HQD_SEMA_CMD_BASE_IDX', - 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT', - 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX', - 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET', - 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'regCP_HQD_SUSPEND_WG_STATE_OFFSET', - 'regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'regCP_HQD_VMID', - 'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET', - 'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR', - 'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA', - 'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR', - 'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA', - 'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'regCP_HYP_ME_UCODE_ADDR', - 'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'regCP_HYP_ME_UCODE_DATA', - 'regCP_HYP_ME_UCODE_DATA_BASE_IDX', 'regCP_HYP_PFP_UCODE_ADDR', - 'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA', - 'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_IB1_BASE_HI', - 'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO', - 'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ', - 'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ', - 'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_BASE_HI', - 'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO', - 'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ', - 'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ', - 'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET', - 'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN', - 'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END', - 'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR', - 'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI', - 'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE', - 'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL', - 'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0', - 'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1', - 'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_STATUS', - 'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0', - 'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1', - 'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_IQ_WAIT_TIME1', - 'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2', - 'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_IQ_WAIT_TIME3', - 'regCP_IQ_WAIT_TIME3_BASE_IDX', 'regCP_MAX_CONTEXT', - 'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_MAX_DRAW_COUNT', - 'regCP_MAX_DRAW_COUNT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY', - 'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID', - 'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY', - 'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID', - 'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE_PRIORITY_CNTS', - 'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX', - 'regCP_ME1_PIPE0_INT_STATUS', - 'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY', - 'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL', - 'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS', - 'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY', - 'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL', - 'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS', - 'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY', - 'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL', - 'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS', - 'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY', - 'regCP_ME1_PIPE3_PRIORITY_BASE_IDX', - 'regCP_ME1_PIPE_PRIORITY_CNTS', - 'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX', - 'regCP_ME2_PIPE0_INT_STATUS', - 'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY', - 'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL', - 'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS', - 'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY', - 'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL', - 'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS', - 'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY', - 'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL', - 'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS', - 'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY', - 'regCP_ME2_PIPE3_PRIORITY_BASE_IDX', - 'regCP_ME2_PIPE_PRIORITY_CNTS', - 'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX', - 'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX', - 'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX', - 'regCP_MEC1_INTR_ROUTINE_START', - 'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MEC1_PRGRM_CNTR_START', - 'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX', - 'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX', - 'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX', - 'regCP_MEC2_INTR_ROUTINE_START', - 'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MEC2_PRGRM_CNTR_START', - 'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL', - 'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DC_APERTURE0_BASE', - 'regCP_MEC_DC_APERTURE0_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE0_CNTL', - 'regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE0_MASK', - 'regCP_MEC_DC_APERTURE0_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_BASE', - 'regCP_MEC_DC_APERTURE10_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_CNTL', - 'regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_MASK', - 'regCP_MEC_DC_APERTURE10_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_BASE', - 'regCP_MEC_DC_APERTURE11_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_CNTL', - 'regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_MASK', - 'regCP_MEC_DC_APERTURE11_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_BASE', - 'regCP_MEC_DC_APERTURE12_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_CNTL', - 'regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_MASK', - 'regCP_MEC_DC_APERTURE12_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_BASE', - 'regCP_MEC_DC_APERTURE13_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_CNTL', - 'regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_MASK', - 'regCP_MEC_DC_APERTURE13_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_BASE', - 'regCP_MEC_DC_APERTURE14_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_CNTL', - 'regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_MASK', - 'regCP_MEC_DC_APERTURE14_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_BASE', - 'regCP_MEC_DC_APERTURE15_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_CNTL', - 'regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_MASK', - 'regCP_MEC_DC_APERTURE15_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_BASE', - 'regCP_MEC_DC_APERTURE1_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_CNTL', - 'regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_MASK', - 'regCP_MEC_DC_APERTURE1_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_BASE', - 'regCP_MEC_DC_APERTURE2_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_CNTL', - 'regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_MASK', - 'regCP_MEC_DC_APERTURE2_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_BASE', - 'regCP_MEC_DC_APERTURE3_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_CNTL', - 'regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_MASK', - 'regCP_MEC_DC_APERTURE3_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_BASE', - 'regCP_MEC_DC_APERTURE4_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_CNTL', - 'regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_MASK', - 'regCP_MEC_DC_APERTURE4_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_BASE', - 'regCP_MEC_DC_APERTURE5_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_CNTL', - 'regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_MASK', - 'regCP_MEC_DC_APERTURE5_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_BASE', - 'regCP_MEC_DC_APERTURE6_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_CNTL', - 'regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_MASK', - 'regCP_MEC_DC_APERTURE6_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_BASE', - 'regCP_MEC_DC_APERTURE7_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_CNTL', - 'regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_MASK', - 'regCP_MEC_DC_APERTURE7_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_BASE', - 'regCP_MEC_DC_APERTURE8_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_CNTL', - 'regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_MASK', - 'regCP_MEC_DC_APERTURE8_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_BASE', - 'regCP_MEC_DC_APERTURE9_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_CNTL', - 'regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_MASK', - 'regCP_MEC_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MEC_DC_BASE_CNTL', - 'regCP_MEC_DC_BASE_CNTL_BASE_IDX', 'regCP_MEC_DC_BASE_HI', - 'regCP_MEC_DC_BASE_HI_BASE_IDX', 'regCP_MEC_DC_BASE_LO', - 'regCP_MEC_DC_BASE_LO_BASE_IDX', 'regCP_MEC_DC_OP_CNTL', - 'regCP_MEC_DC_OP_CNTL_BASE_IDX', 'regCP_MEC_DM_INDEX_ADDR', - 'regCP_MEC_DM_INDEX_ADDR_BASE_IDX', 'regCP_MEC_DM_INDEX_DATA', - 'regCP_MEC_DM_INDEX_DATA_BASE_IDX', - 'regCP_MEC_DOORBELL_RANGE_LOWER', - 'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', - 'regCP_MEC_DOORBELL_RANGE_UPPER', - 'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_MEC_GP0_HI', - 'regCP_MEC_GP0_HI_BASE_IDX', 'regCP_MEC_GP0_LO', - 'regCP_MEC_GP0_LO_BASE_IDX', 'regCP_MEC_GP1_HI', - 'regCP_MEC_GP1_HI_BASE_IDX', 'regCP_MEC_GP1_LO', - 'regCP_MEC_GP1_LO_BASE_IDX', 'regCP_MEC_GP2_HI', - 'regCP_MEC_GP2_HI_BASE_IDX', 'regCP_MEC_GP2_LO', - 'regCP_MEC_GP2_LO_BASE_IDX', 'regCP_MEC_GP3_HI', - 'regCP_MEC_GP3_HI_BASE_IDX', 'regCP_MEC_GP3_LO', - 'regCP_MEC_GP3_LO_BASE_IDX', 'regCP_MEC_GP4_HI', - 'regCP_MEC_GP4_HI_BASE_IDX', 'regCP_MEC_GP4_LO', - 'regCP_MEC_GP4_LO_BASE_IDX', 'regCP_MEC_GP5_HI', - 'regCP_MEC_GP5_HI_BASE_IDX', 'regCP_MEC_GP5_LO', - 'regCP_MEC_GP5_LO_BASE_IDX', 'regCP_MEC_GP6_HI', - 'regCP_MEC_GP6_HI_BASE_IDX', 'regCP_MEC_GP6_LO', - 'regCP_MEC_GP6_LO_BASE_IDX', 'regCP_MEC_GP7_HI', - 'regCP_MEC_GP7_HI_BASE_IDX', 'regCP_MEC_GP7_LO', - 'regCP_MEC_GP7_LO_BASE_IDX', 'regCP_MEC_GP8_HI', - 'regCP_MEC_GP8_HI_BASE_IDX', 'regCP_MEC_GP8_LO', - 'regCP_MEC_GP8_LO_BASE_IDX', 'regCP_MEC_GP9_HI', - 'regCP_MEC_GP9_HI_BASE_IDX', 'regCP_MEC_GP9_LO', - 'regCP_MEC_GP9_LO_BASE_IDX', 'regCP_MEC_ISA_CNTL', - 'regCP_MEC_ISA_CNTL_BASE_IDX', 'regCP_MEC_JT_STAT', - 'regCP_MEC_JT_STAT_BASE_IDX', 'regCP_MEC_LOCAL_APERTURE', - 'regCP_MEC_LOCAL_APERTURE_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_HI', - 'regCP_MEC_LOCAL_BASE0_HI_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_LO', - 'regCP_MEC_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_APERTURE', - 'regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_BASE_HI', - 'regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_BASE_LO', - 'regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_MASK_HI', - 'regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_MASK_LO', - 'regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_MEC_LOCAL_MASK0_HI', 'regCP_MEC_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_MEC_LOCAL_MASK0_LO', 'regCP_MEC_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_APERTURE', - 'regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_BASE_HI', - 'regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_BASE_LO', - 'regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX', 'regCP_MEC_MDBASE_HI', - 'regCP_MEC_MDBASE_HI_BASE_IDX', 'regCP_MEC_MDBASE_LO', - 'regCP_MEC_MDBASE_LO_BASE_IDX', 'regCP_MEC_MDBOUND_HI', - 'regCP_MEC_MDBOUND_HI_BASE_IDX', 'regCP_MEC_MDBOUND_LO', - 'regCP_MEC_MDBOUND_LO_BASE_IDX', 'regCP_MEC_ME1_HEADER_DUMP', - 'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME1_UCODE_ADDR', - 'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME1_UCODE_DATA', - 'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'regCP_MEC_ME2_HEADER_DUMP', - 'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME2_UCODE_ADDR', - 'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME2_UCODE_DATA', - 'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'regCP_MEC_MIBOUND_HI', - 'regCP_MEC_MIBOUND_HI_BASE_IDX', 'regCP_MEC_MIBOUND_LO', - 'regCP_MEC_MIBOUND_LO_BASE_IDX', 'regCP_MEC_MIE_HI', - 'regCP_MEC_MIE_HI_BASE_IDX', 'regCP_MEC_MIE_LO', - 'regCP_MEC_MIE_LO_BASE_IDX', 'regCP_MEC_MIP_HI', - 'regCP_MEC_MIP_HI_BASE_IDX', 'regCP_MEC_MIP_LO', - 'regCP_MEC_MIP_LO_BASE_IDX', 'regCP_MEC_MTIMECMP_HI', - 'regCP_MEC_MTIMECMP_HI_BASE_IDX', 'regCP_MEC_MTIMECMP_LO', - 'regCP_MEC_MTIMECMP_LO_BASE_IDX', 'regCP_MEC_MTVEC_HI', - 'regCP_MEC_MTVEC_HI_BASE_IDX', 'regCP_MEC_MTVEC_LO', - 'regCP_MEC_MTVEC_LO_BASE_IDX', 'regCP_MEC_RS64_CNTL', - 'regCP_MEC_RS64_CNTL_BASE_IDX', 'regCP_MEC_RS64_INSTR_PNTR', - 'regCP_MEC_RS64_INSTR_PNTR_BASE_IDX', 'regCP_MEC_RS64_INTERRUPT', - 'regCP_MEC_RS64_INTERRUPT_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_16', - 'regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_17', - 'regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_18', - 'regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_19', - 'regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_20', - 'regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_21', - 'regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_22', - 'regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_23', - 'regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_24', - 'regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_25', - 'regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_26', - 'regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_27', - 'regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_28', - 'regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_29', - 'regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_30', - 'regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_31', - 'regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX', - 'regCP_MEC_RS64_PENDING_INTERRUPT', - 'regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX', - 'regCP_MEC_RS64_PERFCOUNT_CNTL', - 'regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX', - 'regCP_MEC_RS64_PRGRM_CNTR_START', - 'regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MEC_RS64_PRGRM_CNTR_START_HI', - 'regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_MEQ_AVAIL', - 'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT', - 'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_THRESHOLDS', - 'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_MES_CNTL', - 'regCP_MES_CNTL_BASE_IDX', 'regCP_MES_DC_APERTURE0_BASE', - 'regCP_MES_DC_APERTURE0_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE0_CNTL', - 'regCP_MES_DC_APERTURE0_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE0_MASK', - 'regCP_MES_DC_APERTURE0_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE10_BASE', - 'regCP_MES_DC_APERTURE10_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE10_CNTL', - 'regCP_MES_DC_APERTURE10_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE10_MASK', - 'regCP_MES_DC_APERTURE10_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE11_BASE', - 'regCP_MES_DC_APERTURE11_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE11_CNTL', - 'regCP_MES_DC_APERTURE11_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE11_MASK', - 'regCP_MES_DC_APERTURE11_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE12_BASE', - 'regCP_MES_DC_APERTURE12_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE12_CNTL', - 'regCP_MES_DC_APERTURE12_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE12_MASK', - 'regCP_MES_DC_APERTURE12_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE13_BASE', - 'regCP_MES_DC_APERTURE13_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE13_CNTL', - 'regCP_MES_DC_APERTURE13_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE13_MASK', - 'regCP_MES_DC_APERTURE13_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE14_BASE', - 'regCP_MES_DC_APERTURE14_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE14_CNTL', - 'regCP_MES_DC_APERTURE14_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE14_MASK', - 'regCP_MES_DC_APERTURE14_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE15_BASE', - 'regCP_MES_DC_APERTURE15_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE15_CNTL', - 'regCP_MES_DC_APERTURE15_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE15_MASK', - 'regCP_MES_DC_APERTURE15_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE1_BASE', - 'regCP_MES_DC_APERTURE1_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE1_CNTL', - 'regCP_MES_DC_APERTURE1_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE1_MASK', - 'regCP_MES_DC_APERTURE1_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE2_BASE', - 'regCP_MES_DC_APERTURE2_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE2_CNTL', - 'regCP_MES_DC_APERTURE2_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE2_MASK', - 'regCP_MES_DC_APERTURE2_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE3_BASE', - 'regCP_MES_DC_APERTURE3_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE3_CNTL', - 'regCP_MES_DC_APERTURE3_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE3_MASK', - 'regCP_MES_DC_APERTURE3_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE4_BASE', - 'regCP_MES_DC_APERTURE4_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE4_CNTL', - 'regCP_MES_DC_APERTURE4_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE4_MASK', - 'regCP_MES_DC_APERTURE4_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE5_BASE', - 'regCP_MES_DC_APERTURE5_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE5_CNTL', - 'regCP_MES_DC_APERTURE5_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE5_MASK', - 'regCP_MES_DC_APERTURE5_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE6_BASE', - 'regCP_MES_DC_APERTURE6_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE6_CNTL', - 'regCP_MES_DC_APERTURE6_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE6_MASK', - 'regCP_MES_DC_APERTURE6_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE7_BASE', - 'regCP_MES_DC_APERTURE7_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE7_CNTL', - 'regCP_MES_DC_APERTURE7_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE7_MASK', - 'regCP_MES_DC_APERTURE7_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE8_BASE', - 'regCP_MES_DC_APERTURE8_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE8_CNTL', - 'regCP_MES_DC_APERTURE8_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE8_MASK', - 'regCP_MES_DC_APERTURE8_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE9_BASE', - 'regCP_MES_DC_APERTURE9_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE9_CNTL', - 'regCP_MES_DC_APERTURE9_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE9_MASK', - 'regCP_MES_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MES_DC_BASE_CNTL', - 'regCP_MES_DC_BASE_CNTL_BASE_IDX', 'regCP_MES_DC_BASE_HI', - 'regCP_MES_DC_BASE_HI_BASE_IDX', 'regCP_MES_DC_BASE_LO', - 'regCP_MES_DC_BASE_LO_BASE_IDX', 'regCP_MES_DC_OP_CNTL', - 'regCP_MES_DC_OP_CNTL_BASE_IDX', - 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR', - 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX', - 'regCP_MES_DM_INDEX_ADDR', 'regCP_MES_DM_INDEX_ADDR_BASE_IDX', - 'regCP_MES_DM_INDEX_DATA', 'regCP_MES_DM_INDEX_DATA_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL1', - 'regCP_MES_DOORBELL_CONTROL1_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL2', - 'regCP_MES_DOORBELL_CONTROL2_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL3', - 'regCP_MES_DOORBELL_CONTROL3_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL4', - 'regCP_MES_DOORBELL_CONTROL4_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL5', - 'regCP_MES_DOORBELL_CONTROL5_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL6', - 'regCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'regCP_MES_GP0_HI', - 'regCP_MES_GP0_HI_BASE_IDX', 'regCP_MES_GP0_LO', - 'regCP_MES_GP0_LO_BASE_IDX', 'regCP_MES_GP1_HI', - 'regCP_MES_GP1_HI_BASE_IDX', 'regCP_MES_GP1_LO', - 'regCP_MES_GP1_LO_BASE_IDX', 'regCP_MES_GP2_HI', - 'regCP_MES_GP2_HI_BASE_IDX', 'regCP_MES_GP2_LO', - 'regCP_MES_GP2_LO_BASE_IDX', 'regCP_MES_GP3_HI', - 'regCP_MES_GP3_HI_BASE_IDX', 'regCP_MES_GP3_LO', - 'regCP_MES_GP3_LO_BASE_IDX', 'regCP_MES_GP4_HI', - 'regCP_MES_GP4_HI_BASE_IDX', 'regCP_MES_GP4_LO', - 'regCP_MES_GP4_LO_BASE_IDX', 'regCP_MES_GP5_HI', - 'regCP_MES_GP5_HI_BASE_IDX', 'regCP_MES_GP5_LO', - 'regCP_MES_GP5_LO_BASE_IDX', 'regCP_MES_GP6_HI', - 'regCP_MES_GP6_HI_BASE_IDX', 'regCP_MES_GP6_LO', - 'regCP_MES_GP6_LO_BASE_IDX', 'regCP_MES_GP7_HI', - 'regCP_MES_GP7_HI_BASE_IDX', 'regCP_MES_GP7_LO', - 'regCP_MES_GP7_LO_BASE_IDX', 'regCP_MES_GP8_HI', - 'regCP_MES_GP8_HI_BASE_IDX', 'regCP_MES_GP8_LO', - 'regCP_MES_GP8_LO_BASE_IDX', 'regCP_MES_GP9_HI', - 'regCP_MES_GP9_HI_BASE_IDX', 'regCP_MES_GP9_LO', - 'regCP_MES_GP9_LO_BASE_IDX', 'regCP_MES_HEADER_DUMP', - 'regCP_MES_HEADER_DUMP_BASE_IDX', 'regCP_MES_IC_BASE_CNTL', - 'regCP_MES_IC_BASE_CNTL_BASE_IDX', 'regCP_MES_IC_BASE_HI', - 'regCP_MES_IC_BASE_HI_BASE_IDX', 'regCP_MES_IC_BASE_LO', - 'regCP_MES_IC_BASE_LO_BASE_IDX', 'regCP_MES_IC_OP_CNTL', - 'regCP_MES_IC_OP_CNTL_BASE_IDX', 'regCP_MES_INSTR_PNTR', - 'regCP_MES_INSTR_PNTR_BASE_IDX', 'regCP_MES_INTERRUPT', - 'regCP_MES_INTERRUPT_BASE_IDX', 'regCP_MES_INTERRUPT_DATA_16', - 'regCP_MES_INTERRUPT_DATA_16_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_17', - 'regCP_MES_INTERRUPT_DATA_17_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_18', - 'regCP_MES_INTERRUPT_DATA_18_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_19', - 'regCP_MES_INTERRUPT_DATA_19_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_20', - 'regCP_MES_INTERRUPT_DATA_20_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_21', - 'regCP_MES_INTERRUPT_DATA_21_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_22', - 'regCP_MES_INTERRUPT_DATA_22_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_23', - 'regCP_MES_INTERRUPT_DATA_23_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_24', - 'regCP_MES_INTERRUPT_DATA_24_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_25', - 'regCP_MES_INTERRUPT_DATA_25_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_26', - 'regCP_MES_INTERRUPT_DATA_26_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_27', - 'regCP_MES_INTERRUPT_DATA_27_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_28', - 'regCP_MES_INTERRUPT_DATA_28_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_29', - 'regCP_MES_INTERRUPT_DATA_29_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_30', - 'regCP_MES_INTERRUPT_DATA_30_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_31', - 'regCP_MES_INTERRUPT_DATA_31_BASE_IDX', - 'regCP_MES_INTR_ROUTINE_START', - 'regCP_MES_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MES_INTR_ROUTINE_START_HI', - 'regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX', - 'regCP_MES_LOCAL_APERTURE', 'regCP_MES_LOCAL_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_BASE0_HI', 'regCP_MES_LOCAL_BASE0_HI_BASE_IDX', - 'regCP_MES_LOCAL_BASE0_LO', 'regCP_MES_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_APERTURE', - 'regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_BASE_HI', - 'regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_BASE_LO', - 'regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_MASK_HI', - 'regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_MASK_LO', - 'regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_MES_LOCAL_MASK0_HI', 'regCP_MES_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_MES_LOCAL_MASK0_LO', 'regCP_MES_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_APERTURE', - 'regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_BASE_HI', - 'regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_BASE_LO', - 'regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX', - 'regCP_MES_MARCHID_HI', 'regCP_MES_MARCHID_HI_BASE_IDX', - 'regCP_MES_MARCHID_LO', 'regCP_MES_MARCHID_LO_BASE_IDX', - 'regCP_MES_MBADADDR_HI', 'regCP_MES_MBADADDR_HI_BASE_IDX', - 'regCP_MES_MBADADDR_LO', 'regCP_MES_MBADADDR_LO_BASE_IDX', - 'regCP_MES_MCAUSE_HI', 'regCP_MES_MCAUSE_HI_BASE_IDX', - 'regCP_MES_MCAUSE_LO', 'regCP_MES_MCAUSE_LO_BASE_IDX', - 'regCP_MES_MCYCLE_HI', 'regCP_MES_MCYCLE_HI_BASE_IDX', - 'regCP_MES_MCYCLE_LO', 'regCP_MES_MCYCLE_LO_BASE_IDX', - 'regCP_MES_MDBASE_HI', 'regCP_MES_MDBASE_HI_BASE_IDX', - 'regCP_MES_MDBASE_LO', 'regCP_MES_MDBASE_LO_BASE_IDX', - 'regCP_MES_MDBOUND_HI', 'regCP_MES_MDBOUND_HI_BASE_IDX', - 'regCP_MES_MDBOUND_LO', 'regCP_MES_MDBOUND_LO_BASE_IDX', - 'regCP_MES_MEPC_HI', 'regCP_MES_MEPC_HI_BASE_IDX', - 'regCP_MES_MEPC_LO', 'regCP_MES_MEPC_LO_BASE_IDX', - 'regCP_MES_MHARTID_HI', 'regCP_MES_MHARTID_HI_BASE_IDX', - 'regCP_MES_MHARTID_LO', 'regCP_MES_MHARTID_LO_BASE_IDX', - 'regCP_MES_MIBASE_HI', 'regCP_MES_MIBASE_HI_BASE_IDX', - 'regCP_MES_MIBASE_LO', 'regCP_MES_MIBASE_LO_BASE_IDX', - 'regCP_MES_MIBOUND_HI', 'regCP_MES_MIBOUND_HI_BASE_IDX', - 'regCP_MES_MIBOUND_LO', 'regCP_MES_MIBOUND_LO_BASE_IDX', - 'regCP_MES_MIE_HI', 'regCP_MES_MIE_HI_BASE_IDX', - 'regCP_MES_MIE_LO', 'regCP_MES_MIE_LO_BASE_IDX', - 'regCP_MES_MIMPID_HI', 'regCP_MES_MIMPID_HI_BASE_IDX', - 'regCP_MES_MIMPID_LO', 'regCP_MES_MIMPID_LO_BASE_IDX', - 'regCP_MES_MINSTRET_HI', 'regCP_MES_MINSTRET_HI_BASE_IDX', - 'regCP_MES_MINSTRET_LO', 'regCP_MES_MINSTRET_LO_BASE_IDX', - 'regCP_MES_MIP_HI', 'regCP_MES_MIP_HI_BASE_IDX', - 'regCP_MES_MIP_LO', 'regCP_MES_MIP_LO_BASE_IDX', - 'regCP_MES_MISA_HI', 'regCP_MES_MISA_HI_BASE_IDX', - 'regCP_MES_MISA_LO', 'regCP_MES_MISA_LO_BASE_IDX', - 'regCP_MES_MSCRATCH_HI', 'regCP_MES_MSCRATCH_HI_BASE_IDX', - 'regCP_MES_MSCRATCH_LO', 'regCP_MES_MSCRATCH_LO_BASE_IDX', - 'regCP_MES_MSTATUS_HI', 'regCP_MES_MSTATUS_HI_BASE_IDX', - 'regCP_MES_MSTATUS_LO', 'regCP_MES_MSTATUS_LO_BASE_IDX', - 'regCP_MES_MTIMECMP_HI', 'regCP_MES_MTIMECMP_HI_BASE_IDX', - 'regCP_MES_MTIMECMP_LO', 'regCP_MES_MTIMECMP_LO_BASE_IDX', - 'regCP_MES_MTIME_HI', 'regCP_MES_MTIME_HI_BASE_IDX', - 'regCP_MES_MTIME_LO', 'regCP_MES_MTIME_LO_BASE_IDX', - 'regCP_MES_MTVEC_HI', 'regCP_MES_MTVEC_HI_BASE_IDX', - 'regCP_MES_MTVEC_LO', 'regCP_MES_MTVEC_LO_BASE_IDX', - 'regCP_MES_MVENDORID_HI', 'regCP_MES_MVENDORID_HI_BASE_IDX', - 'regCP_MES_MVENDORID_LO', 'regCP_MES_MVENDORID_LO_BASE_IDX', - 'regCP_MES_PENDING_INTERRUPT', - 'regCP_MES_PENDING_INTERRUPT_BASE_IDX', - 'regCP_MES_PERFCOUNT_CNTL', 'regCP_MES_PERFCOUNT_CNTL_BASE_IDX', - 'regCP_MES_PIPE0_PRIORITY', 'regCP_MES_PIPE0_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE1_PRIORITY', 'regCP_MES_PIPE1_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE2_PRIORITY', 'regCP_MES_PIPE2_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE3_PRIORITY', 'regCP_MES_PIPE3_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE_PRIORITY_CNTS', - 'regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_MES_PRGRM_CNTR_START', - 'regCP_MES_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MES_PRGRM_CNTR_START_HI', - 'regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX', - 'regCP_MES_PROCESS_QUANTUM_PIPE0', - 'regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX', - 'regCP_MES_PROCESS_QUANTUM_PIPE1', - 'regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX', - 'regCP_MES_SCRATCH_DATA', 'regCP_MES_SCRATCH_DATA_BASE_IDX', - 'regCP_MES_SCRATCH_INDEX', 'regCP_MES_SCRATCH_INDEX_BASE_IDX', - 'regCP_ME_ATOMIC_PREOP_HI', 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX', - 'regCP_ME_ATOMIC_PREOP_LO', 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX', - 'regCP_ME_CNTL', 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE', - 'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI', - 'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL', - 'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE', - 'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI', - 'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS', - 'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT', - 'regCP_ME_F32_INTERRUPT_BASE_IDX', - 'regCP_ME_GDS_ATOMIC0_PREOP_HI', - 'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_ME_GDS_ATOMIC0_PREOP_LO', - 'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_ME_GDS_ATOMIC1_PREOP_HI', - 'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_ME_GDS_ATOMIC1_PREOP_LO', - 'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP', - 'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_IC_BASE_CNTL', - 'regCP_ME_IC_BASE_CNTL_BASE_IDX', 'regCP_ME_IC_BASE_HI', - 'regCP_ME_IC_BASE_HI_BASE_IDX', 'regCP_ME_IC_BASE_LO', - 'regCP_ME_IC_BASE_LO_BASE_IDX', 'regCP_ME_IC_OP_CNTL', - 'regCP_ME_IC_OP_CNTL_BASE_IDX', 'regCP_ME_INSTR_PNTR', - 'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START', - 'regCP_ME_INTR_ROUTINE_START_BASE_IDX', - 'regCP_ME_INTR_ROUTINE_START_HI', - 'regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_ME_MC_RADDR_HI', - 'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO', - 'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI', - 'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO', - 'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI', - 'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO', - 'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION', - 'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START', - 'regCP_ME_PRGRM_CNTR_START_BASE_IDX', - 'regCP_ME_PRGRM_CNTR_START_HI', - 'regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_ME_RAM_DATA', - 'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR', - 'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR', - 'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_ME_SDMA_CS', - 'regCP_ME_SDMA_CS_BASE_IDX', 'regCP_MQD_BASE_ADDR', - 'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI', - 'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL', - 'regCP_MQD_CONTROL_BASE_IDX', 'regCP_PA_CINVOC_COUNT_HI', - 'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', 'regCP_PA_CINVOC_COUNT_LO', - 'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', 'regCP_PA_CPRIM_COUNT_HI', - 'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_CPRIM_COUNT_LO', - 'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_HI', - 'regCP_PA_MSPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_LO', - 'regCP_PA_MSPRIM_COUNT_LO_BASE_IDX', 'regCP_PERFMON_CNTL', - 'regCP_PERFMON_CNTL_BASE_IDX', 'regCP_PERFMON_CNTX_CNTL', - 'regCP_PERFMON_CNTX_CNTL_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_HI', - 'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_LO', - 'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', - 'regCP_PFP_COMPLETION_STATUS', - 'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT', - 'regCP_PFP_F32_INTERRUPT_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC0_PREOP_HI', - 'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC0_PREOP_LO', - 'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC1_PREOP_HI', - 'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC1_PREOP_LO', - 'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', - 'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX', - 'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX', - 'regCP_PFP_IC_BASE_CNTL', 'regCP_PFP_IC_BASE_CNTL_BASE_IDX', - 'regCP_PFP_IC_BASE_HI', 'regCP_PFP_IC_BASE_HI_BASE_IDX', - 'regCP_PFP_IC_BASE_LO', 'regCP_PFP_IC_BASE_LO_BASE_IDX', - 'regCP_PFP_IC_OP_CNTL', 'regCP_PFP_IC_OP_CNTL_BASE_IDX', - 'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX', - 'regCP_PFP_INTR_ROUTINE_START', - 'regCP_PFP_INTR_ROUTINE_START_BASE_IDX', - 'regCP_PFP_INTR_ROUTINE_START_HI', - 'regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_PFP_JT_STAT', - 'regCP_PFP_JT_STAT_BASE_IDX', 'regCP_PFP_LOAD_CONTROL', - 'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR', - 'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX', - 'regCP_PFP_METADATA_BASE_ADDR_HI', - 'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', - 'regCP_PFP_PRGRM_CNTR_START', - 'regCP_PFP_PRGRM_CNTR_START_BASE_IDX', - 'regCP_PFP_PRGRM_CNTR_START_HI', - 'regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_PFP_SDMA_CS', - 'regCP_PFP_SDMA_CS_BASE_IDX', 'regCP_PFP_UCODE_ADDR', - 'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA', - 'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID', - 'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI', - 'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO', - 'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL', - 'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS', - 'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL', - 'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', - 'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE', - 'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR', - 'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PROCESS_QUANTUM', - 'regCP_PROCESS_QUANTUM_BASE_IDX', 'regCP_PWR_CNTL', - 'regCP_PWR_CNTL_BASE_IDX', 'regCP_RB0_ACTIVE', - 'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE', - 'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI', - 'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK', - 'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL', - 'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR', - 'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX', - 'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX', - 'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR', - 'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI', - 'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_ACTIVE', - 'regCP_RB1_ACTIVE_BASE_IDX', 'regCP_RB1_BASE', - 'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI', - 'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_BUFSZ_MASK', - 'regCP_RB1_BUFSZ_MASK_BASE_IDX', 'regCP_RB1_CNTL', - 'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR', - 'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX', - 'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX', - 'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR', - 'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI', - 'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB_ACTIVE', - 'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE', - 'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK', - 'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL', - 'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR', - 'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL', - 'regCP_RB_DOORBELL_CONTROL_BASE_IDX', - 'regCP_RB_DOORBELL_RANGE_LOWER', - 'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', - 'regCP_RB_DOORBELL_RANGE_UPPER', - 'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET', - 'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR', - 'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI', - 'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX', - 'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX', - 'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID', - 'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR', - 'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY', - 'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI', - 'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI', - 'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regCP_RB_WPTR_POLL_ADDR_LO', - 'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL', - 'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY', - 'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY', - 'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RINGID', - 'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS', - 'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS', - 'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL', - 'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS', - 'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ3_THRESHOLDS', - 'regCP_ROQ3_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL', - 'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_DB_STAT', - 'regCP_ROQ_DB_STAT_BASE_IDX', 'regCP_ROQ_IB1_STAT', - 'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT', - 'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT', - 'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_SAMPLE_STATUS', - 'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA', - 'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX', - 'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI', - 'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT0_LO', - 'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT1_HI', - 'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT1_LO', - 'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SDMA_DMA_DONE', - 'regCP_SDMA_DMA_DONE_BASE_IDX', 'regCP_SD_CNTL', - 'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER', - 'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI', - 'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO', - 'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL', - 'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1', - 'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2', - 'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3', - 'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT', - 'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL', - 'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT', - 'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS', - 'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT', - 'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_ST_BASE_HI', - 'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO', - 'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ', - 'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ', - 'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_SUSPEND_CNTL', - 'regCP_SUSPEND_CNTL_BASE_IDX', 'regCP_SUSPEND_RESUME_REQ', - 'regCP_SUSPEND_RESUME_REQ_BASE_IDX', 'regCP_VGT_ASINVOC_COUNT_HI', - 'regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_ASINVOC_COUNT_LO', - 'regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_CSINVOC_COUNT_HI', - 'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_CSINVOC_COUNT_LO', - 'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_DSINVOC_COUNT_HI', - 'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_DSINVOC_COUNT_LO', - 'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_GSINVOC_COUNT_HI', - 'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_GSINVOC_COUNT_LO', - 'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', - 'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', - 'regCP_VGT_HSINVOC_COUNT_HI', - 'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_HSINVOC_COUNT_LO', - 'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', - 'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', - 'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX', - 'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX', - 'regCP_VGT_VSINVOC_COUNT_HI', - 'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_VSINVOC_COUNT_LO', - 'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS', - 'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX', - 'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX', - 'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX', - 'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX', - 'regCP_WAIT_REG_MEM_TIMEOUT', - 'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI', - 'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO', - 'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regDB_ALPHA_TO_MASK', - 'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0', - 'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL', - 'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT', - 'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2', - 'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX', - 'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG5', - 'regDB_DEBUG5_BASE_IDX', 'regDB_DEBUG6', 'regDB_DEBUG6_BASE_IDX', - 'regDB_DEBUG7', 'regDB_DEBUG7_BASE_IDX', 'regDB_DEBUG_BASE_IDX', - 'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX', - 'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX', - 'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX', - 'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX', - 'regDB_DEPTH_SIZE_XY', 'regDB_DEPTH_SIZE_XY_BASE_IDX', - 'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', 'regDB_EQAA', - 'regDB_EQAA_BASE_IDX', 'regDB_EQUAD_STUTTER_CONTROL', - 'regDB_EQUAD_STUTTER_CONTROL_BASE_IDX', - 'regDB_ETILE_STUTTER_CONTROL', - 'regDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'regDB_EXCEPTION_CONTROL', - 'regDB_EXCEPTION_CONTROL_BASE_IDX', - 'regDB_FGCG_INTERFACES_CLK_CTRL', - 'regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX', - 'regDB_FGCG_SRAMS_CLK_CTRL', 'regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX', - 'regDB_FIFO_DEPTH1', 'regDB_FIFO_DEPTH1_BASE_IDX', - 'regDB_FIFO_DEPTH2', 'regDB_FIFO_DEPTH2_BASE_IDX', - 'regDB_FIFO_DEPTH3', 'regDB_FIFO_DEPTH3_BASE_IDX', - 'regDB_FIFO_DEPTH4', 'regDB_FIFO_DEPTH4_BASE_IDX', - 'regDB_FREE_CACHELINES', 'regDB_FREE_CACHELINES_BASE_IDX', - 'regDB_HTILE_DATA_BASE', 'regDB_HTILE_DATA_BASE_BASE_IDX', - 'regDB_HTILE_DATA_BASE_HI', 'regDB_HTILE_DATA_BASE_HI_BASE_IDX', - 'regDB_HTILE_SURFACE', 'regDB_HTILE_SURFACE_BASE_IDX', - 'regDB_LAST_OF_BURST_CONFIG', - 'regDB_LAST_OF_BURST_CONFIG_BASE_IDX', - 'regDB_LQUAD_STUTTER_CONTROL', - 'regDB_LQUAD_STUTTER_CONTROL_BASE_IDX', - 'regDB_LTILE_STUTTER_CONTROL', - 'regDB_LTILE_STUTTER_CONTROL_BASE_IDX', - 'regDB_MEM_ARB_WATERMARKS', 'regDB_MEM_ARB_WATERMARKS_BASE_IDX', - 'regDB_OCCLUSION_COUNT0_HI', 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT0_LOW', - 'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT1_LOW', - 'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT2_LOW', - 'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT3_LOW', - 'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI', - 'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO', - 'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT', - 'regDB_PERFCOUNTER0_SELECT1', - 'regDB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI', - 'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO', - 'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT', - 'regDB_PERFCOUNTER1_SELECT1', - 'regDB_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI', - 'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO', - 'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT', - 'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI', - 'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO', - 'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT', - 'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL', - 'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL', - 'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE', - 'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX', - 'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RESERVED_REG_1', - 'regDB_RESERVED_REG_1_BASE_IDX', 'regDB_RESERVED_REG_2', - 'regDB_RESERVED_REG_2_BASE_IDX', 'regDB_RESERVED_REG_3', - 'regDB_RESERVED_REG_3_BASE_IDX', 'regDB_RING_CONTROL', - 'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_L2_CACHE_CONTROL', - 'regDB_RMI_L2_CACHE_CONTROL_BASE_IDX', 'regDB_SHADER_CONTROL', - 'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0', - 'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX', - 'regDB_SRESULTS_COMPARE_STATE1', - 'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK', - 'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF', - 'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR', - 'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL', - 'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO', - 'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE', - 'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI', - 'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE', - 'regDB_STENCIL_WRITE_BASE_BASE_IDX', - 'regDB_STENCIL_WRITE_BASE_HI', - 'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL', - 'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS', - 'regDB_WATERMARKS_BASE_IDX', 'regDB_Z_INFO', - 'regDB_Z_INFO_BASE_IDX', 'regDB_Z_READ_BASE', - 'regDB_Z_READ_BASE_BASE_IDX', 'regDB_Z_READ_BASE_HI', - 'regDB_Z_READ_BASE_HI_BASE_IDX', 'regDB_Z_WRITE_BASE', - 'regDB_Z_WRITE_BASE_BASE_IDX', 'regDB_Z_WRITE_BASE_HI', - 'regDB_Z_WRITE_BASE_HI_BASE_IDX', 'regDIDT_EDC_CTRL', - 'regDIDT_EDC_CTRL_BASE_IDX', 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO', - 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX', - 'regDIDT_EDC_OVERFLOW', 'regDIDT_EDC_OVERFLOW_BASE_IDX', - 'regDIDT_EDC_ROLLING_POWER_DELTA', - 'regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_1_2', - 'regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_3_4', - 'regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_5_6', - 'regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_7', - 'regDIDT_EDC_STALL_PATTERN_7_BASE_IDX', 'regDIDT_EDC_STATUS', - 'regDIDT_EDC_STATUS_BASE_IDX', 'regDIDT_EDC_THRESHOLD', - 'regDIDT_EDC_THRESHOLD_BASE_IDX', 'regDIDT_EDC_THROTTLE_CTRL', - 'regDIDT_EDC_THROTTLE_CTRL_BASE_IDX', - 'regDIDT_INDEX_AUTO_INCR_EN', - 'regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'regDIDT_IND_DATA', - 'regDIDT_IND_DATA_BASE_IDX', 'regDIDT_IND_INDEX', - 'regDIDT_IND_INDEX_BASE_IDX', 'regDIDT_STALL_PATTERN_1_2', - 'regDIDT_STALL_PATTERN_1_2_BASE_IDX', 'regDIDT_STALL_PATTERN_3_4', - 'regDIDT_STALL_PATTERN_3_4_BASE_IDX', 'regDIDT_STALL_PATTERN_5_6', - 'regDIDT_STALL_PATTERN_5_6_BASE_IDX', 'regDIDT_STALL_PATTERN_7', - 'regDIDT_STALL_PATTERN_7_BASE_IDX', 'regDIDT_STALL_PATTERN_CTRL', - 'regDIDT_STALL_PATTERN_CTRL_BASE_IDX', 'regEDC_HYSTERESIS_CNTL', - 'regEDC_HYSTERESIS_CNTL_BASE_IDX', 'regEDC_HYSTERESIS_STAT', - 'regEDC_HYSTERESIS_STAT_BASE_IDX', 'regEDC_PERF_COUNTER', - 'regEDC_PERF_COUNTER_BASE_IDX', 'regEDC_STRETCH_NUM_PERF_COUNTER', - 'regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX', - 'regEDC_STRETCH_PERF_COUNTER', - 'regEDC_STRETCH_PERF_COUNTER_BASE_IDX', - 'regEDC_UNSTRETCH_PERF_COUNTER', - 'regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX', 'regGB_ADDR_CONFIG', - 'regGB_ADDR_CONFIG_BASE_IDX', 'regGB_ADDR_CONFIG_READ', - 'regGB_ADDR_CONFIG_READ_BASE_IDX', 'regGB_BACKEND_MAP', - 'regGB_BACKEND_MAP_BASE_IDX', 'regGB_EDC_MODE', - 'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID', - 'regGB_GPU_ID_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST', - 'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL', - 'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', - 'regGCEA_DRAM_RD_CLI2GRP_MAP0', - 'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_DRAM_RD_CLI2GRP_MAP1', - 'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_DRAM_RD_GRP2VC_MAP', - 'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY', - 'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE', - 'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED', - 'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI1', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI2', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI3', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUEUING', - 'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_URGENCY', - 'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', - 'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', - 'regGCEA_DRAM_WR_CLI2GRP_MAP0', - 'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_DRAM_WR_CLI2GRP_MAP1', - 'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_DRAM_WR_GRP2VC_MAP', - 'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY', - 'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE', - 'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED', - 'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI1', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI2', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI3', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUEUING', - 'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_URGENCY', - 'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL', - 'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A', - 'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B', - 'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX', - 'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX', - 'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX', - 'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_EDC_CNT', - 'regGCEA_EDC_CNT2', 'regGCEA_EDC_CNT2_BASE_IDX', - 'regGCEA_EDC_CNT3', 'regGCEA_EDC_CNT3_BASE_IDX', - 'regGCEA_EDC_CNT_BASE_IDX', 'regGCEA_ERR_STATUS', - 'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_GL2C_XBR_CREDITS', - 'regGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'regGCEA_GL2C_XBR_MAXBURST', - 'regGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'regGCEA_ICG_CTRL', - 'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST', - 'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0', - 'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_IO_RD_CLI2GRP_MAP1', - 'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_IO_RD_COMBINE_FLUSH', - 'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE', - 'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED', - 'regGCEA_IO_RD_PRI_FIXED_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI1', - 'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI2', - 'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI3', - 'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX', - 'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX', - 'regGCEA_IO_RD_PRI_URGENCY_MASKING', - 'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', - 'regGCEA_IO_WR_CLI2GRP_MAP0', - 'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_IO_WR_CLI2GRP_MAP1', - 'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_IO_WR_COMBINE_FLUSH', - 'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE', - 'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED', - 'regGCEA_IO_WR_PRI_FIXED_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI1', - 'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI2', - 'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI3', - 'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX', - 'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX', - 'regGCEA_IO_WR_PRI_URGENCY_MASKING', - 'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', - 'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX', - 'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2', - 'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX', - 'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX', - 'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG', - 'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG', - 'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER2_HI', - 'regGCEA_PERFCOUNTER2_HI_BASE_IDX', 'regGCEA_PERFCOUNTER2_LO', - 'regGCEA_PERFCOUNTER2_LO_BASE_IDX', 'regGCEA_PERFCOUNTER2_MODE', - 'regGCEA_PERFCOUNTER2_MODE_BASE_IDX', - 'regGCEA_PERFCOUNTER2_SELECT', 'regGCEA_PERFCOUNTER2_SELECT1', - 'regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'regGCEA_PERFCOUNTER_HI', - 'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO', - 'regGCEA_PERFCOUNTER_LO_BASE_IDX', - 'regGCEA_PERFCOUNTER_RSLT_CNTL', - 'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL', - 'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP', - 'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_RRET_MEM_RESERVE', - 'regGCEA_RRET_MEM_RESERVE_BASE_IDX', 'regGCEA_SDP_ARB_FINAL', - 'regGCEA_SDP_ARB_FINAL_BASE_IDX', 'regGCEA_SDP_CREDITS', - 'regGCEA_SDP_CREDITS_BASE_IDX', 'regGCEA_SDP_ENABLE', - 'regGCEA_SDP_ENABLE_BASE_IDX', 'regGCEA_SDP_IO_PRIORITY', - 'regGCEA_SDP_IO_PRIORITY_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE0', - 'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE1', - 'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE0', - 'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE1', - 'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', 'regGCMC_MEM_POWER_LS', - 'regGCMC_MEM_POWER_LS_BASE_IDX', 'regGCMC_VM_AGP_BASE', - 'regGCMC_VM_AGP_BASE_BASE_IDX', 'regGCMC_VM_AGP_BOT', - 'regGCMC_VM_AGP_BOT_BASE_IDX', 'regGCMC_VM_AGP_TOP', - 'regGCMC_VM_AGP_TOP_BASE_IDX', 'regGCMC_VM_APT_CNTL', - 'regGCMC_VM_APT_CNTL_BASE_IDX', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_FB_LOCATION_BASE', - 'regGCMC_VM_FB_LOCATION_BASE_BASE_IDX', - 'regGCMC_VM_FB_LOCATION_TOP', - 'regGCMC_VM_FB_LOCATION_TOP_BASE_IDX', - 'regGCMC_VM_FB_NOALLOC_CNTL', - 'regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regGCMC_VM_FB_OFFSET', - 'regGCMC_VM_FB_OFFSET_BASE_IDX', 'regGCMC_VM_FB_SIZE_OFFSET_VF0', - 'regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF1', 'regGCMC_VM_FB_SIZE_OFFSET_VF10', - 'regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF11', - 'regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF12', - 'regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF13', - 'regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF14', - 'regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF15', - 'regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF2', - 'regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF3', - 'regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF4', - 'regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF5', - 'regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF6', - 'regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF7', - 'regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF8', - 'regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF9', - 'regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER0_CFG', - 'regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER1_CFG', - 'regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER2_CFG', - 'regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER3_CFG', - 'regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER4_CFG', - 'regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER5_CFG', - 'regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER6_CFG', - 'regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER7_CFG', - 'regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_HI', - 'regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_LO', - 'regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL', - 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_END', - 'regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL', - 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_START', - 'regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_0', 'regGCMC_VM_MARC_BASE_HI_0_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_1', 'regGCMC_VM_MARC_BASE_HI_10', - 'regGCMC_VM_MARC_BASE_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_11', - 'regGCMC_VM_MARC_BASE_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_12', - 'regGCMC_VM_MARC_BASE_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_13', - 'regGCMC_VM_MARC_BASE_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_14', - 'regGCMC_VM_MARC_BASE_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_15', - 'regGCMC_VM_MARC_BASE_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_2', - 'regGCMC_VM_MARC_BASE_HI_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_3', - 'regGCMC_VM_MARC_BASE_HI_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_4', - 'regGCMC_VM_MARC_BASE_HI_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_5', - 'regGCMC_VM_MARC_BASE_HI_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_6', - 'regGCMC_VM_MARC_BASE_HI_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_7', - 'regGCMC_VM_MARC_BASE_HI_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_8', - 'regGCMC_VM_MARC_BASE_HI_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_9', - 'regGCMC_VM_MARC_BASE_HI_9_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_0', - 'regGCMC_VM_MARC_BASE_LO_0_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_1', - 'regGCMC_VM_MARC_BASE_LO_10', - 'regGCMC_VM_MARC_BASE_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_11', - 'regGCMC_VM_MARC_BASE_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_12', - 'regGCMC_VM_MARC_BASE_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_13', - 'regGCMC_VM_MARC_BASE_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_14', - 'regGCMC_VM_MARC_BASE_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_15', - 'regGCMC_VM_MARC_BASE_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_2', - 'regGCMC_VM_MARC_BASE_LO_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_3', - 'regGCMC_VM_MARC_BASE_LO_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_4', - 'regGCMC_VM_MARC_BASE_LO_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_5', - 'regGCMC_VM_MARC_BASE_LO_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_6', - 'regGCMC_VM_MARC_BASE_LO_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_7', - 'regGCMC_VM_MARC_BASE_LO_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_8', - 'regGCMC_VM_MARC_BASE_LO_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_9', - 'regGCMC_VM_MARC_BASE_LO_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_0', - 'regGCMC_VM_MARC_LEN_HI_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_1', - 'regGCMC_VM_MARC_LEN_HI_10', 'regGCMC_VM_MARC_LEN_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_11', 'regGCMC_VM_MARC_LEN_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_12', 'regGCMC_VM_MARC_LEN_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_13', 'regGCMC_VM_MARC_LEN_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_14', 'regGCMC_VM_MARC_LEN_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_15', 'regGCMC_VM_MARC_LEN_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_2', - 'regGCMC_VM_MARC_LEN_HI_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_3', - 'regGCMC_VM_MARC_LEN_HI_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_4', - 'regGCMC_VM_MARC_LEN_HI_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_5', - 'regGCMC_VM_MARC_LEN_HI_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_6', - 'regGCMC_VM_MARC_LEN_HI_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_7', - 'regGCMC_VM_MARC_LEN_HI_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_8', - 'regGCMC_VM_MARC_LEN_HI_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_9', - 'regGCMC_VM_MARC_LEN_HI_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_0', - 'regGCMC_VM_MARC_LEN_LO_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_1', - 'regGCMC_VM_MARC_LEN_LO_10', 'regGCMC_VM_MARC_LEN_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_11', 'regGCMC_VM_MARC_LEN_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_12', 'regGCMC_VM_MARC_LEN_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_13', 'regGCMC_VM_MARC_LEN_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_14', 'regGCMC_VM_MARC_LEN_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_15', 'regGCMC_VM_MARC_LEN_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_2', - 'regGCMC_VM_MARC_LEN_LO_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_3', - 'regGCMC_VM_MARC_LEN_LO_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_4', - 'regGCMC_VM_MARC_LEN_LO_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_5', - 'regGCMC_VM_MARC_LEN_LO_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_6', - 'regGCMC_VM_MARC_LEN_LO_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_7', - 'regGCMC_VM_MARC_LEN_LO_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_8', - 'regGCMC_VM_MARC_LEN_LO_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_9', - 'regGCMC_VM_MARC_LEN_LO_9_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_0', - 'regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_1', - 'regGCMC_VM_MARC_PFVF_MAPPING_10', - 'regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_11', - 'regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_12', - 'regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_13', - 'regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_14', - 'regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_15', - 'regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_2', - 'regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_3', - 'regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_4', - 'regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_5', - 'regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_6', - 'regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_7', - 'regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_8', - 'regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_9', - 'regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_0', - 'regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_1', 'regGCMC_VM_MARC_RELOC_HI_10', - 'regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_11', - 'regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_12', - 'regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_13', - 'regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_14', - 'regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_15', - 'regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_2', - 'regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_3', - 'regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_4', - 'regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_5', - 'regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_6', - 'regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_7', - 'regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_8', - 'regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_9', - 'regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_0', - 'regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_1', 'regGCMC_VM_MARC_RELOC_LO_10', - 'regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_11', - 'regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_12', - 'regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_13', - 'regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_14', - 'regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_15', - 'regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_2', - 'regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_3', - 'regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_4', - 'regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_5', - 'regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_6', - 'regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_7', - 'regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_8', - 'regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_9', - 'regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX', - 'regGCMC_VM_MX_L1_TLB_CNTL', 'regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX', - 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2', - 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', - 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1', - 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', - 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2', - 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', - 'regGCMC_VM_STEERING', 'regGCMC_VM_STEERING_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR', - 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR', - 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', - 'regGCRD_CREDIT_SAFE', 'regGCRD_CREDIT_SAFE_BASE_IDX', - 'regGCRD_SA0_TARGETS_DISABLE', - 'regGCRD_SA0_TARGETS_DISABLE_BASE_IDX', - 'regGCRD_SA1_TARGETS_DISABLE', - 'regGCRD_SA1_TARGETS_DISABLE_BASE_IDX', 'regGCR_CMD_STATUS', - 'regGCR_CMD_STATUS_BASE_IDX', 'regGCR_GENERAL_CNTL', - 'regGCR_GENERAL_CNTL_BASE_IDX', 'regGCR_PERFCOUNTER0_HI', - 'regGCR_PERFCOUNTER0_HI_BASE_IDX', 'regGCR_PERFCOUNTER0_LO', - 'regGCR_PERFCOUNTER0_LO_BASE_IDX', 'regGCR_PERFCOUNTER0_SELECT', - 'regGCR_PERFCOUNTER0_SELECT1', - 'regGCR_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'regGCR_PERFCOUNTER1_HI', - 'regGCR_PERFCOUNTER1_HI_BASE_IDX', 'regGCR_PERFCOUNTER1_LO', - 'regGCR_PERFCOUNTER1_LO_BASE_IDX', 'regGCR_PERFCOUNTER1_SELECT', - 'regGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'regGCR_PIO_CNTL', - 'regGCR_PIO_CNTL_BASE_IDX', 'regGCR_PIO_DATA', - 'regGCR_PIO_DATA_BASE_IDX', 'regGCR_SPARE', - 'regGCR_SPARE_BASE_IDX', 'regGCUTCL2_CGTT_BUSY_CTRL', - 'regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX', - 'regGCUTCL2_GROUP_RET_FAULT_STATUS', - 'regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX', - 'regGCUTCL2_HARVEST_BYPASS_GROUPS', - 'regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', - 'regGCUTCL2_ICG_CTRL', 'regGCUTCL2_ICG_CTRL_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER0_CFG', - 'regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER1_CFG', - 'regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER2_CFG', - 'regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER3_CFG', - 'regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_HI', 'regGCUTCL2_PERFCOUNTER_HI_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_LO', 'regGCUTCL2_PERFCOUNTER_LO_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL', - 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID', - 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', - 'regGCUTC_TRANSLATION_FAULT_CNTL0', - 'regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX', - 'regGCUTC_TRANSLATION_FAULT_CNTL1', - 'regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX', - 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT', - 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_HI', - 'regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_LO', - 'regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_MODE', - 'regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_SELECT', - 'regGCVML2_PERFCOUNTER2_0_SELECT1', - 'regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_HI', - 'regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_LO', - 'regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_MODE', - 'regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_SELECT', - 'regGCVML2_PERFCOUNTER2_1_SELECT1', - 'regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX', - 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ', - 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', - 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT', - 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'regGCVML2_WALKER_MACRO_THROTTLE_TIME', - 'regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX', - 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT', - 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'regGCVML2_WALKER_MICRO_THROTTLE_TIME', - 'regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX', - 'regGCVM_CONTEXT0_CNTL', 'regGCVM_CONTEXT0_CNTL_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_CNTL', 'regGCVM_CONTEXT10_CNTL_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_CNTL', 'regGCVM_CONTEXT11_CNTL_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_CNTL', 'regGCVM_CONTEXT12_CNTL_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_CNTL', 'regGCVM_CONTEXT13_CNTL_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_CNTL', 'regGCVM_CONTEXT14_CNTL_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_CNTL', 'regGCVM_CONTEXT15_CNTL_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_CNTL', 'regGCVM_CONTEXT1_CNTL_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_CNTL', 'regGCVM_CONTEXT2_CNTL_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_CNTL', 'regGCVM_CONTEXT3_CNTL_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_CNTL', 'regGCVM_CONTEXT4_CNTL_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_CNTL', 'regGCVM_CONTEXT5_CNTL_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_CNTL', 'regGCVM_CONTEXT6_CNTL_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_CNTL', 'regGCVM_CONTEXT7_CNTL_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_CNTL', 'regGCVM_CONTEXT8_CNTL_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_CNTL', 'regGCVM_CONTEXT9_CNTL_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXTS_DISABLE', 'regGCVM_CONTEXTS_DISABLE_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_CNTL', - 'regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', - 'regGCVM_INVALIDATE_CNTL', 'regGCVM_INVALIDATE_CNTL_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ACK', - 'regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_REQ', - 'regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_SEM', - 'regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ACK', - 'regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_REQ', - 'regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_SEM', - 'regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ACK', - 'regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_REQ', - 'regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_SEM', - 'regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ACK', - 'regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_REQ', - 'regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_SEM', - 'regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ACK', - 'regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_REQ', - 'regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_SEM', - 'regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ACK', - 'regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_REQ', - 'regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_SEM', - 'regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ACK', - 'regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_REQ', - 'regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_SEM', - 'regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ACK', - 'regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_REQ', - 'regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_SEM', - 'regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ACK', - 'regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_REQ', - 'regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_SEM', - 'regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ACK', - 'regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_REQ', - 'regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_SEM', - 'regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ACK', - 'regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_REQ', - 'regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_SEM', - 'regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ACK', - 'regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_REQ', - 'regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_SEM', - 'regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ACK', - 'regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_REQ', - 'regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_SEM', - 'regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ACK', - 'regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_REQ', - 'regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_SEM', - 'regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ACK', - 'regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_REQ', - 'regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_SEM', - 'regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ACK', - 'regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_REQ', - 'regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_SEM', - 'regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ACK', - 'regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_REQ', - 'regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_SEM', - 'regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ACK', - 'regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_REQ', - 'regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_SEM', - 'regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_MASKS', - 'regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID2', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', - 'regGCVM_L2_CACHE_PARITY_CNTL', - 'regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', - 'regGCVM_L2_CGTT_BUSY_CTRL', 'regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX', - 'regGCVM_L2_CNTL', 'regGCVM_L2_CNTL2', - 'regGCVM_L2_CNTL2_BASE_IDX', 'regGCVM_L2_CNTL3', - 'regGCVM_L2_CNTL3_BASE_IDX', 'regGCVM_L2_CNTL4', - 'regGCVM_L2_CNTL4_BASE_IDX', 'regGCVM_L2_CNTL5', - 'regGCVM_L2_CNTL5_BASE_IDX', 'regGCVM_L2_CNTL_BASE_IDX', - 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', - 'regGCVM_L2_GCR_CNTL', 'regGCVM_L2_GCR_CNTL_BASE_IDX', - 'regGCVM_L2_ICG_CTRL', 'regGCVM_L2_ICG_CTRL_BASE_IDX', - 'regGCVM_L2_MM_GROUP_RT_CLASSES', - 'regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', - 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_CNTL', - 'regGCVM_L2_PROTECTION_FAULT_CNTL2', - 'regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_STATUS', - 'regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', - 'regGCVM_L2_PTE_CACHE_DUMP_CNTL', - 'regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', - 'regGCVM_L2_PTE_CACHE_DUMP_READ', - 'regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regGCVM_L2_STATUS', - 'regGCVM_L2_STATUS_BASE_IDX', 'regGC_CAC_AGGR_GFXCLK_CYCLE', - 'regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regGC_CAC_AGGR_LOWER', - 'regGC_CAC_AGGR_LOWER_BASE_IDX', 'regGC_CAC_AGGR_UPPER', - 'regGC_CAC_AGGR_UPPER_BASE_IDX', 'regGC_CAC_CTRL_1', - 'regGC_CAC_CTRL_1_BASE_IDX', 'regGC_CAC_CTRL_2', - 'regGC_CAC_CTRL_2_BASE_IDX', 'regGC_CAC_IND_DATA', - 'regGC_CAC_IND_DATA_BASE_IDX', 'regGC_CAC_IND_INDEX', - 'regGC_CAC_IND_INDEX_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_0', - 'regGC_CAC_WEIGHT_CHC_0_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_1', - 'regGC_CAC_WEIGHT_CHC_1_BASE_IDX', 'regGC_CAC_WEIGHT_CP_0', - 'regGC_CAC_WEIGHT_CP_0_BASE_IDX', 'regGC_CAC_WEIGHT_CP_1', - 'regGC_CAC_WEIGHT_CP_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_0', - 'regGC_CAC_WEIGHT_EA_0_BASE_IDX', 'regGC_CAC_WEIGHT_EA_1', - 'regGC_CAC_WEIGHT_EA_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_2', - 'regGC_CAC_WEIGHT_EA_2_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_0', - 'regGC_CAC_WEIGHT_GDS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_1', - 'regGC_CAC_WEIGHT_GDS_1_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_2', - 'regGC_CAC_WEIGHT_GDS_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_0', - 'regGC_CAC_WEIGHT_GE_0_BASE_IDX', 'regGC_CAC_WEIGHT_GE_1', - 'regGC_CAC_WEIGHT_GE_1_BASE_IDX', 'regGC_CAC_WEIGHT_GE_2', - 'regGC_CAC_WEIGHT_GE_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_3', - 'regGC_CAC_WEIGHT_GE_3_BASE_IDX', 'regGC_CAC_WEIGHT_GE_4', - 'regGC_CAC_WEIGHT_GE_4_BASE_IDX', 'regGC_CAC_WEIGHT_GE_5', - 'regGC_CAC_WEIGHT_GE_5_BASE_IDX', 'regGC_CAC_WEIGHT_GE_6', - 'regGC_CAC_WEIGHT_GE_6_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_0', - 'regGC_CAC_WEIGHT_GL2C_0_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_1', - 'regGC_CAC_WEIGHT_GL2C_1_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_2', - 'regGC_CAC_WEIGHT_GL2C_2_BASE_IDX', 'regGC_CAC_WEIGHT_GRBM_0', - 'regGC_CAC_WEIGHT_GRBM_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_0', - 'regGC_CAC_WEIGHT_GUS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_1', - 'regGC_CAC_WEIGHT_GUS_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_0', - 'regGC_CAC_WEIGHT_PH_0_BASE_IDX', 'regGC_CAC_WEIGHT_PH_1', - 'regGC_CAC_WEIGHT_PH_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_2', - 'regGC_CAC_WEIGHT_PH_2_BASE_IDX', 'regGC_CAC_WEIGHT_PH_3', - 'regGC_CAC_WEIGHT_PH_3_BASE_IDX', 'regGC_CAC_WEIGHT_PMM_0', - 'regGC_CAC_WEIGHT_PMM_0_BASE_IDX', 'regGC_CAC_WEIGHT_RLC_0', - 'regGC_CAC_WEIGHT_RLC_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_0', - 'regGC_CAC_WEIGHT_SDMA_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_1', - 'regGC_CAC_WEIGHT_SDMA_1_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_2', - 'regGC_CAC_WEIGHT_SDMA_2_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_3', - 'regGC_CAC_WEIGHT_SDMA_3_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_4', - 'regGC_CAC_WEIGHT_SDMA_4_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_5', - 'regGC_CAC_WEIGHT_SDMA_5_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_0', - 'regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_1', - 'regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_2', - 'regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_0', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_1', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_2', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX', - 'regGC_EDC_CLK_MONITOR_CTRL', - 'regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX', 'regGC_EDC_CTRL', - 'regGC_EDC_CTRL_BASE_IDX', 'regGC_EDC_OVERFLOW', - 'regGC_EDC_OVERFLOW_BASE_IDX', 'regGC_EDC_ROLLING_POWER_DELTA', - 'regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'regGC_EDC_STATUS', - 'regGC_EDC_STATUS_BASE_IDX', 'regGC_EDC_STRETCH_CTRL', - 'regGC_EDC_STRETCH_CTRL_BASE_IDX', 'regGC_EDC_STRETCH_THRESHOLD', - 'regGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'regGC_EDC_THRESHOLD', - 'regGC_EDC_THRESHOLD_BASE_IDX', 'regGC_IH_COOKIE_0_PTR', - 'regGC_IH_COOKIE_0_PTR_BASE_IDX', 'regGC_THROTTLE_CTRL', - 'regGC_THROTTLE_CTRL1', 'regGC_THROTTLE_CTRL1_BASE_IDX', - 'regGC_THROTTLE_CTRL_BASE_IDX', 'regGC_THROTTLE_STATUS', - 'regGC_THROTTLE_STATUS_BASE_IDX', 'regGC_USER_PRIM_CONFIG', - 'regGC_USER_PRIM_CONFIG_BASE_IDX', - 'regGC_USER_RB_BACKEND_DISABLE', - 'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX', - 'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX', - 'regGC_USER_RMI_REDUNDANCY', 'regGC_USER_RMI_REDUNDANCY_BASE_IDX', - 'regGC_USER_SA_UNIT_DISABLE', - 'regGC_USER_SA_UNIT_DISABLE_BASE_IDX', - 'regGC_USER_SHADER_ARRAY_CONFIG', - 'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', - 'regGC_USER_SHADER_RATE_CONFIG', - 'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'regGDS_ATOM_BASE', - 'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL', - 'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE', - 'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST', - 'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0', - 'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1', - 'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP', - 'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0', - 'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U', - 'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1', - 'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U', - 'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE', - 'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0', - 'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U', - 'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1', - 'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U', - 'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CNTL_STATUS', - 'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID', - 'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG', - 'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0', - 'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1', - 'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2', - 'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3', - 'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS', - 'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL', - 'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX', - 'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT', - 'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT', - 'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED', - 'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT', - 'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT', - 'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE', - 'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX', - 'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS', - 'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_0', - 'regGDS_GS_0_BASE_IDX', 'regGDS_GS_1', 'regGDS_GS_1_BASE_IDX', - 'regGDS_GS_2', 'regGDS_GS_2_BASE_IDX', 'regGDS_GS_3', - 'regGDS_GS_3_BASE_IDX', 'regGDS_GS_CTXSW_CNT0', - 'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1', - 'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2', - 'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3', - 'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0', - 'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1', - 'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE', - 'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT', - 'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX', - 'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET', - 'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0', - 'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1', - 'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX', - 'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX', - 'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX', - 'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX', - 'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX', - 'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX', - 'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2', - 'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3', - 'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4', - 'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5', - 'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6', - 'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7', - 'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8', - 'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9', - 'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_MEMORY_CLEAN', - 'regGDS_MEMORY_CLEAN_BASE_IDX', 'regGDS_OA_ADDRESS', - 'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE', - 'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL', - 'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER', - 'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC', - 'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET', - 'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK', - 'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE', - 'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0', - 'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10', - 'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11', - 'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12', - 'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13', - 'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14', - 'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15', - 'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX', - 'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3', - 'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4', - 'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5', - 'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6', - 'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7', - 'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8', - 'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9', - 'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI', - 'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO', - 'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT', - 'regGDS_PERFCOUNTER0_SELECT1', - 'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI', - 'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO', - 'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT', - 'regGDS_PERFCOUNTER1_SELECT1', - 'regGDS_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI', - 'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO', - 'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT', - 'regGDS_PERFCOUNTER2_SELECT1', - 'regGDS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI', - 'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO', - 'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT', - 'regGDS_PERFCOUNTER3_SELECT1', - 'regGDS_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT', - 'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS_CTXSW_CNT0', - 'regGDS_PS_CTXSW_CNT0_BASE_IDX', 'regGDS_PS_CTXSW_CNT1', - 'regGDS_PS_CTXSW_CNT1_BASE_IDX', 'regGDS_PS_CTXSW_CNT2', - 'regGDS_PS_CTXSW_CNT2_BASE_IDX', 'regGDS_PS_CTXSW_CNT3', - 'regGDS_PS_CTXSW_CNT3_BASE_IDX', 'regGDS_PS_CTXSW_IDX', - 'regGDS_PS_CTXSW_IDX_BASE_IDX', 'regGDS_RD_ADDR', - 'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR', - 'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT', - 'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA', - 'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA', - 'regGDS_RD_DATA_BASE_IDX', 'regGDS_STRMOUT_DWORDS_WRITTEN_0', - 'regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_1', - 'regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_2', - 'regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_3', - 'regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX', 'regGDS_VMID0_BASE', - 'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE', - 'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE', - 'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE', - 'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE', - 'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE', - 'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE', - 'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE', - 'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE', - 'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE', - 'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE', - 'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE', - 'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE', - 'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE', - 'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE', - 'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE', - 'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE', - 'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE', - 'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE', - 'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE', - 'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE', - 'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE', - 'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE', - 'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE', - 'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE', - 'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE', - 'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE', - 'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE', - 'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE', - 'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE', - 'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE', - 'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE', - 'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT', - 'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_WRITE_COMPLETE', - 'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR', - 'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR', - 'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA', - 'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA', - 'regGDS_WR_DATA_BASE_IDX', 'regGE1_PERFCOUNTER0_HI', - 'regGE1_PERFCOUNTER0_HI_BASE_IDX', 'regGE1_PERFCOUNTER0_LO', - 'regGE1_PERFCOUNTER0_LO_BASE_IDX', 'regGE1_PERFCOUNTER0_SELECT', - 'regGE1_PERFCOUNTER0_SELECT1', - 'regGE1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER1_HI', - 'regGE1_PERFCOUNTER1_HI_BASE_IDX', 'regGE1_PERFCOUNTER1_LO', - 'regGE1_PERFCOUNTER1_LO_BASE_IDX', 'regGE1_PERFCOUNTER1_SELECT', - 'regGE1_PERFCOUNTER1_SELECT1', - 'regGE1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER2_HI', - 'regGE1_PERFCOUNTER2_HI_BASE_IDX', 'regGE1_PERFCOUNTER2_LO', - 'regGE1_PERFCOUNTER2_LO_BASE_IDX', 'regGE1_PERFCOUNTER2_SELECT', - 'regGE1_PERFCOUNTER2_SELECT1', - 'regGE1_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER3_HI', - 'regGE1_PERFCOUNTER3_HI_BASE_IDX', 'regGE1_PERFCOUNTER3_LO', - 'regGE1_PERFCOUNTER3_LO_BASE_IDX', 'regGE1_PERFCOUNTER3_SELECT', - 'regGE1_PERFCOUNTER3_SELECT1', - 'regGE1_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_HI', - 'regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_LO', - 'regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_SELECT', - 'regGE2_DIST_PERFCOUNTER0_SELECT1', - 'regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_HI', - 'regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_LO', - 'regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_SELECT', - 'regGE2_DIST_PERFCOUNTER1_SELECT1', - 'regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_HI', - 'regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_LO', - 'regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_SELECT', - 'regGE2_DIST_PERFCOUNTER2_SELECT1', - 'regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_HI', - 'regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_LO', - 'regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_SELECT', - 'regGE2_DIST_PERFCOUNTER3_SELECT1', - 'regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGE2_SE_CNTL_STATUS', 'regGE2_SE_CNTL_STATUS_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_HI', 'regGE2_SE_PERFCOUNTER0_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_LO', 'regGE2_SE_PERFCOUNTER0_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_SELECT', 'regGE2_SE_PERFCOUNTER0_SELECT1', - 'regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_HI', 'regGE2_SE_PERFCOUNTER1_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_LO', 'regGE2_SE_PERFCOUNTER1_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_SELECT', 'regGE2_SE_PERFCOUNTER1_SELECT1', - 'regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_HI', 'regGE2_SE_PERFCOUNTER2_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_LO', 'regGE2_SE_PERFCOUNTER2_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_SELECT', 'regGE2_SE_PERFCOUNTER2_SELECT1', - 'regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_HI', 'regGE2_SE_PERFCOUNTER3_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_LO', 'regGE2_SE_PERFCOUNTER3_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_SELECT', 'regGE2_SE_PERFCOUNTER3_SELECT1', - 'regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'regGE_CNTL', - 'regGE_CNTL_BASE_IDX', 'regGE_GS_FAST_LAUNCH_WG_DIM', - 'regGE_GS_FAST_LAUNCH_WG_DIM_1', - 'regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX', - 'regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX', 'regGE_INDX_OFFSET', - 'regGE_INDX_OFFSET_BASE_IDX', 'regGE_MAX_OUTPUT_PER_SUBGROUP', - 'regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'regGE_MAX_VTX_INDX', - 'regGE_MAX_VTX_INDX_BASE_IDX', 'regGE_MIN_VTX_INDX', - 'regGE_MIN_VTX_INDX_BASE_IDX', 'regGE_MULTI_PRIM_IB_RESET_EN', - 'regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'regGE_NGG_SUBGRP_CNTL', - 'regGE_NGG_SUBGRP_CNTL_BASE_IDX', 'regGE_PA_IF_SAFE_REG', - 'regGE_PA_IF_SAFE_REG_BASE_IDX', 'regGE_PC_ALLOC', - 'regGE_PC_ALLOC_BASE_IDX', 'regGE_PRIV_CONTROL', - 'regGE_PRIV_CONTROL_BASE_IDX', 'regGE_RATE_CNTL_1', - 'regGE_RATE_CNTL_1_BASE_IDX', 'regGE_RATE_CNTL_2', - 'regGE_RATE_CNTL_2_BASE_IDX', 'regGE_SPI_IF_SAFE_REG', - 'regGE_SPI_IF_SAFE_REG_BASE_IDX', 'regGE_STATUS', - 'regGE_STATUS_BASE_IDX', 'regGE_STEREO_CNTL', - 'regGE_STEREO_CNTL_BASE_IDX', 'regGE_USER_VGPR1', - 'regGE_USER_VGPR1_BASE_IDX', 'regGE_USER_VGPR2', - 'regGE_USER_VGPR2_BASE_IDX', 'regGE_USER_VGPR3', - 'regGE_USER_VGPR3_BASE_IDX', 'regGE_USER_VGPR_EN', - 'regGE_USER_VGPR_EN_BASE_IDX', 'regGFX_COPY_STATE', - 'regGFX_COPY_STATE_BASE_IDX', 'regGFX_ICG_GL2C_CTRL', - 'regGFX_ICG_GL2C_CTRL1', 'regGFX_ICG_GL2C_CTRL1_BASE_IDX', - 'regGFX_ICG_GL2C_CTRL_BASE_IDX', 'regGFX_IMU_AEB_OVERRIDE', - 'regGFX_IMU_AEB_OVERRIDE_BASE_IDX', 'regGFX_IMU_C2PMSG_0', - 'regGFX_IMU_C2PMSG_0_BASE_IDX', 'regGFX_IMU_C2PMSG_1', - 'regGFX_IMU_C2PMSG_10', 'regGFX_IMU_C2PMSG_10_BASE_IDX', - 'regGFX_IMU_C2PMSG_11', 'regGFX_IMU_C2PMSG_11_BASE_IDX', - 'regGFX_IMU_C2PMSG_12', 'regGFX_IMU_C2PMSG_12_BASE_IDX', - 'regGFX_IMU_C2PMSG_13', 'regGFX_IMU_C2PMSG_13_BASE_IDX', - 'regGFX_IMU_C2PMSG_14', 'regGFX_IMU_C2PMSG_14_BASE_IDX', - 'regGFX_IMU_C2PMSG_15', 'regGFX_IMU_C2PMSG_15_BASE_IDX', - 'regGFX_IMU_C2PMSG_16', 'regGFX_IMU_C2PMSG_16_BASE_IDX', - 'regGFX_IMU_C2PMSG_17', 'regGFX_IMU_C2PMSG_17_BASE_IDX', - 'regGFX_IMU_C2PMSG_18', 'regGFX_IMU_C2PMSG_18_BASE_IDX', - 'regGFX_IMU_C2PMSG_19', 'regGFX_IMU_C2PMSG_19_BASE_IDX', - 'regGFX_IMU_C2PMSG_1_BASE_IDX', 'regGFX_IMU_C2PMSG_2', - 'regGFX_IMU_C2PMSG_20', 'regGFX_IMU_C2PMSG_20_BASE_IDX', - 'regGFX_IMU_C2PMSG_21', 'regGFX_IMU_C2PMSG_21_BASE_IDX', - 'regGFX_IMU_C2PMSG_22', 'regGFX_IMU_C2PMSG_22_BASE_IDX', - 'regGFX_IMU_C2PMSG_23', 'regGFX_IMU_C2PMSG_23_BASE_IDX', - 'regGFX_IMU_C2PMSG_24', 'regGFX_IMU_C2PMSG_24_BASE_IDX', - 'regGFX_IMU_C2PMSG_25', 'regGFX_IMU_C2PMSG_25_BASE_IDX', - 'regGFX_IMU_C2PMSG_26', 'regGFX_IMU_C2PMSG_26_BASE_IDX', - 'regGFX_IMU_C2PMSG_27', 'regGFX_IMU_C2PMSG_27_BASE_IDX', - 'regGFX_IMU_C2PMSG_28', 'regGFX_IMU_C2PMSG_28_BASE_IDX', - 'regGFX_IMU_C2PMSG_29', 'regGFX_IMU_C2PMSG_29_BASE_IDX', - 'regGFX_IMU_C2PMSG_2_BASE_IDX', 'regGFX_IMU_C2PMSG_3', - 'regGFX_IMU_C2PMSG_30', 'regGFX_IMU_C2PMSG_30_BASE_IDX', - 'regGFX_IMU_C2PMSG_31', 'regGFX_IMU_C2PMSG_31_BASE_IDX', - 'regGFX_IMU_C2PMSG_32', 'regGFX_IMU_C2PMSG_32_BASE_IDX', - 'regGFX_IMU_C2PMSG_33', 'regGFX_IMU_C2PMSG_33_BASE_IDX', - 'regGFX_IMU_C2PMSG_34', 'regGFX_IMU_C2PMSG_34_BASE_IDX', - 'regGFX_IMU_C2PMSG_35', 'regGFX_IMU_C2PMSG_35_BASE_IDX', - 'regGFX_IMU_C2PMSG_36', 'regGFX_IMU_C2PMSG_36_BASE_IDX', - 'regGFX_IMU_C2PMSG_37', 'regGFX_IMU_C2PMSG_37_BASE_IDX', - 'regGFX_IMU_C2PMSG_38', 'regGFX_IMU_C2PMSG_38_BASE_IDX', - 'regGFX_IMU_C2PMSG_39', 'regGFX_IMU_C2PMSG_39_BASE_IDX', - 'regGFX_IMU_C2PMSG_3_BASE_IDX', 'regGFX_IMU_C2PMSG_4', - 'regGFX_IMU_C2PMSG_40', 'regGFX_IMU_C2PMSG_40_BASE_IDX', - 'regGFX_IMU_C2PMSG_41', 'regGFX_IMU_C2PMSG_41_BASE_IDX', - 'regGFX_IMU_C2PMSG_42', 'regGFX_IMU_C2PMSG_42_BASE_IDX', - 'regGFX_IMU_C2PMSG_43', 'regGFX_IMU_C2PMSG_43_BASE_IDX', - 'regGFX_IMU_C2PMSG_44', 'regGFX_IMU_C2PMSG_44_BASE_IDX', - 'regGFX_IMU_C2PMSG_45', 'regGFX_IMU_C2PMSG_45_BASE_IDX', - 'regGFX_IMU_C2PMSG_46', 'regGFX_IMU_C2PMSG_46_BASE_IDX', - 'regGFX_IMU_C2PMSG_47', 'regGFX_IMU_C2PMSG_47_BASE_IDX', - 'regGFX_IMU_C2PMSG_4_BASE_IDX', 'regGFX_IMU_C2PMSG_5', - 'regGFX_IMU_C2PMSG_5_BASE_IDX', 'regGFX_IMU_C2PMSG_6', - 'regGFX_IMU_C2PMSG_6_BASE_IDX', 'regGFX_IMU_C2PMSG_7', - 'regGFX_IMU_C2PMSG_7_BASE_IDX', 'regGFX_IMU_C2PMSG_8', - 'regGFX_IMU_C2PMSG_8_BASE_IDX', 'regGFX_IMU_C2PMSG_9', - 'regGFX_IMU_C2PMSG_9_BASE_IDX', 'regGFX_IMU_C2PMSG_ACCESS_CTRL0', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL1', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX', 'regGFX_IMU_CLK_CTRL', - 'regGFX_IMU_CLK_CTRL_BASE_IDX', 'regGFX_IMU_CORE_CTRL', - 'regGFX_IMU_CORE_CTRL_BASE_IDX', 'regGFX_IMU_CORE_INT_STATUS', - 'regGFX_IMU_CORE_INT_STATUS_BASE_IDX', 'regGFX_IMU_CORE_STATUS', - 'regGFX_IMU_CORE_STATUS_BASE_IDX', 'regGFX_IMU_DOORBELL_CONTROL', - 'regGFX_IMU_DOORBELL_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_ACC', - 'regGFX_IMU_DPM_ACC_BASE_IDX', 'regGFX_IMU_DPM_CONTROL', - 'regGFX_IMU_DPM_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_REF_COUNTER', - 'regGFX_IMU_DPM_REF_COUNTER_BASE_IDX', 'regGFX_IMU_D_RAM_ADDR', - 'regGFX_IMU_D_RAM_ADDR_BASE_IDX', 'regGFX_IMU_D_RAM_DATA', - 'regGFX_IMU_D_RAM_DATA_BASE_IDX', 'regGFX_IMU_FENCE_CTRL', - 'regGFX_IMU_FENCE_CTRL_BASE_IDX', 'regGFX_IMU_FENCE_LOG_ADDR', - 'regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX', 'regGFX_IMU_FENCE_LOG_INIT', - 'regGFX_IMU_FENCE_LOG_INIT_BASE_IDX', 'regGFX_IMU_FUSESTRAP', - 'regGFX_IMU_FUSE_CTRL', 'regGFX_IMU_FUSE_CTRL_BASE_IDX', - 'regGFX_IMU_FW_GTS_HI', 'regGFX_IMU_FW_GTS_HI_BASE_IDX', - 'regGFX_IMU_FW_GTS_LO', 'regGFX_IMU_FW_GTS_LO_BASE_IDX', - 'regGFX_IMU_GAP_PWROK', 'regGFX_IMU_GAP_PWROK_BASE_IDX', - 'regGFX_IMU_GFXCLK_BYPASS_CTRL', - 'regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_IH_GASKET_CTRL', - 'regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_ISO_CTRL', 'regGFX_IMU_GFX_ISO_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_RESET_CTRL', 'regGFX_IMU_GFX_RESET_CTRL_BASE_IDX', - 'regGFX_IMU_GTS_OFFSET_HI', 'regGFX_IMU_GTS_OFFSET_HI_BASE_IDX', - 'regGFX_IMU_GTS_OFFSET_LO', 'regGFX_IMU_GTS_OFFSET_LO_BASE_IDX', - 'regGFX_IMU_IH_CTRL_1', 'regGFX_IMU_IH_CTRL_1_BASE_IDX', - 'regGFX_IMU_IH_CTRL_2', 'regGFX_IMU_IH_CTRL_2_BASE_IDX', - 'regGFX_IMU_IH_CTRL_3', 'regGFX_IMU_IH_CTRL_3_BASE_IDX', - 'regGFX_IMU_IH_STATUS', 'regGFX_IMU_IH_STATUS_BASE_IDX', - 'regGFX_IMU_I_RAM_ADDR', 'regGFX_IMU_I_RAM_ADDR_BASE_IDX', - 'regGFX_IMU_I_RAM_DATA', 'regGFX_IMU_I_RAM_DATA_BASE_IDX', - 'regGFX_IMU_MP1_MUTEX', 'regGFX_IMU_MP1_MUTEX_BASE_IDX', - 'regGFX_IMU_MSG_FLAGS', 'regGFX_IMU_MSG_FLAGS_BASE_IDX', - 'regGFX_IMU_PIC_INTR', 'regGFX_IMU_PIC_INTR_BASE_IDX', - 'regGFX_IMU_PIC_INTR_ID', 'regGFX_IMU_PIC_INTR_ID_BASE_IDX', - 'regGFX_IMU_PIC_INT_EDGE', 'regGFX_IMU_PIC_INT_EDGE_BASE_IDX', - 'regGFX_IMU_PIC_INT_LVL', 'regGFX_IMU_PIC_INT_LVL_BASE_IDX', - 'regGFX_IMU_PIC_INT_MASK', 'regGFX_IMU_PIC_INT_MASK_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_0', 'regGFX_IMU_PIC_INT_PRI_0_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_1', 'regGFX_IMU_PIC_INT_PRI_1_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_2', 'regGFX_IMU_PIC_INT_PRI_2_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_3', 'regGFX_IMU_PIC_INT_PRI_3_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_4', 'regGFX_IMU_PIC_INT_PRI_4_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_5', 'regGFX_IMU_PIC_INT_PRI_5_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_6', 'regGFX_IMU_PIC_INT_PRI_6_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_7', 'regGFX_IMU_PIC_INT_PRI_7_BASE_IDX', - 'regGFX_IMU_PIC_INT_STATUS', 'regGFX_IMU_PIC_INT_STATUS_BASE_IDX', - 'regGFX_IMU_PROGRAM_CTR', 'regGFX_IMU_PROGRAM_CTR_BASE_IDX', - 'regGFX_IMU_PWRMGT_IRQ_CTRL', - 'regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX', 'regGFX_IMU_PWROK', - 'regGFX_IMU_PWROKRAW', 'regGFX_IMU_PWROKRAW_BASE_IDX', - 'regGFX_IMU_PWROK_BASE_IDX', 'regGFX_IMU_RESETn', - 'regGFX_IMU_RESETn_BASE_IDX', 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX', - 'regGFX_IMU_RLC_BOOTLOADER_SIZE', - 'regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX', - 'regGFX_IMU_RLC_CG_CTRL', 'regGFX_IMU_RLC_CG_CTRL_BASE_IDX', - 'regGFX_IMU_RLC_CMD', 'regGFX_IMU_RLC_CMD_BASE_IDX', - 'regGFX_IMU_RLC_DATA_0', 'regGFX_IMU_RLC_DATA_0_BASE_IDX', - 'regGFX_IMU_RLC_DATA_1', 'regGFX_IMU_RLC_DATA_1_BASE_IDX', - 'regGFX_IMU_RLC_DATA_2', 'regGFX_IMU_RLC_DATA_2_BASE_IDX', - 'regGFX_IMU_RLC_DATA_3', 'regGFX_IMU_RLC_DATA_3_BASE_IDX', - 'regGFX_IMU_RLC_DATA_4', 'regGFX_IMU_RLC_DATA_4_BASE_IDX', - 'regGFX_IMU_RLC_GTS_OFFSET_HI', - 'regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX', - 'regGFX_IMU_RLC_GTS_OFFSET_LO', - 'regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX', - 'regGFX_IMU_RLC_MSG_STATUS', 'regGFX_IMU_RLC_MSG_STATUS_BASE_IDX', - 'regGFX_IMU_RLC_MUTEX', 'regGFX_IMU_RLC_MUTEX_BASE_IDX', - 'regGFX_IMU_RLC_OVERRIDE', 'regGFX_IMU_RLC_OVERRIDE_BASE_IDX', - 'regGFX_IMU_RLC_RAM_ADDR_HIGH', - 'regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX', - 'regGFX_IMU_RLC_RAM_ADDR_LOW', - 'regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX', 'regGFX_IMU_RLC_RAM_DATA', - 'regGFX_IMU_RLC_RAM_DATA_BASE_IDX', 'regGFX_IMU_RLC_RAM_INDEX', - 'regGFX_IMU_RLC_RAM_INDEX_BASE_IDX', - 'regGFX_IMU_RLC_RESET_VECTOR', - 'regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX', 'regGFX_IMU_RLC_STATUS', - 'regGFX_IMU_RLC_STATUS_BASE_IDX', 'regGFX_IMU_RLC_THROTTLE_GFX', - 'regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX', 'regGFX_IMU_SCRATCH_0', - 'regGFX_IMU_SCRATCH_0_BASE_IDX', 'regGFX_IMU_SCRATCH_1', - 'regGFX_IMU_SCRATCH_10', 'regGFX_IMU_SCRATCH_10_BASE_IDX', - 'regGFX_IMU_SCRATCH_11', 'regGFX_IMU_SCRATCH_11_BASE_IDX', - 'regGFX_IMU_SCRATCH_12', 'regGFX_IMU_SCRATCH_12_BASE_IDX', - 'regGFX_IMU_SCRATCH_13', 'regGFX_IMU_SCRATCH_13_BASE_IDX', - 'regGFX_IMU_SCRATCH_14', 'regGFX_IMU_SCRATCH_14_BASE_IDX', - 'regGFX_IMU_SCRATCH_15', 'regGFX_IMU_SCRATCH_15_BASE_IDX', - 'regGFX_IMU_SCRATCH_1_BASE_IDX', 'regGFX_IMU_SCRATCH_2', - 'regGFX_IMU_SCRATCH_2_BASE_IDX', 'regGFX_IMU_SCRATCH_3', - 'regGFX_IMU_SCRATCH_3_BASE_IDX', 'regGFX_IMU_SCRATCH_4', - 'regGFX_IMU_SCRATCH_4_BASE_IDX', 'regGFX_IMU_SCRATCH_5', - 'regGFX_IMU_SCRATCH_5_BASE_IDX', 'regGFX_IMU_SCRATCH_6', - 'regGFX_IMU_SCRATCH_6_BASE_IDX', 'regGFX_IMU_SCRATCH_7', - 'regGFX_IMU_SCRATCH_7_BASE_IDX', 'regGFX_IMU_SCRATCH_8', - 'regGFX_IMU_SCRATCH_8_BASE_IDX', 'regGFX_IMU_SCRATCH_9', - 'regGFX_IMU_SCRATCH_9_BASE_IDX', 'regGFX_IMU_SMUIO_VIDCHG_CTRL', - 'regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX', 'regGFX_IMU_SOC_ADDR', - 'regGFX_IMU_SOC_ADDR_BASE_IDX', 'regGFX_IMU_SOC_DATA', - 'regGFX_IMU_SOC_DATA_BASE_IDX', 'regGFX_IMU_SOC_REQ', - 'regGFX_IMU_SOC_REQ_BASE_IDX', 'regGFX_IMU_STATUS', - 'regGFX_IMU_STATUS_BASE_IDX', 'regGFX_IMU_TELEMETRY', - 'regGFX_IMU_TELEMETRY_BASE_IDX', 'regGFX_IMU_TELEMETRY_DATA', - 'regGFX_IMU_TELEMETRY_DATA_BASE_IDX', - 'regGFX_IMU_TELEMETRY_TEMPERATURE', - 'regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP0', 'regGFX_IMU_TIMER0_CMP0_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP1', 'regGFX_IMU_TIMER0_CMP1_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP3', 'regGFX_IMU_TIMER0_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP_AUTOINC', - 'regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP_INTEN', - 'regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL0', - 'regGFX_IMU_TIMER0_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL1', - 'regGFX_IMU_TIMER0_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER0_VALUE', - 'regGFX_IMU_TIMER0_VALUE_BASE_IDX', 'regGFX_IMU_TIMER1_CMP0', - 'regGFX_IMU_TIMER1_CMP0_BASE_IDX', 'regGFX_IMU_TIMER1_CMP1', - 'regGFX_IMU_TIMER1_CMP1_BASE_IDX', 'regGFX_IMU_TIMER1_CMP3', - 'regGFX_IMU_TIMER1_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER1_CMP_AUTOINC', - 'regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER1_CMP_INTEN', - 'regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL0', - 'regGFX_IMU_TIMER1_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL1', - 'regGFX_IMU_TIMER1_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER1_VALUE', - 'regGFX_IMU_TIMER1_VALUE_BASE_IDX', 'regGFX_IMU_TIMER2_CMP0', - 'regGFX_IMU_TIMER2_CMP0_BASE_IDX', 'regGFX_IMU_TIMER2_CMP1', - 'regGFX_IMU_TIMER2_CMP1_BASE_IDX', 'regGFX_IMU_TIMER2_CMP3', - 'regGFX_IMU_TIMER2_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER2_CMP_AUTOINC', - 'regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER2_CMP_INTEN', - 'regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL0', - 'regGFX_IMU_TIMER2_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL1', - 'regGFX_IMU_TIMER2_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER2_VALUE', - 'regGFX_IMU_TIMER2_VALUE_BASE_IDX', 'regGFX_IMU_VDCI_RESET_CTRL', - 'regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX', 'regGFX_IMU_VF_CTRL', - 'regGFX_IMU_VF_CTRL_BASE_IDX', 'regGFX_PIPE_CONTROL', - 'regGFX_PIPE_CONTROL_BASE_IDX', 'regGFX_PIPE_PRIORITY', - 'regGFX_PIPE_PRIORITY_BASE_IDX', 'regGL1A_PERFCOUNTER0_HI', - 'regGL1A_PERFCOUNTER0_HI_BASE_IDX', 'regGL1A_PERFCOUNTER0_LO', - 'regGL1A_PERFCOUNTER0_LO_BASE_IDX', 'regGL1A_PERFCOUNTER0_SELECT', - 'regGL1A_PERFCOUNTER0_SELECT1', - 'regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER1_HI', - 'regGL1A_PERFCOUNTER1_HI_BASE_IDX', 'regGL1A_PERFCOUNTER1_LO', - 'regGL1A_PERFCOUNTER1_LO_BASE_IDX', 'regGL1A_PERFCOUNTER1_SELECT', - 'regGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER2_HI', - 'regGL1A_PERFCOUNTER2_HI_BASE_IDX', 'regGL1A_PERFCOUNTER2_LO', - 'regGL1A_PERFCOUNTER2_LO_BASE_IDX', 'regGL1A_PERFCOUNTER2_SELECT', - 'regGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER3_HI', - 'regGL1A_PERFCOUNTER3_HI_BASE_IDX', 'regGL1A_PERFCOUNTER3_LO', - 'regGL1A_PERFCOUNTER3_LO_BASE_IDX', 'regGL1A_PERFCOUNTER3_SELECT', - 'regGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER0_HI', - 'regGL1C_PERFCOUNTER0_HI_BASE_IDX', 'regGL1C_PERFCOUNTER0_LO', - 'regGL1C_PERFCOUNTER0_LO_BASE_IDX', 'regGL1C_PERFCOUNTER0_SELECT', - 'regGL1C_PERFCOUNTER0_SELECT1', - 'regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER1_HI', - 'regGL1C_PERFCOUNTER1_HI_BASE_IDX', 'regGL1C_PERFCOUNTER1_LO', - 'regGL1C_PERFCOUNTER1_LO_BASE_IDX', 'regGL1C_PERFCOUNTER1_SELECT', - 'regGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER2_HI', - 'regGL1C_PERFCOUNTER2_HI_BASE_IDX', 'regGL1C_PERFCOUNTER2_LO', - 'regGL1C_PERFCOUNTER2_LO_BASE_IDX', 'regGL1C_PERFCOUNTER2_SELECT', - 'regGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER3_HI', - 'regGL1C_PERFCOUNTER3_HI_BASE_IDX', 'regGL1C_PERFCOUNTER3_LO', - 'regGL1C_PERFCOUNTER3_LO_BASE_IDX', 'regGL1C_PERFCOUNTER3_SELECT', - 'regGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_STATUS', - 'regGL1C_STATUS_BASE_IDX', 'regGL1C_UTCL0_CNTL1', - 'regGL1C_UTCL0_CNTL1_BASE_IDX', 'regGL1C_UTCL0_CNTL2', - 'regGL1C_UTCL0_CNTL2_BASE_IDX', 'regGL1C_UTCL0_RETRY', - 'regGL1C_UTCL0_RETRY_BASE_IDX', 'regGL1C_UTCL0_STATUS', - 'regGL1C_UTCL0_STATUS_BASE_IDX', 'regGL1H_ARB_CTRL', - 'regGL1H_ARB_CTRL_BASE_IDX', 'regGL1H_ARB_STATUS', - 'regGL1H_ARB_STATUS_BASE_IDX', 'regGL1H_BURST_CTRL', - 'regGL1H_BURST_CTRL_BASE_IDX', 'regGL1H_BURST_MASK', - 'regGL1H_BURST_MASK_BASE_IDX', 'regGL1H_GL1_CREDITS', - 'regGL1H_GL1_CREDITS_BASE_IDX', 'regGL1H_ICG_CTRL', - 'regGL1H_ICG_CTRL_BASE_IDX', 'regGL1H_PERFCOUNTER0_HI', - 'regGL1H_PERFCOUNTER0_HI_BASE_IDX', 'regGL1H_PERFCOUNTER0_LO', - 'regGL1H_PERFCOUNTER0_LO_BASE_IDX', 'regGL1H_PERFCOUNTER0_SELECT', - 'regGL1H_PERFCOUNTER0_SELECT1', - 'regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1H_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER1_HI', - 'regGL1H_PERFCOUNTER1_HI_BASE_IDX', 'regGL1H_PERFCOUNTER1_LO', - 'regGL1H_PERFCOUNTER1_LO_BASE_IDX', 'regGL1H_PERFCOUNTER1_SELECT', - 'regGL1H_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER2_HI', - 'regGL1H_PERFCOUNTER2_HI_BASE_IDX', 'regGL1H_PERFCOUNTER2_LO', - 'regGL1H_PERFCOUNTER2_LO_BASE_IDX', 'regGL1H_PERFCOUNTER2_SELECT', - 'regGL1H_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER3_HI', - 'regGL1H_PERFCOUNTER3_HI_BASE_IDX', 'regGL1H_PERFCOUNTER3_LO', - 'regGL1H_PERFCOUNTER3_LO_BASE_IDX', 'regGL1H_PERFCOUNTER3_SELECT', - 'regGL1H_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGL1I_GL1R_MGCG_OVERRIDE', - 'regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX', - 'regGL1I_GL1R_REP_FGCG_OVERRIDE', - 'regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX', 'regGL1_ARB_STATUS', - 'regGL1_ARB_STATUS_BASE_IDX', 'regGL1_DRAM_BURST_MASK', - 'regGL1_DRAM_BURST_MASK_BASE_IDX', 'regGL1_PIPE_STEER', - 'regGL1_PIPE_STEER_BASE_IDX', 'regGL2A_ADDR_MATCH_CTRL', - 'regGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'regGL2A_ADDR_MATCH_MASK', - 'regGL2A_ADDR_MATCH_MASK_BASE_IDX', 'regGL2A_ADDR_MATCH_SIZE', - 'regGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2A_PERFCOUNTER0_HI', - 'regGL2A_PERFCOUNTER0_HI_BASE_IDX', 'regGL2A_PERFCOUNTER0_LO', - 'regGL2A_PERFCOUNTER0_LO_BASE_IDX', 'regGL2A_PERFCOUNTER0_SELECT', - 'regGL2A_PERFCOUNTER0_SELECT1', - 'regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER1_HI', - 'regGL2A_PERFCOUNTER1_HI_BASE_IDX', 'regGL2A_PERFCOUNTER1_LO', - 'regGL2A_PERFCOUNTER1_LO_BASE_IDX', 'regGL2A_PERFCOUNTER1_SELECT', - 'regGL2A_PERFCOUNTER1_SELECT1', - 'regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER2_HI', - 'regGL2A_PERFCOUNTER2_HI_BASE_IDX', 'regGL2A_PERFCOUNTER2_LO', - 'regGL2A_PERFCOUNTER2_LO_BASE_IDX', 'regGL2A_PERFCOUNTER2_SELECT', - 'regGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER3_HI', - 'regGL2A_PERFCOUNTER3_HI_BASE_IDX', 'regGL2A_PERFCOUNTER3_LO', - 'regGL2A_PERFCOUNTER3_LO_BASE_IDX', 'regGL2A_PERFCOUNTER3_SELECT', - 'regGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2A_PRIORITY_CTRL', - 'regGL2A_PRIORITY_CTRL_BASE_IDX', 'regGL2A_RESP_THROTTLE_CTRL', - 'regGL2A_RESP_THROTTLE_CTRL_BASE_IDX', 'regGL2C_ADDR_MATCH_MASK', - 'regGL2C_ADDR_MATCH_MASK_BASE_IDX', 'regGL2C_ADDR_MATCH_SIZE', - 'regGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2C_CM_CTRL0', - 'regGL2C_CM_CTRL0_BASE_IDX', 'regGL2C_CM_CTRL1', - 'regGL2C_CM_CTRL1_BASE_IDX', 'regGL2C_CM_STALL', - 'regGL2C_CM_STALL_BASE_IDX', 'regGL2C_CTRL', 'regGL2C_CTRL2', - 'regGL2C_CTRL2_BASE_IDX', 'regGL2C_CTRL3', - 'regGL2C_CTRL3_BASE_IDX', 'regGL2C_CTRL4', - 'regGL2C_CTRL4_BASE_IDX', 'regGL2C_CTRL_BASE_IDX', - 'regGL2C_DISCARD_STALL_CTRL', - 'regGL2C_DISCARD_STALL_CTRL_BASE_IDX', 'regGL2C_LB_CTR_CTRL', - 'regGL2C_LB_CTR_CTRL_BASE_IDX', 'regGL2C_LB_CTR_SEL0', - 'regGL2C_LB_CTR_SEL0_BASE_IDX', 'regGL2C_LB_CTR_SEL1', - 'regGL2C_LB_CTR_SEL1_BASE_IDX', 'regGL2C_LB_DATA0', - 'regGL2C_LB_DATA0_BASE_IDX', 'regGL2C_LB_DATA1', - 'regGL2C_LB_DATA1_BASE_IDX', 'regGL2C_LB_DATA2', - 'regGL2C_LB_DATA2_BASE_IDX', 'regGL2C_LB_DATA3', - 'regGL2C_LB_DATA3_BASE_IDX', 'regGL2C_PERFCOUNTER0_HI', - 'regGL2C_PERFCOUNTER0_HI_BASE_IDX', 'regGL2C_PERFCOUNTER0_LO', - 'regGL2C_PERFCOUNTER0_LO_BASE_IDX', 'regGL2C_PERFCOUNTER0_SELECT', - 'regGL2C_PERFCOUNTER0_SELECT1', - 'regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER1_HI', - 'regGL2C_PERFCOUNTER1_HI_BASE_IDX', 'regGL2C_PERFCOUNTER1_LO', - 'regGL2C_PERFCOUNTER1_LO_BASE_IDX', 'regGL2C_PERFCOUNTER1_SELECT', - 'regGL2C_PERFCOUNTER1_SELECT1', - 'regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER2_HI', - 'regGL2C_PERFCOUNTER2_HI_BASE_IDX', 'regGL2C_PERFCOUNTER2_LO', - 'regGL2C_PERFCOUNTER2_LO_BASE_IDX', 'regGL2C_PERFCOUNTER2_SELECT', - 'regGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER3_HI', - 'regGL2C_PERFCOUNTER3_HI_BASE_IDX', 'regGL2C_PERFCOUNTER3_LO', - 'regGL2C_PERFCOUNTER3_LO_BASE_IDX', 'regGL2C_PERFCOUNTER3_SELECT', - 'regGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2C_SOFT_RESET', - 'regGL2C_SOFT_RESET_BASE_IDX', 'regGL2C_WBINVL2', - 'regGL2C_WBINVL2_BASE_IDX', 'regGL2_PIPE_STEER_0', - 'regGL2_PIPE_STEER_0_BASE_IDX', 'regGL2_PIPE_STEER_1', - 'regGL2_PIPE_STEER_1_BASE_IDX', 'regGL2_PIPE_STEER_2', - 'regGL2_PIPE_STEER_2_BASE_IDX', 'regGL2_PIPE_STEER_3', - 'regGL2_PIPE_STEER_3_BASE_IDX', 'regGRBM_CAM_DATA', - 'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_DATA_UPPER', - 'regGRBM_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_CAM_INDEX', - 'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHIP_REVISION', - 'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL', - 'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS', - 'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0', - 'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1', - 'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL', - 'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL', - 'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA', - 'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT', - 'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX', - 'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA', - 'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX', - 'regGRBM_GFX_INDEX_SR_SELECT', - 'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA', - 'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_DATA_UPPER', - 'regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_HYP_CAM_INDEX', - 'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT', - 'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL', - 'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_INVALID_PIPE', - 'regGRBM_INVALID_PIPE_BASE_IDX', 'regGRBM_NOWHERE', - 'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI', - 'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO', - 'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT', - 'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGRBM_PERFCOUNTER0_SELECT_HI', - 'regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX', - 'regGRBM_PERFCOUNTER1_HI', 'regGRBM_PERFCOUNTER1_HI_BASE_IDX', - 'regGRBM_PERFCOUNTER1_LO', 'regGRBM_PERFCOUNTER1_LO_BASE_IDX', - 'regGRBM_PERFCOUNTER1_SELECT', - 'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGRBM_PERFCOUNTER1_SELECT_HI', - 'regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'regGRBM_PWR_CNTL', - 'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX', - 'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR', - 'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX', - 'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0', - 'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1', - 'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2', - 'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3', - 'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4', - 'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5', - 'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6', - 'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7', - 'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI', - 'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE0_PERFCOUNTER_LO', - 'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE0_PERFCOUNTER_SELECT', - 'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_HI', - 'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_LO', - 'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_SELECT', - 'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_HI', - 'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_LO', - 'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_SELECT', - 'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_HI', - 'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_LO', - 'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_SELECT', - 'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_HI', - 'regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_LO', - 'regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_SELECT', - 'regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_HI', - 'regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_LO', - 'regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_SELECT', - 'regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_HI', - 'regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_LO', - 'regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_SELECT', - 'regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL', - 'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SE_REMAP_CNTL', - 'regGRBM_SE_REMAP_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL', - 'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET', - 'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS', - 'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', 'regGRBM_STATUS3', - 'regGRBM_STATUS3_BASE_IDX', 'regGRBM_STATUS_BASE_IDX', - 'regGRBM_STATUS_SE0', 'regGRBM_STATUS_SE0_BASE_IDX', - 'regGRBM_STATUS_SE1', 'regGRBM_STATUS_SE1_BASE_IDX', - 'regGRBM_STATUS_SE2', 'regGRBM_STATUS_SE2_BASE_IDX', - 'regGRBM_STATUS_SE3', 'regGRBM_STATUS_SE3_BASE_IDX', - 'regGRBM_STATUS_SE4', 'regGRBM_STATUS_SE4_BASE_IDX', - 'regGRBM_STATUS_SE5', 'regGRBM_STATUS_SE5_BASE_IDX', - 'regGRBM_TRAP_ADDR', 'regGRBM_TRAP_ADDR_BASE_IDX', - 'regGRBM_TRAP_ADDR_MSK', 'regGRBM_TRAP_ADDR_MSK_BASE_IDX', - 'regGRBM_TRAP_OP', 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD', - 'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK', - 'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END', - 'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', - 'regGRBM_UTCL2_INVAL_RANGE_START', - 'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', - 'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', - 'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX', - 'regGRTAVFS_CLK_CNTL', 'regGRTAVFS_CLK_CNTL_BASE_IDX', - 'regGRTAVFS_GENERAL_0', 'regGRTAVFS_GENERAL_0_BASE_IDX', - 'regGRTAVFS_PSM_CNTL', 'regGRTAVFS_PSM_CNTL_BASE_IDX', - 'regGRTAVFS_RTAVFS_RD_DATA', 'regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_ADDR', - 'regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_CTRL', - 'regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_STATUS', - 'regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX', - 'regGRTAVFS_RTAVFS_WR_DATA', 'regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX', - 'regGRTAVFS_SE_CLK_CNTL', 'regGRTAVFS_SE_CLK_CNTL_BASE_IDX', - 'regGRTAVFS_SE_GENERAL_0', 'regGRTAVFS_SE_GENERAL_0_BASE_IDX', - 'regGRTAVFS_SE_PSM_CNTL', 'regGRTAVFS_SE_PSM_CNTL_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_RD_DATA', - 'regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_ADDR', - 'regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_CTRL', - 'regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_STATUS', - 'regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_WR_DATA', - 'regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX', - 'regGRTAVFS_SE_SOFT_RESET', 'regGRTAVFS_SE_SOFT_RESET_BASE_IDX', - 'regGRTAVFS_SE_TARG_FREQ', 'regGRTAVFS_SE_TARG_FREQ_BASE_IDX', - 'regGRTAVFS_SE_TARG_VOLT', 'regGRTAVFS_SE_TARG_VOLT_BASE_IDX', - 'regGRTAVFS_SOFT_RESET', 'regGRTAVFS_SOFT_RESET_BASE_IDX', - 'regGRTAVFS_TARG_FREQ', 'regGRTAVFS_TARG_FREQ_BASE_IDX', - 'regGRTAVFS_TARG_VOLT', 'regGRTAVFS_TARG_VOLT_BASE_IDX', - 'regGUS_DRAM_COMBINE_FLUSH', 'regGUS_DRAM_COMBINE_FLUSH_BASE_IDX', - 'regGUS_DRAM_COMBINE_RD_WR_EN', - 'regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', - 'regGUS_DRAM_GROUP_BURST', 'regGUS_DRAM_GROUP_BURST_BASE_IDX', - 'regGUS_DRAM_PRI_AGE_COEFF', 'regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_DRAM_PRI_AGE_RATE', 'regGUS_DRAM_PRI_AGE_RATE_BASE_IDX', - 'regGUS_DRAM_PRI_FIXED', 'regGUS_DRAM_PRI_FIXED_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI1', - 'regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI2', - 'regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI3', - 'regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI4', - 'regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI5', - 'regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI1', - 'regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI2', - 'regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI3', - 'regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI4', - 'regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI5', - 'regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', 'regGUS_DRAM_PRI_QUEUING', - 'regGUS_DRAM_PRI_QUEUING_BASE_IDX', - 'regGUS_DRAM_PRI_URGENCY_COEFF', - 'regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_DRAM_PRI_URGENCY_MODE', - 'regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_ERR_STATUS', - 'regGUS_ERR_STATUS_BASE_IDX', 'regGUS_ICG_CTRL', - 'regGUS_ICG_CTRL_BASE_IDX', 'regGUS_IO_GROUP_BURST', - 'regGUS_IO_GROUP_BURST_BASE_IDX', 'regGUS_IO_RD_COMBINE_FLUSH', - 'regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', - 'regGUS_IO_RD_PRI_AGE_COEFF', - 'regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_IO_RD_PRI_AGE_RATE', 'regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', - 'regGUS_IO_RD_PRI_FIXED', 'regGUS_IO_RD_PRI_FIXED_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI1', - 'regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI2', - 'regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI3', - 'regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI4', - 'regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI1', - 'regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI2', - 'regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI3', - 'regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI4', - 'regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_IO_RD_PRI_QUEUING', 'regGUS_IO_RD_PRI_QUEUING_BASE_IDX', - 'regGUS_IO_RD_PRI_URGENCY_COEFF', - 'regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_IO_RD_PRI_URGENCY_MODE', - 'regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX', - 'regGUS_IO_WR_COMBINE_FLUSH', - 'regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX', - 'regGUS_IO_WR_PRI_AGE_COEFF', - 'regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_IO_WR_PRI_AGE_RATE', 'regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX', - 'regGUS_IO_WR_PRI_FIXED', 'regGUS_IO_WR_PRI_FIXED_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI1', - 'regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI2', - 'regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI3', - 'regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI4', - 'regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI1', - 'regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI2', - 'regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI3', - 'regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI4', - 'regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_IO_WR_PRI_QUEUING', 'regGUS_IO_WR_PRI_QUEUING_BASE_IDX', - 'regGUS_IO_WR_PRI_URGENCY_COEFF', - 'regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_IO_WR_PRI_URGENCY_MODE', - 'regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_L1_CH0_CMD_IN', - 'regGUS_L1_CH0_CMD_IN_BASE_IDX', 'regGUS_L1_CH0_CMD_OUT', - 'regGUS_L1_CH0_CMD_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_IN', - 'regGUS_L1_CH0_DATA_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_OUT', - 'regGUS_L1_CH0_DATA_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_U_IN', - 'regGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_U_OUT', - 'regGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_CH1_CMD_IN', - 'regGUS_L1_CH1_CMD_IN_BASE_IDX', 'regGUS_L1_CH1_CMD_OUT', - 'regGUS_L1_CH1_CMD_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_IN', - 'regGUS_L1_CH1_DATA_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_OUT', - 'regGUS_L1_CH1_DATA_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_U_IN', - 'regGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_U_OUT', - 'regGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA0_CMD_IN', - 'regGUS_L1_SA0_CMD_IN_BASE_IDX', 'regGUS_L1_SA0_CMD_OUT', - 'regGUS_L1_SA0_CMD_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_IN', - 'regGUS_L1_SA0_DATA_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_OUT', - 'regGUS_L1_SA0_DATA_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_U_IN', - 'regGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_U_OUT', - 'regGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA1_CMD_IN', - 'regGUS_L1_SA1_CMD_IN_BASE_IDX', 'regGUS_L1_SA1_CMD_OUT', - 'regGUS_L1_SA1_CMD_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_IN', - 'regGUS_L1_SA1_DATA_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_OUT', - 'regGUS_L1_SA1_DATA_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_U_IN', - 'regGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_U_OUT', - 'regGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA2_CMD_IN', - 'regGUS_L1_SA2_CMD_IN_BASE_IDX', 'regGUS_L1_SA2_CMD_OUT', - 'regGUS_L1_SA2_CMD_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_IN', - 'regGUS_L1_SA2_DATA_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_OUT', - 'regGUS_L1_SA2_DATA_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_U_IN', - 'regGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_U_OUT', - 'regGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA3_CMD_IN', - 'regGUS_L1_SA3_CMD_IN_BASE_IDX', 'regGUS_L1_SA3_CMD_OUT', - 'regGUS_L1_SA3_CMD_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_IN', - 'regGUS_L1_SA3_DATA_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_OUT', - 'regGUS_L1_SA3_DATA_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_U_IN', - 'regGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_U_OUT', - 'regGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'regGUS_LATENCY_SAMPLING', - 'regGUS_LATENCY_SAMPLING_BASE_IDX', 'regGUS_MISC', 'regGUS_MISC2', - 'regGUS_MISC2_BASE_IDX', 'regGUS_MISC3', 'regGUS_MISC3_BASE_IDX', - 'regGUS_MISC_BASE_IDX', 'regGUS_PERFCOUNTER0_CFG', - 'regGUS_PERFCOUNTER0_CFG_BASE_IDX', 'regGUS_PERFCOUNTER1_CFG', - 'regGUS_PERFCOUNTER1_CFG_BASE_IDX', 'regGUS_PERFCOUNTER2_HI', - 'regGUS_PERFCOUNTER2_HI_BASE_IDX', 'regGUS_PERFCOUNTER2_LO', - 'regGUS_PERFCOUNTER2_LO_BASE_IDX', 'regGUS_PERFCOUNTER2_MODE', - 'regGUS_PERFCOUNTER2_MODE_BASE_IDX', 'regGUS_PERFCOUNTER2_SELECT', - 'regGUS_PERFCOUNTER2_SELECT1', - 'regGUS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGUS_PERFCOUNTER_HI', - 'regGUS_PERFCOUNTER_HI_BASE_IDX', 'regGUS_PERFCOUNTER_LO', - 'regGUS_PERFCOUNTER_LO_BASE_IDX', 'regGUS_PERFCOUNTER_RSLT_CNTL', - 'regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGUS_SDP_ARB_FINAL', - 'regGUS_SDP_ARB_FINAL_BASE_IDX', 'regGUS_SDP_CREDITS', - 'regGUS_SDP_CREDITS_BASE_IDX', 'regGUS_SDP_ENABLE', - 'regGUS_SDP_ENABLE_BASE_IDX', 'regGUS_SDP_QOS_VC_PRIORITY', - 'regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'regGUS_SDP_REQ_CNTL', - 'regGUS_SDP_REQ_CNTL_BASE_IDX', 'regGUS_SDP_TAG_RESERVE0', - 'regGUS_SDP_TAG_RESERVE0_BASE_IDX', 'regGUS_SDP_TAG_RESERVE1', - 'regGUS_SDP_TAG_RESERVE1_BASE_IDX', 'regGUS_SDP_VCC_RESERVE0', - 'regGUS_SDP_VCC_RESERVE0_BASE_IDX', 'regGUS_SDP_VCC_RESERVE1', - 'regGUS_SDP_VCC_RESERVE1_BASE_IDX', 'regGUS_SDP_VCD_RESERVE0', - 'regGUS_SDP_VCD_RESERVE0_BASE_IDX', 'regGUS_SDP_VCD_RESERVE1', - 'regGUS_SDP_VCD_RESERVE1_BASE_IDX', 'regGUS_WRRSP_FIFO_CNTL', - 'regGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'regIA_ENHANCE', - 'regIA_ENHANCE_BASE_IDX', 'regIA_UTCL1_CNTL', - 'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS', - 'regIA_UTCL1_STATUS_2', 'regIA_UTCL1_STATUS_2_BASE_IDX', - 'regIA_UTCL1_STATUS_BASE_IDX', 'regICG_CHA_CTRL', - 'regICG_CHA_CTRL_BASE_IDX', 'regICG_CHCG_CLK_CTRL', - 'regICG_CHCG_CLK_CTRL_BASE_IDX', 'regICG_CHC_CLK_CTRL', - 'regICG_CHC_CLK_CTRL_BASE_IDX', 'regICG_GL1A_CTRL', - 'regICG_GL1A_CTRL_BASE_IDX', 'regICG_GL1C_CLK_CTRL', - 'regICG_GL1C_CLK_CTRL_BASE_IDX', 'regICG_LDS_CLK_CTRL', - 'regICG_LDS_CLK_CTRL_BASE_IDX', 'regICG_SP_CLK_CTRL', - 'regICG_SP_CLK_CTRL_BASE_IDX', 'regLDS_CONFIG', - 'regLDS_CONFIG_BASE_IDX', 'regPA_CL_CLIP_CNTL', - 'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS', - 'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE', - 'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ', - 'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ', - 'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ', - 'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ', - 'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL', - 'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL', - 'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD', - 'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE', - 'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD', - 'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD', - 'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z', - 'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_UCP_0_W', - 'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X', - 'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y', - 'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z', - 'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W', - 'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X', - 'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y', - 'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z', - 'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W', - 'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X', - 'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y', - 'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z', - 'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W', - 'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X', - 'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y', - 'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z', - 'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W', - 'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X', - 'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y', - 'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z', - 'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W', - 'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X', - 'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y', - 'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z', - 'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET', - 'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10', - 'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11', - 'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12', - 'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13', - 'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14', - 'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15', - 'regPA_CL_VPORT_XOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2', - 'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3', - 'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4', - 'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5', - 'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6', - 'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7', - 'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8', - 'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9', - 'regPA_CL_VPORT_XOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE', - 'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10', - 'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11', - 'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12', - 'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13', - 'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14', - 'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15', - 'regPA_CL_VPORT_XSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2', - 'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3', - 'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4', - 'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5', - 'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6', - 'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7', - 'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8', - 'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9', - 'regPA_CL_VPORT_XSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET', - 'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10', - 'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11', - 'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12', - 'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13', - 'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14', - 'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15', - 'regPA_CL_VPORT_YOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2', - 'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3', - 'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4', - 'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5', - 'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6', - 'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7', - 'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8', - 'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9', - 'regPA_CL_VPORT_YOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE', - 'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10', - 'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11', - 'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12', - 'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13', - 'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14', - 'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15', - 'regPA_CL_VPORT_YSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2', - 'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3', - 'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4', - 'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5', - 'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6', - 'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7', - 'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8', - 'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9', - 'regPA_CL_VPORT_YSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET', - 'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10', - 'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11', - 'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12', - 'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13', - 'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14', - 'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15', - 'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2', - 'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3', - 'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4', - 'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5', - 'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6', - 'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7', - 'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8', - 'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9', - 'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE', - 'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10', - 'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11', - 'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12', - 'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13', - 'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14', - 'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15', - 'regPA_CL_VPORT_ZSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2', - 'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3', - 'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4', - 'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5', - 'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6', - 'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7', - 'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8', - 'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9', - 'regPA_CL_VPORT_ZSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VRS_CNTL', - 'regPA_CL_VRS_CNTL_BASE_IDX', 'regPA_CL_VS_OUT_CNTL', - 'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL', - 'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_PH_ENHANCE', - 'regPA_PH_ENHANCE_BASE_IDX', 'regPA_PH_INTERFACE_FIFO_SIZE', - 'regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_HI', 'regPA_PH_PERFCOUNTER0_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_LO', 'regPA_PH_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_SELECT', 'regPA_PH_PERFCOUNTER0_SELECT1', - 'regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_HI', 'regPA_PH_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_LO', 'regPA_PH_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_SELECT', 'regPA_PH_PERFCOUNTER1_SELECT1', - 'regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_HI', 'regPA_PH_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_LO', 'regPA_PH_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_SELECT', 'regPA_PH_PERFCOUNTER2_SELECT1', - 'regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_HI', 'regPA_PH_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_LO', 'regPA_PH_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_SELECT', 'regPA_PH_PERFCOUNTER3_SELECT1', - 'regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_HI', 'regPA_PH_PERFCOUNTER4_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_LO', 'regPA_PH_PERFCOUNTER4_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_SELECT', - 'regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_HI', 'regPA_PH_PERFCOUNTER5_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_LO', 'regPA_PH_PERFCOUNTER5_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_SELECT', - 'regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_HI', 'regPA_PH_PERFCOUNTER6_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_LO', 'regPA_PH_PERFCOUNTER6_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_SELECT', - 'regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_HI', 'regPA_PH_PERFCOUNTER7_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_LO', 'regPA_PH_PERFCOUNTER7_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_SELECT', - 'regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'regPA_RATE_CNTL', - 'regPA_RATE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG', - 'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0', - 'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', - 'regPA_SC_AA_MASK_X0Y1_X1Y1', - 'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', - 'regPA_SC_ATM_CNTL', 'regPA_SC_ATM_CNTL_BASE_IDX', - 'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_CNTL_2', 'regPA_SC_BINNER_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_CNTL_OVERRIDE', - 'regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_0', - 'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_1', - 'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_2', - 'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_3', - 'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_0', - 'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_1', - 'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_2', - 'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_3', - 'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', - 'regPA_SC_BINNER_TIMEOUT_COUNTER', - 'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', - 'regPA_SC_CENTROID_PRIORITY_0', - 'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX', - 'regPA_SC_CENTROID_PRIORITY_1', - 'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR', - 'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL', - 'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR', - 'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL', - 'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR', - 'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL', - 'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR', - 'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL', - 'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE', - 'regPA_SC_CLIPRECT_RULE_BASE_IDX', - 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', - 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', - 'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX', - 'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX', - 'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1', - 'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2', - 'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_3', - 'regPA_SC_ENHANCE_3_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX', - 'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', - 'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX', - 'regPA_SC_FORCE_EOV_MAX_CNTS', - 'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', - 'regPA_SC_GENERIC_SCISSOR_BR', - 'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', - 'regPA_SC_GENERIC_SCISSOR_TL', - 'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_COUNT', - 'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_V', - 'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE', - 'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LINE_CNTL', - 'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE', - 'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE', - 'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0', - 'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1', - 'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL', - 'regPA_SC_NGG_MODE_CNTL_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_COUNT', - 'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN', - 'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_V', - 'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', - 'regPA_SC_PACKER_WAVE_ID_CNTL', - 'regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX', - 'regPA_SC_PBB_OVERRIDE_FLAG', - 'regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI', - 'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO', - 'regPA_SC_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1', - 'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_SELECT', - 'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_SELECT', - 'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_SELECT', - 'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_SELECT', - 'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_SELECT', - 'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_SELECT', - 'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_SELECT', - 'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', - 'regPA_SC_PKR_WAVE_TABLE_CNTL', - 'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG', - 'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX', - 'regPA_SC_RASTER_CONFIG_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_CONTROL', - 'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MAX_0', - 'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MAX_1', - 'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MIN_0', - 'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MIN_1', - 'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', - 'regPA_SC_SCREEN_SCISSOR_BR', - 'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', - 'regPA_SC_SCREEN_SCISSOR_TL', - 'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL', - 'regPA_SC_SHADER_CONTROL_BASE_IDX', - 'regPA_SC_TILE_STEERING_CREST_OVERRIDE', - 'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', - 'regPA_SC_TILE_STEERING_OVERRIDE', - 'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_COUNT', - 'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H', - 'regPA_SC_TRAP_SCREEN_HV_EN', - 'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_0_BR', - 'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_0_TL', - 'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_10_BR', - 'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_10_TL', - 'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_11_BR', - 'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_11_TL', - 'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_12_BR', - 'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_12_TL', - 'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_13_BR', - 'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_13_TL', - 'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_14_BR', - 'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_14_TL', - 'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_15_BR', - 'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_15_TL', - 'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_1_BR', - 'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_1_TL', - 'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_2_BR', - 'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_2_TL', - 'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_3_BR', - 'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_3_TL', - 'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_4_BR', - 'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_4_TL', - 'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_5_BR', - 'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_5_TL', - 'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_6_BR', - 'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_6_TL', - 'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_7_BR', - 'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_7_TL', - 'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_8_BR', - 'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_8_TL', - 'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_9_BR', - 'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_9_TL', - 'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0', - 'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1', - 'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2', - 'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3', - 'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4', - 'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5', - 'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6', - 'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7', - 'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8', - 'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9', - 'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0', - 'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1', - 'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2', - 'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3', - 'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4', - 'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5', - 'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6', - 'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7', - 'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8', - 'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9', - 'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_VRS_OVERRIDE_CNTL', - 'regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX', 'regPA_SC_VRS_RATE_BASE', - 'regPA_SC_VRS_RATE_BASE_BASE_IDX', 'regPA_SC_VRS_RATE_BASE_EXT', - 'regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX', - 'regPA_SC_VRS_RATE_CACHE_CNTL', - 'regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY', - 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX', - 'regPA_SC_VRS_RATE_SIZE_XY', 'regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX', - 'regPA_SC_VRS_SURFACE_CNTL', 'regPA_SC_VRS_SURFACE_CNTL_1', - 'regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX', - 'regPA_SC_VRS_SURFACE_CNTL_BASE_IDX', 'regPA_SC_WINDOW_OFFSET', - 'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR', - 'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', - 'regPA_SC_WINDOW_SCISSOR_TL', - 'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', 'regPA_STATE_STEREO_X', - 'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL', - 'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS', - 'regPA_SU_CNTL_STATUS_BASE_IDX', - 'regPA_SU_HARDWARE_SCREEN_OFFSET', - 'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL', - 'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL', - 'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', - 'regPA_SU_LINE_STIPPLE_SCALE', - 'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', - 'regPA_SU_LINE_STIPPLE_VALUE', - 'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', - 'regPA_SU_OVER_RASTERIZATION_CNTL', - 'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1', - 'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1', - 'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_SELECT', 'regPA_SU_PERFCOUNTER2_SELECT1', - 'regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_SELECT', 'regPA_SU_PERFCOUNTER3_SELECT1', - 'regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX', - 'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE', - 'regPA_SU_POINT_SIZE_BASE_IDX', - 'regPA_SU_POLY_OFFSET_BACK_OFFSET', - 'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', - 'regPA_SU_POLY_OFFSET_BACK_SCALE', - 'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', - 'regPA_SU_POLY_OFFSET_CLAMP', - 'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', - 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL', - 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', - 'regPA_SU_POLY_OFFSET_FRONT_OFFSET', - 'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', - 'regPA_SU_POLY_OFFSET_FRONT_SCALE', - 'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', - 'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX', - 'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX', - 'regPA_SU_SMALL_PRIM_FILTER_CNTL', - 'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL', - 'regPA_SU_VTX_CNTL_BASE_IDX', 'regPCC_PERF_COUNTER', - 'regPCC_PERF_COUNTER_BASE_IDX', 'regPCC_PWRBRK_HYSTERESIS_CTRL', - 'regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX', - 'regPCC_STALL_PATTERN_1_2', 'regPCC_STALL_PATTERN_1_2_BASE_IDX', - 'regPCC_STALL_PATTERN_3_4', 'regPCC_STALL_PATTERN_3_4_BASE_IDX', - 'regPCC_STALL_PATTERN_5_6', 'regPCC_STALL_PATTERN_5_6_BASE_IDX', - 'regPCC_STALL_PATTERN_7', 'regPCC_STALL_PATTERN_7_BASE_IDX', - 'regPCC_STALL_PATTERN_CTRL', 'regPCC_STALL_PATTERN_CTRL_BASE_IDX', - 'regPC_PERFCOUNTER0_HI', 'regPC_PERFCOUNTER0_HI_BASE_IDX', - 'regPC_PERFCOUNTER0_LO', 'regPC_PERFCOUNTER0_LO_BASE_IDX', - 'regPC_PERFCOUNTER0_SELECT', 'regPC_PERFCOUNTER0_SELECT1', - 'regPC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regPC_PERFCOUNTER1_HI', - 'regPC_PERFCOUNTER1_HI_BASE_IDX', 'regPC_PERFCOUNTER1_LO', - 'regPC_PERFCOUNTER1_LO_BASE_IDX', 'regPC_PERFCOUNTER1_SELECT', - 'regPC_PERFCOUNTER1_SELECT1', - 'regPC_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regPC_PERFCOUNTER2_HI', - 'regPC_PERFCOUNTER2_HI_BASE_IDX', 'regPC_PERFCOUNTER2_LO', - 'regPC_PERFCOUNTER2_LO_BASE_IDX', 'regPC_PERFCOUNTER2_SELECT', - 'regPC_PERFCOUNTER2_SELECT1', - 'regPC_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER2_SELECT_BASE_IDX', 'regPC_PERFCOUNTER3_HI', - 'regPC_PERFCOUNTER3_HI_BASE_IDX', 'regPC_PERFCOUNTER3_LO', - 'regPC_PERFCOUNTER3_LO_BASE_IDX', 'regPC_PERFCOUNTER3_SELECT', - 'regPC_PERFCOUNTER3_SELECT1', - 'regPC_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER3_SELECT_BASE_IDX', 'regPMM_CNTL', - 'regPMM_CNTL2', 'regPMM_CNTL2_BASE_IDX', 'regPMM_CNTL_BASE_IDX', - 'regPMM_STATUS', 'regPMM_STATUS_BASE_IDX', - 'regPWRBRK_PERF_COUNTER', 'regPWRBRK_PERF_COUNTER_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_1_2', - 'regPWRBRK_STALL_PATTERN_1_2_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_3_4', - 'regPWRBRK_STALL_PATTERN_3_4_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_5_6', - 'regPWRBRK_STALL_PATTERN_5_6_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_7', 'regPWRBRK_STALL_PATTERN_7_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_CTRL', - 'regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX', 'regRLC_AUTO_PG_CTRL', - 'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_BUSY_CLK_CNTL', - 'regRLC_BUSY_CLK_CNTL_BASE_IDX', 'regRLC_CAC_MASK_CNTL', - 'regRLC_CAC_MASK_CNTL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', - 'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_3D', - 'regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX', - 'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL', - 'regRLC_CGCG_RAMP_CTRL_3D', 'regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX', - 'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE', - 'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL', - 'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL', - 'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB', - 'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', - 'regRLC_CLK_COUNT_GFXCLK_MSB', - 'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', - 'regRLC_CLK_COUNT_REFCLK_LSB', - 'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', - 'regRLC_CLK_COUNT_REFCLK_MSB', - 'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT', - 'regRLC_CLK_COUNT_STAT_BASE_IDX', - 'regRLC_CLK_RESIDENCY_CNTR_CTRL', - 'regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_CLK_RESIDENCY_EVENT_CNTR', - 'regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_CLK_RESIDENCY_REF_CNTR', - 'regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_CNTL', - 'regRLC_CNTL_BASE_IDX', 'regRLC_CP_EOF_INT', - 'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT', - 'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS', - 'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CP_STAT_INVAL_CTRL', - 'regRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'regRLC_CP_STAT_INVAL_STAT', - 'regRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'regRLC_CSIB_ADDR_HI', - 'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO', - 'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH', - 'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_DS_RESIDENCY_CNTR_CTRL', - 'regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_DS_RESIDENCY_EVENT_CNTR', - 'regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_DS_RESIDENCY_REF_CNTR', - 'regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_DYN_PG_REQUEST', - 'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS', - 'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_F32_UCODE_VERSION', - 'regRLC_F32_UCODE_VERSION_BASE_IDX', 'regRLC_FWL_FIRST_VIOL_ADDR', - 'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL', - 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR', - 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_REF_CNTR', - 'regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX', - 'regRLC_GFX_IH_ARBITER_STAT', - 'regRLC_GFX_IH_ARBITER_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_CTRL', 'regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_OTHER_STAT', - 'regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SDMA_STAT', - 'regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SE_STAT_H', - 'regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SE_STAT_L', - 'regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX', 'regRLC_GFX_IMU_CMD', - 'regRLC_GFX_IMU_CMD_BASE_IDX', 'regRLC_GFX_IMU_DATA_0', - 'regRLC_GFX_IMU_DATA_0_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0', - 'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', - 'regRLC_GPM_CP_DMA_COMPLETE_T1', - 'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0', - 'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1', - 'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX', - 'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX', - 'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX', - 'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX', - 'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX', - 'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX', - 'regRLC_GPM_GENERAL_16', 'regRLC_GPM_GENERAL_16_BASE_IDX', - 'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2', - 'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3', - 'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4', - 'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5', - 'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6', - 'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7', - 'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8', - 'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9', - 'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0', - 'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0', - 'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0', - 'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_IRAM_ADDR', - 'regRLC_GPM_IRAM_ADDR_BASE_IDX', 'regRLC_GPM_IRAM_DATA', - 'regRLC_GPM_IRAM_DATA_BASE_IDX', 'regRLC_GPM_LEGACY_INT_CLEAR', - 'regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX', - 'regRLC_GPM_LEGACY_INT_DISABLE', - 'regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'regRLC_GPM_LEGACY_INT_STAT', - 'regRLC_GPM_LEGACY_INT_STAT_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0', - 'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1', - 'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR', - 'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA', - 'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT', - 'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE', - 'regRLC_GPM_THREAD_ENABLE_BASE_IDX', - 'regRLC_GPM_THREAD_INVALIDATE_CACHE', - 'regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX', - 'regRLC_GPM_THREAD_PRIORITY', - 'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET', - 'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL', - 'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0', - 'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1', - 'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2', - 'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3', - 'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_INT_4', - 'regRLC_GPM_TIMER_INT_4_BASE_IDX', 'regRLC_GPM_TIMER_STAT', - 'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR', - 'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA', - 'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0', - 'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1', - 'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2', - 'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH0_ERROR_1', - 'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH0_ERROR_2', - 'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH1_ERROR_1', - 'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH1_ERROR_2', - 'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH2_ERROR_1', - 'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH2_ERROR_2', - 'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1', - 'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2', - 'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32', - 'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL', - 'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1', - 'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB_2', - 'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1', - 'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB_2', - 'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_SPM_LSB', - 'regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_SPM_MSB', - 'regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX', - 'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX', - 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE', - 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX', - 'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX', - 'regRLC_GPU_IOV_INT_DISABLE', - 'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE', - 'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT', - 'regRLC_GPU_IOV_INT_STAT_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_CNTL', - 'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR', - 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_RD_DATA', - 'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR', - 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_WR_DATA', - 'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', - 'regRLC_GPU_IOV_RLC_RESPONSE', - 'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0', - 'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1', - 'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2', - 'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3', - 'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK', - 'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', - 'regRLC_GPU_IOV_SCRATCH_ADDR', - 'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_SCRATCH_DATA', - 'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', - 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA0_STATUS', - 'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA1_STATUS', - 'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA2_STATUS', - 'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA3_STATUS', - 'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA4_STATUS', - 'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA5_STATUS', - 'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA6_STATUS', - 'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA7_STATUS', - 'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SMU_RESPONSE', - 'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', - 'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', - 'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX', - 'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX', - 'regRLC_GPU_IOV_VM_BUSY_STATUS', - 'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'regRLC_GTS_OFFSET_LSB', - 'regRLC_GTS_OFFSET_LSB_BASE_IDX', 'regRLC_GTS_OFFSET_MSB', - 'regRLC_GTS_OFFSET_MSB_BASE_IDX', 'regRLC_HYP_RLCG_UCODE_CHKSUM', - 'regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX', - 'regRLC_HYP_RLCP_UCODE_CHKSUM', - 'regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX', - 'regRLC_HYP_RLCV_UCODE_CHKSUM', - 'regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'regRLC_HYP_SEMAPHORE_0', - 'regRLC_HYP_SEMAPHORE_0_BASE_IDX', 'regRLC_HYP_SEMAPHORE_1', - 'regRLC_HYP_SEMAPHORE_1_BASE_IDX', 'regRLC_HYP_SEMAPHORE_2', - 'regRLC_HYP_SEMAPHORE_2_BASE_IDX', 'regRLC_HYP_SEMAPHORE_3', - 'regRLC_HYP_SEMAPHORE_3_BASE_IDX', 'regRLC_IH_COOKIE', - 'regRLC_IH_COOKIE_BASE_IDX', 'regRLC_IH_COOKIE_CNTL', - 'regRLC_IH_COOKIE_CNTL_BASE_IDX', 'regRLC_IMU_BOOTLOAD_ADDR_HI', - 'regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX', - 'regRLC_IMU_BOOTLOAD_ADDR_LO', - 'regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX', - 'regRLC_IMU_BOOTLOAD_SIZE', 'regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX', - 'regRLC_IMU_MISC', 'regRLC_IMU_MISC_BASE_IDX', - 'regRLC_IMU_RESET_VECTOR', 'regRLC_IMU_RESET_VECTOR_BASE_IDX', - 'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX', - 'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX', - 'regRLC_LX6_CNTL', 'regRLC_LX6_CNTL_BASE_IDX', - 'regRLC_LX6_DRAM_ADDR', 'regRLC_LX6_DRAM_ADDR_BASE_IDX', - 'regRLC_LX6_DRAM_DATA', 'regRLC_LX6_DRAM_DATA_BASE_IDX', - 'regRLC_LX6_IRAM_ADDR', 'regRLC_LX6_IRAM_ADDR_BASE_IDX', - 'regRLC_LX6_IRAM_DATA', 'regRLC_LX6_IRAM_DATA_BASE_IDX', - 'regRLC_MAX_PG_WGP', 'regRLC_MAX_PG_WGP_BASE_IDX', - 'regRLC_MEM_SLP_CNTL', 'regRLC_MEM_SLP_CNTL_BASE_IDX', - 'regRLC_MGCG_CTRL', 'regRLC_MGCG_CTRL_BASE_IDX', - 'regRLC_PACE_INT_CLEAR', 'regRLC_PACE_INT_CLEAR_BASE_IDX', - 'regRLC_PACE_INT_DISABLE', 'regRLC_PACE_INT_DISABLE_BASE_IDX', - 'regRLC_PACE_INT_FORCE', 'regRLC_PACE_INT_FORCE_BASE_IDX', - 'regRLC_PACE_INT_STAT', 'regRLC_PACE_INT_STAT_BASE_IDX', - 'regRLC_PACE_SCRATCH_ADDR', 'regRLC_PACE_SCRATCH_ADDR_BASE_IDX', - 'regRLC_PACE_SCRATCH_DATA', 'regRLC_PACE_SCRATCH_DATA_BASE_IDX', - 'regRLC_PACE_SPARE_INT', 'regRLC_PACE_SPARE_INT_1', - 'regRLC_PACE_SPARE_INT_1_BASE_IDX', - 'regRLC_PACE_SPARE_INT_BASE_IDX', 'regRLC_PACE_TIMER_CTRL', - 'regRLC_PACE_TIMER_CTRL_BASE_IDX', 'regRLC_PACE_TIMER_INT_0', - 'regRLC_PACE_TIMER_INT_0_BASE_IDX', 'regRLC_PACE_TIMER_INT_1', - 'regRLC_PACE_TIMER_INT_1_BASE_IDX', 'regRLC_PACE_TIMER_STAT', - 'regRLC_PACE_TIMER_STAT_BASE_IDX', 'regRLC_PACE_UCODE_ADDR', - 'regRLC_PACE_UCODE_ADDR_BASE_IDX', 'regRLC_PACE_UCODE_DATA', - 'regRLC_PACE_UCODE_DATA_BASE_IDX', - 'regRLC_PCC_RESIDENCY_CNTR_CTRL', - 'regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_PCC_RESIDENCY_EVENT_CNTR', - 'regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_PCC_RESIDENCY_REF_CNTR', - 'regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX', - 'regRLC_PERFCOUNTER0_HI', 'regRLC_PERFCOUNTER0_HI_BASE_IDX', - 'regRLC_PERFCOUNTER0_LO', 'regRLC_PERFCOUNTER0_LO_BASE_IDX', - 'regRLC_PERFCOUNTER0_SELECT', - 'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI', - 'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO', - 'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT', - 'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL', - 'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_WGP_MASK', - 'regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'regRLC_PG_CNTL', - 'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2', - 'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3', - 'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX', - 'regRLC_POWER_RESIDENCY_CNTR_CTRL', - 'regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_POWER_RESIDENCY_EVENT_CNTR', - 'regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_POWER_RESIDENCY_REF_CNTR', - 'regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_R2I_CNTL_0', - 'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1', - 'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2', - 'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3', - 'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB', - 'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', - 'regRLC_REFCLOCK_TIMESTAMP_MSB', - 'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', - 'regRLC_RLCG_DOORBELL_0_DATA_HI', - 'regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_0_DATA_LO', - 'regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_1_DATA_HI', - 'regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_1_DATA_LO', - 'regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_2_DATA_HI', - 'regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_2_DATA_LO', - 'regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_3_DATA_HI', - 'regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_3_DATA_LO', - 'regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_CNTL', 'regRLC_RLCG_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCG_DOORBELL_RANGE', - 'regRLC_RLCG_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCG_DOORBELL_STAT', 'regRLC_RLCG_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCP_DOORBELL_0_DATA_HI', - 'regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_0_DATA_LO', - 'regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_1_DATA_HI', - 'regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_1_DATA_LO', - 'regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_2_DATA_HI', - 'regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_2_DATA_LO', - 'regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_3_DATA_HI', - 'regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_3_DATA_LO', - 'regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_CNTL', 'regRLC_RLCP_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCP_DOORBELL_RANGE', - 'regRLC_RLCP_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCP_DOORBELL_STAT', 'regRLC_RLCP_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCP_IRAM_ADDR', 'regRLC_RLCP_IRAM_ADDR_BASE_IDX', - 'regRLC_RLCP_IRAM_DATA', 'regRLC_RLCP_IRAM_DATA_BASE_IDX', - 'regRLC_RLCS_ABORTED_PD_SEQUENCE', - 'regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_1', - 'regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_2', - 'regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_3', - 'regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_4', - 'regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS1', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS2', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_STATUS', - 'regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', - 'regRLC_RLCS_CGCG_REQUEST', 'regRLC_RLCS_CGCG_REQUEST_BASE_IDX', - 'regRLC_RLCS_CGCG_STATUS', 'regRLC_RLCS_CGCG_STATUS_BASE_IDX', - 'regRLC_RLCS_CMP_IDLE_CNTL', 'regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX', - 'regRLC_RLCS_CP_DMA_SRCID_OVER', - 'regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX', - 'regRLC_RLCS_CP_INT_CTRL_1', 'regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX', - 'regRLC_RLCS_CP_INT_CTRL_2', 'regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX', - 'regRLC_RLCS_CP_INT_INFO_1', 'regRLC_RLCS_CP_INT_INFO_1_BASE_IDX', - 'regRLC_RLCS_CP_INT_INFO_2', 'regRLC_RLCS_CP_INT_INFO_2_BASE_IDX', - 'regRLC_RLCS_DEC_DUMP_ADDR', 'regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX', - 'regRLC_RLCS_DEC_END', 'regRLC_RLCS_DEC_END_BASE_IDX', - 'regRLC_RLCS_DEC_START', 'regRLC_RLCS_DEC_START_BASE_IDX', - 'regRLC_RLCS_DIDT_FORCE_STALL', - 'regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'regRLC_RLCS_DSM_TRIG', - 'regRLC_RLCS_DSM_TRIG_BASE_IDX', 'regRLC_RLCS_EDC_INT_CNTL', - 'regRLC_RLCS_EDC_INT_CNTL_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_1', - 'regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_2', - 'regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_3', - 'regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_4', - 'regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'regRLC_RLCS_GCR_DATA_0', - 'regRLC_RLCS_GCR_DATA_0_BASE_IDX', 'regRLC_RLCS_GCR_DATA_1', - 'regRLC_RLCS_GCR_DATA_1_BASE_IDX', 'regRLC_RLCS_GCR_DATA_2', - 'regRLC_RLCS_GCR_DATA_2_BASE_IDX', 'regRLC_RLCS_GCR_DATA_3', - 'regRLC_RLCS_GCR_DATA_3_BASE_IDX', 'regRLC_RLCS_GCR_STATUS', - 'regRLC_RLCS_GCR_STATUS_BASE_IDX', 'regRLC_RLCS_GENERAL_0', - 'regRLC_RLCS_GENERAL_0_BASE_IDX', 'regRLC_RLCS_GENERAL_1', - 'regRLC_RLCS_GENERAL_10', 'regRLC_RLCS_GENERAL_10_BASE_IDX', - 'regRLC_RLCS_GENERAL_11', 'regRLC_RLCS_GENERAL_11_BASE_IDX', - 'regRLC_RLCS_GENERAL_12', 'regRLC_RLCS_GENERAL_12_BASE_IDX', - 'regRLC_RLCS_GENERAL_13', 'regRLC_RLCS_GENERAL_13_BASE_IDX', - 'regRLC_RLCS_GENERAL_14', 'regRLC_RLCS_GENERAL_14_BASE_IDX', - 'regRLC_RLCS_GENERAL_15', 'regRLC_RLCS_GENERAL_15_BASE_IDX', - 'regRLC_RLCS_GENERAL_16', 'regRLC_RLCS_GENERAL_16_BASE_IDX', - 'regRLC_RLCS_GENERAL_1_BASE_IDX', 'regRLC_RLCS_GENERAL_2', - 'regRLC_RLCS_GENERAL_2_BASE_IDX', 'regRLC_RLCS_GENERAL_3', - 'regRLC_RLCS_GENERAL_3_BASE_IDX', 'regRLC_RLCS_GENERAL_4', - 'regRLC_RLCS_GENERAL_4_BASE_IDX', 'regRLC_RLCS_GENERAL_5', - 'regRLC_RLCS_GENERAL_5_BASE_IDX', 'regRLC_RLCS_GENERAL_6', - 'regRLC_RLCS_GENERAL_6_BASE_IDX', 'regRLC_RLCS_GENERAL_7', - 'regRLC_RLCS_GENERAL_7_BASE_IDX', 'regRLC_RLCS_GENERAL_8', - 'regRLC_RLCS_GENERAL_8_BASE_IDX', 'regRLC_RLCS_GENERAL_9', - 'regRLC_RLCS_GENERAL_9_BASE_IDX', - 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL', - 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX', - 'regRLC_RLCS_GFX_DS_CNTL', 'regRLC_RLCS_GFX_DS_CNTL_BASE_IDX', - 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO', - 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX', - 'regRLC_RLCS_GFX_RM_CNTL', 'regRLC_RLCS_GFX_RM_CNTL_BASE_IDX', - 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE', - 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'regRLC_RLCS_GPM_LEGACY_INT_STAT', - 'regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', - 'regRLC_RLCS_GPM_STAT', 'regRLC_RLCS_GPM_STAT_2', - 'regRLC_RLCS_GPM_STAT_2_BASE_IDX', - 'regRLC_RLCS_GPM_STAT_BASE_IDX', - 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL', - 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX', - 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT', - 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX', - 'regRLC_RLCS_GRBM_SOFT_RESET', - 'regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX', - 'regRLC_RLCS_IH_COOKIE_SEMAPHORE', - 'regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', - 'regRLC_RLCS_IH_SEMAPHORE', 'regRLC_RLCS_IH_SEMAPHORE_BASE_IDX', - 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE', - 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB', - 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB', - 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB', - 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB', - 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_CNTL', 'regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_DATA_0', - 'regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_DATA_1', - 'regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_CNTL', - 'regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_CONTROL', - 'regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA0', - 'regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA1', - 'regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA2', - 'regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA3', - 'regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA4', - 'regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL', - 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_STATUS', - 'regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX', - 'regRLC_RLCS_IMU_VIDCHG_CNTL', - 'regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX', - 'regRLC_RLCS_IOV_CMD_STATUS', - 'regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX', - 'regRLC_RLCS_IOV_CNTX_LOC_SIZE', - 'regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX', - 'regRLC_RLCS_IOV_SCH_BLOCK', 'regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX', - 'regRLC_RLCS_IOV_VM_BUSY_STATUS', - 'regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX', - 'regRLC_RLCS_KMD_LOG_CNTL1', 'regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX', - 'regRLC_RLCS_KMD_LOG_CNTL2', 'regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX', - 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE', - 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX', - 'regRLC_RLCS_PG_CHANGE_READ', - 'regRLC_RLCS_PG_CHANGE_READ_BASE_IDX', - 'regRLC_RLCS_PG_CHANGE_STATUS', - 'regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX', - 'regRLC_RLCS_PMM_CGCG_CNTL', 'regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX', - 'regRLC_RLCS_POWER_BRAKE_CNTL', - 'regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX', - 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1', - 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_CNTL', - 'regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_CONTROL', - 'regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_DATA0', - 'regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_STATUS', - 'regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_CNTL_1', - 'regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_CNTL_2', - 'regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_INFO', 'regRLC_RLCS_SDMA_INT_INFO_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_STAT', 'regRLC_RLCS_SDMA_INT_STAT_BASE_IDX', - 'regRLC_RLCS_SOC_DS_CNTL', 'regRLC_RLCS_SOC_DS_CNTL_BASE_IDX', - 'regRLC_RLCS_SPM_INT_CTRL', 'regRLC_RLCS_SPM_INT_CTRL_BASE_IDX', - 'regRLC_RLCS_SPM_INT_INFO_1', - 'regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', - 'regRLC_RLCS_SPM_INT_INFO_2', - 'regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', - 'regRLC_RLCS_SPM_SQTT_MODE', 'regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', - 'regRLC_RLCS_SRM_SRCID_CNTL', - 'regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'regRLC_RLCS_UTCL2_CNTL', - 'regRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'regRLC_RLCS_WGP_READ', - 'regRLC_RLCS_WGP_READ_BASE_IDX', 'regRLC_RLCS_WGP_STATUS', - 'regRLC_RLCS_WGP_STATUS_BASE_IDX', 'regRLC_RLCV_COMMAND', - 'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_DOORBELL_0_DATA_HI', - 'regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_0_DATA_LO', - 'regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_1_DATA_HI', - 'regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_1_DATA_LO', - 'regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_2_DATA_HI', - 'regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_2_DATA_LO', - 'regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_3_DATA_HI', - 'regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_3_DATA_LO', - 'regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_CNTL', 'regRLC_RLCV_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCV_DOORBELL_RANGE', - 'regRLC_RLCV_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCV_DOORBELL_STAT', 'regRLC_RLCV_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCV_IRAM_ADDR', 'regRLC_RLCV_IRAM_ADDR_BASE_IDX', - 'regRLC_RLCV_IRAM_DATA', 'regRLC_RLCV_IRAM_DATA_BASE_IDX', - 'regRLC_RLCV_SAFE_MODE', 'regRLC_RLCV_SAFE_MODE_BASE_IDX', - 'regRLC_RLCV_SPARE_INT', 'regRLC_RLCV_SPARE_INT_1', - 'regRLC_RLCV_SPARE_INT_1_BASE_IDX', - 'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL', - 'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0', - 'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1', - 'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT', - 'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE', - 'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SDMA0_BUSY_STATUS', - 'regRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA0_STATUS', - 'regRLC_SDMA0_STATUS_BASE_IDX', 'regRLC_SDMA1_BUSY_STATUS', - 'regRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA1_STATUS', - 'regRLC_SDMA1_STATUS_BASE_IDX', 'regRLC_SDMA2_BUSY_STATUS', - 'regRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA2_STATUS', - 'regRLC_SDMA2_STATUS_BASE_IDX', 'regRLC_SDMA3_BUSY_STATUS', - 'regRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA3_STATUS', - 'regRLC_SDMA3_STATUS_BASE_IDX', 'regRLC_SEMAPHORE_0', - 'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1', - 'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2', - 'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3', - 'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_BUSY', - 'regRLC_SERDES_BUSY_BASE_IDX', 'regRLC_SERDES_CTRL', - 'regRLC_SERDES_CTRL_BASE_IDX', 'regRLC_SERDES_DATA', - 'regRLC_SERDES_DATA_BASE_IDX', 'regRLC_SERDES_MASK', - 'regRLC_SERDES_MASK_BASE_IDX', 'regRLC_SERDES_RD_DATA_0', - 'regRLC_SERDES_RD_DATA_0_BASE_IDX', 'regRLC_SERDES_RD_DATA_1', - 'regRLC_SERDES_RD_DATA_1_BASE_IDX', 'regRLC_SERDES_RD_DATA_2', - 'regRLC_SERDES_RD_DATA_2_BASE_IDX', 'regRLC_SERDES_RD_DATA_3', - 'regRLC_SERDES_RD_DATA_3_BASE_IDX', 'regRLC_SERDES_RD_INDEX', - 'regRLC_SERDES_RD_INDEX_BASE_IDX', 'regRLC_SMU_ARGUMENT_1', - 'regRLC_SMU_ARGUMENT_1_BASE_IDX', 'regRLC_SMU_ARGUMENT_2', - 'regRLC_SMU_ARGUMENT_2_BASE_IDX', 'regRLC_SMU_ARGUMENT_3', - 'regRLC_SMU_ARGUMENT_3_BASE_IDX', 'regRLC_SMU_ARGUMENT_4', - 'regRLC_SMU_ARGUMENT_4_BASE_IDX', 'regRLC_SMU_ARGUMENT_5', - 'regRLC_SMU_ARGUMENT_5_BASE_IDX', 'regRLC_SMU_CLK_REQ', - 'regRLC_SMU_CLK_REQ_BASE_IDX', 'regRLC_SMU_COMMAND', - 'regRLC_SMU_COMMAND_BASE_IDX', 'regRLC_SMU_MESSAGE', - 'regRLC_SMU_MESSAGE_1', 'regRLC_SMU_MESSAGE_1_BASE_IDX', - 'regRLC_SMU_MESSAGE_2', 'regRLC_SMU_MESSAGE_2_BASE_IDX', - 'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE', - 'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE', - 'regRLC_SPARE_BASE_IDX', 'regRLC_SPARE_INT_0', - 'regRLC_SPARE_INT_0_BASE_IDX', 'regRLC_SPARE_INT_1', - 'regRLC_SPARE_INT_1_BASE_IDX', 'regRLC_SPARE_INT_2', - 'regRLC_SPARE_INT_2_BASE_IDX', 'regRLC_SPM_ACCUM_CTRL', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRLRAM_DATA', - 'regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRL_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS', - 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_ADDR', - 'regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_DATA', - 'regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT', - 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX', - 'regRLC_SPM_ACCUM_MODE', 'regRLC_SPM_ACCUM_MODE_BASE_IDX', - 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED', - 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX', - 'regRLC_SPM_ACCUM_STATUS', 'regRLC_SPM_ACCUM_STATUS_BASE_IDX', - 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR', - 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA', - 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_THRESHOLD', - 'regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX', - 'regRLC_SPM_GFXCLOCK_HIGHCOUNT', - 'regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX', - 'regRLC_SPM_GFXCLOCK_LOWCOUNT', - 'regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX', - 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR', - 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX', - 'regRLC_SPM_GLOBAL_DELAY_IND_DATA', - 'regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX', - 'regRLC_SPM_GLOBAL_MUXSEL_ADDR', - 'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', - 'regRLC_SPM_GLOBAL_MUXSEL_DATA', - 'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'regRLC_SPM_INT_CNTL', - 'regRLC_SPM_INT_CNTL_BASE_IDX', 'regRLC_SPM_INT_INFO_1', - 'regRLC_SPM_INT_INFO_1_BASE_IDX', 'regRLC_SPM_INT_INFO_2', - 'regRLC_SPM_INT_INFO_2_BASE_IDX', 'regRLC_SPM_INT_STATUS', - 'regRLC_SPM_INT_STATUS_BASE_IDX', 'regRLC_SPM_MC_CNTL', - 'regRLC_SPM_MC_CNTL_BASE_IDX', 'regRLC_SPM_MODE', - 'regRLC_SPM_MODE_BASE_IDX', 'regRLC_SPM_PAUSE', - 'regRLC_SPM_PAUSE_BASE_IDX', 'regRLC_SPM_PERFMON_CNTL', - 'regRLC_SPM_PERFMON_CNTL_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_BASE_HI', - 'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_BASE_LO', - 'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_SIZE', - 'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', - 'regRLC_SPM_PERFMON_SEGMENT_SIZE', - 'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', - 'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX', - 'regRLC_SPM_RING_WRPTR', 'regRLC_SPM_RING_WRPTR_BASE_IDX', - 'regRLC_SPM_RSPM_CMD', 'regRLC_SPM_RSPM_CMD_ACK', - 'regRLC_SPM_RSPM_CMD_ACK_BASE_IDX', - 'regRLC_SPM_RSPM_CMD_BASE_IDX', 'regRLC_SPM_RSPM_REQ_DATA_HI', - 'regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX', - 'regRLC_SPM_RSPM_REQ_DATA_LO', - 'regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX', 'regRLC_SPM_RSPM_REQ_OP', - 'regRLC_SPM_RSPM_REQ_OP_BASE_IDX', 'regRLC_SPM_RSPM_RET_DATA', - 'regRLC_SPM_RSPM_RET_DATA_BASE_IDX', 'regRLC_SPM_RSPM_RET_OP', - 'regRLC_SPM_RSPM_RET_OP_BASE_IDX', 'regRLC_SPM_SAMPLE_CNT', - 'regRLC_SPM_SAMPLE_CNT_BASE_IDX', 'regRLC_SPM_SEGMENT_THRESHOLD', - 'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', - 'regRLC_SPM_SE_DELAY_IND_ADDR', - 'regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX', - 'regRLC_SPM_SE_DELAY_IND_DATA', - 'regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX', - 'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', - 'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_DATA_HI', - 'regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_DATA_LO', - 'regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_OP', 'regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX', - 'regRLC_SPM_SE_RSPM_RET_DATA', - 'regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX', - 'regRLC_SPM_SE_RSPM_RET_OP', 'regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX', - 'regRLC_SPM_SPARE', 'regRLC_SPM_SPARE_BASE_IDX', - 'regRLC_SPM_STATUS', 'regRLC_SPM_STATUS_BASE_IDX', - 'regRLC_SPM_THREAD_TRACE_CTRL', - 'regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'regRLC_SPM_UTCL1_CNTL', - 'regRLC_SPM_UTCL1_CNTL_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_1', - 'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_2', - 'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'regRLC_SPP_CAM_ADDR', - 'regRLC_SPP_CAM_ADDR_BASE_IDX', 'regRLC_SPP_CAM_DATA', - 'regRLC_SPP_CAM_DATA_BASE_IDX', 'regRLC_SPP_CAM_EXT_ADDR', - 'regRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'regRLC_SPP_CAM_EXT_DATA', - 'regRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'regRLC_SPP_CTRL', - 'regRLC_SPP_CTRL_BASE_IDX', 'regRLC_SPP_GLOBAL_SH_ID', - 'regRLC_SPP_GLOBAL_SH_ID_BASE_IDX', - 'regRLC_SPP_GLOBAL_SH_ID_VALID', - 'regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX', - 'regRLC_SPP_INFLIGHT_RD_ADDR', - 'regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX', - 'regRLC_SPP_INFLIGHT_RD_DATA', - 'regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'regRLC_SPP_PBB_INFO', - 'regRLC_SPP_PBB_INFO_BASE_IDX', 'regRLC_SPP_PROF_INFO_1', - 'regRLC_SPP_PROF_INFO_1_BASE_IDX', 'regRLC_SPP_PROF_INFO_2', - 'regRLC_SPP_PROF_INFO_2_BASE_IDX', 'regRLC_SPP_PVT_LEVEL_MAX', - 'regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'regRLC_SPP_PVT_STAT_0', - 'regRLC_SPP_PVT_STAT_0_BASE_IDX', 'regRLC_SPP_PVT_STAT_1', - 'regRLC_SPP_PVT_STAT_1_BASE_IDX', 'regRLC_SPP_PVT_STAT_2', - 'regRLC_SPP_PVT_STAT_2_BASE_IDX', 'regRLC_SPP_PVT_STAT_3', - 'regRLC_SPP_PVT_STAT_3_BASE_IDX', 'regRLC_SPP_RESET', - 'regRLC_SPP_RESET_BASE_IDX', 'regRLC_SPP_SHADER_PROFILE_EN', - 'regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX', - 'regRLC_SPP_SSF_CAPTURE_EN', 'regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_0', - 'regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_1', - 'regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_2', - 'regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX', - 'regRLC_SPP_STALL_STATE_UPDATE', - 'regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'regRLC_SPP_STATUS', - 'regRLC_SPP_STATUS_BASE_IDX', 'regRLC_SRM_ARAM_ADDR', - 'regRLC_SRM_ARAM_ADDR_BASE_IDX', 'regRLC_SRM_ARAM_DATA', - 'regRLC_SRM_ARAM_DATA_BASE_IDX', 'regRLC_SRM_CNTL', - 'regRLC_SRM_CNTL_BASE_IDX', 'regRLC_SRM_DRAM_ADDR', - 'regRLC_SRM_DRAM_ADDR_BASE_IDX', 'regRLC_SRM_DRAM_DATA', - 'regRLC_SRM_DRAM_DATA_BASE_IDX', 'regRLC_SRM_GPM_ABORT', - 'regRLC_SRM_GPM_ABORT_BASE_IDX', 'regRLC_SRM_GPM_COMMAND', - 'regRLC_SRM_GPM_COMMAND_BASE_IDX', - 'regRLC_SRM_GPM_COMMAND_STATUS', - 'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_0', - 'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_1', - 'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_2', - 'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_3', - 'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_4', - 'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_5', - 'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_6', - 'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_7', - 'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_0', - 'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_1', - 'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_2', - 'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_3', - 'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_4', - 'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_5', - 'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_6', - 'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_7', - 'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'regRLC_SRM_STAT', - 'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT', - 'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX', - 'regRLC_STAT_BASE_IDX', 'regRLC_UCODE_CNTL', - 'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_ULV_RESIDENCY_CNTR_CTRL', - 'regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_ULV_RESIDENCY_EVENT_CNTR', - 'regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_ULV_RESIDENCY_REF_CNTR', - 'regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_UTCL1_STATUS', - 'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX', - 'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_WGP_STATUS', - 'regRLC_WGP_STATUS_BASE_IDX', 'regRLC_XT_CORE_ALT_RESET_VEC', - 'regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX', - 'regRLC_XT_CORE_FAULT_INFO', 'regRLC_XT_CORE_FAULT_INFO_BASE_IDX', - 'regRLC_XT_CORE_INTERRUPT', 'regRLC_XT_CORE_INTERRUPT_BASE_IDX', - 'regRLC_XT_CORE_RESERVED', 'regRLC_XT_CORE_RESERVED_BASE_IDX', - 'regRLC_XT_CORE_STATUS', 'regRLC_XT_CORE_STATUS_BASE_IDX', - 'regRLC_XT_DOORBELL_0_DATA_HI', - 'regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_0_DATA_LO', - 'regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_1_DATA_HI', - 'regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_1_DATA_LO', - 'regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_2_DATA_HI', - 'regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_2_DATA_LO', - 'regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_3_DATA_HI', - 'regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_3_DATA_LO', - 'regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_CNTL', 'regRLC_XT_DOORBELL_CNTL_BASE_IDX', - 'regRLC_XT_DOORBELL_RANGE', 'regRLC_XT_DOORBELL_RANGE_BASE_IDX', - 'regRLC_XT_DOORBELL_STAT', 'regRLC_XT_DOORBELL_STAT_BASE_IDX', - 'regRLC_XT_INT_VEC_CLEAR', 'regRLC_XT_INT_VEC_CLEAR_BASE_IDX', - 'regRLC_XT_INT_VEC_FORCE', 'regRLC_XT_INT_VEC_FORCE_BASE_IDX', - 'regRLC_XT_INT_VEC_MUX_INT_SEL', - 'regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX', - 'regRLC_XT_INT_VEC_MUX_SEL', 'regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX', - 'regRMI_CLOCK_CNTRL', 'regRMI_CLOCK_CNTRL_BASE_IDX', - 'regRMI_DEMUX_CNTL', 'regRMI_DEMUX_CNTL_BASE_IDX', - 'regRMI_GENERAL_CNTL', 'regRMI_GENERAL_CNTL1', - 'regRMI_GENERAL_CNTL1_BASE_IDX', 'regRMI_GENERAL_CNTL_BASE_IDX', - 'regRMI_GENERAL_STATUS', 'regRMI_GENERAL_STATUS_BASE_IDX', - 'regRMI_PERFCOUNTER0_HI', 'regRMI_PERFCOUNTER0_HI_BASE_IDX', - 'regRMI_PERFCOUNTER0_LO', 'regRMI_PERFCOUNTER0_LO_BASE_IDX', - 'regRMI_PERFCOUNTER0_SELECT', 'regRMI_PERFCOUNTER0_SELECT1', - 'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI', - 'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO', - 'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT', - 'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI', - 'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO', - 'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT', - 'regRMI_PERFCOUNTER2_SELECT1', - 'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI', - 'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO', - 'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT', - 'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL', - 'regRMI_PERF_COUNTER_CNTL_BASE_IDX', - 'regRMI_PROBE_POP_LOGIC_CNTL', - 'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_RB_GLX_CID_MAP', - 'regRMI_RB_GLX_CID_MAP_BASE_IDX', 'regRMI_SCOREBOARD_CNTL', - 'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0', - 'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1', - 'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2', - 'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE', - 'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2', - 'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX', - 'regRMI_TCIW_FORMATTER0_CNTL', - 'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', - 'regRMI_TCIW_FORMATTER1_CNTL', - 'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1', - 'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2', - 'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS', - 'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG', - 'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL', - 'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', - 'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1', - 'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', - 'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG', - 'regRMI_XBAR_CONFIG_BASE_IDX', 'regRTAVFS_RTAVFS_REG_ADDR', - 'regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'regRTAVFS_RTAVFS_WR_DATA', - 'regRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'regSCRATCH_REG0', - 'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1', - 'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2', - 'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3', - 'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4', - 'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5', - 'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6', - 'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7', - 'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_REG_ATOMIC', - 'regSCRATCH_REG_ATOMIC_BASE_IDX', 'regSCRATCH_REG_CMPSWAP_ATOMIC', - 'regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'regSDMA0_AQL_STATUS', - 'regSDMA0_AQL_STATUS_BASE_IDX', 'regSDMA0_ATOMIC_CNTL', - 'regSDMA0_ATOMIC_CNTL_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_HI', - 'regSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_LO', - 'regSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA0_BA_THRESHOLD', - 'regSDMA0_BA_THRESHOLD_BASE_IDX', 'regSDMA0_BROADCAST_UCODE_ADDR', - 'regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX', - 'regSDMA0_BROADCAST_UCODE_DATA', - 'regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA0_CE_CTRL', - 'regSDMA0_CE_CTRL_BASE_IDX', 'regSDMA0_CHICKEN_BITS', - 'regSDMA0_CHICKEN_BITS_2', 'regSDMA0_CHICKEN_BITS_2_BASE_IDX', - 'regSDMA0_CHICKEN_BITS_BASE_IDX', 'regSDMA0_CLOCK_GATING_STATUS', - 'regSDMA0_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA0_CNTL', - 'regSDMA0_CNTL1', 'regSDMA0_CNTL1_BASE_IDX', - 'regSDMA0_CNTL_BASE_IDX', 'regSDMA0_CRD_CNTL', - 'regSDMA0_CRD_CNTL_BASE_IDX', 'regSDMA0_DEC_START', - 'regSDMA0_DEC_START_BASE_IDX', 'regSDMA0_EA_DBIT_ADDR_DATA', - 'regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX', - 'regSDMA0_EA_DBIT_ADDR_INDEX', - 'regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA0_EDC_CONFIG', - 'regSDMA0_EDC_CONFIG_BASE_IDX', 'regSDMA0_EDC_COUNTER', - 'regSDMA0_EDC_COUNTER_BASE_IDX', 'regSDMA0_EDC_COUNTER_CLEAR', - 'regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA0_ERROR_LOG', - 'regSDMA0_ERROR_LOG_BASE_IDX', 'regSDMA0_F32_CNTL', - 'regSDMA0_F32_CNTL_BASE_IDX', 'regSDMA0_F32_COUNTER', - 'regSDMA0_F32_COUNTER_BASE_IDX', 'regSDMA0_F32_MISC_CNTL', - 'regSDMA0_F32_MISC_CNTL_BASE_IDX', 'regSDMA0_FED_STATUS', - 'regSDMA0_FED_STATUS_BASE_IDX', 'regSDMA0_FREEZE', - 'regSDMA0_FREEZE_BASE_IDX', 'regSDMA0_GB_ADDR_CONFIG', - 'regSDMA0_GB_ADDR_CONFIG_BASE_IDX', - 'regSDMA0_GB_ADDR_CONFIG_READ', - 'regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX', - 'regSDMA0_GLOBAL_QUANTUM', 'regSDMA0_GLOBAL_QUANTUM_BASE_IDX', - 'regSDMA0_GLOBAL_TIMESTAMP_HI', - 'regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'regSDMA0_GLOBAL_TIMESTAMP_LO', - 'regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', - 'regSDMA0_HBM_PAGE_CONFIG', 'regSDMA0_HBM_PAGE_CONFIG_BASE_IDX', - 'regSDMA0_HOLE_ADDR_HI', 'regSDMA0_HOLE_ADDR_HI_BASE_IDX', - 'regSDMA0_HOLE_ADDR_LO', 'regSDMA0_HOLE_ADDR_LO_BASE_IDX', - 'regSDMA0_IB_OFFSET_FETCH', 'regSDMA0_IB_OFFSET_FETCH_BASE_IDX', - 'regSDMA0_ID', 'regSDMA0_ID_BASE_IDX', 'regSDMA0_INT_STATUS', - 'regSDMA0_INT_STATUS_BASE_IDX', 'regSDMA0_PERFCNT_MISC_CNTL', - 'regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG', - 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG', - 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_HI', - 'regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_LO', - 'regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_HI', 'regSDMA0_PERFCOUNTER0_HI_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_LO', 'regSDMA0_PERFCOUNTER0_LO_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_SELECT', 'regSDMA0_PERFCOUNTER0_SELECT1', - 'regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_HI', 'regSDMA0_PERFCOUNTER1_HI_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_LO', 'regSDMA0_PERFCOUNTER1_LO_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_SELECT', 'regSDMA0_PERFCOUNTER1_SELECT1', - 'regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', - 'regSDMA0_PHYSICAL_ADDR_HI', 'regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', - 'regSDMA0_PHYSICAL_ADDR_LO', 'regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', - 'regSDMA0_POWER_CNTL', 'regSDMA0_POWER_CNTL_BASE_IDX', - 'regSDMA0_PROCESS_QUANTUM0', 'regSDMA0_PROCESS_QUANTUM0_BASE_IDX', - 'regSDMA0_PROCESS_QUANTUM1', 'regSDMA0_PROCESS_QUANTUM1_BASE_IDX', - 'regSDMA0_PROGRAM', 'regSDMA0_PROGRAM_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG0', 'regSDMA0_PUB_DUMMY_REG0_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG1', 'regSDMA0_PUB_DUMMY_REG1_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG2', 'regSDMA0_PUB_DUMMY_REG2_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG3', 'regSDMA0_PUB_DUMMY_REG3_BASE_IDX', - 'regSDMA0_QUEUE0_CONTEXT_STATUS', - 'regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE0_CSA_ADDR_HI', - 'regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_CSA_ADDR_LO', - 'regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL', 'regSDMA0_QUEUE0_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL_LOG', - 'regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL_OFFSET', - 'regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE0_DUMMY_REG', 'regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE0_IB_BASE_HI', - 'regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE0_IB_BASE_LO', - 'regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE0_IB_CNTL', - 'regSDMA0_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_IB_OFFSET', - 'regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE0_IB_RPTR', - 'regSDMA0_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_IB_SIZE', - 'regSDMA0_QUEUE0_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE0_IB_SUB_REMAIN', - 'regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_CNTL', - 'regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA0', - 'regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA1', 'regSDMA0_QUEUE0_MIDCMD_DATA10', - 'regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA2', - 'regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA3', - 'regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA4', - 'regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA5', - 'regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA6', - 'regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA7', - 'regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA8', - 'regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA9', - 'regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE0_PREEMPT', 'regSDMA0_QUEUE0_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE0_RB_AQL_CNTL', - 'regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE', - 'regSDMA0_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE_HI', - 'regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_CNTL', - 'regSDMA0_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_PREEMPT', - 'regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR_HI', - 'regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR', - 'regSDMA0_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR_HI', - 'regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_SCHEDULE_CNTL', - 'regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE0_SKIP_CNTL', 'regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_CONTEXT_STATUS', - 'regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE1_CSA_ADDR_HI', - 'regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_CSA_ADDR_LO', - 'regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL', 'regSDMA0_QUEUE1_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL_LOG', - 'regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL_OFFSET', - 'regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE1_DUMMY_REG', 'regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE1_IB_BASE_HI', - 'regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE1_IB_BASE_LO', - 'regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE1_IB_CNTL', - 'regSDMA0_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_IB_OFFSET', - 'regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE1_IB_RPTR', - 'regSDMA0_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_IB_SIZE', - 'regSDMA0_QUEUE1_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE1_IB_SUB_REMAIN', - 'regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_CNTL', - 'regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA0', - 'regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA1', 'regSDMA0_QUEUE1_MIDCMD_DATA10', - 'regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA2', - 'regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA3', - 'regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA4', - 'regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA5', - 'regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA6', - 'regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA7', - 'regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA8', - 'regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA9', - 'regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE1_PREEMPT', 'regSDMA0_QUEUE1_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE1_RB_AQL_CNTL', - 'regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE', - 'regSDMA0_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE_HI', - 'regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_CNTL', - 'regSDMA0_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_PREEMPT', - 'regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR_HI', - 'regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR', - 'regSDMA0_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR_HI', - 'regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_SCHEDULE_CNTL', - 'regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_SKIP_CNTL', 'regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_CONTEXT_STATUS', - 'regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE2_CSA_ADDR_HI', - 'regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_CSA_ADDR_LO', - 'regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL', 'regSDMA0_QUEUE2_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL_LOG', - 'regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL_OFFSET', - 'regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE2_DUMMY_REG', 'regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE2_IB_BASE_HI', - 'regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE2_IB_BASE_LO', - 'regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE2_IB_CNTL', - 'regSDMA0_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_IB_OFFSET', - 'regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE2_IB_RPTR', - 'regSDMA0_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_IB_SIZE', - 'regSDMA0_QUEUE2_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE2_IB_SUB_REMAIN', - 'regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_CNTL', - 'regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA0', - 'regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA1', 'regSDMA0_QUEUE2_MIDCMD_DATA10', - 'regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA2', - 'regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA3', - 'regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA4', - 'regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA5', - 'regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA6', - 'regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA7', - 'regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA8', - 'regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA9', - 'regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE2_PREEMPT', 'regSDMA0_QUEUE2_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE2_RB_AQL_CNTL', - 'regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE', - 'regSDMA0_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE_HI', - 'regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_CNTL', - 'regSDMA0_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_PREEMPT', - 'regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR_HI', - 'regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR', - 'regSDMA0_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR_HI', - 'regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_SCHEDULE_CNTL', - 'regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_SKIP_CNTL', 'regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_CONTEXT_STATUS', - 'regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE3_CSA_ADDR_HI', - 'regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_CSA_ADDR_LO', - 'regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL', 'regSDMA0_QUEUE3_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL_LOG', - 'regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL_OFFSET', - 'regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE3_DUMMY_REG', 'regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE3_IB_BASE_HI', - 'regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE3_IB_BASE_LO', - 'regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE3_IB_CNTL', - 'regSDMA0_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_IB_OFFSET', - 'regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE3_IB_RPTR', - 'regSDMA0_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_IB_SIZE', - 'regSDMA0_QUEUE3_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE3_IB_SUB_REMAIN', - 'regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_CNTL', - 'regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA0', - 'regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA1', 'regSDMA0_QUEUE3_MIDCMD_DATA10', - 'regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA2', - 'regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA3', - 'regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA4', - 'regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA5', - 'regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA6', - 'regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA7', - 'regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA8', - 'regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA9', - 'regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE3_PREEMPT', 'regSDMA0_QUEUE3_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE3_RB_AQL_CNTL', - 'regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE', - 'regSDMA0_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE_HI', - 'regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_CNTL', - 'regSDMA0_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_PREEMPT', - 'regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR_HI', - 'regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR', - 'regSDMA0_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR_HI', - 'regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_SCHEDULE_CNTL', - 'regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_SKIP_CNTL', 'regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_CONTEXT_STATUS', - 'regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE4_CSA_ADDR_HI', - 'regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_CSA_ADDR_LO', - 'regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL', 'regSDMA0_QUEUE4_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL_LOG', - 'regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL_OFFSET', - 'regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE4_DUMMY_REG', 'regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE4_IB_BASE_HI', - 'regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE4_IB_BASE_LO', - 'regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE4_IB_CNTL', - 'regSDMA0_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_IB_OFFSET', - 'regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE4_IB_RPTR', - 'regSDMA0_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_IB_SIZE', - 'regSDMA0_QUEUE4_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE4_IB_SUB_REMAIN', - 'regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_CNTL', - 'regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA0', - 'regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA1', 'regSDMA0_QUEUE4_MIDCMD_DATA10', - 'regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA2', - 'regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA3', - 'regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA4', - 'regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA5', - 'regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA6', - 'regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA7', - 'regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA8', - 'regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA9', - 'regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE4_PREEMPT', 'regSDMA0_QUEUE4_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE4_RB_AQL_CNTL', - 'regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE', - 'regSDMA0_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE_HI', - 'regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_CNTL', - 'regSDMA0_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_PREEMPT', - 'regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR_HI', - 'regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR', - 'regSDMA0_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR_HI', - 'regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_SCHEDULE_CNTL', - 'regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_SKIP_CNTL', 'regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_CONTEXT_STATUS', - 'regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE5_CSA_ADDR_HI', - 'regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_CSA_ADDR_LO', - 'regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL', 'regSDMA0_QUEUE5_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL_LOG', - 'regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL_OFFSET', - 'regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE5_DUMMY_REG', 'regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE5_IB_BASE_HI', - 'regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE5_IB_BASE_LO', - 'regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE5_IB_CNTL', - 'regSDMA0_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_IB_OFFSET', - 'regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE5_IB_RPTR', - 'regSDMA0_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_IB_SIZE', - 'regSDMA0_QUEUE5_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE5_IB_SUB_REMAIN', - 'regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_CNTL', - 'regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA0', - 'regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA1', 'regSDMA0_QUEUE5_MIDCMD_DATA10', - 'regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA2', - 'regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA3', - 'regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA4', - 'regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA5', - 'regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA6', - 'regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA7', - 'regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA8', - 'regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA9', - 'regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE5_PREEMPT', 'regSDMA0_QUEUE5_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE5_RB_AQL_CNTL', - 'regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE', - 'regSDMA0_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE_HI', - 'regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_CNTL', - 'regSDMA0_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_PREEMPT', - 'regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR_HI', - 'regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR', - 'regSDMA0_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR_HI', - 'regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_SCHEDULE_CNTL', - 'regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_SKIP_CNTL', 'regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_CONTEXT_STATUS', - 'regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE6_CSA_ADDR_HI', - 'regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_CSA_ADDR_LO', - 'regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL', 'regSDMA0_QUEUE6_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL_LOG', - 'regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL_OFFSET', - 'regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE6_DUMMY_REG', 'regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE6_IB_BASE_HI', - 'regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE6_IB_BASE_LO', - 'regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE6_IB_CNTL', - 'regSDMA0_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_IB_OFFSET', - 'regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE6_IB_RPTR', - 'regSDMA0_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_IB_SIZE', - 'regSDMA0_QUEUE6_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE6_IB_SUB_REMAIN', - 'regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_CNTL', - 'regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA0', - 'regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA1', 'regSDMA0_QUEUE6_MIDCMD_DATA10', - 'regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA2', - 'regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA3', - 'regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA4', - 'regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA5', - 'regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA6', - 'regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA7', - 'regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA8', - 'regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA9', - 'regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE6_PREEMPT', 'regSDMA0_QUEUE6_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE6_RB_AQL_CNTL', - 'regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE', - 'regSDMA0_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE_HI', - 'regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_CNTL', - 'regSDMA0_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_PREEMPT', - 'regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR_HI', - 'regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR', - 'regSDMA0_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR_HI', - 'regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_SCHEDULE_CNTL', - 'regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_SKIP_CNTL', 'regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_CONTEXT_STATUS', - 'regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE7_CSA_ADDR_HI', - 'regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_CSA_ADDR_LO', - 'regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL', 'regSDMA0_QUEUE7_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL_LOG', - 'regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL_OFFSET', - 'regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE7_DUMMY_REG', 'regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE7_IB_BASE_HI', - 'regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE7_IB_BASE_LO', - 'regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE7_IB_CNTL', - 'regSDMA0_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_IB_OFFSET', - 'regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE7_IB_RPTR', - 'regSDMA0_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_IB_SIZE', - 'regSDMA0_QUEUE7_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE7_IB_SUB_REMAIN', - 'regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_CNTL', - 'regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA0', - 'regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA1', 'regSDMA0_QUEUE7_MIDCMD_DATA10', - 'regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA2', - 'regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA3', - 'regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA4', - 'regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA5', - 'regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA6', - 'regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA7', - 'regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA8', - 'regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA9', - 'regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE7_PREEMPT', 'regSDMA0_QUEUE7_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE7_RB_AQL_CNTL', - 'regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE', - 'regSDMA0_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE_HI', - 'regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_CNTL', - 'regSDMA0_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_PREEMPT', - 'regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR_HI', - 'regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR', - 'regSDMA0_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR_HI', - 'regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_SCHEDULE_CNTL', - 'regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_SKIP_CNTL', 'regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE_RESET_REQ', 'regSDMA0_QUEUE_RESET_REQ_BASE_IDX', - 'regSDMA0_QUEUE_STATUS0', 'regSDMA0_QUEUE_STATUS0_BASE_IDX', - 'regSDMA0_RB_RPTR_FETCH', 'regSDMA0_RB_RPTR_FETCH_BASE_IDX', - 'regSDMA0_RB_RPTR_FETCH_HI', 'regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', - 'regSDMA0_RELAX_ORDERING_LUT', - 'regSDMA0_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA0_RLC_CGCG_CTRL', - 'regSDMA0_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA0_SCRATCH_RAM_ADDR', - 'regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA0_SCRATCH_RAM_DATA', - 'regSDMA0_SCRATCH_RAM_DATA_BASE_IDX', - 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL', - 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'regSDMA0_STATUS1_REG', 'regSDMA0_STATUS1_REG_BASE_IDX', - 'regSDMA0_STATUS2_REG', 'regSDMA0_STATUS2_REG_BASE_IDX', - 'regSDMA0_STATUS3_REG', 'regSDMA0_STATUS3_REG_BASE_IDX', - 'regSDMA0_STATUS4_REG', 'regSDMA0_STATUS4_REG_BASE_IDX', - 'regSDMA0_STATUS5_REG', 'regSDMA0_STATUS5_REG_BASE_IDX', - 'regSDMA0_STATUS6_REG', 'regSDMA0_STATUS6_REG_BASE_IDX', - 'regSDMA0_STATUS_REG', 'regSDMA0_STATUS_REG_BASE_IDX', - 'regSDMA0_TILING_CONFIG', 'regSDMA0_TILING_CONFIG_BASE_IDX', - 'regSDMA0_TIMESTAMP_CNTL', 'regSDMA0_TIMESTAMP_CNTL_BASE_IDX', - 'regSDMA0_TLBI_GCR_CNTL', 'regSDMA0_TLBI_GCR_CNTL_BASE_IDX', - 'regSDMA0_UCODE1_CHECKSUM', 'regSDMA0_UCODE1_CHECKSUM_BASE_IDX', - 'regSDMA0_UCODE_ADDR', 'regSDMA0_UCODE_ADDR_BASE_IDX', - 'regSDMA0_UCODE_CHECKSUM', 'regSDMA0_UCODE_CHECKSUM_BASE_IDX', - 'regSDMA0_UCODE_DATA', 'regSDMA0_UCODE_DATA_BASE_IDX', - 'regSDMA0_UCODE_SELFLOAD_CONTROL', - 'regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA0_UTCL1_CNTL', - 'regSDMA0_UTCL1_CNTL_BASE_IDX', 'regSDMA0_UTCL1_INV0', - 'regSDMA0_UTCL1_INV0_BASE_IDX', 'regSDMA0_UTCL1_INV1', - 'regSDMA0_UTCL1_INV1_BASE_IDX', 'regSDMA0_UTCL1_INV2', - 'regSDMA0_UTCL1_INV2_BASE_IDX', 'regSDMA0_UTCL1_PAGE', - 'regSDMA0_UTCL1_PAGE_BASE_IDX', 'regSDMA0_UTCL1_RD_STATUS', - 'regSDMA0_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK0', - 'regSDMA0_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK1', - 'regSDMA0_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA0_UTCL1_TIMEOUT', - 'regSDMA0_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA0_UTCL1_WATERMK', - 'regSDMA0_UTCL1_WATERMK_BASE_IDX', 'regSDMA0_UTCL1_WR_STATUS', - 'regSDMA0_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK0', - 'regSDMA0_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK1', - 'regSDMA0_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA0_VERSION', - 'regSDMA0_VERSION_BASE_IDX', 'regSDMA0_WATCHDOG_CNTL', - 'regSDMA0_WATCHDOG_CNTL_BASE_IDX', 'regSDMA1_AQL_STATUS', - 'regSDMA1_AQL_STATUS_BASE_IDX', 'regSDMA1_ATOMIC_CNTL', - 'regSDMA1_ATOMIC_CNTL_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_HI', - 'regSDMA1_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_LO', - 'regSDMA1_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA1_BA_THRESHOLD', - 'regSDMA1_BA_THRESHOLD_BASE_IDX', 'regSDMA1_BROADCAST_UCODE_ADDR', - 'regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX', - 'regSDMA1_BROADCAST_UCODE_DATA', - 'regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA1_CE_CTRL', - 'regSDMA1_CE_CTRL_BASE_IDX', 'regSDMA1_CHICKEN_BITS', - 'regSDMA1_CHICKEN_BITS_2', 'regSDMA1_CHICKEN_BITS_2_BASE_IDX', - 'regSDMA1_CHICKEN_BITS_BASE_IDX', 'regSDMA1_CLOCK_GATING_STATUS', - 'regSDMA1_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA1_CNTL', - 'regSDMA1_CNTL1', 'regSDMA1_CNTL1_BASE_IDX', - 'regSDMA1_CNTL_BASE_IDX', 'regSDMA1_CRD_CNTL', - 'regSDMA1_CRD_CNTL_BASE_IDX', 'regSDMA1_DEC_START', - 'regSDMA1_DEC_START_BASE_IDX', 'regSDMA1_EA_DBIT_ADDR_DATA', - 'regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX', - 'regSDMA1_EA_DBIT_ADDR_INDEX', - 'regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA1_EDC_CONFIG', - 'regSDMA1_EDC_CONFIG_BASE_IDX', 'regSDMA1_EDC_COUNTER', - 'regSDMA1_EDC_COUNTER_BASE_IDX', 'regSDMA1_EDC_COUNTER_CLEAR', - 'regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA1_ERROR_LOG', - 'regSDMA1_ERROR_LOG_BASE_IDX', 'regSDMA1_F32_CNTL', - 'regSDMA1_F32_CNTL_BASE_IDX', 'regSDMA1_F32_COUNTER', - 'regSDMA1_F32_COUNTER_BASE_IDX', 'regSDMA1_F32_MISC_CNTL', - 'regSDMA1_F32_MISC_CNTL_BASE_IDX', 'regSDMA1_FED_STATUS', - 'regSDMA1_FED_STATUS_BASE_IDX', 'regSDMA1_FREEZE', - 'regSDMA1_FREEZE_BASE_IDX', 'regSDMA1_GB_ADDR_CONFIG', - 'regSDMA1_GB_ADDR_CONFIG_BASE_IDX', - 'regSDMA1_GB_ADDR_CONFIG_READ', - 'regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX', - 'regSDMA1_GLOBAL_QUANTUM', 'regSDMA1_GLOBAL_QUANTUM_BASE_IDX', - 'regSDMA1_GLOBAL_TIMESTAMP_HI', - 'regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'regSDMA1_GLOBAL_TIMESTAMP_LO', - 'regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', - 'regSDMA1_HBM_PAGE_CONFIG', 'regSDMA1_HBM_PAGE_CONFIG_BASE_IDX', - 'regSDMA1_HOLE_ADDR_HI', 'regSDMA1_HOLE_ADDR_HI_BASE_IDX', - 'regSDMA1_HOLE_ADDR_LO', 'regSDMA1_HOLE_ADDR_LO_BASE_IDX', - 'regSDMA1_IB_OFFSET_FETCH', 'regSDMA1_IB_OFFSET_FETCH_BASE_IDX', - 'regSDMA1_ID', 'regSDMA1_ID_BASE_IDX', 'regSDMA1_INT_STATUS', - 'regSDMA1_INT_STATUS_BASE_IDX', 'regSDMA1_PERFCNT_MISC_CNTL', - 'regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG', - 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG', - 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_HI', - 'regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_LO', - 'regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_HI', 'regSDMA1_PERFCOUNTER0_HI_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_LO', 'regSDMA1_PERFCOUNTER0_LO_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_SELECT', 'regSDMA1_PERFCOUNTER0_SELECT1', - 'regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_HI', 'regSDMA1_PERFCOUNTER1_HI_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_LO', 'regSDMA1_PERFCOUNTER1_LO_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_SELECT', 'regSDMA1_PERFCOUNTER1_SELECT1', - 'regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', - 'regSDMA1_PHYSICAL_ADDR_HI', 'regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', - 'regSDMA1_PHYSICAL_ADDR_LO', 'regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', - 'regSDMA1_POWER_CNTL', 'regSDMA1_POWER_CNTL_BASE_IDX', - 'regSDMA1_PROCESS_QUANTUM0', 'regSDMA1_PROCESS_QUANTUM0_BASE_IDX', - 'regSDMA1_PROCESS_QUANTUM1', 'regSDMA1_PROCESS_QUANTUM1_BASE_IDX', - 'regSDMA1_PROGRAM', 'regSDMA1_PROGRAM_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG0', 'regSDMA1_PUB_DUMMY_REG0_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG1', 'regSDMA1_PUB_DUMMY_REG1_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG2', 'regSDMA1_PUB_DUMMY_REG2_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG3', 'regSDMA1_PUB_DUMMY_REG3_BASE_IDX', - 'regSDMA1_QUEUE0_CONTEXT_STATUS', - 'regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE0_CSA_ADDR_HI', - 'regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_CSA_ADDR_LO', - 'regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL', 'regSDMA1_QUEUE0_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL_LOG', - 'regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL_OFFSET', - 'regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE0_DUMMY_REG', 'regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE0_IB_BASE_HI', - 'regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE0_IB_BASE_LO', - 'regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE0_IB_CNTL', - 'regSDMA1_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_IB_OFFSET', - 'regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE0_IB_RPTR', - 'regSDMA1_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_IB_SIZE', - 'regSDMA1_QUEUE0_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE0_IB_SUB_REMAIN', - 'regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_CNTL', - 'regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA0', - 'regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA1', 'regSDMA1_QUEUE0_MIDCMD_DATA10', - 'regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA2', - 'regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA3', - 'regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA4', - 'regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA5', - 'regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA6', - 'regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA7', - 'regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA8', - 'regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA9', - 'regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE0_PREEMPT', 'regSDMA1_QUEUE0_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE0_RB_AQL_CNTL', - 'regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE', - 'regSDMA1_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE_HI', - 'regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_CNTL', - 'regSDMA1_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_PREEMPT', - 'regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR_HI', - 'regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR', - 'regSDMA1_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR_HI', - 'regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_SCHEDULE_CNTL', - 'regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE0_SKIP_CNTL', 'regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_CONTEXT_STATUS', - 'regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE1_CSA_ADDR_HI', - 'regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_CSA_ADDR_LO', - 'regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL', 'regSDMA1_QUEUE1_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL_LOG', - 'regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL_OFFSET', - 'regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE1_DUMMY_REG', 'regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE1_IB_BASE_HI', - 'regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE1_IB_BASE_LO', - 'regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE1_IB_CNTL', - 'regSDMA1_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_IB_OFFSET', - 'regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE1_IB_RPTR', - 'regSDMA1_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_IB_SIZE', - 'regSDMA1_QUEUE1_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE1_IB_SUB_REMAIN', - 'regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_CNTL', - 'regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA0', - 'regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA1', 'regSDMA1_QUEUE1_MIDCMD_DATA10', - 'regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA2', - 'regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA3', - 'regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA4', - 'regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA5', - 'regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA6', - 'regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA7', - 'regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA8', - 'regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA9', - 'regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE1_PREEMPT', 'regSDMA1_QUEUE1_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE1_RB_AQL_CNTL', - 'regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE', - 'regSDMA1_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE_HI', - 'regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_CNTL', - 'regSDMA1_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_PREEMPT', - 'regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR_HI', - 'regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR', - 'regSDMA1_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR_HI', - 'regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_SCHEDULE_CNTL', - 'regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_SKIP_CNTL', 'regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_CONTEXT_STATUS', - 'regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE2_CSA_ADDR_HI', - 'regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_CSA_ADDR_LO', - 'regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL', 'regSDMA1_QUEUE2_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL_LOG', - 'regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL_OFFSET', - 'regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE2_DUMMY_REG', 'regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE2_IB_BASE_HI', - 'regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE2_IB_BASE_LO', - 'regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE2_IB_CNTL', - 'regSDMA1_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_IB_OFFSET', - 'regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE2_IB_RPTR', - 'regSDMA1_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_IB_SIZE', - 'regSDMA1_QUEUE2_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE2_IB_SUB_REMAIN', - 'regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_CNTL', - 'regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA0', - 'regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA1', 'regSDMA1_QUEUE2_MIDCMD_DATA10', - 'regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA2', - 'regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA3', - 'regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA4', - 'regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA5', - 'regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA6', - 'regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA7', - 'regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA8', - 'regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA9', - 'regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE2_PREEMPT', 'regSDMA1_QUEUE2_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE2_RB_AQL_CNTL', - 'regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE', - 'regSDMA1_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE_HI', - 'regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_CNTL', - 'regSDMA1_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_PREEMPT', - 'regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR_HI', - 'regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR', - 'regSDMA1_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR_HI', - 'regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_SCHEDULE_CNTL', - 'regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_SKIP_CNTL', 'regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_CONTEXT_STATUS', - 'regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE3_CSA_ADDR_HI', - 'regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_CSA_ADDR_LO', - 'regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL', 'regSDMA1_QUEUE3_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL_LOG', - 'regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL_OFFSET', - 'regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE3_DUMMY_REG', 'regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE3_IB_BASE_HI', - 'regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE3_IB_BASE_LO', - 'regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE3_IB_CNTL', - 'regSDMA1_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_IB_OFFSET', - 'regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE3_IB_RPTR', - 'regSDMA1_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_IB_SIZE', - 'regSDMA1_QUEUE3_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE3_IB_SUB_REMAIN', - 'regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_CNTL', - 'regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA0', - 'regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA1', 'regSDMA1_QUEUE3_MIDCMD_DATA10', - 'regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA2', - 'regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA3', - 'regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA4', - 'regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA5', - 'regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA6', - 'regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA7', - 'regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA8', - 'regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA9', - 'regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE3_PREEMPT', 'regSDMA1_QUEUE3_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE3_RB_AQL_CNTL', - 'regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE', - 'regSDMA1_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE_HI', - 'regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_CNTL', - 'regSDMA1_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_PREEMPT', - 'regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR_HI', - 'regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR', - 'regSDMA1_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR_HI', - 'regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_SCHEDULE_CNTL', - 'regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_SKIP_CNTL', 'regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_CONTEXT_STATUS', - 'regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE4_CSA_ADDR_HI', - 'regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_CSA_ADDR_LO', - 'regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL', 'regSDMA1_QUEUE4_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL_LOG', - 'regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL_OFFSET', - 'regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE4_DUMMY_REG', 'regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE4_IB_BASE_HI', - 'regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE4_IB_BASE_LO', - 'regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE4_IB_CNTL', - 'regSDMA1_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_IB_OFFSET', - 'regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE4_IB_RPTR', - 'regSDMA1_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_IB_SIZE', - 'regSDMA1_QUEUE4_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE4_IB_SUB_REMAIN', - 'regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_CNTL', - 'regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA0', - 'regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA1', 'regSDMA1_QUEUE4_MIDCMD_DATA10', - 'regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA2', - 'regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA3', - 'regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA4', - 'regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA5', - 'regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA6', - 'regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA7', - 'regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA8', - 'regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA9', - 'regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE4_PREEMPT', 'regSDMA1_QUEUE4_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE4_RB_AQL_CNTL', - 'regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE', - 'regSDMA1_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE_HI', - 'regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_CNTL', - 'regSDMA1_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_PREEMPT', - 'regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR_HI', - 'regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR', - 'regSDMA1_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR_HI', - 'regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_SCHEDULE_CNTL', - 'regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_SKIP_CNTL', 'regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_CONTEXT_STATUS', - 'regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE5_CSA_ADDR_HI', - 'regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_CSA_ADDR_LO', - 'regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL', 'regSDMA1_QUEUE5_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL_LOG', - 'regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL_OFFSET', - 'regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE5_DUMMY_REG', 'regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE5_IB_BASE_HI', - 'regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE5_IB_BASE_LO', - 'regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE5_IB_CNTL', - 'regSDMA1_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_IB_OFFSET', - 'regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE5_IB_RPTR', - 'regSDMA1_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_IB_SIZE', - 'regSDMA1_QUEUE5_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE5_IB_SUB_REMAIN', - 'regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_CNTL', - 'regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA0', - 'regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA1', 'regSDMA1_QUEUE5_MIDCMD_DATA10', - 'regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA2', - 'regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA3', - 'regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA4', - 'regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA5', - 'regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA6', - 'regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA7', - 'regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA8', - 'regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA9', - 'regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE5_PREEMPT', 'regSDMA1_QUEUE5_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE5_RB_AQL_CNTL', - 'regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE', - 'regSDMA1_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE_HI', - 'regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_CNTL', - 'regSDMA1_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_PREEMPT', - 'regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR_HI', - 'regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR', - 'regSDMA1_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR_HI', - 'regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_SCHEDULE_CNTL', - 'regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_SKIP_CNTL', 'regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_CONTEXT_STATUS', - 'regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE6_CSA_ADDR_HI', - 'regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_CSA_ADDR_LO', - 'regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL', 'regSDMA1_QUEUE6_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL_LOG', - 'regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL_OFFSET', - 'regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE6_DUMMY_REG', 'regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE6_IB_BASE_HI', - 'regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE6_IB_BASE_LO', - 'regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE6_IB_CNTL', - 'regSDMA1_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_IB_OFFSET', - 'regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE6_IB_RPTR', - 'regSDMA1_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_IB_SIZE', - 'regSDMA1_QUEUE6_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE6_IB_SUB_REMAIN', - 'regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_CNTL', - 'regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA0', - 'regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA1', 'regSDMA1_QUEUE6_MIDCMD_DATA10', - 'regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA2', - 'regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA3', - 'regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA4', - 'regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA5', - 'regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA6', - 'regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA7', - 'regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA8', - 'regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA9', - 'regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE6_PREEMPT', 'regSDMA1_QUEUE6_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE6_RB_AQL_CNTL', - 'regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE', - 'regSDMA1_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE_HI', - 'regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_CNTL', - 'regSDMA1_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_PREEMPT', - 'regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR_HI', - 'regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR', - 'regSDMA1_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR_HI', - 'regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_SCHEDULE_CNTL', - 'regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_SKIP_CNTL', 'regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_CONTEXT_STATUS', - 'regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE7_CSA_ADDR_HI', - 'regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_CSA_ADDR_LO', - 'regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL', 'regSDMA1_QUEUE7_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL_LOG', - 'regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL_OFFSET', - 'regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE7_DUMMY_REG', 'regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE7_IB_BASE_HI', - 'regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE7_IB_BASE_LO', - 'regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE7_IB_CNTL', - 'regSDMA1_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_IB_OFFSET', - 'regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE7_IB_RPTR', - 'regSDMA1_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_IB_SIZE', - 'regSDMA1_QUEUE7_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE7_IB_SUB_REMAIN', - 'regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_CNTL', - 'regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA0', - 'regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA1', 'regSDMA1_QUEUE7_MIDCMD_DATA10', - 'regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA2', - 'regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA3', - 'regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA4', - 'regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA5', - 'regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA6', - 'regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA7', - 'regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA8', - 'regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA9', - 'regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE7_PREEMPT', 'regSDMA1_QUEUE7_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE7_RB_AQL_CNTL', - 'regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE', - 'regSDMA1_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE_HI', - 'regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_CNTL', - 'regSDMA1_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_PREEMPT', - 'regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR_HI', - 'regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR', - 'regSDMA1_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR_HI', - 'regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_SCHEDULE_CNTL', - 'regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_SKIP_CNTL', 'regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE_RESET_REQ', 'regSDMA1_QUEUE_RESET_REQ_BASE_IDX', - 'regSDMA1_QUEUE_STATUS0', 'regSDMA1_QUEUE_STATUS0_BASE_IDX', - 'regSDMA1_RB_RPTR_FETCH', 'regSDMA1_RB_RPTR_FETCH_BASE_IDX', - 'regSDMA1_RB_RPTR_FETCH_HI', 'regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', - 'regSDMA1_RELAX_ORDERING_LUT', - 'regSDMA1_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA1_RLC_CGCG_CTRL', - 'regSDMA1_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA1_SCRATCH_RAM_ADDR', - 'regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA1_SCRATCH_RAM_DATA', - 'regSDMA1_SCRATCH_RAM_DATA_BASE_IDX', - 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL', - 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'regSDMA1_STATUS1_REG', 'regSDMA1_STATUS1_REG_BASE_IDX', - 'regSDMA1_STATUS2_REG', 'regSDMA1_STATUS2_REG_BASE_IDX', - 'regSDMA1_STATUS3_REG', 'regSDMA1_STATUS3_REG_BASE_IDX', - 'regSDMA1_STATUS4_REG', 'regSDMA1_STATUS4_REG_BASE_IDX', - 'regSDMA1_STATUS5_REG', 'regSDMA1_STATUS5_REG_BASE_IDX', - 'regSDMA1_STATUS6_REG', 'regSDMA1_STATUS6_REG_BASE_IDX', - 'regSDMA1_STATUS_REG', 'regSDMA1_STATUS_REG_BASE_IDX', - 'regSDMA1_TILING_CONFIG', 'regSDMA1_TILING_CONFIG_BASE_IDX', - 'regSDMA1_TIMESTAMP_CNTL', 'regSDMA1_TIMESTAMP_CNTL_BASE_IDX', - 'regSDMA1_TLBI_GCR_CNTL', 'regSDMA1_TLBI_GCR_CNTL_BASE_IDX', - 'regSDMA1_UCODE1_CHECKSUM', 'regSDMA1_UCODE1_CHECKSUM_BASE_IDX', - 'regSDMA1_UCODE_ADDR', 'regSDMA1_UCODE_ADDR_BASE_IDX', - 'regSDMA1_UCODE_CHECKSUM', 'regSDMA1_UCODE_CHECKSUM_BASE_IDX', - 'regSDMA1_UCODE_DATA', 'regSDMA1_UCODE_DATA_BASE_IDX', - 'regSDMA1_UCODE_SELFLOAD_CONTROL', - 'regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA1_UTCL1_CNTL', - 'regSDMA1_UTCL1_CNTL_BASE_IDX', 'regSDMA1_UTCL1_INV0', - 'regSDMA1_UTCL1_INV0_BASE_IDX', 'regSDMA1_UTCL1_INV1', - 'regSDMA1_UTCL1_INV1_BASE_IDX', 'regSDMA1_UTCL1_INV2', - 'regSDMA1_UTCL1_INV2_BASE_IDX', 'regSDMA1_UTCL1_PAGE', - 'regSDMA1_UTCL1_PAGE_BASE_IDX', 'regSDMA1_UTCL1_RD_STATUS', - 'regSDMA1_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK0', - 'regSDMA1_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK1', - 'regSDMA1_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA1_UTCL1_TIMEOUT', - 'regSDMA1_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA1_UTCL1_WATERMK', - 'regSDMA1_UTCL1_WATERMK_BASE_IDX', 'regSDMA1_UTCL1_WR_STATUS', - 'regSDMA1_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK0', - 'regSDMA1_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK1', - 'regSDMA1_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA1_VERSION', - 'regSDMA1_VERSION_BASE_IDX', 'regSDMA1_WATCHDOG_CNTL', - 'regSDMA1_WATCHDOG_CNTL_BASE_IDX', 'regSE0_CAC_AGGR_GFXCLK_CYCLE', - 'regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE0_CAC_AGGR_LOWER', - 'regSE0_CAC_AGGR_LOWER_BASE_IDX', 'regSE0_CAC_AGGR_UPPER', - 'regSE0_CAC_AGGR_UPPER_BASE_IDX', 'regSE1_CAC_AGGR_GFXCLK_CYCLE', - 'regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE1_CAC_AGGR_LOWER', - 'regSE1_CAC_AGGR_LOWER_BASE_IDX', 'regSE1_CAC_AGGR_UPPER', - 'regSE1_CAC_AGGR_UPPER_BASE_IDX', 'regSE2_CAC_AGGR_GFXCLK_CYCLE', - 'regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE2_CAC_AGGR_LOWER', - 'regSE2_CAC_AGGR_LOWER_BASE_IDX', 'regSE2_CAC_AGGR_UPPER', - 'regSE2_CAC_AGGR_UPPER_BASE_IDX', 'regSE3_CAC_AGGR_GFXCLK_CYCLE', - 'regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE3_CAC_AGGR_LOWER', - 'regSE3_CAC_AGGR_LOWER_BASE_IDX', 'regSE3_CAC_AGGR_UPPER', - 'regSE3_CAC_AGGR_UPPER_BASE_IDX', 'regSE4_CAC_AGGR_GFXCLK_CYCLE', - 'regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE4_CAC_AGGR_LOWER', - 'regSE4_CAC_AGGR_LOWER_BASE_IDX', 'regSE4_CAC_AGGR_UPPER', - 'regSE4_CAC_AGGR_UPPER_BASE_IDX', 'regSE5_CAC_AGGR_GFXCLK_CYCLE', - 'regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE5_CAC_AGGR_LOWER', - 'regSE5_CAC_AGGR_LOWER_BASE_IDX', 'regSE5_CAC_AGGR_UPPER', - 'regSE5_CAC_AGGR_UPPER_BASE_IDX', 'regSEDC_GL1_GL2_OVERRIDES', - 'regSEDC_GL1_GL2_OVERRIDES_BASE_IDX', 'regSE_CAC_CTRL_1', - 'regSE_CAC_CTRL_1_BASE_IDX', 'regSE_CAC_CTRL_2', - 'regSE_CAC_CTRL_2_BASE_IDX', 'regSE_CAC_IND_DATA', - 'regSE_CAC_IND_DATA_BASE_IDX', 'regSE_CAC_IND_INDEX', - 'regSE_CAC_IND_INDEX_BASE_IDX', 'regSE_CAC_WEIGHT_BCI_0', - 'regSE_CAC_WEIGHT_BCI_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_0', - 'regSE_CAC_WEIGHT_CB_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_1', - 'regSE_CAC_WEIGHT_CB_10', 'regSE_CAC_WEIGHT_CB_10_BASE_IDX', - 'regSE_CAC_WEIGHT_CB_11', 'regSE_CAC_WEIGHT_CB_11_BASE_IDX', - 'regSE_CAC_WEIGHT_CB_1_BASE_IDX', 'regSE_CAC_WEIGHT_CB_2', - 'regSE_CAC_WEIGHT_CB_2_BASE_IDX', 'regSE_CAC_WEIGHT_CB_3', - 'regSE_CAC_WEIGHT_CB_3_BASE_IDX', 'regSE_CAC_WEIGHT_CB_4', - 'regSE_CAC_WEIGHT_CB_4_BASE_IDX', 'regSE_CAC_WEIGHT_CB_5', - 'regSE_CAC_WEIGHT_CB_5_BASE_IDX', 'regSE_CAC_WEIGHT_CB_6', - 'regSE_CAC_WEIGHT_CB_6_BASE_IDX', 'regSE_CAC_WEIGHT_CB_7', - 'regSE_CAC_WEIGHT_CB_7_BASE_IDX', 'regSE_CAC_WEIGHT_CB_8', - 'regSE_CAC_WEIGHT_CB_8_BASE_IDX', 'regSE_CAC_WEIGHT_CB_9', - 'regSE_CAC_WEIGHT_CB_9_BASE_IDX', 'regSE_CAC_WEIGHT_CU_0', - 'regSE_CAC_WEIGHT_CU_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_0', - 'regSE_CAC_WEIGHT_DB_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_1', - 'regSE_CAC_WEIGHT_DB_1_BASE_IDX', 'regSE_CAC_WEIGHT_DB_2', - 'regSE_CAC_WEIGHT_DB_2_BASE_IDX', 'regSE_CAC_WEIGHT_DB_3', - 'regSE_CAC_WEIGHT_DB_3_BASE_IDX', 'regSE_CAC_WEIGHT_DB_4', - 'regSE_CAC_WEIGHT_DB_4_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_0', - 'regSE_CAC_WEIGHT_GL1C_0_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_1', - 'regSE_CAC_WEIGHT_GL1C_1_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_2', - 'regSE_CAC_WEIGHT_GL1C_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_0', - 'regSE_CAC_WEIGHT_LDS_0_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_1', - 'regSE_CAC_WEIGHT_LDS_1_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_2', - 'regSE_CAC_WEIGHT_LDS_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_3', - 'regSE_CAC_WEIGHT_LDS_3_BASE_IDX', 'regSE_CAC_WEIGHT_PA_0', - 'regSE_CAC_WEIGHT_PA_0_BASE_IDX', 'regSE_CAC_WEIGHT_PA_1', - 'regSE_CAC_WEIGHT_PA_1_BASE_IDX', 'regSE_CAC_WEIGHT_PA_2', - 'regSE_CAC_WEIGHT_PA_2_BASE_IDX', 'regSE_CAC_WEIGHT_PA_3', - 'regSE_CAC_WEIGHT_PA_3_BASE_IDX', 'regSE_CAC_WEIGHT_PC_0', - 'regSE_CAC_WEIGHT_PC_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_0', - 'regSE_CAC_WEIGHT_RMI_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_1', - 'regSE_CAC_WEIGHT_RMI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_0', - 'regSE_CAC_WEIGHT_SC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SC_1', - 'regSE_CAC_WEIGHT_SC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_2', - 'regSE_CAC_WEIGHT_SC_2_BASE_IDX', 'regSE_CAC_WEIGHT_SC_3', - 'regSE_CAC_WEIGHT_SC_3_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_0', - 'regSE_CAC_WEIGHT_SPI_0_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_1', - 'regSE_CAC_WEIGHT_SPI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_2', - 'regSE_CAC_WEIGHT_SPI_2_BASE_IDX', 'regSE_CAC_WEIGHT_SP_0', - 'regSE_CAC_WEIGHT_SP_0_BASE_IDX', 'regSE_CAC_WEIGHT_SP_1', - 'regSE_CAC_WEIGHT_SP_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_0', - 'regSE_CAC_WEIGHT_SQC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_1', - 'regSE_CAC_WEIGHT_SQC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_0', - 'regSE_CAC_WEIGHT_SQ_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_1', - 'regSE_CAC_WEIGHT_SQ_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_2', - 'regSE_CAC_WEIGHT_SQ_2_BASE_IDX', 'regSE_CAC_WEIGHT_SXRB_0', - 'regSE_CAC_WEIGHT_SXRB_0_BASE_IDX', 'regSE_CAC_WEIGHT_SX_0', - 'regSE_CAC_WEIGHT_SX_0_BASE_IDX', 'regSE_CAC_WEIGHT_TA_0', - 'regSE_CAC_WEIGHT_TA_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_0', - 'regSE_CAC_WEIGHT_TCP_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_1', - 'regSE_CAC_WEIGHT_TCP_1_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_2', - 'regSE_CAC_WEIGHT_TCP_2_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_3', - 'regSE_CAC_WEIGHT_TCP_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_0', - 'regSE_CAC_WEIGHT_TD_0_BASE_IDX', 'regSE_CAC_WEIGHT_TD_1', - 'regSE_CAC_WEIGHT_TD_1_BASE_IDX', 'regSE_CAC_WEIGHT_TD_2', - 'regSE_CAC_WEIGHT_TD_2_BASE_IDX', 'regSE_CAC_WEIGHT_TD_3', - 'regSE_CAC_WEIGHT_TD_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_4', - 'regSE_CAC_WEIGHT_TD_4_BASE_IDX', 'regSE_CAC_WEIGHT_TD_5', - 'regSE_CAC_WEIGHT_TD_5_BASE_IDX', 'regSE_CAC_WEIGHT_UTCL1_0', - 'regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX', - 'regSE_CAC_WINDOW_AGGR_VALUE', - 'regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX', - 'regSE_CAC_WINDOW_GFXCLK_CYCLE', - 'regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX', 'regSH_MEM_BASES', - 'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG', - 'regSH_MEM_CONFIG_BASE_IDX', 'regSH_RESERVED_REG0', - 'regSH_RESERVED_REG0_BASE_IDX', 'regSH_RESERVED_REG1', - 'regSH_RESERVED_REG1_BASE_IDX', 'regSMU_RLC_RESPONSE', - 'regSMU_RLC_RESPONSE_BASE_IDX', 'regSPI_ARB_CNTL_0', - 'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0', - 'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1', - 'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY', - 'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_ATTRIBUTE_RING_BASE', - 'regSPI_ATTRIBUTE_RING_BASE_BASE_IDX', - 'regSPI_ATTRIBUTE_RING_SIZE', - 'regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX', 'regSPI_BARYC_CNTL', - 'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET', - 'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX', - 'regSPI_COMPUTE_WF_CTX_SAVE', - 'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', - 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS', - 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX', - 'regSPI_CONFIG_CNTL', 'regSPI_CONFIG_CNTL_1', - 'regSPI_CONFIG_CNTL_1_BASE_IDX', 'regSPI_CONFIG_CNTL_2', - 'regSPI_CONFIG_CNTL_2_BASE_IDX', 'regSPI_CONFIG_CNTL_BASE_IDX', - 'regSPI_CONFIG_PS_CU_EN', 'regSPI_CONFIG_PS_CU_EN_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_0', - 'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_1', - 'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_2', - 'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_3', - 'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_STATUS', - 'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DSM_CNTL', - 'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX', - 'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT', - 'regSPI_EDC_CNT_BASE_IDX', 'regSPI_EXP_THROTTLE_CTRL', - 'regSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'regSPI_FEATURE_CTRL', - 'regSPI_FEATURE_CTRL_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL', - 'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG', - 'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL', - 'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX', - 'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS', - 'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL', - 'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_GFX_SCRATCH_BASE_HI', - 'regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX', - 'regSPI_GFX_SCRATCH_BASE_LO', - 'regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL1', - 'regSPI_GS_THROTTLE_CNTL1_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL2', - 'regSPI_GS_THROTTLE_CNTL2_BASE_IDX', 'regSPI_INTERP_CONTROL_0', - 'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL', - 'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_DATA_REG', - 'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES', - 'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_LB_WGP_MASK', - 'regSPI_LB_WGP_MASK_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN', - 'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSBA_HI', - 'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSBA_LO', - 'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSMA_HI', - 'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSMA_LO', - 'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_GPR_MIN', - 'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSBA_HI', - 'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSBA_LO', - 'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSMA_HI', - 'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSMA_LO', - 'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', - 'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX', - 'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX', - 'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1', - 'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI', - 'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO', - 'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT', - 'regSPI_PERFCOUNTER1_SELECT1', - 'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI', - 'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO', - 'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT', - 'regSPI_PERFCOUNTER2_SELECT1', - 'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI', - 'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO', - 'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT', - 'regSPI_PERFCOUNTER3_SELECT1', - 'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI', - 'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO', - 'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT', - 'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI', - 'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO', - 'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT', - 'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS', - 'regSPI_PERFCOUNTER_BINS_BASE_IDX', - 'regSPI_PG_ENABLE_STATIC_WGP_MASK', - 'regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'regSPI_PQEV_CTRL', - 'regSPI_PQEV_CTRL_BASE_IDX', 'regSPI_PS_INPUT_ADDR', - 'regSPI_PS_INPUT_ADDR_BASE_IDX', 'regSPI_PS_INPUT_CNTL_0', - 'regSPI_PS_INPUT_CNTL_0_BASE_IDX', 'regSPI_PS_INPUT_CNTL_1', - 'regSPI_PS_INPUT_CNTL_10', 'regSPI_PS_INPUT_CNTL_10_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_11', 'regSPI_PS_INPUT_CNTL_11_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_12', 'regSPI_PS_INPUT_CNTL_12_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_13', 'regSPI_PS_INPUT_CNTL_13_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_14', 'regSPI_PS_INPUT_CNTL_14_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_15', 'regSPI_PS_INPUT_CNTL_15_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_16', 'regSPI_PS_INPUT_CNTL_16_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_17', 'regSPI_PS_INPUT_CNTL_17_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_18', 'regSPI_PS_INPUT_CNTL_18_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_19', 'regSPI_PS_INPUT_CNTL_19_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2', - 'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3', - 'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4', - 'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5', - 'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6', - 'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7', - 'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8', - 'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9', - 'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA', - 'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL', - 'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID', - 'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0', - 'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10', - 'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_11', - 'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_12', - 'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_13', - 'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_14', - 'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_15', - 'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_2', - 'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_3', - 'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_4', - 'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_5', - 'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_6', - 'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_7', - 'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_8', - 'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_9', - 'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_0', - 'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_1', - 'regSPI_RESOURCE_RESERVE_EN_CU_10', - 'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_11', - 'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_12', - 'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_13', - 'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_14', - 'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_15', - 'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_2', - 'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_3', - 'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_4', - 'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_5', - 'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_6', - 'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_7', - 'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_8', - 'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_9', - 'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', - 'regSPI_SHADER_COL_FORMAT', 'regSPI_SHADER_COL_FORMAT_BASE_IDX', - 'regSPI_SHADER_GS_MESHLET_DIM', - 'regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX', - 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC', - 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX', - 'regSPI_SHADER_IDX_FORMAT', 'regSPI_SHADER_IDX_FORMAT_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_GS', - 'regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_HS', - 'regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_PS', - 'regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES', - 'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES_GS', - 'regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS', - 'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS', - 'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS', - 'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS_HS', - 'regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS', - 'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES', - 'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES_GS', - 'regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS', - 'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS', - 'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS', - 'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS_HS', - 'regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS', - 'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS', - 'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC1_HS', - 'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC1_PS', - 'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_GS', - 'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_HS', - 'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_PS', - 'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_GS', - 'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_HS', - 'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_PS', - 'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_GS', - 'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_HS', - 'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_PS', - 'regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT', - 'regSPI_SHADER_POS_FORMAT_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_ESGS', - 'regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_LSHS', - 'regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_PS', 'regSPI_SHADER_REQ_CTRL_PS_BASE_IDX', - 'regSPI_SHADER_RSRC_LIMIT_CTRL', - 'regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_0', - 'regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_1', - 'regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_2', - 'regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_3', - 'regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_0', - 'regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_1', - 'regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_2', - 'regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_3', - 'regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_0', - 'regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_1', - 'regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_2', - 'regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_3', - 'regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_HI_GS', - 'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_HI_HS', - 'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_LO_GS', - 'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_LO_HS', - 'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_0', - 'regSPI_SHADER_USER_DATA_GS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_1', 'regSPI_SHADER_USER_DATA_GS_10', - 'regSPI_SHADER_USER_DATA_GS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_11', - 'regSPI_SHADER_USER_DATA_GS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_12', - 'regSPI_SHADER_USER_DATA_GS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_13', - 'regSPI_SHADER_USER_DATA_GS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_14', - 'regSPI_SHADER_USER_DATA_GS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_15', - 'regSPI_SHADER_USER_DATA_GS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_16', - 'regSPI_SHADER_USER_DATA_GS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_17', - 'regSPI_SHADER_USER_DATA_GS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_18', - 'regSPI_SHADER_USER_DATA_GS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_19', - 'regSPI_SHADER_USER_DATA_GS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_2', 'regSPI_SHADER_USER_DATA_GS_20', - 'regSPI_SHADER_USER_DATA_GS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_21', - 'regSPI_SHADER_USER_DATA_GS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_22', - 'regSPI_SHADER_USER_DATA_GS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_23', - 'regSPI_SHADER_USER_DATA_GS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_24', - 'regSPI_SHADER_USER_DATA_GS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_25', - 'regSPI_SHADER_USER_DATA_GS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_26', - 'regSPI_SHADER_USER_DATA_GS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_27', - 'regSPI_SHADER_USER_DATA_GS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_28', - 'regSPI_SHADER_USER_DATA_GS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_29', - 'regSPI_SHADER_USER_DATA_GS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_3', 'regSPI_SHADER_USER_DATA_GS_30', - 'regSPI_SHADER_USER_DATA_GS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_31', - 'regSPI_SHADER_USER_DATA_GS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_4', - 'regSPI_SHADER_USER_DATA_GS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_5', - 'regSPI_SHADER_USER_DATA_GS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_6', - 'regSPI_SHADER_USER_DATA_GS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_7', - 'regSPI_SHADER_USER_DATA_GS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_8', - 'regSPI_SHADER_USER_DATA_GS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_9', - 'regSPI_SHADER_USER_DATA_GS_9_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_0', - 'regSPI_SHADER_USER_DATA_HS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_1', 'regSPI_SHADER_USER_DATA_HS_10', - 'regSPI_SHADER_USER_DATA_HS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_11', - 'regSPI_SHADER_USER_DATA_HS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_12', - 'regSPI_SHADER_USER_DATA_HS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_13', - 'regSPI_SHADER_USER_DATA_HS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_14', - 'regSPI_SHADER_USER_DATA_HS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_15', - 'regSPI_SHADER_USER_DATA_HS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_16', - 'regSPI_SHADER_USER_DATA_HS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_17', - 'regSPI_SHADER_USER_DATA_HS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_18', - 'regSPI_SHADER_USER_DATA_HS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_19', - 'regSPI_SHADER_USER_DATA_HS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_2', 'regSPI_SHADER_USER_DATA_HS_20', - 'regSPI_SHADER_USER_DATA_HS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_21', - 'regSPI_SHADER_USER_DATA_HS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_22', - 'regSPI_SHADER_USER_DATA_HS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_23', - 'regSPI_SHADER_USER_DATA_HS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_24', - 'regSPI_SHADER_USER_DATA_HS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_25', - 'regSPI_SHADER_USER_DATA_HS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_26', - 'regSPI_SHADER_USER_DATA_HS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_27', - 'regSPI_SHADER_USER_DATA_HS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_28', - 'regSPI_SHADER_USER_DATA_HS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_29', - 'regSPI_SHADER_USER_DATA_HS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_3', 'regSPI_SHADER_USER_DATA_HS_30', - 'regSPI_SHADER_USER_DATA_HS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_31', - 'regSPI_SHADER_USER_DATA_HS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_4', - 'regSPI_SHADER_USER_DATA_HS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_5', - 'regSPI_SHADER_USER_DATA_HS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_6', - 'regSPI_SHADER_USER_DATA_HS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_7', - 'regSPI_SHADER_USER_DATA_HS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_8', - 'regSPI_SHADER_USER_DATA_HS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_9', - 'regSPI_SHADER_USER_DATA_HS_9_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_0', - 'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10', - 'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_11', - 'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_12', - 'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_13', - 'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_14', - 'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_15', - 'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_16', - 'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_17', - 'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_18', - 'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_19', - 'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20', - 'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_21', - 'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_22', - 'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_23', - 'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_24', - 'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_25', - 'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_26', - 'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_27', - 'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_28', - 'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_29', - 'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30', - 'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_31', - 'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_4', - 'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_5', - 'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_6', - 'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_7', - 'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_8', - 'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_9', - 'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT', - 'regSPI_SHADER_Z_FORMAT_BASE_IDX', - 'regSPI_SX_EXPORT_BUFFER_SIZES', - 'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', - 'regSPI_SX_SCOREBOARD_BUFFER_SIZES', - 'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', - 'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX', - 'regSPI_USER_ACCUM_VMID_CNTL', - 'regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'regSPI_VS_OUT_CONFIG', - 'regSPI_VS_OUT_CONFIG_BASE_IDX', 'regSPI_WAVE_LIMIT_CNTL', - 'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'regSPI_WCL_PIPE_PERCENT_CS0', - 'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS1', - 'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS2', - 'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS3', - 'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS4', - 'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS5', - 'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS6', - 'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS7', - 'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_GFX', - 'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_HP3D', - 'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', - 'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_0', - 'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_1', - 'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_2', - 'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_3', - 'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_4', - 'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_5', - 'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_0', - 'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_11', - 'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_13', - 'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_14', - 'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_15', - 'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_16', - 'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_17', - 'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_18', - 'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_19', - 'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20', - 'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_21', - 'regSPI_WF_LIFETIME_STATUS_21_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_4', - 'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_6', - 'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_7', - 'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_9', - 'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'regSP_CONFIG', - 'regSP_CONFIG_BASE_IDX', 'regSQC_CACHES', - 'regSQC_CACHES_BASE_IDX', 'regSQC_CONFIG', - 'regSQC_CONFIG_BASE_IDX', 'regSQG_CONFIG', - 'regSQG_CONFIG_BASE_IDX', 'regSQG_GL1H_STATUS', - 'regSQG_GL1H_STATUS_BASE_IDX', 'regSQG_PERFCOUNTER0_HI', - 'regSQG_PERFCOUNTER0_HI_BASE_IDX', 'regSQG_PERFCOUNTER0_LO', - 'regSQG_PERFCOUNTER0_LO_BASE_IDX', 'regSQG_PERFCOUNTER0_SELECT', - 'regSQG_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER1_HI', - 'regSQG_PERFCOUNTER1_HI_BASE_IDX', 'regSQG_PERFCOUNTER1_LO', - 'regSQG_PERFCOUNTER1_LO_BASE_IDX', 'regSQG_PERFCOUNTER1_SELECT', - 'regSQG_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER2_HI', - 'regSQG_PERFCOUNTER2_HI_BASE_IDX', 'regSQG_PERFCOUNTER2_LO', - 'regSQG_PERFCOUNTER2_LO_BASE_IDX', 'regSQG_PERFCOUNTER2_SELECT', - 'regSQG_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER3_HI', - 'regSQG_PERFCOUNTER3_HI_BASE_IDX', 'regSQG_PERFCOUNTER3_LO', - 'regSQG_PERFCOUNTER3_LO_BASE_IDX', 'regSQG_PERFCOUNTER3_SELECT', - 'regSQG_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER4_HI', - 'regSQG_PERFCOUNTER4_HI_BASE_IDX', 'regSQG_PERFCOUNTER4_LO', - 'regSQG_PERFCOUNTER4_LO_BASE_IDX', 'regSQG_PERFCOUNTER4_SELECT', - 'regSQG_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER5_HI', - 'regSQG_PERFCOUNTER5_HI_BASE_IDX', 'regSQG_PERFCOUNTER5_LO', - 'regSQG_PERFCOUNTER5_LO_BASE_IDX', 'regSQG_PERFCOUNTER5_SELECT', - 'regSQG_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER6_HI', - 'regSQG_PERFCOUNTER6_HI_BASE_IDX', 'regSQG_PERFCOUNTER6_LO', - 'regSQG_PERFCOUNTER6_LO_BASE_IDX', 'regSQG_PERFCOUNTER6_SELECT', - 'regSQG_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER7_HI', - 'regSQG_PERFCOUNTER7_HI_BASE_IDX', 'regSQG_PERFCOUNTER7_LO', - 'regSQG_PERFCOUNTER7_LO_BASE_IDX', 'regSQG_PERFCOUNTER7_SELECT', - 'regSQG_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER_CTRL', - 'regSQG_PERFCOUNTER_CTRL2', 'regSQG_PERFCOUNTER_CTRL2_BASE_IDX', - 'regSQG_PERFCOUNTER_CTRL_BASE_IDX', 'regSQG_PERF_SAMPLE_FINISH', - 'regSQG_PERF_SAMPLE_FINISH_BASE_IDX', 'regSQG_STATUS', - 'regSQG_STATUS_BASE_IDX', 'regSQ_ALU_CLK_CTRL', - 'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_ARB_CONFIG', - 'regSQ_ARB_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX', - 'regSQ_CONFIG', 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG', - 'regSQ_DEBUG_BASE_IDX', 'regSQ_DEBUG_HOST_TRAP_STATUS', - 'regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL', - 'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX', - 'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL', - 'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX', - 'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_FIFO_SIZES', - 'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_IND_DATA', - 'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX', - 'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INTERRUPT_AUTO_MASK', - 'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'regSQ_INTERRUPT_MSG_CTRL', - 'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'regSQ_LDS_CLK_CTRL', - 'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER0_LO', - 'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT', - 'regSQ_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER10_SELECT', - 'regSQ_PERFCOUNTER10_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER11_SELECT', - 'regSQ_PERFCOUNTER11_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER12_SELECT', - 'regSQ_PERFCOUNTER12_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER13_SELECT', - 'regSQ_PERFCOUNTER13_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER14_SELECT', - 'regSQ_PERFCOUNTER14_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER15_SELECT', - 'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_LO', - 'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT', - 'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_LO', - 'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT', - 'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_LO', - 'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT', - 'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_LO', - 'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT', - 'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_LO', - 'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT', - 'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_LO', - 'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT', - 'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_LO', - 'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT', - 'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT', - 'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT', - 'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL', - 'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX', - 'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL', - 'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI', - 'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_RUNTIME_CONFIG', - 'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SHADER_TBA_HI', - 'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO', - 'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI', - 'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO', - 'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_TEX_CLK_CTRL', - 'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BUF0_BASE', - 'regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF0_SIZE', - 'regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF1_BASE', - 'regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF1_SIZE', - 'regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', - 'regSQ_THREAD_TRACE_CTRL', 'regSQ_THREAD_TRACE_CTRL_BASE_IDX', - 'regSQ_THREAD_TRACE_DROPPED_CNTR', - 'regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR', - 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR', - 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR', - 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR', - 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_MASK', 'regSQ_THREAD_TRACE_MASK_BASE_IDX', - 'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS2', - 'regSQ_THREAD_TRACE_STATUS2_BASE_IDX', - 'regSQ_THREAD_TRACE_STATUS_BASE_IDX', - 'regSQ_THREAD_TRACE_TOKEN_MASK', - 'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_0', - 'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_1', - 'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_2', - 'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_3', - 'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_4', - 'regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_5', - 'regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_6', - 'regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_7', - 'regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', - 'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX', - 'regSQ_WATCH0_ADDR_H', 'regSQ_WATCH0_ADDR_H_BASE_IDX', - 'regSQ_WATCH0_ADDR_L', 'regSQ_WATCH0_ADDR_L_BASE_IDX', - 'regSQ_WATCH0_CNTL', 'regSQ_WATCH0_CNTL_BASE_IDX', - 'regSQ_WATCH1_ADDR_H', 'regSQ_WATCH1_ADDR_H_BASE_IDX', - 'regSQ_WATCH1_ADDR_L', 'regSQ_WATCH1_ADDR_L_BASE_IDX', - 'regSQ_WATCH1_CNTL', 'regSQ_WATCH1_CNTL_BASE_IDX', - 'regSQ_WATCH2_ADDR_H', 'regSQ_WATCH2_ADDR_H_BASE_IDX', - 'regSQ_WATCH2_ADDR_L', 'regSQ_WATCH2_ADDR_L_BASE_IDX', - 'regSQ_WATCH2_CNTL', 'regSQ_WATCH2_CNTL_BASE_IDX', - 'regSQ_WATCH3_ADDR_H', 'regSQ_WATCH3_ADDR_H_BASE_IDX', - 'regSQ_WATCH3_ADDR_L', 'regSQ_WATCH3_ADDR_L_BASE_IDX', - 'regSQ_WATCH3_CNTL', 'regSQ_WATCH3_CNTL_BASE_IDX', - 'regSX_BLEND_OPT_CONTROL', 'regSX_BLEND_OPT_CONTROL_BASE_IDX', - 'regSX_BLEND_OPT_EPSILON', 'regSX_BLEND_OPT_EPSILON_BASE_IDX', - 'regSX_DEBUG_1', 'regSX_DEBUG_1_BASE_IDX', 'regSX_MRT0_BLEND_OPT', - 'regSX_MRT0_BLEND_OPT_BASE_IDX', 'regSX_MRT1_BLEND_OPT', - 'regSX_MRT1_BLEND_OPT_BASE_IDX', 'regSX_MRT2_BLEND_OPT', - 'regSX_MRT2_BLEND_OPT_BASE_IDX', 'regSX_MRT3_BLEND_OPT', - 'regSX_MRT3_BLEND_OPT_BASE_IDX', 'regSX_MRT4_BLEND_OPT', - 'regSX_MRT4_BLEND_OPT_BASE_IDX', 'regSX_MRT5_BLEND_OPT', - 'regSX_MRT5_BLEND_OPT_BASE_IDX', 'regSX_MRT6_BLEND_OPT', - 'regSX_MRT6_BLEND_OPT_BASE_IDX', 'regSX_MRT7_BLEND_OPT', - 'regSX_MRT7_BLEND_OPT_BASE_IDX', 'regSX_PERFCOUNTER0_HI', - 'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO', - 'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT', - 'regSX_PERFCOUNTER0_SELECT1', - 'regSX_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI', - 'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO', - 'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT', - 'regSX_PERFCOUNTER1_SELECT1', - 'regSX_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI', - 'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO', - 'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT', - 'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI', - 'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO', - 'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT', - 'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regSX_PS_DOWNCONVERT', - 'regSX_PS_DOWNCONVERT_BASE_IDX', 'regSX_PS_DOWNCONVERT_CONTROL', - 'regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'regTA_BC_BASE_ADDR', - 'regTA_BC_BASE_ADDR_BASE_IDX', 'regTA_BC_BASE_ADDR_HI', - 'regTA_BC_BASE_ADDR_HI_BASE_IDX', 'regTA_CGTT_CTRL', - 'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL2', - 'regTA_CNTL2_BASE_IDX', 'regTA_CNTL_AUX', - 'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX', - 'regTA_CS_BC_BASE_ADDR', 'regTA_CS_BC_BASE_ADDR_BASE_IDX', - 'regTA_CS_BC_BASE_ADDR_HI', 'regTA_CS_BC_BASE_ADDR_HI_BASE_IDX', - 'regTA_PERFCOUNTER0_HI', 'regTA_PERFCOUNTER0_HI_BASE_IDX', - 'regTA_PERFCOUNTER0_LO', 'regTA_PERFCOUNTER0_LO_BASE_IDX', - 'regTA_PERFCOUNTER0_SELECT', 'regTA_PERFCOUNTER0_SELECT1', - 'regTA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI', - 'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO', - 'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT', - 'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_SCRATCH', - 'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX', - 'regTCP_CNTL', 'regTCP_CNTL2', 'regTCP_CNTL2_BASE_IDX', - 'regTCP_CNTL_BASE_IDX', 'regTCP_DEBUG_DATA', - 'regTCP_DEBUG_DATA_BASE_IDX', 'regTCP_DEBUG_INDEX', - 'regTCP_DEBUG_INDEX_BASE_IDX', 'regTCP_INVALIDATE', - 'regTCP_INVALIDATE_BASE_IDX', 'regTCP_PERFCOUNTER0_HI', - 'regTCP_PERFCOUNTER0_HI_BASE_IDX', 'regTCP_PERFCOUNTER0_LO', - 'regTCP_PERFCOUNTER0_LO_BASE_IDX', 'regTCP_PERFCOUNTER0_SELECT', - 'regTCP_PERFCOUNTER0_SELECT1', - 'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI', - 'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO', - 'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT', - 'regTCP_PERFCOUNTER1_SELECT1', - 'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI', - 'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO', - 'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT', - 'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI', - 'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO', - 'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT', - 'regTCP_PERFCOUNTER3_SELECT_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER2', - 'regTCP_PERFCOUNTER_FILTER2_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER_EN', - 'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS', - 'regTCP_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H', - 'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L', - 'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL', - 'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H', - 'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L', - 'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL', - 'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H', - 'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L', - 'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL', - 'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H', - 'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L', - 'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL', - 'regTCP_WATCH3_CNTL_BASE_IDX', 'regTD_DSM_CNTL', - 'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX', - 'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI', - 'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO', - 'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT', - 'regTD_PERFCOUNTER0_SELECT1', - 'regTD_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI', - 'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO', - 'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT', - 'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_SCRATCH', - 'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX', - 'regUCONFIG_RESERVED_REG0', 'regUCONFIG_RESERVED_REG0_BASE_IDX', - 'regUCONFIG_RESERVED_REG1', 'regUCONFIG_RESERVED_REG1_BASE_IDX', - 'regUTCL1_ALOG', 'regUTCL1_ALOG_BASE_IDX', 'regUTCL1_CTRL_0', - 'regUTCL1_CTRL_0_BASE_IDX', 'regUTCL1_CTRL_1', - 'regUTCL1_CTRL_1_BASE_IDX', 'regUTCL1_CTRL_2', - 'regUTCL1_CTRL_2_BASE_IDX', 'regUTCL1_FIFO_SIZING', - 'regUTCL1_FIFO_SIZING_BASE_IDX', 'regUTCL1_PERFCOUNTER0_HI', - 'regUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'regUTCL1_PERFCOUNTER0_LO', - 'regUTCL1_PERFCOUNTER0_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER0_SELECT', - 'regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_HI', 'regUTCL1_PERFCOUNTER1_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_LO', 'regUTCL1_PERFCOUNTER1_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_SELECT', - 'regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_HI', 'regUTCL1_PERFCOUNTER2_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_LO', 'regUTCL1_PERFCOUNTER2_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_SELECT', - 'regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_HI', 'regUTCL1_PERFCOUNTER3_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_LO', 'regUTCL1_PERFCOUNTER3_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_SELECT', - 'regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX', 'regUTCL1_STATUS', - 'regUTCL1_STATUS_BASE_IDX', 'regUTCL1_UTCL0_INVREQ_DISABLE', - 'regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', 'regVGT_DMA_BASE', - 'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI', - 'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH', - 'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_INDEX_TYPE', - 'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_MAX_SIZE', - 'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES', - 'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH', - 'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE', - 'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR', - 'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH', - 'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', - 'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', - 'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX', - 'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX', - 'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX', - 'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX', - 'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX', - 'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX', - 'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX', - 'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX', - 'regVGT_HOS_MAX_TESS_LEVEL', 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', - 'regVGT_HOS_MIN_TESS_LEVEL', 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', - 'regVGT_HS_OFFCHIP_PARAM', 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX', - 'regVGT_INDEX_TYPE', 'regVGT_INDEX_TYPE_BASE_IDX', - 'regVGT_INSTANCE_BASE_ID', 'regVGT_INSTANCE_BASE_ID_BASE_IDX', - 'regVGT_LS_HS_CONFIG', 'regVGT_LS_HS_CONFIG_BASE_IDX', - 'regVGT_MC_LAT_CNTL', 'regVGT_MC_LAT_CNTL_BASE_IDX', - 'regVGT_MULTI_PRIM_IB_RESET_INDX', - 'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES', - 'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES', - 'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_PRIMITIVEID_EN', - 'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET', - 'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE', - 'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_REUSE_OFF', - 'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN', - 'regVGT_SHADER_STAGES_EN_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', - 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET', - 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', - 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', - 'regVGT_SYS_CONFIG', 'regVGT_SYS_CONFIG_BASE_IDX', - 'regVGT_TESS_DISTRIBUTION', 'regVGT_TESS_DISTRIBUTION_BASE_IDX', - 'regVGT_TF_MEMORY_BASE', 'regVGT_TF_MEMORY_BASE_BASE_IDX', - 'regVGT_TF_MEMORY_BASE_HI', 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX', - 'regVGT_TF_PARAM', 'regVGT_TF_PARAM_BASE_IDX', - 'regVGT_TF_RING_SIZE', 'regVGT_TF_RING_SIZE_BASE_IDX', - 'regVIOLATION_DATA_ASYNC_VF_PROG', - 'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'regWD_CNTL_STATUS', - 'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE', - 'regWD_ENHANCE_BASE_IDX', 'regWD_QOS', 'regWD_QOS_BASE_IDX', - 'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX', - 'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX', - 'struct_IP_BASE', 'struct_IP_BASE_INSTANCE', - 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'struct_pm4_mec_release_mem', - 'struct_pm4_mec_release_mem_1_bitfields2', - 'struct_pm4_mec_release_mem_2_bitfields3', - 'struct_pm4_mec_release_mem_3_bitfields4', - 'struct_pm4_mec_release_mem_3_bitfields4b', - 'struct_pm4_mec_release_mem_5_bitfields6c', - 'struct_pm4_mec_write_data_mmio', - 'struct_pm4_mec_write_data_mmio_1_bitfields2', - 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', - 'union_PM4_MES_TYPE_3_HEADER', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION', - 'union_pm4_mec_release_mem_0', 'union_pm4_mec_release_mem_1', - 'union_pm4_mec_release_mem_2', 'union_pm4_mec_release_mem_3', - 'union_pm4_mec_release_mem_4', 'union_pm4_mec_release_mem_5', - 'union_pm4_mec_release_mem_6', 'union_pm4_mec_write_data_mmio_0', - 'union_pm4_mec_write_data_mmio_1', - 'union_pm4_mec_write_data_mmio_2', - 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 'wr_confirm___write_data__wait_for_write_confirmation'] diff --git a/tinygrad/tinygrad/runtime/autogen/comgr.py b/tinygrad/tinygrad/runtime/autogen/comgr.py deleted file mode 100644 index 3159606f..00000000 --- a/tinygrad/tinygrad/runtime/autogen/comgr.py +++ /dev/null @@ -1,919 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os -PATHS_TO_TRY = [ - '/opt/rocm/lib/libamd_comgr.so', - os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so', - '/usr/local/lib/libamd_comgr.dylib', - '/opt/homebrew/lib/libamd_comgr.dylib', -] -def _try_dlopen_amd_comgr(): - library = ctypes.util.find_library("amd_comgr") - if library: return ctypes.CDLL(library) - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass - return None - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libamd_comgr.so'] = _try_dlopen_amd_comgr() -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - - -# values for enumeration 'amd_comgr_status_s' -amd_comgr_status_s__enumvalues = { - 0: 'AMD_COMGR_STATUS_SUCCESS', - 1: 'AMD_COMGR_STATUS_ERROR', - 2: 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 3: 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', -} -AMD_COMGR_STATUS_SUCCESS = 0 -AMD_COMGR_STATUS_ERROR = 1 -AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 2 -AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 3 -amd_comgr_status_s = ctypes.c_uint32 # enum -amd_comgr_status_t = amd_comgr_status_s -amd_comgr_status_t__enumvalues = amd_comgr_status_s__enumvalues - -# values for enumeration 'amd_comgr_language_s' -amd_comgr_language_s__enumvalues = { - 0: 'AMD_COMGR_LANGUAGE_NONE', - 1: 'AMD_COMGR_LANGUAGE_OPENCL_1_2', - 2: 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 3: 'AMD_COMGR_LANGUAGE_HC', - 4: 'AMD_COMGR_LANGUAGE_HIP', - 5: 'AMD_COMGR_LANGUAGE_LLVM_IR', - 5: 'AMD_COMGR_LANGUAGE_LAST', -} -AMD_COMGR_LANGUAGE_NONE = 0 -AMD_COMGR_LANGUAGE_OPENCL_1_2 = 1 -AMD_COMGR_LANGUAGE_OPENCL_2_0 = 2 -AMD_COMGR_LANGUAGE_HC = 3 -AMD_COMGR_LANGUAGE_HIP = 4 -AMD_COMGR_LANGUAGE_LLVM_IR = 5 -AMD_COMGR_LANGUAGE_LAST = 5 -amd_comgr_language_s = ctypes.c_uint32 # enum -amd_comgr_language_t = amd_comgr_language_s -amd_comgr_language_t__enumvalues = amd_comgr_language_s__enumvalues -try: - amd_comgr_status_string = _libraries['libamd_comgr.so'].amd_comgr_status_string - amd_comgr_status_string.restype = amd_comgr_status_t - amd_comgr_status_string.argtypes = [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_version = _libraries['libamd_comgr.so'].amd_comgr_get_version - amd_comgr_get_version.restype = None - amd_comgr_get_version.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_data_kind_s' -amd_comgr_data_kind_s__enumvalues = { - 0: 'AMD_COMGR_DATA_KIND_UNDEF', - 1: 'AMD_COMGR_DATA_KIND_SOURCE', - 2: 'AMD_COMGR_DATA_KIND_INCLUDE', - 3: 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 4: 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 5: 'AMD_COMGR_DATA_KIND_LOG', - 6: 'AMD_COMGR_DATA_KIND_BC', - 7: 'AMD_COMGR_DATA_KIND_RELOCATABLE', - 8: 'AMD_COMGR_DATA_KIND_EXECUTABLE', - 9: 'AMD_COMGR_DATA_KIND_BYTES', - 16: 'AMD_COMGR_DATA_KIND_FATBIN', - 17: 'AMD_COMGR_DATA_KIND_AR', - 18: 'AMD_COMGR_DATA_KIND_BC_BUNDLE', - 19: 'AMD_COMGR_DATA_KIND_AR_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_LAST', -} -AMD_COMGR_DATA_KIND_UNDEF = 0 -AMD_COMGR_DATA_KIND_SOURCE = 1 -AMD_COMGR_DATA_KIND_INCLUDE = 2 -AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 3 -AMD_COMGR_DATA_KIND_DIAGNOSTIC = 4 -AMD_COMGR_DATA_KIND_LOG = 5 -AMD_COMGR_DATA_KIND_BC = 6 -AMD_COMGR_DATA_KIND_RELOCATABLE = 7 -AMD_COMGR_DATA_KIND_EXECUTABLE = 8 -AMD_COMGR_DATA_KIND_BYTES = 9 -AMD_COMGR_DATA_KIND_FATBIN = 16 -AMD_COMGR_DATA_KIND_AR = 17 -AMD_COMGR_DATA_KIND_BC_BUNDLE = 18 -AMD_COMGR_DATA_KIND_AR_BUNDLE = 19 -AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 20 -AMD_COMGR_DATA_KIND_LAST = 20 -amd_comgr_data_kind_s = ctypes.c_uint32 # enum -amd_comgr_data_kind_t = amd_comgr_data_kind_s -amd_comgr_data_kind_t__enumvalues = amd_comgr_data_kind_s__enumvalues -class struct_amd_comgr_data_s(Structure): - pass - -struct_amd_comgr_data_s._pack_ = 1 # source:False -struct_amd_comgr_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_t = struct_amd_comgr_data_s -class struct_amd_comgr_data_set_s(Structure): - pass - -struct_amd_comgr_data_set_s._pack_ = 1 # source:False -struct_amd_comgr_data_set_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_set_t = struct_amd_comgr_data_set_s -class struct_amd_comgr_action_info_s(Structure): - pass - -struct_amd_comgr_action_info_s._pack_ = 1 # source:False -struct_amd_comgr_action_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_action_info_t = struct_amd_comgr_action_info_s -class struct_amd_comgr_metadata_node_s(Structure): - pass - -struct_amd_comgr_metadata_node_s._pack_ = 1 # source:False -struct_amd_comgr_metadata_node_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_metadata_node_t = struct_amd_comgr_metadata_node_s -class struct_amd_comgr_symbol_s(Structure): - pass - -struct_amd_comgr_symbol_s._pack_ = 1 # source:False -struct_amd_comgr_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbol_t = struct_amd_comgr_symbol_s -class struct_amd_comgr_disassembly_info_s(Structure): - pass - -struct_amd_comgr_disassembly_info_s._pack_ = 1 # source:False -struct_amd_comgr_disassembly_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_disassembly_info_t = struct_amd_comgr_disassembly_info_s -class struct_amd_comgr_symbolizer_info_s(Structure): - pass - -struct_amd_comgr_symbolizer_info_s._pack_ = 1 # source:False -struct_amd_comgr_symbolizer_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbolizer_info_t = struct_amd_comgr_symbolizer_info_s -try: - amd_comgr_get_isa_count = _libraries['libamd_comgr.so'].amd_comgr_get_isa_count - amd_comgr_get_isa_count.restype = amd_comgr_status_t - amd_comgr_get_isa_count.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - amd_comgr_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_isa_name - amd_comgr_get_isa_name.restype = amd_comgr_status_t - amd_comgr_get_isa_name.argtypes = [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_isa_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_isa_metadata - amd_comgr_get_isa_metadata.restype = amd_comgr_status_t - amd_comgr_get_isa_metadata.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_create_data = _libraries['libamd_comgr.so'].amd_comgr_create_data - amd_comgr_create_data.restype = amd_comgr_status_t - amd_comgr_create_data.argtypes = [amd_comgr_data_kind_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_release_data = _libraries['libamd_comgr.so'].amd_comgr_release_data - amd_comgr_release_data.restype = amd_comgr_status_t - amd_comgr_release_data.argtypes = [amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_get_data_kind = _libraries['libamd_comgr.so'].amd_comgr_get_data_kind - amd_comgr_get_data_kind.restype = amd_comgr_status_t - amd_comgr_get_data_kind.argtypes = [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_s)] -except AttributeError: - pass -try: - amd_comgr_set_data = _libraries['libamd_comgr.so'].amd_comgr_set_data - amd_comgr_set_data.restype = amd_comgr_status_t - amd_comgr_set_data.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - amd_comgr_set_data_from_file_slice = _libraries['libamd_comgr.so'].amd_comgr_set_data_from_file_slice - amd_comgr_set_data_from_file_slice.restype = amd_comgr_status_t - amd_comgr_set_data_from_file_slice.argtypes = [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] -except AttributeError: - pass -try: - amd_comgr_set_data_name = _libraries['libamd_comgr.so'].amd_comgr_set_data_name - amd_comgr_set_data_name.restype = amd_comgr_status_t - amd_comgr_set_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data = _libraries['libamd_comgr.so'].amd_comgr_get_data - amd_comgr_get_data.restype = amd_comgr_status_t - amd_comgr_get_data.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_name - amd_comgr_get_data_name.restype = amd_comgr_status_t - amd_comgr_get_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_isa_name - amd_comgr_get_data_isa_name.restype = amd_comgr_status_t - amd_comgr_get_data_isa_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_create_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_create_symbolizer_info - amd_comgr_create_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_create_symbolizer_info.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_symbolizer_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_symbolizer_info - amd_comgr_destroy_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_destroy_symbolizer_info.argtypes = [amd_comgr_symbolizer_info_t] -except AttributeError: - pass -try: - amd_comgr_symbolize = _libraries['libamd_comgr.so'].amd_comgr_symbolize - amd_comgr_symbolize.restype = amd_comgr_status_t - amd_comgr_symbolize.argtypes = [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_get_data_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_data_metadata - amd_comgr_get_data_metadata.restype = amd_comgr_status_t - amd_comgr_get_data_metadata.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_metadata = _libraries['libamd_comgr.so'].amd_comgr_destroy_metadata - amd_comgr_destroy_metadata.restype = amd_comgr_status_t - amd_comgr_destroy_metadata.argtypes = [amd_comgr_metadata_node_t] -except AttributeError: - pass -try: - amd_comgr_create_data_set = _libraries['libamd_comgr.so'].amd_comgr_create_data_set - amd_comgr_create_data_set.restype = amd_comgr_status_t - amd_comgr_create_data_set.argtypes = [ctypes.POINTER(struct_amd_comgr_data_set_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_data_set = _libraries['libamd_comgr.so'].amd_comgr_destroy_data_set - amd_comgr_destroy_data_set.restype = amd_comgr_status_t - amd_comgr_destroy_data_set.argtypes = [amd_comgr_data_set_t] -except AttributeError: - pass -try: - amd_comgr_data_set_add = _libraries['libamd_comgr.so'].amd_comgr_data_set_add - amd_comgr_data_set_add.restype = amd_comgr_status_t - amd_comgr_data_set_add.argtypes = [amd_comgr_data_set_t, amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_data_set_remove = _libraries['libamd_comgr.so'].amd_comgr_data_set_remove - amd_comgr_data_set_remove.restype = amd_comgr_status_t - amd_comgr_data_set_remove.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t] -except AttributeError: - pass -try: - amd_comgr_action_data_count = _libraries['libamd_comgr.so'].amd_comgr_action_data_count - amd_comgr_action_data_count.restype = amd_comgr_status_t - amd_comgr_action_data_count.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_data_get_data = _libraries['libamd_comgr.so'].amd_comgr_action_data_get_data - amd_comgr_action_data_get_data.restype = amd_comgr_status_t - amd_comgr_action_data_get_data.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_create_action_info = _libraries['libamd_comgr.so'].amd_comgr_create_action_info - amd_comgr_create_action_info.restype = amd_comgr_status_t - amd_comgr_create_action_info.argtypes = [ctypes.POINTER(struct_amd_comgr_action_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_action_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_action_info - amd_comgr_destroy_action_info.restype = amd_comgr_status_t - amd_comgr_destroy_action_info.argtypes = [amd_comgr_action_info_t] -except AttributeError: - pass -try: - amd_comgr_action_info_set_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_isa_name - amd_comgr_action_info_set_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_set_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_isa_name - amd_comgr_action_info_get_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_get_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_language - amd_comgr_action_info_set_language.restype = amd_comgr_status_t - amd_comgr_action_info_set_language.argtypes = [amd_comgr_action_info_t, amd_comgr_language_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_language - amd_comgr_action_info_get_language.restype = amd_comgr_status_t - amd_comgr_action_info_get_language.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_s)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_options = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_options - amd_comgr_action_info_set_options.restype = amd_comgr_status_t - amd_comgr_action_info_set_options.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_options = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_options - amd_comgr_action_info_get_options.restype = amd_comgr_status_t - amd_comgr_action_info_get_options.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_option_list = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_option_list - amd_comgr_action_info_set_option_list.restype = amd_comgr_status_t - amd_comgr_action_info_set_option_list.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_count - amd_comgr_action_info_get_option_list_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_item = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_item - amd_comgr_action_info_get_option_list_item.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_item.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_bundle_entry_ids = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_bundle_entry_ids - amd_comgr_action_info_set_bundle_entry_ids.restype = amd_comgr_status_t - amd_comgr_action_info_set_bundle_entry_ids.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id_count - amd_comgr_action_info_get_bundle_entry_id_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id - amd_comgr_action_info_get_bundle_entry_id.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_working_directory_path - amd_comgr_action_info_set_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_set_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_working_directory_path - amd_comgr_action_info_get_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_get_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_logging - amd_comgr_action_info_set_logging.restype = amd_comgr_status_t - amd_comgr_action_info_set_logging.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_get_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_logging - amd_comgr_action_info_get_logging.restype = amd_comgr_status_t - amd_comgr_action_info_get_logging.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_action_kind_s' -amd_comgr_action_kind_s__enumvalues = { - 0: 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 1: 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 2: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 3: 'AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES', - 4: 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 5: 'AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC', - 6: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 7: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 8: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 9: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 10: 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 11: 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 12: 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 13: 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 14: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN', - 15: 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 16: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 17: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 18: 'AMD_COMGR_ACTION_UNBUNDLE', - 18: 'AMD_COMGR_ACTION_LAST', -} -AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0 -AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = 1 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 2 -AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES = 3 -AMD_COMGR_ACTION_LINK_BC_TO_BC = 4 -AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC = 5 -AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 6 -AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 7 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 8 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 9 -AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 10 -AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = 11 -AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = 12 -AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = 13 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN = 14 -AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 15 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 16 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 17 -AMD_COMGR_ACTION_UNBUNDLE = 18 -AMD_COMGR_ACTION_LAST = 18 -amd_comgr_action_kind_s = ctypes.c_uint32 # enum -amd_comgr_action_kind_t = amd_comgr_action_kind_s -amd_comgr_action_kind_t__enumvalues = amd_comgr_action_kind_s__enumvalues -try: - amd_comgr_do_action = _libraries['libamd_comgr.so'].amd_comgr_do_action - amd_comgr_do_action.restype = amd_comgr_status_t - amd_comgr_do_action.argtypes = [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_metadata_kind_s' -amd_comgr_metadata_kind_s__enumvalues = { - 0: 'AMD_COMGR_METADATA_KIND_NULL', - 1: 'AMD_COMGR_METADATA_KIND_STRING', - 2: 'AMD_COMGR_METADATA_KIND_MAP', - 3: 'AMD_COMGR_METADATA_KIND_LIST', - 3: 'AMD_COMGR_METADATA_KIND_LAST', -} -AMD_COMGR_METADATA_KIND_NULL = 0 -AMD_COMGR_METADATA_KIND_STRING = 1 -AMD_COMGR_METADATA_KIND_MAP = 2 -AMD_COMGR_METADATA_KIND_LIST = 3 -AMD_COMGR_METADATA_KIND_LAST = 3 -amd_comgr_metadata_kind_s = ctypes.c_uint32 # enum -amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s -amd_comgr_metadata_kind_t__enumvalues = amd_comgr_metadata_kind_s__enumvalues -try: - amd_comgr_get_metadata_kind = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_kind - amd_comgr_get_metadata_kind.restype = amd_comgr_status_t - amd_comgr_get_metadata_kind.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_string = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_string - amd_comgr_get_metadata_string.restype = amd_comgr_status_t - amd_comgr_get_metadata_string.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_map_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_map_size - amd_comgr_get_metadata_map_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_map_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_iterate_map_metadata = _libraries['libamd_comgr.so'].amd_comgr_iterate_map_metadata - amd_comgr_iterate_map_metadata.restype = amd_comgr_status_t - amd_comgr_iterate_map_metadata.argtypes = [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_metadata_node_s, struct_amd_comgr_metadata_node_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_metadata_lookup = _libraries['libamd_comgr.so'].amd_comgr_metadata_lookup - amd_comgr_metadata_lookup.restype = amd_comgr_status_t - amd_comgr_metadata_lookup.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_list_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_list_size - amd_comgr_get_metadata_list_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_list_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_index_list_metadata = _libraries['libamd_comgr.so'].amd_comgr_index_list_metadata - amd_comgr_index_list_metadata.restype = amd_comgr_status_t - amd_comgr_index_list_metadata.argtypes = [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_iterate_symbols = _libraries['libamd_comgr.so'].amd_comgr_iterate_symbols - amd_comgr_iterate_symbols.restype = amd_comgr_status_t - amd_comgr_iterate_symbols.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_symbol_lookup = _libraries['libamd_comgr.so'].amd_comgr_symbol_lookup - amd_comgr_symbol_lookup.restype = amd_comgr_status_t - amd_comgr_symbol_lookup.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_symbol_type_s' -amd_comgr_symbol_type_s__enumvalues = { - -1: 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', - 0: 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 1: 'AMD_COMGR_SYMBOL_TYPE_OBJECT', - 2: 'AMD_COMGR_SYMBOL_TYPE_FUNC', - 3: 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 4: 'AMD_COMGR_SYMBOL_TYPE_FILE', - 5: 'AMD_COMGR_SYMBOL_TYPE_COMMON', - 10: 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', -} -AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -1 -AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0 -AMD_COMGR_SYMBOL_TYPE_OBJECT = 1 -AMD_COMGR_SYMBOL_TYPE_FUNC = 2 -AMD_COMGR_SYMBOL_TYPE_SECTION = 3 -AMD_COMGR_SYMBOL_TYPE_FILE = 4 -AMD_COMGR_SYMBOL_TYPE_COMMON = 5 -AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 10 -amd_comgr_symbol_type_s = ctypes.c_int32 # enum -amd_comgr_symbol_type_t = amd_comgr_symbol_type_s -amd_comgr_symbol_type_t__enumvalues = amd_comgr_symbol_type_s__enumvalues - -# values for enumeration 'amd_comgr_symbol_info_s' -amd_comgr_symbol_info_s__enumvalues = { - 0: 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', - 1: 'AMD_COMGR_SYMBOL_INFO_NAME', - 2: 'AMD_COMGR_SYMBOL_INFO_TYPE', - 3: 'AMD_COMGR_SYMBOL_INFO_SIZE', - 4: 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 5: 'AMD_COMGR_SYMBOL_INFO_VALUE', - 5: 'AMD_COMGR_SYMBOL_INFO_LAST', -} -AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0 -AMD_COMGR_SYMBOL_INFO_NAME = 1 -AMD_COMGR_SYMBOL_INFO_TYPE = 2 -AMD_COMGR_SYMBOL_INFO_SIZE = 3 -AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 4 -AMD_COMGR_SYMBOL_INFO_VALUE = 5 -AMD_COMGR_SYMBOL_INFO_LAST = 5 -amd_comgr_symbol_info_s = ctypes.c_uint32 # enum -amd_comgr_symbol_info_t = amd_comgr_symbol_info_s -amd_comgr_symbol_info_t__enumvalues = amd_comgr_symbol_info_s__enumvalues -try: - amd_comgr_symbol_get_info = _libraries['libamd_comgr.so'].amd_comgr_symbol_get_info - amd_comgr_symbol_get_info.restype = amd_comgr_status_t - amd_comgr_symbol_get_info.argtypes = [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_create_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_create_disassembly_info - amd_comgr_create_disassembly_info.restype = amd_comgr_status_t - amd_comgr_create_disassembly_info.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(ctypes.c_char), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_disassembly_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_disassembly_info - amd_comgr_destroy_disassembly_info.restype = amd_comgr_status_t - amd_comgr_destroy_disassembly_info.argtypes = [amd_comgr_disassembly_info_t] -except AttributeError: - pass -try: - amd_comgr_disassemble_instruction = _libraries['libamd_comgr.so'].amd_comgr_disassemble_instruction - amd_comgr_disassemble_instruction.restype = amd_comgr_status_t - amd_comgr_disassemble_instruction.argtypes = [amd_comgr_disassembly_info_t, uint64_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_demangle_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_demangle_symbol_name - amd_comgr_demangle_symbol_name.restype = amd_comgr_status_t - amd_comgr_demangle_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_populate_mangled_names = _libraries['libamd_comgr.so'].amd_comgr_populate_mangled_names - amd_comgr_populate_mangled_names.restype = amd_comgr_status_t - amd_comgr_populate_mangled_names.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_get_mangled_name = _libraries['libamd_comgr.so'].amd_comgr_get_mangled_name - amd_comgr_get_mangled_name.restype = amd_comgr_status_t - amd_comgr_get_mangled_name.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_populate_name_expression_map = _libraries['libamd_comgr.so'].amd_comgr_populate_name_expression_map - amd_comgr_populate_name_expression_map.restype = amd_comgr_status_t - amd_comgr_populate_name_expression_map.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_map_name_expression_to_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_map_name_expression_to_symbol_name - amd_comgr_map_name_expression_to_symbol_name.restype = amd_comgr_status_t - amd_comgr_map_name_expression_to_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_code_object_info_s(Structure): - pass - -struct_code_object_info_s._pack_ = 1 # source:False -struct_code_object_info_s._fields_ = [ - ('isa', ctypes.POINTER(ctypes.c_char)), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), -] - -amd_comgr_code_object_info_t = struct_code_object_info_s -try: - amd_comgr_lookup_code_object = _libraries['libamd_comgr.so'].amd_comgr_lookup_code_object - amd_comgr_lookup_code_object.restype = amd_comgr_status_t - amd_comgr_lookup_code_object.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_code_object_info_s), size_t] -except AttributeError: - pass -try: - amd_comgr_map_elf_virtual_address_to_code_object_offset = _libraries['libamd_comgr.so'].amd_comgr_map_elf_virtual_address_to_code_object_offset - amd_comgr_map_elf_virtual_address_to_code_object_offset.restype = amd_comgr_status_t - amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = [amd_comgr_data_t, uint64_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -__all__ = \ - ['AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES', - 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_LAST', 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC', - 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 'AMD_COMGR_ACTION_UNBUNDLE', 'AMD_COMGR_DATA_KIND_AR', - 'AMD_COMGR_DATA_KIND_AR_BUNDLE', 'AMD_COMGR_DATA_KIND_BC', - 'AMD_COMGR_DATA_KIND_BC_BUNDLE', 'AMD_COMGR_DATA_KIND_BYTES', - 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 'AMD_COMGR_DATA_KIND_EXECUTABLE', 'AMD_COMGR_DATA_KIND_FATBIN', - 'AMD_COMGR_DATA_KIND_INCLUDE', 'AMD_COMGR_DATA_KIND_LAST', - 'AMD_COMGR_DATA_KIND_LOG', 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 'AMD_COMGR_DATA_KIND_RELOCATABLE', 'AMD_COMGR_DATA_KIND_SOURCE', - 'AMD_COMGR_DATA_KIND_UNDEF', 'AMD_COMGR_LANGUAGE_HC', - 'AMD_COMGR_LANGUAGE_HIP', 'AMD_COMGR_LANGUAGE_LAST', - 'AMD_COMGR_LANGUAGE_LLVM_IR', 'AMD_COMGR_LANGUAGE_NONE', - 'AMD_COMGR_LANGUAGE_OPENCL_1_2', 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 'AMD_COMGR_METADATA_KIND_LAST', 'AMD_COMGR_METADATA_KIND_LIST', - 'AMD_COMGR_METADATA_KIND_MAP', 'AMD_COMGR_METADATA_KIND_NULL', - 'AMD_COMGR_METADATA_KIND_STRING', 'AMD_COMGR_STATUS_ERROR', - 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', - 'AMD_COMGR_STATUS_SUCCESS', 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 'AMD_COMGR_SYMBOL_INFO_LAST', 'AMD_COMGR_SYMBOL_INFO_NAME', - 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 'AMD_COMGR_SYMBOL_INFO_SIZE', - 'AMD_COMGR_SYMBOL_INFO_TYPE', 'AMD_COMGR_SYMBOL_INFO_VALUE', - 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', - 'AMD_COMGR_SYMBOL_TYPE_COMMON', 'AMD_COMGR_SYMBOL_TYPE_FILE', - 'AMD_COMGR_SYMBOL_TYPE_FUNC', 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 'AMD_COMGR_SYMBOL_TYPE_OBJECT', 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', 'amd_comgr_action_data_count', - 'amd_comgr_action_data_get_data', - 'amd_comgr_action_info_get_bundle_entry_id', - 'amd_comgr_action_info_get_bundle_entry_id_count', - 'amd_comgr_action_info_get_isa_name', - 'amd_comgr_action_info_get_language', - 'amd_comgr_action_info_get_logging', - 'amd_comgr_action_info_get_option_list_count', - 'amd_comgr_action_info_get_option_list_item', - 'amd_comgr_action_info_get_options', - 'amd_comgr_action_info_get_working_directory_path', - 'amd_comgr_action_info_set_bundle_entry_ids', - 'amd_comgr_action_info_set_isa_name', - 'amd_comgr_action_info_set_language', - 'amd_comgr_action_info_set_logging', - 'amd_comgr_action_info_set_option_list', - 'amd_comgr_action_info_set_options', - 'amd_comgr_action_info_set_working_directory_path', - 'amd_comgr_action_info_t', 'amd_comgr_action_kind_s', - 'amd_comgr_action_kind_t', 'amd_comgr_action_kind_t__enumvalues', - 'amd_comgr_code_object_info_t', 'amd_comgr_create_action_info', - 'amd_comgr_create_data', 'amd_comgr_create_data_set', - 'amd_comgr_create_disassembly_info', - 'amd_comgr_create_symbolizer_info', 'amd_comgr_data_kind_s', - 'amd_comgr_data_kind_t', 'amd_comgr_data_kind_t__enumvalues', - 'amd_comgr_data_set_add', 'amd_comgr_data_set_remove', - 'amd_comgr_data_set_t', 'amd_comgr_data_t', - 'amd_comgr_demangle_symbol_name', 'amd_comgr_destroy_action_info', - 'amd_comgr_destroy_data_set', - 'amd_comgr_destroy_disassembly_info', - 'amd_comgr_destroy_metadata', 'amd_comgr_destroy_symbolizer_info', - 'amd_comgr_disassemble_instruction', - 'amd_comgr_disassembly_info_t', 'amd_comgr_do_action', - 'amd_comgr_get_data', 'amd_comgr_get_data_isa_name', - 'amd_comgr_get_data_kind', 'amd_comgr_get_data_metadata', - 'amd_comgr_get_data_name', 'amd_comgr_get_isa_count', - 'amd_comgr_get_isa_metadata', 'amd_comgr_get_isa_name', - 'amd_comgr_get_mangled_name', 'amd_comgr_get_metadata_kind', - 'amd_comgr_get_metadata_list_size', - 'amd_comgr_get_metadata_map_size', - 'amd_comgr_get_metadata_string', 'amd_comgr_get_version', - 'amd_comgr_index_list_metadata', 'amd_comgr_iterate_map_metadata', - 'amd_comgr_iterate_symbols', 'amd_comgr_language_s', - 'amd_comgr_language_t', 'amd_comgr_language_t__enumvalues', - 'amd_comgr_lookup_code_object', - 'amd_comgr_map_elf_virtual_address_to_code_object_offset', - 'amd_comgr_map_name_expression_to_symbol_name', - 'amd_comgr_metadata_kind_s', 'amd_comgr_metadata_kind_t', - 'amd_comgr_metadata_kind_t__enumvalues', - 'amd_comgr_metadata_lookup', 'amd_comgr_metadata_node_t', - 'amd_comgr_populate_mangled_names', - 'amd_comgr_populate_name_expression_map', - 'amd_comgr_release_data', 'amd_comgr_set_data', - 'amd_comgr_set_data_from_file_slice', 'amd_comgr_set_data_name', - 'amd_comgr_status_s', 'amd_comgr_status_string', - 'amd_comgr_status_t', 'amd_comgr_status_t__enumvalues', - 'amd_comgr_symbol_get_info', 'amd_comgr_symbol_info_s', - 'amd_comgr_symbol_info_t', 'amd_comgr_symbol_info_t__enumvalues', - 'amd_comgr_symbol_lookup', 'amd_comgr_symbol_t', - 'amd_comgr_symbol_type_s', 'amd_comgr_symbol_type_t', - 'amd_comgr_symbol_type_t__enumvalues', 'amd_comgr_symbolize', - 'amd_comgr_symbolizer_info_t', 'size_t', - 'struct_amd_comgr_action_info_s', 'struct_amd_comgr_data_s', - 'struct_amd_comgr_data_set_s', - 'struct_amd_comgr_disassembly_info_s', - 'struct_amd_comgr_metadata_node_s', 'struct_amd_comgr_symbol_s', - 'struct_amd_comgr_symbolizer_info_s', 'struct_code_object_info_s', - 'uint64_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/comgr_3.py b/tinygrad/tinygrad/runtime/autogen/comgr_3.py deleted file mode 100644 index 0fb7c920..00000000 --- a/tinygrad/tinygrad/runtime/autogen/comgr_3.py +++ /dev/null @@ -1,906 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os -PATHS_TO_TRY = [ - '/opt/rocm/lib/libamd_comgr.so', - os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so', - '/usr/local/lib/libamd_comgr.dylib', - '/opt/homebrew/lib/libamd_comgr.dylib', -] -def _try_dlopen_amd_comgr(): - library = ctypes.util.find_library("amd_comgr") - if library: return ctypes.CDLL(library) - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass - return None - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libamd_comgr.so'] = _try_dlopen_amd_comgr() -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - - -# values for enumeration 'amd_comgr_status_s' -amd_comgr_status_s__enumvalues = { - 0: 'AMD_COMGR_STATUS_SUCCESS', - 1: 'AMD_COMGR_STATUS_ERROR', - 2: 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 3: 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', -} -AMD_COMGR_STATUS_SUCCESS = 0 -AMD_COMGR_STATUS_ERROR = 1 -AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 2 -AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 3 -amd_comgr_status_s = ctypes.c_uint32 # enum -amd_comgr_status_t = amd_comgr_status_s -amd_comgr_status_t__enumvalues = amd_comgr_status_s__enumvalues - -# values for enumeration 'amd_comgr_language_s' -amd_comgr_language_s__enumvalues = { - 0: 'AMD_COMGR_LANGUAGE_NONE', - 1: 'AMD_COMGR_LANGUAGE_OPENCL_1_2', - 2: 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 3: 'AMD_COMGR_LANGUAGE_HIP', - 4: 'AMD_COMGR_LANGUAGE_LLVM_IR', - 4: 'AMD_COMGR_LANGUAGE_LAST', -} -AMD_COMGR_LANGUAGE_NONE = 0 -AMD_COMGR_LANGUAGE_OPENCL_1_2 = 1 -AMD_COMGR_LANGUAGE_OPENCL_2_0 = 2 -AMD_COMGR_LANGUAGE_HIP = 3 -AMD_COMGR_LANGUAGE_LLVM_IR = 4 -AMD_COMGR_LANGUAGE_LAST = 4 -amd_comgr_language_s = ctypes.c_uint32 # enum -amd_comgr_language_t = amd_comgr_language_s -amd_comgr_language_t__enumvalues = amd_comgr_language_s__enumvalues -try: - amd_comgr_status_string = _libraries['libamd_comgr.so'].amd_comgr_status_string - amd_comgr_status_string.restype = amd_comgr_status_t - amd_comgr_status_string.argtypes = [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_version = _libraries['libamd_comgr.so'].amd_comgr_get_version - amd_comgr_get_version.restype = None - amd_comgr_get_version.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_data_kind_s' -amd_comgr_data_kind_s__enumvalues = { - 0: 'AMD_COMGR_DATA_KIND_UNDEF', - 1: 'AMD_COMGR_DATA_KIND_SOURCE', - 2: 'AMD_COMGR_DATA_KIND_INCLUDE', - 3: 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 4: 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 5: 'AMD_COMGR_DATA_KIND_LOG', - 6: 'AMD_COMGR_DATA_KIND_BC', - 7: 'AMD_COMGR_DATA_KIND_RELOCATABLE', - 8: 'AMD_COMGR_DATA_KIND_EXECUTABLE', - 9: 'AMD_COMGR_DATA_KIND_BYTES', - 16: 'AMD_COMGR_DATA_KIND_FATBIN', - 17: 'AMD_COMGR_DATA_KIND_AR', - 18: 'AMD_COMGR_DATA_KIND_BC_BUNDLE', - 19: 'AMD_COMGR_DATA_KIND_AR_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 21: 'AMD_COMGR_DATA_KIND_SPIRV', - 21: 'AMD_COMGR_DATA_KIND_LAST', -} -AMD_COMGR_DATA_KIND_UNDEF = 0 -AMD_COMGR_DATA_KIND_SOURCE = 1 -AMD_COMGR_DATA_KIND_INCLUDE = 2 -AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 3 -AMD_COMGR_DATA_KIND_DIAGNOSTIC = 4 -AMD_COMGR_DATA_KIND_LOG = 5 -AMD_COMGR_DATA_KIND_BC = 6 -AMD_COMGR_DATA_KIND_RELOCATABLE = 7 -AMD_COMGR_DATA_KIND_EXECUTABLE = 8 -AMD_COMGR_DATA_KIND_BYTES = 9 -AMD_COMGR_DATA_KIND_FATBIN = 16 -AMD_COMGR_DATA_KIND_AR = 17 -AMD_COMGR_DATA_KIND_BC_BUNDLE = 18 -AMD_COMGR_DATA_KIND_AR_BUNDLE = 19 -AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 20 -AMD_COMGR_DATA_KIND_SPIRV = 21 -AMD_COMGR_DATA_KIND_LAST = 21 -amd_comgr_data_kind_s = ctypes.c_uint32 # enum -amd_comgr_data_kind_t = amd_comgr_data_kind_s -amd_comgr_data_kind_t__enumvalues = amd_comgr_data_kind_s__enumvalues -class struct_amd_comgr_data_s(Structure): - pass - -struct_amd_comgr_data_s._pack_ = 1 # source:False -struct_amd_comgr_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_t = struct_amd_comgr_data_s -class struct_amd_comgr_data_set_s(Structure): - pass - -struct_amd_comgr_data_set_s._pack_ = 1 # source:False -struct_amd_comgr_data_set_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_set_t = struct_amd_comgr_data_set_s -class struct_amd_comgr_action_info_s(Structure): - pass - -struct_amd_comgr_action_info_s._pack_ = 1 # source:False -struct_amd_comgr_action_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_action_info_t = struct_amd_comgr_action_info_s -class struct_amd_comgr_metadata_node_s(Structure): - pass - -struct_amd_comgr_metadata_node_s._pack_ = 1 # source:False -struct_amd_comgr_metadata_node_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_metadata_node_t = struct_amd_comgr_metadata_node_s -class struct_amd_comgr_symbol_s(Structure): - pass - -struct_amd_comgr_symbol_s._pack_ = 1 # source:False -struct_amd_comgr_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbol_t = struct_amd_comgr_symbol_s -class struct_amd_comgr_disassembly_info_s(Structure): - pass - -struct_amd_comgr_disassembly_info_s._pack_ = 1 # source:False -struct_amd_comgr_disassembly_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_disassembly_info_t = struct_amd_comgr_disassembly_info_s -class struct_amd_comgr_symbolizer_info_s(Structure): - pass - -struct_amd_comgr_symbolizer_info_s._pack_ = 1 # source:False -struct_amd_comgr_symbolizer_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbolizer_info_t = struct_amd_comgr_symbolizer_info_s -try: - amd_comgr_get_isa_count = _libraries['libamd_comgr.so'].amd_comgr_get_isa_count - amd_comgr_get_isa_count.restype = amd_comgr_status_t - amd_comgr_get_isa_count.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - amd_comgr_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_isa_name - amd_comgr_get_isa_name.restype = amd_comgr_status_t - amd_comgr_get_isa_name.argtypes = [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_isa_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_isa_metadata - amd_comgr_get_isa_metadata.restype = amd_comgr_status_t - amd_comgr_get_isa_metadata.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_create_data = _libraries['libamd_comgr.so'].amd_comgr_create_data - amd_comgr_create_data.restype = amd_comgr_status_t - amd_comgr_create_data.argtypes = [amd_comgr_data_kind_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_release_data = _libraries['libamd_comgr.so'].amd_comgr_release_data - amd_comgr_release_data.restype = amd_comgr_status_t - amd_comgr_release_data.argtypes = [amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_get_data_kind = _libraries['libamd_comgr.so'].amd_comgr_get_data_kind - amd_comgr_get_data_kind.restype = amd_comgr_status_t - amd_comgr_get_data_kind.argtypes = [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_s)] -except AttributeError: - pass -try: - amd_comgr_set_data = _libraries['libamd_comgr.so'].amd_comgr_set_data - amd_comgr_set_data.restype = amd_comgr_status_t - amd_comgr_set_data.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - amd_comgr_set_data_from_file_slice = _libraries['libamd_comgr.so'].amd_comgr_set_data_from_file_slice - amd_comgr_set_data_from_file_slice.restype = amd_comgr_status_t - amd_comgr_set_data_from_file_slice.argtypes = [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] -except AttributeError: - pass -try: - amd_comgr_set_data_name = _libraries['libamd_comgr.so'].amd_comgr_set_data_name - amd_comgr_set_data_name.restype = amd_comgr_status_t - amd_comgr_set_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data = _libraries['libamd_comgr.so'].amd_comgr_get_data - amd_comgr_get_data.restype = amd_comgr_status_t - amd_comgr_get_data.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_name - amd_comgr_get_data_name.restype = amd_comgr_status_t - amd_comgr_get_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_isa_name - amd_comgr_get_data_isa_name.restype = amd_comgr_status_t - amd_comgr_get_data_isa_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_create_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_create_symbolizer_info - amd_comgr_create_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_create_symbolizer_info.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_symbolizer_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_symbolizer_info - amd_comgr_destroy_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_destroy_symbolizer_info.argtypes = [amd_comgr_symbolizer_info_t] -except AttributeError: - pass -try: - amd_comgr_symbolize = _libraries['libamd_comgr.so'].amd_comgr_symbolize - amd_comgr_symbolize.restype = amd_comgr_status_t - amd_comgr_symbolize.argtypes = [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_get_data_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_data_metadata - amd_comgr_get_data_metadata.restype = amd_comgr_status_t - amd_comgr_get_data_metadata.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_metadata = _libraries['libamd_comgr.so'].amd_comgr_destroy_metadata - amd_comgr_destroy_metadata.restype = amd_comgr_status_t - amd_comgr_destroy_metadata.argtypes = [amd_comgr_metadata_node_t] -except AttributeError: - pass -try: - amd_comgr_create_data_set = _libraries['libamd_comgr.so'].amd_comgr_create_data_set - amd_comgr_create_data_set.restype = amd_comgr_status_t - amd_comgr_create_data_set.argtypes = [ctypes.POINTER(struct_amd_comgr_data_set_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_data_set = _libraries['libamd_comgr.so'].amd_comgr_destroy_data_set - amd_comgr_destroy_data_set.restype = amd_comgr_status_t - amd_comgr_destroy_data_set.argtypes = [amd_comgr_data_set_t] -except AttributeError: - pass -try: - amd_comgr_data_set_add = _libraries['libamd_comgr.so'].amd_comgr_data_set_add - amd_comgr_data_set_add.restype = amd_comgr_status_t - amd_comgr_data_set_add.argtypes = [amd_comgr_data_set_t, amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_data_set_remove = _libraries['libamd_comgr.so'].amd_comgr_data_set_remove - amd_comgr_data_set_remove.restype = amd_comgr_status_t - amd_comgr_data_set_remove.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t] -except AttributeError: - pass -try: - amd_comgr_action_data_count = _libraries['libamd_comgr.so'].amd_comgr_action_data_count - amd_comgr_action_data_count.restype = amd_comgr_status_t - amd_comgr_action_data_count.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_data_get_data = _libraries['libamd_comgr.so'].amd_comgr_action_data_get_data - amd_comgr_action_data_get_data.restype = amd_comgr_status_t - amd_comgr_action_data_get_data.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_create_action_info = _libraries['libamd_comgr.so'].amd_comgr_create_action_info - amd_comgr_create_action_info.restype = amd_comgr_status_t - amd_comgr_create_action_info.argtypes = [ctypes.POINTER(struct_amd_comgr_action_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_action_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_action_info - amd_comgr_destroy_action_info.restype = amd_comgr_status_t - amd_comgr_destroy_action_info.argtypes = [amd_comgr_action_info_t] -except AttributeError: - pass -try: - amd_comgr_action_info_set_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_isa_name - amd_comgr_action_info_set_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_set_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_isa_name - amd_comgr_action_info_get_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_get_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_language - amd_comgr_action_info_set_language.restype = amd_comgr_status_t - amd_comgr_action_info_set_language.argtypes = [amd_comgr_action_info_t, amd_comgr_language_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_language - amd_comgr_action_info_get_language.restype = amd_comgr_status_t - amd_comgr_action_info_get_language.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_s)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_option_list = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_option_list - amd_comgr_action_info_set_option_list.restype = amd_comgr_status_t - amd_comgr_action_info_set_option_list.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_count - amd_comgr_action_info_get_option_list_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_item = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_item - amd_comgr_action_info_get_option_list_item.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_item.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_bundle_entry_ids = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_bundle_entry_ids - amd_comgr_action_info_set_bundle_entry_ids.restype = amd_comgr_status_t - amd_comgr_action_info_set_bundle_entry_ids.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id_count - amd_comgr_action_info_get_bundle_entry_id_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id - amd_comgr_action_info_get_bundle_entry_id.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_device_lib_linking = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_device_lib_linking - amd_comgr_action_info_set_device_lib_linking.restype = amd_comgr_status_t - amd_comgr_action_info_set_device_lib_linking.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_set_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_working_directory_path - amd_comgr_action_info_set_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_set_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_working_directory_path - amd_comgr_action_info_get_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_get_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_logging - amd_comgr_action_info_set_logging.restype = amd_comgr_status_t - amd_comgr_action_info_set_logging.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_get_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_logging - amd_comgr_action_info_get_logging.restype = amd_comgr_status_t - amd_comgr_action_info_get_logging.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_action_kind_s' -amd_comgr_action_kind_s__enumvalues = { - 0: 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 1: 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 2: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 3: 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 4: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 5: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 6: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 7: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 8: 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 9: 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 10: 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 11: 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 12: 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 13: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 14: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 15: 'AMD_COMGR_ACTION_UNBUNDLE', - 19: 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 19: 'AMD_COMGR_ACTION_LAST', -} -AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0 -AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = 1 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 2 -AMD_COMGR_ACTION_LINK_BC_TO_BC = 3 -AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 4 -AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 5 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 6 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 7 -AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 8 -AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = 9 -AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = 10 -AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = 11 -AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 12 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 13 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 14 -AMD_COMGR_ACTION_UNBUNDLE = 15 -AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC = 19 -AMD_COMGR_ACTION_LAST = 19 -amd_comgr_action_kind_s = ctypes.c_uint32 # enum -amd_comgr_action_kind_t = amd_comgr_action_kind_s -amd_comgr_action_kind_t__enumvalues = amd_comgr_action_kind_s__enumvalues -try: - amd_comgr_do_action = _libraries['libamd_comgr.so'].amd_comgr_do_action - amd_comgr_do_action.restype = amd_comgr_status_t - amd_comgr_do_action.argtypes = [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_metadata_kind_s' -amd_comgr_metadata_kind_s__enumvalues = { - 0: 'AMD_COMGR_METADATA_KIND_NULL', - 1: 'AMD_COMGR_METADATA_KIND_STRING', - 2: 'AMD_COMGR_METADATA_KIND_MAP', - 3: 'AMD_COMGR_METADATA_KIND_LIST', - 3: 'AMD_COMGR_METADATA_KIND_LAST', -} -AMD_COMGR_METADATA_KIND_NULL = 0 -AMD_COMGR_METADATA_KIND_STRING = 1 -AMD_COMGR_METADATA_KIND_MAP = 2 -AMD_COMGR_METADATA_KIND_LIST = 3 -AMD_COMGR_METADATA_KIND_LAST = 3 -amd_comgr_metadata_kind_s = ctypes.c_uint32 # enum -amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s -amd_comgr_metadata_kind_t__enumvalues = amd_comgr_metadata_kind_s__enumvalues -try: - amd_comgr_get_metadata_kind = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_kind - amd_comgr_get_metadata_kind.restype = amd_comgr_status_t - amd_comgr_get_metadata_kind.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_string = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_string - amd_comgr_get_metadata_string.restype = amd_comgr_status_t - amd_comgr_get_metadata_string.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_map_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_map_size - amd_comgr_get_metadata_map_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_map_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_iterate_map_metadata = _libraries['libamd_comgr.so'].amd_comgr_iterate_map_metadata - amd_comgr_iterate_map_metadata.restype = amd_comgr_status_t - amd_comgr_iterate_map_metadata.argtypes = [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_metadata_node_s, struct_amd_comgr_metadata_node_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_metadata_lookup = _libraries['libamd_comgr.so'].amd_comgr_metadata_lookup - amd_comgr_metadata_lookup.restype = amd_comgr_status_t - amd_comgr_metadata_lookup.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_list_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_list_size - amd_comgr_get_metadata_list_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_list_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_index_list_metadata = _libraries['libamd_comgr.so'].amd_comgr_index_list_metadata - amd_comgr_index_list_metadata.restype = amd_comgr_status_t - amd_comgr_index_list_metadata.argtypes = [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_iterate_symbols = _libraries['libamd_comgr.so'].amd_comgr_iterate_symbols - amd_comgr_iterate_symbols.restype = amd_comgr_status_t - amd_comgr_iterate_symbols.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_symbol_lookup = _libraries['libamd_comgr.so'].amd_comgr_symbol_lookup - amd_comgr_symbol_lookup.restype = amd_comgr_status_t - amd_comgr_symbol_lookup.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_symbol_type_s' -amd_comgr_symbol_type_s__enumvalues = { - -1: 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', - 0: 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 1: 'AMD_COMGR_SYMBOL_TYPE_OBJECT', - 2: 'AMD_COMGR_SYMBOL_TYPE_FUNC', - 3: 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 4: 'AMD_COMGR_SYMBOL_TYPE_FILE', - 5: 'AMD_COMGR_SYMBOL_TYPE_COMMON', - 10: 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', -} -AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -1 -AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0 -AMD_COMGR_SYMBOL_TYPE_OBJECT = 1 -AMD_COMGR_SYMBOL_TYPE_FUNC = 2 -AMD_COMGR_SYMBOL_TYPE_SECTION = 3 -AMD_COMGR_SYMBOL_TYPE_FILE = 4 -AMD_COMGR_SYMBOL_TYPE_COMMON = 5 -AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 10 -amd_comgr_symbol_type_s = ctypes.c_int32 # enum -amd_comgr_symbol_type_t = amd_comgr_symbol_type_s -amd_comgr_symbol_type_t__enumvalues = amd_comgr_symbol_type_s__enumvalues - -# values for enumeration 'amd_comgr_symbol_info_s' -amd_comgr_symbol_info_s__enumvalues = { - 0: 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', - 1: 'AMD_COMGR_SYMBOL_INFO_NAME', - 2: 'AMD_COMGR_SYMBOL_INFO_TYPE', - 3: 'AMD_COMGR_SYMBOL_INFO_SIZE', - 4: 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 5: 'AMD_COMGR_SYMBOL_INFO_VALUE', - 5: 'AMD_COMGR_SYMBOL_INFO_LAST', -} -AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0 -AMD_COMGR_SYMBOL_INFO_NAME = 1 -AMD_COMGR_SYMBOL_INFO_TYPE = 2 -AMD_COMGR_SYMBOL_INFO_SIZE = 3 -AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 4 -AMD_COMGR_SYMBOL_INFO_VALUE = 5 -AMD_COMGR_SYMBOL_INFO_LAST = 5 -amd_comgr_symbol_info_s = ctypes.c_uint32 # enum -amd_comgr_symbol_info_t = amd_comgr_symbol_info_s -amd_comgr_symbol_info_t__enumvalues = amd_comgr_symbol_info_s__enumvalues -try: - amd_comgr_symbol_get_info = _libraries['libamd_comgr.so'].amd_comgr_symbol_get_info - amd_comgr_symbol_get_info.restype = amd_comgr_status_t - amd_comgr_symbol_get_info.argtypes = [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_create_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_create_disassembly_info - amd_comgr_create_disassembly_info.restype = amd_comgr_status_t - amd_comgr_create_disassembly_info.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(ctypes.c_char), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_disassembly_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_disassembly_info - amd_comgr_destroy_disassembly_info.restype = amd_comgr_status_t - amd_comgr_destroy_disassembly_info.argtypes = [amd_comgr_disassembly_info_t] -except AttributeError: - pass -try: - amd_comgr_disassemble_instruction = _libraries['libamd_comgr.so'].amd_comgr_disassemble_instruction - amd_comgr_disassemble_instruction.restype = amd_comgr_status_t - amd_comgr_disassemble_instruction.argtypes = [amd_comgr_disassembly_info_t, uint64_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_demangle_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_demangle_symbol_name - amd_comgr_demangle_symbol_name.restype = amd_comgr_status_t - amd_comgr_demangle_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_populate_mangled_names = _libraries['libamd_comgr.so'].amd_comgr_populate_mangled_names - amd_comgr_populate_mangled_names.restype = amd_comgr_status_t - amd_comgr_populate_mangled_names.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_get_mangled_name = _libraries['libamd_comgr.so'].amd_comgr_get_mangled_name - amd_comgr_get_mangled_name.restype = amd_comgr_status_t - amd_comgr_get_mangled_name.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_populate_name_expression_map = _libraries['libamd_comgr.so'].amd_comgr_populate_name_expression_map - amd_comgr_populate_name_expression_map.restype = amd_comgr_status_t - amd_comgr_populate_name_expression_map.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_map_name_expression_to_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_map_name_expression_to_symbol_name - amd_comgr_map_name_expression_to_symbol_name.restype = amd_comgr_status_t - amd_comgr_map_name_expression_to_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_code_object_info_s(Structure): - pass - -struct_code_object_info_s._pack_ = 1 # source:False -struct_code_object_info_s._fields_ = [ - ('isa', ctypes.POINTER(ctypes.c_char)), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), -] - -amd_comgr_code_object_info_t = struct_code_object_info_s -try: - amd_comgr_lookup_code_object = _libraries['libamd_comgr.so'].amd_comgr_lookup_code_object - amd_comgr_lookup_code_object.restype = amd_comgr_status_t - amd_comgr_lookup_code_object.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_code_object_info_s), size_t] -except AttributeError: - pass -try: - amd_comgr_map_elf_virtual_address_to_code_object_offset = _libraries['libamd_comgr.so'].amd_comgr_map_elf_virtual_address_to_code_object_offset - amd_comgr_map_elf_virtual_address_to_code_object_offset.restype = amd_comgr_status_t - amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = [amd_comgr_data_t, uint64_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -__all__ = \ - ['AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_LAST', 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 'AMD_COMGR_ACTION_UNBUNDLE', 'AMD_COMGR_DATA_KIND_AR', - 'AMD_COMGR_DATA_KIND_AR_BUNDLE', 'AMD_COMGR_DATA_KIND_BC', - 'AMD_COMGR_DATA_KIND_BC_BUNDLE', 'AMD_COMGR_DATA_KIND_BYTES', - 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 'AMD_COMGR_DATA_KIND_EXECUTABLE', 'AMD_COMGR_DATA_KIND_FATBIN', - 'AMD_COMGR_DATA_KIND_INCLUDE', 'AMD_COMGR_DATA_KIND_LAST', - 'AMD_COMGR_DATA_KIND_LOG', 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 'AMD_COMGR_DATA_KIND_RELOCATABLE', 'AMD_COMGR_DATA_KIND_SOURCE', - 'AMD_COMGR_DATA_KIND_SPIRV', 'AMD_COMGR_DATA_KIND_UNDEF', - 'AMD_COMGR_LANGUAGE_HIP', 'AMD_COMGR_LANGUAGE_LAST', - 'AMD_COMGR_LANGUAGE_LLVM_IR', 'AMD_COMGR_LANGUAGE_NONE', - 'AMD_COMGR_LANGUAGE_OPENCL_1_2', 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 'AMD_COMGR_METADATA_KIND_LAST', 'AMD_COMGR_METADATA_KIND_LIST', - 'AMD_COMGR_METADATA_KIND_MAP', 'AMD_COMGR_METADATA_KIND_NULL', - 'AMD_COMGR_METADATA_KIND_STRING', 'AMD_COMGR_STATUS_ERROR', - 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', - 'AMD_COMGR_STATUS_SUCCESS', 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 'AMD_COMGR_SYMBOL_INFO_LAST', 'AMD_COMGR_SYMBOL_INFO_NAME', - 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 'AMD_COMGR_SYMBOL_INFO_SIZE', - 'AMD_COMGR_SYMBOL_INFO_TYPE', 'AMD_COMGR_SYMBOL_INFO_VALUE', - 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', - 'AMD_COMGR_SYMBOL_TYPE_COMMON', 'AMD_COMGR_SYMBOL_TYPE_FILE', - 'AMD_COMGR_SYMBOL_TYPE_FUNC', 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 'AMD_COMGR_SYMBOL_TYPE_OBJECT', 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', 'amd_comgr_action_data_count', - 'amd_comgr_action_data_get_data', - 'amd_comgr_action_info_get_bundle_entry_id', - 'amd_comgr_action_info_get_bundle_entry_id_count', - 'amd_comgr_action_info_get_isa_name', - 'amd_comgr_action_info_get_language', - 'amd_comgr_action_info_get_logging', - 'amd_comgr_action_info_get_option_list_count', - 'amd_comgr_action_info_get_option_list_item', - 'amd_comgr_action_info_get_working_directory_path', - 'amd_comgr_action_info_set_bundle_entry_ids', - 'amd_comgr_action_info_set_device_lib_linking', - 'amd_comgr_action_info_set_isa_name', - 'amd_comgr_action_info_set_language', - 'amd_comgr_action_info_set_logging', - 'amd_comgr_action_info_set_option_list', - 'amd_comgr_action_info_set_working_directory_path', - 'amd_comgr_action_info_t', 'amd_comgr_action_kind_s', - 'amd_comgr_action_kind_t', 'amd_comgr_action_kind_t__enumvalues', - 'amd_comgr_code_object_info_t', 'amd_comgr_create_action_info', - 'amd_comgr_create_data', 'amd_comgr_create_data_set', - 'amd_comgr_create_disassembly_info', - 'amd_comgr_create_symbolizer_info', 'amd_comgr_data_kind_s', - 'amd_comgr_data_kind_t', 'amd_comgr_data_kind_t__enumvalues', - 'amd_comgr_data_set_add', 'amd_comgr_data_set_remove', - 'amd_comgr_data_set_t', 'amd_comgr_data_t', - 'amd_comgr_demangle_symbol_name', 'amd_comgr_destroy_action_info', - 'amd_comgr_destroy_data_set', - 'amd_comgr_destroy_disassembly_info', - 'amd_comgr_destroy_metadata', 'amd_comgr_destroy_symbolizer_info', - 'amd_comgr_disassemble_instruction', - 'amd_comgr_disassembly_info_t', 'amd_comgr_do_action', - 'amd_comgr_get_data', 'amd_comgr_get_data_isa_name', - 'amd_comgr_get_data_kind', 'amd_comgr_get_data_metadata', - 'amd_comgr_get_data_name', 'amd_comgr_get_isa_count', - 'amd_comgr_get_isa_metadata', 'amd_comgr_get_isa_name', - 'amd_comgr_get_mangled_name', 'amd_comgr_get_metadata_kind', - 'amd_comgr_get_metadata_list_size', - 'amd_comgr_get_metadata_map_size', - 'amd_comgr_get_metadata_string', 'amd_comgr_get_version', - 'amd_comgr_index_list_metadata', 'amd_comgr_iterate_map_metadata', - 'amd_comgr_iterate_symbols', 'amd_comgr_language_s', - 'amd_comgr_language_t', 'amd_comgr_language_t__enumvalues', - 'amd_comgr_lookup_code_object', - 'amd_comgr_map_elf_virtual_address_to_code_object_offset', - 'amd_comgr_map_name_expression_to_symbol_name', - 'amd_comgr_metadata_kind_s', 'amd_comgr_metadata_kind_t', - 'amd_comgr_metadata_kind_t__enumvalues', - 'amd_comgr_metadata_lookup', 'amd_comgr_metadata_node_t', - 'amd_comgr_populate_mangled_names', - 'amd_comgr_populate_name_expression_map', - 'amd_comgr_release_data', 'amd_comgr_set_data', - 'amd_comgr_set_data_from_file_slice', 'amd_comgr_set_data_name', - 'amd_comgr_status_s', 'amd_comgr_status_string', - 'amd_comgr_status_t', 'amd_comgr_status_t__enumvalues', - 'amd_comgr_symbol_get_info', 'amd_comgr_symbol_info_s', - 'amd_comgr_symbol_info_t', 'amd_comgr_symbol_info_t__enumvalues', - 'amd_comgr_symbol_lookup', 'amd_comgr_symbol_t', - 'amd_comgr_symbol_type_s', 'amd_comgr_symbol_type_t', - 'amd_comgr_symbol_type_t__enumvalues', 'amd_comgr_symbolize', - 'amd_comgr_symbolizer_info_t', 'size_t', - 'struct_amd_comgr_action_info_s', 'struct_amd_comgr_data_s', - 'struct_amd_comgr_data_set_s', - 'struct_amd_comgr_disassembly_info_s', - 'struct_amd_comgr_metadata_node_s', 'struct_amd_comgr_symbol_s', - 'struct_amd_comgr_symbolizer_info_s', 'struct_code_object_info_s', - 'uint64_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/cuda.py b/tinygrad/tinygrad/runtime/autogen/cuda.py deleted file mode 100644 index 55c101ae..00000000 --- a/tinygrad/tinygrad/runtime/autogen/cuda.py +++ /dev/null @@ -1,7692 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__CUDA_API_VERSION_INTERNAL'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libcuda.so'] = ctypes.CDLL(ctypes.util.find_library('cuda')) - - -cuuint32_t = ctypes.c_uint32 -cuuint64_t = ctypes.c_uint64 -CUdeviceptr_v2 = ctypes.c_uint64 -CUdeviceptr = ctypes.c_uint64 -CUdevice_v1 = ctypes.c_int32 -CUdevice = ctypes.c_int32 -class struct_CUctx_st(Structure): - pass - -CUcontext = ctypes.POINTER(struct_CUctx_st) -class struct_CUmod_st(Structure): - pass - -CUmodule = ctypes.POINTER(struct_CUmod_st) -class struct_CUfunc_st(Structure): - pass - -CUfunction = ctypes.POINTER(struct_CUfunc_st) -class struct_CUlib_st(Structure): - pass - -CUlibrary = ctypes.POINTER(struct_CUlib_st) -class struct_CUkern_st(Structure): - pass - -CUkernel = ctypes.POINTER(struct_CUkern_st) -class struct_CUarray_st(Structure): - pass - -CUarray = ctypes.POINTER(struct_CUarray_st) -class struct_CUmipmappedArray_st(Structure): - pass - -CUmipmappedArray = ctypes.POINTER(struct_CUmipmappedArray_st) -class struct_CUtexref_st(Structure): - pass - -CUtexref = ctypes.POINTER(struct_CUtexref_st) -class struct_CUsurfref_st(Structure): - pass - -CUsurfref = ctypes.POINTER(struct_CUsurfref_st) -class struct_CUevent_st(Structure): - pass - -CUevent = ctypes.POINTER(struct_CUevent_st) -class struct_CUstream_st(Structure): - pass - -CUstream = ctypes.POINTER(struct_CUstream_st) -class struct_CUgraphicsResource_st(Structure): - pass - -CUgraphicsResource = ctypes.POINTER(struct_CUgraphicsResource_st) -CUtexObject_v1 = ctypes.c_uint64 -CUtexObject = ctypes.c_uint64 -CUsurfObject_v1 = ctypes.c_uint64 -CUsurfObject = ctypes.c_uint64 -class struct_CUextMemory_st(Structure): - pass - -CUexternalMemory = ctypes.POINTER(struct_CUextMemory_st) -class struct_CUextSemaphore_st(Structure): - pass - -CUexternalSemaphore = ctypes.POINTER(struct_CUextSemaphore_st) -class struct_CUgraph_st(Structure): - pass - -CUgraph = ctypes.POINTER(struct_CUgraph_st) -class struct_CUgraphNode_st(Structure): - pass - -CUgraphNode = ctypes.POINTER(struct_CUgraphNode_st) -class struct_CUgraphExec_st(Structure): - pass - -CUgraphExec = ctypes.POINTER(struct_CUgraphExec_st) -class struct_CUmemPoolHandle_st(Structure): - pass - -CUmemoryPool = ctypes.POINTER(struct_CUmemPoolHandle_st) -class struct_CUuserObject_st(Structure): - pass - -CUuserObject = ctypes.POINTER(struct_CUuserObject_st) -class struct_CUuuid_st(Structure): - pass - -struct_CUuuid_st._pack_ = 1 # source:False -struct_CUuuid_st._fields_ = [ - ('bytes', ctypes.c_char * 16), -] - -CUuuid = struct_CUuuid_st -class struct_CUipcEventHandle_st(Structure): - pass - -struct_CUipcEventHandle_st._pack_ = 1 # source:False -struct_CUipcEventHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -CUipcEventHandle_v1 = struct_CUipcEventHandle_st -CUipcEventHandle = struct_CUipcEventHandle_st -class struct_CUipcMemHandle_st(Structure): - pass - -struct_CUipcMemHandle_st._pack_ = 1 # source:False -struct_CUipcMemHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -CUipcMemHandle_v1 = struct_CUipcMemHandle_st -CUipcMemHandle = struct_CUipcMemHandle_st - -# values for enumeration 'CUipcMem_flags_enum' -CUipcMem_flags_enum__enumvalues = { - 1: 'CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS', -} -CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS = 1 -CUipcMem_flags_enum = ctypes.c_uint32 # enum -CUipcMem_flags = CUipcMem_flags_enum -CUipcMem_flags__enumvalues = CUipcMem_flags_enum__enumvalues - -# values for enumeration 'CUmemAttach_flags_enum' -CUmemAttach_flags_enum__enumvalues = { - 1: 'CU_MEM_ATTACH_GLOBAL', - 2: 'CU_MEM_ATTACH_HOST', - 4: 'CU_MEM_ATTACH_SINGLE', -} -CU_MEM_ATTACH_GLOBAL = 1 -CU_MEM_ATTACH_HOST = 2 -CU_MEM_ATTACH_SINGLE = 4 -CUmemAttach_flags_enum = ctypes.c_uint32 # enum -CUmemAttach_flags = CUmemAttach_flags_enum -CUmemAttach_flags__enumvalues = CUmemAttach_flags_enum__enumvalues - -# values for enumeration 'CUctx_flags_enum' -CUctx_flags_enum__enumvalues = { - 0: 'CU_CTX_SCHED_AUTO', - 1: 'CU_CTX_SCHED_SPIN', - 2: 'CU_CTX_SCHED_YIELD', - 4: 'CU_CTX_SCHED_BLOCKING_SYNC', - 4: 'CU_CTX_BLOCKING_SYNC', - 7: 'CU_CTX_SCHED_MASK', - 8: 'CU_CTX_MAP_HOST', - 16: 'CU_CTX_LMEM_RESIZE_TO_MAX', - 31: 'CU_CTX_FLAGS_MASK', -} -CU_CTX_SCHED_AUTO = 0 -CU_CTX_SCHED_SPIN = 1 -CU_CTX_SCHED_YIELD = 2 -CU_CTX_SCHED_BLOCKING_SYNC = 4 -CU_CTX_BLOCKING_SYNC = 4 -CU_CTX_SCHED_MASK = 7 -CU_CTX_MAP_HOST = 8 -CU_CTX_LMEM_RESIZE_TO_MAX = 16 -CU_CTX_FLAGS_MASK = 31 -CUctx_flags_enum = ctypes.c_uint32 # enum -CUctx_flags = CUctx_flags_enum -CUctx_flags__enumvalues = CUctx_flags_enum__enumvalues - -# values for enumeration 'CUevent_sched_flags_enum' -CUevent_sched_flags_enum__enumvalues = { - 0: 'CU_EVENT_SCHED_AUTO', - 1: 'CU_EVENT_SCHED_SPIN', - 2: 'CU_EVENT_SCHED_YIELD', - 4: 'CU_EVENT_SCHED_BLOCKING_SYNC', -} -CU_EVENT_SCHED_AUTO = 0 -CU_EVENT_SCHED_SPIN = 1 -CU_EVENT_SCHED_YIELD = 2 -CU_EVENT_SCHED_BLOCKING_SYNC = 4 -CUevent_sched_flags_enum = ctypes.c_uint32 # enum -CUevent_sched_flags = CUevent_sched_flags_enum -CUevent_sched_flags__enumvalues = CUevent_sched_flags_enum__enumvalues - -# values for enumeration 'cl_event_flags_enum' -cl_event_flags_enum__enumvalues = { - 0: 'NVCL_EVENT_SCHED_AUTO', - 1: 'NVCL_EVENT_SCHED_SPIN', - 2: 'NVCL_EVENT_SCHED_YIELD', - 4: 'NVCL_EVENT_SCHED_BLOCKING_SYNC', -} -NVCL_EVENT_SCHED_AUTO = 0 -NVCL_EVENT_SCHED_SPIN = 1 -NVCL_EVENT_SCHED_YIELD = 2 -NVCL_EVENT_SCHED_BLOCKING_SYNC = 4 -cl_event_flags_enum = ctypes.c_uint32 # enum -cl_event_flags = cl_event_flags_enum -cl_event_flags__enumvalues = cl_event_flags_enum__enumvalues - -# values for enumeration 'cl_context_flags_enum' -cl_context_flags_enum__enumvalues = { - 0: 'NVCL_CTX_SCHED_AUTO', - 1: 'NVCL_CTX_SCHED_SPIN', - 2: 'NVCL_CTX_SCHED_YIELD', - 4: 'NVCL_CTX_SCHED_BLOCKING_SYNC', -} -NVCL_CTX_SCHED_AUTO = 0 -NVCL_CTX_SCHED_SPIN = 1 -NVCL_CTX_SCHED_YIELD = 2 -NVCL_CTX_SCHED_BLOCKING_SYNC = 4 -cl_context_flags_enum = ctypes.c_uint32 # enum -cl_context_flags = cl_context_flags_enum -cl_context_flags__enumvalues = cl_context_flags_enum__enumvalues - -# values for enumeration 'CUstream_flags_enum' -CUstream_flags_enum__enumvalues = { - 0: 'CU_STREAM_DEFAULT', - 1: 'CU_STREAM_NON_BLOCKING', -} -CU_STREAM_DEFAULT = 0 -CU_STREAM_NON_BLOCKING = 1 -CUstream_flags_enum = ctypes.c_uint32 # enum -CUstream_flags = CUstream_flags_enum -CUstream_flags__enumvalues = CUstream_flags_enum__enumvalues - -# values for enumeration 'CUevent_flags_enum' -CUevent_flags_enum__enumvalues = { - 0: 'CU_EVENT_DEFAULT', - 1: 'CU_EVENT_BLOCKING_SYNC', - 2: 'CU_EVENT_DISABLE_TIMING', - 4: 'CU_EVENT_INTERPROCESS', -} -CU_EVENT_DEFAULT = 0 -CU_EVENT_BLOCKING_SYNC = 1 -CU_EVENT_DISABLE_TIMING = 2 -CU_EVENT_INTERPROCESS = 4 -CUevent_flags_enum = ctypes.c_uint32 # enum -CUevent_flags = CUevent_flags_enum -CUevent_flags__enumvalues = CUevent_flags_enum__enumvalues - -# values for enumeration 'CUevent_record_flags_enum' -CUevent_record_flags_enum__enumvalues = { - 0: 'CU_EVENT_RECORD_DEFAULT', - 1: 'CU_EVENT_RECORD_EXTERNAL', -} -CU_EVENT_RECORD_DEFAULT = 0 -CU_EVENT_RECORD_EXTERNAL = 1 -CUevent_record_flags_enum = ctypes.c_uint32 # enum -CUevent_record_flags = CUevent_record_flags_enum -CUevent_record_flags__enumvalues = CUevent_record_flags_enum__enumvalues - -# values for enumeration 'CUevent_wait_flags_enum' -CUevent_wait_flags_enum__enumvalues = { - 0: 'CU_EVENT_WAIT_DEFAULT', - 1: 'CU_EVENT_WAIT_EXTERNAL', -} -CU_EVENT_WAIT_DEFAULT = 0 -CU_EVENT_WAIT_EXTERNAL = 1 -CUevent_wait_flags_enum = ctypes.c_uint32 # enum -CUevent_wait_flags = CUevent_wait_flags_enum -CUevent_wait_flags__enumvalues = CUevent_wait_flags_enum__enumvalues - -# values for enumeration 'CUstreamWaitValue_flags_enum' -CUstreamWaitValue_flags_enum__enumvalues = { - 0: 'CU_STREAM_WAIT_VALUE_GEQ', - 1: 'CU_STREAM_WAIT_VALUE_EQ', - 2: 'CU_STREAM_WAIT_VALUE_AND', - 3: 'CU_STREAM_WAIT_VALUE_NOR', - 1073741824: 'CU_STREAM_WAIT_VALUE_FLUSH', -} -CU_STREAM_WAIT_VALUE_GEQ = 0 -CU_STREAM_WAIT_VALUE_EQ = 1 -CU_STREAM_WAIT_VALUE_AND = 2 -CU_STREAM_WAIT_VALUE_NOR = 3 -CU_STREAM_WAIT_VALUE_FLUSH = 1073741824 -CUstreamWaitValue_flags_enum = ctypes.c_uint32 # enum -CUstreamWaitValue_flags = CUstreamWaitValue_flags_enum -CUstreamWaitValue_flags__enumvalues = CUstreamWaitValue_flags_enum__enumvalues - -# values for enumeration 'CUstreamWriteValue_flags_enum' -CUstreamWriteValue_flags_enum__enumvalues = { - 0: 'CU_STREAM_WRITE_VALUE_DEFAULT', - 1: 'CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER', -} -CU_STREAM_WRITE_VALUE_DEFAULT = 0 -CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER = 1 -CUstreamWriteValue_flags_enum = ctypes.c_uint32 # enum -CUstreamWriteValue_flags = CUstreamWriteValue_flags_enum -CUstreamWriteValue_flags__enumvalues = CUstreamWriteValue_flags_enum__enumvalues - -# values for enumeration 'CUstreamBatchMemOpType_enum' -CUstreamBatchMemOpType_enum__enumvalues = { - 1: 'CU_STREAM_MEM_OP_WAIT_VALUE_32', - 2: 'CU_STREAM_MEM_OP_WRITE_VALUE_32', - 4: 'CU_STREAM_MEM_OP_WAIT_VALUE_64', - 5: 'CU_STREAM_MEM_OP_WRITE_VALUE_64', - 6: 'CU_STREAM_MEM_OP_BARRIER', - 3: 'CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES', -} -CU_STREAM_MEM_OP_WAIT_VALUE_32 = 1 -CU_STREAM_MEM_OP_WRITE_VALUE_32 = 2 -CU_STREAM_MEM_OP_WAIT_VALUE_64 = 4 -CU_STREAM_MEM_OP_WRITE_VALUE_64 = 5 -CU_STREAM_MEM_OP_BARRIER = 6 -CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES = 3 -CUstreamBatchMemOpType_enum = ctypes.c_uint32 # enum -CUstreamBatchMemOpType = CUstreamBatchMemOpType_enum -CUstreamBatchMemOpType__enumvalues = CUstreamBatchMemOpType_enum__enumvalues - -# values for enumeration 'CUstreamMemoryBarrier_flags_enum' -CUstreamMemoryBarrier_flags_enum__enumvalues = { - 0: 'CU_STREAM_MEMORY_BARRIER_TYPE_SYS', - 1: 'CU_STREAM_MEMORY_BARRIER_TYPE_GPU', -} -CU_STREAM_MEMORY_BARRIER_TYPE_SYS = 0 -CU_STREAM_MEMORY_BARRIER_TYPE_GPU = 1 -CUstreamMemoryBarrier_flags_enum = ctypes.c_uint32 # enum -CUstreamMemoryBarrier_flags = CUstreamMemoryBarrier_flags_enum -CUstreamMemoryBarrier_flags__enumvalues = CUstreamMemoryBarrier_flags_enum__enumvalues -class union_CUstreamBatchMemOpParams_union(Union): - pass - -class struct_CUstreamMemOpWaitValueParams_st(Structure): - pass - -class union_CUstreamMemOpWaitValueParams_st_0(Union): - pass - -union_CUstreamMemOpWaitValueParams_st_0._pack_ = 1 # source:False -union_CUstreamMemOpWaitValueParams_st_0._fields_ = [ - ('value', ctypes.c_uint32), - ('value64', ctypes.c_uint64), -] - -struct_CUstreamMemOpWaitValueParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpWaitValueParams_st._anonymous_ = ('_0',) -struct_CUstreamMemOpWaitValueParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), - ('_0', union_CUstreamMemOpWaitValueParams_st_0), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('alias', ctypes.c_uint64), -] - -class struct_CUstreamMemOpWriteValueParams_st(Structure): - pass - -class union_CUstreamMemOpWriteValueParams_st_0(Union): - pass - -union_CUstreamMemOpWriteValueParams_st_0._pack_ = 1 # source:False -union_CUstreamMemOpWriteValueParams_st_0._fields_ = [ - ('value', ctypes.c_uint32), - ('value64', ctypes.c_uint64), -] - -struct_CUstreamMemOpWriteValueParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpWriteValueParams_st._anonymous_ = ('_0',) -struct_CUstreamMemOpWriteValueParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), - ('_0', union_CUstreamMemOpWriteValueParams_st_0), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('alias', ctypes.c_uint64), -] - -class struct_CUstreamMemOpFlushRemoteWritesParams_st(Structure): - pass - -struct_CUstreamMemOpFlushRemoteWritesParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpFlushRemoteWritesParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('flags', ctypes.c_uint32), -] - -class struct_CUstreamMemOpMemoryBarrierParams_st(Structure): - pass - -struct_CUstreamMemOpMemoryBarrierParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpMemoryBarrierParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('flags', ctypes.c_uint32), -] - -union_CUstreamBatchMemOpParams_union._pack_ = 1 # source:False -union_CUstreamBatchMemOpParams_union._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('waitValue', struct_CUstreamMemOpWaitValueParams_st), - ('writeValue', struct_CUstreamMemOpWriteValueParams_st), - ('flushRemoteWrites', struct_CUstreamMemOpFlushRemoteWritesParams_st), - ('memoryBarrier', struct_CUstreamMemOpMemoryBarrierParams_st), - ('pad', ctypes.c_uint64 * 6), -] - -CUstreamBatchMemOpParams_v1 = union_CUstreamBatchMemOpParams_union -CUstreamBatchMemOpParams = union_CUstreamBatchMemOpParams_union -class struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st._fields_ = [ - ('ctx', ctypes.POINTER(struct_CUctx_st)), - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('paramArray', ctypes.POINTER(union_CUstreamBatchMemOpParams_union)), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -CUDA_BATCH_MEM_OP_NODE_PARAMS = struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st - -# values for enumeration 'CUoccupancy_flags_enum' -CUoccupancy_flags_enum__enumvalues = { - 0: 'CU_OCCUPANCY_DEFAULT', - 1: 'CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE', -} -CU_OCCUPANCY_DEFAULT = 0 -CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE = 1 -CUoccupancy_flags_enum = ctypes.c_uint32 # enum -CUoccupancy_flags = CUoccupancy_flags_enum -CUoccupancy_flags__enumvalues = CUoccupancy_flags_enum__enumvalues - -# values for enumeration 'CUstreamUpdateCaptureDependencies_flags_enum' -CUstreamUpdateCaptureDependencies_flags_enum__enumvalues = { - 0: 'CU_STREAM_ADD_CAPTURE_DEPENDENCIES', - 1: 'CU_STREAM_SET_CAPTURE_DEPENDENCIES', -} -CU_STREAM_ADD_CAPTURE_DEPENDENCIES = 0 -CU_STREAM_SET_CAPTURE_DEPENDENCIES = 1 -CUstreamUpdateCaptureDependencies_flags_enum = ctypes.c_uint32 # enum -CUstreamUpdateCaptureDependencies_flags = CUstreamUpdateCaptureDependencies_flags_enum -CUstreamUpdateCaptureDependencies_flags__enumvalues = CUstreamUpdateCaptureDependencies_flags_enum__enumvalues - -# values for enumeration 'CUarray_format_enum' -CUarray_format_enum__enumvalues = { - 1: 'CU_AD_FORMAT_UNSIGNED_INT8', - 2: 'CU_AD_FORMAT_UNSIGNED_INT16', - 3: 'CU_AD_FORMAT_UNSIGNED_INT32', - 8: 'CU_AD_FORMAT_SIGNED_INT8', - 9: 'CU_AD_FORMAT_SIGNED_INT16', - 10: 'CU_AD_FORMAT_SIGNED_INT32', - 16: 'CU_AD_FORMAT_HALF', - 32: 'CU_AD_FORMAT_FLOAT', - 176: 'CU_AD_FORMAT_NV12', - 192: 'CU_AD_FORMAT_UNORM_INT8X1', - 193: 'CU_AD_FORMAT_UNORM_INT8X2', - 194: 'CU_AD_FORMAT_UNORM_INT8X4', - 195: 'CU_AD_FORMAT_UNORM_INT16X1', - 196: 'CU_AD_FORMAT_UNORM_INT16X2', - 197: 'CU_AD_FORMAT_UNORM_INT16X4', - 198: 'CU_AD_FORMAT_SNORM_INT8X1', - 199: 'CU_AD_FORMAT_SNORM_INT8X2', - 200: 'CU_AD_FORMAT_SNORM_INT8X4', - 201: 'CU_AD_FORMAT_SNORM_INT16X1', - 202: 'CU_AD_FORMAT_SNORM_INT16X2', - 203: 'CU_AD_FORMAT_SNORM_INT16X4', - 145: 'CU_AD_FORMAT_BC1_UNORM', - 146: 'CU_AD_FORMAT_BC1_UNORM_SRGB', - 147: 'CU_AD_FORMAT_BC2_UNORM', - 148: 'CU_AD_FORMAT_BC2_UNORM_SRGB', - 149: 'CU_AD_FORMAT_BC3_UNORM', - 150: 'CU_AD_FORMAT_BC3_UNORM_SRGB', - 151: 'CU_AD_FORMAT_BC4_UNORM', - 152: 'CU_AD_FORMAT_BC4_SNORM', - 153: 'CU_AD_FORMAT_BC5_UNORM', - 154: 'CU_AD_FORMAT_BC5_SNORM', - 155: 'CU_AD_FORMAT_BC6H_UF16', - 156: 'CU_AD_FORMAT_BC6H_SF16', - 157: 'CU_AD_FORMAT_BC7_UNORM', - 158: 'CU_AD_FORMAT_BC7_UNORM_SRGB', -} -CU_AD_FORMAT_UNSIGNED_INT8 = 1 -CU_AD_FORMAT_UNSIGNED_INT16 = 2 -CU_AD_FORMAT_UNSIGNED_INT32 = 3 -CU_AD_FORMAT_SIGNED_INT8 = 8 -CU_AD_FORMAT_SIGNED_INT16 = 9 -CU_AD_FORMAT_SIGNED_INT32 = 10 -CU_AD_FORMAT_HALF = 16 -CU_AD_FORMAT_FLOAT = 32 -CU_AD_FORMAT_NV12 = 176 -CU_AD_FORMAT_UNORM_INT8X1 = 192 -CU_AD_FORMAT_UNORM_INT8X2 = 193 -CU_AD_FORMAT_UNORM_INT8X4 = 194 -CU_AD_FORMAT_UNORM_INT16X1 = 195 -CU_AD_FORMAT_UNORM_INT16X2 = 196 -CU_AD_FORMAT_UNORM_INT16X4 = 197 -CU_AD_FORMAT_SNORM_INT8X1 = 198 -CU_AD_FORMAT_SNORM_INT8X2 = 199 -CU_AD_FORMAT_SNORM_INT8X4 = 200 -CU_AD_FORMAT_SNORM_INT16X1 = 201 -CU_AD_FORMAT_SNORM_INT16X2 = 202 -CU_AD_FORMAT_SNORM_INT16X4 = 203 -CU_AD_FORMAT_BC1_UNORM = 145 -CU_AD_FORMAT_BC1_UNORM_SRGB = 146 -CU_AD_FORMAT_BC2_UNORM = 147 -CU_AD_FORMAT_BC2_UNORM_SRGB = 148 -CU_AD_FORMAT_BC3_UNORM = 149 -CU_AD_FORMAT_BC3_UNORM_SRGB = 150 -CU_AD_FORMAT_BC4_UNORM = 151 -CU_AD_FORMAT_BC4_SNORM = 152 -CU_AD_FORMAT_BC5_UNORM = 153 -CU_AD_FORMAT_BC5_SNORM = 154 -CU_AD_FORMAT_BC6H_UF16 = 155 -CU_AD_FORMAT_BC6H_SF16 = 156 -CU_AD_FORMAT_BC7_UNORM = 157 -CU_AD_FORMAT_BC7_UNORM_SRGB = 158 -CUarray_format_enum = ctypes.c_uint32 # enum -CUarray_format = CUarray_format_enum -CUarray_format__enumvalues = CUarray_format_enum__enumvalues - -# values for enumeration 'CUaddress_mode_enum' -CUaddress_mode_enum__enumvalues = { - 0: 'CU_TR_ADDRESS_MODE_WRAP', - 1: 'CU_TR_ADDRESS_MODE_CLAMP', - 2: 'CU_TR_ADDRESS_MODE_MIRROR', - 3: 'CU_TR_ADDRESS_MODE_BORDER', -} -CU_TR_ADDRESS_MODE_WRAP = 0 -CU_TR_ADDRESS_MODE_CLAMP = 1 -CU_TR_ADDRESS_MODE_MIRROR = 2 -CU_TR_ADDRESS_MODE_BORDER = 3 -CUaddress_mode_enum = ctypes.c_uint32 # enum -CUaddress_mode = CUaddress_mode_enum -CUaddress_mode__enumvalues = CUaddress_mode_enum__enumvalues - -# values for enumeration 'CUfilter_mode_enum' -CUfilter_mode_enum__enumvalues = { - 0: 'CU_TR_FILTER_MODE_POINT', - 1: 'CU_TR_FILTER_MODE_LINEAR', -} -CU_TR_FILTER_MODE_POINT = 0 -CU_TR_FILTER_MODE_LINEAR = 1 -CUfilter_mode_enum = ctypes.c_uint32 # enum -CUfilter_mode = CUfilter_mode_enum -CUfilter_mode__enumvalues = CUfilter_mode_enum__enumvalues - -# values for enumeration 'CUdevice_attribute_enum' -CUdevice_attribute_enum__enumvalues = { - 1: 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 2: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X', - 3: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y', - 4: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z', - 5: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X', - 6: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y', - 7: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z', - 8: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK', - 8: 'CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK', - 9: 'CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY', - 10: 'CU_DEVICE_ATTRIBUTE_WARP_SIZE', - 11: 'CU_DEVICE_ATTRIBUTE_MAX_PITCH', - 12: 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK', - 12: 'CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK', - 13: 'CU_DEVICE_ATTRIBUTE_CLOCK_RATE', - 14: 'CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT', - 15: 'CU_DEVICE_ATTRIBUTE_GPU_OVERLAP', - 16: 'CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT', - 17: 'CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT', - 18: 'CU_DEVICE_ATTRIBUTE_INTEGRATED', - 19: 'CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY', - 20: 'CU_DEVICE_ATTRIBUTE_COMPUTE_MODE', - 21: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH', - 22: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH', - 23: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT', - 24: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH', - 25: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT', - 26: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH', - 27: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH', - 28: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT', - 29: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS', - 27: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH', - 28: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT', - 29: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES', - 30: 'CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT', - 31: 'CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS', - 32: 'CU_DEVICE_ATTRIBUTE_ECC_ENABLED', - 33: 'CU_DEVICE_ATTRIBUTE_PCI_BUS_ID', - 34: 'CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID', - 35: 'CU_DEVICE_ATTRIBUTE_TCC_DRIVER', - 36: 'CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE', - 37: 'CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH', - 38: 'CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE', - 39: 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR', - 40: 'CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT', - 41: 'CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING', - 42: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH', - 43: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS', - 44: 'CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER', - 45: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH', - 46: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT', - 47: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE', - 48: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE', - 49: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE', - 50: 'CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID', - 51: 'CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT', - 52: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH', - 53: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH', - 54: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS', - 55: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH', - 56: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH', - 57: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT', - 58: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH', - 59: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT', - 60: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH', - 61: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH', - 62: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS', - 63: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH', - 64: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT', - 65: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS', - 66: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH', - 67: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH', - 68: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS', - 69: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH', - 70: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH', - 71: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT', - 72: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH', - 73: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH', - 74: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT', - 75: 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR', - 76: 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR', - 77: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH', - 78: 'CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED', - 79: 'CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED', - 80: 'CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED', - 81: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR', - 82: 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR', - 83: 'CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY', - 84: 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD', - 85: 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID', - 86: 'CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED', - 87: 'CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO', - 88: 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS', - 89: 'CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS', - 90: 'CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED', - 91: 'CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM', - 92: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1', - 93: 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1', - 94: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1', - 95: 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH', - 96: 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH', - 97: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN', - 98: 'CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES', - 99: 'CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED', - 100: 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES', - 101: 'CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST', - 102: 'CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED', - 102: 'CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED', - 103: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED', - 104: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED', - 105: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED', - 106: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR', - 107: 'CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED', - 108: 'CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE', - 109: 'CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE', - 110: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED', - 111: 'CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK', - 112: 'CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED', - 113: 'CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED', - 114: 'CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED', - 115: 'CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED', - 116: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED', - 117: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS', - 118: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING', - 119: 'CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES', - 120: 'CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH', - 121: 'CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED', - 122: 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS', - 123: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR', - 124: 'CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED', - 125: 'CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED', - 126: 'CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT', - 127: 'CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED', - 129: 'CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS', - 130: 'CU_DEVICE_ATTRIBUTE_MAX', -} -CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 1 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X = 2 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y = 3 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z = 4 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X = 5 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y = 6 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z = 7 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK = 8 -CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK = 8 -CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY = 9 -CU_DEVICE_ATTRIBUTE_WARP_SIZE = 10 -CU_DEVICE_ATTRIBUTE_MAX_PITCH = 11 -CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK = 12 -CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK = 12 -CU_DEVICE_ATTRIBUTE_CLOCK_RATE = 13 -CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT = 14 -CU_DEVICE_ATTRIBUTE_GPU_OVERLAP = 15 -CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT = 16 -CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT = 17 -CU_DEVICE_ATTRIBUTE_INTEGRATED = 18 -CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY = 19 -CU_DEVICE_ATTRIBUTE_COMPUTE_MODE = 20 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH = 21 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH = 22 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT = 23 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH = 24 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT = 25 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH = 26 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH = 27 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT = 28 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS = 29 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH = 27 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT = 28 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES = 29 -CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT = 30 -CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS = 31 -CU_DEVICE_ATTRIBUTE_ECC_ENABLED = 32 -CU_DEVICE_ATTRIBUTE_PCI_BUS_ID = 33 -CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID = 34 -CU_DEVICE_ATTRIBUTE_TCC_DRIVER = 35 -CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE = 36 -CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH = 37 -CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE = 38 -CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR = 39 -CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT = 40 -CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING = 41 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH = 42 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS = 43 -CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER = 44 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH = 45 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT = 46 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE = 47 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE = 48 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE = 49 -CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID = 50 -CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT = 51 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH = 52 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH = 53 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS = 54 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH = 55 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH = 56 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT = 57 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH = 58 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT = 59 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH = 60 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH = 61 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS = 62 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH = 63 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT = 64 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS = 65 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH = 66 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH = 67 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS = 68 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH = 69 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH = 70 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT = 71 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH = 72 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH = 73 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT = 74 -CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR = 75 -CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR = 76 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH = 77 -CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED = 78 -CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED = 79 -CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED = 80 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR = 81 -CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR = 82 -CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY = 83 -CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD = 84 -CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID = 85 -CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED = 86 -CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO = 87 -CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS = 88 -CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS = 89 -CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED = 90 -CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM = 91 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1 = 92 -CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1 = 93 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1 = 94 -CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH = 95 -CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH = 96 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN = 97 -CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES = 98 -CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED = 99 -CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES = 100 -CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST = 101 -CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED = 102 -CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED = 102 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED = 103 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED = 104 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED = 105 -CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR = 106 -CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED = 107 -CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE = 108 -CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE = 109 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED = 110 -CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK = 111 -CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED = 112 -CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED = 113 -CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED = 114 -CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED = 115 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED = 116 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS = 117 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING = 118 -CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES = 119 -CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH = 120 -CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED = 121 -CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS = 122 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR = 123 -CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED = 124 -CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED = 125 -CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT = 126 -CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED = 127 -CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS = 129 -CU_DEVICE_ATTRIBUTE_MAX = 130 -CUdevice_attribute_enum = ctypes.c_uint32 # enum -CUdevice_attribute = CUdevice_attribute_enum -CUdevice_attribute__enumvalues = CUdevice_attribute_enum__enumvalues -class struct_CUdevprop_st(Structure): - pass - -struct_CUdevprop_st._pack_ = 1 # source:False -struct_CUdevprop_st._fields_ = [ - ('maxThreadsPerBlock', ctypes.c_int32), - ('maxThreadsDim', ctypes.c_int32 * 3), - ('maxGridSize', ctypes.c_int32 * 3), - ('sharedMemPerBlock', ctypes.c_int32), - ('totalConstantMemory', ctypes.c_int32), - ('SIMDWidth', ctypes.c_int32), - ('memPitch', ctypes.c_int32), - ('regsPerBlock', ctypes.c_int32), - ('clockRate', ctypes.c_int32), - ('textureAlign', ctypes.c_int32), -] - -CUdevprop_v1 = struct_CUdevprop_st -CUdevprop = struct_CUdevprop_st - -# values for enumeration 'CUpointer_attribute_enum' -CUpointer_attribute_enum__enumvalues = { - 1: 'CU_POINTER_ATTRIBUTE_CONTEXT', - 2: 'CU_POINTER_ATTRIBUTE_MEMORY_TYPE', - 3: 'CU_POINTER_ATTRIBUTE_DEVICE_POINTER', - 4: 'CU_POINTER_ATTRIBUTE_HOST_POINTER', - 5: 'CU_POINTER_ATTRIBUTE_P2P_TOKENS', - 6: 'CU_POINTER_ATTRIBUTE_SYNC_MEMOPS', - 7: 'CU_POINTER_ATTRIBUTE_BUFFER_ID', - 8: 'CU_POINTER_ATTRIBUTE_IS_MANAGED', - 9: 'CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 10: 'CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE', - 11: 'CU_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 12: 'CU_POINTER_ATTRIBUTE_RANGE_SIZE', - 13: 'CU_POINTER_ATTRIBUTE_MAPPED', - 14: 'CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 15: 'CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 16: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 17: 'CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 18: 'CU_POINTER_ATTRIBUTE_MAPPING_SIZE', - 19: 'CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR', - 20: 'CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID', -} -CU_POINTER_ATTRIBUTE_CONTEXT = 1 -CU_POINTER_ATTRIBUTE_MEMORY_TYPE = 2 -CU_POINTER_ATTRIBUTE_DEVICE_POINTER = 3 -CU_POINTER_ATTRIBUTE_HOST_POINTER = 4 -CU_POINTER_ATTRIBUTE_P2P_TOKENS = 5 -CU_POINTER_ATTRIBUTE_SYNC_MEMOPS = 6 -CU_POINTER_ATTRIBUTE_BUFFER_ID = 7 -CU_POINTER_ATTRIBUTE_IS_MANAGED = 8 -CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL = 9 -CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE = 10 -CU_POINTER_ATTRIBUTE_RANGE_START_ADDR = 11 -CU_POINTER_ATTRIBUTE_RANGE_SIZE = 12 -CU_POINTER_ATTRIBUTE_MAPPED = 13 -CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = 14 -CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = 15 -CU_POINTER_ATTRIBUTE_ACCESS_FLAGS = 16 -CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = 17 -CU_POINTER_ATTRIBUTE_MAPPING_SIZE = 18 -CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR = 19 -CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID = 20 -CUpointer_attribute_enum = ctypes.c_uint32 # enum -CUpointer_attribute = CUpointer_attribute_enum -CUpointer_attribute__enumvalues = CUpointer_attribute_enum__enumvalues - -# values for enumeration 'CUfunction_attribute_enum' -CUfunction_attribute_enum__enumvalues = { - 0: 'CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 1: 'CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 2: 'CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 3: 'CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', - 4: 'CU_FUNC_ATTRIBUTE_NUM_REGS', - 5: 'CU_FUNC_ATTRIBUTE_PTX_VERSION', - 6: 'CU_FUNC_ATTRIBUTE_BINARY_VERSION', - 7: 'CU_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 8: 'CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 9: 'CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 10: 'CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET', - 11: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH', - 12: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT', - 13: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH', - 14: 'CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED', - 15: 'CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 16: 'CU_FUNC_ATTRIBUTE_MAX', -} -CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 0 -CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = 1 -CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = 2 -CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = 3 -CU_FUNC_ATTRIBUTE_NUM_REGS = 4 -CU_FUNC_ATTRIBUTE_PTX_VERSION = 5 -CU_FUNC_ATTRIBUTE_BINARY_VERSION = 6 -CU_FUNC_ATTRIBUTE_CACHE_MODE_CA = 7 -CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = 8 -CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = 9 -CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET = 10 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH = 11 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT = 12 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH = 13 -CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED = 14 -CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = 15 -CU_FUNC_ATTRIBUTE_MAX = 16 -CUfunction_attribute_enum = ctypes.c_uint32 # enum -CUfunction_attribute = CUfunction_attribute_enum -CUfunction_attribute__enumvalues = CUfunction_attribute_enum__enumvalues - -# values for enumeration 'CUfunc_cache_enum' -CUfunc_cache_enum__enumvalues = { - 0: 'CU_FUNC_CACHE_PREFER_NONE', - 1: 'CU_FUNC_CACHE_PREFER_SHARED', - 2: 'CU_FUNC_CACHE_PREFER_L1', - 3: 'CU_FUNC_CACHE_PREFER_EQUAL', -} -CU_FUNC_CACHE_PREFER_NONE = 0 -CU_FUNC_CACHE_PREFER_SHARED = 1 -CU_FUNC_CACHE_PREFER_L1 = 2 -CU_FUNC_CACHE_PREFER_EQUAL = 3 -CUfunc_cache_enum = ctypes.c_uint32 # enum -CUfunc_cache = CUfunc_cache_enum -CUfunc_cache__enumvalues = CUfunc_cache_enum__enumvalues - -# values for enumeration 'CUsharedconfig_enum' -CUsharedconfig_enum__enumvalues = { - 0: 'CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE', - 1: 'CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE', - 2: 'CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE', -} -CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE = 0 -CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE = 1 -CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE = 2 -CUsharedconfig_enum = ctypes.c_uint32 # enum -CUsharedconfig = CUsharedconfig_enum -CUsharedconfig__enumvalues = CUsharedconfig_enum__enumvalues - -# values for enumeration 'CUshared_carveout_enum' -CUshared_carveout_enum__enumvalues = { - -1: 'CU_SHAREDMEM_CARVEOUT_DEFAULT', - 100: 'CU_SHAREDMEM_CARVEOUT_MAX_SHARED', - 0: 'CU_SHAREDMEM_CARVEOUT_MAX_L1', -} -CU_SHAREDMEM_CARVEOUT_DEFAULT = -1 -CU_SHAREDMEM_CARVEOUT_MAX_SHARED = 100 -CU_SHAREDMEM_CARVEOUT_MAX_L1 = 0 -CUshared_carveout_enum = ctypes.c_int32 # enum -CUshared_carveout = CUshared_carveout_enum -CUshared_carveout__enumvalues = CUshared_carveout_enum__enumvalues - -# values for enumeration 'CUmemorytype_enum' -CUmemorytype_enum__enumvalues = { - 1: 'CU_MEMORYTYPE_HOST', - 2: 'CU_MEMORYTYPE_DEVICE', - 3: 'CU_MEMORYTYPE_ARRAY', - 4: 'CU_MEMORYTYPE_UNIFIED', -} -CU_MEMORYTYPE_HOST = 1 -CU_MEMORYTYPE_DEVICE = 2 -CU_MEMORYTYPE_ARRAY = 3 -CU_MEMORYTYPE_UNIFIED = 4 -CUmemorytype_enum = ctypes.c_uint32 # enum -CUmemorytype = CUmemorytype_enum -CUmemorytype__enumvalues = CUmemorytype_enum__enumvalues - -# values for enumeration 'CUcomputemode_enum' -CUcomputemode_enum__enumvalues = { - 0: 'CU_COMPUTEMODE_DEFAULT', - 2: 'CU_COMPUTEMODE_PROHIBITED', - 3: 'CU_COMPUTEMODE_EXCLUSIVE_PROCESS', -} -CU_COMPUTEMODE_DEFAULT = 0 -CU_COMPUTEMODE_PROHIBITED = 2 -CU_COMPUTEMODE_EXCLUSIVE_PROCESS = 3 -CUcomputemode_enum = ctypes.c_uint32 # enum -CUcomputemode = CUcomputemode_enum -CUcomputemode__enumvalues = CUcomputemode_enum__enumvalues - -# values for enumeration 'CUmem_advise_enum' -CUmem_advise_enum__enumvalues = { - 1: 'CU_MEM_ADVISE_SET_READ_MOSTLY', - 2: 'CU_MEM_ADVISE_UNSET_READ_MOSTLY', - 3: 'CU_MEM_ADVISE_SET_PREFERRED_LOCATION', - 4: 'CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION', - 5: 'CU_MEM_ADVISE_SET_ACCESSED_BY', - 6: 'CU_MEM_ADVISE_UNSET_ACCESSED_BY', -} -CU_MEM_ADVISE_SET_READ_MOSTLY = 1 -CU_MEM_ADVISE_UNSET_READ_MOSTLY = 2 -CU_MEM_ADVISE_SET_PREFERRED_LOCATION = 3 -CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION = 4 -CU_MEM_ADVISE_SET_ACCESSED_BY = 5 -CU_MEM_ADVISE_UNSET_ACCESSED_BY = 6 -CUmem_advise_enum = ctypes.c_uint32 # enum -CUmem_advise = CUmem_advise_enum -CUmem_advise__enumvalues = CUmem_advise_enum__enumvalues - -# values for enumeration 'CUmem_range_attribute_enum' -CUmem_range_attribute_enum__enumvalues = { - 1: 'CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY', - 2: 'CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION', - 3: 'CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY', - 4: 'CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION', -} -CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY = 1 -CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION = 2 -CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY = 3 -CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION = 4 -CUmem_range_attribute_enum = ctypes.c_uint32 # enum -CUmem_range_attribute = CUmem_range_attribute_enum -CUmem_range_attribute__enumvalues = CUmem_range_attribute_enum__enumvalues - -# values for enumeration 'CUjit_option_enum' -CUjit_option_enum__enumvalues = { - 0: 'CU_JIT_MAX_REGISTERS', - 1: 'CU_JIT_THREADS_PER_BLOCK', - 2: 'CU_JIT_WALL_TIME', - 3: 'CU_JIT_INFO_LOG_BUFFER', - 4: 'CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES', - 5: 'CU_JIT_ERROR_LOG_BUFFER', - 6: 'CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 7: 'CU_JIT_OPTIMIZATION_LEVEL', - 8: 'CU_JIT_TARGET_FROM_CUCONTEXT', - 9: 'CU_JIT_TARGET', - 10: 'CU_JIT_FALLBACK_STRATEGY', - 11: 'CU_JIT_GENERATE_DEBUG_INFO', - 12: 'CU_JIT_LOG_VERBOSE', - 13: 'CU_JIT_GENERATE_LINE_INFO', - 14: 'CU_JIT_CACHE_MODE', - 15: 'CU_JIT_NEW_SM3X_OPT', - 16: 'CU_JIT_FAST_COMPILE', - 17: 'CU_JIT_GLOBAL_SYMBOL_NAMES', - 18: 'CU_JIT_GLOBAL_SYMBOL_ADDRESSES', - 19: 'CU_JIT_GLOBAL_SYMBOL_COUNT', - 20: 'CU_JIT_LTO', - 21: 'CU_JIT_FTZ', - 22: 'CU_JIT_PREC_DIV', - 23: 'CU_JIT_PREC_SQRT', - 24: 'CU_JIT_FMA', - 25: 'CU_JIT_REFERENCED_KERNEL_NAMES', - 26: 'CU_JIT_REFERENCED_KERNEL_COUNT', - 27: 'CU_JIT_REFERENCED_VARIABLE_NAMES', - 28: 'CU_JIT_REFERENCED_VARIABLE_COUNT', - 29: 'CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES', - 30: 'CU_JIT_POSITION_INDEPENDENT_CODE', - 31: 'CU_JIT_NUM_OPTIONS', -} -CU_JIT_MAX_REGISTERS = 0 -CU_JIT_THREADS_PER_BLOCK = 1 -CU_JIT_WALL_TIME = 2 -CU_JIT_INFO_LOG_BUFFER = 3 -CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES = 4 -CU_JIT_ERROR_LOG_BUFFER = 5 -CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = 6 -CU_JIT_OPTIMIZATION_LEVEL = 7 -CU_JIT_TARGET_FROM_CUCONTEXT = 8 -CU_JIT_TARGET = 9 -CU_JIT_FALLBACK_STRATEGY = 10 -CU_JIT_GENERATE_DEBUG_INFO = 11 -CU_JIT_LOG_VERBOSE = 12 -CU_JIT_GENERATE_LINE_INFO = 13 -CU_JIT_CACHE_MODE = 14 -CU_JIT_NEW_SM3X_OPT = 15 -CU_JIT_FAST_COMPILE = 16 -CU_JIT_GLOBAL_SYMBOL_NAMES = 17 -CU_JIT_GLOBAL_SYMBOL_ADDRESSES = 18 -CU_JIT_GLOBAL_SYMBOL_COUNT = 19 -CU_JIT_LTO = 20 -CU_JIT_FTZ = 21 -CU_JIT_PREC_DIV = 22 -CU_JIT_PREC_SQRT = 23 -CU_JIT_FMA = 24 -CU_JIT_REFERENCED_KERNEL_NAMES = 25 -CU_JIT_REFERENCED_KERNEL_COUNT = 26 -CU_JIT_REFERENCED_VARIABLE_NAMES = 27 -CU_JIT_REFERENCED_VARIABLE_COUNT = 28 -CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES = 29 -CU_JIT_POSITION_INDEPENDENT_CODE = 30 -CU_JIT_NUM_OPTIONS = 31 -CUjit_option_enum = ctypes.c_uint32 # enum -CUjit_option = CUjit_option_enum -CUjit_option__enumvalues = CUjit_option_enum__enumvalues - -# values for enumeration 'CUjit_target_enum' -CUjit_target_enum__enumvalues = { - 30: 'CU_TARGET_COMPUTE_30', - 32: 'CU_TARGET_COMPUTE_32', - 35: 'CU_TARGET_COMPUTE_35', - 37: 'CU_TARGET_COMPUTE_37', - 50: 'CU_TARGET_COMPUTE_50', - 52: 'CU_TARGET_COMPUTE_52', - 53: 'CU_TARGET_COMPUTE_53', - 60: 'CU_TARGET_COMPUTE_60', - 61: 'CU_TARGET_COMPUTE_61', - 62: 'CU_TARGET_COMPUTE_62', - 70: 'CU_TARGET_COMPUTE_70', - 72: 'CU_TARGET_COMPUTE_72', - 75: 'CU_TARGET_COMPUTE_75', - 80: 'CU_TARGET_COMPUTE_80', - 86: 'CU_TARGET_COMPUTE_86', - 87: 'CU_TARGET_COMPUTE_87', - 89: 'CU_TARGET_COMPUTE_89', - 90: 'CU_TARGET_COMPUTE_90', - 65626: 'CU_TARGET_COMPUTE_90A', -} -CU_TARGET_COMPUTE_30 = 30 -CU_TARGET_COMPUTE_32 = 32 -CU_TARGET_COMPUTE_35 = 35 -CU_TARGET_COMPUTE_37 = 37 -CU_TARGET_COMPUTE_50 = 50 -CU_TARGET_COMPUTE_52 = 52 -CU_TARGET_COMPUTE_53 = 53 -CU_TARGET_COMPUTE_60 = 60 -CU_TARGET_COMPUTE_61 = 61 -CU_TARGET_COMPUTE_62 = 62 -CU_TARGET_COMPUTE_70 = 70 -CU_TARGET_COMPUTE_72 = 72 -CU_TARGET_COMPUTE_75 = 75 -CU_TARGET_COMPUTE_80 = 80 -CU_TARGET_COMPUTE_86 = 86 -CU_TARGET_COMPUTE_87 = 87 -CU_TARGET_COMPUTE_89 = 89 -CU_TARGET_COMPUTE_90 = 90 -CU_TARGET_COMPUTE_90A = 65626 -CUjit_target_enum = ctypes.c_uint32 # enum -CUjit_target = CUjit_target_enum -CUjit_target__enumvalues = CUjit_target_enum__enumvalues - -# values for enumeration 'CUjit_fallback_enum' -CUjit_fallback_enum__enumvalues = { - 0: 'CU_PREFER_PTX', - 1: 'CU_PREFER_BINARY', -} -CU_PREFER_PTX = 0 -CU_PREFER_BINARY = 1 -CUjit_fallback_enum = ctypes.c_uint32 # enum -CUjit_fallback = CUjit_fallback_enum -CUjit_fallback__enumvalues = CUjit_fallback_enum__enumvalues - -# values for enumeration 'CUjit_cacheMode_enum' -CUjit_cacheMode_enum__enumvalues = { - 0: 'CU_JIT_CACHE_OPTION_NONE', - 1: 'CU_JIT_CACHE_OPTION_CG', - 2: 'CU_JIT_CACHE_OPTION_CA', -} -CU_JIT_CACHE_OPTION_NONE = 0 -CU_JIT_CACHE_OPTION_CG = 1 -CU_JIT_CACHE_OPTION_CA = 2 -CUjit_cacheMode_enum = ctypes.c_uint32 # enum -CUjit_cacheMode = CUjit_cacheMode_enum -CUjit_cacheMode__enumvalues = CUjit_cacheMode_enum__enumvalues - -# values for enumeration 'CUjitInputType_enum' -CUjitInputType_enum__enumvalues = { - 0: 'CU_JIT_INPUT_CUBIN', - 1: 'CU_JIT_INPUT_PTX', - 2: 'CU_JIT_INPUT_FATBINARY', - 3: 'CU_JIT_INPUT_OBJECT', - 4: 'CU_JIT_INPUT_LIBRARY', - 5: 'CU_JIT_INPUT_NVVM', - 6: 'CU_JIT_NUM_INPUT_TYPES', -} -CU_JIT_INPUT_CUBIN = 0 -CU_JIT_INPUT_PTX = 1 -CU_JIT_INPUT_FATBINARY = 2 -CU_JIT_INPUT_OBJECT = 3 -CU_JIT_INPUT_LIBRARY = 4 -CU_JIT_INPUT_NVVM = 5 -CU_JIT_NUM_INPUT_TYPES = 6 -CUjitInputType_enum = ctypes.c_uint32 # enum -CUjitInputType = CUjitInputType_enum -CUjitInputType__enumvalues = CUjitInputType_enum__enumvalues -class struct_CUlinkState_st(Structure): - pass - -CUlinkState = ctypes.POINTER(struct_CUlinkState_st) - -# values for enumeration 'CUgraphicsRegisterFlags_enum' -CUgraphicsRegisterFlags_enum__enumvalues = { - 0: 'CU_GRAPHICS_REGISTER_FLAGS_NONE', - 1: 'CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY', - 2: 'CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD', - 4: 'CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST', - 8: 'CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER', -} -CU_GRAPHICS_REGISTER_FLAGS_NONE = 0 -CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY = 1 -CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD = 2 -CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST = 4 -CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER = 8 -CUgraphicsRegisterFlags_enum = ctypes.c_uint32 # enum -CUgraphicsRegisterFlags = CUgraphicsRegisterFlags_enum -CUgraphicsRegisterFlags__enumvalues = CUgraphicsRegisterFlags_enum__enumvalues - -# values for enumeration 'CUgraphicsMapResourceFlags_enum' -CUgraphicsMapResourceFlags_enum__enumvalues = { - 0: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE', - 1: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY', - 2: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD', -} -CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE = 0 -CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY = 1 -CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD = 2 -CUgraphicsMapResourceFlags_enum = ctypes.c_uint32 # enum -CUgraphicsMapResourceFlags = CUgraphicsMapResourceFlags_enum -CUgraphicsMapResourceFlags__enumvalues = CUgraphicsMapResourceFlags_enum__enumvalues - -# values for enumeration 'CUarray_cubemap_face_enum' -CUarray_cubemap_face_enum__enumvalues = { - 0: 'CU_CUBEMAP_FACE_POSITIVE_X', - 1: 'CU_CUBEMAP_FACE_NEGATIVE_X', - 2: 'CU_CUBEMAP_FACE_POSITIVE_Y', - 3: 'CU_CUBEMAP_FACE_NEGATIVE_Y', - 4: 'CU_CUBEMAP_FACE_POSITIVE_Z', - 5: 'CU_CUBEMAP_FACE_NEGATIVE_Z', -} -CU_CUBEMAP_FACE_POSITIVE_X = 0 -CU_CUBEMAP_FACE_NEGATIVE_X = 1 -CU_CUBEMAP_FACE_POSITIVE_Y = 2 -CU_CUBEMAP_FACE_NEGATIVE_Y = 3 -CU_CUBEMAP_FACE_POSITIVE_Z = 4 -CU_CUBEMAP_FACE_NEGATIVE_Z = 5 -CUarray_cubemap_face_enum = ctypes.c_uint32 # enum -CUarray_cubemap_face = CUarray_cubemap_face_enum -CUarray_cubemap_face__enumvalues = CUarray_cubemap_face_enum__enumvalues - -# values for enumeration 'CUlimit_enum' -CUlimit_enum__enumvalues = { - 0: 'CU_LIMIT_STACK_SIZE', - 1: 'CU_LIMIT_PRINTF_FIFO_SIZE', - 2: 'CU_LIMIT_MALLOC_HEAP_SIZE', - 3: 'CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH', - 4: 'CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT', - 5: 'CU_LIMIT_MAX_L2_FETCH_GRANULARITY', - 6: 'CU_LIMIT_PERSISTING_L2_CACHE_SIZE', - 7: 'CU_LIMIT_MAX', -} -CU_LIMIT_STACK_SIZE = 0 -CU_LIMIT_PRINTF_FIFO_SIZE = 1 -CU_LIMIT_MALLOC_HEAP_SIZE = 2 -CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH = 3 -CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT = 4 -CU_LIMIT_MAX_L2_FETCH_GRANULARITY = 5 -CU_LIMIT_PERSISTING_L2_CACHE_SIZE = 6 -CU_LIMIT_MAX = 7 -CUlimit_enum = ctypes.c_uint32 # enum -CUlimit = CUlimit_enum -CUlimit__enumvalues = CUlimit_enum__enumvalues - -# values for enumeration 'CUresourcetype_enum' -CUresourcetype_enum__enumvalues = { - 0: 'CU_RESOURCE_TYPE_ARRAY', - 1: 'CU_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 2: 'CU_RESOURCE_TYPE_LINEAR', - 3: 'CU_RESOURCE_TYPE_PITCH2D', -} -CU_RESOURCE_TYPE_ARRAY = 0 -CU_RESOURCE_TYPE_MIPMAPPED_ARRAY = 1 -CU_RESOURCE_TYPE_LINEAR = 2 -CU_RESOURCE_TYPE_PITCH2D = 3 -CUresourcetype_enum = ctypes.c_uint32 # enum -CUresourcetype = CUresourcetype_enum -CUresourcetype__enumvalues = CUresourcetype_enum__enumvalues -CUhostFn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) - -# values for enumeration 'CUaccessProperty_enum' -CUaccessProperty_enum__enumvalues = { - 0: 'CU_ACCESS_PROPERTY_NORMAL', - 1: 'CU_ACCESS_PROPERTY_STREAMING', - 2: 'CU_ACCESS_PROPERTY_PERSISTING', -} -CU_ACCESS_PROPERTY_NORMAL = 0 -CU_ACCESS_PROPERTY_STREAMING = 1 -CU_ACCESS_PROPERTY_PERSISTING = 2 -CUaccessProperty_enum = ctypes.c_uint32 # enum -CUaccessProperty = CUaccessProperty_enum -CUaccessProperty__enumvalues = CUaccessProperty_enum__enumvalues -class struct_CUaccessPolicyWindow_st(Structure): - pass - -struct_CUaccessPolicyWindow_st._pack_ = 1 # source:False -struct_CUaccessPolicyWindow_st._fields_ = [ - ('base_ptr', ctypes.POINTER(None)), - ('num_bytes', ctypes.c_uint64), - ('hitRatio', ctypes.c_float), - ('hitProp', CUaccessProperty), - ('missProp', CUaccessProperty), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUaccessPolicyWindow_v1 = struct_CUaccessPolicyWindow_st -CUaccessPolicyWindow = struct_CUaccessPolicyWindow_st -class struct_CUDA_KERNEL_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_KERNEL_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_KERNEL_NODE_PARAMS_st._fields_ = [ - ('func', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), -] - -CUDA_KERNEL_NODE_PARAMS_v1 = struct_CUDA_KERNEL_NODE_PARAMS_st -class struct_CUDA_KERNEL_NODE_PARAMS_v2_st(Structure): - pass - -struct_CUDA_KERNEL_NODE_PARAMS_v2_st._pack_ = 1 # source:False -struct_CUDA_KERNEL_NODE_PARAMS_v2_st._fields_ = [ - ('func', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), - ('kern', ctypes.POINTER(struct_CUkern_st)), - ('ctx', ctypes.POINTER(struct_CUctx_st)), -] - -CUDA_KERNEL_NODE_PARAMS_v2 = struct_CUDA_KERNEL_NODE_PARAMS_v2_st -CUDA_KERNEL_NODE_PARAMS = struct_CUDA_KERNEL_NODE_PARAMS_v2_st -class struct_CUDA_MEMSET_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_MEMSET_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_MEMSET_NODE_PARAMS_st._fields_ = [ - ('dst', ctypes.c_uint64), - ('pitch', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('elementSize', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), -] - -CUDA_MEMSET_NODE_PARAMS_v1 = struct_CUDA_MEMSET_NODE_PARAMS_st -CUDA_MEMSET_NODE_PARAMS = struct_CUDA_MEMSET_NODE_PARAMS_st -class struct_CUDA_HOST_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_HOST_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_HOST_NODE_PARAMS_st._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userData', ctypes.POINTER(None)), -] - -CUDA_HOST_NODE_PARAMS_v1 = struct_CUDA_HOST_NODE_PARAMS_st -CUDA_HOST_NODE_PARAMS = struct_CUDA_HOST_NODE_PARAMS_st - -# values for enumeration 'CUgraphNodeType_enum' -CUgraphNodeType_enum__enumvalues = { - 0: 'CU_GRAPH_NODE_TYPE_KERNEL', - 1: 'CU_GRAPH_NODE_TYPE_MEMCPY', - 2: 'CU_GRAPH_NODE_TYPE_MEMSET', - 3: 'CU_GRAPH_NODE_TYPE_HOST', - 4: 'CU_GRAPH_NODE_TYPE_GRAPH', - 5: 'CU_GRAPH_NODE_TYPE_EMPTY', - 6: 'CU_GRAPH_NODE_TYPE_WAIT_EVENT', - 7: 'CU_GRAPH_NODE_TYPE_EVENT_RECORD', - 8: 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL', - 9: 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT', - 10: 'CU_GRAPH_NODE_TYPE_MEM_ALLOC', - 11: 'CU_GRAPH_NODE_TYPE_MEM_FREE', - 12: 'CU_GRAPH_NODE_TYPE_BATCH_MEM_OP', -} -CU_GRAPH_NODE_TYPE_KERNEL = 0 -CU_GRAPH_NODE_TYPE_MEMCPY = 1 -CU_GRAPH_NODE_TYPE_MEMSET = 2 -CU_GRAPH_NODE_TYPE_HOST = 3 -CU_GRAPH_NODE_TYPE_GRAPH = 4 -CU_GRAPH_NODE_TYPE_EMPTY = 5 -CU_GRAPH_NODE_TYPE_WAIT_EVENT = 6 -CU_GRAPH_NODE_TYPE_EVENT_RECORD = 7 -CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL = 8 -CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT = 9 -CU_GRAPH_NODE_TYPE_MEM_ALLOC = 10 -CU_GRAPH_NODE_TYPE_MEM_FREE = 11 -CU_GRAPH_NODE_TYPE_BATCH_MEM_OP = 12 -CUgraphNodeType_enum = ctypes.c_uint32 # enum -CUgraphNodeType = CUgraphNodeType_enum -CUgraphNodeType__enumvalues = CUgraphNodeType_enum__enumvalues - -# values for enumeration 'CUgraphInstantiateResult_enum' -CUgraphInstantiateResult_enum__enumvalues = { - 0: 'CUDA_GRAPH_INSTANTIATE_SUCCESS', - 1: 'CUDA_GRAPH_INSTANTIATE_ERROR', - 2: 'CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE', - 3: 'CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED', - 4: 'CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED', -} -CUDA_GRAPH_INSTANTIATE_SUCCESS = 0 -CUDA_GRAPH_INSTANTIATE_ERROR = 1 -CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE = 2 -CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED = 3 -CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED = 4 -CUgraphInstantiateResult_enum = ctypes.c_uint32 # enum -CUgraphInstantiateResult = CUgraphInstantiateResult_enum -CUgraphInstantiateResult__enumvalues = CUgraphInstantiateResult_enum__enumvalues -class struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st(Structure): - pass - -struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st._fields_ = [ - ('flags', ctypes.c_uint64), - ('hUploadStream', ctypes.POINTER(struct_CUstream_st)), - ('hErrNode_out', ctypes.POINTER(struct_CUgraphNode_st)), - ('result_out', CUgraphInstantiateResult), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_GRAPH_INSTANTIATE_PARAMS = struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st - -# values for enumeration 'CUsynchronizationPolicy_enum' -CUsynchronizationPolicy_enum__enumvalues = { - 1: 'CU_SYNC_POLICY_AUTO', - 2: 'CU_SYNC_POLICY_SPIN', - 3: 'CU_SYNC_POLICY_YIELD', - 4: 'CU_SYNC_POLICY_BLOCKING_SYNC', -} -CU_SYNC_POLICY_AUTO = 1 -CU_SYNC_POLICY_SPIN = 2 -CU_SYNC_POLICY_YIELD = 3 -CU_SYNC_POLICY_BLOCKING_SYNC = 4 -CUsynchronizationPolicy_enum = ctypes.c_uint32 # enum -CUsynchronizationPolicy = CUsynchronizationPolicy_enum -CUsynchronizationPolicy__enumvalues = CUsynchronizationPolicy_enum__enumvalues - -# values for enumeration 'CUclusterSchedulingPolicy_enum' -CUclusterSchedulingPolicy_enum__enumvalues = { - 0: 'CU_CLUSTER_SCHEDULING_POLICY_DEFAULT', - 1: 'CU_CLUSTER_SCHEDULING_POLICY_SPREAD', - 2: 'CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING', -} -CU_CLUSTER_SCHEDULING_POLICY_DEFAULT = 0 -CU_CLUSTER_SCHEDULING_POLICY_SPREAD = 1 -CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING = 2 -CUclusterSchedulingPolicy_enum = ctypes.c_uint32 # enum -CUclusterSchedulingPolicy = CUclusterSchedulingPolicy_enum -CUclusterSchedulingPolicy__enumvalues = CUclusterSchedulingPolicy_enum__enumvalues - -# values for enumeration 'CUlaunchMemSyncDomain_enum' -CUlaunchMemSyncDomain_enum__enumvalues = { - 0: 'CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT', - 1: 'CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE', -} -CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT = 0 -CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE = 1 -CUlaunchMemSyncDomain_enum = ctypes.c_uint32 # enum -CUlaunchMemSyncDomain = CUlaunchMemSyncDomain_enum -CUlaunchMemSyncDomain__enumvalues = CUlaunchMemSyncDomain_enum__enumvalues -class struct_CUlaunchMemSyncDomainMap_st(Structure): - pass - -struct_CUlaunchMemSyncDomainMap_st._pack_ = 1 # source:False -struct_CUlaunchMemSyncDomainMap_st._fields_ = [ - ('default_', ctypes.c_ubyte), - ('remote', ctypes.c_ubyte), -] - -CUlaunchMemSyncDomainMap = struct_CUlaunchMemSyncDomainMap_st - -# values for enumeration 'CUlaunchAttributeID_enum' -CUlaunchAttributeID_enum__enumvalues = { - 0: 'CU_LAUNCH_ATTRIBUTE_IGNORE', - 1: 'CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW', - 2: 'CU_LAUNCH_ATTRIBUTE_COOPERATIVE', - 3: 'CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY', - 4: 'CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION', - 5: 'CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 6: 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION', - 7: 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT', - 8: 'CU_LAUNCH_ATTRIBUTE_PRIORITY', - 9: 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP', - 10: 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN', -} -CU_LAUNCH_ATTRIBUTE_IGNORE = 0 -CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW = 1 -CU_LAUNCH_ATTRIBUTE_COOPERATIVE = 2 -CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY = 3 -CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION = 4 -CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = 5 -CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION = 6 -CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT = 7 -CU_LAUNCH_ATTRIBUTE_PRIORITY = 8 -CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP = 9 -CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN = 10 -CUlaunchAttributeID_enum = ctypes.c_uint32 # enum -CUlaunchAttributeID = CUlaunchAttributeID_enum -CUlaunchAttributeID__enumvalues = CUlaunchAttributeID_enum__enumvalues -class union_CUlaunchAttributeValue_union(Union): - pass - -class struct_CUlaunchAttributeValue_union_clusterDim(Structure): - pass - -struct_CUlaunchAttributeValue_union_clusterDim._pack_ = 1 # source:False -struct_CUlaunchAttributeValue_union_clusterDim._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -class struct_CUlaunchAttributeValue_union_programmaticEvent(Structure): - pass - -struct_CUlaunchAttributeValue_union_programmaticEvent._pack_ = 1 # source:False -struct_CUlaunchAttributeValue_union_programmaticEvent._fields_ = [ - ('event', ctypes.POINTER(struct_CUevent_st)), - ('flags', ctypes.c_int32), - ('triggerAtBlockStart', ctypes.c_int32), -] - -union_CUlaunchAttributeValue_union._pack_ = 1 # source:False -union_CUlaunchAttributeValue_union._fields_ = [ - ('pad', ctypes.c_char * 64), - ('accessPolicyWindow', CUaccessPolicyWindow), - ('cooperative', ctypes.c_int32), - ('syncPolicy', CUsynchronizationPolicy), - ('clusterDim', struct_CUlaunchAttributeValue_union_clusterDim), - ('clusterSchedulingPolicyPreference', CUclusterSchedulingPolicy), - ('programmaticStreamSerializationAllowed', ctypes.c_int32), - ('programmaticEvent', struct_CUlaunchAttributeValue_union_programmaticEvent), - ('priority', ctypes.c_int32), - ('memSyncDomainMap', CUlaunchMemSyncDomainMap), - ('memSyncDomain', CUlaunchMemSyncDomain), - ('PADDING_0', ctypes.c_ubyte * 60), -] - -CUlaunchAttributeValue = union_CUlaunchAttributeValue_union -class struct_CUlaunchAttribute_st(Structure): - pass - -struct_CUlaunchAttribute_st._pack_ = 1 # source:False -struct_CUlaunchAttribute_st._fields_ = [ - ('id', CUlaunchAttributeID), - ('pad', ctypes.c_char * 4), - ('value', CUlaunchAttributeValue), -] - -CUlaunchAttribute = struct_CUlaunchAttribute_st -class struct_CUlaunchConfig_st(Structure): - pass - -struct_CUlaunchConfig_st._pack_ = 1 # source:False -struct_CUlaunchConfig_st._fields_ = [ - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_CUstream_st)), - ('attrs', ctypes.POINTER(struct_CUlaunchAttribute_st)), - ('numAttrs', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -CUlaunchConfig = struct_CUlaunchConfig_st -CUkernelNodeAttrID = CUlaunchAttributeID_enum -CUkernelNodeAttrID__enumvalues = CUlaunchAttributeID_enum__enumvalues -CUkernelNodeAttrValue_v1 = union_CUlaunchAttributeValue_union -CUkernelNodeAttrValue = union_CUlaunchAttributeValue_union - -# values for enumeration 'CUstreamCaptureStatus_enum' -CUstreamCaptureStatus_enum__enumvalues = { - 0: 'CU_STREAM_CAPTURE_STATUS_NONE', - 1: 'CU_STREAM_CAPTURE_STATUS_ACTIVE', - 2: 'CU_STREAM_CAPTURE_STATUS_INVALIDATED', -} -CU_STREAM_CAPTURE_STATUS_NONE = 0 -CU_STREAM_CAPTURE_STATUS_ACTIVE = 1 -CU_STREAM_CAPTURE_STATUS_INVALIDATED = 2 -CUstreamCaptureStatus_enum = ctypes.c_uint32 # enum -CUstreamCaptureStatus = CUstreamCaptureStatus_enum -CUstreamCaptureStatus__enumvalues = CUstreamCaptureStatus_enum__enumvalues - -# values for enumeration 'CUstreamCaptureMode_enum' -CUstreamCaptureMode_enum__enumvalues = { - 0: 'CU_STREAM_CAPTURE_MODE_GLOBAL', - 1: 'CU_STREAM_CAPTURE_MODE_THREAD_LOCAL', - 2: 'CU_STREAM_CAPTURE_MODE_RELAXED', -} -CU_STREAM_CAPTURE_MODE_GLOBAL = 0 -CU_STREAM_CAPTURE_MODE_THREAD_LOCAL = 1 -CU_STREAM_CAPTURE_MODE_RELAXED = 2 -CUstreamCaptureMode_enum = ctypes.c_uint32 # enum -CUstreamCaptureMode = CUstreamCaptureMode_enum -CUstreamCaptureMode__enumvalues = CUstreamCaptureMode_enum__enumvalues -CUstreamAttrID = CUlaunchAttributeID_enum -CUstreamAttrID__enumvalues = CUlaunchAttributeID_enum__enumvalues -CUstreamAttrValue_v1 = union_CUlaunchAttributeValue_union -CUstreamAttrValue = union_CUlaunchAttributeValue_union - -# values for enumeration 'CUdriverProcAddress_flags_enum' -CUdriverProcAddress_flags_enum__enumvalues = { - 0: 'CU_GET_PROC_ADDRESS_DEFAULT', - 1: 'CU_GET_PROC_ADDRESS_LEGACY_STREAM', - 2: 'CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM', -} -CU_GET_PROC_ADDRESS_DEFAULT = 0 -CU_GET_PROC_ADDRESS_LEGACY_STREAM = 1 -CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM = 2 -CUdriverProcAddress_flags_enum = ctypes.c_uint32 # enum -CUdriverProcAddress_flags = CUdriverProcAddress_flags_enum -CUdriverProcAddress_flags__enumvalues = CUdriverProcAddress_flags_enum__enumvalues - -# values for enumeration 'CUdriverProcAddressQueryResult_enum' -CUdriverProcAddressQueryResult_enum__enumvalues = { - 0: 'CU_GET_PROC_ADDRESS_SUCCESS', - 1: 'CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', - 2: 'CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', -} -CU_GET_PROC_ADDRESS_SUCCESS = 0 -CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND = 1 -CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT = 2 -CUdriverProcAddressQueryResult_enum = ctypes.c_uint32 # enum -CUdriverProcAddressQueryResult = CUdriverProcAddressQueryResult_enum -CUdriverProcAddressQueryResult__enumvalues = CUdriverProcAddressQueryResult_enum__enumvalues - -# values for enumeration 'CUexecAffinityType_enum' -CUexecAffinityType_enum__enumvalues = { - 0: 'CU_EXEC_AFFINITY_TYPE_SM_COUNT', - 1: 'CU_EXEC_AFFINITY_TYPE_MAX', -} -CU_EXEC_AFFINITY_TYPE_SM_COUNT = 0 -CU_EXEC_AFFINITY_TYPE_MAX = 1 -CUexecAffinityType_enum = ctypes.c_uint32 # enum -CUexecAffinityType = CUexecAffinityType_enum -CUexecAffinityType__enumvalues = CUexecAffinityType_enum__enumvalues -class struct_CUexecAffinitySmCount_st(Structure): - pass - -struct_CUexecAffinitySmCount_st._pack_ = 1 # source:False -struct_CUexecAffinitySmCount_st._fields_ = [ - ('val', ctypes.c_uint32), -] - -CUexecAffinitySmCount_v1 = struct_CUexecAffinitySmCount_st -CUexecAffinitySmCount = struct_CUexecAffinitySmCount_st -class struct_CUexecAffinityParam_st(Structure): - pass - -class union_CUexecAffinityParam_st_param(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('smCount', CUexecAffinitySmCount), - ] - -struct_CUexecAffinityParam_st._pack_ = 1 # source:False -struct_CUexecAffinityParam_st._fields_ = [ - ('type', CUexecAffinityType), - ('param', union_CUexecAffinityParam_st_param), -] - -CUexecAffinityParam_v1 = struct_CUexecAffinityParam_st -CUexecAffinityParam = struct_CUexecAffinityParam_st - -# values for enumeration 'CUlibraryOption_enum' -CUlibraryOption_enum__enumvalues = { - 0: 'CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE', - 1: 'CU_LIBRARY_BINARY_IS_PRESERVED', - 2: 'CU_LIBRARY_NUM_OPTIONS', -} -CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE = 0 -CU_LIBRARY_BINARY_IS_PRESERVED = 1 -CU_LIBRARY_NUM_OPTIONS = 2 -CUlibraryOption_enum = ctypes.c_uint32 # enum -CUlibraryOption = CUlibraryOption_enum -CUlibraryOption__enumvalues = CUlibraryOption_enum__enumvalues -class struct_CUlibraryHostUniversalFunctionAndDataTable_st(Structure): - pass - -struct_CUlibraryHostUniversalFunctionAndDataTable_st._pack_ = 1 # source:False -struct_CUlibraryHostUniversalFunctionAndDataTable_st._fields_ = [ - ('functionTable', ctypes.POINTER(None)), - ('functionWindowSize', ctypes.c_uint64), - ('dataTable', ctypes.POINTER(None)), - ('dataWindowSize', ctypes.c_uint64), -] - -CUlibraryHostUniversalFunctionAndDataTable = struct_CUlibraryHostUniversalFunctionAndDataTable_st - -# values for enumeration 'cudaError_enum' -cudaError_enum__enumvalues = { - 0: 'CUDA_SUCCESS', - 1: 'CUDA_ERROR_INVALID_VALUE', - 2: 'CUDA_ERROR_OUT_OF_MEMORY', - 3: 'CUDA_ERROR_NOT_INITIALIZED', - 4: 'CUDA_ERROR_DEINITIALIZED', - 5: 'CUDA_ERROR_PROFILER_DISABLED', - 6: 'CUDA_ERROR_PROFILER_NOT_INITIALIZED', - 7: 'CUDA_ERROR_PROFILER_ALREADY_STARTED', - 8: 'CUDA_ERROR_PROFILER_ALREADY_STOPPED', - 34: 'CUDA_ERROR_STUB_LIBRARY', - 46: 'CUDA_ERROR_DEVICE_UNAVAILABLE', - 100: 'CUDA_ERROR_NO_DEVICE', - 101: 'CUDA_ERROR_INVALID_DEVICE', - 102: 'CUDA_ERROR_DEVICE_NOT_LICENSED', - 200: 'CUDA_ERROR_INVALID_IMAGE', - 201: 'CUDA_ERROR_INVALID_CONTEXT', - 202: 'CUDA_ERROR_CONTEXT_ALREADY_CURRENT', - 205: 'CUDA_ERROR_MAP_FAILED', - 206: 'CUDA_ERROR_UNMAP_FAILED', - 207: 'CUDA_ERROR_ARRAY_IS_MAPPED', - 208: 'CUDA_ERROR_ALREADY_MAPPED', - 209: 'CUDA_ERROR_NO_BINARY_FOR_GPU', - 210: 'CUDA_ERROR_ALREADY_ACQUIRED', - 211: 'CUDA_ERROR_NOT_MAPPED', - 212: 'CUDA_ERROR_NOT_MAPPED_AS_ARRAY', - 213: 'CUDA_ERROR_NOT_MAPPED_AS_POINTER', - 214: 'CUDA_ERROR_ECC_UNCORRECTABLE', - 215: 'CUDA_ERROR_UNSUPPORTED_LIMIT', - 216: 'CUDA_ERROR_CONTEXT_ALREADY_IN_USE', - 217: 'CUDA_ERROR_PEER_ACCESS_UNSUPPORTED', - 218: 'CUDA_ERROR_INVALID_PTX', - 219: 'CUDA_ERROR_INVALID_GRAPHICS_CONTEXT', - 220: 'CUDA_ERROR_NVLINK_UNCORRECTABLE', - 221: 'CUDA_ERROR_JIT_COMPILER_NOT_FOUND', - 222: 'CUDA_ERROR_UNSUPPORTED_PTX_VERSION', - 223: 'CUDA_ERROR_JIT_COMPILATION_DISABLED', - 224: 'CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY', - 300: 'CUDA_ERROR_INVALID_SOURCE', - 301: 'CUDA_ERROR_FILE_NOT_FOUND', - 302: 'CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND', - 303: 'CUDA_ERROR_SHARED_OBJECT_INIT_FAILED', - 304: 'CUDA_ERROR_OPERATING_SYSTEM', - 400: 'CUDA_ERROR_INVALID_HANDLE', - 401: 'CUDA_ERROR_ILLEGAL_STATE', - 500: 'CUDA_ERROR_NOT_FOUND', - 600: 'CUDA_ERROR_NOT_READY', - 700: 'CUDA_ERROR_ILLEGAL_ADDRESS', - 701: 'CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES', - 702: 'CUDA_ERROR_LAUNCH_TIMEOUT', - 703: 'CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING', - 704: 'CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED', - 705: 'CUDA_ERROR_PEER_ACCESS_NOT_ENABLED', - 708: 'CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE', - 709: 'CUDA_ERROR_CONTEXT_IS_DESTROYED', - 710: 'CUDA_ERROR_ASSERT', - 711: 'CUDA_ERROR_TOO_MANY_PEERS', - 712: 'CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED', - 713: 'CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED', - 714: 'CUDA_ERROR_HARDWARE_STACK_ERROR', - 715: 'CUDA_ERROR_ILLEGAL_INSTRUCTION', - 716: 'CUDA_ERROR_MISALIGNED_ADDRESS', - 717: 'CUDA_ERROR_INVALID_ADDRESS_SPACE', - 718: 'CUDA_ERROR_INVALID_PC', - 719: 'CUDA_ERROR_LAUNCH_FAILED', - 720: 'CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE', - 800: 'CUDA_ERROR_NOT_PERMITTED', - 801: 'CUDA_ERROR_NOT_SUPPORTED', - 802: 'CUDA_ERROR_SYSTEM_NOT_READY', - 803: 'CUDA_ERROR_SYSTEM_DRIVER_MISMATCH', - 804: 'CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE', - 805: 'CUDA_ERROR_MPS_CONNECTION_FAILED', - 806: 'CUDA_ERROR_MPS_RPC_FAILURE', - 807: 'CUDA_ERROR_MPS_SERVER_NOT_READY', - 808: 'CUDA_ERROR_MPS_MAX_CLIENTS_REACHED', - 809: 'CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED', - 810: 'CUDA_ERROR_MPS_CLIENT_TERMINATED', - 811: 'CUDA_ERROR_CDP_NOT_SUPPORTED', - 812: 'CUDA_ERROR_CDP_VERSION_MISMATCH', - 900: 'CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED', - 901: 'CUDA_ERROR_STREAM_CAPTURE_INVALIDATED', - 902: 'CUDA_ERROR_STREAM_CAPTURE_MERGE', - 903: 'CUDA_ERROR_STREAM_CAPTURE_UNMATCHED', - 904: 'CUDA_ERROR_STREAM_CAPTURE_UNJOINED', - 905: 'CUDA_ERROR_STREAM_CAPTURE_ISOLATION', - 906: 'CUDA_ERROR_STREAM_CAPTURE_IMPLICIT', - 907: 'CUDA_ERROR_CAPTURED_EVENT', - 908: 'CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD', - 909: 'CUDA_ERROR_TIMEOUT', - 910: 'CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE', - 911: 'CUDA_ERROR_EXTERNAL_DEVICE', - 912: 'CUDA_ERROR_INVALID_CLUSTER_SIZE', - 999: 'CUDA_ERROR_UNKNOWN', -} -CUDA_SUCCESS = 0 -CUDA_ERROR_INVALID_VALUE = 1 -CUDA_ERROR_OUT_OF_MEMORY = 2 -CUDA_ERROR_NOT_INITIALIZED = 3 -CUDA_ERROR_DEINITIALIZED = 4 -CUDA_ERROR_PROFILER_DISABLED = 5 -CUDA_ERROR_PROFILER_NOT_INITIALIZED = 6 -CUDA_ERROR_PROFILER_ALREADY_STARTED = 7 -CUDA_ERROR_PROFILER_ALREADY_STOPPED = 8 -CUDA_ERROR_STUB_LIBRARY = 34 -CUDA_ERROR_DEVICE_UNAVAILABLE = 46 -CUDA_ERROR_NO_DEVICE = 100 -CUDA_ERROR_INVALID_DEVICE = 101 -CUDA_ERROR_DEVICE_NOT_LICENSED = 102 -CUDA_ERROR_INVALID_IMAGE = 200 -CUDA_ERROR_INVALID_CONTEXT = 201 -CUDA_ERROR_CONTEXT_ALREADY_CURRENT = 202 -CUDA_ERROR_MAP_FAILED = 205 -CUDA_ERROR_UNMAP_FAILED = 206 -CUDA_ERROR_ARRAY_IS_MAPPED = 207 -CUDA_ERROR_ALREADY_MAPPED = 208 -CUDA_ERROR_NO_BINARY_FOR_GPU = 209 -CUDA_ERROR_ALREADY_ACQUIRED = 210 -CUDA_ERROR_NOT_MAPPED = 211 -CUDA_ERROR_NOT_MAPPED_AS_ARRAY = 212 -CUDA_ERROR_NOT_MAPPED_AS_POINTER = 213 -CUDA_ERROR_ECC_UNCORRECTABLE = 214 -CUDA_ERROR_UNSUPPORTED_LIMIT = 215 -CUDA_ERROR_CONTEXT_ALREADY_IN_USE = 216 -CUDA_ERROR_PEER_ACCESS_UNSUPPORTED = 217 -CUDA_ERROR_INVALID_PTX = 218 -CUDA_ERROR_INVALID_GRAPHICS_CONTEXT = 219 -CUDA_ERROR_NVLINK_UNCORRECTABLE = 220 -CUDA_ERROR_JIT_COMPILER_NOT_FOUND = 221 -CUDA_ERROR_UNSUPPORTED_PTX_VERSION = 222 -CUDA_ERROR_JIT_COMPILATION_DISABLED = 223 -CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY = 224 -CUDA_ERROR_INVALID_SOURCE = 300 -CUDA_ERROR_FILE_NOT_FOUND = 301 -CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND = 302 -CUDA_ERROR_SHARED_OBJECT_INIT_FAILED = 303 -CUDA_ERROR_OPERATING_SYSTEM = 304 -CUDA_ERROR_INVALID_HANDLE = 400 -CUDA_ERROR_ILLEGAL_STATE = 401 -CUDA_ERROR_NOT_FOUND = 500 -CUDA_ERROR_NOT_READY = 600 -CUDA_ERROR_ILLEGAL_ADDRESS = 700 -CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES = 701 -CUDA_ERROR_LAUNCH_TIMEOUT = 702 -CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING = 703 -CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED = 704 -CUDA_ERROR_PEER_ACCESS_NOT_ENABLED = 705 -CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE = 708 -CUDA_ERROR_CONTEXT_IS_DESTROYED = 709 -CUDA_ERROR_ASSERT = 710 -CUDA_ERROR_TOO_MANY_PEERS = 711 -CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED = 712 -CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED = 713 -CUDA_ERROR_HARDWARE_STACK_ERROR = 714 -CUDA_ERROR_ILLEGAL_INSTRUCTION = 715 -CUDA_ERROR_MISALIGNED_ADDRESS = 716 -CUDA_ERROR_INVALID_ADDRESS_SPACE = 717 -CUDA_ERROR_INVALID_PC = 718 -CUDA_ERROR_LAUNCH_FAILED = 719 -CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE = 720 -CUDA_ERROR_NOT_PERMITTED = 800 -CUDA_ERROR_NOT_SUPPORTED = 801 -CUDA_ERROR_SYSTEM_NOT_READY = 802 -CUDA_ERROR_SYSTEM_DRIVER_MISMATCH = 803 -CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE = 804 -CUDA_ERROR_MPS_CONNECTION_FAILED = 805 -CUDA_ERROR_MPS_RPC_FAILURE = 806 -CUDA_ERROR_MPS_SERVER_NOT_READY = 807 -CUDA_ERROR_MPS_MAX_CLIENTS_REACHED = 808 -CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED = 809 -CUDA_ERROR_MPS_CLIENT_TERMINATED = 810 -CUDA_ERROR_CDP_NOT_SUPPORTED = 811 -CUDA_ERROR_CDP_VERSION_MISMATCH = 812 -CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED = 900 -CUDA_ERROR_STREAM_CAPTURE_INVALIDATED = 901 -CUDA_ERROR_STREAM_CAPTURE_MERGE = 902 -CUDA_ERROR_STREAM_CAPTURE_UNMATCHED = 903 -CUDA_ERROR_STREAM_CAPTURE_UNJOINED = 904 -CUDA_ERROR_STREAM_CAPTURE_ISOLATION = 905 -CUDA_ERROR_STREAM_CAPTURE_IMPLICIT = 906 -CUDA_ERROR_CAPTURED_EVENT = 907 -CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD = 908 -CUDA_ERROR_TIMEOUT = 909 -CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE = 910 -CUDA_ERROR_EXTERNAL_DEVICE = 911 -CUDA_ERROR_INVALID_CLUSTER_SIZE = 912 -CUDA_ERROR_UNKNOWN = 999 -cudaError_enum = ctypes.c_uint32 # enum -CUresult = cudaError_enum -CUresult__enumvalues = cudaError_enum__enumvalues - -# values for enumeration 'CUdevice_P2PAttribute_enum' -CUdevice_P2PAttribute_enum__enumvalues = { - 1: 'CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK', - 2: 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED', - 3: 'CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED', - 4: 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED', - 4: 'CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED', -} -CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK = 1 -CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED = 2 -CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED = 3 -CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED = 4 -CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED = 4 -CUdevice_P2PAttribute_enum = ctypes.c_uint32 # enum -CUdevice_P2PAttribute = CUdevice_P2PAttribute_enum -CUdevice_P2PAttribute__enumvalues = CUdevice_P2PAttribute_enum__enumvalues -CUstreamCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_CUstream_st), cudaError_enum, ctypes.POINTER(None)) -CUoccupancyB2DSize = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_int32) -class struct_CUDA_MEMCPY2D_st(Structure): - pass - -struct_CUDA_MEMCPY2D_st._pack_ = 1 # source:False -struct_CUDA_MEMCPY2D_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcPitch', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstPitch', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), -] - -CUDA_MEMCPY2D_v2 = struct_CUDA_MEMCPY2D_st -CUDA_MEMCPY2D = struct_CUDA_MEMCPY2D_st -class struct_CUDA_MEMCPY3D_st(Structure): - pass - -struct_CUDA_MEMCPY3D_st._pack_ = 1 # source:False -struct_CUDA_MEMCPY3D_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved0', ctypes.POINTER(None)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved1', ctypes.POINTER(None)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), -] - -CUDA_MEMCPY3D_v2 = struct_CUDA_MEMCPY3D_st -CUDA_MEMCPY3D = struct_CUDA_MEMCPY3D_st -class struct_CUDA_MEMCPY3D_PEER_st(Structure): - pass - -struct_CUDA_MEMCPY3D_PEER_st._pack_ = 1 # source:False -struct_CUDA_MEMCPY3D_PEER_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcContext', ctypes.POINTER(struct_CUctx_st)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstContext', ctypes.POINTER(struct_CUctx_st)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), -] - -CUDA_MEMCPY3D_PEER_v1 = struct_CUDA_MEMCPY3D_PEER_st -CUDA_MEMCPY3D_PEER = struct_CUDA_MEMCPY3D_PEER_st -class struct_CUDA_ARRAY_DESCRIPTOR_st(Structure): - pass - -struct_CUDA_ARRAY_DESCRIPTOR_st._pack_ = 1 # source:False -struct_CUDA_ARRAY_DESCRIPTOR_st._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), -] - -CUDA_ARRAY_DESCRIPTOR_v2 = struct_CUDA_ARRAY_DESCRIPTOR_st -CUDA_ARRAY_DESCRIPTOR = struct_CUDA_ARRAY_DESCRIPTOR_st -class struct_CUDA_ARRAY3D_DESCRIPTOR_st(Structure): - pass - -struct_CUDA_ARRAY3D_DESCRIPTOR_st._pack_ = 1 # source:False -struct_CUDA_ARRAY3D_DESCRIPTOR_st._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_ARRAY3D_DESCRIPTOR_v2 = struct_CUDA_ARRAY3D_DESCRIPTOR_st -CUDA_ARRAY3D_DESCRIPTOR = struct_CUDA_ARRAY3D_DESCRIPTOR_st -class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st(Structure): - pass - -class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent(Structure): - pass - -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent._pack_ = 1 # source:False -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depth', ctypes.c_uint32), -] - -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st._pack_ = 1 # source:False -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st._fields_ = [ - ('tileExtent', struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent), - ('miptailFirstLevel', ctypes.c_uint32), - ('miptailSize', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 4), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_ARRAY_SPARSE_PROPERTIES_v1 = struct_CUDA_ARRAY_SPARSE_PROPERTIES_st -CUDA_ARRAY_SPARSE_PROPERTIES = struct_CUDA_ARRAY_SPARSE_PROPERTIES_st -class struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st(Structure): - pass - -struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st._pack_ = 1 # source:False -struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st._fields_ = [ - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('reserved', ctypes.c_uint32 * 4), -] - -CUDA_ARRAY_MEMORY_REQUIREMENTS_v1 = struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st -CUDA_ARRAY_MEMORY_REQUIREMENTS = struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st -class struct_CUDA_RESOURCE_DESC_st(Structure): - pass - -class union_CUDA_RESOURCE_DESC_st_res(Union): - pass - -class struct_CUDA_RESOURCE_DESC_st_0_array(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_array._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_array._fields_ = [ - ('hArray', ctypes.POINTER(struct_CUarray_st)), -] - -class struct_CUDA_RESOURCE_DESC_st_0_mipmap(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_mipmap._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_mipmap._fields_ = [ - ('hMipmappedArray', ctypes.POINTER(struct_CUmipmappedArray_st)), -] - -class struct_CUDA_RESOURCE_DESC_st_0_linear(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_linear._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_linear._fields_ = [ - ('devPtr', ctypes.c_uint64), - ('format', CUarray_format), - ('numChannels', ctypes.c_uint32), - ('sizeInBytes', ctypes.c_uint64), -] - -class struct_CUDA_RESOURCE_DESC_st_0_pitch2D(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_pitch2D._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_pitch2D._fields_ = [ - ('devPtr', ctypes.c_uint64), - ('format', CUarray_format), - ('numChannels', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), -] - -class struct_CUDA_RESOURCE_DESC_st_0_reserved(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_reserved._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_reserved._fields_ = [ - ('reserved', ctypes.c_int32 * 32), -] - -union_CUDA_RESOURCE_DESC_st_res._pack_ = 1 # source:False -union_CUDA_RESOURCE_DESC_st_res._fields_ = [ - ('array', struct_CUDA_RESOURCE_DESC_st_0_array), - ('mipmap', struct_CUDA_RESOURCE_DESC_st_0_mipmap), - ('linear', struct_CUDA_RESOURCE_DESC_st_0_linear), - ('pitch2D', struct_CUDA_RESOURCE_DESC_st_0_pitch2D), - ('reserved', struct_CUDA_RESOURCE_DESC_st_0_reserved), -] - -struct_CUDA_RESOURCE_DESC_st._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st._fields_ = [ - ('resType', CUresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_CUDA_RESOURCE_DESC_st_res), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -CUDA_RESOURCE_DESC_v1 = struct_CUDA_RESOURCE_DESC_st -CUDA_RESOURCE_DESC = struct_CUDA_RESOURCE_DESC_st -class struct_CUDA_TEXTURE_DESC_st(Structure): - pass - -struct_CUDA_TEXTURE_DESC_st._pack_ = 1 # source:False -struct_CUDA_TEXTURE_DESC_st._fields_ = [ - ('addressMode', CUaddress_mode_enum * 3), - ('filterMode', CUfilter_mode), - ('flags', ctypes.c_uint32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', CUfilter_mode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('borderColor', ctypes.c_float * 4), - ('reserved', ctypes.c_int32 * 12), -] - -CUDA_TEXTURE_DESC_v1 = struct_CUDA_TEXTURE_DESC_st -CUDA_TEXTURE_DESC = struct_CUDA_TEXTURE_DESC_st - -# values for enumeration 'CUresourceViewFormat_enum' -CUresourceViewFormat_enum__enumvalues = { - 0: 'CU_RES_VIEW_FORMAT_NONE', - 1: 'CU_RES_VIEW_FORMAT_UINT_1X8', - 2: 'CU_RES_VIEW_FORMAT_UINT_2X8', - 3: 'CU_RES_VIEW_FORMAT_UINT_4X8', - 4: 'CU_RES_VIEW_FORMAT_SINT_1X8', - 5: 'CU_RES_VIEW_FORMAT_SINT_2X8', - 6: 'CU_RES_VIEW_FORMAT_SINT_4X8', - 7: 'CU_RES_VIEW_FORMAT_UINT_1X16', - 8: 'CU_RES_VIEW_FORMAT_UINT_2X16', - 9: 'CU_RES_VIEW_FORMAT_UINT_4X16', - 10: 'CU_RES_VIEW_FORMAT_SINT_1X16', - 11: 'CU_RES_VIEW_FORMAT_SINT_2X16', - 12: 'CU_RES_VIEW_FORMAT_SINT_4X16', - 13: 'CU_RES_VIEW_FORMAT_UINT_1X32', - 14: 'CU_RES_VIEW_FORMAT_UINT_2X32', - 15: 'CU_RES_VIEW_FORMAT_UINT_4X32', - 16: 'CU_RES_VIEW_FORMAT_SINT_1X32', - 17: 'CU_RES_VIEW_FORMAT_SINT_2X32', - 18: 'CU_RES_VIEW_FORMAT_SINT_4X32', - 19: 'CU_RES_VIEW_FORMAT_FLOAT_1X16', - 20: 'CU_RES_VIEW_FORMAT_FLOAT_2X16', - 21: 'CU_RES_VIEW_FORMAT_FLOAT_4X16', - 22: 'CU_RES_VIEW_FORMAT_FLOAT_1X32', - 23: 'CU_RES_VIEW_FORMAT_FLOAT_2X32', - 24: 'CU_RES_VIEW_FORMAT_FLOAT_4X32', - 25: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC1', - 26: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC2', - 27: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC3', - 28: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC4', - 29: 'CU_RES_VIEW_FORMAT_SIGNED_BC4', - 30: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC5', - 31: 'CU_RES_VIEW_FORMAT_SIGNED_BC5', - 32: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 33: 'CU_RES_VIEW_FORMAT_SIGNED_BC6H', - 34: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC7', -} -CU_RES_VIEW_FORMAT_NONE = 0 -CU_RES_VIEW_FORMAT_UINT_1X8 = 1 -CU_RES_VIEW_FORMAT_UINT_2X8 = 2 -CU_RES_VIEW_FORMAT_UINT_4X8 = 3 -CU_RES_VIEW_FORMAT_SINT_1X8 = 4 -CU_RES_VIEW_FORMAT_SINT_2X8 = 5 -CU_RES_VIEW_FORMAT_SINT_4X8 = 6 -CU_RES_VIEW_FORMAT_UINT_1X16 = 7 -CU_RES_VIEW_FORMAT_UINT_2X16 = 8 -CU_RES_VIEW_FORMAT_UINT_4X16 = 9 -CU_RES_VIEW_FORMAT_SINT_1X16 = 10 -CU_RES_VIEW_FORMAT_SINT_2X16 = 11 -CU_RES_VIEW_FORMAT_SINT_4X16 = 12 -CU_RES_VIEW_FORMAT_UINT_1X32 = 13 -CU_RES_VIEW_FORMAT_UINT_2X32 = 14 -CU_RES_VIEW_FORMAT_UINT_4X32 = 15 -CU_RES_VIEW_FORMAT_SINT_1X32 = 16 -CU_RES_VIEW_FORMAT_SINT_2X32 = 17 -CU_RES_VIEW_FORMAT_SINT_4X32 = 18 -CU_RES_VIEW_FORMAT_FLOAT_1X16 = 19 -CU_RES_VIEW_FORMAT_FLOAT_2X16 = 20 -CU_RES_VIEW_FORMAT_FLOAT_4X16 = 21 -CU_RES_VIEW_FORMAT_FLOAT_1X32 = 22 -CU_RES_VIEW_FORMAT_FLOAT_2X32 = 23 -CU_RES_VIEW_FORMAT_FLOAT_4X32 = 24 -CU_RES_VIEW_FORMAT_UNSIGNED_BC1 = 25 -CU_RES_VIEW_FORMAT_UNSIGNED_BC2 = 26 -CU_RES_VIEW_FORMAT_UNSIGNED_BC3 = 27 -CU_RES_VIEW_FORMAT_UNSIGNED_BC4 = 28 -CU_RES_VIEW_FORMAT_SIGNED_BC4 = 29 -CU_RES_VIEW_FORMAT_UNSIGNED_BC5 = 30 -CU_RES_VIEW_FORMAT_SIGNED_BC5 = 31 -CU_RES_VIEW_FORMAT_UNSIGNED_BC6H = 32 -CU_RES_VIEW_FORMAT_SIGNED_BC6H = 33 -CU_RES_VIEW_FORMAT_UNSIGNED_BC7 = 34 -CUresourceViewFormat_enum = ctypes.c_uint32 # enum -CUresourceViewFormat = CUresourceViewFormat_enum -CUresourceViewFormat__enumvalues = CUresourceViewFormat_enum__enumvalues -class struct_CUDA_RESOURCE_VIEW_DESC_st(Structure): - pass - -struct_CUDA_RESOURCE_VIEW_DESC_st._pack_ = 1 # source:False -struct_CUDA_RESOURCE_VIEW_DESC_st._fields_ = [ - ('format', CUresourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), -] - -CUDA_RESOURCE_VIEW_DESC_v1 = struct_CUDA_RESOURCE_VIEW_DESC_st -CUDA_RESOURCE_VIEW_DESC = struct_CUDA_RESOURCE_VIEW_DESC_st -class struct_CUtensorMap_st(Structure): - pass - -struct_CUtensorMap_st._pack_ = 1 # source:False -struct_CUtensorMap_st._fields_ = [ - ('opaque', ctypes.c_uint64 * 16), -] - -CUtensorMap = struct_CUtensorMap_st - -# values for enumeration 'CUtensorMapDataType_enum' -CUtensorMapDataType_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_DATA_TYPE_UINT8', - 1: 'CU_TENSOR_MAP_DATA_TYPE_UINT16', - 2: 'CU_TENSOR_MAP_DATA_TYPE_UINT32', - 3: 'CU_TENSOR_MAP_DATA_TYPE_INT32', - 4: 'CU_TENSOR_MAP_DATA_TYPE_UINT64', - 5: 'CU_TENSOR_MAP_DATA_TYPE_INT64', - 6: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT16', - 7: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32', - 8: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT64', - 9: 'CU_TENSOR_MAP_DATA_TYPE_BFLOAT16', - 10: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ', - 11: 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32', - 12: 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ', -} -CU_TENSOR_MAP_DATA_TYPE_UINT8 = 0 -CU_TENSOR_MAP_DATA_TYPE_UINT16 = 1 -CU_TENSOR_MAP_DATA_TYPE_UINT32 = 2 -CU_TENSOR_MAP_DATA_TYPE_INT32 = 3 -CU_TENSOR_MAP_DATA_TYPE_UINT64 = 4 -CU_TENSOR_MAP_DATA_TYPE_INT64 = 5 -CU_TENSOR_MAP_DATA_TYPE_FLOAT16 = 6 -CU_TENSOR_MAP_DATA_TYPE_FLOAT32 = 7 -CU_TENSOR_MAP_DATA_TYPE_FLOAT64 = 8 -CU_TENSOR_MAP_DATA_TYPE_BFLOAT16 = 9 -CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ = 10 -CU_TENSOR_MAP_DATA_TYPE_TFLOAT32 = 11 -CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ = 12 -CUtensorMapDataType_enum = ctypes.c_uint32 # enum -CUtensorMapDataType = CUtensorMapDataType_enum -CUtensorMapDataType__enumvalues = CUtensorMapDataType_enum__enumvalues - -# values for enumeration 'CUtensorMapInterleave_enum' -CUtensorMapInterleave_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_INTERLEAVE_NONE', - 1: 'CU_TENSOR_MAP_INTERLEAVE_16B', - 2: 'CU_TENSOR_MAP_INTERLEAVE_32B', -} -CU_TENSOR_MAP_INTERLEAVE_NONE = 0 -CU_TENSOR_MAP_INTERLEAVE_16B = 1 -CU_TENSOR_MAP_INTERLEAVE_32B = 2 -CUtensorMapInterleave_enum = ctypes.c_uint32 # enum -CUtensorMapInterleave = CUtensorMapInterleave_enum -CUtensorMapInterleave__enumvalues = CUtensorMapInterleave_enum__enumvalues - -# values for enumeration 'CUtensorMapSwizzle_enum' -CUtensorMapSwizzle_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_SWIZZLE_NONE', - 1: 'CU_TENSOR_MAP_SWIZZLE_32B', - 2: 'CU_TENSOR_MAP_SWIZZLE_64B', - 3: 'CU_TENSOR_MAP_SWIZZLE_128B', -} -CU_TENSOR_MAP_SWIZZLE_NONE = 0 -CU_TENSOR_MAP_SWIZZLE_32B = 1 -CU_TENSOR_MAP_SWIZZLE_64B = 2 -CU_TENSOR_MAP_SWIZZLE_128B = 3 -CUtensorMapSwizzle_enum = ctypes.c_uint32 # enum -CUtensorMapSwizzle = CUtensorMapSwizzle_enum -CUtensorMapSwizzle__enumvalues = CUtensorMapSwizzle_enum__enumvalues - -# values for enumeration 'CUtensorMapL2promotion_enum' -CUtensorMapL2promotion_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_L2_PROMOTION_NONE', - 1: 'CU_TENSOR_MAP_L2_PROMOTION_L2_64B', - 2: 'CU_TENSOR_MAP_L2_PROMOTION_L2_128B', - 3: 'CU_TENSOR_MAP_L2_PROMOTION_L2_256B', -} -CU_TENSOR_MAP_L2_PROMOTION_NONE = 0 -CU_TENSOR_MAP_L2_PROMOTION_L2_64B = 1 -CU_TENSOR_MAP_L2_PROMOTION_L2_128B = 2 -CU_TENSOR_MAP_L2_PROMOTION_L2_256B = 3 -CUtensorMapL2promotion_enum = ctypes.c_uint32 # enum -CUtensorMapL2promotion = CUtensorMapL2promotion_enum -CUtensorMapL2promotion__enumvalues = CUtensorMapL2promotion_enum__enumvalues - -# values for enumeration 'CUtensorMapFloatOOBfill_enum' -CUtensorMapFloatOOBfill_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE', - 1: 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA', -} -CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE = 0 -CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA = 1 -CUtensorMapFloatOOBfill_enum = ctypes.c_uint32 # enum -CUtensorMapFloatOOBfill = CUtensorMapFloatOOBfill_enum -CUtensorMapFloatOOBfill__enumvalues = CUtensorMapFloatOOBfill_enum__enumvalues -class struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st(Structure): - pass - -struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st._pack_ = 1 # source:False -struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st._fields_ = [ - ('p2pToken', ctypes.c_uint64), - ('vaSpaceToken', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_v1 = struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st -CUDA_POINTER_ATTRIBUTE_P2P_TOKENS = struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st - -# values for enumeration 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum' -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum__enumvalues = { - 0: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE', - 1: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ', - 3: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE', -} -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE = 0 -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ = 1 -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE = 3 -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum = ctypes.c_uint32 # enum -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS = CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS__enumvalues = CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum__enumvalues -class struct_CUDA_LAUNCH_PARAMS_st(Structure): - pass - -struct_CUDA_LAUNCH_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_LAUNCH_PARAMS_st._fields_ = [ - ('function', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_CUstream_st)), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), -] - -CUDA_LAUNCH_PARAMS_v1 = struct_CUDA_LAUNCH_PARAMS_st -CUDA_LAUNCH_PARAMS = struct_CUDA_LAUNCH_PARAMS_st - -# values for enumeration 'CUexternalMemoryHandleType_enum' -CUexternalMemoryHandleType_enum__enumvalues = { - 1: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD', - 2: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32', - 3: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 4: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP', - 5: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE', - 6: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE', - 7: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT', - 8: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF', -} -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD = 1 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32 = 2 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT = 3 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP = 4 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE = 5 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE = 6 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT = 7 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF = 8 -CUexternalMemoryHandleType_enum = ctypes.c_uint32 # enum -CUexternalMemoryHandleType = CUexternalMemoryHandleType_enum -CUexternalMemoryHandleType__enumvalues = CUexternalMemoryHandleType_enum__enumvalues -class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st(Structure): - pass - -class union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle(Union): - pass - -class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle._pack_ = 1 # source:False -union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32), - ('nvSciBufObject', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st._fields_ = [ - ('type', CUexternalMemoryHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_MEMORY_HANDLE_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st -CUDA_EXTERNAL_MEMORY_HANDLE_DESC = struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st -class struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_MEMORY_BUFFER_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st -CUDA_EXTERNAL_MEMORY_BUFFER_DESC = struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st -class struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('arrayDesc', CUDA_ARRAY3D_DESCRIPTOR), - ('numLevels', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st -CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC = struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st - -# values for enumeration 'CUexternalSemaphoreHandleType_enum' -CUexternalSemaphoreHandleType_enum__enumvalues = { - 1: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD', - 2: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32', - 3: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 4: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE', - 5: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE', - 6: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC', - 7: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX', - 8: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT', - 9: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD', - 10: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32', -} -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD = 1 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32 = 2 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT = 3 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE = 4 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE = 5 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC = 6 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX = 7 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT = 8 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD = 9 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32 = 10 -CUexternalSemaphoreHandleType_enum = ctypes.c_uint32 # enum -CUexternalSemaphoreHandleType = CUexternalSemaphoreHandleType_enum -CUexternalSemaphoreHandleType__enumvalues = CUexternalSemaphoreHandleType_enum__enumvalues -class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st(Structure): - pass - -class union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle(Union): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32), - ('nvSciSyncObj', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st._fields_ = [ - ('type', CUexternalSemaphoreHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st -CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC = struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync(Union): - pass - -union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), -] - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params._fields_ = [ - ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence), - ('nvSciSync', union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync), - ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 12), -] - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st._fields_ = [ - ('params', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st -CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS = struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync(Union): - pass - -union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), - ('timeoutMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params._fields_ = [ - ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence), - ('nvSciSync', union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync), - ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 10), -] - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st._fields_ = [ - ('params', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st -CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS = struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st -class struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st))), - ('paramsArray', ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_v1 = struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st -CUDA_EXT_SEM_SIGNAL_NODE_PARAMS = struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st -class struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st))), - ('paramsArray', ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -CUDA_EXT_SEM_WAIT_NODE_PARAMS_v1 = struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st -CUDA_EXT_SEM_WAIT_NODE_PARAMS = struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st -CUmemGenericAllocationHandle_v1 = ctypes.c_uint64 -CUmemGenericAllocationHandle = ctypes.c_uint64 - -# values for enumeration 'CUmemAllocationHandleType_enum' -CUmemAllocationHandleType_enum__enumvalues = { - 0: 'CU_MEM_HANDLE_TYPE_NONE', - 1: 'CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR', - 2: 'CU_MEM_HANDLE_TYPE_WIN32', - 4: 'CU_MEM_HANDLE_TYPE_WIN32_KMT', - 2147483647: 'CU_MEM_HANDLE_TYPE_MAX', -} -CU_MEM_HANDLE_TYPE_NONE = 0 -CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR = 1 -CU_MEM_HANDLE_TYPE_WIN32 = 2 -CU_MEM_HANDLE_TYPE_WIN32_KMT = 4 -CU_MEM_HANDLE_TYPE_MAX = 2147483647 -CUmemAllocationHandleType_enum = ctypes.c_uint32 # enum -CUmemAllocationHandleType = CUmemAllocationHandleType_enum -CUmemAllocationHandleType__enumvalues = CUmemAllocationHandleType_enum__enumvalues - -# values for enumeration 'CUmemAccess_flags_enum' -CUmemAccess_flags_enum__enumvalues = { - 0: 'CU_MEM_ACCESS_FLAGS_PROT_NONE', - 1: 'CU_MEM_ACCESS_FLAGS_PROT_READ', - 3: 'CU_MEM_ACCESS_FLAGS_PROT_READWRITE', - 2147483647: 'CU_MEM_ACCESS_FLAGS_PROT_MAX', -} -CU_MEM_ACCESS_FLAGS_PROT_NONE = 0 -CU_MEM_ACCESS_FLAGS_PROT_READ = 1 -CU_MEM_ACCESS_FLAGS_PROT_READWRITE = 3 -CU_MEM_ACCESS_FLAGS_PROT_MAX = 2147483647 -CUmemAccess_flags_enum = ctypes.c_uint32 # enum -CUmemAccess_flags = CUmemAccess_flags_enum -CUmemAccess_flags__enumvalues = CUmemAccess_flags_enum__enumvalues - -# values for enumeration 'CUmemLocationType_enum' -CUmemLocationType_enum__enumvalues = { - 0: 'CU_MEM_LOCATION_TYPE_INVALID', - 1: 'CU_MEM_LOCATION_TYPE_DEVICE', - 2147483647: 'CU_MEM_LOCATION_TYPE_MAX', -} -CU_MEM_LOCATION_TYPE_INVALID = 0 -CU_MEM_LOCATION_TYPE_DEVICE = 1 -CU_MEM_LOCATION_TYPE_MAX = 2147483647 -CUmemLocationType_enum = ctypes.c_uint32 # enum -CUmemLocationType = CUmemLocationType_enum -CUmemLocationType__enumvalues = CUmemLocationType_enum__enumvalues - -# values for enumeration 'CUmemAllocationType_enum' -CUmemAllocationType_enum__enumvalues = { - 0: 'CU_MEM_ALLOCATION_TYPE_INVALID', - 1: 'CU_MEM_ALLOCATION_TYPE_PINNED', - 2147483647: 'CU_MEM_ALLOCATION_TYPE_MAX', -} -CU_MEM_ALLOCATION_TYPE_INVALID = 0 -CU_MEM_ALLOCATION_TYPE_PINNED = 1 -CU_MEM_ALLOCATION_TYPE_MAX = 2147483647 -CUmemAllocationType_enum = ctypes.c_uint32 # enum -CUmemAllocationType = CUmemAllocationType_enum -CUmemAllocationType__enumvalues = CUmemAllocationType_enum__enumvalues - -# values for enumeration 'CUmemAllocationGranularity_flags_enum' -CUmemAllocationGranularity_flags_enum__enumvalues = { - 0: 'CU_MEM_ALLOC_GRANULARITY_MINIMUM', - 1: 'CU_MEM_ALLOC_GRANULARITY_RECOMMENDED', -} -CU_MEM_ALLOC_GRANULARITY_MINIMUM = 0 -CU_MEM_ALLOC_GRANULARITY_RECOMMENDED = 1 -CUmemAllocationGranularity_flags_enum = ctypes.c_uint32 # enum -CUmemAllocationGranularity_flags = CUmemAllocationGranularity_flags_enum -CUmemAllocationGranularity_flags__enumvalues = CUmemAllocationGranularity_flags_enum__enumvalues - -# values for enumeration 'CUmemRangeHandleType_enum' -CUmemRangeHandleType_enum__enumvalues = { - 1: 'CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD', - 2147483647: 'CU_MEM_RANGE_HANDLE_TYPE_MAX', -} -CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD = 1 -CU_MEM_RANGE_HANDLE_TYPE_MAX = 2147483647 -CUmemRangeHandleType_enum = ctypes.c_uint32 # enum -CUmemRangeHandleType = CUmemRangeHandleType_enum -CUmemRangeHandleType__enumvalues = CUmemRangeHandleType_enum__enumvalues - -# values for enumeration 'CUarraySparseSubresourceType_enum' -CUarraySparseSubresourceType_enum__enumvalues = { - 0: 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL', - 1: 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL', -} -CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL = 0 -CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL = 1 -CUarraySparseSubresourceType_enum = ctypes.c_uint32 # enum -CUarraySparseSubresourceType = CUarraySparseSubresourceType_enum -CUarraySparseSubresourceType__enumvalues = CUarraySparseSubresourceType_enum__enumvalues - -# values for enumeration 'CUmemOperationType_enum' -CUmemOperationType_enum__enumvalues = { - 1: 'CU_MEM_OPERATION_TYPE_MAP', - 2: 'CU_MEM_OPERATION_TYPE_UNMAP', -} -CU_MEM_OPERATION_TYPE_MAP = 1 -CU_MEM_OPERATION_TYPE_UNMAP = 2 -CUmemOperationType_enum = ctypes.c_uint32 # enum -CUmemOperationType = CUmemOperationType_enum -CUmemOperationType__enumvalues = CUmemOperationType_enum__enumvalues - -# values for enumeration 'CUmemHandleType_enum' -CUmemHandleType_enum__enumvalues = { - 0: 'CU_MEM_HANDLE_TYPE_GENERIC', -} -CU_MEM_HANDLE_TYPE_GENERIC = 0 -CUmemHandleType_enum = ctypes.c_uint32 # enum -CUmemHandleType = CUmemHandleType_enum -CUmemHandleType__enumvalues = CUmemHandleType_enum__enumvalues -class struct_CUarrayMapInfo_st(Structure): - pass - -class union_CUarrayMapInfo_st_resource(Union): - pass - -union_CUarrayMapInfo_st_resource._pack_ = 1 # source:False -union_CUarrayMapInfo_st_resource._fields_ = [ - ('mipmap', ctypes.POINTER(struct_CUmipmappedArray_st)), - ('array', ctypes.POINTER(struct_CUarray_st)), -] - -class union_CUarrayMapInfo_st_subresource(Union): - pass - -class struct_CUarrayMapInfo_st_1_sparseLevel(Structure): - pass - -struct_CUarrayMapInfo_st_1_sparseLevel._pack_ = 1 # source:False -struct_CUarrayMapInfo_st_1_sparseLevel._fields_ = [ - ('level', ctypes.c_uint32), - ('layer', ctypes.c_uint32), - ('offsetX', ctypes.c_uint32), - ('offsetY', ctypes.c_uint32), - ('offsetZ', ctypes.c_uint32), - ('extentWidth', ctypes.c_uint32), - ('extentHeight', ctypes.c_uint32), - ('extentDepth', ctypes.c_uint32), -] - -class struct_CUarrayMapInfo_st_1_miptail(Structure): - pass - -struct_CUarrayMapInfo_st_1_miptail._pack_ = 1 # source:False -struct_CUarrayMapInfo_st_1_miptail._fields_ = [ - ('layer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -union_CUarrayMapInfo_st_subresource._pack_ = 1 # source:False -union_CUarrayMapInfo_st_subresource._fields_ = [ - ('sparseLevel', struct_CUarrayMapInfo_st_1_sparseLevel), - ('miptail', struct_CUarrayMapInfo_st_1_miptail), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -class union_CUarrayMapInfo_st_memHandle(Union): - pass - -union_CUarrayMapInfo_st_memHandle._pack_ = 1 # source:False -union_CUarrayMapInfo_st_memHandle._fields_ = [ - ('memHandle', ctypes.c_uint64), -] - -struct_CUarrayMapInfo_st._pack_ = 1 # source:False -struct_CUarrayMapInfo_st._fields_ = [ - ('resourceType', CUresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resource', union_CUarrayMapInfo_st_resource), - ('subresourceType', CUarraySparseSubresourceType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subresource', union_CUarrayMapInfo_st_subresource), - ('memOperationType', CUmemOperationType), - ('memHandleType', CUmemHandleType), - ('memHandle', union_CUarrayMapInfo_st_memHandle), - ('offset', ctypes.c_uint64), - ('deviceBitMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 2), -] - -CUarrayMapInfo_v1 = struct_CUarrayMapInfo_st -CUarrayMapInfo = struct_CUarrayMapInfo_st -class struct_CUmemLocation_st(Structure): - pass - -struct_CUmemLocation_st._pack_ = 1 # source:False -struct_CUmemLocation_st._fields_ = [ - ('type', CUmemLocationType), - ('id', ctypes.c_int32), -] - -CUmemLocation_v1 = struct_CUmemLocation_st -CUmemLocation = struct_CUmemLocation_st - -# values for enumeration 'CUmemAllocationCompType_enum' -CUmemAllocationCompType_enum__enumvalues = { - 0: 'CU_MEM_ALLOCATION_COMP_NONE', - 1: 'CU_MEM_ALLOCATION_COMP_GENERIC', -} -CU_MEM_ALLOCATION_COMP_NONE = 0 -CU_MEM_ALLOCATION_COMP_GENERIC = 1 -CUmemAllocationCompType_enum = ctypes.c_uint32 # enum -CUmemAllocationCompType = CUmemAllocationCompType_enum -CUmemAllocationCompType__enumvalues = CUmemAllocationCompType_enum__enumvalues -class struct_CUmemAllocationProp_st(Structure): - pass - -class struct_CUmemAllocationProp_st_allocFlags(Structure): - pass - -struct_CUmemAllocationProp_st_allocFlags._pack_ = 1 # source:False -struct_CUmemAllocationProp_st_allocFlags._fields_ = [ - ('compressionType', ctypes.c_ubyte), - ('gpuDirectRDMACapable', ctypes.c_ubyte), - ('usage', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 4), -] - -struct_CUmemAllocationProp_st._pack_ = 1 # source:False -struct_CUmemAllocationProp_st._fields_ = [ - ('type', CUmemAllocationType), - ('requestedHandleTypes', CUmemAllocationHandleType), - ('location', CUmemLocation), - ('win32HandleMetaData', ctypes.POINTER(None)), - ('allocFlags', struct_CUmemAllocationProp_st_allocFlags), -] - -CUmemAllocationProp_v1 = struct_CUmemAllocationProp_st -CUmemAllocationProp = struct_CUmemAllocationProp_st -class struct_CUmemAccessDesc_st(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('location', CUmemLocation), - ('flags', CUmemAccess_flags), - ] - -CUmemAccessDesc_v1 = struct_CUmemAccessDesc_st -CUmemAccessDesc = struct_CUmemAccessDesc_st - -# values for enumeration 'CUgraphExecUpdateResult_enum' -CUgraphExecUpdateResult_enum__enumvalues = { - 0: 'CU_GRAPH_EXEC_UPDATE_SUCCESS', - 1: 'CU_GRAPH_EXEC_UPDATE_ERROR', - 2: 'CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED', - 3: 'CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED', - 4: 'CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED', - 5: 'CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED', - 6: 'CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED', - 7: 'CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE', - 8: 'CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED', -} -CU_GRAPH_EXEC_UPDATE_SUCCESS = 0 -CU_GRAPH_EXEC_UPDATE_ERROR = 1 -CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED = 2 -CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED = 3 -CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED = 4 -CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED = 5 -CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED = 6 -CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE = 7 -CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED = 8 -CUgraphExecUpdateResult_enum = ctypes.c_uint32 # enum -CUgraphExecUpdateResult = CUgraphExecUpdateResult_enum -CUgraphExecUpdateResult__enumvalues = CUgraphExecUpdateResult_enum__enumvalues -class struct_CUgraphExecUpdateResultInfo_st(Structure): - pass - -struct_CUgraphExecUpdateResultInfo_st._pack_ = 1 # source:False -struct_CUgraphExecUpdateResultInfo_st._fields_ = [ - ('result', CUgraphExecUpdateResult), - ('PADDING_0', ctypes.c_ubyte * 4), - ('errorNode', ctypes.POINTER(struct_CUgraphNode_st)), - ('errorFromNode', ctypes.POINTER(struct_CUgraphNode_st)), -] - -CUgraphExecUpdateResultInfo_v1 = struct_CUgraphExecUpdateResultInfo_st -CUgraphExecUpdateResultInfo = struct_CUgraphExecUpdateResultInfo_st - -# values for enumeration 'CUmemPool_attribute_enum' -CUmemPool_attribute_enum__enumvalues = { - 1: 'CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES', - 2: 'CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC', - 3: 'CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES', - 4: 'CU_MEMPOOL_ATTR_RELEASE_THRESHOLD', - 5: 'CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT', - 6: 'CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH', - 7: 'CU_MEMPOOL_ATTR_USED_MEM_CURRENT', - 8: 'CU_MEMPOOL_ATTR_USED_MEM_HIGH', -} -CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES = 1 -CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC = 2 -CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES = 3 -CU_MEMPOOL_ATTR_RELEASE_THRESHOLD = 4 -CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT = 5 -CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH = 6 -CU_MEMPOOL_ATTR_USED_MEM_CURRENT = 7 -CU_MEMPOOL_ATTR_USED_MEM_HIGH = 8 -CUmemPool_attribute_enum = ctypes.c_uint32 # enum -CUmemPool_attribute = CUmemPool_attribute_enum -CUmemPool_attribute__enumvalues = CUmemPool_attribute_enum__enumvalues -class struct_CUmemPoolProps_st(Structure): - pass - -struct_CUmemPoolProps_st._pack_ = 1 # source:False -struct_CUmemPoolProps_st._fields_ = [ - ('allocType', CUmemAllocationType), - ('handleTypes', CUmemAllocationHandleType), - ('location', CUmemLocation), - ('win32SecurityAttributes', ctypes.POINTER(None)), - ('reserved', ctypes.c_ubyte * 64), -] - -CUmemPoolProps_v1 = struct_CUmemPoolProps_st -CUmemPoolProps = struct_CUmemPoolProps_st -class struct_CUmemPoolPtrExportData_st(Structure): - pass - -struct_CUmemPoolPtrExportData_st._pack_ = 1 # source:False -struct_CUmemPoolPtrExportData_st._fields_ = [ - ('reserved', ctypes.c_ubyte * 64), -] - -CUmemPoolPtrExportData_v1 = struct_CUmemPoolPtrExportData_st -CUmemPoolPtrExportData = struct_CUmemPoolPtrExportData_st -class struct_CUDA_MEM_ALLOC_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_MEM_ALLOC_NODE_PARAMS_st._pack_ = 1 # source:False -struct_CUDA_MEM_ALLOC_NODE_PARAMS_st._fields_ = [ - ('poolProps', CUmemPoolProps), - ('accessDescs', ctypes.POINTER(struct_CUmemAccessDesc_st)), - ('accessDescCount', ctypes.c_uint64), - ('bytesize', ctypes.c_uint64), - ('dptr', ctypes.c_uint64), -] - -CUDA_MEM_ALLOC_NODE_PARAMS = struct_CUDA_MEM_ALLOC_NODE_PARAMS_st - -# values for enumeration 'CUgraphMem_attribute_enum' -CUgraphMem_attribute_enum__enumvalues = { - 0: 'CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT', - 1: 'CU_GRAPH_MEM_ATTR_USED_MEM_HIGH', - 2: 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT', - 3: 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH', -} -CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT = 0 -CU_GRAPH_MEM_ATTR_USED_MEM_HIGH = 1 -CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT = 2 -CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH = 3 -CUgraphMem_attribute_enum = ctypes.c_uint32 # enum -CUgraphMem_attribute = CUgraphMem_attribute_enum -CUgraphMem_attribute__enumvalues = CUgraphMem_attribute_enum__enumvalues - -# values for enumeration 'CUflushGPUDirectRDMAWritesOptions_enum' -CUflushGPUDirectRDMAWritesOptions_enum__enumvalues = { - 1: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST', - 2: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST = 1 -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS = 2 -CUflushGPUDirectRDMAWritesOptions_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesOptions = CUflushGPUDirectRDMAWritesOptions_enum -CUflushGPUDirectRDMAWritesOptions__enumvalues = CUflushGPUDirectRDMAWritesOptions_enum__enumvalues - -# values for enumeration 'CUGPUDirectRDMAWritesOrdering_enum' -CUGPUDirectRDMAWritesOrdering_enum__enumvalues = { - 0: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE', - 100: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER', - 200: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES', -} -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE = 0 -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER = 100 -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES = 200 -CUGPUDirectRDMAWritesOrdering_enum = ctypes.c_uint32 # enum -CUGPUDirectRDMAWritesOrdering = CUGPUDirectRDMAWritesOrdering_enum -CUGPUDirectRDMAWritesOrdering__enumvalues = CUGPUDirectRDMAWritesOrdering_enum__enumvalues - -# values for enumeration 'CUflushGPUDirectRDMAWritesScope_enum' -CUflushGPUDirectRDMAWritesScope_enum__enumvalues = { - 100: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER', - 200: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER = 100 -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES = 200 -CUflushGPUDirectRDMAWritesScope_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesScope = CUflushGPUDirectRDMAWritesScope_enum -CUflushGPUDirectRDMAWritesScope__enumvalues = CUflushGPUDirectRDMAWritesScope_enum__enumvalues - -# values for enumeration 'CUflushGPUDirectRDMAWritesTarget_enum' -CUflushGPUDirectRDMAWritesTarget_enum__enumvalues = { - 0: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX = 0 -CUflushGPUDirectRDMAWritesTarget_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesTarget = CUflushGPUDirectRDMAWritesTarget_enum -CUflushGPUDirectRDMAWritesTarget__enumvalues = CUflushGPUDirectRDMAWritesTarget_enum__enumvalues - -# values for enumeration 'CUgraphDebugDot_flags_enum' -CUgraphDebugDot_flags_enum__enumvalues = { - 1: 'CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE', - 2: 'CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES', - 4: 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS', - 8: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS', - 16: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS', - 32: 'CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS', - 64: 'CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS', - 128: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS', - 256: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS', - 512: 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES', - 1024: 'CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES', - 2048: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS', - 4096: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS', - 8192: 'CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS', - 16384: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO', -} -CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE = 1 -CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES = 2 -CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS = 4 -CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS = 8 -CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS = 16 -CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS = 32 -CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS = 64 -CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS = 128 -CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS = 256 -CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES = 512 -CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES = 1024 -CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS = 2048 -CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS = 4096 -CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS = 8192 -CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO = 16384 -CUgraphDebugDot_flags_enum = ctypes.c_uint32 # enum -CUgraphDebugDot_flags = CUgraphDebugDot_flags_enum -CUgraphDebugDot_flags__enumvalues = CUgraphDebugDot_flags_enum__enumvalues - -# values for enumeration 'CUuserObject_flags_enum' -CUuserObject_flags_enum__enumvalues = { - 1: 'CU_USER_OBJECT_NO_DESTRUCTOR_SYNC', -} -CU_USER_OBJECT_NO_DESTRUCTOR_SYNC = 1 -CUuserObject_flags_enum = ctypes.c_uint32 # enum -CUuserObject_flags = CUuserObject_flags_enum -CUuserObject_flags__enumvalues = CUuserObject_flags_enum__enumvalues - -# values for enumeration 'CUuserObjectRetain_flags_enum' -CUuserObjectRetain_flags_enum__enumvalues = { - 1: 'CU_GRAPH_USER_OBJECT_MOVE', -} -CU_GRAPH_USER_OBJECT_MOVE = 1 -CUuserObjectRetain_flags_enum = ctypes.c_uint32 # enum -CUuserObjectRetain_flags = CUuserObjectRetain_flags_enum -CUuserObjectRetain_flags__enumvalues = CUuserObjectRetain_flags_enum__enumvalues - -# values for enumeration 'CUgraphInstantiate_flags_enum' -CUgraphInstantiate_flags_enum__enumvalues = { - 1: 'CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH', - 2: 'CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD', - 4: 'CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH', - 8: 'CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY', -} -CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH = 1 -CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD = 2 -CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH = 4 -CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY = 8 -CUgraphInstantiate_flags_enum = ctypes.c_uint32 # enum -CUgraphInstantiate_flags = CUgraphInstantiate_flags_enum -CUgraphInstantiate_flags__enumvalues = CUgraphInstantiate_flags_enum__enumvalues -try: - cuGetErrorString = _libraries['libcuda.so'].cuGetErrorString - cuGetErrorString.restype = CUresult - cuGetErrorString.argtypes = [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - cuGetErrorName = _libraries['libcuda.so'].cuGetErrorName - cuGetErrorName.restype = CUresult - cuGetErrorName.argtypes = [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - cuInit = _libraries['libcuda.so'].cuInit - cuInit.restype = CUresult - cuInit.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - cuDriverGetVersion = _libraries['libcuda.so'].cuDriverGetVersion - cuDriverGetVersion.restype = CUresult - cuDriverGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDeviceGet = _libraries['libcuda.so'].cuDeviceGet - cuDeviceGet.restype = CUresult - cuDeviceGet.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32] -except AttributeError: - pass -try: - cuDeviceGetCount = _libraries['libcuda.so'].cuDeviceGetCount - cuDeviceGetCount.restype = CUresult - cuDeviceGetCount.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDeviceGetName = _libraries['libcuda.so'].cuDeviceGetName - cuDeviceGetName.restype = CUresult - cuDeviceGetName.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetUuid = _libraries['libcuda.so'].cuDeviceGetUuid - cuDeviceGetUuid.restype = CUresult - cuDeviceGetUuid.argtypes = [ctypes.POINTER(struct_CUuuid_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetUuid_v2 = _libraries['libcuda.so'].cuDeviceGetUuid_v2 - cuDeviceGetUuid_v2.restype = CUresult - cuDeviceGetUuid_v2.argtypes = [ctypes.POINTER(struct_CUuuid_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetLuid = _libraries['libcuda.so'].cuDeviceGetLuid - cuDeviceGetLuid.restype = CUresult - cuDeviceGetLuid.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32), CUdevice] -except AttributeError: - pass -try: - cuDeviceTotalMem_v2 = _libraries['libcuda.so'].cuDeviceTotalMem_v2 - cuDeviceTotalMem_v2.restype = CUresult - cuDeviceTotalMem_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetTexture1DLinearMaxWidth = _libraries['libcuda.so'].cuDeviceGetTexture1DLinearMaxWidth - cuDeviceGetTexture1DLinearMaxWidth.restype = CUresult - cuDeviceGetTexture1DLinearMaxWidth.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUarray_format, ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetAttribute = _libraries['libcuda.so'].cuDeviceGetAttribute - cuDeviceGetAttribute.restype = CUresult - cuDeviceGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice_attribute, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetNvSciSyncAttributes = _libraries['libcuda.so'].cuDeviceGetNvSciSyncAttributes - cuDeviceGetNvSciSyncAttributes.restype = CUresult - cuDeviceGetNvSciSyncAttributes.argtypes = [ctypes.POINTER(None), CUdevice, ctypes.c_int32] -except AttributeError: - pass -try: - cuDeviceSetMemPool = _libraries['libcuda.so'].cuDeviceSetMemPool - cuDeviceSetMemPool.restype = CUresult - cuDeviceSetMemPool.argtypes = [CUdevice, CUmemoryPool] -except AttributeError: - pass -try: - cuDeviceGetMemPool = _libraries['libcuda.so'].cuDeviceGetMemPool - cuDeviceGetMemPool.restype = CUresult - cuDeviceGetMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetDefaultMemPool = _libraries['libcuda.so'].cuDeviceGetDefaultMemPool - cuDeviceGetDefaultMemPool.restype = CUresult - cuDeviceGetDefaultMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetExecAffinitySupport = _libraries['libcuda.so'].cuDeviceGetExecAffinitySupport - cuDeviceGetExecAffinitySupport.restype = CUresult - cuDeviceGetExecAffinitySupport.argtypes = [ctypes.POINTER(ctypes.c_int32), CUexecAffinityType, CUdevice] -except AttributeError: - pass -try: - cuFlushGPUDirectRDMAWrites = _libraries['libcuda.so'].cuFlushGPUDirectRDMAWrites - cuFlushGPUDirectRDMAWrites.restype = CUresult - cuFlushGPUDirectRDMAWrites.argtypes = [CUflushGPUDirectRDMAWritesTarget, CUflushGPUDirectRDMAWritesScope] -except AttributeError: - pass -try: - cuDeviceGetProperties = _libraries['libcuda.so'].cuDeviceGetProperties - cuDeviceGetProperties.restype = CUresult - cuDeviceGetProperties.argtypes = [ctypes.POINTER(struct_CUdevprop_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceComputeCapability = _libraries['libcuda.so'].cuDeviceComputeCapability - cuDeviceComputeCapability.restype = CUresult - cuDeviceComputeCapability.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRetain = _libraries['libcuda.so'].cuDevicePrimaryCtxRetain - cuDevicePrimaryCtxRetain.restype = CUresult - cuDevicePrimaryCtxRetain.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRelease_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxRelease_v2 - cuDevicePrimaryCtxRelease_v2.restype = CUresult - cuDevicePrimaryCtxRelease_v2.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxSetFlags_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxSetFlags_v2 - cuDevicePrimaryCtxSetFlags_v2.restype = CUresult - cuDevicePrimaryCtxSetFlags_v2.argtypes = [CUdevice, ctypes.c_uint32] -except AttributeError: - pass -try: - cuDevicePrimaryCtxGetState = _libraries['libcuda.so'].cuDevicePrimaryCtxGetState - cuDevicePrimaryCtxGetState.restype = CUresult - cuDevicePrimaryCtxGetState.argtypes = [CUdevice, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDevicePrimaryCtxReset_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxReset_v2 - cuDevicePrimaryCtxReset_v2.restype = CUresult - cuDevicePrimaryCtxReset_v2.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuCtxCreate_v2 = _libraries['libcuda.so'].cuCtxCreate_v2 - cuCtxCreate_v2.restype = CUresult - cuCtxCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuCtxCreate_v3 = _libraries['libcuda.so'].cuCtxCreate_v3 - cuCtxCreate_v3.restype = CUresult - cuCtxCreate_v3.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.POINTER(struct_CUexecAffinityParam_st), ctypes.c_int32, ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuCtxDestroy_v2 = _libraries['libcuda.so'].cuCtxDestroy_v2 - cuCtxDestroy_v2.restype = CUresult - cuCtxDestroy_v2.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPushCurrent_v2 = _libraries['libcuda.so'].cuCtxPushCurrent_v2 - cuCtxPushCurrent_v2.restype = CUresult - cuCtxPushCurrent_v2.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPopCurrent_v2 = _libraries['libcuda.so'].cuCtxPopCurrent_v2 - cuCtxPopCurrent_v2.restype = CUresult - cuCtxPopCurrent_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxSetCurrent = _libraries['libcuda.so'].cuCtxSetCurrent - cuCtxSetCurrent.restype = CUresult - cuCtxSetCurrent.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxGetCurrent = _libraries['libcuda.so'].cuCtxGetCurrent - cuCtxGetCurrent.restype = CUresult - cuCtxGetCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxGetDevice = _libraries['libcuda.so'].cuCtxGetDevice - cuCtxGetDevice.restype = CUresult - cuCtxGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuCtxGetFlags = _libraries['libcuda.so'].cuCtxGetFlags - cuCtxGetFlags.restype = CUresult - cuCtxGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuCtxGetId = _libraries['libcuda.so'].cuCtxGetId - cuCtxGetId.restype = CUresult - cuCtxGetId.argtypes = [CUcontext, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuCtxSynchronize = _libraries['libcuda.so'].cuCtxSynchronize - cuCtxSynchronize.restype = CUresult - cuCtxSynchronize.argtypes = [] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - cuCtxSetLimit = _libraries['libcuda.so'].cuCtxSetLimit - cuCtxSetLimit.restype = CUresult - cuCtxSetLimit.argtypes = [CUlimit, size_t] -except AttributeError: - pass -try: - cuCtxGetLimit = _libraries['libcuda.so'].cuCtxGetLimit - cuCtxGetLimit.restype = CUresult - cuCtxGetLimit.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUlimit] -except AttributeError: - pass -try: - cuCtxGetCacheConfig = _libraries['libcuda.so'].cuCtxGetCacheConfig - cuCtxGetCacheConfig.restype = CUresult - cuCtxGetCacheConfig.argtypes = [ctypes.POINTER(CUfunc_cache_enum)] -except AttributeError: - pass -try: - cuCtxSetCacheConfig = _libraries['libcuda.so'].cuCtxSetCacheConfig - cuCtxSetCacheConfig.restype = CUresult - cuCtxSetCacheConfig.argtypes = [CUfunc_cache] -except AttributeError: - pass -try: - cuCtxGetSharedMemConfig = _libraries['libcuda.so'].cuCtxGetSharedMemConfig - cuCtxGetSharedMemConfig.restype = CUresult - cuCtxGetSharedMemConfig.argtypes = [ctypes.POINTER(CUsharedconfig_enum)] -except AttributeError: - pass -try: - cuCtxSetSharedMemConfig = _libraries['libcuda.so'].cuCtxSetSharedMemConfig - cuCtxSetSharedMemConfig.restype = CUresult - cuCtxSetSharedMemConfig.argtypes = [CUsharedconfig] -except AttributeError: - pass -try: - cuCtxGetApiVersion = _libraries['libcuda.so'].cuCtxGetApiVersion - cuCtxGetApiVersion.restype = CUresult - cuCtxGetApiVersion.argtypes = [CUcontext, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuCtxGetStreamPriorityRange = _libraries['libcuda.so'].cuCtxGetStreamPriorityRange - cuCtxGetStreamPriorityRange.restype = CUresult - cuCtxGetStreamPriorityRange.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuCtxResetPersistingL2Cache = _libraries['libcuda.so'].cuCtxResetPersistingL2Cache - cuCtxResetPersistingL2Cache.restype = CUresult - cuCtxResetPersistingL2Cache.argtypes = [] -except AttributeError: - pass -try: - cuCtxGetExecAffinity = _libraries['libcuda.so'].cuCtxGetExecAffinity - cuCtxGetExecAffinity.restype = CUresult - cuCtxGetExecAffinity.argtypes = [ctypes.POINTER(struct_CUexecAffinityParam_st), CUexecAffinityType] -except AttributeError: - pass -try: - cuCtxAttach = _libraries['libcuda.so'].cuCtxAttach - cuCtxAttach.restype = CUresult - cuCtxAttach.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuCtxDetach = _libraries['libcuda.so'].cuCtxDetach - cuCtxDetach.restype = CUresult - cuCtxDetach.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuModuleLoad = _libraries['libcuda.so'].cuModuleLoad - cuModuleLoad.restype = CUresult - cuModuleLoad.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleLoadData = _libraries['libcuda.so'].cuModuleLoadData - cuModuleLoadData.restype = CUresult - cuModuleLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuModuleLoadDataEx = _libraries['libcuda.so'].cuModuleLoadDataEx - cuModuleLoadDataEx.restype = CUresult - cuModuleLoadDataEx.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuModuleLoadFatBinary = _libraries['libcuda.so'].cuModuleLoadFatBinary - cuModuleLoadFatBinary.restype = CUresult - cuModuleLoadFatBinary.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuModuleUnload = _libraries['libcuda.so'].cuModuleUnload - cuModuleUnload.restype = CUresult - cuModuleUnload.argtypes = [CUmodule] -except AttributeError: - pass - -# values for enumeration 'CUmoduleLoadingMode_enum' -CUmoduleLoadingMode_enum__enumvalues = { - 1: 'CU_MODULE_EAGER_LOADING', - 2: 'CU_MODULE_LAZY_LOADING', -} -CU_MODULE_EAGER_LOADING = 1 -CU_MODULE_LAZY_LOADING = 2 -CUmoduleLoadingMode_enum = ctypes.c_uint32 # enum -CUmoduleLoadingMode = CUmoduleLoadingMode_enum -CUmoduleLoadingMode__enumvalues = CUmoduleLoadingMode_enum__enumvalues -try: - cuModuleGetLoadingMode = _libraries['libcuda.so'].cuModuleGetLoadingMode - cuModuleGetLoadingMode.restype = CUresult - cuModuleGetLoadingMode.argtypes = [ctypes.POINTER(CUmoduleLoadingMode_enum)] -except AttributeError: - pass -try: - cuModuleGetFunction = _libraries['libcuda.so'].cuModuleGetFunction - cuModuleGetFunction.restype = CUresult - cuModuleGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUfunc_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleGetGlobal_v2 = _libraries['libcuda.so'].cuModuleGetGlobal_v2 - cuModuleGetGlobal_v2.restype = CUresult - cuModuleGetGlobal_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLinkCreate_v2 = _libraries['libcuda.so'].cuLinkCreate_v2 - cuLinkCreate_v2.restype = CUresult - cuLinkCreate_v2.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_CUlinkState_st))] -except AttributeError: - pass -try: - cuLinkAddData_v2 = _libraries['libcuda.so'].cuLinkAddData_v2 - cuLinkAddData_v2.restype = CUresult - cuLinkAddData_v2.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkAddFile_v2 = _libraries['libcuda.so'].cuLinkAddFile_v2 - cuLinkAddFile_v2.restype = CUresult - cuLinkAddFile_v2.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkComplete = _libraries['libcuda.so'].cuLinkComplete - cuLinkComplete.restype = CUresult - cuLinkComplete.argtypes = [CUlinkState, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuLinkDestroy = _libraries['libcuda.so'].cuLinkDestroy - cuLinkDestroy.restype = CUresult - cuLinkDestroy.argtypes = [CUlinkState] -except AttributeError: - pass -try: - cuModuleGetTexRef = _libraries['libcuda.so'].cuModuleGetTexRef - cuModuleGetTexRef.restype = CUresult - cuModuleGetTexRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUtexref_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleGetSurfRef = _libraries['libcuda.so'].cuModuleGetSurfRef - cuModuleGetSurfRef.restype = CUresult - cuModuleGetSurfRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUsurfref_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryLoadData = _libraries['libcuda.so'].cuLibraryLoadData - cuLibraryLoadData.restype = CUresult - cuLibraryLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUlib_st)), ctypes.POINTER(None), ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLibraryLoadFromFile = _libraries['libcuda.so'].cuLibraryLoadFromFile - cuLibraryLoadFromFile.restype = CUresult - cuLibraryLoadFromFile.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUlib_st)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLibraryUnload = _libraries['libcuda.so'].cuLibraryUnload - cuLibraryUnload.restype = CUresult - cuLibraryUnload.argtypes = [CUlibrary] -except AttributeError: - pass -try: - cuLibraryGetKernel = _libraries['libcuda.so'].cuLibraryGetKernel - cuLibraryGetKernel.restype = CUresult - cuLibraryGetKernel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUkern_st)), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetModule = _libraries['libcuda.so'].cuLibraryGetModule - cuLibraryGetModule.restype = CUresult - cuLibraryGetModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), CUlibrary] -except AttributeError: - pass -try: - cuKernelGetFunction = _libraries['libcuda.so'].cuKernelGetFunction - cuKernelGetFunction.restype = CUresult - cuKernelGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUfunc_st)), CUkernel] -except AttributeError: - pass -try: - cuLibraryGetGlobal = _libraries['libcuda.so'].cuLibraryGetGlobal - cuLibraryGetGlobal.restype = CUresult - cuLibraryGetGlobal.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetManaged = _libraries['libcuda.so'].cuLibraryGetManaged - cuLibraryGetManaged.restype = CUresult - cuLibraryGetManaged.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetUnifiedFunction = _libraries['libcuda.so'].cuLibraryGetUnifiedFunction - cuLibraryGetUnifiedFunction.restype = CUresult - cuLibraryGetUnifiedFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuKernelGetAttribute = _libraries['libcuda.so'].cuKernelGetAttribute - cuKernelGetAttribute.restype = CUresult - cuKernelGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUkernel, CUdevice] -except AttributeError: - pass -try: - cuKernelSetAttribute = _libraries['libcuda.so'].cuKernelSetAttribute - cuKernelSetAttribute.restype = CUresult - cuKernelSetAttribute.argtypes = [CUfunction_attribute, ctypes.c_int32, CUkernel, CUdevice] -except AttributeError: - pass -try: - cuKernelSetCacheConfig = _libraries['libcuda.so'].cuKernelSetCacheConfig - cuKernelSetCacheConfig.restype = CUresult - cuKernelSetCacheConfig.argtypes = [CUkernel, CUfunc_cache, CUdevice] -except AttributeError: - pass -try: - cuMemGetInfo_v2 = _libraries['libcuda.so'].cuMemGetInfo_v2 - cuMemGetInfo_v2.restype = CUresult - cuMemGetInfo_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuMemAlloc_v2 = _libraries['libcuda.so'].cuMemAlloc_v2 - cuMemAlloc_v2.restype = CUresult - cuMemAlloc_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t] -except AttributeError: - pass -try: - cuMemAllocPitch_v2 = _libraries['libcuda.so'].cuMemAllocPitch_v2 - cuMemAllocPitch_v2.restype = CUresult - cuMemAllocPitch_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemFree_v2 = _libraries['libcuda.so'].cuMemFree_v2 - cuMemFree_v2.restype = CUresult - cuMemFree_v2.argtypes = [CUdeviceptr] -except AttributeError: - pass -try: - cuMemGetAddressRange_v2 = _libraries['libcuda.so'].cuMemGetAddressRange_v2 - cuMemGetAddressRange_v2.restype = CUresult - cuMemGetAddressRange_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUdeviceptr] -except AttributeError: - pass -try: - cuMemAllocHost_v2 = _libraries['libcuda.so'].cuMemAllocHost_v2 - cuMemAllocHost_v2.restype = CUresult - cuMemAllocHost_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - cuMemFreeHost = _libraries['libcuda.so'].cuMemFreeHost - cuMemFreeHost.restype = CUresult - cuMemFreeHost.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemHostAlloc = _libraries['libcuda.so'].cuMemHostAlloc - cuMemHostAlloc.restype = CUresult - cuMemHostAlloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetDevicePointer_v2 = _libraries['libcuda.so'].cuMemHostGetDevicePointer_v2 - cuMemHostGetDevicePointer_v2.restype = CUresult - cuMemHostGetDevicePointer_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetFlags = _libraries['libcuda.so'].cuMemHostGetFlags - cuMemHostGetFlags.restype = CUresult - cuMemHostGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemAllocManaged = _libraries['libcuda.so'].cuMemAllocManaged - cuMemAllocManaged.restype = CUresult - cuMemAllocManaged.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuDeviceGetByPCIBusId = _libraries['libcuda.so'].cuDeviceGetByPCIBusId - cuDeviceGetByPCIBusId.restype = CUresult - cuDeviceGetByPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuDeviceGetPCIBusId = _libraries['libcuda.so'].cuDeviceGetPCIBusId - cuDeviceGetPCIBusId.restype = CUresult - cuDeviceGetPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] -except AttributeError: - pass -try: - cuIpcGetEventHandle = _libraries['libcuda.so'].cuIpcGetEventHandle - cuIpcGetEventHandle.restype = CUresult - cuIpcGetEventHandle.argtypes = [ctypes.POINTER(struct_CUipcEventHandle_st), CUevent] -except AttributeError: - pass -try: - cuIpcOpenEventHandle = _libraries['libcuda.so'].cuIpcOpenEventHandle - cuIpcOpenEventHandle.restype = CUresult - cuIpcOpenEventHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUevent_st)), CUipcEventHandle] -except AttributeError: - pass -try: - cuIpcGetMemHandle = _libraries['libcuda.so'].cuIpcGetMemHandle - cuIpcGetMemHandle.restype = CUresult - cuIpcGetMemHandle.argtypes = [ctypes.POINTER(struct_CUipcMemHandle_st), CUdeviceptr] -except AttributeError: - pass -try: - cuIpcOpenMemHandle_v2 = _libraries['libcuda.so'].cuIpcOpenMemHandle_v2 - cuIpcOpenMemHandle_v2.restype = CUresult - cuIpcOpenMemHandle_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUipcMemHandle, ctypes.c_uint32] -except AttributeError: - pass -try: - cuIpcCloseMemHandle = _libraries['libcuda.so'].cuIpcCloseMemHandle - cuIpcCloseMemHandle.restype = CUresult - cuIpcCloseMemHandle.argtypes = [CUdeviceptr] -except AttributeError: - pass -try: - cuMemHostRegister_v2 = _libraries['libcuda.so'].cuMemHostRegister_v2 - cuMemHostRegister_v2.restype = CUresult - cuMemHostRegister_v2.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostUnregister = _libraries['libcuda.so'].cuMemHostUnregister - cuMemHostUnregister.restype = CUresult - cuMemHostUnregister.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemcpy_ptds = _libraries['libcuda.so'].cuMemcpy_ptds - cuMemcpy_ptds.restype = CUresult - cuMemcpy_ptds.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyPeer_ptds = _libraries['libcuda.so'].cuMemcpyPeer_ptds - cuMemcpyPeer_ptds.restype = CUresult - cuMemcpyPeer_ptds.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyHtoD_v2_ptds - cuMemcpyHtoD_v2_ptds.restype = CUresult - cuMemcpyHtoD_v2_ptds.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyDtoH_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoH_v2_ptds - cuMemcpyDtoH_v2_ptds.restype = CUresult - cuMemcpyDtoH_v2_ptds.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoD_v2_ptds - cuMemcpyDtoD_v2_ptds.restype = CUresult - cuMemcpyDtoD_v2_ptds.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoA_v2_ptds - cuMemcpyDtoA_v2_ptds.restype = CUresult - cuMemcpyDtoA_v2_ptds.argtypes = [CUarray, size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoD_v2_ptds - cuMemcpyAtoD_v2_ptds.restype = CUresult - cuMemcpyAtoD_v2_ptds.argtypes = [CUdeviceptr, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyHtoA_v2_ptds - cuMemcpyHtoA_v2_ptds.restype = CUresult - cuMemcpyHtoA_v2_ptds.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyAtoH_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoH_v2_ptds - cuMemcpyAtoH_v2_ptds.restype = CUresult - cuMemcpyAtoH_v2_ptds.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoA_v2_ptds - cuMemcpyAtoA_v2_ptds.restype = CUresult - cuMemcpyAtoA_v2_ptds.argtypes = [CUarray, size_t, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpy2D_v2_ptds = _libraries['libcuda.so'].cuMemcpy2D_v2_ptds - cuMemcpy2D_v2_ptds.restype = CUresult - cuMemcpy2D_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned_v2_ptds = _libraries['libcuda.so'].cuMemcpy2DUnaligned_v2_ptds - cuMemcpy2DUnaligned_v2_ptds.restype = CUresult - cuMemcpy2DUnaligned_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy3D_v2_ptds = _libraries['libcuda.so'].cuMemcpy3D_v2_ptds - cuMemcpy3D_v2_ptds.restype = CUresult - cuMemcpy3D_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuMemcpy3DPeer_ptds = _libraries['libcuda.so'].cuMemcpy3DPeer_ptds - cuMemcpy3DPeer_ptds.restype = CUresult - cuMemcpy3DPeer_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st)] -except AttributeError: - pass -try: - cuMemcpyAsync_ptsz = _libraries['libcuda.so'].cuMemcpyAsync_ptsz - cuMemcpyAsync_ptsz.restype = CUresult - cuMemcpyAsync_ptsz.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyPeerAsync_ptsz = _libraries['libcuda.so'].cuMemcpyPeerAsync_ptsz - cuMemcpyPeerAsync_ptsz.restype = CUresult - cuMemcpyPeerAsync_ptsz.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyHtoDAsync_v2_ptsz - cuMemcpyHtoDAsync_v2_ptsz.restype = CUresult - cuMemcpyHtoDAsync_v2_ptsz.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyDtoHAsync_v2_ptsz - cuMemcpyDtoHAsync_v2_ptsz.restype = CUresult - cuMemcpyDtoHAsync_v2_ptsz.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyDtoDAsync_v2_ptsz - cuMemcpyDtoDAsync_v2_ptsz.restype = CUresult - cuMemcpyDtoDAsync_v2_ptsz.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyHtoAAsync_v2_ptsz - cuMemcpyHtoAAsync_v2_ptsz.restype = CUresult - cuMemcpyHtoAAsync_v2_ptsz.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyAtoHAsync_v2_ptsz - cuMemcpyAtoHAsync_v2_ptsz.restype = CUresult - cuMemcpyAtoHAsync_v2_ptsz.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpy2DAsync_v2_ptsz - cuMemcpy2DAsync_v2_ptsz.restype = CUresult - cuMemcpy2DAsync_v2_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpy3DAsync_v2_ptsz - cuMemcpy3DAsync_v2_ptsz.restype = CUresult - cuMemcpy3DAsync_v2_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DPeerAsync_ptsz = _libraries['libcuda.so'].cuMemcpy3DPeerAsync_ptsz - cuMemcpy3DPeerAsync_ptsz.restype = CUresult - cuMemcpy3DPeerAsync_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8_v2_ptds = _libraries['libcuda.so'].cuMemsetD8_v2_ptds - cuMemsetD8_v2_ptds.restype = CUresult - cuMemsetD8_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - cuMemsetD16_v2_ptds = _libraries['libcuda.so'].cuMemsetD16_v2_ptds - cuMemsetD16_v2_ptds.restype = CUresult - cuMemsetD16_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - cuMemsetD32_v2_ptds = _libraries['libcuda.so'].cuMemsetD32_v2_ptds - cuMemsetD32_v2_ptds.restype = CUresult - cuMemsetD32_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t] -except AttributeError: - pass -try: - cuMemsetD2D8_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D8_v2_ptds - cuMemsetD2D8_v2_ptds.restype = CUresult - cuMemsetD2D8_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D16_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D16_v2_ptds - cuMemsetD2D16_v2_ptds.restype = CUresult - cuMemsetD2D16_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D32_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D32_v2_ptds - cuMemsetD2D32_v2_ptds.restype = CUresult - cuMemsetD2D32_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD8Async_ptsz = _libraries['libcuda.so'].cuMemsetD8Async_ptsz - cuMemsetD8Async_ptsz.restype = CUresult - cuMemsetD8Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD16Async_ptsz = _libraries['libcuda.so'].cuMemsetD16Async_ptsz - cuMemsetD16Async_ptsz.restype = CUresult - cuMemsetD16Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD32Async_ptsz = _libraries['libcuda.so'].cuMemsetD32Async_ptsz - cuMemsetD32Async_ptsz.restype = CUresult - cuMemsetD32Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D8Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D8Async_ptsz - cuMemsetD2D8Async_ptsz.restype = CUresult - cuMemsetD2D8Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D16Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D16Async_ptsz - cuMemsetD2D16Async_ptsz.restype = CUresult - cuMemsetD2D16Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D32Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D32Async_ptsz - cuMemsetD2D32Async_ptsz.restype = CUresult - cuMemsetD2D32Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuArrayCreate_v2 = _libraries['libcuda.so'].cuArrayCreate_v2 - cuArrayCreate_v2.restype = CUresult - cuArrayCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st)] -except AttributeError: - pass -try: - cuArrayGetDescriptor_v2 = _libraries['libcuda.so'].cuArrayGetDescriptor_v2 - cuArrayGetDescriptor_v2.restype = CUresult - cuArrayGetDescriptor_v2.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUarray] -except AttributeError: - pass -try: - cuArrayGetSparseProperties = _libraries['libcuda.so'].cuArrayGetSparseProperties - cuArrayGetSparseProperties.restype = CUresult - cuArrayGetSparseProperties.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_SPARSE_PROPERTIES_st), CUarray] -except AttributeError: - pass -try: - cuMipmappedArrayGetSparseProperties = _libraries['libcuda.so'].cuMipmappedArrayGetSparseProperties - cuMipmappedArrayGetSparseProperties.restype = CUresult - cuMipmappedArrayGetSparseProperties.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_SPARSE_PROPERTIES_st), CUmipmappedArray] -except AttributeError: - pass -try: - cuArrayGetMemoryRequirements = _libraries['libcuda.so'].cuArrayGetMemoryRequirements - cuArrayGetMemoryRequirements.restype = CUresult - cuArrayGetMemoryRequirements.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st), CUarray, CUdevice] -except AttributeError: - pass -try: - cuMipmappedArrayGetMemoryRequirements = _libraries['libcuda.so'].cuMipmappedArrayGetMemoryRequirements - cuMipmappedArrayGetMemoryRequirements.restype = CUresult - cuMipmappedArrayGetMemoryRequirements.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st), CUmipmappedArray, CUdevice] -except AttributeError: - pass -try: - cuArrayGetPlane = _libraries['libcuda.so'].cuArrayGetPlane - cuArrayGetPlane.restype = CUresult - cuArrayGetPlane.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuArrayDestroy = _libraries['libcuda.so'].cuArrayDestroy - cuArrayDestroy.restype = CUresult - cuArrayDestroy.argtypes = [CUarray] -except AttributeError: - pass -try: - cuArray3DCreate_v2 = _libraries['libcuda.so'].cuArray3DCreate_v2 - cuArray3DCreate_v2.restype = CUresult - cuArray3DCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st)] -except AttributeError: - pass -try: - cuArray3DGetDescriptor_v2 = _libraries['libcuda.so'].cuArray3DGetDescriptor_v2 - cuArray3DGetDescriptor_v2.restype = CUresult - cuArray3DGetDescriptor_v2.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st), CUarray] -except AttributeError: - pass -try: - cuMipmappedArrayCreate = _libraries['libcuda.so'].cuMipmappedArrayCreate - cuMipmappedArrayCreate.restype = CUresult - cuMipmappedArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMipmappedArrayGetLevel = _libraries['libcuda.so'].cuMipmappedArrayGetLevel - cuMipmappedArrayGetLevel.restype = CUresult - cuMipmappedArrayGetLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUmipmappedArray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMipmappedArrayDestroy = _libraries['libcuda.so'].cuMipmappedArrayDestroy - cuMipmappedArrayDestroy.restype = CUresult - cuMipmappedArrayDestroy.argtypes = [CUmipmappedArray] -except AttributeError: - pass -try: - cuMemGetHandleForAddressRange = _libraries['libcuda.so'].cuMemGetHandleForAddressRange - cuMemGetHandleForAddressRange.restype = CUresult - cuMemGetHandleForAddressRange.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUmemRangeHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemAddressReserve = _libraries['libcuda.so'].cuMemAddressReserve - cuMemAddressReserve.restype = CUresult - cuMemAddressReserve.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, size_t, CUdeviceptr, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemAddressFree = _libraries['libcuda.so'].cuMemAddressFree - cuMemAddressFree.restype = CUresult - cuMemAddressFree.argtypes = [CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemCreate = _libraries['libcuda.so'].cuMemCreate - cuMemCreate.restype = CUresult - cuMemCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, ctypes.POINTER(struct_CUmemAllocationProp_st), ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemRelease = _libraries['libcuda.so'].cuMemRelease - cuMemRelease.restype = CUresult - cuMemRelease.argtypes = [CUmemGenericAllocationHandle] -except AttributeError: - pass -try: - cuMemMap = _libraries['libcuda.so'].cuMemMap - cuMemMap.restype = CUresult - cuMemMap.argtypes = [CUdeviceptr, size_t, size_t, CUmemGenericAllocationHandle, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemMapArrayAsync_ptsz = _libraries['libcuda.so'].cuMemMapArrayAsync_ptsz - cuMemMapArrayAsync_ptsz.restype = CUresult - cuMemMapArrayAsync_ptsz.argtypes = [ctypes.POINTER(struct_CUarrayMapInfo_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemUnmap = _libraries['libcuda.so'].cuMemUnmap - cuMemUnmap.restype = CUresult - cuMemUnmap.argtypes = [CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemSetAccess = _libraries['libcuda.so'].cuMemSetAccess - cuMemSetAccess.restype = CUresult - cuMemSetAccess.argtypes = [CUdeviceptr, size_t, ctypes.POINTER(struct_CUmemAccessDesc_st), size_t] -except AttributeError: - pass -try: - cuMemGetAccess = _libraries['libcuda.so'].cuMemGetAccess - cuMemGetAccess.restype = CUresult - cuMemGetAccess.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUmemLocation_st), CUdeviceptr] -except AttributeError: - pass -try: - cuMemExportToShareableHandle = _libraries['libcuda.so'].cuMemExportToShareableHandle - cuMemExportToShareableHandle.restype = CUresult - cuMemExportToShareableHandle.argtypes = [ctypes.POINTER(None), CUmemGenericAllocationHandle, CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemImportFromShareableHandle = _libraries['libcuda.so'].cuMemImportFromShareableHandle - cuMemImportFromShareableHandle.restype = CUresult - cuMemImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None), CUmemAllocationHandleType] -except AttributeError: - pass -try: - cuMemGetAllocationGranularity = _libraries['libcuda.so'].cuMemGetAllocationGranularity - cuMemGetAllocationGranularity.restype = CUresult - cuMemGetAllocationGranularity.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUmemAllocationProp_st), CUmemAllocationGranularity_flags] -except AttributeError: - pass -try: - cuMemGetAllocationPropertiesFromHandle = _libraries['libcuda.so'].cuMemGetAllocationPropertiesFromHandle - cuMemGetAllocationPropertiesFromHandle.restype = CUresult - cuMemGetAllocationPropertiesFromHandle.argtypes = [ctypes.POINTER(struct_CUmemAllocationProp_st), CUmemGenericAllocationHandle] -except AttributeError: - pass -try: - cuMemRetainAllocationHandle = _libraries['libcuda.so'].cuMemRetainAllocationHandle - cuMemRetainAllocationHandle.restype = CUresult - cuMemRetainAllocationHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemFreeAsync_ptsz = _libraries['libcuda.so'].cuMemFreeAsync_ptsz - cuMemFreeAsync_ptsz.restype = CUresult - cuMemFreeAsync_ptsz.argtypes = [CUdeviceptr, CUstream] -except AttributeError: - pass -try: - cuMemAllocAsync_ptsz = _libraries['libcuda.so'].cuMemAllocAsync_ptsz - cuMemAllocAsync_ptsz.restype = CUresult - cuMemAllocAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUstream] -except AttributeError: - pass -try: - cuMemPoolTrimTo = _libraries['libcuda.so'].cuMemPoolTrimTo - cuMemPoolTrimTo.restype = CUresult - cuMemPoolTrimTo.argtypes = [CUmemoryPool, size_t] -except AttributeError: - pass -try: - cuMemPoolSetAttribute = _libraries['libcuda.so'].cuMemPoolSetAttribute - cuMemPoolSetAttribute.restype = CUresult - cuMemPoolSetAttribute.argtypes = [CUmemoryPool, CUmemPool_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemPoolGetAttribute = _libraries['libcuda.so'].cuMemPoolGetAttribute - cuMemPoolGetAttribute.restype = CUresult - cuMemPoolGetAttribute.argtypes = [CUmemoryPool, CUmemPool_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemPoolSetAccess = _libraries['libcuda.so'].cuMemPoolSetAccess - cuMemPoolSetAccess.restype = CUresult - cuMemPoolSetAccess.argtypes = [CUmemoryPool, ctypes.POINTER(struct_CUmemAccessDesc_st), size_t] -except AttributeError: - pass -try: - cuMemPoolGetAccess = _libraries['libcuda.so'].cuMemPoolGetAccess - cuMemPoolGetAccess.restype = CUresult - cuMemPoolGetAccess.argtypes = [ctypes.POINTER(CUmemAccess_flags_enum), CUmemoryPool, ctypes.POINTER(struct_CUmemLocation_st)] -except AttributeError: - pass -try: - cuMemPoolCreate = _libraries['libcuda.so'].cuMemPoolCreate - cuMemPoolCreate.restype = CUresult - cuMemPoolCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), ctypes.POINTER(struct_CUmemPoolProps_st)] -except AttributeError: - pass -try: - cuMemPoolDestroy = _libraries['libcuda.so'].cuMemPoolDestroy - cuMemPoolDestroy.restype = CUresult - cuMemPoolDestroy.argtypes = [CUmemoryPool] -except AttributeError: - pass -try: - cuMemAllocFromPoolAsync_ptsz = _libraries['libcuda.so'].cuMemAllocFromPoolAsync_ptsz - cuMemAllocFromPoolAsync_ptsz.restype = CUresult - cuMemAllocFromPoolAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUmemoryPool, CUstream] -except AttributeError: - pass -try: - cuMemPoolExportToShareableHandle = _libraries['libcuda.so'].cuMemPoolExportToShareableHandle - cuMemPoolExportToShareableHandle.restype = CUresult - cuMemPoolExportToShareableHandle.argtypes = [ctypes.POINTER(None), CUmemoryPool, CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemPoolImportFromShareableHandle = _libraries['libcuda.so'].cuMemPoolImportFromShareableHandle - cuMemPoolImportFromShareableHandle.restype = CUresult - cuMemPoolImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), ctypes.POINTER(None), CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemPoolExportPointer = _libraries['libcuda.so'].cuMemPoolExportPointer - cuMemPoolExportPointer.restype = CUresult - cuMemPoolExportPointer.argtypes = [ctypes.POINTER(struct_CUmemPoolPtrExportData_st), CUdeviceptr] -except AttributeError: - pass -try: - cuMemPoolImportPointer = _libraries['libcuda.so'].cuMemPoolImportPointer - cuMemPoolImportPointer.restype = CUresult - cuMemPoolImportPointer.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUmemoryPool, ctypes.POINTER(struct_CUmemPoolPtrExportData_st)] -except AttributeError: - pass -try: - cuPointerGetAttribute = _libraries['libcuda.so'].cuPointerGetAttribute - cuPointerGetAttribute.restype = CUresult - cuPointerGetAttribute.argtypes = [ctypes.POINTER(None), CUpointer_attribute, CUdeviceptr] -except AttributeError: - pass -try: - cuMemPrefetchAsync_ptsz = _libraries['libcuda.so'].cuMemPrefetchAsync_ptsz - cuMemPrefetchAsync_ptsz.restype = CUresult - cuMemPrefetchAsync_ptsz.argtypes = [CUdeviceptr, size_t, CUdevice, CUstream] -except AttributeError: - pass -try: - cuMemAdvise = _libraries['libcuda.so'].cuMemAdvise - cuMemAdvise.restype = CUresult - cuMemAdvise.argtypes = [CUdeviceptr, size_t, CUmem_advise, CUdevice] -except AttributeError: - pass -try: - cuMemRangeGetAttribute = _libraries['libcuda.so'].cuMemRangeGetAttribute - cuMemRangeGetAttribute.restype = CUresult - cuMemRangeGetAttribute.argtypes = [ctypes.POINTER(None), size_t, CUmem_range_attribute, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemRangeGetAttributes = _libraries['libcuda.so'].cuMemRangeGetAttributes - cuMemRangeGetAttributes.restype = CUresult - cuMemRangeGetAttributes.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(CUmem_range_attribute_enum), size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuPointerSetAttribute = _libraries['libcuda.so'].cuPointerSetAttribute - cuPointerSetAttribute.restype = CUresult - cuPointerSetAttribute.argtypes = [ctypes.POINTER(None), CUpointer_attribute, CUdeviceptr] -except AttributeError: - pass -try: - cuPointerGetAttributes = _libraries['libcuda.so'].cuPointerGetAttributes - cuPointerGetAttributes.restype = CUresult - cuPointerGetAttributes.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUpointer_attribute_enum), ctypes.POINTER(ctypes.POINTER(None)), CUdeviceptr] -except AttributeError: - pass -try: - cuStreamCreate = _libraries['libcuda.so'].cuStreamCreate - cuStreamCreate.restype = CUresult - cuStreamCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUstream_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamCreateWithPriority = _libraries['libcuda.so'].cuStreamCreateWithPriority - cuStreamCreateWithPriority.restype = CUresult - cuStreamCreateWithPriority.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUstream_st)), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - cuStreamGetPriority_ptsz = _libraries['libcuda.so'].cuStreamGetPriority_ptsz - cuStreamGetPriority_ptsz.restype = CUresult - cuStreamGetPriority_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuStreamGetFlags_ptsz = _libraries['libcuda.so'].cuStreamGetFlags_ptsz - cuStreamGetFlags_ptsz.restype = CUresult - cuStreamGetFlags_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuStreamGetId_ptsz = _libraries['libcuda.so'].cuStreamGetId_ptsz - cuStreamGetId_ptsz.restype = CUresult - cuStreamGetId_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCtx_ptsz = _libraries['libcuda.so'].cuStreamGetCtx_ptsz - cuStreamGetCtx_ptsz.restype = CUresult - cuStreamGetCtx_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuStreamWaitEvent_ptsz = _libraries['libcuda.so'].cuStreamWaitEvent_ptsz - cuStreamWaitEvent_ptsz.restype = CUresult - cuStreamWaitEvent_ptsz.argtypes = [CUstream, CUevent, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAddCallback_ptsz = _libraries['libcuda.so'].cuStreamAddCallback_ptsz - cuStreamAddCallback_ptsz.restype = CUresult - cuStreamAddCallback_ptsz.argtypes = [CUstream, CUstreamCallback, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBeginCapture_v2_ptsz = _libraries['libcuda.so'].cuStreamBeginCapture_v2_ptsz - cuStreamBeginCapture_v2_ptsz.restype = CUresult - cuStreamBeginCapture_v2_ptsz.argtypes = [CUstream, CUstreamCaptureMode] -except AttributeError: - pass -try: - cuThreadExchangeStreamCaptureMode = _libraries['libcuda.so'].cuThreadExchangeStreamCaptureMode - cuThreadExchangeStreamCaptureMode.restype = CUresult - cuThreadExchangeStreamCaptureMode.argtypes = [ctypes.POINTER(CUstreamCaptureMode_enum)] -except AttributeError: - pass -try: - cuStreamEndCapture_ptsz = _libraries['libcuda.so'].cuStreamEndCapture_ptsz - cuStreamEndCapture_ptsz.restype = CUresult - cuStreamEndCapture_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuStreamIsCapturing_ptsz = _libraries['libcuda.so'].cuStreamIsCapturing_ptsz - cuStreamIsCapturing_ptsz.restype = CUresult - cuStreamIsCapturing_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_v2_ptsz = _libraries['libcuda.so'].cuStreamGetCaptureInfo_v2_ptsz - cuStreamGetCaptureInfo_v2_ptsz.restype = CUresult - cuStreamGetCaptureInfo_v2_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamUpdateCaptureDependencies_ptsz = _libraries['libcuda.so'].cuStreamUpdateCaptureDependencies_ptsz - cuStreamUpdateCaptureDependencies_ptsz.restype = CUresult - cuStreamUpdateCaptureDependencies_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAttachMemAsync_ptsz = _libraries['libcuda.so'].cuStreamAttachMemAsync_ptsz - cuStreamAttachMemAsync_ptsz.restype = CUresult - cuStreamAttachMemAsync_ptsz.argtypes = [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamQuery_ptsz = _libraries['libcuda.so'].cuStreamQuery_ptsz - cuStreamQuery_ptsz.restype = CUresult - cuStreamQuery_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamSynchronize_ptsz = _libraries['libcuda.so'].cuStreamSynchronize_ptsz - cuStreamSynchronize_ptsz.restype = CUresult - cuStreamSynchronize_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamDestroy_v2 = _libraries['libcuda.so'].cuStreamDestroy_v2 - cuStreamDestroy_v2.restype = CUresult - cuStreamDestroy_v2.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamCopyAttributes_ptsz = _libraries['libcuda.so'].cuStreamCopyAttributes_ptsz - cuStreamCopyAttributes_ptsz.restype = CUresult - cuStreamCopyAttributes_ptsz.argtypes = [CUstream, CUstream] -except AttributeError: - pass -try: - cuStreamGetAttribute_ptsz = _libraries['libcuda.so'].cuStreamGetAttribute_ptsz - cuStreamGetAttribute_ptsz.restype = CUresult - cuStreamGetAttribute_ptsz.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuStreamSetAttribute_ptsz = _libraries['libcuda.so'].cuStreamSetAttribute_ptsz - cuStreamSetAttribute_ptsz.restype = CUresult - cuStreamSetAttribute_ptsz.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuEventCreate = _libraries['libcuda.so'].cuEventCreate - cuEventCreate.restype = CUresult - cuEventCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUevent_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuEventRecord_ptsz = _libraries['libcuda.so'].cuEventRecord_ptsz - cuEventRecord_ptsz.restype = CUresult - cuEventRecord_ptsz.argtypes = [CUevent, CUstream] -except AttributeError: - pass -try: - cuEventRecordWithFlags_ptsz = _libraries['libcuda.so'].cuEventRecordWithFlags_ptsz - cuEventRecordWithFlags_ptsz.restype = CUresult - cuEventRecordWithFlags_ptsz.argtypes = [CUevent, CUstream, ctypes.c_uint32] -except AttributeError: - pass -try: - cuEventQuery = _libraries['libcuda.so'].cuEventQuery - cuEventQuery.restype = CUresult - cuEventQuery.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventSynchronize = _libraries['libcuda.so'].cuEventSynchronize - cuEventSynchronize.restype = CUresult - cuEventSynchronize.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventDestroy_v2 = _libraries['libcuda.so'].cuEventDestroy_v2 - cuEventDestroy_v2.restype = CUresult - cuEventDestroy_v2.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventElapsedTime = _libraries['libcuda.so'].cuEventElapsedTime - cuEventElapsedTime.restype = CUresult - cuEventElapsedTime.argtypes = [ctypes.POINTER(ctypes.c_float), CUevent, CUevent] -except AttributeError: - pass -try: - cuImportExternalMemory = _libraries['libcuda.so'].cuImportExternalMemory - cuImportExternalMemory.restype = CUresult - cuImportExternalMemory.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextMemory_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st)] -except AttributeError: - pass -try: - cuExternalMemoryGetMappedBuffer = _libraries['libcuda.so'].cuExternalMemoryGetMappedBuffer - cuExternalMemoryGetMappedBuffer.restype = CUresult - cuExternalMemoryGetMappedBuffer.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUexternalMemory, ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st)] -except AttributeError: - pass -try: - cuExternalMemoryGetMappedMipmappedArray = _libraries['libcuda.so'].cuExternalMemoryGetMappedMipmappedArray - cuExternalMemoryGetMappedMipmappedArray.restype = CUresult - cuExternalMemoryGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUexternalMemory, ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st)] -except AttributeError: - pass -try: - cuDestroyExternalMemory = _libraries['libcuda.so'].cuDestroyExternalMemory - cuDestroyExternalMemory.restype = CUresult - cuDestroyExternalMemory.argtypes = [CUexternalMemory] -except AttributeError: - pass -try: - cuImportExternalSemaphore = _libraries['libcuda.so'].cuImportExternalSemaphore - cuImportExternalSemaphore.restype = CUresult - cuImportExternalSemaphore.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st)] -except AttributeError: - pass -try: - cuSignalExternalSemaphoresAsync_ptsz = _libraries['libcuda.so'].cuSignalExternalSemaphoresAsync_ptsz - cuSignalExternalSemaphoresAsync_ptsz.restype = CUresult - cuSignalExternalSemaphoresAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuWaitExternalSemaphoresAsync_ptsz = _libraries['libcuda.so'].cuWaitExternalSemaphoresAsync_ptsz - cuWaitExternalSemaphoresAsync_ptsz.restype = CUresult - cuWaitExternalSemaphoresAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuDestroyExternalSemaphore = _libraries['libcuda.so'].cuDestroyExternalSemaphore - cuDestroyExternalSemaphore.restype = CUresult - cuDestroyExternalSemaphore.argtypes = [CUexternalSemaphore] -except AttributeError: - pass -try: - cuStreamWaitValue32_v2_ptsz = _libraries['libcuda.so'].cuStreamWaitValue32_v2_ptsz - cuStreamWaitValue32_v2_ptsz.restype = CUresult - cuStreamWaitValue32_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_v2_ptsz = _libraries['libcuda.so'].cuStreamWaitValue64_v2_ptsz - cuStreamWaitValue64_v2_ptsz.restype = CUresult - cuStreamWaitValue64_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_v2_ptsz = _libraries['libcuda.so'].cuStreamWriteValue32_v2_ptsz - cuStreamWriteValue32_v2_ptsz.restype = CUresult - cuStreamWriteValue32_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_v2_ptsz = _libraries['libcuda.so'].cuStreamWriteValue64_v2_ptsz - cuStreamWriteValue64_v2_ptsz.restype = CUresult - cuStreamWriteValue64_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_v2_ptsz = _libraries['libcuda.so'].cuStreamBatchMemOp_v2_ptsz - cuStreamBatchMemOp_v2_ptsz.restype = CUresult - cuStreamBatchMemOp_v2_ptsz.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuFuncGetAttribute = _libraries['libcuda.so'].cuFuncGetAttribute - cuFuncGetAttribute.restype = CUresult - cuFuncGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUfunction] -except AttributeError: - pass -try: - cuFuncSetAttribute = _libraries['libcuda.so'].cuFuncSetAttribute - cuFuncSetAttribute.restype = CUresult - cuFuncSetAttribute.argtypes = [CUfunction, CUfunction_attribute, ctypes.c_int32] -except AttributeError: - pass -try: - cuFuncSetCacheConfig = _libraries['libcuda.so'].cuFuncSetCacheConfig - cuFuncSetCacheConfig.restype = CUresult - cuFuncSetCacheConfig.argtypes = [CUfunction, CUfunc_cache] -except AttributeError: - pass -try: - cuFuncSetSharedMemConfig = _libraries['libcuda.so'].cuFuncSetSharedMemConfig - cuFuncSetSharedMemConfig.restype = CUresult - cuFuncSetSharedMemConfig.argtypes = [CUfunction, CUsharedconfig] -except AttributeError: - pass -try: - cuFuncGetModule = _libraries['libcuda.so'].cuFuncGetModule - cuFuncGetModule.restype = CUresult - cuFuncGetModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), CUfunction] -except AttributeError: - pass -try: - cuLaunchKernel_ptsz = _libraries['libcuda.so'].cuLaunchKernel_ptsz - cuLaunchKernel_ptsz.restype = CUresult - cuLaunchKernel_ptsz.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchKernelEx_ptsz = _libraries['libcuda.so'].cuLaunchKernelEx_ptsz - cuLaunchKernelEx_ptsz.restype = CUresult - cuLaunchKernelEx_ptsz.argtypes = [ctypes.POINTER(struct_CUlaunchConfig_st), CUfunction, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchCooperativeKernel_ptsz = _libraries['libcuda.so'].cuLaunchCooperativeKernel_ptsz - cuLaunchCooperativeKernel_ptsz.restype = CUresult - cuLaunchCooperativeKernel_ptsz.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchCooperativeKernelMultiDevice = _libraries['libcuda.so'].cuLaunchCooperativeKernelMultiDevice - cuLaunchCooperativeKernelMultiDevice.restype = CUresult - cuLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_CUDA_LAUNCH_PARAMS_st), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunchHostFunc_ptsz = _libraries['libcuda.so'].cuLaunchHostFunc_ptsz - cuLaunchHostFunc_ptsz.restype = CUresult - cuLaunchHostFunc_ptsz.argtypes = [CUstream, CUhostFn, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuFuncSetBlockShape = _libraries['libcuda.so'].cuFuncSetBlockShape - cuFuncSetBlockShape.restype = CUresult - cuFuncSetBlockShape.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuFuncSetSharedSize = _libraries['libcuda.so'].cuFuncSetSharedSize - cuFuncSetSharedSize.restype = CUresult - cuFuncSetSharedSize.argtypes = [CUfunction, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSetSize = _libraries['libcuda.so'].cuParamSetSize - cuParamSetSize.restype = CUresult - cuParamSetSize.argtypes = [CUfunction, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSeti = _libraries['libcuda.so'].cuParamSeti - cuParamSeti.restype = CUresult - cuParamSeti.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSetf = _libraries['libcuda.so'].cuParamSetf - cuParamSetf.restype = CUresult - cuParamSetf.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_float] -except AttributeError: - pass -try: - cuParamSetv = _libraries['libcuda.so'].cuParamSetv - cuParamSetv.restype = CUresult - cuParamSetv.argtypes = [CUfunction, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunch = _libraries['libcuda.so'].cuLaunch - cuLaunch.restype = CUresult - cuLaunch.argtypes = [CUfunction] -except AttributeError: - pass -try: - cuLaunchGrid = _libraries['libcuda.so'].cuLaunchGrid - cuLaunchGrid.restype = CUresult - cuLaunchGrid.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuLaunchGridAsync = _libraries['libcuda.so'].cuLaunchGridAsync - cuLaunchGridAsync.restype = CUresult - cuLaunchGridAsync.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32, CUstream] -except AttributeError: - pass -try: - cuParamSetTexRef = _libraries['libcuda.so'].cuParamSetTexRef - cuParamSetTexRef.restype = CUresult - cuParamSetTexRef.argtypes = [CUfunction, ctypes.c_int32, CUtexref] -except AttributeError: - pass -try: - cuGraphCreate = _libraries['libcuda.so'].cuGraphCreate - cuGraphCreate.restype = CUresult - cuGraphCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphAddKernelNode_v2 = _libraries['libcuda.so'].cuGraphAddKernelNode_v2 - cuGraphAddKernelNode_v2.restype = CUresult - cuGraphAddKernelNode_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeGetParams_v2 = _libraries['libcuda.so'].cuGraphKernelNodeGetParams_v2 - cuGraphKernelNodeGetParams_v2.restype = CUresult - cuGraphKernelNodeGetParams_v2.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetParams_v2 = _libraries['libcuda.so'].cuGraphKernelNodeSetParams_v2 - cuGraphKernelNodeSetParams_v2.restype = CUresult - cuGraphKernelNodeSetParams_v2.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphAddMemcpyNode = _libraries['libcuda.so'].cuGraphAddMemcpyNode - cuGraphAddMemcpyNode.restype = CUresult - cuGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUcontext] -except AttributeError: - pass -try: - cuGraphMemcpyNodeGetParams = _libraries['libcuda.so'].cuGraphMemcpyNodeGetParams - cuGraphMemcpyNodeGetParams.restype = CUresult - cuGraphMemcpyNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuGraphMemcpyNodeSetParams = _libraries['libcuda.so'].cuGraphMemcpyNodeSetParams - cuGraphMemcpyNodeSetParams.restype = CUresult - cuGraphMemcpyNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuGraphAddMemsetNode = _libraries['libcuda.so'].cuGraphAddMemsetNode - cuGraphAddMemsetNode.restype = CUresult - cuGraphAddMemsetNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st), CUcontext] -except AttributeError: - pass -try: - cuGraphMemsetNodeGetParams = _libraries['libcuda.so'].cuGraphMemsetNodeGetParams - cuGraphMemsetNodeGetParams.restype = CUresult - cuGraphMemsetNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphMemsetNodeSetParams = _libraries['libcuda.so'].cuGraphMemsetNodeSetParams - cuGraphMemsetNodeSetParams.restype = CUresult - cuGraphMemsetNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddHostNode = _libraries['libcuda.so'].cuGraphAddHostNode - cuGraphAddHostNode.restype = CUresult - cuGraphAddHostNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphHostNodeGetParams = _libraries['libcuda.so'].cuGraphHostNodeGetParams - cuGraphHostNodeGetParams.restype = CUresult - cuGraphHostNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphHostNodeSetParams = _libraries['libcuda.so'].cuGraphHostNodeSetParams - cuGraphHostNodeSetParams.restype = CUresult - cuGraphHostNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddChildGraphNode = _libraries['libcuda.so'].cuGraphAddChildGraphNode - cuGraphAddChildGraphNode.restype = CUresult - cuGraphAddChildGraphNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUgraph] -except AttributeError: - pass -try: - cuGraphChildGraphNodeGetGraph = _libraries['libcuda.so'].cuGraphChildGraphNodeGetGraph - cuGraphChildGraphNodeGetGraph.restype = CUresult - cuGraphChildGraphNodeGetGraph.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuGraphAddEmptyNode = _libraries['libcuda.so'].cuGraphAddEmptyNode - cuGraphAddEmptyNode.restype = CUresult - cuGraphAddEmptyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphAddEventRecordNode = _libraries['libcuda.so'].cuGraphAddEventRecordNode - cuGraphAddEventRecordNode.restype = CUresult - cuGraphAddEventRecordNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUevent] -except AttributeError: - pass -try: - cuGraphEventRecordNodeGetEvent = _libraries['libcuda.so'].cuGraphEventRecordNodeGetEvent - cuGraphEventRecordNodeGetEvent.restype = CUresult - cuGraphEventRecordNodeGetEvent.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUevent_st))] -except AttributeError: - pass -try: - cuGraphEventRecordNodeSetEvent = _libraries['libcuda.so'].cuGraphEventRecordNodeSetEvent - cuGraphEventRecordNodeSetEvent.restype = CUresult - cuGraphEventRecordNodeSetEvent.argtypes = [CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphAddEventWaitNode = _libraries['libcuda.so'].cuGraphAddEventWaitNode - cuGraphAddEventWaitNode.restype = CUresult - cuGraphAddEventWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUevent] -except AttributeError: - pass -try: - cuGraphEventWaitNodeGetEvent = _libraries['libcuda.so'].cuGraphEventWaitNodeGetEvent - cuGraphEventWaitNodeGetEvent.restype = CUresult - cuGraphEventWaitNodeGetEvent.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUevent_st))] -except AttributeError: - pass -try: - cuGraphEventWaitNodeSetEvent = _libraries['libcuda.so'].cuGraphEventWaitNodeSetEvent - cuGraphEventWaitNodeSetEvent.restype = CUresult - cuGraphEventWaitNodeSetEvent.argtypes = [CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphAddExternalSemaphoresSignalNode = _libraries['libcuda.so'].cuGraphAddExternalSemaphoresSignalNode - cuGraphAddExternalSemaphoresSignalNode.restype = CUresult - cuGraphAddExternalSemaphoresSignalNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresSignalNodeGetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresSignalNodeGetParams - cuGraphExternalSemaphoresSignalNodeGetParams.restype = CUresult - cuGraphExternalSemaphoresSignalNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresSignalNodeSetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresSignalNodeSetParams - cuGraphExternalSemaphoresSignalNodeSetParams.restype = CUresult - cuGraphExternalSemaphoresSignalNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddExternalSemaphoresWaitNode = _libraries['libcuda.so'].cuGraphAddExternalSemaphoresWaitNode - cuGraphAddExternalSemaphoresWaitNode.restype = CUresult - cuGraphAddExternalSemaphoresWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresWaitNodeGetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresWaitNodeGetParams - cuGraphExternalSemaphoresWaitNodeGetParams.restype = CUresult - cuGraphExternalSemaphoresWaitNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresWaitNodeSetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresWaitNodeSetParams - cuGraphExternalSemaphoresWaitNodeSetParams.restype = CUresult - cuGraphExternalSemaphoresWaitNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddBatchMemOpNode = _libraries['libcuda.so'].cuGraphAddBatchMemOpNode - cuGraphAddBatchMemOpNode.restype = CUresult - cuGraphAddBatchMemOpNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphBatchMemOpNodeGetParams = _libraries['libcuda.so'].cuGraphBatchMemOpNodeGetParams - cuGraphBatchMemOpNodeGetParams.restype = CUresult - cuGraphBatchMemOpNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphBatchMemOpNodeSetParams = _libraries['libcuda.so'].cuGraphBatchMemOpNodeSetParams - cuGraphBatchMemOpNodeSetParams.restype = CUresult - cuGraphBatchMemOpNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecBatchMemOpNodeSetParams = _libraries['libcuda.so'].cuGraphExecBatchMemOpNodeSetParams - cuGraphExecBatchMemOpNodeSetParams.restype = CUresult - cuGraphExecBatchMemOpNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddMemAllocNode = _libraries['libcuda.so'].cuGraphAddMemAllocNode - cuGraphAddMemAllocNode.restype = CUresult - cuGraphAddMemAllocNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEM_ALLOC_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphMemAllocNodeGetParams = _libraries['libcuda.so'].cuGraphMemAllocNodeGetParams - cuGraphMemAllocNodeGetParams.restype = CUresult - cuGraphMemAllocNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEM_ALLOC_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddMemFreeNode = _libraries['libcuda.so'].cuGraphAddMemFreeNode - cuGraphAddMemFreeNode.restype = CUresult - cuGraphAddMemFreeNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUdeviceptr] -except AttributeError: - pass -try: - cuGraphMemFreeNodeGetParams = _libraries['libcuda.so'].cuGraphMemFreeNodeGetParams - cuGraphMemFreeNodeGetParams.restype = CUresult - cuGraphMemFreeNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuDeviceGraphMemTrim = _libraries['libcuda.so'].cuDeviceGraphMemTrim - cuDeviceGraphMemTrim.restype = CUresult - cuDeviceGraphMemTrim.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDeviceGetGraphMemAttribute = _libraries['libcuda.so'].cuDeviceGetGraphMemAttribute - cuDeviceGetGraphMemAttribute.restype = CUresult - cuDeviceGetGraphMemAttribute.argtypes = [CUdevice, CUgraphMem_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuDeviceSetGraphMemAttribute = _libraries['libcuda.so'].cuDeviceSetGraphMemAttribute - cuDeviceSetGraphMemAttribute.restype = CUresult - cuDeviceSetGraphMemAttribute.argtypes = [CUdevice, CUgraphMem_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuGraphClone = _libraries['libcuda.so'].cuGraphClone - cuGraphClone.restype = CUresult - cuGraphClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), CUgraph] -except AttributeError: - pass -try: - cuGraphNodeFindInClone = _libraries['libcuda.so'].cuGraphNodeFindInClone - cuGraphNodeFindInClone.restype = CUresult - cuGraphNodeFindInClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraphNode, CUgraph] -except AttributeError: - pass -try: - cuGraphNodeGetType = _libraries['libcuda.so'].cuGraphNodeGetType - cuGraphNodeGetType.restype = CUresult - cuGraphNodeGetType.argtypes = [CUgraphNode, ctypes.POINTER(CUgraphNodeType_enum)] -except AttributeError: - pass -try: - cuGraphGetNodes = _libraries['libcuda.so'].cuGraphGetNodes - cuGraphGetNodes.restype = CUresult - cuGraphGetNodes.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphGetRootNodes = _libraries['libcuda.so'].cuGraphGetRootNodes - cuGraphGetRootNodes.restype = CUresult - cuGraphGetRootNodes.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphGetEdges = _libraries['libcuda.so'].cuGraphGetEdges - cuGraphGetEdges.restype = CUresult - cuGraphGetEdges.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphNodeGetDependencies = _libraries['libcuda.so'].cuGraphNodeGetDependencies - cuGraphNodeGetDependencies.restype = CUresult - cuGraphNodeGetDependencies.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphNodeGetDependentNodes = _libraries['libcuda.so'].cuGraphNodeGetDependentNodes - cuGraphNodeGetDependentNodes.restype = CUresult - cuGraphNodeGetDependentNodes.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphAddDependencies = _libraries['libcuda.so'].cuGraphAddDependencies - cuGraphAddDependencies.restype = CUresult - cuGraphAddDependencies.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphRemoveDependencies = _libraries['libcuda.so'].cuGraphRemoveDependencies - cuGraphRemoveDependencies.restype = CUresult - cuGraphRemoveDependencies.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphDestroyNode = _libraries['libcuda.so'].cuGraphDestroyNode - cuGraphDestroyNode.restype = CUresult - cuGraphDestroyNode.argtypes = [CUgraphNode] -except AttributeError: - pass -try: - cuGraphInstantiateWithFlags = _libraries['libcuda.so'].cuGraphInstantiateWithFlags - cuGraphInstantiateWithFlags.restype = CUresult - cuGraphInstantiateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.c_uint64] -except AttributeError: - pass -try: - cuGraphInstantiateWithParams_ptsz = _libraries['libcuda.so'].cuGraphInstantiateWithParams_ptsz - cuGraphInstantiateWithParams_ptsz.restype = CUresult - cuGraphInstantiateWithParams_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecGetFlags = _libraries['libcuda.so'].cuGraphExecGetFlags - cuGraphExecGetFlags.restype = CUresult - cuGraphExecGetFlags.argtypes = [CUgraphExec, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphExecKernelNodeSetParams_v2 = _libraries['libcuda.so'].cuGraphExecKernelNodeSetParams_v2 - cuGraphExecKernelNodeSetParams_v2.restype = CUresult - cuGraphExecKernelNodeSetParams_v2.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphExecMemcpyNodeSetParams = _libraries['libcuda.so'].cuGraphExecMemcpyNodeSetParams - cuGraphExecMemcpyNodeSetParams.restype = CUresult - cuGraphExecMemcpyNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUcontext] -except AttributeError: - pass -try: - cuGraphExecMemsetNodeSetParams = _libraries['libcuda.so'].cuGraphExecMemsetNodeSetParams - cuGraphExecMemsetNodeSetParams.restype = CUresult - cuGraphExecMemsetNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st), CUcontext] -except AttributeError: - pass -try: - cuGraphExecHostNodeSetParams = _libraries['libcuda.so'].cuGraphExecHostNodeSetParams - cuGraphExecHostNodeSetParams.restype = CUresult - cuGraphExecHostNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecChildGraphNodeSetParams = _libraries['libcuda.so'].cuGraphExecChildGraphNodeSetParams - cuGraphExecChildGraphNodeSetParams.restype = CUresult - cuGraphExecChildGraphNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, CUgraph] -except AttributeError: - pass -try: - cuGraphExecEventRecordNodeSetEvent = _libraries['libcuda.so'].cuGraphExecEventRecordNodeSetEvent - cuGraphExecEventRecordNodeSetEvent.restype = CUresult - cuGraphExecEventRecordNodeSetEvent.argtypes = [CUgraphExec, CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphExecEventWaitNodeSetEvent = _libraries['libcuda.so'].cuGraphExecEventWaitNodeSetEvent - cuGraphExecEventWaitNodeSetEvent.restype = CUresult - cuGraphExecEventWaitNodeSetEvent.argtypes = [CUgraphExec, CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphExecExternalSemaphoresSignalNodeSetParams = _libraries['libcuda.so'].cuGraphExecExternalSemaphoresSignalNodeSetParams - cuGraphExecExternalSemaphoresSignalNodeSetParams.restype = CUresult - cuGraphExecExternalSemaphoresSignalNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecExternalSemaphoresWaitNodeSetParams = _libraries['libcuda.so'].cuGraphExecExternalSemaphoresWaitNodeSetParams - cuGraphExecExternalSemaphoresWaitNodeSetParams.restype = CUresult - cuGraphExecExternalSemaphoresWaitNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphNodeSetEnabled = _libraries['libcuda.so'].cuGraphNodeSetEnabled - cuGraphNodeSetEnabled.restype = CUresult - cuGraphNodeSetEnabled.argtypes = [CUgraphExec, CUgraphNode, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphNodeGetEnabled = _libraries['libcuda.so'].cuGraphNodeGetEnabled - cuGraphNodeGetEnabled.restype = CUresult - cuGraphNodeGetEnabled.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuGraphUpload_ptsz = _libraries['libcuda.so'].cuGraphUpload_ptsz - cuGraphUpload_ptsz.restype = CUresult - cuGraphUpload_ptsz.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphLaunch_ptsz = _libraries['libcuda.so'].cuGraphLaunch_ptsz - cuGraphLaunch_ptsz.restype = CUresult - cuGraphLaunch_ptsz.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphExecDestroy = _libraries['libcuda.so'].cuGraphExecDestroy - cuGraphExecDestroy.restype = CUresult - cuGraphExecDestroy.argtypes = [CUgraphExec] -except AttributeError: - pass -try: - cuGraphDestroy = _libraries['libcuda.so'].cuGraphDestroy - cuGraphDestroy.restype = CUresult - cuGraphDestroy.argtypes = [CUgraph] -except AttributeError: - pass -try: - cuGraphExecUpdate_v2 = _libraries['libcuda.so'].cuGraphExecUpdate_v2 - cuGraphExecUpdate_v2.restype = CUresult - cuGraphExecUpdate_v2.argtypes = [CUgraphExec, CUgraph, ctypes.POINTER(struct_CUgraphExecUpdateResultInfo_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeCopyAttributes = _libraries['libcuda.so'].cuGraphKernelNodeCopyAttributes - cuGraphKernelNodeCopyAttributes.restype = CUresult - cuGraphKernelNodeCopyAttributes.argtypes = [CUgraphNode, CUgraphNode] -except AttributeError: - pass -try: - cuGraphKernelNodeGetAttribute = _libraries['libcuda.so'].cuGraphKernelNodeGetAttribute - cuGraphKernelNodeGetAttribute.restype = CUresult - cuGraphKernelNodeGetAttribute.argtypes = [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetAttribute = _libraries['libcuda.so'].cuGraphKernelNodeSetAttribute - cuGraphKernelNodeSetAttribute.restype = CUresult - cuGraphKernelNodeSetAttribute.argtypes = [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuGraphDebugDotPrint = _libraries['libcuda.so'].cuGraphDebugDotPrint - cuGraphDebugDotPrint.restype = CUresult - cuGraphDebugDotPrint.argtypes = [CUgraph, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectCreate = _libraries['libcuda.so'].cuUserObjectCreate - cuUserObjectCreate.restype = CUresult - cuUserObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUuserObject_st)), ctypes.POINTER(None), CUhostFn, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectRetain = _libraries['libcuda.so'].cuUserObjectRetain - cuUserObjectRetain.restype = CUresult - cuUserObjectRetain.argtypes = [CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectRelease = _libraries['libcuda.so'].cuUserObjectRelease - cuUserObjectRelease.restype = CUresult - cuUserObjectRelease.argtypes = [CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphRetainUserObject = _libraries['libcuda.so'].cuGraphRetainUserObject - cuGraphRetainUserObject.restype = CUresult - cuGraphRetainUserObject.argtypes = [CUgraph, CUuserObject, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphReleaseUserObject = _libraries['libcuda.so'].cuGraphReleaseUserObject - cuGraphReleaseUserObject.restype = CUresult - cuGraphReleaseUserObject.argtypes = [CUgraph, CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libcuda.so'].cuOccupancyMaxActiveBlocksPerMultiprocessor - cuOccupancyMaxActiveBlocksPerMultiprocessor.restype = CUresult - cuOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libcuda.so'].cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = CUresult - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialBlockSize = _libraries['libcuda.so'].cuOccupancyMaxPotentialBlockSize - cuOccupancyMaxPotentialBlockSize.restype = CUresult - cuOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialBlockSizeWithFlags = _libraries['libcuda.so'].cuOccupancyMaxPotentialBlockSizeWithFlags - cuOccupancyMaxPotentialBlockSizeWithFlags.restype = CUresult - cuOccupancyMaxPotentialBlockSizeWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyAvailableDynamicSMemPerBlock = _libraries['libcuda.so'].cuOccupancyAvailableDynamicSMemPerBlock - cuOccupancyAvailableDynamicSMemPerBlock.restype = CUresult - cuOccupancyAvailableDynamicSMemPerBlock.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUfunction, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialClusterSize = _libraries['libcuda.so'].cuOccupancyMaxPotentialClusterSize - cuOccupancyMaxPotentialClusterSize.restype = CUresult - cuOccupancyMaxPotentialClusterSize.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(struct_CUlaunchConfig_st)] -except AttributeError: - pass -try: - cuOccupancyMaxActiveClusters = _libraries['libcuda.so'].cuOccupancyMaxActiveClusters - cuOccupancyMaxActiveClusters.restype = CUresult - cuOccupancyMaxActiveClusters.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(struct_CUlaunchConfig_st)] -except AttributeError: - pass -try: - cuTexRefSetArray = _libraries['libcuda.so'].cuTexRefSetArray - cuTexRefSetArray.restype = CUresult - cuTexRefSetArray.argtypes = [CUtexref, CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetMipmappedArray = _libraries['libcuda.so'].cuTexRefSetMipmappedArray - cuTexRefSetMipmappedArray.restype = CUresult - cuTexRefSetMipmappedArray.argtypes = [CUtexref, CUmipmappedArray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetAddress_v2 = _libraries['libcuda.so'].cuTexRefSetAddress_v2 - cuTexRefSetAddress_v2.restype = CUresult - cuTexRefSetAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUtexref, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuTexRefSetAddress2D_v3 = _libraries['libcuda.so'].cuTexRefSetAddress2D_v3 - cuTexRefSetAddress2D_v3.restype = CUresult - cuTexRefSetAddress2D_v3.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuTexRefSetFormat = _libraries['libcuda.so'].cuTexRefSetFormat - cuTexRefSetFormat.restype = CUresult - cuTexRefSetFormat.argtypes = [CUtexref, CUarray_format, ctypes.c_int32] -except AttributeError: - pass -try: - cuTexRefSetAddressMode = _libraries['libcuda.so'].cuTexRefSetAddressMode - cuTexRefSetAddressMode.restype = CUresult - cuTexRefSetAddressMode.argtypes = [CUtexref, ctypes.c_int32, CUaddress_mode] -except AttributeError: - pass -try: - cuTexRefSetFilterMode = _libraries['libcuda.so'].cuTexRefSetFilterMode - cuTexRefSetFilterMode.restype = CUresult - cuTexRefSetFilterMode.argtypes = [CUtexref, CUfilter_mode] -except AttributeError: - pass -try: - cuTexRefSetMipmapFilterMode = _libraries['libcuda.so'].cuTexRefSetMipmapFilterMode - cuTexRefSetMipmapFilterMode.restype = CUresult - cuTexRefSetMipmapFilterMode.argtypes = [CUtexref, CUfilter_mode] -except AttributeError: - pass -try: - cuTexRefSetMipmapLevelBias = _libraries['libcuda.so'].cuTexRefSetMipmapLevelBias - cuTexRefSetMipmapLevelBias.restype = CUresult - cuTexRefSetMipmapLevelBias.argtypes = [CUtexref, ctypes.c_float] -except AttributeError: - pass -try: - cuTexRefSetMipmapLevelClamp = _libraries['libcuda.so'].cuTexRefSetMipmapLevelClamp - cuTexRefSetMipmapLevelClamp.restype = CUresult - cuTexRefSetMipmapLevelClamp.argtypes = [CUtexref, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - cuTexRefSetMaxAnisotropy = _libraries['libcuda.so'].cuTexRefSetMaxAnisotropy - cuTexRefSetMaxAnisotropy.restype = CUresult - cuTexRefSetMaxAnisotropy.argtypes = [CUtexref, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetBorderColor = _libraries['libcuda.so'].cuTexRefSetBorderColor - cuTexRefSetBorderColor.restype = CUresult - cuTexRefSetBorderColor.argtypes = [CUtexref, ctypes.POINTER(ctypes.c_float)] -except AttributeError: - pass -try: - cuTexRefSetFlags = _libraries['libcuda.so'].cuTexRefSetFlags - cuTexRefSetFlags.restype = CUresult - cuTexRefSetFlags.argtypes = [CUtexref, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefGetAddress_v2 = _libraries['libcuda.so'].cuTexRefGetAddress_v2 - cuTexRefGetAddress_v2.restype = CUresult - cuTexRefGetAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetArray = _libraries['libcuda.so'].cuTexRefGetArray - cuTexRefGetArray.restype = CUresult - cuTexRefGetArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmappedArray = _libraries['libcuda.so'].cuTexRefGetMipmappedArray - cuTexRefGetMipmappedArray.restype = CUresult - cuTexRefGetMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetAddressMode = _libraries['libcuda.so'].cuTexRefGetAddressMode - cuTexRefGetAddressMode.restype = CUresult - cuTexRefGetAddressMode.argtypes = [ctypes.POINTER(CUaddress_mode_enum), CUtexref, ctypes.c_int32] -except AttributeError: - pass -try: - cuTexRefGetFilterMode = _libraries['libcuda.so'].cuTexRefGetFilterMode - cuTexRefGetFilterMode.restype = CUresult - cuTexRefGetFilterMode.argtypes = [ctypes.POINTER(CUfilter_mode_enum), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetFormat = _libraries['libcuda.so'].cuTexRefGetFormat - cuTexRefGetFormat.restype = CUresult - cuTexRefGetFormat.argtypes = [ctypes.POINTER(CUarray_format_enum), ctypes.POINTER(ctypes.c_int32), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapFilterMode = _libraries['libcuda.so'].cuTexRefGetMipmapFilterMode - cuTexRefGetMipmapFilterMode.restype = CUresult - cuTexRefGetMipmapFilterMode.argtypes = [ctypes.POINTER(CUfilter_mode_enum), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapLevelBias = _libraries['libcuda.so'].cuTexRefGetMipmapLevelBias - cuTexRefGetMipmapLevelBias.restype = CUresult - cuTexRefGetMipmapLevelBias.argtypes = [ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapLevelClamp = _libraries['libcuda.so'].cuTexRefGetMipmapLevelClamp - cuTexRefGetMipmapLevelClamp.restype = CUresult - cuTexRefGetMipmapLevelClamp.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMaxAnisotropy = _libraries['libcuda.so'].cuTexRefGetMaxAnisotropy - cuTexRefGetMaxAnisotropy.restype = CUresult - cuTexRefGetMaxAnisotropy.argtypes = [ctypes.POINTER(ctypes.c_int32), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetBorderColor = _libraries['libcuda.so'].cuTexRefGetBorderColor - cuTexRefGetBorderColor.restype = CUresult - cuTexRefGetBorderColor.argtypes = [ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetFlags = _libraries['libcuda.so'].cuTexRefGetFlags - cuTexRefGetFlags.restype = CUresult - cuTexRefGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref] -except AttributeError: - pass -try: - cuTexRefCreate = _libraries['libcuda.so'].cuTexRefCreate - cuTexRefCreate.restype = CUresult - cuTexRefCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUtexref_st))] -except AttributeError: - pass -try: - cuTexRefDestroy = _libraries['libcuda.so'].cuTexRefDestroy - cuTexRefDestroy.restype = CUresult - cuTexRefDestroy.argtypes = [CUtexref] -except AttributeError: - pass -try: - cuSurfRefSetArray = _libraries['libcuda.so'].cuSurfRefSetArray - cuSurfRefSetArray.restype = CUresult - cuSurfRefSetArray.argtypes = [CUsurfref, CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuSurfRefGetArray = _libraries['libcuda.so'].cuSurfRefGetArray - cuSurfRefGetArray.restype = CUresult - cuSurfRefGetArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUsurfref] -except AttributeError: - pass -try: - cuTexObjectCreate = _libraries['libcuda.so'].cuTexObjectCreate - cuTexObjectCreate.restype = CUresult - cuTexObjectCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), ctypes.POINTER(struct_CUDA_TEXTURE_DESC_st), ctypes.POINTER(struct_CUDA_RESOURCE_VIEW_DESC_st)] -except AttributeError: - pass -try: - cuTexObjectDestroy = _libraries['libcuda.so'].cuTexObjectDestroy - cuTexObjectDestroy.restype = CUresult - cuTexObjectDestroy.argtypes = [CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetResourceDesc = _libraries['libcuda.so'].cuTexObjectGetResourceDesc - cuTexObjectGetResourceDesc.restype = CUresult - cuTexObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetTextureDesc = _libraries['libcuda.so'].cuTexObjectGetTextureDesc - cuTexObjectGetTextureDesc.restype = CUresult - cuTexObjectGetTextureDesc.argtypes = [ctypes.POINTER(struct_CUDA_TEXTURE_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetResourceViewDesc = _libraries['libcuda.so'].cuTexObjectGetResourceViewDesc - cuTexObjectGetResourceViewDesc.restype = CUresult - cuTexObjectGetResourceViewDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_VIEW_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuSurfObjectCreate = _libraries['libcuda.so'].cuSurfObjectCreate - cuSurfObjectCreate.restype = CUresult - cuSurfObjectCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st)] -except AttributeError: - pass -try: - cuSurfObjectDestroy = _libraries['libcuda.so'].cuSurfObjectDestroy - cuSurfObjectDestroy.restype = CUresult - cuSurfObjectDestroy.argtypes = [CUsurfObject] -except AttributeError: - pass -try: - cuSurfObjectGetResourceDesc = _libraries['libcuda.so'].cuSurfObjectGetResourceDesc - cuSurfObjectGetResourceDesc.restype = CUresult - cuSurfObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), CUsurfObject] -except AttributeError: - pass -try: - cuTensorMapEncodeTiled = _libraries['libcuda.so'].cuTensorMapEncodeTiled - cuTensorMapEncodeTiled.restype = CUresult - cuTensorMapEncodeTiled.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), CUtensorMapDataType, cuuint32_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] -except AttributeError: - pass -try: - cuTensorMapEncodeIm2col = _libraries['libcuda.so'].cuTensorMapEncodeIm2col - cuTensorMapEncodeIm2col.restype = CUresult - cuTensorMapEncodeIm2col.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), CUtensorMapDataType, cuuint32_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), cuuint32_t, cuuint32_t, ctypes.POINTER(ctypes.c_uint32), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] -except AttributeError: - pass -try: - cuTensorMapReplaceAddress = _libraries['libcuda.so'].cuTensorMapReplaceAddress - cuTensorMapReplaceAddress.restype = CUresult - cuTensorMapReplaceAddress.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuDeviceCanAccessPeer = _libraries['libcuda.so'].cuDeviceCanAccessPeer - cuDeviceCanAccessPeer.restype = CUresult - cuDeviceCanAccessPeer.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice, CUdevice] -except AttributeError: - pass -try: - cuCtxEnablePeerAccess = _libraries['libcuda.so'].cuCtxEnablePeerAccess - cuCtxEnablePeerAccess.restype = CUresult - cuCtxEnablePeerAccess.argtypes = [CUcontext, ctypes.c_uint32] -except AttributeError: - pass -try: - cuCtxDisablePeerAccess = _libraries['libcuda.so'].cuCtxDisablePeerAccess - cuCtxDisablePeerAccess.restype = CUresult - cuCtxDisablePeerAccess.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuDeviceGetP2PAttribute = _libraries['libcuda.so'].cuDeviceGetP2PAttribute - cuDeviceGetP2PAttribute.restype = CUresult - cuDeviceGetP2PAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice_P2PAttribute, CUdevice, CUdevice] -except AttributeError: - pass -try: - cuGraphicsUnregisterResource = _libraries['libcuda.so'].cuGraphicsUnregisterResource - cuGraphicsUnregisterResource.restype = CUresult - cuGraphicsUnregisterResource.argtypes = [CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsSubResourceGetMappedArray = _libraries['libcuda.so'].cuGraphicsSubResourceGetMappedArray - cuGraphicsSubResourceGetMappedArray.restype = CUresult - cuGraphicsSubResourceGetMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUgraphicsResource, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedMipmappedArray = _libraries['libcuda.so'].cuGraphicsResourceGetMappedMipmappedArray - cuGraphicsResourceGetMappedMipmappedArray.restype = CUresult - cuGraphicsResourceGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedPointer_v2 = _libraries['libcuda.so'].cuGraphicsResourceGetMappedPointer_v2 - cuGraphicsResourceGetMappedPointer_v2.restype = CUresult - cuGraphicsResourceGetMappedPointer_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsResourceSetMapFlags_v2 = _libraries['libcuda.so'].cuGraphicsResourceSetMapFlags_v2 - cuGraphicsResourceSetMapFlags_v2.restype = CUresult - cuGraphicsResourceSetMapFlags_v2.argtypes = [CUgraphicsResource, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsMapResources_ptsz = _libraries['libcuda.so'].cuGraphicsMapResources_ptsz - cuGraphicsMapResources_ptsz.restype = CUresult - cuGraphicsMapResources_ptsz.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGraphicsUnmapResources_ptsz = _libraries['libcuda.so'].cuGraphicsUnmapResources_ptsz - cuGraphicsUnmapResources_ptsz.restype = CUresult - cuGraphicsUnmapResources_ptsz.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGetProcAddress_v2 = _libraries['libcuda.so'].cuGetProcAddress_v2 - cuGetProcAddress_v2.restype = CUresult - cuGetProcAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_int32, cuuint64_t, ctypes.POINTER(CUdriverProcAddressQueryResult_enum)] -except AttributeError: - pass -try: - cuGetExportTable = _libraries['libcuda.so'].cuGetExportTable - cuGetExportTable.restype = CUresult - cuGetExportTable.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_CUuuid_st)] -except AttributeError: - pass -try: - cuMemHostRegister = _libraries['libcuda.so'].cuMemHostRegister - cuMemHostRegister.restype = CUresult - cuMemHostRegister.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsResourceSetMapFlags = _libraries['libcuda.so'].cuGraphicsResourceSetMapFlags - cuGraphicsResourceSetMapFlags.restype = CUresult - cuGraphicsResourceSetMapFlags.argtypes = [CUgraphicsResource, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLinkCreate = _libraries['libcuda.so'].cuLinkCreate - cuLinkCreate.restype = CUresult - cuLinkCreate.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_CUlinkState_st))] -except AttributeError: - pass -try: - cuLinkAddData = _libraries['libcuda.so'].cuLinkAddData - cuLinkAddData.restype = CUresult - cuLinkAddData.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkAddFile = _libraries['libcuda.so'].cuLinkAddFile - cuLinkAddFile.restype = CUresult - cuLinkAddFile.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuTexRefSetAddress2D_v2 = _libraries['libcuda.so'].cuTexRefSetAddress2D_v2 - cuTexRefSetAddress2D_v2.restype = CUresult - cuTexRefSetAddress2D_v2.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUdeviceptr, size_t] -except AttributeError: - pass -CUdeviceptr_v1 = ctypes.c_uint32 -class struct_CUDA_MEMCPY2D_v1_st(Structure): - pass - -struct_CUDA_MEMCPY2D_v1_st._pack_ = 1 # source:False -struct_CUDA_MEMCPY2D_v1_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint32), - ('srcY', ctypes.c_uint32), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcPitch', ctypes.c_uint32), - ('dstXInBytes', ctypes.c_uint32), - ('dstY', ctypes.c_uint32), - ('dstMemoryType', CUmemorytype), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstPitch', ctypes.c_uint32), - ('WidthInBytes', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -CUDA_MEMCPY2D_v1 = struct_CUDA_MEMCPY2D_v1_st -class struct_CUDA_MEMCPY3D_v1_st(Structure): - pass - -struct_CUDA_MEMCPY3D_v1_st._pack_ = 1 # source:False -struct_CUDA_MEMCPY3D_v1_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint32), - ('srcY', ctypes.c_uint32), - ('srcZ', ctypes.c_uint32), - ('srcLOD', ctypes.c_uint32), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved0', ctypes.POINTER(None)), - ('srcPitch', ctypes.c_uint32), - ('srcHeight', ctypes.c_uint32), - ('dstXInBytes', ctypes.c_uint32), - ('dstY', ctypes.c_uint32), - ('dstZ', ctypes.c_uint32), - ('dstLOD', ctypes.c_uint32), - ('dstMemoryType', CUmemorytype), - ('PADDING_2', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved1', ctypes.POINTER(None)), - ('dstPitch', ctypes.c_uint32), - ('dstHeight', ctypes.c_uint32), - ('WidthInBytes', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Depth', ctypes.c_uint32), - ('PADDING_4', ctypes.c_ubyte * 4), -] - -CUDA_MEMCPY3D_v1 = struct_CUDA_MEMCPY3D_v1_st -class struct_CUDA_ARRAY_DESCRIPTOR_v1_st(Structure): - pass - -struct_CUDA_ARRAY_DESCRIPTOR_v1_st._pack_ = 1 # source:False -struct_CUDA_ARRAY_DESCRIPTOR_v1_st._fields_ = [ - ('Width', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), -] - -CUDA_ARRAY_DESCRIPTOR_v1 = struct_CUDA_ARRAY_DESCRIPTOR_v1_st -class struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st(Structure): - pass - -struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st._pack_ = 1 # source:False -struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st._fields_ = [ - ('Width', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Depth', ctypes.c_uint32), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), -] - -CUDA_ARRAY3D_DESCRIPTOR_v1 = struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st -try: - cuDeviceTotalMem = _libraries['libcuda.so'].cuDeviceTotalMem - cuDeviceTotalMem.restype = CUresult - cuDeviceTotalMem.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUdevice] -except AttributeError: - pass -try: - cuCtxCreate = _libraries['libcuda.so'].cuCtxCreate - cuCtxCreate.restype = CUresult - cuCtxCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuModuleGetGlobal = _libraries['libcuda.so'].cuModuleGetGlobal - cuModuleGetGlobal.restype = CUresult - cuModuleGetGlobal.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuMemGetInfo = _libraries['libcuda.so'].cuMemGetInfo - cuMemGetInfo.restype = CUresult - cuMemGetInfo.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuMemAlloc = _libraries['libcuda.so'].cuMemAlloc - cuMemAlloc.restype = CUresult - cuMemAlloc.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemAllocPitch = _libraries['libcuda.so'].cuMemAllocPitch - cuMemAllocPitch.restype = CUresult - cuMemAllocPitch.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemFree = _libraries['libcuda.so'].cuMemFree - cuMemFree.restype = CUresult - cuMemFree.argtypes = [CUdeviceptr_v1] -except AttributeError: - pass -try: - cuMemGetAddressRange = _libraries['libcuda.so'].cuMemGetAddressRange - cuMemGetAddressRange.restype = CUresult - cuMemGetAddressRange.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUdeviceptr_v1] -except AttributeError: - pass -try: - cuMemAllocHost = _libraries['libcuda.so'].cuMemAllocHost - cuMemAllocHost.restype = CUresult - cuMemAllocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetDevicePointer = _libraries['libcuda.so'].cuMemHostGetDevicePointer - cuMemHostGetDevicePointer.restype = CUresult - cuMemHostGetDevicePointer.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoD = _libraries['libcuda.so'].cuMemcpyHtoD - cuMemcpyHtoD.restype = CUresult - cuMemcpyHtoD.argtypes = [CUdeviceptr_v1, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoH = _libraries['libcuda.so'].cuMemcpyDtoH - cuMemcpyDtoH.restype = CUresult - cuMemcpyDtoH.argtypes = [ctypes.POINTER(None), CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoD = _libraries['libcuda.so'].cuMemcpyDtoD - cuMemcpyDtoD.restype = CUresult - cuMemcpyDtoD.argtypes = [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoA = _libraries['libcuda.so'].cuMemcpyDtoA - cuMemcpyDtoA.restype = CUresult - cuMemcpyDtoA.argtypes = [CUarray, ctypes.c_uint32, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoD = _libraries['libcuda.so'].cuMemcpyAtoD - cuMemcpyAtoD.restype = CUresult - cuMemcpyAtoD.argtypes = [CUdeviceptr_v1, CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoA = _libraries['libcuda.so'].cuMemcpyHtoA - cuMemcpyHtoA.restype = CUresult - cuMemcpyHtoA.argtypes = [CUarray, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoH = _libraries['libcuda.so'].cuMemcpyAtoH - cuMemcpyAtoH.restype = CUresult - cuMemcpyAtoH.argtypes = [ctypes.POINTER(None), CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoA = _libraries['libcuda.so'].cuMemcpyAtoA - cuMemcpyAtoA.restype = CUresult - cuMemcpyAtoA.argtypes = [CUarray, ctypes.c_uint32, CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync = _libraries['libcuda.so'].cuMemcpyHtoAAsync - cuMemcpyHtoAAsync.restype = CUresult - cuMemcpyHtoAAsync.argtypes = [CUarray, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync = _libraries['libcuda.so'].cuMemcpyAtoHAsync - cuMemcpyAtoHAsync.restype = CUresult - cuMemcpyAtoHAsync.argtypes = [ctypes.POINTER(None), CUarray, ctypes.c_uint32, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpy2D = _libraries['libcuda.so'].cuMemcpy2D - cuMemcpy2D.restype = CUresult - cuMemcpy2D.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned = _libraries['libcuda.so'].cuMemcpy2DUnaligned - cuMemcpy2DUnaligned.restype = CUresult - cuMemcpy2DUnaligned.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st)] -except AttributeError: - pass -try: - cuMemcpy3D = _libraries['libcuda.so'].cuMemcpy3D - cuMemcpy3D.restype = CUresult - cuMemcpy3D.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_v1_st)] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync = _libraries['libcuda.so'].cuMemcpyHtoDAsync - cuMemcpyHtoDAsync.restype = CUresult - cuMemcpyHtoDAsync.argtypes = [CUdeviceptr_v1, ctypes.POINTER(None), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync = _libraries['libcuda.so'].cuMemcpyDtoHAsync - cuMemcpyDtoHAsync.restype = CUresult - cuMemcpyDtoHAsync.argtypes = [ctypes.POINTER(None), CUdeviceptr_v1, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync = _libraries['libcuda.so'].cuMemcpyDtoDAsync - cuMemcpyDtoDAsync.restype = CUresult - cuMemcpyDtoDAsync.argtypes = [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync = _libraries['libcuda.so'].cuMemcpy2DAsync - cuMemcpy2DAsync.restype = CUresult - cuMemcpy2DAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync = _libraries['libcuda.so'].cuMemcpy3DAsync - cuMemcpy3DAsync.restype = CUresult - cuMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_v1_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8 = _libraries['libcuda.so'].cuMemsetD8 - cuMemsetD8.restype = CUresult - cuMemsetD8.argtypes = [CUdeviceptr_v1, ctypes.c_ubyte, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD16 = _libraries['libcuda.so'].cuMemsetD16 - cuMemsetD16.restype = CUresult - cuMemsetD16.argtypes = [CUdeviceptr_v1, ctypes.c_uint16, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD32 = _libraries['libcuda.so'].cuMemsetD32 - cuMemsetD32.restype = CUresult - cuMemsetD32.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D8 = _libraries['libcuda.so'].cuMemsetD2D8 - cuMemsetD2D8.restype = CUresult - cuMemsetD2D8.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D16 = _libraries['libcuda.so'].cuMemsetD2D16 - cuMemsetD2D16.restype = CUresult - cuMemsetD2D16.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint16, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D32 = _libraries['libcuda.so'].cuMemsetD2D32 - cuMemsetD2D32.restype = CUresult - cuMemsetD2D32.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuArrayCreate = _libraries['libcuda.so'].cuArrayCreate - cuArrayCreate.restype = CUresult - cuArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st)] -except AttributeError: - pass -try: - cuArrayGetDescriptor = _libraries['libcuda.so'].cuArrayGetDescriptor - cuArrayGetDescriptor.restype = CUresult - cuArrayGetDescriptor.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st), CUarray] -except AttributeError: - pass -try: - cuArray3DCreate = _libraries['libcuda.so'].cuArray3DCreate - cuArray3DCreate.restype = CUresult - cuArray3DCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st)] -except AttributeError: - pass -try: - cuArray3DGetDescriptor = _libraries['libcuda.so'].cuArray3DGetDescriptor - cuArray3DGetDescriptor.restype = CUresult - cuArray3DGetDescriptor.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st), CUarray] -except AttributeError: - pass -try: - cuTexRefSetAddress = _libraries['libcuda.so'].cuTexRefSetAddress - cuTexRefSetAddress.restype = CUresult - cuTexRefSetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetAddress2D = _libraries['libcuda.so'].cuTexRefSetAddress2D - cuTexRefSetAddress2D.restype = CUresult - cuTexRefSetAddress2D.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st), CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefGetAddress = _libraries['libcuda.so'].cuTexRefGetAddress - cuTexRefGetAddress.restype = CUresult - cuTexRefGetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedPointer = _libraries['libcuda.so'].cuGraphicsResourceGetMappedPointer - cuGraphicsResourceGetMappedPointer.restype = CUresult - cuGraphicsResourceGetMappedPointer.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUgraphicsResource] -except AttributeError: - pass -try: - cuCtxDestroy = _libraries['libcuda.so'].cuCtxDestroy - cuCtxDestroy.restype = CUresult - cuCtxDestroy.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPopCurrent = _libraries['libcuda.so'].cuCtxPopCurrent - cuCtxPopCurrent.restype = CUresult - cuCtxPopCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxPushCurrent = _libraries['libcuda.so'].cuCtxPushCurrent - cuCtxPushCurrent.restype = CUresult - cuCtxPushCurrent.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuStreamDestroy = _libraries['libcuda.so'].cuStreamDestroy - cuStreamDestroy.restype = CUresult - cuStreamDestroy.argtypes = [CUstream] -except AttributeError: - pass -try: - cuEventDestroy = _libraries['libcuda.so'].cuEventDestroy - cuEventDestroy.restype = CUresult - cuEventDestroy.argtypes = [CUevent] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRelease = _libraries['libcuda.so'].cuDevicePrimaryCtxRelease - cuDevicePrimaryCtxRelease.restype = CUresult - cuDevicePrimaryCtxRelease.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxReset = _libraries['libcuda.so'].cuDevicePrimaryCtxReset - cuDevicePrimaryCtxReset.restype = CUresult - cuDevicePrimaryCtxReset.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxSetFlags = _libraries['libcuda.so'].cuDevicePrimaryCtxSetFlags - cuDevicePrimaryCtxSetFlags.restype = CUresult - cuDevicePrimaryCtxSetFlags.argtypes = [CUdevice, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoD_v2 = _libraries['libcuda.so'].cuMemcpyHtoD_v2 - cuMemcpyHtoD_v2.restype = CUresult - cuMemcpyHtoD_v2.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyDtoH_v2 = _libraries['libcuda.so'].cuMemcpyDtoH_v2 - cuMemcpyDtoH_v2.restype = CUresult - cuMemcpyDtoH_v2.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoD_v2 = _libraries['libcuda.so'].cuMemcpyDtoD_v2 - cuMemcpyDtoD_v2.restype = CUresult - cuMemcpyDtoD_v2.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoA_v2 = _libraries['libcuda.so'].cuMemcpyDtoA_v2 - cuMemcpyDtoA_v2.restype = CUresult - cuMemcpyDtoA_v2.argtypes = [CUarray, size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoD_v2 = _libraries['libcuda.so'].cuMemcpyAtoD_v2 - cuMemcpyAtoD_v2.restype = CUresult - cuMemcpyAtoD_v2.argtypes = [CUdeviceptr, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoA_v2 = _libraries['libcuda.so'].cuMemcpyHtoA_v2 - cuMemcpyHtoA_v2.restype = CUresult - cuMemcpyHtoA_v2.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyAtoH_v2 = _libraries['libcuda.so'].cuMemcpyAtoH_v2 - cuMemcpyAtoH_v2.restype = CUresult - cuMemcpyAtoH_v2.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoA_v2 = _libraries['libcuda.so'].cuMemcpyAtoA_v2 - cuMemcpyAtoA_v2.restype = CUresult - cuMemcpyAtoA_v2.argtypes = [CUarray, size_t, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync_v2 = _libraries['libcuda.so'].cuMemcpyHtoAAsync_v2 - cuMemcpyHtoAAsync_v2.restype = CUresult - cuMemcpyHtoAAsync_v2.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync_v2 = _libraries['libcuda.so'].cuMemcpyAtoHAsync_v2 - cuMemcpyAtoHAsync_v2.restype = CUresult - cuMemcpyAtoHAsync_v2.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2D_v2 = _libraries['libcuda.so'].cuMemcpy2D_v2 - cuMemcpy2D_v2.restype = CUresult - cuMemcpy2D_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned_v2 = _libraries['libcuda.so'].cuMemcpy2DUnaligned_v2 - cuMemcpy2DUnaligned_v2.restype = CUresult - cuMemcpy2DUnaligned_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy3D_v2 = _libraries['libcuda.so'].cuMemcpy3D_v2 - cuMemcpy3D_v2.restype = CUresult - cuMemcpy3D_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync_v2 = _libraries['libcuda.so'].cuMemcpyHtoDAsync_v2 - cuMemcpyHtoDAsync_v2.restype = CUresult - cuMemcpyHtoDAsync_v2.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync_v2 = _libraries['libcuda.so'].cuMemcpyDtoHAsync_v2 - cuMemcpyDtoHAsync_v2.restype = CUresult - cuMemcpyDtoHAsync_v2.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync_v2 = _libraries['libcuda.so'].cuMemcpyDtoDAsync_v2 - cuMemcpyDtoDAsync_v2.restype = CUresult - cuMemcpyDtoDAsync_v2.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync_v2 = _libraries['libcuda.so'].cuMemcpy2DAsync_v2 - cuMemcpy2DAsync_v2.restype = CUresult - cuMemcpy2DAsync_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync_v2 = _libraries['libcuda.so'].cuMemcpy3DAsync_v2 - cuMemcpy3DAsync_v2.restype = CUresult - cuMemcpy3DAsync_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8_v2 = _libraries['libcuda.so'].cuMemsetD8_v2 - cuMemsetD8_v2.restype = CUresult - cuMemsetD8_v2.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - cuMemsetD16_v2 = _libraries['libcuda.so'].cuMemsetD16_v2 - cuMemsetD16_v2.restype = CUresult - cuMemsetD16_v2.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - cuMemsetD32_v2 = _libraries['libcuda.so'].cuMemsetD32_v2 - cuMemsetD32_v2.restype = CUresult - cuMemsetD32_v2.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t] -except AttributeError: - pass -try: - cuMemsetD2D8_v2 = _libraries['libcuda.so'].cuMemsetD2D8_v2 - cuMemsetD2D8_v2.restype = CUresult - cuMemsetD2D8_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D16_v2 = _libraries['libcuda.so'].cuMemsetD2D16_v2 - cuMemsetD2D16_v2.restype = CUresult - cuMemsetD2D16_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D32_v2 = _libraries['libcuda.so'].cuMemsetD2D32_v2 - cuMemsetD2D32_v2.restype = CUresult - cuMemsetD2D32_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpy = _libraries['libcuda.so'].cuMemcpy - cuMemcpy.restype = CUresult - cuMemcpy.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAsync = _libraries['libcuda.so'].cuMemcpyAsync - cuMemcpyAsync.restype = CUresult - cuMemcpyAsync.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyPeer = _libraries['libcuda.so'].cuMemcpyPeer - cuMemcpyPeer.restype = CUresult - cuMemcpyPeer.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] -except AttributeError: - pass -try: - cuMemcpyPeerAsync = _libraries['libcuda.so'].cuMemcpyPeerAsync - cuMemcpyPeerAsync.restype = CUresult - cuMemcpyPeerAsync.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy3DPeer = _libraries['libcuda.so'].cuMemcpy3DPeer - cuMemcpy3DPeer.restype = CUresult - cuMemcpy3DPeer.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st)] -except AttributeError: - pass -try: - cuMemcpy3DPeerAsync = _libraries['libcuda.so'].cuMemcpy3DPeerAsync - cuMemcpy3DPeerAsync.restype = CUresult - cuMemcpy3DPeerAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8Async = _libraries['libcuda.so'].cuMemsetD8Async - cuMemsetD8Async.restype = CUresult - cuMemsetD8Async.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD16Async = _libraries['libcuda.so'].cuMemsetD16Async - cuMemsetD16Async.restype = CUresult - cuMemsetD16Async.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD32Async = _libraries['libcuda.so'].cuMemsetD32Async - cuMemsetD32Async.restype = CUresult - cuMemsetD32Async.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D8Async = _libraries['libcuda.so'].cuMemsetD2D8Async - cuMemsetD2D8Async.restype = CUresult - cuMemsetD2D8Async.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D16Async = _libraries['libcuda.so'].cuMemsetD2D16Async - cuMemsetD2D16Async.restype = CUresult - cuMemsetD2D16Async.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D32Async = _libraries['libcuda.so'].cuMemsetD2D32Async - cuMemsetD2D32Async.restype = CUresult - cuMemsetD2D32Async.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuStreamGetPriority = _libraries['libcuda.so'].cuStreamGetPriority - cuStreamGetPriority.restype = CUresult - cuStreamGetPriority.argtypes = [CUstream, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuStreamGetId = _libraries['libcuda.so'].cuStreamGetId - cuStreamGetId.restype = CUresult - cuStreamGetId.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetFlags = _libraries['libcuda.so'].cuStreamGetFlags - cuStreamGetFlags.restype = CUresult - cuStreamGetFlags.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuStreamGetCtx = _libraries['libcuda.so'].cuStreamGetCtx - cuStreamGetCtx.restype = CUresult - cuStreamGetCtx.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuStreamWaitEvent = _libraries['libcuda.so'].cuStreamWaitEvent - cuStreamWaitEvent.restype = CUresult - cuStreamWaitEvent.argtypes = [CUstream, CUevent, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAddCallback = _libraries['libcuda.so'].cuStreamAddCallback - cuStreamAddCallback.restype = CUresult - cuStreamAddCallback.argtypes = [CUstream, CUstreamCallback, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAttachMemAsync = _libraries['libcuda.so'].cuStreamAttachMemAsync - cuStreamAttachMemAsync.restype = CUresult - cuStreamAttachMemAsync.argtypes = [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamQuery = _libraries['libcuda.so'].cuStreamQuery - cuStreamQuery.restype = CUresult - cuStreamQuery.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamSynchronize = _libraries['libcuda.so'].cuStreamSynchronize - cuStreamSynchronize.restype = CUresult - cuStreamSynchronize.argtypes = [CUstream] -except AttributeError: - pass -try: - cuEventRecord = _libraries['libcuda.so'].cuEventRecord - cuEventRecord.restype = CUresult - cuEventRecord.argtypes = [CUevent, CUstream] -except AttributeError: - pass -try: - cuEventRecordWithFlags = _libraries['libcuda.so'].cuEventRecordWithFlags - cuEventRecordWithFlags.restype = CUresult - cuEventRecordWithFlags.argtypes = [CUevent, CUstream, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunchKernel = _libraries['libcuda.so'].cuLaunchKernel - cuLaunchKernel.restype = CUresult - cuLaunchKernel.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchKernelEx = _libraries['libcuda.so'].cuLaunchKernelEx - cuLaunchKernelEx.restype = CUresult - cuLaunchKernelEx.argtypes = [ctypes.POINTER(struct_CUlaunchConfig_st), CUfunction, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchHostFunc = _libraries['libcuda.so'].cuLaunchHostFunc - cuLaunchHostFunc.restype = CUresult - cuLaunchHostFunc.argtypes = [CUstream, CUhostFn, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuGraphicsMapResources = _libraries['libcuda.so'].cuGraphicsMapResources - cuGraphicsMapResources.restype = CUresult - cuGraphicsMapResources.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGraphicsUnmapResources = _libraries['libcuda.so'].cuGraphicsUnmapResources - cuGraphicsUnmapResources.restype = CUresult - cuGraphicsUnmapResources.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuStreamWriteValue32 = _libraries['libcuda.so'].cuStreamWriteValue32 - cuStreamWriteValue32.restype = CUresult - cuStreamWriteValue32.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32 = _libraries['libcuda.so'].cuStreamWaitValue32 - cuStreamWaitValue32.restype = CUresult - cuStreamWaitValue32.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64 = _libraries['libcuda.so'].cuStreamWriteValue64 - cuStreamWriteValue64.restype = CUresult - cuStreamWriteValue64.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64 = _libraries['libcuda.so'].cuStreamWaitValue64 - cuStreamWaitValue64.restype = CUresult - cuStreamWaitValue64.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp = _libraries['libcuda.so'].cuStreamBatchMemOp - cuStreamBatchMemOp.restype = CUresult - cuStreamBatchMemOp.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_ptsz = _libraries['libcuda.so'].cuStreamWriteValue32_ptsz - cuStreamWriteValue32_ptsz.restype = CUresult - cuStreamWriteValue32_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32_ptsz = _libraries['libcuda.so'].cuStreamWaitValue32_ptsz - cuStreamWaitValue32_ptsz.restype = CUresult - cuStreamWaitValue32_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_ptsz = _libraries['libcuda.so'].cuStreamWriteValue64_ptsz - cuStreamWriteValue64_ptsz.restype = CUresult - cuStreamWriteValue64_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_ptsz = _libraries['libcuda.so'].cuStreamWaitValue64_ptsz - cuStreamWaitValue64_ptsz.restype = CUresult - cuStreamWaitValue64_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_ptsz = _libraries['libcuda.so'].cuStreamBatchMemOp_ptsz - cuStreamBatchMemOp_ptsz.restype = CUresult - cuStreamBatchMemOp_ptsz.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_v2 = _libraries['libcuda.so'].cuStreamWriteValue32_v2 - cuStreamWriteValue32_v2.restype = CUresult - cuStreamWriteValue32_v2.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32_v2 = _libraries['libcuda.so'].cuStreamWaitValue32_v2 - cuStreamWaitValue32_v2.restype = CUresult - cuStreamWaitValue32_v2.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_v2 = _libraries['libcuda.so'].cuStreamWriteValue64_v2 - cuStreamWriteValue64_v2.restype = CUresult - cuStreamWriteValue64_v2.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_v2 = _libraries['libcuda.so'].cuStreamWaitValue64_v2 - cuStreamWaitValue64_v2.restype = CUresult - cuStreamWaitValue64_v2.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_v2 = _libraries['libcuda.so'].cuStreamBatchMemOp_v2 - cuStreamBatchMemOp_v2.restype = CUresult - cuStreamBatchMemOp_v2.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemPrefetchAsync = _libraries['libcuda.so'].cuMemPrefetchAsync - cuMemPrefetchAsync.restype = CUresult - cuMemPrefetchAsync.argtypes = [CUdeviceptr, size_t, CUdevice, CUstream] -except AttributeError: - pass -try: - cuLaunchCooperativeKernel = _libraries['libcuda.so'].cuLaunchCooperativeKernel - cuLaunchCooperativeKernel.restype = CUresult - cuLaunchCooperativeKernel.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuSignalExternalSemaphoresAsync = _libraries['libcuda.so'].cuSignalExternalSemaphoresAsync - cuSignalExternalSemaphoresAsync.restype = CUresult - cuSignalExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuWaitExternalSemaphoresAsync = _libraries['libcuda.so'].cuWaitExternalSemaphoresAsync - cuWaitExternalSemaphoresAsync.restype = CUresult - cuWaitExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture = _libraries['libcuda.so'].cuStreamBeginCapture - cuStreamBeginCapture.restype = CUresult - cuStreamBeginCapture.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture_ptsz = _libraries['libcuda.so'].cuStreamBeginCapture_ptsz - cuStreamBeginCapture_ptsz.restype = CUresult - cuStreamBeginCapture_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture_v2 = _libraries['libcuda.so'].cuStreamBeginCapture_v2 - cuStreamBeginCapture_v2.restype = CUresult - cuStreamBeginCapture_v2.argtypes = [CUstream, CUstreamCaptureMode] -except AttributeError: - pass -try: - cuStreamEndCapture = _libraries['libcuda.so'].cuStreamEndCapture - cuStreamEndCapture.restype = CUresult - cuStreamEndCapture.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuStreamIsCapturing = _libraries['libcuda.so'].cuStreamIsCapturing - cuStreamIsCapturing.restype = CUresult - cuStreamIsCapturing.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo = _libraries['libcuda.so'].cuStreamGetCaptureInfo - cuStreamGetCaptureInfo.restype = CUresult - cuStreamGetCaptureInfo.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_ptsz = _libraries['libcuda.so'].cuStreamGetCaptureInfo_ptsz - cuStreamGetCaptureInfo_ptsz.restype = CUresult - cuStreamGetCaptureInfo_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_v2 = _libraries['libcuda.so'].cuStreamGetCaptureInfo_v2 - cuStreamGetCaptureInfo_v2.restype = CUresult - cuStreamGetCaptureInfo_v2.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphAddKernelNode = _libraries['libcuda.so'].cuGraphAddKernelNode - cuGraphAddKernelNode.restype = CUresult - cuGraphAddKernelNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeGetParams = _libraries['libcuda.so'].cuGraphKernelNodeGetParams - cuGraphKernelNodeGetParams.restype = CUresult - cuGraphKernelNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetParams = _libraries['libcuda.so'].cuGraphKernelNodeSetParams - cuGraphKernelNodeSetParams.restype = CUresult - cuGraphKernelNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecKernelNodeSetParams = _libraries['libcuda.so'].cuGraphExecKernelNodeSetParams - cuGraphExecKernelNodeSetParams.restype = CUresult - cuGraphExecKernelNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphInstantiateWithParams = _libraries['libcuda.so'].cuGraphInstantiateWithParams - cuGraphInstantiateWithParams.restype = CUresult - cuGraphInstantiateWithParams.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecUpdate = _libraries['libcuda.so'].cuGraphExecUpdate - cuGraphExecUpdate.restype = CUresult - cuGraphExecUpdate.argtypes = [CUgraphExec, CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(CUgraphExecUpdateResult_enum)] -except AttributeError: - pass -try: - cuGraphUpload = _libraries['libcuda.so'].cuGraphUpload - cuGraphUpload.restype = CUresult - cuGraphUpload.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphLaunch = _libraries['libcuda.so'].cuGraphLaunch - cuGraphLaunch.restype = CUresult - cuGraphLaunch.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuStreamCopyAttributes = _libraries['libcuda.so'].cuStreamCopyAttributes - cuStreamCopyAttributes.restype = CUresult - cuStreamCopyAttributes.argtypes = [CUstream, CUstream] -except AttributeError: - pass -try: - cuStreamGetAttribute = _libraries['libcuda.so'].cuStreamGetAttribute - cuStreamGetAttribute.restype = CUresult - cuStreamGetAttribute.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuStreamSetAttribute = _libraries['libcuda.so'].cuStreamSetAttribute - cuStreamSetAttribute.restype = CUresult - cuStreamSetAttribute.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuIpcOpenMemHandle = _libraries['libcuda.so'].cuIpcOpenMemHandle - cuIpcOpenMemHandle.restype = CUresult - cuIpcOpenMemHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUipcMemHandle, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphInstantiate = _libraries['libcuda.so'].cuGraphInstantiate - cuGraphInstantiate.restype = CUresult - cuGraphInstantiate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - cuGraphInstantiate_v2 = _libraries['libcuda.so'].cuGraphInstantiate_v2 - cuGraphInstantiate_v2.restype = CUresult - cuGraphInstantiate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - cuMemMapArrayAsync = _libraries['libcuda.so'].cuMemMapArrayAsync - cuMemMapArrayAsync.restype = CUresult - cuMemMapArrayAsync.argtypes = [ctypes.POINTER(struct_CUarrayMapInfo_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemFreeAsync = _libraries['libcuda.so'].cuMemFreeAsync - cuMemFreeAsync.restype = CUresult - cuMemFreeAsync.argtypes = [CUdeviceptr, CUstream] -except AttributeError: - pass -try: - cuMemAllocAsync = _libraries['libcuda.so'].cuMemAllocAsync - cuMemAllocAsync.restype = CUresult - cuMemAllocAsync.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUstream] -except AttributeError: - pass -try: - cuMemAllocFromPoolAsync = _libraries['libcuda.so'].cuMemAllocFromPoolAsync - cuMemAllocFromPoolAsync.restype = CUresult - cuMemAllocFromPoolAsync.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUmemoryPool, CUstream] -except AttributeError: - pass -try: - cuStreamUpdateCaptureDependencies = _libraries['libcuda.so'].cuStreamUpdateCaptureDependencies - cuStreamUpdateCaptureDependencies.restype = CUresult - cuStreamUpdateCaptureDependencies.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGetProcAddress = _libraries['libcuda.so'].cuGetProcAddress - cuGetProcAddress.restype = CUresult - cuGetProcAddress.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_int32, cuuint64_t] -except AttributeError: - pass -__all__ = \ - ['CUDA_ARRAY3D_DESCRIPTOR', 'CUDA_ARRAY3D_DESCRIPTOR_v1', - 'CUDA_ARRAY3D_DESCRIPTOR_v2', 'CUDA_ARRAY_DESCRIPTOR', - 'CUDA_ARRAY_DESCRIPTOR_v1', 'CUDA_ARRAY_DESCRIPTOR_v2', - 'CUDA_ARRAY_MEMORY_REQUIREMENTS', - 'CUDA_ARRAY_MEMORY_REQUIREMENTS_v1', - 'CUDA_ARRAY_SPARSE_PROPERTIES', 'CUDA_ARRAY_SPARSE_PROPERTIES_v1', - 'CUDA_BATCH_MEM_OP_NODE_PARAMS', 'CUDA_ERROR_ALREADY_ACQUIRED', - 'CUDA_ERROR_ALREADY_MAPPED', 'CUDA_ERROR_ARRAY_IS_MAPPED', - 'CUDA_ERROR_ASSERT', 'CUDA_ERROR_CAPTURED_EVENT', - 'CUDA_ERROR_CDP_NOT_SUPPORTED', 'CUDA_ERROR_CDP_VERSION_MISMATCH', - 'CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE', - 'CUDA_ERROR_CONTEXT_ALREADY_CURRENT', - 'CUDA_ERROR_CONTEXT_ALREADY_IN_USE', - 'CUDA_ERROR_CONTEXT_IS_DESTROYED', - 'CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE', - 'CUDA_ERROR_DEINITIALIZED', 'CUDA_ERROR_DEVICE_NOT_LICENSED', - 'CUDA_ERROR_DEVICE_UNAVAILABLE', 'CUDA_ERROR_ECC_UNCORRECTABLE', - 'CUDA_ERROR_EXTERNAL_DEVICE', 'CUDA_ERROR_FILE_NOT_FOUND', - 'CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE', - 'CUDA_ERROR_HARDWARE_STACK_ERROR', - 'CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED', - 'CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED', - 'CUDA_ERROR_ILLEGAL_ADDRESS', 'CUDA_ERROR_ILLEGAL_INSTRUCTION', - 'CUDA_ERROR_ILLEGAL_STATE', 'CUDA_ERROR_INVALID_ADDRESS_SPACE', - 'CUDA_ERROR_INVALID_CLUSTER_SIZE', 'CUDA_ERROR_INVALID_CONTEXT', - 'CUDA_ERROR_INVALID_DEVICE', - 'CUDA_ERROR_INVALID_GRAPHICS_CONTEXT', - 'CUDA_ERROR_INVALID_HANDLE', 'CUDA_ERROR_INVALID_IMAGE', - 'CUDA_ERROR_INVALID_PC', 'CUDA_ERROR_INVALID_PTX', - 'CUDA_ERROR_INVALID_SOURCE', 'CUDA_ERROR_INVALID_VALUE', - 'CUDA_ERROR_JIT_COMPILATION_DISABLED', - 'CUDA_ERROR_JIT_COMPILER_NOT_FOUND', 'CUDA_ERROR_LAUNCH_FAILED', - 'CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING', - 'CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES', 'CUDA_ERROR_LAUNCH_TIMEOUT', - 'CUDA_ERROR_MAP_FAILED', 'CUDA_ERROR_MISALIGNED_ADDRESS', - 'CUDA_ERROR_MPS_CLIENT_TERMINATED', - 'CUDA_ERROR_MPS_CONNECTION_FAILED', - 'CUDA_ERROR_MPS_MAX_CLIENTS_REACHED', - 'CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED', - 'CUDA_ERROR_MPS_RPC_FAILURE', 'CUDA_ERROR_MPS_SERVER_NOT_READY', - 'CUDA_ERROR_NOT_FOUND', 'CUDA_ERROR_NOT_INITIALIZED', - 'CUDA_ERROR_NOT_MAPPED', 'CUDA_ERROR_NOT_MAPPED_AS_ARRAY', - 'CUDA_ERROR_NOT_MAPPED_AS_POINTER', 'CUDA_ERROR_NOT_PERMITTED', - 'CUDA_ERROR_NOT_READY', 'CUDA_ERROR_NOT_SUPPORTED', - 'CUDA_ERROR_NO_BINARY_FOR_GPU', 'CUDA_ERROR_NO_DEVICE', - 'CUDA_ERROR_NVLINK_UNCORRECTABLE', 'CUDA_ERROR_OPERATING_SYSTEM', - 'CUDA_ERROR_OUT_OF_MEMORY', - 'CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED', - 'CUDA_ERROR_PEER_ACCESS_NOT_ENABLED', - 'CUDA_ERROR_PEER_ACCESS_UNSUPPORTED', - 'CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE', - 'CUDA_ERROR_PROFILER_ALREADY_STARTED', - 'CUDA_ERROR_PROFILER_ALREADY_STOPPED', - 'CUDA_ERROR_PROFILER_DISABLED', - 'CUDA_ERROR_PROFILER_NOT_INITIALIZED', - 'CUDA_ERROR_SHARED_OBJECT_INIT_FAILED', - 'CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND', - 'CUDA_ERROR_STREAM_CAPTURE_IMPLICIT', - 'CUDA_ERROR_STREAM_CAPTURE_INVALIDATED', - 'CUDA_ERROR_STREAM_CAPTURE_ISOLATION', - 'CUDA_ERROR_STREAM_CAPTURE_MERGE', - 'CUDA_ERROR_STREAM_CAPTURE_UNJOINED', - 'CUDA_ERROR_STREAM_CAPTURE_UNMATCHED', - 'CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED', - 'CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD', - 'CUDA_ERROR_STUB_LIBRARY', 'CUDA_ERROR_SYSTEM_DRIVER_MISMATCH', - 'CUDA_ERROR_SYSTEM_NOT_READY', 'CUDA_ERROR_TIMEOUT', - 'CUDA_ERROR_TOO_MANY_PEERS', 'CUDA_ERROR_UNKNOWN', - 'CUDA_ERROR_UNMAP_FAILED', 'CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY', - 'CUDA_ERROR_UNSUPPORTED_LIMIT', - 'CUDA_ERROR_UNSUPPORTED_PTX_VERSION', - 'CUDA_EXTERNAL_MEMORY_BUFFER_DESC', - 'CUDA_EXTERNAL_MEMORY_BUFFER_DESC_v1', - 'CUDA_EXTERNAL_MEMORY_HANDLE_DESC', - 'CUDA_EXTERNAL_MEMORY_HANDLE_DESC_v1', - 'CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC', - 'CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_v1', - 'CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC', - 'CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_v1', - 'CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS', - 'CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_v1', - 'CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS', - 'CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_v1', - 'CUDA_EXT_SEM_SIGNAL_NODE_PARAMS', - 'CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_v1', - 'CUDA_EXT_SEM_WAIT_NODE_PARAMS', - 'CUDA_EXT_SEM_WAIT_NODE_PARAMS_v1', - 'CUDA_GRAPH_INSTANTIATE_ERROR', - 'CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH', - 'CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH', - 'CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD', - 'CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY', - 'CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE', - 'CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED', - 'CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED', - 'CUDA_GRAPH_INSTANTIATE_PARAMS', 'CUDA_GRAPH_INSTANTIATE_SUCCESS', - 'CUDA_HOST_NODE_PARAMS', 'CUDA_HOST_NODE_PARAMS_v1', - 'CUDA_KERNEL_NODE_PARAMS', 'CUDA_KERNEL_NODE_PARAMS_v1', - 'CUDA_KERNEL_NODE_PARAMS_v2', 'CUDA_LAUNCH_PARAMS', - 'CUDA_LAUNCH_PARAMS_v1', 'CUDA_MEMCPY2D', 'CUDA_MEMCPY2D_v1', - 'CUDA_MEMCPY2D_v2', 'CUDA_MEMCPY3D', 'CUDA_MEMCPY3D_PEER', - 'CUDA_MEMCPY3D_PEER_v1', 'CUDA_MEMCPY3D_v1', 'CUDA_MEMCPY3D_v2', - 'CUDA_MEMSET_NODE_PARAMS', 'CUDA_MEMSET_NODE_PARAMS_v1', - 'CUDA_MEM_ALLOC_NODE_PARAMS', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS__enumvalues', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum', - 'CUDA_POINTER_ATTRIBUTE_P2P_TOKENS', - 'CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_v1', 'CUDA_RESOURCE_DESC', - 'CUDA_RESOURCE_DESC_v1', 'CUDA_RESOURCE_VIEW_DESC', - 'CUDA_RESOURCE_VIEW_DESC_v1', 'CUDA_SUCCESS', 'CUDA_TEXTURE_DESC', - 'CUDA_TEXTURE_DESC_v1', 'CUGPUDirectRDMAWritesOrdering', - 'CUGPUDirectRDMAWritesOrdering__enumvalues', - 'CUGPUDirectRDMAWritesOrdering_enum', 'CU_ACCESS_PROPERTY_NORMAL', - 'CU_ACCESS_PROPERTY_PERSISTING', 'CU_ACCESS_PROPERTY_STREAMING', - 'CU_AD_FORMAT_BC1_UNORM', 'CU_AD_FORMAT_BC1_UNORM_SRGB', - 'CU_AD_FORMAT_BC2_UNORM', 'CU_AD_FORMAT_BC2_UNORM_SRGB', - 'CU_AD_FORMAT_BC3_UNORM', 'CU_AD_FORMAT_BC3_UNORM_SRGB', - 'CU_AD_FORMAT_BC4_SNORM', 'CU_AD_FORMAT_BC4_UNORM', - 'CU_AD_FORMAT_BC5_SNORM', 'CU_AD_FORMAT_BC5_UNORM', - 'CU_AD_FORMAT_BC6H_SF16', 'CU_AD_FORMAT_BC6H_UF16', - 'CU_AD_FORMAT_BC7_UNORM', 'CU_AD_FORMAT_BC7_UNORM_SRGB', - 'CU_AD_FORMAT_FLOAT', 'CU_AD_FORMAT_HALF', 'CU_AD_FORMAT_NV12', - 'CU_AD_FORMAT_SIGNED_INT16', 'CU_AD_FORMAT_SIGNED_INT32', - 'CU_AD_FORMAT_SIGNED_INT8', 'CU_AD_FORMAT_SNORM_INT16X1', - 'CU_AD_FORMAT_SNORM_INT16X2', 'CU_AD_FORMAT_SNORM_INT16X4', - 'CU_AD_FORMAT_SNORM_INT8X1', 'CU_AD_FORMAT_SNORM_INT8X2', - 'CU_AD_FORMAT_SNORM_INT8X4', 'CU_AD_FORMAT_UNORM_INT16X1', - 'CU_AD_FORMAT_UNORM_INT16X2', 'CU_AD_FORMAT_UNORM_INT16X4', - 'CU_AD_FORMAT_UNORM_INT8X1', 'CU_AD_FORMAT_UNORM_INT8X2', - 'CU_AD_FORMAT_UNORM_INT8X4', 'CU_AD_FORMAT_UNSIGNED_INT16', - 'CU_AD_FORMAT_UNSIGNED_INT32', 'CU_AD_FORMAT_UNSIGNED_INT8', - 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL', - 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL', - 'CU_CLUSTER_SCHEDULING_POLICY_DEFAULT', - 'CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING', - 'CU_CLUSTER_SCHEDULING_POLICY_SPREAD', 'CU_COMPUTEMODE_DEFAULT', - 'CU_COMPUTEMODE_EXCLUSIVE_PROCESS', 'CU_COMPUTEMODE_PROHIBITED', - 'CU_CTX_BLOCKING_SYNC', 'CU_CTX_FLAGS_MASK', - 'CU_CTX_LMEM_RESIZE_TO_MAX', 'CU_CTX_MAP_HOST', - 'CU_CTX_SCHED_AUTO', 'CU_CTX_SCHED_BLOCKING_SYNC', - 'CU_CTX_SCHED_MASK', 'CU_CTX_SCHED_SPIN', 'CU_CTX_SCHED_YIELD', - 'CU_CUBEMAP_FACE_NEGATIVE_X', 'CU_CUBEMAP_FACE_NEGATIVE_Y', - 'CU_CUBEMAP_FACE_NEGATIVE_Z', 'CU_CUBEMAP_FACE_POSITIVE_X', - 'CU_CUBEMAP_FACE_POSITIVE_Y', 'CU_CUBEMAP_FACE_POSITIVE_Z', - 'CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT', - 'CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES', - 'CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY', - 'CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1', - 'CU_DEVICE_ATTRIBUTE_CLOCK_RATE', - 'CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_MODE', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS', - 'CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS', - 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST', - 'CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_ECC_ENABLED', - 'CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING', - 'CU_DEVICE_ATTRIBUTE_GPU_OVERLAP', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_INTEGRATED', - 'CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT', - 'CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE', - 'CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY', 'CU_DEVICE_ATTRIBUTE_MAX', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z', - 'CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE', - 'CU_DEVICE_ATTRIBUTE_MAX_PITCH', - 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE', - 'CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES', - 'CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT', - 'CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT', - 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD', - 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID', - 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS', - 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES', - 'CU_DEVICE_ATTRIBUTE_PCI_BUS_ID', - 'CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID', - 'CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID', - 'CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO', - 'CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TCC_DRIVER', - 'CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY', - 'CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING', - 'CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS', - 'CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_WARP_SIZE', - 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK', - 'CU_EVENT_BLOCKING_SYNC', 'CU_EVENT_DEFAULT', - 'CU_EVENT_DISABLE_TIMING', 'CU_EVENT_INTERPROCESS', - 'CU_EVENT_RECORD_DEFAULT', 'CU_EVENT_RECORD_EXTERNAL', - 'CU_EVENT_SCHED_AUTO', 'CU_EVENT_SCHED_BLOCKING_SYNC', - 'CU_EVENT_SCHED_SPIN', 'CU_EVENT_SCHED_YIELD', - 'CU_EVENT_WAIT_DEFAULT', 'CU_EVENT_WAIT_EXTERNAL', - 'CU_EXEC_AFFINITY_TYPE_MAX', 'CU_EXEC_AFFINITY_TYPE_SM_COUNT', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER', - 'CU_FUNC_ATTRIBUTE_BINARY_VERSION', - 'CU_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 'CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 'CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET', - 'CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 'CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 'CU_FUNC_ATTRIBUTE_MAX', - 'CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 'CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED', - 'CU_FUNC_ATTRIBUTE_NUM_REGS', - 'CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 'CU_FUNC_ATTRIBUTE_PTX_VERSION', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH', - 'CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 'CU_FUNC_CACHE_PREFER_EQUAL', 'CU_FUNC_CACHE_PREFER_L1', - 'CU_FUNC_CACHE_PREFER_NONE', 'CU_FUNC_CACHE_PREFER_SHARED', - 'CU_GET_PROC_ADDRESS_DEFAULT', - 'CU_GET_PROC_ADDRESS_LEGACY_STREAM', - 'CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM', - 'CU_GET_PROC_ADDRESS_SUCCESS', - 'CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', - 'CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD', - 'CU_GRAPHICS_REGISTER_FLAGS_NONE', - 'CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY', - 'CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST', - 'CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER', - 'CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD', - 'CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE', 'CU_GRAPH_EXEC_UPDATE_ERROR', - 'CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE', - 'CU_GRAPH_EXEC_UPDATE_SUCCESS', - 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT', - 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH', - 'CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT', - 'CU_GRAPH_MEM_ATTR_USED_MEM_HIGH', - 'CU_GRAPH_NODE_TYPE_BATCH_MEM_OP', 'CU_GRAPH_NODE_TYPE_EMPTY', - 'CU_GRAPH_NODE_TYPE_EVENT_RECORD', - 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL', - 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT', 'CU_GRAPH_NODE_TYPE_GRAPH', - 'CU_GRAPH_NODE_TYPE_HOST', 'CU_GRAPH_NODE_TYPE_KERNEL', - 'CU_GRAPH_NODE_TYPE_MEMCPY', 'CU_GRAPH_NODE_TYPE_MEMSET', - 'CU_GRAPH_NODE_TYPE_MEM_ALLOC', 'CU_GRAPH_NODE_TYPE_MEM_FREE', - 'CU_GRAPH_NODE_TYPE_WAIT_EVENT', 'CU_GRAPH_USER_OBJECT_MOVE', - 'CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS', 'CU_JIT_CACHE_MODE', - 'CU_JIT_CACHE_OPTION_CA', 'CU_JIT_CACHE_OPTION_CG', - 'CU_JIT_CACHE_OPTION_NONE', 'CU_JIT_ERROR_LOG_BUFFER', - 'CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', 'CU_JIT_FALLBACK_STRATEGY', - 'CU_JIT_FAST_COMPILE', 'CU_JIT_FMA', 'CU_JIT_FTZ', - 'CU_JIT_GENERATE_DEBUG_INFO', 'CU_JIT_GENERATE_LINE_INFO', - 'CU_JIT_GLOBAL_SYMBOL_ADDRESSES', 'CU_JIT_GLOBAL_SYMBOL_COUNT', - 'CU_JIT_GLOBAL_SYMBOL_NAMES', 'CU_JIT_INFO_LOG_BUFFER', - 'CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 'CU_JIT_INPUT_CUBIN', - 'CU_JIT_INPUT_FATBINARY', 'CU_JIT_INPUT_LIBRARY', - 'CU_JIT_INPUT_NVVM', 'CU_JIT_INPUT_OBJECT', 'CU_JIT_INPUT_PTX', - 'CU_JIT_LOG_VERBOSE', 'CU_JIT_LTO', 'CU_JIT_MAX_REGISTERS', - 'CU_JIT_NEW_SM3X_OPT', 'CU_JIT_NUM_INPUT_TYPES', - 'CU_JIT_NUM_OPTIONS', 'CU_JIT_OPTIMIZATION_LEVEL', - 'CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES', - 'CU_JIT_POSITION_INDEPENDENT_CODE', 'CU_JIT_PREC_DIV', - 'CU_JIT_PREC_SQRT', 'CU_JIT_REFERENCED_KERNEL_COUNT', - 'CU_JIT_REFERENCED_KERNEL_NAMES', - 'CU_JIT_REFERENCED_VARIABLE_COUNT', - 'CU_JIT_REFERENCED_VARIABLE_NAMES', 'CU_JIT_TARGET', - 'CU_JIT_TARGET_FROM_CUCONTEXT', 'CU_JIT_THREADS_PER_BLOCK', - 'CU_JIT_WALL_TIME', 'CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW', - 'CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION', - 'CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 'CU_LAUNCH_ATTRIBUTE_COOPERATIVE', 'CU_LAUNCH_ATTRIBUTE_IGNORE', - 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN', - 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP', - 'CU_LAUNCH_ATTRIBUTE_PRIORITY', - 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT', - 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION', - 'CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY', - 'CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT', - 'CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE', - 'CU_LIBRARY_BINARY_IS_PRESERVED', - 'CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE', - 'CU_LIBRARY_NUM_OPTIONS', - 'CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT', - 'CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH', 'CU_LIMIT_MALLOC_HEAP_SIZE', - 'CU_LIMIT_MAX', 'CU_LIMIT_MAX_L2_FETCH_GRANULARITY', - 'CU_LIMIT_PERSISTING_L2_CACHE_SIZE', 'CU_LIMIT_PRINTF_FIFO_SIZE', - 'CU_LIMIT_STACK_SIZE', 'CU_MEMORYTYPE_ARRAY', - 'CU_MEMORYTYPE_DEVICE', 'CU_MEMORYTYPE_HOST', - 'CU_MEMORYTYPE_UNIFIED', 'CU_MEMPOOL_ATTR_RELEASE_THRESHOLD', - 'CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT', - 'CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH', - 'CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES', - 'CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC', - 'CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES', - 'CU_MEMPOOL_ATTR_USED_MEM_CURRENT', - 'CU_MEMPOOL_ATTR_USED_MEM_HIGH', 'CU_MEM_ACCESS_FLAGS_PROT_MAX', - 'CU_MEM_ACCESS_FLAGS_PROT_NONE', 'CU_MEM_ACCESS_FLAGS_PROT_READ', - 'CU_MEM_ACCESS_FLAGS_PROT_READWRITE', - 'CU_MEM_ADVISE_SET_ACCESSED_BY', - 'CU_MEM_ADVISE_SET_PREFERRED_LOCATION', - 'CU_MEM_ADVISE_SET_READ_MOSTLY', - 'CU_MEM_ADVISE_UNSET_ACCESSED_BY', - 'CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION', - 'CU_MEM_ADVISE_UNSET_READ_MOSTLY', - 'CU_MEM_ALLOCATION_COMP_GENERIC', 'CU_MEM_ALLOCATION_COMP_NONE', - 'CU_MEM_ALLOCATION_TYPE_INVALID', 'CU_MEM_ALLOCATION_TYPE_MAX', - 'CU_MEM_ALLOCATION_TYPE_PINNED', - 'CU_MEM_ALLOC_GRANULARITY_MINIMUM', - 'CU_MEM_ALLOC_GRANULARITY_RECOMMENDED', 'CU_MEM_ATTACH_GLOBAL', - 'CU_MEM_ATTACH_HOST', 'CU_MEM_ATTACH_SINGLE', - 'CU_MEM_HANDLE_TYPE_GENERIC', 'CU_MEM_HANDLE_TYPE_MAX', - 'CU_MEM_HANDLE_TYPE_NONE', - 'CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR', - 'CU_MEM_HANDLE_TYPE_WIN32', 'CU_MEM_HANDLE_TYPE_WIN32_KMT', - 'CU_MEM_LOCATION_TYPE_DEVICE', 'CU_MEM_LOCATION_TYPE_INVALID', - 'CU_MEM_LOCATION_TYPE_MAX', 'CU_MEM_OPERATION_TYPE_MAP', - 'CU_MEM_OPERATION_TYPE_UNMAP', - 'CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY', - 'CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION', - 'CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION', - 'CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY', - 'CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD', - 'CU_MEM_RANGE_HANDLE_TYPE_MAX', 'CU_MODULE_EAGER_LOADING', - 'CU_MODULE_LAZY_LOADING', 'CU_OCCUPANCY_DEFAULT', - 'CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE', - 'CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 'CU_POINTER_ATTRIBUTE_BUFFER_ID', 'CU_POINTER_ATTRIBUTE_CONTEXT', - 'CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 'CU_POINTER_ATTRIBUTE_DEVICE_POINTER', - 'CU_POINTER_ATTRIBUTE_HOST_POINTER', - 'CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 'CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE', - 'CU_POINTER_ATTRIBUTE_IS_MANAGED', 'CU_POINTER_ATTRIBUTE_MAPPED', - 'CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR', - 'CU_POINTER_ATTRIBUTE_MAPPING_SIZE', - 'CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID', - 'CU_POINTER_ATTRIBUTE_MEMORY_TYPE', - 'CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 'CU_POINTER_ATTRIBUTE_P2P_TOKENS', - 'CU_POINTER_ATTRIBUTE_RANGE_SIZE', - 'CU_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 'CU_POINTER_ATTRIBUTE_SYNC_MEMOPS', 'CU_PREFER_BINARY', - 'CU_PREFER_PTX', 'CU_RESOURCE_TYPE_ARRAY', - 'CU_RESOURCE_TYPE_LINEAR', 'CU_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 'CU_RESOURCE_TYPE_PITCH2D', 'CU_RES_VIEW_FORMAT_FLOAT_1X16', - 'CU_RES_VIEW_FORMAT_FLOAT_1X32', 'CU_RES_VIEW_FORMAT_FLOAT_2X16', - 'CU_RES_VIEW_FORMAT_FLOAT_2X32', 'CU_RES_VIEW_FORMAT_FLOAT_4X16', - 'CU_RES_VIEW_FORMAT_FLOAT_4X32', 'CU_RES_VIEW_FORMAT_NONE', - 'CU_RES_VIEW_FORMAT_SIGNED_BC4', 'CU_RES_VIEW_FORMAT_SIGNED_BC5', - 'CU_RES_VIEW_FORMAT_SIGNED_BC6H', 'CU_RES_VIEW_FORMAT_SINT_1X16', - 'CU_RES_VIEW_FORMAT_SINT_1X32', 'CU_RES_VIEW_FORMAT_SINT_1X8', - 'CU_RES_VIEW_FORMAT_SINT_2X16', 'CU_RES_VIEW_FORMAT_SINT_2X32', - 'CU_RES_VIEW_FORMAT_SINT_2X8', 'CU_RES_VIEW_FORMAT_SINT_4X16', - 'CU_RES_VIEW_FORMAT_SINT_4X32', 'CU_RES_VIEW_FORMAT_SINT_4X8', - 'CU_RES_VIEW_FORMAT_UINT_1X16', 'CU_RES_VIEW_FORMAT_UINT_1X32', - 'CU_RES_VIEW_FORMAT_UINT_1X8', 'CU_RES_VIEW_FORMAT_UINT_2X16', - 'CU_RES_VIEW_FORMAT_UINT_2X32', 'CU_RES_VIEW_FORMAT_UINT_2X8', - 'CU_RES_VIEW_FORMAT_UINT_4X16', 'CU_RES_VIEW_FORMAT_UINT_4X32', - 'CU_RES_VIEW_FORMAT_UINT_4X8', 'CU_RES_VIEW_FORMAT_UNSIGNED_BC1', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC2', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC3', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC4', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC5', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC7', - 'CU_SHAREDMEM_CARVEOUT_DEFAULT', 'CU_SHAREDMEM_CARVEOUT_MAX_L1', - 'CU_SHAREDMEM_CARVEOUT_MAX_SHARED', - 'CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE', - 'CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE', - 'CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE', - 'CU_STREAM_ADD_CAPTURE_DEPENDENCIES', - 'CU_STREAM_CAPTURE_MODE_GLOBAL', 'CU_STREAM_CAPTURE_MODE_RELAXED', - 'CU_STREAM_CAPTURE_MODE_THREAD_LOCAL', - 'CU_STREAM_CAPTURE_STATUS_ACTIVE', - 'CU_STREAM_CAPTURE_STATUS_INVALIDATED', - 'CU_STREAM_CAPTURE_STATUS_NONE', 'CU_STREAM_DEFAULT', - 'CU_STREAM_MEMORY_BARRIER_TYPE_GPU', - 'CU_STREAM_MEMORY_BARRIER_TYPE_SYS', 'CU_STREAM_MEM_OP_BARRIER', - 'CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES', - 'CU_STREAM_MEM_OP_WAIT_VALUE_32', - 'CU_STREAM_MEM_OP_WAIT_VALUE_64', - 'CU_STREAM_MEM_OP_WRITE_VALUE_32', - 'CU_STREAM_MEM_OP_WRITE_VALUE_64', 'CU_STREAM_NON_BLOCKING', - 'CU_STREAM_SET_CAPTURE_DEPENDENCIES', 'CU_STREAM_WAIT_VALUE_AND', - 'CU_STREAM_WAIT_VALUE_EQ', 'CU_STREAM_WAIT_VALUE_FLUSH', - 'CU_STREAM_WAIT_VALUE_GEQ', 'CU_STREAM_WAIT_VALUE_NOR', - 'CU_STREAM_WRITE_VALUE_DEFAULT', - 'CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER', 'CU_SYNC_POLICY_AUTO', - 'CU_SYNC_POLICY_BLOCKING_SYNC', 'CU_SYNC_POLICY_SPIN', - 'CU_SYNC_POLICY_YIELD', 'CU_TARGET_COMPUTE_30', - 'CU_TARGET_COMPUTE_32', 'CU_TARGET_COMPUTE_35', - 'CU_TARGET_COMPUTE_37', 'CU_TARGET_COMPUTE_50', - 'CU_TARGET_COMPUTE_52', 'CU_TARGET_COMPUTE_53', - 'CU_TARGET_COMPUTE_60', 'CU_TARGET_COMPUTE_61', - 'CU_TARGET_COMPUTE_62', 'CU_TARGET_COMPUTE_70', - 'CU_TARGET_COMPUTE_72', 'CU_TARGET_COMPUTE_75', - 'CU_TARGET_COMPUTE_80', 'CU_TARGET_COMPUTE_86', - 'CU_TARGET_COMPUTE_87', 'CU_TARGET_COMPUTE_89', - 'CU_TARGET_COMPUTE_90', 'CU_TARGET_COMPUTE_90A', - 'CU_TENSOR_MAP_DATA_TYPE_BFLOAT16', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT16', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT64', - 'CU_TENSOR_MAP_DATA_TYPE_INT32', 'CU_TENSOR_MAP_DATA_TYPE_INT64', - 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32', - 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ', - 'CU_TENSOR_MAP_DATA_TYPE_UINT16', - 'CU_TENSOR_MAP_DATA_TYPE_UINT32', - 'CU_TENSOR_MAP_DATA_TYPE_UINT64', 'CU_TENSOR_MAP_DATA_TYPE_UINT8', - 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA', - 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE', - 'CU_TENSOR_MAP_INTERLEAVE_16B', 'CU_TENSOR_MAP_INTERLEAVE_32B', - 'CU_TENSOR_MAP_INTERLEAVE_NONE', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_128B', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_256B', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_64B', - 'CU_TENSOR_MAP_L2_PROMOTION_NONE', 'CU_TENSOR_MAP_SWIZZLE_128B', - 'CU_TENSOR_MAP_SWIZZLE_32B', 'CU_TENSOR_MAP_SWIZZLE_64B', - 'CU_TENSOR_MAP_SWIZZLE_NONE', 'CU_TR_ADDRESS_MODE_BORDER', - 'CU_TR_ADDRESS_MODE_CLAMP', 'CU_TR_ADDRESS_MODE_MIRROR', - 'CU_TR_ADDRESS_MODE_WRAP', 'CU_TR_FILTER_MODE_LINEAR', - 'CU_TR_FILTER_MODE_POINT', 'CU_USER_OBJECT_NO_DESTRUCTOR_SYNC', - 'CUaccessPolicyWindow', 'CUaccessPolicyWindow_v1', - 'CUaccessProperty', 'CUaccessProperty__enumvalues', - 'CUaccessProperty_enum', 'CUaddress_mode', - 'CUaddress_mode__enumvalues', 'CUaddress_mode_enum', 'CUarray', - 'CUarrayMapInfo', 'CUarrayMapInfo_v1', - 'CUarraySparseSubresourceType', - 'CUarraySparseSubresourceType__enumvalues', - 'CUarraySparseSubresourceType_enum', 'CUarray_cubemap_face', - 'CUarray_cubemap_face__enumvalues', 'CUarray_cubemap_face_enum', - 'CUarray_format', 'CUarray_format__enumvalues', - 'CUarray_format_enum', 'CUclusterSchedulingPolicy', - 'CUclusterSchedulingPolicy__enumvalues', - 'CUclusterSchedulingPolicy_enum', 'CUcomputemode', - 'CUcomputemode__enumvalues', 'CUcomputemode_enum', 'CUcontext', - 'CUctx_flags', 'CUctx_flags__enumvalues', 'CUctx_flags_enum', - 'CUdevice', 'CUdevice_P2PAttribute', - 'CUdevice_P2PAttribute__enumvalues', 'CUdevice_P2PAttribute_enum', - 'CUdevice_attribute', 'CUdevice_attribute__enumvalues', - 'CUdevice_attribute_enum', 'CUdevice_v1', 'CUdeviceptr', - 'CUdeviceptr_v1', 'CUdeviceptr_v2', 'CUdevprop', 'CUdevprop_v1', - 'CUdriverProcAddressQueryResult', - 'CUdriverProcAddressQueryResult__enumvalues', - 'CUdriverProcAddressQueryResult_enum', - 'CUdriverProcAddress_flags', - 'CUdriverProcAddress_flags__enumvalues', - 'CUdriverProcAddress_flags_enum', 'CUevent', 'CUevent_flags', - 'CUevent_flags__enumvalues', 'CUevent_flags_enum', - 'CUevent_record_flags', 'CUevent_record_flags__enumvalues', - 'CUevent_record_flags_enum', 'CUevent_sched_flags', - 'CUevent_sched_flags__enumvalues', 'CUevent_sched_flags_enum', - 'CUevent_wait_flags', 'CUevent_wait_flags__enumvalues', - 'CUevent_wait_flags_enum', 'CUexecAffinityParam', - 'CUexecAffinityParam_v1', 'CUexecAffinitySmCount', - 'CUexecAffinitySmCount_v1', 'CUexecAffinityType', - 'CUexecAffinityType__enumvalues', 'CUexecAffinityType_enum', - 'CUexternalMemory', 'CUexternalMemoryHandleType', - 'CUexternalMemoryHandleType__enumvalues', - 'CUexternalMemoryHandleType_enum', 'CUexternalSemaphore', - 'CUexternalSemaphoreHandleType', - 'CUexternalSemaphoreHandleType__enumvalues', - 'CUexternalSemaphoreHandleType_enum', 'CUfilter_mode', - 'CUfilter_mode__enumvalues', 'CUfilter_mode_enum', - 'CUflushGPUDirectRDMAWritesOptions', - 'CUflushGPUDirectRDMAWritesOptions__enumvalues', - 'CUflushGPUDirectRDMAWritesOptions_enum', - 'CUflushGPUDirectRDMAWritesScope', - 'CUflushGPUDirectRDMAWritesScope__enumvalues', - 'CUflushGPUDirectRDMAWritesScope_enum', - 'CUflushGPUDirectRDMAWritesTarget', - 'CUflushGPUDirectRDMAWritesTarget__enumvalues', - 'CUflushGPUDirectRDMAWritesTarget_enum', 'CUfunc_cache', - 'CUfunc_cache__enumvalues', 'CUfunc_cache_enum', 'CUfunction', - 'CUfunction_attribute', 'CUfunction_attribute__enumvalues', - 'CUfunction_attribute_enum', 'CUgraph', 'CUgraphDebugDot_flags', - 'CUgraphDebugDot_flags__enumvalues', 'CUgraphDebugDot_flags_enum', - 'CUgraphExec', 'CUgraphExecUpdateResult', - 'CUgraphExecUpdateResultInfo', 'CUgraphExecUpdateResultInfo_v1', - 'CUgraphExecUpdateResult__enumvalues', - 'CUgraphExecUpdateResult_enum', 'CUgraphInstantiateResult', - 'CUgraphInstantiateResult__enumvalues', - 'CUgraphInstantiateResult_enum', 'CUgraphInstantiate_flags', - 'CUgraphInstantiate_flags__enumvalues', - 'CUgraphInstantiate_flags_enum', 'CUgraphMem_attribute', - 'CUgraphMem_attribute__enumvalues', 'CUgraphMem_attribute_enum', - 'CUgraphNode', 'CUgraphNodeType', 'CUgraphNodeType__enumvalues', - 'CUgraphNodeType_enum', 'CUgraphicsMapResourceFlags', - 'CUgraphicsMapResourceFlags__enumvalues', - 'CUgraphicsMapResourceFlags_enum', 'CUgraphicsRegisterFlags', - 'CUgraphicsRegisterFlags__enumvalues', - 'CUgraphicsRegisterFlags_enum', 'CUgraphicsResource', 'CUhostFn', - 'CUipcEventHandle', 'CUipcEventHandle_v1', 'CUipcMemHandle', - 'CUipcMemHandle_v1', 'CUipcMem_flags', - 'CUipcMem_flags__enumvalues', 'CUipcMem_flags_enum', - 'CUjitInputType', 'CUjitInputType__enumvalues', - 'CUjitInputType_enum', 'CUjit_cacheMode', - 'CUjit_cacheMode__enumvalues', 'CUjit_cacheMode_enum', - 'CUjit_fallback', 'CUjit_fallback__enumvalues', - 'CUjit_fallback_enum', 'CUjit_option', 'CUjit_option__enumvalues', - 'CUjit_option_enum', 'CUjit_target', 'CUjit_target__enumvalues', - 'CUjit_target_enum', 'CUkernel', 'CUkernelNodeAttrID', - 'CUkernelNodeAttrID__enumvalues', 'CUkernelNodeAttrValue', - 'CUkernelNodeAttrValue_v1', 'CUlaunchAttribute', - 'CUlaunchAttributeID', 'CUlaunchAttributeID__enumvalues', - 'CUlaunchAttributeID_enum', 'CUlaunchAttributeValue', - 'CUlaunchConfig', 'CUlaunchMemSyncDomain', - 'CUlaunchMemSyncDomainMap', 'CUlaunchMemSyncDomain__enumvalues', - 'CUlaunchMemSyncDomain_enum', 'CUlibrary', - 'CUlibraryHostUniversalFunctionAndDataTable', 'CUlibraryOption', - 'CUlibraryOption__enumvalues', 'CUlibraryOption_enum', 'CUlimit', - 'CUlimit__enumvalues', 'CUlimit_enum', 'CUlinkState', - 'CUmemAccessDesc', 'CUmemAccessDesc_v1', 'CUmemAccess_flags', - 'CUmemAccess_flags__enumvalues', 'CUmemAccess_flags_enum', - 'CUmemAllocationCompType', 'CUmemAllocationCompType__enumvalues', - 'CUmemAllocationCompType_enum', - 'CUmemAllocationGranularity_flags', - 'CUmemAllocationGranularity_flags__enumvalues', - 'CUmemAllocationGranularity_flags_enum', - 'CUmemAllocationHandleType', - 'CUmemAllocationHandleType__enumvalues', - 'CUmemAllocationHandleType_enum', 'CUmemAllocationProp', - 'CUmemAllocationProp_v1', 'CUmemAllocationType', - 'CUmemAllocationType__enumvalues', 'CUmemAllocationType_enum', - 'CUmemAttach_flags', 'CUmemAttach_flags__enumvalues', - 'CUmemAttach_flags_enum', 'CUmemGenericAllocationHandle', - 'CUmemGenericAllocationHandle_v1', 'CUmemHandleType', - 'CUmemHandleType__enumvalues', 'CUmemHandleType_enum', - 'CUmemLocation', 'CUmemLocationType', - 'CUmemLocationType__enumvalues', 'CUmemLocationType_enum', - 'CUmemLocation_v1', 'CUmemOperationType', - 'CUmemOperationType__enumvalues', 'CUmemOperationType_enum', - 'CUmemPoolProps', 'CUmemPoolProps_v1', 'CUmemPoolPtrExportData', - 'CUmemPoolPtrExportData_v1', 'CUmemPool_attribute', - 'CUmemPool_attribute__enumvalues', 'CUmemPool_attribute_enum', - 'CUmemRangeHandleType', 'CUmemRangeHandleType__enumvalues', - 'CUmemRangeHandleType_enum', 'CUmem_advise', - 'CUmem_advise__enumvalues', 'CUmem_advise_enum', - 'CUmem_range_attribute', 'CUmem_range_attribute__enumvalues', - 'CUmem_range_attribute_enum', 'CUmemoryPool', 'CUmemorytype', - 'CUmemorytype__enumvalues', 'CUmemorytype_enum', - 'CUmipmappedArray', 'CUmodule', 'CUmoduleLoadingMode', - 'CUmoduleLoadingMode__enumvalues', 'CUmoduleLoadingMode_enum', - 'CUoccupancyB2DSize', 'CUoccupancy_flags', - 'CUoccupancy_flags__enumvalues', 'CUoccupancy_flags_enum', - 'CUpointer_attribute', 'CUpointer_attribute__enumvalues', - 'CUpointer_attribute_enum', 'CUresourceViewFormat', - 'CUresourceViewFormat__enumvalues', 'CUresourceViewFormat_enum', - 'CUresourcetype', 'CUresourcetype__enumvalues', - 'CUresourcetype_enum', 'CUresult', 'CUresult__enumvalues', - 'CUshared_carveout', 'CUshared_carveout__enumvalues', - 'CUshared_carveout_enum', 'CUsharedconfig', - 'CUsharedconfig__enumvalues', 'CUsharedconfig_enum', 'CUstream', - 'CUstreamAttrID', 'CUstreamAttrID__enumvalues', - 'CUstreamAttrValue', 'CUstreamAttrValue_v1', - 'CUstreamBatchMemOpParams', 'CUstreamBatchMemOpParams_v1', - 'CUstreamBatchMemOpType', 'CUstreamBatchMemOpType__enumvalues', - 'CUstreamBatchMemOpType_enum', 'CUstreamCallback', - 'CUstreamCaptureMode', 'CUstreamCaptureMode__enumvalues', - 'CUstreamCaptureMode_enum', 'CUstreamCaptureStatus', - 'CUstreamCaptureStatus__enumvalues', 'CUstreamCaptureStatus_enum', - 'CUstreamMemoryBarrier_flags', - 'CUstreamMemoryBarrier_flags__enumvalues', - 'CUstreamMemoryBarrier_flags_enum', - 'CUstreamUpdateCaptureDependencies_flags', - 'CUstreamUpdateCaptureDependencies_flags__enumvalues', - 'CUstreamUpdateCaptureDependencies_flags_enum', - 'CUstreamWaitValue_flags', 'CUstreamWaitValue_flags__enumvalues', - 'CUstreamWaitValue_flags_enum', 'CUstreamWriteValue_flags', - 'CUstreamWriteValue_flags__enumvalues', - 'CUstreamWriteValue_flags_enum', 'CUstream_flags', - 'CUstream_flags__enumvalues', 'CUstream_flags_enum', - 'CUsurfObject', 'CUsurfObject_v1', 'CUsurfref', - 'CUsynchronizationPolicy', 'CUsynchronizationPolicy__enumvalues', - 'CUsynchronizationPolicy_enum', 'CUtensorMap', - 'CUtensorMapDataType', 'CUtensorMapDataType__enumvalues', - 'CUtensorMapDataType_enum', 'CUtensorMapFloatOOBfill', - 'CUtensorMapFloatOOBfill__enumvalues', - 'CUtensorMapFloatOOBfill_enum', 'CUtensorMapInterleave', - 'CUtensorMapInterleave__enumvalues', 'CUtensorMapInterleave_enum', - 'CUtensorMapL2promotion', 'CUtensorMapL2promotion__enumvalues', - 'CUtensorMapL2promotion_enum', 'CUtensorMapSwizzle', - 'CUtensorMapSwizzle__enumvalues', 'CUtensorMapSwizzle_enum', - 'CUtexObject', 'CUtexObject_v1', 'CUtexref', 'CUuserObject', - 'CUuserObjectRetain_flags', - 'CUuserObjectRetain_flags__enumvalues', - 'CUuserObjectRetain_flags_enum', 'CUuserObject_flags', - 'CUuserObject_flags__enumvalues', 'CUuserObject_flags_enum', - 'CUuuid', 'NVCL_CTX_SCHED_AUTO', 'NVCL_CTX_SCHED_BLOCKING_SYNC', - 'NVCL_CTX_SCHED_SPIN', 'NVCL_CTX_SCHED_YIELD', - 'NVCL_EVENT_SCHED_AUTO', 'NVCL_EVENT_SCHED_BLOCKING_SYNC', - 'NVCL_EVENT_SCHED_SPIN', 'NVCL_EVENT_SCHED_YIELD', - 'cl_context_flags', 'cl_context_flags__enumvalues', - 'cl_context_flags_enum', 'cl_event_flags', - 'cl_event_flags__enumvalues', 'cl_event_flags_enum', - 'cuArray3DCreate', 'cuArray3DCreate_v2', 'cuArray3DGetDescriptor', - 'cuArray3DGetDescriptor_v2', 'cuArrayCreate', 'cuArrayCreate_v2', - 'cuArrayDestroy', 'cuArrayGetDescriptor', - 'cuArrayGetDescriptor_v2', 'cuArrayGetMemoryRequirements', - 'cuArrayGetPlane', 'cuArrayGetSparseProperties', 'cuCtxAttach', - 'cuCtxCreate', 'cuCtxCreate_v2', 'cuCtxCreate_v3', 'cuCtxDestroy', - 'cuCtxDestroy_v2', 'cuCtxDetach', 'cuCtxDisablePeerAccess', - 'cuCtxEnablePeerAccess', 'cuCtxGetApiVersion', - 'cuCtxGetCacheConfig', 'cuCtxGetCurrent', 'cuCtxGetDevice', - 'cuCtxGetExecAffinity', 'cuCtxGetFlags', 'cuCtxGetId', - 'cuCtxGetLimit', 'cuCtxGetSharedMemConfig', - 'cuCtxGetStreamPriorityRange', 'cuCtxPopCurrent', - 'cuCtxPopCurrent_v2', 'cuCtxPushCurrent', 'cuCtxPushCurrent_v2', - 'cuCtxResetPersistingL2Cache', 'cuCtxSetCacheConfig', - 'cuCtxSetCurrent', 'cuCtxSetLimit', 'cuCtxSetSharedMemConfig', - 'cuCtxSynchronize', 'cuDestroyExternalMemory', - 'cuDestroyExternalSemaphore', 'cuDeviceCanAccessPeer', - 'cuDeviceComputeCapability', 'cuDeviceGet', - 'cuDeviceGetAttribute', 'cuDeviceGetByPCIBusId', - 'cuDeviceGetCount', 'cuDeviceGetDefaultMemPool', - 'cuDeviceGetExecAffinitySupport', 'cuDeviceGetGraphMemAttribute', - 'cuDeviceGetLuid', 'cuDeviceGetMemPool', 'cuDeviceGetName', - 'cuDeviceGetNvSciSyncAttributes', 'cuDeviceGetP2PAttribute', - 'cuDeviceGetPCIBusId', 'cuDeviceGetProperties', - 'cuDeviceGetTexture1DLinearMaxWidth', 'cuDeviceGetUuid', - 'cuDeviceGetUuid_v2', 'cuDeviceGraphMemTrim', - 'cuDevicePrimaryCtxGetState', 'cuDevicePrimaryCtxRelease', - 'cuDevicePrimaryCtxRelease_v2', 'cuDevicePrimaryCtxReset', - 'cuDevicePrimaryCtxReset_v2', 'cuDevicePrimaryCtxRetain', - 'cuDevicePrimaryCtxSetFlags', 'cuDevicePrimaryCtxSetFlags_v2', - 'cuDeviceSetGraphMemAttribute', 'cuDeviceSetMemPool', - 'cuDeviceTotalMem', 'cuDeviceTotalMem_v2', 'cuDriverGetVersion', - 'cuEventCreate', 'cuEventDestroy', 'cuEventDestroy_v2', - 'cuEventElapsedTime', 'cuEventQuery', 'cuEventRecord', - 'cuEventRecordWithFlags', 'cuEventRecordWithFlags_ptsz', - 'cuEventRecord_ptsz', 'cuEventSynchronize', - 'cuExternalMemoryGetMappedBuffer', - 'cuExternalMemoryGetMappedMipmappedArray', - 'cuFlushGPUDirectRDMAWrites', 'cuFuncGetAttribute', - 'cuFuncGetModule', 'cuFuncSetAttribute', 'cuFuncSetBlockShape', - 'cuFuncSetCacheConfig', 'cuFuncSetSharedMemConfig', - 'cuFuncSetSharedSize', 'cuGetErrorName', 'cuGetErrorString', - 'cuGetExportTable', 'cuGetProcAddress', 'cuGetProcAddress_v2', - 'cuGraphAddBatchMemOpNode', 'cuGraphAddChildGraphNode', - 'cuGraphAddDependencies', 'cuGraphAddEmptyNode', - 'cuGraphAddEventRecordNode', 'cuGraphAddEventWaitNode', - 'cuGraphAddExternalSemaphoresSignalNode', - 'cuGraphAddExternalSemaphoresWaitNode', 'cuGraphAddHostNode', - 'cuGraphAddKernelNode', 'cuGraphAddKernelNode_v2', - 'cuGraphAddMemAllocNode', 'cuGraphAddMemFreeNode', - 'cuGraphAddMemcpyNode', 'cuGraphAddMemsetNode', - 'cuGraphBatchMemOpNodeGetParams', - 'cuGraphBatchMemOpNodeSetParams', 'cuGraphChildGraphNodeGetGraph', - 'cuGraphClone', 'cuGraphCreate', 'cuGraphDebugDotPrint', - 'cuGraphDestroy', 'cuGraphDestroyNode', - 'cuGraphEventRecordNodeGetEvent', - 'cuGraphEventRecordNodeSetEvent', 'cuGraphEventWaitNodeGetEvent', - 'cuGraphEventWaitNodeSetEvent', - 'cuGraphExecBatchMemOpNodeSetParams', - 'cuGraphExecChildGraphNodeSetParams', 'cuGraphExecDestroy', - 'cuGraphExecEventRecordNodeSetEvent', - 'cuGraphExecEventWaitNodeSetEvent', - 'cuGraphExecExternalSemaphoresSignalNodeSetParams', - 'cuGraphExecExternalSemaphoresWaitNodeSetParams', - 'cuGraphExecGetFlags', 'cuGraphExecHostNodeSetParams', - 'cuGraphExecKernelNodeSetParams', - 'cuGraphExecKernelNodeSetParams_v2', - 'cuGraphExecMemcpyNodeSetParams', - 'cuGraphExecMemsetNodeSetParams', 'cuGraphExecUpdate', - 'cuGraphExecUpdate_v2', - 'cuGraphExternalSemaphoresSignalNodeGetParams', - 'cuGraphExternalSemaphoresSignalNodeSetParams', - 'cuGraphExternalSemaphoresWaitNodeGetParams', - 'cuGraphExternalSemaphoresWaitNodeSetParams', 'cuGraphGetEdges', - 'cuGraphGetNodes', 'cuGraphGetRootNodes', - 'cuGraphHostNodeGetParams', 'cuGraphHostNodeSetParams', - 'cuGraphInstantiate', 'cuGraphInstantiateWithFlags', - 'cuGraphInstantiateWithParams', - 'cuGraphInstantiateWithParams_ptsz', 'cuGraphInstantiate_v2', - 'cuGraphKernelNodeCopyAttributes', - 'cuGraphKernelNodeGetAttribute', 'cuGraphKernelNodeGetParams', - 'cuGraphKernelNodeGetParams_v2', 'cuGraphKernelNodeSetAttribute', - 'cuGraphKernelNodeSetParams', 'cuGraphKernelNodeSetParams_v2', - 'cuGraphLaunch', 'cuGraphLaunch_ptsz', - 'cuGraphMemAllocNodeGetParams', 'cuGraphMemFreeNodeGetParams', - 'cuGraphMemcpyNodeGetParams', 'cuGraphMemcpyNodeSetParams', - 'cuGraphMemsetNodeGetParams', 'cuGraphMemsetNodeSetParams', - 'cuGraphNodeFindInClone', 'cuGraphNodeGetDependencies', - 'cuGraphNodeGetDependentNodes', 'cuGraphNodeGetEnabled', - 'cuGraphNodeGetType', 'cuGraphNodeSetEnabled', - 'cuGraphReleaseUserObject', 'cuGraphRemoveDependencies', - 'cuGraphRetainUserObject', 'cuGraphUpload', 'cuGraphUpload_ptsz', - 'cuGraphicsMapResources', 'cuGraphicsMapResources_ptsz', - 'cuGraphicsResourceGetMappedMipmappedArray', - 'cuGraphicsResourceGetMappedPointer', - 'cuGraphicsResourceGetMappedPointer_v2', - 'cuGraphicsResourceSetMapFlags', - 'cuGraphicsResourceSetMapFlags_v2', - 'cuGraphicsSubResourceGetMappedArray', 'cuGraphicsUnmapResources', - 'cuGraphicsUnmapResources_ptsz', 'cuGraphicsUnregisterResource', - 'cuImportExternalMemory', 'cuImportExternalSemaphore', 'cuInit', - 'cuIpcCloseMemHandle', 'cuIpcGetEventHandle', 'cuIpcGetMemHandle', - 'cuIpcOpenEventHandle', 'cuIpcOpenMemHandle', - 'cuIpcOpenMemHandle_v2', 'cuKernelGetAttribute', - 'cuKernelGetFunction', 'cuKernelSetAttribute', - 'cuKernelSetCacheConfig', 'cuLaunch', 'cuLaunchCooperativeKernel', - 'cuLaunchCooperativeKernelMultiDevice', - 'cuLaunchCooperativeKernel_ptsz', 'cuLaunchGrid', - 'cuLaunchGridAsync', 'cuLaunchHostFunc', 'cuLaunchHostFunc_ptsz', - 'cuLaunchKernel', 'cuLaunchKernelEx', 'cuLaunchKernelEx_ptsz', - 'cuLaunchKernel_ptsz', 'cuLibraryGetGlobal', 'cuLibraryGetKernel', - 'cuLibraryGetManaged', 'cuLibraryGetModule', - 'cuLibraryGetUnifiedFunction', 'cuLibraryLoadData', - 'cuLibraryLoadFromFile', 'cuLibraryUnload', 'cuLinkAddData', - 'cuLinkAddData_v2', 'cuLinkAddFile', 'cuLinkAddFile_v2', - 'cuLinkComplete', 'cuLinkCreate', 'cuLinkCreate_v2', - 'cuLinkDestroy', 'cuMemAddressFree', 'cuMemAddressReserve', - 'cuMemAdvise', 'cuMemAlloc', 'cuMemAllocAsync', - 'cuMemAllocAsync_ptsz', 'cuMemAllocFromPoolAsync', - 'cuMemAllocFromPoolAsync_ptsz', 'cuMemAllocHost', - 'cuMemAllocHost_v2', 'cuMemAllocManaged', 'cuMemAllocPitch', - 'cuMemAllocPitch_v2', 'cuMemAlloc_v2', 'cuMemCreate', - 'cuMemExportToShareableHandle', 'cuMemFree', 'cuMemFreeAsync', - 'cuMemFreeAsync_ptsz', 'cuMemFreeHost', 'cuMemFree_v2', - 'cuMemGetAccess', 'cuMemGetAddressRange', - 'cuMemGetAddressRange_v2', 'cuMemGetAllocationGranularity', - 'cuMemGetAllocationPropertiesFromHandle', - 'cuMemGetHandleForAddressRange', 'cuMemGetInfo', - 'cuMemGetInfo_v2', 'cuMemHostAlloc', 'cuMemHostGetDevicePointer', - 'cuMemHostGetDevicePointer_v2', 'cuMemHostGetFlags', - 'cuMemHostRegister', 'cuMemHostRegister_v2', - 'cuMemHostUnregister', 'cuMemImportFromShareableHandle', - 'cuMemMap', 'cuMemMapArrayAsync', 'cuMemMapArrayAsync_ptsz', - 'cuMemPoolCreate', 'cuMemPoolDestroy', 'cuMemPoolExportPointer', - 'cuMemPoolExportToShareableHandle', 'cuMemPoolGetAccess', - 'cuMemPoolGetAttribute', 'cuMemPoolImportFromShareableHandle', - 'cuMemPoolImportPointer', 'cuMemPoolSetAccess', - 'cuMemPoolSetAttribute', 'cuMemPoolTrimTo', 'cuMemPrefetchAsync', - 'cuMemPrefetchAsync_ptsz', 'cuMemRangeGetAttribute', - 'cuMemRangeGetAttributes', 'cuMemRelease', - 'cuMemRetainAllocationHandle', 'cuMemSetAccess', 'cuMemUnmap', - 'cuMemcpy', 'cuMemcpy2D', 'cuMemcpy2DAsync', 'cuMemcpy2DAsync_v2', - 'cuMemcpy2DAsync_v2_ptsz', 'cuMemcpy2DUnaligned', - 'cuMemcpy2DUnaligned_v2', 'cuMemcpy2DUnaligned_v2_ptds', - 'cuMemcpy2D_v2', 'cuMemcpy2D_v2_ptds', 'cuMemcpy3D', - 'cuMemcpy3DAsync', 'cuMemcpy3DAsync_v2', - 'cuMemcpy3DAsync_v2_ptsz', 'cuMemcpy3DPeer', - 'cuMemcpy3DPeerAsync', 'cuMemcpy3DPeerAsync_ptsz', - 'cuMemcpy3DPeer_ptds', 'cuMemcpy3D_v2', 'cuMemcpy3D_v2_ptds', - 'cuMemcpyAsync', 'cuMemcpyAsync_ptsz', 'cuMemcpyAtoA', - 'cuMemcpyAtoA_v2', 'cuMemcpyAtoA_v2_ptds', 'cuMemcpyAtoD', - 'cuMemcpyAtoD_v2', 'cuMemcpyAtoD_v2_ptds', 'cuMemcpyAtoH', - 'cuMemcpyAtoHAsync', 'cuMemcpyAtoHAsync_v2', - 'cuMemcpyAtoHAsync_v2_ptsz', 'cuMemcpyAtoH_v2', - 'cuMemcpyAtoH_v2_ptds', 'cuMemcpyDtoA', 'cuMemcpyDtoA_v2', - 'cuMemcpyDtoA_v2_ptds', 'cuMemcpyDtoD', 'cuMemcpyDtoDAsync', - 'cuMemcpyDtoDAsync_v2', 'cuMemcpyDtoDAsync_v2_ptsz', - 'cuMemcpyDtoD_v2', 'cuMemcpyDtoD_v2_ptds', 'cuMemcpyDtoH', - 'cuMemcpyDtoHAsync', 'cuMemcpyDtoHAsync_v2', - 'cuMemcpyDtoHAsync_v2_ptsz', 'cuMemcpyDtoH_v2', - 'cuMemcpyDtoH_v2_ptds', 'cuMemcpyHtoA', 'cuMemcpyHtoAAsync', - 'cuMemcpyHtoAAsync_v2', 'cuMemcpyHtoAAsync_v2_ptsz', - 'cuMemcpyHtoA_v2', 'cuMemcpyHtoA_v2_ptds', 'cuMemcpyHtoD', - 'cuMemcpyHtoDAsync', 'cuMemcpyHtoDAsync_v2', - 'cuMemcpyHtoDAsync_v2_ptsz', 'cuMemcpyHtoD_v2', - 'cuMemcpyHtoD_v2_ptds', 'cuMemcpyPeer', 'cuMemcpyPeerAsync', - 'cuMemcpyPeerAsync_ptsz', 'cuMemcpyPeer_ptds', 'cuMemcpy_ptds', - 'cuMemsetD16', 'cuMemsetD16Async', 'cuMemsetD16Async_ptsz', - 'cuMemsetD16_v2', 'cuMemsetD16_v2_ptds', 'cuMemsetD2D16', - 'cuMemsetD2D16Async', 'cuMemsetD2D16Async_ptsz', - 'cuMemsetD2D16_v2', 'cuMemsetD2D16_v2_ptds', 'cuMemsetD2D32', - 'cuMemsetD2D32Async', 'cuMemsetD2D32Async_ptsz', - 'cuMemsetD2D32_v2', 'cuMemsetD2D32_v2_ptds', 'cuMemsetD2D8', - 'cuMemsetD2D8Async', 'cuMemsetD2D8Async_ptsz', 'cuMemsetD2D8_v2', - 'cuMemsetD2D8_v2_ptds', 'cuMemsetD32', 'cuMemsetD32Async', - 'cuMemsetD32Async_ptsz', 'cuMemsetD32_v2', 'cuMemsetD32_v2_ptds', - 'cuMemsetD8', 'cuMemsetD8Async', 'cuMemsetD8Async_ptsz', - 'cuMemsetD8_v2', 'cuMemsetD8_v2_ptds', 'cuMipmappedArrayCreate', - 'cuMipmappedArrayDestroy', 'cuMipmappedArrayGetLevel', - 'cuMipmappedArrayGetMemoryRequirements', - 'cuMipmappedArrayGetSparseProperties', 'cuModuleGetFunction', - 'cuModuleGetGlobal', 'cuModuleGetGlobal_v2', - 'cuModuleGetLoadingMode', 'cuModuleGetSurfRef', - 'cuModuleGetTexRef', 'cuModuleLoad', 'cuModuleLoadData', - 'cuModuleLoadDataEx', 'cuModuleLoadFatBinary', 'cuModuleUnload', - 'cuOccupancyAvailableDynamicSMemPerBlock', - 'cuOccupancyMaxActiveBlocksPerMultiprocessor', - 'cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'cuOccupancyMaxActiveClusters', - 'cuOccupancyMaxPotentialBlockSize', - 'cuOccupancyMaxPotentialBlockSizeWithFlags', - 'cuOccupancyMaxPotentialClusterSize', 'cuParamSetSize', - 'cuParamSetTexRef', 'cuParamSetf', 'cuParamSeti', 'cuParamSetv', - 'cuPointerGetAttribute', 'cuPointerGetAttributes', - 'cuPointerSetAttribute', 'cuSignalExternalSemaphoresAsync', - 'cuSignalExternalSemaphoresAsync_ptsz', 'cuStreamAddCallback', - 'cuStreamAddCallback_ptsz', 'cuStreamAttachMemAsync', - 'cuStreamAttachMemAsync_ptsz', 'cuStreamBatchMemOp', - 'cuStreamBatchMemOp_ptsz', 'cuStreamBatchMemOp_v2', - 'cuStreamBatchMemOp_v2_ptsz', 'cuStreamBeginCapture', - 'cuStreamBeginCapture_ptsz', 'cuStreamBeginCapture_v2', - 'cuStreamBeginCapture_v2_ptsz', 'cuStreamCopyAttributes', - 'cuStreamCopyAttributes_ptsz', 'cuStreamCreate', - 'cuStreamCreateWithPriority', 'cuStreamDestroy', - 'cuStreamDestroy_v2', 'cuStreamEndCapture', - 'cuStreamEndCapture_ptsz', 'cuStreamGetAttribute', - 'cuStreamGetAttribute_ptsz', 'cuStreamGetCaptureInfo', - 'cuStreamGetCaptureInfo_ptsz', 'cuStreamGetCaptureInfo_v2', - 'cuStreamGetCaptureInfo_v2_ptsz', 'cuStreamGetCtx', - 'cuStreamGetCtx_ptsz', 'cuStreamGetFlags', - 'cuStreamGetFlags_ptsz', 'cuStreamGetId', 'cuStreamGetId_ptsz', - 'cuStreamGetPriority', 'cuStreamGetPriority_ptsz', - 'cuStreamIsCapturing', 'cuStreamIsCapturing_ptsz', - 'cuStreamQuery', 'cuStreamQuery_ptsz', 'cuStreamSetAttribute', - 'cuStreamSetAttribute_ptsz', 'cuStreamSynchronize', - 'cuStreamSynchronize_ptsz', 'cuStreamUpdateCaptureDependencies', - 'cuStreamUpdateCaptureDependencies_ptsz', 'cuStreamWaitEvent', - 'cuStreamWaitEvent_ptsz', 'cuStreamWaitValue32', - 'cuStreamWaitValue32_ptsz', 'cuStreamWaitValue32_v2', - 'cuStreamWaitValue32_v2_ptsz', 'cuStreamWaitValue64', - 'cuStreamWaitValue64_ptsz', 'cuStreamWaitValue64_v2', - 'cuStreamWaitValue64_v2_ptsz', 'cuStreamWriteValue32', - 'cuStreamWriteValue32_ptsz', 'cuStreamWriteValue32_v2', - 'cuStreamWriteValue32_v2_ptsz', 'cuStreamWriteValue64', - 'cuStreamWriteValue64_ptsz', 'cuStreamWriteValue64_v2', - 'cuStreamWriteValue64_v2_ptsz', 'cuSurfObjectCreate', - 'cuSurfObjectDestroy', 'cuSurfObjectGetResourceDesc', - 'cuSurfRefGetArray', 'cuSurfRefSetArray', - 'cuTensorMapEncodeIm2col', 'cuTensorMapEncodeTiled', - 'cuTensorMapReplaceAddress', 'cuTexObjectCreate', - 'cuTexObjectDestroy', 'cuTexObjectGetResourceDesc', - 'cuTexObjectGetResourceViewDesc', 'cuTexObjectGetTextureDesc', - 'cuTexRefCreate', 'cuTexRefDestroy', 'cuTexRefGetAddress', - 'cuTexRefGetAddressMode', 'cuTexRefGetAddress_v2', - 'cuTexRefGetArray', 'cuTexRefGetBorderColor', - 'cuTexRefGetFilterMode', 'cuTexRefGetFlags', 'cuTexRefGetFormat', - 'cuTexRefGetMaxAnisotropy', 'cuTexRefGetMipmapFilterMode', - 'cuTexRefGetMipmapLevelBias', 'cuTexRefGetMipmapLevelClamp', - 'cuTexRefGetMipmappedArray', 'cuTexRefSetAddress', - 'cuTexRefSetAddress2D', 'cuTexRefSetAddress2D_v2', - 'cuTexRefSetAddress2D_v3', 'cuTexRefSetAddressMode', - 'cuTexRefSetAddress_v2', 'cuTexRefSetArray', - 'cuTexRefSetBorderColor', 'cuTexRefSetFilterMode', - 'cuTexRefSetFlags', 'cuTexRefSetFormat', - 'cuTexRefSetMaxAnisotropy', 'cuTexRefSetMipmapFilterMode', - 'cuTexRefSetMipmapLevelBias', 'cuTexRefSetMipmapLevelClamp', - 'cuTexRefSetMipmappedArray', 'cuThreadExchangeStreamCaptureMode', - 'cuUserObjectCreate', 'cuUserObjectRelease', 'cuUserObjectRetain', - 'cuWaitExternalSemaphoresAsync', - 'cuWaitExternalSemaphoresAsync_ptsz', 'cudaError_enum', - 'cuuint32_t', 'cuuint64_t', 'size_t', - 'struct_CUDA_ARRAY3D_DESCRIPTOR_st', - 'struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st', - 'struct_CUDA_ARRAY_DESCRIPTOR_st', - 'struct_CUDA_ARRAY_DESCRIPTOR_v1_st', - 'struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st', - 'struct_CUDA_ARRAY_SPARSE_PROPERTIES_st', - 'struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent', - 'struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st', - 'struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st', - 'struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st', - 'struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32', - 'struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params', - 'struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st', - 'struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st', - 'struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st', - 'struct_CUDA_HOST_NODE_PARAMS_st', - 'struct_CUDA_KERNEL_NODE_PARAMS_st', - 'struct_CUDA_KERNEL_NODE_PARAMS_v2_st', - 'struct_CUDA_LAUNCH_PARAMS_st', 'struct_CUDA_MEMCPY2D_st', - 'struct_CUDA_MEMCPY2D_v1_st', 'struct_CUDA_MEMCPY3D_PEER_st', - 'struct_CUDA_MEMCPY3D_st', 'struct_CUDA_MEMCPY3D_v1_st', - 'struct_CUDA_MEMSET_NODE_PARAMS_st', - 'struct_CUDA_MEM_ALLOC_NODE_PARAMS_st', - 'struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st', - 'struct_CUDA_RESOURCE_DESC_st', - 'struct_CUDA_RESOURCE_DESC_st_0_array', - 'struct_CUDA_RESOURCE_DESC_st_0_linear', - 'struct_CUDA_RESOURCE_DESC_st_0_mipmap', - 'struct_CUDA_RESOURCE_DESC_st_0_pitch2D', - 'struct_CUDA_RESOURCE_DESC_st_0_reserved', - 'struct_CUDA_RESOURCE_VIEW_DESC_st', - 'struct_CUDA_TEXTURE_DESC_st', 'struct_CUaccessPolicyWindow_st', - 'struct_CUarrayMapInfo_st', 'struct_CUarrayMapInfo_st_1_miptail', - 'struct_CUarrayMapInfo_st_1_sparseLevel', 'struct_CUarray_st', - 'struct_CUctx_st', 'struct_CUdevprop_st', 'struct_CUevent_st', - 'struct_CUexecAffinityParam_st', - 'struct_CUexecAffinitySmCount_st', 'struct_CUextMemory_st', - 'struct_CUextSemaphore_st', 'struct_CUfunc_st', - 'struct_CUgraphExecUpdateResultInfo_st', 'struct_CUgraphExec_st', - 'struct_CUgraphNode_st', 'struct_CUgraph_st', - 'struct_CUgraphicsResource_st', 'struct_CUipcEventHandle_st', - 'struct_CUipcMemHandle_st', 'struct_CUkern_st', - 'struct_CUlaunchAttributeValue_union_clusterDim', - 'struct_CUlaunchAttributeValue_union_programmaticEvent', - 'struct_CUlaunchAttribute_st', 'struct_CUlaunchConfig_st', - 'struct_CUlaunchMemSyncDomainMap_st', 'struct_CUlib_st', - 'struct_CUlibraryHostUniversalFunctionAndDataTable_st', - 'struct_CUlinkState_st', 'struct_CUmemAccessDesc_st', - 'struct_CUmemAllocationProp_st', - 'struct_CUmemAllocationProp_st_allocFlags', - 'struct_CUmemLocation_st', 'struct_CUmemPoolHandle_st', - 'struct_CUmemPoolProps_st', 'struct_CUmemPoolPtrExportData_st', - 'struct_CUmipmappedArray_st', 'struct_CUmod_st', - 'struct_CUstreamMemOpFlushRemoteWritesParams_st', - 'struct_CUstreamMemOpMemoryBarrierParams_st', - 'struct_CUstreamMemOpWaitValueParams_st', - 'struct_CUstreamMemOpWriteValueParams_st', 'struct_CUstream_st', - 'struct_CUsurfref_st', 'struct_CUtensorMap_st', - 'struct_CUtexref_st', 'struct_CUuserObject_st', - 'struct_CUuuid_st', - 'union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle', - 'union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle', - 'union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync', - 'union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync', - 'union_CUDA_RESOURCE_DESC_st_res', - 'union_CUarrayMapInfo_st_memHandle', - 'union_CUarrayMapInfo_st_resource', - 'union_CUarrayMapInfo_st_subresource', - 'union_CUexecAffinityParam_st_param', - 'union_CUlaunchAttributeValue_union', - 'union_CUstreamBatchMemOpParams_union', - 'union_CUstreamMemOpWaitValueParams_st_0', - 'union_CUstreamMemOpWriteValueParams_st_0'] diff --git a/tinygrad/tinygrad/runtime/autogen/hip.py b/tinygrad/tinygrad/runtime/autogen/hip.py deleted file mode 100644 index fa8dbd15..00000000 --- a/tinygrad/tinygrad/runtime/autogen/hip.py +++ /dev/null @@ -1,5909 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries['libamdhip64.so'] = ctypes.CDLL(os.getenv('ROCM_PATH', '/opt/rocm/')+'/lib/libamdhip64.so') - - - -# values for enumeration 'c__Ea_HIP_SUCCESS' -c__Ea_HIP_SUCCESS__enumvalues = { - 0: 'HIP_SUCCESS', - 1: 'HIP_ERROR_INVALID_VALUE', - 2: 'HIP_ERROR_NOT_INITIALIZED', - 3: 'HIP_ERROR_LAUNCH_OUT_OF_RESOURCES', -} -HIP_SUCCESS = 0 -HIP_ERROR_INVALID_VALUE = 1 -HIP_ERROR_NOT_INITIALIZED = 2 -HIP_ERROR_LAUNCH_OUT_OF_RESOURCES = 3 -c__Ea_HIP_SUCCESS = ctypes.c_uint32 # enum -class struct_c__SA_hipDeviceArch_t(Structure): - pass - -struct_c__SA_hipDeviceArch_t._pack_ = 1 # source:False -struct_c__SA_hipDeviceArch_t._fields_ = [ - ('hasGlobalInt32Atomics', ctypes.c_uint32, 1), - ('hasGlobalFloatAtomicExch', ctypes.c_uint32, 1), - ('hasSharedInt32Atomics', ctypes.c_uint32, 1), - ('hasSharedFloatAtomicExch', ctypes.c_uint32, 1), - ('hasFloatAtomicAdd', ctypes.c_uint32, 1), - ('hasGlobalInt64Atomics', ctypes.c_uint32, 1), - ('hasSharedInt64Atomics', ctypes.c_uint32, 1), - ('hasDoubles', ctypes.c_uint32, 1), - ('hasWarpVote', ctypes.c_uint32, 1), - ('hasWarpBallot', ctypes.c_uint32, 1), - ('hasWarpShuffle', ctypes.c_uint32, 1), - ('hasFunnelShift', ctypes.c_uint32, 1), - ('hasThreadFenceSystem', ctypes.c_uint32, 1), - ('hasSyncThreadsExt', ctypes.c_uint32, 1), - ('hasSurfaceFuncs', ctypes.c_uint32, 1), - ('has3dGrid', ctypes.c_uint32, 1), - ('hasDynamicParallelism', ctypes.c_uint32, 1), - ('PADDING_0', ctypes.c_uint16, 15), -] - -hipDeviceArch_t = struct_c__SA_hipDeviceArch_t -class struct_hipUUID_t(Structure): - pass - -struct_hipUUID_t._pack_ = 1 # source:False -struct_hipUUID_t._fields_ = [ - ('bytes', ctypes.c_char * 16), -] - -hipUUID = struct_hipUUID_t -class struct_hipDeviceProp_tR0600(Structure): - pass - -struct_hipDeviceProp_tR0600._pack_ = 1 # source:False -struct_hipDeviceProp_tR0600._fields_ = [ - ('name', ctypes.c_char * 256), - ('uuid', hipUUID), - ('luid', ctypes.c_char * 8), - ('luidDeviceNodeMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalGlobalMem', ctypes.c_uint64), - ('sharedMemPerBlock', ctypes.c_uint64), - ('regsPerBlock', ctypes.c_int32), - ('warpSize', ctypes.c_int32), - ('memPitch', ctypes.c_uint64), - ('maxThreadsPerBlock', ctypes.c_int32), - ('maxThreadsDim', ctypes.c_int32 * 3), - ('maxGridSize', ctypes.c_int32 * 3), - ('clockRate', ctypes.c_int32), - ('totalConstMem', ctypes.c_uint64), - ('major', ctypes.c_int32), - ('minor', ctypes.c_int32), - ('textureAlignment', ctypes.c_uint64), - ('texturePitchAlignment', ctypes.c_uint64), - ('deviceOverlap', ctypes.c_int32), - ('multiProcessorCount', ctypes.c_int32), - ('kernelExecTimeoutEnabled', ctypes.c_int32), - ('integrated', ctypes.c_int32), - ('canMapHostMemory', ctypes.c_int32), - ('computeMode', ctypes.c_int32), - ('maxTexture1D', ctypes.c_int32), - ('maxTexture1DMipmap', ctypes.c_int32), - ('maxTexture1DLinear', ctypes.c_int32), - ('maxTexture2D', ctypes.c_int32 * 2), - ('maxTexture2DMipmap', ctypes.c_int32 * 2), - ('maxTexture2DLinear', ctypes.c_int32 * 3), - ('maxTexture2DGather', ctypes.c_int32 * 2), - ('maxTexture3D', ctypes.c_int32 * 3), - ('maxTexture3DAlt', ctypes.c_int32 * 3), - ('maxTextureCubemap', ctypes.c_int32), - ('maxTexture1DLayered', ctypes.c_int32 * 2), - ('maxTexture2DLayered', ctypes.c_int32 * 3), - ('maxTextureCubemapLayered', ctypes.c_int32 * 2), - ('maxSurface1D', ctypes.c_int32), - ('maxSurface2D', ctypes.c_int32 * 2), - ('maxSurface3D', ctypes.c_int32 * 3), - ('maxSurface1DLayered', ctypes.c_int32 * 2), - ('maxSurface2DLayered', ctypes.c_int32 * 3), - ('maxSurfaceCubemap', ctypes.c_int32), - ('maxSurfaceCubemapLayered', ctypes.c_int32 * 2), - ('surfaceAlignment', ctypes.c_uint64), - ('concurrentKernels', ctypes.c_int32), - ('ECCEnabled', ctypes.c_int32), - ('pciBusID', ctypes.c_int32), - ('pciDeviceID', ctypes.c_int32), - ('pciDomainID', ctypes.c_int32), - ('tccDriver', ctypes.c_int32), - ('asyncEngineCount', ctypes.c_int32), - ('unifiedAddressing', ctypes.c_int32), - ('memoryClockRate', ctypes.c_int32), - ('memoryBusWidth', ctypes.c_int32), - ('l2CacheSize', ctypes.c_int32), - ('persistingL2CacheMaxSize', ctypes.c_int32), - ('maxThreadsPerMultiProcessor', ctypes.c_int32), - ('streamPrioritiesSupported', ctypes.c_int32), - ('globalL1CacheSupported', ctypes.c_int32), - ('localL1CacheSupported', ctypes.c_int32), - ('sharedMemPerMultiprocessor', ctypes.c_uint64), - ('regsPerMultiprocessor', ctypes.c_int32), - ('managedMemory', ctypes.c_int32), - ('isMultiGpuBoard', ctypes.c_int32), - ('multiGpuBoardGroupID', ctypes.c_int32), - ('hostNativeAtomicSupported', ctypes.c_int32), - ('singleToDoublePrecisionPerfRatio', ctypes.c_int32), - ('pageableMemoryAccess', ctypes.c_int32), - ('concurrentManagedAccess', ctypes.c_int32), - ('computePreemptionSupported', ctypes.c_int32), - ('canUseHostPointerForRegisteredMem', ctypes.c_int32), - ('cooperativeLaunch', ctypes.c_int32), - ('cooperativeMultiDeviceLaunch', ctypes.c_int32), - ('sharedMemPerBlockOptin', ctypes.c_uint64), - ('pageableMemoryAccessUsesHostPageTables', ctypes.c_int32), - ('directManagedMemAccessFromHost', ctypes.c_int32), - ('maxBlocksPerMultiProcessor', ctypes.c_int32), - ('accessPolicyMaxWindowSize', ctypes.c_int32), - ('reservedSharedMemPerBlock', ctypes.c_uint64), - ('hostRegisterSupported', ctypes.c_int32), - ('sparseHipArraySupported', ctypes.c_int32), - ('hostRegisterReadOnlySupported', ctypes.c_int32), - ('timelineSemaphoreInteropSupported', ctypes.c_int32), - ('memoryPoolsSupported', ctypes.c_int32), - ('gpuDirectRDMASupported', ctypes.c_int32), - ('gpuDirectRDMAFlushWritesOptions', ctypes.c_uint32), - ('gpuDirectRDMAWritesOrdering', ctypes.c_int32), - ('memoryPoolSupportedHandleTypes', ctypes.c_uint32), - ('deferredMappingHipArraySupported', ctypes.c_int32), - ('ipcEventSupported', ctypes.c_int32), - ('clusterLaunch', ctypes.c_int32), - ('unifiedFunctionPointers', ctypes.c_int32), - ('reserved', ctypes.c_int32 * 63), - ('hipReserved', ctypes.c_int32 * 32), - ('gcnArchName', ctypes.c_char * 256), - ('maxSharedMemoryPerMultiProcessor', ctypes.c_uint64), - ('clockInstructionRate', ctypes.c_int32), - ('arch', hipDeviceArch_t), - ('hdpMemFlushCntl', ctypes.POINTER(ctypes.c_uint32)), - ('hdpRegFlushCntl', ctypes.POINTER(ctypes.c_uint32)), - ('cooperativeMultiDeviceUnmatchedFunc', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedGridDim', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedBlockDim', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedSharedMem', ctypes.c_int32), - ('isLargeBar', ctypes.c_int32), - ('asicRevision', ctypes.c_int32), -] - -hipDeviceProp_tR0600 = struct_hipDeviceProp_tR0600 - -# values for enumeration 'hipMemoryType' -hipMemoryType__enumvalues = { - 0: 'hipMemoryTypeUnregistered', - 1: 'hipMemoryTypeHost', - 2: 'hipMemoryTypeDevice', - 3: 'hipMemoryTypeManaged', - 10: 'hipMemoryTypeArray', - 11: 'hipMemoryTypeUnified', -} -hipMemoryTypeUnregistered = 0 -hipMemoryTypeHost = 1 -hipMemoryTypeDevice = 2 -hipMemoryTypeManaged = 3 -hipMemoryTypeArray = 10 -hipMemoryTypeUnified = 11 -hipMemoryType = ctypes.c_uint32 # enum -class struct_hipPointerAttribute_t(Structure): - pass - -struct_hipPointerAttribute_t._pack_ = 1 # source:False -struct_hipPointerAttribute_t._fields_ = [ - ('type', hipMemoryType), - ('device', ctypes.c_int32), - ('devicePointer', ctypes.POINTER(None)), - ('hostPointer', ctypes.POINTER(None)), - ('isManaged', ctypes.c_int32), - ('allocationFlags', ctypes.c_uint32), -] - -hipPointerAttribute_t = struct_hipPointerAttribute_t - -# values for enumeration 'hipError_t' -hipError_t__enumvalues = { - 0: 'hipSuccess', - 1: 'hipErrorInvalidValue', - 2: 'hipErrorOutOfMemory', - 2: 'hipErrorMemoryAllocation', - 3: 'hipErrorNotInitialized', - 3: 'hipErrorInitializationError', - 4: 'hipErrorDeinitialized', - 5: 'hipErrorProfilerDisabled', - 6: 'hipErrorProfilerNotInitialized', - 7: 'hipErrorProfilerAlreadyStarted', - 8: 'hipErrorProfilerAlreadyStopped', - 9: 'hipErrorInvalidConfiguration', - 12: 'hipErrorInvalidPitchValue', - 13: 'hipErrorInvalidSymbol', - 17: 'hipErrorInvalidDevicePointer', - 21: 'hipErrorInvalidMemcpyDirection', - 35: 'hipErrorInsufficientDriver', - 52: 'hipErrorMissingConfiguration', - 53: 'hipErrorPriorLaunchFailure', - 98: 'hipErrorInvalidDeviceFunction', - 100: 'hipErrorNoDevice', - 101: 'hipErrorInvalidDevice', - 200: 'hipErrorInvalidImage', - 201: 'hipErrorInvalidContext', - 202: 'hipErrorContextAlreadyCurrent', - 205: 'hipErrorMapFailed', - 205: 'hipErrorMapBufferObjectFailed', - 206: 'hipErrorUnmapFailed', - 207: 'hipErrorArrayIsMapped', - 208: 'hipErrorAlreadyMapped', - 209: 'hipErrorNoBinaryForGpu', - 210: 'hipErrorAlreadyAcquired', - 211: 'hipErrorNotMapped', - 212: 'hipErrorNotMappedAsArray', - 213: 'hipErrorNotMappedAsPointer', - 214: 'hipErrorECCNotCorrectable', - 215: 'hipErrorUnsupportedLimit', - 216: 'hipErrorContextAlreadyInUse', - 217: 'hipErrorPeerAccessUnsupported', - 218: 'hipErrorInvalidKernelFile', - 219: 'hipErrorInvalidGraphicsContext', - 300: 'hipErrorInvalidSource', - 301: 'hipErrorFileNotFound', - 302: 'hipErrorSharedObjectSymbolNotFound', - 303: 'hipErrorSharedObjectInitFailed', - 304: 'hipErrorOperatingSystem', - 400: 'hipErrorInvalidHandle', - 400: 'hipErrorInvalidResourceHandle', - 401: 'hipErrorIllegalState', - 500: 'hipErrorNotFound', - 600: 'hipErrorNotReady', - 700: 'hipErrorIllegalAddress', - 701: 'hipErrorLaunchOutOfResources', - 702: 'hipErrorLaunchTimeOut', - 704: 'hipErrorPeerAccessAlreadyEnabled', - 705: 'hipErrorPeerAccessNotEnabled', - 708: 'hipErrorSetOnActiveProcess', - 709: 'hipErrorContextIsDestroyed', - 710: 'hipErrorAssert', - 712: 'hipErrorHostMemoryAlreadyRegistered', - 713: 'hipErrorHostMemoryNotRegistered', - 719: 'hipErrorLaunchFailure', - 720: 'hipErrorCooperativeLaunchTooLarge', - 801: 'hipErrorNotSupported', - 900: 'hipErrorStreamCaptureUnsupported', - 901: 'hipErrorStreamCaptureInvalidated', - 902: 'hipErrorStreamCaptureMerge', - 903: 'hipErrorStreamCaptureUnmatched', - 904: 'hipErrorStreamCaptureUnjoined', - 905: 'hipErrorStreamCaptureIsolation', - 906: 'hipErrorStreamCaptureImplicit', - 907: 'hipErrorCapturedEvent', - 908: 'hipErrorStreamCaptureWrongThread', - 910: 'hipErrorGraphExecUpdateFailure', - 999: 'hipErrorUnknown', - 1052: 'hipErrorRuntimeMemory', - 1053: 'hipErrorRuntimeOther', - 1054: 'hipErrorTbd', -} -hipSuccess = 0 -hipErrorInvalidValue = 1 -hipErrorOutOfMemory = 2 -hipErrorMemoryAllocation = 2 -hipErrorNotInitialized = 3 -hipErrorInitializationError = 3 -hipErrorDeinitialized = 4 -hipErrorProfilerDisabled = 5 -hipErrorProfilerNotInitialized = 6 -hipErrorProfilerAlreadyStarted = 7 -hipErrorProfilerAlreadyStopped = 8 -hipErrorInvalidConfiguration = 9 -hipErrorInvalidPitchValue = 12 -hipErrorInvalidSymbol = 13 -hipErrorInvalidDevicePointer = 17 -hipErrorInvalidMemcpyDirection = 21 -hipErrorInsufficientDriver = 35 -hipErrorMissingConfiguration = 52 -hipErrorPriorLaunchFailure = 53 -hipErrorInvalidDeviceFunction = 98 -hipErrorNoDevice = 100 -hipErrorInvalidDevice = 101 -hipErrorInvalidImage = 200 -hipErrorInvalidContext = 201 -hipErrorContextAlreadyCurrent = 202 -hipErrorMapFailed = 205 -hipErrorMapBufferObjectFailed = 205 -hipErrorUnmapFailed = 206 -hipErrorArrayIsMapped = 207 -hipErrorAlreadyMapped = 208 -hipErrorNoBinaryForGpu = 209 -hipErrorAlreadyAcquired = 210 -hipErrorNotMapped = 211 -hipErrorNotMappedAsArray = 212 -hipErrorNotMappedAsPointer = 213 -hipErrorECCNotCorrectable = 214 -hipErrorUnsupportedLimit = 215 -hipErrorContextAlreadyInUse = 216 -hipErrorPeerAccessUnsupported = 217 -hipErrorInvalidKernelFile = 218 -hipErrorInvalidGraphicsContext = 219 -hipErrorInvalidSource = 300 -hipErrorFileNotFound = 301 -hipErrorSharedObjectSymbolNotFound = 302 -hipErrorSharedObjectInitFailed = 303 -hipErrorOperatingSystem = 304 -hipErrorInvalidHandle = 400 -hipErrorInvalidResourceHandle = 400 -hipErrorIllegalState = 401 -hipErrorNotFound = 500 -hipErrorNotReady = 600 -hipErrorIllegalAddress = 700 -hipErrorLaunchOutOfResources = 701 -hipErrorLaunchTimeOut = 702 -hipErrorPeerAccessAlreadyEnabled = 704 -hipErrorPeerAccessNotEnabled = 705 -hipErrorSetOnActiveProcess = 708 -hipErrorContextIsDestroyed = 709 -hipErrorAssert = 710 -hipErrorHostMemoryAlreadyRegistered = 712 -hipErrorHostMemoryNotRegistered = 713 -hipErrorLaunchFailure = 719 -hipErrorCooperativeLaunchTooLarge = 720 -hipErrorNotSupported = 801 -hipErrorStreamCaptureUnsupported = 900 -hipErrorStreamCaptureInvalidated = 901 -hipErrorStreamCaptureMerge = 902 -hipErrorStreamCaptureUnmatched = 903 -hipErrorStreamCaptureUnjoined = 904 -hipErrorStreamCaptureIsolation = 905 -hipErrorStreamCaptureImplicit = 906 -hipErrorCapturedEvent = 907 -hipErrorStreamCaptureWrongThread = 908 -hipErrorGraphExecUpdateFailure = 910 -hipErrorUnknown = 999 -hipErrorRuntimeMemory = 1052 -hipErrorRuntimeOther = 1053 -hipErrorTbd = 1054 -hipError_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipDeviceAttribute_t' -hipDeviceAttribute_t__enumvalues = { - 0: 'hipDeviceAttributeCudaCompatibleBegin', - 0: 'hipDeviceAttributeEccEnabled', - 1: 'hipDeviceAttributeAccessPolicyMaxWindowSize', - 2: 'hipDeviceAttributeAsyncEngineCount', - 3: 'hipDeviceAttributeCanMapHostMemory', - 4: 'hipDeviceAttributeCanUseHostPointerForRegisteredMem', - 5: 'hipDeviceAttributeClockRate', - 6: 'hipDeviceAttributeComputeMode', - 7: 'hipDeviceAttributeComputePreemptionSupported', - 8: 'hipDeviceAttributeConcurrentKernels', - 9: 'hipDeviceAttributeConcurrentManagedAccess', - 10: 'hipDeviceAttributeCooperativeLaunch', - 11: 'hipDeviceAttributeCooperativeMultiDeviceLaunch', - 12: 'hipDeviceAttributeDeviceOverlap', - 13: 'hipDeviceAttributeDirectManagedMemAccessFromHost', - 14: 'hipDeviceAttributeGlobalL1CacheSupported', - 15: 'hipDeviceAttributeHostNativeAtomicSupported', - 16: 'hipDeviceAttributeIntegrated', - 17: 'hipDeviceAttributeIsMultiGpuBoard', - 18: 'hipDeviceAttributeKernelExecTimeout', - 19: 'hipDeviceAttributeL2CacheSize', - 20: 'hipDeviceAttributeLocalL1CacheSupported', - 21: 'hipDeviceAttributeLuid', - 22: 'hipDeviceAttributeLuidDeviceNodeMask', - 23: 'hipDeviceAttributeComputeCapabilityMajor', - 24: 'hipDeviceAttributeManagedMemory', - 25: 'hipDeviceAttributeMaxBlocksPerMultiProcessor', - 26: 'hipDeviceAttributeMaxBlockDimX', - 27: 'hipDeviceAttributeMaxBlockDimY', - 28: 'hipDeviceAttributeMaxBlockDimZ', - 29: 'hipDeviceAttributeMaxGridDimX', - 30: 'hipDeviceAttributeMaxGridDimY', - 31: 'hipDeviceAttributeMaxGridDimZ', - 32: 'hipDeviceAttributeMaxSurface1D', - 33: 'hipDeviceAttributeMaxSurface1DLayered', - 34: 'hipDeviceAttributeMaxSurface2D', - 35: 'hipDeviceAttributeMaxSurface2DLayered', - 36: 'hipDeviceAttributeMaxSurface3D', - 37: 'hipDeviceAttributeMaxSurfaceCubemap', - 38: 'hipDeviceAttributeMaxSurfaceCubemapLayered', - 39: 'hipDeviceAttributeMaxTexture1DWidth', - 40: 'hipDeviceAttributeMaxTexture1DLayered', - 41: 'hipDeviceAttributeMaxTexture1DLinear', - 42: 'hipDeviceAttributeMaxTexture1DMipmap', - 43: 'hipDeviceAttributeMaxTexture2DWidth', - 44: 'hipDeviceAttributeMaxTexture2DHeight', - 45: 'hipDeviceAttributeMaxTexture2DGather', - 46: 'hipDeviceAttributeMaxTexture2DLayered', - 47: 'hipDeviceAttributeMaxTexture2DLinear', - 48: 'hipDeviceAttributeMaxTexture2DMipmap', - 49: 'hipDeviceAttributeMaxTexture3DWidth', - 50: 'hipDeviceAttributeMaxTexture3DHeight', - 51: 'hipDeviceAttributeMaxTexture3DDepth', - 52: 'hipDeviceAttributeMaxTexture3DAlt', - 53: 'hipDeviceAttributeMaxTextureCubemap', - 54: 'hipDeviceAttributeMaxTextureCubemapLayered', - 55: 'hipDeviceAttributeMaxThreadsDim', - 56: 'hipDeviceAttributeMaxThreadsPerBlock', - 57: 'hipDeviceAttributeMaxThreadsPerMultiProcessor', - 58: 'hipDeviceAttributeMaxPitch', - 59: 'hipDeviceAttributeMemoryBusWidth', - 60: 'hipDeviceAttributeMemoryClockRate', - 61: 'hipDeviceAttributeComputeCapabilityMinor', - 62: 'hipDeviceAttributeMultiGpuBoardGroupID', - 63: 'hipDeviceAttributeMultiprocessorCount', - 64: 'hipDeviceAttributeUnused1', - 65: 'hipDeviceAttributePageableMemoryAccess', - 66: 'hipDeviceAttributePageableMemoryAccessUsesHostPageTables', - 67: 'hipDeviceAttributePciBusId', - 68: 'hipDeviceAttributePciDeviceId', - 69: 'hipDeviceAttributePciDomainID', - 70: 'hipDeviceAttributePersistingL2CacheMaxSize', - 71: 'hipDeviceAttributeMaxRegistersPerBlock', - 72: 'hipDeviceAttributeMaxRegistersPerMultiprocessor', - 73: 'hipDeviceAttributeReservedSharedMemPerBlock', - 74: 'hipDeviceAttributeMaxSharedMemoryPerBlock', - 75: 'hipDeviceAttributeSharedMemPerBlockOptin', - 76: 'hipDeviceAttributeSharedMemPerMultiprocessor', - 77: 'hipDeviceAttributeSingleToDoublePrecisionPerfRatio', - 78: 'hipDeviceAttributeStreamPrioritiesSupported', - 79: 'hipDeviceAttributeSurfaceAlignment', - 80: 'hipDeviceAttributeTccDriver', - 81: 'hipDeviceAttributeTextureAlignment', - 82: 'hipDeviceAttributeTexturePitchAlignment', - 83: 'hipDeviceAttributeTotalConstantMemory', - 84: 'hipDeviceAttributeTotalGlobalMem', - 85: 'hipDeviceAttributeUnifiedAddressing', - 86: 'hipDeviceAttributeUnused2', - 87: 'hipDeviceAttributeWarpSize', - 88: 'hipDeviceAttributeMemoryPoolsSupported', - 89: 'hipDeviceAttributeVirtualMemoryManagementSupported', - 90: 'hipDeviceAttributeHostRegisterSupported', - 9999: 'hipDeviceAttributeCudaCompatibleEnd', - 10000: 'hipDeviceAttributeAmdSpecificBegin', - 10000: 'hipDeviceAttributeClockInstructionRate', - 10001: 'hipDeviceAttributeUnused3', - 10002: 'hipDeviceAttributeMaxSharedMemoryPerMultiprocessor', - 10003: 'hipDeviceAttributeUnused4', - 10004: 'hipDeviceAttributeUnused5', - 10005: 'hipDeviceAttributeHdpMemFlushCntl', - 10006: 'hipDeviceAttributeHdpRegFlushCntl', - 10007: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc', - 10008: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim', - 10009: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim', - 10010: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem', - 10011: 'hipDeviceAttributeIsLargeBar', - 10012: 'hipDeviceAttributeAsicRevision', - 10013: 'hipDeviceAttributeCanUseStreamWaitValue', - 10014: 'hipDeviceAttributeImageSupport', - 10015: 'hipDeviceAttributePhysicalMultiProcessorCount', - 10016: 'hipDeviceAttributeFineGrainSupport', - 10017: 'hipDeviceAttributeWallClockRate', - 19999: 'hipDeviceAttributeAmdSpecificEnd', - 20000: 'hipDeviceAttributeVendorSpecificBegin', -} -hipDeviceAttributeCudaCompatibleBegin = 0 -hipDeviceAttributeEccEnabled = 0 -hipDeviceAttributeAccessPolicyMaxWindowSize = 1 -hipDeviceAttributeAsyncEngineCount = 2 -hipDeviceAttributeCanMapHostMemory = 3 -hipDeviceAttributeCanUseHostPointerForRegisteredMem = 4 -hipDeviceAttributeClockRate = 5 -hipDeviceAttributeComputeMode = 6 -hipDeviceAttributeComputePreemptionSupported = 7 -hipDeviceAttributeConcurrentKernels = 8 -hipDeviceAttributeConcurrentManagedAccess = 9 -hipDeviceAttributeCooperativeLaunch = 10 -hipDeviceAttributeCooperativeMultiDeviceLaunch = 11 -hipDeviceAttributeDeviceOverlap = 12 -hipDeviceAttributeDirectManagedMemAccessFromHost = 13 -hipDeviceAttributeGlobalL1CacheSupported = 14 -hipDeviceAttributeHostNativeAtomicSupported = 15 -hipDeviceAttributeIntegrated = 16 -hipDeviceAttributeIsMultiGpuBoard = 17 -hipDeviceAttributeKernelExecTimeout = 18 -hipDeviceAttributeL2CacheSize = 19 -hipDeviceAttributeLocalL1CacheSupported = 20 -hipDeviceAttributeLuid = 21 -hipDeviceAttributeLuidDeviceNodeMask = 22 -hipDeviceAttributeComputeCapabilityMajor = 23 -hipDeviceAttributeManagedMemory = 24 -hipDeviceAttributeMaxBlocksPerMultiProcessor = 25 -hipDeviceAttributeMaxBlockDimX = 26 -hipDeviceAttributeMaxBlockDimY = 27 -hipDeviceAttributeMaxBlockDimZ = 28 -hipDeviceAttributeMaxGridDimX = 29 -hipDeviceAttributeMaxGridDimY = 30 -hipDeviceAttributeMaxGridDimZ = 31 -hipDeviceAttributeMaxSurface1D = 32 -hipDeviceAttributeMaxSurface1DLayered = 33 -hipDeviceAttributeMaxSurface2D = 34 -hipDeviceAttributeMaxSurface2DLayered = 35 -hipDeviceAttributeMaxSurface3D = 36 -hipDeviceAttributeMaxSurfaceCubemap = 37 -hipDeviceAttributeMaxSurfaceCubemapLayered = 38 -hipDeviceAttributeMaxTexture1DWidth = 39 -hipDeviceAttributeMaxTexture1DLayered = 40 -hipDeviceAttributeMaxTexture1DLinear = 41 -hipDeviceAttributeMaxTexture1DMipmap = 42 -hipDeviceAttributeMaxTexture2DWidth = 43 -hipDeviceAttributeMaxTexture2DHeight = 44 -hipDeviceAttributeMaxTexture2DGather = 45 -hipDeviceAttributeMaxTexture2DLayered = 46 -hipDeviceAttributeMaxTexture2DLinear = 47 -hipDeviceAttributeMaxTexture2DMipmap = 48 -hipDeviceAttributeMaxTexture3DWidth = 49 -hipDeviceAttributeMaxTexture3DHeight = 50 -hipDeviceAttributeMaxTexture3DDepth = 51 -hipDeviceAttributeMaxTexture3DAlt = 52 -hipDeviceAttributeMaxTextureCubemap = 53 -hipDeviceAttributeMaxTextureCubemapLayered = 54 -hipDeviceAttributeMaxThreadsDim = 55 -hipDeviceAttributeMaxThreadsPerBlock = 56 -hipDeviceAttributeMaxThreadsPerMultiProcessor = 57 -hipDeviceAttributeMaxPitch = 58 -hipDeviceAttributeMemoryBusWidth = 59 -hipDeviceAttributeMemoryClockRate = 60 -hipDeviceAttributeComputeCapabilityMinor = 61 -hipDeviceAttributeMultiGpuBoardGroupID = 62 -hipDeviceAttributeMultiprocessorCount = 63 -hipDeviceAttributeUnused1 = 64 -hipDeviceAttributePageableMemoryAccess = 65 -hipDeviceAttributePageableMemoryAccessUsesHostPageTables = 66 -hipDeviceAttributePciBusId = 67 -hipDeviceAttributePciDeviceId = 68 -hipDeviceAttributePciDomainID = 69 -hipDeviceAttributePersistingL2CacheMaxSize = 70 -hipDeviceAttributeMaxRegistersPerBlock = 71 -hipDeviceAttributeMaxRegistersPerMultiprocessor = 72 -hipDeviceAttributeReservedSharedMemPerBlock = 73 -hipDeviceAttributeMaxSharedMemoryPerBlock = 74 -hipDeviceAttributeSharedMemPerBlockOptin = 75 -hipDeviceAttributeSharedMemPerMultiprocessor = 76 -hipDeviceAttributeSingleToDoublePrecisionPerfRatio = 77 -hipDeviceAttributeStreamPrioritiesSupported = 78 -hipDeviceAttributeSurfaceAlignment = 79 -hipDeviceAttributeTccDriver = 80 -hipDeviceAttributeTextureAlignment = 81 -hipDeviceAttributeTexturePitchAlignment = 82 -hipDeviceAttributeTotalConstantMemory = 83 -hipDeviceAttributeTotalGlobalMem = 84 -hipDeviceAttributeUnifiedAddressing = 85 -hipDeviceAttributeUnused2 = 86 -hipDeviceAttributeWarpSize = 87 -hipDeviceAttributeMemoryPoolsSupported = 88 -hipDeviceAttributeVirtualMemoryManagementSupported = 89 -hipDeviceAttributeHostRegisterSupported = 90 -hipDeviceAttributeCudaCompatibleEnd = 9999 -hipDeviceAttributeAmdSpecificBegin = 10000 -hipDeviceAttributeClockInstructionRate = 10000 -hipDeviceAttributeUnused3 = 10001 -hipDeviceAttributeMaxSharedMemoryPerMultiprocessor = 10002 -hipDeviceAttributeUnused4 = 10003 -hipDeviceAttributeUnused5 = 10004 -hipDeviceAttributeHdpMemFlushCntl = 10005 -hipDeviceAttributeHdpRegFlushCntl = 10006 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc = 10007 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim = 10008 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim = 10009 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem = 10010 -hipDeviceAttributeIsLargeBar = 10011 -hipDeviceAttributeAsicRevision = 10012 -hipDeviceAttributeCanUseStreamWaitValue = 10013 -hipDeviceAttributeImageSupport = 10014 -hipDeviceAttributePhysicalMultiProcessorCount = 10015 -hipDeviceAttributeFineGrainSupport = 10016 -hipDeviceAttributeWallClockRate = 10017 -hipDeviceAttributeAmdSpecificEnd = 19999 -hipDeviceAttributeVendorSpecificBegin = 20000 -hipDeviceAttribute_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipComputeMode' -hipComputeMode__enumvalues = { - 0: 'hipComputeModeDefault', - 1: 'hipComputeModeExclusive', - 2: 'hipComputeModeProhibited', - 3: 'hipComputeModeExclusiveProcess', -} -hipComputeModeDefault = 0 -hipComputeModeExclusive = 1 -hipComputeModeProhibited = 2 -hipComputeModeExclusiveProcess = 3 -hipComputeMode = ctypes.c_uint32 # enum -hipDeviceptr_t = ctypes.POINTER(None) - -# values for enumeration 'hipChannelFormatKind' -hipChannelFormatKind__enumvalues = { - 0: 'hipChannelFormatKindSigned', - 1: 'hipChannelFormatKindUnsigned', - 2: 'hipChannelFormatKindFloat', - 3: 'hipChannelFormatKindNone', -} -hipChannelFormatKindSigned = 0 -hipChannelFormatKindUnsigned = 1 -hipChannelFormatKindFloat = 2 -hipChannelFormatKindNone = 3 -hipChannelFormatKind = ctypes.c_uint32 # enum -class struct_hipChannelFormatDesc(Structure): - pass - -struct_hipChannelFormatDesc._pack_ = 1 # source:False -struct_hipChannelFormatDesc._fields_ = [ - ('x', ctypes.c_int32), - ('y', ctypes.c_int32), - ('z', ctypes.c_int32), - ('w', ctypes.c_int32), - ('f', hipChannelFormatKind), -] - -hipChannelFormatDesc = struct_hipChannelFormatDesc -class struct_hipArray(Structure): - pass - -hipArray_t = ctypes.POINTER(struct_hipArray) -hipArray_const_t = ctypes.POINTER(struct_hipArray) - -# values for enumeration 'hipArray_Format' -hipArray_Format__enumvalues = { - 1: 'HIP_AD_FORMAT_UNSIGNED_INT8', - 2: 'HIP_AD_FORMAT_UNSIGNED_INT16', - 3: 'HIP_AD_FORMAT_UNSIGNED_INT32', - 8: 'HIP_AD_FORMAT_SIGNED_INT8', - 9: 'HIP_AD_FORMAT_SIGNED_INT16', - 10: 'HIP_AD_FORMAT_SIGNED_INT32', - 16: 'HIP_AD_FORMAT_HALF', - 32: 'HIP_AD_FORMAT_FLOAT', -} -HIP_AD_FORMAT_UNSIGNED_INT8 = 1 -HIP_AD_FORMAT_UNSIGNED_INT16 = 2 -HIP_AD_FORMAT_UNSIGNED_INT32 = 3 -HIP_AD_FORMAT_SIGNED_INT8 = 8 -HIP_AD_FORMAT_SIGNED_INT16 = 9 -HIP_AD_FORMAT_SIGNED_INT32 = 10 -HIP_AD_FORMAT_HALF = 16 -HIP_AD_FORMAT_FLOAT = 32 -hipArray_Format = ctypes.c_uint32 # enum -class struct_HIP_ARRAY_DESCRIPTOR(Structure): - pass - -struct_HIP_ARRAY_DESCRIPTOR._pack_ = 1 # source:False -struct_HIP_ARRAY_DESCRIPTOR._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Format', hipArray_Format), - ('NumChannels', ctypes.c_uint32), -] - -HIP_ARRAY_DESCRIPTOR = struct_HIP_ARRAY_DESCRIPTOR -class struct_HIP_ARRAY3D_DESCRIPTOR(Structure): - pass - -struct_HIP_ARRAY3D_DESCRIPTOR._pack_ = 1 # source:False -struct_HIP_ARRAY3D_DESCRIPTOR._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), - ('Format', hipArray_Format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -HIP_ARRAY3D_DESCRIPTOR = struct_HIP_ARRAY3D_DESCRIPTOR -class struct_hip_Memcpy2D(Structure): - pass - -struct_hip_Memcpy2D._pack_ = 1 # source:False -struct_hip_Memcpy2D._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcMemoryType', hipMemoryType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.POINTER(None)), - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPitch', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstMemoryType', hipMemoryType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.POINTER(None)), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPitch', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), -] - -hip_Memcpy2D = struct_hip_Memcpy2D -class struct_hipMipmappedArray(Structure): - pass - -struct_hipMipmappedArray._pack_ = 1 # source:False -struct_hipMipmappedArray._fields_ = [ - ('data', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('type', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depth', ctypes.c_uint32), - ('min_mipmap_level', ctypes.c_uint32), - ('max_mipmap_level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('format', hipArray_Format), - ('num_channels', ctypes.c_uint32), -] - -hipMipmappedArray = struct_hipMipmappedArray -hipMipmappedArray_t = ctypes.POINTER(struct_hipMipmappedArray) -hipmipmappedArray = ctypes.POINTER(struct_hipMipmappedArray) -hipMipmappedArray_const_t = ctypes.POINTER(struct_hipMipmappedArray) - -# values for enumeration 'hipResourceType' -hipResourceType__enumvalues = { - 0: 'hipResourceTypeArray', - 1: 'hipResourceTypeMipmappedArray', - 2: 'hipResourceTypeLinear', - 3: 'hipResourceTypePitch2D', -} -hipResourceTypeArray = 0 -hipResourceTypeMipmappedArray = 1 -hipResourceTypeLinear = 2 -hipResourceTypePitch2D = 3 -hipResourceType = ctypes.c_uint32 # enum - -# values for enumeration 'HIPresourcetype_enum' -HIPresourcetype_enum__enumvalues = { - 0: 'HIP_RESOURCE_TYPE_ARRAY', - 1: 'HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 2: 'HIP_RESOURCE_TYPE_LINEAR', - 3: 'HIP_RESOURCE_TYPE_PITCH2D', -} -HIP_RESOURCE_TYPE_ARRAY = 0 -HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY = 1 -HIP_RESOURCE_TYPE_LINEAR = 2 -HIP_RESOURCE_TYPE_PITCH2D = 3 -HIPresourcetype_enum = ctypes.c_uint32 # enum -HIPresourcetype = HIPresourcetype_enum -HIPresourcetype__enumvalues = HIPresourcetype_enum__enumvalues -hipResourcetype = HIPresourcetype_enum -hipResourcetype__enumvalues = HIPresourcetype_enum__enumvalues - -# values for enumeration 'HIPaddress_mode_enum' -HIPaddress_mode_enum__enumvalues = { - 0: 'HIP_TR_ADDRESS_MODE_WRAP', - 1: 'HIP_TR_ADDRESS_MODE_CLAMP', - 2: 'HIP_TR_ADDRESS_MODE_MIRROR', - 3: 'HIP_TR_ADDRESS_MODE_BORDER', -} -HIP_TR_ADDRESS_MODE_WRAP = 0 -HIP_TR_ADDRESS_MODE_CLAMP = 1 -HIP_TR_ADDRESS_MODE_MIRROR = 2 -HIP_TR_ADDRESS_MODE_BORDER = 3 -HIPaddress_mode_enum = ctypes.c_uint32 # enum -HIPaddress_mode = HIPaddress_mode_enum -HIPaddress_mode__enumvalues = HIPaddress_mode_enum__enumvalues - -# values for enumeration 'HIPfilter_mode_enum' -HIPfilter_mode_enum__enumvalues = { - 0: 'HIP_TR_FILTER_MODE_POINT', - 1: 'HIP_TR_FILTER_MODE_LINEAR', -} -HIP_TR_FILTER_MODE_POINT = 0 -HIP_TR_FILTER_MODE_LINEAR = 1 -HIPfilter_mode_enum = ctypes.c_uint32 # enum -HIPfilter_mode = HIPfilter_mode_enum -HIPfilter_mode__enumvalues = HIPfilter_mode_enum__enumvalues -class struct_HIP_TEXTURE_DESC_st(Structure): - pass - -struct_HIP_TEXTURE_DESC_st._pack_ = 1 # source:False -struct_HIP_TEXTURE_DESC_st._fields_ = [ - ('addressMode', HIPaddress_mode_enum * 3), - ('filterMode', HIPfilter_mode), - ('flags', ctypes.c_uint32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', HIPfilter_mode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('borderColor', ctypes.c_float * 4), - ('reserved', ctypes.c_int32 * 12), -] - -HIP_TEXTURE_DESC = struct_HIP_TEXTURE_DESC_st - -# values for enumeration 'hipResourceViewFormat' -hipResourceViewFormat__enumvalues = { - 0: 'hipResViewFormatNone', - 1: 'hipResViewFormatUnsignedChar1', - 2: 'hipResViewFormatUnsignedChar2', - 3: 'hipResViewFormatUnsignedChar4', - 4: 'hipResViewFormatSignedChar1', - 5: 'hipResViewFormatSignedChar2', - 6: 'hipResViewFormatSignedChar4', - 7: 'hipResViewFormatUnsignedShort1', - 8: 'hipResViewFormatUnsignedShort2', - 9: 'hipResViewFormatUnsignedShort4', - 10: 'hipResViewFormatSignedShort1', - 11: 'hipResViewFormatSignedShort2', - 12: 'hipResViewFormatSignedShort4', - 13: 'hipResViewFormatUnsignedInt1', - 14: 'hipResViewFormatUnsignedInt2', - 15: 'hipResViewFormatUnsignedInt4', - 16: 'hipResViewFormatSignedInt1', - 17: 'hipResViewFormatSignedInt2', - 18: 'hipResViewFormatSignedInt4', - 19: 'hipResViewFormatHalf1', - 20: 'hipResViewFormatHalf2', - 21: 'hipResViewFormatHalf4', - 22: 'hipResViewFormatFloat1', - 23: 'hipResViewFormatFloat2', - 24: 'hipResViewFormatFloat4', - 25: 'hipResViewFormatUnsignedBlockCompressed1', - 26: 'hipResViewFormatUnsignedBlockCompressed2', - 27: 'hipResViewFormatUnsignedBlockCompressed3', - 28: 'hipResViewFormatUnsignedBlockCompressed4', - 29: 'hipResViewFormatSignedBlockCompressed4', - 30: 'hipResViewFormatUnsignedBlockCompressed5', - 31: 'hipResViewFormatSignedBlockCompressed5', - 32: 'hipResViewFormatUnsignedBlockCompressed6H', - 33: 'hipResViewFormatSignedBlockCompressed6H', - 34: 'hipResViewFormatUnsignedBlockCompressed7', -} -hipResViewFormatNone = 0 -hipResViewFormatUnsignedChar1 = 1 -hipResViewFormatUnsignedChar2 = 2 -hipResViewFormatUnsignedChar4 = 3 -hipResViewFormatSignedChar1 = 4 -hipResViewFormatSignedChar2 = 5 -hipResViewFormatSignedChar4 = 6 -hipResViewFormatUnsignedShort1 = 7 -hipResViewFormatUnsignedShort2 = 8 -hipResViewFormatUnsignedShort4 = 9 -hipResViewFormatSignedShort1 = 10 -hipResViewFormatSignedShort2 = 11 -hipResViewFormatSignedShort4 = 12 -hipResViewFormatUnsignedInt1 = 13 -hipResViewFormatUnsignedInt2 = 14 -hipResViewFormatUnsignedInt4 = 15 -hipResViewFormatSignedInt1 = 16 -hipResViewFormatSignedInt2 = 17 -hipResViewFormatSignedInt4 = 18 -hipResViewFormatHalf1 = 19 -hipResViewFormatHalf2 = 20 -hipResViewFormatHalf4 = 21 -hipResViewFormatFloat1 = 22 -hipResViewFormatFloat2 = 23 -hipResViewFormatFloat4 = 24 -hipResViewFormatUnsignedBlockCompressed1 = 25 -hipResViewFormatUnsignedBlockCompressed2 = 26 -hipResViewFormatUnsignedBlockCompressed3 = 27 -hipResViewFormatUnsignedBlockCompressed4 = 28 -hipResViewFormatSignedBlockCompressed4 = 29 -hipResViewFormatUnsignedBlockCompressed5 = 30 -hipResViewFormatSignedBlockCompressed5 = 31 -hipResViewFormatUnsignedBlockCompressed6H = 32 -hipResViewFormatSignedBlockCompressed6H = 33 -hipResViewFormatUnsignedBlockCompressed7 = 34 -hipResourceViewFormat = ctypes.c_uint32 # enum - -# values for enumeration 'HIPresourceViewFormat_enum' -HIPresourceViewFormat_enum__enumvalues = { - 0: 'HIP_RES_VIEW_FORMAT_NONE', - 1: 'HIP_RES_VIEW_FORMAT_UINT_1X8', - 2: 'HIP_RES_VIEW_FORMAT_UINT_2X8', - 3: 'HIP_RES_VIEW_FORMAT_UINT_4X8', - 4: 'HIP_RES_VIEW_FORMAT_SINT_1X8', - 5: 'HIP_RES_VIEW_FORMAT_SINT_2X8', - 6: 'HIP_RES_VIEW_FORMAT_SINT_4X8', - 7: 'HIP_RES_VIEW_FORMAT_UINT_1X16', - 8: 'HIP_RES_VIEW_FORMAT_UINT_2X16', - 9: 'HIP_RES_VIEW_FORMAT_UINT_4X16', - 10: 'HIP_RES_VIEW_FORMAT_SINT_1X16', - 11: 'HIP_RES_VIEW_FORMAT_SINT_2X16', - 12: 'HIP_RES_VIEW_FORMAT_SINT_4X16', - 13: 'HIP_RES_VIEW_FORMAT_UINT_1X32', - 14: 'HIP_RES_VIEW_FORMAT_UINT_2X32', - 15: 'HIP_RES_VIEW_FORMAT_UINT_4X32', - 16: 'HIP_RES_VIEW_FORMAT_SINT_1X32', - 17: 'HIP_RES_VIEW_FORMAT_SINT_2X32', - 18: 'HIP_RES_VIEW_FORMAT_SINT_4X32', - 19: 'HIP_RES_VIEW_FORMAT_FLOAT_1X16', - 20: 'HIP_RES_VIEW_FORMAT_FLOAT_2X16', - 21: 'HIP_RES_VIEW_FORMAT_FLOAT_4X16', - 22: 'HIP_RES_VIEW_FORMAT_FLOAT_1X32', - 23: 'HIP_RES_VIEW_FORMAT_FLOAT_2X32', - 24: 'HIP_RES_VIEW_FORMAT_FLOAT_4X32', - 25: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC1', - 26: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC2', - 27: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC3', - 28: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC4', - 29: 'HIP_RES_VIEW_FORMAT_SIGNED_BC4', - 30: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC5', - 31: 'HIP_RES_VIEW_FORMAT_SIGNED_BC5', - 32: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 33: 'HIP_RES_VIEW_FORMAT_SIGNED_BC6H', - 34: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC7', -} -HIP_RES_VIEW_FORMAT_NONE = 0 -HIP_RES_VIEW_FORMAT_UINT_1X8 = 1 -HIP_RES_VIEW_FORMAT_UINT_2X8 = 2 -HIP_RES_VIEW_FORMAT_UINT_4X8 = 3 -HIP_RES_VIEW_FORMAT_SINT_1X8 = 4 -HIP_RES_VIEW_FORMAT_SINT_2X8 = 5 -HIP_RES_VIEW_FORMAT_SINT_4X8 = 6 -HIP_RES_VIEW_FORMAT_UINT_1X16 = 7 -HIP_RES_VIEW_FORMAT_UINT_2X16 = 8 -HIP_RES_VIEW_FORMAT_UINT_4X16 = 9 -HIP_RES_VIEW_FORMAT_SINT_1X16 = 10 -HIP_RES_VIEW_FORMAT_SINT_2X16 = 11 -HIP_RES_VIEW_FORMAT_SINT_4X16 = 12 -HIP_RES_VIEW_FORMAT_UINT_1X32 = 13 -HIP_RES_VIEW_FORMAT_UINT_2X32 = 14 -HIP_RES_VIEW_FORMAT_UINT_4X32 = 15 -HIP_RES_VIEW_FORMAT_SINT_1X32 = 16 -HIP_RES_VIEW_FORMAT_SINT_2X32 = 17 -HIP_RES_VIEW_FORMAT_SINT_4X32 = 18 -HIP_RES_VIEW_FORMAT_FLOAT_1X16 = 19 -HIP_RES_VIEW_FORMAT_FLOAT_2X16 = 20 -HIP_RES_VIEW_FORMAT_FLOAT_4X16 = 21 -HIP_RES_VIEW_FORMAT_FLOAT_1X32 = 22 -HIP_RES_VIEW_FORMAT_FLOAT_2X32 = 23 -HIP_RES_VIEW_FORMAT_FLOAT_4X32 = 24 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC1 = 25 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC2 = 26 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC3 = 27 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC4 = 28 -HIP_RES_VIEW_FORMAT_SIGNED_BC4 = 29 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC5 = 30 -HIP_RES_VIEW_FORMAT_SIGNED_BC5 = 31 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H = 32 -HIP_RES_VIEW_FORMAT_SIGNED_BC6H = 33 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC7 = 34 -HIPresourceViewFormat_enum = ctypes.c_uint32 # enum -HIPresourceViewFormat = HIPresourceViewFormat_enum -HIPresourceViewFormat__enumvalues = HIPresourceViewFormat_enum__enumvalues -class struct_hipResourceDesc(Structure): - pass - -class union_hipResourceDesc_res(Union): - pass - -class struct_hipResourceDesc_0_array(Structure): - pass - -struct_hipResourceDesc_0_array._pack_ = 1 # source:False -struct_hipResourceDesc_0_array._fields_ = [ - ('array', ctypes.POINTER(struct_hipArray)), -] - -class struct_hipResourceDesc_0_mipmap(Structure): - pass - -struct_hipResourceDesc_0_mipmap._pack_ = 1 # source:False -struct_hipResourceDesc_0_mipmap._fields_ = [ - ('mipmap', ctypes.POINTER(struct_hipMipmappedArray)), -] - -class struct_hipResourceDesc_0_linear(Structure): - pass - -struct_hipResourceDesc_0_linear._pack_ = 1 # source:False -struct_hipResourceDesc_0_linear._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sizeInBytes', ctypes.c_uint64), -] - -class struct_hipResourceDesc_0_pitch2D(Structure): - pass - -struct_hipResourceDesc_0_pitch2D._pack_ = 1 # source:False -struct_hipResourceDesc_0_pitch2D._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), -] - -union_hipResourceDesc_res._pack_ = 1 # source:False -union_hipResourceDesc_res._fields_ = [ - ('array', struct_hipResourceDesc_0_array), - ('mipmap', struct_hipResourceDesc_0_mipmap), - ('linear', struct_hipResourceDesc_0_linear), - ('pitch2D', struct_hipResourceDesc_0_pitch2D), -] - -struct_hipResourceDesc._pack_ = 1 # source:False -struct_hipResourceDesc._fields_ = [ - ('resType', hipResourceType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_hipResourceDesc_res), -] - -hipResourceDesc = struct_hipResourceDesc -class struct_HIP_RESOURCE_DESC_st(Structure): - pass - -class union_HIP_RESOURCE_DESC_st_res(Union): - pass - -class struct_HIP_RESOURCE_DESC_st_0_array(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_array._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_array._fields_ = [ - ('hArray', ctypes.POINTER(struct_hipArray)), -] - -class struct_HIP_RESOURCE_DESC_st_0_mipmap(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_mipmap._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_mipmap._fields_ = [ - ('hMipmappedArray', ctypes.POINTER(struct_hipMipmappedArray)), -] - -class struct_HIP_RESOURCE_DESC_st_0_linear(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_linear._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_linear._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('format', hipArray_Format), - ('numChannels', ctypes.c_uint32), - ('sizeInBytes', ctypes.c_uint64), -] - -class struct_HIP_RESOURCE_DESC_st_0_pitch2D(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_pitch2D._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_pitch2D._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('format', hipArray_Format), - ('numChannels', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), -] - -class struct_HIP_RESOURCE_DESC_st_0_reserved(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_reserved._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_reserved._fields_ = [ - ('reserved', ctypes.c_int32 * 32), -] - -union_HIP_RESOURCE_DESC_st_res._pack_ = 1 # source:False -union_HIP_RESOURCE_DESC_st_res._fields_ = [ - ('array', struct_HIP_RESOURCE_DESC_st_0_array), - ('mipmap', struct_HIP_RESOURCE_DESC_st_0_mipmap), - ('linear', struct_HIP_RESOURCE_DESC_st_0_linear), - ('pitch2D', struct_HIP_RESOURCE_DESC_st_0_pitch2D), - ('reserved', struct_HIP_RESOURCE_DESC_st_0_reserved), -] - -struct_HIP_RESOURCE_DESC_st._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st._fields_ = [ - ('resType', HIPresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_HIP_RESOURCE_DESC_st_res), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -HIP_RESOURCE_DESC = struct_HIP_RESOURCE_DESC_st -class struct_hipResourceViewDesc(Structure): - pass - -struct_hipResourceViewDesc._pack_ = 1 # source:False -struct_hipResourceViewDesc._fields_ = [ - ('format', hipResourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), -] - -class struct_HIP_RESOURCE_VIEW_DESC_st(Structure): - pass - -struct_HIP_RESOURCE_VIEW_DESC_st._pack_ = 1 # source:False -struct_HIP_RESOURCE_VIEW_DESC_st._fields_ = [ - ('format', HIPresourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), -] - -HIP_RESOURCE_VIEW_DESC = struct_HIP_RESOURCE_VIEW_DESC_st - -# values for enumeration 'hipMemcpyKind' -hipMemcpyKind__enumvalues = { - 0: 'hipMemcpyHostToHost', - 1: 'hipMemcpyHostToDevice', - 2: 'hipMemcpyDeviceToHost', - 3: 'hipMemcpyDeviceToDevice', - 4: 'hipMemcpyDefault', -} -hipMemcpyHostToHost = 0 -hipMemcpyHostToDevice = 1 -hipMemcpyDeviceToHost = 2 -hipMemcpyDeviceToDevice = 3 -hipMemcpyDefault = 4 -hipMemcpyKind = ctypes.c_uint32 # enum -class struct_hipPitchedPtr(Structure): - pass - -struct_hipPitchedPtr._pack_ = 1 # source:False -struct_hipPitchedPtr._fields_ = [ - ('ptr', ctypes.POINTER(None)), - ('pitch', ctypes.c_uint64), - ('xsize', ctypes.c_uint64), - ('ysize', ctypes.c_uint64), -] - -hipPitchedPtr = struct_hipPitchedPtr -class struct_hipExtent(Structure): - pass - -struct_hipExtent._pack_ = 1 # source:False -struct_hipExtent._fields_ = [ - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), -] - -hipExtent = struct_hipExtent -class struct_hipPos(Structure): - pass - -struct_hipPos._pack_ = 1 # source:False -struct_hipPos._fields_ = [ - ('x', ctypes.c_uint64), - ('y', ctypes.c_uint64), - ('z', ctypes.c_uint64), -] - -hipPos = struct_hipPos -class struct_hipMemcpy3DParms(Structure): - pass - -struct_hipMemcpy3DParms._pack_ = 1 # source:False -struct_hipMemcpy3DParms._fields_ = [ - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPos', struct_hipPos), - ('srcPtr', struct_hipPitchedPtr), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPos', struct_hipPos), - ('dstPtr', struct_hipPitchedPtr), - ('extent', struct_hipExtent), - ('kind', hipMemcpyKind), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipMemcpy3DParms = struct_hipMemcpy3DParms -class struct_HIP_MEMCPY3D(Structure): - pass - -struct_HIP_MEMCPY3D._pack_ = 1 # source:False -struct_HIP_MEMCPY3D._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', hipMemoryType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.POINTER(None)), - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', hipMemoryType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.POINTER(None)), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), -] - -HIP_MEMCPY3D = struct_HIP_MEMCPY3D -size_t = ctypes.c_uint64 -try: - make_hipPitchedPtr = _libraries['FIXME_STUB'].make_hipPitchedPtr - make_hipPitchedPtr.restype = struct_hipPitchedPtr - make_hipPitchedPtr.argtypes = [ctypes.POINTER(None), size_t, size_t, size_t] -except AttributeError: - pass -try: - make_hipPos = _libraries['FIXME_STUB'].make_hipPos - make_hipPos.restype = struct_hipPos - make_hipPos.argtypes = [size_t, size_t, size_t] -except AttributeError: - pass -try: - make_hipExtent = _libraries['FIXME_STUB'].make_hipExtent - make_hipExtent.restype = struct_hipExtent - make_hipExtent.argtypes = [size_t, size_t, size_t] -except AttributeError: - pass - -# values for enumeration 'hipFunction_attribute' -hipFunction_attribute__enumvalues = { - 0: 'HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 1: 'HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 2: 'HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 3: 'HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', - 4: 'HIP_FUNC_ATTRIBUTE_NUM_REGS', - 5: 'HIP_FUNC_ATTRIBUTE_PTX_VERSION', - 6: 'HIP_FUNC_ATTRIBUTE_BINARY_VERSION', - 7: 'HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 8: 'HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 9: 'HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 10: 'HIP_FUNC_ATTRIBUTE_MAX', -} -HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 0 -HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = 1 -HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = 2 -HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = 3 -HIP_FUNC_ATTRIBUTE_NUM_REGS = 4 -HIP_FUNC_ATTRIBUTE_PTX_VERSION = 5 -HIP_FUNC_ATTRIBUTE_BINARY_VERSION = 6 -HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA = 7 -HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = 8 -HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = 9 -HIP_FUNC_ATTRIBUTE_MAX = 10 -hipFunction_attribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipPointer_attribute' -hipPointer_attribute__enumvalues = { - 1: 'HIP_POINTER_ATTRIBUTE_CONTEXT', - 2: 'HIP_POINTER_ATTRIBUTE_MEMORY_TYPE', - 3: 'HIP_POINTER_ATTRIBUTE_DEVICE_POINTER', - 4: 'HIP_POINTER_ATTRIBUTE_HOST_POINTER', - 5: 'HIP_POINTER_ATTRIBUTE_P2P_TOKENS', - 6: 'HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS', - 7: 'HIP_POINTER_ATTRIBUTE_BUFFER_ID', - 8: 'HIP_POINTER_ATTRIBUTE_IS_MANAGED', - 9: 'HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 10: 'HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE', - 11: 'HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 12: 'HIP_POINTER_ATTRIBUTE_RANGE_SIZE', - 13: 'HIP_POINTER_ATTRIBUTE_MAPPED', - 14: 'HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 15: 'HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 16: 'HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 17: 'HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', -} -HIP_POINTER_ATTRIBUTE_CONTEXT = 1 -HIP_POINTER_ATTRIBUTE_MEMORY_TYPE = 2 -HIP_POINTER_ATTRIBUTE_DEVICE_POINTER = 3 -HIP_POINTER_ATTRIBUTE_HOST_POINTER = 4 -HIP_POINTER_ATTRIBUTE_P2P_TOKENS = 5 -HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS = 6 -HIP_POINTER_ATTRIBUTE_BUFFER_ID = 7 -HIP_POINTER_ATTRIBUTE_IS_MANAGED = 8 -HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL = 9 -HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE = 10 -HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR = 11 -HIP_POINTER_ATTRIBUTE_RANGE_SIZE = 12 -HIP_POINTER_ATTRIBUTE_MAPPED = 13 -HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = 14 -HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = 15 -HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS = 16 -HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = 17 -hipPointer_attribute = ctypes.c_uint32 # enum -try: - hip_init = _libraries['FIXME_STUB'].hip_init - hip_init.restype = hipError_t - hip_init.argtypes = [] -except AttributeError: - pass -class struct_ihipCtx_t(Structure): - pass - -hipCtx_t = ctypes.POINTER(struct_ihipCtx_t) -hipDevice_t = ctypes.c_int32 - -# values for enumeration 'hipDeviceP2PAttr' -hipDeviceP2PAttr__enumvalues = { - 0: 'hipDevP2PAttrPerformanceRank', - 1: 'hipDevP2PAttrAccessSupported', - 2: 'hipDevP2PAttrNativeAtomicSupported', - 3: 'hipDevP2PAttrHipArrayAccessSupported', -} -hipDevP2PAttrPerformanceRank = 0 -hipDevP2PAttrAccessSupported = 1 -hipDevP2PAttrNativeAtomicSupported = 2 -hipDevP2PAttrHipArrayAccessSupported = 3 -hipDeviceP2PAttr = ctypes.c_uint32 # enum -class struct_ihipStream_t(Structure): - pass - -hipStream_t = ctypes.POINTER(struct_ihipStream_t) -class struct_hipIpcMemHandle_st(Structure): - pass - -struct_hipIpcMemHandle_st._pack_ = 1 # source:False -struct_hipIpcMemHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -hipIpcMemHandle_t = struct_hipIpcMemHandle_st -class struct_hipIpcEventHandle_st(Structure): - pass - -struct_hipIpcEventHandle_st._pack_ = 1 # source:False -struct_hipIpcEventHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -hipIpcEventHandle_t = struct_hipIpcEventHandle_st -class struct_ihipModule_t(Structure): - pass - -hipModule_t = ctypes.POINTER(struct_ihipModule_t) -class struct_ihipModuleSymbol_t(Structure): - pass - -hipFunction_t = ctypes.POINTER(struct_ihipModuleSymbol_t) -class struct_ihipMemPoolHandle_t(Structure): - pass - -hipMemPool_t = ctypes.POINTER(struct_ihipMemPoolHandle_t) -class struct_hipFuncAttributes(Structure): - pass - -struct_hipFuncAttributes._pack_ = 1 # source:False -struct_hipFuncAttributes._fields_ = [ - ('binaryVersion', ctypes.c_int32), - ('cacheModeCA', ctypes.c_int32), - ('constSizeBytes', ctypes.c_uint64), - ('localSizeBytes', ctypes.c_uint64), - ('maxDynamicSharedSizeBytes', ctypes.c_int32), - ('maxThreadsPerBlock', ctypes.c_int32), - ('numRegs', ctypes.c_int32), - ('preferredShmemCarveout', ctypes.c_int32), - ('ptxVersion', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sharedSizeBytes', ctypes.c_uint64), -] - -hipFuncAttributes = struct_hipFuncAttributes -class struct_ihipEvent_t(Structure): - pass - -hipEvent_t = ctypes.POINTER(struct_ihipEvent_t) - -# values for enumeration 'hipLimit_t' -hipLimit_t__enumvalues = { - 0: 'hipLimitStackSize', - 1: 'hipLimitPrintfFifoSize', - 2: 'hipLimitMallocHeapSize', - 3: 'hipLimitRange', -} -hipLimitStackSize = 0 -hipLimitPrintfFifoSize = 1 -hipLimitMallocHeapSize = 2 -hipLimitRange = 3 -hipLimit_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemoryAdvise' -hipMemoryAdvise__enumvalues = { - 1: 'hipMemAdviseSetReadMostly', - 2: 'hipMemAdviseUnsetReadMostly', - 3: 'hipMemAdviseSetPreferredLocation', - 4: 'hipMemAdviseUnsetPreferredLocation', - 5: 'hipMemAdviseSetAccessedBy', - 6: 'hipMemAdviseUnsetAccessedBy', - 100: 'hipMemAdviseSetCoarseGrain', - 101: 'hipMemAdviseUnsetCoarseGrain', -} -hipMemAdviseSetReadMostly = 1 -hipMemAdviseUnsetReadMostly = 2 -hipMemAdviseSetPreferredLocation = 3 -hipMemAdviseUnsetPreferredLocation = 4 -hipMemAdviseSetAccessedBy = 5 -hipMemAdviseUnsetAccessedBy = 6 -hipMemAdviseSetCoarseGrain = 100 -hipMemAdviseUnsetCoarseGrain = 101 -hipMemoryAdvise = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemRangeCoherencyMode' -hipMemRangeCoherencyMode__enumvalues = { - 0: 'hipMemRangeCoherencyModeFineGrain', - 1: 'hipMemRangeCoherencyModeCoarseGrain', - 2: 'hipMemRangeCoherencyModeIndeterminate', -} -hipMemRangeCoherencyModeFineGrain = 0 -hipMemRangeCoherencyModeCoarseGrain = 1 -hipMemRangeCoherencyModeIndeterminate = 2 -hipMemRangeCoherencyMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemRangeAttribute' -hipMemRangeAttribute__enumvalues = { - 1: 'hipMemRangeAttributeReadMostly', - 2: 'hipMemRangeAttributePreferredLocation', - 3: 'hipMemRangeAttributeAccessedBy', - 4: 'hipMemRangeAttributeLastPrefetchLocation', - 100: 'hipMemRangeAttributeCoherencyMode', -} -hipMemRangeAttributeReadMostly = 1 -hipMemRangeAttributePreferredLocation = 2 -hipMemRangeAttributeAccessedBy = 3 -hipMemRangeAttributeLastPrefetchLocation = 4 -hipMemRangeAttributeCoherencyMode = 100 -hipMemRangeAttribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemPoolAttr' -hipMemPoolAttr__enumvalues = { - 1: 'hipMemPoolReuseFollowEventDependencies', - 2: 'hipMemPoolReuseAllowOpportunistic', - 3: 'hipMemPoolReuseAllowInternalDependencies', - 4: 'hipMemPoolAttrReleaseThreshold', - 5: 'hipMemPoolAttrReservedMemCurrent', - 6: 'hipMemPoolAttrReservedMemHigh', - 7: 'hipMemPoolAttrUsedMemCurrent', - 8: 'hipMemPoolAttrUsedMemHigh', -} -hipMemPoolReuseFollowEventDependencies = 1 -hipMemPoolReuseAllowOpportunistic = 2 -hipMemPoolReuseAllowInternalDependencies = 3 -hipMemPoolAttrReleaseThreshold = 4 -hipMemPoolAttrReservedMemCurrent = 5 -hipMemPoolAttrReservedMemHigh = 6 -hipMemPoolAttrUsedMemCurrent = 7 -hipMemPoolAttrUsedMemHigh = 8 -hipMemPoolAttr = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemLocationType' -hipMemLocationType__enumvalues = { - 0: 'hipMemLocationTypeInvalid', - 1: 'hipMemLocationTypeDevice', -} -hipMemLocationTypeInvalid = 0 -hipMemLocationTypeDevice = 1 -hipMemLocationType = ctypes.c_uint32 # enum -class struct_hipMemLocation(Structure): - pass - -struct_hipMemLocation._pack_ = 1 # source:False -struct_hipMemLocation._fields_ = [ - ('type', hipMemLocationType), - ('id', ctypes.c_int32), -] - -hipMemLocation = struct_hipMemLocation - -# values for enumeration 'hipMemAccessFlags' -hipMemAccessFlags__enumvalues = { - 0: 'hipMemAccessFlagsProtNone', - 1: 'hipMemAccessFlagsProtRead', - 3: 'hipMemAccessFlagsProtReadWrite', -} -hipMemAccessFlagsProtNone = 0 -hipMemAccessFlagsProtRead = 1 -hipMemAccessFlagsProtReadWrite = 3 -hipMemAccessFlags = ctypes.c_uint32 # enum -class struct_hipMemAccessDesc(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('location', hipMemLocation), - ('flags', hipMemAccessFlags), - ] - -hipMemAccessDesc = struct_hipMemAccessDesc - -# values for enumeration 'hipMemAllocationType' -hipMemAllocationType__enumvalues = { - 0: 'hipMemAllocationTypeInvalid', - 1: 'hipMemAllocationTypePinned', - 2147483647: 'hipMemAllocationTypeMax', -} -hipMemAllocationTypeInvalid = 0 -hipMemAllocationTypePinned = 1 -hipMemAllocationTypeMax = 2147483647 -hipMemAllocationType = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemAllocationHandleType' -hipMemAllocationHandleType__enumvalues = { - 0: 'hipMemHandleTypeNone', - 1: 'hipMemHandleTypePosixFileDescriptor', - 2: 'hipMemHandleTypeWin32', - 4: 'hipMemHandleTypeWin32Kmt', -} -hipMemHandleTypeNone = 0 -hipMemHandleTypePosixFileDescriptor = 1 -hipMemHandleTypeWin32 = 2 -hipMemHandleTypeWin32Kmt = 4 -hipMemAllocationHandleType = ctypes.c_uint32 # enum -class struct_hipMemPoolProps(Structure): - pass - -struct_hipMemPoolProps._pack_ = 1 # source:False -struct_hipMemPoolProps._fields_ = [ - ('allocType', hipMemAllocationType), - ('handleTypes', hipMemAllocationHandleType), - ('location', hipMemLocation), - ('win32SecurityAttributes', ctypes.POINTER(None)), - ('reserved', ctypes.c_ubyte * 64), -] - -hipMemPoolProps = struct_hipMemPoolProps -class struct_hipMemPoolPtrExportData(Structure): - pass - -struct_hipMemPoolPtrExportData._pack_ = 1 # source:False -struct_hipMemPoolPtrExportData._fields_ = [ - ('reserved', ctypes.c_ubyte * 64), -] - -hipMemPoolPtrExportData = struct_hipMemPoolPtrExportData - -# values for enumeration 'hipJitOption' -hipJitOption__enumvalues = { - 0: 'hipJitOptionMaxRegisters', - 1: 'hipJitOptionThreadsPerBlock', - 2: 'hipJitOptionWallTime', - 3: 'hipJitOptionInfoLogBuffer', - 4: 'hipJitOptionInfoLogBufferSizeBytes', - 5: 'hipJitOptionErrorLogBuffer', - 6: 'hipJitOptionErrorLogBufferSizeBytes', - 7: 'hipJitOptionOptimizationLevel', - 8: 'hipJitOptionTargetFromContext', - 9: 'hipJitOptionTarget', - 10: 'hipJitOptionFallbackStrategy', - 11: 'hipJitOptionGenerateDebugInfo', - 12: 'hipJitOptionLogVerbose', - 13: 'hipJitOptionGenerateLineInfo', - 14: 'hipJitOptionCacheMode', - 15: 'hipJitOptionSm3xOpt', - 16: 'hipJitOptionFastCompile', - 17: 'hipJitOptionNumOptions', -} -hipJitOptionMaxRegisters = 0 -hipJitOptionThreadsPerBlock = 1 -hipJitOptionWallTime = 2 -hipJitOptionInfoLogBuffer = 3 -hipJitOptionInfoLogBufferSizeBytes = 4 -hipJitOptionErrorLogBuffer = 5 -hipJitOptionErrorLogBufferSizeBytes = 6 -hipJitOptionOptimizationLevel = 7 -hipJitOptionTargetFromContext = 8 -hipJitOptionTarget = 9 -hipJitOptionFallbackStrategy = 10 -hipJitOptionGenerateDebugInfo = 11 -hipJitOptionLogVerbose = 12 -hipJitOptionGenerateLineInfo = 13 -hipJitOptionCacheMode = 14 -hipJitOptionSm3xOpt = 15 -hipJitOptionFastCompile = 16 -hipJitOptionNumOptions = 17 -hipJitOption = ctypes.c_uint32 # enum - -# values for enumeration 'hipFuncAttribute' -hipFuncAttribute__enumvalues = { - 8: 'hipFuncAttributeMaxDynamicSharedMemorySize', - 9: 'hipFuncAttributePreferredSharedMemoryCarveout', - 10: 'hipFuncAttributeMax', -} -hipFuncAttributeMaxDynamicSharedMemorySize = 8 -hipFuncAttributePreferredSharedMemoryCarveout = 9 -hipFuncAttributeMax = 10 -hipFuncAttribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipFuncCache_t' -hipFuncCache_t__enumvalues = { - 0: 'hipFuncCachePreferNone', - 1: 'hipFuncCachePreferShared', - 2: 'hipFuncCachePreferL1', - 3: 'hipFuncCachePreferEqual', -} -hipFuncCachePreferNone = 0 -hipFuncCachePreferShared = 1 -hipFuncCachePreferL1 = 2 -hipFuncCachePreferEqual = 3 -hipFuncCache_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipSharedMemConfig' -hipSharedMemConfig__enumvalues = { - 0: 'hipSharedMemBankSizeDefault', - 1: 'hipSharedMemBankSizeFourByte', - 2: 'hipSharedMemBankSizeEightByte', -} -hipSharedMemBankSizeDefault = 0 -hipSharedMemBankSizeFourByte = 1 -hipSharedMemBankSizeEightByte = 2 -hipSharedMemConfig = ctypes.c_uint32 # enum -class struct_dim3(Structure): - pass - -struct_dim3._pack_ = 1 # source:False -struct_dim3._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -dim3 = struct_dim3 -class struct_hipLaunchParams_t(Structure): - pass - -struct_hipLaunchParams_t._pack_ = 1 # source:False -struct_hipLaunchParams_t._fields_ = [ - ('func', ctypes.POINTER(None)), - ('gridDim', dim3), - ('blockDim', dim3), - ('args', ctypes.POINTER(ctypes.POINTER(None))), - ('sharedMem', ctypes.c_uint64), - ('stream', ctypes.POINTER(struct_ihipStream_t)), -] - -hipLaunchParams = struct_hipLaunchParams_t -class struct_hipFunctionLaunchParams_t(Structure): - pass - -struct_hipFunctionLaunchParams_t._pack_ = 1 # source:False -struct_hipFunctionLaunchParams_t._fields_ = [ - ('function', ctypes.POINTER(struct_ihipModuleSymbol_t)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_ihipStream_t)), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), -] - -hipFunctionLaunchParams = struct_hipFunctionLaunchParams_t - -# values for enumeration 'hipExternalMemoryHandleType_enum' -hipExternalMemoryHandleType_enum__enumvalues = { - 1: 'hipExternalMemoryHandleTypeOpaqueFd', - 2: 'hipExternalMemoryHandleTypeOpaqueWin32', - 3: 'hipExternalMemoryHandleTypeOpaqueWin32Kmt', - 4: 'hipExternalMemoryHandleTypeD3D12Heap', - 5: 'hipExternalMemoryHandleTypeD3D12Resource', - 6: 'hipExternalMemoryHandleTypeD3D11Resource', - 7: 'hipExternalMemoryHandleTypeD3D11ResourceKmt', - 8: 'hipExternalMemoryHandleTypeNvSciBuf', -} -hipExternalMemoryHandleTypeOpaqueFd = 1 -hipExternalMemoryHandleTypeOpaqueWin32 = 2 -hipExternalMemoryHandleTypeOpaqueWin32Kmt = 3 -hipExternalMemoryHandleTypeD3D12Heap = 4 -hipExternalMemoryHandleTypeD3D12Resource = 5 -hipExternalMemoryHandleTypeD3D11Resource = 6 -hipExternalMemoryHandleTypeD3D11ResourceKmt = 7 -hipExternalMemoryHandleTypeNvSciBuf = 8 -hipExternalMemoryHandleType_enum = ctypes.c_uint32 # enum -hipExternalMemoryHandleType = hipExternalMemoryHandleType_enum -hipExternalMemoryHandleType__enumvalues = hipExternalMemoryHandleType_enum__enumvalues -class struct_hipExternalMemoryHandleDesc_st(Structure): - pass - -class union_hipExternalMemoryHandleDesc_st_handle(Union): - pass - -class struct_hipExternalMemoryHandleDesc_st_0_win32(Structure): - pass - -struct_hipExternalMemoryHandleDesc_st_0_win32._pack_ = 1 # source:False -struct_hipExternalMemoryHandleDesc_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_hipExternalMemoryHandleDesc_st_handle._pack_ = 1 # source:False -union_hipExternalMemoryHandleDesc_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_hipExternalMemoryHandleDesc_st_0_win32), - ('nvSciBufObject', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_hipExternalMemoryHandleDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryHandleDesc_st._fields_ = [ - ('type', hipExternalMemoryHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_hipExternalMemoryHandleDesc_st_handle), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -hipExternalMemoryHandleDesc = struct_hipExternalMemoryHandleDesc_st -class struct_hipExternalMemoryBufferDesc_st(Structure): - pass - -struct_hipExternalMemoryBufferDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryBufferDesc_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalMemoryBufferDesc = struct_hipExternalMemoryBufferDesc_st -class struct_hipExternalMemoryMipmappedArrayDesc_st(Structure): - pass - -struct_hipExternalMemoryMipmappedArrayDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryMipmappedArrayDesc_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('formatDesc', hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('extent', hipExtent), - ('flags', ctypes.c_uint32), - ('numLevels', ctypes.c_uint32), -] - -hipExternalMemoryMipmappedArrayDesc = struct_hipExternalMemoryMipmappedArrayDesc_st -hipExternalMemory_t = ctypes.POINTER(None) - -# values for enumeration 'hipExternalSemaphoreHandleType_enum' -hipExternalSemaphoreHandleType_enum__enumvalues = { - 1: 'hipExternalSemaphoreHandleTypeOpaqueFd', - 2: 'hipExternalSemaphoreHandleTypeOpaqueWin32', - 3: 'hipExternalSemaphoreHandleTypeOpaqueWin32Kmt', - 4: 'hipExternalSemaphoreHandleTypeD3D12Fence', - 5: 'hipExternalSemaphoreHandleTypeD3D11Fence', - 6: 'hipExternalSemaphoreHandleTypeNvSciSync', - 7: 'hipExternalSemaphoreHandleTypeKeyedMutex', - 8: 'hipExternalSemaphoreHandleTypeKeyedMutexKmt', - 9: 'hipExternalSemaphoreHandleTypeTimelineSemaphoreFd', - 10: 'hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32', -} -hipExternalSemaphoreHandleTypeOpaqueFd = 1 -hipExternalSemaphoreHandleTypeOpaqueWin32 = 2 -hipExternalSemaphoreHandleTypeOpaqueWin32Kmt = 3 -hipExternalSemaphoreHandleTypeD3D12Fence = 4 -hipExternalSemaphoreHandleTypeD3D11Fence = 5 -hipExternalSemaphoreHandleTypeNvSciSync = 6 -hipExternalSemaphoreHandleTypeKeyedMutex = 7 -hipExternalSemaphoreHandleTypeKeyedMutexKmt = 8 -hipExternalSemaphoreHandleTypeTimelineSemaphoreFd = 9 -hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32 = 10 -hipExternalSemaphoreHandleType_enum = ctypes.c_uint32 # enum -hipExternalSemaphoreHandleType = hipExternalSemaphoreHandleType_enum -hipExternalSemaphoreHandleType__enumvalues = hipExternalSemaphoreHandleType_enum__enumvalues -class struct_hipExternalSemaphoreHandleDesc_st(Structure): - pass - -class union_hipExternalSemaphoreHandleDesc_st_handle(Union): - pass - -class struct_hipExternalSemaphoreHandleDesc_st_0_win32(Structure): - pass - -struct_hipExternalSemaphoreHandleDesc_st_0_win32._pack_ = 1 # source:False -struct_hipExternalSemaphoreHandleDesc_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_hipExternalSemaphoreHandleDesc_st_handle._pack_ = 1 # source:False -union_hipExternalSemaphoreHandleDesc_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_hipExternalSemaphoreHandleDesc_st_0_win32), - ('NvSciSyncObj', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_hipExternalSemaphoreHandleDesc_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreHandleDesc_st._fields_ = [ - ('type', hipExternalSemaphoreHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_hipExternalSemaphoreHandleDesc_st_handle), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreHandleDesc = struct_hipExternalSemaphoreHandleDesc_st -hipExternalSemaphore_t = ctypes.POINTER(None) -class struct_hipExternalSemaphoreSignalParams_st(Structure): - pass - -class struct_hipExternalSemaphoreSignalParams_st_params(Structure): - pass - -class struct_hipExternalSemaphoreSignalParams_st_0_fence(Structure): - pass - -struct_hipExternalSemaphoreSignalParams_st_0_fence._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_hipExternalSemaphoreSignalParams_st_0_nvSciSync(Union): - pass - -union_hipExternalSemaphoreSignalParams_st_0_nvSciSync._pack_ = 1 # source:False -union_hipExternalSemaphoreSignalParams_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex(Structure): - pass - -struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), -] - -struct_hipExternalSemaphoreSignalParams_st_params._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_params._fields_ = [ - ('fence', struct_hipExternalSemaphoreSignalParams_st_0_fence), - ('nvSciSync', union_hipExternalSemaphoreSignalParams_st_0_nvSciSync), - ('keyedMutex', struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 12), -] - -struct_hipExternalSemaphoreSignalParams_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st._fields_ = [ - ('params', struct_hipExternalSemaphoreSignalParams_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreSignalParams = struct_hipExternalSemaphoreSignalParams_st -class struct_hipExternalSemaphoreWaitParams_st(Structure): - pass - -class struct_hipExternalSemaphoreWaitParams_st_params(Structure): - pass - -class struct_hipExternalSemaphoreWaitParams_st_0_fence(Structure): - pass - -struct_hipExternalSemaphoreWaitParams_st_0_fence._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_hipExternalSemaphoreWaitParams_st_0_nvSciSync(Union): - pass - -union_hipExternalSemaphoreWaitParams_st_0_nvSciSync._pack_ = 1 # source:False -union_hipExternalSemaphoreWaitParams_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex(Structure): - pass - -struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), - ('timeoutMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_hipExternalSemaphoreWaitParams_st_params._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_params._fields_ = [ - ('fence', struct_hipExternalSemaphoreWaitParams_st_0_fence), - ('nvSciSync', union_hipExternalSemaphoreWaitParams_st_0_nvSciSync), - ('keyedMutex', struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 10), -] - -struct_hipExternalSemaphoreWaitParams_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st._fields_ = [ - ('params', struct_hipExternalSemaphoreWaitParams_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreWaitParams = struct_hipExternalSemaphoreWaitParams_st -try: - __hipGetPCH = _libraries['libamdhip64.so'].__hipGetPCH - __hipGetPCH.restype = None - __hipGetPCH.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass - -# values for enumeration 'hipGraphicsRegisterFlags' -hipGraphicsRegisterFlags__enumvalues = { - 0: 'hipGraphicsRegisterFlagsNone', - 1: 'hipGraphicsRegisterFlagsReadOnly', - 2: 'hipGraphicsRegisterFlagsWriteDiscard', - 4: 'hipGraphicsRegisterFlagsSurfaceLoadStore', - 8: 'hipGraphicsRegisterFlagsTextureGather', -} -hipGraphicsRegisterFlagsNone = 0 -hipGraphicsRegisterFlagsReadOnly = 1 -hipGraphicsRegisterFlagsWriteDiscard = 2 -hipGraphicsRegisterFlagsSurfaceLoadStore = 4 -hipGraphicsRegisterFlagsTextureGather = 8 -hipGraphicsRegisterFlags = ctypes.c_uint32 # enum -class struct__hipGraphicsResource(Structure): - pass - -hipGraphicsResource = struct__hipGraphicsResource -hipGraphicsResource_t = ctypes.POINTER(struct__hipGraphicsResource) -class struct_ihipGraph(Structure): - pass - -hipGraph_t = ctypes.POINTER(struct_ihipGraph) -class struct_hipGraphNode(Structure): - pass - -hipGraphNode_t = ctypes.POINTER(struct_hipGraphNode) -class struct_hipGraphExec(Structure): - pass - -hipGraphExec_t = ctypes.POINTER(struct_hipGraphExec) -class struct_hipUserObject(Structure): - pass - -hipUserObject_t = ctypes.POINTER(struct_hipUserObject) - -# values for enumeration 'hipGraphNodeType' -hipGraphNodeType__enumvalues = { - 0: 'hipGraphNodeTypeKernel', - 1: 'hipGraphNodeTypeMemcpy', - 2: 'hipGraphNodeTypeMemset', - 3: 'hipGraphNodeTypeHost', - 4: 'hipGraphNodeTypeGraph', - 5: 'hipGraphNodeTypeEmpty', - 6: 'hipGraphNodeTypeWaitEvent', - 7: 'hipGraphNodeTypeEventRecord', - 8: 'hipGraphNodeTypeExtSemaphoreSignal', - 9: 'hipGraphNodeTypeExtSemaphoreWait', - 10: 'hipGraphNodeTypeMemAlloc', - 11: 'hipGraphNodeTypeMemFree', - 12: 'hipGraphNodeTypeMemcpyFromSymbol', - 13: 'hipGraphNodeTypeMemcpyToSymbol', - 14: 'hipGraphNodeTypeCount', -} -hipGraphNodeTypeKernel = 0 -hipGraphNodeTypeMemcpy = 1 -hipGraphNodeTypeMemset = 2 -hipGraphNodeTypeHost = 3 -hipGraphNodeTypeGraph = 4 -hipGraphNodeTypeEmpty = 5 -hipGraphNodeTypeWaitEvent = 6 -hipGraphNodeTypeEventRecord = 7 -hipGraphNodeTypeExtSemaphoreSignal = 8 -hipGraphNodeTypeExtSemaphoreWait = 9 -hipGraphNodeTypeMemAlloc = 10 -hipGraphNodeTypeMemFree = 11 -hipGraphNodeTypeMemcpyFromSymbol = 12 -hipGraphNodeTypeMemcpyToSymbol = 13 -hipGraphNodeTypeCount = 14 -hipGraphNodeType = ctypes.c_uint32 # enum -hipHostFn_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_hipHostNodeParams(Structure): - pass - -struct_hipHostNodeParams._pack_ = 1 # source:False -struct_hipHostNodeParams._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userData', ctypes.POINTER(None)), -] - -hipHostNodeParams = struct_hipHostNodeParams -class struct_hipKernelNodeParams(Structure): - pass - -struct_hipKernelNodeParams._pack_ = 1 # source:False -struct_hipKernelNodeParams._fields_ = [ - ('blockDim', dim3), - ('PADDING_0', ctypes.c_ubyte * 4), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), - ('func', ctypes.POINTER(None)), - ('gridDim', dim3), - ('PADDING_1', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -hipKernelNodeParams = struct_hipKernelNodeParams -class struct_hipMemsetParams(Structure): - pass - -struct_hipMemsetParams._pack_ = 1 # source:False -struct_hipMemsetParams._fields_ = [ - ('dst', ctypes.POINTER(None)), - ('elementSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('height', ctypes.c_uint64), - ('pitch', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), -] - -hipMemsetParams = struct_hipMemsetParams -class struct_hipMemAllocNodeParams(Structure): - pass - -struct_hipMemAllocNodeParams._pack_ = 1 # source:False -struct_hipMemAllocNodeParams._fields_ = [ - ('poolProps', hipMemPoolProps), - ('accessDescs', ctypes.POINTER(struct_hipMemAccessDesc)), - ('accessDescCount', ctypes.c_uint64), - ('bytesize', ctypes.c_uint64), - ('dptr', ctypes.POINTER(None)), -] - -hipMemAllocNodeParams = struct_hipMemAllocNodeParams - -# values for enumeration 'hipKernelNodeAttrID' -hipKernelNodeAttrID__enumvalues = { - 1: 'hipKernelNodeAttributeAccessPolicyWindow', - 2: 'hipKernelNodeAttributeCooperative', -} -hipKernelNodeAttributeAccessPolicyWindow = 1 -hipKernelNodeAttributeCooperative = 2 -hipKernelNodeAttrID = ctypes.c_uint32 # enum - -# values for enumeration 'hipAccessProperty' -hipAccessProperty__enumvalues = { - 0: 'hipAccessPropertyNormal', - 1: 'hipAccessPropertyStreaming', - 2: 'hipAccessPropertyPersisting', -} -hipAccessPropertyNormal = 0 -hipAccessPropertyStreaming = 1 -hipAccessPropertyPersisting = 2 -hipAccessProperty = ctypes.c_uint32 # enum -class struct_hipAccessPolicyWindow(Structure): - pass - -struct_hipAccessPolicyWindow._pack_ = 1 # source:False -struct_hipAccessPolicyWindow._fields_ = [ - ('base_ptr', ctypes.POINTER(None)), - ('hitProp', hipAccessProperty), - ('hitRatio', ctypes.c_float), - ('missProp', hipAccessProperty), - ('PADDING_0', ctypes.c_ubyte * 4), - ('num_bytes', ctypes.c_uint64), -] - -hipAccessPolicyWindow = struct_hipAccessPolicyWindow -class union_hipKernelNodeAttrValue(Union): - pass - -union_hipKernelNodeAttrValue._pack_ = 1 # source:False -union_hipKernelNodeAttrValue._fields_ = [ - ('accessPolicyWindow', hipAccessPolicyWindow), - ('cooperative', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 28), -] - -hipKernelNodeAttrValue = union_hipKernelNodeAttrValue - -# values for enumeration 'hipGraphExecUpdateResult' -hipGraphExecUpdateResult__enumvalues = { - 0: 'hipGraphExecUpdateSuccess', - 1: 'hipGraphExecUpdateError', - 2: 'hipGraphExecUpdateErrorTopologyChanged', - 3: 'hipGraphExecUpdateErrorNodeTypeChanged', - 4: 'hipGraphExecUpdateErrorFunctionChanged', - 5: 'hipGraphExecUpdateErrorParametersChanged', - 6: 'hipGraphExecUpdateErrorNotSupported', - 7: 'hipGraphExecUpdateErrorUnsupportedFunctionChange', -} -hipGraphExecUpdateSuccess = 0 -hipGraphExecUpdateError = 1 -hipGraphExecUpdateErrorTopologyChanged = 2 -hipGraphExecUpdateErrorNodeTypeChanged = 3 -hipGraphExecUpdateErrorFunctionChanged = 4 -hipGraphExecUpdateErrorParametersChanged = 5 -hipGraphExecUpdateErrorNotSupported = 6 -hipGraphExecUpdateErrorUnsupportedFunctionChange = 7 -hipGraphExecUpdateResult = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamCaptureMode' -hipStreamCaptureMode__enumvalues = { - 0: 'hipStreamCaptureModeGlobal', - 1: 'hipStreamCaptureModeThreadLocal', - 2: 'hipStreamCaptureModeRelaxed', -} -hipStreamCaptureModeGlobal = 0 -hipStreamCaptureModeThreadLocal = 1 -hipStreamCaptureModeRelaxed = 2 -hipStreamCaptureMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamCaptureStatus' -hipStreamCaptureStatus__enumvalues = { - 0: 'hipStreamCaptureStatusNone', - 1: 'hipStreamCaptureStatusActive', - 2: 'hipStreamCaptureStatusInvalidated', -} -hipStreamCaptureStatusNone = 0 -hipStreamCaptureStatusActive = 1 -hipStreamCaptureStatusInvalidated = 2 -hipStreamCaptureStatus = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamUpdateCaptureDependenciesFlags' -hipStreamUpdateCaptureDependenciesFlags__enumvalues = { - 0: 'hipStreamAddCaptureDependencies', - 1: 'hipStreamSetCaptureDependencies', -} -hipStreamAddCaptureDependencies = 0 -hipStreamSetCaptureDependencies = 1 -hipStreamUpdateCaptureDependenciesFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphMemAttributeType' -hipGraphMemAttributeType__enumvalues = { - 0: 'hipGraphMemAttrUsedMemCurrent', - 1: 'hipGraphMemAttrUsedMemHigh', - 2: 'hipGraphMemAttrReservedMemCurrent', - 3: 'hipGraphMemAttrReservedMemHigh', -} -hipGraphMemAttrUsedMemCurrent = 0 -hipGraphMemAttrUsedMemHigh = 1 -hipGraphMemAttrReservedMemCurrent = 2 -hipGraphMemAttrReservedMemHigh = 3 -hipGraphMemAttributeType = ctypes.c_uint32 # enum - -# values for enumeration 'hipUserObjectFlags' -hipUserObjectFlags__enumvalues = { - 1: 'hipUserObjectNoDestructorSync', -} -hipUserObjectNoDestructorSync = 1 -hipUserObjectFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipUserObjectRetainFlags' -hipUserObjectRetainFlags__enumvalues = { - 1: 'hipGraphUserObjectMove', -} -hipGraphUserObjectMove = 1 -hipUserObjectRetainFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphInstantiateFlags' -hipGraphInstantiateFlags__enumvalues = { - 1: 'hipGraphInstantiateFlagAutoFreeOnLaunch', - 2: 'hipGraphInstantiateFlagUpload', - 4: 'hipGraphInstantiateFlagDeviceLaunch', - 8: 'hipGraphInstantiateFlagUseNodePriority', -} -hipGraphInstantiateFlagAutoFreeOnLaunch = 1 -hipGraphInstantiateFlagUpload = 2 -hipGraphInstantiateFlagDeviceLaunch = 4 -hipGraphInstantiateFlagUseNodePriority = 8 -hipGraphInstantiateFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphDebugDotFlags' -hipGraphDebugDotFlags__enumvalues = { - 1: 'hipGraphDebugDotFlagsVerbose', - 4: 'hipGraphDebugDotFlagsKernelNodeParams', - 8: 'hipGraphDebugDotFlagsMemcpyNodeParams', - 16: 'hipGraphDebugDotFlagsMemsetNodeParams', - 32: 'hipGraphDebugDotFlagsHostNodeParams', - 64: 'hipGraphDebugDotFlagsEventNodeParams', - 128: 'hipGraphDebugDotFlagsExtSemasSignalNodeParams', - 256: 'hipGraphDebugDotFlagsExtSemasWaitNodeParams', - 512: 'hipGraphDebugDotFlagsKernelNodeAttributes', - 1024: 'hipGraphDebugDotFlagsHandles', -} -hipGraphDebugDotFlagsVerbose = 1 -hipGraphDebugDotFlagsKernelNodeParams = 4 -hipGraphDebugDotFlagsMemcpyNodeParams = 8 -hipGraphDebugDotFlagsMemsetNodeParams = 16 -hipGraphDebugDotFlagsHostNodeParams = 32 -hipGraphDebugDotFlagsEventNodeParams = 64 -hipGraphDebugDotFlagsExtSemasSignalNodeParams = 128 -hipGraphDebugDotFlagsExtSemasWaitNodeParams = 256 -hipGraphDebugDotFlagsKernelNodeAttributes = 512 -hipGraphDebugDotFlagsHandles = 1024 -hipGraphDebugDotFlags = ctypes.c_uint32 # enum -class struct_hipMemAllocationProp(Structure): - pass - -class struct_hipMemAllocationProp_allocFlags(Structure): - pass - -struct_hipMemAllocationProp_allocFlags._pack_ = 1 # source:False -struct_hipMemAllocationProp_allocFlags._fields_ = [ - ('compressionType', ctypes.c_ubyte), - ('gpuDirectRDMACapable', ctypes.c_ubyte), - ('usage', ctypes.c_uint16), -] - -struct_hipMemAllocationProp._pack_ = 1 # source:False -struct_hipMemAllocationProp._fields_ = [ - ('type', hipMemAllocationType), - ('requestedHandleType', hipMemAllocationHandleType), - ('location', hipMemLocation), - ('win32HandleMetaData', ctypes.POINTER(None)), - ('allocFlags', struct_hipMemAllocationProp_allocFlags), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipMemAllocationProp = struct_hipMemAllocationProp -class struct_hipExternalSemaphoreSignalNodeParams(Structure): - pass - -struct_hipExternalSemaphoreSignalNodeParams._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalNodeParams._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(None))), - ('paramsArray', ctypes.POINTER(struct_hipExternalSemaphoreSignalParams_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreSignalNodeParams = struct_hipExternalSemaphoreSignalNodeParams -class struct_hipExternalSemaphoreWaitNodeParams(Structure): - pass - -struct_hipExternalSemaphoreWaitNodeParams._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitNodeParams._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(None))), - ('paramsArray', ctypes.POINTER(struct_hipExternalSemaphoreWaitParams_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreWaitNodeParams = struct_hipExternalSemaphoreWaitNodeParams -class struct_ihipMemGenericAllocationHandle(Structure): - pass - -hipMemGenericAllocationHandle_t = ctypes.POINTER(struct_ihipMemGenericAllocationHandle) - -# values for enumeration 'hipMemAllocationGranularity_flags' -hipMemAllocationGranularity_flags__enumvalues = { - 0: 'hipMemAllocationGranularityMinimum', - 1: 'hipMemAllocationGranularityRecommended', -} -hipMemAllocationGranularityMinimum = 0 -hipMemAllocationGranularityRecommended = 1 -hipMemAllocationGranularity_flags = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemHandleType' -hipMemHandleType__enumvalues = { - 0: 'hipMemHandleTypeGeneric', -} -hipMemHandleTypeGeneric = 0 -hipMemHandleType = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemOperationType' -hipMemOperationType__enumvalues = { - 1: 'hipMemOperationTypeMap', - 2: 'hipMemOperationTypeUnmap', -} -hipMemOperationTypeMap = 1 -hipMemOperationTypeUnmap = 2 -hipMemOperationType = ctypes.c_uint32 # enum - -# values for enumeration 'hipArraySparseSubresourceType' -hipArraySparseSubresourceType__enumvalues = { - 0: 'hipArraySparseSubresourceTypeSparseLevel', - 1: 'hipArraySparseSubresourceTypeMiptail', -} -hipArraySparseSubresourceTypeSparseLevel = 0 -hipArraySparseSubresourceTypeMiptail = 1 -hipArraySparseSubresourceType = ctypes.c_uint32 # enum -class struct_hipArrayMapInfo(Structure): - pass - -class union_hipArrayMapInfo_resource(Union): - pass - -union_hipArrayMapInfo_resource._pack_ = 1 # source:False -union_hipArrayMapInfo_resource._fields_ = [ - ('mipmap', hipMipmappedArray), - ('array', ctypes.POINTER(struct_hipArray)), - ('PADDING_0', ctypes.c_ubyte * 56), -] - -class union_hipArrayMapInfo_subresource(Union): - pass - -class struct_hipArrayMapInfo_1_sparseLevel(Structure): - pass - -struct_hipArrayMapInfo_1_sparseLevel._pack_ = 1 # source:False -struct_hipArrayMapInfo_1_sparseLevel._fields_ = [ - ('level', ctypes.c_uint32), - ('layer', ctypes.c_uint32), - ('offsetX', ctypes.c_uint32), - ('offsetY', ctypes.c_uint32), - ('offsetZ', ctypes.c_uint32), - ('extentWidth', ctypes.c_uint32), - ('extentHeight', ctypes.c_uint32), - ('extentDepth', ctypes.c_uint32), -] - -class struct_hipArrayMapInfo_1_miptail(Structure): - pass - -struct_hipArrayMapInfo_1_miptail._pack_ = 1 # source:False -struct_hipArrayMapInfo_1_miptail._fields_ = [ - ('layer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -union_hipArrayMapInfo_subresource._pack_ = 1 # source:False -union_hipArrayMapInfo_subresource._fields_ = [ - ('sparseLevel', struct_hipArrayMapInfo_1_sparseLevel), - ('miptail', struct_hipArrayMapInfo_1_miptail), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -class union_hipArrayMapInfo_memHandle(Union): - pass - -union_hipArrayMapInfo_memHandle._pack_ = 1 # source:False -union_hipArrayMapInfo_memHandle._fields_ = [ - ('memHandle', ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), -] - -struct_hipArrayMapInfo._pack_ = 1 # source:False -struct_hipArrayMapInfo._fields_ = [ - ('resourceType', hipResourceType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resource', union_hipArrayMapInfo_resource), - ('subresourceType', hipArraySparseSubresourceType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subresource', union_hipArrayMapInfo_subresource), - ('memOperationType', hipMemOperationType), - ('memHandleType', hipMemHandleType), - ('memHandle', union_hipArrayMapInfo_memHandle), - ('offset', ctypes.c_uint64), - ('deviceBitMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 2), -] - -hipArrayMapInfo = struct_hipArrayMapInfo -try: - hipInit = _libraries['libamdhip64.so'].hipInit - hipInit.restype = hipError_t - hipInit.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - hipDriverGetVersion = _libraries['libamdhip64.so'].hipDriverGetVersion - hipDriverGetVersion.restype = hipError_t - hipDriverGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipRuntimeGetVersion = _libraries['libamdhip64.so'].hipRuntimeGetVersion - hipRuntimeGetVersion.restype = hipError_t - hipRuntimeGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDeviceGet = _libraries['libamdhip64.so'].hipDeviceGet - hipDeviceGet.restype = hipError_t - hipDeviceGet.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceComputeCapability = _libraries['libamdhip64.so'].hipDeviceComputeCapability - hipDeviceComputeCapability.restype = hipError_t - hipDeviceComputeCapability.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetName = _libraries['libamdhip64.so'].hipDeviceGetName - hipDeviceGetName.restype = hipError_t - hipDeviceGetName.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetUuid = _libraries['libamdhip64.so'].hipDeviceGetUuid - hipDeviceGetUuid.restype = hipError_t - hipDeviceGetUuid.argtypes = [ctypes.POINTER(struct_hipUUID_t), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetP2PAttribute = _libraries['libamdhip64.so'].hipDeviceGetP2PAttribute - hipDeviceGetP2PAttribute.restype = hipError_t - hipDeviceGetP2PAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipDeviceP2PAttr, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetPCIBusId = _libraries['libamdhip64.so'].hipDeviceGetPCIBusId - hipDeviceGetPCIBusId.restype = hipError_t - hipDeviceGetPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetByPCIBusId = _libraries['libamdhip64.so'].hipDeviceGetByPCIBusId - hipDeviceGetByPCIBusId.restype = hipError_t - hipDeviceGetByPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipDeviceTotalMem = _libraries['libamdhip64.so'].hipDeviceTotalMem - hipDeviceTotalMem.restype = hipError_t - hipDeviceTotalMem.argtypes = [ctypes.POINTER(ctypes.c_uint64), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceSynchronize = _libraries['libamdhip64.so'].hipDeviceSynchronize - hipDeviceSynchronize.restype = hipError_t - hipDeviceSynchronize.argtypes = [] -except AttributeError: - pass -try: - hipDeviceReset = _libraries['libamdhip64.so'].hipDeviceReset - hipDeviceReset.restype = hipError_t - hipDeviceReset.argtypes = [] -except AttributeError: - pass -try: - hipSetDevice = _libraries['libamdhip64.so'].hipSetDevice - hipSetDevice.restype = hipError_t - hipSetDevice.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipGetDevice = _libraries['libamdhip64.so'].hipGetDevice - hipGetDevice.restype = hipError_t - hipGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipGetDeviceCount = _libraries['libamdhip64.so'].hipGetDeviceCount - hipGetDeviceCount.restype = hipError_t - hipGetDeviceCount.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDeviceGetAttribute = _libraries['libamdhip64.so'].hipDeviceGetAttribute - hipDeviceGetAttribute.restype = hipError_t - hipDeviceGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipDeviceAttribute_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetDefaultMemPool = _libraries['libamdhip64.so'].hipDeviceGetDefaultMemPool - hipDeviceGetDefaultMemPool.restype = hipError_t - hipDeviceGetDefaultMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceSetMemPool = _libraries['libamdhip64.so'].hipDeviceSetMemPool - hipDeviceSetMemPool.restype = hipError_t - hipDeviceSetMemPool.argtypes = [ctypes.c_int32, hipMemPool_t] -except AttributeError: - pass -try: - hipDeviceGetMemPool = _libraries['libamdhip64.so'].hipDeviceGetMemPool - hipDeviceGetMemPool.restype = hipError_t - hipDeviceGetMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.c_int32] -except AttributeError: - pass -try: - hipGetDevicePropertiesR0600 = _libraries['libamdhip64.so'].hipGetDevicePropertiesR0600 - hipGetDevicePropertiesR0600.restype = hipError_t - hipGetDevicePropertiesR0600.argtypes = [ctypes.POINTER(struct_hipDeviceProp_tR0600), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceSetCacheConfig = _libraries['libamdhip64.so'].hipDeviceSetCacheConfig - hipDeviceSetCacheConfig.restype = hipError_t - hipDeviceSetCacheConfig.argtypes = [hipFuncCache_t] -except AttributeError: - pass -try: - hipDeviceGetCacheConfig = _libraries['libamdhip64.so'].hipDeviceGetCacheConfig - hipDeviceGetCacheConfig.restype = hipError_t - hipDeviceGetCacheConfig.argtypes = [ctypes.POINTER(hipFuncCache_t)] -except AttributeError: - pass -try: - hipDeviceGetLimit = _libraries['libamdhip64.so'].hipDeviceGetLimit - hipDeviceGetLimit.restype = hipError_t - hipDeviceGetLimit.argtypes = [ctypes.POINTER(ctypes.c_uint64), hipLimit_t] -except AttributeError: - pass -try: - hipDeviceSetLimit = _libraries['libamdhip64.so'].hipDeviceSetLimit - hipDeviceSetLimit.restype = hipError_t - hipDeviceSetLimit.argtypes = [hipLimit_t, size_t] -except AttributeError: - pass -try: - hipDeviceGetSharedMemConfig = _libraries['libamdhip64.so'].hipDeviceGetSharedMemConfig - hipDeviceGetSharedMemConfig.restype = hipError_t - hipDeviceGetSharedMemConfig.argtypes = [ctypes.POINTER(hipSharedMemConfig)] -except AttributeError: - pass -try: - hipGetDeviceFlags = _libraries['libamdhip64.so'].hipGetDeviceFlags - hipGetDeviceFlags.restype = hipError_t - hipGetDeviceFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipDeviceSetSharedMemConfig = _libraries['libamdhip64.so'].hipDeviceSetSharedMemConfig - hipDeviceSetSharedMemConfig.restype = hipError_t - hipDeviceSetSharedMemConfig.argtypes = [hipSharedMemConfig] -except AttributeError: - pass -try: - hipSetDeviceFlags = _libraries['libamdhip64.so'].hipSetDeviceFlags - hipSetDeviceFlags.restype = hipError_t - hipSetDeviceFlags.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - hipChooseDeviceR0600 = _libraries['libamdhip64.so'].hipChooseDeviceR0600 - hipChooseDeviceR0600.restype = hipError_t - hipChooseDeviceR0600.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_hipDeviceProp_tR0600)] -except AttributeError: - pass -try: - hipExtGetLinkTypeAndHopCount = _libraries['libamdhip64.so'].hipExtGetLinkTypeAndHopCount - hipExtGetLinkTypeAndHopCount.restype = hipError_t - hipExtGetLinkTypeAndHopCount.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipIpcGetMemHandle = _libraries['libamdhip64.so'].hipIpcGetMemHandle - hipIpcGetMemHandle.restype = hipError_t - hipIpcGetMemHandle.argtypes = [ctypes.POINTER(struct_hipIpcMemHandle_st), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipIpcOpenMemHandle = _libraries['libamdhip64.so'].hipIpcOpenMemHandle - hipIpcOpenMemHandle.restype = hipError_t - hipIpcOpenMemHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipIpcMemHandle_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipIpcCloseMemHandle = _libraries['libamdhip64.so'].hipIpcCloseMemHandle - hipIpcCloseMemHandle.restype = hipError_t - hipIpcCloseMemHandle.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipIpcGetEventHandle = _libraries['libamdhip64.so'].hipIpcGetEventHandle - hipIpcGetEventHandle.restype = hipError_t - hipIpcGetEventHandle.argtypes = [ctypes.POINTER(struct_hipIpcEventHandle_st), hipEvent_t] -except AttributeError: - pass -try: - hipIpcOpenEventHandle = _libraries['libamdhip64.so'].hipIpcOpenEventHandle - hipIpcOpenEventHandle.restype = hipError_t - hipIpcOpenEventHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t)), hipIpcEventHandle_t] -except AttributeError: - pass -try: - hipFuncSetAttribute = _libraries['libamdhip64.so'].hipFuncSetAttribute - hipFuncSetAttribute.restype = hipError_t - hipFuncSetAttribute.argtypes = [ctypes.POINTER(None), hipFuncAttribute, ctypes.c_int32] -except AttributeError: - pass -try: - hipFuncSetCacheConfig = _libraries['libamdhip64.so'].hipFuncSetCacheConfig - hipFuncSetCacheConfig.restype = hipError_t - hipFuncSetCacheConfig.argtypes = [ctypes.POINTER(None), hipFuncCache_t] -except AttributeError: - pass -try: - hipFuncSetSharedMemConfig = _libraries['libamdhip64.so'].hipFuncSetSharedMemConfig - hipFuncSetSharedMemConfig.restype = hipError_t - hipFuncSetSharedMemConfig.argtypes = [ctypes.POINTER(None), hipSharedMemConfig] -except AttributeError: - pass -try: - hipGetLastError = _libraries['libamdhip64.so'].hipGetLastError - hipGetLastError.restype = hipError_t - hipGetLastError.argtypes = [] -except AttributeError: - pass -try: - hipExtGetLastError = _libraries['libamdhip64.so'].hipExtGetLastError - hipExtGetLastError.restype = hipError_t - hipExtGetLastError.argtypes = [] -except AttributeError: - pass -try: - hipPeekAtLastError = _libraries['libamdhip64.so'].hipPeekAtLastError - hipPeekAtLastError.restype = hipError_t - hipPeekAtLastError.argtypes = [] -except AttributeError: - pass -try: - hipGetErrorName = _libraries['libamdhip64.so'].hipGetErrorName - hipGetErrorName.restype = ctypes.POINTER(ctypes.c_char) - hipGetErrorName.argtypes = [hipError_t] -except AttributeError: - pass -try: - hipGetErrorString = _libraries['libamdhip64.so'].hipGetErrorString - hipGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - hipGetErrorString.argtypes = [hipError_t] -except AttributeError: - pass -try: - hipDrvGetErrorName = _libraries['libamdhip64.so'].hipDrvGetErrorName - hipDrvGetErrorName.restype = hipError_t - hipDrvGetErrorName.argtypes = [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hipDrvGetErrorString = _libraries['libamdhip64.so'].hipDrvGetErrorString - hipDrvGetErrorString.restype = hipError_t - hipDrvGetErrorString.argtypes = [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hipStreamCreate = _libraries['libamdhip64.so'].hipStreamCreate - hipStreamCreate.restype = hipError_t - hipStreamCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t))] -except AttributeError: - pass -try: - hipStreamCreateWithFlags = _libraries['libamdhip64.so'].hipStreamCreateWithFlags - hipStreamCreateWithFlags.restype = hipError_t - hipStreamCreateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamCreateWithPriority = _libraries['libamdhip64.so'].hipStreamCreateWithPriority - hipStreamCreateWithPriority.restype = hipError_t - hipStreamCreateWithPriority.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetStreamPriorityRange = _libraries['libamdhip64.so'].hipDeviceGetStreamPriorityRange - hipDeviceGetStreamPriorityRange.restype = hipError_t - hipDeviceGetStreamPriorityRange.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipStreamDestroy = _libraries['libamdhip64.so'].hipStreamDestroy - hipStreamDestroy.restype = hipError_t - hipStreamDestroy.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamQuery = _libraries['libamdhip64.so'].hipStreamQuery - hipStreamQuery.restype = hipError_t - hipStreamQuery.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamSynchronize = _libraries['libamdhip64.so'].hipStreamSynchronize - hipStreamSynchronize.restype = hipError_t - hipStreamSynchronize.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamWaitEvent = _libraries['libamdhip64.so'].hipStreamWaitEvent - hipStreamWaitEvent.restype = hipError_t - hipStreamWaitEvent.argtypes = [hipStream_t, hipEvent_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamGetFlags = _libraries['libamdhip64.so'].hipStreamGetFlags - hipStreamGetFlags.restype = hipError_t - hipStreamGetFlags.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipStreamGetPriority = _libraries['libamdhip64.so'].hipStreamGetPriority - hipStreamGetPriority.restype = hipError_t - hipStreamGetPriority.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipStreamGetDevice = _libraries['libamdhip64.so'].hipStreamGetDevice - hipStreamGetDevice.restype = hipError_t - hipStreamGetDevice.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - hipExtStreamCreateWithCUMask = _libraries['libamdhip64.so'].hipExtStreamCreateWithCUMask - hipExtStreamCreateWithCUMask.restype = hipError_t - hipExtStreamCreateWithCUMask.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipExtStreamGetCUMask = _libraries['libamdhip64.so'].hipExtStreamGetCUMask - hipExtStreamGetCUMask.restype = hipError_t - hipExtStreamGetCUMask.argtypes = [hipStream_t, uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -hipStreamCallback_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ihipStream_t), hipError_t, ctypes.POINTER(None)) -try: - hipStreamAddCallback = _libraries['libamdhip64.so'].hipStreamAddCallback - hipStreamAddCallback.restype = hipError_t - hipStreamAddCallback.argtypes = [hipStream_t, hipStreamCallback_t, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamWaitValue32 = _libraries['libamdhip64.so'].hipStreamWaitValue32 - hipStreamWaitValue32.restype = hipError_t - hipStreamWaitValue32.argtypes = [hipStream_t, ctypes.POINTER(None), uint32_t, ctypes.c_uint32, uint32_t] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - hipStreamWaitValue64 = _libraries['libamdhip64.so'].hipStreamWaitValue64 - hipStreamWaitValue64.restype = hipError_t - hipStreamWaitValue64.argtypes = [hipStream_t, ctypes.POINTER(None), uint64_t, ctypes.c_uint32, uint64_t] -except AttributeError: - pass -try: - hipStreamWriteValue32 = _libraries['libamdhip64.so'].hipStreamWriteValue32 - hipStreamWriteValue32.restype = hipError_t - hipStreamWriteValue32.argtypes = [hipStream_t, ctypes.POINTER(None), uint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamWriteValue64 = _libraries['libamdhip64.so'].hipStreamWriteValue64 - hipStreamWriteValue64.restype = hipError_t - hipStreamWriteValue64.argtypes = [hipStream_t, ctypes.POINTER(None), uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipEventCreateWithFlags = _libraries['libamdhip64.so'].hipEventCreateWithFlags - hipEventCreateWithFlags.restype = hipError_t - hipEventCreateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipEventCreate = _libraries['libamdhip64.so'].hipEventCreate - hipEventCreate.restype = hipError_t - hipEventCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipEventRecord = _libraries['libamdhip64.so'].hipEventRecord - hipEventRecord.restype = hipError_t - hipEventRecord.argtypes = [hipEvent_t, hipStream_t] -except AttributeError: - pass -try: - hipEventDestroy = _libraries['libamdhip64.so'].hipEventDestroy - hipEventDestroy.restype = hipError_t - hipEventDestroy.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipEventSynchronize = _libraries['libamdhip64.so'].hipEventSynchronize - hipEventSynchronize.restype = hipError_t - hipEventSynchronize.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipEventElapsedTime = _libraries['libamdhip64.so'].hipEventElapsedTime - hipEventElapsedTime.restype = hipError_t - hipEventElapsedTime.argtypes = [ctypes.POINTER(ctypes.c_float), hipEvent_t, hipEvent_t] -except AttributeError: - pass -try: - hipEventQuery = _libraries['libamdhip64.so'].hipEventQuery - hipEventQuery.restype = hipError_t - hipEventQuery.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipPointerSetAttribute = _libraries['libamdhip64.so'].hipPointerSetAttribute - hipPointerSetAttribute.restype = hipError_t - hipPointerSetAttribute.argtypes = [ctypes.POINTER(None), hipPointer_attribute, hipDeviceptr_t] -except AttributeError: - pass -try: - hipPointerGetAttributes = _libraries['libamdhip64.so'].hipPointerGetAttributes - hipPointerGetAttributes.restype = hipError_t - hipPointerGetAttributes.argtypes = [ctypes.POINTER(struct_hipPointerAttribute_t), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipPointerGetAttribute = _libraries['libamdhip64.so'].hipPointerGetAttribute - hipPointerGetAttribute.restype = hipError_t - hipPointerGetAttribute.argtypes = [ctypes.POINTER(None), hipPointer_attribute, hipDeviceptr_t] -except AttributeError: - pass -try: - hipDrvPointerGetAttributes = _libraries['libamdhip64.so'].hipDrvPointerGetAttributes - hipDrvPointerGetAttributes.restype = hipError_t - hipDrvPointerGetAttributes.argtypes = [ctypes.c_uint32, ctypes.POINTER(hipPointer_attribute), ctypes.POINTER(ctypes.POINTER(None)), hipDeviceptr_t] -except AttributeError: - pass -try: - hipImportExternalSemaphore = _libraries['libamdhip64.so'].hipImportExternalSemaphore - hipImportExternalSemaphore.restype = hipError_t - hipImportExternalSemaphore.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreHandleDesc_st)] -except AttributeError: - pass -try: - hipSignalExternalSemaphoresAsync = _libraries['libamdhip64.so'].hipSignalExternalSemaphoresAsync - hipSignalExternalSemaphoresAsync.restype = hipError_t - hipSignalExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreSignalParams_st), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipWaitExternalSemaphoresAsync = _libraries['libamdhip64.so'].hipWaitExternalSemaphoresAsync - hipWaitExternalSemaphoresAsync.restype = hipError_t - hipWaitExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreWaitParams_st), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipDestroyExternalSemaphore = _libraries['libamdhip64.so'].hipDestroyExternalSemaphore - hipDestroyExternalSemaphore.restype = hipError_t - hipDestroyExternalSemaphore.argtypes = [hipExternalSemaphore_t] -except AttributeError: - pass -try: - hipImportExternalMemory = _libraries['libamdhip64.so'].hipImportExternalMemory - hipImportExternalMemory.restype = hipError_t - hipImportExternalMemory.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalMemoryHandleDesc_st)] -except AttributeError: - pass -try: - hipExternalMemoryGetMappedBuffer = _libraries['libamdhip64.so'].hipExternalMemoryGetMappedBuffer - hipExternalMemoryGetMappedBuffer.restype = hipError_t - hipExternalMemoryGetMappedBuffer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipExternalMemory_t, ctypes.POINTER(struct_hipExternalMemoryBufferDesc_st)] -except AttributeError: - pass -try: - hipDestroyExternalMemory = _libraries['libamdhip64.so'].hipDestroyExternalMemory - hipDestroyExternalMemory.restype = hipError_t - hipDestroyExternalMemory.argtypes = [hipExternalMemory_t] -except AttributeError: - pass -try: - hipExternalMemoryGetMappedMipmappedArray = _libraries['FIXME_STUB'].hipExternalMemoryGetMappedMipmappedArray - hipExternalMemoryGetMappedMipmappedArray.restype = hipError_t - hipExternalMemoryGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), hipExternalMemory_t, ctypes.POINTER(struct_hipExternalMemoryMipmappedArrayDesc_st)] -except AttributeError: - pass -try: - hipMalloc = _libraries['libamdhip64.so'].hipMalloc - hipMalloc.restype = hipError_t - hipMalloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipExtMallocWithFlags = _libraries['libamdhip64.so'].hipExtMallocWithFlags - hipExtMallocWithFlags.restype = hipError_t - hipExtMallocWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocHost = _libraries['libamdhip64.so'].hipMallocHost - hipMallocHost.restype = hipError_t - hipMallocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipMemAllocHost = _libraries['libamdhip64.so'].hipMemAllocHost - hipMemAllocHost.restype = hipError_t - hipMemAllocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipHostMalloc = _libraries['libamdhip64.so'].hipHostMalloc - hipHostMalloc.restype = hipError_t - hipHostMalloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocManaged = _libraries['libamdhip64.so'].hipMallocManaged - hipMallocManaged.restype = hipError_t - hipMallocManaged.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPrefetchAsync = _libraries['libamdhip64.so'].hipMemPrefetchAsync - hipMemPrefetchAsync.restype = hipError_t - hipMemPrefetchAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, hipStream_t] -except AttributeError: - pass -try: - hipMemAdvise = _libraries['libamdhip64.so'].hipMemAdvise - hipMemAdvise.restype = hipError_t - hipMemAdvise.argtypes = [ctypes.POINTER(None), size_t, hipMemoryAdvise, ctypes.c_int32] -except AttributeError: - pass -try: - hipMemRangeGetAttribute = _libraries['libamdhip64.so'].hipMemRangeGetAttribute - hipMemRangeGetAttribute.restype = hipError_t - hipMemRangeGetAttribute.argtypes = [ctypes.POINTER(None), size_t, hipMemRangeAttribute, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemRangeGetAttributes = _libraries['libamdhip64.so'].hipMemRangeGetAttributes - hipMemRangeGetAttributes.restype = hipError_t - hipMemRangeGetAttributes.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(hipMemRangeAttribute), size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipStreamAttachMemAsync = _libraries['libamdhip64.so'].hipStreamAttachMemAsync - hipStreamAttachMemAsync.restype = hipError_t - hipStreamAttachMemAsync.argtypes = [hipStream_t, ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocAsync = _libraries['libamdhip64.so'].hipMallocAsync - hipMallocAsync.restype = hipError_t - hipMallocAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t] -except AttributeError: - pass -try: - hipFreeAsync = _libraries['libamdhip64.so'].hipFreeAsync - hipFreeAsync.restype = hipError_t - hipFreeAsync.argtypes = [ctypes.POINTER(None), hipStream_t] -except AttributeError: - pass -try: - hipMemPoolTrimTo = _libraries['libamdhip64.so'].hipMemPoolTrimTo - hipMemPoolTrimTo.restype = hipError_t - hipMemPoolTrimTo.argtypes = [hipMemPool_t, size_t] -except AttributeError: - pass -try: - hipMemPoolSetAttribute = _libraries['libamdhip64.so'].hipMemPoolSetAttribute - hipMemPoolSetAttribute.restype = hipError_t - hipMemPoolSetAttribute.argtypes = [hipMemPool_t, hipMemPoolAttr, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolGetAttribute = _libraries['libamdhip64.so'].hipMemPoolGetAttribute - hipMemPoolGetAttribute.restype = hipError_t - hipMemPoolGetAttribute.argtypes = [hipMemPool_t, hipMemPoolAttr, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolSetAccess = _libraries['libamdhip64.so'].hipMemPoolSetAccess - hipMemPoolSetAccess.restype = hipError_t - hipMemPoolSetAccess.argtypes = [hipMemPool_t, ctypes.POINTER(struct_hipMemAccessDesc), size_t] -except AttributeError: - pass -try: - hipMemPoolGetAccess = _libraries['libamdhip64.so'].hipMemPoolGetAccess - hipMemPoolGetAccess.restype = hipError_t - hipMemPoolGetAccess.argtypes = [ctypes.POINTER(hipMemAccessFlags), hipMemPool_t, ctypes.POINTER(struct_hipMemLocation)] -except AttributeError: - pass -try: - hipMemPoolCreate = _libraries['libamdhip64.so'].hipMemPoolCreate - hipMemPoolCreate.restype = hipError_t - hipMemPoolCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.POINTER(struct_hipMemPoolProps)] -except AttributeError: - pass -try: - hipMemPoolDestroy = _libraries['libamdhip64.so'].hipMemPoolDestroy - hipMemPoolDestroy.restype = hipError_t - hipMemPoolDestroy.argtypes = [hipMemPool_t] -except AttributeError: - pass -try: - hipMallocFromPoolAsync = _libraries['libamdhip64.so'].hipMallocFromPoolAsync - hipMallocFromPoolAsync.restype = hipError_t - hipMallocFromPoolAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, hipMemPool_t, hipStream_t] -except AttributeError: - pass -try: - hipMemPoolExportToShareableHandle = _libraries['libamdhip64.so'].hipMemPoolExportToShareableHandle - hipMemPoolExportToShareableHandle.restype = hipError_t - hipMemPoolExportToShareableHandle.argtypes = [ctypes.POINTER(None), hipMemPool_t, hipMemAllocationHandleType, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPoolImportFromShareableHandle = _libraries['libamdhip64.so'].hipMemPoolImportFromShareableHandle - hipMemPoolImportFromShareableHandle.restype = hipError_t - hipMemPoolImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.POINTER(None), hipMemAllocationHandleType, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPoolExportPointer = _libraries['libamdhip64.so'].hipMemPoolExportPointer - hipMemPoolExportPointer.restype = hipError_t - hipMemPoolExportPointer.argtypes = [ctypes.POINTER(struct_hipMemPoolPtrExportData), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolImportPointer = _libraries['libamdhip64.so'].hipMemPoolImportPointer - hipMemPoolImportPointer.restype = hipError_t - hipMemPoolImportPointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipMemPool_t, ctypes.POINTER(struct_hipMemPoolPtrExportData)] -except AttributeError: - pass -try: - hipHostAlloc = _libraries['libamdhip64.so'].hipHostAlloc - hipHostAlloc.restype = hipError_t - hipHostAlloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostGetDevicePointer = _libraries['libamdhip64.so'].hipHostGetDevicePointer - hipHostGetDevicePointer.restype = hipError_t - hipHostGetDevicePointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostGetFlags = _libraries['libamdhip64.so'].hipHostGetFlags - hipHostGetFlags.restype = hipError_t - hipHostGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipHostRegister = _libraries['libamdhip64.so'].hipHostRegister - hipHostRegister.restype = hipError_t - hipHostRegister.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostUnregister = _libraries['libamdhip64.so'].hipHostUnregister - hipHostUnregister.restype = hipError_t - hipHostUnregister.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMallocPitch = _libraries['libamdhip64.so'].hipMallocPitch - hipMallocPitch.restype = hipError_t - hipMallocPitch.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), size_t, size_t] -except AttributeError: - pass -try: - hipMemAllocPitch = _libraries['libamdhip64.so'].hipMemAllocPitch - hipMemAllocPitch.restype = hipError_t - hipMemAllocPitch.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipFree = _libraries['libamdhip64.so'].hipFree - hipFree.restype = hipError_t - hipFree.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipFreeHost = _libraries['libamdhip64.so'].hipFreeHost - hipFreeHost.restype = hipError_t - hipFreeHost.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipHostFree = _libraries['libamdhip64.so'].hipHostFree - hipHostFree.restype = hipError_t - hipHostFree.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemcpy = _libraries['libamdhip64.so'].hipMemcpy - hipMemcpy.restype = hipError_t - hipMemcpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyWithStream = _libraries['libamdhip64.so'].hipMemcpyWithStream - hipMemcpyWithStream.restype = hipError_t - hipMemcpyWithStream.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyHtoD = _libraries['libamdhip64.so'].hipMemcpyHtoD - hipMemcpyHtoD.restype = hipError_t - hipMemcpyHtoD.argtypes = [hipDeviceptr_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemcpyDtoH = _libraries['libamdhip64.so'].hipMemcpyDtoH - hipMemcpyDtoH.restype = hipError_t - hipMemcpyDtoH.argtypes = [ctypes.POINTER(None), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipMemcpyDtoD = _libraries['libamdhip64.so'].hipMemcpyDtoD - hipMemcpyDtoD.restype = hipError_t - hipMemcpyDtoD.argtypes = [hipDeviceptr_t, hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipMemcpyHtoDAsync = _libraries['libamdhip64.so'].hipMemcpyHtoDAsync - hipMemcpyHtoDAsync.restype = hipError_t - hipMemcpyHtoDAsync.argtypes = [hipDeviceptr_t, ctypes.POINTER(None), size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyDtoHAsync = _libraries['libamdhip64.so'].hipMemcpyDtoHAsync - hipMemcpyDtoHAsync.restype = hipError_t - hipMemcpyDtoHAsync.argtypes = [ctypes.POINTER(None), hipDeviceptr_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyDtoDAsync = _libraries['libamdhip64.so'].hipMemcpyDtoDAsync - hipMemcpyDtoDAsync.restype = hipError_t - hipMemcpyDtoDAsync.argtypes = [hipDeviceptr_t, hipDeviceptr_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipModuleGetGlobal = _libraries['libamdhip64.so'].hipModuleGetGlobal - hipModuleGetGlobal.restype = hipError_t - hipModuleGetGlobal.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipGetSymbolAddress = _libraries['libamdhip64.so'].hipGetSymbolAddress - hipGetSymbolAddress.restype = hipError_t - hipGetSymbolAddress.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipGetSymbolSize = _libraries['libamdhip64.so'].hipGetSymbolSize - hipGetSymbolSize.restype = hipError_t - hipGetSymbolSize.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemcpyToSymbol = _libraries['libamdhip64.so'].hipMemcpyToSymbol - hipMemcpyToSymbol.restype = hipError_t - hipMemcpyToSymbol.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyToSymbolAsync = _libraries['libamdhip64.so'].hipMemcpyToSymbolAsync - hipMemcpyToSymbolAsync.restype = hipError_t - hipMemcpyToSymbolAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyFromSymbol = _libraries['libamdhip64.so'].hipMemcpyFromSymbol - hipMemcpyFromSymbol.restype = hipError_t - hipMemcpyFromSymbol.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyFromSymbolAsync = _libraries['libamdhip64.so'].hipMemcpyFromSymbolAsync - hipMemcpyFromSymbolAsync.restype = hipError_t - hipMemcpyFromSymbolAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyAsync = _libraries['libamdhip64.so'].hipMemcpyAsync - hipMemcpyAsync.restype = hipError_t - hipMemcpyAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemset = _libraries['libamdhip64.so'].hipMemset - hipMemset.restype = hipError_t - hipMemset.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemsetD8 = _libraries['libamdhip64.so'].hipMemsetD8 - hipMemsetD8.restype = hipError_t - hipMemsetD8.argtypes = [hipDeviceptr_t, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - hipMemsetD8Async = _libraries['libamdhip64.so'].hipMemsetD8Async - hipMemsetD8Async.restype = hipError_t - hipMemsetD8Async.argtypes = [hipDeviceptr_t, ctypes.c_ubyte, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD16 = _libraries['libamdhip64.so'].hipMemsetD16 - hipMemsetD16.restype = hipError_t - hipMemsetD16.argtypes = [hipDeviceptr_t, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - hipMemsetD16Async = _libraries['libamdhip64.so'].hipMemsetD16Async - hipMemsetD16Async.restype = hipError_t - hipMemsetD16Async.argtypes = [hipDeviceptr_t, ctypes.c_uint16, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD32 = _libraries['libamdhip64.so'].hipMemsetD32 - hipMemsetD32.restype = hipError_t - hipMemsetD32.argtypes = [hipDeviceptr_t, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemsetAsync = _libraries['libamdhip64.so'].hipMemsetAsync - hipMemsetAsync.restype = hipError_t - hipMemsetAsync.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD32Async = _libraries['libamdhip64.so'].hipMemsetD32Async - hipMemsetD32Async.restype = hipError_t - hipMemsetD32Async.argtypes = [hipDeviceptr_t, ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemset2D = _libraries['libamdhip64.so'].hipMemset2D - hipMemset2D.restype = hipError_t - hipMemset2D.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, size_t, size_t] -except AttributeError: - pass -try: - hipMemset2DAsync = _libraries['libamdhip64.so'].hipMemset2DAsync - hipMemset2DAsync.restype = hipError_t - hipMemset2DAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, size_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemset3D = _libraries['libamdhip64.so'].hipMemset3D - hipMemset3D.restype = hipError_t - hipMemset3D.argtypes = [hipPitchedPtr, ctypes.c_int32, hipExtent] -except AttributeError: - pass -try: - hipMemset3DAsync = _libraries['libamdhip64.so'].hipMemset3DAsync - hipMemset3DAsync.restype = hipError_t - hipMemset3DAsync.argtypes = [hipPitchedPtr, ctypes.c_int32, hipExtent, hipStream_t] -except AttributeError: - pass -try: - hipMemGetInfo = _libraries['libamdhip64.so'].hipMemGetInfo - hipMemGetInfo.restype = hipError_t - hipMemGetInfo.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipMemPtrGetInfo = _libraries['libamdhip64.so'].hipMemPtrGetInfo - hipMemPtrGetInfo.restype = hipError_t - hipMemPtrGetInfo.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipMallocArray = _libraries['libamdhip64.so'].hipMallocArray - hipMallocArray.restype = hipError_t - hipMallocArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_hipChannelFormatDesc), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipArrayCreate = _libraries['libamdhip64.so'].hipArrayCreate - hipArrayCreate.restype = hipError_t - hipArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR)] -except AttributeError: - pass -try: - hipArrayDestroy = _libraries['libamdhip64.so'].hipArrayDestroy - hipArrayDestroy.restype = hipError_t - hipArrayDestroy.argtypes = [hipArray_t] -except AttributeError: - pass -try: - hipArray3DCreate = _libraries['libamdhip64.so'].hipArray3DCreate - hipArray3DCreate.restype = hipError_t - hipArray3DCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR)] -except AttributeError: - pass -try: - hipMalloc3D = _libraries['libamdhip64.so'].hipMalloc3D - hipMalloc3D.restype = hipError_t - hipMalloc3D.argtypes = [ctypes.POINTER(struct_hipPitchedPtr), hipExtent] -except AttributeError: - pass -try: - hipFreeArray = _libraries['libamdhip64.so'].hipFreeArray - hipFreeArray.restype = hipError_t - hipFreeArray.argtypes = [hipArray_t] -except AttributeError: - pass -try: - hipMalloc3DArray = _libraries['libamdhip64.so'].hipMalloc3DArray - hipMalloc3DArray.restype = hipError_t - hipMalloc3DArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_hipChannelFormatDesc), struct_hipExtent, ctypes.c_uint32] -except AttributeError: - pass -try: - hipArrayGetInfo = _libraries['libamdhip64.so'].hipArrayGetInfo - hipArrayGetInfo.restype = hipError_t - hipArrayGetInfo.argtypes = [ctypes.POINTER(struct_hipChannelFormatDesc), ctypes.POINTER(struct_hipExtent), ctypes.POINTER(ctypes.c_uint32), hipArray_t] -except AttributeError: - pass -try: - hipArrayGetDescriptor = _libraries['libamdhip64.so'].hipArrayGetDescriptor - hipArrayGetDescriptor.restype = hipError_t - hipArrayGetDescriptor.argtypes = [ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR), hipArray_t] -except AttributeError: - pass -try: - hipArray3DGetDescriptor = _libraries['libamdhip64.so'].hipArray3DGetDescriptor - hipArray3DGetDescriptor.restype = hipError_t - hipArray3DGetDescriptor.argtypes = [ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR), hipArray_t] -except AttributeError: - pass -try: - hipMemcpy2D = _libraries['libamdhip64.so'].hipMemcpy2D - hipMemcpy2D.restype = hipError_t - hipMemcpy2D.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyParam2D = _libraries['libamdhip64.so'].hipMemcpyParam2D - hipMemcpyParam2D.restype = hipError_t - hipMemcpyParam2D.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D)] -except AttributeError: - pass -try: - hipMemcpyParam2DAsync = _libraries['libamdhip64.so'].hipMemcpyParam2DAsync - hipMemcpyParam2DAsync.restype = hipError_t - hipMemcpyParam2DAsync.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D), hipStream_t] -except AttributeError: - pass -try: - hipMemcpy2DAsync = _libraries['libamdhip64.so'].hipMemcpy2DAsync - hipMemcpy2DAsync.restype = hipError_t - hipMemcpy2DAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpy2DToArray = _libraries['libamdhip64.so'].hipMemcpy2DToArray - hipMemcpy2DToArray.restype = hipError_t - hipMemcpy2DToArray.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DToArrayAsync = _libraries['libamdhip64.so'].hipMemcpy2DToArrayAsync - hipMemcpy2DToArrayAsync.restype = hipError_t - hipMemcpy2DToArrayAsync.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyToArray = _libraries['libamdhip64.so'].hipMemcpyToArray - hipMemcpyToArray.restype = hipError_t - hipMemcpyToArray.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyFromArray = _libraries['libamdhip64.so'].hipMemcpyFromArray - hipMemcpyFromArray.restype = hipError_t - hipMemcpyFromArray.argtypes = [ctypes.POINTER(None), hipArray_const_t, size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DFromArray = _libraries['libamdhip64.so'].hipMemcpy2DFromArray - hipMemcpy2DFromArray.restype = hipError_t - hipMemcpy2DFromArray.argtypes = [ctypes.POINTER(None), size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DFromArrayAsync = _libraries['libamdhip64.so'].hipMemcpy2DFromArrayAsync - hipMemcpy2DFromArrayAsync.restype = hipError_t - hipMemcpy2DFromArrayAsync.argtypes = [ctypes.POINTER(None), size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyAtoH = _libraries['libamdhip64.so'].hipMemcpyAtoH - hipMemcpyAtoH.restype = hipError_t - hipMemcpyAtoH.argtypes = [ctypes.POINTER(None), hipArray_t, size_t, size_t] -except AttributeError: - pass -try: - hipMemcpyHtoA = _libraries['libamdhip64.so'].hipMemcpyHtoA - hipMemcpyHtoA.restype = hipError_t - hipMemcpyHtoA.argtypes = [hipArray_t, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemcpy3D = _libraries['libamdhip64.so'].hipMemcpy3D - hipMemcpy3D.restype = hipError_t - hipMemcpy3D.argtypes = [ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipMemcpy3DAsync = _libraries['libamdhip64.so'].hipMemcpy3DAsync - hipMemcpy3DAsync.restype = hipError_t - hipMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_hipMemcpy3DParms), hipStream_t] -except AttributeError: - pass -try: - hipDrvMemcpy3D = _libraries['libamdhip64.so'].hipDrvMemcpy3D - hipDrvMemcpy3D.restype = hipError_t - hipDrvMemcpy3D.argtypes = [ctypes.POINTER(struct_HIP_MEMCPY3D)] -except AttributeError: - pass -try: - hipDrvMemcpy3DAsync = _libraries['libamdhip64.so'].hipDrvMemcpy3DAsync - hipDrvMemcpy3DAsync.restype = hipError_t - hipDrvMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_HIP_MEMCPY3D), hipStream_t] -except AttributeError: - pass -try: - hipDeviceCanAccessPeer = _libraries['libamdhip64.so'].hipDeviceCanAccessPeer - hipDeviceCanAccessPeer.restype = hipError_t - hipDeviceCanAccessPeer.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceEnablePeerAccess = _libraries['libamdhip64.so'].hipDeviceEnablePeerAccess - hipDeviceEnablePeerAccess.restype = hipError_t - hipDeviceEnablePeerAccess.argtypes = [ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipDeviceDisablePeerAccess = _libraries['libamdhip64.so'].hipDeviceDisablePeerAccess - hipDeviceDisablePeerAccess.restype = hipError_t - hipDeviceDisablePeerAccess.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipMemGetAddressRange = _libraries['libamdhip64.so'].hipMemGetAddressRange - hipMemGetAddressRange.restype = hipError_t - hipMemGetAddressRange.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipDeviceptr_t] -except AttributeError: - pass -try: - hipMemcpyPeer = _libraries['libamdhip64.so'].hipMemcpyPeer - hipMemcpyPeer.restype = hipError_t - hipMemcpyPeer.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemcpyPeerAsync = _libraries['libamdhip64.so'].hipMemcpyPeerAsync - hipMemcpyPeerAsync.restype = hipError_t - hipMemcpyPeerAsync.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipCtxCreate = _libraries['libamdhip64.so'].hipCtxCreate - hipCtxCreate.restype = hipError_t - hipCtxCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t)), ctypes.c_uint32, hipDevice_t] -except AttributeError: - pass -try: - hipCtxDestroy = _libraries['libamdhip64.so'].hipCtxDestroy - hipCtxDestroy.restype = hipError_t - hipCtxDestroy.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxPopCurrent = _libraries['libamdhip64.so'].hipCtxPopCurrent - hipCtxPopCurrent.restype = hipError_t - hipCtxPopCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t))] -except AttributeError: - pass -try: - hipCtxPushCurrent = _libraries['libamdhip64.so'].hipCtxPushCurrent - hipCtxPushCurrent.restype = hipError_t - hipCtxPushCurrent.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxSetCurrent = _libraries['libamdhip64.so'].hipCtxSetCurrent - hipCtxSetCurrent.restype = hipError_t - hipCtxSetCurrent.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxGetCurrent = _libraries['libamdhip64.so'].hipCtxGetCurrent - hipCtxGetCurrent.restype = hipError_t - hipCtxGetCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t))] -except AttributeError: - pass -try: - hipCtxGetDevice = _libraries['libamdhip64.so'].hipCtxGetDevice - hipCtxGetDevice.restype = hipError_t - hipCtxGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipCtxGetApiVersion = _libraries['libamdhip64.so'].hipCtxGetApiVersion - hipCtxGetApiVersion.restype = hipError_t - hipCtxGetApiVersion.argtypes = [hipCtx_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipCtxGetCacheConfig = _libraries['libamdhip64.so'].hipCtxGetCacheConfig - hipCtxGetCacheConfig.restype = hipError_t - hipCtxGetCacheConfig.argtypes = [ctypes.POINTER(hipFuncCache_t)] -except AttributeError: - pass -try: - hipCtxSetCacheConfig = _libraries['libamdhip64.so'].hipCtxSetCacheConfig - hipCtxSetCacheConfig.restype = hipError_t - hipCtxSetCacheConfig.argtypes = [hipFuncCache_t] -except AttributeError: - pass -try: - hipCtxSetSharedMemConfig = _libraries['libamdhip64.so'].hipCtxSetSharedMemConfig - hipCtxSetSharedMemConfig.restype = hipError_t - hipCtxSetSharedMemConfig.argtypes = [hipSharedMemConfig] -except AttributeError: - pass -try: - hipCtxGetSharedMemConfig = _libraries['libamdhip64.so'].hipCtxGetSharedMemConfig - hipCtxGetSharedMemConfig.restype = hipError_t - hipCtxGetSharedMemConfig.argtypes = [ctypes.POINTER(hipSharedMemConfig)] -except AttributeError: - pass -try: - hipCtxSynchronize = _libraries['libamdhip64.so'].hipCtxSynchronize - hipCtxSynchronize.restype = hipError_t - hipCtxSynchronize.argtypes = [] -except AttributeError: - pass -try: - hipCtxGetFlags = _libraries['libamdhip64.so'].hipCtxGetFlags - hipCtxGetFlags.restype = hipError_t - hipCtxGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipCtxEnablePeerAccess = _libraries['libamdhip64.so'].hipCtxEnablePeerAccess - hipCtxEnablePeerAccess.restype = hipError_t - hipCtxEnablePeerAccess.argtypes = [hipCtx_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipCtxDisablePeerAccess = _libraries['libamdhip64.so'].hipCtxDisablePeerAccess - hipCtxDisablePeerAccess.restype = hipError_t - hipCtxDisablePeerAccess.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxGetState = _libraries['libamdhip64.so'].hipDevicePrimaryCtxGetState - hipDevicePrimaryCtxGetState.restype = hipError_t - hipDevicePrimaryCtxGetState.argtypes = [hipDevice_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDevicePrimaryCtxRelease = _libraries['libamdhip64.so'].hipDevicePrimaryCtxRelease - hipDevicePrimaryCtxRelease.restype = hipError_t - hipDevicePrimaryCtxRelease.argtypes = [hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxRetain = _libraries['libamdhip64.so'].hipDevicePrimaryCtxRetain - hipDevicePrimaryCtxRetain.restype = hipError_t - hipDevicePrimaryCtxRetain.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t)), hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxReset = _libraries['libamdhip64.so'].hipDevicePrimaryCtxReset - hipDevicePrimaryCtxReset.restype = hipError_t - hipDevicePrimaryCtxReset.argtypes = [hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxSetFlags = _libraries['libamdhip64.so'].hipDevicePrimaryCtxSetFlags - hipDevicePrimaryCtxSetFlags.restype = hipError_t - hipDevicePrimaryCtxSetFlags.argtypes = [hipDevice_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleLoad = _libraries['libamdhip64.so'].hipModuleLoad - hipModuleLoad.restype = hipError_t - hipModuleLoad.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipModuleUnload = _libraries['libamdhip64.so'].hipModuleUnload - hipModuleUnload.restype = hipError_t - hipModuleUnload.argtypes = [hipModule_t] -except AttributeError: - pass -try: - hipModuleGetFunction = _libraries['libamdhip64.so'].hipModuleGetFunction - hipModuleGetFunction.restype = hipError_t - hipModuleGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModuleSymbol_t)), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipFuncGetAttributes = _libraries['libamdhip64.so'].hipFuncGetAttributes - hipFuncGetAttributes.restype = hipError_t - hipFuncGetAttributes.argtypes = [ctypes.POINTER(struct_hipFuncAttributes), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipFuncGetAttribute = _libraries['libamdhip64.so'].hipFuncGetAttribute - hipFuncGetAttribute.restype = hipError_t - hipFuncGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_attribute, hipFunction_t] -except AttributeError: - pass -class struct_textureReference(Structure): - pass - -class struct___hip_texture(Structure): - pass - - -# values for enumeration 'hipTextureReadMode' -hipTextureReadMode__enumvalues = { - 0: 'hipReadModeElementType', - 1: 'hipReadModeNormalizedFloat', -} -hipReadModeElementType = 0 -hipReadModeNormalizedFloat = 1 -hipTextureReadMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipTextureFilterMode' -hipTextureFilterMode__enumvalues = { - 0: 'hipFilterModePoint', - 1: 'hipFilterModeLinear', -} -hipFilterModePoint = 0 -hipFilterModeLinear = 1 -hipTextureFilterMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipTextureAddressMode' -hipTextureAddressMode__enumvalues = { - 0: 'hipAddressModeWrap', - 1: 'hipAddressModeClamp', - 2: 'hipAddressModeMirror', - 3: 'hipAddressModeBorder', -} -hipAddressModeWrap = 0 -hipAddressModeClamp = 1 -hipAddressModeMirror = 2 -hipAddressModeBorder = 3 -hipTextureAddressMode = ctypes.c_uint32 # enum -struct_textureReference._pack_ = 1 # source:False -struct_textureReference._fields_ = [ - ('normalized', ctypes.c_int32), - ('readMode', hipTextureReadMode), - ('filterMode', hipTextureFilterMode), - ('addressMode', hipTextureAddressMode * 3), - ('channelDesc', struct_hipChannelFormatDesc), - ('sRGB', ctypes.c_int32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', hipTextureFilterMode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('PADDING_0', ctypes.c_ubyte * 4), - ('textureObject', ctypes.POINTER(struct___hip_texture)), - ('numChannels', ctypes.c_int32), - ('format', hipArray_Format), -] - -try: - hipModuleGetTexRef = _libraries['libamdhip64.so'].hipModuleGetTexRef - hipModuleGetTexRef.restype = hipError_t - hipModuleGetTexRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_textureReference)), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipModuleLoadData = _libraries['libamdhip64.so'].hipModuleLoadData - hipModuleLoadData.restype = hipError_t - hipModuleLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipModuleLoadDataEx = _libraries['libamdhip64.so'].hipModuleLoadDataEx - hipModuleLoadDataEx.restype = hipError_t - hipModuleLoadDataEx.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(None), ctypes.c_uint32, ctypes.POINTER(hipJitOption), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchKernel = _libraries['libamdhip64.so'].hipModuleLaunchKernel - hipModuleLaunchKernel.restype = hipError_t - hipModuleLaunchKernel.argtypes = [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchCooperativeKernel = _libraries['libamdhip64.so'].hipModuleLaunchCooperativeKernel - hipModuleLaunchCooperativeKernel.restype = hipError_t - hipModuleLaunchCooperativeKernel.argtypes = [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchCooperativeKernelMultiDevice = _libraries['libamdhip64.so'].hipModuleLaunchCooperativeKernelMultiDevice - hipModuleLaunchCooperativeKernelMultiDevice.restype = hipError_t - hipModuleLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipFunctionLaunchParams_t), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipLaunchCooperativeKernel = _libraries['libamdhip64.so'].hipLaunchCooperativeKernel - hipLaunchCooperativeKernel.restype = hipError_t - hipLaunchCooperativeKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipLaunchCooperativeKernelMultiDevice = _libraries['libamdhip64.so'].hipLaunchCooperativeKernelMultiDevice - hipLaunchCooperativeKernelMultiDevice.restype = hipError_t - hipLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipLaunchParams_t), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipExtLaunchMultiKernelMultiDevice = _libraries['libamdhip64.so'].hipExtLaunchMultiKernelMultiDevice - hipExtLaunchMultiKernelMultiDevice.restype = hipError_t - hipExtLaunchMultiKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipLaunchParams_t), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxPotentialBlockSize = _libraries['libamdhip64.so'].hipModuleOccupancyMaxPotentialBlockSize - hipModuleOccupancyMaxPotentialBlockSize.restype = hipError_t - hipModuleOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxPotentialBlockSizeWithFlags = _libraries['libamdhip64.so'].hipModuleOccupancyMaxPotentialBlockSizeWithFlags - hipModuleOccupancyMaxPotentialBlockSizeWithFlags.restype = hipError_t - hipModuleOccupancyMaxPotentialBlockSizeWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libamdhip64.so'].hipModuleOccupancyMaxActiveBlocksPerMultiprocessor - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor.restype = hipError_t - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libamdhip64.so'].hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = hipError_t - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libamdhip64.so'].hipOccupancyMaxActiveBlocksPerMultiprocessor - hipOccupancyMaxActiveBlocksPerMultiprocessor.restype = hipError_t - hipOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libamdhip64.so'].hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = hipError_t - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipOccupancyMaxPotentialBlockSize = _libraries['libamdhip64.so'].hipOccupancyMaxPotentialBlockSize - hipOccupancyMaxPotentialBlockSize.restype = hipError_t - hipOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipProfilerStart = _libraries['libamdhip64.so'].hipProfilerStart - hipProfilerStart.restype = hipError_t - hipProfilerStart.argtypes = [] -except AttributeError: - pass -try: - hipProfilerStop = _libraries['libamdhip64.so'].hipProfilerStop - hipProfilerStop.restype = hipError_t - hipProfilerStop.argtypes = [] -except AttributeError: - pass -try: - hipConfigureCall = _libraries['libamdhip64.so'].hipConfigureCall - hipConfigureCall.restype = hipError_t - hipConfigureCall.argtypes = [dim3, dim3, size_t, hipStream_t] -except AttributeError: - pass -try: - hipSetupArgument = _libraries['libamdhip64.so'].hipSetupArgument - hipSetupArgument.restype = hipError_t - hipSetupArgument.argtypes = [ctypes.POINTER(None), size_t, size_t] -except AttributeError: - pass -try: - hipLaunchByPtr = _libraries['libamdhip64.so'].hipLaunchByPtr - hipLaunchByPtr.restype = hipError_t - hipLaunchByPtr.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - __hipPushCallConfiguration = _libraries['libamdhip64.so'].__hipPushCallConfiguration - __hipPushCallConfiguration.restype = hipError_t - __hipPushCallConfiguration.argtypes = [dim3, dim3, size_t, hipStream_t] -except AttributeError: - pass -try: - __hipPopCallConfiguration = _libraries['libamdhip64.so'].__hipPopCallConfiguration - __hipPopCallConfiguration.restype = hipError_t - __hipPopCallConfiguration.argtypes = [ctypes.POINTER(struct_dim3), ctypes.POINTER(struct_dim3), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t))] -except AttributeError: - pass -try: - hipLaunchKernel = _libraries['libamdhip64.so'].hipLaunchKernel - hipLaunchKernel.restype = hipError_t - hipLaunchKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t] -except AttributeError: - pass -try: - hipLaunchHostFunc = _libraries['libamdhip64.so'].hipLaunchHostFunc - hipLaunchHostFunc.restype = hipError_t - hipLaunchHostFunc.argtypes = [hipStream_t, hipHostFn_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDrvMemcpy2DUnaligned = _libraries['libamdhip64.so'].hipDrvMemcpy2DUnaligned - hipDrvMemcpy2DUnaligned.restype = hipError_t - hipDrvMemcpy2DUnaligned.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D)] -except AttributeError: - pass -try: - hipExtLaunchKernel = _libraries['libamdhip64.so'].hipExtLaunchKernel - hipExtLaunchKernel.restype = hipError_t - hipExtLaunchKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t, hipEvent_t, hipEvent_t, ctypes.c_int32] -except AttributeError: - pass -class struct_hipTextureDesc(Structure): - pass - -struct_hipTextureDesc._pack_ = 1 # source:False -struct_hipTextureDesc._fields_ = [ - ('addressMode', hipTextureAddressMode * 3), - ('filterMode', hipTextureFilterMode), - ('readMode', hipTextureReadMode), - ('sRGB', ctypes.c_int32), - ('borderColor', ctypes.c_float * 4), - ('normalizedCoords', ctypes.c_int32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', hipTextureFilterMode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), -] - -try: - hipCreateTextureObject = _libraries['libamdhip64.so'].hipCreateTextureObject - hipCreateTextureObject.restype = hipError_t - hipCreateTextureObject.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_texture)), ctypes.POINTER(struct_hipResourceDesc), ctypes.POINTER(struct_hipTextureDesc), ctypes.POINTER(struct_hipResourceViewDesc)] -except AttributeError: - pass -hipTextureObject_t = ctypes.POINTER(struct___hip_texture) -try: - hipDestroyTextureObject = _libraries['libamdhip64.so'].hipDestroyTextureObject - hipDestroyTextureObject.restype = hipError_t - hipDestroyTextureObject.argtypes = [hipTextureObject_t] -except AttributeError: - pass -try: - hipGetChannelDesc = _libraries['libamdhip64.so'].hipGetChannelDesc - hipGetChannelDesc.restype = hipError_t - hipGetChannelDesc.argtypes = [ctypes.POINTER(struct_hipChannelFormatDesc), hipArray_const_t] -except AttributeError: - pass -try: - hipGetTextureObjectResourceDesc = _libraries['libamdhip64.so'].hipGetTextureObjectResourceDesc - hipGetTextureObjectResourceDesc.restype = hipError_t - hipGetTextureObjectResourceDesc.argtypes = [ctypes.POINTER(struct_hipResourceDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipGetTextureObjectResourceViewDesc = _libraries['libamdhip64.so'].hipGetTextureObjectResourceViewDesc - hipGetTextureObjectResourceViewDesc.restype = hipError_t - hipGetTextureObjectResourceViewDesc.argtypes = [ctypes.POINTER(struct_hipResourceViewDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipGetTextureObjectTextureDesc = _libraries['libamdhip64.so'].hipGetTextureObjectTextureDesc - hipGetTextureObjectTextureDesc.restype = hipError_t - hipGetTextureObjectTextureDesc.argtypes = [ctypes.POINTER(struct_hipTextureDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectCreate = _libraries['libamdhip64.so'].hipTexObjectCreate - hipTexObjectCreate.restype = hipError_t - hipTexObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_texture)), ctypes.POINTER(struct_HIP_RESOURCE_DESC_st), ctypes.POINTER(struct_HIP_TEXTURE_DESC_st), ctypes.POINTER(struct_HIP_RESOURCE_VIEW_DESC_st)] -except AttributeError: - pass -try: - hipTexObjectDestroy = _libraries['libamdhip64.so'].hipTexObjectDestroy - hipTexObjectDestroy.restype = hipError_t - hipTexObjectDestroy.argtypes = [hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetResourceDesc = _libraries['libamdhip64.so'].hipTexObjectGetResourceDesc - hipTexObjectGetResourceDesc.restype = hipError_t - hipTexObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_HIP_RESOURCE_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetResourceViewDesc = _libraries['libamdhip64.so'].hipTexObjectGetResourceViewDesc - hipTexObjectGetResourceViewDesc.restype = hipError_t - hipTexObjectGetResourceViewDesc.argtypes = [ctypes.POINTER(struct_HIP_RESOURCE_VIEW_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetTextureDesc = _libraries['libamdhip64.so'].hipTexObjectGetTextureDesc - hipTexObjectGetTextureDesc.restype = hipError_t - hipTexObjectGetTextureDesc.argtypes = [ctypes.POINTER(struct_HIP_TEXTURE_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipMallocMipmappedArray = _libraries['libamdhip64.so'].hipMallocMipmappedArray - hipMallocMipmappedArray.restype = hipError_t - hipMallocMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_hipChannelFormatDesc), struct_hipExtent, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipFreeMipmappedArray = _libraries['libamdhip64.so'].hipFreeMipmappedArray - hipFreeMipmappedArray.restype = hipError_t - hipFreeMipmappedArray.argtypes = [hipMipmappedArray_t] -except AttributeError: - pass -try: - hipGetMipmappedArrayLevel = _libraries['libamdhip64.so'].hipGetMipmappedArrayLevel - hipGetMipmappedArrayLevel.restype = hipError_t - hipGetMipmappedArrayLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipMipmappedArray_const_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMipmappedArrayCreate = _libraries['libamdhip64.so'].hipMipmappedArrayCreate - hipMipmappedArrayCreate.restype = hipError_t - hipMipmappedArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR), ctypes.c_uint32] -except AttributeError: - pass -try: - hipMipmappedArrayDestroy = _libraries['libamdhip64.so'].hipMipmappedArrayDestroy - hipMipmappedArrayDestroy.restype = hipError_t - hipMipmappedArrayDestroy.argtypes = [hipMipmappedArray_t] -except AttributeError: - pass -try: - hipMipmappedArrayGetLevel = _libraries['libamdhip64.so'].hipMipmappedArrayGetLevel - hipMipmappedArrayGetLevel.restype = hipError_t - hipMipmappedArrayGetLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipMipmappedArray_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipBindTextureToMipmappedArray = _libraries['libamdhip64.so'].hipBindTextureToMipmappedArray - hipBindTextureToMipmappedArray.restype = hipError_t - hipBindTextureToMipmappedArray.argtypes = [ctypes.POINTER(struct_textureReference), hipMipmappedArray_const_t, ctypes.POINTER(struct_hipChannelFormatDesc)] -except AttributeError: - pass -try: - hipGetTextureReference = _libraries['libamdhip64.so'].hipGetTextureReference - hipGetTextureReference.restype = hipError_t - hipGetTextureReference.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_textureReference)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipTexRefSetAddressMode = _libraries['libamdhip64.so'].hipTexRefSetAddressMode - hipTexRefSetAddressMode.restype = hipError_t - hipTexRefSetAddressMode.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_int32, hipTextureAddressMode] -except AttributeError: - pass -try: - hipTexRefSetArray = _libraries['libamdhip64.so'].hipTexRefSetArray - hipTexRefSetArray.restype = hipError_t - hipTexRefSetArray.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_const_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetFilterMode = _libraries['libamdhip64.so'].hipTexRefSetFilterMode - hipTexRefSetFilterMode.restype = hipError_t - hipTexRefSetFilterMode.argtypes = [ctypes.POINTER(struct_textureReference), hipTextureFilterMode] -except AttributeError: - pass -try: - hipTexRefSetFlags = _libraries['libamdhip64.so'].hipTexRefSetFlags - hipTexRefSetFlags.restype = hipError_t - hipTexRefSetFlags.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetFormat = _libraries['libamdhip64.so'].hipTexRefSetFormat - hipTexRefSetFormat.restype = hipError_t - hipTexRefSetFormat.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_Format, ctypes.c_int32] -except AttributeError: - pass -try: - hipBindTexture = _libraries['libamdhip64.so'].hipBindTexture - hipBindTexture.restype = hipError_t - hipBindTexture.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), ctypes.POINTER(None), ctypes.POINTER(struct_hipChannelFormatDesc), size_t] -except AttributeError: - pass -try: - hipBindTexture2D = _libraries['libamdhip64.so'].hipBindTexture2D - hipBindTexture2D.restype = hipError_t - hipBindTexture2D.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), ctypes.POINTER(None), ctypes.POINTER(struct_hipChannelFormatDesc), size_t, size_t, size_t] -except AttributeError: - pass -try: - hipBindTextureToArray = _libraries['libamdhip64.so'].hipBindTextureToArray - hipBindTextureToArray.restype = hipError_t - hipBindTextureToArray.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_const_t, ctypes.POINTER(struct_hipChannelFormatDesc)] -except AttributeError: - pass -try: - hipGetTextureAlignmentOffset = _libraries['libamdhip64.so'].hipGetTextureAlignmentOffset - hipGetTextureAlignmentOffset.restype = hipError_t - hipGetTextureAlignmentOffset.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipUnbindTexture = _libraries['libamdhip64.so'].hipUnbindTexture - hipUnbindTexture.restype = hipError_t - hipUnbindTexture.argtypes = [ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetAddress = _libraries['libamdhip64.so'].hipTexRefGetAddress - hipTexRefGetAddress.restype = hipError_t - hipTexRefGetAddress.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetAddressMode = _libraries['libamdhip64.so'].hipTexRefGetAddressMode - hipTexRefGetAddressMode.restype = hipError_t - hipTexRefGetAddressMode.argtypes = [ctypes.POINTER(hipTextureAddressMode), ctypes.POINTER(struct_textureReference), ctypes.c_int32] -except AttributeError: - pass -try: - hipTexRefGetFilterMode = _libraries['libamdhip64.so'].hipTexRefGetFilterMode - hipTexRefGetFilterMode.restype = hipError_t - hipTexRefGetFilterMode.argtypes = [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetFlags = _libraries['libamdhip64.so'].hipTexRefGetFlags - hipTexRefGetFlags.restype = hipError_t - hipTexRefGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetFormat = _libraries['libamdhip64.so'].hipTexRefGetFormat - hipTexRefGetFormat.restype = hipError_t - hipTexRefGetFormat.argtypes = [ctypes.POINTER(hipArray_Format), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMaxAnisotropy = _libraries['libamdhip64.so'].hipTexRefGetMaxAnisotropy - hipTexRefGetMaxAnisotropy.restype = hipError_t - hipTexRefGetMaxAnisotropy.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapFilterMode = _libraries['libamdhip64.so'].hipTexRefGetMipmapFilterMode - hipTexRefGetMipmapFilterMode.restype = hipError_t - hipTexRefGetMipmapFilterMode.argtypes = [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapLevelBias = _libraries['libamdhip64.so'].hipTexRefGetMipmapLevelBias - hipTexRefGetMipmapLevelBias.restype = hipError_t - hipTexRefGetMipmapLevelBias.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapLevelClamp = _libraries['libamdhip64.so'].hipTexRefGetMipmapLevelClamp - hipTexRefGetMipmapLevelClamp.restype = hipError_t - hipTexRefGetMipmapLevelClamp.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipMappedArray = _libraries['FIXME_STUB'].hipTexRefGetMipMappedArray - hipTexRefGetMipMappedArray.restype = hipError_t - hipTexRefGetMipMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefSetAddress = _libraries['libamdhip64.so'].hipTexRefSetAddress - hipTexRefSetAddress.restype = hipError_t - hipTexRefSetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipTexRefSetAddress2D = _libraries['libamdhip64.so'].hipTexRefSetAddress2D - hipTexRefSetAddress2D.restype = hipError_t - hipTexRefSetAddress2D.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipTexRefSetMaxAnisotropy = _libraries['libamdhip64.so'].hipTexRefSetMaxAnisotropy - hipTexRefSetMaxAnisotropy.restype = hipError_t - hipTexRefSetMaxAnisotropy.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetBorderColor = _libraries['libamdhip64.so'].hipTexRefSetBorderColor - hipTexRefSetBorderColor.restype = hipError_t - hipTexRefSetBorderColor.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(ctypes.c_float)] -except AttributeError: - pass -try: - hipTexRefSetMipmapFilterMode = _libraries['libamdhip64.so'].hipTexRefSetMipmapFilterMode - hipTexRefSetMipmapFilterMode.restype = hipError_t - hipTexRefSetMipmapFilterMode.argtypes = [ctypes.POINTER(struct_textureReference), hipTextureFilterMode] -except AttributeError: - pass -try: - hipTexRefSetMipmapLevelBias = _libraries['libamdhip64.so'].hipTexRefSetMipmapLevelBias - hipTexRefSetMipmapLevelBias.restype = hipError_t - hipTexRefSetMipmapLevelBias.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_float] -except AttributeError: - pass -try: - hipTexRefSetMipmapLevelClamp = _libraries['libamdhip64.so'].hipTexRefSetMipmapLevelClamp - hipTexRefSetMipmapLevelClamp.restype = hipError_t - hipTexRefSetMipmapLevelClamp.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - hipTexRefSetMipmappedArray = _libraries['libamdhip64.so'].hipTexRefSetMipmappedArray - hipTexRefSetMipmappedArray.restype = hipError_t - hipTexRefSetMipmappedArray.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(struct_hipMipmappedArray), ctypes.c_uint32] -except AttributeError: - pass -try: - hipApiName = _libraries['libamdhip64.so'].hipApiName - hipApiName.restype = ctypes.POINTER(ctypes.c_char) - hipApiName.argtypes = [uint32_t] -except AttributeError: - pass -try: - hipKernelNameRef = _libraries['libamdhip64.so'].hipKernelNameRef - hipKernelNameRef.restype = ctypes.POINTER(ctypes.c_char) - hipKernelNameRef.argtypes = [hipFunction_t] -except AttributeError: - pass -try: - hipKernelNameRefByPtr = _libraries['libamdhip64.so'].hipKernelNameRefByPtr - hipKernelNameRefByPtr.restype = ctypes.POINTER(ctypes.c_char) - hipKernelNameRefByPtr.argtypes = [ctypes.POINTER(None), hipStream_t] -except AttributeError: - pass -try: - hipGetStreamDeviceId = _libraries['libamdhip64.so'].hipGetStreamDeviceId - hipGetStreamDeviceId.restype = ctypes.c_int32 - hipGetStreamDeviceId.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamBeginCapture = _libraries['libamdhip64.so'].hipStreamBeginCapture - hipStreamBeginCapture.restype = hipError_t - hipStreamBeginCapture.argtypes = [hipStream_t, hipStreamCaptureMode] -except AttributeError: - pass -try: - hipStreamEndCapture = _libraries['libamdhip64.so'].hipStreamEndCapture - hipStreamEndCapture.restype = hipError_t - hipStreamEndCapture.argtypes = [hipStream_t, ctypes.POINTER(ctypes.POINTER(struct_ihipGraph))] -except AttributeError: - pass -try: - hipStreamGetCaptureInfo = _libraries['libamdhip64.so'].hipStreamGetCaptureInfo - hipStreamGetCaptureInfo.restype = hipError_t - hipStreamGetCaptureInfo.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipStreamGetCaptureInfo_v2 = _libraries['libamdhip64.so'].hipStreamGetCaptureInfo_v2 - hipStreamGetCaptureInfo_v2.restype = hipError_t - hipStreamGetCaptureInfo_v2.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipStreamIsCapturing = _libraries['libamdhip64.so'].hipStreamIsCapturing - hipStreamIsCapturing.restype = hipError_t - hipStreamIsCapturing.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus)] -except AttributeError: - pass -try: - hipStreamUpdateCaptureDependencies = _libraries['libamdhip64.so'].hipStreamUpdateCaptureDependencies - hipStreamUpdateCaptureDependencies.restype = hipError_t - hipStreamUpdateCaptureDependencies.argtypes = [hipStream_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipThreadExchangeStreamCaptureMode = _libraries['libamdhip64.so'].hipThreadExchangeStreamCaptureMode - hipThreadExchangeStreamCaptureMode.restype = hipError_t - hipThreadExchangeStreamCaptureMode.argtypes = [ctypes.POINTER(hipStreamCaptureMode)] -except AttributeError: - pass -try: - hipGraphCreate = _libraries['libamdhip64.so'].hipGraphCreate - hipGraphCreate.restype = hipError_t - hipGraphCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphDestroy = _libraries['libamdhip64.so'].hipGraphDestroy - hipGraphDestroy.restype = hipError_t - hipGraphDestroy.argtypes = [hipGraph_t] -except AttributeError: - pass -try: - hipGraphAddDependencies = _libraries['libamdhip64.so'].hipGraphAddDependencies - hipGraphAddDependencies.restype = hipError_t - hipGraphAddDependencies.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphRemoveDependencies = _libraries['libamdhip64.so'].hipGraphRemoveDependencies - hipGraphRemoveDependencies.restype = hipError_t - hipGraphRemoveDependencies.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphGetEdges = _libraries['libamdhip64.so'].hipGraphGetEdges - hipGraphGetEdges.restype = hipError_t - hipGraphGetEdges.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphGetNodes = _libraries['libamdhip64.so'].hipGraphGetNodes - hipGraphGetNodes.restype = hipError_t - hipGraphGetNodes.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphGetRootNodes = _libraries['libamdhip64.so'].hipGraphGetRootNodes - hipGraphGetRootNodes.restype = hipError_t - hipGraphGetRootNodes.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetDependencies = _libraries['libamdhip64.so'].hipGraphNodeGetDependencies - hipGraphNodeGetDependencies.restype = hipError_t - hipGraphNodeGetDependencies.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetDependentNodes = _libraries['libamdhip64.so'].hipGraphNodeGetDependentNodes - hipGraphNodeGetDependentNodes.restype = hipError_t - hipGraphNodeGetDependentNodes.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetType = _libraries['libamdhip64.so'].hipGraphNodeGetType - hipGraphNodeGetType.restype = hipError_t - hipGraphNodeGetType.argtypes = [hipGraphNode_t, ctypes.POINTER(hipGraphNodeType)] -except AttributeError: - pass -try: - hipGraphDestroyNode = _libraries['libamdhip64.so'].hipGraphDestroyNode - hipGraphDestroyNode.restype = hipError_t - hipGraphDestroyNode.argtypes = [hipGraphNode_t] -except AttributeError: - pass -try: - hipGraphClone = _libraries['libamdhip64.so'].hipGraphClone - hipGraphClone.restype = hipError_t - hipGraphClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), hipGraph_t] -except AttributeError: - pass -try: - hipGraphNodeFindInClone = _libraries['libamdhip64.so'].hipGraphNodeFindInClone - hipGraphNodeFindInClone.restype = hipError_t - hipGraphNodeFindInClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraphNode_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphInstantiate = _libraries['libamdhip64.so'].hipGraphInstantiate - hipGraphInstantiate.restype = hipError_t - hipGraphInstantiate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphExec)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - hipGraphInstantiateWithFlags = _libraries['libamdhip64.so'].hipGraphInstantiateWithFlags - hipGraphInstantiateWithFlags.restype = hipError_t - hipGraphInstantiateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphExec)), hipGraph_t, ctypes.c_uint64] -except AttributeError: - pass -try: - hipGraphLaunch = _libraries['libamdhip64.so'].hipGraphLaunch - hipGraphLaunch.restype = hipError_t - hipGraphLaunch.argtypes = [hipGraphExec_t, hipStream_t] -except AttributeError: - pass -try: - hipGraphUpload = _libraries['libamdhip64.so'].hipGraphUpload - hipGraphUpload.restype = hipError_t - hipGraphUpload.argtypes = [hipGraphExec_t, hipStream_t] -except AttributeError: - pass -try: - hipGraphExecDestroy = _libraries['libamdhip64.so'].hipGraphExecDestroy - hipGraphExecDestroy.restype = hipError_t - hipGraphExecDestroy.argtypes = [hipGraphExec_t] -except AttributeError: - pass -try: - hipGraphExecUpdate = _libraries['libamdhip64.so'].hipGraphExecUpdate - hipGraphExecUpdate.restype = hipError_t - hipGraphExecUpdate.argtypes = [hipGraphExec_t, hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(hipGraphExecUpdateResult)] -except AttributeError: - pass -try: - hipGraphAddKernelNode = _libraries['libamdhip64.so'].hipGraphAddKernelNode - hipGraphAddKernelNode.restype = hipError_t - hipGraphAddKernelNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphKernelNodeGetParams = _libraries['libamdhip64.so'].hipGraphKernelNodeGetParams - hipGraphKernelNodeGetParams.restype = hipError_t - hipGraphKernelNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphKernelNodeSetParams = _libraries['libamdhip64.so'].hipGraphKernelNodeSetParams - hipGraphKernelNodeSetParams.restype = hipError_t - hipGraphKernelNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphExecKernelNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecKernelNodeSetParams - hipGraphExecKernelNodeSetParams.restype = hipError_t - hipGraphExecKernelNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipDrvGraphAddMemcpyNode = _libraries['FIXME_STUB'].hipDrvGraphAddMemcpyNode - hipDrvGraphAddMemcpyNode.restype = hipError_t - hipDrvGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_HIP_MEMCPY3D), hipCtx_t] -except AttributeError: - pass -try: - hipGraphAddMemcpyNode = _libraries['libamdhip64.so'].hipGraphAddMemcpyNode - hipGraphAddMemcpyNode.restype = hipError_t - hipGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphMemcpyNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemcpyNodeGetParams - hipGraphMemcpyNodeGetParams.restype = hipError_t - hipGraphMemcpyNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParams = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParams - hipGraphMemcpyNodeSetParams.restype = hipError_t - hipGraphMemcpyNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphKernelNodeSetAttribute = _libraries['libamdhip64.so'].hipGraphKernelNodeSetAttribute - hipGraphKernelNodeSetAttribute.restype = hipError_t - hipGraphKernelNodeSetAttribute.argtypes = [hipGraphNode_t, hipKernelNodeAttrID, ctypes.POINTER(union_hipKernelNodeAttrValue)] -except AttributeError: - pass -try: - hipGraphKernelNodeGetAttribute = _libraries['libamdhip64.so'].hipGraphKernelNodeGetAttribute - hipGraphKernelNodeGetAttribute.restype = hipError_t - hipGraphKernelNodeGetAttribute.argtypes = [hipGraphNode_t, hipKernelNodeAttrID, ctypes.POINTER(union_hipKernelNodeAttrValue)] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParams - hipGraphExecMemcpyNodeSetParams.restype = hipError_t - hipGraphExecMemcpyNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphAddMemcpyNode1D = _libraries['libamdhip64.so'].hipGraphAddMemcpyNode1D - hipGraphAddMemcpyNode1D.restype = hipError_t - hipGraphAddMemcpyNode1D.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParams1D = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParams1D - hipGraphMemcpyNodeSetParams1D.restype = hipError_t - hipGraphMemcpyNodeSetParams1D.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParams1D = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParams1D - hipGraphExecMemcpyNodeSetParams1D.restype = hipError_t - hipGraphExecMemcpyNodeSetParams1D.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemcpyNodeFromSymbol = _libraries['libamdhip64.so'].hipGraphAddMemcpyNodeFromSymbol - hipGraphAddMemcpyNodeFromSymbol.restype = hipError_t - hipGraphAddMemcpyNodeFromSymbol.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParamsFromSymbol = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParamsFromSymbol - hipGraphMemcpyNodeSetParamsFromSymbol.restype = hipError_t - hipGraphMemcpyNodeSetParamsFromSymbol.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParamsFromSymbol = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParamsFromSymbol - hipGraphExecMemcpyNodeSetParamsFromSymbol.restype = hipError_t - hipGraphExecMemcpyNodeSetParamsFromSymbol.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemcpyNodeToSymbol = _libraries['libamdhip64.so'].hipGraphAddMemcpyNodeToSymbol - hipGraphAddMemcpyNodeToSymbol.restype = hipError_t - hipGraphAddMemcpyNodeToSymbol.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParamsToSymbol = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParamsToSymbol - hipGraphMemcpyNodeSetParamsToSymbol.restype = hipError_t - hipGraphMemcpyNodeSetParamsToSymbol.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParamsToSymbol = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParamsToSymbol - hipGraphExecMemcpyNodeSetParamsToSymbol.restype = hipError_t - hipGraphExecMemcpyNodeSetParamsToSymbol.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemsetNode = _libraries['libamdhip64.so'].hipGraphAddMemsetNode - hipGraphAddMemsetNode.restype = hipError_t - hipGraphAddMemsetNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphMemsetNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemsetNodeGetParams - hipGraphMemsetNodeGetParams.restype = hipError_t - hipGraphMemsetNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphMemsetNodeSetParams = _libraries['libamdhip64.so'].hipGraphMemsetNodeSetParams - hipGraphMemsetNodeSetParams.restype = hipError_t - hipGraphMemsetNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphExecMemsetNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecMemsetNodeSetParams - hipGraphExecMemsetNodeSetParams.restype = hipError_t - hipGraphExecMemsetNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphAddHostNode = _libraries['libamdhip64.so'].hipGraphAddHostNode - hipGraphAddHostNode.restype = hipError_t - hipGraphAddHostNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphHostNodeGetParams = _libraries['libamdhip64.so'].hipGraphHostNodeGetParams - hipGraphHostNodeGetParams.restype = hipError_t - hipGraphHostNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphHostNodeSetParams = _libraries['libamdhip64.so'].hipGraphHostNodeSetParams - hipGraphHostNodeSetParams.restype = hipError_t - hipGraphHostNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphExecHostNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecHostNodeSetParams - hipGraphExecHostNodeSetParams.restype = hipError_t - hipGraphExecHostNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphAddChildGraphNode = _libraries['libamdhip64.so'].hipGraphAddChildGraphNode - hipGraphAddChildGraphNode.restype = hipError_t - hipGraphAddChildGraphNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphChildGraphNodeGetGraph = _libraries['libamdhip64.so'].hipGraphChildGraphNodeGetGraph - hipGraphChildGraphNodeGetGraph.restype = hipError_t - hipGraphChildGraphNodeGetGraph.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipGraph))] -except AttributeError: - pass -try: - hipGraphExecChildGraphNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecChildGraphNodeSetParams - hipGraphExecChildGraphNodeSetParams.restype = hipError_t - hipGraphExecChildGraphNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphAddEmptyNode = _libraries['libamdhip64.so'].hipGraphAddEmptyNode - hipGraphAddEmptyNode.restype = hipError_t - hipGraphAddEmptyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphAddEventRecordNode = _libraries['libamdhip64.so'].hipGraphAddEventRecordNode - hipGraphAddEventRecordNode.restype = hipError_t - hipGraphAddEventRecordNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphEventRecordNodeGetEvent = _libraries['libamdhip64.so'].hipGraphEventRecordNodeGetEvent - hipGraphEventRecordNodeGetEvent.restype = hipError_t - hipGraphEventRecordNodeGetEvent.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipGraphEventRecordNodeSetEvent = _libraries['libamdhip64.so'].hipGraphEventRecordNodeSetEvent - hipGraphEventRecordNodeSetEvent.restype = hipError_t - hipGraphEventRecordNodeSetEvent.argtypes = [hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphExecEventRecordNodeSetEvent = _libraries['libamdhip64.so'].hipGraphExecEventRecordNodeSetEvent - hipGraphExecEventRecordNodeSetEvent.restype = hipError_t - hipGraphExecEventRecordNodeSetEvent.argtypes = [hipGraphExec_t, hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphAddEventWaitNode = _libraries['libamdhip64.so'].hipGraphAddEventWaitNode - hipGraphAddEventWaitNode.restype = hipError_t - hipGraphAddEventWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphEventWaitNodeGetEvent = _libraries['libamdhip64.so'].hipGraphEventWaitNodeGetEvent - hipGraphEventWaitNodeGetEvent.restype = hipError_t - hipGraphEventWaitNodeGetEvent.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipGraphEventWaitNodeSetEvent = _libraries['libamdhip64.so'].hipGraphEventWaitNodeSetEvent - hipGraphEventWaitNodeSetEvent.restype = hipError_t - hipGraphEventWaitNodeSetEvent.argtypes = [hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphExecEventWaitNodeSetEvent = _libraries['libamdhip64.so'].hipGraphExecEventWaitNodeSetEvent - hipGraphExecEventWaitNodeSetEvent.restype = hipError_t - hipGraphExecEventWaitNodeSetEvent.argtypes = [hipGraphExec_t, hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphAddMemAllocNode = _libraries['libamdhip64.so'].hipGraphAddMemAllocNode - hipGraphAddMemAllocNode.restype = hipError_t - hipGraphAddMemAllocNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemAllocNodeParams)] -except AttributeError: - pass -try: - hipGraphMemAllocNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemAllocNodeGetParams - hipGraphMemAllocNodeGetParams.restype = hipError_t - hipGraphMemAllocNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemAllocNodeParams)] -except AttributeError: - pass -try: - hipGraphAddMemFreeNode = _libraries['libamdhip64.so'].hipGraphAddMemFreeNode - hipGraphAddMemFreeNode.restype = hipError_t - hipGraphAddMemFreeNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipGraphMemFreeNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemFreeNodeGetParams - hipGraphMemFreeNodeGetParams.restype = hipError_t - hipGraphMemFreeNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceGetGraphMemAttribute = _libraries['libamdhip64.so'].hipDeviceGetGraphMemAttribute - hipDeviceGetGraphMemAttribute.restype = hipError_t - hipDeviceGetGraphMemAttribute.argtypes = [ctypes.c_int32, hipGraphMemAttributeType, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceSetGraphMemAttribute = _libraries['libamdhip64.so'].hipDeviceSetGraphMemAttribute - hipDeviceSetGraphMemAttribute.restype = hipError_t - hipDeviceSetGraphMemAttribute.argtypes = [ctypes.c_int32, hipGraphMemAttributeType, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceGraphMemTrim = _libraries['libamdhip64.so'].hipDeviceGraphMemTrim - hipDeviceGraphMemTrim.restype = hipError_t - hipDeviceGraphMemTrim.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipUserObjectCreate = _libraries['libamdhip64.so'].hipUserObjectCreate - hipUserObjectCreate.restype = hipError_t - hipUserObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipUserObject)), ctypes.POINTER(None), hipHostFn_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipUserObjectRelease = _libraries['libamdhip64.so'].hipUserObjectRelease - hipUserObjectRelease.restype = hipError_t - hipUserObjectRelease.argtypes = [hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipUserObjectRetain = _libraries['libamdhip64.so'].hipUserObjectRetain - hipUserObjectRetain.restype = hipError_t - hipUserObjectRetain.argtypes = [hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphRetainUserObject = _libraries['libamdhip64.so'].hipGraphRetainUserObject - hipGraphRetainUserObject.restype = hipError_t - hipGraphRetainUserObject.argtypes = [hipGraph_t, hipUserObject_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphReleaseUserObject = _libraries['libamdhip64.so'].hipGraphReleaseUserObject - hipGraphReleaseUserObject.restype = hipError_t - hipGraphReleaseUserObject.argtypes = [hipGraph_t, hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphDebugDotPrint = _libraries['libamdhip64.so'].hipGraphDebugDotPrint - hipGraphDebugDotPrint.restype = hipError_t - hipGraphDebugDotPrint.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphKernelNodeCopyAttributes = _libraries['libamdhip64.so'].hipGraphKernelNodeCopyAttributes - hipGraphKernelNodeCopyAttributes.restype = hipError_t - hipGraphKernelNodeCopyAttributes.argtypes = [hipGraphNode_t, hipGraphNode_t] -except AttributeError: - pass -try: - hipGraphNodeSetEnabled = _libraries['libamdhip64.so'].hipGraphNodeSetEnabled - hipGraphNodeSetEnabled.restype = hipError_t - hipGraphNodeSetEnabled.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphNodeGetEnabled = _libraries['libamdhip64.so'].hipGraphNodeGetEnabled - hipGraphNodeGetEnabled.restype = hipError_t - hipGraphNodeGetEnabled.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipMemAddressFree = _libraries['libamdhip64.so'].hipMemAddressFree - hipMemAddressFree.restype = hipError_t - hipMemAddressFree.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemAddressReserve = _libraries['libamdhip64.so'].hipMemAddressReserve - hipMemAddressReserve.restype = hipError_t - hipMemAddressReserve.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, size_t, ctypes.POINTER(None), ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemCreate = _libraries['libamdhip64.so'].hipMemCreate - hipMemCreate.restype = hipError_t - hipMemCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), size_t, ctypes.POINTER(struct_hipMemAllocationProp), ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemExportToShareableHandle = _libraries['libamdhip64.so'].hipMemExportToShareableHandle - hipMemExportToShareableHandle.restype = hipError_t - hipMemExportToShareableHandle.argtypes = [ctypes.POINTER(None), hipMemGenericAllocationHandle_t, hipMemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemGetAccess = _libraries['libamdhip64.so'].hipMemGetAccess - hipMemGetAccess.restype = hipError_t - hipMemGetAccess.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_hipMemLocation), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemGetAllocationGranularity = _libraries['libamdhip64.so'].hipMemGetAllocationGranularity - hipMemGetAllocationGranularity.restype = hipError_t - hipMemGetAllocationGranularity.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_hipMemAllocationProp), hipMemAllocationGranularity_flags] -except AttributeError: - pass -try: - hipMemGetAllocationPropertiesFromHandle = _libraries['libamdhip64.so'].hipMemGetAllocationPropertiesFromHandle - hipMemGetAllocationPropertiesFromHandle.restype = hipError_t - hipMemGetAllocationPropertiesFromHandle.argtypes = [ctypes.POINTER(struct_hipMemAllocationProp), hipMemGenericAllocationHandle_t] -except AttributeError: - pass -try: - hipMemImportFromShareableHandle = _libraries['libamdhip64.so'].hipMemImportFromShareableHandle - hipMemImportFromShareableHandle.restype = hipError_t - hipMemImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), ctypes.POINTER(None), hipMemAllocationHandleType] -except AttributeError: - pass -try: - hipMemMap = _libraries['libamdhip64.so'].hipMemMap - hipMemMap.restype = hipError_t - hipMemMap.argtypes = [ctypes.POINTER(None), size_t, size_t, hipMemGenericAllocationHandle_t, ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemMapArrayAsync = _libraries['libamdhip64.so'].hipMemMapArrayAsync - hipMemMapArrayAsync.restype = hipError_t - hipMemMapArrayAsync.argtypes = [ctypes.POINTER(struct_hipArrayMapInfo), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipMemRelease = _libraries['libamdhip64.so'].hipMemRelease - hipMemRelease.restype = hipError_t - hipMemRelease.argtypes = [hipMemGenericAllocationHandle_t] -except AttributeError: - pass -try: - hipMemRetainAllocationHandle = _libraries['libamdhip64.so'].hipMemRetainAllocationHandle - hipMemRetainAllocationHandle.restype = hipError_t - hipMemRetainAllocationHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemSetAccess = _libraries['libamdhip64.so'].hipMemSetAccess - hipMemSetAccess.restype = hipError_t - hipMemSetAccess.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hipMemAccessDesc), size_t] -except AttributeError: - pass -try: - hipMemUnmap = _libraries['libamdhip64.so'].hipMemUnmap - hipMemUnmap.restype = hipError_t - hipMemUnmap.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipGraphicsMapResources = _libraries['libamdhip64.so'].hipGraphicsMapResources - hipGraphicsMapResources.restype = hipError_t - hipGraphicsMapResources.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(struct__hipGraphicsResource)), hipStream_t] -except AttributeError: - pass -try: - hipGraphicsSubResourceGetMappedArray = _libraries['libamdhip64.so'].hipGraphicsSubResourceGetMappedArray - hipGraphicsSubResourceGetMappedArray.restype = hipError_t - hipGraphicsSubResourceGetMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipGraphicsResource_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphicsResourceGetMappedPointer = _libraries['libamdhip64.so'].hipGraphicsResourceGetMappedPointer - hipGraphicsResourceGetMappedPointer.restype = hipError_t - hipGraphicsResourceGetMappedPointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipGraphicsResource_t] -except AttributeError: - pass -try: - hipGraphicsUnmapResources = _libraries['libamdhip64.so'].hipGraphicsUnmapResources - hipGraphicsUnmapResources.restype = hipError_t - hipGraphicsUnmapResources.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(struct__hipGraphicsResource)), hipStream_t] -except AttributeError: - pass -try: - hipGraphicsUnregisterResource = _libraries['libamdhip64.so'].hipGraphicsUnregisterResource - hipGraphicsUnregisterResource.restype = hipError_t - hipGraphicsUnregisterResource.argtypes = [hipGraphicsResource_t] -except AttributeError: - pass -class struct___hip_surface(Structure): - pass - -try: - hipCreateSurfaceObject = _libraries['libamdhip64.so'].hipCreateSurfaceObject - hipCreateSurfaceObject.restype = hipError_t - hipCreateSurfaceObject.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_surface)), ctypes.POINTER(struct_hipResourceDesc)] -except AttributeError: - pass -hipSurfaceObject_t = ctypes.POINTER(struct___hip_surface) -try: - hipDestroySurfaceObject = _libraries['libamdhip64.so'].hipDestroySurfaceObject - hipDestroySurfaceObject.restype = hipError_t - hipDestroySurfaceObject.argtypes = [hipSurfaceObject_t] -except AttributeError: - pass -try: - hipExtModuleLaunchKernel = _libraries['FIXME_STUB'].hipExtModuleLaunchKernel - hipExtModuleLaunchKernel.restype = hipError_t - hipExtModuleLaunchKernel.argtypes = [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None)), hipEvent_t, hipEvent_t, uint32_t] -except AttributeError: - pass -try: - hipHccModuleLaunchKernel = _libraries['FIXME_STUB'].hipHccModuleLaunchKernel - hipHccModuleLaunchKernel.restype = hipError_t - hipHccModuleLaunchKernel.argtypes = [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None)), hipEvent_t, hipEvent_t] -except AttributeError: - pass - -# values for enumeration 'hiprtcResult' -hiprtcResult__enumvalues = { - 0: 'HIPRTC_SUCCESS', - 1: 'HIPRTC_ERROR_OUT_OF_MEMORY', - 2: 'HIPRTC_ERROR_PROGRAM_CREATION_FAILURE', - 3: 'HIPRTC_ERROR_INVALID_INPUT', - 4: 'HIPRTC_ERROR_INVALID_PROGRAM', - 5: 'HIPRTC_ERROR_INVALID_OPTION', - 6: 'HIPRTC_ERROR_COMPILATION', - 7: 'HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 8: 'HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 9: 'HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 10: 'HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 11: 'HIPRTC_ERROR_INTERNAL_ERROR', - 100: 'HIPRTC_ERROR_LINKING', -} -HIPRTC_SUCCESS = 0 -HIPRTC_ERROR_OUT_OF_MEMORY = 1 -HIPRTC_ERROR_PROGRAM_CREATION_FAILURE = 2 -HIPRTC_ERROR_INVALID_INPUT = 3 -HIPRTC_ERROR_INVALID_PROGRAM = 4 -HIPRTC_ERROR_INVALID_OPTION = 5 -HIPRTC_ERROR_COMPILATION = 6 -HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE = 7 -HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = 8 -HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = 9 -HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID = 10 -HIPRTC_ERROR_INTERNAL_ERROR = 11 -HIPRTC_ERROR_LINKING = 100 -hiprtcResult = ctypes.c_uint32 # enum - -# values for enumeration 'hiprtcJIT_option' -hiprtcJIT_option__enumvalues = { - 0: 'HIPRTC_JIT_MAX_REGISTERS', - 1: 'HIPRTC_JIT_THREADS_PER_BLOCK', - 2: 'HIPRTC_JIT_WALL_TIME', - 3: 'HIPRTC_JIT_INFO_LOG_BUFFER', - 4: 'HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES', - 5: 'HIPRTC_JIT_ERROR_LOG_BUFFER', - 6: 'HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 7: 'HIPRTC_JIT_OPTIMIZATION_LEVEL', - 8: 'HIPRTC_JIT_TARGET_FROM_HIPCONTEXT', - 9: 'HIPRTC_JIT_TARGET', - 10: 'HIPRTC_JIT_FALLBACK_STRATEGY', - 11: 'HIPRTC_JIT_GENERATE_DEBUG_INFO', - 12: 'HIPRTC_JIT_LOG_VERBOSE', - 13: 'HIPRTC_JIT_GENERATE_LINE_INFO', - 14: 'HIPRTC_JIT_CACHE_MODE', - 15: 'HIPRTC_JIT_NEW_SM3X_OPT', - 16: 'HIPRTC_JIT_FAST_COMPILE', - 17: 'HIPRTC_JIT_GLOBAL_SYMBOL_NAMES', - 18: 'HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS', - 19: 'HIPRTC_JIT_GLOBAL_SYMBOL_COUNT', - 20: 'HIPRTC_JIT_LTO', - 21: 'HIPRTC_JIT_FTZ', - 22: 'HIPRTC_JIT_PREC_DIV', - 23: 'HIPRTC_JIT_PREC_SQRT', - 24: 'HIPRTC_JIT_FMA', - 25: 'HIPRTC_JIT_NUM_OPTIONS', - 10000: 'HIPRTC_JIT_IR_TO_ISA_OPT_EXT', - 10001: 'HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT', -} -HIPRTC_JIT_MAX_REGISTERS = 0 -HIPRTC_JIT_THREADS_PER_BLOCK = 1 -HIPRTC_JIT_WALL_TIME = 2 -HIPRTC_JIT_INFO_LOG_BUFFER = 3 -HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES = 4 -HIPRTC_JIT_ERROR_LOG_BUFFER = 5 -HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = 6 -HIPRTC_JIT_OPTIMIZATION_LEVEL = 7 -HIPRTC_JIT_TARGET_FROM_HIPCONTEXT = 8 -HIPRTC_JIT_TARGET = 9 -HIPRTC_JIT_FALLBACK_STRATEGY = 10 -HIPRTC_JIT_GENERATE_DEBUG_INFO = 11 -HIPRTC_JIT_LOG_VERBOSE = 12 -HIPRTC_JIT_GENERATE_LINE_INFO = 13 -HIPRTC_JIT_CACHE_MODE = 14 -HIPRTC_JIT_NEW_SM3X_OPT = 15 -HIPRTC_JIT_FAST_COMPILE = 16 -HIPRTC_JIT_GLOBAL_SYMBOL_NAMES = 17 -HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS = 18 -HIPRTC_JIT_GLOBAL_SYMBOL_COUNT = 19 -HIPRTC_JIT_LTO = 20 -HIPRTC_JIT_FTZ = 21 -HIPRTC_JIT_PREC_DIV = 22 -HIPRTC_JIT_PREC_SQRT = 23 -HIPRTC_JIT_FMA = 24 -HIPRTC_JIT_NUM_OPTIONS = 25 -HIPRTC_JIT_IR_TO_ISA_OPT_EXT = 10000 -HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT = 10001 -hiprtcJIT_option = ctypes.c_uint32 # enum - -# values for enumeration 'hiprtcJITInputType' -hiprtcJITInputType__enumvalues = { - 0: 'HIPRTC_JIT_INPUT_CUBIN', - 1: 'HIPRTC_JIT_INPUT_PTX', - 2: 'HIPRTC_JIT_INPUT_FATBINARY', - 3: 'HIPRTC_JIT_INPUT_OBJECT', - 4: 'HIPRTC_JIT_INPUT_LIBRARY', - 5: 'HIPRTC_JIT_INPUT_NVVM', - 6: 'HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES', - 100: 'HIPRTC_JIT_INPUT_LLVM_BITCODE', - 101: 'HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE', - 102: 'HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE', - 9: 'HIPRTC_JIT_NUM_INPUT_TYPES', -} -HIPRTC_JIT_INPUT_CUBIN = 0 -HIPRTC_JIT_INPUT_PTX = 1 -HIPRTC_JIT_INPUT_FATBINARY = 2 -HIPRTC_JIT_INPUT_OBJECT = 3 -HIPRTC_JIT_INPUT_LIBRARY = 4 -HIPRTC_JIT_INPUT_NVVM = 5 -HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES = 6 -HIPRTC_JIT_INPUT_LLVM_BITCODE = 100 -HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE = 101 -HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE = 102 -HIPRTC_JIT_NUM_INPUT_TYPES = 9 -hiprtcJITInputType = ctypes.c_uint32 # enum -class struct_ihiprtcLinkState(Structure): - pass - -hiprtcLinkState = ctypes.POINTER(struct_ihiprtcLinkState) -try: - hiprtcGetErrorString = _libraries['libamdhip64.so'].hiprtcGetErrorString - hiprtcGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - hiprtcGetErrorString.argtypes = [hiprtcResult] -except AttributeError: - pass -try: - hiprtcVersion = _libraries['libamdhip64.so'].hiprtcVersion - hiprtcVersion.restype = hiprtcResult - hiprtcVersion.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -class struct__hiprtcProgram(Structure): - pass - -hiprtcProgram = ctypes.POINTER(struct__hiprtcProgram) -try: - hiprtcAddNameExpression = _libraries['libamdhip64.so'].hiprtcAddNameExpression - hiprtcAddNameExpression.restype = hiprtcResult - hiprtcAddNameExpression.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcCompileProgram = _libraries['libamdhip64.so'].hiprtcCompileProgram - hiprtcCompileProgram.restype = hiprtcResult - hiprtcCompileProgram.argtypes = [hiprtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcCreateProgram = _libraries['libamdhip64.so'].hiprtcCreateProgram - hiprtcCreateProgram.restype = hiprtcResult - hiprtcCreateProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__hiprtcProgram)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcDestroyProgram = _libraries['libamdhip64.so'].hiprtcDestroyProgram - hiprtcDestroyProgram.restype = hiprtcResult - hiprtcDestroyProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__hiprtcProgram))] -except AttributeError: - pass -try: - hiprtcGetLoweredName = _libraries['libamdhip64.so'].hiprtcGetLoweredName - hiprtcGetLoweredName.restype = hiprtcResult - hiprtcGetLoweredName.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcGetProgramLog = _libraries['libamdhip64.so'].hiprtcGetProgramLog - hiprtcGetProgramLog.restype = hiprtcResult - hiprtcGetProgramLog.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetProgramLogSize = _libraries['libamdhip64.so'].hiprtcGetProgramLogSize - hiprtcGetProgramLogSize.restype = hiprtcResult - hiprtcGetProgramLogSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcGetCode = _libraries['libamdhip64.so'].hiprtcGetCode - hiprtcGetCode.restype = hiprtcResult - hiprtcGetCode.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetCodeSize = _libraries['libamdhip64.so'].hiprtcGetCodeSize - hiprtcGetCodeSize.restype = hiprtcResult - hiprtcGetCodeSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcGetBitcode = _libraries['libamdhip64.so'].hiprtcGetBitcode - hiprtcGetBitcode.restype = hiprtcResult - hiprtcGetBitcode.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetBitcodeSize = _libraries['libamdhip64.so'].hiprtcGetBitcodeSize - hiprtcGetBitcodeSize.restype = hiprtcResult - hiprtcGetBitcodeSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcLinkCreate = _libraries['libamdhip64.so'].hiprtcLinkCreate - hiprtcLinkCreate.restype = hiprtcResult - hiprtcLinkCreate.argtypes = [ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_ihiprtcLinkState))] -except AttributeError: - pass -try: - hiprtcLinkAddFile = _libraries['libamdhip64.so'].hiprtcLinkAddFile - hiprtcLinkAddFile.restype = hiprtcResult - hiprtcLinkAddFile.argtypes = [hiprtcLinkState, hiprtcJITInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hiprtcLinkAddData = _libraries['libamdhip64.so'].hiprtcLinkAddData - hiprtcLinkAddData.restype = hiprtcResult - hiprtcLinkAddData.argtypes = [hiprtcLinkState, hiprtcJITInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hiprtcLinkComplete = _libraries['libamdhip64.so'].hiprtcLinkComplete - hiprtcLinkComplete.restype = hiprtcResult - hiprtcLinkComplete.argtypes = [hiprtcLinkState, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcLinkDestroy = _libraries['libamdhip64.so'].hiprtcLinkDestroy - hiprtcLinkDestroy.restype = hiprtcResult - hiprtcLinkDestroy.argtypes = [hiprtcLinkState] -except AttributeError: - pass -__all__ = \ - ['HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 'HIPRTC_ERROR_COMPILATION', 'HIPRTC_ERROR_INTERNAL_ERROR', - 'HIPRTC_ERROR_INVALID_INPUT', 'HIPRTC_ERROR_INVALID_OPTION', - 'HIPRTC_ERROR_INVALID_PROGRAM', 'HIPRTC_ERROR_LINKING', - 'HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 'HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 'HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 'HIPRTC_ERROR_OUT_OF_MEMORY', - 'HIPRTC_ERROR_PROGRAM_CREATION_FAILURE', 'HIPRTC_JIT_CACHE_MODE', - 'HIPRTC_JIT_ERROR_LOG_BUFFER', - 'HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 'HIPRTC_JIT_FALLBACK_STRATEGY', 'HIPRTC_JIT_FAST_COMPILE', - 'HIPRTC_JIT_FMA', 'HIPRTC_JIT_FTZ', - 'HIPRTC_JIT_GENERATE_DEBUG_INFO', 'HIPRTC_JIT_GENERATE_LINE_INFO', - 'HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS', - 'HIPRTC_JIT_GLOBAL_SYMBOL_COUNT', - 'HIPRTC_JIT_GLOBAL_SYMBOL_NAMES', 'HIPRTC_JIT_INFO_LOG_BUFFER', - 'HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 'HIPRTC_JIT_INPUT_CUBIN', - 'HIPRTC_JIT_INPUT_FATBINARY', 'HIPRTC_JIT_INPUT_LIBRARY', - 'HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE', - 'HIPRTC_JIT_INPUT_LLVM_BITCODE', - 'HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE', 'HIPRTC_JIT_INPUT_NVVM', - 'HIPRTC_JIT_INPUT_OBJECT', 'HIPRTC_JIT_INPUT_PTX', - 'HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT', - 'HIPRTC_JIT_IR_TO_ISA_OPT_EXT', 'HIPRTC_JIT_LOG_VERBOSE', - 'HIPRTC_JIT_LTO', 'HIPRTC_JIT_MAX_REGISTERS', - 'HIPRTC_JIT_NEW_SM3X_OPT', 'HIPRTC_JIT_NUM_INPUT_TYPES', - 'HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES', 'HIPRTC_JIT_NUM_OPTIONS', - 'HIPRTC_JIT_OPTIMIZATION_LEVEL', 'HIPRTC_JIT_PREC_DIV', - 'HIPRTC_JIT_PREC_SQRT', 'HIPRTC_JIT_TARGET', - 'HIPRTC_JIT_TARGET_FROM_HIPCONTEXT', - 'HIPRTC_JIT_THREADS_PER_BLOCK', 'HIPRTC_JIT_WALL_TIME', - 'HIPRTC_SUCCESS', 'HIP_AD_FORMAT_FLOAT', 'HIP_AD_FORMAT_HALF', - 'HIP_AD_FORMAT_SIGNED_INT16', 'HIP_AD_FORMAT_SIGNED_INT32', - 'HIP_AD_FORMAT_SIGNED_INT8', 'HIP_AD_FORMAT_UNSIGNED_INT16', - 'HIP_AD_FORMAT_UNSIGNED_INT32', 'HIP_AD_FORMAT_UNSIGNED_INT8', - 'HIP_ARRAY3D_DESCRIPTOR', 'HIP_ARRAY_DESCRIPTOR', - 'HIP_ERROR_INVALID_VALUE', 'HIP_ERROR_LAUNCH_OUT_OF_RESOURCES', - 'HIP_ERROR_NOT_INITIALIZED', 'HIP_FUNC_ATTRIBUTE_BINARY_VERSION', - 'HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 'HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 'HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 'HIP_FUNC_ATTRIBUTE_MAX', - 'HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 'HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'HIP_FUNC_ATTRIBUTE_NUM_REGS', - 'HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 'HIP_FUNC_ATTRIBUTE_PTX_VERSION', - 'HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', 'HIP_MEMCPY3D', - 'HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 'HIP_POINTER_ATTRIBUTE_BUFFER_ID', - 'HIP_POINTER_ATTRIBUTE_CONTEXT', - 'HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 'HIP_POINTER_ATTRIBUTE_DEVICE_POINTER', - 'HIP_POINTER_ATTRIBUTE_HOST_POINTER', - 'HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 'HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE', - 'HIP_POINTER_ATTRIBUTE_IS_MANAGED', - 'HIP_POINTER_ATTRIBUTE_MAPPED', - 'HIP_POINTER_ATTRIBUTE_MEMORY_TYPE', - 'HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 'HIP_POINTER_ATTRIBUTE_P2P_TOKENS', - 'HIP_POINTER_ATTRIBUTE_RANGE_SIZE', - 'HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 'HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS', 'HIP_RESOURCE_DESC', - 'HIP_RESOURCE_TYPE_ARRAY', 'HIP_RESOURCE_TYPE_LINEAR', - 'HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY', 'HIP_RESOURCE_TYPE_PITCH2D', - 'HIP_RESOURCE_VIEW_DESC', 'HIP_RES_VIEW_FORMAT_FLOAT_1X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_1X32', - 'HIP_RES_VIEW_FORMAT_FLOAT_2X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_2X32', - 'HIP_RES_VIEW_FORMAT_FLOAT_4X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_4X32', 'HIP_RES_VIEW_FORMAT_NONE', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC4', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC5', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC6H', - 'HIP_RES_VIEW_FORMAT_SINT_1X16', 'HIP_RES_VIEW_FORMAT_SINT_1X32', - 'HIP_RES_VIEW_FORMAT_SINT_1X8', 'HIP_RES_VIEW_FORMAT_SINT_2X16', - 'HIP_RES_VIEW_FORMAT_SINT_2X32', 'HIP_RES_VIEW_FORMAT_SINT_2X8', - 'HIP_RES_VIEW_FORMAT_SINT_4X16', 'HIP_RES_VIEW_FORMAT_SINT_4X32', - 'HIP_RES_VIEW_FORMAT_SINT_4X8', 'HIP_RES_VIEW_FORMAT_UINT_1X16', - 'HIP_RES_VIEW_FORMAT_UINT_1X32', 'HIP_RES_VIEW_FORMAT_UINT_1X8', - 'HIP_RES_VIEW_FORMAT_UINT_2X16', 'HIP_RES_VIEW_FORMAT_UINT_2X32', - 'HIP_RES_VIEW_FORMAT_UINT_2X8', 'HIP_RES_VIEW_FORMAT_UINT_4X16', - 'HIP_RES_VIEW_FORMAT_UINT_4X32', 'HIP_RES_VIEW_FORMAT_UINT_4X8', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC1', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC2', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC3', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC4', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC5', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC7', 'HIP_SUCCESS', - 'HIP_TEXTURE_DESC', 'HIP_TR_ADDRESS_MODE_BORDER', - 'HIP_TR_ADDRESS_MODE_CLAMP', 'HIP_TR_ADDRESS_MODE_MIRROR', - 'HIP_TR_ADDRESS_MODE_WRAP', 'HIP_TR_FILTER_MODE_LINEAR', - 'HIP_TR_FILTER_MODE_POINT', 'HIPaddress_mode', - 'HIPaddress_mode__enumvalues', 'HIPaddress_mode_enum', - 'HIPfilter_mode', 'HIPfilter_mode__enumvalues', - 'HIPfilter_mode_enum', 'HIPresourceViewFormat', - 'HIPresourceViewFormat__enumvalues', 'HIPresourceViewFormat_enum', - 'HIPresourcetype', 'HIPresourcetype__enumvalues', - 'HIPresourcetype_enum', '__hipGetPCH', - '__hipPopCallConfiguration', '__hipPushCallConfiguration', - 'c__Ea_HIP_SUCCESS', 'dim3', 'hipAccessPolicyWindow', - 'hipAccessProperty', 'hipAccessPropertyNormal', - 'hipAccessPropertyPersisting', 'hipAccessPropertyStreaming', - 'hipAddressModeBorder', 'hipAddressModeClamp', - 'hipAddressModeMirror', 'hipAddressModeWrap', 'hipApiName', - 'hipArray3DCreate', 'hipArray3DGetDescriptor', 'hipArrayCreate', - 'hipArrayDestroy', 'hipArrayGetDescriptor', 'hipArrayGetInfo', - 'hipArrayMapInfo', 'hipArraySparseSubresourceType', - 'hipArraySparseSubresourceTypeMiptail', - 'hipArraySparseSubresourceTypeSparseLevel', 'hipArray_Format', - 'hipArray_const_t', 'hipArray_t', 'hipBindTexture', - 'hipBindTexture2D', 'hipBindTextureToArray', - 'hipBindTextureToMipmappedArray', 'hipChannelFormatDesc', - 'hipChannelFormatKind', 'hipChannelFormatKindFloat', - 'hipChannelFormatKindNone', 'hipChannelFormatKindSigned', - 'hipChannelFormatKindUnsigned', 'hipChooseDeviceR0600', - 'hipComputeMode', 'hipComputeModeDefault', - 'hipComputeModeExclusive', 'hipComputeModeExclusiveProcess', - 'hipComputeModeProhibited', 'hipConfigureCall', - 'hipCreateSurfaceObject', 'hipCreateTextureObject', - 'hipCtxCreate', 'hipCtxDestroy', 'hipCtxDisablePeerAccess', - 'hipCtxEnablePeerAccess', 'hipCtxGetApiVersion', - 'hipCtxGetCacheConfig', 'hipCtxGetCurrent', 'hipCtxGetDevice', - 'hipCtxGetFlags', 'hipCtxGetSharedMemConfig', 'hipCtxPopCurrent', - 'hipCtxPushCurrent', 'hipCtxSetCacheConfig', 'hipCtxSetCurrent', - 'hipCtxSetSharedMemConfig', 'hipCtxSynchronize', 'hipCtx_t', - 'hipDestroyExternalMemory', 'hipDestroyExternalSemaphore', - 'hipDestroySurfaceObject', 'hipDestroyTextureObject', - 'hipDevP2PAttrAccessSupported', - 'hipDevP2PAttrHipArrayAccessSupported', - 'hipDevP2PAttrNativeAtomicSupported', - 'hipDevP2PAttrPerformanceRank', 'hipDeviceArch_t', - 'hipDeviceAttributeAccessPolicyMaxWindowSize', - 'hipDeviceAttributeAmdSpecificBegin', - 'hipDeviceAttributeAmdSpecificEnd', - 'hipDeviceAttributeAsicRevision', - 'hipDeviceAttributeAsyncEngineCount', - 'hipDeviceAttributeCanMapHostMemory', - 'hipDeviceAttributeCanUseHostPointerForRegisteredMem', - 'hipDeviceAttributeCanUseStreamWaitValue', - 'hipDeviceAttributeClockInstructionRate', - 'hipDeviceAttributeClockRate', - 'hipDeviceAttributeComputeCapabilityMajor', - 'hipDeviceAttributeComputeCapabilityMinor', - 'hipDeviceAttributeComputeMode', - 'hipDeviceAttributeComputePreemptionSupported', - 'hipDeviceAttributeConcurrentKernels', - 'hipDeviceAttributeConcurrentManagedAccess', - 'hipDeviceAttributeCooperativeLaunch', - 'hipDeviceAttributeCooperativeMultiDeviceLaunch', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem', - 'hipDeviceAttributeCudaCompatibleBegin', - 'hipDeviceAttributeCudaCompatibleEnd', - 'hipDeviceAttributeDeviceOverlap', - 'hipDeviceAttributeDirectManagedMemAccessFromHost', - 'hipDeviceAttributeEccEnabled', - 'hipDeviceAttributeFineGrainSupport', - 'hipDeviceAttributeGlobalL1CacheSupported', - 'hipDeviceAttributeHdpMemFlushCntl', - 'hipDeviceAttributeHdpRegFlushCntl', - 'hipDeviceAttributeHostNativeAtomicSupported', - 'hipDeviceAttributeHostRegisterSupported', - 'hipDeviceAttributeImageSupport', 'hipDeviceAttributeIntegrated', - 'hipDeviceAttributeIsLargeBar', - 'hipDeviceAttributeIsMultiGpuBoard', - 'hipDeviceAttributeKernelExecTimeout', - 'hipDeviceAttributeL2CacheSize', - 'hipDeviceAttributeLocalL1CacheSupported', - 'hipDeviceAttributeLuid', 'hipDeviceAttributeLuidDeviceNodeMask', - 'hipDeviceAttributeManagedMemory', - 'hipDeviceAttributeMaxBlockDimX', - 'hipDeviceAttributeMaxBlockDimY', - 'hipDeviceAttributeMaxBlockDimZ', - 'hipDeviceAttributeMaxBlocksPerMultiProcessor', - 'hipDeviceAttributeMaxGridDimX', 'hipDeviceAttributeMaxGridDimY', - 'hipDeviceAttributeMaxGridDimZ', 'hipDeviceAttributeMaxPitch', - 'hipDeviceAttributeMaxRegistersPerBlock', - 'hipDeviceAttributeMaxRegistersPerMultiprocessor', - 'hipDeviceAttributeMaxSharedMemoryPerBlock', - 'hipDeviceAttributeMaxSharedMemoryPerMultiprocessor', - 'hipDeviceAttributeMaxSurface1D', - 'hipDeviceAttributeMaxSurface1DLayered', - 'hipDeviceAttributeMaxSurface2D', - 'hipDeviceAttributeMaxSurface2DLayered', - 'hipDeviceAttributeMaxSurface3D', - 'hipDeviceAttributeMaxSurfaceCubemap', - 'hipDeviceAttributeMaxSurfaceCubemapLayered', - 'hipDeviceAttributeMaxTexture1DLayered', - 'hipDeviceAttributeMaxTexture1DLinear', - 'hipDeviceAttributeMaxTexture1DMipmap', - 'hipDeviceAttributeMaxTexture1DWidth', - 'hipDeviceAttributeMaxTexture2DGather', - 'hipDeviceAttributeMaxTexture2DHeight', - 'hipDeviceAttributeMaxTexture2DLayered', - 'hipDeviceAttributeMaxTexture2DLinear', - 'hipDeviceAttributeMaxTexture2DMipmap', - 'hipDeviceAttributeMaxTexture2DWidth', - 'hipDeviceAttributeMaxTexture3DAlt', - 'hipDeviceAttributeMaxTexture3DDepth', - 'hipDeviceAttributeMaxTexture3DHeight', - 'hipDeviceAttributeMaxTexture3DWidth', - 'hipDeviceAttributeMaxTextureCubemap', - 'hipDeviceAttributeMaxTextureCubemapLayered', - 'hipDeviceAttributeMaxThreadsDim', - 'hipDeviceAttributeMaxThreadsPerBlock', - 'hipDeviceAttributeMaxThreadsPerMultiProcessor', - 'hipDeviceAttributeMemoryBusWidth', - 'hipDeviceAttributeMemoryClockRate', - 'hipDeviceAttributeMemoryPoolsSupported', - 'hipDeviceAttributeMultiGpuBoardGroupID', - 'hipDeviceAttributeMultiprocessorCount', - 'hipDeviceAttributePageableMemoryAccess', - 'hipDeviceAttributePageableMemoryAccessUsesHostPageTables', - 'hipDeviceAttributePciBusId', 'hipDeviceAttributePciDeviceId', - 'hipDeviceAttributePciDomainID', - 'hipDeviceAttributePersistingL2CacheMaxSize', - 'hipDeviceAttributePhysicalMultiProcessorCount', - 'hipDeviceAttributeReservedSharedMemPerBlock', - 'hipDeviceAttributeSharedMemPerBlockOptin', - 'hipDeviceAttributeSharedMemPerMultiprocessor', - 'hipDeviceAttributeSingleToDoublePrecisionPerfRatio', - 'hipDeviceAttributeStreamPrioritiesSupported', - 'hipDeviceAttributeSurfaceAlignment', - 'hipDeviceAttributeTccDriver', - 'hipDeviceAttributeTextureAlignment', - 'hipDeviceAttributeTexturePitchAlignment', - 'hipDeviceAttributeTotalConstantMemory', - 'hipDeviceAttributeTotalGlobalMem', - 'hipDeviceAttributeUnifiedAddressing', - 'hipDeviceAttributeUnused1', 'hipDeviceAttributeUnused2', - 'hipDeviceAttributeUnused3', 'hipDeviceAttributeUnused4', - 'hipDeviceAttributeUnused5', - 'hipDeviceAttributeVendorSpecificBegin', - 'hipDeviceAttributeVirtualMemoryManagementSupported', - 'hipDeviceAttributeWallClockRate', 'hipDeviceAttributeWarpSize', - 'hipDeviceAttribute_t', 'hipDeviceCanAccessPeer', - 'hipDeviceComputeCapability', 'hipDeviceDisablePeerAccess', - 'hipDeviceEnablePeerAccess', 'hipDeviceGet', - 'hipDeviceGetAttribute', 'hipDeviceGetByPCIBusId', - 'hipDeviceGetCacheConfig', 'hipDeviceGetDefaultMemPool', - 'hipDeviceGetGraphMemAttribute', 'hipDeviceGetLimit', - 'hipDeviceGetMemPool', 'hipDeviceGetName', - 'hipDeviceGetP2PAttribute', 'hipDeviceGetPCIBusId', - 'hipDeviceGetSharedMemConfig', 'hipDeviceGetStreamPriorityRange', - 'hipDeviceGetUuid', 'hipDeviceGraphMemTrim', 'hipDeviceP2PAttr', - 'hipDevicePrimaryCtxGetState', 'hipDevicePrimaryCtxRelease', - 'hipDevicePrimaryCtxReset', 'hipDevicePrimaryCtxRetain', - 'hipDevicePrimaryCtxSetFlags', 'hipDeviceProp_tR0600', - 'hipDeviceReset', 'hipDeviceSetCacheConfig', - 'hipDeviceSetGraphMemAttribute', 'hipDeviceSetLimit', - 'hipDeviceSetMemPool', 'hipDeviceSetSharedMemConfig', - 'hipDeviceSynchronize', 'hipDeviceTotalMem', 'hipDevice_t', - 'hipDeviceptr_t', 'hipDriverGetVersion', 'hipDrvGetErrorName', - 'hipDrvGetErrorString', 'hipDrvGraphAddMemcpyNode', - 'hipDrvMemcpy2DUnaligned', 'hipDrvMemcpy3D', - 'hipDrvMemcpy3DAsync', 'hipDrvPointerGetAttributes', - 'hipErrorAlreadyAcquired', 'hipErrorAlreadyMapped', - 'hipErrorArrayIsMapped', 'hipErrorAssert', - 'hipErrorCapturedEvent', 'hipErrorContextAlreadyCurrent', - 'hipErrorContextAlreadyInUse', 'hipErrorContextIsDestroyed', - 'hipErrorCooperativeLaunchTooLarge', 'hipErrorDeinitialized', - 'hipErrorECCNotCorrectable', 'hipErrorFileNotFound', - 'hipErrorGraphExecUpdateFailure', - 'hipErrorHostMemoryAlreadyRegistered', - 'hipErrorHostMemoryNotRegistered', 'hipErrorIllegalAddress', - 'hipErrorIllegalState', 'hipErrorInitializationError', - 'hipErrorInsufficientDriver', 'hipErrorInvalidConfiguration', - 'hipErrorInvalidContext', 'hipErrorInvalidDevice', - 'hipErrorInvalidDeviceFunction', 'hipErrorInvalidDevicePointer', - 'hipErrorInvalidGraphicsContext', 'hipErrorInvalidHandle', - 'hipErrorInvalidImage', 'hipErrorInvalidKernelFile', - 'hipErrorInvalidMemcpyDirection', 'hipErrorInvalidPitchValue', - 'hipErrorInvalidResourceHandle', 'hipErrorInvalidSource', - 'hipErrorInvalidSymbol', 'hipErrorInvalidValue', - 'hipErrorLaunchFailure', 'hipErrorLaunchOutOfResources', - 'hipErrorLaunchTimeOut', 'hipErrorMapBufferObjectFailed', - 'hipErrorMapFailed', 'hipErrorMemoryAllocation', - 'hipErrorMissingConfiguration', 'hipErrorNoBinaryForGpu', - 'hipErrorNoDevice', 'hipErrorNotFound', 'hipErrorNotInitialized', - 'hipErrorNotMapped', 'hipErrorNotMappedAsArray', - 'hipErrorNotMappedAsPointer', 'hipErrorNotReady', - 'hipErrorNotSupported', 'hipErrorOperatingSystem', - 'hipErrorOutOfMemory', 'hipErrorPeerAccessAlreadyEnabled', - 'hipErrorPeerAccessNotEnabled', 'hipErrorPeerAccessUnsupported', - 'hipErrorPriorLaunchFailure', 'hipErrorProfilerAlreadyStarted', - 'hipErrorProfilerAlreadyStopped', 'hipErrorProfilerDisabled', - 'hipErrorProfilerNotInitialized', 'hipErrorRuntimeMemory', - 'hipErrorRuntimeOther', 'hipErrorSetOnActiveProcess', - 'hipErrorSharedObjectInitFailed', - 'hipErrorSharedObjectSymbolNotFound', - 'hipErrorStreamCaptureImplicit', - 'hipErrorStreamCaptureInvalidated', - 'hipErrorStreamCaptureIsolation', 'hipErrorStreamCaptureMerge', - 'hipErrorStreamCaptureUnjoined', 'hipErrorStreamCaptureUnmatched', - 'hipErrorStreamCaptureUnsupported', - 'hipErrorStreamCaptureWrongThread', 'hipErrorTbd', - 'hipErrorUnknown', 'hipErrorUnmapFailed', - 'hipErrorUnsupportedLimit', 'hipError_t', 'hipEventCreate', - 'hipEventCreateWithFlags', 'hipEventDestroy', - 'hipEventElapsedTime', 'hipEventQuery', 'hipEventRecord', - 'hipEventSynchronize', 'hipEvent_t', 'hipExtGetLastError', - 'hipExtGetLinkTypeAndHopCount', 'hipExtLaunchKernel', - 'hipExtLaunchMultiKernelMultiDevice', 'hipExtMallocWithFlags', - 'hipExtModuleLaunchKernel', 'hipExtStreamCreateWithCUMask', - 'hipExtStreamGetCUMask', 'hipExtent', - 'hipExternalMemoryBufferDesc', 'hipExternalMemoryGetMappedBuffer', - 'hipExternalMemoryGetMappedMipmappedArray', - 'hipExternalMemoryHandleDesc', 'hipExternalMemoryHandleType', - 'hipExternalMemoryHandleTypeD3D11Resource', - 'hipExternalMemoryHandleTypeD3D11ResourceKmt', - 'hipExternalMemoryHandleTypeD3D12Heap', - 'hipExternalMemoryHandleTypeD3D12Resource', - 'hipExternalMemoryHandleTypeNvSciBuf', - 'hipExternalMemoryHandleTypeOpaqueFd', - 'hipExternalMemoryHandleTypeOpaqueWin32', - 'hipExternalMemoryHandleTypeOpaqueWin32Kmt', - 'hipExternalMemoryHandleType__enumvalues', - 'hipExternalMemoryHandleType_enum', - 'hipExternalMemoryMipmappedArrayDesc', 'hipExternalMemory_t', - 'hipExternalSemaphoreHandleDesc', - 'hipExternalSemaphoreHandleType', - 'hipExternalSemaphoreHandleTypeD3D11Fence', - 'hipExternalSemaphoreHandleTypeD3D12Fence', - 'hipExternalSemaphoreHandleTypeKeyedMutex', - 'hipExternalSemaphoreHandleTypeKeyedMutexKmt', - 'hipExternalSemaphoreHandleTypeNvSciSync', - 'hipExternalSemaphoreHandleTypeOpaqueFd', - 'hipExternalSemaphoreHandleTypeOpaqueWin32', - 'hipExternalSemaphoreHandleTypeOpaqueWin32Kmt', - 'hipExternalSemaphoreHandleTypeTimelineSemaphoreFd', - 'hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32', - 'hipExternalSemaphoreHandleType__enumvalues', - 'hipExternalSemaphoreHandleType_enum', - 'hipExternalSemaphoreSignalNodeParams', - 'hipExternalSemaphoreSignalParams', - 'hipExternalSemaphoreWaitNodeParams', - 'hipExternalSemaphoreWaitParams', 'hipExternalSemaphore_t', - 'hipFilterModeLinear', 'hipFilterModePoint', 'hipFree', - 'hipFreeArray', 'hipFreeAsync', 'hipFreeHost', - 'hipFreeMipmappedArray', 'hipFuncAttribute', - 'hipFuncAttributeMax', - 'hipFuncAttributeMaxDynamicSharedMemorySize', - 'hipFuncAttributePreferredSharedMemoryCarveout', - 'hipFuncAttributes', 'hipFuncCachePreferEqual', - 'hipFuncCachePreferL1', 'hipFuncCachePreferNone', - 'hipFuncCachePreferShared', 'hipFuncCache_t', - 'hipFuncGetAttribute', 'hipFuncGetAttributes', - 'hipFuncSetAttribute', 'hipFuncSetCacheConfig', - 'hipFuncSetSharedMemConfig', 'hipFunctionLaunchParams', - 'hipFunction_attribute', 'hipFunction_t', 'hipGetChannelDesc', - 'hipGetDevice', 'hipGetDeviceCount', 'hipGetDeviceFlags', - 'hipGetDevicePropertiesR0600', 'hipGetErrorName', - 'hipGetErrorString', 'hipGetLastError', - 'hipGetMipmappedArrayLevel', 'hipGetStreamDeviceId', - 'hipGetSymbolAddress', 'hipGetSymbolSize', - 'hipGetTextureAlignmentOffset', 'hipGetTextureObjectResourceDesc', - 'hipGetTextureObjectResourceViewDesc', - 'hipGetTextureObjectTextureDesc', 'hipGetTextureReference', - 'hipGraphAddChildGraphNode', 'hipGraphAddDependencies', - 'hipGraphAddEmptyNode', 'hipGraphAddEventRecordNode', - 'hipGraphAddEventWaitNode', 'hipGraphAddHostNode', - 'hipGraphAddKernelNode', 'hipGraphAddMemAllocNode', - 'hipGraphAddMemFreeNode', 'hipGraphAddMemcpyNode', - 'hipGraphAddMemcpyNode1D', 'hipGraphAddMemcpyNodeFromSymbol', - 'hipGraphAddMemcpyNodeToSymbol', 'hipGraphAddMemsetNode', - 'hipGraphChildGraphNodeGetGraph', 'hipGraphClone', - 'hipGraphCreate', 'hipGraphDebugDotFlags', - 'hipGraphDebugDotFlagsEventNodeParams', - 'hipGraphDebugDotFlagsExtSemasSignalNodeParams', - 'hipGraphDebugDotFlagsExtSemasWaitNodeParams', - 'hipGraphDebugDotFlagsHandles', - 'hipGraphDebugDotFlagsHostNodeParams', - 'hipGraphDebugDotFlagsKernelNodeAttributes', - 'hipGraphDebugDotFlagsKernelNodeParams', - 'hipGraphDebugDotFlagsMemcpyNodeParams', - 'hipGraphDebugDotFlagsMemsetNodeParams', - 'hipGraphDebugDotFlagsVerbose', 'hipGraphDebugDotPrint', - 'hipGraphDestroy', 'hipGraphDestroyNode', - 'hipGraphEventRecordNodeGetEvent', - 'hipGraphEventRecordNodeSetEvent', - 'hipGraphEventWaitNodeGetEvent', 'hipGraphEventWaitNodeSetEvent', - 'hipGraphExecChildGraphNodeSetParams', 'hipGraphExecDestroy', - 'hipGraphExecEventRecordNodeSetEvent', - 'hipGraphExecEventWaitNodeSetEvent', - 'hipGraphExecHostNodeSetParams', - 'hipGraphExecKernelNodeSetParams', - 'hipGraphExecMemcpyNodeSetParams', - 'hipGraphExecMemcpyNodeSetParams1D', - 'hipGraphExecMemcpyNodeSetParamsFromSymbol', - 'hipGraphExecMemcpyNodeSetParamsToSymbol', - 'hipGraphExecMemsetNodeSetParams', 'hipGraphExecUpdate', - 'hipGraphExecUpdateError', - 'hipGraphExecUpdateErrorFunctionChanged', - 'hipGraphExecUpdateErrorNodeTypeChanged', - 'hipGraphExecUpdateErrorNotSupported', - 'hipGraphExecUpdateErrorParametersChanged', - 'hipGraphExecUpdateErrorTopologyChanged', - 'hipGraphExecUpdateErrorUnsupportedFunctionChange', - 'hipGraphExecUpdateResult', 'hipGraphExecUpdateSuccess', - 'hipGraphExec_t', 'hipGraphGetEdges', 'hipGraphGetNodes', - 'hipGraphGetRootNodes', 'hipGraphHostNodeGetParams', - 'hipGraphHostNodeSetParams', 'hipGraphInstantiate', - 'hipGraphInstantiateFlagAutoFreeOnLaunch', - 'hipGraphInstantiateFlagDeviceLaunch', - 'hipGraphInstantiateFlagUpload', - 'hipGraphInstantiateFlagUseNodePriority', - 'hipGraphInstantiateFlags', 'hipGraphInstantiateWithFlags', - 'hipGraphKernelNodeCopyAttributes', - 'hipGraphKernelNodeGetAttribute', 'hipGraphKernelNodeGetParams', - 'hipGraphKernelNodeSetAttribute', 'hipGraphKernelNodeSetParams', - 'hipGraphLaunch', 'hipGraphMemAllocNodeGetParams', - 'hipGraphMemAttrReservedMemCurrent', - 'hipGraphMemAttrReservedMemHigh', 'hipGraphMemAttrUsedMemCurrent', - 'hipGraphMemAttrUsedMemHigh', 'hipGraphMemAttributeType', - 'hipGraphMemFreeNodeGetParams', 'hipGraphMemcpyNodeGetParams', - 'hipGraphMemcpyNodeSetParams', 'hipGraphMemcpyNodeSetParams1D', - 'hipGraphMemcpyNodeSetParamsFromSymbol', - 'hipGraphMemcpyNodeSetParamsToSymbol', - 'hipGraphMemsetNodeGetParams', 'hipGraphMemsetNodeSetParams', - 'hipGraphNodeFindInClone', 'hipGraphNodeGetDependencies', - 'hipGraphNodeGetDependentNodes', 'hipGraphNodeGetEnabled', - 'hipGraphNodeGetType', 'hipGraphNodeSetEnabled', - 'hipGraphNodeType', 'hipGraphNodeTypeCount', - 'hipGraphNodeTypeEmpty', 'hipGraphNodeTypeEventRecord', - 'hipGraphNodeTypeExtSemaphoreSignal', - 'hipGraphNodeTypeExtSemaphoreWait', 'hipGraphNodeTypeGraph', - 'hipGraphNodeTypeHost', 'hipGraphNodeTypeKernel', - 'hipGraphNodeTypeMemAlloc', 'hipGraphNodeTypeMemFree', - 'hipGraphNodeTypeMemcpy', 'hipGraphNodeTypeMemcpyFromSymbol', - 'hipGraphNodeTypeMemcpyToSymbol', 'hipGraphNodeTypeMemset', - 'hipGraphNodeTypeWaitEvent', 'hipGraphNode_t', - 'hipGraphReleaseUserObject', 'hipGraphRemoveDependencies', - 'hipGraphRetainUserObject', 'hipGraphUpload', - 'hipGraphUserObjectMove', 'hipGraph_t', 'hipGraphicsMapResources', - 'hipGraphicsRegisterFlags', 'hipGraphicsRegisterFlagsNone', - 'hipGraphicsRegisterFlagsReadOnly', - 'hipGraphicsRegisterFlagsSurfaceLoadStore', - 'hipGraphicsRegisterFlagsTextureGather', - 'hipGraphicsRegisterFlagsWriteDiscard', 'hipGraphicsResource', - 'hipGraphicsResourceGetMappedPointer', 'hipGraphicsResource_t', - 'hipGraphicsSubResourceGetMappedArray', - 'hipGraphicsUnmapResources', 'hipGraphicsUnregisterResource', - 'hipHccModuleLaunchKernel', 'hipHostAlloc', 'hipHostFn_t', - 'hipHostFree', 'hipHostGetDevicePointer', 'hipHostGetFlags', - 'hipHostMalloc', 'hipHostNodeParams', 'hipHostRegister', - 'hipHostUnregister', 'hipImportExternalMemory', - 'hipImportExternalSemaphore', 'hipInit', 'hipIpcCloseMemHandle', - 'hipIpcEventHandle_t', 'hipIpcGetEventHandle', - 'hipIpcGetMemHandle', 'hipIpcMemHandle_t', - 'hipIpcOpenEventHandle', 'hipIpcOpenMemHandle', 'hipJitOption', - 'hipJitOptionCacheMode', 'hipJitOptionErrorLogBuffer', - 'hipJitOptionErrorLogBufferSizeBytes', - 'hipJitOptionFallbackStrategy', 'hipJitOptionFastCompile', - 'hipJitOptionGenerateDebugInfo', 'hipJitOptionGenerateLineInfo', - 'hipJitOptionInfoLogBuffer', 'hipJitOptionInfoLogBufferSizeBytes', - 'hipJitOptionLogVerbose', 'hipJitOptionMaxRegisters', - 'hipJitOptionNumOptions', 'hipJitOptionOptimizationLevel', - 'hipJitOptionSm3xOpt', 'hipJitOptionTarget', - 'hipJitOptionTargetFromContext', 'hipJitOptionThreadsPerBlock', - 'hipJitOptionWallTime', 'hipKernelNameRef', - 'hipKernelNameRefByPtr', 'hipKernelNodeAttrID', - 'hipKernelNodeAttrValue', - 'hipKernelNodeAttributeAccessPolicyWindow', - 'hipKernelNodeAttributeCooperative', 'hipKernelNodeParams', - 'hipLaunchByPtr', 'hipLaunchCooperativeKernel', - 'hipLaunchCooperativeKernelMultiDevice', 'hipLaunchHostFunc', - 'hipLaunchKernel', 'hipLaunchParams', 'hipLimitMallocHeapSize', - 'hipLimitPrintfFifoSize', 'hipLimitRange', 'hipLimitStackSize', - 'hipLimit_t', 'hipMalloc', 'hipMalloc3D', 'hipMalloc3DArray', - 'hipMallocArray', 'hipMallocAsync', 'hipMallocFromPoolAsync', - 'hipMallocHost', 'hipMallocManaged', 'hipMallocMipmappedArray', - 'hipMallocPitch', 'hipMemAccessDesc', 'hipMemAccessFlags', - 'hipMemAccessFlagsProtNone', 'hipMemAccessFlagsProtRead', - 'hipMemAccessFlagsProtReadWrite', 'hipMemAddressFree', - 'hipMemAddressReserve', 'hipMemAdvise', - 'hipMemAdviseSetAccessedBy', 'hipMemAdviseSetCoarseGrain', - 'hipMemAdviseSetPreferredLocation', 'hipMemAdviseSetReadMostly', - 'hipMemAdviseUnsetAccessedBy', 'hipMemAdviseUnsetCoarseGrain', - 'hipMemAdviseUnsetPreferredLocation', - 'hipMemAdviseUnsetReadMostly', 'hipMemAllocHost', - 'hipMemAllocNodeParams', 'hipMemAllocPitch', - 'hipMemAllocationGranularityMinimum', - 'hipMemAllocationGranularityRecommended', - 'hipMemAllocationGranularity_flags', 'hipMemAllocationHandleType', - 'hipMemAllocationProp', 'hipMemAllocationType', - 'hipMemAllocationTypeInvalid', 'hipMemAllocationTypeMax', - 'hipMemAllocationTypePinned', 'hipMemCreate', - 'hipMemExportToShareableHandle', - 'hipMemGenericAllocationHandle_t', 'hipMemGetAccess', - 'hipMemGetAddressRange', 'hipMemGetAllocationGranularity', - 'hipMemGetAllocationPropertiesFromHandle', 'hipMemGetInfo', - 'hipMemHandleType', 'hipMemHandleTypeGeneric', - 'hipMemHandleTypeNone', 'hipMemHandleTypePosixFileDescriptor', - 'hipMemHandleTypeWin32', 'hipMemHandleTypeWin32Kmt', - 'hipMemImportFromShareableHandle', 'hipMemLocation', - 'hipMemLocationType', 'hipMemLocationTypeDevice', - 'hipMemLocationTypeInvalid', 'hipMemMap', 'hipMemMapArrayAsync', - 'hipMemOperationType', 'hipMemOperationTypeMap', - 'hipMemOperationTypeUnmap', 'hipMemPoolAttr', - 'hipMemPoolAttrReleaseThreshold', - 'hipMemPoolAttrReservedMemCurrent', - 'hipMemPoolAttrReservedMemHigh', 'hipMemPoolAttrUsedMemCurrent', - 'hipMemPoolAttrUsedMemHigh', 'hipMemPoolCreate', - 'hipMemPoolDestroy', 'hipMemPoolExportPointer', - 'hipMemPoolExportToShareableHandle', 'hipMemPoolGetAccess', - 'hipMemPoolGetAttribute', 'hipMemPoolImportFromShareableHandle', - 'hipMemPoolImportPointer', 'hipMemPoolProps', - 'hipMemPoolPtrExportData', - 'hipMemPoolReuseAllowInternalDependencies', - 'hipMemPoolReuseAllowOpportunistic', - 'hipMemPoolReuseFollowEventDependencies', 'hipMemPoolSetAccess', - 'hipMemPoolSetAttribute', 'hipMemPoolTrimTo', 'hipMemPool_t', - 'hipMemPrefetchAsync', 'hipMemPtrGetInfo', 'hipMemRangeAttribute', - 'hipMemRangeAttributeAccessedBy', - 'hipMemRangeAttributeCoherencyMode', - 'hipMemRangeAttributeLastPrefetchLocation', - 'hipMemRangeAttributePreferredLocation', - 'hipMemRangeAttributeReadMostly', 'hipMemRangeCoherencyMode', - 'hipMemRangeCoherencyModeCoarseGrain', - 'hipMemRangeCoherencyModeFineGrain', - 'hipMemRangeCoherencyModeIndeterminate', - 'hipMemRangeGetAttribute', 'hipMemRangeGetAttributes', - 'hipMemRelease', 'hipMemRetainAllocationHandle', - 'hipMemSetAccess', 'hipMemUnmap', 'hipMemcpy', 'hipMemcpy2D', - 'hipMemcpy2DAsync', 'hipMemcpy2DFromArray', - 'hipMemcpy2DFromArrayAsync', 'hipMemcpy2DToArray', - 'hipMemcpy2DToArrayAsync', 'hipMemcpy3D', 'hipMemcpy3DAsync', - 'hipMemcpy3DParms', 'hipMemcpyAsync', 'hipMemcpyAtoH', - 'hipMemcpyDefault', 'hipMemcpyDeviceToDevice', - 'hipMemcpyDeviceToHost', 'hipMemcpyDtoD', 'hipMemcpyDtoDAsync', - 'hipMemcpyDtoH', 'hipMemcpyDtoHAsync', 'hipMemcpyFromArray', - 'hipMemcpyFromSymbol', 'hipMemcpyFromSymbolAsync', - 'hipMemcpyHostToDevice', 'hipMemcpyHostToHost', 'hipMemcpyHtoA', - 'hipMemcpyHtoD', 'hipMemcpyHtoDAsync', 'hipMemcpyKind', - 'hipMemcpyParam2D', 'hipMemcpyParam2DAsync', 'hipMemcpyPeer', - 'hipMemcpyPeerAsync', 'hipMemcpyToArray', 'hipMemcpyToSymbol', - 'hipMemcpyToSymbolAsync', 'hipMemcpyWithStream', - 'hipMemoryAdvise', 'hipMemoryType', 'hipMemoryTypeArray', - 'hipMemoryTypeDevice', 'hipMemoryTypeHost', - 'hipMemoryTypeManaged', 'hipMemoryTypeUnified', - 'hipMemoryTypeUnregistered', 'hipMemset', 'hipMemset2D', - 'hipMemset2DAsync', 'hipMemset3D', 'hipMemset3DAsync', - 'hipMemsetAsync', 'hipMemsetD16', 'hipMemsetD16Async', - 'hipMemsetD32', 'hipMemsetD32Async', 'hipMemsetD8', - 'hipMemsetD8Async', 'hipMemsetParams', 'hipMipmappedArray', - 'hipMipmappedArrayCreate', 'hipMipmappedArrayDestroy', - 'hipMipmappedArrayGetLevel', 'hipMipmappedArray_const_t', - 'hipMipmappedArray_t', 'hipModuleGetFunction', - 'hipModuleGetGlobal', 'hipModuleGetTexRef', - 'hipModuleLaunchCooperativeKernel', - 'hipModuleLaunchCooperativeKernelMultiDevice', - 'hipModuleLaunchKernel', 'hipModuleLoad', 'hipModuleLoadData', - 'hipModuleLoadDataEx', - 'hipModuleOccupancyMaxActiveBlocksPerMultiprocessor', - 'hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'hipModuleOccupancyMaxPotentialBlockSize', - 'hipModuleOccupancyMaxPotentialBlockSizeWithFlags', - 'hipModuleUnload', 'hipModule_t', - 'hipOccupancyMaxActiveBlocksPerMultiprocessor', - 'hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'hipOccupancyMaxPotentialBlockSize', 'hipPeekAtLastError', - 'hipPitchedPtr', 'hipPointerAttribute_t', - 'hipPointerGetAttribute', 'hipPointerGetAttributes', - 'hipPointerSetAttribute', 'hipPointer_attribute', 'hipPos', - 'hipProfilerStart', 'hipProfilerStop', 'hipReadModeElementType', - 'hipReadModeNormalizedFloat', 'hipResViewFormatFloat1', - 'hipResViewFormatFloat2', 'hipResViewFormatFloat4', - 'hipResViewFormatHalf1', 'hipResViewFormatHalf2', - 'hipResViewFormatHalf4', 'hipResViewFormatNone', - 'hipResViewFormatSignedBlockCompressed4', - 'hipResViewFormatSignedBlockCompressed5', - 'hipResViewFormatSignedBlockCompressed6H', - 'hipResViewFormatSignedChar1', 'hipResViewFormatSignedChar2', - 'hipResViewFormatSignedChar4', 'hipResViewFormatSignedInt1', - 'hipResViewFormatSignedInt2', 'hipResViewFormatSignedInt4', - 'hipResViewFormatSignedShort1', 'hipResViewFormatSignedShort2', - 'hipResViewFormatSignedShort4', - 'hipResViewFormatUnsignedBlockCompressed1', - 'hipResViewFormatUnsignedBlockCompressed2', - 'hipResViewFormatUnsignedBlockCompressed3', - 'hipResViewFormatUnsignedBlockCompressed4', - 'hipResViewFormatUnsignedBlockCompressed5', - 'hipResViewFormatUnsignedBlockCompressed6H', - 'hipResViewFormatUnsignedBlockCompressed7', - 'hipResViewFormatUnsignedChar1', 'hipResViewFormatUnsignedChar2', - 'hipResViewFormatUnsignedChar4', 'hipResViewFormatUnsignedInt1', - 'hipResViewFormatUnsignedInt2', 'hipResViewFormatUnsignedInt4', - 'hipResViewFormatUnsignedShort1', - 'hipResViewFormatUnsignedShort2', - 'hipResViewFormatUnsignedShort4', 'hipResourceDesc', - 'hipResourceType', 'hipResourceTypeArray', - 'hipResourceTypeLinear', 'hipResourceTypeMipmappedArray', - 'hipResourceTypePitch2D', 'hipResourceViewFormat', - 'hipResourcetype', 'hipResourcetype__enumvalues', - 'hipRuntimeGetVersion', 'hipSetDevice', 'hipSetDeviceFlags', - 'hipSetupArgument', 'hipSharedMemBankSizeDefault', - 'hipSharedMemBankSizeEightByte', 'hipSharedMemBankSizeFourByte', - 'hipSharedMemConfig', 'hipSignalExternalSemaphoresAsync', - 'hipStreamAddCallback', 'hipStreamAddCaptureDependencies', - 'hipStreamAttachMemAsync', 'hipStreamBeginCapture', - 'hipStreamCallback_t', 'hipStreamCaptureMode', - 'hipStreamCaptureModeGlobal', 'hipStreamCaptureModeRelaxed', - 'hipStreamCaptureModeThreadLocal', 'hipStreamCaptureStatus', - 'hipStreamCaptureStatusActive', - 'hipStreamCaptureStatusInvalidated', 'hipStreamCaptureStatusNone', - 'hipStreamCreate', 'hipStreamCreateWithFlags', - 'hipStreamCreateWithPriority', 'hipStreamDestroy', - 'hipStreamEndCapture', 'hipStreamGetCaptureInfo', - 'hipStreamGetCaptureInfo_v2', 'hipStreamGetDevice', - 'hipStreamGetFlags', 'hipStreamGetPriority', - 'hipStreamIsCapturing', 'hipStreamQuery', - 'hipStreamSetCaptureDependencies', 'hipStreamSynchronize', - 'hipStreamUpdateCaptureDependencies', - 'hipStreamUpdateCaptureDependenciesFlags', 'hipStreamWaitEvent', - 'hipStreamWaitValue32', 'hipStreamWaitValue64', - 'hipStreamWriteValue32', 'hipStreamWriteValue64', 'hipStream_t', - 'hipSuccess', 'hipSurfaceObject_t', 'hipTexObjectCreate', - 'hipTexObjectDestroy', 'hipTexObjectGetResourceDesc', - 'hipTexObjectGetResourceViewDesc', 'hipTexObjectGetTextureDesc', - 'hipTexRefGetAddress', 'hipTexRefGetAddressMode', - 'hipTexRefGetFilterMode', 'hipTexRefGetFlags', - 'hipTexRefGetFormat', 'hipTexRefGetMaxAnisotropy', - 'hipTexRefGetMipMappedArray', 'hipTexRefGetMipmapFilterMode', - 'hipTexRefGetMipmapLevelBias', 'hipTexRefGetMipmapLevelClamp', - 'hipTexRefSetAddress', 'hipTexRefSetAddress2D', - 'hipTexRefSetAddressMode', 'hipTexRefSetArray', - 'hipTexRefSetBorderColor', 'hipTexRefSetFilterMode', - 'hipTexRefSetFlags', 'hipTexRefSetFormat', - 'hipTexRefSetMaxAnisotropy', 'hipTexRefSetMipmapFilterMode', - 'hipTexRefSetMipmapLevelBias', 'hipTexRefSetMipmapLevelClamp', - 'hipTexRefSetMipmappedArray', 'hipTextureAddressMode', - 'hipTextureFilterMode', 'hipTextureObject_t', - 'hipTextureReadMode', 'hipThreadExchangeStreamCaptureMode', - 'hipUUID', 'hipUnbindTexture', 'hipUserObjectCreate', - 'hipUserObjectFlags', 'hipUserObjectNoDestructorSync', - 'hipUserObjectRelease', 'hipUserObjectRetain', - 'hipUserObjectRetainFlags', 'hipUserObject_t', - 'hipWaitExternalSemaphoresAsync', 'hip_Memcpy2D', 'hip_init', - 'hipmipmappedArray', 'hiprtcAddNameExpression', - 'hiprtcCompileProgram', 'hiprtcCreateProgram', - 'hiprtcDestroyProgram', 'hiprtcGetBitcode', - 'hiprtcGetBitcodeSize', 'hiprtcGetCode', 'hiprtcGetCodeSize', - 'hiprtcGetErrorString', 'hiprtcGetLoweredName', - 'hiprtcGetProgramLog', 'hiprtcGetProgramLogSize', - 'hiprtcJITInputType', 'hiprtcJIT_option', 'hiprtcLinkAddData', - 'hiprtcLinkAddFile', 'hiprtcLinkComplete', 'hiprtcLinkCreate', - 'hiprtcLinkDestroy', 'hiprtcLinkState', 'hiprtcProgram', - 'hiprtcResult', 'hiprtcVersion', 'make_hipExtent', - 'make_hipPitchedPtr', 'make_hipPos', 'size_t', - 'struct_HIP_ARRAY3D_DESCRIPTOR', 'struct_HIP_ARRAY_DESCRIPTOR', - 'struct_HIP_MEMCPY3D', 'struct_HIP_RESOURCE_DESC_st', - 'struct_HIP_RESOURCE_DESC_st_0_array', - 'struct_HIP_RESOURCE_DESC_st_0_linear', - 'struct_HIP_RESOURCE_DESC_st_0_mipmap', - 'struct_HIP_RESOURCE_DESC_st_0_pitch2D', - 'struct_HIP_RESOURCE_DESC_st_0_reserved', - 'struct_HIP_RESOURCE_VIEW_DESC_st', 'struct_HIP_TEXTURE_DESC_st', - 'struct___hip_surface', 'struct___hip_texture', - 'struct__hipGraphicsResource', 'struct__hiprtcProgram', - 'struct_c__SA_hipDeviceArch_t', 'struct_dim3', - 'struct_hipAccessPolicyWindow', 'struct_hipArray', - 'struct_hipArrayMapInfo', 'struct_hipArrayMapInfo_1_miptail', - 'struct_hipArrayMapInfo_1_sparseLevel', - 'struct_hipChannelFormatDesc', 'struct_hipDeviceProp_tR0600', - 'struct_hipExtent', 'struct_hipExternalMemoryBufferDesc_st', - 'struct_hipExternalMemoryHandleDesc_st', - 'struct_hipExternalMemoryHandleDesc_st_0_win32', - 'struct_hipExternalMemoryMipmappedArrayDesc_st', - 'struct_hipExternalSemaphoreHandleDesc_st', - 'struct_hipExternalSemaphoreHandleDesc_st_0_win32', - 'struct_hipExternalSemaphoreSignalNodeParams', - 'struct_hipExternalSemaphoreSignalParams_st', - 'struct_hipExternalSemaphoreSignalParams_st_0_fence', - 'struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex', - 'struct_hipExternalSemaphoreSignalParams_st_params', - 'struct_hipExternalSemaphoreWaitNodeParams', - 'struct_hipExternalSemaphoreWaitParams_st', - 'struct_hipExternalSemaphoreWaitParams_st_0_fence', - 'struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex', - 'struct_hipExternalSemaphoreWaitParams_st_params', - 'struct_hipFuncAttributes', 'struct_hipFunctionLaunchParams_t', - 'struct_hipGraphExec', 'struct_hipGraphNode', - 'struct_hipHostNodeParams', 'struct_hipIpcEventHandle_st', - 'struct_hipIpcMemHandle_st', 'struct_hipKernelNodeParams', - 'struct_hipLaunchParams_t', 'struct_hipMemAccessDesc', - 'struct_hipMemAllocNodeParams', 'struct_hipMemAllocationProp', - 'struct_hipMemAllocationProp_allocFlags', 'struct_hipMemLocation', - 'struct_hipMemPoolProps', 'struct_hipMemPoolPtrExportData', - 'struct_hipMemcpy3DParms', 'struct_hipMemsetParams', - 'struct_hipMipmappedArray', 'struct_hipPitchedPtr', - 'struct_hipPointerAttribute_t', 'struct_hipPos', - 'struct_hipResourceDesc', 'struct_hipResourceDesc_0_array', - 'struct_hipResourceDesc_0_linear', - 'struct_hipResourceDesc_0_mipmap', - 'struct_hipResourceDesc_0_pitch2D', 'struct_hipResourceViewDesc', - 'struct_hipTextureDesc', 'struct_hipUUID_t', - 'struct_hipUserObject', 'struct_hip_Memcpy2D', 'struct_ihipCtx_t', - 'struct_ihipEvent_t', 'struct_ihipGraph', - 'struct_ihipMemGenericAllocationHandle', - 'struct_ihipMemPoolHandle_t', 'struct_ihipModuleSymbol_t', - 'struct_ihipModule_t', 'struct_ihipStream_t', - 'struct_ihiprtcLinkState', 'struct_textureReference', 'uint32_t', - 'uint64_t', 'union_HIP_RESOURCE_DESC_st_res', - 'union_hipArrayMapInfo_memHandle', - 'union_hipArrayMapInfo_resource', - 'union_hipArrayMapInfo_subresource', - 'union_hipExternalMemoryHandleDesc_st_handle', - 'union_hipExternalSemaphoreHandleDesc_st_handle', - 'union_hipExternalSemaphoreSignalParams_st_0_nvSciSync', - 'union_hipExternalSemaphoreWaitParams_st_0_nvSciSync', - 'union_hipKernelNodeAttrValue', 'union_hipResourceDesc_res'] -hipDeviceProp_t = hipDeviceProp_tR0600 -hipGetDeviceProperties = hipGetDevicePropertiesR0600 diff --git a/tinygrad/tinygrad/runtime/autogen/hsa.py b/tinygrad/tinygrad/runtime/autogen/hsa.py deleted file mode 100644 index bb65911b..00000000 --- a/tinygrad/tinygrad/runtime/autogen/hsa.py +++ /dev/null @@ -1,5934 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libhsa-runtime64.so'] = ctypes.CDLL(os.getenv('ROCM_PATH')+'/lib/libhsa-runtime64.so' if os.getenv('ROCM_PATH') else ctypes.util.find_library('hsa-runtime64')) -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') - - - -# values for enumeration 'c__EA_hsa_status_t' -c__EA_hsa_status_t__enumvalues = { - 0: 'HSA_STATUS_SUCCESS', - 1: 'HSA_STATUS_INFO_BREAK', - 4096: 'HSA_STATUS_ERROR', - 4097: 'HSA_STATUS_ERROR_INVALID_ARGUMENT', - 4098: 'HSA_STATUS_ERROR_INVALID_QUEUE_CREATION', - 4099: 'HSA_STATUS_ERROR_INVALID_ALLOCATION', - 4100: 'HSA_STATUS_ERROR_INVALID_AGENT', - 4101: 'HSA_STATUS_ERROR_INVALID_REGION', - 4102: 'HSA_STATUS_ERROR_INVALID_SIGNAL', - 4103: 'HSA_STATUS_ERROR_INVALID_QUEUE', - 4104: 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', - 4105: 'HSA_STATUS_ERROR_INVALID_PACKET_FORMAT', - 4106: 'HSA_STATUS_ERROR_RESOURCE_FREE', - 4107: 'HSA_STATUS_ERROR_NOT_INITIALIZED', - 4108: 'HSA_STATUS_ERROR_REFCOUNT_OVERFLOW', - 4109: 'HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS', - 4110: 'HSA_STATUS_ERROR_INVALID_INDEX', - 4111: 'HSA_STATUS_ERROR_INVALID_ISA', - 4119: 'HSA_STATUS_ERROR_INVALID_ISA_NAME', - 4112: 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT', - 4113: 'HSA_STATUS_ERROR_INVALID_EXECUTABLE', - 4114: 'HSA_STATUS_ERROR_FROZEN_EXECUTABLE', - 4115: 'HSA_STATUS_ERROR_INVALID_SYMBOL_NAME', - 4116: 'HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED', - 4117: 'HSA_STATUS_ERROR_VARIABLE_UNDEFINED', - 4118: 'HSA_STATUS_ERROR_EXCEPTION', - 4120: 'HSA_STATUS_ERROR_INVALID_CODE_SYMBOL', - 4121: 'HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL', - 4128: 'HSA_STATUS_ERROR_INVALID_FILE', - 4129: 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER', - 4130: 'HSA_STATUS_ERROR_INVALID_CACHE', - 4131: 'HSA_STATUS_ERROR_INVALID_WAVEFRONT', - 4132: 'HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP', - 4133: 'HSA_STATUS_ERROR_INVALID_RUNTIME_STATE', - 4134: 'HSA_STATUS_ERROR_FATAL', -} -HSA_STATUS_SUCCESS = 0 -HSA_STATUS_INFO_BREAK = 1 -HSA_STATUS_ERROR = 4096 -HSA_STATUS_ERROR_INVALID_ARGUMENT = 4097 -HSA_STATUS_ERROR_INVALID_QUEUE_CREATION = 4098 -HSA_STATUS_ERROR_INVALID_ALLOCATION = 4099 -HSA_STATUS_ERROR_INVALID_AGENT = 4100 -HSA_STATUS_ERROR_INVALID_REGION = 4101 -HSA_STATUS_ERROR_INVALID_SIGNAL = 4102 -HSA_STATUS_ERROR_INVALID_QUEUE = 4103 -HSA_STATUS_ERROR_OUT_OF_RESOURCES = 4104 -HSA_STATUS_ERROR_INVALID_PACKET_FORMAT = 4105 -HSA_STATUS_ERROR_RESOURCE_FREE = 4106 -HSA_STATUS_ERROR_NOT_INITIALIZED = 4107 -HSA_STATUS_ERROR_REFCOUNT_OVERFLOW = 4108 -HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS = 4109 -HSA_STATUS_ERROR_INVALID_INDEX = 4110 -HSA_STATUS_ERROR_INVALID_ISA = 4111 -HSA_STATUS_ERROR_INVALID_ISA_NAME = 4119 -HSA_STATUS_ERROR_INVALID_CODE_OBJECT = 4112 -HSA_STATUS_ERROR_INVALID_EXECUTABLE = 4113 -HSA_STATUS_ERROR_FROZEN_EXECUTABLE = 4114 -HSA_STATUS_ERROR_INVALID_SYMBOL_NAME = 4115 -HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED = 4116 -HSA_STATUS_ERROR_VARIABLE_UNDEFINED = 4117 -HSA_STATUS_ERROR_EXCEPTION = 4118 -HSA_STATUS_ERROR_INVALID_CODE_SYMBOL = 4120 -HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL = 4121 -HSA_STATUS_ERROR_INVALID_FILE = 4128 -HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER = 4129 -HSA_STATUS_ERROR_INVALID_CACHE = 4130 -HSA_STATUS_ERROR_INVALID_WAVEFRONT = 4131 -HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP = 4132 -HSA_STATUS_ERROR_INVALID_RUNTIME_STATE = 4133 -HSA_STATUS_ERROR_FATAL = 4134 -c__EA_hsa_status_t = ctypes.c_uint32 # enum -hsa_status_t = c__EA_hsa_status_t -hsa_status_t__enumvalues = c__EA_hsa_status_t__enumvalues -try: - hsa_status_string = _libraries['libhsa-runtime64.so'].hsa_status_string - hsa_status_string.restype = hsa_status_t - hsa_status_string.argtypes = [hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -class struct_hsa_dim3_s(Structure): - pass - -struct_hsa_dim3_s._pack_ = 1 # source:False -struct_hsa_dim3_s._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -hsa_dim3_t = struct_hsa_dim3_s - -# values for enumeration 'c__EA_hsa_access_permission_t' -c__EA_hsa_access_permission_t__enumvalues = { - 0: 'HSA_ACCESS_PERMISSION_NONE', - 1: 'HSA_ACCESS_PERMISSION_RO', - 2: 'HSA_ACCESS_PERMISSION_WO', - 3: 'HSA_ACCESS_PERMISSION_RW', -} -HSA_ACCESS_PERMISSION_NONE = 0 -HSA_ACCESS_PERMISSION_RO = 1 -HSA_ACCESS_PERMISSION_WO = 2 -HSA_ACCESS_PERMISSION_RW = 3 -c__EA_hsa_access_permission_t = ctypes.c_uint32 # enum -hsa_access_permission_t = c__EA_hsa_access_permission_t -hsa_access_permission_t__enumvalues = c__EA_hsa_access_permission_t__enumvalues -hsa_file_t = ctypes.c_int32 -try: - hsa_init = _libraries['libhsa-runtime64.so'].hsa_init - hsa_init.restype = hsa_status_t - hsa_init.argtypes = [] -except AttributeError: - pass -try: - hsa_shut_down = _libraries['libhsa-runtime64.so'].hsa_shut_down - hsa_shut_down.restype = hsa_status_t - hsa_shut_down.argtypes = [] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_endianness_t' -c__EA_hsa_endianness_t__enumvalues = { - 0: 'HSA_ENDIANNESS_LITTLE', - 1: 'HSA_ENDIANNESS_BIG', -} -HSA_ENDIANNESS_LITTLE = 0 -HSA_ENDIANNESS_BIG = 1 -c__EA_hsa_endianness_t = ctypes.c_uint32 # enum -hsa_endianness_t = c__EA_hsa_endianness_t -hsa_endianness_t__enumvalues = c__EA_hsa_endianness_t__enumvalues - -# values for enumeration 'c__EA_hsa_machine_model_t' -c__EA_hsa_machine_model_t__enumvalues = { - 0: 'HSA_MACHINE_MODEL_SMALL', - 1: 'HSA_MACHINE_MODEL_LARGE', -} -HSA_MACHINE_MODEL_SMALL = 0 -HSA_MACHINE_MODEL_LARGE = 1 -c__EA_hsa_machine_model_t = ctypes.c_uint32 # enum -hsa_machine_model_t = c__EA_hsa_machine_model_t -hsa_machine_model_t__enumvalues = c__EA_hsa_machine_model_t__enumvalues - -# values for enumeration 'c__EA_hsa_profile_t' -c__EA_hsa_profile_t__enumvalues = { - 0: 'HSA_PROFILE_BASE', - 1: 'HSA_PROFILE_FULL', -} -HSA_PROFILE_BASE = 0 -HSA_PROFILE_FULL = 1 -c__EA_hsa_profile_t = ctypes.c_uint32 # enum -hsa_profile_t = c__EA_hsa_profile_t -hsa_profile_t__enumvalues = c__EA_hsa_profile_t__enumvalues - -# values for enumeration 'c__EA_hsa_system_info_t' -c__EA_hsa_system_info_t__enumvalues = { - 0: 'HSA_SYSTEM_INFO_VERSION_MAJOR', - 1: 'HSA_SYSTEM_INFO_VERSION_MINOR', - 2: 'HSA_SYSTEM_INFO_TIMESTAMP', - 3: 'HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY', - 4: 'HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT', - 5: 'HSA_SYSTEM_INFO_ENDIANNESS', - 6: 'HSA_SYSTEM_INFO_MACHINE_MODEL', - 7: 'HSA_SYSTEM_INFO_EXTENSIONS', - 512: 'HSA_AMD_SYSTEM_INFO_BUILD_VERSION', - 513: 'HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED', - 514: 'HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT', - 515: 'HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED', - 516: 'HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED', - 517: 'HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED', - 518: 'HSA_AMD_SYSTEM_INFO_XNACK_ENABLED', - 519: 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR', - 520: 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR', -} -HSA_SYSTEM_INFO_VERSION_MAJOR = 0 -HSA_SYSTEM_INFO_VERSION_MINOR = 1 -HSA_SYSTEM_INFO_TIMESTAMP = 2 -HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY = 3 -HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT = 4 -HSA_SYSTEM_INFO_ENDIANNESS = 5 -HSA_SYSTEM_INFO_MACHINE_MODEL = 6 -HSA_SYSTEM_INFO_EXTENSIONS = 7 -HSA_AMD_SYSTEM_INFO_BUILD_VERSION = 512 -HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED = 513 -HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT = 514 -HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED = 515 -HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED = 516 -HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED = 517 -HSA_AMD_SYSTEM_INFO_XNACK_ENABLED = 518 -HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR = 519 -HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR = 520 -c__EA_hsa_system_info_t = ctypes.c_uint32 # enum -hsa_system_info_t = c__EA_hsa_system_info_t -hsa_system_info_t__enumvalues = c__EA_hsa_system_info_t__enumvalues -try: - hsa_system_get_info = _libraries['libhsa-runtime64.so'].hsa_system_get_info - hsa_system_get_info.restype = hsa_status_t - hsa_system_get_info.argtypes = [hsa_system_info_t, ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_extension_t' -c__EA_hsa_extension_t__enumvalues = { - 0: 'HSA_EXTENSION_FINALIZER', - 1: 'HSA_EXTENSION_IMAGES', - 2: 'HSA_EXTENSION_PERFORMANCE_COUNTERS', - 3: 'HSA_EXTENSION_PROFILING_EVENTS', - 3: 'HSA_EXTENSION_STD_LAST', - 512: 'HSA_AMD_FIRST_EXTENSION', - 512: 'HSA_EXTENSION_AMD_PROFILER', - 513: 'HSA_EXTENSION_AMD_LOADER', - 514: 'HSA_EXTENSION_AMD_AQLPROFILE', - 515: 'HSA_EXTENSION_AMD_PC_SAMPLING', - 515: 'HSA_AMD_LAST_EXTENSION', -} -HSA_EXTENSION_FINALIZER = 0 -HSA_EXTENSION_IMAGES = 1 -HSA_EXTENSION_PERFORMANCE_COUNTERS = 2 -HSA_EXTENSION_PROFILING_EVENTS = 3 -HSA_EXTENSION_STD_LAST = 3 -HSA_AMD_FIRST_EXTENSION = 512 -HSA_EXTENSION_AMD_PROFILER = 512 -HSA_EXTENSION_AMD_LOADER = 513 -HSA_EXTENSION_AMD_AQLPROFILE = 514 -HSA_EXTENSION_AMD_PC_SAMPLING = 515 -HSA_AMD_LAST_EXTENSION = 515 -c__EA_hsa_extension_t = ctypes.c_uint32 # enum -hsa_extension_t = c__EA_hsa_extension_t -hsa_extension_t__enumvalues = c__EA_hsa_extension_t__enumvalues -uint16_t = ctypes.c_uint16 -try: - hsa_extension_get_name = _libraries['libhsa-runtime64.so'].hsa_extension_get_name - hsa_extension_get_name.restype = hsa_status_t - hsa_extension_get_name.argtypes = [uint16_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hsa_system_extension_supported = _libraries['libhsa-runtime64.so'].hsa_system_extension_supported - hsa_system_extension_supported.restype = hsa_status_t - hsa_system_extension_supported.argtypes = [uint16_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_system_major_extension_supported = _libraries['libhsa-runtime64.so'].hsa_system_major_extension_supported - hsa_system_major_extension_supported.restype = hsa_status_t - hsa_system_major_extension_supported.argtypes = [uint16_t, uint16_t, ctypes.POINTER(ctypes.c_uint16), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_system_get_extension_table = _libraries['libhsa-runtime64.so'].hsa_system_get_extension_table - hsa_system_get_extension_table.restype = hsa_status_t - hsa_system_get_extension_table.argtypes = [uint16_t, uint16_t, uint16_t, ctypes.POINTER(None)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - hsa_system_get_major_extension_table = _libraries['libhsa-runtime64.so'].hsa_system_get_major_extension_table - hsa_system_get_major_extension_table.restype = hsa_status_t - hsa_system_get_major_extension_table.argtypes = [uint16_t, uint16_t, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_agent_s(Structure): - pass - -struct_hsa_agent_s._pack_ = 1 # source:False -struct_hsa_agent_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_agent_t = struct_hsa_agent_s - -# values for enumeration 'c__EA_hsa_agent_feature_t' -c__EA_hsa_agent_feature_t__enumvalues = { - 1: 'HSA_AGENT_FEATURE_KERNEL_DISPATCH', - 2: 'HSA_AGENT_FEATURE_AGENT_DISPATCH', -} -HSA_AGENT_FEATURE_KERNEL_DISPATCH = 1 -HSA_AGENT_FEATURE_AGENT_DISPATCH = 2 -c__EA_hsa_agent_feature_t = ctypes.c_uint32 # enum -hsa_agent_feature_t = c__EA_hsa_agent_feature_t -hsa_agent_feature_t__enumvalues = c__EA_hsa_agent_feature_t__enumvalues - -# values for enumeration 'c__EA_hsa_device_type_t' -c__EA_hsa_device_type_t__enumvalues = { - 0: 'HSA_DEVICE_TYPE_CPU', - 1: 'HSA_DEVICE_TYPE_GPU', - 2: 'HSA_DEVICE_TYPE_DSP', -} -HSA_DEVICE_TYPE_CPU = 0 -HSA_DEVICE_TYPE_GPU = 1 -HSA_DEVICE_TYPE_DSP = 2 -c__EA_hsa_device_type_t = ctypes.c_uint32 # enum -hsa_device_type_t = c__EA_hsa_device_type_t -hsa_device_type_t__enumvalues = c__EA_hsa_device_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_default_float_rounding_mode_t' -c__EA_hsa_default_float_rounding_mode_t__enumvalues = { - 0: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT', - 1: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO', - 2: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR', -} -HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT = 0 -HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO = 1 -HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR = 2 -c__EA_hsa_default_float_rounding_mode_t = ctypes.c_uint32 # enum -hsa_default_float_rounding_mode_t = c__EA_hsa_default_float_rounding_mode_t -hsa_default_float_rounding_mode_t__enumvalues = c__EA_hsa_default_float_rounding_mode_t__enumvalues - -# values for enumeration 'c__EA_hsa_agent_info_t' -c__EA_hsa_agent_info_t__enumvalues = { - 0: 'HSA_AGENT_INFO_NAME', - 1: 'HSA_AGENT_INFO_VENDOR_NAME', - 2: 'HSA_AGENT_INFO_FEATURE', - 3: 'HSA_AGENT_INFO_MACHINE_MODEL', - 4: 'HSA_AGENT_INFO_PROFILE', - 5: 'HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 23: 'HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 24: 'HSA_AGENT_INFO_FAST_F16_OPERATION', - 6: 'HSA_AGENT_INFO_WAVEFRONT_SIZE', - 7: 'HSA_AGENT_INFO_WORKGROUP_MAX_DIM', - 8: 'HSA_AGENT_INFO_WORKGROUP_MAX_SIZE', - 9: 'HSA_AGENT_INFO_GRID_MAX_DIM', - 10: 'HSA_AGENT_INFO_GRID_MAX_SIZE', - 11: 'HSA_AGENT_INFO_FBARRIER_MAX_SIZE', - 12: 'HSA_AGENT_INFO_QUEUES_MAX', - 13: 'HSA_AGENT_INFO_QUEUE_MIN_SIZE', - 14: 'HSA_AGENT_INFO_QUEUE_MAX_SIZE', - 15: 'HSA_AGENT_INFO_QUEUE_TYPE', - 16: 'HSA_AGENT_INFO_NODE', - 17: 'HSA_AGENT_INFO_DEVICE', - 18: 'HSA_AGENT_INFO_CACHE_SIZE', - 19: 'HSA_AGENT_INFO_ISA', - 20: 'HSA_AGENT_INFO_EXTENSIONS', - 21: 'HSA_AGENT_INFO_VERSION_MAJOR', - 22: 'HSA_AGENT_INFO_VERSION_MINOR', - 2147483647: 'HSA_AGENT_INFO_LAST', -} -HSA_AGENT_INFO_NAME = 0 -HSA_AGENT_INFO_VENDOR_NAME = 1 -HSA_AGENT_INFO_FEATURE = 2 -HSA_AGENT_INFO_MACHINE_MODEL = 3 -HSA_AGENT_INFO_PROFILE = 4 -HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5 -HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = 23 -HSA_AGENT_INFO_FAST_F16_OPERATION = 24 -HSA_AGENT_INFO_WAVEFRONT_SIZE = 6 -HSA_AGENT_INFO_WORKGROUP_MAX_DIM = 7 -HSA_AGENT_INFO_WORKGROUP_MAX_SIZE = 8 -HSA_AGENT_INFO_GRID_MAX_DIM = 9 -HSA_AGENT_INFO_GRID_MAX_SIZE = 10 -HSA_AGENT_INFO_FBARRIER_MAX_SIZE = 11 -HSA_AGENT_INFO_QUEUES_MAX = 12 -HSA_AGENT_INFO_QUEUE_MIN_SIZE = 13 -HSA_AGENT_INFO_QUEUE_MAX_SIZE = 14 -HSA_AGENT_INFO_QUEUE_TYPE = 15 -HSA_AGENT_INFO_NODE = 16 -HSA_AGENT_INFO_DEVICE = 17 -HSA_AGENT_INFO_CACHE_SIZE = 18 -HSA_AGENT_INFO_ISA = 19 -HSA_AGENT_INFO_EXTENSIONS = 20 -HSA_AGENT_INFO_VERSION_MAJOR = 21 -HSA_AGENT_INFO_VERSION_MINOR = 22 -HSA_AGENT_INFO_LAST = 2147483647 -c__EA_hsa_agent_info_t = ctypes.c_uint32 # enum -hsa_agent_info_t = c__EA_hsa_agent_info_t -hsa_agent_info_t__enumvalues = c__EA_hsa_agent_info_t__enumvalues -try: - hsa_agent_get_info = _libraries['libhsa-runtime64.so'].hsa_agent_get_info - hsa_agent_get_info.restype = hsa_status_t - hsa_agent_get_info.argtypes = [hsa_agent_t, hsa_agent_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_iterate_agents = _libraries['libhsa-runtime64.so'].hsa_iterate_agents - hsa_iterate_agents.restype = hsa_status_t - hsa_iterate_agents.argtypes = [ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_exception_policy_t' -c__EA_hsa_exception_policy_t__enumvalues = { - 1: 'HSA_EXCEPTION_POLICY_BREAK', - 2: 'HSA_EXCEPTION_POLICY_DETECT', -} -HSA_EXCEPTION_POLICY_BREAK = 1 -HSA_EXCEPTION_POLICY_DETECT = 2 -c__EA_hsa_exception_policy_t = ctypes.c_uint32 # enum -hsa_exception_policy_t = c__EA_hsa_exception_policy_t -hsa_exception_policy_t__enumvalues = c__EA_hsa_exception_policy_t__enumvalues -try: - hsa_agent_get_exception_policies = _libraries['libhsa-runtime64.so'].hsa_agent_get_exception_policies - hsa_agent_get_exception_policies.restype = hsa_status_t - hsa_agent_get_exception_policies.argtypes = [hsa_agent_t, hsa_profile_t, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -class struct_hsa_cache_s(Structure): - pass - -struct_hsa_cache_s._pack_ = 1 # source:False -struct_hsa_cache_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_cache_t = struct_hsa_cache_s - -# values for enumeration 'c__EA_hsa_cache_info_t' -c__EA_hsa_cache_info_t__enumvalues = { - 0: 'HSA_CACHE_INFO_NAME_LENGTH', - 1: 'HSA_CACHE_INFO_NAME', - 2: 'HSA_CACHE_INFO_LEVEL', - 3: 'HSA_CACHE_INFO_SIZE', -} -HSA_CACHE_INFO_NAME_LENGTH = 0 -HSA_CACHE_INFO_NAME = 1 -HSA_CACHE_INFO_LEVEL = 2 -HSA_CACHE_INFO_SIZE = 3 -c__EA_hsa_cache_info_t = ctypes.c_uint32 # enum -hsa_cache_info_t = c__EA_hsa_cache_info_t -hsa_cache_info_t__enumvalues = c__EA_hsa_cache_info_t__enumvalues -try: - hsa_cache_get_info = _libraries['libhsa-runtime64.so'].hsa_cache_get_info - hsa_cache_get_info.restype = hsa_status_t - hsa_cache_get_info.argtypes = [hsa_cache_t, hsa_cache_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_iterate_caches = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_caches - hsa_agent_iterate_caches.restype = hsa_status_t - hsa_agent_iterate_caches.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_cache_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_extension_supported = _libraries['libhsa-runtime64.so'].hsa_agent_extension_supported - hsa_agent_extension_supported.restype = hsa_status_t - hsa_agent_extension_supported.argtypes = [uint16_t, hsa_agent_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_agent_major_extension_supported = _libraries['libhsa-runtime64.so'].hsa_agent_major_extension_supported - hsa_agent_major_extension_supported.restype = hsa_status_t - hsa_agent_major_extension_supported.argtypes = [uint16_t, hsa_agent_t, uint16_t, ctypes.POINTER(ctypes.c_uint16), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -class struct_hsa_signal_s(Structure): - pass - -struct_hsa_signal_s._pack_ = 1 # source:False -struct_hsa_signal_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_signal_t = struct_hsa_signal_s -hsa_signal_value_t = ctypes.c_int64 -uint32_t = ctypes.c_uint32 -try: - hsa_signal_create = _libraries['libhsa-runtime64.so'].hsa_signal_create - hsa_signal_create.restype = hsa_status_t - hsa_signal_create.argtypes = [hsa_signal_value_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass -try: - hsa_signal_destroy = _libraries['libhsa-runtime64.so'].hsa_signal_destroy - hsa_signal_destroy.restype = hsa_status_t - hsa_signal_destroy.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_load_scacquire - hsa_signal_load_scacquire.restype = hsa_signal_value_t - hsa_signal_load_scacquire.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_load_relaxed - hsa_signal_load_relaxed.restype = hsa_signal_value_t - hsa_signal_load_relaxed.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_load_acquire - hsa_signal_load_acquire.restype = hsa_signal_value_t - hsa_signal_load_acquire.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_store_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_store_relaxed - hsa_signal_store_relaxed.restype = None - hsa_signal_store_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_store_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_store_screlease - hsa_signal_store_screlease.restype = None - hsa_signal_store_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_store_release = _libraries['libhsa-runtime64.so'].hsa_signal_store_release - hsa_signal_store_release.restype = None - hsa_signal_store_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_silent_store_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_silent_store_relaxed - hsa_signal_silent_store_relaxed.restype = None - hsa_signal_silent_store_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_silent_store_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_silent_store_screlease - hsa_signal_silent_store_screlease.restype = None - hsa_signal_silent_store_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_scacq_screl - hsa_signal_exchange_scacq_screl.restype = hsa_signal_value_t - hsa_signal_exchange_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_acq_rel - hsa_signal_exchange_acq_rel.restype = hsa_signal_value_t - hsa_signal_exchange_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_scacquire - hsa_signal_exchange_scacquire.restype = hsa_signal_value_t - hsa_signal_exchange_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_acquire - hsa_signal_exchange_acquire.restype = hsa_signal_value_t - hsa_signal_exchange_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_relaxed - hsa_signal_exchange_relaxed.restype = hsa_signal_value_t - hsa_signal_exchange_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_screlease - hsa_signal_exchange_screlease.restype = hsa_signal_value_t - hsa_signal_exchange_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_release = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_release - hsa_signal_exchange_release.restype = hsa_signal_value_t - hsa_signal_exchange_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_cas_scacq_screl - hsa_signal_cas_scacq_screl.restype = hsa_signal_value_t - hsa_signal_cas_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_cas_acq_rel - hsa_signal_cas_acq_rel.restype = hsa_signal_value_t - hsa_signal_cas_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_cas_scacquire - hsa_signal_cas_scacquire.restype = hsa_signal_value_t - hsa_signal_cas_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_cas_acquire - hsa_signal_cas_acquire.restype = hsa_signal_value_t - hsa_signal_cas_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_cas_relaxed - hsa_signal_cas_relaxed.restype = hsa_signal_value_t - hsa_signal_cas_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_cas_screlease - hsa_signal_cas_screlease.restype = hsa_signal_value_t - hsa_signal_cas_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_release = _libraries['libhsa-runtime64.so'].hsa_signal_cas_release - hsa_signal_cas_release.restype = hsa_signal_value_t - hsa_signal_cas_release.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_add_scacq_screl - hsa_signal_add_scacq_screl.restype = None - hsa_signal_add_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_add_acq_rel - hsa_signal_add_acq_rel.restype = None - hsa_signal_add_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_add_scacquire - hsa_signal_add_scacquire.restype = None - hsa_signal_add_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_add_acquire - hsa_signal_add_acquire.restype = None - hsa_signal_add_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_add_relaxed - hsa_signal_add_relaxed.restype = None - hsa_signal_add_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_add_screlease - hsa_signal_add_screlease.restype = None - hsa_signal_add_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_release = _libraries['libhsa-runtime64.so'].hsa_signal_add_release - hsa_signal_add_release.restype = None - hsa_signal_add_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_scacq_screl - hsa_signal_subtract_scacq_screl.restype = None - hsa_signal_subtract_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_acq_rel - hsa_signal_subtract_acq_rel.restype = None - hsa_signal_subtract_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_scacquire - hsa_signal_subtract_scacquire.restype = None - hsa_signal_subtract_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_acquire - hsa_signal_subtract_acquire.restype = None - hsa_signal_subtract_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_relaxed - hsa_signal_subtract_relaxed.restype = None - hsa_signal_subtract_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_screlease - hsa_signal_subtract_screlease.restype = None - hsa_signal_subtract_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_release = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_release - hsa_signal_subtract_release.restype = None - hsa_signal_subtract_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_and_scacq_screl - hsa_signal_and_scacq_screl.restype = None - hsa_signal_and_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_and_acq_rel - hsa_signal_and_acq_rel.restype = None - hsa_signal_and_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_and_scacquire - hsa_signal_and_scacquire.restype = None - hsa_signal_and_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_and_acquire - hsa_signal_and_acquire.restype = None - hsa_signal_and_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_and_relaxed - hsa_signal_and_relaxed.restype = None - hsa_signal_and_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_and_screlease - hsa_signal_and_screlease.restype = None - hsa_signal_and_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_release = _libraries['libhsa-runtime64.so'].hsa_signal_and_release - hsa_signal_and_release.restype = None - hsa_signal_and_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_or_scacq_screl - hsa_signal_or_scacq_screl.restype = None - hsa_signal_or_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_or_acq_rel - hsa_signal_or_acq_rel.restype = None - hsa_signal_or_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_or_scacquire - hsa_signal_or_scacquire.restype = None - hsa_signal_or_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_or_acquire - hsa_signal_or_acquire.restype = None - hsa_signal_or_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_or_relaxed - hsa_signal_or_relaxed.restype = None - hsa_signal_or_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_or_screlease - hsa_signal_or_screlease.restype = None - hsa_signal_or_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_release = _libraries['libhsa-runtime64.so'].hsa_signal_or_release - hsa_signal_or_release.restype = None - hsa_signal_or_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_xor_scacq_screl - hsa_signal_xor_scacq_screl.restype = None - hsa_signal_xor_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_xor_acq_rel - hsa_signal_xor_acq_rel.restype = None - hsa_signal_xor_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_xor_scacquire - hsa_signal_xor_scacquire.restype = None - hsa_signal_xor_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_xor_acquire - hsa_signal_xor_acquire.restype = None - hsa_signal_xor_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_xor_relaxed - hsa_signal_xor_relaxed.restype = None - hsa_signal_xor_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_xor_screlease - hsa_signal_xor_screlease.restype = None - hsa_signal_xor_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_release = _libraries['libhsa-runtime64.so'].hsa_signal_xor_release - hsa_signal_xor_release.restype = None - hsa_signal_xor_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_signal_condition_t' -c__EA_hsa_signal_condition_t__enumvalues = { - 0: 'HSA_SIGNAL_CONDITION_EQ', - 1: 'HSA_SIGNAL_CONDITION_NE', - 2: 'HSA_SIGNAL_CONDITION_LT', - 3: 'HSA_SIGNAL_CONDITION_GTE', -} -HSA_SIGNAL_CONDITION_EQ = 0 -HSA_SIGNAL_CONDITION_NE = 1 -HSA_SIGNAL_CONDITION_LT = 2 -HSA_SIGNAL_CONDITION_GTE = 3 -c__EA_hsa_signal_condition_t = ctypes.c_uint32 # enum -hsa_signal_condition_t = c__EA_hsa_signal_condition_t -hsa_signal_condition_t__enumvalues = c__EA_hsa_signal_condition_t__enumvalues - -# values for enumeration 'c__EA_hsa_wait_state_t' -c__EA_hsa_wait_state_t__enumvalues = { - 0: 'HSA_WAIT_STATE_BLOCKED', - 1: 'HSA_WAIT_STATE_ACTIVE', -} -HSA_WAIT_STATE_BLOCKED = 0 -HSA_WAIT_STATE_ACTIVE = 1 -c__EA_hsa_wait_state_t = ctypes.c_uint32 # enum -hsa_wait_state_t = c__EA_hsa_wait_state_t -hsa_wait_state_t__enumvalues = c__EA_hsa_wait_state_t__enumvalues -uint64_t = ctypes.c_uint64 -try: - hsa_signal_wait_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_wait_scacquire - hsa_signal_wait_scacquire.restype = hsa_signal_value_t - hsa_signal_wait_scacquire.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -try: - hsa_signal_wait_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_wait_relaxed - hsa_signal_wait_relaxed.restype = hsa_signal_value_t - hsa_signal_wait_relaxed.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -try: - hsa_signal_wait_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_wait_acquire - hsa_signal_wait_acquire.restype = hsa_signal_value_t - hsa_signal_wait_acquire.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -class struct_hsa_signal_group_s(Structure): - pass - -struct_hsa_signal_group_s._pack_ = 1 # source:False -struct_hsa_signal_group_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_signal_group_t = struct_hsa_signal_group_s -try: - hsa_signal_group_create = _libraries['libhsa-runtime64.so'].hsa_signal_group_create - hsa_signal_group_create.restype = hsa_status_t - hsa_signal_group_create.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_signal_s), uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_signal_group_s)] -except AttributeError: - pass -try: - hsa_signal_group_destroy = _libraries['libhsa-runtime64.so'].hsa_signal_group_destroy - hsa_signal_group_destroy.restype = hsa_status_t - hsa_signal_group_destroy.argtypes = [hsa_signal_group_t] -except AttributeError: - pass -try: - hsa_signal_group_wait_any_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_group_wait_any_scacquire - hsa_signal_group_wait_any_scacquire.restype = hsa_status_t - hsa_signal_group_wait_any_scacquire.argtypes = [hsa_signal_group_t, ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), hsa_wait_state_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -try: - hsa_signal_group_wait_any_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_group_wait_any_relaxed - hsa_signal_group_wait_any_relaxed.restype = hsa_status_t - hsa_signal_group_wait_any_relaxed.argtypes = [hsa_signal_group_t, ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), hsa_wait_state_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -class struct_hsa_region_s(Structure): - pass - -struct_hsa_region_s._pack_ = 1 # source:False -struct_hsa_region_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_region_t = struct_hsa_region_s - -# values for enumeration 'c__EA_hsa_queue_type_t' -c__EA_hsa_queue_type_t__enumvalues = { - 0: 'HSA_QUEUE_TYPE_MULTI', - 1: 'HSA_QUEUE_TYPE_SINGLE', - 2: 'HSA_QUEUE_TYPE_COOPERATIVE', -} -HSA_QUEUE_TYPE_MULTI = 0 -HSA_QUEUE_TYPE_SINGLE = 1 -HSA_QUEUE_TYPE_COOPERATIVE = 2 -c__EA_hsa_queue_type_t = ctypes.c_uint32 # enum -hsa_queue_type_t = c__EA_hsa_queue_type_t -hsa_queue_type_t__enumvalues = c__EA_hsa_queue_type_t__enumvalues -hsa_queue_type32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_queue_feature_t' -c__EA_hsa_queue_feature_t__enumvalues = { - 1: 'HSA_QUEUE_FEATURE_KERNEL_DISPATCH', - 2: 'HSA_QUEUE_FEATURE_AGENT_DISPATCH', -} -HSA_QUEUE_FEATURE_KERNEL_DISPATCH = 1 -HSA_QUEUE_FEATURE_AGENT_DISPATCH = 2 -c__EA_hsa_queue_feature_t = ctypes.c_uint32 # enum -hsa_queue_feature_t = c__EA_hsa_queue_feature_t -hsa_queue_feature_t__enumvalues = c__EA_hsa_queue_feature_t__enumvalues -class struct_hsa_queue_s(Structure): - pass - -struct_hsa_queue_s._pack_ = 1 # source:False -struct_hsa_queue_s._fields_ = [ - ('type', ctypes.c_uint32), - ('features', ctypes.c_uint32), - ('base_address', ctypes.POINTER(None)), - ('doorbell_signal', hsa_signal_t), - ('size', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('id', ctypes.c_uint64), -] - -hsa_queue_t = struct_hsa_queue_s -try: - hsa_queue_create = _libraries['libhsa-runtime64.so'].hsa_queue_create - hsa_queue_create.restype = hsa_status_t - hsa_queue_create.argtypes = [hsa_agent_t, uint32_t, hsa_queue_type32_t, ctypes.CFUNCTYPE(None, c__EA_hsa_status_t, ctypes.POINTER(struct_hsa_queue_s), ctypes.POINTER(None)), ctypes.POINTER(None), uint32_t, uint32_t, ctypes.POINTER(ctypes.POINTER(struct_hsa_queue_s))] -except AttributeError: - pass -try: - hsa_soft_queue_create = _libraries['libhsa-runtime64.so'].hsa_soft_queue_create - hsa_soft_queue_create.restype = hsa_status_t - hsa_soft_queue_create.argtypes = [hsa_region_t, uint32_t, hsa_queue_type32_t, uint32_t, hsa_signal_t, ctypes.POINTER(ctypes.POINTER(struct_hsa_queue_s))] -except AttributeError: - pass -try: - hsa_queue_destroy = _libraries['libhsa-runtime64.so'].hsa_queue_destroy - hsa_queue_destroy.restype = hsa_status_t - hsa_queue_destroy.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_inactivate = _libraries['libhsa-runtime64.so'].hsa_queue_inactivate - hsa_queue_inactivate.restype = hsa_status_t - hsa_queue_inactivate.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_acquire - hsa_queue_load_read_index_acquire.restype = uint64_t - hsa_queue_load_read_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_scacquire - hsa_queue_load_read_index_scacquire.restype = uint64_t - hsa_queue_load_read_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_relaxed - hsa_queue_load_read_index_relaxed.restype = uint64_t - hsa_queue_load_read_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_acquire - hsa_queue_load_write_index_acquire.restype = uint64_t - hsa_queue_load_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_scacquire - hsa_queue_load_write_index_scacquire.restype = uint64_t - hsa_queue_load_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_relaxed - hsa_queue_load_write_index_relaxed.restype = uint64_t - hsa_queue_load_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_store_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_relaxed - hsa_queue_store_write_index_relaxed.restype = None - hsa_queue_store_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_release - hsa_queue_store_write_index_release.restype = None - hsa_queue_store_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_screlease - hsa_queue_store_write_index_screlease.restype = None - hsa_queue_store_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_acq_rel = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_acq_rel - hsa_queue_cas_write_index_acq_rel.restype = uint64_t - hsa_queue_cas_write_index_acq_rel.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_scacq_screl - hsa_queue_cas_write_index_scacq_screl.restype = uint64_t - hsa_queue_cas_write_index_scacq_screl.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_acquire - hsa_queue_cas_write_index_acquire.restype = uint64_t - hsa_queue_cas_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_scacquire - hsa_queue_cas_write_index_scacquire.restype = uint64_t - hsa_queue_cas_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_relaxed - hsa_queue_cas_write_index_relaxed.restype = uint64_t - hsa_queue_cas_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_release - hsa_queue_cas_write_index_release.restype = uint64_t - hsa_queue_cas_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_screlease - hsa_queue_cas_write_index_screlease.restype = uint64_t - hsa_queue_cas_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_acq_rel = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_acq_rel - hsa_queue_add_write_index_acq_rel.restype = uint64_t - hsa_queue_add_write_index_acq_rel.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_scacq_screl - hsa_queue_add_write_index_scacq_screl.restype = uint64_t - hsa_queue_add_write_index_scacq_screl.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_acquire - hsa_queue_add_write_index_acquire.restype = uint64_t - hsa_queue_add_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_scacquire - hsa_queue_add_write_index_scacquire.restype = uint64_t - hsa_queue_add_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_relaxed - hsa_queue_add_write_index_relaxed.restype = uint64_t - hsa_queue_add_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_release - hsa_queue_add_write_index_release.restype = uint64_t - hsa_queue_add_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_screlease - hsa_queue_add_write_index_screlease.restype = uint64_t - hsa_queue_add_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_relaxed - hsa_queue_store_read_index_relaxed.restype = None - hsa_queue_store_read_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_release - hsa_queue_store_read_index_release.restype = None - hsa_queue_store_read_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_screlease - hsa_queue_store_read_index_screlease.restype = None - hsa_queue_store_read_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_packet_type_t' -c__EA_hsa_packet_type_t__enumvalues = { - 0: 'HSA_PACKET_TYPE_VENDOR_SPECIFIC', - 1: 'HSA_PACKET_TYPE_INVALID', - 2: 'HSA_PACKET_TYPE_KERNEL_DISPATCH', - 3: 'HSA_PACKET_TYPE_BARRIER_AND', - 4: 'HSA_PACKET_TYPE_AGENT_DISPATCH', - 5: 'HSA_PACKET_TYPE_BARRIER_OR', -} -HSA_PACKET_TYPE_VENDOR_SPECIFIC = 0 -HSA_PACKET_TYPE_INVALID = 1 -HSA_PACKET_TYPE_KERNEL_DISPATCH = 2 -HSA_PACKET_TYPE_BARRIER_AND = 3 -HSA_PACKET_TYPE_AGENT_DISPATCH = 4 -HSA_PACKET_TYPE_BARRIER_OR = 5 -c__EA_hsa_packet_type_t = ctypes.c_uint32 # enum -hsa_packet_type_t = c__EA_hsa_packet_type_t -hsa_packet_type_t__enumvalues = c__EA_hsa_packet_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_fence_scope_t' -c__EA_hsa_fence_scope_t__enumvalues = { - 0: 'HSA_FENCE_SCOPE_NONE', - 1: 'HSA_FENCE_SCOPE_AGENT', - 2: 'HSA_FENCE_SCOPE_SYSTEM', -} -HSA_FENCE_SCOPE_NONE = 0 -HSA_FENCE_SCOPE_AGENT = 1 -HSA_FENCE_SCOPE_SYSTEM = 2 -c__EA_hsa_fence_scope_t = ctypes.c_uint32 # enum -hsa_fence_scope_t = c__EA_hsa_fence_scope_t -hsa_fence_scope_t__enumvalues = c__EA_hsa_fence_scope_t__enumvalues - -# values for enumeration 'c__EA_hsa_packet_header_t' -c__EA_hsa_packet_header_t__enumvalues = { - 0: 'HSA_PACKET_HEADER_TYPE', - 8: 'HSA_PACKET_HEADER_BARRIER', - 9: 'HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE', - 9: 'HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE', - 11: 'HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE', - 11: 'HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE', -} -HSA_PACKET_HEADER_TYPE = 0 -HSA_PACKET_HEADER_BARRIER = 8 -HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE = 9 -HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE = 9 -HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE = 11 -HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE = 11 -c__EA_hsa_packet_header_t = ctypes.c_uint32 # enum -hsa_packet_header_t = c__EA_hsa_packet_header_t -hsa_packet_header_t__enumvalues = c__EA_hsa_packet_header_t__enumvalues - -# values for enumeration 'c__EA_hsa_packet_header_width_t' -c__EA_hsa_packet_header_width_t__enumvalues = { - 8: 'HSA_PACKET_HEADER_WIDTH_TYPE', - 1: 'HSA_PACKET_HEADER_WIDTH_BARRIER', - 2: 'HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE', -} -HSA_PACKET_HEADER_WIDTH_TYPE = 8 -HSA_PACKET_HEADER_WIDTH_BARRIER = 1 -HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE = 2 -c__EA_hsa_packet_header_width_t = ctypes.c_uint32 # enum -hsa_packet_header_width_t = c__EA_hsa_packet_header_width_t -hsa_packet_header_width_t__enumvalues = c__EA_hsa_packet_header_width_t__enumvalues - -# values for enumeration 'c__EA_hsa_kernel_dispatch_packet_setup_t' -c__EA_hsa_kernel_dispatch_packet_setup_t__enumvalues = { - 0: 'HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS', -} -HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS = 0 -c__EA_hsa_kernel_dispatch_packet_setup_t = ctypes.c_uint32 # enum -hsa_kernel_dispatch_packet_setup_t = c__EA_hsa_kernel_dispatch_packet_setup_t -hsa_kernel_dispatch_packet_setup_t__enumvalues = c__EA_hsa_kernel_dispatch_packet_setup_t__enumvalues - -# values for enumeration 'c__EA_hsa_kernel_dispatch_packet_setup_width_t' -c__EA_hsa_kernel_dispatch_packet_setup_width_t__enumvalues = { - 2: 'HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS', -} -HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS = 2 -c__EA_hsa_kernel_dispatch_packet_setup_width_t = ctypes.c_uint32 # enum -hsa_kernel_dispatch_packet_setup_width_t = c__EA_hsa_kernel_dispatch_packet_setup_width_t -hsa_kernel_dispatch_packet_setup_width_t__enumvalues = c__EA_hsa_kernel_dispatch_packet_setup_width_t__enumvalues -class struct_hsa_kernel_dispatch_packet_s(Structure): - pass - -struct_hsa_kernel_dispatch_packet_s._pack_ = 1 # source:False -struct_hsa_kernel_dispatch_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('setup', ctypes.c_uint16), - ('workgroup_size_x', ctypes.c_uint16), - ('workgroup_size_y', ctypes.c_uint16), - ('workgroup_size_z', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('grid_size_x', ctypes.c_uint32), - ('grid_size_y', ctypes.c_uint32), - ('grid_size_z', ctypes.c_uint32), - ('private_segment_size', ctypes.c_uint32), - ('group_segment_size', ctypes.c_uint32), - ('kernel_object', ctypes.c_uint64), - ('kernarg_address', ctypes.POINTER(None)), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), -] - -hsa_kernel_dispatch_packet_t = struct_hsa_kernel_dispatch_packet_s -class struct_hsa_agent_dispatch_packet_s(Structure): - pass - -struct_hsa_agent_dispatch_packet_s._pack_ = 1 # source:False -struct_hsa_agent_dispatch_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('reserved0', ctypes.c_uint32), - ('return_address', ctypes.POINTER(None)), - ('arg', ctypes.c_uint64 * 4), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), -] - -hsa_agent_dispatch_packet_t = struct_hsa_agent_dispatch_packet_s -class struct_hsa_barrier_and_packet_s(Structure): - pass - -struct_hsa_barrier_and_packet_s._pack_ = 1 # source:False -struct_hsa_barrier_and_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('reserved1', ctypes.c_uint32), - ('dep_signal', struct_hsa_signal_s * 5), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), -] - -hsa_barrier_and_packet_t = struct_hsa_barrier_and_packet_s -class struct_hsa_barrier_or_packet_s(Structure): - pass - -struct_hsa_barrier_or_packet_s._pack_ = 1 # source:False -struct_hsa_barrier_or_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('reserved1', ctypes.c_uint32), - ('dep_signal', struct_hsa_signal_s * 5), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), -] - -hsa_barrier_or_packet_t = struct_hsa_barrier_or_packet_s - -# values for enumeration 'c__EA_hsa_region_segment_t' -c__EA_hsa_region_segment_t__enumvalues = { - 0: 'HSA_REGION_SEGMENT_GLOBAL', - 1: 'HSA_REGION_SEGMENT_READONLY', - 2: 'HSA_REGION_SEGMENT_PRIVATE', - 3: 'HSA_REGION_SEGMENT_GROUP', - 4: 'HSA_REGION_SEGMENT_KERNARG', -} -HSA_REGION_SEGMENT_GLOBAL = 0 -HSA_REGION_SEGMENT_READONLY = 1 -HSA_REGION_SEGMENT_PRIVATE = 2 -HSA_REGION_SEGMENT_GROUP = 3 -HSA_REGION_SEGMENT_KERNARG = 4 -c__EA_hsa_region_segment_t = ctypes.c_uint32 # enum -hsa_region_segment_t = c__EA_hsa_region_segment_t -hsa_region_segment_t__enumvalues = c__EA_hsa_region_segment_t__enumvalues - -# values for enumeration 'c__EA_hsa_region_global_flag_t' -c__EA_hsa_region_global_flag_t__enumvalues = { - 1: 'HSA_REGION_GLOBAL_FLAG_KERNARG', - 2: 'HSA_REGION_GLOBAL_FLAG_FINE_GRAINED', - 4: 'HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED', - 8: 'HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', -} -HSA_REGION_GLOBAL_FLAG_KERNARG = 1 -HSA_REGION_GLOBAL_FLAG_FINE_GRAINED = 2 -HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED = 4 -HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = 8 -c__EA_hsa_region_global_flag_t = ctypes.c_uint32 # enum -hsa_region_global_flag_t = c__EA_hsa_region_global_flag_t -hsa_region_global_flag_t__enumvalues = c__EA_hsa_region_global_flag_t__enumvalues - -# values for enumeration 'c__EA_hsa_region_info_t' -c__EA_hsa_region_info_t__enumvalues = { - 0: 'HSA_REGION_INFO_SEGMENT', - 1: 'HSA_REGION_INFO_GLOBAL_FLAGS', - 2: 'HSA_REGION_INFO_SIZE', - 4: 'HSA_REGION_INFO_ALLOC_MAX_SIZE', - 8: 'HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE', - 5: 'HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED', - 6: 'HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE', - 7: 'HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT', -} -HSA_REGION_INFO_SEGMENT = 0 -HSA_REGION_INFO_GLOBAL_FLAGS = 1 -HSA_REGION_INFO_SIZE = 2 -HSA_REGION_INFO_ALLOC_MAX_SIZE = 4 -HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE = 8 -HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED = 5 -HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE = 6 -HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT = 7 -c__EA_hsa_region_info_t = ctypes.c_uint32 # enum -hsa_region_info_t = c__EA_hsa_region_info_t -hsa_region_info_t__enumvalues = c__EA_hsa_region_info_t__enumvalues -try: - hsa_region_get_info = _libraries['libhsa-runtime64.so'].hsa_region_get_info - hsa_region_get_info.restype = hsa_status_t - hsa_region_get_info.argtypes = [hsa_region_t, hsa_region_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_iterate_regions = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_regions - hsa_agent_iterate_regions.restype = hsa_status_t - hsa_agent_iterate_regions.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_region_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_memory_allocate = _libraries['libhsa-runtime64.so'].hsa_memory_allocate - hsa_memory_allocate.restype = hsa_status_t - hsa_memory_allocate.argtypes = [hsa_region_t, size_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_memory_free = _libraries['libhsa-runtime64.so'].hsa_memory_free - hsa_memory_free.restype = hsa_status_t - hsa_memory_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_memory_copy = _libraries['libhsa-runtime64.so'].hsa_memory_copy - hsa_memory_copy.restype = hsa_status_t - hsa_memory_copy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hsa_memory_assign_agent = _libraries['libhsa-runtime64.so'].hsa_memory_assign_agent - hsa_memory_assign_agent.restype = hsa_status_t - hsa_memory_assign_agent.argtypes = [ctypes.POINTER(None), hsa_agent_t, hsa_access_permission_t] -except AttributeError: - pass -try: - hsa_memory_register = _libraries['libhsa-runtime64.so'].hsa_memory_register - hsa_memory_register.restype = hsa_status_t - hsa_memory_register.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hsa_memory_deregister = _libraries['libhsa-runtime64.so'].hsa_memory_deregister - hsa_memory_deregister.restype = hsa_status_t - hsa_memory_deregister.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_isa_s(Structure): - pass - -struct_hsa_isa_s._pack_ = 1 # source:False -struct_hsa_isa_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_isa_t = struct_hsa_isa_s -try: - hsa_isa_from_name = _libraries['libhsa-runtime64.so'].hsa_isa_from_name - hsa_isa_from_name.restype = hsa_status_t - hsa_isa_from_name.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_isa_s)] -except AttributeError: - pass -try: - hsa_agent_iterate_isas = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_isas - hsa_agent_iterate_isas.restype = hsa_status_t - hsa_agent_iterate_isas.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_isa_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_isa_info_t' -c__EA_hsa_isa_info_t__enumvalues = { - 0: 'HSA_ISA_INFO_NAME_LENGTH', - 1: 'HSA_ISA_INFO_NAME', - 2: 'HSA_ISA_INFO_CALL_CONVENTION_COUNT', - 3: 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE', - 4: 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT', - 5: 'HSA_ISA_INFO_MACHINE_MODELS', - 6: 'HSA_ISA_INFO_PROFILES', - 7: 'HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES', - 8: 'HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 9: 'HSA_ISA_INFO_FAST_F16_OPERATION', - 12: 'HSA_ISA_INFO_WORKGROUP_MAX_DIM', - 13: 'HSA_ISA_INFO_WORKGROUP_MAX_SIZE', - 14: 'HSA_ISA_INFO_GRID_MAX_DIM', - 16: 'HSA_ISA_INFO_GRID_MAX_SIZE', - 17: 'HSA_ISA_INFO_FBARRIER_MAX_SIZE', -} -HSA_ISA_INFO_NAME_LENGTH = 0 -HSA_ISA_INFO_NAME = 1 -HSA_ISA_INFO_CALL_CONVENTION_COUNT = 2 -HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE = 3 -HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT = 4 -HSA_ISA_INFO_MACHINE_MODELS = 5 -HSA_ISA_INFO_PROFILES = 6 -HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES = 7 -HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = 8 -HSA_ISA_INFO_FAST_F16_OPERATION = 9 -HSA_ISA_INFO_WORKGROUP_MAX_DIM = 12 -HSA_ISA_INFO_WORKGROUP_MAX_SIZE = 13 -HSA_ISA_INFO_GRID_MAX_DIM = 14 -HSA_ISA_INFO_GRID_MAX_SIZE = 16 -HSA_ISA_INFO_FBARRIER_MAX_SIZE = 17 -c__EA_hsa_isa_info_t = ctypes.c_uint32 # enum -hsa_isa_info_t = c__EA_hsa_isa_info_t -hsa_isa_info_t__enumvalues = c__EA_hsa_isa_info_t__enumvalues -try: - hsa_isa_get_info = _libraries['libhsa-runtime64.so'].hsa_isa_get_info - hsa_isa_get_info.restype = hsa_status_t - hsa_isa_get_info.argtypes = [hsa_isa_t, hsa_isa_info_t, uint32_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_get_info_alt = _libraries['libhsa-runtime64.so'].hsa_isa_get_info_alt - hsa_isa_get_info_alt.restype = hsa_status_t - hsa_isa_get_info_alt.argtypes = [hsa_isa_t, hsa_isa_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_get_exception_policies = _libraries['libhsa-runtime64.so'].hsa_isa_get_exception_policies - hsa_isa_get_exception_policies.restype = hsa_status_t - hsa_isa_get_exception_policies.argtypes = [hsa_isa_t, hsa_profile_t, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_fp_type_t' -c__EA_hsa_fp_type_t__enumvalues = { - 1: 'HSA_FP_TYPE_16', - 2: 'HSA_FP_TYPE_32', - 4: 'HSA_FP_TYPE_64', -} -HSA_FP_TYPE_16 = 1 -HSA_FP_TYPE_32 = 2 -HSA_FP_TYPE_64 = 4 -c__EA_hsa_fp_type_t = ctypes.c_uint32 # enum -hsa_fp_type_t = c__EA_hsa_fp_type_t -hsa_fp_type_t__enumvalues = c__EA_hsa_fp_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_flush_mode_t' -c__EA_hsa_flush_mode_t__enumvalues = { - 1: 'HSA_FLUSH_MODE_FTZ', - 2: 'HSA_FLUSH_MODE_NON_FTZ', -} -HSA_FLUSH_MODE_FTZ = 1 -HSA_FLUSH_MODE_NON_FTZ = 2 -c__EA_hsa_flush_mode_t = ctypes.c_uint32 # enum -hsa_flush_mode_t = c__EA_hsa_flush_mode_t -hsa_flush_mode_t__enumvalues = c__EA_hsa_flush_mode_t__enumvalues - -# values for enumeration 'c__EA_hsa_round_method_t' -c__EA_hsa_round_method_t__enumvalues = { - 1: 'HSA_ROUND_METHOD_SINGLE', - 2: 'HSA_ROUND_METHOD_DOUBLE', -} -HSA_ROUND_METHOD_SINGLE = 1 -HSA_ROUND_METHOD_DOUBLE = 2 -c__EA_hsa_round_method_t = ctypes.c_uint32 # enum -hsa_round_method_t = c__EA_hsa_round_method_t -hsa_round_method_t__enumvalues = c__EA_hsa_round_method_t__enumvalues -try: - hsa_isa_get_round_method = _libraries['libhsa-runtime64.so'].hsa_isa_get_round_method - hsa_isa_get_round_method.restype = hsa_status_t - hsa_isa_get_round_method.argtypes = [hsa_isa_t, hsa_fp_type_t, hsa_flush_mode_t, ctypes.POINTER(c__EA_hsa_round_method_t)] -except AttributeError: - pass -class struct_hsa_wavefront_s(Structure): - pass - -struct_hsa_wavefront_s._pack_ = 1 # source:False -struct_hsa_wavefront_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_wavefront_t = struct_hsa_wavefront_s - -# values for enumeration 'c__EA_hsa_wavefront_info_t' -c__EA_hsa_wavefront_info_t__enumvalues = { - 0: 'HSA_WAVEFRONT_INFO_SIZE', -} -HSA_WAVEFRONT_INFO_SIZE = 0 -c__EA_hsa_wavefront_info_t = ctypes.c_uint32 # enum -hsa_wavefront_info_t = c__EA_hsa_wavefront_info_t -hsa_wavefront_info_t__enumvalues = c__EA_hsa_wavefront_info_t__enumvalues -try: - hsa_wavefront_get_info = _libraries['libhsa-runtime64.so'].hsa_wavefront_get_info - hsa_wavefront_get_info.restype = hsa_status_t - hsa_wavefront_get_info.argtypes = [hsa_wavefront_t, hsa_wavefront_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_iterate_wavefronts = _libraries['libhsa-runtime64.so'].hsa_isa_iterate_wavefronts - hsa_isa_iterate_wavefronts.restype = hsa_status_t - hsa_isa_iterate_wavefronts.argtypes = [hsa_isa_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_wavefront_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_compatible = _libraries['libhsa-runtime64.so'].hsa_isa_compatible - hsa_isa_compatible.restype = hsa_status_t - hsa_isa_compatible.argtypes = [hsa_isa_t, hsa_isa_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -class struct_hsa_code_object_reader_s(Structure): - pass - -struct_hsa_code_object_reader_s._pack_ = 1 # source:False -struct_hsa_code_object_reader_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_code_object_reader_t = struct_hsa_code_object_reader_s -try: - hsa_code_object_reader_create_from_file = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_create_from_file - hsa_code_object_reader_create_from_file.restype = hsa_status_t - hsa_code_object_reader_create_from_file.argtypes = [hsa_file_t, ctypes.POINTER(struct_hsa_code_object_reader_s)] -except AttributeError: - pass -try: - hsa_code_object_reader_create_from_memory = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_create_from_memory - hsa_code_object_reader_create_from_memory.restype = hsa_status_t - hsa_code_object_reader_create_from_memory.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_code_object_reader_s)] -except AttributeError: - pass -try: - hsa_code_object_reader_destroy = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_destroy - hsa_code_object_reader_destroy.restype = hsa_status_t - hsa_code_object_reader_destroy.argtypes = [hsa_code_object_reader_t] -except AttributeError: - pass -class struct_hsa_executable_s(Structure): - pass - -struct_hsa_executable_s._pack_ = 1 # source:False -struct_hsa_executable_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_executable_t = struct_hsa_executable_s - -# values for enumeration 'c__EA_hsa_executable_state_t' -c__EA_hsa_executable_state_t__enumvalues = { - 0: 'HSA_EXECUTABLE_STATE_UNFROZEN', - 1: 'HSA_EXECUTABLE_STATE_FROZEN', -} -HSA_EXECUTABLE_STATE_UNFROZEN = 0 -HSA_EXECUTABLE_STATE_FROZEN = 1 -c__EA_hsa_executable_state_t = ctypes.c_uint32 # enum -hsa_executable_state_t = c__EA_hsa_executable_state_t -hsa_executable_state_t__enumvalues = c__EA_hsa_executable_state_t__enumvalues -try: - hsa_executable_create = _libraries['libhsa-runtime64.so'].hsa_executable_create - hsa_executable_create.restype = hsa_status_t - hsa_executable_create.argtypes = [hsa_profile_t, hsa_executable_state_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_executable_s)] -except AttributeError: - pass -try: - hsa_executable_create_alt = _libraries['libhsa-runtime64.so'].hsa_executable_create_alt - hsa_executable_create_alt.restype = hsa_status_t - hsa_executable_create_alt.argtypes = [hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_executable_s)] -except AttributeError: - pass -try: - hsa_executable_destroy = _libraries['libhsa-runtime64.so'].hsa_executable_destroy - hsa_executable_destroy.restype = hsa_status_t - hsa_executable_destroy.argtypes = [hsa_executable_t] -except AttributeError: - pass -class struct_hsa_loaded_code_object_s(Structure): - pass - -struct_hsa_loaded_code_object_s._pack_ = 1 # source:False -struct_hsa_loaded_code_object_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_loaded_code_object_t = struct_hsa_loaded_code_object_s -try: - hsa_executable_load_program_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_program_code_object - hsa_executable_load_program_code_object.restype = hsa_status_t - hsa_executable_load_program_code_object.argtypes = [hsa_executable_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_loaded_code_object_s)] -except AttributeError: - pass -try: - hsa_executable_load_agent_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_agent_code_object - hsa_executable_load_agent_code_object.restype = hsa_status_t - hsa_executable_load_agent_code_object.argtypes = [hsa_executable_t, hsa_agent_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_loaded_code_object_s)] -except AttributeError: - pass -try: - hsa_executable_freeze = _libraries['libhsa-runtime64.so'].hsa_executable_freeze - hsa_executable_freeze.restype = hsa_status_t - hsa_executable_freeze.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_executable_info_t' -c__EA_hsa_executable_info_t__enumvalues = { - 1: 'HSA_EXECUTABLE_INFO_PROFILE', - 2: 'HSA_EXECUTABLE_INFO_STATE', - 3: 'HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_EXECUTABLE_INFO_PROFILE = 1 -HSA_EXECUTABLE_INFO_STATE = 2 -HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 3 -c__EA_hsa_executable_info_t = ctypes.c_uint32 # enum -hsa_executable_info_t = c__EA_hsa_executable_info_t -hsa_executable_info_t__enumvalues = c__EA_hsa_executable_info_t__enumvalues -try: - hsa_executable_get_info = _libraries['libhsa-runtime64.so'].hsa_executable_get_info - hsa_executable_get_info.restype = hsa_status_t - hsa_executable_get_info.argtypes = [hsa_executable_t, hsa_executable_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_global_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_global_variable_define - hsa_executable_global_variable_define.restype = hsa_status_t - hsa_executable_global_variable_define.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_agent_global_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_agent_global_variable_define - hsa_executable_agent_global_variable_define.restype = hsa_status_t - hsa_executable_agent_global_variable_define.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_readonly_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_readonly_variable_define - hsa_executable_readonly_variable_define.restype = hsa_status_t - hsa_executable_readonly_variable_define.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_validate = _libraries['libhsa-runtime64.so'].hsa_executable_validate - hsa_executable_validate.restype = hsa_status_t - hsa_executable_validate.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_executable_validate_alt = _libraries['libhsa-runtime64.so'].hsa_executable_validate_alt - hsa_executable_validate_alt.restype = hsa_status_t - hsa_executable_validate_alt.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_executable_symbol_s(Structure): - pass - -struct_hsa_executable_symbol_s._pack_ = 1 # source:False -struct_hsa_executable_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_executable_symbol_t = struct_hsa_executable_symbol_s -int32_t = ctypes.c_int32 -try: - hsa_executable_get_symbol = _libraries['libhsa-runtime64.so'].hsa_executable_get_symbol - hsa_executable_get_symbol.restype = hsa_status_t - hsa_executable_get_symbol.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), hsa_agent_t, int32_t, ctypes.POINTER(struct_hsa_executable_symbol_s)] -except AttributeError: - pass -try: - hsa_executable_get_symbol_by_name = _libraries['libhsa-runtime64.so'].hsa_executable_get_symbol_by_name - hsa_executable_get_symbol_by_name.restype = hsa_status_t - hsa_executable_get_symbol_by_name.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_executable_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_symbol_kind_t' -c__EA_hsa_symbol_kind_t__enumvalues = { - 0: 'HSA_SYMBOL_KIND_VARIABLE', - 1: 'HSA_SYMBOL_KIND_KERNEL', - 2: 'HSA_SYMBOL_KIND_INDIRECT_FUNCTION', -} -HSA_SYMBOL_KIND_VARIABLE = 0 -HSA_SYMBOL_KIND_KERNEL = 1 -HSA_SYMBOL_KIND_INDIRECT_FUNCTION = 2 -c__EA_hsa_symbol_kind_t = ctypes.c_uint32 # enum -hsa_symbol_kind_t = c__EA_hsa_symbol_kind_t -hsa_symbol_kind_t__enumvalues = c__EA_hsa_symbol_kind_t__enumvalues - -# values for enumeration 'c__EA_hsa_symbol_linkage_t' -c__EA_hsa_symbol_linkage_t__enumvalues = { - 0: 'HSA_SYMBOL_LINKAGE_MODULE', - 1: 'HSA_SYMBOL_LINKAGE_PROGRAM', -} -HSA_SYMBOL_LINKAGE_MODULE = 0 -HSA_SYMBOL_LINKAGE_PROGRAM = 1 -c__EA_hsa_symbol_linkage_t = ctypes.c_uint32 # enum -hsa_symbol_linkage_t = c__EA_hsa_symbol_linkage_t -hsa_symbol_linkage_t__enumvalues = c__EA_hsa_symbol_linkage_t__enumvalues - -# values for enumeration 'c__EA_hsa_variable_allocation_t' -c__EA_hsa_variable_allocation_t__enumvalues = { - 0: 'HSA_VARIABLE_ALLOCATION_AGENT', - 1: 'HSA_VARIABLE_ALLOCATION_PROGRAM', -} -HSA_VARIABLE_ALLOCATION_AGENT = 0 -HSA_VARIABLE_ALLOCATION_PROGRAM = 1 -c__EA_hsa_variable_allocation_t = ctypes.c_uint32 # enum -hsa_variable_allocation_t = c__EA_hsa_variable_allocation_t -hsa_variable_allocation_t__enumvalues = c__EA_hsa_variable_allocation_t__enumvalues - -# values for enumeration 'c__EA_hsa_variable_segment_t' -c__EA_hsa_variable_segment_t__enumvalues = { - 0: 'HSA_VARIABLE_SEGMENT_GLOBAL', - 1: 'HSA_VARIABLE_SEGMENT_READONLY', -} -HSA_VARIABLE_SEGMENT_GLOBAL = 0 -HSA_VARIABLE_SEGMENT_READONLY = 1 -c__EA_hsa_variable_segment_t = ctypes.c_uint32 # enum -hsa_variable_segment_t = c__EA_hsa_variable_segment_t -hsa_variable_segment_t__enumvalues = c__EA_hsa_variable_segment_t__enumvalues - -# values for enumeration 'c__EA_hsa_executable_symbol_info_t' -c__EA_hsa_executable_symbol_info_t__enumvalues = { - 0: 'HSA_EXECUTABLE_SYMBOL_INFO_TYPE', - 1: 'HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH', - 2: 'HSA_EXECUTABLE_SYMBOL_INFO_NAME', - 3: 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 4: 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME', - 20: 'HSA_EXECUTABLE_SYMBOL_INFO_AGENT', - 21: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS', - 5: 'HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE', - 17: 'HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION', - 6: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 7: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT', - 8: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 9: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE', - 10: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST', - 22: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT', - 11: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 12: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 13: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 14: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 15: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 18: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 23: 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT', - 16: 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', -} -HSA_EXECUTABLE_SYMBOL_INFO_TYPE = 0 -HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH = 1 -HSA_EXECUTABLE_SYMBOL_INFO_NAME = 2 -HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3 -HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME = 4 -HSA_EXECUTABLE_SYMBOL_INFO_AGENT = 20 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS = 21 -HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE = 5 -HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION = 17 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT = 7 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE = 9 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST = 10 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT = 22 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = 18 -HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT = 23 -HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 -c__EA_hsa_executable_symbol_info_t = ctypes.c_uint32 # enum -hsa_executable_symbol_info_t = c__EA_hsa_executable_symbol_info_t -hsa_executable_symbol_info_t__enumvalues = c__EA_hsa_executable_symbol_info_t__enumvalues -try: - hsa_executable_symbol_get_info = _libraries['libhsa-runtime64.so'].hsa_executable_symbol_get_info - hsa_executable_symbol_get_info.restype = hsa_status_t - hsa_executable_symbol_get_info.argtypes = [hsa_executable_symbol_t, hsa_executable_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_symbols - hsa_executable_iterate_symbols.restype = hsa_status_t - hsa_executable_iterate_symbols.argtypes = [hsa_executable_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_agent_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_agent_symbols - hsa_executable_iterate_agent_symbols.restype = hsa_status_t - hsa_executable_iterate_agent_symbols.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_agent_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_program_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_program_symbols - hsa_executable_iterate_program_symbols.restype = hsa_status_t - hsa_executable_iterate_program_symbols.argtypes = [hsa_executable_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_code_object_s(Structure): - pass - -struct_hsa_code_object_s._pack_ = 1 # source:False -struct_hsa_code_object_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_code_object_t = struct_hsa_code_object_s -class struct_hsa_callback_data_s(Structure): - pass - -struct_hsa_callback_data_s._pack_ = 1 # source:False -struct_hsa_callback_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_callback_data_t = struct_hsa_callback_data_s -try: - hsa_code_object_serialize = _libraries['libhsa-runtime64.so'].hsa_code_object_serialize - hsa_code_object_serialize.restype = hsa_status_t - hsa_code_object_serialize.argtypes = [hsa_code_object_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_uint64, struct_hsa_callback_data_s, ctypes.POINTER(ctypes.POINTER(None))), hsa_callback_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hsa_code_object_deserialize = _libraries['libhsa-runtime64.so'].hsa_code_object_deserialize - hsa_code_object_deserialize.restype = hsa_status_t - hsa_code_object_deserialize.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_object_s)] -except AttributeError: - pass -try: - hsa_code_object_destroy = _libraries['libhsa-runtime64.so'].hsa_code_object_destroy - hsa_code_object_destroy.restype = hsa_status_t - hsa_code_object_destroy.argtypes = [hsa_code_object_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_code_object_type_t' -c__EA_hsa_code_object_type_t__enumvalues = { - 0: 'HSA_CODE_OBJECT_TYPE_PROGRAM', -} -HSA_CODE_OBJECT_TYPE_PROGRAM = 0 -c__EA_hsa_code_object_type_t = ctypes.c_uint32 # enum -hsa_code_object_type_t = c__EA_hsa_code_object_type_t -hsa_code_object_type_t__enumvalues = c__EA_hsa_code_object_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_code_object_info_t' -c__EA_hsa_code_object_info_t__enumvalues = { - 0: 'HSA_CODE_OBJECT_INFO_VERSION', - 1: 'HSA_CODE_OBJECT_INFO_TYPE', - 2: 'HSA_CODE_OBJECT_INFO_ISA', - 3: 'HSA_CODE_OBJECT_INFO_MACHINE_MODEL', - 4: 'HSA_CODE_OBJECT_INFO_PROFILE', - 5: 'HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_CODE_OBJECT_INFO_VERSION = 0 -HSA_CODE_OBJECT_INFO_TYPE = 1 -HSA_CODE_OBJECT_INFO_ISA = 2 -HSA_CODE_OBJECT_INFO_MACHINE_MODEL = 3 -HSA_CODE_OBJECT_INFO_PROFILE = 4 -HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5 -c__EA_hsa_code_object_info_t = ctypes.c_uint32 # enum -hsa_code_object_info_t = c__EA_hsa_code_object_info_t -hsa_code_object_info_t__enumvalues = c__EA_hsa_code_object_info_t__enumvalues -try: - hsa_code_object_get_info = _libraries['libhsa-runtime64.so'].hsa_code_object_get_info - hsa_code_object_get_info.restype = hsa_status_t - hsa_code_object_get_info.argtypes = [hsa_code_object_t, hsa_code_object_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_load_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_code_object - hsa_executable_load_code_object.restype = hsa_status_t - hsa_executable_load_code_object.argtypes = [hsa_executable_t, hsa_agent_t, hsa_code_object_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_hsa_code_symbol_s(Structure): - pass - -struct_hsa_code_symbol_s._pack_ = 1 # source:False -struct_hsa_code_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_code_symbol_t = struct_hsa_code_symbol_s -try: - hsa_code_object_get_symbol = _libraries['libhsa-runtime64.so'].hsa_code_object_get_symbol - hsa_code_object_get_symbol.restype = hsa_status_t - hsa_code_object_get_symbol.argtypes = [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_symbol_s)] -except AttributeError: - pass -try: - hsa_code_object_get_symbol_from_name = _libraries['libhsa-runtime64.so'].hsa_code_object_get_symbol_from_name - hsa_code_object_get_symbol_from_name.restype = hsa_status_t - hsa_code_object_get_symbol_from_name.argtypes = [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_code_symbol_info_t' -c__EA_hsa_code_symbol_info_t__enumvalues = { - 0: 'HSA_CODE_SYMBOL_INFO_TYPE', - 1: 'HSA_CODE_SYMBOL_INFO_NAME_LENGTH', - 2: 'HSA_CODE_SYMBOL_INFO_NAME', - 3: 'HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 4: 'HSA_CODE_SYMBOL_INFO_MODULE_NAME', - 5: 'HSA_CODE_SYMBOL_INFO_LINKAGE', - 17: 'HSA_CODE_SYMBOL_INFO_IS_DEFINITION', - 6: 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 7: 'HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT', - 8: 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 9: 'HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE', - 10: 'HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST', - 11: 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 12: 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 13: 'HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 14: 'HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 15: 'HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 18: 'HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 16: 'HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 19: 'HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE', -} -HSA_CODE_SYMBOL_INFO_TYPE = 0 -HSA_CODE_SYMBOL_INFO_NAME_LENGTH = 1 -HSA_CODE_SYMBOL_INFO_NAME = 2 -HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3 -HSA_CODE_SYMBOL_INFO_MODULE_NAME = 4 -HSA_CODE_SYMBOL_INFO_LINKAGE = 5 -HSA_CODE_SYMBOL_INFO_IS_DEFINITION = 17 -HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6 -HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT = 7 -HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8 -HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE = 9 -HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST = 10 -HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11 -HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12 -HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13 -HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14 -HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15 -HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = 18 -HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 -HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE = 19 -c__EA_hsa_code_symbol_info_t = ctypes.c_uint32 # enum -hsa_code_symbol_info_t = c__EA_hsa_code_symbol_info_t -hsa_code_symbol_info_t__enumvalues = c__EA_hsa_code_symbol_info_t__enumvalues -try: - hsa_code_symbol_get_info = _libraries['libhsa-runtime64.so'].hsa_code_symbol_get_info - hsa_code_symbol_get_info.restype = hsa_status_t - hsa_code_symbol_get_info.argtypes = [hsa_code_symbol_t, hsa_code_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_code_object_iterate_symbols = _libraries['libhsa-runtime64.so'].hsa_code_object_iterate_symbols - hsa_code_object_iterate_symbols.restype = hsa_status_t - hsa_code_object_iterate_symbols.argtypes = [hsa_code_object_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_code_object_s, struct_hsa_code_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED' -c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED__enumvalues = { - 12288: 'HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 12289: 'HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED', - 12290: 'HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED', - 12291: 'HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED', -} -HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED = 12288 -HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED = 12289 -HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED = 12290 -HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED = 12291 -c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS' -c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS__enumvalues = { - 12288: 'HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 12289: 'HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS', - 12290: 'HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS', - 12291: 'HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS', - 12292: 'HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS', - 12293: 'HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS', - 12294: 'HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS', - 12295: 'HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS', - 12296: 'HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS', - 12297: 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES', - 12298: 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES', - 12299: 'HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS', - 12300: 'HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT', -} -HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS = 12288 -HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS = 12289 -HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS = 12290 -HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS = 12291 -HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS = 12292 -HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS = 12293 -HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS = 12294 -HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS = 12295 -HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS = 12296 -HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES = 12297 -HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES = 12298 -HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS = 12299 -HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT = 12300 -c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS = ctypes.c_uint32 # enum -class struct_hsa_ext_image_s(Structure): - pass - -struct_hsa_ext_image_s._pack_ = 1 # source:False -struct_hsa_ext_image_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_ext_image_t = struct_hsa_ext_image_s - -# values for enumeration 'c__EA_hsa_ext_image_geometry_t' -c__EA_hsa_ext_image_geometry_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_GEOMETRY_1D', - 1: 'HSA_EXT_IMAGE_GEOMETRY_2D', - 2: 'HSA_EXT_IMAGE_GEOMETRY_3D', - 3: 'HSA_EXT_IMAGE_GEOMETRY_1DA', - 4: 'HSA_EXT_IMAGE_GEOMETRY_2DA', - 5: 'HSA_EXT_IMAGE_GEOMETRY_1DB', - 6: 'HSA_EXT_IMAGE_GEOMETRY_2DDEPTH', - 7: 'HSA_EXT_IMAGE_GEOMETRY_2DADEPTH', -} -HSA_EXT_IMAGE_GEOMETRY_1D = 0 -HSA_EXT_IMAGE_GEOMETRY_2D = 1 -HSA_EXT_IMAGE_GEOMETRY_3D = 2 -HSA_EXT_IMAGE_GEOMETRY_1DA = 3 -HSA_EXT_IMAGE_GEOMETRY_2DA = 4 -HSA_EXT_IMAGE_GEOMETRY_1DB = 5 -HSA_EXT_IMAGE_GEOMETRY_2DDEPTH = 6 -HSA_EXT_IMAGE_GEOMETRY_2DADEPTH = 7 -c__EA_hsa_ext_image_geometry_t = ctypes.c_uint32 # enum -hsa_ext_image_geometry_t = c__EA_hsa_ext_image_geometry_t -hsa_ext_image_geometry_t__enumvalues = c__EA_hsa_ext_image_geometry_t__enumvalues - -# values for enumeration 'c__EA_hsa_ext_image_channel_type_t' -c__EA_hsa_ext_image_channel_type_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8', - 1: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16', - 2: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8', - 3: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16', - 4: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24', - 5: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555', - 6: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565', - 7: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010', - 8: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8', - 9: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16', - 10: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32', - 11: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8', - 12: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16', - 13: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32', - 14: 'HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT', - 15: 'HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT', -} -HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0 -HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555 = 5 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565 = 6 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010 = 7 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13 -HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14 -HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT = 15 -c__EA_hsa_ext_image_channel_type_t = ctypes.c_uint32 # enum -hsa_ext_image_channel_type_t = c__EA_hsa_ext_image_channel_type_t -hsa_ext_image_channel_type_t__enumvalues = c__EA_hsa_ext_image_channel_type_t__enumvalues -hsa_ext_image_channel_type32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_image_channel_order_t' -c__EA_hsa_ext_image_channel_order_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CHANNEL_ORDER_A', - 1: 'HSA_EXT_IMAGE_CHANNEL_ORDER_R', - 2: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RX', - 3: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RG', - 4: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGX', - 5: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RA', - 6: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGB', - 7: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX', - 8: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA', - 9: 'HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA', - 10: 'HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB', - 11: 'HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR', - 12: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB', - 13: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX', - 14: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA', - 15: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA', - 16: 'HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY', - 17: 'HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE', - 18: 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH', - 19: 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL', -} -HSA_EXT_IMAGE_CHANNEL_ORDER_A = 0 -HSA_EXT_IMAGE_CHANNEL_ORDER_R = 1 -HSA_EXT_IMAGE_CHANNEL_ORDER_RX = 2 -HSA_EXT_IMAGE_CHANNEL_ORDER_RG = 3 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGX = 4 -HSA_EXT_IMAGE_CHANNEL_ORDER_RA = 5 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGB = 6 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX = 7 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA = 8 -HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA = 9 -HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB = 10 -HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR = 11 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB = 12 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX = 13 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA = 14 -HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA = 15 -HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY = 16 -HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE = 17 -HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH = 18 -HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19 -c__EA_hsa_ext_image_channel_order_t = ctypes.c_uint32 # enum -hsa_ext_image_channel_order_t = c__EA_hsa_ext_image_channel_order_t -hsa_ext_image_channel_order_t__enumvalues = c__EA_hsa_ext_image_channel_order_t__enumvalues -hsa_ext_image_channel_order32_t = ctypes.c_uint32 -class struct_hsa_ext_image_format_s(Structure): - pass - -struct_hsa_ext_image_format_s._pack_ = 1 # source:False -struct_hsa_ext_image_format_s._fields_ = [ - ('channel_type', ctypes.c_uint32), - ('channel_order', ctypes.c_uint32), -] - -hsa_ext_image_format_t = struct_hsa_ext_image_format_s -class struct_hsa_ext_image_descriptor_s(Structure): - pass - -struct_hsa_ext_image_descriptor_s._pack_ = 1 # source:False -struct_hsa_ext_image_descriptor_s._fields_ = [ - ('geometry', hsa_ext_image_geometry_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('array_size', ctypes.c_uint64), - ('format', hsa_ext_image_format_t), -] - -hsa_ext_image_descriptor_t = struct_hsa_ext_image_descriptor_s - -# values for enumeration 'c__EA_hsa_ext_image_capability_t' -c__EA_hsa_ext_image_capability_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED', - 1: 'HSA_EXT_IMAGE_CAPABILITY_READ_ONLY', - 2: 'HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY', - 4: 'HSA_EXT_IMAGE_CAPABILITY_READ_WRITE', - 8: 'HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE', - 16: 'HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT', -} -HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED = 0 -HSA_EXT_IMAGE_CAPABILITY_READ_ONLY = 1 -HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY = 2 -HSA_EXT_IMAGE_CAPABILITY_READ_WRITE = 4 -HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE = 8 -HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT = 16 -c__EA_hsa_ext_image_capability_t = ctypes.c_uint32 # enum -hsa_ext_image_capability_t = c__EA_hsa_ext_image_capability_t -hsa_ext_image_capability_t__enumvalues = c__EA_hsa_ext_image_capability_t__enumvalues - -# values for enumeration 'c__EA_hsa_ext_image_data_layout_t' -c__EA_hsa_ext_image_data_layout_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE', - 1: 'HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR', -} -HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE = 0 -HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR = 1 -c__EA_hsa_ext_image_data_layout_t = ctypes.c_uint32 # enum -hsa_ext_image_data_layout_t = c__EA_hsa_ext_image_data_layout_t -hsa_ext_image_data_layout_t__enumvalues = c__EA_hsa_ext_image_data_layout_t__enumvalues -try: - hsa_ext_image_get_capability = _libraries['libhsa-runtime64.so'].hsa_ext_image_get_capability - hsa_ext_image_get_capability.restype = hsa_status_t - hsa_ext_image_get_capability.argtypes = [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_ext_image_get_capability_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_get_capability_with_layout - hsa_ext_image_get_capability_with_layout.restype = hsa_status_t - hsa_ext_image_get_capability_with_layout.argtypes = [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), hsa_ext_image_data_layout_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_ext_image_data_info_s(Structure): - pass - -struct_hsa_ext_image_data_info_s._pack_ = 1 # source:False -struct_hsa_ext_image_data_info_s._fields_ = [ - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), -] - -hsa_ext_image_data_info_t = struct_hsa_ext_image_data_info_s -try: - hsa_ext_image_data_get_info = _libraries['libhsa-runtime64.so'].hsa_ext_image_data_get_info - hsa_ext_image_data_get_info.restype = hsa_status_t - hsa_ext_image_data_get_info.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s)] -except AttributeError: - pass -try: - hsa_ext_image_data_get_info_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_data_get_info_with_layout - hsa_ext_image_data_get_info_with_layout.restype = hsa_status_t - hsa_ext_image_data_get_info_with_layout.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s)] -except AttributeError: - pass -try: - hsa_ext_image_create = _libraries['libhsa-runtime64.so'].hsa_ext_image_create - hsa_ext_image_create.restype = hsa_status_t - hsa_ext_image_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass -try: - hsa_ext_image_create_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_create_with_layout - hsa_ext_image_create_with_layout.restype = hsa_status_t - hsa_ext_image_create_with_layout.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass -try: - hsa_ext_image_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_image_destroy - hsa_ext_image_destroy.restype = hsa_status_t - hsa_ext_image_destroy.argtypes = [hsa_agent_t, hsa_ext_image_t] -except AttributeError: - pass -try: - hsa_ext_image_copy = _libraries['libhsa-runtime64.so'].hsa_ext_image_copy - hsa_ext_image_copy.restype = hsa_status_t - hsa_ext_image_copy.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(struct_hsa_dim3_s), hsa_ext_image_t, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s)] -except AttributeError: - pass -class struct_hsa_ext_image_region_s(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('offset', hsa_dim3_t), - ('range', hsa_dim3_t), - ] - -hsa_ext_image_region_t = struct_hsa_ext_image_region_s -try: - hsa_ext_image_import = _libraries['libhsa-runtime64.so'].hsa_ext_image_import - hsa_ext_image_import.restype = hsa_status_t - hsa_ext_image_import.argtypes = [hsa_agent_t, ctypes.POINTER(None), size_t, size_t, hsa_ext_image_t, ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -try: - hsa_ext_image_export = _libraries['libhsa-runtime64.so'].hsa_ext_image_export - hsa_ext_image_export.restype = hsa_status_t - hsa_ext_image_export.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(None), size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -try: - hsa_ext_image_clear = _libraries['libhsa-runtime64.so'].hsa_ext_image_clear - hsa_ext_image_clear.restype = hsa_status_t - hsa_ext_image_clear.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -class struct_hsa_ext_sampler_s(Structure): - pass - -struct_hsa_ext_sampler_s._pack_ = 1 # source:False -struct_hsa_ext_sampler_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_ext_sampler_t = struct_hsa_ext_sampler_s - -# values for enumeration 'c__EA_hsa_ext_sampler_addressing_mode_t' -c__EA_hsa_ext_sampler_addressing_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED', - 1: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE', - 2: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER', - 3: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT', - 4: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT', -} -HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED = 0 -HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE = 1 -HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER = 2 -HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT = 3 -HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT = 4 -c__EA_hsa_ext_sampler_addressing_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_addressing_mode_t = c__EA_hsa_ext_sampler_addressing_mode_t -hsa_ext_sampler_addressing_mode_t__enumvalues = c__EA_hsa_ext_sampler_addressing_mode_t__enumvalues -hsa_ext_sampler_addressing_mode32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_sampler_coordinate_mode_t' -c__EA_hsa_ext_sampler_coordinate_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED', - 1: 'HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED', -} -HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED = 0 -HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED = 1 -c__EA_hsa_ext_sampler_coordinate_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_coordinate_mode_t = c__EA_hsa_ext_sampler_coordinate_mode_t -hsa_ext_sampler_coordinate_mode_t__enumvalues = c__EA_hsa_ext_sampler_coordinate_mode_t__enumvalues -hsa_ext_sampler_coordinate_mode32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_sampler_filter_mode_t' -c__EA_hsa_ext_sampler_filter_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_FILTER_MODE_NEAREST', - 1: 'HSA_EXT_SAMPLER_FILTER_MODE_LINEAR', -} -HSA_EXT_SAMPLER_FILTER_MODE_NEAREST = 0 -HSA_EXT_SAMPLER_FILTER_MODE_LINEAR = 1 -c__EA_hsa_ext_sampler_filter_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_filter_mode_t = c__EA_hsa_ext_sampler_filter_mode_t -hsa_ext_sampler_filter_mode_t__enumvalues = c__EA_hsa_ext_sampler_filter_mode_t__enumvalues -hsa_ext_sampler_filter_mode32_t = ctypes.c_uint32 -class struct_hsa_ext_sampler_descriptor_s(Structure): - pass - -struct_hsa_ext_sampler_descriptor_s._pack_ = 1 # source:False -struct_hsa_ext_sampler_descriptor_s._fields_ = [ - ('coordinate_mode', ctypes.c_uint32), - ('filter_mode', ctypes.c_uint32), - ('address_mode', ctypes.c_uint32), -] - -hsa_ext_sampler_descriptor_t = struct_hsa_ext_sampler_descriptor_s -try: - hsa_ext_sampler_create = _libraries['libhsa-runtime64.so'].hsa_ext_sampler_create - hsa_ext_sampler_create.restype = hsa_status_t - hsa_ext_sampler_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s)] -except AttributeError: - pass -try: - hsa_ext_sampler_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_sampler_destroy - hsa_ext_sampler_destroy.restype = hsa_status_t - hsa_ext_sampler_destroy.argtypes = [hsa_agent_t, hsa_ext_sampler_t] -except AttributeError: - pass -class struct_hsa_ext_images_1_00_pfn_s(Structure): - pass - -struct_hsa_ext_images_1_00_pfn_s._pack_ = 1 # source:False -struct_hsa_ext_images_1_00_pfn_s._fields_ = [ - ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s))), - ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s)), - ('hsa_ext_image_copy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s))), - ('hsa_ext_image_import', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_export', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_clear', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s))), - ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_sampler_s)), -] - -hsa_ext_images_1_00_pfn_t = struct_hsa_ext_images_1_00_pfn_s -class struct_hsa_ext_images_1_pfn_s(Structure): - pass - -struct_hsa_ext_images_1_pfn_s._pack_ = 1 # source:False -struct_hsa_ext_images_1_pfn_s._fields_ = [ - ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s))), - ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s)), - ('hsa_ext_image_copy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s))), - ('hsa_ext_image_import', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_export', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_clear', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s))), - ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_sampler_s)), - ('hsa_ext_image_get_capability_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), c__EA_hsa_ext_image_data_layout_t, ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, c__EA_hsa_ext_image_data_layout_t, ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, c__EA_hsa_ext_image_data_layout_t, ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_s))), -] - -hsa_ext_images_1_pfn_t = struct_hsa_ext_images_1_pfn_s -try: - hsa_flag_isset64 = _libraries['FIXME_STUB'].hsa_flag_isset64 - hsa_flag_isset64.restype = ctypes.c_bool - hsa_flag_isset64.argtypes = [ctypes.POINTER(ctypes.c_ubyte), uint32_t] -except AttributeError: - pass -hsa_signal_condition32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_amd_packet_type_t' -c__EA_hsa_amd_packet_type_t__enumvalues = { - 2: 'HSA_AMD_PACKET_TYPE_BARRIER_VALUE', -} -HSA_AMD_PACKET_TYPE_BARRIER_VALUE = 2 -c__EA_hsa_amd_packet_type_t = ctypes.c_uint32 # enum -hsa_amd_packet_type_t = c__EA_hsa_amd_packet_type_t -hsa_amd_packet_type_t__enumvalues = c__EA_hsa_amd_packet_type_t__enumvalues -hsa_amd_packet_type8_t = ctypes.c_ubyte -class struct_hsa_amd_packet_header_s(Structure): - pass - -struct_hsa_amd_packet_header_s._pack_ = 1 # source:False -struct_hsa_amd_packet_header_s._fields_ = [ - ('header', ctypes.c_uint16), - ('AmdFormat', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -hsa_amd_vendor_packet_header_t = struct_hsa_amd_packet_header_s -class struct_hsa_amd_barrier_value_packet_s(Structure): - pass - -struct_hsa_amd_barrier_value_packet_s._pack_ = 1 # source:False -struct_hsa_amd_barrier_value_packet_s._fields_ = [ - ('header', hsa_amd_vendor_packet_header_t), - ('reserved0', ctypes.c_uint32), - ('signal', hsa_signal_t), - ('value', ctypes.c_int64), - ('mask', ctypes.c_int64), - ('cond', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('reserved2', ctypes.c_uint64), - ('reserved3', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), -] - -hsa_amd_barrier_value_packet_t = struct_hsa_amd_barrier_value_packet_s - -# values for enumeration 'c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL' -c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL__enumvalues = { - 40: 'HSA_STATUS_ERROR_INVALID_MEMORY_POOL', - 41: 'HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION', - 42: 'HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION', - 43: 'HSA_STATUS_ERROR_MEMORY_FAULT', - 44: 'HSA_STATUS_CU_MASK_REDUCED', - 45: 'HSA_STATUS_ERROR_OUT_OF_REGISTERS', - 46: 'HSA_STATUS_ERROR_RESOURCE_BUSY', -} -HSA_STATUS_ERROR_INVALID_MEMORY_POOL = 40 -HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION = 41 -HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION = 42 -HSA_STATUS_ERROR_MEMORY_FAULT = 43 -HSA_STATUS_CU_MASK_REDUCED = 44 -HSA_STATUS_ERROR_OUT_OF_REGISTERS = 45 -HSA_STATUS_ERROR_RESOURCE_BUSY = 46 -c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL = ctypes.c_uint32 # enum - -# values for enumeration 'c__EA_hsa_amd_iommu_version_t' -c__EA_hsa_amd_iommu_version_t__enumvalues = { - 0: 'HSA_IOMMU_SUPPORT_NONE', - 1: 'HSA_IOMMU_SUPPORT_V2', -} -HSA_IOMMU_SUPPORT_NONE = 0 -HSA_IOMMU_SUPPORT_V2 = 1 -c__EA_hsa_amd_iommu_version_t = ctypes.c_uint32 # enum -hsa_amd_iommu_version_t = c__EA_hsa_amd_iommu_version_t -hsa_amd_iommu_version_t__enumvalues = c__EA_hsa_amd_iommu_version_t__enumvalues - -# values for enumeration 'hsa_amd_agent_info_s' -hsa_amd_agent_info_s__enumvalues = { - 40960: 'HSA_AMD_AGENT_INFO_CHIP_ID', - 40961: 'HSA_AMD_AGENT_INFO_CACHELINE_SIZE', - 40962: 'HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT', - 40963: 'HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY', - 40964: 'HSA_AMD_AGENT_INFO_DRIVER_NODE_ID', - 40965: 'HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS', - 40966: 'HSA_AMD_AGENT_INFO_BDFID', - 40967: 'HSA_AMD_AGENT_INFO_MEMORY_WIDTH', - 40968: 'HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY', - 40969: 'HSA_AMD_AGENT_INFO_PRODUCT_NAME', - 40970: 'HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU', - 40971: 'HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU', - 40972: 'HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES', - 40973: 'HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE', - 40974: 'HSA_AMD_AGENT_INFO_HDP_FLUSH', - 40975: 'HSA_AMD_AGENT_INFO_DOMAIN', - 40976: 'HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES', - 40977: 'HSA_AMD_AGENT_INFO_UUID', - 40978: 'HSA_AMD_AGENT_INFO_ASIC_REVISION', - 40979: 'HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS', - 40980: 'HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT', - 40981: 'HSA_AMD_AGENT_INFO_MEMORY_AVAIL', - 40982: 'HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY', - 41223: 'HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID', - 41224: 'HSA_AMD_AGENT_INFO_UCODE_VERSION', - 41225: 'HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION', - 41226: 'HSA_AMD_AGENT_INFO_NUM_SDMA_ENG', - 41227: 'HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG', - 41232: 'HSA_AMD_AGENT_INFO_IOMMU_SUPPORT', - 41233: 'HSA_AMD_AGENT_INFO_NUM_XCC', - 41234: 'HSA_AMD_AGENT_INFO_DRIVER_UID', - 41235: 'HSA_AMD_AGENT_INFO_NEAREST_CPU', - 41236: 'HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES', - 41237: 'HSA_AMD_AGENT_INFO_AQL_EXTENSIONS', -} -HSA_AMD_AGENT_INFO_CHIP_ID = 40960 -HSA_AMD_AGENT_INFO_CACHELINE_SIZE = 40961 -HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT = 40962 -HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY = 40963 -HSA_AMD_AGENT_INFO_DRIVER_NODE_ID = 40964 -HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS = 40965 -HSA_AMD_AGENT_INFO_BDFID = 40966 -HSA_AMD_AGENT_INFO_MEMORY_WIDTH = 40967 -HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY = 40968 -HSA_AMD_AGENT_INFO_PRODUCT_NAME = 40969 -HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU = 40970 -HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU = 40971 -HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES = 40972 -HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE = 40973 -HSA_AMD_AGENT_INFO_HDP_FLUSH = 40974 -HSA_AMD_AGENT_INFO_DOMAIN = 40975 -HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES = 40976 -HSA_AMD_AGENT_INFO_UUID = 40977 -HSA_AMD_AGENT_INFO_ASIC_REVISION = 40978 -HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS = 40979 -HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT = 40980 -HSA_AMD_AGENT_INFO_MEMORY_AVAIL = 40981 -HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY = 40982 -HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID = 41223 -HSA_AMD_AGENT_INFO_UCODE_VERSION = 41224 -HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION = 41225 -HSA_AMD_AGENT_INFO_NUM_SDMA_ENG = 41226 -HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG = 41227 -HSA_AMD_AGENT_INFO_IOMMU_SUPPORT = 41232 -HSA_AMD_AGENT_INFO_NUM_XCC = 41233 -HSA_AMD_AGENT_INFO_DRIVER_UID = 41234 -HSA_AMD_AGENT_INFO_NEAREST_CPU = 41235 -HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES = 41236 -HSA_AMD_AGENT_INFO_AQL_EXTENSIONS = 41237 -hsa_amd_agent_info_s = ctypes.c_uint32 # enum -hsa_amd_agent_info_t = hsa_amd_agent_info_s -hsa_amd_agent_info_t__enumvalues = hsa_amd_agent_info_s__enumvalues - -# values for enumeration 'hsa_amd_agent_memory_properties_s' -hsa_amd_agent_memory_properties_s__enumvalues = { - 1: 'HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU', -} -HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU = 1 -hsa_amd_agent_memory_properties_s = ctypes.c_uint32 # enum -hsa_amd_agent_memory_properties_t = hsa_amd_agent_memory_properties_s -hsa_amd_agent_memory_properties_t__enumvalues = hsa_amd_agent_memory_properties_s__enumvalues - -# values for enumeration 'hsa_amd_sdma_engine_id' -hsa_amd_sdma_engine_id__enumvalues = { - 1: 'HSA_AMD_SDMA_ENGINE_0', - 2: 'HSA_AMD_SDMA_ENGINE_1', - 4: 'HSA_AMD_SDMA_ENGINE_2', - 8: 'HSA_AMD_SDMA_ENGINE_3', - 16: 'HSA_AMD_SDMA_ENGINE_4', - 32: 'HSA_AMD_SDMA_ENGINE_5', - 64: 'HSA_AMD_SDMA_ENGINE_6', - 128: 'HSA_AMD_SDMA_ENGINE_7', - 256: 'HSA_AMD_SDMA_ENGINE_8', - 512: 'HSA_AMD_SDMA_ENGINE_9', - 1024: 'HSA_AMD_SDMA_ENGINE_10', - 2048: 'HSA_AMD_SDMA_ENGINE_11', - 4096: 'HSA_AMD_SDMA_ENGINE_12', - 8192: 'HSA_AMD_SDMA_ENGINE_13', - 16384: 'HSA_AMD_SDMA_ENGINE_14', - 32768: 'HSA_AMD_SDMA_ENGINE_15', -} -HSA_AMD_SDMA_ENGINE_0 = 1 -HSA_AMD_SDMA_ENGINE_1 = 2 -HSA_AMD_SDMA_ENGINE_2 = 4 -HSA_AMD_SDMA_ENGINE_3 = 8 -HSA_AMD_SDMA_ENGINE_4 = 16 -HSA_AMD_SDMA_ENGINE_5 = 32 -HSA_AMD_SDMA_ENGINE_6 = 64 -HSA_AMD_SDMA_ENGINE_7 = 128 -HSA_AMD_SDMA_ENGINE_8 = 256 -HSA_AMD_SDMA_ENGINE_9 = 512 -HSA_AMD_SDMA_ENGINE_10 = 1024 -HSA_AMD_SDMA_ENGINE_11 = 2048 -HSA_AMD_SDMA_ENGINE_12 = 4096 -HSA_AMD_SDMA_ENGINE_13 = 8192 -HSA_AMD_SDMA_ENGINE_14 = 16384 -HSA_AMD_SDMA_ENGINE_15 = 32768 -hsa_amd_sdma_engine_id = ctypes.c_uint32 # enum -hsa_amd_sdma_engine_id_t = hsa_amd_sdma_engine_id -hsa_amd_sdma_engine_id_t__enumvalues = hsa_amd_sdma_engine_id__enumvalues -class struct_hsa_amd_hdp_flush_s(Structure): - pass - -struct_hsa_amd_hdp_flush_s._pack_ = 1 # source:False -struct_hsa_amd_hdp_flush_s._fields_ = [ - ('HDP_MEM_FLUSH_CNTL', ctypes.POINTER(ctypes.c_uint32)), - ('HDP_REG_FLUSH_CNTL', ctypes.POINTER(ctypes.c_uint32)), -] - -hsa_amd_hdp_flush_t = struct_hsa_amd_hdp_flush_s - -# values for enumeration 'hsa_amd_region_info_s' -hsa_amd_region_info_s__enumvalues = { - 40960: 'HSA_AMD_REGION_INFO_HOST_ACCESSIBLE', - 40961: 'HSA_AMD_REGION_INFO_BASE', - 40962: 'HSA_AMD_REGION_INFO_BUS_WIDTH', - 40963: 'HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY', -} -HSA_AMD_REGION_INFO_HOST_ACCESSIBLE = 40960 -HSA_AMD_REGION_INFO_BASE = 40961 -HSA_AMD_REGION_INFO_BUS_WIDTH = 40962 -HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY = 40963 -hsa_amd_region_info_s = ctypes.c_uint32 # enum -hsa_amd_region_info_t = hsa_amd_region_info_s -hsa_amd_region_info_t__enumvalues = hsa_amd_region_info_s__enumvalues - -# values for enumeration 'hsa_amd_coherency_type_s' -hsa_amd_coherency_type_s__enumvalues = { - 0: 'HSA_AMD_COHERENCY_TYPE_COHERENT', - 1: 'HSA_AMD_COHERENCY_TYPE_NONCOHERENT', -} -HSA_AMD_COHERENCY_TYPE_COHERENT = 0 -HSA_AMD_COHERENCY_TYPE_NONCOHERENT = 1 -hsa_amd_coherency_type_s = ctypes.c_uint32 # enum -hsa_amd_coherency_type_t = hsa_amd_coherency_type_s -hsa_amd_coherency_type_t__enumvalues = hsa_amd_coherency_type_s__enumvalues -try: - hsa_amd_coherency_get_type = _libraries['libhsa-runtime64.so'].hsa_amd_coherency_get_type - hsa_amd_coherency_get_type.restype = hsa_status_t - hsa_amd_coherency_get_type.argtypes = [hsa_agent_t, ctypes.POINTER(hsa_amd_coherency_type_s)] -except AttributeError: - pass -try: - hsa_amd_coherency_set_type = _libraries['libhsa-runtime64.so'].hsa_amd_coherency_set_type - hsa_amd_coherency_set_type.restype = hsa_status_t - hsa_amd_coherency_set_type.argtypes = [hsa_agent_t, hsa_amd_coherency_type_t] -except AttributeError: - pass -class struct_hsa_amd_profiling_dispatch_time_s(Structure): - pass - -struct_hsa_amd_profiling_dispatch_time_s._pack_ = 1 # source:False -struct_hsa_amd_profiling_dispatch_time_s._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), -] - -hsa_amd_profiling_dispatch_time_t = struct_hsa_amd_profiling_dispatch_time_s -class struct_hsa_amd_profiling_async_copy_time_s(Structure): - pass - -struct_hsa_amd_profiling_async_copy_time_s._pack_ = 1 # source:False -struct_hsa_amd_profiling_async_copy_time_s._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), -] - -hsa_amd_profiling_async_copy_time_t = struct_hsa_amd_profiling_async_copy_time_s -try: - hsa_amd_profiling_set_profiler_enabled = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_set_profiler_enabled - hsa_amd_profiling_set_profiler_enabled.restype = hsa_status_t - hsa_amd_profiling_set_profiler_enabled.argtypes = [ctypes.POINTER(struct_hsa_queue_s), ctypes.c_int32] -except AttributeError: - pass -try: - hsa_amd_profiling_async_copy_enable = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_async_copy_enable - hsa_amd_profiling_async_copy_enable.restype = hsa_status_t - hsa_amd_profiling_async_copy_enable.argtypes = [ctypes.c_bool] -except AttributeError: - pass -try: - hsa_amd_profiling_get_dispatch_time = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_get_dispatch_time - hsa_amd_profiling_get_dispatch_time.restype = hsa_status_t - hsa_amd_profiling_get_dispatch_time.argtypes = [hsa_agent_t, hsa_signal_t, ctypes.POINTER(struct_hsa_amd_profiling_dispatch_time_s)] -except AttributeError: - pass -try: - hsa_amd_profiling_get_async_copy_time = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_get_async_copy_time - hsa_amd_profiling_get_async_copy_time.restype = hsa_status_t - hsa_amd_profiling_get_async_copy_time.argtypes = [hsa_signal_t, ctypes.POINTER(struct_hsa_amd_profiling_async_copy_time_s)] -except AttributeError: - pass -try: - hsa_amd_profiling_convert_tick_to_system_domain = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_convert_tick_to_system_domain - hsa_amd_profiling_convert_tick_to_system_domain.restype = hsa_status_t - hsa_amd_profiling_convert_tick_to_system_domain.argtypes = [hsa_agent_t, uint64_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_amd_signal_attribute_t' -c__EA_hsa_amd_signal_attribute_t__enumvalues = { - 1: 'HSA_AMD_SIGNAL_AMD_GPU_ONLY', - 2: 'HSA_AMD_SIGNAL_IPC', -} -HSA_AMD_SIGNAL_AMD_GPU_ONLY = 1 -HSA_AMD_SIGNAL_IPC = 2 -c__EA_hsa_amd_signal_attribute_t = ctypes.c_uint32 # enum -hsa_amd_signal_attribute_t = c__EA_hsa_amd_signal_attribute_t -hsa_amd_signal_attribute_t__enumvalues = c__EA_hsa_amd_signal_attribute_t__enumvalues -try: - hsa_amd_signal_create = _libraries['libhsa-runtime64.so'].hsa_amd_signal_create - hsa_amd_signal_create.restype = hsa_status_t - hsa_amd_signal_create.argtypes = [hsa_signal_value_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), uint64_t, ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass -try: - hsa_amd_signal_value_pointer = _libraries['libhsa-runtime64.so'].hsa_amd_signal_value_pointer - hsa_amd_signal_value_pointer.restype = hsa_status_t - hsa_amd_signal_value_pointer.argtypes = [hsa_signal_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_int64))] -except AttributeError: - pass -hsa_amd_signal_handler = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_int64, ctypes.POINTER(None)) -try: - hsa_amd_signal_async_handler = _libraries['libhsa-runtime64.so'].hsa_amd_signal_async_handler - hsa_amd_signal_async_handler.restype = hsa_status_t - hsa_amd_signal_async_handler.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, hsa_amd_signal_handler, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_async_function = _libraries['libhsa-runtime64.so'].hsa_amd_async_function - hsa_amd_async_function.restype = hsa_status_t - hsa_amd_async_function.argtypes = [ctypes.CFUNCTYPE(None, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_signal_wait_any = _libraries['libhsa-runtime64.so'].hsa_amd_signal_wait_any - hsa_amd_signal_wait_any.restype = uint32_t - hsa_amd_signal_wait_any.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), uint64_t, hsa_wait_state_t, ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -try: - hsa_amd_image_get_info_max_dim = _libraries['libhsa-runtime64.so'].hsa_amd_image_get_info_max_dim - hsa_amd_image_get_info_max_dim.restype = hsa_status_t - hsa_amd_image_get_info_max_dim.argtypes = [hsa_agent_t, hsa_agent_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_queue_cu_set_mask = _libraries['libhsa-runtime64.so'].hsa_amd_queue_cu_set_mask - hsa_amd_queue_cu_set_mask.restype = hsa_status_t - hsa_amd_queue_cu_set_mask.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_amd_queue_cu_get_mask = _libraries['libhsa-runtime64.so'].hsa_amd_queue_cu_get_mask - hsa_amd_queue_cu_get_mask.restype = hsa_status_t - hsa_amd_queue_cu_get_mask.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_amd_segment_t' -c__EA_hsa_amd_segment_t__enumvalues = { - 0: 'HSA_AMD_SEGMENT_GLOBAL', - 1: 'HSA_AMD_SEGMENT_READONLY', - 2: 'HSA_AMD_SEGMENT_PRIVATE', - 3: 'HSA_AMD_SEGMENT_GROUP', -} -HSA_AMD_SEGMENT_GLOBAL = 0 -HSA_AMD_SEGMENT_READONLY = 1 -HSA_AMD_SEGMENT_PRIVATE = 2 -HSA_AMD_SEGMENT_GROUP = 3 -c__EA_hsa_amd_segment_t = ctypes.c_uint32 # enum -hsa_amd_segment_t = c__EA_hsa_amd_segment_t -hsa_amd_segment_t__enumvalues = c__EA_hsa_amd_segment_t__enumvalues -class struct_hsa_amd_memory_pool_s(Structure): - pass - -struct_hsa_amd_memory_pool_s._pack_ = 1 # source:False -struct_hsa_amd_memory_pool_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_amd_memory_pool_t = struct_hsa_amd_memory_pool_s - -# values for enumeration 'hsa_amd_memory_pool_global_flag_s' -hsa_amd_memory_pool_global_flag_s__enumvalues = { - 1: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT', - 2: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED', - 4: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED', - 8: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', -} -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT = 1 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED = 2 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED = 4 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = 8 -hsa_amd_memory_pool_global_flag_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_global_flag_t = hsa_amd_memory_pool_global_flag_s -hsa_amd_memory_pool_global_flag_t__enumvalues = hsa_amd_memory_pool_global_flag_s__enumvalues - -# values for enumeration 'hsa_amd_memory_pool_location_s' -hsa_amd_memory_pool_location_s__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_LOCATION_CPU', - 1: 'HSA_AMD_MEMORY_POOL_LOCATION_GPU', -} -HSA_AMD_MEMORY_POOL_LOCATION_CPU = 0 -HSA_AMD_MEMORY_POOL_LOCATION_GPU = 1 -hsa_amd_memory_pool_location_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_location_t = hsa_amd_memory_pool_location_s -hsa_amd_memory_pool_location_t__enumvalues = hsa_amd_memory_pool_location_s__enumvalues - -# values for enumeration 'c__EA_hsa_amd_memory_pool_info_t' -c__EA_hsa_amd_memory_pool_info_t__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_INFO_SEGMENT', - 1: 'HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS', - 2: 'HSA_AMD_MEMORY_POOL_INFO_SIZE', - 5: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED', - 6: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE', - 7: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT', - 15: 'HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL', - 16: 'HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE', - 17: 'HSA_AMD_MEMORY_POOL_INFO_LOCATION', - 18: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE', -} -HSA_AMD_MEMORY_POOL_INFO_SEGMENT = 0 -HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS = 1 -HSA_AMD_MEMORY_POOL_INFO_SIZE = 2 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED = 5 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE = 6 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT = 7 -HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL = 15 -HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE = 16 -HSA_AMD_MEMORY_POOL_INFO_LOCATION = 17 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE = 18 -c__EA_hsa_amd_memory_pool_info_t = ctypes.c_uint32 # enum -hsa_amd_memory_pool_info_t = c__EA_hsa_amd_memory_pool_info_t -hsa_amd_memory_pool_info_t__enumvalues = c__EA_hsa_amd_memory_pool_info_t__enumvalues - -# values for enumeration 'hsa_amd_memory_pool_flag_s' -hsa_amd_memory_pool_flag_s__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_STANDARD_FLAG', - 1: 'HSA_AMD_MEMORY_POOL_PCIE_FLAG', - 2: 'HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG', -} -HSA_AMD_MEMORY_POOL_STANDARD_FLAG = 0 -HSA_AMD_MEMORY_POOL_PCIE_FLAG = 1 -HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG = 2 -hsa_amd_memory_pool_flag_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_flag_t = hsa_amd_memory_pool_flag_s -hsa_amd_memory_pool_flag_t__enumvalues = hsa_amd_memory_pool_flag_s__enumvalues -try: - hsa_amd_memory_pool_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_get_info - hsa_amd_memory_pool_get_info.restype = hsa_status_t - hsa_amd_memory_pool_get_info.argtypes = [hsa_amd_memory_pool_t, hsa_amd_memory_pool_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_agent_iterate_memory_pools = _libraries['libhsa-runtime64.so'].hsa_amd_agent_iterate_memory_pools - hsa_amd_agent_iterate_memory_pools.restype = hsa_status_t - hsa_amd_agent_iterate_memory_pools.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_amd_memory_pool_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_pool_allocate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_allocate - hsa_amd_memory_pool_allocate.restype = hsa_status_t - hsa_amd_memory_pool_allocate.argtypes = [hsa_amd_memory_pool_t, size_t, uint32_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_pool_free = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_free - hsa_amd_memory_pool_free.restype = hsa_status_t - hsa_amd_memory_pool_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_async_copy = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy - hsa_amd_memory_async_copy.restype = hsa_status_t - hsa_amd_memory_async_copy.argtypes = [ctypes.POINTER(None), hsa_agent_t, ctypes.POINTER(None), hsa_agent_t, size_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass -try: - hsa_amd_memory_async_copy_on_engine = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy_on_engine - hsa_amd_memory_async_copy_on_engine.restype = hsa_status_t - hsa_amd_memory_async_copy_on_engine.argtypes = [ctypes.POINTER(None), hsa_agent_t, ctypes.POINTER(None), hsa_agent_t, size_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t, hsa_amd_sdma_engine_id_t, ctypes.c_bool] -except AttributeError: - pass -try: - hsa_amd_memory_copy_engine_status = _libraries['libhsa-runtime64.so'].hsa_amd_memory_copy_engine_status - hsa_amd_memory_copy_engine_status.restype = hsa_status_t - hsa_amd_memory_copy_engine_status.argtypes = [hsa_agent_t, hsa_agent_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_pitched_ptr_s(Structure): - pass - -struct_hsa_pitched_ptr_s._pack_ = 1 # source:False -struct_hsa_pitched_ptr_s._fields_ = [ - ('base', ctypes.POINTER(None)), - ('pitch', ctypes.c_uint64), - ('slice', ctypes.c_uint64), -] - -hsa_pitched_ptr_t = struct_hsa_pitched_ptr_s - -# values for enumeration 'c__EA_hsa_amd_copy_direction_t' -c__EA_hsa_amd_copy_direction_t__enumvalues = { - 0: 'hsaHostToHost', - 1: 'hsaHostToDevice', - 2: 'hsaDeviceToHost', - 3: 'hsaDeviceToDevice', -} -hsaHostToHost = 0 -hsaHostToDevice = 1 -hsaDeviceToHost = 2 -hsaDeviceToDevice = 3 -c__EA_hsa_amd_copy_direction_t = ctypes.c_uint32 # enum -hsa_amd_copy_direction_t = c__EA_hsa_amd_copy_direction_t -hsa_amd_copy_direction_t__enumvalues = c__EA_hsa_amd_copy_direction_t__enumvalues -try: - hsa_amd_memory_async_copy_rect = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy_rect - hsa_amd_memory_async_copy_rect.restype = hsa_status_t - hsa_amd_memory_async_copy_rect.argtypes = [ctypes.POINTER(struct_hsa_pitched_ptr_s), ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_pitched_ptr_s), ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s), hsa_agent_t, hsa_amd_copy_direction_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_amd_memory_pool_access_t' -c__EA_hsa_amd_memory_pool_access_t__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED', - 1: 'HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT', - 2: 'HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT', -} -HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED = 0 -HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT = 1 -HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT = 2 -c__EA_hsa_amd_memory_pool_access_t = ctypes.c_uint32 # enum -hsa_amd_memory_pool_access_t = c__EA_hsa_amd_memory_pool_access_t -hsa_amd_memory_pool_access_t__enumvalues = c__EA_hsa_amd_memory_pool_access_t__enumvalues - -# values for enumeration 'c__EA_hsa_amd_link_info_type_t' -c__EA_hsa_amd_link_info_type_t__enumvalues = { - 0: 'HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT', - 1: 'HSA_AMD_LINK_INFO_TYPE_QPI', - 2: 'HSA_AMD_LINK_INFO_TYPE_PCIE', - 3: 'HSA_AMD_LINK_INFO_TYPE_INFINBAND', - 4: 'HSA_AMD_LINK_INFO_TYPE_XGMI', -} -HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT = 0 -HSA_AMD_LINK_INFO_TYPE_QPI = 1 -HSA_AMD_LINK_INFO_TYPE_PCIE = 2 -HSA_AMD_LINK_INFO_TYPE_INFINBAND = 3 -HSA_AMD_LINK_INFO_TYPE_XGMI = 4 -c__EA_hsa_amd_link_info_type_t = ctypes.c_uint32 # enum -hsa_amd_link_info_type_t = c__EA_hsa_amd_link_info_type_t -hsa_amd_link_info_type_t__enumvalues = c__EA_hsa_amd_link_info_type_t__enumvalues -class struct_hsa_amd_memory_pool_link_info_s(Structure): - pass - -struct_hsa_amd_memory_pool_link_info_s._pack_ = 1 # source:False -struct_hsa_amd_memory_pool_link_info_s._fields_ = [ - ('min_latency', ctypes.c_uint32), - ('max_latency', ctypes.c_uint32), - ('min_bandwidth', ctypes.c_uint32), - ('max_bandwidth', ctypes.c_uint32), - ('atomic_support_32bit', ctypes.c_bool), - ('atomic_support_64bit', ctypes.c_bool), - ('coherent_support', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), - ('link_type', hsa_amd_link_info_type_t), - ('numa_distance', ctypes.c_uint32), -] - -hsa_amd_memory_pool_link_info_t = struct_hsa_amd_memory_pool_link_info_s - -# values for enumeration 'c__EA_hsa_amd_agent_memory_pool_info_t' -c__EA_hsa_amd_agent_memory_pool_info_t__enumvalues = { - 0: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS', - 1: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS', - 2: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO', -} -HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS = 0 -HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS = 1 -HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO = 2 -c__EA_hsa_amd_agent_memory_pool_info_t = ctypes.c_uint32 # enum -hsa_amd_agent_memory_pool_info_t = c__EA_hsa_amd_agent_memory_pool_info_t -hsa_amd_agent_memory_pool_info_t__enumvalues = c__EA_hsa_amd_agent_memory_pool_info_t__enumvalues -try: - hsa_amd_agent_memory_pool_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_agent_memory_pool_get_info - hsa_amd_agent_memory_pool_get_info.restype = hsa_status_t - hsa_amd_agent_memory_pool_get_info.argtypes = [hsa_agent_t, hsa_amd_memory_pool_t, hsa_amd_agent_memory_pool_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_agents_allow_access = _libraries['libhsa-runtime64.so'].hsa_amd_agents_allow_access - hsa_amd_agents_allow_access.restype = hsa_status_t - hsa_amd_agents_allow_access.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_pool_can_migrate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_can_migrate - hsa_amd_memory_pool_can_migrate.restype = hsa_status_t - hsa_amd_memory_pool_can_migrate.argtypes = [hsa_amd_memory_pool_t, hsa_amd_memory_pool_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_amd_memory_migrate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_migrate - hsa_amd_memory_migrate.restype = hsa_status_t - hsa_amd_memory_migrate.argtypes = [ctypes.POINTER(None), hsa_amd_memory_pool_t, uint32_t] -except AttributeError: - pass -try: - hsa_amd_memory_lock = _libraries['libhsa-runtime64.so'].hsa_amd_memory_lock - hsa_amd_memory_lock.restype = hsa_status_t - hsa_amd_memory_lock.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_lock_to_pool = _libraries['libhsa-runtime64.so'].hsa_amd_memory_lock_to_pool - hsa_amd_memory_lock_to_pool.restype = hsa_status_t - hsa_amd_memory_lock_to_pool.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, hsa_amd_memory_pool_t, uint32_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_unlock = _libraries['libhsa-runtime64.so'].hsa_amd_memory_unlock - hsa_amd_memory_unlock.restype = hsa_status_t - hsa_amd_memory_unlock.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_fill = _libraries['libhsa-runtime64.so'].hsa_amd_memory_fill - hsa_amd_memory_fill.restype = hsa_status_t - hsa_amd_memory_fill.argtypes = [ctypes.POINTER(None), uint32_t, size_t] -except AttributeError: - pass -try: - hsa_amd_interop_map_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_interop_map_buffer - hsa_amd_interop_map_buffer.restype = hsa_status_t - hsa_amd_interop_map_buffer.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, uint32_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_interop_unmap_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_interop_unmap_buffer - hsa_amd_interop_unmap_buffer.restype = hsa_status_t - hsa_amd_interop_unmap_buffer.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_amd_image_descriptor_s(Structure): - pass - -struct_hsa_amd_image_descriptor_s._pack_ = 1 # source:False -struct_hsa_amd_image_descriptor_s._fields_ = [ - ('version', ctypes.c_uint32), - ('deviceID', ctypes.c_uint32), - ('data', ctypes.c_uint32 * 1), -] - -hsa_amd_image_descriptor_t = struct_hsa_amd_image_descriptor_s -try: - hsa_amd_image_create = _libraries['libhsa-runtime64.so'].hsa_amd_image_create - hsa_amd_image_create.restype = hsa_status_t - hsa_amd_image_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(struct_hsa_amd_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_amd_pointer_type_t' -c__EA_hsa_amd_pointer_type_t__enumvalues = { - 0: 'HSA_EXT_POINTER_TYPE_UNKNOWN', - 1: 'HSA_EXT_POINTER_TYPE_HSA', - 2: 'HSA_EXT_POINTER_TYPE_LOCKED', - 3: 'HSA_EXT_POINTER_TYPE_GRAPHICS', - 4: 'HSA_EXT_POINTER_TYPE_IPC', -} -HSA_EXT_POINTER_TYPE_UNKNOWN = 0 -HSA_EXT_POINTER_TYPE_HSA = 1 -HSA_EXT_POINTER_TYPE_LOCKED = 2 -HSA_EXT_POINTER_TYPE_GRAPHICS = 3 -HSA_EXT_POINTER_TYPE_IPC = 4 -c__EA_hsa_amd_pointer_type_t = ctypes.c_uint32 # enum -hsa_amd_pointer_type_t = c__EA_hsa_amd_pointer_type_t -hsa_amd_pointer_type_t__enumvalues = c__EA_hsa_amd_pointer_type_t__enumvalues -class struct_hsa_amd_pointer_info_s(Structure): - pass - -struct_hsa_amd_pointer_info_s._pack_ = 1 # source:False -struct_hsa_amd_pointer_info_s._fields_ = [ - ('size', ctypes.c_uint32), - ('type', hsa_amd_pointer_type_t), - ('agentBaseAddress', ctypes.POINTER(None)), - ('hostBaseAddress', ctypes.POINTER(None)), - ('sizeInBytes', ctypes.c_uint64), - ('userData', ctypes.POINTER(None)), - ('agentOwner', hsa_agent_t), - ('global_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hsa_amd_pointer_info_t = struct_hsa_amd_pointer_info_s -try: - hsa_amd_pointer_info = _libraries['libhsa-runtime64.so'].hsa_amd_pointer_info - hsa_amd_pointer_info.restype = hsa_status_t - hsa_amd_pointer_info.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_hsa_amd_pointer_info_s), ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.POINTER(struct_hsa_agent_s))] -except AttributeError: - pass -try: - hsa_amd_pointer_info_set_userdata = _libraries['libhsa-runtime64.so'].hsa_amd_pointer_info_set_userdata - hsa_amd_pointer_info_set_userdata.restype = hsa_status_t - hsa_amd_pointer_info_set_userdata.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_amd_ipc_memory_s(Structure): - pass - -struct_hsa_amd_ipc_memory_s._pack_ = 1 # source:False -struct_hsa_amd_ipc_memory_s._fields_ = [ - ('handle', ctypes.c_uint32 * 8), -] - -hsa_amd_ipc_memory_t = struct_hsa_amd_ipc_memory_s -try: - hsa_amd_ipc_memory_create = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_create - hsa_amd_ipc_memory_create.restype = hsa_status_t - hsa_amd_ipc_memory_create.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_ipc_memory_s)] -except AttributeError: - pass -try: - hsa_amd_ipc_memory_attach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_attach - hsa_amd_ipc_memory_attach.restype = hsa_status_t - hsa_amd_ipc_memory_attach.argtypes = [ctypes.POINTER(struct_hsa_amd_ipc_memory_s), size_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_ipc_memory_detach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_detach - hsa_amd_ipc_memory_detach.restype = hsa_status_t - hsa_amd_ipc_memory_detach.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -hsa_amd_ipc_signal_t = struct_hsa_amd_ipc_memory_s -try: - hsa_amd_ipc_signal_create = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_signal_create - hsa_amd_ipc_signal_create.restype = hsa_status_t - hsa_amd_ipc_signal_create.argtypes = [hsa_signal_t, ctypes.POINTER(struct_hsa_amd_ipc_memory_s)] -except AttributeError: - pass -try: - hsa_amd_ipc_signal_attach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_signal_attach - hsa_amd_ipc_signal_attach.restype = hsa_status_t - hsa_amd_ipc_signal_attach.argtypes = [ctypes.POINTER(struct_hsa_amd_ipc_memory_s), ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass - -# values for enumeration 'hsa_amd_event_type_s' -hsa_amd_event_type_s__enumvalues = { - 0: 'HSA_AMD_GPU_MEMORY_FAULT_EVENT', - 1: 'HSA_AMD_GPU_HW_EXCEPTION_EVENT', -} -HSA_AMD_GPU_MEMORY_FAULT_EVENT = 0 -HSA_AMD_GPU_HW_EXCEPTION_EVENT = 1 -hsa_amd_event_type_s = ctypes.c_uint32 # enum -hsa_amd_event_type_t = hsa_amd_event_type_s -hsa_amd_event_type_t__enumvalues = hsa_amd_event_type_s__enumvalues - -# values for enumeration 'c__EA_hsa_amd_memory_fault_reason_t' -c__EA_hsa_amd_memory_fault_reason_t__enumvalues = { - 1: 'HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT', - 2: 'HSA_AMD_MEMORY_FAULT_READ_ONLY', - 4: 'HSA_AMD_MEMORY_FAULT_NX', - 8: 'HSA_AMD_MEMORY_FAULT_HOST_ONLY', - 16: 'HSA_AMD_MEMORY_FAULT_DRAMECC', - 32: 'HSA_AMD_MEMORY_FAULT_IMPRECISE', - 64: 'HSA_AMD_MEMORY_FAULT_SRAMECC', - 2147483648: 'HSA_AMD_MEMORY_FAULT_HANG', -} -HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT = 1 -HSA_AMD_MEMORY_FAULT_READ_ONLY = 2 -HSA_AMD_MEMORY_FAULT_NX = 4 -HSA_AMD_MEMORY_FAULT_HOST_ONLY = 8 -HSA_AMD_MEMORY_FAULT_DRAMECC = 16 -HSA_AMD_MEMORY_FAULT_IMPRECISE = 32 -HSA_AMD_MEMORY_FAULT_SRAMECC = 64 -HSA_AMD_MEMORY_FAULT_HANG = 2147483648 -c__EA_hsa_amd_memory_fault_reason_t = ctypes.c_uint32 # enum -hsa_amd_memory_fault_reason_t = c__EA_hsa_amd_memory_fault_reason_t -hsa_amd_memory_fault_reason_t__enumvalues = c__EA_hsa_amd_memory_fault_reason_t__enumvalues -class struct_hsa_amd_gpu_memory_fault_info_s(Structure): - pass - -struct_hsa_amd_gpu_memory_fault_info_s._pack_ = 1 # source:False -struct_hsa_amd_gpu_memory_fault_info_s._fields_ = [ - ('agent', hsa_agent_t), - ('virtual_address', ctypes.c_uint64), - ('fault_reason_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hsa_amd_gpu_memory_fault_info_t = struct_hsa_amd_gpu_memory_fault_info_s - -# values for enumeration 'c__EA_hsa_amd_hw_exception_reset_type_t' -c__EA_hsa_amd_hw_exception_reset_type_t__enumvalues = { - 1: 'HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER', -} -HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER = 1 -c__EA_hsa_amd_hw_exception_reset_type_t = ctypes.c_uint32 # enum -hsa_amd_hw_exception_reset_type_t = c__EA_hsa_amd_hw_exception_reset_type_t -hsa_amd_hw_exception_reset_type_t__enumvalues = c__EA_hsa_amd_hw_exception_reset_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_amd_hw_exception_reset_cause_t' -c__EA_hsa_amd_hw_exception_reset_cause_t__enumvalues = { - 1: 'HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG', - 2: 'HSA_AMD_HW_EXCEPTION_CAUSE_ECC', -} -HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG = 1 -HSA_AMD_HW_EXCEPTION_CAUSE_ECC = 2 -c__EA_hsa_amd_hw_exception_reset_cause_t = ctypes.c_uint32 # enum -hsa_amd_hw_exception_reset_cause_t = c__EA_hsa_amd_hw_exception_reset_cause_t -hsa_amd_hw_exception_reset_cause_t__enumvalues = c__EA_hsa_amd_hw_exception_reset_cause_t__enumvalues -class struct_hsa_amd_gpu_hw_exception_info_s(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('agent', hsa_agent_t), - ('reset_type', hsa_amd_hw_exception_reset_type_t), - ('reset_cause', hsa_amd_hw_exception_reset_cause_t), - ] - -hsa_amd_gpu_hw_exception_info_t = struct_hsa_amd_gpu_hw_exception_info_s -class struct_hsa_amd_event_s(Structure): - pass - -class union_hsa_amd_event_s_0(Union): - pass - -union_hsa_amd_event_s_0._pack_ = 1 # source:False -union_hsa_amd_event_s_0._fields_ = [ - ('memory_fault', hsa_amd_gpu_memory_fault_info_t), - ('hw_exception', hsa_amd_gpu_hw_exception_info_t), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_hsa_amd_event_s._pack_ = 1 # source:False -struct_hsa_amd_event_s._anonymous_ = ('_0',) -struct_hsa_amd_event_s._fields_ = [ - ('event_type', hsa_amd_event_type_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_hsa_amd_event_s_0), -] - -hsa_amd_event_t = struct_hsa_amd_event_s -hsa_amd_system_event_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_hsa_amd_event_s), ctypes.POINTER(None)) -try: - hsa_amd_register_system_event_handler = _libraries['libhsa-runtime64.so'].hsa_amd_register_system_event_handler - hsa_amd_register_system_event_handler.restype = hsa_status_t - hsa_amd_register_system_event_handler.argtypes = [hsa_amd_system_event_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'hsa_amd_queue_priority_s' -hsa_amd_queue_priority_s__enumvalues = { - 0: 'HSA_AMD_QUEUE_PRIORITY_LOW', - 1: 'HSA_AMD_QUEUE_PRIORITY_NORMAL', - 2: 'HSA_AMD_QUEUE_PRIORITY_HIGH', -} -HSA_AMD_QUEUE_PRIORITY_LOW = 0 -HSA_AMD_QUEUE_PRIORITY_NORMAL = 1 -HSA_AMD_QUEUE_PRIORITY_HIGH = 2 -hsa_amd_queue_priority_s = ctypes.c_uint32 # enum -hsa_amd_queue_priority_t = hsa_amd_queue_priority_s -hsa_amd_queue_priority_t__enumvalues = hsa_amd_queue_priority_s__enumvalues -try: - hsa_amd_queue_set_priority = _libraries['libhsa-runtime64.so'].hsa_amd_queue_set_priority - hsa_amd_queue_set_priority.restype = hsa_status_t - hsa_amd_queue_set_priority.argtypes = [ctypes.POINTER(struct_hsa_queue_s), hsa_amd_queue_priority_t] -except AttributeError: - pass -hsa_amd_deallocation_callback_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None)) -try: - hsa_amd_register_deallocation_callback = _libraries['libhsa-runtime64.so'].hsa_amd_register_deallocation_callback - hsa_amd_register_deallocation_callback.restype = hsa_status_t - hsa_amd_register_deallocation_callback.argtypes = [ctypes.POINTER(None), hsa_amd_deallocation_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_deregister_deallocation_callback = _libraries['libhsa-runtime64.so'].hsa_amd_deregister_deallocation_callback - hsa_amd_deregister_deallocation_callback.restype = hsa_status_t - hsa_amd_deregister_deallocation_callback.argtypes = [ctypes.POINTER(None), hsa_amd_deallocation_callback_t] -except AttributeError: - pass - -# values for enumeration 'hsa_amd_svm_model_s' -hsa_amd_svm_model_s__enumvalues = { - 0: 'HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED', - 1: 'HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED', - 2: 'HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE', -} -HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED = 0 -HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED = 1 -HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE = 2 -hsa_amd_svm_model_s = ctypes.c_uint32 # enum -hsa_amd_svm_model_t = hsa_amd_svm_model_s -hsa_amd_svm_model_t__enumvalues = hsa_amd_svm_model_s__enumvalues - -# values for enumeration 'hsa_amd_svm_attribute_s' -hsa_amd_svm_attribute_s__enumvalues = { - 0: 'HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG', - 1: 'HSA_AMD_SVM_ATTRIB_READ_ONLY', - 2: 'HSA_AMD_SVM_ATTRIB_HIVE_LOCAL', - 3: 'HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY', - 4: 'HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION', - 5: 'HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION', - 6: 'HSA_AMD_SVM_ATTRIB_READ_MOSTLY', - 7: 'HSA_AMD_SVM_ATTRIB_GPU_EXEC', - 512: 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE', - 513: 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE', - 514: 'HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS', - 515: 'HSA_AMD_SVM_ATTRIB_ACCESS_QUERY', -} -HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG = 0 -HSA_AMD_SVM_ATTRIB_READ_ONLY = 1 -HSA_AMD_SVM_ATTRIB_HIVE_LOCAL = 2 -HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY = 3 -HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION = 4 -HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION = 5 -HSA_AMD_SVM_ATTRIB_READ_MOSTLY = 6 -HSA_AMD_SVM_ATTRIB_GPU_EXEC = 7 -HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE = 512 -HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE = 513 -HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS = 514 -HSA_AMD_SVM_ATTRIB_ACCESS_QUERY = 515 -hsa_amd_svm_attribute_s = ctypes.c_uint32 # enum -hsa_amd_svm_attribute_t = hsa_amd_svm_attribute_s -hsa_amd_svm_attribute_t__enumvalues = hsa_amd_svm_attribute_s__enumvalues -class struct_hsa_amd_svm_attribute_pair_s(Structure): - pass - -struct_hsa_amd_svm_attribute_pair_s._pack_ = 1 # source:False -struct_hsa_amd_svm_attribute_pair_s._fields_ = [ - ('attribute', ctypes.c_uint64), - ('value', ctypes.c_uint64), -] - -hsa_amd_svm_attribute_pair_t = struct_hsa_amd_svm_attribute_pair_s -try: - hsa_amd_svm_attributes_set = _libraries['libhsa-runtime64.so'].hsa_amd_svm_attributes_set - hsa_amd_svm_attributes_set.restype = hsa_status_t - hsa_amd_svm_attributes_set.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_svm_attribute_pair_s), size_t] -except AttributeError: - pass -try: - hsa_amd_svm_attributes_get = _libraries['libhsa-runtime64.so'].hsa_amd_svm_attributes_get - hsa_amd_svm_attributes_get.restype = hsa_status_t - hsa_amd_svm_attributes_get.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_svm_attribute_pair_s), size_t] -except AttributeError: - pass -try: - hsa_amd_svm_prefetch_async = _libraries['libhsa-runtime64.so'].hsa_amd_svm_prefetch_async - hsa_amd_svm_prefetch_async.restype = hsa_status_t - hsa_amd_svm_prefetch_async.argtypes = [ctypes.POINTER(None), size_t, hsa_agent_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass -try: - hsa_amd_spm_acquire = _libraries['libhsa-runtime64.so'].hsa_amd_spm_acquire - hsa_amd_spm_acquire.restype = hsa_status_t - hsa_amd_spm_acquire.argtypes = [hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_spm_release = _libraries['libhsa-runtime64.so'].hsa_amd_spm_release - hsa_amd_spm_release.restype = hsa_status_t - hsa_amd_spm_release.argtypes = [hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_spm_set_dest_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_spm_set_dest_buffer - hsa_amd_spm_set_dest_buffer.restype = hsa_status_t - hsa_amd_spm_set_dest_buffer.argtypes = [hsa_agent_t, size_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_amd_portable_export_dmabuf = _libraries['libhsa-runtime64.so'].hsa_amd_portable_export_dmabuf - hsa_amd_portable_export_dmabuf.restype = hsa_status_t - hsa_amd_portable_export_dmabuf.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hsa_amd_portable_close_dmabuf = _libraries['libhsa-runtime64.so'].hsa_amd_portable_close_dmabuf - hsa_amd_portable_close_dmabuf.restype = hsa_status_t - hsa_amd_portable_close_dmabuf.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hsa_amd_vmem_address_reserve = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_reserve - hsa_amd_vmem_address_reserve.restype = hsa_status_t - hsa_amd_vmem_address_reserve.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_address_reserve_align = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_reserve_align - hsa_amd_vmem_address_reserve_align.restype = hsa_status_t - hsa_amd_vmem_address_reserve_align.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, uint64_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_address_free = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_free - hsa_amd_vmem_address_free.restype = hsa_status_t - hsa_amd_vmem_address_free.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_amd_vmem_alloc_handle_s(Structure): - pass - -struct_hsa_amd_vmem_alloc_handle_s._pack_ = 1 # source:False -struct_hsa_amd_vmem_alloc_handle_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_amd_vmem_alloc_handle_t = struct_hsa_amd_vmem_alloc_handle_s - -# values for enumeration 'c__EA_hsa_amd_memory_type_t' -c__EA_hsa_amd_memory_type_t__enumvalues = { - 0: 'MEMORY_TYPE_NONE', - 1: 'MEMORY_TYPE_PINNED', -} -MEMORY_TYPE_NONE = 0 -MEMORY_TYPE_PINNED = 1 -c__EA_hsa_amd_memory_type_t = ctypes.c_uint32 # enum -hsa_amd_memory_type_t = c__EA_hsa_amd_memory_type_t -hsa_amd_memory_type_t__enumvalues = c__EA_hsa_amd_memory_type_t__enumvalues -try: - hsa_amd_vmem_handle_create = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_handle_create - hsa_amd_vmem_handle_create.restype = hsa_status_t - hsa_amd_vmem_handle_create.argtypes = [hsa_amd_memory_pool_t, size_t, hsa_amd_memory_type_t, uint64_t, ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s)] -except AttributeError: - pass -try: - hsa_amd_vmem_handle_release = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_handle_release - hsa_amd_vmem_handle_release.restype = hsa_status_t - hsa_amd_vmem_handle_release.argtypes = [hsa_amd_vmem_alloc_handle_t] -except AttributeError: - pass -try: - hsa_amd_vmem_map = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_map - hsa_amd_vmem_map.restype = hsa_status_t - hsa_amd_vmem_map.argtypes = [ctypes.POINTER(None), size_t, size_t, hsa_amd_vmem_alloc_handle_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_unmap = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_unmap - hsa_amd_vmem_unmap.restype = hsa_status_t - hsa_amd_vmem_unmap.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_amd_memory_access_desc_s(Structure): - pass - -struct_hsa_amd_memory_access_desc_s._pack_ = 1 # source:False -struct_hsa_amd_memory_access_desc_s._fields_ = [ - ('permissions', hsa_access_permission_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('agent_handle', hsa_agent_t), -] - -hsa_amd_memory_access_desc_t = struct_hsa_amd_memory_access_desc_s -try: - hsa_amd_vmem_set_access = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_set_access - hsa_amd_vmem_set_access.restype = hsa_status_t - hsa_amd_vmem_set_access.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_memory_access_desc_s), size_t] -except AttributeError: - pass -try: - hsa_amd_vmem_get_access = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_get_access - hsa_amd_vmem_get_access.restype = hsa_status_t - hsa_amd_vmem_get_access.argtypes = [ctypes.POINTER(None), ctypes.POINTER(c__EA_hsa_access_permission_t), hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_vmem_export_shareable_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_export_shareable_handle - hsa_amd_vmem_export_shareable_handle.restype = hsa_status_t - hsa_amd_vmem_export_shareable_handle.argtypes = [ctypes.POINTER(ctypes.c_int32), hsa_amd_vmem_alloc_handle_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_import_shareable_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_import_shareable_handle - hsa_amd_vmem_import_shareable_handle.restype = hsa_status_t - hsa_amd_vmem_import_shareable_handle.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s)] -except AttributeError: - pass -try: - hsa_amd_vmem_retain_alloc_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_retain_alloc_handle - hsa_amd_vmem_retain_alloc_handle.restype = hsa_status_t - hsa_amd_vmem_retain_alloc_handle.argtypes = [ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_vmem_get_alloc_properties_from_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_get_alloc_properties_from_handle - hsa_amd_vmem_get_alloc_properties_from_handle.restype = hsa_status_t - hsa_amd_vmem_get_alloc_properties_from_handle.argtypes = [hsa_amd_vmem_alloc_handle_t, ctypes.POINTER(struct_hsa_amd_memory_pool_s), ctypes.POINTER(c__EA_hsa_amd_memory_type_t)] -except AttributeError: - pass -try: - hsa_amd_agent_set_async_scratch_limit = _libraries['libhsa-runtime64.so'].hsa_amd_agent_set_async_scratch_limit - hsa_amd_agent_set_async_scratch_limit.restype = hsa_status_t - hsa_amd_agent_set_async_scratch_limit.argtypes = [hsa_agent_t, size_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_queue_info_attribute_t' -c__EA_hsa_queue_info_attribute_t__enumvalues = { - 0: 'HSA_AMD_QUEUE_INFO_AGENT', - 1: 'HSA_AMD_QUEUE_INFO_DOORBELL_ID', -} -HSA_AMD_QUEUE_INFO_AGENT = 0 -HSA_AMD_QUEUE_INFO_DOORBELL_ID = 1 -c__EA_hsa_queue_info_attribute_t = ctypes.c_uint32 # enum -hsa_queue_info_attribute_t = c__EA_hsa_queue_info_attribute_t -hsa_queue_info_attribute_t__enumvalues = c__EA_hsa_queue_info_attribute_t__enumvalues -try: - hsa_amd_queue_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_queue_get_info - hsa_amd_queue_get_info.restype = hsa_status_t - hsa_amd_queue_get_info.argtypes = [ctypes.POINTER(struct_hsa_queue_s), hsa_queue_info_attribute_t, ctypes.POINTER(None)] -except AttributeError: - pass -amd_queue_properties32_t = ctypes.c_uint32 - -# values for enumeration 'amd_queue_properties_t' -amd_queue_properties_t__enumvalues = { - 0: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER', - 1: 'AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH', - 2: 'AMD_QUEUE_PROPERTIES_IS_PTR64', - 2: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH', - 4: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS', - 3: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH', - 8: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING', - 4: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH', - 16: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE', - 5: 'AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT', - 27: 'AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH', - -32: 'AMD_QUEUE_PROPERTIES_RESERVED1', -} -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT = 0 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64 = 2 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT = 2 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS = 4 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT = 3 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING = 8 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT = 4 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH = 1 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE = 16 -AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT = 5 -AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH = 27 -AMD_QUEUE_PROPERTIES_RESERVED1 = -32 -amd_queue_properties_t = ctypes.c_int32 # enum -amd_queue_capabilities32_t = ctypes.c_uint32 - -# values for enumeration 'amd_queue_capabilities_t' -amd_queue_capabilities_t__enumvalues = { - 0: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT', - 1: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH', - 1: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM', -} -AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT = 0 -AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH = 1 -AMD_QUEUE_CAPS_ASYNC_RECLAIM = 1 -amd_queue_capabilities_t = ctypes.c_uint32 # enum -class struct_amd_queue_s(Structure): - pass - -struct_amd_queue_s._pack_ = 1 # source:False -struct_amd_queue_s._fields_ = [ - ('hsa_queue', hsa_queue_t), - ('caps', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32 * 3), - ('write_dispatch_id', ctypes.c_uint64), - ('group_segment_aperture_base_hi', ctypes.c_uint32), - ('private_segment_aperture_base_hi', ctypes.c_uint32), - ('max_cu_id', ctypes.c_uint32), - ('max_wave_id', ctypes.c_uint32), - ('max_legacy_doorbell_dispatch_id_plus_1', ctypes.c_uint64), - ('legacy_doorbell_lock', ctypes.c_uint32), - ('reserved2', ctypes.c_uint32 * 9), - ('read_dispatch_id', ctypes.c_uint64), - ('read_dispatch_id_field_base_byte_offset', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('scratch_resource_descriptor', ctypes.c_uint32 * 4), - ('scratch_backing_memory_location', ctypes.c_uint64), - ('scratch_backing_memory_byte_size', ctypes.c_uint64), - ('scratch_wave64_lane_byte_size', ctypes.c_uint32), - ('queue_properties', ctypes.c_uint32), - ('scratch_last_used_index', ctypes.c_uint64), - ('queue_inactive_signal', hsa_signal_t), - ('reserved4', ctypes.c_uint32 * 2), - ('alt_scratch_last_used_index', ctypes.c_uint64), - ('alt_scratch_backing_memory_location', ctypes.c_uint64), - ('alt_scratch_backing_memory_byte_size', ctypes.c_uint64), - ('alt_scratch_dispatch_limit_x', ctypes.c_uint32), - ('alt_scratch_dispatch_limit_y', ctypes.c_uint32), - ('alt_scratch_dispatch_limit_z', ctypes.c_uint32), - ('alt_scratch_wave64_lane_byte_size', ctypes.c_uint32), - ('alt_compute_tmpring_size', ctypes.c_uint32), - ('reserved5', ctypes.c_uint32), -] - -amd_queue_t = struct_amd_queue_s -amd_signal_kind64_t = ctypes.c_int64 - -# values for enumeration 'amd_signal_kind_t' -amd_signal_kind_t__enumvalues = { - 0: 'AMD_SIGNAL_KIND_INVALID', - 1: 'AMD_SIGNAL_KIND_USER', - -1: 'AMD_SIGNAL_KIND_DOORBELL', - -2: 'AMD_SIGNAL_KIND_LEGACY_DOORBELL', -} -AMD_SIGNAL_KIND_INVALID = 0 -AMD_SIGNAL_KIND_USER = 1 -AMD_SIGNAL_KIND_DOORBELL = -1 -AMD_SIGNAL_KIND_LEGACY_DOORBELL = -2 -amd_signal_kind_t = ctypes.c_int32 # enum -class struct_amd_signal_s(Structure): - pass - -class union_amd_signal_s_0(Union): - pass - -union_amd_signal_s_0._pack_ = 1 # source:False -union_amd_signal_s_0._fields_ = [ - ('value', ctypes.c_int64), - ('legacy_hardware_doorbell_ptr', ctypes.POINTER(ctypes.c_uint32)), - ('hardware_doorbell_ptr', ctypes.POINTER(ctypes.c_uint64)), -] - -class union_amd_signal_s_1(Union): - pass - -union_amd_signal_s_1._pack_ = 1 # source:False -union_amd_signal_s_1._fields_ = [ - ('queue_ptr', ctypes.POINTER(struct_amd_queue_s)), - ('reserved2', ctypes.c_uint64), -] - -struct_amd_signal_s._pack_ = 1 # source:False -struct_amd_signal_s._anonymous_ = ('_0', '_1',) -struct_amd_signal_s._fields_ = [ - ('kind', ctypes.c_int64), - ('_0', union_amd_signal_s_0), - ('event_mailbox_ptr', ctypes.c_uint64), - ('event_id', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('start_ts', ctypes.c_uint64), - ('end_ts', ctypes.c_uint64), - ('_1', union_amd_signal_s_1), - ('reserved3', ctypes.c_uint32 * 2), -] - -amd_signal_t = struct_amd_signal_s -amd_kernel_code_version32_t = ctypes.c_uint32 - -# values for enumeration 'amd_kernel_code_version_t' -amd_kernel_code_version_t__enumvalues = { - 1: 'AMD_KERNEL_CODE_VERSION_MAJOR', - 1: 'AMD_KERNEL_CODE_VERSION_MINOR', -} -AMD_KERNEL_CODE_VERSION_MAJOR = 1 -AMD_KERNEL_CODE_VERSION_MINOR = 1 -amd_kernel_code_version_t = ctypes.c_uint32 # enum -amd_machine_kind16_t = ctypes.c_uint16 - -# values for enumeration 'amd_machine_kind_t' -amd_machine_kind_t__enumvalues = { - 0: 'AMD_MACHINE_KIND_UNDEFINED', - 1: 'AMD_MACHINE_KIND_AMDGPU', -} -AMD_MACHINE_KIND_UNDEFINED = 0 -AMD_MACHINE_KIND_AMDGPU = 1 -amd_machine_kind_t = ctypes.c_uint32 # enum -amd_machine_version16_t = ctypes.c_uint16 - -# values for enumeration 'amd_float_round_mode_t' -amd_float_round_mode_t__enumvalues = { - 0: 'AMD_FLOAT_ROUND_MODE_NEAREST_EVEN', - 1: 'AMD_FLOAT_ROUND_MODE_PLUS_INFINITY', - 2: 'AMD_FLOAT_ROUND_MODE_MINUS_INFINITY', - 3: 'AMD_FLOAT_ROUND_MODE_ZERO', -} -AMD_FLOAT_ROUND_MODE_NEAREST_EVEN = 0 -AMD_FLOAT_ROUND_MODE_PLUS_INFINITY = 1 -AMD_FLOAT_ROUND_MODE_MINUS_INFINITY = 2 -AMD_FLOAT_ROUND_MODE_ZERO = 3 -amd_float_round_mode_t = ctypes.c_uint32 # enum - -# values for enumeration 'amd_float_denorm_mode_t' -amd_float_denorm_mode_t__enumvalues = { - 0: 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT', - 1: 'AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT', - 2: 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE', - 3: 'AMD_FLOAT_DENORM_MODE_NO_FLUSH', -} -AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT = 0 -AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT = 1 -AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE = 2 -AMD_FLOAT_DENORM_MODE_NO_FLUSH = 3 -amd_float_denorm_mode_t = ctypes.c_uint32 # enum -amd_compute_pgm_rsrc_one32_t = ctypes.c_uint32 - -# values for enumeration 'amd_compute_pgm_rsrc_one_t' -amd_compute_pgm_rsrc_one_t__enumvalues = { - 0: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH', - 63: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT', - 4: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH', - 960: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT', - 10: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH', - 3072: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY', - 12: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH', - 12288: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32', - 14: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH', - 49152: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64', - 16: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH', - 196608: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32', - 18: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH', - 786432: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64', - 20: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH', - 1048576: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV', - 21: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH', - 2097152: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP', - 22: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH', - 4194304: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE', - 23: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH', - 8388608: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE', - 24: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH', - 16777216: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY', - 25: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH', - 33554432: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER', - 26: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH', - -67108864: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1', -} -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT = 0 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH = 6 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT = 63 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT = 6 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH = 4 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT = 960 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT = 10 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY = 3072 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT = 12 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32 = 12288 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT = 14 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64 = 49152 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT = 16 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32 = 196608 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT = 18 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64 = 786432 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT = 20 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV = 1048576 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT = 21 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP = 2097152 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT = 22 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE = 4194304 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT = 23 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE = 8388608 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT = 24 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY = 16777216 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT = 25 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER = 33554432 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT = 26 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH = 6 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1 = -67108864 -amd_compute_pgm_rsrc_one_t = ctypes.c_int32 # enum - -# values for enumeration 'amd_system_vgpr_workitem_id_t' -amd_system_vgpr_workitem_id_t__enumvalues = { - 0: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X', - 1: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y', - 2: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z', - 3: 'AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED', -} -AMD_SYSTEM_VGPR_WORKITEM_ID_X = 0 -AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1 -AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2 -AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 -amd_system_vgpr_workitem_id_t = ctypes.c_uint32 # enum -amd_compute_pgm_rsrc_two32_t = ctypes.c_uint32 - -# values for enumeration 'amd_compute_pgm_rsrc_two_t' -amd_compute_pgm_rsrc_two_t__enumvalues = { - 0: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT', - 5: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH', - 62: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT', - 6: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH', - 64: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER', - 7: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH', - 128: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X', - 8: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH', - 256: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y', - 9: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH', - 512: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z', - 10: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH', - 1024: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO', - 11: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH', - 6144: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID', - 13: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH', - 8192: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH', - 14: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH', - 16384: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION', - 15: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT', - 9: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH', - 16744448: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE', - 24: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH', - 16777216: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION', - 25: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH', - 33554432: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE', - 26: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH', - 67108864: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO', - 27: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH', - 134217728: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW', - 28: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH', - 268435456: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW', - 29: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH', - 536870912: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT', - 30: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH', - 1073741824: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO', - 31: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH', - -2147483648: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1', -} -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT = 0 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 1 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT = 1 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH = 5 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT = 62 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT = 6 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER = 64 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT = 7 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X = 128 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT = 8 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y = 256 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT = 9 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z = 512 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT = 10 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO = 1024 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT = 11 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID = 6144 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT = 13 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH = 8192 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT = 14 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION = 16384 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT = 15 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH = 9 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE = 16744448 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT = 24 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION = 16777216 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT = 25 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE = 33554432 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT = 26 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO = 67108864 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT = 27 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW = 134217728 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT = 28 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW = 268435456 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT = 29 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT = 536870912 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT = 30 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO = 1073741824 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT = 31 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1 = -2147483648 -amd_compute_pgm_rsrc_two_t = ctypes.c_int32 # enum - -# values for enumeration 'amd_element_byte_size_t' -amd_element_byte_size_t__enumvalues = { - 0: 'AMD_ELEMENT_BYTE_SIZE_2', - 1: 'AMD_ELEMENT_BYTE_SIZE_4', - 2: 'AMD_ELEMENT_BYTE_SIZE_8', - 3: 'AMD_ELEMENT_BYTE_SIZE_16', -} -AMD_ELEMENT_BYTE_SIZE_2 = 0 -AMD_ELEMENT_BYTE_SIZE_4 = 1 -AMD_ELEMENT_BYTE_SIZE_8 = 2 -AMD_ELEMENT_BYTE_SIZE_16 = 3 -amd_element_byte_size_t = ctypes.c_uint32 # enum -amd_kernel_code_properties32_t = ctypes.c_uint32 - -# values for enumeration 'amd_kernel_code_properties_t' -amd_kernel_code_properties_t__enumvalues = { - 0: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH', - 2: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR', - 2: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH', - 4: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR', - 3: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH', - 8: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR', - 4: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH', - 16: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID', - 5: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH', - 32: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT', - 6: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH', - 64: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE', - 7: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH', - 128: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X', - 8: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH', - 256: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y', - 9: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH', - 512: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z', - 10: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT', - 6: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH', - 64512: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1', - 16: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH', - 65536: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS', - 17: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT', - 2: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH', - 393216: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE', - 19: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH', - 524288: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64', - 20: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH', - 1048576: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK', - 21: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH', - 2097152: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED', - 22: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH', - 4194304: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED', - 23: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT', - 9: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH', - -8388608: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2', -} -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT = 0 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR = 2 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT = 2 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR = 4 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT = 3 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR = 8 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT = 4 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID = 16 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT = 5 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT = 32 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT = 6 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE = 64 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT = 7 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X = 128 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT = 8 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y = 256 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT = 9 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z = 512 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT = 10 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH = 6 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1 = 64512 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT = 16 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS = 65536 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT = 17 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH = 2 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE = 393216 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT = 19 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64 = 524288 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT = 20 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK = 1048576 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT = 21 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED = 2097152 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT = 22 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED = 4194304 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT = 23 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH = 9 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2 = -8388608 -amd_kernel_code_properties_t = ctypes.c_int32 # enum -amd_powertwo8_t = ctypes.c_ubyte - -# values for enumeration 'amd_powertwo_t' -amd_powertwo_t__enumvalues = { - 0: 'AMD_POWERTWO_1', - 1: 'AMD_POWERTWO_2', - 2: 'AMD_POWERTWO_4', - 3: 'AMD_POWERTWO_8', - 4: 'AMD_POWERTWO_16', - 5: 'AMD_POWERTWO_32', - 6: 'AMD_POWERTWO_64', - 7: 'AMD_POWERTWO_128', - 8: 'AMD_POWERTWO_256', -} -AMD_POWERTWO_1 = 0 -AMD_POWERTWO_2 = 1 -AMD_POWERTWO_4 = 2 -AMD_POWERTWO_8 = 3 -AMD_POWERTWO_16 = 4 -AMD_POWERTWO_32 = 5 -AMD_POWERTWO_64 = 6 -AMD_POWERTWO_128 = 7 -AMD_POWERTWO_256 = 8 -amd_powertwo_t = ctypes.c_uint32 # enum -amd_enabled_control_directive64_t = ctypes.c_uint64 - -# values for enumeration 'amd_enabled_control_directive_t' -amd_enabled_control_directive_t__enumvalues = { - 1: 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS', - 2: 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS', - 4: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE', - 8: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE', - 16: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE', - 32: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM', - 64: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE', - 128: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE', - 256: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS', -} -AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS = 1 -AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS = 2 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE = 4 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE = 8 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE = 16 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM = 32 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE = 64 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE = 128 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS = 256 -amd_enabled_control_directive_t = ctypes.c_uint32 # enum -amd_exception_kind16_t = ctypes.c_uint16 - -# values for enumeration 'amd_exception_kind_t' -amd_exception_kind_t__enumvalues = { - 1: 'AMD_EXCEPTION_KIND_INVALID_OPERATION', - 2: 'AMD_EXCEPTION_KIND_DIVISION_BY_ZERO', - 4: 'AMD_EXCEPTION_KIND_OVERFLOW', - 8: 'AMD_EXCEPTION_KIND_UNDERFLOW', - 16: 'AMD_EXCEPTION_KIND_INEXACT', -} -AMD_EXCEPTION_KIND_INVALID_OPERATION = 1 -AMD_EXCEPTION_KIND_DIVISION_BY_ZERO = 2 -AMD_EXCEPTION_KIND_OVERFLOW = 4 -AMD_EXCEPTION_KIND_UNDERFLOW = 8 -AMD_EXCEPTION_KIND_INEXACT = 16 -amd_exception_kind_t = ctypes.c_uint32 # enum -class struct_amd_control_directives_s(Structure): - pass - -struct_amd_control_directives_s._pack_ = 1 # source:False -struct_amd_control_directives_s._fields_ = [ - ('enabled_control_directives', ctypes.c_uint64), - ('enable_break_exceptions', ctypes.c_uint16), - ('enable_detect_exceptions', ctypes.c_uint16), - ('max_dynamic_group_size', ctypes.c_uint32), - ('max_flat_grid_size', ctypes.c_uint64), - ('max_flat_workgroup_size', ctypes.c_uint32), - ('required_dim', ctypes.c_ubyte), - ('reserved1', ctypes.c_ubyte * 3), - ('required_grid_size', ctypes.c_uint64 * 3), - ('required_workgroup_size', ctypes.c_uint32 * 3), - ('reserved2', ctypes.c_ubyte * 60), -] - -amd_control_directives_t = struct_amd_control_directives_s -class struct_amd_kernel_code_s(Structure): - pass - -struct_amd_kernel_code_s._pack_ = 1 # source:False -struct_amd_kernel_code_s._fields_ = [ - ('amd_kernel_code_version_major', ctypes.c_uint32), - ('amd_kernel_code_version_minor', ctypes.c_uint32), - ('amd_machine_kind', ctypes.c_uint16), - ('amd_machine_version_major', ctypes.c_uint16), - ('amd_machine_version_minor', ctypes.c_uint16), - ('amd_machine_version_stepping', ctypes.c_uint16), - ('kernel_code_entry_byte_offset', ctypes.c_int64), - ('kernel_code_prefetch_byte_offset', ctypes.c_int64), - ('kernel_code_prefetch_byte_size', ctypes.c_uint64), - ('max_scratch_backing_memory_byte_size', ctypes.c_uint64), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('kernel_code_properties', ctypes.c_uint32), - ('workitem_private_segment_byte_size', ctypes.c_uint32), - ('workgroup_group_segment_byte_size', ctypes.c_uint32), - ('gds_segment_byte_size', ctypes.c_uint32), - ('kernarg_segment_byte_size', ctypes.c_uint64), - ('workgroup_fbarrier_count', ctypes.c_uint32), - ('wavefront_sgpr_count', ctypes.c_uint16), - ('workitem_vgpr_count', ctypes.c_uint16), - ('reserved_vgpr_first', ctypes.c_uint16), - ('reserved_vgpr_count', ctypes.c_uint16), - ('reserved_sgpr_first', ctypes.c_uint16), - ('reserved_sgpr_count', ctypes.c_uint16), - ('debug_wavefront_private_segment_offset_sgpr', ctypes.c_uint16), - ('debug_private_segment_buffer_sgpr', ctypes.c_uint16), - ('kernarg_segment_alignment', ctypes.c_ubyte), - ('group_segment_alignment', ctypes.c_ubyte), - ('private_segment_alignment', ctypes.c_ubyte), - ('wavefront_size', ctypes.c_ubyte), - ('call_convention', ctypes.c_int32), - ('reserved1', ctypes.c_ubyte * 12), - ('runtime_loader_kernel_symbol', ctypes.c_uint64), - ('control_directives', amd_control_directives_t), -] - -amd_kernel_code_t = struct_amd_kernel_code_s -class struct_amd_runtime_loader_debug_info_s(Structure): - pass - -struct_amd_runtime_loader_debug_info_s._pack_ = 1 # source:False -struct_amd_runtime_loader_debug_info_s._fields_ = [ - ('elf_raw', ctypes.POINTER(None)), - ('elf_size', ctypes.c_uint64), - ('kernel_name', ctypes.POINTER(ctypes.c_char)), - ('owning_segment', ctypes.POINTER(None)), -] - -amd_runtime_loader_debug_info_t = struct_amd_runtime_loader_debug_info_s -class struct_BrigModuleHeader(Structure): - pass - -BrigModule_t = ctypes.POINTER(struct_BrigModuleHeader) - -# values for enumeration 'c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM' -c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM__enumvalues = { - 8192: 'HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 8193: 'HSA_EXT_STATUS_ERROR_INVALID_MODULE', - 8194: 'HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE', - 8195: 'HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED', - 8196: 'HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH', - 8197: 'HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED', - 8198: 'HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH', -} -HSA_EXT_STATUS_ERROR_INVALID_PROGRAM = 8192 -HSA_EXT_STATUS_ERROR_INVALID_MODULE = 8193 -HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE = 8194 -HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED = 8195 -HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH = 8196 -HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED = 8197 -HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH = 8198 -c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM = ctypes.c_uint32 # enum -hsa_ext_module_t = ctypes.POINTER(struct_BrigModuleHeader) -class struct_hsa_ext_program_s(Structure): - pass - -struct_hsa_ext_program_s._pack_ = 1 # source:False -struct_hsa_ext_program_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_ext_program_t = struct_hsa_ext_program_s -try: - hsa_ext_program_create = _libraries['libhsa-runtime64.so'].hsa_ext_program_create - hsa_ext_program_create.restype = hsa_status_t - hsa_ext_program_create.argtypes = [hsa_machine_model_t, hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_ext_program_s)] -except AttributeError: - pass -try: - hsa_ext_program_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_program_destroy - hsa_ext_program_destroy.restype = hsa_status_t - hsa_ext_program_destroy.argtypes = [hsa_ext_program_t] -except AttributeError: - pass -try: - hsa_ext_program_add_module = _libraries['libhsa-runtime64.so'].hsa_ext_program_add_module - hsa_ext_program_add_module.restype = hsa_status_t - hsa_ext_program_add_module.argtypes = [hsa_ext_program_t, hsa_ext_module_t] -except AttributeError: - pass -try: - hsa_ext_program_iterate_modules = _libraries['libhsa-runtime64.so'].hsa_ext_program_iterate_modules - hsa_ext_program_iterate_modules.restype = hsa_status_t - hsa_ext_program_iterate_modules.argtypes = [hsa_ext_program_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_ext_program_info_t' -c__EA_hsa_ext_program_info_t__enumvalues = { - 0: 'HSA_EXT_PROGRAM_INFO_MACHINE_MODEL', - 1: 'HSA_EXT_PROGRAM_INFO_PROFILE', - 2: 'HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_EXT_PROGRAM_INFO_MACHINE_MODEL = 0 -HSA_EXT_PROGRAM_INFO_PROFILE = 1 -HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 2 -c__EA_hsa_ext_program_info_t = ctypes.c_uint32 # enum -hsa_ext_program_info_t = c__EA_hsa_ext_program_info_t -hsa_ext_program_info_t__enumvalues = c__EA_hsa_ext_program_info_t__enumvalues -try: - hsa_ext_program_get_info = _libraries['libhsa-runtime64.so'].hsa_ext_program_get_info - hsa_ext_program_get_info.restype = hsa_status_t - hsa_ext_program_get_info.argtypes = [hsa_ext_program_t, hsa_ext_program_info_t, ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_ext_finalizer_call_convention_t' -c__EA_hsa_ext_finalizer_call_convention_t__enumvalues = { - -1: 'HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO', -} -HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO = -1 -c__EA_hsa_ext_finalizer_call_convention_t = ctypes.c_int32 # enum -hsa_ext_finalizer_call_convention_t = c__EA_hsa_ext_finalizer_call_convention_t -hsa_ext_finalizer_call_convention_t__enumvalues = c__EA_hsa_ext_finalizer_call_convention_t__enumvalues -class struct_hsa_ext_control_directives_s(Structure): - pass - -struct_hsa_ext_control_directives_s._pack_ = 1 # source:False -struct_hsa_ext_control_directives_s._fields_ = [ - ('control_directives_mask', ctypes.c_uint64), - ('break_exceptions_mask', ctypes.c_uint16), - ('detect_exceptions_mask', ctypes.c_uint16), - ('max_dynamic_group_size', ctypes.c_uint32), - ('max_flat_grid_size', ctypes.c_uint64), - ('max_flat_workgroup_size', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('required_grid_size', ctypes.c_uint64 * 3), - ('required_workgroup_size', hsa_dim3_t), - ('required_dim', ctypes.c_ubyte), - ('reserved2', ctypes.c_ubyte * 75), -] - -hsa_ext_control_directives_t = struct_hsa_ext_control_directives_s -try: - hsa_ext_program_finalize = _libraries['libhsa-runtime64.so'].hsa_ext_program_finalize - hsa_ext_program_finalize.restype = hsa_status_t - hsa_ext_program_finalize.argtypes = [hsa_ext_program_t, hsa_isa_t, int32_t, hsa_ext_control_directives_t, ctypes.POINTER(ctypes.c_char), hsa_code_object_type_t, ctypes.POINTER(struct_hsa_code_object_s)] -except AttributeError: - pass -class struct_hsa_ext_finalizer_1_00_pfn_s(Structure): - pass - -struct_hsa_ext_finalizer_1_00_pfn_s._pack_ = 1 # source:False -struct_hsa_ext_finalizer_1_00_pfn_s._fields_ = [ - ('hsa_ext_program_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_machine_model_t, c__EA_hsa_profile_t, c__EA_hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_ext_program_s))), - ('hsa_ext_program_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s)), - ('hsa_ext_program_add_module', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader))), - ('hsa_ext_program_iterate_modules', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ext_program_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, c__EA_hsa_ext_program_info_t, ctypes.POINTER(None))), - ('hsa_ext_program_finalize', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, struct_hsa_isa_s, ctypes.c_int32, struct_hsa_ext_control_directives_s, ctypes.POINTER(ctypes.c_char), c__EA_hsa_code_object_type_t, ctypes.POINTER(struct_hsa_code_object_s))), -] - -hsa_ext_finalizer_1_00_pfn_t = struct_hsa_ext_finalizer_1_00_pfn_s -try: - hsa_ven_amd_aqlprofile_version_major = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_version_major - hsa_ven_amd_aqlprofile_version_major.restype = uint32_t - hsa_ven_amd_aqlprofile_version_major.argtypes = [] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_version_minor = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_version_minor - hsa_ven_amd_aqlprofile_version_minor.restype = uint32_t - hsa_ven_amd_aqlprofile_version_minor.argtypes = [] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_event_type_t' -c__EA_hsa_ven_amd_aqlprofile_event_type_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC', - 1: 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE', -} -HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC = 0 -HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE = 1 -c__EA_hsa_ven_amd_aqlprofile_event_type_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_event_type_t = c__EA_hsa_ven_amd_aqlprofile_event_type_t -hsa_ven_amd_aqlprofile_event_type_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_event_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_block_name_t' -c__EA_hsa_ven_amd_aqlprofile_block_name_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC', - 1: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF', - 2: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS', - 3: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM', - 4: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE', - 5: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI', - 6: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ', - 7: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS', - 8: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM', - 9: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX', - 10: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA', - 11: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA', - 12: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC', - 13: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP', - 14: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD', - 15: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB', - 16: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB', - 17: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM', - 18: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ', - 19: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2', - 20: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR', - 21: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC', - 22: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2', - 23: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA', - 24: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB', - 25: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA', - 26: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A', - 27: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C', - 28: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A', - 29: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C', - 30: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR', - 31: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS', - 32: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC', - 33: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA', - 34: 'HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER', -} -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC = 0 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF = 1 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS = 2 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM = 3 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE = 4 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI = 5 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ = 6 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS = 7 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM = 8 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX = 9 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA = 10 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA = 11 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC = 12 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP = 13 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD = 14 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB = 15 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB = 16 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM = 17 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ = 18 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2 = 19 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR = 20 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC = 21 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2 = 22 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA = 23 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB = 24 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA = 25 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A = 26 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C = 27 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A = 28 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C = 29 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR = 30 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS = 31 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC = 32 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA = 33 -HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER = 34 -c__EA_hsa_ven_amd_aqlprofile_block_name_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_block_name_t = c__EA_hsa_ven_amd_aqlprofile_block_name_t -hsa_ven_amd_aqlprofile_block_name_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_block_name_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_event_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_event_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_event_t._fields_ = [ - ('block_name', hsa_ven_amd_aqlprofile_block_name_t), - ('block_index', ctypes.c_uint32), - ('counter_id', ctypes.c_uint32), -] - -hsa_ven_amd_aqlprofile_event_t = struct_c__SA_hsa_ven_amd_aqlprofile_event_t -try: - hsa_ven_amd_aqlprofile_validate_event = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_validate_event - hsa_ven_amd_aqlprofile_validate_event.restype = hsa_status_t - hsa_ven_amd_aqlprofile_validate_event.argtypes = [hsa_agent_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_parameter_name_t' -c__EA_hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET', - 1: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK', - 2: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK', - 3: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK', - 4: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2', - 5: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK', - 6: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE', - 7: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT', - 8: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION', - 9: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE', - 10: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE', - 240: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK', - 241: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL', - 242: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME', -} -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET = 0 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK = 1 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK = 2 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK = 3 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2 = 4 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK = 5 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE = 6 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT = 7 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION = 8 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE = 9 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE = 10 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK = 240 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL = 241 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME = 242 -c__EA_hsa_ven_amd_aqlprofile_parameter_name_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_parameter_name_t = c__EA_hsa_ven_amd_aqlprofile_parameter_name_t -hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t._fields_ = [ - ('parameter_name', hsa_ven_amd_aqlprofile_parameter_name_t), - ('value', ctypes.c_uint32), -] - -hsa_ven_amd_aqlprofile_parameter_t = struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t - -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t' -c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0', - 1: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1', - 2: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2', - 3: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3', -} -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0 = 0 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1 = 1 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2 = 2 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3 = 3 -c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_att_marker_channel_t = c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t -hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t._fields_ = [ - ('ptr', ctypes.POINTER(None)), - ('size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hsa_ven_amd_aqlprofile_descriptor_t = struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t -class struct_c__SA_hsa_ven_amd_aqlprofile_profile_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_profile_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_profile_t._fields_ = [ - ('agent', hsa_agent_t), - ('type', hsa_ven_amd_aqlprofile_event_type_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('events', ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t)), - ('event_count', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('parameters', ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t)), - ('parameter_count', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('output_buffer', hsa_ven_amd_aqlprofile_descriptor_t), - ('command_buffer', hsa_ven_amd_aqlprofile_descriptor_t), -] - -hsa_ven_amd_aqlprofile_profile_t = struct_c__SA_hsa_ven_amd_aqlprofile_profile_t -class struct_c__SA_hsa_ext_amd_aql_pm4_packet_t(Structure): - pass - -struct_c__SA_hsa_ext_amd_aql_pm4_packet_t._pack_ = 1 # source:False -struct_c__SA_hsa_ext_amd_aql_pm4_packet_t._fields_ = [ - ('header', ctypes.c_uint16), - ('pm4_command', ctypes.c_uint16 * 27), - ('completion_signal', hsa_signal_t), -] - -hsa_ext_amd_aql_pm4_packet_t = struct_c__SA_hsa_ext_amd_aql_pm4_packet_t -try: - hsa_ven_amd_aqlprofile_start = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_start - hsa_ven_amd_aqlprofile_start.restype = hsa_status_t - hsa_ven_amd_aqlprofile_start.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_stop = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_stop - hsa_ven_amd_aqlprofile_stop.restype = hsa_status_t - hsa_ven_amd_aqlprofile_stop.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_read = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_read - hsa_ven_amd_aqlprofile_read.restype = hsa_status_t - hsa_ven_amd_aqlprofile_read.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE = 192 # Variable ctypes.c_uint32 -try: - hsa_ven_amd_aqlprofile_legacy_get_pm4 = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_legacy_get_pm4 - hsa_ven_amd_aqlprofile_legacy_get_pm4.restype = hsa_status_t - hsa_ven_amd_aqlprofile_legacy_get_pm4.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_att_marker = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_att_marker - hsa_ven_amd_aqlprofile_att_marker.restype = hsa_status_t - hsa_ven_amd_aqlprofile_att_marker.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), uint32_t, hsa_ven_amd_aqlprofile_att_marker_channel_t] -except AttributeError: - pass -class struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t(Structure): - pass - -class union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0(Union): - pass - -class struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data._fields_ = [ - ('event', hsa_ven_amd_aqlprofile_event_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('result', ctypes.c_uint64), -] - -union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0._pack_ = 1 # source:False -union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0._fields_ = [ - ('pmc_data', struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data), - ('trace_data', hsa_ven_amd_aqlprofile_descriptor_t), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._anonymous_ = ('_0',) -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._fields_ = [ - ('sample_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0), -] - -hsa_ven_amd_aqlprofile_info_data_t = struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t -class struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t._fields_ = [ - ('name', ctypes.POINTER(ctypes.c_char)), - ('id', ctypes.c_uint32), - ('instance_count', ctypes.c_uint32), -] - -hsa_ven_amd_aqlprofile_id_query_t = struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t - -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_info_type_t' -c__EA_hsa_ven_amd_aqlprofile_info_type_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE', - 1: 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE', - 2: 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA', - 3: 'HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA', - 4: 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS', - 5: 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID', - 6: 'HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD', - 7: 'HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD', -} -HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE = 0 -HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE = 1 -HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA = 2 -HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA = 3 -HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS = 4 -HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID = 5 -HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD = 6 -HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD = 7 -c__EA_hsa_ven_amd_aqlprofile_info_type_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_info_type_t = c__EA_hsa_ven_amd_aqlprofile_info_type_t -hsa_ven_amd_aqlprofile_info_type_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_info_type_t__enumvalues -hsa_ven_amd_aqlprofile_data_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t), ctypes.POINTER(None)) -try: - hsa_ven_amd_aqlprofile_get_info = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_get_info - hsa_ven_amd_aqlprofile_get_info.restype = hsa_status_t - hsa_ven_amd_aqlprofile_get_info.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_iterate_data = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_data - hsa_ven_amd_aqlprofile_iterate_data.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_data.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_data_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_error_string = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_error_string - hsa_ven_amd_aqlprofile_error_string.restype = hsa_status_t - hsa_ven_amd_aqlprofile_error_string.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -hsa_ven_amd_aqlprofile_eventname_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_char)) -try: - hsa_ven_amd_aqlprofile_iterate_event_ids = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_event_ids - hsa_ven_amd_aqlprofile_iterate_event_ids.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_event_ids.argtypes = [hsa_ven_amd_aqlprofile_eventname_callback_t] -except AttributeError: - pass -hsa_ven_amd_aqlprofile_coordinate_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)) -try: - hsa_ven_amd_aqlprofile_iterate_event_coord = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_event_coord - hsa_ven_amd_aqlprofile_iterate_event_coord.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_event_coord.argtypes = [hsa_agent_t, hsa_ven_amd_aqlprofile_event_t, uint32_t, hsa_ven_amd_aqlprofile_coordinate_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -kAqlProfileLib = 'libhsa-amd-aqlprofile64.so' # Variable ctypes.c_char * 27 -class struct_hsa_ven_amd_aqlprofile_1_00_pfn_s(Structure): - pass - -struct_hsa_ven_amd_aqlprofile_1_00_pfn_s._pack_ = 1 # source:False -struct_hsa_ven_amd_aqlprofile_1_00_pfn_s._fields_ = [ - ('hsa_ven_amd_aqlprofile_version_major', ctypes.CFUNCTYPE(ctypes.c_uint32)), - ('hsa_ven_amd_aqlprofile_version_minor', ctypes.CFUNCTYPE(ctypes.c_uint32)), - ('hsa_ven_amd_aqlprofile_error_string', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)))), - ('hsa_ven_amd_aqlprofile_validate_event', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool))), - ('hsa_ven_amd_aqlprofile_start', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_stop', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_read', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_legacy_get_pm4', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_iterate_data', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_iterate_event_ids', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_char)))), - ('hsa_ven_amd_aqlprofile_iterate_event_coord', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_c__SA_hsa_ven_amd_aqlprofile_event_t, ctypes.c_uint32, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_att_marker', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.c_uint32, c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t)), -] - -hsa_ven_amd_aqlprofile_1_00_pfn_t = struct_hsa_ven_amd_aqlprofile_1_00_pfn_s -hsa_ven_amd_aqlprofile_pfn_t = struct_hsa_ven_amd_aqlprofile_1_00_pfn_s -__all__ = \ - ['AMD_COMPUTE_PGM_RSRC_ONE_BULKY', - 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH', - 'AMD_ELEMENT_BYTE_SIZE_16', 'AMD_ELEMENT_BYTE_SIZE_2', - 'AMD_ELEMENT_BYTE_SIZE_4', 'AMD_ELEMENT_BYTE_SIZE_8', - 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS', - 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS', - 'AMD_EXCEPTION_KIND_DIVISION_BY_ZERO', - 'AMD_EXCEPTION_KIND_INEXACT', - 'AMD_EXCEPTION_KIND_INVALID_OPERATION', - 'AMD_EXCEPTION_KIND_OVERFLOW', 'AMD_EXCEPTION_KIND_UNDERFLOW', - 'AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT', - 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE', - 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT', - 'AMD_FLOAT_DENORM_MODE_NO_FLUSH', - 'AMD_FLOAT_ROUND_MODE_MINUS_INFINITY', - 'AMD_FLOAT_ROUND_MODE_NEAREST_EVEN', - 'AMD_FLOAT_ROUND_MODE_PLUS_INFINITY', 'AMD_FLOAT_ROUND_MODE_ZERO', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH', - 'AMD_KERNEL_CODE_VERSION_MAJOR', 'AMD_KERNEL_CODE_VERSION_MINOR', - 'AMD_MACHINE_KIND_AMDGPU', 'AMD_MACHINE_KIND_UNDEFINED', - 'AMD_POWERTWO_1', 'AMD_POWERTWO_128', 'AMD_POWERTWO_16', - 'AMD_POWERTWO_2', 'AMD_POWERTWO_256', 'AMD_POWERTWO_32', - 'AMD_POWERTWO_4', 'AMD_POWERTWO_64', 'AMD_POWERTWO_8', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH', - 'AMD_QUEUE_PROPERTIES_IS_PTR64', - 'AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT', - 'AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH', - 'AMD_QUEUE_PROPERTIES_RESERVED1', - 'AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT', - 'AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH', - 'AMD_SIGNAL_KIND_DOORBELL', 'AMD_SIGNAL_KIND_INVALID', - 'AMD_SIGNAL_KIND_LEGACY_DOORBELL', 'AMD_SIGNAL_KIND_USER', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z', 'BrigModule_t', - 'HSA_ACCESS_PERMISSION_NONE', 'HSA_ACCESS_PERMISSION_RO', - 'HSA_ACCESS_PERMISSION_RW', 'HSA_ACCESS_PERMISSION_WO', - 'HSA_AGENT_FEATURE_AGENT_DISPATCH', - 'HSA_AGENT_FEATURE_KERNEL_DISPATCH', - 'HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_AGENT_INFO_CACHE_SIZE', - 'HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_AGENT_INFO_DEVICE', 'HSA_AGENT_INFO_EXTENSIONS', - 'HSA_AGENT_INFO_FAST_F16_OPERATION', - 'HSA_AGENT_INFO_FBARRIER_MAX_SIZE', 'HSA_AGENT_INFO_FEATURE', - 'HSA_AGENT_INFO_GRID_MAX_DIM', 'HSA_AGENT_INFO_GRID_MAX_SIZE', - 'HSA_AGENT_INFO_ISA', 'HSA_AGENT_INFO_LAST', - 'HSA_AGENT_INFO_MACHINE_MODEL', 'HSA_AGENT_INFO_NAME', - 'HSA_AGENT_INFO_NODE', 'HSA_AGENT_INFO_PROFILE', - 'HSA_AGENT_INFO_QUEUES_MAX', 'HSA_AGENT_INFO_QUEUE_MAX_SIZE', - 'HSA_AGENT_INFO_QUEUE_MIN_SIZE', 'HSA_AGENT_INFO_QUEUE_TYPE', - 'HSA_AGENT_INFO_VENDOR_NAME', 'HSA_AGENT_INFO_VERSION_MAJOR', - 'HSA_AGENT_INFO_VERSION_MINOR', 'HSA_AGENT_INFO_WAVEFRONT_SIZE', - 'HSA_AGENT_INFO_WORKGROUP_MAX_DIM', - 'HSA_AGENT_INFO_WORKGROUP_MAX_SIZE', - 'HSA_AMD_AGENT_INFO_AQL_EXTENSIONS', - 'HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID', - 'HSA_AMD_AGENT_INFO_ASIC_REVISION', 'HSA_AMD_AGENT_INFO_BDFID', - 'HSA_AMD_AGENT_INFO_CACHELINE_SIZE', 'HSA_AMD_AGENT_INFO_CHIP_ID', - 'HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT', - 'HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT', - 'HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES', - 'HSA_AMD_AGENT_INFO_DOMAIN', 'HSA_AMD_AGENT_INFO_DRIVER_NODE_ID', - 'HSA_AMD_AGENT_INFO_DRIVER_UID', 'HSA_AMD_AGENT_INFO_HDP_FLUSH', - 'HSA_AMD_AGENT_INFO_IOMMU_SUPPORT', - 'HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS', - 'HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY', - 'HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU', - 'HSA_AMD_AGENT_INFO_MEMORY_AVAIL', - 'HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY', - 'HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES', - 'HSA_AMD_AGENT_INFO_MEMORY_WIDTH', - 'HSA_AMD_AGENT_INFO_NEAREST_CPU', - 'HSA_AMD_AGENT_INFO_NUM_SDMA_ENG', - 'HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG', - 'HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE', - 'HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES', - 'HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU', - 'HSA_AMD_AGENT_INFO_NUM_XCC', 'HSA_AMD_AGENT_INFO_PRODUCT_NAME', - 'HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION', - 'HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS', - 'HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY', - 'HSA_AMD_AGENT_INFO_UCODE_VERSION', 'HSA_AMD_AGENT_INFO_UUID', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS', - 'HSA_AMD_COHERENCY_TYPE_COHERENT', - 'HSA_AMD_COHERENCY_TYPE_NONCOHERENT', 'HSA_AMD_FIRST_EXTENSION', - 'HSA_AMD_GPU_HW_EXCEPTION_EVENT', - 'HSA_AMD_GPU_MEMORY_FAULT_EVENT', - 'HSA_AMD_HW_EXCEPTION_CAUSE_ECC', - 'HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG', - 'HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER', 'HSA_AMD_LAST_EXTENSION', - 'HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT', - 'HSA_AMD_LINK_INFO_TYPE_INFINBAND', 'HSA_AMD_LINK_INFO_TYPE_PCIE', - 'HSA_AMD_LINK_INFO_TYPE_QPI', 'HSA_AMD_LINK_INFO_TYPE_XGMI', - 'HSA_AMD_MEMORY_FAULT_DRAMECC', 'HSA_AMD_MEMORY_FAULT_HANG', - 'HSA_AMD_MEMORY_FAULT_HOST_ONLY', - 'HSA_AMD_MEMORY_FAULT_IMPRECISE', 'HSA_AMD_MEMORY_FAULT_NX', - 'HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT', - 'HSA_AMD_MEMORY_FAULT_READ_ONLY', 'HSA_AMD_MEMORY_FAULT_SRAMECC', - 'HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT', - 'HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT', - 'HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED', - 'HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT', - 'HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL', - 'HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE', - 'HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS', - 'HSA_AMD_MEMORY_POOL_INFO_LOCATION', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE', - 'HSA_AMD_MEMORY_POOL_INFO_SEGMENT', - 'HSA_AMD_MEMORY_POOL_INFO_SIZE', - 'HSA_AMD_MEMORY_POOL_LOCATION_CPU', - 'HSA_AMD_MEMORY_POOL_LOCATION_GPU', - 'HSA_AMD_MEMORY_POOL_PCIE_FLAG', - 'HSA_AMD_MEMORY_POOL_STANDARD_FLAG', - 'HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU', - 'HSA_AMD_PACKET_TYPE_BARRIER_VALUE', 'HSA_AMD_QUEUE_INFO_AGENT', - 'HSA_AMD_QUEUE_INFO_DOORBELL_ID', 'HSA_AMD_QUEUE_PRIORITY_HIGH', - 'HSA_AMD_QUEUE_PRIORITY_LOW', 'HSA_AMD_QUEUE_PRIORITY_NORMAL', - 'HSA_AMD_REGION_INFO_BASE', 'HSA_AMD_REGION_INFO_BUS_WIDTH', - 'HSA_AMD_REGION_INFO_HOST_ACCESSIBLE', - 'HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY', - 'HSA_AMD_SDMA_ENGINE_0', 'HSA_AMD_SDMA_ENGINE_1', - 'HSA_AMD_SDMA_ENGINE_10', 'HSA_AMD_SDMA_ENGINE_11', - 'HSA_AMD_SDMA_ENGINE_12', 'HSA_AMD_SDMA_ENGINE_13', - 'HSA_AMD_SDMA_ENGINE_14', 'HSA_AMD_SDMA_ENGINE_15', - 'HSA_AMD_SDMA_ENGINE_2', 'HSA_AMD_SDMA_ENGINE_3', - 'HSA_AMD_SDMA_ENGINE_4', 'HSA_AMD_SDMA_ENGINE_5', - 'HSA_AMD_SDMA_ENGINE_6', 'HSA_AMD_SDMA_ENGINE_7', - 'HSA_AMD_SDMA_ENGINE_8', 'HSA_AMD_SDMA_ENGINE_9', - 'HSA_AMD_SEGMENT_GLOBAL', 'HSA_AMD_SEGMENT_GROUP', - 'HSA_AMD_SEGMENT_PRIVATE', 'HSA_AMD_SEGMENT_READONLY', - 'HSA_AMD_SIGNAL_AMD_GPU_ONLY', 'HSA_AMD_SIGNAL_IPC', - 'HSA_AMD_SVM_ATTRIB_ACCESS_QUERY', - 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE', - 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE', - 'HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS', - 'HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG', 'HSA_AMD_SVM_ATTRIB_GPU_EXEC', - 'HSA_AMD_SVM_ATTRIB_HIVE_LOCAL', - 'HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY', - 'HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION', - 'HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION', - 'HSA_AMD_SVM_ATTRIB_READ_MOSTLY', 'HSA_AMD_SVM_ATTRIB_READ_ONLY', - 'HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE', - 'HSA_AMD_SYSTEM_INFO_BUILD_VERSION', - 'HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR', - 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR', - 'HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED', - 'HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT', - 'HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_XNACK_ENABLED', 'HSA_CACHE_INFO_LEVEL', - 'HSA_CACHE_INFO_NAME', 'HSA_CACHE_INFO_NAME_LENGTH', - 'HSA_CACHE_INFO_SIZE', - 'HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_CODE_OBJECT_INFO_ISA', 'HSA_CODE_OBJECT_INFO_MACHINE_MODEL', - 'HSA_CODE_OBJECT_INFO_PROFILE', 'HSA_CODE_OBJECT_INFO_TYPE', - 'HSA_CODE_OBJECT_INFO_VERSION', 'HSA_CODE_OBJECT_TYPE_PROGRAM', - 'HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 'HSA_CODE_SYMBOL_INFO_IS_DEFINITION', - 'HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 'HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 'HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE', - 'HSA_CODE_SYMBOL_INFO_LINKAGE', - 'HSA_CODE_SYMBOL_INFO_MODULE_NAME', - 'HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 'HSA_CODE_SYMBOL_INFO_NAME', 'HSA_CODE_SYMBOL_INFO_NAME_LENGTH', - 'HSA_CODE_SYMBOL_INFO_TYPE', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO', 'HSA_DEVICE_TYPE_CPU', - 'HSA_DEVICE_TYPE_DSP', 'HSA_DEVICE_TYPE_GPU', - 'HSA_ENDIANNESS_BIG', 'HSA_ENDIANNESS_LITTLE', - 'HSA_EXCEPTION_POLICY_BREAK', 'HSA_EXCEPTION_POLICY_DETECT', - 'HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_EXECUTABLE_INFO_PROFILE', 'HSA_EXECUTABLE_INFO_STATE', - 'HSA_EXECUTABLE_STATE_FROZEN', 'HSA_EXECUTABLE_STATE_UNFROZEN', - 'HSA_EXECUTABLE_SYMBOL_INFO_AGENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT', - 'HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE', - 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME', - 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 'HSA_EXECUTABLE_SYMBOL_INFO_NAME', - 'HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH', - 'HSA_EXECUTABLE_SYMBOL_INFO_TYPE', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE', - 'HSA_EXTENSION_AMD_AQLPROFILE', 'HSA_EXTENSION_AMD_LOADER', - 'HSA_EXTENSION_AMD_PC_SAMPLING', 'HSA_EXTENSION_AMD_PROFILER', - 'HSA_EXTENSION_FINALIZER', 'HSA_EXTENSION_IMAGES', - 'HSA_EXTENSION_PERFORMANCE_COUNTERS', - 'HSA_EXTENSION_PROFILING_EVENTS', 'HSA_EXTENSION_STD_LAST', - 'HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS', - 'HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT', - 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES', - 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES', - 'HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS', - 'HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO', - 'HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT', - 'HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED', - 'HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE', - 'HSA_EXT_IMAGE_CAPABILITY_READ_ONLY', - 'HSA_EXT_IMAGE_CAPABILITY_READ_WRITE', - 'HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_A', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_R', 'HSA_EXT_IMAGE_CHANNEL_ORDER_RA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RG', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8', - 'HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR', - 'HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE', 'HSA_EXT_IMAGE_GEOMETRY_1D', - 'HSA_EXT_IMAGE_GEOMETRY_1DA', 'HSA_EXT_IMAGE_GEOMETRY_1DB', - 'HSA_EXT_IMAGE_GEOMETRY_2D', 'HSA_EXT_IMAGE_GEOMETRY_2DA', - 'HSA_EXT_IMAGE_GEOMETRY_2DADEPTH', - 'HSA_EXT_IMAGE_GEOMETRY_2DDEPTH', 'HSA_EXT_IMAGE_GEOMETRY_3D', - 'HSA_EXT_POINTER_TYPE_GRAPHICS', 'HSA_EXT_POINTER_TYPE_HSA', - 'HSA_EXT_POINTER_TYPE_IPC', 'HSA_EXT_POINTER_TYPE_LOCKED', - 'HSA_EXT_POINTER_TYPE_UNKNOWN', - 'HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_EXT_PROGRAM_INFO_MACHINE_MODEL', - 'HSA_EXT_PROGRAM_INFO_PROFILE', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED', - 'HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED', - 'HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED', - 'HSA_EXT_SAMPLER_FILTER_MODE_LINEAR', - 'HSA_EXT_SAMPLER_FILTER_MODE_NEAREST', - 'HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH', - 'HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED', - 'HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE', - 'HSA_EXT_STATUS_ERROR_INVALID_MODULE', - 'HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 'HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED', - 'HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH', 'HSA_FENCE_SCOPE_AGENT', - 'HSA_FENCE_SCOPE_NONE', 'HSA_FENCE_SCOPE_SYSTEM', - 'HSA_FLUSH_MODE_FTZ', 'HSA_FLUSH_MODE_NON_FTZ', 'HSA_FP_TYPE_16', - 'HSA_FP_TYPE_32', 'HSA_FP_TYPE_64', 'HSA_IOMMU_SUPPORT_NONE', - 'HSA_IOMMU_SUPPORT_V2', - 'HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_ISA_INFO_CALL_CONVENTION_COUNT', - 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT', - 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE', - 'HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_ISA_INFO_FAST_F16_OPERATION', - 'HSA_ISA_INFO_FBARRIER_MAX_SIZE', 'HSA_ISA_INFO_GRID_MAX_DIM', - 'HSA_ISA_INFO_GRID_MAX_SIZE', 'HSA_ISA_INFO_MACHINE_MODELS', - 'HSA_ISA_INFO_NAME', 'HSA_ISA_INFO_NAME_LENGTH', - 'HSA_ISA_INFO_PROFILES', 'HSA_ISA_INFO_WORKGROUP_MAX_DIM', - 'HSA_ISA_INFO_WORKGROUP_MAX_SIZE', - 'HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS', - 'HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS', - 'HSA_MACHINE_MODEL_LARGE', 'HSA_MACHINE_MODEL_SMALL', - 'HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_BARRIER', - 'HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_TYPE', - 'HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_BARRIER', - 'HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_TYPE', 'HSA_PACKET_TYPE_AGENT_DISPATCH', - 'HSA_PACKET_TYPE_BARRIER_AND', 'HSA_PACKET_TYPE_BARRIER_OR', - 'HSA_PACKET_TYPE_INVALID', 'HSA_PACKET_TYPE_KERNEL_DISPATCH', - 'HSA_PACKET_TYPE_VENDOR_SPECIFIC', 'HSA_PROFILE_BASE', - 'HSA_PROFILE_FULL', 'HSA_QUEUE_FEATURE_AGENT_DISPATCH', - 'HSA_QUEUE_FEATURE_KERNEL_DISPATCH', 'HSA_QUEUE_TYPE_COOPERATIVE', - 'HSA_QUEUE_TYPE_MULTI', 'HSA_QUEUE_TYPE_SINGLE', - 'HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_KERNARG', - 'HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE', - 'HSA_REGION_INFO_ALLOC_MAX_SIZE', 'HSA_REGION_INFO_GLOBAL_FLAGS', - 'HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT', - 'HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED', - 'HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE', - 'HSA_REGION_INFO_SEGMENT', 'HSA_REGION_INFO_SIZE', - 'HSA_REGION_SEGMENT_GLOBAL', 'HSA_REGION_SEGMENT_GROUP', - 'HSA_REGION_SEGMENT_KERNARG', 'HSA_REGION_SEGMENT_PRIVATE', - 'HSA_REGION_SEGMENT_READONLY', 'HSA_ROUND_METHOD_DOUBLE', - 'HSA_ROUND_METHOD_SINGLE', 'HSA_SIGNAL_CONDITION_EQ', - 'HSA_SIGNAL_CONDITION_GTE', 'HSA_SIGNAL_CONDITION_LT', - 'HSA_SIGNAL_CONDITION_NE', 'HSA_STATUS_CU_MASK_REDUCED', - 'HSA_STATUS_ERROR', 'HSA_STATUS_ERROR_EXCEPTION', - 'HSA_STATUS_ERROR_FATAL', 'HSA_STATUS_ERROR_FROZEN_EXECUTABLE', - 'HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION', - 'HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS', - 'HSA_STATUS_ERROR_INVALID_AGENT', - 'HSA_STATUS_ERROR_INVALID_ALLOCATION', - 'HSA_STATUS_ERROR_INVALID_ARGUMENT', - 'HSA_STATUS_ERROR_INVALID_CACHE', - 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT', - 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER', - 'HSA_STATUS_ERROR_INVALID_CODE_SYMBOL', - 'HSA_STATUS_ERROR_INVALID_EXECUTABLE', - 'HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL', - 'HSA_STATUS_ERROR_INVALID_FILE', 'HSA_STATUS_ERROR_INVALID_INDEX', - 'HSA_STATUS_ERROR_INVALID_ISA', - 'HSA_STATUS_ERROR_INVALID_ISA_NAME', - 'HSA_STATUS_ERROR_INVALID_MEMORY_POOL', - 'HSA_STATUS_ERROR_INVALID_PACKET_FORMAT', - 'HSA_STATUS_ERROR_INVALID_QUEUE', - 'HSA_STATUS_ERROR_INVALID_QUEUE_CREATION', - 'HSA_STATUS_ERROR_INVALID_REGION', - 'HSA_STATUS_ERROR_INVALID_RUNTIME_STATE', - 'HSA_STATUS_ERROR_INVALID_SIGNAL', - 'HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP', - 'HSA_STATUS_ERROR_INVALID_SYMBOL_NAME', - 'HSA_STATUS_ERROR_INVALID_WAVEFRONT', - 'HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION', - 'HSA_STATUS_ERROR_MEMORY_FAULT', - 'HSA_STATUS_ERROR_NOT_INITIALIZED', - 'HSA_STATUS_ERROR_OUT_OF_REGISTERS', - 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', - 'HSA_STATUS_ERROR_REFCOUNT_OVERFLOW', - 'HSA_STATUS_ERROR_RESOURCE_BUSY', - 'HSA_STATUS_ERROR_RESOURCE_FREE', - 'HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED', - 'HSA_STATUS_ERROR_VARIABLE_UNDEFINED', 'HSA_STATUS_INFO_BREAK', - 'HSA_STATUS_SUCCESS', 'HSA_SYMBOL_KIND_INDIRECT_FUNCTION', - 'HSA_SYMBOL_KIND_KERNEL', 'HSA_SYMBOL_KIND_VARIABLE', - 'HSA_SYMBOL_LINKAGE_MODULE', 'HSA_SYMBOL_LINKAGE_PROGRAM', - 'HSA_SYSTEM_INFO_ENDIANNESS', 'HSA_SYSTEM_INFO_EXTENSIONS', - 'HSA_SYSTEM_INFO_MACHINE_MODEL', - 'HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT', 'HSA_SYSTEM_INFO_TIMESTAMP', - 'HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY', - 'HSA_SYSTEM_INFO_VERSION_MAJOR', 'HSA_SYSTEM_INFO_VERSION_MINOR', - 'HSA_VARIABLE_ALLOCATION_AGENT', - 'HSA_VARIABLE_ALLOCATION_PROGRAM', 'HSA_VARIABLE_SEGMENT_GLOBAL', - 'HSA_VARIABLE_SEGMENT_READONLY', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3', - 'HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC', - 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC', - 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS', - 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID', - 'HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD', - 'HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD', - 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA', - 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA', - 'HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK', - 'HSA_WAIT_STATE_ACTIVE', 'HSA_WAIT_STATE_BLOCKED', - 'HSA_WAVEFRONT_INFO_SIZE', 'MEMORY_TYPE_NONE', - 'MEMORY_TYPE_PINNED', 'amd_compute_pgm_rsrc_one32_t', - 'amd_compute_pgm_rsrc_one_t', 'amd_compute_pgm_rsrc_two32_t', - 'amd_compute_pgm_rsrc_two_t', 'amd_control_directives_t', - 'amd_element_byte_size_t', 'amd_enabled_control_directive64_t', - 'amd_enabled_control_directive_t', 'amd_exception_kind16_t', - 'amd_exception_kind_t', 'amd_float_denorm_mode_t', - 'amd_float_round_mode_t', 'amd_kernel_code_properties32_t', - 'amd_kernel_code_properties_t', 'amd_kernel_code_t', - 'amd_kernel_code_version32_t', 'amd_kernel_code_version_t', - 'amd_machine_kind16_t', 'amd_machine_kind_t', - 'amd_machine_version16_t', 'amd_powertwo8_t', 'amd_powertwo_t', - 'amd_queue_capabilities32_t', 'amd_queue_capabilities_t', - 'amd_queue_properties32_t', 'amd_queue_properties_t', - 'amd_queue_t', 'amd_runtime_loader_debug_info_t', - 'amd_signal_kind64_t', 'amd_signal_kind_t', 'amd_signal_t', - 'amd_system_vgpr_workitem_id_t', 'c__EA_hsa_access_permission_t', - 'c__EA_hsa_agent_feature_t', 'c__EA_hsa_agent_info_t', - 'c__EA_hsa_amd_agent_memory_pool_info_t', - 'c__EA_hsa_amd_copy_direction_t', - 'c__EA_hsa_amd_hw_exception_reset_cause_t', - 'c__EA_hsa_amd_hw_exception_reset_type_t', - 'c__EA_hsa_amd_iommu_version_t', 'c__EA_hsa_amd_link_info_type_t', - 'c__EA_hsa_amd_memory_fault_reason_t', - 'c__EA_hsa_amd_memory_pool_access_t', - 'c__EA_hsa_amd_memory_pool_info_t', 'c__EA_hsa_amd_memory_type_t', - 'c__EA_hsa_amd_packet_type_t', 'c__EA_hsa_amd_pointer_type_t', - 'c__EA_hsa_amd_segment_t', 'c__EA_hsa_amd_signal_attribute_t', - 'c__EA_hsa_cache_info_t', 'c__EA_hsa_code_object_info_t', - 'c__EA_hsa_code_object_type_t', 'c__EA_hsa_code_symbol_info_t', - 'c__EA_hsa_default_float_rounding_mode_t', - 'c__EA_hsa_device_type_t', 'c__EA_hsa_endianness_t', - 'c__EA_hsa_exception_policy_t', 'c__EA_hsa_executable_info_t', - 'c__EA_hsa_executable_state_t', - 'c__EA_hsa_executable_symbol_info_t', - 'c__EA_hsa_ext_finalizer_call_convention_t', - 'c__EA_hsa_ext_image_capability_t', - 'c__EA_hsa_ext_image_channel_order_t', - 'c__EA_hsa_ext_image_channel_type_t', - 'c__EA_hsa_ext_image_data_layout_t', - 'c__EA_hsa_ext_image_geometry_t', 'c__EA_hsa_ext_program_info_t', - 'c__EA_hsa_ext_sampler_addressing_mode_t', - 'c__EA_hsa_ext_sampler_coordinate_mode_t', - 'c__EA_hsa_ext_sampler_filter_mode_t', 'c__EA_hsa_extension_t', - 'c__EA_hsa_fence_scope_t', 'c__EA_hsa_flush_mode_t', - 'c__EA_hsa_fp_type_t', 'c__EA_hsa_isa_info_t', - 'c__EA_hsa_kernel_dispatch_packet_setup_t', - 'c__EA_hsa_kernel_dispatch_packet_setup_width_t', - 'c__EA_hsa_machine_model_t', 'c__EA_hsa_packet_header_t', - 'c__EA_hsa_packet_header_width_t', 'c__EA_hsa_packet_type_t', - 'c__EA_hsa_profile_t', 'c__EA_hsa_queue_feature_t', - 'c__EA_hsa_queue_info_attribute_t', 'c__EA_hsa_queue_type_t', - 'c__EA_hsa_region_global_flag_t', 'c__EA_hsa_region_info_t', - 'c__EA_hsa_region_segment_t', 'c__EA_hsa_round_method_t', - 'c__EA_hsa_signal_condition_t', 'c__EA_hsa_status_t', - 'c__EA_hsa_symbol_kind_t', 'c__EA_hsa_symbol_linkage_t', - 'c__EA_hsa_system_info_t', 'c__EA_hsa_variable_allocation_t', - 'c__EA_hsa_variable_segment_t', - 'c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t', - 'c__EA_hsa_ven_amd_aqlprofile_block_name_t', - 'c__EA_hsa_ven_amd_aqlprofile_event_type_t', - 'c__EA_hsa_ven_amd_aqlprofile_info_type_t', - 'c__EA_hsa_ven_amd_aqlprofile_parameter_name_t', - 'c__EA_hsa_wait_state_t', 'c__EA_hsa_wavefront_info_t', - 'c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 'c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 'c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 'c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL', 'hsaDeviceToDevice', - 'hsaDeviceToHost', 'hsaHostToDevice', 'hsaHostToHost', - 'hsa_access_permission_t', 'hsa_access_permission_t__enumvalues', - 'hsa_agent_dispatch_packet_t', 'hsa_agent_extension_supported', - 'hsa_agent_feature_t', 'hsa_agent_feature_t__enumvalues', - 'hsa_agent_get_exception_policies', 'hsa_agent_get_info', - 'hsa_agent_info_t', 'hsa_agent_info_t__enumvalues', - 'hsa_agent_iterate_caches', 'hsa_agent_iterate_isas', - 'hsa_agent_iterate_regions', - 'hsa_agent_major_extension_supported', 'hsa_agent_t', - 'hsa_amd_agent_info_s', 'hsa_amd_agent_info_t', - 'hsa_amd_agent_info_t__enumvalues', - 'hsa_amd_agent_iterate_memory_pools', - 'hsa_amd_agent_memory_pool_get_info', - 'hsa_amd_agent_memory_pool_info_t', - 'hsa_amd_agent_memory_pool_info_t__enumvalues', - 'hsa_amd_agent_memory_properties_s', - 'hsa_amd_agent_memory_properties_t', - 'hsa_amd_agent_memory_properties_t__enumvalues', - 'hsa_amd_agent_set_async_scratch_limit', - 'hsa_amd_agents_allow_access', 'hsa_amd_async_function', - 'hsa_amd_barrier_value_packet_t', 'hsa_amd_coherency_get_type', - 'hsa_amd_coherency_set_type', 'hsa_amd_coherency_type_s', - 'hsa_amd_coherency_type_t', - 'hsa_amd_coherency_type_t__enumvalues', - 'hsa_amd_copy_direction_t', - 'hsa_amd_copy_direction_t__enumvalues', - 'hsa_amd_deallocation_callback_t', - 'hsa_amd_deregister_deallocation_callback', 'hsa_amd_event_t', - 'hsa_amd_event_type_s', 'hsa_amd_event_type_t', - 'hsa_amd_event_type_t__enumvalues', - 'hsa_amd_gpu_hw_exception_info_t', - 'hsa_amd_gpu_memory_fault_info_t', 'hsa_amd_hdp_flush_t', - 'hsa_amd_hw_exception_reset_cause_t', - 'hsa_amd_hw_exception_reset_cause_t__enumvalues', - 'hsa_amd_hw_exception_reset_type_t', - 'hsa_amd_hw_exception_reset_type_t__enumvalues', - 'hsa_amd_image_create', 'hsa_amd_image_descriptor_t', - 'hsa_amd_image_get_info_max_dim', 'hsa_amd_interop_map_buffer', - 'hsa_amd_interop_unmap_buffer', 'hsa_amd_iommu_version_t', - 'hsa_amd_iommu_version_t__enumvalues', - 'hsa_amd_ipc_memory_attach', 'hsa_amd_ipc_memory_create', - 'hsa_amd_ipc_memory_detach', 'hsa_amd_ipc_memory_t', - 'hsa_amd_ipc_signal_attach', 'hsa_amd_ipc_signal_create', - 'hsa_amd_ipc_signal_t', 'hsa_amd_link_info_type_t', - 'hsa_amd_link_info_type_t__enumvalues', - 'hsa_amd_memory_access_desc_t', 'hsa_amd_memory_async_copy', - 'hsa_amd_memory_async_copy_on_engine', - 'hsa_amd_memory_async_copy_rect', - 'hsa_amd_memory_copy_engine_status', - 'hsa_amd_memory_fault_reason_t', - 'hsa_amd_memory_fault_reason_t__enumvalues', - 'hsa_amd_memory_fill', 'hsa_amd_memory_lock', - 'hsa_amd_memory_lock_to_pool', 'hsa_amd_memory_migrate', - 'hsa_amd_memory_pool_access_t', - 'hsa_amd_memory_pool_access_t__enumvalues', - 'hsa_amd_memory_pool_allocate', 'hsa_amd_memory_pool_can_migrate', - 'hsa_amd_memory_pool_flag_s', 'hsa_amd_memory_pool_flag_t', - 'hsa_amd_memory_pool_flag_t__enumvalues', - 'hsa_amd_memory_pool_free', 'hsa_amd_memory_pool_get_info', - 'hsa_amd_memory_pool_global_flag_s', - 'hsa_amd_memory_pool_global_flag_t', - 'hsa_amd_memory_pool_global_flag_t__enumvalues', - 'hsa_amd_memory_pool_info_t', - 'hsa_amd_memory_pool_info_t__enumvalues', - 'hsa_amd_memory_pool_link_info_t', - 'hsa_amd_memory_pool_location_s', - 'hsa_amd_memory_pool_location_t', - 'hsa_amd_memory_pool_location_t__enumvalues', - 'hsa_amd_memory_pool_t', 'hsa_amd_memory_type_t', - 'hsa_amd_memory_type_t__enumvalues', 'hsa_amd_memory_unlock', - 'hsa_amd_packet_type8_t', 'hsa_amd_packet_type_t', - 'hsa_amd_packet_type_t__enumvalues', 'hsa_amd_pointer_info', - 'hsa_amd_pointer_info_set_userdata', 'hsa_amd_pointer_info_t', - 'hsa_amd_pointer_type_t', 'hsa_amd_pointer_type_t__enumvalues', - 'hsa_amd_portable_close_dmabuf', 'hsa_amd_portable_export_dmabuf', - 'hsa_amd_profiling_async_copy_enable', - 'hsa_amd_profiling_async_copy_time_t', - 'hsa_amd_profiling_convert_tick_to_system_domain', - 'hsa_amd_profiling_dispatch_time_t', - 'hsa_amd_profiling_get_async_copy_time', - 'hsa_amd_profiling_get_dispatch_time', - 'hsa_amd_profiling_set_profiler_enabled', - 'hsa_amd_queue_cu_get_mask', 'hsa_amd_queue_cu_set_mask', - 'hsa_amd_queue_get_info', 'hsa_amd_queue_priority_s', - 'hsa_amd_queue_priority_t', - 'hsa_amd_queue_priority_t__enumvalues', - 'hsa_amd_queue_set_priority', 'hsa_amd_region_info_s', - 'hsa_amd_region_info_t', 'hsa_amd_region_info_t__enumvalues', - 'hsa_amd_register_deallocation_callback', - 'hsa_amd_register_system_event_handler', 'hsa_amd_sdma_engine_id', - 'hsa_amd_sdma_engine_id_t', - 'hsa_amd_sdma_engine_id_t__enumvalues', 'hsa_amd_segment_t', - 'hsa_amd_segment_t__enumvalues', 'hsa_amd_signal_async_handler', - 'hsa_amd_signal_attribute_t', - 'hsa_amd_signal_attribute_t__enumvalues', 'hsa_amd_signal_create', - 'hsa_amd_signal_handler', 'hsa_amd_signal_value_pointer', - 'hsa_amd_signal_wait_any', 'hsa_amd_spm_acquire', - 'hsa_amd_spm_release', 'hsa_amd_spm_set_dest_buffer', - 'hsa_amd_svm_attribute_pair_t', 'hsa_amd_svm_attribute_s', - 'hsa_amd_svm_attribute_t', 'hsa_amd_svm_attribute_t__enumvalues', - 'hsa_amd_svm_attributes_get', 'hsa_amd_svm_attributes_set', - 'hsa_amd_svm_model_s', 'hsa_amd_svm_model_t', - 'hsa_amd_svm_model_t__enumvalues', 'hsa_amd_svm_prefetch_async', - 'hsa_amd_system_event_callback_t', - 'hsa_amd_vendor_packet_header_t', 'hsa_amd_vmem_address_free', - 'hsa_amd_vmem_address_reserve', - 'hsa_amd_vmem_address_reserve_align', - 'hsa_amd_vmem_alloc_handle_t', - 'hsa_amd_vmem_export_shareable_handle', 'hsa_amd_vmem_get_access', - 'hsa_amd_vmem_get_alloc_properties_from_handle', - 'hsa_amd_vmem_handle_create', 'hsa_amd_vmem_handle_release', - 'hsa_amd_vmem_import_shareable_handle', 'hsa_amd_vmem_map', - 'hsa_amd_vmem_retain_alloc_handle', 'hsa_amd_vmem_set_access', - 'hsa_amd_vmem_unmap', 'hsa_barrier_and_packet_t', - 'hsa_barrier_or_packet_t', 'hsa_cache_get_info', - 'hsa_cache_info_t', 'hsa_cache_info_t__enumvalues', 'hsa_cache_t', - 'hsa_callback_data_t', 'hsa_code_object_deserialize', - 'hsa_code_object_destroy', 'hsa_code_object_get_info', - 'hsa_code_object_get_symbol', - 'hsa_code_object_get_symbol_from_name', 'hsa_code_object_info_t', - 'hsa_code_object_info_t__enumvalues', - 'hsa_code_object_iterate_symbols', - 'hsa_code_object_reader_create_from_file', - 'hsa_code_object_reader_create_from_memory', - 'hsa_code_object_reader_destroy', 'hsa_code_object_reader_t', - 'hsa_code_object_serialize', 'hsa_code_object_t', - 'hsa_code_object_type_t', 'hsa_code_object_type_t__enumvalues', - 'hsa_code_symbol_get_info', 'hsa_code_symbol_info_t', - 'hsa_code_symbol_info_t__enumvalues', 'hsa_code_symbol_t', - 'hsa_default_float_rounding_mode_t', - 'hsa_default_float_rounding_mode_t__enumvalues', - 'hsa_device_type_t', 'hsa_device_type_t__enumvalues', - 'hsa_dim3_t', 'hsa_endianness_t', 'hsa_endianness_t__enumvalues', - 'hsa_exception_policy_t', 'hsa_exception_policy_t__enumvalues', - 'hsa_executable_agent_global_variable_define', - 'hsa_executable_create', 'hsa_executable_create_alt', - 'hsa_executable_destroy', 'hsa_executable_freeze', - 'hsa_executable_get_info', 'hsa_executable_get_symbol', - 'hsa_executable_get_symbol_by_name', - 'hsa_executable_global_variable_define', 'hsa_executable_info_t', - 'hsa_executable_info_t__enumvalues', - 'hsa_executable_iterate_agent_symbols', - 'hsa_executable_iterate_program_symbols', - 'hsa_executable_iterate_symbols', - 'hsa_executable_load_agent_code_object', - 'hsa_executable_load_code_object', - 'hsa_executable_load_program_code_object', - 'hsa_executable_readonly_variable_define', - 'hsa_executable_state_t', 'hsa_executable_state_t__enumvalues', - 'hsa_executable_symbol_get_info', 'hsa_executable_symbol_info_t', - 'hsa_executable_symbol_info_t__enumvalues', - 'hsa_executable_symbol_t', 'hsa_executable_t', - 'hsa_executable_validate', 'hsa_executable_validate_alt', - 'hsa_ext_amd_aql_pm4_packet_t', 'hsa_ext_control_directives_t', - 'hsa_ext_finalizer_1_00_pfn_t', - 'hsa_ext_finalizer_call_convention_t', - 'hsa_ext_finalizer_call_convention_t__enumvalues', - 'hsa_ext_image_capability_t', - 'hsa_ext_image_capability_t__enumvalues', - 'hsa_ext_image_channel_order32_t', - 'hsa_ext_image_channel_order_t', - 'hsa_ext_image_channel_order_t__enumvalues', - 'hsa_ext_image_channel_type32_t', 'hsa_ext_image_channel_type_t', - 'hsa_ext_image_channel_type_t__enumvalues', 'hsa_ext_image_clear', - 'hsa_ext_image_copy', 'hsa_ext_image_create', - 'hsa_ext_image_create_with_layout', 'hsa_ext_image_data_get_info', - 'hsa_ext_image_data_get_info_with_layout', - 'hsa_ext_image_data_info_t', 'hsa_ext_image_data_layout_t', - 'hsa_ext_image_data_layout_t__enumvalues', - 'hsa_ext_image_descriptor_t', 'hsa_ext_image_destroy', - 'hsa_ext_image_export', 'hsa_ext_image_format_t', - 'hsa_ext_image_geometry_t', - 'hsa_ext_image_geometry_t__enumvalues', - 'hsa_ext_image_get_capability', - 'hsa_ext_image_get_capability_with_layout', - 'hsa_ext_image_import', 'hsa_ext_image_region_t', - 'hsa_ext_image_t', 'hsa_ext_images_1_00_pfn_t', - 'hsa_ext_images_1_pfn_t', 'hsa_ext_module_t', - 'hsa_ext_program_add_module', 'hsa_ext_program_create', - 'hsa_ext_program_destroy', 'hsa_ext_program_finalize', - 'hsa_ext_program_get_info', 'hsa_ext_program_info_t', - 'hsa_ext_program_info_t__enumvalues', - 'hsa_ext_program_iterate_modules', 'hsa_ext_program_t', - 'hsa_ext_sampler_addressing_mode32_t', - 'hsa_ext_sampler_addressing_mode_t', - 'hsa_ext_sampler_addressing_mode_t__enumvalues', - 'hsa_ext_sampler_coordinate_mode32_t', - 'hsa_ext_sampler_coordinate_mode_t', - 'hsa_ext_sampler_coordinate_mode_t__enumvalues', - 'hsa_ext_sampler_create', 'hsa_ext_sampler_descriptor_t', - 'hsa_ext_sampler_destroy', 'hsa_ext_sampler_filter_mode32_t', - 'hsa_ext_sampler_filter_mode_t', - 'hsa_ext_sampler_filter_mode_t__enumvalues', 'hsa_ext_sampler_t', - 'hsa_extension_get_name', 'hsa_extension_t', - 'hsa_extension_t__enumvalues', 'hsa_fence_scope_t', - 'hsa_fence_scope_t__enumvalues', 'hsa_file_t', 'hsa_flag_isset64', - 'hsa_flush_mode_t', 'hsa_flush_mode_t__enumvalues', - 'hsa_fp_type_t', 'hsa_fp_type_t__enumvalues', 'hsa_init', - 'hsa_isa_compatible', 'hsa_isa_from_name', - 'hsa_isa_get_exception_policies', 'hsa_isa_get_info', - 'hsa_isa_get_info_alt', 'hsa_isa_get_round_method', - 'hsa_isa_info_t', 'hsa_isa_info_t__enumvalues', - 'hsa_isa_iterate_wavefronts', 'hsa_isa_t', 'hsa_iterate_agents', - 'hsa_kernel_dispatch_packet_setup_t', - 'hsa_kernel_dispatch_packet_setup_t__enumvalues', - 'hsa_kernel_dispatch_packet_setup_width_t', - 'hsa_kernel_dispatch_packet_setup_width_t__enumvalues', - 'hsa_kernel_dispatch_packet_t', 'hsa_loaded_code_object_t', - 'hsa_machine_model_t', 'hsa_machine_model_t__enumvalues', - 'hsa_memory_allocate', 'hsa_memory_assign_agent', - 'hsa_memory_copy', 'hsa_memory_deregister', 'hsa_memory_free', - 'hsa_memory_register', 'hsa_packet_header_t', - 'hsa_packet_header_t__enumvalues', 'hsa_packet_header_width_t', - 'hsa_packet_header_width_t__enumvalues', 'hsa_packet_type_t', - 'hsa_packet_type_t__enumvalues', 'hsa_pitched_ptr_t', - 'hsa_profile_t', 'hsa_profile_t__enumvalues', - 'hsa_queue_add_write_index_acq_rel', - 'hsa_queue_add_write_index_acquire', - 'hsa_queue_add_write_index_relaxed', - 'hsa_queue_add_write_index_release', - 'hsa_queue_add_write_index_scacq_screl', - 'hsa_queue_add_write_index_scacquire', - 'hsa_queue_add_write_index_screlease', - 'hsa_queue_cas_write_index_acq_rel', - 'hsa_queue_cas_write_index_acquire', - 'hsa_queue_cas_write_index_relaxed', - 'hsa_queue_cas_write_index_release', - 'hsa_queue_cas_write_index_scacq_screl', - 'hsa_queue_cas_write_index_scacquire', - 'hsa_queue_cas_write_index_screlease', 'hsa_queue_create', - 'hsa_queue_destroy', 'hsa_queue_feature_t', - 'hsa_queue_feature_t__enumvalues', 'hsa_queue_inactivate', - 'hsa_queue_info_attribute_t', - 'hsa_queue_info_attribute_t__enumvalues', - 'hsa_queue_load_read_index_acquire', - 'hsa_queue_load_read_index_relaxed', - 'hsa_queue_load_read_index_scacquire', - 'hsa_queue_load_write_index_acquire', - 'hsa_queue_load_write_index_relaxed', - 'hsa_queue_load_write_index_scacquire', - 'hsa_queue_store_read_index_relaxed', - 'hsa_queue_store_read_index_release', - 'hsa_queue_store_read_index_screlease', - 'hsa_queue_store_write_index_relaxed', - 'hsa_queue_store_write_index_release', - 'hsa_queue_store_write_index_screlease', 'hsa_queue_t', - 'hsa_queue_type32_t', 'hsa_queue_type_t', - 'hsa_queue_type_t__enumvalues', 'hsa_region_get_info', - 'hsa_region_global_flag_t', - 'hsa_region_global_flag_t__enumvalues', 'hsa_region_info_t', - 'hsa_region_info_t__enumvalues', 'hsa_region_segment_t', - 'hsa_region_segment_t__enumvalues', 'hsa_region_t', - 'hsa_round_method_t', 'hsa_round_method_t__enumvalues', - 'hsa_shut_down', 'hsa_signal_add_acq_rel', - 'hsa_signal_add_acquire', 'hsa_signal_add_relaxed', - 'hsa_signal_add_release', 'hsa_signal_add_scacq_screl', - 'hsa_signal_add_scacquire', 'hsa_signal_add_screlease', - 'hsa_signal_and_acq_rel', 'hsa_signal_and_acquire', - 'hsa_signal_and_relaxed', 'hsa_signal_and_release', - 'hsa_signal_and_scacq_screl', 'hsa_signal_and_scacquire', - 'hsa_signal_and_screlease', 'hsa_signal_cas_acq_rel', - 'hsa_signal_cas_acquire', 'hsa_signal_cas_relaxed', - 'hsa_signal_cas_release', 'hsa_signal_cas_scacq_screl', - 'hsa_signal_cas_scacquire', 'hsa_signal_cas_screlease', - 'hsa_signal_condition32_t', 'hsa_signal_condition_t', - 'hsa_signal_condition_t__enumvalues', 'hsa_signal_create', - 'hsa_signal_destroy', 'hsa_signal_exchange_acq_rel', - 'hsa_signal_exchange_acquire', 'hsa_signal_exchange_relaxed', - 'hsa_signal_exchange_release', 'hsa_signal_exchange_scacq_screl', - 'hsa_signal_exchange_scacquire', 'hsa_signal_exchange_screlease', - 'hsa_signal_group_create', 'hsa_signal_group_destroy', - 'hsa_signal_group_t', 'hsa_signal_group_wait_any_relaxed', - 'hsa_signal_group_wait_any_scacquire', 'hsa_signal_load_acquire', - 'hsa_signal_load_relaxed', 'hsa_signal_load_scacquire', - 'hsa_signal_or_acq_rel', 'hsa_signal_or_acquire', - 'hsa_signal_or_relaxed', 'hsa_signal_or_release', - 'hsa_signal_or_scacq_screl', 'hsa_signal_or_scacquire', - 'hsa_signal_or_screlease', 'hsa_signal_silent_store_relaxed', - 'hsa_signal_silent_store_screlease', 'hsa_signal_store_relaxed', - 'hsa_signal_store_release', 'hsa_signal_store_screlease', - 'hsa_signal_subtract_acq_rel', 'hsa_signal_subtract_acquire', - 'hsa_signal_subtract_relaxed', 'hsa_signal_subtract_release', - 'hsa_signal_subtract_scacq_screl', - 'hsa_signal_subtract_scacquire', 'hsa_signal_subtract_screlease', - 'hsa_signal_t', 'hsa_signal_value_t', 'hsa_signal_wait_acquire', - 'hsa_signal_wait_relaxed', 'hsa_signal_wait_scacquire', - 'hsa_signal_xor_acq_rel', 'hsa_signal_xor_acquire', - 'hsa_signal_xor_relaxed', 'hsa_signal_xor_release', - 'hsa_signal_xor_scacq_screl', 'hsa_signal_xor_scacquire', - 'hsa_signal_xor_screlease', 'hsa_soft_queue_create', - 'hsa_status_string', 'hsa_status_t', 'hsa_status_t__enumvalues', - 'hsa_symbol_kind_t', 'hsa_symbol_kind_t__enumvalues', - 'hsa_symbol_linkage_t', 'hsa_symbol_linkage_t__enumvalues', - 'hsa_system_extension_supported', - 'hsa_system_get_extension_table', 'hsa_system_get_info', - 'hsa_system_get_major_extension_table', 'hsa_system_info_t', - 'hsa_system_info_t__enumvalues', - 'hsa_system_major_extension_supported', - 'hsa_variable_allocation_t', - 'hsa_variable_allocation_t__enumvalues', 'hsa_variable_segment_t', - 'hsa_variable_segment_t__enumvalues', - 'hsa_ven_amd_aqlprofile_1_00_pfn_t', - 'hsa_ven_amd_aqlprofile_att_marker', - 'hsa_ven_amd_aqlprofile_att_marker_channel_t', - 'hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues', - 'hsa_ven_amd_aqlprofile_block_name_t', - 'hsa_ven_amd_aqlprofile_block_name_t__enumvalues', - 'hsa_ven_amd_aqlprofile_coordinate_callback_t', - 'hsa_ven_amd_aqlprofile_data_callback_t', - 'hsa_ven_amd_aqlprofile_descriptor_t', - 'hsa_ven_amd_aqlprofile_error_string', - 'hsa_ven_amd_aqlprofile_event_t', - 'hsa_ven_amd_aqlprofile_event_type_t', - 'hsa_ven_amd_aqlprofile_event_type_t__enumvalues', - 'hsa_ven_amd_aqlprofile_eventname_callback_t', - 'hsa_ven_amd_aqlprofile_get_info', - 'hsa_ven_amd_aqlprofile_id_query_t', - 'hsa_ven_amd_aqlprofile_info_data_t', - 'hsa_ven_amd_aqlprofile_info_type_t', - 'hsa_ven_amd_aqlprofile_info_type_t__enumvalues', - 'hsa_ven_amd_aqlprofile_iterate_data', - 'hsa_ven_amd_aqlprofile_iterate_event_coord', - 'hsa_ven_amd_aqlprofile_iterate_event_ids', - 'hsa_ven_amd_aqlprofile_legacy_get_pm4', - 'hsa_ven_amd_aqlprofile_parameter_name_t', - 'hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues', - 'hsa_ven_amd_aqlprofile_parameter_t', - 'hsa_ven_amd_aqlprofile_pfn_t', - 'hsa_ven_amd_aqlprofile_profile_t', 'hsa_ven_amd_aqlprofile_read', - 'hsa_ven_amd_aqlprofile_start', 'hsa_ven_amd_aqlprofile_stop', - 'hsa_ven_amd_aqlprofile_validate_event', - 'hsa_ven_amd_aqlprofile_version_major', - 'hsa_ven_amd_aqlprofile_version_minor', 'hsa_wait_state_t', - 'hsa_wait_state_t__enumvalues', 'hsa_wavefront_get_info', - 'hsa_wavefront_info_t', 'hsa_wavefront_info_t__enumvalues', - 'hsa_wavefront_t', 'int32_t', 'kAqlProfileLib', 'size_t', - 'struct_BrigModuleHeader', 'struct_amd_control_directives_s', - 'struct_amd_kernel_code_s', 'struct_amd_queue_s', - 'struct_amd_runtime_loader_debug_info_s', 'struct_amd_signal_s', - 'struct_c__SA_hsa_ext_amd_aql_pm4_packet_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_event_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data', - 'struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_profile_t', - 'struct_hsa_agent_dispatch_packet_s', 'struct_hsa_agent_s', - 'struct_hsa_amd_barrier_value_packet_s', 'struct_hsa_amd_event_s', - 'struct_hsa_amd_gpu_hw_exception_info_s', - 'struct_hsa_amd_gpu_memory_fault_info_s', - 'struct_hsa_amd_hdp_flush_s', 'struct_hsa_amd_image_descriptor_s', - 'struct_hsa_amd_ipc_memory_s', - 'struct_hsa_amd_memory_access_desc_s', - 'struct_hsa_amd_memory_pool_link_info_s', - 'struct_hsa_amd_memory_pool_s', 'struct_hsa_amd_packet_header_s', - 'struct_hsa_amd_pointer_info_s', - 'struct_hsa_amd_profiling_async_copy_time_s', - 'struct_hsa_amd_profiling_dispatch_time_s', - 'struct_hsa_amd_svm_attribute_pair_s', - 'struct_hsa_amd_vmem_alloc_handle_s', - 'struct_hsa_barrier_and_packet_s', - 'struct_hsa_barrier_or_packet_s', 'struct_hsa_cache_s', - 'struct_hsa_callback_data_s', 'struct_hsa_code_object_reader_s', - 'struct_hsa_code_object_s', 'struct_hsa_code_symbol_s', - 'struct_hsa_dim3_s', 'struct_hsa_executable_s', - 'struct_hsa_executable_symbol_s', - 'struct_hsa_ext_control_directives_s', - 'struct_hsa_ext_finalizer_1_00_pfn_s', - 'struct_hsa_ext_image_data_info_s', - 'struct_hsa_ext_image_descriptor_s', - 'struct_hsa_ext_image_format_s', 'struct_hsa_ext_image_region_s', - 'struct_hsa_ext_image_s', 'struct_hsa_ext_images_1_00_pfn_s', - 'struct_hsa_ext_images_1_pfn_s', 'struct_hsa_ext_program_s', - 'struct_hsa_ext_sampler_descriptor_s', 'struct_hsa_ext_sampler_s', - 'struct_hsa_isa_s', 'struct_hsa_kernel_dispatch_packet_s', - 'struct_hsa_loaded_code_object_s', 'struct_hsa_pitched_ptr_s', - 'struct_hsa_queue_s', 'struct_hsa_region_s', - 'struct_hsa_signal_group_s', 'struct_hsa_signal_s', - 'struct_hsa_ven_amd_aqlprofile_1_00_pfn_s', - 'struct_hsa_wavefront_s', 'uint16_t', 'uint32_t', 'uint64_t', - 'union_amd_signal_s_0', 'union_amd_signal_s_1', - 'union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0', - 'union_hsa_amd_event_s_0'] diff --git a/tinygrad/tinygrad/runtime/autogen/io_uring.py b/tinygrad/tinygrad/runtime/autogen/io_uring.py deleted file mode 100644 index 420d7503..00000000 --- a/tinygrad/tinygrad/runtime/autogen/io_uring.py +++ /dev/null @@ -1,2319 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -LIB_URING_H = True # macro -_XOPEN_SOURCE = 500 # macro -_GNU_SOURCE = True # macro -# def uring_unlikely(cond): # macro -# return __builtin_expect(!!(cond),0) -# def uring_likely(cond): # macro -# return __builtin_expect(!!(cond),1) -IOURINGINLINE = True # macro -__NR_io_uring_setup = 425 # macro -__NR_io_uring_enter = 426 # macro -__NR_io_uring_register = 427 # macro -def io_uring_cqe_index(ring, ptr, mask): # macro - return (((ptr)&(mask))<cq.khead;(cqe=(head!=io_uring_smp_load_acquire((ring)->cq.ktail)?&(ring)->cq.cqes[io_uring_cqe_index(ring,head,(ring)->cq.ring_mask)]:NULL));head++) -LIBURING_HAVE_DATA64 = True # macro -def UNUSED(x): # macro - return (void)(x) -# def IO_URING_CHECK_VERSION(major, minor): # macro -# return (major>IO_URING_VERSION_MAJOR or (major==IO_URING_VERSION_MAJOR and minor>=IO_URING_VERSION_MINOR)) -class struct_io_uring_sq(Structure): - pass - -class struct_io_uring_sqe(Structure): - pass - -struct_io_uring_sq._pack_ = 1 # source:False -struct_io_uring_sq._fields_ = [ - ('khead', ctypes.POINTER(ctypes.c_uint32)), - ('ktail', ctypes.POINTER(ctypes.c_uint32)), - ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), - ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), - ('kflags', ctypes.POINTER(ctypes.c_uint32)), - ('kdropped', ctypes.POINTER(ctypes.c_uint32)), - ('array', ctypes.POINTER(ctypes.c_uint32)), - ('sqes', ctypes.POINTER(struct_io_uring_sqe)), - ('sqe_head', ctypes.c_uint32), - ('sqe_tail', ctypes.c_uint32), - ('ring_sz', ctypes.c_uint64), - ('ring_ptr', ctypes.POINTER(None)), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('pad', ctypes.c_uint32 * 2), -] - -class union_io_uring_sqe_0(Union): - pass - -class struct_io_uring_sqe_0_0(Structure): - pass - -struct_io_uring_sqe_0_0._pack_ = 1 # source:False -struct_io_uring_sqe_0_0._fields_ = [ - ('cmd_op', ctypes.c_uint32), - ('__pad1', ctypes.c_uint32), -] - -union_io_uring_sqe_0._pack_ = 1 # source:False -union_io_uring_sqe_0._anonymous_ = ('_0',) -union_io_uring_sqe_0._fields_ = [ - ('off', ctypes.c_uint64), - ('addr2', ctypes.c_uint64), - ('_0', struct_io_uring_sqe_0_0), -] - -class union_io_uring_sqe_1(Union): - pass - -union_io_uring_sqe_1._pack_ = 1 # source:False -union_io_uring_sqe_1._fields_ = [ - ('addr', ctypes.c_uint64), - ('splice_off_in', ctypes.c_uint64), -] - -class union_io_uring_sqe_2(Union): - pass - -union_io_uring_sqe_2._pack_ = 1 # source:False -union_io_uring_sqe_2._fields_ = [ - ('rw_flags', ctypes.c_int32), - ('fsync_flags', ctypes.c_uint32), - ('poll_events', ctypes.c_uint16), - ('poll32_events', ctypes.c_uint32), - ('sync_range_flags', ctypes.c_uint32), - ('msg_flags', ctypes.c_uint32), - ('timeout_flags', ctypes.c_uint32), - ('accept_flags', ctypes.c_uint32), - ('cancel_flags', ctypes.c_uint32), - ('open_flags', ctypes.c_uint32), - ('statx_flags', ctypes.c_uint32), - ('fadvise_advice', ctypes.c_uint32), - ('splice_flags', ctypes.c_uint32), - ('rename_flags', ctypes.c_uint32), - ('unlink_flags', ctypes.c_uint32), - ('hardlink_flags', ctypes.c_uint32), - ('xattr_flags', ctypes.c_uint32), - ('msg_ring_flags', ctypes.c_uint32), - ('uring_cmd_flags', ctypes.c_uint32), -] - -class union_io_uring_sqe_3(Union): - pass - -union_io_uring_sqe_3._pack_ = 1 # source:True -union_io_uring_sqe_3._fields_ = [ - ('buf_index', ctypes.c_uint16), - ('buf_group', ctypes.c_uint16), -] - -class union_io_uring_sqe_4(Union): - pass - -class struct_io_uring_sqe_4_0(Structure): - pass - -struct_io_uring_sqe_4_0._pack_ = 1 # source:False -struct_io_uring_sqe_4_0._fields_ = [ - ('addr_len', ctypes.c_uint16), - ('__pad3', ctypes.c_uint16 * 1), -] - -union_io_uring_sqe_4._pack_ = 1 # source:False -union_io_uring_sqe_4._anonymous_ = ('_0',) -union_io_uring_sqe_4._fields_ = [ - ('splice_fd_in', ctypes.c_int32), - ('file_index', ctypes.c_uint32), - ('_0', struct_io_uring_sqe_4_0), -] - -class union_io_uring_sqe_5(Union): - pass - -class struct_io_uring_sqe_5_0(Structure): - pass - -struct_io_uring_sqe_5_0._pack_ = 1 # source:False -struct_io_uring_sqe_5_0._fields_ = [ - ('addr3', ctypes.c_uint64), - ('__pad2', ctypes.c_uint64 * 1), -] - -union_io_uring_sqe_5._pack_ = 1 # source:False -union_io_uring_sqe_5._anonymous_ = ('_0',) -union_io_uring_sqe_5._fields_ = [ - ('_0', struct_io_uring_sqe_5_0), - ('cmd', ctypes.c_ubyte * 0), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_io_uring_sqe._pack_ = 1 # source:False -struct_io_uring_sqe._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5',) -struct_io_uring_sqe._fields_ = [ - ('opcode', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('ioprio', ctypes.c_uint16), - ('fd', ctypes.c_int32), - ('_0', union_io_uring_sqe_0), - ('_1', union_io_uring_sqe_1), - ('len', ctypes.c_uint32), - ('_2', union_io_uring_sqe_2), - ('user_data', ctypes.c_uint64), - ('_3', union_io_uring_sqe_3), - ('personality', ctypes.c_uint16), - ('_4', union_io_uring_sqe_4), - ('_5', union_io_uring_sqe_5), -] - -class struct_io_uring_cq(Structure): - pass - -class struct_io_uring_cqe(Structure): - pass - -struct_io_uring_cq._pack_ = 1 # source:False -struct_io_uring_cq._fields_ = [ - ('khead', ctypes.POINTER(ctypes.c_uint32)), - ('ktail', ctypes.POINTER(ctypes.c_uint32)), - ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), - ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), - ('kflags', ctypes.POINTER(ctypes.c_uint32)), - ('koverflow', ctypes.POINTER(ctypes.c_uint32)), - ('cqes', ctypes.POINTER(struct_io_uring_cqe)), - ('ring_sz', ctypes.c_uint64), - ('ring_ptr', ctypes.POINTER(None)), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('pad', ctypes.c_uint32 * 2), -] - -struct_io_uring_cqe._pack_ = 1 # source:False -struct_io_uring_cqe._fields_ = [ - ('user_data', ctypes.c_uint64), - ('res', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('big_cqe', ctypes.c_uint64 * 0), -] - -class struct_io_uring(Structure): - pass - -struct_io_uring._pack_ = 1 # source:False -struct_io_uring._fields_ = [ - ('sq', struct_io_uring_sq), - ('cq', struct_io_uring_cq), - ('flags', ctypes.c_uint32), - ('ring_fd', ctypes.c_int32), - ('features', ctypes.c_uint32), - ('enter_ring_fd', ctypes.c_int32), - ('int_flags', ctypes.c_ubyte), - ('pad', ctypes.c_ubyte * 3), - ('pad2', ctypes.c_uint32), -] - -class struct_io_uring_probe(Structure): - pass - -class struct_io_uring_probe_op(Structure): - pass - -struct_io_uring_probe_op._pack_ = 1 # source:False -struct_io_uring_probe_op._fields_ = [ - ('op', ctypes.c_ubyte), - ('resv', ctypes.c_ubyte), - ('flags', ctypes.c_uint16), - ('resv2', ctypes.c_uint32), -] - -struct_io_uring_probe._pack_ = 1 # source:False -struct_io_uring_probe._fields_ = [ - ('last_op', ctypes.c_ubyte), - ('ops_len', ctypes.c_ubyte), - ('resv', ctypes.c_uint16), - ('resv2', ctypes.c_uint32 * 3), - ('ops', struct_io_uring_probe_op * 0), -] - -try: - io_uring_get_probe_ring = _libraries['FIXME_STUB'].io_uring_get_probe_ring - io_uring_get_probe_ring.restype = ctypes.POINTER(struct_io_uring_probe) - io_uring_get_probe_ring.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_get_probe = _libraries['FIXME_STUB'].io_uring_get_probe - io_uring_get_probe.restype = ctypes.POINTER(struct_io_uring_probe) - io_uring_get_probe.argtypes = [] -except AttributeError: - pass -try: - io_uring_free_probe = _libraries['FIXME_STUB'].io_uring_free_probe - io_uring_free_probe.restype = None - io_uring_free_probe.argtypes = [ctypes.POINTER(struct_io_uring_probe)] -except AttributeError: - pass -try: - io_uring_opcode_supported = _libraries['FIXME_STUB'].io_uring_opcode_supported - io_uring_opcode_supported.restype = ctypes.c_int32 - io_uring_opcode_supported.argtypes = [ctypes.POINTER(struct_io_uring_probe), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_params(Structure): - pass - -class struct_io_sqring_offsets(Structure): - pass - -struct_io_sqring_offsets._pack_ = 1 # source:False -struct_io_sqring_offsets._fields_ = [ - ('head', ctypes.c_uint32), - ('tail', ctypes.c_uint32), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dropped', ctypes.c_uint32), - ('array', ctypes.c_uint32), - ('resv1', ctypes.c_uint32), - ('user_addr', ctypes.c_uint64), -] - -class struct_io_cqring_offsets(Structure): - pass - -struct_io_cqring_offsets._pack_ = 1 # source:False -struct_io_cqring_offsets._fields_ = [ - ('head', ctypes.c_uint32), - ('tail', ctypes.c_uint32), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('overflow', ctypes.c_uint32), - ('cqes', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('resv1', ctypes.c_uint32), - ('user_addr', ctypes.c_uint64), -] - -struct_io_uring_params._pack_ = 1 # source:False -struct_io_uring_params._fields_ = [ - ('sq_entries', ctypes.c_uint32), - ('cq_entries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('sq_thread_cpu', ctypes.c_uint32), - ('sq_thread_idle', ctypes.c_uint32), - ('features', ctypes.c_uint32), - ('wq_fd', ctypes.c_uint32), - ('resv', ctypes.c_uint32 * 3), - ('sq_off', struct_io_sqring_offsets), - ('cq_off', struct_io_cqring_offsets), -] - -size_t = ctypes.c_uint64 -try: - io_uring_queue_init_mem = _libraries['FIXME_STUB'].io_uring_queue_init_mem - io_uring_queue_init_mem.restype = ctypes.c_int32 - io_uring_queue_init_mem.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_params), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - io_uring_queue_init_params = _libraries['FIXME_STUB'].io_uring_queue_init_params - io_uring_queue_init_params.restype = ctypes.c_int32 - io_uring_queue_init_params.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_queue_init = _libraries['FIXME_STUB'].io_uring_queue_init - io_uring_queue_init.restype = ctypes.c_int32 - io_uring_queue_init.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_queue_mmap = _libraries['FIXME_STUB'].io_uring_queue_mmap - io_uring_queue_mmap.restype = ctypes.c_int32 - io_uring_queue_mmap.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_io_uring_params), ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_ring_dontfork = _libraries['FIXME_STUB'].io_uring_ring_dontfork - io_uring_ring_dontfork.restype = ctypes.c_int32 - io_uring_ring_dontfork.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_queue_exit = _libraries['FIXME_STUB'].io_uring_queue_exit - io_uring_queue_exit.restype = None - io_uring_queue_exit.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_peek_batch_cqe = _libraries['FIXME_STUB'].io_uring_peek_batch_cqe - io_uring_peek_batch_cqe.restype = ctypes.c_uint32 - io_uring_peek_batch_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32] -except AttributeError: - pass -class struct___kernel_timespec(Structure): - pass - -struct___kernel_timespec._pack_ = 1 # source:False -struct___kernel_timespec._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_nsec', ctypes.c_int64), -] - -class struct_c__SA___sigset_t(Structure): - pass - -struct_c__SA___sigset_t._pack_ = 1 # source:False -struct_c__SA___sigset_t._fields_ = [ - ('__val', ctypes.c_uint64 * 16), -] - -try: - io_uring_wait_cqes = _libraries['FIXME_STUB'].io_uring_wait_cqes - io_uring_wait_cqes.restype = ctypes.c_int32 - io_uring_wait_cqes.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.POINTER(struct___kernel_timespec), ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_wait_cqe_timeout = _libraries['FIXME_STUB'].io_uring_wait_cqe_timeout - io_uring_wait_cqe_timeout.restype = ctypes.c_int32 - io_uring_wait_cqe_timeout.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.POINTER(struct___kernel_timespec)] -except AttributeError: - pass -try: - io_uring_submit = _libraries['FIXME_STUB'].io_uring_submit - io_uring_submit.restype = ctypes.c_int32 - io_uring_submit.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_submit_and_wait = _libraries['FIXME_STUB'].io_uring_submit_and_wait - io_uring_submit_and_wait.restype = ctypes.c_int32 - io_uring_submit_and_wait.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_submit_and_wait_timeout = _libraries['FIXME_STUB'].io_uring_submit_and_wait_timeout - io_uring_submit_and_wait_timeout.restype = ctypes.c_int32 - io_uring_submit_and_wait_timeout.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.POINTER(struct___kernel_timespec), ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -class struct_iovec(Structure): - pass - -struct_iovec._pack_ = 1 # source:False -struct_iovec._fields_ = [ - ('iov_base', ctypes.POINTER(None)), - ('iov_len', ctypes.c_uint64), -] - -try: - io_uring_register_buffers = _libraries['FIXME_STUB'].io_uring_register_buffers - io_uring_register_buffers.restype = ctypes.c_int32 - io_uring_register_buffers.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_iovec), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_tags = _libraries['FIXME_STUB'].io_uring_register_buffers_tags - io_uring_register_buffers_tags.restype = ctypes.c_int32 - io_uring_register_buffers_tags.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_iovec), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_sparse = _libraries['FIXME_STUB'].io_uring_register_buffers_sparse - io_uring_register_buffers_sparse.restype = ctypes.c_int32 - io_uring_register_buffers_sparse.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_update_tag = _libraries['FIXME_STUB'].io_uring_register_buffers_update_tag - io_uring_register_buffers_update_tag.restype = ctypes.c_int32 - io_uring_register_buffers_update_tag.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(struct_iovec), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_buffers = _libraries['FIXME_STUB'].io_uring_unregister_buffers - io_uring_unregister_buffers.restype = ctypes.c_int32 - io_uring_unregister_buffers.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_files = _libraries['FIXME_STUB'].io_uring_register_files - io_uring_register_files.restype = ctypes.c_int32 - io_uring_register_files.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_tags = _libraries['FIXME_STUB'].io_uring_register_files_tags - io_uring_register_files_tags.restype = ctypes.c_int32 - io_uring_register_files_tags.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_sparse = _libraries['FIXME_STUB'].io_uring_register_files_sparse - io_uring_register_files_sparse.restype = ctypes.c_int32 - io_uring_register_files_sparse.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_update_tag = _libraries['FIXME_STUB'].io_uring_register_files_update_tag - io_uring_register_files_update_tag.restype = ctypes.c_int32 - io_uring_register_files_update_tag.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_files = _libraries['FIXME_STUB'].io_uring_unregister_files - io_uring_unregister_files.restype = ctypes.c_int32 - io_uring_unregister_files.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_files_update = _libraries['FIXME_STUB'].io_uring_register_files_update - io_uring_register_files_update.restype = ctypes.c_int32 - io_uring_register_files_update.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_eventfd = _libraries['FIXME_STUB'].io_uring_register_eventfd - io_uring_register_eventfd.restype = ctypes.c_int32 - io_uring_register_eventfd.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_register_eventfd_async = _libraries['FIXME_STUB'].io_uring_register_eventfd_async - io_uring_register_eventfd_async.restype = ctypes.c_int32 - io_uring_register_eventfd_async.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_unregister_eventfd = _libraries['FIXME_STUB'].io_uring_unregister_eventfd - io_uring_unregister_eventfd.restype = ctypes.c_int32 - io_uring_unregister_eventfd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_probe = _libraries['FIXME_STUB'].io_uring_register_probe - io_uring_register_probe.restype = ctypes.c_int32 - io_uring_register_probe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_probe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_personality = _libraries['FIXME_STUB'].io_uring_register_personality - io_uring_register_personality.restype = ctypes.c_int32 - io_uring_register_personality.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_unregister_personality = _libraries['FIXME_STUB'].io_uring_unregister_personality - io_uring_unregister_personality.restype = ctypes.c_int32 - io_uring_unregister_personality.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_restriction(Structure): - pass - -class union_io_uring_restriction_0(Union): - pass - -union_io_uring_restriction_0._pack_ = 1 # source:False -union_io_uring_restriction_0._fields_ = [ - ('register_op', ctypes.c_ubyte), - ('sqe_op', ctypes.c_ubyte), - ('sqe_flags', ctypes.c_ubyte), -] - -struct_io_uring_restriction._pack_ = 1 # source:False -struct_io_uring_restriction._anonymous_ = ('_0',) -struct_io_uring_restriction._fields_ = [ - ('opcode', ctypes.c_uint16), - ('_0', union_io_uring_restriction_0), - ('resv', ctypes.c_ubyte), - ('resv2', ctypes.c_uint32 * 3), -] - -try: - io_uring_register_restrictions = _libraries['FIXME_STUB'].io_uring_register_restrictions - io_uring_register_restrictions.restype = ctypes.c_int32 - io_uring_register_restrictions.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_restriction), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_enable_rings = _libraries['FIXME_STUB'].io_uring_enable_rings - io_uring_enable_rings.restype = ctypes.c_int32 - io_uring_enable_rings.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - __io_uring_sqring_wait = _libraries['FIXME_STUB'].__io_uring_sqring_wait - __io_uring_sqring_wait.restype = ctypes.c_int32 - __io_uring_sqring_wait.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -class struct_c__SA_cpu_set_t(Structure): - pass - -struct_c__SA_cpu_set_t._pack_ = 1 # source:False -struct_c__SA_cpu_set_t._fields_ = [ - ('__bits', ctypes.c_uint64 * 16), -] - -try: - io_uring_register_iowq_aff = _libraries['FIXME_STUB'].io_uring_register_iowq_aff - io_uring_register_iowq_aff.restype = ctypes.c_int32 - io_uring_register_iowq_aff.argtypes = [ctypes.POINTER(struct_io_uring), size_t, ctypes.POINTER(struct_c__SA_cpu_set_t)] -except AttributeError: - pass -try: - io_uring_unregister_iowq_aff = _libraries['FIXME_STUB'].io_uring_unregister_iowq_aff - io_uring_unregister_iowq_aff.restype = ctypes.c_int32 - io_uring_unregister_iowq_aff.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_iowq_max_workers = _libraries['FIXME_STUB'].io_uring_register_iowq_max_workers - io_uring_register_iowq_max_workers.restype = ctypes.c_int32 - io_uring_register_iowq_max_workers.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - io_uring_register_ring_fd = _libraries['FIXME_STUB'].io_uring_register_ring_fd - io_uring_register_ring_fd.restype = ctypes.c_int32 - io_uring_register_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_unregister_ring_fd = _libraries['FIXME_STUB'].io_uring_unregister_ring_fd - io_uring_unregister_ring_fd.restype = ctypes.c_int32 - io_uring_unregister_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_close_ring_fd = _libraries['FIXME_STUB'].io_uring_close_ring_fd - io_uring_close_ring_fd.restype = ctypes.c_int32 - io_uring_close_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -class struct_io_uring_buf_reg(Structure): - pass - -struct_io_uring_buf_reg._pack_ = 1 # source:False -struct_io_uring_buf_reg._fields_ = [ - ('ring_addr', ctypes.c_uint64), - ('ring_entries', ctypes.c_uint32), - ('bgid', ctypes.c_uint16), - ('flags', ctypes.c_uint16), - ('resv', ctypes.c_uint64 * 3), -] - -try: - io_uring_register_buf_ring = _libraries['FIXME_STUB'].io_uring_register_buf_ring - io_uring_register_buf_ring.restype = ctypes.c_int32 - io_uring_register_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_reg), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_buf_ring = _libraries['FIXME_STUB'].io_uring_unregister_buf_ring - io_uring_unregister_buf_ring.restype = ctypes.c_int32 - io_uring_unregister_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_sync_cancel_reg(Structure): - pass - -struct_io_uring_sync_cancel_reg._pack_ = 1 # source:False -struct_io_uring_sync_cancel_reg._fields_ = [ - ('addr', ctypes.c_uint64), - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('timeout', struct___kernel_timespec), - ('pad', ctypes.c_uint64 * 4), -] - -try: - io_uring_register_sync_cancel = _libraries['FIXME_STUB'].io_uring_register_sync_cancel - io_uring_register_sync_cancel.restype = ctypes.c_int32 - io_uring_register_sync_cancel.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_sync_cancel_reg)] -except AttributeError: - pass -try: - io_uring_register_file_alloc_range = _libraries['FIXME_STUB'].io_uring_register_file_alloc_range - io_uring_register_file_alloc_range.restype = ctypes.c_int32 - io_uring_register_file_alloc_range.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_get_events = _libraries['FIXME_STUB'].io_uring_get_events - io_uring_get_events.restype = ctypes.c_int32 - io_uring_get_events.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_submit_and_get_events = _libraries['FIXME_STUB'].io_uring_submit_and_get_events - io_uring_submit_and_get_events.restype = ctypes.c_int32 - io_uring_submit_and_get_events.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_enter = _libraries['FIXME_STUB'].io_uring_enter - io_uring_enter.restype = ctypes.c_int32 - io_uring_enter.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_enter2 = _libraries['FIXME_STUB'].io_uring_enter2 - io_uring_enter2.restype = ctypes.c_int32 - io_uring_enter2.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t), size_t] -except AttributeError: - pass -try: - io_uring_setup = _libraries['FIXME_STUB'].io_uring_setup - io_uring_setup.restype = ctypes.c_int32 - io_uring_setup.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_register = _libraries['FIXME_STUB'].io_uring_register - io_uring_register.restype = ctypes.c_int32 - io_uring_register.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -class struct_io_uring_buf_ring(Structure): - pass - -class union_io_uring_buf_ring_0(Union): - pass - -class struct_io_uring_buf_ring_0_0(Structure): - pass - -struct_io_uring_buf_ring_0_0._pack_ = 1 # source:False -struct_io_uring_buf_ring_0_0._fields_ = [ - ('resv1', ctypes.c_uint64), - ('resv2', ctypes.c_uint32), - ('resv3', ctypes.c_uint16), - ('tail', ctypes.c_uint16), -] - -class struct_io_uring_buf(Structure): - pass - -struct_io_uring_buf._pack_ = 1 # source:False -struct_io_uring_buf._fields_ = [ - ('addr', ctypes.c_uint64), - ('len', ctypes.c_uint32), - ('bid', ctypes.c_uint16), - ('resv', ctypes.c_uint16), -] - -union_io_uring_buf_ring_0._pack_ = 1 # source:False -union_io_uring_buf_ring_0._anonymous_ = ('_0',) -union_io_uring_buf_ring_0._fields_ = [ - ('_0', struct_io_uring_buf_ring_0_0), - ('bufs', struct_io_uring_buf * 0), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_io_uring_buf_ring._pack_ = 1 # source:False -struct_io_uring_buf_ring._anonymous_ = ('_0',) -struct_io_uring_buf_ring._fields_ = [ - ('_0', union_io_uring_buf_ring_0), -] - -try: - io_uring_setup_buf_ring = _libraries['FIXME_STUB'].io_uring_setup_buf_ring - io_uring_setup_buf_ring.restype = ctypes.POINTER(struct_io_uring_buf_ring) - io_uring_setup_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.c_int32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - io_uring_free_buf_ring = _libraries['FIXME_STUB'].io_uring_free_buf_ring - io_uring_free_buf_ring.restype = ctypes.c_int32 - io_uring_free_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - __io_uring_get_cqe = _libraries['FIXME_STUB'].__io_uring_get_cqe - __io_uring_get_cqe.restype = ctypes.c_int32 - __io_uring_get_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_cq_advance = _libraries['FIXME_STUB'].io_uring_cq_advance - io_uring_cq_advance.restype = None - io_uring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_cqe_seen = _libraries['FIXME_STUB'].io_uring_cqe_seen - io_uring_cqe_seen.restype = None - io_uring_cqe_seen.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -try: - io_uring_sqe_set_data = _libraries['FIXME_STUB'].io_uring_sqe_set_data - io_uring_sqe_set_data.restype = None - io_uring_sqe_set_data.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None)] -except AttributeError: - pass -try: - io_uring_cqe_get_data = _libraries['FIXME_STUB'].io_uring_cqe_get_data - io_uring_cqe_get_data.restype = ctypes.POINTER(None) - io_uring_cqe_get_data.argtypes = [ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -__u64 = ctypes.c_uint64 -# LIBURING_UDATA_TIMEOUT = ((__u64)-1) # macro -try: - io_uring_sqe_set_data64 = _libraries['FIXME_STUB'].io_uring_sqe_set_data64 - io_uring_sqe_set_data64.restype = None - io_uring_sqe_set_data64.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64] -except AttributeError: - pass -try: - io_uring_cqe_get_data64 = _libraries['FIXME_STUB'].io_uring_cqe_get_data64 - io_uring_cqe_get_data64.restype = __u64 - io_uring_cqe_get_data64.argtypes = [ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -try: - io_uring_sqe_set_flags = _libraries['FIXME_STUB'].io_uring_sqe_set_flags - io_uring_sqe_set_flags.restype = None - io_uring_sqe_set_flags.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_set_target_fixed_file = _libraries['FIXME_STUB'].__io_uring_set_target_fixed_file - __io_uring_set_target_fixed_file.restype = None - __io_uring_set_target_fixed_file.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_rw = _libraries['FIXME_STUB'].io_uring_prep_rw - io_uring_prep_rw.restype = None - io_uring_prep_rw.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -int64_t = ctypes.c_int64 -try: - io_uring_prep_splice = _libraries['FIXME_STUB'].io_uring_prep_splice - io_uring_prep_splice.restype = None - io_uring_prep_splice.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, int64_t, ctypes.c_int32, int64_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_tee = _libraries['FIXME_STUB'].io_uring_prep_tee - io_uring_prep_tee.restype = None - io_uring_prep_tee.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_readv = _libraries['FIXME_STUB'].io_uring_prep_readv - io_uring_prep_readv.restype = None - io_uring_prep_readv.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_readv2 = _libraries['FIXME_STUB'].io_uring_prep_readv2 - io_uring_prep_readv2.restype = None - io_uring_prep_readv2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_read_fixed = _libraries['FIXME_STUB'].io_uring_prep_read_fixed - io_uring_prep_read_fixed.restype = None - io_uring_prep_read_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_writev = _libraries['FIXME_STUB'].io_uring_prep_writev - io_uring_prep_writev.restype = None - io_uring_prep_writev.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_writev2 = _libraries['FIXME_STUB'].io_uring_prep_writev2 - io_uring_prep_writev2.restype = None - io_uring_prep_writev2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_write_fixed = _libraries['FIXME_STUB'].io_uring_prep_write_fixed - io_uring_prep_write_fixed.restype = None - io_uring_prep_write_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -class struct_msghdr(Structure): - pass - -struct_msghdr._pack_ = 1 # source:False -struct_msghdr._fields_ = [ - ('msg_name', ctypes.POINTER(None)), - ('msg_namelen', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('msg_iov', ctypes.POINTER(struct_iovec)), - ('msg_iovlen', ctypes.c_uint64), - ('msg_control', ctypes.POINTER(None)), - ('msg_controllen', ctypes.c_uint64), - ('msg_flags', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -try: - io_uring_prep_recvmsg = _libraries['FIXME_STUB'].io_uring_prep_recvmsg - io_uring_prep_recvmsg.restype = None - io_uring_prep_recvmsg.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_recvmsg_multishot = _libraries['FIXME_STUB'].io_uring_prep_recvmsg_multishot - io_uring_prep_recvmsg_multishot.restype = None - io_uring_prep_recvmsg_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_sendmsg = _libraries['FIXME_STUB'].io_uring_prep_sendmsg - io_uring_prep_sendmsg.restype = None - io_uring_prep_sendmsg.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_prep_poll_mask = _libraries['FIXME_STUB'].__io_uring_prep_poll_mask - __io_uring_prep_poll_mask.restype = ctypes.c_uint32 - __io_uring_prep_poll_mask.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_add = _libraries['FIXME_STUB'].io_uring_prep_poll_add - io_uring_prep_poll_add.restype = None - io_uring_prep_poll_add.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_multishot = _libraries['FIXME_STUB'].io_uring_prep_poll_multishot - io_uring_prep_poll_multishot.restype = None - io_uring_prep_poll_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_remove = _libraries['FIXME_STUB'].io_uring_prep_poll_remove - io_uring_prep_poll_remove.restype = None - io_uring_prep_poll_remove.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64] -except AttributeError: - pass -try: - io_uring_prep_poll_update = _libraries['FIXME_STUB'].io_uring_prep_poll_update - io_uring_prep_poll_update.restype = None - io_uring_prep_poll_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, __u64, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fsync = _libraries['FIXME_STUB'].io_uring_prep_fsync - io_uring_prep_fsync.restype = None - io_uring_prep_fsync.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_nop = _libraries['FIXME_STUB'].io_uring_prep_nop - io_uring_prep_nop.restype = None - io_uring_prep_nop.argtypes = [ctypes.POINTER(struct_io_uring_sqe)] -except AttributeError: - pass -try: - io_uring_prep_timeout = _libraries['FIXME_STUB'].io_uring_prep_timeout - io_uring_prep_timeout.restype = None - io_uring_prep_timeout.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_timeout_remove = _libraries['FIXME_STUB'].io_uring_prep_timeout_remove - io_uring_prep_timeout_remove.restype = None - io_uring_prep_timeout_remove.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_timeout_update = _libraries['FIXME_STUB'].io_uring_prep_timeout_update - io_uring_prep_timeout_update.restype = None - io_uring_prep_timeout_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), __u64, ctypes.c_uint32] -except AttributeError: - pass -class struct_sockaddr(Structure): - pass - -struct_sockaddr._pack_ = 1 # source:False -struct_sockaddr._fields_ = [ - ('sa_family', ctypes.c_uint16), - ('sa_data', ctypes.c_char * 14), -] - -try: - io_uring_prep_accept = _libraries['FIXME_STUB'].io_uring_prep_accept - io_uring_prep_accept.restype = None - io_uring_prep_accept.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_accept_direct = _libraries['FIXME_STUB'].io_uring_prep_accept_direct - io_uring_prep_accept_direct.restype = None - io_uring_prep_accept_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_multishot_accept = _libraries['FIXME_STUB'].io_uring_prep_multishot_accept - io_uring_prep_multishot_accept.restype = None - io_uring_prep_multishot_accept.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_multishot_accept_direct = _libraries['FIXME_STUB'].io_uring_prep_multishot_accept_direct - io_uring_prep_multishot_accept_direct.restype = None - io_uring_prep_multishot_accept_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel64 = _libraries['FIXME_STUB'].io_uring_prep_cancel64 - io_uring_prep_cancel64.restype = None - io_uring_prep_cancel64.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel = _libraries['FIXME_STUB'].io_uring_prep_cancel - io_uring_prep_cancel.restype = None - io_uring_prep_cancel.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel_fd = _libraries['FIXME_STUB'].io_uring_prep_cancel_fd - io_uring_prep_cancel_fd.restype = None - io_uring_prep_cancel_fd.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_link_timeout = _libraries['FIXME_STUB'].io_uring_prep_link_timeout - io_uring_prep_link_timeout.restype = None - io_uring_prep_link_timeout.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), ctypes.c_uint32] -except AttributeError: - pass -socklen_t = ctypes.c_uint32 -try: - io_uring_prep_connect = _libraries['FIXME_STUB'].io_uring_prep_connect - io_uring_prep_connect.restype = None - io_uring_prep_connect.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), socklen_t] -except AttributeError: - pass -try: - io_uring_prep_files_update = _libraries['FIXME_STUB'].io_uring_prep_files_update - io_uring_prep_files_update.restype = None - io_uring_prep_files_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_fallocate = _libraries['FIXME_STUB'].io_uring_prep_fallocate - io_uring_prep_fallocate.restype = None - io_uring_prep_fallocate.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, __u64, __u64] -except AttributeError: - pass -mode_t = ctypes.c_uint32 -try: - io_uring_prep_openat = _libraries['FIXME_STUB'].io_uring_prep_openat - io_uring_prep_openat.restype = None - io_uring_prep_openat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, mode_t] -except AttributeError: - pass -try: - io_uring_prep_openat_direct = _libraries['FIXME_STUB'].io_uring_prep_openat_direct - io_uring_prep_openat_direct.restype = None - io_uring_prep_openat_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, mode_t, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_close = _libraries['FIXME_STUB'].io_uring_prep_close - io_uring_prep_close.restype = None - io_uring_prep_close.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_close_direct = _libraries['FIXME_STUB'].io_uring_prep_close_direct - io_uring_prep_close_direct.restype = None - io_uring_prep_close_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_read = _libraries['FIXME_STUB'].io_uring_prep_read - io_uring_prep_read.restype = None - io_uring_prep_read.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_write = _libraries['FIXME_STUB'].io_uring_prep_write - io_uring_prep_write.restype = None - io_uring_prep_write.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -class struct_statx(Structure): - pass - -try: - io_uring_prep_statx = _libraries['FIXME_STUB'].io_uring_prep_statx - io_uring_prep_statx.restype = None - io_uring_prep_statx.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32, ctypes.POINTER(struct_statx)] -except AttributeError: - pass -off_t = ctypes.c_int64 -try: - io_uring_prep_fadvise = _libraries['FIXME_STUB'].io_uring_prep_fadvise - io_uring_prep_fadvise.restype = None - io_uring_prep_fadvise.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, __u64, off_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_madvise = _libraries['FIXME_STUB'].io_uring_prep_madvise - io_uring_prep_madvise.restype = None - io_uring_prep_madvise.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), off_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_send = _libraries['FIXME_STUB'].io_uring_prep_send - io_uring_prep_send.restype = None - io_uring_prep_send.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -__u16 = ctypes.c_uint16 -try: - io_uring_prep_send_set_addr = _libraries['FIXME_STUB'].io_uring_prep_send_set_addr - io_uring_prep_send_set_addr.restype = None - io_uring_prep_send_set_addr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct_sockaddr), __u16] -except AttributeError: - pass -try: - io_uring_prep_sendto = _libraries['FIXME_STUB'].io_uring_prep_sendto - io_uring_prep_sendto.restype = None - io_uring_prep_sendto.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.POINTER(struct_sockaddr), socklen_t] -except AttributeError: - pass -try: - io_uring_prep_send_zc = _libraries['FIXME_STUB'].io_uring_prep_send_zc - io_uring_prep_send_zc.restype = None - io_uring_prep_send_zc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_send_zc_fixed = _libraries['FIXME_STUB'].io_uring_prep_send_zc_fixed - io_uring_prep_send_zc_fixed.restype = None - io_uring_prep_send_zc_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_sendmsg_zc = _libraries['FIXME_STUB'].io_uring_prep_sendmsg_zc - io_uring_prep_sendmsg_zc.restype = None - io_uring_prep_sendmsg_zc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_recv = _libraries['FIXME_STUB'].io_uring_prep_recv - io_uring_prep_recv.restype = None - io_uring_prep_recv.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_recv_multishot = _libraries['FIXME_STUB'].io_uring_prep_recv_multishot - io_uring_prep_recv_multishot.restype = None - io_uring_prep_recv_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_recvmsg_out(Structure): - pass - -struct_io_uring_recvmsg_out._pack_ = 1 # source:False -struct_io_uring_recvmsg_out._fields_ = [ - ('namelen', ctypes.c_uint32), - ('controllen', ctypes.c_uint32), - ('payloadlen', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -try: - io_uring_recvmsg_validate = _libraries['FIXME_STUB'].io_uring_recvmsg_validate - io_uring_recvmsg_validate.restype = ctypes.POINTER(struct_io_uring_recvmsg_out) - io_uring_recvmsg_validate.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_name = _libraries['FIXME_STUB'].io_uring_recvmsg_name - io_uring_recvmsg_name.restype = ctypes.POINTER(None) - io_uring_recvmsg_name.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out)] -except AttributeError: - pass -class struct_cmsghdr(Structure): - pass - -struct_cmsghdr._pack_ = 1 # source:False -struct_cmsghdr._fields_ = [ - ('cmsg_len', ctypes.c_uint64), - ('cmsg_level', ctypes.c_int32), - ('cmsg_type', ctypes.c_int32), - ('__cmsg_data', ctypes.c_ubyte * 0), -] - -try: - io_uring_recvmsg_cmsg_firsthdr = _libraries['FIXME_STUB'].io_uring_recvmsg_cmsg_firsthdr - io_uring_recvmsg_cmsg_firsthdr.restype = ctypes.POINTER(struct_cmsghdr) - io_uring_recvmsg_cmsg_firsthdr.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_cmsg_nexthdr = _libraries['FIXME_STUB'].io_uring_recvmsg_cmsg_nexthdr - io_uring_recvmsg_cmsg_nexthdr.restype = ctypes.POINTER(struct_cmsghdr) - io_uring_recvmsg_cmsg_nexthdr.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr), ctypes.POINTER(struct_cmsghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_payload = _libraries['FIXME_STUB'].io_uring_recvmsg_payload - io_uring_recvmsg_payload.restype = ctypes.POINTER(None) - io_uring_recvmsg_payload.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_payload_length = _libraries['FIXME_STUB'].io_uring_recvmsg_payload_length - io_uring_recvmsg_payload_length.restype = ctypes.c_uint32 - io_uring_recvmsg_payload_length.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.c_int32, ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -class struct_open_how(Structure): - pass - -struct_open_how._pack_ = 1 # source:False -struct_open_how._fields_ = [ - ('flags', ctypes.c_uint64), - ('mode', ctypes.c_uint64), - ('resolve', ctypes.c_uint64), -] - -try: - io_uring_prep_openat2 = _libraries['FIXME_STUB'].io_uring_prep_openat2 - io_uring_prep_openat2.restype = None - io_uring_prep_openat2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_open_how)] -except AttributeError: - pass -try: - io_uring_prep_openat2_direct = _libraries['FIXME_STUB'].io_uring_prep_openat2_direct - io_uring_prep_openat2_direct.restype = None - io_uring_prep_openat2_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_open_how), ctypes.c_uint32] -except AttributeError: - pass -class struct_epoll_event(Structure): - pass - -try: - io_uring_prep_epoll_ctl = _libraries['FIXME_STUB'].io_uring_prep_epoll_ctl - io_uring_prep_epoll_ctl.restype = None - io_uring_prep_epoll_ctl.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(struct_epoll_event)] -except AttributeError: - pass -try: - io_uring_prep_provide_buffers = _libraries['FIXME_STUB'].io_uring_prep_provide_buffers - io_uring_prep_provide_buffers.restype = None - io_uring_prep_provide_buffers.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_remove_buffers = _libraries['FIXME_STUB'].io_uring_prep_remove_buffers - io_uring_prep_remove_buffers.restype = None - io_uring_prep_remove_buffers.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_shutdown = _libraries['FIXME_STUB'].io_uring_prep_shutdown - io_uring_prep_shutdown.restype = None - io_uring_prep_shutdown.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_unlinkat = _libraries['FIXME_STUB'].io_uring_prep_unlinkat - io_uring_prep_unlinkat.restype = None - io_uring_prep_unlinkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_unlink = _libraries['FIXME_STUB'].io_uring_prep_unlink - io_uring_prep_unlink.restype = None - io_uring_prep_unlink.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_renameat = _libraries['FIXME_STUB'].io_uring_prep_renameat - io_uring_prep_renameat.restype = None - io_uring_prep_renameat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_rename = _libraries['FIXME_STUB'].io_uring_prep_rename - io_uring_prep_rename.restype = None - io_uring_prep_rename.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_sync_file_range = _libraries['FIXME_STUB'].io_uring_prep_sync_file_range - io_uring_prep_sync_file_range.restype = None - io_uring_prep_sync_file_range.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_mkdirat = _libraries['FIXME_STUB'].io_uring_prep_mkdirat - io_uring_prep_mkdirat.restype = None - io_uring_prep_mkdirat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), mode_t] -except AttributeError: - pass -try: - io_uring_prep_mkdir = _libraries['FIXME_STUB'].io_uring_prep_mkdir - io_uring_prep_mkdir.restype = None - io_uring_prep_mkdir.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), mode_t] -except AttributeError: - pass -try: - io_uring_prep_symlinkat = _libraries['FIXME_STUB'].io_uring_prep_symlinkat - io_uring_prep_symlinkat.restype = None - io_uring_prep_symlinkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_symlink = _libraries['FIXME_STUB'].io_uring_prep_symlink - io_uring_prep_symlink.restype = None - io_uring_prep_symlink.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_linkat = _libraries['FIXME_STUB'].io_uring_prep_linkat - io_uring_prep_linkat.restype = None - io_uring_prep_linkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_link = _libraries['FIXME_STUB'].io_uring_prep_link - io_uring_prep_link.restype = None - io_uring_prep_link.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_cqe_flags = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_cqe_flags - io_uring_prep_msg_ring_cqe_flags.restype = None - io_uring_prep_msg_ring_cqe_flags.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring = _libraries['FIXME_STUB'].io_uring_prep_msg_ring - io_uring_prep_msg_ring.restype = None - io_uring_prep_msg_ring.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_fd = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_fd - io_uring_prep_msg_ring_fd.restype = None - io_uring_prep_msg_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_fd_alloc = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_fd_alloc - io_uring_prep_msg_ring_fd_alloc.restype = None - io_uring_prep_msg_ring_fd_alloc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_getxattr = _libraries['FIXME_STUB'].io_uring_prep_getxattr - io_uring_prep_getxattr.restype = None - io_uring_prep_getxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_setxattr = _libraries['FIXME_STUB'].io_uring_prep_setxattr - io_uring_prep_setxattr.restype = None - io_uring_prep_setxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fgetxattr = _libraries['FIXME_STUB'].io_uring_prep_fgetxattr - io_uring_prep_fgetxattr.restype = None - io_uring_prep_fgetxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fsetxattr = _libraries['FIXME_STUB'].io_uring_prep_fsetxattr - io_uring_prep_fsetxattr.restype = None - io_uring_prep_fsetxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket = _libraries['FIXME_STUB'].io_uring_prep_socket - io_uring_prep_socket.restype = None - io_uring_prep_socket.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket_direct = _libraries['FIXME_STUB'].io_uring_prep_socket_direct - io_uring_prep_socket_direct.restype = None - io_uring_prep_socket_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket_direct_alloc = _libraries['FIXME_STUB'].io_uring_prep_socket_direct_alloc - io_uring_prep_socket_direct_alloc.restype = None - io_uring_prep_socket_direct_alloc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_cmd_sock = _libraries['FIXME_STUB'].io_uring_prep_cmd_sock - io_uring_prep_cmd_sock.restype = None - io_uring_prep_cmd_sock.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_sq_ready = _libraries['FIXME_STUB'].io_uring_sq_ready - io_uring_sq_ready.restype = ctypes.c_uint32 - io_uring_sq_ready.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_sq_space_left = _libraries['FIXME_STUB'].io_uring_sq_space_left - io_uring_sq_space_left.restype = ctypes.c_uint32 - io_uring_sq_space_left.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_sqring_wait = _libraries['FIXME_STUB'].io_uring_sqring_wait - io_uring_sqring_wait.restype = ctypes.c_int32 - io_uring_sqring_wait.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_ready = _libraries['FIXME_STUB'].io_uring_cq_ready - io_uring_cq_ready.restype = ctypes.c_uint32 - io_uring_cq_ready.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_has_overflow = _libraries['FIXME_STUB'].io_uring_cq_has_overflow - io_uring_cq_has_overflow.restype = ctypes.c_bool - io_uring_cq_has_overflow.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_eventfd_enabled = _libraries['FIXME_STUB'].io_uring_cq_eventfd_enabled - io_uring_cq_eventfd_enabled.restype = ctypes.c_bool - io_uring_cq_eventfd_enabled.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_eventfd_toggle = _libraries['FIXME_STUB'].io_uring_cq_eventfd_toggle - io_uring_cq_eventfd_toggle.restype = ctypes.c_int32 - io_uring_cq_eventfd_toggle.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_bool] -except AttributeError: - pass -try: - io_uring_wait_cqe_nr = _libraries['FIXME_STUB'].io_uring_wait_cqe_nr - io_uring_wait_cqe_nr.restype = ctypes.c_int32 - io_uring_wait_cqe_nr.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_peek_cqe = _libraries['FIXME_STUB'].__io_uring_peek_cqe - __io_uring_peek_cqe.restype = ctypes.c_int32 - __io_uring_peek_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - io_uring_peek_cqe = _libraries['FIXME_STUB'].io_uring_peek_cqe - io_uring_peek_cqe.restype = ctypes.c_int32 - io_uring_peek_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe))] -except AttributeError: - pass -try: - io_uring_wait_cqe = _libraries['FIXME_STUB'].io_uring_wait_cqe - io_uring_wait_cqe.restype = ctypes.c_int32 - io_uring_wait_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe))] -except AttributeError: - pass -try: - _io_uring_get_sqe = _libraries['FIXME_STUB']._io_uring_get_sqe - _io_uring_get_sqe.restype = ctypes.POINTER(struct_io_uring_sqe) - _io_uring_get_sqe.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -__u32 = ctypes.c_uint32 -try: - io_uring_buf_ring_mask = _libraries['FIXME_STUB'].io_uring_buf_ring_mask - io_uring_buf_ring_mask.restype = ctypes.c_int32 - io_uring_buf_ring_mask.argtypes = [__u32] -except AttributeError: - pass -try: - io_uring_buf_ring_init = _libraries['FIXME_STUB'].io_uring_buf_ring_init - io_uring_buf_ring_init.restype = None - io_uring_buf_ring_init.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring)] -except AttributeError: - pass -try: - io_uring_buf_ring_add = _libraries['FIXME_STUB'].io_uring_buf_ring_add - io_uring_buf_ring_add.restype = None - io_uring_buf_ring_add.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint16, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_buf_ring_advance = _libraries['FIXME_STUB'].io_uring_buf_ring_advance - io_uring_buf_ring_advance.restype = None - io_uring_buf_ring_advance.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32] -except AttributeError: - pass -try: - __io_uring_buf_ring_cq_advance = _libraries['FIXME_STUB'].__io_uring_buf_ring_cq_advance - __io_uring_buf_ring_cq_advance.restype = None - __io_uring_buf_ring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_buf_ring_cq_advance = _libraries['FIXME_STUB'].io_uring_buf_ring_cq_advance - io_uring_buf_ring_cq_advance.restype = None - io_uring_buf_ring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_get_sqe = _libraries['FIXME_STUB'].io_uring_get_sqe - io_uring_get_sqe.restype = ctypes.POINTER(struct_io_uring_sqe) - io_uring_get_sqe.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - io_uring_mlock_size = _libraries['FIXME_STUB'].io_uring_mlock_size - io_uring_mlock_size.restype = ssize_t - io_uring_mlock_size.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_mlock_size_params = _libraries['FIXME_STUB'].io_uring_mlock_size_params - io_uring_mlock_size_params.restype = ssize_t - io_uring_mlock_size_params.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_major_version = _libraries['FIXME_STUB'].io_uring_major_version - io_uring_major_version.restype = ctypes.c_int32 - io_uring_major_version.argtypes = [] -except AttributeError: - pass -try: - io_uring_minor_version = _libraries['FIXME_STUB'].io_uring_minor_version - io_uring_minor_version.restype = ctypes.c_int32 - io_uring_minor_version.argtypes = [] -except AttributeError: - pass -try: - io_uring_check_version = _libraries['FIXME_STUB'].io_uring_check_version - io_uring_check_version.restype = ctypes.c_bool - io_uring_check_version.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -LINUX_IO_URING_H = True # macro -IORING_FILE_INDEX_ALLOC = (~0) # macro -IORING_SETUP_IOPOLL = (1<<0) # macro -IORING_SETUP_SQPOLL = (1<<1) # macro -IORING_SETUP_SQ_AFF = (1<<2) # macro -IORING_SETUP_CQSIZE = (1<<3) # macro -IORING_SETUP_CLAMP = (1<<4) # macro -IORING_SETUP_ATTACH_WQ = (1<<5) # macro -IORING_SETUP_R_DISABLED = (1<<6) # macro -IORING_SETUP_SUBMIT_ALL = (1<<7) # macro -IORING_SETUP_COOP_TASKRUN = (1<<8) # macro -IORING_SETUP_TASKRUN_FLAG = (1<<9) # macro -IORING_SETUP_SQE128 = (1<<10) # macro -IORING_SETUP_CQE32 = (1<<11) # macro -# def io_uring_cqe_shift(ring): # macro -# return (!!((ring)->flags&IORING_SETUP_CQE32)) -IORING_SETUP_SINGLE_ISSUER = (1<<12) # macro -IORING_SETUP_DEFER_TASKRUN = (1<<13) # macro -IORING_SETUP_NO_MMAP = (1<<14) # macro -IORING_SETUP_REGISTERED_FD_ONLY = (1<<15) # macro -IORING_SETUP_NO_SQARRAY = (1<<16) # macro -IORING_URING_CMD_FIXED = (1<<0) # macro -IORING_URING_CMD_MASK = (1<<0) # macro -IORING_FSYNC_DATASYNC = (1<<0) # macro -IORING_TIMEOUT_ABS = (1<<0) # macro -IORING_TIMEOUT_UPDATE = (1<<1) # macro -IORING_TIMEOUT_BOOTTIME = (1<<2) # macro -IORING_TIMEOUT_REALTIME = (1<<3) # macro -IORING_LINK_TIMEOUT_UPDATE = (1<<4) # macro -IORING_TIMEOUT_ETIME_SUCCESS = (1<<5) # macro -IORING_TIMEOUT_MULTISHOT = (1<<6) # macro -IORING_TIMEOUT_CLOCK_MASK = ((1<<2)|(1<<3)) # macro -IORING_TIMEOUT_UPDATE_MASK = ((1<<1)|(1<<4)) # macro -SPLICE_F_FD_IN_FIXED = (1<<31) # macro -IORING_POLL_ADD_MULTI = (1<<0) # macro -IORING_POLL_UPDATE_EVENTS = (1<<1) # macro -IORING_POLL_UPDATE_USER_DATA = (1<<2) # macro -IORING_POLL_ADD_LEVEL = (1<<3) # macro -IORING_ASYNC_CANCEL_ALL = (1<<0) # macro -IORING_ASYNC_CANCEL_FD = (1<<1) # macro -IORING_ASYNC_CANCEL_ANY = (1<<2) # macro -IORING_ASYNC_CANCEL_FD_FIXED = (1<<3) # macro -IORING_ASYNC_CANCEL_USERDATA = (1<<4) # macro -IORING_ASYNC_CANCEL_OP = (1<<5) # macro -IORING_RECVSEND_POLL_FIRST = (1<<0) # macro -IORING_RECV_MULTISHOT = (1<<1) # macro -IORING_RECVSEND_FIXED_BUF = (1<<2) # macro -IORING_SEND_ZC_REPORT_USAGE = (1<<3) # macro -IORING_NOTIF_USAGE_ZC_COPIED = (1<<31) # macro -IORING_ACCEPT_MULTISHOT = (1<<0) # macro -IORING_MSG_RING_CQE_SKIP = (1<<0) # macro -IORING_MSG_RING_FLAGS_PASS = (1<<1) # macro -IORING_FIXED_FD_NO_CLOEXEC = (1<<0) # macro -IORING_CQE_F_BUFFER = (1<<0) # macro -IORING_CQE_F_MORE = (1<<1) # macro -IORING_CQE_F_SOCK_NONEMPTY = (1<<2) # macro -IORING_CQE_F_NOTIF = (1<<3) # macro -IORING_OFF_SQ_RING = 0 # macro -IORING_OFF_CQ_RING = 0x8000000 # macro -IORING_OFF_SQES = 0x10000000 # macro -IORING_OFF_PBUF_RING = 0x80000000 # macro -IORING_OFF_PBUF_SHIFT = 16 # macro -IORING_OFF_MMAP_MASK = 0xf8000000 # macro -IORING_SQ_NEED_WAKEUP = (1<<0) # macro -IORING_SQ_CQ_OVERFLOW = (1<<1) # macro -IORING_SQ_TASKRUN = (1<<2) # macro -IORING_CQ_EVENTFD_DISABLED = (1<<0) # macro -IORING_ENTER_GETEVENTS = (1<<0) # macro -IORING_ENTER_SQ_WAKEUP = (1<<1) # macro -IORING_ENTER_SQ_WAIT = (1<<2) # macro -IORING_ENTER_EXT_ARG = (1<<3) # macro -IORING_ENTER_REGISTERED_RING = (1<<4) # macro -IORING_FEAT_SINGLE_MMAP = (1<<0) # macro -IORING_FEAT_NODROP = (1<<1) # macro -IORING_FEAT_SUBMIT_STABLE = (1<<2) # macro -IORING_FEAT_RW_CUR_POS = (1<<3) # macro -IORING_FEAT_CUR_PERSONALITY = (1<<4) # macro -IORING_FEAT_FAST_POLL = (1<<5) # macro -IORING_FEAT_POLL_32BITS = (1<<6) # macro -IORING_FEAT_SQPOLL_NONFIXED = (1<<7) # macro -IORING_FEAT_EXT_ARG = (1<<8) # macro -IORING_FEAT_NATIVE_WORKERS = (1<<9) # macro -IORING_FEAT_RSRC_TAGS = (1<<10) # macro -IORING_FEAT_CQE_SKIP = (1<<11) # macro -IORING_FEAT_LINKED_FILE = (1<<12) # macro -IORING_FEAT_REG_REG_RING = (1<<13) # macro -IORING_RSRC_REGISTER_SPARSE = (1<<0) # macro -IORING_REGISTER_FILES_SKIP = (-2) # macro -IO_URING_OP_SUPPORTED = (1<<0) # macro - -# values for enumeration 'c__Ea_IOSQE_FIXED_FILE_BIT' -c__Ea_IOSQE_FIXED_FILE_BIT__enumvalues = { - 0: 'IOSQE_FIXED_FILE_BIT', - 1: 'IOSQE_IO_DRAIN_BIT', - 2: 'IOSQE_IO_LINK_BIT', - 3: 'IOSQE_IO_HARDLINK_BIT', - 4: 'IOSQE_ASYNC_BIT', - 5: 'IOSQE_BUFFER_SELECT_BIT', - 6: 'IOSQE_CQE_SKIP_SUCCESS_BIT', -} -IOSQE_FIXED_FILE_BIT = 0 -IOSQE_IO_DRAIN_BIT = 1 -IOSQE_IO_LINK_BIT = 2 -IOSQE_IO_HARDLINK_BIT = 3 -IOSQE_ASYNC_BIT = 4 -IOSQE_BUFFER_SELECT_BIT = 5 -IOSQE_CQE_SKIP_SUCCESS_BIT = 6 -c__Ea_IOSQE_FIXED_FILE_BIT = ctypes.c_uint32 # enum -IOSQE_FIXED_FILE = (1<= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -KFD_IOCTL_H_INCLUDED = True # macro -KFD_IOCTL_MAJOR_VERSION = 1 # macro -KFD_IOCTL_MINOR_VERSION = 14 # macro -KFD_IOC_QUEUE_TYPE_COMPUTE = 0x0 # macro -KFD_IOC_QUEUE_TYPE_SDMA = 0x1 # macro -KFD_IOC_QUEUE_TYPE_COMPUTE_AQL = 0x2 # macro -KFD_IOC_QUEUE_TYPE_SDMA_XGMI = 0x3 # macro -KFD_MAX_QUEUE_PERCENTAGE = 100 # macro -KFD_MAX_QUEUE_PRIORITY = 15 # macro -KFD_IOC_CACHE_POLICY_COHERENT = 0 # macro -KFD_IOC_CACHE_POLICY_NONCOHERENT = 1 # macro -NUM_OF_SUPPORTED_GPUS = 7 # macro -MAX_ALLOWED_NUM_POINTS = 100 # macro -MAX_ALLOWED_AW_BUFF_SIZE = 4096 # macro -MAX_ALLOWED_WAC_BUFF_SIZE = 128 # macro -KFD_INVALID_FD = 0xffffffff # macro -KFD_IOC_EVENT_SIGNAL = 0 # macro -KFD_IOC_EVENT_NODECHANGE = 1 # macro -KFD_IOC_EVENT_DEVICESTATECHANGE = 2 # macro -KFD_IOC_EVENT_HW_EXCEPTION = 3 # macro -KFD_IOC_EVENT_SYSTEM_EVENT = 4 # macro -KFD_IOC_EVENT_DEBUG_EVENT = 5 # macro -KFD_IOC_EVENT_PROFILE_EVENT = 6 # macro -KFD_IOC_EVENT_QUEUE_EVENT = 7 # macro -KFD_IOC_EVENT_MEMORY = 8 # macro -KFD_IOC_WAIT_RESULT_COMPLETE = 0 # macro -KFD_IOC_WAIT_RESULT_TIMEOUT = 1 # macro -KFD_IOC_WAIT_RESULT_FAIL = 2 # macro -KFD_SIGNAL_EVENT_LIMIT = 4096 # macro -KFD_HW_EXCEPTION_WHOLE_GPU_RESET = 0 # macro -KFD_HW_EXCEPTION_PER_ENGINE_RESET = 1 # macro -KFD_HW_EXCEPTION_GPU_HANG = 0 # macro -KFD_HW_EXCEPTION_ECC = 1 # macro -KFD_MEM_ERR_NO_RAS = 0 # macro -KFD_MEM_ERR_SRAM_ECC = 1 # macro -KFD_MEM_ERR_POISON_CONSUMED = 2 # macro -KFD_MEM_ERR_GPU_HANG = 3 # macro -KFD_IOC_ALLOC_MEM_FLAGS_VRAM = (1<<0) # macro -KFD_IOC_ALLOC_MEM_FLAGS_GTT = (1<<1) # macro -KFD_IOC_ALLOC_MEM_FLAGS_USERPTR = (1<<2) # macro -KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL = (1<<3) # macro -KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP = (1<<4) # macro -KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE = (1<<31) # macro -KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE = (1<<30) # macro -KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC = (1<<29) # macro -KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE = (1<<28) # macro -KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM = (1<<27) # macro -KFD_IOC_ALLOC_MEM_FLAGS_COHERENT = (1<<26) # macro -KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED = (1<<25) # macro -KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT = (1<<24) # macro -def KFD_SMI_EVENT_MASK_FROM_INDEX(i): # macro - return (1<<((i)-1)) -KFD_SMI_EVENT_MSG_SIZE = 96 # macro -KFD_IOCTL_SVM_FLAG_HOST_ACCESS = 0x00000001 # macro -KFD_IOCTL_SVM_FLAG_COHERENT = 0x00000002 # macro -KFD_IOCTL_SVM_FLAG_HIVE_LOCAL = 0x00000004 # macro -KFD_IOCTL_SVM_FLAG_GPU_RO = 0x00000008 # macro -KFD_IOCTL_SVM_FLAG_GPU_EXEC = 0x00000010 # macro -KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY = 0x00000020 # macro -KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED = 0x00000040 # macro -KFD_IOCTL_SVM_FLAG_EXT_COHERENT = 0x00000080 # macro -def KFD_EC_MASK(ecode): # macro - return (1<<(ecode-1)) -KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK = 1 # macro -KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK = 2 # macro -KFD_DBG_QUEUE_ERROR_BIT = 30 # macro -KFD_DBG_QUEUE_INVALID_BIT = 31 # macro -KFD_DBG_QUEUE_ERROR_MASK = (1<<30) # macro -KFD_DBG_QUEUE_INVALID_MASK = (1<<31) # macro -AMDKFD_IOCTL_BASE = 'K' # macro -def AMDKFD_IO(nr): # macro - return _IO('K',nr) -def AMDKFD_IOR(nr, type): # macro - return _IOR('K',nr,type) -def AMDKFD_IOW(nr, type): # macro - return _IOW('K',nr,type) -def AMDKFD_IOWR(nr, type): # macro - return _IOWR('K',nr,type) -AMDKFD_COMMAND_START = 0x01 # macro -AMDKFD_COMMAND_END = 0x27 # macro -class struct_kfd_ioctl_get_version_args(Structure): - pass - -struct_kfd_ioctl_get_version_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_version_args._fields_ = [ - ('major_version', ctypes.c_uint32), - ('minor_version', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_VERSION = AMDKFD_IOR ( 0x01 , struct_kfd_ioctl_get_version_args ) # macro (from list) -class struct_kfd_ioctl_create_queue_args(Structure): - pass - -struct_kfd_ioctl_create_queue_args._pack_ = 1 # source:False -struct_kfd_ioctl_create_queue_args._fields_ = [ - ('ring_base_address', ctypes.c_uint64), - ('write_pointer_address', ctypes.c_uint64), - ('read_pointer_address', ctypes.c_uint64), - ('doorbell_offset', ctypes.c_uint64), - ('ring_size', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('queue_type', ctypes.c_uint32), - ('queue_percentage', ctypes.c_uint32), - ('queue_priority', ctypes.c_uint32), - ('queue_id', ctypes.c_uint32), - ('eop_buffer_address', ctypes.c_uint64), - ('eop_buffer_size', ctypes.c_uint64), - ('ctx_save_restore_address', ctypes.c_uint64), - ('ctx_save_restore_size', ctypes.c_uint32), - ('ctl_stack_size', ctypes.c_uint32), -] - -AMDKFD_IOC_CREATE_QUEUE = AMDKFD_IOWR ( 0x02 , struct_kfd_ioctl_create_queue_args ) # macro (from list) -class struct_kfd_ioctl_destroy_queue_args(Structure): - pass - -struct_kfd_ioctl_destroy_queue_args._pack_ = 1 # source:False -struct_kfd_ioctl_destroy_queue_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_DESTROY_QUEUE = AMDKFD_IOWR ( 0x03 , struct_kfd_ioctl_destroy_queue_args ) # macro (from list) -class struct_kfd_ioctl_update_queue_args(Structure): - pass - -struct_kfd_ioctl_update_queue_args._pack_ = 1 # source:False -struct_kfd_ioctl_update_queue_args._fields_ = [ - ('ring_base_address', ctypes.c_uint64), - ('queue_id', ctypes.c_uint32), - ('ring_size', ctypes.c_uint32), - ('queue_percentage', ctypes.c_uint32), - ('queue_priority', ctypes.c_uint32), -] - -AMDKFD_IOC_UPDATE_QUEUE = AMDKFD_IOW ( 0x07 , struct_kfd_ioctl_update_queue_args ) # macro (from list) -class struct_kfd_ioctl_set_cu_mask_args(Structure): - pass - -struct_kfd_ioctl_set_cu_mask_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_cu_mask_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('num_cu_mask', ctypes.c_uint32), - ('cu_mask_ptr', ctypes.c_uint64), -] - -AMDKFD_IOC_SET_CU_MASK = AMDKFD_IOW ( 0x1A , struct_kfd_ioctl_set_cu_mask_args ) # macro (from list) -class struct_kfd_ioctl_get_queue_wave_state_args(Structure): - pass - -struct_kfd_ioctl_get_queue_wave_state_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_queue_wave_state_args._fields_ = [ - ('ctl_stack_address', ctypes.c_uint64), - ('ctl_stack_used_size', ctypes.c_uint32), - ('save_area_used_size', ctypes.c_uint32), - ('queue_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_QUEUE_WAVE_STATE = AMDKFD_IOWR ( 0x1B , struct_kfd_ioctl_get_queue_wave_state_args ) # macro (from list) -class struct_kfd_ioctl_get_available_memory_args(Structure): - pass - -struct_kfd_ioctl_get_available_memory_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_available_memory_args._fields_ = [ - ('available', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_AVAILABLE_MEMORY = AMDKFD_IOWR ( 0x23 , struct_kfd_ioctl_get_available_memory_args ) # macro (from list) -class struct_kfd_dbg_device_info_entry(Structure): - pass - -struct_kfd_dbg_device_info_entry._pack_ = 1 # source:False -struct_kfd_dbg_device_info_entry._fields_ = [ - ('exception_status', ctypes.c_uint64), - ('lds_base', ctypes.c_uint64), - ('lds_limit', ctypes.c_uint64), - ('scratch_base', ctypes.c_uint64), - ('scratch_limit', ctypes.c_uint64), - ('gpuvm_base', ctypes.c_uint64), - ('gpuvm_limit', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('location_id', ctypes.c_uint32), - ('vendor_id', ctypes.c_uint32), - ('device_id', ctypes.c_uint32), - ('revision_id', ctypes.c_uint32), - ('subsystem_vendor_id', ctypes.c_uint32), - ('subsystem_device_id', ctypes.c_uint32), - ('fw_version', ctypes.c_uint32), - ('gfx_target_version', ctypes.c_uint32), - ('simd_count', ctypes.c_uint32), - ('max_waves_per_simd', ctypes.c_uint32), - ('array_count', ctypes.c_uint32), - ('simd_arrays_per_engine', ctypes.c_uint32), - ('num_xcc', ctypes.c_uint32), - ('capability', ctypes.c_uint32), - ('debug_prop', ctypes.c_uint32), -] - -class struct_kfd_ioctl_set_memory_policy_args(Structure): - pass - -struct_kfd_ioctl_set_memory_policy_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_memory_policy_args._fields_ = [ - ('alternate_aperture_base', ctypes.c_uint64), - ('alternate_aperture_size', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('default_policy', ctypes.c_uint32), - ('alternate_policy', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_SET_MEMORY_POLICY = AMDKFD_IOW ( 0x04 , struct_kfd_ioctl_set_memory_policy_args ) # macro (from list) -class struct_kfd_ioctl_get_clock_counters_args(Structure): - pass - -struct_kfd_ioctl_get_clock_counters_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_clock_counters_args._fields_ = [ - ('gpu_clock_counter', ctypes.c_uint64), - ('cpu_clock_counter', ctypes.c_uint64), - ('system_clock_counter', ctypes.c_uint64), - ('system_clock_freq', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_CLOCK_COUNTERS = AMDKFD_IOWR ( 0x05 , struct_kfd_ioctl_get_clock_counters_args ) # macro (from list) -class struct_kfd_process_device_apertures(Structure): - pass - -struct_kfd_process_device_apertures._pack_ = 1 # source:False -struct_kfd_process_device_apertures._fields_ = [ - ('lds_base', ctypes.c_uint64), - ('lds_limit', ctypes.c_uint64), - ('scratch_base', ctypes.c_uint64), - ('scratch_limit', ctypes.c_uint64), - ('gpuvm_base', ctypes.c_uint64), - ('gpuvm_limit', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -class struct_kfd_ioctl_get_process_apertures_args(Structure): - pass - -struct_kfd_ioctl_get_process_apertures_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_process_apertures_args._fields_ = [ - ('process_apertures', struct_kfd_process_device_apertures * 7), - ('num_of_nodes', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_PROCESS_APERTURES = AMDKFD_IOR ( 0x06 , struct_kfd_ioctl_get_process_apertures_args ) # macro (from list) -class struct_kfd_ioctl_get_process_apertures_new_args(Structure): - pass - -struct_kfd_ioctl_get_process_apertures_new_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_process_apertures_new_args._fields_ = [ - ('kfd_process_device_apertures_ptr', ctypes.c_uint64), - ('num_of_nodes', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_PROCESS_APERTURES_NEW = AMDKFD_IOWR ( 0x14 , struct_kfd_ioctl_get_process_apertures_new_args ) # macro (from list) -class struct_kfd_ioctl_dbg_register_args(Structure): - pass - -struct_kfd_ioctl_dbg_register_args._pack_ = 1 # source:False -struct_kfd_ioctl_dbg_register_args._fields_ = [ - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_DBG_REGISTER_DEPRECATED = AMDKFD_IOW ( 0x0D , struct_kfd_ioctl_dbg_register_args ) # macro (from list) -class struct_kfd_ioctl_dbg_unregister_args(Structure): - pass - -struct_kfd_ioctl_dbg_unregister_args._pack_ = 1 # source:False -struct_kfd_ioctl_dbg_unregister_args._fields_ = [ - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED = AMDKFD_IOW ( 0x0E , struct_kfd_ioctl_dbg_unregister_args ) # macro (from list) -class struct_kfd_ioctl_dbg_address_watch_args(Structure): - pass - -struct_kfd_ioctl_dbg_address_watch_args._pack_ = 1 # source:False -struct_kfd_ioctl_dbg_address_watch_args._fields_ = [ - ('content_ptr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('buf_size_in_bytes', ctypes.c_uint32), -] - -AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED = AMDKFD_IOW ( 0x0F , struct_kfd_ioctl_dbg_address_watch_args ) # macro (from list) -class struct_kfd_ioctl_dbg_wave_control_args(Structure): - pass - -struct_kfd_ioctl_dbg_wave_control_args._pack_ = 1 # source:False -struct_kfd_ioctl_dbg_wave_control_args._fields_ = [ - ('content_ptr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('buf_size_in_bytes', ctypes.c_uint32), -] - -AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED = AMDKFD_IOW ( 0x10 , struct_kfd_ioctl_dbg_wave_control_args ) # macro (from list) -class struct_kfd_ioctl_create_event_args(Structure): - pass - -struct_kfd_ioctl_create_event_args._pack_ = 1 # source:False -struct_kfd_ioctl_create_event_args._fields_ = [ - ('event_page_offset', ctypes.c_uint64), - ('event_trigger_data', ctypes.c_uint32), - ('event_type', ctypes.c_uint32), - ('auto_reset', ctypes.c_uint32), - ('node_id', ctypes.c_uint32), - ('event_id', ctypes.c_uint32), - ('event_slot_index', ctypes.c_uint32), -] - -AMDKFD_IOC_CREATE_EVENT = AMDKFD_IOWR ( 0x08 , struct_kfd_ioctl_create_event_args ) # macro (from list) -class struct_kfd_ioctl_destroy_event_args(Structure): - pass - -struct_kfd_ioctl_destroy_event_args._pack_ = 1 # source:False -struct_kfd_ioctl_destroy_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_DESTROY_EVENT = AMDKFD_IOW ( 0x09 , struct_kfd_ioctl_destroy_event_args ) # macro (from list) -class struct_kfd_ioctl_set_event_args(Structure): - pass - -struct_kfd_ioctl_set_event_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_SET_EVENT = AMDKFD_IOW ( 0x0A , struct_kfd_ioctl_set_event_args ) # macro (from list) -class struct_kfd_ioctl_reset_event_args(Structure): - pass - -struct_kfd_ioctl_reset_event_args._pack_ = 1 # source:False -struct_kfd_ioctl_reset_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_RESET_EVENT = AMDKFD_IOW ( 0x0B , struct_kfd_ioctl_reset_event_args ) # macro (from list) -class struct_kfd_memory_exception_failure(Structure): - pass - -struct_kfd_memory_exception_failure._pack_ = 1 # source:False -struct_kfd_memory_exception_failure._fields_ = [ - ('NotPresent', ctypes.c_uint32), - ('ReadOnly', ctypes.c_uint32), - ('NoExecute', ctypes.c_uint32), - ('imprecise', ctypes.c_uint32), -] - -class struct_kfd_hsa_memory_exception_data(Structure): - pass - -struct_kfd_hsa_memory_exception_data._pack_ = 1 # source:False -struct_kfd_hsa_memory_exception_data._fields_ = [ - ('failure', struct_kfd_memory_exception_failure), - ('va', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('ErrorType', ctypes.c_uint32), -] - -class struct_kfd_hsa_hw_exception_data(Structure): - pass - -struct_kfd_hsa_hw_exception_data._pack_ = 1 # source:False -struct_kfd_hsa_hw_exception_data._fields_ = [ - ('reset_type', ctypes.c_uint32), - ('reset_cause', ctypes.c_uint32), - ('memory_lost', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), -] - -class struct_kfd_hsa_signal_event_data(Structure): - pass - -struct_kfd_hsa_signal_event_data._pack_ = 1 # source:False -struct_kfd_hsa_signal_event_data._fields_ = [ - ('last_event_age', ctypes.c_uint64), -] - -class struct_kfd_event_data(Structure): - pass - -class union_kfd_event_data_0(Union): - pass - -union_kfd_event_data_0._pack_ = 1 # source:False -union_kfd_event_data_0._fields_ = [ - ('memory_exception_data', struct_kfd_hsa_memory_exception_data), - ('hw_exception_data', struct_kfd_hsa_hw_exception_data), - ('signal_event_data', struct_kfd_hsa_signal_event_data), - ('PADDING_0', ctypes.c_ubyte * 24), -] - -struct_kfd_event_data._pack_ = 1 # source:False -struct_kfd_event_data._anonymous_ = ('_0',) -struct_kfd_event_data._fields_ = [ - ('_0', union_kfd_event_data_0), - ('kfd_event_data_ext', ctypes.c_uint64), - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -class struct_kfd_ioctl_wait_events_args(Structure): - pass - -struct_kfd_ioctl_wait_events_args._pack_ = 1 # source:False -struct_kfd_ioctl_wait_events_args._fields_ = [ - ('events_ptr', ctypes.c_uint64), - ('num_events', ctypes.c_uint32), - ('wait_for_all', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), - ('wait_result', ctypes.c_uint32), -] - -AMDKFD_IOC_WAIT_EVENTS = AMDKFD_IOWR ( 0x0C , struct_kfd_ioctl_wait_events_args ) # macro (from list) -class struct_kfd_ioctl_set_scratch_backing_va_args(Structure): - pass - -struct_kfd_ioctl_set_scratch_backing_va_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_scratch_backing_va_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_SET_SCRATCH_BACKING_VA = AMDKFD_IOWR ( 0x11 , struct_kfd_ioctl_set_scratch_backing_va_args ) # macro (from list) -class struct_kfd_ioctl_get_tile_config_args(Structure): - pass - -struct_kfd_ioctl_get_tile_config_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_tile_config_args._fields_ = [ - ('tile_config_ptr', ctypes.c_uint64), - ('macro_tile_config_ptr', ctypes.c_uint64), - ('num_tile_configs', ctypes.c_uint32), - ('num_macro_tile_configs', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('gb_addr_config', ctypes.c_uint32), - ('num_banks', ctypes.c_uint32), - ('num_ranks', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_TILE_CONFIG = AMDKFD_IOWR ( 0x12 , struct_kfd_ioctl_get_tile_config_args ) # macro (from list) -class struct_kfd_ioctl_set_trap_handler_args(Structure): - pass - -struct_kfd_ioctl_set_trap_handler_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_trap_handler_args._fields_ = [ - ('tba_addr', ctypes.c_uint64), - ('tma_addr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_SET_TRAP_HANDLER = AMDKFD_IOW ( 0x13 , struct_kfd_ioctl_set_trap_handler_args ) # macro (from list) -class struct_kfd_ioctl_acquire_vm_args(Structure): - pass - -struct_kfd_ioctl_acquire_vm_args._pack_ = 1 # source:False -struct_kfd_ioctl_acquire_vm_args._fields_ = [ - ('drm_fd', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), -] - -AMDKFD_IOC_ACQUIRE_VM = AMDKFD_IOW ( 0x15 , struct_kfd_ioctl_acquire_vm_args ) # macro (from list) -class struct_kfd_ioctl_alloc_memory_of_gpu_args(Structure): - pass - -struct_kfd_ioctl_alloc_memory_of_gpu_args._pack_ = 1 # source:False -struct_kfd_ioctl_alloc_memory_of_gpu_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('handle', ctypes.c_uint64), - ('mmap_offset', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -AMDKFD_IOC_ALLOC_MEMORY_OF_GPU = AMDKFD_IOWR ( 0x16 , struct_kfd_ioctl_alloc_memory_of_gpu_args ) # macro (from list) -class struct_kfd_ioctl_free_memory_of_gpu_args(Structure): - pass - -struct_kfd_ioctl_free_memory_of_gpu_args._pack_ = 1 # source:False -struct_kfd_ioctl_free_memory_of_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), -] - -AMDKFD_IOC_FREE_MEMORY_OF_GPU = AMDKFD_IOW ( 0x17 , struct_kfd_ioctl_free_memory_of_gpu_args ) # macro (from list) -class struct_kfd_ioctl_map_memory_to_gpu_args(Structure): - pass - -struct_kfd_ioctl_map_memory_to_gpu_args._pack_ = 1 # source:False -struct_kfd_ioctl_map_memory_to_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('device_ids_array_ptr', ctypes.c_uint64), - ('n_devices', ctypes.c_uint32), - ('n_success', ctypes.c_uint32), -] - -AMDKFD_IOC_MAP_MEMORY_TO_GPU = AMDKFD_IOWR ( 0x18 , struct_kfd_ioctl_map_memory_to_gpu_args ) # macro (from list) -class struct_kfd_ioctl_unmap_memory_from_gpu_args(Structure): - pass - -struct_kfd_ioctl_unmap_memory_from_gpu_args._pack_ = 1 # source:False -struct_kfd_ioctl_unmap_memory_from_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('device_ids_array_ptr', ctypes.c_uint64), - ('n_devices', ctypes.c_uint32), - ('n_success', ctypes.c_uint32), -] - -AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU = AMDKFD_IOWR ( 0x19 , struct_kfd_ioctl_unmap_memory_from_gpu_args ) # macro (from list) -class struct_kfd_ioctl_alloc_queue_gws_args(Structure): - pass - -struct_kfd_ioctl_alloc_queue_gws_args._pack_ = 1 # source:False -struct_kfd_ioctl_alloc_queue_gws_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('num_gws', ctypes.c_uint32), - ('first_gws', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -AMDKFD_IOC_ALLOC_QUEUE_GWS = AMDKFD_IOWR ( 0x1E , struct_kfd_ioctl_alloc_queue_gws_args ) # macro (from list) -class struct_kfd_ioctl_get_dmabuf_info_args(Structure): - pass - -struct_kfd_ioctl_get_dmabuf_info_args._pack_ = 1 # source:False -struct_kfd_ioctl_get_dmabuf_info_args._fields_ = [ - ('size', ctypes.c_uint64), - ('metadata_ptr', ctypes.c_uint64), - ('metadata_size', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), -] - -AMDKFD_IOC_GET_DMABUF_INFO = AMDKFD_IOWR ( 0x1C , struct_kfd_ioctl_get_dmabuf_info_args ) # macro (from list) -class struct_kfd_ioctl_import_dmabuf_args(Structure): - pass - -struct_kfd_ioctl_import_dmabuf_args._pack_ = 1 # source:False -struct_kfd_ioctl_import_dmabuf_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('handle', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), -] - -AMDKFD_IOC_IMPORT_DMABUF = AMDKFD_IOWR ( 0x1D , struct_kfd_ioctl_import_dmabuf_args ) # macro (from list) -class struct_kfd_ioctl_export_dmabuf_args(Structure): - pass - -struct_kfd_ioctl_export_dmabuf_args._pack_ = 1 # source:False -struct_kfd_ioctl_export_dmabuf_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), -] - -AMDKFD_IOC_EXPORT_DMABUF = AMDKFD_IOWR ( 0x24 , struct_kfd_ioctl_export_dmabuf_args ) # macro (from list) - -# values for enumeration 'kfd_smi_event' -kfd_smi_event__enumvalues = { - 0: 'KFD_SMI_EVENT_NONE', - 1: 'KFD_SMI_EVENT_VMFAULT', - 2: 'KFD_SMI_EVENT_THERMAL_THROTTLE', - 3: 'KFD_SMI_EVENT_GPU_PRE_RESET', - 4: 'KFD_SMI_EVENT_GPU_POST_RESET', - 5: 'KFD_SMI_EVENT_MIGRATE_START', - 6: 'KFD_SMI_EVENT_MIGRATE_END', - 7: 'KFD_SMI_EVENT_PAGE_FAULT_START', - 8: 'KFD_SMI_EVENT_PAGE_FAULT_END', - 9: 'KFD_SMI_EVENT_QUEUE_EVICTION', - 10: 'KFD_SMI_EVENT_QUEUE_RESTORE', - 11: 'KFD_SMI_EVENT_UNMAP_FROM_GPU', - 64: 'KFD_SMI_EVENT_ALL_PROCESS', -} -KFD_SMI_EVENT_NONE = 0 -KFD_SMI_EVENT_VMFAULT = 1 -KFD_SMI_EVENT_THERMAL_THROTTLE = 2 -KFD_SMI_EVENT_GPU_PRE_RESET = 3 -KFD_SMI_EVENT_GPU_POST_RESET = 4 -KFD_SMI_EVENT_MIGRATE_START = 5 -KFD_SMI_EVENT_MIGRATE_END = 6 -KFD_SMI_EVENT_PAGE_FAULT_START = 7 -KFD_SMI_EVENT_PAGE_FAULT_END = 8 -KFD_SMI_EVENT_QUEUE_EVICTION = 9 -KFD_SMI_EVENT_QUEUE_RESTORE = 10 -KFD_SMI_EVENT_UNMAP_FROM_GPU = 11 -KFD_SMI_EVENT_ALL_PROCESS = 64 -kfd_smi_event = ctypes.c_uint32 # enum - -# values for enumeration 'KFD_MIGRATE_TRIGGERS' -KFD_MIGRATE_TRIGGERS__enumvalues = { - 0: 'KFD_MIGRATE_TRIGGER_PREFETCH', - 1: 'KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU', - 2: 'KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU', - 3: 'KFD_MIGRATE_TRIGGER_TTM_EVICTION', -} -KFD_MIGRATE_TRIGGER_PREFETCH = 0 -KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU = 1 -KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU = 2 -KFD_MIGRATE_TRIGGER_TTM_EVICTION = 3 -KFD_MIGRATE_TRIGGERS = ctypes.c_uint32 # enum - -# values for enumeration 'KFD_QUEUE_EVICTION_TRIGGERS' -KFD_QUEUE_EVICTION_TRIGGERS__enumvalues = { - 0: 'KFD_QUEUE_EVICTION_TRIGGER_SVM', - 1: 'KFD_QUEUE_EVICTION_TRIGGER_USERPTR', - 2: 'KFD_QUEUE_EVICTION_TRIGGER_TTM', - 3: 'KFD_QUEUE_EVICTION_TRIGGER_SUSPEND', - 4: 'KFD_QUEUE_EVICTION_CRIU_CHECKPOINT', - 5: 'KFD_QUEUE_EVICTION_CRIU_RESTORE', -} -KFD_QUEUE_EVICTION_TRIGGER_SVM = 0 -KFD_QUEUE_EVICTION_TRIGGER_USERPTR = 1 -KFD_QUEUE_EVICTION_TRIGGER_TTM = 2 -KFD_QUEUE_EVICTION_TRIGGER_SUSPEND = 3 -KFD_QUEUE_EVICTION_CRIU_CHECKPOINT = 4 -KFD_QUEUE_EVICTION_CRIU_RESTORE = 5 -KFD_QUEUE_EVICTION_TRIGGERS = ctypes.c_uint32 # enum - -# values for enumeration 'KFD_SVM_UNMAP_TRIGGERS' -KFD_SVM_UNMAP_TRIGGERS__enumvalues = { - 0: 'KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY', - 1: 'KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE', - 2: 'KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU', -} -KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY = 0 -KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE = 1 -KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU = 2 -KFD_SVM_UNMAP_TRIGGERS = ctypes.c_uint32 # enum -class struct_kfd_ioctl_smi_events_args(Structure): - pass - -struct_kfd_ioctl_smi_events_args._pack_ = 1 # source:False -struct_kfd_ioctl_smi_events_args._fields_ = [ - ('gpuid', ctypes.c_uint32), - ('anon_fd', ctypes.c_uint32), -] - -AMDKFD_IOC_SMI_EVENTS = AMDKFD_IOWR ( 0x1F , struct_kfd_ioctl_smi_events_args ) # macro (from list) - -# values for enumeration 'kfd_criu_op' -kfd_criu_op__enumvalues = { - 0: 'KFD_CRIU_OP_PROCESS_INFO', - 1: 'KFD_CRIU_OP_CHECKPOINT', - 2: 'KFD_CRIU_OP_UNPAUSE', - 3: 'KFD_CRIU_OP_RESTORE', - 4: 'KFD_CRIU_OP_RESUME', -} -KFD_CRIU_OP_PROCESS_INFO = 0 -KFD_CRIU_OP_CHECKPOINT = 1 -KFD_CRIU_OP_UNPAUSE = 2 -KFD_CRIU_OP_RESTORE = 3 -KFD_CRIU_OP_RESUME = 4 -kfd_criu_op = ctypes.c_uint32 # enum -class struct_kfd_ioctl_criu_args(Structure): - pass - -struct_kfd_ioctl_criu_args._pack_ = 1 # source:False -struct_kfd_ioctl_criu_args._fields_ = [ - ('devices', ctypes.c_uint64), - ('bos', ctypes.c_uint64), - ('priv_data', ctypes.c_uint64), - ('priv_data_size', ctypes.c_uint64), - ('num_devices', ctypes.c_uint32), - ('num_bos', ctypes.c_uint32), - ('num_objects', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -AMDKFD_IOC_CRIU_OP = AMDKFD_IOWR ( 0x22 , struct_kfd_ioctl_criu_args ) # macro (from list) -class struct_kfd_criu_device_bucket(Structure): - pass - -struct_kfd_criu_device_bucket._pack_ = 1 # source:False -struct_kfd_criu_device_bucket._fields_ = [ - ('user_gpu_id', ctypes.c_uint32), - ('actual_gpu_id', ctypes.c_uint32), - ('drm_fd', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - -class struct_kfd_criu_bo_bucket(Structure): - pass - -struct_kfd_criu_bo_bucket._pack_ = 1 # source:False -struct_kfd_criu_bo_bucket._fields_ = [ - ('addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('restored_offset', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('alloc_flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), - ('pad', ctypes.c_uint32), -] - - -# values for enumeration 'kfd_mmio_remap' -kfd_mmio_remap__enumvalues = { - 0: 'KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL', - 4: 'KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL', -} -KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0 -KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4 -kfd_mmio_remap = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_ioctl_svm_op' -kfd_ioctl_svm_op__enumvalues = { - 0: 'KFD_IOCTL_SVM_OP_SET_ATTR', - 1: 'KFD_IOCTL_SVM_OP_GET_ATTR', -} -KFD_IOCTL_SVM_OP_SET_ATTR = 0 -KFD_IOCTL_SVM_OP_GET_ATTR = 1 -kfd_ioctl_svm_op = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_ioctl_svm_location' -kfd_ioctl_svm_location__enumvalues = { - 0: 'KFD_IOCTL_SVM_LOCATION_SYSMEM', - 4294967295: 'KFD_IOCTL_SVM_LOCATION_UNDEFINED', -} -KFD_IOCTL_SVM_LOCATION_SYSMEM = 0 -KFD_IOCTL_SVM_LOCATION_UNDEFINED = 4294967295 -kfd_ioctl_svm_location = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_ioctl_svm_attr_type' -kfd_ioctl_svm_attr_type__enumvalues = { - 0: 'KFD_IOCTL_SVM_ATTR_PREFERRED_LOC', - 1: 'KFD_IOCTL_SVM_ATTR_PREFETCH_LOC', - 2: 'KFD_IOCTL_SVM_ATTR_ACCESS', - 3: 'KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE', - 4: 'KFD_IOCTL_SVM_ATTR_NO_ACCESS', - 5: 'KFD_IOCTL_SVM_ATTR_SET_FLAGS', - 6: 'KFD_IOCTL_SVM_ATTR_CLR_FLAGS', - 7: 'KFD_IOCTL_SVM_ATTR_GRANULARITY', -} -KFD_IOCTL_SVM_ATTR_PREFERRED_LOC = 0 -KFD_IOCTL_SVM_ATTR_PREFETCH_LOC = 1 -KFD_IOCTL_SVM_ATTR_ACCESS = 2 -KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE = 3 -KFD_IOCTL_SVM_ATTR_NO_ACCESS = 4 -KFD_IOCTL_SVM_ATTR_SET_FLAGS = 5 -KFD_IOCTL_SVM_ATTR_CLR_FLAGS = 6 -KFD_IOCTL_SVM_ATTR_GRANULARITY = 7 -kfd_ioctl_svm_attr_type = ctypes.c_uint32 # enum -class struct_kfd_ioctl_svm_attribute(Structure): - pass - -struct_kfd_ioctl_svm_attribute._pack_ = 1 # source:False -struct_kfd_ioctl_svm_attribute._fields_ = [ - ('type', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -class struct_kfd_ioctl_svm_args(Structure): - pass - -struct_kfd_ioctl_svm_args._pack_ = 1 # source:False -struct_kfd_ioctl_svm_args._fields_ = [ - ('start_addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('op', ctypes.c_uint32), - ('nattr', ctypes.c_uint32), - ('attrs', struct_kfd_ioctl_svm_attribute * 0), -] - -AMDKFD_IOC_SVM = AMDKFD_IOWR ( 0x20 , struct_kfd_ioctl_svm_args ) # macro (from list) -class struct_kfd_ioctl_set_xnack_mode_args(Structure): - pass - -struct_kfd_ioctl_set_xnack_mode_args._pack_ = 1 # source:False -struct_kfd_ioctl_set_xnack_mode_args._fields_ = [ - ('xnack_enabled', ctypes.c_int32), -] - -AMDKFD_IOC_SET_XNACK_MODE = AMDKFD_IOWR ( 0x21 , struct_kfd_ioctl_set_xnack_mode_args ) # macro (from list) - -# values for enumeration 'kfd_dbg_trap_override_mode' -kfd_dbg_trap_override_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_OVERRIDE_OR', - 1: 'KFD_DBG_TRAP_OVERRIDE_REPLACE', -} -KFD_DBG_TRAP_OVERRIDE_OR = 0 -KFD_DBG_TRAP_OVERRIDE_REPLACE = 1 -kfd_dbg_trap_override_mode = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_dbg_trap_mask' -kfd_dbg_trap_mask__enumvalues = { - 1: 'KFD_DBG_TRAP_MASK_FP_INVALID', - 2: 'KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL', - 4: 'KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO', - 8: 'KFD_DBG_TRAP_MASK_FP_OVERFLOW', - 16: 'KFD_DBG_TRAP_MASK_FP_UNDERFLOW', - 32: 'KFD_DBG_TRAP_MASK_FP_INEXACT', - 64: 'KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO', - 128: 'KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH', - 256: 'KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION', - 1073741824: 'KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START', - -2147483648: 'KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END', -} -KFD_DBG_TRAP_MASK_FP_INVALID = 1 -KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL = 2 -KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = 4 -KFD_DBG_TRAP_MASK_FP_OVERFLOW = 8 -KFD_DBG_TRAP_MASK_FP_UNDERFLOW = 16 -KFD_DBG_TRAP_MASK_FP_INEXACT = 32 -KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = 64 -KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = 128 -KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = 256 -KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START = 1073741824 -KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END = -2147483648 -kfd_dbg_trap_mask = ctypes.c_int32 # enum - -# values for enumeration 'kfd_dbg_trap_wave_launch_mode' -kfd_dbg_trap_wave_launch_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL', - 1: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT', - 3: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG', -} -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL = 0 -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT = 1 -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG = 3 -kfd_dbg_trap_wave_launch_mode = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_dbg_trap_address_watch_mode' -kfd_dbg_trap_address_watch_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ', - 1: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD', - 2: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC', - 3: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL', -} -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ = 0 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD = 1 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC = 2 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL = 3 -kfd_dbg_trap_address_watch_mode = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_dbg_trap_flags' -kfd_dbg_trap_flags__enumvalues = { - 1: 'KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP', -} -KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP = 1 -kfd_dbg_trap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_dbg_trap_exception_code' -kfd_dbg_trap_exception_code__enumvalues = { - 0: 'EC_NONE', - 1: 'EC_QUEUE_WAVE_ABORT', - 2: 'EC_QUEUE_WAVE_TRAP', - 3: 'EC_QUEUE_WAVE_MATH_ERROR', - 4: 'EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION', - 5: 'EC_QUEUE_WAVE_MEMORY_VIOLATION', - 6: 'EC_QUEUE_WAVE_APERTURE_VIOLATION', - 16: 'EC_QUEUE_PACKET_DISPATCH_DIM_INVALID', - 17: 'EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID', - 18: 'EC_QUEUE_PACKET_DISPATCH_CODE_INVALID', - 19: 'EC_QUEUE_PACKET_RESERVED', - 20: 'EC_QUEUE_PACKET_UNSUPPORTED', - 21: 'EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID', - 22: 'EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID', - 23: 'EC_QUEUE_PACKET_VENDOR_UNSUPPORTED', - 30: 'EC_QUEUE_PREEMPTION_ERROR', - 31: 'EC_QUEUE_NEW', - 32: 'EC_DEVICE_QUEUE_DELETE', - 33: 'EC_DEVICE_MEMORY_VIOLATION', - 34: 'EC_DEVICE_RAS_ERROR', - 35: 'EC_DEVICE_FATAL_HALT', - 36: 'EC_DEVICE_NEW', - 48: 'EC_PROCESS_RUNTIME', - 49: 'EC_PROCESS_DEVICE_REMOVE', - 50: 'EC_MAX', -} -EC_NONE = 0 -EC_QUEUE_WAVE_ABORT = 1 -EC_QUEUE_WAVE_TRAP = 2 -EC_QUEUE_WAVE_MATH_ERROR = 3 -EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION = 4 -EC_QUEUE_WAVE_MEMORY_VIOLATION = 5 -EC_QUEUE_WAVE_APERTURE_VIOLATION = 6 -EC_QUEUE_PACKET_DISPATCH_DIM_INVALID = 16 -EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID = 17 -EC_QUEUE_PACKET_DISPATCH_CODE_INVALID = 18 -EC_QUEUE_PACKET_RESERVED = 19 -EC_QUEUE_PACKET_UNSUPPORTED = 20 -EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID = 21 -EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID = 22 -EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = 23 -EC_QUEUE_PREEMPTION_ERROR = 30 -EC_QUEUE_NEW = 31 -EC_DEVICE_QUEUE_DELETE = 32 -EC_DEVICE_MEMORY_VIOLATION = 33 -EC_DEVICE_RAS_ERROR = 34 -EC_DEVICE_FATAL_HALT = 35 -EC_DEVICE_NEW = 36 -EC_PROCESS_RUNTIME = 48 -EC_PROCESS_DEVICE_REMOVE = 49 -EC_MAX = 50 -kfd_dbg_trap_exception_code = ctypes.c_uint32 # enum -KFD_EC_MASK_QUEUE = (KFD_EC_MASK(EC_QUEUE_WAVE_ABORT)|KFD_EC_MASK(EC_QUEUE_WAVE_TRAP)|KFD_EC_MASK(EC_QUEUE_WAVE_MATH_ERROR)|KFD_EC_MASK(EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION)|KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION)|KFD_EC_MASK(EC_QUEUE_WAVE_APERTURE_VIOLATION)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_RESERVED)|KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PREEMPTION_ERROR)|KFD_EC_MASK(EC_QUEUE_NEW)) # macro -KFD_EC_MASK_DEVICE = (KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE)|KFD_EC_MASK(EC_DEVICE_RAS_ERROR)|KFD_EC_MASK(EC_DEVICE_FATAL_HALT)|KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION)|KFD_EC_MASK(EC_DEVICE_NEW)) # macro -KFD_EC_MASK_PROCESS = (KFD_EC_MASK(EC_PROCESS_RUNTIME)|KFD_EC_MASK(EC_PROCESS_DEVICE_REMOVE)) # macro -KFD_EC_MASK_PACKET = (KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_RESERVED)|KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED)) # macro -def KFD_DBG_EC_IS_VALID(ecode): # macro - return (ecode>EC_NONE and ecode= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - -import fcntl, functools - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, __payload=None, **kwargs): - ret = __fd.ioctl((__idir<<30) | (ctypes.sizeof(made := (__payload or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - - - -_UAPI_MSM_KGSL_H = True # macro -size_t = True # macro -uint64_t = True # macro -KGSL_VERSION_MAJOR = 3 # macro -KGSL_VERSION_MINOR = 14 # macro -KGSL_CONTEXT_SAVE_GMEM = 0x00000001 # macro -KGSL_CONTEXT_NO_GMEM_ALLOC = 0x00000002 # macro -KGSL_CONTEXT_SUBMIT_IB_LIST = 0x00000004 # macro -KGSL_CONTEXT_CTX_SWITCH = 0x00000008 # macro -KGSL_CONTEXT_PREAMBLE = 0x00000010 # macro -KGSL_CONTEXT_TRASH_STATE = 0x00000020 # macro -KGSL_CONTEXT_PER_CONTEXT_TS = 0x00000040 # macro -KGSL_CONTEXT_USER_GENERATED_TS = 0x00000080 # macro -KGSL_CONTEXT_END_OF_FRAME = 0x00000100 # macro -KGSL_CONTEXT_NO_FAULT_TOLERANCE = 0x00000200 # macro -KGSL_CONTEXT_SYNC = 0x00000400 # macro -KGSL_CONTEXT_PWR_CONSTRAINT = 0x00000800 # macro -KGSL_CONTEXT_PRIORITY_MASK = 0x0000F000 # macro -KGSL_CONTEXT_PRIORITY_SHIFT = 12 # macro -KGSL_CONTEXT_PRIORITY_UNDEF = 0 # macro -KGSL_CONTEXT_IFH_NOP = 0x00010000 # macro -KGSL_CONTEXT_SECURE = 0x00020000 # macro -KGSL_CONTEXT_PREEMPT_STYLE_MASK = 0x0E000000 # macro -KGSL_CONTEXT_PREEMPT_STYLE_SHIFT = 25 # macro -KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT = 0x0 # macro -KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER = 0x1 # macro -KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN = 0x2 # macro -KGSL_CONTEXT_TYPE_MASK = 0x01F00000 # macro -KGSL_CONTEXT_TYPE_SHIFT = 20 # macro -KGSL_CONTEXT_TYPE_ANY = 0 # macro -KGSL_CONTEXT_TYPE_GL = 1 # macro -KGSL_CONTEXT_TYPE_CL = 2 # macro -KGSL_CONTEXT_TYPE_C2D = 3 # macro -KGSL_CONTEXT_TYPE_RS = 4 # macro -KGSL_CONTEXT_TYPE_UNKNOWN = 0x1E # macro -KGSL_CONTEXT_INVALID = 0xffffffff # macro -KGSL_CMDBATCH_MEMLIST = 0x00000001 # macro -KGSL_CMDBATCH_MARKER = 0x00000002 # macro -KGSL_CMDBATCH_SUBMIT_IB_LIST = 0x00000004 # macro -KGSL_CMDBATCH_CTX_SWITCH = 0x00000008 # macro -KGSL_CMDBATCH_PROFILING = 0x00000010 # macro -KGSL_CMDBATCH_PROFILING_KTIME = 0x00000020 # macro -KGSL_CMDBATCH_END_OF_FRAME = 0x00000100 # macro -KGSL_CMDBATCH_SYNC = 0x00000400 # macro -KGSL_CMDBATCH_PWR_CONSTRAINT = 0x00000800 # macro -KGSL_CMDLIST_IB = 0x00000001 # macro -KGSL_CMDLIST_CTXTSWITCH_PREAMBLE = 0x00000002 # macro -KGSL_CMDLIST_IB_PREAMBLE = 0x00000004 # macro -KGSL_OBJLIST_MEMOBJ = 0x00000008 # macro -KGSL_OBJLIST_PROFILE = 0x00000010 # macro -KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP = 0 # macro -KGSL_CMD_SYNCPOINT_TYPE_FENCE = 1 # macro -KGSL_MEMFLAGS_SECURE = 0x00000008 # macro -KGSL_MEMFLAGS_GPUREADONLY = 0x01000000 # macro -KGSL_MEMFLAGS_GPUWRITEONLY = 0x02000000 # macro -KGSL_MEMFLAGS_FORCE_32BIT = 0x100000000 # macro -KGSL_CACHEMODE_MASK = 0x0C000000 # macro -KGSL_CACHEMODE_SHIFT = 26 # macro -KGSL_CACHEMODE_WRITECOMBINE = 0 # macro -KGSL_CACHEMODE_UNCACHED = 1 # macro -KGSL_CACHEMODE_WRITETHROUGH = 2 # macro -KGSL_CACHEMODE_WRITEBACK = 3 # macro -KGSL_MEMFLAGS_USE_CPU_MAP = 0x10000000 # macro -KGSL_MEMTYPE_MASK = 0x0000FF00 # macro -KGSL_MEMTYPE_SHIFT = 8 # macro -KGSL_MEMTYPE_OBJECTANY = 0 # macro -KGSL_MEMTYPE_FRAMEBUFFER = 1 # macro -KGSL_MEMTYPE_RENDERBUFFER = 2 # macro -KGSL_MEMTYPE_ARRAYBUFFER = 3 # macro -KGSL_MEMTYPE_ELEMENTARRAYBUFFER = 4 # macro -KGSL_MEMTYPE_VERTEXARRAYBUFFER = 5 # macro -KGSL_MEMTYPE_TEXTURE = 6 # macro -KGSL_MEMTYPE_SURFACE = 7 # macro -KGSL_MEMTYPE_EGL_SURFACE = 8 # macro -KGSL_MEMTYPE_GL = 9 # macro -KGSL_MEMTYPE_CL = 10 # macro -KGSL_MEMTYPE_CL_BUFFER_MAP = 11 # macro -KGSL_MEMTYPE_CL_BUFFER_NOMAP = 12 # macro -KGSL_MEMTYPE_CL_IMAGE_MAP = 13 # macro -KGSL_MEMTYPE_CL_IMAGE_NOMAP = 14 # macro -KGSL_MEMTYPE_CL_KERNEL_STACK = 15 # macro -KGSL_MEMTYPE_COMMAND = 16 # macro -KGSL_MEMTYPE_2D = 17 # macro -KGSL_MEMTYPE_EGL_IMAGE = 18 # macro -KGSL_MEMTYPE_EGL_SHADOW = 19 # macro -KGSL_MEMTYPE_MULTISAMPLE = 20 # macro -KGSL_MEMTYPE_KERNEL = 255 # macro -KGSL_MEMALIGN_MASK = 0x00FF0000 # macro -KGSL_MEMALIGN_SHIFT = 16 # macro -KGSL_MEMFLAGS_USERMEM_MASK = 0x000000e0 # macro -KGSL_MEMFLAGS_USERMEM_SHIFT = 5 # macro -def KGSL_USERMEM_FLAG(x): # macro - return (((x)+1)<<5) -KGSL_MEMFLAGS_NOT_USERMEM = 0 # macro -KGSL_FLAGS_NORMALMODE = 0x00000000 # macro -KGSL_FLAGS_SAFEMODE = 0x00000001 # macro -KGSL_FLAGS_INITIALIZED0 = 0x00000002 # macro -KGSL_FLAGS_INITIALIZED = 0x00000004 # macro -KGSL_FLAGS_STARTED = 0x00000008 # macro -KGSL_FLAGS_ACTIVE = 0x00000010 # macro -KGSL_FLAGS_RESERVED0 = 0x00000020 # macro -KGSL_FLAGS_RESERVED1 = 0x00000040 # macro -KGSL_FLAGS_RESERVED2 = 0x00000080 # macro -KGSL_FLAGS_SOFT_RESET = 0x00000100 # macro -KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS = 0x00000200 # macro -KGSL_SYNCOBJ_SERVER_TIMEOUT = 2000 # macro -def KGSL_CONVERT_TO_MBPS(val): # macro - return (val*1000*1000) -KGSL_PROP_DEVICE_INFO = 0x1 # macro -KGSL_PROP_DEVICE_SHADOW = 0x2 # macro -KGSL_PROP_DEVICE_POWER = 0x3 # macro -KGSL_PROP_SHMEM = 0x4 # macro -KGSL_PROP_SHMEM_APERTURES = 0x5 # macro -KGSL_PROP_MMU_ENABLE = 0x6 # macro -KGSL_PROP_INTERRUPT_WAITS = 0x7 # macro -KGSL_PROP_VERSION = 0x8 # macro -KGSL_PROP_GPU_RESET_STAT = 0x9 # macro -KGSL_PROP_PWRCTRL = 0xE # macro -KGSL_PROP_PWR_CONSTRAINT = 0x12 # macro -KGSL_PROP_UCHE_GMEM_VADDR = 0x13 # macro -KGSL_PROP_SP_GENERIC_MEM = 0x14 # macro -KGSL_PROP_UCODE_VERSION = 0x15 # macro -KGSL_PROP_GPMU_VERSION = 0x16 # macro -KGSL_PROP_DEVICE_BITNESS = 0x18 # macro -KGSL_PERFCOUNTER_GROUP_CP = 0x0 # macro -KGSL_PERFCOUNTER_GROUP_RBBM = 0x1 # macro -KGSL_PERFCOUNTER_GROUP_PC = 0x2 # macro -KGSL_PERFCOUNTER_GROUP_VFD = 0x3 # macro -KGSL_PERFCOUNTER_GROUP_HLSQ = 0x4 # macro -KGSL_PERFCOUNTER_GROUP_VPC = 0x5 # macro -KGSL_PERFCOUNTER_GROUP_TSE = 0x6 # macro -KGSL_PERFCOUNTER_GROUP_RAS = 0x7 # macro -KGSL_PERFCOUNTER_GROUP_UCHE = 0x8 # macro -KGSL_PERFCOUNTER_GROUP_TP = 0x9 # macro -KGSL_PERFCOUNTER_GROUP_SP = 0xA # macro -KGSL_PERFCOUNTER_GROUP_RB = 0xB # macro -KGSL_PERFCOUNTER_GROUP_PWR = 0xC # macro -KGSL_PERFCOUNTER_GROUP_VBIF = 0xD # macro -KGSL_PERFCOUNTER_GROUP_VBIF_PWR = 0xE # macro -KGSL_PERFCOUNTER_GROUP_MH = 0xF # macro -KGSL_PERFCOUNTER_GROUP_PA_SU = 0x10 # macro -KGSL_PERFCOUNTER_GROUP_SQ = 0x11 # macro -KGSL_PERFCOUNTER_GROUP_SX = 0x12 # macro -KGSL_PERFCOUNTER_GROUP_TCF = 0x13 # macro -KGSL_PERFCOUNTER_GROUP_TCM = 0x14 # macro -KGSL_PERFCOUNTER_GROUP_TCR = 0x15 # macro -KGSL_PERFCOUNTER_GROUP_L2 = 0x16 # macro -KGSL_PERFCOUNTER_GROUP_VSC = 0x17 # macro -KGSL_PERFCOUNTER_GROUP_CCU = 0x18 # macro -KGSL_PERFCOUNTER_GROUP_LRZ = 0x19 # macro -KGSL_PERFCOUNTER_GROUP_CMP = 0x1A # macro -KGSL_PERFCOUNTER_GROUP_ALWAYSON = 0x1B # macro -KGSL_PERFCOUNTER_GROUP_SP_PWR = 0x1C # macro -KGSL_PERFCOUNTER_GROUP_TP_PWR = 0x1D # macro -KGSL_PERFCOUNTER_GROUP_RB_PWR = 0x1E # macro -KGSL_PERFCOUNTER_GROUP_CCU_PWR = 0x1F # macro -KGSL_PERFCOUNTER_GROUP_UCHE_PWR = 0x20 # macro -KGSL_PERFCOUNTER_GROUP_CP_PWR = 0x21 # macro -KGSL_PERFCOUNTER_GROUP_GPMU_PWR = 0x22 # macro -KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR = 0x23 # macro -KGSL_PERFCOUNTER_GROUP_MAX = 0x24 # macro -KGSL_PERFCOUNTER_NOT_USED = 0xFFFFFFFF # macro -KGSL_PERFCOUNTER_BROKEN = 0xFFFFFFFE # macro -KGSL_IOC_TYPE = 0x09 # macro -KGSL_TIMESTAMP_EVENT_GENLOCK = 1 # macro -KGSL_TIMESTAMP_EVENT_FENCE = 2 # macro -KGSL_GPUMEM_CACHE_CLEAN = (1<<0) # macro -KGSL_GPUMEM_CACHE_TO_GPU = (1<<0) # macro -KGSL_GPUMEM_CACHE_INV = (1<<1) # macro -KGSL_GPUMEM_CACHE_FROM_GPU = (1<<1) # macro -KGSL_GPUMEM_CACHE_FLUSH = ((1<<0)|(1<<1)) # macro -KGSL_GPUMEM_CACHE_RANGE = (1<<31) # macro -KGSL_IBDESC_MEMLIST = 0x1 # macro -KGSL_IBDESC_PROFILING_BUFFER = 0x2 # macro -KGSL_CONSTRAINT_NONE = 0 # macro -KGSL_CONSTRAINT_PWRLEVEL = 1 # macro -KGSL_CONSTRAINT_PWR_MIN = 0 # macro -KGSL_CONSTRAINT_PWR_MAX = 1 # macro -KGSL_GPUOBJ_ALLOC_METADATA_MAX = 64 # macro -KGSL_GPUOBJ_FREE_ON_EVENT = 1 # macro -KGSL_GPU_EVENT_TIMESTAMP = 1 # macro -KGSL_GPU_EVENT_FENCE = 2 # macro -KGSL_GPUOBJ_SET_INFO_METADATA = (1<<0) # macro -KGSL_GPUOBJ_SET_INFO_TYPE = (1<<1) # macro - -# values for enumeration 'kgsl_user_mem_type' -kgsl_user_mem_type__enumvalues = { - 0: 'KGSL_USER_MEM_TYPE_PMEM', - 1: 'KGSL_USER_MEM_TYPE_ASHMEM', - 2: 'KGSL_USER_MEM_TYPE_ADDR', - 3: 'KGSL_USER_MEM_TYPE_ION', - 3: 'KGSL_USER_MEM_TYPE_DMABUF', - 7: 'KGSL_USER_MEM_TYPE_MAX', -} -KGSL_USER_MEM_TYPE_PMEM = 0 -KGSL_USER_MEM_TYPE_ASHMEM = 1 -KGSL_USER_MEM_TYPE_ADDR = 2 -KGSL_USER_MEM_TYPE_ION = 3 -KGSL_USER_MEM_TYPE_DMABUF = 3 -KGSL_USER_MEM_TYPE_MAX = 7 -kgsl_user_mem_type = ctypes.c_uint32 # enum -KGSL_MEMFLAGS_USERMEM_PMEM = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_PMEM ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ASHMEM = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ASHMEM ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ADDR = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ADDR ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ION = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ION ) # macro (from list) - -# values for enumeration 'kgsl_ctx_reset_stat' -kgsl_ctx_reset_stat__enumvalues = { - 0: 'KGSL_CTX_STAT_NO_ERROR', - 1: 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 2: 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 3: 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', -} -KGSL_CTX_STAT_NO_ERROR = 0 -KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 1 -KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 2 -KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 3 -kgsl_ctx_reset_stat = ctypes.c_uint32 # enum - -# values for enumeration 'kgsl_deviceid' -kgsl_deviceid__enumvalues = { - 0: 'KGSL_DEVICE_3D0', - 1: 'KGSL_DEVICE_MAX', -} -KGSL_DEVICE_3D0 = 0 -KGSL_DEVICE_MAX = 1 -kgsl_deviceid = ctypes.c_uint32 # enum -class struct_kgsl_devinfo(Structure): - pass - -struct_kgsl_devinfo._pack_ = 1 # source:False -struct_kgsl_devinfo._fields_ = [ - ('device_id', ctypes.c_uint32), - ('chip_id', ctypes.c_uint32), - ('mmu_enabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gmem_gpubaseaddr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('gmem_sizebytes', ctypes.c_uint64), -] - -class struct_kgsl_devmemstore(Structure): - pass - -struct_kgsl_devmemstore._pack_ = 1 # source:False -struct_kgsl_devmemstore._fields_ = [ - ('soptimestamp', ctypes.c_uint32), - ('sbz', ctypes.c_uint32), - ('eoptimestamp', ctypes.c_uint32), - ('sbz2', ctypes.c_uint32), - ('preempted', ctypes.c_uint32), - ('sbz3', ctypes.c_uint32), - ('ref_wait_ts', ctypes.c_uint32), - ('sbz4', ctypes.c_uint32), - ('current_context', ctypes.c_uint32), - ('sbz5', ctypes.c_uint32), -] - -# def KGSL_MEMSTORE_OFFSET(ctxt_id, field): # macro -# return ((ctxt_id)*ctypes.sizeof(struct_kgsl_devmemstore)+offsetof(struct_kgsl_devmemstore,field)) - -# values for enumeration 'kgsl_timestamp_type' -kgsl_timestamp_type__enumvalues = { - 1: 'KGSL_TIMESTAMP_CONSUMED', - 2: 'KGSL_TIMESTAMP_RETIRED', - 3: 'KGSL_TIMESTAMP_QUEUED', -} -KGSL_TIMESTAMP_CONSUMED = 1 -KGSL_TIMESTAMP_RETIRED = 2 -KGSL_TIMESTAMP_QUEUED = 3 -kgsl_timestamp_type = ctypes.c_uint32 # enum -class struct_kgsl_shadowprop(Structure): - pass - -struct_kgsl_shadowprop._pack_ = 1 # source:False -struct_kgsl_shadowprop._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_version(Structure): - pass - -struct_kgsl_version._pack_ = 1 # source:False -struct_kgsl_version._fields_ = [ - ('drv_major', ctypes.c_uint32), - ('drv_minor', ctypes.c_uint32), - ('dev_major', ctypes.c_uint32), - ('dev_minor', ctypes.c_uint32), -] - -class struct_kgsl_sp_generic_mem(Structure): - pass - -struct_kgsl_sp_generic_mem._pack_ = 1 # source:False -struct_kgsl_sp_generic_mem._fields_ = [ - ('local', ctypes.c_uint64), - ('pvt', ctypes.c_uint64), -] - -class struct_kgsl_ucode_version(Structure): - pass - -struct_kgsl_ucode_version._pack_ = 1 # source:False -struct_kgsl_ucode_version._fields_ = [ - ('pfp', ctypes.c_uint32), - ('pm4', ctypes.c_uint32), -] - -class struct_kgsl_gpmu_version(Structure): - pass - -struct_kgsl_gpmu_version._pack_ = 1 # source:False -struct_kgsl_gpmu_version._fields_ = [ - ('major', ctypes.c_uint32), - ('minor', ctypes.c_uint32), - ('features', ctypes.c_uint32), -] - -class struct_kgsl_ibdesc(Structure): - pass - -struct_kgsl_ibdesc._pack_ = 1 # source:False -struct_kgsl_ibdesc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64), - ('sizedwords', ctypes.c_uint64), - ('ctrl', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_cmdbatch_profiling_buffer(Structure): - pass - -struct_kgsl_cmdbatch_profiling_buffer._pack_ = 1 # source:False -struct_kgsl_cmdbatch_profiling_buffer._fields_ = [ - ('wall_clock_s', ctypes.c_uint64), - ('wall_clock_ns', ctypes.c_uint64), - ('gpu_ticks_queued', ctypes.c_uint64), - ('gpu_ticks_submitted', ctypes.c_uint64), - ('gpu_ticks_retired', ctypes.c_uint64), -] - -class struct_kgsl_device_getproperty(Structure): - pass - -struct_kgsl_device_getproperty._pack_ = 1 # source:False -struct_kgsl_device_getproperty._fields_ = [ - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('value', ctypes.POINTER(None)), - ('sizebytes', ctypes.c_uint64), -] - -IOCTL_KGSL_DEVICE_GETPROPERTY = _IOWR ( 0x09 , 0x2 , struct_kgsl_device_getproperty ) # macro (from list) -IOCTL_KGSL_SETPROPERTY = _IOW ( 0x09 , 0x32 , struct_kgsl_device_getproperty ) # macro (from list) -class struct_kgsl_device_waittimestamp(Structure): - pass - -struct_kgsl_device_waittimestamp._pack_ = 1 # source:False -struct_kgsl_device_waittimestamp._fields_ = [ - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -IOCTL_KGSL_DEVICE_WAITTIMESTAMP = _IOW ( 0x09 , 0x6 , struct_kgsl_device_waittimestamp ) # macro (from list) -class struct_kgsl_device_waittimestamp_ctxtid(Structure): - pass - -struct_kgsl_device_waittimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_device_waittimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID = _IOW ( 0x09 , 0x7 , struct_kgsl_device_waittimestamp_ctxtid ) # macro (from list) -class struct_kgsl_ringbuffer_issueibcmds(Structure): - pass - -struct_kgsl_ringbuffer_issueibcmds._pack_ = 1 # source:False -struct_kgsl_ringbuffer_issueibcmds._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ibdesc_addr', ctypes.c_uint64), - ('numibs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS = _IOWR ( 0x09 , 0x10 , struct_kgsl_ringbuffer_issueibcmds ) # macro (from list) -class struct_kgsl_cmdstream_readtimestamp(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp._pack_ = 1 # source:False -struct_kgsl_cmdstream_readtimestamp._fields_ = [ - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD = _IOR ( 0x09 , 0x11 , struct_kgsl_cmdstream_readtimestamp ) # macro (from list) -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP = _IOWR ( 0x09 , 0x11 , struct_kgsl_cmdstream_readtimestamp ) # macro (from list) -class struct_kgsl_cmdstream_freememontimestamp(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp._pack_ = 1 # source:False -struct_kgsl_cmdstream_freememontimestamp._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP = _IOW ( 0x09 , 0x12 , struct_kgsl_cmdstream_freememontimestamp ) # macro (from list) -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD = _IOR ( 0x09 , 0x12 , struct_kgsl_cmdstream_freememontimestamp ) # macro (from list) -class struct_kgsl_drawctxt_create(Structure): - pass - -struct_kgsl_drawctxt_create._pack_ = 1 # source:False -struct_kgsl_drawctxt_create._fields_ = [ - ('flags', ctypes.c_uint32), - ('drawctxt_id', ctypes.c_uint32), -] - -IOCTL_KGSL_DRAWCTXT_CREATE = _IOWR ( 0x09 , 0x13 , struct_kgsl_drawctxt_create ) # macro (from list) -class struct_kgsl_drawctxt_destroy(Structure): - pass - -struct_kgsl_drawctxt_destroy._pack_ = 1 # source:False -struct_kgsl_drawctxt_destroy._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), -] - -IOCTL_KGSL_DRAWCTXT_DESTROY = _IOW ( 0x09 , 0x14 , struct_kgsl_drawctxt_destroy ) # macro (from list) -class struct_kgsl_map_user_mem(Structure): - pass - -struct_kgsl_map_user_mem._pack_ = 1 # source:False -struct_kgsl_map_user_mem._fields_ = [ - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('hostptr', ctypes.c_uint64), - ('memtype', kgsl_user_mem_type), - ('flags', ctypes.c_uint32), -] - -IOCTL_KGSL_MAP_USER_MEM = _IOWR ( 0x09 , 0x15 , struct_kgsl_map_user_mem ) # macro (from list) -class struct_kgsl_cmdstream_readtimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_cmdstream_readtimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID = _IOWR ( 0x09 , 0x16 , struct_kgsl_cmdstream_readtimestamp_ctxtid ) # macro (from list) -class struct_kgsl_cmdstream_freememontimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp_ctxtid._pack_ = 1 # source:False -struct_kgsl_cmdstream_freememontimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID = _IOW ( 0x09 , 0x17 , struct_kgsl_cmdstream_freememontimestamp_ctxtid ) # macro (from list) -class struct_kgsl_sharedmem_from_pmem(Structure): - pass - -struct_kgsl_sharedmem_from_pmem._pack_ = 1 # source:False -struct_kgsl_sharedmem_from_pmem._fields_ = [ - ('pmem_fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint32), - ('offset', ctypes.c_uint32), -] - -IOCTL_KGSL_SHAREDMEM_FROM_PMEM = _IOWR ( 0x09 , 0x20 , struct_kgsl_sharedmem_from_pmem ) # macro (from list) -class struct_kgsl_sharedmem_free(Structure): - pass - -struct_kgsl_sharedmem_free._pack_ = 1 # source:False -struct_kgsl_sharedmem_free._fields_ = [ - ('gpuaddr', ctypes.c_uint64), -] - -IOCTL_KGSL_SHAREDMEM_FREE = _IOW ( 0x09 , 0x21 , struct_kgsl_sharedmem_free ) # macro (from list) -IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE = _IOW ( 0x09 , 0x24 , struct_kgsl_sharedmem_free ) # macro (from list) -class struct_kgsl_cff_user_event(Structure): - pass - -struct_kgsl_cff_user_event._pack_ = 1 # source:False -struct_kgsl_cff_user_event._fields_ = [ - ('cff_opcode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('op1', ctypes.c_uint32), - ('op2', ctypes.c_uint32), - ('op3', ctypes.c_uint32), - ('op4', ctypes.c_uint32), - ('op5', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -IOCTL_KGSL_CFF_USER_EVENT = _IOW ( 0x09 , 0x31 , struct_kgsl_cff_user_event ) # macro (from list) -class struct_kgsl_gmem_desc(Structure): - pass - -struct_kgsl_gmem_desc._pack_ = 1 # source:False -struct_kgsl_gmem_desc._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), -] - -class struct_kgsl_buffer_desc(Structure): - pass - -struct_kgsl_buffer_desc._pack_ = 1 # source:False -struct_kgsl_buffer_desc._fields_ = [ - ('hostptr', ctypes.POINTER(None)), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_int32), - ('format', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), - ('enabled', ctypes.c_uint32), -] - -class struct_kgsl_bind_gmem_shadow(Structure): - pass - -struct_kgsl_bind_gmem_shadow._pack_ = 1 # source:False -struct_kgsl_bind_gmem_shadow._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('gmem_desc', struct_kgsl_gmem_desc), - ('shadow_x', ctypes.c_uint32), - ('shadow_y', ctypes.c_uint32), - ('shadow_buffer', struct_kgsl_buffer_desc), - ('buffer_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW = _IOW ( 0x09 , 0x22 , struct_kgsl_bind_gmem_shadow ) # macro (from list) -class struct_kgsl_sharedmem_from_vmalloc(Structure): - pass - -struct_kgsl_sharedmem_from_vmalloc._pack_ = 1 # source:False -struct_kgsl_sharedmem_from_vmalloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('hostptr', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC = _IOWR ( 0x09 , 0x23 , struct_kgsl_sharedmem_from_vmalloc ) # macro (from list) -class struct_kgsl_drawctxt_set_bin_base_offset(Structure): - pass - -struct_kgsl_drawctxt_set_bin_base_offset._pack_ = 1 # source:False -struct_kgsl_drawctxt_set_bin_base_offset._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('offset', ctypes.c_uint32), -] - -IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET = _IOW ( 0x09 , 0x25 , struct_kgsl_drawctxt_set_bin_base_offset ) # macro (from list) - -# values for enumeration 'kgsl_cmdwindow_type' -kgsl_cmdwindow_type__enumvalues = { - 0: 'KGSL_CMDWINDOW_MIN', - 0: 'KGSL_CMDWINDOW_2D', - 1: 'KGSL_CMDWINDOW_3D', - 2: 'KGSL_CMDWINDOW_MMU', - 255: 'KGSL_CMDWINDOW_ARBITER', - 255: 'KGSL_CMDWINDOW_MAX', -} -KGSL_CMDWINDOW_MIN = 0 -KGSL_CMDWINDOW_2D = 0 -KGSL_CMDWINDOW_3D = 1 -KGSL_CMDWINDOW_MMU = 2 -KGSL_CMDWINDOW_ARBITER = 255 -KGSL_CMDWINDOW_MAX = 255 -kgsl_cmdwindow_type = ctypes.c_uint32 # enum -class struct_kgsl_cmdwindow_write(Structure): - pass - -struct_kgsl_cmdwindow_write._pack_ = 1 # source:False -struct_kgsl_cmdwindow_write._fields_ = [ - ('target', kgsl_cmdwindow_type), - ('addr', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -IOCTL_KGSL_CMDWINDOW_WRITE = _IOW ( 0x09 , 0x2e , struct_kgsl_cmdwindow_write ) # macro (from list) -class struct_kgsl_gpumem_alloc(Structure): - pass - -struct_kgsl_gpumem_alloc._pack_ = 1 # source:False -struct_kgsl_gpumem_alloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_GPUMEM_ALLOC = _IOWR ( 0x09 , 0x2f , struct_kgsl_gpumem_alloc ) # macro (from list) -class struct_kgsl_cff_syncmem(Structure): - pass - -struct_kgsl_cff_syncmem._pack_ = 1 # source:False -struct_kgsl_cff_syncmem._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('__pad', ctypes.c_uint32 * 2), -] - -IOCTL_KGSL_CFF_SYNCMEM = _IOW ( 0x09 , 0x30 , struct_kgsl_cff_syncmem ) # macro (from list) -class struct_kgsl_timestamp_event(Structure): - pass - -struct_kgsl_timestamp_event._pack_ = 1 # source:False -struct_kgsl_timestamp_event._fields_ = [ - ('type', ctypes.c_int32), - ('timestamp', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('len', ctypes.c_uint64), -] - -IOCTL_KGSL_TIMESTAMP_EVENT_OLD = _IOW ( 0x09 , 0x31 , struct_kgsl_timestamp_event ) # macro (from list) -IOCTL_KGSL_TIMESTAMP_EVENT = _IOWR ( 0x09 , 0x33 , struct_kgsl_timestamp_event ) # macro (from list) -class struct_kgsl_timestamp_event_genlock(Structure): - pass - -struct_kgsl_timestamp_event_genlock._pack_ = 1 # source:False -struct_kgsl_timestamp_event_genlock._fields_ = [ - ('handle', ctypes.c_int32), -] - -class struct_kgsl_timestamp_event_fence(Structure): - pass - -struct_kgsl_timestamp_event_fence._pack_ = 1 # source:False -struct_kgsl_timestamp_event_fence._fields_ = [ - ('fence_fd', ctypes.c_int32), -] - -class struct_kgsl_gpumem_alloc_id(Structure): - pass - -struct_kgsl_gpumem_alloc_id._pack_ = 1 # source:False -struct_kgsl_gpumem_alloc_id._fields_ = [ - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 2), -] - -IOCTL_KGSL_GPUMEM_ALLOC_ID = _IOWR ( 0x09 , 0x34 , struct_kgsl_gpumem_alloc_id ) # macro (from list) -class struct_kgsl_gpumem_free_id(Structure): - pass - -struct_kgsl_gpumem_free_id._pack_ = 1 # source:False -struct_kgsl_gpumem_free_id._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), -] - -IOCTL_KGSL_GPUMEM_FREE_ID = _IOWR ( 0x09 , 0x35 , struct_kgsl_gpumem_free_id ) # macro (from list) -class struct_kgsl_gpumem_get_info(Structure): - pass - -struct_kgsl_gpumem_get_info._pack_ = 1 # source:False -struct_kgsl_gpumem_get_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('useraddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 4), -] - -IOCTL_KGSL_GPUMEM_GET_INFO = _IOWR ( 0x09 , 0x36 , struct_kgsl_gpumem_get_info ) # macro (from list) -class struct_kgsl_gpumem_sync_cache(Structure): - pass - -struct_kgsl_gpumem_sync_cache._pack_ = 1 # source:False -struct_kgsl_gpumem_sync_cache._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), -] - -IOCTL_KGSL_GPUMEM_SYNC_CACHE = _IOW ( 0x09 , 0x37 , struct_kgsl_gpumem_sync_cache ) # macro (from list) -class struct_kgsl_perfcounter_get(Structure): - pass - -struct_kgsl_perfcounter_get._pack_ = 1 # source:False -struct_kgsl_perfcounter_get._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('offset_hi', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), -] - -IOCTL_KGSL_PERFCOUNTER_GET = _IOWR ( 0x09 , 0x38 , struct_kgsl_perfcounter_get ) # macro (from list) -class struct_kgsl_perfcounter_put(Structure): - pass - -struct_kgsl_perfcounter_put._pack_ = 1 # source:False -struct_kgsl_perfcounter_put._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -IOCTL_KGSL_PERFCOUNTER_PUT = _IOW ( 0x09 , 0x39 , struct_kgsl_perfcounter_put ) # macro (from list) -class struct_kgsl_perfcounter_query(Structure): - pass - -struct_kgsl_perfcounter_query._pack_ = 1 # source:False -struct_kgsl_perfcounter_query._fields_ = [ - ('groupid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('countables', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('max_counters', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -IOCTL_KGSL_PERFCOUNTER_QUERY = _IOWR ( 0x09 , 0x3A , struct_kgsl_perfcounter_query ) # macro (from list) -class struct_kgsl_perfcounter_read_group(Structure): - pass - -struct_kgsl_perfcounter_read_group._pack_ = 1 # source:False -struct_kgsl_perfcounter_read_group._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('value', ctypes.c_uint64), -] - -class struct_kgsl_perfcounter_read(Structure): - pass - -struct_kgsl_perfcounter_read._pack_ = 1 # source:False -struct_kgsl_perfcounter_read._fields_ = [ - ('reads', ctypes.POINTER(struct_kgsl_perfcounter_read_group)), - ('count', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_PERFCOUNTER_READ = _IOWR ( 0x09 , 0x3B , struct_kgsl_perfcounter_read ) # macro (from list) -class struct_kgsl_gpumem_sync_cache_bulk(Structure): - pass - -struct_kgsl_gpumem_sync_cache_bulk._pack_ = 1 # source:False -struct_kgsl_gpumem_sync_cache_bulk._fields_ = [ - ('id_list', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), -] - -IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK = _IOWR ( 0x09 , 0x3C , struct_kgsl_gpumem_sync_cache_bulk ) # macro (from list) -class struct_kgsl_cmd_syncpoint_timestamp(Structure): - pass - -struct_kgsl_cmd_syncpoint_timestamp._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_cmd_syncpoint_fence(Structure): - pass - -struct_kgsl_cmd_syncpoint_fence._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint_fence._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_cmd_syncpoint(Structure): - pass - -struct_kgsl_cmd_syncpoint._pack_ = 1 # source:False -struct_kgsl_cmd_syncpoint._fields_ = [ - ('type', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), -] - -class struct_kgsl_submit_commands(Structure): - pass - -struct_kgsl_submit_commands._pack_ = 1 # source:False -struct_kgsl_submit_commands._fields_ = [ - ('context_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('cmdlist', ctypes.POINTER(struct_kgsl_ibdesc)), - ('numcmds', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('synclist', ctypes.POINTER(struct_kgsl_cmd_syncpoint)), - ('numsyncs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 4), -] - -IOCTL_KGSL_SUBMIT_COMMANDS = _IOWR ( 0x09 , 0x3D , struct_kgsl_submit_commands ) # macro (from list) -class struct_kgsl_device_constraint(Structure): - pass - -struct_kgsl_device_constraint._pack_ = 1 # source:False -struct_kgsl_device_constraint._fields_ = [ - ('type', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('data', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), -] - -class struct_kgsl_device_constraint_pwrlevel(Structure): - pass - -struct_kgsl_device_constraint_pwrlevel._pack_ = 1 # source:False -struct_kgsl_device_constraint_pwrlevel._fields_ = [ - ('level', ctypes.c_uint32), -] - -class struct_kgsl_syncsource_create(Structure): - pass - -struct_kgsl_syncsource_create._pack_ = 1 # source:False -struct_kgsl_syncsource_create._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), -] - -IOCTL_KGSL_SYNCSOURCE_CREATE = _IOWR ( 0x09 , 0x40 , struct_kgsl_syncsource_create ) # macro (from list) -class struct_kgsl_syncsource_destroy(Structure): - pass - -struct_kgsl_syncsource_destroy._pack_ = 1 # source:False -struct_kgsl_syncsource_destroy._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), -] - -IOCTL_KGSL_SYNCSOURCE_DESTROY = _IOWR ( 0x09 , 0x41 , struct_kgsl_syncsource_destroy ) # macro (from list) -class struct_kgsl_syncsource_create_fence(Structure): - pass - -struct_kgsl_syncsource_create_fence._pack_ = 1 # source:False -struct_kgsl_syncsource_create_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), -] - -IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE = _IOWR ( 0x09 , 0x42 , struct_kgsl_syncsource_create_fence ) # macro (from list) -class struct_kgsl_syncsource_signal_fence(Structure): - pass - -struct_kgsl_syncsource_signal_fence._pack_ = 1 # source:False -struct_kgsl_syncsource_signal_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), -] - -IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE = _IOWR ( 0x09 , 0x43 , struct_kgsl_syncsource_signal_fence ) # macro (from list) -class struct_kgsl_cff_sync_gpuobj(Structure): - pass - -struct_kgsl_cff_sync_gpuobj._pack_ = 1 # source:False -struct_kgsl_cff_sync_gpuobj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_CFF_SYNC_GPUOBJ = _IOW ( 0x09 , 0x44 , struct_kgsl_cff_sync_gpuobj ) # macro (from list) -class struct_kgsl_gpuobj_alloc(Structure): - pass - -struct_kgsl_gpuobj_alloc._pack_ = 1 # source:False -struct_kgsl_gpuobj_alloc._fields_ = [ - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('metadata', ctypes.c_uint64), -] - -IOCTL_KGSL_GPUOBJ_ALLOC = _IOWR ( 0x09 , 0x45 , struct_kgsl_gpuobj_alloc ) # macro (from list) -class struct_kgsl_gpuobj_free(Structure): - pass - -struct_kgsl_gpuobj_free._pack_ = 1 # source:False -struct_kgsl_gpuobj_free._fields_ = [ - ('flags', ctypes.c_uint64), - ('priv', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_GPUOBJ_FREE = _IOW ( 0x09 , 0x46 , struct_kgsl_gpuobj_free ) # macro (from list) -class struct_kgsl_gpu_event_timestamp(Structure): - pass - -struct_kgsl_gpu_event_timestamp._pack_ = 1 # source:False -struct_kgsl_gpu_event_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -class struct_kgsl_gpu_event_fence(Structure): - pass - -struct_kgsl_gpu_event_fence._pack_ = 1 # source:False -struct_kgsl_gpu_event_fence._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_gpuobj_info(Structure): - pass - -struct_kgsl_gpuobj_info._pack_ = 1 # source:False -struct_kgsl_gpuobj_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('va_addr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_GPUOBJ_INFO = _IOWR ( 0x09 , 0x47 , struct_kgsl_gpuobj_info ) # macro (from list) -class struct_kgsl_gpuobj_import(Structure): - pass - -struct_kgsl_gpuobj_import._pack_ = 1 # source:False -struct_kgsl_gpuobj_import._fields_ = [ - ('priv', ctypes.c_uint64), - ('priv_len', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('id', ctypes.c_uint32), -] - -IOCTL_KGSL_GPUOBJ_IMPORT = _IOWR ( 0x09 , 0x48 , struct_kgsl_gpuobj_import ) # macro (from list) -class struct_kgsl_gpuobj_import_dma_buf(Structure): - pass - -struct_kgsl_gpuobj_import_dma_buf._pack_ = 1 # source:False -struct_kgsl_gpuobj_import_dma_buf._fields_ = [ - ('fd', ctypes.c_int32), -] - -class struct_kgsl_gpuobj_import_useraddr(Structure): - pass - -struct_kgsl_gpuobj_import_useraddr._pack_ = 1 # source:False -struct_kgsl_gpuobj_import_useraddr._fields_ = [ - ('virtaddr', ctypes.c_uint64), -] - -class struct_kgsl_gpuobj_sync_obj(Structure): - pass - -struct_kgsl_gpuobj_sync_obj._pack_ = 1 # source:False -struct_kgsl_gpuobj_sync_obj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), -] - -class struct_kgsl_gpuobj_sync(Structure): - pass - -struct_kgsl_gpuobj_sync._pack_ = 1 # source:False -struct_kgsl_gpuobj_sync._fields_ = [ - ('objs', ctypes.c_uint64), - ('obj_len', ctypes.c_uint32), - ('count', ctypes.c_uint32), -] - -IOCTL_KGSL_GPUOBJ_SYNC = _IOW ( 0x09 , 0x49 , struct_kgsl_gpuobj_sync ) # macro (from list) -class struct_kgsl_command_object(Structure): - pass - -struct_kgsl_command_object._pack_ = 1 # source:False -struct_kgsl_command_object._fields_ = [ - ('offset', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('id', ctypes.c_uint32), -] - -class struct_kgsl_command_syncpoint(Structure): - pass - -struct_kgsl_command_syncpoint._pack_ = 1 # source:False -struct_kgsl_command_syncpoint._fields_ = [ - ('priv', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_kgsl_gpu_command(Structure): - pass - -struct_kgsl_gpu_command._pack_ = 1 # source:False -struct_kgsl_gpu_command._fields_ = [ - ('flags', ctypes.c_uint64), - ('cmdlist', ctypes.c_uint64), - ('cmdsize', ctypes.c_uint32), - ('numcmds', ctypes.c_uint32), - ('objlist', ctypes.c_uint64), - ('objsize', ctypes.c_uint32), - ('numobjs', ctypes.c_uint32), - ('synclist', ctypes.c_uint64), - ('syncsize', ctypes.c_uint32), - ('numsyncs', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -IOCTL_KGSL_GPU_COMMAND = _IOWR ( 0x09 , 0x4A , struct_kgsl_gpu_command ) # macro (from list) -class struct_kgsl_preemption_counters_query(Structure): - pass - -struct_kgsl_preemption_counters_query._pack_ = 1 # source:False -struct_kgsl_preemption_counters_query._fields_ = [ - ('counters', ctypes.c_uint64), - ('size_user', ctypes.c_uint32), - ('size_priority_level', ctypes.c_uint32), - ('max_priority_level', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY = _IOWR ( 0x09 , 0x4B , struct_kgsl_preemption_counters_query ) # macro (from list) -class struct_kgsl_gpuobj_set_info(Structure): - pass - -struct_kgsl_gpuobj_set_info._pack_ = 1 # source:False -struct_kgsl_gpuobj_set_info._fields_ = [ - ('flags', ctypes.c_uint64), - ('metadata', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -IOCTL_KGSL_GPUOBJ_SET_INFO = _IOW ( 0x09 , 0x4C , struct_kgsl_gpuobj_set_info ) # macro (from list) -__all__ = \ - ['KGSL_CACHEMODE_MASK', 'KGSL_CACHEMODE_SHIFT', - 'KGSL_CACHEMODE_UNCACHED', 'KGSL_CACHEMODE_WRITEBACK', - 'KGSL_CACHEMODE_WRITECOMBINE', 'KGSL_CACHEMODE_WRITETHROUGH', - 'KGSL_CMDBATCH_CTX_SWITCH', 'KGSL_CMDBATCH_END_OF_FRAME', - 'KGSL_CMDBATCH_MARKER', 'KGSL_CMDBATCH_MEMLIST', - 'KGSL_CMDBATCH_PROFILING', 'KGSL_CMDBATCH_PROFILING_KTIME', - 'KGSL_CMDBATCH_PWR_CONSTRAINT', 'KGSL_CMDBATCH_SUBMIT_IB_LIST', - 'KGSL_CMDBATCH_SYNC', 'KGSL_CMDLIST_CTXTSWITCH_PREAMBLE', - 'KGSL_CMDLIST_IB', 'KGSL_CMDLIST_IB_PREAMBLE', - 'KGSL_CMDWINDOW_2D', 'KGSL_CMDWINDOW_3D', - 'KGSL_CMDWINDOW_ARBITER', 'KGSL_CMDWINDOW_MAX', - 'KGSL_CMDWINDOW_MIN', 'KGSL_CMDWINDOW_MMU', - 'KGSL_CMD_SYNCPOINT_TYPE_FENCE', - 'KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP', 'KGSL_CONSTRAINT_NONE', - 'KGSL_CONSTRAINT_PWRLEVEL', 'KGSL_CONSTRAINT_PWR_MAX', - 'KGSL_CONSTRAINT_PWR_MIN', 'KGSL_CONTEXT_CTX_SWITCH', - 'KGSL_CONTEXT_END_OF_FRAME', 'KGSL_CONTEXT_IFH_NOP', - 'KGSL_CONTEXT_INVALID', 'KGSL_CONTEXT_NO_FAULT_TOLERANCE', - 'KGSL_CONTEXT_NO_GMEM_ALLOC', 'KGSL_CONTEXT_PER_CONTEXT_TS', - 'KGSL_CONTEXT_PREAMBLE', 'KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT', - 'KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN', - 'KGSL_CONTEXT_PREEMPT_STYLE_MASK', - 'KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER', - 'KGSL_CONTEXT_PREEMPT_STYLE_SHIFT', 'KGSL_CONTEXT_PRIORITY_MASK', - 'KGSL_CONTEXT_PRIORITY_SHIFT', 'KGSL_CONTEXT_PRIORITY_UNDEF', - 'KGSL_CONTEXT_PWR_CONSTRAINT', 'KGSL_CONTEXT_SAVE_GMEM', - 'KGSL_CONTEXT_SECURE', 'KGSL_CONTEXT_SUBMIT_IB_LIST', - 'KGSL_CONTEXT_SYNC', 'KGSL_CONTEXT_TRASH_STATE', - 'KGSL_CONTEXT_TYPE_ANY', 'KGSL_CONTEXT_TYPE_C2D', - 'KGSL_CONTEXT_TYPE_CL', 'KGSL_CONTEXT_TYPE_GL', - 'KGSL_CONTEXT_TYPE_MASK', 'KGSL_CONTEXT_TYPE_RS', - 'KGSL_CONTEXT_TYPE_SHIFT', 'KGSL_CONTEXT_TYPE_UNKNOWN', - 'KGSL_CONTEXT_USER_GENERATED_TS', - 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_NO_ERROR', - 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', 'KGSL_DEVICE_3D0', - 'KGSL_DEVICE_MAX', 'KGSL_FLAGS_ACTIVE', 'KGSL_FLAGS_INITIALIZED', - 'KGSL_FLAGS_INITIALIZED0', 'KGSL_FLAGS_NORMALMODE', - 'KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS', 'KGSL_FLAGS_RESERVED0', - 'KGSL_FLAGS_RESERVED1', 'KGSL_FLAGS_RESERVED2', - 'KGSL_FLAGS_SAFEMODE', 'KGSL_FLAGS_SOFT_RESET', - 'KGSL_FLAGS_STARTED', 'KGSL_GPUMEM_CACHE_CLEAN', - 'KGSL_GPUMEM_CACHE_FLUSH', 'KGSL_GPUMEM_CACHE_FROM_GPU', - 'KGSL_GPUMEM_CACHE_INV', 'KGSL_GPUMEM_CACHE_RANGE', - 'KGSL_GPUMEM_CACHE_TO_GPU', 'KGSL_GPUOBJ_ALLOC_METADATA_MAX', - 'KGSL_GPUOBJ_FREE_ON_EVENT', 'KGSL_GPUOBJ_SET_INFO_METADATA', - 'KGSL_GPUOBJ_SET_INFO_TYPE', 'KGSL_GPU_EVENT_FENCE', - 'KGSL_GPU_EVENT_TIMESTAMP', 'KGSL_IBDESC_MEMLIST', - 'KGSL_IBDESC_PROFILING_BUFFER', 'KGSL_IOC_TYPE', - 'KGSL_MEMALIGN_MASK', 'KGSL_MEMALIGN_SHIFT', - 'KGSL_MEMFLAGS_FORCE_32BIT', 'KGSL_MEMFLAGS_GPUREADONLY', - 'KGSL_MEMFLAGS_GPUWRITEONLY', 'KGSL_MEMFLAGS_NOT_USERMEM', - 'KGSL_MEMFLAGS_SECURE', 'KGSL_MEMFLAGS_USERMEM_MASK', - 'KGSL_MEMFLAGS_USERMEM_SHIFT', 'KGSL_MEMFLAGS_USE_CPU_MAP', - 'KGSL_MEMTYPE_2D', 'KGSL_MEMTYPE_ARRAYBUFFER', 'KGSL_MEMTYPE_CL', - 'KGSL_MEMTYPE_CL_BUFFER_MAP', 'KGSL_MEMTYPE_CL_BUFFER_NOMAP', - 'KGSL_MEMTYPE_CL_IMAGE_MAP', 'KGSL_MEMTYPE_CL_IMAGE_NOMAP', - 'KGSL_MEMTYPE_CL_KERNEL_STACK', 'KGSL_MEMTYPE_COMMAND', - 'KGSL_MEMTYPE_EGL_IMAGE', 'KGSL_MEMTYPE_EGL_SHADOW', - 'KGSL_MEMTYPE_EGL_SURFACE', 'KGSL_MEMTYPE_ELEMENTARRAYBUFFER', - 'KGSL_MEMTYPE_FRAMEBUFFER', 'KGSL_MEMTYPE_GL', - 'KGSL_MEMTYPE_KERNEL', 'KGSL_MEMTYPE_MASK', - 'KGSL_MEMTYPE_MULTISAMPLE', 'KGSL_MEMTYPE_OBJECTANY', - 'KGSL_MEMTYPE_RENDERBUFFER', 'KGSL_MEMTYPE_SHIFT', - 'KGSL_MEMTYPE_SURFACE', 'KGSL_MEMTYPE_TEXTURE', - 'KGSL_MEMTYPE_VERTEXARRAYBUFFER', 'KGSL_OBJLIST_MEMOBJ', - 'KGSL_OBJLIST_PROFILE', 'KGSL_PERFCOUNTER_BROKEN', - 'KGSL_PERFCOUNTER_GROUP_ALWAYSON', - 'KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR', - 'KGSL_PERFCOUNTER_GROUP_CCU', 'KGSL_PERFCOUNTER_GROUP_CCU_PWR', - 'KGSL_PERFCOUNTER_GROUP_CMP', 'KGSL_PERFCOUNTER_GROUP_CP', - 'KGSL_PERFCOUNTER_GROUP_CP_PWR', - 'KGSL_PERFCOUNTER_GROUP_GPMU_PWR', 'KGSL_PERFCOUNTER_GROUP_HLSQ', - 'KGSL_PERFCOUNTER_GROUP_L2', 'KGSL_PERFCOUNTER_GROUP_LRZ', - 'KGSL_PERFCOUNTER_GROUP_MAX', 'KGSL_PERFCOUNTER_GROUP_MH', - 'KGSL_PERFCOUNTER_GROUP_PA_SU', 'KGSL_PERFCOUNTER_GROUP_PC', - 'KGSL_PERFCOUNTER_GROUP_PWR', 'KGSL_PERFCOUNTER_GROUP_RAS', - 'KGSL_PERFCOUNTER_GROUP_RB', 'KGSL_PERFCOUNTER_GROUP_RBBM', - 'KGSL_PERFCOUNTER_GROUP_RB_PWR', 'KGSL_PERFCOUNTER_GROUP_SP', - 'KGSL_PERFCOUNTER_GROUP_SP_PWR', 'KGSL_PERFCOUNTER_GROUP_SQ', - 'KGSL_PERFCOUNTER_GROUP_SX', 'KGSL_PERFCOUNTER_GROUP_TCF', - 'KGSL_PERFCOUNTER_GROUP_TCM', 'KGSL_PERFCOUNTER_GROUP_TCR', - 'KGSL_PERFCOUNTER_GROUP_TP', 'KGSL_PERFCOUNTER_GROUP_TP_PWR', - 'KGSL_PERFCOUNTER_GROUP_TSE', 'KGSL_PERFCOUNTER_GROUP_UCHE', - 'KGSL_PERFCOUNTER_GROUP_UCHE_PWR', 'KGSL_PERFCOUNTER_GROUP_VBIF', - 'KGSL_PERFCOUNTER_GROUP_VBIF_PWR', 'KGSL_PERFCOUNTER_GROUP_VFD', - 'KGSL_PERFCOUNTER_GROUP_VPC', 'KGSL_PERFCOUNTER_GROUP_VSC', - 'KGSL_PERFCOUNTER_NOT_USED', 'KGSL_PROP_DEVICE_BITNESS', - 'KGSL_PROP_DEVICE_INFO', 'KGSL_PROP_DEVICE_POWER', - 'KGSL_PROP_DEVICE_SHADOW', 'KGSL_PROP_GPMU_VERSION', - 'KGSL_PROP_GPU_RESET_STAT', 'KGSL_PROP_INTERRUPT_WAITS', - 'KGSL_PROP_MMU_ENABLE', 'KGSL_PROP_PWRCTRL', - 'KGSL_PROP_PWR_CONSTRAINT', 'KGSL_PROP_SHMEM', - 'KGSL_PROP_SHMEM_APERTURES', 'KGSL_PROP_SP_GENERIC_MEM', - 'KGSL_PROP_UCHE_GMEM_VADDR', 'KGSL_PROP_UCODE_VERSION', - 'KGSL_PROP_VERSION', 'KGSL_SYNCOBJ_SERVER_TIMEOUT', - 'KGSL_TIMESTAMP_CONSUMED', 'KGSL_TIMESTAMP_EVENT_FENCE', - 'KGSL_TIMESTAMP_EVENT_GENLOCK', 'KGSL_TIMESTAMP_QUEUED', - 'KGSL_TIMESTAMP_RETIRED', 'KGSL_USER_MEM_TYPE_ADDR', - 'KGSL_USER_MEM_TYPE_ASHMEM', 'KGSL_USER_MEM_TYPE_DMABUF', - 'KGSL_USER_MEM_TYPE_ION', 'KGSL_USER_MEM_TYPE_MAX', - 'KGSL_USER_MEM_TYPE_PMEM', 'KGSL_VERSION_MAJOR', - 'KGSL_VERSION_MINOR', '_IO', '_IOR', '_IOW', '_IOWR', - '_UAPI_MSM_KGSL_H', 'kgsl_cmdwindow_type', 'kgsl_ctx_reset_stat', - 'kgsl_deviceid', 'kgsl_timestamp_type', 'kgsl_user_mem_type', - 'size_t', 'struct_kgsl_bind_gmem_shadow', - 'struct_kgsl_buffer_desc', 'struct_kgsl_cff_sync_gpuobj', - 'struct_kgsl_cff_syncmem', 'struct_kgsl_cff_user_event', - 'struct_kgsl_cmd_syncpoint', 'struct_kgsl_cmd_syncpoint_fence', - 'struct_kgsl_cmd_syncpoint_timestamp', - 'struct_kgsl_cmdbatch_profiling_buffer', - 'struct_kgsl_cmdstream_freememontimestamp', - 'struct_kgsl_cmdstream_freememontimestamp_ctxtid', - 'struct_kgsl_cmdstream_readtimestamp', - 'struct_kgsl_cmdstream_readtimestamp_ctxtid', - 'struct_kgsl_cmdwindow_write', 'struct_kgsl_command_object', - 'struct_kgsl_command_syncpoint', 'struct_kgsl_device_constraint', - 'struct_kgsl_device_constraint_pwrlevel', - 'struct_kgsl_device_getproperty', - 'struct_kgsl_device_waittimestamp', - 'struct_kgsl_device_waittimestamp_ctxtid', 'struct_kgsl_devinfo', - 'struct_kgsl_devmemstore', 'struct_kgsl_drawctxt_create', - 'struct_kgsl_drawctxt_destroy', - 'struct_kgsl_drawctxt_set_bin_base_offset', - 'struct_kgsl_gmem_desc', 'struct_kgsl_gpmu_version', - 'struct_kgsl_gpu_command', 'struct_kgsl_gpu_event_fence', - 'struct_kgsl_gpu_event_timestamp', 'struct_kgsl_gpumem_alloc', - 'struct_kgsl_gpumem_alloc_id', 'struct_kgsl_gpumem_free_id', - 'struct_kgsl_gpumem_get_info', 'struct_kgsl_gpumem_sync_cache', - 'struct_kgsl_gpumem_sync_cache_bulk', 'struct_kgsl_gpuobj_alloc', - 'struct_kgsl_gpuobj_free', 'struct_kgsl_gpuobj_import', - 'struct_kgsl_gpuobj_import_dma_buf', - 'struct_kgsl_gpuobj_import_useraddr', 'struct_kgsl_gpuobj_info', - 'struct_kgsl_gpuobj_set_info', 'struct_kgsl_gpuobj_sync', - 'struct_kgsl_gpuobj_sync_obj', 'struct_kgsl_ibdesc', - 'struct_kgsl_map_user_mem', 'struct_kgsl_perfcounter_get', - 'struct_kgsl_perfcounter_put', 'struct_kgsl_perfcounter_query', - 'struct_kgsl_perfcounter_read', - 'struct_kgsl_perfcounter_read_group', - 'struct_kgsl_preemption_counters_query', - 'struct_kgsl_ringbuffer_issueibcmds', 'struct_kgsl_shadowprop', - 'struct_kgsl_sharedmem_free', 'struct_kgsl_sharedmem_from_pmem', - 'struct_kgsl_sharedmem_from_vmalloc', - 'struct_kgsl_sp_generic_mem', 'struct_kgsl_submit_commands', - 'struct_kgsl_syncsource_create', - 'struct_kgsl_syncsource_create_fence', - 'struct_kgsl_syncsource_destroy', - 'struct_kgsl_syncsource_signal_fence', - 'struct_kgsl_timestamp_event', - 'struct_kgsl_timestamp_event_fence', - 'struct_kgsl_timestamp_event_genlock', - 'struct_kgsl_ucode_version', 'struct_kgsl_version', 'uint64_t'] -def KGSL_CONTEXT_PRIORITY(val): return (val << KGSL_CONTEXT_PRIORITY_SHIFT) & KGSL_CONTEXT_PRIORITY_MASK -def KGSL_CONTEXT_PREEMPT_STYLE(val): return (val << KGSL_CONTEXT_PREEMPT_STYLE_SHIFT) & KGSL_CONTEXT_PREEMPT_STYLE_MASK -def KGSL_CONTEXT_TYPE(val): return (val << KGSL_CONTEXT_TYPE_SHIFT) & KGSL_CONTEXT_TYPE_MASK -def KGSL_CACHEMODE(val): return (val << KGSL_CACHEMODE_SHIFT) & KGSL_CACHEMODE_MASK -def KGSL_MEMTYPE(val): return (val << KGSL_MEMTYPE_SHIFT) & KGSL_MEMTYPE_MASK -def KGSL_MEMALIGN(val): return (val << KGSL_MEMALIGN_SHIFT) & KGSL_MEMALIGN_MASK -def KGSL_MEMFLAGS_USERMEM(val): return (val << KGSL_MEMFLAGS_USERMEM_SHIFT) & KGSL_MEMFLAGS_USERMEM_MASK diff --git a/tinygrad/tinygrad/runtime/autogen/libc.py b/tinygrad/tinygrad/runtime/autogen/libc.py deleted file mode 100644 index 45ba91a8..00000000 --- a/tinygrad/tinygrad/runtime/autogen/libc.py +++ /dev/null @@ -1,6190 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['libc'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['libc'] = None if (libc_path := ctypes.util.find_library('c')) is None else ctypes.CDLL(libc_path, use_errno=True) # ctypes.CDLL('libc') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -_SYS_MMAN_H = 1 # macro -__need_size_t = True # macro -__off_t_defined = True # macro -__mode_t_defined = True # macro -# MAP_FAILED = ((void*)-1) # macro -off_t = ctypes.c_int64 -mode_t = ctypes.c_uint32 -size_t = ctypes.c_uint64 -__off_t = ctypes.c_int64 -try: - mmap = _libraries['libc'].mmap - mmap.restype = ctypes.POINTER(None) - mmap.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, __off_t] -except AttributeError: - pass -try: - munmap = _libraries['libc'].munmap - munmap.restype = ctypes.c_int32 - munmap.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - mprotect = _libraries['libc'].mprotect - mprotect.restype = ctypes.c_int32 - mprotect.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - msync = _libraries['libc'].msync - msync.restype = ctypes.c_int32 - msync.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - madvise = _libraries['libc'].madvise - madvise.restype = ctypes.c_int32 - madvise.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - posix_madvise = _libraries['libc'].posix_madvise - posix_madvise.restype = ctypes.c_int32 - posix_madvise.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - mlock = _libraries['libc'].mlock - mlock.restype = ctypes.c_int32 - mlock.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - munlock = _libraries['libc'].munlock - munlock.restype = ctypes.c_int32 - munlock.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - mlockall = _libraries['libc'].mlockall - mlockall.restype = ctypes.c_int32 - mlockall.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - munlockall = _libraries['libc'].munlockall - munlockall.restype = ctypes.c_int32 - munlockall.argtypes = [] -except AttributeError: - pass -try: - mincore = _libraries['libc'].mincore - mincore.restype = ctypes.c_int32 - mincore.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_ubyte)] -except AttributeError: - pass -try: - shm_open = _libraries['libc'].shm_open - shm_open.restype = ctypes.c_int32 - shm_open.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, mode_t] -except AttributeError: - pass -try: - shm_unlink = _libraries['libc'].shm_unlink - shm_unlink.restype = ctypes.c_int32 - shm_unlink.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -_SYSCALL_H = 1 # macro -_STRING_H = 1 # macro -__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION = True # macro -__need_NULL = True # macro -try: - memcpy = _libraries['libc'].memcpy - memcpy.restype = ctypes.POINTER(None) - memcpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - memmove = _libraries['libc'].memmove - memmove.restype = ctypes.POINTER(None) - memmove.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - memccpy = _libraries['libc'].memccpy - memccpy.restype = ctypes.POINTER(None) - memccpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - memset = _libraries['libc'].memset - memset.restype = ctypes.POINTER(None) - memset.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - memcmp = _libraries['libc'].memcmp - memcmp.restype = ctypes.c_int32 - memcmp.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - __memcmpeq = _libraries['libc'].__memcmpeq - __memcmpeq.restype = ctypes.c_int32 - __memcmpeq.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - memchr = _libraries['libc'].memchr - memchr.restype = ctypes.POINTER(None) - memchr.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - strcpy = _libraries['libc'].strcpy - strcpy.restype = ctypes.POINTER(ctypes.c_char) - strcpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strncpy = _libraries['libc'].strncpy - strncpy.restype = ctypes.POINTER(ctypes.c_char) - strncpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strcat = _libraries['libc'].strcat - strcat.restype = ctypes.POINTER(ctypes.c_char) - strcat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strncat = _libraries['libc'].strncat - strncat.restype = ctypes.POINTER(ctypes.c_char) - strncat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strcmp = _libraries['libc'].strcmp - strcmp.restype = ctypes.c_int32 - strcmp.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strncmp = _libraries['libc'].strncmp - strncmp.restype = ctypes.c_int32 - strncmp.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strcoll = _libraries['libc'].strcoll - strcoll.restype = ctypes.c_int32 - strcoll.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strxfrm = _libraries['libc'].strxfrm - strxfrm.restype = ctypes.c_uint64 - strxfrm.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -class struct___locale_struct(Structure): - pass - -class struct___locale_data(Structure): - pass - -struct___locale_struct._pack_ = 1 # source:False -struct___locale_struct._fields_ = [ - ('__locales', ctypes.POINTER(struct___locale_data) * 13), - ('__ctype_b', ctypes.POINTER(ctypes.c_uint16)), - ('__ctype_tolower', ctypes.POINTER(ctypes.c_int32)), - ('__ctype_toupper', ctypes.POINTER(ctypes.c_int32)), - ('__names', ctypes.POINTER(ctypes.c_char) * 13), -] - -locale_t = ctypes.POINTER(struct___locale_struct) -try: - strcoll_l = _libraries['libc'].strcoll_l - strcoll_l.restype = ctypes.c_int32 - strcoll_l.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), locale_t] -except AttributeError: - pass -try: - strxfrm_l = _libraries['libc'].strxfrm_l - strxfrm_l.restype = size_t - strxfrm_l.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t, locale_t] -except AttributeError: - pass -try: - strdup = _libraries['libc'].strdup - strdup.restype = ctypes.POINTER(ctypes.c_char) - strdup.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strndup = _libraries['libc'].strndup - strndup.restype = ctypes.POINTER(ctypes.c_char) - strndup.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strchr = _libraries['libc'].strchr - strchr.restype = ctypes.POINTER(ctypes.c_char) - strchr.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - strrchr = _libraries['libc'].strrchr - strrchr.restype = ctypes.POINTER(ctypes.c_char) - strrchr.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - strchrnul = _libraries['libc'].strchrnul - strchrnul.restype = ctypes.POINTER(ctypes.c_char) - strchrnul.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - strcspn = _libraries['libc'].strcspn - strcspn.restype = ctypes.c_uint64 - strcspn.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strspn = _libraries['libc'].strspn - strspn.restype = ctypes.c_uint64 - strspn.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strpbrk = _libraries['libc'].strpbrk - strpbrk.restype = ctypes.POINTER(ctypes.c_char) - strpbrk.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strstr = _libraries['libc'].strstr - strstr.restype = ctypes.POINTER(ctypes.c_char) - strstr.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strtok = _libraries['libc'].strtok - strtok.restype = ctypes.POINTER(ctypes.c_char) - strtok.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __strtok_r = _libraries['libc'].__strtok_r - __strtok_r.restype = ctypes.POINTER(ctypes.c_char) - __strtok_r.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - strtok_r = _libraries['libc'].strtok_r - strtok_r.restype = ctypes.POINTER(ctypes.c_char) - strtok_r.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - strcasestr = _libraries['libc'].strcasestr - strcasestr.restype = ctypes.POINTER(ctypes.c_char) - strcasestr.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - memmem = _libraries['libc'].memmem - memmem.restype = ctypes.POINTER(None) - memmem.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - __mempcpy = _libraries['libc'].__mempcpy - __mempcpy.restype = ctypes.POINTER(None) - __mempcpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - mempcpy = _libraries['libc'].mempcpy - mempcpy.restype = ctypes.POINTER(None) - mempcpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - strlen = _libraries['libc'].strlen - strlen.restype = ctypes.c_uint64 - strlen.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strnlen = _libraries['libc'].strnlen - strnlen.restype = size_t - strnlen.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strerror = _libraries['libc'].strerror - strerror.restype = ctypes.POINTER(ctypes.c_char) - strerror.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - strerror_r = _libraries['libc'].strerror_r - strerror_r.restype = ctypes.c_int32 - strerror_r.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strerror_l = _libraries['libc'].strerror_l - strerror_l.restype = ctypes.POINTER(ctypes.c_char) - strerror_l.argtypes = [ctypes.c_int32, locale_t] -except AttributeError: - pass -try: - explicit_bzero = _libraries['libc'].explicit_bzero - explicit_bzero.restype = None - explicit_bzero.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - strsep = _libraries['libc'].strsep - strsep.restype = ctypes.POINTER(ctypes.c_char) - strsep.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - strsignal = _libraries['libc'].strsignal - strsignal.restype = ctypes.POINTER(ctypes.c_char) - strsignal.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - __stpcpy = _libraries['libc'].__stpcpy - __stpcpy.restype = ctypes.POINTER(ctypes.c_char) - __stpcpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - stpcpy = _libraries['libc'].stpcpy - stpcpy.restype = ctypes.POINTER(ctypes.c_char) - stpcpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __stpncpy = _libraries['libc'].__stpncpy - __stpncpy.restype = ctypes.POINTER(ctypes.c_char) - __stpncpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - stpncpy = _libraries['libc'].stpncpy - stpncpy.restype = ctypes.POINTER(ctypes.c_char) - stpncpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strlcpy = _libraries['libc'].strlcpy - strlcpy.restype = size_t - strlcpy.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - strlcat = _libraries['libc'].strlcat - strlcat.restype = size_t - strlcat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -_ELF_H = 1 # macro -EI_NIDENT = (16) # macro -EI_MAG0 = 0 # macro -ELFMAG0 = 0x7f # macro -EI_MAG1 = 1 # macro -ELFMAG1 = 'E' # macro -EI_MAG2 = 2 # macro -ELFMAG2 = 'L' # macro -EI_MAG3 = 3 # macro -ELFMAG3 = 'F' # macro -ELFMAG = "\177ELF" # macro -SELFMAG = 4 # macro -EI_CLASS = 4 # macro -ELFCLASSNONE = 0 # macro -ELFCLASS32 = 1 # macro -ELFCLASS64 = 2 # macro -ELFCLASSNUM = 3 # macro -EI_DATA = 5 # macro -ELFDATANONE = 0 # macro -ELFDATA2LSB = 1 # macro -ELFDATA2MSB = 2 # macro -ELFDATANUM = 3 # macro -EI_VERSION = 6 # macro -EI_OSABI = 7 # macro -ELFOSABI_NONE = 0 # macro -ELFOSABI_SYSV = 0 # macro -ELFOSABI_HPUX = 1 # macro -ELFOSABI_NETBSD = 2 # macro -ELFOSABI_GNU = 3 # macro -ELFOSABI_LINUX = 3 # macro -ELFOSABI_SOLARIS = 6 # macro -ELFOSABI_AIX = 7 # macro -ELFOSABI_IRIX = 8 # macro -ELFOSABI_FREEBSD = 9 # macro -ELFOSABI_TRU64 = 10 # macro -ELFOSABI_MODESTO = 11 # macro -ELFOSABI_OPENBSD = 12 # macro -ELFOSABI_ARM_AEABI = 64 # macro -ELFOSABI_ARM = 97 # macro -ELFOSABI_STANDALONE = 255 # macro -EI_ABIVERSION = 8 # macro -EI_PAD = 9 # macro -ET_NONE = 0 # macro -ET_REL = 1 # macro -ET_EXEC = 2 # macro -ET_DYN = 3 # macro -ET_CORE = 4 # macro -ET_NUM = 5 # macro -ET_LOOS = 0xfe00 # macro -ET_HIOS = 0xfeff # macro -ET_LOPROC = 0xff00 # macro -ET_HIPROC = 0xffff # macro -EM_NONE = 0 # macro -EM_M32 = 1 # macro -EM_SPARC = 2 # macro -EM_386 = 3 # macro -EM_68K = 4 # macro -EM_88K = 5 # macro -EM_IAMCU = 6 # macro -EM_860 = 7 # macro -EM_MIPS = 8 # macro -EM_S370 = 9 # macro -EM_MIPS_RS3_LE = 10 # macro -EM_PARISC = 15 # macro -EM_VPP500 = 17 # macro -EM_SPARC32PLUS = 18 # macro -EM_960 = 19 # macro -EM_PPC = 20 # macro -EM_PPC64 = 21 # macro -EM_S390 = 22 # macro -EM_SPU = 23 # macro -EM_V800 = 36 # macro -EM_FR20 = 37 # macro -EM_RH32 = 38 # macro -EM_RCE = 39 # macro -EM_ARM = 40 # macro -EM_FAKE_ALPHA = 41 # macro -EM_SH = 42 # macro -EM_SPARCV9 = 43 # macro -EM_TRICORE = 44 # macro -EM_ARC = 45 # macro -EM_H8_300 = 46 # macro -EM_H8_300H = 47 # macro -EM_H8S = 48 # macro -EM_H8_500 = 49 # macro -EM_IA_64 = 50 # macro -EM_MIPS_X = 51 # macro -EM_COLDFIRE = 52 # macro -EM_68HC12 = 53 # macro -EM_MMA = 54 # macro -EM_PCP = 55 # macro -EM_NCPU = 56 # macro -EM_NDR1 = 57 # macro -EM_STARCORE = 58 # macro -EM_ME16 = 59 # macro -EM_ST100 = 60 # macro -EM_TINYJ = 61 # macro -EM_X86_64 = 62 # macro -EM_PDSP = 63 # macro -EM_PDP10 = 64 # macro -EM_PDP11 = 65 # macro -EM_FX66 = 66 # macro -EM_ST9PLUS = 67 # macro -EM_ST7 = 68 # macro -EM_68HC16 = 69 # macro -EM_68HC11 = 70 # macro -EM_68HC08 = 71 # macro -EM_68HC05 = 72 # macro -EM_SVX = 73 # macro -EM_ST19 = 74 # macro -EM_VAX = 75 # macro -EM_CRIS = 76 # macro -EM_JAVELIN = 77 # macro -EM_FIREPATH = 78 # macro -EM_ZSP = 79 # macro -EM_MMIX = 80 # macro -EM_HUANY = 81 # macro -EM_PRISM = 82 # macro -EM_AVR = 83 # macro -EM_FR30 = 84 # macro -EM_D10V = 85 # macro -EM_D30V = 86 # macro -EM_V850 = 87 # macro -EM_M32R = 88 # macro -EM_MN10300 = 89 # macro -EM_MN10200 = 90 # macro -EM_PJ = 91 # macro -EM_OPENRISC = 92 # macro -EM_ARC_COMPACT = 93 # macro -EM_XTENSA = 94 # macro -EM_VIDEOCORE = 95 # macro -EM_TMM_GPP = 96 # macro -EM_NS32K = 97 # macro -EM_TPC = 98 # macro -EM_SNP1K = 99 # macro -EM_ST200 = 100 # macro -EM_IP2K = 101 # macro -EM_MAX = 102 # macro -EM_CR = 103 # macro -EM_F2MC16 = 104 # macro -EM_MSP430 = 105 # macro -EM_BLACKFIN = 106 # macro -EM_SE_C33 = 107 # macro -EM_SEP = 108 # macro -EM_ARCA = 109 # macro -EM_UNICORE = 110 # macro -EM_EXCESS = 111 # macro -EM_DXP = 112 # macro -EM_ALTERA_NIOS2 = 113 # macro -EM_CRX = 114 # macro -EM_XGATE = 115 # macro -EM_C166 = 116 # macro -EM_M16C = 117 # macro -EM_DSPIC30F = 118 # macro -EM_CE = 119 # macro -EM_M32C = 120 # macro -EM_TSK3000 = 131 # macro -EM_RS08 = 132 # macro -EM_SHARC = 133 # macro -EM_ECOG2 = 134 # macro -EM_SCORE7 = 135 # macro -EM_DSP24 = 136 # macro -EM_VIDEOCORE3 = 137 # macro -EM_LATTICEMICO32 = 138 # macro -EM_SE_C17 = 139 # macro -EM_TI_C6000 = 140 # macro -EM_TI_C2000 = 141 # macro -EM_TI_C5500 = 142 # macro -EM_TI_ARP32 = 143 # macro -EM_TI_PRU = 144 # macro -EM_MMDSP_PLUS = 160 # macro -EM_CYPRESS_M8C = 161 # macro -EM_R32C = 162 # macro -EM_TRIMEDIA = 163 # macro -EM_QDSP6 = 164 # macro -EM_8051 = 165 # macro -EM_STXP7X = 166 # macro -EM_NDS32 = 167 # macro -EM_ECOG1X = 168 # macro -EM_MAXQ30 = 169 # macro -EM_XIMO16 = 170 # macro -EM_MANIK = 171 # macro -EM_CRAYNV2 = 172 # macro -EM_RX = 173 # macro -EM_METAG = 174 # macro -EM_MCST_ELBRUS = 175 # macro -EM_ECOG16 = 176 # macro -EM_CR16 = 177 # macro -EM_ETPU = 178 # macro -EM_SLE9X = 179 # macro -EM_L10M = 180 # macro -EM_K10M = 181 # macro -EM_AARCH64 = 183 # macro -EM_AVR32 = 185 # macro -EM_STM8 = 186 # macro -EM_TILE64 = 187 # macro -EM_TILEPRO = 188 # macro -EM_MICROBLAZE = 189 # macro -EM_CUDA = 190 # macro -EM_TILEGX = 191 # macro -EM_CLOUDSHIELD = 192 # macro -EM_COREA_1ST = 193 # macro -EM_COREA_2ND = 194 # macro -EM_ARCV2 = 195 # macro -EM_OPEN8 = 196 # macro -EM_RL78 = 197 # macro -EM_VIDEOCORE5 = 198 # macro -EM_78KOR = 199 # macro -EM_56800EX = 200 # macro -EM_BA1 = 201 # macro -EM_BA2 = 202 # macro -EM_XCORE = 203 # macro -EM_MCHP_PIC = 204 # macro -EM_INTELGT = 205 # macro -EM_KM32 = 210 # macro -EM_KMX32 = 211 # macro -EM_EMX16 = 212 # macro -EM_EMX8 = 213 # macro -EM_KVARC = 214 # macro -EM_CDP = 215 # macro -EM_COGE = 216 # macro -EM_COOL = 217 # macro -EM_NORC = 218 # macro -EM_CSR_KALIMBA = 219 # macro -EM_Z80 = 220 # macro -EM_VISIUM = 221 # macro -EM_FT32 = 222 # macro -EM_MOXIE = 223 # macro -EM_AMDGPU = 224 # macro -EM_RISCV = 243 # macro -EM_BPF = 247 # macro -EM_CSKY = 252 # macro -EM_LOONGARCH = 258 # macro -EM_NUM = 259 # macro -EM_ARC_A5 = 93 # macro -EM_ALPHA = 0x9026 # macro -EV_NONE = 0 # macro -EV_CURRENT = 1 # macro -EV_NUM = 2 # macro -SHN_UNDEF = 0 # macro -SHN_LORESERVE = 0xff00 # macro -SHN_LOPROC = 0xff00 # macro -SHN_BEFORE = 0xff00 # macro -SHN_AFTER = 0xff01 # macro -SHN_HIPROC = 0xff1f # macro -SHN_LOOS = 0xff20 # macro -SHN_HIOS = 0xff3f # macro -SHN_ABS = 0xfff1 # macro -SHN_COMMON = 0xfff2 # macro -SHN_XINDEX = 0xffff # macro -SHN_HIRESERVE = 0xffff # macro -SHT_NULL = 0 # macro -SHT_PROGBITS = 1 # macro -SHT_SYMTAB = 2 # macro -SHT_STRTAB = 3 # macro -SHT_RELA = 4 # macro -SHT_HASH = 5 # macro -SHT_DYNAMIC = 6 # macro -SHT_NOTE = 7 # macro -SHT_NOBITS = 8 # macro -SHT_REL = 9 # macro -SHT_SHLIB = 10 # macro -SHT_DYNSYM = 11 # macro -SHT_INIT_ARRAY = 14 # macro -SHT_FINI_ARRAY = 15 # macro -SHT_PREINIT_ARRAY = 16 # macro -SHT_GROUP = 17 # macro -SHT_SYMTAB_SHNDX = 18 # macro -SHT_RELR = 19 # macro -SHT_NUM = 20 # macro -SHT_LOOS = 0x60000000 # macro -SHT_GNU_ATTRIBUTES = 0x6ffffff5 # macro -SHT_GNU_HASH = 0x6ffffff6 # macro -SHT_GNU_LIBLIST = 0x6ffffff7 # macro -SHT_CHECKSUM = 0x6ffffff8 # macro -SHT_LOSUNW = 0x6ffffffa # macro -SHT_SUNW_move = 0x6ffffffa # macro -SHT_SUNW_COMDAT = 0x6ffffffb # macro -SHT_SUNW_syminfo = 0x6ffffffc # macro -SHT_GNU_verdef = 0x6ffffffd # macro -SHT_GNU_verneed = 0x6ffffffe # macro -SHT_GNU_versym = 0x6fffffff # macro -SHT_HISUNW = 0x6fffffff # macro -SHT_HIOS = 0x6fffffff # macro -SHT_LOPROC = 0x70000000 # macro -SHT_HIPROC = 0x7fffffff # macro -SHT_LOUSER = 0x80000000 # macro -SHT_HIUSER = 0x8fffffff # macro -SHF_WRITE = (1<<0) # macro -SHF_ALLOC = (1<<1) # macro -SHF_EXECINSTR = (1<<2) # macro -SHF_MERGE = (1<<4) # macro -SHF_STRINGS = (1<<5) # macro -SHF_INFO_LINK = (1<<6) # macro -SHF_LINK_ORDER = (1<<7) # macro -SHF_OS_NONCONFORMING = (1<<8) # macro -SHF_GROUP = (1<<9) # macro -SHF_TLS = (1<<10) # macro -SHF_COMPRESSED = (1<<11) # macro -SHF_MASKOS = 0x0ff00000 # macro -SHF_MASKPROC = 0xf0000000 # macro -SHF_GNU_RETAIN = (1<<21) # macro -SHF_ORDERED = (1<<30) # macro -SHF_EXCLUDE = (1<<31) # macro -ELFCOMPRESS_ZLIB = 1 # macro -ELFCOMPRESS_ZSTD = 2 # macro -ELFCOMPRESS_LOOS = 0x60000000 # macro -ELFCOMPRESS_HIOS = 0x6fffffff # macro -ELFCOMPRESS_LOPROC = 0x70000000 # macro -ELFCOMPRESS_HIPROC = 0x7fffffff # macro -GRP_COMDAT = 0x1 # macro -SYMINFO_BT_SELF = 0xffff # macro -SYMINFO_BT_PARENT = 0xfffe # macro -SYMINFO_BT_LOWRESERVE = 0xff00 # macro -SYMINFO_FLG_DIRECT = 0x0001 # macro -SYMINFO_FLG_PASSTHRU = 0x0002 # macro -SYMINFO_FLG_COPY = 0x0004 # macro -SYMINFO_FLG_LAZYLOAD = 0x0008 # macro -SYMINFO_NONE = 0 # macro -SYMINFO_CURRENT = 1 # macro -SYMINFO_NUM = 2 # macro -def ELF32_ST_BIND(val): # macro - return (((val))>>4) -def ELF32_ST_TYPE(val): # macro - return ((val)&0xf) -def ELF32_ST_INFO(bind, type): # macro - return (((bind)<<4)+((type)&0xf)) -def ELF64_ST_BIND(val): # macro - return ELF32_ST_BIND(val) -def ELF64_ST_TYPE(val): # macro - return ELF32_ST_TYPE(val) -def ELF64_ST_INFO(bind, type): # macro - return ELF32_ST_INFO((bind),(type)) -STB_LOCAL = 0 # macro -STB_GLOBAL = 1 # macro -STB_WEAK = 2 # macro -STB_NUM = 3 # macro -STB_LOOS = 10 # macro -STB_GNU_UNIQUE = 10 # macro -STB_HIOS = 12 # macro -STB_LOPROC = 13 # macro -STB_HIPROC = 15 # macro -STT_NOTYPE = 0 # macro -STT_OBJECT = 1 # macro -STT_FUNC = 2 # macro -STT_SECTION = 3 # macro -STT_FILE = 4 # macro -STT_COMMON = 5 # macro -STT_TLS = 6 # macro -STT_NUM = 7 # macro -STT_LOOS = 10 # macro -STT_GNU_IFUNC = 10 # macro -STT_HIOS = 12 # macro -STT_LOPROC = 13 # macro -STT_HIPROC = 15 # macro -STN_UNDEF = 0 # macro -def ELF32_ST_VISIBILITY(o): # macro - return ((o)&0x03) -def ELF64_ST_VISIBILITY(o): # macro - return ELF32_ST_VISIBILITY(o) -STV_DEFAULT = 0 # macro -STV_INTERNAL = 1 # macro -STV_HIDDEN = 2 # macro -STV_PROTECTED = 3 # macro -def ELF32_R_SYM(val): # macro - return ((val)>>8) -def ELF32_R_TYPE(val): # macro - return ((val)&0xff) -def ELF32_R_INFO(sym, type): # macro - return (((sym)<<8)+((type)&0xff)) -def ELF64_R_SYM(i): # macro - return ((i)>>32) -def ELF64_R_TYPE(i): # macro - return ((i)&0xffffffff) -PN_XNUM = 0xffff # macro -PT_NULL = 0 # macro -PT_LOAD = 1 # macro -PT_DYNAMIC = 2 # macro -PT_INTERP = 3 # macro -PT_NOTE = 4 # macro -PT_SHLIB = 5 # macro -PT_PHDR = 6 # macro -PT_TLS = 7 # macro -PT_NUM = 8 # macro -PT_LOOS = 0x60000000 # macro -PT_GNU_EH_FRAME = 0x6474e550 # macro -PT_GNU_STACK = 0x6474e551 # macro -PT_GNU_RELRO = 0x6474e552 # macro -PT_GNU_PROPERTY = 0x6474e553 # macro -PT_GNU_SFRAME = 0x6474e554 # macro -PT_LOSUNW = 0x6ffffffa # macro -PT_SUNWBSS = 0x6ffffffa # macro -PT_SUNWSTACK = 0x6ffffffb # macro -PT_HISUNW = 0x6fffffff # macro -PT_HIOS = 0x6fffffff # macro -PT_LOPROC = 0x70000000 # macro -PT_HIPROC = 0x7fffffff # macro -PF_X = (1<<0) # macro -PF_W = (1<<1) # macro -PF_R = (1<<2) # macro -PF_MASKOS = 0x0ff00000 # macro -PF_MASKPROC = 0xf0000000 # macro -NT_PRSTATUS = 1 # macro -NT_PRFPREG = 2 # macro -NT_FPREGSET = 2 # macro -NT_PRPSINFO = 3 # macro -NT_PRXREG = 4 # macro -NT_TASKSTRUCT = 4 # macro -NT_PLATFORM = 5 # macro -NT_AUXV = 6 # macro -NT_GWINDOWS = 7 # macro -NT_ASRS = 8 # macro -NT_PSTATUS = 10 # macro -NT_PSINFO = 13 # macro -NT_PRCRED = 14 # macro -NT_UTSNAME = 15 # macro -NT_LWPSTATUS = 16 # macro -NT_LWPSINFO = 17 # macro -NT_PRFPXREG = 20 # macro -NT_SIGINFO = 0x53494749 # macro -NT_FILE = 0x46494c45 # macro -NT_PRXFPREG = 0x46e62b7f # macro -NT_PPC_VMX = 0x100 # macro -NT_PPC_SPE = 0x101 # macro -NT_PPC_VSX = 0x102 # macro -NT_PPC_TAR = 0x103 # macro -NT_PPC_PPR = 0x104 # macro -NT_PPC_DSCR = 0x105 # macro -NT_PPC_EBB = 0x106 # macro -NT_PPC_PMU = 0x107 # macro -NT_PPC_TM_CGPR = 0x108 # macro -NT_PPC_TM_CFPR = 0x109 # macro -NT_PPC_TM_CVMX = 0x10a # macro -NT_PPC_TM_CVSX = 0x10b # macro -NT_PPC_TM_SPR = 0x10c # macro -NT_PPC_TM_CTAR = 0x10d # macro -NT_PPC_TM_CPPR = 0x10e # macro -NT_PPC_TM_CDSCR = 0x10f # macro -NT_PPC_PKEY = 0x110 # macro -NT_PPC_DEXCR = 0x111 # macro -NT_PPC_HASHKEYR = 0x112 # macro -NT_386_TLS = 0x200 # macro -NT_386_IOPERM = 0x201 # macro -NT_X86_XSTATE = 0x202 # macro -NT_X86_SHSTK = 0x204 # macro -NT_S390_HIGH_GPRS = 0x300 # macro -NT_S390_TIMER = 0x301 # macro -NT_S390_TODCMP = 0x302 # macro -NT_S390_TODPREG = 0x303 # macro -NT_S390_CTRS = 0x304 # macro -NT_S390_PREFIX = 0x305 # macro -NT_S390_LAST_BREAK = 0x306 # macro -NT_S390_SYSTEM_CALL = 0x307 # macro -NT_S390_TDB = 0x308 # macro -NT_S390_VXRS_LOW = 0x309 # macro -NT_S390_VXRS_HIGH = 0x30a # macro -NT_S390_GS_CB = 0x30b # macro -NT_S390_GS_BC = 0x30c # macro -NT_S390_RI_CB = 0x30d # macro -NT_S390_PV_CPU_DATA = 0x30e # macro -NT_ARM_VFP = 0x400 # macro -NT_ARM_TLS = 0x401 # macro -NT_ARM_HW_BREAK = 0x402 # macro -NT_ARM_HW_WATCH = 0x403 # macro -NT_ARM_SYSTEM_CALL = 0x404 # macro -NT_ARM_SVE = 0x405 # macro -NT_ARM_PAC_MASK = 0x406 # macro -NT_ARM_PACA_KEYS = 0x407 # macro -NT_ARM_PACG_KEYS = 0x408 # macro -NT_ARM_TAGGED_ADDR_CTRL = 0x409 # macro -NT_ARM_PAC_ENABLED_KEYS = 0x40a # macro -NT_VMCOREDD = 0x700 # macro -NT_MIPS_DSP = 0x800 # macro -NT_MIPS_FP_MODE = 0x801 # macro -NT_MIPS_MSA = 0x802 # macro -NT_RISCV_CSR = 0x900 # macro -NT_RISCV_VECTOR = 0x901 # macro -NT_LOONGARCH_CPUCFG = 0xa00 # macro -NT_LOONGARCH_CSR = 0xa01 # macro -NT_LOONGARCH_LSX = 0xa02 # macro -NT_LOONGARCH_LASX = 0xa03 # macro -NT_LOONGARCH_LBT = 0xa04 # macro -NT_LOONGARCH_HW_BREAK = 0xa05 # macro -NT_LOONGARCH_HW_WATCH = 0xa06 # macro -NT_VERSION = 1 # macro -DT_NULL = 0 # macro -DT_NEEDED = 1 # macro -DT_PLTRELSZ = 2 # macro -DT_PLTGOT = 3 # macro -DT_HASH = 4 # macro -DT_STRTAB = 5 # macro -DT_SYMTAB = 6 # macro -DT_RELA = 7 # macro -DT_RELASZ = 8 # macro -DT_RELAENT = 9 # macro -DT_STRSZ = 10 # macro -DT_SYMENT = 11 # macro -DT_INIT = 12 # macro -DT_FINI = 13 # macro -DT_SONAME = 14 # macro -DT_RPATH = 15 # macro -DT_SYMBOLIC = 16 # macro -DT_REL = 17 # macro -DT_RELSZ = 18 # macro -DT_RELENT = 19 # macro -DT_PLTREL = 20 # macro -DT_DEBUG = 21 # macro -DT_TEXTREL = 22 # macro -DT_JMPREL = 23 # macro -DT_BIND_NOW = 24 # macro -DT_INIT_ARRAY = 25 # macro -DT_FINI_ARRAY = 26 # macro -DT_INIT_ARRAYSZ = 27 # macro -DT_FINI_ARRAYSZ = 28 # macro -DT_RUNPATH = 29 # macro -DT_FLAGS = 30 # macro -DT_ENCODING = 32 # macro -DT_PREINIT_ARRAY = 32 # macro -DT_PREINIT_ARRAYSZ = 33 # macro -DT_SYMTAB_SHNDX = 34 # macro -DT_RELRSZ = 35 # macro -DT_RELR = 36 # macro -DT_RELRENT = 37 # macro -DT_NUM = 38 # macro -DT_LOOS = 0x6000000d # macro -DT_HIOS = 0x6ffff000 # macro -DT_LOPROC = 0x70000000 # macro -DT_HIPROC = 0x7fffffff # macro -DT_VALRNGLO = 0x6ffffd00 # macro -DT_GNU_PRELINKED = 0x6ffffdf5 # macro -DT_GNU_CONFLICTSZ = 0x6ffffdf6 # macro -DT_GNU_LIBLISTSZ = 0x6ffffdf7 # macro -DT_CHECKSUM = 0x6ffffdf8 # macro -DT_PLTPADSZ = 0x6ffffdf9 # macro -DT_MOVEENT = 0x6ffffdfa # macro -DT_MOVESZ = 0x6ffffdfb # macro -DT_FEATURE_1 = 0x6ffffdfc # macro -DT_POSFLAG_1 = 0x6ffffdfd # macro -DT_SYMINSZ = 0x6ffffdfe # macro -DT_SYMINENT = 0x6ffffdff # macro -DT_VALRNGHI = 0x6ffffdff # macro -def DT_VALTAGIDX(tag): # macro - return (0x6ffffdff-(tag)) -DT_VALNUM = 12 # macro -DT_ADDRRNGLO = 0x6ffffe00 # macro -DT_GNU_HASH = 0x6ffffef5 # macro -DT_TLSDESC_PLT = 0x6ffffef6 # macro -DT_TLSDESC_GOT = 0x6ffffef7 # macro -DT_GNU_CONFLICT = 0x6ffffef8 # macro -DT_GNU_LIBLIST = 0x6ffffef9 # macro -DT_CONFIG = 0x6ffffefa # macro -DT_DEPAUDIT = 0x6ffffefb # macro -DT_AUDIT = 0x6ffffefc # macro -DT_PLTPAD = 0x6ffffefd # macro -DT_MOVETAB = 0x6ffffefe # macro -DT_SYMINFO = 0x6ffffeff # macro -DT_ADDRRNGHI = 0x6ffffeff # macro -def DT_ADDRTAGIDX(tag): # macro - return (0x6ffffeff-(tag)) -DT_ADDRNUM = 11 # macro -DT_VERSYM = 0x6ffffff0 # macro -DT_RELACOUNT = 0x6ffffff9 # macro -DT_RELCOUNT = 0x6ffffffa # macro -DT_FLAGS_1 = 0x6ffffffb # macro -DT_VERDEF = 0x6ffffffc # macro -DT_VERDEFNUM = 0x6ffffffd # macro -DT_VERNEED = 0x6ffffffe # macro -DT_VERNEEDNUM = 0x6fffffff # macro -def DT_VERSIONTAGIDX(tag): # macro - return (0x6fffffff-(tag)) -DT_VERSIONTAGNUM = 16 # macro -DT_AUXILIARY = 0x7ffffffd # macro -DT_FILTER = 0x7fffffff # macro -DT_EXTRANUM = 3 # macro -DF_ORIGIN = 0x00000001 # macro -DF_SYMBOLIC = 0x00000002 # macro -DF_TEXTREL = 0x00000004 # macro -DF_BIND_NOW = 0x00000008 # macro -DF_STATIC_TLS = 0x00000010 # macro -DF_1_NOW = 0x00000001 # macro -DF_1_GLOBAL = 0x00000002 # macro -DF_1_GROUP = 0x00000004 # macro -DF_1_NODELETE = 0x00000008 # macro -DF_1_LOADFLTR = 0x00000010 # macro -DF_1_INITFIRST = 0x00000020 # macro -DF_1_NOOPEN = 0x00000040 # macro -DF_1_ORIGIN = 0x00000080 # macro -DF_1_DIRECT = 0x00000100 # macro -DF_1_TRANS = 0x00000200 # macro -DF_1_INTERPOSE = 0x00000400 # macro -DF_1_NODEFLIB = 0x00000800 # macro -DF_1_NODUMP = 0x00001000 # macro -DF_1_CONFALT = 0x00002000 # macro -DF_1_ENDFILTEE = 0x00004000 # macro -DF_1_DISPRELDNE = 0x00008000 # macro -DF_1_DISPRELPND = 0x00010000 # macro -DF_1_NODIRECT = 0x00020000 # macro -DF_1_IGNMULDEF = 0x00040000 # macro -DF_1_NOKSYMS = 0x00080000 # macro -DF_1_NOHDR = 0x00100000 # macro -DF_1_EDITED = 0x00200000 # macro -DF_1_NORELOC = 0x00400000 # macro -DF_1_SYMINTPOSE = 0x00800000 # macro -DF_1_GLOBAUDIT = 0x01000000 # macro -DF_1_SINGLETON = 0x02000000 # macro -DF_1_STUB = 0x04000000 # macro -DF_1_PIE = 0x08000000 # macro -DF_1_KMOD = 0x10000000 # macro -DF_1_WEAKFILTER = 0x20000000 # macro -DF_1_NOCOMMON = 0x40000000 # macro -DTF_1_PARINIT = 0x00000001 # macro -DTF_1_CONFEXP = 0x00000002 # macro -DF_P1_LAZYLOAD = 0x00000001 # macro -DF_P1_GROUPPERM = 0x00000002 # macro -VER_DEF_NONE = 0 # macro -VER_DEF_CURRENT = 1 # macro -VER_DEF_NUM = 2 # macro -VER_FLG_BASE = 0x1 # macro -VER_FLG_WEAK = 0x2 # macro -VER_NDX_LOCAL = 0 # macro -VER_NDX_GLOBAL = 1 # macro -VER_NDX_LORESERVE = 0xff00 # macro -VER_NDX_ELIMINATE = 0xff01 # macro -VER_NEED_NONE = 0 # macro -VER_NEED_CURRENT = 1 # macro -VER_NEED_NUM = 2 # macro -AT_NULL = 0 # macro -AT_IGNORE = 1 # macro -AT_EXECFD = 2 # macro -AT_PHDR = 3 # macro -AT_PHENT = 4 # macro -AT_PHNUM = 5 # macro -AT_PAGESZ = 6 # macro -AT_BASE = 7 # macro -AT_FLAGS = 8 # macro -AT_ENTRY = 9 # macro -AT_NOTELF = 10 # macro -AT_UID = 11 # macro -AT_EUID = 12 # macro -AT_GID = 13 # macro -AT_EGID = 14 # macro -AT_CLKTCK = 17 # macro -AT_PLATFORM = 15 # macro -AT_HWCAP = 16 # macro -AT_FPUCW = 18 # macro -AT_DCACHEBSIZE = 19 # macro -AT_ICACHEBSIZE = 20 # macro -AT_UCACHEBSIZE = 21 # macro -AT_IGNOREPPC = 22 # macro -AT_SECURE = 23 # macro -AT_BASE_PLATFORM = 24 # macro -AT_RANDOM = 25 # macro -AT_HWCAP2 = 26 # macro -AT_RSEQ_FEATURE_SIZE = 27 # macro -AT_RSEQ_ALIGN = 28 # macro -AT_HWCAP3 = 29 # macro -AT_HWCAP4 = 30 # macro -AT_EXECFN = 31 # macro -AT_SYSINFO = 32 # macro -AT_SYSINFO_EHDR = 33 # macro -AT_L1I_CACHESHAPE = 34 # macro -AT_L1D_CACHESHAPE = 35 # macro -AT_L2_CACHESHAPE = 36 # macro -AT_L3_CACHESHAPE = 37 # macro -AT_L1I_CACHESIZE = 40 # macro -AT_L1I_CACHEGEOMETRY = 41 # macro -AT_L1D_CACHESIZE = 42 # macro -AT_L1D_CACHEGEOMETRY = 43 # macro -AT_L2_CACHESIZE = 44 # macro -AT_L2_CACHEGEOMETRY = 45 # macro -AT_L3_CACHESIZE = 46 # macro -AT_L3_CACHEGEOMETRY = 47 # macro -AT_MINSIGSTKSZ = 51 # macro -ELF_NOTE_SOLARIS = "SUNW Solaris" # macro -ELF_NOTE_GNU = "GNU" # macro -ELF_NOTE_FDO = "FDO" # macro -ELF_NOTE_PAGESIZE_HINT = 1 # macro -NT_GNU_ABI_TAG = 1 # macro -ELF_NOTE_ABI = 1 # macro -ELF_NOTE_OS_LINUX = 0 # macro -ELF_NOTE_OS_GNU = 1 # macro -ELF_NOTE_OS_SOLARIS2 = 2 # macro -ELF_NOTE_OS_FREEBSD = 3 # macro -NT_GNU_HWCAP = 2 # macro -NT_GNU_BUILD_ID = 3 # macro -NT_GNU_GOLD_VERSION = 4 # macro -NT_GNU_PROPERTY_TYPE_0 = 5 # macro -NT_FDO_PACKAGING_METADATA = 0xcafe1a7e # macro -NOTE_GNU_PROPERTY_SECTION_NAME = ".note.gnu.property" # macro -GNU_PROPERTY_STACK_SIZE = 1 # macro -GNU_PROPERTY_NO_COPY_ON_PROTECTED = 2 # macro -GNU_PROPERTY_UINT32_AND_LO = 0xb0000000 # macro -GNU_PROPERTY_UINT32_AND_HI = 0xb0007fff # macro -GNU_PROPERTY_UINT32_OR_LO = 0xb0008000 # macro -GNU_PROPERTY_UINT32_OR_HI = 0xb000ffff # macro -GNU_PROPERTY_1_NEEDED = 0xb0008000 # macro -GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS = (1<<0) # macro -GNU_PROPERTY_LOPROC = 0xc0000000 # macro -GNU_PROPERTY_HIPROC = 0xdfffffff # macro -GNU_PROPERTY_LOUSER = 0xe0000000 # macro -GNU_PROPERTY_HIUSER = 0xffffffff # macro -GNU_PROPERTY_AARCH64_FEATURE_1_AND = 0xc0000000 # macro -GNU_PROPERTY_AARCH64_FEATURE_1_BTI = (1<<0) # macro -GNU_PROPERTY_AARCH64_FEATURE_1_PAC = (1<<1) # macro -GNU_PROPERTY_X86_ISA_1_USED = 0xc0010002 # macro -GNU_PROPERTY_X86_ISA_1_NEEDED = 0xc0008002 # macro -GNU_PROPERTY_X86_FEATURE_1_AND = 0xc0000002 # macro -GNU_PROPERTY_X86_ISA_1_BASELINE = (1<<0) # macro -GNU_PROPERTY_X86_ISA_1_V2 = (1<<1) # macro -GNU_PROPERTY_X86_ISA_1_V3 = (1<<2) # macro -GNU_PROPERTY_X86_ISA_1_V4 = (1<<3) # macro -GNU_PROPERTY_X86_FEATURE_1_IBT = (1<<0) # macro -GNU_PROPERTY_X86_FEATURE_1_SHSTK = (1<<1) # macro -def ELF32_M_SYM(info): # macro - return ((info)>>8) -def ELF32_M_SIZE(info): # macro - return ((info)) -def ELF32_M_INFO(sym, size): # macro - return (((sym)<<8)+(size)) -def ELF64_M_SYM(info): # macro - return ELF32_M_SYM(info) -def ELF64_M_SIZE(info): # macro - return ELF32_M_SIZE(info) -def ELF64_M_INFO(sym, size): # macro - return ELF32_M_INFO(sym,size) -EF_CPU32 = 0x00810000 # macro -R_68K_NONE = 0 # macro -R_68K_32 = 1 # macro -R_68K_16 = 2 # macro -R_68K_8 = 3 # macro -R_68K_PC32 = 4 # macro -R_68K_PC16 = 5 # macro -R_68K_PC8 = 6 # macro -R_68K_GOT32 = 7 # macro -R_68K_GOT16 = 8 # macro -R_68K_GOT8 = 9 # macro -R_68K_GOT32O = 10 # macro -R_68K_GOT16O = 11 # macro -R_68K_GOT8O = 12 # macro -R_68K_PLT32 = 13 # macro -R_68K_PLT16 = 14 # macro -R_68K_PLT8 = 15 # macro -R_68K_PLT32O = 16 # macro -R_68K_PLT16O = 17 # macro -R_68K_PLT8O = 18 # macro -R_68K_COPY = 19 # macro -R_68K_GLOB_DAT = 20 # macro -R_68K_JMP_SLOT = 21 # macro -R_68K_RELATIVE = 22 # macro -R_68K_TLS_GD32 = 25 # macro -R_68K_TLS_GD16 = 26 # macro -R_68K_TLS_GD8 = 27 # macro -R_68K_TLS_LDM32 = 28 # macro -R_68K_TLS_LDM16 = 29 # macro -R_68K_TLS_LDM8 = 30 # macro -R_68K_TLS_LDO32 = 31 # macro -R_68K_TLS_LDO16 = 32 # macro -R_68K_TLS_LDO8 = 33 # macro -R_68K_TLS_IE32 = 34 # macro -R_68K_TLS_IE16 = 35 # macro -R_68K_TLS_IE8 = 36 # macro -R_68K_TLS_LE32 = 37 # macro -R_68K_TLS_LE16 = 38 # macro -R_68K_TLS_LE8 = 39 # macro -R_68K_TLS_DTPMOD32 = 40 # macro -R_68K_TLS_DTPREL32 = 41 # macro -R_68K_TLS_TPREL32 = 42 # macro -R_68K_NUM = 43 # macro -R_386_NONE = 0 # macro -R_386_32 = 1 # macro -R_386_PC32 = 2 # macro -R_386_GOT32 = 3 # macro -R_386_PLT32 = 4 # macro -R_386_COPY = 5 # macro -R_386_GLOB_DAT = 6 # macro -R_386_JMP_SLOT = 7 # macro -R_386_RELATIVE = 8 # macro -R_386_GOTOFF = 9 # macro -R_386_GOTPC = 10 # macro -R_386_32PLT = 11 # macro -R_386_TLS_TPOFF = 14 # macro -R_386_TLS_IE = 15 # macro -R_386_TLS_GOTIE = 16 # macro -R_386_TLS_LE = 17 # macro -R_386_TLS_GD = 18 # macro -R_386_TLS_LDM = 19 # macro -R_386_16 = 20 # macro -R_386_PC16 = 21 # macro -R_386_8 = 22 # macro -R_386_PC8 = 23 # macro -R_386_TLS_GD_32 = 24 # macro -R_386_TLS_GD_PUSH = 25 # macro -R_386_TLS_GD_CALL = 26 # macro -R_386_TLS_GD_POP = 27 # macro -R_386_TLS_LDM_32 = 28 # macro -R_386_TLS_LDM_PUSH = 29 # macro -R_386_TLS_LDM_CALL = 30 # macro -R_386_TLS_LDM_POP = 31 # macro -R_386_TLS_LDO_32 = 32 # macro -R_386_TLS_IE_32 = 33 # macro -R_386_TLS_LE_32 = 34 # macro -R_386_TLS_DTPMOD32 = 35 # macro -R_386_TLS_DTPOFF32 = 36 # macro -R_386_TLS_TPOFF32 = 37 # macro -R_386_SIZE32 = 38 # macro -R_386_TLS_GOTDESC = 39 # macro -R_386_TLS_DESC_CALL = 40 # macro -R_386_TLS_DESC = 41 # macro -R_386_IRELATIVE = 42 # macro -R_386_GOT32X = 43 # macro -R_386_NUM = 44 # macro -STT_SPARC_REGISTER = 13 # macro -EF_SPARCV9_MM = 3 # macro -EF_SPARCV9_TSO = 0 # macro -EF_SPARCV9_PSO = 1 # macro -EF_SPARCV9_RMO = 2 # macro -EF_SPARC_LEDATA = 0x800000 # macro -EF_SPARC_EXT_MASK = 0xFFFF00 # macro -EF_SPARC_32PLUS = 0x000100 # macro -EF_SPARC_SUN_US1 = 0x000200 # macro -EF_SPARC_HAL_R1 = 0x000400 # macro -EF_SPARC_SUN_US3 = 0x000800 # macro -R_SPARC_NONE = 0 # macro -R_SPARC_8 = 1 # macro -R_SPARC_16 = 2 # macro -R_SPARC_32 = 3 # macro -R_SPARC_DISP8 = 4 # macro -R_SPARC_DISP16 = 5 # macro -R_SPARC_DISP32 = 6 # macro -R_SPARC_WDISP30 = 7 # macro -R_SPARC_WDISP22 = 8 # macro -R_SPARC_HI22 = 9 # macro -R_SPARC_22 = 10 # macro -R_SPARC_13 = 11 # macro -R_SPARC_LO10 = 12 # macro -R_SPARC_GOT10 = 13 # macro -R_SPARC_GOT13 = 14 # macro -R_SPARC_GOT22 = 15 # macro -R_SPARC_PC10 = 16 # macro -R_SPARC_PC22 = 17 # macro -R_SPARC_WPLT30 = 18 # macro -R_SPARC_COPY = 19 # macro -R_SPARC_GLOB_DAT = 20 # macro -R_SPARC_JMP_SLOT = 21 # macro -R_SPARC_RELATIVE = 22 # macro -R_SPARC_UA32 = 23 # macro -R_SPARC_PLT32 = 24 # macro -R_SPARC_HIPLT22 = 25 # macro -R_SPARC_LOPLT10 = 26 # macro -R_SPARC_PCPLT32 = 27 # macro -R_SPARC_PCPLT22 = 28 # macro -R_SPARC_PCPLT10 = 29 # macro -R_SPARC_10 = 30 # macro -R_SPARC_11 = 31 # macro -R_SPARC_64 = 32 # macro -R_SPARC_OLO10 = 33 # macro -R_SPARC_HH22 = 34 # macro -R_SPARC_HM10 = 35 # macro -R_SPARC_LM22 = 36 # macro -R_SPARC_PC_HH22 = 37 # macro -R_SPARC_PC_HM10 = 38 # macro -R_SPARC_PC_LM22 = 39 # macro -R_SPARC_WDISP16 = 40 # macro -R_SPARC_WDISP19 = 41 # macro -R_SPARC_GLOB_JMP = 42 # macro -R_SPARC_7 = 43 # macro -R_SPARC_5 = 44 # macro -R_SPARC_6 = 45 # macro -R_SPARC_DISP64 = 46 # macro -R_SPARC_PLT64 = 47 # macro -R_SPARC_HIX22 = 48 # macro -R_SPARC_LOX10 = 49 # macro -R_SPARC_H44 = 50 # macro -R_SPARC_M44 = 51 # macro -R_SPARC_L44 = 52 # macro -R_SPARC_REGISTER = 53 # macro -R_SPARC_UA64 = 54 # macro -R_SPARC_UA16 = 55 # macro -R_SPARC_TLS_GD_HI22 = 56 # macro -R_SPARC_TLS_GD_LO10 = 57 # macro -R_SPARC_TLS_GD_ADD = 58 # macro -R_SPARC_TLS_GD_CALL = 59 # macro -R_SPARC_TLS_LDM_HI22 = 60 # macro -R_SPARC_TLS_LDM_LO10 = 61 # macro -R_SPARC_TLS_LDM_ADD = 62 # macro -R_SPARC_TLS_LDM_CALL = 63 # macro -R_SPARC_TLS_LDO_HIX22 = 64 # macro -R_SPARC_TLS_LDO_LOX10 = 65 # macro -R_SPARC_TLS_LDO_ADD = 66 # macro -R_SPARC_TLS_IE_HI22 = 67 # macro -R_SPARC_TLS_IE_LO10 = 68 # macro -R_SPARC_TLS_IE_LD = 69 # macro -R_SPARC_TLS_IE_LDX = 70 # macro -R_SPARC_TLS_IE_ADD = 71 # macro -R_SPARC_TLS_LE_HIX22 = 72 # macro -R_SPARC_TLS_LE_LOX10 = 73 # macro -R_SPARC_TLS_DTPMOD32 = 74 # macro -R_SPARC_TLS_DTPMOD64 = 75 # macro -R_SPARC_TLS_DTPOFF32 = 76 # macro -R_SPARC_TLS_DTPOFF64 = 77 # macro -R_SPARC_TLS_TPOFF32 = 78 # macro -R_SPARC_TLS_TPOFF64 = 79 # macro -R_SPARC_GOTDATA_HIX22 = 80 # macro -R_SPARC_GOTDATA_LOX10 = 81 # macro -R_SPARC_GOTDATA_OP_HIX22 = 82 # macro -R_SPARC_GOTDATA_OP_LOX10 = 83 # macro -R_SPARC_GOTDATA_OP = 84 # macro -R_SPARC_H34 = 85 # macro -R_SPARC_SIZE32 = 86 # macro -R_SPARC_SIZE64 = 87 # macro -R_SPARC_WDISP10 = 88 # macro -R_SPARC_JMP_IREL = 248 # macro -R_SPARC_IRELATIVE = 249 # macro -R_SPARC_GNU_VTINHERIT = 250 # macro -R_SPARC_GNU_VTENTRY = 251 # macro -R_SPARC_REV32 = 252 # macro -R_SPARC_NUM = 253 # macro -DT_SPARC_REGISTER = 0x70000001 # macro -DT_SPARC_NUM = 2 # macro -EF_MIPS_NOREORDER = 1 # macro -EF_MIPS_PIC = 2 # macro -EF_MIPS_CPIC = 4 # macro -EF_MIPS_XGOT = 8 # macro -EF_MIPS_UCODE = 16 # macro -EF_MIPS_ABI2 = 32 # macro -EF_MIPS_ABI_ON32 = 64 # macro -EF_MIPS_OPTIONS_FIRST = 0x00000080 # macro -EF_MIPS_32BITMODE = 0x00000100 # macro -EF_MIPS_FP64 = 512 # macro -EF_MIPS_NAN2008 = 1024 # macro -EF_MIPS_ARCH_ASE = 0x0f000000 # macro -EF_MIPS_ARCH_ASE_MDMX = 0x08000000 # macro -EF_MIPS_ARCH_ASE_M16 = 0x04000000 # macro -EF_MIPS_ARCH_ASE_MICROMIPS = 0x02000000 # macro -EF_MIPS_ARCH = 0xf0000000 # macro -EF_MIPS_ARCH_1 = 0x00000000 # macro -EF_MIPS_ARCH_2 = 0x10000000 # macro -EF_MIPS_ARCH_3 = 0x20000000 # macro -EF_MIPS_ARCH_4 = 0x30000000 # macro -EF_MIPS_ARCH_5 = 0x40000000 # macro -EF_MIPS_ARCH_32 = 0x50000000 # macro -EF_MIPS_ARCH_64 = 0x60000000 # macro -EF_MIPS_ARCH_32R2 = 0x70000000 # macro -EF_MIPS_ARCH_64R2 = 0x80000000 # macro -EF_MIPS_ARCH_32R6 = 0x90000000 # macro -EF_MIPS_ARCH_64R6 = 0xa0000000 # macro -EF_MIPS_ABI = 0x0000F000 # macro -EF_MIPS_ABI_O32 = 0x00001000 # macro -EF_MIPS_ABI_O64 = 0x00002000 # macro -EF_MIPS_ABI_EABI32 = 0x00003000 # macro -EF_MIPS_ABI_EABI64 = 0x00004000 # macro -EF_MIPS_MACH = 0x00FF0000 # macro -EF_MIPS_MACH_3900 = 0x00810000 # macro -EF_MIPS_MACH_4010 = 0x00820000 # macro -EF_MIPS_MACH_4100 = 0x00830000 # macro -EF_MIPS_MACH_ALLEGREX = 0x00840000 # macro -EF_MIPS_MACH_4650 = 0x00850000 # macro -EF_MIPS_MACH_4120 = 0x00870000 # macro -EF_MIPS_MACH_4111 = 0x00880000 # macro -EF_MIPS_MACH_SB1 = 0x008a0000 # macro -EF_MIPS_MACH_OCTEON = 0x008b0000 # macro -EF_MIPS_MACH_XLR = 0x008c0000 # macro -EF_MIPS_MACH_OCTEON2 = 0x008d0000 # macro -EF_MIPS_MACH_OCTEON3 = 0x008e0000 # macro -EF_MIPS_MACH_5400 = 0x00910000 # macro -EF_MIPS_MACH_5900 = 0x00920000 # macro -EF_MIPS_MACH_IAMR2 = 0x00930000 # macro -EF_MIPS_MACH_5500 = 0x00980000 # macro -EF_MIPS_MACH_9000 = 0x00990000 # macro -EF_MIPS_MACH_LS2E = 0x00A00000 # macro -EF_MIPS_MACH_LS2F = 0x00A10000 # macro -EF_MIPS_MACH_GS464 = 0x00A20000 # macro -EF_MIPS_MACH_GS464E = 0x00A30000 # macro -EF_MIPS_MACH_GS264E = 0x00A40000 # macro -E_MIPS_ARCH_1 = 0x00000000 # macro -E_MIPS_ARCH_2 = 0x10000000 # macro -E_MIPS_ARCH_3 = 0x20000000 # macro -E_MIPS_ARCH_4 = 0x30000000 # macro -E_MIPS_ARCH_5 = 0x40000000 # macro -E_MIPS_ARCH_32 = 0x50000000 # macro -E_MIPS_ARCH_64 = 0x60000000 # macro -SHN_MIPS_ACOMMON = 0xff00 # macro -SHN_MIPS_TEXT = 0xff01 # macro -SHN_MIPS_DATA = 0xff02 # macro -SHN_MIPS_SCOMMON = 0xff03 # macro -SHN_MIPS_SUNDEFINED = 0xff04 # macro -SHT_MIPS_LIBLIST = 0x70000000 # macro -SHT_MIPS_MSYM = 0x70000001 # macro -SHT_MIPS_CONFLICT = 0x70000002 # macro -SHT_MIPS_GPTAB = 0x70000003 # macro -SHT_MIPS_UCODE = 0x70000004 # macro -SHT_MIPS_DEBUG = 0x70000005 # macro -SHT_MIPS_REGINFO = 0x70000006 # macro -SHT_MIPS_PACKAGE = 0x70000007 # macro -SHT_MIPS_PACKSYM = 0x70000008 # macro -SHT_MIPS_RELD = 0x70000009 # macro -SHT_MIPS_IFACE = 0x7000000b # macro -SHT_MIPS_CONTENT = 0x7000000c # macro -SHT_MIPS_OPTIONS = 0x7000000d # macro -SHT_MIPS_SHDR = 0x70000010 # macro -SHT_MIPS_FDESC = 0x70000011 # macro -SHT_MIPS_EXTSYM = 0x70000012 # macro -SHT_MIPS_DENSE = 0x70000013 # macro -SHT_MIPS_PDESC = 0x70000014 # macro -SHT_MIPS_LOCSYM = 0x70000015 # macro -SHT_MIPS_AUXSYM = 0x70000016 # macro -SHT_MIPS_OPTSYM = 0x70000017 # macro -SHT_MIPS_LOCSTR = 0x70000018 # macro -SHT_MIPS_LINE = 0x70000019 # macro -SHT_MIPS_RFDESC = 0x7000001a # macro -SHT_MIPS_DELTASYM = 0x7000001b # macro -SHT_MIPS_DELTAINST = 0x7000001c # macro -SHT_MIPS_DELTACLASS = 0x7000001d # macro -SHT_MIPS_DWARF = 0x7000001e # macro -SHT_MIPS_DELTADECL = 0x7000001f # macro -SHT_MIPS_SYMBOL_LIB = 0x70000020 # macro -SHT_MIPS_EVENTS = 0x70000021 # macro -SHT_MIPS_TRANSLATE = 0x70000022 # macro -SHT_MIPS_PIXIE = 0x70000023 # macro -SHT_MIPS_XLATE = 0x70000024 # macro -SHT_MIPS_XLATE_DEBUG = 0x70000025 # macro -SHT_MIPS_WHIRL = 0x70000026 # macro -SHT_MIPS_EH_REGION = 0x70000027 # macro -SHT_MIPS_XLATE_OLD = 0x70000028 # macro -SHT_MIPS_PDR_EXCEPTION = 0x70000029 # macro -SHT_MIPS_ABIFLAGS = 0x7000002a # macro -SHT_MIPS_XHASH = 0x7000002b # macro -SHF_MIPS_GPREL = 0x10000000 # macro -SHF_MIPS_MERGE = 0x20000000 # macro -SHF_MIPS_ADDR = 0x40000000 # macro -SHF_MIPS_STRINGS = 0x80000000 # macro -SHF_MIPS_NOSTRIP = 0x08000000 # macro -SHF_MIPS_LOCAL = 0x04000000 # macro -SHF_MIPS_NAMES = 0x02000000 # macro -SHF_MIPS_NODUPE = 0x01000000 # macro -STO_MIPS_DEFAULT = 0x0 # macro -STO_MIPS_INTERNAL = 0x1 # macro -STO_MIPS_HIDDEN = 0x2 # macro -STO_MIPS_PROTECTED = 0x3 # macro -STO_MIPS_PLT = 0x8 # macro -STO_MIPS_SC_ALIGN_UNUSED = 0xff # macro -STB_MIPS_SPLIT_COMMON = 13 # macro -ODK_NULL = 0 # macro -ODK_REGINFO = 1 # macro -ODK_EXCEPTIONS = 2 # macro -ODK_PAD = 3 # macro -ODK_HWPATCH = 4 # macro -ODK_FILL = 5 # macro -ODK_TAGS = 6 # macro -ODK_HWAND = 7 # macro -ODK_HWOR = 8 # macro -OEX_FPU_MIN = 0x1f # macro -OEX_FPU_MAX = 0x1f00 # macro -OEX_PAGE0 = 0x10000 # macro -OEX_SMM = 0x20000 # macro -OEX_FPDBUG = 0x40000 # macro -OEX_PRECISEFP = 0x40000 # macro -OEX_DISMISS = 0x80000 # macro -OEX_FPU_INVAL = 0x10 # macro -OEX_FPU_DIV0 = 0x08 # macro -OEX_FPU_OFLO = 0x04 # macro -OEX_FPU_UFLO = 0x02 # macro -OEX_FPU_INEX = 0x01 # macro -OHW_R4KEOP = 0x1 # macro -OHW_R8KPFETCH = 0x2 # macro -OHW_R5KEOP = 0x4 # macro -OHW_R5KCVTL = 0x8 # macro -OPAD_PREFIX = 0x1 # macro -OPAD_POSTFIX = 0x2 # macro -OPAD_SYMBOL = 0x4 # macro -OHWA0_R4KEOP_CHECKED = 0x00000001 # macro -OHWA1_R4KEOP_CLEAN = 0x00000002 # macro -R_MIPS_NONE = 0 # macro -R_MIPS_16 = 1 # macro -R_MIPS_32 = 2 # macro -R_MIPS_REL32 = 3 # macro -R_MIPS_26 = 4 # macro -R_MIPS_HI16 = 5 # macro -R_MIPS_LO16 = 6 # macro -R_MIPS_GPREL16 = 7 # macro -R_MIPS_LITERAL = 8 # macro -R_MIPS_GOT16 = 9 # macro -R_MIPS_PC16 = 10 # macro -R_MIPS_CALL16 = 11 # macro -R_MIPS_GPREL32 = 12 # macro -R_MIPS_SHIFT5 = 16 # macro -R_MIPS_SHIFT6 = 17 # macro -R_MIPS_64 = 18 # macro -R_MIPS_GOT_DISP = 19 # macro -R_MIPS_GOT_PAGE = 20 # macro -R_MIPS_GOT_OFST = 21 # macro -R_MIPS_GOT_HI16 = 22 # macro -R_MIPS_GOT_LO16 = 23 # macro -R_MIPS_SUB = 24 # macro -R_MIPS_INSERT_A = 25 # macro -R_MIPS_INSERT_B = 26 # macro -R_MIPS_DELETE = 27 # macro -R_MIPS_HIGHER = 28 # macro -R_MIPS_HIGHEST = 29 # macro -R_MIPS_CALL_HI16 = 30 # macro -R_MIPS_CALL_LO16 = 31 # macro -R_MIPS_SCN_DISP = 32 # macro -R_MIPS_REL16 = 33 # macro -R_MIPS_ADD_IMMEDIATE = 34 # macro -R_MIPS_PJUMP = 35 # macro -R_MIPS_RELGOT = 36 # macro -R_MIPS_JALR = 37 # macro -R_MIPS_TLS_DTPMOD32 = 38 # macro -R_MIPS_TLS_DTPREL32 = 39 # macro -R_MIPS_TLS_DTPMOD64 = 40 # macro -R_MIPS_TLS_DTPREL64 = 41 # macro -R_MIPS_TLS_GD = 42 # macro -R_MIPS_TLS_LDM = 43 # macro -R_MIPS_TLS_DTPREL_HI16 = 44 # macro -R_MIPS_TLS_DTPREL_LO16 = 45 # macro -R_MIPS_TLS_GOTTPREL = 46 # macro -R_MIPS_TLS_TPREL32 = 47 # macro -R_MIPS_TLS_TPREL64 = 48 # macro -R_MIPS_TLS_TPREL_HI16 = 49 # macro -R_MIPS_TLS_TPREL_LO16 = 50 # macro -R_MIPS_GLOB_DAT = 51 # macro -R_MIPS_PC21_S2 = 60 # macro -R_MIPS_PC26_S2 = 61 # macro -R_MIPS_PC18_S3 = 62 # macro -R_MIPS_PC19_S2 = 63 # macro -R_MIPS_PCHI16 = 64 # macro -R_MIPS_PCLO16 = 65 # macro -R_MIPS16_26 = 100 # macro -R_MIPS16_GPREL = 101 # macro -R_MIPS16_GOT16 = 102 # macro -R_MIPS16_CALL16 = 103 # macro -R_MIPS16_HI16 = 104 # macro -R_MIPS16_LO16 = 105 # macro -R_MIPS16_TLS_GD = 106 # macro -R_MIPS16_TLS_LDM = 107 # macro -R_MIPS16_TLS_DTPREL_HI16 = 108 # macro -R_MIPS16_TLS_DTPREL_LO16 = 109 # macro -R_MIPS16_TLS_GOTTPREL = 110 # macro -R_MIPS16_TLS_TPREL_HI16 = 111 # macro -R_MIPS16_TLS_TPREL_LO16 = 112 # macro -R_MIPS16_PC16_S1 = 113 # macro -R_MIPS_COPY = 126 # macro -R_MIPS_JUMP_SLOT = 127 # macro -R_MIPS_RELATIVE = 128 # macro -R_MICROMIPS_26_S1 = 133 # macro -R_MICROMIPS_HI16 = 134 # macro -R_MICROMIPS_LO16 = 135 # macro -R_MICROMIPS_GPREL16 = 136 # macro -R_MICROMIPS_LITERAL = 137 # macro -R_MICROMIPS_GOT16 = 138 # macro -R_MICROMIPS_PC7_S1 = 139 # macro -R_MICROMIPS_PC10_S1 = 140 # macro -R_MICROMIPS_PC16_S1 = 141 # macro -R_MICROMIPS_CALL16 = 142 # macro -R_MICROMIPS_GOT_DISP = 145 # macro -R_MICROMIPS_GOT_PAGE = 146 # macro -R_MICROMIPS_GOT_OFST = 147 # macro -R_MICROMIPS_GOT_HI16 = 148 # macro -R_MICROMIPS_GOT_LO16 = 149 # macro -R_MICROMIPS_SUB = 150 # macro -R_MICROMIPS_HIGHER = 151 # macro -R_MICROMIPS_HIGHEST = 152 # macro -R_MICROMIPS_CALL_HI16 = 153 # macro -R_MICROMIPS_CALL_LO16 = 154 # macro -R_MICROMIPS_SCN_DISP = 155 # macro -R_MICROMIPS_JALR = 156 # macro -R_MICROMIPS_HI0_LO16 = 157 # macro -R_MICROMIPS_TLS_GD = 162 # macro -R_MICROMIPS_TLS_LDM = 163 # macro -R_MICROMIPS_TLS_DTPREL_HI16 = 164 # macro -R_MICROMIPS_TLS_DTPREL_LO16 = 165 # macro -R_MICROMIPS_TLS_GOTTPREL = 166 # macro -R_MICROMIPS_TLS_TPREL_HI16 = 169 # macro -R_MICROMIPS_TLS_TPREL_LO16 = 170 # macro -R_MICROMIPS_GPREL7_S2 = 172 # macro -R_MICROMIPS_PC23_S2 = 173 # macro -R_MIPS_PC32 = 248 # macro -R_MIPS_EH = 249 # macro -R_MIPS_GNU_REL16_S2 = 250 # macro -R_MIPS_GNU_VTINHERIT = 253 # macro -R_MIPS_GNU_VTENTRY = 254 # macro -R_MIPS_NUM = 255 # macro -PT_MIPS_REGINFO = 0x70000000 # macro -PT_MIPS_RTPROC = 0x70000001 # macro -PT_MIPS_OPTIONS = 0x70000002 # macro -PT_MIPS_ABIFLAGS = 0x70000003 # macro -PF_MIPS_LOCAL = 0x10000000 # macro -DT_MIPS_RLD_VERSION = 0x70000001 # macro -DT_MIPS_TIME_STAMP = 0x70000002 # macro -DT_MIPS_ICHECKSUM = 0x70000003 # macro -DT_MIPS_IVERSION = 0x70000004 # macro -DT_MIPS_FLAGS = 0x70000005 # macro -DT_MIPS_BASE_ADDRESS = 0x70000006 # macro -DT_MIPS_MSYM = 0x70000007 # macro -DT_MIPS_CONFLICT = 0x70000008 # macro -DT_MIPS_LIBLIST = 0x70000009 # macro -DT_MIPS_LOCAL_GOTNO = 0x7000000a # macro -DT_MIPS_CONFLICTNO = 0x7000000b # macro -DT_MIPS_LIBLISTNO = 0x70000010 # macro -DT_MIPS_SYMTABNO = 0x70000011 # macro -DT_MIPS_UNREFEXTNO = 0x70000012 # macro -DT_MIPS_GOTSYM = 0x70000013 # macro -DT_MIPS_HIPAGENO = 0x70000014 # macro -DT_MIPS_RLD_MAP = 0x70000016 # macro -DT_MIPS_DELTA_CLASS = 0x70000017 # macro -DT_MIPS_DELTA_CLASS_NO = 0x70000018 # macro -DT_MIPS_DELTA_INSTANCE = 0x70000019 # macro -DT_MIPS_DELTA_INSTANCE_NO = 0x7000001a # macro -DT_MIPS_DELTA_RELOC = 0x7000001b # macro -DT_MIPS_DELTA_RELOC_NO = 0x7000001c # macro -DT_MIPS_DELTA_SYM = 0x7000001d # macro -DT_MIPS_DELTA_SYM_NO = 0x7000001e # macro -DT_MIPS_DELTA_CLASSSYM = 0x70000020 # macro -DT_MIPS_DELTA_CLASSSYM_NO = 0x70000021 # macro -DT_MIPS_CXX_FLAGS = 0x70000022 # macro -DT_MIPS_PIXIE_INIT = 0x70000023 # macro -DT_MIPS_SYMBOL_LIB = 0x70000024 # macro -DT_MIPS_LOCALPAGE_GOTIDX = 0x70000025 # macro -DT_MIPS_LOCAL_GOTIDX = 0x70000026 # macro -DT_MIPS_HIDDEN_GOTIDX = 0x70000027 # macro -DT_MIPS_PROTECTED_GOTIDX = 0x70000028 # macro -DT_MIPS_OPTIONS = 0x70000029 # macro -DT_MIPS_INTERFACE = 0x7000002a # macro -DT_MIPS_DYNSTR_ALIGN = 0x7000002b # macro -DT_MIPS_INTERFACE_SIZE = 0x7000002c # macro -DT_MIPS_RLD_TEXT_RESOLVE_ADDR = 0x7000002d # macro -DT_MIPS_PERF_SUFFIX = 0x7000002e # macro -DT_MIPS_COMPACT_SIZE = 0x7000002f # macro -DT_MIPS_GP_VALUE = 0x70000030 # macro -DT_MIPS_AUX_DYNAMIC = 0x70000031 # macro -DT_MIPS_PLTGOT = 0x70000032 # macro -DT_MIPS_RWPLT = 0x70000034 # macro -DT_MIPS_RLD_MAP_REL = 0x70000035 # macro -DT_MIPS_XHASH = 0x70000036 # macro -DT_MIPS_NUM = 0x37 # macro -DT_PROCNUM = DT_MIPS_NUM # macro -RHF_NONE = 0 # macro -RHF_QUICKSTART = (1<<0) # macro -RHF_NOTPOT = (1<<1) # macro -RHF_NO_LIBRARY_REPLACEMENT = (1<<2) # macro -RHF_NO_MOVE = (1<<3) # macro -RHF_SGI_ONLY = (1<<4) # macro -RHF_GUARANTEE_INIT = (1<<5) # macro -RHF_DELTA_C_PLUS_PLUS = (1<<6) # macro -RHF_GUARANTEE_START_INIT = (1<<7) # macro -RHF_PIXIE = (1<<8) # macro -RHF_DEFAULT_DELAY_LOAD = (1<<9) # macro -RHF_REQUICKSTART = (1<<10) # macro -RHF_REQUICKSTARTED = (1<<11) # macro -RHF_CORD = (1<<12) # macro -RHF_NO_UNRES_UNDEF = (1<<13) # macro -RHF_RLD_ORDER_SAFE = (1<<14) # macro -LL_NONE = 0 # macro -LL_EXACT_MATCH = (1<<0) # macro -LL_IGNORE_INT_VER = (1<<1) # macro -LL_REQUIRE_MINOR = (1<<2) # macro -LL_EXPORTS = (1<<3) # macro -LL_DELAY_LOAD = (1<<4) # macro -LL_DELTA = (1<<5) # macro -MIPS_AFL_REG_NONE = 0x00 # macro -MIPS_AFL_REG_32 = 0x01 # macro -MIPS_AFL_REG_64 = 0x02 # macro -MIPS_AFL_REG_128 = 0x03 # macro -MIPS_AFL_ASE_DSP = 0x00000001 # macro -MIPS_AFL_ASE_DSPR2 = 0x00000002 # macro -MIPS_AFL_ASE_EVA = 0x00000004 # macro -MIPS_AFL_ASE_MCU = 0x00000008 # macro -MIPS_AFL_ASE_MDMX = 0x00000010 # macro -MIPS_AFL_ASE_MIPS3D = 0x00000020 # macro -MIPS_AFL_ASE_MT = 0x00000040 # macro -MIPS_AFL_ASE_SMARTMIPS = 0x00000080 # macro -MIPS_AFL_ASE_VIRT = 0x00000100 # macro -MIPS_AFL_ASE_MSA = 0x00000200 # macro -MIPS_AFL_ASE_MIPS16 = 0x00000400 # macro -MIPS_AFL_ASE_MICROMIPS = 0x00000800 # macro -MIPS_AFL_ASE_XPA = 0x00001000 # macro -MIPS_AFL_ASE_MASK = 0x00001fff # macro -MIPS_AFL_EXT_XLR = 1 # macro -MIPS_AFL_EXT_OCTEON2 = 2 # macro -MIPS_AFL_EXT_OCTEONP = 3 # macro -MIPS_AFL_EXT_LOONGSON_3A = 4 # macro -MIPS_AFL_EXT_OCTEON = 5 # macro -MIPS_AFL_EXT_5900 = 6 # macro -MIPS_AFL_EXT_4650 = 7 # macro -MIPS_AFL_EXT_4010 = 8 # macro -MIPS_AFL_EXT_4100 = 9 # macro -MIPS_AFL_EXT_3900 = 10 # macro -MIPS_AFL_EXT_10000 = 11 # macro -MIPS_AFL_EXT_SB1 = 12 # macro -MIPS_AFL_EXT_4111 = 13 # macro -MIPS_AFL_EXT_4120 = 14 # macro -MIPS_AFL_EXT_5400 = 15 # macro -MIPS_AFL_EXT_5500 = 16 # macro -MIPS_AFL_EXT_LOONGSON_2E = 17 # macro -MIPS_AFL_EXT_LOONGSON_2F = 18 # macro -MIPS_AFL_FLAGS1_ODDSPREG = 1 # macro -EF_PARISC_TRAPNIL = 0x00010000 # macro -EF_PARISC_EXT = 0x00020000 # macro -EF_PARISC_LSB = 0x00040000 # macro -EF_PARISC_WIDE = 0x00080000 # macro -EF_PARISC_NO_KABP = 0x00100000 # macro -EF_PARISC_LAZYSWAP = 0x00400000 # macro -EF_PARISC_ARCH = 0x0000ffff # macro -EFA_PARISC_1_0 = 0x020b # macro -EFA_PARISC_1_1 = 0x0210 # macro -EFA_PARISC_2_0 = 0x0214 # macro -SHN_PARISC_ANSI_COMMON = 0xff00 # macro -SHN_PARISC_HUGE_COMMON = 0xff01 # macro -SHT_PARISC_EXT = 0x70000000 # macro -SHT_PARISC_UNWIND = 0x70000001 # macro -SHT_PARISC_DOC = 0x70000002 # macro -SHF_PARISC_SHORT = 0x20000000 # macro -SHF_PARISC_HUGE = 0x40000000 # macro -SHF_PARISC_SBP = 0x80000000 # macro -STT_PARISC_MILLICODE = 13 # macro -STT_HP_OPAQUE = (10+0x1) # macro -STT_HP_STUB = (10+0x2) # macro -R_PARISC_NONE = 0 # macro -R_PARISC_DIR32 = 1 # macro -R_PARISC_DIR21L = 2 # macro -R_PARISC_DIR17R = 3 # macro -R_PARISC_DIR17F = 4 # macro -R_PARISC_DIR14R = 6 # macro -R_PARISC_PCREL32 = 9 # macro -R_PARISC_PCREL21L = 10 # macro -R_PARISC_PCREL17R = 11 # macro -R_PARISC_PCREL17F = 12 # macro -R_PARISC_PCREL14R = 14 # macro -R_PARISC_DPREL21L = 18 # macro -R_PARISC_DPREL14R = 22 # macro -R_PARISC_GPREL21L = 26 # macro -R_PARISC_GPREL14R = 30 # macro -R_PARISC_LTOFF21L = 34 # macro -R_PARISC_LTOFF14R = 38 # macro -R_PARISC_SECREL32 = 41 # macro -R_PARISC_SEGBASE = 48 # macro -R_PARISC_SEGREL32 = 49 # macro -R_PARISC_PLTOFF21L = 50 # macro -R_PARISC_PLTOFF14R = 54 # macro -R_PARISC_LTOFF_FPTR32 = 57 # macro -R_PARISC_LTOFF_FPTR21L = 58 # macro -R_PARISC_LTOFF_FPTR14R = 62 # macro -R_PARISC_FPTR64 = 64 # macro -R_PARISC_PLABEL32 = 65 # macro -R_PARISC_PLABEL21L = 66 # macro -R_PARISC_PLABEL14R = 70 # macro -R_PARISC_PCREL64 = 72 # macro -R_PARISC_PCREL22F = 74 # macro -R_PARISC_PCREL14WR = 75 # macro -R_PARISC_PCREL14DR = 76 # macro -R_PARISC_PCREL16F = 77 # macro -R_PARISC_PCREL16WF = 78 # macro -R_PARISC_PCREL16DF = 79 # macro -R_PARISC_DIR64 = 80 # macro -R_PARISC_DIR14WR = 83 # macro -R_PARISC_DIR14DR = 84 # macro -R_PARISC_DIR16F = 85 # macro -R_PARISC_DIR16WF = 86 # macro -R_PARISC_DIR16DF = 87 # macro -R_PARISC_GPREL64 = 88 # macro -R_PARISC_GPREL14WR = 91 # macro -R_PARISC_GPREL14DR = 92 # macro -R_PARISC_GPREL16F = 93 # macro -R_PARISC_GPREL16WF = 94 # macro -R_PARISC_GPREL16DF = 95 # macro -R_PARISC_LTOFF64 = 96 # macro -R_PARISC_LTOFF14WR = 99 # macro -R_PARISC_LTOFF14DR = 100 # macro -R_PARISC_LTOFF16F = 101 # macro -R_PARISC_LTOFF16WF = 102 # macro -R_PARISC_LTOFF16DF = 103 # macro -R_PARISC_SECREL64 = 104 # macro -R_PARISC_SEGREL64 = 112 # macro -R_PARISC_PLTOFF14WR = 115 # macro -R_PARISC_PLTOFF14DR = 116 # macro -R_PARISC_PLTOFF16F = 117 # macro -R_PARISC_PLTOFF16WF = 118 # macro -R_PARISC_PLTOFF16DF = 119 # macro -R_PARISC_LTOFF_FPTR64 = 120 # macro -R_PARISC_LTOFF_FPTR14WR = 123 # macro -R_PARISC_LTOFF_FPTR14DR = 124 # macro -R_PARISC_LTOFF_FPTR16F = 125 # macro -R_PARISC_LTOFF_FPTR16WF = 126 # macro -R_PARISC_LTOFF_FPTR16DF = 127 # macro -R_PARISC_LORESERVE = 128 # macro -R_PARISC_COPY = 128 # macro -R_PARISC_IPLT = 129 # macro -R_PARISC_EPLT = 130 # macro -R_PARISC_TPREL32 = 153 # macro -R_PARISC_TPREL21L = 154 # macro -R_PARISC_TPREL14R = 158 # macro -R_PARISC_LTOFF_TP21L = 162 # macro -R_PARISC_LTOFF_TP14R = 166 # macro -R_PARISC_LTOFF_TP14F = 167 # macro -R_PARISC_TPREL64 = 216 # macro -R_PARISC_TPREL14WR = 219 # macro -R_PARISC_TPREL14DR = 220 # macro -R_PARISC_TPREL16F = 221 # macro -R_PARISC_TPREL16WF = 222 # macro -R_PARISC_TPREL16DF = 223 # macro -R_PARISC_LTOFF_TP64 = 224 # macro -R_PARISC_LTOFF_TP14WR = 227 # macro -R_PARISC_LTOFF_TP14DR = 228 # macro -R_PARISC_LTOFF_TP16F = 229 # macro -R_PARISC_LTOFF_TP16WF = 230 # macro -R_PARISC_LTOFF_TP16DF = 231 # macro -R_PARISC_GNU_VTENTRY = 232 # macro -R_PARISC_GNU_VTINHERIT = 233 # macro -R_PARISC_TLS_GD21L = 234 # macro -R_PARISC_TLS_GD14R = 235 # macro -R_PARISC_TLS_GDCALL = 236 # macro -R_PARISC_TLS_LDM21L = 237 # macro -R_PARISC_TLS_LDM14R = 238 # macro -R_PARISC_TLS_LDMCALL = 239 # macro -R_PARISC_TLS_LDO21L = 240 # macro -R_PARISC_TLS_LDO14R = 241 # macro -R_PARISC_TLS_DTPMOD32 = 242 # macro -R_PARISC_TLS_DTPMOD64 = 243 # macro -R_PARISC_TLS_DTPOFF32 = 244 # macro -R_PARISC_TLS_DTPOFF64 = 245 # macro -R_PARISC_TLS_LE21L = 154 # macro -R_PARISC_TLS_LE14R = 158 # macro -R_PARISC_TLS_IE21L = 162 # macro -R_PARISC_TLS_IE14R = 166 # macro -R_PARISC_TLS_TPREL32 = 153 # macro -R_PARISC_TLS_TPREL64 = 216 # macro -R_PARISC_HIRESERVE = 255 # macro -PT_HP_TLS = (0x60000000+0x0) # macro -PT_HP_CORE_NONE = (0x60000000+0x1) # macro -PT_HP_CORE_VERSION = (0x60000000+0x2) # macro -PT_HP_CORE_KERNEL = (0x60000000+0x3) # macro -PT_HP_CORE_COMM = (0x60000000+0x4) # macro -PT_HP_CORE_PROC = (0x60000000+0x5) # macro -PT_HP_CORE_LOADABLE = (0x60000000+0x6) # macro -PT_HP_CORE_STACK = (0x60000000+0x7) # macro -PT_HP_CORE_SHM = (0x60000000+0x8) # macro -PT_HP_CORE_MMF = (0x60000000+0x9) # macro -PT_HP_PARALLEL = (0x60000000+0x10) # macro -PT_HP_FASTBIND = (0x60000000+0x11) # macro -PT_HP_OPT_ANNOT = (0x60000000+0x12) # macro -PT_HP_HSL_ANNOT = (0x60000000+0x13) # macro -PT_HP_STACK = (0x60000000+0x14) # macro -PT_PARISC_ARCHEXT = 0x70000000 # macro -PT_PARISC_UNWIND = 0x70000001 # macro -PF_PARISC_SBP = 0x08000000 # macro -PF_HP_PAGE_SIZE = 0x00100000 # macro -PF_HP_FAR_SHARED = 0x00200000 # macro -PF_HP_NEAR_SHARED = 0x00400000 # macro -PF_HP_CODE = 0x01000000 # macro -PF_HP_MODIFY = 0x02000000 # macro -PF_HP_LAZYSWAP = 0x04000000 # macro -PF_HP_SBP = 0x08000000 # macro -EF_ALPHA_32BIT = 1 # macro -EF_ALPHA_CANRELAX = 2 # macro -SHT_ALPHA_DEBUG = 0x70000001 # macro -SHT_ALPHA_REGINFO = 0x70000002 # macro -SHF_ALPHA_GPREL = 0x10000000 # macro -STO_ALPHA_NOPV = 0x80 # macro -STO_ALPHA_STD_GPLOAD = 0x88 # macro -R_ALPHA_NONE = 0 # macro -R_ALPHA_REFLONG = 1 # macro -R_ALPHA_REFQUAD = 2 # macro -R_ALPHA_GPREL32 = 3 # macro -R_ALPHA_LITERAL = 4 # macro -R_ALPHA_LITUSE = 5 # macro -R_ALPHA_GPDISP = 6 # macro -R_ALPHA_BRADDR = 7 # macro -R_ALPHA_HINT = 8 # macro -R_ALPHA_SREL16 = 9 # macro -R_ALPHA_SREL32 = 10 # macro -R_ALPHA_SREL64 = 11 # macro -R_ALPHA_GPRELHIGH = 17 # macro -R_ALPHA_GPRELLOW = 18 # macro -R_ALPHA_GPREL16 = 19 # macro -R_ALPHA_COPY = 24 # macro -R_ALPHA_GLOB_DAT = 25 # macro -R_ALPHA_JMP_SLOT = 26 # macro -R_ALPHA_RELATIVE = 27 # macro -R_ALPHA_TLS_GD_HI = 28 # macro -R_ALPHA_TLSGD = 29 # macro -R_ALPHA_TLS_LDM = 30 # macro -R_ALPHA_DTPMOD64 = 31 # macro -R_ALPHA_GOTDTPREL = 32 # macro -R_ALPHA_DTPREL64 = 33 # macro -R_ALPHA_DTPRELHI = 34 # macro -R_ALPHA_DTPRELLO = 35 # macro -R_ALPHA_DTPREL16 = 36 # macro -R_ALPHA_GOTTPREL = 37 # macro -R_ALPHA_TPREL64 = 38 # macro -R_ALPHA_TPRELHI = 39 # macro -R_ALPHA_TPRELLO = 40 # macro -R_ALPHA_TPREL16 = 41 # macro -R_ALPHA_NUM = 46 # macro -LITUSE_ALPHA_ADDR = 0 # macro -LITUSE_ALPHA_BASE = 1 # macro -LITUSE_ALPHA_BYTOFF = 2 # macro -LITUSE_ALPHA_JSR = 3 # macro -LITUSE_ALPHA_TLS_GD = 4 # macro -LITUSE_ALPHA_TLS_LDM = 5 # macro -DT_ALPHA_PLTRO = (0x70000000+0) # macro -DT_ALPHA_NUM = 1 # macro -EF_PPC_EMB = 0x80000000 # macro -EF_PPC_RELOCATABLE = 0x00010000 # macro -EF_PPC_RELOCATABLE_LIB = 0x00008000 # macro -R_PPC_NONE = 0 # macro -R_PPC_ADDR32 = 1 # macro -R_PPC_ADDR24 = 2 # macro -R_PPC_ADDR16 = 3 # macro -R_PPC_ADDR16_LO = 4 # macro -R_PPC_ADDR16_HI = 5 # macro -R_PPC_ADDR16_HA = 6 # macro -R_PPC_ADDR14 = 7 # macro -R_PPC_ADDR14_BRTAKEN = 8 # macro -R_PPC_ADDR14_BRNTAKEN = 9 # macro -R_PPC_REL24 = 10 # macro -R_PPC_REL14 = 11 # macro -R_PPC_REL14_BRTAKEN = 12 # macro -R_PPC_REL14_BRNTAKEN = 13 # macro -R_PPC_GOT16 = 14 # macro -R_PPC_GOT16_LO = 15 # macro -R_PPC_GOT16_HI = 16 # macro -R_PPC_GOT16_HA = 17 # macro -R_PPC_PLTREL24 = 18 # macro -R_PPC_COPY = 19 # macro -R_PPC_GLOB_DAT = 20 # macro -R_PPC_JMP_SLOT = 21 # macro -R_PPC_RELATIVE = 22 # macro -R_PPC_LOCAL24PC = 23 # macro -R_PPC_UADDR32 = 24 # macro -R_PPC_UADDR16 = 25 # macro -R_PPC_REL32 = 26 # macro -R_PPC_PLT32 = 27 # macro -R_PPC_PLTREL32 = 28 # macro -R_PPC_PLT16_LO = 29 # macro -R_PPC_PLT16_HI = 30 # macro -R_PPC_PLT16_HA = 31 # macro -R_PPC_SDAREL16 = 32 # macro -R_PPC_SECTOFF = 33 # macro -R_PPC_SECTOFF_LO = 34 # macro -R_PPC_SECTOFF_HI = 35 # macro -R_PPC_SECTOFF_HA = 36 # macro -R_PPC_TLS = 67 # macro -R_PPC_DTPMOD32 = 68 # macro -R_PPC_TPREL16 = 69 # macro -R_PPC_TPREL16_LO = 70 # macro -R_PPC_TPREL16_HI = 71 # macro -R_PPC_TPREL16_HA = 72 # macro -R_PPC_TPREL32 = 73 # macro -R_PPC_DTPREL16 = 74 # macro -R_PPC_DTPREL16_LO = 75 # macro -R_PPC_DTPREL16_HI = 76 # macro -R_PPC_DTPREL16_HA = 77 # macro -R_PPC_DTPREL32 = 78 # macro -R_PPC_GOT_TLSGD16 = 79 # macro -R_PPC_GOT_TLSGD16_LO = 80 # macro -R_PPC_GOT_TLSGD16_HI = 81 # macro -R_PPC_GOT_TLSGD16_HA = 82 # macro -R_PPC_GOT_TLSLD16 = 83 # macro -R_PPC_GOT_TLSLD16_LO = 84 # macro -R_PPC_GOT_TLSLD16_HI = 85 # macro -R_PPC_GOT_TLSLD16_HA = 86 # macro -R_PPC_GOT_TPREL16 = 87 # macro -R_PPC_GOT_TPREL16_LO = 88 # macro -R_PPC_GOT_TPREL16_HI = 89 # macro -R_PPC_GOT_TPREL16_HA = 90 # macro -R_PPC_GOT_DTPREL16 = 91 # macro -R_PPC_GOT_DTPREL16_LO = 92 # macro -R_PPC_GOT_DTPREL16_HI = 93 # macro -R_PPC_GOT_DTPREL16_HA = 94 # macro -R_PPC_TLSGD = 95 # macro -R_PPC_TLSLD = 96 # macro -R_PPC_EMB_NADDR32 = 101 # macro -R_PPC_EMB_NADDR16 = 102 # macro -R_PPC_EMB_NADDR16_LO = 103 # macro -R_PPC_EMB_NADDR16_HI = 104 # macro -R_PPC_EMB_NADDR16_HA = 105 # macro -R_PPC_EMB_SDAI16 = 106 # macro -R_PPC_EMB_SDA2I16 = 107 # macro -R_PPC_EMB_SDA2REL = 108 # macro -R_PPC_EMB_SDA21 = 109 # macro -R_PPC_EMB_MRKREF = 110 # macro -R_PPC_EMB_RELSEC16 = 111 # macro -R_PPC_EMB_RELST_LO = 112 # macro -R_PPC_EMB_RELST_HI = 113 # macro -R_PPC_EMB_RELST_HA = 114 # macro -R_PPC_EMB_BIT_FLD = 115 # macro -R_PPC_EMB_RELSDA = 116 # macro -R_PPC_DIAB_SDA21_LO = 180 # macro -R_PPC_DIAB_SDA21_HI = 181 # macro -R_PPC_DIAB_SDA21_HA = 182 # macro -R_PPC_DIAB_RELSDA_LO = 183 # macro -R_PPC_DIAB_RELSDA_HI = 184 # macro -R_PPC_DIAB_RELSDA_HA = 185 # macro -R_PPC_IRELATIVE = 248 # macro -R_PPC_REL16 = 249 # macro -R_PPC_REL16_LO = 250 # macro -R_PPC_REL16_HI = 251 # macro -R_PPC_REL16_HA = 252 # macro -R_PPC_TOC16 = 255 # macro -DT_PPC_GOT = (0x70000000+0) # macro -DT_PPC_OPT = (0x70000000+1) # macro -DT_PPC_NUM = 2 # macro -PPC_OPT_TLS = 1 # macro -R_PPC64_NONE = 0 # macro -R_PPC64_ADDR32 = 1 # macro -R_PPC64_ADDR24 = 2 # macro -R_PPC64_ADDR16 = 3 # macro -R_PPC64_ADDR16_LO = 4 # macro -R_PPC64_ADDR16_HI = 5 # macro -R_PPC64_ADDR16_HA = 6 # macro -R_PPC64_ADDR14 = 7 # macro -R_PPC64_ADDR14_BRTAKEN = 8 # macro -R_PPC64_ADDR14_BRNTAKEN = 9 # macro -R_PPC64_REL24 = 10 # macro -R_PPC64_REL14 = 11 # macro -R_PPC64_REL14_BRTAKEN = 12 # macro -R_PPC64_REL14_BRNTAKEN = 13 # macro -R_PPC64_GOT16 = 14 # macro -R_PPC64_GOT16_LO = 15 # macro -R_PPC64_GOT16_HI = 16 # macro -R_PPC64_GOT16_HA = 17 # macro -R_PPC64_COPY = 19 # macro -R_PPC64_GLOB_DAT = 20 # macro -R_PPC64_JMP_SLOT = 21 # macro -R_PPC64_RELATIVE = 22 # macro -R_PPC64_UADDR32 = 24 # macro -R_PPC64_UADDR16 = 25 # macro -R_PPC64_REL32 = 26 # macro -R_PPC64_PLT32 = 27 # macro -R_PPC64_PLTREL32 = 28 # macro -R_PPC64_PLT16_LO = 29 # macro -R_PPC64_PLT16_HI = 30 # macro -R_PPC64_PLT16_HA = 31 # macro -R_PPC64_SECTOFF = 33 # macro -R_PPC64_SECTOFF_LO = 34 # macro -R_PPC64_SECTOFF_HI = 35 # macro -R_PPC64_SECTOFF_HA = 36 # macro -R_PPC64_ADDR30 = 37 # macro -R_PPC64_ADDR64 = 38 # macro -R_PPC64_ADDR16_HIGHER = 39 # macro -R_PPC64_ADDR16_HIGHERA = 40 # macro -R_PPC64_ADDR16_HIGHEST = 41 # macro -R_PPC64_ADDR16_HIGHESTA = 42 # macro -R_PPC64_UADDR64 = 43 # macro -R_PPC64_REL64 = 44 # macro -R_PPC64_PLT64 = 45 # macro -R_PPC64_PLTREL64 = 46 # macro -R_PPC64_TOC16 = 47 # macro -R_PPC64_TOC16_LO = 48 # macro -R_PPC64_TOC16_HI = 49 # macro -R_PPC64_TOC16_HA = 50 # macro -R_PPC64_TOC = 51 # macro -R_PPC64_PLTGOT16 = 52 # macro -R_PPC64_PLTGOT16_LO = 53 # macro -R_PPC64_PLTGOT16_HI = 54 # macro -R_PPC64_PLTGOT16_HA = 55 # macro -R_PPC64_ADDR16_DS = 56 # macro -R_PPC64_ADDR16_LO_DS = 57 # macro -R_PPC64_GOT16_DS = 58 # macro -R_PPC64_GOT16_LO_DS = 59 # macro -R_PPC64_PLT16_LO_DS = 60 # macro -R_PPC64_SECTOFF_DS = 61 # macro -R_PPC64_SECTOFF_LO_DS = 62 # macro -R_PPC64_TOC16_DS = 63 # macro -R_PPC64_TOC16_LO_DS = 64 # macro -R_PPC64_PLTGOT16_DS = 65 # macro -R_PPC64_PLTGOT16_LO_DS = 66 # macro -R_PPC64_TLS = 67 # macro -R_PPC64_DTPMOD64 = 68 # macro -R_PPC64_TPREL16 = 69 # macro -R_PPC64_TPREL16_LO = 70 # macro -R_PPC64_TPREL16_HI = 71 # macro -R_PPC64_TPREL16_HA = 72 # macro -R_PPC64_TPREL64 = 73 # macro -R_PPC64_DTPREL16 = 74 # macro -R_PPC64_DTPREL16_LO = 75 # macro -R_PPC64_DTPREL16_HI = 76 # macro -R_PPC64_DTPREL16_HA = 77 # macro -R_PPC64_DTPREL64 = 78 # macro -R_PPC64_GOT_TLSGD16 = 79 # macro -R_PPC64_GOT_TLSGD16_LO = 80 # macro -R_PPC64_GOT_TLSGD16_HI = 81 # macro -R_PPC64_GOT_TLSGD16_HA = 82 # macro -R_PPC64_GOT_TLSLD16 = 83 # macro -R_PPC64_GOT_TLSLD16_LO = 84 # macro -R_PPC64_GOT_TLSLD16_HI = 85 # macro -R_PPC64_GOT_TLSLD16_HA = 86 # macro -R_PPC64_GOT_TPREL16_DS = 87 # macro -R_PPC64_GOT_TPREL16_LO_DS = 88 # macro -R_PPC64_GOT_TPREL16_HI = 89 # macro -R_PPC64_GOT_TPREL16_HA = 90 # macro -R_PPC64_GOT_DTPREL16_DS = 91 # macro -R_PPC64_GOT_DTPREL16_LO_DS = 92 # macro -R_PPC64_GOT_DTPREL16_HI = 93 # macro -R_PPC64_GOT_DTPREL16_HA = 94 # macro -R_PPC64_TPREL16_DS = 95 # macro -R_PPC64_TPREL16_LO_DS = 96 # macro -R_PPC64_TPREL16_HIGHER = 97 # macro -R_PPC64_TPREL16_HIGHERA = 98 # macro -R_PPC64_TPREL16_HIGHEST = 99 # macro -R_PPC64_TPREL16_HIGHESTA = 100 # macro -R_PPC64_DTPREL16_DS = 101 # macro -R_PPC64_DTPREL16_LO_DS = 102 # macro -R_PPC64_DTPREL16_HIGHER = 103 # macro -R_PPC64_DTPREL16_HIGHERA = 104 # macro -R_PPC64_DTPREL16_HIGHEST = 105 # macro -R_PPC64_DTPREL16_HIGHESTA = 106 # macro -R_PPC64_TLSGD = 107 # macro -R_PPC64_TLSLD = 108 # macro -R_PPC64_TOCSAVE = 109 # macro -R_PPC64_ADDR16_HIGH = 110 # macro -R_PPC64_ADDR16_HIGHA = 111 # macro -R_PPC64_TPREL16_HIGH = 112 # macro -R_PPC64_TPREL16_HIGHA = 113 # macro -R_PPC64_DTPREL16_HIGH = 114 # macro -R_PPC64_DTPREL16_HIGHA = 115 # macro -R_PPC64_JMP_IREL = 247 # macro -R_PPC64_IRELATIVE = 248 # macro -R_PPC64_REL16 = 249 # macro -R_PPC64_REL16_LO = 250 # macro -R_PPC64_REL16_HI = 251 # macro -R_PPC64_REL16_HA = 252 # macro -EF_PPC64_ABI = 3 # macro -DT_PPC64_GLINK = (0x70000000+0) # macro -DT_PPC64_OPD = (0x70000000+1) # macro -DT_PPC64_OPDSZ = (0x70000000+2) # macro -DT_PPC64_OPT = (0x70000000+3) # macro -DT_PPC64_NUM = 4 # macro -PPC64_OPT_TLS = 1 # macro -PPC64_OPT_MULTI_TOC = 2 # macro -PPC64_OPT_LOCALENTRY = 4 # macro -STO_PPC64_LOCAL_BIT = 5 # macro -STO_PPC64_LOCAL_MASK = (7<<5) # macro -def PPC64_LOCAL_ENTRY_OFFSET(other): # macro - return (((1<<(((other)&(7<<5))>>5))>>2)<<2) -EF_ARM_RELEXEC = 0x01 # macro -EF_ARM_HASENTRY = 0x02 # macro -EF_ARM_INTERWORK = 0x04 # macro -EF_ARM_APCS_26 = 0x08 # macro -EF_ARM_APCS_FLOAT = 0x10 # macro -EF_ARM_PIC = 0x20 # macro -EF_ARM_ALIGN8 = 0x40 # macro -EF_ARM_NEW_ABI = 0x80 # macro -EF_ARM_OLD_ABI = 0x100 # macro -EF_ARM_SOFT_FLOAT = 0x200 # macro -EF_ARM_VFP_FLOAT = 0x400 # macro -EF_ARM_MAVERICK_FLOAT = 0x800 # macro -EF_ARM_ABI_FLOAT_SOFT = 0x200 # macro -EF_ARM_ABI_FLOAT_HARD = 0x400 # macro -EF_ARM_SYMSARESORTED = 0x04 # macro -EF_ARM_DYNSYMSUSESEGIDX = 0x08 # macro -EF_ARM_MAPSYMSFIRST = 0x10 # macro -EF_ARM_EABIMASK = 0XFF000000 # macro -EF_ARM_BE8 = 0x00800000 # macro -EF_ARM_LE8 = 0x00400000 # macro -def EF_ARM_EABI_VERSION(flags): # macro - return ((flags)&0XFF000000) -EF_ARM_EABI_UNKNOWN = 0x00000000 # macro -EF_ARM_EABI_VER1 = 0x01000000 # macro -EF_ARM_EABI_VER2 = 0x02000000 # macro -EF_ARM_EABI_VER3 = 0x03000000 # macro -EF_ARM_EABI_VER4 = 0x04000000 # macro -EF_ARM_EABI_VER5 = 0x05000000 # macro -STT_ARM_TFUNC = 13 # macro -STT_ARM_16BIT = 15 # macro -SHF_ARM_ENTRYSECT = 0x10000000 # macro -SHF_ARM_COMDEF = 0x80000000 # macro -PF_ARM_SB = 0x10000000 # macro -PF_ARM_PI = 0x20000000 # macro -PF_ARM_ABS = 0x40000000 # macro -PT_ARM_EXIDX = (0x70000000+1) # macro -SHT_ARM_EXIDX = (0x70000000+1) # macro -SHT_ARM_PREEMPTMAP = (0x70000000+2) # macro -SHT_ARM_ATTRIBUTES = (0x70000000+3) # macro -R_AARCH64_NONE = 0 # macro -R_AARCH64_P32_ABS32 = 1 # macro -R_AARCH64_P32_COPY = 180 # macro -R_AARCH64_P32_GLOB_DAT = 181 # macro -R_AARCH64_P32_JUMP_SLOT = 182 # macro -R_AARCH64_P32_RELATIVE = 183 # macro -R_AARCH64_P32_TLS_DTPMOD = 184 # macro -R_AARCH64_P32_TLS_DTPREL = 185 # macro -R_AARCH64_P32_TLS_TPREL = 186 # macro -R_AARCH64_P32_TLSDESC = 187 # macro -R_AARCH64_P32_IRELATIVE = 188 # macro -R_AARCH64_ABS64 = 257 # macro -R_AARCH64_ABS32 = 258 # macro -R_AARCH64_ABS16 = 259 # macro -R_AARCH64_PREL64 = 260 # macro -R_AARCH64_PREL32 = 261 # macro -R_AARCH64_PREL16 = 262 # macro -R_AARCH64_MOVW_UABS_G0 = 263 # macro -R_AARCH64_MOVW_UABS_G0_NC = 264 # macro -R_AARCH64_MOVW_UABS_G1 = 265 # macro -R_AARCH64_MOVW_UABS_G1_NC = 266 # macro -R_AARCH64_MOVW_UABS_G2 = 267 # macro -R_AARCH64_MOVW_UABS_G2_NC = 268 # macro -R_AARCH64_MOVW_UABS_G3 = 269 # macro -R_AARCH64_MOVW_SABS_G0 = 270 # macro -R_AARCH64_MOVW_SABS_G1 = 271 # macro -R_AARCH64_MOVW_SABS_G2 = 272 # macro -R_AARCH64_LD_PREL_LO19 = 273 # macro -R_AARCH64_ADR_PREL_LO21 = 274 # macro -R_AARCH64_ADR_PREL_PG_HI21 = 275 # macro -R_AARCH64_ADR_PREL_PG_HI21_NC = 276 # macro -R_AARCH64_ADD_ABS_LO12_NC = 277 # macro -R_AARCH64_LDST8_ABS_LO12_NC = 278 # macro -R_AARCH64_TSTBR14 = 279 # macro -R_AARCH64_CONDBR19 = 280 # macro -R_AARCH64_JUMP26 = 282 # macro -R_AARCH64_CALL26 = 283 # macro -R_AARCH64_LDST16_ABS_LO12_NC = 284 # macro -R_AARCH64_LDST32_ABS_LO12_NC = 285 # macro -R_AARCH64_LDST64_ABS_LO12_NC = 286 # macro -R_AARCH64_MOVW_PREL_G0 = 287 # macro -R_AARCH64_MOVW_PREL_G0_NC = 288 # macro -R_AARCH64_MOVW_PREL_G1 = 289 # macro -R_AARCH64_MOVW_PREL_G1_NC = 290 # macro -R_AARCH64_MOVW_PREL_G2 = 291 # macro -R_AARCH64_MOVW_PREL_G2_NC = 292 # macro -R_AARCH64_MOVW_PREL_G3 = 293 # macro -R_AARCH64_LDST128_ABS_LO12_NC = 299 # macro -R_AARCH64_MOVW_GOTOFF_G0 = 300 # macro -R_AARCH64_MOVW_GOTOFF_G0_NC = 301 # macro -R_AARCH64_MOVW_GOTOFF_G1 = 302 # macro -R_AARCH64_MOVW_GOTOFF_G1_NC = 303 # macro -R_AARCH64_MOVW_GOTOFF_G2 = 304 # macro -R_AARCH64_MOVW_GOTOFF_G2_NC = 305 # macro -R_AARCH64_MOVW_GOTOFF_G3 = 306 # macro -R_AARCH64_GOTREL64 = 307 # macro -R_AARCH64_GOTREL32 = 308 # macro -R_AARCH64_GOT_LD_PREL19 = 309 # macro -R_AARCH64_LD64_GOTOFF_LO15 = 310 # macro -R_AARCH64_ADR_GOT_PAGE = 311 # macro -R_AARCH64_LD64_GOT_LO12_NC = 312 # macro -R_AARCH64_LD64_GOTPAGE_LO15 = 313 # macro -R_AARCH64_TLSGD_ADR_PREL21 = 512 # macro -R_AARCH64_TLSGD_ADR_PAGE21 = 513 # macro -R_AARCH64_TLSGD_ADD_LO12_NC = 514 # macro -R_AARCH64_TLSGD_MOVW_G1 = 515 # macro -R_AARCH64_TLSGD_MOVW_G0_NC = 516 # macro -R_AARCH64_TLSLD_ADR_PREL21 = 517 # macro -R_AARCH64_TLSLD_ADR_PAGE21 = 518 # macro -R_AARCH64_TLSLD_ADD_LO12_NC = 519 # macro -R_AARCH64_TLSLD_MOVW_G1 = 520 # macro -R_AARCH64_TLSLD_MOVW_G0_NC = 521 # macro -R_AARCH64_TLSLD_LD_PREL19 = 522 # macro -R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 523 # macro -R_AARCH64_TLSLD_MOVW_DTPREL_G1 = 524 # macro -R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 525 # macro -R_AARCH64_TLSLD_MOVW_DTPREL_G0 = 526 # macro -R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC = 527 # macro -R_AARCH64_TLSLD_ADD_DTPREL_HI12 = 528 # macro -R_AARCH64_TLSLD_ADD_DTPREL_LO12 = 529 # macro -R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC = 530 # macro -R_AARCH64_TLSLD_LDST8_DTPREL_LO12 = 531 # macro -R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC = 532 # macro -R_AARCH64_TLSLD_LDST16_DTPREL_LO12 = 533 # macro -R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC = 534 # macro -R_AARCH64_TLSLD_LDST32_DTPREL_LO12 = 535 # macro -R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC = 536 # macro -R_AARCH64_TLSLD_LDST64_DTPREL_LO12 = 537 # macro -R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC = 538 # macro -R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 = 539 # macro -R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC = 540 # macro -R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 541 # macro -R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 542 # macro -R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 = 543 # macro -R_AARCH64_TLSLE_MOVW_TPREL_G2 = 544 # macro -R_AARCH64_TLSLE_MOVW_TPREL_G1 = 545 # macro -R_AARCH64_TLSLE_MOVW_TPREL_G1_NC = 546 # macro -R_AARCH64_TLSLE_MOVW_TPREL_G0 = 547 # macro -R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = 548 # macro -R_AARCH64_TLSLE_ADD_TPREL_HI12 = 549 # macro -R_AARCH64_TLSLE_ADD_TPREL_LO12 = 550 # macro -R_AARCH64_TLSLE_ADD_TPREL_LO12_NC = 551 # macro -R_AARCH64_TLSLE_LDST8_TPREL_LO12 = 552 # macro -R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 553 # macro -R_AARCH64_TLSLE_LDST16_TPREL_LO12 = 554 # macro -R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC = 555 # macro -R_AARCH64_TLSLE_LDST32_TPREL_LO12 = 556 # macro -R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 557 # macro -R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 558 # macro -R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 559 # macro -R_AARCH64_TLSDESC_LD_PREL19 = 560 # macro -R_AARCH64_TLSDESC_ADR_PREL21 = 561 # macro -R_AARCH64_TLSDESC_ADR_PAGE21 = 562 # macro -R_AARCH64_TLSDESC_LD64_LO12 = 563 # macro -R_AARCH64_TLSDESC_ADD_LO12 = 564 # macro -R_AARCH64_TLSDESC_OFF_G1 = 565 # macro -R_AARCH64_TLSDESC_OFF_G0_NC = 566 # macro -R_AARCH64_TLSDESC_LDR = 567 # macro -R_AARCH64_TLSDESC_ADD = 568 # macro -R_AARCH64_TLSDESC_CALL = 569 # macro -R_AARCH64_TLSLE_LDST128_TPREL_LO12 = 570 # macro -R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC = 571 # macro -R_AARCH64_TLSLD_LDST128_DTPREL_LO12 = 572 # macro -R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC = 573 # macro -R_AARCH64_COPY = 1024 # macro -R_AARCH64_GLOB_DAT = 1025 # macro -R_AARCH64_JUMP_SLOT = 1026 # macro -R_AARCH64_RELATIVE = 1027 # macro -R_AARCH64_TLS_DTPMOD = 1028 # macro -R_AARCH64_TLS_DTPREL = 1029 # macro -R_AARCH64_TLS_TPREL = 1030 # macro -R_AARCH64_TLSDESC = 1031 # macro -R_AARCH64_IRELATIVE = 1032 # macro -PT_AARCH64_MEMTAG_MTE = (0x70000000+2) # macro -DT_AARCH64_BTI_PLT = (0x70000000+1) # macro -DT_AARCH64_PAC_PLT = (0x70000000+3) # macro -DT_AARCH64_VARIANT_PCS = (0x70000000+5) # macro -DT_AARCH64_NUM = 6 # macro -STO_AARCH64_VARIANT_PCS = 0x80 # macro -R_ARM_NONE = 0 # macro -R_ARM_PC24 = 1 # macro -R_ARM_ABS32 = 2 # macro -R_ARM_REL32 = 3 # macro -R_ARM_PC13 = 4 # macro -R_ARM_ABS16 = 5 # macro -R_ARM_ABS12 = 6 # macro -R_ARM_THM_ABS5 = 7 # macro -R_ARM_ABS8 = 8 # macro -R_ARM_SBREL32 = 9 # macro -R_ARM_THM_PC22 = 10 # macro -R_ARM_THM_PC8 = 11 # macro -R_ARM_AMP_VCALL9 = 12 # macro -R_ARM_SWI24 = 13 # macro -R_ARM_TLS_DESC = 13 # macro -R_ARM_THM_SWI8 = 14 # macro -R_ARM_XPC25 = 15 # macro -R_ARM_THM_XPC22 = 16 # macro -R_ARM_TLS_DTPMOD32 = 17 # macro -R_ARM_TLS_DTPOFF32 = 18 # macro -R_ARM_TLS_TPOFF32 = 19 # macro -R_ARM_COPY = 20 # macro -R_ARM_GLOB_DAT = 21 # macro -R_ARM_JUMP_SLOT = 22 # macro -R_ARM_RELATIVE = 23 # macro -R_ARM_GOTOFF = 24 # macro -R_ARM_GOTPC = 25 # macro -R_ARM_GOT32 = 26 # macro -R_ARM_PLT32 = 27 # macro -R_ARM_CALL = 28 # macro -R_ARM_JUMP24 = 29 # macro -R_ARM_THM_JUMP24 = 30 # macro -R_ARM_BASE_ABS = 31 # macro -R_ARM_ALU_PCREL_7_0 = 32 # macro -R_ARM_ALU_PCREL_15_8 = 33 # macro -R_ARM_ALU_PCREL_23_15 = 34 # macro -R_ARM_LDR_SBREL_11_0 = 35 # macro -R_ARM_ALU_SBREL_19_12 = 36 # macro -R_ARM_ALU_SBREL_27_20 = 37 # macro -R_ARM_TARGET1 = 38 # macro -R_ARM_SBREL31 = 39 # macro -R_ARM_V4BX = 40 # macro -R_ARM_TARGET2 = 41 # macro -R_ARM_PREL31 = 42 # macro -R_ARM_MOVW_ABS_NC = 43 # macro -R_ARM_MOVT_ABS = 44 # macro -R_ARM_MOVW_PREL_NC = 45 # macro -R_ARM_MOVT_PREL = 46 # macro -R_ARM_THM_MOVW_ABS_NC = 47 # macro -R_ARM_THM_MOVT_ABS = 48 # macro -R_ARM_THM_MOVW_PREL_NC = 49 # macro -R_ARM_THM_MOVT_PREL = 50 # macro -R_ARM_THM_JUMP19 = 51 # macro -R_ARM_THM_JUMP6 = 52 # macro -R_ARM_THM_ALU_PREL_11_0 = 53 # macro -R_ARM_THM_PC12 = 54 # macro -R_ARM_ABS32_NOI = 55 # macro -R_ARM_REL32_NOI = 56 # macro -R_ARM_ALU_PC_G0_NC = 57 # macro -R_ARM_ALU_PC_G0 = 58 # macro -R_ARM_ALU_PC_G1_NC = 59 # macro -R_ARM_ALU_PC_G1 = 60 # macro -R_ARM_ALU_PC_G2 = 61 # macro -R_ARM_LDR_PC_G1 = 62 # macro -R_ARM_LDR_PC_G2 = 63 # macro -R_ARM_LDRS_PC_G0 = 64 # macro -R_ARM_LDRS_PC_G1 = 65 # macro -R_ARM_LDRS_PC_G2 = 66 # macro -R_ARM_LDC_PC_G0 = 67 # macro -R_ARM_LDC_PC_G1 = 68 # macro -R_ARM_LDC_PC_G2 = 69 # macro -R_ARM_ALU_SB_G0_NC = 70 # macro -R_ARM_ALU_SB_G0 = 71 # macro -R_ARM_ALU_SB_G1_NC = 72 # macro -R_ARM_ALU_SB_G1 = 73 # macro -R_ARM_ALU_SB_G2 = 74 # macro -R_ARM_LDR_SB_G0 = 75 # macro -R_ARM_LDR_SB_G1 = 76 # macro -R_ARM_LDR_SB_G2 = 77 # macro -R_ARM_LDRS_SB_G0 = 78 # macro -R_ARM_LDRS_SB_G1 = 79 # macro -R_ARM_LDRS_SB_G2 = 80 # macro -R_ARM_LDC_SB_G0 = 81 # macro -R_ARM_LDC_SB_G1 = 82 # macro -R_ARM_LDC_SB_G2 = 83 # macro -R_ARM_MOVW_BREL_NC = 84 # macro -R_ARM_MOVT_BREL = 85 # macro -R_ARM_MOVW_BREL = 86 # macro -R_ARM_THM_MOVW_BREL_NC = 87 # macro -R_ARM_THM_MOVT_BREL = 88 # macro -R_ARM_THM_MOVW_BREL = 89 # macro -R_ARM_TLS_GOTDESC = 90 # macro -R_ARM_TLS_CALL = 91 # macro -R_ARM_TLS_DESCSEQ = 92 # macro -R_ARM_THM_TLS_CALL = 93 # macro -R_ARM_PLT32_ABS = 94 # macro -R_ARM_GOT_ABS = 95 # macro -R_ARM_GOT_PREL = 96 # macro -R_ARM_GOT_BREL12 = 97 # macro -R_ARM_GOTOFF12 = 98 # macro -R_ARM_GOTRELAX = 99 # macro -R_ARM_GNU_VTENTRY = 100 # macro -R_ARM_GNU_VTINHERIT = 101 # macro -R_ARM_THM_PC11 = 102 # macro -R_ARM_THM_PC9 = 103 # macro -R_ARM_TLS_GD32 = 104 # macro -R_ARM_TLS_LDM32 = 105 # macro -R_ARM_TLS_LDO32 = 106 # macro -R_ARM_TLS_IE32 = 107 # macro -R_ARM_TLS_LE32 = 108 # macro -R_ARM_TLS_LDO12 = 109 # macro -R_ARM_TLS_LE12 = 110 # macro -R_ARM_TLS_IE12GP = 111 # macro -R_ARM_ME_TOO = 128 # macro -R_ARM_THM_TLS_DESCSEQ = 129 # macro -R_ARM_THM_TLS_DESCSEQ16 = 129 # macro -R_ARM_THM_TLS_DESCSEQ32 = 130 # macro -R_ARM_THM_GOT_BREL12 = 131 # macro -R_ARM_IRELATIVE = 160 # macro -R_ARM_RXPC25 = 249 # macro -R_ARM_RSBREL32 = 250 # macro -R_ARM_THM_RPC22 = 251 # macro -R_ARM_RREL32 = 252 # macro -R_ARM_RABS22 = 253 # macro -R_ARM_RPC24 = 254 # macro -R_ARM_RBASE = 255 # macro -R_ARM_NUM = 256 # macro -R_CKCORE_NONE = 0 # macro -R_CKCORE_ADDR32 = 1 # macro -R_CKCORE_PCRELIMM8BY4 = 2 # macro -R_CKCORE_PCRELIMM11BY2 = 3 # macro -R_CKCORE_PCREL32 = 5 # macro -R_CKCORE_PCRELJSR_IMM11BY2 = 6 # macro -R_CKCORE_RELATIVE = 9 # macro -R_CKCORE_COPY = 10 # macro -R_CKCORE_GLOB_DAT = 11 # macro -R_CKCORE_JUMP_SLOT = 12 # macro -R_CKCORE_GOTOFF = 13 # macro -R_CKCORE_GOTPC = 14 # macro -R_CKCORE_GOT32 = 15 # macro -R_CKCORE_PLT32 = 16 # macro -R_CKCORE_ADDRGOT = 17 # macro -R_CKCORE_ADDRPLT = 18 # macro -R_CKCORE_PCREL_IMM26BY2 = 19 # macro -R_CKCORE_PCREL_IMM16BY2 = 20 # macro -R_CKCORE_PCREL_IMM16BY4 = 21 # macro -R_CKCORE_PCREL_IMM10BY2 = 22 # macro -R_CKCORE_PCREL_IMM10BY4 = 23 # macro -R_CKCORE_ADDR_HI16 = 24 # macro -R_CKCORE_ADDR_LO16 = 25 # macro -R_CKCORE_GOTPC_HI16 = 26 # macro -R_CKCORE_GOTPC_LO16 = 27 # macro -R_CKCORE_GOTOFF_HI16 = 28 # macro -R_CKCORE_GOTOFF_LO16 = 29 # macro -R_CKCORE_GOT12 = 30 # macro -R_CKCORE_GOT_HI16 = 31 # macro -R_CKCORE_GOT_LO16 = 32 # macro -R_CKCORE_PLT12 = 33 # macro -R_CKCORE_PLT_HI16 = 34 # macro -R_CKCORE_PLT_LO16 = 35 # macro -R_CKCORE_ADDRGOT_HI16 = 36 # macro -R_CKCORE_ADDRGOT_LO16 = 37 # macro -R_CKCORE_ADDRPLT_HI16 = 38 # macro -R_CKCORE_ADDRPLT_LO16 = 39 # macro -R_CKCORE_PCREL_JSR_IMM26BY2 = 40 # macro -R_CKCORE_TOFFSET_LO16 = 41 # macro -R_CKCORE_DOFFSET_LO16 = 42 # macro -R_CKCORE_PCREL_IMM18BY2 = 43 # macro -R_CKCORE_DOFFSET_IMM18 = 44 # macro -R_CKCORE_DOFFSET_IMM18BY2 = 45 # macro -R_CKCORE_DOFFSET_IMM18BY4 = 46 # macro -R_CKCORE_GOT_IMM18BY4 = 48 # macro -R_CKCORE_PLT_IMM18BY4 = 49 # macro -R_CKCORE_PCREL_IMM7BY4 = 50 # macro -R_CKCORE_TLS_LE32 = 51 # macro -R_CKCORE_TLS_IE32 = 52 # macro -R_CKCORE_TLS_GD32 = 53 # macro -R_CKCORE_TLS_LDM32 = 54 # macro -R_CKCORE_TLS_LDO32 = 55 # macro -R_CKCORE_TLS_DTPMOD32 = 56 # macro -R_CKCORE_TLS_DTPOFF32 = 57 # macro -R_CKCORE_TLS_TPOFF32 = 58 # macro -EF_CSKY_ABIMASK = 0XF0000000 # macro -EF_CSKY_OTHER = 0X0FFF0000 # macro -EF_CSKY_PROCESSOR = 0X0000FFFF # macro -EF_CSKY_ABIV1 = 0X10000000 # macro -EF_CSKY_ABIV2 = 0X20000000 # macro -SHT_CSKY_ATTRIBUTES = (0x70000000+1) # macro -EF_IA_64_MASKOS = 0x0000000f # macro -EF_IA_64_ABI64 = 0x00000010 # macro -EF_IA_64_ARCH = 0xff000000 # macro -PT_IA_64_ARCHEXT = (0x70000000+0) # macro -PT_IA_64_UNWIND = (0x70000000+1) # macro -PT_IA_64_HP_OPT_ANOT = (0x60000000+0x12) # macro -PT_IA_64_HP_HSL_ANOT = (0x60000000+0x13) # macro -PT_IA_64_HP_STACK = (0x60000000+0x14) # macro -PF_IA_64_NORECOV = 0x80000000 # macro -SHT_IA_64_EXT = (0x70000000+0) # macro -SHT_IA_64_UNWIND = (0x70000000+1) # macro -SHF_IA_64_SHORT = 0x10000000 # macro -SHF_IA_64_NORECOV = 0x20000000 # macro -DT_IA_64_PLT_RESERVE = (0x70000000+0) # macro -DT_IA_64_NUM = 1 # macro -R_IA64_NONE = 0x00 # macro -R_IA64_IMM14 = 0x21 # macro -R_IA64_IMM22 = 0x22 # macro -R_IA64_IMM64 = 0x23 # macro -R_IA64_DIR32MSB = 0x24 # macro -R_IA64_DIR32LSB = 0x25 # macro -R_IA64_DIR64MSB = 0x26 # macro -R_IA64_DIR64LSB = 0x27 # macro -R_IA64_GPREL22 = 0x2a # macro -R_IA64_GPREL64I = 0x2b # macro -R_IA64_GPREL32MSB = 0x2c # macro -R_IA64_GPREL32LSB = 0x2d # macro -R_IA64_GPREL64MSB = 0x2e # macro -R_IA64_GPREL64LSB = 0x2f # macro -R_IA64_LTOFF22 = 0x32 # macro -R_IA64_LTOFF64I = 0x33 # macro -R_IA64_PLTOFF22 = 0x3a # macro -R_IA64_PLTOFF64I = 0x3b # macro -R_IA64_PLTOFF64MSB = 0x3e # macro -R_IA64_PLTOFF64LSB = 0x3f # macro -R_IA64_FPTR64I = 0x43 # macro -R_IA64_FPTR32MSB = 0x44 # macro -R_IA64_FPTR32LSB = 0x45 # macro -R_IA64_FPTR64MSB = 0x46 # macro -R_IA64_FPTR64LSB = 0x47 # macro -R_IA64_PCREL60B = 0x48 # macro -R_IA64_PCREL21B = 0x49 # macro -R_IA64_PCREL21M = 0x4a # macro -R_IA64_PCREL21F = 0x4b # macro -R_IA64_PCREL32MSB = 0x4c # macro -R_IA64_PCREL32LSB = 0x4d # macro -R_IA64_PCREL64MSB = 0x4e # macro -R_IA64_PCREL64LSB = 0x4f # macro -R_IA64_LTOFF_FPTR22 = 0x52 # macro -R_IA64_LTOFF_FPTR64I = 0x53 # macro -R_IA64_LTOFF_FPTR32MSB = 0x54 # macro -R_IA64_LTOFF_FPTR32LSB = 0x55 # macro -R_IA64_LTOFF_FPTR64MSB = 0x56 # macro -R_IA64_LTOFF_FPTR64LSB = 0x57 # macro -R_IA64_SEGREL32MSB = 0x5c # macro -R_IA64_SEGREL32LSB = 0x5d # macro -R_IA64_SEGREL64MSB = 0x5e # macro -R_IA64_SEGREL64LSB = 0x5f # macro -R_IA64_SECREL32MSB = 0x64 # macro -R_IA64_SECREL32LSB = 0x65 # macro -R_IA64_SECREL64MSB = 0x66 # macro -R_IA64_SECREL64LSB = 0x67 # macro -R_IA64_REL32MSB = 0x6c # macro -R_IA64_REL32LSB = 0x6d # macro -R_IA64_REL64MSB = 0x6e # macro -R_IA64_REL64LSB = 0x6f # macro -R_IA64_LTV32MSB = 0x74 # macro -R_IA64_LTV32LSB = 0x75 # macro -R_IA64_LTV64MSB = 0x76 # macro -R_IA64_LTV64LSB = 0x77 # macro -R_IA64_PCREL21BI = 0x79 # macro -R_IA64_PCREL22 = 0x7a # macro -R_IA64_PCREL64I = 0x7b # macro -R_IA64_IPLTMSB = 0x80 # macro -R_IA64_IPLTLSB = 0x81 # macro -R_IA64_COPY = 0x84 # macro -R_IA64_SUB = 0x85 # macro -R_IA64_LTOFF22X = 0x86 # macro -R_IA64_LDXMOV = 0x87 # macro -R_IA64_TPREL14 = 0x91 # macro -R_IA64_TPREL22 = 0x92 # macro -R_IA64_TPREL64I = 0x93 # macro -R_IA64_TPREL64MSB = 0x96 # macro -R_IA64_TPREL64LSB = 0x97 # macro -R_IA64_LTOFF_TPREL22 = 0x9a # macro -R_IA64_DTPMOD64MSB = 0xa6 # macro -R_IA64_DTPMOD64LSB = 0xa7 # macro -R_IA64_LTOFF_DTPMOD22 = 0xaa # macro -R_IA64_DTPREL14 = 0xb1 # macro -R_IA64_DTPREL22 = 0xb2 # macro -R_IA64_DTPREL64I = 0xb3 # macro -R_IA64_DTPREL32MSB = 0xb4 # macro -R_IA64_DTPREL32LSB = 0xb5 # macro -R_IA64_DTPREL64MSB = 0xb6 # macro -R_IA64_DTPREL64LSB = 0xb7 # macro -R_IA64_LTOFF_DTPREL22 = 0xba # macro -EF_SH_MACH_MASK = 0x1f # macro -EF_SH_UNKNOWN = 0x0 # macro -EF_SH1 = 0x1 # macro -EF_SH2 = 0x2 # macro -EF_SH3 = 0x3 # macro -EF_SH_DSP = 0x4 # macro -EF_SH3_DSP = 0x5 # macro -EF_SH4AL_DSP = 0x6 # macro -EF_SH3E = 0x8 # macro -EF_SH4 = 0x9 # macro -EF_SH2E = 0xb # macro -EF_SH4A = 0xc # macro -EF_SH2A = 0xd # macro -EF_SH4_NOFPU = 0x10 # macro -EF_SH4A_NOFPU = 0x11 # macro -EF_SH4_NOMMU_NOFPU = 0x12 # macro -EF_SH2A_NOFPU = 0x13 # macro -EF_SH3_NOMMU = 0x14 # macro -EF_SH2A_SH4_NOFPU = 0x15 # macro -EF_SH2A_SH3_NOFPU = 0x16 # macro -EF_SH2A_SH4 = 0x17 # macro -EF_SH2A_SH3E = 0x18 # macro -R_SH_NONE = 0 # macro -R_SH_DIR32 = 1 # macro -R_SH_REL32 = 2 # macro -R_SH_DIR8WPN = 3 # macro -R_SH_IND12W = 4 # macro -R_SH_DIR8WPL = 5 # macro -R_SH_DIR8WPZ = 6 # macro -R_SH_DIR8BP = 7 # macro -R_SH_DIR8W = 8 # macro -R_SH_DIR8L = 9 # macro -R_SH_SWITCH16 = 25 # macro -R_SH_SWITCH32 = 26 # macro -R_SH_USES = 27 # macro -R_SH_COUNT = 28 # macro -R_SH_ALIGN = 29 # macro -R_SH_CODE = 30 # macro -R_SH_DATA = 31 # macro -R_SH_LABEL = 32 # macro -R_SH_SWITCH8 = 33 # macro -R_SH_GNU_VTINHERIT = 34 # macro -R_SH_GNU_VTENTRY = 35 # macro -R_SH_TLS_GD_32 = 144 # macro -R_SH_TLS_LD_32 = 145 # macro -R_SH_TLS_LDO_32 = 146 # macro -R_SH_TLS_IE_32 = 147 # macro -R_SH_TLS_LE_32 = 148 # macro -R_SH_TLS_DTPMOD32 = 149 # macro -R_SH_TLS_DTPOFF32 = 150 # macro -R_SH_TLS_TPOFF32 = 151 # macro -R_SH_GOT32 = 160 # macro -R_SH_PLT32 = 161 # macro -R_SH_COPY = 162 # macro -R_SH_GLOB_DAT = 163 # macro -R_SH_JMP_SLOT = 164 # macro -R_SH_RELATIVE = 165 # macro -R_SH_GOTOFF = 166 # macro -R_SH_GOTPC = 167 # macro -R_SH_NUM = 256 # macro -EF_S390_HIGH_GPRS = 0x00000001 # macro -R_390_NONE = 0 # macro -R_390_8 = 1 # macro -R_390_12 = 2 # macro -R_390_16 = 3 # macro -R_390_32 = 4 # macro -R_390_PC32 = 5 # macro -R_390_GOT12 = 6 # macro -R_390_GOT32 = 7 # macro -R_390_PLT32 = 8 # macro -R_390_COPY = 9 # macro -R_390_GLOB_DAT = 10 # macro -R_390_JMP_SLOT = 11 # macro -R_390_RELATIVE = 12 # macro -R_390_GOTOFF32 = 13 # macro -R_390_GOTPC = 14 # macro -R_390_GOT16 = 15 # macro -R_390_PC16 = 16 # macro -R_390_PC16DBL = 17 # macro -R_390_PLT16DBL = 18 # macro -R_390_PC32DBL = 19 # macro -R_390_PLT32DBL = 20 # macro -R_390_GOTPCDBL = 21 # macro -R_390_64 = 22 # macro -R_390_PC64 = 23 # macro -R_390_GOT64 = 24 # macro -R_390_PLT64 = 25 # macro -R_390_GOTENT = 26 # macro -R_390_GOTOFF16 = 27 # macro -R_390_GOTOFF64 = 28 # macro -R_390_GOTPLT12 = 29 # macro -R_390_GOTPLT16 = 30 # macro -R_390_GOTPLT32 = 31 # macro -R_390_GOTPLT64 = 32 # macro -R_390_GOTPLTENT = 33 # macro -R_390_PLTOFF16 = 34 # macro -R_390_PLTOFF32 = 35 # macro -R_390_PLTOFF64 = 36 # macro -R_390_TLS_LOAD = 37 # macro -R_390_TLS_GDCALL = 38 # macro -R_390_TLS_LDCALL = 39 # macro -R_390_TLS_GD32 = 40 # macro -R_390_TLS_GD64 = 41 # macro -R_390_TLS_GOTIE12 = 42 # macro -R_390_TLS_GOTIE32 = 43 # macro -R_390_TLS_GOTIE64 = 44 # macro -R_390_TLS_LDM32 = 45 # macro -R_390_TLS_LDM64 = 46 # macro -R_390_TLS_IE32 = 47 # macro -R_390_TLS_IE64 = 48 # macro -R_390_TLS_IEENT = 49 # macro -R_390_TLS_LE32 = 50 # macro -R_390_TLS_LE64 = 51 # macro -R_390_TLS_LDO32 = 52 # macro -R_390_TLS_LDO64 = 53 # macro -R_390_TLS_DTPMOD = 54 # macro -R_390_TLS_DTPOFF = 55 # macro -R_390_TLS_TPOFF = 56 # macro -R_390_20 = 57 # macro -R_390_GOT20 = 58 # macro -R_390_GOTPLT20 = 59 # macro -R_390_TLS_GOTIE20 = 60 # macro -R_390_IRELATIVE = 61 # macro -R_390_NUM = 62 # macro -R_CRIS_NONE = 0 # macro -R_CRIS_8 = 1 # macro -R_CRIS_16 = 2 # macro -R_CRIS_32 = 3 # macro -R_CRIS_8_PCREL = 4 # macro -R_CRIS_16_PCREL = 5 # macro -R_CRIS_32_PCREL = 6 # macro -R_CRIS_GNU_VTINHERIT = 7 # macro -R_CRIS_GNU_VTENTRY = 8 # macro -R_CRIS_COPY = 9 # macro -R_CRIS_GLOB_DAT = 10 # macro -R_CRIS_JUMP_SLOT = 11 # macro -R_CRIS_RELATIVE = 12 # macro -R_CRIS_16_GOT = 13 # macro -R_CRIS_32_GOT = 14 # macro -R_CRIS_16_GOTPLT = 15 # macro -R_CRIS_32_GOTPLT = 16 # macro -R_CRIS_32_GOTREL = 17 # macro -R_CRIS_32_PLT_GOTREL = 18 # macro -R_CRIS_32_PLT_PCREL = 19 # macro -R_CRIS_NUM = 20 # macro -R_X86_64_NONE = 0 # macro -R_X86_64_64 = 1 # macro -R_X86_64_PC32 = 2 # macro -R_X86_64_GOT32 = 3 # macro -R_X86_64_PLT32 = 4 # macro -R_X86_64_COPY = 5 # macro -R_X86_64_GLOB_DAT = 6 # macro -R_X86_64_JUMP_SLOT = 7 # macro -R_X86_64_RELATIVE = 8 # macro -R_X86_64_GOTPCREL = 9 # macro -R_X86_64_32 = 10 # macro -R_X86_64_32S = 11 # macro -R_X86_64_16 = 12 # macro -R_X86_64_PC16 = 13 # macro -R_X86_64_8 = 14 # macro -R_X86_64_PC8 = 15 # macro -R_X86_64_DTPMOD64 = 16 # macro -R_X86_64_DTPOFF64 = 17 # macro -R_X86_64_TPOFF64 = 18 # macro -R_X86_64_TLSGD = 19 # macro -R_X86_64_TLSLD = 20 # macro -R_X86_64_DTPOFF32 = 21 # macro -R_X86_64_GOTTPOFF = 22 # macro -R_X86_64_TPOFF32 = 23 # macro -R_X86_64_PC64 = 24 # macro -R_X86_64_GOTOFF64 = 25 # macro -R_X86_64_GOTPC32 = 26 # macro -R_X86_64_GOT64 = 27 # macro -R_X86_64_GOTPCREL64 = 28 # macro -R_X86_64_GOTPC64 = 29 # macro -R_X86_64_GOTPLT64 = 30 # macro -R_X86_64_PLTOFF64 = 31 # macro -R_X86_64_SIZE32 = 32 # macro -R_X86_64_SIZE64 = 33 # macro -R_X86_64_GOTPC32_TLSDESC = 34 # macro -R_X86_64_TLSDESC_CALL = 35 # macro -R_X86_64_TLSDESC = 36 # macro -R_X86_64_IRELATIVE = 37 # macro -R_X86_64_RELATIVE64 = 38 # macro -R_X86_64_GOTPCRELX = 41 # macro -R_X86_64_REX_GOTPCRELX = 42 # macro -R_X86_64_NUM = 43 # macro -SHT_X86_64_UNWIND = 0x70000001 # macro -DT_X86_64_PLT = (0x70000000+0) # macro -DT_X86_64_PLTSZ = (0x70000000+1) # macro -DT_X86_64_PLTENT = (0x70000000+3) # macro -DT_X86_64_NUM = 4 # macro -R_MN10300_NONE = 0 # macro -R_MN10300_32 = 1 # macro -R_MN10300_16 = 2 # macro -R_MN10300_8 = 3 # macro -R_MN10300_PCREL32 = 4 # macro -R_MN10300_PCREL16 = 5 # macro -R_MN10300_PCREL8 = 6 # macro -R_MN10300_GNU_VTINHERIT = 7 # macro -R_MN10300_GNU_VTENTRY = 8 # macro -R_MN10300_24 = 9 # macro -R_MN10300_GOTPC32 = 10 # macro -R_MN10300_GOTPC16 = 11 # macro -R_MN10300_GOTOFF32 = 12 # macro -R_MN10300_GOTOFF24 = 13 # macro -R_MN10300_GOTOFF16 = 14 # macro -R_MN10300_PLT32 = 15 # macro -R_MN10300_PLT16 = 16 # macro -R_MN10300_GOT32 = 17 # macro -R_MN10300_GOT24 = 18 # macro -R_MN10300_GOT16 = 19 # macro -R_MN10300_COPY = 20 # macro -R_MN10300_GLOB_DAT = 21 # macro -R_MN10300_JMP_SLOT = 22 # macro -R_MN10300_RELATIVE = 23 # macro -R_MN10300_TLS_GD = 24 # macro -R_MN10300_TLS_LD = 25 # macro -R_MN10300_TLS_LDO = 26 # macro -R_MN10300_TLS_GOTIE = 27 # macro -R_MN10300_TLS_IE = 28 # macro -R_MN10300_TLS_LE = 29 # macro -R_MN10300_TLS_DTPMOD = 30 # macro -R_MN10300_TLS_DTPOFF = 31 # macro -R_MN10300_TLS_TPOFF = 32 # macro -R_MN10300_SYM_DIFF = 33 # macro -R_MN10300_ALIGN = 34 # macro -R_MN10300_NUM = 35 # macro -R_M32R_NONE = 0 # macro -R_M32R_16 = 1 # macro -R_M32R_32 = 2 # macro -R_M32R_24 = 3 # macro -R_M32R_10_PCREL = 4 # macro -R_M32R_18_PCREL = 5 # macro -R_M32R_26_PCREL = 6 # macro -R_M32R_HI16_ULO = 7 # macro -R_M32R_HI16_SLO = 8 # macro -R_M32R_LO16 = 9 # macro -R_M32R_SDA16 = 10 # macro -R_M32R_GNU_VTINHERIT = 11 # macro -R_M32R_GNU_VTENTRY = 12 # macro -R_M32R_16_RELA = 33 # macro -R_M32R_32_RELA = 34 # macro -R_M32R_24_RELA = 35 # macro -R_M32R_10_PCREL_RELA = 36 # macro -R_M32R_18_PCREL_RELA = 37 # macro -R_M32R_26_PCREL_RELA = 38 # macro -R_M32R_HI16_ULO_RELA = 39 # macro -R_M32R_HI16_SLO_RELA = 40 # macro -R_M32R_LO16_RELA = 41 # macro -R_M32R_SDA16_RELA = 42 # macro -R_M32R_RELA_GNU_VTINHERIT = 43 # macro -R_M32R_RELA_GNU_VTENTRY = 44 # macro -R_M32R_REL32 = 45 # macro -R_M32R_GOT24 = 48 # macro -R_M32R_26_PLTREL = 49 # macro -R_M32R_COPY = 50 # macro -R_M32R_GLOB_DAT = 51 # macro -R_M32R_JMP_SLOT = 52 # macro -R_M32R_RELATIVE = 53 # macro -R_M32R_GOTOFF = 54 # macro -R_M32R_GOTPC24 = 55 # macro -R_M32R_GOT16_HI_ULO = 56 # macro -R_M32R_GOT16_HI_SLO = 57 # macro -R_M32R_GOT16_LO = 58 # macro -R_M32R_GOTPC_HI_ULO = 59 # macro -R_M32R_GOTPC_HI_SLO = 60 # macro -R_M32R_GOTPC_LO = 61 # macro -R_M32R_GOTOFF_HI_ULO = 62 # macro -R_M32R_GOTOFF_HI_SLO = 63 # macro -R_M32R_GOTOFF_LO = 64 # macro -R_M32R_NUM = 256 # macro -R_MICROBLAZE_NONE = 0 # macro -R_MICROBLAZE_32 = 1 # macro -R_MICROBLAZE_32_PCREL = 2 # macro -R_MICROBLAZE_64_PCREL = 3 # macro -R_MICROBLAZE_32_PCREL_LO = 4 # macro -R_MICROBLAZE_64 = 5 # macro -R_MICROBLAZE_32_LO = 6 # macro -R_MICROBLAZE_SRO32 = 7 # macro -R_MICROBLAZE_SRW32 = 8 # macro -R_MICROBLAZE_64_NONE = 9 # macro -R_MICROBLAZE_32_SYM_OP_SYM = 10 # macro -R_MICROBLAZE_GNU_VTINHERIT = 11 # macro -R_MICROBLAZE_GNU_VTENTRY = 12 # macro -R_MICROBLAZE_GOTPC_64 = 13 # macro -R_MICROBLAZE_GOT_64 = 14 # macro -R_MICROBLAZE_PLT_64 = 15 # macro -R_MICROBLAZE_REL = 16 # macro -R_MICROBLAZE_JUMP_SLOT = 17 # macro -R_MICROBLAZE_GLOB_DAT = 18 # macro -R_MICROBLAZE_GOTOFF_64 = 19 # macro -R_MICROBLAZE_GOTOFF_32 = 20 # macro -R_MICROBLAZE_COPY = 21 # macro -R_MICROBLAZE_TLS = 22 # macro -R_MICROBLAZE_TLSGD = 23 # macro -R_MICROBLAZE_TLSLD = 24 # macro -R_MICROBLAZE_TLSDTPMOD32 = 25 # macro -R_MICROBLAZE_TLSDTPREL32 = 26 # macro -R_MICROBLAZE_TLSDTPREL64 = 27 # macro -R_MICROBLAZE_TLSGOTTPREL32 = 28 # macro -R_MICROBLAZE_TLSTPREL32 = 29 # macro -DT_NIOS2_GP = 0x70000002 # macro -R_NIOS2_NONE = 0 # macro -R_NIOS2_S16 = 1 # macro -R_NIOS2_U16 = 2 # macro -R_NIOS2_PCREL16 = 3 # macro -R_NIOS2_CALL26 = 4 # macro -R_NIOS2_IMM5 = 5 # macro -R_NIOS2_CACHE_OPX = 6 # macro -R_NIOS2_IMM6 = 7 # macro -R_NIOS2_IMM8 = 8 # macro -R_NIOS2_HI16 = 9 # macro -R_NIOS2_LO16 = 10 # macro -R_NIOS2_HIADJ16 = 11 # macro -R_NIOS2_BFD_RELOC_32 = 12 # macro -R_NIOS2_BFD_RELOC_16 = 13 # macro -R_NIOS2_BFD_RELOC_8 = 14 # macro -R_NIOS2_GPREL = 15 # macro -R_NIOS2_GNU_VTINHERIT = 16 # macro -R_NIOS2_GNU_VTENTRY = 17 # macro -R_NIOS2_UJMP = 18 # macro -R_NIOS2_CJMP = 19 # macro -R_NIOS2_CALLR = 20 # macro -R_NIOS2_ALIGN = 21 # macro -R_NIOS2_GOT16 = 22 # macro -R_NIOS2_CALL16 = 23 # macro -R_NIOS2_GOTOFF_LO = 24 # macro -R_NIOS2_GOTOFF_HA = 25 # macro -R_NIOS2_PCREL_LO = 26 # macro -R_NIOS2_PCREL_HA = 27 # macro -R_NIOS2_TLS_GD16 = 28 # macro -R_NIOS2_TLS_LDM16 = 29 # macro -R_NIOS2_TLS_LDO16 = 30 # macro -R_NIOS2_TLS_IE16 = 31 # macro -R_NIOS2_TLS_LE16 = 32 # macro -R_NIOS2_TLS_DTPMOD = 33 # macro -R_NIOS2_TLS_DTPREL = 34 # macro -R_NIOS2_TLS_TPREL = 35 # macro -R_NIOS2_COPY = 36 # macro -R_NIOS2_GLOB_DAT = 37 # macro -R_NIOS2_JUMP_SLOT = 38 # macro -R_NIOS2_RELATIVE = 39 # macro -R_NIOS2_GOTOFF = 40 # macro -R_NIOS2_CALL26_NOAT = 41 # macro -R_NIOS2_GOT_LO = 42 # macro -R_NIOS2_GOT_HA = 43 # macro -R_NIOS2_CALL_LO = 44 # macro -R_NIOS2_CALL_HA = 45 # macro -R_TILEPRO_NONE = 0 # macro -R_TILEPRO_32 = 1 # macro -R_TILEPRO_16 = 2 # macro -R_TILEPRO_8 = 3 # macro -R_TILEPRO_32_PCREL = 4 # macro -R_TILEPRO_16_PCREL = 5 # macro -R_TILEPRO_8_PCREL = 6 # macro -R_TILEPRO_LO16 = 7 # macro -R_TILEPRO_HI16 = 8 # macro -R_TILEPRO_HA16 = 9 # macro -R_TILEPRO_COPY = 10 # macro -R_TILEPRO_GLOB_DAT = 11 # macro -R_TILEPRO_JMP_SLOT = 12 # macro -R_TILEPRO_RELATIVE = 13 # macro -R_TILEPRO_BROFF_X1 = 14 # macro -R_TILEPRO_JOFFLONG_X1 = 15 # macro -R_TILEPRO_JOFFLONG_X1_PLT = 16 # macro -R_TILEPRO_IMM8_X0 = 17 # macro -R_TILEPRO_IMM8_Y0 = 18 # macro -R_TILEPRO_IMM8_X1 = 19 # macro -R_TILEPRO_IMM8_Y1 = 20 # macro -R_TILEPRO_MT_IMM15_X1 = 21 # macro -R_TILEPRO_MF_IMM15_X1 = 22 # macro -R_TILEPRO_IMM16_X0 = 23 # macro -R_TILEPRO_IMM16_X1 = 24 # macro -R_TILEPRO_IMM16_X0_LO = 25 # macro -R_TILEPRO_IMM16_X1_LO = 26 # macro -R_TILEPRO_IMM16_X0_HI = 27 # macro -R_TILEPRO_IMM16_X1_HI = 28 # macro -R_TILEPRO_IMM16_X0_HA = 29 # macro -R_TILEPRO_IMM16_X1_HA = 30 # macro -R_TILEPRO_IMM16_X0_PCREL = 31 # macro -R_TILEPRO_IMM16_X1_PCREL = 32 # macro -R_TILEPRO_IMM16_X0_LO_PCREL = 33 # macro -R_TILEPRO_IMM16_X1_LO_PCREL = 34 # macro -R_TILEPRO_IMM16_X0_HI_PCREL = 35 # macro -R_TILEPRO_IMM16_X1_HI_PCREL = 36 # macro -R_TILEPRO_IMM16_X0_HA_PCREL = 37 # macro -R_TILEPRO_IMM16_X1_HA_PCREL = 38 # macro -R_TILEPRO_IMM16_X0_GOT = 39 # macro -R_TILEPRO_IMM16_X1_GOT = 40 # macro -R_TILEPRO_IMM16_X0_GOT_LO = 41 # macro -R_TILEPRO_IMM16_X1_GOT_LO = 42 # macro -R_TILEPRO_IMM16_X0_GOT_HI = 43 # macro -R_TILEPRO_IMM16_X1_GOT_HI = 44 # macro -R_TILEPRO_IMM16_X0_GOT_HA = 45 # macro -R_TILEPRO_IMM16_X1_GOT_HA = 46 # macro -R_TILEPRO_MMSTART_X0 = 47 # macro -R_TILEPRO_MMEND_X0 = 48 # macro -R_TILEPRO_MMSTART_X1 = 49 # macro -R_TILEPRO_MMEND_X1 = 50 # macro -R_TILEPRO_SHAMT_X0 = 51 # macro -R_TILEPRO_SHAMT_X1 = 52 # macro -R_TILEPRO_SHAMT_Y0 = 53 # macro -R_TILEPRO_SHAMT_Y1 = 54 # macro -R_TILEPRO_DEST_IMM8_X1 = 55 # macro -R_TILEPRO_TLS_GD_CALL = 60 # macro -R_TILEPRO_IMM8_X0_TLS_GD_ADD = 61 # macro -R_TILEPRO_IMM8_X1_TLS_GD_ADD = 62 # macro -R_TILEPRO_IMM8_Y0_TLS_GD_ADD = 63 # macro -R_TILEPRO_IMM8_Y1_TLS_GD_ADD = 64 # macro -R_TILEPRO_TLS_IE_LOAD = 65 # macro -R_TILEPRO_IMM16_X0_TLS_GD = 66 # macro -R_TILEPRO_IMM16_X1_TLS_GD = 67 # macro -R_TILEPRO_IMM16_X0_TLS_GD_LO = 68 # macro -R_TILEPRO_IMM16_X1_TLS_GD_LO = 69 # macro -R_TILEPRO_IMM16_X0_TLS_GD_HI = 70 # macro -R_TILEPRO_IMM16_X1_TLS_GD_HI = 71 # macro -R_TILEPRO_IMM16_X0_TLS_GD_HA = 72 # macro -R_TILEPRO_IMM16_X1_TLS_GD_HA = 73 # macro -R_TILEPRO_IMM16_X0_TLS_IE = 74 # macro -R_TILEPRO_IMM16_X1_TLS_IE = 75 # macro -R_TILEPRO_IMM16_X0_TLS_IE_LO = 76 # macro -R_TILEPRO_IMM16_X1_TLS_IE_LO = 77 # macro -R_TILEPRO_IMM16_X0_TLS_IE_HI = 78 # macro -R_TILEPRO_IMM16_X1_TLS_IE_HI = 79 # macro -R_TILEPRO_IMM16_X0_TLS_IE_HA = 80 # macro -R_TILEPRO_IMM16_X1_TLS_IE_HA = 81 # macro -R_TILEPRO_TLS_DTPMOD32 = 82 # macro -R_TILEPRO_TLS_DTPOFF32 = 83 # macro -R_TILEPRO_TLS_TPOFF32 = 84 # macro -R_TILEPRO_IMM16_X0_TLS_LE = 85 # macro -R_TILEPRO_IMM16_X1_TLS_LE = 86 # macro -R_TILEPRO_IMM16_X0_TLS_LE_LO = 87 # macro -R_TILEPRO_IMM16_X1_TLS_LE_LO = 88 # macro -R_TILEPRO_IMM16_X0_TLS_LE_HI = 89 # macro -R_TILEPRO_IMM16_X1_TLS_LE_HI = 90 # macro -R_TILEPRO_IMM16_X0_TLS_LE_HA = 91 # macro -R_TILEPRO_IMM16_X1_TLS_LE_HA = 92 # macro -R_TILEPRO_GNU_VTINHERIT = 128 # macro -R_TILEPRO_GNU_VTENTRY = 129 # macro -R_TILEPRO_NUM = 130 # macro -R_TILEGX_NONE = 0 # macro -R_TILEGX_64 = 1 # macro -R_TILEGX_32 = 2 # macro -R_TILEGX_16 = 3 # macro -R_TILEGX_8 = 4 # macro -R_TILEGX_64_PCREL = 5 # macro -R_TILEGX_32_PCREL = 6 # macro -R_TILEGX_16_PCREL = 7 # macro -R_TILEGX_8_PCREL = 8 # macro -R_TILEGX_HW0 = 9 # macro -R_TILEGX_HW1 = 10 # macro -R_TILEGX_HW2 = 11 # macro -R_TILEGX_HW3 = 12 # macro -R_TILEGX_HW0_LAST = 13 # macro -R_TILEGX_HW1_LAST = 14 # macro -R_TILEGX_HW2_LAST = 15 # macro -R_TILEGX_COPY = 16 # macro -R_TILEGX_GLOB_DAT = 17 # macro -R_TILEGX_JMP_SLOT = 18 # macro -R_TILEGX_RELATIVE = 19 # macro -R_TILEGX_BROFF_X1 = 20 # macro -R_TILEGX_JUMPOFF_X1 = 21 # macro -R_TILEGX_JUMPOFF_X1_PLT = 22 # macro -R_TILEGX_IMM8_X0 = 23 # macro -R_TILEGX_IMM8_Y0 = 24 # macro -R_TILEGX_IMM8_X1 = 25 # macro -R_TILEGX_IMM8_Y1 = 26 # macro -R_TILEGX_DEST_IMM8_X1 = 27 # macro -R_TILEGX_MT_IMM14_X1 = 28 # macro -R_TILEGX_MF_IMM14_X1 = 29 # macro -R_TILEGX_MMSTART_X0 = 30 # macro -R_TILEGX_MMEND_X0 = 31 # macro -R_TILEGX_SHAMT_X0 = 32 # macro -R_TILEGX_SHAMT_X1 = 33 # macro -R_TILEGX_SHAMT_Y0 = 34 # macro -R_TILEGX_SHAMT_Y1 = 35 # macro -R_TILEGX_IMM16_X0_HW0 = 36 # macro -R_TILEGX_IMM16_X1_HW0 = 37 # macro -R_TILEGX_IMM16_X0_HW1 = 38 # macro -R_TILEGX_IMM16_X1_HW1 = 39 # macro -R_TILEGX_IMM16_X0_HW2 = 40 # macro -R_TILEGX_IMM16_X1_HW2 = 41 # macro -R_TILEGX_IMM16_X0_HW3 = 42 # macro -R_TILEGX_IMM16_X1_HW3 = 43 # macro -R_TILEGX_IMM16_X0_HW0_LAST = 44 # macro -R_TILEGX_IMM16_X1_HW0_LAST = 45 # macro -R_TILEGX_IMM16_X0_HW1_LAST = 46 # macro -R_TILEGX_IMM16_X1_HW1_LAST = 47 # macro -R_TILEGX_IMM16_X0_HW2_LAST = 48 # macro -R_TILEGX_IMM16_X1_HW2_LAST = 49 # macro -R_TILEGX_IMM16_X0_HW0_PCREL = 50 # macro -R_TILEGX_IMM16_X1_HW0_PCREL = 51 # macro -R_TILEGX_IMM16_X0_HW1_PCREL = 52 # macro -R_TILEGX_IMM16_X1_HW1_PCREL = 53 # macro -R_TILEGX_IMM16_X0_HW2_PCREL = 54 # macro -R_TILEGX_IMM16_X1_HW2_PCREL = 55 # macro -R_TILEGX_IMM16_X0_HW3_PCREL = 56 # macro -R_TILEGX_IMM16_X1_HW3_PCREL = 57 # macro -R_TILEGX_IMM16_X0_HW0_LAST_PCREL = 58 # macro -R_TILEGX_IMM16_X1_HW0_LAST_PCREL = 59 # macro -R_TILEGX_IMM16_X0_HW1_LAST_PCREL = 60 # macro -R_TILEGX_IMM16_X1_HW1_LAST_PCREL = 61 # macro -R_TILEGX_IMM16_X0_HW2_LAST_PCREL = 62 # macro -R_TILEGX_IMM16_X1_HW2_LAST_PCREL = 63 # macro -R_TILEGX_IMM16_X0_HW0_GOT = 64 # macro -R_TILEGX_IMM16_X1_HW0_GOT = 65 # macro -R_TILEGX_IMM16_X0_HW0_PLT_PCREL = 66 # macro -R_TILEGX_IMM16_X1_HW0_PLT_PCREL = 67 # macro -R_TILEGX_IMM16_X0_HW1_PLT_PCREL = 68 # macro -R_TILEGX_IMM16_X1_HW1_PLT_PCREL = 69 # macro -R_TILEGX_IMM16_X0_HW2_PLT_PCREL = 70 # macro -R_TILEGX_IMM16_X1_HW2_PLT_PCREL = 71 # macro -R_TILEGX_IMM16_X0_HW0_LAST_GOT = 72 # macro -R_TILEGX_IMM16_X1_HW0_LAST_GOT = 73 # macro -R_TILEGX_IMM16_X0_HW1_LAST_GOT = 74 # macro -R_TILEGX_IMM16_X1_HW1_LAST_GOT = 75 # macro -R_TILEGX_IMM16_X0_HW3_PLT_PCREL = 76 # macro -R_TILEGX_IMM16_X1_HW3_PLT_PCREL = 77 # macro -R_TILEGX_IMM16_X0_HW0_TLS_GD = 78 # macro -R_TILEGX_IMM16_X1_HW0_TLS_GD = 79 # macro -R_TILEGX_IMM16_X0_HW0_TLS_LE = 80 # macro -R_TILEGX_IMM16_X1_HW0_TLS_LE = 81 # macro -R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE = 82 # macro -R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE = 83 # macro -R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE = 84 # macro -R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE = 85 # macro -R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD = 86 # macro -R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD = 87 # macro -R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD = 88 # macro -R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD = 89 # macro -R_TILEGX_IMM16_X0_HW0_TLS_IE = 92 # macro -R_TILEGX_IMM16_X1_HW0_TLS_IE = 93 # macro -R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL = 94 # macro -R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL = 95 # macro -R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL = 96 # macro -R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL = 97 # macro -R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL = 98 # macro -R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL = 99 # macro -R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE = 100 # macro -R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE = 101 # macro -R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE = 102 # macro -R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE = 103 # macro -R_TILEGX_TLS_DTPMOD64 = 106 # macro -R_TILEGX_TLS_DTPOFF64 = 107 # macro -R_TILEGX_TLS_TPOFF64 = 108 # macro -R_TILEGX_TLS_DTPMOD32 = 109 # macro -R_TILEGX_TLS_DTPOFF32 = 110 # macro -R_TILEGX_TLS_TPOFF32 = 111 # macro -R_TILEGX_TLS_GD_CALL = 112 # macro -R_TILEGX_IMM8_X0_TLS_GD_ADD = 113 # macro -R_TILEGX_IMM8_X1_TLS_GD_ADD = 114 # macro -R_TILEGX_IMM8_Y0_TLS_GD_ADD = 115 # macro -R_TILEGX_IMM8_Y1_TLS_GD_ADD = 116 # macro -R_TILEGX_TLS_IE_LOAD = 117 # macro -R_TILEGX_IMM8_X0_TLS_ADD = 118 # macro -R_TILEGX_IMM8_X1_TLS_ADD = 119 # macro -R_TILEGX_IMM8_Y0_TLS_ADD = 120 # macro -R_TILEGX_IMM8_Y1_TLS_ADD = 121 # macro -R_TILEGX_GNU_VTINHERIT = 128 # macro -R_TILEGX_GNU_VTENTRY = 129 # macro -R_TILEGX_NUM = 130 # macro -EF_RISCV_RVC = 0x0001 # macro -EF_RISCV_FLOAT_ABI = 0x0006 # macro -EF_RISCV_FLOAT_ABI_SOFT = 0x0000 # macro -EF_RISCV_FLOAT_ABI_SINGLE = 0x0002 # macro -EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004 # macro -EF_RISCV_FLOAT_ABI_QUAD = 0x0006 # macro -EF_RISCV_RVE = 0x0008 # macro -EF_RISCV_TSO = 0x0010 # macro -R_RISCV_NONE = 0 # macro -R_RISCV_32 = 1 # macro -R_RISCV_64 = 2 # macro -R_RISCV_RELATIVE = 3 # macro -R_RISCV_COPY = 4 # macro -R_RISCV_JUMP_SLOT = 5 # macro -R_RISCV_TLS_DTPMOD32 = 6 # macro -R_RISCV_TLS_DTPMOD64 = 7 # macro -R_RISCV_TLS_DTPREL32 = 8 # macro -R_RISCV_TLS_DTPREL64 = 9 # macro -R_RISCV_TLS_TPREL32 = 10 # macro -R_RISCV_TLS_TPREL64 = 11 # macro -R_RISCV_BRANCH = 16 # macro -R_RISCV_JAL = 17 # macro -R_RISCV_CALL = 18 # macro -R_RISCV_CALL_PLT = 19 # macro -R_RISCV_GOT_HI20 = 20 # macro -R_RISCV_TLS_GOT_HI20 = 21 # macro -R_RISCV_TLS_GD_HI20 = 22 # macro -R_RISCV_PCREL_HI20 = 23 # macro -R_RISCV_PCREL_LO12_I = 24 # macro -R_RISCV_PCREL_LO12_S = 25 # macro -R_RISCV_HI20 = 26 # macro -R_RISCV_LO12_I = 27 # macro -R_RISCV_LO12_S = 28 # macro -R_RISCV_TPREL_HI20 = 29 # macro -R_RISCV_TPREL_LO12_I = 30 # macro -R_RISCV_TPREL_LO12_S = 31 # macro -R_RISCV_TPREL_ADD = 32 # macro -R_RISCV_ADD8 = 33 # macro -R_RISCV_ADD16 = 34 # macro -R_RISCV_ADD32 = 35 # macro -R_RISCV_ADD64 = 36 # macro -R_RISCV_SUB8 = 37 # macro -R_RISCV_SUB16 = 38 # macro -R_RISCV_SUB32 = 39 # macro -R_RISCV_SUB64 = 40 # macro -R_RISCV_GNU_VTINHERIT = 41 # macro -R_RISCV_GNU_VTENTRY = 42 # macro -R_RISCV_ALIGN = 43 # macro -R_RISCV_RVC_BRANCH = 44 # macro -R_RISCV_RVC_JUMP = 45 # macro -R_RISCV_RVC_LUI = 46 # macro -R_RISCV_GPREL_I = 47 # macro -R_RISCV_GPREL_S = 48 # macro -R_RISCV_TPREL_I = 49 # macro -R_RISCV_TPREL_S = 50 # macro -R_RISCV_RELAX = 51 # macro -R_RISCV_SUB6 = 52 # macro -R_RISCV_SET6 = 53 # macro -R_RISCV_SET8 = 54 # macro -R_RISCV_SET16 = 55 # macro -R_RISCV_SET32 = 56 # macro -R_RISCV_32_PCREL = 57 # macro -R_RISCV_IRELATIVE = 58 # macro -R_RISCV_PLT32 = 59 # macro -R_RISCV_SET_ULEB128 = 60 # macro -R_RISCV_SUB_ULEB128 = 61 # macro -R_RISCV_NUM = 62 # macro -STO_RISCV_VARIANT_CC = 0x80 # macro -SHT_RISCV_ATTRIBUTES = (0x70000000+3) # macro -PT_RISCV_ATTRIBUTES = (0x70000000+3) # macro -DT_RISCV_VARIANT_CC = (0x70000000+1) # macro -R_BPF_NONE = 0 # macro -R_BPF_64_64 = 1 # macro -R_BPF_64_32 = 10 # macro -R_METAG_HIADDR16 = 0 # macro -R_METAG_LOADDR16 = 1 # macro -R_METAG_ADDR32 = 2 # macro -R_METAG_NONE = 3 # macro -R_METAG_RELBRANCH = 4 # macro -R_METAG_GETSETOFF = 5 # macro -R_METAG_REG32OP1 = 6 # macro -R_METAG_REG32OP2 = 7 # macro -R_METAG_REG32OP3 = 8 # macro -R_METAG_REG16OP1 = 9 # macro -R_METAG_REG16OP2 = 10 # macro -R_METAG_REG16OP3 = 11 # macro -R_METAG_REG32OP4 = 12 # macro -R_METAG_HIOG = 13 # macro -R_METAG_LOOG = 14 # macro -R_METAG_REL8 = 15 # macro -R_METAG_REL16 = 16 # macro -R_METAG_GNU_VTINHERIT = 30 # macro -R_METAG_GNU_VTENTRY = 31 # macro -R_METAG_HI16_GOTOFF = 32 # macro -R_METAG_LO16_GOTOFF = 33 # macro -R_METAG_GETSET_GOTOFF = 34 # macro -R_METAG_GETSET_GOT = 35 # macro -R_METAG_HI16_GOTPC = 36 # macro -R_METAG_LO16_GOTPC = 37 # macro -R_METAG_HI16_PLT = 38 # macro -R_METAG_LO16_PLT = 39 # macro -R_METAG_RELBRANCH_PLT = 40 # macro -R_METAG_GOTOFF = 41 # macro -R_METAG_PLT = 42 # macro -R_METAG_COPY = 43 # macro -R_METAG_JMP_SLOT = 44 # macro -R_METAG_RELATIVE = 45 # macro -R_METAG_GLOB_DAT = 46 # macro -R_METAG_TLS_GD = 47 # macro -R_METAG_TLS_LDM = 48 # macro -R_METAG_TLS_LDO_HI16 = 49 # macro -R_METAG_TLS_LDO_LO16 = 50 # macro -R_METAG_TLS_LDO = 51 # macro -R_METAG_TLS_IE = 52 # macro -R_METAG_TLS_IENONPIC = 53 # macro -R_METAG_TLS_IENONPIC_HI16 = 54 # macro -R_METAG_TLS_IENONPIC_LO16 = 55 # macro -R_METAG_TLS_TPOFF = 56 # macro -R_METAG_TLS_DTPMOD = 57 # macro -R_METAG_TLS_DTPOFF = 58 # macro -R_METAG_TLS_LE = 59 # macro -R_METAG_TLS_LE_HI16 = 60 # macro -R_METAG_TLS_LE_LO16 = 61 # macro -R_NDS32_NONE = 0 # macro -R_NDS32_32_RELA = 20 # macro -R_NDS32_COPY = 39 # macro -R_NDS32_GLOB_DAT = 40 # macro -R_NDS32_JMP_SLOT = 41 # macro -R_NDS32_RELATIVE = 42 # macro -R_NDS32_TLS_TPOFF = 102 # macro -R_NDS32_TLS_DESC = 119 # macro -EF_LARCH_ABI_MODIFIER_MASK = 0x07 # macro -EF_LARCH_ABI_SOFT_FLOAT = 0x01 # macro -EF_LARCH_ABI_SINGLE_FLOAT = 0x02 # macro -EF_LARCH_ABI_DOUBLE_FLOAT = 0x03 # macro -EF_LARCH_OBJABI_V1 = 0x40 # macro -R_LARCH_NONE = 0 # macro -R_LARCH_32 = 1 # macro -R_LARCH_64 = 2 # macro -R_LARCH_RELATIVE = 3 # macro -R_LARCH_COPY = 4 # macro -R_LARCH_JUMP_SLOT = 5 # macro -R_LARCH_TLS_DTPMOD32 = 6 # macro -R_LARCH_TLS_DTPMOD64 = 7 # macro -R_LARCH_TLS_DTPREL32 = 8 # macro -R_LARCH_TLS_DTPREL64 = 9 # macro -R_LARCH_TLS_TPREL32 = 10 # macro -R_LARCH_TLS_TPREL64 = 11 # macro -R_LARCH_IRELATIVE = 12 # macro -R_LARCH_MARK_LA = 20 # macro -R_LARCH_MARK_PCREL = 21 # macro -R_LARCH_SOP_PUSH_PCREL = 22 # macro -R_LARCH_SOP_PUSH_ABSOLUTE = 23 # macro -R_LARCH_SOP_PUSH_DUP = 24 # macro -R_LARCH_SOP_PUSH_GPREL = 25 # macro -R_LARCH_SOP_PUSH_TLS_TPREL = 26 # macro -R_LARCH_SOP_PUSH_TLS_GOT = 27 # macro -R_LARCH_SOP_PUSH_TLS_GD = 28 # macro -R_LARCH_SOP_PUSH_PLT_PCREL = 29 # macro -R_LARCH_SOP_ASSERT = 30 # macro -R_LARCH_SOP_NOT = 31 # macro -R_LARCH_SOP_SUB = 32 # macro -R_LARCH_SOP_SL = 33 # macro -R_LARCH_SOP_SR = 34 # macro -R_LARCH_SOP_ADD = 35 # macro -R_LARCH_SOP_AND = 36 # macro -R_LARCH_SOP_IF_ELSE = 37 # macro -R_LARCH_SOP_POP_32_S_10_5 = 38 # macro -R_LARCH_SOP_POP_32_U_10_12 = 39 # macro -R_LARCH_SOP_POP_32_S_10_12 = 40 # macro -R_LARCH_SOP_POP_32_S_10_16 = 41 # macro -R_LARCH_SOP_POP_32_S_10_16_S2 = 42 # macro -R_LARCH_SOP_POP_32_S_5_20 = 43 # macro -R_LARCH_SOP_POP_32_S_0_5_10_16_S2 = 44 # macro -R_LARCH_SOP_POP_32_S_0_10_10_16_S2 = 45 # macro -R_LARCH_SOP_POP_32_U = 46 # macro -R_LARCH_ADD8 = 47 # macro -R_LARCH_ADD16 = 48 # macro -R_LARCH_ADD24 = 49 # macro -R_LARCH_ADD32 = 50 # macro -R_LARCH_ADD64 = 51 # macro -R_LARCH_SUB8 = 52 # macro -R_LARCH_SUB16 = 53 # macro -R_LARCH_SUB24 = 54 # macro -R_LARCH_SUB32 = 55 # macro -R_LARCH_SUB64 = 56 # macro -R_LARCH_GNU_VTINHERIT = 57 # macro -R_LARCH_GNU_VTENTRY = 58 # macro -R_LARCH_B16 = 64 # macro -R_LARCH_B21 = 65 # macro -R_LARCH_B26 = 66 # macro -R_LARCH_ABS_HI20 = 67 # macro -R_LARCH_ABS_LO12 = 68 # macro -R_LARCH_ABS64_LO20 = 69 # macro -R_LARCH_ABS64_HI12 = 70 # macro -R_LARCH_PCALA_HI20 = 71 # macro -R_LARCH_PCALA_LO12 = 72 # macro -R_LARCH_PCALA64_LO20 = 73 # macro -R_LARCH_PCALA64_HI12 = 74 # macro -R_LARCH_GOT_PC_HI20 = 75 # macro -R_LARCH_GOT_PC_LO12 = 76 # macro -R_LARCH_GOT64_PC_LO20 = 77 # macro -R_LARCH_GOT64_PC_HI12 = 78 # macro -R_LARCH_GOT_HI20 = 79 # macro -R_LARCH_GOT_LO12 = 80 # macro -R_LARCH_GOT64_LO20 = 81 # macro -R_LARCH_GOT64_HI12 = 82 # macro -R_LARCH_TLS_LE_HI20 = 83 # macro -R_LARCH_TLS_LE_LO12 = 84 # macro -R_LARCH_TLS_LE64_LO20 = 85 # macro -R_LARCH_TLS_LE64_HI12 = 86 # macro -R_LARCH_TLS_IE_PC_HI20 = 87 # macro -R_LARCH_TLS_IE_PC_LO12 = 88 # macro -R_LARCH_TLS_IE64_PC_LO20 = 89 # macro -R_LARCH_TLS_IE64_PC_HI12 = 90 # macro -R_LARCH_TLS_IE_HI20 = 91 # macro -R_LARCH_TLS_IE_LO12 = 92 # macro -R_LARCH_TLS_IE64_LO20 = 93 # macro -R_LARCH_TLS_IE64_HI12 = 94 # macro -R_LARCH_TLS_LD_PC_HI20 = 95 # macro -R_LARCH_TLS_LD_HI20 = 96 # macro -R_LARCH_TLS_GD_PC_HI20 = 97 # macro -R_LARCH_TLS_GD_HI20 = 98 # macro -R_LARCH_32_PCREL = 99 # macro -R_LARCH_RELAX = 100 # macro -R_LARCH_DELETE = 101 # macro -R_LARCH_ALIGN = 102 # macro -R_LARCH_PCREL20_S2 = 103 # macro -R_LARCH_CFA = 104 # macro -R_LARCH_ADD6 = 105 # macro -R_LARCH_SUB6 = 106 # macro -R_LARCH_ADD_ULEB128 = 107 # macro -R_LARCH_SUB_ULEB128 = 108 # macro -R_LARCH_64_PCREL = 109 # macro -EF_ARC_MACH_MSK = 0x000000ff # macro -EF_ARC_OSABI_MSK = 0x00000f00 # macro -EF_ARC_ALL_MSK = (0x000000ff|0x00000f00) # macro -SHT_ARC_ATTRIBUTES = (0x70000000+1) # macro -R_ARC_NONE = 0x0 # macro -R_ARC_8 = 0x1 # macro -R_ARC_16 = 0x2 # macro -R_ARC_24 = 0x3 # macro -R_ARC_32 = 0x4 # macro -R_ARC_B22_PCREL = 0x6 # macro -R_ARC_H30 = 0x7 # macro -R_ARC_N8 = 0x8 # macro -R_ARC_N16 = 0x9 # macro -R_ARC_N24 = 0xA # macro -R_ARC_N32 = 0xB # macro -R_ARC_SDA = 0xC # macro -R_ARC_SECTOFF = 0xD # macro -R_ARC_S21H_PCREL = 0xE # macro -R_ARC_S21W_PCREL = 0xF # macro -R_ARC_S25H_PCREL = 0x10 # macro -R_ARC_S25W_PCREL = 0x11 # macro -R_ARC_SDA32 = 0x12 # macro -R_ARC_SDA_LDST = 0x13 # macro -R_ARC_SDA_LDST1 = 0x14 # macro -R_ARC_SDA_LDST2 = 0x15 # macro -R_ARC_SDA16_LD = 0x16 # macro -R_ARC_SDA16_LD1 = 0x17 # macro -R_ARC_SDA16_LD2 = 0x18 # macro -R_ARC_S13_PCREL = 0x19 # macro -R_ARC_W = 0x1A # macro -R_ARC_32_ME = 0x1B # macro -R_ARC_N32_ME = 0x1C # macro -R_ARC_SECTOFF_ME = 0x1D # macro -R_ARC_SDA32_ME = 0x1E # macro -R_ARC_W_ME = 0x1F # macro -R_ARC_H30_ME = 0x20 # macro -R_ARC_SECTOFF_U8 = 0x21 # macro -R_ARC_SECTOFF_S9 = 0x22 # macro -R_AC_SECTOFF_U8 = 0x23 # macro -R_AC_SECTOFF_U8_1 = 0x24 # macro -R_AC_SECTOFF_U8_2 = 0x25 # macro -R_AC_SECTOFF_S9 = 0x26 # macro -R_AC_SECTOFF_S9_1 = 0x27 # macro -R_AC_SECTOFF_S9_2 = 0x28 # macro -R_ARC_SECTOFF_ME_1 = 0x29 # macro -R_ARC_SECTOFF_ME_2 = 0x2A # macro -R_ARC_SECTOFF_1 = 0x2B # macro -R_ARC_SECTOFF_2 = 0x2C # macro -R_ARC_SDA_12 = 0x2D # macro -R_ARC_SDA16_ST2 = 0x30 # macro -R_ARC_32_PCREL = 0x31 # macro -R_ARC_PC32 = 0x32 # macro -R_ARC_GOTPC32 = 0x33 # macro -R_ARC_PLT32 = 0x34 # macro -R_ARC_COPY = 0x35 # macro -R_ARC_GLOB_DAT = 0x36 # macro -R_ARC_JMP_SLOT = 0x37 # macro -R_ARC_RELATIVE = 0x38 # macro -R_ARC_GOTOFF = 0x39 # macro -R_ARC_GOTPC = 0x3A # macro -R_ARC_GOT32 = 0x3B # macro -R_ARC_S21W_PCREL_PLT = 0x3C # macro -R_ARC_S25H_PCREL_PLT = 0x3D # macro -R_ARC_JLI_SECTOFF = 0x3F # macro -R_ARC_TLS_DTPMOD = 0x42 # macro -R_ARC_TLS_DTPOFF = 0x43 # macro -R_ARC_TLS_TPOFF = 0x44 # macro -R_ARC_TLS_GD_GOT = 0x45 # macro -R_ARC_TLS_GD_LD = 0x46 # macro -R_ARC_TLS_GD_CALL = 0x47 # macro -R_ARC_TLS_IE_GOT = 0x48 # macro -R_ARC_TLS_DTPOFF_S9 = 0x49 # macro -R_ARC_TLS_LE_S9 = 0x4A # macro -R_ARC_TLS_LE_32 = 0x4B # macro -R_ARC_S25W_PCREL_PLT = 0x4C # macro -R_ARC_S21H_PCREL_PLT = 0x4D # macro -R_ARC_NPS_CMEM16 = 0x4E # macro -R_OR1K_NONE = 0 # macro -R_OR1K_32 = 1 # macro -R_OR1K_16 = 2 # macro -R_OR1K_8 = 3 # macro -R_OR1K_LO_16_IN_INSN = 4 # macro -R_OR1K_HI_16_IN_INSN = 5 # macro -R_OR1K_INSN_REL_26 = 6 # macro -R_OR1K_GNU_VTENTRY = 7 # macro -R_OR1K_GNU_VTINHERIT = 8 # macro -R_OR1K_32_PCREL = 9 # macro -R_OR1K_16_PCREL = 10 # macro -R_OR1K_8_PCREL = 11 # macro -R_OR1K_GOTPC_HI16 = 12 # macro -R_OR1K_GOTPC_LO16 = 13 # macro -R_OR1K_GOT16 = 14 # macro -R_OR1K_PLT26 = 15 # macro -R_OR1K_GOTOFF_HI16 = 16 # macro -R_OR1K_GOTOFF_LO16 = 17 # macro -R_OR1K_COPY = 18 # macro -R_OR1K_GLOB_DAT = 19 # macro -R_OR1K_JMP_SLOT = 20 # macro -R_OR1K_RELATIVE = 21 # macro -R_OR1K_TLS_GD_HI16 = 22 # macro -R_OR1K_TLS_GD_LO16 = 23 # macro -R_OR1K_TLS_LDM_HI16 = 24 # macro -R_OR1K_TLS_LDM_LO16 = 25 # macro -R_OR1K_TLS_LDO_HI16 = 26 # macro -R_OR1K_TLS_LDO_LO16 = 27 # macro -R_OR1K_TLS_IE_HI16 = 28 # macro -R_OR1K_TLS_IE_LO16 = 29 # macro -R_OR1K_TLS_LE_HI16 = 30 # macro -R_OR1K_TLS_LE_LO16 = 31 # macro -R_OR1K_TLS_TPOFF = 32 # macro -R_OR1K_TLS_DTPOFF = 33 # macro -R_OR1K_TLS_DTPMOD = 34 # macro -Elf32_Half = ctypes.c_uint16 -Elf64_Half = ctypes.c_uint16 -Elf32_Word = ctypes.c_uint32 -Elf32_Sword = ctypes.c_int32 -def DT_EXTRATAGIDX(tag): # macro - return ((Elf32_Word)-((Elf32_Sword)(tag)<<1>>1)-1) -Elf64_Word = ctypes.c_uint32 -Elf64_Sword = ctypes.c_int32 -Elf32_Xword = ctypes.c_uint64 -Elf32_Sxword = ctypes.c_int64 -Elf64_Xword = ctypes.c_uint64 -def ELF64_R_INFO(sym, type): # macro - return ((((Elf64_Xword)(sym))<<32)+(type)) -Elf64_Sxword = ctypes.c_int64 -Elf32_Addr = ctypes.c_uint32 -Elf64_Addr = ctypes.c_uint64 -Elf32_Off = ctypes.c_uint32 -Elf64_Off = ctypes.c_uint64 -Elf32_Section = ctypes.c_uint16 -Elf64_Section = ctypes.c_uint16 -Elf32_Versym = ctypes.c_uint16 -Elf64_Versym = ctypes.c_uint16 -class struct_c__SA_Elf32_Ehdr(Structure): - pass - -struct_c__SA_Elf32_Ehdr._pack_ = 1 # source:False -struct_c__SA_Elf32_Ehdr._fields_ = [ - ('e_ident', ctypes.c_ubyte * 16), - ('e_type', ctypes.c_uint16), - ('e_machine', ctypes.c_uint16), - ('e_version', ctypes.c_uint32), - ('e_entry', ctypes.c_uint32), - ('e_phoff', ctypes.c_uint32), - ('e_shoff', ctypes.c_uint32), - ('e_flags', ctypes.c_uint32), - ('e_ehsize', ctypes.c_uint16), - ('e_phentsize', ctypes.c_uint16), - ('e_phnum', ctypes.c_uint16), - ('e_shentsize', ctypes.c_uint16), - ('e_shnum', ctypes.c_uint16), - ('e_shstrndx', ctypes.c_uint16), -] - -Elf32_Ehdr = struct_c__SA_Elf32_Ehdr -class struct_c__SA_Elf64_Ehdr(Structure): - pass - -struct_c__SA_Elf64_Ehdr._pack_ = 1 # source:False -struct_c__SA_Elf64_Ehdr._fields_ = [ - ('e_ident', ctypes.c_ubyte * 16), - ('e_type', ctypes.c_uint16), - ('e_machine', ctypes.c_uint16), - ('e_version', ctypes.c_uint32), - ('e_entry', ctypes.c_uint64), - ('e_phoff', ctypes.c_uint64), - ('e_shoff', ctypes.c_uint64), - ('e_flags', ctypes.c_uint32), - ('e_ehsize', ctypes.c_uint16), - ('e_phentsize', ctypes.c_uint16), - ('e_phnum', ctypes.c_uint16), - ('e_shentsize', ctypes.c_uint16), - ('e_shnum', ctypes.c_uint16), - ('e_shstrndx', ctypes.c_uint16), -] - -Elf64_Ehdr = struct_c__SA_Elf64_Ehdr -class struct_c__SA_Elf32_Shdr(Structure): - pass - -struct_c__SA_Elf32_Shdr._pack_ = 1 # source:False -struct_c__SA_Elf32_Shdr._fields_ = [ - ('sh_name', ctypes.c_uint32), - ('sh_type', ctypes.c_uint32), - ('sh_flags', ctypes.c_uint32), - ('sh_addr', ctypes.c_uint32), - ('sh_offset', ctypes.c_uint32), - ('sh_size', ctypes.c_uint32), - ('sh_link', ctypes.c_uint32), - ('sh_info', ctypes.c_uint32), - ('sh_addralign', ctypes.c_uint32), - ('sh_entsize', ctypes.c_uint32), -] - -Elf32_Shdr = struct_c__SA_Elf32_Shdr -class struct_c__SA_Elf64_Shdr(Structure): - pass - -struct_c__SA_Elf64_Shdr._pack_ = 1 # source:False -struct_c__SA_Elf64_Shdr._fields_ = [ - ('sh_name', ctypes.c_uint32), - ('sh_type', ctypes.c_uint32), - ('sh_flags', ctypes.c_uint64), - ('sh_addr', ctypes.c_uint64), - ('sh_offset', ctypes.c_uint64), - ('sh_size', ctypes.c_uint64), - ('sh_link', ctypes.c_uint32), - ('sh_info', ctypes.c_uint32), - ('sh_addralign', ctypes.c_uint64), - ('sh_entsize', ctypes.c_uint64), -] - -Elf64_Shdr = struct_c__SA_Elf64_Shdr -class struct_c__SA_Elf32_Chdr(Structure): - pass - -struct_c__SA_Elf32_Chdr._pack_ = 1 # source:False -struct_c__SA_Elf32_Chdr._fields_ = [ - ('ch_type', ctypes.c_uint32), - ('ch_size', ctypes.c_uint32), - ('ch_addralign', ctypes.c_uint32), -] - -Elf32_Chdr = struct_c__SA_Elf32_Chdr -class struct_c__SA_Elf64_Chdr(Structure): - pass - -struct_c__SA_Elf64_Chdr._pack_ = 1 # source:False -struct_c__SA_Elf64_Chdr._fields_ = [ - ('ch_type', ctypes.c_uint32), - ('ch_reserved', ctypes.c_uint32), - ('ch_size', ctypes.c_uint64), - ('ch_addralign', ctypes.c_uint64), -] - -Elf64_Chdr = struct_c__SA_Elf64_Chdr -class struct_c__SA_Elf32_Sym(Structure): - pass - -struct_c__SA_Elf32_Sym._pack_ = 1 # source:False -struct_c__SA_Elf32_Sym._fields_ = [ - ('st_name', ctypes.c_uint32), - ('st_value', ctypes.c_uint32), - ('st_size', ctypes.c_uint32), - ('st_info', ctypes.c_ubyte), - ('st_other', ctypes.c_ubyte), - ('st_shndx', ctypes.c_uint16), -] - -Elf32_Sym = struct_c__SA_Elf32_Sym -class struct_c__SA_Elf64_Sym(Structure): - pass - -struct_c__SA_Elf64_Sym._pack_ = 1 # source:False -struct_c__SA_Elf64_Sym._fields_ = [ - ('st_name', ctypes.c_uint32), - ('st_info', ctypes.c_ubyte), - ('st_other', ctypes.c_ubyte), - ('st_shndx', ctypes.c_uint16), - ('st_value', ctypes.c_uint64), - ('st_size', ctypes.c_uint64), -] - -Elf64_Sym = struct_c__SA_Elf64_Sym -class struct_c__SA_Elf32_Syminfo(Structure): - pass - -struct_c__SA_Elf32_Syminfo._pack_ = 1 # source:False -struct_c__SA_Elf32_Syminfo._fields_ = [ - ('si_boundto', ctypes.c_uint16), - ('si_flags', ctypes.c_uint16), -] - -Elf32_Syminfo = struct_c__SA_Elf32_Syminfo -class struct_c__SA_Elf64_Syminfo(Structure): - pass - -struct_c__SA_Elf64_Syminfo._pack_ = 1 # source:False -struct_c__SA_Elf64_Syminfo._fields_ = [ - ('si_boundto', ctypes.c_uint16), - ('si_flags', ctypes.c_uint16), -] - -Elf64_Syminfo = struct_c__SA_Elf64_Syminfo -class struct_c__SA_Elf32_Rel(Structure): - pass - -struct_c__SA_Elf32_Rel._pack_ = 1 # source:False -struct_c__SA_Elf32_Rel._fields_ = [ - ('r_offset', ctypes.c_uint32), - ('r_info', ctypes.c_uint32), -] - -Elf32_Rel = struct_c__SA_Elf32_Rel -class struct_c__SA_Elf64_Rel(Structure): - pass - -struct_c__SA_Elf64_Rel._pack_ = 1 # source:False -struct_c__SA_Elf64_Rel._fields_ = [ - ('r_offset', ctypes.c_uint64), - ('r_info', ctypes.c_uint64), -] - -Elf64_Rel = struct_c__SA_Elf64_Rel -class struct_c__SA_Elf32_Rela(Structure): - pass - -struct_c__SA_Elf32_Rela._pack_ = 1 # source:False -struct_c__SA_Elf32_Rela._fields_ = [ - ('r_offset', ctypes.c_uint32), - ('r_info', ctypes.c_uint32), - ('r_addend', ctypes.c_int32), -] - -Elf32_Rela = struct_c__SA_Elf32_Rela -class struct_c__SA_Elf64_Rela(Structure): - pass - -struct_c__SA_Elf64_Rela._pack_ = 1 # source:False -struct_c__SA_Elf64_Rela._fields_ = [ - ('r_offset', ctypes.c_uint64), - ('r_info', ctypes.c_uint64), - ('r_addend', ctypes.c_int64), -] - -Elf64_Rela = struct_c__SA_Elf64_Rela -Elf32_Relr = ctypes.c_uint32 -Elf64_Relr = ctypes.c_uint64 -class struct_c__SA_Elf32_Phdr(Structure): - pass - -struct_c__SA_Elf32_Phdr._pack_ = 1 # source:False -struct_c__SA_Elf32_Phdr._fields_ = [ - ('p_type', ctypes.c_uint32), - ('p_offset', ctypes.c_uint32), - ('p_vaddr', ctypes.c_uint32), - ('p_paddr', ctypes.c_uint32), - ('p_filesz', ctypes.c_uint32), - ('p_memsz', ctypes.c_uint32), - ('p_flags', ctypes.c_uint32), - ('p_align', ctypes.c_uint32), -] - -Elf32_Phdr = struct_c__SA_Elf32_Phdr -class struct_c__SA_Elf64_Phdr(Structure): - pass - -struct_c__SA_Elf64_Phdr._pack_ = 1 # source:False -struct_c__SA_Elf64_Phdr._fields_ = [ - ('p_type', ctypes.c_uint32), - ('p_flags', ctypes.c_uint32), - ('p_offset', ctypes.c_uint64), - ('p_vaddr', ctypes.c_uint64), - ('p_paddr', ctypes.c_uint64), - ('p_filesz', ctypes.c_uint64), - ('p_memsz', ctypes.c_uint64), - ('p_align', ctypes.c_uint64), -] - -Elf64_Phdr = struct_c__SA_Elf64_Phdr -class struct_c__SA_Elf32_Dyn(Structure): - pass - -class union_c__SA_Elf32_Dyn_d_un(Union): - pass - -union_c__SA_Elf32_Dyn_d_un._pack_ = 1 # source:False -union_c__SA_Elf32_Dyn_d_un._fields_ = [ - ('d_val', ctypes.c_uint32), - ('d_ptr', ctypes.c_uint32), -] - -struct_c__SA_Elf32_Dyn._pack_ = 1 # source:False -struct_c__SA_Elf32_Dyn._fields_ = [ - ('d_tag', ctypes.c_int32), - ('d_un', union_c__SA_Elf32_Dyn_d_un), -] - -Elf32_Dyn = struct_c__SA_Elf32_Dyn -class struct_c__SA_Elf64_Dyn(Structure): - pass - -class union_c__SA_Elf64_Dyn_d_un(Union): - pass - -union_c__SA_Elf64_Dyn_d_un._pack_ = 1 # source:False -union_c__SA_Elf64_Dyn_d_un._fields_ = [ - ('d_val', ctypes.c_uint64), - ('d_ptr', ctypes.c_uint64), -] - -struct_c__SA_Elf64_Dyn._pack_ = 1 # source:False -struct_c__SA_Elf64_Dyn._fields_ = [ - ('d_tag', ctypes.c_int64), - ('d_un', union_c__SA_Elf64_Dyn_d_un), -] - -Elf64_Dyn = struct_c__SA_Elf64_Dyn -class struct_c__SA_Elf32_Verdef(Structure): - pass - -struct_c__SA_Elf32_Verdef._pack_ = 1 # source:False -struct_c__SA_Elf32_Verdef._fields_ = [ - ('vd_version', ctypes.c_uint16), - ('vd_flags', ctypes.c_uint16), - ('vd_ndx', ctypes.c_uint16), - ('vd_cnt', ctypes.c_uint16), - ('vd_hash', ctypes.c_uint32), - ('vd_aux', ctypes.c_uint32), - ('vd_next', ctypes.c_uint32), -] - -Elf32_Verdef = struct_c__SA_Elf32_Verdef -class struct_c__SA_Elf64_Verdef(Structure): - pass - -struct_c__SA_Elf64_Verdef._pack_ = 1 # source:False -struct_c__SA_Elf64_Verdef._fields_ = [ - ('vd_version', ctypes.c_uint16), - ('vd_flags', ctypes.c_uint16), - ('vd_ndx', ctypes.c_uint16), - ('vd_cnt', ctypes.c_uint16), - ('vd_hash', ctypes.c_uint32), - ('vd_aux', ctypes.c_uint32), - ('vd_next', ctypes.c_uint32), -] - -Elf64_Verdef = struct_c__SA_Elf64_Verdef -class struct_c__SA_Elf32_Verdaux(Structure): - pass - -struct_c__SA_Elf32_Verdaux._pack_ = 1 # source:False -struct_c__SA_Elf32_Verdaux._fields_ = [ - ('vda_name', ctypes.c_uint32), - ('vda_next', ctypes.c_uint32), -] - -Elf32_Verdaux = struct_c__SA_Elf32_Verdaux -class struct_c__SA_Elf64_Verdaux(Structure): - pass - -struct_c__SA_Elf64_Verdaux._pack_ = 1 # source:False -struct_c__SA_Elf64_Verdaux._fields_ = [ - ('vda_name', ctypes.c_uint32), - ('vda_next', ctypes.c_uint32), -] - -Elf64_Verdaux = struct_c__SA_Elf64_Verdaux -class struct_c__SA_Elf32_Verneed(Structure): - pass - -struct_c__SA_Elf32_Verneed._pack_ = 1 # source:False -struct_c__SA_Elf32_Verneed._fields_ = [ - ('vn_version', ctypes.c_uint16), - ('vn_cnt', ctypes.c_uint16), - ('vn_file', ctypes.c_uint32), - ('vn_aux', ctypes.c_uint32), - ('vn_next', ctypes.c_uint32), -] - -Elf32_Verneed = struct_c__SA_Elf32_Verneed -class struct_c__SA_Elf64_Verneed(Structure): - pass - -struct_c__SA_Elf64_Verneed._pack_ = 1 # source:False -struct_c__SA_Elf64_Verneed._fields_ = [ - ('vn_version', ctypes.c_uint16), - ('vn_cnt', ctypes.c_uint16), - ('vn_file', ctypes.c_uint32), - ('vn_aux', ctypes.c_uint32), - ('vn_next', ctypes.c_uint32), -] - -Elf64_Verneed = struct_c__SA_Elf64_Verneed -class struct_c__SA_Elf32_Vernaux(Structure): - pass - -struct_c__SA_Elf32_Vernaux._pack_ = 1 # source:False -struct_c__SA_Elf32_Vernaux._fields_ = [ - ('vna_hash', ctypes.c_uint32), - ('vna_flags', ctypes.c_uint16), - ('vna_other', ctypes.c_uint16), - ('vna_name', ctypes.c_uint32), - ('vna_next', ctypes.c_uint32), -] - -Elf32_Vernaux = struct_c__SA_Elf32_Vernaux -class struct_c__SA_Elf64_Vernaux(Structure): - pass - -struct_c__SA_Elf64_Vernaux._pack_ = 1 # source:False -struct_c__SA_Elf64_Vernaux._fields_ = [ - ('vna_hash', ctypes.c_uint32), - ('vna_flags', ctypes.c_uint16), - ('vna_other', ctypes.c_uint16), - ('vna_name', ctypes.c_uint32), - ('vna_next', ctypes.c_uint32), -] - -Elf64_Vernaux = struct_c__SA_Elf64_Vernaux -class struct_c__SA_Elf32_auxv_t(Structure): - pass - -class union_c__SA_Elf32_auxv_t_a_un(Union): - pass - -union_c__SA_Elf32_auxv_t_a_un._pack_ = 1 # source:False -union_c__SA_Elf32_auxv_t_a_un._fields_ = [ - ('a_val', ctypes.c_uint32), -] - -struct_c__SA_Elf32_auxv_t._pack_ = 1 # source:False -struct_c__SA_Elf32_auxv_t._fields_ = [ - ('a_type', ctypes.c_uint32), - ('a_un', union_c__SA_Elf32_auxv_t_a_un), -] - -Elf32_auxv_t = struct_c__SA_Elf32_auxv_t -class struct_c__SA_Elf64_auxv_t(Structure): - pass - -class union_c__SA_Elf64_auxv_t_a_un(Union): - pass - -union_c__SA_Elf64_auxv_t_a_un._pack_ = 1 # source:False -union_c__SA_Elf64_auxv_t_a_un._fields_ = [ - ('a_val', ctypes.c_uint64), -] - -struct_c__SA_Elf64_auxv_t._pack_ = 1 # source:False -struct_c__SA_Elf64_auxv_t._fields_ = [ - ('a_type', ctypes.c_uint64), - ('a_un', union_c__SA_Elf64_auxv_t_a_un), -] - -Elf64_auxv_t = struct_c__SA_Elf64_auxv_t -class struct_c__SA_Elf32_Nhdr(Structure): - pass - -struct_c__SA_Elf32_Nhdr._pack_ = 1 # source:False -struct_c__SA_Elf32_Nhdr._fields_ = [ - ('n_namesz', ctypes.c_uint32), - ('n_descsz', ctypes.c_uint32), - ('n_type', ctypes.c_uint32), -] - -Elf32_Nhdr = struct_c__SA_Elf32_Nhdr -class struct_c__SA_Elf64_Nhdr(Structure): - pass - -struct_c__SA_Elf64_Nhdr._pack_ = 1 # source:False -struct_c__SA_Elf64_Nhdr._fields_ = [ - ('n_namesz', ctypes.c_uint32), - ('n_descsz', ctypes.c_uint32), - ('n_type', ctypes.c_uint32), -] - -Elf64_Nhdr = struct_c__SA_Elf64_Nhdr -class struct_c__SA_Elf32_Move(Structure): - pass - -struct_c__SA_Elf32_Move._pack_ = 1 # source:False -struct_c__SA_Elf32_Move._fields_ = [ - ('m_value', ctypes.c_uint64), - ('m_info', ctypes.c_uint32), - ('m_poffset', ctypes.c_uint32), - ('m_repeat', ctypes.c_uint16), - ('m_stride', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -Elf32_Move = struct_c__SA_Elf32_Move -class struct_c__SA_Elf64_Move(Structure): - pass - -struct_c__SA_Elf64_Move._pack_ = 1 # source:False -struct_c__SA_Elf64_Move._fields_ = [ - ('m_value', ctypes.c_uint64), - ('m_info', ctypes.c_uint64), - ('m_poffset', ctypes.c_uint64), - ('m_repeat', ctypes.c_uint16), - ('m_stride', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -Elf64_Move = struct_c__SA_Elf64_Move -class union_c__UA_Elf32_gptab(Union): - pass - -class struct_c__UA_Elf32_gptab_gt_header(Structure): - pass - -struct_c__UA_Elf32_gptab_gt_header._pack_ = 1 # source:False -struct_c__UA_Elf32_gptab_gt_header._fields_ = [ - ('gt_current_g_value', ctypes.c_uint32), - ('gt_unused', ctypes.c_uint32), -] - -class struct_c__UA_Elf32_gptab_gt_entry(Structure): - pass - -struct_c__UA_Elf32_gptab_gt_entry._pack_ = 1 # source:False -struct_c__UA_Elf32_gptab_gt_entry._fields_ = [ - ('gt_g_value', ctypes.c_uint32), - ('gt_bytes', ctypes.c_uint32), -] - -union_c__UA_Elf32_gptab._pack_ = 1 # source:False -union_c__UA_Elf32_gptab._fields_ = [ - ('gt_header', struct_c__UA_Elf32_gptab_gt_header), - ('gt_entry', struct_c__UA_Elf32_gptab_gt_entry), -] - -Elf32_gptab = union_c__UA_Elf32_gptab -class struct_c__SA_Elf32_RegInfo(Structure): - pass - -struct_c__SA_Elf32_RegInfo._pack_ = 1 # source:False -struct_c__SA_Elf32_RegInfo._fields_ = [ - ('ri_gprmask', ctypes.c_uint32), - ('ri_cprmask', ctypes.c_uint32 * 4), - ('ri_gp_value', ctypes.c_int32), -] - -Elf32_RegInfo = struct_c__SA_Elf32_RegInfo -class struct_c__SA_Elf_Options(Structure): - pass - -struct_c__SA_Elf_Options._pack_ = 1 # source:False -struct_c__SA_Elf_Options._fields_ = [ - ('kind', ctypes.c_ubyte), - ('size', ctypes.c_ubyte), - ('section', ctypes.c_uint16), - ('info', ctypes.c_uint32), -] - -Elf_Options = struct_c__SA_Elf_Options -class struct_c__SA_Elf_Options_Hw(Structure): - pass - -struct_c__SA_Elf_Options_Hw._pack_ = 1 # source:False -struct_c__SA_Elf_Options_Hw._fields_ = [ - ('hwp_flags1', ctypes.c_uint32), - ('hwp_flags2', ctypes.c_uint32), -] - -Elf_Options_Hw = struct_c__SA_Elf_Options_Hw -class struct_c__SA_Elf32_Lib(Structure): - pass - -struct_c__SA_Elf32_Lib._pack_ = 1 # source:False -struct_c__SA_Elf32_Lib._fields_ = [ - ('l_name', ctypes.c_uint32), - ('l_time_stamp', ctypes.c_uint32), - ('l_checksum', ctypes.c_uint32), - ('l_version', ctypes.c_uint32), - ('l_flags', ctypes.c_uint32), -] - -Elf32_Lib = struct_c__SA_Elf32_Lib -class struct_c__SA_Elf64_Lib(Structure): - pass - -struct_c__SA_Elf64_Lib._pack_ = 1 # source:False -struct_c__SA_Elf64_Lib._fields_ = [ - ('l_name', ctypes.c_uint32), - ('l_time_stamp', ctypes.c_uint32), - ('l_checksum', ctypes.c_uint32), - ('l_version', ctypes.c_uint32), - ('l_flags', ctypes.c_uint32), -] - -Elf64_Lib = struct_c__SA_Elf64_Lib -Elf32_Conflict = ctypes.c_uint32 -class struct_c__SA_Elf_MIPS_ABIFlags_v0(Structure): - pass - -struct_c__SA_Elf_MIPS_ABIFlags_v0._pack_ = 1 # source:False -struct_c__SA_Elf_MIPS_ABIFlags_v0._fields_ = [ - ('version', ctypes.c_uint16), - ('isa_level', ctypes.c_ubyte), - ('isa_rev', ctypes.c_ubyte), - ('gpr_size', ctypes.c_ubyte), - ('cpr1_size', ctypes.c_ubyte), - ('cpr2_size', ctypes.c_ubyte), - ('fp_abi', ctypes.c_ubyte), - ('isa_ext', ctypes.c_uint32), - ('ases', ctypes.c_uint32), - ('flags1', ctypes.c_uint32), - ('flags2', ctypes.c_uint32), -] - -Elf_MIPS_ABIFlags_v0 = struct_c__SA_Elf_MIPS_ABIFlags_v0 - -# values for enumeration 'c__Ea_Val_GNU_MIPS_ABI_FP_ANY' -c__Ea_Val_GNU_MIPS_ABI_FP_ANY__enumvalues = { - 0: 'Val_GNU_MIPS_ABI_FP_ANY', - 1: 'Val_GNU_MIPS_ABI_FP_DOUBLE', - 2: 'Val_GNU_MIPS_ABI_FP_SINGLE', - 3: 'Val_GNU_MIPS_ABI_FP_SOFT', - 4: 'Val_GNU_MIPS_ABI_FP_OLD_64', - 5: 'Val_GNU_MIPS_ABI_FP_XX', - 6: 'Val_GNU_MIPS_ABI_FP_64', - 7: 'Val_GNU_MIPS_ABI_FP_64A', - 7: 'Val_GNU_MIPS_ABI_FP_MAX', -} -Val_GNU_MIPS_ABI_FP_ANY = 0 -Val_GNU_MIPS_ABI_FP_DOUBLE = 1 -Val_GNU_MIPS_ABI_FP_SINGLE = 2 -Val_GNU_MIPS_ABI_FP_SOFT = 3 -Val_GNU_MIPS_ABI_FP_OLD_64 = 4 -Val_GNU_MIPS_ABI_FP_XX = 5 -Val_GNU_MIPS_ABI_FP_64 = 6 -Val_GNU_MIPS_ABI_FP_64A = 7 -Val_GNU_MIPS_ABI_FP_MAX = 7 -c__Ea_Val_GNU_MIPS_ABI_FP_ANY = ctypes.c_uint32 # enum -_UNISTD_H = 1 # macro -_POSIX_VERSION = 200809 # macro -__POSIX2_THIS_VERSION = 200809 # macro -_POSIX2_VERSION = 200809 # macro -_POSIX2_C_VERSION = 200809 # macro -_POSIX2_C_BIND = 200809 # macro -_POSIX2_C_DEV = 200809 # macro -_POSIX2_SW_DEV = 200809 # macro -_POSIX2_LOCALEDEF = 200809 # macro -_XOPEN_VERSION = 700 # macro -_XOPEN_XCU_VERSION = 4 # macro -_XOPEN_XPG2 = 1 # macro -_XOPEN_XPG3 = 1 # macro -_XOPEN_XPG4 = 1 # macro -_XOPEN_UNIX = 1 # macro -_XOPEN_ENH_I18N = 1 # macro -_XOPEN_LEGACY = 1 # macro -STDIN_FILENO = 0 # macro -STDOUT_FILENO = 1 # macro -STDERR_FILENO = 2 # macro -__ssize_t_defined = True # macro -__gid_t_defined = True # macro -__uid_t_defined = True # macro -__useconds_t_defined = True # macro -__pid_t_defined = True # macro -__intptr_t_defined = True # macro -__socklen_t_defined = True # macro -R_OK = 4 # macro -W_OK = 2 # macro -X_OK = 1 # macro -F_OK = 0 # macro -SEEK_SET = 0 # macro -SEEK_CUR = 1 # macro -SEEK_END = 2 # macro -L_SET = 0 # macro -L_INCR = 1 # macro -L_XTND = 2 # macro -F_ULOCK = 0 # macro -F_LOCK = 1 # macro -F_TLOCK = 2 # macro -F_TEST = 3 # macro -ssize_t = ctypes.c_int64 -gid_t = ctypes.c_uint32 -uid_t = ctypes.c_uint32 -useconds_t = ctypes.c_uint32 -pid_t = ctypes.c_int32 -intptr_t = ctypes.c_int64 -socklen_t = ctypes.c_uint32 -try: - access = _libraries['libc'].access - access.restype = ctypes.c_int32 - access.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - faccessat = _libraries['libc'].faccessat - faccessat.restype = ctypes.c_int32 - faccessat.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - lseek = _libraries['libc'].lseek - lseek.restype = __off_t - lseek.argtypes = [ctypes.c_int32, __off_t, ctypes.c_int32] -except AttributeError: - pass -try: - close = _libraries['libc'].close - close.restype = ctypes.c_int32 - close.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - closefrom = _libraries['libc'].closefrom - closefrom.restype = None - closefrom.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - read = _libraries['libc'].read - read.restype = ssize_t - read.argtypes = [ctypes.c_int32, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - write = _libraries['libc'].write - write.restype = ssize_t - write.argtypes = [ctypes.c_int32, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - pread = _libraries['libc'].pread - pread.restype = ssize_t - pread.argtypes = [ctypes.c_int32, ctypes.POINTER(None), size_t, __off_t] -except AttributeError: - pass -try: - pwrite = _libraries['libc'].pwrite - pwrite.restype = ssize_t - pwrite.argtypes = [ctypes.c_int32, ctypes.POINTER(None), size_t, __off_t] -except AttributeError: - pass -try: - pipe = _libraries['libc'].pipe - pipe.restype = ctypes.c_int32 - pipe.argtypes = [ctypes.c_int32 * 2] -except AttributeError: - pass -try: - alarm = _libraries['libc'].alarm - alarm.restype = ctypes.c_uint32 - alarm.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - sleep = _libraries['libc'].sleep - sleep.restype = ctypes.c_uint32 - sleep.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -__useconds_t = ctypes.c_uint32 -try: - ualarm = _libraries['libc'].ualarm - ualarm.restype = __useconds_t - ualarm.argtypes = [__useconds_t, __useconds_t] -except AttributeError: - pass -try: - usleep = _libraries['libc'].usleep - usleep.restype = ctypes.c_int32 - usleep.argtypes = [__useconds_t] -except AttributeError: - pass -try: - pause = _libraries['libc'].pause - pause.restype = ctypes.c_int32 - pause.argtypes = [] -except AttributeError: - pass -__uid_t = ctypes.c_uint32 -__gid_t = ctypes.c_uint32 -try: - chown = _libraries['libc'].chown - chown.restype = ctypes.c_int32 - chown.argtypes = [ctypes.POINTER(ctypes.c_char), __uid_t, __gid_t] -except AttributeError: - pass -try: - fchown = _libraries['libc'].fchown - fchown.restype = ctypes.c_int32 - fchown.argtypes = [ctypes.c_int32, __uid_t, __gid_t] -except AttributeError: - pass -try: - lchown = _libraries['libc'].lchown - lchown.restype = ctypes.c_int32 - lchown.argtypes = [ctypes.POINTER(ctypes.c_char), __uid_t, __gid_t] -except AttributeError: - pass -try: - fchownat = _libraries['libc'].fchownat - fchownat.restype = ctypes.c_int32 - fchownat.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), __uid_t, __gid_t, ctypes.c_int32] -except AttributeError: - pass -try: - chdir = _libraries['libc'].chdir - chdir.restype = ctypes.c_int32 - chdir.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - fchdir = _libraries['libc'].fchdir - fchdir.restype = ctypes.c_int32 - fchdir.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - getcwd = _libraries['libc'].getcwd - getcwd.restype = ctypes.POINTER(ctypes.c_char) - getcwd.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - getwd = _libraries['libc'].getwd - getwd.restype = ctypes.POINTER(ctypes.c_char) - getwd.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - dup = _libraries['libc'].dup - dup.restype = ctypes.c_int32 - dup.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - dup2 = _libraries['libc'].dup2 - dup2.restype = ctypes.c_int32 - dup2.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -__environ = ctypes.POINTER(ctypes.POINTER(ctypes.c_char))() # Variable ctypes.POINTER(ctypes.POINTER(ctypes.c_char)) -try: - execve = _libraries['libc'].execve - execve.restype = ctypes.c_int32 - execve.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char) * 0, ctypes.POINTER(ctypes.c_char) * 0] -except AttributeError: - pass -try: - fexecve = _libraries['libc'].fexecve - fexecve.restype = ctypes.c_int32 - fexecve.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char) * 0, ctypes.POINTER(ctypes.c_char) * 0] -except AttributeError: - pass -try: - execv = _libraries['libc'].execv - execv.restype = ctypes.c_int32 - execv.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char) * 0] -except AttributeError: - pass -try: - execle = _libraries['libc'].execle - execle.restype = ctypes.c_int32 - execle.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - execl = _libraries['libc'].execl - execl.restype = ctypes.c_int32 - execl.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - execvp = _libraries['libc'].execvp - execvp.restype = ctypes.c_int32 - execvp.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char) * 0] -except AttributeError: - pass -try: - execlp = _libraries['libc'].execlp - execlp.restype = ctypes.c_int32 - execlp.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nice = _libraries['libc'].nice - nice.restype = ctypes.c_int32 - nice.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - _exit = _libraries['libc']._exit - _exit.restype = None - _exit.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - pathconf = _libraries['libc'].pathconf - pathconf.restype = ctypes.c_int64 - pathconf.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - fpathconf = _libraries['libc'].fpathconf - fpathconf.restype = ctypes.c_int64 - fpathconf.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - sysconf = _libraries['libc'].sysconf - sysconf.restype = ctypes.c_int64 - sysconf.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - confstr = _libraries['libc'].confstr - confstr.restype = size_t - confstr.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -__pid_t = ctypes.c_int32 -try: - getpid = _libraries['libc'].getpid - getpid.restype = __pid_t - getpid.argtypes = [] -except AttributeError: - pass -try: - getppid = _libraries['libc'].getppid - getppid.restype = __pid_t - getppid.argtypes = [] -except AttributeError: - pass -try: - getpgrp = _libraries['libc'].getpgrp - getpgrp.restype = __pid_t - getpgrp.argtypes = [] -except AttributeError: - pass -try: - __getpgid = _libraries['libc'].__getpgid - __getpgid.restype = __pid_t - __getpgid.argtypes = [__pid_t] -except AttributeError: - pass -try: - getpgid = _libraries['libc'].getpgid - getpgid.restype = __pid_t - getpgid.argtypes = [__pid_t] -except AttributeError: - pass -try: - setpgid = _libraries['libc'].setpgid - setpgid.restype = ctypes.c_int32 - setpgid.argtypes = [__pid_t, __pid_t] -except AttributeError: - pass -try: - setpgrp = _libraries['libc'].setpgrp - setpgrp.restype = ctypes.c_int32 - setpgrp.argtypes = [] -except AttributeError: - pass -try: - setsid = _libraries['libc'].setsid - setsid.restype = __pid_t - setsid.argtypes = [] -except AttributeError: - pass -try: - getsid = _libraries['libc'].getsid - getsid.restype = __pid_t - getsid.argtypes = [__pid_t] -except AttributeError: - pass -try: - getuid = _libraries['libc'].getuid - getuid.restype = __uid_t - getuid.argtypes = [] -except AttributeError: - pass -try: - geteuid = _libraries['libc'].geteuid - geteuid.restype = __uid_t - geteuid.argtypes = [] -except AttributeError: - pass -try: - getgid = _libraries['libc'].getgid - getgid.restype = __gid_t - getgid.argtypes = [] -except AttributeError: - pass -try: - getegid = _libraries['libc'].getegid - getegid.restype = __gid_t - getegid.argtypes = [] -except AttributeError: - pass -try: - getgroups = _libraries['libc'].getgroups - getgroups.restype = ctypes.c_int32 - getgroups.argtypes = [ctypes.c_int32, ctypes.c_uint32 * 0] -except AttributeError: - pass -try: - setuid = _libraries['libc'].setuid - setuid.restype = ctypes.c_int32 - setuid.argtypes = [__uid_t] -except AttributeError: - pass -try: - setreuid = _libraries['libc'].setreuid - setreuid.restype = ctypes.c_int32 - setreuid.argtypes = [__uid_t, __uid_t] -except AttributeError: - pass -try: - seteuid = _libraries['libc'].seteuid - seteuid.restype = ctypes.c_int32 - seteuid.argtypes = [__uid_t] -except AttributeError: - pass -try: - setgid = _libraries['libc'].setgid - setgid.restype = ctypes.c_int32 - setgid.argtypes = [__gid_t] -except AttributeError: - pass -try: - setregid = _libraries['libc'].setregid - setregid.restype = ctypes.c_int32 - setregid.argtypes = [__gid_t, __gid_t] -except AttributeError: - pass -try: - setegid = _libraries['libc'].setegid - setegid.restype = ctypes.c_int32 - setegid.argtypes = [__gid_t] -except AttributeError: - pass -try: - fork = _libraries['libc'].fork - fork.restype = __pid_t - fork.argtypes = [] -except AttributeError: - pass -try: - vfork = _libraries['libc'].vfork - vfork.restype = ctypes.c_int32 - vfork.argtypes = [] -except AttributeError: - pass -try: - ttyname = _libraries['libc'].ttyname - ttyname.restype = ctypes.POINTER(ctypes.c_char) - ttyname.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ttyname_r = _libraries['libc'].ttyname_r - ttyname_r.restype = ctypes.c_int32 - ttyname_r.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - isatty = _libraries['libc'].isatty - isatty.restype = ctypes.c_int32 - isatty.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ttyslot = _libraries['libc'].ttyslot - ttyslot.restype = ctypes.c_int32 - ttyslot.argtypes = [] -except AttributeError: - pass -try: - link = _libraries['libc'].link - link.restype = ctypes.c_int32 - link.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - linkat = _libraries['libc'].linkat - linkat.restype = ctypes.c_int32 - linkat.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - symlink = _libraries['libc'].symlink - symlink.restype = ctypes.c_int32 - symlink.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - readlink = _libraries['libc'].readlink - readlink.restype = ssize_t - readlink.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - symlinkat = _libraries['libc'].symlinkat - symlinkat.restype = ctypes.c_int32 - symlinkat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - readlinkat = _libraries['libc'].readlinkat - readlinkat.restype = ssize_t - readlinkat.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - unlink = _libraries['libc'].unlink - unlink.restype = ctypes.c_int32 - unlink.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - unlinkat = _libraries['libc'].unlinkat - unlinkat.restype = ctypes.c_int32 - unlinkat.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - rmdir = _libraries['libc'].rmdir - rmdir.restype = ctypes.c_int32 - rmdir.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - tcgetpgrp = _libraries['libc'].tcgetpgrp - tcgetpgrp.restype = __pid_t - tcgetpgrp.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - tcsetpgrp = _libraries['libc'].tcsetpgrp - tcsetpgrp.restype = ctypes.c_int32 - tcsetpgrp.argtypes = [ctypes.c_int32, __pid_t] -except AttributeError: - pass -try: - getlogin = _libraries['libc'].getlogin - getlogin.restype = ctypes.POINTER(ctypes.c_char) - getlogin.argtypes = [] -except AttributeError: - pass -try: - getlogin_r = _libraries['libc'].getlogin_r - getlogin_r.restype = ctypes.c_int32 - getlogin_r.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - setlogin = _libraries['libc'].setlogin - setlogin.restype = ctypes.c_int32 - setlogin.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - gethostname = _libraries['libc'].gethostname - gethostname.restype = ctypes.c_int32 - gethostname.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - sethostname = _libraries['libc'].sethostname - sethostname.restype = ctypes.c_int32 - sethostname.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - sethostid = _libraries['libc'].sethostid - sethostid.restype = ctypes.c_int32 - sethostid.argtypes = [ctypes.c_int64] -except AttributeError: - pass -try: - getdomainname = _libraries['libc'].getdomainname - getdomainname.restype = ctypes.c_int32 - getdomainname.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - setdomainname = _libraries['libc'].setdomainname - setdomainname.restype = ctypes.c_int32 - setdomainname.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - vhangup = _libraries['libc'].vhangup - vhangup.restype = ctypes.c_int32 - vhangup.argtypes = [] -except AttributeError: - pass -try: - revoke = _libraries['libc'].revoke - revoke.restype = ctypes.c_int32 - revoke.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - profil = _libraries['libc'].profil - profil.restype = ctypes.c_int32 - profil.argtypes = [ctypes.POINTER(ctypes.c_uint16), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - acct = _libraries['libc'].acct - acct.restype = ctypes.c_int32 - acct.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - getusershell = _libraries['libc'].getusershell - getusershell.restype = ctypes.POINTER(ctypes.c_char) - getusershell.argtypes = [] -except AttributeError: - pass -try: - endusershell = _libraries['libc'].endusershell - endusershell.restype = None - endusershell.argtypes = [] -except AttributeError: - pass -try: - setusershell = _libraries['libc'].setusershell - setusershell.restype = None - setusershell.argtypes = [] -except AttributeError: - pass -try: - daemon = _libraries['libc'].daemon - daemon.restype = ctypes.c_int32 - daemon.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - chroot = _libraries['libc'].chroot - chroot.restype = ctypes.c_int32 - chroot.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - getpass = _libraries['libc'].getpass - getpass.restype = ctypes.POINTER(ctypes.c_char) - getpass.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - fsync = _libraries['libc'].fsync - fsync.restype = ctypes.c_int32 - fsync.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - gethostid = _libraries['libc'].gethostid - gethostid.restype = ctypes.c_int64 - gethostid.argtypes = [] -except AttributeError: - pass -try: - sync = _libraries['libc'].sync - sync.restype = None - sync.argtypes = [] -except AttributeError: - pass -try: - getpagesize = _libraries['libc'].getpagesize - getpagesize.restype = ctypes.c_int32 - getpagesize.argtypes = [] -except AttributeError: - pass -try: - getdtablesize = _libraries['libc'].getdtablesize - getdtablesize.restype = ctypes.c_int32 - getdtablesize.argtypes = [] -except AttributeError: - pass -try: - truncate = _libraries['libc'].truncate - truncate.restype = ctypes.c_int32 - truncate.argtypes = [ctypes.POINTER(ctypes.c_char), __off_t] -except AttributeError: - pass -try: - ftruncate = _libraries['libc'].ftruncate - ftruncate.restype = ctypes.c_int32 - ftruncate.argtypes = [ctypes.c_int32, __off_t] -except AttributeError: - pass -try: - brk = _libraries['libc'].brk - brk.restype = ctypes.c_int32 - brk.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - sbrk = _libraries['libc'].sbrk - sbrk.restype = ctypes.POINTER(None) - sbrk.argtypes = [intptr_t] -except AttributeError: - pass -try: - syscall = _libraries['libc'].syscall - syscall.restype = ctypes.c_int64 - syscall.argtypes = [ctypes.c_int64] -except AttributeError: - pass -try: - lockf = _libraries['libc'].lockf - lockf.restype = ctypes.c_int32 - lockf.argtypes = [ctypes.c_int32, ctypes.c_int32, __off_t] -except AttributeError: - pass -try: - fdatasync = _libraries['libc'].fdatasync - fdatasync.restype = ctypes.c_int32 - fdatasync.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - crypt = _libraries['libc'].crypt - crypt.restype = ctypes.POINTER(ctypes.c_char) - crypt.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - getentropy = _libraries['libc'].getentropy - getentropy.restype = ctypes.c_int32 - getentropy.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -__ASM_GENERIC_MMAN_COMMON_H = True # macro -PROT_READ = 0x1 # macro -PROT_WRITE = 0x2 # macro -PROT_EXEC = 0x4 # macro -PROT_SEM = 0x8 # macro -PROT_NONE = 0x0 # macro -PROT_GROWSDOWN = 0x01000000 # macro -PROT_GROWSUP = 0x02000000 # macro -MAP_TYPE = 0x0f # macro -MAP_FIXED = 0x10 # macro -MAP_ANONYMOUS = 0x20 # macro -MAP_POPULATE = 0x008000 # macro -MAP_NONBLOCK = 0x010000 # macro -MAP_STACK = 0x020000 # macro -MAP_HUGETLB = 0x040000 # macro -MAP_SYNC = 0x080000 # macro -MAP_FIXED_NOREPLACE = 0x100000 # macro -MAP_UNINITIALIZED = 0x4000000 # macro -MLOCK_ONFAULT = 0x01 # macro -MS_ASYNC = 1 # macro -MS_INVALIDATE = 2 # macro -MS_SYNC = 4 # macro -MADV_NORMAL = 0 # macro -MADV_RANDOM = 1 # macro -MADV_SEQUENTIAL = 2 # macro -MADV_WILLNEED = 3 # macro -MADV_DONTNEED = 4 # macro -MADV_FREE = 8 # macro -MADV_REMOVE = 9 # macro -MADV_DONTFORK = 10 # macro -MADV_DOFORK = 11 # macro -MADV_HWPOISON = 100 # macro -MADV_SOFT_OFFLINE = 101 # macro -MADV_MERGEABLE = 12 # macro -MADV_UNMERGEABLE = 13 # macro -MADV_HUGEPAGE = 14 # macro -MADV_NOHUGEPAGE = 15 # macro -MADV_DONTDUMP = 16 # macro -MADV_DODUMP = 17 # macro -MADV_WIPEONFORK = 18 # macro -MADV_KEEPONFORK = 19 # macro -MADV_COLD = 20 # macro -MADV_PAGEOUT = 21 # macro -MADV_POPULATE_READ = 22 # macro -MADV_POPULATE_WRITE = 23 # macro -MADV_DONTNEED_LOCKED = 24 # macro -MADV_COLLAPSE = 25 # macro -MAP_FILE = 0 # macro -PKEY_DISABLE_ACCESS = 0x1 # macro -PKEY_DISABLE_WRITE = 0x2 # macro -PKEY_ACCESS_MASK = (0x1|0x2) # macro -__all__ = \ - ['AT_BASE', 'AT_BASE_PLATFORM', 'AT_CLKTCK', 'AT_DCACHEBSIZE', - 'AT_EGID', 'AT_ENTRY', 'AT_EUID', 'AT_EXECFD', 'AT_EXECFN', - 'AT_FLAGS', 'AT_FPUCW', 'AT_GID', 'AT_HWCAP', 'AT_HWCAP2', - 'AT_HWCAP3', 'AT_HWCAP4', 'AT_ICACHEBSIZE', 'AT_IGNORE', - 'AT_IGNOREPPC', 'AT_L1D_CACHEGEOMETRY', 'AT_L1D_CACHESHAPE', - 'AT_L1D_CACHESIZE', 'AT_L1I_CACHEGEOMETRY', 'AT_L1I_CACHESHAPE', - 'AT_L1I_CACHESIZE', 'AT_L2_CACHEGEOMETRY', 'AT_L2_CACHESHAPE', - 'AT_L2_CACHESIZE', 'AT_L3_CACHEGEOMETRY', 'AT_L3_CACHESHAPE', - 'AT_L3_CACHESIZE', 'AT_MINSIGSTKSZ', 'AT_NOTELF', 'AT_NULL', - 'AT_PAGESZ', 'AT_PHDR', 'AT_PHENT', 'AT_PHNUM', 'AT_PLATFORM', - 'AT_RANDOM', 'AT_RSEQ_ALIGN', 'AT_RSEQ_FEATURE_SIZE', 'AT_SECURE', - 'AT_SYSINFO', 'AT_SYSINFO_EHDR', 'AT_UCACHEBSIZE', 'AT_UID', - 'DF_1_CONFALT', 'DF_1_DIRECT', 'DF_1_DISPRELDNE', - 'DF_1_DISPRELPND', 'DF_1_EDITED', 'DF_1_ENDFILTEE', 'DF_1_GLOBAL', - 'DF_1_GLOBAUDIT', 'DF_1_GROUP', 'DF_1_IGNMULDEF', - 'DF_1_INITFIRST', 'DF_1_INTERPOSE', 'DF_1_KMOD', 'DF_1_LOADFLTR', - 'DF_1_NOCOMMON', 'DF_1_NODEFLIB', 'DF_1_NODELETE', - 'DF_1_NODIRECT', 'DF_1_NODUMP', 'DF_1_NOHDR', 'DF_1_NOKSYMS', - 'DF_1_NOOPEN', 'DF_1_NORELOC', 'DF_1_NOW', 'DF_1_ORIGIN', - 'DF_1_PIE', 'DF_1_SINGLETON', 'DF_1_STUB', 'DF_1_SYMINTPOSE', - 'DF_1_TRANS', 'DF_1_WEAKFILTER', 'DF_BIND_NOW', 'DF_ORIGIN', - 'DF_P1_GROUPPERM', 'DF_P1_LAZYLOAD', 'DF_STATIC_TLS', - 'DF_SYMBOLIC', 'DF_TEXTREL', 'DTF_1_CONFEXP', 'DTF_1_PARINIT', - 'DT_AARCH64_BTI_PLT', 'DT_AARCH64_NUM', 'DT_AARCH64_PAC_PLT', - 'DT_AARCH64_VARIANT_PCS', 'DT_ADDRNUM', 'DT_ADDRRNGHI', - 'DT_ADDRRNGLO', 'DT_ALPHA_NUM', 'DT_ALPHA_PLTRO', 'DT_AUDIT', - 'DT_AUXILIARY', 'DT_BIND_NOW', 'DT_CHECKSUM', 'DT_CONFIG', - 'DT_DEBUG', 'DT_DEPAUDIT', 'DT_ENCODING', 'DT_EXTRANUM', - 'DT_FEATURE_1', 'DT_FILTER', 'DT_FINI', 'DT_FINI_ARRAY', - 'DT_FINI_ARRAYSZ', 'DT_FLAGS', 'DT_FLAGS_1', 'DT_GNU_CONFLICT', - 'DT_GNU_CONFLICTSZ', 'DT_GNU_HASH', 'DT_GNU_LIBLIST', - 'DT_GNU_LIBLISTSZ', 'DT_GNU_PRELINKED', 'DT_HASH', 'DT_HIOS', - 'DT_HIPROC', 'DT_IA_64_NUM', 'DT_IA_64_PLT_RESERVE', 'DT_INIT', - 'DT_INIT_ARRAY', 'DT_INIT_ARRAYSZ', 'DT_JMPREL', 'DT_LOOS', - 'DT_LOPROC', 'DT_MIPS_AUX_DYNAMIC', 'DT_MIPS_BASE_ADDRESS', - 'DT_MIPS_COMPACT_SIZE', 'DT_MIPS_CONFLICT', 'DT_MIPS_CONFLICTNO', - 'DT_MIPS_CXX_FLAGS', 'DT_MIPS_DELTA_CLASS', - 'DT_MIPS_DELTA_CLASSSYM', 'DT_MIPS_DELTA_CLASSSYM_NO', - 'DT_MIPS_DELTA_CLASS_NO', 'DT_MIPS_DELTA_INSTANCE', - 'DT_MIPS_DELTA_INSTANCE_NO', 'DT_MIPS_DELTA_RELOC', - 'DT_MIPS_DELTA_RELOC_NO', 'DT_MIPS_DELTA_SYM', - 'DT_MIPS_DELTA_SYM_NO', 'DT_MIPS_DYNSTR_ALIGN', 'DT_MIPS_FLAGS', - 'DT_MIPS_GOTSYM', 'DT_MIPS_GP_VALUE', 'DT_MIPS_HIDDEN_GOTIDX', - 'DT_MIPS_HIPAGENO', 'DT_MIPS_ICHECKSUM', 'DT_MIPS_INTERFACE', - 'DT_MIPS_INTERFACE_SIZE', 'DT_MIPS_IVERSION', 'DT_MIPS_LIBLIST', - 'DT_MIPS_LIBLISTNO', 'DT_MIPS_LOCALPAGE_GOTIDX', - 'DT_MIPS_LOCAL_GOTIDX', 'DT_MIPS_LOCAL_GOTNO', 'DT_MIPS_MSYM', - 'DT_MIPS_NUM', 'DT_MIPS_OPTIONS', 'DT_MIPS_PERF_SUFFIX', - 'DT_MIPS_PIXIE_INIT', 'DT_MIPS_PLTGOT', - 'DT_MIPS_PROTECTED_GOTIDX', 'DT_MIPS_RLD_MAP', - 'DT_MIPS_RLD_MAP_REL', 'DT_MIPS_RLD_TEXT_RESOLVE_ADDR', - 'DT_MIPS_RLD_VERSION', 'DT_MIPS_RWPLT', 'DT_MIPS_SYMBOL_LIB', - 'DT_MIPS_SYMTABNO', 'DT_MIPS_TIME_STAMP', 'DT_MIPS_UNREFEXTNO', - 'DT_MIPS_XHASH', 'DT_MOVEENT', 'DT_MOVESZ', 'DT_MOVETAB', - 'DT_NEEDED', 'DT_NIOS2_GP', 'DT_NULL', 'DT_NUM', 'DT_PLTGOT', - 'DT_PLTPAD', 'DT_PLTPADSZ', 'DT_PLTREL', 'DT_PLTRELSZ', - 'DT_POSFLAG_1', 'DT_PPC64_GLINK', 'DT_PPC64_NUM', 'DT_PPC64_OPD', - 'DT_PPC64_OPDSZ', 'DT_PPC64_OPT', 'DT_PPC_GOT', 'DT_PPC_NUM', - 'DT_PPC_OPT', 'DT_PREINIT_ARRAY', 'DT_PREINIT_ARRAYSZ', - 'DT_PROCNUM', 'DT_REL', 'DT_RELA', 'DT_RELACOUNT', 'DT_RELAENT', - 'DT_RELASZ', 'DT_RELCOUNT', 'DT_RELENT', 'DT_RELR', 'DT_RELRENT', - 'DT_RELRSZ', 'DT_RELSZ', 'DT_RISCV_VARIANT_CC', 'DT_RPATH', - 'DT_RUNPATH', 'DT_SONAME', 'DT_SPARC_NUM', 'DT_SPARC_REGISTER', - 'DT_STRSZ', 'DT_STRTAB', 'DT_SYMBOLIC', 'DT_SYMENT', - 'DT_SYMINENT', 'DT_SYMINFO', 'DT_SYMINSZ', 'DT_SYMTAB', - 'DT_SYMTAB_SHNDX', 'DT_TEXTREL', 'DT_TLSDESC_GOT', - 'DT_TLSDESC_PLT', 'DT_VALNUM', 'DT_VALRNGHI', 'DT_VALRNGLO', - 'DT_VERDEF', 'DT_VERDEFNUM', 'DT_VERNEED', 'DT_VERNEEDNUM', - 'DT_VERSIONTAGNUM', 'DT_VERSYM', 'DT_X86_64_NUM', 'DT_X86_64_PLT', - 'DT_X86_64_PLTENT', 'DT_X86_64_PLTSZ', 'EFA_PARISC_1_0', - 'EFA_PARISC_1_1', 'EFA_PARISC_2_0', 'EF_ALPHA_32BIT', - 'EF_ALPHA_CANRELAX', 'EF_ARC_ALL_MSK', 'EF_ARC_MACH_MSK', - 'EF_ARC_OSABI_MSK', 'EF_ARM_ABI_FLOAT_HARD', - 'EF_ARM_ABI_FLOAT_SOFT', 'EF_ARM_ALIGN8', 'EF_ARM_APCS_26', - 'EF_ARM_APCS_FLOAT', 'EF_ARM_BE8', 'EF_ARM_DYNSYMSUSESEGIDX', - 'EF_ARM_EABIMASK', 'EF_ARM_EABI_UNKNOWN', 'EF_ARM_EABI_VER1', - 'EF_ARM_EABI_VER2', 'EF_ARM_EABI_VER3', 'EF_ARM_EABI_VER4', - 'EF_ARM_EABI_VER5', 'EF_ARM_HASENTRY', 'EF_ARM_INTERWORK', - 'EF_ARM_LE8', 'EF_ARM_MAPSYMSFIRST', 'EF_ARM_MAVERICK_FLOAT', - 'EF_ARM_NEW_ABI', 'EF_ARM_OLD_ABI', 'EF_ARM_PIC', - 'EF_ARM_RELEXEC', 'EF_ARM_SOFT_FLOAT', 'EF_ARM_SYMSARESORTED', - 'EF_ARM_VFP_FLOAT', 'EF_CPU32', 'EF_CSKY_ABIMASK', - 'EF_CSKY_ABIV1', 'EF_CSKY_ABIV2', 'EF_CSKY_OTHER', - 'EF_CSKY_PROCESSOR', 'EF_IA_64_ABI64', 'EF_IA_64_ARCH', - 'EF_IA_64_MASKOS', 'EF_LARCH_ABI_DOUBLE_FLOAT', - 'EF_LARCH_ABI_MODIFIER_MASK', 'EF_LARCH_ABI_SINGLE_FLOAT', - 'EF_LARCH_ABI_SOFT_FLOAT', 'EF_LARCH_OBJABI_V1', - 'EF_MIPS_32BITMODE', 'EF_MIPS_ABI', 'EF_MIPS_ABI2', - 'EF_MIPS_ABI_EABI32', 'EF_MIPS_ABI_EABI64', 'EF_MIPS_ABI_O32', - 'EF_MIPS_ABI_O64', 'EF_MIPS_ABI_ON32', 'EF_MIPS_ARCH', - 'EF_MIPS_ARCH_1', 'EF_MIPS_ARCH_2', 'EF_MIPS_ARCH_3', - 'EF_MIPS_ARCH_32', 'EF_MIPS_ARCH_32R2', 'EF_MIPS_ARCH_32R6', - 'EF_MIPS_ARCH_4', 'EF_MIPS_ARCH_5', 'EF_MIPS_ARCH_64', - 'EF_MIPS_ARCH_64R2', 'EF_MIPS_ARCH_64R6', 'EF_MIPS_ARCH_ASE', - 'EF_MIPS_ARCH_ASE_M16', 'EF_MIPS_ARCH_ASE_MDMX', - 'EF_MIPS_ARCH_ASE_MICROMIPS', 'EF_MIPS_CPIC', 'EF_MIPS_FP64', - 'EF_MIPS_MACH', 'EF_MIPS_MACH_3900', 'EF_MIPS_MACH_4010', - 'EF_MIPS_MACH_4100', 'EF_MIPS_MACH_4111', 'EF_MIPS_MACH_4120', - 'EF_MIPS_MACH_4650', 'EF_MIPS_MACH_5400', 'EF_MIPS_MACH_5500', - 'EF_MIPS_MACH_5900', 'EF_MIPS_MACH_9000', 'EF_MIPS_MACH_ALLEGREX', - 'EF_MIPS_MACH_GS264E', 'EF_MIPS_MACH_GS464', - 'EF_MIPS_MACH_GS464E', 'EF_MIPS_MACH_IAMR2', 'EF_MIPS_MACH_LS2E', - 'EF_MIPS_MACH_LS2F', 'EF_MIPS_MACH_OCTEON', - 'EF_MIPS_MACH_OCTEON2', 'EF_MIPS_MACH_OCTEON3', - 'EF_MIPS_MACH_SB1', 'EF_MIPS_MACH_XLR', 'EF_MIPS_NAN2008', - 'EF_MIPS_NOREORDER', 'EF_MIPS_OPTIONS_FIRST', 'EF_MIPS_PIC', - 'EF_MIPS_UCODE', 'EF_MIPS_XGOT', 'EF_PARISC_ARCH', - 'EF_PARISC_EXT', 'EF_PARISC_LAZYSWAP', 'EF_PARISC_LSB', - 'EF_PARISC_NO_KABP', 'EF_PARISC_TRAPNIL', 'EF_PARISC_WIDE', - 'EF_PPC64_ABI', 'EF_PPC_EMB', 'EF_PPC_RELOCATABLE', - 'EF_PPC_RELOCATABLE_LIB', 'EF_RISCV_FLOAT_ABI', - 'EF_RISCV_FLOAT_ABI_DOUBLE', 'EF_RISCV_FLOAT_ABI_QUAD', - 'EF_RISCV_FLOAT_ABI_SINGLE', 'EF_RISCV_FLOAT_ABI_SOFT', - 'EF_RISCV_RVC', 'EF_RISCV_RVE', 'EF_RISCV_TSO', - 'EF_S390_HIGH_GPRS', 'EF_SH1', 'EF_SH2', 'EF_SH2A', - 'EF_SH2A_NOFPU', 'EF_SH2A_SH3E', 'EF_SH2A_SH3_NOFPU', - 'EF_SH2A_SH4', 'EF_SH2A_SH4_NOFPU', 'EF_SH2E', 'EF_SH3', - 'EF_SH3E', 'EF_SH3_DSP', 'EF_SH3_NOMMU', 'EF_SH4', 'EF_SH4A', - 'EF_SH4AL_DSP', 'EF_SH4A_NOFPU', 'EF_SH4_NOFPU', - 'EF_SH4_NOMMU_NOFPU', 'EF_SH_DSP', 'EF_SH_MACH_MASK', - 'EF_SH_UNKNOWN', 'EF_SPARCV9_MM', 'EF_SPARCV9_PSO', - 'EF_SPARCV9_RMO', 'EF_SPARCV9_TSO', 'EF_SPARC_32PLUS', - 'EF_SPARC_EXT_MASK', 'EF_SPARC_HAL_R1', 'EF_SPARC_LEDATA', - 'EF_SPARC_SUN_US1', 'EF_SPARC_SUN_US3', 'EI_ABIVERSION', - 'EI_CLASS', 'EI_DATA', 'EI_MAG0', 'EI_MAG1', 'EI_MAG2', 'EI_MAG3', - 'EI_NIDENT', 'EI_OSABI', 'EI_PAD', 'EI_VERSION', 'ELFCLASS32', - 'ELFCLASS64', 'ELFCLASSNONE', 'ELFCLASSNUM', 'ELFCOMPRESS_HIOS', - 'ELFCOMPRESS_HIPROC', 'ELFCOMPRESS_LOOS', 'ELFCOMPRESS_LOPROC', - 'ELFCOMPRESS_ZLIB', 'ELFCOMPRESS_ZSTD', 'ELFDATA2LSB', - 'ELFDATA2MSB', 'ELFDATANONE', 'ELFDATANUM', 'ELFMAG', 'ELFMAG0', - 'ELFMAG1', 'ELFMAG2', 'ELFMAG3', 'ELFOSABI_AIX', 'ELFOSABI_ARM', - 'ELFOSABI_ARM_AEABI', 'ELFOSABI_FREEBSD', 'ELFOSABI_GNU', - 'ELFOSABI_HPUX', 'ELFOSABI_IRIX', 'ELFOSABI_LINUX', - 'ELFOSABI_MODESTO', 'ELFOSABI_NETBSD', 'ELFOSABI_NONE', - 'ELFOSABI_OPENBSD', 'ELFOSABI_SOLARIS', 'ELFOSABI_STANDALONE', - 'ELFOSABI_SYSV', 'ELFOSABI_TRU64', 'ELF_NOTE_ABI', 'ELF_NOTE_FDO', - 'ELF_NOTE_GNU', 'ELF_NOTE_OS_FREEBSD', 'ELF_NOTE_OS_GNU', - 'ELF_NOTE_OS_LINUX', 'ELF_NOTE_OS_SOLARIS2', - 'ELF_NOTE_PAGESIZE_HINT', 'ELF_NOTE_SOLARIS', 'EM_386', - 'EM_56800EX', 'EM_68HC05', 'EM_68HC08', 'EM_68HC11', 'EM_68HC12', - 'EM_68HC16', 'EM_68K', 'EM_78KOR', 'EM_8051', 'EM_860', 'EM_88K', - 'EM_960', 'EM_AARCH64', 'EM_ALPHA', 'EM_ALTERA_NIOS2', - 'EM_AMDGPU', 'EM_ARC', 'EM_ARCA', 'EM_ARCV2', 'EM_ARC_A5', - 'EM_ARC_COMPACT', 'EM_ARM', 'EM_AVR', 'EM_AVR32', 'EM_BA1', - 'EM_BA2', 'EM_BLACKFIN', 'EM_BPF', 'EM_C166', 'EM_CDP', 'EM_CE', - 'EM_CLOUDSHIELD', 'EM_COGE', 'EM_COLDFIRE', 'EM_COOL', - 'EM_COREA_1ST', 'EM_COREA_2ND', 'EM_CR', 'EM_CR16', 'EM_CRAYNV2', - 'EM_CRIS', 'EM_CRX', 'EM_CSKY', 'EM_CSR_KALIMBA', 'EM_CUDA', - 'EM_CYPRESS_M8C', 'EM_D10V', 'EM_D30V', 'EM_DSP24', 'EM_DSPIC30F', - 'EM_DXP', 'EM_ECOG16', 'EM_ECOG1X', 'EM_ECOG2', 'EM_EMX16', - 'EM_EMX8', 'EM_ETPU', 'EM_EXCESS', 'EM_F2MC16', 'EM_FAKE_ALPHA', - 'EM_FIREPATH', 'EM_FR20', 'EM_FR30', 'EM_FT32', 'EM_FX66', - 'EM_H8S', 'EM_H8_300', 'EM_H8_300H', 'EM_H8_500', 'EM_HUANY', - 'EM_IAMCU', 'EM_IA_64', 'EM_INTELGT', 'EM_IP2K', 'EM_JAVELIN', - 'EM_K10M', 'EM_KM32', 'EM_KMX32', 'EM_KVARC', 'EM_L10M', - 'EM_LATTICEMICO32', 'EM_LOONGARCH', 'EM_M16C', 'EM_M32', - 'EM_M32C', 'EM_M32R', 'EM_MANIK', 'EM_MAX', 'EM_MAXQ30', - 'EM_MCHP_PIC', 'EM_MCST_ELBRUS', 'EM_ME16', 'EM_METAG', - 'EM_MICROBLAZE', 'EM_MIPS', 'EM_MIPS_RS3_LE', 'EM_MIPS_X', - 'EM_MMA', 'EM_MMDSP_PLUS', 'EM_MMIX', 'EM_MN10200', 'EM_MN10300', - 'EM_MOXIE', 'EM_MSP430', 'EM_NCPU', 'EM_NDR1', 'EM_NDS32', - 'EM_NONE', 'EM_NORC', 'EM_NS32K', 'EM_NUM', 'EM_OPEN8', - 'EM_OPENRISC', 'EM_PARISC', 'EM_PCP', 'EM_PDP10', 'EM_PDP11', - 'EM_PDSP', 'EM_PJ', 'EM_PPC', 'EM_PPC64', 'EM_PRISM', 'EM_QDSP6', - 'EM_R32C', 'EM_RCE', 'EM_RH32', 'EM_RISCV', 'EM_RL78', 'EM_RS08', - 'EM_RX', 'EM_S370', 'EM_S390', 'EM_SCORE7', 'EM_SEP', 'EM_SE_C17', - 'EM_SE_C33', 'EM_SH', 'EM_SHARC', 'EM_SLE9X', 'EM_SNP1K', - 'EM_SPARC', 'EM_SPARC32PLUS', 'EM_SPARCV9', 'EM_SPU', 'EM_ST100', - 'EM_ST19', 'EM_ST200', 'EM_ST7', 'EM_ST9PLUS', 'EM_STARCORE', - 'EM_STM8', 'EM_STXP7X', 'EM_SVX', 'EM_TILE64', 'EM_TILEGX', - 'EM_TILEPRO', 'EM_TINYJ', 'EM_TI_ARP32', 'EM_TI_C2000', - 'EM_TI_C5500', 'EM_TI_C6000', 'EM_TI_PRU', 'EM_TMM_GPP', 'EM_TPC', - 'EM_TRICORE', 'EM_TRIMEDIA', 'EM_TSK3000', 'EM_UNICORE', - 'EM_V800', 'EM_V850', 'EM_VAX', 'EM_VIDEOCORE', 'EM_VIDEOCORE3', - 'EM_VIDEOCORE5', 'EM_VISIUM', 'EM_VPP500', 'EM_X86_64', - 'EM_XCORE', 'EM_XGATE', 'EM_XIMO16', 'EM_XTENSA', 'EM_Z80', - 'EM_ZSP', 'ET_CORE', 'ET_DYN', 'ET_EXEC', 'ET_HIOS', 'ET_HIPROC', - 'ET_LOOS', 'ET_LOPROC', 'ET_NONE', 'ET_NUM', 'ET_REL', - 'EV_CURRENT', 'EV_NONE', 'EV_NUM', 'E_MIPS_ARCH_1', - 'E_MIPS_ARCH_2', 'E_MIPS_ARCH_3', 'E_MIPS_ARCH_32', - 'E_MIPS_ARCH_4', 'E_MIPS_ARCH_5', 'E_MIPS_ARCH_64', 'Elf32_Addr', - 'Elf32_Chdr', 'Elf32_Conflict', 'Elf32_Dyn', 'Elf32_Ehdr', - 'Elf32_Half', 'Elf32_Lib', 'Elf32_Move', 'Elf32_Nhdr', - 'Elf32_Off', 'Elf32_Phdr', 'Elf32_RegInfo', 'Elf32_Rel', - 'Elf32_Rela', 'Elf32_Relr', 'Elf32_Section', 'Elf32_Shdr', - 'Elf32_Sword', 'Elf32_Sxword', 'Elf32_Sym', 'Elf32_Syminfo', - 'Elf32_Verdaux', 'Elf32_Verdef', 'Elf32_Vernaux', 'Elf32_Verneed', - 'Elf32_Versym', 'Elf32_Word', 'Elf32_Xword', 'Elf32_auxv_t', - 'Elf32_gptab', 'Elf64_Addr', 'Elf64_Chdr', 'Elf64_Dyn', - 'Elf64_Ehdr', 'Elf64_Half', 'Elf64_Lib', 'Elf64_Move', - 'Elf64_Nhdr', 'Elf64_Off', 'Elf64_Phdr', 'Elf64_Rel', - 'Elf64_Rela', 'Elf64_Relr', 'Elf64_Section', 'Elf64_Shdr', - 'Elf64_Sword', 'Elf64_Sxword', 'Elf64_Sym', 'Elf64_Syminfo', - 'Elf64_Verdaux', 'Elf64_Verdef', 'Elf64_Vernaux', 'Elf64_Verneed', - 'Elf64_Versym', 'Elf64_Word', 'Elf64_Xword', 'Elf64_auxv_t', - 'Elf_MIPS_ABIFlags_v0', 'Elf_Options', 'Elf_Options_Hw', 'F_LOCK', - 'F_OK', 'F_TEST', 'F_TLOCK', 'F_ULOCK', 'GNU_PROPERTY_1_NEEDED', - 'GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS', - 'GNU_PROPERTY_AARCH64_FEATURE_1_AND', - 'GNU_PROPERTY_AARCH64_FEATURE_1_BTI', - 'GNU_PROPERTY_AARCH64_FEATURE_1_PAC', 'GNU_PROPERTY_HIPROC', - 'GNU_PROPERTY_HIUSER', 'GNU_PROPERTY_LOPROC', - 'GNU_PROPERTY_LOUSER', 'GNU_PROPERTY_NO_COPY_ON_PROTECTED', - 'GNU_PROPERTY_STACK_SIZE', 'GNU_PROPERTY_UINT32_AND_HI', - 'GNU_PROPERTY_UINT32_AND_LO', 'GNU_PROPERTY_UINT32_OR_HI', - 'GNU_PROPERTY_UINT32_OR_LO', 'GNU_PROPERTY_X86_FEATURE_1_AND', - 'GNU_PROPERTY_X86_FEATURE_1_IBT', - 'GNU_PROPERTY_X86_FEATURE_1_SHSTK', - 'GNU_PROPERTY_X86_ISA_1_BASELINE', - 'GNU_PROPERTY_X86_ISA_1_NEEDED', 'GNU_PROPERTY_X86_ISA_1_USED', - 'GNU_PROPERTY_X86_ISA_1_V2', 'GNU_PROPERTY_X86_ISA_1_V3', - 'GNU_PROPERTY_X86_ISA_1_V4', 'GRP_COMDAT', 'LITUSE_ALPHA_ADDR', - 'LITUSE_ALPHA_BASE', 'LITUSE_ALPHA_BYTOFF', 'LITUSE_ALPHA_JSR', - 'LITUSE_ALPHA_TLS_GD', 'LITUSE_ALPHA_TLS_LDM', 'LL_DELAY_LOAD', - 'LL_DELTA', 'LL_EXACT_MATCH', 'LL_EXPORTS', 'LL_IGNORE_INT_VER', - 'LL_NONE', 'LL_REQUIRE_MINOR', 'L_INCR', 'L_SET', 'L_XTND', - 'MADV_COLD', 'MADV_COLLAPSE', 'MADV_DODUMP', 'MADV_DOFORK', - 'MADV_DONTDUMP', 'MADV_DONTFORK', 'MADV_DONTNEED', - 'MADV_DONTNEED_LOCKED', 'MADV_FREE', 'MADV_HUGEPAGE', - 'MADV_HWPOISON', 'MADV_KEEPONFORK', 'MADV_MERGEABLE', - 'MADV_NOHUGEPAGE', 'MADV_NORMAL', 'MADV_PAGEOUT', - 'MADV_POPULATE_READ', 'MADV_POPULATE_WRITE', 'MADV_RANDOM', - 'MADV_REMOVE', 'MADV_SEQUENTIAL', 'MADV_SOFT_OFFLINE', - 'MADV_UNMERGEABLE', 'MADV_WILLNEED', 'MADV_WIPEONFORK', - 'MAP_ANONYMOUS', 'MAP_FILE', 'MAP_FIXED', 'MAP_FIXED_NOREPLACE', - 'MAP_HUGETLB', 'MAP_NONBLOCK', 'MAP_POPULATE', 'MAP_STACK', - 'MAP_SYNC', 'MAP_TYPE', 'MAP_UNINITIALIZED', 'MIPS_AFL_ASE_DSP', - 'MIPS_AFL_ASE_DSPR2', 'MIPS_AFL_ASE_EVA', 'MIPS_AFL_ASE_MASK', - 'MIPS_AFL_ASE_MCU', 'MIPS_AFL_ASE_MDMX', 'MIPS_AFL_ASE_MICROMIPS', - 'MIPS_AFL_ASE_MIPS16', 'MIPS_AFL_ASE_MIPS3D', 'MIPS_AFL_ASE_MSA', - 'MIPS_AFL_ASE_MT', 'MIPS_AFL_ASE_SMARTMIPS', 'MIPS_AFL_ASE_VIRT', - 'MIPS_AFL_ASE_XPA', 'MIPS_AFL_EXT_10000', 'MIPS_AFL_EXT_3900', - 'MIPS_AFL_EXT_4010', 'MIPS_AFL_EXT_4100', 'MIPS_AFL_EXT_4111', - 'MIPS_AFL_EXT_4120', 'MIPS_AFL_EXT_4650', 'MIPS_AFL_EXT_5400', - 'MIPS_AFL_EXT_5500', 'MIPS_AFL_EXT_5900', - 'MIPS_AFL_EXT_LOONGSON_2E', 'MIPS_AFL_EXT_LOONGSON_2F', - 'MIPS_AFL_EXT_LOONGSON_3A', 'MIPS_AFL_EXT_OCTEON', - 'MIPS_AFL_EXT_OCTEON2', 'MIPS_AFL_EXT_OCTEONP', - 'MIPS_AFL_EXT_SB1', 'MIPS_AFL_EXT_XLR', - 'MIPS_AFL_FLAGS1_ODDSPREG', 'MIPS_AFL_REG_128', 'MIPS_AFL_REG_32', - 'MIPS_AFL_REG_64', 'MIPS_AFL_REG_NONE', 'MLOCK_ONFAULT', - 'MS_ASYNC', 'MS_INVALIDATE', 'MS_SYNC', - 'NOTE_GNU_PROPERTY_SECTION_NAME', 'NT_386_IOPERM', 'NT_386_TLS', - 'NT_ARM_HW_BREAK', 'NT_ARM_HW_WATCH', 'NT_ARM_PACA_KEYS', - 'NT_ARM_PACG_KEYS', 'NT_ARM_PAC_ENABLED_KEYS', 'NT_ARM_PAC_MASK', - 'NT_ARM_SVE', 'NT_ARM_SYSTEM_CALL', 'NT_ARM_TAGGED_ADDR_CTRL', - 'NT_ARM_TLS', 'NT_ARM_VFP', 'NT_ASRS', 'NT_AUXV', - 'NT_FDO_PACKAGING_METADATA', 'NT_FILE', 'NT_FPREGSET', - 'NT_GNU_ABI_TAG', 'NT_GNU_BUILD_ID', 'NT_GNU_GOLD_VERSION', - 'NT_GNU_HWCAP', 'NT_GNU_PROPERTY_TYPE_0', 'NT_GWINDOWS', - 'NT_LOONGARCH_CPUCFG', 'NT_LOONGARCH_CSR', - 'NT_LOONGARCH_HW_BREAK', 'NT_LOONGARCH_HW_WATCH', - 'NT_LOONGARCH_LASX', 'NT_LOONGARCH_LBT', 'NT_LOONGARCH_LSX', - 'NT_LWPSINFO', 'NT_LWPSTATUS', 'NT_MIPS_DSP', 'NT_MIPS_FP_MODE', - 'NT_MIPS_MSA', 'NT_PLATFORM', 'NT_PPC_DEXCR', 'NT_PPC_DSCR', - 'NT_PPC_EBB', 'NT_PPC_HASHKEYR', 'NT_PPC_PKEY', 'NT_PPC_PMU', - 'NT_PPC_PPR', 'NT_PPC_SPE', 'NT_PPC_TAR', 'NT_PPC_TM_CDSCR', - 'NT_PPC_TM_CFPR', 'NT_PPC_TM_CGPR', 'NT_PPC_TM_CPPR', - 'NT_PPC_TM_CTAR', 'NT_PPC_TM_CVMX', 'NT_PPC_TM_CVSX', - 'NT_PPC_TM_SPR', 'NT_PPC_VMX', 'NT_PPC_VSX', 'NT_PRCRED', - 'NT_PRFPREG', 'NT_PRFPXREG', 'NT_PRPSINFO', 'NT_PRSTATUS', - 'NT_PRXFPREG', 'NT_PRXREG', 'NT_PSINFO', 'NT_PSTATUS', - 'NT_RISCV_CSR', 'NT_RISCV_VECTOR', 'NT_S390_CTRS', - 'NT_S390_GS_BC', 'NT_S390_GS_CB', 'NT_S390_HIGH_GPRS', - 'NT_S390_LAST_BREAK', 'NT_S390_PREFIX', 'NT_S390_PV_CPU_DATA', - 'NT_S390_RI_CB', 'NT_S390_SYSTEM_CALL', 'NT_S390_TDB', - 'NT_S390_TIMER', 'NT_S390_TODCMP', 'NT_S390_TODPREG', - 'NT_S390_VXRS_HIGH', 'NT_S390_VXRS_LOW', 'NT_SIGINFO', - 'NT_TASKSTRUCT', 'NT_UTSNAME', 'NT_VERSION', 'NT_VMCOREDD', - 'NT_X86_SHSTK', 'NT_X86_XSTATE', 'ODK_EXCEPTIONS', 'ODK_FILL', - 'ODK_HWAND', 'ODK_HWOR', 'ODK_HWPATCH', 'ODK_NULL', 'ODK_PAD', - 'ODK_REGINFO', 'ODK_TAGS', 'OEX_DISMISS', 'OEX_FPDBUG', - 'OEX_FPU_DIV0', 'OEX_FPU_INEX', 'OEX_FPU_INVAL', 'OEX_FPU_MAX', - 'OEX_FPU_MIN', 'OEX_FPU_OFLO', 'OEX_FPU_UFLO', 'OEX_PAGE0', - 'OEX_PRECISEFP', 'OEX_SMM', 'OHWA0_R4KEOP_CHECKED', - 'OHWA1_R4KEOP_CLEAN', 'OHW_R4KEOP', 'OHW_R5KCVTL', 'OHW_R5KEOP', - 'OHW_R8KPFETCH', 'OPAD_POSTFIX', 'OPAD_PREFIX', 'OPAD_SYMBOL', - 'PF_ARM_ABS', 'PF_ARM_PI', 'PF_ARM_SB', 'PF_HP_CODE', - 'PF_HP_FAR_SHARED', 'PF_HP_LAZYSWAP', 'PF_HP_MODIFY', - 'PF_HP_NEAR_SHARED', 'PF_HP_PAGE_SIZE', 'PF_HP_SBP', - 'PF_IA_64_NORECOV', 'PF_MASKOS', 'PF_MASKPROC', 'PF_MIPS_LOCAL', - 'PF_PARISC_SBP', 'PF_R', 'PF_W', 'PF_X', 'PKEY_ACCESS_MASK', - 'PKEY_DISABLE_ACCESS', 'PKEY_DISABLE_WRITE', 'PN_XNUM', - 'PPC64_OPT_LOCALENTRY', 'PPC64_OPT_MULTI_TOC', 'PPC64_OPT_TLS', - 'PPC_OPT_TLS', 'PROT_EXEC', 'PROT_GROWSDOWN', 'PROT_GROWSUP', - 'PROT_NONE', 'PROT_READ', 'PROT_SEM', 'PROT_WRITE', - 'PT_AARCH64_MEMTAG_MTE', 'PT_ARM_EXIDX', 'PT_DYNAMIC', - 'PT_GNU_EH_FRAME', 'PT_GNU_PROPERTY', 'PT_GNU_RELRO', - 'PT_GNU_SFRAME', 'PT_GNU_STACK', 'PT_HIOS', 'PT_HIPROC', - 'PT_HISUNW', 'PT_HP_CORE_COMM', 'PT_HP_CORE_KERNEL', - 'PT_HP_CORE_LOADABLE', 'PT_HP_CORE_MMF', 'PT_HP_CORE_NONE', - 'PT_HP_CORE_PROC', 'PT_HP_CORE_SHM', 'PT_HP_CORE_STACK', - 'PT_HP_CORE_VERSION', 'PT_HP_FASTBIND', 'PT_HP_HSL_ANNOT', - 'PT_HP_OPT_ANNOT', 'PT_HP_PARALLEL', 'PT_HP_STACK', 'PT_HP_TLS', - 'PT_IA_64_ARCHEXT', 'PT_IA_64_HP_HSL_ANOT', - 'PT_IA_64_HP_OPT_ANOT', 'PT_IA_64_HP_STACK', 'PT_IA_64_UNWIND', - 'PT_INTERP', 'PT_LOAD', 'PT_LOOS', 'PT_LOPROC', 'PT_LOSUNW', - 'PT_MIPS_ABIFLAGS', 'PT_MIPS_OPTIONS', 'PT_MIPS_REGINFO', - 'PT_MIPS_RTPROC', 'PT_NOTE', 'PT_NULL', 'PT_NUM', - 'PT_PARISC_ARCHEXT', 'PT_PARISC_UNWIND', 'PT_PHDR', - 'PT_RISCV_ATTRIBUTES', 'PT_SHLIB', 'PT_SUNWBSS', 'PT_SUNWSTACK', - 'PT_TLS', 'RHF_CORD', 'RHF_DEFAULT_DELAY_LOAD', - 'RHF_DELTA_C_PLUS_PLUS', 'RHF_GUARANTEE_INIT', - 'RHF_GUARANTEE_START_INIT', 'RHF_NONE', 'RHF_NOTPOT', - 'RHF_NO_LIBRARY_REPLACEMENT', 'RHF_NO_MOVE', 'RHF_NO_UNRES_UNDEF', - 'RHF_PIXIE', 'RHF_QUICKSTART', 'RHF_REQUICKSTART', - 'RHF_REQUICKSTARTED', 'RHF_RLD_ORDER_SAFE', 'RHF_SGI_ONLY', - 'R_386_16', 'R_386_32', 'R_386_32PLT', 'R_386_8', 'R_386_COPY', - 'R_386_GLOB_DAT', 'R_386_GOT32', 'R_386_GOT32X', 'R_386_GOTOFF', - 'R_386_GOTPC', 'R_386_IRELATIVE', 'R_386_JMP_SLOT', 'R_386_NONE', - 'R_386_NUM', 'R_386_PC16', 'R_386_PC32', 'R_386_PC8', - 'R_386_PLT32', 'R_386_RELATIVE', 'R_386_SIZE32', 'R_386_TLS_DESC', - 'R_386_TLS_DESC_CALL', 'R_386_TLS_DTPMOD32', 'R_386_TLS_DTPOFF32', - 'R_386_TLS_GD', 'R_386_TLS_GD_32', 'R_386_TLS_GD_CALL', - 'R_386_TLS_GD_POP', 'R_386_TLS_GD_PUSH', 'R_386_TLS_GOTDESC', - 'R_386_TLS_GOTIE', 'R_386_TLS_IE', 'R_386_TLS_IE_32', - 'R_386_TLS_LDM', 'R_386_TLS_LDM_32', 'R_386_TLS_LDM_CALL', - 'R_386_TLS_LDM_POP', 'R_386_TLS_LDM_PUSH', 'R_386_TLS_LDO_32', - 'R_386_TLS_LE', 'R_386_TLS_LE_32', 'R_386_TLS_TPOFF', - 'R_386_TLS_TPOFF32', 'R_390_12', 'R_390_16', 'R_390_20', - 'R_390_32', 'R_390_64', 'R_390_8', 'R_390_COPY', 'R_390_GLOB_DAT', - 'R_390_GOT12', 'R_390_GOT16', 'R_390_GOT20', 'R_390_GOT32', - 'R_390_GOT64', 'R_390_GOTENT', 'R_390_GOTOFF16', 'R_390_GOTOFF32', - 'R_390_GOTOFF64', 'R_390_GOTPC', 'R_390_GOTPCDBL', - 'R_390_GOTPLT12', 'R_390_GOTPLT16', 'R_390_GOTPLT20', - 'R_390_GOTPLT32', 'R_390_GOTPLT64', 'R_390_GOTPLTENT', - 'R_390_IRELATIVE', 'R_390_JMP_SLOT', 'R_390_NONE', 'R_390_NUM', - 'R_390_PC16', 'R_390_PC16DBL', 'R_390_PC32', 'R_390_PC32DBL', - 'R_390_PC64', 'R_390_PLT16DBL', 'R_390_PLT32', 'R_390_PLT32DBL', - 'R_390_PLT64', 'R_390_PLTOFF16', 'R_390_PLTOFF32', - 'R_390_PLTOFF64', 'R_390_RELATIVE', 'R_390_TLS_DTPMOD', - 'R_390_TLS_DTPOFF', 'R_390_TLS_GD32', 'R_390_TLS_GD64', - 'R_390_TLS_GDCALL', 'R_390_TLS_GOTIE12', 'R_390_TLS_GOTIE20', - 'R_390_TLS_GOTIE32', 'R_390_TLS_GOTIE64', 'R_390_TLS_IE32', - 'R_390_TLS_IE64', 'R_390_TLS_IEENT', 'R_390_TLS_LDCALL', - 'R_390_TLS_LDM32', 'R_390_TLS_LDM64', 'R_390_TLS_LDO32', - 'R_390_TLS_LDO64', 'R_390_TLS_LE32', 'R_390_TLS_LE64', - 'R_390_TLS_LOAD', 'R_390_TLS_TPOFF', 'R_68K_16', 'R_68K_32', - 'R_68K_8', 'R_68K_COPY', 'R_68K_GLOB_DAT', 'R_68K_GOT16', - 'R_68K_GOT16O', 'R_68K_GOT32', 'R_68K_GOT32O', 'R_68K_GOT8', - 'R_68K_GOT8O', 'R_68K_JMP_SLOT', 'R_68K_NONE', 'R_68K_NUM', - 'R_68K_PC16', 'R_68K_PC32', 'R_68K_PC8', 'R_68K_PLT16', - 'R_68K_PLT16O', 'R_68K_PLT32', 'R_68K_PLT32O', 'R_68K_PLT8', - 'R_68K_PLT8O', 'R_68K_RELATIVE', 'R_68K_TLS_DTPMOD32', - 'R_68K_TLS_DTPREL32', 'R_68K_TLS_GD16', 'R_68K_TLS_GD32', - 'R_68K_TLS_GD8', 'R_68K_TLS_IE16', 'R_68K_TLS_IE32', - 'R_68K_TLS_IE8', 'R_68K_TLS_LDM16', 'R_68K_TLS_LDM32', - 'R_68K_TLS_LDM8', 'R_68K_TLS_LDO16', 'R_68K_TLS_LDO32', - 'R_68K_TLS_LDO8', 'R_68K_TLS_LE16', 'R_68K_TLS_LE32', - 'R_68K_TLS_LE8', 'R_68K_TLS_TPREL32', 'R_AARCH64_ABS16', - 'R_AARCH64_ABS32', 'R_AARCH64_ABS64', 'R_AARCH64_ADD_ABS_LO12_NC', - 'R_AARCH64_ADR_GOT_PAGE', 'R_AARCH64_ADR_PREL_LO21', - 'R_AARCH64_ADR_PREL_PG_HI21', 'R_AARCH64_ADR_PREL_PG_HI21_NC', - 'R_AARCH64_CALL26', 'R_AARCH64_CONDBR19', 'R_AARCH64_COPY', - 'R_AARCH64_GLOB_DAT', 'R_AARCH64_GOTREL32', 'R_AARCH64_GOTREL64', - 'R_AARCH64_GOT_LD_PREL19', 'R_AARCH64_IRELATIVE', - 'R_AARCH64_JUMP26', 'R_AARCH64_JUMP_SLOT', - 'R_AARCH64_LD64_GOTOFF_LO15', 'R_AARCH64_LD64_GOTPAGE_LO15', - 'R_AARCH64_LD64_GOT_LO12_NC', 'R_AARCH64_LDST128_ABS_LO12_NC', - 'R_AARCH64_LDST16_ABS_LO12_NC', 'R_AARCH64_LDST32_ABS_LO12_NC', - 'R_AARCH64_LDST64_ABS_LO12_NC', 'R_AARCH64_LDST8_ABS_LO12_NC', - 'R_AARCH64_LD_PREL_LO19', 'R_AARCH64_MOVW_GOTOFF_G0', - 'R_AARCH64_MOVW_GOTOFF_G0_NC', 'R_AARCH64_MOVW_GOTOFF_G1', - 'R_AARCH64_MOVW_GOTOFF_G1_NC', 'R_AARCH64_MOVW_GOTOFF_G2', - 'R_AARCH64_MOVW_GOTOFF_G2_NC', 'R_AARCH64_MOVW_GOTOFF_G3', - 'R_AARCH64_MOVW_PREL_G0', 'R_AARCH64_MOVW_PREL_G0_NC', - 'R_AARCH64_MOVW_PREL_G1', 'R_AARCH64_MOVW_PREL_G1_NC', - 'R_AARCH64_MOVW_PREL_G2', 'R_AARCH64_MOVW_PREL_G2_NC', - 'R_AARCH64_MOVW_PREL_G3', 'R_AARCH64_MOVW_SABS_G0', - 'R_AARCH64_MOVW_SABS_G1', 'R_AARCH64_MOVW_SABS_G2', - 'R_AARCH64_MOVW_UABS_G0', 'R_AARCH64_MOVW_UABS_G0_NC', - 'R_AARCH64_MOVW_UABS_G1', 'R_AARCH64_MOVW_UABS_G1_NC', - 'R_AARCH64_MOVW_UABS_G2', 'R_AARCH64_MOVW_UABS_G2_NC', - 'R_AARCH64_MOVW_UABS_G3', 'R_AARCH64_NONE', 'R_AARCH64_P32_ABS32', - 'R_AARCH64_P32_COPY', 'R_AARCH64_P32_GLOB_DAT', - 'R_AARCH64_P32_IRELATIVE', 'R_AARCH64_P32_JUMP_SLOT', - 'R_AARCH64_P32_RELATIVE', 'R_AARCH64_P32_TLSDESC', - 'R_AARCH64_P32_TLS_DTPMOD', 'R_AARCH64_P32_TLS_DTPREL', - 'R_AARCH64_P32_TLS_TPREL', 'R_AARCH64_PREL16', 'R_AARCH64_PREL32', - 'R_AARCH64_PREL64', 'R_AARCH64_RELATIVE', 'R_AARCH64_TLSDESC', - 'R_AARCH64_TLSDESC_ADD', 'R_AARCH64_TLSDESC_ADD_LO12', - 'R_AARCH64_TLSDESC_ADR_PAGE21', 'R_AARCH64_TLSDESC_ADR_PREL21', - 'R_AARCH64_TLSDESC_CALL', 'R_AARCH64_TLSDESC_LD64_LO12', - 'R_AARCH64_TLSDESC_LDR', 'R_AARCH64_TLSDESC_LD_PREL19', - 'R_AARCH64_TLSDESC_OFF_G0_NC', 'R_AARCH64_TLSDESC_OFF_G1', - 'R_AARCH64_TLSGD_ADD_LO12_NC', 'R_AARCH64_TLSGD_ADR_PAGE21', - 'R_AARCH64_TLSGD_ADR_PREL21', 'R_AARCH64_TLSGD_MOVW_G0_NC', - 'R_AARCH64_TLSGD_MOVW_G1', 'R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21', - 'R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC', - 'R_AARCH64_TLSIE_LD_GOTTPREL_PREL19', - 'R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC', - 'R_AARCH64_TLSIE_MOVW_GOTTPREL_G1', - 'R_AARCH64_TLSLD_ADD_DTPREL_HI12', - 'R_AARCH64_TLSLD_ADD_DTPREL_LO12', - 'R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_ADD_LO12_NC', 'R_AARCH64_TLSLD_ADR_PAGE21', - 'R_AARCH64_TLSLD_ADR_PREL21', - 'R_AARCH64_TLSLD_LDST128_DTPREL_LO12', - 'R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_LDST16_DTPREL_LO12', - 'R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_LDST32_DTPREL_LO12', - 'R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_LDST64_DTPREL_LO12', - 'R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_LDST8_DTPREL_LO12', - 'R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC', - 'R_AARCH64_TLSLD_LD_PREL19', 'R_AARCH64_TLSLD_MOVW_DTPREL_G0', - 'R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC', - 'R_AARCH64_TLSLD_MOVW_DTPREL_G1', - 'R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC', - 'R_AARCH64_TLSLD_MOVW_DTPREL_G2', 'R_AARCH64_TLSLD_MOVW_G0_NC', - 'R_AARCH64_TLSLD_MOVW_G1', 'R_AARCH64_TLSLE_ADD_TPREL_HI12', - 'R_AARCH64_TLSLE_ADD_TPREL_LO12', - 'R_AARCH64_TLSLE_ADD_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_LDST128_TPREL_LO12', - 'R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_LDST16_TPREL_LO12', - 'R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_LDST32_TPREL_LO12', - 'R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_LDST64_TPREL_LO12', - 'R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_LDST8_TPREL_LO12', - 'R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC', - 'R_AARCH64_TLSLE_MOVW_TPREL_G0', - 'R_AARCH64_TLSLE_MOVW_TPREL_G0_NC', - 'R_AARCH64_TLSLE_MOVW_TPREL_G1', - 'R_AARCH64_TLSLE_MOVW_TPREL_G1_NC', - 'R_AARCH64_TLSLE_MOVW_TPREL_G2', 'R_AARCH64_TLS_DTPMOD', - 'R_AARCH64_TLS_DTPREL', 'R_AARCH64_TLS_TPREL', - 'R_AARCH64_TSTBR14', 'R_AC_SECTOFF_S9', 'R_AC_SECTOFF_S9_1', - 'R_AC_SECTOFF_S9_2', 'R_AC_SECTOFF_U8', 'R_AC_SECTOFF_U8_1', - 'R_AC_SECTOFF_U8_2', 'R_ALPHA_BRADDR', 'R_ALPHA_COPY', - 'R_ALPHA_DTPMOD64', 'R_ALPHA_DTPREL16', 'R_ALPHA_DTPREL64', - 'R_ALPHA_DTPRELHI', 'R_ALPHA_DTPRELLO', 'R_ALPHA_GLOB_DAT', - 'R_ALPHA_GOTDTPREL', 'R_ALPHA_GOTTPREL', 'R_ALPHA_GPDISP', - 'R_ALPHA_GPREL16', 'R_ALPHA_GPREL32', 'R_ALPHA_GPRELHIGH', - 'R_ALPHA_GPRELLOW', 'R_ALPHA_HINT', 'R_ALPHA_JMP_SLOT', - 'R_ALPHA_LITERAL', 'R_ALPHA_LITUSE', 'R_ALPHA_NONE', - 'R_ALPHA_NUM', 'R_ALPHA_REFLONG', 'R_ALPHA_REFQUAD', - 'R_ALPHA_RELATIVE', 'R_ALPHA_SREL16', 'R_ALPHA_SREL32', - 'R_ALPHA_SREL64', 'R_ALPHA_TLSGD', 'R_ALPHA_TLS_GD_HI', - 'R_ALPHA_TLS_LDM', 'R_ALPHA_TPREL16', 'R_ALPHA_TPREL64', - 'R_ALPHA_TPRELHI', 'R_ALPHA_TPRELLO', 'R_ARC_16', 'R_ARC_24', - 'R_ARC_32', 'R_ARC_32_ME', 'R_ARC_32_PCREL', 'R_ARC_8', - 'R_ARC_B22_PCREL', 'R_ARC_COPY', 'R_ARC_GLOB_DAT', 'R_ARC_GOT32', - 'R_ARC_GOTOFF', 'R_ARC_GOTPC', 'R_ARC_GOTPC32', 'R_ARC_H30', - 'R_ARC_H30_ME', 'R_ARC_JLI_SECTOFF', 'R_ARC_JMP_SLOT', - 'R_ARC_N16', 'R_ARC_N24', 'R_ARC_N32', 'R_ARC_N32_ME', 'R_ARC_N8', - 'R_ARC_NONE', 'R_ARC_NPS_CMEM16', 'R_ARC_PC32', 'R_ARC_PLT32', - 'R_ARC_RELATIVE', 'R_ARC_S13_PCREL', 'R_ARC_S21H_PCREL', - 'R_ARC_S21H_PCREL_PLT', 'R_ARC_S21W_PCREL', - 'R_ARC_S21W_PCREL_PLT', 'R_ARC_S25H_PCREL', - 'R_ARC_S25H_PCREL_PLT', 'R_ARC_S25W_PCREL', - 'R_ARC_S25W_PCREL_PLT', 'R_ARC_SDA', 'R_ARC_SDA16_LD', - 'R_ARC_SDA16_LD1', 'R_ARC_SDA16_LD2', 'R_ARC_SDA16_ST2', - 'R_ARC_SDA32', 'R_ARC_SDA32_ME', 'R_ARC_SDA_12', 'R_ARC_SDA_LDST', - 'R_ARC_SDA_LDST1', 'R_ARC_SDA_LDST2', 'R_ARC_SECTOFF', - 'R_ARC_SECTOFF_1', 'R_ARC_SECTOFF_2', 'R_ARC_SECTOFF_ME', - 'R_ARC_SECTOFF_ME_1', 'R_ARC_SECTOFF_ME_2', 'R_ARC_SECTOFF_S9', - 'R_ARC_SECTOFF_U8', 'R_ARC_TLS_DTPMOD', 'R_ARC_TLS_DTPOFF', - 'R_ARC_TLS_DTPOFF_S9', 'R_ARC_TLS_GD_CALL', 'R_ARC_TLS_GD_GOT', - 'R_ARC_TLS_GD_LD', 'R_ARC_TLS_IE_GOT', 'R_ARC_TLS_LE_32', - 'R_ARC_TLS_LE_S9', 'R_ARC_TLS_TPOFF', 'R_ARC_W', 'R_ARC_W_ME', - 'R_ARM_ABS12', 'R_ARM_ABS16', 'R_ARM_ABS32', 'R_ARM_ABS32_NOI', - 'R_ARM_ABS8', 'R_ARM_ALU_PCREL_15_8', 'R_ARM_ALU_PCREL_23_15', - 'R_ARM_ALU_PCREL_7_0', 'R_ARM_ALU_PC_G0', 'R_ARM_ALU_PC_G0_NC', - 'R_ARM_ALU_PC_G1', 'R_ARM_ALU_PC_G1_NC', 'R_ARM_ALU_PC_G2', - 'R_ARM_ALU_SBREL_19_12', 'R_ARM_ALU_SBREL_27_20', - 'R_ARM_ALU_SB_G0', 'R_ARM_ALU_SB_G0_NC', 'R_ARM_ALU_SB_G1', - 'R_ARM_ALU_SB_G1_NC', 'R_ARM_ALU_SB_G2', 'R_ARM_AMP_VCALL9', - 'R_ARM_BASE_ABS', 'R_ARM_CALL', 'R_ARM_COPY', 'R_ARM_GLOB_DAT', - 'R_ARM_GNU_VTENTRY', 'R_ARM_GNU_VTINHERIT', 'R_ARM_GOT32', - 'R_ARM_GOTOFF', 'R_ARM_GOTOFF12', 'R_ARM_GOTPC', 'R_ARM_GOTRELAX', - 'R_ARM_GOT_ABS', 'R_ARM_GOT_BREL12', 'R_ARM_GOT_PREL', - 'R_ARM_IRELATIVE', 'R_ARM_JUMP24', 'R_ARM_JUMP_SLOT', - 'R_ARM_LDC_PC_G0', 'R_ARM_LDC_PC_G1', 'R_ARM_LDC_PC_G2', - 'R_ARM_LDC_SB_G0', 'R_ARM_LDC_SB_G1', 'R_ARM_LDC_SB_G2', - 'R_ARM_LDRS_PC_G0', 'R_ARM_LDRS_PC_G1', 'R_ARM_LDRS_PC_G2', - 'R_ARM_LDRS_SB_G0', 'R_ARM_LDRS_SB_G1', 'R_ARM_LDRS_SB_G2', - 'R_ARM_LDR_PC_G1', 'R_ARM_LDR_PC_G2', 'R_ARM_LDR_SBREL_11_0', - 'R_ARM_LDR_SB_G0', 'R_ARM_LDR_SB_G1', 'R_ARM_LDR_SB_G2', - 'R_ARM_ME_TOO', 'R_ARM_MOVT_ABS', 'R_ARM_MOVT_BREL', - 'R_ARM_MOVT_PREL', 'R_ARM_MOVW_ABS_NC', 'R_ARM_MOVW_BREL', - 'R_ARM_MOVW_BREL_NC', 'R_ARM_MOVW_PREL_NC', 'R_ARM_NONE', - 'R_ARM_NUM', 'R_ARM_PC13', 'R_ARM_PC24', 'R_ARM_PLT32', - 'R_ARM_PLT32_ABS', 'R_ARM_PREL31', 'R_ARM_RABS22', 'R_ARM_RBASE', - 'R_ARM_REL32', 'R_ARM_REL32_NOI', 'R_ARM_RELATIVE', 'R_ARM_RPC24', - 'R_ARM_RREL32', 'R_ARM_RSBREL32', 'R_ARM_RXPC25', 'R_ARM_SBREL31', - 'R_ARM_SBREL32', 'R_ARM_SWI24', 'R_ARM_TARGET1', 'R_ARM_TARGET2', - 'R_ARM_THM_ABS5', 'R_ARM_THM_ALU_PREL_11_0', - 'R_ARM_THM_GOT_BREL12', 'R_ARM_THM_JUMP19', 'R_ARM_THM_JUMP24', - 'R_ARM_THM_JUMP6', 'R_ARM_THM_MOVT_ABS', 'R_ARM_THM_MOVT_BREL', - 'R_ARM_THM_MOVT_PREL', 'R_ARM_THM_MOVW_ABS_NC', - 'R_ARM_THM_MOVW_BREL', 'R_ARM_THM_MOVW_BREL_NC', - 'R_ARM_THM_MOVW_PREL_NC', 'R_ARM_THM_PC11', 'R_ARM_THM_PC12', - 'R_ARM_THM_PC22', 'R_ARM_THM_PC8', 'R_ARM_THM_PC9', - 'R_ARM_THM_RPC22', 'R_ARM_THM_SWI8', 'R_ARM_THM_TLS_CALL', - 'R_ARM_THM_TLS_DESCSEQ', 'R_ARM_THM_TLS_DESCSEQ16', - 'R_ARM_THM_TLS_DESCSEQ32', 'R_ARM_THM_XPC22', 'R_ARM_TLS_CALL', - 'R_ARM_TLS_DESC', 'R_ARM_TLS_DESCSEQ', 'R_ARM_TLS_DTPMOD32', - 'R_ARM_TLS_DTPOFF32', 'R_ARM_TLS_GD32', 'R_ARM_TLS_GOTDESC', - 'R_ARM_TLS_IE12GP', 'R_ARM_TLS_IE32', 'R_ARM_TLS_LDM32', - 'R_ARM_TLS_LDO12', 'R_ARM_TLS_LDO32', 'R_ARM_TLS_LE12', - 'R_ARM_TLS_LE32', 'R_ARM_TLS_TPOFF32', 'R_ARM_V4BX', - 'R_ARM_XPC25', 'R_BPF_64_32', 'R_BPF_64_64', 'R_BPF_NONE', - 'R_CKCORE_ADDR32', 'R_CKCORE_ADDRGOT', 'R_CKCORE_ADDRGOT_HI16', - 'R_CKCORE_ADDRGOT_LO16', 'R_CKCORE_ADDRPLT', - 'R_CKCORE_ADDRPLT_HI16', 'R_CKCORE_ADDRPLT_LO16', - 'R_CKCORE_ADDR_HI16', 'R_CKCORE_ADDR_LO16', 'R_CKCORE_COPY', - 'R_CKCORE_DOFFSET_IMM18', 'R_CKCORE_DOFFSET_IMM18BY2', - 'R_CKCORE_DOFFSET_IMM18BY4', 'R_CKCORE_DOFFSET_LO16', - 'R_CKCORE_GLOB_DAT', 'R_CKCORE_GOT12', 'R_CKCORE_GOT32', - 'R_CKCORE_GOTOFF', 'R_CKCORE_GOTOFF_HI16', 'R_CKCORE_GOTOFF_LO16', - 'R_CKCORE_GOTPC', 'R_CKCORE_GOTPC_HI16', 'R_CKCORE_GOTPC_LO16', - 'R_CKCORE_GOT_HI16', 'R_CKCORE_GOT_IMM18BY4', 'R_CKCORE_GOT_LO16', - 'R_CKCORE_JUMP_SLOT', 'R_CKCORE_NONE', 'R_CKCORE_PCREL32', - 'R_CKCORE_PCRELIMM11BY2', 'R_CKCORE_PCRELIMM8BY4', - 'R_CKCORE_PCRELJSR_IMM11BY2', 'R_CKCORE_PCREL_IMM10BY2', - 'R_CKCORE_PCREL_IMM10BY4', 'R_CKCORE_PCREL_IMM16BY2', - 'R_CKCORE_PCREL_IMM16BY4', 'R_CKCORE_PCREL_IMM18BY2', - 'R_CKCORE_PCREL_IMM26BY2', 'R_CKCORE_PCREL_IMM7BY4', - 'R_CKCORE_PCREL_JSR_IMM26BY2', 'R_CKCORE_PLT12', 'R_CKCORE_PLT32', - 'R_CKCORE_PLT_HI16', 'R_CKCORE_PLT_IMM18BY4', 'R_CKCORE_PLT_LO16', - 'R_CKCORE_RELATIVE', 'R_CKCORE_TLS_DTPMOD32', - 'R_CKCORE_TLS_DTPOFF32', 'R_CKCORE_TLS_GD32', 'R_CKCORE_TLS_IE32', - 'R_CKCORE_TLS_LDM32', 'R_CKCORE_TLS_LDO32', 'R_CKCORE_TLS_LE32', - 'R_CKCORE_TLS_TPOFF32', 'R_CKCORE_TOFFSET_LO16', 'R_CRIS_16', - 'R_CRIS_16_GOT', 'R_CRIS_16_GOTPLT', 'R_CRIS_16_PCREL', - 'R_CRIS_32', 'R_CRIS_32_GOT', 'R_CRIS_32_GOTPLT', - 'R_CRIS_32_GOTREL', 'R_CRIS_32_PCREL', 'R_CRIS_32_PLT_GOTREL', - 'R_CRIS_32_PLT_PCREL', 'R_CRIS_8', 'R_CRIS_8_PCREL', - 'R_CRIS_COPY', 'R_CRIS_GLOB_DAT', 'R_CRIS_GNU_VTENTRY', - 'R_CRIS_GNU_VTINHERIT', 'R_CRIS_JUMP_SLOT', 'R_CRIS_NONE', - 'R_CRIS_NUM', 'R_CRIS_RELATIVE', 'R_IA64_COPY', 'R_IA64_DIR32LSB', - 'R_IA64_DIR32MSB', 'R_IA64_DIR64LSB', 'R_IA64_DIR64MSB', - 'R_IA64_DTPMOD64LSB', 'R_IA64_DTPMOD64MSB', 'R_IA64_DTPREL14', - 'R_IA64_DTPREL22', 'R_IA64_DTPREL32LSB', 'R_IA64_DTPREL32MSB', - 'R_IA64_DTPREL64I', 'R_IA64_DTPREL64LSB', 'R_IA64_DTPREL64MSB', - 'R_IA64_FPTR32LSB', 'R_IA64_FPTR32MSB', 'R_IA64_FPTR64I', - 'R_IA64_FPTR64LSB', 'R_IA64_FPTR64MSB', 'R_IA64_GPREL22', - 'R_IA64_GPREL32LSB', 'R_IA64_GPREL32MSB', 'R_IA64_GPREL64I', - 'R_IA64_GPREL64LSB', 'R_IA64_GPREL64MSB', 'R_IA64_IMM14', - 'R_IA64_IMM22', 'R_IA64_IMM64', 'R_IA64_IPLTLSB', - 'R_IA64_IPLTMSB', 'R_IA64_LDXMOV', 'R_IA64_LTOFF22', - 'R_IA64_LTOFF22X', 'R_IA64_LTOFF64I', 'R_IA64_LTOFF_DTPMOD22', - 'R_IA64_LTOFF_DTPREL22', 'R_IA64_LTOFF_FPTR22', - 'R_IA64_LTOFF_FPTR32LSB', 'R_IA64_LTOFF_FPTR32MSB', - 'R_IA64_LTOFF_FPTR64I', 'R_IA64_LTOFF_FPTR64LSB', - 'R_IA64_LTOFF_FPTR64MSB', 'R_IA64_LTOFF_TPREL22', - 'R_IA64_LTV32LSB', 'R_IA64_LTV32MSB', 'R_IA64_LTV64LSB', - 'R_IA64_LTV64MSB', 'R_IA64_NONE', 'R_IA64_PCREL21B', - 'R_IA64_PCREL21BI', 'R_IA64_PCREL21F', 'R_IA64_PCREL21M', - 'R_IA64_PCREL22', 'R_IA64_PCREL32LSB', 'R_IA64_PCREL32MSB', - 'R_IA64_PCREL60B', 'R_IA64_PCREL64I', 'R_IA64_PCREL64LSB', - 'R_IA64_PCREL64MSB', 'R_IA64_PLTOFF22', 'R_IA64_PLTOFF64I', - 'R_IA64_PLTOFF64LSB', 'R_IA64_PLTOFF64MSB', 'R_IA64_REL32LSB', - 'R_IA64_REL32MSB', 'R_IA64_REL64LSB', 'R_IA64_REL64MSB', - 'R_IA64_SECREL32LSB', 'R_IA64_SECREL32MSB', 'R_IA64_SECREL64LSB', - 'R_IA64_SECREL64MSB', 'R_IA64_SEGREL32LSB', 'R_IA64_SEGREL32MSB', - 'R_IA64_SEGREL64LSB', 'R_IA64_SEGREL64MSB', 'R_IA64_SUB', - 'R_IA64_TPREL14', 'R_IA64_TPREL22', 'R_IA64_TPREL64I', - 'R_IA64_TPREL64LSB', 'R_IA64_TPREL64MSB', 'R_LARCH_32', - 'R_LARCH_32_PCREL', 'R_LARCH_64', 'R_LARCH_64_PCREL', - 'R_LARCH_ABS64_HI12', 'R_LARCH_ABS64_LO20', 'R_LARCH_ABS_HI20', - 'R_LARCH_ABS_LO12', 'R_LARCH_ADD16', 'R_LARCH_ADD24', - 'R_LARCH_ADD32', 'R_LARCH_ADD6', 'R_LARCH_ADD64', 'R_LARCH_ADD8', - 'R_LARCH_ADD_ULEB128', 'R_LARCH_ALIGN', 'R_LARCH_B16', - 'R_LARCH_B21', 'R_LARCH_B26', 'R_LARCH_CFA', 'R_LARCH_COPY', - 'R_LARCH_DELETE', 'R_LARCH_GNU_VTENTRY', 'R_LARCH_GNU_VTINHERIT', - 'R_LARCH_GOT64_HI12', 'R_LARCH_GOT64_LO20', - 'R_LARCH_GOT64_PC_HI12', 'R_LARCH_GOT64_PC_LO20', - 'R_LARCH_GOT_HI20', 'R_LARCH_GOT_LO12', 'R_LARCH_GOT_PC_HI20', - 'R_LARCH_GOT_PC_LO12', 'R_LARCH_IRELATIVE', 'R_LARCH_JUMP_SLOT', - 'R_LARCH_MARK_LA', 'R_LARCH_MARK_PCREL', 'R_LARCH_NONE', - 'R_LARCH_PCALA64_HI12', 'R_LARCH_PCALA64_LO20', - 'R_LARCH_PCALA_HI20', 'R_LARCH_PCALA_LO12', 'R_LARCH_PCREL20_S2', - 'R_LARCH_RELATIVE', 'R_LARCH_RELAX', 'R_LARCH_SOP_ADD', - 'R_LARCH_SOP_AND', 'R_LARCH_SOP_ASSERT', 'R_LARCH_SOP_IF_ELSE', - 'R_LARCH_SOP_NOT', 'R_LARCH_SOP_POP_32_S_0_10_10_16_S2', - 'R_LARCH_SOP_POP_32_S_0_5_10_16_S2', 'R_LARCH_SOP_POP_32_S_10_12', - 'R_LARCH_SOP_POP_32_S_10_16', 'R_LARCH_SOP_POP_32_S_10_16_S2', - 'R_LARCH_SOP_POP_32_S_10_5', 'R_LARCH_SOP_POP_32_S_5_20', - 'R_LARCH_SOP_POP_32_U', 'R_LARCH_SOP_POP_32_U_10_12', - 'R_LARCH_SOP_PUSH_ABSOLUTE', 'R_LARCH_SOP_PUSH_DUP', - 'R_LARCH_SOP_PUSH_GPREL', 'R_LARCH_SOP_PUSH_PCREL', - 'R_LARCH_SOP_PUSH_PLT_PCREL', 'R_LARCH_SOP_PUSH_TLS_GD', - 'R_LARCH_SOP_PUSH_TLS_GOT', 'R_LARCH_SOP_PUSH_TLS_TPREL', - 'R_LARCH_SOP_SL', 'R_LARCH_SOP_SR', 'R_LARCH_SOP_SUB', - 'R_LARCH_SUB16', 'R_LARCH_SUB24', 'R_LARCH_SUB32', 'R_LARCH_SUB6', - 'R_LARCH_SUB64', 'R_LARCH_SUB8', 'R_LARCH_SUB_ULEB128', - 'R_LARCH_TLS_DTPMOD32', 'R_LARCH_TLS_DTPMOD64', - 'R_LARCH_TLS_DTPREL32', 'R_LARCH_TLS_DTPREL64', - 'R_LARCH_TLS_GD_HI20', 'R_LARCH_TLS_GD_PC_HI20', - 'R_LARCH_TLS_IE64_HI12', 'R_LARCH_TLS_IE64_LO20', - 'R_LARCH_TLS_IE64_PC_HI12', 'R_LARCH_TLS_IE64_PC_LO20', - 'R_LARCH_TLS_IE_HI20', 'R_LARCH_TLS_IE_LO12', - 'R_LARCH_TLS_IE_PC_HI20', 'R_LARCH_TLS_IE_PC_LO12', - 'R_LARCH_TLS_LD_HI20', 'R_LARCH_TLS_LD_PC_HI20', - 'R_LARCH_TLS_LE64_HI12', 'R_LARCH_TLS_LE64_LO20', - 'R_LARCH_TLS_LE_HI20', 'R_LARCH_TLS_LE_LO12', - 'R_LARCH_TLS_TPREL32', 'R_LARCH_TLS_TPREL64', 'R_M32R_10_PCREL', - 'R_M32R_10_PCREL_RELA', 'R_M32R_16', 'R_M32R_16_RELA', - 'R_M32R_18_PCREL', 'R_M32R_18_PCREL_RELA', 'R_M32R_24', - 'R_M32R_24_RELA', 'R_M32R_26_PCREL', 'R_M32R_26_PCREL_RELA', - 'R_M32R_26_PLTREL', 'R_M32R_32', 'R_M32R_32_RELA', 'R_M32R_COPY', - 'R_M32R_GLOB_DAT', 'R_M32R_GNU_VTENTRY', 'R_M32R_GNU_VTINHERIT', - 'R_M32R_GOT16_HI_SLO', 'R_M32R_GOT16_HI_ULO', 'R_M32R_GOT16_LO', - 'R_M32R_GOT24', 'R_M32R_GOTOFF', 'R_M32R_GOTOFF_HI_SLO', - 'R_M32R_GOTOFF_HI_ULO', 'R_M32R_GOTOFF_LO', 'R_M32R_GOTPC24', - 'R_M32R_GOTPC_HI_SLO', 'R_M32R_GOTPC_HI_ULO', 'R_M32R_GOTPC_LO', - 'R_M32R_HI16_SLO', 'R_M32R_HI16_SLO_RELA', 'R_M32R_HI16_ULO', - 'R_M32R_HI16_ULO_RELA', 'R_M32R_JMP_SLOT', 'R_M32R_LO16', - 'R_M32R_LO16_RELA', 'R_M32R_NONE', 'R_M32R_NUM', 'R_M32R_REL32', - 'R_M32R_RELATIVE', 'R_M32R_RELA_GNU_VTENTRY', - 'R_M32R_RELA_GNU_VTINHERIT', 'R_M32R_SDA16', 'R_M32R_SDA16_RELA', - 'R_METAG_ADDR32', 'R_METAG_COPY', 'R_METAG_GETSETOFF', - 'R_METAG_GETSET_GOT', 'R_METAG_GETSET_GOTOFF', 'R_METAG_GLOB_DAT', - 'R_METAG_GNU_VTENTRY', 'R_METAG_GNU_VTINHERIT', 'R_METAG_GOTOFF', - 'R_METAG_HI16_GOTOFF', 'R_METAG_HI16_GOTPC', 'R_METAG_HI16_PLT', - 'R_METAG_HIADDR16', 'R_METAG_HIOG', 'R_METAG_JMP_SLOT', - 'R_METAG_LO16_GOTOFF', 'R_METAG_LO16_GOTPC', 'R_METAG_LO16_PLT', - 'R_METAG_LOADDR16', 'R_METAG_LOOG', 'R_METAG_NONE', 'R_METAG_PLT', - 'R_METAG_REG16OP1', 'R_METAG_REG16OP2', 'R_METAG_REG16OP3', - 'R_METAG_REG32OP1', 'R_METAG_REG32OP2', 'R_METAG_REG32OP3', - 'R_METAG_REG32OP4', 'R_METAG_REL16', 'R_METAG_REL8', - 'R_METAG_RELATIVE', 'R_METAG_RELBRANCH', 'R_METAG_RELBRANCH_PLT', - 'R_METAG_TLS_DTPMOD', 'R_METAG_TLS_DTPOFF', 'R_METAG_TLS_GD', - 'R_METAG_TLS_IE', 'R_METAG_TLS_IENONPIC', - 'R_METAG_TLS_IENONPIC_HI16', 'R_METAG_TLS_IENONPIC_LO16', - 'R_METAG_TLS_LDM', 'R_METAG_TLS_LDO', 'R_METAG_TLS_LDO_HI16', - 'R_METAG_TLS_LDO_LO16', 'R_METAG_TLS_LE', 'R_METAG_TLS_LE_HI16', - 'R_METAG_TLS_LE_LO16', 'R_METAG_TLS_TPOFF', 'R_MICROBLAZE_32', - 'R_MICROBLAZE_32_LO', 'R_MICROBLAZE_32_PCREL', - 'R_MICROBLAZE_32_PCREL_LO', 'R_MICROBLAZE_32_SYM_OP_SYM', - 'R_MICROBLAZE_64', 'R_MICROBLAZE_64_NONE', - 'R_MICROBLAZE_64_PCREL', 'R_MICROBLAZE_COPY', - 'R_MICROBLAZE_GLOB_DAT', 'R_MICROBLAZE_GNU_VTENTRY', - 'R_MICROBLAZE_GNU_VTINHERIT', 'R_MICROBLAZE_GOTOFF_32', - 'R_MICROBLAZE_GOTOFF_64', 'R_MICROBLAZE_GOTPC_64', - 'R_MICROBLAZE_GOT_64', 'R_MICROBLAZE_JUMP_SLOT', - 'R_MICROBLAZE_NONE', 'R_MICROBLAZE_PLT_64', 'R_MICROBLAZE_REL', - 'R_MICROBLAZE_SRO32', 'R_MICROBLAZE_SRW32', 'R_MICROBLAZE_TLS', - 'R_MICROBLAZE_TLSDTPMOD32', 'R_MICROBLAZE_TLSDTPREL32', - 'R_MICROBLAZE_TLSDTPREL64', 'R_MICROBLAZE_TLSGD', - 'R_MICROBLAZE_TLSGOTTPREL32', 'R_MICROBLAZE_TLSLD', - 'R_MICROBLAZE_TLSTPREL32', 'R_MICROMIPS_26_S1', - 'R_MICROMIPS_CALL16', 'R_MICROMIPS_CALL_HI16', - 'R_MICROMIPS_CALL_LO16', 'R_MICROMIPS_GOT16', - 'R_MICROMIPS_GOT_DISP', 'R_MICROMIPS_GOT_HI16', - 'R_MICROMIPS_GOT_LO16', 'R_MICROMIPS_GOT_OFST', - 'R_MICROMIPS_GOT_PAGE', 'R_MICROMIPS_GPREL16', - 'R_MICROMIPS_GPREL7_S2', 'R_MICROMIPS_HI0_LO16', - 'R_MICROMIPS_HI16', 'R_MICROMIPS_HIGHER', 'R_MICROMIPS_HIGHEST', - 'R_MICROMIPS_JALR', 'R_MICROMIPS_LITERAL', 'R_MICROMIPS_LO16', - 'R_MICROMIPS_PC10_S1', 'R_MICROMIPS_PC16_S1', - 'R_MICROMIPS_PC23_S2', 'R_MICROMIPS_PC7_S1', - 'R_MICROMIPS_SCN_DISP', 'R_MICROMIPS_SUB', - 'R_MICROMIPS_TLS_DTPREL_HI16', 'R_MICROMIPS_TLS_DTPREL_LO16', - 'R_MICROMIPS_TLS_GD', 'R_MICROMIPS_TLS_GOTTPREL', - 'R_MICROMIPS_TLS_LDM', 'R_MICROMIPS_TLS_TPREL_HI16', - 'R_MICROMIPS_TLS_TPREL_LO16', 'R_MIPS16_26', 'R_MIPS16_CALL16', - 'R_MIPS16_GOT16', 'R_MIPS16_GPREL', 'R_MIPS16_HI16', - 'R_MIPS16_LO16', 'R_MIPS16_PC16_S1', 'R_MIPS16_TLS_DTPREL_HI16', - 'R_MIPS16_TLS_DTPREL_LO16', 'R_MIPS16_TLS_GD', - 'R_MIPS16_TLS_GOTTPREL', 'R_MIPS16_TLS_LDM', - 'R_MIPS16_TLS_TPREL_HI16', 'R_MIPS16_TLS_TPREL_LO16', 'R_MIPS_16', - 'R_MIPS_26', 'R_MIPS_32', 'R_MIPS_64', 'R_MIPS_ADD_IMMEDIATE', - 'R_MIPS_CALL16', 'R_MIPS_CALL_HI16', 'R_MIPS_CALL_LO16', - 'R_MIPS_COPY', 'R_MIPS_DELETE', 'R_MIPS_EH', 'R_MIPS_GLOB_DAT', - 'R_MIPS_GNU_REL16_S2', 'R_MIPS_GNU_VTENTRY', - 'R_MIPS_GNU_VTINHERIT', 'R_MIPS_GOT16', 'R_MIPS_GOT_DISP', - 'R_MIPS_GOT_HI16', 'R_MIPS_GOT_LO16', 'R_MIPS_GOT_OFST', - 'R_MIPS_GOT_PAGE', 'R_MIPS_GPREL16', 'R_MIPS_GPREL32', - 'R_MIPS_HI16', 'R_MIPS_HIGHER', 'R_MIPS_HIGHEST', - 'R_MIPS_INSERT_A', 'R_MIPS_INSERT_B', 'R_MIPS_JALR', - 'R_MIPS_JUMP_SLOT', 'R_MIPS_LITERAL', 'R_MIPS_LO16', - 'R_MIPS_NONE', 'R_MIPS_NUM', 'R_MIPS_PC16', 'R_MIPS_PC18_S3', - 'R_MIPS_PC19_S2', 'R_MIPS_PC21_S2', 'R_MIPS_PC26_S2', - 'R_MIPS_PC32', 'R_MIPS_PCHI16', 'R_MIPS_PCLO16', 'R_MIPS_PJUMP', - 'R_MIPS_REL16', 'R_MIPS_REL32', 'R_MIPS_RELATIVE', - 'R_MIPS_RELGOT', 'R_MIPS_SCN_DISP', 'R_MIPS_SHIFT5', - 'R_MIPS_SHIFT6', 'R_MIPS_SUB', 'R_MIPS_TLS_DTPMOD32', - 'R_MIPS_TLS_DTPMOD64', 'R_MIPS_TLS_DTPREL32', - 'R_MIPS_TLS_DTPREL64', 'R_MIPS_TLS_DTPREL_HI16', - 'R_MIPS_TLS_DTPREL_LO16', 'R_MIPS_TLS_GD', 'R_MIPS_TLS_GOTTPREL', - 'R_MIPS_TLS_LDM', 'R_MIPS_TLS_TPREL32', 'R_MIPS_TLS_TPREL64', - 'R_MIPS_TLS_TPREL_HI16', 'R_MIPS_TLS_TPREL_LO16', 'R_MN10300_16', - 'R_MN10300_24', 'R_MN10300_32', 'R_MN10300_8', 'R_MN10300_ALIGN', - 'R_MN10300_COPY', 'R_MN10300_GLOB_DAT', 'R_MN10300_GNU_VTENTRY', - 'R_MN10300_GNU_VTINHERIT', 'R_MN10300_GOT16', 'R_MN10300_GOT24', - 'R_MN10300_GOT32', 'R_MN10300_GOTOFF16', 'R_MN10300_GOTOFF24', - 'R_MN10300_GOTOFF32', 'R_MN10300_GOTPC16', 'R_MN10300_GOTPC32', - 'R_MN10300_JMP_SLOT', 'R_MN10300_NONE', 'R_MN10300_NUM', - 'R_MN10300_PCREL16', 'R_MN10300_PCREL32', 'R_MN10300_PCREL8', - 'R_MN10300_PLT16', 'R_MN10300_PLT32', 'R_MN10300_RELATIVE', - 'R_MN10300_SYM_DIFF', 'R_MN10300_TLS_DTPMOD', - 'R_MN10300_TLS_DTPOFF', 'R_MN10300_TLS_GD', 'R_MN10300_TLS_GOTIE', - 'R_MN10300_TLS_IE', 'R_MN10300_TLS_LD', 'R_MN10300_TLS_LDO', - 'R_MN10300_TLS_LE', 'R_MN10300_TLS_TPOFF', 'R_NDS32_32_RELA', - 'R_NDS32_COPY', 'R_NDS32_GLOB_DAT', 'R_NDS32_JMP_SLOT', - 'R_NDS32_NONE', 'R_NDS32_RELATIVE', 'R_NDS32_TLS_DESC', - 'R_NDS32_TLS_TPOFF', 'R_NIOS2_ALIGN', 'R_NIOS2_BFD_RELOC_16', - 'R_NIOS2_BFD_RELOC_32', 'R_NIOS2_BFD_RELOC_8', - 'R_NIOS2_CACHE_OPX', 'R_NIOS2_CALL16', 'R_NIOS2_CALL26', - 'R_NIOS2_CALL26_NOAT', 'R_NIOS2_CALLR', 'R_NIOS2_CALL_HA', - 'R_NIOS2_CALL_LO', 'R_NIOS2_CJMP', 'R_NIOS2_COPY', - 'R_NIOS2_GLOB_DAT', 'R_NIOS2_GNU_VTENTRY', - 'R_NIOS2_GNU_VTINHERIT', 'R_NIOS2_GOT16', 'R_NIOS2_GOTOFF', - 'R_NIOS2_GOTOFF_HA', 'R_NIOS2_GOTOFF_LO', 'R_NIOS2_GOT_HA', - 'R_NIOS2_GOT_LO', 'R_NIOS2_GPREL', 'R_NIOS2_HI16', - 'R_NIOS2_HIADJ16', 'R_NIOS2_IMM5', 'R_NIOS2_IMM6', 'R_NIOS2_IMM8', - 'R_NIOS2_JUMP_SLOT', 'R_NIOS2_LO16', 'R_NIOS2_NONE', - 'R_NIOS2_PCREL16', 'R_NIOS2_PCREL_HA', 'R_NIOS2_PCREL_LO', - 'R_NIOS2_RELATIVE', 'R_NIOS2_S16', 'R_NIOS2_TLS_DTPMOD', - 'R_NIOS2_TLS_DTPREL', 'R_NIOS2_TLS_GD16', 'R_NIOS2_TLS_IE16', - 'R_NIOS2_TLS_LDM16', 'R_NIOS2_TLS_LDO16', 'R_NIOS2_TLS_LE16', - 'R_NIOS2_TLS_TPREL', 'R_NIOS2_U16', 'R_NIOS2_UJMP', 'R_OK', - 'R_OR1K_16', 'R_OR1K_16_PCREL', 'R_OR1K_32', 'R_OR1K_32_PCREL', - 'R_OR1K_8', 'R_OR1K_8_PCREL', 'R_OR1K_COPY', 'R_OR1K_GLOB_DAT', - 'R_OR1K_GNU_VTENTRY', 'R_OR1K_GNU_VTINHERIT', 'R_OR1K_GOT16', - 'R_OR1K_GOTOFF_HI16', 'R_OR1K_GOTOFF_LO16', 'R_OR1K_GOTPC_HI16', - 'R_OR1K_GOTPC_LO16', 'R_OR1K_HI_16_IN_INSN', 'R_OR1K_INSN_REL_26', - 'R_OR1K_JMP_SLOT', 'R_OR1K_LO_16_IN_INSN', 'R_OR1K_NONE', - 'R_OR1K_PLT26', 'R_OR1K_RELATIVE', 'R_OR1K_TLS_DTPMOD', - 'R_OR1K_TLS_DTPOFF', 'R_OR1K_TLS_GD_HI16', 'R_OR1K_TLS_GD_LO16', - 'R_OR1K_TLS_IE_HI16', 'R_OR1K_TLS_IE_LO16', 'R_OR1K_TLS_LDM_HI16', - 'R_OR1K_TLS_LDM_LO16', 'R_OR1K_TLS_LDO_HI16', - 'R_OR1K_TLS_LDO_LO16', 'R_OR1K_TLS_LE_HI16', 'R_OR1K_TLS_LE_LO16', - 'R_OR1K_TLS_TPOFF', 'R_PARISC_COPY', 'R_PARISC_DIR14DR', - 'R_PARISC_DIR14R', 'R_PARISC_DIR14WR', 'R_PARISC_DIR16DF', - 'R_PARISC_DIR16F', 'R_PARISC_DIR16WF', 'R_PARISC_DIR17F', - 'R_PARISC_DIR17R', 'R_PARISC_DIR21L', 'R_PARISC_DIR32', - 'R_PARISC_DIR64', 'R_PARISC_DPREL14R', 'R_PARISC_DPREL21L', - 'R_PARISC_EPLT', 'R_PARISC_FPTR64', 'R_PARISC_GNU_VTENTRY', - 'R_PARISC_GNU_VTINHERIT', 'R_PARISC_GPREL14DR', - 'R_PARISC_GPREL14R', 'R_PARISC_GPREL14WR', 'R_PARISC_GPREL16DF', - 'R_PARISC_GPREL16F', 'R_PARISC_GPREL16WF', 'R_PARISC_GPREL21L', - 'R_PARISC_GPREL64', 'R_PARISC_HIRESERVE', 'R_PARISC_IPLT', - 'R_PARISC_LORESERVE', 'R_PARISC_LTOFF14DR', 'R_PARISC_LTOFF14R', - 'R_PARISC_LTOFF14WR', 'R_PARISC_LTOFF16DF', 'R_PARISC_LTOFF16F', - 'R_PARISC_LTOFF16WF', 'R_PARISC_LTOFF21L', 'R_PARISC_LTOFF64', - 'R_PARISC_LTOFF_FPTR14DR', 'R_PARISC_LTOFF_FPTR14R', - 'R_PARISC_LTOFF_FPTR14WR', 'R_PARISC_LTOFF_FPTR16DF', - 'R_PARISC_LTOFF_FPTR16F', 'R_PARISC_LTOFF_FPTR16WF', - 'R_PARISC_LTOFF_FPTR21L', 'R_PARISC_LTOFF_FPTR32', - 'R_PARISC_LTOFF_FPTR64', 'R_PARISC_LTOFF_TP14DR', - 'R_PARISC_LTOFF_TP14F', 'R_PARISC_LTOFF_TP14R', - 'R_PARISC_LTOFF_TP14WR', 'R_PARISC_LTOFF_TP16DF', - 'R_PARISC_LTOFF_TP16F', 'R_PARISC_LTOFF_TP16WF', - 'R_PARISC_LTOFF_TP21L', 'R_PARISC_LTOFF_TP64', 'R_PARISC_NONE', - 'R_PARISC_PCREL14DR', 'R_PARISC_PCREL14R', 'R_PARISC_PCREL14WR', - 'R_PARISC_PCREL16DF', 'R_PARISC_PCREL16F', 'R_PARISC_PCREL16WF', - 'R_PARISC_PCREL17F', 'R_PARISC_PCREL17R', 'R_PARISC_PCREL21L', - 'R_PARISC_PCREL22F', 'R_PARISC_PCREL32', 'R_PARISC_PCREL64', - 'R_PARISC_PLABEL14R', 'R_PARISC_PLABEL21L', 'R_PARISC_PLABEL32', - 'R_PARISC_PLTOFF14DR', 'R_PARISC_PLTOFF14R', - 'R_PARISC_PLTOFF14WR', 'R_PARISC_PLTOFF16DF', - 'R_PARISC_PLTOFF16F', 'R_PARISC_PLTOFF16WF', 'R_PARISC_PLTOFF21L', - 'R_PARISC_SECREL32', 'R_PARISC_SECREL64', 'R_PARISC_SEGBASE', - 'R_PARISC_SEGREL32', 'R_PARISC_SEGREL64', 'R_PARISC_TLS_DTPMOD32', - 'R_PARISC_TLS_DTPMOD64', 'R_PARISC_TLS_DTPOFF32', - 'R_PARISC_TLS_DTPOFF64', 'R_PARISC_TLS_GD14R', - 'R_PARISC_TLS_GD21L', 'R_PARISC_TLS_GDCALL', 'R_PARISC_TLS_IE14R', - 'R_PARISC_TLS_IE21L', 'R_PARISC_TLS_LDM14R', - 'R_PARISC_TLS_LDM21L', 'R_PARISC_TLS_LDMCALL', - 'R_PARISC_TLS_LDO14R', 'R_PARISC_TLS_LDO21L', - 'R_PARISC_TLS_LE14R', 'R_PARISC_TLS_LE21L', - 'R_PARISC_TLS_TPREL32', 'R_PARISC_TLS_TPREL64', - 'R_PARISC_TPREL14DR', 'R_PARISC_TPREL14R', 'R_PARISC_TPREL14WR', - 'R_PARISC_TPREL16DF', 'R_PARISC_TPREL16F', 'R_PARISC_TPREL16WF', - 'R_PARISC_TPREL21L', 'R_PARISC_TPREL32', 'R_PARISC_TPREL64', - 'R_PPC64_ADDR14', 'R_PPC64_ADDR14_BRNTAKEN', - 'R_PPC64_ADDR14_BRTAKEN', 'R_PPC64_ADDR16', 'R_PPC64_ADDR16_DS', - 'R_PPC64_ADDR16_HA', 'R_PPC64_ADDR16_HI', 'R_PPC64_ADDR16_HIGH', - 'R_PPC64_ADDR16_HIGHA', 'R_PPC64_ADDR16_HIGHER', - 'R_PPC64_ADDR16_HIGHERA', 'R_PPC64_ADDR16_HIGHEST', - 'R_PPC64_ADDR16_HIGHESTA', 'R_PPC64_ADDR16_LO', - 'R_PPC64_ADDR16_LO_DS', 'R_PPC64_ADDR24', 'R_PPC64_ADDR30', - 'R_PPC64_ADDR32', 'R_PPC64_ADDR64', 'R_PPC64_COPY', - 'R_PPC64_DTPMOD64', 'R_PPC64_DTPREL16', 'R_PPC64_DTPREL16_DS', - 'R_PPC64_DTPREL16_HA', 'R_PPC64_DTPREL16_HI', - 'R_PPC64_DTPREL16_HIGH', 'R_PPC64_DTPREL16_HIGHA', - 'R_PPC64_DTPREL16_HIGHER', 'R_PPC64_DTPREL16_HIGHERA', - 'R_PPC64_DTPREL16_HIGHEST', 'R_PPC64_DTPREL16_HIGHESTA', - 'R_PPC64_DTPREL16_LO', 'R_PPC64_DTPREL16_LO_DS', - 'R_PPC64_DTPREL64', 'R_PPC64_GLOB_DAT', 'R_PPC64_GOT16', - 'R_PPC64_GOT16_DS', 'R_PPC64_GOT16_HA', 'R_PPC64_GOT16_HI', - 'R_PPC64_GOT16_LO', 'R_PPC64_GOT16_LO_DS', - 'R_PPC64_GOT_DTPREL16_DS', 'R_PPC64_GOT_DTPREL16_HA', - 'R_PPC64_GOT_DTPREL16_HI', 'R_PPC64_GOT_DTPREL16_LO_DS', - 'R_PPC64_GOT_TLSGD16', 'R_PPC64_GOT_TLSGD16_HA', - 'R_PPC64_GOT_TLSGD16_HI', 'R_PPC64_GOT_TLSGD16_LO', - 'R_PPC64_GOT_TLSLD16', 'R_PPC64_GOT_TLSLD16_HA', - 'R_PPC64_GOT_TLSLD16_HI', 'R_PPC64_GOT_TLSLD16_LO', - 'R_PPC64_GOT_TPREL16_DS', 'R_PPC64_GOT_TPREL16_HA', - 'R_PPC64_GOT_TPREL16_HI', 'R_PPC64_GOT_TPREL16_LO_DS', - 'R_PPC64_IRELATIVE', 'R_PPC64_JMP_IREL', 'R_PPC64_JMP_SLOT', - 'R_PPC64_NONE', 'R_PPC64_PLT16_HA', 'R_PPC64_PLT16_HI', - 'R_PPC64_PLT16_LO', 'R_PPC64_PLT16_LO_DS', 'R_PPC64_PLT32', - 'R_PPC64_PLT64', 'R_PPC64_PLTGOT16', 'R_PPC64_PLTGOT16_DS', - 'R_PPC64_PLTGOT16_HA', 'R_PPC64_PLTGOT16_HI', - 'R_PPC64_PLTGOT16_LO', 'R_PPC64_PLTGOT16_LO_DS', - 'R_PPC64_PLTREL32', 'R_PPC64_PLTREL64', 'R_PPC64_REL14', - 'R_PPC64_REL14_BRNTAKEN', 'R_PPC64_REL14_BRTAKEN', - 'R_PPC64_REL16', 'R_PPC64_REL16_HA', 'R_PPC64_REL16_HI', - 'R_PPC64_REL16_LO', 'R_PPC64_REL24', 'R_PPC64_REL32', - 'R_PPC64_REL64', 'R_PPC64_RELATIVE', 'R_PPC64_SECTOFF', - 'R_PPC64_SECTOFF_DS', 'R_PPC64_SECTOFF_HA', 'R_PPC64_SECTOFF_HI', - 'R_PPC64_SECTOFF_LO', 'R_PPC64_SECTOFF_LO_DS', 'R_PPC64_TLS', - 'R_PPC64_TLSGD', 'R_PPC64_TLSLD', 'R_PPC64_TOC', 'R_PPC64_TOC16', - 'R_PPC64_TOC16_DS', 'R_PPC64_TOC16_HA', 'R_PPC64_TOC16_HI', - 'R_PPC64_TOC16_LO', 'R_PPC64_TOC16_LO_DS', 'R_PPC64_TOCSAVE', - 'R_PPC64_TPREL16', 'R_PPC64_TPREL16_DS', 'R_PPC64_TPREL16_HA', - 'R_PPC64_TPREL16_HI', 'R_PPC64_TPREL16_HIGH', - 'R_PPC64_TPREL16_HIGHA', 'R_PPC64_TPREL16_HIGHER', - 'R_PPC64_TPREL16_HIGHERA', 'R_PPC64_TPREL16_HIGHEST', - 'R_PPC64_TPREL16_HIGHESTA', 'R_PPC64_TPREL16_LO', - 'R_PPC64_TPREL16_LO_DS', 'R_PPC64_TPREL64', 'R_PPC64_UADDR16', - 'R_PPC64_UADDR32', 'R_PPC64_UADDR64', 'R_PPC_ADDR14', - 'R_PPC_ADDR14_BRNTAKEN', 'R_PPC_ADDR14_BRTAKEN', 'R_PPC_ADDR16', - 'R_PPC_ADDR16_HA', 'R_PPC_ADDR16_HI', 'R_PPC_ADDR16_LO', - 'R_PPC_ADDR24', 'R_PPC_ADDR32', 'R_PPC_COPY', - 'R_PPC_DIAB_RELSDA_HA', 'R_PPC_DIAB_RELSDA_HI', - 'R_PPC_DIAB_RELSDA_LO', 'R_PPC_DIAB_SDA21_HA', - 'R_PPC_DIAB_SDA21_HI', 'R_PPC_DIAB_SDA21_LO', 'R_PPC_DTPMOD32', - 'R_PPC_DTPREL16', 'R_PPC_DTPREL16_HA', 'R_PPC_DTPREL16_HI', - 'R_PPC_DTPREL16_LO', 'R_PPC_DTPREL32', 'R_PPC_EMB_BIT_FLD', - 'R_PPC_EMB_MRKREF', 'R_PPC_EMB_NADDR16', 'R_PPC_EMB_NADDR16_HA', - 'R_PPC_EMB_NADDR16_HI', 'R_PPC_EMB_NADDR16_LO', - 'R_PPC_EMB_NADDR32', 'R_PPC_EMB_RELSDA', 'R_PPC_EMB_RELSEC16', - 'R_PPC_EMB_RELST_HA', 'R_PPC_EMB_RELST_HI', 'R_PPC_EMB_RELST_LO', - 'R_PPC_EMB_SDA21', 'R_PPC_EMB_SDA2I16', 'R_PPC_EMB_SDA2REL', - 'R_PPC_EMB_SDAI16', 'R_PPC_GLOB_DAT', 'R_PPC_GOT16', - 'R_PPC_GOT16_HA', 'R_PPC_GOT16_HI', 'R_PPC_GOT16_LO', - 'R_PPC_GOT_DTPREL16', 'R_PPC_GOT_DTPREL16_HA', - 'R_PPC_GOT_DTPREL16_HI', 'R_PPC_GOT_DTPREL16_LO', - 'R_PPC_GOT_TLSGD16', 'R_PPC_GOT_TLSGD16_HA', - 'R_PPC_GOT_TLSGD16_HI', 'R_PPC_GOT_TLSGD16_LO', - 'R_PPC_GOT_TLSLD16', 'R_PPC_GOT_TLSLD16_HA', - 'R_PPC_GOT_TLSLD16_HI', 'R_PPC_GOT_TLSLD16_LO', - 'R_PPC_GOT_TPREL16', 'R_PPC_GOT_TPREL16_HA', - 'R_PPC_GOT_TPREL16_HI', 'R_PPC_GOT_TPREL16_LO', 'R_PPC_IRELATIVE', - 'R_PPC_JMP_SLOT', 'R_PPC_LOCAL24PC', 'R_PPC_NONE', - 'R_PPC_PLT16_HA', 'R_PPC_PLT16_HI', 'R_PPC_PLT16_LO', - 'R_PPC_PLT32', 'R_PPC_PLTREL24', 'R_PPC_PLTREL32', 'R_PPC_REL14', - 'R_PPC_REL14_BRNTAKEN', 'R_PPC_REL14_BRTAKEN', 'R_PPC_REL16', - 'R_PPC_REL16_HA', 'R_PPC_REL16_HI', 'R_PPC_REL16_LO', - 'R_PPC_REL24', 'R_PPC_REL32', 'R_PPC_RELATIVE', 'R_PPC_SDAREL16', - 'R_PPC_SECTOFF', 'R_PPC_SECTOFF_HA', 'R_PPC_SECTOFF_HI', - 'R_PPC_SECTOFF_LO', 'R_PPC_TLS', 'R_PPC_TLSGD', 'R_PPC_TLSLD', - 'R_PPC_TOC16', 'R_PPC_TPREL16', 'R_PPC_TPREL16_HA', - 'R_PPC_TPREL16_HI', 'R_PPC_TPREL16_LO', 'R_PPC_TPREL32', - 'R_PPC_UADDR16', 'R_PPC_UADDR32', 'R_RISCV_32', - 'R_RISCV_32_PCREL', 'R_RISCV_64', 'R_RISCV_ADD16', - 'R_RISCV_ADD32', 'R_RISCV_ADD64', 'R_RISCV_ADD8', 'R_RISCV_ALIGN', - 'R_RISCV_BRANCH', 'R_RISCV_CALL', 'R_RISCV_CALL_PLT', - 'R_RISCV_COPY', 'R_RISCV_GNU_VTENTRY', 'R_RISCV_GNU_VTINHERIT', - 'R_RISCV_GOT_HI20', 'R_RISCV_GPREL_I', 'R_RISCV_GPREL_S', - 'R_RISCV_HI20', 'R_RISCV_IRELATIVE', 'R_RISCV_JAL', - 'R_RISCV_JUMP_SLOT', 'R_RISCV_LO12_I', 'R_RISCV_LO12_S', - 'R_RISCV_NONE', 'R_RISCV_NUM', 'R_RISCV_PCREL_HI20', - 'R_RISCV_PCREL_LO12_I', 'R_RISCV_PCREL_LO12_S', 'R_RISCV_PLT32', - 'R_RISCV_RELATIVE', 'R_RISCV_RELAX', 'R_RISCV_RVC_BRANCH', - 'R_RISCV_RVC_JUMP', 'R_RISCV_RVC_LUI', 'R_RISCV_SET16', - 'R_RISCV_SET32', 'R_RISCV_SET6', 'R_RISCV_SET8', - 'R_RISCV_SET_ULEB128', 'R_RISCV_SUB16', 'R_RISCV_SUB32', - 'R_RISCV_SUB6', 'R_RISCV_SUB64', 'R_RISCV_SUB8', - 'R_RISCV_SUB_ULEB128', 'R_RISCV_TLS_DTPMOD32', - 'R_RISCV_TLS_DTPMOD64', 'R_RISCV_TLS_DTPREL32', - 'R_RISCV_TLS_DTPREL64', 'R_RISCV_TLS_GD_HI20', - 'R_RISCV_TLS_GOT_HI20', 'R_RISCV_TLS_TPREL32', - 'R_RISCV_TLS_TPREL64', 'R_RISCV_TPREL_ADD', 'R_RISCV_TPREL_HI20', - 'R_RISCV_TPREL_I', 'R_RISCV_TPREL_LO12_I', 'R_RISCV_TPREL_LO12_S', - 'R_RISCV_TPREL_S', 'R_SH_ALIGN', 'R_SH_CODE', 'R_SH_COPY', - 'R_SH_COUNT', 'R_SH_DATA', 'R_SH_DIR32', 'R_SH_DIR8BP', - 'R_SH_DIR8L', 'R_SH_DIR8W', 'R_SH_DIR8WPL', 'R_SH_DIR8WPN', - 'R_SH_DIR8WPZ', 'R_SH_GLOB_DAT', 'R_SH_GNU_VTENTRY', - 'R_SH_GNU_VTINHERIT', 'R_SH_GOT32', 'R_SH_GOTOFF', 'R_SH_GOTPC', - 'R_SH_IND12W', 'R_SH_JMP_SLOT', 'R_SH_LABEL', 'R_SH_NONE', - 'R_SH_NUM', 'R_SH_PLT32', 'R_SH_REL32', 'R_SH_RELATIVE', - 'R_SH_SWITCH16', 'R_SH_SWITCH32', 'R_SH_SWITCH8', - 'R_SH_TLS_DTPMOD32', 'R_SH_TLS_DTPOFF32', 'R_SH_TLS_GD_32', - 'R_SH_TLS_IE_32', 'R_SH_TLS_LDO_32', 'R_SH_TLS_LD_32', - 'R_SH_TLS_LE_32', 'R_SH_TLS_TPOFF32', 'R_SH_USES', 'R_SPARC_10', - 'R_SPARC_11', 'R_SPARC_13', 'R_SPARC_16', 'R_SPARC_22', - 'R_SPARC_32', 'R_SPARC_5', 'R_SPARC_6', 'R_SPARC_64', 'R_SPARC_7', - 'R_SPARC_8', 'R_SPARC_COPY', 'R_SPARC_DISP16', 'R_SPARC_DISP32', - 'R_SPARC_DISP64', 'R_SPARC_DISP8', 'R_SPARC_GLOB_DAT', - 'R_SPARC_GLOB_JMP', 'R_SPARC_GNU_VTENTRY', - 'R_SPARC_GNU_VTINHERIT', 'R_SPARC_GOT10', 'R_SPARC_GOT13', - 'R_SPARC_GOT22', 'R_SPARC_GOTDATA_HIX22', 'R_SPARC_GOTDATA_LOX10', - 'R_SPARC_GOTDATA_OP', 'R_SPARC_GOTDATA_OP_HIX22', - 'R_SPARC_GOTDATA_OP_LOX10', 'R_SPARC_H34', 'R_SPARC_H44', - 'R_SPARC_HH22', 'R_SPARC_HI22', 'R_SPARC_HIPLT22', - 'R_SPARC_HIX22', 'R_SPARC_HM10', 'R_SPARC_IRELATIVE', - 'R_SPARC_JMP_IREL', 'R_SPARC_JMP_SLOT', 'R_SPARC_L44', - 'R_SPARC_LM22', 'R_SPARC_LO10', 'R_SPARC_LOPLT10', - 'R_SPARC_LOX10', 'R_SPARC_M44', 'R_SPARC_NONE', 'R_SPARC_NUM', - 'R_SPARC_OLO10', 'R_SPARC_PC10', 'R_SPARC_PC22', - 'R_SPARC_PCPLT10', 'R_SPARC_PCPLT22', 'R_SPARC_PCPLT32', - 'R_SPARC_PC_HH22', 'R_SPARC_PC_HM10', 'R_SPARC_PC_LM22', - 'R_SPARC_PLT32', 'R_SPARC_PLT64', 'R_SPARC_REGISTER', - 'R_SPARC_RELATIVE', 'R_SPARC_REV32', 'R_SPARC_SIZE32', - 'R_SPARC_SIZE64', 'R_SPARC_TLS_DTPMOD32', 'R_SPARC_TLS_DTPMOD64', - 'R_SPARC_TLS_DTPOFF32', 'R_SPARC_TLS_DTPOFF64', - 'R_SPARC_TLS_GD_ADD', 'R_SPARC_TLS_GD_CALL', - 'R_SPARC_TLS_GD_HI22', 'R_SPARC_TLS_GD_LO10', - 'R_SPARC_TLS_IE_ADD', 'R_SPARC_TLS_IE_HI22', 'R_SPARC_TLS_IE_LD', - 'R_SPARC_TLS_IE_LDX', 'R_SPARC_TLS_IE_LO10', - 'R_SPARC_TLS_LDM_ADD', 'R_SPARC_TLS_LDM_CALL', - 'R_SPARC_TLS_LDM_HI22', 'R_SPARC_TLS_LDM_LO10', - 'R_SPARC_TLS_LDO_ADD', 'R_SPARC_TLS_LDO_HIX22', - 'R_SPARC_TLS_LDO_LOX10', 'R_SPARC_TLS_LE_HIX22', - 'R_SPARC_TLS_LE_LOX10', 'R_SPARC_TLS_TPOFF32', - 'R_SPARC_TLS_TPOFF64', 'R_SPARC_UA16', 'R_SPARC_UA32', - 'R_SPARC_UA64', 'R_SPARC_WDISP10', 'R_SPARC_WDISP16', - 'R_SPARC_WDISP19', 'R_SPARC_WDISP22', 'R_SPARC_WDISP30', - 'R_SPARC_WPLT30', 'R_TILEGX_16', 'R_TILEGX_16_PCREL', - 'R_TILEGX_32', 'R_TILEGX_32_PCREL', 'R_TILEGX_64', - 'R_TILEGX_64_PCREL', 'R_TILEGX_8', 'R_TILEGX_8_PCREL', - 'R_TILEGX_BROFF_X1', 'R_TILEGX_COPY', 'R_TILEGX_DEST_IMM8_X1', - 'R_TILEGX_GLOB_DAT', 'R_TILEGX_GNU_VTENTRY', - 'R_TILEGX_GNU_VTINHERIT', 'R_TILEGX_HW0', 'R_TILEGX_HW0_LAST', - 'R_TILEGX_HW1', 'R_TILEGX_HW1_LAST', 'R_TILEGX_HW2', - 'R_TILEGX_HW2_LAST', 'R_TILEGX_HW3', 'R_TILEGX_IMM16_X0_HW0', - 'R_TILEGX_IMM16_X0_HW0_GOT', 'R_TILEGX_IMM16_X0_HW0_LAST', - 'R_TILEGX_IMM16_X0_HW0_LAST_GOT', - 'R_TILEGX_IMM16_X0_HW0_LAST_PCREL', - 'R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD', - 'R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE', - 'R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE', - 'R_TILEGX_IMM16_X0_HW0_PCREL', 'R_TILEGX_IMM16_X0_HW0_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW0_TLS_GD', 'R_TILEGX_IMM16_X0_HW0_TLS_IE', - 'R_TILEGX_IMM16_X0_HW0_TLS_LE', 'R_TILEGX_IMM16_X0_HW1', - 'R_TILEGX_IMM16_X0_HW1_LAST', 'R_TILEGX_IMM16_X0_HW1_LAST_GOT', - 'R_TILEGX_IMM16_X0_HW1_LAST_PCREL', - 'R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD', - 'R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE', - 'R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE', - 'R_TILEGX_IMM16_X0_HW1_PCREL', 'R_TILEGX_IMM16_X0_HW1_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW2', 'R_TILEGX_IMM16_X0_HW2_LAST', - 'R_TILEGX_IMM16_X0_HW2_LAST_PCREL', - 'R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW2_PCREL', 'R_TILEGX_IMM16_X0_HW2_PLT_PCREL', - 'R_TILEGX_IMM16_X0_HW3', 'R_TILEGX_IMM16_X0_HW3_PCREL', - 'R_TILEGX_IMM16_X0_HW3_PLT_PCREL', 'R_TILEGX_IMM16_X1_HW0', - 'R_TILEGX_IMM16_X1_HW0_GOT', 'R_TILEGX_IMM16_X1_HW0_LAST', - 'R_TILEGX_IMM16_X1_HW0_LAST_GOT', - 'R_TILEGX_IMM16_X1_HW0_LAST_PCREL', - 'R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD', - 'R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE', - 'R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE', - 'R_TILEGX_IMM16_X1_HW0_PCREL', 'R_TILEGX_IMM16_X1_HW0_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW0_TLS_GD', 'R_TILEGX_IMM16_X1_HW0_TLS_IE', - 'R_TILEGX_IMM16_X1_HW0_TLS_LE', 'R_TILEGX_IMM16_X1_HW1', - 'R_TILEGX_IMM16_X1_HW1_LAST', 'R_TILEGX_IMM16_X1_HW1_LAST_GOT', - 'R_TILEGX_IMM16_X1_HW1_LAST_PCREL', - 'R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD', - 'R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE', - 'R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE', - 'R_TILEGX_IMM16_X1_HW1_PCREL', 'R_TILEGX_IMM16_X1_HW1_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW2', 'R_TILEGX_IMM16_X1_HW2_LAST', - 'R_TILEGX_IMM16_X1_HW2_LAST_PCREL', - 'R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW2_PCREL', 'R_TILEGX_IMM16_X1_HW2_PLT_PCREL', - 'R_TILEGX_IMM16_X1_HW3', 'R_TILEGX_IMM16_X1_HW3_PCREL', - 'R_TILEGX_IMM16_X1_HW3_PLT_PCREL', 'R_TILEGX_IMM8_X0', - 'R_TILEGX_IMM8_X0_TLS_ADD', 'R_TILEGX_IMM8_X0_TLS_GD_ADD', - 'R_TILEGX_IMM8_X1', 'R_TILEGX_IMM8_X1_TLS_ADD', - 'R_TILEGX_IMM8_X1_TLS_GD_ADD', 'R_TILEGX_IMM8_Y0', - 'R_TILEGX_IMM8_Y0_TLS_ADD', 'R_TILEGX_IMM8_Y0_TLS_GD_ADD', - 'R_TILEGX_IMM8_Y1', 'R_TILEGX_IMM8_Y1_TLS_ADD', - 'R_TILEGX_IMM8_Y1_TLS_GD_ADD', 'R_TILEGX_JMP_SLOT', - 'R_TILEGX_JUMPOFF_X1', 'R_TILEGX_JUMPOFF_X1_PLT', - 'R_TILEGX_MF_IMM14_X1', 'R_TILEGX_MMEND_X0', - 'R_TILEGX_MMSTART_X0', 'R_TILEGX_MT_IMM14_X1', 'R_TILEGX_NONE', - 'R_TILEGX_NUM', 'R_TILEGX_RELATIVE', 'R_TILEGX_SHAMT_X0', - 'R_TILEGX_SHAMT_X1', 'R_TILEGX_SHAMT_Y0', 'R_TILEGX_SHAMT_Y1', - 'R_TILEGX_TLS_DTPMOD32', 'R_TILEGX_TLS_DTPMOD64', - 'R_TILEGX_TLS_DTPOFF32', 'R_TILEGX_TLS_DTPOFF64', - 'R_TILEGX_TLS_GD_CALL', 'R_TILEGX_TLS_IE_LOAD', - 'R_TILEGX_TLS_TPOFF32', 'R_TILEGX_TLS_TPOFF64', 'R_TILEPRO_16', - 'R_TILEPRO_16_PCREL', 'R_TILEPRO_32', 'R_TILEPRO_32_PCREL', - 'R_TILEPRO_8', 'R_TILEPRO_8_PCREL', 'R_TILEPRO_BROFF_X1', - 'R_TILEPRO_COPY', 'R_TILEPRO_DEST_IMM8_X1', 'R_TILEPRO_GLOB_DAT', - 'R_TILEPRO_GNU_VTENTRY', 'R_TILEPRO_GNU_VTINHERIT', - 'R_TILEPRO_HA16', 'R_TILEPRO_HI16', 'R_TILEPRO_IMM16_X0', - 'R_TILEPRO_IMM16_X0_GOT', 'R_TILEPRO_IMM16_X0_GOT_HA', - 'R_TILEPRO_IMM16_X0_GOT_HI', 'R_TILEPRO_IMM16_X0_GOT_LO', - 'R_TILEPRO_IMM16_X0_HA', 'R_TILEPRO_IMM16_X0_HA_PCREL', - 'R_TILEPRO_IMM16_X0_HI', 'R_TILEPRO_IMM16_X0_HI_PCREL', - 'R_TILEPRO_IMM16_X0_LO', 'R_TILEPRO_IMM16_X0_LO_PCREL', - 'R_TILEPRO_IMM16_X0_PCREL', 'R_TILEPRO_IMM16_X0_TLS_GD', - 'R_TILEPRO_IMM16_X0_TLS_GD_HA', 'R_TILEPRO_IMM16_X0_TLS_GD_HI', - 'R_TILEPRO_IMM16_X0_TLS_GD_LO', 'R_TILEPRO_IMM16_X0_TLS_IE', - 'R_TILEPRO_IMM16_X0_TLS_IE_HA', 'R_TILEPRO_IMM16_X0_TLS_IE_HI', - 'R_TILEPRO_IMM16_X0_TLS_IE_LO', 'R_TILEPRO_IMM16_X0_TLS_LE', - 'R_TILEPRO_IMM16_X0_TLS_LE_HA', 'R_TILEPRO_IMM16_X0_TLS_LE_HI', - 'R_TILEPRO_IMM16_X0_TLS_LE_LO', 'R_TILEPRO_IMM16_X1', - 'R_TILEPRO_IMM16_X1_GOT', 'R_TILEPRO_IMM16_X1_GOT_HA', - 'R_TILEPRO_IMM16_X1_GOT_HI', 'R_TILEPRO_IMM16_X1_GOT_LO', - 'R_TILEPRO_IMM16_X1_HA', 'R_TILEPRO_IMM16_X1_HA_PCREL', - 'R_TILEPRO_IMM16_X1_HI', 'R_TILEPRO_IMM16_X1_HI_PCREL', - 'R_TILEPRO_IMM16_X1_LO', 'R_TILEPRO_IMM16_X1_LO_PCREL', - 'R_TILEPRO_IMM16_X1_PCREL', 'R_TILEPRO_IMM16_X1_TLS_GD', - 'R_TILEPRO_IMM16_X1_TLS_GD_HA', 'R_TILEPRO_IMM16_X1_TLS_GD_HI', - 'R_TILEPRO_IMM16_X1_TLS_GD_LO', 'R_TILEPRO_IMM16_X1_TLS_IE', - 'R_TILEPRO_IMM16_X1_TLS_IE_HA', 'R_TILEPRO_IMM16_X1_TLS_IE_HI', - 'R_TILEPRO_IMM16_X1_TLS_IE_LO', 'R_TILEPRO_IMM16_X1_TLS_LE', - 'R_TILEPRO_IMM16_X1_TLS_LE_HA', 'R_TILEPRO_IMM16_X1_TLS_LE_HI', - 'R_TILEPRO_IMM16_X1_TLS_LE_LO', 'R_TILEPRO_IMM8_X0', - 'R_TILEPRO_IMM8_X0_TLS_GD_ADD', 'R_TILEPRO_IMM8_X1', - 'R_TILEPRO_IMM8_X1_TLS_GD_ADD', 'R_TILEPRO_IMM8_Y0', - 'R_TILEPRO_IMM8_Y0_TLS_GD_ADD', 'R_TILEPRO_IMM8_Y1', - 'R_TILEPRO_IMM8_Y1_TLS_GD_ADD', 'R_TILEPRO_JMP_SLOT', - 'R_TILEPRO_JOFFLONG_X1', 'R_TILEPRO_JOFFLONG_X1_PLT', - 'R_TILEPRO_LO16', 'R_TILEPRO_MF_IMM15_X1', 'R_TILEPRO_MMEND_X0', - 'R_TILEPRO_MMEND_X1', 'R_TILEPRO_MMSTART_X0', - 'R_TILEPRO_MMSTART_X1', 'R_TILEPRO_MT_IMM15_X1', 'R_TILEPRO_NONE', - 'R_TILEPRO_NUM', 'R_TILEPRO_RELATIVE', 'R_TILEPRO_SHAMT_X0', - 'R_TILEPRO_SHAMT_X1', 'R_TILEPRO_SHAMT_Y0', 'R_TILEPRO_SHAMT_Y1', - 'R_TILEPRO_TLS_DTPMOD32', 'R_TILEPRO_TLS_DTPOFF32', - 'R_TILEPRO_TLS_GD_CALL', 'R_TILEPRO_TLS_IE_LOAD', - 'R_TILEPRO_TLS_TPOFF32', 'R_X86_64_16', 'R_X86_64_32', - 'R_X86_64_32S', 'R_X86_64_64', 'R_X86_64_8', 'R_X86_64_COPY', - 'R_X86_64_DTPMOD64', 'R_X86_64_DTPOFF32', 'R_X86_64_DTPOFF64', - 'R_X86_64_GLOB_DAT', 'R_X86_64_GOT32', 'R_X86_64_GOT64', - 'R_X86_64_GOTOFF64', 'R_X86_64_GOTPC32', - 'R_X86_64_GOTPC32_TLSDESC', 'R_X86_64_GOTPC64', - 'R_X86_64_GOTPCREL', 'R_X86_64_GOTPCREL64', 'R_X86_64_GOTPCRELX', - 'R_X86_64_GOTPLT64', 'R_X86_64_GOTTPOFF', 'R_X86_64_IRELATIVE', - 'R_X86_64_JUMP_SLOT', 'R_X86_64_NONE', 'R_X86_64_NUM', - 'R_X86_64_PC16', 'R_X86_64_PC32', 'R_X86_64_PC64', 'R_X86_64_PC8', - 'R_X86_64_PLT32', 'R_X86_64_PLTOFF64', 'R_X86_64_RELATIVE', - 'R_X86_64_RELATIVE64', 'R_X86_64_REX_GOTPCRELX', - 'R_X86_64_SIZE32', 'R_X86_64_SIZE64', 'R_X86_64_TLSDESC', - 'R_X86_64_TLSDESC_CALL', 'R_X86_64_TLSGD', 'R_X86_64_TLSLD', - 'R_X86_64_TPOFF32', 'R_X86_64_TPOFF64', 'SEEK_CUR', 'SEEK_END', - 'SEEK_SET', 'SELFMAG', 'SHF_ALLOC', 'SHF_ALPHA_GPREL', - 'SHF_ARM_COMDEF', 'SHF_ARM_ENTRYSECT', 'SHF_COMPRESSED', - 'SHF_EXCLUDE', 'SHF_EXECINSTR', 'SHF_GNU_RETAIN', 'SHF_GROUP', - 'SHF_IA_64_NORECOV', 'SHF_IA_64_SHORT', 'SHF_INFO_LINK', - 'SHF_LINK_ORDER', 'SHF_MASKOS', 'SHF_MASKPROC', 'SHF_MERGE', - 'SHF_MIPS_ADDR', 'SHF_MIPS_GPREL', 'SHF_MIPS_LOCAL', - 'SHF_MIPS_MERGE', 'SHF_MIPS_NAMES', 'SHF_MIPS_NODUPE', - 'SHF_MIPS_NOSTRIP', 'SHF_MIPS_STRINGS', 'SHF_ORDERED', - 'SHF_OS_NONCONFORMING', 'SHF_PARISC_HUGE', 'SHF_PARISC_SBP', - 'SHF_PARISC_SHORT', 'SHF_STRINGS', 'SHF_TLS', 'SHF_WRITE', - 'SHN_ABS', 'SHN_AFTER', 'SHN_BEFORE', 'SHN_COMMON', 'SHN_HIOS', - 'SHN_HIPROC', 'SHN_HIRESERVE', 'SHN_LOOS', 'SHN_LOPROC', - 'SHN_LORESERVE', 'SHN_MIPS_ACOMMON', 'SHN_MIPS_DATA', - 'SHN_MIPS_SCOMMON', 'SHN_MIPS_SUNDEFINED', 'SHN_MIPS_TEXT', - 'SHN_PARISC_ANSI_COMMON', 'SHN_PARISC_HUGE_COMMON', 'SHN_UNDEF', - 'SHN_XINDEX', 'SHT_ALPHA_DEBUG', 'SHT_ALPHA_REGINFO', - 'SHT_ARC_ATTRIBUTES', 'SHT_ARM_ATTRIBUTES', 'SHT_ARM_EXIDX', - 'SHT_ARM_PREEMPTMAP', 'SHT_CHECKSUM', 'SHT_CSKY_ATTRIBUTES', - 'SHT_DYNAMIC', 'SHT_DYNSYM', 'SHT_FINI_ARRAY', - 'SHT_GNU_ATTRIBUTES', 'SHT_GNU_HASH', 'SHT_GNU_LIBLIST', - 'SHT_GNU_verdef', 'SHT_GNU_verneed', 'SHT_GNU_versym', - 'SHT_GROUP', 'SHT_HASH', 'SHT_HIOS', 'SHT_HIPROC', 'SHT_HISUNW', - 'SHT_HIUSER', 'SHT_IA_64_EXT', 'SHT_IA_64_UNWIND', - 'SHT_INIT_ARRAY', 'SHT_LOOS', 'SHT_LOPROC', 'SHT_LOSUNW', - 'SHT_LOUSER', 'SHT_MIPS_ABIFLAGS', 'SHT_MIPS_AUXSYM', - 'SHT_MIPS_CONFLICT', 'SHT_MIPS_CONTENT', 'SHT_MIPS_DEBUG', - 'SHT_MIPS_DELTACLASS', 'SHT_MIPS_DELTADECL', 'SHT_MIPS_DELTAINST', - 'SHT_MIPS_DELTASYM', 'SHT_MIPS_DENSE', 'SHT_MIPS_DWARF', - 'SHT_MIPS_EH_REGION', 'SHT_MIPS_EVENTS', 'SHT_MIPS_EXTSYM', - 'SHT_MIPS_FDESC', 'SHT_MIPS_GPTAB', 'SHT_MIPS_IFACE', - 'SHT_MIPS_LIBLIST', 'SHT_MIPS_LINE', 'SHT_MIPS_LOCSTR', - 'SHT_MIPS_LOCSYM', 'SHT_MIPS_MSYM', 'SHT_MIPS_OPTIONS', - 'SHT_MIPS_OPTSYM', 'SHT_MIPS_PACKAGE', 'SHT_MIPS_PACKSYM', - 'SHT_MIPS_PDESC', 'SHT_MIPS_PDR_EXCEPTION', 'SHT_MIPS_PIXIE', - 'SHT_MIPS_REGINFO', 'SHT_MIPS_RELD', 'SHT_MIPS_RFDESC', - 'SHT_MIPS_SHDR', 'SHT_MIPS_SYMBOL_LIB', 'SHT_MIPS_TRANSLATE', - 'SHT_MIPS_UCODE', 'SHT_MIPS_WHIRL', 'SHT_MIPS_XHASH', - 'SHT_MIPS_XLATE', 'SHT_MIPS_XLATE_DEBUG', 'SHT_MIPS_XLATE_OLD', - 'SHT_NOBITS', 'SHT_NOTE', 'SHT_NULL', 'SHT_NUM', 'SHT_PARISC_DOC', - 'SHT_PARISC_EXT', 'SHT_PARISC_UNWIND', 'SHT_PREINIT_ARRAY', - 'SHT_PROGBITS', 'SHT_REL', 'SHT_RELA', 'SHT_RELR', - 'SHT_RISCV_ATTRIBUTES', 'SHT_SHLIB', 'SHT_STRTAB', - 'SHT_SUNW_COMDAT', 'SHT_SUNW_move', 'SHT_SUNW_syminfo', - 'SHT_SYMTAB', 'SHT_SYMTAB_SHNDX', 'SHT_X86_64_UNWIND', - 'STB_GLOBAL', 'STB_GNU_UNIQUE', 'STB_HIOS', 'STB_HIPROC', - 'STB_LOCAL', 'STB_LOOS', 'STB_LOPROC', 'STB_MIPS_SPLIT_COMMON', - 'STB_NUM', 'STB_WEAK', 'STDERR_FILENO', 'STDIN_FILENO', - 'STDOUT_FILENO', 'STN_UNDEF', 'STO_AARCH64_VARIANT_PCS', - 'STO_ALPHA_NOPV', 'STO_ALPHA_STD_GPLOAD', 'STO_MIPS_DEFAULT', - 'STO_MIPS_HIDDEN', 'STO_MIPS_INTERNAL', 'STO_MIPS_PLT', - 'STO_MIPS_PROTECTED', 'STO_MIPS_SC_ALIGN_UNUSED', - 'STO_PPC64_LOCAL_BIT', 'STO_PPC64_LOCAL_MASK', - 'STO_RISCV_VARIANT_CC', 'STT_ARM_16BIT', 'STT_ARM_TFUNC', - 'STT_COMMON', 'STT_FILE', 'STT_FUNC', 'STT_GNU_IFUNC', 'STT_HIOS', - 'STT_HIPROC', 'STT_HP_OPAQUE', 'STT_HP_STUB', 'STT_LOOS', - 'STT_LOPROC', 'STT_NOTYPE', 'STT_NUM', 'STT_OBJECT', - 'STT_PARISC_MILLICODE', 'STT_SECTION', 'STT_SPARC_REGISTER', - 'STT_TLS', 'STV_DEFAULT', 'STV_HIDDEN', 'STV_INTERNAL', - 'STV_PROTECTED', 'SYMINFO_BT_LOWRESERVE', 'SYMINFO_BT_PARENT', - 'SYMINFO_BT_SELF', 'SYMINFO_CURRENT', 'SYMINFO_FLG_COPY', - 'SYMINFO_FLG_DIRECT', 'SYMINFO_FLG_LAZYLOAD', - 'SYMINFO_FLG_PASSTHRU', 'SYMINFO_NONE', 'SYMINFO_NUM', - 'VER_DEF_CURRENT', 'VER_DEF_NONE', 'VER_DEF_NUM', 'VER_FLG_BASE', - 'VER_FLG_WEAK', 'VER_NDX_ELIMINATE', 'VER_NDX_GLOBAL', - 'VER_NDX_LOCAL', 'VER_NDX_LORESERVE', 'VER_NEED_CURRENT', - 'VER_NEED_NONE', 'VER_NEED_NUM', 'Val_GNU_MIPS_ABI_FP_64', - 'Val_GNU_MIPS_ABI_FP_64A', 'Val_GNU_MIPS_ABI_FP_ANY', - 'Val_GNU_MIPS_ABI_FP_DOUBLE', 'Val_GNU_MIPS_ABI_FP_MAX', - 'Val_GNU_MIPS_ABI_FP_OLD_64', 'Val_GNU_MIPS_ABI_FP_SINGLE', - 'Val_GNU_MIPS_ABI_FP_SOFT', 'Val_GNU_MIPS_ABI_FP_XX', 'W_OK', - 'X_OK', '_ELF_H', '_POSIX2_C_BIND', '_POSIX2_C_DEV', - '_POSIX2_C_VERSION', '_POSIX2_LOCALEDEF', '_POSIX2_SW_DEV', - '_POSIX2_VERSION', '_POSIX_VERSION', '_STRING_H', '_SYSCALL_H', - '_SYS_MMAN_H', '_UNISTD_H', '_XOPEN_ENH_I18N', '_XOPEN_LEGACY', - '_XOPEN_UNIX', '_XOPEN_VERSION', '_XOPEN_XCU_VERSION', - '_XOPEN_XPG2', '_XOPEN_XPG3', '_XOPEN_XPG4', - '__ASM_GENERIC_MMAN_COMMON_H', - '__GLIBC_INTERNAL_STARTING_HEADER_IMPLEMENTATION', - '__POSIX2_THIS_VERSION', '__environ', '__getpgid', '__gid_t', - '__gid_t_defined', '__intptr_t_defined', '__memcmpeq', - '__mempcpy', '__mode_t_defined', '__need_NULL', '__need_size_t', - '__off_t', '__off_t_defined', '__pid_t', '__pid_t_defined', - '__socklen_t_defined', '__ssize_t_defined', '__stpcpy', - '__stpncpy', '__strtok_r', '__uid_t', '__uid_t_defined', - '__useconds_t', '__useconds_t_defined', '_exit', 'access', 'acct', - 'alarm', 'brk', 'c__Ea_Val_GNU_MIPS_ABI_FP_ANY', 'chdir', 'chown', - 'chroot', 'close', 'closefrom', 'confstr', 'crypt', 'daemon', - 'dup', 'dup2', 'endusershell', 'execl', 'execle', 'execlp', - 'execv', 'execve', 'execvp', 'explicit_bzero', 'faccessat', - 'fchdir', 'fchown', 'fchownat', 'fdatasync', 'fexecve', 'fork', - 'fpathconf', 'fsync', 'ftruncate', 'getcwd', 'getdomainname', - 'getdtablesize', 'getegid', 'getentropy', 'geteuid', 'getgid', - 'getgroups', 'gethostid', 'gethostname', 'getlogin', 'getlogin_r', - 'getpagesize', 'getpass', 'getpgid', 'getpgrp', 'getpid', - 'getppid', 'getsid', 'getuid', 'getusershell', 'getwd', 'gid_t', - 'intptr_t', 'isatty', 'lchown', 'link', 'linkat', 'locale_t', - 'lockf', 'lseek', 'madvise', 'memccpy', 'memchr', 'memcmp', - 'memcpy', 'memmem', 'memmove', 'mempcpy', 'memset', 'mincore', - 'mlock', 'mlockall', 'mmap', 'mode_t', 'mprotect', 'msync', - 'munlock', 'munlockall', 'munmap', 'nice', 'off_t', 'pathconf', - 'pause', 'pid_t', 'pipe', 'posix_madvise', 'pread', 'profil', - 'pwrite', 'read', 'readlink', 'readlinkat', 'revoke', 'rmdir', - 'sbrk', 'setdomainname', 'setegid', 'seteuid', 'setgid', - 'sethostid', 'sethostname', 'setlogin', 'setpgid', 'setpgrp', - 'setregid', 'setreuid', 'setsid', 'setuid', 'setusershell', - 'shm_open', 'shm_unlink', 'size_t', 'sleep', 'socklen_t', - 'ssize_t', 'stpcpy', 'stpncpy', 'strcasestr', 'strcat', 'strchr', - 'strchrnul', 'strcmp', 'strcoll', 'strcoll_l', 'strcpy', - 'strcspn', 'strdup', 'strerror', 'strerror_l', 'strerror_r', - 'strlcat', 'strlcpy', 'strlen', 'strncat', 'strncmp', 'strncpy', - 'strndup', 'strnlen', 'strpbrk', 'strrchr', 'strsep', 'strsignal', - 'strspn', 'strstr', 'strtok', 'strtok_r', 'struct___locale_data', - 'struct___locale_struct', 'struct_c__SA_Elf32_Chdr', - 'struct_c__SA_Elf32_Dyn', 'struct_c__SA_Elf32_Ehdr', - 'struct_c__SA_Elf32_Lib', 'struct_c__SA_Elf32_Move', - 'struct_c__SA_Elf32_Nhdr', 'struct_c__SA_Elf32_Phdr', - 'struct_c__SA_Elf32_RegInfo', 'struct_c__SA_Elf32_Rel', - 'struct_c__SA_Elf32_Rela', 'struct_c__SA_Elf32_Shdr', - 'struct_c__SA_Elf32_Sym', 'struct_c__SA_Elf32_Syminfo', - 'struct_c__SA_Elf32_Verdaux', 'struct_c__SA_Elf32_Verdef', - 'struct_c__SA_Elf32_Vernaux', 'struct_c__SA_Elf32_Verneed', - 'struct_c__SA_Elf32_auxv_t', 'struct_c__SA_Elf64_Chdr', - 'struct_c__SA_Elf64_Dyn', 'struct_c__SA_Elf64_Ehdr', - 'struct_c__SA_Elf64_Lib', 'struct_c__SA_Elf64_Move', - 'struct_c__SA_Elf64_Nhdr', 'struct_c__SA_Elf64_Phdr', - 'struct_c__SA_Elf64_Rel', 'struct_c__SA_Elf64_Rela', - 'struct_c__SA_Elf64_Shdr', 'struct_c__SA_Elf64_Sym', - 'struct_c__SA_Elf64_Syminfo', 'struct_c__SA_Elf64_Verdaux', - 'struct_c__SA_Elf64_Verdef', 'struct_c__SA_Elf64_Vernaux', - 'struct_c__SA_Elf64_Verneed', 'struct_c__SA_Elf64_auxv_t', - 'struct_c__SA_Elf_MIPS_ABIFlags_v0', 'struct_c__SA_Elf_Options', - 'struct_c__SA_Elf_Options_Hw', - 'struct_c__UA_Elf32_gptab_gt_entry', - 'struct_c__UA_Elf32_gptab_gt_header', 'strxfrm', 'strxfrm_l', - 'symlink', 'symlinkat', 'sync', 'syscall', 'sysconf', 'tcgetpgrp', - 'tcsetpgrp', 'truncate', 'ttyname', 'ttyname_r', 'ttyslot', - 'ualarm', 'uid_t', 'union_c__SA_Elf32_Dyn_d_un', - 'union_c__SA_Elf32_auxv_t_a_un', 'union_c__SA_Elf64_Dyn_d_un', - 'union_c__SA_Elf64_auxv_t_a_un', 'union_c__UA_Elf32_gptab', - 'unlink', 'unlinkat', 'useconds_t', 'usleep', 'vfork', 'vhangup', - 'write'] diff --git a/tinygrad/tinygrad/runtime/autogen/libusb.py b/tinygrad/tinygrad/runtime/autogen/libusb.py deleted file mode 100644 index c516ef6d..00000000 --- a/tinygrad/tinygrad/runtime/autogen/libusb.py +++ /dev/null @@ -1,1643 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['libusb'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['libusb'] = None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path) # ctypes.CDLL('libusb') -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -LIBUSB_H = True # macro -ZERO_SIZED_ARRAY = True # macro -# def LIBUSB_DEPRECATED_FOR(f): # macro -# return ((deprecated)) -# LIBUSB_PACKED = ((packed)) # macro -LIBUSB_CALL = True # macro -LIBUSB_API_VERSION = 0x01000109 # macro -LIBUSBX_API_VERSION = 0x01000109 # macro -LIBUSB_DT_DEVICE_SIZE = 18 # macro -LIBUSB_DT_CONFIG_SIZE = 9 # macro -LIBUSB_DT_INTERFACE_SIZE = 9 # macro -LIBUSB_DT_ENDPOINT_SIZE = 7 # macro -LIBUSB_DT_ENDPOINT_AUDIO_SIZE = 9 # macro -LIBUSB_DT_HUB_NONVAR_SIZE = 7 # macro -LIBUSB_DT_SS_ENDPOINT_COMPANION_SIZE = 6 # macro -LIBUSB_DT_BOS_SIZE = 5 # macro -LIBUSB_DT_DEVICE_CAPABILITY_SIZE = 3 # macro -LIBUSB_BT_USB_2_0_EXTENSION_SIZE = 7 # macro -LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE = 10 # macro -LIBUSB_BT_CONTAINER_ID_SIZE = 20 # macro -LIBUSB_DT_BOS_MAX_SIZE = (5+7+10+20) # macro -LIBUSB_ENDPOINT_ADDRESS_MASK = 0x0f # macro -LIBUSB_ENDPOINT_DIR_MASK = 0x80 # macro -LIBUSB_TRANSFER_TYPE_MASK = 0x03 # macro -LIBUSB_ISO_SYNC_TYPE_MASK = 0x0c # macro -LIBUSB_ISO_USAGE_TYPE_MASK = 0x30 # macro -LIBUSB_ERROR_COUNT = 14 # macro -LIBUSB_HOTPLUG_NO_FLAGS = 0 # macro -LIBUSB_HOTPLUG_MATCH_ANY = -1 # macro -uint16_t = ctypes.c_uint16 -try: - libusb_cpu_to_le16 = _libraries['libusb'].libusb_cpu_to_le16 - libusb_cpu_to_le16.restype = uint16_t - libusb_cpu_to_le16.argtypes = [uint16_t] -except AttributeError: - pass - # macro - -# values for enumeration 'libusb_class_code' -libusb_class_code__enumvalues = { - 0: 'LIBUSB_CLASS_PER_INTERFACE', - 1: 'LIBUSB_CLASS_AUDIO', - 2: 'LIBUSB_CLASS_COMM', - 3: 'LIBUSB_CLASS_HID', - 5: 'LIBUSB_CLASS_PHYSICAL', - 6: 'LIBUSB_CLASS_IMAGE', - 6: 'LIBUSB_CLASS_PTP', - 7: 'LIBUSB_CLASS_PRINTER', - 8: 'LIBUSB_CLASS_MASS_STORAGE', - 9: 'LIBUSB_CLASS_HUB', - 10: 'LIBUSB_CLASS_DATA', - 11: 'LIBUSB_CLASS_SMART_CARD', - 13: 'LIBUSB_CLASS_CONTENT_SECURITY', - 14: 'LIBUSB_CLASS_VIDEO', - 15: 'LIBUSB_CLASS_PERSONAL_HEALTHCARE', - 220: 'LIBUSB_CLASS_DIAGNOSTIC_DEVICE', - 224: 'LIBUSB_CLASS_WIRELESS', - 239: 'LIBUSB_CLASS_MISCELLANEOUS', - 254: 'LIBUSB_CLASS_APPLICATION', - 255: 'LIBUSB_CLASS_VENDOR_SPEC', -} -LIBUSB_CLASS_PER_INTERFACE = 0 -LIBUSB_CLASS_AUDIO = 1 -LIBUSB_CLASS_COMM = 2 -LIBUSB_CLASS_HID = 3 -LIBUSB_CLASS_PHYSICAL = 5 -LIBUSB_CLASS_IMAGE = 6 -LIBUSB_CLASS_PTP = 6 -LIBUSB_CLASS_PRINTER = 7 -LIBUSB_CLASS_MASS_STORAGE = 8 -LIBUSB_CLASS_HUB = 9 -LIBUSB_CLASS_DATA = 10 -LIBUSB_CLASS_SMART_CARD = 11 -LIBUSB_CLASS_CONTENT_SECURITY = 13 -LIBUSB_CLASS_VIDEO = 14 -LIBUSB_CLASS_PERSONAL_HEALTHCARE = 15 -LIBUSB_CLASS_DIAGNOSTIC_DEVICE = 220 -LIBUSB_CLASS_WIRELESS = 224 -LIBUSB_CLASS_MISCELLANEOUS = 239 -LIBUSB_CLASS_APPLICATION = 254 -LIBUSB_CLASS_VENDOR_SPEC = 255 -libusb_class_code = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_descriptor_type' -libusb_descriptor_type__enumvalues = { - 1: 'LIBUSB_DT_DEVICE', - 2: 'LIBUSB_DT_CONFIG', - 3: 'LIBUSB_DT_STRING', - 4: 'LIBUSB_DT_INTERFACE', - 5: 'LIBUSB_DT_ENDPOINT', - 15: 'LIBUSB_DT_BOS', - 16: 'LIBUSB_DT_DEVICE_CAPABILITY', - 33: 'LIBUSB_DT_HID', - 34: 'LIBUSB_DT_REPORT', - 35: 'LIBUSB_DT_PHYSICAL', - 41: 'LIBUSB_DT_HUB', - 42: 'LIBUSB_DT_SUPERSPEED_HUB', - 48: 'LIBUSB_DT_SS_ENDPOINT_COMPANION', -} -LIBUSB_DT_DEVICE = 1 -LIBUSB_DT_CONFIG = 2 -LIBUSB_DT_STRING = 3 -LIBUSB_DT_INTERFACE = 4 -LIBUSB_DT_ENDPOINT = 5 -LIBUSB_DT_BOS = 15 -LIBUSB_DT_DEVICE_CAPABILITY = 16 -LIBUSB_DT_HID = 33 -LIBUSB_DT_REPORT = 34 -LIBUSB_DT_PHYSICAL = 35 -LIBUSB_DT_HUB = 41 -LIBUSB_DT_SUPERSPEED_HUB = 42 -LIBUSB_DT_SS_ENDPOINT_COMPANION = 48 -libusb_descriptor_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_endpoint_direction' -libusb_endpoint_direction__enumvalues = { - 0: 'LIBUSB_ENDPOINT_OUT', - 128: 'LIBUSB_ENDPOINT_IN', -} -LIBUSB_ENDPOINT_OUT = 0 -LIBUSB_ENDPOINT_IN = 128 -libusb_endpoint_direction = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_endpoint_transfer_type' -libusb_endpoint_transfer_type__enumvalues = { - 0: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL', - 1: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS', - 2: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK', - 3: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT', -} -LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL = 0 -LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS = 1 -LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK = 2 -LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT = 3 -libusb_endpoint_transfer_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_standard_request' -libusb_standard_request__enumvalues = { - 0: 'LIBUSB_REQUEST_GET_STATUS', - 1: 'LIBUSB_REQUEST_CLEAR_FEATURE', - 3: 'LIBUSB_REQUEST_SET_FEATURE', - 5: 'LIBUSB_REQUEST_SET_ADDRESS', - 6: 'LIBUSB_REQUEST_GET_DESCRIPTOR', - 7: 'LIBUSB_REQUEST_SET_DESCRIPTOR', - 8: 'LIBUSB_REQUEST_GET_CONFIGURATION', - 9: 'LIBUSB_REQUEST_SET_CONFIGURATION', - 10: 'LIBUSB_REQUEST_GET_INTERFACE', - 11: 'LIBUSB_REQUEST_SET_INTERFACE', - 12: 'LIBUSB_REQUEST_SYNCH_FRAME', - 48: 'LIBUSB_REQUEST_SET_SEL', - 49: 'LIBUSB_SET_ISOCH_DELAY', -} -LIBUSB_REQUEST_GET_STATUS = 0 -LIBUSB_REQUEST_CLEAR_FEATURE = 1 -LIBUSB_REQUEST_SET_FEATURE = 3 -LIBUSB_REQUEST_SET_ADDRESS = 5 -LIBUSB_REQUEST_GET_DESCRIPTOR = 6 -LIBUSB_REQUEST_SET_DESCRIPTOR = 7 -LIBUSB_REQUEST_GET_CONFIGURATION = 8 -LIBUSB_REQUEST_SET_CONFIGURATION = 9 -LIBUSB_REQUEST_GET_INTERFACE = 10 -LIBUSB_REQUEST_SET_INTERFACE = 11 -LIBUSB_REQUEST_SYNCH_FRAME = 12 -LIBUSB_REQUEST_SET_SEL = 48 -LIBUSB_SET_ISOCH_DELAY = 49 -libusb_standard_request = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_request_type' -libusb_request_type__enumvalues = { - 0: 'LIBUSB_REQUEST_TYPE_STANDARD', - 32: 'LIBUSB_REQUEST_TYPE_CLASS', - 64: 'LIBUSB_REQUEST_TYPE_VENDOR', - 96: 'LIBUSB_REQUEST_TYPE_RESERVED', -} -LIBUSB_REQUEST_TYPE_STANDARD = 0 -LIBUSB_REQUEST_TYPE_CLASS = 32 -LIBUSB_REQUEST_TYPE_VENDOR = 64 -LIBUSB_REQUEST_TYPE_RESERVED = 96 -libusb_request_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_request_recipient' -libusb_request_recipient__enumvalues = { - 0: 'LIBUSB_RECIPIENT_DEVICE', - 1: 'LIBUSB_RECIPIENT_INTERFACE', - 2: 'LIBUSB_RECIPIENT_ENDPOINT', - 3: 'LIBUSB_RECIPIENT_OTHER', -} -LIBUSB_RECIPIENT_DEVICE = 0 -LIBUSB_RECIPIENT_INTERFACE = 1 -LIBUSB_RECIPIENT_ENDPOINT = 2 -LIBUSB_RECIPIENT_OTHER = 3 -libusb_request_recipient = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_iso_sync_type' -libusb_iso_sync_type__enumvalues = { - 0: 'LIBUSB_ISO_SYNC_TYPE_NONE', - 1: 'LIBUSB_ISO_SYNC_TYPE_ASYNC', - 2: 'LIBUSB_ISO_SYNC_TYPE_ADAPTIVE', - 3: 'LIBUSB_ISO_SYNC_TYPE_SYNC', -} -LIBUSB_ISO_SYNC_TYPE_NONE = 0 -LIBUSB_ISO_SYNC_TYPE_ASYNC = 1 -LIBUSB_ISO_SYNC_TYPE_ADAPTIVE = 2 -LIBUSB_ISO_SYNC_TYPE_SYNC = 3 -libusb_iso_sync_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_iso_usage_type' -libusb_iso_usage_type__enumvalues = { - 0: 'LIBUSB_ISO_USAGE_TYPE_DATA', - 1: 'LIBUSB_ISO_USAGE_TYPE_FEEDBACK', - 2: 'LIBUSB_ISO_USAGE_TYPE_IMPLICIT', -} -LIBUSB_ISO_USAGE_TYPE_DATA = 0 -LIBUSB_ISO_USAGE_TYPE_FEEDBACK = 1 -LIBUSB_ISO_USAGE_TYPE_IMPLICIT = 2 -libusb_iso_usage_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_supported_speed' -libusb_supported_speed__enumvalues = { - 1: 'LIBUSB_LOW_SPEED_OPERATION', - 2: 'LIBUSB_FULL_SPEED_OPERATION', - 4: 'LIBUSB_HIGH_SPEED_OPERATION', - 8: 'LIBUSB_SUPER_SPEED_OPERATION', -} -LIBUSB_LOW_SPEED_OPERATION = 1 -LIBUSB_FULL_SPEED_OPERATION = 2 -LIBUSB_HIGH_SPEED_OPERATION = 4 -LIBUSB_SUPER_SPEED_OPERATION = 8 -libusb_supported_speed = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_usb_2_0_extension_attributes' -libusb_usb_2_0_extension_attributes__enumvalues = { - 2: 'LIBUSB_BM_LPM_SUPPORT', -} -LIBUSB_BM_LPM_SUPPORT = 2 -libusb_usb_2_0_extension_attributes = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_ss_usb_device_capability_attributes' -libusb_ss_usb_device_capability_attributes__enumvalues = { - 2: 'LIBUSB_BM_LTM_SUPPORT', -} -LIBUSB_BM_LTM_SUPPORT = 2 -libusb_ss_usb_device_capability_attributes = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_bos_type' -libusb_bos_type__enumvalues = { - 1: 'LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY', - 2: 'LIBUSB_BT_USB_2_0_EXTENSION', - 3: 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY', - 4: 'LIBUSB_BT_CONTAINER_ID', -} -LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY = 1 -LIBUSB_BT_USB_2_0_EXTENSION = 2 -LIBUSB_BT_SS_USB_DEVICE_CAPABILITY = 3 -LIBUSB_BT_CONTAINER_ID = 4 -libusb_bos_type = ctypes.c_uint32 # enum -class struct_libusb_device_descriptor(Structure): - pass - -struct_libusb_device_descriptor._pack_ = 1 # source:False -struct_libusb_device_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bcdUSB', ctypes.c_uint16), - ('bDeviceClass', ctypes.c_ubyte), - ('bDeviceSubClass', ctypes.c_ubyte), - ('bDeviceProtocol', ctypes.c_ubyte), - ('bMaxPacketSize0', ctypes.c_ubyte), - ('idVendor', ctypes.c_uint16), - ('idProduct', ctypes.c_uint16), - ('bcdDevice', ctypes.c_uint16), - ('iManufacturer', ctypes.c_ubyte), - ('iProduct', ctypes.c_ubyte), - ('iSerialNumber', ctypes.c_ubyte), - ('bNumConfigurations', ctypes.c_ubyte), -] - -class struct_libusb_endpoint_descriptor(Structure): - pass - -struct_libusb_endpoint_descriptor._pack_ = 1 # source:False -struct_libusb_endpoint_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bEndpointAddress', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wMaxPacketSize', ctypes.c_uint16), - ('bInterval', ctypes.c_ubyte), - ('bRefresh', ctypes.c_ubyte), - ('bSynchAddress', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_libusb_interface_descriptor(Structure): - pass - -struct_libusb_interface_descriptor._pack_ = 1 # source:False -struct_libusb_interface_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bInterfaceNumber', ctypes.c_ubyte), - ('bAlternateSetting', ctypes.c_ubyte), - ('bNumEndpoints', ctypes.c_ubyte), - ('bInterfaceClass', ctypes.c_ubyte), - ('bInterfaceSubClass', ctypes.c_ubyte), - ('bInterfaceProtocol', ctypes.c_ubyte), - ('iInterface', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('endpoint', ctypes.POINTER(struct_libusb_endpoint_descriptor)), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_libusb_interface(Structure): - pass - -struct_libusb_interface._pack_ = 1 # source:False -struct_libusb_interface._fields_ = [ - ('altsetting', ctypes.POINTER(struct_libusb_interface_descriptor)), - ('num_altsetting', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_libusb_config_descriptor(Structure): - pass - -struct_libusb_config_descriptor._pack_ = 1 # source:False -struct_libusb_config_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('wTotalLength', ctypes.c_uint16), - ('bNumInterfaces', ctypes.c_ubyte), - ('bConfigurationValue', ctypes.c_ubyte), - ('iConfiguration', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('MaxPower', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('interface', ctypes.POINTER(struct_libusb_interface)), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_libusb_ss_endpoint_companion_descriptor(Structure): - pass - -struct_libusb_ss_endpoint_companion_descriptor._pack_ = 1 # source:False -struct_libusb_ss_endpoint_companion_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bMaxBurst', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wBytesPerInterval', ctypes.c_uint16), -] - -class struct_libusb_bos_dev_capability_descriptor(Structure): - pass - -struct_libusb_bos_dev_capability_descriptor._pack_ = 1 # source:False -struct_libusb_bos_dev_capability_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('dev_capability_data', ctypes.c_ubyte * 0), -] - -class struct_libusb_bos_descriptor(Structure): - pass - -struct_libusb_bos_descriptor._pack_ = 1 # source:False -struct_libusb_bos_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('wTotalLength', ctypes.c_uint16), - ('bNumDeviceCaps', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('dev_capability', ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor) * 0), -] - -class struct_libusb_usb_2_0_extension_descriptor(Structure): - pass - -struct_libusb_usb_2_0_extension_descriptor._pack_ = 1 # source:False -struct_libusb_usb_2_0_extension_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_uint32), -] - -class struct_libusb_ss_usb_device_capability_descriptor(Structure): - pass - -struct_libusb_ss_usb_device_capability_descriptor._pack_ = 1 # source:False -struct_libusb_ss_usb_device_capability_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wSpeedSupported', ctypes.c_uint16), - ('bFunctionalitySupport', ctypes.c_ubyte), - ('bU1DevExitLat', ctypes.c_ubyte), - ('bU2DevExitLat', ctypes.c_uint16), -] - -class struct_libusb_container_id_descriptor(Structure): - pass - -struct_libusb_container_id_descriptor._pack_ = 1 # source:False -struct_libusb_container_id_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('bReserved', ctypes.c_ubyte), - ('ContainerID', ctypes.c_ubyte * 16), -] - -class struct_libusb_control_setup(Structure): - pass - -struct_libusb_control_setup._pack_ = 1 # source:True -struct_libusb_control_setup._fields_ = [ - ('bmRequestType', ctypes.c_ubyte), - ('bRequest', ctypes.c_ubyte), - ('wValue', ctypes.c_uint16), - ('wIndex', ctypes.c_uint16), - ('wLength', ctypes.c_uint16), -] - -# LIBUSB_CONTROL_SETUP_SIZE = (ctypes.sizeof(struct_libusb_control_setup)) # macro -class struct_libusb_context(Structure): - pass - -class struct_libusb_device(Structure): - pass - -class struct_libusb_device_handle(Structure): - pass - -class struct_libusb_version(Structure): - pass - -struct_libusb_version._pack_ = 1 # source:False -struct_libusb_version._fields_ = [ - ('major', ctypes.c_uint16), - ('minor', ctypes.c_uint16), - ('micro', ctypes.c_uint16), - ('nano', ctypes.c_uint16), - ('rc', ctypes.POINTER(ctypes.c_char)), - ('describe', ctypes.POINTER(ctypes.c_char)), -] - -libusb_context = struct_libusb_context -libusb_device = struct_libusb_device -libusb_device_handle = struct_libusb_device_handle - -# values for enumeration 'libusb_speed' -libusb_speed__enumvalues = { - 0: 'LIBUSB_SPEED_UNKNOWN', - 1: 'LIBUSB_SPEED_LOW', - 2: 'LIBUSB_SPEED_FULL', - 3: 'LIBUSB_SPEED_HIGH', - 4: 'LIBUSB_SPEED_SUPER', - 5: 'LIBUSB_SPEED_SUPER_PLUS', -} -LIBUSB_SPEED_UNKNOWN = 0 -LIBUSB_SPEED_LOW = 1 -LIBUSB_SPEED_FULL = 2 -LIBUSB_SPEED_HIGH = 3 -LIBUSB_SPEED_SUPER = 4 -LIBUSB_SPEED_SUPER_PLUS = 5 -libusb_speed = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_error' -libusb_error__enumvalues = { - 0: 'LIBUSB_SUCCESS', - -1: 'LIBUSB_ERROR_IO', - -2: 'LIBUSB_ERROR_INVALID_PARAM', - -3: 'LIBUSB_ERROR_ACCESS', - -4: 'LIBUSB_ERROR_NO_DEVICE', - -5: 'LIBUSB_ERROR_NOT_FOUND', - -6: 'LIBUSB_ERROR_BUSY', - -7: 'LIBUSB_ERROR_TIMEOUT', - -8: 'LIBUSB_ERROR_OVERFLOW', - -9: 'LIBUSB_ERROR_PIPE', - -10: 'LIBUSB_ERROR_INTERRUPTED', - -11: 'LIBUSB_ERROR_NO_MEM', - -12: 'LIBUSB_ERROR_NOT_SUPPORTED', - -99: 'LIBUSB_ERROR_OTHER', -} -LIBUSB_SUCCESS = 0 -LIBUSB_ERROR_IO = -1 -LIBUSB_ERROR_INVALID_PARAM = -2 -LIBUSB_ERROR_ACCESS = -3 -LIBUSB_ERROR_NO_DEVICE = -4 -LIBUSB_ERROR_NOT_FOUND = -5 -LIBUSB_ERROR_BUSY = -6 -LIBUSB_ERROR_TIMEOUT = -7 -LIBUSB_ERROR_OVERFLOW = -8 -LIBUSB_ERROR_PIPE = -9 -LIBUSB_ERROR_INTERRUPTED = -10 -LIBUSB_ERROR_NO_MEM = -11 -LIBUSB_ERROR_NOT_SUPPORTED = -12 -LIBUSB_ERROR_OTHER = -99 -libusb_error = ctypes.c_int32 # enum - -# values for enumeration 'libusb_transfer_type' -libusb_transfer_type__enumvalues = { - 0: 'LIBUSB_TRANSFER_TYPE_CONTROL', - 1: 'LIBUSB_TRANSFER_TYPE_ISOCHRONOUS', - 2: 'LIBUSB_TRANSFER_TYPE_BULK', - 3: 'LIBUSB_TRANSFER_TYPE_INTERRUPT', - 4: 'LIBUSB_TRANSFER_TYPE_BULK_STREAM', -} -LIBUSB_TRANSFER_TYPE_CONTROL = 0 -LIBUSB_TRANSFER_TYPE_ISOCHRONOUS = 1 -LIBUSB_TRANSFER_TYPE_BULK = 2 -LIBUSB_TRANSFER_TYPE_INTERRUPT = 3 -LIBUSB_TRANSFER_TYPE_BULK_STREAM = 4 -libusb_transfer_type = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_transfer_status' -libusb_transfer_status__enumvalues = { - 0: 'LIBUSB_TRANSFER_COMPLETED', - 1: 'LIBUSB_TRANSFER_ERROR', - 2: 'LIBUSB_TRANSFER_TIMED_OUT', - 3: 'LIBUSB_TRANSFER_CANCELLED', - 4: 'LIBUSB_TRANSFER_STALL', - 5: 'LIBUSB_TRANSFER_NO_DEVICE', - 6: 'LIBUSB_TRANSFER_OVERFLOW', -} -LIBUSB_TRANSFER_COMPLETED = 0 -LIBUSB_TRANSFER_ERROR = 1 -LIBUSB_TRANSFER_TIMED_OUT = 2 -LIBUSB_TRANSFER_CANCELLED = 3 -LIBUSB_TRANSFER_STALL = 4 -LIBUSB_TRANSFER_NO_DEVICE = 5 -LIBUSB_TRANSFER_OVERFLOW = 6 -libusb_transfer_status = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_transfer_flags' -libusb_transfer_flags__enumvalues = { - 1: 'LIBUSB_TRANSFER_SHORT_NOT_OK', - 2: 'LIBUSB_TRANSFER_FREE_BUFFER', - 4: 'LIBUSB_TRANSFER_FREE_TRANSFER', - 8: 'LIBUSB_TRANSFER_ADD_ZERO_PACKET', -} -LIBUSB_TRANSFER_SHORT_NOT_OK = 1 -LIBUSB_TRANSFER_FREE_BUFFER = 2 -LIBUSB_TRANSFER_FREE_TRANSFER = 4 -LIBUSB_TRANSFER_ADD_ZERO_PACKET = 8 -libusb_transfer_flags = ctypes.c_uint32 # enum -class struct_libusb_iso_packet_descriptor(Structure): - pass - -struct_libusb_iso_packet_descriptor._pack_ = 1 # source:False -struct_libusb_iso_packet_descriptor._fields_ = [ - ('length', ctypes.c_uint32), - ('actual_length', ctypes.c_uint32), - ('status', libusb_transfer_status), -] - -class struct_libusb_transfer(Structure): - pass - -libusb_transfer_cb_fn = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_transfer)) - -# values for enumeration 'libusb_capability' -libusb_capability__enumvalues = { - 0: 'LIBUSB_CAP_HAS_CAPABILITY', - 1: 'LIBUSB_CAP_HAS_HOTPLUG', - 256: 'LIBUSB_CAP_HAS_HID_ACCESS', - 257: 'LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER', -} -LIBUSB_CAP_HAS_CAPABILITY = 0 -LIBUSB_CAP_HAS_HOTPLUG = 1 -LIBUSB_CAP_HAS_HID_ACCESS = 256 -LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER = 257 -libusb_capability = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_log_level' -libusb_log_level__enumvalues = { - 0: 'LIBUSB_LOG_LEVEL_NONE', - 1: 'LIBUSB_LOG_LEVEL_ERROR', - 2: 'LIBUSB_LOG_LEVEL_WARNING', - 3: 'LIBUSB_LOG_LEVEL_INFO', - 4: 'LIBUSB_LOG_LEVEL_DEBUG', -} -LIBUSB_LOG_LEVEL_NONE = 0 -LIBUSB_LOG_LEVEL_ERROR = 1 -LIBUSB_LOG_LEVEL_WARNING = 2 -LIBUSB_LOG_LEVEL_INFO = 3 -LIBUSB_LOG_LEVEL_DEBUG = 4 -libusb_log_level = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_log_cb_mode' -libusb_log_cb_mode__enumvalues = { - 1: 'LIBUSB_LOG_CB_GLOBAL', - 2: 'LIBUSB_LOG_CB_CONTEXT', -} -LIBUSB_LOG_CB_GLOBAL = 1 -LIBUSB_LOG_CB_CONTEXT = 2 -libusb_log_cb_mode = ctypes.c_uint32 # enum -libusb_log_cb = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_context), libusb_log_level, ctypes.POINTER(ctypes.c_char)) -try: - libusb_init = _libraries['libusb'].libusb_init - libusb_init.restype = ctypes.c_int32 - libusb_init.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_context))] -except AttributeError: - pass -try: - libusb_exit = _libraries['libusb'].libusb_exit - libusb_exit.restype = None - libusb_exit.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_set_debug = _libraries['libusb'].libusb_set_debug - libusb_set_debug.restype = None - libusb_set_debug.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_set_log_cb = _libraries['libusb'].libusb_set_log_cb - libusb_set_log_cb.restype = None - libusb_set_log_cb.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_log_cb, ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_version = _libraries['libusb'].libusb_get_version - libusb_get_version.restype = ctypes.POINTER(struct_libusb_version) - libusb_get_version.argtypes = [] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - libusb_has_capability = _libraries['libusb'].libusb_has_capability - libusb_has_capability.restype = ctypes.c_int32 - libusb_has_capability.argtypes = [uint32_t] -except AttributeError: - pass -try: - libusb_error_name = _libraries['libusb'].libusb_error_name - libusb_error_name.restype = ctypes.POINTER(ctypes.c_char) - libusb_error_name.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - libusb_setlocale = _libraries['libusb'].libusb_setlocale - libusb_setlocale.restype = ctypes.c_int32 - libusb_setlocale.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - libusb_strerror = _libraries['libusb'].libusb_strerror - libusb_strerror.restype = ctypes.POINTER(ctypes.c_char) - libusb_strerror.argtypes = [ctypes.c_int32] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - libusb_get_device_list = _libraries['libusb'].libusb_get_device_list - libusb_get_device_list.restype = ssize_t - libusb_get_device_list.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_libusb_device)))] -except AttributeError: - pass -try: - libusb_free_device_list = _libraries['libusb'].libusb_free_device_list - libusb_free_device_list.restype = None - libusb_free_device_list.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_device)), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_ref_device = _libraries['libusb'].libusb_ref_device - libusb_ref_device.restype = ctypes.POINTER(struct_libusb_device) - libusb_ref_device.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_unref_device = _libraries['libusb'].libusb_unref_device - libusb_unref_device.restype = None - libusb_unref_device.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_configuration = _libraries['libusb'].libusb_get_configuration - libusb_get_configuration.restype = ctypes.c_int32 - libusb_get_configuration.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_get_device_descriptor = _libraries['libusb'].libusb_get_device_descriptor - libusb_get_device_descriptor.restype = ctypes.c_int32 - libusb_get_device_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(struct_libusb_device_descriptor)] -except AttributeError: - pass -try: - libusb_get_active_config_descriptor = _libraries['libusb'].libusb_get_active_config_descriptor - libusb_get_active_config_descriptor.restype = ctypes.c_int32 - libusb_get_active_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -uint8_t = ctypes.c_uint8 -try: - libusb_get_config_descriptor = _libraries['libusb'].libusb_get_config_descriptor - libusb_get_config_descriptor.restype = ctypes.c_int32 - libusb_get_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -try: - libusb_get_config_descriptor_by_value = _libraries['libusb'].libusb_get_config_descriptor_by_value - libusb_get_config_descriptor_by_value.restype = ctypes.c_int32 - libusb_get_config_descriptor_by_value.argtypes = [ctypes.POINTER(struct_libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -try: - libusb_free_config_descriptor = _libraries['libusb'].libusb_free_config_descriptor - libusb_free_config_descriptor.restype = None - libusb_free_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_config_descriptor)] -except AttributeError: - pass -try: - libusb_get_ss_endpoint_companion_descriptor = _libraries['libusb'].libusb_get_ss_endpoint_companion_descriptor - libusb_get_ss_endpoint_companion_descriptor.restype = ctypes.c_int32 - libusb_get_ss_endpoint_companion_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_endpoint_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor))] -except AttributeError: - pass -try: - libusb_free_ss_endpoint_companion_descriptor = _libraries['libusb'].libusb_free_ss_endpoint_companion_descriptor - libusb_free_ss_endpoint_companion_descriptor.restype = None - libusb_free_ss_endpoint_companion_descriptor.argtypes = [ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor)] -except AttributeError: - pass -try: - libusb_get_bos_descriptor = _libraries['libusb'].libusb_get_bos_descriptor - libusb_get_bos_descriptor.restype = ctypes.c_int32 - libusb_get_bos_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.POINTER(struct_libusb_bos_descriptor))] -except AttributeError: - pass -try: - libusb_free_bos_descriptor = _libraries['libusb'].libusb_free_bos_descriptor - libusb_free_bos_descriptor.restype = None - libusb_free_bos_descriptor.argtypes = [ctypes.POINTER(struct_libusb_bos_descriptor)] -except AttributeError: - pass -try: - libusb_get_usb_2_0_extension_descriptor = _libraries['libusb'].libusb_get_usb_2_0_extension_descriptor - libusb_get_usb_2_0_extension_descriptor.restype = ctypes.c_int32 - libusb_get_usb_2_0_extension_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor))] -except AttributeError: - pass -try: - libusb_free_usb_2_0_extension_descriptor = _libraries['libusb'].libusb_free_usb_2_0_extension_descriptor - libusb_free_usb_2_0_extension_descriptor.restype = None - libusb_free_usb_2_0_extension_descriptor.argtypes = [ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor)] -except AttributeError: - pass -try: - libusb_get_ss_usb_device_capability_descriptor = _libraries['libusb'].libusb_get_ss_usb_device_capability_descriptor - libusb_get_ss_usb_device_capability_descriptor.restype = ctypes.c_int32 - libusb_get_ss_usb_device_capability_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor))] -except AttributeError: - pass -try: - libusb_free_ss_usb_device_capability_descriptor = _libraries['libusb'].libusb_free_ss_usb_device_capability_descriptor - libusb_free_ss_usb_device_capability_descriptor.restype = None - libusb_free_ss_usb_device_capability_descriptor.argtypes = [ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor)] -except AttributeError: - pass -try: - libusb_get_container_id_descriptor = _libraries['libusb'].libusb_get_container_id_descriptor - libusb_get_container_id_descriptor.restype = ctypes.c_int32 - libusb_get_container_id_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_container_id_descriptor))] -except AttributeError: - pass -try: - libusb_free_container_id_descriptor = _libraries['libusb'].libusb_free_container_id_descriptor - libusb_free_container_id_descriptor.restype = None - libusb_free_container_id_descriptor.argtypes = [ctypes.POINTER(struct_libusb_container_id_descriptor)] -except AttributeError: - pass -try: - libusb_get_bus_number = _libraries['libusb'].libusb_get_bus_number - libusb_get_bus_number.restype = uint8_t - libusb_get_bus_number.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_port_number = _libraries['libusb'].libusb_get_port_number - libusb_get_port_number.restype = uint8_t - libusb_get_port_number.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_port_numbers = _libraries['libusb'].libusb_get_port_numbers - libusb_get_port_numbers.restype = ctypes.c_int32 - libusb_get_port_numbers.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_port_path = _libraries['libusb'].libusb_get_port_path - libusb_get_port_path.restype = ctypes.c_int32 - libusb_get_port_path.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.c_ubyte), uint8_t] -except AttributeError: - pass -try: - libusb_get_parent = _libraries['libusb'].libusb_get_parent - libusb_get_parent.restype = ctypes.POINTER(struct_libusb_device) - libusb_get_parent.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_device_address = _libraries['libusb'].libusb_get_device_address - libusb_get_device_address.restype = uint8_t - libusb_get_device_address.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_device_speed = _libraries['libusb'].libusb_get_device_speed - libusb_get_device_speed.restype = ctypes.c_int32 - libusb_get_device_speed.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_max_packet_size = _libraries['libusb'].libusb_get_max_packet_size - libusb_get_max_packet_size.restype = ctypes.c_int32 - libusb_get_max_packet_size.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.c_ubyte] -except AttributeError: - pass -try: - libusb_get_max_iso_packet_size = _libraries['libusb'].libusb_get_max_iso_packet_size - libusb_get_max_iso_packet_size.restype = ctypes.c_int32 - libusb_get_max_iso_packet_size.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.c_ubyte] -except AttributeError: - pass -intptr_t = ctypes.c_int64 -try: - libusb_wrap_sys_device = _libraries['libusb'].libusb_wrap_sys_device - libusb_wrap_sys_device.restype = ctypes.c_int32 - libusb_wrap_sys_device.argtypes = [ctypes.POINTER(struct_libusb_context), intptr_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_device_handle))] -except AttributeError: - pass -try: - libusb_open = _libraries['libusb'].libusb_open - libusb_open.restype = ctypes.c_int32 - libusb_open.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_device_handle))] -except AttributeError: - pass -try: - libusb_close = _libraries['libusb'].libusb_close - libusb_close.restype = None - libusb_close.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_get_device = _libraries['libusb'].libusb_get_device - libusb_get_device.restype = ctypes.POINTER(struct_libusb_device) - libusb_get_device.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_set_configuration = _libraries['libusb'].libusb_set_configuration - libusb_set_configuration.restype = ctypes.c_int32 - libusb_set_configuration.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_claim_interface = _libraries['libusb'].libusb_claim_interface - libusb_claim_interface.restype = ctypes.c_int32 - libusb_claim_interface.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_release_interface = _libraries['libusb'].libusb_release_interface - libusb_release_interface.restype = ctypes.c_int32 - libusb_release_interface.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_open_device_with_vid_pid = _libraries['libusb'].libusb_open_device_with_vid_pid - libusb_open_device_with_vid_pid.restype = ctypes.POINTER(struct_libusb_device_handle) - libusb_open_device_with_vid_pid.argtypes = [ctypes.POINTER(struct_libusb_context), uint16_t, uint16_t] -except AttributeError: - pass -try: - libusb_set_interface_alt_setting = _libraries['libusb'].libusb_set_interface_alt_setting - libusb_set_interface_alt_setting.restype = ctypes.c_int32 - libusb_set_interface_alt_setting.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - libusb_clear_halt = _libraries['libusb'].libusb_clear_halt - libusb_clear_halt.restype = ctypes.c_int32 - libusb_clear_halt.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte] -except AttributeError: - pass -try: - libusb_reset_device = _libraries['libusb'].libusb_reset_device - libusb_reset_device.restype = ctypes.c_int32 - libusb_reset_device.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_alloc_streams = _libraries['libusb'].libusb_alloc_streams - libusb_alloc_streams.restype = ctypes.c_int32 - libusb_alloc_streams.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint32_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_free_streams = _libraries['libusb'].libusb_free_streams - libusb_free_streams.restype = ctypes.c_int32 - libusb_free_streams.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - libusb_dev_mem_alloc = _libraries['libusb'].libusb_dev_mem_alloc - libusb_dev_mem_alloc.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_dev_mem_alloc.argtypes = [ctypes.POINTER(struct_libusb_device_handle), size_t] -except AttributeError: - pass -try: - libusb_dev_mem_free = _libraries['libusb'].libusb_dev_mem_free - libusb_dev_mem_free.restype = ctypes.c_int32 - libusb_dev_mem_free.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), size_t] -except AttributeError: - pass -try: - libusb_kernel_driver_active = _libraries['libusb'].libusb_kernel_driver_active - libusb_kernel_driver_active.restype = ctypes.c_int32 - libusb_kernel_driver_active.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_detach_kernel_driver = _libraries['libusb'].libusb_detach_kernel_driver - libusb_detach_kernel_driver.restype = ctypes.c_int32 - libusb_detach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_attach_kernel_driver = _libraries['libusb'].libusb_attach_kernel_driver - libusb_attach_kernel_driver.restype = ctypes.c_int32 - libusb_attach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_set_auto_detach_kernel_driver = _libraries['libusb'].libusb_set_auto_detach_kernel_driver - libusb_set_auto_detach_kernel_driver.restype = ctypes.c_int32 - libusb_set_auto_detach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_control_transfer_get_data = _libraries['libusb'].libusb_control_transfer_get_data - libusb_control_transfer_get_data.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_control_transfer_get_data.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_control_transfer_get_setup = _libraries['libusb'].libusb_control_transfer_get_setup - libusb_control_transfer_get_setup.restype = ctypes.POINTER(struct_libusb_control_setup) - libusb_control_transfer_get_setup.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_fill_control_setup = _libraries['libusb'].libusb_fill_control_setup - libusb_fill_control_setup.restype = None - libusb_fill_control_setup.argtypes = [ctypes.POINTER(ctypes.c_ubyte), uint8_t, uint8_t, uint16_t, uint16_t, uint16_t] -except AttributeError: - pass -try: - libusb_alloc_transfer = _libraries['libusb'].libusb_alloc_transfer - libusb_alloc_transfer.restype = ctypes.POINTER(struct_libusb_transfer) - libusb_alloc_transfer.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - libusb_submit_transfer = _libraries['libusb'].libusb_submit_transfer - libusb_submit_transfer.restype = ctypes.c_int32 - libusb_submit_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_cancel_transfer = _libraries['libusb'].libusb_cancel_transfer - libusb_cancel_transfer.restype = ctypes.c_int32 - libusb_cancel_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_free_transfer = _libraries['libusb'].libusb_free_transfer - libusb_free_transfer.restype = None - libusb_free_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_transfer_set_stream_id = _libraries['libusb'].libusb_transfer_set_stream_id - libusb_transfer_set_stream_id.restype = None - libusb_transfer_set_stream_id.argtypes = [ctypes.POINTER(struct_libusb_transfer), uint32_t] -except AttributeError: - pass -try: - libusb_transfer_get_stream_id = _libraries['libusb'].libusb_transfer_get_stream_id - libusb_transfer_get_stream_id.restype = uint32_t - libusb_transfer_get_stream_id.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_fill_control_transfer = _libraries['libusb'].libusb_fill_control_transfer - libusb_fill_control_transfer.restype = None - libusb_fill_control_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_bulk_transfer = _libraries['libusb'].libusb_fill_bulk_transfer - libusb_fill_bulk_transfer.restype = None - libusb_fill_bulk_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_bulk_stream_transfer = _libraries['libusb'].libusb_fill_bulk_stream_transfer - libusb_fill_bulk_stream_transfer.restype = None - libusb_fill_bulk_stream_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, uint32_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_interrupt_transfer = _libraries['libusb'].libusb_fill_interrupt_transfer - libusb_fill_interrupt_transfer.restype = None - libusb_fill_interrupt_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_iso_transfer = _libraries['libusb'].libusb_fill_iso_transfer - libusb_fill_iso_transfer.restype = None - libusb_fill_iso_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_set_iso_packet_lengths = _libraries['libusb'].libusb_set_iso_packet_lengths - libusb_set_iso_packet_lengths.restype = None - libusb_set_iso_packet_lengths.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_iso_packet_buffer = _libraries['libusb'].libusb_get_iso_packet_buffer - libusb_get_iso_packet_buffer.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_get_iso_packet_buffer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_iso_packet_buffer_simple = _libraries['libusb'].libusb_get_iso_packet_buffer_simple - libusb_get_iso_packet_buffer_simple.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_get_iso_packet_buffer_simple.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_control_transfer = _libraries['libusb'].libusb_control_transfer - libusb_control_transfer.restype = ctypes.c_int32 - libusb_control_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint8_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_ubyte), uint16_t, ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_bulk_transfer = _libraries['libusb'].libusb_bulk_transfer - libusb_bulk_transfer.restype = ctypes.c_int32 - libusb_bulk_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_interrupt_transfer = _libraries['libusb'].libusb_interrupt_transfer - libusb_interrupt_transfer.restype = ctypes.c_int32 - libusb_interrupt_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_descriptor = _libraries['libusb'].libusb_get_descriptor - libusb_get_descriptor.restype = ctypes.c_int32 - libusb_get_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint8_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_string_descriptor = _libraries['libusb'].libusb_get_string_descriptor - libusb_get_string_descriptor.restype = ctypes.c_int32 - libusb_get_string_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint16_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_string_descriptor_ascii = _libraries['libusb'].libusb_get_string_descriptor_ascii - libusb_get_string_descriptor_ascii.restype = ctypes.c_int32 - libusb_get_string_descriptor_ascii.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_try_lock_events = _libraries['libusb'].libusb_try_lock_events - libusb_try_lock_events.restype = ctypes.c_int32 - libusb_try_lock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_lock_events = _libraries['libusb'].libusb_lock_events - libusb_lock_events.restype = None - libusb_lock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_unlock_events = _libraries['libusb'].libusb_unlock_events - libusb_unlock_events.restype = None - libusb_unlock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_event_handling_ok = _libraries['libusb'].libusb_event_handling_ok - libusb_event_handling_ok.restype = ctypes.c_int32 - libusb_event_handling_ok.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_event_handler_active = _libraries['libusb'].libusb_event_handler_active - libusb_event_handler_active.restype = ctypes.c_int32 - libusb_event_handler_active.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_interrupt_event_handler = _libraries['libusb'].libusb_interrupt_event_handler - libusb_interrupt_event_handler.restype = None - libusb_interrupt_event_handler.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_lock_event_waiters = _libraries['libusb'].libusb_lock_event_waiters - libusb_lock_event_waiters.restype = None - libusb_lock_event_waiters.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_unlock_event_waiters = _libraries['libusb'].libusb_unlock_event_waiters - libusb_unlock_event_waiters.restype = None - libusb_unlock_event_waiters.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -class struct_timeval(Structure): - pass - -struct_timeval._pack_ = 1 # source:False -struct_timeval._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_usec', ctypes.c_int64), -] - -try: - libusb_wait_for_event = _libraries['libusb'].libusb_wait_for_event - libusb_wait_for_event.restype = ctypes.c_int32 - libusb_wait_for_event.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_handle_events_timeout = _libraries['libusb'].libusb_handle_events_timeout - libusb_handle_events_timeout.restype = ctypes.c_int32 - libusb_handle_events_timeout.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_handle_events_timeout_completed = _libraries['libusb'].libusb_handle_events_timeout_completed - libusb_handle_events_timeout_completed.restype = ctypes.c_int32 - libusb_handle_events_timeout_completed.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_handle_events = _libraries['libusb'].libusb_handle_events - libusb_handle_events.restype = ctypes.c_int32 - libusb_handle_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_handle_events_completed = _libraries['libusb'].libusb_handle_events_completed - libusb_handle_events_completed.restype = ctypes.c_int32 - libusb_handle_events_completed.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_handle_events_locked = _libraries['libusb'].libusb_handle_events_locked - libusb_handle_events_locked.restype = ctypes.c_int32 - libusb_handle_events_locked.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_pollfds_handle_timeouts = _libraries['libusb'].libusb_pollfds_handle_timeouts - libusb_pollfds_handle_timeouts.restype = ctypes.c_int32 - libusb_pollfds_handle_timeouts.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_get_next_timeout = _libraries['libusb'].libusb_get_next_timeout - libusb_get_next_timeout.restype = ctypes.c_int32 - libusb_get_next_timeout.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -class struct_libusb_pollfd(Structure): - pass - -struct_libusb_pollfd._pack_ = 1 # source:False -struct_libusb_pollfd._fields_ = [ - ('fd', ctypes.c_int32), - ('events', ctypes.c_int16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -libusb_pollfd_added_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.c_int16, ctypes.POINTER(None)) -libusb_pollfd_removed_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.POINTER(None)) -try: - libusb_get_pollfds = _libraries['libusb'].libusb_get_pollfds - libusb_get_pollfds.restype = ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd)) - libusb_get_pollfds.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_free_pollfds = _libraries['libusb'].libusb_free_pollfds - libusb_free_pollfds.restype = None - libusb_free_pollfds.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd))] -except AttributeError: - pass -try: - libusb_set_pollfd_notifiers = _libraries['libusb'].libusb_set_pollfd_notifiers - libusb_set_pollfd_notifiers.restype = None - libusb_set_pollfd_notifiers.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_pollfd_added_cb, libusb_pollfd_removed_cb, ctypes.POINTER(None)] -except AttributeError: - pass -libusb_hotplug_callback_handle = ctypes.c_int32 - -# values for enumeration 'c__EA_libusb_hotplug_event' -c__EA_libusb_hotplug_event__enumvalues = { - 1: 'LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED', - 2: 'LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT', -} -LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED = 1 -LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT = 2 -c__EA_libusb_hotplug_event = ctypes.c_uint32 # enum -libusb_hotplug_event = c__EA_libusb_hotplug_event -libusb_hotplug_event__enumvalues = c__EA_libusb_hotplug_event__enumvalues - -# values for enumeration 'c__EA_libusb_hotplug_flag' -c__EA_libusb_hotplug_flag__enumvalues = { - 1: 'LIBUSB_HOTPLUG_ENUMERATE', -} -LIBUSB_HOTPLUG_ENUMERATE = 1 -c__EA_libusb_hotplug_flag = ctypes.c_uint32 # enum -libusb_hotplug_flag = c__EA_libusb_hotplug_flag -libusb_hotplug_flag__enumvalues = c__EA_libusb_hotplug_flag__enumvalues -libusb_hotplug_callback_fn = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_device), c__EA_libusb_hotplug_event, ctypes.POINTER(None)) -try: - libusb_hotplug_register_callback = _libraries['libusb'].libusb_hotplug_register_callback - libusb_hotplug_register_callback.restype = ctypes.c_int32 - libusb_hotplug_register_callback.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, libusb_hotplug_callback_fn, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_hotplug_deregister_callback = _libraries['libusb'].libusb_hotplug_deregister_callback - libusb_hotplug_deregister_callback.restype = None - libusb_hotplug_deregister_callback.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_hotplug_callback_handle] -except AttributeError: - pass -try: - libusb_hotplug_get_user_data = _libraries['libusb'].libusb_hotplug_get_user_data - libusb_hotplug_get_user_data.restype = ctypes.POINTER(None) - libusb_hotplug_get_user_data.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_hotplug_callback_handle] -except AttributeError: - pass - -# values for enumeration 'libusb_option' -libusb_option__enumvalues = { - 0: 'LIBUSB_OPTION_LOG_LEVEL', - 1: 'LIBUSB_OPTION_USE_USBDK', - 2: 'LIBUSB_OPTION_NO_DEVICE_DISCOVERY', - 3: 'LIBUSB_OPTION_MAX', -} -LIBUSB_OPTION_LOG_LEVEL = 0 -LIBUSB_OPTION_USE_USBDK = 1 -LIBUSB_OPTION_NO_DEVICE_DISCOVERY = 2 -LIBUSB_OPTION_MAX = 3 -libusb_option = ctypes.c_uint32 # enum -LIBUSB_OPTION_WEAK_AUTHORITY = LIBUSB_OPTION_NO_DEVICE_DISCOVERY # macro -try: - libusb_set_option = _libraries['libusb'].libusb_set_option - libusb_set_option.restype = ctypes.c_int32 - libusb_set_option.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_option] -except AttributeError: - pass -struct_libusb_transfer._pack_ = 1 # source:False -struct_libusb_transfer._fields_ = [ - ('dev_handle', ctypes.POINTER(struct_libusb_device_handle)), - ('flags', ctypes.c_ubyte), - ('endpoint', ctypes.c_ubyte), - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('timeout', ctypes.c_uint32), - ('status', libusb_transfer_status), - ('length', ctypes.c_int32), - ('actual_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_transfer))), - ('user_data', ctypes.POINTER(None)), - ('buffer', ctypes.POINTER(ctypes.c_ubyte)), - ('num_iso_packets', ctypes.c_int32), - ('iso_packet_desc', struct_libusb_iso_packet_descriptor * 0), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -__all__ = \ - ['LIBUSBX_API_VERSION', 'LIBUSB_API_VERSION', - 'LIBUSB_BM_LPM_SUPPORT', 'LIBUSB_BM_LTM_SUPPORT', - 'LIBUSB_BT_CONTAINER_ID', 'LIBUSB_BT_CONTAINER_ID_SIZE', - 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY', - 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE', - 'LIBUSB_BT_USB_2_0_EXTENSION', 'LIBUSB_BT_USB_2_0_EXTENSION_SIZE', - 'LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY', 'LIBUSB_CALL', - 'LIBUSB_CAP_HAS_CAPABILITY', 'LIBUSB_CAP_HAS_HID_ACCESS', - 'LIBUSB_CAP_HAS_HOTPLUG', - 'LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER', - 'LIBUSB_CLASS_APPLICATION', 'LIBUSB_CLASS_AUDIO', - 'LIBUSB_CLASS_COMM', 'LIBUSB_CLASS_CONTENT_SECURITY', - 'LIBUSB_CLASS_DATA', 'LIBUSB_CLASS_DIAGNOSTIC_DEVICE', - 'LIBUSB_CLASS_HID', 'LIBUSB_CLASS_HUB', 'LIBUSB_CLASS_IMAGE', - 'LIBUSB_CLASS_MASS_STORAGE', 'LIBUSB_CLASS_MISCELLANEOUS', - 'LIBUSB_CLASS_PERSONAL_HEALTHCARE', 'LIBUSB_CLASS_PER_INTERFACE', - 'LIBUSB_CLASS_PHYSICAL', 'LIBUSB_CLASS_PRINTER', - 'LIBUSB_CLASS_PTP', 'LIBUSB_CLASS_SMART_CARD', - 'LIBUSB_CLASS_VENDOR_SPEC', 'LIBUSB_CLASS_VIDEO', - 'LIBUSB_CLASS_WIRELESS', 'LIBUSB_DT_BOS', - 'LIBUSB_DT_BOS_MAX_SIZE', 'LIBUSB_DT_BOS_SIZE', - 'LIBUSB_DT_CONFIG', 'LIBUSB_DT_CONFIG_SIZE', 'LIBUSB_DT_DEVICE', - 'LIBUSB_DT_DEVICE_CAPABILITY', 'LIBUSB_DT_DEVICE_CAPABILITY_SIZE', - 'LIBUSB_DT_DEVICE_SIZE', 'LIBUSB_DT_ENDPOINT', - 'LIBUSB_DT_ENDPOINT_AUDIO_SIZE', 'LIBUSB_DT_ENDPOINT_SIZE', - 'LIBUSB_DT_HID', 'LIBUSB_DT_HUB', 'LIBUSB_DT_HUB_NONVAR_SIZE', - 'LIBUSB_DT_INTERFACE', 'LIBUSB_DT_INTERFACE_SIZE', - 'LIBUSB_DT_PHYSICAL', 'LIBUSB_DT_REPORT', - 'LIBUSB_DT_SS_ENDPOINT_COMPANION', - 'LIBUSB_DT_SS_ENDPOINT_COMPANION_SIZE', 'LIBUSB_DT_STRING', - 'LIBUSB_DT_SUPERSPEED_HUB', 'LIBUSB_ENDPOINT_ADDRESS_MASK', - 'LIBUSB_ENDPOINT_DIR_MASK', 'LIBUSB_ENDPOINT_IN', - 'LIBUSB_ENDPOINT_OUT', 'LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS', - 'LIBUSB_ERROR_ACCESS', 'LIBUSB_ERROR_BUSY', 'LIBUSB_ERROR_COUNT', - 'LIBUSB_ERROR_INTERRUPTED', 'LIBUSB_ERROR_INVALID_PARAM', - 'LIBUSB_ERROR_IO', 'LIBUSB_ERROR_NOT_FOUND', - 'LIBUSB_ERROR_NOT_SUPPORTED', 'LIBUSB_ERROR_NO_DEVICE', - 'LIBUSB_ERROR_NO_MEM', 'LIBUSB_ERROR_OTHER', - 'LIBUSB_ERROR_OVERFLOW', 'LIBUSB_ERROR_PIPE', - 'LIBUSB_ERROR_TIMEOUT', 'LIBUSB_FULL_SPEED_OPERATION', 'LIBUSB_H', - 'LIBUSB_HIGH_SPEED_OPERATION', 'LIBUSB_HOTPLUG_ENUMERATE', - 'LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED', - 'LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT', 'LIBUSB_HOTPLUG_MATCH_ANY', - 'LIBUSB_HOTPLUG_NO_FLAGS', 'LIBUSB_ISO_SYNC_TYPE_ADAPTIVE', - 'LIBUSB_ISO_SYNC_TYPE_ASYNC', 'LIBUSB_ISO_SYNC_TYPE_MASK', - 'LIBUSB_ISO_SYNC_TYPE_NONE', 'LIBUSB_ISO_SYNC_TYPE_SYNC', - 'LIBUSB_ISO_USAGE_TYPE_DATA', 'LIBUSB_ISO_USAGE_TYPE_FEEDBACK', - 'LIBUSB_ISO_USAGE_TYPE_IMPLICIT', 'LIBUSB_ISO_USAGE_TYPE_MASK', - 'LIBUSB_LOG_CB_CONTEXT', 'LIBUSB_LOG_CB_GLOBAL', - 'LIBUSB_LOG_LEVEL_DEBUG', 'LIBUSB_LOG_LEVEL_ERROR', - 'LIBUSB_LOG_LEVEL_INFO', 'LIBUSB_LOG_LEVEL_NONE', - 'LIBUSB_LOG_LEVEL_WARNING', 'LIBUSB_LOW_SPEED_OPERATION', - 'LIBUSB_OPTION_LOG_LEVEL', 'LIBUSB_OPTION_MAX', - 'LIBUSB_OPTION_NO_DEVICE_DISCOVERY', 'LIBUSB_OPTION_USE_USBDK', - 'LIBUSB_OPTION_WEAK_AUTHORITY', 'LIBUSB_RECIPIENT_DEVICE', - 'LIBUSB_RECIPIENT_ENDPOINT', 'LIBUSB_RECIPIENT_INTERFACE', - 'LIBUSB_RECIPIENT_OTHER', 'LIBUSB_REQUEST_CLEAR_FEATURE', - 'LIBUSB_REQUEST_GET_CONFIGURATION', - 'LIBUSB_REQUEST_GET_DESCRIPTOR', 'LIBUSB_REQUEST_GET_INTERFACE', - 'LIBUSB_REQUEST_GET_STATUS', 'LIBUSB_REQUEST_SET_ADDRESS', - 'LIBUSB_REQUEST_SET_CONFIGURATION', - 'LIBUSB_REQUEST_SET_DESCRIPTOR', 'LIBUSB_REQUEST_SET_FEATURE', - 'LIBUSB_REQUEST_SET_INTERFACE', 'LIBUSB_REQUEST_SET_SEL', - 'LIBUSB_REQUEST_SYNCH_FRAME', 'LIBUSB_REQUEST_TYPE_CLASS', - 'LIBUSB_REQUEST_TYPE_RESERVED', 'LIBUSB_REQUEST_TYPE_STANDARD', - 'LIBUSB_REQUEST_TYPE_VENDOR', 'LIBUSB_SET_ISOCH_DELAY', - 'LIBUSB_SPEED_FULL', 'LIBUSB_SPEED_HIGH', 'LIBUSB_SPEED_LOW', - 'LIBUSB_SPEED_SUPER', 'LIBUSB_SPEED_SUPER_PLUS', - 'LIBUSB_SPEED_UNKNOWN', 'LIBUSB_SUCCESS', - 'LIBUSB_SUPER_SPEED_OPERATION', 'LIBUSB_TRANSFER_ADD_ZERO_PACKET', - 'LIBUSB_TRANSFER_CANCELLED', 'LIBUSB_TRANSFER_COMPLETED', - 'LIBUSB_TRANSFER_ERROR', 'LIBUSB_TRANSFER_FREE_BUFFER', - 'LIBUSB_TRANSFER_FREE_TRANSFER', 'LIBUSB_TRANSFER_NO_DEVICE', - 'LIBUSB_TRANSFER_OVERFLOW', 'LIBUSB_TRANSFER_SHORT_NOT_OK', - 'LIBUSB_TRANSFER_STALL', 'LIBUSB_TRANSFER_TIMED_OUT', - 'LIBUSB_TRANSFER_TYPE_BULK', 'LIBUSB_TRANSFER_TYPE_BULK_STREAM', - 'LIBUSB_TRANSFER_TYPE_CONTROL', 'LIBUSB_TRANSFER_TYPE_INTERRUPT', - 'LIBUSB_TRANSFER_TYPE_ISOCHRONOUS', 'LIBUSB_TRANSFER_TYPE_MASK', - 'ZERO_SIZED_ARRAY', 'c__EA_libusb_hotplug_event', - 'c__EA_libusb_hotplug_flag', 'intptr_t', 'libusb_alloc_streams', - 'libusb_alloc_transfer', 'libusb_attach_kernel_driver', - 'libusb_bos_type', 'libusb_bulk_transfer', - 'libusb_cancel_transfer', 'libusb_capability', - 'libusb_claim_interface', 'libusb_class_code', - 'libusb_clear_halt', 'libusb_close', 'libusb_context', - 'libusb_control_transfer', 'libusb_control_transfer_get_data', - 'libusb_control_transfer_get_setup', 'libusb_cpu_to_le16', - 'libusb_descriptor_type', 'libusb_detach_kernel_driver', - 'libusb_dev_mem_alloc', 'libusb_dev_mem_free', 'libusb_device', - 'libusb_device_handle', 'libusb_endpoint_direction', - 'libusb_endpoint_transfer_type', 'libusb_error', - 'libusb_error_name', 'libusb_event_handler_active', - 'libusb_event_handling_ok', 'libusb_exit', - 'libusb_fill_bulk_stream_transfer', 'libusb_fill_bulk_transfer', - 'libusb_fill_control_setup', 'libusb_fill_control_transfer', - 'libusb_fill_interrupt_transfer', 'libusb_fill_iso_transfer', - 'libusb_free_bos_descriptor', 'libusb_free_config_descriptor', - 'libusb_free_container_id_descriptor', 'libusb_free_device_list', - 'libusb_free_pollfds', - 'libusb_free_ss_endpoint_companion_descriptor', - 'libusb_free_ss_usb_device_capability_descriptor', - 'libusb_free_streams', 'libusb_free_transfer', - 'libusb_free_usb_2_0_extension_descriptor', - 'libusb_get_active_config_descriptor', - 'libusb_get_bos_descriptor', 'libusb_get_bus_number', - 'libusb_get_config_descriptor', - 'libusb_get_config_descriptor_by_value', - 'libusb_get_configuration', 'libusb_get_container_id_descriptor', - 'libusb_get_descriptor', 'libusb_get_device', - 'libusb_get_device_address', 'libusb_get_device_descriptor', - 'libusb_get_device_list', 'libusb_get_device_speed', - 'libusb_get_iso_packet_buffer', - 'libusb_get_iso_packet_buffer_simple', - 'libusb_get_max_iso_packet_size', 'libusb_get_max_packet_size', - 'libusb_get_next_timeout', 'libusb_get_parent', - 'libusb_get_pollfds', 'libusb_get_port_number', - 'libusb_get_port_numbers', 'libusb_get_port_path', - 'libusb_get_ss_endpoint_companion_descriptor', - 'libusb_get_ss_usb_device_capability_descriptor', - 'libusb_get_string_descriptor', - 'libusb_get_string_descriptor_ascii', - 'libusb_get_usb_2_0_extension_descriptor', 'libusb_get_version', - 'libusb_handle_events', 'libusb_handle_events_completed', - 'libusb_handle_events_locked', 'libusb_handle_events_timeout', - 'libusb_handle_events_timeout_completed', 'libusb_has_capability', - 'libusb_hotplug_callback_fn', 'libusb_hotplug_callback_handle', - 'libusb_hotplug_deregister_callback', 'libusb_hotplug_event', - 'libusb_hotplug_event__enumvalues', 'libusb_hotplug_flag', - 'libusb_hotplug_flag__enumvalues', 'libusb_hotplug_get_user_data', - 'libusb_hotplug_register_callback', 'libusb_init', - 'libusb_interrupt_event_handler', 'libusb_interrupt_transfer', - 'libusb_iso_sync_type', 'libusb_iso_usage_type', - 'libusb_kernel_driver_active', 'libusb_le16_to_cpu', - 'libusb_lock_event_waiters', 'libusb_lock_events', - 'libusb_log_cb', 'libusb_log_cb_mode', 'libusb_log_level', - 'libusb_open', 'libusb_open_device_with_vid_pid', 'libusb_option', - 'libusb_pollfd_added_cb', 'libusb_pollfd_removed_cb', - 'libusb_pollfds_handle_timeouts', 'libusb_ref_device', - 'libusb_release_interface', 'libusb_request_recipient', - 'libusb_request_type', 'libusb_reset_device', - 'libusb_set_auto_detach_kernel_driver', - 'libusb_set_configuration', 'libusb_set_debug', - 'libusb_set_interface_alt_setting', - 'libusb_set_iso_packet_lengths', 'libusb_set_log_cb', - 'libusb_set_option', 'libusb_set_pollfd_notifiers', - 'libusb_setlocale', 'libusb_speed', - 'libusb_ss_usb_device_capability_attributes', - 'libusb_standard_request', 'libusb_strerror', - 'libusb_submit_transfer', 'libusb_supported_speed', - 'libusb_transfer_cb_fn', 'libusb_transfer_flags', - 'libusb_transfer_get_stream_id', 'libusb_transfer_set_stream_id', - 'libusb_transfer_status', 'libusb_transfer_type', - 'libusb_try_lock_events', 'libusb_unlock_event_waiters', - 'libusb_unlock_events', 'libusb_unref_device', - 'libusb_usb_2_0_extension_attributes', 'libusb_wait_for_event', - 'libusb_wrap_sys_device', 'size_t', 'ssize_t', - 'struct_libusb_bos_descriptor', - 'struct_libusb_bos_dev_capability_descriptor', - 'struct_libusb_config_descriptor', - 'struct_libusb_container_id_descriptor', 'struct_libusb_context', - 'struct_libusb_control_setup', 'struct_libusb_device', - 'struct_libusb_device_descriptor', 'struct_libusb_device_handle', - 'struct_libusb_endpoint_descriptor', 'struct_libusb_interface', - 'struct_libusb_interface_descriptor', - 'struct_libusb_iso_packet_descriptor', 'struct_libusb_pollfd', - 'struct_libusb_ss_endpoint_companion_descriptor', - 'struct_libusb_ss_usb_device_capability_descriptor', - 'struct_libusb_transfer', - 'struct_libusb_usb_2_0_extension_descriptor', - 'struct_libusb_version', 'struct_timeval', 'uint16_t', 'uint32_t', - 'uint8_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/llvm.py b/tinygrad/tinygrad/runtime/autogen/llvm.py deleted file mode 100644 index 1b50e41e..00000000 --- a/tinygrad/tinygrad/runtime/autogen/llvm.py +++ /dev/null @@ -1,11379 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/usr/lib/llvm-14/include', '-D_GNU_SOURCE', '-D__STDC_CONSTANT_MACROS', '-D__STDC_FORMAT_MACROS', '-D__STDC_LIMIT_MACROS'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, tinygrad.runtime.support.llvm as llvm_support - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['llvm'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['llvm'] = ctypes.CDLL(llvm_support.LLVM_PATH) # ctypes.CDLL('llvm') -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -LLVM_C_ANALYSIS_H = True # macro -LLVM_C_EXTERNC_H = True # macro -# LLVM_C_STRICT_PROTOTYPES_BEGIN = _Pragma ( "clang diagnostic push" ) _Pragma ( "clang diagnostic error \"-Wstrict-prototypes\"" ) # macro -# LLVM_C_STRICT_PROTOTYPES_END = _Pragma ( "clang diagnostic pop" ) # macro -# LLVM_C_EXTERN_C_BEGIN = _Pragma ( "clang diagnostic push" ) _Pragma ( "clang diagnostic error \"-Wstrict-prototypes\"" ) # macro -# LLVM_C_EXTERN_C_END = _Pragma ( "clang diagnostic pop" ) # macro -LLVM_C_TYPES_H = True # macro -LLVM_C_DATATYPES_H = True # macro -LLVMBool = ctypes.c_int32 -class struct_LLVMOpaqueMemoryBuffer(Structure): - pass - -LLVMMemoryBufferRef = ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer) -class struct_LLVMOpaqueContext(Structure): - pass - -LLVMContextRef = ctypes.POINTER(struct_LLVMOpaqueContext) -class struct_LLVMOpaqueModule(Structure): - pass - -LLVMModuleRef = ctypes.POINTER(struct_LLVMOpaqueModule) -class struct_LLVMOpaqueType(Structure): - pass - -LLVMTypeRef = ctypes.POINTER(struct_LLVMOpaqueType) -class struct_LLVMOpaqueValue(Structure): - pass - -LLVMValueRef = ctypes.POINTER(struct_LLVMOpaqueValue) -class struct_LLVMOpaqueBasicBlock(Structure): - pass - -LLVMBasicBlockRef = ctypes.POINTER(struct_LLVMOpaqueBasicBlock) -class struct_LLVMOpaqueMetadata(Structure): - pass - -LLVMMetadataRef = ctypes.POINTER(struct_LLVMOpaqueMetadata) -class struct_LLVMOpaqueNamedMDNode(Structure): - pass - -LLVMNamedMDNodeRef = ctypes.POINTER(struct_LLVMOpaqueNamedMDNode) -class struct_LLVMOpaqueValueMetadataEntry(Structure): - pass - -LLVMValueMetadataEntry = struct_LLVMOpaqueValueMetadataEntry -class struct_LLVMOpaqueBuilder(Structure): - pass - -LLVMBuilderRef = ctypes.POINTER(struct_LLVMOpaqueBuilder) -class struct_LLVMOpaqueDIBuilder(Structure): - pass - -LLVMDIBuilderRef = ctypes.POINTER(struct_LLVMOpaqueDIBuilder) -class struct_LLVMOpaqueModuleProvider(Structure): - pass - -LLVMModuleProviderRef = ctypes.POINTER(struct_LLVMOpaqueModuleProvider) -class struct_LLVMOpaquePassManager(Structure): - pass - -LLVMPassManagerRef = ctypes.POINTER(struct_LLVMOpaquePassManager) -class struct_LLVMOpaquePassRegistry(Structure): - pass - -LLVMPassRegistryRef = ctypes.POINTER(struct_LLVMOpaquePassRegistry) -class struct_LLVMOpaqueUse(Structure): - pass - -LLVMUseRef = ctypes.POINTER(struct_LLVMOpaqueUse) -class struct_LLVMOpaqueAttributeRef(Structure): - pass - -LLVMAttributeRef = ctypes.POINTER(struct_LLVMOpaqueAttributeRef) -class struct_LLVMOpaqueDiagnosticInfo(Structure): - pass - -LLVMDiagnosticInfoRef = ctypes.POINTER(struct_LLVMOpaqueDiagnosticInfo) -class struct_LLVMComdat(Structure): - pass - -LLVMComdatRef = ctypes.POINTER(struct_LLVMComdat) -class struct_LLVMOpaqueModuleFlagEntry(Structure): - pass - -LLVMModuleFlagEntry = struct_LLVMOpaqueModuleFlagEntry -class struct_LLVMOpaqueJITEventListener(Structure): - pass - -LLVMJITEventListenerRef = ctypes.POINTER(struct_LLVMOpaqueJITEventListener) -class struct_LLVMOpaqueBinary(Structure): - pass - -LLVMBinaryRef = ctypes.POINTER(struct_LLVMOpaqueBinary) - -# values for enumeration 'c__EA_LLVMVerifierFailureAction' -c__EA_LLVMVerifierFailureAction__enumvalues = { - 0: 'LLVMAbortProcessAction', - 1: 'LLVMPrintMessageAction', - 2: 'LLVMReturnStatusAction', -} -LLVMAbortProcessAction = 0 -LLVMPrintMessageAction = 1 -LLVMReturnStatusAction = 2 -c__EA_LLVMVerifierFailureAction = ctypes.c_uint32 # enum -LLVMVerifierFailureAction = c__EA_LLVMVerifierFailureAction -LLVMVerifierFailureAction__enumvalues = c__EA_LLVMVerifierFailureAction__enumvalues -try: - LLVMVerifyModule = _libraries['llvm'].LLVMVerifyModule - LLVMVerifyModule.restype = LLVMBool - LLVMVerifyModule.argtypes = [LLVMModuleRef, LLVMVerifierFailureAction, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMVerifyFunction = _libraries['llvm'].LLVMVerifyFunction - LLVMVerifyFunction.restype = LLVMBool - LLVMVerifyFunction.argtypes = [LLVMValueRef, LLVMVerifierFailureAction] -except AttributeError: - pass -try: - LLVMViewFunctionCFG = _libraries['llvm'].LLVMViewFunctionCFG - LLVMViewFunctionCFG.restype = None - LLVMViewFunctionCFG.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMViewFunctionCFGOnly = _libraries['llvm'].LLVMViewFunctionCFGOnly - LLVMViewFunctionCFGOnly.restype = None - LLVMViewFunctionCFGOnly.argtypes = [LLVMValueRef] -except AttributeError: - pass -LLVM_C_BITREADER_H = True # macro -try: - LLVMParseBitcode = _libraries['llvm'].LLVMParseBitcode - LLVMParseBitcode.restype = LLVMBool - LLVMParseBitcode.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMParseBitcode2 = _libraries['llvm'].LLVMParseBitcode2 - LLVMParseBitcode2.restype = LLVMBool - LLVMParseBitcode2.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMParseBitcodeInContext = _libraries['llvm'].LLVMParseBitcodeInContext - LLVMParseBitcodeInContext.restype = LLVMBool - LLVMParseBitcodeInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMParseBitcodeInContext2 = _libraries['llvm'].LLVMParseBitcodeInContext2 - LLVMParseBitcodeInContext2.restype = LLVMBool - LLVMParseBitcodeInContext2.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMGetBitcodeModuleInContext = _libraries['llvm'].LLVMGetBitcodeModuleInContext - LLVMGetBitcodeModuleInContext.restype = LLVMBool - LLVMGetBitcodeModuleInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetBitcodeModuleInContext2 = _libraries['llvm'].LLVMGetBitcodeModuleInContext2 - LLVMGetBitcodeModuleInContext2.restype = LLVMBool - LLVMGetBitcodeModuleInContext2.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMGetBitcodeModule = _libraries['llvm'].LLVMGetBitcodeModule - LLVMGetBitcodeModule.restype = LLVMBool - LLVMGetBitcodeModule.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetBitcodeModule2 = _libraries['llvm'].LLVMGetBitcodeModule2 - LLVMGetBitcodeModule2.restype = LLVMBool - LLVMGetBitcodeModule2.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -LLVM_C_BITWRITER_H = True # macro -try: - LLVMWriteBitcodeToFile = _libraries['llvm'].LLVMWriteBitcodeToFile - LLVMWriteBitcodeToFile.restype = ctypes.c_int32 - LLVMWriteBitcodeToFile.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMWriteBitcodeToFD = _libraries['llvm'].LLVMWriteBitcodeToFD - LLVMWriteBitcodeToFD.restype = ctypes.c_int32 - LLVMWriteBitcodeToFD.argtypes = [LLVMModuleRef, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMWriteBitcodeToFileHandle = _libraries['llvm'].LLVMWriteBitcodeToFileHandle - LLVMWriteBitcodeToFileHandle.restype = ctypes.c_int32 - LLVMWriteBitcodeToFileHandle.argtypes = [LLVMModuleRef, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMWriteBitcodeToMemoryBuffer = _libraries['llvm'].LLVMWriteBitcodeToMemoryBuffer - LLVMWriteBitcodeToMemoryBuffer.restype = LLVMMemoryBufferRef - LLVMWriteBitcodeToMemoryBuffer.argtypes = [LLVMModuleRef] -except AttributeError: - pass -LLVM_C_COMDAT_H = True # macro - -# values for enumeration 'c__EA_LLVMComdatSelectionKind' -c__EA_LLVMComdatSelectionKind__enumvalues = { - 0: 'LLVMAnyComdatSelectionKind', - 1: 'LLVMExactMatchComdatSelectionKind', - 2: 'LLVMLargestComdatSelectionKind', - 3: 'LLVMNoDeduplicateComdatSelectionKind', - 4: 'LLVMSameSizeComdatSelectionKind', -} -LLVMAnyComdatSelectionKind = 0 -LLVMExactMatchComdatSelectionKind = 1 -LLVMLargestComdatSelectionKind = 2 -LLVMNoDeduplicateComdatSelectionKind = 3 -LLVMSameSizeComdatSelectionKind = 4 -c__EA_LLVMComdatSelectionKind = ctypes.c_uint32 # enum -LLVMComdatSelectionKind = c__EA_LLVMComdatSelectionKind -LLVMComdatSelectionKind__enumvalues = c__EA_LLVMComdatSelectionKind__enumvalues -try: - LLVMGetOrInsertComdat = _libraries['llvm'].LLVMGetOrInsertComdat - LLVMGetOrInsertComdat.restype = LLVMComdatRef - LLVMGetOrInsertComdat.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetComdat = _libraries['llvm'].LLVMGetComdat - LLVMGetComdat.restype = LLVMComdatRef - LLVMGetComdat.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetComdat = _libraries['llvm'].LLVMSetComdat - LLVMSetComdat.restype = None - LLVMSetComdat.argtypes = [LLVMValueRef, LLVMComdatRef] -except AttributeError: - pass -try: - LLVMGetComdatSelectionKind = _libraries['llvm'].LLVMGetComdatSelectionKind - LLVMGetComdatSelectionKind.restype = LLVMComdatSelectionKind - LLVMGetComdatSelectionKind.argtypes = [LLVMComdatRef] -except AttributeError: - pass -try: - LLVMSetComdatSelectionKind = _libraries['llvm'].LLVMSetComdatSelectionKind - LLVMSetComdatSelectionKind.restype = None - LLVMSetComdatSelectionKind.argtypes = [LLVMComdatRef, LLVMComdatSelectionKind] -except AttributeError: - pass -LLVM_C_CORE_H = True # macro -LLVM_C_DEPRECATED_H = True # macro -# def LLVM_ATTRIBUTE_C_DEPRECATED(decl, message): # macro -# return decl((deprecated(message))) -LLVM_C_ERRORHANDLING_H = True # macro -# def LLVM_FOR_EACH_VALUE_SUBCLASS(macro): # macro -# return macro(Argument)macro(BasicBlock)macro(InlineAsm)macro(User)macro(Constant)macro(BlockAddress)macro(ConstantAggregateZero)macro(ConstantArray)macro(ConstantDataSequential)macro(ConstantDataArray)macro(ConstantDataVector)macro(ConstantExpr)macro(ConstantFP)macro(ConstantInt)macro(ConstantPointerNull)macro(ConstantStruct)macro(ConstantTokenNone)macro(ConstantVector)macro(GlobalValue)macro(GlobalAlias)macro(GlobalObject)macro(Function)macro(GlobalVariable)macro(GlobalIFunc)macro(UndefValue)macro(PoisonValue)macro(Instruction)macro(UnaryOperator)macro(BinaryOperator)macro(CallInst)macro(IntrinsicInst)macro(DbgInfoIntrinsic)macro(DbgVariableIntrinsic)macro(DbgDeclareInst)macro(DbgLabelInst)macro(MemIntrinsic)macro(MemCpyInst)macro(MemMoveInst)macro(MemSetInst)macro(CmpInst)macro(FCmpInst)macro(ICmpInst)macro(ExtractElementInst)macro(GetElementPtrInst)macro(InsertElementInst)macro(InsertValueInst)macro(LandingPadInst)macro(PHINode)macro(SelectInst)macro(ShuffleVectorInst)macro(StoreInst)macro(BranchInst)macro(IndirectBrInst)macro(InvokeInst)macro(ReturnInst)macro(SwitchInst)macro(UnreachableInst)macro(ResumeInst)macro(CleanupReturnInst)macro(CatchReturnInst)macro(CatchSwitchInst)macro(CallBrInst)macro(FuncletPadInst)macro(CatchPadInst)macro(CleanupPadInst)macro(UnaryInstruction)macro(AllocaInst)macro(CastInst)macro(AddrSpaceCastInst)macro(BitCastInst)macro(FPExtInst)macro(FPToSIInst)macro(FPToUIInst)macro(FPTruncInst)macro(IntToPtrInst)macro(PtrToIntInst)macro(SExtInst)macro(SIToFPInst)macro(TruncInst)macro(UIToFPInst)macro(ZExtInst)macro(ExtractValueInst)macro(LoadInst)macro(VAArgInst)macro(FreezeInst)macro(AtomicCmpXchgInst)macro(AtomicRMWInst)macro(FenceInst) -# def LLVM_DECLARE_VALUE_CAST(name): # macro -# return LLVMIsA##name(Val); -LLVMFatalErrorHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char)) -try: - LLVMInstallFatalErrorHandler = _libraries['llvm'].LLVMInstallFatalErrorHandler - LLVMInstallFatalErrorHandler.restype = None - LLVMInstallFatalErrorHandler.argtypes = [LLVMFatalErrorHandler] -except AttributeError: - pass -try: - LLVMResetFatalErrorHandler = _libraries['llvm'].LLVMResetFatalErrorHandler - LLVMResetFatalErrorHandler.restype = None - LLVMResetFatalErrorHandler.argtypes = [] -except AttributeError: - pass -try: - LLVMEnablePrettyStackTrace = _libraries['llvm'].LLVMEnablePrettyStackTrace - LLVMEnablePrettyStackTrace.restype = None - LLVMEnablePrettyStackTrace.argtypes = [] -except AttributeError: - pass - -# values for enumeration 'c__EA_LLVMOpcode' -c__EA_LLVMOpcode__enumvalues = { - 1: 'LLVMRet', - 2: 'LLVMBr', - 3: 'LLVMSwitch', - 4: 'LLVMIndirectBr', - 5: 'LLVMInvoke', - 7: 'LLVMUnreachable', - 67: 'LLVMCallBr', - 66: 'LLVMFNeg', - 8: 'LLVMAdd', - 9: 'LLVMFAdd', - 10: 'LLVMSub', - 11: 'LLVMFSub', - 12: 'LLVMMul', - 13: 'LLVMFMul', - 14: 'LLVMUDiv', - 15: 'LLVMSDiv', - 16: 'LLVMFDiv', - 17: 'LLVMURem', - 18: 'LLVMSRem', - 19: 'LLVMFRem', - 20: 'LLVMShl', - 21: 'LLVMLShr', - 22: 'LLVMAShr', - 23: 'LLVMAnd', - 24: 'LLVMOr', - 25: 'LLVMXor', - 26: 'LLVMAlloca', - 27: 'LLVMLoad', - 28: 'LLVMStore', - 29: 'LLVMGetElementPtr', - 30: 'LLVMTrunc', - 31: 'LLVMZExt', - 32: 'LLVMSExt', - 33: 'LLVMFPToUI', - 34: 'LLVMFPToSI', - 35: 'LLVMUIToFP', - 36: 'LLVMSIToFP', - 37: 'LLVMFPTrunc', - 38: 'LLVMFPExt', - 39: 'LLVMPtrToInt', - 40: 'LLVMIntToPtr', - 41: 'LLVMBitCast', - 60: 'LLVMAddrSpaceCast', - 42: 'LLVMICmp', - 43: 'LLVMFCmp', - 44: 'LLVMPHI', - 45: 'LLVMCall', - 46: 'LLVMSelect', - 47: 'LLVMUserOp1', - 48: 'LLVMUserOp2', - 49: 'LLVMVAArg', - 50: 'LLVMExtractElement', - 51: 'LLVMInsertElement', - 52: 'LLVMShuffleVector', - 53: 'LLVMExtractValue', - 54: 'LLVMInsertValue', - 68: 'LLVMFreeze', - 55: 'LLVMFence', - 56: 'LLVMAtomicCmpXchg', - 57: 'LLVMAtomicRMW', - 58: 'LLVMResume', - 59: 'LLVMLandingPad', - 61: 'LLVMCleanupRet', - 62: 'LLVMCatchRet', - 63: 'LLVMCatchPad', - 64: 'LLVMCleanupPad', - 65: 'LLVMCatchSwitch', -} -LLVMRet = 1 -LLVMBr = 2 -LLVMSwitch = 3 -LLVMIndirectBr = 4 -LLVMInvoke = 5 -LLVMUnreachable = 7 -LLVMCallBr = 67 -LLVMFNeg = 66 -LLVMAdd = 8 -LLVMFAdd = 9 -LLVMSub = 10 -LLVMFSub = 11 -LLVMMul = 12 -LLVMFMul = 13 -LLVMUDiv = 14 -LLVMSDiv = 15 -LLVMFDiv = 16 -LLVMURem = 17 -LLVMSRem = 18 -LLVMFRem = 19 -LLVMShl = 20 -LLVMLShr = 21 -LLVMAShr = 22 -LLVMAnd = 23 -LLVMOr = 24 -LLVMXor = 25 -LLVMAlloca = 26 -LLVMLoad = 27 -LLVMStore = 28 -LLVMGetElementPtr = 29 -LLVMTrunc = 30 -LLVMZExt = 31 -LLVMSExt = 32 -LLVMFPToUI = 33 -LLVMFPToSI = 34 -LLVMUIToFP = 35 -LLVMSIToFP = 36 -LLVMFPTrunc = 37 -LLVMFPExt = 38 -LLVMPtrToInt = 39 -LLVMIntToPtr = 40 -LLVMBitCast = 41 -LLVMAddrSpaceCast = 60 -LLVMICmp = 42 -LLVMFCmp = 43 -LLVMPHI = 44 -LLVMCall = 45 -LLVMSelect = 46 -LLVMUserOp1 = 47 -LLVMUserOp2 = 48 -LLVMVAArg = 49 -LLVMExtractElement = 50 -LLVMInsertElement = 51 -LLVMShuffleVector = 52 -LLVMExtractValue = 53 -LLVMInsertValue = 54 -LLVMFreeze = 68 -LLVMFence = 55 -LLVMAtomicCmpXchg = 56 -LLVMAtomicRMW = 57 -LLVMResume = 58 -LLVMLandingPad = 59 -LLVMCleanupRet = 61 -LLVMCatchRet = 62 -LLVMCatchPad = 63 -LLVMCleanupPad = 64 -LLVMCatchSwitch = 65 -c__EA_LLVMOpcode = ctypes.c_uint32 # enum -LLVMOpcode = c__EA_LLVMOpcode -LLVMOpcode__enumvalues = c__EA_LLVMOpcode__enumvalues - -# values for enumeration 'c__EA_LLVMTypeKind' -c__EA_LLVMTypeKind__enumvalues = { - 0: 'LLVMVoidTypeKind', - 1: 'LLVMHalfTypeKind', - 2: 'LLVMFloatTypeKind', - 3: 'LLVMDoubleTypeKind', - 4: 'LLVMX86_FP80TypeKind', - 5: 'LLVMFP128TypeKind', - 6: 'LLVMPPC_FP128TypeKind', - 7: 'LLVMLabelTypeKind', - 8: 'LLVMIntegerTypeKind', - 9: 'LLVMFunctionTypeKind', - 10: 'LLVMStructTypeKind', - 11: 'LLVMArrayTypeKind', - 12: 'LLVMPointerTypeKind', - 13: 'LLVMVectorTypeKind', - 14: 'LLVMMetadataTypeKind', - 15: 'LLVMX86_MMXTypeKind', - 16: 'LLVMTokenTypeKind', - 17: 'LLVMScalableVectorTypeKind', - 18: 'LLVMBFloatTypeKind', - 19: 'LLVMX86_AMXTypeKind', -} -LLVMVoidTypeKind = 0 -LLVMHalfTypeKind = 1 -LLVMFloatTypeKind = 2 -LLVMDoubleTypeKind = 3 -LLVMX86_FP80TypeKind = 4 -LLVMFP128TypeKind = 5 -LLVMPPC_FP128TypeKind = 6 -LLVMLabelTypeKind = 7 -LLVMIntegerTypeKind = 8 -LLVMFunctionTypeKind = 9 -LLVMStructTypeKind = 10 -LLVMArrayTypeKind = 11 -LLVMPointerTypeKind = 12 -LLVMVectorTypeKind = 13 -LLVMMetadataTypeKind = 14 -LLVMX86_MMXTypeKind = 15 -LLVMTokenTypeKind = 16 -LLVMScalableVectorTypeKind = 17 -LLVMBFloatTypeKind = 18 -LLVMX86_AMXTypeKind = 19 -c__EA_LLVMTypeKind = ctypes.c_uint32 # enum -LLVMTypeKind = c__EA_LLVMTypeKind -LLVMTypeKind__enumvalues = c__EA_LLVMTypeKind__enumvalues - -# values for enumeration 'c__EA_LLVMLinkage' -c__EA_LLVMLinkage__enumvalues = { - 0: 'LLVMExternalLinkage', - 1: 'LLVMAvailableExternallyLinkage', - 2: 'LLVMLinkOnceAnyLinkage', - 3: 'LLVMLinkOnceODRLinkage', - 4: 'LLVMLinkOnceODRAutoHideLinkage', - 5: 'LLVMWeakAnyLinkage', - 6: 'LLVMWeakODRLinkage', - 7: 'LLVMAppendingLinkage', - 8: 'LLVMInternalLinkage', - 9: 'LLVMPrivateLinkage', - 10: 'LLVMDLLImportLinkage', - 11: 'LLVMDLLExportLinkage', - 12: 'LLVMExternalWeakLinkage', - 13: 'LLVMGhostLinkage', - 14: 'LLVMCommonLinkage', - 15: 'LLVMLinkerPrivateLinkage', - 16: 'LLVMLinkerPrivateWeakLinkage', -} -LLVMExternalLinkage = 0 -LLVMAvailableExternallyLinkage = 1 -LLVMLinkOnceAnyLinkage = 2 -LLVMLinkOnceODRLinkage = 3 -LLVMLinkOnceODRAutoHideLinkage = 4 -LLVMWeakAnyLinkage = 5 -LLVMWeakODRLinkage = 6 -LLVMAppendingLinkage = 7 -LLVMInternalLinkage = 8 -LLVMPrivateLinkage = 9 -LLVMDLLImportLinkage = 10 -LLVMDLLExportLinkage = 11 -LLVMExternalWeakLinkage = 12 -LLVMGhostLinkage = 13 -LLVMCommonLinkage = 14 -LLVMLinkerPrivateLinkage = 15 -LLVMLinkerPrivateWeakLinkage = 16 -c__EA_LLVMLinkage = ctypes.c_uint32 # enum -LLVMLinkage = c__EA_LLVMLinkage -LLVMLinkage__enumvalues = c__EA_LLVMLinkage__enumvalues - -# values for enumeration 'c__EA_LLVMVisibility' -c__EA_LLVMVisibility__enumvalues = { - 0: 'LLVMDefaultVisibility', - 1: 'LLVMHiddenVisibility', - 2: 'LLVMProtectedVisibility', -} -LLVMDefaultVisibility = 0 -LLVMHiddenVisibility = 1 -LLVMProtectedVisibility = 2 -c__EA_LLVMVisibility = ctypes.c_uint32 # enum -LLVMVisibility = c__EA_LLVMVisibility -LLVMVisibility__enumvalues = c__EA_LLVMVisibility__enumvalues - -# values for enumeration 'c__EA_LLVMUnnamedAddr' -c__EA_LLVMUnnamedAddr__enumvalues = { - 0: 'LLVMNoUnnamedAddr', - 1: 'LLVMLocalUnnamedAddr', - 2: 'LLVMGlobalUnnamedAddr', -} -LLVMNoUnnamedAddr = 0 -LLVMLocalUnnamedAddr = 1 -LLVMGlobalUnnamedAddr = 2 -c__EA_LLVMUnnamedAddr = ctypes.c_uint32 # enum -LLVMUnnamedAddr = c__EA_LLVMUnnamedAddr -LLVMUnnamedAddr__enumvalues = c__EA_LLVMUnnamedAddr__enumvalues - -# values for enumeration 'c__EA_LLVMDLLStorageClass' -c__EA_LLVMDLLStorageClass__enumvalues = { - 0: 'LLVMDefaultStorageClass', - 1: 'LLVMDLLImportStorageClass', - 2: 'LLVMDLLExportStorageClass', -} -LLVMDefaultStorageClass = 0 -LLVMDLLImportStorageClass = 1 -LLVMDLLExportStorageClass = 2 -c__EA_LLVMDLLStorageClass = ctypes.c_uint32 # enum -LLVMDLLStorageClass = c__EA_LLVMDLLStorageClass -LLVMDLLStorageClass__enumvalues = c__EA_LLVMDLLStorageClass__enumvalues - -# values for enumeration 'c__EA_LLVMCallConv' -c__EA_LLVMCallConv__enumvalues = { - 0: 'LLVMCCallConv', - 8: 'LLVMFastCallConv', - 9: 'LLVMColdCallConv', - 10: 'LLVMGHCCallConv', - 11: 'LLVMHiPECallConv', - 12: 'LLVMWebKitJSCallConv', - 13: 'LLVMAnyRegCallConv', - 14: 'LLVMPreserveMostCallConv', - 15: 'LLVMPreserveAllCallConv', - 16: 'LLVMSwiftCallConv', - 17: 'LLVMCXXFASTTLSCallConv', - 64: 'LLVMX86StdcallCallConv', - 65: 'LLVMX86FastcallCallConv', - 66: 'LLVMARMAPCSCallConv', - 67: 'LLVMARMAAPCSCallConv', - 68: 'LLVMARMAAPCSVFPCallConv', - 69: 'LLVMMSP430INTRCallConv', - 70: 'LLVMX86ThisCallCallConv', - 71: 'LLVMPTXKernelCallConv', - 72: 'LLVMPTXDeviceCallConv', - 75: 'LLVMSPIRFUNCCallConv', - 76: 'LLVMSPIRKERNELCallConv', - 77: 'LLVMIntelOCLBICallConv', - 78: 'LLVMX8664SysVCallConv', - 79: 'LLVMWin64CallConv', - 80: 'LLVMX86VectorCallCallConv', - 81: 'LLVMHHVMCallConv', - 82: 'LLVMHHVMCCallConv', - 83: 'LLVMX86INTRCallConv', - 84: 'LLVMAVRINTRCallConv', - 85: 'LLVMAVRSIGNALCallConv', - 86: 'LLVMAVRBUILTINCallConv', - 87: 'LLVMAMDGPUVSCallConv', - 88: 'LLVMAMDGPUGSCallConv', - 89: 'LLVMAMDGPUPSCallConv', - 90: 'LLVMAMDGPUCSCallConv', - 91: 'LLVMAMDGPUKERNELCallConv', - 92: 'LLVMX86RegCallCallConv', - 93: 'LLVMAMDGPUHSCallConv', - 94: 'LLVMMSP430BUILTINCallConv', - 95: 'LLVMAMDGPULSCallConv', - 96: 'LLVMAMDGPUESCallConv', -} -LLVMCCallConv = 0 -LLVMFastCallConv = 8 -LLVMColdCallConv = 9 -LLVMGHCCallConv = 10 -LLVMHiPECallConv = 11 -LLVMWebKitJSCallConv = 12 -LLVMAnyRegCallConv = 13 -LLVMPreserveMostCallConv = 14 -LLVMPreserveAllCallConv = 15 -LLVMSwiftCallConv = 16 -LLVMCXXFASTTLSCallConv = 17 -LLVMX86StdcallCallConv = 64 -LLVMX86FastcallCallConv = 65 -LLVMARMAPCSCallConv = 66 -LLVMARMAAPCSCallConv = 67 -LLVMARMAAPCSVFPCallConv = 68 -LLVMMSP430INTRCallConv = 69 -LLVMX86ThisCallCallConv = 70 -LLVMPTXKernelCallConv = 71 -LLVMPTXDeviceCallConv = 72 -LLVMSPIRFUNCCallConv = 75 -LLVMSPIRKERNELCallConv = 76 -LLVMIntelOCLBICallConv = 77 -LLVMX8664SysVCallConv = 78 -LLVMWin64CallConv = 79 -LLVMX86VectorCallCallConv = 80 -LLVMHHVMCallConv = 81 -LLVMHHVMCCallConv = 82 -LLVMX86INTRCallConv = 83 -LLVMAVRINTRCallConv = 84 -LLVMAVRSIGNALCallConv = 85 -LLVMAVRBUILTINCallConv = 86 -LLVMAMDGPUVSCallConv = 87 -LLVMAMDGPUGSCallConv = 88 -LLVMAMDGPUPSCallConv = 89 -LLVMAMDGPUCSCallConv = 90 -LLVMAMDGPUKERNELCallConv = 91 -LLVMX86RegCallCallConv = 92 -LLVMAMDGPUHSCallConv = 93 -LLVMMSP430BUILTINCallConv = 94 -LLVMAMDGPULSCallConv = 95 -LLVMAMDGPUESCallConv = 96 -c__EA_LLVMCallConv = ctypes.c_uint32 # enum -LLVMCallConv = c__EA_LLVMCallConv -LLVMCallConv__enumvalues = c__EA_LLVMCallConv__enumvalues - -# values for enumeration 'c__EA_LLVMValueKind' -c__EA_LLVMValueKind__enumvalues = { - 0: 'LLVMArgumentValueKind', - 1: 'LLVMBasicBlockValueKind', - 2: 'LLVMMemoryUseValueKind', - 3: 'LLVMMemoryDefValueKind', - 4: 'LLVMMemoryPhiValueKind', - 5: 'LLVMFunctionValueKind', - 6: 'LLVMGlobalAliasValueKind', - 7: 'LLVMGlobalIFuncValueKind', - 8: 'LLVMGlobalVariableValueKind', - 9: 'LLVMBlockAddressValueKind', - 10: 'LLVMConstantExprValueKind', - 11: 'LLVMConstantArrayValueKind', - 12: 'LLVMConstantStructValueKind', - 13: 'LLVMConstantVectorValueKind', - 14: 'LLVMUndefValueValueKind', - 15: 'LLVMConstantAggregateZeroValueKind', - 16: 'LLVMConstantDataArrayValueKind', - 17: 'LLVMConstantDataVectorValueKind', - 18: 'LLVMConstantIntValueKind', - 19: 'LLVMConstantFPValueKind', - 20: 'LLVMConstantPointerNullValueKind', - 21: 'LLVMConstantTokenNoneValueKind', - 22: 'LLVMMetadataAsValueValueKind', - 23: 'LLVMInlineAsmValueKind', - 24: 'LLVMInstructionValueKind', - 25: 'LLVMPoisonValueValueKind', -} -LLVMArgumentValueKind = 0 -LLVMBasicBlockValueKind = 1 -LLVMMemoryUseValueKind = 2 -LLVMMemoryDefValueKind = 3 -LLVMMemoryPhiValueKind = 4 -LLVMFunctionValueKind = 5 -LLVMGlobalAliasValueKind = 6 -LLVMGlobalIFuncValueKind = 7 -LLVMGlobalVariableValueKind = 8 -LLVMBlockAddressValueKind = 9 -LLVMConstantExprValueKind = 10 -LLVMConstantArrayValueKind = 11 -LLVMConstantStructValueKind = 12 -LLVMConstantVectorValueKind = 13 -LLVMUndefValueValueKind = 14 -LLVMConstantAggregateZeroValueKind = 15 -LLVMConstantDataArrayValueKind = 16 -LLVMConstantDataVectorValueKind = 17 -LLVMConstantIntValueKind = 18 -LLVMConstantFPValueKind = 19 -LLVMConstantPointerNullValueKind = 20 -LLVMConstantTokenNoneValueKind = 21 -LLVMMetadataAsValueValueKind = 22 -LLVMInlineAsmValueKind = 23 -LLVMInstructionValueKind = 24 -LLVMPoisonValueValueKind = 25 -c__EA_LLVMValueKind = ctypes.c_uint32 # enum -LLVMValueKind = c__EA_LLVMValueKind -LLVMValueKind__enumvalues = c__EA_LLVMValueKind__enumvalues - -# values for enumeration 'c__EA_LLVMIntPredicate' -c__EA_LLVMIntPredicate__enumvalues = { - 32: 'LLVMIntEQ', - 33: 'LLVMIntNE', - 34: 'LLVMIntUGT', - 35: 'LLVMIntUGE', - 36: 'LLVMIntULT', - 37: 'LLVMIntULE', - 38: 'LLVMIntSGT', - 39: 'LLVMIntSGE', - 40: 'LLVMIntSLT', - 41: 'LLVMIntSLE', -} -LLVMIntEQ = 32 -LLVMIntNE = 33 -LLVMIntUGT = 34 -LLVMIntUGE = 35 -LLVMIntULT = 36 -LLVMIntULE = 37 -LLVMIntSGT = 38 -LLVMIntSGE = 39 -LLVMIntSLT = 40 -LLVMIntSLE = 41 -c__EA_LLVMIntPredicate = ctypes.c_uint32 # enum -LLVMIntPredicate = c__EA_LLVMIntPredicate -LLVMIntPredicate__enumvalues = c__EA_LLVMIntPredicate__enumvalues - -# values for enumeration 'c__EA_LLVMRealPredicate' -c__EA_LLVMRealPredicate__enumvalues = { - 0: 'LLVMRealPredicateFalse', - 1: 'LLVMRealOEQ', - 2: 'LLVMRealOGT', - 3: 'LLVMRealOGE', - 4: 'LLVMRealOLT', - 5: 'LLVMRealOLE', - 6: 'LLVMRealONE', - 7: 'LLVMRealORD', - 8: 'LLVMRealUNO', - 9: 'LLVMRealUEQ', - 10: 'LLVMRealUGT', - 11: 'LLVMRealUGE', - 12: 'LLVMRealULT', - 13: 'LLVMRealULE', - 14: 'LLVMRealUNE', - 15: 'LLVMRealPredicateTrue', -} -LLVMRealPredicateFalse = 0 -LLVMRealOEQ = 1 -LLVMRealOGT = 2 -LLVMRealOGE = 3 -LLVMRealOLT = 4 -LLVMRealOLE = 5 -LLVMRealONE = 6 -LLVMRealORD = 7 -LLVMRealUNO = 8 -LLVMRealUEQ = 9 -LLVMRealUGT = 10 -LLVMRealUGE = 11 -LLVMRealULT = 12 -LLVMRealULE = 13 -LLVMRealUNE = 14 -LLVMRealPredicateTrue = 15 -c__EA_LLVMRealPredicate = ctypes.c_uint32 # enum -LLVMRealPredicate = c__EA_LLVMRealPredicate -LLVMRealPredicate__enumvalues = c__EA_LLVMRealPredicate__enumvalues - -# values for enumeration 'c__EA_LLVMLandingPadClauseTy' -c__EA_LLVMLandingPadClauseTy__enumvalues = { - 0: 'LLVMLandingPadCatch', - 1: 'LLVMLandingPadFilter', -} -LLVMLandingPadCatch = 0 -LLVMLandingPadFilter = 1 -c__EA_LLVMLandingPadClauseTy = ctypes.c_uint32 # enum -LLVMLandingPadClauseTy = c__EA_LLVMLandingPadClauseTy -LLVMLandingPadClauseTy__enumvalues = c__EA_LLVMLandingPadClauseTy__enumvalues - -# values for enumeration 'c__EA_LLVMThreadLocalMode' -c__EA_LLVMThreadLocalMode__enumvalues = { - 0: 'LLVMNotThreadLocal', - 1: 'LLVMGeneralDynamicTLSModel', - 2: 'LLVMLocalDynamicTLSModel', - 3: 'LLVMInitialExecTLSModel', - 4: 'LLVMLocalExecTLSModel', -} -LLVMNotThreadLocal = 0 -LLVMGeneralDynamicTLSModel = 1 -LLVMLocalDynamicTLSModel = 2 -LLVMInitialExecTLSModel = 3 -LLVMLocalExecTLSModel = 4 -c__EA_LLVMThreadLocalMode = ctypes.c_uint32 # enum -LLVMThreadLocalMode = c__EA_LLVMThreadLocalMode -LLVMThreadLocalMode__enumvalues = c__EA_LLVMThreadLocalMode__enumvalues - -# values for enumeration 'c__EA_LLVMAtomicOrdering' -c__EA_LLVMAtomicOrdering__enumvalues = { - 0: 'LLVMAtomicOrderingNotAtomic', - 1: 'LLVMAtomicOrderingUnordered', - 2: 'LLVMAtomicOrderingMonotonic', - 4: 'LLVMAtomicOrderingAcquire', - 5: 'LLVMAtomicOrderingRelease', - 6: 'LLVMAtomicOrderingAcquireRelease', - 7: 'LLVMAtomicOrderingSequentiallyConsistent', -} -LLVMAtomicOrderingNotAtomic = 0 -LLVMAtomicOrderingUnordered = 1 -LLVMAtomicOrderingMonotonic = 2 -LLVMAtomicOrderingAcquire = 4 -LLVMAtomicOrderingRelease = 5 -LLVMAtomicOrderingAcquireRelease = 6 -LLVMAtomicOrderingSequentiallyConsistent = 7 -c__EA_LLVMAtomicOrdering = ctypes.c_uint32 # enum -LLVMAtomicOrdering = c__EA_LLVMAtomicOrdering -LLVMAtomicOrdering__enumvalues = c__EA_LLVMAtomicOrdering__enumvalues - -# values for enumeration 'c__EA_LLVMAtomicRMWBinOp' -c__EA_LLVMAtomicRMWBinOp__enumvalues = { - 0: 'LLVMAtomicRMWBinOpXchg', - 1: 'LLVMAtomicRMWBinOpAdd', - 2: 'LLVMAtomicRMWBinOpSub', - 3: 'LLVMAtomicRMWBinOpAnd', - 4: 'LLVMAtomicRMWBinOpNand', - 5: 'LLVMAtomicRMWBinOpOr', - 6: 'LLVMAtomicRMWBinOpXor', - 7: 'LLVMAtomicRMWBinOpMax', - 8: 'LLVMAtomicRMWBinOpMin', - 9: 'LLVMAtomicRMWBinOpUMax', - 10: 'LLVMAtomicRMWBinOpUMin', - 11: 'LLVMAtomicRMWBinOpFAdd', - 12: 'LLVMAtomicRMWBinOpFSub', -} -LLVMAtomicRMWBinOpXchg = 0 -LLVMAtomicRMWBinOpAdd = 1 -LLVMAtomicRMWBinOpSub = 2 -LLVMAtomicRMWBinOpAnd = 3 -LLVMAtomicRMWBinOpNand = 4 -LLVMAtomicRMWBinOpOr = 5 -LLVMAtomicRMWBinOpXor = 6 -LLVMAtomicRMWBinOpMax = 7 -LLVMAtomicRMWBinOpMin = 8 -LLVMAtomicRMWBinOpUMax = 9 -LLVMAtomicRMWBinOpUMin = 10 -LLVMAtomicRMWBinOpFAdd = 11 -LLVMAtomicRMWBinOpFSub = 12 -c__EA_LLVMAtomicRMWBinOp = ctypes.c_uint32 # enum -LLVMAtomicRMWBinOp = c__EA_LLVMAtomicRMWBinOp -LLVMAtomicRMWBinOp__enumvalues = c__EA_LLVMAtomicRMWBinOp__enumvalues - -# values for enumeration 'c__EA_LLVMDiagnosticSeverity' -c__EA_LLVMDiagnosticSeverity__enumvalues = { - 0: 'LLVMDSError', - 1: 'LLVMDSWarning', - 2: 'LLVMDSRemark', - 3: 'LLVMDSNote', -} -LLVMDSError = 0 -LLVMDSWarning = 1 -LLVMDSRemark = 2 -LLVMDSNote = 3 -c__EA_LLVMDiagnosticSeverity = ctypes.c_uint32 # enum -LLVMDiagnosticSeverity = c__EA_LLVMDiagnosticSeverity -LLVMDiagnosticSeverity__enumvalues = c__EA_LLVMDiagnosticSeverity__enumvalues - -# values for enumeration 'c__EA_LLVMInlineAsmDialect' -c__EA_LLVMInlineAsmDialect__enumvalues = { - 0: 'LLVMInlineAsmDialectATT', - 1: 'LLVMInlineAsmDialectIntel', -} -LLVMInlineAsmDialectATT = 0 -LLVMInlineAsmDialectIntel = 1 -c__EA_LLVMInlineAsmDialect = ctypes.c_uint32 # enum -LLVMInlineAsmDialect = c__EA_LLVMInlineAsmDialect -LLVMInlineAsmDialect__enumvalues = c__EA_LLVMInlineAsmDialect__enumvalues - -# values for enumeration 'c__EA_LLVMModuleFlagBehavior' -c__EA_LLVMModuleFlagBehavior__enumvalues = { - 0: 'LLVMModuleFlagBehaviorError', - 1: 'LLVMModuleFlagBehaviorWarning', - 2: 'LLVMModuleFlagBehaviorRequire', - 3: 'LLVMModuleFlagBehaviorOverride', - 4: 'LLVMModuleFlagBehaviorAppend', - 5: 'LLVMModuleFlagBehaviorAppendUnique', -} -LLVMModuleFlagBehaviorError = 0 -LLVMModuleFlagBehaviorWarning = 1 -LLVMModuleFlagBehaviorRequire = 2 -LLVMModuleFlagBehaviorOverride = 3 -LLVMModuleFlagBehaviorAppend = 4 -LLVMModuleFlagBehaviorAppendUnique = 5 -c__EA_LLVMModuleFlagBehavior = ctypes.c_uint32 # enum -LLVMModuleFlagBehavior = c__EA_LLVMModuleFlagBehavior -LLVMModuleFlagBehavior__enumvalues = c__EA_LLVMModuleFlagBehavior__enumvalues - -# values for enumeration 'c__Ea_LLVMAttributeReturnIndex' -c__Ea_LLVMAttributeReturnIndex__enumvalues = { - 0: 'LLVMAttributeReturnIndex', - -1: 'LLVMAttributeFunctionIndex', -} -LLVMAttributeReturnIndex = 0 -LLVMAttributeFunctionIndex = -1 -c__Ea_LLVMAttributeReturnIndex = ctypes.c_int32 # enum -LLVMAttributeIndex = ctypes.c_uint32 -try: - LLVMInitializeCore = _libraries['llvm'].LLVMInitializeCore - LLVMInitializeCore.restype = None - LLVMInitializeCore.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMShutdown = _libraries['llvm'].LLVMShutdown - LLVMShutdown.restype = None - LLVMShutdown.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateMessage = _libraries['llvm'].LLVMCreateMessage - LLVMCreateMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMCreateMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeMessage = _libraries['llvm'].LLVMDisposeMessage - LLVMDisposeMessage.restype = None - LLVMDisposeMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -LLVMDiagnosticHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueDiagnosticInfo), ctypes.POINTER(None)) -LLVMYieldCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueContext), ctypes.POINTER(None)) -try: - LLVMContextCreate = _libraries['llvm'].LLVMContextCreate - LLVMContextCreate.restype = LLVMContextRef - LLVMContextCreate.argtypes = [] -except AttributeError: - pass -try: - LLVMGetGlobalContext = _libraries['llvm'].LLVMGetGlobalContext - LLVMGetGlobalContext.restype = LLVMContextRef - LLVMGetGlobalContext.argtypes = [] -except AttributeError: - pass -try: - LLVMContextSetDiagnosticHandler = _libraries['llvm'].LLVMContextSetDiagnosticHandler - LLVMContextSetDiagnosticHandler.restype = None - LLVMContextSetDiagnosticHandler.argtypes = [LLVMContextRef, LLVMDiagnosticHandler, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMContextGetDiagnosticHandler = _libraries['llvm'].LLVMContextGetDiagnosticHandler - LLVMContextGetDiagnosticHandler.restype = LLVMDiagnosticHandler - LLVMContextGetDiagnosticHandler.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextGetDiagnosticContext = _libraries['llvm'].LLVMContextGetDiagnosticContext - LLVMContextGetDiagnosticContext.restype = ctypes.POINTER(None) - LLVMContextGetDiagnosticContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextSetYieldCallback = _libraries['llvm'].LLVMContextSetYieldCallback - LLVMContextSetYieldCallback.restype = None - LLVMContextSetYieldCallback.argtypes = [LLVMContextRef, LLVMYieldCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMContextShouldDiscardValueNames = _libraries['llvm'].LLVMContextShouldDiscardValueNames - LLVMContextShouldDiscardValueNames.restype = LLVMBool - LLVMContextShouldDiscardValueNames.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextSetDiscardValueNames = _libraries['llvm'].LLVMContextSetDiscardValueNames - LLVMContextSetDiscardValueNames.restype = None - LLVMContextSetDiscardValueNames.argtypes = [LLVMContextRef, LLVMBool] -except AttributeError: - pass -try: - LLVMContextDispose = _libraries['llvm'].LLVMContextDispose - LLVMContextDispose.restype = None - LLVMContextDispose.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMGetDiagInfoDescription = _libraries['llvm'].LLVMGetDiagInfoDescription - LLVMGetDiagInfoDescription.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDiagInfoDescription.argtypes = [LLVMDiagnosticInfoRef] -except AttributeError: - pass -try: - LLVMGetDiagInfoSeverity = _libraries['llvm'].LLVMGetDiagInfoSeverity - LLVMGetDiagInfoSeverity.restype = LLVMDiagnosticSeverity - LLVMGetDiagInfoSeverity.argtypes = [LLVMDiagnosticInfoRef] -except AttributeError: - pass -try: - LLVMGetMDKindIDInContext = _libraries['llvm'].LLVMGetMDKindIDInContext - LLVMGetMDKindIDInContext.restype = ctypes.c_uint32 - LLVMGetMDKindIDInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetMDKindID = _libraries['llvm'].LLVMGetMDKindID - LLVMGetMDKindID.restype = ctypes.c_uint32 - LLVMGetMDKindID.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - LLVMGetEnumAttributeKindForName = _libraries['llvm'].LLVMGetEnumAttributeKindForName - LLVMGetEnumAttributeKindForName.restype = ctypes.c_uint32 - LLVMGetEnumAttributeKindForName.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetLastEnumAttributeKind = _libraries['llvm'].LLVMGetLastEnumAttributeKind - LLVMGetLastEnumAttributeKind.restype = ctypes.c_uint32 - LLVMGetLastEnumAttributeKind.argtypes = [] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - LLVMCreateEnumAttribute = _libraries['llvm'].LLVMCreateEnumAttribute - LLVMCreateEnumAttribute.restype = LLVMAttributeRef - LLVMCreateEnumAttribute.argtypes = [LLVMContextRef, ctypes.c_uint32, uint64_t] -except AttributeError: - pass -try: - LLVMGetEnumAttributeKind = _libraries['llvm'].LLVMGetEnumAttributeKind - LLVMGetEnumAttributeKind.restype = ctypes.c_uint32 - LLVMGetEnumAttributeKind.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetEnumAttributeValue = _libraries['llvm'].LLVMGetEnumAttributeValue - LLVMGetEnumAttributeValue.restype = uint64_t - LLVMGetEnumAttributeValue.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMCreateTypeAttribute = _libraries['llvm'].LLVMCreateTypeAttribute - LLVMCreateTypeAttribute.restype = LLVMAttributeRef - LLVMCreateTypeAttribute.argtypes = [LLVMContextRef, ctypes.c_uint32, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetTypeAttributeValue = _libraries['llvm'].LLVMGetTypeAttributeValue - LLVMGetTypeAttributeValue.restype = LLVMTypeRef - LLVMGetTypeAttributeValue.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMCreateStringAttribute = _libraries['llvm'].LLVMCreateStringAttribute - LLVMCreateStringAttribute.restype = LLVMAttributeRef - LLVMCreateStringAttribute.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetStringAttributeKind = _libraries['llvm'].LLVMGetStringAttributeKind - LLVMGetStringAttributeKind.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStringAttributeKind.argtypes = [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetStringAttributeValue = _libraries['llvm'].LLVMGetStringAttributeValue - LLVMGetStringAttributeValue.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStringAttributeValue.argtypes = [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMIsEnumAttribute = _libraries['llvm'].LLVMIsEnumAttribute - LLVMIsEnumAttribute.restype = LLVMBool - LLVMIsEnumAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMIsStringAttribute = _libraries['llvm'].LLVMIsStringAttribute - LLVMIsStringAttribute.restype = LLVMBool - LLVMIsStringAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMIsTypeAttribute = _libraries['llvm'].LLVMIsTypeAttribute - LLVMIsTypeAttribute.restype = LLVMBool - LLVMIsTypeAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetTypeByName2 = _libraries['llvm'].LLVMGetTypeByName2 - LLVMGetTypeByName2.restype = LLVMTypeRef - LLVMGetTypeByName2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMModuleCreateWithName = _libraries['llvm'].LLVMModuleCreateWithName - LLVMModuleCreateWithName.restype = LLVMModuleRef - LLVMModuleCreateWithName.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMModuleCreateWithNameInContext = _libraries['llvm'].LLVMModuleCreateWithNameInContext - LLVMModuleCreateWithNameInContext.restype = LLVMModuleRef - LLVMModuleCreateWithNameInContext.argtypes = [ctypes.POINTER(ctypes.c_char), LLVMContextRef] -except AttributeError: - pass -try: - LLVMCloneModule = _libraries['llvm'].LLVMCloneModule - LLVMCloneModule.restype = LLVMModuleRef - LLVMCloneModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeModule = _libraries['llvm'].LLVMDisposeModule - LLVMDisposeModule.restype = None - LLVMDisposeModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetModuleIdentifier = _libraries['llvm'].LLVMGetModuleIdentifier - LLVMGetModuleIdentifier.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetModuleIdentifier.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetModuleIdentifier = _libraries['llvm'].LLVMSetModuleIdentifier - LLVMSetModuleIdentifier.restype = None - LLVMSetModuleIdentifier.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetSourceFileName = _libraries['llvm'].LLVMGetSourceFileName - LLVMGetSourceFileName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSourceFileName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetSourceFileName = _libraries['llvm'].LLVMSetSourceFileName - LLVMSetSourceFileName.restype = None - LLVMSetSourceFileName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetDataLayoutStr = _libraries['llvm'].LLVMGetDataLayoutStr - LLVMGetDataLayoutStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDataLayoutStr.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetDataLayout = _libraries['llvm'].LLVMGetDataLayout - LLVMGetDataLayout.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDataLayout.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetDataLayout = _libraries['llvm'].LLVMSetDataLayout - LLVMSetDataLayout.restype = None - LLVMSetDataLayout.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTarget = _libraries['llvm'].LLVMGetTarget - LLVMGetTarget.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTarget.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetTarget = _libraries['llvm'].LLVMSetTarget - LLVMSetTarget.restype = None - LLVMSetTarget.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMCopyModuleFlagsMetadata = _libraries['llvm'].LLVMCopyModuleFlagsMetadata - LLVMCopyModuleFlagsMetadata.restype = ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry) - LLVMCopyModuleFlagsMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDisposeModuleFlagsMetadata = _libraries['llvm'].LLVMDisposeModuleFlagsMetadata - LLVMDisposeModuleFlagsMetadata.restype = None - LLVMDisposeModuleFlagsMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry)] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetFlagBehavior = _libraries['llvm'].LLVMModuleFlagEntriesGetFlagBehavior - LLVMModuleFlagEntriesGetFlagBehavior.restype = LLVMModuleFlagBehavior - LLVMModuleFlagEntriesGetFlagBehavior.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetKey = _libraries['llvm'].LLVMModuleFlagEntriesGetKey - LLVMModuleFlagEntriesGetKey.restype = ctypes.POINTER(ctypes.c_char) - LLVMModuleFlagEntriesGetKey.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetMetadata = _libraries['llvm'].LLVMModuleFlagEntriesGetMetadata - LLVMModuleFlagEntriesGetMetadata.restype = LLVMMetadataRef - LLVMModuleFlagEntriesGetMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetModuleFlag = _libraries['llvm'].LLVMGetModuleFlag - LLVMGetModuleFlag.restype = LLVMMetadataRef - LLVMGetModuleFlag.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMAddModuleFlag = _libraries['llvm'].LLVMAddModuleFlag - LLVMAddModuleFlag.restype = None - LLVMAddModuleFlag.argtypes = [LLVMModuleRef, LLVMModuleFlagBehavior, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDumpModule = _libraries['llvm'].LLVMDumpModule - LLVMDumpModule.restype = None - LLVMDumpModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMPrintModuleToFile = _libraries['llvm'].LLVMPrintModuleToFile - LLVMPrintModuleToFile.restype = LLVMBool - LLVMPrintModuleToFile.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMPrintModuleToString = _libraries['llvm'].LLVMPrintModuleToString - LLVMPrintModuleToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintModuleToString.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetModuleInlineAsm = _libraries['llvm'].LLVMGetModuleInlineAsm - LLVMGetModuleInlineAsm.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetModuleInlineAsm2 = _libraries['llvm'].LLVMSetModuleInlineAsm2 - LLVMSetModuleInlineAsm2.restype = None - LLVMSetModuleInlineAsm2.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMAppendModuleInlineAsm = _libraries['llvm'].LLVMAppendModuleInlineAsm - LLVMAppendModuleInlineAsm.restype = None - LLVMAppendModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetInlineAsm = _libraries['llvm'].LLVMGetInlineAsm - LLVMGetInlineAsm.restype = LLVMValueRef - LLVMGetInlineAsm.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, LLVMBool, LLVMInlineAsmDialect, LLVMBool] -except AttributeError: - pass -try: - LLVMGetModuleContext = _libraries['llvm'].LLVMGetModuleContext - LLVMGetModuleContext.restype = LLVMContextRef - LLVMGetModuleContext.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetTypeByName = _libraries['llvm'].LLVMGetTypeByName - LLVMGetTypeByName.restype = LLVMTypeRef - LLVMGetTypeByName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstNamedMetadata = _libraries['llvm'].LLVMGetFirstNamedMetadata - LLVMGetFirstNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetFirstNamedMetadata.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastNamedMetadata = _libraries['llvm'].LLVMGetLastNamedMetadata - LLVMGetLastNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetLastNamedMetadata.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextNamedMetadata = _libraries['llvm'].LLVMGetNextNamedMetadata - LLVMGetNextNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetNextNamedMetadata.argtypes = [LLVMNamedMDNodeRef] -except AttributeError: - pass -try: - LLVMGetPreviousNamedMetadata = _libraries['llvm'].LLVMGetPreviousNamedMetadata - LLVMGetPreviousNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetPreviousNamedMetadata.argtypes = [LLVMNamedMDNodeRef] -except AttributeError: - pass -try: - LLVMGetNamedMetadata = _libraries['llvm'].LLVMGetNamedMetadata - LLVMGetNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetNamedMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetOrInsertNamedMetadata = _libraries['llvm'].LLVMGetOrInsertNamedMetadata - LLVMGetOrInsertNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetOrInsertNamedMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetNamedMetadataName = _libraries['llvm'].LLVMGetNamedMetadataName - LLVMGetNamedMetadataName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetNamedMetadataName.argtypes = [LLVMNamedMDNodeRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMGetNamedMetadataNumOperands = _libraries['llvm'].LLVMGetNamedMetadataNumOperands - LLVMGetNamedMetadataNumOperands.restype = ctypes.c_uint32 - LLVMGetNamedMetadataNumOperands.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetNamedMetadataOperands = _libraries['llvm'].LLVMGetNamedMetadataOperands - LLVMGetNamedMetadataOperands.restype = None - LLVMGetNamedMetadataOperands.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMAddNamedMetadataOperand = _libraries['llvm'].LLVMAddNamedMetadataOperand - LLVMAddNamedMetadataOperand.restype = None - LLVMAddNamedMetadataOperand.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetDebugLocDirectory = _libraries['llvm'].LLVMGetDebugLocDirectory - LLVMGetDebugLocDirectory.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDebugLocDirectory.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetDebugLocFilename = _libraries['llvm'].LLVMGetDebugLocFilename - LLVMGetDebugLocFilename.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDebugLocFilename.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetDebugLocLine = _libraries['llvm'].LLVMGetDebugLocLine - LLVMGetDebugLocLine.restype = ctypes.c_uint32 - LLVMGetDebugLocLine.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetDebugLocColumn = _libraries['llvm'].LLVMGetDebugLocColumn - LLVMGetDebugLocColumn.restype = ctypes.c_uint32 - LLVMGetDebugLocColumn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddFunction = _libraries['llvm'].LLVMAddFunction - LLVMAddFunction.restype = LLVMValueRef - LLVMAddFunction.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetNamedFunction = _libraries['llvm'].LLVMGetNamedFunction - LLVMGetNamedFunction.restype = LLVMValueRef - LLVMGetNamedFunction.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstFunction = _libraries['llvm'].LLVMGetFirstFunction - LLVMGetFirstFunction.restype = LLVMValueRef - LLVMGetFirstFunction.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastFunction = _libraries['llvm'].LLVMGetLastFunction - LLVMGetLastFunction.restype = LLVMValueRef - LLVMGetLastFunction.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextFunction = _libraries['llvm'].LLVMGetNextFunction - LLVMGetNextFunction.restype = LLVMValueRef - LLVMGetNextFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousFunction = _libraries['llvm'].LLVMGetPreviousFunction - LLVMGetPreviousFunction.restype = LLVMValueRef - LLVMGetPreviousFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetModuleInlineAsm = _libraries['llvm'].LLVMSetModuleInlineAsm - LLVMSetModuleInlineAsm.restype = None - LLVMSetModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTypeKind = _libraries['llvm'].LLVMGetTypeKind - LLVMGetTypeKind.restype = LLVMTypeKind - LLVMGetTypeKind.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMTypeIsSized = _libraries['llvm'].LLVMTypeIsSized - LLVMTypeIsSized.restype = LLVMBool - LLVMTypeIsSized.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetTypeContext = _libraries['llvm'].LLVMGetTypeContext - LLVMGetTypeContext.restype = LLVMContextRef - LLVMGetTypeContext.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMDumpType = _libraries['llvm'].LLVMDumpType - LLVMDumpType.restype = None - LLVMDumpType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPrintTypeToString = _libraries['llvm'].LLVMPrintTypeToString - LLVMPrintTypeToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintTypeToString.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMInt1TypeInContext = _libraries['llvm'].LLVMInt1TypeInContext - LLVMInt1TypeInContext.restype = LLVMTypeRef - LLVMInt1TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt8TypeInContext = _libraries['llvm'].LLVMInt8TypeInContext - LLVMInt8TypeInContext.restype = LLVMTypeRef - LLVMInt8TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt16TypeInContext = _libraries['llvm'].LLVMInt16TypeInContext - LLVMInt16TypeInContext.restype = LLVMTypeRef - LLVMInt16TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt32TypeInContext = _libraries['llvm'].LLVMInt32TypeInContext - LLVMInt32TypeInContext.restype = LLVMTypeRef - LLVMInt32TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt64TypeInContext = _libraries['llvm'].LLVMInt64TypeInContext - LLVMInt64TypeInContext.restype = LLVMTypeRef - LLVMInt64TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt128TypeInContext = _libraries['llvm'].LLVMInt128TypeInContext - LLVMInt128TypeInContext.restype = LLVMTypeRef - LLVMInt128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMIntTypeInContext = _libraries['llvm'].LLVMIntTypeInContext - LLVMIntTypeInContext.restype = LLVMTypeRef - LLVMIntTypeInContext.argtypes = [LLVMContextRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMInt1Type = _libraries['llvm'].LLVMInt1Type - LLVMInt1Type.restype = LLVMTypeRef - LLVMInt1Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt8Type = _libraries['llvm'].LLVMInt8Type - LLVMInt8Type.restype = LLVMTypeRef - LLVMInt8Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt16Type = _libraries['llvm'].LLVMInt16Type - LLVMInt16Type.restype = LLVMTypeRef - LLVMInt16Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt32Type = _libraries['llvm'].LLVMInt32Type - LLVMInt32Type.restype = LLVMTypeRef - LLVMInt32Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt64Type = _libraries['llvm'].LLVMInt64Type - LLVMInt64Type.restype = LLVMTypeRef - LLVMInt64Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt128Type = _libraries['llvm'].LLVMInt128Type - LLVMInt128Type.restype = LLVMTypeRef - LLVMInt128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMIntType = _libraries['llvm'].LLVMIntType - LLVMIntType.restype = LLVMTypeRef - LLVMIntType.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetIntTypeWidth = _libraries['llvm'].LLVMGetIntTypeWidth - LLVMGetIntTypeWidth.restype = ctypes.c_uint32 - LLVMGetIntTypeWidth.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMHalfTypeInContext = _libraries['llvm'].LLVMHalfTypeInContext - LLVMHalfTypeInContext.restype = LLVMTypeRef - LLVMHalfTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMBFloatTypeInContext = _libraries['llvm'].LLVMBFloatTypeInContext - LLVMBFloatTypeInContext.restype = LLVMTypeRef - LLVMBFloatTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMFloatTypeInContext = _libraries['llvm'].LLVMFloatTypeInContext - LLVMFloatTypeInContext.restype = LLVMTypeRef - LLVMFloatTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMDoubleTypeInContext = _libraries['llvm'].LLVMDoubleTypeInContext - LLVMDoubleTypeInContext.restype = LLVMTypeRef - LLVMDoubleTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86FP80TypeInContext = _libraries['llvm'].LLVMX86FP80TypeInContext - LLVMX86FP80TypeInContext.restype = LLVMTypeRef - LLVMX86FP80TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMFP128TypeInContext = _libraries['llvm'].LLVMFP128TypeInContext - LLVMFP128TypeInContext.restype = LLVMTypeRef - LLVMFP128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMPPCFP128TypeInContext = _libraries['llvm'].LLVMPPCFP128TypeInContext - LLVMPPCFP128TypeInContext.restype = LLVMTypeRef - LLVMPPCFP128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMHalfType = _libraries['llvm'].LLVMHalfType - LLVMHalfType.restype = LLVMTypeRef - LLVMHalfType.argtypes = [] -except AttributeError: - pass -try: - LLVMBFloatType = _libraries['llvm'].LLVMBFloatType - LLVMBFloatType.restype = LLVMTypeRef - LLVMBFloatType.argtypes = [] -except AttributeError: - pass -try: - LLVMFloatType = _libraries['llvm'].LLVMFloatType - LLVMFloatType.restype = LLVMTypeRef - LLVMFloatType.argtypes = [] -except AttributeError: - pass -try: - LLVMDoubleType = _libraries['llvm'].LLVMDoubleType - LLVMDoubleType.restype = LLVMTypeRef - LLVMDoubleType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86FP80Type = _libraries['llvm'].LLVMX86FP80Type - LLVMX86FP80Type.restype = LLVMTypeRef - LLVMX86FP80Type.argtypes = [] -except AttributeError: - pass -try: - LLVMFP128Type = _libraries['llvm'].LLVMFP128Type - LLVMFP128Type.restype = LLVMTypeRef - LLVMFP128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMPPCFP128Type = _libraries['llvm'].LLVMPPCFP128Type - LLVMPPCFP128Type.restype = LLVMTypeRef - LLVMPPCFP128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMFunctionType = _libraries['llvm'].LLVMFunctionType - LLVMFunctionType.restype = LLVMTypeRef - LLVMFunctionType.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMIsFunctionVarArg = _libraries['llvm'].LLVMIsFunctionVarArg - LLVMIsFunctionVarArg.restype = LLVMBool - LLVMIsFunctionVarArg.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetReturnType = _libraries['llvm'].LLVMGetReturnType - LLVMGetReturnType.restype = LLVMTypeRef - LLVMGetReturnType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMCountParamTypes = _libraries['llvm'].LLVMCountParamTypes - LLVMCountParamTypes.restype = ctypes.c_uint32 - LLVMCountParamTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetParamTypes = _libraries['llvm'].LLVMGetParamTypes - LLVMGetParamTypes.restype = None - LLVMGetParamTypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMStructTypeInContext = _libraries['llvm'].LLVMStructTypeInContext - LLVMStructTypeInContext.restype = LLVMTypeRef - LLVMStructTypeInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMStructType = _libraries['llvm'].LLVMStructType - LLVMStructType.restype = LLVMTypeRef - LLVMStructType.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMStructCreateNamed = _libraries['llvm'].LLVMStructCreateNamed - LLVMStructCreateNamed.restype = LLVMTypeRef - LLVMStructCreateNamed.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetStructName = _libraries['llvm'].LLVMGetStructName - LLVMGetStructName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStructName.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMStructSetBody = _libraries['llvm'].LLVMStructSetBody - LLVMStructSetBody.restype = None - LLVMStructSetBody.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMCountStructElementTypes = _libraries['llvm'].LLVMCountStructElementTypes - LLVMCountStructElementTypes.restype = ctypes.c_uint32 - LLVMCountStructElementTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetStructElementTypes = _libraries['llvm'].LLVMGetStructElementTypes - LLVMGetStructElementTypes.restype = None - LLVMGetStructElementTypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMStructGetTypeAtIndex = _libraries['llvm'].LLVMStructGetTypeAtIndex - LLVMStructGetTypeAtIndex.restype = LLVMTypeRef - LLVMStructGetTypeAtIndex.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIsPackedStruct = _libraries['llvm'].LLVMIsPackedStruct - LLVMIsPackedStruct.restype = LLVMBool - LLVMIsPackedStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsOpaqueStruct = _libraries['llvm'].LLVMIsOpaqueStruct - LLVMIsOpaqueStruct.restype = LLVMBool - LLVMIsOpaqueStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsLiteralStruct = _libraries['llvm'].LLVMIsLiteralStruct - LLVMIsLiteralStruct.restype = LLVMBool - LLVMIsLiteralStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetElementType = _libraries['llvm'].LLVMGetElementType - LLVMGetElementType.restype = LLVMTypeRef - LLVMGetElementType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetSubtypes = _libraries['llvm'].LLVMGetSubtypes - LLVMGetSubtypes.restype = None - LLVMGetSubtypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMGetNumContainedTypes = _libraries['llvm'].LLVMGetNumContainedTypes - LLVMGetNumContainedTypes.restype = ctypes.c_uint32 - LLVMGetNumContainedTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMArrayType = _libraries['llvm'].LLVMArrayType - LLVMArrayType.restype = LLVMTypeRef - LLVMArrayType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetArrayLength = _libraries['llvm'].LLVMGetArrayLength - LLVMGetArrayLength.restype = ctypes.c_uint32 - LLVMGetArrayLength.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPointerType = _libraries['llvm'].LLVMPointerType - LLVMPointerType.restype = LLVMTypeRef - LLVMPointerType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetPointerAddressSpace = _libraries['llvm'].LLVMGetPointerAddressSpace - LLVMGetPointerAddressSpace.restype = ctypes.c_uint32 - LLVMGetPointerAddressSpace.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMVectorType = _libraries['llvm'].LLVMVectorType - LLVMVectorType.restype = LLVMTypeRef - LLVMVectorType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMScalableVectorType = _libraries['llvm'].LLVMScalableVectorType - LLVMScalableVectorType.restype = LLVMTypeRef - LLVMScalableVectorType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetVectorSize = _libraries['llvm'].LLVMGetVectorSize - LLVMGetVectorSize.restype = ctypes.c_uint32 - LLVMGetVectorSize.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMVoidTypeInContext = _libraries['llvm'].LLVMVoidTypeInContext - LLVMVoidTypeInContext.restype = LLVMTypeRef - LLVMVoidTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMLabelTypeInContext = _libraries['llvm'].LLVMLabelTypeInContext - LLVMLabelTypeInContext.restype = LLVMTypeRef - LLVMLabelTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86MMXTypeInContext = _libraries['llvm'].LLVMX86MMXTypeInContext - LLVMX86MMXTypeInContext.restype = LLVMTypeRef - LLVMX86MMXTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86AMXTypeInContext = _libraries['llvm'].LLVMX86AMXTypeInContext - LLVMX86AMXTypeInContext.restype = LLVMTypeRef - LLVMX86AMXTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMTokenTypeInContext = _libraries['llvm'].LLVMTokenTypeInContext - LLVMTokenTypeInContext.restype = LLVMTypeRef - LLVMTokenTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMMetadataTypeInContext = _libraries['llvm'].LLVMMetadataTypeInContext - LLVMMetadataTypeInContext.restype = LLVMTypeRef - LLVMMetadataTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMVoidType = _libraries['llvm'].LLVMVoidType - LLVMVoidType.restype = LLVMTypeRef - LLVMVoidType.argtypes = [] -except AttributeError: - pass -try: - LLVMLabelType = _libraries['llvm'].LLVMLabelType - LLVMLabelType.restype = LLVMTypeRef - LLVMLabelType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86MMXType = _libraries['llvm'].LLVMX86MMXType - LLVMX86MMXType.restype = LLVMTypeRef - LLVMX86MMXType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86AMXType = _libraries['llvm'].LLVMX86AMXType - LLVMX86AMXType.restype = LLVMTypeRef - LLVMX86AMXType.argtypes = [] -except AttributeError: - pass -try: - LLVMTypeOf = _libraries['llvm'].LLVMTypeOf - LLVMTypeOf.restype = LLVMTypeRef - LLVMTypeOf.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueKind = _libraries['llvm'].LLVMGetValueKind - LLVMGetValueKind.restype = LLVMValueKind - LLVMGetValueKind.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueName2 = _libraries['llvm'].LLVMGetValueName2 - LLVMGetValueName2.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetValueName2.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetValueName2 = _libraries['llvm'].LLVMSetValueName2 - LLVMSetValueName2.restype = None - LLVMSetValueName2.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDumpValue = _libraries['llvm'].LLVMDumpValue - LLVMDumpValue.restype = None - LLVMDumpValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMPrintValueToString = _libraries['llvm'].LLVMPrintValueToString - LLVMPrintValueToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintValueToString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMReplaceAllUsesWith = _libraries['llvm'].LLVMReplaceAllUsesWith - LLVMReplaceAllUsesWith.restype = None - LLVMReplaceAllUsesWith.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsConstant = _libraries['llvm'].LLVMIsConstant - LLVMIsConstant.restype = LLVMBool - LLVMIsConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsUndef = _libraries['llvm'].LLVMIsUndef - LLVMIsUndef.restype = LLVMBool - LLVMIsUndef.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsPoison = _libraries['llvm'].LLVMIsPoison - LLVMIsPoison.restype = LLVMBool - LLVMIsPoison.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAArgument = _libraries['llvm'].LLVMIsAArgument - LLVMIsAArgument.restype = LLVMValueRef - LLVMIsAArgument.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABasicBlock = _libraries['llvm'].LLVMIsABasicBlock - LLVMIsABasicBlock.restype = LLVMValueRef - LLVMIsABasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInlineAsm = _libraries['llvm'].LLVMIsAInlineAsm - LLVMIsAInlineAsm.restype = LLVMValueRef - LLVMIsAInlineAsm.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUser = _libraries['llvm'].LLVMIsAUser - LLVMIsAUser.restype = LLVMValueRef - LLVMIsAUser.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstant = _libraries['llvm'].LLVMIsAConstant - LLVMIsAConstant.restype = LLVMValueRef - LLVMIsAConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABlockAddress = _libraries['llvm'].LLVMIsABlockAddress - LLVMIsABlockAddress.restype = LLVMValueRef - LLVMIsABlockAddress.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantAggregateZero = _libraries['llvm'].LLVMIsAConstantAggregateZero - LLVMIsAConstantAggregateZero.restype = LLVMValueRef - LLVMIsAConstantAggregateZero.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantArray = _libraries['llvm'].LLVMIsAConstantArray - LLVMIsAConstantArray.restype = LLVMValueRef - LLVMIsAConstantArray.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataSequential = _libraries['llvm'].LLVMIsAConstantDataSequential - LLVMIsAConstantDataSequential.restype = LLVMValueRef - LLVMIsAConstantDataSequential.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataArray = _libraries['llvm'].LLVMIsAConstantDataArray - LLVMIsAConstantDataArray.restype = LLVMValueRef - LLVMIsAConstantDataArray.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataVector = _libraries['llvm'].LLVMIsAConstantDataVector - LLVMIsAConstantDataVector.restype = LLVMValueRef - LLVMIsAConstantDataVector.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantExpr = _libraries['llvm'].LLVMIsAConstantExpr - LLVMIsAConstantExpr.restype = LLVMValueRef - LLVMIsAConstantExpr.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantFP = _libraries['llvm'].LLVMIsAConstantFP - LLVMIsAConstantFP.restype = LLVMValueRef - LLVMIsAConstantFP.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantInt = _libraries['llvm'].LLVMIsAConstantInt - LLVMIsAConstantInt.restype = LLVMValueRef - LLVMIsAConstantInt.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantPointerNull = _libraries['llvm'].LLVMIsAConstantPointerNull - LLVMIsAConstantPointerNull.restype = LLVMValueRef - LLVMIsAConstantPointerNull.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantStruct = _libraries['llvm'].LLVMIsAConstantStruct - LLVMIsAConstantStruct.restype = LLVMValueRef - LLVMIsAConstantStruct.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantTokenNone = _libraries['llvm'].LLVMIsAConstantTokenNone - LLVMIsAConstantTokenNone.restype = LLVMValueRef - LLVMIsAConstantTokenNone.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantVector = _libraries['llvm'].LLVMIsAConstantVector - LLVMIsAConstantVector.restype = LLVMValueRef - LLVMIsAConstantVector.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalValue = _libraries['llvm'].LLVMIsAGlobalValue - LLVMIsAGlobalValue.restype = LLVMValueRef - LLVMIsAGlobalValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalAlias = _libraries['llvm'].LLVMIsAGlobalAlias - LLVMIsAGlobalAlias.restype = LLVMValueRef - LLVMIsAGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalObject = _libraries['llvm'].LLVMIsAGlobalObject - LLVMIsAGlobalObject.restype = LLVMValueRef - LLVMIsAGlobalObject.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFunction = _libraries['llvm'].LLVMIsAFunction - LLVMIsAFunction.restype = LLVMValueRef - LLVMIsAFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalVariable = _libraries['llvm'].LLVMIsAGlobalVariable - LLVMIsAGlobalVariable.restype = LLVMValueRef - LLVMIsAGlobalVariable.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalIFunc = _libraries['llvm'].LLVMIsAGlobalIFunc - LLVMIsAGlobalIFunc.restype = LLVMValueRef - LLVMIsAGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUndefValue = _libraries['llvm'].LLVMIsAUndefValue - LLVMIsAUndefValue.restype = LLVMValueRef - LLVMIsAUndefValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPoisonValue = _libraries['llvm'].LLVMIsAPoisonValue - LLVMIsAPoisonValue.restype = LLVMValueRef - LLVMIsAPoisonValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInstruction = _libraries['llvm'].LLVMIsAInstruction - LLVMIsAInstruction.restype = LLVMValueRef - LLVMIsAInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnaryOperator = _libraries['llvm'].LLVMIsAUnaryOperator - LLVMIsAUnaryOperator.restype = LLVMValueRef - LLVMIsAUnaryOperator.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABinaryOperator = _libraries['llvm'].LLVMIsABinaryOperator - LLVMIsABinaryOperator.restype = LLVMValueRef - LLVMIsABinaryOperator.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACallInst = _libraries['llvm'].LLVMIsACallInst - LLVMIsACallInst.restype = LLVMValueRef - LLVMIsACallInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIntrinsicInst = _libraries['llvm'].LLVMIsAIntrinsicInst - LLVMIsAIntrinsicInst.restype = LLVMValueRef - LLVMIsAIntrinsicInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgInfoIntrinsic = _libraries['llvm'].LLVMIsADbgInfoIntrinsic - LLVMIsADbgInfoIntrinsic.restype = LLVMValueRef - LLVMIsADbgInfoIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgVariableIntrinsic = _libraries['llvm'].LLVMIsADbgVariableIntrinsic - LLVMIsADbgVariableIntrinsic.restype = LLVMValueRef - LLVMIsADbgVariableIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgDeclareInst = _libraries['llvm'].LLVMIsADbgDeclareInst - LLVMIsADbgDeclareInst.restype = LLVMValueRef - LLVMIsADbgDeclareInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgLabelInst = _libraries['llvm'].LLVMIsADbgLabelInst - LLVMIsADbgLabelInst.restype = LLVMValueRef - LLVMIsADbgLabelInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemIntrinsic = _libraries['llvm'].LLVMIsAMemIntrinsic - LLVMIsAMemIntrinsic.restype = LLVMValueRef - LLVMIsAMemIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemCpyInst = _libraries['llvm'].LLVMIsAMemCpyInst - LLVMIsAMemCpyInst.restype = LLVMValueRef - LLVMIsAMemCpyInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemMoveInst = _libraries['llvm'].LLVMIsAMemMoveInst - LLVMIsAMemMoveInst.restype = LLVMValueRef - LLVMIsAMemMoveInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemSetInst = _libraries['llvm'].LLVMIsAMemSetInst - LLVMIsAMemSetInst.restype = LLVMValueRef - LLVMIsAMemSetInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACmpInst = _libraries['llvm'].LLVMIsACmpInst - LLVMIsACmpInst.restype = LLVMValueRef - LLVMIsACmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFCmpInst = _libraries['llvm'].LLVMIsAFCmpInst - LLVMIsAFCmpInst.restype = LLVMValueRef - LLVMIsAFCmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAICmpInst = _libraries['llvm'].LLVMIsAICmpInst - LLVMIsAICmpInst.restype = LLVMValueRef - LLVMIsAICmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAExtractElementInst = _libraries['llvm'].LLVMIsAExtractElementInst - LLVMIsAExtractElementInst.restype = LLVMValueRef - LLVMIsAExtractElementInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGetElementPtrInst = _libraries['llvm'].LLVMIsAGetElementPtrInst - LLVMIsAGetElementPtrInst.restype = LLVMValueRef - LLVMIsAGetElementPtrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInsertElementInst = _libraries['llvm'].LLVMIsAInsertElementInst - LLVMIsAInsertElementInst.restype = LLVMValueRef - LLVMIsAInsertElementInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInsertValueInst = _libraries['llvm'].LLVMIsAInsertValueInst - LLVMIsAInsertValueInst.restype = LLVMValueRef - LLVMIsAInsertValueInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsALandingPadInst = _libraries['llvm'].LLVMIsALandingPadInst - LLVMIsALandingPadInst.restype = LLVMValueRef - LLVMIsALandingPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPHINode = _libraries['llvm'].LLVMIsAPHINode - LLVMIsAPHINode.restype = LLVMValueRef - LLVMIsAPHINode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASelectInst = _libraries['llvm'].LLVMIsASelectInst - LLVMIsASelectInst.restype = LLVMValueRef - LLVMIsASelectInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAShuffleVectorInst = _libraries['llvm'].LLVMIsAShuffleVectorInst - LLVMIsAShuffleVectorInst.restype = LLVMValueRef - LLVMIsAShuffleVectorInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAStoreInst = _libraries['llvm'].LLVMIsAStoreInst - LLVMIsAStoreInst.restype = LLVMValueRef - LLVMIsAStoreInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABranchInst = _libraries['llvm'].LLVMIsABranchInst - LLVMIsABranchInst.restype = LLVMValueRef - LLVMIsABranchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIndirectBrInst = _libraries['llvm'].LLVMIsAIndirectBrInst - LLVMIsAIndirectBrInst.restype = LLVMValueRef - LLVMIsAIndirectBrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInvokeInst = _libraries['llvm'].LLVMIsAInvokeInst - LLVMIsAInvokeInst.restype = LLVMValueRef - LLVMIsAInvokeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAReturnInst = _libraries['llvm'].LLVMIsAReturnInst - LLVMIsAReturnInst.restype = LLVMValueRef - LLVMIsAReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASwitchInst = _libraries['llvm'].LLVMIsASwitchInst - LLVMIsASwitchInst.restype = LLVMValueRef - LLVMIsASwitchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnreachableInst = _libraries['llvm'].LLVMIsAUnreachableInst - LLVMIsAUnreachableInst.restype = LLVMValueRef - LLVMIsAUnreachableInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAResumeInst = _libraries['llvm'].LLVMIsAResumeInst - LLVMIsAResumeInst.restype = LLVMValueRef - LLVMIsAResumeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACleanupReturnInst = _libraries['llvm'].LLVMIsACleanupReturnInst - LLVMIsACleanupReturnInst.restype = LLVMValueRef - LLVMIsACleanupReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchReturnInst = _libraries['llvm'].LLVMIsACatchReturnInst - LLVMIsACatchReturnInst.restype = LLVMValueRef - LLVMIsACatchReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchSwitchInst = _libraries['llvm'].LLVMIsACatchSwitchInst - LLVMIsACatchSwitchInst.restype = LLVMValueRef - LLVMIsACatchSwitchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACallBrInst = _libraries['llvm'].LLVMIsACallBrInst - LLVMIsACallBrInst.restype = LLVMValueRef - LLVMIsACallBrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFuncletPadInst = _libraries['llvm'].LLVMIsAFuncletPadInst - LLVMIsAFuncletPadInst.restype = LLVMValueRef - LLVMIsAFuncletPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchPadInst = _libraries['llvm'].LLVMIsACatchPadInst - LLVMIsACatchPadInst.restype = LLVMValueRef - LLVMIsACatchPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACleanupPadInst = _libraries['llvm'].LLVMIsACleanupPadInst - LLVMIsACleanupPadInst.restype = LLVMValueRef - LLVMIsACleanupPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnaryInstruction = _libraries['llvm'].LLVMIsAUnaryInstruction - LLVMIsAUnaryInstruction.restype = LLVMValueRef - LLVMIsAUnaryInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAllocaInst = _libraries['llvm'].LLVMIsAAllocaInst - LLVMIsAAllocaInst.restype = LLVMValueRef - LLVMIsAAllocaInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACastInst = _libraries['llvm'].LLVMIsACastInst - LLVMIsACastInst.restype = LLVMValueRef - LLVMIsACastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAddrSpaceCastInst = _libraries['llvm'].LLVMIsAAddrSpaceCastInst - LLVMIsAAddrSpaceCastInst.restype = LLVMValueRef - LLVMIsAAddrSpaceCastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABitCastInst = _libraries['llvm'].LLVMIsABitCastInst - LLVMIsABitCastInst.restype = LLVMValueRef - LLVMIsABitCastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPExtInst = _libraries['llvm'].LLVMIsAFPExtInst - LLVMIsAFPExtInst.restype = LLVMValueRef - LLVMIsAFPExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPToSIInst = _libraries['llvm'].LLVMIsAFPToSIInst - LLVMIsAFPToSIInst.restype = LLVMValueRef - LLVMIsAFPToSIInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPToUIInst = _libraries['llvm'].LLVMIsAFPToUIInst - LLVMIsAFPToUIInst.restype = LLVMValueRef - LLVMIsAFPToUIInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPTruncInst = _libraries['llvm'].LLVMIsAFPTruncInst - LLVMIsAFPTruncInst.restype = LLVMValueRef - LLVMIsAFPTruncInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIntToPtrInst = _libraries['llvm'].LLVMIsAIntToPtrInst - LLVMIsAIntToPtrInst.restype = LLVMValueRef - LLVMIsAIntToPtrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPtrToIntInst = _libraries['llvm'].LLVMIsAPtrToIntInst - LLVMIsAPtrToIntInst.restype = LLVMValueRef - LLVMIsAPtrToIntInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASExtInst = _libraries['llvm'].LLVMIsASExtInst - LLVMIsASExtInst.restype = LLVMValueRef - LLVMIsASExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASIToFPInst = _libraries['llvm'].LLVMIsASIToFPInst - LLVMIsASIToFPInst.restype = LLVMValueRef - LLVMIsASIToFPInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsATruncInst = _libraries['llvm'].LLVMIsATruncInst - LLVMIsATruncInst.restype = LLVMValueRef - LLVMIsATruncInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUIToFPInst = _libraries['llvm'].LLVMIsAUIToFPInst - LLVMIsAUIToFPInst.restype = LLVMValueRef - LLVMIsAUIToFPInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAZExtInst = _libraries['llvm'].LLVMIsAZExtInst - LLVMIsAZExtInst.restype = LLVMValueRef - LLVMIsAZExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAExtractValueInst = _libraries['llvm'].LLVMIsAExtractValueInst - LLVMIsAExtractValueInst.restype = LLVMValueRef - LLVMIsAExtractValueInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsALoadInst = _libraries['llvm'].LLVMIsALoadInst - LLVMIsALoadInst.restype = LLVMValueRef - LLVMIsALoadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAVAArgInst = _libraries['llvm'].LLVMIsAVAArgInst - LLVMIsAVAArgInst.restype = LLVMValueRef - LLVMIsAVAArgInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFreezeInst = _libraries['llvm'].LLVMIsAFreezeInst - LLVMIsAFreezeInst.restype = LLVMValueRef - LLVMIsAFreezeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAtomicCmpXchgInst = _libraries['llvm'].LLVMIsAAtomicCmpXchgInst - LLVMIsAAtomicCmpXchgInst.restype = LLVMValueRef - LLVMIsAAtomicCmpXchgInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAtomicRMWInst = _libraries['llvm'].LLVMIsAAtomicRMWInst - LLVMIsAAtomicRMWInst.restype = LLVMValueRef - LLVMIsAAtomicRMWInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFenceInst = _libraries['llvm'].LLVMIsAFenceInst - LLVMIsAFenceInst.restype = LLVMValueRef - LLVMIsAFenceInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMDNode = _libraries['llvm'].LLVMIsAMDNode - LLVMIsAMDNode.restype = LLVMValueRef - LLVMIsAMDNode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMDString = _libraries['llvm'].LLVMIsAMDString - LLVMIsAMDString.restype = LLVMValueRef - LLVMIsAMDString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueName = _libraries['llvm'].LLVMGetValueName - LLVMGetValueName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetValueName.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetValueName = _libraries['llvm'].LLVMSetValueName - LLVMSetValueName.restype = None - LLVMSetValueName.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstUse = _libraries['llvm'].LLVMGetFirstUse - LLVMGetFirstUse.restype = LLVMUseRef - LLVMGetFirstUse.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextUse = _libraries['llvm'].LLVMGetNextUse - LLVMGetNextUse.restype = LLVMUseRef - LLVMGetNextUse.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetUser = _libraries['llvm'].LLVMGetUser - LLVMGetUser.restype = LLVMValueRef - LLVMGetUser.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetUsedValue = _libraries['llvm'].LLVMGetUsedValue - LLVMGetUsedValue.restype = LLVMValueRef - LLVMGetUsedValue.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetOperand = _libraries['llvm'].LLVMGetOperand - LLVMGetOperand.restype = LLVMValueRef - LLVMGetOperand.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetOperandUse = _libraries['llvm'].LLVMGetOperandUse - LLVMGetOperandUse.restype = LLVMUseRef - LLVMGetOperandUse.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetOperand = _libraries['llvm'].LLVMSetOperand - LLVMSetOperand.restype = None - LLVMSetOperand.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNumOperands = _libraries['llvm'].LLVMGetNumOperands - LLVMGetNumOperands.restype = ctypes.c_int32 - LLVMGetNumOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNull = _libraries['llvm'].LLVMConstNull - LLVMConstNull.restype = LLVMValueRef - LLVMConstNull.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstAllOnes = _libraries['llvm'].LLVMConstAllOnes - LLVMConstAllOnes.restype = LLVMValueRef - LLVMConstAllOnes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetUndef = _libraries['llvm'].LLVMGetUndef - LLVMGetUndef.restype = LLVMValueRef - LLVMGetUndef.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetPoison = _libraries['llvm'].LLVMGetPoison - LLVMGetPoison.restype = LLVMValueRef - LLVMGetPoison.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsNull = _libraries['llvm'].LLVMIsNull - LLVMIsNull.restype = LLVMBool - LLVMIsNull.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstPointerNull = _libraries['llvm'].LLVMConstPointerNull - LLVMConstPointerNull.restype = LLVMValueRef - LLVMConstPointerNull.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstInt = _libraries['llvm'].LLVMConstInt - LLVMConstInt.restype = LLVMValueRef - LLVMConstInt.argtypes = [LLVMTypeRef, ctypes.c_uint64, LLVMBool] -except AttributeError: - pass -try: - LLVMConstIntOfArbitraryPrecision = _libraries['llvm'].LLVMConstIntOfArbitraryPrecision - LLVMConstIntOfArbitraryPrecision.restype = LLVMValueRef - LLVMConstIntOfArbitraryPrecision.argtypes = [LLVMTypeRef, ctypes.c_uint32, ctypes.c_uint64 * 0] -except AttributeError: - pass -uint8_t = ctypes.c_uint8 -try: - LLVMConstIntOfString = _libraries['llvm'].LLVMConstIntOfString - LLVMConstIntOfString.restype = LLVMValueRef - LLVMConstIntOfString.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), uint8_t] -except AttributeError: - pass -try: - LLVMConstIntOfStringAndSize = _libraries['llvm'].LLVMConstIntOfStringAndSize - LLVMConstIntOfStringAndSize.restype = LLVMValueRef - LLVMConstIntOfStringAndSize.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, uint8_t] -except AttributeError: - pass -try: - LLVMConstReal = _libraries['llvm'].LLVMConstReal - LLVMConstReal.restype = LLVMValueRef - LLVMConstReal.argtypes = [LLVMTypeRef, ctypes.c_double] -except AttributeError: - pass -try: - LLVMConstRealOfString = _libraries['llvm'].LLVMConstRealOfString - LLVMConstRealOfString.restype = LLVMValueRef - LLVMConstRealOfString.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMConstRealOfStringAndSize = _libraries['llvm'].LLVMConstRealOfStringAndSize - LLVMConstRealOfStringAndSize.restype = LLVMValueRef - LLVMConstRealOfStringAndSize.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstIntGetZExtValue = _libraries['llvm'].LLVMConstIntGetZExtValue - LLVMConstIntGetZExtValue.restype = ctypes.c_uint64 - LLVMConstIntGetZExtValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstIntGetSExtValue = _libraries['llvm'].LLVMConstIntGetSExtValue - LLVMConstIntGetSExtValue.restype = ctypes.c_int64 - LLVMConstIntGetSExtValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstRealGetDouble = _libraries['llvm'].LLVMConstRealGetDouble - LLVMConstRealGetDouble.restype = ctypes.c_double - LLVMConstRealGetDouble.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - LLVMConstStringInContext = _libraries['llvm'].LLVMConstStringInContext - LLVMConstStringInContext.restype = LLVMValueRef - LLVMConstStringInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstString = _libraries['llvm'].LLVMConstString - LLVMConstString.restype = LLVMValueRef - LLVMConstString.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMIsConstantString = _libraries['llvm'].LLVMIsConstantString - LLVMIsConstantString.restype = LLVMBool - LLVMIsConstantString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetAsString = _libraries['llvm'].LLVMGetAsString - LLVMGetAsString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetAsString.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMConstStructInContext = _libraries['llvm'].LLVMConstStructInContext - LLVMConstStructInContext.restype = LLVMValueRef - LLVMConstStructInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstStruct = _libraries['llvm'].LLVMConstStruct - LLVMConstStruct.restype = LLVMValueRef - LLVMConstStruct.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstArray = _libraries['llvm'].LLVMConstArray - LLVMConstArray.restype = LLVMValueRef - LLVMConstArray.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstNamedStruct = _libraries['llvm'].LLVMConstNamedStruct - LLVMConstNamedStruct.restype = LLVMValueRef - LLVMConstNamedStruct.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetElementAsConstant = _libraries['llvm'].LLVMGetElementAsConstant - LLVMGetElementAsConstant.restype = LLVMValueRef - LLVMGetElementAsConstant.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstVector = _libraries['llvm'].LLVMConstVector - LLVMConstVector.restype = LLVMValueRef - LLVMConstVector.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetConstOpcode = _libraries['llvm'].LLVMGetConstOpcode - LLVMGetConstOpcode.restype = LLVMOpcode - LLVMGetConstOpcode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAlignOf = _libraries['llvm'].LLVMAlignOf - LLVMAlignOf.restype = LLVMValueRef - LLVMAlignOf.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMSizeOf = _libraries['llvm'].LLVMSizeOf - LLVMSizeOf.restype = LLVMValueRef - LLVMSizeOf.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstNeg = _libraries['llvm'].LLVMConstNeg - LLVMConstNeg.restype = LLVMValueRef - LLVMConstNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWNeg = _libraries['llvm'].LLVMConstNSWNeg - LLVMConstNSWNeg.restype = LLVMValueRef - LLVMConstNSWNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWNeg = _libraries['llvm'].LLVMConstNUWNeg - LLVMConstNUWNeg.restype = LLVMValueRef - LLVMConstNUWNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFNeg = _libraries['llvm'].LLVMConstFNeg - LLVMConstFNeg.restype = LLVMValueRef - LLVMConstFNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNot = _libraries['llvm'].LLVMConstNot - LLVMConstNot.restype = LLVMValueRef - LLVMConstNot.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAdd = _libraries['llvm'].LLVMConstAdd - LLVMConstAdd.restype = LLVMValueRef - LLVMConstAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWAdd = _libraries['llvm'].LLVMConstNSWAdd - LLVMConstNSWAdd.restype = LLVMValueRef - LLVMConstNSWAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWAdd = _libraries['llvm'].LLVMConstNUWAdd - LLVMConstNUWAdd.restype = LLVMValueRef - LLVMConstNUWAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFAdd = _libraries['llvm'].LLVMConstFAdd - LLVMConstFAdd.restype = LLVMValueRef - LLVMConstFAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSub = _libraries['llvm'].LLVMConstSub - LLVMConstSub.restype = LLVMValueRef - LLVMConstSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWSub = _libraries['llvm'].LLVMConstNSWSub - LLVMConstNSWSub.restype = LLVMValueRef - LLVMConstNSWSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWSub = _libraries['llvm'].LLVMConstNUWSub - LLVMConstNUWSub.restype = LLVMValueRef - LLVMConstNUWSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFSub = _libraries['llvm'].LLVMConstFSub - LLVMConstFSub.restype = LLVMValueRef - LLVMConstFSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstMul = _libraries['llvm'].LLVMConstMul - LLVMConstMul.restype = LLVMValueRef - LLVMConstMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWMul = _libraries['llvm'].LLVMConstNSWMul - LLVMConstNSWMul.restype = LLVMValueRef - LLVMConstNSWMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWMul = _libraries['llvm'].LLVMConstNUWMul - LLVMConstNUWMul.restype = LLVMValueRef - LLVMConstNUWMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFMul = _libraries['llvm'].LLVMConstFMul - LLVMConstFMul.restype = LLVMValueRef - LLVMConstFMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstUDiv = _libraries['llvm'].LLVMConstUDiv - LLVMConstUDiv.restype = LLVMValueRef - LLVMConstUDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExactUDiv = _libraries['llvm'].LLVMConstExactUDiv - LLVMConstExactUDiv.restype = LLVMValueRef - LLVMConstExactUDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSDiv = _libraries['llvm'].LLVMConstSDiv - LLVMConstSDiv.restype = LLVMValueRef - LLVMConstSDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExactSDiv = _libraries['llvm'].LLVMConstExactSDiv - LLVMConstExactSDiv.restype = LLVMValueRef - LLVMConstExactSDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFDiv = _libraries['llvm'].LLVMConstFDiv - LLVMConstFDiv.restype = LLVMValueRef - LLVMConstFDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstURem = _libraries['llvm'].LLVMConstURem - LLVMConstURem.restype = LLVMValueRef - LLVMConstURem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSRem = _libraries['llvm'].LLVMConstSRem - LLVMConstSRem.restype = LLVMValueRef - LLVMConstSRem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFRem = _libraries['llvm'].LLVMConstFRem - LLVMConstFRem.restype = LLVMValueRef - LLVMConstFRem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAnd = _libraries['llvm'].LLVMConstAnd - LLVMConstAnd.restype = LLVMValueRef - LLVMConstAnd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstOr = _libraries['llvm'].LLVMConstOr - LLVMConstOr.restype = LLVMValueRef - LLVMConstOr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstXor = _libraries['llvm'].LLVMConstXor - LLVMConstXor.restype = LLVMValueRef - LLVMConstXor.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstICmp = _libraries['llvm'].LLVMConstICmp - LLVMConstICmp.restype = LLVMValueRef - LLVMConstICmp.argtypes = [LLVMIntPredicate, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFCmp = _libraries['llvm'].LLVMConstFCmp - LLVMConstFCmp.restype = LLVMValueRef - LLVMConstFCmp.argtypes = [LLVMRealPredicate, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstShl = _libraries['llvm'].LLVMConstShl - LLVMConstShl.restype = LLVMValueRef - LLVMConstShl.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstLShr = _libraries['llvm'].LLVMConstLShr - LLVMConstLShr.restype = LLVMValueRef - LLVMConstLShr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAShr = _libraries['llvm'].LLVMConstAShr - LLVMConstAShr.restype = LLVMValueRef - LLVMConstAShr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstGEP = _libraries['llvm'].LLVMConstGEP - LLVMConstGEP.restype = LLVMValueRef - LLVMConstGEP.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstGEP2 = _libraries['llvm'].LLVMConstGEP2 - LLVMConstGEP2.restype = LLVMValueRef - LLVMConstGEP2.argtypes = [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInBoundsGEP = _libraries['llvm'].LLVMConstInBoundsGEP - LLVMConstInBoundsGEP.restype = LLVMValueRef - LLVMConstInBoundsGEP.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInBoundsGEP2 = _libraries['llvm'].LLVMConstInBoundsGEP2 - LLVMConstInBoundsGEP2.restype = LLVMValueRef - LLVMConstInBoundsGEP2.argtypes = [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstTrunc = _libraries['llvm'].LLVMConstTrunc - LLVMConstTrunc.restype = LLVMValueRef - LLVMConstTrunc.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSExt = _libraries['llvm'].LLVMConstSExt - LLVMConstSExt.restype = LLVMValueRef - LLVMConstSExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstZExt = _libraries['llvm'].LLVMConstZExt - LLVMConstZExt.restype = LLVMValueRef - LLVMConstZExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPTrunc = _libraries['llvm'].LLVMConstFPTrunc - LLVMConstFPTrunc.restype = LLVMValueRef - LLVMConstFPTrunc.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPExt = _libraries['llvm'].LLVMConstFPExt - LLVMConstFPExt.restype = LLVMValueRef - LLVMConstFPExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstUIToFP = _libraries['llvm'].LLVMConstUIToFP - LLVMConstUIToFP.restype = LLVMValueRef - LLVMConstUIToFP.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSIToFP = _libraries['llvm'].LLVMConstSIToFP - LLVMConstSIToFP.restype = LLVMValueRef - LLVMConstSIToFP.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPToUI = _libraries['llvm'].LLVMConstFPToUI - LLVMConstFPToUI.restype = LLVMValueRef - LLVMConstFPToUI.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPToSI = _libraries['llvm'].LLVMConstFPToSI - LLVMConstFPToSI.restype = LLVMValueRef - LLVMConstFPToSI.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstPtrToInt = _libraries['llvm'].LLVMConstPtrToInt - LLVMConstPtrToInt.restype = LLVMValueRef - LLVMConstPtrToInt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstIntToPtr = _libraries['llvm'].LLVMConstIntToPtr - LLVMConstIntToPtr.restype = LLVMValueRef - LLVMConstIntToPtr.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstBitCast = _libraries['llvm'].LLVMConstBitCast - LLVMConstBitCast.restype = LLVMValueRef - LLVMConstBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstAddrSpaceCast = _libraries['llvm'].LLVMConstAddrSpaceCast - LLVMConstAddrSpaceCast.restype = LLVMValueRef - LLVMConstAddrSpaceCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstZExtOrBitCast = _libraries['llvm'].LLVMConstZExtOrBitCast - LLVMConstZExtOrBitCast.restype = LLVMValueRef - LLVMConstZExtOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSExtOrBitCast = _libraries['llvm'].LLVMConstSExtOrBitCast - LLVMConstSExtOrBitCast.restype = LLVMValueRef - LLVMConstSExtOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstTruncOrBitCast = _libraries['llvm'].LLVMConstTruncOrBitCast - LLVMConstTruncOrBitCast.restype = LLVMValueRef - LLVMConstTruncOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstPointerCast = _libraries['llvm'].LLVMConstPointerCast - LLVMConstPointerCast.restype = LLVMValueRef - LLVMConstPointerCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstIntCast = _libraries['llvm'].LLVMConstIntCast - LLVMConstIntCast.restype = LLVMValueRef - LLVMConstIntCast.argtypes = [LLVMValueRef, LLVMTypeRef, LLVMBool] -except AttributeError: - pass -try: - LLVMConstFPCast = _libraries['llvm'].LLVMConstFPCast - LLVMConstFPCast.restype = LLVMValueRef - LLVMConstFPCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSelect = _libraries['llvm'].LLVMConstSelect - LLVMConstSelect.restype = LLVMValueRef - LLVMConstSelect.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExtractElement = _libraries['llvm'].LLVMConstExtractElement - LLVMConstExtractElement.restype = LLVMValueRef - LLVMConstExtractElement.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstInsertElement = _libraries['llvm'].LLVMConstInsertElement - LLVMConstInsertElement.restype = LLVMValueRef - LLVMConstInsertElement.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstShuffleVector = _libraries['llvm'].LLVMConstShuffleVector - LLVMConstShuffleVector.restype = LLVMValueRef - LLVMConstShuffleVector.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExtractValue = _libraries['llvm'].LLVMConstExtractValue - LLVMConstExtractValue.restype = LLVMValueRef - LLVMConstExtractValue.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInsertValue = _libraries['llvm'].LLVMConstInsertValue - LLVMConstInsertValue.restype = LLVMValueRef - LLVMConstInsertValue.argtypes = [LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBlockAddress = _libraries['llvm'].LLVMBlockAddress - LLVMBlockAddress.restype = LLVMValueRef - LLVMBlockAddress.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMConstInlineAsm = _libraries['llvm'].LLVMConstInlineAsm - LLVMConstInlineAsm.restype = LLVMValueRef - LLVMConstInlineAsm.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMBool, LLVMBool] -except AttributeError: - pass -try: - LLVMGetGlobalParent = _libraries['llvm'].LLVMGetGlobalParent - LLVMGetGlobalParent.restype = LLVMModuleRef - LLVMGetGlobalParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsDeclaration = _libraries['llvm'].LLVMIsDeclaration - LLVMIsDeclaration.restype = LLVMBool - LLVMIsDeclaration.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLinkage = _libraries['llvm'].LLVMGetLinkage - LLVMGetLinkage.restype = LLVMLinkage - LLVMGetLinkage.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetLinkage = _libraries['llvm'].LLVMSetLinkage - LLVMSetLinkage.restype = None - LLVMSetLinkage.argtypes = [LLVMValueRef, LLVMLinkage] -except AttributeError: - pass -try: - LLVMGetSection = _libraries['llvm'].LLVMGetSection - LLVMGetSection.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSection.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetSection = _libraries['llvm'].LLVMSetSection - LLVMSetSection.restype = None - LLVMSetSection.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetVisibility = _libraries['llvm'].LLVMGetVisibility - LLVMGetVisibility.restype = LLVMVisibility - LLVMGetVisibility.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetVisibility = _libraries['llvm'].LLVMSetVisibility - LLVMSetVisibility.restype = None - LLVMSetVisibility.argtypes = [LLVMValueRef, LLVMVisibility] -except AttributeError: - pass -try: - LLVMGetDLLStorageClass = _libraries['llvm'].LLVMGetDLLStorageClass - LLVMGetDLLStorageClass.restype = LLVMDLLStorageClass - LLVMGetDLLStorageClass.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetDLLStorageClass = _libraries['llvm'].LLVMSetDLLStorageClass - LLVMSetDLLStorageClass.restype = None - LLVMSetDLLStorageClass.argtypes = [LLVMValueRef, LLVMDLLStorageClass] -except AttributeError: - pass -try: - LLVMGetUnnamedAddress = _libraries['llvm'].LLVMGetUnnamedAddress - LLVMGetUnnamedAddress.restype = LLVMUnnamedAddr - LLVMGetUnnamedAddress.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetUnnamedAddress = _libraries['llvm'].LLVMSetUnnamedAddress - LLVMSetUnnamedAddress.restype = None - LLVMSetUnnamedAddress.argtypes = [LLVMValueRef, LLVMUnnamedAddr] -except AttributeError: - pass -try: - LLVMGlobalGetValueType = _libraries['llvm'].LLVMGlobalGetValueType - LLVMGlobalGetValueType.restype = LLVMTypeRef - LLVMGlobalGetValueType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMHasUnnamedAddr = _libraries['llvm'].LLVMHasUnnamedAddr - LLVMHasUnnamedAddr.restype = LLVMBool - LLVMHasUnnamedAddr.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetUnnamedAddr = _libraries['llvm'].LLVMSetUnnamedAddr - LLVMSetUnnamedAddr.restype = None - LLVMSetUnnamedAddr.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetAlignment = _libraries['llvm'].LLVMGetAlignment - LLVMGetAlignment.restype = ctypes.c_uint32 - LLVMGetAlignment.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAlignment = _libraries['llvm'].LLVMSetAlignment - LLVMSetAlignment.restype = None - LLVMSetAlignment.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGlobalSetMetadata = _libraries['llvm'].LLVMGlobalSetMetadata - LLVMGlobalSetMetadata.restype = None - LLVMGlobalSetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMGlobalEraseMetadata = _libraries['llvm'].LLVMGlobalEraseMetadata - LLVMGlobalEraseMetadata.restype = None - LLVMGlobalEraseMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGlobalClearMetadata = _libraries['llvm'].LLVMGlobalClearMetadata - LLVMGlobalClearMetadata.restype = None - LLVMGlobalClearMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGlobalCopyAllMetadata = _libraries['llvm'].LLVMGlobalCopyAllMetadata - LLVMGlobalCopyAllMetadata.restype = ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry) - LLVMGlobalCopyAllMetadata.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDisposeValueMetadataEntries = _libraries['llvm'].LLVMDisposeValueMetadataEntries - LLVMDisposeValueMetadataEntries.restype = None - LLVMDisposeValueMetadataEntries.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry)] -except AttributeError: - pass -try: - LLVMValueMetadataEntriesGetKind = _libraries['llvm'].LLVMValueMetadataEntriesGetKind - LLVMValueMetadataEntriesGetKind.restype = ctypes.c_uint32 - LLVMValueMetadataEntriesGetKind.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMValueMetadataEntriesGetMetadata = _libraries['llvm'].LLVMValueMetadataEntriesGetMetadata - LLVMValueMetadataEntriesGetMetadata.restype = LLVMMetadataRef - LLVMValueMetadataEntriesGetMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddGlobal = _libraries['llvm'].LLVMAddGlobal - LLVMAddGlobal.restype = LLVMValueRef - LLVMAddGlobal.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddGlobalInAddressSpace = _libraries['llvm'].LLVMAddGlobalInAddressSpace - LLVMAddGlobalInAddressSpace.restype = LLVMValueRef - LLVMAddGlobalInAddressSpace.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetNamedGlobal = _libraries['llvm'].LLVMGetNamedGlobal - LLVMGetNamedGlobal.restype = LLVMValueRef - LLVMGetNamedGlobal.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstGlobal = _libraries['llvm'].LLVMGetFirstGlobal - LLVMGetFirstGlobal.restype = LLVMValueRef - LLVMGetFirstGlobal.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobal = _libraries['llvm'].LLVMGetLastGlobal - LLVMGetLastGlobal.restype = LLVMValueRef - LLVMGetLastGlobal.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobal = _libraries['llvm'].LLVMGetNextGlobal - LLVMGetNextGlobal.restype = LLVMValueRef - LLVMGetNextGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobal = _libraries['llvm'].LLVMGetPreviousGlobal - LLVMGetPreviousGlobal.restype = LLVMValueRef - LLVMGetPreviousGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMDeleteGlobal = _libraries['llvm'].LLVMDeleteGlobal - LLVMDeleteGlobal.restype = None - LLVMDeleteGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetInitializer = _libraries['llvm'].LLVMGetInitializer - LLVMGetInitializer.restype = LLVMValueRef - LLVMGetInitializer.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInitializer = _libraries['llvm'].LLVMSetInitializer - LLVMSetInitializer.restype = None - LLVMSetInitializer.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsThreadLocal = _libraries['llvm'].LLVMIsThreadLocal - LLVMIsThreadLocal.restype = LLVMBool - LLVMIsThreadLocal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetThreadLocal = _libraries['llvm'].LLVMSetThreadLocal - LLVMSetThreadLocal.restype = None - LLVMSetThreadLocal.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMIsGlobalConstant = _libraries['llvm'].LLVMIsGlobalConstant - LLVMIsGlobalConstant.restype = LLVMBool - LLVMIsGlobalConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGlobalConstant = _libraries['llvm'].LLVMSetGlobalConstant - LLVMSetGlobalConstant.restype = None - LLVMSetGlobalConstant.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetThreadLocalMode = _libraries['llvm'].LLVMGetThreadLocalMode - LLVMGetThreadLocalMode.restype = LLVMThreadLocalMode - LLVMGetThreadLocalMode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetThreadLocalMode = _libraries['llvm'].LLVMSetThreadLocalMode - LLVMSetThreadLocalMode.restype = None - LLVMSetThreadLocalMode.argtypes = [LLVMValueRef, LLVMThreadLocalMode] -except AttributeError: - pass -try: - LLVMIsExternallyInitialized = _libraries['llvm'].LLVMIsExternallyInitialized - LLVMIsExternallyInitialized.restype = LLVMBool - LLVMIsExternallyInitialized.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetExternallyInitialized = _libraries['llvm'].LLVMSetExternallyInitialized - LLVMSetExternallyInitialized.restype = None - LLVMSetExternallyInitialized.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMAddAlias = _libraries['llvm'].LLVMAddAlias - LLVMAddAlias.restype = LLVMValueRef - LLVMAddAlias.argtypes = [LLVMModuleRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddAlias2 = _libraries['llvm'].LLVMAddAlias2 - LLVMAddAlias2.restype = LLVMValueRef - LLVMAddAlias2.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetNamedGlobalAlias = _libraries['llvm'].LLVMGetNamedGlobalAlias - LLVMGetNamedGlobalAlias.restype = LLVMValueRef - LLVMGetNamedGlobalAlias.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetFirstGlobalAlias = _libraries['llvm'].LLVMGetFirstGlobalAlias - LLVMGetFirstGlobalAlias.restype = LLVMValueRef - LLVMGetFirstGlobalAlias.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobalAlias = _libraries['llvm'].LLVMGetLastGlobalAlias - LLVMGetLastGlobalAlias.restype = LLVMValueRef - LLVMGetLastGlobalAlias.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobalAlias = _libraries['llvm'].LLVMGetNextGlobalAlias - LLVMGetNextGlobalAlias.restype = LLVMValueRef - LLVMGetNextGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobalAlias = _libraries['llvm'].LLVMGetPreviousGlobalAlias - LLVMGetPreviousGlobalAlias.restype = LLVMValueRef - LLVMGetPreviousGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAliasGetAliasee = _libraries['llvm'].LLVMAliasGetAliasee - LLVMAliasGetAliasee.restype = LLVMValueRef - LLVMAliasGetAliasee.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAliasSetAliasee = _libraries['llvm'].LLVMAliasSetAliasee - LLVMAliasSetAliasee.restype = None - LLVMAliasSetAliasee.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDeleteFunction = _libraries['llvm'].LLVMDeleteFunction - LLVMDeleteFunction.restype = None - LLVMDeleteFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMHasPersonalityFn = _libraries['llvm'].LLVMHasPersonalityFn - LLVMHasPersonalityFn.restype = LLVMBool - LLVMHasPersonalityFn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPersonalityFn = _libraries['llvm'].LLVMGetPersonalityFn - LLVMGetPersonalityFn.restype = LLVMValueRef - LLVMGetPersonalityFn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetPersonalityFn = _libraries['llvm'].LLVMSetPersonalityFn - LLVMSetPersonalityFn.restype = None - LLVMSetPersonalityFn.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMLookupIntrinsicID = _libraries['llvm'].LLVMLookupIntrinsicID - LLVMLookupIntrinsicID.restype = ctypes.c_uint32 - LLVMLookupIntrinsicID.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetIntrinsicID = _libraries['llvm'].LLVMGetIntrinsicID - LLVMGetIntrinsicID.restype = ctypes.c_uint32 - LLVMGetIntrinsicID.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIntrinsicDeclaration = _libraries['llvm'].LLVMGetIntrinsicDeclaration - LLVMGetIntrinsicDeclaration.restype = LLVMValueRef - LLVMGetIntrinsicDeclaration.argtypes = [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t] -except AttributeError: - pass -try: - LLVMIntrinsicGetType = _libraries['llvm'].LLVMIntrinsicGetType - LLVMIntrinsicGetType.restype = LLVMTypeRef - LLVMIntrinsicGetType.argtypes = [LLVMContextRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t] -except AttributeError: - pass -try: - LLVMIntrinsicGetName = _libraries['llvm'].LLVMIntrinsicGetName - LLVMIntrinsicGetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicGetName.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicCopyOverloadedName = _libraries['llvm'].LLVMIntrinsicCopyOverloadedName - LLVMIntrinsicCopyOverloadedName.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicCopyOverloadedName.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicCopyOverloadedName2 = _libraries['llvm'].LLVMIntrinsicCopyOverloadedName2 - LLVMIntrinsicCopyOverloadedName2.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicCopyOverloadedName2.argtypes = [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicIsOverloaded = _libraries['llvm'].LLVMIntrinsicIsOverloaded - LLVMIntrinsicIsOverloaded.restype = LLVMBool - LLVMIntrinsicIsOverloaded.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetFunctionCallConv = _libraries['llvm'].LLVMGetFunctionCallConv - LLVMGetFunctionCallConv.restype = ctypes.c_uint32 - LLVMGetFunctionCallConv.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetFunctionCallConv = _libraries['llvm'].LLVMSetFunctionCallConv - LLVMSetFunctionCallConv.restype = None - LLVMSetFunctionCallConv.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetGC = _libraries['llvm'].LLVMGetGC - LLVMGetGC.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetGC.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGC = _libraries['llvm'].LLVMSetGC - LLVMSetGC.restype = None - LLVMSetGC.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddAttributeAtIndex = _libraries['llvm'].LLVMAddAttributeAtIndex - LLVMAddAttributeAtIndex.restype = None - LLVMAddAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetAttributeCountAtIndex = _libraries['llvm'].LLVMGetAttributeCountAtIndex - LLVMGetAttributeCountAtIndex.restype = ctypes.c_uint32 - LLVMGetAttributeCountAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex] -except AttributeError: - pass -try: - LLVMGetAttributesAtIndex = _libraries['llvm'].LLVMGetAttributesAtIndex - LLVMGetAttributesAtIndex.restype = None - LLVMGetAttributesAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueAttributeRef))] -except AttributeError: - pass -try: - LLVMGetEnumAttributeAtIndex = _libraries['llvm'].LLVMGetEnumAttributeAtIndex - LLVMGetEnumAttributeAtIndex.restype = LLVMAttributeRef - LLVMGetEnumAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetStringAttributeAtIndex = _libraries['llvm'].LLVMGetStringAttributeAtIndex - LLVMGetStringAttributeAtIndex.restype = LLVMAttributeRef - LLVMGetStringAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveEnumAttributeAtIndex = _libraries['llvm'].LLVMRemoveEnumAttributeAtIndex - LLVMRemoveEnumAttributeAtIndex.restype = None - LLVMRemoveEnumAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveStringAttributeAtIndex = _libraries['llvm'].LLVMRemoveStringAttributeAtIndex - LLVMRemoveStringAttributeAtIndex.restype = None - LLVMRemoveStringAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddTargetDependentFunctionAttr = _libraries['llvm'].LLVMAddTargetDependentFunctionAttr - LLVMAddTargetDependentFunctionAttr.restype = None - LLVMAddTargetDependentFunctionAttr.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMCountParams = _libraries['llvm'].LLVMCountParams - LLVMCountParams.restype = ctypes.c_uint32 - LLVMCountParams.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetParams = _libraries['llvm'].LLVMGetParams - LLVMGetParams.restype = None - LLVMGetParams.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMGetParam = _libraries['llvm'].LLVMGetParam - LLVMGetParam.restype = LLVMValueRef - LLVMGetParam.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetParamParent = _libraries['llvm'].LLVMGetParamParent - LLVMGetParamParent.restype = LLVMValueRef - LLVMGetParamParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetFirstParam = _libraries['llvm'].LLVMGetFirstParam - LLVMGetFirstParam.restype = LLVMValueRef - LLVMGetFirstParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLastParam = _libraries['llvm'].LLVMGetLastParam - LLVMGetLastParam.restype = LLVMValueRef - LLVMGetLastParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextParam = _libraries['llvm'].LLVMGetNextParam - LLVMGetNextParam.restype = LLVMValueRef - LLVMGetNextParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousParam = _libraries['llvm'].LLVMGetPreviousParam - LLVMGetPreviousParam.restype = LLVMValueRef - LLVMGetPreviousParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetParamAlignment = _libraries['llvm'].LLVMSetParamAlignment - LLVMSetParamAlignment.restype = None - LLVMSetParamAlignment.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddGlobalIFunc = _libraries['llvm'].LLVMAddGlobalIFunc - LLVMAddGlobalIFunc.restype = LLVMValueRef - LLVMAddGlobalIFunc.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNamedGlobalIFunc = _libraries['llvm'].LLVMGetNamedGlobalIFunc - LLVMGetNamedGlobalIFunc.restype = LLVMValueRef - LLVMGetNamedGlobalIFunc.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetFirstGlobalIFunc = _libraries['llvm'].LLVMGetFirstGlobalIFunc - LLVMGetFirstGlobalIFunc.restype = LLVMValueRef - LLVMGetFirstGlobalIFunc.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobalIFunc = _libraries['llvm'].LLVMGetLastGlobalIFunc - LLVMGetLastGlobalIFunc.restype = LLVMValueRef - LLVMGetLastGlobalIFunc.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobalIFunc = _libraries['llvm'].LLVMGetNextGlobalIFunc - LLVMGetNextGlobalIFunc.restype = LLVMValueRef - LLVMGetNextGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobalIFunc = _libraries['llvm'].LLVMGetPreviousGlobalIFunc - LLVMGetPreviousGlobalIFunc.restype = LLVMValueRef - LLVMGetPreviousGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetGlobalIFuncResolver = _libraries['llvm'].LLVMGetGlobalIFuncResolver - LLVMGetGlobalIFuncResolver.restype = LLVMValueRef - LLVMGetGlobalIFuncResolver.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGlobalIFuncResolver = _libraries['llvm'].LLVMSetGlobalIFuncResolver - LLVMSetGlobalIFuncResolver.restype = None - LLVMSetGlobalIFuncResolver.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMEraseGlobalIFunc = _libraries['llvm'].LLVMEraseGlobalIFunc - LLVMEraseGlobalIFunc.restype = None - LLVMEraseGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMRemoveGlobalIFunc = _libraries['llvm'].LLVMRemoveGlobalIFunc - LLVMRemoveGlobalIFunc.restype = None - LLVMRemoveGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMMDStringInContext2 = _libraries['llvm'].LLVMMDStringInContext2 - LLVMMDStringInContext2.restype = LLVMMetadataRef - LLVMMDStringInContext2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMMDNodeInContext2 = _libraries['llvm'].LLVMMDNodeInContext2 - LLVMMDNodeInContext2.restype = LLVMMetadataRef - LLVMMDNodeInContext2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMMetadataAsValue = _libraries['llvm'].LLVMMetadataAsValue - LLVMMetadataAsValue.restype = LLVMValueRef - LLVMMetadataAsValue.argtypes = [LLVMContextRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMValueAsMetadata = _libraries['llvm'].LLVMValueAsMetadata - LLVMValueAsMetadata.restype = LLVMMetadataRef - LLVMValueAsMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMDString = _libraries['llvm'].LLVMGetMDString - LLVMGetMDString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetMDString.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetMDNodeNumOperands = _libraries['llvm'].LLVMGetMDNodeNumOperands - LLVMGetMDNodeNumOperands.restype = ctypes.c_uint32 - LLVMGetMDNodeNumOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMDNodeOperands = _libraries['llvm'].LLVMGetMDNodeOperands - LLVMGetMDNodeOperands.restype = None - LLVMGetMDNodeOperands.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMMDStringInContext = _libraries['llvm'].LLVMMDStringInContext - LLVMMDStringInContext.restype = LLVMValueRef - LLVMMDStringInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDString = _libraries['llvm'].LLVMMDString - LLVMMDString.restype = LLVMValueRef - LLVMMDString.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDNodeInContext = _libraries['llvm'].LLVMMDNodeInContext - LLVMMDNodeInContext.restype = LLVMValueRef - LLVMMDNodeInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDNode = _libraries['llvm'].LLVMMDNode - LLVMMDNode.restype = LLVMValueRef - LLVMMDNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBasicBlockAsValue = _libraries['llvm'].LLVMBasicBlockAsValue - LLVMBasicBlockAsValue.restype = LLVMValueRef - LLVMBasicBlockAsValue.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMValueIsBasicBlock = _libraries['llvm'].LLVMValueIsBasicBlock - LLVMValueIsBasicBlock.restype = LLVMBool - LLVMValueIsBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMValueAsBasicBlock = _libraries['llvm'].LLVMValueAsBasicBlock - LLVMValueAsBasicBlock.restype = LLVMBasicBlockRef - LLVMValueAsBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockName = _libraries['llvm'].LLVMGetBasicBlockName - LLVMGetBasicBlockName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetBasicBlockName.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockParent = _libraries['llvm'].LLVMGetBasicBlockParent - LLVMGetBasicBlockParent.restype = LLVMValueRef - LLVMGetBasicBlockParent.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockTerminator = _libraries['llvm'].LLVMGetBasicBlockTerminator - LLVMGetBasicBlockTerminator.restype = LLVMValueRef - LLVMGetBasicBlockTerminator.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMCountBasicBlocks = _libraries['llvm'].LLVMCountBasicBlocks - LLVMCountBasicBlocks.restype = ctypes.c_uint32 - LLVMCountBasicBlocks.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetBasicBlocks = _libraries['llvm'].LLVMGetBasicBlocks - LLVMGetBasicBlocks.restype = None - LLVMGetBasicBlocks.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock))] -except AttributeError: - pass -try: - LLVMGetFirstBasicBlock = _libraries['llvm'].LLVMGetFirstBasicBlock - LLVMGetFirstBasicBlock.restype = LLVMBasicBlockRef - LLVMGetFirstBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLastBasicBlock = _libraries['llvm'].LLVMGetLastBasicBlock - LLVMGetLastBasicBlock.restype = LLVMBasicBlockRef - LLVMGetLastBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextBasicBlock = _libraries['llvm'].LLVMGetNextBasicBlock - LLVMGetNextBasicBlock.restype = LLVMBasicBlockRef - LLVMGetNextBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetPreviousBasicBlock = _libraries['llvm'].LLVMGetPreviousBasicBlock - LLVMGetPreviousBasicBlock.restype = LLVMBasicBlockRef - LLVMGetPreviousBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetEntryBasicBlock = _libraries['llvm'].LLVMGetEntryBasicBlock - LLVMGetEntryBasicBlock.restype = LLVMBasicBlockRef - LLVMGetEntryBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInsertExistingBasicBlockAfterInsertBlock = _libraries['llvm'].LLVMInsertExistingBasicBlockAfterInsertBlock - LLVMInsertExistingBasicBlockAfterInsertBlock.restype = None - LLVMInsertExistingBasicBlockAfterInsertBlock.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMAppendExistingBasicBlock = _libraries['llvm'].LLVMAppendExistingBasicBlock - LLVMAppendExistingBasicBlock.restype = None - LLVMAppendExistingBasicBlock.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMCreateBasicBlockInContext = _libraries['llvm'].LLVMCreateBasicBlockInContext - LLVMCreateBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMCreateBasicBlockInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAppendBasicBlockInContext = _libraries['llvm'].LLVMAppendBasicBlockInContext - LLVMAppendBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMAppendBasicBlockInContext.argtypes = [LLVMContextRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAppendBasicBlock = _libraries['llvm'].LLVMAppendBasicBlock - LLVMAppendBasicBlock.restype = LLVMBasicBlockRef - LLVMAppendBasicBlock.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMInsertBasicBlockInContext = _libraries['llvm'].LLVMInsertBasicBlockInContext - LLVMInsertBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMInsertBasicBlockInContext.argtypes = [LLVMContextRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMInsertBasicBlock = _libraries['llvm'].LLVMInsertBasicBlock - LLVMInsertBasicBlock.restype = LLVMBasicBlockRef - LLVMInsertBasicBlock.argtypes = [LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDeleteBasicBlock = _libraries['llvm'].LLVMDeleteBasicBlock - LLVMDeleteBasicBlock.restype = None - LLVMDeleteBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMRemoveBasicBlockFromParent = _libraries['llvm'].LLVMRemoveBasicBlockFromParent - LLVMRemoveBasicBlockFromParent.restype = None - LLVMRemoveBasicBlockFromParent.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMMoveBasicBlockBefore = _libraries['llvm'].LLVMMoveBasicBlockBefore - LLVMMoveBasicBlockBefore.restype = None - LLVMMoveBasicBlockBefore.argtypes = [LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMMoveBasicBlockAfter = _libraries['llvm'].LLVMMoveBasicBlockAfter - LLVMMoveBasicBlockAfter.restype = None - LLVMMoveBasicBlockAfter.argtypes = [LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetFirstInstruction = _libraries['llvm'].LLVMGetFirstInstruction - LLVMGetFirstInstruction.restype = LLVMValueRef - LLVMGetFirstInstruction.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetLastInstruction = _libraries['llvm'].LLVMGetLastInstruction - LLVMGetLastInstruction.restype = LLVMValueRef - LLVMGetLastInstruction.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMHasMetadata = _libraries['llvm'].LLVMHasMetadata - LLVMHasMetadata.restype = ctypes.c_int32 - LLVMHasMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMetadata = _libraries['llvm'].LLVMGetMetadata - LLVMGetMetadata.restype = LLVMValueRef - LLVMGetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetMetadata = _libraries['llvm'].LLVMSetMetadata - LLVMSetMetadata.restype = None - LLVMSetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionGetAllMetadataOtherThanDebugLoc = _libraries['llvm'].LLVMInstructionGetAllMetadataOtherThanDebugLoc - LLVMInstructionGetAllMetadataOtherThanDebugLoc.restype = ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry) - LLVMInstructionGetAllMetadataOtherThanDebugLoc.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMGetInstructionParent = _libraries['llvm'].LLVMGetInstructionParent - LLVMGetInstructionParent.restype = LLVMBasicBlockRef - LLVMGetInstructionParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextInstruction = _libraries['llvm'].LLVMGetNextInstruction - LLVMGetNextInstruction.restype = LLVMValueRef - LLVMGetNextInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousInstruction = _libraries['llvm'].LLVMGetPreviousInstruction - LLVMGetPreviousInstruction.restype = LLVMValueRef - LLVMGetPreviousInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionRemoveFromParent = _libraries['llvm'].LLVMInstructionRemoveFromParent - LLVMInstructionRemoveFromParent.restype = None - LLVMInstructionRemoveFromParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionEraseFromParent = _libraries['llvm'].LLVMInstructionEraseFromParent - LLVMInstructionEraseFromParent.restype = None - LLVMInstructionEraseFromParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetInstructionOpcode = _libraries['llvm'].LLVMGetInstructionOpcode - LLVMGetInstructionOpcode.restype = LLVMOpcode - LLVMGetInstructionOpcode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetICmpPredicate = _libraries['llvm'].LLVMGetICmpPredicate - LLVMGetICmpPredicate.restype = LLVMIntPredicate - LLVMGetICmpPredicate.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetFCmpPredicate = _libraries['llvm'].LLVMGetFCmpPredicate - LLVMGetFCmpPredicate.restype = LLVMRealPredicate - LLVMGetFCmpPredicate.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionClone = _libraries['llvm'].LLVMInstructionClone - LLVMInstructionClone.restype = LLVMValueRef - LLVMInstructionClone.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsATerminatorInst = _libraries['llvm'].LLVMIsATerminatorInst - LLVMIsATerminatorInst.restype = LLVMValueRef - LLVMIsATerminatorInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNumArgOperands = _libraries['llvm'].LLVMGetNumArgOperands - LLVMGetNumArgOperands.restype = ctypes.c_uint32 - LLVMGetNumArgOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInstructionCallConv = _libraries['llvm'].LLVMSetInstructionCallConv - LLVMSetInstructionCallConv.restype = None - LLVMSetInstructionCallConv.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetInstructionCallConv = _libraries['llvm'].LLVMGetInstructionCallConv - LLVMGetInstructionCallConv.restype = ctypes.c_uint32 - LLVMGetInstructionCallConv.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInstrParamAlignment = _libraries['llvm'].LLVMSetInstrParamAlignment - LLVMSetInstrParamAlignment.restype = None - LLVMSetInstrParamAlignment.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddCallSiteAttribute = _libraries['llvm'].LLVMAddCallSiteAttribute - LLVMAddCallSiteAttribute.restype = None - LLVMAddCallSiteAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetCallSiteAttributeCount = _libraries['llvm'].LLVMGetCallSiteAttributeCount - LLVMGetCallSiteAttributeCount.restype = ctypes.c_uint32 - LLVMGetCallSiteAttributeCount.argtypes = [LLVMValueRef, LLVMAttributeIndex] -except AttributeError: - pass -try: - LLVMGetCallSiteAttributes = _libraries['llvm'].LLVMGetCallSiteAttributes - LLVMGetCallSiteAttributes.restype = None - LLVMGetCallSiteAttributes.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueAttributeRef))] -except AttributeError: - pass -try: - LLVMGetCallSiteEnumAttribute = _libraries['llvm'].LLVMGetCallSiteEnumAttribute - LLVMGetCallSiteEnumAttribute.restype = LLVMAttributeRef - LLVMGetCallSiteEnumAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetCallSiteStringAttribute = _libraries['llvm'].LLVMGetCallSiteStringAttribute - LLVMGetCallSiteStringAttribute.restype = LLVMAttributeRef - LLVMGetCallSiteStringAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveCallSiteEnumAttribute = _libraries['llvm'].LLVMRemoveCallSiteEnumAttribute - LLVMRemoveCallSiteEnumAttribute.restype = None - LLVMRemoveCallSiteEnumAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveCallSiteStringAttribute = _libraries['llvm'].LLVMRemoveCallSiteStringAttribute - LLVMRemoveCallSiteStringAttribute.restype = None - LLVMRemoveCallSiteStringAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetCalledFunctionType = _libraries['llvm'].LLVMGetCalledFunctionType - LLVMGetCalledFunctionType.restype = LLVMTypeRef - LLVMGetCalledFunctionType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCalledValue = _libraries['llvm'].LLVMGetCalledValue - LLVMGetCalledValue.restype = LLVMValueRef - LLVMGetCalledValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsTailCall = _libraries['llvm'].LLVMIsTailCall - LLVMIsTailCall.restype = LLVMBool - LLVMIsTailCall.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetTailCall = _libraries['llvm'].LLVMSetTailCall - LLVMSetTailCall.restype = None - LLVMSetTailCall.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetNormalDest = _libraries['llvm'].LLVMGetNormalDest - LLVMGetNormalDest.restype = LLVMBasicBlockRef - LLVMGetNormalDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetUnwindDest = _libraries['llvm'].LLVMGetUnwindDest - LLVMGetUnwindDest.restype = LLVMBasicBlockRef - LLVMGetUnwindDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetNormalDest = _libraries['llvm'].LLVMSetNormalDest - LLVMSetNormalDest.restype = None - LLVMSetNormalDest.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMSetUnwindDest = _libraries['llvm'].LLVMSetUnwindDest - LLVMSetUnwindDest.restype = None - LLVMSetUnwindDest.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumSuccessors = _libraries['llvm'].LLVMGetNumSuccessors - LLVMGetNumSuccessors.restype = ctypes.c_uint32 - LLVMGetNumSuccessors.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetSuccessor = _libraries['llvm'].LLVMGetSuccessor - LLVMGetSuccessor.restype = LLVMBasicBlockRef - LLVMGetSuccessor.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetSuccessor = _libraries['llvm'].LLVMSetSuccessor - LLVMSetSuccessor.restype = None - LLVMSetSuccessor.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMIsConditional = _libraries['llvm'].LLVMIsConditional - LLVMIsConditional.restype = LLVMBool - LLVMIsConditional.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCondition = _libraries['llvm'].LLVMGetCondition - LLVMGetCondition.restype = LLVMValueRef - LLVMGetCondition.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCondition = _libraries['llvm'].LLVMSetCondition - LLVMSetCondition.restype = None - LLVMSetCondition.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetSwitchDefaultDest = _libraries['llvm'].LLVMGetSwitchDefaultDest - LLVMGetSwitchDefaultDest.restype = LLVMBasicBlockRef - LLVMGetSwitchDefaultDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetAllocatedType = _libraries['llvm'].LLVMGetAllocatedType - LLVMGetAllocatedType.restype = LLVMTypeRef - LLVMGetAllocatedType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsInBounds = _libraries['llvm'].LLVMIsInBounds - LLVMIsInBounds.restype = LLVMBool - LLVMIsInBounds.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetIsInBounds = _libraries['llvm'].LLVMSetIsInBounds - LLVMSetIsInBounds.restype = None - LLVMSetIsInBounds.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetGEPSourceElementType = _libraries['llvm'].LLVMGetGEPSourceElementType - LLVMGetGEPSourceElementType.restype = LLVMTypeRef - LLVMGetGEPSourceElementType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddIncoming = _libraries['llvm'].LLVMAddIncoming - LLVMAddIncoming.restype = None - LLVMAddIncoming.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMCountIncoming = _libraries['llvm'].LLVMCountIncoming - LLVMCountIncoming.restype = ctypes.c_uint32 - LLVMCountIncoming.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIncomingValue = _libraries['llvm'].LLVMGetIncomingValue - LLVMGetIncomingValue.restype = LLVMValueRef - LLVMGetIncomingValue.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetIncomingBlock = _libraries['llvm'].LLVMGetIncomingBlock - LLVMGetIncomingBlock.restype = LLVMBasicBlockRef - LLVMGetIncomingBlock.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetNumIndices = _libraries['llvm'].LLVMGetNumIndices - LLVMGetNumIndices.restype = ctypes.c_uint32 - LLVMGetNumIndices.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIndices = _libraries['llvm'].LLVMGetIndices - LLVMGetIndices.restype = ctypes.POINTER(ctypes.c_uint32) - LLVMGetIndices.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMCreateBuilderInContext = _libraries['llvm'].LLVMCreateBuilderInContext - LLVMCreateBuilderInContext.restype = LLVMBuilderRef - LLVMCreateBuilderInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMCreateBuilder = _libraries['llvm'].LLVMCreateBuilder - LLVMCreateBuilder.restype = LLVMBuilderRef - LLVMCreateBuilder.argtypes = [] -except AttributeError: - pass -try: - LLVMPositionBuilder = _libraries['llvm'].LLVMPositionBuilder - LLVMPositionBuilder.restype = None - LLVMPositionBuilder.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMPositionBuilderBefore = _libraries['llvm'].LLVMPositionBuilderBefore - LLVMPositionBuilderBefore.restype = None - LLVMPositionBuilderBefore.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMPositionBuilderAtEnd = _libraries['llvm'].LLVMPositionBuilderAtEnd - LLVMPositionBuilderAtEnd.restype = None - LLVMPositionBuilderAtEnd.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetInsertBlock = _libraries['llvm'].LLVMGetInsertBlock - LLVMGetInsertBlock.restype = LLVMBasicBlockRef - LLVMGetInsertBlock.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMClearInsertionPosition = _libraries['llvm'].LLVMClearInsertionPosition - LLVMClearInsertionPosition.restype = None - LLVMClearInsertionPosition.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMInsertIntoBuilder = _libraries['llvm'].LLVMInsertIntoBuilder - LLVMInsertIntoBuilder.restype = None - LLVMInsertIntoBuilder.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMInsertIntoBuilderWithName = _libraries['llvm'].LLVMInsertIntoBuilderWithName - LLVMInsertIntoBuilderWithName.restype = None - LLVMInsertIntoBuilderWithName.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeBuilder = _libraries['llvm'].LLVMDisposeBuilder - LLVMDisposeBuilder.restype = None - LLVMDisposeBuilder.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMGetCurrentDebugLocation2 = _libraries['llvm'].LLVMGetCurrentDebugLocation2 - LLVMGetCurrentDebugLocation2.restype = LLVMMetadataRef - LLVMGetCurrentDebugLocation2.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMSetCurrentDebugLocation2 = _libraries['llvm'].LLVMSetCurrentDebugLocation2 - LLVMSetCurrentDebugLocation2.restype = None - LLVMSetCurrentDebugLocation2.argtypes = [LLVMBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMSetInstDebugLocation = _libraries['llvm'].LLVMSetInstDebugLocation - LLVMSetInstDebugLocation.restype = None - LLVMSetInstDebugLocation.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddMetadataToInst = _libraries['llvm'].LLVMAddMetadataToInst - LLVMAddMetadataToInst.restype = None - LLVMAddMetadataToInst.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuilderGetDefaultFPMathTag = _libraries['llvm'].LLVMBuilderGetDefaultFPMathTag - LLVMBuilderGetDefaultFPMathTag.restype = LLVMMetadataRef - LLVMBuilderGetDefaultFPMathTag.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuilderSetDefaultFPMathTag = _libraries['llvm'].LLVMBuilderSetDefaultFPMathTag - LLVMBuilderSetDefaultFPMathTag.restype = None - LLVMBuilderSetDefaultFPMathTag.argtypes = [LLVMBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMSetCurrentDebugLocation = _libraries['llvm'].LLVMSetCurrentDebugLocation - LLVMSetCurrentDebugLocation.restype = None - LLVMSetCurrentDebugLocation.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCurrentDebugLocation = _libraries['llvm'].LLVMGetCurrentDebugLocation - LLVMGetCurrentDebugLocation.restype = LLVMValueRef - LLVMGetCurrentDebugLocation.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildRetVoid = _libraries['llvm'].LLVMBuildRetVoid - LLVMBuildRetVoid.restype = LLVMValueRef - LLVMBuildRetVoid.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildRet = _libraries['llvm'].LLVMBuildRet - LLVMBuildRet.restype = LLVMValueRef - LLVMBuildRet.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAggregateRet = _libraries['llvm'].LLVMBuildAggregateRet - LLVMBuildAggregateRet.restype = LLVMValueRef - LLVMBuildAggregateRet.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildBr = _libraries['llvm'].LLVMBuildBr - LLVMBuildBr.restype = LLVMValueRef - LLVMBuildBr.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCondBr = _libraries['llvm'].LLVMBuildCondBr - LLVMBuildCondBr.restype = LLVMValueRef - LLVMBuildCondBr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildSwitch = _libraries['llvm'].LLVMBuildSwitch - LLVMBuildSwitch.restype = LLVMValueRef - LLVMBuildSwitch.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildIndirectBr = _libraries['llvm'].LLVMBuildIndirectBr - LLVMBuildIndirectBr.restype = LLVMValueRef - LLVMBuildIndirectBr.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildInvoke = _libraries['llvm'].LLVMBuildInvoke - LLVMBuildInvoke.restype = LLVMValueRef - LLVMBuildInvoke.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInvoke2 = _libraries['llvm'].LLVMBuildInvoke2 - LLVMBuildInvoke2.restype = LLVMValueRef - LLVMBuildInvoke2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUnreachable = _libraries['llvm'].LLVMBuildUnreachable - LLVMBuildUnreachable.restype = LLVMValueRef - LLVMBuildUnreachable.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildResume = _libraries['llvm'].LLVMBuildResume - LLVMBuildResume.restype = LLVMValueRef - LLVMBuildResume.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildLandingPad = _libraries['llvm'].LLVMBuildLandingPad - LLVMBuildLandingPad.restype = LLVMValueRef - LLVMBuildLandingPad.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCleanupRet = _libraries['llvm'].LLVMBuildCleanupRet - LLVMBuildCleanupRet.restype = LLVMValueRef - LLVMBuildCleanupRet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCatchRet = _libraries['llvm'].LLVMBuildCatchRet - LLVMBuildCatchRet.restype = LLVMValueRef - LLVMBuildCatchRet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCatchPad = _libraries['llvm'].LLVMBuildCatchPad - LLVMBuildCatchPad.restype = LLVMValueRef - LLVMBuildCatchPad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCleanupPad = _libraries['llvm'].LLVMBuildCleanupPad - LLVMBuildCleanupPad.restype = LLVMValueRef - LLVMBuildCleanupPad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCatchSwitch = _libraries['llvm'].LLVMBuildCatchSwitch - LLVMBuildCatchSwitch.restype = LLVMValueRef - LLVMBuildCatchSwitch.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddCase = _libraries['llvm'].LLVMAddCase - LLVMAddCase.restype = None - LLVMAddCase.argtypes = [LLVMValueRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMAddDestination = _libraries['llvm'].LLVMAddDestination - LLVMAddDestination.restype = None - LLVMAddDestination.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumClauses = _libraries['llvm'].LLVMGetNumClauses - LLVMGetNumClauses.restype = ctypes.c_uint32 - LLVMGetNumClauses.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetClause = _libraries['llvm'].LLVMGetClause - LLVMGetClause.restype = LLVMValueRef - LLVMGetClause.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddClause = _libraries['llvm'].LLVMAddClause - LLVMAddClause.restype = None - LLVMAddClause.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsCleanup = _libraries['llvm'].LLVMIsCleanup - LLVMIsCleanup.restype = LLVMBool - LLVMIsCleanup.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCleanup = _libraries['llvm'].LLVMSetCleanup - LLVMSetCleanup.restype = None - LLVMSetCleanup.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMAddHandler = _libraries['llvm'].LLVMAddHandler - LLVMAddHandler.restype = None - LLVMAddHandler.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumHandlers = _libraries['llvm'].LLVMGetNumHandlers - LLVMGetNumHandlers.restype = ctypes.c_uint32 - LLVMGetNumHandlers.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetHandlers = _libraries['llvm'].LLVMGetHandlers - LLVMGetHandlers.restype = None - LLVMGetHandlers.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock))] -except AttributeError: - pass -try: - LLVMGetArgOperand = _libraries['llvm'].LLVMGetArgOperand - LLVMGetArgOperand.restype = LLVMValueRef - LLVMGetArgOperand.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetArgOperand = _libraries['llvm'].LLVMSetArgOperand - LLVMSetArgOperand.restype = None - LLVMSetArgOperand.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetParentCatchSwitch = _libraries['llvm'].LLVMGetParentCatchSwitch - LLVMGetParentCatchSwitch.restype = LLVMValueRef - LLVMGetParentCatchSwitch.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetParentCatchSwitch = _libraries['llvm'].LLVMSetParentCatchSwitch - LLVMSetParentCatchSwitch.restype = None - LLVMSetParentCatchSwitch.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAdd = _libraries['llvm'].LLVMBuildAdd - LLVMBuildAdd.restype = LLVMValueRef - LLVMBuildAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWAdd = _libraries['llvm'].LLVMBuildNSWAdd - LLVMBuildNSWAdd.restype = LLVMValueRef - LLVMBuildNSWAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWAdd = _libraries['llvm'].LLVMBuildNUWAdd - LLVMBuildNUWAdd.restype = LLVMValueRef - LLVMBuildNUWAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFAdd = _libraries['llvm'].LLVMBuildFAdd - LLVMBuildFAdd.restype = LLVMValueRef - LLVMBuildFAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSub = _libraries['llvm'].LLVMBuildSub - LLVMBuildSub.restype = LLVMValueRef - LLVMBuildSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWSub = _libraries['llvm'].LLVMBuildNSWSub - LLVMBuildNSWSub.restype = LLVMValueRef - LLVMBuildNSWSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWSub = _libraries['llvm'].LLVMBuildNUWSub - LLVMBuildNUWSub.restype = LLVMValueRef - LLVMBuildNUWSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFSub = _libraries['llvm'].LLVMBuildFSub - LLVMBuildFSub.restype = LLVMValueRef - LLVMBuildFSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMul = _libraries['llvm'].LLVMBuildMul - LLVMBuildMul.restype = LLVMValueRef - LLVMBuildMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWMul = _libraries['llvm'].LLVMBuildNSWMul - LLVMBuildNSWMul.restype = LLVMValueRef - LLVMBuildNSWMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWMul = _libraries['llvm'].LLVMBuildNUWMul - LLVMBuildNUWMul.restype = LLVMValueRef - LLVMBuildNUWMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFMul = _libraries['llvm'].LLVMBuildFMul - LLVMBuildFMul.restype = LLVMValueRef - LLVMBuildFMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUDiv = _libraries['llvm'].LLVMBuildUDiv - LLVMBuildUDiv.restype = LLVMValueRef - LLVMBuildUDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExactUDiv = _libraries['llvm'].LLVMBuildExactUDiv - LLVMBuildExactUDiv.restype = LLVMValueRef - LLVMBuildExactUDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSDiv = _libraries['llvm'].LLVMBuildSDiv - LLVMBuildSDiv.restype = LLVMValueRef - LLVMBuildSDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExactSDiv = _libraries['llvm'].LLVMBuildExactSDiv - LLVMBuildExactSDiv.restype = LLVMValueRef - LLVMBuildExactSDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFDiv = _libraries['llvm'].LLVMBuildFDiv - LLVMBuildFDiv.restype = LLVMValueRef - LLVMBuildFDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildURem = _libraries['llvm'].LLVMBuildURem - LLVMBuildURem.restype = LLVMValueRef - LLVMBuildURem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSRem = _libraries['llvm'].LLVMBuildSRem - LLVMBuildSRem.restype = LLVMValueRef - LLVMBuildSRem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFRem = _libraries['llvm'].LLVMBuildFRem - LLVMBuildFRem.restype = LLVMValueRef - LLVMBuildFRem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildShl = _libraries['llvm'].LLVMBuildShl - LLVMBuildShl.restype = LLVMValueRef - LLVMBuildShl.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildLShr = _libraries['llvm'].LLVMBuildLShr - LLVMBuildLShr.restype = LLVMValueRef - LLVMBuildLShr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAShr = _libraries['llvm'].LLVMBuildAShr - LLVMBuildAShr.restype = LLVMValueRef - LLVMBuildAShr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAnd = _libraries['llvm'].LLVMBuildAnd - LLVMBuildAnd.restype = LLVMValueRef - LLVMBuildAnd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildOr = _libraries['llvm'].LLVMBuildOr - LLVMBuildOr.restype = LLVMValueRef - LLVMBuildOr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildXor = _libraries['llvm'].LLVMBuildXor - LLVMBuildXor.restype = LLVMValueRef - LLVMBuildXor.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildBinOp = _libraries['llvm'].LLVMBuildBinOp - LLVMBuildBinOp.restype = LLVMValueRef - LLVMBuildBinOp.argtypes = [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNeg = _libraries['llvm'].LLVMBuildNeg - LLVMBuildNeg.restype = LLVMValueRef - LLVMBuildNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWNeg = _libraries['llvm'].LLVMBuildNSWNeg - LLVMBuildNSWNeg.restype = LLVMValueRef - LLVMBuildNSWNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWNeg = _libraries['llvm'].LLVMBuildNUWNeg - LLVMBuildNUWNeg.restype = LLVMValueRef - LLVMBuildNUWNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFNeg = _libraries['llvm'].LLVMBuildFNeg - LLVMBuildFNeg.restype = LLVMValueRef - LLVMBuildFNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNot = _libraries['llvm'].LLVMBuildNot - LLVMBuildNot.restype = LLVMValueRef - LLVMBuildNot.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMalloc = _libraries['llvm'].LLVMBuildMalloc - LLVMBuildMalloc.restype = LLVMValueRef - LLVMBuildMalloc.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildArrayMalloc = _libraries['llvm'].LLVMBuildArrayMalloc - LLVMBuildArrayMalloc.restype = LLVMValueRef - LLVMBuildArrayMalloc.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMemSet = _libraries['llvm'].LLVMBuildMemSet - LLVMBuildMemSet.restype = LLVMValueRef - LLVMBuildMemSet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildMemCpy = _libraries['llvm'].LLVMBuildMemCpy - LLVMBuildMemCpy.restype = LLVMValueRef - LLVMBuildMemCpy.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildMemMove = _libraries['llvm'].LLVMBuildMemMove - LLVMBuildMemMove.restype = LLVMValueRef - LLVMBuildMemMove.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAlloca = _libraries['llvm'].LLVMBuildAlloca - LLVMBuildAlloca.restype = LLVMValueRef - LLVMBuildAlloca.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildArrayAlloca = _libraries['llvm'].LLVMBuildArrayAlloca - LLVMBuildArrayAlloca.restype = LLVMValueRef - LLVMBuildArrayAlloca.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFree = _libraries['llvm'].LLVMBuildFree - LLVMBuildFree.restype = LLVMValueRef - LLVMBuildFree.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildLoad = _libraries['llvm'].LLVMBuildLoad - LLVMBuildLoad.restype = LLVMValueRef - LLVMBuildLoad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildLoad2 = _libraries['llvm'].LLVMBuildLoad2 - LLVMBuildLoad2.restype = LLVMValueRef - LLVMBuildLoad2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStore = _libraries['llvm'].LLVMBuildStore - LLVMBuildStore.restype = LLVMValueRef - LLVMBuildStore.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildGEP = _libraries['llvm'].LLVMBuildGEP - LLVMBuildGEP.restype = LLVMValueRef - LLVMBuildGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInBoundsGEP = _libraries['llvm'].LLVMBuildInBoundsGEP - LLVMBuildInBoundsGEP.restype = LLVMValueRef - LLVMBuildInBoundsGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStructGEP = _libraries['llvm'].LLVMBuildStructGEP - LLVMBuildStructGEP.restype = LLVMValueRef - LLVMBuildStructGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGEP2 = _libraries['llvm'].LLVMBuildGEP2 - LLVMBuildGEP2.restype = LLVMValueRef - LLVMBuildGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInBoundsGEP2 = _libraries['llvm'].LLVMBuildInBoundsGEP2 - LLVMBuildInBoundsGEP2.restype = LLVMValueRef - LLVMBuildInBoundsGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStructGEP2 = _libraries['llvm'].LLVMBuildStructGEP2 - LLVMBuildStructGEP2.restype = LLVMValueRef - LLVMBuildStructGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGlobalString = _libraries['llvm'].LLVMBuildGlobalString - LLVMBuildGlobalString.restype = LLVMValueRef - LLVMBuildGlobalString.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGlobalStringPtr = _libraries['llvm'].LLVMBuildGlobalStringPtr - LLVMBuildGlobalStringPtr.restype = LLVMValueRef - LLVMBuildGlobalStringPtr.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetVolatile = _libraries['llvm'].LLVMGetVolatile - LLVMGetVolatile.restype = LLVMBool - LLVMGetVolatile.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetVolatile = _libraries['llvm'].LLVMSetVolatile - LLVMSetVolatile.restype = None - LLVMSetVolatile.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetWeak = _libraries['llvm'].LLVMGetWeak - LLVMGetWeak.restype = LLVMBool - LLVMGetWeak.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetWeak = _libraries['llvm'].LLVMSetWeak - LLVMSetWeak.restype = None - LLVMSetWeak.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetOrdering = _libraries['llvm'].LLVMGetOrdering - LLVMGetOrdering.restype = LLVMAtomicOrdering - LLVMGetOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetOrdering = _libraries['llvm'].LLVMSetOrdering - LLVMSetOrdering.restype = None - LLVMSetOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMGetAtomicRMWBinOp = _libraries['llvm'].LLVMGetAtomicRMWBinOp - LLVMGetAtomicRMWBinOp.restype = LLVMAtomicRMWBinOp - LLVMGetAtomicRMWBinOp.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAtomicRMWBinOp = _libraries['llvm'].LLVMSetAtomicRMWBinOp - LLVMSetAtomicRMWBinOp.restype = None - LLVMSetAtomicRMWBinOp.argtypes = [LLVMValueRef, LLVMAtomicRMWBinOp] -except AttributeError: - pass -try: - LLVMBuildTrunc = _libraries['llvm'].LLVMBuildTrunc - LLVMBuildTrunc.restype = LLVMValueRef - LLVMBuildTrunc.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildZExt = _libraries['llvm'].LLVMBuildZExt - LLVMBuildZExt.restype = LLVMValueRef - LLVMBuildZExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSExt = _libraries['llvm'].LLVMBuildSExt - LLVMBuildSExt.restype = LLVMValueRef - LLVMBuildSExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPToUI = _libraries['llvm'].LLVMBuildFPToUI - LLVMBuildFPToUI.restype = LLVMValueRef - LLVMBuildFPToUI.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPToSI = _libraries['llvm'].LLVMBuildFPToSI - LLVMBuildFPToSI.restype = LLVMValueRef - LLVMBuildFPToSI.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUIToFP = _libraries['llvm'].LLVMBuildUIToFP - LLVMBuildUIToFP.restype = LLVMValueRef - LLVMBuildUIToFP.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSIToFP = _libraries['llvm'].LLVMBuildSIToFP - LLVMBuildSIToFP.restype = LLVMValueRef - LLVMBuildSIToFP.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPTrunc = _libraries['llvm'].LLVMBuildFPTrunc - LLVMBuildFPTrunc.restype = LLVMValueRef - LLVMBuildFPTrunc.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPExt = _libraries['llvm'].LLVMBuildFPExt - LLVMBuildFPExt.restype = LLVMValueRef - LLVMBuildFPExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrToInt = _libraries['llvm'].LLVMBuildPtrToInt - LLVMBuildPtrToInt.restype = LLVMValueRef - LLVMBuildPtrToInt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntToPtr = _libraries['llvm'].LLVMBuildIntToPtr - LLVMBuildIntToPtr.restype = LLVMValueRef - LLVMBuildIntToPtr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildBitCast = _libraries['llvm'].LLVMBuildBitCast - LLVMBuildBitCast.restype = LLVMValueRef - LLVMBuildBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAddrSpaceCast = _libraries['llvm'].LLVMBuildAddrSpaceCast - LLVMBuildAddrSpaceCast.restype = LLVMValueRef - LLVMBuildAddrSpaceCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildZExtOrBitCast = _libraries['llvm'].LLVMBuildZExtOrBitCast - LLVMBuildZExtOrBitCast.restype = LLVMValueRef - LLVMBuildZExtOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSExtOrBitCast = _libraries['llvm'].LLVMBuildSExtOrBitCast - LLVMBuildSExtOrBitCast.restype = LLVMValueRef - LLVMBuildSExtOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildTruncOrBitCast = _libraries['llvm'].LLVMBuildTruncOrBitCast - LLVMBuildTruncOrBitCast.restype = LLVMValueRef - LLVMBuildTruncOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCast = _libraries['llvm'].LLVMBuildCast - LLVMBuildCast.restype = LLVMValueRef - LLVMBuildCast.argtypes = [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPointerCast = _libraries['llvm'].LLVMBuildPointerCast - LLVMBuildPointerCast.restype = LLVMValueRef - LLVMBuildPointerCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntCast2 = _libraries['llvm'].LLVMBuildIntCast2 - LLVMBuildIntCast2.restype = LLVMValueRef - LLVMBuildIntCast2.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, LLVMBool, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPCast = _libraries['llvm'].LLVMBuildFPCast - LLVMBuildFPCast.restype = LLVMValueRef - LLVMBuildFPCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntCast = _libraries['llvm'].LLVMBuildIntCast - LLVMBuildIntCast.restype = LLVMValueRef - LLVMBuildIntCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildICmp = _libraries['llvm'].LLVMBuildICmp - LLVMBuildICmp.restype = LLVMValueRef - LLVMBuildICmp.argtypes = [LLVMBuilderRef, LLVMIntPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFCmp = _libraries['llvm'].LLVMBuildFCmp - LLVMBuildFCmp.restype = LLVMValueRef - LLVMBuildFCmp.argtypes = [LLVMBuilderRef, LLVMRealPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPhi = _libraries['llvm'].LLVMBuildPhi - LLVMBuildPhi.restype = LLVMValueRef - LLVMBuildPhi.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCall = _libraries['llvm'].LLVMBuildCall - LLVMBuildCall.restype = LLVMValueRef - LLVMBuildCall.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCall2 = _libraries['llvm'].LLVMBuildCall2 - LLVMBuildCall2.restype = LLVMValueRef - LLVMBuildCall2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSelect = _libraries['llvm'].LLVMBuildSelect - LLVMBuildSelect.restype = LLVMValueRef - LLVMBuildSelect.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildVAArg = _libraries['llvm'].LLVMBuildVAArg - LLVMBuildVAArg.restype = LLVMValueRef - LLVMBuildVAArg.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExtractElement = _libraries['llvm'].LLVMBuildExtractElement - LLVMBuildExtractElement.restype = LLVMValueRef - LLVMBuildExtractElement.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInsertElement = _libraries['llvm'].LLVMBuildInsertElement - LLVMBuildInsertElement.restype = LLVMValueRef - LLVMBuildInsertElement.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildShuffleVector = _libraries['llvm'].LLVMBuildShuffleVector - LLVMBuildShuffleVector.restype = LLVMValueRef - LLVMBuildShuffleVector.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExtractValue = _libraries['llvm'].LLVMBuildExtractValue - LLVMBuildExtractValue.restype = LLVMValueRef - LLVMBuildExtractValue.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInsertValue = _libraries['llvm'].LLVMBuildInsertValue - LLVMBuildInsertValue.restype = LLVMValueRef - LLVMBuildInsertValue.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFreeze = _libraries['llvm'].LLVMBuildFreeze - LLVMBuildFreeze.restype = LLVMValueRef - LLVMBuildFreeze.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIsNull = _libraries['llvm'].LLVMBuildIsNull - LLVMBuildIsNull.restype = LLVMValueRef - LLVMBuildIsNull.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIsNotNull = _libraries['llvm'].LLVMBuildIsNotNull - LLVMBuildIsNotNull.restype = LLVMValueRef - LLVMBuildIsNotNull.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrDiff = _libraries['llvm'].LLVMBuildPtrDiff - LLVMBuildPtrDiff.restype = LLVMValueRef - LLVMBuildPtrDiff.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrDiff2 = _libraries['llvm'].LLVMBuildPtrDiff2 - LLVMBuildPtrDiff2.restype = LLVMValueRef - LLVMBuildPtrDiff2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFence = _libraries['llvm'].LLVMBuildFence - LLVMBuildFence.restype = LLVMValueRef - LLVMBuildFence.argtypes = [LLVMBuilderRef, LLVMAtomicOrdering, LLVMBool, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAtomicRMW = _libraries['llvm'].LLVMBuildAtomicRMW - LLVMBuildAtomicRMW.restype = LLVMValueRef - LLVMBuildAtomicRMW.argtypes = [LLVMBuilderRef, LLVMAtomicRMWBinOp, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMBool] -except AttributeError: - pass -try: - LLVMBuildAtomicCmpXchg = _libraries['llvm'].LLVMBuildAtomicCmpXchg - LLVMBuildAtomicCmpXchg.restype = LLVMValueRef - LLVMBuildAtomicCmpXchg.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMAtomicOrdering, LLVMBool] -except AttributeError: - pass -try: - LLVMGetNumMaskElements = _libraries['llvm'].LLVMGetNumMaskElements - LLVMGetNumMaskElements.restype = ctypes.c_uint32 - LLVMGetNumMaskElements.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetUndefMaskElem = _libraries['llvm'].LLVMGetUndefMaskElem - LLVMGetUndefMaskElem.restype = ctypes.c_int32 - LLVMGetUndefMaskElem.argtypes = [] -except AttributeError: - pass -try: - LLVMGetMaskValue = _libraries['llvm'].LLVMGetMaskValue - LLVMGetMaskValue.restype = ctypes.c_int32 - LLVMGetMaskValue.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIsAtomicSingleThread = _libraries['llvm'].LLVMIsAtomicSingleThread - LLVMIsAtomicSingleThread.restype = LLVMBool - LLVMIsAtomicSingleThread.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAtomicSingleThread = _libraries['llvm'].LLVMSetAtomicSingleThread - LLVMSetAtomicSingleThread.restype = None - LLVMSetAtomicSingleThread.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetCmpXchgSuccessOrdering = _libraries['llvm'].LLVMGetCmpXchgSuccessOrdering - LLVMGetCmpXchgSuccessOrdering.restype = LLVMAtomicOrdering - LLVMGetCmpXchgSuccessOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCmpXchgSuccessOrdering = _libraries['llvm'].LLVMSetCmpXchgSuccessOrdering - LLVMSetCmpXchgSuccessOrdering.restype = None - LLVMSetCmpXchgSuccessOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMGetCmpXchgFailureOrdering = _libraries['llvm'].LLVMGetCmpXchgFailureOrdering - LLVMGetCmpXchgFailureOrdering.restype = LLVMAtomicOrdering - LLVMGetCmpXchgFailureOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCmpXchgFailureOrdering = _libraries['llvm'].LLVMSetCmpXchgFailureOrdering - LLVMSetCmpXchgFailureOrdering.restype = None - LLVMSetCmpXchgFailureOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMCreateModuleProviderForExistingModule = _libraries['llvm'].LLVMCreateModuleProviderForExistingModule - LLVMCreateModuleProviderForExistingModule.restype = LLVMModuleProviderRef - LLVMCreateModuleProviderForExistingModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeModuleProvider = _libraries['llvm'].LLVMDisposeModuleProvider - LLVMDisposeModuleProvider.restype = None - LLVMDisposeModuleProvider.argtypes = [LLVMModuleProviderRef] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithContentsOfFile = _libraries['llvm'].LLVMCreateMemoryBufferWithContentsOfFile - LLVMCreateMemoryBufferWithContentsOfFile.restype = LLVMBool - LLVMCreateMemoryBufferWithContentsOfFile.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithSTDIN = _libraries['llvm'].LLVMCreateMemoryBufferWithSTDIN - LLVMCreateMemoryBufferWithSTDIN.restype = LLVMBool - LLVMCreateMemoryBufferWithSTDIN.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithMemoryRange = _libraries['llvm'].LLVMCreateMemoryBufferWithMemoryRange - LLVMCreateMemoryBufferWithMemoryRange.restype = LLVMMemoryBufferRef - LLVMCreateMemoryBufferWithMemoryRange.argtypes = [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), LLVMBool] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithMemoryRangeCopy = _libraries['llvm'].LLVMCreateMemoryBufferWithMemoryRangeCopy - LLVMCreateMemoryBufferWithMemoryRangeCopy.restype = LLVMMemoryBufferRef - LLVMCreateMemoryBufferWithMemoryRangeCopy.argtypes = [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetBufferStart = _libraries['llvm'].LLVMGetBufferStart - LLVMGetBufferStart.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetBufferStart.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMGetBufferSize = _libraries['llvm'].LLVMGetBufferSize - LLVMGetBufferSize.restype = size_t - LLVMGetBufferSize.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMDisposeMemoryBuffer = _libraries['llvm'].LLVMDisposeMemoryBuffer - LLVMDisposeMemoryBuffer.restype = None - LLVMDisposeMemoryBuffer.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMGetGlobalPassRegistry = _libraries['llvm'].LLVMGetGlobalPassRegistry - LLVMGetGlobalPassRegistry.restype = LLVMPassRegistryRef - LLVMGetGlobalPassRegistry.argtypes = [] -except AttributeError: - pass -try: - LLVMCreatePassManager = _libraries['llvm'].LLVMCreatePassManager - LLVMCreatePassManager.restype = LLVMPassManagerRef - LLVMCreatePassManager.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateFunctionPassManagerForModule = _libraries['llvm'].LLVMCreateFunctionPassManagerForModule - LLVMCreateFunctionPassManagerForModule.restype = LLVMPassManagerRef - LLVMCreateFunctionPassManagerForModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateFunctionPassManager = _libraries['llvm'].LLVMCreateFunctionPassManager - LLVMCreateFunctionPassManager.restype = LLVMPassManagerRef - LLVMCreateFunctionPassManager.argtypes = [LLVMModuleProviderRef] -except AttributeError: - pass -try: - LLVMRunPassManager = _libraries['llvm'].LLVMRunPassManager - LLVMRunPassManager.restype = LLVMBool - LLVMRunPassManager.argtypes = [LLVMPassManagerRef, LLVMModuleRef] -except AttributeError: - pass -try: - LLVMInitializeFunctionPassManager = _libraries['llvm'].LLVMInitializeFunctionPassManager - LLVMInitializeFunctionPassManager.restype = LLVMBool - LLVMInitializeFunctionPassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMRunFunctionPassManager = _libraries['llvm'].LLVMRunFunctionPassManager - LLVMRunFunctionPassManager.restype = LLVMBool - LLVMRunFunctionPassManager.argtypes = [LLVMPassManagerRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMFinalizeFunctionPassManager = _libraries['llvm'].LLVMFinalizeFunctionPassManager - LLVMFinalizeFunctionPassManager.restype = LLVMBool - LLVMFinalizeFunctionPassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMDisposePassManager = _libraries['llvm'].LLVMDisposePassManager - LLVMDisposePassManager.restype = None - LLVMDisposePassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMStartMultithreaded = _libraries['llvm'].LLVMStartMultithreaded - LLVMStartMultithreaded.restype = LLVMBool - LLVMStartMultithreaded.argtypes = [] -except AttributeError: - pass -try: - LLVMStopMultithreaded = _libraries['llvm'].LLVMStopMultithreaded - LLVMStopMultithreaded.restype = None - LLVMStopMultithreaded.argtypes = [] -except AttributeError: - pass -try: - LLVMIsMultithreaded = _libraries['llvm'].LLVMIsMultithreaded - LLVMIsMultithreaded.restype = LLVMBool - LLVMIsMultithreaded.argtypes = [] -except AttributeError: - pass -LLVM_C_DEBUGINFO_H = True # macro - -# values for enumeration 'c__EA_LLVMDIFlags' -c__EA_LLVMDIFlags__enumvalues = { - 0: 'LLVMDIFlagZero', - 1: 'LLVMDIFlagPrivate', - 2: 'LLVMDIFlagProtected', - 3: 'LLVMDIFlagPublic', - 4: 'LLVMDIFlagFwdDecl', - 8: 'LLVMDIFlagAppleBlock', - 16: 'LLVMDIFlagReservedBit4', - 32: 'LLVMDIFlagVirtual', - 64: 'LLVMDIFlagArtificial', - 128: 'LLVMDIFlagExplicit', - 256: 'LLVMDIFlagPrototyped', - 512: 'LLVMDIFlagObjcClassComplete', - 1024: 'LLVMDIFlagObjectPointer', - 2048: 'LLVMDIFlagVector', - 4096: 'LLVMDIFlagStaticMember', - 8192: 'LLVMDIFlagLValueReference', - 16384: 'LLVMDIFlagRValueReference', - 32768: 'LLVMDIFlagReserved', - 65536: 'LLVMDIFlagSingleInheritance', - 131072: 'LLVMDIFlagMultipleInheritance', - 196608: 'LLVMDIFlagVirtualInheritance', - 262144: 'LLVMDIFlagIntroducedVirtual', - 524288: 'LLVMDIFlagBitField', - 1048576: 'LLVMDIFlagNoReturn', - 4194304: 'LLVMDIFlagTypePassByValue', - 8388608: 'LLVMDIFlagTypePassByReference', - 16777216: 'LLVMDIFlagEnumClass', - 16777216: 'LLVMDIFlagFixedEnum', - 33554432: 'LLVMDIFlagThunk', - 67108864: 'LLVMDIFlagNonTrivial', - 134217728: 'LLVMDIFlagBigEndian', - 268435456: 'LLVMDIFlagLittleEndian', - 36: 'LLVMDIFlagIndirectVirtualBase', - 3: 'LLVMDIFlagAccessibility', - 196608: 'LLVMDIFlagPtrToMemberRep', -} -LLVMDIFlagZero = 0 -LLVMDIFlagPrivate = 1 -LLVMDIFlagProtected = 2 -LLVMDIFlagPublic = 3 -LLVMDIFlagFwdDecl = 4 -LLVMDIFlagAppleBlock = 8 -LLVMDIFlagReservedBit4 = 16 -LLVMDIFlagVirtual = 32 -LLVMDIFlagArtificial = 64 -LLVMDIFlagExplicit = 128 -LLVMDIFlagPrototyped = 256 -LLVMDIFlagObjcClassComplete = 512 -LLVMDIFlagObjectPointer = 1024 -LLVMDIFlagVector = 2048 -LLVMDIFlagStaticMember = 4096 -LLVMDIFlagLValueReference = 8192 -LLVMDIFlagRValueReference = 16384 -LLVMDIFlagReserved = 32768 -LLVMDIFlagSingleInheritance = 65536 -LLVMDIFlagMultipleInheritance = 131072 -LLVMDIFlagVirtualInheritance = 196608 -LLVMDIFlagIntroducedVirtual = 262144 -LLVMDIFlagBitField = 524288 -LLVMDIFlagNoReturn = 1048576 -LLVMDIFlagTypePassByValue = 4194304 -LLVMDIFlagTypePassByReference = 8388608 -LLVMDIFlagEnumClass = 16777216 -LLVMDIFlagFixedEnum = 16777216 -LLVMDIFlagThunk = 33554432 -LLVMDIFlagNonTrivial = 67108864 -LLVMDIFlagBigEndian = 134217728 -LLVMDIFlagLittleEndian = 268435456 -LLVMDIFlagIndirectVirtualBase = 36 -LLVMDIFlagAccessibility = 3 -LLVMDIFlagPtrToMemberRep = 196608 -c__EA_LLVMDIFlags = ctypes.c_uint32 # enum -LLVMDIFlags = c__EA_LLVMDIFlags -LLVMDIFlags__enumvalues = c__EA_LLVMDIFlags__enumvalues - -# values for enumeration 'c__EA_LLVMDWARFSourceLanguage' -c__EA_LLVMDWARFSourceLanguage__enumvalues = { - 0: 'LLVMDWARFSourceLanguageC89', - 1: 'LLVMDWARFSourceLanguageC', - 2: 'LLVMDWARFSourceLanguageAda83', - 3: 'LLVMDWARFSourceLanguageC_plus_plus', - 4: 'LLVMDWARFSourceLanguageCobol74', - 5: 'LLVMDWARFSourceLanguageCobol85', - 6: 'LLVMDWARFSourceLanguageFortran77', - 7: 'LLVMDWARFSourceLanguageFortran90', - 8: 'LLVMDWARFSourceLanguagePascal83', - 9: 'LLVMDWARFSourceLanguageModula2', - 10: 'LLVMDWARFSourceLanguageJava', - 11: 'LLVMDWARFSourceLanguageC99', - 12: 'LLVMDWARFSourceLanguageAda95', - 13: 'LLVMDWARFSourceLanguageFortran95', - 14: 'LLVMDWARFSourceLanguagePLI', - 15: 'LLVMDWARFSourceLanguageObjC', - 16: 'LLVMDWARFSourceLanguageObjC_plus_plus', - 17: 'LLVMDWARFSourceLanguageUPC', - 18: 'LLVMDWARFSourceLanguageD', - 19: 'LLVMDWARFSourceLanguagePython', - 20: 'LLVMDWARFSourceLanguageOpenCL', - 21: 'LLVMDWARFSourceLanguageGo', - 22: 'LLVMDWARFSourceLanguageModula3', - 23: 'LLVMDWARFSourceLanguageHaskell', - 24: 'LLVMDWARFSourceLanguageC_plus_plus_03', - 25: 'LLVMDWARFSourceLanguageC_plus_plus_11', - 26: 'LLVMDWARFSourceLanguageOCaml', - 27: 'LLVMDWARFSourceLanguageRust', - 28: 'LLVMDWARFSourceLanguageC11', - 29: 'LLVMDWARFSourceLanguageSwift', - 30: 'LLVMDWARFSourceLanguageJulia', - 31: 'LLVMDWARFSourceLanguageDylan', - 32: 'LLVMDWARFSourceLanguageC_plus_plus_14', - 33: 'LLVMDWARFSourceLanguageFortran03', - 34: 'LLVMDWARFSourceLanguageFortran08', - 35: 'LLVMDWARFSourceLanguageRenderScript', - 36: 'LLVMDWARFSourceLanguageBLISS', - 37: 'LLVMDWARFSourceLanguageMips_Assembler', - 38: 'LLVMDWARFSourceLanguageGOOGLE_RenderScript', - 39: 'LLVMDWARFSourceLanguageBORLAND_Delphi', -} -LLVMDWARFSourceLanguageC89 = 0 -LLVMDWARFSourceLanguageC = 1 -LLVMDWARFSourceLanguageAda83 = 2 -LLVMDWARFSourceLanguageC_plus_plus = 3 -LLVMDWARFSourceLanguageCobol74 = 4 -LLVMDWARFSourceLanguageCobol85 = 5 -LLVMDWARFSourceLanguageFortran77 = 6 -LLVMDWARFSourceLanguageFortran90 = 7 -LLVMDWARFSourceLanguagePascal83 = 8 -LLVMDWARFSourceLanguageModula2 = 9 -LLVMDWARFSourceLanguageJava = 10 -LLVMDWARFSourceLanguageC99 = 11 -LLVMDWARFSourceLanguageAda95 = 12 -LLVMDWARFSourceLanguageFortran95 = 13 -LLVMDWARFSourceLanguagePLI = 14 -LLVMDWARFSourceLanguageObjC = 15 -LLVMDWARFSourceLanguageObjC_plus_plus = 16 -LLVMDWARFSourceLanguageUPC = 17 -LLVMDWARFSourceLanguageD = 18 -LLVMDWARFSourceLanguagePython = 19 -LLVMDWARFSourceLanguageOpenCL = 20 -LLVMDWARFSourceLanguageGo = 21 -LLVMDWARFSourceLanguageModula3 = 22 -LLVMDWARFSourceLanguageHaskell = 23 -LLVMDWARFSourceLanguageC_plus_plus_03 = 24 -LLVMDWARFSourceLanguageC_plus_plus_11 = 25 -LLVMDWARFSourceLanguageOCaml = 26 -LLVMDWARFSourceLanguageRust = 27 -LLVMDWARFSourceLanguageC11 = 28 -LLVMDWARFSourceLanguageSwift = 29 -LLVMDWARFSourceLanguageJulia = 30 -LLVMDWARFSourceLanguageDylan = 31 -LLVMDWARFSourceLanguageC_plus_plus_14 = 32 -LLVMDWARFSourceLanguageFortran03 = 33 -LLVMDWARFSourceLanguageFortran08 = 34 -LLVMDWARFSourceLanguageRenderScript = 35 -LLVMDWARFSourceLanguageBLISS = 36 -LLVMDWARFSourceLanguageMips_Assembler = 37 -LLVMDWARFSourceLanguageGOOGLE_RenderScript = 38 -LLVMDWARFSourceLanguageBORLAND_Delphi = 39 -c__EA_LLVMDWARFSourceLanguage = ctypes.c_uint32 # enum -LLVMDWARFSourceLanguage = c__EA_LLVMDWARFSourceLanguage -LLVMDWARFSourceLanguage__enumvalues = c__EA_LLVMDWARFSourceLanguage__enumvalues - -# values for enumeration 'c__EA_LLVMDWARFEmissionKind' -c__EA_LLVMDWARFEmissionKind__enumvalues = { - 0: 'LLVMDWARFEmissionNone', - 1: 'LLVMDWARFEmissionFull', - 2: 'LLVMDWARFEmissionLineTablesOnly', -} -LLVMDWARFEmissionNone = 0 -LLVMDWARFEmissionFull = 1 -LLVMDWARFEmissionLineTablesOnly = 2 -c__EA_LLVMDWARFEmissionKind = ctypes.c_uint32 # enum -LLVMDWARFEmissionKind = c__EA_LLVMDWARFEmissionKind -LLVMDWARFEmissionKind__enumvalues = c__EA_LLVMDWARFEmissionKind__enumvalues - -# values for enumeration 'c__Ea_LLVMMDStringMetadataKind' -c__Ea_LLVMMDStringMetadataKind__enumvalues = { - 0: 'LLVMMDStringMetadataKind', - 1: 'LLVMConstantAsMetadataMetadataKind', - 2: 'LLVMLocalAsMetadataMetadataKind', - 3: 'LLVMDistinctMDOperandPlaceholderMetadataKind', - 4: 'LLVMMDTupleMetadataKind', - 5: 'LLVMDILocationMetadataKind', - 6: 'LLVMDIExpressionMetadataKind', - 7: 'LLVMDIGlobalVariableExpressionMetadataKind', - 8: 'LLVMGenericDINodeMetadataKind', - 9: 'LLVMDISubrangeMetadataKind', - 10: 'LLVMDIEnumeratorMetadataKind', - 11: 'LLVMDIBasicTypeMetadataKind', - 12: 'LLVMDIDerivedTypeMetadataKind', - 13: 'LLVMDICompositeTypeMetadataKind', - 14: 'LLVMDISubroutineTypeMetadataKind', - 15: 'LLVMDIFileMetadataKind', - 16: 'LLVMDICompileUnitMetadataKind', - 17: 'LLVMDISubprogramMetadataKind', - 18: 'LLVMDILexicalBlockMetadataKind', - 19: 'LLVMDILexicalBlockFileMetadataKind', - 20: 'LLVMDINamespaceMetadataKind', - 21: 'LLVMDIModuleMetadataKind', - 22: 'LLVMDITemplateTypeParameterMetadataKind', - 23: 'LLVMDITemplateValueParameterMetadataKind', - 24: 'LLVMDIGlobalVariableMetadataKind', - 25: 'LLVMDILocalVariableMetadataKind', - 26: 'LLVMDILabelMetadataKind', - 27: 'LLVMDIObjCPropertyMetadataKind', - 28: 'LLVMDIImportedEntityMetadataKind', - 29: 'LLVMDIMacroMetadataKind', - 30: 'LLVMDIMacroFileMetadataKind', - 31: 'LLVMDICommonBlockMetadataKind', - 32: 'LLVMDIStringTypeMetadataKind', - 33: 'LLVMDIGenericSubrangeMetadataKind', - 34: 'LLVMDIArgListMetadataKind', -} -LLVMMDStringMetadataKind = 0 -LLVMConstantAsMetadataMetadataKind = 1 -LLVMLocalAsMetadataMetadataKind = 2 -LLVMDistinctMDOperandPlaceholderMetadataKind = 3 -LLVMMDTupleMetadataKind = 4 -LLVMDILocationMetadataKind = 5 -LLVMDIExpressionMetadataKind = 6 -LLVMDIGlobalVariableExpressionMetadataKind = 7 -LLVMGenericDINodeMetadataKind = 8 -LLVMDISubrangeMetadataKind = 9 -LLVMDIEnumeratorMetadataKind = 10 -LLVMDIBasicTypeMetadataKind = 11 -LLVMDIDerivedTypeMetadataKind = 12 -LLVMDICompositeTypeMetadataKind = 13 -LLVMDISubroutineTypeMetadataKind = 14 -LLVMDIFileMetadataKind = 15 -LLVMDICompileUnitMetadataKind = 16 -LLVMDISubprogramMetadataKind = 17 -LLVMDILexicalBlockMetadataKind = 18 -LLVMDILexicalBlockFileMetadataKind = 19 -LLVMDINamespaceMetadataKind = 20 -LLVMDIModuleMetadataKind = 21 -LLVMDITemplateTypeParameterMetadataKind = 22 -LLVMDITemplateValueParameterMetadataKind = 23 -LLVMDIGlobalVariableMetadataKind = 24 -LLVMDILocalVariableMetadataKind = 25 -LLVMDILabelMetadataKind = 26 -LLVMDIObjCPropertyMetadataKind = 27 -LLVMDIImportedEntityMetadataKind = 28 -LLVMDIMacroMetadataKind = 29 -LLVMDIMacroFileMetadataKind = 30 -LLVMDICommonBlockMetadataKind = 31 -LLVMDIStringTypeMetadataKind = 32 -LLVMDIGenericSubrangeMetadataKind = 33 -LLVMDIArgListMetadataKind = 34 -c__Ea_LLVMMDStringMetadataKind = ctypes.c_uint32 # enum -LLVMMetadataKind = ctypes.c_uint32 -LLVMDWARFTypeEncoding = ctypes.c_uint32 - -# values for enumeration 'c__EA_LLVMDWARFMacinfoRecordType' -c__EA_LLVMDWARFMacinfoRecordType__enumvalues = { - 1: 'LLVMDWARFMacinfoRecordTypeDefine', - 2: 'LLVMDWARFMacinfoRecordTypeMacro', - 3: 'LLVMDWARFMacinfoRecordTypeStartFile', - 4: 'LLVMDWARFMacinfoRecordTypeEndFile', - 255: 'LLVMDWARFMacinfoRecordTypeVendorExt', -} -LLVMDWARFMacinfoRecordTypeDefine = 1 -LLVMDWARFMacinfoRecordTypeMacro = 2 -LLVMDWARFMacinfoRecordTypeStartFile = 3 -LLVMDWARFMacinfoRecordTypeEndFile = 4 -LLVMDWARFMacinfoRecordTypeVendorExt = 255 -c__EA_LLVMDWARFMacinfoRecordType = ctypes.c_uint32 # enum -LLVMDWARFMacinfoRecordType = c__EA_LLVMDWARFMacinfoRecordType -LLVMDWARFMacinfoRecordType__enumvalues = c__EA_LLVMDWARFMacinfoRecordType__enumvalues -try: - LLVMDebugMetadataVersion = _libraries['llvm'].LLVMDebugMetadataVersion - LLVMDebugMetadataVersion.restype = ctypes.c_uint32 - LLVMDebugMetadataVersion.argtypes = [] -except AttributeError: - pass -try: - LLVMGetModuleDebugMetadataVersion = _libraries['llvm'].LLVMGetModuleDebugMetadataVersion - LLVMGetModuleDebugMetadataVersion.restype = ctypes.c_uint32 - LLVMGetModuleDebugMetadataVersion.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMStripModuleDebugInfo = _libraries['llvm'].LLVMStripModuleDebugInfo - LLVMStripModuleDebugInfo.restype = LLVMBool - LLVMStripModuleDebugInfo.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateDIBuilderDisallowUnresolved = _libraries['llvm'].LLVMCreateDIBuilderDisallowUnresolved - LLVMCreateDIBuilderDisallowUnresolved.restype = LLVMDIBuilderRef - LLVMCreateDIBuilderDisallowUnresolved.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateDIBuilder = _libraries['llvm'].LLVMCreateDIBuilder - LLVMCreateDIBuilder.restype = LLVMDIBuilderRef - LLVMCreateDIBuilder.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeDIBuilder = _libraries['llvm'].LLVMDisposeDIBuilder - LLVMDisposeDIBuilder.restype = None - LLVMDisposeDIBuilder.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderFinalize = _libraries['llvm'].LLVMDIBuilderFinalize - LLVMDIBuilderFinalize.restype = None - LLVMDIBuilderFinalize.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderFinalizeSubprogram = _libraries['llvm'].LLVMDIBuilderFinalizeSubprogram - LLVMDIBuilderFinalizeSubprogram.restype = None - LLVMDIBuilderFinalizeSubprogram.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateCompileUnit = _libraries['llvm'].LLVMDIBuilderCreateCompileUnit - LLVMDIBuilderCreateCompileUnit.restype = LLVMMetadataRef - LLVMDIBuilderCreateCompileUnit.argtypes = [LLVMDIBuilderRef, LLVMDWARFSourceLanguage, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMDWARFEmissionKind, ctypes.c_uint32, LLVMBool, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateFile = _libraries['llvm'].LLVMDIBuilderCreateFile - LLVMDIBuilderCreateFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateFile.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateModule = _libraries['llvm'].LLVMDIBuilderCreateModule - LLVMDIBuilderCreateModule.restype = LLVMMetadataRef - LLVMDIBuilderCreateModule.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateNameSpace = _libraries['llvm'].LLVMDIBuilderCreateNameSpace - LLVMDIBuilderCreateNameSpace.restype = LLVMMetadataRef - LLVMDIBuilderCreateNameSpace.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool] -except AttributeError: - pass -try: - LLVMDIBuilderCreateFunction = _libraries['llvm'].LLVMDIBuilderCreateFunction - LLVMDIBuilderCreateFunction.restype = LLVMMetadataRef - LLVMDIBuilderCreateFunction.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMBool, ctypes.c_uint32, LLVMDIFlags, LLVMBool] -except AttributeError: - pass -try: - LLVMDIBuilderCreateLexicalBlock = _libraries['llvm'].LLVMDIBuilderCreateLexicalBlock - LLVMDIBuilderCreateLexicalBlock.restype = LLVMMetadataRef - LLVMDIBuilderCreateLexicalBlock.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateLexicalBlockFile = _libraries['llvm'].LLVMDIBuilderCreateLexicalBlockFile - LLVMDIBuilderCreateLexicalBlockFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateLexicalBlockFile.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromNamespace = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromNamespace - LLVMDIBuilderCreateImportedModuleFromNamespace.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromNamespace.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromAlias = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromAlias - LLVMDIBuilderCreateImportedModuleFromAlias.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromAlias.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromModule = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromModule - LLVMDIBuilderCreateImportedModuleFromModule.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromModule.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedDeclaration = _libraries['llvm'].LLVMDIBuilderCreateImportedDeclaration - LLVMDIBuilderCreateImportedDeclaration.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedDeclaration.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateDebugLocation = _libraries['llvm'].LLVMDIBuilderCreateDebugLocation - LLVMDIBuilderCreateDebugLocation.restype = LLVMMetadataRef - LLVMDIBuilderCreateDebugLocation.argtypes = [LLVMContextRef, ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetLine = _libraries['llvm'].LLVMDILocationGetLine - LLVMDILocationGetLine.restype = ctypes.c_uint32 - LLVMDILocationGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetColumn = _libraries['llvm'].LLVMDILocationGetColumn - LLVMDILocationGetColumn.restype = ctypes.c_uint32 - LLVMDILocationGetColumn.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetScope = _libraries['llvm'].LLVMDILocationGetScope - LLVMDILocationGetScope.restype = LLVMMetadataRef - LLVMDILocationGetScope.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetInlinedAt = _libraries['llvm'].LLVMDILocationGetInlinedAt - LLVMDILocationGetInlinedAt.restype = LLVMMetadataRef - LLVMDILocationGetInlinedAt.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIScopeGetFile = _libraries['llvm'].LLVMDIScopeGetFile - LLVMDIScopeGetFile.restype = LLVMMetadataRef - LLVMDIScopeGetFile.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIFileGetDirectory = _libraries['llvm'].LLVMDIFileGetDirectory - LLVMDIFileGetDirectory.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetDirectory.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIFileGetFilename = _libraries['llvm'].LLVMDIFileGetFilename - LLVMDIFileGetFilename.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetFilename.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIFileGetSource = _libraries['llvm'].LLVMDIFileGetSource - LLVMDIFileGetSource.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetSource.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateTypeArray = _libraries['llvm'].LLVMDIBuilderGetOrCreateTypeArray - LLVMDIBuilderGetOrCreateTypeArray.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateTypeArray.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateSubroutineType = _libraries['llvm'].LLVMDIBuilderCreateSubroutineType - LLVMDIBuilderCreateSubroutineType.restype = LLVMMetadataRef - LLVMDIBuilderCreateSubroutineType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMacro = _libraries['llvm'].LLVMDIBuilderCreateMacro - LLVMDIBuilderCreateMacro.restype = LLVMMetadataRef - LLVMDIBuilderCreateMacro.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMDWARFMacinfoRecordType, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTempMacroFile = _libraries['llvm'].LLVMDIBuilderCreateTempMacroFile - LLVMDIBuilderCreateTempMacroFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateTempMacroFile.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -int64_t = ctypes.c_int64 -try: - LLVMDIBuilderCreateEnumerator = _libraries['llvm'].LLVMDIBuilderCreateEnumerator - LLVMDIBuilderCreateEnumerator.restype = LLVMMetadataRef - LLVMDIBuilderCreateEnumerator.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, int64_t, LLVMBool] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - LLVMDIBuilderCreateEnumerationType = _libraries['llvm'].LLVMDIBuilderCreateEnumerationType - LLVMDIBuilderCreateEnumerationType.restype = LLVMMetadataRef - LLVMDIBuilderCreateEnumerationType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateUnionType = _libraries['llvm'].LLVMDIBuilderCreateUnionType - LLVMDIBuilderCreateUnionType.restype = LLVMMetadataRef - LLVMDIBuilderCreateUnionType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateArrayType = _libraries['llvm'].LLVMDIBuilderCreateArrayType - LLVMDIBuilderCreateArrayType.restype = LLVMMetadataRef - LLVMDIBuilderCreateArrayType.argtypes = [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateVectorType = _libraries['llvm'].LLVMDIBuilderCreateVectorType - LLVMDIBuilderCreateVectorType.restype = LLVMMetadataRef - LLVMDIBuilderCreateVectorType.argtypes = [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateUnspecifiedType = _libraries['llvm'].LLVMDIBuilderCreateUnspecifiedType - LLVMDIBuilderCreateUnspecifiedType.restype = LLVMMetadataRef - LLVMDIBuilderCreateUnspecifiedType.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateBasicType = _libraries['llvm'].LLVMDIBuilderCreateBasicType - LLVMDIBuilderCreateBasicType.restype = LLVMMetadataRef - LLVMDIBuilderCreateBasicType.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, uint64_t, LLVMDWARFTypeEncoding, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreatePointerType = _libraries['llvm'].LLVMDIBuilderCreatePointerType - LLVMDIBuilderCreatePointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreatePointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, uint64_t, uint32_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateStructType = _libraries['llvm'].LLVMDIBuilderCreateStructType - LLVMDIBuilderCreateStructType.restype = LLVMMetadataRef - LLVMDIBuilderCreateStructType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMemberType = _libraries['llvm'].LLVMDIBuilderCreateMemberType - LLVMDIBuilderCreateMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateStaticMemberType = _libraries['llvm'].LLVMDIBuilderCreateStaticMemberType - LLVMDIBuilderCreateStaticMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateStaticMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMDIFlags, LLVMValueRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMemberPointerType = _libraries['llvm'].LLVMDIBuilderCreateMemberPointerType - LLVMDIBuilderCreateMemberPointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreateMemberPointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjCIVar = _libraries['llvm'].LLVMDIBuilderCreateObjCIVar - LLVMDIBuilderCreateObjCIVar.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjCIVar.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjCProperty = _libraries['llvm'].LLVMDIBuilderCreateObjCProperty - LLVMDIBuilderCreateObjCProperty.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjCProperty.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjectPointerType = _libraries['llvm'].LLVMDIBuilderCreateObjectPointerType - LLVMDIBuilderCreateObjectPointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjectPointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateQualifiedType = _libraries['llvm'].LLVMDIBuilderCreateQualifiedType - LLVMDIBuilderCreateQualifiedType.restype = LLVMMetadataRef - LLVMDIBuilderCreateQualifiedType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateReferenceType = _libraries['llvm'].LLVMDIBuilderCreateReferenceType - LLVMDIBuilderCreateReferenceType.restype = LLVMMetadataRef - LLVMDIBuilderCreateReferenceType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateNullPtrType = _libraries['llvm'].LLVMDIBuilderCreateNullPtrType - LLVMDIBuilderCreateNullPtrType.restype = LLVMMetadataRef - LLVMDIBuilderCreateNullPtrType.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTypedef = _libraries['llvm'].LLVMDIBuilderCreateTypedef - LLVMDIBuilderCreateTypedef.restype = LLVMMetadataRef - LLVMDIBuilderCreateTypedef.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateInheritance = _libraries['llvm'].LLVMDIBuilderCreateInheritance - LLVMDIBuilderCreateInheritance.restype = LLVMMetadataRef - LLVMDIBuilderCreateInheritance.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateForwardDecl = _libraries['llvm'].LLVMDIBuilderCreateForwardDecl - LLVMDIBuilderCreateForwardDecl.restype = LLVMMetadataRef - LLVMDIBuilderCreateForwardDecl.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateReplaceableCompositeType = _libraries['llvm'].LLVMDIBuilderCreateReplaceableCompositeType - LLVMDIBuilderCreateReplaceableCompositeType.restype = LLVMMetadataRef - LLVMDIBuilderCreateReplaceableCompositeType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateBitFieldMemberType = _libraries['llvm'].LLVMDIBuilderCreateBitFieldMemberType - LLVMDIBuilderCreateBitFieldMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateBitFieldMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint64_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateClassType = _libraries['llvm'].LLVMDIBuilderCreateClassType - LLVMDIBuilderCreateClassType.restype = LLVMMetadataRef - LLVMDIBuilderCreateClassType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateArtificialType = _libraries['llvm'].LLVMDIBuilderCreateArtificialType - LLVMDIBuilderCreateArtificialType.restype = LLVMMetadataRef - LLVMDIBuilderCreateArtificialType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetName = _libraries['llvm'].LLVMDITypeGetName - LLVMDITypeGetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMDITypeGetName.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDITypeGetSizeInBits = _libraries['llvm'].LLVMDITypeGetSizeInBits - LLVMDITypeGetSizeInBits.restype = uint64_t - LLVMDITypeGetSizeInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetOffsetInBits = _libraries['llvm'].LLVMDITypeGetOffsetInBits - LLVMDITypeGetOffsetInBits.restype = uint64_t - LLVMDITypeGetOffsetInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetAlignInBits = _libraries['llvm'].LLVMDITypeGetAlignInBits - LLVMDITypeGetAlignInBits.restype = uint32_t - LLVMDITypeGetAlignInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetLine = _libraries['llvm'].LLVMDITypeGetLine - LLVMDITypeGetLine.restype = ctypes.c_uint32 - LLVMDITypeGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetFlags = _libraries['llvm'].LLVMDITypeGetFlags - LLVMDITypeGetFlags.restype = LLVMDIFlags - LLVMDITypeGetFlags.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateSubrange = _libraries['llvm'].LLVMDIBuilderGetOrCreateSubrange - LLVMDIBuilderGetOrCreateSubrange.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateSubrange.argtypes = [LLVMDIBuilderRef, int64_t, int64_t] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateArray = _libraries['llvm'].LLVMDIBuilderGetOrCreateArray - LLVMDIBuilderGetOrCreateArray.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateArray.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateExpression = _libraries['llvm'].LLVMDIBuilderCreateExpression - LLVMDIBuilderCreateExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateExpression.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_uint64), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateConstantValueExpression = _libraries['llvm'].LLVMDIBuilderCreateConstantValueExpression - LLVMDIBuilderCreateConstantValueExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateConstantValueExpression.argtypes = [LLVMDIBuilderRef, uint64_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateGlobalVariableExpression = _libraries['llvm'].LLVMDIBuilderCreateGlobalVariableExpression - LLVMDIBuilderCreateGlobalVariableExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateGlobalVariableExpression.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIGlobalVariableExpressionGetVariable = _libraries['llvm'].LLVMDIGlobalVariableExpressionGetVariable - LLVMDIGlobalVariableExpressionGetVariable.restype = LLVMMetadataRef - LLVMDIGlobalVariableExpressionGetVariable.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIGlobalVariableExpressionGetExpression = _libraries['llvm'].LLVMDIGlobalVariableExpressionGetExpression - LLVMDIGlobalVariableExpressionGetExpression.restype = LLVMMetadataRef - LLVMDIGlobalVariableExpressionGetExpression.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetFile = _libraries['llvm'].LLVMDIVariableGetFile - LLVMDIVariableGetFile.restype = LLVMMetadataRef - LLVMDIVariableGetFile.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetScope = _libraries['llvm'].LLVMDIVariableGetScope - LLVMDIVariableGetScope.restype = LLVMMetadataRef - LLVMDIVariableGetScope.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetLine = _libraries['llvm'].LLVMDIVariableGetLine - LLVMDIVariableGetLine.restype = ctypes.c_uint32 - LLVMDIVariableGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMTemporaryMDNode = _libraries['llvm'].LLVMTemporaryMDNode - LLVMTemporaryMDNode.restype = LLVMMetadataRef - LLVMTemporaryMDNode.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDisposeTemporaryMDNode = _libraries['llvm'].LLVMDisposeTemporaryMDNode - LLVMDisposeTemporaryMDNode.restype = None - LLVMDisposeTemporaryMDNode.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMMetadataReplaceAllUsesWith = _libraries['llvm'].LLVMMetadataReplaceAllUsesWith - LLVMMetadataReplaceAllUsesWith.restype = None - LLVMMetadataReplaceAllUsesWith.argtypes = [LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTempGlobalVariableFwdDecl = _libraries['llvm'].LLVMDIBuilderCreateTempGlobalVariableFwdDecl - LLVMDIBuilderCreateTempGlobalVariableFwdDecl.restype = LLVMMetadataRef - LLVMDIBuilderCreateTempGlobalVariableFwdDecl.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDeclareBefore = _libraries['llvm'].LLVMDIBuilderInsertDeclareBefore - LLVMDIBuilderInsertDeclareBefore.restype = LLVMValueRef - LLVMDIBuilderInsertDeclareBefore.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDeclareAtEnd = _libraries['llvm'].LLVMDIBuilderInsertDeclareAtEnd - LLVMDIBuilderInsertDeclareAtEnd.restype = LLVMValueRef - LLVMDIBuilderInsertDeclareAtEnd.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDbgValueBefore = _libraries['llvm'].LLVMDIBuilderInsertDbgValueBefore - LLVMDIBuilderInsertDbgValueBefore.restype = LLVMValueRef - LLVMDIBuilderInsertDbgValueBefore.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDbgValueAtEnd = _libraries['llvm'].LLVMDIBuilderInsertDbgValueAtEnd - LLVMDIBuilderInsertDbgValueAtEnd.restype = LLVMValueRef - LLVMDIBuilderInsertDbgValueAtEnd.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateAutoVariable = _libraries['llvm'].LLVMDIBuilderCreateAutoVariable - LLVMDIBuilderCreateAutoVariable.restype = LLVMMetadataRef - LLVMDIBuilderCreateAutoVariable.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateParameterVariable = _libraries['llvm'].LLVMDIBuilderCreateParameterVariable - LLVMDIBuilderCreateParameterVariable.restype = LLVMMetadataRef - LLVMDIBuilderCreateParameterVariable.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMGetSubprogram = _libraries['llvm'].LLVMGetSubprogram - LLVMGetSubprogram.restype = LLVMMetadataRef - LLVMGetSubprogram.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetSubprogram = _libraries['llvm'].LLVMSetSubprogram - LLVMSetSubprogram.restype = None - LLVMSetSubprogram.argtypes = [LLVMValueRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDISubprogramGetLine = _libraries['llvm'].LLVMDISubprogramGetLine - LLVMDISubprogramGetLine.restype = ctypes.c_uint32 - LLVMDISubprogramGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMInstructionGetDebugLoc = _libraries['llvm'].LLVMInstructionGetDebugLoc - LLVMInstructionGetDebugLoc.restype = LLVMMetadataRef - LLVMInstructionGetDebugLoc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionSetDebugLoc = _libraries['llvm'].LLVMInstructionSetDebugLoc - LLVMInstructionSetDebugLoc.restype = None - LLVMInstructionSetDebugLoc.argtypes = [LLVMValueRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMGetMetadataKind = _libraries['llvm'].LLVMGetMetadataKind - LLVMGetMetadataKind.restype = LLVMMetadataKind - LLVMGetMetadataKind.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -LLVM_C_DISASSEMBLER_H = True # macro -LLVM_C_DISASSEMBLERTYPES_H = True # macro -LLVMDisassembler_VariantKind_None = 0 # macro -LLVMDisassembler_VariantKind_ARM_HI16 = 1 # macro -LLVMDisassembler_VariantKind_ARM_LO16 = 2 # macro -LLVMDisassembler_VariantKind_ARM64_PAGE = 1 # macro -LLVMDisassembler_VariantKind_ARM64_PAGEOFF = 2 # macro -LLVMDisassembler_VariantKind_ARM64_GOTPAGE = 3 # macro -LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF = 4 # macro -LLVMDisassembler_VariantKind_ARM64_TLVP = 5 # macro -LLVMDisassembler_VariantKind_ARM64_TLVOFF = 6 # macro -LLVMDisassembler_ReferenceType_InOut_None = 0 # macro -LLVMDisassembler_ReferenceType_In_Branch = 1 # macro -LLVMDisassembler_ReferenceType_In_PCrel_Load = 2 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADRP = 0x100000001 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADDXri = 0x100000002 # macro -LLVMDisassembler_ReferenceType_In_ARM64_LDRXui = 0x100000003 # macro -LLVMDisassembler_ReferenceType_In_ARM64_LDRXl = 0x100000004 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADR = 0x100000005 # macro -LLVMDisassembler_ReferenceType_Out_SymbolStub = 1 # macro -LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr = 2 # macro -LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr = 3 # macro -LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref = 4 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Message = 5 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref = 6 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref = 7 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref = 8 # macro -LLVMDisassembler_ReferenceType_DeMangled_Name = 9 # macro -LLVMDisassembler_Option_UseMarkup = 1 # macro -LLVMDisassembler_Option_PrintImmHex = 2 # macro -LLVMDisassembler_Option_AsmPrinterVariant = 4 # macro -LLVMDisassembler_Option_SetInstrComments = 8 # macro -LLVMDisassembler_Option_PrintLatency = 16 # macro -LLVMDisasmContextRef = ctypes.POINTER(None) -LLVMOpInfoCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_int32, ctypes.POINTER(None)) -class struct_LLVMOpInfoSymbol1(Structure): - pass - -struct_LLVMOpInfoSymbol1._pack_ = 1 # source:False -struct_LLVMOpInfoSymbol1._fields_ = [ - ('Present', ctypes.c_uint64), - ('Name', ctypes.POINTER(ctypes.c_char)), - ('Value', ctypes.c_uint64), -] - -class struct_LLVMOpInfo1(Structure): - pass - -struct_LLVMOpInfo1._pack_ = 1 # source:False -struct_LLVMOpInfo1._fields_ = [ - ('AddSymbol', struct_LLVMOpInfoSymbol1), - ('SubtractSymbol', struct_LLVMOpInfoSymbol1), - ('Value', ctypes.c_uint64), - ('VariantKind', ctypes.c_uint64), -] - -LLVMSymbolLookupCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) -try: - LLVMCreateDisasm = _libraries['llvm'].LLVMCreateDisasm - LLVMCreateDisasm.restype = LLVMDisasmContextRef - LLVMCreateDisasm.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMCreateDisasmCPU = _libraries['llvm'].LLVMCreateDisasmCPU - LLVMCreateDisasmCPU.restype = LLVMDisasmContextRef - LLVMCreateDisasmCPU.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMCreateDisasmCPUFeatures = _libraries['llvm'].LLVMCreateDisasmCPUFeatures - LLVMCreateDisasmCPUFeatures.restype = LLVMDisasmContextRef - LLVMCreateDisasmCPUFeatures.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMSetDisasmOptions = _libraries['llvm'].LLVMSetDisasmOptions - LLVMSetDisasmOptions.restype = ctypes.c_int32 - LLVMSetDisasmOptions.argtypes = [LLVMDisasmContextRef, uint64_t] -except AttributeError: - pass -try: - LLVMDisasmDispose = _libraries['llvm'].LLVMDisasmDispose - LLVMDisasmDispose.restype = None - LLVMDisasmDispose.argtypes = [LLVMDisasmContextRef] -except AttributeError: - pass -try: - LLVMDisasmInstruction = _libraries['llvm'].LLVMDisasmInstruction - LLVMDisasmInstruction.restype = size_t - LLVMDisasmInstruction.argtypes = [LLVMDisasmContextRef, ctypes.POINTER(ctypes.c_ubyte), uint64_t, uint64_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -LLVM_C_ERROR_H = True # macro -LLVMErrorSuccess = 0 # macro -class struct_LLVMOpaqueError(Structure): - pass - -LLVMErrorRef = ctypes.POINTER(struct_LLVMOpaqueError) -LLVMErrorTypeId = ctypes.POINTER(None) -try: - LLVMGetErrorTypeId = _libraries['llvm'].LLVMGetErrorTypeId - LLVMGetErrorTypeId.restype = LLVMErrorTypeId - LLVMGetErrorTypeId.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMConsumeError = _libraries['llvm'].LLVMConsumeError - LLVMConsumeError.restype = None - LLVMConsumeError.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMGetErrorMessage = _libraries['llvm'].LLVMGetErrorMessage - LLVMGetErrorMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetErrorMessage.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMDisposeErrorMessage = _libraries['llvm'].LLVMDisposeErrorMessage - LLVMDisposeErrorMessage.restype = None - LLVMDisposeErrorMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetStringErrorTypeId = _libraries['llvm'].LLVMGetStringErrorTypeId - LLVMGetStringErrorTypeId.restype = LLVMErrorTypeId - LLVMGetStringErrorTypeId.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateStringError = _libraries['llvm'].LLVMCreateStringError - LLVMCreateStringError.restype = LLVMErrorRef - LLVMCreateStringError.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -LLVM_C_EXECUTIONENGINE_H = True # macro -LLVM_C_TARGET_H = True # macro -# def LLVM_TARGET(TargetName): # macro -# return LLVMInitialize##TargetName##TargetMC; -# def LLVM_ASM_PRINTER(TargetName): # macro -# return LLVMInitialize##TargetName##AsmPrinter; -# def LLVM_ASM_PARSER(TargetName): # macro -# return LLVMInitialize##TargetName##AsmParser; -# def LLVM_DISASSEMBLER(TargetName): # macro -# return LLVMInitialize##TargetName##Disassembler; -LLVM_C_TARGETMACHINE_H = True # macro - -# values for enumeration 'LLVMByteOrdering' -LLVMByteOrdering__enumvalues = { - 0: 'LLVMBigEndian', - 1: 'LLVMLittleEndian', -} -LLVMBigEndian = 0 -LLVMLittleEndian = 1 -LLVMByteOrdering = ctypes.c_uint32 # enum -class struct_LLVMOpaqueTargetData(Structure): - pass - -LLVMTargetDataRef = ctypes.POINTER(struct_LLVMOpaqueTargetData) -class struct_LLVMOpaqueTargetLibraryInfotData(Structure): - pass - -LLVMTargetLibraryInfoRef = ctypes.POINTER(struct_LLVMOpaqueTargetLibraryInfotData) -try: - LLVMInitializeAArch64TargetInfo = _libraries['llvm'].LLVMInitializeAArch64TargetInfo - LLVMInitializeAArch64TargetInfo.restype = None - LLVMInitializeAArch64TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTargetInfo = _libraries['llvm'].LLVMInitializeAMDGPUTargetInfo - LLVMInitializeAMDGPUTargetInfo.restype = None - LLVMInitializeAMDGPUTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTargetInfo = _libraries['llvm'].LLVMInitializeARMTargetInfo - LLVMInitializeARMTargetInfo.restype = None - LLVMInitializeARMTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTargetInfo = _libraries['llvm'].LLVMInitializeAVRTargetInfo - LLVMInitializeAVRTargetInfo.restype = None - LLVMInitializeAVRTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTargetInfo = _libraries['llvm'].LLVMInitializeBPFTargetInfo - LLVMInitializeBPFTargetInfo.restype = None - LLVMInitializeBPFTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTargetInfo = _libraries['llvm'].LLVMInitializeHexagonTargetInfo - LLVMInitializeHexagonTargetInfo.restype = None - LLVMInitializeHexagonTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTargetInfo = _libraries['llvm'].LLVMInitializeLanaiTargetInfo - LLVMInitializeLanaiTargetInfo.restype = None - LLVMInitializeLanaiTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTargetInfo = _libraries['llvm'].LLVMInitializeMipsTargetInfo - LLVMInitializeMipsTargetInfo.restype = None - LLVMInitializeMipsTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430TargetInfo = _libraries['llvm'].LLVMInitializeMSP430TargetInfo - LLVMInitializeMSP430TargetInfo.restype = None - LLVMInitializeMSP430TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTargetInfo = _libraries['llvm'].LLVMInitializeNVPTXTargetInfo - LLVMInitializeNVPTXTargetInfo.restype = None - LLVMInitializeNVPTXTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTargetInfo = _libraries['llvm'].LLVMInitializePowerPCTargetInfo - LLVMInitializePowerPCTargetInfo.restype = None - LLVMInitializePowerPCTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTargetInfo = _libraries['llvm'].LLVMInitializeRISCVTargetInfo - LLVMInitializeRISCVTargetInfo.restype = None - LLVMInitializeRISCVTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTargetInfo = _libraries['llvm'].LLVMInitializeSparcTargetInfo - LLVMInitializeSparcTargetInfo.restype = None - LLVMInitializeSparcTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTargetInfo = _libraries['llvm'].LLVMInitializeSystemZTargetInfo - LLVMInitializeSystemZTargetInfo.restype = None - LLVMInitializeSystemZTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETargetInfo = _libraries['llvm'].LLVMInitializeVETargetInfo - LLVMInitializeVETargetInfo.restype = None - LLVMInitializeVETargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTargetInfo = _libraries['llvm'].LLVMInitializeWebAssemblyTargetInfo - LLVMInitializeWebAssemblyTargetInfo.restype = None - LLVMInitializeWebAssemblyTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86TargetInfo = _libraries['llvm'].LLVMInitializeX86TargetInfo - LLVMInitializeX86TargetInfo.restype = None - LLVMInitializeX86TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTargetInfo = _libraries['llvm'].LLVMInitializeXCoreTargetInfo - LLVMInitializeXCoreTargetInfo.restype = None - LLVMInitializeXCoreTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTargetInfo = _libraries['llvm'].LLVMInitializeM68kTargetInfo - LLVMInitializeM68kTargetInfo.restype = None - LLVMInitializeM68kTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64Target = _libraries['llvm'].LLVMInitializeAArch64Target - LLVMInitializeAArch64Target.restype = None - LLVMInitializeAArch64Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTarget = _libraries['llvm'].LLVMInitializeAMDGPUTarget - LLVMInitializeAMDGPUTarget.restype = None - LLVMInitializeAMDGPUTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTarget = _libraries['llvm'].LLVMInitializeARMTarget - LLVMInitializeARMTarget.restype = None - LLVMInitializeARMTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTarget = _libraries['llvm'].LLVMInitializeAVRTarget - LLVMInitializeAVRTarget.restype = None - LLVMInitializeAVRTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTarget = _libraries['llvm'].LLVMInitializeBPFTarget - LLVMInitializeBPFTarget.restype = None - LLVMInitializeBPFTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTarget = _libraries['llvm'].LLVMInitializeHexagonTarget - LLVMInitializeHexagonTarget.restype = None - LLVMInitializeHexagonTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTarget = _libraries['llvm'].LLVMInitializeLanaiTarget - LLVMInitializeLanaiTarget.restype = None - LLVMInitializeLanaiTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTarget = _libraries['llvm'].LLVMInitializeMipsTarget - LLVMInitializeMipsTarget.restype = None - LLVMInitializeMipsTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430Target = _libraries['llvm'].LLVMInitializeMSP430Target - LLVMInitializeMSP430Target.restype = None - LLVMInitializeMSP430Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTarget = _libraries['llvm'].LLVMInitializeNVPTXTarget - LLVMInitializeNVPTXTarget.restype = None - LLVMInitializeNVPTXTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTarget = _libraries['llvm'].LLVMInitializePowerPCTarget - LLVMInitializePowerPCTarget.restype = None - LLVMInitializePowerPCTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTarget = _libraries['llvm'].LLVMInitializeRISCVTarget - LLVMInitializeRISCVTarget.restype = None - LLVMInitializeRISCVTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTarget = _libraries['llvm'].LLVMInitializeSparcTarget - LLVMInitializeSparcTarget.restype = None - LLVMInitializeSparcTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTarget = _libraries['llvm'].LLVMInitializeSystemZTarget - LLVMInitializeSystemZTarget.restype = None - LLVMInitializeSystemZTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETarget = _libraries['llvm'].LLVMInitializeVETarget - LLVMInitializeVETarget.restype = None - LLVMInitializeVETarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTarget = _libraries['llvm'].LLVMInitializeWebAssemblyTarget - LLVMInitializeWebAssemblyTarget.restype = None - LLVMInitializeWebAssemblyTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86Target = _libraries['llvm'].LLVMInitializeX86Target - LLVMInitializeX86Target.restype = None - LLVMInitializeX86Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTarget = _libraries['llvm'].LLVMInitializeXCoreTarget - LLVMInitializeXCoreTarget.restype = None - LLVMInitializeXCoreTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTarget = _libraries['llvm'].LLVMInitializeM68kTarget - LLVMInitializeM68kTarget.restype = None - LLVMInitializeM68kTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64TargetMC = _libraries['llvm'].LLVMInitializeAArch64TargetMC - LLVMInitializeAArch64TargetMC.restype = None - LLVMInitializeAArch64TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTargetMC = _libraries['llvm'].LLVMInitializeAMDGPUTargetMC - LLVMInitializeAMDGPUTargetMC.restype = None - LLVMInitializeAMDGPUTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTargetMC = _libraries['llvm'].LLVMInitializeARMTargetMC - LLVMInitializeARMTargetMC.restype = None - LLVMInitializeARMTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTargetMC = _libraries['llvm'].LLVMInitializeAVRTargetMC - LLVMInitializeAVRTargetMC.restype = None - LLVMInitializeAVRTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTargetMC = _libraries['llvm'].LLVMInitializeBPFTargetMC - LLVMInitializeBPFTargetMC.restype = None - LLVMInitializeBPFTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTargetMC = _libraries['llvm'].LLVMInitializeHexagonTargetMC - LLVMInitializeHexagonTargetMC.restype = None - LLVMInitializeHexagonTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTargetMC = _libraries['llvm'].LLVMInitializeLanaiTargetMC - LLVMInitializeLanaiTargetMC.restype = None - LLVMInitializeLanaiTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTargetMC = _libraries['llvm'].LLVMInitializeMipsTargetMC - LLVMInitializeMipsTargetMC.restype = None - LLVMInitializeMipsTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430TargetMC = _libraries['llvm'].LLVMInitializeMSP430TargetMC - LLVMInitializeMSP430TargetMC.restype = None - LLVMInitializeMSP430TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTargetMC = _libraries['llvm'].LLVMInitializeNVPTXTargetMC - LLVMInitializeNVPTXTargetMC.restype = None - LLVMInitializeNVPTXTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTargetMC = _libraries['llvm'].LLVMInitializePowerPCTargetMC - LLVMInitializePowerPCTargetMC.restype = None - LLVMInitializePowerPCTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTargetMC = _libraries['llvm'].LLVMInitializeRISCVTargetMC - LLVMInitializeRISCVTargetMC.restype = None - LLVMInitializeRISCVTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTargetMC = _libraries['llvm'].LLVMInitializeSparcTargetMC - LLVMInitializeSparcTargetMC.restype = None - LLVMInitializeSparcTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTargetMC = _libraries['llvm'].LLVMInitializeSystemZTargetMC - LLVMInitializeSystemZTargetMC.restype = None - LLVMInitializeSystemZTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETargetMC = _libraries['llvm'].LLVMInitializeVETargetMC - LLVMInitializeVETargetMC.restype = None - LLVMInitializeVETargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTargetMC = _libraries['llvm'].LLVMInitializeWebAssemblyTargetMC - LLVMInitializeWebAssemblyTargetMC.restype = None - LLVMInitializeWebAssemblyTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86TargetMC = _libraries['llvm'].LLVMInitializeX86TargetMC - LLVMInitializeX86TargetMC.restype = None - LLVMInitializeX86TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTargetMC = _libraries['llvm'].LLVMInitializeXCoreTargetMC - LLVMInitializeXCoreTargetMC.restype = None - LLVMInitializeXCoreTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTargetMC = _libraries['llvm'].LLVMInitializeM68kTargetMC - LLVMInitializeM68kTargetMC.restype = None - LLVMInitializeM68kTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64AsmPrinter = _libraries['llvm'].LLVMInitializeAArch64AsmPrinter - LLVMInitializeAArch64AsmPrinter.restype = None - LLVMInitializeAArch64AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUAsmPrinter = _libraries['llvm'].LLVMInitializeAMDGPUAsmPrinter - LLVMInitializeAMDGPUAsmPrinter.restype = None - LLVMInitializeAMDGPUAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMAsmPrinter = _libraries['llvm'].LLVMInitializeARMAsmPrinter - LLVMInitializeARMAsmPrinter.restype = None - LLVMInitializeARMAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRAsmPrinter = _libraries['llvm'].LLVMInitializeAVRAsmPrinter - LLVMInitializeAVRAsmPrinter.restype = None - LLVMInitializeAVRAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFAsmPrinter = _libraries['llvm'].LLVMInitializeBPFAsmPrinter - LLVMInitializeBPFAsmPrinter.restype = None - LLVMInitializeBPFAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonAsmPrinter = _libraries['llvm'].LLVMInitializeHexagonAsmPrinter - LLVMInitializeHexagonAsmPrinter.restype = None - LLVMInitializeHexagonAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiAsmPrinter = _libraries['llvm'].LLVMInitializeLanaiAsmPrinter - LLVMInitializeLanaiAsmPrinter.restype = None - LLVMInitializeLanaiAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsAsmPrinter = _libraries['llvm'].LLVMInitializeMipsAsmPrinter - LLVMInitializeMipsAsmPrinter.restype = None - LLVMInitializeMipsAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430AsmPrinter = _libraries['llvm'].LLVMInitializeMSP430AsmPrinter - LLVMInitializeMSP430AsmPrinter.restype = None - LLVMInitializeMSP430AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXAsmPrinter = _libraries['llvm'].LLVMInitializeNVPTXAsmPrinter - LLVMInitializeNVPTXAsmPrinter.restype = None - LLVMInitializeNVPTXAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCAsmPrinter = _libraries['llvm'].LLVMInitializePowerPCAsmPrinter - LLVMInitializePowerPCAsmPrinter.restype = None - LLVMInitializePowerPCAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVAsmPrinter = _libraries['llvm'].LLVMInitializeRISCVAsmPrinter - LLVMInitializeRISCVAsmPrinter.restype = None - LLVMInitializeRISCVAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcAsmPrinter = _libraries['llvm'].LLVMInitializeSparcAsmPrinter - LLVMInitializeSparcAsmPrinter.restype = None - LLVMInitializeSparcAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZAsmPrinter = _libraries['llvm'].LLVMInitializeSystemZAsmPrinter - LLVMInitializeSystemZAsmPrinter.restype = None - LLVMInitializeSystemZAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEAsmPrinter = _libraries['llvm'].LLVMInitializeVEAsmPrinter - LLVMInitializeVEAsmPrinter.restype = None - LLVMInitializeVEAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyAsmPrinter = _libraries['llvm'].LLVMInitializeWebAssemblyAsmPrinter - LLVMInitializeWebAssemblyAsmPrinter.restype = None - LLVMInitializeWebAssemblyAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86AsmPrinter = _libraries['llvm'].LLVMInitializeX86AsmPrinter - LLVMInitializeX86AsmPrinter.restype = None - LLVMInitializeX86AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreAsmPrinter = _libraries['llvm'].LLVMInitializeXCoreAsmPrinter - LLVMInitializeXCoreAsmPrinter.restype = None - LLVMInitializeXCoreAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kAsmPrinter = _libraries['llvm'].LLVMInitializeM68kAsmPrinter - LLVMInitializeM68kAsmPrinter.restype = None - LLVMInitializeM68kAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64AsmParser = _libraries['llvm'].LLVMInitializeAArch64AsmParser - LLVMInitializeAArch64AsmParser.restype = None - LLVMInitializeAArch64AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUAsmParser = _libraries['llvm'].LLVMInitializeAMDGPUAsmParser - LLVMInitializeAMDGPUAsmParser.restype = None - LLVMInitializeAMDGPUAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMAsmParser = _libraries['llvm'].LLVMInitializeARMAsmParser - LLVMInitializeARMAsmParser.restype = None - LLVMInitializeARMAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRAsmParser = _libraries['llvm'].LLVMInitializeAVRAsmParser - LLVMInitializeAVRAsmParser.restype = None - LLVMInitializeAVRAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFAsmParser = _libraries['llvm'].LLVMInitializeBPFAsmParser - LLVMInitializeBPFAsmParser.restype = None - LLVMInitializeBPFAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonAsmParser = _libraries['llvm'].LLVMInitializeHexagonAsmParser - LLVMInitializeHexagonAsmParser.restype = None - LLVMInitializeHexagonAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiAsmParser = _libraries['llvm'].LLVMInitializeLanaiAsmParser - LLVMInitializeLanaiAsmParser.restype = None - LLVMInitializeLanaiAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsAsmParser = _libraries['llvm'].LLVMInitializeMipsAsmParser - LLVMInitializeMipsAsmParser.restype = None - LLVMInitializeMipsAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430AsmParser = _libraries['llvm'].LLVMInitializeMSP430AsmParser - LLVMInitializeMSP430AsmParser.restype = None - LLVMInitializeMSP430AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCAsmParser = _libraries['llvm'].LLVMInitializePowerPCAsmParser - LLVMInitializePowerPCAsmParser.restype = None - LLVMInitializePowerPCAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVAsmParser = _libraries['llvm'].LLVMInitializeRISCVAsmParser - LLVMInitializeRISCVAsmParser.restype = None - LLVMInitializeRISCVAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcAsmParser = _libraries['llvm'].LLVMInitializeSparcAsmParser - LLVMInitializeSparcAsmParser.restype = None - LLVMInitializeSparcAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZAsmParser = _libraries['llvm'].LLVMInitializeSystemZAsmParser - LLVMInitializeSystemZAsmParser.restype = None - LLVMInitializeSystemZAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEAsmParser = _libraries['llvm'].LLVMInitializeVEAsmParser - LLVMInitializeVEAsmParser.restype = None - LLVMInitializeVEAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyAsmParser = _libraries['llvm'].LLVMInitializeWebAssemblyAsmParser - LLVMInitializeWebAssemblyAsmParser.restype = None - LLVMInitializeWebAssemblyAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86AsmParser = _libraries['llvm'].LLVMInitializeX86AsmParser - LLVMInitializeX86AsmParser.restype = None - LLVMInitializeX86AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kAsmParser = _libraries['llvm'].LLVMInitializeM68kAsmParser - LLVMInitializeM68kAsmParser.restype = None - LLVMInitializeM68kAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64Disassembler = _libraries['llvm'].LLVMInitializeAArch64Disassembler - LLVMInitializeAArch64Disassembler.restype = None - LLVMInitializeAArch64Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUDisassembler = _libraries['llvm'].LLVMInitializeAMDGPUDisassembler - LLVMInitializeAMDGPUDisassembler.restype = None - LLVMInitializeAMDGPUDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMDisassembler = _libraries['llvm'].LLVMInitializeARMDisassembler - LLVMInitializeARMDisassembler.restype = None - LLVMInitializeARMDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRDisassembler = _libraries['llvm'].LLVMInitializeAVRDisassembler - LLVMInitializeAVRDisassembler.restype = None - LLVMInitializeAVRDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFDisassembler = _libraries['llvm'].LLVMInitializeBPFDisassembler - LLVMInitializeBPFDisassembler.restype = None - LLVMInitializeBPFDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonDisassembler = _libraries['llvm'].LLVMInitializeHexagonDisassembler - LLVMInitializeHexagonDisassembler.restype = None - LLVMInitializeHexagonDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiDisassembler = _libraries['llvm'].LLVMInitializeLanaiDisassembler - LLVMInitializeLanaiDisassembler.restype = None - LLVMInitializeLanaiDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsDisassembler = _libraries['llvm'].LLVMInitializeMipsDisassembler - LLVMInitializeMipsDisassembler.restype = None - LLVMInitializeMipsDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430Disassembler = _libraries['llvm'].LLVMInitializeMSP430Disassembler - LLVMInitializeMSP430Disassembler.restype = None - LLVMInitializeMSP430Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCDisassembler = _libraries['llvm'].LLVMInitializePowerPCDisassembler - LLVMInitializePowerPCDisassembler.restype = None - LLVMInitializePowerPCDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVDisassembler = _libraries['llvm'].LLVMInitializeRISCVDisassembler - LLVMInitializeRISCVDisassembler.restype = None - LLVMInitializeRISCVDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcDisassembler = _libraries['llvm'].LLVMInitializeSparcDisassembler - LLVMInitializeSparcDisassembler.restype = None - LLVMInitializeSparcDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZDisassembler = _libraries['llvm'].LLVMInitializeSystemZDisassembler - LLVMInitializeSystemZDisassembler.restype = None - LLVMInitializeSystemZDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEDisassembler = _libraries['llvm'].LLVMInitializeVEDisassembler - LLVMInitializeVEDisassembler.restype = None - LLVMInitializeVEDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyDisassembler = _libraries['llvm'].LLVMInitializeWebAssemblyDisassembler - LLVMInitializeWebAssemblyDisassembler.restype = None - LLVMInitializeWebAssemblyDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86Disassembler = _libraries['llvm'].LLVMInitializeX86Disassembler - LLVMInitializeX86Disassembler.restype = None - LLVMInitializeX86Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreDisassembler = _libraries['llvm'].LLVMInitializeXCoreDisassembler - LLVMInitializeXCoreDisassembler.restype = None - LLVMInitializeXCoreDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kDisassembler = _libraries['llvm'].LLVMInitializeM68kDisassembler - LLVMInitializeM68kDisassembler.restype = None - LLVMInitializeM68kDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargetInfos = _libraries['llvm'].LLVMInitializeAllTargetInfos - LLVMInitializeAllTargetInfos.restype = None - LLVMInitializeAllTargetInfos.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargets = _libraries['llvm'].LLVMInitializeAllTargets - LLVMInitializeAllTargets.restype = None - LLVMInitializeAllTargets.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargetMCs = _libraries['llvm'].LLVMInitializeAllTargetMCs - LLVMInitializeAllTargetMCs.restype = None - LLVMInitializeAllTargetMCs.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllAsmPrinters = _libraries['llvm'].LLVMInitializeAllAsmPrinters - LLVMInitializeAllAsmPrinters.restype = None - LLVMInitializeAllAsmPrinters.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllAsmParsers = _libraries['llvm'].LLVMInitializeAllAsmParsers - LLVMInitializeAllAsmParsers.restype = None - LLVMInitializeAllAsmParsers.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllDisassemblers = _libraries['llvm'].LLVMInitializeAllDisassemblers - LLVMInitializeAllDisassemblers.restype = None - LLVMInitializeAllDisassemblers.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeTarget = _libraries['llvm'].LLVMInitializeNativeTarget - LLVMInitializeNativeTarget.restype = LLVMBool - LLVMInitializeNativeTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeAsmParser = _libraries['llvm'].LLVMInitializeNativeAsmParser - LLVMInitializeNativeAsmParser.restype = LLVMBool - LLVMInitializeNativeAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeAsmPrinter = _libraries['llvm'].LLVMInitializeNativeAsmPrinter - LLVMInitializeNativeAsmPrinter.restype = LLVMBool - LLVMInitializeNativeAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeDisassembler = _libraries['llvm'].LLVMInitializeNativeDisassembler - LLVMInitializeNativeDisassembler.restype = LLVMBool - LLVMInitializeNativeDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMGetModuleDataLayout = _libraries['llvm'].LLVMGetModuleDataLayout - LLVMGetModuleDataLayout.restype = LLVMTargetDataRef - LLVMGetModuleDataLayout.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetModuleDataLayout = _libraries['llvm'].LLVMSetModuleDataLayout - LLVMSetModuleDataLayout.restype = None - LLVMSetModuleDataLayout.argtypes = [LLVMModuleRef, LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMCreateTargetData = _libraries['llvm'].LLVMCreateTargetData - LLVMCreateTargetData.restype = LLVMTargetDataRef - LLVMCreateTargetData.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeTargetData = _libraries['llvm'].LLVMDisposeTargetData - LLVMDisposeTargetData.restype = None - LLVMDisposeTargetData.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMAddTargetLibraryInfo = _libraries['llvm'].LLVMAddTargetLibraryInfo - LLVMAddTargetLibraryInfo.restype = None - LLVMAddTargetLibraryInfo.argtypes = [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMCopyStringRepOfTargetData = _libraries['llvm'].LLVMCopyStringRepOfTargetData - LLVMCopyStringRepOfTargetData.restype = ctypes.POINTER(ctypes.c_char) - LLVMCopyStringRepOfTargetData.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMByteOrder = _libraries['llvm'].LLVMByteOrder - LLVMByteOrder.restype = LLVMByteOrdering - LLVMByteOrder.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMPointerSize = _libraries['llvm'].LLVMPointerSize - LLVMPointerSize.restype = ctypes.c_uint32 - LLVMPointerSize.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMPointerSizeForAS = _libraries['llvm'].LLVMPointerSizeForAS - LLVMPointerSizeForAS.restype = ctypes.c_uint32 - LLVMPointerSizeForAS.argtypes = [LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIntPtrType = _libraries['llvm'].LLVMIntPtrType - LLVMIntPtrType.restype = LLVMTypeRef - LLVMIntPtrType.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMIntPtrTypeForAS = _libraries['llvm'].LLVMIntPtrTypeForAS - LLVMIntPtrTypeForAS.restype = LLVMTypeRef - LLVMIntPtrTypeForAS.argtypes = [LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIntPtrTypeInContext = _libraries['llvm'].LLVMIntPtrTypeInContext - LLVMIntPtrTypeInContext.restype = LLVMTypeRef - LLVMIntPtrTypeInContext.argtypes = [LLVMContextRef, LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMIntPtrTypeForASInContext = _libraries['llvm'].LLVMIntPtrTypeForASInContext - LLVMIntPtrTypeForASInContext.restype = LLVMTypeRef - LLVMIntPtrTypeForASInContext.argtypes = [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSizeOfTypeInBits = _libraries['llvm'].LLVMSizeOfTypeInBits - LLVMSizeOfTypeInBits.restype = ctypes.c_uint64 - LLVMSizeOfTypeInBits.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMStoreSizeOfType = _libraries['llvm'].LLVMStoreSizeOfType - LLVMStoreSizeOfType.restype = ctypes.c_uint64 - LLVMStoreSizeOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMABISizeOfType = _libraries['llvm'].LLVMABISizeOfType - LLVMABISizeOfType.restype = ctypes.c_uint64 - LLVMABISizeOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMABIAlignmentOfType = _libraries['llvm'].LLVMABIAlignmentOfType - LLVMABIAlignmentOfType.restype = ctypes.c_uint32 - LLVMABIAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMCallFrameAlignmentOfType = _libraries['llvm'].LLVMCallFrameAlignmentOfType - LLVMCallFrameAlignmentOfType.restype = ctypes.c_uint32 - LLVMCallFrameAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPreferredAlignmentOfType = _libraries['llvm'].LLVMPreferredAlignmentOfType - LLVMPreferredAlignmentOfType.restype = ctypes.c_uint32 - LLVMPreferredAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPreferredAlignmentOfGlobal = _libraries['llvm'].LLVMPreferredAlignmentOfGlobal - LLVMPreferredAlignmentOfGlobal.restype = ctypes.c_uint32 - LLVMPreferredAlignmentOfGlobal.argtypes = [LLVMTargetDataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMElementAtOffset = _libraries['llvm'].LLVMElementAtOffset - LLVMElementAtOffset.restype = ctypes.c_uint32 - LLVMElementAtOffset.argtypes = [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] -except AttributeError: - pass -try: - LLVMOffsetOfElement = _libraries['llvm'].LLVMOffsetOfElement - LLVMOffsetOfElement.restype = ctypes.c_uint64 - LLVMOffsetOfElement.argtypes = [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -class struct_LLVMOpaqueTargetMachine(Structure): - pass - -LLVMTargetMachineRef = ctypes.POINTER(struct_LLVMOpaqueTargetMachine) -class struct_LLVMTarget(Structure): - pass - -LLVMTargetRef = ctypes.POINTER(struct_LLVMTarget) - -# values for enumeration 'c__EA_LLVMCodeGenOptLevel' -c__EA_LLVMCodeGenOptLevel__enumvalues = { - 0: 'LLVMCodeGenLevelNone', - 1: 'LLVMCodeGenLevelLess', - 2: 'LLVMCodeGenLevelDefault', - 3: 'LLVMCodeGenLevelAggressive', -} -LLVMCodeGenLevelNone = 0 -LLVMCodeGenLevelLess = 1 -LLVMCodeGenLevelDefault = 2 -LLVMCodeGenLevelAggressive = 3 -c__EA_LLVMCodeGenOptLevel = ctypes.c_uint32 # enum -LLVMCodeGenOptLevel = c__EA_LLVMCodeGenOptLevel -LLVMCodeGenOptLevel__enumvalues = c__EA_LLVMCodeGenOptLevel__enumvalues - -# values for enumeration 'c__EA_LLVMRelocMode' -c__EA_LLVMRelocMode__enumvalues = { - 0: 'LLVMRelocDefault', - 1: 'LLVMRelocStatic', - 2: 'LLVMRelocPIC', - 3: 'LLVMRelocDynamicNoPic', - 4: 'LLVMRelocROPI', - 5: 'LLVMRelocRWPI', - 6: 'LLVMRelocROPI_RWPI', -} -LLVMRelocDefault = 0 -LLVMRelocStatic = 1 -LLVMRelocPIC = 2 -LLVMRelocDynamicNoPic = 3 -LLVMRelocROPI = 4 -LLVMRelocRWPI = 5 -LLVMRelocROPI_RWPI = 6 -c__EA_LLVMRelocMode = ctypes.c_uint32 # enum -LLVMRelocMode = c__EA_LLVMRelocMode -LLVMRelocMode__enumvalues = c__EA_LLVMRelocMode__enumvalues - -# values for enumeration 'c__EA_LLVMCodeModel' -c__EA_LLVMCodeModel__enumvalues = { - 0: 'LLVMCodeModelDefault', - 1: 'LLVMCodeModelJITDefault', - 2: 'LLVMCodeModelTiny', - 3: 'LLVMCodeModelSmall', - 4: 'LLVMCodeModelKernel', - 5: 'LLVMCodeModelMedium', - 6: 'LLVMCodeModelLarge', -} -LLVMCodeModelDefault = 0 -LLVMCodeModelJITDefault = 1 -LLVMCodeModelTiny = 2 -LLVMCodeModelSmall = 3 -LLVMCodeModelKernel = 4 -LLVMCodeModelMedium = 5 -LLVMCodeModelLarge = 6 -c__EA_LLVMCodeModel = ctypes.c_uint32 # enum -LLVMCodeModel = c__EA_LLVMCodeModel -LLVMCodeModel__enumvalues = c__EA_LLVMCodeModel__enumvalues - -# values for enumeration 'c__EA_LLVMCodeGenFileType' -c__EA_LLVMCodeGenFileType__enumvalues = { - 0: 'LLVMAssemblyFile', - 1: 'LLVMObjectFile', -} -LLVMAssemblyFile = 0 -LLVMObjectFile = 1 -c__EA_LLVMCodeGenFileType = ctypes.c_uint32 # enum -LLVMCodeGenFileType = c__EA_LLVMCodeGenFileType -LLVMCodeGenFileType__enumvalues = c__EA_LLVMCodeGenFileType__enumvalues -try: - LLVMGetFirstTarget = _libraries['llvm'].LLVMGetFirstTarget - LLVMGetFirstTarget.restype = LLVMTargetRef - LLVMGetFirstTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMGetNextTarget = _libraries['llvm'].LLVMGetNextTarget - LLVMGetNextTarget.restype = LLVMTargetRef - LLVMGetNextTarget.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMGetTargetFromName = _libraries['llvm'].LLVMGetTargetFromName - LLVMGetTargetFromName.restype = LLVMTargetRef - LLVMGetTargetFromName.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTargetFromTriple = _libraries['llvm'].LLVMGetTargetFromTriple - LLVMGetTargetFromTriple.restype = LLVMBool - LLVMGetTargetFromTriple.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMTarget)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetTargetName = _libraries['llvm'].LLVMGetTargetName - LLVMGetTargetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetName.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMGetTargetDescription = _libraries['llvm'].LLVMGetTargetDescription - LLVMGetTargetDescription.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetDescription.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasJIT = _libraries['llvm'].LLVMTargetHasJIT - LLVMTargetHasJIT.restype = LLVMBool - LLVMTargetHasJIT.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasTargetMachine = _libraries['llvm'].LLVMTargetHasTargetMachine - LLVMTargetHasTargetMachine.restype = LLVMBool - LLVMTargetHasTargetMachine.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasAsmBackend = _libraries['llvm'].LLVMTargetHasAsmBackend - LLVMTargetHasAsmBackend.restype = LLVMBool - LLVMTargetHasAsmBackend.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMCreateTargetMachine = _libraries['llvm'].LLVMCreateTargetMachine - LLVMCreateTargetMachine.restype = LLVMTargetMachineRef - LLVMCreateTargetMachine.argtypes = [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] -except AttributeError: - pass -try: - LLVMDisposeTargetMachine = _libraries['llvm'].LLVMDisposeTargetMachine - LLVMDisposeTargetMachine.restype = None - LLVMDisposeTargetMachine.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineTarget = _libraries['llvm'].LLVMGetTargetMachineTarget - LLVMGetTargetMachineTarget.restype = LLVMTargetRef - LLVMGetTargetMachineTarget.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineTriple = _libraries['llvm'].LLVMGetTargetMachineTriple - LLVMGetTargetMachineTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineTriple.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineCPU = _libraries['llvm'].LLVMGetTargetMachineCPU - LLVMGetTargetMachineCPU.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineCPU.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineFeatureString = _libraries['llvm'].LLVMGetTargetMachineFeatureString - LLVMGetTargetMachineFeatureString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineFeatureString.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMCreateTargetDataLayout = _libraries['llvm'].LLVMCreateTargetDataLayout - LLVMCreateTargetDataLayout.restype = LLVMTargetDataRef - LLVMCreateTargetDataLayout.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMSetTargetMachineAsmVerbosity = _libraries['llvm'].LLVMSetTargetMachineAsmVerbosity - LLVMSetTargetMachineAsmVerbosity.restype = None - LLVMSetTargetMachineAsmVerbosity.argtypes = [LLVMTargetMachineRef, LLVMBool] -except AttributeError: - pass -try: - LLVMTargetMachineEmitToFile = _libraries['llvm'].LLVMTargetMachineEmitToFile - LLVMTargetMachineEmitToFile.restype = LLVMBool - LLVMTargetMachineEmitToFile.argtypes = [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMTargetMachineEmitToMemoryBuffer = _libraries['llvm'].LLVMTargetMachineEmitToMemoryBuffer - LLVMTargetMachineEmitToMemoryBuffer.restype = LLVMBool - LLVMTargetMachineEmitToMemoryBuffer.argtypes = [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))] -except AttributeError: - pass -try: - LLVMGetDefaultTargetTriple = _libraries['llvm'].LLVMGetDefaultTargetTriple - LLVMGetDefaultTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDefaultTargetTriple.argtypes = [] -except AttributeError: - pass -try: - LLVMNormalizeTargetTriple = _libraries['llvm'].LLVMNormalizeTargetTriple - LLVMNormalizeTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMNormalizeTargetTriple.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetHostCPUName = _libraries['llvm'].LLVMGetHostCPUName - LLVMGetHostCPUName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetHostCPUName.argtypes = [] -except AttributeError: - pass -try: - LLVMGetHostCPUFeatures = _libraries['llvm'].LLVMGetHostCPUFeatures - LLVMGetHostCPUFeatures.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetHostCPUFeatures.argtypes = [] -except AttributeError: - pass -try: - LLVMAddAnalysisPasses = _libraries['llvm'].LLVMAddAnalysisPasses - LLVMAddAnalysisPasses.restype = None - LLVMAddAnalysisPasses.argtypes = [LLVMTargetMachineRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMLinkInMCJIT = _libraries['llvm'].LLVMLinkInMCJIT - LLVMLinkInMCJIT.restype = None - LLVMLinkInMCJIT.argtypes = [] -except AttributeError: - pass -try: - LLVMLinkInInterpreter = _libraries['llvm'].LLVMLinkInInterpreter - LLVMLinkInInterpreter.restype = None - LLVMLinkInInterpreter.argtypes = [] -except AttributeError: - pass -class struct_LLVMOpaqueGenericValue(Structure): - pass - -LLVMGenericValueRef = ctypes.POINTER(struct_LLVMOpaqueGenericValue) -class struct_LLVMOpaqueExecutionEngine(Structure): - pass - -LLVMExecutionEngineRef = ctypes.POINTER(struct_LLVMOpaqueExecutionEngine) -class struct_LLVMOpaqueMCJITMemoryManager(Structure): - pass - -LLVMMCJITMemoryManagerRef = ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager) -class struct_LLVMMCJITCompilerOptions(Structure): - pass - -struct_LLVMMCJITCompilerOptions._pack_ = 1 # source:False -struct_LLVMMCJITCompilerOptions._fields_ = [ - ('OptLevel', ctypes.c_uint32), - ('CodeModel', LLVMCodeModel), - ('NoFramePointerElim', ctypes.c_int32), - ('EnableFastISel', ctypes.c_int32), - ('MCJMM', ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager)), -] - -try: - LLVMCreateGenericValueOfInt = _libraries['llvm'].LLVMCreateGenericValueOfInt - LLVMCreateGenericValueOfInt.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfInt.argtypes = [LLVMTypeRef, ctypes.c_uint64, LLVMBool] -except AttributeError: - pass -try: - LLVMCreateGenericValueOfPointer = _libraries['llvm'].LLVMCreateGenericValueOfPointer - LLVMCreateGenericValueOfPointer.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfPointer.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMCreateGenericValueOfFloat = _libraries['llvm'].LLVMCreateGenericValueOfFloat - LLVMCreateGenericValueOfFloat.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfFloat.argtypes = [LLVMTypeRef, ctypes.c_double] -except AttributeError: - pass -try: - LLVMGenericValueIntWidth = _libraries['llvm'].LLVMGenericValueIntWidth - LLVMGenericValueIntWidth.restype = ctypes.c_uint32 - LLVMGenericValueIntWidth.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMGenericValueToInt = _libraries['llvm'].LLVMGenericValueToInt - LLVMGenericValueToInt.restype = ctypes.c_uint64 - LLVMGenericValueToInt.argtypes = [LLVMGenericValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGenericValueToPointer = _libraries['llvm'].LLVMGenericValueToPointer - LLVMGenericValueToPointer.restype = ctypes.POINTER(None) - LLVMGenericValueToPointer.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMGenericValueToFloat = _libraries['llvm'].LLVMGenericValueToFloat - LLVMGenericValueToFloat.restype = ctypes.c_double - LLVMGenericValueToFloat.argtypes = [LLVMTypeRef, LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMDisposeGenericValue = _libraries['llvm'].LLVMDisposeGenericValue - LLVMDisposeGenericValue.restype = None - LLVMDisposeGenericValue.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMCreateExecutionEngineForModule = _libraries['llvm'].LLVMCreateExecutionEngineForModule - LLVMCreateExecutionEngineForModule.restype = LLVMBool - LLVMCreateExecutionEngineForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateInterpreterForModule = _libraries['llvm'].LLVMCreateInterpreterForModule - LLVMCreateInterpreterForModule.restype = LLVMBool - LLVMCreateInterpreterForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateJITCompilerForModule = _libraries['llvm'].LLVMCreateJITCompilerForModule - LLVMCreateJITCompilerForModule.restype = LLVMBool - LLVMCreateJITCompilerForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMInitializeMCJITCompilerOptions = _libraries['llvm'].LLVMInitializeMCJITCompilerOptions - LLVMInitializeMCJITCompilerOptions.restype = None - LLVMInitializeMCJITCompilerOptions.argtypes = [ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t] -except AttributeError: - pass -try: - LLVMCreateMCJITCompilerForModule = _libraries['llvm'].LLVMCreateMCJITCompilerForModule - LLVMCreateMCJITCompilerForModule.restype = LLVMBool - LLVMCreateMCJITCompilerForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMDisposeExecutionEngine = _libraries['llvm'].LLVMDisposeExecutionEngine - LLVMDisposeExecutionEngine.restype = None - LLVMDisposeExecutionEngine.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunStaticConstructors = _libraries['llvm'].LLVMRunStaticConstructors - LLVMRunStaticConstructors.restype = None - LLVMRunStaticConstructors.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunStaticDestructors = _libraries['llvm'].LLVMRunStaticDestructors - LLVMRunStaticDestructors.restype = None - LLVMRunStaticDestructors.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunFunctionAsMain = _libraries['llvm'].LLVMRunFunctionAsMain - LLVMRunFunctionAsMain.restype = ctypes.c_int32 - LLVMRunFunctionAsMain.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMRunFunction = _libraries['llvm'].LLVMRunFunction - LLVMRunFunction.restype = LLVMGenericValueRef - LLVMRunFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueGenericValue))] -except AttributeError: - pass -try: - LLVMFreeMachineCodeForFunction = _libraries['llvm'].LLVMFreeMachineCodeForFunction - LLVMFreeMachineCodeForFunction.restype = None - LLVMFreeMachineCodeForFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddModule = _libraries['llvm'].LLVMAddModule - LLVMAddModule.restype = None - LLVMAddModule.argtypes = [LLVMExecutionEngineRef, LLVMModuleRef] -except AttributeError: - pass -try: - LLVMRemoveModule = _libraries['llvm'].LLVMRemoveModule - LLVMRemoveModule.restype = LLVMBool - LLVMRemoveModule.argtypes = [LLVMExecutionEngineRef, LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMFindFunction = _libraries['llvm'].LLVMFindFunction - LLVMFindFunction.restype = LLVMBool - LLVMFindFunction.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMRecompileAndRelinkFunction = _libraries['llvm'].LLVMRecompileAndRelinkFunction - LLVMRecompileAndRelinkFunction.restype = ctypes.POINTER(None) - LLVMRecompileAndRelinkFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetExecutionEngineTargetData = _libraries['llvm'].LLVMGetExecutionEngineTargetData - LLVMGetExecutionEngineTargetData.restype = LLVMTargetDataRef - LLVMGetExecutionEngineTargetData.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMGetExecutionEngineTargetMachine = _libraries['llvm'].LLVMGetExecutionEngineTargetMachine - LLVMGetExecutionEngineTargetMachine.restype = LLVMTargetMachineRef - LLVMGetExecutionEngineTargetMachine.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMAddGlobalMapping = _libraries['llvm'].LLVMAddGlobalMapping - LLVMAddGlobalMapping.restype = None - LLVMAddGlobalMapping.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMGetPointerToGlobal = _libraries['llvm'].LLVMGetPointerToGlobal - LLVMGetPointerToGlobal.restype = ctypes.POINTER(None) - LLVMGetPointerToGlobal.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetGlobalValueAddress = _libraries['llvm'].LLVMGetGlobalValueAddress - LLVMGetGlobalValueAddress.restype = uint64_t - LLVMGetGlobalValueAddress.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFunctionAddress = _libraries['llvm'].LLVMGetFunctionAddress - LLVMGetFunctionAddress.restype = uint64_t - LLVMGetFunctionAddress.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMExecutionEngineGetErrMsg = _libraries['llvm'].LLVMExecutionEngineGetErrMsg - LLVMExecutionEngineGetErrMsg.restype = LLVMBool - LLVMExecutionEngineGetErrMsg.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -LLVMMemoryManagerAllocateCodeSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)) -LLVMMemoryManagerAllocateDataSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32) -LLVMMemoryManagerFinalizeMemoryCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) -LLVMMemoryManagerDestroyCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -try: - LLVMCreateSimpleMCJITMemoryManager = _libraries['llvm'].LLVMCreateSimpleMCJITMemoryManager - LLVMCreateSimpleMCJITMemoryManager.restype = LLVMMCJITMemoryManagerRef - LLVMCreateSimpleMCJITMemoryManager.argtypes = [ctypes.POINTER(None), LLVMMemoryManagerAllocateCodeSectionCallback, LLVMMemoryManagerAllocateDataSectionCallback, LLVMMemoryManagerFinalizeMemoryCallback, LLVMMemoryManagerDestroyCallback] -except AttributeError: - pass -try: - LLVMDisposeMCJITMemoryManager = _libraries['llvm'].LLVMDisposeMCJITMemoryManager - LLVMDisposeMCJITMemoryManager.restype = None - LLVMDisposeMCJITMemoryManager.argtypes = [LLVMMCJITMemoryManagerRef] -except AttributeError: - pass -try: - LLVMCreateGDBRegistrationListener = _libraries['llvm'].LLVMCreateGDBRegistrationListener - LLVMCreateGDBRegistrationListener.restype = LLVMJITEventListenerRef - LLVMCreateGDBRegistrationListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateIntelJITEventListener = _libraries['llvm'].LLVMCreateIntelJITEventListener - LLVMCreateIntelJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreateIntelJITEventListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateOProfileJITEventListener = _libraries['llvm'].LLVMCreateOProfileJITEventListener - LLVMCreateOProfileJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreateOProfileJITEventListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreatePerfJITEventListener = _libraries['llvm'].LLVMCreatePerfJITEventListener - LLVMCreatePerfJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreatePerfJITEventListener.argtypes = [] -except AttributeError: - pass -LLVM_C_IRREADER_H = True # macro -try: - LLVMParseIRInContext = _libraries['llvm'].LLVMParseIRInContext - LLVMParseIRInContext.restype = LLVMBool - LLVMParseIRInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -LLVM_C_INITIALIZATION_H = True # macro -try: - LLVMInitializeTransformUtils = _libraries['llvm'].LLVMInitializeTransformUtils - LLVMInitializeTransformUtils.restype = None - LLVMInitializeTransformUtils.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeScalarOpts = _libraries['llvm'].LLVMInitializeScalarOpts - LLVMInitializeScalarOpts.restype = None - LLVMInitializeScalarOpts.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeObjCARCOpts = _libraries['llvm'].LLVMInitializeObjCARCOpts - LLVMInitializeObjCARCOpts.restype = None - LLVMInitializeObjCARCOpts.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeVectorization = _libraries['llvm'].LLVMInitializeVectorization - LLVMInitializeVectorization.restype = None - LLVMInitializeVectorization.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeInstCombine = _libraries['llvm'].LLVMInitializeInstCombine - LLVMInitializeInstCombine.restype = None - LLVMInitializeInstCombine.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeAggressiveInstCombiner = _libraries['llvm'].LLVMInitializeAggressiveInstCombiner - LLVMInitializeAggressiveInstCombiner.restype = None - LLVMInitializeAggressiveInstCombiner.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeIPO = _libraries['llvm'].LLVMInitializeIPO - LLVMInitializeIPO.restype = None - LLVMInitializeIPO.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeInstrumentation = _libraries['llvm'].LLVMInitializeInstrumentation - LLVMInitializeInstrumentation.restype = None - LLVMInitializeInstrumentation.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeAnalysis = _libraries['llvm'].LLVMInitializeAnalysis - LLVMInitializeAnalysis.restype = None - LLVMInitializeAnalysis.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeIPA = _libraries['llvm'].LLVMInitializeIPA - LLVMInitializeIPA.restype = None - LLVMInitializeIPA.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeCodeGen = _libraries['llvm'].LLVMInitializeCodeGen - LLVMInitializeCodeGen.restype = None - LLVMInitializeCodeGen.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeTarget = _libraries['llvm'].LLVMInitializeTarget - LLVMInitializeTarget.restype = None - LLVMInitializeTarget.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -LLVM_C_LLJIT_H = True # macro -LLVM_C_ORC_H = True # macro -LLVMOrcJITTargetAddress = ctypes.c_uint64 -LLVMOrcExecutorAddress = ctypes.c_uint64 - -# values for enumeration 'c__EA_LLVMJITSymbolGenericFlags' -c__EA_LLVMJITSymbolGenericFlags__enumvalues = { - 1: 'LLVMJITSymbolGenericFlagsExported', - 2: 'LLVMJITSymbolGenericFlagsWeak', - 4: 'LLVMJITSymbolGenericFlagsCallable', - 8: 'LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly', -} -LLVMJITSymbolGenericFlagsExported = 1 -LLVMJITSymbolGenericFlagsWeak = 2 -LLVMJITSymbolGenericFlagsCallable = 4 -LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly = 8 -c__EA_LLVMJITSymbolGenericFlags = ctypes.c_uint32 # enum -LLVMJITSymbolGenericFlags = c__EA_LLVMJITSymbolGenericFlags -LLVMJITSymbolGenericFlags__enumvalues = c__EA_LLVMJITSymbolGenericFlags__enumvalues -LLVMJITSymbolTargetFlags = ctypes.c_ubyte -class struct_c__SA_LLVMJITSymbolFlags(Structure): - pass - -struct_c__SA_LLVMJITSymbolFlags._pack_ = 1 # source:False -struct_c__SA_LLVMJITSymbolFlags._fields_ = [ - ('GenericFlags', ctypes.c_ubyte), - ('TargetFlags', ctypes.c_ubyte), -] - -LLVMJITSymbolFlags = struct_c__SA_LLVMJITSymbolFlags -class struct_c__SA_LLVMJITEvaluatedSymbol(Structure): - pass - -struct_c__SA_LLVMJITEvaluatedSymbol._pack_ = 1 # source:False -struct_c__SA_LLVMJITEvaluatedSymbol._fields_ = [ - ('Address', ctypes.c_uint64), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LLVMJITEvaluatedSymbol = struct_c__SA_LLVMJITEvaluatedSymbol -class struct_LLVMOrcOpaqueExecutionSession(Structure): - pass - -LLVMOrcExecutionSessionRef = ctypes.POINTER(struct_LLVMOrcOpaqueExecutionSession) -LLVMOrcErrorReporterFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOpaqueError)) -class struct_LLVMOrcOpaqueSymbolStringPool(Structure): - pass - -LLVMOrcSymbolStringPoolRef = ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPool) -class struct_LLVMOrcOpaqueSymbolStringPoolEntry(Structure): - pass - -LLVMOrcSymbolStringPoolEntryRef = ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry) -class struct_c__SA_LLVMOrcCSymbolFlagsMapPair(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolFlagsMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolFlagsMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LLVMOrcCSymbolFlagsMapPair = struct_c__SA_LLVMOrcCSymbolFlagsMapPair -LLVMOrcCSymbolFlagsMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCSymbolFlagsMapPair) -class struct_c__SA_LLVMJITCSymbolMapPair(Structure): - pass - -struct_c__SA_LLVMJITCSymbolMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMJITCSymbolMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Sym', LLVMJITEvaluatedSymbol), -] - -LLVMJITCSymbolMapPair = struct_c__SA_LLVMJITCSymbolMapPair -LLVMOrcCSymbolMapPairs = ctypes.POINTER(struct_c__SA_LLVMJITCSymbolMapPair) -class struct_c__SA_LLVMOrcCSymbolAliasMapEntry(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolAliasMapEntry._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolAliasMapEntry._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LLVMOrcCSymbolAliasMapEntry = struct_c__SA_LLVMOrcCSymbolAliasMapEntry -class struct_c__SA_LLVMOrcCSymbolAliasMapPair(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolAliasMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolAliasMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Entry', LLVMOrcCSymbolAliasMapEntry), -] - -LLVMOrcCSymbolAliasMapPair = struct_c__SA_LLVMOrcCSymbolAliasMapPair -LLVMOrcCSymbolAliasMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCSymbolAliasMapPair) -class struct_LLVMOrcOpaqueJITDylib(Structure): - pass - -LLVMOrcJITDylibRef = ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib) -class struct_c__SA_LLVMOrcCSymbolsList(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolsList._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolsList._fields_ = [ - ('Symbols', ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry))), - ('Length', ctypes.c_uint64), -] - -LLVMOrcCSymbolsList = struct_c__SA_LLVMOrcCSymbolsList -class struct_c__SA_LLVMOrcCDependenceMapPair(Structure): - pass - -struct_c__SA_LLVMOrcCDependenceMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCDependenceMapPair._fields_ = [ - ('JD', ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib)), - ('Names', LLVMOrcCSymbolsList), -] - -LLVMOrcCDependenceMapPair = struct_c__SA_LLVMOrcCDependenceMapPair -LLVMOrcCDependenceMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCDependenceMapPair) - -# values for enumeration 'c__EA_LLVMOrcLookupKind' -c__EA_LLVMOrcLookupKind__enumvalues = { - 0: 'LLVMOrcLookupKindStatic', - 1: 'LLVMOrcLookupKindDLSym', -} -LLVMOrcLookupKindStatic = 0 -LLVMOrcLookupKindDLSym = 1 -c__EA_LLVMOrcLookupKind = ctypes.c_uint32 # enum -LLVMOrcLookupKind = c__EA_LLVMOrcLookupKind -LLVMOrcLookupKind__enumvalues = c__EA_LLVMOrcLookupKind__enumvalues - -# values for enumeration 'c__EA_LLVMOrcJITDylibLookupFlags' -c__EA_LLVMOrcJITDylibLookupFlags__enumvalues = { - 0: 'LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly', - 1: 'LLVMOrcJITDylibLookupFlagsMatchAllSymbols', -} -LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly = 0 -LLVMOrcJITDylibLookupFlagsMatchAllSymbols = 1 -c__EA_LLVMOrcJITDylibLookupFlags = ctypes.c_uint32 # enum -LLVMOrcJITDylibLookupFlags = c__EA_LLVMOrcJITDylibLookupFlags -LLVMOrcJITDylibLookupFlags__enumvalues = c__EA_LLVMOrcJITDylibLookupFlags__enumvalues - -# values for enumeration 'c__EA_LLVMOrcSymbolLookupFlags' -c__EA_LLVMOrcSymbolLookupFlags__enumvalues = { - 0: 'LLVMOrcSymbolLookupFlagsRequiredSymbol', - 1: 'LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol', -} -LLVMOrcSymbolLookupFlagsRequiredSymbol = 0 -LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol = 1 -c__EA_LLVMOrcSymbolLookupFlags = ctypes.c_uint32 # enum -LLVMOrcSymbolLookupFlags = c__EA_LLVMOrcSymbolLookupFlags -LLVMOrcSymbolLookupFlags__enumvalues = c__EA_LLVMOrcSymbolLookupFlags__enumvalues -class struct_c__SA_LLVMOrcCLookupSetElement(Structure): - pass - -struct_c__SA_LLVMOrcCLookupSetElement._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCLookupSetElement._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('LookupFlags', LLVMOrcSymbolLookupFlags), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -LLVMOrcCLookupSetElement = struct_c__SA_LLVMOrcCLookupSetElement -LLVMOrcCLookupSet = ctypes.POINTER(struct_c__SA_LLVMOrcCLookupSetElement) -class struct_LLVMOrcOpaqueMaterializationUnit(Structure): - pass - -LLVMOrcMaterializationUnitRef = ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationUnit) -class struct_LLVMOrcOpaqueMaterializationResponsibility(Structure): - pass - -LLVMOrcMaterializationResponsibilityRef = ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility) -LLVMOrcMaterializationUnitMaterializeFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) -LLVMOrcMaterializationUnitDiscardFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) -LLVMOrcMaterializationUnitDestroyFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_LLVMOrcOpaqueResourceTracker(Structure): - pass - -LLVMOrcResourceTrackerRef = ctypes.POINTER(struct_LLVMOrcOpaqueResourceTracker) -class struct_LLVMOrcOpaqueDefinitionGenerator(Structure): - pass - -LLVMOrcDefinitionGeneratorRef = ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator) -class struct_LLVMOrcOpaqueLookupState(Structure): - pass - -LLVMOrcLookupStateRef = ctypes.POINTER(struct_LLVMOrcOpaqueLookupState) -LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLookupState)), c__EA_LLVMOrcLookupKind, ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), c__EA_LLVMOrcJITDylibLookupFlags, ctypes.POINTER(struct_c__SA_LLVMOrcCLookupSetElement), ctypes.c_uint64) -LLVMOrcSymbolPredicate = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) -class struct_LLVMOrcOpaqueThreadSafeContext(Structure): - pass - -LLVMOrcThreadSafeContextRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeContext) -class struct_LLVMOrcOpaqueThreadSafeModule(Structure): - pass - -LLVMOrcThreadSafeModuleRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule) -LLVMOrcGenericIRModuleOperationFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOpaqueModule)) -class struct_LLVMOrcOpaqueJITTargetMachineBuilder(Structure): - pass - -LLVMOrcJITTargetMachineBuilderRef = ctypes.POINTER(struct_LLVMOrcOpaqueJITTargetMachineBuilder) -class struct_LLVMOrcOpaqueObjectLayer(Structure): - pass - -LLVMOrcObjectLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectLayer) -class struct_LLVMOrcOpaqueObjectLinkingLayer(Structure): - pass - -LLVMOrcObjectLinkingLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectLinkingLayer) -class struct_LLVMOrcOpaqueIRTransformLayer(Structure): - pass - -LLVMOrcIRTransformLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueIRTransformLayer) -LLVMOrcIRTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule)), ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) -class struct_LLVMOrcOpaqueObjectTransformLayer(Structure): - pass - -LLVMOrcObjectTransformLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectTransformLayer) -LLVMOrcObjectTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))) -class struct_LLVMOrcOpaqueIndirectStubsManager(Structure): - pass - -LLVMOrcIndirectStubsManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueIndirectStubsManager) -class struct_LLVMOrcOpaqueLazyCallThroughManager(Structure): - pass - -LLVMOrcLazyCallThroughManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueLazyCallThroughManager) -class struct_LLVMOrcOpaqueDumpObjects(Structure): - pass - -LLVMOrcDumpObjectsRef = ctypes.POINTER(struct_LLVMOrcOpaqueDumpObjects) -try: - LLVMOrcExecutionSessionSetErrorReporter = _libraries['llvm'].LLVMOrcExecutionSessionSetErrorReporter - LLVMOrcExecutionSessionSetErrorReporter.restype = None - LLVMOrcExecutionSessionSetErrorReporter.argtypes = [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionGetSymbolStringPool = _libraries['llvm'].LLVMOrcExecutionSessionGetSymbolStringPool - LLVMOrcExecutionSessionGetSymbolStringPool.restype = LLVMOrcSymbolStringPoolRef - LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = [LLVMOrcExecutionSessionRef] -except AttributeError: - pass -try: - LLVMOrcSymbolStringPoolClearDeadEntries = _libraries['llvm'].LLVMOrcSymbolStringPoolClearDeadEntries - LLVMOrcSymbolStringPoolClearDeadEntries.restype = None - LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = [LLVMOrcSymbolStringPoolRef] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionIntern = _libraries['llvm'].LLVMOrcExecutionSessionIntern - LLVMOrcExecutionSessionIntern.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcExecutionSessionIntern.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcRetainSymbolStringPoolEntry = _libraries['llvm'].LLVMOrcRetainSymbolStringPoolEntry - LLVMOrcRetainSymbolStringPoolEntry.restype = None - LLVMOrcRetainSymbolStringPoolEntry.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcReleaseSymbolStringPoolEntry = _libraries['llvm'].LLVMOrcReleaseSymbolStringPoolEntry - LLVMOrcReleaseSymbolStringPoolEntry.restype = None - LLVMOrcReleaseSymbolStringPoolEntry.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcSymbolStringPoolEntryStr = _libraries['llvm'].LLVMOrcSymbolStringPoolEntryStr - LLVMOrcSymbolStringPoolEntryStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcSymbolStringPoolEntryStr.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcReleaseResourceTracker = _libraries['llvm'].LLVMOrcReleaseResourceTracker - LLVMOrcReleaseResourceTracker.restype = None - LLVMOrcReleaseResourceTracker.argtypes = [LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcResourceTrackerTransferTo = _libraries['llvm'].LLVMOrcResourceTrackerTransferTo - LLVMOrcResourceTrackerTransferTo.restype = None - LLVMOrcResourceTrackerTransferTo.argtypes = [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcResourceTrackerRemove = _libraries['llvm'].LLVMOrcResourceTrackerRemove - LLVMOrcResourceTrackerRemove.restype = LLVMErrorRef - LLVMOrcResourceTrackerRemove.argtypes = [LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcDisposeDefinitionGenerator = _libraries['llvm'].LLVMOrcDisposeDefinitionGenerator - LLVMOrcDisposeDefinitionGenerator.restype = None - LLVMOrcDisposeDefinitionGenerator.argtypes = [LLVMOrcDefinitionGeneratorRef] -except AttributeError: - pass -try: - LLVMOrcDisposeMaterializationUnit = _libraries['llvm'].LLVMOrcDisposeMaterializationUnit - LLVMOrcDisposeMaterializationUnit.restype = None - LLVMOrcDisposeMaterializationUnit.argtypes = [LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcCreateCustomMaterializationUnit = _libraries['llvm'].LLVMOrcCreateCustomMaterializationUnit - LLVMOrcCreateCustomMaterializationUnit.restype = LLVMOrcMaterializationUnitRef - LLVMOrcCreateCustomMaterializationUnit.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] -except AttributeError: - pass -try: - LLVMOrcAbsoluteSymbols = _libraries['llvm'].LLVMOrcAbsoluteSymbols - LLVMOrcAbsoluteSymbols.restype = LLVMOrcMaterializationUnitRef - LLVMOrcAbsoluteSymbols.argtypes = [LLVMOrcCSymbolMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcLazyReexports = _libraries['llvm'].LLVMOrcLazyReexports - LLVMOrcLazyReexports.restype = LLVMOrcMaterializationUnitRef - LLVMOrcLazyReexports.argtypes = [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcDisposeMaterializationResponsibility = _libraries['llvm'].LLVMOrcDisposeMaterializationResponsibility - LLVMOrcDisposeMaterializationResponsibility.restype = None - LLVMOrcDisposeMaterializationResponsibility.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetTargetDylib = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetTargetDylib - LLVMOrcMaterializationResponsibilityGetTargetDylib.restype = LLVMOrcJITDylibRef - LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetExecutionSession = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetExecutionSession - LLVMOrcMaterializationResponsibilityGetExecutionSession.restype = LLVMOrcExecutionSessionRef - LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetSymbols = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetSymbols - LLVMOrcMaterializationResponsibilityGetSymbols.restype = LLVMOrcCSymbolFlagsMapPairs - LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMOrcDisposeCSymbolFlagsMap = _libraries['llvm'].LLVMOrcDisposeCSymbolFlagsMap - LLVMOrcDisposeCSymbolFlagsMap.restype = None - LLVMOrcDisposeCSymbolFlagsMap.argtypes = [LLVMOrcCSymbolFlagsMapPairs] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetInitializerSymbol = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetInitializerSymbol - LLVMOrcMaterializationResponsibilityGetInitializerSymbol.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetRequestedSymbols = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetRequestedSymbols - LLVMOrcMaterializationResponsibilityGetRequestedSymbols.restype = ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) - LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMOrcDisposeSymbols = _libraries['llvm'].LLVMOrcDisposeSymbols - LLVMOrcDisposeSymbols.restype = None - LLVMOrcDisposeSymbols.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry))] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityNotifyResolved = _libraries['llvm'].LLVMOrcMaterializationResponsibilityNotifyResolved - LLVMOrcMaterializationResponsibilityNotifyResolved.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityNotifyEmitted = _libraries['llvm'].LLVMOrcMaterializationResponsibilityNotifyEmitted - LLVMOrcMaterializationResponsibilityNotifyEmitted.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityDefineMaterializing = _libraries['llvm'].LLVMOrcMaterializationResponsibilityDefineMaterializing - LLVMOrcMaterializationResponsibilityDefineMaterializing.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityFailMaterialization = _libraries['llvm'].LLVMOrcMaterializationResponsibilityFailMaterialization - LLVMOrcMaterializationResponsibilityFailMaterialization.restype = None - LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityReplace = _libraries['llvm'].LLVMOrcMaterializationResponsibilityReplace - LLVMOrcMaterializationResponsibilityReplace.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityReplace.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityDelegate = _libraries['llvm'].LLVMOrcMaterializationResponsibilityDelegate - LLVMOrcMaterializationResponsibilityDelegate.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityDelegate.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), size_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility))] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityAddDependencies = _libraries['llvm'].LLVMOrcMaterializationResponsibilityAddDependencies - LLVMOrcMaterializationResponsibilityAddDependencies.restype = None - LLVMOrcMaterializationResponsibilityAddDependencies.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcCDependenceMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityAddDependenciesForAll = _libraries['llvm'].LLVMOrcMaterializationResponsibilityAddDependenciesForAll - LLVMOrcMaterializationResponsibilityAddDependenciesForAll.restype = None - LLVMOrcMaterializationResponsibilityAddDependenciesForAll.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCDependenceMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionCreateBareJITDylib = _libraries['llvm'].LLVMOrcExecutionSessionCreateBareJITDylib - LLVMOrcExecutionSessionCreateBareJITDylib.restype = LLVMOrcJITDylibRef - LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionCreateJITDylib = _libraries['llvm'].LLVMOrcExecutionSessionCreateJITDylib - LLVMOrcExecutionSessionCreateJITDylib.restype = LLVMErrorRef - LLVMOrcExecutionSessionCreateJITDylib.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionGetJITDylibByName = _libraries['llvm'].LLVMOrcExecutionSessionGetJITDylibByName - LLVMOrcExecutionSessionGetJITDylibByName.restype = LLVMOrcJITDylibRef - LLVMOrcExecutionSessionGetJITDylibByName.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcJITDylibCreateResourceTracker = _libraries['llvm'].LLVMOrcJITDylibCreateResourceTracker - LLVMOrcJITDylibCreateResourceTracker.restype = LLVMOrcResourceTrackerRef - LLVMOrcJITDylibCreateResourceTracker.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibGetDefaultResourceTracker = _libraries['llvm'].LLVMOrcJITDylibGetDefaultResourceTracker - LLVMOrcJITDylibGetDefaultResourceTracker.restype = LLVMOrcResourceTrackerRef - LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibDefine = _libraries['llvm'].LLVMOrcJITDylibDefine - LLVMOrcJITDylibDefine.restype = LLVMErrorRef - LLVMOrcJITDylibDefine.argtypes = [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibClear = _libraries['llvm'].LLVMOrcJITDylibClear - LLVMOrcJITDylibClear.restype = LLVMErrorRef - LLVMOrcJITDylibClear.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibAddGenerator = _libraries['llvm'].LLVMOrcJITDylibAddGenerator - LLVMOrcJITDylibAddGenerator.restype = None - LLVMOrcJITDylibAddGenerator.argtypes = [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] -except AttributeError: - pass -try: - LLVMOrcCreateCustomCAPIDefinitionGenerator = _libraries['llvm'].LLVMOrcCreateCustomCAPIDefinitionGenerator - LLVMOrcCreateCustomCAPIDefinitionGenerator.restype = LLVMOrcDefinitionGeneratorRef - LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess = _libraries['llvm'].LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.restype = LLVMErrorRef - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath = _libraries['llvm'].LLVMOrcCreateDynamicLibrarySearchGeneratorForPath - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.restype = LLVMErrorRef - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateStaticLibrarySearchGeneratorForPath = _libraries['llvm'].LLVMOrcCreateStaticLibrarySearchGeneratorForPath - LLVMOrcCreateStaticLibrarySearchGeneratorForPath.restype = LLVMErrorRef - LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcCreateNewThreadSafeContext = _libraries['llvm'].LLVMOrcCreateNewThreadSafeContext - LLVMOrcCreateNewThreadSafeContext.restype = LLVMOrcThreadSafeContextRef - LLVMOrcCreateNewThreadSafeContext.argtypes = [] -except AttributeError: - pass -try: - LLVMOrcThreadSafeContextGetContext = _libraries['llvm'].LLVMOrcThreadSafeContextGetContext - LLVMOrcThreadSafeContextGetContext.restype = LLVMContextRef - LLVMOrcThreadSafeContextGetContext.argtypes = [LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcDisposeThreadSafeContext = _libraries['llvm'].LLVMOrcDisposeThreadSafeContext - LLVMOrcDisposeThreadSafeContext.restype = None - LLVMOrcDisposeThreadSafeContext.argtypes = [LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcCreateNewThreadSafeModule = _libraries['llvm'].LLVMOrcCreateNewThreadSafeModule - LLVMOrcCreateNewThreadSafeModule.restype = LLVMOrcThreadSafeModuleRef - LLVMOrcCreateNewThreadSafeModule.argtypes = [LLVMModuleRef, LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcDisposeThreadSafeModule = _libraries['llvm'].LLVMOrcDisposeThreadSafeModule - LLVMOrcDisposeThreadSafeModule.restype = None - LLVMOrcDisposeThreadSafeModule.argtypes = [LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcThreadSafeModuleWithModuleDo = _libraries['llvm'].LLVMOrcThreadSafeModuleWithModuleDo - LLVMOrcThreadSafeModuleWithModuleDo.restype = LLVMErrorRef - LLVMOrcThreadSafeModuleWithModuleDo.argtypes = [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderDetectHost = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderDetectHost - LLVMOrcJITTargetMachineBuilderDetectHost.restype = LLVMErrorRef - LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueJITTargetMachineBuilder))] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.restype = LLVMOrcJITTargetMachineBuilderRef - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMOrcDisposeJITTargetMachineBuilder = _libraries['llvm'].LLVMOrcDisposeJITTargetMachineBuilder - LLVMOrcDisposeJITTargetMachineBuilder.restype = None - LLVMOrcDisposeJITTargetMachineBuilder.argtypes = [LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderGetTargetTriple = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderGetTargetTriple - LLVMOrcJITTargetMachineBuilderGetTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = [LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderSetTargetTriple = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderSetTargetTriple - LLVMOrcJITTargetMachineBuilderSetTargetTriple.restype = None - LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcObjectLayerAddObjectFile = _libraries['llvm'].LLVMOrcObjectLayerAddObjectFile - LLVMOrcObjectLayerAddObjectFile.restype = LLVMErrorRef - LLVMOrcObjectLayerAddObjectFile.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcObjectLayerAddObjectFileWithRT = _libraries['llvm'].LLVMOrcObjectLayerAddObjectFileWithRT - LLVMOrcObjectLayerAddObjectFileWithRT.restype = LLVMErrorRef - LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcObjectLayerEmit = _libraries['llvm'].LLVMOrcObjectLayerEmit - LLVMOrcObjectLayerEmit.restype = None - LLVMOrcObjectLayerEmit.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcDisposeObjectLayer = _libraries['llvm'].LLVMOrcDisposeObjectLayer - LLVMOrcDisposeObjectLayer.restype = None - LLVMOrcDisposeObjectLayer.argtypes = [LLVMOrcObjectLayerRef] -except AttributeError: - pass -try: - LLVMOrcIRTransformLayerEmit = _libraries['llvm'].LLVMOrcIRTransformLayerEmit - LLVMOrcIRTransformLayerEmit.restype = None - LLVMOrcIRTransformLayerEmit.argtypes = [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcIRTransformLayerSetTransform = _libraries['llvm'].LLVMOrcIRTransformLayerSetTransform - LLVMOrcIRTransformLayerSetTransform.restype = None - LLVMOrcIRTransformLayerSetTransform.argtypes = [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcObjectTransformLayerSetTransform = _libraries['llvm'].LLVMOrcObjectTransformLayerSetTransform - LLVMOrcObjectTransformLayerSetTransform.restype = None - LLVMOrcObjectTransformLayerSetTransform.argtypes = [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateLocalIndirectStubsManager = _libraries['llvm'].LLVMOrcCreateLocalIndirectStubsManager - LLVMOrcCreateLocalIndirectStubsManager.restype = LLVMOrcIndirectStubsManagerRef - LLVMOrcCreateLocalIndirectStubsManager.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcDisposeIndirectStubsManager = _libraries['llvm'].LLVMOrcDisposeIndirectStubsManager - LLVMOrcDisposeIndirectStubsManager.restype = None - LLVMOrcDisposeIndirectStubsManager.argtypes = [LLVMOrcIndirectStubsManagerRef] -except AttributeError: - pass -try: - LLVMOrcCreateLocalLazyCallThroughManager = _libraries['llvm'].LLVMOrcCreateLocalLazyCallThroughManager - LLVMOrcCreateLocalLazyCallThroughManager.restype = LLVMErrorRef - LLVMOrcCreateLocalLazyCallThroughManager.argtypes = [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLazyCallThroughManager))] -except AttributeError: - pass -try: - LLVMOrcDisposeLazyCallThroughManager = _libraries['llvm'].LLVMOrcDisposeLazyCallThroughManager - LLVMOrcDisposeLazyCallThroughManager.restype = None - LLVMOrcDisposeLazyCallThroughManager.argtypes = [LLVMOrcLazyCallThroughManagerRef] -except AttributeError: - pass -try: - LLVMOrcCreateDumpObjects = _libraries['llvm'].LLVMOrcCreateDumpObjects - LLVMOrcCreateDumpObjects.restype = LLVMOrcDumpObjectsRef - LLVMOrcCreateDumpObjects.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcDisposeDumpObjects = _libraries['llvm'].LLVMOrcDisposeDumpObjects - LLVMOrcDisposeDumpObjects.restype = None - LLVMOrcDisposeDumpObjects.argtypes = [LLVMOrcDumpObjectsRef] -except AttributeError: - pass -try: - LLVMOrcDumpObjects_CallOperator = _libraries['llvm'].LLVMOrcDumpObjects_CallOperator - LLVMOrcDumpObjects_CallOperator.restype = LLVMErrorRef - LLVMOrcDumpObjects_CallOperator.argtypes = [LLVMOrcDumpObjectsRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))] -except AttributeError: - pass -LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOrcOpaqueObjectLayer), ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueExecutionSession), ctypes.POINTER(ctypes.c_char)) -class struct_LLVMOrcOpaqueLLJITBuilder(Structure): - pass - -LLVMOrcLLJITBuilderRef = ctypes.POINTER(struct_LLVMOrcOpaqueLLJITBuilder) -class struct_LLVMOrcOpaqueLLJIT(Structure): - pass - -LLVMOrcLLJITRef = ctypes.POINTER(struct_LLVMOrcOpaqueLLJIT) -try: - LLVMOrcCreateLLJITBuilder = _libraries['llvm'].LLVMOrcCreateLLJITBuilder - LLVMOrcCreateLLJITBuilder.restype = LLVMOrcLLJITBuilderRef - LLVMOrcCreateLLJITBuilder.argtypes = [] -except AttributeError: - pass -try: - LLVMOrcDisposeLLJITBuilder = _libraries['llvm'].LLVMOrcDisposeLLJITBuilder - LLVMOrcDisposeLLJITBuilder.restype = None - LLVMOrcDisposeLLJITBuilder.argtypes = [LLVMOrcLLJITBuilderRef] -except AttributeError: - pass -try: - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder = _libraries['llvm'].LLVMOrcLLJITBuilderSetJITTargetMachineBuilder - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.restype = None - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.argtypes = [LLVMOrcLLJITBuilderRef, LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator = _libraries['llvm'].LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.restype = None - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.argtypes = [LLVMOrcLLJITBuilderRef, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateLLJIT = _libraries['llvm'].LLVMOrcCreateLLJIT - LLVMOrcCreateLLJIT.restype = LLVMErrorRef - LLVMOrcCreateLLJIT.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLLJIT)), LLVMOrcLLJITBuilderRef] -except AttributeError: - pass -try: - LLVMOrcDisposeLLJIT = _libraries['llvm'].LLVMOrcDisposeLLJIT - LLVMOrcDisposeLLJIT.restype = LLVMErrorRef - LLVMOrcDisposeLLJIT.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetExecutionSession = _libraries['llvm'].LLVMOrcLLJITGetExecutionSession - LLVMOrcLLJITGetExecutionSession.restype = LLVMOrcExecutionSessionRef - LLVMOrcLLJITGetExecutionSession.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetMainJITDylib = _libraries['llvm'].LLVMOrcLLJITGetMainJITDylib - LLVMOrcLLJITGetMainJITDylib.restype = LLVMOrcJITDylibRef - LLVMOrcLLJITGetMainJITDylib.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetTripleString = _libraries['llvm'].LLVMOrcLLJITGetTripleString - LLVMOrcLLJITGetTripleString.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcLLJITGetTripleString.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetGlobalPrefix = _libraries['llvm'].LLVMOrcLLJITGetGlobalPrefix - LLVMOrcLLJITGetGlobalPrefix.restype = ctypes.c_char - LLVMOrcLLJITGetGlobalPrefix.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITMangleAndIntern = _libraries['llvm'].LLVMOrcLLJITMangleAndIntern - LLVMOrcLLJITMangleAndIntern.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcLLJITMangleAndIntern.argtypes = [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcLLJITAddObjectFile = _libraries['llvm'].LLVMOrcLLJITAddObjectFile - LLVMOrcLLJITAddObjectFile.restype = LLVMErrorRef - LLVMOrcLLJITAddObjectFile.argtypes = [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddObjectFileWithRT = _libraries['llvm'].LLVMOrcLLJITAddObjectFileWithRT - LLVMOrcLLJITAddObjectFileWithRT.restype = LLVMErrorRef - LLVMOrcLLJITAddObjectFileWithRT.argtypes = [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddLLVMIRModule = _libraries['llvm'].LLVMOrcLLJITAddLLVMIRModule - LLVMOrcLLJITAddLLVMIRModule.restype = LLVMErrorRef - LLVMOrcLLJITAddLLVMIRModule.argtypes = [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddLLVMIRModuleWithRT = _libraries['llvm'].LLVMOrcLLJITAddLLVMIRModuleWithRT - LLVMOrcLLJITAddLLVMIRModuleWithRT.restype = LLVMErrorRef - LLVMOrcLLJITAddLLVMIRModuleWithRT.argtypes = [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcLLJITLookup = _libraries['llvm'].LLVMOrcLLJITLookup - LLVMOrcLLJITLookup.restype = LLVMErrorRef - LLVMOrcLLJITLookup.argtypes = [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcLLJITGetObjLinkingLayer = _libraries['llvm'].LLVMOrcLLJITGetObjLinkingLayer - LLVMOrcLLJITGetObjLinkingLayer.restype = LLVMOrcObjectLayerRef - LLVMOrcLLJITGetObjLinkingLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetObjTransformLayer = _libraries['llvm'].LLVMOrcLLJITGetObjTransformLayer - LLVMOrcLLJITGetObjTransformLayer.restype = LLVMOrcObjectTransformLayerRef - LLVMOrcLLJITGetObjTransformLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetIRTransformLayer = _libraries['llvm'].LLVMOrcLLJITGetIRTransformLayer - LLVMOrcLLJITGetIRTransformLayer.restype = LLVMOrcIRTransformLayerRef - LLVMOrcLLJITGetIRTransformLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetDataLayoutStr = _libraries['llvm'].LLVMOrcLLJITGetDataLayoutStr - LLVMOrcLLJITGetDataLayoutStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcLLJITGetDataLayoutStr.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -LLVM_C_LINKER_H = True # macro - -# values for enumeration 'c__EA_LLVMLinkerMode' -c__EA_LLVMLinkerMode__enumvalues = { - 0: 'LLVMLinkerDestroySource', - 1: 'LLVMLinkerPreserveSource_Removed', -} -LLVMLinkerDestroySource = 0 -LLVMLinkerPreserveSource_Removed = 1 -c__EA_LLVMLinkerMode = ctypes.c_uint32 # enum -LLVMLinkerMode = c__EA_LLVMLinkerMode -LLVMLinkerMode__enumvalues = c__EA_LLVMLinkerMode__enumvalues -try: - LLVMLinkModules2 = _libraries['llvm'].LLVMLinkModules2 - LLVMLinkModules2.restype = LLVMBool - LLVMLinkModules2.argtypes = [LLVMModuleRef, LLVMModuleRef] -except AttributeError: - pass -LLVM_C_OBJECT_H = True # macro -class struct_LLVMOpaqueSectionIterator(Structure): - pass - -LLVMSectionIteratorRef = ctypes.POINTER(struct_LLVMOpaqueSectionIterator) -class struct_LLVMOpaqueSymbolIterator(Structure): - pass - -LLVMSymbolIteratorRef = ctypes.POINTER(struct_LLVMOpaqueSymbolIterator) -class struct_LLVMOpaqueRelocationIterator(Structure): - pass - -LLVMRelocationIteratorRef = ctypes.POINTER(struct_LLVMOpaqueRelocationIterator) - -# values for enumeration 'c__EA_LLVMBinaryType' -c__EA_LLVMBinaryType__enumvalues = { - 0: 'LLVMBinaryTypeArchive', - 1: 'LLVMBinaryTypeMachOUniversalBinary', - 2: 'LLVMBinaryTypeCOFFImportFile', - 3: 'LLVMBinaryTypeIR', - 4: 'LLVMBinaryTypeWinRes', - 5: 'LLVMBinaryTypeCOFF', - 6: 'LLVMBinaryTypeELF32L', - 7: 'LLVMBinaryTypeELF32B', - 8: 'LLVMBinaryTypeELF64L', - 9: 'LLVMBinaryTypeELF64B', - 10: 'LLVMBinaryTypeMachO32L', - 11: 'LLVMBinaryTypeMachO32B', - 12: 'LLVMBinaryTypeMachO64L', - 13: 'LLVMBinaryTypeMachO64B', - 14: 'LLVMBinaryTypeWasm', -} -LLVMBinaryTypeArchive = 0 -LLVMBinaryTypeMachOUniversalBinary = 1 -LLVMBinaryTypeCOFFImportFile = 2 -LLVMBinaryTypeIR = 3 -LLVMBinaryTypeWinRes = 4 -LLVMBinaryTypeCOFF = 5 -LLVMBinaryTypeELF32L = 6 -LLVMBinaryTypeELF32B = 7 -LLVMBinaryTypeELF64L = 8 -LLVMBinaryTypeELF64B = 9 -LLVMBinaryTypeMachO32L = 10 -LLVMBinaryTypeMachO32B = 11 -LLVMBinaryTypeMachO64L = 12 -LLVMBinaryTypeMachO64B = 13 -LLVMBinaryTypeWasm = 14 -c__EA_LLVMBinaryType = ctypes.c_uint32 # enum -LLVMBinaryType = c__EA_LLVMBinaryType -LLVMBinaryType__enumvalues = c__EA_LLVMBinaryType__enumvalues -try: - LLVMCreateBinary = _libraries['llvm'].LLVMCreateBinary - LLVMCreateBinary.restype = LLVMBinaryRef - LLVMCreateBinary.argtypes = [LLVMMemoryBufferRef, LLVMContextRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMDisposeBinary = _libraries['llvm'].LLVMDisposeBinary - LLVMDisposeBinary.restype = None - LLVMDisposeBinary.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMBinaryCopyMemoryBuffer = _libraries['llvm'].LLVMBinaryCopyMemoryBuffer - LLVMBinaryCopyMemoryBuffer.restype = LLVMMemoryBufferRef - LLVMBinaryCopyMemoryBuffer.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMBinaryGetType = _libraries['llvm'].LLVMBinaryGetType - LLVMBinaryGetType.restype = LLVMBinaryType - LLVMBinaryGetType.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMMachOUniversalBinaryCopyObjectForArch = _libraries['llvm'].LLVMMachOUniversalBinaryCopyObjectForArch - LLVMMachOUniversalBinaryCopyObjectForArch.restype = LLVMBinaryRef - LLVMMachOUniversalBinaryCopyObjectForArch.argtypes = [LLVMBinaryRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMObjectFileCopySectionIterator = _libraries['llvm'].LLVMObjectFileCopySectionIterator - LLVMObjectFileCopySectionIterator.restype = LLVMSectionIteratorRef - LLVMObjectFileCopySectionIterator.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMObjectFileIsSectionIteratorAtEnd = _libraries['llvm'].LLVMObjectFileIsSectionIteratorAtEnd - LLVMObjectFileIsSectionIteratorAtEnd.restype = LLVMBool - LLVMObjectFileIsSectionIteratorAtEnd.argtypes = [LLVMBinaryRef, LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMObjectFileCopySymbolIterator = _libraries['llvm'].LLVMObjectFileCopySymbolIterator - LLVMObjectFileCopySymbolIterator.restype = LLVMSymbolIteratorRef - LLVMObjectFileCopySymbolIterator.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMObjectFileIsSymbolIteratorAtEnd = _libraries['llvm'].LLVMObjectFileIsSymbolIteratorAtEnd - LLVMObjectFileIsSymbolIteratorAtEnd.restype = LLVMBool - LLVMObjectFileIsSymbolIteratorAtEnd.argtypes = [LLVMBinaryRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeSectionIterator = _libraries['llvm'].LLVMDisposeSectionIterator - LLVMDisposeSectionIterator.restype = None - LLVMDisposeSectionIterator.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextSection = _libraries['llvm'].LLVMMoveToNextSection - LLVMMoveToNextSection.restype = None - LLVMMoveToNextSection.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToContainingSection = _libraries['llvm'].LLVMMoveToContainingSection - LLVMMoveToContainingSection.restype = None - LLVMMoveToContainingSection.argtypes = [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeSymbolIterator = _libraries['llvm'].LLVMDisposeSymbolIterator - LLVMDisposeSymbolIterator.restype = None - LLVMDisposeSymbolIterator.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextSymbol = _libraries['llvm'].LLVMMoveToNextSymbol - LLVMMoveToNextSymbol.restype = None - LLVMMoveToNextSymbol.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionName = _libraries['llvm'].LLVMGetSectionName - LLVMGetSectionName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSectionName.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionSize = _libraries['llvm'].LLVMGetSectionSize - LLVMGetSectionSize.restype = uint64_t - LLVMGetSectionSize.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionContents = _libraries['llvm'].LLVMGetSectionContents - LLVMGetSectionContents.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSectionContents.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionAddress = _libraries['llvm'].LLVMGetSectionAddress - LLVMGetSectionAddress.restype = uint64_t - LLVMGetSectionAddress.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionContainsSymbol = _libraries['llvm'].LLVMGetSectionContainsSymbol - LLVMGetSectionContainsSymbol.restype = LLVMBool - LLVMGetSectionContainsSymbol.argtypes = [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocations = _libraries['llvm'].LLVMGetRelocations - LLVMGetRelocations.restype = LLVMRelocationIteratorRef - LLVMGetRelocations.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeRelocationIterator = _libraries['llvm'].LLVMDisposeRelocationIterator - LLVMDisposeRelocationIterator.restype = None - LLVMDisposeRelocationIterator.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMIsRelocationIteratorAtEnd = _libraries['llvm'].LLVMIsRelocationIteratorAtEnd - LLVMIsRelocationIteratorAtEnd.restype = LLVMBool - LLVMIsRelocationIteratorAtEnd.argtypes = [LLVMSectionIteratorRef, LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextRelocation = _libraries['llvm'].LLVMMoveToNextRelocation - LLVMMoveToNextRelocation.restype = None - LLVMMoveToNextRelocation.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolName = _libraries['llvm'].LLVMGetSymbolName - LLVMGetSymbolName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSymbolName.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolAddress = _libraries['llvm'].LLVMGetSymbolAddress - LLVMGetSymbolAddress.restype = uint64_t - LLVMGetSymbolAddress.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolSize = _libraries['llvm'].LLVMGetSymbolSize - LLVMGetSymbolSize.restype = uint64_t - LLVMGetSymbolSize.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationOffset = _libraries['llvm'].LLVMGetRelocationOffset - LLVMGetRelocationOffset.restype = uint64_t - LLVMGetRelocationOffset.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationSymbol = _libraries['llvm'].LLVMGetRelocationSymbol - LLVMGetRelocationSymbol.restype = LLVMSymbolIteratorRef - LLVMGetRelocationSymbol.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationType = _libraries['llvm'].LLVMGetRelocationType - LLVMGetRelocationType.restype = uint64_t - LLVMGetRelocationType.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationTypeName = _libraries['llvm'].LLVMGetRelocationTypeName - LLVMGetRelocationTypeName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetRelocationTypeName.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationValueString = _libraries['llvm'].LLVMGetRelocationValueString - LLVMGetRelocationValueString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetRelocationValueString.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -class struct_LLVMOpaqueObjectFile(Structure): - pass - -LLVMObjectFileRef = ctypes.POINTER(struct_LLVMOpaqueObjectFile) -try: - LLVMCreateObjectFile = _libraries['llvm'].LLVMCreateObjectFile - LLVMCreateObjectFile.restype = LLVMObjectFileRef - LLVMCreateObjectFile.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMDisposeObjectFile = _libraries['llvm'].LLVMDisposeObjectFile - LLVMDisposeObjectFile.restype = None - LLVMDisposeObjectFile.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMGetSections = _libraries['llvm'].LLVMGetSections - LLVMGetSections.restype = LLVMSectionIteratorRef - LLVMGetSections.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMIsSectionIteratorAtEnd = _libraries['llvm'].LLVMIsSectionIteratorAtEnd - LLVMIsSectionIteratorAtEnd.restype = LLVMBool - LLVMIsSectionIteratorAtEnd.argtypes = [LLVMObjectFileRef, LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbols = _libraries['llvm'].LLVMGetSymbols - LLVMGetSymbols.restype = LLVMSymbolIteratorRef - LLVMGetSymbols.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMIsSymbolIteratorAtEnd = _libraries['llvm'].LLVMIsSymbolIteratorAtEnd - LLVMIsSymbolIteratorAtEnd.restype = LLVMBool - LLVMIsSymbolIteratorAtEnd.argtypes = [LLVMObjectFileRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -LLVM_C_ORCEE_H = True # macro -try: - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager = _libraries['llvm'].LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager.restype = LLVMOrcObjectLayerRef - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager.argtypes = [LLVMOrcExecutionSessionRef] -except AttributeError: - pass -try: - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener = _libraries['llvm'].LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener.restype = None - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener.argtypes = [LLVMOrcObjectLayerRef, LLVMJITEventListenerRef] -except AttributeError: - pass -LLVM_C_REMARKS_H = True # macro -REMARKS_API_VERSION = 1 # macro - -# values for enumeration 'LLVMRemarkType' -LLVMRemarkType__enumvalues = { - 0: 'LLVMRemarkTypeUnknown', - 1: 'LLVMRemarkTypePassed', - 2: 'LLVMRemarkTypeMissed', - 3: 'LLVMRemarkTypeAnalysis', - 4: 'LLVMRemarkTypeAnalysisFPCommute', - 5: 'LLVMRemarkTypeAnalysisAliasing', - 6: 'LLVMRemarkTypeFailure', -} -LLVMRemarkTypeUnknown = 0 -LLVMRemarkTypePassed = 1 -LLVMRemarkTypeMissed = 2 -LLVMRemarkTypeAnalysis = 3 -LLVMRemarkTypeAnalysisFPCommute = 4 -LLVMRemarkTypeAnalysisAliasing = 5 -LLVMRemarkTypeFailure = 6 -LLVMRemarkType = ctypes.c_uint32 # enum -class struct_LLVMRemarkOpaqueString(Structure): - pass - -LLVMRemarkStringRef = ctypes.POINTER(struct_LLVMRemarkOpaqueString) -try: - LLVMRemarkStringGetData = _libraries['llvm'].LLVMRemarkStringGetData - LLVMRemarkStringGetData.restype = ctypes.POINTER(ctypes.c_char) - LLVMRemarkStringGetData.argtypes = [LLVMRemarkStringRef] -except AttributeError: - pass -try: - LLVMRemarkStringGetLen = _libraries['llvm'].LLVMRemarkStringGetLen - LLVMRemarkStringGetLen.restype = uint32_t - LLVMRemarkStringGetLen.argtypes = [LLVMRemarkStringRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueDebugLoc(Structure): - pass - -LLVMRemarkDebugLocRef = ctypes.POINTER(struct_LLVMRemarkOpaqueDebugLoc) -try: - LLVMRemarkDebugLocGetSourceFilePath = _libraries['llvm'].LLVMRemarkDebugLocGetSourceFilePath - LLVMRemarkDebugLocGetSourceFilePath.restype = LLVMRemarkStringRef - LLVMRemarkDebugLocGetSourceFilePath.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -try: - LLVMRemarkDebugLocGetSourceLine = _libraries['llvm'].LLVMRemarkDebugLocGetSourceLine - LLVMRemarkDebugLocGetSourceLine.restype = uint32_t - LLVMRemarkDebugLocGetSourceLine.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -try: - LLVMRemarkDebugLocGetSourceColumn = _libraries['llvm'].LLVMRemarkDebugLocGetSourceColumn - LLVMRemarkDebugLocGetSourceColumn.restype = uint32_t - LLVMRemarkDebugLocGetSourceColumn.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueArg(Structure): - pass - -LLVMRemarkArgRef = ctypes.POINTER(struct_LLVMRemarkOpaqueArg) -try: - LLVMRemarkArgGetKey = _libraries['llvm'].LLVMRemarkArgGetKey - LLVMRemarkArgGetKey.restype = LLVMRemarkStringRef - LLVMRemarkArgGetKey.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -try: - LLVMRemarkArgGetValue = _libraries['llvm'].LLVMRemarkArgGetValue - LLVMRemarkArgGetValue.restype = LLVMRemarkStringRef - LLVMRemarkArgGetValue.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -try: - LLVMRemarkArgGetDebugLoc = _libraries['llvm'].LLVMRemarkArgGetDebugLoc - LLVMRemarkArgGetDebugLoc.restype = LLVMRemarkDebugLocRef - LLVMRemarkArgGetDebugLoc.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueEntry(Structure): - pass - -LLVMRemarkEntryRef = ctypes.POINTER(struct_LLVMRemarkOpaqueEntry) -try: - LLVMRemarkEntryDispose = _libraries['llvm'].LLVMRemarkEntryDispose - LLVMRemarkEntryDispose.restype = None - LLVMRemarkEntryDispose.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetType = _libraries['llvm'].LLVMRemarkEntryGetType - LLVMRemarkEntryGetType.restype = LLVMRemarkType - LLVMRemarkEntryGetType.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetPassName = _libraries['llvm'].LLVMRemarkEntryGetPassName - LLVMRemarkEntryGetPassName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetPassName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetRemarkName = _libraries['llvm'].LLVMRemarkEntryGetRemarkName - LLVMRemarkEntryGetRemarkName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetRemarkName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetFunctionName = _libraries['llvm'].LLVMRemarkEntryGetFunctionName - LLVMRemarkEntryGetFunctionName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetFunctionName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetDebugLoc = _libraries['llvm'].LLVMRemarkEntryGetDebugLoc - LLVMRemarkEntryGetDebugLoc.restype = LLVMRemarkDebugLocRef - LLVMRemarkEntryGetDebugLoc.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetHotness = _libraries['llvm'].LLVMRemarkEntryGetHotness - LLVMRemarkEntryGetHotness.restype = uint64_t - LLVMRemarkEntryGetHotness.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetNumArgs = _libraries['llvm'].LLVMRemarkEntryGetNumArgs - LLVMRemarkEntryGetNumArgs.restype = uint32_t - LLVMRemarkEntryGetNumArgs.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetFirstArg = _libraries['llvm'].LLVMRemarkEntryGetFirstArg - LLVMRemarkEntryGetFirstArg.restype = LLVMRemarkArgRef - LLVMRemarkEntryGetFirstArg.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetNextArg = _libraries['llvm'].LLVMRemarkEntryGetNextArg - LLVMRemarkEntryGetNextArg.restype = LLVMRemarkArgRef - LLVMRemarkEntryGetNextArg.argtypes = [LLVMRemarkArgRef, LLVMRemarkEntryRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueParser(Structure): - pass - -LLVMRemarkParserRef = ctypes.POINTER(struct_LLVMRemarkOpaqueParser) -try: - LLVMRemarkParserCreateYAML = _libraries['llvm'].LLVMRemarkParserCreateYAML - LLVMRemarkParserCreateYAML.restype = LLVMRemarkParserRef - LLVMRemarkParserCreateYAML.argtypes = [ctypes.POINTER(None), uint64_t] -except AttributeError: - pass -try: - LLVMRemarkParserCreateBitstream = _libraries['llvm'].LLVMRemarkParserCreateBitstream - LLVMRemarkParserCreateBitstream.restype = LLVMRemarkParserRef - LLVMRemarkParserCreateBitstream.argtypes = [ctypes.POINTER(None), uint64_t] -except AttributeError: - pass -try: - LLVMRemarkParserGetNext = _libraries['llvm'].LLVMRemarkParserGetNext - LLVMRemarkParserGetNext.restype = LLVMRemarkEntryRef - LLVMRemarkParserGetNext.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserHasError = _libraries['llvm'].LLVMRemarkParserHasError - LLVMRemarkParserHasError.restype = LLVMBool - LLVMRemarkParserHasError.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserGetErrorMessage = _libraries['llvm'].LLVMRemarkParserGetErrorMessage - LLVMRemarkParserGetErrorMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMRemarkParserGetErrorMessage.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserDispose = _libraries['llvm'].LLVMRemarkParserDispose - LLVMRemarkParserDispose.restype = None - LLVMRemarkParserDispose.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkVersion = _libraries['llvm'].LLVMRemarkVersion - LLVMRemarkVersion.restype = uint32_t - LLVMRemarkVersion.argtypes = [] -except AttributeError: - pass -LLVM_C_SUPPORT_H = True # macro -try: - LLVMLoadLibraryPermanently = _libraries['llvm'].LLVMLoadLibraryPermanently - LLVMLoadLibraryPermanently.restype = LLVMBool - LLVMLoadLibraryPermanently.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMParseCommandLineOptions = _libraries['llvm'].LLVMParseCommandLineOptions - LLVMParseCommandLineOptions.restype = None - LLVMParseCommandLineOptions.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMSearchForAddressOfSymbol = _libraries['llvm'].LLVMSearchForAddressOfSymbol - LLVMSearchForAddressOfSymbol.restype = ctypes.POINTER(None) - LLVMSearchForAddressOfSymbol.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddSymbol = _libraries['llvm'].LLVMAddSymbol - LLVMAddSymbol.restype = None - LLVMAddSymbol.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -LLVM_C_TRANSFORMS_AGGRESSIVEINSTCOMBINE_H = True # macro -try: - LLVMAddAggressiveInstCombinerPass = _libraries['llvm'].LLVMAddAggressiveInstCombinerPass - LLVMAddAggressiveInstCombinerPass.restype = None - LLVMAddAggressiveInstCombinerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_COROUTINES_H = True # macro -LLVM_C_TRANSFORMS_PASSMANAGERBUILDER_H = True # macro -class struct_LLVMOpaquePassManagerBuilder(Structure): - pass - -LLVMPassManagerBuilderRef = ctypes.POINTER(struct_LLVMOpaquePassManagerBuilder) -try: - LLVMPassManagerBuilderCreate = _libraries['llvm'].LLVMPassManagerBuilderCreate - LLVMPassManagerBuilderCreate.restype = LLVMPassManagerBuilderRef - LLVMPassManagerBuilderCreate.argtypes = [] -except AttributeError: - pass -try: - LLVMPassManagerBuilderDispose = _libraries['llvm'].LLVMPassManagerBuilderDispose - LLVMPassManagerBuilderDispose.restype = None - LLVMPassManagerBuilderDispose.argtypes = [LLVMPassManagerBuilderRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetOptLevel = _libraries['llvm'].LLVMPassManagerBuilderSetOptLevel - LLVMPassManagerBuilderSetOptLevel.restype = None - LLVMPassManagerBuilderSetOptLevel.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetSizeLevel = _libraries['llvm'].LLVMPassManagerBuilderSetSizeLevel - LLVMPassManagerBuilderSetSizeLevel.restype = None - LLVMPassManagerBuilderSetSizeLevel.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableUnitAtATime = _libraries['llvm'].LLVMPassManagerBuilderSetDisableUnitAtATime - LLVMPassManagerBuilderSetDisableUnitAtATime.restype = None - LLVMPassManagerBuilderSetDisableUnitAtATime.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableUnrollLoops = _libraries['llvm'].LLVMPassManagerBuilderSetDisableUnrollLoops - LLVMPassManagerBuilderSetDisableUnrollLoops.restype = None - LLVMPassManagerBuilderSetDisableUnrollLoops.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableSimplifyLibCalls = _libraries['llvm'].LLVMPassManagerBuilderSetDisableSimplifyLibCalls - LLVMPassManagerBuilderSetDisableSimplifyLibCalls.restype = None - LLVMPassManagerBuilderSetDisableSimplifyLibCalls.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderUseInlinerWithThreshold = _libraries['llvm'].LLVMPassManagerBuilderUseInlinerWithThreshold - LLVMPassManagerBuilderUseInlinerWithThreshold.restype = None - LLVMPassManagerBuilderUseInlinerWithThreshold.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateFunctionPassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateFunctionPassManager - LLVMPassManagerBuilderPopulateFunctionPassManager.restype = None - LLVMPassManagerBuilderPopulateFunctionPassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateModulePassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateModulePassManager - LLVMPassManagerBuilderPopulateModulePassManager.restype = None - LLVMPassManagerBuilderPopulateModulePassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateLTOPassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateLTOPassManager - LLVMPassManagerBuilderPopulateLTOPassManager.restype = None - LLVMPassManagerBuilderPopulateLTOPassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef, LLVMBool, LLVMBool] -except AttributeError: - pass -try: - LLVMAddCoroEarlyPass = _libraries['llvm'].LLVMAddCoroEarlyPass - LLVMAddCoroEarlyPass.restype = None - LLVMAddCoroEarlyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroSplitPass = _libraries['llvm'].LLVMAddCoroSplitPass - LLVMAddCoroSplitPass.restype = None - LLVMAddCoroSplitPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroElidePass = _libraries['llvm'].LLVMAddCoroElidePass - LLVMAddCoroElidePass.restype = None - LLVMAddCoroElidePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroCleanupPass = _libraries['llvm'].LLVMAddCoroCleanupPass - LLVMAddCoroCleanupPass.restype = None - LLVMAddCoroCleanupPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints = _libraries['llvm'].LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints.restype = None - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints.argtypes = [LLVMPassManagerBuilderRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_IPO_H = True # macro -try: - LLVMAddArgumentPromotionPass = _libraries['llvm'].LLVMAddArgumentPromotionPass - LLVMAddArgumentPromotionPass.restype = None - LLVMAddArgumentPromotionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddConstantMergePass = _libraries['llvm'].LLVMAddConstantMergePass - LLVMAddConstantMergePass.restype = None - LLVMAddConstantMergePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMergeFunctionsPass = _libraries['llvm'].LLVMAddMergeFunctionsPass - LLVMAddMergeFunctionsPass.restype = None - LLVMAddMergeFunctionsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCalledValuePropagationPass = _libraries['llvm'].LLVMAddCalledValuePropagationPass - LLVMAddCalledValuePropagationPass.restype = None - LLVMAddCalledValuePropagationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDeadArgEliminationPass = _libraries['llvm'].LLVMAddDeadArgEliminationPass - LLVMAddDeadArgEliminationPass.restype = None - LLVMAddDeadArgEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddFunctionAttrsPass = _libraries['llvm'].LLVMAddFunctionAttrsPass - LLVMAddFunctionAttrsPass.restype = None - LLVMAddFunctionAttrsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddFunctionInliningPass = _libraries['llvm'].LLVMAddFunctionInliningPass - LLVMAddFunctionInliningPass.restype = None - LLVMAddFunctionInliningPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAlwaysInlinerPass = _libraries['llvm'].LLVMAddAlwaysInlinerPass - LLVMAddAlwaysInlinerPass.restype = None - LLVMAddAlwaysInlinerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGlobalDCEPass = _libraries['llvm'].LLVMAddGlobalDCEPass - LLVMAddGlobalDCEPass.restype = None - LLVMAddGlobalDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGlobalOptimizerPass = _libraries['llvm'].LLVMAddGlobalOptimizerPass - LLVMAddGlobalOptimizerPass.restype = None - LLVMAddGlobalOptimizerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPruneEHPass = _libraries['llvm'].LLVMAddPruneEHPass - LLVMAddPruneEHPass.restype = None - LLVMAddPruneEHPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddIPSCCPPass = _libraries['llvm'].LLVMAddIPSCCPPass - LLVMAddIPSCCPPass.restype = None - LLVMAddIPSCCPPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddInternalizePass = _libraries['llvm'].LLVMAddInternalizePass - LLVMAddInternalizePass.restype = None - LLVMAddInternalizePass.argtypes = [LLVMPassManagerRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddInternalizePassWithMustPreservePredicate = _libraries['llvm'].LLVMAddInternalizePassWithMustPreservePredicate - LLVMAddInternalizePassWithMustPreservePredicate.restype = None - LLVMAddInternalizePassWithMustPreservePredicate.argtypes = [LLVMPassManagerRef, ctypes.POINTER(None), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(None))] -except AttributeError: - pass -try: - LLVMAddStripDeadPrototypesPass = _libraries['llvm'].LLVMAddStripDeadPrototypesPass - LLVMAddStripDeadPrototypesPass.restype = None - LLVMAddStripDeadPrototypesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddStripSymbolsPass = _libraries['llvm'].LLVMAddStripSymbolsPass - LLVMAddStripSymbolsPass.restype = None - LLVMAddStripSymbolsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_INSTCOMBINE_H = True # macro -try: - LLVMAddInstructionCombiningPass = _libraries['llvm'].LLVMAddInstructionCombiningPass - LLVMAddInstructionCombiningPass.restype = None - LLVMAddInstructionCombiningPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_PASSBUILDER_H = True # macro -class struct_LLVMOpaquePassBuilderOptions(Structure): - pass - -LLVMPassBuilderOptionsRef = ctypes.POINTER(struct_LLVMOpaquePassBuilderOptions) -try: - LLVMRunPasses = _libraries['llvm'].LLVMRunPasses - LLVMRunPasses.restype = LLVMErrorRef - LLVMRunPasses.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineRef, LLVMPassBuilderOptionsRef] -except AttributeError: - pass -try: - LLVMCreatePassBuilderOptions = _libraries['llvm'].LLVMCreatePassBuilderOptions - LLVMCreatePassBuilderOptions.restype = LLVMPassBuilderOptionsRef - LLVMCreatePassBuilderOptions.argtypes = [] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetVerifyEach = _libraries['llvm'].LLVMPassBuilderOptionsSetVerifyEach - LLVMPassBuilderOptionsSetVerifyEach.restype = None - LLVMPassBuilderOptionsSetVerifyEach.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetDebugLogging = _libraries['llvm'].LLVMPassBuilderOptionsSetDebugLogging - LLVMPassBuilderOptionsSetDebugLogging.restype = None - LLVMPassBuilderOptionsSetDebugLogging.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopInterleaving = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopInterleaving - LLVMPassBuilderOptionsSetLoopInterleaving.restype = None - LLVMPassBuilderOptionsSetLoopInterleaving.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopVectorization = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopVectorization - LLVMPassBuilderOptionsSetLoopVectorization.restype = None - LLVMPassBuilderOptionsSetLoopVectorization.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetSLPVectorization = _libraries['llvm'].LLVMPassBuilderOptionsSetSLPVectorization - LLVMPassBuilderOptionsSetSLPVectorization.restype = None - LLVMPassBuilderOptionsSetSLPVectorization.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopUnrolling = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopUnrolling - LLVMPassBuilderOptionsSetLoopUnrolling.restype = None - LLVMPassBuilderOptionsSetLoopUnrolling.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll = _libraries['llvm'].LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll.restype = None - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLicmMssaOptCap = _libraries['llvm'].LLVMPassBuilderOptionsSetLicmMssaOptCap - LLVMPassBuilderOptionsSetLicmMssaOptCap.restype = None - LLVMPassBuilderOptionsSetLicmMssaOptCap.argtypes = [LLVMPassBuilderOptionsRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap = _libraries['llvm'].LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap.restype = None - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap.argtypes = [LLVMPassBuilderOptionsRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetCallGraphProfile = _libraries['llvm'].LLVMPassBuilderOptionsSetCallGraphProfile - LLVMPassBuilderOptionsSetCallGraphProfile.restype = None - LLVMPassBuilderOptionsSetCallGraphProfile.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetMergeFunctions = _libraries['llvm'].LLVMPassBuilderOptionsSetMergeFunctions - LLVMPassBuilderOptionsSetMergeFunctions.restype = None - LLVMPassBuilderOptionsSetMergeFunctions.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMDisposePassBuilderOptions = _libraries['llvm'].LLVMDisposePassBuilderOptions - LLVMDisposePassBuilderOptions.restype = None - LLVMDisposePassBuilderOptions.argtypes = [LLVMPassBuilderOptionsRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_SCALAR_H = True # macro -try: - LLVMAddAggressiveDCEPass = _libraries['llvm'].LLVMAddAggressiveDCEPass - LLVMAddAggressiveDCEPass.restype = None - LLVMAddAggressiveDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDCEPass = _libraries['llvm'].LLVMAddDCEPass - LLVMAddDCEPass.restype = None - LLVMAddDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddBitTrackingDCEPass = _libraries['llvm'].LLVMAddBitTrackingDCEPass - LLVMAddBitTrackingDCEPass.restype = None - LLVMAddBitTrackingDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAlignmentFromAssumptionsPass = _libraries['llvm'].LLVMAddAlignmentFromAssumptionsPass - LLVMAddAlignmentFromAssumptionsPass.restype = None - LLVMAddAlignmentFromAssumptionsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCFGSimplificationPass = _libraries['llvm'].LLVMAddCFGSimplificationPass - LLVMAddCFGSimplificationPass.restype = None - LLVMAddCFGSimplificationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDeadStoreEliminationPass = _libraries['llvm'].LLVMAddDeadStoreEliminationPass - LLVMAddDeadStoreEliminationPass.restype = None - LLVMAddDeadStoreEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarizerPass = _libraries['llvm'].LLVMAddScalarizerPass - LLVMAddScalarizerPass.restype = None - LLVMAddScalarizerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMergedLoadStoreMotionPass = _libraries['llvm'].LLVMAddMergedLoadStoreMotionPass - LLVMAddMergedLoadStoreMotionPass.restype = None - LLVMAddMergedLoadStoreMotionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGVNPass = _libraries['llvm'].LLVMAddGVNPass - LLVMAddGVNPass.restype = None - LLVMAddGVNPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddNewGVNPass = _libraries['llvm'].LLVMAddNewGVNPass - LLVMAddNewGVNPass.restype = None - LLVMAddNewGVNPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddIndVarSimplifyPass = _libraries['llvm'].LLVMAddIndVarSimplifyPass - LLVMAddIndVarSimplifyPass.restype = None - LLVMAddIndVarSimplifyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddInstructionSimplifyPass = _libraries['llvm'].LLVMAddInstructionSimplifyPass - LLVMAddInstructionSimplifyPass.restype = None - LLVMAddInstructionSimplifyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddJumpThreadingPass = _libraries['llvm'].LLVMAddJumpThreadingPass - LLVMAddJumpThreadingPass.restype = None - LLVMAddJumpThreadingPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLICMPass = _libraries['llvm'].LLVMAddLICMPass - LLVMAddLICMPass.restype = None - LLVMAddLICMPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopDeletionPass = _libraries['llvm'].LLVMAddLoopDeletionPass - LLVMAddLoopDeletionPass.restype = None - LLVMAddLoopDeletionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopIdiomPass = _libraries['llvm'].LLVMAddLoopIdiomPass - LLVMAddLoopIdiomPass.restype = None - LLVMAddLoopIdiomPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopRotatePass = _libraries['llvm'].LLVMAddLoopRotatePass - LLVMAddLoopRotatePass.restype = None - LLVMAddLoopRotatePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopRerollPass = _libraries['llvm'].LLVMAddLoopRerollPass - LLVMAddLoopRerollPass.restype = None - LLVMAddLoopRerollPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnrollPass = _libraries['llvm'].LLVMAddLoopUnrollPass - LLVMAddLoopUnrollPass.restype = None - LLVMAddLoopUnrollPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnrollAndJamPass = _libraries['llvm'].LLVMAddLoopUnrollAndJamPass - LLVMAddLoopUnrollAndJamPass.restype = None - LLVMAddLoopUnrollAndJamPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnswitchPass = _libraries['llvm'].LLVMAddLoopUnswitchPass - LLVMAddLoopUnswitchPass.restype = None - LLVMAddLoopUnswitchPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerAtomicPass = _libraries['llvm'].LLVMAddLowerAtomicPass - LLVMAddLowerAtomicPass.restype = None - LLVMAddLowerAtomicPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMemCpyOptPass = _libraries['llvm'].LLVMAddMemCpyOptPass - LLVMAddMemCpyOptPass.restype = None - LLVMAddMemCpyOptPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPartiallyInlineLibCallsPass = _libraries['llvm'].LLVMAddPartiallyInlineLibCallsPass - LLVMAddPartiallyInlineLibCallsPass.restype = None - LLVMAddPartiallyInlineLibCallsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddReassociatePass = _libraries['llvm'].LLVMAddReassociatePass - LLVMAddReassociatePass.restype = None - LLVMAddReassociatePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddSCCPPass = _libraries['llvm'].LLVMAddSCCPPass - LLVMAddSCCPPass.restype = None - LLVMAddSCCPPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPass = _libraries['llvm'].LLVMAddScalarReplAggregatesPass - LLVMAddScalarReplAggregatesPass.restype = None - LLVMAddScalarReplAggregatesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPassSSA = _libraries['llvm'].LLVMAddScalarReplAggregatesPassSSA - LLVMAddScalarReplAggregatesPassSSA.restype = None - LLVMAddScalarReplAggregatesPassSSA.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPassWithThreshold = _libraries['llvm'].LLVMAddScalarReplAggregatesPassWithThreshold - LLVMAddScalarReplAggregatesPassWithThreshold.restype = None - LLVMAddScalarReplAggregatesPassWithThreshold.argtypes = [LLVMPassManagerRef, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMAddSimplifyLibCallsPass = _libraries['llvm'].LLVMAddSimplifyLibCallsPass - LLVMAddSimplifyLibCallsPass.restype = None - LLVMAddSimplifyLibCallsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddTailCallEliminationPass = _libraries['llvm'].LLVMAddTailCallEliminationPass - LLVMAddTailCallEliminationPass.restype = None - LLVMAddTailCallEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDemoteMemoryToRegisterPass = _libraries['llvm'].LLVMAddDemoteMemoryToRegisterPass - LLVMAddDemoteMemoryToRegisterPass.restype = None - LLVMAddDemoteMemoryToRegisterPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddVerifierPass = _libraries['llvm'].LLVMAddVerifierPass - LLVMAddVerifierPass.restype = None - LLVMAddVerifierPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCorrelatedValuePropagationPass = _libraries['llvm'].LLVMAddCorrelatedValuePropagationPass - LLVMAddCorrelatedValuePropagationPass.restype = None - LLVMAddCorrelatedValuePropagationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddEarlyCSEPass = _libraries['llvm'].LLVMAddEarlyCSEPass - LLVMAddEarlyCSEPass.restype = None - LLVMAddEarlyCSEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddEarlyCSEMemSSAPass = _libraries['llvm'].LLVMAddEarlyCSEMemSSAPass - LLVMAddEarlyCSEMemSSAPass.restype = None - LLVMAddEarlyCSEMemSSAPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerExpectIntrinsicPass = _libraries['llvm'].LLVMAddLowerExpectIntrinsicPass - LLVMAddLowerExpectIntrinsicPass.restype = None - LLVMAddLowerExpectIntrinsicPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerConstantIntrinsicsPass = _libraries['llvm'].LLVMAddLowerConstantIntrinsicsPass - LLVMAddLowerConstantIntrinsicsPass.restype = None - LLVMAddLowerConstantIntrinsicsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddTypeBasedAliasAnalysisPass = _libraries['llvm'].LLVMAddTypeBasedAliasAnalysisPass - LLVMAddTypeBasedAliasAnalysisPass.restype = None - LLVMAddTypeBasedAliasAnalysisPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScopedNoAliasAAPass = _libraries['llvm'].LLVMAddScopedNoAliasAAPass - LLVMAddScopedNoAliasAAPass.restype = None - LLVMAddScopedNoAliasAAPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddBasicAliasAnalysisPass = _libraries['llvm'].LLVMAddBasicAliasAnalysisPass - LLVMAddBasicAliasAnalysisPass.restype = None - LLVMAddBasicAliasAnalysisPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddUnifyFunctionExitNodesPass = _libraries['llvm'].LLVMAddUnifyFunctionExitNodesPass - LLVMAddUnifyFunctionExitNodesPass.restype = None - LLVMAddUnifyFunctionExitNodesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_UTILS_H = True # macro -try: - LLVMAddLowerSwitchPass = _libraries['llvm'].LLVMAddLowerSwitchPass - LLVMAddLowerSwitchPass.restype = None - LLVMAddLowerSwitchPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPromoteMemoryToRegisterPass = _libraries['llvm'].LLVMAddPromoteMemoryToRegisterPass - LLVMAddPromoteMemoryToRegisterPass.restype = None - LLVMAddPromoteMemoryToRegisterPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAddDiscriminatorsPass = _libraries['llvm'].LLVMAddAddDiscriminatorsPass - LLVMAddAddDiscriminatorsPass.restype = None - LLVMAddAddDiscriminatorsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_VECTORIZE_H = True # macro -try: - LLVMAddLoopVectorizePass = _libraries['llvm'].LLVMAddLoopVectorizePass - LLVMAddLoopVectorizePass.restype = None - LLVMAddLoopVectorizePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddSLPVectorizePass = _libraries['llvm'].LLVMAddSLPVectorizePass - LLVMAddSLPVectorizePass.restype = None - LLVMAddSLPVectorizePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_LTO_H = True # macro -LTO_API_VERSION = 29 # macro -lto_bool_t = ctypes.c_bool - -# values for enumeration 'c__EA_lto_symbol_attributes' -c__EA_lto_symbol_attributes__enumvalues = { - 31: 'LTO_SYMBOL_ALIGNMENT_MASK', - 224: 'LTO_SYMBOL_PERMISSIONS_MASK', - 160: 'LTO_SYMBOL_PERMISSIONS_CODE', - 192: 'LTO_SYMBOL_PERMISSIONS_DATA', - 128: 'LTO_SYMBOL_PERMISSIONS_RODATA', - 1792: 'LTO_SYMBOL_DEFINITION_MASK', - 256: 'LTO_SYMBOL_DEFINITION_REGULAR', - 512: 'LTO_SYMBOL_DEFINITION_TENTATIVE', - 768: 'LTO_SYMBOL_DEFINITION_WEAK', - 1024: 'LTO_SYMBOL_DEFINITION_UNDEFINED', - 1280: 'LTO_SYMBOL_DEFINITION_WEAKUNDEF', - 14336: 'LTO_SYMBOL_SCOPE_MASK', - 2048: 'LTO_SYMBOL_SCOPE_INTERNAL', - 4096: 'LTO_SYMBOL_SCOPE_HIDDEN', - 8192: 'LTO_SYMBOL_SCOPE_PROTECTED', - 6144: 'LTO_SYMBOL_SCOPE_DEFAULT', - 10240: 'LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN', - 16384: 'LTO_SYMBOL_COMDAT', - 32768: 'LTO_SYMBOL_ALIAS', -} -LTO_SYMBOL_ALIGNMENT_MASK = 31 -LTO_SYMBOL_PERMISSIONS_MASK = 224 -LTO_SYMBOL_PERMISSIONS_CODE = 160 -LTO_SYMBOL_PERMISSIONS_DATA = 192 -LTO_SYMBOL_PERMISSIONS_RODATA = 128 -LTO_SYMBOL_DEFINITION_MASK = 1792 -LTO_SYMBOL_DEFINITION_REGULAR = 256 -LTO_SYMBOL_DEFINITION_TENTATIVE = 512 -LTO_SYMBOL_DEFINITION_WEAK = 768 -LTO_SYMBOL_DEFINITION_UNDEFINED = 1024 -LTO_SYMBOL_DEFINITION_WEAKUNDEF = 1280 -LTO_SYMBOL_SCOPE_MASK = 14336 -LTO_SYMBOL_SCOPE_INTERNAL = 2048 -LTO_SYMBOL_SCOPE_HIDDEN = 4096 -LTO_SYMBOL_SCOPE_PROTECTED = 8192 -LTO_SYMBOL_SCOPE_DEFAULT = 6144 -LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN = 10240 -LTO_SYMBOL_COMDAT = 16384 -LTO_SYMBOL_ALIAS = 32768 -c__EA_lto_symbol_attributes = ctypes.c_uint32 # enum -lto_symbol_attributes = c__EA_lto_symbol_attributes -lto_symbol_attributes__enumvalues = c__EA_lto_symbol_attributes__enumvalues - -# values for enumeration 'c__EA_lto_debug_model' -c__EA_lto_debug_model__enumvalues = { - 0: 'LTO_DEBUG_MODEL_NONE', - 1: 'LTO_DEBUG_MODEL_DWARF', -} -LTO_DEBUG_MODEL_NONE = 0 -LTO_DEBUG_MODEL_DWARF = 1 -c__EA_lto_debug_model = ctypes.c_uint32 # enum -lto_debug_model = c__EA_lto_debug_model -lto_debug_model__enumvalues = c__EA_lto_debug_model__enumvalues - -# values for enumeration 'c__EA_lto_codegen_model' -c__EA_lto_codegen_model__enumvalues = { - 0: 'LTO_CODEGEN_PIC_MODEL_STATIC', - 1: 'LTO_CODEGEN_PIC_MODEL_DYNAMIC', - 2: 'LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC', - 3: 'LTO_CODEGEN_PIC_MODEL_DEFAULT', -} -LTO_CODEGEN_PIC_MODEL_STATIC = 0 -LTO_CODEGEN_PIC_MODEL_DYNAMIC = 1 -LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC = 2 -LTO_CODEGEN_PIC_MODEL_DEFAULT = 3 -c__EA_lto_codegen_model = ctypes.c_uint32 # enum -lto_codegen_model = c__EA_lto_codegen_model -lto_codegen_model__enumvalues = c__EA_lto_codegen_model__enumvalues -class struct_LLVMOpaqueLTOModule(Structure): - pass - -lto_module_t = ctypes.POINTER(struct_LLVMOpaqueLTOModule) -class struct_LLVMOpaqueLTOCodeGenerator(Structure): - pass - -lto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueLTOCodeGenerator) -class struct_LLVMOpaqueThinLTOCodeGenerator(Structure): - pass - -thinlto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueThinLTOCodeGenerator) -try: - lto_get_version = _libraries['llvm'].lto_get_version - lto_get_version.restype = ctypes.POINTER(ctypes.c_char) - lto_get_version.argtypes = [] -except AttributeError: - pass -try: - lto_get_error_message = _libraries['llvm'].lto_get_error_message - lto_get_error_message.restype = ctypes.POINTER(ctypes.c_char) - lto_get_error_message.argtypes = [] -except AttributeError: - pass -try: - lto_module_is_object_file = _libraries['llvm'].lto_module_is_object_file - lto_module_is_object_file.restype = lto_bool_t - lto_module_is_object_file.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_is_object_file_for_target = _libraries['llvm'].lto_module_is_object_file_for_target - lto_module_is_object_file_for_target.restype = lto_bool_t - lto_module_is_object_file_for_target.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_has_objc_category = _libraries['llvm'].lto_module_has_objc_category - lto_module_has_objc_category.restype = lto_bool_t - lto_module_has_objc_category.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_is_object_file_in_memory = _libraries['llvm'].lto_module_is_object_file_in_memory - lto_module_is_object_file_in_memory.restype = lto_bool_t - lto_module_is_object_file_in_memory.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_is_object_file_in_memory_for_target = _libraries['llvm'].lto_module_is_object_file_in_memory_for_target - lto_module_is_object_file_in_memory_for_target.restype = lto_bool_t - lto_module_is_object_file_in_memory_for_target.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create = _libraries['llvm'].lto_module_create - lto_module_create.restype = lto_module_t - lto_module_create.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_from_memory = _libraries['llvm'].lto_module_create_from_memory - lto_module_create_from_memory.restype = lto_module_t - lto_module_create_from_memory.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_create_from_memory_with_path = _libraries['llvm'].lto_module_create_from_memory_with_path - lto_module_create_from_memory_with_path.restype = lto_module_t - lto_module_create_from_memory_with_path.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_in_local_context = _libraries['llvm'].lto_module_create_in_local_context - lto_module_create_in_local_context.restype = lto_module_t - lto_module_create_in_local_context.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_in_codegen_context = _libraries['llvm'].lto_module_create_in_codegen_context - lto_module_create_in_codegen_context.restype = lto_module_t - lto_module_create_in_codegen_context.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), lto_code_gen_t] -except AttributeError: - pass -try: - lto_module_create_from_fd = _libraries['llvm'].lto_module_create_from_fd - lto_module_create_from_fd.restype = lto_module_t - lto_module_create_from_fd.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -off_t = ctypes.c_int64 -try: - lto_module_create_from_fd_at_offset = _libraries['llvm'].lto_module_create_from_fd_at_offset - lto_module_create_from_fd_at_offset.restype = lto_module_t - lto_module_create_from_fd_at_offset.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t, size_t, off_t] -except AttributeError: - pass -try: - lto_module_dispose = _libraries['llvm'].lto_module_dispose - lto_module_dispose.restype = None - lto_module_dispose.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_target_triple = _libraries['llvm'].lto_module_get_target_triple - lto_module_get_target_triple.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_target_triple.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_set_target_triple = _libraries['llvm'].lto_module_set_target_triple - lto_module_set_target_triple.restype = None - lto_module_set_target_triple.argtypes = [lto_module_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_get_num_symbols = _libraries['llvm'].lto_module_get_num_symbols - lto_module_get_num_symbols.restype = ctypes.c_uint32 - lto_module_get_num_symbols.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_symbol_name = _libraries['llvm'].lto_module_get_symbol_name - lto_module_get_symbol_name.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_symbol_name.argtypes = [lto_module_t, ctypes.c_uint32] -except AttributeError: - pass -try: - lto_module_get_symbol_attribute = _libraries['llvm'].lto_module_get_symbol_attribute - lto_module_get_symbol_attribute.restype = lto_symbol_attributes - lto_module_get_symbol_attribute.argtypes = [lto_module_t, ctypes.c_uint32] -except AttributeError: - pass -try: - lto_module_get_linkeropts = _libraries['llvm'].lto_module_get_linkeropts - lto_module_get_linkeropts.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_linkeropts.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_macho_cputype = _libraries['llvm'].lto_module_get_macho_cputype - lto_module_get_macho_cputype.restype = lto_bool_t - lto_module_get_macho_cputype.argtypes = [lto_module_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - lto_module_has_ctor_dtor = _libraries['llvm'].lto_module_has_ctor_dtor - lto_module_has_ctor_dtor.restype = lto_bool_t - lto_module_has_ctor_dtor.argtypes = [lto_module_t] -except AttributeError: - pass - -# values for enumeration 'c__EA_lto_codegen_diagnostic_severity_t' -c__EA_lto_codegen_diagnostic_severity_t__enumvalues = { - 0: 'LTO_DS_ERROR', - 1: 'LTO_DS_WARNING', - 3: 'LTO_DS_REMARK', - 2: 'LTO_DS_NOTE', -} -LTO_DS_ERROR = 0 -LTO_DS_WARNING = 1 -LTO_DS_REMARK = 3 -LTO_DS_NOTE = 2 -c__EA_lto_codegen_diagnostic_severity_t = ctypes.c_uint32 # enum -lto_codegen_diagnostic_severity_t = c__EA_lto_codegen_diagnostic_severity_t -lto_codegen_diagnostic_severity_t__enumvalues = c__EA_lto_codegen_diagnostic_severity_t__enumvalues -lto_diagnostic_handler_t = ctypes.CFUNCTYPE(None, c__EA_lto_codegen_diagnostic_severity_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)) -try: - lto_codegen_set_diagnostic_handler = _libraries['llvm'].lto_codegen_set_diagnostic_handler - lto_codegen_set_diagnostic_handler.restype = None - lto_codegen_set_diagnostic_handler.argtypes = [lto_code_gen_t, lto_diagnostic_handler_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - lto_codegen_create = _libraries['llvm'].lto_codegen_create - lto_codegen_create.restype = lto_code_gen_t - lto_codegen_create.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_create_in_local_context = _libraries['llvm'].lto_codegen_create_in_local_context - lto_codegen_create_in_local_context.restype = lto_code_gen_t - lto_codegen_create_in_local_context.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_dispose = _libraries['llvm'].lto_codegen_dispose - lto_codegen_dispose.restype = None - lto_codegen_dispose.argtypes = [lto_code_gen_t] -except AttributeError: - pass -try: - lto_codegen_add_module = _libraries['llvm'].lto_codegen_add_module - lto_codegen_add_module.restype = lto_bool_t - lto_codegen_add_module.argtypes = [lto_code_gen_t, lto_module_t] -except AttributeError: - pass -try: - lto_codegen_set_module = _libraries['llvm'].lto_codegen_set_module - lto_codegen_set_module.restype = None - lto_codegen_set_module.argtypes = [lto_code_gen_t, lto_module_t] -except AttributeError: - pass -try: - lto_codegen_set_debug_model = _libraries['llvm'].lto_codegen_set_debug_model - lto_codegen_set_debug_model.restype = lto_bool_t - lto_codegen_set_debug_model.argtypes = [lto_code_gen_t, lto_debug_model] -except AttributeError: - pass -try: - lto_codegen_set_pic_model = _libraries['llvm'].lto_codegen_set_pic_model - lto_codegen_set_pic_model.restype = lto_bool_t - lto_codegen_set_pic_model.argtypes = [lto_code_gen_t, lto_codegen_model] -except AttributeError: - pass -try: - lto_codegen_set_cpu = _libraries['llvm'].lto_codegen_set_cpu - lto_codegen_set_cpu.restype = None - lto_codegen_set_cpu.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_set_assembler_path = _libraries['llvm'].lto_codegen_set_assembler_path - lto_codegen_set_assembler_path.restype = None - lto_codegen_set_assembler_path.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_set_assembler_args = _libraries['llvm'].lto_codegen_set_assembler_args - lto_codegen_set_assembler_args.restype = None - lto_codegen_set_assembler_args.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_codegen_add_must_preserve_symbol = _libraries['llvm'].lto_codegen_add_must_preserve_symbol - lto_codegen_add_must_preserve_symbol.restype = None - lto_codegen_add_must_preserve_symbol.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_write_merged_modules = _libraries['llvm'].lto_codegen_write_merged_modules - lto_codegen_write_merged_modules.restype = lto_bool_t - lto_codegen_write_merged_modules.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_compile = _libraries['llvm'].lto_codegen_compile - lto_codegen_compile.restype = ctypes.POINTER(None) - lto_codegen_compile.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_codegen_compile_to_file = _libraries['llvm'].lto_codegen_compile_to_file - lto_codegen_compile_to_file.restype = lto_bool_t - lto_codegen_compile_to_file.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - lto_codegen_optimize = _libraries['llvm'].lto_codegen_optimize - lto_codegen_optimize.restype = lto_bool_t - lto_codegen_optimize.argtypes = [lto_code_gen_t] -except AttributeError: - pass -try: - lto_codegen_compile_optimized = _libraries['llvm'].lto_codegen_compile_optimized - lto_codegen_compile_optimized.restype = ctypes.POINTER(None) - lto_codegen_compile_optimized.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_api_version = _libraries['llvm'].lto_api_version - lto_api_version.restype = ctypes.c_uint32 - lto_api_version.argtypes = [] -except AttributeError: - pass -try: - lto_set_debug_options = _libraries['llvm'].lto_set_debug_options - lto_set_debug_options.restype = None - lto_set_debug_options.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_codegen_debug_options = _libraries['llvm'].lto_codegen_debug_options - lto_codegen_debug_options.restype = None - lto_codegen_debug_options.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_debug_options_array = _libraries['llvm'].lto_codegen_debug_options_array - lto_codegen_debug_options_array.restype = None - lto_codegen_debug_options_array.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_initialize_disassembler = _libraries['llvm'].lto_initialize_disassembler - lto_initialize_disassembler.restype = None - lto_initialize_disassembler.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_set_should_internalize = _libraries['llvm'].lto_codegen_set_should_internalize - lto_codegen_set_should_internalize.restype = None - lto_codegen_set_should_internalize.argtypes = [lto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - lto_codegen_set_should_embed_uselists = _libraries['llvm'].lto_codegen_set_should_embed_uselists - lto_codegen_set_should_embed_uselists.restype = None - lto_codegen_set_should_embed_uselists.argtypes = [lto_code_gen_t, lto_bool_t] -except AttributeError: - pass -class struct_LLVMOpaqueLTOInput(Structure): - pass - -lto_input_t = ctypes.POINTER(struct_LLVMOpaqueLTOInput) -try: - lto_input_create = _libraries['llvm'].lto_input_create - lto_input_create.restype = lto_input_t - lto_input_create.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_input_dispose = _libraries['llvm'].lto_input_dispose - lto_input_dispose.restype = None - lto_input_dispose.argtypes = [lto_input_t] -except AttributeError: - pass -try: - lto_input_get_num_dependent_libraries = _libraries['llvm'].lto_input_get_num_dependent_libraries - lto_input_get_num_dependent_libraries.restype = ctypes.c_uint32 - lto_input_get_num_dependent_libraries.argtypes = [lto_input_t] -except AttributeError: - pass -try: - lto_input_get_dependent_library = _libraries['llvm'].lto_input_get_dependent_library - lto_input_get_dependent_library.restype = ctypes.POINTER(ctypes.c_char) - lto_input_get_dependent_library.argtypes = [lto_input_t, size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_runtime_lib_symbols_list = _libraries['llvm'].lto_runtime_lib_symbols_list - lto_runtime_lib_symbols_list.restype = ctypes.POINTER(ctypes.POINTER(ctypes.c_char)) - lto_runtime_lib_symbols_list.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -class struct_c__SA_LTOObjectBuffer(Structure): - pass - -struct_c__SA_LTOObjectBuffer._pack_ = 1 # source:False -struct_c__SA_LTOObjectBuffer._fields_ = [ - ('Buffer', ctypes.POINTER(ctypes.c_char)), - ('Size', ctypes.c_uint64), -] - -LTOObjectBuffer = struct_c__SA_LTOObjectBuffer -try: - thinlto_create_codegen = _libraries['llvm'].thinlto_create_codegen - thinlto_create_codegen.restype = thinlto_code_gen_t - thinlto_create_codegen.argtypes = [] -except AttributeError: - pass -try: - thinlto_codegen_dispose = _libraries['llvm'].thinlto_codegen_dispose - thinlto_codegen_dispose.restype = None - thinlto_codegen_dispose.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_codegen_add_module = _libraries['llvm'].thinlto_codegen_add_module - thinlto_codegen_add_module.restype = None - thinlto_codegen_add_module.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_process = _libraries['llvm'].thinlto_codegen_process - thinlto_codegen_process.restype = None - thinlto_codegen_process.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_num_objects = _libraries['llvm'].thinlto_module_get_num_objects - thinlto_module_get_num_objects.restype = ctypes.c_uint32 - thinlto_module_get_num_objects.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_object = _libraries['llvm'].thinlto_module_get_object - thinlto_module_get_object.restype = LTOObjectBuffer - thinlto_module_get_object.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_module_get_num_object_files = _libraries['llvm'].thinlto_module_get_num_object_files - thinlto_module_get_num_object_files.restype = ctypes.c_uint32 - thinlto_module_get_num_object_files.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_object_file = _libraries['llvm'].thinlto_module_get_object_file - thinlto_module_get_object_file.restype = ctypes.POINTER(ctypes.c_char) - thinlto_module_get_object_file.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_pic_model = _libraries['llvm'].thinlto_codegen_set_pic_model - thinlto_codegen_set_pic_model.restype = lto_bool_t - thinlto_codegen_set_pic_model.argtypes = [thinlto_code_gen_t, lto_codegen_model] -except AttributeError: - pass -try: - thinlto_codegen_set_savetemps_dir = _libraries['llvm'].thinlto_codegen_set_savetemps_dir - thinlto_codegen_set_savetemps_dir.restype = None - thinlto_codegen_set_savetemps_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_set_generated_objects_dir = _libraries['llvm'].thinlto_set_generated_objects_dir - thinlto_set_generated_objects_dir.restype = None - thinlto_set_generated_objects_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_set_cpu = _libraries['llvm'].thinlto_codegen_set_cpu - thinlto_codegen_set_cpu.restype = None - thinlto_codegen_set_cpu.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_disable_codegen = _libraries['llvm'].thinlto_codegen_disable_codegen - thinlto_codegen_disable_codegen.restype = None - thinlto_codegen_disable_codegen.argtypes = [thinlto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - thinlto_codegen_set_codegen_only = _libraries['llvm'].thinlto_codegen_set_codegen_only - thinlto_codegen_set_codegen_only.restype = None - thinlto_codegen_set_codegen_only.argtypes = [thinlto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - thinlto_debug_options = _libraries['llvm'].thinlto_debug_options - thinlto_debug_options.restype = None - thinlto_debug_options.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_module_is_thinlto = _libraries['llvm'].lto_module_is_thinlto - lto_module_is_thinlto.restype = lto_bool_t - lto_module_is_thinlto.argtypes = [lto_module_t] -except AttributeError: - pass -try: - thinlto_codegen_add_must_preserve_symbol = _libraries['llvm'].thinlto_codegen_add_must_preserve_symbol - thinlto_codegen_add_must_preserve_symbol.restype = None - thinlto_codegen_add_must_preserve_symbol.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_add_cross_referenced_symbol = _libraries['llvm'].thinlto_codegen_add_cross_referenced_symbol - thinlto_codegen_add_cross_referenced_symbol.restype = None - thinlto_codegen_add_cross_referenced_symbol.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_dir = _libraries['llvm'].thinlto_codegen_set_cache_dir - thinlto_codegen_set_cache_dir.restype = None - thinlto_codegen_set_cache_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_pruning_interval = _libraries['llvm'].thinlto_codegen_set_cache_pruning_interval - thinlto_codegen_set_cache_pruning_interval.restype = None - thinlto_codegen_set_cache_pruning_interval.argtypes = [thinlto_code_gen_t, ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_set_final_cache_size_relative_to_available_space = _libraries['llvm'].thinlto_codegen_set_final_cache_size_relative_to_available_space - thinlto_codegen_set_final_cache_size_relative_to_available_space.restype = None - thinlto_codegen_set_final_cache_size_relative_to_available_space.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_entry_expiration = _libraries['llvm'].thinlto_codegen_set_cache_entry_expiration - thinlto_codegen_set_cache_entry_expiration.restype = None - thinlto_codegen_set_cache_entry_expiration.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_bytes = _libraries['llvm'].thinlto_codegen_set_cache_size_bytes - thinlto_codegen_set_cache_size_bytes.restype = None - thinlto_codegen_set_cache_size_bytes.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_megabytes = _libraries['llvm'].thinlto_codegen_set_cache_size_megabytes - thinlto_codegen_set_cache_size_megabytes.restype = None - thinlto_codegen_set_cache_size_megabytes.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_files = _libraries['llvm'].thinlto_codegen_set_cache_size_files - thinlto_codegen_set_cache_size_files.restype = None - thinlto_codegen_set_cache_size_files.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -__all__ = \ - ['LLVMABIAlignmentOfType', 'LLVMABISizeOfType', - 'LLVMAMDGPUCSCallConv', 'LLVMAMDGPUESCallConv', - 'LLVMAMDGPUGSCallConv', 'LLVMAMDGPUHSCallConv', - 'LLVMAMDGPUKERNELCallConv', 'LLVMAMDGPULSCallConv', - 'LLVMAMDGPUPSCallConv', 'LLVMAMDGPUVSCallConv', - 'LLVMARMAAPCSCallConv', 'LLVMARMAAPCSVFPCallConv', - 'LLVMARMAPCSCallConv', 'LLVMAShr', 'LLVMAVRBUILTINCallConv', - 'LLVMAVRINTRCallConv', 'LLVMAVRSIGNALCallConv', - 'LLVMAbortProcessAction', 'LLVMAdd', - 'LLVMAddAddDiscriminatorsPass', 'LLVMAddAggressiveDCEPass', - 'LLVMAddAggressiveInstCombinerPass', 'LLVMAddAlias', - 'LLVMAddAlias2', 'LLVMAddAlignmentFromAssumptionsPass', - 'LLVMAddAlwaysInlinerPass', 'LLVMAddAnalysisPasses', - 'LLVMAddArgumentPromotionPass', 'LLVMAddAttributeAtIndex', - 'LLVMAddBasicAliasAnalysisPass', 'LLVMAddBitTrackingDCEPass', - 'LLVMAddCFGSimplificationPass', 'LLVMAddCallSiteAttribute', - 'LLVMAddCalledValuePropagationPass', 'LLVMAddCase', - 'LLVMAddClause', 'LLVMAddConstantMergePass', - 'LLVMAddCoroCleanupPass', 'LLVMAddCoroEarlyPass', - 'LLVMAddCoroElidePass', 'LLVMAddCoroSplitPass', - 'LLVMAddCorrelatedValuePropagationPass', 'LLVMAddDCEPass', - 'LLVMAddDeadArgEliminationPass', - 'LLVMAddDeadStoreEliminationPass', - 'LLVMAddDemoteMemoryToRegisterPass', 'LLVMAddDestination', - 'LLVMAddEarlyCSEMemSSAPass', 'LLVMAddEarlyCSEPass', - 'LLVMAddFunction', 'LLVMAddFunctionAttrsPass', - 'LLVMAddFunctionInliningPass', 'LLVMAddGVNPass', 'LLVMAddGlobal', - 'LLVMAddGlobalDCEPass', 'LLVMAddGlobalIFunc', - 'LLVMAddGlobalInAddressSpace', 'LLVMAddGlobalMapping', - 'LLVMAddGlobalOptimizerPass', 'LLVMAddHandler', - 'LLVMAddIPSCCPPass', 'LLVMAddIncoming', - 'LLVMAddIndVarSimplifyPass', 'LLVMAddInstructionCombiningPass', - 'LLVMAddInstructionSimplifyPass', 'LLVMAddInternalizePass', - 'LLVMAddInternalizePassWithMustPreservePredicate', - 'LLVMAddJumpThreadingPass', 'LLVMAddLICMPass', - 'LLVMAddLoopDeletionPass', 'LLVMAddLoopIdiomPass', - 'LLVMAddLoopRerollPass', 'LLVMAddLoopRotatePass', - 'LLVMAddLoopUnrollAndJamPass', 'LLVMAddLoopUnrollPass', - 'LLVMAddLoopUnswitchPass', 'LLVMAddLoopVectorizePass', - 'LLVMAddLowerAtomicPass', 'LLVMAddLowerConstantIntrinsicsPass', - 'LLVMAddLowerExpectIntrinsicPass', 'LLVMAddLowerSwitchPass', - 'LLVMAddMemCpyOptPass', 'LLVMAddMergeFunctionsPass', - 'LLVMAddMergedLoadStoreMotionPass', 'LLVMAddMetadataToInst', - 'LLVMAddModule', 'LLVMAddModuleFlag', - 'LLVMAddNamedMetadataOperand', 'LLVMAddNewGVNPass', - 'LLVMAddPartiallyInlineLibCallsPass', - 'LLVMAddPromoteMemoryToRegisterPass', 'LLVMAddPruneEHPass', - 'LLVMAddReassociatePass', 'LLVMAddSCCPPass', - 'LLVMAddSLPVectorizePass', 'LLVMAddScalarReplAggregatesPass', - 'LLVMAddScalarReplAggregatesPassSSA', - 'LLVMAddScalarReplAggregatesPassWithThreshold', - 'LLVMAddScalarizerPass', 'LLVMAddScopedNoAliasAAPass', - 'LLVMAddSimplifyLibCallsPass', 'LLVMAddStripDeadPrototypesPass', - 'LLVMAddStripSymbolsPass', 'LLVMAddSymbol', - 'LLVMAddTailCallEliminationPass', - 'LLVMAddTargetDependentFunctionAttr', 'LLVMAddTargetLibraryInfo', - 'LLVMAddTypeBasedAliasAnalysisPass', - 'LLVMAddUnifyFunctionExitNodesPass', 'LLVMAddVerifierPass', - 'LLVMAddrSpaceCast', 'LLVMAliasGetAliasee', 'LLVMAliasSetAliasee', - 'LLVMAlignOf', 'LLVMAlloca', 'LLVMAnd', - 'LLVMAnyComdatSelectionKind', 'LLVMAnyRegCallConv', - 'LLVMAppendBasicBlock', 'LLVMAppendBasicBlockInContext', - 'LLVMAppendExistingBasicBlock', 'LLVMAppendModuleInlineAsm', - 'LLVMAppendingLinkage', 'LLVMArgumentValueKind', 'LLVMArrayType', - 'LLVMArrayTypeKind', 'LLVMAssemblyFile', 'LLVMAtomicCmpXchg', - 'LLVMAtomicOrdering', 'LLVMAtomicOrderingAcquire', - 'LLVMAtomicOrderingAcquireRelease', 'LLVMAtomicOrderingMonotonic', - 'LLVMAtomicOrderingNotAtomic', 'LLVMAtomicOrderingRelease', - 'LLVMAtomicOrderingSequentiallyConsistent', - 'LLVMAtomicOrderingUnordered', 'LLVMAtomicOrdering__enumvalues', - 'LLVMAtomicRMW', 'LLVMAtomicRMWBinOp', 'LLVMAtomicRMWBinOpAdd', - 'LLVMAtomicRMWBinOpAnd', 'LLVMAtomicRMWBinOpFAdd', - 'LLVMAtomicRMWBinOpFSub', 'LLVMAtomicRMWBinOpMax', - 'LLVMAtomicRMWBinOpMin', 'LLVMAtomicRMWBinOpNand', - 'LLVMAtomicRMWBinOpOr', 'LLVMAtomicRMWBinOpSub', - 'LLVMAtomicRMWBinOpUMax', 'LLVMAtomicRMWBinOpUMin', - 'LLVMAtomicRMWBinOpXchg', 'LLVMAtomicRMWBinOpXor', - 'LLVMAtomicRMWBinOp__enumvalues', 'LLVMAttributeFunctionIndex', - 'LLVMAttributeIndex', 'LLVMAttributeRef', - 'LLVMAttributeReturnIndex', 'LLVMAvailableExternallyLinkage', - 'LLVMBFloatType', 'LLVMBFloatTypeInContext', 'LLVMBFloatTypeKind', - 'LLVMBasicBlockAsValue', 'LLVMBasicBlockRef', - 'LLVMBasicBlockValueKind', 'LLVMBigEndian', - 'LLVMBinaryCopyMemoryBuffer', 'LLVMBinaryGetType', - 'LLVMBinaryRef', 'LLVMBinaryType', 'LLVMBinaryTypeArchive', - 'LLVMBinaryTypeCOFF', 'LLVMBinaryTypeCOFFImportFile', - 'LLVMBinaryTypeELF32B', 'LLVMBinaryTypeELF32L', - 'LLVMBinaryTypeELF64B', 'LLVMBinaryTypeELF64L', - 'LLVMBinaryTypeIR', 'LLVMBinaryTypeMachO32B', - 'LLVMBinaryTypeMachO32L', 'LLVMBinaryTypeMachO64B', - 'LLVMBinaryTypeMachO64L', 'LLVMBinaryTypeMachOUniversalBinary', - 'LLVMBinaryTypeWasm', 'LLVMBinaryTypeWinRes', - 'LLVMBinaryType__enumvalues', 'LLVMBitCast', 'LLVMBlockAddress', - 'LLVMBlockAddressValueKind', 'LLVMBool', 'LLVMBr', - 'LLVMBuildAShr', 'LLVMBuildAdd', 'LLVMBuildAddrSpaceCast', - 'LLVMBuildAggregateRet', 'LLVMBuildAlloca', 'LLVMBuildAnd', - 'LLVMBuildArrayAlloca', 'LLVMBuildArrayMalloc', - 'LLVMBuildAtomicCmpXchg', 'LLVMBuildAtomicRMW', 'LLVMBuildBinOp', - 'LLVMBuildBitCast', 'LLVMBuildBr', 'LLVMBuildCall', - 'LLVMBuildCall2', 'LLVMBuildCast', 'LLVMBuildCatchPad', - 'LLVMBuildCatchRet', 'LLVMBuildCatchSwitch', - 'LLVMBuildCleanupPad', 'LLVMBuildCleanupRet', 'LLVMBuildCondBr', - 'LLVMBuildExactSDiv', 'LLVMBuildExactUDiv', - 'LLVMBuildExtractElement', 'LLVMBuildExtractValue', - 'LLVMBuildFAdd', 'LLVMBuildFCmp', 'LLVMBuildFDiv', - 'LLVMBuildFMul', 'LLVMBuildFNeg', 'LLVMBuildFPCast', - 'LLVMBuildFPExt', 'LLVMBuildFPToSI', 'LLVMBuildFPToUI', - 'LLVMBuildFPTrunc', 'LLVMBuildFRem', 'LLVMBuildFSub', - 'LLVMBuildFence', 'LLVMBuildFree', 'LLVMBuildFreeze', - 'LLVMBuildGEP', 'LLVMBuildGEP2', 'LLVMBuildGlobalString', - 'LLVMBuildGlobalStringPtr', 'LLVMBuildICmp', - 'LLVMBuildInBoundsGEP', 'LLVMBuildInBoundsGEP2', - 'LLVMBuildIndirectBr', 'LLVMBuildInsertElement', - 'LLVMBuildInsertValue', 'LLVMBuildIntCast', 'LLVMBuildIntCast2', - 'LLVMBuildIntToPtr', 'LLVMBuildInvoke', 'LLVMBuildInvoke2', - 'LLVMBuildIsNotNull', 'LLVMBuildIsNull', 'LLVMBuildLShr', - 'LLVMBuildLandingPad', 'LLVMBuildLoad', 'LLVMBuildLoad2', - 'LLVMBuildMalloc', 'LLVMBuildMemCpy', 'LLVMBuildMemMove', - 'LLVMBuildMemSet', 'LLVMBuildMul', 'LLVMBuildNSWAdd', - 'LLVMBuildNSWMul', 'LLVMBuildNSWNeg', 'LLVMBuildNSWSub', - 'LLVMBuildNUWAdd', 'LLVMBuildNUWMul', 'LLVMBuildNUWNeg', - 'LLVMBuildNUWSub', 'LLVMBuildNeg', 'LLVMBuildNot', 'LLVMBuildOr', - 'LLVMBuildPhi', 'LLVMBuildPointerCast', 'LLVMBuildPtrDiff', - 'LLVMBuildPtrDiff2', 'LLVMBuildPtrToInt', 'LLVMBuildResume', - 'LLVMBuildRet', 'LLVMBuildRetVoid', 'LLVMBuildSDiv', - 'LLVMBuildSExt', 'LLVMBuildSExtOrBitCast', 'LLVMBuildSIToFP', - 'LLVMBuildSRem', 'LLVMBuildSelect', 'LLVMBuildShl', - 'LLVMBuildShuffleVector', 'LLVMBuildStore', 'LLVMBuildStructGEP', - 'LLVMBuildStructGEP2', 'LLVMBuildSub', 'LLVMBuildSwitch', - 'LLVMBuildTrunc', 'LLVMBuildTruncOrBitCast', 'LLVMBuildUDiv', - 'LLVMBuildUIToFP', 'LLVMBuildURem', 'LLVMBuildUnreachable', - 'LLVMBuildVAArg', 'LLVMBuildXor', 'LLVMBuildZExt', - 'LLVMBuildZExtOrBitCast', 'LLVMBuilderGetDefaultFPMathTag', - 'LLVMBuilderRef', 'LLVMBuilderSetDefaultFPMathTag', - 'LLVMByteOrder', 'LLVMByteOrdering', 'LLVMCCallConv', - 'LLVMCXXFASTTLSCallConv', 'LLVMCall', 'LLVMCallBr', - 'LLVMCallConv', 'LLVMCallConv__enumvalues', - 'LLVMCallFrameAlignmentOfType', 'LLVMCatchPad', 'LLVMCatchRet', - 'LLVMCatchSwitch', 'LLVMCleanupPad', 'LLVMCleanupRet', - 'LLVMClearInsertionPosition', 'LLVMCloneModule', - 'LLVMCodeGenFileType', 'LLVMCodeGenFileType__enumvalues', - 'LLVMCodeGenLevelAggressive', 'LLVMCodeGenLevelDefault', - 'LLVMCodeGenLevelLess', 'LLVMCodeGenLevelNone', - 'LLVMCodeGenOptLevel', 'LLVMCodeGenOptLevel__enumvalues', - 'LLVMCodeModel', 'LLVMCodeModelDefault', - 'LLVMCodeModelJITDefault', 'LLVMCodeModelKernel', - 'LLVMCodeModelLarge', 'LLVMCodeModelMedium', 'LLVMCodeModelSmall', - 'LLVMCodeModelTiny', 'LLVMCodeModel__enumvalues', - 'LLVMColdCallConv', 'LLVMComdatRef', 'LLVMComdatSelectionKind', - 'LLVMComdatSelectionKind__enumvalues', 'LLVMCommonLinkage', - 'LLVMConstAShr', 'LLVMConstAdd', 'LLVMConstAddrSpaceCast', - 'LLVMConstAllOnes', 'LLVMConstAnd', 'LLVMConstArray', - 'LLVMConstBitCast', 'LLVMConstExactSDiv', 'LLVMConstExactUDiv', - 'LLVMConstExtractElement', 'LLVMConstExtractValue', - 'LLVMConstFAdd', 'LLVMConstFCmp', 'LLVMConstFDiv', - 'LLVMConstFMul', 'LLVMConstFNeg', 'LLVMConstFPCast', - 'LLVMConstFPExt', 'LLVMConstFPToSI', 'LLVMConstFPToUI', - 'LLVMConstFPTrunc', 'LLVMConstFRem', 'LLVMConstFSub', - 'LLVMConstGEP', 'LLVMConstGEP2', 'LLVMConstICmp', - 'LLVMConstInBoundsGEP', 'LLVMConstInBoundsGEP2', - 'LLVMConstInlineAsm', 'LLVMConstInsertElement', - 'LLVMConstInsertValue', 'LLVMConstInt', 'LLVMConstIntCast', - 'LLVMConstIntGetSExtValue', 'LLVMConstIntGetZExtValue', - 'LLVMConstIntOfArbitraryPrecision', 'LLVMConstIntOfString', - 'LLVMConstIntOfStringAndSize', 'LLVMConstIntToPtr', - 'LLVMConstLShr', 'LLVMConstMul', 'LLVMConstNSWAdd', - 'LLVMConstNSWMul', 'LLVMConstNSWNeg', 'LLVMConstNSWSub', - 'LLVMConstNUWAdd', 'LLVMConstNUWMul', 'LLVMConstNUWNeg', - 'LLVMConstNUWSub', 'LLVMConstNamedStruct', 'LLVMConstNeg', - 'LLVMConstNot', 'LLVMConstNull', 'LLVMConstOr', - 'LLVMConstPointerCast', 'LLVMConstPointerNull', - 'LLVMConstPtrToInt', 'LLVMConstReal', 'LLVMConstRealGetDouble', - 'LLVMConstRealOfString', 'LLVMConstRealOfStringAndSize', - 'LLVMConstSDiv', 'LLVMConstSExt', 'LLVMConstSExtOrBitCast', - 'LLVMConstSIToFP', 'LLVMConstSRem', 'LLVMConstSelect', - 'LLVMConstShl', 'LLVMConstShuffleVector', 'LLVMConstString', - 'LLVMConstStringInContext', 'LLVMConstStruct', - 'LLVMConstStructInContext', 'LLVMConstSub', 'LLVMConstTrunc', - 'LLVMConstTruncOrBitCast', 'LLVMConstUDiv', 'LLVMConstUIToFP', - 'LLVMConstURem', 'LLVMConstVector', 'LLVMConstXor', - 'LLVMConstZExt', 'LLVMConstZExtOrBitCast', - 'LLVMConstantAggregateZeroValueKind', - 'LLVMConstantArrayValueKind', - 'LLVMConstantAsMetadataMetadataKind', - 'LLVMConstantDataArrayValueKind', - 'LLVMConstantDataVectorValueKind', 'LLVMConstantExprValueKind', - 'LLVMConstantFPValueKind', 'LLVMConstantIntValueKind', - 'LLVMConstantPointerNullValueKind', 'LLVMConstantStructValueKind', - 'LLVMConstantTokenNoneValueKind', 'LLVMConstantVectorValueKind', - 'LLVMConsumeError', 'LLVMContextCreate', 'LLVMContextDispose', - 'LLVMContextGetDiagnosticContext', - 'LLVMContextGetDiagnosticHandler', 'LLVMContextRef', - 'LLVMContextSetDiagnosticHandler', - 'LLVMContextSetDiscardValueNames', 'LLVMContextSetYieldCallback', - 'LLVMContextShouldDiscardValueNames', - 'LLVMCopyModuleFlagsMetadata', 'LLVMCopyStringRepOfTargetData', - 'LLVMCountBasicBlocks', 'LLVMCountIncoming', - 'LLVMCountParamTypes', 'LLVMCountParams', - 'LLVMCountStructElementTypes', 'LLVMCreateBasicBlockInContext', - 'LLVMCreateBinary', 'LLVMCreateBuilder', - 'LLVMCreateBuilderInContext', 'LLVMCreateDIBuilder', - 'LLVMCreateDIBuilderDisallowUnresolved', 'LLVMCreateDisasm', - 'LLVMCreateDisasmCPU', 'LLVMCreateDisasmCPUFeatures', - 'LLVMCreateEnumAttribute', 'LLVMCreateExecutionEngineForModule', - 'LLVMCreateFunctionPassManager', - 'LLVMCreateFunctionPassManagerForModule', - 'LLVMCreateGDBRegistrationListener', - 'LLVMCreateGenericValueOfFloat', 'LLVMCreateGenericValueOfInt', - 'LLVMCreateGenericValueOfPointer', - 'LLVMCreateIntelJITEventListener', - 'LLVMCreateInterpreterForModule', - 'LLVMCreateJITCompilerForModule', - 'LLVMCreateMCJITCompilerForModule', - 'LLVMCreateMemoryBufferWithContentsOfFile', - 'LLVMCreateMemoryBufferWithMemoryRange', - 'LLVMCreateMemoryBufferWithMemoryRangeCopy', - 'LLVMCreateMemoryBufferWithSTDIN', 'LLVMCreateMessage', - 'LLVMCreateModuleProviderForExistingModule', - 'LLVMCreateOProfileJITEventListener', 'LLVMCreateObjectFile', - 'LLVMCreatePassBuilderOptions', 'LLVMCreatePassManager', - 'LLVMCreatePerfJITEventListener', - 'LLVMCreateSimpleMCJITMemoryManager', 'LLVMCreateStringAttribute', - 'LLVMCreateStringError', 'LLVMCreateTargetData', - 'LLVMCreateTargetDataLayout', 'LLVMCreateTargetMachine', - 'LLVMCreateTypeAttribute', 'LLVMDIArgListMetadataKind', - 'LLVMDIBasicTypeMetadataKind', 'LLVMDIBuilderCreateArrayType', - 'LLVMDIBuilderCreateArtificialType', - 'LLVMDIBuilderCreateAutoVariable', 'LLVMDIBuilderCreateBasicType', - 'LLVMDIBuilderCreateBitFieldMemberType', - 'LLVMDIBuilderCreateClassType', 'LLVMDIBuilderCreateCompileUnit', - 'LLVMDIBuilderCreateConstantValueExpression', - 'LLVMDIBuilderCreateDebugLocation', - 'LLVMDIBuilderCreateEnumerationType', - 'LLVMDIBuilderCreateEnumerator', 'LLVMDIBuilderCreateExpression', - 'LLVMDIBuilderCreateFile', 'LLVMDIBuilderCreateForwardDecl', - 'LLVMDIBuilderCreateFunction', - 'LLVMDIBuilderCreateGlobalVariableExpression', - 'LLVMDIBuilderCreateImportedDeclaration', - 'LLVMDIBuilderCreateImportedModuleFromAlias', - 'LLVMDIBuilderCreateImportedModuleFromModule', - 'LLVMDIBuilderCreateImportedModuleFromNamespace', - 'LLVMDIBuilderCreateInheritance', - 'LLVMDIBuilderCreateLexicalBlock', - 'LLVMDIBuilderCreateLexicalBlockFile', 'LLVMDIBuilderCreateMacro', - 'LLVMDIBuilderCreateMemberPointerType', - 'LLVMDIBuilderCreateMemberType', 'LLVMDIBuilderCreateModule', - 'LLVMDIBuilderCreateNameSpace', 'LLVMDIBuilderCreateNullPtrType', - 'LLVMDIBuilderCreateObjCIVar', 'LLVMDIBuilderCreateObjCProperty', - 'LLVMDIBuilderCreateObjectPointerType', - 'LLVMDIBuilderCreateParameterVariable', - 'LLVMDIBuilderCreatePointerType', - 'LLVMDIBuilderCreateQualifiedType', - 'LLVMDIBuilderCreateReferenceType', - 'LLVMDIBuilderCreateReplaceableCompositeType', - 'LLVMDIBuilderCreateStaticMemberType', - 'LLVMDIBuilderCreateStructType', - 'LLVMDIBuilderCreateSubroutineType', - 'LLVMDIBuilderCreateTempGlobalVariableFwdDecl', - 'LLVMDIBuilderCreateTempMacroFile', 'LLVMDIBuilderCreateTypedef', - 'LLVMDIBuilderCreateUnionType', - 'LLVMDIBuilderCreateUnspecifiedType', - 'LLVMDIBuilderCreateVectorType', 'LLVMDIBuilderFinalize', - 'LLVMDIBuilderFinalizeSubprogram', - 'LLVMDIBuilderGetOrCreateArray', - 'LLVMDIBuilderGetOrCreateSubrange', - 'LLVMDIBuilderGetOrCreateTypeArray', - 'LLVMDIBuilderInsertDbgValueAtEnd', - 'LLVMDIBuilderInsertDbgValueBefore', - 'LLVMDIBuilderInsertDeclareAtEnd', - 'LLVMDIBuilderInsertDeclareBefore', 'LLVMDIBuilderRef', - 'LLVMDICommonBlockMetadataKind', 'LLVMDICompileUnitMetadataKind', - 'LLVMDICompositeTypeMetadataKind', - 'LLVMDIDerivedTypeMetadataKind', 'LLVMDIEnumeratorMetadataKind', - 'LLVMDIExpressionMetadataKind', 'LLVMDIFileGetDirectory', - 'LLVMDIFileGetFilename', 'LLVMDIFileGetSource', - 'LLVMDIFileMetadataKind', 'LLVMDIFlagAccessibility', - 'LLVMDIFlagAppleBlock', 'LLVMDIFlagArtificial', - 'LLVMDIFlagBigEndian', 'LLVMDIFlagBitField', - 'LLVMDIFlagEnumClass', 'LLVMDIFlagExplicit', - 'LLVMDIFlagFixedEnum', 'LLVMDIFlagFwdDecl', - 'LLVMDIFlagIndirectVirtualBase', 'LLVMDIFlagIntroducedVirtual', - 'LLVMDIFlagLValueReference', 'LLVMDIFlagLittleEndian', - 'LLVMDIFlagMultipleInheritance', 'LLVMDIFlagNoReturn', - 'LLVMDIFlagNonTrivial', 'LLVMDIFlagObjcClassComplete', - 'LLVMDIFlagObjectPointer', 'LLVMDIFlagPrivate', - 'LLVMDIFlagProtected', 'LLVMDIFlagPrototyped', - 'LLVMDIFlagPtrToMemberRep', 'LLVMDIFlagPublic', - 'LLVMDIFlagRValueReference', 'LLVMDIFlagReserved', - 'LLVMDIFlagReservedBit4', 'LLVMDIFlagSingleInheritance', - 'LLVMDIFlagStaticMember', 'LLVMDIFlagThunk', - 'LLVMDIFlagTypePassByReference', 'LLVMDIFlagTypePassByValue', - 'LLVMDIFlagVector', 'LLVMDIFlagVirtual', - 'LLVMDIFlagVirtualInheritance', 'LLVMDIFlagZero', 'LLVMDIFlags', - 'LLVMDIFlags__enumvalues', 'LLVMDIGenericSubrangeMetadataKind', - 'LLVMDIGlobalVariableExpressionGetExpression', - 'LLVMDIGlobalVariableExpressionGetVariable', - 'LLVMDIGlobalVariableExpressionMetadataKind', - 'LLVMDIGlobalVariableMetadataKind', - 'LLVMDIImportedEntityMetadataKind', 'LLVMDILabelMetadataKind', - 'LLVMDILexicalBlockFileMetadataKind', - 'LLVMDILexicalBlockMetadataKind', - 'LLVMDILocalVariableMetadataKind', 'LLVMDILocationGetColumn', - 'LLVMDILocationGetInlinedAt', 'LLVMDILocationGetLine', - 'LLVMDILocationGetScope', 'LLVMDILocationMetadataKind', - 'LLVMDIMacroFileMetadataKind', 'LLVMDIMacroMetadataKind', - 'LLVMDIModuleMetadataKind', 'LLVMDINamespaceMetadataKind', - 'LLVMDIObjCPropertyMetadataKind', 'LLVMDIScopeGetFile', - 'LLVMDIStringTypeMetadataKind', 'LLVMDISubprogramGetLine', - 'LLVMDISubprogramMetadataKind', 'LLVMDISubrangeMetadataKind', - 'LLVMDISubroutineTypeMetadataKind', - 'LLVMDITemplateTypeParameterMetadataKind', - 'LLVMDITemplateValueParameterMetadataKind', - 'LLVMDITypeGetAlignInBits', 'LLVMDITypeGetFlags', - 'LLVMDITypeGetLine', 'LLVMDITypeGetName', - 'LLVMDITypeGetOffsetInBits', 'LLVMDITypeGetSizeInBits', - 'LLVMDIVariableGetFile', 'LLVMDIVariableGetLine', - 'LLVMDIVariableGetScope', 'LLVMDLLExportLinkage', - 'LLVMDLLExportStorageClass', 'LLVMDLLImportLinkage', - 'LLVMDLLImportStorageClass', 'LLVMDLLStorageClass', - 'LLVMDLLStorageClass__enumvalues', 'LLVMDSError', 'LLVMDSNote', - 'LLVMDSRemark', 'LLVMDSWarning', 'LLVMDWARFEmissionFull', - 'LLVMDWARFEmissionKind', 'LLVMDWARFEmissionKind__enumvalues', - 'LLVMDWARFEmissionLineTablesOnly', 'LLVMDWARFEmissionNone', - 'LLVMDWARFMacinfoRecordType', 'LLVMDWARFMacinfoRecordTypeDefine', - 'LLVMDWARFMacinfoRecordTypeEndFile', - 'LLVMDWARFMacinfoRecordTypeMacro', - 'LLVMDWARFMacinfoRecordTypeStartFile', - 'LLVMDWARFMacinfoRecordTypeVendorExt', - 'LLVMDWARFMacinfoRecordType__enumvalues', - 'LLVMDWARFSourceLanguage', 'LLVMDWARFSourceLanguageAda83', - 'LLVMDWARFSourceLanguageAda95', 'LLVMDWARFSourceLanguageBLISS', - 'LLVMDWARFSourceLanguageBORLAND_Delphi', - 'LLVMDWARFSourceLanguageC', 'LLVMDWARFSourceLanguageC11', - 'LLVMDWARFSourceLanguageC89', 'LLVMDWARFSourceLanguageC99', - 'LLVMDWARFSourceLanguageC_plus_plus', - 'LLVMDWARFSourceLanguageC_plus_plus_03', - 'LLVMDWARFSourceLanguageC_plus_plus_11', - 'LLVMDWARFSourceLanguageC_plus_plus_14', - 'LLVMDWARFSourceLanguageCobol74', - 'LLVMDWARFSourceLanguageCobol85', 'LLVMDWARFSourceLanguageD', - 'LLVMDWARFSourceLanguageDylan', - 'LLVMDWARFSourceLanguageFortran03', - 'LLVMDWARFSourceLanguageFortran08', - 'LLVMDWARFSourceLanguageFortran77', - 'LLVMDWARFSourceLanguageFortran90', - 'LLVMDWARFSourceLanguageFortran95', - 'LLVMDWARFSourceLanguageGOOGLE_RenderScript', - 'LLVMDWARFSourceLanguageGo', 'LLVMDWARFSourceLanguageHaskell', - 'LLVMDWARFSourceLanguageJava', 'LLVMDWARFSourceLanguageJulia', - 'LLVMDWARFSourceLanguageMips_Assembler', - 'LLVMDWARFSourceLanguageModula2', - 'LLVMDWARFSourceLanguageModula3', 'LLVMDWARFSourceLanguageOCaml', - 'LLVMDWARFSourceLanguageObjC', - 'LLVMDWARFSourceLanguageObjC_plus_plus', - 'LLVMDWARFSourceLanguageOpenCL', 'LLVMDWARFSourceLanguagePLI', - 'LLVMDWARFSourceLanguagePascal83', - 'LLVMDWARFSourceLanguagePython', - 'LLVMDWARFSourceLanguageRenderScript', - 'LLVMDWARFSourceLanguageRust', 'LLVMDWARFSourceLanguageSwift', - 'LLVMDWARFSourceLanguageUPC', - 'LLVMDWARFSourceLanguage__enumvalues', 'LLVMDWARFTypeEncoding', - 'LLVMDebugMetadataVersion', 'LLVMDefaultStorageClass', - 'LLVMDefaultVisibility', 'LLVMDeleteBasicBlock', - 'LLVMDeleteFunction', 'LLVMDeleteGlobal', 'LLVMDiagnosticHandler', - 'LLVMDiagnosticInfoRef', 'LLVMDiagnosticSeverity', - 'LLVMDiagnosticSeverity__enumvalues', 'LLVMDisasmContextRef', - 'LLVMDisasmDispose', 'LLVMDisasmInstruction', - 'LLVMDisassembler_Option_AsmPrinterVariant', - 'LLVMDisassembler_Option_PrintImmHex', - 'LLVMDisassembler_Option_PrintLatency', - 'LLVMDisassembler_Option_SetInstrComments', - 'LLVMDisassembler_Option_UseMarkup', - 'LLVMDisassembler_ReferenceType_DeMangled_Name', - 'LLVMDisassembler_ReferenceType_InOut_None', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADDXri', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADR', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADRP', - 'LLVMDisassembler_ReferenceType_In_ARM64_LDRXl', - 'LLVMDisassembler_ReferenceType_In_ARM64_LDRXui', - 'LLVMDisassembler_ReferenceType_In_Branch', - 'LLVMDisassembler_ReferenceType_In_PCrel_Load', - 'LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr', - 'LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr', - 'LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Message', - 'LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref', - 'LLVMDisassembler_ReferenceType_Out_SymbolStub', - 'LLVMDisassembler_VariantKind_ARM64_GOTPAGE', - 'LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF', - 'LLVMDisassembler_VariantKind_ARM64_PAGE', - 'LLVMDisassembler_VariantKind_ARM64_PAGEOFF', - 'LLVMDisassembler_VariantKind_ARM64_TLVOFF', - 'LLVMDisassembler_VariantKind_ARM64_TLVP', - 'LLVMDisassembler_VariantKind_ARM_HI16', - 'LLVMDisassembler_VariantKind_ARM_LO16', - 'LLVMDisassembler_VariantKind_None', 'LLVMDisposeBinary', - 'LLVMDisposeBuilder', 'LLVMDisposeDIBuilder', - 'LLVMDisposeErrorMessage', 'LLVMDisposeExecutionEngine', - 'LLVMDisposeGenericValue', 'LLVMDisposeMCJITMemoryManager', - 'LLVMDisposeMemoryBuffer', 'LLVMDisposeMessage', - 'LLVMDisposeModule', 'LLVMDisposeModuleFlagsMetadata', - 'LLVMDisposeModuleProvider', 'LLVMDisposeObjectFile', - 'LLVMDisposePassBuilderOptions', 'LLVMDisposePassManager', - 'LLVMDisposeRelocationIterator', 'LLVMDisposeSectionIterator', - 'LLVMDisposeSymbolIterator', 'LLVMDisposeTargetData', - 'LLVMDisposeTargetMachine', 'LLVMDisposeTemporaryMDNode', - 'LLVMDisposeValueMetadataEntries', - 'LLVMDistinctMDOperandPlaceholderMetadataKind', 'LLVMDoubleType', - 'LLVMDoubleTypeInContext', 'LLVMDoubleTypeKind', 'LLVMDumpModule', - 'LLVMDumpType', 'LLVMDumpValue', 'LLVMElementAtOffset', - 'LLVMEnablePrettyStackTrace', 'LLVMEraseGlobalIFunc', - 'LLVMErrorRef', 'LLVMErrorSuccess', 'LLVMErrorTypeId', - 'LLVMExactMatchComdatSelectionKind', - 'LLVMExecutionEngineGetErrMsg', 'LLVMExecutionEngineRef', - 'LLVMExternalLinkage', 'LLVMExternalWeakLinkage', - 'LLVMExtractElement', 'LLVMExtractValue', 'LLVMFAdd', 'LLVMFCmp', - 'LLVMFDiv', 'LLVMFMul', 'LLVMFNeg', 'LLVMFP128Type', - 'LLVMFP128TypeInContext', 'LLVMFP128TypeKind', 'LLVMFPExt', - 'LLVMFPToSI', 'LLVMFPToUI', 'LLVMFPTrunc', 'LLVMFRem', 'LLVMFSub', - 'LLVMFastCallConv', 'LLVMFatalErrorHandler', 'LLVMFence', - 'LLVMFinalizeFunctionPassManager', 'LLVMFindFunction', - 'LLVMFloatType', 'LLVMFloatTypeInContext', 'LLVMFloatTypeKind', - 'LLVMFreeMachineCodeForFunction', 'LLVMFreeze', - 'LLVMFunctionType', 'LLVMFunctionTypeKind', - 'LLVMFunctionValueKind', 'LLVMGHCCallConv', - 'LLVMGeneralDynamicTLSModel', 'LLVMGenericDINodeMetadataKind', - 'LLVMGenericValueIntWidth', 'LLVMGenericValueRef', - 'LLVMGenericValueToFloat', 'LLVMGenericValueToInt', - 'LLVMGenericValueToPointer', 'LLVMGetAlignment', - 'LLVMGetAllocatedType', 'LLVMGetArgOperand', 'LLVMGetArrayLength', - 'LLVMGetAsString', 'LLVMGetAtomicRMWBinOp', - 'LLVMGetAttributeCountAtIndex', 'LLVMGetAttributesAtIndex', - 'LLVMGetBasicBlockName', 'LLVMGetBasicBlockParent', - 'LLVMGetBasicBlockTerminator', 'LLVMGetBasicBlocks', - 'LLVMGetBitcodeModule', 'LLVMGetBitcodeModule2', - 'LLVMGetBitcodeModuleInContext', 'LLVMGetBitcodeModuleInContext2', - 'LLVMGetBufferSize', 'LLVMGetBufferStart', - 'LLVMGetCallSiteAttributeCount', 'LLVMGetCallSiteAttributes', - 'LLVMGetCallSiteEnumAttribute', 'LLVMGetCallSiteStringAttribute', - 'LLVMGetCalledFunctionType', 'LLVMGetCalledValue', - 'LLVMGetClause', 'LLVMGetCmpXchgFailureOrdering', - 'LLVMGetCmpXchgSuccessOrdering', 'LLVMGetComdat', - 'LLVMGetComdatSelectionKind', 'LLVMGetCondition', - 'LLVMGetConstOpcode', 'LLVMGetCurrentDebugLocation', - 'LLVMGetCurrentDebugLocation2', 'LLVMGetDLLStorageClass', - 'LLVMGetDataLayout', 'LLVMGetDataLayoutStr', - 'LLVMGetDebugLocColumn', 'LLVMGetDebugLocDirectory', - 'LLVMGetDebugLocFilename', 'LLVMGetDebugLocLine', - 'LLVMGetDefaultTargetTriple', 'LLVMGetDiagInfoDescription', - 'LLVMGetDiagInfoSeverity', 'LLVMGetElementAsConstant', - 'LLVMGetElementPtr', 'LLVMGetElementType', - 'LLVMGetEntryBasicBlock', 'LLVMGetEnumAttributeAtIndex', - 'LLVMGetEnumAttributeKind', 'LLVMGetEnumAttributeKindForName', - 'LLVMGetEnumAttributeValue', 'LLVMGetErrorMessage', - 'LLVMGetErrorTypeId', 'LLVMGetExecutionEngineTargetData', - 'LLVMGetExecutionEngineTargetMachine', 'LLVMGetFCmpPredicate', - 'LLVMGetFirstBasicBlock', 'LLVMGetFirstFunction', - 'LLVMGetFirstGlobal', 'LLVMGetFirstGlobalAlias', - 'LLVMGetFirstGlobalIFunc', 'LLVMGetFirstInstruction', - 'LLVMGetFirstNamedMetadata', 'LLVMGetFirstParam', - 'LLVMGetFirstTarget', 'LLVMGetFirstUse', 'LLVMGetFunctionAddress', - 'LLVMGetFunctionCallConv', 'LLVMGetGC', - 'LLVMGetGEPSourceElementType', 'LLVMGetGlobalContext', - 'LLVMGetGlobalIFuncResolver', 'LLVMGetGlobalParent', - 'LLVMGetGlobalPassRegistry', 'LLVMGetGlobalValueAddress', - 'LLVMGetHandlers', 'LLVMGetHostCPUFeatures', 'LLVMGetHostCPUName', - 'LLVMGetICmpPredicate', 'LLVMGetIncomingBlock', - 'LLVMGetIncomingValue', 'LLVMGetIndices', 'LLVMGetInitializer', - 'LLVMGetInlineAsm', 'LLVMGetInsertBlock', - 'LLVMGetInstructionCallConv', 'LLVMGetInstructionOpcode', - 'LLVMGetInstructionParent', 'LLVMGetIntTypeWidth', - 'LLVMGetIntrinsicDeclaration', 'LLVMGetIntrinsicID', - 'LLVMGetLastBasicBlock', 'LLVMGetLastEnumAttributeKind', - 'LLVMGetLastFunction', 'LLVMGetLastGlobal', - 'LLVMGetLastGlobalAlias', 'LLVMGetLastGlobalIFunc', - 'LLVMGetLastInstruction', 'LLVMGetLastNamedMetadata', - 'LLVMGetLastParam', 'LLVMGetLinkage', 'LLVMGetMDKindID', - 'LLVMGetMDKindIDInContext', 'LLVMGetMDNodeNumOperands', - 'LLVMGetMDNodeOperands', 'LLVMGetMDString', 'LLVMGetMaskValue', - 'LLVMGetMetadata', 'LLVMGetMetadataKind', 'LLVMGetModuleContext', - 'LLVMGetModuleDataLayout', 'LLVMGetModuleDebugMetadataVersion', - 'LLVMGetModuleFlag', 'LLVMGetModuleIdentifier', - 'LLVMGetModuleInlineAsm', 'LLVMGetNamedFunction', - 'LLVMGetNamedGlobal', 'LLVMGetNamedGlobalAlias', - 'LLVMGetNamedGlobalIFunc', 'LLVMGetNamedMetadata', - 'LLVMGetNamedMetadataName', 'LLVMGetNamedMetadataNumOperands', - 'LLVMGetNamedMetadataOperands', 'LLVMGetNextBasicBlock', - 'LLVMGetNextFunction', 'LLVMGetNextGlobal', - 'LLVMGetNextGlobalAlias', 'LLVMGetNextGlobalIFunc', - 'LLVMGetNextInstruction', 'LLVMGetNextNamedMetadata', - 'LLVMGetNextParam', 'LLVMGetNextTarget', 'LLVMGetNextUse', - 'LLVMGetNormalDest', 'LLVMGetNumArgOperands', 'LLVMGetNumClauses', - 'LLVMGetNumContainedTypes', 'LLVMGetNumHandlers', - 'LLVMGetNumIndices', 'LLVMGetNumMaskElements', - 'LLVMGetNumOperands', 'LLVMGetNumSuccessors', 'LLVMGetOperand', - 'LLVMGetOperandUse', 'LLVMGetOrInsertComdat', - 'LLVMGetOrInsertNamedMetadata', 'LLVMGetOrdering', 'LLVMGetParam', - 'LLVMGetParamParent', 'LLVMGetParamTypes', 'LLVMGetParams', - 'LLVMGetParentCatchSwitch', 'LLVMGetPersonalityFn', - 'LLVMGetPointerAddressSpace', 'LLVMGetPointerToGlobal', - 'LLVMGetPoison', 'LLVMGetPreviousBasicBlock', - 'LLVMGetPreviousFunction', 'LLVMGetPreviousGlobal', - 'LLVMGetPreviousGlobalAlias', 'LLVMGetPreviousGlobalIFunc', - 'LLVMGetPreviousInstruction', 'LLVMGetPreviousNamedMetadata', - 'LLVMGetPreviousParam', 'LLVMGetRelocationOffset', - 'LLVMGetRelocationSymbol', 'LLVMGetRelocationType', - 'LLVMGetRelocationTypeName', 'LLVMGetRelocationValueString', - 'LLVMGetRelocations', 'LLVMGetReturnType', 'LLVMGetSection', - 'LLVMGetSectionAddress', 'LLVMGetSectionContainsSymbol', - 'LLVMGetSectionContents', 'LLVMGetSectionName', - 'LLVMGetSectionSize', 'LLVMGetSections', 'LLVMGetSourceFileName', - 'LLVMGetStringAttributeAtIndex', 'LLVMGetStringAttributeKind', - 'LLVMGetStringAttributeValue', 'LLVMGetStringErrorTypeId', - 'LLVMGetStructElementTypes', 'LLVMGetStructName', - 'LLVMGetSubprogram', 'LLVMGetSubtypes', 'LLVMGetSuccessor', - 'LLVMGetSwitchDefaultDest', 'LLVMGetSymbolAddress', - 'LLVMGetSymbolName', 'LLVMGetSymbolSize', 'LLVMGetSymbols', - 'LLVMGetTarget', 'LLVMGetTargetDescription', - 'LLVMGetTargetFromName', 'LLVMGetTargetFromTriple', - 'LLVMGetTargetMachineCPU', 'LLVMGetTargetMachineFeatureString', - 'LLVMGetTargetMachineTarget', 'LLVMGetTargetMachineTriple', - 'LLVMGetTargetName', 'LLVMGetThreadLocalMode', - 'LLVMGetTypeAttributeValue', 'LLVMGetTypeByName', - 'LLVMGetTypeByName2', 'LLVMGetTypeContext', 'LLVMGetTypeKind', - 'LLVMGetUndef', 'LLVMGetUndefMaskElem', 'LLVMGetUnnamedAddress', - 'LLVMGetUnwindDest', 'LLVMGetUsedValue', 'LLVMGetUser', - 'LLVMGetValueKind', 'LLVMGetValueName', 'LLVMGetValueName2', - 'LLVMGetVectorSize', 'LLVMGetVisibility', 'LLVMGetVolatile', - 'LLVMGetWeak', 'LLVMGhostLinkage', 'LLVMGlobalAliasValueKind', - 'LLVMGlobalClearMetadata', 'LLVMGlobalCopyAllMetadata', - 'LLVMGlobalEraseMetadata', 'LLVMGlobalGetValueType', - 'LLVMGlobalIFuncValueKind', 'LLVMGlobalSetMetadata', - 'LLVMGlobalUnnamedAddr', 'LLVMGlobalVariableValueKind', - 'LLVMHHVMCCallConv', 'LLVMHHVMCallConv', 'LLVMHalfType', - 'LLVMHalfTypeInContext', 'LLVMHalfTypeKind', 'LLVMHasMetadata', - 'LLVMHasPersonalityFn', 'LLVMHasUnnamedAddr', 'LLVMHiPECallConv', - 'LLVMHiddenVisibility', 'LLVMICmp', 'LLVMIndirectBr', - 'LLVMInitialExecTLSModel', 'LLVMInitializeAArch64AsmParser', - 'LLVMInitializeAArch64AsmPrinter', - 'LLVMInitializeAArch64Disassembler', - 'LLVMInitializeAArch64Target', 'LLVMInitializeAArch64TargetInfo', - 'LLVMInitializeAArch64TargetMC', 'LLVMInitializeAMDGPUAsmParser', - 'LLVMInitializeAMDGPUAsmPrinter', - 'LLVMInitializeAMDGPUDisassembler', 'LLVMInitializeAMDGPUTarget', - 'LLVMInitializeAMDGPUTargetInfo', 'LLVMInitializeAMDGPUTargetMC', - 'LLVMInitializeARMAsmParser', 'LLVMInitializeARMAsmPrinter', - 'LLVMInitializeARMDisassembler', 'LLVMInitializeARMTarget', - 'LLVMInitializeARMTargetInfo', 'LLVMInitializeARMTargetMC', - 'LLVMInitializeAVRAsmParser', 'LLVMInitializeAVRAsmPrinter', - 'LLVMInitializeAVRDisassembler', 'LLVMInitializeAVRTarget', - 'LLVMInitializeAVRTargetInfo', 'LLVMInitializeAVRTargetMC', - 'LLVMInitializeAggressiveInstCombiner', - 'LLVMInitializeAllAsmParsers', 'LLVMInitializeAllAsmPrinters', - 'LLVMInitializeAllDisassemblers', 'LLVMInitializeAllTargetInfos', - 'LLVMInitializeAllTargetMCs', 'LLVMInitializeAllTargets', - 'LLVMInitializeAnalysis', 'LLVMInitializeBPFAsmParser', - 'LLVMInitializeBPFAsmPrinter', 'LLVMInitializeBPFDisassembler', - 'LLVMInitializeBPFTarget', 'LLVMInitializeBPFTargetInfo', - 'LLVMInitializeBPFTargetMC', 'LLVMInitializeCodeGen', - 'LLVMInitializeCore', 'LLVMInitializeFunctionPassManager', - 'LLVMInitializeHexagonAsmParser', - 'LLVMInitializeHexagonAsmPrinter', - 'LLVMInitializeHexagonDisassembler', - 'LLVMInitializeHexagonTarget', 'LLVMInitializeHexagonTargetInfo', - 'LLVMInitializeHexagonTargetMC', 'LLVMInitializeIPA', - 'LLVMInitializeIPO', 'LLVMInitializeInstCombine', - 'LLVMInitializeInstrumentation', 'LLVMInitializeLanaiAsmParser', - 'LLVMInitializeLanaiAsmPrinter', - 'LLVMInitializeLanaiDisassembler', 'LLVMInitializeLanaiTarget', - 'LLVMInitializeLanaiTargetInfo', 'LLVMInitializeLanaiTargetMC', - 'LLVMInitializeM68kAsmParser', 'LLVMInitializeM68kAsmPrinter', - 'LLVMInitializeM68kDisassembler', 'LLVMInitializeM68kTarget', - 'LLVMInitializeM68kTargetInfo', 'LLVMInitializeM68kTargetMC', - 'LLVMInitializeMCJITCompilerOptions', - 'LLVMInitializeMSP430AsmParser', 'LLVMInitializeMSP430AsmPrinter', - 'LLVMInitializeMSP430Disassembler', 'LLVMInitializeMSP430Target', - 'LLVMInitializeMSP430TargetInfo', 'LLVMInitializeMSP430TargetMC', - 'LLVMInitializeMipsAsmParser', 'LLVMInitializeMipsAsmPrinter', - 'LLVMInitializeMipsDisassembler', 'LLVMInitializeMipsTarget', - 'LLVMInitializeMipsTargetInfo', 'LLVMInitializeMipsTargetMC', - 'LLVMInitializeNVPTXAsmPrinter', 'LLVMInitializeNVPTXTarget', - 'LLVMInitializeNVPTXTargetInfo', 'LLVMInitializeNVPTXTargetMC', - 'LLVMInitializeNativeAsmParser', 'LLVMInitializeNativeAsmPrinter', - 'LLVMInitializeNativeDisassembler', 'LLVMInitializeNativeTarget', - 'LLVMInitializeObjCARCOpts', 'LLVMInitializePowerPCAsmParser', - 'LLVMInitializePowerPCAsmPrinter', - 'LLVMInitializePowerPCDisassembler', - 'LLVMInitializePowerPCTarget', 'LLVMInitializePowerPCTargetInfo', - 'LLVMInitializePowerPCTargetMC', 'LLVMInitializeRISCVAsmParser', - 'LLVMInitializeRISCVAsmPrinter', - 'LLVMInitializeRISCVDisassembler', 'LLVMInitializeRISCVTarget', - 'LLVMInitializeRISCVTargetInfo', 'LLVMInitializeRISCVTargetMC', - 'LLVMInitializeScalarOpts', 'LLVMInitializeSparcAsmParser', - 'LLVMInitializeSparcAsmPrinter', - 'LLVMInitializeSparcDisassembler', 'LLVMInitializeSparcTarget', - 'LLVMInitializeSparcTargetInfo', 'LLVMInitializeSparcTargetMC', - 'LLVMInitializeSystemZAsmParser', - 'LLVMInitializeSystemZAsmPrinter', - 'LLVMInitializeSystemZDisassembler', - 'LLVMInitializeSystemZTarget', 'LLVMInitializeSystemZTargetInfo', - 'LLVMInitializeSystemZTargetMC', 'LLVMInitializeTarget', - 'LLVMInitializeTransformUtils', 'LLVMInitializeVEAsmParser', - 'LLVMInitializeVEAsmPrinter', 'LLVMInitializeVEDisassembler', - 'LLVMInitializeVETarget', 'LLVMInitializeVETargetInfo', - 'LLVMInitializeVETargetMC', 'LLVMInitializeVectorization', - 'LLVMInitializeWebAssemblyAsmParser', - 'LLVMInitializeWebAssemblyAsmPrinter', - 'LLVMInitializeWebAssemblyDisassembler', - 'LLVMInitializeWebAssemblyTarget', - 'LLVMInitializeWebAssemblyTargetInfo', - 'LLVMInitializeWebAssemblyTargetMC', 'LLVMInitializeX86AsmParser', - 'LLVMInitializeX86AsmPrinter', 'LLVMInitializeX86Disassembler', - 'LLVMInitializeX86Target', 'LLVMInitializeX86TargetInfo', - 'LLVMInitializeX86TargetMC', 'LLVMInitializeXCoreAsmPrinter', - 'LLVMInitializeXCoreDisassembler', 'LLVMInitializeXCoreTarget', - 'LLVMInitializeXCoreTargetInfo', 'LLVMInitializeXCoreTargetMC', - 'LLVMInlineAsmDialect', 'LLVMInlineAsmDialectATT', - 'LLVMInlineAsmDialectIntel', 'LLVMInlineAsmDialect__enumvalues', - 'LLVMInlineAsmValueKind', 'LLVMInsertBasicBlock', - 'LLVMInsertBasicBlockInContext', 'LLVMInsertElement', - 'LLVMInsertExistingBasicBlockAfterInsertBlock', - 'LLVMInsertIntoBuilder', 'LLVMInsertIntoBuilderWithName', - 'LLVMInsertValue', 'LLVMInstallFatalErrorHandler', - 'LLVMInstructionClone', 'LLVMInstructionEraseFromParent', - 'LLVMInstructionGetAllMetadataOtherThanDebugLoc', - 'LLVMInstructionGetDebugLoc', 'LLVMInstructionRemoveFromParent', - 'LLVMInstructionSetDebugLoc', 'LLVMInstructionValueKind', - 'LLVMInt128Type', 'LLVMInt128TypeInContext', 'LLVMInt16Type', - 'LLVMInt16TypeInContext', 'LLVMInt1Type', 'LLVMInt1TypeInContext', - 'LLVMInt32Type', 'LLVMInt32TypeInContext', 'LLVMInt64Type', - 'LLVMInt64TypeInContext', 'LLVMInt8Type', 'LLVMInt8TypeInContext', - 'LLVMIntEQ', 'LLVMIntNE', 'LLVMIntPredicate', - 'LLVMIntPredicate__enumvalues', 'LLVMIntPtrType', - 'LLVMIntPtrTypeForAS', 'LLVMIntPtrTypeForASInContext', - 'LLVMIntPtrTypeInContext', 'LLVMIntSGE', 'LLVMIntSGT', - 'LLVMIntSLE', 'LLVMIntSLT', 'LLVMIntToPtr', 'LLVMIntType', - 'LLVMIntTypeInContext', 'LLVMIntUGE', 'LLVMIntUGT', 'LLVMIntULE', - 'LLVMIntULT', 'LLVMIntegerTypeKind', 'LLVMIntelOCLBICallConv', - 'LLVMInternalLinkage', 'LLVMIntrinsicCopyOverloadedName', - 'LLVMIntrinsicCopyOverloadedName2', 'LLVMIntrinsicGetName', - 'LLVMIntrinsicGetType', 'LLVMIntrinsicIsOverloaded', 'LLVMInvoke', - 'LLVMIsAAddrSpaceCastInst', 'LLVMIsAAllocaInst', - 'LLVMIsAArgument', 'LLVMIsAAtomicCmpXchgInst', - 'LLVMIsAAtomicRMWInst', 'LLVMIsABasicBlock', - 'LLVMIsABinaryOperator', 'LLVMIsABitCastInst', - 'LLVMIsABlockAddress', 'LLVMIsABranchInst', 'LLVMIsACallBrInst', - 'LLVMIsACallInst', 'LLVMIsACastInst', 'LLVMIsACatchPadInst', - 'LLVMIsACatchReturnInst', 'LLVMIsACatchSwitchInst', - 'LLVMIsACleanupPadInst', 'LLVMIsACleanupReturnInst', - 'LLVMIsACmpInst', 'LLVMIsAConstant', - 'LLVMIsAConstantAggregateZero', 'LLVMIsAConstantArray', - 'LLVMIsAConstantDataArray', 'LLVMIsAConstantDataSequential', - 'LLVMIsAConstantDataVector', 'LLVMIsAConstantExpr', - 'LLVMIsAConstantFP', 'LLVMIsAConstantInt', - 'LLVMIsAConstantPointerNull', 'LLVMIsAConstantStruct', - 'LLVMIsAConstantTokenNone', 'LLVMIsAConstantVector', - 'LLVMIsADbgDeclareInst', 'LLVMIsADbgInfoIntrinsic', - 'LLVMIsADbgLabelInst', 'LLVMIsADbgVariableIntrinsic', - 'LLVMIsAExtractElementInst', 'LLVMIsAExtractValueInst', - 'LLVMIsAFCmpInst', 'LLVMIsAFPExtInst', 'LLVMIsAFPToSIInst', - 'LLVMIsAFPToUIInst', 'LLVMIsAFPTruncInst', 'LLVMIsAFenceInst', - 'LLVMIsAFreezeInst', 'LLVMIsAFuncletPadInst', 'LLVMIsAFunction', - 'LLVMIsAGetElementPtrInst', 'LLVMIsAGlobalAlias', - 'LLVMIsAGlobalIFunc', 'LLVMIsAGlobalObject', 'LLVMIsAGlobalValue', - 'LLVMIsAGlobalVariable', 'LLVMIsAICmpInst', - 'LLVMIsAIndirectBrInst', 'LLVMIsAInlineAsm', - 'LLVMIsAInsertElementInst', 'LLVMIsAInsertValueInst', - 'LLVMIsAInstruction', 'LLVMIsAIntToPtrInst', - 'LLVMIsAIntrinsicInst', 'LLVMIsAInvokeInst', - 'LLVMIsALandingPadInst', 'LLVMIsALoadInst', 'LLVMIsAMDNode', - 'LLVMIsAMDString', 'LLVMIsAMemCpyInst', 'LLVMIsAMemIntrinsic', - 'LLVMIsAMemMoveInst', 'LLVMIsAMemSetInst', 'LLVMIsAPHINode', - 'LLVMIsAPoisonValue', 'LLVMIsAPtrToIntInst', 'LLVMIsAResumeInst', - 'LLVMIsAReturnInst', 'LLVMIsASExtInst', 'LLVMIsASIToFPInst', - 'LLVMIsASelectInst', 'LLVMIsAShuffleVectorInst', - 'LLVMIsAStoreInst', 'LLVMIsASwitchInst', 'LLVMIsATerminatorInst', - 'LLVMIsATruncInst', 'LLVMIsAUIToFPInst', - 'LLVMIsAUnaryInstruction', 'LLVMIsAUnaryOperator', - 'LLVMIsAUndefValue', 'LLVMIsAUnreachableInst', 'LLVMIsAUser', - 'LLVMIsAVAArgInst', 'LLVMIsAZExtInst', 'LLVMIsAtomicSingleThread', - 'LLVMIsCleanup', 'LLVMIsConditional', 'LLVMIsConstant', - 'LLVMIsConstantString', 'LLVMIsDeclaration', - 'LLVMIsEnumAttribute', 'LLVMIsExternallyInitialized', - 'LLVMIsFunctionVarArg', 'LLVMIsGlobalConstant', 'LLVMIsInBounds', - 'LLVMIsLiteralStruct', 'LLVMIsMultithreaded', 'LLVMIsNull', - 'LLVMIsOpaqueStruct', 'LLVMIsPackedStruct', 'LLVMIsPoison', - 'LLVMIsRelocationIteratorAtEnd', 'LLVMIsSectionIteratorAtEnd', - 'LLVMIsStringAttribute', 'LLVMIsSymbolIteratorAtEnd', - 'LLVMIsTailCall', 'LLVMIsThreadLocal', 'LLVMIsTypeAttribute', - 'LLVMIsUndef', 'LLVMJITCSymbolMapPair', 'LLVMJITEvaluatedSymbol', - 'LLVMJITEventListenerRef', 'LLVMJITSymbolFlags', - 'LLVMJITSymbolGenericFlags', 'LLVMJITSymbolGenericFlagsCallable', - 'LLVMJITSymbolGenericFlagsExported', - 'LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly', - 'LLVMJITSymbolGenericFlagsWeak', - 'LLVMJITSymbolGenericFlags__enumvalues', - 'LLVMJITSymbolTargetFlags', 'LLVMLShr', 'LLVMLabelType', - 'LLVMLabelTypeInContext', 'LLVMLabelTypeKind', 'LLVMLandingPad', - 'LLVMLandingPadCatch', 'LLVMLandingPadClauseTy', - 'LLVMLandingPadClauseTy__enumvalues', 'LLVMLandingPadFilter', - 'LLVMLargestComdatSelectionKind', 'LLVMLinkInInterpreter', - 'LLVMLinkInMCJIT', 'LLVMLinkModules2', 'LLVMLinkOnceAnyLinkage', - 'LLVMLinkOnceODRAutoHideLinkage', 'LLVMLinkOnceODRLinkage', - 'LLVMLinkage', 'LLVMLinkage__enumvalues', - 'LLVMLinkerDestroySource', 'LLVMLinkerMode', - 'LLVMLinkerMode__enumvalues', 'LLVMLinkerPreserveSource_Removed', - 'LLVMLinkerPrivateLinkage', 'LLVMLinkerPrivateWeakLinkage', - 'LLVMLittleEndian', 'LLVMLoad', 'LLVMLoadLibraryPermanently', - 'LLVMLocalAsMetadataMetadataKind', 'LLVMLocalDynamicTLSModel', - 'LLVMLocalExecTLSModel', 'LLVMLocalUnnamedAddr', - 'LLVMLookupIntrinsicID', 'LLVMMCJITMemoryManagerRef', - 'LLVMMDNode', 'LLVMMDNodeInContext', 'LLVMMDNodeInContext2', - 'LLVMMDString', 'LLVMMDStringInContext', 'LLVMMDStringInContext2', - 'LLVMMDStringMetadataKind', 'LLVMMDTupleMetadataKind', - 'LLVMMSP430BUILTINCallConv', 'LLVMMSP430INTRCallConv', - 'LLVMMachOUniversalBinaryCopyObjectForArch', - 'LLVMMemoryBufferRef', 'LLVMMemoryDefValueKind', - 'LLVMMemoryManagerAllocateCodeSectionCallback', - 'LLVMMemoryManagerAllocateDataSectionCallback', - 'LLVMMemoryManagerDestroyCallback', - 'LLVMMemoryManagerFinalizeMemoryCallback', - 'LLVMMemoryPhiValueKind', 'LLVMMemoryUseValueKind', - 'LLVMMetadataAsValue', 'LLVMMetadataAsValueValueKind', - 'LLVMMetadataKind', 'LLVMMetadataRef', - 'LLVMMetadataReplaceAllUsesWith', 'LLVMMetadataTypeInContext', - 'LLVMMetadataTypeKind', 'LLVMModuleCreateWithName', - 'LLVMModuleCreateWithNameInContext', 'LLVMModuleFlagBehavior', - 'LLVMModuleFlagBehaviorAppend', - 'LLVMModuleFlagBehaviorAppendUnique', - 'LLVMModuleFlagBehaviorError', 'LLVMModuleFlagBehaviorOverride', - 'LLVMModuleFlagBehaviorRequire', 'LLVMModuleFlagBehaviorWarning', - 'LLVMModuleFlagBehavior__enumvalues', - 'LLVMModuleFlagEntriesGetFlagBehavior', - 'LLVMModuleFlagEntriesGetKey', 'LLVMModuleFlagEntriesGetMetadata', - 'LLVMModuleFlagEntry', 'LLVMModuleProviderRef', 'LLVMModuleRef', - 'LLVMMoveBasicBlockAfter', 'LLVMMoveBasicBlockBefore', - 'LLVMMoveToContainingSection', 'LLVMMoveToNextRelocation', - 'LLVMMoveToNextSection', 'LLVMMoveToNextSymbol', 'LLVMMul', - 'LLVMNamedMDNodeRef', 'LLVMNoDeduplicateComdatSelectionKind', - 'LLVMNoUnnamedAddr', 'LLVMNormalizeTargetTriple', - 'LLVMNotThreadLocal', 'LLVMObjectFile', - 'LLVMObjectFileCopySectionIterator', - 'LLVMObjectFileCopySymbolIterator', - 'LLVMObjectFileIsSectionIteratorAtEnd', - 'LLVMObjectFileIsSymbolIteratorAtEnd', 'LLVMObjectFileRef', - 'LLVMOffsetOfElement', 'LLVMOpInfoCallback', 'LLVMOpcode', - 'LLVMOpcode__enumvalues', 'LLVMOr', 'LLVMOrcAbsoluteSymbols', - 'LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction', - 'LLVMOrcCDependenceMapPair', 'LLVMOrcCDependenceMapPairs', - 'LLVMOrcCLookupSet', 'LLVMOrcCLookupSetElement', - 'LLVMOrcCSymbolAliasMapEntry', 'LLVMOrcCSymbolAliasMapPair', - 'LLVMOrcCSymbolAliasMapPairs', 'LLVMOrcCSymbolFlagsMapPair', - 'LLVMOrcCSymbolFlagsMapPairs', 'LLVMOrcCSymbolMapPairs', - 'LLVMOrcCSymbolsList', - 'LLVMOrcCreateCustomCAPIDefinitionGenerator', - 'LLVMOrcCreateCustomMaterializationUnit', - 'LLVMOrcCreateDumpObjects', - 'LLVMOrcCreateDynamicLibrarySearchGeneratorForPath', - 'LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess', - 'LLVMOrcCreateLLJIT', 'LLVMOrcCreateLLJITBuilder', - 'LLVMOrcCreateLocalIndirectStubsManager', - 'LLVMOrcCreateLocalLazyCallThroughManager', - 'LLVMOrcCreateNewThreadSafeContext', - 'LLVMOrcCreateNewThreadSafeModule', - 'LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager', - 'LLVMOrcCreateStaticLibrarySearchGeneratorForPath', - 'LLVMOrcDefinitionGeneratorRef', 'LLVMOrcDisposeCSymbolFlagsMap', - 'LLVMOrcDisposeDefinitionGenerator', 'LLVMOrcDisposeDumpObjects', - 'LLVMOrcDisposeIndirectStubsManager', - 'LLVMOrcDisposeJITTargetMachineBuilder', 'LLVMOrcDisposeLLJIT', - 'LLVMOrcDisposeLLJITBuilder', - 'LLVMOrcDisposeLazyCallThroughManager', - 'LLVMOrcDisposeMaterializationResponsibility', - 'LLVMOrcDisposeMaterializationUnit', 'LLVMOrcDisposeObjectLayer', - 'LLVMOrcDisposeSymbols', 'LLVMOrcDisposeThreadSafeContext', - 'LLVMOrcDisposeThreadSafeModule', 'LLVMOrcDumpObjectsRef', - 'LLVMOrcDumpObjects_CallOperator', 'LLVMOrcErrorReporterFunction', - 'LLVMOrcExecutionSessionCreateBareJITDylib', - 'LLVMOrcExecutionSessionCreateJITDylib', - 'LLVMOrcExecutionSessionGetJITDylibByName', - 'LLVMOrcExecutionSessionGetSymbolStringPool', - 'LLVMOrcExecutionSessionIntern', 'LLVMOrcExecutionSessionRef', - 'LLVMOrcExecutionSessionSetErrorReporter', - 'LLVMOrcExecutorAddress', - 'LLVMOrcGenericIRModuleOperationFunction', - 'LLVMOrcIRTransformLayerEmit', 'LLVMOrcIRTransformLayerRef', - 'LLVMOrcIRTransformLayerSetTransform', - 'LLVMOrcIRTransformLayerTransformFunction', - 'LLVMOrcIndirectStubsManagerRef', 'LLVMOrcJITDylibAddGenerator', - 'LLVMOrcJITDylibClear', 'LLVMOrcJITDylibCreateResourceTracker', - 'LLVMOrcJITDylibDefine', - 'LLVMOrcJITDylibGetDefaultResourceTracker', - 'LLVMOrcJITDylibLookupFlags', - 'LLVMOrcJITDylibLookupFlagsMatchAllSymbols', - 'LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly', - 'LLVMOrcJITDylibLookupFlags__enumvalues', 'LLVMOrcJITDylibRef', - 'LLVMOrcJITTargetAddress', - 'LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine', - 'LLVMOrcJITTargetMachineBuilderDetectHost', - 'LLVMOrcJITTargetMachineBuilderGetTargetTriple', - 'LLVMOrcJITTargetMachineBuilderRef', - 'LLVMOrcJITTargetMachineBuilderSetTargetTriple', - 'LLVMOrcLLJITAddLLVMIRModule', - 'LLVMOrcLLJITAddLLVMIRModuleWithRT', 'LLVMOrcLLJITAddObjectFile', - 'LLVMOrcLLJITAddObjectFileWithRT', - 'LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction', - 'LLVMOrcLLJITBuilderRef', - 'LLVMOrcLLJITBuilderSetJITTargetMachineBuilder', - 'LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator', - 'LLVMOrcLLJITGetDataLayoutStr', 'LLVMOrcLLJITGetExecutionSession', - 'LLVMOrcLLJITGetGlobalPrefix', 'LLVMOrcLLJITGetIRTransformLayer', - 'LLVMOrcLLJITGetMainJITDylib', 'LLVMOrcLLJITGetObjLinkingLayer', - 'LLVMOrcLLJITGetObjTransformLayer', 'LLVMOrcLLJITGetTripleString', - 'LLVMOrcLLJITLookup', 'LLVMOrcLLJITMangleAndIntern', - 'LLVMOrcLLJITRef', 'LLVMOrcLazyCallThroughManagerRef', - 'LLVMOrcLazyReexports', 'LLVMOrcLookupKind', - 'LLVMOrcLookupKindDLSym', 'LLVMOrcLookupKindStatic', - 'LLVMOrcLookupKind__enumvalues', 'LLVMOrcLookupStateRef', - 'LLVMOrcMaterializationResponsibilityAddDependencies', - 'LLVMOrcMaterializationResponsibilityAddDependenciesForAll', - 'LLVMOrcMaterializationResponsibilityDefineMaterializing', - 'LLVMOrcMaterializationResponsibilityDelegate', - 'LLVMOrcMaterializationResponsibilityFailMaterialization', - 'LLVMOrcMaterializationResponsibilityGetExecutionSession', - 'LLVMOrcMaterializationResponsibilityGetInitializerSymbol', - 'LLVMOrcMaterializationResponsibilityGetRequestedSymbols', - 'LLVMOrcMaterializationResponsibilityGetSymbols', - 'LLVMOrcMaterializationResponsibilityGetTargetDylib', - 'LLVMOrcMaterializationResponsibilityNotifyEmitted', - 'LLVMOrcMaterializationResponsibilityNotifyResolved', - 'LLVMOrcMaterializationResponsibilityRef', - 'LLVMOrcMaterializationResponsibilityReplace', - 'LLVMOrcMaterializationUnitDestroyFunction', - 'LLVMOrcMaterializationUnitDiscardFunction', - 'LLVMOrcMaterializationUnitMaterializeFunction', - 'LLVMOrcMaterializationUnitRef', - 'LLVMOrcObjectLayerAddObjectFile', - 'LLVMOrcObjectLayerAddObjectFileWithRT', 'LLVMOrcObjectLayerEmit', - 'LLVMOrcObjectLayerRef', 'LLVMOrcObjectLinkingLayerRef', - 'LLVMOrcObjectTransformLayerRef', - 'LLVMOrcObjectTransformLayerSetTransform', - 'LLVMOrcObjectTransformLayerTransformFunction', - 'LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener', - 'LLVMOrcReleaseResourceTracker', - 'LLVMOrcReleaseSymbolStringPoolEntry', - 'LLVMOrcResourceTrackerRef', 'LLVMOrcResourceTrackerRemove', - 'LLVMOrcResourceTrackerTransferTo', - 'LLVMOrcRetainSymbolStringPoolEntry', 'LLVMOrcSymbolLookupFlags', - 'LLVMOrcSymbolLookupFlagsRequiredSymbol', - 'LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol', - 'LLVMOrcSymbolLookupFlags__enumvalues', 'LLVMOrcSymbolPredicate', - 'LLVMOrcSymbolStringPoolClearDeadEntries', - 'LLVMOrcSymbolStringPoolEntryRef', - 'LLVMOrcSymbolStringPoolEntryStr', 'LLVMOrcSymbolStringPoolRef', - 'LLVMOrcThreadSafeContextGetContext', - 'LLVMOrcThreadSafeContextRef', 'LLVMOrcThreadSafeModuleRef', - 'LLVMOrcThreadSafeModuleWithModuleDo', 'LLVMPHI', - 'LLVMPPCFP128Type', 'LLVMPPCFP128TypeInContext', - 'LLVMPPC_FP128TypeKind', 'LLVMPTXDeviceCallConv', - 'LLVMPTXKernelCallConv', 'LLVMParseBitcode', 'LLVMParseBitcode2', - 'LLVMParseBitcodeInContext', 'LLVMParseBitcodeInContext2', - 'LLVMParseCommandLineOptions', 'LLVMParseIRInContext', - 'LLVMPassBuilderOptionsRef', - 'LLVMPassBuilderOptionsSetCallGraphProfile', - 'LLVMPassBuilderOptionsSetDebugLogging', - 'LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll', - 'LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap', - 'LLVMPassBuilderOptionsSetLicmMssaOptCap', - 'LLVMPassBuilderOptionsSetLoopInterleaving', - 'LLVMPassBuilderOptionsSetLoopUnrolling', - 'LLVMPassBuilderOptionsSetLoopVectorization', - 'LLVMPassBuilderOptionsSetMergeFunctions', - 'LLVMPassBuilderOptionsSetSLPVectorization', - 'LLVMPassBuilderOptionsSetVerifyEach', - 'LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints', - 'LLVMPassManagerBuilderCreate', 'LLVMPassManagerBuilderDispose', - 'LLVMPassManagerBuilderPopulateFunctionPassManager', - 'LLVMPassManagerBuilderPopulateLTOPassManager', - 'LLVMPassManagerBuilderPopulateModulePassManager', - 'LLVMPassManagerBuilderRef', - 'LLVMPassManagerBuilderSetDisableSimplifyLibCalls', - 'LLVMPassManagerBuilderSetDisableUnitAtATime', - 'LLVMPassManagerBuilderSetDisableUnrollLoops', - 'LLVMPassManagerBuilderSetOptLevel', - 'LLVMPassManagerBuilderSetSizeLevel', - 'LLVMPassManagerBuilderUseInlinerWithThreshold', - 'LLVMPassManagerRef', 'LLVMPassRegistryRef', 'LLVMPointerSize', - 'LLVMPointerSizeForAS', 'LLVMPointerType', 'LLVMPointerTypeKind', - 'LLVMPoisonValueValueKind', 'LLVMPositionBuilder', - 'LLVMPositionBuilderAtEnd', 'LLVMPositionBuilderBefore', - 'LLVMPreferredAlignmentOfGlobal', 'LLVMPreferredAlignmentOfType', - 'LLVMPreserveAllCallConv', 'LLVMPreserveMostCallConv', - 'LLVMPrintMessageAction', 'LLVMPrintModuleToFile', - 'LLVMPrintModuleToString', 'LLVMPrintTypeToString', - 'LLVMPrintValueToString', 'LLVMPrivateLinkage', - 'LLVMProtectedVisibility', 'LLVMPtrToInt', 'LLVMRealOEQ', - 'LLVMRealOGE', 'LLVMRealOGT', 'LLVMRealOLE', 'LLVMRealOLT', - 'LLVMRealONE', 'LLVMRealORD', 'LLVMRealPredicate', - 'LLVMRealPredicateFalse', 'LLVMRealPredicateTrue', - 'LLVMRealPredicate__enumvalues', 'LLVMRealUEQ', 'LLVMRealUGE', - 'LLVMRealUGT', 'LLVMRealULE', 'LLVMRealULT', 'LLVMRealUNE', - 'LLVMRealUNO', 'LLVMRecompileAndRelinkFunction', - 'LLVMRelocDefault', 'LLVMRelocDynamicNoPic', 'LLVMRelocMode', - 'LLVMRelocMode__enumvalues', 'LLVMRelocPIC', 'LLVMRelocROPI', - 'LLVMRelocROPI_RWPI', 'LLVMRelocRWPI', 'LLVMRelocStatic', - 'LLVMRelocationIteratorRef', 'LLVMRemarkArgGetDebugLoc', - 'LLVMRemarkArgGetKey', 'LLVMRemarkArgGetValue', - 'LLVMRemarkArgRef', 'LLVMRemarkDebugLocGetSourceColumn', - 'LLVMRemarkDebugLocGetSourceFilePath', - 'LLVMRemarkDebugLocGetSourceLine', 'LLVMRemarkDebugLocRef', - 'LLVMRemarkEntryDispose', 'LLVMRemarkEntryGetDebugLoc', - 'LLVMRemarkEntryGetFirstArg', 'LLVMRemarkEntryGetFunctionName', - 'LLVMRemarkEntryGetHotness', 'LLVMRemarkEntryGetNextArg', - 'LLVMRemarkEntryGetNumArgs', 'LLVMRemarkEntryGetPassName', - 'LLVMRemarkEntryGetRemarkName', 'LLVMRemarkEntryGetType', - 'LLVMRemarkEntryRef', 'LLVMRemarkParserCreateBitstream', - 'LLVMRemarkParserCreateYAML', 'LLVMRemarkParserDispose', - 'LLVMRemarkParserGetErrorMessage', 'LLVMRemarkParserGetNext', - 'LLVMRemarkParserHasError', 'LLVMRemarkParserRef', - 'LLVMRemarkStringGetData', 'LLVMRemarkStringGetLen', - 'LLVMRemarkStringRef', 'LLVMRemarkType', 'LLVMRemarkTypeAnalysis', - 'LLVMRemarkTypeAnalysisAliasing', - 'LLVMRemarkTypeAnalysisFPCommute', 'LLVMRemarkTypeFailure', - 'LLVMRemarkTypeMissed', 'LLVMRemarkTypePassed', - 'LLVMRemarkTypeUnknown', 'LLVMRemarkVersion', - 'LLVMRemoveBasicBlockFromParent', - 'LLVMRemoveCallSiteEnumAttribute', - 'LLVMRemoveCallSiteStringAttribute', - 'LLVMRemoveEnumAttributeAtIndex', 'LLVMRemoveGlobalIFunc', - 'LLVMRemoveModule', 'LLVMRemoveStringAttributeAtIndex', - 'LLVMReplaceAllUsesWith', 'LLVMResetFatalErrorHandler', - 'LLVMResume', 'LLVMRet', 'LLVMReturnStatusAction', - 'LLVMRunFunction', 'LLVMRunFunctionAsMain', - 'LLVMRunFunctionPassManager', 'LLVMRunPassManager', - 'LLVMRunPasses', 'LLVMRunStaticConstructors', - 'LLVMRunStaticDestructors', 'LLVMSDiv', 'LLVMSExt', 'LLVMSIToFP', - 'LLVMSPIRFUNCCallConv', 'LLVMSPIRKERNELCallConv', 'LLVMSRem', - 'LLVMSameSizeComdatSelectionKind', 'LLVMScalableVectorType', - 'LLVMScalableVectorTypeKind', 'LLVMSearchForAddressOfSymbol', - 'LLVMSectionIteratorRef', 'LLVMSelect', 'LLVMSetAlignment', - 'LLVMSetArgOperand', 'LLVMSetAtomicRMWBinOp', - 'LLVMSetAtomicSingleThread', 'LLVMSetCleanup', - 'LLVMSetCmpXchgFailureOrdering', 'LLVMSetCmpXchgSuccessOrdering', - 'LLVMSetComdat', 'LLVMSetComdatSelectionKind', 'LLVMSetCondition', - 'LLVMSetCurrentDebugLocation', 'LLVMSetCurrentDebugLocation2', - 'LLVMSetDLLStorageClass', 'LLVMSetDataLayout', - 'LLVMSetDisasmOptions', 'LLVMSetExternallyInitialized', - 'LLVMSetFunctionCallConv', 'LLVMSetGC', 'LLVMSetGlobalConstant', - 'LLVMSetGlobalIFuncResolver', 'LLVMSetInitializer', - 'LLVMSetInstDebugLocation', 'LLVMSetInstrParamAlignment', - 'LLVMSetInstructionCallConv', 'LLVMSetIsInBounds', - 'LLVMSetLinkage', 'LLVMSetMetadata', 'LLVMSetModuleDataLayout', - 'LLVMSetModuleIdentifier', 'LLVMSetModuleInlineAsm', - 'LLVMSetModuleInlineAsm2', 'LLVMSetNormalDest', 'LLVMSetOperand', - 'LLVMSetOrdering', 'LLVMSetParamAlignment', - 'LLVMSetParentCatchSwitch', 'LLVMSetPersonalityFn', - 'LLVMSetSection', 'LLVMSetSourceFileName', 'LLVMSetSubprogram', - 'LLVMSetSuccessor', 'LLVMSetTailCall', 'LLVMSetTarget', - 'LLVMSetTargetMachineAsmVerbosity', 'LLVMSetThreadLocal', - 'LLVMSetThreadLocalMode', 'LLVMSetUnnamedAddr', - 'LLVMSetUnnamedAddress', 'LLVMSetUnwindDest', 'LLVMSetValueName', - 'LLVMSetValueName2', 'LLVMSetVisibility', 'LLVMSetVolatile', - 'LLVMSetWeak', 'LLVMShl', 'LLVMShuffleVector', 'LLVMShutdown', - 'LLVMSizeOf', 'LLVMSizeOfTypeInBits', 'LLVMStartMultithreaded', - 'LLVMStopMultithreaded', 'LLVMStore', 'LLVMStoreSizeOfType', - 'LLVMStripModuleDebugInfo', 'LLVMStructCreateNamed', - 'LLVMStructGetTypeAtIndex', 'LLVMStructSetBody', 'LLVMStructType', - 'LLVMStructTypeInContext', 'LLVMStructTypeKind', 'LLVMSub', - 'LLVMSwiftCallConv', 'LLVMSwitch', 'LLVMSymbolIteratorRef', - 'LLVMSymbolLookupCallback', 'LLVMTargetDataRef', - 'LLVMTargetHasAsmBackend', 'LLVMTargetHasJIT', - 'LLVMTargetHasTargetMachine', 'LLVMTargetLibraryInfoRef', - 'LLVMTargetMachineEmitToFile', - 'LLVMTargetMachineEmitToMemoryBuffer', 'LLVMTargetMachineRef', - 'LLVMTargetRef', 'LLVMTemporaryMDNode', 'LLVMThreadLocalMode', - 'LLVMThreadLocalMode__enumvalues', 'LLVMTokenTypeInContext', - 'LLVMTokenTypeKind', 'LLVMTrunc', 'LLVMTypeIsSized', - 'LLVMTypeKind', 'LLVMTypeKind__enumvalues', 'LLVMTypeOf', - 'LLVMTypeRef', 'LLVMUDiv', 'LLVMUIToFP', 'LLVMURem', - 'LLVMUndefValueValueKind', 'LLVMUnnamedAddr', - 'LLVMUnnamedAddr__enumvalues', 'LLVMUnreachable', 'LLVMUseRef', - 'LLVMUserOp1', 'LLVMUserOp2', 'LLVMVAArg', - 'LLVMValueAsBasicBlock', 'LLVMValueAsMetadata', - 'LLVMValueIsBasicBlock', 'LLVMValueKind', - 'LLVMValueKind__enumvalues', 'LLVMValueMetadataEntriesGetKind', - 'LLVMValueMetadataEntriesGetMetadata', 'LLVMValueMetadataEntry', - 'LLVMValueRef', 'LLVMVectorType', 'LLVMVectorTypeKind', - 'LLVMVerifierFailureAction', - 'LLVMVerifierFailureAction__enumvalues', 'LLVMVerifyFunction', - 'LLVMVerifyModule', 'LLVMViewFunctionCFG', - 'LLVMViewFunctionCFGOnly', 'LLVMVisibility', - 'LLVMVisibility__enumvalues', 'LLVMVoidType', - 'LLVMVoidTypeInContext', 'LLVMVoidTypeKind', 'LLVMWeakAnyLinkage', - 'LLVMWeakODRLinkage', 'LLVMWebKitJSCallConv', 'LLVMWin64CallConv', - 'LLVMWriteBitcodeToFD', 'LLVMWriteBitcodeToFile', - 'LLVMWriteBitcodeToFileHandle', 'LLVMWriteBitcodeToMemoryBuffer', - 'LLVMX8664SysVCallConv', 'LLVMX86AMXType', - 'LLVMX86AMXTypeInContext', 'LLVMX86FP80Type', - 'LLVMX86FP80TypeInContext', 'LLVMX86FastcallCallConv', - 'LLVMX86INTRCallConv', 'LLVMX86MMXType', - 'LLVMX86MMXTypeInContext', 'LLVMX86RegCallCallConv', - 'LLVMX86StdcallCallConv', 'LLVMX86ThisCallCallConv', - 'LLVMX86VectorCallCallConv', 'LLVMX86_AMXTypeKind', - 'LLVMX86_FP80TypeKind', 'LLVMX86_MMXTypeKind', 'LLVMXor', - 'LLVMYieldCallback', 'LLVMZExt', 'LLVM_C_ANALYSIS_H', - 'LLVM_C_BITREADER_H', 'LLVM_C_BITWRITER_H', 'LLVM_C_COMDAT_H', - 'LLVM_C_CORE_H', 'LLVM_C_DATATYPES_H', 'LLVM_C_DEBUGINFO_H', - 'LLVM_C_DEPRECATED_H', 'LLVM_C_DISASSEMBLERTYPES_H', - 'LLVM_C_DISASSEMBLER_H', 'LLVM_C_ERRORHANDLING_H', - 'LLVM_C_ERROR_H', 'LLVM_C_EXECUTIONENGINE_H', 'LLVM_C_EXTERNC_H', - 'LLVM_C_INITIALIZATION_H', 'LLVM_C_IRREADER_H', 'LLVM_C_LINKER_H', - 'LLVM_C_LLJIT_H', 'LLVM_C_LTO_H', 'LLVM_C_OBJECT_H', - 'LLVM_C_ORCEE_H', 'LLVM_C_ORC_H', 'LLVM_C_REMARKS_H', - 'LLVM_C_SUPPORT_H', 'LLVM_C_TARGETMACHINE_H', 'LLVM_C_TARGET_H', - 'LLVM_C_TRANSFORMS_AGGRESSIVEINSTCOMBINE_H', - 'LLVM_C_TRANSFORMS_COROUTINES_H', - 'LLVM_C_TRANSFORMS_INSTCOMBINE_H', 'LLVM_C_TRANSFORMS_IPO_H', - 'LLVM_C_TRANSFORMS_PASSBUILDER_H', - 'LLVM_C_TRANSFORMS_PASSMANAGERBUILDER_H', - 'LLVM_C_TRANSFORMS_SCALAR_H', 'LLVM_C_TRANSFORMS_UTILS_H', - 'LLVM_C_TRANSFORMS_VECTORIZE_H', 'LLVM_C_TYPES_H', - 'LTOObjectBuffer', 'LTO_API_VERSION', - 'LTO_CODEGEN_PIC_MODEL_DEFAULT', 'LTO_CODEGEN_PIC_MODEL_DYNAMIC', - 'LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC', - 'LTO_CODEGEN_PIC_MODEL_STATIC', 'LTO_DEBUG_MODEL_DWARF', - 'LTO_DEBUG_MODEL_NONE', 'LTO_DS_ERROR', 'LTO_DS_NOTE', - 'LTO_DS_REMARK', 'LTO_DS_WARNING', 'LTO_SYMBOL_ALIAS', - 'LTO_SYMBOL_ALIGNMENT_MASK', 'LTO_SYMBOL_COMDAT', - 'LTO_SYMBOL_DEFINITION_MASK', 'LTO_SYMBOL_DEFINITION_REGULAR', - 'LTO_SYMBOL_DEFINITION_TENTATIVE', - 'LTO_SYMBOL_DEFINITION_UNDEFINED', 'LTO_SYMBOL_DEFINITION_WEAK', - 'LTO_SYMBOL_DEFINITION_WEAKUNDEF', 'LTO_SYMBOL_PERMISSIONS_CODE', - 'LTO_SYMBOL_PERMISSIONS_DATA', 'LTO_SYMBOL_PERMISSIONS_MASK', - 'LTO_SYMBOL_PERMISSIONS_RODATA', 'LTO_SYMBOL_SCOPE_DEFAULT', - 'LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN', - 'LTO_SYMBOL_SCOPE_HIDDEN', 'LTO_SYMBOL_SCOPE_INTERNAL', - 'LTO_SYMBOL_SCOPE_MASK', 'LTO_SYMBOL_SCOPE_PROTECTED', - 'REMARKS_API_VERSION', 'c__EA_LLVMAtomicOrdering', - 'c__EA_LLVMAtomicRMWBinOp', 'c__EA_LLVMBinaryType', - 'c__EA_LLVMCallConv', 'c__EA_LLVMCodeGenFileType', - 'c__EA_LLVMCodeGenOptLevel', 'c__EA_LLVMCodeModel', - 'c__EA_LLVMComdatSelectionKind', 'c__EA_LLVMDIFlags', - 'c__EA_LLVMDLLStorageClass', 'c__EA_LLVMDWARFEmissionKind', - 'c__EA_LLVMDWARFMacinfoRecordType', - 'c__EA_LLVMDWARFSourceLanguage', 'c__EA_LLVMDiagnosticSeverity', - 'c__EA_LLVMInlineAsmDialect', 'c__EA_LLVMIntPredicate', - 'c__EA_LLVMJITSymbolGenericFlags', 'c__EA_LLVMLandingPadClauseTy', - 'c__EA_LLVMLinkage', 'c__EA_LLVMLinkerMode', - 'c__EA_LLVMModuleFlagBehavior', 'c__EA_LLVMOpcode', - 'c__EA_LLVMOrcJITDylibLookupFlags', 'c__EA_LLVMOrcLookupKind', - 'c__EA_LLVMOrcSymbolLookupFlags', 'c__EA_LLVMRealPredicate', - 'c__EA_LLVMRelocMode', 'c__EA_LLVMThreadLocalMode', - 'c__EA_LLVMTypeKind', 'c__EA_LLVMUnnamedAddr', - 'c__EA_LLVMValueKind', 'c__EA_LLVMVerifierFailureAction', - 'c__EA_LLVMVisibility', 'c__EA_lto_codegen_diagnostic_severity_t', - 'c__EA_lto_codegen_model', 'c__EA_lto_debug_model', - 'c__EA_lto_symbol_attributes', 'c__Ea_LLVMAttributeReturnIndex', - 'c__Ea_LLVMMDStringMetadataKind', 'int64_t', 'lto_api_version', - 'lto_bool_t', 'lto_code_gen_t', 'lto_codegen_add_module', - 'lto_codegen_add_must_preserve_symbol', 'lto_codegen_compile', - 'lto_codegen_compile_optimized', 'lto_codegen_compile_to_file', - 'lto_codegen_create', 'lto_codegen_create_in_local_context', - 'lto_codegen_debug_options', 'lto_codegen_debug_options_array', - 'lto_codegen_diagnostic_severity_t', - 'lto_codegen_diagnostic_severity_t__enumvalues', - 'lto_codegen_dispose', 'lto_codegen_model', - 'lto_codegen_model__enumvalues', 'lto_codegen_optimize', - 'lto_codegen_set_assembler_args', - 'lto_codegen_set_assembler_path', 'lto_codegen_set_cpu', - 'lto_codegen_set_debug_model', - 'lto_codegen_set_diagnostic_handler', 'lto_codegen_set_module', - 'lto_codegen_set_pic_model', - 'lto_codegen_set_should_embed_uselists', - 'lto_codegen_set_should_internalize', - 'lto_codegen_write_merged_modules', 'lto_debug_model', - 'lto_debug_model__enumvalues', 'lto_diagnostic_handler_t', - 'lto_get_error_message', 'lto_get_version', - 'lto_initialize_disassembler', 'lto_input_create', - 'lto_input_dispose', 'lto_input_get_dependent_library', - 'lto_input_get_num_dependent_libraries', 'lto_input_t', - 'lto_module_create', 'lto_module_create_from_fd', - 'lto_module_create_from_fd_at_offset', - 'lto_module_create_from_memory', - 'lto_module_create_from_memory_with_path', - 'lto_module_create_in_codegen_context', - 'lto_module_create_in_local_context', 'lto_module_dispose', - 'lto_module_get_linkeropts', 'lto_module_get_macho_cputype', - 'lto_module_get_num_symbols', 'lto_module_get_symbol_attribute', - 'lto_module_get_symbol_name', 'lto_module_get_target_triple', - 'lto_module_has_ctor_dtor', 'lto_module_has_objc_category', - 'lto_module_is_object_file', - 'lto_module_is_object_file_for_target', - 'lto_module_is_object_file_in_memory', - 'lto_module_is_object_file_in_memory_for_target', - 'lto_module_is_thinlto', 'lto_module_set_target_triple', - 'lto_module_t', 'lto_runtime_lib_symbols_list', - 'lto_set_debug_options', 'lto_symbol_attributes', - 'lto_symbol_attributes__enumvalues', 'off_t', 'size_t', - 'struct_LLVMComdat', 'struct_LLVMMCJITCompilerOptions', - 'struct_LLVMOpInfo1', 'struct_LLVMOpInfoSymbol1', - 'struct_LLVMOpaqueAttributeRef', 'struct_LLVMOpaqueBasicBlock', - 'struct_LLVMOpaqueBinary', 'struct_LLVMOpaqueBuilder', - 'struct_LLVMOpaqueContext', 'struct_LLVMOpaqueDIBuilder', - 'struct_LLVMOpaqueDiagnosticInfo', 'struct_LLVMOpaqueError', - 'struct_LLVMOpaqueExecutionEngine', - 'struct_LLVMOpaqueGenericValue', - 'struct_LLVMOpaqueJITEventListener', - 'struct_LLVMOpaqueLTOCodeGenerator', 'struct_LLVMOpaqueLTOInput', - 'struct_LLVMOpaqueLTOModule', - 'struct_LLVMOpaqueMCJITMemoryManager', - 'struct_LLVMOpaqueMemoryBuffer', 'struct_LLVMOpaqueMetadata', - 'struct_LLVMOpaqueModule', 'struct_LLVMOpaqueModuleFlagEntry', - 'struct_LLVMOpaqueModuleProvider', 'struct_LLVMOpaqueNamedMDNode', - 'struct_LLVMOpaqueObjectFile', - 'struct_LLVMOpaquePassBuilderOptions', - 'struct_LLVMOpaquePassManager', - 'struct_LLVMOpaquePassManagerBuilder', - 'struct_LLVMOpaquePassRegistry', - 'struct_LLVMOpaqueRelocationIterator', - 'struct_LLVMOpaqueSectionIterator', - 'struct_LLVMOpaqueSymbolIterator', 'struct_LLVMOpaqueTargetData', - 'struct_LLVMOpaqueTargetLibraryInfotData', - 'struct_LLVMOpaqueTargetMachine', - 'struct_LLVMOpaqueThinLTOCodeGenerator', 'struct_LLVMOpaqueType', - 'struct_LLVMOpaqueUse', 'struct_LLVMOpaqueValue', - 'struct_LLVMOpaqueValueMetadataEntry', - 'struct_LLVMOrcOpaqueDefinitionGenerator', - 'struct_LLVMOrcOpaqueDumpObjects', - 'struct_LLVMOrcOpaqueExecutionSession', - 'struct_LLVMOrcOpaqueIRTransformLayer', - 'struct_LLVMOrcOpaqueIndirectStubsManager', - 'struct_LLVMOrcOpaqueJITDylib', - 'struct_LLVMOrcOpaqueJITTargetMachineBuilder', - 'struct_LLVMOrcOpaqueLLJIT', 'struct_LLVMOrcOpaqueLLJITBuilder', - 'struct_LLVMOrcOpaqueLazyCallThroughManager', - 'struct_LLVMOrcOpaqueLookupState', - 'struct_LLVMOrcOpaqueMaterializationResponsibility', - 'struct_LLVMOrcOpaqueMaterializationUnit', - 'struct_LLVMOrcOpaqueObjectLayer', - 'struct_LLVMOrcOpaqueObjectLinkingLayer', - 'struct_LLVMOrcOpaqueObjectTransformLayer', - 'struct_LLVMOrcOpaqueResourceTracker', - 'struct_LLVMOrcOpaqueSymbolStringPool', - 'struct_LLVMOrcOpaqueSymbolStringPoolEntry', - 'struct_LLVMOrcOpaqueThreadSafeContext', - 'struct_LLVMOrcOpaqueThreadSafeModule', - 'struct_LLVMRemarkOpaqueArg', 'struct_LLVMRemarkOpaqueDebugLoc', - 'struct_LLVMRemarkOpaqueEntry', 'struct_LLVMRemarkOpaqueParser', - 'struct_LLVMRemarkOpaqueString', 'struct_LLVMTarget', - 'struct_c__SA_LLVMJITCSymbolMapPair', - 'struct_c__SA_LLVMJITEvaluatedSymbol', - 'struct_c__SA_LLVMJITSymbolFlags', - 'struct_c__SA_LLVMOrcCDependenceMapPair', - 'struct_c__SA_LLVMOrcCLookupSetElement', - 'struct_c__SA_LLVMOrcCSymbolAliasMapEntry', - 'struct_c__SA_LLVMOrcCSymbolAliasMapPair', - 'struct_c__SA_LLVMOrcCSymbolFlagsMapPair', - 'struct_c__SA_LLVMOrcCSymbolsList', - 'struct_c__SA_LTOObjectBuffer', 'thinlto_code_gen_t', - 'thinlto_codegen_add_cross_referenced_symbol', - 'thinlto_codegen_add_module', - 'thinlto_codegen_add_must_preserve_symbol', - 'thinlto_codegen_disable_codegen', 'thinlto_codegen_dispose', - 'thinlto_codegen_process', 'thinlto_codegen_set_cache_dir', - 'thinlto_codegen_set_cache_entry_expiration', - 'thinlto_codegen_set_cache_pruning_interval', - 'thinlto_codegen_set_cache_size_bytes', - 'thinlto_codegen_set_cache_size_files', - 'thinlto_codegen_set_cache_size_megabytes', - 'thinlto_codegen_set_codegen_only', 'thinlto_codegen_set_cpu', - 'thinlto_codegen_set_final_cache_size_relative_to_available_space', - 'thinlto_codegen_set_pic_model', - 'thinlto_codegen_set_savetemps_dir', 'thinlto_create_codegen', - 'thinlto_debug_options', 'thinlto_module_get_num_object_files', - 'thinlto_module_get_num_objects', 'thinlto_module_get_object', - 'thinlto_module_get_object_file', - 'thinlto_set_generated_objects_dir', 'uint32_t', 'uint64_t', - 'uint8_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/nv_gpu.py b/tinygrad/tinygrad/runtime/autogen/nv_gpu.py deleted file mode 100644 index 32c01d4b..00000000 --- a/tinygrad/tinygrad/runtime/autogen/nv_gpu.py +++ /dev/null @@ -1,38561 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', '/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/nvtypes.h', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/nvidia-uvm', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/arch/nvalloc/unix/include', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/ctrl'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -__CLC6C0QMD_H__ = True # macro -NVC6C0_QMDV02_03_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV02_03_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV02_03_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV02_03_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV02_03_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV02_03_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138 , 138) # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139 , 139) # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141 , 141) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142 , 142) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143 , 143) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_B = (159 , 144) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_C = (185 , 185) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366 , 366) # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV02_03_QMD_RESERVED13A = (447 , 432) # macro -NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV02_03_QMD_RESERVED14A = (479 , 464) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511 , 480) # macro -NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568 , 562) # macro -NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575 , 569) # macro -NVC6C0_QMDV02_03_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_H = (591 , 584) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663 , 657) # macro -NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767 , 736) # macro -NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775 , 768) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_J = (783 , 776) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790 , 788) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_K = (791 , 791) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793 , 792) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794 , 794) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799 , 799) # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831 , 800) # macro -NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863 , 832) # macro -NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871 , 864) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_L = (879 , 872) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886 , 884) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_M = (887 , 887) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889 , 888) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890 , 890) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895 , 895) # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927 , 896) # macro -NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951 , 928) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_N = (954 , 952) # macro -NVC6C0_QMDV02_03_BARRIER_COUNT = (959 , 955) # macro -NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983 , 960) # macro -NVC6C0_QMDV02_03_REGISTER_COUNT = (991 , 984) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000 , 992) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009 , 1001) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015 , 1010) # macro -NVC6C0_QMDV02_03_SASS_VERSION = (1023 , 1016) # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599 , 1585) # macro -NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630 , 1600) # macro -NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631 , 1631) # macro -NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662 , 1632) # macro -NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663 , 1663) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693 , 1664) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694 , 1694) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695 , 1695) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727 , 1696) # macro -NVC6C0_QMDV02_03_QMD_SPARE_G = (1759 , 1728) # macro -NVC6C0_QMDV02_03_QMD_SPARE_H = (1791 , 1760) # macro -NVC6C0_QMDV02_03_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV02_03_QMD_SPARE_J = (1855 , 1824) # macro -NVC6C0_QMDV02_03_QMD_SPARE_K = (1887 , 1856) # macro -NVC6C0_QMDV02_03_QMD_SPARE_L = (1919 , 1888) # macro -NVC6C0_QMDV02_03_QMD_SPARE_M = (1951 , 1920) # macro -NVC6C0_QMDV02_03_QMD_SPARE_N = (1983 , 1952) # macro -NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047 , 2016) # macro -NVC6C0_QMDV02_04_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV02_04_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV02_04_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV02_04_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV02_04_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV02_04_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138 , 138) # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139 , 139) # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141 , 141) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144 , 142) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145 , 145) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146 , 146) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149 , 147) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150 , 150) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157 , 151) # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158 , 158) # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_B = (159 , 159) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185 , 185) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366 , 366) # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383 , 383) # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV02_04_QMD_RESERVED13A = (447 , 432) # macro -NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV02_04_QMD_RESERVED14A = (479 , 464) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511 , 480) # macro -NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568 , 562) # macro -NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575 , 569) # macro -NVC6C0_QMDV02_04_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_H = (591 , 584) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663 , 657) # macro -NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767 , 736) # macro -NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775 , 768) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_J = (783 , 776) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790 , 788) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_K = (791 , 791) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793 , 792) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794 , 794) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799 , 799) # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831 , 800) # macro -NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863 , 832) # macro -NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871 , 864) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_L = (879 , 872) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886 , 884) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_M = (887 , 887) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889 , 888) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890 , 890) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895 , 895) # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927 , 896) # macro -NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951 , 928) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_N = (954 , 952) # macro -NVC6C0_QMDV02_04_BARRIER_COUNT = (959 , 955) # macro -NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983 , 960) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_G = (991 , 984) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000 , 992) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009 , 1001) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011 , 1010) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015 , 1012) # macro -NVC6C0_QMDV02_04_SASS_VERSION = (1023 , 1016) # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599 , 1585) # macro -NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630 , 1600) # macro -NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631 , 1631) # macro -NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662 , 1632) # macro -NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663 , 1663) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693 , 1664) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694 , 1694) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695 , 1695) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727 , 1696) # macro -NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734 , 1728) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759 , 1735) # macro -NVC6C0_QMDV02_04_QMD_SPARE_H = (1791 , 1760) # macro -NVC6C0_QMDV02_04_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV02_04_QMD_SPARE_J = (1855 , 1824) # macro -NVC6C0_QMDV02_04_QMD_SPARE_K = (1887 , 1856) # macro -NVC6C0_QMDV02_04_QMD_SPARE_L = (1919 , 1888) # macro -NVC6C0_QMDV02_04_QMD_SPARE_M = (1951 , 1920) # macro -NVC6C0_QMDV02_04_QMD_SPARE_N = (1983 , 1952) # macro -NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047 , 2016) # macro -NVC6C0_QMDV03_00_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV03_00_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV03_00_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV03_00_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV03_00_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV03_00_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04A = (139 , 138) # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04B = (141 , 141) # macro -NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157 , 142) # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158 , 158) # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04C = (159 , 159) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185 , 185) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV03_00_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV03_00_QMD_RESERVED11A = (366 , 366) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED11B = (377 , 372) # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED11C = (381 , 379) # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383 , 383) # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511 , 480) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512 , 512) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515 , 513) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516 , 516) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517 , 517) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520 , 518) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521 , 521) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567 , 562) # macro -NVC6C0_QMDV03_00_QMD_RESERVED17A = (568 , 568) # macro -NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574 , 569) # macro -NVC6C0_QMDV03_00_QMD_RESERVED17B = (575 , 575) # macro -NVC6C0_QMDV03_00_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662 , 657) # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663 , 663) # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759 , 736) # macro -NVC6C0_QMDV03_00_BARRIER_COUNT = (767 , 763) # macro -NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799 , 768) # macro -NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807 , 800) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818 , 808) # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819 , 819) # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822 , 820) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823 , 823) # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825 , 824) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826 , 826) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828 , 827) # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829 , 829) # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831 , 830) # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863 , 832) # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895 , 864) # macro -NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927 , 896) # macro -NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935 , 928) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946 , 936) # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947 , 947) # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950 , 948) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951 , 951) # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953 , 952) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954 , 954) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956 , 955) # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957 , 957) # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959 , 958) # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991 , 960) # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023 , 992) # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623 , 1600) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640 , 1632) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649 , 1641) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651 , 1650) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVC6C0_QMDV03_00_SASS_VERSION = (1663 , 1656) # macro -NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695 , 1664) # macro -NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703 , 1696) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714 , 1704) # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715 , 1715) # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718 , 1716) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719 , 1719) # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721 , 1720) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722 , 1722) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724 , 1723) # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725 , 1725) # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727 , 1726) # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759 , 1728) # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791 , 1760) # macro -NVC6C0_QMDV03_00_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854 , 1824) # macro -NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855 , 1855) # macro -NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886 , 1856) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917 , 1888) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919 , 1919) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951 , 1920) # macro -NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958 , 1952) # macro -NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047 , 2016) # macro -__CLCEC0QMD_H__ = True # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29 , 0) # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30 , 30) # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31 , 31) # macro -NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63 , 32) # macro -NVCEC0_QMDV05_00_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV05_00_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV05_00_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143 , 128) # macro -NVCEC0_QMDV05_00_QMD_GROUP_ID = (149 , 144) # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150 , 150) # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_QMD_TYPE = (153 , 151) # macro -NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157 , 154) # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158 , 158) # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159 , 159) # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207 , 192) # macro -NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210 , 208) # macro -NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218 , 211) # macro -NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255 , 224) # macro -NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271 , 256) # macro -NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287 , 272) # macro -def NVCEC0_QMDV05_00_RELEASE_ENABLE(i): # macro - return ((288+(i)*16) , (288+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE(i): # macro - return ((290+(i)*16) , (289+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE(i): # macro - return ((291+(i)*16) , (291+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE(i): # macro - return ((292+(i)*16) , (292+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP(i): # macro - return ((295+(i)*16) , (293+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT(i): # macro - return ((297+(i)*16) , (296+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE(i): # macro - return ((299+(i)*16) , (298+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B(i): # macro - return ((300+(i)*16) , (300+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO(i): # macro - return ((303+(i)*16) , (301+(i)*16)) -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336 , 336) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339 , 337) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340 , 340) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341 , 341) # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342 , 342) # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343 , 343) # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344 , 344) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347 , 345) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348 , 348) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349 , 349) # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350 , 350) # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351 , 351) # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CORRELATION_ID = (383 , 352) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415 , 384) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447 , 416) # macro -NVCEC0_QMDV05_00_SASS_VERSION = (455 , 448) # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456 , 456) # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX = (457 , 457) # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463 , 458) # macro -NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467 , 464) # macro -NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471 , 468) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472 , 472) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473 , 473) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474 , 474) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475 , 475) # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476 , 476) # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477 , 477) # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478 , 478) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479 , 479) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511 , 480) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536 , 512) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575 , 544) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607 , 576) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615 , 608) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621 , 616) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622 , 622) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623 , 623) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625 , 624) # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626 , 626) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627 , 627) # macro -NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635 , 628) # macro -NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637 , 636) # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638 , 638) # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639 , 639) # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671 , 640) # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703 , 672) # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721 , 714) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729 , 722) # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730 , 730) # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731 , 731) # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732 , 732) # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733 , 733) # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734 , 734) # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735 , 735) # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743 , 736) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751 , 744) # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759 , 752) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767 , 760) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799 , 768) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824 , 800) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863 , 832) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895 , 864) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927 , 896) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952 , 928) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991 , 960) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023 , 992) # macro -NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055 , 1024) # macro -NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076 , 1056) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085 , 1077) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087 , 1086) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103 , 1088) # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119 , 1104) # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127 , 1120) # macro -NVCEC0_QMDV05_00_REGISTER_COUNT = (1136 , 1128) # macro -NVCEC0_QMDV05_00_BARRIER_COUNT = (1141 , 1137) # macro -NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147 , 1142) # macro -NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162 , 1152) # macro -NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168 , 1163) # macro -NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174 , 1169) # macro -NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180 , 1175) # macro -NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181 , 1181) # macro -NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199 , 1184) # macro -NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215 , 1200) # macro -NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223 , 1216) # macro -NVCEC0_QMDV05_00_GRID_WIDTH = (1279 , 1248) # macro -NVCEC0_QMDV05_00_GRID_HEIGHT = (1295 , 1280) # macro -NVCEC0_QMDV05_00_GRID_DEPTH = (1327 , 1312) # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i): # macro - return ((1375+(i)*64) , (1344+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i): # macro - return ((1394+(i)*64) , (1376+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1407+(i)*64) , (1395+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID(i): # macro - return ((1856+(i)*4) , (1856+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH(i): # macro - return ((1858+(i)*4) , (1857+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1859+(i)*4) , (1859+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919 , 1888) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936 , 1920) # macro -NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053 , 2048) # macro -NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061 , 2056) # macro -NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069 , 2064) # macro -NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075 , 2072) # macro -NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079 , 2076) # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111 , 2111) # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # macro -NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127 , 2112) # macro -NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143 , 2128) # macro -NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159 , 2144) # macro -NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207 , 2176) # macro -NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239 , 2208) # macro -def NVCEC0_QMDV05_00_TPC_DISABLE_MASK(i): # macro - return ((2271+(i)*32) , (2240+(i)*32)) -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527 , 2496) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543 , 2528) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559 , 2544) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563 , 2560) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567 , 2564) # macro -NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596 , 2592) # macro -NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654 , 2624) # macro -NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686 , 2656) # macro -NVCEC0_QMDV05_00_OUTER_PUT = (3038 , 3008) # macro -NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039 , 3039) # macro -NVCEC0_QMDV05_00_OUTER_GET = (3070 , 3040) # macro -NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071 , 3071) # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE(i): # macro - return ((336+(i)*8) , (336+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION(i): # macro - return ((339+(i)*8) , (337+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH(i): # macro - return ((340+(i)*8) , (340+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER(i): # macro - return ((415+(i)*32) , (384+(i)*32)) -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29 , 0) # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30 , 30) # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31 , 31) # macro -NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63 , 32) # macro -NVCEC0_QMDV05_01_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV05_01_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV05_01_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143 , 128) # macro -NVCEC0_QMDV05_01_QMD_GROUP_ID = (149 , 144) # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150 , 150) # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_QMD_TYPE = (153 , 151) # macro -NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157 , 154) # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158 , 158) # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159 , 159) # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207 , 192) # macro -NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210 , 208) # macro -NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218 , 211) # macro -NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255 , 224) # macro -NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271 , 256) # macro -NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287 , 272) # macro -def NVCEC0_QMDV05_01_RELEASE_ENABLE(i): # macro - return ((288+(i)*16) , (288+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE(i): # macro - return ((290+(i)*16) , (289+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE(i): # macro - return ((291+(i)*16) , (291+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE(i): # macro - return ((292+(i)*16) , (292+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP(i): # macro - return ((295+(i)*16) , (293+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT(i): # macro - return ((297+(i)*16) , (296+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE(i): # macro - return ((299+(i)*16) , (298+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B(i): # macro - return ((300+(i)*16) , (300+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO(i): # macro - return ((303+(i)*16) , (301+(i)*16)) -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336 , 336) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339 , 337) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340 , 340) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341 , 341) # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342 , 342) # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343 , 343) # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344 , 344) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347 , 345) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348 , 348) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349 , 349) # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350 , 350) # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351 , 351) # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CORRELATION_ID = (383 , 352) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415 , 384) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447 , 416) # macro -NVCEC0_QMDV05_01_SASS_VERSION = (455 , 448) # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456 , 456) # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX = (457 , 457) # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463 , 458) # macro -NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467 , 464) # macro -NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471 , 468) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472 , 472) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473 , 473) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474 , 474) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475 , 475) # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476 , 476) # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477 , 477) # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478 , 478) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479 , 479) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511 , 480) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536 , 512) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575 , 544) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607 , 576) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615 , 608) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621 , 616) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622 , 622) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623 , 623) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625 , 624) # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626 , 626) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627 , 627) # macro -NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635 , 628) # macro -NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637 , 636) # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638 , 638) # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639 , 639) # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671 , 640) # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703 , 672) # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721 , 714) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729 , 722) # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730 , 730) # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731 , 731) # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732 , 732) # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733 , 733) # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734 , 734) # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735 , 735) # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743 , 736) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751 , 744) # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759 , 752) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767 , 760) # macro -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4(i): # macro - return ((799+(i)*416) , (768+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4(i): # macro - return ((820+(i)*416) , (800+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE(i): # macro - return ((829+(i)*416) , (821+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE(i): # macro - return ((831+(i)*416) , (830+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0(i): # macro - return ((847+(i)*416) , (832+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1(i): # macro - return ((863+(i)*416) , (848+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2(i): # macro - return ((871+(i)*416) , (864+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT(i): # macro - return ((880+(i)*416) , (872+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT(i): # macro - return ((885+(i)*416) , (881+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID(i): # macro - return ((886+(i)*416) , (886+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH(i): # macro - return ((888+(i)*416) , (887+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE(i): # macro - return ((889+(i)*416) , (889+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE(i): # macro - return ((895+(i)*416) , (890+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7(i): # macro - return ((906+(i)*416) , (896+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((912+(i)*416) , (907+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((918+(i)*416) , (913+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((924+(i)*416) , (919+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE(i): # macro - return ((925+(i)*416) , (925+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4(i): # macro - return ((943+(i)*416) , (928+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4(i): # macro - return ((959+(i)*416) , (944+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6(i): # macro - return ((991+(i)*416) , (960+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6(i): # macro - return ((1010+(i)*416) , (992+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4(i): # macro - return ((1023+(i)*416) , (1011+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6(i): # macro - return ((1055+(i)*416) , (1024+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6(i): # macro - return ((1074+(i)*416) , (1056+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*416) , (1075+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID(i): # macro - return ((1088+(i)*416) , (1088+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH(i): # macro - return ((1090+(i)*416) , (1089+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE(i): # macro - return ((1091+(i)*416) , (1091+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT(i): # macro - return ((1099+(i)*416) , (1092+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH(i): # macro - return ((1151+(i)*416) , (1120+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT(i): # macro - return ((1167+(i)*416) , (1152+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH(i): # macro - return ((1183+(i)*416) , (1168+(i)*416)) -def NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE(i): # macro - return ((336+(i)*8) , (336+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION(i): # macro - return ((339+(i)*8) , (337+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH(i): # macro - return ((340+(i)*8) , (340+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER(i): # macro - return ((415+(i)*32) , (384+(i)*32)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID(i, j): # macro -# return MW((886+(i)*416+(j)*202):(886+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH(i, j): # macro -# return MW((888+(i)*416+(j)*202):(887+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE(i, j): # macro -# return MW((889+(i)*416+(j)*202):(889+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6(i, j): # macro -# return MW((991+(i)*416+(j)*64):(960+(i)*416+(j)*64)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6(i, j): # macro -# return MW((1010+(i)*416+(j)*64):(992+(i)*416+(j)*64)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4(i, j): # macro -# return MW((1023+(i)*416+(j)*64):(1011+(i)*416+(j)*64)) -NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15 , 0) # macro -NVCEC0_QMDV04_01_QMD_GROUP_ID = (21 , 16) # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22 , 22) # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_QMD_TYPE = (25 , 23) # macro -NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28 , 28) # macro -NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29 , 29) # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30 , 30) # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31 , 31) # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56 , 32) # macro -NVCEC0_QMDV04_01_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV04_01_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV04_01_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190 , 160) # macro -NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222 , 192) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253 , 224) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254 , 254) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287 , 256) # macro -NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303 , 288) # macro -NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304 , 304) # macro -def NVCEC0_QMDV04_01_RELEASE_ENABLE(i): # macro - return ((320+(i)*16) , (320+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE(i): # macro - return ((322+(i)*16) , (321+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE(i): # macro - return ((323+(i)*16) , (323+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE(i): # macro - return ((324+(i)*16) , (324+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP(i): # macro - return ((327+(i)*16) , (325+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT(i): # macro - return ((329+(i)*16) , (328+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE(i): # macro - return ((331+(i)*16) , (330+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B(i): # macro - return ((332+(i)*16) , (332+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO(i): # macro - return ((335+(i)*16) , (333+(i)*16)) -def NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE(i): # macro - return ((368+(i)*5) , (368+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION(i): # macro - return ((371+(i)*5) , (369+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH(i): # macro - return ((372+(i)*5) , (372+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378 , 378) # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379 , 379) # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380 , 380) # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381 , 381) # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382 , 382) # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CORRELATION_ID = (415 , 384) # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID(i): # macro - return ((416+(i)*4) , (416+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH(i): # macro - return ((418+(i)*4) , (417+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((419+(i)*4) , (419+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479 , 448) # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511 , 480) # macro -NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535 , 512) # macro -NVCEC0_QMDV04_01_SASS_VERSION = (543 , 536) # macro -NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567 , 544) # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568 , 568) # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX = (569 , 569) # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575 , 570) # macro -NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579 , 576) # macro -NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583 , 580) # macro -NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601 , 584) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602 , 602) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603 , 603) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604 , 604) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605 , 605) # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606 , 606) # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607 , 607) # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613 , 608) # macro -NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619 , 614) # macro -NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625 , 620) # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626 , 626) # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671 , 640) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696 , 672) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735 , 704) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767 , 736) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799 , 768) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824 , 800) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863 , 832) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895 , 864) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927 , 896) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952 , 928) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991 , 960) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023 , 992) # macro -NVCEC0_QMDV04_01_GRID_WIDTH = (1055 , 1024) # macro -NVCEC0_QMDV04_01_GRID_HEIGHT = (1071 , 1056) # macro -NVCEC0_QMDV04_01_GRID_DEPTH = (1103 , 1088) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127 , 1120) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133 , 1128) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134 , 1134) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135 , 1135) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137 , 1136) # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138 , 1138) # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139 , 1139) # macro -NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147 , 1140) # macro -NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149 , 1148) # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150 , 1150) # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151 , 1151) # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167 , 1152) # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183 , 1168) # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191 , 1184) # macro -NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199 , 1192) # macro -NVCEC0_QMDV04_01_REGISTER_COUNT = (1208 , 1200) # macro -NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210 , 1210) # macro -NVCEC0_QMDV04_01_BARRIER_COUNT = (1215 , 1211) # macro -NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247 , 1216) # macro -NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272 , 1248) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287 , 1280) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295 , 1288) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303 , 1296) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311 , 1304) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319 , 1312) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327 , 1320) # macro -NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333 , 1328) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375 , 1344) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392 , 1376) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401 , 1393) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403 , 1402) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406 , 1406) # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407 , 1407) # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439 , 1408) # macro -NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455 , 1440) # macro -NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471 , 1456) # macro -NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503 , 1472) # macro -NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535 , 1504) # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i): # macro - return ((1567+(i)*64) , (1536+(i)*64)) -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i): # macro - return ((1586+(i)*64) , (1568+(i)*64)) -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1599+(i)*64) , (1587+(i)*64)) -NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135 , 2128) # macro -NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140 , 2136) # macro -NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149 , 2144) # macro -NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157 , 2152) # macro -NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165 , 2160) # macro -NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171 , 2168) # macro -NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175 , 2172) # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207 , 2207) # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # macro -NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223 , 2208) # macro -NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239 , 2224) # macro -NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255 , 2240) # macro -NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399 , 2368) # macro -NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431 , 2400) # macro -def NVCEC0_QMDV04_01_TPC_DISABLE_MASK(i): # macro - return ((2463+(i)*32) , (2432+(i)*32)) -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591 , 2560) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607 , 2592) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623 , 2608) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627 , 2624) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631 , 2628) # macro -def NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER(i): # macro - return ((2719+(i)*32) , (2688+(i)*32)) -NVCEC0_QMDV04_01_OUTER_PUT = (3038 , 3008) # macro -NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039 , 3039) # macro -NVCEC0_QMDV04_01_OUTER_GET = (3070 , 3040) # macro -NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071 , 3071) # macro -NV01_DEVICE_0 = (0x00000080) # macro -# NV0080_MAX_DEVICES = NV_MAX_DEVICES # macro -NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080) # macro -class struct_NV0080_ALLOC_PARAMETERS(Structure): - pass - -struct_NV0080_ALLOC_PARAMETERS._pack_ = 1 # source:False -struct_NV0080_ALLOC_PARAMETERS._fields_ = [ - ('deviceId', ctypes.c_uint32), - ('hClientShare', ctypes.c_uint32), - ('hTargetClient', ctypes.c_uint32), - ('hTargetDevice', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaSpaceSize', ctypes.c_uint64), - ('vaStartInternal', ctypes.c_uint64), - ('vaLimitInternal', ctypes.c_uint64), - ('vaMode', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_ALLOC_PARAMETERS = struct_NV0080_ALLOC_PARAMETERS -_cl2080_notification_h_ = True # macro -NV2080_NOTIFIERS_SW = (0) # macro -NV2080_NOTIFIERS_HOTPLUG = (1) # macro -NV2080_NOTIFIERS_POWER_CONNECTOR = (2) # macro -NV2080_NOTIFIERS_THERMAL_SW = (3) # macro -NV2080_NOTIFIERS_THERMAL_HW = (4) # macro -NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5) # macro -NV2080_NOTIFIERS_EVENTBUFFER = (6) # macro -NV2080_NOTIFIERS_DP_IRQ = (7) # macro -NV2080_NOTIFIERS_GR_DEBUG_INTR = (8) # macro -NV2080_NOTIFIERS_PMU_EVENT = (9) # macro -NV2080_NOTIFIERS_PMU_COMMAND = (10) # macro -NV2080_NOTIFIERS_TIMER = (11) # macro -NV2080_NOTIFIERS_GRAPHICS = (12) # macro -NV2080_NOTIFIERS_PPP = (13) # macro -NV2080_NOTIFIERS_VLD = (14) # macro -NV2080_NOTIFIERS_NVDEC0 = (14) # macro -NV2080_NOTIFIERS_NVDEC1 = (15) # macro -NV2080_NOTIFIERS_NVDEC2 = (16) # macro -NV2080_NOTIFIERS_NVDEC3 = (17) # macro -NV2080_NOTIFIERS_NVDEC4 = (18) # macro -NV2080_NOTIFIERS_NVDEC5 = (19) # macro -NV2080_NOTIFIERS_NVDEC6 = (20) # macro -NV2080_NOTIFIERS_NVDEC7 = (21) # macro -NV2080_NOTIFIERS_PDEC = (22) # macro -NV2080_NOTIFIERS_CE0 = (23) # macro -NV2080_NOTIFIERS_CE1 = (24) # macro -NV2080_NOTIFIERS_CE2 = (25) # macro -NV2080_NOTIFIERS_CE3 = (26) # macro -NV2080_NOTIFIERS_CE4 = (27) # macro -NV2080_NOTIFIERS_CE5 = (28) # macro -NV2080_NOTIFIERS_CE6 = (29) # macro -NV2080_NOTIFIERS_CE7 = (30) # macro -NV2080_NOTIFIERS_CE8 = (31) # macro -NV2080_NOTIFIERS_CE9 = (32) # macro -NV2080_NOTIFIERS_PSTATE_CHANGE = (33) # macro -NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34) # macro -NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35) # macro -NV2080_NOTIFIERS_PRIV_RING_HANG = (36) # macro -NV2080_NOTIFIERS_RC_ERROR = (37) # macro -NV2080_NOTIFIERS_MSENC = (38) # macro -NV2080_NOTIFIERS_NVENC0 = (38) # macro -NV2080_NOTIFIERS_NVENC1 = (39) # macro -NV2080_NOTIFIERS_NVENC2 = (40) # macro -NV2080_NOTIFIERS_UNUSED_0 = (41) # macro -NV2080_NOTIFIERS_ACPI_NOTIFY = (42) # macro -NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43) # macro -NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44) # macro -NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45) # macro -NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46) # macro -NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47) # macro -NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48) # macro -NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49) # macro -NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50) # macro -NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51) # macro -NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52) # macro -NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53) # macro -NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54) # macro -NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55) # macro -NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56) # macro -NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57) # macro -NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58) # macro -NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59) # macro -NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60) # macro -NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61) # macro -NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62) # macro -NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63) # macro -NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64) # macro -NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65) # macro -NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66) # macro -NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67) # macro -NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68) # macro -NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69) # macro -NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70) # macro -NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71) # macro -NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72) # macro -NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73) # macro -NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74) # macro -NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75) # macro -NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76) # macro -NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77) # macro -NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78) # macro -NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79) # macro -NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80) # macro -NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81) # macro -NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82) # macro -NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83) # macro -NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84) # macro -NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85) # macro -NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86) # macro -NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87) # macro -NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88) # macro -NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89) # macro -NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90) # macro -NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91) # macro -NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92) # macro -NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93) # macro -NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94) # macro -NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95) # macro -NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96) # macro -NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97) # macro -NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98) # macro -NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99) # macro -NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100) # macro -NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101) # macro -NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102) # macro -NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103) # macro -NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104) # macro -NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105) # macro -NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106) # macro -NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107) # macro -NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108) # macro -NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109) # macro -NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110) # macro -NV2080_NOTIFIERS_ECC_SBE = (111) # macro -NV2080_NOTIFIERS_ECC_DBE = (112) # macro -NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113) # macro -NV2080_NOTIFIERS_GC5_GPU_READY = (114) # macro -NV2080_NOTIFIERS_SEC2 = (115) # macro -NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116) # macro -NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117) # macro -NV2080_NOTIFIERS_POWER_EVENT = (118) # macro -NV2080_NOTIFIERS_CLOCKS_CHANGE = (119) # macro -NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120) # macro -NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121) # macro -NV2080_NOTIFIERS_RESERVED122 = (122) # macro -NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123) # macro -NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124) # macro -NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125) # macro -NV2080_NOTIFIERS_NVJPG = (126) # macro -NV2080_NOTIFIERS_NVJPEG0 = (126) # macro -NV2080_NOTIFIERS_NVJPEG1 = (127) # macro -NV2080_NOTIFIERS_NVJPEG2 = (128) # macro -NV2080_NOTIFIERS_NVJPEG3 = (129) # macro -NV2080_NOTIFIERS_NVJPEG4 = (130) # macro -NV2080_NOTIFIERS_NVJPEG5 = (131) # macro -NV2080_NOTIFIERS_NVJPEG6 = (132) # macro -NV2080_NOTIFIERS_NVJPEG7 = (133) # macro -NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134) # macro -NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135) # macro -NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136) # macro -NV2080_NOTIFIERS_RUNLIST_IDLE = (137) # macro -NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138) # macro -NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139) # macro -NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140) # macro -NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141) # macro -NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142) # macro -NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143) # macro -NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144) # macro -NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145) # macro -NV2080_NOTIFIERS_GR0 = (12) # macro -NV2080_NOTIFIERS_GR1 = (146) # macro -NV2080_NOTIFIERS_GR2 = (147) # macro -NV2080_NOTIFIERS_GR3 = (148) # macro -NV2080_NOTIFIERS_GR4 = (149) # macro -NV2080_NOTIFIERS_GR5 = (150) # macro -NV2080_NOTIFIERS_GR6 = (151) # macro -NV2080_NOTIFIERS_GR7 = (152) # macro -NV2080_NOTIFIERS_OFA = (153) # macro -NV2080_NOTIFIERS_OFA0 = (153) # macro -NV2080_NOTIFIERS_DSTATE_HDA = (154) # macro -NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155) # macro -NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156) # macro -NV2080_NOTIFIERS_UCODE_RESET = (157) # macro -NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158) # macro -NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159) # macro -NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160) # macro -NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161) # macro -NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162) # macro -NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163) # macro -NV2080_NOTIFIERS_UNUSED_1 = (164) # macro -NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165) # macro -NV2080_NOTIFIERS_CE10 = (166) # macro -NV2080_NOTIFIERS_CE11 = (167) # macro -NV2080_NOTIFIERS_CE12 = (168) # macro -NV2080_NOTIFIERS_CE13 = (169) # macro -NV2080_NOTIFIERS_CE14 = (170) # macro -NV2080_NOTIFIERS_CE15 = (171) # macro -NV2080_NOTIFIERS_CE16 = (172) # macro -NV2080_NOTIFIERS_CE17 = (173) # macro -NV2080_NOTIFIERS_CE18 = (174) # macro -NV2080_NOTIFIERS_CE19 = (175) # macro -NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176) # macro -NV2080_NOTIFIERS_NVPCF_EVENTS = (177) # macro -NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178) # macro -NV2080_NOTIFIERS_VRR_SET_TIMEOUT = (179) # macro -NV2080_NOTIFIERS_OFA1 = (180) # macro -NV2080_NOTIFIERS_AUX_POWER_EVENT = (181) # macro -NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182) # macro -NV2080_NOTIFIERS_NVENC3 = (183) # macro -NV2080_NOTIFIERS_GSP_PERF_TRACE = (184) # macro -NV2080_NOTIFIERS_INBAND_RESPONSE = (185) # macro -NV2080_NOTIFIERS_RESERVED_186 = (186) # macro -NV2080_NOTIFIERS_ECC_SBE_STORM = (187) # macro -NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188) # macro -NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189) # macro -NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190) # macro -NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191) # macro -NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192) # macro -NV2080_NOTIFIERS_POWER_SUSPEND = (193) # macro -NV2080_NOTIFIERS_POWER_RESUME = (194) # macro -NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195) # macro -NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196) # macro -NV2080_NOTIFIERS_MAXCOUNT = (197) # macro -# def NV2080_NOTIFIERS_GR(x): # macro -# return ((x==0)?((12)):((146)+(x-1))) -def NV2080_NOTIFIERS_GR_IDX(x): # macro - return ((x)-(12)) -def NV2080_NOTIFIER_TYPE_IS_GR(x): # macro - return (((x)==(12)) or (((x)>=(146)) and ((x)<=(152)))) -# def NV2080_NOTIFIERS_CE(x): # macro -# return (((x)<10)?((23)+(x)):((166)+(x)-10)) -# def NV2080_NOTIFIERS_CE_IDX(x): # macro -# return (((x)<=(32))?((x)-(23)):((x)-(166)+10)) -def NV2080_NOTIFIER_TYPE_IS_CE(x): # macro - return ((((x)>=(23)) and ((x)<=(32))) or (((x)>=(166)) and ((x)<=(175)))) -# def NV2080_NOTIFIERS_NVENC(x): # macro -# return (((x)<3)?((38)+(x)):((183)+(x)-3)) -# def NV2080_NOTIFIERS_NVENC_IDX(x): # macro -# return (((x)<=(40))?((x)-(38)):((x)-(183)+3)) -def NV2080_NOTIFIER_TYPE_IS_NVENC(x): # macro - return ((((x)>=(38)) and ((x)<=(40))) or (((x)==(183)))) -def NV2080_NOTIFIERS_NVDEC(x): # macro - return ((14)+(x)) -def NV2080_NOTIFIERS_NVDEC_IDX(x): # macro - return ((x)-(14)) -def NV2080_NOTIFIER_TYPE_IS_NVDEC(x): # macro - return (((x)>=(14)) and ((x)<=(21))) -def NV2080_NOTIFIERS_NVJPEG(x): # macro - return ((126)+(x)) -def NV2080_NOTIFIERS_NVJPEG_IDX(x): # macro - return ((x)-(126)) -def NV2080_NOTIFIER_TYPE_IS_NVJPEG(x): # macro - return (((x)>=(126)) and ((x)<=(133))) -# def NV2080_NOTIFIERS_OFAn(x): # macro -# return ((x==0)?((153)):((180))) -# def NV2080_NOTIFIERS_OFA_IDX(x): # macro -# return ((x==(153))?((x)-(153)):((x)-(180)+1)) -def NV2080_NOTIFIER_TYPE_IS_OFA(x): # macro - return (((x)==(153)) or ((x)==(180))) -def NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin): # macro - return ((47)+(pin)) -def NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin): # macro - return ((79)+(pin)) -NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000) # macro -NV2080_ENGINE_TYPE_NULL = (0x00000000) # macro -NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001) # macro -NV2080_ENGINE_TYPE_GR0 = (0x00000001) # macro -NV2080_ENGINE_TYPE_GR1 = (0x00000002) # macro -NV2080_ENGINE_TYPE_GR2 = (0x00000003) # macro -NV2080_ENGINE_TYPE_GR3 = (0x00000004) # macro -NV2080_ENGINE_TYPE_GR4 = (0x00000005) # macro -NV2080_ENGINE_TYPE_GR5 = (0x00000006) # macro -NV2080_ENGINE_TYPE_GR6 = (0x00000007) # macro -NV2080_ENGINE_TYPE_GR7 = (0x00000008) # macro -NV2080_ENGINE_TYPE_COPY0 = (0x00000009) # macro -NV2080_ENGINE_TYPE_COPY1 = (0x0000000a) # macro -NV2080_ENGINE_TYPE_COPY2 = (0x0000000b) # macro -NV2080_ENGINE_TYPE_COPY3 = (0x0000000c) # macro -NV2080_ENGINE_TYPE_COPY4 = (0x0000000d) # macro -NV2080_ENGINE_TYPE_COPY5 = (0x0000000e) # macro -NV2080_ENGINE_TYPE_COPY6 = (0x0000000f) # macro -NV2080_ENGINE_TYPE_COPY7 = (0x00000010) # macro -NV2080_ENGINE_TYPE_COPY8 = (0x00000011) # macro -NV2080_ENGINE_TYPE_COPY9 = (0x00000012) # macro -NV2080_ENGINE_TYPE_BSP = (0x00000013) # macro -NV2080_ENGINE_TYPE_NVDEC0 = (0x00000013) # macro -NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014) # macro -NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015) # macro -NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016) # macro -NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017) # macro -NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018) # macro -NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019) # macro -NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a) # macro -NV2080_ENGINE_TYPE_MSENC = (0x0000001b) # macro -NV2080_ENGINE_TYPE_NVENC0 = (0x0000001b) # macro -NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c) # macro -NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d) # macro -NV2080_ENGINE_TYPE_VP = (0x0000001e) # macro -NV2080_ENGINE_TYPE_ME = (0x0000001f) # macro -NV2080_ENGINE_TYPE_PPP = (0x00000020) # macro -NV2080_ENGINE_TYPE_MPEG = (0x00000021) # macro -NV2080_ENGINE_TYPE_SW = (0x00000022) # macro -NV2080_ENGINE_TYPE_CIPHER = (0x00000023) # macro -NV2080_ENGINE_TYPE_TSEC = (0x00000023) # macro -NV2080_ENGINE_TYPE_VIC = (0x00000024) # macro -NV2080_ENGINE_TYPE_MP = (0x00000025) # macro -NV2080_ENGINE_TYPE_SEC2 = (0x00000026) # macro -NV2080_ENGINE_TYPE_HOST = (0x00000027) # macro -NV2080_ENGINE_TYPE_DPU = (0x00000028) # macro -NV2080_ENGINE_TYPE_PMU = (0x00000029) # macro -NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a) # macro -NV2080_ENGINE_TYPE_NVJPG = (0x0000002b) # macro -NV2080_ENGINE_TYPE_NVJPEG0 = (0x0000002b) # macro -NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c) # macro -NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d) # macro -NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e) # macro -NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f) # macro -NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030) # macro -NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031) # macro -NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032) # macro -NV2080_ENGINE_TYPE_OFA = (0x00000033) # macro -NV2080_ENGINE_TYPE_OFA0 = (0x00000033) # macro -NV2080_ENGINE_TYPE_COPY10 = (0x00000034) # macro -NV2080_ENGINE_TYPE_COPY11 = (0x00000035) # macro -NV2080_ENGINE_TYPE_COPY12 = (0x00000036) # macro -NV2080_ENGINE_TYPE_COPY13 = (0x00000037) # macro -NV2080_ENGINE_TYPE_COPY14 = (0x00000038) # macro -NV2080_ENGINE_TYPE_COPY15 = (0x00000039) # macro -NV2080_ENGINE_TYPE_COPY16 = (0x0000003a) # macro -NV2080_ENGINE_TYPE_COPY17 = (0x0000003b) # macro -NV2080_ENGINE_TYPE_COPY18 = (0x0000003c) # macro -NV2080_ENGINE_TYPE_COPY19 = (0x0000003d) # macro -NV2080_ENGINE_TYPE_OFA1 = (0x0000003e) # macro -NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053) # macro -NV2080_ENGINE_TYPE_LAST = (0x00000054) # macro -NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff) # macro -NV2080_ENGINE_TYPE_COPY_SIZE = 64 # macro -NV2080_ENGINE_TYPE_NVENC_SIZE = 4 # macro -NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8 # macro -NV2080_ENGINE_TYPE_NVDEC_SIZE = 8 # macro -NV2080_ENGINE_TYPE_GR_SIZE = 8 # macro -NV2080_ENGINE_TYPE_OFA_SIZE = 2 # macro -def NV2080_ENGINE_TYPE_COMP_DECOMP_COPY(i): # macro - return ((0x00000040)+(i)) -def NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i): # macro - return (((i)>=(0x00000040)) and ((i)<=(0x00000053))) -def NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX(i): # macro - return ((i)-(0x00000040)) -# def NV2080_ENGINE_TYPE_COPY(i): # macro -# return (((i)<10)?((0x00000009)+(i)):((0x00000034)+(i)-10)) -def NV2080_ENGINE_TYPE_IS_COPY(i): # macro - return ((((i)>=(0x00000009)) and ((i)<=(0x00000012))) or (((i)>=(0x00000034)) and ((i)<=(0x0000003d)))) -# def NV2080_ENGINE_TYPE_COPY_IDX(i): # macro -# return (((i)<=(0x00000012))?((i)-(0x00000009)):((i)-(0x00000034)+10)) -# def NV2080_ENGINE_TYPE_NVENC(i): # macro -# return (((i)<3)?((0x0000001b)+(i)):((0x0000003f)+(i)-3)) -def NV2080_ENGINE_TYPE_IS_NVENC(i): # macro - return ((((i)>=(0x0000001b)) and ((i)<=(0x0000001d))) or (((i)==(0x0000003f)))) -# def NV2080_ENGINE_TYPE_NVENC_IDX(i): # macro -# return (((i)<=(0x0000001d))?((i)-(0x0000001b)):((i)-(0x0000003f)+3)) -def NV2080_ENGINE_TYPE_NVDEC(i): # macro - return ((0x00000013)+(i)) -def NV2080_ENGINE_TYPE_IS_NVDEC(i): # macro - return (((i)>=(0x00000013)) and ((i)=(0x0000002b)) and ((i)=(0x00000001)) and ((i)((0x00000000))) and ((i)<((0x00000054)))) -NV2080_CLIENT_TYPE_TEX = (0x00000001) # macro -NV2080_CLIENT_TYPE_COLOR = (0x00000002) # macro -NV2080_CLIENT_TYPE_DEPTH = (0x00000003) # macro -NV2080_CLIENT_TYPE_DA = (0x00000004) # macro -NV2080_CLIENT_TYPE_FE = (0x00000005) # macro -NV2080_CLIENT_TYPE_SCC = (0x00000006) # macro -NV2080_CLIENT_TYPE_WID = (0x00000007) # macro -NV2080_CLIENT_TYPE_MSVLD = (0x00000008) # macro -NV2080_CLIENT_TYPE_MSPDEC = (0x00000009) # macro -NV2080_CLIENT_TYPE_MSPPP = (0x0000000a) # macro -NV2080_CLIENT_TYPE_VIC = (0x0000000b) # macro -NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff) # macro -NV2080_GC5_EXIT_COMPLETE = (0x00000001) # macro -NV2080_GC5_ENTRY_ABORTED = (0x00000002) # macro -NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000) # macro -NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001) # macro -NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000) # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX = 7 : 0 # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK = 15 : 8 # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON = 23 : 16 # macro -class struct__cl2080_tag0(Structure): - pass - -struct__cl2080_tag0._pack_ = 1 # source:False -struct__cl2080_tag0._fields_ = [ - ('Reserved00', ctypes.c_uint32 * 1984), -] - -Nv2080Typedef = struct__cl2080_tag0 -Nv20Subdevice0 = struct__cl2080_tag0 -NV2080_TYPEDEF = Nv20Subdevice0 # macro -class struct_Nv2080HdcpStatusChangeNotificationRec(Structure): - pass - -struct_Nv2080HdcpStatusChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080HdcpStatusChangeNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), - ('hdcpStatusChangeNotif', ctypes.c_uint32), -] - -Nv2080HdcpStatusChangeNotification = struct_Nv2080HdcpStatusChangeNotificationRec -class struct_Nv2080PStateChangeNotificationRec(Structure): - pass - -class struct_Nv2080PStateChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080PStateChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080PStateChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080PStateChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080PStateChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080PStateChangeNotificationRec_timeStamp), - ('NewPstate', ctypes.c_uint32), -] - -Nv2080PStateChangeNotification = struct_Nv2080PStateChangeNotificationRec -class struct_Nv2080ClocksChangeNotificationRec(Structure): - pass - -class struct_Nv2080ClocksChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080ClocksChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080ClocksChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080ClocksChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080ClocksChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080ClocksChangeNotificationRec_timeStamp), -] - -Nv2080ClocksChangeNotification = struct_Nv2080ClocksChangeNotificationRec -class struct_Nv2080WorkloadModulationChangeNotificationRec(Structure): - pass - -class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080WorkloadModulationChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080WorkloadModulationChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp), - ('WorkloadModulationEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -Nv2080WorkloadModulationChangeNotification = struct_Nv2080WorkloadModulationChangeNotificationRec -class struct_c__SA_Nv2080HotplugNotification(Structure): - pass - -struct_c__SA_Nv2080HotplugNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080HotplugNotification._fields_ = [ - ('plugDisplayMask', ctypes.c_uint32), - ('unplugDisplayMask', ctypes.c_uint32), -] - -Nv2080HotplugNotification = struct_c__SA_Nv2080HotplugNotification -class struct_c__SA_Nv2080PowerEventNotification(Structure): - pass - -struct_c__SA_Nv2080PowerEventNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080PowerEventNotification._fields_ = [ - ('bSwitchToAC', ctypes.c_ubyte), - ('bGPUCapabilityChanged', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('displayMaskAffected', ctypes.c_uint32), -] - -Nv2080PowerEventNotification = struct_c__SA_Nv2080PowerEventNotification -class struct_Nv2080DpIrqNotificationRec(Structure): - pass - -struct_Nv2080DpIrqNotificationRec._pack_ = 1 # source:False -struct_Nv2080DpIrqNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), -] - -Nv2080DpIrqNotification = struct_Nv2080DpIrqNotificationRec -class struct_Nv2080DstateXusbPpcNotificationRec(Structure): - pass - -struct_Nv2080DstateXusbPpcNotificationRec._pack_ = 1 # source:False -struct_Nv2080DstateXusbPpcNotificationRec._fields_ = [ - ('dstateXusb', ctypes.c_uint32), - ('dstatePpc', ctypes.c_uint32), -] - -Nv2080DstateXusbPpcNotification = struct_Nv2080DstateXusbPpcNotificationRec -class struct_Nv2080XusbPpcConnectStateNotificationRec(Structure): - pass - -struct_Nv2080XusbPpcConnectStateNotificationRec._pack_ = 1 # source:False -struct_Nv2080XusbPpcConnectStateNotificationRec._fields_ = [ - ('bConnected', ctypes.c_ubyte), -] - -Nv2080XusbPpcConnectStateNotification = struct_Nv2080XusbPpcConnectStateNotificationRec -class struct_Nv2080ACPIEvent(Structure): - pass - -struct_Nv2080ACPIEvent._pack_ = 1 # source:False -struct_Nv2080ACPIEvent._fields_ = [ - ('event', ctypes.c_uint32), -] - -Nv2080ACPIEvent = struct_Nv2080ACPIEvent -class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(Structure): - pass - -struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._pack_ = 1 # source:False -struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ - ('currentZone', ctypes.c_uint32), -] - -NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC -class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(Structure): - pass - -struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._pack_ = 1 # source:False -struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ - ('currentZone', ctypes.c_uint32), -] - -NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC -class struct_Nv2080AudioHdcpRequestRec(Structure): - pass - -struct_Nv2080AudioHdcpRequestRec._pack_ = 1 # source:False -struct_Nv2080AudioHdcpRequestRec._fields_ = [ - ('displayId', ctypes.c_uint32), - ('requestedState', ctypes.c_uint32), -] - -Nv2080AudioHdcpRequest = struct_Nv2080AudioHdcpRequestRec -class struct_Nv2080GC5GpuReadyParams(Structure): - pass - -struct_Nv2080GC5GpuReadyParams._pack_ = 1 # source:False -struct_Nv2080GC5GpuReadyParams._fields_ = [ - ('event', ctypes.c_uint32), - ('sciIntr0', ctypes.c_uint32), - ('sciIntr1', ctypes.c_uint32), -] - -Nv2080GC5GpuReadyParams = struct_Nv2080GC5GpuReadyParams -class struct_c__SA_Nv2080PrivRegAccessFaultNotification(Structure): - pass - -struct_c__SA_Nv2080PrivRegAccessFaultNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080PrivRegAccessFaultNotification._fields_ = [ - ('errAddr', ctypes.c_uint32), -] - -Nv2080PrivRegAccessFaultNotification = struct_c__SA_Nv2080PrivRegAccessFaultNotification -class struct_Nv2080DstateHdaCodecNotificationRec(Structure): - pass - -struct_Nv2080DstateHdaCodecNotificationRec._pack_ = 1 # source:False -struct_Nv2080DstateHdaCodecNotificationRec._fields_ = [ - ('dstateHdaCodec', ctypes.c_uint32), -] - -Nv2080DstateHdaCodecNotification = struct_Nv2080DstateHdaCodecNotificationRec -class struct_Nv2080HdmiFrlRequestNotificationRec(Structure): - pass - -struct_Nv2080HdmiFrlRequestNotificationRec._pack_ = 1 # source:False -struct_Nv2080HdmiFrlRequestNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), -] - -Nv2080HdmiFrlRequestNotification = struct_Nv2080HdmiFrlRequestNotificationRec -class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(Structure): - pass - -struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._pack_ = 1 # source:False -struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._fields_ = [ - ('platformPowerModeIndex', ctypes.c_ubyte), - ('platformPowerModeMask', ctypes.c_ubyte), - ('eventReason', ctypes.c_ubyte), -] - -NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS -class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(Structure): - pass - -struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._pack_ = 1 # source:False -struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._fields_ = [ - ('workloadType', ctypes.c_ubyte), -] - -NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE -class struct_c__SA_Nv2080QosIntrNotification(Structure): - pass - -struct_c__SA_Nv2080QosIntrNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080QosIntrNotification._fields_ = [ - ('engineType', ctypes.c_uint32), -] - -Nv2080QosIntrNotification = struct_c__SA_Nv2080QosIntrNotification -class struct_c__SA_Nv2080EccDbeNotification(Structure): - pass - -struct_c__SA_Nv2080EccDbeNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080EccDbeNotification._fields_ = [ - ('physAddress', ctypes.c_uint64), -] - -Nv2080EccDbeNotification = struct_c__SA_Nv2080EccDbeNotification -class struct_c__SA_Nv2080LpwrDifrPrefetchNotification(Structure): - pass - -struct_c__SA_Nv2080LpwrDifrPrefetchNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080LpwrDifrPrefetchNotification._fields_ = [ - ('l2CacheSize', ctypes.c_uint32), -] - -Nv2080LpwrDifrPrefetchNotification = struct_c__SA_Nv2080LpwrDifrPrefetchNotification -class struct_c__SA_Nv2080NvlinkLnkChangeNotification(Structure): - pass - -struct_c__SA_Nv2080NvlinkLnkChangeNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080NvlinkLnkChangeNotification._fields_ = [ - ('GpuId', ctypes.c_uint32), - ('linkId', ctypes.c_uint32), -] - -Nv2080NvlinkLnkChangeNotification = struct_c__SA_Nv2080NvlinkLnkChangeNotification -class struct_c__SA_Nv2080VrrSetTimeoutNotification(Structure): - pass - -struct_c__SA_Nv2080VrrSetTimeoutNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080VrrSetTimeoutNotification._fields_ = [ - ('head', ctypes.c_uint32), -] - -Nv2080VrrSetTimeoutNotification = struct_c__SA_Nv2080VrrSetTimeoutNotification -_clc56f_h_ = True # macro -AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f) # macro -# NVC56F_TYPEDEF = AMPERE_CHANNELChannelGPFifoA # macro -NVC56F_NUMBER_OF_SUBCHANNELS = (8) # macro -NVC56F_SET_OBJECT = (0x00000000) # macro -# NVC56F_SET_OBJECT_NVCLASS = 15 : 0 # macro -# NVC56F_SET_OBJECT_ENGINE = 20 : 16 # macro -NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f # macro -NVC56F_ILLEGAL = (0x00000004) # macro -# NVC56F_ILLEGAL_HANDLE = 31 : 0 # macro -NVC56F_NOP = (0x00000008) # macro -# NVC56F_NOP_HANDLE = 31 : 0 # macro -NVC56F_SEMAPHOREA = (0x00000010) # macro -# NVC56F_SEMAPHOREA_OFFSET_UPPER = 7 : 0 # macro -NVC56F_SEMAPHOREB = (0x00000014) # macro -# NVC56F_SEMAPHOREB_OFFSET_LOWER = 31 : 2 # macro -NVC56F_SEMAPHOREC = (0x00000018) # macro -# NVC56F_SEMAPHOREC_PAYLOAD = 31 : 0 # macro -NVC56F_SEMAPHORED = (0x0000001C) # macro -# NVC56F_SEMAPHORED_OPERATION = 4 : 0 # macro -NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001 # macro -NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002 # macro -NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004 # macro -NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008 # macro -NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010 # macro -# NVC56F_SEMAPHORED_ACQUIRE_SWITCH = 12 : 12 # macro -NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000 # macro -NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001 # macro -# NVC56F_SEMAPHORED_RELEASE_WFI = 20 : 20 # macro -NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000 # macro -NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001 # macro -# NVC56F_SEMAPHORED_RELEASE_SIZE = 24 : 24 # macro -NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000 # macro -NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001 # macro -# NVC56F_SEMAPHORED_REDUCTION = 30 : 27 # macro -NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000 # macro -NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001 # macro -NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002 # macro -NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003 # macro -NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004 # macro -NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005 # macro -NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006 # macro -NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007 # macro -# NVC56F_SEMAPHORED_FORMAT = 31 : 31 # macro -NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000 # macro -NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001 # macro -NVC56F_NON_STALL_INTERRUPT = (0x00000020) # macro -# NVC56F_NON_STALL_INTERRUPT_HANDLE = 31 : 0 # macro -NVC56F_FB_FLUSH = (0x00000024) # macro -# NVC56F_FB_FLUSH_HANDLE = 31 : 0 # macro -NVC56F_MEM_OP_A = (0x00000028) # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = 5 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = 5 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = 10 : 6 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = 7 : 6 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = 6 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = 11 : 11 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = 31 : 12 # macro -NVC56F_MEM_OP_B = (0x0000002c) # macro -# NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = 31 : 0 # macro -NVC56F_MEM_OP_C = (0x00000030) # macro -# NVC56F_MEM_OP_C_MEMBAR_TYPE = 2 : 0 # macro -NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # macro -NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB = 0 : 0 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC = 1 : 1 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY = 4 : 2 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = 6 : 5 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = 9 : 7 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = 9 : 7 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = 11 : 10 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = 31 : 12 # macro -# NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = 19 : 0 # macro -NVC56F_MEM_OP_D = (0x00000034) # macro -# NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = 26 : 0 # macro -# NVC56F_MEM_OP_D_OPERATION = 31 : 27 # macro -NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # macro -NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # macro -NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # macro -NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # macro -NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # macro -NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # macro -NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # macro -NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # macro -NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # macro -NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = 1 : 0 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = 2 : 2 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = 6 : 3 # macro -NVC56F_SET_REFERENCE = (0x00000050) # macro -# NVC56F_SET_REFERENCE_COUNT = 31 : 0 # macro -NVC56F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC56F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC56F_SEM_ADDR_HI = (0x00000060) # macro -# NVC56F_SEM_ADDR_HI_OFFSET = 7 : 0 # macro -NVC56F_SEM_PAYLOAD_LO = (0x00000064) # macro -# NVC56F_SEM_PAYLOAD_LO_PAYLOAD = 31 : 0 # macro -NVC56F_SEM_PAYLOAD_HI = (0x00000068) # macro -# NVC56F_SEM_PAYLOAD_HI_PAYLOAD = 31 : 0 # macro -NVC56F_SEM_EXECUTE = (0x0000006c) # macro -# NVC56F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005 # macro -NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006 # macro -# NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG = 12 : 12 # macro -NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP = 25 : 25 # macro -NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_REDUCTION = 30 : 27 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005 # macro -NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006 # macro -NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007 # macro -# NVC56F_SEM_EXECUTE_REDUCTION_FORMAT = 31 : 31 # macro -NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000 # macro -NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001 # macro -NVC56F_WFI = (0x00000078) # macro -# NVC56F_WFI_SCOPE = 0 : 0 # macro -NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # macro -NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # macro -NVC56F_WFI_SCOPE_ALL = 0x00000001 # macro -NVC56F_YIELD = (0x00000080) # macro -# NVC56F_YIELD_OP = 1 : 0 # macro -NVC56F_YIELD_OP_NOP = 0x00000000 # macro -NVC56F_YIELD_OP_TSG = 0x00000003 # macro -NVC56F_CLEAR_FAULTED = (0x00000084) # macro -# NVC56F_CLEAR_FAULTED_HANDLE = 30 : 0 # macro -# NVC56F_CLEAR_FAULTED_TYPE = 31 : 31 # macro -NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000 # macro -NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001 # macro -NVC56F_GP_ENTRY__SIZE = 8 # macro -# NVC56F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC56F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC56F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC56F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC56F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC56F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC56F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC56F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -# NVC56F_DMA_METHOD_ADDRESS_OLD = 12 : 2 # macro -# NVC56F_DMA_METHOD_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_SUBDEVICE_MASK = 15 : 4 # macro -# NVC56F_DMA_METHOD_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_TERT_OP = 17 : 16 # macro -NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000) # macro -NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001) # macro -NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002) # macro -NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003) # macro -NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000) # macro -# NVC56F_DMA_METHOD_COUNT_OLD = 28 : 18 # macro -# NVC56F_DMA_METHOD_COUNT = 28 : 16 # macro -# NVC56F_DMA_IMMD_DATA = 28 : 16 # macro -# NVC56F_DMA_SEC_OP = 31 : 29 # macro -NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000) # macro -NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001) # macro -NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002) # macro -NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003) # macro -NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004) # macro -NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005) # macro -NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006) # macro -NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007) # macro -# NVC56F_DMA_INCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_INCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_INCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_INCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001) # macro -# NVC56F_DMA_INCR_DATA = 31 : 0 # macro -# NVC56F_DMA_NONINCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_NONINCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_NONINCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_NONINCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003) # macro -# NVC56F_DMA_NONINCR_DATA = 31 : 0 # macro -# NVC56F_DMA_ONEINCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_ONEINCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_ONEINCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_ONEINCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005) # macro -# NVC56F_DMA_ONEINCR_DATA = 31 : 0 # macro -NVC56F_DMA_NOP = (0x00000000) # macro -# NVC56F_DMA_IMMD_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_IMMD_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_IMMD_OPCODE = 31 : 29 # macro -NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004) # macro -# NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE = 15 : 4 # macro -# NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001) # macro -# NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE = 15 : 4 # macro -# NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002) # macro -# NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003) # macro -# NVC56F_DMA_ENDSEG_OPCODE = 31 : 29 # macro -NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007) # macro -# NVC56F_DMA_ADDRESS = 12 : 2 # macro -# NVC56F_DMA_SUBCH = 15 : 13 # macro -# NVC56F_DMA_OPCODE3 = 17 : 16 # macro -NVC56F_DMA_OPCODE3_NONE = (0x00000000) # macro -# NVC56F_DMA_COUNT = 28 : 18 # macro -# NVC56F_DMA_OPCODE = 31 : 29 # macro -NVC56F_DMA_OPCODE_METHOD = (0x00000000) # macro -NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002) # macro -# NVC56F_DMA_DATA = 31 : 0 # macro -class struct_Nvc56fControl_struct(Structure): - pass - -struct_Nvc56fControl_struct._pack_ = 1 # source:False -struct_Nvc56fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 16), - ('Put', ctypes.c_uint32), - ('Get', ctypes.c_uint32), - ('Reference', ctypes.c_uint32), - ('PutHi', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 2), - ('TopLevelGet', ctypes.c_uint32), - ('TopLevelGetHi', ctypes.c_uint32), - ('GetHi', ctypes.c_uint32), - ('Ignored02', ctypes.c_uint32 * 7), - ('Ignored03', ctypes.c_uint32), - ('Ignored04', ctypes.c_uint32 * 1), - ('GPGet', ctypes.c_uint32), - ('GPPut', ctypes.c_uint32), - ('Ignored05', ctypes.c_uint32 * 92), -] - -Nvc56fControl = struct_Nvc56fControl_struct -AmpereAControlGPFifo = struct_Nvc56fControl_struct -__gh100_clc86f_h__ = True # macro -HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f) # macro -NVC86F_SET_OBJECT = (0x00000000) # macro -NVC86F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC86F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC86F_SEM_ADDR_HI = (0x00000060) # macro -# NVC86F_SEM_ADDR_HI_OFFSET = 24 : 0 # macro -NVC86F_SEM_PAYLOAD_LO = (0x00000064) # macro -NVC86F_SEM_PAYLOAD_HI = (0x00000068) # macro -NVC86F_SEM_EXECUTE = (0x0000006c) # macro -# NVC86F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -# NVC86F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -# NVC86F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC86F_GP_ENTRY__SIZE = 8 # macro -# NVC86F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC86F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC86F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = 24 : 8 # macro -# NVC86F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC86F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC86F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC86F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC86F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # macro -NVC86F_WFI = (0x00000078) # macro -# NVC86F_WFI_SCOPE = 0 : 0 # macro -NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # macro -NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # macro -NVC86F_WFI_SCOPE_ALL = 0x00000001 # macro -NVC86F_MEM_OP_A = (0x00000028) # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = 5 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = 5 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = 10 : 6 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = 7 : 6 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = 8 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = 11 : 11 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = 31 : 12 # macro -NVC86F_MEM_OP_B = (0x0000002c) # macro -# NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = 31 : 0 # macro -NVC86F_MEM_OP_C = (0x00000030) # macro -# NVC86F_MEM_OP_C_MEMBAR_TYPE = 2 : 0 # macro -NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # macro -NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB = 0 : 0 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC = 1 : 1 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY = 4 : 2 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = 6 : 5 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = 9 : 7 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = 9 : 7 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = 11 : 10 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = 31 : 12 # macro -# NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = 19 : 0 # macro -NVC86F_MEM_OP_D = (0x00000034) # macro -# NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = 26 : 0 # macro -# NVC86F_MEM_OP_D_OPERATION = 31 : 27 # macro -NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # macro -NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # macro -NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # macro -NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b # macro -NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # macro -NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # macro -NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # macro -NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # macro -NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # macro -NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # macro -NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = 1 : 0 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = 2 : 2 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = 6 : 3 # macro -# NVC86F_MEM_OP_D_MMU_OPERATION_TYPE = 23 : 20 # macro -NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000 # macro -NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001 # macro -class struct_Nvc86fControl_struct(Structure): - pass - -struct_Nvc86fControl_struct._pack_ = 1 # source:False -struct_Nvc86fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 16), - ('Put', ctypes.c_uint32), - ('Get', ctypes.c_uint32), - ('Reference', ctypes.c_uint32), - ('PutHi', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 2), - ('TopLevelGet', ctypes.c_uint32), - ('TopLevelGetHi', ctypes.c_uint32), - ('GetHi', ctypes.c_uint32), - ('Ignored02', ctypes.c_uint32 * 7), - ('Ignored03', ctypes.c_uint32), - ('Ignored04', ctypes.c_uint32 * 1), - ('GPGet', ctypes.c_uint32), - ('GPPut', ctypes.c_uint32), - ('Ignored05', ctypes.c_uint32 * 92), -] - -Nvc86fControl = struct_Nvc86fControl_struct -HopperAControlGPFifo = struct_Nvc86fControl_struct -__gb100_clc96f_h__ = True # macro -BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f) # macro -NVC96F_SET_OBJECT = (0x00000000) # macro -NVC96F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC96F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC96F_SEM_ADDR_HI = (0x00000060) # macro -# NVC96F_SEM_ADDR_HI_OFFSET = 24 : 0 # macro -NVC96F_SEM_PAYLOAD_LO = (0x00000064) # macro -NVC96F_SEM_PAYLOAD_HI = (0x00000068) # macro -NVC96F_SEM_EXECUTE = (0x0000006c) # macro -# NVC96F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -# NVC96F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -# NVC96F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC96F_GP_ENTRY__SIZE = 8 # macro -# NVC96F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC96F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC96F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = 24 : 8 # macro -# NVC96F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC96F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC96F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC96F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC96F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # macro -class struct_Nvc96fControl_struct(Structure): - pass - -struct_Nvc96fControl_struct._pack_ = 1 # source:False -struct_Nvc96fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 35), - ('GPPut', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 92), -] - -Nvc96fControl = struct_Nvc96fControl_struct -BlackwellAControlGPFifo = struct_Nvc96fControl_struct -_clc761_h_ = True # macro -BLACKWELL_USERMODE_A = (0x0000c761) # macro -GT200_DEBUGGER = (0x000083de) # macro -NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de) # macro -class struct_NV83DE_ALLOC_PARAMETERS(Structure): - pass - -struct_NV83DE_ALLOC_PARAMETERS._pack_ = 1 # source:False -struct_NV83DE_ALLOC_PARAMETERS._fields_ = [ - ('hDebuggerClient_Obsolete', ctypes.c_uint32), - ('hAppClient', ctypes.c_uint32), - ('hClass3dObject', ctypes.c_uint32), -] - -NV83DE_ALLOC_PARAMETERS = struct_NV83DE_ALLOC_PARAMETERS -NV01_ROOT = (0x0) # macro -NV1_ROOT = (0x00000000) # macro -NV01_NULL_OBJECT = (0x00000000) # macro -NV1_NULL_OBJECT = (0x00000000) # macro -NV01_ROOT_NON_PRIV = (0x00000001) # macro -NV1_ROOT_NON_PRIV = (0x00000001) # macro -NV01_ROOT_CLIENT = (0x00000041) # macro -FABRIC_MANAGER_SESSION = (0x0000000f) # macro -NV0020_GPU_MANAGEMENT = (0x00000020) # macro -NV20_SUBDEVICE_0 = (0x00002080) # macro -NV2081_BINAPI = (0x00002081) # macro -NV2082_BINAPI_PRIVILEGED = (0x00002082) # macro -NV20_SUBDEVICE_DIAG = (0x0000208f) # macro -NV01_CONTEXT_DMA = (0x00000002) # macro -NV01_MEMORY_SYSTEM = (0x0000003e) # macro -NV1_MEMORY_SYSTEM = (0x0000003e) # macro -NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # macro -NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # macro -NV01_MEMORY_PRIVILEGED = (0x0000003f) # macro -NV1_MEMORY_PRIVILEGED = (0x0000003f) # macro -NV01_MEMORY_LOCAL_USER = (0x00000040) # macro -NV1_MEMORY_LOCAL_USER = (0x00000040) # macro -NV01_MEMORY_USER = (0x00000040) # macro -NV1_MEMORY_USER = (0x00000040) # macro -NV_MEMORY_EXTENDED_USER = (0x00000042) # macro -NV01_MEMORY_VIRTUAL = (0x00000070) # macro -NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # macro -NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # macro -NV_MEMORY_MAPPER = (0x000000fe) # macro -NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2) # macro -NV01_MEMORY_SYNCPOINT = (0x000000c3) # macro -NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071) # macro -NV01_MEMORY_DEVICELESS = (0x000090ce) # macro -NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076) # macro -NV01_MEMORY_HW_RESOURCES = (0x000000b1) # macro -NV01_MEMORY_LIST_SYSTEM = (0x00000081) # macro -NV01_MEMORY_LIST_FBMEM = (0x00000082) # macro -NV01_MEMORY_LIST_OBJECT = (0x00000083) # macro -NV_IMEX_SESSION = (0x000000f1) # macro -NV01_MEMORY_FLA = (0x000000f3) # macro -NV_MEMORY_EXPORT = (0x000000e0) # macro -NV_CE_UTILS = (0x00000050) # macro -NV_MEMORY_FABRIC = (0x000000f8) # macro -NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9) # macro -NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb) # macro -FABRIC_VASPACE_A = (0x000000fc) # macro -NV_MEMORY_MULTICAST_FABRIC = (0x000000fd) # macro -IO_VASPACE_A = (0x000000f2) # macro -NV01_NULL = (0x00000030) # macro -NV1_NULL = (0x00000030) # macro -NV01_EVENT = (0x00000005) # macro -NV1_EVENT = (0x00000005) # macro -NV01_EVENT_KERNEL_CALLBACK = (0x00000078) # macro -NV1_EVENT_KERNEL_CALLBACK = (0x00000078) # macro -NV01_EVENT_OS_EVENT = (0x00000079) # macro -NV1_EVENT_OS_EVENT = (0x00000079) # macro -NV01_EVENT_WIN32_EVENT = (0x00000079) # macro -NV1_EVENT_WIN32_EVENT = (0x00000079) # macro -NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E) # macro -NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) # macro -NV01_TIMER = (0x00000004) # macro -NV1_TIMER = (0x00000004) # macro -KERNEL_GRAPHICS_CONTEXT = (0x00000090) # macro -LOCK_STRESS_OBJECT = (0x00000100) # macro -NV50_CHANNEL_GPFIFO = (0x0000506f) # macro -GF100_CHANNEL_GPFIFO = (0x0000906f) # macro -KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f) # macro -UVM_CHANNEL_RETAINER = (0x0000c574) # macro -KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f) # macro -MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f) # macro -PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f) # macro -VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f) # macro -TURING_CHANNEL_GPFIFO_A = (0x0000c46f) # macro -BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f) # macro -NV04_SOFTWARE_TEST = (0x0000007d) # macro -NV4_SOFTWARE_TEST = (0x0000007d) # macro -NV30_GSYNC = (0x000030f1) # macro -VOLTA_USERMODE_A = (0x0000c361) # macro -TURING_USERMODE_A = (0x0000c461) # macro -AMPERE_USERMODE_A = (0x0000c561) # macro -HOPPER_USERMODE_A = (0x0000c661) # macro -NVC371_DISP_SF_USER = (0x0000c371) # macro -NVC372_DISPLAY_SW = (0x0000c372) # macro -NVC573_DISP_CAPABILITIES = (0x0000c573) # macro -NVC673_DISP_CAPABILITIES = (0x0000c673) # macro -NVC773_DISP_CAPABILITIES = (0x0000c773) # macro -NVC973_DISP_CAPABILITIES = (0x0000c973) # macro -NVCA73_DISP_CAPABILITIES = (0x0000ca73) # macro -NV04_DISPLAY_COMMON = (0x00000073) # macro -NV50_DEFERRED_API_CLASS = (0x00005080) # macro -MPS_COMPUTE = (0x0000900e) # macro -NVC570_DISPLAY = (0x0000c570) # macro -NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a) # macro -NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b) # macro -NVC57D_CORE_CHANNEL_DMA = (0x0000c57d) # macro -NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e) # macro -NVC670_DISPLAY = (0x0000c670) # macro -NVC671_DISP_SF_USER = (0x0000c671) # macro -NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a) # macro -NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b) # macro -NVC67D_CORE_CHANNEL_DMA = (0x0000c67d) # macro -NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e) # macro -NVC77F_ANY_CHANNEL_DMA = (0x0000c77f) # macro -NVC770_DISPLAY = (0x0000c770) # macro -NVC771_DISP_SF_USER = (0x0000c771) # macro -NVC77D_CORE_CHANNEL_DMA = (0x0000c77d) # macro -NVC970_DISPLAY = (0x0000c970) # macro -NVC971_DISP_SF_USER = (0x0000c971) # macro -NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a) # macro -NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b) # macro -NVC97D_CORE_CHANNEL_DMA = (0x0000c97d) # macro -NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e) # macro -NVCA70_DISPLAY = (0x0000ca70) # macro -NVCA71_DISP_SF_USER = (0x0000ca71) # macro -NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a) # macro -NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b) # macro -NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d) # macro -NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e) # macro -NV9010_VBLANK_CALLBACK = (0x00009010) # macro -GF100_PROFILER = (0x000090cc) # macro -MAXWELL_PROFILER = (0x0000b0cc) # macro -MAXWELL_PROFILER_CONTEXT = (0x0000b1cc) # macro -MAXWELL_PROFILER_DEVICE = (0x0000b2cc) # macro -GF100_SUBDEVICE_MASTER = (0x000090e6) # macro -GF100_SUBDEVICE_INFOROM = (0x000090e7) # macro -GF100_ZBC_CLEAR = (0x00009096) # macro -GF100_DISP_SW = (0x00009072) # macro -GF100_TIMED_SEMAPHORE_SW = (0x00009074) # macro -G84_PERFBUFFER = (0x0000844c) # macro -NV50_MEMORY_VIRTUAL = (0x000050a0) # macro -NV50_P2P = (0x0000503b) # macro -NV50_THIRD_PARTY_P2P = (0x0000503c) # macro -FERMI_TWOD_A = (0x0000902d) # macro -FERMI_VASPACE_A = (0x000090f1) # macro -HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2) # macro -GF100_HDACODEC = (0x000090ec) # macro -NVB8B0_VIDEO_DECODER = (0x0000b8b0) # macro -NVC4B0_VIDEO_DECODER = (0x0000c4b0) # macro -NVC6B0_VIDEO_DECODER = (0x0000c6b0) # macro -NVC7B0_VIDEO_DECODER = (0x0000c7b0) # macro -NVC9B0_VIDEO_DECODER = (0x0000c9b0) # macro -NVCDB0_VIDEO_DECODER = (0x0000cdb0) # macro -NVCFB0_VIDEO_DECODER = (0x0000cfb0) # macro -NVC4B7_VIDEO_ENCODER = (0x0000c4b7) # macro -NVB4B7_VIDEO_ENCODER = (0x0000b4b7) # macro -NVC7B7_VIDEO_ENCODER = (0x0000c7b7) # macro -NVC9B7_VIDEO_ENCODER = (0x0000c9b7) # macro -NVCFB7_VIDEO_ENCODER = (0x0000cfb7) # macro -NVB8D1_VIDEO_NVJPG = (0x0000b8d1) # macro -NVC4D1_VIDEO_NVJPG = (0x0000c4d1) # macro -NVC9D1_VIDEO_NVJPG = (0x0000c9d1) # macro -NVCDD1_VIDEO_NVJPG = (0x0000cdd1) # macro -NVCFD1_VIDEO_NVJPG = (0x0000cfd1) # macro -NVB8FA_VIDEO_OFA = (0x0000b8fa) # macro -NVC6FA_VIDEO_OFA = (0x0000c6fa) # macro -NVC7FA_VIDEO_OFA = (0x0000c7fa) # macro -NVC9FA_VIDEO_OFA = (0x0000c9fa) # macro -NVCDFA_VIDEO_OFA = (0x0000cdfa) # macro -NVCFFA_VIDEO_OFA = (0x0000cffa) # macro -KEPLER_INLINE_TO_MEMORY_B = (0x0000a140) # macro -FERMI_CONTEXT_SHARE_A = (0x00009067) # macro -KEPLER_CHANNEL_GROUP_A = (0x0000a06c) # macro -PASCAL_DMA_COPY_A = (0x0000c0b5) # macro -TURING_DMA_COPY_A = (0x0000c5b5) # macro -AMPERE_DMA_COPY_A = (0x0000C6B5) # macro -AMPERE_DMA_COPY_B = (0x0000c7b5) # macro -HOPPER_DMA_COPY_A = (0x0000c8b5) # macro -BLACKWELL_DMA_COPY_A = (0x0000C9B5) # macro -BLACKWELL_DMA_COPY_B = (0x0000cab5) # macro -MAXWELL_DMA_COPY_A = (0x0000b0b5) # macro -ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365) # macro -MMU_FAULT_BUFFER = (0x0000c369) # macro -MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763) # macro -TURING_A = (0x0000c597) # macro -TURING_COMPUTE_A = (0x0000c5c0) # macro -AMPERE_A = (0x0000c697) # macro -AMPERE_COMPUTE_A = 0xC6C0 # macro -AMPERE_B = (0x0000c797) # macro -AMPERE_COMPUTE_B = (0x0000c7c0) # macro -ADA_A = (0x0000c997) # macro -ADA_COMPUTE_A = (0x0000c9c0) # macro -AMPERE_SMC_PARTITION_REF = (0x0000c637) # macro -AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638) # macro -AMPERE_SMC_CONFIG_SESSION = (0x0000c639) # macro -NV0092_RG_LINE_CALLBACK = (0x00000092) # macro -AMPERE_SMC_MONITOR_SESSION = (0x0000c640) # macro -HOPPER_A = (0x0000cb97) # macro -HOPPER_COMPUTE_A = (0x0000cbc0) # macro -BLACKWELL_A = (0x0000cd97) # macro -BLACKWELL_COMPUTE_A = 0xCDC0 # macro -BLACKWELL_B = (0x0000ce97) # macro -BLACKWELL_COMPUTE_B = (0x0000cec0) # macro -BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40) # macro -NV40_DEBUG_BUFFER = (0x000000db) # macro -RM_USER_SHARED_DATA = (0x000000de) # macro -NV40_I2C = (0x0000402c) # macro -KEPLER_DEVICE_VGPU = (0x0000a080) # macro -NVA081_VGPU_CONFIG = (0x0000a081) # macro -NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084) # macro -NV0060_SYNC_GPU_BOOST = (0x00000060) # macro -GP100_UVM_SW = (0x0000c076) # macro -NVENC_SW_SESSION = (0x0000a0bc) # macro -NV_EVENT_BUFFER = (0x000090cd) # macro -NVFBC_SW_SESSION = (0x0000a0bd) # macro -NV_CONFIDENTIAL_COMPUTE = (0x0000cb33) # macro -NV_COUNTER_COLLECTION_UNIT = (0x0000cbca) # macro -NV_SEMAPHORE_SURFACE = (0x000000da) # macro -_cl_ampere_compute_a_h_ = True # macro -NVC6C0_SET_OBJECT = 0x0000 # macro -# NVC6C0_SET_OBJECT_CLASS_ID = 15 : 0 # macro -# NVC6C0_SET_OBJECT_ENGINE_ID = 20 : 16 # macro -NVC6C0_NO_OPERATION = 0x0100 # macro -# NVC6C0_NO_OPERATION_V = 31 : 0 # macro -NVC6C0_SET_NOTIFY_A = 0x0104 # macro -# NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_NOTIFY_B = 0x0108 # macro -# NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_NOTIFY = 0x010c # macro -# NVC6C0_NOTIFY_TYPE = 31 : 0 # macro -NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000 # macro -NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001 # macro -NVC6C0_WAIT_FOR_IDLE = 0x0110 # macro -# NVC6C0_WAIT_FOR_IDLE_V = 31 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # macro -NVC6C0_SEND_GO_IDLE = 0x013c # macro -# NVC6C0_SEND_GO_IDLE_V = 31 : 0 # macro -NVC6C0_PM_TRIGGER = 0x0140 # macro -# NVC6C0_PM_TRIGGER_V = 31 : 0 # macro -NVC6C0_PM_TRIGGER_WFI = 0x0144 # macro -# NVC6C0_PM_TRIGGER_WFI_V = 31 : 0 # macro -NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148 # macro -# NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V = 31 : 0 # macro -NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c # macro -# NVC6C0_FE_ATOMIC_SEQUENCE_END_V = 31 : 0 # macro -NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150 # macro -# NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V = 31 : 0 # macro -NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154 # macro -# NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V = 31 : 0 # macro -NVC6C0_LINE_LENGTH_IN = 0x0180 # macro -# NVC6C0_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC6C0_LINE_COUNT = 0x0184 # macro -# NVC6C0_LINE_COUNT_VALUE = 31 : 0 # macro -NVC6C0_OFFSET_OUT_UPPER = 0x0188 # macro -# NVC6C0_OFFSET_OUT_UPPER_VALUE = 16 : 0 # macro -NVC6C0_OFFSET_OUT = 0x018c # macro -# NVC6C0_OFFSET_OUT_VALUE = 31 : 0 # macro -NVC6C0_PITCH_OUT = 0x0190 # macro -# NVC6C0_PITCH_OUT_VALUE = 31 : 0 # macro -NVC6C0_SET_DST_BLOCK_SIZE = 0x0194 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005 # macro -NVC6C0_SET_DST_WIDTH = 0x0198 # macro -# NVC6C0_SET_DST_WIDTH_V = 31 : 0 # macro -NVC6C0_SET_DST_HEIGHT = 0x019c # macro -# NVC6C0_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC6C0_SET_DST_DEPTH = 0x01a0 # macro -# NVC6C0_SET_DST_DEPTH_V = 31 : 0 # macro -NVC6C0_SET_DST_LAYER = 0x01a4 # macro -# NVC6C0_SET_DST_LAYER_V = 31 : 0 # macro -NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8 # macro -# NVC6C0_SET_DST_ORIGIN_BYTES_X_V = 20 : 0 # macro -NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac # macro -# NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V = 16 : 0 # macro -NVC6C0_LAUNCH_DMA = 0x01b0 # macro -# NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT = 0 : 0 # macro -NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_COMPLETION_TYPE = 5 : 4 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002 # macro -# NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE = 9 : 8 # macro -NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE = 12 : 12 # macro -NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE = 1 : 1 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_OP = 15 : 13 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT = 3 : 2 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE = 6 : 6 # macro -NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001 # macro -NVC6C0_LOAD_INLINE_DATA = 0x01b4 # macro -# NVC6C0_LOAD_INLINE_DATA_V = 31 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc # macro -# NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0 # macro -# NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4 # macro -# NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD = 31 : 0 # macro -NVC6C0_SET_SM_SCG_CONTROL = 0x01e8 # macro -# NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS = 0 : 0 # macro -NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000 # macro -NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001 # macro -NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0 # macro -# NVC6C0_SET_I2M_SPARE_NOOP00_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4 # macro -# NVC6C0_SET_I2M_SPARE_NOOP01_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8 # macro -# NVC6C0_SET_I2M_SPARE_NOOP02_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc # macro -# NVC6C0_SET_I2M_SPARE_NOOP03_V = 31 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE = 31 : 0 # macro -NVC6C0_PERFMON_TRANSFER = 0x0210 # macro -# NVC6C0_PERFMON_TRANSFER_V = 31 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION = 0 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_DATA = 4 : 4 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT = 12 : 12 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS = 1 : 1 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA = 2 : 2 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001 # macro -NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220 # macro -# NVC6C0_SET_RESERVED_SW_METHOD00_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224 # macro -# NVC6C0_SET_RESERVED_SW_METHOD01_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228 # macro -# NVC6C0_SET_RESERVED_SW_METHOD02_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c # macro -# NVC6C0_SET_RESERVED_SW_METHOD03_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230 # macro -# NVC6C0_SET_RESERVED_SW_METHOD04_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234 # macro -# NVC6C0_SET_RESERVED_SW_METHOD05_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238 # macro -# NVC6C0_SET_RESERVED_SW_METHOD06_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c # macro -# NVC6C0_SET_RESERVED_SW_METHOD07_V = 31 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_SET_CWD_REF_COUNTER = 0x0248 # macro -# NVC6C0_SET_CWD_REF_COUNTER_SELECT = 5 : 0 # macro -# NVC6C0_SET_CWD_REF_COUNTER_VALUE = 23 : 8 # macro -NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c # macro -# NVC6C0_SET_RESERVED_SW_METHOD08_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250 # macro -# NVC6C0_SET_RESERVED_SW_METHOD09_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254 # macro -# NVC6C0_SET_RESERVED_SW_METHOD10_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258 # macro -# NVC6C0_SET_RESERVED_SW_METHOD11_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c # macro -# NVC6C0_SET_RESERVED_SW_METHOD12_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260 # macro -# NVC6C0_SET_RESERVED_SW_METHOD13_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264 # macro -# NVC6C0_SET_RESERVED_SW_METHOD14_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268 # macro -# NVC6C0_SET_RESERVED_SW_METHOD15_V = 31 : 0 # macro -NVC6C0_SET_SCG_CONTROL = 0x0270 # macro -# NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT = 8 : 0 # macro -# NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT = 20 : 12 # macro -# NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE = 24 : 24 # macro -NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000 # macro -NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001 # macro -NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280 # macro -# NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284 # macro -# NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_SET_QMD_VERSION = 0x0288 # macro -# NVC6C0_SET_QMD_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_CHECK_QMD_VERSION = 0x0290 # macro -# NVC6C0_CHECK_QMD_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_INVALIDATE_SKED_CACHES = 0x0298 # macro -# NVC6C0_INVALIDATE_SKED_CACHES_V = 0 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK = 7 : 0 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE = 8 : 8 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE = 12 : 12 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE = 16 : 16 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE = 20 : 20 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE = 24 : 24 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0 # macro -# NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4 # macro -# NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS = 31 : 0 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8 # macro -# NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE = 0 : 0 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001 # macro -# NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE = 1 : 1 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001 # macro -NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0 # macro -# NVC6C0_SET_CWD_SLOT_COUNT_V = 7 : 0 # macro -NVC6C0_SEND_PCAS_A = 0x02b4 # macro -# NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 = 31 : 0 # macro -NVC6C0_SEND_PCAS_B = 0x02b8 # macro -# NVC6C0_SEND_PCAS_B_FROM = 23 : 0 # macro -# NVC6C0_SEND_PCAS_B_DELTA = 31 : 24 # macro -NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc # macro -# NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE = 0 : 0 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001 # macro -# NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE = 1 : 1 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0 # macro -# NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION = 3 : 0 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B # macro -NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc # macro -# NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID = 0 : 0 # macro -NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000 # macro -NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER = 7 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT = 8 : 0 # macro -NVC6C0_SET_SPA_VERSION = 0x0310 # macro -# NVC6C0_SET_SPA_VERSION_MINOR = 7 : 0 # macro -# NVC6C0_SET_SPA_VERSION_MAJOR = 15 : 8 # macro -NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318 # macro -# NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER = 31 : 0 # macro -NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c # macro -# NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER = 31 : 0 # macro -def NVC6C0_LOAD_INLINE_QMD_DATA(i): # macro - return (0x0320+(i)*4) -# NVC6C0_LOAD_INLINE_QMD_DATA_V = 31 : 0 # macro -NVC6C0_SET_FALCON00 = 0x0500 # macro -# NVC6C0_SET_FALCON00_V = 31 : 0 # macro -NVC6C0_SET_FALCON01 = 0x0504 # macro -# NVC6C0_SET_FALCON01_V = 31 : 0 # macro -NVC6C0_SET_FALCON02 = 0x0508 # macro -# NVC6C0_SET_FALCON02_V = 31 : 0 # macro -NVC6C0_SET_FALCON03 = 0x050c # macro -# NVC6C0_SET_FALCON03_V = 31 : 0 # macro -NVC6C0_SET_FALCON04 = 0x0510 # macro -# NVC6C0_SET_FALCON04_V = 31 : 0 # macro -NVC6C0_SET_FALCON05 = 0x0514 # macro -# NVC6C0_SET_FALCON05_V = 31 : 0 # macro -NVC6C0_SET_FALCON06 = 0x0518 # macro -# NVC6C0_SET_FALCON06_V = 31 : 0 # macro -NVC6C0_SET_FALCON07 = 0x051c # macro -# NVC6C0_SET_FALCON07_V = 31 : 0 # macro -NVC6C0_SET_FALCON08 = 0x0520 # macro -# NVC6C0_SET_FALCON08_V = 31 : 0 # macro -NVC6C0_SET_FALCON09 = 0x0524 # macro -# NVC6C0_SET_FALCON09_V = 31 : 0 # macro -NVC6C0_SET_FALCON10 = 0x0528 # macro -# NVC6C0_SET_FALCON10_V = 31 : 0 # macro -NVC6C0_SET_FALCON11 = 0x052c # macro -# NVC6C0_SET_FALCON11_V = 31 : 0 # macro -NVC6C0_SET_FALCON12 = 0x0530 # macro -# NVC6C0_SET_FALCON12_V = 31 : 0 # macro -NVC6C0_SET_FALCON13 = 0x0534 # macro -# NVC6C0_SET_FALCON13_V = 31 : 0 # macro -NVC6C0_SET_FALCON14 = 0x0538 # macro -# NVC6C0_SET_FALCON14_V = 31 : 0 # macro -NVC6C0_SET_FALCON15 = 0x053c # macro -# NVC6C0_SET_FALCON15_V = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS = 31 : 0 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94 # macro -# NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE = 0 : 0 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001 # macro -def NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i): # macro - return (0x0da0+(i)*4) -# NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V = 31 : 0 # macro -NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4 # macro -# NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT = 5 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8 # macro -# NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL = 0 : 0 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528 # macro -# NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE = 0 : 0 # macro -NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_A = 0x1550 # macro -# NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_B = 0x1554 # macro -# NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_C = 0x1558 # macro -# NVC6C0_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER = 16 : 0 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560 # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564 # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX = 19 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574 # macro -# NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER = 16 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578 # macro -# NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c # macro -# NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX = 21 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION = 0 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA = 4 : 4 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT = 12 : 12 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944 # macro -# NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE = 1 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002 # macro -NVC6C0_PIPE_NOP = 0x1a2c # macro -# NVC6C0_PIPE_NOP_V = 31 : 0 # macro -NVC6C0_SET_SPARE00 = 0x1a30 # macro -# NVC6C0_SET_SPARE00_V = 31 : 0 # macro -NVC6C0_SET_SPARE01 = 0x1a34 # macro -# NVC6C0_SET_SPARE01_V = 31 : 0 # macro -NVC6C0_SET_SPARE02 = 0x1a38 # macro -# NVC6C0_SET_SPARE02_V = 31 : 0 # macro -NVC6C0_SET_SPARE03 = 0x1a3c # macro -# NVC6C0_SET_SPARE03_V = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION = 1 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE = 20 : 20 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE = 28 : 28 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE = 2 : 2 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE = 3 : 3 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP = 11 : 9 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT = 18 : 17 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP = 19 : 19 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001 # macro -NVC6C0_SET_TRAP_HANDLER_A = 0x25f8 # macro -# NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_TRAP_HANDLER_B = 0x25fc # macro -# NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_BINDLESS_TEXTURE = 0x2608 # macro -# NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT = 2 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i): # macro - return (0x32f4+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i): # macro - return (0x3314+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V = 31 : 0 # macro -NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334 # macro -# NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = 0 : 0 # macro -NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338 # macro -# NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = 0 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i): # macro - return (0x333c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i): # macro - return (0x335c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i): # macro - return (0x337c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT = 7 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i): # macro - return (0x339c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 = 1 : 0 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 = 4 : 2 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 = 6 : 5 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 = 9 : 7 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 = 11 : 10 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 = 14 : 12 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 = 16 : 15 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 = 19 : 17 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 = 21 : 20 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 = 24 : 22 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 = 26 : 25 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 = 29 : 27 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE = 31 : 30 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i): # macro - return (0x33bc+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE = 0 : 0 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE = 2 : 1 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED = 3 : 3 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC = 19 : 4 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK = 7 : 0 # macro -NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0 # macro -# NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = 7 : 0 # macro -NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4 # macro -# NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = 7 : 0 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V = 31 : 0 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V = 31 : 0 # macro -def NVC6C0_SET_MME_SHADOW_SCRATCH(i): # macro - return (0x3400+(i)*4) -# NVC6C0_SET_MME_SHADOW_SCRATCH_V = 31 : 0 # macro -__gb100_clcdc0_h__ = True # macro -_clc6b5_h_ = True # macro -NVC6B5_NOP = (0x00000100) # macro -# NVC6B5_NOP_PARAMETER = 31 : 0 # macro -NVC6B5_PM_TRIGGER = (0x00000140) # macro -# NVC6B5_PM_TRIGGER_V = 31 : 0 # macro -NVC6B5_SET_SEMAPHORE_A = (0x00000240) # macro -# NVC6B5_SET_SEMAPHORE_A_UPPER = 16 : 0 # macro -NVC6B5_SET_SEMAPHORE_B = (0x00000244) # macro -# NVC6B5_SET_SEMAPHORE_B_LOWER = 31 : 0 # macro -NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # macro -# NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = 31 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_A = (0x00000254) # macro -# NVC6B5_SET_RENDER_ENABLE_A_UPPER = 7 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_B = (0x00000258) # macro -# NVC6B5_SET_RENDER_ENABLE_B_LOWER = 31 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C) # macro -# NVC6B5_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # macro -NVC6B5_SET_SRC_PHYS_MODE = (0x00000260) # macro -# NVC6B5_SET_SRC_PHYS_MODE_TARGET = 1 : 0 # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC6B5_SET_SRC_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC6B5_SET_SRC_PHYS_MODE_FLA = 9 : 9 # macro -NVC6B5_SET_DST_PHYS_MODE = (0x00000264) # macro -# NVC6B5_SET_DST_PHYS_MODE_TARGET = 1 : 0 # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC6B5_SET_DST_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC6B5_SET_DST_PHYS_MODE_FLA = 9 : 9 # macro -NVC6B5_LAUNCH_DMA = (0x00000300) # macro -# NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = 1 : 0 # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # macro -# NVC6B5_LAUNCH_DMA_FLUSH_ENABLE = 2 : 2 # macro -NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_FLUSH_TYPE = 25 : 25 # macro -NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE = 4 : 3 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # macro -# NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE = 6 : 5 # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # macro -# NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = 7 : 7 # macro -NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = 8 : 8 # macro -NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE = 9 : 9 # macro -NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_REMAP_ENABLE = 10 : 10 # macro -NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE = 11 : 11 # macro -NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SRC_TYPE = 12 : 12 # macro -NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_DST_TYPE = 13 : 13 # macro -NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = 17 : 14 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = 18 : 18 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = 19 : 19 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_VPRMODE = 23 : 22 # macro -NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY = 24 : 24 # macro -# NVC6B5_LAUNCH_DMA_DISABLE_PLC = 26 : 26 # macro -NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE = 31 : 28 # macro -NVC6B5_OFFSET_IN_UPPER = (0x00000400) # macro -# NVC6B5_OFFSET_IN_UPPER_UPPER = 16 : 0 # macro -NVC6B5_OFFSET_IN_LOWER = (0x00000404) # macro -# NVC6B5_OFFSET_IN_LOWER_VALUE = 31 : 0 # macro -NVC6B5_OFFSET_OUT_UPPER = (0x00000408) # macro -# NVC6B5_OFFSET_OUT_UPPER_UPPER = 16 : 0 # macro -NVC6B5_OFFSET_OUT_LOWER = (0x0000040C) # macro -# NVC6B5_OFFSET_OUT_LOWER_VALUE = 31 : 0 # macro -NVC6B5_PITCH_IN = (0x00000410) # macro -# NVC6B5_PITCH_IN_VALUE = 31 : 0 # macro -NVC6B5_PITCH_OUT = (0x00000414) # macro -# NVC6B5_PITCH_OUT_VALUE = 31 : 0 # macro -NVC6B5_LINE_LENGTH_IN = (0x00000418) # macro -# NVC6B5_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC6B5_LINE_COUNT = (0x0000041C) # macro -# NVC6B5_LINE_COUNT_VALUE = 31 : 0 # macro -NVC6B5_SET_REMAP_CONST_A = (0x00000700) # macro -# NVC6B5_SET_REMAP_CONST_A_V = 31 : 0 # macro -NVC6B5_SET_REMAP_CONST_B = (0x00000704) # macro -# NVC6B5_SET_REMAP_CONST_B_V = 31 : 0 # macro -NVC6B5_SET_REMAP_COMPONENTS = (0x00000708) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_X = 2 : 0 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_Y = 6 : 4 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_Z = 10 : 8 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_W = 14 : 12 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = 17 : 16 # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # macro -# NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = 21 : 20 # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # macro -# NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = 25 : 24 # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC6B5_SET_DST_WIDTH = (0x00000710) # macro -# NVC6B5_SET_DST_WIDTH_V = 31 : 0 # macro -NVC6B5_SET_DST_HEIGHT = (0x00000714) # macro -# NVC6B5_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC6B5_SET_DST_DEPTH = (0x00000718) # macro -# NVC6B5_SET_DST_DEPTH_V = 31 : 0 # macro -NVC6B5_SET_DST_LAYER = (0x0000071C) # macro -# NVC6B5_SET_DST_LAYER_V = 31 : 0 # macro -NVC6B5_SET_DST_ORIGIN = (0x00000720) # macro -# NVC6B5_SET_DST_ORIGIN_X = 15 : 0 # macro -# NVC6B5_SET_DST_ORIGIN_Y = 31 : 16 # macro -NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC6B5_SET_SRC_WIDTH = (0x0000072C) # macro -# NVC6B5_SET_SRC_WIDTH_V = 31 : 0 # macro -NVC6B5_SET_SRC_HEIGHT = (0x00000730) # macro -# NVC6B5_SET_SRC_HEIGHT_V = 31 : 0 # macro -NVC6B5_SET_SRC_DEPTH = (0x00000734) # macro -# NVC6B5_SET_SRC_DEPTH_V = 31 : 0 # macro -NVC6B5_SET_SRC_LAYER = (0x00000738) # macro -# NVC6B5_SET_SRC_LAYER_V = 31 : 0 # macro -NVC6B5_SET_SRC_ORIGIN = (0x0000073C) # macro -# NVC6B5_SET_SRC_ORIGIN_X = 15 : 0 # macro -# NVC6B5_SET_SRC_ORIGIN_Y = 31 : 16 # macro -NVC6B5_SRC_ORIGIN_X = (0x00000744) # macro -# NVC6B5_SRC_ORIGIN_X_VALUE = 31 : 0 # macro -NVC6B5_SRC_ORIGIN_Y = (0x00000748) # macro -# NVC6B5_SRC_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC6B5_DST_ORIGIN_X = (0x0000074C) # macro -# NVC6B5_DST_ORIGIN_X_VALUE = 31 : 0 # macro -NVC6B5_DST_ORIGIN_Y = (0x00000750) # macro -# NVC6B5_DST_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC6B5_PM_TRIGGER_END = (0x00001114) # macro -# NVC6B5_PM_TRIGGER_END_V = 31 : 0 # macro -_clc9b5_h_ = True # macro -NVC9B5_NOP = (0x00000100) # macro -# NVC9B5_NOP_PARAMETER = 31 : 0 # macro -NVC9B5_PM_TRIGGER = (0x00000140) # macro -# NVC9B5_PM_TRIGGER_V = 31 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_TYPE = (0x0000021C) # macro -# NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE = 0 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE = (0x00000000) # macro -NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT = (0x00000001) # macro -NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER = (0x00000220) # macro -# NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER = (0x00000224) # macro -# NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_A = (0x00000240) # macro -# NVC9B5_SET_SEMAPHORE_A_UPPER = 24 : 0 # macro -NVC9B5_SET_SEMAPHORE_B = (0x00000244) # macro -# NVC9B5_SET_SEMAPHORE_B_LOWER = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # macro -# NVC9B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER = (0x0000024C) # macro -# NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD = 31 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_A = (0x00000254) # macro -# NVC9B5_SET_RENDER_ENABLE_A_UPPER = 24 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_B = (0x00000258) # macro -# NVC9B5_SET_RENDER_ENABLE_B_LOWER = 31 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_C = (0x0000025C) # macro -# NVC9B5_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # macro -NVC9B5_SET_SRC_PHYS_MODE = (0x00000260) # macro -# NVC9B5_SET_SRC_PHYS_MODE_TARGET = 1 : 0 # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SRC_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC9B5_SET_SRC_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC9B5_SET_SRC_PHYS_MODE_FLA = 9 : 9 # macro -NVC9B5_SET_DST_PHYS_MODE = (0x00000264) # macro -# NVC9B5_SET_DST_PHYS_MODE_TARGET = 1 : 0 # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_DST_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC9B5_SET_DST_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC9B5_SET_DST_PHYS_MODE_FLA = 9 : 9 # macro -NVC9B5_LAUNCH_DMA = (0x00000300) # macro -# NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = 1 : 0 # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # macro -# NVC9B5_LAUNCH_DMA_FLUSH_ENABLE = 2 : 2 # macro -NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_FLUSH_TYPE = 25 : 25 # macro -NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE = 4 : 3 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # macro -# NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE = 6 : 5 # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # macro -# NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = 7 : 7 # macro -NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = 8 : 8 # macro -NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE = 9 : 9 # macro -NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_REMAP_ENABLE = 10 : 10 # macro -NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE = 11 : 11 # macro -NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SRC_TYPE = 12 : 12 # macro -NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_DST_TYPE = 13 : 13 # macro -NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = 17 : 14 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA = (0x00000008) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB = (0x00000009) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN = (0x0000000B) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX = (0x0000000C) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC = (0x0000000D) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD = (0x0000000E) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE = (0x0000000F) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = 18 : 18 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = 19 : 19 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_COPY_TYPE = 21 : 20 # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED = (0x00000003) # macro -# NVC9B5_LAUNCH_DMA_VPRMODE = 22 : 22 # macro -NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE = 23 : 23 # macro -NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_RESERVED_START_OF_COPY = 24 : 24 # macro -# NVC9B5_LAUNCH_DMA_DISABLE_PLC = 26 : 26 # macro -NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE = 27 : 27 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_RESERVED_ERR_CODE = 31 : 28 # macro -NVC9B5_OFFSET_IN_UPPER = (0x00000400) # macro -# NVC9B5_OFFSET_IN_UPPER_UPPER = 24 : 0 # macro -NVC9B5_OFFSET_IN_LOWER = (0x00000404) # macro -# NVC9B5_OFFSET_IN_LOWER_VALUE = 31 : 0 # macro -NVC9B5_OFFSET_OUT_UPPER = (0x00000408) # macro -# NVC9B5_OFFSET_OUT_UPPER_UPPER = 24 : 0 # macro -NVC9B5_OFFSET_OUT_LOWER = (0x0000040C) # macro -# NVC9B5_OFFSET_OUT_LOWER_VALUE = 31 : 0 # macro -NVC9B5_PITCH_IN = (0x00000410) # macro -# NVC9B5_PITCH_IN_VALUE = 31 : 0 # macro -NVC9B5_PITCH_OUT = (0x00000414) # macro -# NVC9B5_PITCH_OUT_VALUE = 31 : 0 # macro -NVC9B5_LINE_LENGTH_IN = (0x00000418) # macro -# NVC9B5_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC9B5_LINE_COUNT = (0x0000041C) # macro -# NVC9B5_LINE_COUNT_VALUE = 31 : 0 # macro -NVC9B5_SET_SECURE_COPY_MODE = (0x00000500) # macro -# NVC9B5_SET_SECURE_COPY_MODE_MODE = 0 : 0 # macro -NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT = (0x00000001) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET = 20 : 19 # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID = 23 : 21 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA = 24 : 24 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET = 26 : 25 # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID = 29 : 27 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA = 30 : 30 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY = 31 : 31 # macro -NVC9B5_SET_DECRYPT_IV0 = (0x00000504) # macro -# NVC9B5_SET_DECRYPT_IV0_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_IV1 = (0x00000508) # macro -# NVC9B5_SET_DECRYPT_IV1_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_IV2 = (0x0000050C) # macro -# NVC9B5_SET_DECRYPT_IV2_VALUE = 31 : 0 # macro -NVC9B5_RESERVED_SET_AESCOUNTER = (0x00000510) # macro -# NVC9B5_RESERVED_SET_AESCOUNTER_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER = (0x00000514) # macro -# NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER = (0x00000518) # macro -# NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER = (0x00000530) # macro -# NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER = (0x00000534) # macro -# NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER = (0x00000538) # macro -# NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER = (0x0000053C) # macro -# NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS = (0x00000580) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION = 0 : 0 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS = (0x00000001) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO = 3 : 1 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY = (0x00000001) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK = (0x00000002) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM = (0x00000003) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE = (0x00000004) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH = (0x00000005) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM = 29 : 28 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32 = (0x00000001) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32 = (0x00000002) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC = (0x00000003) # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH = (0x00000584) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_V = 31 : 0 # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER = (0x00000588) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER = (0x0000058C) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_DECOMPRESS_CHECKSUM = (0x00000590) # macro -# NVC9B5_SET_DECOMPRESS_CHECKSUM_V = 31 : 0 # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS = (0x000006FC) # macro -# NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE = 0 : 0 # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE = (0x00000000) # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE = (0x00000001) # macro -NVC9B5_SET_REMAP_CONST_A = (0x00000700) # macro -# NVC9B5_SET_REMAP_CONST_A_V = 31 : 0 # macro -NVC9B5_SET_REMAP_CONST_B = (0x00000704) # macro -# NVC9B5_SET_REMAP_CONST_B_V = 31 : 0 # macro -NVC9B5_SET_REMAP_COMPONENTS = (0x00000708) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_X = 2 : 0 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_Y = 6 : 4 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_Z = 10 : 8 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_W = 14 : 12 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = 17 : 16 # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # macro -# NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = 21 : 20 # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # macro -# NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = 25 : 24 # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE = (0x0000070C) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC9B5_SET_DST_WIDTH = (0x00000710) # macro -# NVC9B5_SET_DST_WIDTH_V = 31 : 0 # macro -NVC9B5_SET_DST_HEIGHT = (0x00000714) # macro -# NVC9B5_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC9B5_SET_DST_DEPTH = (0x00000718) # macro -# NVC9B5_SET_DST_DEPTH_V = 31 : 0 # macro -NVC9B5_SET_DST_LAYER = (0x0000071C) # macro -# NVC9B5_SET_DST_LAYER_V = 31 : 0 # macro -NVC9B5_SET_DST_ORIGIN = (0x00000720) # macro -# NVC9B5_SET_DST_ORIGIN_X = 15 : 0 # macro -# NVC9B5_SET_DST_ORIGIN_Y = 31 : 16 # macro -NVC9B5_SET_SRC_BLOCK_SIZE = (0x00000728) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC9B5_SET_SRC_WIDTH = (0x0000072C) # macro -# NVC9B5_SET_SRC_WIDTH_V = 31 : 0 # macro -NVC9B5_SET_SRC_HEIGHT = (0x00000730) # macro -# NVC9B5_SET_SRC_HEIGHT_V = 31 : 0 # macro -NVC9B5_SET_SRC_DEPTH = (0x00000734) # macro -# NVC9B5_SET_SRC_DEPTH_V = 31 : 0 # macro -NVC9B5_SET_SRC_LAYER = (0x00000738) # macro -# NVC9B5_SET_SRC_LAYER_V = 31 : 0 # macro -NVC9B5_SET_SRC_ORIGIN = (0x0000073C) # macro -# NVC9B5_SET_SRC_ORIGIN_X = 15 : 0 # macro -# NVC9B5_SET_SRC_ORIGIN_Y = 31 : 16 # macro -NVC9B5_SRC_ORIGIN_X = (0x00000744) # macro -# NVC9B5_SRC_ORIGIN_X_VALUE = 31 : 0 # macro -NVC9B5_SRC_ORIGIN_Y = (0x00000748) # macro -# NVC9B5_SRC_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC9B5_DST_ORIGIN_X = (0x0000074C) # macro -# NVC9B5_DST_ORIGIN_X_VALUE = 31 : 0 # macro -NVC9B5_DST_ORIGIN_Y = (0x00000750) # macro -# NVC9B5_DST_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC9B5_PM_TRIGGER_END = (0x00001114) # macro -# NVC9B5_PM_TRIGGER_END_V = 31 : 0 # macro -class struct__clc9b5_tag0(Structure): - pass - -struct__clc9b5_tag0._pack_ = 1 # source:False -struct__clc9b5_tag0._fields_ = [ - ('Reserved00', ctypes.c_uint32 * 64), - ('Nop', ctypes.c_uint32), - ('Reserved01', ctypes.c_uint32 * 15), - ('PmTrigger', ctypes.c_uint32), - ('Reserved02', ctypes.c_uint32 * 54), - ('SetMonitoredFenceType', ctypes.c_uint32), - ('SetMonitoredFenceSignalAddrBaseUpper', ctypes.c_uint32), - ('SetMonitoredFenceSignalAddrBaseLower', ctypes.c_uint32), - ('Reserved03', ctypes.c_uint32 * 6), - ('SetSemaphoreA', ctypes.c_uint32), - ('SetSemaphoreB', ctypes.c_uint32), - ('SetSemaphorePayload', ctypes.c_uint32), - ('SetSemaphorePayloadUpper', ctypes.c_uint32), - ('Reserved04', ctypes.c_uint32 * 1), - ('SetRenderEnableA', ctypes.c_uint32), - ('SetRenderEnableB', ctypes.c_uint32), - ('SetRenderEnableC', ctypes.c_uint32), - ('SetSrcPhysMode', ctypes.c_uint32), - ('SetDstPhysMode', ctypes.c_uint32), - ('Reserved05', ctypes.c_uint32 * 38), - ('LaunchDma', ctypes.c_uint32), - ('Reserved06', ctypes.c_uint32 * 63), - ('OffsetInUpper', ctypes.c_uint32), - ('OffsetInLower', ctypes.c_uint32), - ('OffsetOutUpper', ctypes.c_uint32), - ('OffsetOutLower', ctypes.c_uint32), - ('PitchIn', ctypes.c_uint32), - ('PitchOut', ctypes.c_uint32), - ('LineLengthIn', ctypes.c_uint32), - ('LineCount', ctypes.c_uint32), - ('Reserved07', ctypes.c_uint32 * 56), - ('SetSecureCopyMode', ctypes.c_uint32), - ('SetDecryptIv0', ctypes.c_uint32), - ('SetDecryptIv1', ctypes.c_uint32), - ('SetDecryptIv2', ctypes.c_uint32), - ('Reserved_SetAESCounter', ctypes.c_uint32), - ('SetDecryptAuthTagCompareAddrUpper', ctypes.c_uint32), - ('SetDecryptAuthTagCompareAddrLower', ctypes.c_uint32), - ('Reserved08', ctypes.c_uint32 * 5), - ('SetEncryptAuthTagAddrUpper', ctypes.c_uint32), - ('SetEncryptAuthTagAddrLower', ctypes.c_uint32), - ('SetEncryptIvAddrUpper', ctypes.c_uint32), - ('SetEncryptIvAddrLower', ctypes.c_uint32), - ('Reserved09', ctypes.c_uint32 * 16), - ('SetCompressionParameters', ctypes.c_uint32), - ('SetDecompressOutLength', ctypes.c_uint32), - ('SetDecompressOutLengthAddrUpper', ctypes.c_uint32), - ('SetDecompressOutLengthAddrLower', ctypes.c_uint32), - ('SetDecompressChecksum', ctypes.c_uint32), - ('Reserved10', ctypes.c_uint32 * 90), - ('SetMemoryScrubParameters', ctypes.c_uint32), - ('SetRemapConstA', ctypes.c_uint32), - ('SetRemapConstB', ctypes.c_uint32), - ('SetRemapComponents', ctypes.c_uint32), - ('SetDstBlockSize', ctypes.c_uint32), - ('SetDstWidth', ctypes.c_uint32), - ('SetDstHeight', ctypes.c_uint32), - ('SetDstDepth', ctypes.c_uint32), - ('SetDstLayer', ctypes.c_uint32), - ('SetDstOrigin', ctypes.c_uint32), - ('Reserved11', ctypes.c_uint32 * 1), - ('SetSrcBlockSize', ctypes.c_uint32), - ('SetSrcWidth', ctypes.c_uint32), - ('SetSrcHeight', ctypes.c_uint32), - ('SetSrcDepth', ctypes.c_uint32), - ('SetSrcLayer', ctypes.c_uint32), - ('SetSrcOrigin', ctypes.c_uint32), - ('Reserved12', ctypes.c_uint32 * 1), - ('SrcOriginX', ctypes.c_uint32), - ('SrcOriginY', ctypes.c_uint32), - ('DstOriginX', ctypes.c_uint32), - ('DstOriginY', ctypes.c_uint32), - ('Reserved13', ctypes.c_uint32 * 624), - ('PmTriggerEnd', ctypes.c_uint32), - ('Reserved14', ctypes.c_uint32 * 954), -] - -blackwell_dma_copy_aControlPio = struct__clc9b5_tag0 -_UVM_IOCTL_H = True # macro -def UVM_IOCTL_BASE(i): # macro - return i -UVM_RESERVE_VA = UVM_IOCTL_BASE ( 1 ) # macro -UVM_RELEASE_VA = UVM_IOCTL_BASE ( 2 ) # macro -UVM_REGION_COMMIT = UVM_IOCTL_BASE ( 3 ) # macro -UVM_REGION_DECOMMIT = UVM_IOCTL_BASE ( 4 ) # macro -UVM_REGION_SET_STREAM = UVM_IOCTL_BASE ( 5 ) # macro -UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE ( 6 ) # macro -UVM_MAX_STREAMS_PER_IOCTL_CALL = 32 # macro -UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE ( 7 ) # macro -UVM_RUN_TEST = UVM_IOCTL_BASE ( 9 ) # macro -UVM_EVENTS_OFFSET_BASE = (1<<63) # macro -UVM_COUNTERS_OFFSET_BASE = (1<<62) # macro -UVM_ADD_SESSION = UVM_IOCTL_BASE ( 10 ) # macro -UVM_REMOVE_SESSION = UVM_IOCTL_BASE ( 11 ) # macro -UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32 # macro -UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE ( 12 ) # macro -UVM_MAP_COUNTER = UVM_IOCTL_BASE ( 13 ) # macro -UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE ( 14 ) # macro -UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE ( 15 ) # macro -UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE ( 16 ) # macro -UVM_EVENT_CTRL = UVM_IOCTL_BASE ( 17 ) # macro -UVM_REGISTER_MPS_SERVER = UVM_IOCTL_BASE ( 18 ) # macro -UVM_REGISTER_MPS_CLIENT = UVM_IOCTL_BASE ( 19 ) # macro -UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE ( 20 ) # macro -UVM_CREATE_RANGE_GROUP = UVM_IOCTL_BASE ( 23 ) # macro -UVM_DESTROY_RANGE_GROUP = UVM_IOCTL_BASE ( 24 ) # macro -UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE ( 25 ) # macro -UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE ( 26 ) # macro -UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE ( 27 ) # macro -UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE ( 28 ) # macro -UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE ( 29 ) # macro -UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE ( 30 ) # macro -UVM_SET_RANGE_GROUP = UVM_IOCTL_BASE ( 31 ) # macro -UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE ( 33 ) # macro -UVM_FREE = UVM_IOCTL_BASE ( 34 ) # macro -UVM_MEM_MAP = UVM_IOCTL_BASE ( 35 ) # macro -UVM_DEBUG_ACCESS_MEMORY = UVM_IOCTL_BASE ( 36 ) # macro -UVM_REGISTER_GPU = UVM_IOCTL_BASE ( 37 ) # macro -UVM_UNREGISTER_GPU = UVM_IOCTL_BASE ( 38 ) # macro -UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE ( 39 ) # macro -UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL = 32 # macro -UVM_PREVENT_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE ( 40 ) # macro -UVM_ALLOW_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE ( 41 ) # macro -UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE ( 42 ) # macro -UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE ( 43 ) # macro -UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE ( 44 ) # macro -UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE ( 45 ) # macro -UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE ( 46 ) # macro -UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE ( 47 ) # macro -UVM_MIGRATE_FLAG_ASYNC = 0x00000001 # macro -UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002 # macro -UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004 # macro -UVM_MIGRATE_FLAGS_TEST_ALL = (0x00000002|0x00000004) # macro -UVM_MIGRATE_FLAGS_ALL = (0x00000001|(0x00000002|0x00000004)) # macro -UVM_MIGRATE = UVM_IOCTL_BASE ( 51 ) # macro -UVM_MIGRATE_RANGE_GROUP = UVM_IOCTL_BASE ( 53 ) # macro -UVM_ENABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE ( 54 ) # macro -UVM_DISABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE ( 55 ) # macro -UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE ( 56 ) # macro -UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE ( 57 ) # macro -UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE ( 58 ) # macro -UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE ( 59 ) # macro -UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE ( 60 ) # macro -UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE ( 61 ) # macro -UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE ( 62 ) # macro -UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE ( 63 ) # macro -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE ( 64 ) # macro -UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE ( 65 ) # macro -UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE ( 66 ) # macro -UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE ( 67 ) # macro -UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE ( 68 ) # macro -UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE ( 69 ) # macro -UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE ( 70 ) # macro -UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE ( 71 ) # macro -UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001 # macro -UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002 # macro -UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL = (0x00000001|0x00000002) # macro -UVM_POPULATE_PAGEABLE_FLAGS_ALL = (0x00000001|0x00000002) # macro -UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE ( 72 ) # macro -UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE ( 73 ) # macro -UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE ( 74 ) # macro -UVM_MM_INITIALIZE = UVM_IOCTL_BASE ( 75 ) # macro -UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE ( 76 ) # macro -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE ( 77 ) # macro -UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE ( 78 ) # macro -UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE ( 79 ) # macro -UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE ( 2047 ) # macro -class struct_c__SA_UVM_RESERVE_VA_PARAMS(Structure): - pass - -struct_c__SA_UVM_RESERVE_VA_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RESERVE_VA_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_RESERVE_VA_PARAMS = struct_c__SA_UVM_RESERVE_VA_PARAMS -class struct_c__SA_UVM_RELEASE_VA_PARAMS(Structure): - pass - -struct_c__SA_UVM_RELEASE_VA_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RELEASE_VA_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_RELEASE_VA_PARAMS = struct_c__SA_UVM_RELEASE_VA_PARAMS -class struct_c__SA_UVM_REGION_COMMIT_PARAMS(Structure): - pass - -class struct_nv_uuid(Structure): - pass - -struct_nv_uuid._pack_ = 1 # source:False -struct_nv_uuid._fields_ = [ - ('uuid', ctypes.c_ubyte * 16), -] - -struct_c__SA_UVM_REGION_COMMIT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_COMMIT_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('streamId', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_COMMIT_PARAMS = struct_c__SA_UVM_REGION_COMMIT_PARAMS -class struct_c__SA_UVM_REGION_DECOMMIT_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGION_DECOMMIT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_DECOMMIT_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_DECOMMIT_PARAMS = struct_c__SA_UVM_REGION_DECOMMIT_PARAMS -class struct_c__SA_UVM_REGION_SET_STREAM_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGION_SET_STREAM_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_SET_STREAM_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('newStreamId', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_SET_STREAM_PARAMS = struct_c__SA_UVM_REGION_SET_STREAM_PARAMS -class struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS._fields_ = [ - ('streamId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_STREAM_RUNNING_PARAMS = struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS -class struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS._fields_ = [ - ('streamIdArray', ctypes.c_uint64 * 32), - ('nStreams', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_STREAM_STOPPED_PARAMS = struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS -class struct_c__SA_UVM_RUN_TEST_PARAMS(Structure): - pass - -class struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu(Structure): - pass - -struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu._pack_ = 1 # source:False -struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu._fields_ = [ - ('peerGpuUuid', struct_nv_uuid), - ('peerId', ctypes.c_uint32), -] - -struct_c__SA_UVM_RUN_TEST_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RUN_TEST_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('test', ctypes.c_uint32), - ('multiGpu', struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu), - ('rmStatus', ctypes.c_uint32), -] - -UVM_RUN_TEST_PARAMS = struct_c__SA_UVM_RUN_TEST_PARAMS -class struct_c__SA_UVM_ADD_SESSION_PARAMS(Structure): - pass - -struct_c__SA_UVM_ADD_SESSION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ADD_SESSION_PARAMS._fields_ = [ - ('pidTarget', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('countersBaseAddress', ctypes.POINTER(None)), - ('sessionIndex', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ADD_SESSION_PARAMS = struct_c__SA_UVM_ADD_SESSION_PARAMS -class struct_c__SA_UVM_REMOVE_SESSION_PARAMS(Structure): - pass - -struct_c__SA_UVM_REMOVE_SESSION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REMOVE_SESSION_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REMOVE_SESSION_PARAMS = struct_c__SA_UVM_REMOVE_SESSION_PARAMS -class struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS(Structure): - pass - -class struct_c__SA_UvmCounterConfig(Structure): - pass - -struct_c__SA_UvmCounterConfig._pack_ = 1 # source:False -struct_c__SA_UvmCounterConfig._fields_ = [ - ('scope', ctypes.c_uint32), - ('name', ctypes.c_uint32), - ('gpuid', struct_nv_uuid), - ('state', ctypes.c_uint32), -] - -struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('config', struct_c__SA_UvmCounterConfig * 32), - ('count', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_COUNTERS_PARAMS = struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_MAP_COUNTER_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_COUNTER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_COUNTER_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('scope', ctypes.c_uint32), - ('counterName', ctypes.c_uint32), - ('gpuUuid', struct_nv_uuid), - ('PADDING_0', ctypes.c_ubyte * 4), - ('addr', ctypes.POINTER(None)), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_MAP_COUNTER_PARAMS = struct_c__SA_UVM_MAP_COUNTER_PARAMS -class struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('queueSize', ctypes.c_uint64), - ('notificationCount', ctypes.c_uint64), - ('timeStampType', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_CREATE_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REMOVE_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('userRODataAddr', ctypes.POINTER(None)), - ('userRWDataAddr', ctypes.POINTER(None)), - ('readIndexAddr', ctypes.POINTER(None)), - ('writeIndexAddr', ctypes.POINTER(None)), - ('queueBufferAddr', ctypes.POINTER(None)), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_EVENT_CTRL_PARAMS(Structure): - pass - -struct_c__SA_UVM_EVENT_CTRL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_EVENT_CTRL_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('eventType', ctypes.c_int32), - ('enable', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_EVENT_CTRL_PARAMS = struct_c__SA_UVM_EVENT_CTRL_PARAMS -class struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS._fields_ = [ - ('gpuUuidArray', struct_nv_uuid * 32), - ('numGpus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('serverId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_MPS_SERVER_PARAMS = struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS -class struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS._fields_ = [ - ('serverId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_MPS_CLIENT_PARAMS = struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS -class struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS._fields_ = [ - ('gpuUuidArray', struct_nv_uuid * 32), - ('validCount', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_GET_GPU_UUID_TABLE_PARAMS = struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS -class struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_CREATE_RANGE_GROUP_PARAMS = struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_DESTROY_RANGE_GROUP_PARAMS = struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hVaSpace', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REGISTER_GPU_VASPACE_PARAMS = struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS -class struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_GPU_VASPACE_PARAMS = struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS -class struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_CHANNEL_PARAMS = struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS -class struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_CHANNEL_PARAMS = struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS -class struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS._fields_ = [ - ('gpuUuidA', struct_nv_uuid), - ('gpuUuidB', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_PEER_ACCESS_PARAMS = struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS -class struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS._fields_ = [ - ('gpuUuidA', struct_nv_uuid), - ('gpuUuidB', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_DISABLE_PEER_ACCESS_PARAMS = struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS -class struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_RANGE_GROUP_PARAMS = struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(Structure): - pass - -class struct_c__SA_UvmGpuMappingAttributes(Structure): - pass - -struct_c__SA_UvmGpuMappingAttributes._pack_ = 1 # source:False -struct_c__SA_UvmGpuMappingAttributes._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('gpuMappingType', ctypes.c_uint32), - ('gpuCachingType', ctypes.c_uint32), - ('gpuFormatType', ctypes.c_uint32), - ('gpuElementBits', ctypes.c_uint32), - ('gpuCompressionType', ctypes.c_uint32), -] - -struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('perGpuAttributes', struct_c__SA_UvmGpuMappingAttributes * 256), - ('gpuAttributesCount', ctypes.c_uint64), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_MAP_EXTERNAL_ALLOCATION_PARAMS = struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS -class struct_c__SA_UVM_FREE_PARAMS(Structure): - pass - -struct_c__SA_UVM_FREE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_FREE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_FREE_PARAMS = struct_c__SA_UVM_FREE_PARAMS -class struct_c__SA_UVM_MEM_MAP_PARAMS(Structure): - pass - -struct_c__SA_UVM_MEM_MAP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MEM_MAP_PARAMS._fields_ = [ - ('regionBase', ctypes.POINTER(None)), - ('regionLength', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MEM_MAP_PARAMS = struct_c__SA_UVM_MEM_MAP_PARAMS -class struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('baseAddress', ctypes.c_uint64), - ('sizeInBytes', ctypes.c_uint64), - ('accessType', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('buffer', ctypes.c_uint64), - ('isBitmaskSet', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), - ('bitmask', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -UVM_DEBUG_ACCESS_MEMORY_PARAMS = struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS -class struct_c__SA_UVM_REGISTER_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('numaEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numaNodeId', ctypes.c_int32), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hSmcPartRef', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REGISTER_GPU_PARAMS = struct_c__SA_UVM_REGISTER_GPU_PARAMS -class struct_c__SA_UVM_UNREGISTER_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_GPU_PARAMS = struct_c__SA_UVM_UNREGISTER_GPU_PARAMS -class struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS._fields_ = [ - ('pageableMemAccess', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rmStatus', ctypes.c_uint32), -] - -UVM_PAGEABLE_MEM_ACCESS_PARAMS = struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS -class struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS(Structure): - pass - -struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ - ('rangeGroupIds', ctypes.c_uint64 * 32), - ('numGroupIds', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS = struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS -class struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ - ('rangeGroupIds', ctypes.c_uint64 * 32), - ('numGroupIds', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS = struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS -class struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('preferredLocation', struct_nv_uuid), - ('preferredCpuNumaNode', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_SET_PREFERRED_LOCATION_PARAMS = struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS -class struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNSET_PREFERRED_LOCATION_PARAMS = struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS -class struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ENABLE_READ_DUPLICATION_PARAMS = struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS -class struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_DISABLE_READ_DUPLICATION_PARAMS = struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS -class struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('accessedByUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_ACCESSED_BY_PARAMS = struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS -class struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('accessedByUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNSET_ACCESSED_BY_PARAMS = struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS -class struct_c__SA_UVM_MIGRATE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MIGRATE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MIGRATE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('destinationUuid', struct_nv_uuid), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('semaphoreAddress', ctypes.c_uint64), - ('semaphorePayload', ctypes.c_uint32), - ('cpuNumaNode', ctypes.c_int32), - ('userSpaceStart', ctypes.c_uint64), - ('userSpaceLength', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_MIGRATE_PARAMS = struct_c__SA_UVM_MIGRATE_PARAMS -class struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('destinationUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MIGRATE_RANGE_GROUP_PARAMS = struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS = struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS -class struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS = struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS -class struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._fields_ = [ - ('queueBuffer', ctypes.c_uint64), - ('queueBufferSize', ctypes.c_uint64), - ('controlBuffer', ctypes.c_uint64), - ('processor', struct_nv_uuid), - ('allProcessors', ctypes.c_uint32), - ('uvmFd', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS = struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS -class struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._fields_ = [ - ('notificationThreshold', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS = struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS -class struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._fields_ = [ - ('eventTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS -class struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._fields_ = [ - ('eventTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS -class struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS._fields_ = [ - ('counterTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_ENABLE_COUNTERS_PARAMS = struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS._fields_ = [ - ('counterTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_DISABLE_COUNTERS_PARAMS = struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._fields_ = [ - ('buffer', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('targetVa', ctypes.c_uint64), - ('bytesRead', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS = struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS -class struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._fields_ = [ - ('buffer', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('targetVa', ctypes.c_uint64), - ('bytesWritten', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS = struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS -class struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._fields_ = [ - ('tablePtr', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS = struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS -class struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS = struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS -class struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNMAP_EXTERNAL_PARAMS = struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS -class struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_TOOLS_FLUSH_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS -class struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('perGpuAttributes', struct_c__SA_UvmGpuMappingAttributes * 256), - ('gpuAttributesCount', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ALLOC_SEMAPHORE_POOL_PARAMS = struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS -class struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(Structure): - pass - -struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS = struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS -class struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('pageableMemAccess', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rmStatus', ctypes.c_uint32), -] - -UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS = struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS -class struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_POPULATE_PAGEABLE_PARAMS = struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS -class struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS(Structure): - pass - -struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_VALIDATE_VA_RANGE_PARAMS = struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS -class struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_CREATE_EXTERNAL_RANGE_PARAMS = struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS -class struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_EXTERNAL_SPARSE_PARAMS = struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS -class struct_c__SA_UVM_MM_INITIALIZE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MM_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MM_INITIALIZE_PARAMS._fields_ = [ - ('uvmFd', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_MM_INITIALIZE_PARAMS = struct_c__SA_UVM_MM_INITIALIZE_PARAMS -UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS = struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS = struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS -class struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ALLOC_DEVICE_P2P_PARAMS = struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS -class struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS = struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS -class struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS(Structure): - pass - -struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS._fields_ = [ - ('is8Supported', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_IS_8_SUPPORTED_PARAMS = struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS -_UVM_LINUX_IOCTL_H = True # macro -UVM_INITIALIZE = 0x30000001 # macro -UVM_DEINITIALIZE = 0x30000002 # macro -class struct_c__SA_UVM_INITIALIZE_PARAMS(Structure): - pass - -struct_c__SA_UVM_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_INITIALIZE_PARAMS._fields_ = [ - ('flags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_INITIALIZE_PARAMS = struct_c__SA_UVM_INITIALIZE_PARAMS -__ga100_dev_fault_h__ = True # macro -NV_PFAULT = True # macro -NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64 # macro -NV_PFAULT_MMU_ENG_ID_DISPLAY = 1 # macro -NV_PFAULT_MMU_ENG_ID_GSP = 2 # macro -NV_PFAULT_MMU_ENG_ID_IFB = 9 # macro -NV_PFAULT_MMU_ENG_ID_FLA = 4 # macro -NV_PFAULT_MMU_ENG_ID_BAR1 = 128 # macro -NV_PFAULT_MMU_ENG_ID_BAR2 = 192 # macro -NV_PFAULT_MMU_ENG_ID_SEC = 14 # macro -NV_PFAULT_MMU_ENG_ID_PERF = 8 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC = 25 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29 # macro -NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30 # macro -NV_PFAULT_MMU_ENG_ID_GRCOPY = 15 # macro -NV_PFAULT_MMU_ENG_ID_CE0 = 15 # macro -NV_PFAULT_MMU_ENG_ID_CE1 = 16 # macro -NV_PFAULT_MMU_ENG_ID_CE2 = 17 # macro -NV_PFAULT_MMU_ENG_ID_CE3 = 18 # macro -NV_PFAULT_MMU_ENG_ID_CE4 = 19 # macro -NV_PFAULT_MMU_ENG_ID_CE5 = 20 # macro -NV_PFAULT_MMU_ENG_ID_CE6 = 21 # macro -NV_PFAULT_MMU_ENG_ID_CE7 = 22 # macro -NV_PFAULT_MMU_ENG_ID_CE8 = 23 # macro -NV_PFAULT_MMU_ENG_ID_CE9 = 24 # macro -NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6 # macro -NV_PFAULT_MMU_ENG_ID_PTP = 3 # macro -NV_PFAULT_MMU_ENG_ID_NVENC0 = 11 # macro -NV_PFAULT_MMU_ENG_ID_NVENC1 = 12 # macro -NV_PFAULT_MMU_ENG_ID_NVENC2 = 13 # macro -NV_PFAULT_MMU_ENG_ID_OFA0 = 10 # macro -NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31 # macro -NV_PFAULT_MMU_ENG_ID_HOST0 = 32 # macro -NV_PFAULT_MMU_ENG_ID_HOST1 = 33 # macro -NV_PFAULT_MMU_ENG_ID_HOST2 = 34 # macro -NV_PFAULT_MMU_ENG_ID_HOST3 = 35 # macro -NV_PFAULT_MMU_ENG_ID_HOST4 = 36 # macro -NV_PFAULT_MMU_ENG_ID_HOST5 = 37 # macro -NV_PFAULT_MMU_ENG_ID_HOST6 = 38 # macro -NV_PFAULT_MMU_ENG_ID_HOST7 = 39 # macro -NV_PFAULT_MMU_ENG_ID_HOST8 = 40 # macro -NV_PFAULT_MMU_ENG_ID_HOST9 = 41 # macro -NV_PFAULT_MMU_ENG_ID_HOST10 = 42 # macro -NV_PFAULT_MMU_ENG_ID_HOST11 = 43 # macro -NV_PFAULT_MMU_ENG_ID_HOST12 = 44 # macro -NV_PFAULT_MMU_ENG_ID_HOST13 = 45 # macro -NV_PFAULT_MMU_ENG_ID_HOST14 = 46 # macro -NV_PFAULT_MMU_ENG_ID_HOST15 = 47 # macro -NV_PFAULT_MMU_ENG_ID_HOST16 = 48 # macro -NV_PFAULT_MMU_ENG_ID_HOST17 = 49 # macro -NV_PFAULT_MMU_ENG_ID_HOST18 = 50 # macro -NV_PFAULT_MMU_ENG_ID_HOST19 = 51 # macro -NV_PFAULT_MMU_ENG_ID_HOST20 = 52 # macro -NV_PFAULT_MMU_ENG_ID_HOST21 = 53 # macro -NV_PFAULT_MMU_ENG_ID_HOST22 = 54 # macro -NV_PFAULT_MMU_ENG_ID_HOST23 = 55 # macro -NV_PFAULT_MMU_ENG_ID_HOST24 = 56 # macro -NV_PFAULT_MMU_ENG_ID_HOST25 = 57 # macro -NV_PFAULT_MMU_ENG_ID_HOST26 = 58 # macro -NV_PFAULT_MMU_ENG_ID_HOST27 = 59 # macro -NV_PFAULT_MMU_ENG_ID_HOST28 = 60 # macro -NV_PFAULT_MMU_ENG_ID_HOST29 = 61 # macro -NV_PFAULT_MMU_ENG_ID_HOST30 = 62 # macro -NV_PFAULT_MMU_ENG_ID_HOST31 = 63 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255 # macro -# NV_PFAULT_FAULT_TYPE = 4 : 0 # macro -NV_PFAULT_FAULT_TYPE_PDE = 0x00000000 # macro -NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001 # macro -NV_PFAULT_FAULT_TYPE_PTE = 0x00000002 # macro -NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003 # macro -NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004 # macro -NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005 # macro -NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006 # macro -NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007 # macro -NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008 # macro -NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009 # macro -NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a # macro -NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b # macro -NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c # macro -NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d # macro -NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e # macro -NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f # macro -# NV_PFAULT_CLIENT = 14 : 8 # macro -NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000 # macro -NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001 # macro -NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002 # macro -NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003 # macro -NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004 # macro -NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005 # macro -NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006 # macro -NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007 # macro -NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008 # macro -NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009 # macro -NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A # macro -NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B # macro -NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C # macro -NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D # macro -NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E # macro -NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F # macro -NV_PFAULT_CLIENT_GPC_RAST = 0x00000010 # macro -NV_PFAULT_CLIENT_GPC_GCC = 0x00000011 # macro -NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012 # macro -NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013 # macro -NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014 # macro -NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015 # macro -NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016 # macro -NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021 # macro -NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022 # macro -NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023 # macro -NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024 # macro -NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025 # macro -NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026 # macro -NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027 # macro -NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C # macro -NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D # macro -NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E # macro -NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F # macro -NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030 # macro -NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031 # macro -NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034 # macro -NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035 # macro -NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036 # macro -NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037 # macro -NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038 # macro -NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039 # macro -NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C # macro -NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D # macro -NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E # macro -NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F # macro -NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040 # macro -NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041 # macro -NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044 # macro -NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045 # macro -NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046 # macro -NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047 # macro -NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048 # macro -NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049 # macro -NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C # macro -NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D # macro -NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E # macro -NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F # macro -NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050 # macro -NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051 # macro -NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054 # macro -NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055 # macro -NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056 # macro -NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057 # macro -NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058 # macro -NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059 # macro -NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C # macro -NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D # macro -NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E # macro -NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F # macro -NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060 # macro -NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070 # macro -NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071 # macro -NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072 # macro -NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073 # macro -NV_PFAULT_CLIENT_GPC_GPM = 0x00000017 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F # macro -NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038 # macro -NV_PFAULT_CLIENT_HUB_VIP = 0x00000000 # macro -NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001 # macro -NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002 # macro -NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003 # macro -NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003 # macro -NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004 # macro -NV_PFAULT_CLIENT_HUB_FE = 0x00000004 # macro -NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005 # macro -NV_PFAULT_CLIENT_HUB_FECS = 0x00000005 # macro -NV_PFAULT_CLIENT_HUB_HOST = 0x00000006 # macro -NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007 # macro -NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008 # macro -NV_PFAULT_CLIENT_HUB_ISO = 0x00000009 # macro -NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A # macro -NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B # macro -NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B # macro -NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D # macro -NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E # macro -NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E # macro -NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F # macro -NV_PFAULT_CLIENT_HUB_PD = 0x00000010 # macro -NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011 # macro -NV_PFAULT_CLIENT_HUB_PERF = 0x00000011 # macro -NV_PFAULT_CLIENT_HUB_PMU = 0x00000012 # macro -NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013 # macro -NV_PFAULT_CLIENT_HUB_SCC = 0x00000014 # macro -NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015 # macro -NV_PFAULT_CLIENT_HUB_SEC = 0x00000016 # macro -NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017 # macro -NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018 # macro -NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018 # macro -NV_PFAULT_CLIENT_HUB_XV = 0x00000019 # macro -NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A # macro -NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B # macro -NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B # macro -NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C # macro -NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D # macro -NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D # macro -NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E # macro -NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F # macro -NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020 # macro -NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021 # macro -NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022 # macro -NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023 # macro -NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024 # macro -NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025 # macro -NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026 # macro -NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027 # macro -NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028 # macro -NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029 # macro -NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A # macro -NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B # macro -NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C # macro -NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D # macro -NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E # macro -NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F # macro -NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030 # macro -NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031 # macro -NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032 # macro -NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033 # macro -NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034 # macro -NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035 # macro -NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036 # macro -NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037 # macro -NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038 # macro -NV_PFAULT_CLIENT_HUB_GSP = 0x00000039 # macro -NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A # macro -NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B # macro -NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C # macro -NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D # macro -NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E # macro -NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F # macro -NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040 # macro -NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041 # macro -NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042 # macro -NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043 # macro -NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044 # macro -NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045 # macro -NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046 # macro -NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047 # macro -NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048 # macro -NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049 # macro -NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A # macro -NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B # macro -NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C # macro -NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D # macro -NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E # macro -NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F # macro -NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050 # macro -NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051 # macro -NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052 # macro -NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053 # macro -NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054 # macro -NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055 # macro -NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056 # macro -NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057 # macro -NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058 # macro -NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059 # macro -NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A # macro -NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B # macro -NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C # macro -NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D # macro -NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E # macro -NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F # macro -NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060 # macro -NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061 # macro -NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062 # macro -NV_PFAULT_CLIENT_HUB_ESC = 0x00000063 # macro -# NV_PFAULT_ACCESS_TYPE = 19 : 16 # macro -NV_PFAULT_ACCESS_TYPE_READ = 0x00000000 # macro -NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001 # macro -NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a # macro -NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b # macro -# NV_PFAULT_MMU_CLIENT_TYPE = 20 : 20 # macro -NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000 # macro -NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001 # macro -# NV_PFAULT_GPC_ID = 28 : 24 # macro -# NV_PFAULT_PROTECTED_MODE = 29 : 29 # macro -# NV_PFAULT_REPLAYABLE_FAULT_EN = 30 : 30 # macro -# NV_PFAULT_VALID = 31 : 31 # macro -NV_ESCAPE_H_INCLUDED = True # macro -NV_ESC_RM_ALLOC_MEMORY = 0x27 # macro -NV_ESC_RM_ALLOC_OBJECT = 0x28 # macro -NV_ESC_RM_FREE = 0x29 # macro -NV_ESC_RM_CONTROL = 0x2A # macro -NV_ESC_RM_ALLOC = 0x2B # macro -NV_ESC_RM_CONFIG_GET = 0x32 # macro -NV_ESC_RM_CONFIG_SET = 0x33 # macro -NV_ESC_RM_DUP_OBJECT = 0x34 # macro -NV_ESC_RM_SHARE = 0x35 # macro -NV_ESC_RM_CONFIG_GET_EX = 0x37 # macro -NV_ESC_RM_CONFIG_SET_EX = 0x38 # macro -NV_ESC_RM_I2C_ACCESS = 0x39 # macro -NV_ESC_RM_IDLE_CHANNELS = 0x41 # macro -NV_ESC_RM_VID_HEAP_CONTROL = 0x4A # macro -NV_ESC_RM_ACCESS_REGISTRY = 0x4D # macro -NV_ESC_RM_MAP_MEMORY = 0x4E # macro -NV_ESC_RM_UNMAP_MEMORY = 0x4F # macro -NV_ESC_RM_GET_EVENT_DATA = 0x52 # macro -NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54 # macro -NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56 # macro -NV_ESC_RM_MAP_MEMORY_DMA = 0x57 # macro -NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58 # macro -NV_ESC_RM_BIND_CONTEXT_DMA = 0x59 # macro -NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C # macro -NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D # macro -NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E # macro -NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F # macro -NV_IOCTL_H = True # macro -NV_RM_API_VERSION_STRING_LENGTH = 64 # macro -NV_RM_API_VERSION_CMD_STRICT = 0 # macro -NV_RM_API_VERSION_CMD_RELAXED = '1' # macro -NV_RM_API_VERSION_CMD_QUERY = '2' # macro -NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0 # macro -NV_RM_API_VERSION_REPLY_RECOGNIZED = 1 # macro -NV_DMABUF_EXPORT_MAX_HANDLES = 128 # macro -NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0 # macro -NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1 # macro -class struct_c__SA_nv_pci_info_t(Structure): - pass - -struct_c__SA_nv_pci_info_t._pack_ = 1 # source:False -struct_c__SA_nv_pci_info_t._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('function', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('vendor_id', ctypes.c_uint16), - ('device_id', ctypes.c_uint16), -] - -nv_pci_info_t = struct_c__SA_nv_pci_info_t -class struct_nv_ioctl_xfer(Structure): - pass - -struct_nv_ioctl_xfer._pack_ = 1 # source:False -struct_nv_ioctl_xfer._fields_ = [ - ('cmd', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('ptr', ctypes.POINTER(None)), -] - -nv_ioctl_xfer_t = struct_nv_ioctl_xfer -class struct_nv_ioctl_card_info(Structure): - pass - -struct_nv_ioctl_card_info._pack_ = 1 # source:False -struct_nv_ioctl_card_info._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pci_info', nv_pci_info_t), - ('gpu_id', ctypes.c_uint32), - ('interrupt_line', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('reg_address', ctypes.c_uint64), - ('reg_size', ctypes.c_uint64), - ('fb_address', ctypes.c_uint64), - ('fb_size', ctypes.c_uint64), - ('minor_number', ctypes.c_uint32), - ('dev_name', ctypes.c_ubyte * 10), - ('PADDING_2', ctypes.c_ubyte * 2), -] - -nv_ioctl_card_info_t = struct_nv_ioctl_card_info -class struct_nv_ioctl_alloc_os_event(Structure): - pass - -struct_nv_ioctl_alloc_os_event._pack_ = 1 # source:False -struct_nv_ioctl_alloc_os_event._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('fd', ctypes.c_uint32), - ('Status', ctypes.c_uint32), -] - -nv_ioctl_alloc_os_event_t = struct_nv_ioctl_alloc_os_event -class struct_nv_ioctl_free_os_event(Structure): - pass - -struct_nv_ioctl_free_os_event._pack_ = 1 # source:False -struct_nv_ioctl_free_os_event._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('fd', ctypes.c_uint32), - ('Status', ctypes.c_uint32), -] - -nv_ioctl_free_os_event_t = struct_nv_ioctl_free_os_event -class struct_nv_ioctl_status_code(Structure): - pass - -struct_nv_ioctl_status_code._pack_ = 1 # source:False -struct_nv_ioctl_status_code._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), -] - -nv_ioctl_status_code_t = struct_nv_ioctl_status_code -class struct_nv_ioctl_rm_api_version(Structure): - pass - -struct_nv_ioctl_rm_api_version._pack_ = 1 # source:False -struct_nv_ioctl_rm_api_version._fields_ = [ - ('cmd', ctypes.c_uint32), - ('reply', ctypes.c_uint32), - ('versionString', ctypes.c_char * 64), -] - -nv_ioctl_rm_api_version_t = struct_nv_ioctl_rm_api_version -class struct_nv_ioctl_query_device_intr(Structure): - pass - -struct_nv_ioctl_query_device_intr._pack_ = 1 # source:False -struct_nv_ioctl_query_device_intr._fields_ = [ - ('intrStatus', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -nv_ioctl_query_device_intr = struct_nv_ioctl_query_device_intr -class struct_nv_ioctl_sys_params(Structure): - pass - -struct_nv_ioctl_sys_params._pack_ = 1 # source:False -struct_nv_ioctl_sys_params._fields_ = [ - ('memblock_size', ctypes.c_uint64), -] - -nv_ioctl_sys_params_t = struct_nv_ioctl_sys_params -class struct_nv_ioctl_register_fd(Structure): - pass - -struct_nv_ioctl_register_fd._pack_ = 1 # source:False -struct_nv_ioctl_register_fd._fields_ = [ - ('ctl_fd', ctypes.c_int32), -] - -nv_ioctl_register_fd_t = struct_nv_ioctl_register_fd -class struct_nv_ioctl_export_to_dma_buf_fd(Structure): - pass - -struct_nv_ioctl_export_to_dma_buf_fd._pack_ = 1 # source:False -struct_nv_ioctl_export_to_dma_buf_fd._fields_ = [ - ('fd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('totalObjects', ctypes.c_uint32), - ('numObjects', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalSize', ctypes.c_uint64), - ('mappingType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('handles', ctypes.c_uint32 * 128), - ('PADDING_2', ctypes.c_ubyte * 4), - ('offsets', ctypes.c_uint64 * 128), - ('sizes', ctypes.c_uint64 * 128), - ('status', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -nv_ioctl_export_to_dma_buf_fd_t = struct_nv_ioctl_export_to_dma_buf_fd -class struct_nv_ioctl_wait_open_complete(Structure): - pass - -struct_nv_ioctl_wait_open_complete._pack_ = 1 # source:False -struct_nv_ioctl_wait_open_complete._fields_ = [ - ('rc', ctypes.c_int32), - ('adapterStatus', ctypes.c_uint32), -] - -nv_ioctl_wait_open_complete_t = struct_nv_ioctl_wait_open_complete -NV_IOCTL_NUMBERS_H = True # macro -NV_IOCTL_MAGIC = 'F' # macro -NV_IOCTL_BASE = 200 # macro -NV_ESC_CARD_INFO = (200+0) # macro -NV_ESC_REGISTER_FD = (200+1) # macro -NV_ESC_ALLOC_OS_EVENT = (200+6) # macro -NV_ESC_FREE_OS_EVENT = (200+7) # macro -NV_ESC_STATUS_CODE = (200+9) # macro -NV_ESC_CHECK_VERSION_STR = (200+10) # macro -NV_ESC_IOCTL_XFER_CMD = (200+11) # macro -NV_ESC_ATTACH_GPUS_TO_FD = (200+12) # macro -NV_ESC_QUERY_DEVICE_INTR = (200+13) # macro -NV_ESC_SYS_PARAMS = (200+14) # macro -NV_ESC_EXPORT_TO_DMABUF_FD = (200+17) # macro -NV_ESC_WAIT_OPEN_COMPLETE = (200+18) # macro -NV_IOCTL_NUMA_H = True # macro -# def __aligned(n): # macro -# return ((aligned(n))) -NV_ESC_NUMA_INFO = (200+15) # macro -NV_ESC_SET_NUMA_STATUS = (200+16) # macro -NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # macro -NV_IOCTL_NUMA_STATUS_DISABLED = 0 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE = 1 # macro -NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2 # macro -NV_IOCTL_NUMA_STATUS_ONLINE = 3 # macro -NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6 # macro -class struct_offline_addresses(Structure): - pass - -struct_offline_addresses._pack_ = 1 # source:False -struct_offline_addresses._fields_ = [ - ('addresses', ctypes.c_uint64 * 64), - ('numEntries', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -nv_offline_addresses_t = struct_offline_addresses -class struct_nv_ioctl_numa_info(Structure): - pass - -struct_nv_ioctl_numa_info._pack_ = 1 # source:False -struct_nv_ioctl_numa_info._fields_ = [ - ('nid', ctypes.c_int32), - ('status', ctypes.c_int32), - ('memblock_size', ctypes.c_uint64), - ('numa_mem_addr', ctypes.c_uint64), - ('numa_mem_size', ctypes.c_uint64), - ('use_auto_online', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('offline_addresses', nv_offline_addresses_t), -] - -nv_ioctl_numa_info_t = struct_nv_ioctl_numa_info -class struct_nv_ioctl_set_numa_status(Structure): - pass - -struct_nv_ioctl_set_numa_status._pack_ = 1 # source:False -struct_nv_ioctl_set_numa_status._fields_ = [ - ('status', ctypes.c_int32), -] - -nv_ioctl_set_numa_status_t = struct_nv_ioctl_set_numa_status -_NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ = True # macro -NVOS_INCLUDED = True # macro -# NVOS04_FLAGS_CHANNEL_TYPE = 1 : 0 # macro -NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001 # macro -NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002 # macro -# NVOS04_FLAGS_VPR = 2 : 2 # macro -NVOS04_FLAGS_VPR_FALSE = 0x00000000 # macro -NVOS04_FLAGS_VPR_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CC_SECURE = 2 : 2 # macro -NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING = 3 : 3 # macro -NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE = 4 : 4 # macro -NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000 # macro -NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001 # macro -# NVOS04_FLAGS_PRIVILEGED_CHANNEL = 5 : 5 # macro -NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING = 6 : 6 # macro -NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000 # macro -NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE = 7 : 7 # macro -NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE = 10 : 8 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED = 11 : 11 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE = 20 : 12 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED = 21 : 21 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV = 22 : 22 # macro -NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER = 23 : 23 # macro -NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO = 24 : 24 # macro -NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL = 25 : 25 # macro -NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT = 26 : 26 # macro -NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT = 27 : 27 # macro -NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_GROUP_CHANNEL_THREAD = 29 : 28 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002 # macro -# NVOS04_FLAGS_MAP_CHANNEL = 30 : 30 # macro -NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC = 31 : 31 # macro -NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000 # macro -NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001 # macro -CC_CHAN_ALLOC_IV_SIZE_DWORD = 3 # macro -CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8 # macro -NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f) # macro -FILE_DEVICE_NV = 0x00008000 # macro -NV_IOCTL_FCT_BASE = 0x00000800 # macro -NVOS_MAX_SUBDEVICES = 8 # macro -UNIFIED_NV_STATUS = 1 # macro -# NVOS_STATUS = NV_STATUS # macro -# NVOS_STATUS_SUCCESS = NV_OK # macro -# NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT # macro -# NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE # macro -# NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC # macro -# NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER # macro -# NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION # macro -# NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES # macro -# NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE # macro -# NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT # macro -# NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE # macro -# NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL # macro -# NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS # macro -# NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT # macro -# NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND # macro -# NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA # macro -# NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE # macro -# NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER # macro -# NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT # macro -# NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS # macro -# NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION # macro -# NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP # macro -# NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX # macro -# NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT # macro -# NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT # macro -# NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET # macro -# NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER # macro -# NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT # macro -# NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER # macro -# NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER # macro -# NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY # macro -# NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE # macro -# NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH # macro -# NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE # macro -# NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING # macro -# NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES # macro -# NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED # macro -# NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM # macro -# NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH # macro -# NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT # macro -# NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT # macro -# NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES # macro -# NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED # macro -# NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION # macro -# NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE # macro -# NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS # macro -# NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY # macro -# NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY # macro -# NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST # macro -# NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET # macro -# NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE # macro -# NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS # macro -# NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL # macro -# NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED # macro -# NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER # macro -# NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND # macro -# NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST # macro -# NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL # macro -# NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED # macro -# NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST # macro -# NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION # macro -# NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE # macro -# NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED # macro -NV01_FREE = (0x00000000) # macro -NV01_ROOT_USER = (0x00000041) # macro -NV01_ALLOC_MEMORY = (0x00000002) # macro -# NVOS02_FLAGS_PHYSICALITY = 7 : 4 # macro -NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000) # macro -NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001) # macro -# NVOS02_FLAGS_LOCATION = 11 : 8 # macro -NVOS02_FLAGS_LOCATION_PCI = (0x00000000) # macro -NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002) # macro -# NVOS02_FLAGS_COHERENCY = 15 : 12 # macro -NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000) # macro -NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001) # macro -NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002) # macro -NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003) # macro -NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004) # macro -NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005) # macro -# NVOS02_FLAGS_ALLOC = 17 : 16 # macro -NVOS02_FLAGS_ALLOC_NONE = (0x00000001) # macro -# NVOS02_FLAGS_GPU_CACHEABLE = 18 : 18 # macro -NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000) # macro -NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001) # macro -# NVOS02_FLAGS_KERNEL_MAPPING = 19 : 19 # macro -NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000) # macro -NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_NISO_DISPLAY = 20 : 20 # macro -NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_USER_READ_ONLY = 21 : 21 # macro -NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY = 22 : 22 # macro -NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001) # macro -# NVOS02_FLAGS_PEER_MAP_OVERRIDE = 23 : 23 # macro -NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT = 24 : 24 # macro -NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001) # macro -# NVOS02_FLAGS_MEMORY_PROTECTION = 26 : 25 # macro -NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001) # macro -NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002) # macro -# NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM = 27 : 27 # macro -NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000) # macro -NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001) # macro -# NVOS02_FLAGS_MAPPING = 31 : 30 # macro -NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001) # macro -NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002) # macro -# NVOS03_FLAGS_ACCESS = 1 : 0 # macro -NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS03_FLAGS_PREALLOCATE = 2 : 2 # macro -NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000) # macro -NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001) # macro -# NVOS03_FLAGS_GPU_MAPPABLE = 15 : 15 # macro -NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000) # macro -NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001) # macro -# NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE = 16 : 16 # macro -NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000) # macro -NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001) # macro -# NVOS03_FLAGS_PTE_KIND = 17 : 16 # macro -NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000) # macro -NVOS03_FLAGS_PTE_KIND_BL = (0x00000001) # macro -NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002) # macro -# NVOS03_FLAGS_TYPE = 23 : 20 # macro -NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001) # macro -# NVOS03_FLAGS_MAPPING = 20 : 20 # macro -NVOS03_FLAGS_MAPPING_NONE = (0x00000000) # macro -NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001) # macro -# NVOS03_FLAGS_CACHE_SNOOP = 28 : 28 # macro -NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000) # macro -NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001) # macro -# NVOS03_FLAGS_HASH_TABLE = 29 : 29 # macro -NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000) # macro -NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001) # macro -NV01_ALLOC_OBJECT = (0x00000005) # macro -NV01_EVENT_BROADCAST = (0x80000000) # macro -NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000) # macro -NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000) # macro -NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000) # macro -NV01_EVENT_NONSTALL_INTR = (0x08000000) # macro -NV01_EVENT_CLIENT_RM = (0x04000000) # macro -NV04_I2C_ACCESS = (0x00000013) # macro -NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048 # macro -NVOS20_COMMAND_unused0001 = 0x0001 # macro -NVOS20_COMMAND_unused0002 = 0x0002 # macro -NVOS20_COMMAND_STRING_PRINT = 0x0003 # macro -NV04_ALLOC = (0x00000015) # macro -NVOS64_FLAGS_NONE = (0x00000000) # macro -NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001) # macro -NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E # macro -NV04_IDLE_CHANNELS = (0x0000001E) # macro -# NVOS30_FLAGS_BEHAVIOR = 3 : 0 # macro -NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000) # macro -NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001) # macro -NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002) # macro -NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003) # macro -# NVOS30_FLAGS_CHANNEL = 7 : 4 # macro -NVOS30_FLAGS_CHANNEL_LIST = (0x00000000) # macro -NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001) # macro -# NVOS30_FLAGS_IDLE = 30 : 8 # macro -NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001) # macro -NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002) # macro -NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004) # macro -NVOS30_FLAGS_IDLE_MPEG = (0x00000008) # macro -NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010) # macro -NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020) # macro -NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020) # macro -NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040) # macro -NVOS30_FLAGS_IDLE_MSVLD = (0x00000040) # macro -NVOS30_FLAGS_IDLE_NVDEC0 = (0x00000040) # macro -NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080) # macro -NVOS30_FLAGS_IDLE_SEC = (0x00000080) # macro -NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100) # macro -NVOS30_FLAGS_IDLE_MSPPP = (0x00000200) # macro -NVOS30_FLAGS_IDLE_CE0 = (0x00000400) # macro -NVOS30_FLAGS_IDLE_CE1 = (0x00000800) # macro -NVOS30_FLAGS_IDLE_CE2 = (0x00001000) # macro -NVOS30_FLAGS_IDLE_CE3 = (0x00002000) # macro -NVOS30_FLAGS_IDLE_CE4 = (0x00004000) # macro -NVOS30_FLAGS_IDLE_CE5 = (0x00008000) # macro -NVOS30_FLAGS_IDLE_VIC = (0x00010000) # macro -NVOS30_FLAGS_IDLE_MSENC = (0x00020000) # macro -NVOS30_FLAGS_IDLE_NVENC0 = (0x00020000) # macro -NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000) # macro -NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000) # macro -NVOS30_FLAGS_IDLE_NVJPG = (0x00100000) # macro -NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000) # macro -NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000) # macro -NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000) # macro -NVOS30_FLAGS_IDLE_ALL_ENGINES = ((0x00000004)|(0x00000008)|(0x00000010)|(0x00000020)|(0x00000040)|(0x00000080)|(0x00000020)|(0x00000040)|(0x00000080)|(0x00000200)|(0x00000400)|(0x00000800)|(0x00001000)|(0x00002000)|(0x00004000)|(0x00008000)|(0x00020000)|(0x00040000)|(0x00080000)|(0x00010000)|(0x00100000)|(0x00200000)|(0x00400000)) # macro -# NVOS30_FLAGS_WAIT_FOR_ELPG_ON = 31 : 31 # macro -NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000) # macro -NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001) # macro -NV04_VID_HEAP_CONTROL = (0x00000020) # macro -NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0 # macro -NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1 # macro -NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2 # macro -NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3 # macro -NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4 # macro -NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5 # macro -NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6 # macro -NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7 # macro -NVOS32_FUNCTION_ALLOC_SIZE = 2 # macro -NVOS32_FUNCTION_FREE = 3 # macro -NVOS32_FUNCTION_INFO = 5 # macro -NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6 # macro -NVOS32_FUNCTION_DUMP = 11 # macro -NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14 # macro -NVOS32_FUNCTION_REACQUIRE_COMPR = 15 # macro -NVOS32_FUNCTION_RELEASE_COMPR = 16 # macro -NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18 # macro -NVOS32_FUNCTION_HW_ALLOC = 19 # macro -NVOS32_FUNCTION_HW_FREE = 20 # macro -NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27 # macro -NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU = (0x00000001) # macro -NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0 # macro -NVAL_MAX_BANKS = (4) # macro -# NVAL_MAP_DIRECTION = 0 : 0 # macro -NVAL_MAP_DIRECTION_DOWN = 0x00000000 # macro -NVAL_MAP_DIRECTION_UP = 0x00000001 # macro -NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1 # macro -NVOS32_DELETE_RESOURCES_ALL = 0 # macro -NVOS32_TYPE_IMAGE = 0 # macro -NVOS32_TYPE_DEPTH = 1 # macro -NVOS32_TYPE_TEXTURE = 2 # macro -NVOS32_TYPE_VIDEO = 3 # macro -NVOS32_TYPE_FONT = 4 # macro -NVOS32_TYPE_CURSOR = 5 # macro -NVOS32_TYPE_DMA = 6 # macro -NVOS32_TYPE_INSTANCE = 7 # macro -NVOS32_TYPE_PRIMARY = 8 # macro -NVOS32_TYPE_ZCULL = 9 # macro -NVOS32_TYPE_UNUSED = 10 # macro -NVOS32_TYPE_SHADER_PROGRAM = 11 # macro -NVOS32_TYPE_OWNER_RM = 12 # macro -NVOS32_TYPE_NOTIFIER = 13 # macro -NVOS32_TYPE_RESERVED = 14 # macro -NVOS32_TYPE_PMA = 15 # macro -NVOS32_TYPE_STENCIL = 16 # macro -NVOS32_NUM_MEM_TYPES = 17 # macro -NVOS32_ATTR_NONE = 0x00000000 # macro -# NVOS32_ATTR_DEPTH = 2 : 0 # macro -NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000 # macro -NVOS32_ATTR_DEPTH_8 = 0x00000001 # macro -NVOS32_ATTR_DEPTH_16 = 0x00000002 # macro -NVOS32_ATTR_DEPTH_24 = 0x00000003 # macro -NVOS32_ATTR_DEPTH_32 = 0x00000004 # macro -NVOS32_ATTR_DEPTH_64 = 0x00000005 # macro -NVOS32_ATTR_DEPTH_128 = 0x00000006 # macro -# NVOS32_ATTR_COMPR_COVG = 3 : 3 # macro -NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001 # macro -# NVOS32_ATTR_AA_SAMPLES = 7 : 4 # macro -NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000 # macro -NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001 # macro -NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002 # macro -NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003 # macro -NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004 # macro -NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005 # macro -NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006 # macro -NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007 # macro -NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008 # macro -NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009 # macro -NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A # macro -# NVOS32_ATTR_ZCULL = 11 : 10 # macro -NVOS32_ATTR_ZCULL_NONE = 0x00000000 # macro -NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_ZCULL_ANY = 0x00000002 # macro -NVOS32_ATTR_ZCULL_SHARED = 0x00000003 # macro -# NVOS32_ATTR_COMPR = 13 : 12 # macro -NVOS32_ATTR_COMPR_NONE = 0x00000000 # macro -NVOS32_ATTR_COMPR_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_COMPR_ANY = 0x00000002 # macro -NVOS32_ATTR_COMPR_PLC_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_COMPR_PLC_ANY = 0x00000002 # macro -NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003 # macro -# NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP = 14 : 14 # macro -NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000 # macro -NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001 # macro -# NVOS32_ATTR_FORMAT = 17 : 16 # macro -NVOS32_ATTR_FORMAT_LOW_FIELD = 16 # macro -NVOS32_ATTR_FORMAT_HIGH_FIELD = 17 # macro -NVOS32_ATTR_FORMAT_PITCH = 0x00000000 # macro -NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001 # macro -NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002 # macro -# NVOS32_ATTR_Z_TYPE = 18 : 18 # macro -NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000 # macro -NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001 # macro -# NVOS32_ATTR_ZS_PACKING = 21 : 19 # macro -NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000 # macro -NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000 # macro -NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001 # macro -NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002 # macro -NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003 # macro -NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004 # macro -NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005 # macro -NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006 # macro -NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007 # macro -# NVOS32_ATTR_COLOR_PACKING = 21 : 19 # macro -NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000 # macro -NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001 # macro -# NVOS32_ATTR_PAGE_SIZE = 24 : 23 # macro -NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001 # macro -NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002 # macro -NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003 # macro -# NVOS32_ATTR_LOCATION = 26 : 25 # macro -NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000 # macro -NVOS32_ATTR_LOCATION_PCI = 0x00000001 # macro -NVOS32_ATTR_LOCATION_ANY = 0x00000003 # macro -# NVOS32_ATTR_PHYSICALITY = 28 : 27 # macro -NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001 # macro -NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002 # macro -NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003 # macro -# NVOS32_ATTR_COHERENCY = 31 : 29 # macro -NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000 # macro -NVOS32_ATTR_COHERENCY_CACHED = 0x00000001 # macro -NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002 # macro -NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003 # macro -NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004 # macro -NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005 # macro -NVOS32_ATTR2_NONE = 0x00000000 # macro -# NVOS32_ATTR2_ZBC = 1 : 0 # macro -NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001 # macro -NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002 # macro -NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003 # macro -NVOS32_ATTR2_ZBC_INVALID = 0x00000003 # macro -# NVOS32_ATTR2_GPU_CACHEABLE = 3 : 2 # macro -NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001 # macro -NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002 # macro -NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003 # macro -# NVOS32_ATTR2_P2P_GPU_CACHEABLE = 5 : 4 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002 # macro -# NVOS32_ATTR2_32BIT_POINTER = 6 : 6 # macro -NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000 # macro -NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001 # macro -# NVOS32_ATTR2_FIXED_NUMA_NODE_ID = 7 : 7 # macro -NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000 # macro -NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001 # macro -# NVOS32_ATTR2_SMMU_ON_GPU = 9 : 8 # macro -NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001 # macro -NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002 # macro -# NVOS32_ATTR2_USE_SCANOUT_CARVEOUT = 10 : 10 # macro -NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000 # macro -NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001 # macro -# NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN = 11 : 11 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = 0x0 # macro -# NVOS32_ATTR2_PRIORITY = 13 : 12 # macro -NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0 # macro -NVOS32_ATTR2_PRIORITY_HIGH = 0x1 # macro -NVOS32_ATTR2_PRIORITY_LOW = 0x2 # macro -# NVOS32_ATTR2_INTERNAL = 14 : 14 # macro -NVOS32_ATTR2_INTERNAL_NO = 0x0 # macro -NVOS32_ATTR2_INTERNAL_YES = 0x1 # macro -# NVOS32_ATTR2_PREFER_2C = 15 : 15 # macro -NVOS32_ATTR2_PREFER_2C_NO = 0x00000000 # macro -NVOS32_ATTR2_PREFER_2C_YES = 0x00000001 # macro -# NVOS32_ATTR2_NISO_DISPLAY = 16 : 16 # macro -NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000 # macro -NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001 # macro -# NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT = 17 : 17 # macro -NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000 # macro -NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001 # macro -# NVOS32_ATTR2_ISO = 18 : 18 # macro -NVOS32_ATTR2_ISO_NO = 0x00000000 # macro -NVOS32_ATTR2_ISO_YES = 0x00000001 # macro -# NVOS32_ATTR2_BLACKLIST = 19 : 19 # macro -NVOS32_ATTR2_BLACKLIST_ON = 0x00000000 # macro -NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001 # macro -# NVOS32_ATTR2_PAGE_OFFLINING = 19 : 19 # macro -NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000 # macro -NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001 # macro -# NVOS32_ATTR2_PAGE_SIZE_HUGE = 21 : 20 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003 # macro -# NVOS32_ATTR2_PROTECTION_USER = 22 : 22 # macro -NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000 # macro -NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001 # macro -# NVOS32_ATTR2_PROTECTION_DEVICE = 23 : 23 # macro -NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000 # macro -NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001 # macro -# NVOS32_ATTR2_USE_EGM = 24 : 24 # macro -NVOS32_ATTR2_USE_EGM_FALSE = 0x00000000 # macro -NVOS32_ATTR2_USE_EGM_TRUE = 0x00000001 # macro -# NVOS32_ATTR2_MEMORY_PROTECTION = 26 : 25 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002 # macro -# NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP = 27 : 27 # macro -NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000 # macro -NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001 # macro -# NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM = 31 : 31 # macro -NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000 # macro -NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001 # macro -NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001 # macro -NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002 # macro -NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004 # macro -NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008 # macro -NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010 # macro -NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020 # macro -NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040 # macro -NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080 # macro -NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100 # macro -NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000 # macro -NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200 # macro -NVOS32_ALLOC_FLAGS_LAZY = 0x00000400 # macro -NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800 # macro -NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000 # macro -NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000 # macro -NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000 # macro -NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000 # macro -NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000 # macro -NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000 # macro -NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000 # macro -NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000 # macro -NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000 # macro -NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000 # macro -NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000 # macro -NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000 # macro -NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000 # macro -NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000 # macro -NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000 # macro -NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000 # macro -NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED = 0x08000000 # macro -NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000 # macro -NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000 # macro -NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000 # macro -NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000 # macro -NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000 # macro -NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000 # macro -NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001 # macro -NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004 # macro -NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = (0x00080000|0x00000400|0x00400000|0x04000000|0x02000000|0x20000000) # macro -NVOS32_ALLOC_COMPR_COVG_SCALE = 10 # macro -# NVOS32_ALLOC_COMPR_COVG_BITS = 1 : 0 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003 # macro -# NVOS32_ALLOC_COMPR_COVG_MAX = 11 : 2 # macro -# NVOS32_ALLOC_COMPR_COVG_MIN = 21 : 12 # macro -# NVOS32_ALLOC_COMPR_COVG_START = 31 : 22 # macro -# NVOS32_ALLOC_ZCULL_COVG_FORMAT = 3 : 0 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003 # macro -# NVOS32_ALLOC_ZCULL_COVG_FALLBACK = 4 : 4 # macro -NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000 # macro -NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001 # macro -# NVOS32_ALLOC_COMPTAG_OFFSET_START = 19 : 0 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000 # macro -# NVOS32_ALLOC_COMPTAG_OFFSET_USAGE = 31 : 30 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002 # macro -NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000 # macro -NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001 # macro -NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000 # macro -NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002 # macro -NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # macro -NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # macro -NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001 # macro -# NVOS32_DUMP_FLAGS_TYPE = 1 : 0 # macro -NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003 # macro -NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF # macro -NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF # macro -NVOS32_MEM_TAG_NONE = 0x00000000 # macro -NV04_MAP_MEMORY = (0x00000021) # macro -NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000) # macro -NV04_MAP_MEMORY_FLAGS_USER = (0x00004000) # macro -# NVOS33_FLAGS_ACCESS = 1 : 0 # macro -NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS33_FLAGS_PERSISTENT = 4 : 4 # macro -NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_SKIP_SIZE_CHECK = 8 : 8 # macro -NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_MEM_SPACE = 14 : 14 # macro -NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000) # macro -NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001) # macro -# NVOS33_FLAGS_MAPPING = 16 : 15 # macro -NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000) # macro -NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001) # macro -NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002) # macro -# NVOS33_FLAGS_FIFO_MAPPING = 17 : 17 # macro -NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000) # macro -NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_MAP_FIXED = 18 : 18 # macro -NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_RESERVE_ON_UNMAP = 19 : 19 # macro -NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_OS_DESCRIPTOR = 22 : 22 # macro -NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_CACHING_TYPE = 25 : 23 # macro -NVOS33_FLAGS_CACHING_TYPE_CACHED = 0 # macro -NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1 # macro -NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2 # macro -NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5 # macro -NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6 # macro -NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7 # macro -# NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC = 26 : 26 # macro -NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000) # macro -NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001) # macro -NV04_UNMAP_MEMORY = (0x00000022) # macro -NV04_ACCESS_REGISTRY = (0x00000026) # macro -NVOS38_ACCESS_TYPE_READ_DWORD = 1 # macro -NVOS38_ACCESS_TYPE_WRITE_DWORD = 2 # macro -NVOS38_ACCESS_TYPE_READ_BINARY = 6 # macro -NVOS38_ACCESS_TYPE_WRITE_BINARY = 7 # macro -NVOS38_MAX_REGISTRY_STRING_LENGTH = 256 # macro -NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256 # macro -NV04_ALLOC_CONTEXT_DMA = (0x00000027) # macro -NV04_GET_EVENT_DATA = (0x00000028) # macro -NVSIM01_BUS_XACT = (0x0000002C) # macro -NV04_MAP_MEMORY_DMA = (0x0000002E) # macro -# NVOS46_FLAGS_ACCESS = 1 : 0 # macro -NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS46_FLAGS_32BIT_POINTER = 2 : 2 # macro -NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_PAGE_KIND = 3 : 3 # macro -NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000) # macro -NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001) # macro -# NVOS46_FLAGS_CACHE_SNOOP = 4 : 4 # macro -NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_KERNEL_MAPPING = 5 : 5 # macro -NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000) # macro -NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_SHADER_ACCESS = 7 : 6 # macro -NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # macro -NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003) # macro -# NVOS46_FLAGS_PAGE_SIZE = 11 : 8 # macro -NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001) # macro -NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002) # macro -NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003) # macro -NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004) # macro -NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005) # macro -# NVOS46_FLAGS_SYSTEM_L3_ALLOC = 13 : 13 # macro -NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001) # macro -# NVOS46_FLAGS_DMA_OFFSET_GROWS = 14 : 14 # macro -NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000) # macro -NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001) # macro -# NVOS46_FLAGS_DMA_OFFSET_FIXED = 15 : 15 # macro -NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_DISABLE_ENCRYPTION = 16 : 16 # macro -NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_P2P = 27 : 20 # macro -# NVOS46_FLAGS_P2P_ENABLE = 21 : 20 # macro -NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000) # macro -NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001) # macro -NVOS46_FLAGS_P2P_ENABLE_NONE = (0x00000000) # macro -NVOS46_FLAGS_P2P_ENABLE_SLI = (0x00000001) # macro -NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002) # macro -# NVOS46_FLAGS_P2P_SUBDEVICE_ID = 24 : 22 # macro -# NVOS46_FLAGS_P2P_SUBDEV_ID_SRC = 24 : 22 # macro -# NVOS46_FLAGS_P2P_SUBDEV_ID_TGT = 27 : 25 # macro -# NVOS46_FLAGS_TLB_LOCK = 28 : 28 # macro -NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC = 29 : 29 # macro -NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP = 30 : 30 # macro -NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000) # macro -NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_DEFER_TLB_INVALIDATION = 31 : 31 # macro -NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # macro -NV04_UNMAP_MEMORY_DMA = (0x0000002F) # macro -# NVOS47_FLAGS_DEFER_TLB_INVALIDATION = 0 : 0 # macro -NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # macro -NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # macro -NV04_BIND_CONTEXT_DMA = (0x00000031) # macro -NV04_CONTROL = (0x00000036) # macro -NVOS54_FLAGS_NONE = (0x00000000) # macro -NVOS54_FLAGS_IRQL_RAISED = (0x00000001) # macro -NVOS54_FLAGS_LOCK_BYPASS = (0x00000002) # macro -NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004) # macro -NV04_DUP_OBJECT = (0x00000037) # macro -NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000) # macro -NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001) # macro -NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038) # macro -NV04_SHARE = (0x0000003E) # macro -NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128 # macro -NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000) # macro -NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001) # macro -NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002) # macro -NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008) # macro -NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400) # macro -NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED = (0x00000040) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000) # macro -NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000) # macro -NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000) # macro -NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000) # macro -NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001) # macro -NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002) # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3 # macro -# NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE = 14 : 0 # macro -# NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS = 15 : 15 # macro -NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1 # macro -NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0 # macro -# NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB = 1 : 1 # macro -NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000 # macro -NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001 # macro -NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000 # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE = (1 << 0) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE = (1 << 1) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE = (1 << 2) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE = (1 << 3) # macro -NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000) # macro -NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001) # macro -NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002) # macro -NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000) # macro -NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001) # macro -NV04_ADD_VBLANK_CALLBACK = (0x0000003D) # macro -NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000) # macro -NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (1 << 0) # macro -NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (1 << 1) # macro -NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = (1 << 2) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = (1 << 3) # macro -NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = (1 << 4) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED = (1 << 5) # macro -NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = (1 << 6) # macro -NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = (1 << 7) # macro -NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = (1 << 8) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = (1 << 9) # macro -NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = (1 << 10) # macro -NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = (1 << 11) # macro -NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = (1 << 12) # macro -NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = (1 << 13) # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05 # macro -NV_VASPACE_BIG_PAGE_SIZE_64K = (64*1024) # macro -NV_VASPACE_BIG_PAGE_SIZE_128K = (128*1024) # macro -# NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT = 1 : 0 # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003) # macro -# NV_CTXSHARE_ALLOCATION_SUBCTXID_SUBCTXID = 30 : 0 # macro -# NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION = 31 : 31 # macro -NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001) # macro -NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000) # macro -NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002) # macro -NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003) # macro -class struct_NV_MEMORY_DESC_PARAMS(Structure): - pass - -struct_NV_MEMORY_DESC_PARAMS._pack_ = 1 # source:False -struct_NV_MEMORY_DESC_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), -] - -NV_MEMORY_DESC_PARAMS = struct_NV_MEMORY_DESC_PARAMS -class struct_NV_CHANNEL_ALLOC_PARAMS(Structure): - pass - -struct_NV_CHANNEL_ALLOC_PARAMS._pack_ = 1 # source:False -struct_NV_CHANNEL_ALLOC_PARAMS._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hObjectBuffer', ctypes.c_uint32), - ('gpFifoOffset', ctypes.c_uint64), - ('gpFifoEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hContextShare', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('hUserdMemory', ctypes.c_uint32 * 8), - ('userdOffset', ctypes.c_uint64 * 8), - ('engineType', ctypes.c_uint32), - ('cid', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('hObjectEccError', ctypes.c_uint32), - ('instanceMem', NV_MEMORY_DESC_PARAMS), - ('userdMem', NV_MEMORY_DESC_PARAMS), - ('ramfcMem', NV_MEMORY_DESC_PARAMS), - ('mthdbufMem', NV_MEMORY_DESC_PARAMS), - ('hPhysChannelGroup', ctypes.c_uint32), - ('internalFlags', ctypes.c_uint32), - ('errorNotifierMem', NV_MEMORY_DESC_PARAMS), - ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS), - ('ProcessID', ctypes.c_uint32), - ('SubProcessID', ctypes.c_uint32), - ('encryptIv', ctypes.c_uint32 * 3), - ('decryptIv', ctypes.c_uint32 * 3), - ('hmacNonce', ctypes.c_uint32 * 8), - ('tpcConfigID', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV_CHANNEL_ALLOC_PARAMS = struct_NV_CHANNEL_ALLOC_PARAMS -NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS = struct_NV_CHANNEL_ALLOC_PARAMS -class struct_c__SA_NVOS00_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS00_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS00_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectOld', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS00_PARAMETERS = struct_c__SA_NVOS00_PARAMETERS -class struct_c__SA_NVOS02_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS02_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS02_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pMemory', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS02_PARAMETERS = struct_c__SA_NVOS02_PARAMETERS -class struct_c__SA_NVOS05_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS05_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS05_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS05_PARAMETERS = struct_c__SA_NVOS05_PARAMETERS -Callback1ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -Callback5ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -class struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK(Structure): - pass - -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK._pack_ = 1 # source:False -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK._fields_ = [ - ('func', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('arg', ctypes.POINTER(None)), -] - -NVOS10_EVENT_KERNEL_CALLBACK = struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK -class struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX(Structure): - pass - -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX._pack_ = 1 # source:False -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX._fields_ = [ - ('func', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32)), - ('arg', ctypes.POINTER(None)), -] - -NVOS10_EVENT_KERNEL_CALLBACK_EX = struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX -class struct_c__SA_NVOS_I2C_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_NVOS_I2C_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_NVOS_I2C_ACCESS_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('paramStructPtr', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS_I2C_ACCESS_PARAMS = struct_c__SA_NVOS_I2C_ACCESS_PARAMS -class struct_c__SA_NVOS21_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS21_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS21_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('pAllocParms', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS21_PARAMETERS = struct_c__SA_NVOS21_PARAMETERS -class struct_c__SA_NVOS64_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS64_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS64_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('pAllocParms', ctypes.POINTER(None)), - ('pRightsRequested', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NVOS64_PARAMETERS = struct_c__SA_NVOS64_PARAMETERS -class struct_c__SA_NVOS62_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS62_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS62_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS62_PARAMETERS = struct_c__SA_NVOS62_PARAMETERS -class struct_c__SA_NVOS65_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS65_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS65_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('versionMagic', ctypes.c_uint32), - ('maskSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS65_PARAMETERS = struct_c__SA_NVOS65_PARAMETERS -class struct_c__SA_NVOS30_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS30_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS30_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('phClients', ctypes.POINTER(None)), - ('phDevices', ctypes.POINTER(None)), - ('phChannels', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NVOS30_PARAMETERS = struct_c__SA_NVOS30_PARAMETERS -BindResultFunc = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -class struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._fields_ = [ - ('sgt', ctypes.POINTER(None)), - ('gem', ctypes.POINTER(None)), -] - -NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS = struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS -class struct_c__SA_NVOS32_BLOCKINFO(Structure): - pass - -struct_c__SA_NVOS32_BLOCKINFO._pack_ = 1 # source:False -struct_c__SA_NVOS32_BLOCKINFO._fields_ = [ - ('startOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NVOS32_BLOCKINFO = struct_c__SA_NVOS32_BLOCKINFO -class struct_c__SA_NVOS32_PARAMETERS(Structure): - pass - -class union_c__SA_NVOS32_PARAMETERS_data(Union): - pass - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocSize(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocSize._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocSize._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_int32), - ('attr', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_Free(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Free._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Free._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_Info(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Info._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Info._fields_ = [ - ('attr', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('base', ctypes.c_uint64), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_Dump(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Dump._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Dump._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pBuffer', ctypes.POINTER(None)), - ('numBlocks', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment._fields_ = [ - ('alignType', ctypes.c_uint32), - ('alignAttr', ctypes.c_uint32), - ('alignInputFlags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('alignSize', ctypes.c_uint64), - ('alignHeight', ctypes.c_uint32), - ('alignWidth', ctypes.c_uint32), - ('alignPitch', ctypes.c_uint32), - ('alignPad', ctypes.c_uint32), - ('alignMask', ctypes.c_uint32), - ('alignOutputFlags', ctypes.c_uint32 * 4), - ('alignBank', ctypes.c_uint32 * 4), - ('alignKind', ctypes.c_uint32), - ('alignAdjust', ctypes.c_uint32), - ('alignAttr2', ctypes.c_uint32), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc(Structure): - pass - -class struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo._fields_ = [ - ('compPageShift', ctypes.c_uint32), - ('compressedKind', ctypes.c_uint32), - ('compTagLineMin', ctypes.c_uint32), - ('compPageIndexLo', ctypes.c_uint32), - ('compPageIndexHi', ctypes.c_uint32), - ('compTagLineMultiplier', ctypes.c_uint32), -] - -struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc._fields_ = [ - ('allocOwner', ctypes.c_uint32), - ('allochMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('allocType', ctypes.c_uint32), - ('allocAttr', ctypes.c_uint32), - ('allocInputFlags', ctypes.c_uint32), - ('allocSize', ctypes.c_uint64), - ('allocHeight', ctypes.c_uint32), - ('allocWidth', ctypes.c_uint32), - ('allocPitch', ctypes.c_uint32), - ('allocMask', ctypes.c_uint32), - ('allocComprCovg', ctypes.c_uint32), - ('allocZcullCovg', ctypes.c_uint32), - ('bindResultFunc', ctypes.POINTER(None)), - ('pHandle', ctypes.POINTER(None)), - ('hResourceHandle', ctypes.c_uint32), - ('retAttr', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('osDeviceHandle', ctypes.c_uint64), - ('allocAttr2', ctypes.c_uint32), - ('retAttr2', ctypes.c_uint32), - ('allocAddr', ctypes.c_uint64), - ('comprInfo', struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo), - ('uncompressedKind', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_HwFree(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_HwFree._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_HwFree._fields_ = [ - ('hResourceHandle', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('descriptor', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('descriptorType', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -union_c__SA_NVOS32_PARAMETERS_data._pack_ = 1 # source:False -union_c__SA_NVOS32_PARAMETERS_data._fields_ = [ - ('AllocSize', struct_c__SA_NVOS32_PARAMETERS_0_AllocSize), - ('AllocTiledPitchHeight', struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight), - ('Free', struct_c__SA_NVOS32_PARAMETERS_0_Free), - ('ReleaseCompr', struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr), - ('ReacquireCompr', struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr), - ('Info', struct_c__SA_NVOS32_PARAMETERS_0_Info), - ('Dump', struct_c__SA_NVOS32_PARAMETERS_0_Dump), - ('AllocSizeRange', struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange), - ('AllocHintAlignment', struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment), - ('HwAlloc', struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc), - ('HwFree', struct_c__SA_NVOS32_PARAMETERS_0_HwFree), - ('AllocOsDesc', struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc), - ('PADDING_0', ctypes.c_ubyte * 96), -] - -struct_c__SA_NVOS32_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('function', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('ivcHeapNumber', ctypes.c_int16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('total', ctypes.c_uint64), - ('free', ctypes.c_uint64), - ('data', union_c__SA_NVOS32_PARAMETERS_data), -] - -NVOS32_PARAMETERS = struct_c__SA_NVOS32_PARAMETERS -class struct_c__SA_NVOS32_HEAP_DUMP_BLOCK(Structure): - pass - -struct_c__SA_NVOS32_HEAP_DUMP_BLOCK._pack_ = 1 # source:False -struct_c__SA_NVOS32_HEAP_DUMP_BLOCK._fields_ = [ - ('owner', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('begin', ctypes.c_uint64), - ('align', ctypes.c_uint64), - ('end', ctypes.c_uint64), -] - -NVOS32_HEAP_DUMP_BLOCK = struct_c__SA_NVOS32_HEAP_DUMP_BLOCK -class struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), -] - -NV_CONTEXT_DMA_ALLOCATION_PARAMS = struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS -class struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('owner', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_int32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rangeLo', ctypes.c_uint64), - ('rangeHi', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('ctagOffset', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('internalflags', ctypes.c_uint32), - ('tag', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('descriptor', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('descriptorType', ctypes.c_uint32), - ('tag', ctypes.c_uint32), -] - -NV_OS_DESC_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('tag', ctypes.c_uint32), - ('bGuestAllocated', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('bindResultFunc', ctypes.POINTER(None)), - ('pHandle', ctypes.POINTER(None)), - ('osDeviceHandle', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('allocAddr', ctypes.c_uint64), - ('compPageShift', ctypes.c_uint32), - ('compressedKind', ctypes.c_uint32), - ('compTagLineMin', ctypes.c_uint32), - ('compPageIndexLo', ctypes.c_uint32), - ('compPageIndexHi', ctypes.c_uint32), - ('compTagLineMultiplier', ctypes.c_uint32), - ('uncompressedKind', ctypes.c_uint32), - ('tag', ctypes.c_uint32), -] - -NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS = struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS -class struct_c__SA_NVOS33_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS33_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS33_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('pLinearAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NVOS33_PARAMETERS = struct_c__SA_NVOS33_PARAMETERS -class struct_c__SA_NVOS34_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS34_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS34_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pLinearAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NVOS34_PARAMETERS = struct_c__SA_NVOS34_PARAMETERS -class struct_c__SA_NVOS38_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS38_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS38_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('AccessType', ctypes.c_uint32), - ('DevNodeLength', ctypes.c_uint32), - ('pDevNode', ctypes.POINTER(None)), - ('ParmStrLength', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pParmStr', ctypes.POINTER(None)), - ('BinaryDataLength', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pBinaryData', ctypes.POINTER(None)), - ('Data', ctypes.c_uint32), - ('Entry', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -NVOS38_PARAMETERS = struct_c__SA_NVOS38_PARAMETERS -class struct_c__SA_NVOS39_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS39_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS39_PARAMETERS._fields_ = [ - ('hObjectParent', ctypes.c_uint32), - ('hSubDevice', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('selector', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS39_PARAMETERS = struct_c__SA_NVOS39_PARAMETERS -class struct_c__SA_NvUnixEvent(Structure): - pass - -struct_c__SA_NvUnixEvent._pack_ = 1 # source:False -struct_c__SA_NvUnixEvent._fields_ = [ - ('hObject', ctypes.c_uint32), - ('NotifyIndex', ctypes.c_uint32), - ('info32', ctypes.c_uint32), - ('info16', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NvUnixEvent = struct_c__SA_NvUnixEvent -class struct_c__SA_NVOS41_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS41_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS41_PARAMETERS._fields_ = [ - ('pEvent', ctypes.POINTER(None)), - ('MoreEvents', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS41_PARAMETERS = struct_c__SA_NVOS41_PARAMETERS -class struct_c__SA_NVOS2C_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS2C_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS2C_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('bar', ctypes.c_uint32), - ('bytes', ctypes.c_uint32), - ('write', ctypes.c_uint32), - ('data', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS2C_PARAMETERS = struct_c__SA_NVOS2C_PARAMETERS -class struct_c__SA_NVOS46_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS46_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS46_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS46_PARAMETERS = struct_c__SA_NVOS46_PARAMETERS -class struct_c__SA_NVOS47_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS47_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS47_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS47_PARAMETERS = struct_c__SA_NVOS47_PARAMETERS -class struct_c__SA_NVOS49_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS49_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS49_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hCtxDma', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS49_PARAMETERS = struct_c__SA_NVOS49_PARAMETERS -class struct_c__SA_NVOS54_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS54_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS54_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('params', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS54_PARAMETERS = struct_c__SA_NVOS54_PARAMETERS -class struct_c__SA_NVOS63_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS63_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS63_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS63_PARAMETERS = struct_c__SA_NVOS63_PARAMETERS -class struct_c__SA_NVOS55_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS55_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS55_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClientSrc', ctypes.c_uint32), - ('hObjectSrc', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS55_PARAMETERS = struct_c__SA_NVOS55_PARAMETERS -class struct_c__SA_NVOS56_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS56_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS56_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pOldCpuAddress', ctypes.POINTER(None)), - ('pNewCpuAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS56_PARAMETERS = struct_c__SA_NVOS56_PARAMETERS -class struct_c__SA_NVOS57_PARAMETERS(Structure): - pass - -class struct_RS_SHARE_POLICY(Structure): - pass - -class struct_RS_ACCESS_MASK(Structure): - pass - -struct_RS_ACCESS_MASK._pack_ = 1 # source:False -struct_RS_ACCESS_MASK._fields_ = [ - ('limbs', ctypes.c_uint32 * 1), -] - -struct_RS_SHARE_POLICY._pack_ = 1 # source:False -struct_RS_SHARE_POLICY._fields_ = [ - ('target', ctypes.c_uint32), - ('accessMask', struct_RS_ACCESS_MASK), - ('type', ctypes.c_uint16), - ('action', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -struct_c__SA_NVOS57_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS57_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('sharePolicy', struct_RS_SHARE_POLICY), - ('status', ctypes.c_uint32), -] - -NVOS57_PARAMETERS = struct_c__SA_NVOS57_PARAMETERS -class struct_c__SA_NVPOWERSTATE_PARAMETERS(Structure): - pass - -struct_c__SA_NVPOWERSTATE_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVPOWERSTATE_PARAMETERS._fields_ = [ - ('deviceReference', ctypes.c_uint32), - ('head', ctypes.c_uint32), - ('state', ctypes.c_uint32), - ('forceMonitorState', ctypes.c_ubyte), - ('bForcePerfBiosLevel', ctypes.c_ubyte), - ('bIsD3HotTransition', ctypes.c_ubyte), - ('bForcePowerStateFail', ctypes.c_ubyte), - ('errorStatus', ctypes.c_uint32), - ('fastBootPowerState', ctypes.c_uint32), - ('bGC8Transition', ctypes.c_ubyte), - ('bGC8InputRailCutOff', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NVPOWERSTATE_PARAMETERS = struct_c__SA_NVPOWERSTATE_PARAMETERS -PNVPOWERSTATE_PARAMETERS = ctypes.POINTER(struct_c__SA_NVPOWERSTATE_PARAMETERS) -class struct_c__SA_NV_GR_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_GR_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_GR_ALLOCATION_PARAMETERS._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), -] - -NV_GR_ALLOCATION_PARAMETERS = struct_c__SA_NV_GR_ALLOCATION_PARAMETERS - -# values for enumeration 'c__EA_ChannelPBSize' -c__EA_ChannelPBSize__enumvalues = { - 0: 'PB_SIZE_4KB', - 1: 'PB_SIZE_8KB', - 2: 'PB_SIZE_16KB', - 3: 'PB_SIZE_32KB', - 4: 'PB_SIZE_64KB', -} -PB_SIZE_4KB = 0 -PB_SIZE_8KB = 1 -PB_SIZE_16KB = 2 -PB_SIZE_32KB = 3 -PB_SIZE_64KB = 4 -c__EA_ChannelPBSize = ctypes.c_uint32 # enum -ChannelPBSize = c__EA_ChannelPBSize -ChannelPBSize__enumvalues = c__EA_ChannelPBSize__enumvalues -class struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._fields_ = [ - ('channelInstance', ctypes.c_uint32), - ('hObjectBuffer', ctypes.c_uint32), - ('hObjectNotify', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('pControl', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('channelPBSize', ChannelPBSize), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS = struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS -class struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._fields_ = [ - ('channelInstance', ctypes.c_uint32), - ('hObjectNotify', ctypes.c_uint32), - ('pControl', ctypes.POINTER(None)), -] - -NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS = struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS -class struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hObjectEccError', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('engineType', ctypes.c_uint32), - ('bIsCallingContextVgpuPlugin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS = struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('maxTSGs', ctypes.c_uint32), - ('qosIntrEnableMask', ctypes.c_uint32), -] - -NV_SWRUNLIST_ALLOCATION_PARAMS = struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS -class struct_c__SA_NV_ME_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_ME_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_ME_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), -] - -NV_ME_ALLOCATION_PARAMETERS = struct_c__SA_NV_ME_ALLOCATION_PARAMETERS -class struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -NV_BSP_ALLOCATION_PARAMETERS = struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_VP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_VP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_VP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('altUcode', ctypes.c_uint32), - ('rawUcode', ctypes.POINTER(None)), - ('rawUcodeSize', ctypes.c_uint32), - ('numSubClasses', ctypes.c_uint32), - ('numSubSets', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('subClasses', ctypes.POINTER(None)), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pControl', ctypes.POINTER(None)), - ('hMemoryCmdBuffer', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), -] - -NV_VP_ALLOCATION_PARAMETERS = struct_c__SA_NV_VP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), -] - -NV_PPP_ALLOCATION_PARAMETERS = struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -NV_MSENC_ALLOCATION_PARAMETERS = struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS -class struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), -] - -NV_SEC2_ALLOCATION_PARAMETERS = struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS -class struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -NV_NVJPG_ALLOCATION_PARAMETERS = struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS -class struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -NV_OFA_ALLOCATION_PARAMETERS = struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS -class struct_c__SA_NVOS61_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS61_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS61_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hVblank', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pProc', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None))), - ('LogicalHead', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pParm1', ctypes.POINTER(None)), - ('pParm2', ctypes.POINTER(None)), - ('bAdd', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS61_PARAMETERS = struct_c__SA_NVOS61_PARAMETERS -class struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaSize', ctypes.c_uint64), - ('vaStartInternal', ctypes.c_uint64), - ('vaLimitInternal', ctypes.c_uint64), - ('bigPageSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaBase', ctypes.c_uint64), -] - -NV_VASPACE_ALLOCATION_PARAMETERS = struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS -class struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('subctxId', ctypes.c_uint32), -] - -NV_CTXSHARE_ALLOCATION_PARAMETERS = struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS -class struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS(Structure): - pass - -struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('timeoutInMs', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), -] - -NV_TIMEOUT_CONTROL_PARAMETERS = struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS - -# values for enumeration 'c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE' -c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues = { - 0: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', - 1: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', - 2: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', - 3: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', -} -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH = 1 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH = 2 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID = 3 -c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = ctypes.c_uint32 # enum -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues = c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues -class struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._fields_ = [ - ('bDirtyTracking', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('granularity', ctypes.c_uint32), - ('accessBitMask', ctypes.c_uint64 * 64), - ('noOfEntries', ctypes.c_uint32), - ('addrSpace', NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE), -] - -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS = struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS -class struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS(Structure): - pass - -struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS._fields_ = [ - ('bBar1Mapping', ctypes.c_ubyte), - ('bPriv', ctypes.c_ubyte), -] - -NV_HOPPER_USERMODE_A_PARAMS = struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS -class struct_c__SA_nv_ioctl_nvos02_parameters_with_fd(Structure): - pass - -struct_c__SA_nv_ioctl_nvos02_parameters_with_fd._pack_ = 1 # source:False -struct_c__SA_nv_ioctl_nvos02_parameters_with_fd._fields_ = [ - ('params', NVOS02_PARAMETERS), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -nv_ioctl_nvos02_parameters_with_fd = struct_c__SA_nv_ioctl_nvos02_parameters_with_fd -class struct_c__SA_nv_ioctl_nvos33_parameters_with_fd(Structure): - pass - -struct_c__SA_nv_ioctl_nvos33_parameters_with_fd._pack_ = 1 # source:False -struct_c__SA_nv_ioctl_nvos33_parameters_with_fd._fields_ = [ - ('params', NVOS33_PARAMETERS), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -nv_ioctl_nvos33_parameters_with_fd = struct_c__SA_nv_ioctl_nvos33_parameters_with_fd -# def NV0000_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx) -NV0000_CTRL_RESERVED = (0x00) # macro -NV0000_CTRL_SYSTEM = (0x01) # macro -NV0000_CTRL_GPU = (0x02) # macro -NV0000_CTRL_GSYNC = (0x03) # macro -NV0000_CTRL_DIAG = (0x04) # macro -NV0000_CTRL_EVENT = (0x05) # macro -NV0000_CTRL_NVD = (0x06) # macro -NV0000_CTRL_SWINSTR = (0x07) # macro -NV0000_CTRL_PROC = (0x09) # macro -NV0000_CTRL_SYNC_GPU_BOOST = (0x0A) # macro -NV0000_CTRL_GPUACCT = (0x0B) # macro -NV0000_CTRL_VGPU = (0x0C) # macro -NV0000_CTRL_CLIENT = (0x0D) # macro -NV0000_CTRL_OS_WINDOWS = (0x3F) # macro -NV0000_CTRL_OS_MACOS = (0x3E) # macro -NV0000_CTRL_OS_UNIX = (0x3D) # macro -NV0000_CTRL_CMD_NULL = (0x0) # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01) # macro -NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02) # macro -NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002 # macro -NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03) # macro -NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04) # macro -NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05) # macro -NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5) # macro -NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06) # macro -NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07) # macro -NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08) # macro -NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('mapFlags', ctypes.c_uint32), - ('addrSpaceType', ctypes.c_uint32), -] - -NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS -class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(Structure): - pass - -class union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(Union): - pass - -union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._pack_ = 1 # source:False -union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._fields_ = [ - ('hResult', ctypes.c_uint32), - ('iResult', ctypes.c_uint64), -] - -struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('data', union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data), -] - -NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS = struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS -class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('maskResult', struct_RS_ACCESS_MASK), -] - -NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS -class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sharePolicy', struct_RS_SHARE_POLICY), - ] - -NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS = struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS -class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS._fields_ = [ - ('hParent', ctypes.c_uint32), - ('classId', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS = struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS -class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('sharePolicy', struct_RS_SHARE_POLICY), -] - -NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS = struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS -class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS._fields_ = [ - ('hObject1', ctypes.c_uint32), - ('hObject2', ctypes.c_uint32), - ('bDuplicates', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS = struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS -class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS._fields_ = [ - ('devDescriptor', ctypes.c_uint64), - ('channel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS = struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS -NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001) # macro -NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000) # macro -NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002) # macro -NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET = (0x00002000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET = (0x00002001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F) # macro -NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85) # macro -NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488) # macro -NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88) # macro -NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000) # macro -NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001) # macro -NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002) # macro -NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489) # macro -NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100) # macro -NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89) # macro -class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS._fields_ = [ - ('state', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('missedCount', ctypes.c_uint32), - ('bCircularBuffer', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS -class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS._fields_ = [ - ('state', ctypes.c_uint32), - ('bCircularBuffer', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS -class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(Structure): - pass - -struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY._fields_ = [ - ('counter', ctypes.c_uint64), - ('line', ctypes.c_uint32), - ('filename', ctypes.c_ubyte * 12), - ('tag', ctypes.c_uint16), - ('cpuNum', ctypes.c_ubyte), - ('irql', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), - ('threadId', ctypes.c_uint64), - ('data0', ctypes.c_uint32), - ('data1', ctypes.c_uint32), - ('data2', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0000_CTRL_DIAG_LOCK_METER_ENTRY = struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY -class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS._fields_ = [ - ('entryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('entries', struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY * 64), -] - -NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS -class struct_RPC_METER_ENTRY(Structure): - pass - -struct_RPC_METER_ENTRY._pack_ = 1 # source:False -struct_RPC_METER_ENTRY._fields_ = [ - ('startTimeInNs', ctypes.c_uint64), - ('endTimeInNs', ctypes.c_uint64), - ('rpcDataTag', ctypes.c_uint64), - ('rpcExtraData', ctypes.c_uint64), -] - -RPC_METER_ENTRY = struct_RPC_METER_ENTRY -class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS._fields_ = [ - ('rpcProfileCmd', ctypes.c_uint32), -] - -NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS = struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS -class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS._fields_ = [ - ('firstEntryOffset', ctypes.c_uint32), - ('outputEntryCount', ctypes.c_uint32), - ('remainingEntryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('elapsedTimeInNs', ctypes.c_uint64), - ('rpcProfilerBuffer', struct_RPC_METER_ENTRY * 100), -] - -NV0000_CTRL_DIAG_DUMP_RPC_PARAMS = struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS -NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # macro -NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS = (0x502) # macro -NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('action', ctypes.c_uint32), -] - -NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS -class struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS = struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS -NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_SLI = 0 : 0 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT = 2 : 2 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING = 3 : 3 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED = 4 : 4 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102) # macro -NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -# NV0000_CTRL_SYSTEM_CPU_FAMILY = 3 : 0 # macro -# NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY = 11 : 4 # macro -# NV0000_CTRL_SYSTEM_CPU_MODEL = 3 : 0 # macro -# NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL = 7 : 4 # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0 # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9 # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104) # macro -NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020) # macro -NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff) # macro -NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -# NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE = 0 : 0 # macro -NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000) # macro -NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001) # macro -NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107) # macro -NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109) # macro -NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108) # macro -NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32) # macro -NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8) # macro -NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110) # macro -NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111) # macro -NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003) # macro -NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512 # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21) # macro -NV0000_CTRL_SYSTEM_HWBC_INVALID_ID = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO = (0x124) # macro -NV0000_CTRL_SYSTEM_MAX_HWBCS = (0x00000080) # macro -NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID = (0x24) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122) # macro -NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000) # macro -def NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i): # macro - return (0x0100+((i)%0x100)) -def NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i): # macro - return (0x0200+((i)%0x100)) -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16) # macro -NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127) # macro -NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32 # macro -NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024 # macro -NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff # macro -NV0000_CTRL_P2P_CAPS_INDEX_READ = 0 # macro -NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1 # macro -NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2 # macro -NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4 # macro -NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6 # macro -NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8 # macro -NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED = 0 : 0 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED = 1 : 1 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED = 2 : 2 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED = 3 : 3 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED = 4 : 4 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED = 5 : 5 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED = 6 : 6 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED = 7 : 7 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED = 8 : 8 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED = 9 : 9 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED = 10 : 10 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED = 12 : 12 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED = 13 : 13 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001) # macro -NV0000_P2P_CAPS_STATUS_OK = (0x00) # macro -NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01) # macro -NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02) # macro -NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03) # macro -NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04) # macro -NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a) # macro -NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A) # macro -NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # macro -NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001) # macro -NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002) # macro -NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # macro -NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # macro -NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # macro -NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # macro -NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # macro -NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B) # macro -NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # macro -NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # macro -NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # macro -NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # macro -NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # macro -NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # macro -NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # macro -NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = 1 # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # macro -# NV0000_CTRL_GPS_PPM_INDEX = 7 : 0 # macro -NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0) # macro -NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1) # macro -NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2) # macro -NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF) # macro -# NV0000_CTRL_GPS_PPM_MASK = 15 : 8 # macro -NV0000_CTRL_GPS_PPM_MASK_INVALID = (0) # macro -NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0) # macro -NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1) # macro -NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS = (0x129) # macro -GPS_MAX_COUNTERS_PER_BLOCK = 32 # macro -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c) # macro -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e) # macro -NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E) # macro -GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # macro -NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d) # macro -NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000) # macro -NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002) # macro -NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003) # macro -NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004) # macro -NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005) # macro -NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006) # macro -NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007) # macro -NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008) # macro -NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009) # macro -NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131) # macro -NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f) # macro -NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64 # macro -NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132) # macro -NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32) # macro -NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256 # macro -NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133) # macro -NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33) # macro -NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134) # macro -NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34) # macro -NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0 # macro -NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1 # macro -NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136) # macro -NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36) # macro -NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137) # macro -NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37) # macro -NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138) # macro -NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38) # macro -NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139) # macro -NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39) # macro -NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b) # macro -NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1 # macro -NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32 # macro -NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48) # macro -NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B) # macro -CONTROLLER_FILTER_TYPE_EMWA = 0 # macro -CONTROLLER_FILTER_TYPE_MOVING_MAX = 1 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6 # macro -NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000) # macro -NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # macro -# NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED = 0 : 0 # macro -NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1 # macro -NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009) # macro -NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255) # macro -NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c) # macro -NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d) # macro -NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256 # macro -NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E) # macro -NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000) # macro -def NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i): # macro - return (0x0100+((i)%0x100)) -def NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i): # macro - return (0x0200+((i)%0x100)) -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = 1 # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # macro -# NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX = 7 : 0 # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF) # macro -# NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK = 15 : 8 # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1) # macro -PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32 # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47) # macro -PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64 # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45) # macro -NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201) # macro -NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32 # macro -NV0000_CTRL_GPU_INVALID_ID = (0xffffffff) # macro -NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202) # macro -NV0000_CTRL_GPU_MAX_SZNAME = 128 # macro -NV0000_CTRL_NO_NUMA_NODE = (-1) # macro -NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_SLI_STATUS_OK = (0x00000000) # macro -NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002) # macro -NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040) # macro -NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205) # macro -NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_GPU_ID_INFO_IN_USE = 0 : 0 # macro -NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE = 1 : 1 # macro -NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_MOBILE = 2 : 2 # macro -NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER = 3 : 3 # macro -NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_SOC = 5 : 5 # macro -NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED = 6 : 6 # macro -NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203) # macro -NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204) # macro -NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214) # macro -# NV0000_CTRL_GPU_MAX_PROBED_GPUS = NV_MAX_DEVICES # macro -NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14) # macro -NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b) # macro -NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B) # macro -NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215) # macro -NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff) # macro -NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15) # macro -NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216) # macro -NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff) # macro -NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16) # macro -NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219) # macro -NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8 # macro -NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19) # macro -NV0000_CTRL_CMD_GPU_GET_SVM_SIZE = (0x240) # macro -NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID = (0x40) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274) # macro -NV0000_GPU_MAX_GID_LENGTH = (0x00000100) # macro -NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT = 1 : 0 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE = 2 : 2 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275) # macro -NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT = 1 : 0 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE = 2 : 2 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278) # macro -NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000) # macro -NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001) # macro -NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001) # macro -NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002) # macro -NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78) # macro -NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279) # macro -NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79) # macro -NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a) # macro -NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b) # macro -NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B) # macro -NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281) # macro -NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175 # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6 # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5 # macro -NV0000_CTRL_CMD_GPU_LEGACY_CONFIG = (0x282) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID = (0x82) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET = (0x00000001) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX = (0x00000002) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX = (0x00000003) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED = (0x00000004) # macro -NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283) # macro -NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003) # macro -NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285) # macro -NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85) # macro -# NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY = 2 : 0 # macro -# NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT = 7 : 3 # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02) # macro -NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286) # macro -NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # macro -NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287) # macro -NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # macro -NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288) # macro -NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256 # macro -NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88) # macro -NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289) # macro -NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89) # macro -NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290) # macro -NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90) # macro -class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS._fields_ = [ - ('featuresMask', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS._fields_ = [ - ('sizeOfStrings', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pDriverVersionBuffer', ctypes.POINTER(None)), - ('pVersionBuffer', ctypes.POINTER(None)), - ('pTitleBuffer', ctypes.POINTER(None)), - ('changelistNumber', ctypes.c_uint32), - ('officialChangelistNumber', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS - -# values for enumeration 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE' -NV0000_CTRL_SYSTEM_SH_SOC_TYPE__enumvalues = { - 0: 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', - 1: 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', -} -NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = 0 -NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = 1 -NV0000_CTRL_SYSTEM_SH_SOC_TYPE = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), - ('capabilities', ctypes.c_uint32), - ('clock', ctypes.c_uint32), - ('L1DataCacheSize', ctypes.c_uint32), - ('L2DataCacheSize', ctypes.c_uint32), - ('dataCacheLineSize', ctypes.c_uint32), - ('numLogicalCpus', ctypes.c_uint32), - ('numPhysicalCpus', ctypes.c_uint32), - ('name', ctypes.c_ubyte * 52), - ('family', ctypes.c_uint32), - ('model', ctypes.c_uint32), - ('stepping', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('coresOnDie', ctypes.c_uint32), - ('bCCEnabled', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('selfHostedSocType', NV0000_CTRL_SYSTEM_SH_SOC_TYPE), -] - -NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS._fields_ = [ - ('vendorId', ctypes.c_uint16), - ('deviceId', ctypes.c_uint16), - ('subSysVendorId', ctypes.c_uint16), - ('subSysDeviceId', ctypes.c_uint16), - ('HBvendorId', ctypes.c_uint16), - ('HBdeviceId', ctypes.c_uint16), - ('HBsubSysVendorId', ctypes.c_uint16), - ('HBsubSysDeviceId', ctypes.c_uint16), - ('sliBondId', ctypes.c_uint32), - ('vendorNameString', ctypes.c_ubyte * 32), - ('subSysVendorNameString', ctypes.c_ubyte * 32), - ('chipsetNameString', ctypes.c_ubyte * 32), - ('sliBondNameString', ctypes.c_ubyte * 32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS._fields_ = [ - ('bIsPresent', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS._fields_ = [ - ('waitApiLock', ctypes.c_uint64), - ('holdRoApiLock', ctypes.c_uint64), - ('holdRwApiLock', ctypes.c_uint64), - ('waitGpuLock', ctypes.c_uint64), - ('holdGpuLock', ctypes.c_uint64), -] - -NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('classes', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS -class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS._fields_ = [ - ('eventType', ctypes.c_uint32), - ('eventData', ctypes.c_uint32), - ('bEventDataForced', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS = struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS._fields_ = [ - ('systemType', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS -class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 512), -] - -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_HWBC_INFO(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_HWBC_INFO._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_HWBC_INFO._fields_ = [ - ('hwbcId', ctypes.c_uint32), - ('firmwareVersion', ctypes.c_uint32), - ('subordinateBus', ctypes.c_uint32), - ('secondaryBus', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_HWBC_INFO = struct_NV0000_CTRL_SYSTEM_HWBC_INFO -class struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('hwbcInfo', struct_NV0000_CTRL_SYSTEM_HWBC_INFO * 128), - ] - -NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), -] - -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS._fields_ = [ - ('cmdCount', ctypes.c_uint32), - ('succeeded', ctypes.c_uint32), - ('cmdData', struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0 * 16), -] - -NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 7), - ('busPeerIds', ctypes.POINTER(None)), - ('busEgmPeerIds', ctypes.POINTER(None)), -] - -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerIds', ctypes.c_uint32 * 1024), - ('busEgmPeerIds', ctypes.c_uint32 * 1024), -] - -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS -NV0000_CTRL_P2P_CAPS_MATRIX_ROW = ctypes.c_uint32 * 8 -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS._fields_ = [ - ('grpACount', ctypes.c_uint32), - ('grpBCount', ctypes.c_uint32), - ('gpuIdGrpA', ctypes.c_uint32 * 8), - ('gpuIdGrpB', ctypes.c_uint32 * 8), - ('p2pCaps', ctypes.c_uint32 * 8 * 8), - ('a2bOptimalReadCes', ctypes.c_uint32 * 8 * 8), - ('a2bOptimalWriteCes', ctypes.c_uint32 * 8 * 8), - ('b2aOptimalReadCes', ctypes.c_uint32 * 8 * 8), - ('b2aOptimalWriteCes', ctypes.c_uint32 * 8 * 8), -] - -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_int32 * 2), - ('result', ctypes.c_int32 * 4), -] - -NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [ - ('objHndl', ctypes.c_uint32), - ('blockId', ctypes.c_uint32), - ('nextExpectedSampleTimems', ctypes.c_uint32), - ('countersReq', ctypes.c_uint32), - ('countersReturned', ctypes.c_uint32), - ('counterBlock', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS -NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_uint32), - ('resultSz', ctypes.c_uint32), - ('result', ctypes.c_uint32 * 288), -] - -NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS -class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS._fields_ = [ - ('method', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('inData', ctypes.POINTER(None)), - ('inDataSize', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('outStatus', ctypes.c_uint32), - ('outData', ctypes.POINTER(None)), - ('outDataSize', ctypes.c_uint16), - ('PADDING_2', ctypes.c_ubyte * 6), -] - -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS = struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS -class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS._fields_ = [ - ('moduleMask', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS = struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE._fields_ = [ - ('frameTime', ctypes.c_uint16), - ('renderTime', ctypes.c_uint16), - ('targetTime', ctypes.c_uint16), - ('sleepTime', ctypes.c_ubyte), - ('sampleNumber', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE -class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS._fields_ = [ - ('samples', struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE * 64), - ('nextSampleNumber', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sampleData', NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE), - ] - -NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS._fields_ = [ - ('szHostDriverVersionBuffer', ctypes.c_char * 256), - ('szHostVersionBuffer', ctypes.c_char * 256), - ('szHostTitleBuffer', ctypes.c_char * 256), - ('szPluginTitleBuffer', ctypes.c_char * 256), - ('szHostUnameBuffer', ctypes.c_char * 256), - ('iHostChangelistNumber', ctypes.c_uint32), - ('iPluginChangelistNumber', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS._fields_ = [ - ('gpuCount', ctypes.c_ubyte), - ('gpuBus', ctypes.c_ubyte * 32), - ('gpuExternalPowerStatus', ctypes.c_ubyte * 32), -] - -NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS._fields_ = [ - ('privStatusFlags', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS - -# values for enumeration 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS' -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS__enumvalues = { - 1: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', - 2: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', - 3: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', - 4: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', -} -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fabricStatus', NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS), - ] - -NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS -class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS._fields_ = [ - ('host_min_supported_version', ctypes.c_uint32), - ('host_max_supported_version', ctypes.c_uint32), - ('user_min_supported_version', ctypes.c_uint32), - ('user_max_supported_version', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS -class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS._fields_ = [ - ('min_version', ctypes.c_uint32), - ('max_version', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS._fields_ = [ - ('rm_instance_id', ctypes.c_uint64), -] - -NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT._fields_ = [ - ('batteryStateOfChargePercent', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('batteryCurrentLimitmA', ctypes.c_uint32), - ('restOfSytemReservedPowermW', ctypes.c_uint32), - ('minCpuTdpmW', ctypes.c_uint32), - ('maxCpuTdpmW', ctypes.c_uint32), - ('shortTimescaleBatteryCurrentLimitmA', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT = struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT -class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(Structure): - pass - -class union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(Union): - pass - -union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._pack_ = 1 # source:False -union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._fields_ = [ - ('weight', ctypes.c_ubyte), - ('windowSize', ctypes.c_ubyte), -] - -struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('tpp', ctypes.c_uint32), - ('ratedTgp', ctypes.c_uint32), - ('subFunc', ctypes.c_uint32), - ('ctgpOffsetmW', ctypes.c_int32), - ('targetTppOffsetmW', ctypes.c_int32), - ('maxOutputOffsetmW', ctypes.c_int32), - ('minOutputOffsetmW', ctypes.c_int32), - ('ctgpBattOffsetmW', ctypes.c_int32), - ('targetTppBattOffsetmW', ctypes.c_int32), - ('dcRosReserveOverridemW', ctypes.c_uint32), - ('dcTspLongTimescaleLimitmA', ctypes.c_uint32), - ('dcTspShortTimescaleLimitmA', ctypes.c_uint32), - ('bRequireDcSysPowerLimitsTable', ctypes.c_ubyte), - ('bAllowDcRestOfSystemReserveOverride', ctypes.c_ubyte), - ('bSupportDcTsp', ctypes.c_ubyte), - ('bEnableForAC', ctypes.c_ubyte), - ('bEnableForDC', ctypes.c_ubyte), - ('version', ctypes.c_ubyte), - ('samplingPeriodmS', ctypes.c_uint16), - ('samplingMulti', ctypes.c_uint16), - ('filterType', ctypes.c_ubyte), - ('filterParam', union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam), - ('filterReserved', ctypes.c_uint16), - ('bIsBoostController', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('incRatio', ctypes.c_uint16), - ('decRatio', ctypes.c_uint16), - ('bSupportBatt', ctypes.c_ubyte), - ('cpuType', ctypes.c_ubyte), - ('gpuType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('sysPwrIndex', ctypes.c_uint32), - ('sysPwrGetInfo', struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT * 32), - ('bIsTspSupported', ctypes.c_ubyte), - ('sysPwrLimitsTableVersion', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 2), - ('type', ctypes.c_uint32), - ('cpuTdpmw', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS -NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS._fields_ = [ - ('bExternalFabricMgmt', ctypes.c_ubyte), -] - -NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS._fields_ = [ - ('clientCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resourceCount', ctypes.c_uint64), -] - -NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS._fields_ = [ - ('driverVersionBuffer', ctypes.c_char * 256), - ('versionBuffer', ctypes.c_char * 256), - ('driverBranch', ctypes.c_char * 256), - ('titleBuffer', ctypes.c_char * 256), - ('changelistNumber', ctypes.c_uint32), - ('officialChangelistNumber', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS -class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('mode', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), -] - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS._fields_ = [ - ('cmdCount', ctypes.c_uint32), - ('succeeded', ctypes.c_uint32), - ('cmdData', struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0 * 16), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_int32 * 2), - ('result', ctypes.c_int32 * 4), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [ - ('objHndl', ctypes.c_uint32), - ('blockId', ctypes.c_uint32), - ('nextExpectedSampleTimems', ctypes.c_uint32), - ('countersReq', ctypes.c_uint32), - ('countersReturned', ctypes.c_uint32), - ('counterBlock', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_uint32), - ('resultSz', ctypes.c_uint32), - ('result', ctypes.c_uint32 * 288), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE._fields_ = [ - ('frameTime', ctypes.c_uint16), - ('renderTime', ctypes.c_uint16), - ('targetTime', ctypes.c_uint16), - ('sleepTime', ctypes.c_ubyte), - ('sampleNumber', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS._fields_ = [ - ('samples', struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE * 64), - ('nextSampleNumber', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sampleData', NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE), - ] - -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuFlags', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subDeviceInstance', ctypes.c_uint32), - ('szName', ctypes.POINTER(None)), - ('sliStatus', ctypes.c_uint32), - ('boardId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('numaId', ctypes.c_int32), -] - -NV0000_CTRL_GPU_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS -class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuFlags', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subDeviceInstance', ctypes.c_uint32), - ('sliStatus', ctypes.c_uint32), - ('boardId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('numaId', ctypes.c_int32), -] - -NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS -class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS -class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._fields_ = [ - ('deviceIds', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('excludedGpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('slot', ctypes.c_uint16), -] - -NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS -class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('failedId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ATTACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS -class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_DETACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS -class struct_NV0000_CTRL_GPU_VIDEO_LINKS(Structure): - pass - -struct_NV0000_CTRL_GPU_VIDEO_LINKS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_VIDEO_LINKS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('connectedGpuIds', ctypes.c_uint32 * 8), -] - -NV0000_CTRL_GPU_VIDEO_LINKS = struct_NV0000_CTRL_GPU_VIDEO_LINKS -class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('links', struct_NV0000_CTRL_GPU_VIDEO_LINKS * 32), - ] - -NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS -class struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('svmSize', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS = struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS -class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._fields_ = [ - ('gpuUuid', ctypes.c_ubyte * 256), - ('flags', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subdeviceInstance', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS -class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('gpuUuid', ctypes.c_ubyte * 256), - ('uuidStrLen', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS -class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('newState', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS -class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('drainState', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS -class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('function', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_DISCOVER_PARAMS = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS -class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._fields_ = [ - ('enableMask', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS -class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('bSkipHwNvlinkDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS(Structure): - pass - -class union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data(Union): - pass - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet._fields_ = [ - ('newValue', ctypes.c_uint32), - ('oldValue', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx._fields_ = [ - ('paramData', ctypes.c_ubyte * 373), - ('PADDING_0', ctypes.c_ubyte * 3), - ('paramSize', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty._fields_ = [ - ('propertyId', ctypes.c_uint32), - ('propertyIn', ctypes.c_uint32 * 6), - ('propertyOut', ctypes.c_uint32 * 5), -] - -union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._pack_ = 1 # source:False -union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._fields_ = [ - ('configSet', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet), - ('configEx', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx), - ('reservedProperty', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty), - ('PADDING_0', ctypes.c_ubyte * 332), -] - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._fields_ = [ - ('hContext', ctypes.c_uint32), - ('opType', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('dataType', ctypes.c_uint32), - ('data', union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data), -] - -NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS = struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS -class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('phClients', ctypes.POINTER(None)), - ('phDevices', ctypes.POINTER(None)), - ('phChannels', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS -class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._fields_ = [ - ('image', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('totalSize', ctypes.c_uint64), - ('pData', ctypes.POINTER(None)), -] - -NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS -class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS -class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_ubyte), - ('bwModeScope', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS -class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(Structure): - pass - -struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), - ('computeInstanceId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ACTIVE_DEVICE = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE -class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._fields_ = [ - ('numDevices', ctypes.c_uint32), - ('devices', struct_NV0000_CTRL_GPU_ACTIVE_DEVICE * 256), -] - -NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS -class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS -class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS -NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01) # macro -NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000) # macro -NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001) # macro -NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02) # macro -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03) # macro -NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04) # macro -NV0000_GPUACCT_PID_MAX_COUNT = 4000 # macro -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05) # macro -NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5) # macro -class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('newState', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('state', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('subPid', ctypes.c_uint32), - ('gpuUtil', ctypes.c_uint32), - ('fbUtil', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('maxFbUsage', ctypes.c_uint64), - ('startTime', ctypes.c_uint64), - ('endTime', ctypes.c_uint64), -] - -NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('pidTbl', ctypes.c_uint32 * 4000), - ('pidCount', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS -class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS -NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301) # macro -NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff) # macro -NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302) # macro -NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._fields_ = [ - ('gsyncIds', ctypes.c_uint32 * 4), -] - -NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS -class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._fields_ = [ - ('gsyncId', ctypes.c_uint32), - ('gsyncFlags', ctypes.c_uint32), - ('gsyncInstance', ctypes.c_uint32), -] - -NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS -NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400) # macro -NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800) # macro -NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00) # macro -NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601) # macro -NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000) # macro -NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602) # macro -NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000) # macro -NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001) # macro -NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002) # macro -NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003) # macro -NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603) # macro -NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604) # macro -NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16) # macro -NV0000_CTRL_NVD_SIGNATURE_SIZE = (4) # macro -NV0000_CTRL_NVD_MAX_BUFFERS = (3840) # macro -NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO = 7 : 0 # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE = 23 : 8 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL = 28 : 25 # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP = 30 : 29 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED = 31 : 31 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605) # macro -NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE = 0 : 0 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED = 0 : 0 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE = 1 : 1 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE = 2 : 2 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED = 3 : 3 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING = 5 : 4 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA = 6 : 6 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606) # macro -NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000) # macro -NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607) # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008 # macro -def TPC_REG_ATTR(gpcId, tpcId): # macro - return ((gpcId<<8)|(tpcId)) -def ROP_REG_ATTR(gpcId, ropId): # macro - return ((gpcId<<8)|(ropId)) -def SM_REG_ATTR(gpcId, tpcId, smId): # macro - return ((((gpcId)<<16)|((tpcId)<<8))|(smId)) -NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF # macro -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608) # macro -NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS -class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [ - ('pBuffer', ctypes.POINTER(None)), - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_DUMP_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS -class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._fields_ = [ - ('timestamp', ctypes.c_uint64), - ('cpuClkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('version', ctypes.c_uint32), - ('runtimeSizes', ctypes.c_ubyte * 16), - ('printFlags', ctypes.c_uint32), - ('signature', ctypes.c_uint32 * 4), - ('bufferTags', ctypes.c_uint32 * 3840), -] - -NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('buffer', ctypes.c_uint32), - ('tag', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('pos', ctypes.c_uint32), - ('overflow', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('buffer', ctypes.c_uint32), - ('blockNum', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 4000), -] - -NV0000_CTRL_NVD_GET_NVLOG_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS -class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(Structure): - pass - -struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._fields_ = [ - ('tag', ctypes.c_uint32), - ('value', ctypes.c_uint32), - ('attribute', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY -class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._fields_ = [ - ('reqIdx', ctypes.c_uint16), - ('rptIdx', ctypes.c_uint16), - ('GPUTag', ctypes.c_uint32), - ('rptTime', ctypes.c_uint32), - ('startIdx', ctypes.c_uint16), - ('endIdx', ctypes.c_uint16), - ('rptType', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), - ('rptCount', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('owner', ctypes.c_uint32), - ('processId', ctypes.c_uint32), - ('report', struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY * 200), -] - -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS -class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._fields_ = [ - ('tsBufferSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pTSBuffer', ctypes.POINTER(None)), -] - -NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS -NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901) # macro -NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902) # macro -class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._fields_ = [ - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), -] - -NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS -class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._fields_ = [ - ('bIsSubProcessDisabled', ctypes.c_ubyte), -] - -NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS -NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10) # macro -NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01) # macro -NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02) # macro -NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03) # macro -NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04) # macro -NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._fields_ = [ - ('bEnabled', ctypes.c_ubyte), -] - -NV0000_SYNC_GPU_BOOST_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._fields_ = [ - ('gpuCount', ctypes.c_uint32), - ('gpuIds', ctypes.c_uint32 * 32), - ('boostGroupId', ctypes.c_uint32), - ('bBridgeless', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_SYNC_GPU_BOOST_GROUP_CONFIG = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG -class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('boostConfig', NV0000_SYNC_GPU_BOOST_GROUP_CONFIG), - ] - -NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._fields_ = [ - ('boostGroupId', ctypes.c_uint32), -] - -NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._fields_ = [ - ('groupCount', ctypes.c_uint32), - ('pBoostGroups', struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG * 16), -] - -NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS -NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02) # macro -NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003) # macro -NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04) # macro -NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD = 0 : 0 # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06) # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07) # macro -NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08) # macro -NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 # macro -NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09) # macro -NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a) # macro -NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 # macro -NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA) # macro -NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512 # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB) # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c) # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4 # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('cacheOps', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('internalOnly', ctypes.c_uint64), -] - -NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS = struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS -class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), -] - -NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS - -# values for enumeration 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE' -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE__enumvalues = { - 0: 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', - 1: 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', -} -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0 -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1 -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(Structure): - pass - -class union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(Union): - pass - -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._pack_ = 1 # source:False -union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._fields_ = [ - ('rmObject', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject), -] - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT._fields_ = [ - ('type', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE), - ('data', union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data), -] - -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS._fields_ = [ - ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), -] - -NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS -class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('minorNum', ctypes.c_uint32), -] - -NV0000_CTRL_OS_GET_GPU_INFO_PARAMS = struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS -class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('deviceInstance', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS -class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), - ('fd', ctypes.c_int32), -] - -NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('hDevice', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), - ('objects', ctypes.c_uint32 * 512), - ('numObjects', ctypes.c_uint16), - ('index', ctypes.c_uint16), -] - -NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('hParent', ctypes.c_uint32), - ('objects', ctypes.c_uint32 * 128), - ('objectTypes', ctypes.c_ubyte * 128), - ('numObjects', ctypes.c_uint16), - ('index', ctypes.c_uint16), -] - -NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS -# def NV2080_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x2080,NV2080_CTRL_##cat,idx) -NV2080_CTRL_RESERVED = (0x00) # macro -NV2080_CTRL_GPU = (0x01) # macro -NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81) # macro -NV2080_CTRL_FUSE = (0x02) # macro -NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82) # macro -NV2080_CTRL_EVENT = (0x03) # macro -NV2080_CTRL_TIMER = (0x04) # macro -NV2080_CTRL_THERMAL = (0x05) # macro -NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5) # macro -NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85) # macro -NV2080_CTRL_I2C = (0x06) # macro -NV2080_CTRL_EXTI2C = (0x07) # macro -NV2080_CTRL_BIOS = (0x08) # macro -NV2080_CTRL_CIPHER = (0x09) # macro -NV2080_CTRL_INTERNAL = (0x0A) # macro -NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0) # macro -NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90) # macro -NV2080_CTRL_CLK = (0x10) # macro -NV2080_CTRL_FIFO = (0x11) # macro -NV2080_CTRL_GR = (0x12) # macro -NV2080_CTRL_FB = (0x13) # macro -NV2080_CTRL_MC = (0x17) # macro -NV2080_CTRL_BUS = (0x18) # macro -NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0) # macro -NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0) # macro -NV2080_CTRL_PERF = (0x20) # macro -NV2080_CTRL_NVIF = (0x21) # macro -NV2080_CTRL_RC = (0x22) # macro -NV2080_CTRL_GPIO = (0x23) # macro -NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3) # macro -NV2080_CTRL_NVD = (0x24) # macro -NV2080_CTRL_DMA = (0x25) # macro -NV2080_CTRL_PMGR = (0x26) # macro -NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6) # macro -NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6) # macro -NV2080_CTRL_POWER = (0x27) # macro -NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7) # macro -NV2080_CTRL_LPWR = (0x28) # macro -NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8) # macro -NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8) # macro -NV2080_CTRL_ACR = (0x29) # macro -NV2080_CTRL_CE = (0x2A) # macro -NV2080_CTRL_SPI = (0x2B) # macro -NV2080_CTRL_NVLINK = (0x30) # macro -NV2080_CTRL_FLCN = (0x31) # macro -NV2080_CTRL_VOLT = (0x32) # macro -NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2) # macro -NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2) # macro -NV2080_CTRL_FAS = (0x33) # macro -NV2080_CTRL_ECC = (0x34) # macro -NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4) # macro -NV2080_CTRL_FLA = (0x35) # macro -NV2080_CTRL_GSP = (0x36) # macro -NV2080_CTRL_NNE = (0x37) # macro -NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7) # macro -NV2080_CTRL_GRMGR = (0x38) # macro -NV2080_CTRL_UCODE_FUZZER = (0x39) # macro -NV2080_CTRL_DMABUF = (0x3A) # macro -NV2080_CTRL_BIF = (0x3B) # macro -NV2080_CTRL_OS_WINDOWS = (0x3F) # macro -NV2080_CTRL_OS_MACOS = (0x3E) # macro -NV2080_CTRL_OS_UNIX = (0x3D) # macro -NV2080_CTRL_CMD_NULL = (0x20800000) # macro -# def NV0080_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x0080,NV0080_CTRL_##cat,idx) -NV0080_CTRL_RESERVED = (0x00) # macro -NV0080_CTRL_BIF = (0x01) # macro -NV0080_CTRL_GPU = (0x02) # macro -NV0080_CTRL_CLK = (0x10) # macro -NV0080_CTRL_GR = (0x11) # macro -NV0080_CTRL_CIPHER = (0x12) # macro -NV0080_CTRL_FB = (0x13) # macro -NV0080_CTRL_HOST = (0x14) # macro -NV0080_CTRL_VIDEO = (0x15) # macro -NV0080_CTRL_FIFO = (0x17) # macro -NV0080_CTRL_DMA = (0x18) # macro -NV0080_CTRL_PERF = (0x19) # macro -NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99) # macro -NV0080_CTRL_MSENC = (0x1B) # macro -NV0080_CTRL_BSP = (0x1C) # macro -NV0080_CTRL_RC = (0x1D) # macro -NV0080_CTRL_OS_UNIX = (0x1E) # macro -NV0080_CTRL_NVJPG = (0x1F) # macro -NV0080_CTRL_INTERNAL = (0x20) # macro -NV0080_CTRL_NVLINK = (0x21) # macro -NV0080_CTRL_CMD_NULL = (0x800000) # macro -# def NV0080_CTRL_GET_CAP(cat, tbl, c): # macro -# return NV0080_CTRL_##cat##_GET_CAP(tbl,NV0080_CTRL_##cat##_CAPS_##c) -NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102) # macro -NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2) # macro -# def NV0080_CTRL_GR_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -NV0080_CTRL_GR_CAPS_TBL_SIZE = 23 # macro -NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) # macro -NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) # macro -NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) # macro -NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) # macro -NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) # macro -NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) # macro -NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) # macro -NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) # macro -NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) # macro -NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) # macro -NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) # macro -NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) # macro -NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) # macro -NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) # macro -NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) # macro -NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) # macro -NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) # macro -NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) # macro -NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) # macro -NV0080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) # macro -NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) # macro -NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3a) # macro -NV0080_CTRL_CMD_GR_GET_INFO = (0x801104) # macro -NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107) # macro -NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108) # macro -NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8) # macro -NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109) # macro -NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110) # macro -NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # macro -# NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE = 1 : 0 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2 # macro -# NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE = 31 : 0 # macro -# NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID = 31 : 0 # macro -NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) # macro -NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) # macro -NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) # macro -NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) # macro -NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) # macro -NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) # macro -NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) # macro -NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) # macro -NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) # macro -NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) # macro -NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) # macro -NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) # macro -NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) # macro -NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) # macro -NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) # macro -NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) # macro -NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) # macro -NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) # macro -NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) # macro -NV2080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) # macro -NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) # macro -NV2080_CTRL_GR_INFO_MAX_SIZE = (0x3a) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = ((0x00000502)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = ((0x00000503)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = ((0x00000601)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = ((0x00000602)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = ((0x00000701)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = ((0x00000702)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = ((0x00000703)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = ((0x00000705)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = ((0x00000802)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = ((0x00000806)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = ((0x00000807)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = ((0x00000808)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = ((0x00000809)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = ((0x00000900)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = ((0x00000A00)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = ((0x00000A01)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = ((0x00000A04)) # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D = 0 : 0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D = 1 : 1 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE = 2 : 2 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M = 3 : 3 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1 # macro -NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201) # macro -NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205) # macro -NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002) # macro -NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206) # macro -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED = True # macro -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207) # macro -NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000) # macro -NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001) # macro -NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002) # macro -NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208) # macro -NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209) # macro -NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a) # macro -NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128 # macro -NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a) # macro -NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e) # macro -NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000) # macro -NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f) # macro -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 240 # macro -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10) # macro -# NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP = 0 : 0 # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001) # macro -# NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP = 1 : 1 # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002) # macro -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211) # macro -NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212) # macro -NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000) # macro -NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213) # macro -NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215) # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15) # macro -# NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET = 0 : 0 # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000) # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218) # macro -NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64 # macro -NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219) # macro -NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0 # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1 # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2 # macro -NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b) # macro -NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512 # macro -NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF # macro -NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B) # macro -NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c) # macro -NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C) # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT = 10 # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA = (0x2080121d) # macro -NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID = (0x1D) # macro -NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e) # macro -NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f) # macro -NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220) # macro -NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64 # macro -NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221) # macro -NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222) # macro -NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227) # macro -NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228) # macro -NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a) # macro -NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b) # macro -NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c) # macro -NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d) # macro -NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D) # macro -NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231) # macro -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232) # macro -NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32) # macro -NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233) # macro -NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234) # macro -NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235) # macro -NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35) # macro -NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236) # macro -NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237) # macro -NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238) # macro -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239) # macro -NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b) # macro -NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b) # macro -NV_GRID_LICENSE_INFO_MAX_LENGTH = (128) # macro -NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # macro -NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0" # macro -NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # macro -NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0" # macro -NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0" # macro -NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation" # macro -NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming" # macro -NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC" # macro -NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications" # macro -NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server" # macro -# NV2080_CTRL_GPU_INFO_INDEX_INDEX = 23 : 0 # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004) # macro -NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012) # macro -NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013) # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b) # macro -NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027) # macro -NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a) # macro -NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030) # macro -NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED = (0x00000033) # macro -NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f) # macro -NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000041) # macro -# NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID = 30 : 24 # macro -# NV2080_CTRL_GPU_INFO_INDEX_RESERVED = 31 : 31 # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003) # macro -NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004) # macro -NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001) # macro -# NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID = 31 : 1 # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101) # macro -NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102) # macro -NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110) # macro -NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040) # macro -# NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE = 31 : 0 # macro -NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000) # macro -NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE = (0x00000001) # macro -NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111) # macro -NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112) # macro -NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007) # macro -NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118) # macro -NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120) # macro -NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001) # macro -NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003) # macro -NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122) # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123) # macro -NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170) # macro -NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54 # macro -NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124) # macro -NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125) # macro -NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_GPU_QUERY_MODE = (0x20800128) # macro -NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE = (0x00000002) # macro -NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12 # macro -NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16 # macro -NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b) # macro -NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c) # macro -NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE = 1 : 0 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE = 2 : 2 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX = 3 : 3 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f) # macro -NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D) # macro -NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000024) # macro -# NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE = 0 : 0 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003) # macro -NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131) # macro -NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001) # macro -NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002) # macro -# NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE = 0 : 0 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137) # macro -NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138) # macro -NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139) # macro -NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f) # macro -NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018) # macro -NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010) # macro -NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014) # macro -NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006) # macro -NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014) # macro -NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142) # macro -NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143) # macro -NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002) # macro -NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144) # macro -NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147) # macro -NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020) # macro -NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a) # macro -NV2080_GPU_MAX_GID_LENGTH = (0x000000100) # macro -NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010) # macro -NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A) # macro -# NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT = 1 : 0 # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE = 2 : 2 # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b) # macro -NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3 # macro -NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B) # macro -NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c) # macro -NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C) # macro -NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005) # macro -NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0 # macro -NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1 # macro -NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153) # macro -NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154) # macro -NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155) # macro -NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156) # macro -NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16 # macro -NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157) # macro -NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a) # macro -NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100) # macro -NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b) # macro -NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160) # macro -NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60) # macro -NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167) # macro -NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168) # macro -NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169) # macro -NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8) # macro -NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b) # macro -NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B) # macro -NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c) # macro -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D) # macro -NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200 # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e) # macro -NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F) # macro -NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f) # macro -NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172) # macro -NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173) # macro -NV_GI_UUID_LEN = 16 # macro -PARTITIONID_INVALID = 0xFFFFFFFF # macro -NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF # macro -NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008 # macro -NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009 # macro -NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008 # macro -NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x0000000c # macro -NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE = 1 : 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE = 4 : 2 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE = 7 : 5 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8 # macro -NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 40 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA = 30 : 30 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN = 31 : 31 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_FULL)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_FULL)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_HALF)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_HALF)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_HALF)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_MINI_HALF)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_QUARTER)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_QUARTER)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_QUARTER)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_MINI_QUARTER)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_EIGHTH)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_EIGHTH)) # macro -NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174) # macro -NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175) # macro -NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176) # macro -NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32 # macro -NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177) # macro -NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178) # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B) # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010 # macro -NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256 # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c) # macro -NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6) # macro -NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6) # macro -NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e) # macro -NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E) # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000 # macro -NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181) # macro -NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182) # macro -NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183) # macro -# NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING = 1 : 0 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185) # macro -NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188) # macro -NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A) # macro -NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a) # macro -NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B) # macro -NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b) # macro -NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d) # macro -NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950 # macro -NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D) # macro -NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000) # macro -NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001) # macro -NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000) # macro -NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = (0x00000000) # macro -NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e) # macro -NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200 # macro -NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192) # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0 # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1 # macro -NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195) # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32 # macro -NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95) # macro -NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196) # macro -NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197) # macro -NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97) # macro -NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198) # macro -NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98) # macro -NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR = (0x20800199) # macro -NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x99) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b) # macro -NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8 # macro -NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B) # macro -NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c) # macro -NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d) # macro -NV2080_CTRL_REG_OPS_ARRAY_MAX = 100 # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D) # macro -NV2080_GET_P2P_CAPS_UUID_LEN = 16 # macro -NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0) # macro -NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0) # macro -NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2) # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3 # macro -NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16 # macro -# NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED = NVBIT64 ( 0 ) # macro -# NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED = NVBIT64 ( 1 ) # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW = 1 : 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE = 3 : 2 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY = 5 : 4 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY = 7 : 6 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2 # macro -NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3) # macro -NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3) # macro -NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4) # macro -GPU_PART_NUMBER_FMT = "%04X-%s-%X%X" # macro -NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004 # macro -NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4) # macro -NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5) # macro -NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8) # macro -NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50 # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6) # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7) # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8) # macro -NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9) # macro -NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa) # macro -NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab) # macro -NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB) # macro -NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac) # macro -NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad) # macro -NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae) # macro -NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af) # macro -NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40 # macro -NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0) # macro -NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0) # macro -NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1) # macro -NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1) # macro -NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2) # macro -NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2) # macro -NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4) # macro -NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4) # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2 # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18) # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a) # macro -NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3) # macro -NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5) # macro -NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5) # macro -NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7) # macro -NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7) # macro -# NV0000_BUSDEVICE_DOMAIN = 31 : 16 # macro -# NV0000_BUSDEVICE_BUS = 15 : 8 # macro -# NV0000_BUSDEVICE_DEVICE = 7 : 0 # macro -# def GPU_32_BIT_ID_DECODE_DOMAIN(gpuId): # macro -# return (NvU16)DRF_VAL(0000,_BUSDEVICE,_DOMAIN,gpuId); -# def GPU_32_BIT_ID_DECODE_BUS(gpuId): # macro -# return (NvU8)DRF_VAL(0000,_BUSDEVICE,_BUS,gpuId); -# def GPU_32_BIT_ID_DECODE_DEVICE(gpuId): # macro -# return (NvU8)DRF_VAL(0000,_BUSDEVICE,_DEVICE,gpuId); -NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02) # macro -NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03) # macro -NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04) # macro -NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05) # macro -NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5) # macro -NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206) # macro -NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6) # macro -class struct_NV0080_CTRL_GR_ROUTE_INFO(Structure): - pass - -struct_NV0080_CTRL_GR_ROUTE_INFO._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_ROUTE_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('route', ctypes.c_uint64), -] - -NV0080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO -class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_GR_GET_CAPS_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_PARAMS -class struct_NVXXXX_CTRL_XXX_INFO(Structure): - pass - -struct_NVXXXX_CTRL_XXX_INFO._pack_ = 1 # source:False -struct_NVXXXX_CTRL_XXX_INFO._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -NV0080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_GET_INFO_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grInfoList', ctypes.POINTER(None)), -] - -NV0080_CTRL_GR_GET_INFO_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_PARAMS - -# values for enumeration 'NV0080_CTRL_GR_TPC_PARTITION_MODE' -NV0080_CTRL_GR_TPC_PARTITION_MODE__enumvalues = { - 0: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 1: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', - 2: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', -} -NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0 -NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1 -NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2 -NV0080_CTRL_GR_TPC_PARTITION_MODE = ctypes.c_uint32 # enum -class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS._fields_ = [ - ('hChannelGroup', ctypes.c_uint32), - ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE), - ('bEnableAllTpcs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), -] - -NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 23), - ('PADDING_0', ctypes.c_ubyte), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), - ('bCapsPopulated', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV0080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('grInfoList', struct_NVXXXX_CTRL_XXX_INFO * 58), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), -] - -NV0080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS -NV2080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO -NV2080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_INFO_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grInfoList', ctypes.POINTER(None)), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_INFO_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('hShareClient', ctypes.c_uint32), - ('hShareChannel', ctypes.c_uint32), - ('zcullMode', ctypes.c_uint32), -] - -NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._fields_ = [ - ('widthAlignPixels', ctypes.c_uint32), - ('heightAlignPixels', ctypes.c_uint32), - ('pixelSquaresByAliquots', ctypes.c_uint32), - ('aliquotTotal', ctypes.c_uint32), - ('zcullRegionByteMultiplier', ctypes.c_uint32), - ('zcullRegionHeaderSize', ctypes.c_uint32), - ('zcullSubregionHeaderSize', ctypes.c_uint32), - ('subregionCount', ctypes.c_uint32), - ('subregionWidthAlignPixels', ctypes.c_uint32), - ('subregionHeightAlignPixels', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('pmMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), - ('zcullMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), - ('pmMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), -] - -NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS -class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._fields_ = [ - ('mapValueCount', ctypes.c_uint32), - ('mapValues', ctypes.c_ubyte * 128), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('smpcMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcId', ctypes.c_uint32), -] - -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._fields_ = [ - ('smId', struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0 * 240), - ('smCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS -class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS' -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS__enumvalues = { - 0: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', - 1: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', - 2: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', - 3: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', - 4: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', - 5: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', - 6: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', - 7: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', - 8: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', - 9: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', -} -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vMemPtrs', ctypes.c_uint64 * 9), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS -class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('samplingMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._fields_ = [ - ('ropUnitCount', ctypes.c_uint32), - ('ropOperationsFactor', ctypes.c_uint32), - ('ropOperationsCount', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('saveCnt', ctypes.c_uint32), - ('restoreCnt', ctypes.c_uint32), - ('wfiSaveCnt', ctypes.c_uint32), - ('ctaSaveCnt', ctypes.c_uint32), - ('cilpSaveCnt', ctypes.c_uint32), - ('gfxpSaveCnt', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS -class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalBufferSize', ctypes.c_uint64), -] - -NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(Structure): - pass - -struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._fields_ = [ - ('alignment', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bufferHandle', ctypes.POINTER(None)), - ('pageCount', ctypes.c_uint64), - ('physAddr', ctypes.c_uint64), - ('bufferType', ctypes.c_uint32), - ('aperture', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('bIsContigous', ctypes.c_ubyte), - ('bGlobalBuffer', ctypes.c_ubyte), - ('bLocalBuffer', ctypes.c_ubyte), - ('bDeviceDescendant', ctypes.c_ubyte), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GR_CTX_BUFFER_INFO = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO -PNV2080_CTRL_GR_CTX_BUFFER_INFO = ctypes.POINTER(struct_NV2080_CTRL_GR_CTX_BUFFER_INFO) -class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('bufferCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ctxBufferInfo', struct_NV2080_CTRL_GR_CTX_BUFFER_INFO * 64), -] - -NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0._fields_ = [ - ('gpcId', ctypes.c_uint16), - ('localTpcId', ctypes.c_uint16), - ('localSmId', ctypes.c_uint16), - ('globalTpcId', ctypes.c_uint16), - ('virtualGpcId', ctypes.c_uint16), - ('migratableTpcId', ctypes.c_uint16), -] - -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [ - ('globalSmId', struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0 * 512), - ('numSm', ctypes.c_uint16), - ('numTpc', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS -class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._fields_ = [ - ('chID', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC(Structure): - pass - -struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._fields_ = [ - ('errorCounter', ctypes.c_uint64), - ('errorTimestamp', ctypes.c_uint64), - ('warningCounter', ctypes.c_uint64), - ('warningTimestamp', ctypes.c_uint64), -] - -NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('tpc', struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC * 10), - ] - -NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('gpc', struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC * 10), - ] - -NV2080_CTRL_GR_VAT_ALARM_DATA = struct_NV2080_CTRL_GR_VAT_ALARM_DATA -class struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._fields_ = [ - ('smVatAlarm', NV2080_CTRL_GR_VAT_ALARM_DATA), - ('maxGpcCount', ctypes.c_uint32), - ('maxTpcPerGpcCount', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS -PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS) -class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._fields_ = [ - ('attribBufferSize', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._fields_ = [ - ('maxSlots', ctypes.c_uint32), - ('slotStride', ctypes.c_uint32), - ('ctrlStructSize', ctypes.c_uint64), - ('ctrlStructAlign', ctypes.c_uint64), - ('poolSize', ctypes.c_uint64), - ('poolAlign', ctypes.c_uint64), -] - -NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._fields_ = [ - ('maxSlots', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._fields_ = [ - ('numSlots', ctypes.c_uint32), - ('slots', ctypes.c_uint32 * 64), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._fields_ = [ - ('numSlots', ctypes.c_uint32), - ('slots', ctypes.c_uint32 * 64), - ('bRemoveSpecificSlots', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS -NV2080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS -NV2080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GR_GET_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_TPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS -NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('engineId', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('bInfoPopulated', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS -class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('imla0', ctypes.c_ubyte), - ('fmla16', ctypes.c_ubyte), - ('dp', ctypes.c_ubyte), - ('fmla32', ctypes.c_ubyte), - ('ffma', ctypes.c_ubyte), - ('imla1', ctypes.c_ubyte), - ('imla2', ctypes.c_ubyte), - ('imla3', ctypes.c_ubyte), - ('imla4', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - -# values for enumeration 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD' -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD__enumvalues = { - 0: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', - 1: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', - 2: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', - 3: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', -} -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS -class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._fields_ = [ - ('physSyspipeId', ctypes.c_uint32), - ('gpcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcId', ctypes.c_uint32), - ('ppcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_PPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('numTpcs', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS -class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('zcullMode', ctypes.c_uint32), - ('pmMode', ctypes.c_uint32), - ('smpcMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('gfxpPreemptMode', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS -NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS -class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('zcullMask', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS - -# values for enumeration 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE' -NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE__enumvalues = { - 0: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', - 1: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', - 2: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', - 3: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', - 4: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', - 5: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', -} -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('reasonCode', ctypes.c_uint32), -] - -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS -class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('physGfxGpcMask', ctypes.c_uint32), - ('numGfxTpc', ctypes.c_uint32), -] - -NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [ - ('gpc', ctypes.c_uint32), - ('tpcReconfigMask', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS -NV2080_CTRL_GPU_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_INFO_PARAMS._fields_ = [ - ('gpuInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_GPU_GET_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS._fields_ = [ - ('gpuInfoListSize', ctypes.c_uint32), - ('gpuInfoList', struct_NVXXXX_CTRL_XXX_INFO * 65), -] - -NV2080_CTRL_GPU_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(Structure): - pass - -class union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(Union): - pass - -union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._pack_ = 1 # source:False -union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._fields_ = [ - ('ascii', ctypes.c_ubyte * 64), - ('unicode', ctypes.c_uint16 * 64), -] - -struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS._fields_ = [ - ('gpuNameStringFlags', ctypes.c_uint32), - ('gpuNameString', union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString), -] - -NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS -class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS._fields_ = [ - ('gpuShortNameString', ctypes.c_ubyte * 64), -] - -NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS -class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_POWER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_POWER_PARAMS._fields_ = [ - ('target', ctypes.c_uint32), - ('newLevel', ctypes.c_uint32), - ('oldLevel', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_POWER_PARAMS = struct_NV2080_CTRL_GPU_SET_POWER_PARAMS -class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SDM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_SDM_PARAMS._fields_ = [ - ('subdeviceMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_SDM_PARAMS = struct_NV2080_CTRL_GPU_GET_SDM_PARAMS -class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_SDM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_SDM_PARAMS._fields_ = [ - ('subdeviceMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_SDM_PARAMS = struct_NV2080_CTRL_GPU_SET_SDM_PARAMS -class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_REG_OP(Structure): - pass - -struct_NV2080_CTRL_GPU_REG_OP._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_REG_OP._fields_ = [ - ('regOp', ctypes.c_ubyte), - ('regType', ctypes.c_ubyte), - ('regStatus', ctypes.c_ubyte), - ('regQuad', ctypes.c_ubyte), - ('regGroupMask', ctypes.c_uint32), - ('regSubGroupMask', ctypes.c_uint32), - ('regOffset', ctypes.c_uint32), - ('regValueHi', ctypes.c_uint32), - ('regValueLo', ctypes.c_uint32), - ('regAndNMaskHi', ctypes.c_uint32), - ('regAndNMaskLo', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_REG_OP = struct_NV2080_CTRL_GPU_REG_OP -class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('reserved00', ctypes.c_uint32 * 2), - ('regOpCount', ctypes.c_uint32), - ('regOps', ctypes.POINTER(None)), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('engineList', ctypes.POINTER(None)), -] - -NV2080_CTRL_GPU_GET_ENGINES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineList', ctypes.c_uint32 * 84), -] - -NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('numClasses', ctypes.c_uint32), - ('classList', ctypes.POINTER(None)), -] - -NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('mmuFaultId', ctypes.c_uint32), - ('bSubcontextSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_QUERY_MODE_PARAMS = struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(Structure): - pass - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY._fields_ = [ - ('gpuPhysAddr', ctypes.c_uint64), - ('gpuVirtAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('bufferId', ctypes.c_uint16), - ('bInitialize', ctypes.c_ubyte), - ('bNonmapped', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('virtAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('entryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('promoteEntry', struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY * 16), -] - -NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS -PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_EVICT_CTX_PARAMS = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS -PNV2080_CTRL_GPU_EVICT_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('physAddress', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('hDmaHandle', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS -PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS._fields_ = [ - ('eccIntrStatus', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS._fields_ = [ - ('count', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS -class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS._fields_ = [ - ('enabled', ctypes.c_ubyte), - ('scrubComplete', ctypes.c_ubyte), - ('supported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 5), - ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), -] - -NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS -class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS._fields_ = [ - ('units', struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS * 36), - ('bFatalPoisonError', ctypes.c_ubyte), - ('uncorrectableError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS._fields_ = [ - ('rules', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS._fields_ = [ - ('rules', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS._fields_ = [ - ('currentConfiguration', ctypes.c_uint32), - ('defaultConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS._fields_ = [ - ('newConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS._fields_ = [ - ('statuses', ctypes.c_uint32), - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS = struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS._fields_ = [ - ('gpcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('zcullMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS._fields_ = [ - ('buildDate', ctypes.c_uint32), - ('marketingName', ctypes.c_ubyte * 24), - ('serialNumber', ctypes.c_ubyte * 16), - ('memoryManufacturer', ctypes.c_ubyte), - ('memoryPartID', ctypes.c_ubyte * 20), - ('memoryDateCode', ctypes.c_ubyte * 6), - ('productPartNumber', ctypes.c_ubyte * 20), - ('boardRevision', ctypes.c_ubyte * 3), - ('boardType', ctypes.c_ubyte), - ('board699PartNumber', ctypes.c_ubyte * 20), - ('board965PartNumber', ctypes.c_ubyte * 20), - ('PADDING_0', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_PARAMS -class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS -class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS._fields_ = [ - ('currentMode', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('partnershipClassId', ctypes.c_uint32), - ('runqueue', ctypes.c_uint32), - ('numPartners', ctypes.c_uint32), - ('partnerList', ctypes.c_uint32 * 32), -] - -NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS -class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 256), -] - -NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS._fields_ = [ - ('objectType', ctypes.c_char * 3), - ('version', ctypes.c_ubyte), - ('subversion', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS._fields_ = [ - ('isOptimusEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS = struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS._fields_ = [ - ('targetEngine', ctypes.c_uint32), - ('ipVersion', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS -class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('bSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS -class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_GPU_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS -NV2080_CTRL_GPU_GET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS -NV2080_CTRL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS._fields_ = [ - ('version', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS._fields_ = [ - ('fwVersion', ctypes.c_uint32), - ('oemVersion', ctypes.c_ubyte), - ('siliconRevision', ctypes.c_ubyte), - ('hwbcResourceType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS._fields_ = [ - ('bridgeCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('hPhysicalBridges', ctypes.c_uint32 * 100), - ('bridgeList', struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS * 100), -] - -NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS._fields_ = [ - ('bus', ctypes.c_ubyte), - ('device', ctypes.c_ubyte), - ('func', ctypes.c_ubyte), - ('oemVersion', ctypes.c_ubyte), - ('siliconRevision', ctypes.c_ubyte), - ('hwbcResourceType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('domain', ctypes.c_uint32), - ('fwVersion', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS._fields_ = [ - ('bridgeCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('physicalBridgeIds', ctypes.c_uint32 * 100), - ('bridgeList', struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS * 100), -] - -NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS = struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS._fields_ = [ - ('scrubberStatus', ctypes.c_uint32), - ('remainingTimeMs', ctypes.c_uint32), - ('scrubStartAddr', ctypes.c_uint64), - ('scrubEndAddr', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS._fields_ = [ - ('minStartAddr', ctypes.c_uint64), - ('maxEndAddr', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('numPesInGpc', ctypes.c_uint32), - ('activePesMask', ctypes.c_uint32), - ('maxTpcPerGpcCount', ctypes.c_uint32), - ('tpcToPesMap', ctypes.c_uint32 * 10), -] - -NV2080_CTRL_GPU_GET_PES_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS._fields_ = [ - ('oemInfo', ctypes.c_ubyte * 504), -] - -NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS - -# values for enumeration 'NV2080_CTRL_VPR_INFO_QUERY_TYPE' -NV2080_CTRL_VPR_INFO_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', - 1: 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', -} -NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0 -NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1 -NV2080_CTRL_VPR_INFO_QUERY_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS._fields_ = [ - ('queryType', NV2080_CTRL_VPR_INFO_QUERY_TYPE), - ('bIsVprEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vprStartAddressInBytes', ctypes.c_uint64), - ('vprEndAddressInBytes', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS - -# values for enumeration 'NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE' -NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', - 1: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', - 2: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', -} -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0 -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1 -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2 -NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS._fields_ = [ - ('queryType', NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE), - ('encoderCapacity', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS._fields_ = [ - ('encoderSessionCount', ctypes.c_uint32), - ('averageEncodeFps', ctypes.c_uint32), - ('averageEncodeLatency', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS -class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(Structure): - pass - -struct_NV2080_CTRL_NVENC_SW_SESSION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVENC_SW_SESSION_INFO._fields_ = [ - ('processId', ctypes.c_uint32), - ('subProcessId', ctypes.c_uint32), - ('sessionId', ctypes.c_uint32), - ('codecType', ctypes.c_uint32), - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), - ('averageEncodeFps', ctypes.c_uint32), - ('averageEncodeLatency', ctypes.c_uint32), -] - -NV2080_CTRL_NVENC_SW_SESSION_INFO = struct_NV2080_CTRL_NVENC_SW_SESSION_INFO -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS._fields_ = [ - ('sessionInfoTblEntry', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sessionInfoTbl', ctypes.POINTER(None)), -] - -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS._fields_ = [ - ('fabricBaseAddr', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS._fields_ = [ - ('handle', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS = struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS -class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS._fields_ = [ - ('statusMask', ctypes.c_uint32), - ('xusbData', ctypes.c_uint32), - ('ppcData', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_PARTITION_SPAN(Structure): - pass - -struct_NV2080_CTRL_GPU_PARTITION_SPAN._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PARTITION_SPAN._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_PARTITION_SPAN = struct_NV2080_CTRL_GPU_PARTITION_SPAN -class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(Structure): - pass - -struct_NV2080_CTRL_EXEC_PARTITION_SPAN._pack_ = 1 # source:False -struct_NV2080_CTRL_EXEC_PARTITION_SPAN._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), -] - -NV2080_CTRL_EXEC_PARTITION_SPAN = struct_NV2080_CTRL_EXEC_PARTITION_SPAN -class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_PARTITION_INFO._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('uuid', ctypes.c_ubyte * 16), - ('partitionFlag', ctypes.c_uint32), - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('placement', NV2080_CTRL_GPU_PARTITION_SPAN), -] - -NV2080_CTRL_GPU_SET_PARTITION_INFO = struct_NV2080_CTRL_GPU_SET_PARTITION_INFO -class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS._fields_ = [ - ('partitionCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('partitionInfo', struct_NV2080_CTRL_GPU_SET_PARTITION_INFO * 8), -] - -NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PARTITION_INFO._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('partitionFlag', ctypes.c_uint32), - ('grEngCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcsPerGr', ctypes.c_uint32 * 8), - ('virtualGpcsPerGr', ctypes.c_uint32 * 8), - ('gfxGpcPerGr', ctypes.c_uint32 * 8), - ('veidsPerGr', ctypes.c_uint32 * 8), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memSize', ctypes.c_uint64), - ('span', NV2080_CTRL_GPU_PARTITION_SPAN), - ('bValid', ctypes.c_ubyte), - ('bPartitionError', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 6), - ('validCTSIdMask', ctypes.c_uint64), - ('validGfxCTSIdMask', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_GET_PARTITION_INFO = struct_NV2080_CTRL_GPU_GET_PARTITION_INFO -class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS._fields_ = [ - ('queryPartitionInfo', struct_NV2080_CTRL_GPU_GET_PARTITION_INFO * 8), - ('validPartitionCount', ctypes.c_uint32), - ('bGetAllPartitionInfo', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('gpcCountPerSmcEng', ctypes.c_uint32 * 8), - ('updateSmcEngMask', ctypes.c_uint32), - ('bUseAllGPCs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS -class struct_NV2080_CTRL_GPU_FAULT_PACKET(Structure): - pass - -struct_NV2080_CTRL_GPU_FAULT_PACKET._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_FAULT_PACKET._fields_ = [ - ('data', ctypes.c_ubyte * 32), -] - -NV2080_CTRL_GPU_FAULT_PACKET = struct_NV2080_CTRL_GPU_FAULT_PACKET -class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('faultPacket', NV2080_CTRL_GPU_FAULT_PACKET), - ] - -NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS = struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS -NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS._fields_ = [ - ('engineList', ctypes.c_uint32 * 84), - ('runlistPriBase', ctypes.c_uint32 * 84), - ('runlistId', ctypes.c_uint32 * 84), -] - -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS -class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS._fields_ = [ - ('engineList', ctypes.c_uint32 * 84), - ('hwEngineID', ctypes.c_uint32 * 84), -] - -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS._fields_ = [ - ('sessionCount', ctypes.c_uint32), - ('averageFPS', ctypes.c_uint32), - ('averageLatency', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS -class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(Structure): - pass - -struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO._fields_ = [ - ('processId', ctypes.c_uint32), - ('subProcessId', ctypes.c_uint32), - ('vgpuInstanceId', ctypes.c_uint32), - ('sessionId', ctypes.c_uint32), - ('sessionType', ctypes.c_uint32), - ('displayOrdinal', ctypes.c_uint32), - ('sessionFlags', ctypes.c_uint32), - ('hMaxResolution', ctypes.c_uint32), - ('vMaxResolution', ctypes.c_uint32), - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), - ('averageFPS', ctypes.c_uint32), - ('averageLatency', ctypes.c_uint32), -] - -NV2080_CTRL_NVFBC_SW_SESSION_INFO = struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO -class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS._fields_ = [ - ('sessionInfoCount', ctypes.c_uint32), - ('sessionInfoTbl', struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO * 256), -] - -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS._fields_ = [ - ('firstAsyncCEIdx', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS = struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS -class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS._fields_ = [ - ('vmmuSegmentSize', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS -class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('partitionCount', ctypes.c_uint32), - ('availableSpans', struct_NV2080_CTRL_GPU_PARTITION_SPAN * 8), - ('availableSpansCount', ctypes.c_uint32), - ('totalPartitionCount', ctypes.c_uint32), - ('totalSpans', struct_NV2080_CTRL_GPU_PARTITION_SPAN * 8), - ('totalSpansCount', ctypes.c_uint32), - ('bStaticInfo', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS -NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS._fields_ = [ - ('partitioningMode', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS -class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('grCount', ctypes.c_uint32), - ('gfxGrCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memorySize', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO -class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS._fields_ = [ - ('descCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('partitionDescs', struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO * 40), -] - -NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS._fields_ = [ - ('maxSupportedPageSize', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS -class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS = struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS -class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32 * 9), - ('partitionCount', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS = struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS._fields_ = [ - ('idType', ctypes.c_uint32), - ('id', ctypes.c_uint32), - ('pidTblCount', ctypes.c_uint32), - ('pidTbl', ctypes.c_uint32 * 950), -] - -NV2080_CTRL_GPU_GET_PIDS_PARAMS = struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS -class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(Structure): - pass - -struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO._fields_ = [ - ('computeInstanceId', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), -] - -NV2080_CTRL_SMC_SUBSCRIPTION_INFO = struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO -class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(Structure): - pass - -struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA._fields_ = [ - ('memPrivate', ctypes.c_uint64), - ('memSharedOwned', ctypes.c_uint64), - ('memSharedDuped', ctypes.c_uint64), - ('protectedMemPrivate', ctypes.c_uint64), - ('protectedMemSharedOwned', ctypes.c_uint64), - ('protectedMemSharedDuped', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA = struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA -class union_NV2080_CTRL_GPU_PID_INFO_DATA(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('vidMemUsage', NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA), - ] - -NV2080_CTRL_GPU_PID_INFO_DATA = union_NV2080_CTRL_GPU_PID_INFO_DATA -class struct_NV2080_CTRL_GPU_PID_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_PID_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PID_INFO._fields_ = [ - ('pid', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('result', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('data', NV2080_CTRL_GPU_PID_INFO_DATA), - ('smcSubscription', NV2080_CTRL_SMC_SUBSCRIPTION_INFO), -] - -NV2080_CTRL_GPU_PID_INFO = struct_NV2080_CTRL_GPU_PID_INFO -class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS._fields_ = [ - ('pidInfoListCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pidInfoList', struct_NV2080_CTRL_GPU_PID_INFO * 200), -] - -NV2080_CTRL_GPU_GET_PID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS -class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS._fields_ = [ - ('faultType', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS - -# values for enumeration 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE' -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE__enumvalues = { - 0: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', - 1: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', - 2: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', - 3: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', - 4: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', -} -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4 -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(Structure): - pass - -class union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('timeslice', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE), - ] - -struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG._fields_ = [ - ('type', ctypes.c_uint32), - ('data', union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data), -] - -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG = struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG -class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('config', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG), - ] - -NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS -class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS._fields_ = [ - ('numConfigs', ctypes.c_uint32), - ('configList', struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG * 32), -] - -NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS -class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GFID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_GFID_PARAMS._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('device', ctypes.c_ubyte), - ('func', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('gfid', ctypes.c_uint32), - ('gfidMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_GFID_PARAMS = struct_NV2080_CTRL_GPU_GET_GFID_PARAMS -class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('fabricPartitionId', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS = struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS -class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS._fields_ = [ - ('addressStart', ctypes.c_uint64), - ('addressLength', ctypes.c_uint64), - ('protection', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS = struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS -class struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS._fields_ = [ - ('egmGpaFabricBaseAddr', ctypes.c_uint64), -] - -NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineList', ctypes.c_uint32 * 200), - ('PADDING_0', ctypes.c_ubyte * 4), - ('engineStateLoadTime', ctypes.c_uint64 * 200), - ('engineIsInit', ctypes.c_ubyte * 200), -] - -NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS -class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineID', ctypes.c_uint32 * 200), - ('engineName', ctypes.c_char * 100 * 200), -] - -NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS -class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('reserved00', ctypes.c_uint32 * 2), - ('regOpCount', ctypes.c_uint32), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 100), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS -class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuUuid', ctypes.c_ubyte * 16), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerId', ctypes.c_uint32), - ('busEgmPeerId', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO -class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS._fields_ = [ - ('bAllCaps', ctypes.c_ubyte), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('peerGpuCount', ctypes.c_uint32), - ('peerGpuCaps', struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO * 32), -] - -NV2080_CTRL_GET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(Structure): - pass - -struct_NV2080_CTRL_GPU_COMPUTE_PROFILE._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_COMPUTE_PROFILE._fields_ = [ - ('computeSize', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_COMPUTE_PROFILE = struct_NV2080_CTRL_GPU_COMPUTE_PROFILE -class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('profileCount', ctypes.c_uint32), - ('profiles', struct_NV2080_CTRL_GPU_COMPUTE_PROFILE * 8), -] - -NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS -class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('state', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('status', ctypes.c_uint32), - ('clusterUuid', ctypes.c_ubyte * 16), - ('fabricPartitionId', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 6), - ('fabricCaps', ctypes.c_uint64), - ('fabricCliqueId', ctypes.c_uint32), - ('fabricHealthMask', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS._fields_ = [ - ('pciDevId', ctypes.c_uint32), - ('chipSku', ctypes.c_ubyte * 4), - ('chipMajor', ctypes.c_uint32), - ('chipMinor', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS = struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS -class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS = struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS -class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('regOpCount', ctypes.c_uint32), - ('smIds', ctypes.c_uint32 * 50), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 50), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), -] - -NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS -NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS -NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS -NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS -class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS._fields_ = [ - ('bResetRequired', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS._fields_ = [ - ('bDrainRecommended', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS._fields_ = [ - ('sessionInfoTblEntry', ctypes.c_uint32), - ('sessionInfoTbl', struct_NV2080_CTRL_NVENC_SW_SESSION_INFO * 512), -] - -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO._fields_ = [ - ('engDesc', ctypes.c_uint32), - ('ctxAttr', ctypes.c_uint32), - ('ctxBufferSize', ctypes.c_uint32), - ('addrSpaceList', ctypes.c_uint32), - ('registerBase', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO = struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO -class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS._fields_ = [ - ('numConstructedFalcons', ctypes.c_uint32), - ('constructedFalconsTable', struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO * 64), -] - -NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS -class struct_NV2080_VF_MSIX_CAPS(Structure): - pass - -struct_NV2080_VF_MSIX_CAPS._pack_ = 1 # source:False -struct_NV2080_VF_MSIX_CAPS._fields_ = [ - ('msix_header', ctypes.c_uint32), - ('msix_table', ctypes.c_uint32), - ('msix_pba', ctypes.c_uint32), -] - -NV2080_VF_MSIX_CAPS = struct_NV2080_VF_MSIX_CAPS -class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('vfMsixCap', NV2080_VF_MSIX_CAPS), -] - -NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS - -# values for enumeration 'NV2080_CTRL_GPU_RECOVERY_ACTION' -NV2080_CTRL_GPU_RECOVERY_ACTION__enumvalues = { - 0: 'NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', - 1: 'NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', - 2: 'NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', - 3: 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', - 4: 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', -} -NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0 -NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1 -NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2 -NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3 -NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4 -NV2080_CTRL_GPU_RECOVERY_ACTION = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('action', NV2080_CTRL_GPU_RECOVERY_ACTION), - ] - -NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS = struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS -class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS._fields_ = [ - ('bFipsEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS - -# values for enumeration 'NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE' -NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE__enumvalues = { - 0: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', - 1: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', - 2: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', -} -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0 -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1 -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2 -NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_RAFTS_FLOORSWEEP_INFO(Structure): - pass - -struct_NV2080_RAFTS_FLOORSWEEP_INFO._pack_ = 1 # source:False -struct_NV2080_RAFTS_FLOORSWEEP_INFO._fields_ = [ - ('unitType', NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE), - ('parentId', ctypes.c_uint32), - ('mask', ctypes.c_uint32), -] - -NV2080_RAFTS_FLOORSWEEP_INFO = struct_NV2080_RAFTS_FLOORSWEEP_INFO -class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS._fields_ = [ - ('tpcCountMatrix', ctypes.c_ubyte * 12 * 2), - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('floorSweepConfig', struct_NV2080_RAFTS_FLOORSWEEP_INFO * 26), - ('gfxGpcCount', ctypes.c_ubyte), - ('gfxTpcPerGpcCount', ctypes.c_ubyte), - ('maxUgpuTpcDiff', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS -class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('computeSize', ctypes.c_uint32), - ('totalProfileCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalSpans', struct_NV2080_CTRL_EXEC_PARTITION_SPAN * 8), - ('totalSpansCount', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS -class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [ - ('gpc', ctypes.c_uint32), - ('tpcReconfigMask', ctypes.c_uint32), -] - -NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS -class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('gpuPciId', ctypes.c_uint32), - ('gpuPciBdf', ctypes.c_uint32), - ('vgpuTypeId', ctypes.c_uint32), - ('vgpuId', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('gpuInstanceId', ctypes.c_uint32), - ('placementId', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS -class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._fields_ = [ - ('gpuPciId', ctypes.c_uint32), - ('gpuPciBdf', ctypes.c_uint32), - ('numVgpuTypes', ctypes.c_uint32), - ('vgpuTypeIds', ctypes.c_uint32 * 64), - ('availableInstances', ctypes.c_uint32 * 64), -] - -NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS -class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('vgpuId', ctypes.c_uint16), -] - -NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS -class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._fields_ = [ - ('returnStatus', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS -class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('mode', ctypes.c_uint32), - ('sysfs_val', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS -NV0080_CTRL_CMD_BIF_RESET = (0x800102) # macro -NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2) # macro -# NV0080_CTRL_BIF_RESET_FLAGS_TYPE = 4 : 0 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8 # macro -NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE = (0x800104) # macro -NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID = (0x4) # macro -# NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S = 0 : 0 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED = 0x000000001 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED = 0x000000000 # macro -# NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 = 1 : 1 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED = 0x000000001 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED = 0x000000000 # macro -NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105) # macro -NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5) # macro -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106) # macro -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6) # macro -class struct_NV0080_CTRL_BIF_RESET_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_RESET_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_RESET_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV0080_CTRL_BIF_RESET_PARAMS = struct_NV0080_CTRL_BIF_RESET_PARAMS -class struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._fields_ = [ - ('aspmFeatureSupported', ctypes.c_uint32), -] - -NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS = struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS -class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._fields_ = [ - ('bL0sEnable', ctypes.c_ubyte), - ('bL1Enable', ctypes.c_ubyte), -] - -NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS -class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(Structure): - pass - -struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._fields_ = [ - ('pciePowerControlMask', ctypes.c_uint32), - ('pciePowerControlIdentifiedKeyOrder', ctypes.c_uint32), - ('pciePowerControlIdentifiedKeyLocation', ctypes.c_uint32), -] - -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS -NV0080_CTRL_CMD_BSP_GET_CAPS = (0x801c01) # macro -NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_BSP_CAPS_TBL_SIZE = 8 # macro -NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = (0x801c02) # macro -NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), - ('instanceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_BSP_GET_CAPS_PARAMS = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS -class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2(Structure): - pass - -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._pack_ = 1 # source:False -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 8), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID = 0 : 0 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED = 2 : 1 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE = 6 : 3 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS = 10 : 7 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED = 12 : 11 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS = 14 : 13 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY = 15 : 15 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC = 16 : 16 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING = 17 : 17 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED = 18 : 18 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801) # macro -NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a) # macro -NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA) # macro -NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802) # macro -NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2) # macro -NV0080_CTRL_CMD_DMA_FLUSH = (0x801805) # macro -NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 = 0 : 0 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG = 1 : 1 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB = 2 : 2 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE = 4 : 3 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002) # macro -NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806) # macro -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16) # macro -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6) # macro -NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1 # macro -NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4 # macro -NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c) # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC) # macro -# NV0080_CTRL_DMA_INVALIDATE_TLB_ALL = 0 : 0 # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d) # macro -NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8 # macro -NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD) # macro -# def NV0080_CTRL_DMA_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED = 0 : 0x01 # macro -# NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED = 0 : 0x04 # macro -# NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED = 0 : 0x08 # macro -# NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED = 0 : 0x10 # macro -NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e) # macro -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE) # macro -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF) # macro -NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE = 0 : 0 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE = 1 : 1 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE = 3 : 2 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE = 4 : 4 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE = (0x801810) # macro -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID = (0x10) # macro -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812) # macro -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12) # macro -NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE = 1 : 0 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES = 2 : 2 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS = 3 : 3 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY = 4 : 4 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE = 5 : 5 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814) # macro -NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14) # macro -class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(Structure): - pass - -struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._fields_ = [ - ('pageSize', ctypes.c_uint64), - ('pteEntrySize', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pteFlags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK -class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('subDeviceId', ctypes.c_uint32), - ('skipVASpaceInit', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pteBlocks', struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5), - ('hVASpace', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pteBlocks', struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5), - ('hVASpace', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(Structure): - pass - -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(Structure): - pass - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), -] - -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(Structure): - pass - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._fields_ = [ - ('fbKind', ctypes.c_uint32), - ('sysKind', ctypes.c_uint32), - ('compTagStartOffset', ctypes.c_uint32), -] - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._fields_ = [ - ('pageCount', ctypes.c_uint32), - ('hwResource', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource), - ('comprInfo', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo), - ('offset', ctypes.c_uint64), - ('gpuAddr', ctypes.c_uint64), - ('pageArray', ctypes.POINTER(None)), - ('pteMem', ctypes.POINTER(None)), - ('pteMemPfn', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('startPageIndex', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hSrcVASpace', ctypes.c_uint32), - ('hTgtVASpace', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS -class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_FLUSH_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FLUSH_PARAMS._fields_ = [ - ('targetUnit', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_FLUSH_PARAMS = struct_NV0080_CTRL_DMA_FLUSH_PARAMS -class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(Structure): - pass - -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._fields_ = [ - ('pageTableSize', ctypes.c_uint32), - ('pageTableCoverage', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT -class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._fields_ = [ - ('vaBitCount', ctypes.c_uint32), - ('pdeCoverageBitCount', ctypes.c_uint32), - ('num4KPageTableFormats', ctypes.c_uint32), - ('bigPageSize', ctypes.c_uint32), - ('compressionPageSize', ctypes.c_uint32), - ('dualPageTableSupported', ctypes.c_uint32), - ('idealVRAMPageSize', ctypes.c_uint32), - ('pageTableBigFormat', NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT), - ('pageTable4KFormat', struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT * 16), - ('hVASpace', ctypes.c_uint32), - ('vaRangeLo', ctypes.c_uint64), - ('vaSpaceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('supportedPageSizeMask', ctypes.c_uint64), -] - -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS -class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(Structure): - pass - -struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._fields_ = [ - ('ptePhysAddr', ctypes.c_uint64), - ('pteCacheAttrib', ctypes.c_uint32), - ('pteEntrySize', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('pteAddrSpace', ctypes.c_uint32), - ('pdeVASpaceSize', ctypes.c_uint32), - ('pdeFlags', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK -class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('pdeVirtAddr', ctypes.c_uint64), - ('pdeEntrySize', ctypes.c_uint32), - ('pdeAddrSpace', ctypes.c_uint32), - ('pdeSize', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pteBlocks', struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK * 5), - ('pdbAddr', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS -class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('capsTbl', ctypes.c_ubyte * 8), -] - -NV0080_CTRL_DMA_GET_CAPS_PARAMS = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS -class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._fields_ = [ - ('vaSpaceSize', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS -class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._fields_ = [ - ('physAddr', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('aperture', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS -class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._fields_ = [ - ('pdeIndex', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('ptParams', struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS * 2), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pPdeBuffer', ctypes.POINTER(None)), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS -class struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS = struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS -class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS -class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('chId', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS -class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS -NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301) # macro -NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_FB_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM = 0 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_BLOCKLINEAR = 0 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM = 0 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM = 0 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION = 0 : 0x10 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION = 0 : 0x20 # macro -# NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 = 0 : 0x40 # macro -# NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 = 0 : 0x80 # macro -# NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 = 1 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 = 1 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT = 1 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 = 1 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB = 1 : 0x10 # macro -# NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET = 1 : 0x20 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 = 1 : 0x40 # macro -# NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND = 1 : 0x80 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 = 2 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED = 2 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY = 2 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 = 2 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_PARTIAL_UNMAP = 2 : 0x10 # macro -NV0080_CTRL_FB_CAPS_TBL_SIZE = 3 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306) # macro -NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3 # macro -NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307) # macro -NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308) # macro -NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_FB_GET_CAPS_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS -class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._fields_ = [ - ('Size', ctypes.c_uint64), - ('Address', ctypes.c_uint64), - ('AddressSpace', ctypes.c_uint32), - ('MaxCompbitLine', ctypes.c_uint32), - ('comptagsPerCacheLine', ctypes.c_uint32), - ('cacheLineSize', ctypes.c_uint32), - ('cacheLineSizePerSlice', ctypes.c_uint32), - ('cacheLineFetchAlignment', ctypes.c_uint32), - ('backingStoreBase', ctypes.c_uint64), - ('gobsPerComptagPerSlice', ctypes.c_uint32), - ('backingStoreCbcBase', ctypes.c_uint32), - ('comptaglineAllocationPolicy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('privRegionStartOffset', ctypes.c_uint64), - ('cbcCoveragePerSlice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS -class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_FB_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), -] - -NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS - -# values for enumeration 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY' -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY__enumvalues = { - 0: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', - 1: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', - 2: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', - 3: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', -} -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = ctypes.c_uint32 # enum -NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701) # macro -NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_FIFO_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT = 0 : 0x01 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB = 0 : 0x02 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB = 0 : 0x04 # macro -# NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM = 0 : 0x40 # macro -# NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT = 0 : 0x80 # macro -# NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL = 1 : 0x01 # macro -# NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING = 1 : 0x02 # macro -# NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 = 1 : 0x08 # macro -# NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 = 1 : 0x10 # macro -# NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP = 1 : 0x20 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING = 1 : 0x40 # macro -NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2 # macro -NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707) # macro -# NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID = 4 : 0 # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS = (0x801709) # macro -NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS = (8) # macro -NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE = (0x80170b) # macro -NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR = (12) # macro -NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST = (0x80170c) # macro -NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d) # macro -NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD) # macro -NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e) # macro -NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE) # macro -NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff) # macro -NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS = (0x00000000) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS = (0x00000001) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE = (0x00000002) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE = (0x00000003) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008) # macro -NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711) # macro -NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11) # macro -NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712) # macro -NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12) # macro -NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713) # macro -NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13) # macro -NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714) # macro -NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096 # macro -NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14) # macro -class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_FIFO_GET_CAPS_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS -class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS -class struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM(Structure): - pass - -struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._fields_ = [ - ('hChannel1', ctypes.c_uint32), - ('hChannel2', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM -class struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM(Structure): - pass - -struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('tsDivisor', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM -class struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._fields_ = [ - ('hRunlist', ctypes.c_uint32), - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pChannelHandleList', ctypes.POINTER(None)), - ('pChannelList', ctypes.POINTER(None)), -] - -NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), - ('gpEntries', ctypes.c_uint32), - ('pbEntries', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS -class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('property', ctypes.c_uint32), - ('value', ctypes.c_uint64), -] - -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS -class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_START_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 2), -] - -NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hChannels', ctypes.c_uint32 * 4096), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS -NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201) # macro -NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280) # macro -NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80) # macro -NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281) # macro -NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81) # macro -NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282) # macro -NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82) # macro -NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283) # macro -NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83) # macro -NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285) # macro -NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85) # macro -NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000) # macro -NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3 # macro -NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287) # macro -NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000) # macro -NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001) # macro -NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87) # macro -NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288) # macro -NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88) # macro -NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = (0x00000003) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004) # macro -NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89) # macro -NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c) # macro -NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C) # macro -NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d) # macro -NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D) # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0 # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1 # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2 # macro -NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e) # macro -NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E) # macro -NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291) # macro -NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91) # macro -NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 100 # macro -NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292) # macro -NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92) # macro -NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293) # macro -NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = (1 << 0) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = (1 << 1) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = (1 << 2) # macro -NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1<<6) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1<<7) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1<<8) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1<<9) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1<<10) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1<<11) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1<<12) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1<<13) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1<<14) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1<<15) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1<<16) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1<<17) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1<<18) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = (1<<6) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = (1<<18) # macro -NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0 # macro -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296) # macro -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96) # macro -NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297) # macro -NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97) # macro -NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298) # macro -NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98) # macro -class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('classList', ctypes.POINTER(None)), -] - -NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS -class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._fields_ = [ - ('numSubDevices', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS -class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._fields_ = [ - ('ConnectionCount', ctypes.c_uint32), - ('Order', ctypes.c_uint32 * 8), -] - -NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS -class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS -class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS -class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._fields_ = [ - ('enable', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_VIDLINK_PARAMS = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS -class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ - ('newState', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS -class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ - ('swStatePersistence', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._fields_ = [ - ('virtualizationMode', ctypes.c_uint32), - ('isGridBuild', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ - ('defaultSetting', ctypes.c_uint32), - ('currentSetting', ctypes.c_uint32), - ('pendingSetting', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS -class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ - ('setting', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._fields_ = [ - ('isVgx', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [ - ('totalVFs', ctypes.c_uint32), - ('firstVfOffset', ctypes.c_uint32), - ('vfFeatureMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('FirstVFBar0Address', ctypes.c_uint64), - ('FirstVFBar1Address', ctypes.c_uint64), - ('FirstVFBar2Address', ctypes.c_uint64), - ('bar0Size', ctypes.c_uint64), - ('bar1Size', ctypes.c_uint64), - ('bar2Size', ctypes.c_uint64), - ('b64bitBar0', ctypes.c_ubyte), - ('b64bitBar1', ctypes.c_ubyte), - ('b64bitBar2', ctypes.c_ubyte), - ('bSriovEnabled', ctypes.c_ubyte), - ('bSriovHeavyEnabled', ctypes.c_ubyte), - ('bEmulateVFBar0TlbInvalidationRegister', ctypes.c_ubyte), - ('bClientRmAllocatedCtxBuffer', ctypes.c_ubyte), - ('bNonPowerOf2ChannelCountSupported', ctypes.c_ubyte), - ('bVfResizableBAR1Supported', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('classList', ctypes.c_uint32 * 100), -] - -NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS -class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(Structure): - pass - -struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._fields_ = [ - ('subDeviceInst', ctypes.c_uint32), - ('hSubDevice', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM -class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._fields_ = [ - ('brands', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._fields_ = [ - ('vfBar1SizeMB', ctypes.c_uint32), - ('numVfs', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS -class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS -NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401) # macro -NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_HOST_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 = 2 : 0x20 # macro -# NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD = 2 : 0x40 # macro -NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3 # macro -NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402) # macro -NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_HOST_GET_CAPS_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS -class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS -NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909) # macro -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002) # macro -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2) # macro -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003) # macro -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007) # macro -NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008) # macro -NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200 # macro -NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08) # macro -class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(Structure): - pass - -struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [ - ('bActivate', ctypes.c_ubyte), -] - -NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS -class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(Structure): - pass - -struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._fields_ = [ - ('bCudaLimit', ctypes.c_ubyte), -] - -NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS -class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), - ] - -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS -class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), - ] - -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS -class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._fields_ = [ - ('numClients', ctypes.c_uint32), - ('clientHandles', ctypes.c_uint32 * 200), -] - -NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS -NV0080_CTRL_CMD_MSENC_GET_CAPS = (0x801b01) # macro -NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_MSENC_CAPS_TBL_SIZE = 4 # macro -NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = (0x801b02) # macro -NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_MSENC_GET_CAPS_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS -class struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 4), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS -NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9 # macro -NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02) # macro -NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS -NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003) # macro -NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02) # macro -NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(Structure): - pass - -struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), -] - -NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS -class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), - ('width', ctypes.c_uint16), - ('height', ctypes.c_uint16), - ('depth', ctypes.c_uint16), - ('pitch', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('baseAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS -NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F) # macro -NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000) # macro -NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001) # macro -NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802) # macro -NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810) # macro -NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008) # macro -NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000) # macro -NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000) # macro -NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001) # macro -NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA) # macro -NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB) # macro -NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC) # macro -NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD) # macro -NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE) # macro -NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803) # macro -NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e) # macro -NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100) # macro -NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806) # macro -NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6) # macro -GLOB_TYPE_GET_NBSI_DIR = 0xfffe # macro -GLOB_TYPE_APITEST = 0xffff # macro -GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd # macro -NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808) # macro -NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809) # macro -NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b) # macro -NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE = 1 : 0 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING = 2 : 2 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT = 3 : 3 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001) # macro -NV2080_CTRL_BIOS_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._fields_ = [ - ('biosInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('biosInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_BIOS_GET_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS -class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._fields_ = [ - ('biosInfoListSize', ctypes.c_uint32), - ('biosInfoList', struct_NVXXXX_CTRL_XXX_INFO * 15), -] - -NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(Structure): - pass - -class union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(Union): - pass - -union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._pack_ = 1 # source:False -union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._fields_ = [ - ('ascii', ctypes.c_ubyte * 256), - ('unicode', ctypes.c_uint16 * 256), - ('hash', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 510), -] - -struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._fields_ = [ - ('size', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('value', union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value), -] - -NV2080_CTRL_BIOS_NBSI_REG_STRING = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING -class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._fields_ = [ - ('module', ctypes.c_uint32), - ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('PADDING_0', ctypes.c_ubyte * 4), - ('retBuf', ctypes.POINTER(None)), - ('retSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_NBSI_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS -class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._fields_ = [ - ('module', ctypes.c_uint32), - ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('retBuf', ctypes.c_ubyte * 256), - ('retSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS -class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._fields_ = [ - ('globType', ctypes.c_uint16), - ('globIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('globSource', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('retBufOffset', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('retBuf', ctypes.POINTER(None)), - ('retSize', ctypes.c_uint32), - ('totalObjSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS -class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [ - ('BoardID', ctypes.c_uint32), - ('chipSKU', ctypes.c_char * 9), - ('chipSKUMod', ctypes.c_char * 5), - ('PADDING_0', ctypes.c_ubyte * 2), - ('skuConfigVersion', ctypes.c_uint32), - ('project', ctypes.c_char * 5), - ('projectSKU', ctypes.c_char * 5), - ('CDP', ctypes.c_char * 6), - ('projectSKUMod', ctypes.c_char * 2), - ('PADDING_1', ctypes.c_ubyte * 2), - ('businessCycle', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS -class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._fields_ = [ - ('vbiosPostTime', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS -class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS -NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801) # macro -NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A) # macro -NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B) # macro -NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E) # macro -NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F) # macro -NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012) # macro -NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B) # macro -NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030) # macro -NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033) # macro -NV2080_CTRL_BUS_INFO_INDEX_MAX = (0x00000033) # macro -NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034) # macro -NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED = 3 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH = 9 : 4 # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM = 11 : 10 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN = 15 : 12 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL = 19 : 16 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN = 23 : 20 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES = 24 : 24 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM = 1 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED = 19 : 16 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH = 25 : 20 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020) # macro -# NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 = 4 : 4 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM = 2 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_MSI_STATUS = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED = 4 : 4 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED = 7 : 5 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME = 15 : 8 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE = 17 : 16 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE = 23 : 19 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME = 15 : 8 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE = 25 : 16 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE = 31 : 29 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE = 1 : 0 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE = 7 : 3 # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002) # macro -NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802) # macro -NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823) # macro -NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803) # macro -NV2080_CTRL_BUS_MAX_PCI_BARS = (8) # macro -NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006) # macro -NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809) # macro -NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a) # macro -NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b) # macro -NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812) # macro -NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000) # macro -NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001) # macro -NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002) # macro -NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813) # macro -NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31 # macro -NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080 # macro -NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000 # macro -NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814) # macro -NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815) # macro -NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816) # macro -NV2080_CTRL_PEX_MAX_LANES = 16 # macro -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040 # macro -NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7 # macro -NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819) # macro -NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820) # macro -NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_BUS_GET_BFD = (0x20801821) # macro -NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE = 0x00000000 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS = 0x00000001 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE = 0x00000002 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED = 0x00000003 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED = 0x00000004 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY = 0x00000005 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED = 0x00000006 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY = 0x00000007 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 = 0x00000008 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS = 9 # macro -NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS = (0x20801822) # macro -NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824) # macro -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825) # macro -NV2080_CTRL_BUS_MAX_NUM_GPUS = 32 # macro -NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826) # macro -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827) # macro -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828) # macro -NV2080_CTRL_BUS_MAX_NUM_LANES = 32 # macro -NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0 # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1 # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2 # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 = 0 : 0 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 = 1 : 1 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 = 2 : 2 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 = 3 : 3 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 = 4 : 4 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 = 5 : 5 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 = 6 : 6 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a) # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A) # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR = 0 : 0 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR = 1 : 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION = 2 : 2 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 = 3 : 3 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 = 4 : 4 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 = 5 : 5 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED = 6 : 6 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED = 7 : 7 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0 # macro -NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b) # macro -NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1 # macro -NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2 # macro -NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c) # macro -NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e) # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4 # macro -NV2080_SET_P2P_MAPPING_UUID_LEN = 16 # macro -NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E) # macro -NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f) # macro -NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 = 0 : 0 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 = 1 : 1 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 = 2 : 2 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 = 3 : 3 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 = 4 : 4 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 = 5 : 5 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 = 6 : 6 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # macro -class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._fields_ = [ - ('pciDeviceId', ctypes.c_uint32), - ('pciSubSystemId', ctypes.c_uint32), - ('pciRevisionId', ctypes.c_uint32), - ('pciExtDeviceId', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS -NV2080_CTRL_BUS_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._fields_ = [ - ('busInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('busInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_BUS_GET_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS -class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._fields_ = [ - ('busInfoListSize', ctypes.c_uint32), - ('busInfoList', struct_NVXXXX_CTRL_XXX_INFO * 52), -] - -NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(Structure): - pass - -struct_NV2080_CTRL_BUS_PCI_BAR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_PCI_BAR_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('barSize', ctypes.c_uint32), - ('barSizeBytes', ctypes.c_uint64), - ('barOffset', ctypes.c_uint64), -] - -NV2080_CTRL_BUS_PCI_BAR_INFO = struct_NV2080_CTRL_BUS_PCI_BAR_INFO -class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._fields_ = [ - ('pciBarCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pciBarInfo', struct_NV2080_CTRL_BUS_PCI_BAR_INFO * 8), -] - -NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS -class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._fields_ = [ - ('pcieLinkWidth', ctypes.c_uint32), - ('failingReason', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS -class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._fields_ = [ - ('busSpeed', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS -class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_MAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._fields_ = [ - ('command', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('deviceState', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS -class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('pexTotalCorrectableErrors', ctypes.c_uint32), - ('pexCorrectableErrors', ctypes.c_uint16), - ('pexTotalNonFatalErrors', ctypes.c_ubyte), - ('pexTotalFatalErrors', ctypes.c_ubyte), - ('pexTotalUnsupportedReqs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexCounters', ctypes.c_uint16 * 31), -] - -NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('bFreezeRmCounter', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._fields_ = [ - ('pexLaneErrorStatus', ctypes.c_uint16), - ('pexLaneCounter', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ - ('bPexLtrRegkeyOverride', ctypes.c_ubyte), - ('bPexRootPortLtrSupported', ctypes.c_ubyte), - ('bPexGpuLtrSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexLtrSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('pexLtrNoSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrNoSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS -class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ - ('pexLtrSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexLtrNoSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrNoSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS -class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('pexCounters', ctypes.c_uint32 * 7), -] - -NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_GET_BFD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('deviceID', ctypes.c_uint16), - ('vendorID', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_BUS_GET_BFD_PARAMS = struct_NV2080_CTRL_BUS_GET_BFD_PARAMS -class struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', struct_NV2080_CTRL_BUS_GET_BFD_PARAMS * 32), - ] - -NV2080_CTRL_BUS_GET_BFD_PARAMSARR = struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR -class struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._fields_ = [ - ('aspmDisableFlags', ctypes.c_ubyte * 9), -] - -NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS = struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS -class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._fields_ = [ - ('nvlinkPeerIdMask', ctypes.c_uint32 * 32), -] - -NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS -class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._fields_ = [ - ('eomMode', ctypes.c_ubyte), - ('eomNblks', ctypes.c_ubyte), - ('eomNerrs', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._fields_ = [ - ('regAddress', ctypes.c_uint32), - ('laneSelectMask', ctypes.c_uint32), - ('regValue', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS -class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._fields_ = [ - ('eomMode', ctypes.c_ubyte), - ('eomNblks', ctypes.c_ubyte), - ('eomNerrs', ctypes.c_ubyte), - ('eomBerEyeSel', ctypes.c_ubyte), - ('eomPamEyeSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('laneMask', ctypes.c_uint32), - ('eomStatus', ctypes.c_uint16 * 32), -] - -NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._fields_ = [ - ('capType', ctypes.c_uint32), - ('dbdf', ctypes.c_uint32), - ('atomicsCaps', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS -class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(Structure): - pass - -struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._fields_ = [ - ('bSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('attributes', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._fields_ = [ - ('capType', ctypes.c_uint32), - ('dbdf', ctypes.c_uint32), - ('atomicOp', struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO * 13), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._fields_ = [ - ('bIsLinkUp', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('nrLinks', ctypes.c_uint32), - ('maxNrLinks', ctypes.c_uint32), - ('linkMask', ctypes.c_uint32), - ('perLinkBwMBps', ctypes.c_uint32), - ('perLinkLaneWidth', ctypes.c_uint32), - ('remoteType', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS -class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), -] - -NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS -class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bEgmPeer', ctypes.c_ubyte), - ('bSpaAccessOnly', ctypes.c_ubyte), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS -class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._fields_ = [ - ('atomicsCaps', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS -NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01) # macro -NV2080_CTRL_CE_CAPS_TBL_SIZE = 2 # macro -NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03) # macro -NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3) # macro -# def NV2080_CTRL_CE_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV2080_CTRL_CE_CAPS_CE_GRCE = 0 : 0x01 # macro -# NV2080_CTRL_CE_CAPS_CE_SHARED = 0 : 0x02 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ = 0 : 0x04 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE = 0 : 0x08 # macro -# NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P = 0 : 0x10 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM = 0 : 0x20 # macro -# NV2080_CTRL_CE_CAPS_CE_P2P = 0 : 0x40 # macro -# NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED = 0 : 0x80 # macro -# NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL = 1 : 0x01 # macro -# NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL = 1 : 0x02 # macro -# NV2080_CTRL_CE_CAPS_CE_CC_SECURE = 1 : 0x04 # macro -# NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED = 1 : 0x08 # macro -NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02) # macro -NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04) # macro -NV2080_CTRL_MAX_PCES = 32 # macro -NV2080_CTRL_MAX_GRCES = 4 # macro -NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf # macro -NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06) # macro -NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07) # macro -NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08) # macro -NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09) # macro -NV2080_CTRL_CE_MAX_HSHUBS = 32 # macro -NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a) # macro -NV2080_CTRL_MAX_CES = 64 # macro -NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa) # macro -NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b) # macro -NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb) # macro -NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c) # macro -NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc) # macro -NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd) # macro -NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e) # macro -NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe) # macro -NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f) # macro -NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf) # macro -NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11) # macro -NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12) # macro -NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12) # macro -class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('capsTblSize', ctypes.c_uint32), - ('capsTbl', ctypes.POINTER(None)), -] - -NV2080_CTRL_CE_GET_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS -class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('capsTbl', ctypes.c_ubyte * 2), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_CE_GET_CAPS_V2_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('pceMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceSharedLceMap', ctypes.c_uint32 * 4), -] - -NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._fields_ = [ - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceConfig', ctypes.c_uint32 * 4), - ('exposeCeMask', ctypes.c_uint32), - ('bUpdateNvlinkPceLce', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._fields_ = [ - ('stubbedCeMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS -NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._fields_ = [ - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._fields_ = [ - ('hshubPceMasks', ctypes.c_uint32 * 32), - ('fbhubPceMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 2 * 64), - ('present', ctypes.c_uint64), -] - -NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS -NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS -class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('shimInstance', ctypes.c_uint32), - ('shimLocalLceIdx', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._fields_ = [ - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceConfig', ctypes.c_uint32 * 4), - ('exposeCeMask', ctypes.c_uint32), - ('bUpdateNvlinkPceLce', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('shimInstance', ctypes.c_uint32), -] - -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._fields_ = [ - ('connectingHubPceMasks', ctypes.c_uint32 * 32), - ('fbhubPceMask', ctypes.c_uint32), - ('shimInstance', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS - -# values for enumeration 'NV2080_CTRL_CE_LCE_TYPE' -NV2080_CTRL_CE_LCE_TYPE__enumvalues = { - 1: 'NV2080_CTRL_CE_LCE_TYPE_PCIE', - 2: 'NV2080_CTRL_CE_LCE_TYPE_DECOMP', - 3: 'NV2080_CTRL_CE_LCE_TYPE_SCRUB', - 4: 'NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', - 5: 'NV2080_CTRL_CE_LCE_TYPE_C2C', - 6: 'NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', - 7: 'NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', - 8: 'NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', - 9: 'NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', -} -NV2080_CTRL_CE_LCE_TYPE_PCIE = 1 -NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2 -NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3 -NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4 -NV2080_CTRL_CE_LCE_TYPE_C2C = 5 -NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6 -NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7 -NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8 -NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9 -NV2080_CTRL_CE_LCE_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._fields_ = [ - ('lceType', NV2080_CTRL_CE_LCE_TYPE), - ('numPces', ctypes.c_uint32), - ('numLces', ctypes.c_uint32), - ('supportedPceMask', ctypes.c_uint32), - ('supportedLceMask', ctypes.c_uint32), - ('pcePerHshub', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS -class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._fields_ = [ - ('decompLceMask', ctypes.c_uint64), - ('shimInstance', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._fields_ = [ - ('lceIndex', ctypes.c_uint32), - ('bDecompEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS -NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001 # macro -NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002 # macro -# NV2080_GPUMON_PID_INVALID = ((NvU32)(~0)) # macro -class struct_NV2080_CTRL_GPUMON_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_GPUMON_SAMPLE._pack_ = 1 # source:False -struct_NV2080_CTRL_GPUMON_SAMPLE._fields_ = [ - ('timeStamp', ctypes.c_uint64), -] - -NV2080_CTRL_GPUMON_SAMPLE = struct_NV2080_CTRL_GPUMON_SAMPLE -class struct_NV2080_CTRL_GPUMON_SAMPLES(Structure): - pass - -struct_NV2080_CTRL_GPUMON_SAMPLES._pack_ = 1 # source:False -struct_NV2080_CTRL_GPUMON_SAMPLES._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bufSize', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('tracker', ctypes.c_uint32), - ('pSamples', ctypes.POINTER(None)), -] - -NV2080_CTRL_GPUMON_SAMPLES = struct_NV2080_CTRL_GPUMON_SAMPLES -NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS = 0 : 0 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO = 1 : 1 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY = 2 : 2 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE = 3 : 3 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB = 4 : 4 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV = 5 : 5 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG = 6 : 6 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD = 7 : 7 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION = 8 : 8 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON = 9 : 9 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS = 10 : 10 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR = 11 : 11 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001) # macro -NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000) # macro -NV2080_CTRL_DMA_INFO_INDEX_MAX = (0x000000000) # macro -NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503) # macro -NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256) # macro -NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('engine', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), -] - -NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS -NV2080_CTRL_DMA_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._fields_ = [ - ('dmaInfoTblSize', ctypes.c_uint32), - ('dmaInfoTbl', struct_NVXXXX_CTRL_XXX_INFO * 256), -] - -NV2080_CTRL_DMA_GET_INFO_PARAMS = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS -class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(Structure): - pass - -struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._fields_ = [ - ('srcAddr', ctypes.c_uint32), - ('dstAddr', ctypes.c_uint32), - ('relComptagIndex', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO -NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01) # macro -NV2080_CTRL_DMABUF_MAX_HANDLES = 128 # macro -NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001) # macro -NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(Structure): - pass - -struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_DMABUF_MEM_HANDLE_INFO = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO -class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('totalObjects', ctypes.c_uint32), - ('numObjects', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('totalSize', ctypes.c_uint64), - ('mappingType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('handles', struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO * 128), -] - -NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS -NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400) # macro -NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0) # macro -NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401) # macro -NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._fields_ = [ - ('sramParityUncorrectedUnique', ctypes.c_uint64), - ('sramSecDedUncorrectedUnique', ctypes.c_uint64), - ('sramCorrectedUnique', ctypes.c_uint64), - ('dramUncorrectedTotal', ctypes.c_uint64), - ('dramCorrectedTotal', ctypes.c_uint64), - ('lastClearedTimestamp', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sramBucketL2', ctypes.c_uint64), - ('sramBucketSM', ctypes.c_uint64), - ('sramBucketPcie', ctypes.c_uint64), - ('sramBucketFirmware', ctypes.c_uint64), - ('sramBucketOther', ctypes.c_uint64), - ('sramErrorThresholdExceeded', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS -class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._fields_ = [ - ('sramCorUni', ctypes.c_uint64), - ('sramUncParityUni', ctypes.c_uint64), - ('sramUncSecDedUni', ctypes.c_uint64), - ('dramCorTot', ctypes.c_uint64), - ('dramUncTot', ctypes.c_uint64), -] - -NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS -NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # macro -NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000) # macro -NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003) # macro -NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF) # macro -NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000) # macro -NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003) # macro -NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302) # macro -NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303) # macro -NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0 # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1 # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2 # macro -NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304) # macro -NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305) # macro -NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306) # macro -NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308) # macro -NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309) # macro -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a) # macro -NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA) # macro -class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('action', ctypes.c_uint32), - ('bNotifyState', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('info32', ctypes.c_uint32), - ('info16', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS - -# values for enumeration 'NV2080_EVENT_HDACODEC_DSTATE' -NV2080_EVENT_HDACODEC_DSTATE__enumvalues = { - 0: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', - 1: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', - 2: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', - 3: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', - 4: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', - 5: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', -} -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5 -NV2080_EVENT_HDACODEC_DSTATE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS -class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._fields_ = [ - ('hSemMemory', ctypes.c_uint32), - ('semOffset', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS -class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._fields_ = [ - ('guestMSIAddr', ctypes.c_uint64), - ('guestMSIData', ctypes.c_uint32), - ('hSemMemory', ctypes.c_uint32), - ('isReset', ctypes.c_ubyte), - ('vgpuUuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 7), - ('domainId', ctypes.c_uint64), -] - -NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS -class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._fields_ = [ - ('hSemMemory', ctypes.c_uint32), - ('isSemaMemValidationEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS -class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._fields_ = [ - ('hEvent', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS - -# values for enumeration 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD' -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD__enumvalues = { - 0: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', - 1: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', - 2: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', -} -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS -class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('tracepointMask', ctypes.c_uint64), - ('gspLoggingBufferSize', ctypes.c_uint32), - ('gspLoggingBufferWatermark', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS -NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000) # macro -NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001) # macro -NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002) # macro -NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005) # macro -NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007) # macro -NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009) # macro -NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A) # macro -NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D) # macro -NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E) # macro -NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011) # macro -NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012) # macro -NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014) # macro -NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017) # macro -NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018) # macro -NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019) # macro -NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A) # macro -NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B) # macro -NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F) # macro -NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020) # macro -NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022) # macro -NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023) # macro -NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024) # macro -NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025) # macro -NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027) # macro -NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028) # macro -NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029) # macro -NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B) # macro -NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C) # macro -NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D) # macro -NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E) # macro -NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032) # macro -NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033) # macro -NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034) # macro -NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035) # macro -NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = ((0x00000014)) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = ((0x0000002B)) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038) # macro -NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000039) # macro -NV2080_CTRL_FB_INFO_INDEX_MAX = (0x38) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = (0x00000003) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = (0x00000007) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002) # macro -NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301) # macro -NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303) # macro -NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310) # macro -NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c) # macro -NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000) # macro -NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK = 0 : 0 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE = 1 : 1 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH = 2 : 2 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE = 1 : 0 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK = 2 : 2 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE = 3 : 3 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE = 4 : 4 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH = 5 : 5 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001) # macro -NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313) # macro -NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008) # macro -NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003) # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320) # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 17 # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16 # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322) # macro -# NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE = 0 : 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1 # macro -# NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE = 1 : 1 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325) # macro -NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2 # macro -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326) # macro -NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328) # macro -NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335) # macro -NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336) # macro -NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337) # macro -NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338) # macro -NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F # macro -NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339) # macro -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a) # macro -NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b) # macro -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B) # macro -NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c) # macro -NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D) # macro -NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e) # macro -# NV2080_CTRL_FB_SET_RRD_RESET_VALUE = (~((NvU32)0)) # macro -NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E) # macro -NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f) # macro -NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340) # macro -NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341) # macro -NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342) # macro -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS = (4) # macro -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343) # macro -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43) # macro -# NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING = 0 : 0 # macro -NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0 # macro -NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1 # macro -NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002) # macro -NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003) # macro -NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200) # macro -NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344) # macro -# NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING = 0 : 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = 1 # macro -# NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE = 1 : 1 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24 # macro -NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0 # macro -NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1 # macro -NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2 # macro -NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3 # macro -NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4 # macro -NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9 # macro -NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB # macro -NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC # macro -NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD # macro -NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE # macro -NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10 # macro -NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11 # macro -NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120 # macro -NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4) # macro -NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347) # macro -NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512 # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64 # macro -NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001) # macro -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349) # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE = 4 : 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1 # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED = 5 : 5 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1 # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER = 6 : 6 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1 # macro -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49) # macro -NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350) # macro -NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351) # macro -NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # macro -NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52) # macro -NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353) # macro -NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 200 # macro -NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132a) # macro -NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354) # macro -NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_FB_GET_STATUS = (0x20801357) # macro -NV2080_CTRL_FB_STATUS_FAILED = (0x00000000) # macro -NV2080_CTRL_FB_STATUS_READY = (0x00000001) # macro -NV2080_CTRL_FB_STATUS_PENDING = (0x00000002) # macro -NV2080_CTRL_FB_STATUS_NOT_APPLICABLE = (0x00000003) # macro -NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID = (0x57) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801358) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x58) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801359) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x59) # macro -NV2080_CTRL_FB_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_PARAMS._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_FB_GET_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('fbInfoList', struct_NVXXXX_CTRL_XXX_INFO * 57), -] - -NV2080_CTRL_FB_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._fields_ = [ - ('cpuVirtAddress', ctypes.POINTER(None)), - ('gpuVirtAddress', ctypes.c_uint64), -] - -NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS -class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('driveStrengthRiseCount', ctypes.c_uint32), - ('driveStrengthFallCount', ctypes.c_uint32), - ('driveStrengthTermCount', ctypes.c_uint32), - ('slewStrengthRiseCount', ctypes.c_uint32), - ('slewStrengthFallCount', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS -class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS -class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._fields_ = [ - ('addressArray', ctypes.c_uint64 * 500), - ('addressArraySize', ctypes.c_uint32), - ('addressAlign', ctypes.c_uint32), - ('memBlockSizeBytes', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS -class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_IS_KIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_IS_KIND_PARAMS._fields_ = [ - ('operation', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('result', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FB_IS_KIND_PARAMS = struct_NV2080_CTRL_FB_IS_KIND_PARAMS -class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), - ('writeMode', ctypes.c_uint32), - ('bypassMode', ctypes.c_uint32), - ('rcmState', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS -NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = ctypes.c_ubyte * 17 -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [ - ('base', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), - ('performance', ctypes.c_uint32), - ('supportCompressed', ctypes.c_ubyte), - ('supportISO', ctypes.c_ubyte), - ('bProtected', ctypes.c_ubyte), - ('blackList', ctypes.c_ubyte * 17), -] - -NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [ - ('numFBRegions', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbRegion', struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16), -] - -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS -class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(Structure): - pass - -struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._fields_ = [ - ('pageAddressWithEccOn', ctypes.c_uint64), - ('pageAddressWithEccOff', ctypes.c_uint64), - ('rbcAddress', ctypes.c_uint32), - ('source', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO -class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64), - ('pageSize', ctypes.c_uint32), - ('validEntries', ctypes.c_uint32), - ('numPagesAdded', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS -class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64), - ('validEntries', ctypes.c_uint32), - ('bRetirementPending', ctypes.c_ubyte), - ('retirementPending', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE' -NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', - 1: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', - 2: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', -} -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0 -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1 -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2 -NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE' -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', - 1: 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', -} -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0 -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1 -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = ctypes.c_uint32 # enum -class struct_ACR_REQUEST_PARAMS(Structure): - pass - -struct_ACR_REQUEST_PARAMS._pack_ = 1 # source:False -struct_ACR_REQUEST_PARAMS._fields_ = [ - ('clientId', ctypes.c_uint32), - ('reqReadMask', ctypes.c_uint32), - ('reqWriteMask', ctypes.c_uint32), - ('regionSize', ctypes.c_uint32), -] - -ACR_REQUEST_PARAMS = struct_ACR_REQUEST_PARAMS -class struct_ACR_REGION_ID_PROP(Structure): - pass - -struct_ACR_REGION_ID_PROP._pack_ = 1 # source:False -struct_ACR_REGION_ID_PROP._fields_ = [ - ('regionId', ctypes.c_uint32), - ('readMask', ctypes.c_uint32), - ('writeMask', ctypes.c_uint32), - ('regionSize', ctypes.c_uint32), - ('clientMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physicalAddress', ctypes.c_uint64), -] - -ACR_REGION_ID_PROP = struct_ACR_REGION_ID_PROP -class struct_ACR_STATUS_PARAMS(Structure): - pass - -struct_ACR_STATUS_PARAMS._pack_ = 1 # source:False -struct_ACR_STATUS_PARAMS._fields_ = [ - ('allocStatus', ctypes.c_uint32), - ('regionId', ctypes.c_uint32), - ('physicalAddress', ctypes.c_uint64), -] - -ACR_STATUS_PARAMS = struct_ACR_STATUS_PARAMS -class struct_ACR_REGION_HANDLE(Structure): - pass - -struct_ACR_REGION_HANDLE._pack_ = 1 # source:False -struct_ACR_REGION_HANDLE._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), -] - -ACR_REGION_HANDLE = struct_ACR_REGION_HANDLE -class struct_ACR_FALCON_LS_STATUS(Structure): - pass - -struct_ACR_FALCON_LS_STATUS._pack_ = 1 # source:False -struct_ACR_FALCON_LS_STATUS._fields_ = [ - ('falconId', ctypes.c_uint16), - ('bIsInLs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -ACR_FALCON_LS_STATUS = struct_ACR_FALCON_LS_STATUS -class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('queryType', NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE), - ('errorCode', NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE), - ('acrRegionIdProp', ACR_REGION_ID_PROP), - ('clientReq', ACR_REQUEST_PARAMS), - ('clientReqStatus', ACR_STATUS_PARAMS), - ('handle', ACR_REGION_HANDLE), - ('falconStatus', ACR_FALCON_LS_STATUS), - ] - -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS -class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._fields_ = [ - ('sourceMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._fields_ = [ - ('pCompBitCopyObj', ctypes.POINTER(None)), - ('pSwizzleParams', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ltcMask', ctypes.c_uint32), - ('ltcCount', ctypes.c_uint32), - ('ltsMask', ctypes.c_uint32), - ('ltsCount', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._fields_ = [ - ('CBCBaseAddress', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('backingStorePA', ctypes.c_uint64), - ('backingStoreVA', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkPA', ctypes.c_uint64), - ('backingStoreChunkVA', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('cacheWriteBitMap', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkOverfetch', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), - ('PageSizeSrc', ctypes.c_uint32), - ('PageSizeDest', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._fields_ = [ - ('fcbits', ctypes.POINTER(ctypes.c_uint32)), - ('compbits', ctypes.POINTER(ctypes.c_uint32)), - ('dataPhysicalStart', ctypes.c_uint64), - ('surfaceOffset', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._fields_ = [ - ('fcbits', ctypes.c_uint32), - ('compbits', ctypes.c_uint32), - ('writeFc', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('dataPhysicalStart', ctypes.c_uint64), - ('surfaceOffset', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._fields_ = [ - ('SrcDataPhysicalStart', ctypes.c_uint64), - ('SrcComptagLine', ctypes.c_uint32), - ('page64KB', ctypes.c_uint32), - ('compbitBuffer', ctypes.POINTER(ctypes.c_uint32)), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._fields_ = [ - ('DstDataPhysicalStart', ctypes.c_uint64), - ('DstComptagLine', ctypes.c_uint32), - ('page64KB', ctypes.c_uint32), - ('compbitBuffer', ctypes.POINTER(ctypes.c_uint32)), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._fields_ = [ - ('bForceBar1', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._fields_ = [ - ('pAmapConfParams', ctypes.POINTER(None)), - ('pCbcSwizzleParams', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS - -# values for enumeration 'CTRL_CMD_FB_CBC_OP' -CTRL_CMD_FB_CBC_OP__enumvalues = { - 0: 'CTRL_CMD_FB_CBC_OP_CLEAN', - 1: 'CTRL_CMD_FB_CBC_OP_INVALIDATE', -} -CTRL_CMD_FB_CBC_OP_CLEAN = 0 -CTRL_CMD_FB_CBC_OP_INVALIDATE = 1 -CTRL_CMD_FB_CBC_OP = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fbCBCOp', CTRL_CMD_FB_CBC_OP), - ] - -NV2080_CTRL_CMD_FB_CBC_OP_PARAMS = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS -class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._fields_ = [ - ('pCompTags', ctypes.c_uint32 * 127), - ('numCompTags', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS -class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._fields_ = [ - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('hwResId', ctypes.c_uint32), - ('retCompTagLineMin', ctypes.c_uint32), - ('retCompTagLineMax', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS -class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._fields_ = [ - ('hwResId', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE' -NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_SET_VPR', -} -NV2080_CTRL_CMD_FB_SET_VPR = 0 -NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_CMD_FB_VPR_ERROR_CODE' -NV2080_CTRL_CMD_FB_VPR_ERROR_CODE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', - 1: 'NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', -} -NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0 -NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1 -NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = ctypes.c_uint32 # enum -class struct_VPR_REQUEST_PARAMS(Structure): - pass - -struct_VPR_REQUEST_PARAMS._pack_ = 1 # source:False -struct_VPR_REQUEST_PARAMS._fields_ = [ - ('startAddr', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -VPR_REQUEST_PARAMS = struct_VPR_REQUEST_PARAMS -class struct_VPR_STATUS_PARAMS(Structure): - pass - -struct_VPR_STATUS_PARAMS._pack_ = 1 # source:False -struct_VPR_STATUS_PARAMS._fields_ = [ - ('status', ctypes.c_uint32), -] - -VPR_STATUS_PARAMS = struct_VPR_STATUS_PARAMS -class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('requestType', NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE), - ('requestParams', VPR_REQUEST_PARAMS), - ('statusParams', VPR_STATUS_PARAMS), - ] - -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS -PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS) -class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlinedPages', ctypes.c_uint32 * 64), - ('pageSize', ctypes.c_uint32), - ('validEntries', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._fields_ = [ - ('defaultPageSize', ctypes.c_uint32), - ('comptagsPerCacheLine', ctypes.c_uint32), - ('unpackedComptagLinesPerCacheLine', ctypes.c_uint32), - ('compCacheLineSizePerLTC', ctypes.c_uint32), - ('unpackedCompCacheLineSizePerLTC', ctypes.c_uint32), - ('slicesPerLTC', ctypes.c_uint32), - ('numActiveLTCs', ctypes.c_uint32), - ('familyName', ctypes.c_uint32), - ('chipName', ctypes.c_uint32), - ('bitsPerRAMEntry', ctypes.c_uint32), - ('ramBankWidth', ctypes.c_uint32), - ('bitsPerComptagLine', ctypes.c_uint32), - ('ramEntriesPerCompCacheLine', ctypes.c_uint32), - ('comptagLineSize', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS -class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_RRD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_RRD_PARAMS._fields_ = [ - ('rrd', ctypes.c_uint32), -] - -NV2080_CTRL_FB_SET_RRD_PARAMS = struct_NV2080_CTRL_FB_SET_RRD_PARAMS -class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._fields_ = [ - ('limit', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS -class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._fields_ = [ - ('alignType', ctypes.c_uint32), - ('alignAttr', ctypes.c_uint32), - ('alignInputFlags', ctypes.c_uint32), - ('alignHead', ctypes.c_uint32), - ('alignSize', ctypes.c_uint64), - ('alignHeight', ctypes.c_uint32), - ('alignWidth', ctypes.c_uint32), - ('alignPitch', ctypes.c_uint32), - ('alignPad', ctypes.c_uint32), - ('alignMask', ctypes.c_uint32), - ('alignOutputFlags', ctypes.c_uint32 * 4), - ('alignBank', ctypes.c_uint32 * 4), - ('alignKind', ctypes.c_uint32), - ('alignAdjust', ctypes.c_uint32), - ('alignAttr2', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._fields_ = [ - ('cbcBaseAddress', ctypes.c_uint32), - ('compCacheLineSize', ctypes.c_uint32), - ('backingStoreStartPA', ctypes.c_uint64), - ('backingStoreAllocPA', ctypes.c_uint64), - ('backingStoreChunkOverfetch', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_FB_REMAP_ENTRY(Structure): - pass - -struct_NV2080_CTRL_FB_REMAP_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_REMAP_ENTRY._fields_ = [ - ('remapRegVal', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('fbpa', ctypes.c_ubyte), - ('sublocation', ctypes.c_ubyte), - ('source', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_REMAP_ENTRY = struct_NV2080_CTRL_FB_REMAP_ENTRY -class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._fields_ = [ - ('entryCount', ctypes.c_uint32), - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('entries', struct_NV2080_CTRL_FB_REMAP_ENTRY * 512), -] - -NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._fields_ = [ - ('data', ctypes.c_ubyte * 24), -] - -NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbpEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpLogicalIndex', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS -class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._fields_ = [ - ('sysIdx', ctypes.c_uint32), - ('sysl2LtcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS -class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._fields_ = [ - ('sysIdx', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sysl2LtsEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('pacEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_QUERY(Structure): - pass - -class union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(Union): - pass - -union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._pack_ = 1 # source:False -union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._fields_ = [ - ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS), - ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS), - ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS), - ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS), - ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS), - ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS), - ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS), - ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS), - ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS), - ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS), - ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS), - ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS), - ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS), - ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS), - ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS), - ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS), - ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS), - ('sysl2Lts', NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_NV2080_CTRL_FB_FS_INFO_QUERY._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_QUERY._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryParams', union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams), -] - -NV2080_CTRL_FB_FS_INFO_QUERY = struct_NV2080_CTRL_FB_FS_INFO_QUERY -class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_FB_FS_INFO_QUERY * 120), -] - -NV2080_CTRL_FB_GET_FS_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._fields_ = [ - ('histogram', ctypes.c_uint32 * 5), -] - -NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS -class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(Structure): - pass - -struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._fields_ = [ - ('pageNumber', ctypes.c_uint64), - ('source', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO -class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO * 64), - ('validEntries', ctypes.c_uint32), - ('baseIndex', ctypes.c_uint32), - ('bMore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._fields_ = [ - ('client', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('beginAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_ALLOCATION_INFO = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO -class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._fields_ = [ - ('handle', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), -] - -NV2080_CTRL_CMD_FB_CLIENT_INFO = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO -class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._fields_ = [ - ('allocCount', ctypes.c_uint64), - ('pAllocInfo', ctypes.POINTER(None)), - ('clientCount', ctypes.c_uint64), - ('pClientInfo', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS -class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._fields_ = [ - ('bOnline', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS -class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._fields_ = [ - ('numaNodeId', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('numaMemAddr', ctypes.c_uint64), - ('numaMemSize', ctypes.c_uint64), - ('numaOfflineAddressesCount', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('numaOfflineAddresses', ctypes.c_uint64 * 64), -] - -NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._fields_ = [ - ('maxSubmittedSemaphoreValueOffset', ctypes.c_uint64), - ('monitoredFenceThresholdOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('caps', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS -class struct_NV2080_CTRL_CMD_FB_STATS_ENTRY(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._fields_ = [ - ('totalSize', ctypes.c_uint64), - ('rsvdSize', ctypes.c_uint64), - ('osSize', ctypes.c_uint64), - ('r1Size', ctypes.c_uint64), - ('r2Size', ctypes.c_uint64), - ('freeSize', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_STATS_ENTRY = struct_NV2080_CTRL_CMD_FB_STATS_ENTRY -class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('invalidateAll', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS -class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._fields_ = [ - ('allocSize', ctypes.c_uint64), - ('numBlocks', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rsvdSize', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_STATS_OWNER_INFO = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO -class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._fields_ = [ - ('version', ctypes.c_uint64), - ('fbSizeInfo', NV2080_CTRL_CMD_FB_STATS_ENTRY), - ('fbBlockInfo', struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO * 200), -] - -NV2080_CTRL_CMD_FB_STATS_GET_PARAMS = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS -class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._fields_ = [ - ('bStaticBar1Enabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('staticBar1StartOffset', ctypes.c_uint64), - ('staticBar1Size', ctypes.c_uint64), -] - -NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS -class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._fields_ = [ - ('currentConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._fields_ = [ - ('newConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_FB_GET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._fields_ = [ - ('fbStatus', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_STATUS_PARAMS = struct_NV2080_CTRL_FB_GET_STATUS_PARAMS -class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._fields_ = [ - ('isSupported', ctypes.c_uint32), -] - -NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS -class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._fields_ = [ - ('currentStatus', ctypes.c_uint32), -] - -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS -NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102) # macro -NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS = (16) # macro -NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FIFO_BIND_ENGINES = (0x20801103) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES = (0x20801104) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID = (0x4) # macro -# NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE = 0 : 0 # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE = (0x00000000) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108) # macro -NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003) # macro -NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004) # macro -NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005) # macro -NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006) # macro -NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008) # macro -NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX = (0x00000000a) # macro -NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12) # macro -NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109) # macro -NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256) # macro -NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a) # macro -NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000) # macro -NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c) # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d) # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4 # macro -NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2 # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e) # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112) # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113) # macro -NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001 # macro -NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002 # macro -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115) # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0 # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1 # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2 # macro -# NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE = 0 : 0 # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000) # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116) # macro -NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117) # macro -NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17) # macro -NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118) # macro -NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119) # macro -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096 # macro -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120) # macro -NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121) # macro -NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122) # macro -NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123) # macro -NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124) # macro -NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24) # macro -class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_SET_GPFIFO_PARAMS = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS -class struct_NV2080_CTRL_FIFO_BIND_CHANNEL(Structure): - pass - -struct_NV2080_CTRL_FIFO_BIND_CHANNEL._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_BIND_CHANNEL._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_BIND_CHANNEL = struct_NV2080_CTRL_FIFO_BIND_CHANNEL -class struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._fields_ = [ - ('bindChannelCount', ctypes.c_uint32), - ('bindChannels', struct_NV2080_CTRL_FIFO_BIND_CHANNEL * 16), -] - -NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS = struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS -class struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS = struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS -class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._fields_ = [ - ('physChannelCount', ctypes.c_uint32), - ('physChannelCountInUse', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS -NV2080_CTRL_FIFO_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._fields_ = [ - ('fifoInfoTblSize', ctypes.c_uint32), - ('fifoInfoTbl', struct_NVXXXX_CTRL_XXX_INFO * 256), - ('engineType', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_GET_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numChannels', ctypes.c_uint32), - ('bOnlyDisableScheduling', ctypes.c_ubyte), - ('bRewindGpPut', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 6), - ('pRunlistPreemptEvent', ctypes.POINTER(None)), - ('hClientList', ctypes.c_uint32 * 64), - ('hChannelList', ctypes.c_uint32 * 64), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_MEM_INFO(Structure): - pass - -struct_NV2080_CTRL_FIFO_MEM_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_MEM_INFO._fields_ = [ - ('aperture', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_FIFO_MEM_INFO = struct_NV2080_CTRL_FIFO_MEM_INFO -class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(Structure): - pass - -struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._fields_ = [ - ('inst', NV2080_CTRL_FIFO_MEM_INFO), - ('ramfc', NV2080_CTRL_FIFO_MEM_INFO), - ('methodBuf', struct_NV2080_CTRL_FIFO_MEM_INFO * 2), - ('methodBufCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FIFO_CHANNEL_MEM_INFO = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO -class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('chMemInfo', NV2080_CTRL_FIFO_CHANNEL_MEM_INFO), -] - -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS -class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._fields_ = [ - ('aperture', ctypes.c_uint32), - ('attribute', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0._fields_ = [ - ('timestampNs', ctypes.c_uint64), - ('timeRunTotalNs', ctypes.c_int64), - ('timeRunNs', ctypes.c_uint32), - ('swrlId', ctypes.c_uint32), - ('targetTimeSlice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cumulativePreemptionTime', ctypes.c_uint64), - ('counters', ctypes.c_uint64 * 8), -] - -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('entry', struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0 * 200), - ('schedPolicy', ctypes.c_uint32), - ('arrEnabled', ctypes.c_uint32), - ('arrAvgFactor', ctypes.c_uint32), - ('targetTimesliceNs', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS -class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(Structure): - pass - -struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._fields_ = [ - ('engineData', ctypes.c_uint32 * 16), - ('pbdmaIds', ctypes.c_uint32 * 2), - ('pbdmaFaultIds', ctypes.c_uint32 * 2), - ('numPbdmas', ctypes.c_uint32), - ('engineName', ctypes.c_char * 16), -] - -NV2080_CTRL_FIFO_DEVICE_ENTRY = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY -class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [ - ('baseIndex', ctypes.c_uint32), - ('numEntries', ctypes.c_uint32), - ('bMore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('entries', struct_NV2080_CTRL_FIFO_DEVICE_ENTRY * 32), -] - -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS -class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('vChid', ctypes.c_uint32), - ('faultType', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS -class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS -class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hUserdMemory', ctypes.c_uint32), - ('gpFifoEntries', ctypes.c_uint32), - ('gpFifoOffset', ctypes.c_uint64), - ('userdOffset', ctypes.c_uint64), -] - -NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), -] - -NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS -class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._fields_ = [ - ('runlistId', ctypes.c_uint32), - ('bitMask', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hClientList', ctypes.c_uint32 * 64), - ('hChannelList', ctypes.c_uint32 * 64), - ('bEnableAfterKeyRotation', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hChannelList', ctypes.c_uint32 * 64), - ('bEnableAfterKeyRotation', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), - ('arrEnabled', ctypes.c_uint32), - ('targetTimesliceNs', ctypes.c_uint32), - ('arrAvgFactor', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), - ('enableArr', ctypes.c_uint32), - ('timesliceTargetNs', ctypes.c_uint32), - ('frequencyForARR', ctypes.c_uint32), - ('avgFactorForARR', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('supportedSchedulers', ctypes.c_uint32 * 3), - ('bIsArrModeSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('maxTimesliceNs', ctypes.c_uint32), - ('minTimesliceNs', ctypes.c_uint32), - ('maxFrequencyForARR', ctypes.c_uint32), - ('minFrequencyForARR', ctypes.c_uint32), - ('maxAvgFactorForARR', ctypes.c_uint32), - ('minAvgFactorForARR', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS -class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannelOrTsg', ctypes.c_uint32), - ('tsgId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('channelUniqueID', ctypes.c_uint32 * 128), - ('vasUniqueID', ctypes.c_uint32 * 128), - ('veid', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._fields_ = [ - ('hClients', ctypes.c_uint32 * 128), - ('hChannels', ctypes.c_uint32 * 128), - ('numChannels', ctypes.c_uint32), - ('channelUniqueIDs', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS -NV2080_CTRL_CMD_FLA_RANGE = (0x20803501) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000 # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = (1 << 0) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = (1 << 1) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = (1 << 2) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = (1 << 3) # macro -NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502) # macro -NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503) # macro -NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504) # macro -NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV2080_CTRL_FLA_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('mode', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), -] - -NV2080_CTRL_FLA_RANGE_PARAMS = struct_NV2080_CTRL_FLA_RANGE_PARAMS - -# values for enumeration 'NV2080_CTRL_FLA_ADDRSPACE' -NV2080_CTRL_FLA_ADDRSPACE__enumvalues = { - 0: 'NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', - 1: 'NV2080_CTRL_FLA_ADDRSPACE_FBMEM', -} -NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0 -NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1 -NV2080_CTRL_FLA_ADDRSPACE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_FLA_ACTION' -NV2080_CTRL_FLA_ACTION__enumvalues = { - 0: 'NV2080_CTRL_FLA_ACTION_BIND', - 1: 'NV2080_CTRL_FLA_ACTION_UNBIND', -} -NV2080_CTRL_FLA_ACTION_BIND = 0 -NV2080_CTRL_FLA_ACTION_UNBIND = 1 -NV2080_CTRL_FLA_ACTION = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._fields_ = [ - ('imbPhysAddr', ctypes.c_uint64), - ('addrSpace', NV2080_CTRL_FLA_ADDRSPACE), - ('flaAction', NV2080_CTRL_FLA_ACTION), -] - -NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS -class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_FLA_GET_RANGE_PARAMS = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS -class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._fields_ = [ - ('totalSize', ctypes.c_uint64), - ('freeSize', ctypes.c_uint64), -] - -NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS -FALCON_ID_PMU = ((0x00000029)) # macro -FALCON_ID_DPU = ((0x00000028)) # macro -FALCON_ID_SEC2 = ((0x00000026)) # macro -FALCON_ID_FBFLCN = ((0x0000002a)) # macro -NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101) # macro -NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D # macro -NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF # macro -NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118) # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG = 31 : 31 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD = 30 : 30 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE = 29 : 29 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND = 28 : 28 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID = ((27)):((20)) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT = ((28)):((24)) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH = 19 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT = 23 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME = 29 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD = 30 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON = 10 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT = 23 : 11 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP = 23 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID = 15 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE = 23 : 16 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID = 15 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC = 15 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID = 23 : 16 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID = 23 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID = 11 : 0 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON = 1 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 2 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH = 0 : 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH = 1 : 1 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH = 2 : 2 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD = 31 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20) # macro -NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120) # macro -NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120) # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123) # macro -NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124) # macro -NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24) # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON = ADDR_UNKNOWN # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM = ADDR_SYSMEM # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM = ADDR_FBMEM # macro -NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125) # macro -NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25) # macro -class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._fields_ = [ - ('flcnID', ctypes.c_uint32), - ('heapSize', ctypes.c_uint32), - ('heapFree', ctypes.c_uint32), -] - -NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS -class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('engineArch', ctypes.c_uint32), -] - -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS -class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._fields_ = [ - ('mask', ctypes.c_ubyte * 36), -] - -NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER -class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint32), - ('queueFeatureId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS -class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('eventFilter', NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER), - ('queueId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('alignment', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bufferHandle', ctypes.POINTER(None)), - ('pageCount', ctypes.c_uint64), - ('physAddr', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('bIsContigous', ctypes.c_ubyte), - ('bDeviceDescendant', ctypes.c_ubyte), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS -class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalBufferSize', ctypes.c_uint64), -] - -NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS -NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300) # macro -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301) # macro -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302) # macro -NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303) # macro -NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03) # macro -class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('bInput', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._fields_ = [ - ('function', ctypes.c_uint32), - ('pin', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS -NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801) # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32 # macro -NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8 # macro -NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10 # macro -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS._fields_ = [ - ('gpcCount', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ppcMask', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ropMask', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS._fields_ = [ - ('chipletSyspipeMask', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint16), - ('physSyspipeIdCount', ctypes.c_uint16), - ('physSyspipeId', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('grIdx', ctypes.c_uint32), - ('gpcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS._fields_ = [ - ('syspipeId', ctypes.c_uint32), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(Structure): - pass - -class union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(Union): - pass - -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._pack_ = 1 # source:False -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._fields_ = [ - ('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS), - ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS), - ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS), - ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS), - ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS), - ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS), - ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS), - ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS), - ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS), - ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryData', union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData), -] - -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS -class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS * 96), -] - -NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS -NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601) # macro -NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040) # macro -NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1) # macro -# NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED = 0 : 0 # macro -NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000) # macro -NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001) # macro -# NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED = 1 : 1 # macro -NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000) # macro -NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602) # macro -NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603) # macro -NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604) # macro -NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64 # macro -NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS._fields_ = [ - ('gspFeatures', ctypes.c_uint32), - ('bValid', ctypes.c_ubyte), - ('bDefaultGspRmGpu', ctypes.c_ubyte), - ('firmwareVersion', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_GSP_GET_FEATURES_PARAMS = struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS -class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(Structure): - pass - -struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT._pack_ = 1 # source:False -struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('usableSize', ctypes.c_uint64), - ('memTrackOverhead', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT = struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT -class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('managedSize', ctypes.c_uint64), - ('largestFreeChunkSize', ctypes.c_uint64), - ('current', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), - ('peak', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), -] - -NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS = struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS -class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('peakAllocatedSize', ctypes.c_uint64), - ('managedSize', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('peakAllocationCount', ctypes.c_uint32), - ('largestFreeChunkSize', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS -class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(Structure): - pass - -struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS._pack_ = 1 # source:False -struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS._fields_ = [ - ('allocations', ctypes.c_uint32), - ('peakAllocations', ctypes.c_uint32), - ('objectSize', ctypes.c_uint64), -] - -NV2080_CTRL_GSP_LIBOS_POOL_STATS = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS -class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS._fields_ = [ - ('poolStats', struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS * 64), - ('totalHeapSize', ctypes.c_uint64), - ('poolCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS -NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101) # macro -NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102) # macro -class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS._fields_ = [ - ('hshubNcisocMask', ctypes.c_uint32), - ('hshubNvlMask', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS -class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS._fields_ = [ - ('ecMode', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS -NV2080_CTRL_I2C_VERSION_0 = 0x00 # macro -NV2080_CTRL_I2C_MAX_ENTRIES = 256 # macro -NV2080_CTRL_I2C_MAX_REG_LEN = 8 # macro -NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20 # macro -NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001) # macro -NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002) # macro -NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004) # macro -NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010) # macro -NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008) # macro -NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601) # macro -NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602) # macro -NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603) # macro -NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604) # macro -NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610) # macro -NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5 # macro -NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6 # macro -NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13 # macro -NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14 # macro -NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15 # macro -NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17 # macro -NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000 # macro -NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0 # macro -NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5 # macro -NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6 # macro -NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7 # macro -NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8 # macro -NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9 # macro -NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_NUM_PORTS = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5 # macro -NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620) # macro -NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20) # macro -class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('inputCount', ctypes.c_uint32), - ('inputBuffer', ctypes.c_ubyte * 256), - ('outputCount', ctypes.c_uint32), - ('outputBuffer', ctypes.c_ubyte * 256), -] - -NV2080_CTRL_I2C_READ_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS -class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('inputCount', ctypes.c_uint32), - ('inputBuffer', ctypes.c_ubyte * 256), - ('encrClientID', ctypes.c_uint32), -] - -NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS -class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_RW_REG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_I2C_RW_REG_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('addr', ctypes.c_uint32), - ('reg', ctypes.c_ubyte), - ('bufsize', ctypes.c_ubyte), - ('buffer', ctypes.c_ubyte * 255), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_I2C_RW_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS -NV2080_CTRL_I2C_READ_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS -NV2080_CTRL_I2C_WRITE_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS -class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_ACCESS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_I2C_ACCESS_PARAMS._fields_ = [ - ('token', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('dataBuffSize', ctypes.c_uint32), - ('speed', ctypes.c_uint32), - ('encrClientID', ctypes.c_uint32), -] - -NV2080_CTRL_I2C_ACCESS_PARAMS = struct_NV2080_CTRL_I2C_ACCESS_PARAMS -class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._fields_ = [ - ('head', ctypes.c_uint32), - ('authType', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c) # macro -NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d) # macro -NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64 # macro -NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D) # macro -NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e) # macro -NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E) # macro -NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F) # macro -NV2080_CTRL_INTERNAL_GR_MAX_SM = 240 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = 8 # macro -NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = 8 # macro -NV2080_CTRL_INTERNAL_GR_MAX_GPC = 12 # macro -NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128 # macro -NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28) # macro -NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36) # macro -NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16 # macro -NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512 # macro -NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40) # macro -NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41) # macro -NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 4096 # macro -NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096 # macro -NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43) # macro -NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45) # macro -NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x20800a46) # macro -NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49) # macro -NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49) # macro -NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c) # macro -NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d) # macro -NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D) # macro -NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 60 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52) # macro -NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2 # macro -NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64 # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53) # macro -NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54) # macro -NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55) # macro -NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73) # macro -NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74) # macro -NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75) # macro -NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57) # macro -NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128 # macro -NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58) # macro -NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59) # macro -NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a) # macro -NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b) # macro -NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c) # macro -NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128 # macro -# NV2080_INTR_INVALID_SUBTREE = NV_U8_MAX # macro -NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C) # macro -NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98) # macro -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99) # macro -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60) # macro -NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67) # macro -NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8 # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B) # macro -NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x20800a7a) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR = (0x20800a7c) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81) # macro -NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A) # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = 1 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b) # macro -NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256 # macro -NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c) # macro -NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000) # macro -NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d) # macro -NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000 # macro -NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e) # macro -NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f) # macro -NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2) # macro -NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 8 # macro -NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 12 # macro -NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3) # macro -NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4) # macro -NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5) # macro -NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6) # macro -NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4 # macro -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7) # macro -NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9) # macro -NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac) # macro -NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88) # macro -NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32 # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c) # macro -NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d) # macro -NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS = (0x20800ab0) # macro -NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID = (0xb0) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32 # macro -NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f) # macro -NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3) # macro -NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1 # macro -NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4) # macro -NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4) # macro -NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5) # macro -NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5) # macro -NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6) # macro -NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6) # macro -NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8) # macro -NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9) # macro -NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd) # macro -NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe) # macro -NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf) # macro -NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0) # macro -NV2080_MAX_NUM_HEADS = 4 # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1) # macro -NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4) # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9) # macro -NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca) # macro -NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA) # macro -NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2) # macro -NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3) # macro -NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5) # macro -NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5) # macro -NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6) # macro -NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000) # macro -NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8) # macro -NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb) # macro -NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB) # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03 # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc) # macro -NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd) # macro -NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD) # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01 # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6) # macro -NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7) # macro -NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb) # macro -NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB) # macro -NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc) # macro -NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC) # macro -NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add) # macro -NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade) # macro -NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE) # macro -NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf) # macro -MAX_EDID_SIZE_FROM_SBIOS = 512 # macro -NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2) # macro -NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4) # macro -NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7) # macro -NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF) # macro -NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa) # macro -CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10) # macro -NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD) # macro -NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE) # macro -NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe) # macro -NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF) # macro -NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff) # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3) # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3) # macro -NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF) # macro -NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf) # macro -NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4) # macro -NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4) # macro -NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9) # macro -NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea) # macro -NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA) # macro -NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb) # macro -NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec) # macro -NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14) # macro -NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09 # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6 # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7) # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D # macro -NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0 # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1 # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42) # macro -NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e) # macro -NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50) # macro -NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56) # macro -NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81) # macro -NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1 # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2 # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f) # macro -NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83) # macro -NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84) # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64 # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85) # macro -NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87) # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6 # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f) # macro -NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91) # macro -NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93) # macro -NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95) # macro -NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97) # macro -NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab) # macro -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS._fields_ = [ - ('feHwSysCap', ctypes.c_uint32), - ('windowPresentMask', ctypes.c_uint32), - ('bFbRemapperEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numHeads', ctypes.c_uint32), - ('i2cPort', ctypes.c_uint32), - ('internalDispActiveMask', ctypes.c_uint32), - ('embeddedDisplayPortMask', ctypes.c_uint32), - ('bExternalMuxSupported', ctypes.c_ubyte), - ('bInternalMuxSupported', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('numDispChannels', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS._fields_ = [ - ('bOneToOneComptagLineAllocation', ctypes.c_ubyte), - ('bUseOneToFourComptagLineAllocation', ctypes.c_ubyte), - ('bUseRawModeComptaglineAllocation', ctypes.c_ubyte), - ('bDisableCompbitBacking', ctypes.c_ubyte), - ('bDisablePostL2Compression', ctypes.c_ubyte), - ('bEnabledEccFBPA', ctypes.c_ubyte), - ('bL2PreFill', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('l2CacheSize', ctypes.c_uint64), - ('bFbpaPresent', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('comprPageSize', ctypes.c_uint32), - ('comprPageShift', ctypes.c_uint32), - ('ramType', ctypes.c_uint32), - ('ltcCount', ctypes.c_uint32), - ('ltsPerLtcCount', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [ - ('accessCounterIndex', ctypes.c_uint32), - ('bufferSize', ctypes.c_uint32), - ('bufferPteArray', ctypes.c_uint64 * 64), -] - -NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [ - ('accessCounterIndex', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 23), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_CAPS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineCaps', struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0._fields_ = [ - ('gpcId', ctypes.c_uint16), - ('localTpcId', ctypes.c_uint16), - ('localSmId', ctypes.c_uint16), - ('globalTpcId', ctypes.c_uint16), - ('virtualGpcId', ctypes.c_uint16), - ('migratableTpcId', ctypes.c_uint16), -] - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER._fields_ = [ - ('globalSmId', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0 * 240), - ('numSm', ctypes.c_uint16), - ('numTpc', ctypes.c_uint16), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('globalSmOrder', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS -class struct_NV2080_CTRL_INTERNAL_BSP_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BSP_CAPS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BSP_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_INTERNAL_BSP_CAPS = struct_NV2080_CTRL_INTERNAL_BSP_CAPS -class struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS._fields_ = [ - ('caps', struct_NV2080_CTRL_INTERNAL_BSP_CAPS * 8), - ('valid', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_MSENC_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MSENC_CAPS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MSENC_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_MSENC_CAPS = struct_NV2080_CTRL_INTERNAL_MSENC_CAPS -class struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS._fields_ = [ - ('caps', struct_NV2080_CTRL_INTERNAL_MSENC_CAPS * 8), - ('valid', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS._fields_ = [ - ('gpcMask', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32 * 12), - ('tpcCount', ctypes.c_uint32 * 12), - ('physGpcMask', ctypes.c_uint32), - ('mmuPerGpc', ctypes.c_uint32 * 12), - ('tpcToPesMap', ctypes.c_uint32 * 10), - ('numPesPerGpc', ctypes.c_uint32 * 12), - ('zcullMask', ctypes.c_uint32 * 12), - ('physGfxGpcMask', ctypes.c_uint32), - ('numGfxTpc', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('floorsweepingMasks', struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS -class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('bufferType', ctypes.c_uint32), - ('firstPage', ctypes.c_uint32), - ('numPages', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physAddrs', ctypes.c_uint64 * 128), - ('bNoMorePages', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS = struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cpuCacheAttrib', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_MEMDESC_INFO = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO -class struct_NV2080_CTRL_INTERNAL_GR_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GR_INFO._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GR_INFO = struct_NV2080_CTRL_INTERNAL_GR_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('infoList', struct_NV2080_CTRL_INTERNAL_GR_INFO * 58), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO._fields_ = [ - ('widthAlignPixels', ctypes.c_uint32), - ('heightAlignPixels', ctypes.c_uint32), - ('pixelSquaresByAliquots', ctypes.c_uint32), - ('aliquotTotal', ctypes.c_uint32), - ('zcullRegionByteMultiplier', ctypes.c_uint32), - ('zcullRegionHeaderSize', ctypes.c_uint32), - ('zcullSubregionHeaderSize', ctypes.c_uint32), - ('subregionCount', ctypes.c_uint32), - ('subregionWidthAlignPixels', ctypes.c_uint32), - ('subregionHeightAlignPixels', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineZcullInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO._fields_ = [ - ('ropUnitCount', ctypes.c_uint32), - ('ropOperationsFactor', ctypes.c_uint32), - ('ropOperationsCount', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineRopInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS._fields_ = [ - ('mask', ctypes.c_uint32 * 12), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('enginePpcMasks', struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO._fields_ = [ - ('size', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO = struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engine', struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO * 26), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineContextBuffersInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER._fields_ = [ - ('imla0', ctypes.c_ubyte), - ('fmla16', ctypes.c_ubyte), - ('dp', ctypes.c_ubyte), - ('fmla32', ctypes.c_ubyte), - ('ffma', ctypes.c_ubyte), - ('imla1', ctypes.c_ubyte), - ('imla2', ctypes.c_ubyte), - ('imla3', ctypes.c_ubyte), - ('imla4', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('smIssueRateModifier', struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS._fields_ = [ - ('chipSubRev', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('emulationRev1', ctypes.c_uint32), - ('isCmpSku', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('pciDeviceId', ctypes.c_uint32), - ('pciSubDeviceId', ctypes.c_uint32), - ('pciRevisionId', ctypes.c_uint32), - ('regBases', ctypes.c_uint32 * 16), -] - -NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('offset', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE._fields_ = [ - ('fecsRecordSize', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fecsRecordSize', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES._fields_ = [ - ('fecsRecordSize', ctypes.c_uint32), - ('timestampHiTagMask', ctypes.c_uint32), - ('timestampHiTagShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('timestampVMask', ctypes.c_uint64), - ('numLowerBitsZeroShift', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fecsTraceDefines', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DEVICE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DEVICE_INFO._fields_ = [ - ('faultId', ctypes.c_uint32), - ('instanceId', ctypes.c_uint32), - ('typeEnum', ctypes.c_uint32), - ('resetId', ctypes.c_uint32), - ('devicePriBase', ctypes.c_uint32), - ('isEngine', ctypes.c_uint32), - ('rlEngId', ctypes.c_uint32), - ('runlistPriBase', ctypes.c_uint32), - ('groupId', ctypes.c_uint32), - ('ginTargetId', ctypes.c_uint32), - ('deviceBroadcastPriBase', ctypes.c_uint32), - ('groupLocalInstanceId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DEVICE_INFO = struct_NV2080_CTRL_INTERNAL_DEVICE_INFO -class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('deviceInfoTable', struct_NV2080_CTRL_INTERNAL_DEVICE_INFO * 512), -] - -NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS._fields_ = [ - ('userRegisterAccessMapSize', ctypes.c_uint32), - ('compressedSize', ctypes.c_uint32), - ('compressedData', ctypes.c_ubyte * 4096), - ('profilingRangesSize', ctypes.c_uint32), - ('profilingRanges', ctypes.c_ubyte * 4096), -] - -NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS -class struct_NV2080_CTRL_INTERNAL_NV_RANGE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NV_RANGE._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NV_RANGE._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_NV_RANGE = struct_NV2080_CTRL_INTERNAL_NV_RANGE -class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memAddrRange', NV2080_CTRL_INTERNAL_NV_RANGE), -] - -NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS -NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS._fields_ = [ - ('bTeardown', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS -NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES._fields_ = [ - ('bPerSubCtxheaderSupported', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('pdbTable', struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES * 8), - ] - -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS._fields_ = [ - ('instMemPhysAddr', ctypes.c_uint64), - ('instMemSize', ctypes.c_uint64), - ('instMemAddrSpace', ctypes.c_uint32), - ('instMemCpuCacheAttr', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS._fields_ = [ - ('ipVersion', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS._fields_ = [ - ('smcMode', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS._fields_ = [ - ('head', ctypes.c_uint32), - ('rgLineNum', ctypes.c_uint32), - ('intrLine', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS -class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('grCount', ctypes.c_uint32), - ('gfxGrCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('validCTSIdMask', ctypes.c_uint64), - ('validGfxCTSIdMask', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS._fields_ = [ - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('table', struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO * 60), -] - -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS._fields_ = [ - ('partitionableMemSize', ctypes.c_uint64), - ('bottomRsvdSize', ctypes.c_uint64), - ('topRsvdSize', ctypes.c_uint64), - ('partitionableStartAddr', ctypes.c_uint64), - ('partitionableEndAddr', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS._fields_ = [ - ('engineMask', ctypes.c_uint64 * 4), -] - -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS._fields_ = [ - ('rlBuffers', struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2 * 64), - ('runlistIdMask', ctypes.c_uint64), - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(Structure): - pass - -class struct_TEGRA_IMP_IMPORT_DATA(Structure): - pass - -class struct_DRAM_CLK_INSTANCE(Structure): - pass - -struct_DRAM_CLK_INSTANCE._pack_ = 1 # source:False -struct_DRAM_CLK_INSTANCE._fields_ = [ - ('dram_clk_freq_khz', ctypes.c_uint32), - ('mchub_clk_khz', ctypes.c_uint32), - ('mc_clk_khz', ctypes.c_uint32), - ('max_iso_bw_kbps', ctypes.c_uint32), - ('switch_latency_ns', ctypes.c_uint32), -] - -struct_TEGRA_IMP_IMPORT_DATA._pack_ = 1 # source:False -struct_TEGRA_IMP_IMPORT_DATA._fields_ = [ - ('max_iso_bw_kbps', ctypes.c_uint32), - ('num_dram_channels', ctypes.c_uint32), - ('num_dram_clk_entries', ctypes.c_uint32), - ('dram_clk_instance', struct_DRAM_CLK_INSTANCE * 24), -] - -struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS._fields_ = [ - ('tegraImpImportData', struct_TEGRA_IMP_IMPORT_DATA), -] - -NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS._fields_ = [ - ('pciDeviceId', ctypes.c_uint16), - ('pciSubDeviceId', ctypes.c_uint16), - ('iseGPUBridge', ctypes.c_ubyte), - ('approvedBusType', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS._fields_ = [ - ('local2Remote', ctypes.c_uint32), - ('remote2Local', ctypes.c_uint32), - ('localP2PDomainRemoteAddr', ctypes.c_uint64), - ('remoteP2PDomainLocalAddr', ctypes.c_uint64), - ('remoteWMBoxLocalAddr', ctypes.c_uint64), - ('p2pWmbTag', ctypes.c_uint64), - ('bNeedWarBug999673', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS._fields_ = [ - ('local2Remote', ctypes.c_uint32), - ('remote2Local', ctypes.c_uint32), - ('localP2PDomainRemoteAddr', ctypes.c_uint64), - ('remoteP2PDomainLocalAddr', ctypes.c_uint64), - ('remoteWMBoxAddrU64', ctypes.c_uint64), - ('p2pWmbTag', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS._fields_ = [ - ('peerIdx', ctypes.c_uint32), - ('bNeedWarBug999673', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('numEntries', ctypes.c_uint32), - ('gpaEntries', ctypes.c_uint64 * 128), - ('spaEntries', ctypes.c_uint64 * 128), -] - -NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS = struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS._fields_ = [ - ('addressSpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physicalAddr', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('cacheSnoop', ctypes.c_uint32), - ('hclass', ctypes.c_uint32), - ('channelInstance', ctypes.c_uint32), - ('valid', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('pbTargetAperture', ctypes.c_uint32), - ('channelPBSize', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS._fields_ = [ - ('replayableFaultBufferSize', ctypes.c_uint32), - ('replayableShadowFaultBufferMetadataSize', ctypes.c_uint32), - ('nonReplayableFaultBufferSize', ctypes.c_uint32), - ('nonReplayableShadowFaultBufferMetadataSize', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS -NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS._fields_ = [ - ('moduleIndex', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS - -# values for enumeration 'NV2080_INTR_CATEGORY' -NV2080_INTR_CATEGORY__enumvalues = { - 0: 'NV2080_INTR_CATEGORY_DEFAULT', - 1: 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', - 2: 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', - 3: 'NV2080_INTR_CATEGORY_RUNLIST', - 4: 'NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', - 5: 'NV2080_INTR_CATEGORY_UVM_OWNED', - 6: 'NV2080_INTR_CATEGORY_UVM_SHARED', - 7: 'NV2080_INTR_CATEGORY_ENUM_COUNT', -} -NV2080_INTR_CATEGORY_DEFAULT = 0 -NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1 -NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2 -NV2080_INTR_CATEGORY_RUNLIST = 3 -NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4 -NV2080_INTR_CATEGORY_UVM_OWNED = 5 -NV2080_INTR_CATEGORY_UVM_SHARED = 6 -NV2080_INTR_CATEGORY_ENUM_COUNT = 7 -NV2080_INTR_CATEGORY = ctypes.c_uint32 # enum -class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(Structure): - pass - -struct_NV2080_INTR_CATEGORY_SUBTREE_MAP._pack_ = 1 # source:False -struct_NV2080_INTR_CATEGORY_SUBTREE_MAP._fields_ = [ - ('subtreeStart', ctypes.c_ubyte), - ('subtreeEnd', ctypes.c_ubyte), -] - -NV2080_INTR_CATEGORY_SUBTREE_MAP = struct_NV2080_INTR_CATEGORY_SUBTREE_MAP -class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY._fields_ = [ - ('engineIdx', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pmcIntrMask', ctypes.c_uint32), - ('vectorStall', ctypes.c_uint32), - ('vectorNonStall', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY -class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS._fields_ = [ - ('tableLen', ctypes.c_uint32), - ('table', struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY * 128), - ('subtreeMap', struct_NV2080_INTR_CATEGORY_SUBTREE_MAP * 7), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS._fields_ = [ - ('bReservation', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS._fields_ = [ - ('bReservation', ctypes.c_ubyte), - ('bClientHandlesGrGating', ctypes.c_ubyte), - ('bRmHandlesIdleSlow', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS._fields_ = [ - ('displayMask', ctypes.c_uint32), - ('numHeads', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fbMemPageRanges', struct_NV2080_CTRL_INTERNAL_NV_RANGE * 15), - ] - -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._fields_ = [ - ('runlistId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS._fields_ = [ - ('memBoundaryCfgA', ctypes.c_uint64), - ('memBoundaryCfgB', ctypes.c_uint64), - ('memBoundaryCfgC', ctypes.c_uint32), - ('memBoundaryCfg', ctypes.c_uint32), - ('memBoundaryCfgValInit', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS -NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS._fields_ = [ - ('data', ctypes.c_uint32 * 8), -] - -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X._fields_ = [ - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('duration', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [ - ('bActivate', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('bBridgeless', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('currLimits', ctypes.c_uint32 * 2), -] - -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS._fields_ = [ - ('hysteresisus', ctypes.c_uint64), - ('bHystersisEnable', ctypes.c_ubyte), - ('bSliGpuBoostSyncEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('faultBufferSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('faultBufferPteArray', ctypes.c_uint64 * 256), -] - -NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [ - ('shadowFaultBufferQueuePhysAddr', ctypes.c_uint64), - ('shadowFaultBufferSize', ctypes.c_uint32), - ('shadowFaultBufferMetadataSize', ctypes.c_uint32), - ('shadowFaultBufferPteArray', ctypes.c_uint64 * 3000), - ('shadowFaultBufferType', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('faultBufferSharedMemoryPhysAddr', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [ - ('shadowFaultBufferType', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('pageShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), - ('numLevelsToCopy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0 * 6), -] - -struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._fields_ = [ - ('PdeCopyParams', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), -] - -NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X._fields_ = [ - ('flags', ctypes.c_uint32), - ('boostDuration', ctypes.c_uint32), - ('gfId', ctypes.c_uint32), - ('bOverrideInfinite', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X._fields_ = [ - ('bIsCudaClient', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X -class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO._fields_ = [ - ('skylineVgpcSize', ctypes.c_ubyte * 12), - ('singletonVgpcMask', ctypes.c_uint32), - ('maxInstances', ctypes.c_uint32), - ('computeSizeFlag', ctypes.c_uint32), - ('numNonSingletonVgpcs', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO = struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS._fields_ = [ - ('skylineTable', struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO * 8), - ('validEntries', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS._fields_ = [ - ('bZbcSurfacesExist', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS -class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO._fields_ = [ - ('enginesMask', ctypes.c_uint64 * 4), - ('partitionFlags', ctypes.c_uint32), - ('gpcMask', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('veidOffset', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO = struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO -class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('info', NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO), -] - -NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS._fields_ = [ - ('bPcieGen4Capable', ctypes.c_ubyte), - ('bIsC2CLinkUp', ctypes.c_ubyte), - ('bIsDeviceMultiFunction', ctypes.c_ubyte), - ('bGcxPmuCfgSpaceRestore', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS._fields_ = [ - ('programPeerMask', ctypes.c_uint32), - ('invalidatePeerMask', ctypes.c_uint32), - ('programPciePeerMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('hshubIds', ctypes.c_ubyte * 32), -] - -NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS._fields_ = [ - ('numHshubs', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS._fields_ = [ - ('hshubId', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS._fields_ = [ - ('egmPeerId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS._fields_ = [ - ('bGet', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('addr', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS._fields_ = [ - ('bCyaMaskL1', ctypes.c_ubyte), - ('bEnableAspmDtL1', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS._fields_ = [ - ('maxActiveVGpuVMCount', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS._fields_ = [ - ('bRawMode', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS._fields_ = [ - ('ccuSampleSize', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO._fields_ = [ - ('phyAddr', ctypes.c_uint64), - ('shrBufSize', ctypes.c_uint32), - ('cntBlkSize', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_CCU_MAP_INFO = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO -class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('mapInfo', struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO * 9), - ] - -NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS._fields_ = [ - ('bDevShrBuf', ctypes.c_ubyte), - ('bMigShrBuf', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerId', ctypes.c_uint32), - ('busEgmPeerId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO -class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS._fields_ = [ - ('peerGpuCount', ctypes.c_uint32), - ('peerGpuInfos', struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO * 32), -] - -NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS._fields_ = [ - ('peerGpuIdCount', ctypes.c_uint32), - ('peerGpuIds', ctypes.c_uint32 * 32), -] - -NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS._fields_ = [ - ('bCommonPciSwitchFound', ctypes.c_ubyte), - ('p2pReadCapsStatus', ctypes.c_ubyte), - ('p2pWriteCapsStatus', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS._fields_ = [ - ('enableRo', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('bUseVbios', ctypes.c_ubyte), - ('bReturnEarly', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('bUseVbios', ctypes.c_ubyte), - ('bVbiosCallSuccessful', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE._fields_ = [ - ('computeSize', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('physicalSlots', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE = struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS._fields_ = [ - ('profileCount', ctypes.c_uint32), - ('profiles', struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE * 8), -] - -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS._fields_ = [ - ('bStreamState', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS._fields_ = [ - ('bExtDevFound', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(Structure): - pass - -class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(Structure): - pass - -struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS._pack_ = 1 # source:False -struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('output', ctypes.c_uint32), - ('protocol', ctypes.c_uint32), - ('structure', ctypes.c_uint32), - ('adjust', ctypes.c_uint32), - ('hDeltaStep', ctypes.c_uint32), - ('hDeltaMax', ctypes.c_uint32), - ('vDeltaStep', ctypes.c_uint32), - ('vDeltaMax', ctypes.c_uint32), - ('hSyncEnd', ctypes.c_uint32), - ('hBlankEnd', ctypes.c_uint32), - ('hBlankStart', ctypes.c_uint32), - ('hTotal', ctypes.c_uint32), - ('vSyncEnd', ctypes.c_uint32), - ('vBlankEnd', ctypes.c_uint32), - ('vBlankStart', ctypes.c_uint32), - ('vInterlacedBlankEnd', ctypes.c_uint32), - ('vInterlacedBlankStart', ctypes.c_uint32), - ('vTotal', ctypes.c_uint32), - ('refreshX10K', ctypes.c_uint32), - ('pixelClockHz', ctypes.c_uint64), - ('bOptimized', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS._fields_ = [ - ('timingParameters', struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS), -] - -NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS._fields_ = [ - ('displayIds', ctypes.c_uint32 * 4), -] - -NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS._fields_ = [ - ('slave', ctypes.c_uint32 * 4), - ('localSlave', ctypes.c_uint32 * 4), - ('master', ctypes.c_uint32 * 4), - ('regStatus', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS._fields_ = [ - ('headIdx', ctypes.c_uint32), - ('vActiveLines', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS._fields_ = [ - ('displays', ctypes.c_uint32), - ('displayId', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS._fields_ = [ - ('bEnableMaster', ctypes.c_ubyte), - ('bRasterSyncGpioSaved', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('bRasterSyncGpioDirection', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS -class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hSysMem', ctypes.c_uint32), - ('bEnteringGcoffState', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('sysmemAddrOfSuspendResumeData', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS._fields_ = [ - ('bDisableActiveChannels', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS._fields_ = [ - ('hostReservedFb', ctypes.c_uint64), - ('vgpuTypeId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS -class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS._fields_ = [ - ('status', ctypes.c_uint32), - ('backLightDataSize', ctypes.c_uint16), - ('backLightData', ctypes.c_ubyte * 4096), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS._fields_ = [ - ('numActiveLinksPerIoctrl', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS._fields_ = [ - ('numLinksPerIoctrl', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS -class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS._fields_ = [ - ('bIsSysCtrlSupported', ctypes.c_ubyte), - ('bIsPlatformLegacy', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS = struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI._fields_ = [ - ('sensorId', ctypes.c_uint32), - ('limit', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI), - ] - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('data', union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data), -] - -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS._fields_ = [ - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA), -] - -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS -NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS -NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS._fields_ = [ - ('flag', ctypes.c_ubyte), - ('bStatus', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('clientLimit', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS._fields_ = [ - ('targetTemp', ctypes.c_int32), -] - -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS._fields_ = [ - ('ctgpOffsetmW', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS._fields_ = [ - ('bVpsPs20Supported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vPstateIdxHighest', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS._fields_ = [ - ('pStateIdx', ctypes.c_uint32), - ('vPstateIdxMapping', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS._fields_ = [ - ('vPstateIdx', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS._fields_ = [ - ('bIsGC6Satisfied', ctypes.c_ubyte), - ('bIsGCOFFSatisfied', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS = struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [ - ('maxSec2SecureChannels', ctypes.c_uint32), - ('maxCeSecureChannels', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS._fields_ = [ - ('pinSetIn', ctypes.c_uint32), - ('pinSetOut', ctypes.c_uint32), - ('bMasterScanLock', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('masterScanLockPin', ctypes.c_uint32), - ('bSlaveScanLock', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('slaveScanLockPin', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS._fields_ = [ - ('pinSet', ctypes.c_uint32), - ('gpioFunction', ctypes.c_uint32), - ('gpioPin', ctypes.c_uint32), - ('gpioDirection', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS -class struct_NV2080_CTRL_INTERNAL_EDID_DATA(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_EDID_DATA._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_EDID_DATA._fields_ = [ - ('status', ctypes.c_uint32), - ('acpiId', ctypes.c_uint32), - ('bufferSize', ctypes.c_uint32), - ('edidBuffer', ctypes.c_ubyte * 512), -] - -NV2080_CTRL_INTERNAL_EDID_DATA = struct_NV2080_CTRL_INTERNAL_EDID_DATA -class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS._fields_ = [ - ('tableLen', ctypes.c_uint32), - ('edidTable', struct_NV2080_CTRL_INTERNAL_EDID_DATA * 16), -] - -NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('numProbes', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('bwMode', ctypes.c_ubyte), - ('bLocalEgmEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('bwMode', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS._fields_ = [ - ('bIsBar1Trusted', ctypes.c_ubyte), - ('bIsPcieTrusted', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK._fields_ = [ - ('ivMask', ctypes.c_uint32 * 3), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('ivMaskSet', struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 3), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('ivMaskSet', struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 6), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS._fields_ = [ - ('globalH2DKey', ctypes.c_uint32), - ('updatedEncryptIVMask', ctypes.c_uint32 * 3), - ('updatedDecryptIVMask', ctypes.c_uint32 * 3), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [ - ('exceptionType', ctypes.c_uint32), - ('globalH2DKey', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS._fields_ = [ - ('attackerAdvantage', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS._fields_ = [ - ('logicalUprocId', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS - -# values for enumeration 'NV2080_CTRL_MEMMGR_MEMORY_OP' -NV2080_CTRL_MEMMGR_MEMORY_OP__enumvalues = { - 0: 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', - 1: 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', -} -NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0 -NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1 -NV2080_CTRL_MEMMGR_MEMORY_OP = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO._fields_ = [ - ('baseAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('cpuCacheAttrib', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO = struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO -class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS._fields_ = [ - ('src', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), - ('authTag', ctypes.c_ubyte * 16), - ('dst', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), - ('transferSize', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('memop', NV2080_CTRL_MEMMGR_MEMORY_OP), -] - -NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS._fields_ = [ - ('addrSysPhys', ctypes.c_uint64), - ('addrWidth', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('maskWidth', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('addrSysPhys', ctypes.c_uint64), - ('addrWidth', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('maskWidth', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS._fields_ = [ - ('limitMin', ctypes.c_uint32), - ('limitRated', ctypes.c_uint32), - ('limitMax', ctypes.c_uint32), - ('limitCurr', ctypes.c_uint32), - ('limitBattRated', ctypes.c_uint32), - ('limitBattMax', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS._fields_ = [ - ('physAddr', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS -class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS._fields_ = [ - ('polledDataMask', ctypes.c_uint64), - ('pollFrequencyMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS = struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS._fields_ = [ - ('tracepointMask', ctypes.c_uint64), - ('bufferAddr', ctypes.c_uint64), - ('bufferSize', ctypes.c_uint32), - ('bufferWatermark', ctypes.c_uint32), - ('flag', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS._fields_ = [ - ('bMaxwellSec2Enabled', ctypes.c_ubyte), - ('bNv95A1TsecEnabled', ctypes.c_ubyte), - ('bHopperSec2WorkLaunchAEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS -NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS._fields_ = [ - ('bInPMTransition', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('newPMLevel', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS._fields_ = [ - ('bSuccessful', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS._fields_ = [ - ('freeHeapSize', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS._fields_ = [ - ('bApplyStereoPinAlwaysHiWar', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS._fields_ = [ - ('maxHshubs', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS._fields_ = [ - ('rasterSyncDecodeMode', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS._fields_ = [ - ('spaValue', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS._fields_ = [ - ('seedData', ctypes.c_uint32 * 7), -] - -NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS._fields_ = [ - ('remoteDeviceType', ctypes.c_uint32), - ('ipVerDlPl', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS._fields_ = [ - ('seedData', ctypes.c_uint32 * 7), -] - -NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO._fields_ = [ - ('remoteSid', ctypes.c_uint64), - ('remoteDeviceType', ctypes.c_uint32), - ('remoteLinkId', ctypes.c_uint32), - ('localSid', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS._fields_ = [ - ('bInitnegotiateConfigGood', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), -] - -NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS._fields_ = [ - ('bPollDone', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(Union): - pass - -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._pack_ = 1 # source:False -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._fields_ = [ - ('linkModeOffParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS), - ('linkModePreHsParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS), - ('linkModeInitPhase1Params', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS), - ('linkModePostInitNegotiateParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS), - ('linkModePostInitOptimizeParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 31), -] - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkMode', ctypes.c_uint32), - ('linkModeParams', union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS._fields_ = [ - ('sublinkMode', ctypes.c_uint32), - ('sublinkSubMode', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS._fields_ = [ - ('laneRxdetStatusMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS._fields_ = [ - ('bSync', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS._fields_ = [ - ('ipVerDlPl', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('token', ctypes.c_uint64), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS._fields_ = [ - ('bUnlocked', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(Union): - pass - -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._pack_ = 1 # source:False -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._fields_ = [ - ('getDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS), - ('setDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS), - ('getTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS), - ('setTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS), - ('getTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), - ('setTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS), - ('getRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), - ('setRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS), - ('getRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS), - ('setRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS), - ('writeDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), - ('readDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), - ('getUphyLoad', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 47), -] - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('callbackParams', union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams), -] - -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE -class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callbackType', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE), -] - -NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), -] - -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS._fields_ = [ - ('bEnableAli', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS._fields_ = [ - ('updateType', ctypes.c_ubyte), - ('bSysMem', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('peerMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), - ('peerLinkMask', ctypes.c_uint32), - ('bEgmPeer', ctypes.c_ubyte), - ('bNvswitchConn', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS._fields_ = [ - ('xid', ctypes.c_uint32), - ('message', ctypes.c_ubyte * 81), - ('PADDING_0', ctypes.c_ubyte * 3), - ('len', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS = struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS._fields_ = [ - ('mapTypeMask', ctypes.c_uint32), - ('peerMask', ctypes.c_uint32), - ('bL2Entry', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('bSysmem', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('peerLinkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS._fields_ = [ - ('bNvlinkSysmemEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS._fields_ = [ - ('gpuInst', ctypes.c_uint32), - ('peerLinkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS._fields_ = [ - ('remoteDeviceType', ctypes.c_uint64), - ('remoteChipSid', ctypes.c_uint64), - ('linkId', ctypes.c_uint32), - ('laneRxdetStatusMask', ctypes.c_uint32), - ('remoteLinkNumber', ctypes.c_uint32), - ('remotePciDeviceId', ctypes.c_uint32), - ('remoteDomain', ctypes.c_uint32), - ('remoteBus', ctypes.c_ubyte), - ('remoteDevice', ctypes.c_ubyte), - ('remoteFunction', ctypes.c_ubyte), - ('bConnected', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('initializedLinks', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS._fields_ = [ - ('postRxDetLinkMask', ctypes.c_uint64), - ('laneRxdetStatusMask', ctypes.c_uint32 * 64), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('linkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('ioctrlId', ctypes.c_uint32), - ('pllMasterLinkId', ctypes.c_ubyte), - ('pllSlaveLinkId', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('ipVerDlPl', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS._fields_ = [ - ('ioctrlMask', ctypes.c_uint32), - ('ioctrlNumEntries', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ioctrlSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('discoveredLinks', ctypes.c_uint64), - ('ipVerNvlink', ctypes.c_uint32), - ('linkInfo', struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES * 64), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES._fields_ = [ - ('ipVerIoctrl', ctypes.c_uint32), - ('ipVerMinion', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS._fields_ = [ - ('ioctrlIdx', ctypes.c_uint32), - ('PublicId', ctypes.c_uint32), - ('localDiscoveredLinks', ctypes.c_uint32), - ('localGlobalLinkOffset', ctypes.c_uint32), - ('ioctrlDiscoverySize', ctypes.c_uint32), - ('numDevices', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ipRevisions', NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS._fields_ = [ - ('bPlatformLinerateDefined', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('platformLineRate', ctypes.c_uint32), - ('nvlinkLinkSpeed', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bActiveOnly', ctypes.c_ubyte), - ('bIsLinkActive', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES._fields_ = [ - ('bLinkConnectedToSystem', ctypes.c_ubyte), - ('bLinkConnectedToPeer', ctypes.c_ubyte), - ('bLinkReset', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('linkState', ctypes.c_uint32), - ('txSublinkState', ctypes.c_uint32), - ('rxSublinkState', ctypes.c_uint32), - ('bLaneReversal', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('nvlinkLinkClockMhz', ctypes.c_uint32), - ('nvlinkLinkDataRateKiBps', ctypes.c_uint32), - ('nvlinkRefClkType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('nvlinkReqLinkClockMhz', ctypes.c_uint32), - ('nvlinkMinL1Threshold', ctypes.c_uint32), - ('nvlinkMaxL1Threshold', ctypes.c_uint32), - ('nvlinkL1ThresholdUnits', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('nvlinkRefClkSpeedKHz', ctypes.c_uint32), - ('bSublinkStateInst', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkInfo', struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES * 64), -] - -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS._fields_ = [ - ('sysmemLinkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS._fields_ = [ - ('bLegacyForcedConfig', ctypes.c_ubyte), - ('bOverrideComputePeerMode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('phase', ctypes.c_uint32), - ('linkConnection', ctypes.c_uint32 * 64), -] - -NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS._fields_ = [ - ('bLaneShutdownOnUnload', ctypes.c_ubyte), -] - -NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS._fields_ = [ - ('notUsed', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS._fields_ = [ - ('sysmemLinkMask', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS -NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003) # macro -NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004) # macro -NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS._fields_ = [ - ('ctrlParamVal', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS -class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS._fields_ = [ - ('responseVal', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS -NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701) # macro -NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B = (0x0000000B) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003) # macro -NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702) # macro -NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001 # macro -NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF # macro -NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703) # macro -NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c) # macro -NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d) # macro -NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256 # macro -NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e) # macro -NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32 # macro -NV2080_INTR_TYPE_NULL = (0x00000000) # macro -NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001) # macro -NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002) # macro -NV2080_INTR_TYPE_INFO_FAULT = (0x00000003) # macro -NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004) # macro -NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005) # macro -NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006) # macro -NV2080_INTR_TYPE_TMR = (0x00000007) # macro -NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008) # macro -NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009) # macro -NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A) # macro -NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B) # macro -NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C) # macro -NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D) # macro -NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E) # macro -NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F) # macro -NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010) # macro -NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE) # macro -class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS._fields_ = [ - ('architecture', ctypes.c_uint32), - ('implementation', ctypes.c_uint32), - ('revision', ctypes.c_uint32), - ('subRevision', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS = struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS -class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS._fields_ = [ - ('engines', ctypes.c_uint32), -] - -NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS -class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS._fields_ = [ - ('manufacturer', ctypes.c_uint32), -] - -NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS = struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS -class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS._fields_ = [ - ('bOwnedByRm', ctypes.c_ubyte), -] - -NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS = struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS -class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(Structure): - pass - -struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY._fields_ = [ - ('nv2080EngineType', ctypes.c_uint32), - ('notificationIntrVector', ctypes.c_uint32), -] - -NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY = struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY -class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('entries', struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY * 256), -] - -NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS = struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS -class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(Structure): - pass - -struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY._fields_ = [ - ('nv2080IntrType', ctypes.c_uint32), - ('pmcIntrMask', ctypes.c_uint32), - ('intrVectorStall', ctypes.c_uint32), - ('intrVectorNonStall', ctypes.c_uint32), -] - -NV2080_CTRL_MC_STATIC_INTR_ENTRY = struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY -class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('entries', struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY * 32), -] - -NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS = struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS -NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401) # macro -NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402) # macro -NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409) # macro -NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024 # macro -NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65 # macro -NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10 # macro -NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7) # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20) # macro -# NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY = 0 : 0 # macro -NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1 # macro -NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0 # macro -# NV2080_CTRL_NOCAT_GET_RESET_COUNTERS = 1 : 1 # macro -NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1 # macro -NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0 # macro -NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b) # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 7 # macro -# NV2080_CTRL_NOCAT_TAG_CLEAR = 0 : 0 # macro -NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1 # macro -NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0 # macro -NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c) # macro -# NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR = 0 : 0 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0 # macro -# NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER = 1 : 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0 # macro -NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS -class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [ - ('pBuffer', ctypes.POINTER(None)), - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_NVD_GET_DUMP_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS -class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS._pack_ = 1 # source:False -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS._fields_ = [ - ('userMinOffset', ctypes.c_int32), - ('userMaxOffset', ctypes.c_int32), - ('factoryMinOffset', ctypes.c_uint32), - ('factoryMaxOffset', ctypes.c_uint32), - ('lastActiveClock', ctypes.c_uint32), - ('lastActiveVolt', ctypes.c_uint32), - ('lastActivePoint', ctypes.c_uint32), - ('kappa', ctypes.c_uint32), -] - -NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS -class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG._pack_ = 1 # source:False -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG._fields_ = [ - ('pstateVer', ctypes.c_uint32), - ('gpcOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), - ('mclkOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), - ('bUserOverclocked', ctypes.c_ubyte), - ('bFactoryOverclocked', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG -class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_GPU_STATE._pack_ = 1 # source:False -struct_NV2080_NOCAT_JOURNAL_GPU_STATE._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('strap', ctypes.c_uint32), - ('deviceId', ctypes.c_uint16), - ('vendorId', ctypes.c_uint16), - ('subsystemVendor', ctypes.c_uint16), - ('subsystemId', ctypes.c_uint16), - ('revision', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('vbiosVersion', ctypes.c_uint32), - ('bOptimus', ctypes.c_ubyte), - ('bMsHybrid', ctypes.c_ubyte), - ('bFullPower', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('vbiosOemVersion', ctypes.c_uint32), - ('memoryType', ctypes.c_uint16), - ('tag', ctypes.c_ubyte * 65), - ('vbiosProject', ctypes.c_ubyte * 65), - ('bInFullchipReset', ctypes.c_ubyte), - ('bInSecBusReset', ctypes.c_ubyte), - ('bInGc6Reset', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), - ('overclockCfg', NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG), -] - -NV2080_NOCAT_JOURNAL_GPU_STATE = struct_NV2080_NOCAT_JOURNAL_GPU_STATE -class struct_NV2080_NOCAT_JOURNAL_ENTRY(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_ENTRY._pack_ = 1 # source:False -struct_NV2080_NOCAT_JOURNAL_ENTRY._fields_ = [ - ('recType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bugcheck', ctypes.c_uint32), - ('tdrBucketId', ctypes.c_uint32), - ('source', ctypes.c_ubyte * 65), - ('PADDING_1', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('errorCode', ctypes.c_uint64), - ('diagBufferLen', ctypes.c_uint32), - ('diagBuffer', ctypes.c_ubyte * 1024), - ('faultingEngine', ctypes.c_ubyte * 65), - ('PADDING_3', ctypes.c_ubyte * 3), - ('mmuFaultType', ctypes.c_uint32), - ('mmuErrorSrc', ctypes.c_uint32), - ('tdrReason', ctypes.c_ubyte * 65), - ('PADDING_4', ctypes.c_ubyte * 7), -] - -NV2080_NOCAT_JOURNAL_ENTRY = struct_NV2080_NOCAT_JOURNAL_ENTRY -class struct_NV2080_NOCAT_JOURNAL_RECORD(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_RECORD._pack_ = 1 # source:False -struct_NV2080_NOCAT_JOURNAL_RECORD._fields_ = [ - ('GPUTag', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('loadAddress', ctypes.c_uint64), - ('timeStamp', ctypes.c_uint64), - ('stateMask', ctypes.c_uint64), - ('nocatGpuState', NV2080_NOCAT_JOURNAL_GPU_STATE), - ('nocatJournalEntry', NV2080_NOCAT_JOURNAL_ENTRY), -] - -NV2080_NOCAT_JOURNAL_RECORD = struct_NV2080_NOCAT_JOURNAL_RECORD -class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('nocatRecordCount', ctypes.c_uint32), - ('nocatOutstandingRecordCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('journalRecords', struct_NV2080_NOCAT_JOURNAL_RECORD * 10), - ('activityCounters', ctypes.c_uint32 * 32), - ('reserved', ctypes.c_ubyte * 65), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS = struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS -class struct_NV2080CtrlNocatJournalDataTdrReason(Structure): - pass - -struct_NV2080CtrlNocatJournalDataTdrReason._pack_ = 1 # source:False -struct_NV2080CtrlNocatJournalDataTdrReason._fields_ = [ - ('flags', ctypes.c_uint32), - ('source', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('errorCode', ctypes.c_uint64), - ('reasonCode', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -NV2080CtrlNocatJournalDataTdrReason = struct_NV2080CtrlNocatJournalDataTdrReason -class struct_NV2080CtrlNocatJournalSetTag(Structure): - pass - -struct_NV2080CtrlNocatJournalSetTag._pack_ = 1 # source:False -struct_NV2080CtrlNocatJournalSetTag._fields_ = [ - ('flags', ctypes.c_uint32), - ('tag', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080CtrlNocatJournalSetTag = struct_NV2080CtrlNocatJournalSetTag -class struct_NV2080CtrlNocatJournalRclog(Structure): - pass - -struct_NV2080CtrlNocatJournalRclog._pack_ = 1 # source:False -struct_NV2080CtrlNocatJournalRclog._fields_ = [ - ('flags', ctypes.c_uint32), - ('rclogSize', ctypes.c_uint32), - ('rmGpuId', ctypes.c_uint32), - ('APIType', ctypes.c_uint32), - ('contextType', ctypes.c_uint32), - ('exceptType', ctypes.c_uint32), - ('processImageName', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080CtrlNocatJournalRclog = struct_NV2080CtrlNocatJournalRclog -class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(Structure): - pass - -class union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(Union): - pass - -union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._pack_ = 1 # source:False -union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._fields_ = [ - ('tdrReason', NV2080CtrlNocatJournalDataTdrReason), - ('tagData', NV2080CtrlNocatJournalSetTag), - ('rclog', NV2080CtrlNocatJournalRclog), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS._fields_ = [ - ('dataType', ctypes.c_uint32), - ('targetRecordType', ctypes.c_uint32), - ('nocatJournalData', union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData), -] - -NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS = struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS -class struct_NV2080CtrlNocatJournalInsertRecord(Structure): - pass - -struct_NV2080CtrlNocatJournalInsertRecord._pack_ = 1 # source:False -struct_NV2080CtrlNocatJournalInsertRecord._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timestamp', ctypes.c_uint64), - ('recType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('bugcheck', ctypes.c_uint32), - ('source', ctypes.c_char * 65), - ('PADDING_2', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('errorCode', ctypes.c_uint64), - ('faultingEngine', ctypes.c_char * 65), - ('PADDING_3', ctypes.c_ubyte * 3), - ('tdrReason', ctypes.c_uint32), - ('diagBufferLen', ctypes.c_uint32), - ('diagBuffer', ctypes.c_ubyte * 1024), - ('PADDING_4', ctypes.c_ubyte * 4), -] - -NV2080CtrlNocatJournalInsertRecord = struct_NV2080CtrlNocatJournalInsertRecord -class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('nocatJournalRecord', NV2080CtrlNocatJournalInsertRecord), - ] - -NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS = struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV2080_CTRL_NVLINK_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV2080_CTRL_NVLINK_CAPS_SUPPORTED = 0 : 0x01 # macro -# NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED = 0 : 0x02 # macro -# NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS = 0 : 0x04 # macro -# NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS = 0 : 0x08 # macro -# NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS = 0 : 0x10 # macro -# NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING = 0 : 0x20 # macro -# NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE = 0 : 0x40 # macro -# NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE = 0 : 0x80 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0 = 1 : 0x01 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1 = 1 : 0x02 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 = 1 : 0x04 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 = 1 : 0x08 # macro -# NV2080_CTRL_NVLINK_CAPS_VALID = 1 : 0x10 # macro -# NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY = 1 : 0x20 # macro -NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2 # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS = 31 : 0 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED = 0 : 0 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY = 1 : 1 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_MAX_LINKS = 32 # macro -NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64 # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00) # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01) # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002) # macro -def NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i): # macro - return (((1<>i) -def NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i): # macro - return NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr,i) -NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14 # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2) # macro -NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3 # macro -NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003) # macro -NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008 # macro -NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010 # macro -def NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i): # macro - return (1<<(i+8)) -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000 # macro -def NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i): # macro - return (1<<(i+17)) -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32 # macro -NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005) # macro -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21 # macro -NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = 21 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35 # macro -NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38 # macro -NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40 # macro -NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50 # macro -NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51 # macro -NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52 # macro -NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53 # macro -NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54 # macro -NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55 # macro -NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56 # macro -NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57 # macro -NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106 # macro -NV2080_CTRL_NVLINK_COUNTERS_MAX = 107 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28 # macro -def NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i): # macro - return ((i)/64) -# def NV2080_CTRL_NVLINK_COUNTER_V2_COUNTER_MASK(i): # macro -# return ((NvU64)1<<((i)%64)) -NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050) # macro -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006) # macro -NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_NVLINK_UNIT_DL = 0x01 # macro -NV2080_CTRL_NVLINK_UNIT_TL = 0x02 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05 # macro -NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06 # macro -NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07 # macro -NV2080_CTRL_NVLINK_UNIT_MINION = 0x08 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE = 31 : 28 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION = 27 : 12 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA = 11 : 8 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT = 7 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT = 15 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP = 16 : 16 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON = 17 : 17 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS = 18 : 18 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX = 3 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR = 4 : 4 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN = 0 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001 # macro -NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081) # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE = 1 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS = 0 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001 # macro -NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008) # macro -NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009) # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62 # macro -NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63 # macro -# def NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts): # macro -# return (!!((supportedCounts)&NVBIT64(count))) -NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a) # macro -NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5 # macro -NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b) # macro -NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c) # macro -NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d) # macro -NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03) # macro -NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e) # macro -NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f) # macro -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011) # macro -NV2080_CTRL_NVLINK_MAX_LANES = 4 # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012) # macro -NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013) # macro -NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014) # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015) # macro -NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016) # macro -NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023) # macro -NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32 # macro -NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028) # macro -NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029) # macro -NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038) # macro -NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039) # macro -NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a) # macro -NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b) # macro -NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b) # macro -NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c) # macro -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c) # macro -NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120 # macro -NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d) # macro -NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d) # macro -NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF) # macro -NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e) # macro -NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e) # macro -NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f) # macro -NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f) # macro -NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040) # macro -NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041) # macro -NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042) # macro -NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043) # macro -NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64 # macro -NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044) # macro -NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45) # macro -NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045) # macro -NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496 # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS = (0x20803047) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY = (0x20803048) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC = (0x20803053) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM = (0x20803054) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC = (0x20803055) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM = (0x20803056) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR = (0x2080305c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID = (0x5c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE = (0x2080305e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID = (0x5e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE = (0x2080305f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID = (0x5f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP = (0x20803061) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID = (0x61) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU = (0x20803062) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID = (0x62) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP = (0x20803064) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID = (0x64) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT = (0x20803065) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID = (0x65) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR = (0x20803066) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID = (0x66) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT = (0x20803068) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT = (0x20803069) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR = (0x2080306a) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID = (0x6a) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS = (0x2080306b) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID = (0x6b) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR = (0x2080306c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID = (0x6c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP = (0x2080306d) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID = (0x6d) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID = (0x2080306e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID = (0x6e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT = (0x2080306f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID = (0x6f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS = (0x20803070) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID = (0x70) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG = (0x20803071) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID = (0x71) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS = (0x20803072) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR = (0x20803073) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074) # macro -NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD = (0x20803075) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP = (0x20803076) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF = (0x20803077) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL = (0x20803078) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM = (0x20803079) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE = (0x2080307a) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID = (0x7a) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM = (0x2080307b) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID = (0x7b) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR = (0x2080307c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID = (0x7c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR = (0x2080307d) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID = (0x7d) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS = (0x2080307e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID = (0x7e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC = (0x2080307f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID = (0x7f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB = (0x20803080) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID = (0x80) # macro -NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083) # macro -NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS = 18 # macro -NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084) # macro -NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84) # macro -NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23 # macro -NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085) # macro -NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086) # macro -NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # macro -NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087) # macro -NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088) # macro -NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089) # macro -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89) # macro -NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a) # macro -NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e) # macro -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f) # macro -NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F) # macro -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('lowestNvlinkVersion', ctypes.c_ubyte), - ('highestNvlinkVersion', ctypes.c_ubyte), - ('lowestNciVersion', ctypes.c_ubyte), - ('highestNciVersion', ctypes.c_ubyte), - ('discoveredLinkMask', ctypes.c_uint32), - ('enabledLinkMask', ctypes.c_uint32), - ('discoveredLinks', ctypes.c_uint64), - ('enabledLinks', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS -class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DEVICE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_DEVICE_INFO._fields_ = [ - ('deviceIdFlags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pciDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('deviceType', ctypes.c_uint64), - ('deviceUUID', ctypes.c_ubyte * 16), - ('fabricRecoveryStatusMask', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_NVLINK_DEVICE_INFO = struct_NV2080_CTRL_NVLINK_DEVICE_INFO -class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('phyType', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('linkState', ctypes.c_uint32), - ('rxSublinkStatus', ctypes.c_ubyte), - ('txSublinkStatus', ctypes.c_ubyte), - ('bLaneReversal', ctypes.c_ubyte), - ('nvlinkVersion', ctypes.c_ubyte), - ('nciVersion', ctypes.c_ubyte), - ('phyVersion', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkCommonClockSpeedKHz', ctypes.c_uint32), - ('nvlinkRefClkSpeedKHz', ctypes.c_uint32), - ('nvlinkCommonClockSpeedMhz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('nvlinkLinkClockMhz', ctypes.c_uint32), - ('nvlinkRefClkType', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), - ('nvlinkLinkDataRateKiBps', ctypes.c_uint32), - ('nvlinkRefClkSpeedMhz', ctypes.c_uint32), - ('connected', ctypes.c_ubyte), - ('loopProperty', ctypes.c_ubyte), - ('remoteDeviceLinkNumber', ctypes.c_ubyte), - ('localDeviceLinkNumber', ctypes.c_ubyte), - ('PADDING_3', ctypes.c_ubyte * 4), - ('remoteLinkSid', ctypes.c_uint64), - ('localLinkSid', ctypes.c_uint64), - ('laneRxdetStatusMask', ctypes.c_uint32), - ('nvlinkMinL1Threshold', ctypes.c_uint32), - ('nvlinkMaxL1Threshold', ctypes.c_uint32), - ('nvlinkL1ThresholdUnits', ctypes.c_uint32), - ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), - ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), -] - -NV2080_CTRL_NVLINK_LINK_STATUS_INFO = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO - -# values for enumeration 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT' -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', - 1: 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', -} -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = 0 -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1 -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS._fields_ = [ - ('enabledLinkMask', ctypes.c_uint32), - ('bSublinkStateInst', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkInfo', struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO * 64), -] - -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS -class struct_NV2080_CTRL_NVLINK_ERR_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_ERR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_ERR_INFO._fields_ = [ - ('TLErrlog', ctypes.c_uint32), - ('TLIntrEn', ctypes.c_uint32), - ('TLCTxErrStatus0', ctypes.c_uint32), - ('TLCTxErrStatus1', ctypes.c_uint32), - ('TLCTxSysErrStatus0', ctypes.c_uint32), - ('TLCRxErrStatus0', ctypes.c_uint32), - ('TLCRxErrStatus1', ctypes.c_uint32), - ('TLCRxSysErrStatus0', ctypes.c_uint32), - ('TLCTxErrLogEn0', ctypes.c_uint32), - ('TLCTxErrLogEn1', ctypes.c_uint32), - ('TLCTxSysErrLogEn0', ctypes.c_uint32), - ('TLCRxErrLogEn0', ctypes.c_uint32), - ('TLCRxErrLogEn1', ctypes.c_uint32), - ('TLCRxSysErrLogEn0', ctypes.c_uint32), - ('MIFTxErrStatus0', ctypes.c_uint32), - ('MIFRxErrStatus0', ctypes.c_uint32), - ('NVLIPTLnkErrStatus0', ctypes.c_uint32), - ('NVLIPTLnkErrLogEn0', ctypes.c_uint32), - ('NVLIPTLnkCtrlLinkStateRequest', ctypes.c_uint32), - ('DLSpeedStatusTx', ctypes.c_uint32), - ('DLSpeedStatusRx', ctypes.c_uint32), - ('NVLDLRxSlsmErrCntl', ctypes.c_uint32), - ('NVLDLTopLinkState', ctypes.c_uint32), - ('NVLDLTopIntr', ctypes.c_uint32), - ('DLStatMN00', ctypes.c_uint32), - ('DLStatUC01', ctypes.c_uint32), - ('MinionNvlinkLinkIntr', ctypes.c_uint32), - ('bExcessErrorDL', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_ERR_INFO = struct_NV2080_CTRL_NVLINK_ERR_INFO -class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO._fields_ = [ - ('NVLIPTErrStatus0', ctypes.c_uint32), - ('NVLIPTErrLogEn0', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_COMMON_ERR_INFO = struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO -class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('linkErrInfo', struct_NV2080_CTRL_NVLINK_ERR_INFO * 64), - ('ioctrlMask', ctypes.c_uint32), - ('commonErrInfo', struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO * 3), - ('ErrInfoFlags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES._fields_ = [ - ('bTx0TlCounterOverflow', ctypes.c_ubyte), - ('bTx1TlCounterOverflow', ctypes.c_ubyte), - ('bRx0TlCounterOverflow', ctypes.c_ubyte), - ('bRx1TlCounterOverflow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), - ('value', ctypes.c_uint64 * 32), -] - -NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkMask', ctypes.c_uint64), - ('counters', struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES * 64), -] - -NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkMask', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES._fields_ = [ - ('overFlow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('value', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES = struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('counterMask', ctypes.c_uint64 * 2), - ('counter', struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES * 28 * 64), -] - -NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('counterMask', ctypes.c_uint64 * 2), -] - -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS -class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bFatalError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS - -# values for enumeration 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE' -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE__enumvalues = { - 1: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', - 2: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', - 3: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', - 4: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', - 5: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', -} -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(Structure): - pass - -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG._fields_ = [ - ('errType', NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE), - ('PADDING_0', ctypes.c_ubyte * 4), - ('errSettings', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG -class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('errCfg', struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG * 64), -] - -NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS -class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO._fields_ = [ - ('txErrInfo', ctypes.c_uint32), - ('packetErrInfo', ctypes.c_uint32), - ('authErrInfo', ctypes.c_uint32), - ('linkStatus', ctypes.c_uint32), - ('errInjectStatus', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO -class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('errInfo', struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO * 64), -] - -NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('numRecoveries', ctypes.c_uint32 * 64), -] - -NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('remoteType', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('supportedCounts', ctypes.c_uint64), - ('fatalErrorCounts', ctypes.c_ubyte * 63), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS -class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(Structure): - pass - -struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE._fields_ = [ - ('errorsPerMinute', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE = struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE -class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('numDailyMaxNonfatalErrorRates', ctypes.c_uint32), - ('dailyMaxNonfatalErrorRates', struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5), - ('numMonthlyMaxNonfatalErrorRates', ctypes.c_uint32), - ('monthlyMaxNonfatalErrorRates', struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5), -] - -NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS._fields_ = [ - ('bEnabled', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS._fields_ = [ - ('linkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('params', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('powerState', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('powerState', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS - -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE' -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE__enumvalues = { - 0: 'TLC_RX_LNK', - 1: 'TLC_TX_SYS', -} -TLC_RX_LNK = 0 -TLC_TX_SYS = 1 -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE' -NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE__enumvalues = { - 0: 'TX_SYS_TX_RSP_STATUS_HW_ERR', - 1: 'TX_SYS_TX_RSP_STATUS_UR_ERR', - 2: 'TX_SYS_TX_RSP_STATUS_PRIV_ERR', -} -TX_SYS_TX_RSP_STATUS_HW_ERR = 0 -TX_SYS_TX_RSP_STATUS_UR_ERR = 1 -TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2 -NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE' -NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE__enumvalues = { - 0: 'RX_LNK_RX_RSP_STATUS_HW_ERR', - 1: 'RX_LNK_RX_RSP_STATUS_UR_ERR', - 2: 'RX_LNK_RX_RSP_STATUS_PRIV_ERR', -} -RX_LNK_RX_RSP_STATUS_HW_ERR = 0 -RX_LNK_RX_RSP_STATUS_UR_ERR = 1 -RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2 -NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = ctypes.c_uint32 # enum -class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('txSysErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE), - ('rxLnkErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE), - ] - -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE = union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE -class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('device', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE), - ('bBroadcast', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('errorType', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE), -] - -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('numLanes', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('figureOfMeritValues', ctypes.c_uint16 * 4), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS._fields_ = [ - ('linkId', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('addr', ctypes.c_uint16), - ('phyConfigData', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS -class struct_NV2080_CTRL_NVLINK_LANE_ERROR(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LANE_ERROR._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_LANE_ERROR._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('eccErrorValue', ctypes.c_uint32), - ('overflowed', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_LANE_ERROR = struct_NV2080_CTRL_NVLINK_LANE_ERROR -class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR._fields_ = [ - ('errorLane', struct_NV2080_CTRL_NVLINK_LANE_ERROR * 4), - ('eccDecFailed', ctypes.c_uint32), - ('eccDecFailedOverflowed', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_LINK_ECC_ERROR = struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR -class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('errorLink', struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR * 64), -] - -NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS -class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES._fields_ = [ - ('value', ctypes.c_uint64 * 4), -] - -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES -class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 6), - ('linkMask', ctypes.c_uint64), - ('counters', struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES * 64), -] - -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS._fields_ = [ - ('bLockPowerMode', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('counterValidMask', ctypes.c_uint32), - ('counterValues', ctypes.c_uint32 * 16), -] - -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('loopbackMode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('passCount', ctypes.c_uint16), - ('failCount', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO = struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO -class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('refreshCount', struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO * 32), -] - -NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS._fields_ = [ - ('bGet', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('addr', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS -class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS._fields_ = [ - ('discoveredLinks', ctypes.c_uint64), - ('connectedLinksMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bridgeSensableLinks', ctypes.c_uint64), - ('bridgedLinks', ctypes.c_uint32), - ('initDisabledLinksMask', ctypes.c_uint32), - ('vbiosDisabledLinkMask', ctypes.c_uint64), - ('initializedLinks', ctypes.c_uint32), - ('bEnableTrainingAtLoad', ctypes.c_ubyte), - ('bEnableSafeModeAtLoad', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS._fields_ = [ - ('initDisabledLinksMask', ctypes.c_uint32), - ('bSkipHwNvlinkDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS = struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND' -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND__enumvalues = { - 0: 'NVLINK_EOM_CONTROL_START_EOM', - 1: 'NVLINK_EOM_CONTROL_END_EOM', - 2: 'NVLINK_EOM_CONTROL_CONFIG_EOM', - 3: 'NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', -} -NVLINK_EOM_CONTROL_START_EOM = 0 -NVLINK_EOM_CONTROL_END_EOM = 1 -NVLINK_EOM_CONTROL_CONFIG_EOM = 2 -NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3 -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(Structure): - pass - -struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT._fields_ = [ - ('upper', ctypes.c_ubyte), - ('middle', ctypes.c_ubyte), - ('lower', ctypes.c_ubyte), - ('composite', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_EOM_MEASUREMENT = struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT -class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS._fields_ = [ - ('cmd', NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND), - ('linkId', ctypes.c_uint32), - ('params', ctypes.c_uint32), - ('measurements', struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT * 4), -] - -NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS = struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS._fields_ = [ - ('data', ctypes.c_ubyte * 5120), - ('dataSize', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS._fields_ = [ - ('l1Threshold', ctypes.c_uint32), - ('l1ExitThreshold', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS._fields_ = [ - ('l1Threshold', ctypes.c_uint32), - ('l1ExitThreshold', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS -class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS._fields_ = [ - ('buffer', ctypes.c_ubyte * 5120), - ('dataSize', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS -class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('bIsGpuDegraded', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS -class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS._fields_ = [ - ('bIsEnoughNvLink', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numBridge', ctypes.c_uint32), - ('bridgePresenceMask', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS = struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS -class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS = struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS -class struct_NV2080_CTRL_NVLINK_PORT_EVENT(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PORT_EVENT._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PORT_EVENT._fields_ = [ - ('portEventType', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('time', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_PORT_EVENT = struct_NV2080_CTRL_NVLINK_PORT_EVENT -class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS._fields_ = [ - ('portEventIndex', ctypes.c_uint64), - ('nextPortEventIndex', ctypes.c_uint64), - ('portEventCount', ctypes.c_uint32), - ('bOverflow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('portEvent', struct_NV2080_CTRL_NVLINK_PORT_EVENT * 64), -] - -NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS -class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS = struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS -class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS._fields_ = [ - ('bReducedNvlinkConfig', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS = struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_DATA(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_DATA._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_DATA._fields_ = [ - ('data', ctypes.c_ubyte * 496), -] - -NV2080_CTRL_NVLINK_PRM_DATA = struct_NV2080_CTRL_NVLINK_PRM_DATA -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('admin_status', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('fd', ctypes.c_ubyte), - ('ps_e', ctypes.c_ubyte), - ('ls_e', ctypes.c_ubyte), - ('ee_ps', ctypes.c_ubyte), - ('ee_ls', ctypes.c_ubyte), - ('ee', ctypes.c_ubyte), - ('ase', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lane_mask', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('local_tx_precoding_admin', ctypes.c_ubyte), - ('local_rx_precoding_admin', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('test_mode', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('fec_override_admin_10g_40g', ctypes.c_ubyte), - ('fec_override_admin_25g', ctypes.c_ubyte), - ('fec_override_admin_50g', ctypes.c_ubyte), - ('fec_override_admin_100g', ctypes.c_ubyte), - ('fec_override_admin_56g', ctypes.c_ubyte), - ('rs_fec_correction_bypass_admin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('fec_override_admin_200g_4x', ctypes.c_uint16), - ('fec_override_admin_400g_8x', ctypes.c_uint16), - ('fec_override_admin_50g_1x', ctypes.c_uint16), - ('fec_override_admin_100g_2x', ctypes.c_uint16), - ('fec_override_admin_400g_4x', ctypes.c_uint16), - ('fec_override_admin_800g_8x', ctypes.c_uint16), - ('fec_override_admin_100g_1x', ctypes.c_uint16), - ('fec_override_admin_200g_2x', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('l1_req_en', ctypes.c_ubyte), - ('l1_fw_req_en', ctypes.c_ubyte), - ('l1_cap_adv', ctypes.c_ubyte), - ('l1_fw_cap_adv', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('hp_queues_bitmap', ctypes.c_uint32), - ('l1_hw_active_time', ctypes.c_uint16), - ('l1_hw_inactive_time', ctypes.c_uint16), - ('qem', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('access_reg_group', ctypes.c_ubyte), - ('feature_group', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('itre', ctypes.c_ubyte), - ('i_e', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('protocol', ctypes.c_ubyte), - ('admin_mtu', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('width', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('m_lane_m', ctypes.c_ubyte), - ('rxtx', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('trap_id', ctypes.c_uint16), - ('action', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('page_select', ctypes.c_ubyte), - ('module_info_ext', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('le', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('sw', ctypes.c_ubyte), - ('dm_ig', ctypes.c_ubyte), - ('p', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('modulation', ctypes.c_ubyte), - ('prbs_mode_admin', ctypes.c_ubyte), - ('prbs_fec_admin', ctypes.c_ubyte), - ('lane_rate_admin', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('grp', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('prio_tc', ctypes.c_ubyte), - ('grp_profile', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('counters_cap', ctypes.c_ubyte), - ('lp_gl', ctypes.c_ubyte), - ('clr', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('phy_test_mode_admin', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('phy_status_admin', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('hist_type', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('c_db', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane_speed', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('tx_policy', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('le', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('sw', ctypes.c_ubyte), - ('dm_ig', ctypes.c_ubyte), - ('p', ctypes.c_ubyte), - ('s', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('modulation', ctypes.c_ubyte), - ('prbs_mode_admin', ctypes.c_ubyte), - ('lane_rate_oper', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('proto_mask', ctypes.c_ubyte), - ('transmit_allowed', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('tx_ready_e', ctypes.c_ubyte), - ('ee_tx_ready', ctypes.c_ubyte), - ('an_disable_admin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('ext_eth_proto_admin', ctypes.c_uint32), - ('eth_proto_admin', ctypes.c_uint32), - ('ib_proto_admin', ctypes.c_uint16), - ('ib_link_width_admin', ctypes.c_uint16), - ('xdr_2x_slow_admin', ctypes.c_ubyte), - ('force_lt_frames_admin', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('admin_status', ctypes.c_ubyte), - ('module', ctypes.c_ubyte), - ('slot_index', ctypes.c_ubyte), - ('rst', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('ee', ctypes.c_ubyte), - ('ase', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('op_mod', ctypes.c_ubyte), - ('apply_im', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('lb_en', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint64 * 2), -] - -NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('segment_type', ctypes.c_uint16), - ('seq_num', ctypes.c_ubyte), - ('vhca_id_valid', ctypes.c_ubyte), - ('inline_dump', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('vhca_id', ctypes.c_uint16), - ('PADDING_2', ctypes.c_ubyte * 2), - ('index1', ctypes.c_uint32), - ('index2', ctypes.c_uint32), - ('num_of_obj2', ctypes.c_uint16), - ('num_of_obj1', ctypes.c_uint16), - ('device_opaque', ctypes.c_uint64), - ('mkey', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('trace_owner', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('trace_mode', ctypes.c_ubyte), - ('log_trace_buffer_size', ctypes.c_ubyte), - ('trace_mkey', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('modify_field_select', ctypes.c_uint16), - ('arm_event', ctypes.c_ubyte), - ('trace_status', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('enable_all', ctypes.c_ubyte), - ('log_delay', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('source_id_bitmask', ctypes.c_uint32 * 8), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('log_level', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('log_bit_mask', ctypes.c_uint32), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('warning_inactive_time', ctypes.c_ubyte), - ('warning_active_time', ctypes.c_ubyte), - ('critical_inactive_time', ctypes.c_ubyte), - ('critical_active_time', ctypes.c_ubyte), - ('cc', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('cnt_64bit', ctypes.c_ubyte), - ('stop_at_ff', ctypes.c_ubyte), - ('counter_rst', ctypes.c_ubyte), - ('counter_en', ctypes.c_ubyte), - ('force_count_mask', ctypes.c_ubyte), - ('cnt_type', ctypes.c_ubyte * 8), - ('cnt_val', ctypes.c_ubyte * 8), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('ib_port', ctypes.c_uint16), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('split_num', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS._fields_ = [ - ('ibGuid', ctypes.c_ubyte * 16), - ('rackGuid', ctypes.c_ubyte * 16), - ('chassisPhysicalSlotNumber', ctypes.c_ubyte), - ('computeSlotIndex', ctypes.c_ubyte), - ('nodeIndex', ctypes.c_ubyte), - ('peerType', ctypes.c_ubyte), - ('moduleId', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(Structure): - pass - -struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD._fields_ = [ - ('pllIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('address', ctypes.c_uint16), -] - -NV2080_CTRL_NVLINK_UPHY_CLN_CMD = struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD -class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('uphyCmd', struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD * 18), - ('data', ctypes.c_uint32 * 18), -] - -NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS._fields_ = [ - ('rbmModesList', ctypes.c_ubyte * 23), - ('rbmTotalModes', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS._fields_ = [ - ('rbmMode', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS._fields_ = [ - ('rbmMode', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), - ] - -NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS - -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY' -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', - 1: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', - 2: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', - 3: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', - 4: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', - 5: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', - 6: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', - 7: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', - 8: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', - 9: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', - 10: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', - 11: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', - 12: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', - 13: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', - 14: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', - 15: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', - 16: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', - 17: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', - 18: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', - 19: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', - 20: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', - 21: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', -} -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('severity', NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY), -] - -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS - -# values for enumeration 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE' -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', - 1: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', - 2: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', - 3: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', - 4: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', -} -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(Structure): - pass - -struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG._fields_ = [ - ('mode', NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE), - ('toggleActiveTime', ctypes.c_ubyte), - ('toggleInactiveTime', ctypes.c_ubyte), - ('bTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV2080_CTRL_NVLINK_L1_FORCE_CONFIG = struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG -class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('config', NV2080_CTRL_NVLINK_L1_FORCE_CONFIG), -] - -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('config', struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG * 32), -] - -NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS -NV_SUBPROC_NAME_MAX_LENGTH = 100 # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CMD = 1 : 0 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CUDA = 4 : 4 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC = 5 : 5 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY = 6 : 6 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001) # macro -NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600 # macro -NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff # macro -NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a) # macro -NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093) # macro -NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93) # macro -NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000) # macro -NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001) # macro -NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b) # macro -NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092) # macro -NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005) # macro -NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D) # macro -NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e) # macro -NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E) # macro -NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f) # macro -NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F) # macro -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72 # macro -NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096) # macro -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002) # macro -NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f) # macro -NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F) # macro -NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32 # macro -NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB) # macro -# NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE = 0 : 0 # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001) # macro -# NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE = 2 : 1 # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002) # macro -NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087) # macro -NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a) # macro -NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d) # macro -NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D) # macro -NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = (0x00000001) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = (0x00000002) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006) # macro -NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007) # macro -NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008) # macro -NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000) # macro -NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000) # macro -NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000) # macro -NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001) # macro -NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001) # macro -NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002) # macro -NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004) # macro -NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008) # macro -NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010) # macro -NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020) # macro -NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040) # macro -NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080) # macro -NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100) # macro -NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200) # macro -NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400) # macro -NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800) # macro -NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000) # macro -NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000) # macro -NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000) # macro -NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000) # macro -NV2080_CTRL_PERF_PSTATES_MAX = (0x00008000) # macro -NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000) # macro -NV2080_CTRL_PERF_PSTATES_ALL = (0xffff) # macro -NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068) # macro -NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68) # macro -class struct_NV2080_CTRL_PERF_BOOST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_BOOST_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_BOOST_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('duration', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_BOOST_PARAMS = struct_NV2080_CTRL_PERF_BOOST_PARAMS -class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS._fields_ = [ - ('bAcquire', ctypes.c_ubyte), -] - -NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS = struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS -class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), - ] - -NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_CLIENT' -NV2080_CTRL_PERF_RATED_TDP_CLIENT__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 1: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 2: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 3: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 4: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 5: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', -} -NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5 -NV2080_CTRL_PERF_RATED_TDP_CLIENT = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_ACTION' -NV2080_CTRL_PERF_RATED_TDP_ACTION__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 1: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 2: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 3: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 4: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', -} -NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4 -NV2080_CTRL_PERF_RATED_TDP_ACTION = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE' -NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE__enumvalues = { - 0: 'NV2080_CTRL_PERF_VPSTATE_RATED_TDP', - 1: 'NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', - 2: 'NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', -} -NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0 -NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1 -NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2 -NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('action', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ] - -NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST = struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST -class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(Structure): - pass - -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm._fields_ = [ - ('clientActiveMask', ctypes.c_uint32), - ('bRegkeyLimitRatedTdp', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS._fields_ = [ - ('rm', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm), - ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('outputVPstate', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ('inputs', NV2080_CTRL_PERF_RATED_TDP_ACTION * 5), - ('vPstateTypes', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE * 5), -] - -NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS -class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT), - ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ] - -NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS -NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS -NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS -class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE._fields_ = [ - ('util', ctypes.c_uint32), - ('vgpuScale', ctypes.c_uint32), - ('procId', ctypes.c_uint32), - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pOsPidInfo', ctypes.c_uint64), -] - -NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE -class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('base', NV2080_CTRL_GPUMON_SAMPLE), - ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvjpg', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvofa', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ] - -NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE -NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE = ctypes.sizeof ( NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE ) * 72 # macro (from list) -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM = struct_NV2080_CTRL_GPUMON_SAMPLES -class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bufSize', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('tracker', ctypes.c_uint32), - ('samples', struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE * 72), -] - -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS -class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS._fields_ = [ - ('prevPstate', ctypes.c_uint32), - ('action', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS = struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS -class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS._fields_ = [ - ('bGpuIsIdle', ctypes.c_ubyte), - ('bRestoreToMax', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('idleTimeUs', ctypes.c_uint64), - ('busyTimeUs', ctypes.c_uint64), -] - -NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS = struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS -class struct_NV2080_CTRL_PERF_GET_CLK_INFO(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_CLK_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_CLK_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('currentFreq', ctypes.c_uint32), - ('defaultFreq', ctypes.c_uint32), - ('minFreq', ctypes.c_uint32), - ('maxFreq', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_GET_CLK_INFO = struct_NV2080_CTRL_PERF_GET_CLK_INFO -class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS._fields_ = [ - ('level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('perfGetClkInfoList', ctypes.POINTER(None)), - ('perfGetClkInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS -class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS._fields_ = [ - ('level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('perfGetClkInfoList', struct_NV2080_CTRL_PERF_GET_CLK_INFO * 32), - ('perfGetClkInfoListSize', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_PERF_VID_ENG' -NV2080_CTRL_CMD_PERF_VID_ENG__enumvalues = { - 1: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 2: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 3: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 4: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', -} -NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1 -NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2 -NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3 -NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4 -NV2080_CTRL_CMD_PERF_VID_ENG = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS._fields_ = [ - ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG), - ('clkPercentBusy', ctypes.c_uint32), - ('samplingPeriodUs', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS -class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), - ] - -NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._fields_ = [ - ('videoEvent', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS = struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS -NV2080_CTRL_PERF_PSTATES_ID = ctypes.c_uint32 -class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS._fields_ = [ - ('currPstate', ctypes.c_uint32), -] - -NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1 # macro -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2 # macro -NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609) # macro -class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS._fields_ = [ - ('moduleId', ctypes.c_uint32), - ('nvswitchSupport', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_PMGR_MODULE_INFO_PARAMS = struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS -NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d) # macro -NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e) # macro -NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE) # macro - -# values for enumeration 'NV2080_CTRL_GC6_FLAVOR_ID' -NV2080_CTRL_GC6_FLAVOR_ID__enumvalues = { - 0: 'NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', - 1: 'NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', - 4: 'NV2080_CTRL_GC6_FLAVOR_ID_MAX', -} -NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0 -NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1 -NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4 -NV2080_CTRL_GC6_FLAVOR_ID = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(Structure): - pass - -struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params._pack_ = 1 # source:False -struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params._fields_ = [ - ('bIsRTD3Transition', ctypes.c_ubyte), - ('bIsRTD3CoreRailPowerCut', ctypes.c_ubyte), - ('bSkipPstateSanity', ctypes.c_ubyte), -] - -struct_NV2080_CTRL_GC6_ENTRY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GC6_ENTRY_PARAMS._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('stepMask', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params), - ('PADDING_0', ctypes.c_ubyte), -] - -NV2080_CTRL_GC6_ENTRY_PARAMS = struct_NV2080_CTRL_GC6_ENTRY_PARAMS -class struct_NV2080_CTRL_GC6_EXIT_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(Structure): - pass - -struct_NV2080_CTRL_GC6_EXIT_PARAMS_params._pack_ = 1 # source:False -struct_NV2080_CTRL_GC6_EXIT_PARAMS_params._fields_ = [ - ('bIsGpuSelfWake', ctypes.c_ubyte), - ('bIsRTD3Transition', ctypes.c_ubyte), - ('bIsRTD3HotTransition', ctypes.c_ubyte), -] - -struct_NV2080_CTRL_GC6_EXIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GC6_EXIT_PARAMS._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('params', struct_NV2080_CTRL_GC6_EXIT_PARAMS_params), - ('PADDING_0', ctypes.c_ubyte), -] - -NV2080_CTRL_GC6_EXIT_PARAMS = struct_NV2080_CTRL_GC6_EXIT_PARAMS - -# values for enumeration 'NV2080_CTRL_GC6_STEP_ID' -NV2080_CTRL_GC6_STEP_ID__enumvalues = { - 0: 'NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', - 1: 'NV2080_CTRL_GC6_STEP_ID_GPU_OFF', - 2: 'NV2080_CTRL_GC6_STEP_ID_MAX', -} -NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0 -NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1 -NV2080_CTRL_GC6_STEP_ID_MAX = 2 -NV2080_CTRL_GC6_STEP_ID = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GC6_FLAVOR_INFO(Structure): - pass - -struct_NV2080_CTRL_GC6_FLAVOR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GC6_FLAVOR_INFO._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('stepMask', ctypes.c_uint32), -] - -NV2080_CTRL_GC6_FLAVOR_INFO = struct_NV2080_CTRL_GC6_FLAVOR_INFO -NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204) # macro -NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205) # macro -NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000) # macro -NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206) # macro -NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213) # macro -NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004) # macro -NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a) # macro -NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b) # macro -NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c) # macro -NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d) # macro -NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e) # macro -NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001) # macro -NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001) # macro -NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210) # macro -NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211) # macro -NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212) # macro -NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000) # macro -NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001) # macro -NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000) # macro -NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001) # macro -class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('virtAddress', ctypes.c_uint64), - ('bufferPtr', ctypes.POINTER(None)), - ('bufferSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS = struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS -class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS._fields_ = [ - ('errorCount', ctypes.c_uint32), -] - -NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS -class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS._fields_ = [ - ('whichBuffer', ctypes.c_uint32), - ('outputRecordSize', ctypes.c_uint32), - ('recordBuffer', ctypes.c_ubyte * 8192), -] - -NV2080_CTRL_RC_GET_ERROR_V2_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS -class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS._fields_ = [ - ('watchdogStatusFlags', ctypes.c_uint32), -] - -NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS = struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS -class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS._fields_ = [ - ('rcEnable', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS -NV2080_CTRL_SET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS -NV2080_CTRL_GET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS -class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('status', ctypes.c_int32), -] - -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS = struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS -class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_RC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_RC_INFO_PARAMS._fields_ = [ - ('rcMode', ctypes.c_uint32), - ('rcBreak', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS -NV2080_CTRL_SET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS -NV2080_CTRL_GET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS -RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1) # macro -RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2) # macro -RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3) # macro -RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4) # macro -RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5) # macro -RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6) # macro -RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF) # macro -SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400 # macro -RSVD7_SIZE = 16 # macro -RSVD8_SIZE = 2 # macro -CE_FIPS_SELF_TEST_DATA_SIZE = 16 # macro -CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16 # macro -CE_FIPS_SELF_TEST_IV_SIZE = 12 # macro -RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1) # macro -RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2) # macro -RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3) # macro -RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4) # macro -RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5) # macro -RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6) # macro -RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF) # macro -NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9) # macro -NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9) # macro -NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada) # macro -NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA) # macro -class struct_RM_GSP_SPDM_CMD_CC_INIT(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_INIT._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_CC_INIT._fields_ = [ - ('cmdType', ctypes.c_ubyte), -] - -RM_GSP_SPDM_CMD_CC_INIT = struct_RM_GSP_SPDM_CMD_CC_INIT -PRM_GSP_SPDM_CMD_CC_INIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT) -class struct_RM_GSP_SPDM_CMD_CC_DEINIT(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_DEINIT._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_CC_DEINIT._fields_ = [ - ('cmdType', ctypes.c_ubyte), -] - -RM_GSP_SPDM_CMD_CC_DEINIT = struct_RM_GSP_SPDM_CMD_CC_DEINIT -PRM_GSP_SPDM_CMD_CC_DEINIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_DEINIT) -class struct_RM_GSP_SPDM_CMD_CC_CTRL(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_CTRL._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_CC_CTRL._fields_ = [ - ('cmdType', ctypes.c_ubyte), -] - -RM_GSP_SPDM_CMD_CC_CTRL = struct_RM_GSP_SPDM_CMD_CC_CTRL -PRM_GSP_SPDM_CMD_CC_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_CTRL) -class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rsvd0', ctypes.c_uint32 * 2), - ('rsvd1', ctypes.c_uint32), - ('rsvd2', ctypes.c_char * 9), - ('rsvd3', ctypes.c_char * 5), - ('rsvd4', ctypes.c_char * 5), - ('rsvd5', ctypes.c_char * 5), - ('rsvd6', ctypes.c_char * 2), - ('rsvd7', ctypes.c_char * 16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('rsvd8', ctypes.c_uint32 * 2), -] - -RM_GSP_SPDM_CMD_CC_INIT_RM_DATA = struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA -PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA) -class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('bEnable', ctypes.c_ubyte), -] - -RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL -PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL) -class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(Structure): - pass - -class struct_CC_KMB(Structure): - pass - -class struct_CC_AES_CRYPTOBUNDLE(Structure): - pass - -struct_CC_AES_CRYPTOBUNDLE._pack_ = 1 # source:False -struct_CC_AES_CRYPTOBUNDLE._fields_ = [ - ('iv', ctypes.c_uint32 * 3), - ('key', ctypes.c_uint32 * 8), - ('ivMask', ctypes.c_uint32 * 3), -] - -class union_CC_KMB_0(Union): - pass - -class struct_CC_HMAC_CRYPTOBUNDLE(Structure): - pass - -struct_CC_HMAC_CRYPTOBUNDLE._pack_ = 1 # source:False -struct_CC_HMAC_CRYPTOBUNDLE._fields_ = [ - ('nonce', ctypes.c_uint32 * 8), - ('key', ctypes.c_uint32 * 8), -] - -union_CC_KMB_0._pack_ = 1 # source:False -union_CC_KMB_0._fields_ = [ - ('hmacBundle', struct_CC_HMAC_CRYPTOBUNDLE), - ('decryptBundle', struct_CC_AES_CRYPTOBUNDLE), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_CC_KMB._pack_ = 1 # source:False -struct_CC_KMB._anonymous_ = ('_0',) -struct_CC_KMB._fields_ = [ - ('encryptBundle', struct_CC_AES_CRYPTOBUNDLE), - ('_0', union_CC_KMB_0), - ('bIsWorkLaunch', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST._pack_ = 1 # source:False -struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('isEnc', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('kmb', struct_CC_KMB), - ('text', ctypes.c_ubyte * 16), - ('authTag', ctypes.c_ubyte * 16), -] - -RM_GSP_SPDM_CMD_FIPS_SELFTEST = struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST -PRM_GSP_SPDM_CMD_FIPS_SELFTEST = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST) -class union_RM_GSP_SPDM_CMD(Union): - pass - -union_RM_GSP_SPDM_CMD._pack_ = 1 # source:False -union_RM_GSP_SPDM_CMD._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('ccInit', RM_GSP_SPDM_CMD_CC_INIT), - ('ccDeinit', RM_GSP_SPDM_CMD_CC_DEINIT), - ('ccCtrl', RM_GSP_SPDM_CMD_CC_CTRL), - ('rmDataInitCmd', RM_GSP_SPDM_CMD_CC_INIT_RM_DATA), - ('ccHeartbeatCtrl', RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL), - ('ccFipsTest', RM_GSP_SPDM_CMD_FIPS_SELFTEST), -] - -RM_GSP_SPDM_CMD = union_RM_GSP_SPDM_CMD -PRM_GSP_SPDM_CMD = ctypes.POINTER(union_RM_GSP_SPDM_CMD) -class struct_RM_GSP_SPDM_MSG(Structure): - pass - -struct_RM_GSP_SPDM_MSG._pack_ = 1 # source:False -struct_RM_GSP_SPDM_MSG._fields_ = [ - ('msgType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('status', ctypes.c_uint32), - ('rsvd1', ctypes.c_uint32), - ('rsvd2', ctypes.c_uint32), - ('rsvd3', ctypes.c_uint32), - ('rsvd4', ctypes.c_uint32), - ('rsvd5', ctypes.c_uint32), -] - -RM_GSP_SPDM_MSG = struct_RM_GSP_SPDM_MSG -PRM_GSP_SPDM_MSG = ctypes.POINTER(struct_RM_GSP_SPDM_MSG) -class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS._fields_ = [ - ('index', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('cmd', RM_GSP_SPDM_CMD), - ('msg', RM_GSP_SPDM_MSG), -] - -NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS -class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS._fields_ = [ - ('transcript', ctypes.c_ubyte * 9216), - ('transcriptSize', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS -NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401) # macro -NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -# NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME = 0 : 0 # macro -NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000) # macro -NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001) # macro -NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402) # macro -NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403) # macro -NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404) # macro -NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406) # macro -NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16 # macro -NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -# NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE = 3 : 0 # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004) # macro -# NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR = 7 : 4 # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001) # macro -NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407) # macro -NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7) # macro -class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS._fields_ = [ - ('time_nsec', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS -class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS._fields_ = [ - ('time_nsec', ctypes.c_uint64), -] - -NV2080_CTRL_TIMER_GET_TIME_PARAMS = struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS -class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS._fields_ = [ - ('tmr_offset', ctypes.c_uint32), -] - -NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS = struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS -class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE._pack_ = 1 # source:False -struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE._fields_ = [ - ('cpuTime', ctypes.c_uint64), - ('gpuTime', ctypes.c_uint64), -] - -NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE = struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE -class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS._fields_ = [ - ('cpuClkId', ctypes.c_ubyte), - ('sampleCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('samples', struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE * 16), -] - -NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS = struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS -class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS._fields_ = [ - ('bSetMaxFreq', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS -NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002) # macro -NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002) # macro -NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03) # macro -NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04) # macro -NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05) # macro -NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06) # macro -NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07) # macro -NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08) # macro -NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), -] - -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS = struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS -class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), -] - -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS = struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS -class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS._fields_ = [ - ('bEnter', ctypes.c_ubyte), -] - -NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS = struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS -class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS._fields_ = [ - ('hNotifierResource', ctypes.c_uint32), - ('notifyDataSize', ctypes.c_uint32), - ('hNotifyDataMemory', ctypes.c_uint32), - ('perfmonIdCount', ctypes.c_uint32), - ('snapshotBufferSize', ctypes.c_uint32), - ('hSnapshotMemory', ctypes.c_uint32), -] - -NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS = struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS -class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS._fields_ = [ - ('bVidmemPersistent', ctypes.c_ubyte), -] - -NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS -class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS._fields_ = [ - ('bUpdateTGP', ctypes.c_ubyte), -] - -NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001) # macro -NV2080_CTRL_MAX_VMMU_SEGMENTS = 384 # macro -NV2080_GPU_MAX_ENGINES = 0x54 # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8 # macro -NV2080_CTRL_MAX_GPC_COUNT = 32 # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d) # macro -NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE) # macro -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [ - ('dbdf', ctypes.c_uint32), - ('gfid', ctypes.c_uint32), - ('vgpuType', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('numPluginChannels', ctypes.c_uint32), - ('chidOffset', ctypes.c_uint32 * 84), - ('bDisableDefaultSmcExecPartRestore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numGuestFbSegments', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('guestFbPhysAddrList', ctypes.c_uint64 * 384), - ('guestFbLengthList', ctypes.c_uint64 * 384), - ('pluginHeapMemoryPhysAddr', ctypes.c_uint64), - ('pluginHeapMemoryLength', ctypes.c_uint64), - ('ctrlBuffOffset', ctypes.c_uint64), - ('initTaskLogBuffOffset', ctypes.c_uint64), - ('initTaskLogBuffSize', ctypes.c_uint64), - ('vgpuTaskLogBuffOffset', ctypes.c_uint64), - ('vgpuTaskLogBuffSize', ctypes.c_uint64), - ('kernelLogBuffOffset', ctypes.c_uint64), - ('kernelLogBuffSize', ctypes.c_uint64), - ('migRmHeapMemoryPhysAddr', ctypes.c_uint64), - ('migRmHeapMemoryLength', ctypes.c_uint64), - ('bDeviceProfilingEnabled', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(Structure): - pass - -class struct_NVA081_CTRL_VGPU_INFO(Structure): - pass - -struct_NVA081_CTRL_VGPU_INFO._pack_ = 1 # source:False -struct_NVA081_CTRL_VGPU_INFO._fields_ = [ - ('vgpuType', ctypes.c_uint32), - ('vgpuName', ctypes.c_ubyte * 32), - ('vgpuClass', ctypes.c_ubyte * 32), - ('vgpuSignature', ctypes.c_ubyte * 128), - ('license', ctypes.c_ubyte * 128), - ('maxInstance', ctypes.c_uint32), - ('numHeads', ctypes.c_uint32), - ('maxResolutionX', ctypes.c_uint32), - ('maxResolutionY', ctypes.c_uint32), - ('maxPixels', ctypes.c_uint32), - ('frlConfig', ctypes.c_uint32), - ('cudaEnabled', ctypes.c_uint32), - ('eccSupported', ctypes.c_uint32), - ('gpuInstanceSize', ctypes.c_uint32), - ('multiVgpuSupported', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vdevId', ctypes.c_uint64), - ('pdevId', ctypes.c_uint64), - ('profileSize', ctypes.c_uint64), - ('fbLength', ctypes.c_uint64), - ('gspHeapSize', ctypes.c_uint64), - ('fbReservation', ctypes.c_uint64), - ('mappableVideoSize', ctypes.c_uint64), - ('encoderCapacity', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('bar1Length', ctypes.c_uint64), - ('frlEnable', ctypes.c_uint32), - ('adapterName', ctypes.c_ubyte * 64), - ('adapterName_Unicode', ctypes.c_uint16 * 64), - ('shortGpuNameString', ctypes.c_ubyte * 64), - ('licensedProductName', ctypes.c_ubyte * 128), - ('vgpuExtraParams', ctypes.c_uint32 * 1024), - ('ftraceEnable', ctypes.c_uint32), - ('gpuDirectSupported', ctypes.c_uint32), - ('nvlinkP2PSupported', ctypes.c_uint32), - ('multiVgpuExclusive', ctypes.c_uint32), - ('exclusiveType', ctypes.c_uint32), - ('exclusiveSize', ctypes.c_uint32), - ('gpuInstanceProfileId', ctypes.c_uint32), - ('placementSize', ctypes.c_uint32), - ('homogeneousPlacementCount', ctypes.c_uint32), - ('homogeneousPlacementIds', ctypes.c_uint32 * 32), - ('heterogeneousPlacementCount', ctypes.c_uint32), - ('heterogeneousPlacementIds', ctypes.c_uint32 * 32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS._fields_ = [ - ('discardVgpuTypes', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vgpuInfoCount', ctypes.c_uint32), - ('vgpuInfo', struct_NVA081_CTRL_VGPU_INFO * 64), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS -class struct_NV2080_GUEST_VM_INFO(Structure): - pass - - -# values for enumeration 'GUEST_VM_INFO_STATE' -GUEST_VM_INFO_STATE__enumvalues = { - 0: 'GUEST_VM_INFO_STATE_UNINITIALIZED', - 1: 'GUEST_VM_INFO_STATE_INITIALIZED', -} -GUEST_VM_INFO_STATE_UNINITIALIZED = 0 -GUEST_VM_INFO_STATE_INITIALIZED = 1 -GUEST_VM_INFO_STATE = ctypes.c_uint32 # enum -struct_NV2080_GUEST_VM_INFO._pack_ = 1 # source:False -struct_NV2080_GUEST_VM_INFO._fields_ = [ - ('vmPid', ctypes.c_uint32), - ('guestOs', ctypes.c_uint32), - ('migrationProhibited', ctypes.c_uint32), - ('guestNegotiatedVgpuVersion', ctypes.c_uint32), - ('frameRateLimit', ctypes.c_uint32), - ('licensed', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('licenseState', ctypes.c_uint32), - ('licenseExpiryTimestamp', ctypes.c_uint32), - ('licenseExpiryStatus', ctypes.c_ubyte), - ('guestDriverVersion', ctypes.c_ubyte * 32), - ('guestDriverBranch', ctypes.c_ubyte * 32), - ('PADDING_1', ctypes.c_ubyte * 3), - ('guestVmInfoState', GUEST_VM_INFO_STATE), -] - -NV2080_GUEST_VM_INFO = struct_NV2080_GUEST_VM_INFO -class struct_NV2080_HOST_VGPU_DEVICE(Structure): - pass - -struct_NV2080_HOST_VGPU_DEVICE._pack_ = 1 # source:False -struct_NV2080_HOST_VGPU_DEVICE._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuPciId', ctypes.c_uint64), - ('vgpuDeviceInstanceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('fbUsed', ctypes.c_uint64), - ('encoderCapacity', ctypes.c_uint32), - ('eccState', ctypes.c_uint32), - ('bDriverLoaded', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), -] - -NV2080_HOST_VGPU_DEVICE = struct_NV2080_HOST_VGPU_DEVICE -class struct_NV2080_VGPU_GUEST(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('guestVmInfo', NV2080_GUEST_VM_INFO), - ('vgpuDevice', NV2080_HOST_VGPU_DEVICE), - ] - -NV2080_VGPU_GUEST = struct_NV2080_VGPU_GUEST -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS._fields_ = [ - ('numVgpu', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuGuest', struct_NV2080_VGPU_GUEST * 32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS -class struct_NV2080_VGPU_FB_USAGE(Structure): - pass - -struct_NV2080_VGPU_FB_USAGE._pack_ = 1 # source:False -struct_NV2080_VGPU_FB_USAGE._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbUsed', ctypes.c_uint64), -] - -NV2080_VGPU_FB_USAGE = struct_NV2080_VGPU_FB_USAGE -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS._fields_ = [ - ('vgpuCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuFbUsage', struct_NV2080_VGPU_FB_USAGE * 32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('encoderCapacity', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS._fields_ = [ - ('pgpuString', ctypes.c_ubyte * 256), - ('pgpuStringSize', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS._fields_ = [ - ('bIsMigrationSupported', ctypes.c_ubyte), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS._fields_ = [ - ('bSupportHeterogeneousTimeSlicedVgpuTypes', ctypes.c_ubyte), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS._fields_ = [ - ('bFlrDisabled', ctypes.c_ubyte), -] - -NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS = struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), -] - -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS -# def NV83DE_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x83DE,NV83DE_CTRL_##cat,idx) -NV83DE_CTRL_RESERVED = (0x00) # macro -NV83DE_CTRL_GR = (0x01) # macro -NV83DE_CTRL_FIFO = (0x02) # macro -NV83DE_CTRL_DEBUG = (0x03) # macro -NV83DE_CTRL_INTERNAL = (0x04) # macro -NV83DE_CTRL_CMD_NULL = (0x83de0000) # macro -NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301) # macro -NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307) # macro -NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308) # macro -NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF) # macro -NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b) # macro -NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB) # macro -NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c) # macro -NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100 # macro -NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC) # macro -NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f) # macro -NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF) # macro -NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310) # macro -NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1 # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1 # macro -NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315) # macro -NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15) # macro -NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316) # macro -NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17) # macro -NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318) # macro -NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319) # macro -NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a) # macro -NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b) # macro -MAX_ACCESS_OPS = 64 # macro -NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c) # macro -MAX_GET_MAPPINGS_OPS = 64 # macro -NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d) # macro -NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100 # macro -NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f) # macro -NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320) # macro -NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322) # macro -# NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST = ((NvU32)~0) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24) # macro -NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325) # macro -NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25) # macro -NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326) # macro -NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327) # macro -MAX_ACCESS_MEMORY_OPS = 150 # macro -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4 # macro -NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328) # macro -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28) # macro -NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329) # macro -NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a) # macro -NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b) # macro -NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002) # macro -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS._fields_ = [ - ('exceptionMask', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS -class struct_NV83DE_SM_ERROR_STATE_REGISTERS(Structure): - pass - -struct_NV83DE_SM_ERROR_STATE_REGISTERS._pack_ = 1 # source:False -struct_NV83DE_SM_ERROR_STATE_REGISTERS._fields_ = [ - ('hwwGlobalEsr', ctypes.c_uint32), - ('hwwWarpEsr', ctypes.c_uint32), - ('hwwWarpEsrPc', ctypes.c_uint32), - ('hwwGlobalEsrReportMask', ctypes.c_uint32), - ('hwwWarpEsrReportMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hwwEsrAddr', ctypes.c_uint64), - ('hwwWarpEsrPc64', ctypes.c_uint64), - ('hwwCgaEsr', ctypes.c_uint32), - ('hwwCgaEsrReportMask', ctypes.c_uint32), -] - -NV83DE_SM_ERROR_STATE_REGISTERS = struct_NV83DE_SM_ERROR_STATE_REGISTERS -class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), - ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS), -] - -NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS -class struct_NV83DE_MMU_FAULT_INFO(Structure): - pass - -struct_NV83DE_MMU_FAULT_INFO._pack_ = 1 # source:False -struct_NV83DE_MMU_FAULT_INFO._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('faultInfo', ctypes.c_uint32), -] - -NV83DE_MMU_FAULT_INFO = struct_NV83DE_MMU_FAULT_INFO -class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToRead', ctypes.c_uint32), - ('smErrorStateArray', struct_NV83DE_SM_ERROR_STATE_REGISTERS * 100), - ('mmuFaultInfo', ctypes.c_uint32), - ('mmuFault', NV83DE_MMU_FAULT_INFO), - ('startingSM', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS -class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS -class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToClear', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS -class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS._fields_ = [ - ('waitForEvent', ctypes.c_uint32), - ('hResidentChannel', ctypes.c_uint32), -] - -NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS._fields_ = [ - ('stopTriggerType', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS._fields_ = [ - ('singleStepHandling', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS -class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('buffer', ctypes.POINTER(None)), -] - -NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS -class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('buffer', ctypes.POINTER(None)), -] - -NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS -NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('hSubdevice', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS -class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_OP._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_ACCESS_OP._fields_ = [ - ('gpuVA', ctypes.c_uint64), - ('pCpuVA', ctypes.POINTER(None)), - ('size', ctypes.c_uint32), - ('valid', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_ACCESS_OP = struct_NV83DE_CTRL_DEBUG_ACCESS_OP -class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS._fields_ = [ - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('opsBuffer', struct_NV83DE_CTRL_DEBUG_ACCESS_OP * 64), -] - -NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS = struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS -class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP._fields_ = [ - ('gpuVA', ctypes.c_uint64), - ('size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP -class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS._fields_ = [ - ('vaLo', ctypes.c_uint64), - ('vaHi', ctypes.c_uint64), - ('count', ctypes.c_uint32), - ('hasMore', ctypes.c_uint32), - ('opsBuffer', struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP * 64), -] - -NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS -class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS._fields_ = [ - ('bNonTransactional', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('regOpCount', ctypes.c_uint32), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 100), -] - -NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bSingleStep', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bStopTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bRunTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bSkipIdleWarpDetect', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS -class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS._fields_ = [ - ('bInTrapMode', ctypes.c_ubyte), - ('bCrsFlushDone', ctypes.c_ubyte), - ('bRunTriggerInProgress', ctypes.c_ubyte), - ('bComputeContext', ctypes.c_ubyte), - ('bLockedDown', ctypes.c_ubyte), -] - -NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS = struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS -class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('smDebuggerStatus', NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS -class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('memOffset', ctypes.c_uint64), - ('dataOffset', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY -class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [ - ('pData', ctypes.POINTER(None)), - ('dataLength', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('entries', struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY * 150), -] - -NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS -class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY._fields_ = [ - ('faultAddress', ctypes.c_uint64), - ('faultType', ctypes.c_uint32), - ('accessType', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY -class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS._fields_ = [ - ('mmuFaultInfoList', struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY * 4), - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS._fields_ = [ - ('bDropDeferredRc', ctypes.c_ubyte), -] - -NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), -] - -NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS -# def NVC36F_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xC36F,NVC36F_CTRL_##cat,idx) -NVC36F_CTRL_RESERVED = (0x00) # macro -NVC36F_CTRL_GPFIFO = (0x01) # macro -NVC36F_CTRL_EVENT = (0x02) # macro -NVC36F_CTRL_INTERNAL = (0x03) # macro -NVC36F_CTRL_CMD_NULL = (0xc36f0000) # macro -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108) # macro -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8) # macro -NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2 # macro -NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109) # macro -NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9) # macro -NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a) # macro -NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA) # macro -NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION = (0xc36f0205) # macro -NVC36F_CTRL_CMD_EVENT_SET_TRIGGER = (0xc36f0206) # macro -NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301) # macro -NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(Structure): - pass - -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._fields_ = [ - ('workSubmitToken', ctypes.c_uint32), -] - -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS -class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(Structure): - pass - -struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._fields_ = [ - ('bar2Addr', ctypes.c_uint64 * 2), -] - -NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS -class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(Structure): - pass - -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._fields_ = [ - ('index', ctypes.c_uint32), -] - -NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS -NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS -# def NV_CONF_COMPUTE_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xCB33,NVCB33_CTRL_##cat,idx) -NVCB33_CTRL_RESERVED = (0x00) # macro -NVCB33_CTRL_CONF_COMPUTE = (0x01) # macro -NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000) # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101) # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2 # macro -NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0 # macro -NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1 # macro -NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1 # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104) # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109) # macro -NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000 # macro -NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400 # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a) # macro -NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000 # macro -NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000 # macro -NV_CONF_COMPUTE_NONCE_SIZE = 0x20 # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._fields_ = [ - ('cpuCapability', ctypes.c_ubyte), - ('gpusCapability', ctypes.c_ubyte), - ('environment', ctypes.c_ubyte), - ('ccFeature', ctypes.c_ubyte), - ('devToolsMode', ctypes.c_ubyte), - ('multiGpuMode', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('protectedMemSizeInKb', ctypes.c_uint64), - ('unprotectedMemSizeInKb', ctypes.c_uint64), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('protectedMemSizeInKb', ctypes.c_uint64), - ('unprotectedMemSizeInKb', ctypes.c_uint64), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('numSupportedSec2CCSecureChannels', ctypes.c_uint32), - ('numSupportedCeCCSecureChannels', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('certChain', ctypes.c_ubyte * 4096), - ('certChainSize', ctypes.c_uint32), - ('attestationCertChain', ctypes.c_ubyte * 5120), - ('attestationCertChainSize', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('nonce', ctypes.c_ubyte * 32), - ('attestationReport', ctypes.c_ubyte * 8192), - ('attestationReportSize', ctypes.c_uint32), - ('isCecAttestationReportPresent', ctypes.c_ubyte), - ('cecAttestationReport', ctypes.c_ubyte * 4096), - ('PADDING_0', ctypes.c_ubyte * 3), - ('cecAttestationReportSize', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('maxSec2Channels', ctypes.c_uint32), - ('maxCeChannels', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('keyRotationState', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS -# def NVA06C_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xA06C,NVA06C_CTRL_##cat,idx) -NVA06C_CTRL_RESERVED = (0x00) # macro -NVA06C_CTRL_GPFIFO = (0x01) # macro -NVA06C_CTRL_INTERNAL = (0x02) # macro -NVA06C_CTRL_CMD_NULL = (0xa06c0000) # macro -NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101) # macro -NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -NVA06C_CTRL_CMD_BIND = (0xa06c0102) # macro -NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2) # macro -NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103) # macro -NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3) # macro -NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104) # macro -NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4) # macro -NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105) # macro -NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5) # macro -NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000) # macro -NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106) # macro -NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002) # macro -NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7) # macro -NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108) # macro -NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8) # macro -NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109) # macro -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9) # macro -NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a) # macro -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (0x2) # macro -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa) # macro -NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110) # macro -NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10) # macro -NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201) # macro -NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202) # macro -NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(Structure): - pass - -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._pack_ = 1 # source:False -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), - ('bSkipSubmit', ctypes.c_ubyte), -] - -NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS -class struct_NVA06F_CTRL_BIND_PARAMS(Structure): - pass - -struct_NVA06F_CTRL_BIND_PARAMS._pack_ = 1 # source:False -struct_NVA06F_CTRL_BIND_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), -] - -NVA06C_CTRL_BIND_PARAMS = struct_NVA06F_CTRL_BIND_PARAMS -class struct_NVA06C_CTRL_TIMESLICE_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_TIMESLICE_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_TIMESLICE_PARAMS._fields_ = [ - ('timesliceUs', ctypes.c_uint64), -] - -NVA06C_CTRL_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -NVA06C_CTRL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -NVA06C_CTRL_GET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -class struct_NVA06C_CTRL_PREEMPT_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_PREEMPT_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_PREEMPT_PARAMS._fields_ = [ - ('bWait', ctypes.c_ubyte), - ('bManualTimeout', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('timeoutUs', ctypes.c_uint32), -] - -NVA06C_CTRL_PREEMPT_PARAMS = struct_NVA06C_CTRL_PREEMPT_PARAMS -class struct_NVA06C_CTRL_GET_INFO_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_GET_INFO_PARAMS._fields_ = [ - ('tsgID', ctypes.c_uint32), -] - -NVA06C_CTRL_GET_INFO_PARAMS = struct_NVA06C_CTRL_GET_INFO_PARAMS -class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._fields_ = [ - ('tsgInterleaveLevel', ctypes.c_uint32), -] - -NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS -NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS -NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS - -# values for enumeration 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE' -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE__enumvalues = { - 0: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', - 1: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', - 2: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', -} -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = ctypes.c_uint32 # enum -class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('size', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE), - ] - -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD -class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('l1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), - ('t1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), - ] - -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS -class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._fields_ = [ - ('methodBufferMemdesc', struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2), - ('bar2Addr', ctypes.c_uint64 * 2), - ('numValidEntries', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS -class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._fields_ = [ - ('bRealtime', ctypes.c_ubyte), -] - -NVA06C_CTRL_MAKE_REALTIME_PARAMS = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS -NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS -NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -__all__ = \ - ['ACCESS_COUNTER_NOTIFY_BUFFER', 'ACR_FALCON_LS_STATUS', - 'ACR_REGION_HANDLE', 'ACR_REGION_ID_PROP', 'ACR_REQUEST_PARAMS', - 'ACR_STATUS_PARAMS', 'ADA_A', 'ADA_COMPUTE_A', 'AMPERE_A', - 'AMPERE_B', 'AMPERE_CHANNEL_GPFIFO_A', 'AMPERE_COMPUTE_A', - 'AMPERE_COMPUTE_B', 'AMPERE_DMA_COPY_A', 'AMPERE_DMA_COPY_B', - 'AMPERE_SMC_CONFIG_SESSION', 'AMPERE_SMC_EXEC_PARTITION_REF', - 'AMPERE_SMC_MONITOR_SESSION', 'AMPERE_SMC_PARTITION_REF', - 'AMPERE_USERMODE_A', 'AmpereAControlGPFifo', 'BLACKWELL_A', - 'BLACKWELL_B', 'BLACKWELL_CHANNEL_GPFIFO_A', - 'BLACKWELL_CHANNEL_GPFIFO_B', 'BLACKWELL_COMPUTE_A', - 'BLACKWELL_COMPUTE_B', 'BLACKWELL_DMA_COPY_A', - 'BLACKWELL_DMA_COPY_B', 'BLACKWELL_INLINE_TO_MEMORY_A', - 'BLACKWELL_USERMODE_A', 'BindResultFunc', - 'BlackwellAControlGPFifo', 'CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES', - 'CC_CHAN_ALLOC_IV_SIZE_DWORD', 'CC_CHAN_ALLOC_NONCE_SIZE_DWORD', - 'CE_FIPS_SELF_TEST_AUTH_TAG_SIZE', 'CE_FIPS_SELF_TEST_DATA_SIZE', - 'CE_FIPS_SELF_TEST_IV_SIZE', 'CONTROLLER_FILTER_TYPE_EMWA', - 'CONTROLLER_FILTER_TYPE_MOVING_MAX', 'CTRL_CMD_FB_CBC_OP', - 'CTRL_CMD_FB_CBC_OP_CLEAN', 'CTRL_CMD_FB_CBC_OP_INVALIDATE', - 'Callback1ArgVoidReturn', 'Callback5ArgVoidReturn', - 'ChannelPBSize', 'ChannelPBSize__enumvalues', - 'FABRIC_MANAGER_SESSION', 'FABRIC_VASPACE_A', 'FALCON_ID_DPU', - 'FALCON_ID_FBFLCN', 'FALCON_ID_PMU', 'FALCON_ID_SEC2', - 'FERMI_CONTEXT_SHARE_A', 'FERMI_TWOD_A', 'FERMI_VASPACE_A', - 'FILE_DEVICE_NV', 'G84_PERFBUFFER', 'GF100_CHANNEL_GPFIFO', - 'GF100_DISP_SW', 'GF100_HDACODEC', 'GF100_PROFILER', - 'GF100_SUBDEVICE_INFOROM', 'GF100_SUBDEVICE_MASTER', - 'GF100_TIMED_SEMAPHORE_SW', 'GF100_ZBC_CLEAR', - 'GLOB_TYPE_APITEST', 'GLOB_TYPE_GET_NBSI_ACPI_RAW', - 'GLOB_TYPE_GET_NBSI_DIR', 'GP100_UVM_SW', - 'GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE', 'GPS_MAX_COUNTERS_PER_BLOCK', - 'GPU_PART_NUMBER_FMT', 'GT200_DEBUGGER', 'GUEST_VM_INFO_STATE', - 'GUEST_VM_INFO_STATE_INITIALIZED', - 'GUEST_VM_INFO_STATE_UNINITIALIZED', 'HOPPER_A', - 'HOPPER_CHANNEL_GPFIFO_A', 'HOPPER_COMPUTE_A', - 'HOPPER_DMA_COPY_A', 'HOPPER_SEC2_WORK_LAUNCH_A', - 'HOPPER_USERMODE_A', 'HopperAControlGPFifo', 'IO_VASPACE_A', - 'KEPLER_CHANNEL_GPFIFO_A', 'KEPLER_CHANNEL_GPFIFO_B', - 'KEPLER_CHANNEL_GROUP_A', 'KEPLER_DEVICE_VGPU', - 'KEPLER_INLINE_TO_MEMORY_B', 'KERNEL_GRAPHICS_CONTEXT', - 'LOCK_STRESS_OBJECT', 'MAXWELL_CHANNEL_GPFIFO_A', - 'MAXWELL_DMA_COPY_A', 'MAXWELL_PROFILER', - 'MAXWELL_PROFILER_CONTEXT', 'MAXWELL_PROFILER_DEVICE', - 'MAX_ACCESS_MEMORY_OPS', 'MAX_ACCESS_OPS', - 'MAX_EDID_SIZE_FROM_SBIOS', 'MAX_GET_MAPPINGS_OPS', - 'MMU_FAULT_BUFFER', 'MMU_VIDMEM_ACCESS_BIT_BUFFER', 'MPS_COMPUTE', - 'NV0000_CTRL_CLIENT', - 'NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS', - 'NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS', - 'NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS', - 'NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS', - 'NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS', - 'NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS', - 'NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS', - 'NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT', - 'NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES', - 'NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY', - 'NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT', - 'NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL', - 'NV0000_CTRL_CMD_DIAG_DUMP_RPC', - 'NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES', - 'NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE', - 'NV0000_CTRL_CMD_DIAG_PROFILE_RPC', - 'NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE', - 'NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION', - 'NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS', - 'NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA', - 'NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS', - 'NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE', - 'NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO', - 'NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE', - 'NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID', - 'NV0000_CTRL_CMD_GPU_ATTACH_IDS', - 'NV0000_CTRL_CMD_GPU_DETACH_IDS', - 'NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT', - 'NV0000_CTRL_CMD_GPU_DISCOVER', - 'NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS', - 'NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS', - 'NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS', - 'NV0000_CTRL_CMD_GPU_GET_ID_INFO', - 'NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2', - 'NV0000_CTRL_CMD_GPU_GET_INIT_STATUS', - 'NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE', - 'NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE', - 'NV0000_CTRL_CMD_GPU_GET_PCI_INFO', - 'NV0000_CTRL_CMD_GPU_GET_PROBED_IDS', - 'NV0000_CTRL_CMD_GPU_GET_SVM_SIZE', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256', - 'NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS', - 'NV0000_CTRL_CMD_GPU_LEGACY_CONFIG', - 'NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET', - 'NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE', - 'NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE', - 'NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE', - 'NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID', - 'NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS', - 'NV0000_CTRL_CMD_GSYNC_GET_ID_INFO', - 'NV0000_CTRL_CMD_IDLE_CHANNELS', 'NV0000_CTRL_CMD_NULL', - 'NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS', - 'NV0000_CTRL_CMD_NVD_GET_DUMP', - 'NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_NVD_GET_TIMESTAMP', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST', - 'NV0000_CTRL_CMD_OS_GET_GPU_INFO', - 'NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD', - 'NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD', - 'NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD', - 'NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE', - 'NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR', - 'NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM', - 'NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST', - 'NV0000_CTRL_CMD_PUSH_UCODE_IMAGE', - 'NV0000_CTRL_CMD_SET_SUB_PROCESS_ID', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO', - 'NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS', - 'NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD', - 'NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION', - 'NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2', - 'NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST', - 'NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_FEATURES', - 'NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX', - 'NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_VGPU_CREATE_DEVICE', - 'NV0000_CTRL_CMD_VGPU_DELETE_DEVICE', - 'NV0000_CTRL_CMD_VGPU_GET_INSTANCES', - 'NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS', 'NV0000_CTRL_DIAG', - 'NV0000_CTRL_DIAG_DUMP_RPC_PARAMS', - 'NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_LOCK_METER_ENTRY', - 'NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH', - 'NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP', - 'NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS', - 'NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_RPC_MAX_ENTRIES', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET', - 'NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS', - 'NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_EVENT', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS', - 'NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', - 'NV0000_CTRL_GPS_CMD_PS_STATUS_OFF', - 'NV0000_CTRL_GPS_CMD_PS_STATUS_ON', - 'NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT', - 'NV0000_CTRL_GPS_INPUT_ACPI_CMD', - 'NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN', - 'NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL', - 'NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_INPUT_SENSOR_INDEX', - 'NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERIOD', - 'NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2', - 'NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_PPM_INDEX_BALANCED', - 'NV0000_CTRL_GPS_PPM_INDEX_INVALID', - 'NV0000_CTRL_GPS_PPM_INDEX_MAXPERF', - 'NV0000_CTRL_GPS_PPM_INDEX_QUIET', - 'NV0000_CTRL_GPS_PPM_MASK_INVALID', - 'NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION', - 'NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE', - 'NV0000_CTRL_GPS_RESULT_MAX_LIMIT', - 'NV0000_CTRL_GPS_RESULT_MIN_LIMIT', - 'NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE', - 'NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERIOD', - 'NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT', 'NV0000_CTRL_GPU', - 'NV0000_CTRL_GPUACCT', - 'NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS', - 'NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS', - 'NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED', - 'NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED', - 'NV0000_CTRL_GPU_ACTIVE_DEVICE', - 'NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS', - 'NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS', - 'NV0000_CTRL_GPU_ATTACH_IDS_PARAMS', - 'NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS', - 'NV0000_CTRL_GPU_DETACH_IDS_PARAMS', - 'NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS', - 'NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DISCOVER_PARAMS', - 'NV0000_CTRL_GPU_DRAIN_STATE_DISABLED', - 'NV0000_CTRL_GPU_DRAIN_STATE_ENABLED', - 'NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE', - 'NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE', - 'NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE', - 'NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ID_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS', - 'NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS', - 'NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS', - 'NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS', - 'NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS', - 'NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS', - 'NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS', - 'NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS', - 'NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_SOC_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_SOC_TRUE', - 'NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE', - 'NV0000_CTRL_GPU_IMAGE_TYPE_GSP', - 'NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG', - 'NV0000_CTRL_GPU_INVALID_ID', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES', - 'NV0000_CTRL_GPU_MAX_ATTACHED_GPUS', 'NV0000_CTRL_GPU_MAX_SZNAME', - 'NV0000_CTRL_GPU_MAX_VIDEO_LINKS', - 'NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS', - 'NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS', - 'NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS', - 'NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS', - 'NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS', - 'NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_VIDEO_LINKS', - 'NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS', - 'NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC', 'NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS', - 'NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS', - 'NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC_INVALID_ID', 'NV0000_CTRL_NO_NUMA_NODE', - 'NV0000_CTRL_NVD', 'NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG', - 'NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED', - 'NV0000_CTRL_NVD_DUMP_COMPONENT_SYS', - 'NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS', - 'NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_DUMP_PARAMS', - 'NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS', - 'NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_MAX_BUFFERS', 'NV0000_CTRL_NVD_MAX_DUMP_SIZE', - 'NV0000_CTRL_NVD_MAX_RUNTIME_SIZES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_INT', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_PTR', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_STRING', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED', - 'NV0000_CTRL_NVD_SIGNATURE_SIZE', - 'NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE', - 'NV0000_CTRL_OS_GET_GPU_INFO_PARAMS', 'NV0000_CTRL_OS_MACOS', - 'NV0000_CTRL_OS_UNIX', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE', - 'NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS', - 'NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS', - 'NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS', - 'NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_WINDOWS', 'NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS', - 'NV0000_CTRL_P2P_CAPS_INDEX_C2C', - 'NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK', - 'NV0000_CTRL_P2P_CAPS_INDEX_NVLINK', - 'NV0000_CTRL_P2P_CAPS_INDEX_PCI', - 'NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1', - 'NV0000_CTRL_P2P_CAPS_INDEX_PROP', - 'NV0000_CTRL_P2P_CAPS_INDEX_READ', - 'NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE', - 'NV0000_CTRL_P2P_CAPS_INDEX_WRITE', - 'NV0000_CTRL_P2P_CAPS_MATRIX_ROW', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID', - 'NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT', - 'NV0000_CTRL_PROC', 'NV0000_CTRL_PROFILE_RPC_CMD_DISABLE', - 'NV0000_CTRL_PROFILE_RPC_CMD_ENABLE', - 'NV0000_CTRL_PROFILE_RPC_CMD_RESET', 'NV0000_CTRL_RESERVED', - 'NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS', - 'NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED', - 'NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT', - 'NV0000_CTRL_SLI_STATUS_OK', - 'NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED', 'NV0000_CTRL_SWINSTR', - 'NV0000_CTRL_SYNC_GPU_BOOST', 'NV0000_CTRL_SYSTEM', - 'NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO', - 'NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES', - 'NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW', - 'NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT', - 'NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC', - 'NV0000_CTRL_SYSTEM_CPU_CAP_AVX', - 'NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH', - 'NV0000_CTRL_SYSTEM_CPU_CAP_CMOV', - 'NV0000_CTRL_SYSTEM_CPU_CAP_ERMS', - 'NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_MMX', - 'NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND', - 'NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE2', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE3', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE41', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE42', - 'NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_C6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_C62', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CELA', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_GX', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K10', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K11', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K5', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K62', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K63', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K7', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K8', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_M1', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_M2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_MGX', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P3', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P4', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P5', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P55', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE', - 'NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS', - 'NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE', - 'NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG', - 'NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE', - 'NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE', - 'NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED', - 'NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED', - 'NV0000_CTRL_SYSTEM_HWBC_INFO', - 'NV0000_CTRL_SYSTEM_HWBC_INVALID_ID', - 'NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS', - 'NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED', - 'NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE', - 'NV0000_CTRL_SYSTEM_MAX_HWBCS', - 'NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS', - 'NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS', - 'NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_PARAM_COUNT', 'NV0000_CTRL_SYSTEM_PARAM_CPUE', - 'NV0000_CTRL_SYSTEM_PARAM_CTGP', 'NV0000_CTRL_SYSTEM_PARAM_PDTS', - 'NV0000_CTRL_SYSTEM_PARAM_PPMD', 'NV0000_CTRL_SYSTEM_PARAM_SFAN', - 'NV0000_CTRL_SYSTEM_PARAM_SKNT', 'NV0000_CTRL_SYSTEM_PARAM_TGPU', - 'NV0000_CTRL_SYSTEM_PARAM_TMP1', 'NV0000_CTRL_SYSTEM_PARAM_TMP2', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', 'NV0000_CTRL_VGPU', - 'NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS', - 'NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS', - 'NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS', - 'NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS', - 'NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_GPUACCT_PID_MAX_COUNT', 'NV0000_GPU_MAX_GID_LENGTH', - 'NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT', - 'NV0000_NVD_CPU_TIME_CLK_ID_OSTIME', - 'NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API', - 'NV0000_NVD_CPU_TIME_CLK_ID_TSC', - 'NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE', - 'NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY', - 'NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_OK', 'NV0000_SYNC_GPU_BOOST_GROUP_CONFIG', - 'NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_INFO_PARAMS', - 'NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID', - 'NV0000_SYNC_GPU_BOOST_MAX_GROUPS', - 'NV0000_SYSTEM_CHIPSET_INVALID_ID', - 'NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH', - 'NV0020_GPU_MANAGEMENT', 'NV0060_SYNC_GPU_BOOST', - 'NV0080_ALLOC_PARAMETERS', 'NV0080_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV0080_CTRL_BIF', 'NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS', - 'NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET', - 'NV0080_CTRL_BIF_RESET_PARAMS', - 'NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS', - 'NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BSP', 'NV0080_CTRL_BSP_CAPS_TBL_SIZE', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID', - 'NV0080_CTRL_CIPHER', 'NV0080_CTRL_CLK', - 'NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_BIF_RESET', - 'NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE', - 'NV0080_CTRL_CMD_BSP_GET_CAPS', 'NV0080_CTRL_CMD_BSP_GET_CAPS_V2', - 'NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS', - 'NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO', - 'NV0080_CTRL_CMD_DMA_FILL_PTE_MEM', 'NV0080_CTRL_CMD_DMA_FLUSH', - 'NV0080_CTRL_CMD_DMA_GET_CAPS', - 'NV0080_CTRL_CMD_DMA_GET_PDE_INFO', - 'NV0080_CTRL_CMD_DMA_GET_PTE_INFO', - 'NV0080_CTRL_CMD_DMA_INVALIDATE_TLB', - 'NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY', - 'NV0080_CTRL_CMD_DMA_SET_PTE_INFO', - 'NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE', - 'NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY', - 'NV0080_CTRL_CMD_DMA_UPDATE_PDE_2', 'NV0080_CTRL_CMD_FB_GET_CAPS', - 'NV0080_CTRL_CMD_FB_GET_CAPS_V2', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE', - 'NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY', - 'NV0080_CTRL_CMD_FIFO_GET_CAPS', - 'NV0080_CTRL_CMD_FIFO_GET_CAPS_V2', - 'NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST', - 'NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES', - 'NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE', - 'NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST', - 'NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE', - 'NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES', - 'NV0080_CTRL_CMD_FIFO_START_RUNLIST', - 'NV0080_CTRL_CMD_FIFO_STOP_RUNLIST', - 'NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE', - 'NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_CLASSLIST', - 'NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2', - 'NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER', - 'NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES', - 'NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE', - 'NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE', - 'NV0080_CTRL_CMD_GPU_GET_VGX_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER', - 'NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE', - 'NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE', - 'NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE', - 'NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER', - 'NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE', - 'NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE', - 'NV0080_CTRL_CMD_GPU_SET_VIDLINK', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON', - 'NV0080_CTRL_CMD_GR_GET_CAPS', 'NV0080_CTRL_CMD_GR_GET_CAPS_V2', - 'NV0080_CTRL_CMD_GR_GET_INFO', 'NV0080_CTRL_CMD_GR_GET_INFO_V2', - 'NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_HOST_GET_CAPS', - 'NV0080_CTRL_CMD_HOST_GET_CAPS_V2', - 'NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE', - 'NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL', - 'NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL', - 'NV0080_CTRL_CMD_MSENC_GET_CAPS', - 'NV0080_CTRL_CMD_MSENC_GET_CAPS_V2', 'NV0080_CTRL_CMD_NULL', - 'NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2', - 'NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO', - 'NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH', - 'NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL', 'NV0080_CTRL_DMA', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_CAPS_TBL_SIZE', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS', - 'NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FLUSH_PARAMS', - 'NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM', - 'NV0080_CTRL_DMA_GET_CAPS_PARAMS', - 'NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK', - 'NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS', - 'NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE', 'NV0080_CTRL_FB', - 'NV0080_CTRL_FB_CAPS_TBL_SIZE', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', - 'NV0080_CTRL_FB_GET_CAPS_PARAMS', - 'NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS', - 'NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS', - 'NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO', 'NV0080_CTRL_FIFO_CAPS_TBL_SIZE', - 'NV0080_CTRL_FIFO_GET_CAPS_PARAMS', - 'NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS', - 'NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS', - 'NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM', - 'NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM', - 'NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS', - 'NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT', - 'NV0080_CTRL_FIFO_START_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU', 'NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE', - 'NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM', - 'NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS', - 'NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS', - 'NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS', - 'NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS', - 'NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS', - 'NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS', - 'NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS', - 'NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS', - 'NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE', - 'NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE', - 'NV0080_CTRL_GPU_SET_VIDLINK_PARAMS', - 'NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE', - 'NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED', - 'NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED', - 'NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX', 'NV0080_CTRL_GR', - 'NV0080_CTRL_GR_CAPS_TBL_SIZE', 'NV0080_CTRL_GR_GET_CAPS_PARAMS', - 'NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_INFO_PARAMS', - 'NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_INFO_V2_PARAMS', - 'NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_INFO', - 'NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT', - 'NV0080_CTRL_GR_INFO_INDEX_DUMMY', - 'NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY', - 'NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES', - 'NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES', - 'NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES', - 'NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX', - 'NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM', - 'NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894', - 'NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_VERSION', - 'NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT', - 'NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR', - 'NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED', - 'NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE', - 'NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT', - 'NV0080_CTRL_GR_INFO_MAX_SIZE', - 'NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK', - 'NV0080_CTRL_GR_ROUTE_INFO', - 'NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 'NV0080_CTRL_HOST', - 'NV0080_CTRL_HOST_CAPS_TBL_SIZE', - 'NV0080_CTRL_HOST_GET_CAPS_PARAMS', - 'NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_INTERNAL', - 'NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS', - 'NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_MSENC', 'NV0080_CTRL_MSENC_CAPS_TBL_SIZE', - 'NV0080_CTRL_MSENC_GET_CAPS_PARAMS', - 'NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_NVJPG', 'NV0080_CTRL_NVJPG_CAPS_TBL_SIZE', - 'NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_NVLINK', 'NV0080_CTRL_OS_UNIX', - 'NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS', - 'NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_PERF', 'NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS', - 'NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED', - 'NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_RC', 'NV0080_CTRL_RESERVED', 'NV0080_CTRL_VIDEO', - 'NV0092_RG_LINE_CALLBACK', 'NV01_ALLOC_MEMORY', - 'NV01_ALLOC_OBJECT', 'NV01_CONTEXT_DMA', 'NV01_DEVICE_0', - 'NV01_EVENT', 'NV01_EVENT_BROADCAST', 'NV01_EVENT_CLIENT_RM', - 'NV01_EVENT_KERNEL_CALLBACK', 'NV01_EVENT_KERNEL_CALLBACK_EX', - 'NV01_EVENT_NONSTALL_INTR', 'NV01_EVENT_OS_EVENT', - 'NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION', - 'NV01_EVENT_SUBDEVICE_SPECIFIC', 'NV01_EVENT_WIN32_EVENT', - 'NV01_EVENT_WITHOUT_EVENT_DATA', 'NV01_FREE', - 'NV01_MEMORY_DEVICELESS', 'NV01_MEMORY_FLA', - 'NV01_MEMORY_FRAMEBUFFER_CONSOLE', 'NV01_MEMORY_HW_RESOURCES', - 'NV01_MEMORY_LIST_FBMEM', 'NV01_MEMORY_LIST_OBJECT', - 'NV01_MEMORY_LIST_SYSTEM', 'NV01_MEMORY_LOCAL_PHYSICAL', - 'NV01_MEMORY_LOCAL_PRIVILEGED', 'NV01_MEMORY_LOCAL_USER', - 'NV01_MEMORY_PRIVILEGED', 'NV01_MEMORY_SYNCPOINT', - 'NV01_MEMORY_SYSTEM', 'NV01_MEMORY_SYSTEM_DYNAMIC', - 'NV01_MEMORY_SYSTEM_OS_DESCRIPTOR', 'NV01_MEMORY_USER', - 'NV01_MEMORY_VIRTUAL', 'NV01_NULL', 'NV01_NULL_OBJECT', - 'NV01_ROOT', 'NV01_ROOT_CLIENT', 'NV01_ROOT_NON_PRIV', - 'NV01_ROOT_USER', 'NV01_TIMER', 'NV04_ACCESS_REGISTRY', - 'NV04_ADD_VBLANK_CALLBACK', 'NV04_ALLOC', - 'NV04_ALLOC_CONTEXT_DMA', 'NV04_BIND_CONTEXT_DMA', 'NV04_CONTROL', - 'NV04_DISPLAY_COMMON', 'NV04_DUP_HANDLE_FLAGS_NONE', - 'NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE', - 'NV04_DUP_OBJECT', 'NV04_GET_EVENT_DATA', 'NV04_I2C_ACCESS', - 'NV04_IDLE_CHANNELS', 'NV04_MAP_MEMORY', 'NV04_MAP_MEMORY_DMA', - 'NV04_MAP_MEMORY_FLAGS_NONE', 'NV04_MAP_MEMORY_FLAGS_USER', - 'NV04_SHARE', 'NV04_SOFTWARE_TEST', 'NV04_UNMAP_MEMORY', - 'NV04_UNMAP_MEMORY_DMA', 'NV04_UPDATE_DEVICE_MAPPING_INFO', - 'NV04_VID_HEAP_CONTROL', 'NV1_EVENT', 'NV1_EVENT_KERNEL_CALLBACK', - 'NV1_EVENT_KERNEL_CALLBACK_EX', 'NV1_EVENT_OS_EVENT', - 'NV1_EVENT_WIN32_EVENT', 'NV1_MEMORY_LOCAL_PRIVILEGED', - 'NV1_MEMORY_LOCAL_USER', 'NV1_MEMORY_PRIVILEGED', - 'NV1_MEMORY_SYSTEM', 'NV1_MEMORY_SYSTEM_DYNAMIC', - 'NV1_MEMORY_USER', 'NV1_NULL', 'NV1_NULL_OBJECT', 'NV1_ROOT', - 'NV1_ROOT_NON_PRIV', 'NV1_TIMER', - 'NV2080CtrlNocatJournalDataTdrReason', - 'NV2080CtrlNocatJournalInsertRecord', - 'NV2080CtrlNocatJournalRclog', 'NV2080CtrlNocatJournalSetTag', - 'NV2080_BIOS_GET_NBSI_MAX_RET_SIZE', - 'NV2080_CLIENT_TYPE_ALLCLIENTS', 'NV2080_CLIENT_TYPE_COLOR', - 'NV2080_CLIENT_TYPE_DA', 'NV2080_CLIENT_TYPE_DEPTH', - 'NV2080_CLIENT_TYPE_FE', 'NV2080_CLIENT_TYPE_MSPDEC', - 'NV2080_CLIENT_TYPE_MSPPP', 'NV2080_CLIENT_TYPE_MSVLD', - 'NV2080_CLIENT_TYPE_SCC', 'NV2080_CLIENT_TYPE_TEX', - 'NV2080_CLIENT_TYPE_VIC', 'NV2080_CLIENT_TYPE_WID', - 'NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC', - 'NV2080_CTRL_ACPI_DSM_READ_SIZE', 'NV2080_CTRL_ACR', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS', - 'NV2080_CTRL_BIF', 'NV2080_CTRL_BIOS', - 'NV2080_CTRL_BIOS_GET_INFO_PARAMS', - 'NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS', - 'NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH', - 'NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE', - 'NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE', - 'NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND', - 'NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE', - 'NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE', - 'NV2080_CTRL_BIOS_GET_NBSI_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_SUCCESS', - 'NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS', - 'NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS', - 'NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_INFO', - 'NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION', - 'NV2080_CTRL_BIOS_INFO_INDEX_REVISION', - 'NV2080_CTRL_BIOS_INFO_MAX_SIZE', - 'NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH', - 'NV2080_CTRL_BIOS_NBSI_MODULE_CPL', - 'NV2080_CTRL_BIOS_NBSI_MODULE_D3D', - 'NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER', - 'NV2080_CTRL_BIOS_NBSI_MODULE_MODE', - 'NV2080_CTRL_BIOS_NBSI_MODULE_OGL', - 'NV2080_CTRL_BIOS_NBSI_MODULE_PMU', - 'NV2080_CTRL_BIOS_NBSI_MODULE_RM', - 'NV2080_CTRL_BIOS_NBSI_MODULE_ROOT', - 'NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN', - 'NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO', - 'NV2080_CTRL_BIOS_NBSI_NUM_MODULES', - 'NV2080_CTRL_BIOS_NBSI_REG_STRING', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE', - 'NV2080_CTRL_BUS', 'NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS', - 'NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_BFD_PARAMS', - 'NV2080_CTRL_BUS_GET_BFD_PARAMSARR', - 'NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU', - 'NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU', - 'NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS', - 'NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_GET_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS', - 'NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_INFO', - 'NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED', - 'NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE', - 'NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_INTLINE', - 'NV2080_CTRL_BUS_INFO_INDEX_MAX', - 'NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE', - 'NV2080_CTRL_BUS_INFO_INDEX_TYPE', - 'NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED', - 'NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST', - 'NV2080_CTRL_BUS_INFO_TYPE_AXI', 'NV2080_CTRL_BUS_INFO_TYPE_FPCI', - 'NV2080_CTRL_BUS_INFO_TYPE_PCI', - 'NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS', - 'NV2080_CTRL_BUS_MAP_BAR2_PARAMS', - 'NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_MAX_NUM_GPUS', 'NV2080_CTRL_BUS_MAX_NUM_LANES', - 'NV2080_CTRL_BUS_MAX_PCI_BARS', - 'NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO', - 'NV2080_CTRL_BUS_PCI_BAR_INFO', - 'NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE', - 'NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS', - 'NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_TYPE', - 'NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S', - 'NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS', - 'NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS', - 'NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS', - 'NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS', - 'NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS', - 'NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS', - 'NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID', 'NV2080_CTRL_CE', - 'NV2080_CTRL_CE_CAPS_TBL_SIZE', - 'NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CAPS_V2_PARAMS', - 'NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS', - 'NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS', - 'NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_LCE_TYPE', 'NV2080_CTRL_CE_LCE_TYPE_C2C', - 'NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', - 'NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', - 'NV2080_CTRL_CE_LCE_TYPE_DECOMP', - 'NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', - 'NV2080_CTRL_CE_LCE_TYPE_PCIE', 'NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', - 'NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', - 'NV2080_CTRL_CE_LCE_TYPE_SCRUB', 'NV2080_CTRL_CE_MAX_HSHUBS', - 'NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS', - 'NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS', - 'NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CIPHER', 'NV2080_CTRL_CLK', - 'NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_CLK_LEGACY_PRIVILEGED', - 'NV2080_CTRL_CMD_BIOS_GET_INFO', - 'NV2080_CTRL_CMD_BIOS_GET_INFO_V2', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI_V2', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BIOS_GET_SKU_INFO', - 'NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT', - 'NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS', - 'NV2080_CTRL_CMD_BUS_GET_BFD', 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO', - 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_EOM_STATUS', - 'NV2080_CTRL_CMD_BUS_GET_INFO', 'NV2080_CTRL_CMD_BUS_GET_INFO_V2', - 'NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO', - 'NV2080_CTRL_CMD_BUS_GET_PCI_INFO', - 'NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_MAP_BAR2', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM', - 'NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED', - 'NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS', - 'NV2080_CTRL_CMD_BUS_UNMAP_BAR2', - 'NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING', - 'NV2080_CTRL_CMD_BUS_VERIFY_BAR2', - 'NV2080_CTRL_CMD_CE_GET_ALL_CAPS', - 'NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS', - 'NV2080_CTRL_CMD_CE_GET_CAPS', 'NV2080_CTRL_CMD_CE_GET_CAPS_V2', - 'NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE', - 'NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2', - 'NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO', - 'NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS', - 'NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED', - 'NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG', - 'NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB', - 'NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS', - 'NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2', - 'NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD', - 'NV2080_CTRL_CMD_DMA_GET_INFO', - 'NV2080_CTRL_CMD_DMA_INVALIDATE_TLB', - 'NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS', - 'NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS', - 'NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF', - 'NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI', - 'NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES', - 'NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY', - 'NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION', - 'NV2080_CTRL_CMD_EVENT_SET_TRIGGER', - 'NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO', - 'NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF', - 'NV2080_CTRL_CMD_FB_ACR_CLIENT_ID', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM', - 'NV2080_CTRL_CMD_FB_ALLOCATION_INFO', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_CBC_OP', 'NV2080_CTRL_CMD_FB_CBC_OP_PARAMS', - 'NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_CLIENT_INFO', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_FREE_TILE', - 'NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS', - 'NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET', - 'NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED', - 'NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE', - 'NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION', - 'NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG', - 'NV2080_CTRL_CMD_FB_GET_FS_INFO', - 'NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO', - 'NV2080_CTRL_CMD_FB_GET_INFO', 'NV2080_CTRL_CMD_FB_GET_INFO_V2', - 'NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP', - 'NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT', - 'NV2080_CTRL_CMD_FB_GET_NUMA_INFO', - 'NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS', - 'NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM', - 'NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT', - 'NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO', - 'NV2080_CTRL_CMD_FB_GET_STATUS', 'NV2080_CTRL_CMD_FB_IS_KIND', - 'NV2080_CTRL_CMD_FB_OFFLINE_PAGES', - 'NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION', - 'NV2080_CTRL_CMD_FB_SET_READ_LIMIT', 'NV2080_CTRL_CMD_FB_SET_RRD', - 'NV2080_CTRL_CMD_FB_SET_VPR', - 'NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT', - 'NV2080_CTRL_CMD_FB_STATS_ENTRY', 'NV2080_CTRL_CMD_FB_STATS_GET', - 'NV2080_CTRL_CMD_FB_STATS_GET_PARAMS', - 'NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_STATS_MAX_OWNER', - 'NV2080_CTRL_CMD_FB_STATS_OWNER_INFO', - 'NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_CODE', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', - 'NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE', - 'NV2080_CTRL_CMD_FIFO_BIND_ENGINES', - 'NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2', - 'NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE', - 'NV2080_CTRL_CMD_FIFO_GET_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG', - 'NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE', - 'NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB', - 'NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO', - 'NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS', - 'NV2080_CTRL_CMD_FLA_GET_RANGE', 'NV2080_CTRL_CMD_FLA_RANGE', - 'NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK', - 'NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO', - 'NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE', - 'NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE', - 'NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO', - 'NV2080_CTRL_CMD_GC6_ENTRY', 'NV2080_CTRL_CMD_GC6_EXIT', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GET_P2P_CAPS', 'NV2080_CTRL_CMD_GET_RC_INFO', - 'NV2080_CTRL_CMD_GET_RC_RECOVERY', - 'NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', - 'NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION', - 'NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_EVICT_CTX', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU', - 'NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS', - 'NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU', - 'NV2080_CTRL_CMD_GPU_GET_CACHED_INFO', - 'NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO', - 'NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS', - 'NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_ENGINES', - 'NV2080_CTRL_CMD_GPU_GET_ENGINES_V2', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX', - 'NV2080_CTRL_CMD_GPU_GET_GFID', - 'NV2080_CTRL_CMD_GPU_GET_GID_INFO', - 'NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE', - 'NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID', - 'NV2080_CTRL_CMD_GPU_GET_ID', - 'NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING', - 'NV2080_CTRL_CMD_GPU_GET_ILLUM', 'NV2080_CTRL_CMD_GPU_GET_INFO', - 'NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_INFO_V2', - 'NV2080_CTRL_CMD_GPU_GET_IP_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE', - 'NV2080_CTRL_CMD_GPU_GET_NAME_STRING', - 'NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC', - 'NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO', - 'NV2080_CTRL_CMD_GPU_GET_OEM_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_PES_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PIDS', - 'NV2080_CTRL_CMD_GPU_GET_PID_INFO', - 'NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION', - 'NV2080_CTRL_CMD_GPU_GET_RESET_STATUS', - 'NV2080_CTRL_CMD_GPU_GET_SDM', - 'NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING', - 'NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO', - 'NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK', - 'NV2080_CTRL_CMD_GPU_GET_VF_CAPS', - 'NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE', - 'NV2080_CTRL_CMD_GPU_GET_VPR_CAPS', - 'NV2080_CTRL_CMD_GPU_GET_VPR_INFO', - 'NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE', - 'NV2080_CTRL_CMD_GPU_ILLUM_PARAMS', - 'NV2080_CTRL_CMD_GPU_INITIALIZE_CTX', - 'NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET', - 'NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU', - 'NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP', - 'NV2080_CTRL_CMD_GPU_PROMOTE_CTX', - 'NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT', - 'NV2080_CTRL_CMD_GPU_QUERY_MODE', - 'NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS', - 'NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT', - 'NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS', - 'NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES', - 'NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION', - 'NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR', - 'NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR', - 'NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE', - 'NV2080_CTRL_CMD_GPU_SET_ILLUM', - 'NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE', - 'NV2080_CTRL_CMD_GPU_SET_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_SET_POWER', 'NV2080_CTRL_CMD_GPU_SET_SDM', - 'NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET', - 'NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST', - 'NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT', - 'NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO', - 'NV2080_CTRL_CMD_GR_CTXSW_PM_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_PM_MODE', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', - 'NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE', - 'NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE', - 'NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID', - 'NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2', - 'NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE', - 'NV2080_CTRL_CMD_GR_GET_CAPS_V2', - 'NV2080_CTRL_CMD_GR_GET_CTXSW_MODES', - 'NV2080_CTRL_CMD_GR_GET_CTXSW_STATS', - 'NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO', - 'NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE', - 'NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL', - 'NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES', - 'NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO', - 'NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER', - 'NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT', - 'NV2080_CTRL_CMD_GR_GET_GPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP', - 'NV2080_CTRL_CMD_GR_GET_INFO', 'NV2080_CTRL_CMD_GR_GET_INFO_V2', - 'NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC', - 'NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_PPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_ROP_INFO', - 'NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS', - 'NV2080_CTRL_CMD_GR_GET_TPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_CMD_GR_GET_ZCULL_INFO', - 'NV2080_CTRL_CMD_GR_GET_ZCULL_MASK', - 'NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS', - 'NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE', - 'NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE', - 'NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS', - 'NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE', - 'NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE', - 'NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP', - 'NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE', - 'NV2080_CTRL_CMD_GSP_GET_FEATURES', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_I2C_ACCESS', - 'NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE', - 'NV2080_CTRL_CMD_I2C_READ_BUFFER', 'NV2080_CTRL_CMD_I2C_READ_REG', - 'NV2080_CTRL_CMD_I2C_WRITE_BUFFER', - 'NV2080_CTRL_CMD_I2C_WRITE_REG', - 'NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS', - 'NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS', - 'NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO', - 'NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX', - 'NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR', - 'NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_CCU_MAP', - 'NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE', - 'NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP', - 'NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE', - 'NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM', - 'NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS', - 'NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL', - 'NV2080_CTRL_CMD_INTERNAL_FBSR_INIT', - 'NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE', - 'NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP', - 'NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM', - 'NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD', - 'NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA', - 'NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR', - 'NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE', - 'NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID', - 'NV2080_CTRL_CMD_INTERNAL_MAX_BSPS', - 'NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS', - 'NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB', - 'NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT', - 'NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS', - 'NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE', - 'NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL', - 'NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES', - 'NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP', - 'NV2080_CTRL_CMD_MC_GET_ARCH_INFO', - 'NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS', - 'NV2080_CTRL_CMD_MC_GET_MANUFACTURER', - 'NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE', - 'NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS', 'NV2080_CTRL_CMD_NULL', - 'NV2080_CTRL_CMD_NVD_GET_DUMP', - 'NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE', - 'NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE', - 'NV2080_CTRL_CMD_NVLINK_CYCLE_LINK', - 'NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK', - 'NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS', - 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL', - 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND', - 'NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_NVLINK_GET_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_GET_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT', - 'NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD', - 'NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES', - 'NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS', - 'NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR', - 'NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA', - 'NV2080_CTRL_CMD_NVLINK_INJECT_ERROR', - 'NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR', - 'NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR', - 'NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED', - 'NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP', - 'NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP', - 'NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS', - 'NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN', - 'NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_SET_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT', - 'NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD', - 'NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER', - 'NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO', - 'NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF', - 'NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER', - 'NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER', - 'NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT', - 'NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS', - 'NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER', - 'NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS', - 'NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS', - 'NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY', - 'NV2080_CTRL_CMD_PERF_BOOST', - 'NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE', - 'NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2', - 'NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO', - 'NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2', - 'NV2080_CTRL_CMD_PERF_GET_POWERSTATE', - 'NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE', - 'NV2080_CTRL_CMD_PERF_GPU_IS_IDLE', - 'NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT', - 'NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL', - 'NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL', - 'NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW', - 'NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE', - 'NV2080_CTRL_CMD_PERF_SET_POWERSTATE', - 'NV2080_CTRL_CMD_PERF_VID_ENG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', - 'NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO', - 'NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG', - 'NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG', - 'NV2080_CTRL_CMD_RC_GET_ERROR', - 'NV2080_CTRL_CMD_RC_GET_ERROR_COUNT', - 'NV2080_CTRL_CMD_RC_GET_ERROR_V2', - 'NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO', - 'NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE', - 'NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE', - 'NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE', - 'NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE', - 'NV2080_CTRL_CMD_RC_INFO_PARAMS', - 'NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM', - 'NV2080_CTRL_CMD_RC_RECOVERY_DISABLED', - 'NV2080_CTRL_CMD_RC_RECOVERY_ENABLED', - 'NV2080_CTRL_CMD_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS', - 'NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY', - 'NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG', - 'NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE', - 'NV2080_CTRL_CMD_SET_GPFIFO', 'NV2080_CTRL_CMD_SET_GPFIFO_PARAMS', - 'NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_SET_RC_INFO', 'NV2080_CTRL_CMD_SET_RC_RECOVERY', - 'NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT', - 'NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE', - 'NV2080_CTRL_CMD_TIMER_CANCEL', - 'NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO', - 'NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET', - 'NV2080_CTRL_CMD_TIMER_GET_TIME', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN', - 'NV2080_CTRL_CTXSW_PM_MODE_CTXSW', - 'NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW', - 'NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW', - 'NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER', 'NV2080_CTRL_DMA', - 'NV2080_CTRL_DMABUF', - 'NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT', - 'NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE', - 'NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS', - 'NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMABUF_MAX_HANDLES', - 'NV2080_CTRL_DMABUF_MEM_HANDLE_INFO', - 'NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES', - 'NV2080_CTRL_DMA_GET_INFO_PARAMS', - 'NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMA_INFO', 'NV2080_CTRL_DMA_INFO_INDEX_MAX', - 'NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO', - 'NV2080_CTRL_ECC', - 'NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS', - 'NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS', - 'NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_ECC_NON_PRIVILEGED', - 'NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE', 'NV2080_CTRL_EVENT', - 'NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS', - 'NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS', - 'NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS', - 'NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS', - 'NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS', - 'NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS', - 'NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EXEC_PARTITION_SPAN', 'NV2080_CTRL_EXTI2C', - 'NV2080_CTRL_FAS', 'NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE', - 'NV2080_CTRL_FAULT_BUFFER_REPLAYABLE', 'NV2080_CTRL_FB', - 'NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS', - 'NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES', - 'NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_FS_INFO_FBPA_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP', - 'NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_INVALID_QUERY', - 'NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LTS_MASK', - 'NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_MAX_QUERIES', - 'NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE', - 'NV2080_CTRL_FB_FS_INFO_PAC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_QUERY', 'NV2080_CTRL_FB_FS_INFO_ROP_MASK', - 'NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS', - 'NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS', - 'NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS', - 'NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS', - 'NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_FS_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH', - 'NV2080_CTRL_FB_GET_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS', - 'NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS', - 'NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_STATUS_PARAMS', - 'NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW', - 'NV2080_CTRL_FB_INFO', - 'NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED', - 'NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT', - 'NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH', - 'NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE', - 'NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW', - 'NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_FBP_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN', - 'NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_START', - 'NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB', - 'NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE', - 'NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1', - 'NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_MAX', - 'NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID', - 'NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1', - 'NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB', - 'NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_CFG', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE', - 'NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T', - 'NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND', - 'NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4', - 'NV2080_CTRL_FB_IS_KIND_PARAMS', - 'NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES', - 'NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO', - 'NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS', - 'NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL', - 'NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS', - 'NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS', - 'NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS', - 'NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD', - 'NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD', - 'NV2080_CTRL_FB_REMAP_ENTRY', - 'NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE', - 'NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_SET_RRD_PARAMS', - 'NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_STATUS_FAILED', - 'NV2080_CTRL_FB_STATUS_NOT_APPLICABLE', - 'NV2080_CTRL_FB_STATUS_PENDING', 'NV2080_CTRL_FB_STATUS_READY', - 'NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS', - 'NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO', 'NV2080_CTRL_FIFO_BIND_CHANNEL', - 'NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS', - 'NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS', - 'NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_CHANNEL_MEM_INFO', - 'NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS', - 'NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE', - 'NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA', - 'NV2080_CTRL_FIFO_DEVICE_ENTRY', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE', - 'NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE', - 'NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS', - 'NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_GET_INFO_PARAMS', - 'NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT', - 'NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS', - 'NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_INFO', - 'NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET', - 'NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE', - 'NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE', - 'NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE', - 'NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL', - 'NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP', - 'NV2080_CTRL_FIFO_MEM_INFO', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS', - 'NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE', - 'NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE', - 'NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS', - 'NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT', - 'NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS', - 'NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS', - 'NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS', - 'NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA', 'NV2080_CTRL_FLA_ACTION', - 'NV2080_CTRL_FLA_ACTION_BIND', 'NV2080_CTRL_FLA_ACTION_UNBIND', - 'NV2080_CTRL_FLA_ADDRSPACE', 'NV2080_CTRL_FLA_ADDRSPACE_FBMEM', - 'NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', - 'NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS', - 'NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_GET_RANGE_PARAMS', - 'NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_RANGE_PARAMS', - 'NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE', - 'NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS', - 'NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN', 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS', - 'NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0', - 'NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT', - 'NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES', - 'NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES', - 'NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED', - 'NV2080_CTRL_FUSE', 'NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GC6_ENTRY_PARAMS', - 'NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GC6_EXIT_PARAMS', - 'NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GC6_FLAVOR_ID', 'NV2080_CTRL_GC6_FLAVOR_ID_MAX', - 'NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', - 'NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', - 'NV2080_CTRL_GC6_FLAVOR_INFO', 'NV2080_CTRL_GC6_STEP_ID', - 'NV2080_CTRL_GC6_STEP_ID_GPU_OFF', 'NV2080_CTRL_GC6_STEP_ID_MAX', - 'NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', - 'NV2080_CTRL_GET_P2P_CAPS_PARAMS', - 'NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GET_RC_INFO_PARAMS', - 'NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GET_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS', - 'NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPIO', 'NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GPU', 'NV2080_CTRL_GPUMON_SAMPLE', - 'NV2080_CTRL_GPUMON_SAMPLES', - 'NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL', - 'NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS', - 'NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_MAX', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE', - 'NV2080_CTRL_GPU_COMPUTE_PROFILE', - 'NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS', - 'NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO', - 'NV2080_CTRL_GPU_DEBUG_MODE_DISABLED', - 'NV2080_CTRL_GPU_DEBUG_MODE_ENABLED', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE', - 'NV2080_CTRL_GPU_ECC_UNIT_COUNT', 'NV2080_CTRL_GPU_ECC_UNIT_GSP', - 'NV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED', - 'NV2080_CTRL_GPU_FAULT_PACKET', - 'NV2080_CTRL_GPU_FAULT_PACKET_SIZE', - 'NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS', - 'NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS', - 'NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS', - 'NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINES_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS', - 'NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GFID_PARAMS', - 'NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GID_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS', - 'NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS', - 'NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ID_PARAMS', - 'NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ILLUM_PARAMS', - 'NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY', - 'NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON', - 'NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PMGR', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU', - 'NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS', - 'NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII', - 'NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE', - 'NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS', - 'NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS', - 'NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITION_INFO', - 'NV2080_CTRL_GPU_GET_PES_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS', - 'NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST', - 'NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT', - 'NV2080_CTRL_GPU_GET_PIDS_PARAMS', - 'NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT', - 'NV2080_CTRL_GPU_GET_PID_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS', - 'NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SDM_PARAMS', - 'NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS', - 'NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN', - 'NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS', - 'NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS', - 'NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS', - 'NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS', - 'NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', - 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', - 'NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS', - 'NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS', - 'NV2080_CTRL_GPU_INFO', - 'NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN', - 'NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN', - 'NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0', - 'NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1', - 'NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE', - 'NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS', - 'NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO', - 'NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES', - 'NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO', - 'NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES', - 'NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO', - 'NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES', - 'NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GPU_MAX_CE_PER_SMC', - 'NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS', - 'NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS', - 'NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS', - 'NV2080_CTRL_GPU_MAX_GPC_PER_SMC', - 'NV2080_CTRL_GPU_MAX_PARTITIONS', - 'NV2080_CTRL_GPU_MAX_PARTITION_IDS', - 'NV2080_CTRL_GPU_MAX_SMC_IDS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS', - 'NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES', - 'NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS', - 'NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE', - 'NV2080_CTRL_GPU_PARTITION_ID_INVALID', - 'NV2080_CTRL_GPU_PARTITION_MAX_TYPES', - 'NV2080_CTRL_GPU_PARTITION_SPAN', - 'NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_PID_INFO', 'NV2080_CTRL_GPU_PID_INFO_DATA', - 'NV2080_CTRL_GPU_PID_INFO_INDEX_MAX', - 'NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE', - 'NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA', - 'NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS', - 'NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS', - 'NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE', - 'NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS', - 'NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE', - 'NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE', - 'NV2080_CTRL_GPU_QUERY_MODE_PARAMS', - 'NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU', - 'NV2080_CTRL_GPU_RECOVERY_ACTION', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', 'NV2080_CTRL_GPU_REG_OP', - 'NV2080_CTRL_GPU_REG_OP_READ_08', - 'NV2080_CTRL_GPU_REG_OP_READ_32', - 'NV2080_CTRL_GPU_REG_OP_READ_64', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE', - 'NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS', - 'NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS', - 'NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP', - 'NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE', - 'NV2080_CTRL_GPU_REG_OP_TYPE_FB', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP', - 'NV2080_CTRL_GPU_REG_OP_WRITE_08', - 'NV2080_CTRL_GPU_REG_OP_WRITE_32', - 'NV2080_CTRL_GPU_REG_OP_WRITE_64', - 'NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS', - 'NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS', - 'NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS', - 'NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS', - 'NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS', - 'NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_ILLUM_PARAMS', - 'NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF', - 'NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITION_INFO', - 'NV2080_CTRL_GPU_SET_POWER_PARAMS', - 'NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7', - 'NV2080_CTRL_GPU_SET_SDM_PARAMS', - 'NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS', - 'NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS', - 'NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB', 'NV2080_CTRL_GR', - 'NV2080_CTRL_GRMGR', 'NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS', - 'NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_MAX_SMC_IDS', - 'NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN', - 'NV2080_CTRL_GR_DISABLED_SM_VGPC_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', - 'NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS', - 'NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS', - 'NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS', - 'NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS', - 'NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_PPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_TPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED', - 'NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS', - 'NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_INFO', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE', - 'NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT', - 'NV2080_CTRL_GR_INFO_INDEX_DUMMY', - 'NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY', - 'NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES', - 'NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES', - 'NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES', - 'NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX', - 'NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM', - 'NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894', - 'NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_VERSION', - 'NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT', - 'NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR', - 'NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED', - 'NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE', - 'NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT', - 'NV2080_CTRL_GR_INFO_MAX_SIZE', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_00', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_04', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_4', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_05', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_4', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_6', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_8', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_9', - 'NV2080_CTRL_GR_INFO_SM_VERSION_4_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_03', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_03', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_05', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_06', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_07', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_08', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_09', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_6', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_7', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_8', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_9', - 'NV2080_CTRL_GR_INFO_SM_VERSION_9_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_9_00', - 'NV2080_CTRL_GR_INFO_SM_VERSION_NONE', - 'NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK', - 'NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT', - 'NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS', - 'NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_ROUTE_INFO', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS', - 'NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_VAT_ALARM_DATA', - 'NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC', - 'NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC', 'NV2080_CTRL_GSP', - 'NV2080_CTRL_GSP_GET_FEATURES_PARAMS', - 'NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE', - 'NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE', - 'NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE', - 'NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE', - 'NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS', - 'NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX', - 'NV2080_CTRL_GSP_LIBOS_POOL_STATS', - 'NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT', 'NV2080_CTRL_I2C', - 'NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE', - 'NV2080_CTRL_I2C_ACCESS_CMD_NULL', - 'NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER', - 'NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE', - 'NV2080_CTRL_I2C_ACCESS_CMD_RELEASE', - 'NV2080_CTRL_I2C_ACCESS_CMD_RESET', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_START', - 'NV2080_CTRL_I2C_ACCESS_CMD_STOP', - 'NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT', - 'NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER', - 'NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE', - 'NV2080_CTRL_I2C_ACCESS_FLAG_ACK', - 'NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS', - 'NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED', - 'NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE', - 'NV2080_CTRL_I2C_ACCESS_FLAG_RAB', - 'NV2080_CTRL_I2C_ACCESS_FLAG_RESTART', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_START', - 'NV2080_CTRL_I2C_ACCESS_FLAG_STOP', - 'NV2080_CTRL_I2C_ACCESS_NUM_PORTS', - 'NV2080_CTRL_I2C_ACCESS_PARAMS', - 'NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_ACCESS_PORT_1', 'NV2080_CTRL_I2C_ACCESS_PORT_10', - 'NV2080_CTRL_I2C_ACCESS_PORT_2', 'NV2080_CTRL_I2C_ACCESS_PORT_3', - 'NV2080_CTRL_I2C_ACCESS_PORT_4', 'NV2080_CTRL_I2C_ACCESS_PORT_5', - 'NV2080_CTRL_I2C_ACCESS_PORT_6', 'NV2080_CTRL_I2C_ACCESS_PORT_7', - 'NV2080_CTRL_I2C_ACCESS_PORT_8', 'NV2080_CTRL_I2C_ACCESS_PORT_9', - 'NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC', - 'NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY', - 'NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY', - 'NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING', - 'NV2080_CTRL_I2C_ACCESS_STATUS_ERROR', - 'NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND', - 'NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR', - 'NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS', - 'NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS', - 'NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED', - 'NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED', - 'NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC', - 'NV2080_CTRL_I2C_FLAGS_PRIVILEGE', 'NV2080_CTRL_I2C_FLAGS_PX3540', - 'NV2080_CTRL_I2C_MAX_ADDR_ENTRIES', 'NV2080_CTRL_I2C_MAX_ENTRIES', - 'NV2080_CTRL_I2C_MAX_REG_LEN', - 'NV2080_CTRL_I2C_READ_BUFFER_PARAMS', - 'NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_READ_REG_PARAMS', - 'NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_RW_REG_PARAMS', 'NV2080_CTRL_I2C_VERSION_0', - 'NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS', - 'NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_WRITE_REG_PARAMS', - 'NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL', - 'NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BSP_CAPS', - 'NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS', - 'NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DEVICE_INFO', - 'NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS', - 'NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS', - 'NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_EDID_DATA', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3', - 'NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO', - 'NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT', - 'NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS', - 'NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS', - 'NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID', - 'NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS', - 'NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX', - 'NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE', - 'NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES', - 'NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES', - 'NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_INFO', - 'NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_MAX_ENGINES', - 'NV2080_CTRL_INTERNAL_GR_MAX_GPC', - 'NV2080_CTRL_INTERNAL_GR_MAX_SM', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS', - 'NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS', - 'NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS', - 'NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID', - 'NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_INTERNAL_MEMDESC_INFO', - 'NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE', - 'NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MSENC_CAPS', - 'NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN', - 'NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NV_RANGE', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO', - 'NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS', - 'NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_CAPS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER', - 'NV2080_CTRL_INTERNAL_STATIC_GR_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES', - 'NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO', - 'NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS', - 'NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS', - 'NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES', - 'NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS', - 'NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_KGR_MAX_BUFFER_PTES', 'NV2080_CTRL_LPWR', - 'NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE', - 'NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE', - 'NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS', - 'NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS', - 'NV2080_CTRL_LPWR_DIFR_SUPPORTED', - 'NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_LPWR_LEGACY_PRIVILEGED', 'NV2080_CTRL_MAX_CES', - 'NV2080_CTRL_MAX_GPC_COUNT', 'NV2080_CTRL_MAX_GRCES', - 'NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN', - 'NV2080_CTRL_MAX_PCES', 'NV2080_CTRL_MAX_PHYSICAL_BRIDGE', - 'NV2080_CTRL_MAX_VMMU_SEGMENTS', 'NV2080_CTRL_MC', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R', - 'NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS', - 'NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_ENGINE_ID_ALL', - 'NV2080_CTRL_MC_ENGINE_ID_GRAPHICS', - 'NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY', - 'NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS', - 'NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS', - 'NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS', - 'NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_STATIC_INTR_ENTRY', - 'NV2080_CTRL_MEMMGR_MEMORY_OP', - 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', - 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', - 'NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX', 'NV2080_CTRL_NNE', - 'NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO', - 'NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES', - 'NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO', - 'NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON', - 'NV2080_CTRL_NOCAT_TAG_CLEAR_NO', - 'NV2080_CTRL_NOCAT_TAG_CLEAR_YES', - 'NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET', - 'NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP', - 'NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET', - 'NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY', - 'NV2080_CTRL_NOCAT_TDR_TYPE_NONE', - 'NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL', - 'NV2080_CTRL_NOCAT_TDR_TYPE_TEST', - 'NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET', 'NV2080_CTRL_NVD', - 'NV2080_CTRL_NVD_GET_DUMP_PARAMS', - 'NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS', - 'NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS', - 'NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVENC_SW_SESSION_INFO', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED', - 'NV2080_CTRL_NVFBC_SW_SESSION_INFO', 'NV2080_CTRL_NVIF', - 'NV2080_CTRL_NVLINK', 'NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_CAPS_TBL_SIZE', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_COMMON_ERR_INFO', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_COUNTERS_MAX', - 'NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES', - 'NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY', - 'NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER', - 'NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_0', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_1', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_10', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_11', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_12', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_13', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_14', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_15', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_2', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_3', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_4', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_5', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_6', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_7', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_8', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_9', - 'NV2080_CTRL_NVLINK_COUNTER_INVALID', - 'NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY', - 'NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE', - 'NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LP_DL', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES', - 'NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS', - 'NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER', - 'NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR', - 'NV2080_CTRL_NVLINK_COUNTER_TL_RX0', - 'NV2080_CTRL_NVLINK_COUNTER_TL_RX1', - 'NV2080_CTRL_NVLINK_COUNTER_TL_TX0', - 'NV2080_CTRL_NVLINK_COUNTER_TL_TX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA', - 'NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW', - 'NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME', - 'NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS', - 'NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE', - 'NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS', - 'NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS', - 'NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_EOM_MEASUREMENT', - 'NV2080_CTRL_NVLINK_ERR_INFO', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES', - 'NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS', - 'NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS', - 'NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER', - 'NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE', - 'NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS', - 'NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS', - 'NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS', - 'NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS', - 'NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_L1_FORCE_CONFIG', - 'NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT', - 'NV2080_CTRL_NVLINK_LANE_ERROR', - 'NV2080_CTRL_NVLINK_LINK_ECC_ERROR', - 'NV2080_CTRL_NVLINK_LINK_STATUS_INFO', - 'NV2080_CTRL_NVLINK_LP_COUNTERS_DL', - 'NV2080_CTRL_NVLINK_MAX_ARR_SIZE', - 'NV2080_CTRL_NVLINK_MAX_IOCTRLS', 'NV2080_CTRL_NVLINK_MAX_LANES', - 'NV2080_CTRL_NVLINK_MAX_LINKS', - 'NV2080_CTRL_NVLINK_MAX_LINK_COUNT', - 'NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE', - 'NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES', - 'NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES', - 'NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO', - 'NV2080_CTRL_NVLINK_PORT_EVENT', - 'NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE', - 'NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS', - 'NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_POWER_STATE_L0', - 'NV2080_CTRL_NVLINK_POWER_STATE_L1', - 'NV2080_CTRL_NVLINK_POWER_STATE_L2', - 'NV2080_CTRL_NVLINK_POWER_STATE_L3', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_DATA', - 'NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS', - 'NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES', - 'NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS', - 'NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS', - 'NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX', - 'NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS', - 'NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS', - 'NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE', - 'NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN', - 'NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE', - 'NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE', - 'NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_PHY_GRS', - 'NV2080_CTRL_NVLINK_STATUS_PHY_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_PHY_NVHS', - 'NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING', - 'NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT', - 'NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE', - 'NV2080_CTRL_NVLINK_TL_INTEN_FALSE', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_TRUE', 'NV2080_CTRL_NVLINK_UNIT_DL', - 'NV2080_CTRL_NVLINK_UNIT_MIF_RX_0', - 'NV2080_CTRL_NVLINK_UNIT_MIF_TX_0', - 'NV2080_CTRL_NVLINK_UNIT_MINION', 'NV2080_CTRL_NVLINK_UNIT_TL', - 'NV2080_CTRL_NVLINK_UNIT_TLC_RX_0', - 'NV2080_CTRL_NVLINK_UNIT_TLC_RX_1', - 'NV2080_CTRL_NVLINK_UNIT_TLC_TX_0', - 'NV2080_CTRL_NVLINK_UPHY_CLN_CMD', 'NV2080_CTRL_OS_MACOS', - 'NV2080_CTRL_OS_UNIX', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS', - 'NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS', - 'NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS', - 'NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS', - 'NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_WINDOWS', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR', - 'NV2080_CTRL_PC_SAMPLING_MODE_DISABLED', - 'NV2080_CTRL_PC_SAMPLING_MODE_ENABLED', 'NV2080_CTRL_PERF', - 'NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS', - 'NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P0', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P1', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P2', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P3', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P4', - 'NV2080_CTRL_PERF_BOOST_DURATION_INFINITE', - 'NV2080_CTRL_PERF_BOOST_DURATION_MAX', - 'NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO', - 'NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES', - 'NV2080_CTRL_PERF_BOOST_PARAMS', - 'NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_CLK_MAX_DOMAINS', - 'NV2080_CTRL_PERF_GET_CLK_INFO', - 'NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS', - 'NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS', - 'NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE', - 'NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE', - 'NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE', - 'NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_PERF_LEGACY_PRIVILEGED', - 'NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS', - 'NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_POWER_SOURCE_AC', - 'NV2080_CTRL_PERF_POWER_SOURCE_BATTERY', - 'NV2080_CTRL_PERF_PSTATES_ALL', - 'NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED', - 'NV2080_CTRL_PERF_PSTATES_ID', 'NV2080_CTRL_PERF_PSTATES_MAX', - 'NV2080_CTRL_PERF_PSTATES_MIN', 'NV2080_CTRL_PERF_PSTATES_P0', - 'NV2080_CTRL_PERF_PSTATES_P1', 'NV2080_CTRL_PERF_PSTATES_P10', - 'NV2080_CTRL_PERF_PSTATES_P11', 'NV2080_CTRL_PERF_PSTATES_P12', - 'NV2080_CTRL_PERF_PSTATES_P13', 'NV2080_CTRL_PERF_PSTATES_P14', - 'NV2080_CTRL_PERF_PSTATES_P15', 'NV2080_CTRL_PERF_PSTATES_P2', - 'NV2080_CTRL_PERF_PSTATES_P3', 'NV2080_CTRL_PERF_PSTATES_P4', - 'NV2080_CTRL_PERF_PSTATES_P5', 'NV2080_CTRL_PERF_PSTATES_P6', - 'NV2080_CTRL_PERF_PSTATES_P7', 'NV2080_CTRL_PERF_PSTATES_P8', - 'NV2080_CTRL_PERF_PSTATES_P9', - 'NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY', - 'NV2080_CTRL_PERF_PSTATES_UNDEFINED', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 'NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE', - 'NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS', - 'NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS', - 'NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK', - 'NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE', - 'NV2080_CTRL_PERF_VIDEOEVENT_OFA_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP', - 'NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', - 'NV2080_CTRL_PERF_VPSTATE_RATED_TDP', - 'NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', - 'NV2080_CTRL_PEX_MAX_COUNTER_TYPES', 'NV2080_CTRL_PEX_MAX_LANES', - 'NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES', 'NV2080_CTRL_PMGR', - 'NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_PMGR_LEGACY_PRIVILEGED', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED', - 'NV2080_CTRL_PMGR_MODULE_INFO_PARAMS', - 'NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_POWER', 'NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_RC', 'NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE', - 'NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS', - 'NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_GET_ERROR_V2_PARAMS', - 'NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS', - 'NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_REG_OPS_ARRAY_MAX', 'NV2080_CTRL_RESERVED', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI', - 'NV2080_CTRL_SET_RC_INFO_PARAMS', - 'NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_SET_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_SMC_SUBSCRIPTION_INFO', 'NV2080_CTRL_SPI', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS', - 'NV2080_CTRL_THERMAL', - 'NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED', 'NV2080_CTRL_TIMER', - 'NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS', - 'NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS', - 'NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GET_TIME_PARAMS', - 'NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES', - 'NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE', - 'NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS', - 'NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL', - 'NV2080_CTRL_UCODE_FUZZER', - 'NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS', - 'NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VOLT', 'NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_VOLT_LEGACY_PRIVILEGED', - 'NV2080_CTRL_VPR_INFO_QUERY_TYPE', - 'NV2080_ENGINE_TYPE_ALLENGINES', 'NV2080_ENGINE_TYPE_BSP', - 'NV2080_ENGINE_TYPE_CIPHER', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9', - 'NV2080_ENGINE_TYPE_COPY0', 'NV2080_ENGINE_TYPE_COPY1', - 'NV2080_ENGINE_TYPE_COPY10', 'NV2080_ENGINE_TYPE_COPY11', - 'NV2080_ENGINE_TYPE_COPY12', 'NV2080_ENGINE_TYPE_COPY13', - 'NV2080_ENGINE_TYPE_COPY14', 'NV2080_ENGINE_TYPE_COPY15', - 'NV2080_ENGINE_TYPE_COPY16', 'NV2080_ENGINE_TYPE_COPY17', - 'NV2080_ENGINE_TYPE_COPY18', 'NV2080_ENGINE_TYPE_COPY19', - 'NV2080_ENGINE_TYPE_COPY2', 'NV2080_ENGINE_TYPE_COPY3', - 'NV2080_ENGINE_TYPE_COPY4', 'NV2080_ENGINE_TYPE_COPY5', - 'NV2080_ENGINE_TYPE_COPY6', 'NV2080_ENGINE_TYPE_COPY7', - 'NV2080_ENGINE_TYPE_COPY8', 'NV2080_ENGINE_TYPE_COPY9', - 'NV2080_ENGINE_TYPE_COPY_SIZE', 'NV2080_ENGINE_TYPE_DPU', - 'NV2080_ENGINE_TYPE_FBFLCN', 'NV2080_ENGINE_TYPE_GR0', - 'NV2080_ENGINE_TYPE_GR1', 'NV2080_ENGINE_TYPE_GR2', - 'NV2080_ENGINE_TYPE_GR3', 'NV2080_ENGINE_TYPE_GR4', - 'NV2080_ENGINE_TYPE_GR5', 'NV2080_ENGINE_TYPE_GR6', - 'NV2080_ENGINE_TYPE_GR7', 'NV2080_ENGINE_TYPE_GRAPHICS', - 'NV2080_ENGINE_TYPE_GR_SIZE', 'NV2080_ENGINE_TYPE_HOST', - 'NV2080_ENGINE_TYPE_LAST', 'NV2080_ENGINE_TYPE_ME', - 'NV2080_ENGINE_TYPE_MP', 'NV2080_ENGINE_TYPE_MPEG', - 'NV2080_ENGINE_TYPE_MSENC', 'NV2080_ENGINE_TYPE_NULL', - 'NV2080_ENGINE_TYPE_NVDEC0', 'NV2080_ENGINE_TYPE_NVDEC1', - 'NV2080_ENGINE_TYPE_NVDEC2', 'NV2080_ENGINE_TYPE_NVDEC3', - 'NV2080_ENGINE_TYPE_NVDEC4', 'NV2080_ENGINE_TYPE_NVDEC5', - 'NV2080_ENGINE_TYPE_NVDEC6', 'NV2080_ENGINE_TYPE_NVDEC7', - 'NV2080_ENGINE_TYPE_NVDEC_SIZE', 'NV2080_ENGINE_TYPE_NVENC0', - 'NV2080_ENGINE_TYPE_NVENC1', 'NV2080_ENGINE_TYPE_NVENC2', - 'NV2080_ENGINE_TYPE_NVENC3', 'NV2080_ENGINE_TYPE_NVENC_SIZE', - 'NV2080_ENGINE_TYPE_NVJPEG0', 'NV2080_ENGINE_TYPE_NVJPEG1', - 'NV2080_ENGINE_TYPE_NVJPEG2', 'NV2080_ENGINE_TYPE_NVJPEG3', - 'NV2080_ENGINE_TYPE_NVJPEG4', 'NV2080_ENGINE_TYPE_NVJPEG5', - 'NV2080_ENGINE_TYPE_NVJPEG6', 'NV2080_ENGINE_TYPE_NVJPEG7', - 'NV2080_ENGINE_TYPE_NVJPEG_SIZE', 'NV2080_ENGINE_TYPE_NVJPG', - 'NV2080_ENGINE_TYPE_OFA', 'NV2080_ENGINE_TYPE_OFA0', - 'NV2080_ENGINE_TYPE_OFA1', 'NV2080_ENGINE_TYPE_OFA_SIZE', - 'NV2080_ENGINE_TYPE_PMU', 'NV2080_ENGINE_TYPE_PPP', - 'NV2080_ENGINE_TYPE_SEC2', 'NV2080_ENGINE_TYPE_SW', - 'NV2080_ENGINE_TYPE_TSEC', 'NV2080_ENGINE_TYPE_VIC', - 'NV2080_ENGINE_TYPE_VP', 'NV2080_EVENT_DSTATE_PPC_D0', - 'NV2080_EVENT_DSTATE_PPC_D3', 'NV2080_EVENT_DSTATE_PPC_INVALID', - 'NV2080_EVENT_DSTATE_XUSB_D0', 'NV2080_EVENT_DSTATE_XUSB_D3', - 'NV2080_EVENT_DSTATE_XUSB_INVALID', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', - 'NV2080_EVENT_HDACODEC_DSTATE', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING', - 'NV2080_GC5_ENTRY_ABORTED', 'NV2080_GC5_EXIT_COMPLETE', - 'NV2080_GET_P2P_CAPS_UUID_LEN', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1', - 'NV2080_GPU_FABRIC_CLUSTER_UUID_LEN', 'NV2080_GPU_MAX_ENGINES', - 'NV2080_GPU_MAX_ENGINES_LIST_SIZE', 'NV2080_GPU_MAX_GID_LENGTH', - 'NV2080_GPU_MAX_MARKETING_NAME_LENGTH', - 'NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH', - 'NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH', - 'NV2080_GPU_MAX_NAME_STRING_LENGTH', - 'NV2080_GPU_MAX_OEM_INFO_LENGTH', - 'NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH', - 'NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH', - 'NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH', - 'NV2080_GPU_NVFBC_MAX_SESSION_COUNT', - 'NV2080_GSP_MAX_BUILD_VERSION_LENGTH', 'NV2080_GUEST_VM_INFO', - 'NV2080_HOST_VGPU_DEVICE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP', - 'NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE', - 'NV2080_INTR_CATEGORY', 'NV2080_INTR_CATEGORY_DEFAULT', - 'NV2080_INTR_CATEGORY_ENUM_COUNT', - 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', - 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', - 'NV2080_INTR_CATEGORY_RUNLIST', - 'NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', - 'NV2080_INTR_CATEGORY_SUBTREE_MAP', - 'NV2080_INTR_CATEGORY_UVM_OWNED', - 'NV2080_INTR_CATEGORY_UVM_SHARED', 'NV2080_INTR_TYPE_ACCESS_CNTR', - 'NV2080_INTR_TYPE_CPU_DOORBELL', 'NV2080_INTR_TYPE_GR0_FECS_LOG', - 'NV2080_INTR_TYPE_GR1_FECS_LOG', 'NV2080_INTR_TYPE_GR2_FECS_LOG', - 'NV2080_INTR_TYPE_GR3_FECS_LOG', 'NV2080_INTR_TYPE_GR4_FECS_LOG', - 'NV2080_INTR_TYPE_GR5_FECS_LOG', 'NV2080_INTR_TYPE_GR6_FECS_LOG', - 'NV2080_INTR_TYPE_GR7_FECS_LOG', 'NV2080_INTR_TYPE_INFO_FAULT', - 'NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT', - 'NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR', - 'NV2080_INTR_TYPE_NULL', 'NV2080_INTR_TYPE_REPLAYABLE_FAULT', - 'NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR', 'NV2080_INTR_TYPE_TMR', - 'NV2080_MAX_CHIP_SKU_LENGTH', 'NV2080_MAX_CTAGS_FOR_CBC_EVICTION', - 'NV2080_MAX_NUM_HEADS', 'NV2080_NOCAT_JOURNAL_ENTRY', - 'NV2080_NOCAT_JOURNAL_GPU_STATE', - 'NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS', - 'NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER', - 'NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS', - 'NV2080_NOCAT_JOURNAL_MAX_STR_LEN', - 'NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG', - 'NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS', - 'NV2080_NOCAT_JOURNAL_RECORD', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ANY', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_RC', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_TDR', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX', - 'NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT', - 'NV2080_NOTIFIERS_ACPI_NOTIFY', - 'NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST', - 'NV2080_NOTIFIERS_AUX_POWER_EVENT', - 'NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE', 'NV2080_NOTIFIERS_CE0', - 'NV2080_NOTIFIERS_CE1', 'NV2080_NOTIFIERS_CE10', - 'NV2080_NOTIFIERS_CE11', 'NV2080_NOTIFIERS_CE12', - 'NV2080_NOTIFIERS_CE13', 'NV2080_NOTIFIERS_CE14', - 'NV2080_NOTIFIERS_CE15', 'NV2080_NOTIFIERS_CE16', - 'NV2080_NOTIFIERS_CE17', 'NV2080_NOTIFIERS_CE18', - 'NV2080_NOTIFIERS_CE19', 'NV2080_NOTIFIERS_CE2', - 'NV2080_NOTIFIERS_CE3', 'NV2080_NOTIFIERS_CE4', - 'NV2080_NOTIFIERS_CE5', 'NV2080_NOTIFIERS_CE6', - 'NV2080_NOTIFIERS_CE7', 'NV2080_NOTIFIERS_CE8', - 'NV2080_NOTIFIERS_CE9', 'NV2080_NOTIFIERS_CLOCKS_CHANGE', - 'NV2080_NOTIFIERS_COOLER_DIAG_ZONE', - 'NV2080_NOTIFIERS_CTXSW_TIMEOUT', - 'NV2080_NOTIFIERS_CTXSW_UCODE_ERROR', 'NV2080_NOTIFIERS_DP_IRQ', - 'NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT', - 'NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE', - 'NV2080_NOTIFIERS_DSTATE_HDA', 'NV2080_NOTIFIERS_DSTATE_XUSB_PPC', - 'NV2080_NOTIFIERS_ECC_DBE', 'NV2080_NOTIFIERS_ECC_SBE', - 'NV2080_NOTIFIERS_ECC_SBE_STORM', 'NV2080_NOTIFIERS_EVENTBUFFER', - 'NV2080_NOTIFIERS_FECS_CTX_SWITCH', - 'NV2080_NOTIFIERS_FIFO_EVENT_MTHD', - 'NV2080_NOTIFIERS_FULL_SCREEN_CHANGE', - 'NV2080_NOTIFIERS_GC5_GPU_READY', - 'NV2080_NOTIFIERS_GC6_REFCOUNT_DEC', - 'NV2080_NOTIFIERS_GC6_REFCOUNT_INC', - 'NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPU_RECOVERY_ACTION', - 'NV2080_NOTIFIERS_GPU_UNAVAILABLE', 'NV2080_NOTIFIERS_GR0', - 'NV2080_NOTIFIERS_GR1', 'NV2080_NOTIFIERS_GR2', - 'NV2080_NOTIFIERS_GR3', 'NV2080_NOTIFIERS_GR4', - 'NV2080_NOTIFIERS_GR5', 'NV2080_NOTIFIERS_GR6', - 'NV2080_NOTIFIERS_GR7', 'NV2080_NOTIFIERS_GRAPHICS', - 'NV2080_NOTIFIERS_GR_DEBUG_INTR', - 'NV2080_NOTIFIERS_GSP_PERF_TRACE', - 'NV2080_NOTIFIERS_HDCP_STATUS_CHANGE', - 'NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST', - 'NV2080_NOTIFIERS_HOTPLUG', - 'NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE', - 'NV2080_NOTIFIERS_INBAND_RESPONSE', - 'NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST', - 'NV2080_NOTIFIERS_MAXCOUNT', 'NV2080_NOTIFIERS_MSENC', - 'NV2080_NOTIFIERS_NVDEC0', 'NV2080_NOTIFIERS_NVDEC1', - 'NV2080_NOTIFIERS_NVDEC2', 'NV2080_NOTIFIERS_NVDEC3', - 'NV2080_NOTIFIERS_NVDEC4', 'NV2080_NOTIFIERS_NVDEC5', - 'NV2080_NOTIFIERS_NVDEC6', 'NV2080_NOTIFIERS_NVDEC7', - 'NV2080_NOTIFIERS_NVENC0', 'NV2080_NOTIFIERS_NVENC1', - 'NV2080_NOTIFIERS_NVENC2', 'NV2080_NOTIFIERS_NVENC3', - 'NV2080_NOTIFIERS_NVJPEG0', 'NV2080_NOTIFIERS_NVJPEG1', - 'NV2080_NOTIFIERS_NVJPEG2', 'NV2080_NOTIFIERS_NVJPEG3', - 'NV2080_NOTIFIERS_NVJPEG4', 'NV2080_NOTIFIERS_NVJPEG5', - 'NV2080_NOTIFIERS_NVJPEG6', 'NV2080_NOTIFIERS_NVJPEG7', - 'NV2080_NOTIFIERS_NVJPG', 'NV2080_NOTIFIERS_NVLINK_ERROR_FATAL', - 'NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED', - 'NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN', - 'NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP', - 'NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR', - 'NV2080_NOTIFIERS_NVPCF_EVENTS', - 'NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT', - 'NV2080_NOTIFIERS_OFA', 'NV2080_NOTIFIERS_OFA0', - 'NV2080_NOTIFIERS_OFA1', 'NV2080_NOTIFIERS_PDEC', - 'NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT', - 'NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE', - 'NV2080_NOTIFIERS_PMU_COMMAND', 'NV2080_NOTIFIERS_PMU_EVENT', - 'NV2080_NOTIFIERS_POISON_ERROR_FATAL', - 'NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL', - 'NV2080_NOTIFIERS_POWER_CONNECTOR', - 'NV2080_NOTIFIERS_POWER_EVENT', 'NV2080_NOTIFIERS_POWER_RESUME', - 'NV2080_NOTIFIERS_POWER_SUSPEND', 'NV2080_NOTIFIERS_PPP', - 'NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT', - 'NV2080_NOTIFIERS_PRIV_RING_HANG', - 'NV2080_NOTIFIERS_PSTATE_CHANGE', 'NV2080_NOTIFIERS_RC_ERROR', - 'NV2080_NOTIFIERS_RESERVED122', 'NV2080_NOTIFIERS_RESERVED_186', - 'NV2080_NOTIFIERS_RUNLIST_ACQUIRE', - 'NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE', - 'NV2080_NOTIFIERS_SEC2', 'NV2080_NOTIFIERS_SEC_FAULT_ERROR', - 'NV2080_NOTIFIERS_SMC_CONFIG_UPDATE', - 'NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION', - 'NV2080_NOTIFIERS_SW', 'NV2080_NOTIFIERS_THERMAL_DIAG_ZONE', - 'NV2080_NOTIFIERS_THERMAL_HW', 'NV2080_NOTIFIERS_THERMAL_SW', - 'NV2080_NOTIFIERS_TIMER', 'NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE', - 'NV2080_NOTIFIERS_UCODE_RESET', 'NV2080_NOTIFIERS_UNUSED_0', - 'NV2080_NOTIFIERS_UNUSED_1', - 'NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD', - 'NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE', - 'NV2080_NOTIFIERS_VLD', 'NV2080_NOTIFIERS_VRR_SET_TIMEOUT', - 'NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE', - 'NV2080_NOTIFIERS_XUSB_PPC_CONNECTED', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS', - 'NV2080_RAFTS_FLOORSWEEP_INFO', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', - 'NV2080_SET_P2P_MAPPING_UUID_LEN', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS', - 'NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC', 'NV2080_TYPEDEF', - 'NV2080_VF_MSIX_CAPS', 'NV2080_VGPU_FB_USAGE', - 'NV2080_VGPU_GUEST', 'NV2081_BINAPI', 'NV2082_BINAPI_PRIVILEGED', - 'NV20_SUBDEVICE_0', 'NV20_SUBDEVICE_DIAG', 'NV30_GSYNC', - 'NV40_DEBUG_BUFFER', 'NV40_I2C', 'NV4_SOFTWARE_TEST', - 'NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO', - 'NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES', - 'NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS', - 'NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS', - 'NV50_CHANNEL_GPFIFO', 'NV50_DEFERRED_API_CLASS', - 'NV50_MEMORY_VIRTUAL', 'NV50_P2P', 'NV50_THIRD_PARTY_P2P', - 'NV83DE_ALLOC_PARAMETERS', 'NV83DE_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES', - 'NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE', - 'NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS', - 'NV83DE_CTRL_CMD_DEBUG_GET_HANDLES', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS', - 'NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES', - 'NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_READ_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO', - 'NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE', - 'NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS', - 'NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS', - 'NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT', - 'NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC', - 'NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY', - 'NV83DE_CTRL_CMD_GET_MAPPINGS', 'NV83DE_CTRL_CMD_NULL', - 'NV83DE_CTRL_CMD_READ_SURFACE', - 'NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE', - 'NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE', - 'NV83DE_CTRL_CMD_WRITE_SURFACE', 'NV83DE_CTRL_DEBUG', - 'NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY', - 'NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_ACCESS_OP', - 'NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS', - 'NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS', - 'NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS', - 'NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS', - 'NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP', - 'NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS', - 'NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL', - 'NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP', - 'NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING', - 'NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS', - 'NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_FIFO', 'NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS', - 'NV83DE_CTRL_GR', 'NV83DE_CTRL_INTERNAL', 'NV83DE_CTRL_RESERVED', - 'NV83DE_MMU_FAULT_INFO', 'NV83DE_SM_ERROR_STATE_REGISTERS', - 'NV9010_VBLANK_CALLBACK', 'NVA06C_CTRL_BIND_PARAMS', - 'NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID', 'NVA06C_CTRL_CMD_BIND', - 'NVA06C_CTRL_CMD_GET_INFO', - 'NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL', - 'NVA06C_CTRL_CMD_GET_TIMESLICE', - 'NVA06C_CTRL_CMD_GPFIFO_SCHEDULE', - 'NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE', - 'NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS', - 'NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE', - 'NVA06C_CTRL_CMD_MAKE_REALTIME', 'NVA06C_CTRL_CMD_NULL', - 'NVA06C_CTRL_CMD_PREEMPT', - 'NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US', - 'NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE', - 'NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL', - 'NVA06C_CTRL_CMD_SET_TIMESLICE', 'NVA06C_CTRL_GET_INFO_PARAMS', - 'NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS', - 'NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GPFIFO', 'NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS', - 'NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_LOW', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS', 'NVA06C_CTRL_INTERNAL', - 'NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS', - 'NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_MAKE_REALTIME_PARAMS', - 'NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PREEMPT_PARAMS', - 'NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', - 'NVA06C_CTRL_RESERVED', 'NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS', - 'NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_SET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_TIMESLICE_PARAMS', 'NVA081_VGPU_CONFIG', - 'NVA084_KERNEL_HOST_VGPU_DEVICE', 'NVAL_MAP_DIRECTION_DOWN', - 'NVAL_MAP_DIRECTION_UP', 'NVAL_MAX_BANKS', 'NVB4B7_VIDEO_ENCODER', - 'NVB8B0_VIDEO_DECODER', 'NVB8D1_VIDEO_NVJPG', 'NVB8FA_VIDEO_OFA', - 'NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NVC36F_CTRL_CMD_EVENT_SET_TRIGGER', - 'NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX', - 'NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER', - 'NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 'NVC36F_CTRL_CMD_NULL', 'NVC36F_CTRL_EVENT', 'NVC36F_CTRL_GPFIFO', - 'NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS', - 'NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS', - 'NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_INTERNAL', - 'NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_RESERVED', 'NVC371_DISP_SF_USER', - 'NVC372_DISPLAY_SW', 'NVC4B0_VIDEO_DECODER', - 'NVC4B7_VIDEO_ENCODER', 'NVC4D1_VIDEO_NVJPG', - 'NVC56F_CLEAR_FAULTED', 'NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED', - 'NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED', - 'NVC56F_DMA_ENDSEG_OPCODE_VALUE', 'NVC56F_DMA_IMMD_OPCODE_VALUE', - 'NVC56F_DMA_INCR_OPCODE_VALUE', 'NVC56F_DMA_NONINCR_OPCODE_VALUE', - 'NVC56F_DMA_NOP', 'NVC56F_DMA_ONEINCR_OPCODE_VALUE', - 'NVC56F_DMA_OPCODE3_NONE', 'NVC56F_DMA_OPCODE_METHOD', - 'NVC56F_DMA_OPCODE_NONINC_METHOD', - 'NVC56F_DMA_SEC_OP_END_PB_SEGMENT', - 'NVC56F_DMA_SEC_OP_GRP0_USE_TERT', - 'NVC56F_DMA_SEC_OP_GRP2_USE_TERT', - 'NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD', - 'NVC56F_DMA_SEC_OP_INC_METHOD', - 'NVC56F_DMA_SEC_OP_NON_INC_METHOD', 'NVC56F_DMA_SEC_OP_ONE_INC', - 'NVC56F_DMA_SEC_OP_RESERVED6', - 'NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE', - 'NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE', - 'NVC56F_DMA_TERT_OP_GRP0_INC_METHOD', - 'NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD', - 'NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE', 'NVC56F_FB_FLUSH', - 'NVC56F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC56F_GP_ENTRY1_LEVEL_MAIN', - 'NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC56F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC56F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC56F_GP_ENTRY1_OPCODE_NOP', - 'NVC56F_GP_ENTRY1_OPCODE_PB_CRC', 'NVC56F_GP_ENTRY1_SYNC_PROCEED', - 'NVC56F_GP_ENTRY1_SYNC_WAIT', 'NVC56F_GP_ENTRY__SIZE', - 'NVC56F_ILLEGAL', 'NVC56F_MEM_OP_A', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN', 'NVC56F_MEM_OP_B', - 'NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES', - 'NVC56F_MEM_OP_C', 'NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR', - 'NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL', - 'NVC56F_MEM_OP_D', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED', - 'NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR', - 'NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS', - 'NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY', - 'NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS', - 'NVC56F_MEM_OP_D_OPERATION_MEMBAR', - 'NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED', - 'NVC56F_NON_STALL_INTERRUPT', 'NVC56F_NOP', - 'NVC56F_NUMBER_OF_SUBCHANNELS', 'NVC56F_SEMAPHOREA', - 'NVC56F_SEMAPHOREB', 'NVC56F_SEMAPHOREC', 'NVC56F_SEMAPHORED', - 'NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED', - 'NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED', - 'NVC56F_SEMAPHORED_FORMAT_SIGNED', - 'NVC56F_SEMAPHORED_FORMAT_UNSIGNED', - 'NVC56F_SEMAPHORED_OPERATION_ACQUIRE', - 'NVC56F_SEMAPHORED_OPERATION_ACQ_AND', - 'NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ', - 'NVC56F_SEMAPHORED_OPERATION_REDUCTION', - 'NVC56F_SEMAPHORED_OPERATION_RELEASE', - 'NVC56F_SEMAPHORED_REDUCTION_ADD', - 'NVC56F_SEMAPHORED_REDUCTION_AND', - 'NVC56F_SEMAPHORED_REDUCTION_DEC', - 'NVC56F_SEMAPHORED_REDUCTION_INC', - 'NVC56F_SEMAPHORED_REDUCTION_MAX', - 'NVC56F_SEMAPHORED_REDUCTION_MIN', - 'NVC56F_SEMAPHORED_REDUCTION_OR', - 'NVC56F_SEMAPHORED_REDUCTION_XOR', - 'NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE', - 'NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE', - 'NVC56F_SEMAPHORED_RELEASE_WFI_DIS', - 'NVC56F_SEMAPHORED_RELEASE_WFI_EN', 'NVC56F_SEM_ADDR_HI', - 'NVC56F_SEM_ADDR_LO', 'NVC56F_SEM_EXECUTE', - 'NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS', - 'NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ', - 'NVC56F_SEM_EXECUTE_OPERATION_REDUCTION', - 'NVC56F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT', - 'NVC56F_SEM_EXECUTE_REDUCTION_DEC', - 'NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED', - 'NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED', - 'NVC56F_SEM_EXECUTE_REDUCTION_IADD', - 'NVC56F_SEM_EXECUTE_REDUCTION_IAND', - 'NVC56F_SEM_EXECUTE_REDUCTION_IMAX', - 'NVC56F_SEM_EXECUTE_REDUCTION_IMIN', - 'NVC56F_SEM_EXECUTE_REDUCTION_INC', - 'NVC56F_SEM_EXECUTE_REDUCTION_IOR', - 'NVC56F_SEM_EXECUTE_REDUCTION_IXOR', - 'NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS', - 'NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN', - 'NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS', - 'NVC56F_SEM_EXECUTE_RELEASE_WFI_EN', 'NVC56F_SEM_PAYLOAD_HI', - 'NVC56F_SEM_PAYLOAD_LO', 'NVC56F_SET_OBJECT', - 'NVC56F_SET_OBJECT_ENGINE_SW', 'NVC56F_SET_REFERENCE', - 'NVC56F_WFI', 'NVC56F_WFI_SCOPE_ALL', - 'NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE', - 'NVC56F_WFI_SCOPE_CURRENT_VEID', 'NVC56F_YIELD', - 'NVC56F_YIELD_OP_NOP', 'NVC56F_YIELD_OP_TSG', 'NVC570_DISPLAY', - 'NVC573_DISP_CAPABILITIES', 'NVC57A_CURSOR_IMM_CHANNEL_PIO', - 'NVC57B_WINDOW_IMM_CHANNEL_DMA', 'NVC57D_CORE_CHANNEL_DMA', - 'NVC57E_WINDOW_CHANNEL_DMA', 'NVC670_DISPLAY', - 'NVC671_DISP_SF_USER', 'NVC673_DISP_CAPABILITIES', - 'NVC67A_CURSOR_IMM_CHANNEL_PIO', 'NVC67B_WINDOW_IMM_CHANNEL_DMA', - 'NVC67D_CORE_CHANNEL_DMA', 'NVC67E_WINDOW_CHANNEL_DMA', - 'NVC6B0_VIDEO_DECODER', 'NVC6B5_DST_ORIGIN_X', - 'NVC6B5_DST_ORIGIN_Y', 'NVC6B5_LAUNCH_DMA', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED', - 'NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE', - 'NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE', - 'NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL', - 'NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL', - 'NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL', - 'NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS', - 'NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING', - 'NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH', - 'NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL', - 'NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL', - 'NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE', - 'NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID', 'NVC6B5_LINE_COUNT', - 'NVC6B5_LINE_LENGTH_IN', 'NVC6B5_NOP', 'NVC6B5_OFFSET_IN_LOWER', - 'NVC6B5_OFFSET_IN_UPPER', 'NVC6B5_OFFSET_OUT_LOWER', - 'NVC6B5_OFFSET_OUT_UPPER', 'NVC6B5_PITCH_IN', 'NVC6B5_PITCH_OUT', - 'NVC6B5_PM_TRIGGER', 'NVC6B5_PM_TRIGGER_END', - 'NVC6B5_SET_DST_BLOCK_SIZE', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6B5_SET_DST_DEPTH', - 'NVC6B5_SET_DST_HEIGHT', 'NVC6B5_SET_DST_LAYER', - 'NVC6B5_SET_DST_ORIGIN', 'NVC6B5_SET_DST_PHYS_MODE', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM', 'NVC6B5_SET_DST_WIDTH', - 'NVC6B5_SET_REMAP_COMPONENTS', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO', - 'NVC6B5_SET_REMAP_CONST_A', 'NVC6B5_SET_REMAP_CONST_B', - 'NVC6B5_SET_RENDER_ENABLE_A', 'NVC6B5_SET_RENDER_ENABLE_B', - 'NVC6B5_SET_RENDER_ENABLE_C', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE', 'NVC6B5_SET_SEMAPHORE_A', - 'NVC6B5_SET_SEMAPHORE_B', 'NVC6B5_SET_SEMAPHORE_PAYLOAD', - 'NVC6B5_SET_SRC_BLOCK_SIZE', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6B5_SET_SRC_DEPTH', - 'NVC6B5_SET_SRC_HEIGHT', 'NVC6B5_SET_SRC_LAYER', - 'NVC6B5_SET_SRC_ORIGIN', 'NVC6B5_SET_SRC_PHYS_MODE', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM', 'NVC6B5_SET_SRC_WIDTH', - 'NVC6B5_SRC_ORIGIN_X', 'NVC6B5_SRC_ORIGIN_Y', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE', - 'NVC6C0_CHECK_COMPUTE_CLASS_VERSION', 'NVC6C0_CHECK_QMD_VERSION', - 'NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER', - 'NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER', - 'NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN', - 'NVC6C0_FE_ATOMIC_SEQUENCE_END', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_INVALIDATE_SHADER_CACHES', - 'NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE', - 'NVC6C0_INVALIDATE_SKED_CACHES', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_LAUNCH_DMA', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE', - 'NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT', - 'NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR', - 'NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS', - 'NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD', - 'NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE', - 'NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE', 'NVC6C0_LINE_COUNT', - 'NVC6C0_LINE_LENGTH_IN', 'NVC6C0_LOAD_INLINE_DATA', - 'NVC6C0_NOTIFY', 'NVC6C0_NOTIFY_TYPE_WRITE_ONLY', - 'NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN', 'NVC6C0_NO_OPERATION', - 'NVC6C0_OFFSET_OUT', 'NVC6C0_OFFSET_OUT_UPPER', - 'NVC6C0_PERFMON_TRANSFER', 'NVC6C0_PIPE_NOP', 'NVC6C0_PITCH_OUT', - 'NVC6C0_PM_TRIGGER', 'NVC6C0_PM_TRIGGER_WFI', - 'NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE', - 'NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVC6C0_QMDV02_03_IS_QUEUE_FALSE', - 'NVC6C0_QMDV02_03_IS_QUEUE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE', - 'NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE', - 'NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY', - 'NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE', - 'NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE', - 'NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE', - 'NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE', - 'NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE', - 'NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE', - 'NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE', - 'NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE', - 'NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE', - 'NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE', - 'NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE', - 'NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVC6C0_QMDV02_04_IS_QUEUE_FALSE', - 'NVC6C0_QMDV02_04_IS_QUEUE_TRUE', - 'NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE', - 'NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE', - 'NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY', - 'NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE', - 'NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE', - 'NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE', - 'NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE', - 'NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE', - 'NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE', - 'NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE', - 'NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE', - 'NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE', - 'NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE', - 'NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE', - 'NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE', - 'NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE', - 'NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVC6C0_QMDV03_00_IS_QUEUE_FALSE', - 'NVC6C0_QMDV03_00_IS_QUEUE_TRUE', - 'NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP', - 'NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE', - 'NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP', - 'NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE', - 'NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP', - 'NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE', - 'NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP', - 'NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE', - 'NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP', - 'NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE', - 'NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP', - 'NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE', - 'NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE', - 'NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE', - 'NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY', - 'NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE', - 'NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE', - 'NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE', - 'NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE', - 'NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE', - 'NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE', - 'NVC6C0_SCG_HYSTERESIS_CONTROL', - 'NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE', - 'NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE', - 'NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE', - 'NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE', - 'NVC6C0_SEND_GO_IDLE', 'NVC6C0_SEND_PCAS_A', 'NVC6C0_SEND_PCAS_B', - 'NVC6C0_SEND_SIGNALING_PCAS2_B', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS_B', - 'NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE', - 'NVC6C0_SET_BINDLESS_TEXTURE', 'NVC6C0_SET_COMPUTE_CLASS_VERSION', - 'NVC6C0_SET_CWD_REF_COUNTER', 'NVC6C0_SET_CWD_SLOT_COUNT', - 'NVC6C0_SET_DST_BLOCK_SIZE', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6C0_SET_DST_DEPTH', - 'NVC6C0_SET_DST_HEIGHT', 'NVC6C0_SET_DST_LAYER', - 'NVC6C0_SET_DST_ORIGIN_BYTES_X', - 'NVC6C0_SET_DST_ORIGIN_SAMPLES_Y', 'NVC6C0_SET_DST_WIDTH', - 'NVC6C0_SET_FALCON00', 'NVC6C0_SET_FALCON01', - 'NVC6C0_SET_FALCON02', 'NVC6C0_SET_FALCON03', - 'NVC6C0_SET_FALCON04', 'NVC6C0_SET_FALCON05', - 'NVC6C0_SET_FALCON06', 'NVC6C0_SET_FALCON07', - 'NVC6C0_SET_FALCON08', 'NVC6C0_SET_FALCON09', - 'NVC6C0_SET_FALCON10', 'NVC6C0_SET_FALCON11', - 'NVC6C0_SET_FALCON12', 'NVC6C0_SET_FALCON13', - 'NVC6C0_SET_FALCON14', 'NVC6C0_SET_FALCON15', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_A', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_B', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE', - 'NVC6C0_SET_I2M_SEMAPHORE_A', 'NVC6C0_SET_I2M_SEMAPHORE_B', - 'NVC6C0_SET_I2M_SEMAPHORE_C', 'NVC6C0_SET_I2M_SPARE_NOOP00', - 'NVC6C0_SET_I2M_SPARE_NOOP01', 'NVC6C0_SET_I2M_SPARE_NOOP02', - 'NVC6C0_SET_I2M_SPARE_NOOP03', 'NVC6C0_SET_INLINE_QMD_ADDRESS_A', - 'NVC6C0_SET_INLINE_QMD_ADDRESS_B', - 'NVC6C0_SET_INSTRUMENTATION_METHOD_DATA', - 'NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER', 'NVC6C0_SET_NOTIFY_A', - 'NVC6C0_SET_NOTIFY_B', 'NVC6C0_SET_OBJECT', - 'NVC6C0_SET_QMD_VERSION', 'NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A', - 'NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE', - 'NVC6C0_SET_RENDER_ENABLE_A', 'NVC6C0_SET_RENDER_ENABLE_B', - 'NVC6C0_SET_RENDER_ENABLE_C', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE', - 'NVC6C0_SET_REPORT_SEMAPHORE_A', 'NVC6C0_SET_REPORT_SEMAPHORE_B', - 'NVC6C0_SET_REPORT_SEMAPHORE_C', 'NVC6C0_SET_REPORT_SEMAPHORE_D', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_SET_RESERVED_SW_METHOD00', - 'NVC6C0_SET_RESERVED_SW_METHOD01', - 'NVC6C0_SET_RESERVED_SW_METHOD02', - 'NVC6C0_SET_RESERVED_SW_METHOD03', - 'NVC6C0_SET_RESERVED_SW_METHOD04', - 'NVC6C0_SET_RESERVED_SW_METHOD05', - 'NVC6C0_SET_RESERVED_SW_METHOD06', - 'NVC6C0_SET_RESERVED_SW_METHOD07', - 'NVC6C0_SET_RESERVED_SW_METHOD08', - 'NVC6C0_SET_RESERVED_SW_METHOD09', - 'NVC6C0_SET_RESERVED_SW_METHOD10', - 'NVC6C0_SET_RESERVED_SW_METHOD11', - 'NVC6C0_SET_RESERVED_SW_METHOD12', - 'NVC6C0_SET_RESERVED_SW_METHOD13', - 'NVC6C0_SET_RESERVED_SW_METHOD14', - 'NVC6C0_SET_RESERVED_SW_METHOD15', 'NVC6C0_SET_SCG_CONTROL', - 'NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE', - 'NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE', - 'NVC6C0_SET_SHADER_CACHE_CONTROL', - 'NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE', - 'NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE', - 'NVC6C0_SET_SHADER_EXCEPTIONS', - 'NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE', - 'NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_B', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL', - 'NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A', - 'NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B', - 'NVC6C0_SET_SKED_CACHE_CONTROL', - 'NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE', - 'NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE', - 'NVC6C0_SET_SM_SCG_CONTROL', - 'NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE', - 'NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE', - 'NVC6C0_SET_SM_TIMEOUT_INTERVAL', 'NVC6C0_SET_SPARE00', - 'NVC6C0_SET_SPARE01', 'NVC6C0_SET_SPARE02', 'NVC6C0_SET_SPARE03', - 'NVC6C0_SET_SPA_VERSION', 'NVC6C0_SET_TEX_HEADER_POOL_A', - 'NVC6C0_SET_TEX_HEADER_POOL_B', 'NVC6C0_SET_TEX_HEADER_POOL_C', - 'NVC6C0_SET_TEX_SAMPLER_POOL_A', 'NVC6C0_SET_TEX_SAMPLER_POOL_B', - 'NVC6C0_SET_TEX_SAMPLER_POOL_C', 'NVC6C0_SET_TRAP_HANDLER_A', - 'NVC6C0_SET_TRAP_HANDLER_B', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C', - 'NVC6C0_START_SHADER_PERFORMANCE_COUNTER', - 'NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER', 'NVC6C0_WAIT_FOR_IDLE', - 'NVC6FA_VIDEO_OFA', 'NVC770_DISPLAY', 'NVC771_DISP_SF_USER', - 'NVC773_DISP_CAPABILITIES', 'NVC77D_CORE_CHANNEL_DMA', - 'NVC77F_ANY_CHANNEL_DMA', 'NVC7B0_VIDEO_DECODER', - 'NVC7B7_VIDEO_ENCODER', 'NVC7FA_VIDEO_OFA', - 'NVC86F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC86F_GP_ENTRY1_LEVEL_MAIN', - 'NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC86F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC86F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC86F_GP_ENTRY1_OPCODE_NOP', - 'NVC86F_GP_ENTRY1_OPCODE_PB_CRC', - 'NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE', - 'NVC86F_GP_ENTRY1_SYNC_PROCEED', 'NVC86F_GP_ENTRY1_SYNC_WAIT', - 'NVC86F_GP_ENTRY__SIZE', 'NVC86F_MEM_OP_A', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN', 'NVC86F_MEM_OP_B', - 'NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES', - 'NVC86F_MEM_OP_C', 'NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR', - 'NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL', - 'NVC86F_MEM_OP_D', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED', - 'NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED', - 'NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP', - 'NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR', - 'NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS', - 'NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY', - 'NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS', - 'NVC86F_MEM_OP_D_OPERATION_MEMBAR', - 'NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION', - 'NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED', - 'NVC86F_SEM_ADDR_HI', 'NVC86F_SEM_ADDR_LO', 'NVC86F_SEM_EXECUTE', - 'NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC86F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS', 'NVC86F_SEM_PAYLOAD_HI', - 'NVC86F_SEM_PAYLOAD_LO', 'NVC86F_SET_OBJECT', 'NVC86F_WFI', - 'NVC86F_WFI_SCOPE_ALL', 'NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE', - 'NVC86F_WFI_SCOPE_CURRENT_VEID', - 'NVC96F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC96F_GP_ENTRY1_LEVEL_MAIN', - 'NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC96F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC96F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC96F_GP_ENTRY1_OPCODE_NOP', - 'NVC96F_GP_ENTRY1_OPCODE_PB_CRC', - 'NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE', - 'NVC96F_GP_ENTRY1_SYNC_PROCEED', 'NVC96F_GP_ENTRY1_SYNC_WAIT', - 'NVC96F_GP_ENTRY__SIZE', 'NVC96F_SEM_ADDR_HI', - 'NVC96F_SEM_ADDR_LO', 'NVC96F_SEM_EXECUTE', - 'NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC96F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS', 'NVC96F_SEM_PAYLOAD_HI', - 'NVC96F_SEM_PAYLOAD_LO', 'NVC96F_SET_OBJECT', 'NVC970_DISPLAY', - 'NVC971_DISP_SF_USER', 'NVC973_DISP_CAPABILITIES', - 'NVC97A_CURSOR_IMM_CHANNEL_PIO', 'NVC97B_WINDOW_IMM_CHANNEL_DMA', - 'NVC97D_CORE_CHANNEL_DMA', 'NVC97E_WINDOW_CHANNEL_DMA', - 'NVC9B0_VIDEO_DECODER', 'NVC9B5_DST_ORIGIN_X', - 'NVC9B5_DST_ORIGIN_Y', 'NVC9B5_LAUNCH_DMA', - 'NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED', - 'NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE', - 'NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE', - 'NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL', - 'NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL', - 'NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL', - 'NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING', - 'NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP', - 'NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH', - 'NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL', - 'NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL', - 'NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE', - 'NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID', 'NVC9B5_LINE_COUNT', - 'NVC9B5_LINE_LENGTH_IN', 'NVC9B5_NOP', 'NVC9B5_OFFSET_IN_LOWER', - 'NVC9B5_OFFSET_IN_UPPER', 'NVC9B5_OFFSET_OUT_LOWER', - 'NVC9B5_OFFSET_OUT_UPPER', 'NVC9B5_PITCH_IN', 'NVC9B5_PITCH_OUT', - 'NVC9B5_PM_TRIGGER', 'NVC9B5_PM_TRIGGER_END', - 'NVC9B5_RESERVED_SET_AESCOUNTER', - 'NVC9B5_SET_COMPRESSION_PARAMETERS', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS', - 'NVC9B5_SET_DECOMPRESS_CHECKSUM', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER', - 'NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER', - 'NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER', - 'NVC9B5_SET_DECRYPT_IV0', 'NVC9B5_SET_DECRYPT_IV1', - 'NVC9B5_SET_DECRYPT_IV2', 'NVC9B5_SET_DST_BLOCK_SIZE', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC9B5_SET_DST_DEPTH', - 'NVC9B5_SET_DST_HEIGHT', 'NVC9B5_SET_DST_LAYER', - 'NVC9B5_SET_DST_ORIGIN', 'NVC9B5_SET_DST_PHYS_MODE', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM', 'NVC9B5_SET_DST_WIDTH', - 'NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER', - 'NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER', - 'NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER', - 'NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE', - 'NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER', - 'NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER', - 'NVC9B5_SET_MONITORED_FENCE_TYPE', - 'NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE', - 'NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT', - 'NVC9B5_SET_REMAP_COMPONENTS', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO', - 'NVC9B5_SET_REMAP_CONST_A', 'NVC9B5_SET_REMAP_CONST_B', - 'NVC9B5_SET_RENDER_ENABLE_A', 'NVC9B5_SET_RENDER_ENABLE_B', - 'NVC9B5_SET_RENDER_ENABLE_C', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE', - 'NVC9B5_SET_SECURE_COPY_MODE', - 'NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT', - 'NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM', - 'NVC9B5_SET_SEMAPHORE_A', 'NVC9B5_SET_SEMAPHORE_B', - 'NVC9B5_SET_SEMAPHORE_PAYLOAD', - 'NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER', 'NVC9B5_SET_SRC_BLOCK_SIZE', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC9B5_SET_SRC_DEPTH', - 'NVC9B5_SET_SRC_HEIGHT', 'NVC9B5_SET_SRC_LAYER', - 'NVC9B5_SET_SRC_ORIGIN', 'NVC9B5_SET_SRC_PHYS_MODE', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM', 'NVC9B5_SET_SRC_WIDTH', - 'NVC9B5_SRC_ORIGIN_X', 'NVC9B5_SRC_ORIGIN_Y', - 'NVC9B7_VIDEO_ENCODER', 'NVC9D1_VIDEO_NVJPG', 'NVC9FA_VIDEO_OFA', - 'NVCA70_DISPLAY', 'NVCA71_DISP_SF_USER', - 'NVCA73_DISP_CAPABILITIES', 'NVCA7A_CURSOR_IMM_CHANNEL_PIO', - 'NVCA7B_WINDOW_IMM_CHANNEL_DMA', 'NVCA7D_CORE_CHANNEL_DMA', - 'NVCA7E_WINDOW_CHANNEL_DMA', 'NVCB33_CTRL_CONF_COMPUTE', - 'NVCB33_CTRL_RESERVED', 'NVCDB0_VIDEO_DECODER', - 'NVCDD1_VIDEO_NVJPG', 'NVCDFA_VIDEO_OFA', - 'NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32', - 'NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING', - 'NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE', - 'NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE', - 'NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE', - 'NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE', - 'NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE', - 'NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE', - 'NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE', - 'NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE', - 'NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL', - 'NVCEC0_QMDV04_01_QMD_TYPE_QUEUE', - 'NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE', - 'NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR', - 'NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR', - 'NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL', - 'NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT', - 'NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE', - 'NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL', - 'NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY', - 'NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE', - 'NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE', - 'NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE', - 'NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE', - 'NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE', - 'NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE', - 'NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32', - 'NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE', - 'NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE', - 'NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING', - 'NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE', - 'NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE', - 'NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE', - 'NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE', - 'NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE', - 'NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE', - 'NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE', - 'NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE', - 'NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE', - 'NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE', - 'NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE', - 'NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE', - 'NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE', - 'NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE', - 'NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE', - 'NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE', - 'NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE', - 'NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE', - 'NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA', - 'NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA', - 'NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA', - 'NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA', - 'NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL', - 'NVCEC0_QMDV05_00_QMD_TYPE_QUEUE', - 'NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE', - 'NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR', - 'NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR', - 'NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL', - 'NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT', - 'NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE', - 'NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL', - 'NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY', - 'NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE', - 'NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE', - 'NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE', - 'NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE', - 'NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE', - 'NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE', - 'NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE', - 'NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE', - 'NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32', - 'NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE', - 'NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE', - 'NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE', - 'NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE', - 'NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE', - 'NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE', - 'NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE', - 'NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE', - 'NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE', - 'NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE', - 'NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE', - 'NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE', - 'NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE', - 'NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE', - 'NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE', - 'NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE', - 'NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE', - 'NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL', - 'NVCEC0_QMDV05_01_QMD_TYPE_QUEUE', - 'NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL', - 'NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY', - 'NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE', - 'NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE', - 'NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE', - 'NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE', - 'NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE', - 'NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE', - 'NVCFB0_VIDEO_DECODER', 'NVCFB7_VIDEO_ENCODER', - 'NVCFD1_VIDEO_NVJPG', 'NVCFFA_VIDEO_OFA', 'NVENC_SW_SESSION', - 'NVFBC_SW_SESSION', 'NVLINK_EOM_CONTROL_CONFIG_EOM', - 'NVLINK_EOM_CONTROL_END_EOM', - 'NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', - 'NVLINK_EOM_CONTROL_START_EOM', 'NVOS00_PARAMETERS', - 'NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO', - 'NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES', - 'NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO', - 'NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES', 'NVOS02_FLAGS_ALLOC_NONE', - 'NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE', - 'NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO', - 'NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES', - 'NVOS02_FLAGS_COHERENCY_CACHED', - 'NVOS02_FLAGS_COHERENCY_UNCACHED', - 'NVOS02_FLAGS_COHERENCY_WRITE_BACK', - 'NVOS02_FLAGS_COHERENCY_WRITE_COMBINE', - 'NVOS02_FLAGS_COHERENCY_WRITE_PROTECT', - 'NVOS02_FLAGS_COHERENCY_WRITE_THROUGH', - 'NVOS02_FLAGS_GPU_CACHEABLE_NO', 'NVOS02_FLAGS_GPU_CACHEABLE_YES', - 'NVOS02_FLAGS_KERNEL_MAPPING_MAP', - 'NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP', 'NVOS02_FLAGS_LOCATION_PCI', - 'NVOS02_FLAGS_LOCATION_VIDMEM', 'NVOS02_FLAGS_MAPPING_DEFAULT', - 'NVOS02_FLAGS_MAPPING_NEVER_MAP', 'NVOS02_FLAGS_MAPPING_NO_MAP', - 'NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT', - 'NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED', - 'NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED', - 'NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT', - 'NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED', - 'NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS', - 'NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS', - 'NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE', - 'NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE', - 'NVOS02_PARAMETERS', 'NVOS03_FLAGS_ACCESS_READ_ONLY', - 'NVOS03_FLAGS_ACCESS_READ_WRITE', - 'NVOS03_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS03_FLAGS_CACHE_SNOOP_DISABLE', - 'NVOS03_FLAGS_CACHE_SNOOP_ENABLE', - 'NVOS03_FLAGS_GPU_MAPPABLE_DISABLE', - 'NVOS03_FLAGS_GPU_MAPPABLE_ENABLE', - 'NVOS03_FLAGS_HASH_TABLE_DISABLE', - 'NVOS03_FLAGS_HASH_TABLE_ENABLE', 'NVOS03_FLAGS_MAPPING_KERNEL', - 'NVOS03_FLAGS_MAPPING_NONE', 'NVOS03_FLAGS_PREALLOCATE_DISABLE', - 'NVOS03_FLAGS_PREALLOCATE_ENABLE', 'NVOS03_FLAGS_PTE_KIND_BL', - 'NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE', - 'NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE', - 'NVOS03_FLAGS_PTE_KIND_NONE', 'NVOS03_FLAGS_PTE_KIND_PITCH', - 'NVOS03_FLAGS_TYPE_NOTIFIER', 'NVOS04_FLAGS_CC_SECURE_FALSE', - 'NVOS04_FLAGS_CC_SECURE_TRUE', - 'NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE', - 'NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE', - 'NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE', - 'NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE', - 'NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE', - 'NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE', - 'NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE', - 'NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE', - 'NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE', - 'NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE', - 'NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE', - 'NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE', - 'NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL', - 'NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL', - 'NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL', - 'NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE', - 'NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE', - 'NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE', - 'NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE', - 'NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE', - 'NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE', - 'NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE', - 'NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE', - 'NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT', - 'NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE', - 'NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT', - 'NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE', - 'NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO', - 'NVOS04_FLAGS_MAP_CHANNEL_FALSE', 'NVOS04_FLAGS_MAP_CHANNEL_TRUE', - 'NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE', - 'NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE', - 'NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE', - 'NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE', - 'NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE', - 'NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE', - 'NVOS04_FLAGS_VPR_FALSE', 'NVOS04_FLAGS_VPR_TRUE', - 'NVOS05_PARAMETERS', 'NVOS10_EVENT_KERNEL_CALLBACK', - 'NVOS10_EVENT_KERNEL_CALLBACK_EX', 'NVOS20_COMMAND_STRING_PRINT', - 'NVOS20_COMMAND_unused0001', 'NVOS20_COMMAND_unused0002', - 'NVOS21_PARAMETERS', 'NVOS2C_PARAMETERS', - 'NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK', - 'NVOS30_FLAGS_BEHAVIOR_QUERY', 'NVOS30_FLAGS_BEHAVIOR_SLEEP', - 'NVOS30_FLAGS_BEHAVIOR_SPIN', 'NVOS30_FLAGS_CHANNEL_LIST', - 'NVOS30_FLAGS_CHANNEL_SINGLE', 'NVOS30_FLAGS_IDLE_ACTIVECHANNELS', - 'NVOS30_FLAGS_IDLE_ALL_ENGINES', - 'NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR', - 'NVOS30_FLAGS_IDLE_CACHE1', 'NVOS30_FLAGS_IDLE_CALLBACKS', - 'NVOS30_FLAGS_IDLE_CE0', 'NVOS30_FLAGS_IDLE_CE1', - 'NVOS30_FLAGS_IDLE_CE2', 'NVOS30_FLAGS_IDLE_CE3', - 'NVOS30_FLAGS_IDLE_CE4', 'NVOS30_FLAGS_IDLE_CE5', - 'NVOS30_FLAGS_IDLE_CIPHER_DMA', 'NVOS30_FLAGS_IDLE_GRAPHICS', - 'NVOS30_FLAGS_IDLE_MOTION_ESTIMATION', 'NVOS30_FLAGS_IDLE_MPEG', - 'NVOS30_FLAGS_IDLE_MSENC', 'NVOS30_FLAGS_IDLE_MSPDEC', - 'NVOS30_FLAGS_IDLE_MSPPP', 'NVOS30_FLAGS_IDLE_MSVLD', - 'NVOS30_FLAGS_IDLE_NVDEC0', 'NVOS30_FLAGS_IDLE_NVDEC1', - 'NVOS30_FLAGS_IDLE_NVDEC2', 'NVOS30_FLAGS_IDLE_NVENC0', - 'NVOS30_FLAGS_IDLE_NVENC1', 'NVOS30_FLAGS_IDLE_NVENC2', - 'NVOS30_FLAGS_IDLE_NVJPG', 'NVOS30_FLAGS_IDLE_PUSH_BUFFER', - 'NVOS30_FLAGS_IDLE_SEC', 'NVOS30_FLAGS_IDLE_VIC', - 'NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR', - 'NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO', - 'NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES', 'NVOS30_PARAMETERS', - 'NVOS32_ALLOC_COMPR_COVG_BITS_1', - 'NVOS32_ALLOC_COMPR_COVG_BITS_2', - 'NVOS32_ALLOC_COMPR_COVG_BITS_4', - 'NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT', - 'NVOS32_ALLOC_COMPR_COVG_SCALE', - 'NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF', - 'NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE', - 'NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT', - 'NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED', - 'NVOS32_ALLOC_FLAGS_BANK_FORCE', - 'NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN', - 'NVOS32_ALLOC_FLAGS_BANK_GROW_UP', 'NVOS32_ALLOC_FLAGS_BANK_HINT', - 'NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY', - 'NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED', - 'NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE', - 'NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE', - 'NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE', - 'NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX', - 'NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN', - 'NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP', - 'NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC', - 'NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT', - 'NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP', - 'NVOS32_ALLOC_FLAGS_LAZY', 'NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED', - 'NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE', - 'NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE', - 'NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_ALLOC_FLAGS_NO_SCANOUT', - 'NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM', - 'NVOS32_ALLOC_FLAGS_PITCH_FORCE', - 'NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY', - 'NVOS32_ALLOC_FLAGS_PROTECTED', - 'NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD', - 'NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC', - 'NVOS32_ALLOC_FLAGS_SPARSE', - 'NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED', - 'NVOS32_ALLOC_FLAGS_USER_READ_ONLY', - 'NVOS32_ALLOC_FLAGS_USE_BEGIN_END', 'NVOS32_ALLOC_FLAGS_VIRTUAL', - 'NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY', 'NVOS32_ALLOC_FLAGS_WPR1', - 'NVOS32_ALLOC_FLAGS_WPR2', - 'NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED', - 'NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X', - 'NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC', - 'NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB', - 'NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW', - 'NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS', - 'NVOS32_ATTR2_32BIT_POINTER_DISABLE', - 'NVOS32_ATTR2_32BIT_POINTER_ENABLE', - 'NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO', - 'NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES', - 'NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT', - 'NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF', - 'NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON', - 'NVOS32_ATTR2_BLACKLIST_OFF', 'NVOS32_ATTR2_BLACKLIST_ON', - 'NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO', - 'NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES', - 'NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT', - 'NVOS32_ATTR2_GPU_CACHEABLE_INVALID', - 'NVOS32_ATTR2_GPU_CACHEABLE_NO', 'NVOS32_ATTR2_GPU_CACHEABLE_YES', - 'NVOS32_ATTR2_INTERNAL_NO', 'NVOS32_ATTR2_INTERNAL_YES', - 'NVOS32_ATTR2_ISO_NO', 'NVOS32_ATTR2_ISO_YES', - 'NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT', - 'NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED', - 'NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED', - 'NVOS32_ATTR2_NISO_DISPLAY_NO', 'NVOS32_ATTR2_NISO_DISPLAY_YES', - 'NVOS32_ATTR2_NONE', 'NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT', - 'NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO', - 'NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES', - 'NVOS32_ATTR2_PAGE_OFFLINING_OFF', - 'NVOS32_ATTR2_PAGE_OFFLINING_ON', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT', - 'NVOS32_ATTR2_PREFER_2C_NO', 'NVOS32_ATTR2_PREFER_2C_YES', - 'NVOS32_ATTR2_PRIORITY_DEFAULT', 'NVOS32_ATTR2_PRIORITY_HIGH', - 'NVOS32_ATTR2_PRIORITY_LOW', - 'NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY', - 'NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE', - 'NVOS32_ATTR2_PROTECTION_USER_READ_ONLY', - 'NVOS32_ATTR2_PROTECTION_USER_READ_WRITE', - 'NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE', - 'NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE', - 'NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT', - 'NVOS32_ATTR2_SMMU_ON_GPU_DISABLE', - 'NVOS32_ATTR2_SMMU_ON_GPU_ENABLE', 'NVOS32_ATTR2_USE_EGM_FALSE', - 'NVOS32_ATTR2_USE_EGM_TRUE', - 'NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE', - 'NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE', - 'NVOS32_ATTR2_ZBC_DEFAULT', 'NVOS32_ATTR2_ZBC_INVALID', - 'NVOS32_ATTR2_ZBC_PREFER_NO_ZBC', 'NVOS32_ATTR2_ZBC_PREFER_ZBC', - 'NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC', - 'NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO', - 'NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES', - 'NVOS32_ATTR_AA_SAMPLES_1', 'NVOS32_ATTR_AA_SAMPLES_16', - 'NVOS32_ATTR_AA_SAMPLES_2', 'NVOS32_ATTR_AA_SAMPLES_4', - 'NVOS32_ATTR_AA_SAMPLES_4_ROTATED', - 'NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16', - 'NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8', 'NVOS32_ATTR_AA_SAMPLES_6', - 'NVOS32_ATTR_AA_SAMPLES_8', 'NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16', - 'NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32', - 'NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO', - 'NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES', - 'NVOS32_ATTR_COHERENCY_CACHED', 'NVOS32_ATTR_COHERENCY_UNCACHED', - 'NVOS32_ATTR_COHERENCY_WRITE_BACK', - 'NVOS32_ATTR_COHERENCY_WRITE_COMBINE', - 'NVOS32_ATTR_COHERENCY_WRITE_PROTECT', - 'NVOS32_ATTR_COHERENCY_WRITE_THROUGH', - 'NVOS32_ATTR_COLOR_PACKING_A8R8G8B8', - 'NVOS32_ATTR_COLOR_PACKING_X8R8G8B8', 'NVOS32_ATTR_COMPR_ANY', - 'NVOS32_ATTR_COMPR_COVG_DEFAULT', - 'NVOS32_ATTR_COMPR_COVG_PROVIDED', - 'NVOS32_ATTR_COMPR_DISABLE_PLC_ANY', 'NVOS32_ATTR_COMPR_NONE', - 'NVOS32_ATTR_COMPR_PLC_ANY', 'NVOS32_ATTR_COMPR_PLC_REQUIRED', - 'NVOS32_ATTR_COMPR_REQUIRED', 'NVOS32_ATTR_DEPTH_128', - 'NVOS32_ATTR_DEPTH_16', 'NVOS32_ATTR_DEPTH_24', - 'NVOS32_ATTR_DEPTH_32', 'NVOS32_ATTR_DEPTH_64', - 'NVOS32_ATTR_DEPTH_8', 'NVOS32_ATTR_DEPTH_UNKNOWN', - 'NVOS32_ATTR_FORMAT_BLOCK_LINEAR', - 'NVOS32_ATTR_FORMAT_HIGH_FIELD', 'NVOS32_ATTR_FORMAT_LOW_FIELD', - 'NVOS32_ATTR_FORMAT_PITCH', 'NVOS32_ATTR_FORMAT_SWIZZLED', - 'NVOS32_ATTR_LOCATION_ANY', 'NVOS32_ATTR_LOCATION_PCI', - 'NVOS32_ATTR_LOCATION_VIDMEM', 'NVOS32_ATTR_NONE', - 'NVOS32_ATTR_PAGE_SIZE_4KB', 'NVOS32_ATTR_PAGE_SIZE_BIG', - 'NVOS32_ATTR_PAGE_SIZE_DEFAULT', 'NVOS32_ATTR_PAGE_SIZE_HUGE', - 'NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS', - 'NVOS32_ATTR_PHYSICALITY_CONTIGUOUS', - 'NVOS32_ATTR_PHYSICALITY_DEFAULT', - 'NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS', 'NVOS32_ATTR_ZCULL_ANY', - 'NVOS32_ATTR_ZCULL_NONE', 'NVOS32_ATTR_ZCULL_REQUIRED', - 'NVOS32_ATTR_ZCULL_SHARED', 'NVOS32_ATTR_ZS_PACKING_S8', - 'NVOS32_ATTR_ZS_PACKING_S8Z24', 'NVOS32_ATTR_ZS_PACKING_X8Z24', - 'NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8', - 'NVOS32_ATTR_ZS_PACKING_Z16', 'NVOS32_ATTR_ZS_PACKING_Z24S8', - 'NVOS32_ATTR_ZS_PACKING_Z24X8', 'NVOS32_ATTR_ZS_PACKING_Z32', - 'NVOS32_ATTR_ZS_PACKING_Z32_X24S8', 'NVOS32_ATTR_Z_TYPE_FIXED', - 'NVOS32_ATTR_Z_TYPE_FLOAT', 'NVOS32_BLOCKINFO', - 'NVOS32_BLOCK_TYPE_FREE', 'NVOS32_DELETE_RESOURCES_ALL', - 'NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS', - 'NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR', - 'NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE', - 'NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY', - 'NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY', - 'NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR', - 'NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR', - 'NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS', - 'NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE', - 'NVOS32_DUMP_FLAGS_TYPE_FB', - 'NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU', - 'NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR', - 'NVOS32_FUNCTION_ALLOC_SIZE', 'NVOS32_FUNCTION_ALLOC_SIZE_RANGE', - 'NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT', - 'NVOS32_FUNCTION_DUMP', 'NVOS32_FUNCTION_FREE', - 'NVOS32_FUNCTION_GET_MEM_ALIGNMENT', 'NVOS32_FUNCTION_HW_ALLOC', - 'NVOS32_FUNCTION_HW_FREE', 'NVOS32_FUNCTION_INFO', - 'NVOS32_FUNCTION_REACQUIRE_COMPR', - 'NVOS32_FUNCTION_RELEASE_COMPR', 'NVOS32_HEAP_DUMP_BLOCK', - 'NVOS32_INVALID_BLOCK_FREE_OFFSET', - 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP', - 'NVOS32_MEM_TAG_NONE', 'NVOS32_NUM_MEM_TYPES', - 'NVOS32_PARAMETERS', - 'NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_REALLOC_FLAGS_GROW_ALLOCATION', - 'NVOS32_REALLOC_FLAGS_REALLOC_DOWN', - 'NVOS32_REALLOC_FLAGS_REALLOC_UP', - 'NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION', - 'NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_TYPE_CURSOR', 'NVOS32_TYPE_DEPTH', 'NVOS32_TYPE_DMA', - 'NVOS32_TYPE_FONT', 'NVOS32_TYPE_IMAGE', 'NVOS32_TYPE_INSTANCE', - 'NVOS32_TYPE_NOTIFIER', 'NVOS32_TYPE_OWNER_RM', 'NVOS32_TYPE_PMA', - 'NVOS32_TYPE_PRIMARY', 'NVOS32_TYPE_RESERVED', - 'NVOS32_TYPE_SHADER_PROGRAM', 'NVOS32_TYPE_STENCIL', - 'NVOS32_TYPE_TEXTURE', 'NVOS32_TYPE_UNUSED', 'NVOS32_TYPE_VIDEO', - 'NVOS32_TYPE_ZCULL', 'NVOS33_FLAGS_ACCESS_READ_ONLY', - 'NVOS33_FLAGS_ACCESS_READ_WRITE', - 'NVOS33_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO', - 'NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES', - 'NVOS33_FLAGS_CACHING_TYPE_CACHED', - 'NVOS33_FLAGS_CACHING_TYPE_DEFAULT', - 'NVOS33_FLAGS_CACHING_TYPE_UNCACHED', - 'NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK', - 'NVOS33_FLAGS_CACHING_TYPE_WRITEBACK', - 'NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED', - 'NVOS33_FLAGS_FIFO_MAPPING_DEFAULT', - 'NVOS33_FLAGS_FIFO_MAPPING_ENABLE', - 'NVOS33_FLAGS_MAPPING_DEFAULT', 'NVOS33_FLAGS_MAPPING_DIRECT', - 'NVOS33_FLAGS_MAPPING_REFLECTED', - 'NVOS33_FLAGS_MAP_FIXED_DISABLE', 'NVOS33_FLAGS_MAP_FIXED_ENABLE', - 'NVOS33_FLAGS_MEM_SPACE_CLIENT', 'NVOS33_FLAGS_MEM_SPACE_USER', - 'NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE', - 'NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE', - 'NVOS33_FLAGS_PERSISTENT_DISABLE', - 'NVOS33_FLAGS_PERSISTENT_ENABLE', - 'NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE', - 'NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE', - 'NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE', - 'NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE', 'NVOS33_PARAMETERS', - 'NVOS34_PARAMETERS', 'NVOS38_ACCESS_TYPE_READ_BINARY', - 'NVOS38_ACCESS_TYPE_READ_DWORD', - 'NVOS38_ACCESS_TYPE_WRITE_BINARY', - 'NVOS38_ACCESS_TYPE_WRITE_DWORD', - 'NVOS38_MAX_REGISTRY_BINARY_LENGTH', - 'NVOS38_MAX_REGISTRY_STRING_LENGTH', 'NVOS38_PARAMETERS', - 'NVOS39_PARAMETERS', 'NVOS41_PARAMETERS', - 'NVOS46_FLAGS_32BIT_POINTER_DISABLE', - 'NVOS46_FLAGS_32BIT_POINTER_ENABLE', - 'NVOS46_FLAGS_ACCESS_READ_ONLY', 'NVOS46_FLAGS_ACCESS_READ_WRITE', - 'NVOS46_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS46_FLAGS_CACHE_SNOOP_DISABLE', - 'NVOS46_FLAGS_CACHE_SNOOP_ENABLE', - 'NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE', - 'NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE', - 'NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE', - 'NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE', - 'NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE', - 'NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE', - 'NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN', - 'NVOS46_FLAGS_DMA_OFFSET_GROWS_UP', - 'NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE', - 'NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE', - 'NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE', - 'NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE', - 'NVOS46_FLAGS_KERNEL_MAPPING_ENABLE', - 'NVOS46_FLAGS_KERNEL_MAPPING_NONE', 'NVOS46_FLAGS_P2P_ENABLE_NO', - 'NVOS46_FLAGS_P2P_ENABLE_NONE', 'NVOS46_FLAGS_P2P_ENABLE_NOSLI', - 'NVOS46_FLAGS_P2P_ENABLE_SLI', 'NVOS46_FLAGS_P2P_ENABLE_YES', - 'NVOS46_FLAGS_PAGE_KIND_PHYSICAL', - 'NVOS46_FLAGS_PAGE_KIND_VIRTUAL', 'NVOS46_FLAGS_PAGE_SIZE_4KB', - 'NVOS46_FLAGS_PAGE_SIZE_512M', 'NVOS46_FLAGS_PAGE_SIZE_BIG', - 'NVOS46_FLAGS_PAGE_SIZE_BOTH', 'NVOS46_FLAGS_PAGE_SIZE_DEFAULT', - 'NVOS46_FLAGS_PAGE_SIZE_HUGE', - 'NVOS46_FLAGS_SHADER_ACCESS_DEFAULT', - 'NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY', - 'NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE', - 'NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY', - 'NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT', - 'NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT', - 'NVOS46_FLAGS_TLB_LOCK_DISABLE', 'NVOS46_FLAGS_TLB_LOCK_ENABLE', - 'NVOS46_PARAMETERS', 'NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE', - 'NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE', 'NVOS47_PARAMETERS', - 'NVOS49_PARAMETERS', 'NVOS54_FLAGS_FINN_SERIALIZED', - 'NVOS54_FLAGS_IRQL_RAISED', 'NVOS54_FLAGS_LOCK_BYPASS', - 'NVOS54_FLAGS_NONE', 'NVOS54_PARAMETERS', 'NVOS55_PARAMETERS', - 'NVOS56_PARAMETERS', 'NVOS57_PARAMETERS', 'NVOS61_PARAMETERS', - 'NVOS62_PARAMETERS', 'NVOS63_PARAMETERS', - 'NVOS64_FLAGS_FINN_SERIALIZED', 'NVOS64_FLAGS_NONE', - 'NVOS64_PARAMETERS', 'NVOS65_PARAMETERS', - 'NVOS65_PARAMETERS_VERSION_MAGIC', - 'NVOS_I2C_ACCESS_MAX_BUFFER_SIZE', 'NVOS_I2C_ACCESS_PARAMS', - 'NVOS_INCLUDED', 'NVOS_MAX_SUBDEVICES', - 'NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX', - 'NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS', - 'NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION', - 'NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO', - 'NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES', - 'NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE', 'NVPOWERSTATE_PARAMETERS', - 'NVSIM01_BUS_XACT', 'NV_BSP_ALLOCATION_PARAMETERS', 'NV_CE_UTILS', - 'NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS', - 'NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE', - 'NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1', - 'NV_CHANNEL_ALLOC_PARAMS', 'NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID', - 'NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS', - 'NV_CONFIDENTIAL_COMPUTE', - 'NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE', - 'NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_NULL', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS', - 'NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE', - 'NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE', - 'NV_CONF_COMPUTE_NONCE_SIZE', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE', - 'NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED', - 'NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE', - 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE', - 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE', - 'NV_CONTEXT_DMA_ALLOCATION_PARAMS', 'NV_COUNTER_COLLECTION_UNIT', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC', - 'NV_CTXSHARE_ALLOCATION_PARAMETERS', - 'NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL', - 'NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS', - 'NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE', - 'NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE', - 'NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY', - 'NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE', - 'NV_DEVICE_ALLOCATION_FLAGS_NONE', - 'NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT', - 'NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS', - 'NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE', - 'NV_DEVICE_ALLOCATION_SZNAME_MAXLEN', - 'NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES', - 'NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES', - 'NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE', - 'NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT', - 'NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE', - 'NV_DMABUF_EXPORT_MAX_HANDLES', 'NV_ESCAPE_H_INCLUDED', - 'NV_ESC_ALLOC_OS_EVENT', 'NV_ESC_ATTACH_GPUS_TO_FD', - 'NV_ESC_CARD_INFO', 'NV_ESC_CHECK_VERSION_STR', - 'NV_ESC_EXPORT_TO_DMABUF_FD', 'NV_ESC_FREE_OS_EVENT', - 'NV_ESC_IOCTL_XFER_CMD', 'NV_ESC_NUMA_INFO', - 'NV_ESC_QUERY_DEVICE_INTR', 'NV_ESC_REGISTER_FD', - 'NV_ESC_RM_ACCESS_REGISTRY', 'NV_ESC_RM_ADD_VBLANK_CALLBACK', - 'NV_ESC_RM_ALLOC', 'NV_ESC_RM_ALLOC_CONTEXT_DMA2', - 'NV_ESC_RM_ALLOC_MEMORY', 'NV_ESC_RM_ALLOC_OBJECT', - 'NV_ESC_RM_BIND_CONTEXT_DMA', 'NV_ESC_RM_CONFIG_GET', - 'NV_ESC_RM_CONFIG_GET_EX', 'NV_ESC_RM_CONFIG_SET', - 'NV_ESC_RM_CONFIG_SET_EX', 'NV_ESC_RM_CONTROL', - 'NV_ESC_RM_DUP_OBJECT', 'NV_ESC_RM_EXPORT_OBJECT_TO_FD', - 'NV_ESC_RM_FREE', 'NV_ESC_RM_GET_EVENT_DATA', - 'NV_ESC_RM_I2C_ACCESS', 'NV_ESC_RM_IDLE_CHANNELS', - 'NV_ESC_RM_IMPORT_OBJECT_FROM_FD', - 'NV_ESC_RM_LOCKLESS_DIAGNOSTIC', 'NV_ESC_RM_MAP_MEMORY', - 'NV_ESC_RM_MAP_MEMORY_DMA', 'NV_ESC_RM_SHARE', - 'NV_ESC_RM_UNMAP_MEMORY', 'NV_ESC_RM_UNMAP_MEMORY_DMA', - 'NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO', - 'NV_ESC_RM_VID_HEAP_CONTROL', 'NV_ESC_SET_NUMA_STATUS', - 'NV_ESC_STATUS_CODE', 'NV_ESC_SYS_PARAMS', - 'NV_ESC_WAIT_OPEN_COMPLETE', 'NV_EVENT_BUFFER', - 'NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS', - 'NV_GI_UUID_LEN', 'NV_GRID_LICENSED_PRODUCT_COMPUTE', - 'NV_GRID_LICENSED_PRODUCT_GAMING', - 'NV_GRID_LICENSED_PRODUCT_VAPPS', 'NV_GRID_LICENSED_PRODUCT_VPC', - 'NV_GRID_LICENSED_PRODUCT_VWS', - 'NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION', - 'NV_GRID_LICENSE_FEATURE_GAMING_EDITION', - 'NV_GRID_LICENSE_FEATURE_VAPPS_EDITION', - 'NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION', - 'NV_GRID_LICENSE_FEATURE_VPC_EDITION', - 'NV_GRID_LICENSE_INFO_MAX_LENGTH', 'NV_GR_ALLOCATION_PARAMETERS', - 'NV_HOPPER_USERMODE_A_PARAMS', 'NV_IMEX_SESSION', 'NV_IOCTL_BASE', - 'NV_IOCTL_FCT_BASE', 'NV_IOCTL_H', 'NV_IOCTL_MAGIC', - 'NV_IOCTL_NUMA_H', 'NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES', - 'NV_IOCTL_NUMA_STATUS_DISABLED', 'NV_IOCTL_NUMA_STATUS_OFFLINE', - 'NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED', - 'NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS', - 'NV_IOCTL_NUMA_STATUS_ONLINE', - 'NV_IOCTL_NUMA_STATUS_ONLINE_FAILED', - 'NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS', 'NV_IOCTL_NUMBERS_H', - 'NV_MEMORY_ALLOCATION_PARAMS', 'NV_MEMORY_DESC_PARAMS', - 'NV_MEMORY_EXPORT', 'NV_MEMORY_EXTENDED_USER', 'NV_MEMORY_FABRIC', - 'NV_MEMORY_FABRIC_IMPORTED_REF', 'NV_MEMORY_FABRIC_IMPORT_V2', - 'NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS', 'NV_MEMORY_MAPPER', - 'NV_MEMORY_MULTICAST_FABRIC', 'NV_ME_ALLOCATION_PARAMETERS', - 'NV_MSENC_ALLOCATION_PARAMETERS', - 'NV_NVJPG_ALLOCATION_PARAMETERS', 'NV_OFA_ALLOCATION_PARAMETERS', - 'NV_OS_DESC_MEMORY_ALLOCATION_PARAMS', 'NV_PFAULT', - 'NV_PFAULT_ACCESS_TYPE_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH', - 'NV_PFAULT_ACCESS_TYPE_PHYS_READ', - 'NV_PFAULT_ACCESS_TYPE_PHYS_WRITE', - 'NV_PFAULT_ACCESS_TYPE_PREFETCH', 'NV_PFAULT_ACCESS_TYPE_READ', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH', - 'NV_PFAULT_ACCESS_TYPE_VIRT_READ', - 'NV_PFAULT_ACCESS_TYPE_VIRT_WRITE', 'NV_PFAULT_ACCESS_TYPE_WRITE', - 'NV_PFAULT_CLIENT_GPC_GCC', 'NV_PFAULT_CLIENT_GPC_GPCCS', - 'NV_PFAULT_CLIENT_GPC_GPM', 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_0', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_1', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_10', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_11', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_12', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_13', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_14', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_15', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_2', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_3', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_4', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_5', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_6', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_7', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_8', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_9', 'NV_PFAULT_CLIENT_GPC_PE_0', - 'NV_PFAULT_CLIENT_GPC_PE_1', 'NV_PFAULT_CLIENT_GPC_PE_10', - 'NV_PFAULT_CLIENT_GPC_PE_11', 'NV_PFAULT_CLIENT_GPC_PE_12', - 'NV_PFAULT_CLIENT_GPC_PE_13', 'NV_PFAULT_CLIENT_GPC_PE_14', - 'NV_PFAULT_CLIENT_GPC_PE_15', 'NV_PFAULT_CLIENT_GPC_PE_16', - 'NV_PFAULT_CLIENT_GPC_PE_17', 'NV_PFAULT_CLIENT_GPC_PE_18', - 'NV_PFAULT_CLIENT_GPC_PE_19', 'NV_PFAULT_CLIENT_GPC_PE_2', - 'NV_PFAULT_CLIENT_GPC_PE_3', 'NV_PFAULT_CLIENT_GPC_PE_4', - 'NV_PFAULT_CLIENT_GPC_PE_5', 'NV_PFAULT_CLIENT_GPC_PE_6', - 'NV_PFAULT_CLIENT_GPC_PE_7', 'NV_PFAULT_CLIENT_GPC_PE_8', - 'NV_PFAULT_CLIENT_GPC_PE_9', 'NV_PFAULT_CLIENT_GPC_PROP_0', - 'NV_PFAULT_CLIENT_GPC_PROP_1', 'NV_PFAULT_CLIENT_GPC_PROP_2', - 'NV_PFAULT_CLIENT_GPC_PROP_3', 'NV_PFAULT_CLIENT_GPC_RAST', - 'NV_PFAULT_CLIENT_GPC_RGG_UTLB', 'NV_PFAULT_CLIENT_GPC_ROP_0', - 'NV_PFAULT_CLIENT_GPC_ROP_1', 'NV_PFAULT_CLIENT_GPC_ROP_2', - 'NV_PFAULT_CLIENT_GPC_ROP_3', 'NV_PFAULT_CLIENT_GPC_T1_0', - 'NV_PFAULT_CLIENT_GPC_T1_1', 'NV_PFAULT_CLIENT_GPC_T1_10', - 'NV_PFAULT_CLIENT_GPC_T1_11', 'NV_PFAULT_CLIENT_GPC_T1_12', - 'NV_PFAULT_CLIENT_GPC_T1_13', 'NV_PFAULT_CLIENT_GPC_T1_14', - 'NV_PFAULT_CLIENT_GPC_T1_15', 'NV_PFAULT_CLIENT_GPC_T1_16', - 'NV_PFAULT_CLIENT_GPC_T1_17', 'NV_PFAULT_CLIENT_GPC_T1_18', - 'NV_PFAULT_CLIENT_GPC_T1_19', 'NV_PFAULT_CLIENT_GPC_T1_2', - 'NV_PFAULT_CLIENT_GPC_T1_20', 'NV_PFAULT_CLIENT_GPC_T1_21', - 'NV_PFAULT_CLIENT_GPC_T1_22', 'NV_PFAULT_CLIENT_GPC_T1_23', - 'NV_PFAULT_CLIENT_GPC_T1_24', 'NV_PFAULT_CLIENT_GPC_T1_25', - 'NV_PFAULT_CLIENT_GPC_T1_26', 'NV_PFAULT_CLIENT_GPC_T1_27', - 'NV_PFAULT_CLIENT_GPC_T1_28', 'NV_PFAULT_CLIENT_GPC_T1_29', - 'NV_PFAULT_CLIENT_GPC_T1_3', 'NV_PFAULT_CLIENT_GPC_T1_30', - 'NV_PFAULT_CLIENT_GPC_T1_31', 'NV_PFAULT_CLIENT_GPC_T1_32', - 'NV_PFAULT_CLIENT_GPC_T1_33', 'NV_PFAULT_CLIENT_GPC_T1_34', - 'NV_PFAULT_CLIENT_GPC_T1_35', 'NV_PFAULT_CLIENT_GPC_T1_36', - 'NV_PFAULT_CLIENT_GPC_T1_37', 'NV_PFAULT_CLIENT_GPC_T1_38', - 'NV_PFAULT_CLIENT_GPC_T1_39', 'NV_PFAULT_CLIENT_GPC_T1_4', - 'NV_PFAULT_CLIENT_GPC_T1_5', 'NV_PFAULT_CLIENT_GPC_T1_6', - 'NV_PFAULT_CLIENT_GPC_T1_7', 'NV_PFAULT_CLIENT_GPC_T1_8', - 'NV_PFAULT_CLIENT_GPC_T1_9', 'NV_PFAULT_CLIENT_GPC_TPCCS_0', - 'NV_PFAULT_CLIENT_GPC_TPCCS_1', 'NV_PFAULT_CLIENT_GPC_TPCCS_10', - 'NV_PFAULT_CLIENT_GPC_TPCCS_11', 'NV_PFAULT_CLIENT_GPC_TPCCS_12', - 'NV_PFAULT_CLIENT_GPC_TPCCS_13', 'NV_PFAULT_CLIENT_GPC_TPCCS_14', - 'NV_PFAULT_CLIENT_GPC_TPCCS_15', 'NV_PFAULT_CLIENT_GPC_TPCCS_16', - 'NV_PFAULT_CLIENT_GPC_TPCCS_17', 'NV_PFAULT_CLIENT_GPC_TPCCS_18', - 'NV_PFAULT_CLIENT_GPC_TPCCS_19', 'NV_PFAULT_CLIENT_GPC_TPCCS_2', - 'NV_PFAULT_CLIENT_GPC_TPCCS_3', 'NV_PFAULT_CLIENT_GPC_TPCCS_4', - 'NV_PFAULT_CLIENT_GPC_TPCCS_5', 'NV_PFAULT_CLIENT_GPC_TPCCS_6', - 'NV_PFAULT_CLIENT_GPC_TPCCS_7', 'NV_PFAULT_CLIENT_GPC_TPCCS_8', - 'NV_PFAULT_CLIENT_GPC_TPCCS_9', 'NV_PFAULT_CLIENT_HUB_ACTRS', - 'NV_PFAULT_CLIENT_HUB_AFALCON', 'NV_PFAULT_CLIENT_HUB_CE0', - 'NV_PFAULT_CLIENT_HUB_CE1', 'NV_PFAULT_CLIENT_HUB_CE2', - 'NV_PFAULT_CLIENT_HUB_CE_SHIM', 'NV_PFAULT_CLIENT_HUB_DFALCON', - 'NV_PFAULT_CLIENT_HUB_DISPNISO', 'NV_PFAULT_CLIENT_HUB_DNISO', - 'NV_PFAULT_CLIENT_HUB_DONT_CARE', 'NV_PFAULT_CLIENT_HUB_DWBIF', - 'NV_PFAULT_CLIENT_HUB_ESC', 'NV_PFAULT_CLIENT_HUB_FBFALCON', - 'NV_PFAULT_CLIENT_HUB_FE', 'NV_PFAULT_CLIENT_HUB_FE0', - 'NV_PFAULT_CLIENT_HUB_FE1', 'NV_PFAULT_CLIENT_HUB_FE2', - 'NV_PFAULT_CLIENT_HUB_FE3', 'NV_PFAULT_CLIENT_HUB_FE4', - 'NV_PFAULT_CLIENT_HUB_FE5', 'NV_PFAULT_CLIENT_HUB_FE6', - 'NV_PFAULT_CLIENT_HUB_FE7', 'NV_PFAULT_CLIENT_HUB_FECS', - 'NV_PFAULT_CLIENT_HUB_FECS0', 'NV_PFAULT_CLIENT_HUB_FECS1', - 'NV_PFAULT_CLIENT_HUB_FECS2', 'NV_PFAULT_CLIENT_HUB_FECS3', - 'NV_PFAULT_CLIENT_HUB_FECS4', 'NV_PFAULT_CLIENT_HUB_FECS5', - 'NV_PFAULT_CLIENT_HUB_FECS6', 'NV_PFAULT_CLIENT_HUB_FECS7', - 'NV_PFAULT_CLIENT_HUB_GRCOPY', 'NV_PFAULT_CLIENT_HUB_GSP', - 'NV_PFAULT_CLIENT_HUB_HOST', 'NV_PFAULT_CLIENT_HUB_HOST_CPU', - 'NV_PFAULT_CLIENT_HUB_HOST_CPU_NB', 'NV_PFAULT_CLIENT_HUB_HSCE0', - 'NV_PFAULT_CLIENT_HUB_HSCE1', 'NV_PFAULT_CLIENT_HUB_HSCE10', - 'NV_PFAULT_CLIENT_HUB_HSCE11', 'NV_PFAULT_CLIENT_HUB_HSCE12', - 'NV_PFAULT_CLIENT_HUB_HSCE13', 'NV_PFAULT_CLIENT_HUB_HSCE14', - 'NV_PFAULT_CLIENT_HUB_HSCE15', 'NV_PFAULT_CLIENT_HUB_HSCE2', - 'NV_PFAULT_CLIENT_HUB_HSCE3', 'NV_PFAULT_CLIENT_HUB_HSCE4', - 'NV_PFAULT_CLIENT_HUB_HSCE5', 'NV_PFAULT_CLIENT_HUB_HSCE6', - 'NV_PFAULT_CLIENT_HUB_HSCE7', 'NV_PFAULT_CLIENT_HUB_HSCE8', - 'NV_PFAULT_CLIENT_HUB_HSCE9', 'NV_PFAULT_CLIENT_HUB_HSHUB', - 'NV_PFAULT_CLIENT_HUB_ISO', 'NV_PFAULT_CLIENT_HUB_MMU', - 'NV_PFAULT_CLIENT_HUB_MMU_NB', 'NV_PFAULT_CLIENT_HUB_NISO', - 'NV_PFAULT_CLIENT_HUB_NVDEC', 'NV_PFAULT_CLIENT_HUB_NVDEC0', - 'NV_PFAULT_CLIENT_HUB_NVDEC1', 'NV_PFAULT_CLIENT_HUB_NVDEC2', - 'NV_PFAULT_CLIENT_HUB_NVDEC3', 'NV_PFAULT_CLIENT_HUB_NVDEC4', - 'NV_PFAULT_CLIENT_HUB_NVENC', 'NV_PFAULT_CLIENT_HUB_NVENC0', - 'NV_PFAULT_CLIENT_HUB_NVENC1', 'NV_PFAULT_CLIENT_HUB_NVENC2', - 'NV_PFAULT_CLIENT_HUB_NVJPG0', 'NV_PFAULT_CLIENT_HUB_OFA0', - 'NV_PFAULT_CLIENT_HUB_P2P', 'NV_PFAULT_CLIENT_HUB_PD', - 'NV_PFAULT_CLIENT_HUB_PERF', 'NV_PFAULT_CLIENT_HUB_PERF0', - 'NV_PFAULT_CLIENT_HUB_PMU', 'NV_PFAULT_CLIENT_HUB_PTP_X0', - 'NV_PFAULT_CLIENT_HUB_PTP_X1', 'NV_PFAULT_CLIENT_HUB_PTP_X10', - 'NV_PFAULT_CLIENT_HUB_PTP_X11', 'NV_PFAULT_CLIENT_HUB_PTP_X12', - 'NV_PFAULT_CLIENT_HUB_PTP_X13', 'NV_PFAULT_CLIENT_HUB_PTP_X14', - 'NV_PFAULT_CLIENT_HUB_PTP_X15', 'NV_PFAULT_CLIENT_HUB_PTP_X2', - 'NV_PFAULT_CLIENT_HUB_PTP_X3', 'NV_PFAULT_CLIENT_HUB_PTP_X4', - 'NV_PFAULT_CLIENT_HUB_PTP_X5', 'NV_PFAULT_CLIENT_HUB_PTP_X6', - 'NV_PFAULT_CLIENT_HUB_PTP_X7', 'NV_PFAULT_CLIENT_HUB_PTP_X8', - 'NV_PFAULT_CLIENT_HUB_PTP_X9', 'NV_PFAULT_CLIENT_HUB_RASTERTWOD', - 'NV_PFAULT_CLIENT_HUB_SCC', 'NV_PFAULT_CLIENT_HUB_SCC_NB', - 'NV_PFAULT_CLIENT_HUB_SEC', 'NV_PFAULT_CLIENT_HUB_SKED', - 'NV_PFAULT_CLIENT_HUB_SKED0', 'NV_PFAULT_CLIENT_HUB_SKED1', - 'NV_PFAULT_CLIENT_HUB_SKED2', 'NV_PFAULT_CLIENT_HUB_SKED3', - 'NV_PFAULT_CLIENT_HUB_SKED4', 'NV_PFAULT_CLIENT_HUB_SKED5', - 'NV_PFAULT_CLIENT_HUB_SKED6', 'NV_PFAULT_CLIENT_HUB_SKED7', - 'NV_PFAULT_CLIENT_HUB_SSYNC', 'NV_PFAULT_CLIENT_HUB_VIP', - 'NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0', - 'NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1', 'NV_PFAULT_CLIENT_HUB_XV', - 'NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE', - 'NV_PFAULT_FAULT_TYPE_PDE', 'NV_PFAULT_FAULT_TYPE_PDE_SIZE', - 'NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_POISONED', - 'NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION', 'NV_PFAULT_FAULT_TYPE_PTE', - 'NV_PFAULT_FAULT_TYPE_REGION_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_RO_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK', - 'NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE', - 'NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND', - 'NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_WORK_CREATION', - 'NV_PFAULT_FAULT_TYPE_WO_VIOLATION', - 'NV_PFAULT_MMU_CLIENT_TYPE_GPC', 'NV_PFAULT_MMU_CLIENT_TYPE_HUB', - 'NV_PFAULT_MMU_ENG_ID_BAR1', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN0', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN1', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN10', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN11', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN12', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN13', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN14', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN15', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN16', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN17', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN18', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN19', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN2', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN20', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN21', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN22', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN23', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN24', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN25', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN26', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN27', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN28', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN29', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN3', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN30', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN31', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN32', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN33', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN34', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN35', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN36', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN37', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN38', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN39', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN4', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN40', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN41', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN42', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN43', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN44', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN45', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN46', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN47', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN48', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN49', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN5', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN50', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN51', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN52', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN53', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN54', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN55', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN56', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN57', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN58', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN59', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN6', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN60', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN61', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN62', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN63', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN7', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN8', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN9', - 'NV_PFAULT_MMU_ENG_ID_BAR2', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN0', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN1', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN10', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN11', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN12', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN13', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN14', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN15', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN16', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN17', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN18', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN19', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN2', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN20', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN21', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN22', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN23', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN24', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN25', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN26', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN27', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN28', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN29', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN3', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN30', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN31', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN32', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN33', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN34', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN35', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN36', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN37', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN38', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN39', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN4', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN40', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN41', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN42', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN43', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN44', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN45', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN46', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN47', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN48', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN49', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN5', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN50', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN51', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN52', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN53', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN54', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN55', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN56', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN57', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN58', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN59', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN6', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN60', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN61', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN62', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN63', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN7', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN8', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN9', - 'NV_PFAULT_MMU_ENG_ID_CE0', 'NV_PFAULT_MMU_ENG_ID_CE1', - 'NV_PFAULT_MMU_ENG_ID_CE2', 'NV_PFAULT_MMU_ENG_ID_CE3', - 'NV_PFAULT_MMU_ENG_ID_CE4', 'NV_PFAULT_MMU_ENG_ID_CE5', - 'NV_PFAULT_MMU_ENG_ID_CE6', 'NV_PFAULT_MMU_ENG_ID_CE7', - 'NV_PFAULT_MMU_ENG_ID_CE8', 'NV_PFAULT_MMU_ENG_ID_CE9', - 'NV_PFAULT_MMU_ENG_ID_DISPLAY', 'NV_PFAULT_MMU_ENG_ID_FLA', - 'NV_PFAULT_MMU_ENG_ID_GRAPHICS', 'NV_PFAULT_MMU_ENG_ID_GRCOPY', - 'NV_PFAULT_MMU_ENG_ID_GSP', 'NV_PFAULT_MMU_ENG_ID_HOST0', - 'NV_PFAULT_MMU_ENG_ID_HOST1', 'NV_PFAULT_MMU_ENG_ID_HOST10', - 'NV_PFAULT_MMU_ENG_ID_HOST11', 'NV_PFAULT_MMU_ENG_ID_HOST12', - 'NV_PFAULT_MMU_ENG_ID_HOST13', 'NV_PFAULT_MMU_ENG_ID_HOST14', - 'NV_PFAULT_MMU_ENG_ID_HOST15', 'NV_PFAULT_MMU_ENG_ID_HOST16', - 'NV_PFAULT_MMU_ENG_ID_HOST17', 'NV_PFAULT_MMU_ENG_ID_HOST18', - 'NV_PFAULT_MMU_ENG_ID_HOST19', 'NV_PFAULT_MMU_ENG_ID_HOST2', - 'NV_PFAULT_MMU_ENG_ID_HOST20', 'NV_PFAULT_MMU_ENG_ID_HOST21', - 'NV_PFAULT_MMU_ENG_ID_HOST22', 'NV_PFAULT_MMU_ENG_ID_HOST23', - 'NV_PFAULT_MMU_ENG_ID_HOST24', 'NV_PFAULT_MMU_ENG_ID_HOST25', - 'NV_PFAULT_MMU_ENG_ID_HOST26', 'NV_PFAULT_MMU_ENG_ID_HOST27', - 'NV_PFAULT_MMU_ENG_ID_HOST28', 'NV_PFAULT_MMU_ENG_ID_HOST29', - 'NV_PFAULT_MMU_ENG_ID_HOST3', 'NV_PFAULT_MMU_ENG_ID_HOST30', - 'NV_PFAULT_MMU_ENG_ID_HOST31', 'NV_PFAULT_MMU_ENG_ID_HOST4', - 'NV_PFAULT_MMU_ENG_ID_HOST5', 'NV_PFAULT_MMU_ENG_ID_HOST6', - 'NV_PFAULT_MMU_ENG_ID_HOST7', 'NV_PFAULT_MMU_ENG_ID_HOST8', - 'NV_PFAULT_MMU_ENG_ID_HOST9', 'NV_PFAULT_MMU_ENG_ID_IFB', - 'NV_PFAULT_MMU_ENG_ID_NVDEC', 'NV_PFAULT_MMU_ENG_ID_NVDEC0', - 'NV_PFAULT_MMU_ENG_ID_NVDEC1', 'NV_PFAULT_MMU_ENG_ID_NVDEC2', - 'NV_PFAULT_MMU_ENG_ID_NVDEC3', 'NV_PFAULT_MMU_ENG_ID_NVDEC4', - 'NV_PFAULT_MMU_ENG_ID_NVENC0', 'NV_PFAULT_MMU_ENG_ID_NVENC1', - 'NV_PFAULT_MMU_ENG_ID_NVENC2', 'NV_PFAULT_MMU_ENG_ID_NVJPG0', - 'NV_PFAULT_MMU_ENG_ID_OFA0', 'NV_PFAULT_MMU_ENG_ID_PERF', - 'NV_PFAULT_MMU_ENG_ID_PHYSICAL', 'NV_PFAULT_MMU_ENG_ID_PTP', - 'NV_PFAULT_MMU_ENG_ID_PWR_PMU', 'NV_PFAULT_MMU_ENG_ID_SEC', - 'NV_PPP_ALLOCATION_PARAMETERS', 'NV_RM_API_VERSION_CMD_QUERY', - 'NV_RM_API_VERSION_CMD_RELAXED', 'NV_RM_API_VERSION_CMD_STRICT', - 'NV_RM_API_VERSION_REPLY_RECOGNIZED', - 'NV_RM_API_VERSION_REPLY_UNRECOGNIZED', - 'NV_RM_API_VERSION_STRING_LENGTH', - 'NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR', - 'NV_SEC2_ALLOCATION_PARAMETERS', 'NV_SEMAPHORE_SURFACE', - 'NV_SUBPROC_NAME_MAX_LENGTH', 'NV_SWRUNLIST_ALLOCATION_PARAMS', - 'NV_SWRUNLIST_QOS_INTR_NONE', - 'NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT', - 'NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT', - 'NV_TIMEOUT_CONTROL_PARAMETERS', - 'NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS', - 'NV_VASPACE_ALLOCATION_FLAGS_NONE', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_FLA', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_HOST', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_MAX', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_NEW', - 'NV_VASPACE_ALLOCATION_PARAMETERS', - 'NV_VASPACE_BIG_PAGE_SIZE_128K', 'NV_VASPACE_BIG_PAGE_SIZE_64K', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', - 'NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO', - 'NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO', - 'NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE', - 'NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE', - 'NV_VP_ALLOCATION_FLAGS_STATIC_UCODE', - 'NV_VP_ALLOCATION_PARAMETERS', 'Nv2080ACPIEvent', - 'Nv2080AudioHdcpRequest', 'Nv2080ClocksChangeNotification', - 'Nv2080DpIrqNotification', 'Nv2080DstateHdaCodecNotification', - 'Nv2080DstateXusbPpcNotification', 'Nv2080EccDbeNotification', - 'Nv2080GC5GpuReadyParams', 'Nv2080HdcpStatusChangeNotification', - 'Nv2080HdmiFrlRequestNotification', 'Nv2080HotplugNotification', - 'Nv2080LpwrDifrPrefetchNotification', - 'Nv2080NvlinkLnkChangeNotification', - 'Nv2080PStateChangeNotification', 'Nv2080PowerEventNotification', - 'Nv2080PrivRegAccessFaultNotification', - 'Nv2080QosIntrNotification', 'Nv2080Typedef', - 'Nv2080VrrSetTimeoutNotification', - 'Nv2080WorkloadModulationChangeNotification', - 'Nv2080XusbPpcConnectStateNotification', 'Nv20Subdevice0', - 'NvUnixEvent', 'Nvc56fControl', 'Nvc86fControl', 'Nvc96fControl', - 'PARTITIONID_INVALID', 'PASCAL_CHANNEL_GPFIFO_A', - 'PASCAL_DMA_COPY_A', 'PB_SIZE_16KB', 'PB_SIZE_32KB', - 'PB_SIZE_4KB', 'PB_SIZE_64KB', 'PB_SIZE_8KB', - 'PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE', - 'PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK', - 'PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'PNV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'PNV2080_CTRL_GR_CTX_BUFFER_INFO', - 'PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'PNVPOWERSTATE_PARAMETERS', 'PRM_GSP_SPDM_CMD', - 'PRM_GSP_SPDM_CMD_CC_CTRL', 'PRM_GSP_SPDM_CMD_CC_DEINIT', - 'PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', 'PRM_GSP_SPDM_CMD_CC_INIT', - 'PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'PRM_GSP_SPDM_CMD_FIPS_SELFTEST', 'PRM_GSP_SPDM_MSG', - 'RM_GSP_SPDM_CMD', 'RM_GSP_SPDM_CMD_CC_CTRL', - 'RM_GSP_SPDM_CMD_CC_DEINIT', 'RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_CMD_CC_INIT', 'RM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_CMD_FIPS_SELFTEST', 'RM_GSP_SPDM_CMD_ID_CC_CTRL', - 'RM_GSP_SPDM_CMD_ID_CC_DEINIT', - 'RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_CMD_ID_CC_INIT', - 'RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST', - 'RM_GSP_SPDM_CMD_ID_INVALID_COMMAND', 'RM_GSP_SPDM_MSG', - 'RM_GSP_SPDM_MSG_ID_CC_CTRL', 'RM_GSP_SPDM_MSG_ID_CC_DEINIT', - 'RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_MSG_ID_CC_INIT', - 'RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST', - 'RM_GSP_SPDM_MSG_ID_INVALID_COMMAND', 'RM_USER_SHARED_DATA', - 'RPC_METER_ENTRY', 'RSVD7_SIZE', 'RSVD8_SIZE', - 'RX_LNK_RX_RSP_STATUS_HW_ERR', 'RX_LNK_RX_RSP_STATUS_PRIV_ERR', - 'RX_LNK_RX_RSP_STATUS_UR_ERR', - 'SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE', 'TLC_RX_LNK', - 'TLC_TX_SYS', 'TURING_A', 'TURING_CHANNEL_GPFIFO_A', - 'TURING_COMPUTE_A', 'TURING_DMA_COPY_A', 'TURING_USERMODE_A', - 'TX_SYS_TX_RSP_STATUS_HW_ERR', 'TX_SYS_TX_RSP_STATUS_PRIV_ERR', - 'TX_SYS_TX_RSP_STATUS_UR_ERR', 'UNIFIED_NV_STATUS', - 'UVM_ADD_SESSION', 'UVM_ADD_SESSION_PARAMS', - 'UVM_ALLOC_DEVICE_P2P', 'UVM_ALLOC_DEVICE_P2P_PARAMS', - 'UVM_ALLOC_SEMAPHORE_POOL', 'UVM_ALLOC_SEMAPHORE_POOL_PARAMS', - 'UVM_ALLOW_MIGRATION_RANGE_GROUPS', - 'UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS', 'UVM_CHANNEL_RETAINER', - 'UVM_CLEAN_UP_ZOMBIE_RESOURCES', - 'UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS', - 'UVM_CLEAR_ALL_ACCESS_COUNTERS', - 'UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS', - 'UVM_COUNTERS_OFFSET_BASE', 'UVM_CREATE_EVENT_QUEUE', - 'UVM_CREATE_EVENT_QUEUE_PARAMS', 'UVM_CREATE_EXTERNAL_RANGE', - 'UVM_CREATE_EXTERNAL_RANGE_PARAMS', 'UVM_CREATE_RANGE_GROUP', - 'UVM_CREATE_RANGE_GROUP_PARAMS', 'UVM_DEBUG_ACCESS_MEMORY', - 'UVM_DEBUG_ACCESS_MEMORY_PARAMS', 'UVM_DEINITIALIZE', - 'UVM_DESTROY_RANGE_GROUP', 'UVM_DESTROY_RANGE_GROUP_PARAMS', - 'UVM_DISABLE_PEER_ACCESS', 'UVM_DISABLE_PEER_ACCESS_PARAMS', - 'UVM_DISABLE_READ_DUPLICATION', - 'UVM_DISABLE_READ_DUPLICATION_PARAMS', - 'UVM_DISABLE_SYSTEM_WIDE_ATOMICS', - 'UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS', 'UVM_ENABLE_COUNTERS', - 'UVM_ENABLE_COUNTERS_PARAMS', 'UVM_ENABLE_PEER_ACCESS', - 'UVM_ENABLE_PEER_ACCESS_PARAMS', 'UVM_ENABLE_READ_DUPLICATION', - 'UVM_ENABLE_READ_DUPLICATION_PARAMS', - 'UVM_ENABLE_SYSTEM_WIDE_ATOMICS', - 'UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS', 'UVM_EVENTS_OFFSET_BASE', - 'UVM_EVENT_CTRL', 'UVM_EVENT_CTRL_PARAMS', 'UVM_FREE', - 'UVM_FREE_PARAMS', 'UVM_GET_GPU_UUID_TABLE', - 'UVM_GET_GPU_UUID_TABLE_PARAMS', 'UVM_INITIALIZE', - 'UVM_INITIALIZE_PARAMS', 'UVM_IS_8_SUPPORTED', - 'UVM_IS_8_SUPPORTED_PARAMS', 'UVM_MAP_COUNTER', - 'UVM_MAP_COUNTER_PARAMS', 'UVM_MAP_DYNAMIC_PARALLELISM_REGION', - 'UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS', - 'UVM_MAP_EVENT_QUEUE', 'UVM_MAP_EVENT_QUEUE_PARAMS', - 'UVM_MAP_EXTERNAL_ALLOCATION', - 'UVM_MAP_EXTERNAL_ALLOCATION_PARAMS', 'UVM_MAP_EXTERNAL_SPARSE', - 'UVM_MAP_EXTERNAL_SPARSE_PARAMS', - 'UVM_MAX_COUNTERS_PER_IOCTL_CALL', - 'UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL', - 'UVM_MAX_STREAMS_PER_IOCTL_CALL', 'UVM_MEM_MAP', - 'UVM_MEM_MAP_PARAMS', 'UVM_MIGRATE', 'UVM_MIGRATE_FLAGS_ALL', - 'UVM_MIGRATE_FLAGS_TEST_ALL', 'UVM_MIGRATE_FLAG_ASYNC', - 'UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE', - 'UVM_MIGRATE_FLAG_SKIP_CPU_MAP', 'UVM_MIGRATE_PARAMS', - 'UVM_MIGRATE_RANGE_GROUP', 'UVM_MIGRATE_RANGE_GROUP_PARAMS', - 'UVM_MM_INITIALIZE', 'UVM_MM_INITIALIZE_PARAMS', - 'UVM_PAGEABLE_MEM_ACCESS', 'UVM_PAGEABLE_MEM_ACCESS_ON_GPU', - 'UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS', - 'UVM_PAGEABLE_MEM_ACCESS_PARAMS', 'UVM_POPULATE_PAGEABLE', - 'UVM_POPULATE_PAGEABLE_FLAGS_ALL', - 'UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL', - 'UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED', - 'UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK', - 'UVM_POPULATE_PAGEABLE_PARAMS', - 'UVM_PREVENT_MIGRATION_RANGE_GROUPS', - 'UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS', 'UVM_REGION_COMMIT', - 'UVM_REGION_COMMIT_PARAMS', 'UVM_REGION_DECOMMIT', - 'UVM_REGION_DECOMMIT_PARAMS', 'UVM_REGION_SET_STREAM', - 'UVM_REGION_SET_STREAM_PARAMS', 'UVM_REGISTER_CHANNEL', - 'UVM_REGISTER_CHANNEL_PARAMS', 'UVM_REGISTER_GPU', - 'UVM_REGISTER_GPU_PARAMS', 'UVM_REGISTER_GPU_VASPACE', - 'UVM_REGISTER_GPU_VASPACE_PARAMS', 'UVM_REGISTER_MPS_CLIENT', - 'UVM_REGISTER_MPS_CLIENT_PARAMS', 'UVM_REGISTER_MPS_SERVER', - 'UVM_REGISTER_MPS_SERVER_PARAMS', 'UVM_RELEASE_VA', - 'UVM_RELEASE_VA_PARAMS', 'UVM_REMOVE_EVENT_QUEUE', - 'UVM_REMOVE_EVENT_QUEUE_PARAMS', 'UVM_REMOVE_SESSION', - 'UVM_REMOVE_SESSION_PARAMS', 'UVM_RESERVE_VA', - 'UVM_RESERVE_VA_PARAMS', 'UVM_RUN_TEST', 'UVM_RUN_TEST_PARAMS', - 'UVM_SET_ACCESSED_BY', 'UVM_SET_ACCESSED_BY_PARAMS', - 'UVM_SET_PREFERRED_LOCATION', 'UVM_SET_PREFERRED_LOCATION_PARAMS', - 'UVM_SET_RANGE_GROUP', 'UVM_SET_RANGE_GROUP_PARAMS', - 'UVM_SET_STREAM_RUNNING', 'UVM_SET_STREAM_RUNNING_PARAMS', - 'UVM_SET_STREAM_STOPPED', 'UVM_SET_STREAM_STOPPED_PARAMS', - 'UVM_TOOLS_DISABLE_COUNTERS', 'UVM_TOOLS_DISABLE_COUNTERS_PARAMS', - 'UVM_TOOLS_ENABLE_COUNTERS', 'UVM_TOOLS_ENABLE_COUNTERS_PARAMS', - 'UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS', - 'UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS', - 'UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS', - 'UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS', - 'UVM_TOOLS_FLUSH_EVENTS', 'UVM_TOOLS_FLUSH_EVENTS_PARAMS', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS', - 'UVM_TOOLS_INIT_EVENT_TRACKER', - 'UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS', - 'UVM_TOOLS_INIT_EVENT_TRACKER_V2', - 'UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS', - 'UVM_TOOLS_READ_PROCESS_MEMORY', - 'UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS', - 'UVM_TOOLS_SET_NOTIFICATION_THRESHOLD', - 'UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS', - 'UVM_TOOLS_WRITE_PROCESS_MEMORY', - 'UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS', 'UVM_UNMAP_EXTERNAL', - 'UVM_UNMAP_EXTERNAL_PARAMS', 'UVM_UNREGISTER_CHANNEL', - 'UVM_UNREGISTER_CHANNEL_PARAMS', 'UVM_UNREGISTER_GPU', - 'UVM_UNREGISTER_GPU_PARAMS', 'UVM_UNREGISTER_GPU_VASPACE', - 'UVM_UNREGISTER_GPU_VASPACE_PARAMS', 'UVM_UNSET_ACCESSED_BY', - 'UVM_UNSET_ACCESSED_BY_PARAMS', 'UVM_UNSET_PREFERRED_LOCATION', - 'UVM_UNSET_PREFERRED_LOCATION_PARAMS', 'UVM_VALIDATE_VA_RANGE', - 'UVM_VALIDATE_VA_RANGE_PARAMS', 'VOLTA_CHANNEL_GPFIFO_A', - 'VOLTA_USERMODE_A', 'VPR_REQUEST_PARAMS', 'VPR_STATUS_PARAMS', - '_NV_UNIX_NVOS_PARAMS_WRAPPERS_H_', '_UVM_IOCTL_H', - '_UVM_LINUX_IOCTL_H', '__CLC6C0QMD_H__', '__CLCEC0QMD_H__', - '__ga100_dev_fault_h__', '__gb100_clc96f_h__', - '__gb100_clcdc0_h__', '__gh100_clc86f_h__', - '_cl2080_notification_h_', '_cl_ampere_compute_a_h_', - '_clc56f_h_', '_clc6b5_h_', '_clc761_h_', '_clc9b5_h_', - 'blackwell_dma_copy_aControlPio', 'c__EA_ChannelPBSize', - 'c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE', - 'nv_ioctl_alloc_os_event_t', 'nv_ioctl_card_info_t', - 'nv_ioctl_export_to_dma_buf_fd_t', 'nv_ioctl_free_os_event_t', - 'nv_ioctl_numa_info_t', 'nv_ioctl_nvos02_parameters_with_fd', - 'nv_ioctl_nvos33_parameters_with_fd', - 'nv_ioctl_query_device_intr', 'nv_ioctl_register_fd_t', - 'nv_ioctl_rm_api_version_t', 'nv_ioctl_set_numa_status_t', - 'nv_ioctl_status_code_t', 'nv_ioctl_sys_params_t', - 'nv_ioctl_wait_open_complete_t', 'nv_ioctl_xfer_t', - 'nv_offline_addresses_t', 'nv_pci_info_t', - 'struct_ACR_FALCON_LS_STATUS', 'struct_ACR_REGION_HANDLE', - 'struct_ACR_REGION_ID_PROP', 'struct_ACR_REQUEST_PARAMS', - 'struct_ACR_STATUS_PARAMS', 'struct_CC_AES_CRYPTOBUNDLE', - 'struct_CC_HMAC_CRYPTOBUNDLE', 'struct_CC_KMB', - 'struct_DRAM_CLK_INSTANCE', - 'struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS', - 'struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS', - 'struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS', - 'struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS', - 'struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS', - 'struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS', - 'struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY', - 'struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS', - 'struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT', - 'struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS', - 'struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS', - 'struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS', - 'struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS', - 'struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY', - 'struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS', - 'struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS', - 'struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS', - 'struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_ACTIVE_DEVICE', - 'struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS', - 'struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS', - 'struct_NV0000_CTRL_GPU_DISCOVER_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS', - 'struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty', - 'struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS', - 'struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS', - 'struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS', - 'struct_NV0000_CTRL_GPU_VIDEO_LINKS', - 'struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS', - 'struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS', - 'struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS', - 'struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS', - 'struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0', - 'struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE', - 'struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_HWBC_INFO', - 'struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS', - 'struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS', - 'struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS', - 'struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS', - 'struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS', - 'struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS', - 'struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS', - 'struct_NV0080_ALLOC_PARAMETERS', - 'struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS', - 'struct_NV0080_CTRL_BIF_RESET_PARAMS', - 'struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS', - 'struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2', - 'struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS', - 'struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS', - 'struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS', - 'struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT', - 'struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS', - 'struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource', - 'struct_NV0080_CTRL_DMA_FLUSH_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK', - 'struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK', - 'struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS', - 'struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS', - 'struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS', - 'struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS', - 'struct_NV0080_CTRL_FB_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS', - 'struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS', - 'struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS', - 'struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM', - 'struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM', - 'struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS', - 'struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM', - 'struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS', - 'struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS', - 'struct_NV0080_CTRL_GR_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_GR_GET_INFO_PARAMS', - 'struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS', - 'struct_NV0080_CTRL_GR_ROUTE_INFO', - 'struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS', - 'struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS', - 'struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS', - 'struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS', - 'struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS', - 'struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'struct_NV2080CtrlNocatJournalDataTdrReason', - 'struct_NV2080CtrlNocatJournalInsertRecord', - 'struct_NV2080CtrlNocatJournalRclog', - 'struct_NV2080CtrlNocatJournalSetTag', - 'struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_BIOS_NBSI_REG_STRING', - 'struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_BFD_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR', - 'struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS', - 'struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO', - 'struct_NV2080_CTRL_BUS_PCI_BAR_INFO', - 'struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS', - 'struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS', - 'struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS', - 'struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS', - 'struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS', - 'struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS', - 'struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS', - 'struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO', - 'struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_CLIENT_INFO', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_STATS_ENTRY', - 'struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO', - 'struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS', - 'struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS', - 'struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS', - 'struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS', - 'struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS', - 'struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS', - 'struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS', - 'struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS', - 'struct_NV2080_CTRL_CMD_RC_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS', - 'struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS', - 'struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS', - 'struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS', - 'struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS', - 'struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO', - 'struct_NV2080_CTRL_DMA_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO', - 'struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS', - 'struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS', - 'struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS', - 'struct_NV2080_CTRL_EXEC_PARTITION_SPAN', - 'struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO', - 'struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_QUERY', - 'struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS', - 'struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS', - 'struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS', - 'struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS', - 'struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS', - 'struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS', - 'struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_STATUS_PARAMS', - 'struct_NV2080_CTRL_FB_IS_KIND_PARAMS', - 'struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO', - 'struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS', - 'struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS', - 'struct_NV2080_CTRL_FB_REMAP_ENTRY', - 'struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS', - 'struct_NV2080_CTRL_FB_SET_RRD_PARAMS', - 'struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS', - 'struct_NV2080_CTRL_FIFO_BIND_CHANNEL', - 'struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS', - 'struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO', - 'struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS', - 'struct_NV2080_CTRL_FIFO_DEVICE_ENTRY', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS', - 'struct_NV2080_CTRL_FIFO_MEM_INFO', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0', - 'struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS', - 'struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS', - 'struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS', - 'struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS', - 'struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS', - 'struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS', - 'struct_NV2080_CTRL_FLA_RANGE_PARAMS', - 'struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS', - 'struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS', - 'struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER', - 'struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS', - 'struct_NV2080_CTRL_GC6_ENTRY_PARAMS', - 'struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params', - 'struct_NV2080_CTRL_GC6_EXIT_PARAMS', - 'struct_NV2080_CTRL_GC6_EXIT_PARAMS_params', - 'struct_NV2080_CTRL_GC6_FLAVOR_INFO', - 'struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS', - 'struct_NV2080_CTRL_GPUMON_SAMPLE', - 'struct_NV2080_CTRL_GPUMON_SAMPLES', - 'struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG', - 'struct_NV2080_CTRL_GPU_COMPUTE_PROFILE', - 'struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS', - 'struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO', - 'struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO', - 'struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS', - 'struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS', - 'struct_NV2080_CTRL_GPU_FAULT_PACKET', - 'struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GFID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITION_INFO', - 'struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SDM_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS', - 'struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS', - 'struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO', - 'struct_NV2080_CTRL_GPU_PARTITION_SPAN', - 'struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_PID_INFO', - 'struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS', - 'struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_REG_OP', - 'struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS', - 'struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITION_INFO', - 'struct_NV2080_CTRL_GPU_SET_POWER_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_SDM_PARAMS', - 'struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS', - 'struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTX_BUFFER_INFO', - 'struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS', - 'struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0', - 'struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS', - 'struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0', - 'struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS', - 'struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC', - 'struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS', - 'struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS', - 'struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT', - 'struct_NV2080_CTRL_I2C_ACCESS_PARAMS', - 'struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS', - 'struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS', - 'struct_NV2080_CTRL_I2C_RW_REG_PARAMS', - 'struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BSP_CAPS', - 'struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO', - 'struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DEVICE_INFO', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_EDID_DATA', - 'struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO', - 'struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO', - 'struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GR_INFO', - 'struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY', - 'struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO', - 'struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO', - 'struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MSENC_CAPS', - 'struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NV_RANGE', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X', - 'struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO', - 'struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO', - 'struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS', - 'struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS', - 'struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS', - 'struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY', - 'struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS', - 'struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS', - 'struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS', - 'struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS', - 'struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS', - 'struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY', - 'struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS', - 'struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS', - 'struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS', - 'struct_NV2080_CTRL_NVENC_SW_SESSION_INFO', - 'struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO', - 'struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS', - 'struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO', - 'struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES', - 'struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS', - 'struct_NV2080_CTRL_NVLINK_DEVICE_INFO', - 'struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS', - 'struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS', - 'struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT', - 'struct_NV2080_CTRL_NVLINK_ERR_INFO', - 'struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES', - 'struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG', - 'struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS', - 'struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG', - 'struct_NV2080_CTRL_NVLINK_LANE_ERROR', - 'struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR', - 'struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO', - 'struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE', - 'struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO', - 'struct_NV2080_CTRL_NVLINK_PORT_EVENT', - 'struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_DATA', - 'struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES', - 'struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD', - 'struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS', - 'struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS', - 'struct_NV2080_CTRL_PERF_BOOST_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_CLK_INFO', - 'struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS', - 'struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE', - 'struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE', - 'struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS', - 'struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS', - 'struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST', - 'struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm', - 'struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS', - 'struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS', - 'struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS', - 'struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS', - 'struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS', - 'struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS', - 'struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO', - 'struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS', - 'struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS', - 'struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS', - 'struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE', - 'struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS', - 'struct_NV2080_GUEST_VM_INFO', 'struct_NV2080_HOST_VGPU_DEVICE', - 'struct_NV2080_INTR_CATEGORY_SUBTREE_MAP', - 'struct_NV2080_NOCAT_JOURNAL_ENTRY', - 'struct_NV2080_NOCAT_JOURNAL_GPU_STATE', - 'struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG', - 'struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS', - 'struct_NV2080_NOCAT_JOURNAL_RECORD', - 'struct_NV2080_RAFTS_FLOORSWEEP_INFO', - 'struct_NV2080_VF_MSIX_CAPS', 'struct_NV2080_VGPU_FB_USAGE', - 'struct_NV2080_VGPU_GUEST', - 'struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS', - 'struct_NV83DE_ALLOC_PARAMETERS', - 'struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_OP', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP', - 'struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY', - 'struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS', - 'struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS', - 'struct_NV83DE_MMU_FAULT_INFO', - 'struct_NV83DE_SM_ERROR_STATE_REGISTERS', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0', - 'struct_NVA06C_CTRL_GET_INFO_PARAMS', - 'struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS', - 'struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS', - 'struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS', - 'struct_NVA06C_CTRL_PREEMPT_PARAMS', - 'struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD', - 'struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS', - 'struct_NVA06C_CTRL_TIMESLICE_PARAMS', - 'struct_NVA06F_CTRL_BIND_PARAMS', - 'struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS', - 'struct_NVA081_CTRL_VGPU_INFO', - 'struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS', - 'struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS', - 'struct_NVXXXX_CTRL_XXX_INFO', 'struct_NV_CHANNEL_ALLOC_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS', - 'struct_NV_MEMORY_DESC_PARAMS', 'struct_Nv2080ACPIEvent', - 'struct_Nv2080AudioHdcpRequestRec', - 'struct_Nv2080ClocksChangeNotificationRec', - 'struct_Nv2080ClocksChangeNotificationRec_timeStamp', - 'struct_Nv2080DpIrqNotificationRec', - 'struct_Nv2080DstateHdaCodecNotificationRec', - 'struct_Nv2080DstateXusbPpcNotificationRec', - 'struct_Nv2080GC5GpuReadyParams', - 'struct_Nv2080HdcpStatusChangeNotificationRec', - 'struct_Nv2080HdmiFrlRequestNotificationRec', - 'struct_Nv2080PStateChangeNotificationRec', - 'struct_Nv2080PStateChangeNotificationRec_timeStamp', - 'struct_Nv2080WorkloadModulationChangeNotificationRec', - 'struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp', - 'struct_Nv2080XusbPpcConnectStateNotificationRec', - 'struct_Nvc56fControl_struct', 'struct_Nvc86fControl_struct', - 'struct_Nvc96fControl_struct', 'struct_RM_GSP_SPDM_CMD_CC_CTRL', - 'struct_RM_GSP_SPDM_CMD_CC_DEINIT', - 'struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', - 'struct_RM_GSP_SPDM_CMD_CC_INIT', - 'struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST', 'struct_RM_GSP_SPDM_MSG', - 'struct_RPC_METER_ENTRY', 'struct_RS_ACCESS_MASK', - 'struct_RS_SHARE_POLICY', 'struct_TEGRA_IMP_IMPORT_DATA', - 'struct_VPR_REQUEST_PARAMS', 'struct_VPR_STATUS_PARAMS', - 'struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC', - 'struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE', - 'struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS', - 'struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC', - 'struct__cl2080_tag0', 'struct__clc9b5_tag0', - 'struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS', - 'struct_c__SA_NVOS00_PARAMETERS', - 'struct_c__SA_NVOS02_PARAMETERS', - 'struct_c__SA_NVOS05_PARAMETERS', - 'struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK', - 'struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX', - 'struct_c__SA_NVOS21_PARAMETERS', - 'struct_c__SA_NVOS2C_PARAMETERS', - 'struct_c__SA_NVOS30_PARAMETERS', 'struct_c__SA_NVOS32_BLOCKINFO', - 'struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS', - 'struct_c__SA_NVOS32_HEAP_DUMP_BLOCK', - 'struct_c__SA_NVOS32_PARAMETERS', - 'struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocSize', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight', - 'struct_c__SA_NVOS32_PARAMETERS_0_Dump', - 'struct_c__SA_NVOS32_PARAMETERS_0_Free', - 'struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc', - 'struct_c__SA_NVOS32_PARAMETERS_0_HwFree', - 'struct_c__SA_NVOS32_PARAMETERS_0_Info', - 'struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr', - 'struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr', - 'struct_c__SA_NVOS33_PARAMETERS', - 'struct_c__SA_NVOS34_PARAMETERS', - 'struct_c__SA_NVOS38_PARAMETERS', - 'struct_c__SA_NVOS39_PARAMETERS', - 'struct_c__SA_NVOS41_PARAMETERS', - 'struct_c__SA_NVOS46_PARAMETERS', - 'struct_c__SA_NVOS47_PARAMETERS', - 'struct_c__SA_NVOS49_PARAMETERS', - 'struct_c__SA_NVOS54_PARAMETERS', - 'struct_c__SA_NVOS55_PARAMETERS', - 'struct_c__SA_NVOS56_PARAMETERS', - 'struct_c__SA_NVOS57_PARAMETERS', - 'struct_c__SA_NVOS61_PARAMETERS', - 'struct_c__SA_NVOS62_PARAMETERS', - 'struct_c__SA_NVOS63_PARAMETERS', - 'struct_c__SA_NVOS64_PARAMETERS', - 'struct_c__SA_NVOS65_PARAMETERS', - 'struct_c__SA_NVOS_I2C_ACCESS_PARAMS', - 'struct_c__SA_NVPOWERSTATE_PARAMETERS', - 'struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS', - 'struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_GR_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS', - 'struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS', - 'struct_c__SA_NV_ME_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS', - 'struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS', - 'struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS', - 'struct_c__SA_NV_VP_ALLOCATION_PARAMETERS', - 'struct_c__SA_Nv2080EccDbeNotification', - 'struct_c__SA_Nv2080HotplugNotification', - 'struct_c__SA_Nv2080LpwrDifrPrefetchNotification', - 'struct_c__SA_Nv2080NvlinkLnkChangeNotification', - 'struct_c__SA_Nv2080PowerEventNotification', - 'struct_c__SA_Nv2080PrivRegAccessFaultNotification', - 'struct_c__SA_Nv2080QosIntrNotification', - 'struct_c__SA_Nv2080VrrSetTimeoutNotification', - 'struct_c__SA_NvUnixEvent', 'struct_c__SA_UVM_ADD_SESSION_PARAMS', - 'struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS', - 'struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS', - 'struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS', - 'struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS', - 'struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS', - 'struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS', - 'struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS', - 'struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS', - 'struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS', - 'struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS', - 'struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS', - 'struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS', - 'struct_c__SA_UVM_EVENT_CTRL_PARAMS', - 'struct_c__SA_UVM_FREE_PARAMS', - 'struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS', - 'struct_c__SA_UVM_INITIALIZE_PARAMS', - 'struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS', - 'struct_c__SA_UVM_MAP_COUNTER_PARAMS', - 'struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS', - 'struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS', - 'struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS', - 'struct_c__SA_UVM_MEM_MAP_PARAMS', - 'struct_c__SA_UVM_MIGRATE_PARAMS', - 'struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_MM_INITIALIZE_PARAMS', - 'struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS', - 'struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS', - 'struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS', - 'struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS', - 'struct_c__SA_UVM_REGION_COMMIT_PARAMS', - 'struct_c__SA_UVM_REGION_DECOMMIT_PARAMS', - 'struct_c__SA_UVM_REGION_SET_STREAM_PARAMS', - 'struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS', - 'struct_c__SA_UVM_REGISTER_GPU_PARAMS', - 'struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS', - 'struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS', - 'struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS', - 'struct_c__SA_UVM_RELEASE_VA_PARAMS', - 'struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_REMOVE_SESSION_PARAMS', - 'struct_c__SA_UVM_RESERVE_VA_PARAMS', - 'struct_c__SA_UVM_RUN_TEST_PARAMS', - 'struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu', - 'struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS', - 'struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS', - 'struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS', - 'struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS', - 'struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS', - 'struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS', - 'struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS', - 'struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_GPU_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS', - 'struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS', - 'struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS', - 'struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS', - 'struct_c__SA_UvmCounterConfig', - 'struct_c__SA_UvmGpuMappingAttributes', - 'struct_c__SA_nv_ioctl_nvos02_parameters_with_fd', - 'struct_c__SA_nv_ioctl_nvos33_parameters_with_fd', - 'struct_c__SA_nv_pci_info_t', 'struct_nv_ioctl_alloc_os_event', - 'struct_nv_ioctl_card_info', - 'struct_nv_ioctl_export_to_dma_buf_fd', - 'struct_nv_ioctl_free_os_event', 'struct_nv_ioctl_numa_info', - 'struct_nv_ioctl_query_device_intr', - 'struct_nv_ioctl_register_fd', 'struct_nv_ioctl_rm_api_version', - 'struct_nv_ioctl_set_numa_status', 'struct_nv_ioctl_status_code', - 'struct_nv_ioctl_sys_params', - 'struct_nv_ioctl_wait_open_complete', 'struct_nv_ioctl_xfer', - 'struct_nv_uuid', 'struct_offline_addresses', 'union_CC_KMB_0', - 'union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data', - 'union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam', - 'union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data', - 'union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data', - 'union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value', - 'union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams', - 'union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data', - 'union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString', - 'union_NV2080_CTRL_GPU_PID_INFO_DATA', - 'union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData', - 'union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams', - 'union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams', - 'union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data', - 'union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData', - 'union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE', - 'union_RM_GSP_SPDM_CMD', 'union_c__SA_NVOS32_PARAMETERS_data'] -NVCEC0_QMDV05_00_RELEASE0_ENABLE=NVCEC0_QMDV05_00_RELEASE_ENABLE(0) -NVCEC0_QMDV05_00_RELEASE1_ENABLE=NVCEC0_QMDV05_00_RELEASE_ENABLE(1) # macro -nv_status_codes = {} -NV_OK = 0x00000000 -nv_status_codes[NV_OK] = "Success" -NV_ERR_GENERIC = 0x0000FFFF -nv_status_codes[NV_ERR_GENERIC] = "Failure: Generic Error" -NV_ERR_BROKEN_FB = 0x00000001 -nv_status_codes[NV_ERR_BROKEN_FB] = "Frame-Buffer broken" -NV_ERR_BUFFER_TOO_SMALL = 0x00000002 -nv_status_codes[NV_ERR_BUFFER_TOO_SMALL] = "Buffer passed in is too small" -NV_ERR_BUSY_RETRY = 0x00000003 -nv_status_codes[NV_ERR_BUSY_RETRY] = "System is busy, retry later" -NV_ERR_CALLBACK_NOT_SCHEDULED = 0x00000004 -nv_status_codes[NV_ERR_CALLBACK_NOT_SCHEDULED] = "The requested callback API not scheduled" -NV_ERR_CARD_NOT_PRESENT = 0x00000005 -nv_status_codes[NV_ERR_CARD_NOT_PRESENT] = "Card not detected" -NV_ERR_CYCLE_DETECTED = 0x00000006 -nv_status_codes[NV_ERR_CYCLE_DETECTED] = "Call cycle detected" -NV_ERR_DMA_IN_USE = 0x00000007 -nv_status_codes[NV_ERR_DMA_IN_USE] = "Requested DMA is in use" -NV_ERR_DMA_MEM_NOT_LOCKED = 0x00000008 -nv_status_codes[NV_ERR_DMA_MEM_NOT_LOCKED] = "Requested DMA memory is not locked" -NV_ERR_DMA_MEM_NOT_UNLOCKED = 0x00000009 -nv_status_codes[NV_ERR_DMA_MEM_NOT_UNLOCKED] = "Requested DMA memory is not unlocked" -NV_ERR_DUAL_LINK_INUSE = 0x0000000A -nv_status_codes[NV_ERR_DUAL_LINK_INUSE] = "Dual-Link is in use" -NV_ERR_ECC_ERROR = 0x0000000B -nv_status_codes[NV_ERR_ECC_ERROR] = "Generic ECC error" -NV_ERR_FIFO_BAD_ACCESS = 0x0000000C -nv_status_codes[NV_ERR_FIFO_BAD_ACCESS] = "FIFO: Invalid access" -NV_ERR_FREQ_NOT_SUPPORTED = 0x0000000D -nv_status_codes[NV_ERR_FREQ_NOT_SUPPORTED] = "Requested frequency is not supported" -NV_ERR_GPU_DMA_NOT_INITIALIZED = 0x0000000E -nv_status_codes[NV_ERR_GPU_DMA_NOT_INITIALIZED] = "Requested DMA not initialized" -NV_ERR_GPU_IS_LOST = 0x0000000F -nv_status_codes[NV_ERR_GPU_IS_LOST] = "GPU lost from the bus" -NV_ERR_GPU_IN_FULLCHIP_RESET = 0x00000010 -nv_status_codes[NV_ERR_GPU_IN_FULLCHIP_RESET] = "GPU currently in full-chip reset" -NV_ERR_GPU_NOT_FULL_POWER = 0x00000011 -nv_status_codes[NV_ERR_GPU_NOT_FULL_POWER] = "GPU not in full power" -NV_ERR_GPU_UUID_NOT_FOUND = 0x00000012 -nv_status_codes[NV_ERR_GPU_UUID_NOT_FOUND] = "GPU UUID not found" -NV_ERR_HOT_SWITCH = 0x00000013 -nv_status_codes[NV_ERR_HOT_SWITCH] = "System in hot switch" -NV_ERR_I2C_ERROR = 0x00000014 -nv_status_codes[NV_ERR_I2C_ERROR] = "I2C Error" -NV_ERR_I2C_SPEED_TOO_HIGH = 0x00000015 -nv_status_codes[NV_ERR_I2C_SPEED_TOO_HIGH] = "I2C Error: Speed too high" -NV_ERR_ILLEGAL_ACTION = 0x00000016 -nv_status_codes[NV_ERR_ILLEGAL_ACTION] = "Current action is not allowed" -NV_ERR_IN_USE = 0x00000017 -nv_status_codes[NV_ERR_IN_USE] = "Generic busy error" -NV_ERR_INFLATE_COMPRESSED_DATA_FAILED = 0x00000018 -nv_status_codes[NV_ERR_INFLATE_COMPRESSED_DATA_FAILED] = "Failed to inflate compressed data" -NV_ERR_INSERT_DUPLICATE_NAME = 0x00000019 -nv_status_codes[NV_ERR_INSERT_DUPLICATE_NAME] = "Found a duplicate entry in the requested btree" -NV_ERR_INSUFFICIENT_RESOURCES = 0x0000001A -nv_status_codes[NV_ERR_INSUFFICIENT_RESOURCES] = "Ran out of a critical resource, other than memory" -NV_ERR_INSUFFICIENT_PERMISSIONS = 0x0000001B -nv_status_codes[NV_ERR_INSUFFICIENT_PERMISSIONS] = "The requester does not have sufficient permissions" -NV_ERR_INSUFFICIENT_POWER = 0x0000001C -nv_status_codes[NV_ERR_INSUFFICIENT_POWER] = "Generic Error: Low power" -NV_ERR_INVALID_ACCESS_TYPE = 0x0000001D -nv_status_codes[NV_ERR_INVALID_ACCESS_TYPE] = "This type of access is not allowed" -NV_ERR_INVALID_ADDRESS = 0x0000001E -nv_status_codes[NV_ERR_INVALID_ADDRESS] = "Address not valid" -NV_ERR_INVALID_ARGUMENT = 0x0000001F -nv_status_codes[NV_ERR_INVALID_ARGUMENT] = "Invalid argument to call" -NV_ERR_INVALID_BASE = 0x00000020 -nv_status_codes[NV_ERR_INVALID_BASE] = "Invalid base" -NV_ERR_INVALID_CHANNEL = 0x00000021 -nv_status_codes[NV_ERR_INVALID_CHANNEL] = "Given channel-id not valid" -NV_ERR_INVALID_CLASS = 0x00000022 -nv_status_codes[NV_ERR_INVALID_CLASS] = "Given class-id not valid" -NV_ERR_INVALID_CLIENT = 0x00000023 -nv_status_codes[NV_ERR_INVALID_CLIENT] = "Given client not valid" -NV_ERR_INVALID_COMMAND = 0x00000024 -nv_status_codes[NV_ERR_INVALID_COMMAND] = "Command passed is not valid" -NV_ERR_INVALID_DATA = 0x00000025 -nv_status_codes[NV_ERR_INVALID_DATA] = "Invalid data passed" -NV_ERR_INVALID_DEVICE = 0x00000026 -nv_status_codes[NV_ERR_INVALID_DEVICE] = "Current device is not valid" -NV_ERR_INVALID_DMA_SPECIFIER = 0x00000027 -nv_status_codes[NV_ERR_INVALID_DMA_SPECIFIER] = "The requested DMA specifier is not valid" -NV_ERR_INVALID_EVENT = 0x00000028 -nv_status_codes[NV_ERR_INVALID_EVENT] = "Invalid event occurred" -NV_ERR_INVALID_FLAGS = 0x00000029 -nv_status_codes[NV_ERR_INVALID_FLAGS] = "Invalid flags passed" -NV_ERR_INVALID_FUNCTION = 0x0000002A -nv_status_codes[NV_ERR_INVALID_FUNCTION] = "Called function is not valid" -NV_ERR_INVALID_HEAP = 0x0000002B -nv_status_codes[NV_ERR_INVALID_HEAP] = "Heap corrupted" -NV_ERR_INVALID_INDEX = 0x0000002C -nv_status_codes[NV_ERR_INVALID_INDEX] = "Index invalid" -NV_ERR_INVALID_IRQ_LEVEL = 0x0000002D -nv_status_codes[NV_ERR_INVALID_IRQ_LEVEL] = "Requested IRQ level is not valid" -NV_ERR_INVALID_LIMIT = 0x0000002E -nv_status_codes[NV_ERR_INVALID_LIMIT] = "Generic Error: Invalid limit" -NV_ERR_INVALID_LOCK_STATE = 0x0000002F -nv_status_codes[NV_ERR_INVALID_LOCK_STATE] = "Requested lock state not valid" -NV_ERR_INVALID_METHOD = 0x00000030 -nv_status_codes[NV_ERR_INVALID_METHOD] = "Requested method not valid" -NV_ERR_INVALID_OBJECT = 0x00000031 -nv_status_codes[NV_ERR_INVALID_OBJECT] = "Object not valid" -NV_ERR_INVALID_OBJECT_BUFFER = 0x00000032 -nv_status_codes[NV_ERR_INVALID_OBJECT_BUFFER] = "Object buffer passed is not valid" -NV_ERR_INVALID_OBJECT_HANDLE = 0x00000033 -nv_status_codes[NV_ERR_INVALID_OBJECT_HANDLE] = "Object handle is not valid" -NV_ERR_INVALID_OBJECT_NEW = 0x00000034 -nv_status_codes[NV_ERR_INVALID_OBJECT_NEW] = "New object is not valid" -NV_ERR_INVALID_OBJECT_OLD = 0x00000035 -nv_status_codes[NV_ERR_INVALID_OBJECT_OLD] = "Old object is not valid" -NV_ERR_INVALID_OBJECT_PARENT = 0x00000036 -nv_status_codes[NV_ERR_INVALID_OBJECT_PARENT] = "Object parent is not valid" -NV_ERR_INVALID_OFFSET = 0x00000037 -nv_status_codes[NV_ERR_INVALID_OFFSET] = "The offset passed is not valid" -NV_ERR_INVALID_OPERATION = 0x00000038 -nv_status_codes[NV_ERR_INVALID_OPERATION] = "Requested operation is not valid" -NV_ERR_INVALID_OWNER = 0x00000039 -nv_status_codes[NV_ERR_INVALID_OWNER] = "Owner not valid" -NV_ERR_INVALID_PARAM_STRUCT = 0x0000003A -nv_status_codes[NV_ERR_INVALID_PARAM_STRUCT] = "Invalid structure parameter" -NV_ERR_INVALID_PARAMETER = 0x0000003B -nv_status_codes[NV_ERR_INVALID_PARAMETER] = "At least one of the parameters passed is not valid" -NV_ERR_INVALID_PATH = 0x0000003C -nv_status_codes[NV_ERR_INVALID_PATH] = "The requested path is not valid" -NV_ERR_INVALID_POINTER = 0x0000003D -nv_status_codes[NV_ERR_INVALID_POINTER] = "Pointer not valid" -NV_ERR_INVALID_REGISTRY_KEY = 0x0000003E -nv_status_codes[NV_ERR_INVALID_REGISTRY_KEY] = "Found an invalid registry key" -NV_ERR_INVALID_REQUEST = 0x0000003F -nv_status_codes[NV_ERR_INVALID_REQUEST] = "Generic Error: Invalid request" -NV_ERR_INVALID_STATE = 0x00000040 -nv_status_codes[NV_ERR_INVALID_STATE] = "Generic Error: Invalid state" -NV_ERR_INVALID_STRING_LENGTH = 0x00000041 -nv_status_codes[NV_ERR_INVALID_STRING_LENGTH] = "The string length is not valid" -NV_ERR_INVALID_READ = 0x00000042 -nv_status_codes[NV_ERR_INVALID_READ] = "The requested read operation is not valid" -NV_ERR_INVALID_WRITE = 0x00000043 -nv_status_codes[NV_ERR_INVALID_WRITE] = "The requested write operation is not valid" -NV_ERR_INVALID_XLATE = 0x00000044 -nv_status_codes[NV_ERR_INVALID_XLATE] = "The requested translate operation is not valid" -NV_ERR_IRQ_NOT_FIRING = 0x00000045 -nv_status_codes[NV_ERR_IRQ_NOT_FIRING] = "Requested IRQ is not firing" -NV_ERR_IRQ_EDGE_TRIGGERED = 0x00000046 -nv_status_codes[NV_ERR_IRQ_EDGE_TRIGGERED] = "IRQ is edge triggered" -NV_ERR_MEMORY_TRAINING_FAILED = 0x00000047 -nv_status_codes[NV_ERR_MEMORY_TRAINING_FAILED] = "Failed memory training sequence" -NV_ERR_MISMATCHED_SLAVE = 0x00000048 -nv_status_codes[NV_ERR_MISMATCHED_SLAVE] = "Slave mismatch" -NV_ERR_MISMATCHED_TARGET = 0x00000049 -nv_status_codes[NV_ERR_MISMATCHED_TARGET] = "Target mismatch" -NV_ERR_MISSING_TABLE_ENTRY = 0x0000004A -nv_status_codes[NV_ERR_MISSING_TABLE_ENTRY] = "Requested entry missing not found in the table" -NV_ERR_MODULE_LOAD_FAILED = 0x0000004B -nv_status_codes[NV_ERR_MODULE_LOAD_FAILED] = "Failed to load the requested module" -NV_ERR_MORE_DATA_AVAILABLE = 0x0000004C -nv_status_codes[NV_ERR_MORE_DATA_AVAILABLE] = "There is more data available" -NV_ERR_MORE_PROCESSING_REQUIRED = 0x0000004D -nv_status_codes[NV_ERR_MORE_PROCESSING_REQUIRED] = "More processing required for the given call" -NV_ERR_MULTIPLE_MEMORY_TYPES = 0x0000004E -nv_status_codes[NV_ERR_MULTIPLE_MEMORY_TYPES] = "Multiple memory types found" -NV_ERR_NO_FREE_FIFOS = 0x0000004F -nv_status_codes[NV_ERR_NO_FREE_FIFOS] = "No more free FIFOs found" -NV_ERR_NO_INTR_PENDING = 0x00000050 -nv_status_codes[NV_ERR_NO_INTR_PENDING] = "No interrupt pending" -NV_ERR_NO_MEMORY = 0x00000051 -nv_status_codes[NV_ERR_NO_MEMORY] = "Out of memory" -NV_ERR_NO_SUCH_DOMAIN = 0x00000052 -nv_status_codes[NV_ERR_NO_SUCH_DOMAIN] = "Requested domain does not exist" -NV_ERR_NO_VALID_PATH = 0x00000053 -nv_status_codes[NV_ERR_NO_VALID_PATH] = "Caller did not specify a valid path" -NV_ERR_NOT_COMPATIBLE = 0x00000054 -nv_status_codes[NV_ERR_NOT_COMPATIBLE] = "Generic Error: Incompatible types" -NV_ERR_NOT_READY = 0x00000055 -nv_status_codes[NV_ERR_NOT_READY] = "Generic Error: Not ready" -NV_ERR_NOT_SUPPORTED = 0x00000056 -nv_status_codes[NV_ERR_NOT_SUPPORTED] = "Call not supported" -NV_ERR_OBJECT_NOT_FOUND = 0x00000057 -nv_status_codes[NV_ERR_OBJECT_NOT_FOUND] = "Requested object not found" -NV_ERR_OBJECT_TYPE_MISMATCH = 0x00000058 -nv_status_codes[NV_ERR_OBJECT_TYPE_MISMATCH] = "Specified objects do not match" -NV_ERR_OPERATING_SYSTEM = 0x00000059 -nv_status_codes[NV_ERR_OPERATING_SYSTEM] = "Generic operating system error" -NV_ERR_OTHER_DEVICE_FOUND = 0x0000005A -nv_status_codes[NV_ERR_OTHER_DEVICE_FOUND] = "Found other device instead of the requested one" -NV_ERR_OUT_OF_RANGE = 0x0000005B -nv_status_codes[NV_ERR_OUT_OF_RANGE] = "The specified value is out of bounds" -NV_ERR_OVERLAPPING_UVM_COMMIT = 0x0000005C -nv_status_codes[NV_ERR_OVERLAPPING_UVM_COMMIT] = "Overlapping unified virtual memory commit" -NV_ERR_PAGE_TABLE_NOT_AVAIL = 0x0000005D -nv_status_codes[NV_ERR_PAGE_TABLE_NOT_AVAIL] = "Requested page table not available" -NV_ERR_PID_NOT_FOUND = 0x0000005E -nv_status_codes[NV_ERR_PID_NOT_FOUND] = "Process-Id not found" -NV_ERR_PROTECTION_FAULT = 0x0000005F -nv_status_codes[NV_ERR_PROTECTION_FAULT] = "Protection fault" -NV_ERR_RC_ERROR = 0x00000060 -nv_status_codes[NV_ERR_RC_ERROR] = "Generic RC error" -NV_ERR_REJECTED_VBIOS = 0x00000061 -nv_status_codes[NV_ERR_REJECTED_VBIOS] = "Given Video BIOS rejected/invalid" -NV_ERR_RESET_REQUIRED = 0x00000062 -nv_status_codes[NV_ERR_RESET_REQUIRED] = "Reset required" -NV_ERR_STATE_IN_USE = 0x00000063 -nv_status_codes[NV_ERR_STATE_IN_USE] = "State in use" -NV_ERR_SIGNAL_PENDING = 0x00000064 -nv_status_codes[NV_ERR_SIGNAL_PENDING] = "Signal pending" -NV_ERR_TIMEOUT = 0x00000065 -nv_status_codes[NV_ERR_TIMEOUT] = "Call timed out" -NV_ERR_TIMEOUT_RETRY = 0x00000066 -nv_status_codes[NV_ERR_TIMEOUT_RETRY] = "Call timed out, please retry later" -NV_ERR_TOO_MANY_PRIMARIES = 0x00000067 -nv_status_codes[NV_ERR_TOO_MANY_PRIMARIES] = "Too many primaries" -NV_ERR_UVM_ADDRESS_IN_USE = 0x00000068 -nv_status_codes[NV_ERR_UVM_ADDRESS_IN_USE] = "Unified virtual memory requested address already in use" -NV_ERR_MAX_SESSION_LIMIT_REACHED = 0x00000069 -nv_status_codes[NV_ERR_MAX_SESSION_LIMIT_REACHED] = "Maximum number of sessions reached" -NV_ERR_LIB_RM_VERSION_MISMATCH = 0x0000006A -nv_status_codes[NV_ERR_LIB_RM_VERSION_MISMATCH] = "Library version doesn't match driver version" -NV_ERR_PRIV_SEC_VIOLATION = 0x0000006B -nv_status_codes[NV_ERR_PRIV_SEC_VIOLATION] = "Priv security violation" -NV_ERR_GPU_IN_DEBUG_MODE = 0x0000006C -nv_status_codes[NV_ERR_GPU_IN_DEBUG_MODE] = "GPU currently in debug mode" -NV_ERR_FEATURE_NOT_ENABLED = 0x0000006D -nv_status_codes[NV_ERR_FEATURE_NOT_ENABLED] = "Requested Feature functionality is not enabled" -NV_ERR_RESOURCE_LOST = 0x0000006E -nv_status_codes[NV_ERR_RESOURCE_LOST] = "Requested resource has been destroyed" -NV_ERR_PMU_NOT_READY = 0x0000006F -nv_status_codes[NV_ERR_PMU_NOT_READY] = "PMU is not ready or has not yet been initialized" -NV_ERR_FLCN_ERROR = 0x00000070 -nv_status_codes[NV_ERR_FLCN_ERROR] = "Generic falcon assert or halt" -NV_ERR_FATAL_ERROR = 0x00000071 -nv_status_codes[NV_ERR_FATAL_ERROR] = "Fatal/unrecoverable error" -NV_ERR_MEMORY_ERROR = 0x00000072 -nv_status_codes[NV_ERR_MEMORY_ERROR] = "Generic memory error" -NV_ERR_INVALID_LICENSE = 0x00000073 -nv_status_codes[NV_ERR_INVALID_LICENSE] = "License provided is rejected or invalid" -NV_ERR_NVLINK_INIT_ERROR = 0x00000074 -nv_status_codes[NV_ERR_NVLINK_INIT_ERROR] = "Nvlink Init Error" -NV_ERR_NVLINK_MINION_ERROR = 0x00000075 -nv_status_codes[NV_ERR_NVLINK_MINION_ERROR] = "Nvlink Minion Error" -NV_ERR_NVLINK_CLOCK_ERROR = 0x00000076 -nv_status_codes[NV_ERR_NVLINK_CLOCK_ERROR] = "Nvlink Clock Error" -NV_ERR_NVLINK_TRAINING_ERROR = 0x00000077 -nv_status_codes[NV_ERR_NVLINK_TRAINING_ERROR] = "Nvlink Training Error" -NV_ERR_NVLINK_CONFIGURATION_ERROR = 0x00000078 -nv_status_codes[NV_ERR_NVLINK_CONFIGURATION_ERROR] = "Nvlink Configuration Error" -NV_ERR_RISCV_ERROR = 0x00000079 -nv_status_codes[NV_ERR_RISCV_ERROR] = "Generic RISC-V assert or halt" -NV_ERR_FABRIC_MANAGER_NOT_PRESENT = 0x0000007A -nv_status_codes[NV_ERR_FABRIC_MANAGER_NOT_PRESENT] = "Fabric Manager is not loaded" -NV_ERR_ALREADY_SIGNALLED = 0x0000007B -nv_status_codes[NV_ERR_ALREADY_SIGNALLED] = "Semaphore Surface value already >= requested wait value" -NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE = 0x0000007C -nv_status_codes[NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE] = "PMU RPC error due to no queue slot available for this event" -NV_ERR_KEY_ROTATION_IN_PROGRESS = 0x0000007D -nv_status_codes[NV_ERR_KEY_ROTATION_IN_PROGRESS] = "Operation not allowed as key rotation is in progress" -NV_ERR_TEST_ONLY_CODE_NOT_ENABLED = 0x0000007E -nv_status_codes[NV_ERR_TEST_ONLY_CODE_NOT_ENABLED] = "Test-only code path not enabled" -NV_ERR_SECURE_BOOT_FAILED = 0x0000007F -nv_status_codes[NV_ERR_SECURE_BOOT_FAILED] = "GFW secure boot failed" -NV_ERR_INSUFFICIENT_ZBC_ENTRY = 0x00000080 -nv_status_codes[NV_ERR_INSUFFICIENT_ZBC_ENTRY] = "No more ZBC entry for the client" -NV_ERR_NVLINK_FABRIC_NOT_READY = 0x00000081 -nv_status_codes[NV_ERR_NVLINK_FABRIC_NOT_READY] = "Nvlink Fabric Status or Fabric Probe is not yet complete, caller needs to retry" -NV_ERR_NVLINK_FABRIC_FAILURE = 0x00000082 -nv_status_codes[NV_ERR_NVLINK_FABRIC_FAILURE] = "Nvlink Fabric Probe failed" -NV_ERR_GPU_MEMORY_ONLINING_FAILURE = 0x00000083 -nv_status_codes[NV_ERR_GPU_MEMORY_ONLINING_FAILURE] = "GPU Memory Onlining failed" -NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE = 0x00000084 -nv_status_codes[NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE] = "Reduction Manager is not available" -NV_WARN_HOT_SWITCH = 0x00010001 -nv_status_codes[NV_WARN_HOT_SWITCH] = "WARNING Hot switch" -NV_WARN_INCORRECT_PERFMON_DATA = 0x00010002 -nv_status_codes[NV_WARN_INCORRECT_PERFMON_DATA] = "WARNING Incorrect performance monitor data" -NV_WARN_MISMATCHED_SLAVE = 0x00010003 -nv_status_codes[NV_WARN_MISMATCHED_SLAVE] = "WARNING Slave mismatch" -NV_WARN_MISMATCHED_TARGET = 0x00010004 -nv_status_codes[NV_WARN_MISMATCHED_TARGET] = "WARNING Target mismatch" -NV_WARN_MORE_PROCESSING_REQUIRED = 0x00010005 -nv_status_codes[NV_WARN_MORE_PROCESSING_REQUIRED] = "WARNING More processing required for the call" -NV_WARN_NOTHING_TO_DO = 0x00010006 -nv_status_codes[NV_WARN_NOTHING_TO_DO] = "WARNING Nothing to do" -NV_WARN_NULL_OBJECT = 0x00010007 -nv_status_codes[NV_WARN_NULL_OBJECT] = "WARNING NULL object found" -NV_WARN_OUT_OF_RANGE = 0x00010008 -nv_status_codes[NV_WARN_OUT_OF_RANGE] = "WARNING value out of range" diff --git a/tinygrad/tinygrad/runtime/autogen/nvrtc.py b/tinygrad/tinygrad/runtime/autogen/nvrtc.py deleted file mode 100644 index 6af74187..00000000 --- a/tinygrad/tinygrad/runtime/autogen/nvrtc.py +++ /dev/null @@ -1,579 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -_libraries = {} -_libraries['libnvrtc.so'] = ctypes.CDLL(ctypes.util.find_library('nvrtc')) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -_libraries['libnvJitLink.so'] = ctypes.CDLL(ctypes.util.find_library('nvJitLink')) -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - - -# values for enumeration 'c__EA_nvrtcResult' -c__EA_nvrtcResult__enumvalues = { - 0: 'NVRTC_SUCCESS', - 1: 'NVRTC_ERROR_OUT_OF_MEMORY', - 2: 'NVRTC_ERROR_PROGRAM_CREATION_FAILURE', - 3: 'NVRTC_ERROR_INVALID_INPUT', - 4: 'NVRTC_ERROR_INVALID_PROGRAM', - 5: 'NVRTC_ERROR_INVALID_OPTION', - 6: 'NVRTC_ERROR_COMPILATION', - 7: 'NVRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 8: 'NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 9: 'NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 10: 'NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 11: 'NVRTC_ERROR_INTERNAL_ERROR', - 12: 'NVRTC_ERROR_TIME_FILE_WRITE_FAILED', -} -NVRTC_SUCCESS = 0 -NVRTC_ERROR_OUT_OF_MEMORY = 1 -NVRTC_ERROR_PROGRAM_CREATION_FAILURE = 2 -NVRTC_ERROR_INVALID_INPUT = 3 -NVRTC_ERROR_INVALID_PROGRAM = 4 -NVRTC_ERROR_INVALID_OPTION = 5 -NVRTC_ERROR_COMPILATION = 6 -NVRTC_ERROR_BUILTIN_OPERATION_FAILURE = 7 -NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = 8 -NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = 9 -NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID = 10 -NVRTC_ERROR_INTERNAL_ERROR = 11 -NVRTC_ERROR_TIME_FILE_WRITE_FAILED = 12 -c__EA_nvrtcResult = ctypes.c_uint32 # enum -nvrtcResult = c__EA_nvrtcResult -nvrtcResult__enumvalues = c__EA_nvrtcResult__enumvalues -try: - nvrtcGetErrorString = _libraries['libnvrtc.so'].nvrtcGetErrorString - nvrtcGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - nvrtcGetErrorString.argtypes = [nvrtcResult] -except AttributeError: - pass -try: - nvrtcVersion = _libraries['libnvrtc.so'].nvrtcVersion - nvrtcVersion.restype = nvrtcResult - nvrtcVersion.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - nvrtcGetNumSupportedArchs = _libraries['libnvrtc.so'].nvrtcGetNumSupportedArchs - nvrtcGetNumSupportedArchs.restype = nvrtcResult - nvrtcGetNumSupportedArchs.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - nvrtcGetSupportedArchs = _libraries['libnvrtc.so'].nvrtcGetSupportedArchs - nvrtcGetSupportedArchs.restype = nvrtcResult - nvrtcGetSupportedArchs.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -class struct__nvrtcProgram(Structure): - pass - -nvrtcProgram = ctypes.POINTER(struct__nvrtcProgram) -try: - nvrtcCreateProgram = _libraries['libnvrtc.so'].nvrtcCreateProgram - nvrtcCreateProgram.restype = nvrtcResult - nvrtcCreateProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__nvrtcProgram)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvrtcDestroyProgram = _libraries['libnvrtc.so'].nvrtcDestroyProgram - nvrtcDestroyProgram.restype = nvrtcResult - nvrtcDestroyProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__nvrtcProgram))] -except AttributeError: - pass -try: - nvrtcCompileProgram = _libraries['libnvrtc.so'].nvrtcCompileProgram - nvrtcCompileProgram.restype = nvrtcResult - nvrtcCompileProgram.argtypes = [nvrtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvrtcGetPTXSize = _libraries['libnvrtc.so'].nvrtcGetPTXSize - nvrtcGetPTXSize.restype = nvrtcResult - nvrtcGetPTXSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetPTX = _libraries['libnvrtc.so'].nvrtcGetPTX - nvrtcGetPTX.restype = nvrtcResult - nvrtcGetPTX.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetCUBINSize = _libraries['libnvrtc.so'].nvrtcGetCUBINSize - nvrtcGetCUBINSize.restype = nvrtcResult - nvrtcGetCUBINSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetCUBIN = _libraries['libnvrtc.so'].nvrtcGetCUBIN - nvrtcGetCUBIN.restype = nvrtcResult - nvrtcGetCUBIN.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetNVVMSize = _libraries['libnvrtc.so'].nvrtcGetNVVMSize - nvrtcGetNVVMSize.restype = nvrtcResult - nvrtcGetNVVMSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetNVVM = _libraries['libnvrtc.so'].nvrtcGetNVVM - nvrtcGetNVVM.restype = nvrtcResult - nvrtcGetNVVM.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetLTOIRSize = _libraries['libnvrtc.so'].nvrtcGetLTOIRSize - nvrtcGetLTOIRSize.restype = nvrtcResult - nvrtcGetLTOIRSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetLTOIR = _libraries['libnvrtc.so'].nvrtcGetLTOIR - nvrtcGetLTOIR.restype = nvrtcResult - nvrtcGetLTOIR.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetOptiXIRSize = _libraries['libnvrtc.so'].nvrtcGetOptiXIRSize - nvrtcGetOptiXIRSize.restype = nvrtcResult - nvrtcGetOptiXIRSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetOptiXIR = _libraries['libnvrtc.so'].nvrtcGetOptiXIR - nvrtcGetOptiXIR.restype = nvrtcResult - nvrtcGetOptiXIR.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetProgramLogSize = _libraries['libnvrtc.so'].nvrtcGetProgramLogSize - nvrtcGetProgramLogSize.restype = nvrtcResult - nvrtcGetProgramLogSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetProgramLog = _libraries['libnvrtc.so'].nvrtcGetProgramLog - nvrtcGetProgramLog.restype = nvrtcResult - nvrtcGetProgramLog.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcAddNameExpression = _libraries['libnvrtc.so'].nvrtcAddNameExpression - nvrtcAddNameExpression.restype = nvrtcResult - nvrtcAddNameExpression.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetLoweredName = _libraries['libnvrtc.so'].nvrtcGetLoweredName - nvrtcGetLoweredName.restype = nvrtcResult - nvrtcGetLoweredName.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass - -# values for enumeration 'c__EA_nvJitLinkResult' -c__EA_nvJitLinkResult__enumvalues = { - 0: 'NVJITLINK_SUCCESS', - 1: 'NVJITLINK_ERROR_UNRECOGNIZED_OPTION', - 2: 'NVJITLINK_ERROR_MISSING_ARCH', - 3: 'NVJITLINK_ERROR_INVALID_INPUT', - 4: 'NVJITLINK_ERROR_PTX_COMPILE', - 5: 'NVJITLINK_ERROR_NVVM_COMPILE', - 6: 'NVJITLINK_ERROR_INTERNAL', - 7: 'NVJITLINK_ERROR_THREADPOOL', - 8: 'NVJITLINK_ERROR_UNRECOGNIZED_INPUT', -} -NVJITLINK_SUCCESS = 0 -NVJITLINK_ERROR_UNRECOGNIZED_OPTION = 1 -NVJITLINK_ERROR_MISSING_ARCH = 2 -NVJITLINK_ERROR_INVALID_INPUT = 3 -NVJITLINK_ERROR_PTX_COMPILE = 4 -NVJITLINK_ERROR_NVVM_COMPILE = 5 -NVJITLINK_ERROR_INTERNAL = 6 -NVJITLINK_ERROR_THREADPOOL = 7 -NVJITLINK_ERROR_UNRECOGNIZED_INPUT = 8 -c__EA_nvJitLinkResult = ctypes.c_uint32 # enum -nvJitLinkResult = c__EA_nvJitLinkResult -nvJitLinkResult__enumvalues = c__EA_nvJitLinkResult__enumvalues - -# values for enumeration 'c__EA_nvJitLinkInputType' -c__EA_nvJitLinkInputType__enumvalues = { - 0: 'NVJITLINK_INPUT_NONE', - 1: 'NVJITLINK_INPUT_CUBIN', - 2: 'NVJITLINK_INPUT_PTX', - 3: 'NVJITLINK_INPUT_LTOIR', - 4: 'NVJITLINK_INPUT_FATBIN', - 5: 'NVJITLINK_INPUT_OBJECT', - 6: 'NVJITLINK_INPUT_LIBRARY', - 10: 'NVJITLINK_INPUT_ANY', -} -NVJITLINK_INPUT_NONE = 0 -NVJITLINK_INPUT_CUBIN = 1 -NVJITLINK_INPUT_PTX = 2 -NVJITLINK_INPUT_LTOIR = 3 -NVJITLINK_INPUT_FATBIN = 4 -NVJITLINK_INPUT_OBJECT = 5 -NVJITLINK_INPUT_LIBRARY = 6 -NVJITLINK_INPUT_ANY = 10 -c__EA_nvJitLinkInputType = ctypes.c_uint32 # enum -nvJitLinkInputType = c__EA_nvJitLinkInputType -nvJitLinkInputType__enumvalues = c__EA_nvJitLinkInputType__enumvalues -class struct_nvJitLink(Structure): - pass - -nvJitLinkHandle = ctypes.POINTER(struct_nvJitLink) -uint32_t = ctypes.c_uint32 -try: - __nvJitLinkCreate_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkCreate_12_4 - __nvJitLinkCreate_12_4.restype = nvJitLinkResult - __nvJitLinkCreate_12_4.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink)), uint32_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvJitLinkCreate = _libraries['libnvJitLink.so'].nvJitLinkCreate - nvJitLinkCreate.restype = nvJitLinkResult - nvJitLinkCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink)), uint32_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - __nvJitLinkDestroy_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkDestroy_12_4 - __nvJitLinkDestroy_12_4.restype = nvJitLinkResult - __nvJitLinkDestroy_12_4.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink))] -except AttributeError: - pass -try: - nvJitLinkDestroy = _libraries['libnvJitLink.so'].nvJitLinkDestroy - nvJitLinkDestroy.restype = nvJitLinkResult - nvJitLinkDestroy.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink))] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - __nvJitLinkAddData_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkAddData_12_4 - __nvJitLinkAddData_12_4.restype = nvJitLinkResult - __nvJitLinkAddData_12_4.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkAddData = _libraries['libnvJitLink.so'].nvJitLinkAddData - nvJitLinkAddData.restype = nvJitLinkResult - nvJitLinkAddData.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkAddFile_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkAddFile_12_4 - __nvJitLinkAddFile_12_4.restype = nvJitLinkResult - __nvJitLinkAddFile_12_4.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkAddFile = _libraries['libnvJitLink.so'].nvJitLinkAddFile - nvJitLinkAddFile.restype = nvJitLinkResult - nvJitLinkAddFile.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkComplete_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkComplete_12_4 - __nvJitLinkComplete_12_4.restype = nvJitLinkResult - __nvJitLinkComplete_12_4.argtypes = [nvJitLinkHandle] -except AttributeError: - pass -try: - nvJitLinkComplete = _libraries['libnvJitLink.so'].nvJitLinkComplete - nvJitLinkComplete.restype = nvJitLinkResult - nvJitLinkComplete.argtypes = [nvJitLinkHandle] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedCubinSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedCubinSize_12_4 - __nvJitLinkGetLinkedCubinSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedCubinSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedCubinSize = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedCubinSize - nvJitLinkGetLinkedCubinSize.restype = nvJitLinkResult - nvJitLinkGetLinkedCubinSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedCubin_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedCubin_12_4 - __nvJitLinkGetLinkedCubin_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedCubin_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedCubin = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedCubin - nvJitLinkGetLinkedCubin.restype = nvJitLinkResult - nvJitLinkGetLinkedCubin.argtypes = [nvJitLinkHandle, ctypes.POINTER(None)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedPtxSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedPtxSize_12_4 - __nvJitLinkGetLinkedPtxSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedPtxSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedPtxSize = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedPtxSize - nvJitLinkGetLinkedPtxSize.restype = nvJitLinkResult - nvJitLinkGetLinkedPtxSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedPtx_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedPtx_12_4 - __nvJitLinkGetLinkedPtx_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedPtx_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedPtx = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedPtx - nvJitLinkGetLinkedPtx.restype = nvJitLinkResult - nvJitLinkGetLinkedPtx.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkGetErrorLogSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetErrorLogSize_12_4 - __nvJitLinkGetErrorLogSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetErrorLogSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetErrorLogSize = _libraries['libnvJitLink.so'].nvJitLinkGetErrorLogSize - nvJitLinkGetErrorLogSize.restype = nvJitLinkResult - nvJitLinkGetErrorLogSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetErrorLog_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetErrorLog_12_4 - __nvJitLinkGetErrorLog_12_4.restype = nvJitLinkResult - __nvJitLinkGetErrorLog_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetErrorLog = _libraries['libnvJitLink.so'].nvJitLinkGetErrorLog - nvJitLinkGetErrorLog.restype = nvJitLinkResult - nvJitLinkGetErrorLog.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkGetInfoLogSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetInfoLogSize_12_4 - __nvJitLinkGetInfoLogSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetInfoLogSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetInfoLogSize = _libraries['libnvJitLink.so'].nvJitLinkGetInfoLogSize - nvJitLinkGetInfoLogSize.restype = nvJitLinkResult - nvJitLinkGetInfoLogSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetInfoLog_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetInfoLog_12_4 - __nvJitLinkGetInfoLog_12_4.restype = nvJitLinkResult - __nvJitLinkGetInfoLog_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetInfoLog = _libraries['libnvJitLink.so'].nvJitLinkGetInfoLog - nvJitLinkGetInfoLog.restype = nvJitLinkResult - nvJitLinkGetInfoLog.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkVersion = _libraries['libnvJitLink.so'].nvJitLinkVersion - nvJitLinkVersion.restype = nvJitLinkResult - nvJitLinkVersion.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -__all__ = \ - ['NVJITLINK_ERROR_INTERNAL', 'NVJITLINK_ERROR_INVALID_INPUT', - 'NVJITLINK_ERROR_MISSING_ARCH', 'NVJITLINK_ERROR_NVVM_COMPILE', - 'NVJITLINK_ERROR_PTX_COMPILE', 'NVJITLINK_ERROR_THREADPOOL', - 'NVJITLINK_ERROR_UNRECOGNIZED_INPUT', - 'NVJITLINK_ERROR_UNRECOGNIZED_OPTION', 'NVJITLINK_INPUT_ANY', - 'NVJITLINK_INPUT_CUBIN', 'NVJITLINK_INPUT_FATBIN', - 'NVJITLINK_INPUT_LIBRARY', 'NVJITLINK_INPUT_LTOIR', - 'NVJITLINK_INPUT_NONE', 'NVJITLINK_INPUT_OBJECT', - 'NVJITLINK_INPUT_PTX', 'NVJITLINK_SUCCESS', - 'NVRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 'NVRTC_ERROR_COMPILATION', 'NVRTC_ERROR_INTERNAL_ERROR', - 'NVRTC_ERROR_INVALID_INPUT', 'NVRTC_ERROR_INVALID_OPTION', - 'NVRTC_ERROR_INVALID_PROGRAM', - 'NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 'NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 'NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 'NVRTC_ERROR_OUT_OF_MEMORY', - 'NVRTC_ERROR_PROGRAM_CREATION_FAILURE', - 'NVRTC_ERROR_TIME_FILE_WRITE_FAILED', 'NVRTC_SUCCESS', - '__nvJitLinkAddData_12_4', '__nvJitLinkAddFile_12_4', - '__nvJitLinkComplete_12_4', '__nvJitLinkCreate_12_4', - '__nvJitLinkDestroy_12_4', '__nvJitLinkGetErrorLogSize_12_4', - '__nvJitLinkGetErrorLog_12_4', '__nvJitLinkGetInfoLogSize_12_4', - '__nvJitLinkGetInfoLog_12_4', - '__nvJitLinkGetLinkedCubinSize_12_4', - '__nvJitLinkGetLinkedCubin_12_4', - '__nvJitLinkGetLinkedPtxSize_12_4', - '__nvJitLinkGetLinkedPtx_12_4', 'c__EA_nvJitLinkInputType', - 'c__EA_nvJitLinkResult', 'c__EA_nvrtcResult', 'nvJitLinkAddData', - 'nvJitLinkAddFile', 'nvJitLinkComplete', 'nvJitLinkCreate', - 'nvJitLinkDestroy', 'nvJitLinkGetErrorLog', - 'nvJitLinkGetErrorLogSize', 'nvJitLinkGetInfoLog', - 'nvJitLinkGetInfoLogSize', 'nvJitLinkGetLinkedCubin', - 'nvJitLinkGetLinkedCubinSize', 'nvJitLinkGetLinkedPtx', - 'nvJitLinkGetLinkedPtxSize', 'nvJitLinkHandle', - 'nvJitLinkInputType', 'nvJitLinkInputType__enumvalues', - 'nvJitLinkResult', 'nvJitLinkResult__enumvalues', - 'nvJitLinkVersion', 'nvrtcAddNameExpression', - 'nvrtcCompileProgram', 'nvrtcCreateProgram', - 'nvrtcDestroyProgram', 'nvrtcGetCUBIN', 'nvrtcGetCUBINSize', - 'nvrtcGetErrorString', 'nvrtcGetLTOIR', 'nvrtcGetLTOIRSize', - 'nvrtcGetLoweredName', 'nvrtcGetNVVM', 'nvrtcGetNVVMSize', - 'nvrtcGetNumSupportedArchs', 'nvrtcGetOptiXIR', - 'nvrtcGetOptiXIRSize', 'nvrtcGetPTX', 'nvrtcGetPTXSize', - 'nvrtcGetProgramLog', 'nvrtcGetProgramLogSize', - 'nvrtcGetSupportedArchs', 'nvrtcProgram', 'nvrtcResult', - 'nvrtcResult__enumvalues', 'nvrtcVersion', 'size_t', - 'struct__nvrtcProgram', 'struct_nvJitLink', 'uint32_t'] diff --git a/tinygrad/tinygrad/runtime/autogen/opencl.py b/tinygrad/tinygrad/runtime/autogen/opencl.py deleted file mode 100644 index e2f2691c..00000000 --- a/tinygrad/tinygrad/runtime/autogen/opencl.py +++ /dev/null @@ -1,1793 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -_libraries = {} -_libraries['libOpenCL.so.1'] = ctypes.CDLL(ctypes.util.find_library('OpenCL')) -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -__OPENCL_CL_H = True # macro -CL_NAME_VERSION_MAX_NAME_SIZE = 64 # macro -CL_SUCCESS = 0 # macro -CL_DEVICE_NOT_FOUND = -1 # macro -CL_DEVICE_NOT_AVAILABLE = -2 # macro -CL_COMPILER_NOT_AVAILABLE = -3 # macro -CL_MEM_OBJECT_ALLOCATION_FAILURE = -4 # macro -CL_OUT_OF_RESOURCES = -5 # macro -CL_OUT_OF_HOST_MEMORY = -6 # macro -CL_PROFILING_INFO_NOT_AVAILABLE = -7 # macro -CL_MEM_COPY_OVERLAP = -8 # macro -CL_IMAGE_FORMAT_MISMATCH = -9 # macro -CL_IMAGE_FORMAT_NOT_SUPPORTED = -10 # macro -CL_BUILD_PROGRAM_FAILURE = -11 # macro -CL_MAP_FAILURE = -12 # macro -CL_MISALIGNED_SUB_BUFFER_OFFSET = -13 # macro -CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST = -14 # macro -CL_COMPILE_PROGRAM_FAILURE = -15 # macro -CL_LINKER_NOT_AVAILABLE = -16 # macro -CL_LINK_PROGRAM_FAILURE = -17 # macro -CL_DEVICE_PARTITION_FAILED = -18 # macro -CL_KERNEL_ARG_INFO_NOT_AVAILABLE = -19 # macro -CL_INVALID_VALUE = -30 # macro -CL_INVALID_DEVICE_TYPE = -31 # macro -CL_INVALID_PLATFORM = -32 # macro -CL_INVALID_DEVICE = -33 # macro -CL_INVALID_CONTEXT = -34 # macro -CL_INVALID_QUEUE_PROPERTIES = -35 # macro -CL_INVALID_COMMAND_QUEUE = -36 # macro -CL_INVALID_HOST_PTR = -37 # macro -CL_INVALID_MEM_OBJECT = -38 # macro -CL_INVALID_IMAGE_FORMAT_DESCRIPTOR = -39 # macro -CL_INVALID_IMAGE_SIZE = -40 # macro -CL_INVALID_SAMPLER = -41 # macro -CL_INVALID_BINARY = -42 # macro -CL_INVALID_BUILD_OPTIONS = -43 # macro -CL_INVALID_PROGRAM = -44 # macro -CL_INVALID_PROGRAM_EXECUTABLE = -45 # macro -CL_INVALID_KERNEL_NAME = -46 # macro -CL_INVALID_KERNEL_DEFINITION = -47 # macro -CL_INVALID_KERNEL = -48 # macro -CL_INVALID_ARG_INDEX = -49 # macro -CL_INVALID_ARG_VALUE = -50 # macro -CL_INVALID_ARG_SIZE = -51 # macro -CL_INVALID_KERNEL_ARGS = -52 # macro -CL_INVALID_WORK_DIMENSION = -53 # macro -CL_INVALID_WORK_GROUP_SIZE = -54 # macro -CL_INVALID_WORK_ITEM_SIZE = -55 # macro -CL_INVALID_GLOBAL_OFFSET = -56 # macro -CL_INVALID_EVENT_WAIT_LIST = -57 # macro -CL_INVALID_EVENT = -58 # macro -CL_INVALID_OPERATION = -59 # macro -CL_INVALID_GL_OBJECT = -60 # macro -CL_INVALID_BUFFER_SIZE = -61 # macro -CL_INVALID_MIP_LEVEL = -62 # macro -CL_INVALID_GLOBAL_WORK_SIZE = -63 # macro -CL_INVALID_PROPERTY = -64 # macro -CL_INVALID_IMAGE_DESCRIPTOR = -65 # macro -CL_INVALID_COMPILER_OPTIONS = -66 # macro -CL_INVALID_LINKER_OPTIONS = -67 # macro -CL_INVALID_DEVICE_PARTITION_COUNT = -68 # macro -CL_INVALID_PIPE_SIZE = -69 # macro -CL_INVALID_DEVICE_QUEUE = -70 # macro -CL_INVALID_SPEC_ID = -71 # macro -CL_MAX_SIZE_RESTRICTION_EXCEEDED = -72 # macro -CL_FALSE = 0 # macro -CL_TRUE = 1 # macro -CL_BLOCKING = 1 # macro -CL_NON_BLOCKING = 0 # macro -CL_PLATFORM_PROFILE = 0x0900 # macro -CL_PLATFORM_VERSION = 0x0901 # macro -CL_PLATFORM_NAME = 0x0902 # macro -CL_PLATFORM_VENDOR = 0x0903 # macro -CL_PLATFORM_EXTENSIONS = 0x0904 # macro -CL_PLATFORM_HOST_TIMER_RESOLUTION = 0x0905 # macro -CL_PLATFORM_NUMERIC_VERSION = 0x0906 # macro -CL_PLATFORM_EXTENSIONS_WITH_VERSION = 0x0907 # macro -CL_DEVICE_TYPE_DEFAULT = (1<<0) # macro -CL_DEVICE_TYPE_CPU = (1<<1) # macro -CL_DEVICE_TYPE_GPU = (1<<2) # macro -CL_DEVICE_TYPE_ACCELERATOR = (1<<3) # macro -CL_DEVICE_TYPE_CUSTOM = (1<<4) # macro -CL_DEVICE_TYPE_ALL = 0xFFFFFFFF # macro -CL_DEVICE_TYPE = 0x1000 # macro -CL_DEVICE_VENDOR_ID = 0x1001 # macro -CL_DEVICE_MAX_COMPUTE_UNITS = 0x1002 # macro -CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 0x1003 # macro -CL_DEVICE_MAX_WORK_GROUP_SIZE = 0x1004 # macro -CL_DEVICE_MAX_WORK_ITEM_SIZES = 0x1005 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 0x1006 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 0x1007 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 0x1008 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 0x1009 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 0x100A # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0x100B # macro -CL_DEVICE_MAX_CLOCK_FREQUENCY = 0x100C # macro -CL_DEVICE_ADDRESS_BITS = 0x100D # macro -CL_DEVICE_MAX_READ_IMAGE_ARGS = 0x100E # macro -CL_DEVICE_MAX_WRITE_IMAGE_ARGS = 0x100F # macro -CL_DEVICE_MAX_MEM_ALLOC_SIZE = 0x1010 # macro -CL_DEVICE_IMAGE2D_MAX_WIDTH = 0x1011 # macro -CL_DEVICE_IMAGE2D_MAX_HEIGHT = 0x1012 # macro -CL_DEVICE_IMAGE3D_MAX_WIDTH = 0x1013 # macro -CL_DEVICE_IMAGE3D_MAX_HEIGHT = 0x1014 # macro -CL_DEVICE_IMAGE3D_MAX_DEPTH = 0x1015 # macro -CL_DEVICE_IMAGE_SUPPORT = 0x1016 # macro -CL_DEVICE_MAX_PARAMETER_SIZE = 0x1017 # macro -CL_DEVICE_MAX_SAMPLERS = 0x1018 # macro -CL_DEVICE_MEM_BASE_ADDR_ALIGN = 0x1019 # macro -CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 0x101A # macro -CL_DEVICE_SINGLE_FP_CONFIG = 0x101B # macro -CL_DEVICE_GLOBAL_MEM_CACHE_TYPE = 0x101C # macro -CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0x101D # macro -CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 0x101E # macro -CL_DEVICE_GLOBAL_MEM_SIZE = 0x101F # macro -CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 0x1020 # macro -CL_DEVICE_MAX_CONSTANT_ARGS = 0x1021 # macro -CL_DEVICE_LOCAL_MEM_TYPE = 0x1022 # macro -CL_DEVICE_LOCAL_MEM_SIZE = 0x1023 # macro -CL_DEVICE_ERROR_CORRECTION_SUPPORT = 0x1024 # macro -CL_DEVICE_PROFILING_TIMER_RESOLUTION = 0x1025 # macro -CL_DEVICE_ENDIAN_LITTLE = 0x1026 # macro -CL_DEVICE_AVAILABLE = 0x1027 # macro -CL_DEVICE_COMPILER_AVAILABLE = 0x1028 # macro -CL_DEVICE_EXECUTION_CAPABILITIES = 0x1029 # macro -CL_DEVICE_QUEUE_PROPERTIES = 0x102A # macro -CL_DEVICE_QUEUE_ON_HOST_PROPERTIES = 0x102A # macro -CL_DEVICE_NAME = 0x102B # macro -CL_DEVICE_VENDOR = 0x102C # macro -CL_DRIVER_VERSION = 0x102D # macro -CL_DEVICE_PROFILE = 0x102E # macro -CL_DEVICE_VERSION = 0x102F # macro -CL_DEVICE_EXTENSIONS = 0x1030 # macro -CL_DEVICE_PLATFORM = 0x1031 # macro -CL_DEVICE_DOUBLE_FP_CONFIG = 0x1032 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF = 0x1034 # macro -CL_DEVICE_HOST_UNIFIED_MEMORY = 0x1035 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR = 0x1036 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT = 0x1037 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_INT = 0x1038 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG = 0x1039 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT = 0x103A # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE = 0x103B # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF = 0x103C # macro -CL_DEVICE_OPENCL_C_VERSION = 0x103D # macro -CL_DEVICE_LINKER_AVAILABLE = 0x103E # macro -CL_DEVICE_BUILT_IN_KERNELS = 0x103F # macro -CL_DEVICE_IMAGE_MAX_BUFFER_SIZE = 0x1040 # macro -CL_DEVICE_IMAGE_MAX_ARRAY_SIZE = 0x1041 # macro -CL_DEVICE_PARENT_DEVICE = 0x1042 # macro -CL_DEVICE_PARTITION_MAX_SUB_DEVICES = 0x1043 # macro -CL_DEVICE_PARTITION_PROPERTIES = 0x1044 # macro -CL_DEVICE_PARTITION_AFFINITY_DOMAIN = 0x1045 # macro -CL_DEVICE_PARTITION_TYPE = 0x1046 # macro -CL_DEVICE_REFERENCE_COUNT = 0x1047 # macro -CL_DEVICE_PREFERRED_INTEROP_USER_SYNC = 0x1048 # macro -CL_DEVICE_PRINTF_BUFFER_SIZE = 0x1049 # macro -CL_DEVICE_IMAGE_PITCH_ALIGNMENT = 0x104A # macro -CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT = 0x104B # macro -CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS = 0x104C # macro -CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE = 0x104D # macro -CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES = 0x104E # macro -CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE = 0x104F # macro -CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE = 0x1050 # macro -CL_DEVICE_MAX_ON_DEVICE_QUEUES = 0x1051 # macro -CL_DEVICE_MAX_ON_DEVICE_EVENTS = 0x1052 # macro -CL_DEVICE_SVM_CAPABILITIES = 0x1053 # macro -CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE = 0x1054 # macro -CL_DEVICE_MAX_PIPE_ARGS = 0x1055 # macro -CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS = 0x1056 # macro -CL_DEVICE_PIPE_MAX_PACKET_SIZE = 0x1057 # macro -CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT = 0x1058 # macro -CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT = 0x1059 # macro -CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT = 0x105A # macro -CL_DEVICE_IL_VERSION = 0x105B # macro -CL_DEVICE_MAX_NUM_SUB_GROUPS = 0x105C # macro -CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS = 0x105D # macro -CL_DEVICE_NUMERIC_VERSION = 0x105E # macro -CL_DEVICE_EXTENSIONS_WITH_VERSION = 0x1060 # macro -CL_DEVICE_ILS_WITH_VERSION = 0x1061 # macro -CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION = 0x1062 # macro -CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES = 0x1063 # macro -CL_DEVICE_ATOMIC_FENCE_CAPABILITIES = 0x1064 # macro -CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT = 0x1065 # macro -CL_DEVICE_OPENCL_C_ALL_VERSIONS = 0x1066 # macro -CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x1067 # macro -CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT = 0x1068 # macro -CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT = 0x1069 # macro -CL_DEVICE_OPENCL_C_FEATURES = 0x106F # macro -CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES = 0x1070 # macro -CL_DEVICE_PIPE_SUPPORT = 0x1071 # macro -CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED = 0x1072 # macro -CL_FP_DENORM = (1<<0) # macro -CL_FP_INF_NAN = (1<<1) # macro -CL_FP_ROUND_TO_NEAREST = (1<<2) # macro -CL_FP_ROUND_TO_ZERO = (1<<3) # macro -CL_FP_ROUND_TO_INF = (1<<4) # macro -CL_FP_FMA = (1<<5) # macro -CL_FP_SOFT_FLOAT = (1<<6) # macro -CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT = (1<<7) # macro -CL_NONE = 0x0 # macro -CL_READ_ONLY_CACHE = 0x1 # macro -CL_READ_WRITE_CACHE = 0x2 # macro -CL_LOCAL = 0x1 # macro -CL_GLOBAL = 0x2 # macro -CL_EXEC_KERNEL = (1<<0) # macro -CL_EXEC_NATIVE_KERNEL = (1<<1) # macro -CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE = (1<<0) # macro -CL_QUEUE_PROFILING_ENABLE = (1<<1) # macro -CL_QUEUE_ON_DEVICE = (1<<2) # macro -CL_QUEUE_ON_DEVICE_DEFAULT = (1<<3) # macro -CL_CONTEXT_REFERENCE_COUNT = 0x1080 # macro -CL_CONTEXT_DEVICES = 0x1081 # macro -CL_CONTEXT_PROPERTIES = 0x1082 # macro -CL_CONTEXT_NUM_DEVICES = 0x1083 # macro -CL_CONTEXT_PLATFORM = 0x1084 # macro -CL_CONTEXT_INTEROP_USER_SYNC = 0x1085 # macro -CL_DEVICE_PARTITION_EQUALLY = 0x1086 # macro -CL_DEVICE_PARTITION_BY_COUNTS = 0x1087 # macro -CL_DEVICE_PARTITION_BY_COUNTS_LIST_END = 0x0 # macro -CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN = 0x1088 # macro -CL_DEVICE_AFFINITY_DOMAIN_NUMA = (1<<0) # macro -CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE = (1<<1) # macro -CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE = (1<<2) # macro -CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE = (1<<3) # macro -CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE = (1<<4) # macro -CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE = (1<<5) # macro -CL_DEVICE_SVM_COARSE_GRAIN_BUFFER = (1<<0) # macro -CL_DEVICE_SVM_FINE_GRAIN_BUFFER = (1<<1) # macro -CL_DEVICE_SVM_FINE_GRAIN_SYSTEM = (1<<2) # macro -CL_DEVICE_SVM_ATOMICS = (1<<3) # macro -CL_QUEUE_CONTEXT = 0x1090 # macro -CL_QUEUE_DEVICE = 0x1091 # macro -CL_QUEUE_REFERENCE_COUNT = 0x1092 # macro -CL_QUEUE_PROPERTIES = 0x1093 # macro -CL_QUEUE_SIZE = 0x1094 # macro -CL_QUEUE_DEVICE_DEFAULT = 0x1095 # macro -CL_QUEUE_PROPERTIES_ARRAY = 0x1098 # macro -CL_MEM_READ_WRITE = (1<<0) # macro -CL_MEM_WRITE_ONLY = (1<<1) # macro -CL_MEM_READ_ONLY = (1<<2) # macro -CL_MEM_USE_HOST_PTR = (1<<3) # macro -CL_MEM_ALLOC_HOST_PTR = (1<<4) # macro -CL_MEM_COPY_HOST_PTR = (1<<5) # macro -CL_MEM_HOST_WRITE_ONLY = (1<<7) # macro -CL_MEM_HOST_READ_ONLY = (1<<8) # macro -CL_MEM_HOST_NO_ACCESS = (1<<9) # macro -CL_MEM_SVM_FINE_GRAIN_BUFFER = (1<<10) # macro -CL_MEM_SVM_ATOMICS = (1<<11) # macro -CL_MEM_KERNEL_READ_AND_WRITE = (1<<12) # macro -CL_MIGRATE_MEM_OBJECT_HOST = (1<<0) # macro -CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED = (1<<1) # macro -CL_R = 0x10B0 # macro -CL_A = 0x10B1 # macro -CL_RG = 0x10B2 # macro -CL_RA = 0x10B3 # macro -CL_RGB = 0x10B4 # macro -CL_RGBA = 0x10B5 # macro -CL_BGRA = 0x10B6 # macro -CL_ARGB = 0x10B7 # macro -CL_INTENSITY = 0x10B8 # macro -CL_LUMINANCE = 0x10B9 # macro -CL_Rx = 0x10BA # macro -CL_RGx = 0x10BB # macro -CL_RGBx = 0x10BC # macro -CL_DEPTH = 0x10BD # macro -CL_sRGB = 0x10BF # macro -CL_sRGBx = 0x10C0 # macro -CL_sRGBA = 0x10C1 # macro -CL_sBGRA = 0x10C2 # macro -CL_ABGR = 0x10C3 # macro -CL_SNORM_INT8 = 0x10D0 # macro -CL_SNORM_INT16 = 0x10D1 # macro -CL_UNORM_INT8 = 0x10D2 # macro -CL_UNORM_INT16 = 0x10D3 # macro -CL_UNORM_SHORT_565 = 0x10D4 # macro -CL_UNORM_SHORT_555 = 0x10D5 # macro -CL_UNORM_INT_101010 = 0x10D6 # macro -CL_SIGNED_INT8 = 0x10D7 # macro -CL_SIGNED_INT16 = 0x10D8 # macro -CL_SIGNED_INT32 = 0x10D9 # macro -CL_UNSIGNED_INT8 = 0x10DA # macro -CL_UNSIGNED_INT16 = 0x10DB # macro -CL_UNSIGNED_INT32 = 0x10DC # macro -CL_HALF_FLOAT = 0x10DD # macro -CL_FLOAT = 0x10DE # macro -CL_UNORM_INT_101010_2 = 0x10E0 # macro -CL_MEM_OBJECT_BUFFER = 0x10F0 # macro -CL_MEM_OBJECT_IMAGE2D = 0x10F1 # macro -CL_MEM_OBJECT_IMAGE3D = 0x10F2 # macro -CL_MEM_OBJECT_IMAGE2D_ARRAY = 0x10F3 # macro -CL_MEM_OBJECT_IMAGE1D = 0x10F4 # macro -CL_MEM_OBJECT_IMAGE1D_ARRAY = 0x10F5 # macro -CL_MEM_OBJECT_IMAGE1D_BUFFER = 0x10F6 # macro -CL_MEM_OBJECT_PIPE = 0x10F7 # macro -CL_MEM_TYPE = 0x1100 # macro -CL_MEM_FLAGS = 0x1101 # macro -CL_MEM_SIZE = 0x1102 # macro -CL_MEM_HOST_PTR = 0x1103 # macro -CL_MEM_MAP_COUNT = 0x1104 # macro -CL_MEM_REFERENCE_COUNT = 0x1105 # macro -CL_MEM_CONTEXT = 0x1106 # macro -CL_MEM_ASSOCIATED_MEMOBJECT = 0x1107 # macro -CL_MEM_OFFSET = 0x1108 # macro -CL_MEM_USES_SVM_POINTER = 0x1109 # macro -CL_MEM_PROPERTIES = 0x110A # macro -CL_IMAGE_FORMAT = 0x1110 # macro -CL_IMAGE_ELEMENT_SIZE = 0x1111 # macro -CL_IMAGE_ROW_PITCH = 0x1112 # macro -CL_IMAGE_SLICE_PITCH = 0x1113 # macro -CL_IMAGE_WIDTH = 0x1114 # macro -CL_IMAGE_HEIGHT = 0x1115 # macro -CL_IMAGE_DEPTH = 0x1116 # macro -CL_IMAGE_ARRAY_SIZE = 0x1117 # macro -CL_IMAGE_BUFFER = 0x1118 # macro -CL_IMAGE_NUM_MIP_LEVELS = 0x1119 # macro -CL_IMAGE_NUM_SAMPLES = 0x111A # macro -CL_PIPE_PACKET_SIZE = 0x1120 # macro -CL_PIPE_MAX_PACKETS = 0x1121 # macro -CL_PIPE_PROPERTIES = 0x1122 # macro -CL_ADDRESS_NONE = 0x1130 # macro -CL_ADDRESS_CLAMP_TO_EDGE = 0x1131 # macro -CL_ADDRESS_CLAMP = 0x1132 # macro -CL_ADDRESS_REPEAT = 0x1133 # macro -CL_ADDRESS_MIRRORED_REPEAT = 0x1134 # macro -CL_FILTER_NEAREST = 0x1140 # macro -CL_FILTER_LINEAR = 0x1141 # macro -CL_SAMPLER_REFERENCE_COUNT = 0x1150 # macro -CL_SAMPLER_CONTEXT = 0x1151 # macro -CL_SAMPLER_NORMALIZED_COORDS = 0x1152 # macro -CL_SAMPLER_ADDRESSING_MODE = 0x1153 # macro -CL_SAMPLER_FILTER_MODE = 0x1154 # macro -CL_SAMPLER_MIP_FILTER_MODE = 0x1155 # macro -CL_SAMPLER_LOD_MIN = 0x1156 # macro -CL_SAMPLER_LOD_MAX = 0x1157 # macro -CL_SAMPLER_PROPERTIES = 0x1158 # macro -CL_MAP_READ = (1<<0) # macro -CL_MAP_WRITE = (1<<1) # macro -CL_MAP_WRITE_INVALIDATE_REGION = (1<<2) # macro -CL_PROGRAM_REFERENCE_COUNT = 0x1160 # macro -CL_PROGRAM_CONTEXT = 0x1161 # macro -CL_PROGRAM_NUM_DEVICES = 0x1162 # macro -CL_PROGRAM_DEVICES = 0x1163 # macro -CL_PROGRAM_SOURCE = 0x1164 # macro -CL_PROGRAM_BINARY_SIZES = 0x1165 # macro -CL_PROGRAM_BINARIES = 0x1166 # macro -CL_PROGRAM_NUM_KERNELS = 0x1167 # macro -CL_PROGRAM_KERNEL_NAMES = 0x1168 # macro -CL_PROGRAM_IL = 0x1169 # macro -CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT = 0x116A # macro -CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT = 0x116B # macro -CL_PROGRAM_BUILD_STATUS = 0x1181 # macro -CL_PROGRAM_BUILD_OPTIONS = 0x1182 # macro -CL_PROGRAM_BUILD_LOG = 0x1183 # macro -CL_PROGRAM_BINARY_TYPE = 0x1184 # macro -CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE = 0x1185 # macro -CL_PROGRAM_BINARY_TYPE_NONE = 0x0 # macro -CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT = 0x1 # macro -CL_PROGRAM_BINARY_TYPE_LIBRARY = 0x2 # macro -CL_PROGRAM_BINARY_TYPE_EXECUTABLE = 0x4 # macro -CL_BUILD_SUCCESS = 0 # macro -CL_BUILD_NONE = -1 # macro -CL_BUILD_ERROR = -2 # macro -CL_BUILD_IN_PROGRESS = -3 # macro -CL_KERNEL_FUNCTION_NAME = 0x1190 # macro -CL_KERNEL_NUM_ARGS = 0x1191 # macro -CL_KERNEL_REFERENCE_COUNT = 0x1192 # macro -CL_KERNEL_CONTEXT = 0x1193 # macro -CL_KERNEL_PROGRAM = 0x1194 # macro -CL_KERNEL_ATTRIBUTES = 0x1195 # macro -CL_KERNEL_ARG_ADDRESS_QUALIFIER = 0x1196 # macro -CL_KERNEL_ARG_ACCESS_QUALIFIER = 0x1197 # macro -CL_KERNEL_ARG_TYPE_NAME = 0x1198 # macro -CL_KERNEL_ARG_TYPE_QUALIFIER = 0x1199 # macro -CL_KERNEL_ARG_NAME = 0x119A # macro -CL_KERNEL_ARG_ADDRESS_GLOBAL = 0x119B # macro -CL_KERNEL_ARG_ADDRESS_LOCAL = 0x119C # macro -CL_KERNEL_ARG_ADDRESS_CONSTANT = 0x119D # macro -CL_KERNEL_ARG_ADDRESS_PRIVATE = 0x119E # macro -CL_KERNEL_ARG_ACCESS_READ_ONLY = 0x11A0 # macro -CL_KERNEL_ARG_ACCESS_WRITE_ONLY = 0x11A1 # macro -CL_KERNEL_ARG_ACCESS_READ_WRITE = 0x11A2 # macro -CL_KERNEL_ARG_ACCESS_NONE = 0x11A3 # macro -CL_KERNEL_ARG_TYPE_NONE = 0 # macro -CL_KERNEL_ARG_TYPE_CONST = (1<<0) # macro -CL_KERNEL_ARG_TYPE_RESTRICT = (1<<1) # macro -CL_KERNEL_ARG_TYPE_VOLATILE = (1<<2) # macro -CL_KERNEL_ARG_TYPE_PIPE = (1<<3) # macro -CL_KERNEL_WORK_GROUP_SIZE = 0x11B0 # macro -CL_KERNEL_COMPILE_WORK_GROUP_SIZE = 0x11B1 # macro -CL_KERNEL_LOCAL_MEM_SIZE = 0x11B2 # macro -CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x11B3 # macro -CL_KERNEL_PRIVATE_MEM_SIZE = 0x11B4 # macro -CL_KERNEL_GLOBAL_WORK_SIZE = 0x11B5 # macro -CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE = 0x2033 # macro -CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE = 0x2034 # macro -CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT = 0x11B8 # macro -CL_KERNEL_MAX_NUM_SUB_GROUPS = 0x11B9 # macro -CL_KERNEL_COMPILE_NUM_SUB_GROUPS = 0x11BA # macro -CL_KERNEL_EXEC_INFO_SVM_PTRS = 0x11B6 # macro -CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM = 0x11B7 # macro -CL_EVENT_COMMAND_QUEUE = 0x11D0 # macro -CL_EVENT_COMMAND_TYPE = 0x11D1 # macro -CL_EVENT_REFERENCE_COUNT = 0x11D2 # macro -CL_EVENT_COMMAND_EXECUTION_STATUS = 0x11D3 # macro -CL_EVENT_CONTEXT = 0x11D4 # macro -CL_COMMAND_NDRANGE_KERNEL = 0x11F0 # macro -CL_COMMAND_TASK = 0x11F1 # macro -CL_COMMAND_NATIVE_KERNEL = 0x11F2 # macro -CL_COMMAND_READ_BUFFER = 0x11F3 # macro -CL_COMMAND_WRITE_BUFFER = 0x11F4 # macro -CL_COMMAND_COPY_BUFFER = 0x11F5 # macro -CL_COMMAND_READ_IMAGE = 0x11F6 # macro -CL_COMMAND_WRITE_IMAGE = 0x11F7 # macro -CL_COMMAND_COPY_IMAGE = 0x11F8 # macro -CL_COMMAND_COPY_IMAGE_TO_BUFFER = 0x11F9 # macro -CL_COMMAND_COPY_BUFFER_TO_IMAGE = 0x11FA # macro -CL_COMMAND_MAP_BUFFER = 0x11FB # macro -CL_COMMAND_MAP_IMAGE = 0x11FC # macro -CL_COMMAND_UNMAP_MEM_OBJECT = 0x11FD # macro -CL_COMMAND_MARKER = 0x11FE # macro -CL_COMMAND_ACQUIRE_GL_OBJECTS = 0x11FF # macro -CL_COMMAND_RELEASE_GL_OBJECTS = 0x1200 # macro -CL_COMMAND_READ_BUFFER_RECT = 0x1201 # macro -CL_COMMAND_WRITE_BUFFER_RECT = 0x1202 # macro -CL_COMMAND_COPY_BUFFER_RECT = 0x1203 # macro -CL_COMMAND_USER = 0x1204 # macro -CL_COMMAND_BARRIER = 0x1205 # macro -CL_COMMAND_MIGRATE_MEM_OBJECTS = 0x1206 # macro -CL_COMMAND_FILL_BUFFER = 0x1207 # macro -CL_COMMAND_FILL_IMAGE = 0x1208 # macro -CL_COMMAND_SVM_FREE = 0x1209 # macro -CL_COMMAND_SVM_MEMCPY = 0x120A # macro -CL_COMMAND_SVM_MEMFILL = 0x120B # macro -CL_COMMAND_SVM_MAP = 0x120C # macro -CL_COMMAND_SVM_UNMAP = 0x120D # macro -CL_COMMAND_SVM_MIGRATE_MEM = 0x120E # macro -CL_COMPLETE = 0x0 # macro -CL_RUNNING = 0x1 # macro -CL_SUBMITTED = 0x2 # macro -CL_QUEUED = 0x3 # macro -CL_BUFFER_CREATE_TYPE_REGION = 0x1220 # macro -CL_PROFILING_COMMAND_QUEUED = 0x1280 # macro -CL_PROFILING_COMMAND_SUBMIT = 0x1281 # macro -CL_PROFILING_COMMAND_START = 0x1282 # macro -CL_PROFILING_COMMAND_END = 0x1283 # macro -CL_PROFILING_COMMAND_COMPLETE = 0x1284 # macro -CL_DEVICE_ATOMIC_ORDER_RELAXED = (1<<0) # macro -CL_DEVICE_ATOMIC_ORDER_ACQ_REL = (1<<1) # macro -CL_DEVICE_ATOMIC_ORDER_SEQ_CST = (1<<2) # macro -CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM = (1<<3) # macro -CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP = (1<<4) # macro -CL_DEVICE_ATOMIC_SCOPE_DEVICE = (1<<5) # macro -CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES = (1<<6) # macro -CL_DEVICE_QUEUE_SUPPORTED = (1<<0) # macro -CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT = (1<<1) # macro -CL_KHRONOS_VENDOR_ID_CODEPLAY = 0x10004 # macro -CL_VERSION_MAJOR_BITS = (10) # macro -CL_VERSION_MINOR_BITS = (10) # macro -CL_VERSION_PATCH_BITS = (12) # macro -CL_VERSION_MAJOR_MASK = ((1<<(10))-1) # macro -CL_VERSION_MINOR_MASK = ((1<<(10))-1) # macro -CL_VERSION_PATCH_MASK = ((1<<(12))-1) # macro -def CL_VERSION_MAJOR(version): # macro - return ((version)>>((10)+(12))) -def CL_VERSION_MINOR(version): # macro - return (((version)>>(12))&((1<<(10))-1)) -def CL_VERSION_PATCH(version): # macro - return ((version)&((1<<(12))-1)) -def CL_MAKE_VERSION(major, minor, patch): # macro - return ((((major)&((1<<(10))-1))<<((10)+(12)))|(((minor)&((1<<(10))-1))<<(12))|((patch)&((1<<(12))-1))) -class struct__cl_platform_id(Structure): - pass - -cl_platform_id = ctypes.POINTER(struct__cl_platform_id) -class struct__cl_device_id(Structure): - pass - -cl_device_id = ctypes.POINTER(struct__cl_device_id) -class struct__cl_context(Structure): - pass - -cl_context = ctypes.POINTER(struct__cl_context) -class struct__cl_command_queue(Structure): - pass - -cl_command_queue = ctypes.POINTER(struct__cl_command_queue) -class struct__cl_mem(Structure): - pass - -cl_mem = ctypes.POINTER(struct__cl_mem) -class struct__cl_program(Structure): - pass - -cl_program = ctypes.POINTER(struct__cl_program) -class struct__cl_kernel(Structure): - pass - -cl_kernel = ctypes.POINTER(struct__cl_kernel) -class struct__cl_event(Structure): - pass - -cl_event = ctypes.POINTER(struct__cl_event) -class struct__cl_sampler(Structure): - pass - -cl_sampler = ctypes.POINTER(struct__cl_sampler) -cl_bool = ctypes.c_uint32 -cl_bitfield = ctypes.c_uint64 -cl_properties = ctypes.c_uint64 -cl_device_type = ctypes.c_uint64 -cl_platform_info = ctypes.c_uint32 -cl_device_info = ctypes.c_uint32 -cl_device_fp_config = ctypes.c_uint64 -cl_device_mem_cache_type = ctypes.c_uint32 -cl_device_local_mem_type = ctypes.c_uint32 -cl_device_exec_capabilities = ctypes.c_uint64 -cl_device_svm_capabilities = ctypes.c_uint64 -cl_command_queue_properties = ctypes.c_uint64 -cl_device_partition_property = ctypes.c_int64 -cl_device_affinity_domain = ctypes.c_uint64 -cl_context_properties = ctypes.c_int64 -cl_context_info = ctypes.c_uint32 -cl_queue_properties = ctypes.c_uint64 -cl_command_queue_info = ctypes.c_uint32 -cl_channel_order = ctypes.c_uint32 -cl_channel_type = ctypes.c_uint32 -cl_mem_flags = ctypes.c_uint64 -cl_svm_mem_flags = ctypes.c_uint64 -cl_mem_object_type = ctypes.c_uint32 -cl_mem_info = ctypes.c_uint32 -cl_mem_migration_flags = ctypes.c_uint64 -cl_image_info = ctypes.c_uint32 -cl_buffer_create_type = ctypes.c_uint32 -cl_addressing_mode = ctypes.c_uint32 -cl_filter_mode = ctypes.c_uint32 -cl_sampler_info = ctypes.c_uint32 -cl_map_flags = ctypes.c_uint64 -cl_pipe_properties = ctypes.c_int64 -cl_pipe_info = ctypes.c_uint32 -cl_program_info = ctypes.c_uint32 -cl_program_build_info = ctypes.c_uint32 -cl_program_binary_type = ctypes.c_uint32 -cl_build_status = ctypes.c_int32 -cl_kernel_info = ctypes.c_uint32 -cl_kernel_arg_info = ctypes.c_uint32 -cl_kernel_arg_address_qualifier = ctypes.c_uint32 -cl_kernel_arg_access_qualifier = ctypes.c_uint32 -cl_kernel_arg_type_qualifier = ctypes.c_uint64 -cl_kernel_work_group_info = ctypes.c_uint32 -cl_kernel_sub_group_info = ctypes.c_uint32 -cl_event_info = ctypes.c_uint32 -cl_command_type = ctypes.c_uint32 -cl_profiling_info = ctypes.c_uint32 -cl_sampler_properties = ctypes.c_uint64 -cl_kernel_exec_info = ctypes.c_uint32 -cl_device_atomic_capabilities = ctypes.c_uint64 -cl_device_device_enqueue_capabilities = ctypes.c_uint64 -cl_khronos_vendor_id = ctypes.c_uint32 -cl_mem_properties = ctypes.c_uint64 -cl_version = ctypes.c_uint32 -class struct__cl_image_format(Structure): - pass - -struct__cl_image_format._pack_ = 1 # source:False -struct__cl_image_format._fields_ = [ - ('image_channel_order', ctypes.c_uint32), - ('image_channel_data_type', ctypes.c_uint32), -] - -cl_image_format = struct__cl_image_format -class struct__cl_image_desc(Structure): - pass - -class union__cl_image_desc_0(Union): - pass - -union__cl_image_desc_0._pack_ = 1 # source:False -union__cl_image_desc_0._fields_ = [ - ('buffer', ctypes.POINTER(struct__cl_mem)), - ('mem_object', ctypes.POINTER(struct__cl_mem)), -] - -struct__cl_image_desc._pack_ = 1 # source:False -struct__cl_image_desc._anonymous_ = ('_0',) -struct__cl_image_desc._fields_ = [ - ('image_type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('image_width', ctypes.c_uint64), - ('image_height', ctypes.c_uint64), - ('image_depth', ctypes.c_uint64), - ('image_array_size', ctypes.c_uint64), - ('image_row_pitch', ctypes.c_uint64), - ('image_slice_pitch', ctypes.c_uint64), - ('num_mip_levels', ctypes.c_uint32), - ('num_samples', ctypes.c_uint32), - ('_0', union__cl_image_desc_0), -] - -cl_image_desc = struct__cl_image_desc -class struct__cl_buffer_region(Structure): - pass - -struct__cl_buffer_region._pack_ = 1 # source:False -struct__cl_buffer_region._fields_ = [ - ('origin', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -cl_buffer_region = struct__cl_buffer_region -class struct__cl_name_version(Structure): - pass - -struct__cl_name_version._pack_ = 1 # source:False -struct__cl_name_version._fields_ = [ - ('version', ctypes.c_uint32), - ('name', ctypes.c_char * 64), -] - -cl_name_version = struct__cl_name_version -cl_int = ctypes.c_int32 -cl_uint = ctypes.c_uint32 -try: - clGetPlatformIDs = _libraries['libOpenCL.so.1'].clGetPlatformIDs - clGetPlatformIDs.restype = cl_int - clGetPlatformIDs.argtypes = [cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_platform_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - clGetPlatformInfo = _libraries['libOpenCL.so.1'].clGetPlatformInfo - clGetPlatformInfo.restype = cl_int - clGetPlatformInfo.argtypes = [cl_platform_id, cl_platform_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetDeviceIDs = _libraries['libOpenCL.so.1'].clGetDeviceIDs - clGetDeviceIDs.restype = cl_int - clGetDeviceIDs.argtypes = [cl_platform_id, cl_device_type, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clGetDeviceInfo = _libraries['libOpenCL.so.1'].clGetDeviceInfo - clGetDeviceInfo.restype = cl_int - clGetDeviceInfo.argtypes = [cl_device_id, cl_device_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateSubDevices = _libraries['libOpenCL.so.1'].clCreateSubDevices - clCreateSubDevices.restype = cl_int - clCreateSubDevices.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_int64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clRetainDevice = _libraries['libOpenCL.so.1'].clRetainDevice - clRetainDevice.restype = cl_int - clRetainDevice.argtypes = [cl_device_id] -except AttributeError: - pass -try: - clReleaseDevice = _libraries['libOpenCL.so.1'].clReleaseDevice - clReleaseDevice.restype = cl_int - clReleaseDevice.argtypes = [cl_device_id] -except AttributeError: - pass -try: - clSetDefaultDeviceCommandQueue = _libraries['libOpenCL.so.1'].clSetDefaultDeviceCommandQueue - clSetDefaultDeviceCommandQueue.restype = cl_int - clSetDefaultDeviceCommandQueue.argtypes = [cl_context, cl_device_id, cl_command_queue] -except AttributeError: - pass -try: - clGetDeviceAndHostTimer = _libraries['libOpenCL.so.1'].clGetDeviceAndHostTimer - clGetDeviceAndHostTimer.restype = cl_int - clGetDeviceAndHostTimer.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetHostTimer = _libraries['libOpenCL.so.1'].clGetHostTimer - clGetHostTimer.restype = cl_int - clGetHostTimer.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateContext = _libraries['libOpenCL.so.1'].clCreateContext - clCreateContext.restype = cl_context - clCreateContext.argtypes = [ctypes.POINTER(ctypes.c_int64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateContextFromType = _libraries['libOpenCL.so.1'].clCreateContextFromType - clCreateContextFromType.restype = cl_context - clCreateContextFromType.argtypes = [ctypes.POINTER(ctypes.c_int64), cl_device_type, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainContext = _libraries['libOpenCL.so.1'].clRetainContext - clRetainContext.restype = cl_int - clRetainContext.argtypes = [cl_context] -except AttributeError: - pass -try: - clReleaseContext = _libraries['libOpenCL.so.1'].clReleaseContext - clReleaseContext.restype = cl_int - clReleaseContext.argtypes = [cl_context] -except AttributeError: - pass -try: - clGetContextInfo = _libraries['libOpenCL.so.1'].clGetContextInfo - clGetContextInfo.restype = cl_int - clGetContextInfo.argtypes = [cl_context, cl_context_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clSetContextDestructorCallback = _libraries['libOpenCL.so.1'].clSetContextDestructorCallback - clSetContextDestructorCallback.restype = cl_int - clSetContextDestructorCallback.argtypes = [cl_context, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_context), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCreateCommandQueueWithProperties = _libraries['libOpenCL.so.1'].clCreateCommandQueueWithProperties - clCreateCommandQueueWithProperties.restype = cl_command_queue - clCreateCommandQueueWithProperties.argtypes = [cl_context, cl_device_id, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainCommandQueue = _libraries['libOpenCL.so.1'].clRetainCommandQueue - clRetainCommandQueue.restype = cl_int - clRetainCommandQueue.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clReleaseCommandQueue = _libraries['libOpenCL.so.1'].clReleaseCommandQueue - clReleaseCommandQueue.restype = cl_int - clReleaseCommandQueue.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clGetCommandQueueInfo = _libraries['libOpenCL.so.1'].clGetCommandQueueInfo - clGetCommandQueueInfo.restype = cl_int - clGetCommandQueueInfo.argtypes = [cl_command_queue, cl_command_queue_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateBuffer = _libraries['libOpenCL.so.1'].clCreateBuffer - clCreateBuffer.restype = cl_mem - clCreateBuffer.argtypes = [cl_context, cl_mem_flags, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateSubBuffer = _libraries['libOpenCL.so.1'].clCreateSubBuffer - clCreateSubBuffer.restype = cl_mem - clCreateSubBuffer.argtypes = [cl_mem, cl_mem_flags, cl_buffer_create_type, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImage = _libraries['libOpenCL.so.1'].clCreateImage - clCreateImage.restype = cl_mem - clCreateImage.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(struct__cl_image_desc), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreatePipe = _libraries['libOpenCL.so.1'].clCreatePipe - clCreatePipe.restype = cl_mem - clCreatePipe.argtypes = [cl_context, cl_mem_flags, cl_uint, cl_uint, ctypes.POINTER(ctypes.c_int64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateBufferWithProperties = _libraries['libOpenCL.so.1'].clCreateBufferWithProperties - clCreateBufferWithProperties.restype = cl_mem - clCreateBufferWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), cl_mem_flags, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImageWithProperties = _libraries['libOpenCL.so.1'].clCreateImageWithProperties - clCreateImageWithProperties.restype = cl_mem - clCreateImageWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), cl_mem_flags, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(struct__cl_image_desc), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainMemObject = _libraries['libOpenCL.so.1'].clRetainMemObject - clRetainMemObject.restype = cl_int - clRetainMemObject.argtypes = [cl_mem] -except AttributeError: - pass -try: - clReleaseMemObject = _libraries['libOpenCL.so.1'].clReleaseMemObject - clReleaseMemObject.restype = cl_int - clReleaseMemObject.argtypes = [cl_mem] -except AttributeError: - pass -try: - clGetSupportedImageFormats = _libraries['libOpenCL.so.1'].clGetSupportedImageFormats - clGetSupportedImageFormats.restype = cl_int - clGetSupportedImageFormats.argtypes = [cl_context, cl_mem_flags, cl_mem_object_type, cl_uint, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clGetMemObjectInfo = _libraries['libOpenCL.so.1'].clGetMemObjectInfo - clGetMemObjectInfo.restype = cl_int - clGetMemObjectInfo.argtypes = [cl_mem, cl_mem_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetImageInfo = _libraries['libOpenCL.so.1'].clGetImageInfo - clGetImageInfo.restype = cl_int - clGetImageInfo.argtypes = [cl_mem, cl_image_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetPipeInfo = _libraries['libOpenCL.so.1'].clGetPipeInfo - clGetPipeInfo.restype = cl_int - clGetPipeInfo.argtypes = [cl_mem, cl_pipe_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clSetMemObjectDestructorCallback = _libraries['libOpenCL.so.1'].clSetMemObjectDestructorCallback - clSetMemObjectDestructorCallback.restype = cl_int - clSetMemObjectDestructorCallback.argtypes = [cl_mem, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_mem), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSVMAlloc = _libraries['libOpenCL.so.1'].clSVMAlloc - clSVMAlloc.restype = ctypes.POINTER(None) - clSVMAlloc.argtypes = [cl_context, cl_svm_mem_flags, size_t, cl_uint] -except AttributeError: - pass -try: - clSVMFree = _libraries['libOpenCL.so.1'].clSVMFree - clSVMFree.restype = None - clSVMFree.argtypes = [cl_context, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCreateSamplerWithProperties = _libraries['libOpenCL.so.1'].clCreateSamplerWithProperties - clCreateSamplerWithProperties.restype = cl_sampler - clCreateSamplerWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainSampler = _libraries['libOpenCL.so.1'].clRetainSampler - clRetainSampler.restype = cl_int - clRetainSampler.argtypes = [cl_sampler] -except AttributeError: - pass -try: - clReleaseSampler = _libraries['libOpenCL.so.1'].clReleaseSampler - clReleaseSampler.restype = cl_int - clReleaseSampler.argtypes = [cl_sampler] -except AttributeError: - pass -try: - clGetSamplerInfo = _libraries['libOpenCL.so.1'].clGetSamplerInfo - clGetSamplerInfo.restype = cl_int - clGetSamplerInfo.argtypes = [cl_sampler, cl_sampler_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateProgramWithSource = _libraries['libOpenCL.so.1'].clCreateProgramWithSource - clCreateProgramWithSource.restype = cl_program - clCreateProgramWithSource.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithBinary = _libraries['libOpenCL.so.1'].clCreateProgramWithBinary - clCreateProgramWithBinary.restype = cl_program - clCreateProgramWithBinary.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(ctypes.c_ubyte)), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithBuiltInKernels = _libraries['libOpenCL.so.1'].clCreateProgramWithBuiltInKernels - clCreateProgramWithBuiltInKernels.restype = cl_program - clCreateProgramWithBuiltInKernels.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithIL = _libraries['libOpenCL.so.1'].clCreateProgramWithIL - clCreateProgramWithIL.restype = cl_program - clCreateProgramWithIL.argtypes = [cl_context, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainProgram = _libraries['libOpenCL.so.1'].clRetainProgram - clRetainProgram.restype = cl_int - clRetainProgram.argtypes = [cl_program] -except AttributeError: - pass -try: - clReleaseProgram = _libraries['libOpenCL.so.1'].clReleaseProgram - clReleaseProgram.restype = cl_int - clReleaseProgram.argtypes = [cl_program] -except AttributeError: - pass -try: - clBuildProgram = _libraries['libOpenCL.so.1'].clBuildProgram - clBuildProgram.restype = cl_int - clBuildProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCompileProgram = _libraries['libOpenCL.so.1'].clCompileProgram - clCompileProgram.restype = cl_int - clCompileProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_program)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clLinkProgram = _libraries['libOpenCL.so.1'].clLinkProgram - clLinkProgram.restype = cl_program - clLinkProgram.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_program)), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clSetProgramReleaseCallback = _libraries['libOpenCL.so.1'].clSetProgramReleaseCallback - clSetProgramReleaseCallback.restype = cl_int - clSetProgramReleaseCallback.argtypes = [cl_program, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetProgramSpecializationConstant = _libraries['libOpenCL.so.1'].clSetProgramSpecializationConstant - clSetProgramSpecializationConstant.restype = cl_int - clSetProgramSpecializationConstant.argtypes = [cl_program, cl_uint, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clUnloadPlatformCompiler = _libraries['libOpenCL.so.1'].clUnloadPlatformCompiler - clUnloadPlatformCompiler.restype = cl_int - clUnloadPlatformCompiler.argtypes = [cl_platform_id] -except AttributeError: - pass -try: - clGetProgramInfo = _libraries['libOpenCL.so.1'].clGetProgramInfo - clGetProgramInfo.restype = cl_int - clGetProgramInfo.argtypes = [cl_program, cl_program_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetProgramBuildInfo = _libraries['libOpenCL.so.1'].clGetProgramBuildInfo - clGetProgramBuildInfo.restype = cl_int - clGetProgramBuildInfo.argtypes = [cl_program, cl_device_id, cl_program_build_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateKernel = _libraries['libOpenCL.so.1'].clCreateKernel - clCreateKernel.restype = cl_kernel - clCreateKernel.argtypes = [cl_program, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateKernelsInProgram = _libraries['libOpenCL.so.1'].clCreateKernelsInProgram - clCreateKernelsInProgram.restype = cl_int - clCreateKernelsInProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_kernel)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clCloneKernel = _libraries['libOpenCL.so.1'].clCloneKernel - clCloneKernel.restype = cl_kernel - clCloneKernel.argtypes = [cl_kernel, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainKernel = _libraries['libOpenCL.so.1'].clRetainKernel - clRetainKernel.restype = cl_int - clRetainKernel.argtypes = [cl_kernel] -except AttributeError: - pass -try: - clReleaseKernel = _libraries['libOpenCL.so.1'].clReleaseKernel - clReleaseKernel.restype = cl_int - clReleaseKernel.argtypes = [cl_kernel] -except AttributeError: - pass -try: - clSetKernelArg = _libraries['libOpenCL.so.1'].clSetKernelArg - clSetKernelArg.restype = cl_int - clSetKernelArg.argtypes = [cl_kernel, cl_uint, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetKernelArgSVMPointer = _libraries['libOpenCL.so.1'].clSetKernelArgSVMPointer - clSetKernelArgSVMPointer.restype = cl_int - clSetKernelArgSVMPointer.argtypes = [cl_kernel, cl_uint, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetKernelExecInfo = _libraries['libOpenCL.so.1'].clSetKernelExecInfo - clSetKernelExecInfo.restype = cl_int - clSetKernelExecInfo.argtypes = [cl_kernel, cl_kernel_exec_info, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clGetKernelInfo = _libraries['libOpenCL.so.1'].clGetKernelInfo - clGetKernelInfo.restype = cl_int - clGetKernelInfo.argtypes = [cl_kernel, cl_kernel_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelArgInfo = _libraries['libOpenCL.so.1'].clGetKernelArgInfo - clGetKernelArgInfo.restype = cl_int - clGetKernelArgInfo.argtypes = [cl_kernel, cl_uint, cl_kernel_arg_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelWorkGroupInfo = _libraries['libOpenCL.so.1'].clGetKernelWorkGroupInfo - clGetKernelWorkGroupInfo.restype = cl_int - clGetKernelWorkGroupInfo.argtypes = [cl_kernel, cl_device_id, cl_kernel_work_group_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelSubGroupInfo = _libraries['libOpenCL.so.1'].clGetKernelSubGroupInfo - clGetKernelSubGroupInfo.restype = cl_int - clGetKernelSubGroupInfo.argtypes = [cl_kernel, cl_device_id, cl_kernel_sub_group_info, size_t, ctypes.POINTER(None), size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clWaitForEvents = _libraries['libOpenCL.so.1'].clWaitForEvents - clWaitForEvents.restype = cl_int - clWaitForEvents.argtypes = [cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clGetEventInfo = _libraries['libOpenCL.so.1'].clGetEventInfo - clGetEventInfo.restype = cl_int - clGetEventInfo.argtypes = [cl_event, cl_event_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateUserEvent = _libraries['libOpenCL.so.1'].clCreateUserEvent - clCreateUserEvent.restype = cl_event - clCreateUserEvent.argtypes = [cl_context, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainEvent = _libraries['libOpenCL.so.1'].clRetainEvent - clRetainEvent.restype = cl_int - clRetainEvent.argtypes = [cl_event] -except AttributeError: - pass -try: - clReleaseEvent = _libraries['libOpenCL.so.1'].clReleaseEvent - clReleaseEvent.restype = cl_int - clReleaseEvent.argtypes = [cl_event] -except AttributeError: - pass -try: - clSetUserEventStatus = _libraries['libOpenCL.so.1'].clSetUserEventStatus - clSetUserEventStatus.restype = cl_int - clSetUserEventStatus.argtypes = [cl_event, cl_int] -except AttributeError: - pass -try: - clSetEventCallback = _libraries['libOpenCL.so.1'].clSetEventCallback - clSetEventCallback.restype = cl_int - clSetEventCallback.argtypes = [cl_event, cl_int, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_event), ctypes.c_int32, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clGetEventProfilingInfo = _libraries['libOpenCL.so.1'].clGetEventProfilingInfo - clGetEventProfilingInfo.restype = cl_int - clGetEventProfilingInfo.argtypes = [cl_event, cl_profiling_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clFlush = _libraries['libOpenCL.so.1'].clFlush - clFlush.restype = cl_int - clFlush.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clFinish = _libraries['libOpenCL.so.1'].clFinish - clFinish.restype = cl_int - clFinish.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clEnqueueReadBuffer = _libraries['libOpenCL.so.1'].clEnqueueReadBuffer - clEnqueueReadBuffer.restype = cl_int - clEnqueueReadBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueReadBufferRect = _libraries['libOpenCL.so.1'].clEnqueueReadBufferRect - clEnqueueReadBufferRect.restype = cl_int - clEnqueueReadBufferRect.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteBuffer = _libraries['libOpenCL.so.1'].clEnqueueWriteBuffer - clEnqueueWriteBuffer.restype = cl_int - clEnqueueWriteBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteBufferRect = _libraries['libOpenCL.so.1'].clEnqueueWriteBufferRect - clEnqueueWriteBufferRect.restype = cl_int - clEnqueueWriteBufferRect.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueFillBuffer = _libraries['libOpenCL.so.1'].clEnqueueFillBuffer - clEnqueueFillBuffer.restype = cl_int - clEnqueueFillBuffer.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBuffer = _libraries['libOpenCL.so.1'].clEnqueueCopyBuffer - clEnqueueCopyBuffer.restype = cl_int - clEnqueueCopyBuffer.argtypes = [cl_command_queue, cl_mem, cl_mem, size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBufferRect = _libraries['libOpenCL.so.1'].clEnqueueCopyBufferRect - clEnqueueCopyBufferRect.restype = cl_int - clEnqueueCopyBufferRect.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueReadImage = _libraries['libOpenCL.so.1'].clEnqueueReadImage - clEnqueueReadImage.restype = cl_int - clEnqueueReadImage.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteImage = _libraries['libOpenCL.so.1'].clEnqueueWriteImage - clEnqueueWriteImage.restype = cl_int - clEnqueueWriteImage.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueFillImage = _libraries['libOpenCL.so.1'].clEnqueueFillImage - clEnqueueFillImage.restype = cl_int - clEnqueueFillImage.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyImage = _libraries['libOpenCL.so.1'].clEnqueueCopyImage - clEnqueueCopyImage.restype = cl_int - clEnqueueCopyImage.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyImageToBuffer = _libraries['libOpenCL.so.1'].clEnqueueCopyImageToBuffer - clEnqueueCopyImageToBuffer.restype = cl_int - clEnqueueCopyImageToBuffer.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBufferToImage = _libraries['libOpenCL.so.1'].clEnqueueCopyBufferToImage - clEnqueueCopyBufferToImage.restype = cl_int - clEnqueueCopyBufferToImage.argtypes = [cl_command_queue, cl_mem, cl_mem, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMapBuffer = _libraries['libOpenCL.so.1'].clEnqueueMapBuffer - clEnqueueMapBuffer.restype = ctypes.POINTER(None) - clEnqueueMapBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, cl_map_flags, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueMapImage = _libraries['libOpenCL.so.1'].clEnqueueMapImage - clEnqueueMapImage.restype = ctypes.POINTER(None) - clEnqueueMapImage.argtypes = [cl_command_queue, cl_mem, cl_bool, cl_map_flags, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueUnmapMemObject = _libraries['libOpenCL.so.1'].clEnqueueUnmapMemObject - clEnqueueUnmapMemObject.restype = cl_int - clEnqueueUnmapMemObject.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMigrateMemObjects = _libraries['libOpenCL.so.1'].clEnqueueMigrateMemObjects - clEnqueueMigrateMemObjects.restype = cl_int - clEnqueueMigrateMemObjects.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_mem)), cl_mem_migration_flags, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueNDRangeKernel = _libraries['libOpenCL.so.1'].clEnqueueNDRangeKernel - clEnqueueNDRangeKernel.restype = cl_int - clEnqueueNDRangeKernel.argtypes = [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueNativeKernel = _libraries['libOpenCL.so.1'].clEnqueueNativeKernel - clEnqueueNativeKernel.restype = cl_int - clEnqueueNativeKernel.argtypes = [cl_command_queue, ctypes.CFUNCTYPE(None, ctypes.POINTER(None)), ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_mem)), ctypes.POINTER(ctypes.POINTER(None)), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMarkerWithWaitList = _libraries['libOpenCL.so.1'].clEnqueueMarkerWithWaitList - clEnqueueMarkerWithWaitList.restype = cl_int - clEnqueueMarkerWithWaitList.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueBarrierWithWaitList = _libraries['libOpenCL.so.1'].clEnqueueBarrierWithWaitList - clEnqueueBarrierWithWaitList.restype = cl_int - clEnqueueBarrierWithWaitList.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMFree = _libraries['libOpenCL.so.1'].clEnqueueSVMFree - clEnqueueSVMFree.restype = cl_int - clEnqueueSVMFree.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(None) * 0, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_command_queue), ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None)), ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMemcpy = _libraries['libOpenCL.so.1'].clEnqueueSVMMemcpy - clEnqueueSVMMemcpy.restype = cl_int - clEnqueueSVMMemcpy.argtypes = [cl_command_queue, cl_bool, ctypes.POINTER(None), ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMemFill = _libraries['libOpenCL.so.1'].clEnqueueSVMMemFill - clEnqueueSVMMemFill.restype = cl_int - clEnqueueSVMMemFill.argtypes = [cl_command_queue, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMap = _libraries['libOpenCL.so.1'].clEnqueueSVMMap - clEnqueueSVMMap.restype = cl_int - clEnqueueSVMMap.argtypes = [cl_command_queue, cl_bool, cl_map_flags, ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMUnmap = _libraries['libOpenCL.so.1'].clEnqueueSVMUnmap - clEnqueueSVMUnmap.restype = cl_int - clEnqueueSVMUnmap.argtypes = [cl_command_queue, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMigrateMem = _libraries['libOpenCL.so.1'].clEnqueueSVMMigrateMem - clEnqueueSVMMigrateMem.restype = cl_int - clEnqueueSVMMigrateMem.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), cl_mem_migration_flags, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clGetExtensionFunctionAddressForPlatform = _libraries['libOpenCL.so.1'].clGetExtensionFunctionAddressForPlatform - clGetExtensionFunctionAddressForPlatform.restype = ctypes.POINTER(None) - clGetExtensionFunctionAddressForPlatform.argtypes = [cl_platform_id, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - clCreateImage2D = _libraries['libOpenCL.so.1'].clCreateImage2D - clCreateImage2D.restype = cl_mem - clCreateImage2D.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), size_t, size_t, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImage3D = _libraries['libOpenCL.so.1'].clCreateImage3D - clCreateImage3D.restype = cl_mem - clCreateImage3D.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), size_t, size_t, size_t, size_t, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueMarker = _libraries['libOpenCL.so.1'].clEnqueueMarker - clEnqueueMarker.restype = cl_int - clEnqueueMarker.argtypes = [cl_command_queue, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWaitForEvents = _libraries['libOpenCL.so.1'].clEnqueueWaitForEvents - clEnqueueWaitForEvents.restype = cl_int - clEnqueueWaitForEvents.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueBarrier = _libraries['libOpenCL.so.1'].clEnqueueBarrier - clEnqueueBarrier.restype = cl_int - clEnqueueBarrier.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clUnloadCompiler = _libraries['libOpenCL.so.1'].clUnloadCompiler - clUnloadCompiler.restype = cl_int - clUnloadCompiler.argtypes = [] -except AttributeError: - pass -try: - clGetExtensionFunctionAddress = _libraries['libOpenCL.so.1'].clGetExtensionFunctionAddress - clGetExtensionFunctionAddress.restype = ctypes.POINTER(None) - clGetExtensionFunctionAddress.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - clCreateCommandQueue = _libraries['libOpenCL.so.1'].clCreateCommandQueue - clCreateCommandQueue.restype = cl_command_queue - clCreateCommandQueue.argtypes = [cl_context, cl_device_id, cl_command_queue_properties, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateSampler = _libraries['libOpenCL.so.1'].clCreateSampler - clCreateSampler.restype = cl_sampler - clCreateSampler.argtypes = [cl_context, cl_bool, cl_addressing_mode, cl_filter_mode, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueTask = _libraries['libOpenCL.so.1'].clEnqueueTask - clEnqueueTask.restype = cl_int - clEnqueueTask.argtypes = [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -__all__ = \ - ['CL_A', 'CL_ABGR', 'CL_ADDRESS_CLAMP', - 'CL_ADDRESS_CLAMP_TO_EDGE', 'CL_ADDRESS_MIRRORED_REPEAT', - 'CL_ADDRESS_NONE', 'CL_ADDRESS_REPEAT', 'CL_ARGB', 'CL_BGRA', - 'CL_BLOCKING', 'CL_BUFFER_CREATE_TYPE_REGION', 'CL_BUILD_ERROR', - 'CL_BUILD_IN_PROGRESS', 'CL_BUILD_NONE', - 'CL_BUILD_PROGRAM_FAILURE', 'CL_BUILD_SUCCESS', - 'CL_COMMAND_ACQUIRE_GL_OBJECTS', 'CL_COMMAND_BARRIER', - 'CL_COMMAND_COPY_BUFFER', 'CL_COMMAND_COPY_BUFFER_RECT', - 'CL_COMMAND_COPY_BUFFER_TO_IMAGE', 'CL_COMMAND_COPY_IMAGE', - 'CL_COMMAND_COPY_IMAGE_TO_BUFFER', 'CL_COMMAND_FILL_BUFFER', - 'CL_COMMAND_FILL_IMAGE', 'CL_COMMAND_MAP_BUFFER', - 'CL_COMMAND_MAP_IMAGE', 'CL_COMMAND_MARKER', - 'CL_COMMAND_MIGRATE_MEM_OBJECTS', 'CL_COMMAND_NATIVE_KERNEL', - 'CL_COMMAND_NDRANGE_KERNEL', 'CL_COMMAND_READ_BUFFER', - 'CL_COMMAND_READ_BUFFER_RECT', 'CL_COMMAND_READ_IMAGE', - 'CL_COMMAND_RELEASE_GL_OBJECTS', 'CL_COMMAND_SVM_FREE', - 'CL_COMMAND_SVM_MAP', 'CL_COMMAND_SVM_MEMCPY', - 'CL_COMMAND_SVM_MEMFILL', 'CL_COMMAND_SVM_MIGRATE_MEM', - 'CL_COMMAND_SVM_UNMAP', 'CL_COMMAND_TASK', - 'CL_COMMAND_UNMAP_MEM_OBJECT', 'CL_COMMAND_USER', - 'CL_COMMAND_WRITE_BUFFER', 'CL_COMMAND_WRITE_BUFFER_RECT', - 'CL_COMMAND_WRITE_IMAGE', 'CL_COMPILER_NOT_AVAILABLE', - 'CL_COMPILE_PROGRAM_FAILURE', 'CL_COMPLETE', 'CL_CONTEXT_DEVICES', - 'CL_CONTEXT_INTEROP_USER_SYNC', 'CL_CONTEXT_NUM_DEVICES', - 'CL_CONTEXT_PLATFORM', 'CL_CONTEXT_PROPERTIES', - 'CL_CONTEXT_REFERENCE_COUNT', 'CL_DEPTH', - 'CL_DEVICE_ADDRESS_BITS', 'CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE', - 'CL_DEVICE_AFFINITY_DOMAIN_NUMA', - 'CL_DEVICE_ATOMIC_FENCE_CAPABILITIES', - 'CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES', - 'CL_DEVICE_ATOMIC_ORDER_ACQ_REL', - 'CL_DEVICE_ATOMIC_ORDER_RELAXED', - 'CL_DEVICE_ATOMIC_ORDER_SEQ_CST', - 'CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES', - 'CL_DEVICE_ATOMIC_SCOPE_DEVICE', - 'CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP', - 'CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM', 'CL_DEVICE_AVAILABLE', - 'CL_DEVICE_BUILT_IN_KERNELS', - 'CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION', - 'CL_DEVICE_COMPILER_AVAILABLE', - 'CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES', - 'CL_DEVICE_DOUBLE_FP_CONFIG', 'CL_DEVICE_ENDIAN_LITTLE', - 'CL_DEVICE_ERROR_CORRECTION_SUPPORT', - 'CL_DEVICE_EXECUTION_CAPABILITIES', 'CL_DEVICE_EXTENSIONS', - 'CL_DEVICE_EXTENSIONS_WITH_VERSION', - 'CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT', - 'CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE', - 'CL_DEVICE_GLOBAL_MEM_CACHE_SIZE', - 'CL_DEVICE_GLOBAL_MEM_CACHE_TYPE', 'CL_DEVICE_GLOBAL_MEM_SIZE', - 'CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE', - 'CL_DEVICE_HOST_UNIFIED_MEMORY', 'CL_DEVICE_ILS_WITH_VERSION', - 'CL_DEVICE_IL_VERSION', 'CL_DEVICE_IMAGE2D_MAX_HEIGHT', - 'CL_DEVICE_IMAGE2D_MAX_WIDTH', 'CL_DEVICE_IMAGE3D_MAX_DEPTH', - 'CL_DEVICE_IMAGE3D_MAX_HEIGHT', 'CL_DEVICE_IMAGE3D_MAX_WIDTH', - 'CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT', - 'CL_DEVICE_IMAGE_MAX_ARRAY_SIZE', - 'CL_DEVICE_IMAGE_MAX_BUFFER_SIZE', - 'CL_DEVICE_IMAGE_PITCH_ALIGNMENT', 'CL_DEVICE_IMAGE_SUPPORT', - 'CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED', - 'CL_DEVICE_LINKER_AVAILABLE', 'CL_DEVICE_LOCAL_MEM_SIZE', - 'CL_DEVICE_LOCAL_MEM_TYPE', 'CL_DEVICE_MAX_CLOCK_FREQUENCY', - 'CL_DEVICE_MAX_COMPUTE_UNITS', 'CL_DEVICE_MAX_CONSTANT_ARGS', - 'CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE', - 'CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE', - 'CL_DEVICE_MAX_MEM_ALLOC_SIZE', 'CL_DEVICE_MAX_NUM_SUB_GROUPS', - 'CL_DEVICE_MAX_ON_DEVICE_EVENTS', - 'CL_DEVICE_MAX_ON_DEVICE_QUEUES', 'CL_DEVICE_MAX_PARAMETER_SIZE', - 'CL_DEVICE_MAX_PIPE_ARGS', 'CL_DEVICE_MAX_READ_IMAGE_ARGS', - 'CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS', 'CL_DEVICE_MAX_SAMPLERS', - 'CL_DEVICE_MAX_WORK_GROUP_SIZE', - 'CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS', - 'CL_DEVICE_MAX_WORK_ITEM_SIZES', 'CL_DEVICE_MAX_WRITE_IMAGE_ARGS', - 'CL_DEVICE_MEM_BASE_ADDR_ALIGN', - 'CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE', 'CL_DEVICE_NAME', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_INT', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT', - 'CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT', - 'CL_DEVICE_NOT_AVAILABLE', 'CL_DEVICE_NOT_FOUND', - 'CL_DEVICE_NUMERIC_VERSION', 'CL_DEVICE_OPENCL_C_ALL_VERSIONS', - 'CL_DEVICE_OPENCL_C_FEATURES', 'CL_DEVICE_OPENCL_C_VERSION', - 'CL_DEVICE_PARENT_DEVICE', 'CL_DEVICE_PARTITION_AFFINITY_DOMAIN', - 'CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN', - 'CL_DEVICE_PARTITION_BY_COUNTS', - 'CL_DEVICE_PARTITION_BY_COUNTS_LIST_END', - 'CL_DEVICE_PARTITION_EQUALLY', 'CL_DEVICE_PARTITION_FAILED', - 'CL_DEVICE_PARTITION_MAX_SUB_DEVICES', - 'CL_DEVICE_PARTITION_PROPERTIES', 'CL_DEVICE_PARTITION_TYPE', - 'CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS', - 'CL_DEVICE_PIPE_MAX_PACKET_SIZE', 'CL_DEVICE_PIPE_SUPPORT', - 'CL_DEVICE_PLATFORM', - 'CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_INTEROP_USER_SYNC', - 'CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT', - 'CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE', - 'CL_DEVICE_PRINTF_BUFFER_SIZE', 'CL_DEVICE_PROFILE', - 'CL_DEVICE_PROFILING_TIMER_RESOLUTION', - 'CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE', - 'CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE', - 'CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES', - 'CL_DEVICE_QUEUE_ON_HOST_PROPERTIES', - 'CL_DEVICE_QUEUE_PROPERTIES', - 'CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT', - 'CL_DEVICE_QUEUE_SUPPORTED', 'CL_DEVICE_REFERENCE_COUNT', - 'CL_DEVICE_SINGLE_FP_CONFIG', - 'CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS', - 'CL_DEVICE_SVM_ATOMICS', 'CL_DEVICE_SVM_CAPABILITIES', - 'CL_DEVICE_SVM_COARSE_GRAIN_BUFFER', - 'CL_DEVICE_SVM_FINE_GRAIN_BUFFER', - 'CL_DEVICE_SVM_FINE_GRAIN_SYSTEM', 'CL_DEVICE_TYPE', - 'CL_DEVICE_TYPE_ACCELERATOR', 'CL_DEVICE_TYPE_ALL', - 'CL_DEVICE_TYPE_CPU', 'CL_DEVICE_TYPE_CUSTOM', - 'CL_DEVICE_TYPE_DEFAULT', 'CL_DEVICE_TYPE_GPU', - 'CL_DEVICE_VENDOR', 'CL_DEVICE_VENDOR_ID', 'CL_DEVICE_VERSION', - 'CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT', - 'CL_DRIVER_VERSION', 'CL_EVENT_COMMAND_EXECUTION_STATUS', - 'CL_EVENT_COMMAND_QUEUE', 'CL_EVENT_COMMAND_TYPE', - 'CL_EVENT_CONTEXT', 'CL_EVENT_REFERENCE_COUNT', 'CL_EXEC_KERNEL', - 'CL_EXEC_NATIVE_KERNEL', - 'CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST', 'CL_FALSE', - 'CL_FILTER_LINEAR', 'CL_FILTER_NEAREST', 'CL_FLOAT', - 'CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT', 'CL_FP_DENORM', - 'CL_FP_FMA', 'CL_FP_INF_NAN', 'CL_FP_ROUND_TO_INF', - 'CL_FP_ROUND_TO_NEAREST', 'CL_FP_ROUND_TO_ZERO', - 'CL_FP_SOFT_FLOAT', 'CL_GLOBAL', 'CL_HALF_FLOAT', - 'CL_IMAGE_ARRAY_SIZE', 'CL_IMAGE_BUFFER', 'CL_IMAGE_DEPTH', - 'CL_IMAGE_ELEMENT_SIZE', 'CL_IMAGE_FORMAT', - 'CL_IMAGE_FORMAT_MISMATCH', 'CL_IMAGE_FORMAT_NOT_SUPPORTED', - 'CL_IMAGE_HEIGHT', 'CL_IMAGE_NUM_MIP_LEVELS', - 'CL_IMAGE_NUM_SAMPLES', 'CL_IMAGE_ROW_PITCH', - 'CL_IMAGE_SLICE_PITCH', 'CL_IMAGE_WIDTH', 'CL_INTENSITY', - 'CL_INVALID_ARG_INDEX', 'CL_INVALID_ARG_SIZE', - 'CL_INVALID_ARG_VALUE', 'CL_INVALID_BINARY', - 'CL_INVALID_BUFFER_SIZE', 'CL_INVALID_BUILD_OPTIONS', - 'CL_INVALID_COMMAND_QUEUE', 'CL_INVALID_COMPILER_OPTIONS', - 'CL_INVALID_CONTEXT', 'CL_INVALID_DEVICE', - 'CL_INVALID_DEVICE_PARTITION_COUNT', 'CL_INVALID_DEVICE_QUEUE', - 'CL_INVALID_DEVICE_TYPE', 'CL_INVALID_EVENT', - 'CL_INVALID_EVENT_WAIT_LIST', 'CL_INVALID_GLOBAL_OFFSET', - 'CL_INVALID_GLOBAL_WORK_SIZE', 'CL_INVALID_GL_OBJECT', - 'CL_INVALID_HOST_PTR', 'CL_INVALID_IMAGE_DESCRIPTOR', - 'CL_INVALID_IMAGE_FORMAT_DESCRIPTOR', 'CL_INVALID_IMAGE_SIZE', - 'CL_INVALID_KERNEL', 'CL_INVALID_KERNEL_ARGS', - 'CL_INVALID_KERNEL_DEFINITION', 'CL_INVALID_KERNEL_NAME', - 'CL_INVALID_LINKER_OPTIONS', 'CL_INVALID_MEM_OBJECT', - 'CL_INVALID_MIP_LEVEL', 'CL_INVALID_OPERATION', - 'CL_INVALID_PIPE_SIZE', 'CL_INVALID_PLATFORM', - 'CL_INVALID_PROGRAM', 'CL_INVALID_PROGRAM_EXECUTABLE', - 'CL_INVALID_PROPERTY', 'CL_INVALID_QUEUE_PROPERTIES', - 'CL_INVALID_SAMPLER', 'CL_INVALID_SPEC_ID', 'CL_INVALID_VALUE', - 'CL_INVALID_WORK_DIMENSION', 'CL_INVALID_WORK_GROUP_SIZE', - 'CL_INVALID_WORK_ITEM_SIZE', 'CL_KERNEL_ARG_ACCESS_NONE', - 'CL_KERNEL_ARG_ACCESS_QUALIFIER', - 'CL_KERNEL_ARG_ACCESS_READ_ONLY', - 'CL_KERNEL_ARG_ACCESS_READ_WRITE', - 'CL_KERNEL_ARG_ACCESS_WRITE_ONLY', - 'CL_KERNEL_ARG_ADDRESS_CONSTANT', 'CL_KERNEL_ARG_ADDRESS_GLOBAL', - 'CL_KERNEL_ARG_ADDRESS_LOCAL', 'CL_KERNEL_ARG_ADDRESS_PRIVATE', - 'CL_KERNEL_ARG_ADDRESS_QUALIFIER', - 'CL_KERNEL_ARG_INFO_NOT_AVAILABLE', 'CL_KERNEL_ARG_NAME', - 'CL_KERNEL_ARG_TYPE_CONST', 'CL_KERNEL_ARG_TYPE_NAME', - 'CL_KERNEL_ARG_TYPE_NONE', 'CL_KERNEL_ARG_TYPE_PIPE', - 'CL_KERNEL_ARG_TYPE_QUALIFIER', 'CL_KERNEL_ARG_TYPE_RESTRICT', - 'CL_KERNEL_ARG_TYPE_VOLATILE', 'CL_KERNEL_ATTRIBUTES', - 'CL_KERNEL_COMPILE_NUM_SUB_GROUPS', - 'CL_KERNEL_COMPILE_WORK_GROUP_SIZE', 'CL_KERNEL_CONTEXT', - 'CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM', - 'CL_KERNEL_EXEC_INFO_SVM_PTRS', 'CL_KERNEL_FUNCTION_NAME', - 'CL_KERNEL_GLOBAL_WORK_SIZE', 'CL_KERNEL_LOCAL_MEM_SIZE', - 'CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT', - 'CL_KERNEL_MAX_NUM_SUB_GROUPS', - 'CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE', 'CL_KERNEL_NUM_ARGS', - 'CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE', - 'CL_KERNEL_PRIVATE_MEM_SIZE', 'CL_KERNEL_PROGRAM', - 'CL_KERNEL_REFERENCE_COUNT', - 'CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE', - 'CL_KERNEL_WORK_GROUP_SIZE', 'CL_KHRONOS_VENDOR_ID_CODEPLAY', - 'CL_LINKER_NOT_AVAILABLE', 'CL_LINK_PROGRAM_FAILURE', 'CL_LOCAL', - 'CL_LUMINANCE', 'CL_MAP_FAILURE', 'CL_MAP_READ', 'CL_MAP_WRITE', - 'CL_MAP_WRITE_INVALIDATE_REGION', - 'CL_MAX_SIZE_RESTRICTION_EXCEEDED', 'CL_MEM_ALLOC_HOST_PTR', - 'CL_MEM_ASSOCIATED_MEMOBJECT', 'CL_MEM_CONTEXT', - 'CL_MEM_COPY_HOST_PTR', 'CL_MEM_COPY_OVERLAP', 'CL_MEM_FLAGS', - 'CL_MEM_HOST_NO_ACCESS', 'CL_MEM_HOST_PTR', - 'CL_MEM_HOST_READ_ONLY', 'CL_MEM_HOST_WRITE_ONLY', - 'CL_MEM_KERNEL_READ_AND_WRITE', 'CL_MEM_MAP_COUNT', - 'CL_MEM_OBJECT_ALLOCATION_FAILURE', 'CL_MEM_OBJECT_BUFFER', - 'CL_MEM_OBJECT_IMAGE1D', 'CL_MEM_OBJECT_IMAGE1D_ARRAY', - 'CL_MEM_OBJECT_IMAGE1D_BUFFER', 'CL_MEM_OBJECT_IMAGE2D', - 'CL_MEM_OBJECT_IMAGE2D_ARRAY', 'CL_MEM_OBJECT_IMAGE3D', - 'CL_MEM_OBJECT_PIPE', 'CL_MEM_OFFSET', 'CL_MEM_PROPERTIES', - 'CL_MEM_READ_ONLY', 'CL_MEM_READ_WRITE', 'CL_MEM_REFERENCE_COUNT', - 'CL_MEM_SIZE', 'CL_MEM_SVM_ATOMICS', - 'CL_MEM_SVM_FINE_GRAIN_BUFFER', 'CL_MEM_TYPE', - 'CL_MEM_USES_SVM_POINTER', 'CL_MEM_USE_HOST_PTR', - 'CL_MEM_WRITE_ONLY', 'CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED', - 'CL_MIGRATE_MEM_OBJECT_HOST', 'CL_MISALIGNED_SUB_BUFFER_OFFSET', - 'CL_NAME_VERSION_MAX_NAME_SIZE', 'CL_NONE', 'CL_NON_BLOCKING', - 'CL_OUT_OF_HOST_MEMORY', 'CL_OUT_OF_RESOURCES', - 'CL_PIPE_MAX_PACKETS', 'CL_PIPE_PACKET_SIZE', - 'CL_PIPE_PROPERTIES', 'CL_PLATFORM_EXTENSIONS', - 'CL_PLATFORM_EXTENSIONS_WITH_VERSION', - 'CL_PLATFORM_HOST_TIMER_RESOLUTION', 'CL_PLATFORM_NAME', - 'CL_PLATFORM_NUMERIC_VERSION', 'CL_PLATFORM_PROFILE', - 'CL_PLATFORM_VENDOR', 'CL_PLATFORM_VERSION', - 'CL_PROFILING_COMMAND_COMPLETE', 'CL_PROFILING_COMMAND_END', - 'CL_PROFILING_COMMAND_QUEUED', 'CL_PROFILING_COMMAND_START', - 'CL_PROFILING_COMMAND_SUBMIT', 'CL_PROFILING_INFO_NOT_AVAILABLE', - 'CL_PROGRAM_BINARIES', 'CL_PROGRAM_BINARY_SIZES', - 'CL_PROGRAM_BINARY_TYPE', - 'CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT', - 'CL_PROGRAM_BINARY_TYPE_EXECUTABLE', - 'CL_PROGRAM_BINARY_TYPE_LIBRARY', 'CL_PROGRAM_BINARY_TYPE_NONE', - 'CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE', - 'CL_PROGRAM_BUILD_LOG', 'CL_PROGRAM_BUILD_OPTIONS', - 'CL_PROGRAM_BUILD_STATUS', 'CL_PROGRAM_CONTEXT', - 'CL_PROGRAM_DEVICES', 'CL_PROGRAM_IL', 'CL_PROGRAM_KERNEL_NAMES', - 'CL_PROGRAM_NUM_DEVICES', 'CL_PROGRAM_NUM_KERNELS', - 'CL_PROGRAM_REFERENCE_COUNT', - 'CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT', - 'CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT', 'CL_PROGRAM_SOURCE', - 'CL_QUEUED', 'CL_QUEUE_CONTEXT', 'CL_QUEUE_DEVICE', - 'CL_QUEUE_DEVICE_DEFAULT', 'CL_QUEUE_ON_DEVICE', - 'CL_QUEUE_ON_DEVICE_DEFAULT', - 'CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE', - 'CL_QUEUE_PROFILING_ENABLE', 'CL_QUEUE_PROPERTIES', - 'CL_QUEUE_PROPERTIES_ARRAY', 'CL_QUEUE_REFERENCE_COUNT', - 'CL_QUEUE_SIZE', 'CL_R', 'CL_RA', 'CL_READ_ONLY_CACHE', - 'CL_READ_WRITE_CACHE', 'CL_RG', 'CL_RGB', 'CL_RGBA', 'CL_RGBx', - 'CL_RGx', 'CL_RUNNING', 'CL_Rx', 'CL_SAMPLER_ADDRESSING_MODE', - 'CL_SAMPLER_CONTEXT', 'CL_SAMPLER_FILTER_MODE', - 'CL_SAMPLER_LOD_MAX', 'CL_SAMPLER_LOD_MIN', - 'CL_SAMPLER_MIP_FILTER_MODE', 'CL_SAMPLER_NORMALIZED_COORDS', - 'CL_SAMPLER_PROPERTIES', 'CL_SAMPLER_REFERENCE_COUNT', - 'CL_SIGNED_INT16', 'CL_SIGNED_INT32', 'CL_SIGNED_INT8', - 'CL_SNORM_INT16', 'CL_SNORM_INT8', 'CL_SUBMITTED', 'CL_SUCCESS', - 'CL_TRUE', 'CL_UNORM_INT16', 'CL_UNORM_INT8', - 'CL_UNORM_INT_101010', 'CL_UNORM_INT_101010_2', - 'CL_UNORM_SHORT_555', 'CL_UNORM_SHORT_565', 'CL_UNSIGNED_INT16', - 'CL_UNSIGNED_INT32', 'CL_UNSIGNED_INT8', 'CL_VERSION_MAJOR_BITS', - 'CL_VERSION_MAJOR_MASK', 'CL_VERSION_MINOR_BITS', - 'CL_VERSION_MINOR_MASK', 'CL_VERSION_PATCH_BITS', - 'CL_VERSION_PATCH_MASK', 'CL_sBGRA', 'CL_sRGB', 'CL_sRGBA', - 'CL_sRGBx', '__OPENCL_CL_H', 'clBuildProgram', 'clCloneKernel', - 'clCompileProgram', 'clCreateBuffer', - 'clCreateBufferWithProperties', 'clCreateCommandQueue', - 'clCreateCommandQueueWithProperties', 'clCreateContext', - 'clCreateContextFromType', 'clCreateImage', 'clCreateImage2D', - 'clCreateImage3D', 'clCreateImageWithProperties', - 'clCreateKernel', 'clCreateKernelsInProgram', 'clCreatePipe', - 'clCreateProgramWithBinary', 'clCreateProgramWithBuiltInKernels', - 'clCreateProgramWithIL', 'clCreateProgramWithSource', - 'clCreateSampler', 'clCreateSamplerWithProperties', - 'clCreateSubBuffer', 'clCreateSubDevices', 'clCreateUserEvent', - 'clEnqueueBarrier', 'clEnqueueBarrierWithWaitList', - 'clEnqueueCopyBuffer', 'clEnqueueCopyBufferRect', - 'clEnqueueCopyBufferToImage', 'clEnqueueCopyImage', - 'clEnqueueCopyImageToBuffer', 'clEnqueueFillBuffer', - 'clEnqueueFillImage', 'clEnqueueMapBuffer', 'clEnqueueMapImage', - 'clEnqueueMarker', 'clEnqueueMarkerWithWaitList', - 'clEnqueueMigrateMemObjects', 'clEnqueueNDRangeKernel', - 'clEnqueueNativeKernel', 'clEnqueueReadBuffer', - 'clEnqueueReadBufferRect', 'clEnqueueReadImage', - 'clEnqueueSVMFree', 'clEnqueueSVMMap', 'clEnqueueSVMMemFill', - 'clEnqueueSVMMemcpy', 'clEnqueueSVMMigrateMem', - 'clEnqueueSVMUnmap', 'clEnqueueTask', 'clEnqueueUnmapMemObject', - 'clEnqueueWaitForEvents', 'clEnqueueWriteBuffer', - 'clEnqueueWriteBufferRect', 'clEnqueueWriteImage', 'clFinish', - 'clFlush', 'clGetCommandQueueInfo', 'clGetContextInfo', - 'clGetDeviceAndHostTimer', 'clGetDeviceIDs', 'clGetDeviceInfo', - 'clGetEventInfo', 'clGetEventProfilingInfo', - 'clGetExtensionFunctionAddress', - 'clGetExtensionFunctionAddressForPlatform', 'clGetHostTimer', - 'clGetImageInfo', 'clGetKernelArgInfo', 'clGetKernelInfo', - 'clGetKernelSubGroupInfo', 'clGetKernelWorkGroupInfo', - 'clGetMemObjectInfo', 'clGetPipeInfo', 'clGetPlatformIDs', - 'clGetPlatformInfo', 'clGetProgramBuildInfo', 'clGetProgramInfo', - 'clGetSamplerInfo', 'clGetSupportedImageFormats', 'clLinkProgram', - 'clReleaseCommandQueue', 'clReleaseContext', 'clReleaseDevice', - 'clReleaseEvent', 'clReleaseKernel', 'clReleaseMemObject', - 'clReleaseProgram', 'clReleaseSampler', 'clRetainCommandQueue', - 'clRetainContext', 'clRetainDevice', 'clRetainEvent', - 'clRetainKernel', 'clRetainMemObject', 'clRetainProgram', - 'clRetainSampler', 'clSVMAlloc', 'clSVMFree', - 'clSetContextDestructorCallback', - 'clSetDefaultDeviceCommandQueue', 'clSetEventCallback', - 'clSetKernelArg', 'clSetKernelArgSVMPointer', - 'clSetKernelExecInfo', 'clSetMemObjectDestructorCallback', - 'clSetProgramReleaseCallback', - 'clSetProgramSpecializationConstant', 'clSetUserEventStatus', - 'clUnloadCompiler', 'clUnloadPlatformCompiler', 'clWaitForEvents', - 'cl_addressing_mode', 'cl_bitfield', 'cl_bool', - 'cl_buffer_create_type', 'cl_buffer_region', 'cl_build_status', - 'cl_channel_order', 'cl_channel_type', 'cl_command_queue', - 'cl_command_queue_info', 'cl_command_queue_properties', - 'cl_command_type', 'cl_context', 'cl_context_info', - 'cl_context_properties', 'cl_device_affinity_domain', - 'cl_device_atomic_capabilities', - 'cl_device_device_enqueue_capabilities', - 'cl_device_exec_capabilities', 'cl_device_fp_config', - 'cl_device_id', 'cl_device_info', 'cl_device_local_mem_type', - 'cl_device_mem_cache_type', 'cl_device_partition_property', - 'cl_device_svm_capabilities', 'cl_device_type', 'cl_event', - 'cl_event_info', 'cl_filter_mode', 'cl_image_desc', - 'cl_image_format', 'cl_image_info', 'cl_int', 'cl_kernel', - 'cl_kernel_arg_access_qualifier', - 'cl_kernel_arg_address_qualifier', 'cl_kernel_arg_info', - 'cl_kernel_arg_type_qualifier', 'cl_kernel_exec_info', - 'cl_kernel_info', 'cl_kernel_sub_group_info', - 'cl_kernel_work_group_info', 'cl_khronos_vendor_id', - 'cl_map_flags', 'cl_mem', 'cl_mem_flags', 'cl_mem_info', - 'cl_mem_migration_flags', 'cl_mem_object_type', - 'cl_mem_properties', 'cl_name_version', 'cl_pipe_info', - 'cl_pipe_properties', 'cl_platform_id', 'cl_platform_info', - 'cl_profiling_info', 'cl_program', 'cl_program_binary_type', - 'cl_program_build_info', 'cl_program_info', 'cl_properties', - 'cl_queue_properties', 'cl_sampler', 'cl_sampler_info', - 'cl_sampler_properties', 'cl_svm_mem_flags', 'cl_uint', - 'cl_version', 'size_t', 'struct__cl_buffer_region', - 'struct__cl_command_queue', 'struct__cl_context', - 'struct__cl_device_id', 'struct__cl_event', - 'struct__cl_image_desc', 'struct__cl_image_format', - 'struct__cl_kernel', 'struct__cl_mem', 'struct__cl_name_version', - 'struct__cl_platform_id', 'struct__cl_program', - 'struct__cl_sampler', 'union__cl_image_desc_0'] diff --git a/tinygrad/tinygrad/runtime/autogen/pci.py b/tinygrad/tinygrad/runtime/autogen/pci.py deleted file mode 100644 index 82ec9c13..00000000 --- a/tinygrad/tinygrad/runtime/autogen/pci.py +++ /dev/null @@ -1,1333 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - - - -LINUX_PCI_REGS_H = True # macro -PCI_CFG_SPACE_SIZE = 256 # macro -PCI_CFG_SPACE_EXP_SIZE = 4096 # macro -PCI_STD_HEADER_SIZEOF = 64 # macro -PCI_STD_NUM_BARS = 6 # macro -PCI_VENDOR_ID = 0x00 # macro -PCI_DEVICE_ID = 0x02 # macro -PCI_COMMAND = 0x04 # macro -PCI_COMMAND_IO = 0x1 # macro -PCI_COMMAND_MEMORY = 0x2 # macro -PCI_COMMAND_MASTER = 0x4 # macro -PCI_COMMAND_SPECIAL = 0x8 # macro -PCI_COMMAND_INVALIDATE = 0x10 # macro -PCI_COMMAND_VGA_PALETTE = 0x20 # macro -PCI_COMMAND_PARITY = 0x40 # macro -PCI_COMMAND_WAIT = 0x80 # macro -PCI_COMMAND_SERR = 0x100 # macro -PCI_COMMAND_FAST_BACK = 0x200 # macro -PCI_COMMAND_INTX_DISABLE = 0x400 # macro -PCI_STATUS = 0x06 # macro -PCI_STATUS_IMM_READY = 0x01 # macro -PCI_STATUS_INTERRUPT = 0x08 # macro -PCI_STATUS_CAP_LIST = 0x10 # macro -PCI_STATUS_66MHZ = 0x20 # macro -PCI_STATUS_UDF = 0x40 # macro -PCI_STATUS_FAST_BACK = 0x80 # macro -PCI_STATUS_PARITY = 0x100 # macro -PCI_STATUS_DEVSEL_MASK = 0x600 # macro -PCI_STATUS_DEVSEL_FAST = 0x000 # macro -PCI_STATUS_DEVSEL_MEDIUM = 0x200 # macro -PCI_STATUS_DEVSEL_SLOW = 0x400 # macro -PCI_STATUS_SIG_TARGET_ABORT = 0x800 # macro -PCI_STATUS_REC_TARGET_ABORT = 0x1000 # macro -PCI_STATUS_REC_MASTER_ABORT = 0x2000 # macro -PCI_STATUS_SIG_SYSTEM_ERROR = 0x4000 # macro -PCI_STATUS_DETECTED_PARITY = 0x8000 # macro -PCI_CLASS_REVISION = 0x08 # macro -PCI_REVISION_ID = 0x08 # macro -PCI_CLASS_PROG = 0x09 # macro -PCI_CLASS_DEVICE = 0x0a # macro -PCI_CACHE_LINE_SIZE = 0x0c # macro -PCI_LATENCY_TIMER = 0x0d # macro -PCI_HEADER_TYPE = 0x0e # macro -PCI_HEADER_TYPE_MASK = 0x7f # macro -PCI_HEADER_TYPE_NORMAL = 0 # macro -PCI_HEADER_TYPE_BRIDGE = 1 # macro -PCI_HEADER_TYPE_CARDBUS = 2 # macro -PCI_BIST = 0x0f # macro -PCI_BIST_CODE_MASK = 0x0f # macro -PCI_BIST_START = 0x40 # macro -PCI_BIST_CAPABLE = 0x80 # macro -PCI_BASE_ADDRESS_0 = 0x10 # macro -PCI_BASE_ADDRESS_1 = 0x14 # macro -PCI_BASE_ADDRESS_2 = 0x18 # macro -PCI_BASE_ADDRESS_3 = 0x1c # macro -PCI_BASE_ADDRESS_4 = 0x20 # macro -PCI_BASE_ADDRESS_5 = 0x24 # macro -PCI_BASE_ADDRESS_SPACE = 0x01 # macro -PCI_BASE_ADDRESS_SPACE_IO = 0x01 # macro -PCI_BASE_ADDRESS_SPACE_MEMORY = 0x00 # macro -PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x06 # macro -PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x00 # macro -PCI_BASE_ADDRESS_MEM_TYPE_1M = 0x02 # macro -PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x04 # macro -PCI_BASE_ADDRESS_MEM_PREFETCH = 0x08 # macro -PCI_BASE_ADDRESS_MEM_MASK = (~0x0f) # macro -PCI_BASE_ADDRESS_IO_MASK = (~0x03) # macro -PCI_CARDBUS_CIS = 0x28 # macro -PCI_SUBSYSTEM_VENDOR_ID = 0x2c # macro -PCI_SUBSYSTEM_ID = 0x2e # macro -PCI_ROM_ADDRESS = 0x30 # macro -PCI_ROM_ADDRESS_ENABLE = 0x01 # macro -PCI_ROM_ADDRESS_MASK = (~0x7ff) # macro -PCI_CAPABILITY_LIST = 0x34 # macro -PCI_INTERRUPT_LINE = 0x3c # macro -PCI_INTERRUPT_PIN = 0x3d # macro -PCI_MIN_GNT = 0x3e # macro -PCI_MAX_LAT = 0x3f # macro -PCI_PRIMARY_BUS = 0x18 # macro -PCI_SECONDARY_BUS = 0x19 # macro -PCI_SUBORDINATE_BUS = 0x1a # macro -PCI_SEC_LATENCY_TIMER = 0x1b # macro -PCI_IO_BASE = 0x1c # macro -PCI_IO_LIMIT = 0x1d # macro -PCI_IO_RANGE_TYPE_MASK = 0x0f # macro -PCI_IO_RANGE_TYPE_16 = 0x00 # macro -PCI_IO_RANGE_TYPE_32 = 0x01 # macro -PCI_IO_RANGE_MASK = (~0x0f) # macro -PCI_IO_1K_RANGE_MASK = (~0x03) # macro -PCI_SEC_STATUS = 0x1e # macro -PCI_MEMORY_BASE = 0x20 # macro -PCI_MEMORY_LIMIT = 0x22 # macro -PCI_MEMORY_RANGE_TYPE_MASK = 0x0f # macro -PCI_MEMORY_RANGE_MASK = (~0x0f) # macro -PCI_PREF_MEMORY_BASE = 0x24 # macro -PCI_PREF_MEMORY_LIMIT = 0x26 # macro -PCI_PREF_RANGE_TYPE_MASK = 0x0f # macro -PCI_PREF_RANGE_TYPE_32 = 0x00 # macro -PCI_PREF_RANGE_TYPE_64 = 0x01 # macro -PCI_PREF_RANGE_MASK = (~0x0f) # macro -PCI_PREF_BASE_UPPER32 = 0x28 # macro -PCI_PREF_LIMIT_UPPER32 = 0x2c # macro -PCI_IO_BASE_UPPER16 = 0x30 # macro -PCI_IO_LIMIT_UPPER16 = 0x32 # macro -PCI_ROM_ADDRESS1 = 0x38 # macro -PCI_BRIDGE_CONTROL = 0x3e # macro -PCI_BRIDGE_CTL_PARITY = 0x01 # macro -PCI_BRIDGE_CTL_SERR = 0x02 # macro -PCI_BRIDGE_CTL_ISA = 0x04 # macro -PCI_BRIDGE_CTL_VGA = 0x08 # macro -PCI_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro -PCI_BRIDGE_CTL_BUS_RESET = 0x40 # macro -PCI_BRIDGE_CTL_FAST_BACK = 0x80 # macro -PCI_CB_CAPABILITY_LIST = 0x14 # macro -PCI_CB_SEC_STATUS = 0x16 # macro -PCI_CB_PRIMARY_BUS = 0x18 # macro -PCI_CB_CARD_BUS = 0x19 # macro -PCI_CB_SUBORDINATE_BUS = 0x1a # macro -PCI_CB_LATENCY_TIMER = 0x1b # macro -PCI_CB_MEMORY_BASE_0 = 0x1c # macro -PCI_CB_MEMORY_LIMIT_0 = 0x20 # macro -PCI_CB_MEMORY_BASE_1 = 0x24 # macro -PCI_CB_MEMORY_LIMIT_1 = 0x28 # macro -PCI_CB_IO_BASE_0 = 0x2c # macro -PCI_CB_IO_BASE_0_HI = 0x2e # macro -PCI_CB_IO_LIMIT_0 = 0x30 # macro -PCI_CB_IO_LIMIT_0_HI = 0x32 # macro -PCI_CB_IO_BASE_1 = 0x34 # macro -PCI_CB_IO_BASE_1_HI = 0x36 # macro -PCI_CB_IO_LIMIT_1 = 0x38 # macro -PCI_CB_IO_LIMIT_1_HI = 0x3a # macro -PCI_CB_IO_RANGE_MASK = (~0x03) # macro -PCI_CB_BRIDGE_CONTROL = 0x3e # macro -PCI_CB_BRIDGE_CTL_PARITY = 0x01 # macro -PCI_CB_BRIDGE_CTL_SERR = 0x02 # macro -PCI_CB_BRIDGE_CTL_ISA = 0x04 # macro -PCI_CB_BRIDGE_CTL_VGA = 0x08 # macro -PCI_CB_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro -PCI_CB_BRIDGE_CTL_CB_RESET = 0x40 # macro -PCI_CB_BRIDGE_CTL_16BIT_INT = 0x80 # macro -PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 = 0x100 # macro -PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 = 0x200 # macro -PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400 # macro -PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40 # macro -PCI_CB_SUBSYSTEM_ID = 0x42 # macro -PCI_CB_LEGACY_MODE_BASE = 0x44 # macro -PCI_CAP_LIST_ID = 0 # macro -PCI_CAP_ID_PM = 0x01 # macro -PCI_CAP_ID_AGP = 0x02 # macro -PCI_CAP_ID_VPD = 0x03 # macro -PCI_CAP_ID_SLOTID = 0x04 # macro -PCI_CAP_ID_MSI = 0x05 # macro -PCI_CAP_ID_CHSWP = 0x06 # macro -PCI_CAP_ID_PCIX = 0x07 # macro -PCI_CAP_ID_HT = 0x08 # macro -PCI_CAP_ID_VNDR = 0x09 # macro -PCI_CAP_ID_DBG = 0x0A # macro -PCI_CAP_ID_CCRC = 0x0B # macro -PCI_CAP_ID_SHPC = 0x0C # macro -PCI_CAP_ID_SSVID = 0x0D # macro -PCI_CAP_ID_AGP3 = 0x0E # macro -PCI_CAP_ID_SECDEV = 0x0F # macro -PCI_CAP_ID_EXP = 0x10 # macro -PCI_CAP_ID_MSIX = 0x11 # macro -PCI_CAP_ID_SATA = 0x12 # macro -PCI_CAP_ID_AF = 0x13 # macro -PCI_CAP_ID_EA = 0x14 # macro -PCI_CAP_ID_MAX = 0x14 # macro -PCI_CAP_LIST_NEXT = 1 # macro -PCI_CAP_FLAGS = 2 # macro -PCI_CAP_SIZEOF = 4 # macro -PCI_PM_PMC = 2 # macro -PCI_PM_CAP_VER_MASK = 0x0007 # macro -PCI_PM_CAP_PME_CLOCK = 0x0008 # macro -PCI_PM_CAP_RESERVED = 0x0010 # macro -PCI_PM_CAP_DSI = 0x0020 # macro -PCI_PM_CAP_AUX_POWER = 0x01C0 # macro -PCI_PM_CAP_D1 = 0x0200 # macro -PCI_PM_CAP_D2 = 0x0400 # macro -PCI_PM_CAP_PME = 0x0800 # macro -PCI_PM_CAP_PME_MASK = 0xF800 # macro -PCI_PM_CAP_PME_D0 = 0x0800 # macro -PCI_PM_CAP_PME_D1 = 0x1000 # macro -PCI_PM_CAP_PME_D2 = 0x2000 # macro -PCI_PM_CAP_PME_D3hot = 0x4000 # macro -PCI_PM_CAP_PME_D3cold = 0x8000 # macro -PCI_PM_CAP_PME_SHIFT = 11 # macro -PCI_PM_CTRL = 4 # macro -PCI_PM_CTRL_STATE_MASK = 0x0003 # macro -PCI_PM_CTRL_NO_SOFT_RESET = 0x0008 # macro -PCI_PM_CTRL_PME_ENABLE = 0x0100 # macro -PCI_PM_CTRL_DATA_SEL_MASK = 0x1e00 # macro -PCI_PM_CTRL_DATA_SCALE_MASK = 0x6000 # macro -PCI_PM_CTRL_PME_STATUS = 0x8000 # macro -PCI_PM_PPB_EXTENSIONS = 6 # macro -PCI_PM_PPB_B2_B3 = 0x40 # macro -PCI_PM_BPCC_ENABLE = 0x80 # macro -PCI_PM_DATA_REGISTER = 7 # macro -PCI_PM_SIZEOF = 8 # macro -PCI_AGP_VERSION = 2 # macro -PCI_AGP_RFU = 3 # macro -PCI_AGP_STATUS = 4 # macro -PCI_AGP_STATUS_RQ_MASK = 0xff000000 # macro -PCI_AGP_STATUS_SBA = 0x0200 # macro -PCI_AGP_STATUS_64BIT = 0x0020 # macro -PCI_AGP_STATUS_FW = 0x0010 # macro -PCI_AGP_STATUS_RATE4 = 0x0004 # macro -PCI_AGP_STATUS_RATE2 = 0x0002 # macro -PCI_AGP_STATUS_RATE1 = 0x0001 # macro -PCI_AGP_COMMAND = 8 # macro -PCI_AGP_COMMAND_RQ_MASK = 0xff000000 # macro -PCI_AGP_COMMAND_SBA = 0x0200 # macro -PCI_AGP_COMMAND_AGP = 0x0100 # macro -PCI_AGP_COMMAND_64BIT = 0x0020 # macro -PCI_AGP_COMMAND_FW = 0x0010 # macro -PCI_AGP_COMMAND_RATE4 = 0x0004 # macro -PCI_AGP_COMMAND_RATE2 = 0x0002 # macro -PCI_AGP_COMMAND_RATE1 = 0x0001 # macro -PCI_AGP_SIZEOF = 12 # macro -PCI_VPD_ADDR = 2 # macro -PCI_VPD_ADDR_MASK = 0x7fff # macro -PCI_VPD_ADDR_F = 0x8000 # macro -PCI_VPD_DATA = 4 # macro -PCI_CAP_VPD_SIZEOF = 8 # macro -PCI_SID_ESR = 2 # macro -PCI_SID_ESR_NSLOTS = 0x1f # macro -PCI_SID_ESR_FIC = 0x20 # macro -PCI_SID_CHASSIS_NR = 3 # macro -PCI_MSI_FLAGS = 2 # macro -PCI_MSI_FLAGS_ENABLE = 0x0001 # macro -PCI_MSI_FLAGS_QMASK = 0x000e # macro -PCI_MSI_FLAGS_QSIZE = 0x0070 # macro -PCI_MSI_FLAGS_64BIT = 0x0080 # macro -PCI_MSI_FLAGS_MASKBIT = 0x0100 # macro -PCI_MSI_RFU = 3 # macro -PCI_MSI_ADDRESS_LO = 4 # macro -PCI_MSI_ADDRESS_HI = 8 # macro -PCI_MSI_DATA_32 = 8 # macro -PCI_MSI_MASK_32 = 12 # macro -PCI_MSI_PENDING_32 = 16 # macro -PCI_MSI_DATA_64 = 12 # macro -PCI_MSI_MASK_64 = 16 # macro -PCI_MSI_PENDING_64 = 20 # macro -PCI_MSIX_FLAGS = 2 # macro -PCI_MSIX_FLAGS_QSIZE = 0x07FF # macro -PCI_MSIX_FLAGS_MASKALL = 0x4000 # macro -PCI_MSIX_FLAGS_ENABLE = 0x8000 # macro -PCI_MSIX_TABLE = 4 # macro -PCI_MSIX_TABLE_BIR = 0x00000007 # macro -PCI_MSIX_TABLE_OFFSET = 0xfffffff8 # macro -PCI_MSIX_PBA = 8 # macro -PCI_MSIX_PBA_BIR = 0x00000007 # macro -PCI_MSIX_PBA_OFFSET = 0xfffffff8 # macro -PCI_MSIX_FLAGS_BIRMASK = 0x00000007 # macro -PCI_CAP_MSIX_SIZEOF = 12 # macro -PCI_MSIX_ENTRY_SIZE = 16 # macro -PCI_MSIX_ENTRY_LOWER_ADDR = 0 # macro -PCI_MSIX_ENTRY_UPPER_ADDR = 4 # macro -PCI_MSIX_ENTRY_DATA = 8 # macro -PCI_MSIX_ENTRY_VECTOR_CTRL = 12 # macro -PCI_MSIX_ENTRY_CTRL_MASKBIT = 0x00000001 # macro -PCI_CHSWP_CSR = 2 # macro -PCI_CHSWP_DHA = 0x01 # macro -PCI_CHSWP_EIM = 0x02 # macro -PCI_CHSWP_PIE = 0x04 # macro -PCI_CHSWP_LOO = 0x08 # macro -PCI_CHSWP_PI = 0x30 # macro -PCI_CHSWP_EXT = 0x40 # macro -PCI_CHSWP_INS = 0x80 # macro -PCI_AF_LENGTH = 2 # macro -PCI_AF_CAP = 3 # macro -PCI_AF_CAP_TP = 0x01 # macro -PCI_AF_CAP_FLR = 0x02 # macro -PCI_AF_CTRL = 4 # macro -PCI_AF_CTRL_FLR = 0x01 # macro -PCI_AF_STATUS = 5 # macro -PCI_AF_STATUS_TP = 0x01 # macro -PCI_CAP_AF_SIZEOF = 6 # macro -PCI_EA_NUM_ENT = 2 # macro -PCI_EA_NUM_ENT_MASK = 0x3f # macro -PCI_EA_FIRST_ENT = 4 # macro -PCI_EA_FIRST_ENT_BRIDGE = 8 # macro -PCI_EA_ES = 0x00000007 # macro -PCI_EA_BEI = 0x000000f0 # macro -PCI_EA_SEC_BUS_MASK = 0xff # macro -PCI_EA_SUB_BUS_MASK = 0xff00 # macro -PCI_EA_SUB_BUS_SHIFT = 8 # macro -PCI_EA_BEI_BAR0 = 0 # macro -PCI_EA_BEI_BAR5 = 5 # macro -PCI_EA_BEI_BRIDGE = 6 # macro -PCI_EA_BEI_ENI = 7 # macro -PCI_EA_BEI_ROM = 8 # macro -PCI_EA_BEI_VF_BAR0 = 9 # macro -PCI_EA_BEI_VF_BAR5 = 14 # macro -PCI_EA_BEI_RESERVED = 15 # macro -PCI_EA_PP = 0x0000ff00 # macro -PCI_EA_SP = 0x00ff0000 # macro -PCI_EA_P_MEM = 0x00 # macro -PCI_EA_P_MEM_PREFETCH = 0x01 # macro -PCI_EA_P_IO = 0x02 # macro -PCI_EA_P_VF_MEM_PREFETCH = 0x03 # macro -PCI_EA_P_VF_MEM = 0x04 # macro -PCI_EA_P_BRIDGE_MEM = 0x05 # macro -PCI_EA_P_BRIDGE_MEM_PREFETCH = 0x06 # macro -PCI_EA_P_BRIDGE_IO = 0x07 # macro -PCI_EA_P_MEM_RESERVED = 0xfd # macro -PCI_EA_P_IO_RESERVED = 0xfe # macro -PCI_EA_P_UNAVAILABLE = 0xff # macro -PCI_EA_WRITABLE = 0x40000000 # macro -PCI_EA_ENABLE = 0x80000000 # macro -PCI_EA_BASE = 4 # macro -PCI_EA_MAX_OFFSET = 8 # macro -PCI_EA_IS_64 = 0x00000002 # macro -PCI_EA_FIELD_MASK = 0xfffffffc # macro -PCI_X_CMD = 2 # macro -PCI_X_CMD_DPERR_E = 0x0001 # macro -PCI_X_CMD_ERO = 0x0002 # macro -PCI_X_CMD_READ_512 = 0x0000 # macro -PCI_X_CMD_READ_1K = 0x0004 # macro -PCI_X_CMD_READ_2K = 0x0008 # macro -PCI_X_CMD_READ_4K = 0x000c # macro -PCI_X_CMD_MAX_READ = 0x000c # macro -PCI_X_CMD_SPLIT_1 = 0x0000 # macro -PCI_X_CMD_SPLIT_2 = 0x0010 # macro -PCI_X_CMD_SPLIT_3 = 0x0020 # macro -PCI_X_CMD_SPLIT_4 = 0x0030 # macro -PCI_X_CMD_SPLIT_8 = 0x0040 # macro -PCI_X_CMD_SPLIT_12 = 0x0050 # macro -PCI_X_CMD_SPLIT_16 = 0x0060 # macro -PCI_X_CMD_SPLIT_32 = 0x0070 # macro -PCI_X_CMD_MAX_SPLIT = 0x0070 # macro -def PCI_X_CMD_VERSION(x): # macro - return (((x)>>12)&3) -PCI_X_STATUS = 4 # macro -PCI_X_STATUS_DEVFN = 0x000000ff # macro -PCI_X_STATUS_BUS = 0x0000ff00 # macro -PCI_X_STATUS_64BIT = 0x00010000 # macro -PCI_X_STATUS_133MHZ = 0x00020000 # macro -PCI_X_STATUS_SPL_DISC = 0x00040000 # macro -PCI_X_STATUS_UNX_SPL = 0x00080000 # macro -PCI_X_STATUS_COMPLEX = 0x00100000 # macro -PCI_X_STATUS_MAX_READ = 0x00600000 # macro -PCI_X_STATUS_MAX_SPLIT = 0x03800000 # macro -PCI_X_STATUS_MAX_CUM = 0x1c000000 # macro -PCI_X_STATUS_SPL_ERR = 0x20000000 # macro -PCI_X_STATUS_266MHZ = 0x40000000 # macro -PCI_X_STATUS_533MHZ = 0x80000000 # macro -PCI_X_ECC_CSR = 8 # macro -PCI_CAP_PCIX_SIZEOF_V0 = 8 # macro -PCI_CAP_PCIX_SIZEOF_V1 = 24 # macro -PCI_CAP_PCIX_SIZEOF_V2 = 24 # macro -PCI_X_BRIDGE_SSTATUS = 2 # macro -PCI_X_SSTATUS_64BIT = 0x0001 # macro -PCI_X_SSTATUS_133MHZ = 0x0002 # macro -PCI_X_SSTATUS_FREQ = 0x03c0 # macro -PCI_X_SSTATUS_VERS = 0x3000 # macro -PCI_X_SSTATUS_V1 = 0x1000 # macro -PCI_X_SSTATUS_V2 = 0x2000 # macro -PCI_X_SSTATUS_266MHZ = 0x4000 # macro -PCI_X_SSTATUS_533MHZ = 0x8000 # macro -PCI_X_BRIDGE_STATUS = 4 # macro -PCI_SSVID_VENDOR_ID = 4 # macro -PCI_SSVID_DEVICE_ID = 6 # macro -PCI_EXP_FLAGS = 2 # macro -PCI_EXP_FLAGS_VERS = 0x000f # macro -PCI_EXP_FLAGS_TYPE = 0x00f0 # macro -PCI_EXP_TYPE_ENDPOINT = 0x0 # macro -PCI_EXP_TYPE_LEG_END = 0x1 # macro -PCI_EXP_TYPE_ROOT_PORT = 0x4 # macro -PCI_EXP_TYPE_UPSTREAM = 0x5 # macro -PCI_EXP_TYPE_DOWNSTREAM = 0x6 # macro -PCI_EXP_TYPE_PCI_BRIDGE = 0x7 # macro -PCI_EXP_TYPE_PCIE_BRIDGE = 0x8 # macro -PCI_EXP_TYPE_RC_END = 0x9 # macro -PCI_EXP_TYPE_RC_EC = 0xa # macro -PCI_EXP_FLAGS_SLOT = 0x0100 # macro -PCI_EXP_FLAGS_IRQ = 0x3e00 # macro -PCI_EXP_DEVCAP = 4 # macro -PCI_EXP_DEVCAP_PAYLOAD = 0x00000007 # macro -PCI_EXP_DEVCAP_PHANTOM = 0x00000018 # macro -PCI_EXP_DEVCAP_EXT_TAG = 0x00000020 # macro -PCI_EXP_DEVCAP_L0S = 0x000001c0 # macro -PCI_EXP_DEVCAP_L1 = 0x00000e00 # macro -PCI_EXP_DEVCAP_ATN_BUT = 0x00001000 # macro -PCI_EXP_DEVCAP_ATN_IND = 0x00002000 # macro -PCI_EXP_DEVCAP_PWR_IND = 0x00004000 # macro -PCI_EXP_DEVCAP_RBER = 0x00008000 # macro -PCI_EXP_DEVCAP_PWR_VAL = 0x03fc0000 # macro -PCI_EXP_DEVCAP_PWR_SCL = 0x0c000000 # macro -PCI_EXP_DEVCAP_FLR = 0x10000000 # macro -PCI_EXP_DEVCTL = 8 # macro -PCI_EXP_DEVCTL_CERE = 0x0001 # macro -PCI_EXP_DEVCTL_NFERE = 0x0002 # macro -PCI_EXP_DEVCTL_FERE = 0x0004 # macro -PCI_EXP_DEVCTL_URRE = 0x0008 # macro -PCI_EXP_DEVCTL_RELAX_EN = 0x0010 # macro -PCI_EXP_DEVCTL_PAYLOAD = 0x00e0 # macro -PCI_EXP_DEVCTL_PAYLOAD_128B = 0x0000 # macro -PCI_EXP_DEVCTL_PAYLOAD_256B = 0x0020 # macro -PCI_EXP_DEVCTL_PAYLOAD_512B = 0x0040 # macro -PCI_EXP_DEVCTL_PAYLOAD_1024B = 0x0060 # macro -PCI_EXP_DEVCTL_PAYLOAD_2048B = 0x0080 # macro -PCI_EXP_DEVCTL_PAYLOAD_4096B = 0x00a0 # macro -PCI_EXP_DEVCTL_EXT_TAG = 0x0100 # macro -PCI_EXP_DEVCTL_PHANTOM = 0x0200 # macro -PCI_EXP_DEVCTL_AUX_PME = 0x0400 # macro -PCI_EXP_DEVCTL_NOSNOOP_EN = 0x0800 # macro -PCI_EXP_DEVCTL_READRQ = 0x7000 # macro -PCI_EXP_DEVCTL_READRQ_128B = 0x0000 # macro -PCI_EXP_DEVCTL_READRQ_256B = 0x1000 # macro -PCI_EXP_DEVCTL_READRQ_512B = 0x2000 # macro -PCI_EXP_DEVCTL_READRQ_1024B = 0x3000 # macro -PCI_EXP_DEVCTL_READRQ_2048B = 0x4000 # macro -PCI_EXP_DEVCTL_READRQ_4096B = 0x5000 # macro -PCI_EXP_DEVCTL_BCR_FLR = 0x8000 # macro -PCI_EXP_DEVSTA = 10 # macro -PCI_EXP_DEVSTA_CED = 0x0001 # macro -PCI_EXP_DEVSTA_NFED = 0x0002 # macro -PCI_EXP_DEVSTA_FED = 0x0004 # macro -PCI_EXP_DEVSTA_URD = 0x0008 # macro -PCI_EXP_DEVSTA_AUXPD = 0x0010 # macro -PCI_EXP_DEVSTA_TRPND = 0x0020 # macro -PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 = 12 # macro -PCI_EXP_LNKCAP = 12 # macro -PCI_EXP_LNKCAP_SLS = 0x0000000f # macro -PCI_EXP_LNKCAP_SLS_2_5GB = 0x00000001 # macro -PCI_EXP_LNKCAP_SLS_5_0GB = 0x00000002 # macro -PCI_EXP_LNKCAP_SLS_8_0GB = 0x00000003 # macro -PCI_EXP_LNKCAP_SLS_16_0GB = 0x00000004 # macro -PCI_EXP_LNKCAP_SLS_32_0GB = 0x00000005 # macro -PCI_EXP_LNKCAP_SLS_64_0GB = 0x00000006 # macro -PCI_EXP_LNKCAP_MLW = 0x000003f0 # macro -PCI_EXP_LNKCAP_ASPMS = 0x00000c00 # macro -PCI_EXP_LNKCAP_ASPM_L0S = 0x00000400 # macro -PCI_EXP_LNKCAP_ASPM_L1 = 0x00000800 # macro -PCI_EXP_LNKCAP_L0SEL = 0x00007000 # macro -PCI_EXP_LNKCAP_L1EL = 0x00038000 # macro -PCI_EXP_LNKCAP_CLKPM = 0x00040000 # macro -PCI_EXP_LNKCAP_SDERC = 0x00080000 # macro -PCI_EXP_LNKCAP_DLLLARC = 0x00100000 # macro -PCI_EXP_LNKCAP_LBNC = 0x00200000 # macro -PCI_EXP_LNKCAP_PN = 0xff000000 # macro -PCI_EXP_LNKCTL = 16 # macro -PCI_EXP_LNKCTL_ASPMC = 0x0003 # macro -PCI_EXP_LNKCTL_ASPM_L0S = 0x0001 # macro -PCI_EXP_LNKCTL_ASPM_L1 = 0x0002 # macro -PCI_EXP_LNKCTL_RCB = 0x0008 # macro -PCI_EXP_LNKCTL_LD = 0x0010 # macro -PCI_EXP_LNKCTL_RL = 0x0020 # macro -PCI_EXP_LNKCTL_CCC = 0x0040 # macro -PCI_EXP_LNKCTL_ES = 0x0080 # macro -PCI_EXP_LNKCTL_CLKREQ_EN = 0x0100 # macro -PCI_EXP_LNKCTL_HAWD = 0x0200 # macro -PCI_EXP_LNKCTL_LBMIE = 0x0400 # macro -PCI_EXP_LNKCTL_LABIE = 0x0800 # macro -PCI_EXP_LNKSTA = 18 # macro -PCI_EXP_LNKSTA_CLS = 0x000f # macro -PCI_EXP_LNKSTA_CLS_2_5GB = 0x0001 # macro -PCI_EXP_LNKSTA_CLS_5_0GB = 0x0002 # macro -PCI_EXP_LNKSTA_CLS_8_0GB = 0x0003 # macro -PCI_EXP_LNKSTA_CLS_16_0GB = 0x0004 # macro -PCI_EXP_LNKSTA_CLS_32_0GB = 0x0005 # macro -PCI_EXP_LNKSTA_CLS_64_0GB = 0x0006 # macro -PCI_EXP_LNKSTA_NLW = 0x03f0 # macro -PCI_EXP_LNKSTA_NLW_X1 = 0x0010 # macro -PCI_EXP_LNKSTA_NLW_X2 = 0x0020 # macro -PCI_EXP_LNKSTA_NLW_X4 = 0x0040 # macro -PCI_EXP_LNKSTA_NLW_X8 = 0x0080 # macro -PCI_EXP_LNKSTA_NLW_SHIFT = 4 # macro -PCI_EXP_LNKSTA_LT = 0x0800 # macro -PCI_EXP_LNKSTA_SLC = 0x1000 # macro -PCI_EXP_LNKSTA_DLLLA = 0x2000 # macro -PCI_EXP_LNKSTA_LBMS = 0x4000 # macro -PCI_EXP_LNKSTA_LABS = 0x8000 # macro -PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 = 20 # macro -PCI_EXP_SLTCAP = 20 # macro -PCI_EXP_SLTCAP_ABP = 0x00000001 # macro -PCI_EXP_SLTCAP_PCP = 0x00000002 # macro -PCI_EXP_SLTCAP_MRLSP = 0x00000004 # macro -PCI_EXP_SLTCAP_AIP = 0x00000008 # macro -PCI_EXP_SLTCAP_PIP = 0x00000010 # macro -PCI_EXP_SLTCAP_HPS = 0x00000020 # macro -PCI_EXP_SLTCAP_HPC = 0x00000040 # macro -PCI_EXP_SLTCAP_SPLV = 0x00007f80 # macro -PCI_EXP_SLTCAP_SPLS = 0x00018000 # macro -PCI_EXP_SLTCAP_EIP = 0x00020000 # macro -PCI_EXP_SLTCAP_NCCS = 0x00040000 # macro -PCI_EXP_SLTCAP_PSN = 0xfff80000 # macro -PCI_EXP_SLTCTL = 24 # macro -PCI_EXP_SLTCTL_ABPE = 0x0001 # macro -PCI_EXP_SLTCTL_PFDE = 0x0002 # macro -PCI_EXP_SLTCTL_MRLSCE = 0x0004 # macro -PCI_EXP_SLTCTL_PDCE = 0x0008 # macro -PCI_EXP_SLTCTL_CCIE = 0x0010 # macro -PCI_EXP_SLTCTL_HPIE = 0x0020 # macro -PCI_EXP_SLTCTL_AIC = 0x00c0 # macro -PCI_EXP_SLTCTL_ATTN_IND_SHIFT = 6 # macro -PCI_EXP_SLTCTL_ATTN_IND_ON = 0x0040 # macro -PCI_EXP_SLTCTL_ATTN_IND_BLINK = 0x0080 # macro -PCI_EXP_SLTCTL_ATTN_IND_OFF = 0x00c0 # macro -PCI_EXP_SLTCTL_PIC = 0x0300 # macro -PCI_EXP_SLTCTL_PWR_IND_ON = 0x0100 # macro -PCI_EXP_SLTCTL_PWR_IND_BLINK = 0x0200 # macro -PCI_EXP_SLTCTL_PWR_IND_OFF = 0x0300 # macro -PCI_EXP_SLTCTL_PCC = 0x0400 # macro -PCI_EXP_SLTCTL_PWR_ON = 0x0000 # macro -PCI_EXP_SLTCTL_PWR_OFF = 0x0400 # macro -PCI_EXP_SLTCTL_EIC = 0x0800 # macro -PCI_EXP_SLTCTL_DLLSCE = 0x1000 # macro -PCI_EXP_SLTCTL_IBPD_DISABLE = 0x4000 # macro -PCI_EXP_SLTSTA = 26 # macro -PCI_EXP_SLTSTA_ABP = 0x0001 # macro -PCI_EXP_SLTSTA_PFD = 0x0002 # macro -PCI_EXP_SLTSTA_MRLSC = 0x0004 # macro -PCI_EXP_SLTSTA_PDC = 0x0008 # macro -PCI_EXP_SLTSTA_CC = 0x0010 # macro -PCI_EXP_SLTSTA_MRLSS = 0x0020 # macro -PCI_EXP_SLTSTA_PDS = 0x0040 # macro -PCI_EXP_SLTSTA_EIS = 0x0080 # macro -PCI_EXP_SLTSTA_DLLSC = 0x0100 # macro -PCI_EXP_RTCTL = 28 # macro -PCI_EXP_RTCTL_SECEE = 0x0001 # macro -PCI_EXP_RTCTL_SENFEE = 0x0002 # macro -PCI_EXP_RTCTL_SEFEE = 0x0004 # macro -PCI_EXP_RTCTL_PMEIE = 0x0008 # macro -PCI_EXP_RTCTL_CRSSVE = 0x0010 # macro -PCI_EXP_RTCAP = 30 # macro -PCI_EXP_RTCAP_CRSVIS = 0x0001 # macro -PCI_EXP_RTSTA = 32 # macro -PCI_EXP_RTSTA_PME = 0x00010000 # macro -PCI_EXP_RTSTA_PENDING = 0x00020000 # macro -PCI_EXP_DEVCAP2 = 36 # macro -PCI_EXP_DEVCAP2_COMP_TMOUT_DIS = 0x00000010 # macro -PCI_EXP_DEVCAP2_ARI = 0x00000020 # macro -PCI_EXP_DEVCAP2_ATOMIC_ROUTE = 0x00000040 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP32 = 0x00000080 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP64 = 0x00000100 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP128 = 0x00000200 # macro -PCI_EXP_DEVCAP2_LTR = 0x00000800 # macro -PCI_EXP_DEVCAP2_OBFF_MASK = 0x000c0000 # macro -PCI_EXP_DEVCAP2_OBFF_MSG = 0x00040000 # macro -PCI_EXP_DEVCAP2_OBFF_WAKE = 0x00080000 # macro -PCI_EXP_DEVCAP2_EE_PREFIX = 0x00200000 # macro -PCI_EXP_DEVCTL2 = 40 # macro -PCI_EXP_DEVCTL2_COMP_TIMEOUT = 0x000f # macro -PCI_EXP_DEVCTL2_COMP_TMOUT_DIS = 0x0010 # macro -PCI_EXP_DEVCTL2_ARI = 0x0020 # macro -PCI_EXP_DEVCTL2_ATOMIC_REQ = 0x0040 # macro -PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK = 0x0080 # macro -PCI_EXP_DEVCTL2_IDO_REQ_EN = 0x0100 # macro -PCI_EXP_DEVCTL2_IDO_CMP_EN = 0x0200 # macro -PCI_EXP_DEVCTL2_LTR_EN = 0x0400 # macro -PCI_EXP_DEVCTL2_OBFF_MSGA_EN = 0x2000 # macro -PCI_EXP_DEVCTL2_OBFF_MSGB_EN = 0x4000 # macro -PCI_EXP_DEVCTL2_OBFF_WAKE_EN = 0x6000 # macro -PCI_EXP_DEVSTA2 = 42 # macro -PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 = 44 # macro -PCI_EXP_LNKCAP2 = 44 # macro -PCI_EXP_LNKCAP2_SLS_2_5GB = 0x00000002 # macro -PCI_EXP_LNKCAP2_SLS_5_0GB = 0x00000004 # macro -PCI_EXP_LNKCAP2_SLS_8_0GB = 0x00000008 # macro -PCI_EXP_LNKCAP2_SLS_16_0GB = 0x00000010 # macro -PCI_EXP_LNKCAP2_SLS_32_0GB = 0x00000020 # macro -PCI_EXP_LNKCAP2_SLS_64_0GB = 0x00000040 # macro -PCI_EXP_LNKCAP2_CROSSLINK = 0x00000100 # macro -PCI_EXP_LNKCTL2 = 48 # macro -PCI_EXP_LNKCTL2_TLS = 0x000f # macro -PCI_EXP_LNKCTL2_TLS_2_5GT = 0x0001 # macro -PCI_EXP_LNKCTL2_TLS_5_0GT = 0x0002 # macro -PCI_EXP_LNKCTL2_TLS_8_0GT = 0x0003 # macro -PCI_EXP_LNKCTL2_TLS_16_0GT = 0x0004 # macro -PCI_EXP_LNKCTL2_TLS_32_0GT = 0x0005 # macro -PCI_EXP_LNKCTL2_TLS_64_0GT = 0x0006 # macro -PCI_EXP_LNKCTL2_ENTER_COMP = 0x0010 # macro -PCI_EXP_LNKCTL2_TX_MARGIN = 0x0380 # macro -PCI_EXP_LNKCTL2_HASD = 0x0020 # macro -PCI_EXP_LNKSTA2 = 50 # macro -PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 = 52 # macro -PCI_EXP_SLTCAP2 = 52 # macro -PCI_EXP_SLTCAP2_IBPD = 0x00000001 # macro -PCI_EXP_SLTCTL2 = 56 # macro -PCI_EXP_SLTSTA2 = 58 # macro -def PCI_EXT_CAP_ID(header): # macro - return (header&0x0000ffff) -def PCI_EXT_CAP_VER(header): # macro - return ((header>>16)&0xf) -def PCI_EXT_CAP_NEXT(header): # macro - return ((header>>20)&0xffc) -PCI_EXT_CAP_ID_ERR = 0x01 # macro -PCI_EXT_CAP_ID_VC = 0x02 # macro -PCI_EXT_CAP_ID_DSN = 0x03 # macro -PCI_EXT_CAP_ID_PWR = 0x04 # macro -PCI_EXT_CAP_ID_RCLD = 0x05 # macro -PCI_EXT_CAP_ID_RCILC = 0x06 # macro -PCI_EXT_CAP_ID_RCEC = 0x07 # macro -PCI_EXT_CAP_ID_MFVC = 0x08 # macro -PCI_EXT_CAP_ID_VC9 = 0x09 # macro -PCI_EXT_CAP_ID_RCRB = 0x0A # macro -PCI_EXT_CAP_ID_VNDR = 0x0B # macro -PCI_EXT_CAP_ID_CAC = 0x0C # macro -PCI_EXT_CAP_ID_ACS = 0x0D # macro -PCI_EXT_CAP_ID_ARI = 0x0E # macro -PCI_EXT_CAP_ID_ATS = 0x0F # macro -PCI_EXT_CAP_ID_SRIOV = 0x10 # macro -PCI_EXT_CAP_ID_MRIOV = 0x11 # macro -PCI_EXT_CAP_ID_MCAST = 0x12 # macro -PCI_EXT_CAP_ID_PRI = 0x13 # macro -PCI_EXT_CAP_ID_AMD_XXX = 0x14 # macro -PCI_EXT_CAP_ID_REBAR = 0x15 # macro -PCI_EXT_CAP_ID_DPA = 0x16 # macro -PCI_EXT_CAP_ID_TPH = 0x17 # macro -PCI_EXT_CAP_ID_LTR = 0x18 # macro -PCI_EXT_CAP_ID_SECPCI = 0x19 # macro -PCI_EXT_CAP_ID_PMUX = 0x1A # macro -PCI_EXT_CAP_ID_PASID = 0x1B # macro -PCI_EXT_CAP_ID_DPC = 0x1D # macro -PCI_EXT_CAP_ID_L1SS = 0x1E # macro -PCI_EXT_CAP_ID_PTM = 0x1F # macro -PCI_EXT_CAP_ID_DVSEC = 0x23 # macro -PCI_EXT_CAP_ID_DLF = 0x25 # macro -PCI_EXT_CAP_ID_PL_16GT = 0x26 # macro -PCI_EXT_CAP_ID_MAX = 0x26 # macro -PCI_EXT_CAP_DSN_SIZEOF = 12 # macro -PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF = 40 # macro -PCI_ERR_UNCOR_STATUS = 4 # macro -PCI_ERR_UNC_UND = 0x00000001 # macro -PCI_ERR_UNC_DLP = 0x00000010 # macro -PCI_ERR_UNC_SURPDN = 0x00000020 # macro -PCI_ERR_UNC_POISON_TLP = 0x00001000 # macro -PCI_ERR_UNC_FCP = 0x00002000 # macro -PCI_ERR_UNC_COMP_TIME = 0x00004000 # macro -PCI_ERR_UNC_COMP_ABORT = 0x00008000 # macro -PCI_ERR_UNC_UNX_COMP = 0x00010000 # macro -PCI_ERR_UNC_RX_OVER = 0x00020000 # macro -PCI_ERR_UNC_MALF_TLP = 0x00040000 # macro -PCI_ERR_UNC_ECRC = 0x00080000 # macro -PCI_ERR_UNC_UNSUP = 0x00100000 # macro -PCI_ERR_UNC_ACSV = 0x00200000 # macro -PCI_ERR_UNC_INTN = 0x00400000 # macro -PCI_ERR_UNC_MCBTLP = 0x00800000 # macro -PCI_ERR_UNC_ATOMEG = 0x01000000 # macro -PCI_ERR_UNC_TLPPRE = 0x02000000 # macro -PCI_ERR_UNCOR_MASK = 8 # macro -PCI_ERR_UNCOR_SEVER = 12 # macro -PCI_ERR_COR_STATUS = 16 # macro -PCI_ERR_COR_RCVR = 0x00000001 # macro -PCI_ERR_COR_BAD_TLP = 0x00000040 # macro -PCI_ERR_COR_BAD_DLLP = 0x00000080 # macro -PCI_ERR_COR_REP_ROLL = 0x00000100 # macro -PCI_ERR_COR_REP_TIMER = 0x00001000 # macro -PCI_ERR_COR_ADV_NFAT = 0x00002000 # macro -PCI_ERR_COR_INTERNAL = 0x00004000 # macro -PCI_ERR_COR_LOG_OVER = 0x00008000 # macro -PCI_ERR_COR_MASK = 20 # macro -PCI_ERR_CAP = 24 # macro -def PCI_ERR_CAP_FEP(x): # macro - return ((x)&31) -PCI_ERR_CAP_ECRC_GENC = 0x00000020 # macro -PCI_ERR_CAP_ECRC_GENE = 0x00000040 # macro -PCI_ERR_CAP_ECRC_CHKC = 0x00000080 # macro -PCI_ERR_CAP_ECRC_CHKE = 0x00000100 # macro -PCI_ERR_HEADER_LOG = 28 # macro -PCI_ERR_ROOT_COMMAND = 44 # macro -PCI_ERR_ROOT_CMD_COR_EN = 0x00000001 # macro -PCI_ERR_ROOT_CMD_NONFATAL_EN = 0x00000002 # macro -PCI_ERR_ROOT_CMD_FATAL_EN = 0x00000004 # macro -PCI_ERR_ROOT_STATUS = 48 # macro -PCI_ERR_ROOT_COR_RCV = 0x00000001 # macro -PCI_ERR_ROOT_MULTI_COR_RCV = 0x00000002 # macro -PCI_ERR_ROOT_UNCOR_RCV = 0x00000004 # macro -PCI_ERR_ROOT_MULTI_UNCOR_RCV = 0x00000008 # macro -PCI_ERR_ROOT_FIRST_FATAL = 0x00000010 # macro -PCI_ERR_ROOT_NONFATAL_RCV = 0x00000020 # macro -PCI_ERR_ROOT_FATAL_RCV = 0x00000040 # macro -PCI_ERR_ROOT_AER_IRQ = 0xf8000000 # macro -PCI_ERR_ROOT_ERR_SRC = 52 # macro -PCI_VC_PORT_CAP1 = 4 # macro -PCI_VC_CAP1_EVCC = 0x00000007 # macro -PCI_VC_CAP1_LPEVCC = 0x00000070 # macro -PCI_VC_CAP1_ARB_SIZE = 0x00000c00 # macro -PCI_VC_PORT_CAP2 = 8 # macro -PCI_VC_CAP2_32_PHASE = 0x00000002 # macro -PCI_VC_CAP2_64_PHASE = 0x00000004 # macro -PCI_VC_CAP2_128_PHASE = 0x00000008 # macro -PCI_VC_CAP2_ARB_OFF = 0xff000000 # macro -PCI_VC_PORT_CTRL = 12 # macro -PCI_VC_PORT_CTRL_LOAD_TABLE = 0x00000001 # macro -PCI_VC_PORT_STATUS = 14 # macro -PCI_VC_PORT_STATUS_TABLE = 0x00000001 # macro -PCI_VC_RES_CAP = 16 # macro -PCI_VC_RES_CAP_32_PHASE = 0x00000002 # macro -PCI_VC_RES_CAP_64_PHASE = 0x00000004 # macro -PCI_VC_RES_CAP_128_PHASE = 0x00000008 # macro -PCI_VC_RES_CAP_128_PHASE_TB = 0x00000010 # macro -PCI_VC_RES_CAP_256_PHASE = 0x00000020 # macro -PCI_VC_RES_CAP_ARB_OFF = 0xff000000 # macro -PCI_VC_RES_CTRL = 20 # macro -PCI_VC_RES_CTRL_LOAD_TABLE = 0x00010000 # macro -PCI_VC_RES_CTRL_ARB_SELECT = 0x000e0000 # macro -PCI_VC_RES_CTRL_ID = 0x07000000 # macro -PCI_VC_RES_CTRL_ENABLE = 0x80000000 # macro -PCI_VC_RES_STATUS = 26 # macro -PCI_VC_RES_STATUS_TABLE = 0x00000001 # macro -PCI_VC_RES_STATUS_NEGO = 0x00000002 # macro -PCI_CAP_VC_BASE_SIZEOF = 0x10 # macro -PCI_CAP_VC_PER_VC_SIZEOF = 0x0C # macro -PCI_PWR_DSR = 4 # macro -PCI_PWR_DATA = 8 # macro -def PCI_PWR_DATA_BASE(x): # macro - return ((x)&0xff) -def PCI_PWR_DATA_SCALE(x): # macro - return (((x)>>8)&3) -def PCI_PWR_DATA_PM_SUB(x): # macro - return (((x)>>10)&7) -def PCI_PWR_DATA_PM_STATE(x): # macro - return (((x)>>13)&3) -def PCI_PWR_DATA_TYPE(x): # macro - return (((x)>>15)&7) -def PCI_PWR_DATA_RAIL(x): # macro - return (((x)>>18)&7) -PCI_PWR_CAP = 12 # macro -def PCI_PWR_CAP_BUDGET(x): # macro - return ((x)&1) -PCI_EXT_CAP_PWR_SIZEOF = 16 # macro -PCI_RCEC_RCIEP_BITMAP = 4 # macro -PCI_RCEC_BUSN = 8 # macro -PCI_RCEC_BUSN_REG_VER = 0x02 # macro -def PCI_RCEC_BUSN_NEXT(x): # macro - return (((x)>>8)&0xff) -def PCI_RCEC_BUSN_LAST(x): # macro - return (((x)>>16)&0xff) -PCI_VNDR_HEADER = 4 # macro -def PCI_VNDR_HEADER_ID(x): # macro - return ((x)&0xffff) -def PCI_VNDR_HEADER_REV(x): # macro - return (((x)>>16)&0xf) -def PCI_VNDR_HEADER_LEN(x): # macro - return (((x)>>20)&0xfff) -HT_3BIT_CAP_MASK = 0xE0 # macro -HT_CAPTYPE_SLAVE = 0x00 # macro -HT_CAPTYPE_HOST = 0x20 # macro -HT_5BIT_CAP_MASK = 0xF8 # macro -HT_CAPTYPE_IRQ = 0x80 # macro -HT_CAPTYPE_REMAPPING_40 = 0xA0 # macro -HT_CAPTYPE_REMAPPING_64 = 0xA2 # macro -HT_CAPTYPE_UNITID_CLUMP = 0x90 # macro -HT_CAPTYPE_EXTCONF = 0x98 # macro -HT_CAPTYPE_MSI_MAPPING = 0xA8 # macro -HT_MSI_FLAGS = 0x02 # macro -HT_MSI_FLAGS_ENABLE = 0x1 # macro -HT_MSI_FLAGS_FIXED = 0x2 # macro -HT_MSI_FIXED_ADDR = 0x00000000FEE00000 # macro -HT_MSI_ADDR_LO = 0x04 # macro -HT_MSI_ADDR_LO_MASK = 0xFFF00000 # macro -HT_MSI_ADDR_HI = 0x08 # macro -HT_CAPTYPE_DIRECT_ROUTE = 0xB0 # macro -HT_CAPTYPE_VCSET = 0xB8 # macro -HT_CAPTYPE_ERROR_RETRY = 0xC0 # macro -HT_CAPTYPE_GEN3 = 0xD0 # macro -HT_CAPTYPE_PM = 0xE0 # macro -HT_CAP_SIZEOF_LONG = 28 # macro -HT_CAP_SIZEOF_SHORT = 24 # macro -PCI_ARI_CAP = 0x04 # macro -PCI_ARI_CAP_MFVC = 0x0001 # macro -PCI_ARI_CAP_ACS = 0x0002 # macro -def PCI_ARI_CAP_NFN(x): # macro - return (((x)>>8)&0xff) -PCI_ARI_CTRL = 0x06 # macro -PCI_ARI_CTRL_MFVC = 0x0001 # macro -PCI_ARI_CTRL_ACS = 0x0002 # macro -def PCI_ARI_CTRL_FG(x): # macro - return (((x)>>4)&7) -PCI_EXT_CAP_ARI_SIZEOF = 8 # macro -PCI_ATS_CAP = 0x04 # macro -def PCI_ATS_CAP_QDEP(x): # macro - return ((x)&0x1f) -PCI_ATS_MAX_QDEP = 32 # macro -PCI_ATS_CAP_PAGE_ALIGNED = 0x0020 # macro -PCI_ATS_CTRL = 0x06 # macro -PCI_ATS_CTRL_ENABLE = 0x8000 # macro -def PCI_ATS_CTRL_STU(x): # macro - return ((x)&0x1f) -PCI_ATS_MIN_STU = 12 # macro -PCI_EXT_CAP_ATS_SIZEOF = 8 # macro -PCI_PRI_CTRL = 0x04 # macro -PCI_PRI_CTRL_ENABLE = 0x0001 # macro -PCI_PRI_CTRL_RESET = 0x0002 # macro -PCI_PRI_STATUS = 0x06 # macro -PCI_PRI_STATUS_RF = 0x0001 # macro -PCI_PRI_STATUS_UPRGI = 0x0002 # macro -PCI_PRI_STATUS_STOPPED = 0x0100 # macro -PCI_PRI_STATUS_PASID = 0x8000 # macro -PCI_PRI_MAX_REQ = 0x08 # macro -PCI_PRI_ALLOC_REQ = 0x0c # macro -PCI_EXT_CAP_PRI_SIZEOF = 16 # macro -PCI_PASID_CAP = 0x04 # macro -PCI_PASID_CAP_EXEC = 0x02 # macro -PCI_PASID_CAP_PRIV = 0x04 # macro -PCI_PASID_CTRL = 0x06 # macro -PCI_PASID_CTRL_ENABLE = 0x01 # macro -PCI_PASID_CTRL_EXEC = 0x02 # macro -PCI_PASID_CTRL_PRIV = 0x04 # macro -PCI_EXT_CAP_PASID_SIZEOF = 8 # macro -PCI_SRIOV_CAP = 0x04 # macro -PCI_SRIOV_CAP_VFM = 0x00000001 # macro -def PCI_SRIOV_CAP_INTR(x): # macro - return ((x)>>21) -PCI_SRIOV_CTRL = 0x08 # macro -PCI_SRIOV_CTRL_VFE = 0x0001 # macro -PCI_SRIOV_CTRL_VFM = 0x0002 # macro -PCI_SRIOV_CTRL_INTR = 0x0004 # macro -PCI_SRIOV_CTRL_MSE = 0x0008 # macro -PCI_SRIOV_CTRL_ARI = 0x0010 # macro -PCI_SRIOV_STATUS = 0x0a # macro -PCI_SRIOV_STATUS_VFM = 0x0001 # macro -PCI_SRIOV_INITIAL_VF = 0x0c # macro -PCI_SRIOV_TOTAL_VF = 0x0e # macro -PCI_SRIOV_NUM_VF = 0x10 # macro -PCI_SRIOV_FUNC_LINK = 0x12 # macro -PCI_SRIOV_VF_OFFSET = 0x14 # macro -PCI_SRIOV_VF_STRIDE = 0x16 # macro -PCI_SRIOV_VF_DID = 0x1a # macro -PCI_SRIOV_SUP_PGSIZE = 0x1c # macro -PCI_SRIOV_SYS_PGSIZE = 0x20 # macro -PCI_SRIOV_BAR = 0x24 # macro -PCI_SRIOV_NUM_BARS = 6 # macro -PCI_SRIOV_VFM = 0x3c # macro -def PCI_SRIOV_VFM_BIR(x): # macro - return ((x)&7) -def PCI_SRIOV_VFM_OFFSET(x): # macro - return ((x)&~7) -PCI_SRIOV_VFM_UA = 0x0 # macro -PCI_SRIOV_VFM_MI = 0x1 # macro -PCI_SRIOV_VFM_MO = 0x2 # macro -PCI_SRIOV_VFM_AV = 0x3 # macro -PCI_EXT_CAP_SRIOV_SIZEOF = 64 # macro -PCI_LTR_MAX_SNOOP_LAT = 0x4 # macro -PCI_LTR_MAX_NOSNOOP_LAT = 0x6 # macro -PCI_LTR_VALUE_MASK = 0x000003ff # macro -PCI_LTR_SCALE_MASK = 0x00001c00 # macro -PCI_LTR_SCALE_SHIFT = 10 # macro -PCI_EXT_CAP_LTR_SIZEOF = 8 # macro -PCI_ACS_CAP = 0x04 # macro -PCI_ACS_SV = 0x0001 # macro -PCI_ACS_TB = 0x0002 # macro -PCI_ACS_RR = 0x0004 # macro -PCI_ACS_CR = 0x0008 # macro -PCI_ACS_UF = 0x0010 # macro -PCI_ACS_EC = 0x0020 # macro -PCI_ACS_DT = 0x0040 # macro -PCI_ACS_EGRESS_BITS = 0x05 # macro -PCI_ACS_CTRL = 0x06 # macro -PCI_ACS_EGRESS_CTL_V = 0x08 # macro -PCI_VSEC_HDR = 4 # macro -PCI_VSEC_HDR_LEN_SHIFT = 20 # macro -PCI_SATA_REGS = 4 # macro -PCI_SATA_REGS_MASK = 0xF # macro -PCI_SATA_REGS_INLINE = 0xF # macro -PCI_SATA_SIZEOF_SHORT = 8 # macro -PCI_SATA_SIZEOF_LONG = 16 # macro -PCI_REBAR_CAP = 4 # macro -PCI_REBAR_CAP_SIZES = 0x00FFFFF0 # macro -PCI_REBAR_CTRL = 8 # macro -PCI_REBAR_CTRL_BAR_IDX = 0x00000007 # macro -PCI_REBAR_CTRL_NBAR_MASK = 0x000000E0 # macro -PCI_REBAR_CTRL_NBAR_SHIFT = 5 # macro -PCI_REBAR_CTRL_BAR_SIZE = 0x00001F00 # macro -PCI_REBAR_CTRL_BAR_SHIFT = 8 # macro -PCI_DPA_CAP = 4 # macro -PCI_DPA_CAP_SUBSTATE_MASK = 0x1F # macro -PCI_DPA_BASE_SIZEOF = 16 # macro -PCI_TPH_CAP = 4 # macro -PCI_TPH_CAP_LOC_MASK = 0x600 # macro -PCI_TPH_LOC_NONE = 0x000 # macro -PCI_TPH_LOC_CAP = 0x200 # macro -PCI_TPH_LOC_MSIX = 0x400 # macro -PCI_TPH_CAP_ST_MASK = 0x07FF0000 # macro -PCI_TPH_CAP_ST_SHIFT = 16 # macro -PCI_TPH_BASE_SIZEOF = 12 # macro -PCI_EXP_DPC_CAP = 4 # macro -PCI_EXP_DPC_IRQ = 0x001F # macro -PCI_EXP_DPC_CAP_RP_EXT = 0x0020 # macro -PCI_EXP_DPC_CAP_POISONED_TLP = 0x0040 # macro -PCI_EXP_DPC_CAP_SW_TRIGGER = 0x0080 # macro -PCI_EXP_DPC_RP_PIO_LOG_SIZE = 0x0F00 # macro -PCI_EXP_DPC_CAP_DL_ACTIVE = 0x1000 # macro -PCI_EXP_DPC_CTL = 6 # macro -PCI_EXP_DPC_CTL_EN_FATAL = 0x0001 # macro -PCI_EXP_DPC_CTL_EN_NONFATAL = 0x0002 # macro -PCI_EXP_DPC_CTL_INT_EN = 0x0008 # macro -PCI_EXP_DPC_STATUS = 8 # macro -PCI_EXP_DPC_STATUS_TRIGGER = 0x0001 # macro -PCI_EXP_DPC_STATUS_TRIGGER_RSN = 0x0006 # macro -PCI_EXP_DPC_STATUS_INTERRUPT = 0x0008 # macro -PCI_EXP_DPC_RP_BUSY = 0x0010 # macro -PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT = 0x0060 # macro -PCI_EXP_DPC_SOURCE_ID = 10 # macro -PCI_EXP_DPC_RP_PIO_STATUS = 0x0C # macro -PCI_EXP_DPC_RP_PIO_MASK = 0x10 # macro -PCI_EXP_DPC_RP_PIO_SEVERITY = 0x14 # macro -PCI_EXP_DPC_RP_PIO_SYSERROR = 0x18 # macro -PCI_EXP_DPC_RP_PIO_EXCEPTION = 0x1C # macro -PCI_EXP_DPC_RP_PIO_HEADER_LOG = 0x20 # macro -PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG = 0x30 # macro -PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG = 0x34 # macro -PCI_PTM_CAP = 0x04 # macro -PCI_PTM_CAP_REQ = 0x00000001 # macro -PCI_PTM_CAP_ROOT = 0x00000004 # macro -PCI_PTM_GRANULARITY_MASK = 0x0000FF00 # macro -PCI_PTM_CTRL = 0x08 # macro -PCI_PTM_CTRL_ENABLE = 0x00000001 # macro -PCI_PTM_CTRL_ROOT = 0x00000002 # macro -PCI_L1SS_CAP = 0x04 # macro -PCI_L1SS_CAP_PCIPM_L1_2 = 0x00000001 # macro -PCI_L1SS_CAP_PCIPM_L1_1 = 0x00000002 # macro -PCI_L1SS_CAP_ASPM_L1_2 = 0x00000004 # macro -PCI_L1SS_CAP_ASPM_L1_1 = 0x00000008 # macro -PCI_L1SS_CAP_L1_PM_SS = 0x00000010 # macro -PCI_L1SS_CAP_CM_RESTORE_TIME = 0x0000ff00 # macro -PCI_L1SS_CAP_P_PWR_ON_SCALE = 0x00030000 # macro -PCI_L1SS_CAP_P_PWR_ON_VALUE = 0x00f80000 # macro -PCI_L1SS_CTL1 = 0x08 # macro -PCI_L1SS_CTL1_PCIPM_L1_2 = 0x00000001 # macro -PCI_L1SS_CTL1_PCIPM_L1_1 = 0x00000002 # macro -PCI_L1SS_CTL1_ASPM_L1_2 = 0x00000004 # macro -PCI_L1SS_CTL1_ASPM_L1_1 = 0x00000008 # macro -PCI_L1SS_CTL1_L1_2_MASK = 0x00000005 # macro -PCI_L1SS_CTL1_L1SS_MASK = 0x0000000f # macro -PCI_L1SS_CTL1_CM_RESTORE_TIME = 0x0000ff00 # macro -PCI_L1SS_CTL1_LTR_L12_TH_VALUE = 0x03ff0000 # macro -PCI_L1SS_CTL1_LTR_L12_TH_SCALE = 0xe0000000 # macro -PCI_L1SS_CTL2 = 0x0c # macro -PCI_DVSEC_HEADER1 = 0x4 # macro -PCI_DVSEC_HEADER2 = 0x8 # macro -PCI_DLF_CAP = 0x04 # macro -PCI_DLF_EXCHANGE_ENABLE = 0x80000000 # macro -PCI_PL_16GT_LE_CTRL = 0x20 # macro -PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK = 0x0000000F # macro -PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK = 0x000000F0 # macro -PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT = 4 # macro -__all__ = \ - ['HT_3BIT_CAP_MASK', 'HT_5BIT_CAP_MASK', - 'HT_CAPTYPE_DIRECT_ROUTE', 'HT_CAPTYPE_ERROR_RETRY', - 'HT_CAPTYPE_EXTCONF', 'HT_CAPTYPE_GEN3', 'HT_CAPTYPE_HOST', - 'HT_CAPTYPE_IRQ', 'HT_CAPTYPE_MSI_MAPPING', 'HT_CAPTYPE_PM', - 'HT_CAPTYPE_REMAPPING_40', 'HT_CAPTYPE_REMAPPING_64', - 'HT_CAPTYPE_SLAVE', 'HT_CAPTYPE_UNITID_CLUMP', 'HT_CAPTYPE_VCSET', - 'HT_CAP_SIZEOF_LONG', 'HT_CAP_SIZEOF_SHORT', 'HT_MSI_ADDR_HI', - 'HT_MSI_ADDR_LO', 'HT_MSI_ADDR_LO_MASK', 'HT_MSI_FIXED_ADDR', - 'HT_MSI_FLAGS', 'HT_MSI_FLAGS_ENABLE', 'HT_MSI_FLAGS_FIXED', - 'LINUX_PCI_REGS_H', 'PCI_ACS_CAP', 'PCI_ACS_CR', 'PCI_ACS_CTRL', - 'PCI_ACS_DT', 'PCI_ACS_EC', 'PCI_ACS_EGRESS_BITS', - 'PCI_ACS_EGRESS_CTL_V', 'PCI_ACS_RR', 'PCI_ACS_SV', 'PCI_ACS_TB', - 'PCI_ACS_UF', 'PCI_AF_CAP', 'PCI_AF_CAP_FLR', 'PCI_AF_CAP_TP', - 'PCI_AF_CTRL', 'PCI_AF_CTRL_FLR', 'PCI_AF_LENGTH', - 'PCI_AF_STATUS', 'PCI_AF_STATUS_TP', 'PCI_AGP_COMMAND', - 'PCI_AGP_COMMAND_64BIT', 'PCI_AGP_COMMAND_AGP', - 'PCI_AGP_COMMAND_FW', 'PCI_AGP_COMMAND_RATE1', - 'PCI_AGP_COMMAND_RATE2', 'PCI_AGP_COMMAND_RATE4', - 'PCI_AGP_COMMAND_RQ_MASK', 'PCI_AGP_COMMAND_SBA', 'PCI_AGP_RFU', - 'PCI_AGP_SIZEOF', 'PCI_AGP_STATUS', 'PCI_AGP_STATUS_64BIT', - 'PCI_AGP_STATUS_FW', 'PCI_AGP_STATUS_RATE1', - 'PCI_AGP_STATUS_RATE2', 'PCI_AGP_STATUS_RATE4', - 'PCI_AGP_STATUS_RQ_MASK', 'PCI_AGP_STATUS_SBA', 'PCI_AGP_VERSION', - 'PCI_ARI_CAP', 'PCI_ARI_CAP_ACS', 'PCI_ARI_CAP_MFVC', - 'PCI_ARI_CTRL', 'PCI_ARI_CTRL_ACS', 'PCI_ARI_CTRL_MFVC', - 'PCI_ATS_CAP', 'PCI_ATS_CAP_PAGE_ALIGNED', 'PCI_ATS_CTRL', - 'PCI_ATS_CTRL_ENABLE', 'PCI_ATS_MAX_QDEP', 'PCI_ATS_MIN_STU', - 'PCI_BASE_ADDRESS_0', 'PCI_BASE_ADDRESS_1', 'PCI_BASE_ADDRESS_2', - 'PCI_BASE_ADDRESS_3', 'PCI_BASE_ADDRESS_4', 'PCI_BASE_ADDRESS_5', - 'PCI_BASE_ADDRESS_IO_MASK', 'PCI_BASE_ADDRESS_MEM_MASK', - 'PCI_BASE_ADDRESS_MEM_PREFETCH', 'PCI_BASE_ADDRESS_MEM_TYPE_1M', - 'PCI_BASE_ADDRESS_MEM_TYPE_32', 'PCI_BASE_ADDRESS_MEM_TYPE_64', - 'PCI_BASE_ADDRESS_MEM_TYPE_MASK', 'PCI_BASE_ADDRESS_SPACE', - 'PCI_BASE_ADDRESS_SPACE_IO', 'PCI_BASE_ADDRESS_SPACE_MEMORY', - 'PCI_BIST', 'PCI_BIST_CAPABLE', 'PCI_BIST_CODE_MASK', - 'PCI_BIST_START', 'PCI_BRIDGE_CONTROL', - 'PCI_BRIDGE_CTL_BUS_RESET', 'PCI_BRIDGE_CTL_FAST_BACK', - 'PCI_BRIDGE_CTL_ISA', 'PCI_BRIDGE_CTL_MASTER_ABORT', - 'PCI_BRIDGE_CTL_PARITY', 'PCI_BRIDGE_CTL_SERR', - 'PCI_BRIDGE_CTL_VGA', 'PCI_CACHE_LINE_SIZE', - 'PCI_CAPABILITY_LIST', 'PCI_CAP_AF_SIZEOF', - 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V1', - 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V2', - 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1', - 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2', 'PCI_CAP_FLAGS', - 'PCI_CAP_ID_AF', 'PCI_CAP_ID_AGP', 'PCI_CAP_ID_AGP3', - 'PCI_CAP_ID_CCRC', 'PCI_CAP_ID_CHSWP', 'PCI_CAP_ID_DBG', - 'PCI_CAP_ID_EA', 'PCI_CAP_ID_EXP', 'PCI_CAP_ID_HT', - 'PCI_CAP_ID_MAX', 'PCI_CAP_ID_MSI', 'PCI_CAP_ID_MSIX', - 'PCI_CAP_ID_PCIX', 'PCI_CAP_ID_PM', 'PCI_CAP_ID_SATA', - 'PCI_CAP_ID_SECDEV', 'PCI_CAP_ID_SHPC', 'PCI_CAP_ID_SLOTID', - 'PCI_CAP_ID_SSVID', 'PCI_CAP_ID_VNDR', 'PCI_CAP_ID_VPD', - 'PCI_CAP_LIST_ID', 'PCI_CAP_LIST_NEXT', 'PCI_CAP_MSIX_SIZEOF', - 'PCI_CAP_PCIX_SIZEOF_V0', 'PCI_CAP_PCIX_SIZEOF_V1', - 'PCI_CAP_PCIX_SIZEOF_V2', 'PCI_CAP_SIZEOF', - 'PCI_CAP_VC_BASE_SIZEOF', 'PCI_CAP_VC_PER_VC_SIZEOF', - 'PCI_CAP_VPD_SIZEOF', 'PCI_CARDBUS_CIS', 'PCI_CB_BRIDGE_CONTROL', - 'PCI_CB_BRIDGE_CTL_16BIT_INT', 'PCI_CB_BRIDGE_CTL_CB_RESET', - 'PCI_CB_BRIDGE_CTL_ISA', 'PCI_CB_BRIDGE_CTL_MASTER_ABORT', - 'PCI_CB_BRIDGE_CTL_PARITY', 'PCI_CB_BRIDGE_CTL_POST_WRITES', - 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM0', - 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM1', 'PCI_CB_BRIDGE_CTL_SERR', - 'PCI_CB_BRIDGE_CTL_VGA', 'PCI_CB_CAPABILITY_LIST', - 'PCI_CB_CARD_BUS', 'PCI_CB_IO_BASE_0', 'PCI_CB_IO_BASE_0_HI', - 'PCI_CB_IO_BASE_1', 'PCI_CB_IO_BASE_1_HI', 'PCI_CB_IO_LIMIT_0', - 'PCI_CB_IO_LIMIT_0_HI', 'PCI_CB_IO_LIMIT_1', - 'PCI_CB_IO_LIMIT_1_HI', 'PCI_CB_IO_RANGE_MASK', - 'PCI_CB_LATENCY_TIMER', 'PCI_CB_LEGACY_MODE_BASE', - 'PCI_CB_MEMORY_BASE_0', 'PCI_CB_MEMORY_BASE_1', - 'PCI_CB_MEMORY_LIMIT_0', 'PCI_CB_MEMORY_LIMIT_1', - 'PCI_CB_PRIMARY_BUS', 'PCI_CB_SEC_STATUS', - 'PCI_CB_SUBORDINATE_BUS', 'PCI_CB_SUBSYSTEM_ID', - 'PCI_CB_SUBSYSTEM_VENDOR_ID', 'PCI_CFG_SPACE_EXP_SIZE', - 'PCI_CFG_SPACE_SIZE', 'PCI_CHSWP_CSR', 'PCI_CHSWP_DHA', - 'PCI_CHSWP_EIM', 'PCI_CHSWP_EXT', 'PCI_CHSWP_INS', - 'PCI_CHSWP_LOO', 'PCI_CHSWP_PI', 'PCI_CHSWP_PIE', - 'PCI_CLASS_DEVICE', 'PCI_CLASS_PROG', 'PCI_CLASS_REVISION', - 'PCI_COMMAND', 'PCI_COMMAND_FAST_BACK', - 'PCI_COMMAND_INTX_DISABLE', 'PCI_COMMAND_INVALIDATE', - 'PCI_COMMAND_IO', 'PCI_COMMAND_MASTER', 'PCI_COMMAND_MEMORY', - 'PCI_COMMAND_PARITY', 'PCI_COMMAND_SERR', 'PCI_COMMAND_SPECIAL', - 'PCI_COMMAND_VGA_PALETTE', 'PCI_COMMAND_WAIT', 'PCI_DEVICE_ID', - 'PCI_DLF_CAP', 'PCI_DLF_EXCHANGE_ENABLE', 'PCI_DPA_BASE_SIZEOF', - 'PCI_DPA_CAP', 'PCI_DPA_CAP_SUBSTATE_MASK', 'PCI_DVSEC_HEADER1', - 'PCI_DVSEC_HEADER2', 'PCI_EA_BASE', 'PCI_EA_BEI', - 'PCI_EA_BEI_BAR0', 'PCI_EA_BEI_BAR5', 'PCI_EA_BEI_BRIDGE', - 'PCI_EA_BEI_ENI', 'PCI_EA_BEI_RESERVED', 'PCI_EA_BEI_ROM', - 'PCI_EA_BEI_VF_BAR0', 'PCI_EA_BEI_VF_BAR5', 'PCI_EA_ENABLE', - 'PCI_EA_ES', 'PCI_EA_FIELD_MASK', 'PCI_EA_FIRST_ENT', - 'PCI_EA_FIRST_ENT_BRIDGE', 'PCI_EA_IS_64', 'PCI_EA_MAX_OFFSET', - 'PCI_EA_NUM_ENT', 'PCI_EA_NUM_ENT_MASK', 'PCI_EA_PP', - 'PCI_EA_P_BRIDGE_IO', 'PCI_EA_P_BRIDGE_MEM', - 'PCI_EA_P_BRIDGE_MEM_PREFETCH', 'PCI_EA_P_IO', - 'PCI_EA_P_IO_RESERVED', 'PCI_EA_P_MEM', 'PCI_EA_P_MEM_PREFETCH', - 'PCI_EA_P_MEM_RESERVED', 'PCI_EA_P_UNAVAILABLE', - 'PCI_EA_P_VF_MEM', 'PCI_EA_P_VF_MEM_PREFETCH', - 'PCI_EA_SEC_BUS_MASK', 'PCI_EA_SP', 'PCI_EA_SUB_BUS_MASK', - 'PCI_EA_SUB_BUS_SHIFT', 'PCI_EA_WRITABLE', 'PCI_ERR_CAP', - 'PCI_ERR_CAP_ECRC_CHKC', 'PCI_ERR_CAP_ECRC_CHKE', - 'PCI_ERR_CAP_ECRC_GENC', 'PCI_ERR_CAP_ECRC_GENE', - 'PCI_ERR_COR_ADV_NFAT', 'PCI_ERR_COR_BAD_DLLP', - 'PCI_ERR_COR_BAD_TLP', 'PCI_ERR_COR_INTERNAL', - 'PCI_ERR_COR_LOG_OVER', 'PCI_ERR_COR_MASK', 'PCI_ERR_COR_RCVR', - 'PCI_ERR_COR_REP_ROLL', 'PCI_ERR_COR_REP_TIMER', - 'PCI_ERR_COR_STATUS', 'PCI_ERR_HEADER_LOG', - 'PCI_ERR_ROOT_AER_IRQ', 'PCI_ERR_ROOT_CMD_COR_EN', - 'PCI_ERR_ROOT_CMD_FATAL_EN', 'PCI_ERR_ROOT_CMD_NONFATAL_EN', - 'PCI_ERR_ROOT_COMMAND', 'PCI_ERR_ROOT_COR_RCV', - 'PCI_ERR_ROOT_ERR_SRC', 'PCI_ERR_ROOT_FATAL_RCV', - 'PCI_ERR_ROOT_FIRST_FATAL', 'PCI_ERR_ROOT_MULTI_COR_RCV', - 'PCI_ERR_ROOT_MULTI_UNCOR_RCV', 'PCI_ERR_ROOT_NONFATAL_RCV', - 'PCI_ERR_ROOT_STATUS', 'PCI_ERR_ROOT_UNCOR_RCV', - 'PCI_ERR_UNCOR_MASK', 'PCI_ERR_UNCOR_SEVER', - 'PCI_ERR_UNCOR_STATUS', 'PCI_ERR_UNC_ACSV', 'PCI_ERR_UNC_ATOMEG', - 'PCI_ERR_UNC_COMP_ABORT', 'PCI_ERR_UNC_COMP_TIME', - 'PCI_ERR_UNC_DLP', 'PCI_ERR_UNC_ECRC', 'PCI_ERR_UNC_FCP', - 'PCI_ERR_UNC_INTN', 'PCI_ERR_UNC_MALF_TLP', 'PCI_ERR_UNC_MCBTLP', - 'PCI_ERR_UNC_POISON_TLP', 'PCI_ERR_UNC_RX_OVER', - 'PCI_ERR_UNC_SURPDN', 'PCI_ERR_UNC_TLPPRE', 'PCI_ERR_UNC_UND', - 'PCI_ERR_UNC_UNSUP', 'PCI_ERR_UNC_UNX_COMP', 'PCI_EXP_DEVCAP', - 'PCI_EXP_DEVCAP2', 'PCI_EXP_DEVCAP2_ARI', - 'PCI_EXP_DEVCAP2_ATOMIC_COMP128', 'PCI_EXP_DEVCAP2_ATOMIC_COMP32', - 'PCI_EXP_DEVCAP2_ATOMIC_COMP64', 'PCI_EXP_DEVCAP2_ATOMIC_ROUTE', - 'PCI_EXP_DEVCAP2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCAP2_EE_PREFIX', - 'PCI_EXP_DEVCAP2_LTR', 'PCI_EXP_DEVCAP2_OBFF_MASK', - 'PCI_EXP_DEVCAP2_OBFF_MSG', 'PCI_EXP_DEVCAP2_OBFF_WAKE', - 'PCI_EXP_DEVCAP_ATN_BUT', 'PCI_EXP_DEVCAP_ATN_IND', - 'PCI_EXP_DEVCAP_EXT_TAG', 'PCI_EXP_DEVCAP_FLR', - 'PCI_EXP_DEVCAP_L0S', 'PCI_EXP_DEVCAP_L1', - 'PCI_EXP_DEVCAP_PAYLOAD', 'PCI_EXP_DEVCAP_PHANTOM', - 'PCI_EXP_DEVCAP_PWR_IND', 'PCI_EXP_DEVCAP_PWR_SCL', - 'PCI_EXP_DEVCAP_PWR_VAL', 'PCI_EXP_DEVCAP_RBER', 'PCI_EXP_DEVCTL', - 'PCI_EXP_DEVCTL2', 'PCI_EXP_DEVCTL2_ARI', - 'PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK', - 'PCI_EXP_DEVCTL2_ATOMIC_REQ', 'PCI_EXP_DEVCTL2_COMP_TIMEOUT', - 'PCI_EXP_DEVCTL2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCTL2_IDO_CMP_EN', - 'PCI_EXP_DEVCTL2_IDO_REQ_EN', 'PCI_EXP_DEVCTL2_LTR_EN', - 'PCI_EXP_DEVCTL2_OBFF_MSGA_EN', 'PCI_EXP_DEVCTL2_OBFF_MSGB_EN', - 'PCI_EXP_DEVCTL2_OBFF_WAKE_EN', 'PCI_EXP_DEVCTL_AUX_PME', - 'PCI_EXP_DEVCTL_BCR_FLR', 'PCI_EXP_DEVCTL_CERE', - 'PCI_EXP_DEVCTL_EXT_TAG', 'PCI_EXP_DEVCTL_FERE', - 'PCI_EXP_DEVCTL_NFERE', 'PCI_EXP_DEVCTL_NOSNOOP_EN', - 'PCI_EXP_DEVCTL_PAYLOAD', 'PCI_EXP_DEVCTL_PAYLOAD_1024B', - 'PCI_EXP_DEVCTL_PAYLOAD_128B', 'PCI_EXP_DEVCTL_PAYLOAD_2048B', - 'PCI_EXP_DEVCTL_PAYLOAD_256B', 'PCI_EXP_DEVCTL_PAYLOAD_4096B', - 'PCI_EXP_DEVCTL_PAYLOAD_512B', 'PCI_EXP_DEVCTL_PHANTOM', - 'PCI_EXP_DEVCTL_READRQ', 'PCI_EXP_DEVCTL_READRQ_1024B', - 'PCI_EXP_DEVCTL_READRQ_128B', 'PCI_EXP_DEVCTL_READRQ_2048B', - 'PCI_EXP_DEVCTL_READRQ_256B', 'PCI_EXP_DEVCTL_READRQ_4096B', - 'PCI_EXP_DEVCTL_READRQ_512B', 'PCI_EXP_DEVCTL_RELAX_EN', - 'PCI_EXP_DEVCTL_URRE', 'PCI_EXP_DEVSTA', 'PCI_EXP_DEVSTA2', - 'PCI_EXP_DEVSTA_AUXPD', 'PCI_EXP_DEVSTA_CED', - 'PCI_EXP_DEVSTA_FED', 'PCI_EXP_DEVSTA_NFED', - 'PCI_EXP_DEVSTA_TRPND', 'PCI_EXP_DEVSTA_URD', 'PCI_EXP_DPC_CAP', - 'PCI_EXP_DPC_CAP_DL_ACTIVE', 'PCI_EXP_DPC_CAP_POISONED_TLP', - 'PCI_EXP_DPC_CAP_RP_EXT', 'PCI_EXP_DPC_CAP_SW_TRIGGER', - 'PCI_EXP_DPC_CTL', 'PCI_EXP_DPC_CTL_EN_FATAL', - 'PCI_EXP_DPC_CTL_EN_NONFATAL', 'PCI_EXP_DPC_CTL_INT_EN', - 'PCI_EXP_DPC_IRQ', 'PCI_EXP_DPC_RP_BUSY', - 'PCI_EXP_DPC_RP_PIO_EXCEPTION', 'PCI_EXP_DPC_RP_PIO_HEADER_LOG', - 'PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG', 'PCI_EXP_DPC_RP_PIO_LOG_SIZE', - 'PCI_EXP_DPC_RP_PIO_MASK', 'PCI_EXP_DPC_RP_PIO_SEVERITY', - 'PCI_EXP_DPC_RP_PIO_STATUS', 'PCI_EXP_DPC_RP_PIO_SYSERROR', - 'PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG', 'PCI_EXP_DPC_SOURCE_ID', - 'PCI_EXP_DPC_STATUS', 'PCI_EXP_DPC_STATUS_INTERRUPT', - 'PCI_EXP_DPC_STATUS_TRIGGER', 'PCI_EXP_DPC_STATUS_TRIGGER_RSN', - 'PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT', 'PCI_EXP_FLAGS', - 'PCI_EXP_FLAGS_IRQ', 'PCI_EXP_FLAGS_SLOT', 'PCI_EXP_FLAGS_TYPE', - 'PCI_EXP_FLAGS_VERS', 'PCI_EXP_LNKCAP', 'PCI_EXP_LNKCAP2', - 'PCI_EXP_LNKCAP2_CROSSLINK', 'PCI_EXP_LNKCAP2_SLS_16_0GB', - 'PCI_EXP_LNKCAP2_SLS_2_5GB', 'PCI_EXP_LNKCAP2_SLS_32_0GB', - 'PCI_EXP_LNKCAP2_SLS_5_0GB', 'PCI_EXP_LNKCAP2_SLS_64_0GB', - 'PCI_EXP_LNKCAP2_SLS_8_0GB', 'PCI_EXP_LNKCAP_ASPMS', - 'PCI_EXP_LNKCAP_ASPM_L0S', 'PCI_EXP_LNKCAP_ASPM_L1', - 'PCI_EXP_LNKCAP_CLKPM', 'PCI_EXP_LNKCAP_DLLLARC', - 'PCI_EXP_LNKCAP_L0SEL', 'PCI_EXP_LNKCAP_L1EL', - 'PCI_EXP_LNKCAP_LBNC', 'PCI_EXP_LNKCAP_MLW', 'PCI_EXP_LNKCAP_PN', - 'PCI_EXP_LNKCAP_SDERC', 'PCI_EXP_LNKCAP_SLS', - 'PCI_EXP_LNKCAP_SLS_16_0GB', 'PCI_EXP_LNKCAP_SLS_2_5GB', - 'PCI_EXP_LNKCAP_SLS_32_0GB', 'PCI_EXP_LNKCAP_SLS_5_0GB', - 'PCI_EXP_LNKCAP_SLS_64_0GB', 'PCI_EXP_LNKCAP_SLS_8_0GB', - 'PCI_EXP_LNKCTL', 'PCI_EXP_LNKCTL2', 'PCI_EXP_LNKCTL2_ENTER_COMP', - 'PCI_EXP_LNKCTL2_HASD', 'PCI_EXP_LNKCTL2_TLS', - 'PCI_EXP_LNKCTL2_TLS_16_0GT', 'PCI_EXP_LNKCTL2_TLS_2_5GT', - 'PCI_EXP_LNKCTL2_TLS_32_0GT', 'PCI_EXP_LNKCTL2_TLS_5_0GT', - 'PCI_EXP_LNKCTL2_TLS_64_0GT', 'PCI_EXP_LNKCTL2_TLS_8_0GT', - 'PCI_EXP_LNKCTL2_TX_MARGIN', 'PCI_EXP_LNKCTL_ASPMC', - 'PCI_EXP_LNKCTL_ASPM_L0S', 'PCI_EXP_LNKCTL_ASPM_L1', - 'PCI_EXP_LNKCTL_CCC', 'PCI_EXP_LNKCTL_CLKREQ_EN', - 'PCI_EXP_LNKCTL_ES', 'PCI_EXP_LNKCTL_HAWD', - 'PCI_EXP_LNKCTL_LABIE', 'PCI_EXP_LNKCTL_LBMIE', - 'PCI_EXP_LNKCTL_LD', 'PCI_EXP_LNKCTL_RCB', 'PCI_EXP_LNKCTL_RL', - 'PCI_EXP_LNKSTA', 'PCI_EXP_LNKSTA2', 'PCI_EXP_LNKSTA_CLS', - 'PCI_EXP_LNKSTA_CLS_16_0GB', 'PCI_EXP_LNKSTA_CLS_2_5GB', - 'PCI_EXP_LNKSTA_CLS_32_0GB', 'PCI_EXP_LNKSTA_CLS_5_0GB', - 'PCI_EXP_LNKSTA_CLS_64_0GB', 'PCI_EXP_LNKSTA_CLS_8_0GB', - 'PCI_EXP_LNKSTA_DLLLA', 'PCI_EXP_LNKSTA_LABS', - 'PCI_EXP_LNKSTA_LBMS', 'PCI_EXP_LNKSTA_LT', 'PCI_EXP_LNKSTA_NLW', - 'PCI_EXP_LNKSTA_NLW_SHIFT', 'PCI_EXP_LNKSTA_NLW_X1', - 'PCI_EXP_LNKSTA_NLW_X2', 'PCI_EXP_LNKSTA_NLW_X4', - 'PCI_EXP_LNKSTA_NLW_X8', 'PCI_EXP_LNKSTA_SLC', 'PCI_EXP_RTCAP', - 'PCI_EXP_RTCAP_CRSVIS', 'PCI_EXP_RTCTL', 'PCI_EXP_RTCTL_CRSSVE', - 'PCI_EXP_RTCTL_PMEIE', 'PCI_EXP_RTCTL_SECEE', - 'PCI_EXP_RTCTL_SEFEE', 'PCI_EXP_RTCTL_SENFEE', 'PCI_EXP_RTSTA', - 'PCI_EXP_RTSTA_PENDING', 'PCI_EXP_RTSTA_PME', 'PCI_EXP_SLTCAP', - 'PCI_EXP_SLTCAP2', 'PCI_EXP_SLTCAP2_IBPD', 'PCI_EXP_SLTCAP_ABP', - 'PCI_EXP_SLTCAP_AIP', 'PCI_EXP_SLTCAP_EIP', 'PCI_EXP_SLTCAP_HPC', - 'PCI_EXP_SLTCAP_HPS', 'PCI_EXP_SLTCAP_MRLSP', - 'PCI_EXP_SLTCAP_NCCS', 'PCI_EXP_SLTCAP_PCP', 'PCI_EXP_SLTCAP_PIP', - 'PCI_EXP_SLTCAP_PSN', 'PCI_EXP_SLTCAP_SPLS', - 'PCI_EXP_SLTCAP_SPLV', 'PCI_EXP_SLTCTL', 'PCI_EXP_SLTCTL2', - 'PCI_EXP_SLTCTL_ABPE', 'PCI_EXP_SLTCTL_AIC', - 'PCI_EXP_SLTCTL_ATTN_IND_BLINK', 'PCI_EXP_SLTCTL_ATTN_IND_OFF', - 'PCI_EXP_SLTCTL_ATTN_IND_ON', 'PCI_EXP_SLTCTL_ATTN_IND_SHIFT', - 'PCI_EXP_SLTCTL_CCIE', 'PCI_EXP_SLTCTL_DLLSCE', - 'PCI_EXP_SLTCTL_EIC', 'PCI_EXP_SLTCTL_HPIE', - 'PCI_EXP_SLTCTL_IBPD_DISABLE', 'PCI_EXP_SLTCTL_MRLSCE', - 'PCI_EXP_SLTCTL_PCC', 'PCI_EXP_SLTCTL_PDCE', - 'PCI_EXP_SLTCTL_PFDE', 'PCI_EXP_SLTCTL_PIC', - 'PCI_EXP_SLTCTL_PWR_IND_BLINK', 'PCI_EXP_SLTCTL_PWR_IND_OFF', - 'PCI_EXP_SLTCTL_PWR_IND_ON', 'PCI_EXP_SLTCTL_PWR_OFF', - 'PCI_EXP_SLTCTL_PWR_ON', 'PCI_EXP_SLTSTA', 'PCI_EXP_SLTSTA2', - 'PCI_EXP_SLTSTA_ABP', 'PCI_EXP_SLTSTA_CC', 'PCI_EXP_SLTSTA_DLLSC', - 'PCI_EXP_SLTSTA_EIS', 'PCI_EXP_SLTSTA_MRLSC', - 'PCI_EXP_SLTSTA_MRLSS', 'PCI_EXP_SLTSTA_PDC', - 'PCI_EXP_SLTSTA_PDS', 'PCI_EXP_SLTSTA_PFD', - 'PCI_EXP_TYPE_DOWNSTREAM', 'PCI_EXP_TYPE_ENDPOINT', - 'PCI_EXP_TYPE_LEG_END', 'PCI_EXP_TYPE_PCIE_BRIDGE', - 'PCI_EXP_TYPE_PCI_BRIDGE', 'PCI_EXP_TYPE_RC_EC', - 'PCI_EXP_TYPE_RC_END', 'PCI_EXP_TYPE_ROOT_PORT', - 'PCI_EXP_TYPE_UPSTREAM', 'PCI_EXT_CAP_ARI_SIZEOF', - 'PCI_EXT_CAP_ATS_SIZEOF', 'PCI_EXT_CAP_DSN_SIZEOF', - 'PCI_EXT_CAP_ID_ACS', 'PCI_EXT_CAP_ID_AMD_XXX', - 'PCI_EXT_CAP_ID_ARI', 'PCI_EXT_CAP_ID_ATS', 'PCI_EXT_CAP_ID_CAC', - 'PCI_EXT_CAP_ID_DLF', 'PCI_EXT_CAP_ID_DPA', 'PCI_EXT_CAP_ID_DPC', - 'PCI_EXT_CAP_ID_DSN', 'PCI_EXT_CAP_ID_DVSEC', - 'PCI_EXT_CAP_ID_ERR', 'PCI_EXT_CAP_ID_L1SS', 'PCI_EXT_CAP_ID_LTR', - 'PCI_EXT_CAP_ID_MAX', 'PCI_EXT_CAP_ID_MCAST', - 'PCI_EXT_CAP_ID_MFVC', 'PCI_EXT_CAP_ID_MRIOV', - 'PCI_EXT_CAP_ID_PASID', 'PCI_EXT_CAP_ID_PL_16GT', - 'PCI_EXT_CAP_ID_PMUX', 'PCI_EXT_CAP_ID_PRI', 'PCI_EXT_CAP_ID_PTM', - 'PCI_EXT_CAP_ID_PWR', 'PCI_EXT_CAP_ID_RCEC', - 'PCI_EXT_CAP_ID_RCILC', 'PCI_EXT_CAP_ID_RCLD', - 'PCI_EXT_CAP_ID_RCRB', 'PCI_EXT_CAP_ID_REBAR', - 'PCI_EXT_CAP_ID_SECPCI', 'PCI_EXT_CAP_ID_SRIOV', - 'PCI_EXT_CAP_ID_TPH', 'PCI_EXT_CAP_ID_VC', 'PCI_EXT_CAP_ID_VC9', - 'PCI_EXT_CAP_ID_VNDR', 'PCI_EXT_CAP_LTR_SIZEOF', - 'PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF', 'PCI_EXT_CAP_PASID_SIZEOF', - 'PCI_EXT_CAP_PRI_SIZEOF', 'PCI_EXT_CAP_PWR_SIZEOF', - 'PCI_EXT_CAP_SRIOV_SIZEOF', 'PCI_HEADER_TYPE', - 'PCI_HEADER_TYPE_BRIDGE', 'PCI_HEADER_TYPE_CARDBUS', - 'PCI_HEADER_TYPE_MASK', 'PCI_HEADER_TYPE_NORMAL', - 'PCI_INTERRUPT_LINE', 'PCI_INTERRUPT_PIN', 'PCI_IO_1K_RANGE_MASK', - 'PCI_IO_BASE', 'PCI_IO_BASE_UPPER16', 'PCI_IO_LIMIT', - 'PCI_IO_LIMIT_UPPER16', 'PCI_IO_RANGE_MASK', - 'PCI_IO_RANGE_TYPE_16', 'PCI_IO_RANGE_TYPE_32', - 'PCI_IO_RANGE_TYPE_MASK', 'PCI_L1SS_CAP', - 'PCI_L1SS_CAP_ASPM_L1_1', 'PCI_L1SS_CAP_ASPM_L1_2', - 'PCI_L1SS_CAP_CM_RESTORE_TIME', 'PCI_L1SS_CAP_L1_PM_SS', - 'PCI_L1SS_CAP_PCIPM_L1_1', 'PCI_L1SS_CAP_PCIPM_L1_2', - 'PCI_L1SS_CAP_P_PWR_ON_SCALE', 'PCI_L1SS_CAP_P_PWR_ON_VALUE', - 'PCI_L1SS_CTL1', 'PCI_L1SS_CTL1_ASPM_L1_1', - 'PCI_L1SS_CTL1_ASPM_L1_2', 'PCI_L1SS_CTL1_CM_RESTORE_TIME', - 'PCI_L1SS_CTL1_L1SS_MASK', 'PCI_L1SS_CTL1_L1_2_MASK', - 'PCI_L1SS_CTL1_LTR_L12_TH_SCALE', - 'PCI_L1SS_CTL1_LTR_L12_TH_VALUE', 'PCI_L1SS_CTL1_PCIPM_L1_1', - 'PCI_L1SS_CTL1_PCIPM_L1_2', 'PCI_L1SS_CTL2', 'PCI_LATENCY_TIMER', - 'PCI_LTR_MAX_NOSNOOP_LAT', 'PCI_LTR_MAX_SNOOP_LAT', - 'PCI_LTR_SCALE_MASK', 'PCI_LTR_SCALE_SHIFT', 'PCI_LTR_VALUE_MASK', - 'PCI_MAX_LAT', 'PCI_MEMORY_BASE', 'PCI_MEMORY_LIMIT', - 'PCI_MEMORY_RANGE_MASK', 'PCI_MEMORY_RANGE_TYPE_MASK', - 'PCI_MIN_GNT', 'PCI_MSIX_ENTRY_CTRL_MASKBIT', - 'PCI_MSIX_ENTRY_DATA', 'PCI_MSIX_ENTRY_LOWER_ADDR', - 'PCI_MSIX_ENTRY_SIZE', 'PCI_MSIX_ENTRY_UPPER_ADDR', - 'PCI_MSIX_ENTRY_VECTOR_CTRL', 'PCI_MSIX_FLAGS', - 'PCI_MSIX_FLAGS_BIRMASK', 'PCI_MSIX_FLAGS_ENABLE', - 'PCI_MSIX_FLAGS_MASKALL', 'PCI_MSIX_FLAGS_QSIZE', 'PCI_MSIX_PBA', - 'PCI_MSIX_PBA_BIR', 'PCI_MSIX_PBA_OFFSET', 'PCI_MSIX_TABLE', - 'PCI_MSIX_TABLE_BIR', 'PCI_MSIX_TABLE_OFFSET', - 'PCI_MSI_ADDRESS_HI', 'PCI_MSI_ADDRESS_LO', 'PCI_MSI_DATA_32', - 'PCI_MSI_DATA_64', 'PCI_MSI_FLAGS', 'PCI_MSI_FLAGS_64BIT', - 'PCI_MSI_FLAGS_ENABLE', 'PCI_MSI_FLAGS_MASKBIT', - 'PCI_MSI_FLAGS_QMASK', 'PCI_MSI_FLAGS_QSIZE', 'PCI_MSI_MASK_32', - 'PCI_MSI_MASK_64', 'PCI_MSI_PENDING_32', 'PCI_MSI_PENDING_64', - 'PCI_MSI_RFU', 'PCI_PASID_CAP', 'PCI_PASID_CAP_EXEC', - 'PCI_PASID_CAP_PRIV', 'PCI_PASID_CTRL', 'PCI_PASID_CTRL_ENABLE', - 'PCI_PASID_CTRL_EXEC', 'PCI_PASID_CTRL_PRIV', - 'PCI_PL_16GT_LE_CTRL', 'PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK', - 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK', - 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT', 'PCI_PM_BPCC_ENABLE', - 'PCI_PM_CAP_AUX_POWER', 'PCI_PM_CAP_D1', 'PCI_PM_CAP_D2', - 'PCI_PM_CAP_DSI', 'PCI_PM_CAP_PME', 'PCI_PM_CAP_PME_CLOCK', - 'PCI_PM_CAP_PME_D0', 'PCI_PM_CAP_PME_D1', 'PCI_PM_CAP_PME_D2', - 'PCI_PM_CAP_PME_D3cold', 'PCI_PM_CAP_PME_D3hot', - 'PCI_PM_CAP_PME_MASK', 'PCI_PM_CAP_PME_SHIFT', - 'PCI_PM_CAP_RESERVED', 'PCI_PM_CAP_VER_MASK', 'PCI_PM_CTRL', - 'PCI_PM_CTRL_DATA_SCALE_MASK', 'PCI_PM_CTRL_DATA_SEL_MASK', - 'PCI_PM_CTRL_NO_SOFT_RESET', 'PCI_PM_CTRL_PME_ENABLE', - 'PCI_PM_CTRL_PME_STATUS', 'PCI_PM_CTRL_STATE_MASK', - 'PCI_PM_DATA_REGISTER', 'PCI_PM_PMC', 'PCI_PM_PPB_B2_B3', - 'PCI_PM_PPB_EXTENSIONS', 'PCI_PM_SIZEOF', 'PCI_PREF_BASE_UPPER32', - 'PCI_PREF_LIMIT_UPPER32', 'PCI_PREF_MEMORY_BASE', - 'PCI_PREF_MEMORY_LIMIT', 'PCI_PREF_RANGE_MASK', - 'PCI_PREF_RANGE_TYPE_32', 'PCI_PREF_RANGE_TYPE_64', - 'PCI_PREF_RANGE_TYPE_MASK', 'PCI_PRIMARY_BUS', - 'PCI_PRI_ALLOC_REQ', 'PCI_PRI_CTRL', 'PCI_PRI_CTRL_ENABLE', - 'PCI_PRI_CTRL_RESET', 'PCI_PRI_MAX_REQ', 'PCI_PRI_STATUS', - 'PCI_PRI_STATUS_PASID', 'PCI_PRI_STATUS_RF', - 'PCI_PRI_STATUS_STOPPED', 'PCI_PRI_STATUS_UPRGI', 'PCI_PTM_CAP', - 'PCI_PTM_CAP_REQ', 'PCI_PTM_CAP_ROOT', 'PCI_PTM_CTRL', - 'PCI_PTM_CTRL_ENABLE', 'PCI_PTM_CTRL_ROOT', - 'PCI_PTM_GRANULARITY_MASK', 'PCI_PWR_CAP', 'PCI_PWR_DATA', - 'PCI_PWR_DSR', 'PCI_RCEC_BUSN', 'PCI_RCEC_BUSN_REG_VER', - 'PCI_RCEC_RCIEP_BITMAP', 'PCI_REBAR_CAP', 'PCI_REBAR_CAP_SIZES', - 'PCI_REBAR_CTRL', 'PCI_REBAR_CTRL_BAR_IDX', - 'PCI_REBAR_CTRL_BAR_SHIFT', 'PCI_REBAR_CTRL_BAR_SIZE', - 'PCI_REBAR_CTRL_NBAR_MASK', 'PCI_REBAR_CTRL_NBAR_SHIFT', - 'PCI_REVISION_ID', 'PCI_ROM_ADDRESS', 'PCI_ROM_ADDRESS1', - 'PCI_ROM_ADDRESS_ENABLE', 'PCI_ROM_ADDRESS_MASK', 'PCI_SATA_REGS', - 'PCI_SATA_REGS_INLINE', 'PCI_SATA_REGS_MASK', - 'PCI_SATA_SIZEOF_LONG', 'PCI_SATA_SIZEOF_SHORT', - 'PCI_SECONDARY_BUS', 'PCI_SEC_LATENCY_TIMER', 'PCI_SEC_STATUS', - 'PCI_SID_CHASSIS_NR', 'PCI_SID_ESR', 'PCI_SID_ESR_FIC', - 'PCI_SID_ESR_NSLOTS', 'PCI_SRIOV_BAR', 'PCI_SRIOV_CAP', - 'PCI_SRIOV_CAP_VFM', 'PCI_SRIOV_CTRL', 'PCI_SRIOV_CTRL_ARI', - 'PCI_SRIOV_CTRL_INTR', 'PCI_SRIOV_CTRL_MSE', 'PCI_SRIOV_CTRL_VFE', - 'PCI_SRIOV_CTRL_VFM', 'PCI_SRIOV_FUNC_LINK', - 'PCI_SRIOV_INITIAL_VF', 'PCI_SRIOV_NUM_BARS', 'PCI_SRIOV_NUM_VF', - 'PCI_SRIOV_STATUS', 'PCI_SRIOV_STATUS_VFM', - 'PCI_SRIOV_SUP_PGSIZE', 'PCI_SRIOV_SYS_PGSIZE', - 'PCI_SRIOV_TOTAL_VF', 'PCI_SRIOV_VFM', 'PCI_SRIOV_VFM_AV', - 'PCI_SRIOV_VFM_MI', 'PCI_SRIOV_VFM_MO', 'PCI_SRIOV_VFM_UA', - 'PCI_SRIOV_VF_DID', 'PCI_SRIOV_VF_OFFSET', 'PCI_SRIOV_VF_STRIDE', - 'PCI_SSVID_DEVICE_ID', 'PCI_SSVID_VENDOR_ID', 'PCI_STATUS', - 'PCI_STATUS_66MHZ', 'PCI_STATUS_CAP_LIST', - 'PCI_STATUS_DETECTED_PARITY', 'PCI_STATUS_DEVSEL_FAST', - 'PCI_STATUS_DEVSEL_MASK', 'PCI_STATUS_DEVSEL_MEDIUM', - 'PCI_STATUS_DEVSEL_SLOW', 'PCI_STATUS_FAST_BACK', - 'PCI_STATUS_IMM_READY', 'PCI_STATUS_INTERRUPT', - 'PCI_STATUS_PARITY', 'PCI_STATUS_REC_MASTER_ABORT', - 'PCI_STATUS_REC_TARGET_ABORT', 'PCI_STATUS_SIG_SYSTEM_ERROR', - 'PCI_STATUS_SIG_TARGET_ABORT', 'PCI_STATUS_UDF', - 'PCI_STD_HEADER_SIZEOF', 'PCI_STD_NUM_BARS', - 'PCI_SUBORDINATE_BUS', 'PCI_SUBSYSTEM_ID', - 'PCI_SUBSYSTEM_VENDOR_ID', 'PCI_TPH_BASE_SIZEOF', 'PCI_TPH_CAP', - 'PCI_TPH_CAP_LOC_MASK', 'PCI_TPH_CAP_ST_MASK', - 'PCI_TPH_CAP_ST_SHIFT', 'PCI_TPH_LOC_CAP', 'PCI_TPH_LOC_MSIX', - 'PCI_TPH_LOC_NONE', 'PCI_VC_CAP1_ARB_SIZE', 'PCI_VC_CAP1_EVCC', - 'PCI_VC_CAP1_LPEVCC', 'PCI_VC_CAP2_128_PHASE', - 'PCI_VC_CAP2_32_PHASE', 'PCI_VC_CAP2_64_PHASE', - 'PCI_VC_CAP2_ARB_OFF', 'PCI_VC_PORT_CAP1', 'PCI_VC_PORT_CAP2', - 'PCI_VC_PORT_CTRL', 'PCI_VC_PORT_CTRL_LOAD_TABLE', - 'PCI_VC_PORT_STATUS', 'PCI_VC_PORT_STATUS_TABLE', - 'PCI_VC_RES_CAP', 'PCI_VC_RES_CAP_128_PHASE', - 'PCI_VC_RES_CAP_128_PHASE_TB', 'PCI_VC_RES_CAP_256_PHASE', - 'PCI_VC_RES_CAP_32_PHASE', 'PCI_VC_RES_CAP_64_PHASE', - 'PCI_VC_RES_CAP_ARB_OFF', 'PCI_VC_RES_CTRL', - 'PCI_VC_RES_CTRL_ARB_SELECT', 'PCI_VC_RES_CTRL_ENABLE', - 'PCI_VC_RES_CTRL_ID', 'PCI_VC_RES_CTRL_LOAD_TABLE', - 'PCI_VC_RES_STATUS', 'PCI_VC_RES_STATUS_NEGO', - 'PCI_VC_RES_STATUS_TABLE', 'PCI_VENDOR_ID', 'PCI_VNDR_HEADER', - 'PCI_VPD_ADDR', 'PCI_VPD_ADDR_F', 'PCI_VPD_ADDR_MASK', - 'PCI_VPD_DATA', 'PCI_VSEC_HDR', 'PCI_VSEC_HDR_LEN_SHIFT', - 'PCI_X_BRIDGE_SSTATUS', 'PCI_X_BRIDGE_STATUS', 'PCI_X_CMD', - 'PCI_X_CMD_DPERR_E', 'PCI_X_CMD_ERO', 'PCI_X_CMD_MAX_READ', - 'PCI_X_CMD_MAX_SPLIT', 'PCI_X_CMD_READ_1K', 'PCI_X_CMD_READ_2K', - 'PCI_X_CMD_READ_4K', 'PCI_X_CMD_READ_512', 'PCI_X_CMD_SPLIT_1', - 'PCI_X_CMD_SPLIT_12', 'PCI_X_CMD_SPLIT_16', 'PCI_X_CMD_SPLIT_2', - 'PCI_X_CMD_SPLIT_3', 'PCI_X_CMD_SPLIT_32', 'PCI_X_CMD_SPLIT_4', - 'PCI_X_CMD_SPLIT_8', 'PCI_X_ECC_CSR', 'PCI_X_SSTATUS_133MHZ', - 'PCI_X_SSTATUS_266MHZ', 'PCI_X_SSTATUS_533MHZ', - 'PCI_X_SSTATUS_64BIT', 'PCI_X_SSTATUS_FREQ', 'PCI_X_SSTATUS_V1', - 'PCI_X_SSTATUS_V2', 'PCI_X_SSTATUS_VERS', 'PCI_X_STATUS', - 'PCI_X_STATUS_133MHZ', 'PCI_X_STATUS_266MHZ', - 'PCI_X_STATUS_533MHZ', 'PCI_X_STATUS_64BIT', 'PCI_X_STATUS_BUS', - 'PCI_X_STATUS_COMPLEX', 'PCI_X_STATUS_DEVFN', - 'PCI_X_STATUS_MAX_CUM', 'PCI_X_STATUS_MAX_READ', - 'PCI_X_STATUS_MAX_SPLIT', 'PCI_X_STATUS_SPL_DISC', - 'PCI_X_STATUS_SPL_ERR', 'PCI_X_STATUS_UNX_SPL'] diff --git a/tinygrad/tinygrad/runtime/autogen/qcom_dsp.py b/tinygrad/tinygrad/runtime/autogen/qcom_dsp.py deleted file mode 100644 index fa517a5a..00000000 --- a/tinygrad/tinygrad/runtime/autogen/qcom_dsp.py +++ /dev/null @@ -1,1739 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - -import fcntl, functools - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, *args, **kwargs): - ret = fcntl.ioctl(__fd, (__idir<<30) | (ctypes.sizeof(made := __user_struct(*args, **kwargs))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise OSError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -_UAPI_LINUX_ION_H = True # macro -# ION_NUM_HEAP_IDS = (ctypes.sizeof*8) # macro -ION_FLAG_CACHED = 1 # macro -ION_FLAG_CACHED_NEEDS_SYNC = 2 # macro -ION_IOC_MAGIC = 'I' # macro -ion_user_handle_t = ctypes.c_int32 - -# values for enumeration 'ion_heap_type' -ion_heap_type__enumvalues = { - 0: 'ION_HEAP_TYPE_SYSTEM', - 1: 'ION_HEAP_TYPE_SYSTEM_CONTIG', - 2: 'ION_HEAP_TYPE_CARVEOUT', - 3: 'ION_HEAP_TYPE_CHUNK', - 4: 'ION_HEAP_TYPE_DMA', - 5: 'ION_HEAP_TYPE_CUSTOM', - 16: 'ION_NUM_HEAPS', -} -ION_HEAP_TYPE_SYSTEM = 0 -ION_HEAP_TYPE_SYSTEM_CONTIG = 1 -ION_HEAP_TYPE_CARVEOUT = 2 -ION_HEAP_TYPE_CHUNK = 3 -ION_HEAP_TYPE_DMA = 4 -ION_HEAP_TYPE_CUSTOM = 5 -ION_NUM_HEAPS = 16 -ion_heap_type = ctypes.c_uint32 # enum -ION_HEAP_SYSTEM_MASK = ((1<>16)&0x0ff) -def REMOTE_SCALARS_OUTBUFS(dwScalars): # macro - return (((dwScalars)>>8)&0x0ff) -def REMOTE_SCALARS_INHANDLES(dwScalars): # macro - return (((dwScalars)>>4)&0x0f) -def REMOTE_SCALARS_OUTHANDLES(dwScalars): # macro - return ((dwScalars)&0x0f) -def REMOTE_SCALARS_LENGTH(sc): # macro - return (REMOTE_SCALARS_INBUFS(sc)+REMOTE_SCALARS_OUTBUFS(sc)+REMOTE_SCALARS_INHANDLES(sc)+REMOTE_SCALARS_OUTHANDLES(sc)) -def REMOTE_SCALARS_MAKEX(nAttr, nMethod, nIn, nOut, noIn, noOut): # macro - return ((((nAttr)&0x7)<<29)|(((nMethod)&0x1f)<<24)|(((nIn)&0xff)<<16)|(((nOut)&0xff)<<8)|(((noIn)&0x0f)<<4)|((noOut)&0x0f)) -def REMOTE_SCALARS_MAKE(nMethod, nIn, nOut): # macro - return REMOTE_SCALARS_MAKEX(0,nMethod,nIn,nOut,0,0) -# def VERIFY_EPRINTF(format, args): # macro -# return (void)0 -# def VERIFY_IPRINTF(args): # macro -# return (void)0 -# def __STR__(x): # macro -# return #x":" -def __TOSTR__(x): # macro - return __STR__(x) -# __FILE_LINE__ = __FILE__ ":" __TOSTR__ ( __LINE__ ) # macro -# def VERIFY(err, val): # macro -# return {VERIFY_IPRINTF(__FILE__":"__TOSTR__(__LINE__)"info: calling: "#val"\n");((val)==0){(err)=(err)==0?-1:(err);VERIFY_EPRINTF(__FILE__":"__TOSTR__(__LINE__)"error: %d: "#val"\n",(err));}{VERIFY_IPRINTF(__FILE__":"__TOSTR__(__LINE__)"info: passed: "#val"\n");}\}(0) -# remote_arg64_t = remote_arg64 # macro -FASTRPC_CONTROL_LATENCY = (1) # macro -FASTRPC_CONTROL_SMMU = (2) # macro -FASTRPC_CONTROL_KALLOC = (3) # macro -class struct_remote_buf64(Structure): - pass - -struct_remote_buf64._pack_ = 1 # source:False -struct_remote_buf64._fields_ = [ - ('pv', ctypes.c_uint64), - ('len', ctypes.c_uint64), -] - -class struct_remote_dma_handle64(Structure): - pass - -struct_remote_dma_handle64._pack_ = 1 # source:False -struct_remote_dma_handle64._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), - ('len', ctypes.c_uint32), -] - -class union_remote_arg64(Union): - pass - -union_remote_arg64._pack_ = 1 # source:False -union_remote_arg64._fields_ = [ - ('buf', struct_remote_buf64), - ('dma', struct_remote_dma_handle64), - ('h', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 12), -] - -class struct_remote_buf(Structure): - pass - -struct_remote_buf._pack_ = 1 # source:False -struct_remote_buf._fields_ = [ - ('pv', ctypes.POINTER(None)), - ('len', ctypes.c_uint64), -] - -class struct_remote_dma_handle(Structure): - pass - -struct_remote_dma_handle._pack_ = 1 # source:False -struct_remote_dma_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), -] - -class union_remote_arg(Union): - pass - -union_remote_arg._pack_ = 1 # source:False -union_remote_arg._fields_ = [ - ('buf', struct_remote_buf), - ('dma', struct_remote_dma_handle), - ('h', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 12), -] - -class struct_fastrpc_ioctl_invoke(Structure): - pass - -struct_fastrpc_ioctl_invoke._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke._fields_ = [ - ('handle', ctypes.c_uint32), - ('sc', ctypes.c_uint32), - ('pra', ctypes.POINTER(union_remote_arg)), -] - -FASTRPC_IOCTL_INVOKE = _IOWR ( 'R' , 1 , struct_fastrpc_ioctl_invoke ) # macro (from list) -class struct_fastrpc_ioctl_invoke_fd(Structure): - pass - -struct_fastrpc_ioctl_invoke_fd._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_fd._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), -] - -FASTRPC_IOCTL_INVOKE_FD = _IOWR ( 'R' , 4 , struct_fastrpc_ioctl_invoke_fd ) # macro (from list) -class struct_fastrpc_ioctl_invoke_attrs(Structure): - pass - -struct_fastrpc_ioctl_invoke_attrs._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_attrs._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), - ('attrs', ctypes.POINTER(ctypes.c_uint32)), -] - -FASTRPC_IOCTL_INVOKE_ATTRS = _IOWR ( 'R' , 7 , struct_fastrpc_ioctl_invoke_attrs ) # macro (from list) -class struct_fastrpc_ioctl_invoke_crc(Structure): - pass - -struct_fastrpc_ioctl_invoke_crc._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_crc._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), - ('attrs', ctypes.POINTER(ctypes.c_uint32)), - ('crc', ctypes.POINTER(ctypes.c_uint32)), -] - -FASTRPC_IOCTL_INVOKE_CRC = _IOWR ( 'R' , 11 , struct_fastrpc_ioctl_invoke_crc ) # macro (from list) -class struct_fastrpc_ioctl_init(Structure): - pass - -struct_fastrpc_ioctl_init._pack_ = 1 # source:False -struct_fastrpc_ioctl_init._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('file', ctypes.c_uint64), - ('filelen', ctypes.c_uint32), - ('filefd', ctypes.c_int32), - ('mem', ctypes.c_uint64), - ('memlen', ctypes.c_uint32), - ('memfd', ctypes.c_int32), -] - -FASTRPC_IOCTL_INIT = _IOWR ( 'R' , 6 , struct_fastrpc_ioctl_init ) # macro (from list) -class struct_fastrpc_ioctl_init_attrs(Structure): - pass - -struct_fastrpc_ioctl_init_attrs._pack_ = 1 # source:False -struct_fastrpc_ioctl_init_attrs._fields_ = [ - ('init', struct_fastrpc_ioctl_init), - ('attrs', ctypes.c_int32), - ('siglen', ctypes.c_uint32), -] - -FASTRPC_IOCTL_INIT_ATTRS = _IOWR ( 'R' , 10 , struct_fastrpc_ioctl_init_attrs ) # macro (from list) -class struct_fastrpc_ioctl_munmap(Structure): - pass - -struct_fastrpc_ioctl_munmap._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap._fields_ = [ - ('vaddrout', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MUNMAP = _IOWR ( 'R' , 3 , struct_fastrpc_ioctl_munmap ) # macro (from list) -class struct_fastrpc_ioctl_munmap_64(Structure): - pass - -struct_fastrpc_ioctl_munmap_64._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap_64._fields_ = [ - ('vaddrout', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MUNMAP_64 = _IOWR ( 'R' , 15 , struct_fastrpc_ioctl_munmap_64 ) # macro (from list) -class struct_fastrpc_ioctl_mmap(Structure): - pass - -struct_fastrpc_ioctl_mmap._pack_ = 1 # source:False -struct_fastrpc_ioctl_mmap._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('vaddrin', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('vaddrout', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MMAP = _IOWR ( 'R' , 2 , struct_fastrpc_ioctl_mmap ) # macro (from list) -class struct_fastrpc_ioctl_mmap_64(Structure): - pass - -struct_fastrpc_ioctl_mmap_64._pack_ = 1 # source:False -struct_fastrpc_ioctl_mmap_64._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('vaddrin', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('vaddrout', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MMAP_64 = _IOWR ( 'R' , 14 , struct_fastrpc_ioctl_mmap_64 ) # macro (from list) -class struct_fastrpc_ioctl_munmap_fd(Structure): - pass - -struct_fastrpc_ioctl_munmap_fd._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap_fd._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('va', ctypes.c_uint64), - ('len', ctypes.c_int64), -] - -FASTRPC_IOCTL_MUNMAP_FD = _IOWR ( 'R' , 13 , struct_fastrpc_ioctl_munmap_fd ) # macro (from list) -class struct_fastrpc_ioctl_perf(Structure): - pass - -struct_fastrpc_ioctl_perf._pack_ = 1 # source:False -struct_fastrpc_ioctl_perf._fields_ = [ - ('data', ctypes.c_uint64), - ('numkeys', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('keys', ctypes.c_uint64), -] - -FASTRPC_IOCTL_GETPERF = _IOWR ( 'R' , 9 , struct_fastrpc_ioctl_perf ) # macro (from list) -class struct_fastrpc_ctrl_latency(Structure): - pass - -struct_fastrpc_ctrl_latency._pack_ = 1 # source:False -struct_fastrpc_ctrl_latency._fields_ = [ - ('enable', ctypes.c_uint32), - ('level', ctypes.c_uint32), -] - -class struct_fastrpc_ctrl_smmu(Structure): - pass - -struct_fastrpc_ctrl_smmu._pack_ = 1 # source:False -struct_fastrpc_ctrl_smmu._fields_ = [ - ('sharedcb', ctypes.c_uint32), -] - -class struct_fastrpc_ctrl_kalloc(Structure): - pass - -struct_fastrpc_ctrl_kalloc._pack_ = 1 # source:False -struct_fastrpc_ctrl_kalloc._fields_ = [ - ('kalloc_support', ctypes.c_uint32), -] - -class struct_fastrpc_ioctl_control(Structure): - pass - -class union_fastrpc_ioctl_control_0(Union): - pass - -union_fastrpc_ioctl_control_0._pack_ = 1 # source:False -union_fastrpc_ioctl_control_0._fields_ = [ - ('lp', struct_fastrpc_ctrl_latency), - ('smmu', struct_fastrpc_ctrl_smmu), - ('kalloc', struct_fastrpc_ctrl_kalloc), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_fastrpc_ioctl_control._pack_ = 1 # source:False -struct_fastrpc_ioctl_control._anonymous_ = ('_0',) -struct_fastrpc_ioctl_control._fields_ = [ - ('req', ctypes.c_uint32), - ('_0', union_fastrpc_ioctl_control_0), -] - -FASTRPC_IOCTL_CONTROL = _IOWR ( 'R' , 12 , struct_fastrpc_ioctl_control ) # macro (from list) -class struct_smq_null_invoke(Structure): - pass - -struct_smq_null_invoke._pack_ = 1 # source:False -struct_smq_null_invoke._fields_ = [ - ('ctx', ctypes.c_uint64), - ('handle', ctypes.c_uint32), - ('sc', ctypes.c_uint32), -] - -class struct_smq_phy_page(Structure): - pass - -struct_smq_phy_page._pack_ = 1 # source:False -struct_smq_phy_page._fields_ = [ - ('addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -class struct_smq_invoke_buf(Structure): - pass - -struct_smq_invoke_buf._pack_ = 1 # source:False -struct_smq_invoke_buf._fields_ = [ - ('num', ctypes.c_int32), - ('pgidx', ctypes.c_int32), -] - -class struct_smq_invoke(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_smq_null_invoke), - ('page', struct_smq_phy_page), - ] - -class struct_smq_msg(Structure): - pass - -struct_smq_msg._pack_ = 1 # source:False -struct_smq_msg._fields_ = [ - ('pid', ctypes.c_uint32), - ('tid', ctypes.c_uint32), - ('invoke', struct_smq_invoke), -] - -class struct_smq_invoke_rsp(Structure): - pass - -struct_smq_invoke_rsp._pack_ = 1 # source:False -struct_smq_invoke_rsp._fields_ = [ - ('ctx', ctypes.c_uint64), - ('retval', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -uint32_t = ctypes.c_uint32 -FASTRPC_IOCTL_SETMODE = _IOWR ( 'R' , 5 , uint32_t ) # macro (from list) -FASTRPC_IOCTL_GETINFO = _IOWR ( 'R' , 8 , uint32_t ) # macro (from list) -try: - smq_invoke_buf_start = _libraries['FIXME_STUB'].smq_invoke_buf_start - smq_invoke_buf_start.restype = ctypes.POINTER(struct_smq_invoke_buf) - smq_invoke_buf_start.argtypes = [ctypes.POINTER(union_remote_arg64), uint32_t] -except AttributeError: - pass -try: - smq_phy_page_start = _libraries['FIXME_STUB'].smq_phy_page_start - smq_phy_page_start.restype = ctypes.POINTER(struct_smq_phy_page) - smq_phy_page_start.argtypes = [uint32_t, ctypes.POINTER(struct_smq_invoke_buf)] -except AttributeError: - pass -REMOTE_DEFAULT_H = True # macro -def REMOTE_SCALARS_METHOD_ATTR(dwScalars): # macro - return (((dwScalars)>>29)&0x7) -def REMOTE_SCALARS_METHOD(dwScalars): # macro - return (((dwScalars)>>24)&0x1f) -def __QAIC_REMOTE(ff): # macro - return ff -__QAIC_REMOTE_EXPORT = True # macro -__QAIC_REMOTE_ATTRIBUTE = True # macro -NUM_DOMAINS = 4 # macro -NUM_SESSIONS = 2 # macro -DOMAIN_ID_MASK = 3 # macro -DEFAULT_DOMAIN_ID = 0 # macro -ADSP_DOMAIN_ID = 0 # macro -MDSP_DOMAIN_ID = 1 # macro -SDSP_DOMAIN_ID = 2 # macro -CDSP_DOMAIN_ID = 3 # macro -ADSP_DOMAIN = "&_dom=adsp" # macro -MDSP_DOMAIN = "&_dom=mdsp" # macro -SDSP_DOMAIN = "&_dom=sdsp" # macro -CDSP_DOMAIN = "&_dom=cdsp" # macro -FASTRPC_WAKELOCK_CONTROL_SUPPORTED = 1 # macro -REMOTE_MODE_PARALLEL = 0 # macro -REMOTE_MODE_SERIAL = 1 # macro -# ITRANSPORT_PREFIX = "'\":;./\\" # macro -remote_handle = ctypes.c_uint32 -remote_handle64 = ctypes.c_uint64 -fastrpc_async_jobid = ctypes.c_uint64 -class struct_c__SA_remote_buf(Structure): - pass - -struct_c__SA_remote_buf._pack_ = 1 # source:False -struct_c__SA_remote_buf._fields_ = [ - ('pv', ctypes.POINTER(None)), - ('nLen', ctypes.c_uint64), -] - -remote_buf = struct_c__SA_remote_buf -class struct_c__SA_remote_dma_handle(Structure): - pass - -struct_c__SA_remote_dma_handle._pack_ = 1 # source:False -struct_c__SA_remote_dma_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), -] - -remote_dma_handle = struct_c__SA_remote_dma_handle -class union_c__UA_remote_arg(Union): - pass - -union_c__UA_remote_arg._pack_ = 1 # source:False -union_c__UA_remote_arg._fields_ = [ - ('buf', remote_buf), - ('h', ctypes.c_uint32), - ('h64', ctypes.c_uint64), - ('dma', remote_dma_handle), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -remote_arg = union_c__UA_remote_arg -remote_arg_t = remote_arg # macro - -# values for enumeration 'fastrpc_async_notify_type' -fastrpc_async_notify_type__enumvalues = { - 0: 'FASTRPC_ASYNC_NO_SYNC', - 1: 'FASTRPC_ASYNC_CALLBACK', - 2: 'FASTRPC_ASYNC_POLL', - 3: 'FASTRPC_ASYNC_TYPE_MAX', -} -FASTRPC_ASYNC_NO_SYNC = 0 -FASTRPC_ASYNC_CALLBACK = 1 -FASTRPC_ASYNC_POLL = 2 -FASTRPC_ASYNC_TYPE_MAX = 3 -fastrpc_async_notify_type = ctypes.c_uint32 # enum -class struct_fastrpc_async_callback(Structure): - pass - -struct_fastrpc_async_callback._pack_ = 1 # source:False -struct_fastrpc_async_callback._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_int32)), - ('context', ctypes.POINTER(None)), -] - -fastrpc_async_callback_t = struct_fastrpc_async_callback -class struct_fastrpc_async_descriptor(Structure): - pass - -class union_fastrpc_async_descriptor_0(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('cb', fastrpc_async_callback_t), - ] - -struct_fastrpc_async_descriptor._pack_ = 1 # source:False -struct_fastrpc_async_descriptor._anonymous_ = ('_0',) -struct_fastrpc_async_descriptor._fields_ = [ - ('type', fastrpc_async_notify_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('jobid', ctypes.c_uint64), - ('_0', union_fastrpc_async_descriptor_0), -] - -fastrpc_async_descriptor_t = struct_fastrpc_async_descriptor - -# values for enumeration 'fastrpc_process_type' -fastrpc_process_type__enumvalues = { - 0: 'PROCESS_TYPE_SIGNED', - 1: 'PROCESS_TYPE_UNSIGNED', -} -PROCESS_TYPE_SIGNED = 0 -PROCESS_TYPE_UNSIGNED = 1 -fastrpc_process_type = ctypes.c_uint32 # enum -try: - remote_handle_open = _libraries['FIXME_STUB'].remote_handle_open - remote_handle_open.restype = ctypes.c_int32 - remote_handle_open.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - remote_handle64_open = _libraries['FIXME_STUB'].remote_handle64_open - remote_handle64_open.restype = ctypes.c_int32 - remote_handle64_open.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - remote_handle_invoke = _libraries['FIXME_STUB'].remote_handle_invoke - remote_handle_invoke.restype = ctypes.c_int32 - remote_handle_invoke.argtypes = [remote_handle, uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle64_invoke = _libraries['FIXME_STUB'].remote_handle64_invoke - remote_handle64_invoke.restype = ctypes.c_int32 - remote_handle64_invoke.argtypes = [remote_handle64, uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle_invoke_async = _libraries['FIXME_STUB'].remote_handle_invoke_async - remote_handle_invoke_async.restype = ctypes.c_int32 - remote_handle_invoke_async.argtypes = [remote_handle, ctypes.POINTER(struct_fastrpc_async_descriptor), uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle64_invoke_async = _libraries['FIXME_STUB'].remote_handle64_invoke_async - remote_handle64_invoke_async.restype = ctypes.c_int32 - remote_handle64_invoke_async.argtypes = [remote_handle64, ctypes.POINTER(struct_fastrpc_async_descriptor), uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle_close = _libraries['FIXME_STUB'].remote_handle_close - remote_handle_close.restype = ctypes.c_int32 - remote_handle_close.argtypes = [remote_handle] -except AttributeError: - pass -try: - remote_handle64_close = _libraries['FIXME_STUB'].remote_handle64_close - remote_handle64_close.restype = ctypes.c_int32 - remote_handle64_close.argtypes = [remote_handle64] -except AttributeError: - pass - -# values for enumeration 'handle_control_req_id' -handle_control_req_id__enumvalues = { - 1: 'DSPRPC_CONTROL_LATENCY', - 2: 'DSPRPC_GET_DSP_INFO', - 3: 'DSPRPC_CONTROL_WAKELOCK', - 4: 'DSPRPC_GET_DOMAIN', -} -DSPRPC_CONTROL_LATENCY = 1 -DSPRPC_GET_DSP_INFO = 2 -DSPRPC_CONTROL_WAKELOCK = 3 -DSPRPC_GET_DOMAIN = 4 -handle_control_req_id = ctypes.c_uint32 # enum - -# values for enumeration 'remote_rpc_latency_flags' -remote_rpc_latency_flags__enumvalues = { - 0: 'RPC_DISABLE_QOS', - 1: 'RPC_PM_QOS', - 2: 'RPC_ADAPTIVE_QOS', - 3: 'RPC_POLL_QOS', -} -RPC_DISABLE_QOS = 0 -RPC_PM_QOS = 1 -RPC_ADAPTIVE_QOS = 2 -RPC_POLL_QOS = 3 -remote_rpc_latency_flags = ctypes.c_uint32 # enum -remote_rpc_control_latency_t = remote_rpc_latency_flags -remote_rpc_control_latency_t__enumvalues = remote_rpc_latency_flags__enumvalues -class struct_remote_rpc_control_latency(Structure): - pass - -struct_remote_rpc_control_latency._pack_ = 1 # source:False -struct_remote_rpc_control_latency._fields_ = [ - ('enable', remote_rpc_control_latency_t), - ('latency', ctypes.c_uint32), -] - - -# values for enumeration 'remote_dsp_attributes' -remote_dsp_attributes__enumvalues = { - 0: 'DOMAIN_SUPPORT', - 1: 'UNSIGNED_PD_SUPPORT', - 2: 'HVX_SUPPORT_64B', - 3: 'HVX_SUPPORT_128B', - 4: 'VTCM_PAGE', - 5: 'VTCM_COUNT', - 6: 'ARCH_VER', - 7: 'HMX_SUPPORT_DEPTH', - 8: 'HMX_SUPPORT_SPATIAL', - 9: 'ASYNC_FASTRPC_SUPPORT', - 10: 'STATUS_NOTIFICATION_SUPPORT', - 11: 'FASTRPC_MAX_DSP_ATTRIBUTES', -} -DOMAIN_SUPPORT = 0 -UNSIGNED_PD_SUPPORT = 1 -HVX_SUPPORT_64B = 2 -HVX_SUPPORT_128B = 3 -VTCM_PAGE = 4 -VTCM_COUNT = 5 -ARCH_VER = 6 -HMX_SUPPORT_DEPTH = 7 -HMX_SUPPORT_SPATIAL = 8 -ASYNC_FASTRPC_SUPPORT = 9 -STATUS_NOTIFICATION_SUPPORT = 10 -FASTRPC_MAX_DSP_ATTRIBUTES = 11 -remote_dsp_attributes = ctypes.c_uint32 # enum -class struct_remote_dsp_capability(Structure): - pass - -struct_remote_dsp_capability._pack_ = 1 # source:False -struct_remote_dsp_capability._fields_ = [ - ('domain', ctypes.c_uint32), - ('attribute_ID', ctypes.c_uint32), - ('capability', ctypes.c_uint32), -] - -fastrpc_capability = struct_remote_dsp_capability -class struct_remote_rpc_control_wakelock(Structure): - pass - -struct_remote_rpc_control_wakelock._pack_ = 1 # source:False -struct_remote_rpc_control_wakelock._fields_ = [ - ('enable', ctypes.c_uint32), -] - -class struct_remote_rpc_get_domain(Structure): - pass - -struct_remote_rpc_get_domain._pack_ = 1 # source:False -struct_remote_rpc_get_domain._fields_ = [ - ('domain', ctypes.c_int32), -] - -remote_rpc_get_domain_t = struct_remote_rpc_get_domain -try: - remote_handle_control = _libraries['FIXME_STUB'].remote_handle_control - remote_handle_control.restype = ctypes.c_int32 - remote_handle_control.argtypes = [uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass -try: - remote_handle64_control = _libraries['FIXME_STUB'].remote_handle64_control - remote_handle64_control.restype = ctypes.c_int32 - remote_handle64_control.argtypes = [remote_handle64, uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass - -# values for enumeration 'session_control_req_id' -session_control_req_id__enumvalues = { - 1: 'FASTRPC_THREAD_PARAMS', - 2: 'DSPRPC_CONTROL_UNSIGNED_MODULE', - 4: 'FASTRPC_RELATIVE_THREAD_PRIORITY', - 6: 'FASTRPC_REMOTE_PROCESS_KILL', - 7: 'FASTRPC_SESSION_CLOSE', - 8: 'FASTRPC_CONTROL_PD_DUMP', - 9: 'FASTRPC_REMOTE_PROCESS_EXCEPTION', - 10: 'FASTRPC_REMOTE_PROCESS_TYPE', - 11: 'FASTRPC_REGISTER_STATUS_NOTIFICATIONS', -} -FASTRPC_THREAD_PARAMS = 1 -DSPRPC_CONTROL_UNSIGNED_MODULE = 2 -FASTRPC_RELATIVE_THREAD_PRIORITY = 4 -FASTRPC_REMOTE_PROCESS_KILL = 6 -FASTRPC_SESSION_CLOSE = 7 -FASTRPC_CONTROL_PD_DUMP = 8 -FASTRPC_REMOTE_PROCESS_EXCEPTION = 9 -FASTRPC_REMOTE_PROCESS_TYPE = 10 -FASTRPC_REGISTER_STATUS_NOTIFICATIONS = 11 -session_control_req_id = ctypes.c_uint32 # enum -class struct_remote_rpc_thread_params(Structure): - pass - -struct_remote_rpc_thread_params._pack_ = 1 # source:False -struct_remote_rpc_thread_params._fields_ = [ - ('domain', ctypes.c_int32), - ('prio', ctypes.c_int32), - ('stack_size', ctypes.c_int32), -] - -class struct_remote_rpc_control_unsigned_module(Structure): - pass - -struct_remote_rpc_control_unsigned_module._pack_ = 1 # source:False -struct_remote_rpc_control_unsigned_module._fields_ = [ - ('domain', ctypes.c_int32), - ('enable', ctypes.c_int32), -] - -class struct_remote_rpc_relative_thread_priority(Structure): - pass - -struct_remote_rpc_relative_thread_priority._pack_ = 1 # source:False -struct_remote_rpc_relative_thread_priority._fields_ = [ - ('domain', ctypes.c_int32), - ('relative_thread_priority', ctypes.c_int32), -] - -class struct_remote_rpc_process_clean_params(Structure): - pass - -struct_remote_rpc_process_clean_params._pack_ = 1 # source:False -struct_remote_rpc_process_clean_params._fields_ = [ - ('domain', ctypes.c_int32), -] - -class struct_remote_rpc_session_close(Structure): - pass - -struct_remote_rpc_session_close._pack_ = 1 # source:False -struct_remote_rpc_session_close._fields_ = [ - ('domain', ctypes.c_int32), -] - -class struct_remote_rpc_control_pd_dump(Structure): - pass - -struct_remote_rpc_control_pd_dump._pack_ = 1 # source:False -struct_remote_rpc_control_pd_dump._fields_ = [ - ('domain', ctypes.c_int32), - ('enable', ctypes.c_int32), -] - -class struct_remote_process_type(Structure): - pass - -struct_remote_process_type._pack_ = 1 # source:False -struct_remote_process_type._fields_ = [ - ('domain', ctypes.c_int32), - ('process_type', ctypes.c_int32), -] - -remote_rpc_process_exception = struct_remote_rpc_process_clean_params - -# values for enumeration 'remote_rpc_status_flags' -remote_rpc_status_flags__enumvalues = { - 0: 'FASTRPC_USER_PD_UP', - 1: 'FASTRPC_USER_PD_EXIT', - 2: 'FASTRPC_USER_PD_FORCE_KILL', - 3: 'FASTRPC_USER_PD_EXCEPTION', - 4: 'FASTRPC_DSP_SSR', -} -FASTRPC_USER_PD_UP = 0 -FASTRPC_USER_PD_EXIT = 1 -FASTRPC_USER_PD_FORCE_KILL = 2 -FASTRPC_USER_PD_EXCEPTION = 3 -FASTRPC_DSP_SSR = 4 -remote_rpc_status_flags = ctypes.c_uint32 # enum -remote_rpc_status_flags_t = remote_rpc_status_flags -remote_rpc_status_flags_t__enumvalues = remote_rpc_status_flags__enumvalues -fastrpc_notif_fn_t = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, remote_rpc_status_flags) -class struct_remote_rpc_notif_register(Structure): - pass - -struct_remote_rpc_notif_register._pack_ = 1 # source:False -struct_remote_rpc_notif_register._fields_ = [ - ('context', ctypes.POINTER(None)), - ('domain', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('notifier_fn', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, remote_rpc_status_flags)), -] - -remote_rpc_notif_register_t = struct_remote_rpc_notif_register -try: - remote_session_control = _libraries['FIXME_STUB'].remote_session_control - remote_session_control.restype = ctypes.c_int32 - remote_session_control.argtypes = [uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass -try: - remote_mmap = _libraries['FIXME_STUB'].remote_mmap - remote_mmap.restype = ctypes.c_int32 - remote_mmap.argtypes = [ctypes.c_int32, uint32_t, uint32_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - remote_munmap = _libraries['FIXME_STUB'].remote_munmap - remote_munmap.restype = ctypes.c_int32 - remote_munmap.argtypes = [uint32_t, ctypes.c_int32] -except AttributeError: - pass - -# values for enumeration 'remote_mem_map_flags' -remote_mem_map_flags__enumvalues = { - 0: 'REMOTE_MAP_MEM_STATIC', - 1: 'REMOTE_MAP_MAX_FLAG', -} -REMOTE_MAP_MEM_STATIC = 0 -REMOTE_MAP_MAX_FLAG = 1 -remote_mem_map_flags = ctypes.c_uint32 # enum -uint64_t = ctypes.c_uint64 -size_t = ctypes.c_uint64 -try: - remote_mem_map = _libraries['FIXME_STUB'].remote_mem_map - remote_mem_map.restype = ctypes.c_int32 - remote_mem_map.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, uint64_t, size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - remote_mem_unmap = _libraries['FIXME_STUB'].remote_mem_unmap - remote_mem_unmap.restype = ctypes.c_int32 - remote_mem_unmap.argtypes = [ctypes.c_int32, uint64_t, size_t] -except AttributeError: - pass - -# values for enumeration 'remote_buf_attributes' -remote_buf_attributes__enumvalues = { - 2: 'FASTRPC_ATTR_NON_COHERENT', - 4: 'FASTRPC_ATTR_COHERENT', - 8: 'FASTRPC_ATTR_KEEP_MAP', - 16: 'FASTRPC_ATTR_NOMAP', - 32: 'FASTRPC_ATTR_FORCE_NOFLUSH', - 64: 'FASTRPC_ATTR_FORCE_NOINVALIDATE', - 128: 'FASTRPC_ATTR_TRY_MAP_STATIC', -} -FASTRPC_ATTR_NON_COHERENT = 2 -FASTRPC_ATTR_COHERENT = 4 -FASTRPC_ATTR_KEEP_MAP = 8 -FASTRPC_ATTR_NOMAP = 16 -FASTRPC_ATTR_FORCE_NOFLUSH = 32 -FASTRPC_ATTR_FORCE_NOINVALIDATE = 64 -FASTRPC_ATTR_TRY_MAP_STATIC = 128 -remote_buf_attributes = ctypes.c_uint32 # enum -try: - remote_register_buf_attr = _libraries['FIXME_STUB'].remote_register_buf_attr - remote_register_buf_attr.restype = None - remote_register_buf_attr.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - remote_register_buf = _libraries['FIXME_STUB'].remote_register_buf - remote_register_buf.restype = None - remote_register_buf.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - remote_register_dma_handle_attr = _libraries['FIXME_STUB'].remote_register_dma_handle_attr - remote_register_dma_handle_attr.restype = ctypes.c_int32 - remote_register_dma_handle_attr.argtypes = [ctypes.c_int32, uint32_t, uint32_t] -except AttributeError: - pass -try: - remote_register_dma_handle = _libraries['FIXME_STUB'].remote_register_dma_handle - remote_register_dma_handle.restype = ctypes.c_int32 - remote_register_dma_handle.argtypes = [ctypes.c_int32, uint32_t] -except AttributeError: - pass -try: - remote_register_fd = _libraries['FIXME_STUB'].remote_register_fd - remote_register_fd.restype = ctypes.POINTER(None) - remote_register_fd.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - fastrpc_async_get_status = _libraries['FIXME_STUB'].fastrpc_async_get_status - fastrpc_async_get_status.restype = ctypes.c_int32 - fastrpc_async_get_status.argtypes = [fastrpc_async_jobid, ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - fastrpc_release_async_job = _libraries['FIXME_STUB'].fastrpc_release_async_job - fastrpc_release_async_job.restype = ctypes.c_int32 - fastrpc_release_async_job.argtypes = [fastrpc_async_jobid] -except AttributeError: - pass -try: - remote_set_mode = _libraries['FIXME_STUB'].remote_set_mode - remote_set_mode.restype = ctypes.c_int32 - remote_set_mode.argtypes = [uint32_t] -except AttributeError: - pass - -# values for enumeration 'fastrpc_map_flags' -fastrpc_map_flags__enumvalues = { - 0: 'FASTRPC_MAP_STATIC', - 1: 'FASTRPC_MAP_RESERVED', - 2: 'FASTRPC_MAP_FD', - 3: 'FASTRPC_MAP_FD_DELAYED', - 4: 'FASTRPC_MAP_MAX', -} -FASTRPC_MAP_STATIC = 0 -FASTRPC_MAP_RESERVED = 1 -FASTRPC_MAP_FD = 2 -FASTRPC_MAP_FD_DELAYED = 3 -FASTRPC_MAP_MAX = 4 -fastrpc_map_flags = ctypes.c_uint32 # enum -try: - fastrpc_mmap = _libraries['FIXME_STUB'].fastrpc_mmap - fastrpc_mmap.restype = ctypes.c_int32 - fastrpc_mmap.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t, fastrpc_map_flags] -except AttributeError: - pass -try: - fastrpc_munmap = _libraries['FIXME_STUB'].fastrpc_munmap - fastrpc_munmap.restype = ctypes.c_int32 - fastrpc_munmap.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), size_t] -except AttributeError: - pass -_APPS_STD_H = True # macro -def __QAIC_HEADER(ff): # macro - return ff -__QAIC_HEADER_EXPORT = True # macro -__QAIC_HEADER_ATTRIBUTE = True # macro -def __QAIC_IMPL(ff): # macro - return ff -__QAIC_IMPL_EXPORT = True # macro -__QAIC_IMPL_ATTRIBUTE = True # macro -__QAIC_STRING1_OBJECT_DEFINED__ = True # macro -__STRING1_OBJECT__ = True # macro -class struct__cstring1_s(Structure): - pass - -struct__cstring1_s._pack_ = 1 # source:False -struct__cstring1_s._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_char)), - ('dataLen', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -_cstring1_t = struct__cstring1_s -apps_std_FILE = ctypes.c_int32 - -# values for enumeration 'apps_std_SEEK' -apps_std_SEEK__enumvalues = { - 0: 'APPS_STD_SEEK_SET', - 1: 'APPS_STD_SEEK_CUR', - 2: 'APPS_STD_SEEK_END', - 2147483647: '_32BIT_PLACEHOLDER_apps_std_SEEK', -} -APPS_STD_SEEK_SET = 0 -APPS_STD_SEEK_CUR = 1 -APPS_STD_SEEK_END = 2 -_32BIT_PLACEHOLDER_apps_std_SEEK = 2147483647 -apps_std_SEEK = ctypes.c_uint32 # enum -class struct_apps_std_DIR(Structure): - pass - -struct_apps_std_DIR._pack_ = 1 # source:False -struct_apps_std_DIR._fields_ = [ - ('handle', ctypes.c_uint64), -] - -apps_std_DIR = struct_apps_std_DIR -class struct_apps_std_DIRENT(Structure): - pass - -struct_apps_std_DIRENT._pack_ = 1 # source:False -struct_apps_std_DIRENT._fields_ = [ - ('ino', ctypes.c_int32), - ('name', ctypes.c_char * 255), - ('PADDING_0', ctypes.c_ubyte), -] - -apps_std_DIRENT = struct_apps_std_DIRENT -class struct_apps_std_STAT(Structure): - pass - -struct_apps_std_STAT._pack_ = 1 # source:False -struct_apps_std_STAT._fields_ = [ - ('tsz', ctypes.c_uint64), - ('dev', ctypes.c_uint64), - ('ino', ctypes.c_uint64), - ('mode', ctypes.c_uint32), - ('nlink', ctypes.c_uint32), - ('rdev', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('atime', ctypes.c_int64), - ('atimensec', ctypes.c_int64), - ('mtime', ctypes.c_int64), - ('mtimensec', ctypes.c_int64), - ('ctime', ctypes.c_int64), - ('ctimensec', ctypes.c_int64), -] - -apps_std_STAT = struct_apps_std_STAT -try: - apps_std_fopen = _libraries['FIXME_STUB'].apps_std_fopen - apps_std_fopen.restype = ctypes.c_int32 - apps_std_fopen.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_freopen = _libraries['FIXME_STUB'].apps_std_freopen - apps_std_freopen.restype = ctypes.c_int32 - apps_std_freopen.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fflush = _libraries['FIXME_STUB'].apps_std_fflush - apps_std_fflush.restype = ctypes.c_int32 - apps_std_fflush.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fclose = _libraries['FIXME_STUB'].apps_std_fclose - apps_std_fclose.restype = ctypes.c_int32 - apps_std_fclose.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fread = _libraries['FIXME_STUB'].apps_std_fread - apps_std_fread.restype = ctypes.c_int32 - apps_std_fread.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fwrite = _libraries['FIXME_STUB'].apps_std_fwrite - apps_std_fwrite.restype = ctypes.c_int32 - apps_std_fwrite.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fgetpos = _libraries['FIXME_STUB'].apps_std_fgetpos - apps_std_fgetpos.restype = ctypes.c_int32 - apps_std_fgetpos.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fsetpos = _libraries['FIXME_STUB'].apps_std_fsetpos - apps_std_fsetpos.restype = ctypes.c_int32 - apps_std_fsetpos.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_ftell = _libraries['FIXME_STUB'].apps_std_ftell - apps_std_ftell.restype = ctypes.c_int32 - apps_std_ftell.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fseek = _libraries['FIXME_STUB'].apps_std_fseek - apps_std_fseek.restype = ctypes.c_int32 - apps_std_fseek.argtypes = [apps_std_FILE, ctypes.c_int32, apps_std_SEEK] -except AttributeError: - pass -try: - apps_std_flen = _libraries['FIXME_STUB'].apps_std_flen - apps_std_flen.restype = ctypes.c_int32 - apps_std_flen.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - apps_std_rewind = _libraries['FIXME_STUB'].apps_std_rewind - apps_std_rewind.restype = ctypes.c_int32 - apps_std_rewind.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_feof = _libraries['FIXME_STUB'].apps_std_feof - apps_std_feof.restype = ctypes.c_int32 - apps_std_feof.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_ferror = _libraries['FIXME_STUB'].apps_std_ferror - apps_std_ferror.restype = ctypes.c_int32 - apps_std_ferror.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_clearerr = _libraries['FIXME_STUB'].apps_std_clearerr - apps_std_clearerr.restype = ctypes.c_int32 - apps_std_clearerr.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_print_string = _libraries['FIXME_STUB'].apps_std_print_string - apps_std_print_string.restype = ctypes.c_int32 - apps_std_print_string.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_getenv = _libraries['FIXME_STUB'].apps_std_getenv - apps_std_getenv.restype = ctypes.c_int32 - apps_std_getenv.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_setenv = _libraries['FIXME_STUB'].apps_std_setenv - apps_std_setenv.restype = ctypes.c_int32 - apps_std_setenv.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_unsetenv = _libraries['FIXME_STUB'].apps_std_unsetenv - apps_std_unsetenv.restype = ctypes.c_int32 - apps_std_unsetenv.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_fopen_with_env = _libraries['FIXME_STUB'].apps_std_fopen_with_env - apps_std_fopen_with_env.restype = ctypes.c_int32 - apps_std_fopen_with_env.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fgets = _libraries['FIXME_STUB'].apps_std_fgets - apps_std_fgets.restype = ctypes.c_int32 - apps_std_fgets.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_get_search_paths_with_env = _libraries['FIXME_STUB'].apps_std_get_search_paths_with_env - apps_std_get_search_paths_with_env.restype = ctypes.c_int32 - apps_std_get_search_paths_with_env.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct__cstring1_s), ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -try: - apps_std_fileExists = _libraries['FIXME_STUB'].apps_std_fileExists - apps_std_fileExists.restype = ctypes.c_int32 - apps_std_fileExists.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_ubyte)] -except AttributeError: - pass -try: - apps_std_fsync = _libraries['FIXME_STUB'].apps_std_fsync - apps_std_fsync.restype = ctypes.c_int32 - apps_std_fsync.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fremove = _libraries['FIXME_STUB'].apps_std_fremove - apps_std_fremove.restype = ctypes.c_int32 - apps_std_fremove.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_fdopen_decrypt = _libraries['FIXME_STUB'].apps_std_fdopen_decrypt - apps_std_fdopen_decrypt.restype = ctypes.c_int32 - apps_std_fdopen_decrypt.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_opendir = _libraries['FIXME_STUB'].apps_std_opendir - apps_std_opendir.restype = ctypes.c_int32 - apps_std_opendir.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_apps_std_DIR)] -except AttributeError: - pass -try: - apps_std_closedir = _libraries['FIXME_STUB'].apps_std_closedir - apps_std_closedir.restype = ctypes.c_int32 - apps_std_closedir.argtypes = [ctypes.POINTER(struct_apps_std_DIR)] -except AttributeError: - pass -try: - apps_std_readdir = _libraries['FIXME_STUB'].apps_std_readdir - apps_std_readdir.restype = ctypes.c_int32 - apps_std_readdir.argtypes = [ctypes.POINTER(struct_apps_std_DIR), ctypes.POINTER(struct_apps_std_DIRENT), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_mkdir = _libraries['FIXME_STUB'].apps_std_mkdir - apps_std_mkdir.restype = ctypes.c_int32 - apps_std_mkdir.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_rmdir = _libraries['FIXME_STUB'].apps_std_rmdir - apps_std_rmdir.restype = ctypes.c_int32 - apps_std_rmdir.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_stat = _libraries['FIXME_STUB'].apps_std_stat - apps_std_stat.restype = ctypes.c_int32 - apps_std_stat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_apps_std_STAT)] -except AttributeError: - pass -try: - apps_std_ftrunc = _libraries['FIXME_STUB'].apps_std_ftrunc - apps_std_ftrunc.restype = ctypes.c_int32 - apps_std_ftrunc.argtypes = [apps_std_FILE, ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_frename = _libraries['FIXME_STUB'].apps_std_frename - apps_std_frename.restype = ctypes.c_int32 - apps_std_frename.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -__all__ = \ - ['ADSPRPC_SHARED_H', 'ADSP_DOMAIN', 'ADSP_DOMAIN_ID', - 'APPS_STD_SEEK_CUR', 'APPS_STD_SEEK_END', 'APPS_STD_SEEK_SET', - 'ARCH_VER', 'ASYNC_FASTRPC_SUPPORT', 'CAMERA_SECURE_CP_USAGE', - 'CDSP_DOMAIN', 'CDSP_DOMAIN_ID', 'DEFAULT_DOMAIN_ID', - 'DEVICE_NAME', 'DISPLAY_SECURE_CP_USAGE', 'DOMAIN_ID_MASK', - 'DOMAIN_SUPPORT', 'DSPRPC_CONTROL_LATENCY', - 'DSPRPC_CONTROL_UNSIGNED_MODULE', 'DSPRPC_CONTROL_WAKELOCK', - 'DSPRPC_GET_DOMAIN', 'DSPRPC_GET_DSP_INFO', - 'FASTRPC_ASYNC_CALLBACK', 'FASTRPC_ASYNC_NO_SYNC', - 'FASTRPC_ASYNC_POLL', 'FASTRPC_ASYNC_TYPE_MAX', - 'FASTRPC_ATTR_COHERENT', 'FASTRPC_ATTR_COHERENT', - 'FASTRPC_ATTR_FORCE_NOFLUSH', 'FASTRPC_ATTR_FORCE_NOINVALIDATE', - 'FASTRPC_ATTR_KEEP_MAP', 'FASTRPC_ATTR_KEEP_MAP', - 'FASTRPC_ATTR_NOMAP', 'FASTRPC_ATTR_NOMAP', - 'FASTRPC_ATTR_NON_COHERENT', 'FASTRPC_ATTR_NON_COHERENT', - 'FASTRPC_ATTR_NOVA', 'FASTRPC_ATTR_TRY_MAP_STATIC', - 'FASTRPC_CONTROL_KALLOC', 'FASTRPC_CONTROL_LATENCY', - 'FASTRPC_CONTROL_PD_DUMP', 'FASTRPC_CONTROL_SMMU', - 'FASTRPC_DSP_SSR', 'FASTRPC_GLINK_GUID', 'FASTRPC_INIT_ATTACH', - 'FASTRPC_INIT_ATTACH_SENSORS', 'FASTRPC_INIT_CREATE', - 'FASTRPC_INIT_CREATE_STATIC', 'FASTRPC_MAP_FD', - 'FASTRPC_MAP_FD_DELAYED', 'FASTRPC_MAP_MAX', - 'FASTRPC_MAP_RESERVED', 'FASTRPC_MAP_STATIC', - 'FASTRPC_MAX_DSP_ATTRIBUTES', 'FASTRPC_MODE_PARALLEL', - 'FASTRPC_MODE_PROFILE', 'FASTRPC_MODE_SERIAL', - 'FASTRPC_MODE_SESSION', 'FASTRPC_REGISTER_STATUS_NOTIFICATIONS', - 'FASTRPC_RELATIVE_THREAD_PRIORITY', - 'FASTRPC_REMOTE_PROCESS_EXCEPTION', 'FASTRPC_REMOTE_PROCESS_KILL', - 'FASTRPC_REMOTE_PROCESS_TYPE', 'FASTRPC_SESSION_CLOSE', - 'FASTRPC_SMD_GUID', 'FASTRPC_THREAD_PARAMS', - 'FASTRPC_USER_PD_EXCEPTION', 'FASTRPC_USER_PD_EXIT', - 'FASTRPC_USER_PD_FORCE_KILL', 'FASTRPC_USER_PD_UP', - 'FASTRPC_WAKELOCK_CONTROL_SUPPORTED', 'FIXED_HIGH', 'FIXED_LOW', - 'FIXED_MIDDLE', 'HMX_SUPPORT_DEPTH', 'HMX_SUPPORT_SPATIAL', - 'HVX_SUPPORT_128B', 'HVX_SUPPORT_64B', 'INVALID_HEAP_ID', - 'ION_ADSP_HEAP_ID', 'ION_ADSP_HEAP_NAME', 'ION_AUDIO_HEAP_ID', - 'ION_AUDIO_HEAP_NAME', 'ION_CAMERA_HEAP_ID', - 'ION_CAMERA_HEAP_NAME', 'ION_CP_MFC_HEAP_ID', 'ION_CP_MM_HEAP_ID', - 'ION_CP_WB_HEAP_ID', 'ION_FLAG_ALLOW_NON_CONTIG', - 'ION_FLAG_CACHED', 'ION_FLAG_CACHED_NEEDS_SYNC', - 'ION_FLAG_CP_APP', 'ION_FLAG_CP_BITSTREAM', 'ION_FLAG_CP_CAMERA', - 'ION_FLAG_CP_HLOS', 'ION_FLAG_CP_HLOS_FREE', - 'ION_FLAG_CP_NON_PIXEL', 'ION_FLAG_CP_PIXEL', - 'ION_FLAG_CP_SEC_DISPLAY', 'ION_FLAG_CP_TOUCH', - 'ION_FLAG_FORCE_CONTIGUOUS', 'ION_FLAG_POOL_FORCE_ALLOC', - 'ION_FLAG_POOL_PREFETCH', 'ION_FLAG_SECURE', - 'ION_FORCE_CONTIGUOUS', 'ION_HEAP_CARVEOUT_MASK', - 'ION_HEAP_ID_RESERVED', 'ION_HEAP_SYSTEM_CONTIG_MASK', - 'ION_HEAP_SYSTEM_MASK', 'ION_HEAP_TYPE_CARVEOUT', - 'ION_HEAP_TYPE_CHUNK', 'ION_HEAP_TYPE_CUSTOM', - 'ION_HEAP_TYPE_DMA', 'ION_HEAP_TYPE_DMA_MASK', - 'ION_HEAP_TYPE_HYP_CMA', 'ION_HEAP_TYPE_IOMMU', - 'ION_HEAP_TYPE_MSM_START', 'ION_HEAP_TYPE_SECURE_DMA', - 'ION_HEAP_TYPE_SYSTEM', 'ION_HEAP_TYPE_SYSTEM_CONTIG', - 'ION_HEAP_TYPE_SYSTEM_SECURE', 'ION_IOC_MAGIC', - 'ION_IOC_MSM_MAGIC', 'ION_IOMMU_HEAP_ID', 'ION_IOMMU_HEAP_NAME', - 'ION_KMALLOC_HEAP_NAME', 'ION_MFC_HEAP_NAME', - 'ION_MM_FIRMWARE_HEAP_ID', 'ION_MM_FIRMWARE_HEAP_NAME', - 'ION_MM_HEAP_NAME', 'ION_NUM_HEAPS', 'ION_PIL1_HEAP_ID', - 'ION_PIL1_HEAP_NAME', 'ION_PIL2_HEAP_ID', 'ION_PIL2_HEAP_NAME', - 'ION_QSECOM_HEAP_ID', 'ION_QSECOM_HEAP_NAME', 'ION_SECURE', - 'ION_SECURE_DISPLAY_HEAP_ID', 'ION_SECURE_DISPLAY_HEAP_NAME', - 'ION_SECURE_HEAP_ID', 'ION_SECURE_HEAP_NAME', 'ION_SF_HEAP_ID', - 'ION_SF_HEAP_NAME', 'ION_SYSTEM_CONTIG_HEAP_ID', - 'ION_SYSTEM_HEAP_ID', 'ION_SYSTEM_HEAP_NAME', - 'ION_VMALLOC_HEAP_NAME', 'ION_WB_HEAP_NAME', 'MAX_USAGE', - 'MDSP_DOMAIN', 'MDSP_DOMAIN_ID', 'NOT_FIXED', 'NUM_DOMAINS', - 'NUM_SESSIONS', 'PROCESS_TYPE_SIGNED', 'PROCESS_TYPE_UNSIGNED', - 'REMOTE_DEFAULT_H', 'REMOTE_MAP_MAX_FLAG', - 'REMOTE_MAP_MEM_STATIC', 'REMOTE_MODE_PARALLEL', - 'REMOTE_MODE_SERIAL', 'RPC_ADAPTIVE_QOS', 'RPC_DISABLE_QOS', - 'RPC_PM_QOS', 'RPC_POLL_QOS', 'SDSP_DOMAIN', 'SDSP_DOMAIN_ID', - 'STATUS_NOTIFICATION_SUPPORT', 'UNKNOWN', 'UNSIGNED_PD_SUPPORT', - 'VIDEO_BITSTREAM', 'VIDEO_NONPIXEL', 'VIDEO_PIXEL', 'VTCM_COUNT', - 'VTCM_PAGE', '_32BIT_PLACEHOLDER_apps_std_SEEK', '_APPS_STD_H', - '_IO', '_IOR', '_IOW', '_IOWR', '_UAPI_LINUX_ION_H', - '_UAPI_MSM_ION_H', '__QAIC_HEADER_ATTRIBUTE', - '__QAIC_HEADER_EXPORT', '__QAIC_IMPL_ATTRIBUTE', - '__QAIC_IMPL_EXPORT', '__QAIC_REMOTE_ATTRIBUTE', - '__QAIC_REMOTE_EXPORT', '__QAIC_STRING1_OBJECT_DEFINED__', - '__STRING1_OBJECT__', '_cstring1_t', 'apps_std_DIR', - 'apps_std_DIRENT', 'apps_std_FILE', 'apps_std_SEEK', - 'apps_std_STAT', 'apps_std_clearerr', 'apps_std_closedir', - 'apps_std_fclose', 'apps_std_fdopen_decrypt', 'apps_std_feof', - 'apps_std_ferror', 'apps_std_fflush', 'apps_std_fgetpos', - 'apps_std_fgets', 'apps_std_fileExists', 'apps_std_flen', - 'apps_std_fopen', 'apps_std_fopen_with_env', 'apps_std_fread', - 'apps_std_fremove', 'apps_std_frename', 'apps_std_freopen', - 'apps_std_fseek', 'apps_std_fsetpos', 'apps_std_fsync', - 'apps_std_ftell', 'apps_std_ftrunc', 'apps_std_fwrite', - 'apps_std_get_search_paths_with_env', 'apps_std_getenv', - 'apps_std_mkdir', 'apps_std_opendir', 'apps_std_print_string', - 'apps_std_readdir', 'apps_std_rewind', 'apps_std_rmdir', - 'apps_std_setenv', 'apps_std_stat', 'apps_std_unsetenv', - 'cp_mem_usage', 'fastrpc_async_callback_t', - 'fastrpc_async_descriptor_t', 'fastrpc_async_get_status', - 'fastrpc_async_jobid', 'fastrpc_async_notify_type', - 'fastrpc_capability', 'fastrpc_map_flags', 'fastrpc_mmap', - 'fastrpc_munmap', 'fastrpc_notif_fn_t', 'fastrpc_process_type', - 'fastrpc_release_async_job', 'handle_control_req_id', - 'ion_fixed_position', 'ion_heap_ids', 'ion_heap_type', - 'ion_user_handle_t', 'msm_ion_heap_types', 'remote_arg', - 'remote_arg_t', 'remote_buf', 'remote_buf_attributes', - 'remote_dma_handle', 'remote_dsp_attributes', 'remote_handle', - 'remote_handle64', 'remote_handle64_close', - 'remote_handle64_control', 'remote_handle64_invoke', - 'remote_handle64_invoke_async', 'remote_handle64_open', - 'remote_handle_close', 'remote_handle_control', - 'remote_handle_invoke', 'remote_handle_invoke_async', - 'remote_handle_open', 'remote_mem_map', 'remote_mem_map_flags', - 'remote_mem_unmap', 'remote_mmap', 'remote_munmap', - 'remote_register_buf', 'remote_register_buf_attr', - 'remote_register_dma_handle', 'remote_register_dma_handle_attr', - 'remote_register_fd', 'remote_rpc_control_latency_t', - 'remote_rpc_control_latency_t__enumvalues', - 'remote_rpc_get_domain_t', 'remote_rpc_latency_flags', - 'remote_rpc_notif_register_t', 'remote_rpc_process_exception', - 'remote_rpc_status_flags', 'remote_rpc_status_flags_t', - 'remote_rpc_status_flags_t__enumvalues', 'remote_session_control', - 'remote_set_mode', 'session_control_req_id', 'size_t', - 'smq_invoke_buf_start', 'smq_phy_page_start', - 'struct__cstring1_s', 'struct_apps_std_DIR', - 'struct_apps_std_DIRENT', 'struct_apps_std_STAT', - 'struct_c__SA_remote_buf', 'struct_c__SA_remote_dma_handle', - 'struct_fastrpc_async_callback', - 'struct_fastrpc_async_descriptor', 'struct_fastrpc_ctrl_kalloc', - 'struct_fastrpc_ctrl_latency', 'struct_fastrpc_ctrl_smmu', - 'struct_fastrpc_ioctl_control', 'struct_fastrpc_ioctl_init', - 'struct_fastrpc_ioctl_init_attrs', 'struct_fastrpc_ioctl_invoke', - 'struct_fastrpc_ioctl_invoke_attrs', - 'struct_fastrpc_ioctl_invoke_crc', - 'struct_fastrpc_ioctl_invoke_fd', 'struct_fastrpc_ioctl_mmap', - 'struct_fastrpc_ioctl_mmap_64', 'struct_fastrpc_ioctl_munmap', - 'struct_fastrpc_ioctl_munmap_64', - 'struct_fastrpc_ioctl_munmap_fd', 'struct_fastrpc_ioctl_perf', - 'struct_ion_allocation_data', 'struct_ion_custom_data', - 'struct_ion_fd_data', 'struct_ion_flush_data', - 'struct_ion_handle_data', 'struct_ion_prefetch_data', - 'struct_ion_prefetch_regions', 'struct_remote_buf', - 'struct_remote_buf64', 'struct_remote_dma_handle', - 'struct_remote_dma_handle64', 'struct_remote_dsp_capability', - 'struct_remote_process_type', 'struct_remote_rpc_control_latency', - 'struct_remote_rpc_control_pd_dump', - 'struct_remote_rpc_control_unsigned_module', - 'struct_remote_rpc_control_wakelock', - 'struct_remote_rpc_get_domain', - 'struct_remote_rpc_notif_register', - 'struct_remote_rpc_process_clean_params', - 'struct_remote_rpc_relative_thread_priority', - 'struct_remote_rpc_session_close', - 'struct_remote_rpc_thread_params', 'struct_smq_invoke', - 'struct_smq_invoke_buf', 'struct_smq_invoke_rsp', - 'struct_smq_msg', 'struct_smq_null_invoke', 'struct_smq_phy_page', - 'uint32_t', 'uint64_t', 'union_c__UA_remote_arg', - 'union_fastrpc_async_descriptor_0', - 'union_fastrpc_ioctl_control_0', 'union_remote_arg', - 'union_remote_arg64'] diff --git a/tinygrad/tinygrad/runtime/autogen/sqtt.py b/tinygrad/tinygrad/runtime/autogen/sqtt.py deleted file mode 100644 index 5d246bff..00000000 --- a/tinygrad/tinygrad/runtime/autogen/sqtt.py +++ /dev/null @@ -1,1789 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -SQTT_FILE_MAGIC_NUMBER = 0x50303042 # macro -SQTT_FILE_VERSION_MAJOR = 1 # macro -SQTT_FILE_VERSION_MINOR = 5 # macro -SQTT_GPU_NAME_MAX_SIZE = 256 # macro -SQTT_MAX_NUM_SE = 32 # macro -SQTT_SA_PER_SE = 2 # macro -SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS = 4 # macro -class struct_sqtt_data_info(Structure): - pass - -class union_sqtt_data_info_0(Union): - pass - -union_sqtt_data_info_0._pack_ = 1 # source:False -union_sqtt_data_info_0._fields_ = [ - ('gfx9_write_counter', ctypes.c_uint32), - ('gfx10_dropped_cntr', ctypes.c_uint32), -] - -struct_sqtt_data_info._pack_ = 1 # source:False -struct_sqtt_data_info._anonymous_ = ('_0',) -struct_sqtt_data_info._fields_ = [ - ('cur_offset', ctypes.c_uint32), - ('trace_status', ctypes.c_uint32), - ('_0', union_sqtt_data_info_0), -] - -class struct_sqtt_data_se(Structure): - pass - -struct_sqtt_data_se._pack_ = 1 # source:False -struct_sqtt_data_se._fields_ = [ - ('info', struct_sqtt_data_info), - ('PADDING_0', ctypes.c_ubyte * 4), - ('data_ptr', ctypes.POINTER(None)), - ('shader_engine', ctypes.c_uint32), - ('compute_unit', ctypes.c_uint32), -] - - -# values for enumeration 'sqtt_version' -sqtt_version__enumvalues = { - 0: 'SQTT_VERSION_NONE', - 5: 'SQTT_VERSION_2_2', - 6: 'SQTT_VERSION_2_3', - 7: 'SQTT_VERSION_2_4', - 11: 'SQTT_VERSION_3_2', -} -SQTT_VERSION_NONE = 0 -SQTT_VERSION_2_2 = 5 -SQTT_VERSION_2_3 = 6 -SQTT_VERSION_2_4 = 7 -SQTT_VERSION_3_2 = 11 -sqtt_version = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_file_chunk_type' -sqtt_file_chunk_type__enumvalues = { - 0: 'SQTT_FILE_CHUNK_TYPE_ASIC_INFO', - 1: 'SQTT_FILE_CHUNK_TYPE_SQTT_DESC', - 2: 'SQTT_FILE_CHUNK_TYPE_SQTT_DATA', - 3: 'SQTT_FILE_CHUNK_TYPE_API_INFO', - 4: 'SQTT_FILE_CHUNK_TYPE_RESERVED', - 5: 'SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS', - 6: 'SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION', - 7: 'SQTT_FILE_CHUNK_TYPE_CPU_INFO', - 8: 'SQTT_FILE_CHUNK_TYPE_SPM_DB', - 9: 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE', - 10: 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS', - 11: 'SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION', - 12: 'SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE', - 13: 'SQTT_FILE_CHUNK_TYPE_COUNT', -} -SQTT_FILE_CHUNK_TYPE_ASIC_INFO = 0 -SQTT_FILE_CHUNK_TYPE_SQTT_DESC = 1 -SQTT_FILE_CHUNK_TYPE_SQTT_DATA = 2 -SQTT_FILE_CHUNK_TYPE_API_INFO = 3 -SQTT_FILE_CHUNK_TYPE_RESERVED = 4 -SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS = 5 -SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION = 6 -SQTT_FILE_CHUNK_TYPE_CPU_INFO = 7 -SQTT_FILE_CHUNK_TYPE_SPM_DB = 8 -SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE = 9 -SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS = 10 -SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION = 11 -SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE = 12 -SQTT_FILE_CHUNK_TYPE_COUNT = 13 -sqtt_file_chunk_type = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_id(Structure): - pass - -struct_sqtt_file_chunk_id._pack_ = 1 # source:False -struct_sqtt_file_chunk_id._fields_ = [ - ('type', ctypes.c_int32, 8), - ('index', ctypes.c_int32, 8), - ('reserved', ctypes.c_int32, 16), -] - -class struct_sqtt_file_chunk_header(Structure): - pass - -struct_sqtt_file_chunk_header._pack_ = 1 # source:False -struct_sqtt_file_chunk_header._fields_ = [ - ('chunk_id', struct_sqtt_file_chunk_id), - ('minor_version', ctypes.c_uint16), - ('major_version', ctypes.c_uint16), - ('size_in_bytes', ctypes.c_int32), - ('padding', ctypes.c_int32), -] - -class struct_sqtt_file_header_flags(Structure): - pass - -class union_sqtt_file_header_flags_0(Union): - pass - -class struct_sqtt_file_header_flags_0_0(Structure): - pass - -struct_sqtt_file_header_flags_0_0._pack_ = 1 # source:False -struct_sqtt_file_header_flags_0_0._fields_ = [ - ('is_semaphore_queue_timing_etw', ctypes.c_uint32, 1), - ('no_queue_semaphore_timestamps', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 30), -] - -union_sqtt_file_header_flags_0._pack_ = 1 # source:False -union_sqtt_file_header_flags_0._anonymous_ = ('_0',) -union_sqtt_file_header_flags_0._fields_ = [ - ('_0', struct_sqtt_file_header_flags_0_0), - ('value', ctypes.c_uint32), -] - -struct_sqtt_file_header_flags._pack_ = 1 # source:False -struct_sqtt_file_header_flags._anonymous_ = ('_0',) -struct_sqtt_file_header_flags._fields_ = [ - ('_0', union_sqtt_file_header_flags_0), -] - -class struct_sqtt_file_header(Structure): - pass - -struct_sqtt_file_header._pack_ = 1 # source:False -struct_sqtt_file_header._fields_ = [ - ('magic_number', ctypes.c_uint32), - ('version_major', ctypes.c_uint32), - ('version_minor', ctypes.c_uint32), - ('flags', struct_sqtt_file_header_flags), - ('chunk_offset', ctypes.c_int32), - ('second', ctypes.c_int32), - ('minute', ctypes.c_int32), - ('hour', ctypes.c_int32), - ('day_in_month', ctypes.c_int32), - ('month', ctypes.c_int32), - ('year', ctypes.c_int32), - ('day_in_week', ctypes.c_int32), - ('day_in_year', ctypes.c_int32), - ('is_daylight_savings', ctypes.c_int32), -] - -class struct_sqtt_file_chunk_cpu_info(Structure): - pass - -struct_sqtt_file_chunk_cpu_info._pack_ = 1 # source:False -struct_sqtt_file_chunk_cpu_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('vendor_id', ctypes.c_uint32 * 4), - ('processor_brand', ctypes.c_uint32 * 12), - ('reserved', ctypes.c_uint32 * 2), - ('cpu_timestamp_freq', ctypes.c_uint64), - ('clock_speed', ctypes.c_uint32), - ('num_logical_cores', ctypes.c_uint32), - ('num_physical_cores', ctypes.c_uint32), - ('system_ram_size', ctypes.c_uint32), -] - - -# values for enumeration 'sqtt_file_chunk_asic_info_flags' -sqtt_file_chunk_asic_info_flags__enumvalues = { - 1: 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING', - 2: 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED', -} -SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING = 1 -SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED = 2 -sqtt_file_chunk_asic_info_flags = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_gpu_type' -sqtt_gpu_type__enumvalues = { - 0: 'SQTT_GPU_TYPE_UNKNOWN', - 1: 'SQTT_GPU_TYPE_INTEGRATED', - 2: 'SQTT_GPU_TYPE_DISCRETE', - 3: 'SQTT_GPU_TYPE_VIRTUAL', -} -SQTT_GPU_TYPE_UNKNOWN = 0 -SQTT_GPU_TYPE_INTEGRATED = 1 -SQTT_GPU_TYPE_DISCRETE = 2 -SQTT_GPU_TYPE_VIRTUAL = 3 -sqtt_gpu_type = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_gfxip_level' -sqtt_gfxip_level__enumvalues = { - 0: 'SQTT_GFXIP_LEVEL_NONE', - 1: 'SQTT_GFXIP_LEVEL_GFXIP_6', - 2: 'SQTT_GFXIP_LEVEL_GFXIP_7', - 3: 'SQTT_GFXIP_LEVEL_GFXIP_8', - 4: 'SQTT_GFXIP_LEVEL_GFXIP_8_1', - 5: 'SQTT_GFXIP_LEVEL_GFXIP_9', - 7: 'SQTT_GFXIP_LEVEL_GFXIP_10_1', - 9: 'SQTT_GFXIP_LEVEL_GFXIP_10_3', - 12: 'SQTT_GFXIP_LEVEL_GFXIP_11_0', -} -SQTT_GFXIP_LEVEL_NONE = 0 -SQTT_GFXIP_LEVEL_GFXIP_6 = 1 -SQTT_GFXIP_LEVEL_GFXIP_7 = 2 -SQTT_GFXIP_LEVEL_GFXIP_8 = 3 -SQTT_GFXIP_LEVEL_GFXIP_8_1 = 4 -SQTT_GFXIP_LEVEL_GFXIP_9 = 5 -SQTT_GFXIP_LEVEL_GFXIP_10_1 = 7 -SQTT_GFXIP_LEVEL_GFXIP_10_3 = 9 -SQTT_GFXIP_LEVEL_GFXIP_11_0 = 12 -sqtt_gfxip_level = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_memory_type' -sqtt_memory_type__enumvalues = { - 0: 'SQTT_MEMORY_TYPE_UNKNOWN', - 1: 'SQTT_MEMORY_TYPE_DDR', - 2: 'SQTT_MEMORY_TYPE_DDR2', - 3: 'SQTT_MEMORY_TYPE_DDR3', - 4: 'SQTT_MEMORY_TYPE_DDR4', - 5: 'SQTT_MEMORY_TYPE_DDR5', - 16: 'SQTT_MEMORY_TYPE_GDDR3', - 17: 'SQTT_MEMORY_TYPE_GDDR4', - 18: 'SQTT_MEMORY_TYPE_GDDR5', - 19: 'SQTT_MEMORY_TYPE_GDDR6', - 32: 'SQTT_MEMORY_TYPE_HBM', - 33: 'SQTT_MEMORY_TYPE_HBM2', - 34: 'SQTT_MEMORY_TYPE_HBM3', - 48: 'SQTT_MEMORY_TYPE_LPDDR4', - 49: 'SQTT_MEMORY_TYPE_LPDDR5', -} -SQTT_MEMORY_TYPE_UNKNOWN = 0 -SQTT_MEMORY_TYPE_DDR = 1 -SQTT_MEMORY_TYPE_DDR2 = 2 -SQTT_MEMORY_TYPE_DDR3 = 3 -SQTT_MEMORY_TYPE_DDR4 = 4 -SQTT_MEMORY_TYPE_DDR5 = 5 -SQTT_MEMORY_TYPE_GDDR3 = 16 -SQTT_MEMORY_TYPE_GDDR4 = 17 -SQTT_MEMORY_TYPE_GDDR5 = 18 -SQTT_MEMORY_TYPE_GDDR6 = 19 -SQTT_MEMORY_TYPE_HBM = 32 -SQTT_MEMORY_TYPE_HBM2 = 33 -SQTT_MEMORY_TYPE_HBM3 = 34 -SQTT_MEMORY_TYPE_LPDDR4 = 48 -SQTT_MEMORY_TYPE_LPDDR5 = 49 -sqtt_memory_type = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_asic_info(Structure): - pass - -struct_sqtt_file_chunk_asic_info._pack_ = 1 # source:False -struct_sqtt_file_chunk_asic_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('flags', ctypes.c_uint64), - ('trace_shader_core_clock', ctypes.c_uint64), - ('trace_memory_clock', ctypes.c_uint64), - ('device_id', ctypes.c_int32), - ('device_revision_id', ctypes.c_int32), - ('vgprs_per_simd', ctypes.c_int32), - ('sgprs_per_simd', ctypes.c_int32), - ('shader_engines', ctypes.c_int32), - ('compute_unit_per_shader_engine', ctypes.c_int32), - ('simd_per_compute_unit', ctypes.c_int32), - ('wavefronts_per_simd', ctypes.c_int32), - ('minimum_vgpr_alloc', ctypes.c_int32), - ('vgpr_alloc_granularity', ctypes.c_int32), - ('minimum_sgpr_alloc', ctypes.c_int32), - ('sgpr_alloc_granularity', ctypes.c_int32), - ('hardware_contexts', ctypes.c_int32), - ('gpu_type', sqtt_gpu_type), - ('gfxip_level', sqtt_gfxip_level), - ('gpu_index', ctypes.c_int32), - ('gds_size', ctypes.c_int32), - ('gds_per_shader_engine', ctypes.c_int32), - ('ce_ram_size', ctypes.c_int32), - ('ce_ram_size_graphics', ctypes.c_int32), - ('ce_ram_size_compute', ctypes.c_int32), - ('max_number_of_dedicated_cus', ctypes.c_int32), - ('vram_size', ctypes.c_int64), - ('vram_bus_width', ctypes.c_int32), - ('l2_cache_size', ctypes.c_int32), - ('l1_cache_size', ctypes.c_int32), - ('lds_size', ctypes.c_int32), - ('gpu_name', ctypes.c_char * 256), - ('alu_per_clock', ctypes.c_float), - ('texture_per_clock', ctypes.c_float), - ('prims_per_clock', ctypes.c_float), - ('pixels_per_clock', ctypes.c_float), - ('gpu_timestamp_frequency', ctypes.c_uint64), - ('max_shader_core_clock', ctypes.c_uint64), - ('max_memory_clock', ctypes.c_uint64), - ('memory_ops_per_clock', ctypes.c_uint32), - ('memory_chip_type', sqtt_memory_type), - ('lds_granularity', ctypes.c_uint32), - ('cu_mask', ctypes.c_uint16 * 2 * 32), - ('reserved1', ctypes.c_char * 128), - ('active_pixel_packer_mask', ctypes.c_uint32 * 4), - ('reserved2', ctypes.c_char * 16), - ('gl1_cache_size', ctypes.c_uint32), - ('instruction_cache_size', ctypes.c_uint32), - ('scalar_cache_size', ctypes.c_uint32), - ('mall_cache_size', ctypes.c_uint32), - ('padding', ctypes.c_char * 4), -] - - -# values for enumeration 'sqtt_api_type' -sqtt_api_type__enumvalues = { - 0: 'SQTT_API_TYPE_DIRECTX_12', - 1: 'SQTT_API_TYPE_VULKAN', - 2: 'SQTT_API_TYPE_GENERIC', - 3: 'SQTT_API_TYPE_OPENCL', -} -SQTT_API_TYPE_DIRECTX_12 = 0 -SQTT_API_TYPE_VULKAN = 1 -SQTT_API_TYPE_GENERIC = 2 -SQTT_API_TYPE_OPENCL = 3 -sqtt_api_type = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_instruction_trace_mode' -sqtt_instruction_trace_mode__enumvalues = { - 0: 'SQTT_INSTRUCTION_TRACE_DISABLED', - 1: 'SQTT_INSTRUCTION_TRACE_FULL_FRAME', - 2: 'SQTT_INSTRUCTION_TRACE_API_PSO', -} -SQTT_INSTRUCTION_TRACE_DISABLED = 0 -SQTT_INSTRUCTION_TRACE_FULL_FRAME = 1 -SQTT_INSTRUCTION_TRACE_API_PSO = 2 -sqtt_instruction_trace_mode = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_profiling_mode' -sqtt_profiling_mode__enumvalues = { - 0: 'SQTT_PROFILING_MODE_PRESENT', - 1: 'SQTT_PROFILING_MODE_USER_MARKERS', - 2: 'SQTT_PROFILING_MODE_INDEX', - 3: 'SQTT_PROFILING_MODE_TAG', -} -SQTT_PROFILING_MODE_PRESENT = 0 -SQTT_PROFILING_MODE_USER_MARKERS = 1 -SQTT_PROFILING_MODE_INDEX = 2 -SQTT_PROFILING_MODE_TAG = 3 -sqtt_profiling_mode = ctypes.c_uint32 # enum -class union_sqtt_profiling_mode_data(Union): - pass - -class struct_sqtt_profiling_mode_data_user_marker_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_user_marker_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_user_marker_profiling_data._fields_ = [ - ('start', ctypes.c_char * 256), - ('end', ctypes.c_char * 256), -] - -class struct_sqtt_profiling_mode_data_index_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_index_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_index_profiling_data._fields_ = [ - ('start', ctypes.c_uint32), - ('end', ctypes.c_uint32), -] - -class struct_sqtt_profiling_mode_data_tag_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_tag_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_tag_profiling_data._fields_ = [ - ('begin_hi', ctypes.c_uint32), - ('begin_lo', ctypes.c_uint32), - ('end_hi', ctypes.c_uint32), - ('end_lo', ctypes.c_uint32), -] - -union_sqtt_profiling_mode_data._pack_ = 1 # source:False -union_sqtt_profiling_mode_data._fields_ = [ - ('user_marker_profiling_data', struct_sqtt_profiling_mode_data_user_marker_profiling_data), - ('index_profiling_data', struct_sqtt_profiling_mode_data_index_profiling_data), - ('tag_profiling_data', struct_sqtt_profiling_mode_data_tag_profiling_data), - ('PADDING_0', ctypes.c_ubyte * 496), -] - -class union_sqtt_instruction_trace_data(Union): - pass - -class struct_sqtt_instruction_trace_data_api_pso_data(Structure): - pass - -struct_sqtt_instruction_trace_data_api_pso_data._pack_ = 1 # source:False -struct_sqtt_instruction_trace_data_api_pso_data._fields_ = [ - ('api_pso_filter', ctypes.c_uint64), -] - -class struct_sqtt_instruction_trace_data_shader_engine_filter(Structure): - pass - -struct_sqtt_instruction_trace_data_shader_engine_filter._pack_ = 1 # source:False -struct_sqtt_instruction_trace_data_shader_engine_filter._fields_ = [ - ('mask', ctypes.c_uint32), -] - -union_sqtt_instruction_trace_data._pack_ = 1 # source:False -union_sqtt_instruction_trace_data._fields_ = [ - ('api_pso_data', struct_sqtt_instruction_trace_data_api_pso_data), - ('shader_engine_filter', struct_sqtt_instruction_trace_data_shader_engine_filter), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_sqtt_file_chunk_api_info(Structure): - pass - -struct_sqtt_file_chunk_api_info._pack_ = 1 # source:False -struct_sqtt_file_chunk_api_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('api_type', sqtt_api_type), - ('major_version', ctypes.c_uint16), - ('minor_version', ctypes.c_uint16), - ('profiling_mode', sqtt_profiling_mode), - ('reserved', ctypes.c_uint32), - ('profiling_mode_data', union_sqtt_profiling_mode_data), - ('instruction_trace_mode', sqtt_instruction_trace_mode), - ('reserved2', ctypes.c_uint32), - ('instruction_trace_data', union_sqtt_instruction_trace_data), -] - -class struct_sqtt_code_object_database_record(Structure): - pass - -struct_sqtt_code_object_database_record._pack_ = 1 # source:False -struct_sqtt_code_object_database_record._fields_ = [ - ('size', ctypes.c_uint32), -] - -class struct_sqtt_file_chunk_code_object_database(Structure): - pass - -struct_sqtt_file_chunk_code_object_database._pack_ = 1 # source:False -struct_sqtt_file_chunk_code_object_database._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), -] - -class struct_sqtt_code_object_loader_events_record(Structure): - pass - -struct_sqtt_code_object_loader_events_record._pack_ = 1 # source:False -struct_sqtt_code_object_loader_events_record._fields_ = [ - ('loader_event_type', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('base_address', ctypes.c_uint64), - ('code_object_hash', ctypes.c_uint64 * 2), - ('time_stamp', ctypes.c_uint64), -] - -class struct_sqtt_file_chunk_code_object_loader_events(Structure): - pass - -struct_sqtt_file_chunk_code_object_loader_events._pack_ = 1 # source:False -struct_sqtt_file_chunk_code_object_loader_events._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('record_size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), -] - -class struct_sqtt_pso_correlation_record(Structure): - pass - -struct_sqtt_pso_correlation_record._pack_ = 1 # source:False -struct_sqtt_pso_correlation_record._fields_ = [ - ('api_pso_hash', ctypes.c_uint64), - ('pipeline_hash', ctypes.c_uint64 * 2), - ('api_level_obj_name', ctypes.c_char * 64), -] - -class struct_sqtt_file_chunk_pso_correlation(Structure): - pass - -struct_sqtt_file_chunk_pso_correlation._pack_ = 1 # source:False -struct_sqtt_file_chunk_pso_correlation._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('record_size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), -] - -class struct_sqtt_file_chunk_sqtt_desc(Structure): - pass - -class union_sqtt_file_chunk_sqtt_desc_0(Union): - pass - -class struct_sqtt_file_chunk_sqtt_desc_0_v0(Structure): - pass - -struct_sqtt_file_chunk_sqtt_desc_0_v0._pack_ = 1 # source:False -struct_sqtt_file_chunk_sqtt_desc_0_v0._fields_ = [ - ('instrumentation_version', ctypes.c_int32), -] - -class struct_sqtt_file_chunk_sqtt_desc_0_v1(Structure): - pass - -struct_sqtt_file_chunk_sqtt_desc_0_v1._pack_ = 1 # source:False -struct_sqtt_file_chunk_sqtt_desc_0_v1._fields_ = [ - ('instrumentation_spec_version', ctypes.c_int16), - ('instrumentation_api_version', ctypes.c_int16), - ('compute_unit_index', ctypes.c_int32), -] - -union_sqtt_file_chunk_sqtt_desc_0._pack_ = 1 # source:False -union_sqtt_file_chunk_sqtt_desc_0._fields_ = [ - ('v0', struct_sqtt_file_chunk_sqtt_desc_0_v0), - ('v1', struct_sqtt_file_chunk_sqtt_desc_0_v1), -] - -struct_sqtt_file_chunk_sqtt_desc._pack_ = 1 # source:False -struct_sqtt_file_chunk_sqtt_desc._anonymous_ = ('_0',) -struct_sqtt_file_chunk_sqtt_desc._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('shader_engine_index', ctypes.c_int32), - ('sqtt_version', sqtt_version), - ('_0', union_sqtt_file_chunk_sqtt_desc_0), -] - -class struct_sqtt_file_chunk_sqtt_data(Structure): - pass - -struct_sqtt_file_chunk_sqtt_data._pack_ = 1 # source:False -struct_sqtt_file_chunk_sqtt_data._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_int32), - ('size', ctypes.c_int32), -] - -class struct_sqtt_file_chunk_queue_event_timings(Structure): - pass - -struct_sqtt_file_chunk_queue_event_timings._pack_ = 1 # source:False -struct_sqtt_file_chunk_queue_event_timings._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('queue_info_table_record_count', ctypes.c_uint32), - ('queue_info_table_size', ctypes.c_uint32), - ('queue_event_table_record_count', ctypes.c_uint32), - ('queue_event_table_size', ctypes.c_uint32), -] - - -# values for enumeration 'sqtt_queue_type' -sqtt_queue_type__enumvalues = { - 0: 'SQTT_QUEUE_TYPE_UNKNOWN', - 1: 'SQTT_QUEUE_TYPE_UNIVERSAL', - 2: 'SQTT_QUEUE_TYPE_COMPUTE', - 3: 'SQTT_QUEUE_TYPE_DMA', -} -SQTT_QUEUE_TYPE_UNKNOWN = 0 -SQTT_QUEUE_TYPE_UNIVERSAL = 1 -SQTT_QUEUE_TYPE_COMPUTE = 2 -SQTT_QUEUE_TYPE_DMA = 3 -sqtt_queue_type = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_engine_type' -sqtt_engine_type__enumvalues = { - 0: 'SQTT_ENGINE_TYPE_UNKNOWN', - 1: 'SQTT_ENGINE_TYPE_UNIVERSAL', - 2: 'SQTT_ENGINE_TYPE_COMPUTE', - 3: 'SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE', - 4: 'SQTT_ENGINE_TYPE_DMA', - 7: 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL', - 8: 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS', -} -SQTT_ENGINE_TYPE_UNKNOWN = 0 -SQTT_ENGINE_TYPE_UNIVERSAL = 1 -SQTT_ENGINE_TYPE_COMPUTE = 2 -SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = 3 -SQTT_ENGINE_TYPE_DMA = 4 -SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = 7 -SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = 8 -sqtt_engine_type = ctypes.c_uint32 # enum -class struct_sqtt_queue_hardware_info(Structure): - pass - -class union_sqtt_queue_hardware_info_0(Union): - pass - -class struct_sqtt_queue_hardware_info_0_0(Structure): - pass - -struct_sqtt_queue_hardware_info_0_0._pack_ = 1 # source:False -struct_sqtt_queue_hardware_info_0_0._fields_ = [ - ('queue_type', ctypes.c_int32, 8), - ('engine_type', ctypes.c_int32, 8), - ('reserved', ctypes.c_int32, 16), -] - -union_sqtt_queue_hardware_info_0._pack_ = 1 # source:False -union_sqtt_queue_hardware_info_0._anonymous_ = ('_0',) -union_sqtt_queue_hardware_info_0._fields_ = [ - ('_0', struct_sqtt_queue_hardware_info_0_0), - ('value', ctypes.c_uint32), -] - -struct_sqtt_queue_hardware_info._pack_ = 1 # source:False -struct_sqtt_queue_hardware_info._anonymous_ = ('_0',) -struct_sqtt_queue_hardware_info._fields_ = [ - ('_0', union_sqtt_queue_hardware_info_0), -] - -class struct_sqtt_queue_info_record(Structure): - pass - -struct_sqtt_queue_info_record._pack_ = 1 # source:False -struct_sqtt_queue_info_record._fields_ = [ - ('queue_id', ctypes.c_uint64), - ('queue_context', ctypes.c_uint64), - ('hardware_info', struct_sqtt_queue_hardware_info), - ('reserved', ctypes.c_uint32), -] - - -# values for enumeration 'sqtt_queue_event_type' -sqtt_queue_event_type__enumvalues = { - 0: 'SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT', - 1: 'SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE', - 2: 'SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE', - 3: 'SQTT_QUEUE_TIMING_EVENT_PRESENT', -} -SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT = 0 -SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE = 1 -SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE = 2 -SQTT_QUEUE_TIMING_EVENT_PRESENT = 3 -sqtt_queue_event_type = ctypes.c_uint32 # enum -class struct_sqtt_queue_event_record(Structure): - pass - -struct_sqtt_queue_event_record._pack_ = 1 # source:False -struct_sqtt_queue_event_record._fields_ = [ - ('event_type', sqtt_queue_event_type), - ('sqtt_cb_id', ctypes.c_uint32), - ('frame_index', ctypes.c_uint64), - ('queue_info_index', ctypes.c_uint32), - ('submit_sub_index', ctypes.c_uint32), - ('api_id', ctypes.c_uint64), - ('cpu_timestamp', ctypes.c_uint64), - ('gpu_timestamps', ctypes.c_uint64 * 2), -] - -class struct_sqtt_file_chunk_clock_calibration(Structure): - pass - -struct_sqtt_file_chunk_clock_calibration._pack_ = 1 # source:False -struct_sqtt_file_chunk_clock_calibration._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('cpu_timestamp', ctypes.c_uint64), - ('gpu_timestamp', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), -] - - -# values for enumeration 'elf_gfxip_level' -elf_gfxip_level__enumvalues = { - 40: 'EF_AMDGPU_MACH_AMDGCN_GFX801', - 44: 'EF_AMDGPU_MACH_AMDGCN_GFX900', - 51: 'EF_AMDGPU_MACH_AMDGCN_GFX1010', - 54: 'EF_AMDGPU_MACH_AMDGCN_GFX1030', - 65: 'EF_AMDGPU_MACH_AMDGCN_GFX1100', -} -EF_AMDGPU_MACH_AMDGCN_GFX801 = 40 -EF_AMDGPU_MACH_AMDGCN_GFX900 = 44 -EF_AMDGPU_MACH_AMDGCN_GFX1010 = 51 -EF_AMDGPU_MACH_AMDGCN_GFX1030 = 54 -EF_AMDGPU_MACH_AMDGCN_GFX1100 = 65 -elf_gfxip_level = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_spm_db(Structure): - pass - -struct_sqtt_file_chunk_spm_db._pack_ = 1 # source:False -struct_sqtt_file_chunk_spm_db._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('flags', ctypes.c_uint32), - ('preamble_size', ctypes.c_uint32), - ('num_timestamps', ctypes.c_uint32), - ('num_spm_counter_info', ctypes.c_uint32), - ('spm_counter_info_size', ctypes.c_uint32), - ('sample_interval', ctypes.c_uint32), -] - - -# values for enumeration 'rgp_sqtt_marker_identifier' -rgp_sqtt_marker_identifier__enumvalues = { - 0: 'RGP_SQTT_MARKER_IDENTIFIER_EVENT', - 1: 'RGP_SQTT_MARKER_IDENTIFIER_CB_START', - 2: 'RGP_SQTT_MARKER_IDENTIFIER_CB_END', - 3: 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START', - 4: 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END', - 5: 'RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT', - 6: 'RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API', - 7: 'RGP_SQTT_MARKER_IDENTIFIER_SYNC', - 8: 'RGP_SQTT_MARKER_IDENTIFIER_PRESENT', - 9: 'RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION', - 10: 'RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS', - 11: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED2', - 12: 'RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE', - 13: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED4', - 14: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED5', - 15: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED6', -} -RGP_SQTT_MARKER_IDENTIFIER_EVENT = 0 -RGP_SQTT_MARKER_IDENTIFIER_CB_START = 1 -RGP_SQTT_MARKER_IDENTIFIER_CB_END = 2 -RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START = 3 -RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END = 4 -RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT = 5 -RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API = 6 -RGP_SQTT_MARKER_IDENTIFIER_SYNC = 7 -RGP_SQTT_MARKER_IDENTIFIER_PRESENT = 8 -RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION = 9 -RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS = 10 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED2 = 11 -RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE = 12 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED4 = 13 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED5 = 14 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED6 = 15 -rgp_sqtt_marker_identifier = ctypes.c_uint32 # enum -class union_rgp_sqtt_marker_cb_id(Union): - pass - -class struct_rgp_sqtt_marker_cb_id_per_frame_cb_id(Structure): - pass - -struct_rgp_sqtt_marker_cb_id_per_frame_cb_id._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_id_per_frame_cb_id._fields_ = [ - ('per_frame', ctypes.c_uint32, 1), - ('frame_index', ctypes.c_uint32, 7), - ('cb_index', ctypes.c_uint32, 12), - ('reserved', ctypes.c_uint32, 12), -] - -class struct_rgp_sqtt_marker_cb_id_global_cb_id(Structure): - pass - -struct_rgp_sqtt_marker_cb_id_global_cb_id._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_id_global_cb_id._fields_ = [ - ('per_frame', ctypes.c_uint32, 1), - ('cb_index', ctypes.c_uint32, 19), - ('reserved', ctypes.c_uint32, 12), -] - -union_rgp_sqtt_marker_cb_id._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_id._fields_ = [ - ('per_frame_cb_id', struct_rgp_sqtt_marker_cb_id_per_frame_cb_id), - ('global_cb_id', struct_rgp_sqtt_marker_cb_id_global_cb_id), - ('all', ctypes.c_uint32), -] - -class struct_rgp_sqtt_marker_cb_start(Structure): - pass - -class union_rgp_sqtt_marker_cb_start_0(Union): - pass - -class struct_rgp_sqtt_marker_cb_start_0_0(Structure): - pass - -struct_rgp_sqtt_marker_cb_start_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_start_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('queue', ctypes.c_uint32, 5), -] - -union_rgp_sqtt_marker_cb_start_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_cb_start_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_cb_start_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_cb_start_1(Union): - pass - -union_rgp_sqtt_marker_cb_start_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_1._fields_ = [ - ('device_id_low', ctypes.c_uint32), - ('dword02', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_cb_start_2(Union): - pass - -union_rgp_sqtt_marker_cb_start_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_2._fields_ = [ - ('device_id_high', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_cb_start_3(Union): - pass - -union_rgp_sqtt_marker_cb_start_3._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_3._fields_ = [ - ('queue_flags', ctypes.c_uint32), - ('dword04', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_cb_start._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_start._anonymous_ = ('_0', '_1', '_2', '_3',) -struct_rgp_sqtt_marker_cb_start._fields_ = [ - ('_0', union_rgp_sqtt_marker_cb_start_0), - ('_1', union_rgp_sqtt_marker_cb_start_1), - ('_2', union_rgp_sqtt_marker_cb_start_2), - ('_3', union_rgp_sqtt_marker_cb_start_3), -] - -class struct_rgp_sqtt_marker_cb_end(Structure): - pass - -class union_rgp_sqtt_marker_cb_end_0(Union): - pass - -class struct_rgp_sqtt_marker_cb_end_0_0(Structure): - pass - -struct_rgp_sqtt_marker_cb_end_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_end_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 5), -] - -union_rgp_sqtt_marker_cb_end_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_cb_end_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_cb_end_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_cb_end_1(Union): - pass - -union_rgp_sqtt_marker_cb_end_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_1._fields_ = [ - ('device_id_low', ctypes.c_uint32), - ('dword02', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_cb_end_2(Union): - pass - -union_rgp_sqtt_marker_cb_end_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_2._fields_ = [ - ('device_id_high', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_cb_end._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_end._anonymous_ = ('_0', '_1', '_2',) -struct_rgp_sqtt_marker_cb_end._fields_ = [ - ('_0', union_rgp_sqtt_marker_cb_end_0), - ('_1', union_rgp_sqtt_marker_cb_end_1), - ('_2', union_rgp_sqtt_marker_cb_end_2), -] - - -# values for enumeration 'rgp_sqtt_marker_general_api_type' -rgp_sqtt_marker_general_api_type__enumvalues = { - 0: 'ApiCmdBindPipeline', - 1: 'ApiCmdBindDescriptorSets', - 2: 'ApiCmdBindIndexBuffer', - 3: 'ApiCmdBindVertexBuffers', - 4: 'ApiCmdDraw', - 5: 'ApiCmdDrawIndexed', - 6: 'ApiCmdDrawIndirect', - 7: 'ApiCmdDrawIndexedIndirect', - 8: 'ApiCmdDrawIndirectCountAMD', - 9: 'ApiCmdDrawIndexedIndirectCountAMD', - 10: 'ApiCmdDispatch', - 11: 'ApiCmdDispatchIndirect', - 12: 'ApiCmdCopyBuffer', - 13: 'ApiCmdCopyImage', - 14: 'ApiCmdBlitImage', - 15: 'ApiCmdCopyBufferToImage', - 16: 'ApiCmdCopyImageToBuffer', - 17: 'ApiCmdUpdateBuffer', - 18: 'ApiCmdFillBuffer', - 19: 'ApiCmdClearColorImage', - 20: 'ApiCmdClearDepthStencilImage', - 21: 'ApiCmdClearAttachments', - 22: 'ApiCmdResolveImage', - 23: 'ApiCmdWaitEvents', - 24: 'ApiCmdPipelineBarrier', - 25: 'ApiCmdBeginQuery', - 26: 'ApiCmdEndQuery', - 27: 'ApiCmdResetQueryPool', - 28: 'ApiCmdWriteTimestamp', - 29: 'ApiCmdCopyQueryPoolResults', - 30: 'ApiCmdPushConstants', - 31: 'ApiCmdBeginRenderPass', - 32: 'ApiCmdNextSubpass', - 33: 'ApiCmdEndRenderPass', - 34: 'ApiCmdExecuteCommands', - 35: 'ApiCmdSetViewport', - 36: 'ApiCmdSetScissor', - 37: 'ApiCmdSetLineWidth', - 38: 'ApiCmdSetDepthBias', - 39: 'ApiCmdSetBlendConstants', - 40: 'ApiCmdSetDepthBounds', - 41: 'ApiCmdSetStencilCompareMask', - 42: 'ApiCmdSetStencilWriteMask', - 43: 'ApiCmdSetStencilReference', - 44: 'ApiCmdDrawIndirectCount', - 45: 'ApiCmdDrawIndexedIndirectCount', - 47: 'ApiCmdDrawMeshTasksEXT', - 48: 'ApiCmdDrawMeshTasksIndirectCountEXT', - 49: 'ApiCmdDrawMeshTasksIndirectEXT', - 8388608: 'ApiRayTracingSeparateCompiled', - 4294967295: 'ApiInvalid', -} -ApiCmdBindPipeline = 0 -ApiCmdBindDescriptorSets = 1 -ApiCmdBindIndexBuffer = 2 -ApiCmdBindVertexBuffers = 3 -ApiCmdDraw = 4 -ApiCmdDrawIndexed = 5 -ApiCmdDrawIndirect = 6 -ApiCmdDrawIndexedIndirect = 7 -ApiCmdDrawIndirectCountAMD = 8 -ApiCmdDrawIndexedIndirectCountAMD = 9 -ApiCmdDispatch = 10 -ApiCmdDispatchIndirect = 11 -ApiCmdCopyBuffer = 12 -ApiCmdCopyImage = 13 -ApiCmdBlitImage = 14 -ApiCmdCopyBufferToImage = 15 -ApiCmdCopyImageToBuffer = 16 -ApiCmdUpdateBuffer = 17 -ApiCmdFillBuffer = 18 -ApiCmdClearColorImage = 19 -ApiCmdClearDepthStencilImage = 20 -ApiCmdClearAttachments = 21 -ApiCmdResolveImage = 22 -ApiCmdWaitEvents = 23 -ApiCmdPipelineBarrier = 24 -ApiCmdBeginQuery = 25 -ApiCmdEndQuery = 26 -ApiCmdResetQueryPool = 27 -ApiCmdWriteTimestamp = 28 -ApiCmdCopyQueryPoolResults = 29 -ApiCmdPushConstants = 30 -ApiCmdBeginRenderPass = 31 -ApiCmdNextSubpass = 32 -ApiCmdEndRenderPass = 33 -ApiCmdExecuteCommands = 34 -ApiCmdSetViewport = 35 -ApiCmdSetScissor = 36 -ApiCmdSetLineWidth = 37 -ApiCmdSetDepthBias = 38 -ApiCmdSetBlendConstants = 39 -ApiCmdSetDepthBounds = 40 -ApiCmdSetStencilCompareMask = 41 -ApiCmdSetStencilWriteMask = 42 -ApiCmdSetStencilReference = 43 -ApiCmdDrawIndirectCount = 44 -ApiCmdDrawIndexedIndirectCount = 45 -ApiCmdDrawMeshTasksEXT = 47 -ApiCmdDrawMeshTasksIndirectCountEXT = 48 -ApiCmdDrawMeshTasksIndirectEXT = 49 -ApiRayTracingSeparateCompiled = 8388608 -ApiInvalid = 4294967295 -rgp_sqtt_marker_general_api_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_general_api(Structure): - pass - -class union_rgp_sqtt_marker_general_api_0(Union): - pass - -class struct_rgp_sqtt_marker_general_api_0_0(Structure): - pass - -struct_rgp_sqtt_marker_general_api_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_general_api_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('api_type', ctypes.c_uint32, 20), - ('is_end', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 4), -] - -union_rgp_sqtt_marker_general_api_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_general_api_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_general_api_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_general_api_0_0), - ('dword01', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_general_api._pack_ = 1 # source:False -struct_rgp_sqtt_marker_general_api._anonymous_ = ('_0',) -struct_rgp_sqtt_marker_general_api._fields_ = [ - ('_0', union_rgp_sqtt_marker_general_api_0), -] - - -# values for enumeration 'rgp_sqtt_marker_event_type' -rgp_sqtt_marker_event_type__enumvalues = { - 0: 'EventCmdDraw', - 1: 'EventCmdDrawIndexed', - 2: 'EventCmdDrawIndirect', - 3: 'EventCmdDrawIndexedIndirect', - 4: 'EventCmdDrawIndirectCountAMD', - 5: 'EventCmdDrawIndexedIndirectCountAMD', - 6: 'EventCmdDispatch', - 7: 'EventCmdDispatchIndirect', - 8: 'EventCmdCopyBuffer', - 9: 'EventCmdCopyImage', - 10: 'EventCmdBlitImage', - 11: 'EventCmdCopyBufferToImage', - 12: 'EventCmdCopyImageToBuffer', - 13: 'EventCmdUpdateBuffer', - 14: 'EventCmdFillBuffer', - 15: 'EventCmdClearColorImage', - 16: 'EventCmdClearDepthStencilImage', - 17: 'EventCmdClearAttachments', - 18: 'EventCmdResolveImage', - 19: 'EventCmdWaitEvents', - 20: 'EventCmdPipelineBarrier', - 21: 'EventCmdResetQueryPool', - 22: 'EventCmdCopyQueryPoolResults', - 23: 'EventRenderPassColorClear', - 24: 'EventRenderPassDepthStencilClear', - 25: 'EventRenderPassResolve', - 26: 'EventInternalUnknown', - 27: 'EventCmdDrawIndirectCount', - 28: 'EventCmdDrawIndexedIndirectCount', - 30: 'EventCmdTraceRaysKHR', - 31: 'EventCmdTraceRaysIndirectKHR', - 32: 'EventCmdBuildAccelerationStructuresKHR', - 33: 'EventCmdBuildAccelerationStructuresIndirectKHR', - 34: 'EventCmdCopyAccelerationStructureKHR', - 35: 'EventCmdCopyAccelerationStructureToMemoryKHR', - 36: 'EventCmdCopyMemoryToAccelerationStructureKHR', - 41: 'EventCmdDrawMeshTasksEXT', - 42: 'EventCmdDrawMeshTasksIndirectCountEXT', - 43: 'EventCmdDrawMeshTasksIndirectEXT', - 32767: 'EventUnknown', - 4294967295: 'EventInvalid', -} -EventCmdDraw = 0 -EventCmdDrawIndexed = 1 -EventCmdDrawIndirect = 2 -EventCmdDrawIndexedIndirect = 3 -EventCmdDrawIndirectCountAMD = 4 -EventCmdDrawIndexedIndirectCountAMD = 5 -EventCmdDispatch = 6 -EventCmdDispatchIndirect = 7 -EventCmdCopyBuffer = 8 -EventCmdCopyImage = 9 -EventCmdBlitImage = 10 -EventCmdCopyBufferToImage = 11 -EventCmdCopyImageToBuffer = 12 -EventCmdUpdateBuffer = 13 -EventCmdFillBuffer = 14 -EventCmdClearColorImage = 15 -EventCmdClearDepthStencilImage = 16 -EventCmdClearAttachments = 17 -EventCmdResolveImage = 18 -EventCmdWaitEvents = 19 -EventCmdPipelineBarrier = 20 -EventCmdResetQueryPool = 21 -EventCmdCopyQueryPoolResults = 22 -EventRenderPassColorClear = 23 -EventRenderPassDepthStencilClear = 24 -EventRenderPassResolve = 25 -EventInternalUnknown = 26 -EventCmdDrawIndirectCount = 27 -EventCmdDrawIndexedIndirectCount = 28 -EventCmdTraceRaysKHR = 30 -EventCmdTraceRaysIndirectKHR = 31 -EventCmdBuildAccelerationStructuresKHR = 32 -EventCmdBuildAccelerationStructuresIndirectKHR = 33 -EventCmdCopyAccelerationStructureKHR = 34 -EventCmdCopyAccelerationStructureToMemoryKHR = 35 -EventCmdCopyMemoryToAccelerationStructureKHR = 36 -EventCmdDrawMeshTasksEXT = 41 -EventCmdDrawMeshTasksIndirectCountEXT = 42 -EventCmdDrawMeshTasksIndirectEXT = 43 -EventUnknown = 32767 -EventInvalid = 4294967295 -rgp_sqtt_marker_event_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_event(Structure): - pass - -class union_rgp_sqtt_marker_event_0(Union): - pass - -class struct_rgp_sqtt_marker_event_0_0(Structure): - pass - -struct_rgp_sqtt_marker_event_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_event_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('api_type', ctypes.c_uint32, 24), - ('has_thread_dims', ctypes.c_uint32, 1), -] - -union_rgp_sqtt_marker_event_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_event_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_event_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_event_1(Union): - pass - -class struct_rgp_sqtt_marker_event_1_0(Structure): - pass - -struct_rgp_sqtt_marker_event_1_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_event_1_0._fields_ = [ - ('cb_id', ctypes.c_uint32, 20), - ('vertex_offset_reg_idx', ctypes.c_uint32, 4), - ('instance_offset_reg_idx', ctypes.c_uint32, 4), - ('draw_index_reg_idx', ctypes.c_uint32, 4), -] - -union_rgp_sqtt_marker_event_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_event_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_event_1_0), - ('dword02', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_event_2(Union): - pass - -union_rgp_sqtt_marker_event_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_2._fields_ = [ - ('cmd_id', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_event._pack_ = 1 # source:False -struct_rgp_sqtt_marker_event._anonymous_ = ('_0', '_1', '_2',) -struct_rgp_sqtt_marker_event._fields_ = [ - ('_0', union_rgp_sqtt_marker_event_0), - ('_1', union_rgp_sqtt_marker_event_1), - ('_2', union_rgp_sqtt_marker_event_2), -] - -class struct_rgp_sqtt_marker_event_with_dims(Structure): - pass - -struct_rgp_sqtt_marker_event_with_dims._pack_ = 1 # source:False -struct_rgp_sqtt_marker_event_with_dims._fields_ = [ - ('event', struct_rgp_sqtt_marker_event), - ('thread_x', ctypes.c_uint32), - ('thread_y', ctypes.c_uint32), - ('thread_z', ctypes.c_uint32), -] - -class struct_rgp_sqtt_marker_barrier_start(Structure): - pass - -class union_rgp_sqtt_marker_barrier_start_0(Union): - pass - -class struct_rgp_sqtt_marker_barrier_start_0_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_start_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_start_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 5), -] - -union_rgp_sqtt_marker_barrier_start_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_start_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_start_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_start_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_barrier_start_1(Union): - pass - -class struct_rgp_sqtt_marker_barrier_start_1_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_start_1_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_start_1_0._fields_ = [ - ('driver_reason', ctypes.c_uint32, 31), - ('internal', ctypes.c_uint32, 1), -] - -union_rgp_sqtt_marker_barrier_start_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_start_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_start_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_start_1_0), - ('dword02', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_barrier_start._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_start._anonymous_ = ('_0', '_1',) -struct_rgp_sqtt_marker_barrier_start._fields_ = [ - ('_0', union_rgp_sqtt_marker_barrier_start_0), - ('_1', union_rgp_sqtt_marker_barrier_start_1), -] - -class struct_rgp_sqtt_marker_barrier_end(Structure): - pass - -class union_rgp_sqtt_marker_barrier_end_0(Union): - pass - -class struct_rgp_sqtt_marker_barrier_end_0_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_end_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_end_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('wait_on_eop_ts', ctypes.c_uint32, 1), - ('vs_partial_flush', ctypes.c_uint32, 1), - ('ps_partial_flush', ctypes.c_uint32, 1), - ('cs_partial_flush', ctypes.c_uint32, 1), - ('pfp_sync_me', ctypes.c_uint32, 1), -] - -union_rgp_sqtt_marker_barrier_end_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_end_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_end_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_end_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_barrier_end_1(Union): - pass - -class struct_rgp_sqtt_marker_barrier_end_1_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_end_1_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_end_1_0._fields_ = [ - ('sync_cp_dma', ctypes.c_uint32, 1), - ('inval_tcp', ctypes.c_uint32, 1), - ('inval_sqI', ctypes.c_uint32, 1), - ('inval_sqK', ctypes.c_uint32, 1), - ('flush_tcc', ctypes.c_uint32, 1), - ('inval_tcc', ctypes.c_uint32, 1), - ('flush_cb', ctypes.c_uint32, 1), - ('inval_cb', ctypes.c_uint32, 1), - ('flush_db', ctypes.c_uint32, 1), - ('inval_db', ctypes.c_uint32, 1), - ('num_layout_transitions', ctypes.c_uint32, 16), - ('inval_gl1', ctypes.c_uint32, 1), - ('wait_on_ts', ctypes.c_uint32, 1), - ('eop_ts_bottom_of_pipe', ctypes.c_uint32, 1), - ('eos_ts_ps_done', ctypes.c_uint32, 1), - ('eos_ts_cs_done', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 1), -] - -union_rgp_sqtt_marker_barrier_end_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_end_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_end_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_end_1_0), - ('dword02', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_barrier_end._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_end._anonymous_ = ('_0', '_1',) -struct_rgp_sqtt_marker_barrier_end._fields_ = [ - ('_0', union_rgp_sqtt_marker_barrier_end_0), - ('_1', union_rgp_sqtt_marker_barrier_end_1), -] - -class struct_rgp_sqtt_marker_layout_transition(Structure): - pass - -class union_rgp_sqtt_marker_layout_transition_0(Union): - pass - -class struct_rgp_sqtt_marker_layout_transition_0_0(Structure): - pass - -struct_rgp_sqtt_marker_layout_transition_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_layout_transition_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('depth_stencil_expand', ctypes.c_uint32, 1), - ('htile_hiz_range_expand', ctypes.c_uint32, 1), - ('depth_stencil_resummarize', ctypes.c_uint32, 1), - ('dcc_decompress', ctypes.c_uint32, 1), - ('fmask_decompress', ctypes.c_uint32, 1), - ('fast_clear_eliminate', ctypes.c_uint32, 1), - ('fmask_color_expand', ctypes.c_uint32, 1), - ('init_mask_ram', ctypes.c_uint32, 1), - ('reserved1', ctypes.c_uint32, 17), -] - -union_rgp_sqtt_marker_layout_transition_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_layout_transition_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_layout_transition_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_layout_transition_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_layout_transition_1(Union): - pass - -class struct_rgp_sqtt_marker_layout_transition_1_0(Structure): - pass - -struct_rgp_sqtt_marker_layout_transition_1_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_layout_transition_1_0._fields_ = [ - ('reserved2', ctypes.c_uint32, 32), -] - -union_rgp_sqtt_marker_layout_transition_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_layout_transition_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_layout_transition_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_layout_transition_1_0), - ('dword02', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_layout_transition._pack_ = 1 # source:False -struct_rgp_sqtt_marker_layout_transition._anonymous_ = ('_0', '_1',) -struct_rgp_sqtt_marker_layout_transition._fields_ = [ - ('_0', union_rgp_sqtt_marker_layout_transition_0), - ('_1', union_rgp_sqtt_marker_layout_transition_1), -] - -class struct_rgp_sqtt_marker_user_event(Structure): - pass - -class union_rgp_sqtt_marker_user_event_0(Union): - pass - -class struct_rgp_sqtt_marker_user_event_0_0(Structure): - pass - -struct_rgp_sqtt_marker_user_event_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_user_event_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('reserved0', ctypes.c_uint32, 8), - ('data_type', ctypes.c_uint32, 8), - ('reserved1', ctypes.c_uint32, 12), -] - -union_rgp_sqtt_marker_user_event_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_user_event_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_user_event_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_user_event_0_0), - ('dword01', ctypes.c_uint32), -] - -struct_rgp_sqtt_marker_user_event._pack_ = 1 # source:False -struct_rgp_sqtt_marker_user_event._anonymous_ = ('_0',) -struct_rgp_sqtt_marker_user_event._fields_ = [ - ('_0', union_rgp_sqtt_marker_user_event_0), -] - -class struct_rgp_sqtt_marker_user_event_with_length(Structure): - pass - -struct_rgp_sqtt_marker_user_event_with_length._pack_ = 1 # source:False -struct_rgp_sqtt_marker_user_event_with_length._fields_ = [ - ('user_event', struct_rgp_sqtt_marker_user_event), - ('length', ctypes.c_uint32), -] - - -# values for enumeration 'rgp_sqtt_marker_user_event_type' -rgp_sqtt_marker_user_event_type__enumvalues = { - 0: 'UserEventTrigger', - 1: 'UserEventPop', - 2: 'UserEventPush', - 3: 'UserEventObjectName', -} -UserEventTrigger = 0 -UserEventPop = 1 -UserEventPush = 2 -UserEventObjectName = 3 -rgp_sqtt_marker_user_event_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_pipeline_bind(Structure): - pass - -class union_rgp_sqtt_marker_pipeline_bind_0(Union): - pass - -class struct_rgp_sqtt_marker_pipeline_bind_0_0(Structure): - pass - -struct_rgp_sqtt_marker_pipeline_bind_0_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_pipeline_bind_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('bind_point', ctypes.c_uint32, 1), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 4), -] - -union_rgp_sqtt_marker_pipeline_bind_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_pipeline_bind_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_pipeline_bind_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_pipeline_bind_0_0), - ('dword01', ctypes.c_uint32), -] - -class union_rgp_sqtt_marker_pipeline_bind_1(Union): - pass - -class struct_rgp_sqtt_marker_pipeline_bind_1_0(Structure): - pass - -struct_rgp_sqtt_marker_pipeline_bind_1_0._pack_ = 1 # source:False -struct_rgp_sqtt_marker_pipeline_bind_1_0._fields_ = [ - ('dword02', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), -] - -union_rgp_sqtt_marker_pipeline_bind_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_pipeline_bind_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_pipeline_bind_1._fields_ = [ - ('api_pso_hash', ctypes.c_uint32 * 2), - ('_0', struct_rgp_sqtt_marker_pipeline_bind_1_0), -] - -struct_rgp_sqtt_marker_pipeline_bind._pack_ = 1 # source:False -struct_rgp_sqtt_marker_pipeline_bind._anonymous_ = ('_0', '_1',) -struct_rgp_sqtt_marker_pipeline_bind._fields_ = [ - ('_0', union_rgp_sqtt_marker_pipeline_bind_0), - ('_1', union_rgp_sqtt_marker_pipeline_bind_1), -] - -__all__ = \ - ['ApiCmdBeginQuery', 'ApiCmdBeginRenderPass', - 'ApiCmdBindDescriptorSets', 'ApiCmdBindIndexBuffer', - 'ApiCmdBindPipeline', 'ApiCmdBindVertexBuffers', - 'ApiCmdBlitImage', 'ApiCmdClearAttachments', - 'ApiCmdClearColorImage', 'ApiCmdClearDepthStencilImage', - 'ApiCmdCopyBuffer', 'ApiCmdCopyBufferToImage', 'ApiCmdCopyImage', - 'ApiCmdCopyImageToBuffer', 'ApiCmdCopyQueryPoolResults', - 'ApiCmdDispatch', 'ApiCmdDispatchIndirect', 'ApiCmdDraw', - 'ApiCmdDrawIndexed', 'ApiCmdDrawIndexedIndirect', - 'ApiCmdDrawIndexedIndirectCount', - 'ApiCmdDrawIndexedIndirectCountAMD', 'ApiCmdDrawIndirect', - 'ApiCmdDrawIndirectCount', 'ApiCmdDrawIndirectCountAMD', - 'ApiCmdDrawMeshTasksEXT', 'ApiCmdDrawMeshTasksIndirectCountEXT', - 'ApiCmdDrawMeshTasksIndirectEXT', 'ApiCmdEndQuery', - 'ApiCmdEndRenderPass', 'ApiCmdExecuteCommands', - 'ApiCmdFillBuffer', 'ApiCmdNextSubpass', 'ApiCmdPipelineBarrier', - 'ApiCmdPushConstants', 'ApiCmdResetQueryPool', - 'ApiCmdResolveImage', 'ApiCmdSetBlendConstants', - 'ApiCmdSetDepthBias', 'ApiCmdSetDepthBounds', - 'ApiCmdSetLineWidth', 'ApiCmdSetScissor', - 'ApiCmdSetStencilCompareMask', 'ApiCmdSetStencilReference', - 'ApiCmdSetStencilWriteMask', 'ApiCmdSetViewport', - 'ApiCmdUpdateBuffer', 'ApiCmdWaitEvents', 'ApiCmdWriteTimestamp', - 'ApiInvalid', 'ApiRayTracingSeparateCompiled', - 'EF_AMDGPU_MACH_AMDGCN_GFX1010', 'EF_AMDGPU_MACH_AMDGCN_GFX1030', - 'EF_AMDGPU_MACH_AMDGCN_GFX1100', 'EF_AMDGPU_MACH_AMDGCN_GFX801', - 'EF_AMDGPU_MACH_AMDGCN_GFX900', 'EventCmdBlitImage', - 'EventCmdBuildAccelerationStructuresIndirectKHR', - 'EventCmdBuildAccelerationStructuresKHR', - 'EventCmdClearAttachments', 'EventCmdClearColorImage', - 'EventCmdClearDepthStencilImage', - 'EventCmdCopyAccelerationStructureKHR', - 'EventCmdCopyAccelerationStructureToMemoryKHR', - 'EventCmdCopyBuffer', 'EventCmdCopyBufferToImage', - 'EventCmdCopyImage', 'EventCmdCopyImageToBuffer', - 'EventCmdCopyMemoryToAccelerationStructureKHR', - 'EventCmdCopyQueryPoolResults', 'EventCmdDispatch', - 'EventCmdDispatchIndirect', 'EventCmdDraw', 'EventCmdDrawIndexed', - 'EventCmdDrawIndexedIndirect', 'EventCmdDrawIndexedIndirectCount', - 'EventCmdDrawIndexedIndirectCountAMD', 'EventCmdDrawIndirect', - 'EventCmdDrawIndirectCount', 'EventCmdDrawIndirectCountAMD', - 'EventCmdDrawMeshTasksEXT', - 'EventCmdDrawMeshTasksIndirectCountEXT', - 'EventCmdDrawMeshTasksIndirectEXT', 'EventCmdFillBuffer', - 'EventCmdPipelineBarrier', 'EventCmdResetQueryPool', - 'EventCmdResolveImage', 'EventCmdTraceRaysIndirectKHR', - 'EventCmdTraceRaysKHR', 'EventCmdUpdateBuffer', - 'EventCmdWaitEvents', 'EventInternalUnknown', 'EventInvalid', - 'EventRenderPassColorClear', 'EventRenderPassDepthStencilClear', - 'EventRenderPassResolve', 'EventUnknown', - 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END', - 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START', - 'RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE', - 'RGP_SQTT_MARKER_IDENTIFIER_CB_END', - 'RGP_SQTT_MARKER_IDENTIFIER_CB_START', - 'RGP_SQTT_MARKER_IDENTIFIER_EVENT', - 'RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API', - 'RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION', - 'RGP_SQTT_MARKER_IDENTIFIER_PRESENT', - 'RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED2', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED4', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED5', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED6', - 'RGP_SQTT_MARKER_IDENTIFIER_SYNC', - 'RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT', - 'SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS', - 'SQTT_API_TYPE_DIRECTX_12', 'SQTT_API_TYPE_GENERIC', - 'SQTT_API_TYPE_OPENCL', 'SQTT_API_TYPE_VULKAN', - 'SQTT_ENGINE_TYPE_COMPUTE', 'SQTT_ENGINE_TYPE_DMA', - 'SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE', - 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS', - 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL', - 'SQTT_ENGINE_TYPE_UNIVERSAL', 'SQTT_ENGINE_TYPE_UNKNOWN', - 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED', - 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING', - 'SQTT_FILE_CHUNK_TYPE_API_INFO', 'SQTT_FILE_CHUNK_TYPE_ASIC_INFO', - 'SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION', - 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE', - 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS', - 'SQTT_FILE_CHUNK_TYPE_COUNT', 'SQTT_FILE_CHUNK_TYPE_CPU_INFO', - 'SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE', - 'SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION', - 'SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS', - 'SQTT_FILE_CHUNK_TYPE_RESERVED', 'SQTT_FILE_CHUNK_TYPE_SPM_DB', - 'SQTT_FILE_CHUNK_TYPE_SQTT_DATA', - 'SQTT_FILE_CHUNK_TYPE_SQTT_DESC', 'SQTT_FILE_MAGIC_NUMBER', - 'SQTT_FILE_VERSION_MAJOR', 'SQTT_FILE_VERSION_MINOR', - 'SQTT_GFXIP_LEVEL_GFXIP_10_1', 'SQTT_GFXIP_LEVEL_GFXIP_10_3', - 'SQTT_GFXIP_LEVEL_GFXIP_11_0', 'SQTT_GFXIP_LEVEL_GFXIP_6', - 'SQTT_GFXIP_LEVEL_GFXIP_7', 'SQTT_GFXIP_LEVEL_GFXIP_8', - 'SQTT_GFXIP_LEVEL_GFXIP_8_1', 'SQTT_GFXIP_LEVEL_GFXIP_9', - 'SQTT_GFXIP_LEVEL_NONE', 'SQTT_GPU_NAME_MAX_SIZE', - 'SQTT_GPU_TYPE_DISCRETE', 'SQTT_GPU_TYPE_INTEGRATED', - 'SQTT_GPU_TYPE_UNKNOWN', 'SQTT_GPU_TYPE_VIRTUAL', - 'SQTT_INSTRUCTION_TRACE_API_PSO', - 'SQTT_INSTRUCTION_TRACE_DISABLED', - 'SQTT_INSTRUCTION_TRACE_FULL_FRAME', 'SQTT_MAX_NUM_SE', - 'SQTT_MEMORY_TYPE_DDR', 'SQTT_MEMORY_TYPE_DDR2', - 'SQTT_MEMORY_TYPE_DDR3', 'SQTT_MEMORY_TYPE_DDR4', - 'SQTT_MEMORY_TYPE_DDR5', 'SQTT_MEMORY_TYPE_GDDR3', - 'SQTT_MEMORY_TYPE_GDDR4', 'SQTT_MEMORY_TYPE_GDDR5', - 'SQTT_MEMORY_TYPE_GDDR6', 'SQTT_MEMORY_TYPE_HBM', - 'SQTT_MEMORY_TYPE_HBM2', 'SQTT_MEMORY_TYPE_HBM3', - 'SQTT_MEMORY_TYPE_LPDDR4', 'SQTT_MEMORY_TYPE_LPDDR5', - 'SQTT_MEMORY_TYPE_UNKNOWN', 'SQTT_PROFILING_MODE_INDEX', - 'SQTT_PROFILING_MODE_PRESENT', 'SQTT_PROFILING_MODE_TAG', - 'SQTT_PROFILING_MODE_USER_MARKERS', - 'SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT', - 'SQTT_QUEUE_TIMING_EVENT_PRESENT', - 'SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE', - 'SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE', - 'SQTT_QUEUE_TYPE_COMPUTE', 'SQTT_QUEUE_TYPE_DMA', - 'SQTT_QUEUE_TYPE_UNIVERSAL', 'SQTT_QUEUE_TYPE_UNKNOWN', - 'SQTT_SA_PER_SE', 'SQTT_VERSION_2_2', 'SQTT_VERSION_2_3', - 'SQTT_VERSION_2_4', 'SQTT_VERSION_3_2', 'SQTT_VERSION_NONE', - 'UserEventObjectName', 'UserEventPop', 'UserEventPush', - 'UserEventTrigger', 'elf_gfxip_level', - 'rgp_sqtt_marker_event_type', 'rgp_sqtt_marker_general_api_type', - 'rgp_sqtt_marker_identifier', 'rgp_sqtt_marker_user_event_type', - 'sqtt_api_type', 'sqtt_engine_type', - 'sqtt_file_chunk_asic_info_flags', 'sqtt_file_chunk_type', - 'sqtt_gfxip_level', 'sqtt_gpu_type', - 'sqtt_instruction_trace_mode', 'sqtt_memory_type', - 'sqtt_profiling_mode', 'sqtt_queue_event_type', 'sqtt_queue_type', - 'sqtt_version', 'struct_rgp_sqtt_marker_barrier_end', - 'struct_rgp_sqtt_marker_barrier_end_0_0', - 'struct_rgp_sqtt_marker_barrier_end_1_0', - 'struct_rgp_sqtt_marker_barrier_start', - 'struct_rgp_sqtt_marker_barrier_start_0_0', - 'struct_rgp_sqtt_marker_barrier_start_1_0', - 'struct_rgp_sqtt_marker_cb_end', - 'struct_rgp_sqtt_marker_cb_end_0_0', - 'struct_rgp_sqtt_marker_cb_id_global_cb_id', - 'struct_rgp_sqtt_marker_cb_id_per_frame_cb_id', - 'struct_rgp_sqtt_marker_cb_start', - 'struct_rgp_sqtt_marker_cb_start_0_0', - 'struct_rgp_sqtt_marker_event', - 'struct_rgp_sqtt_marker_event_0_0', - 'struct_rgp_sqtt_marker_event_1_0', - 'struct_rgp_sqtt_marker_event_with_dims', - 'struct_rgp_sqtt_marker_general_api', - 'struct_rgp_sqtt_marker_general_api_0_0', - 'struct_rgp_sqtt_marker_layout_transition', - 'struct_rgp_sqtt_marker_layout_transition_0_0', - 'struct_rgp_sqtt_marker_layout_transition_1_0', - 'struct_rgp_sqtt_marker_pipeline_bind', - 'struct_rgp_sqtt_marker_pipeline_bind_0_0', - 'struct_rgp_sqtt_marker_pipeline_bind_1_0', - 'struct_rgp_sqtt_marker_user_event', - 'struct_rgp_sqtt_marker_user_event_0_0', - 'struct_rgp_sqtt_marker_user_event_with_length', - 'struct_sqtt_code_object_database_record', - 'struct_sqtt_code_object_loader_events_record', - 'struct_sqtt_data_info', 'struct_sqtt_data_se', - 'struct_sqtt_file_chunk_api_info', - 'struct_sqtt_file_chunk_asic_info', - 'struct_sqtt_file_chunk_clock_calibration', - 'struct_sqtt_file_chunk_code_object_database', - 'struct_sqtt_file_chunk_code_object_loader_events', - 'struct_sqtt_file_chunk_cpu_info', - 'struct_sqtt_file_chunk_header', 'struct_sqtt_file_chunk_id', - 'struct_sqtt_file_chunk_pso_correlation', - 'struct_sqtt_file_chunk_queue_event_timings', - 'struct_sqtt_file_chunk_spm_db', - 'struct_sqtt_file_chunk_sqtt_data', - 'struct_sqtt_file_chunk_sqtt_desc', - 'struct_sqtt_file_chunk_sqtt_desc_0_v0', - 'struct_sqtt_file_chunk_sqtt_desc_0_v1', - 'struct_sqtt_file_header', 'struct_sqtt_file_header_flags', - 'struct_sqtt_file_header_flags_0_0', - 'struct_sqtt_instruction_trace_data_api_pso_data', - 'struct_sqtt_instruction_trace_data_shader_engine_filter', - 'struct_sqtt_profiling_mode_data_index_profiling_data', - 'struct_sqtt_profiling_mode_data_tag_profiling_data', - 'struct_sqtt_profiling_mode_data_user_marker_profiling_data', - 'struct_sqtt_pso_correlation_record', - 'struct_sqtt_queue_event_record', - 'struct_sqtt_queue_hardware_info', - 'struct_sqtt_queue_hardware_info_0_0', - 'struct_sqtt_queue_info_record', - 'union_rgp_sqtt_marker_barrier_end_0', - 'union_rgp_sqtt_marker_barrier_end_1', - 'union_rgp_sqtt_marker_barrier_start_0', - 'union_rgp_sqtt_marker_barrier_start_1', - 'union_rgp_sqtt_marker_cb_end_0', - 'union_rgp_sqtt_marker_cb_end_1', - 'union_rgp_sqtt_marker_cb_end_2', 'union_rgp_sqtt_marker_cb_id', - 'union_rgp_sqtt_marker_cb_start_0', - 'union_rgp_sqtt_marker_cb_start_1', - 'union_rgp_sqtt_marker_cb_start_2', - 'union_rgp_sqtt_marker_cb_start_3', - 'union_rgp_sqtt_marker_event_0', 'union_rgp_sqtt_marker_event_1', - 'union_rgp_sqtt_marker_event_2', - 'union_rgp_sqtt_marker_general_api_0', - 'union_rgp_sqtt_marker_layout_transition_0', - 'union_rgp_sqtt_marker_layout_transition_1', - 'union_rgp_sqtt_marker_pipeline_bind_0', - 'union_rgp_sqtt_marker_pipeline_bind_1', - 'union_rgp_sqtt_marker_user_event_0', 'union_sqtt_data_info_0', - 'union_sqtt_file_chunk_sqtt_desc_0', - 'union_sqtt_file_header_flags_0', - 'union_sqtt_instruction_trace_data', - 'union_sqtt_profiling_mode_data', - 'union_sqtt_queue_hardware_info_0'] diff --git a/tinygrad/tinygrad/runtime/autogen/vfio.py b/tinygrad/tinygrad/runtime/autogen/vfio.py deleted file mode 100644 index 2cc7377e..00000000 --- a/tinygrad/tinygrad/runtime/autogen/vfio.py +++ /dev/null @@ -1,891 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -from tinygrad.runtime.support.hcq import FileIOInterface -import functools - -def _do_ioctl_io(__idir, __base, __nr, __fd:FileIOInterface, val=0, __len=0): - return __fd.ioctl((__idir<<30) | (__len<<16) | (__base<<8) | __nr, val) - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, __val=None, **kwargs): - ret = __fd.ioctl((__idir<<30) | (ctypes.sizeof(made := (__made or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl_io, 0, ord(base) if isinstance(base, str) else base, nr) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -VFIO_H = True # macro -VFIO_API_VERSION = 0 # macro -VFIO_TYPE1_IOMMU = 1 # macro -VFIO_SPAPR_TCE_IOMMU = 2 # macro -VFIO_TYPE1v2_IOMMU = 3 # macro -VFIO_DMA_CC_IOMMU = 4 # macro -VFIO_EEH = 5 # macro -VFIO_TYPE1_NESTING_IOMMU = 6 # macro -VFIO_SPAPR_TCE_v2_IOMMU = 7 # macro -VFIO_NOIOMMU_IOMMU = 8 # macro -VFIO_UNMAP_ALL = 9 # macro -VFIO_UPDATE_VADDR = 10 # macro -VFIO_TYPE = (';') # macro -VFIO_BASE = 100 # macro -VFIO_GET_API_VERSION = _IO ( ( ';' ) , 100 + 0 ) # macro (from list) -VFIO_CHECK_EXTENSION = _IO ( ( ';' ) , 100 + 1 ) # macro (from list) -VFIO_SET_IOMMU = _IO ( ( ';' ) , 100 + 2 ) # macro (from list) -VFIO_GROUP_FLAGS_VIABLE = (1<<0) # macro -VFIO_GROUP_FLAGS_CONTAINER_SET = (1<<1) # macro -VFIO_GROUP_GET_STATUS = _IO ( ( ';' ) , 100 + 3 ) # macro (from list) -VFIO_GROUP_SET_CONTAINER = _IO ( ( ';' ) , 100 + 4 ) # macro (from list) -VFIO_GROUP_UNSET_CONTAINER = _IO ( ( ';' ) , 100 + 5 ) # macro (from list) -VFIO_GROUP_GET_DEVICE_FD = _IO ( ( ';' ) , 100 + 6 ) # macro (from list) -VFIO_DEVICE_FLAGS_RESET = (1<<0) # macro -VFIO_DEVICE_FLAGS_PCI = (1<<1) # macro -VFIO_DEVICE_FLAGS_PLATFORM = (1<<2) # macro -VFIO_DEVICE_FLAGS_AMBA = (1<<3) # macro -VFIO_DEVICE_FLAGS_CCW = (1<<4) # macro -VFIO_DEVICE_FLAGS_AP = (1<<5) # macro -VFIO_DEVICE_FLAGS_FSL_MC = (1<<6) # macro -VFIO_DEVICE_FLAGS_CAPS = (1<<7) # macro -VFIO_DEVICE_GET_INFO = _IO ( ( ';' ) , 100 + 7 ) # macro (from list) -VFIO_DEVICE_API_PCI_STRING = "vfio-pci" # macro -VFIO_DEVICE_API_PLATFORM_STRING = "vfio-platform" # macro -VFIO_DEVICE_API_AMBA_STRING = "vfio-amba" # macro -VFIO_DEVICE_API_CCW_STRING = "vfio-ccw" # macro -VFIO_DEVICE_API_AP_STRING = "vfio-ap" # macro -VFIO_DEVICE_INFO_CAP_ZPCI_BASE = 1 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_GROUP = 2 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_UTIL = 3 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_PFIP = 4 # macro -VFIO_REGION_INFO_FLAG_READ = (1<<0) # macro -VFIO_REGION_INFO_FLAG_WRITE = (1<<1) # macro -VFIO_REGION_INFO_FLAG_MMAP = (1<<2) # macro -VFIO_REGION_INFO_FLAG_CAPS = (1<<3) # macro -VFIO_DEVICE_GET_REGION_INFO = _IO ( ( ';' ) , 100 + 8 ) # macro (from list) -VFIO_REGION_INFO_CAP_SPARSE_MMAP = 1 # macro -VFIO_REGION_INFO_CAP_TYPE = 2 # macro -VFIO_REGION_TYPE_PCI_VENDOR_TYPE = (1<<31) # macro -VFIO_REGION_TYPE_PCI_VENDOR_MASK = (0xffff) # macro -VFIO_REGION_TYPE_GFX = (1) # macro -VFIO_REGION_TYPE_CCW = (2) # macro -VFIO_REGION_TYPE_MIGRATION = (3) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION = (1) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG = (2) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG = (3) # macro -VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM = (1) # macro -VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD = (1) # macro -VFIO_REGION_SUBTYPE_GFX_EDID = (1) # macro -VFIO_DEVICE_GFX_LINK_STATE_UP = 1 # macro -VFIO_DEVICE_GFX_LINK_STATE_DOWN = 2 # macro -VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD = (1) # macro -VFIO_REGION_SUBTYPE_CCW_SCHIB = (2) # macro -VFIO_REGION_SUBTYPE_CCW_CRW = (3) # macro -VFIO_REGION_SUBTYPE_MIGRATION = (1) # macro -VFIO_DEVICE_STATE_STOP = (0) # macro -VFIO_DEVICE_STATE_RUNNING = (1<<0) # macro -VFIO_DEVICE_STATE_SAVING = (1<<1) # macro -VFIO_DEVICE_STATE_RESUMING = (1<<2) # macro -VFIO_DEVICE_STATE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro -# def VFIO_DEVICE_STATE_VALID(state): # macro -# return (state&(1<<2)?(state&((1<<0)|(1<<1)|(1<<2)))==(1<<2):1) -def VFIO_DEVICE_STATE_IS_ERROR(state): # macro - return ((state&((1<<0)|(1<<1)|(1<<2)))==((1<<1)|(1<<2))) -# def VFIO_DEVICE_STATE_SET_ERROR(state): # macro -# return ((state&~((1<<0)|(1<<1)|(1<<2)))|VFIO_DEVICE_SATE_SAVING|(1<<2)) -VFIO_REGION_INFO_CAP_MSIX_MAPPABLE = 3 # macro -VFIO_REGION_INFO_CAP_NVLINK2_SSATGT = 4 # macro -VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD = 5 # macro -VFIO_IRQ_INFO_EVENTFD = (1<<0) # macro -VFIO_IRQ_INFO_MASKABLE = (1<<1) # macro -VFIO_IRQ_INFO_AUTOMASKED = (1<<2) # macro -VFIO_IRQ_INFO_NORESIZE = (1<<3) # macro -VFIO_DEVICE_GET_IRQ_INFO = _IO ( ( ';' ) , 100 + 9 ) # macro (from list) -VFIO_IRQ_SET_DATA_NONE = (1<<0) # macro -VFIO_IRQ_SET_DATA_BOOL = (1<<1) # macro -VFIO_IRQ_SET_DATA_EVENTFD = (1<<2) # macro -VFIO_IRQ_SET_ACTION_MASK = (1<<3) # macro -VFIO_IRQ_SET_ACTION_UNMASK = (1<<4) # macro -VFIO_IRQ_SET_ACTION_TRIGGER = (1<<5) # macro -VFIO_DEVICE_SET_IRQS = _IO ( ( ';' ) , 100 + 10 ) # macro (from list) -VFIO_IRQ_SET_DATA_TYPE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro -VFIO_IRQ_SET_ACTION_TYPE_MASK = ((1<<3)|(1<<4)|(1<<5)) # macro -VFIO_DEVICE_RESET = _IO ( ( ';' ) , 100 + 11 ) # macro (from list) -VFIO_DEVICE_GET_PCI_HOT_RESET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_DEVICE_PCI_HOT_RESET = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) -VFIO_GFX_PLANE_TYPE_PROBE = (1<<0) # macro -VFIO_GFX_PLANE_TYPE_DMABUF = (1<<1) # macro -VFIO_GFX_PLANE_TYPE_REGION = (1<<2) # macro -VFIO_DEVICE_QUERY_GFX_PLANE = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) -VFIO_DEVICE_GET_GFX_DMABUF = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) -VFIO_DEVICE_IOEVENTFD_8 = (1<<0) # macro -VFIO_DEVICE_IOEVENTFD_16 = (1<<1) # macro -VFIO_DEVICE_IOEVENTFD_32 = (1<<2) # macro -VFIO_DEVICE_IOEVENTFD_64 = (1<<3) # macro -VFIO_DEVICE_IOEVENTFD_SIZE_MASK = (0xf) # macro -VFIO_DEVICE_IOEVENTFD = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) -VFIO_DEVICE_FEATURE_MASK = (0xffff) # macro -VFIO_DEVICE_FEATURE_GET = (1<<16) # macro -VFIO_DEVICE_FEATURE_SET = (1<<17) # macro -VFIO_DEVICE_FEATURE_PROBE = (1<<18) # macro -VFIO_DEVICE_FEATURE = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) # macro -VFIO_IOMMU_INFO_PGSIZES = (1<<0) # macro -VFIO_IOMMU_INFO_CAPS = (1<<1) # macro -VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 # macro -VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION = 2 # macro -VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL = 3 # macro -VFIO_IOMMU_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_DMA_MAP_FLAG_READ = (1<<0) # macro -VFIO_DMA_MAP_FLAG_WRITE = (1<<1) # macro -VFIO_DMA_MAP_FLAG_VADDR = (1<<2) # macro -VFIO_IOMMU_MAP_DMA = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) -VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP = (1<<0) # macro -VFIO_DMA_UNMAP_FLAG_ALL = (1<<1) # macro -VFIO_DMA_UNMAP_FLAG_VADDR = (1<<2) # macro -VFIO_IOMMU_UNMAP_DMA = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) -VFIO_IOMMU_ENABLE = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) -VFIO_IOMMU_DISABLE = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) -VFIO_IOMMU_DIRTY_PAGES_FLAG_START = (1<<0) # macro -VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP = (1<<1) # macro -VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP = (1<<2) # macro -VFIO_IOMMU_DIRTY_PAGES = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_IOMMU_SPAPR_INFO_DDW = (1<<0) # macro -VFIO_IOMMU_SPAPR_TCE_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_EEH_PE_DISABLE = 0 # macro -VFIO_EEH_PE_ENABLE = 1 # macro -VFIO_EEH_PE_UNFREEZE_IO = 2 # macro -VFIO_EEH_PE_UNFREEZE_DMA = 3 # macro -VFIO_EEH_PE_GET_STATE = 4 # macro -VFIO_EEH_PE_STATE_NORMAL = 0 # macro -VFIO_EEH_PE_STATE_RESET = 1 # macro -VFIO_EEH_PE_STATE_STOPPED = 2 # macro -VFIO_EEH_PE_STATE_STOPPED_DMA = 4 # macro -VFIO_EEH_PE_STATE_UNAVAIL = 5 # macro -VFIO_EEH_PE_RESET_DEACTIVATE = 5 # macro -VFIO_EEH_PE_RESET_HOT = 6 # macro -VFIO_EEH_PE_RESET_FUNDAMENTAL = 7 # macro -VFIO_EEH_PE_CONFIGURE = 8 # macro -VFIO_EEH_PE_INJECT_ERR = 9 # macro -VFIO_EEH_PE_OP = _IO ( ( ';' ) , 100 + 21 ) # macro (from list) -VFIO_IOMMU_SPAPR_REGISTER_MEMORY = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY = _IO ( ( ';' ) , 100 + 18 ) # macro (from list) -VFIO_IOMMU_SPAPR_TCE_CREATE = _IO ( ( ';' ) , 100 + 19 ) # macro (from list) -VFIO_IOMMU_SPAPR_TCE_REMOVE = _IO ( ( ';' ) , 100 + 20 ) # macro (from list) -class struct_vfio_info_cap_header(Structure): - pass - -struct_vfio_info_cap_header._pack_ = 1 # source:False -struct_vfio_info_cap_header._fields_ = [ - ('id', ctypes.c_uint16), - ('version', ctypes.c_uint16), - ('next', ctypes.c_uint32), -] - -class struct_vfio_group_status(Structure): - pass - -struct_vfio_group_status._pack_ = 1 # source:False -struct_vfio_group_status._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -class struct_vfio_device_info(Structure): - pass - -struct_vfio_device_info._pack_ = 1 # source:False -struct_vfio_device_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('num_regions', ctypes.c_uint32), - ('num_irqs', ctypes.c_uint32), - ('cap_offset', ctypes.c_uint32), -] - -class struct_vfio_region_info(Structure): - pass - -struct_vfio_region_info._pack_ = 1 # source:False -struct_vfio_region_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('cap_offset', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), -] - -class struct_vfio_region_sparse_mmap_area(Structure): - pass - -struct_vfio_region_sparse_mmap_area._pack_ = 1 # source:False -struct_vfio_region_sparse_mmap_area._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -class struct_vfio_region_info_cap_sparse_mmap(Structure): - pass - -struct_vfio_region_info_cap_sparse_mmap._pack_ = 1 # source:False -struct_vfio_region_info_cap_sparse_mmap._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('nr_areas', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('areas', struct_vfio_region_sparse_mmap_area * 0), -] - -class struct_vfio_region_info_cap_type(Structure): - pass - -struct_vfio_region_info_cap_type._pack_ = 1 # source:False -struct_vfio_region_info_cap_type._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('type', ctypes.c_uint32), - ('subtype', ctypes.c_uint32), -] - -class struct_vfio_region_gfx_edid(Structure): - pass - -struct_vfio_region_gfx_edid._pack_ = 1 # source:False -struct_vfio_region_gfx_edid._fields_ = [ - ('edid_offset', ctypes.c_uint32), - ('edid_max_size', ctypes.c_uint32), - ('edid_size', ctypes.c_uint32), - ('max_xres', ctypes.c_uint32), - ('max_yres', ctypes.c_uint32), - ('link_state', ctypes.c_uint32), -] - -class struct_vfio_device_migration_info(Structure): - pass - -struct_vfio_device_migration_info._pack_ = 1 # source:False -struct_vfio_device_migration_info._fields_ = [ - ('device_state', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('pending_bytes', ctypes.c_uint64), - ('data_offset', ctypes.c_uint64), - ('data_size', ctypes.c_uint64), -] - -class struct_vfio_region_info_cap_nvlink2_ssatgt(Structure): - pass - -struct_vfio_region_info_cap_nvlink2_ssatgt._pack_ = 1 # source:False -struct_vfio_region_info_cap_nvlink2_ssatgt._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('tgt', ctypes.c_uint64), -] - -class struct_vfio_region_info_cap_nvlink2_lnkspd(Structure): - pass - -struct_vfio_region_info_cap_nvlink2_lnkspd._pack_ = 1 # source:False -struct_vfio_region_info_cap_nvlink2_lnkspd._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('link_speed', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), -] - -class struct_vfio_irq_info(Structure): - pass - -struct_vfio_irq_info._pack_ = 1 # source:False -struct_vfio_irq_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('count', ctypes.c_uint32), -] - -class struct_vfio_irq_set(Structure): - pass - -struct_vfio_irq_set._pack_ = 1 # source:False -struct_vfio_irq_set._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('start', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('data', ctypes.c_int * 1), -] - - -# values for enumeration 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX' -c__Ea_VFIO_PCI_BAR0_REGION_INDEX__enumvalues = { - 0: 'VFIO_PCI_BAR0_REGION_INDEX', - 1: 'VFIO_PCI_BAR1_REGION_INDEX', - 2: 'VFIO_PCI_BAR2_REGION_INDEX', - 3: 'VFIO_PCI_BAR3_REGION_INDEX', - 4: 'VFIO_PCI_BAR4_REGION_INDEX', - 5: 'VFIO_PCI_BAR5_REGION_INDEX', - 6: 'VFIO_PCI_ROM_REGION_INDEX', - 7: 'VFIO_PCI_CONFIG_REGION_INDEX', - 8: 'VFIO_PCI_VGA_REGION_INDEX', - 9: 'VFIO_PCI_NUM_REGIONS', -} -VFIO_PCI_BAR0_REGION_INDEX = 0 -VFIO_PCI_BAR1_REGION_INDEX = 1 -VFIO_PCI_BAR2_REGION_INDEX = 2 -VFIO_PCI_BAR3_REGION_INDEX = 3 -VFIO_PCI_BAR4_REGION_INDEX = 4 -VFIO_PCI_BAR5_REGION_INDEX = 5 -VFIO_PCI_ROM_REGION_INDEX = 6 -VFIO_PCI_CONFIG_REGION_INDEX = 7 -VFIO_PCI_VGA_REGION_INDEX = 8 -VFIO_PCI_NUM_REGIONS = 9 -c__Ea_VFIO_PCI_BAR0_REGION_INDEX = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX' -c__Ea_VFIO_PCI_INTX_IRQ_INDEX__enumvalues = { - 0: 'VFIO_PCI_INTX_IRQ_INDEX', - 1: 'VFIO_PCI_MSI_IRQ_INDEX', - 2: 'VFIO_PCI_MSIX_IRQ_INDEX', - 3: 'VFIO_PCI_ERR_IRQ_INDEX', - 4: 'VFIO_PCI_REQ_IRQ_INDEX', - 5: 'VFIO_PCI_NUM_IRQS', -} -VFIO_PCI_INTX_IRQ_INDEX = 0 -VFIO_PCI_MSI_IRQ_INDEX = 1 -VFIO_PCI_MSIX_IRQ_INDEX = 2 -VFIO_PCI_ERR_IRQ_INDEX = 3 -VFIO_PCI_REQ_IRQ_INDEX = 4 -VFIO_PCI_NUM_IRQS = 5 -c__Ea_VFIO_PCI_INTX_IRQ_INDEX = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX' -c__Ea_VFIO_CCW_CONFIG_REGION_INDEX__enumvalues = { - 0: 'VFIO_CCW_CONFIG_REGION_INDEX', - 1: 'VFIO_CCW_NUM_REGIONS', -} -VFIO_CCW_CONFIG_REGION_INDEX = 0 -VFIO_CCW_NUM_REGIONS = 1 -c__Ea_VFIO_CCW_CONFIG_REGION_INDEX = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_VFIO_CCW_IO_IRQ_INDEX' -c__Ea_VFIO_CCW_IO_IRQ_INDEX__enumvalues = { - 0: 'VFIO_CCW_IO_IRQ_INDEX', - 1: 'VFIO_CCW_CRW_IRQ_INDEX', - 2: 'VFIO_CCW_REQ_IRQ_INDEX', - 3: 'VFIO_CCW_NUM_IRQS', -} -VFIO_CCW_IO_IRQ_INDEX = 0 -VFIO_CCW_CRW_IRQ_INDEX = 1 -VFIO_CCW_REQ_IRQ_INDEX = 2 -VFIO_CCW_NUM_IRQS = 3 -c__Ea_VFIO_CCW_IO_IRQ_INDEX = ctypes.c_uint32 # enum -class struct_vfio_pci_dependent_device(Structure): - pass - -struct_vfio_pci_dependent_device._pack_ = 1 # source:False -struct_vfio_pci_dependent_device._fields_ = [ - ('group_id', ctypes.c_uint32), - ('segment', ctypes.c_uint16), - ('bus', ctypes.c_ubyte), - ('devfn', ctypes.c_ubyte), -] - -class struct_vfio_pci_hot_reset_info(Structure): - pass - -struct_vfio_pci_hot_reset_info._pack_ = 1 # source:False -struct_vfio_pci_hot_reset_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('devices', struct_vfio_pci_dependent_device * 0), -] - -class struct_vfio_pci_hot_reset(Structure): - pass - -struct_vfio_pci_hot_reset._pack_ = 1 # source:False -struct_vfio_pci_hot_reset._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('group_fds', ctypes.c_int32 * 0), -] - -class struct_vfio_device_gfx_plane_info(Structure): - pass - -class union_vfio_device_gfx_plane_info_0(Union): - pass - -union_vfio_device_gfx_plane_info_0._pack_ = 1 # source:False -union_vfio_device_gfx_plane_info_0._fields_ = [ - ('region_index', ctypes.c_uint32), - ('dmabuf_id', ctypes.c_uint32), -] - -struct_vfio_device_gfx_plane_info._pack_ = 1 # source:False -struct_vfio_device_gfx_plane_info._anonymous_ = ('_0',) -struct_vfio_device_gfx_plane_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('drm_plane_type', ctypes.c_uint32), - ('drm_format', ctypes.c_uint32), - ('drm_format_mod', ctypes.c_uint64), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('stride', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('x_pos', ctypes.c_uint32), - ('y_pos', ctypes.c_uint32), - ('x_hot', ctypes.c_uint32), - ('y_hot', ctypes.c_uint32), - ('_0', union_vfio_device_gfx_plane_info_0), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_vfio_device_ioeventfd(Structure): - pass - -struct_vfio_device_ioeventfd._pack_ = 1 # source:False -struct_vfio_device_ioeventfd._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('data', ctypes.c_uint64), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_vfio_device_feature(Structure): - pass - -struct_vfio_device_feature._pack_ = 1 # source:False -struct_vfio_device_feature._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 0), -] - -class struct_vfio_iommu_type1_info(Structure): - pass - -struct_vfio_iommu_type1_info._pack_ = 1 # source:False -struct_vfio_iommu_type1_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('iova_pgsizes', ctypes.c_uint64), - ('cap_offset', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_vfio_iova_range(Structure): - pass - -struct_vfio_iova_range._pack_ = 1 # source:False -struct_vfio_iova_range._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), -] - -class struct_vfio_iommu_type1_info_cap_iova_range(Structure): - pass - -struct_vfio_iommu_type1_info_cap_iova_range._pack_ = 1 # source:False -struct_vfio_iommu_type1_info_cap_iova_range._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('nr_iovas', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('iova_ranges', struct_vfio_iova_range * 0), -] - -class struct_vfio_iommu_type1_info_cap_migration(Structure): - pass - -struct_vfio_iommu_type1_info_cap_migration._pack_ = 1 # source:False -struct_vfio_iommu_type1_info_cap_migration._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pgsize_bitmap', ctypes.c_uint64), - ('max_dirty_bitmap_size', ctypes.c_uint64), -] - -class struct_vfio_iommu_type1_info_dma_avail(Structure): - pass - -struct_vfio_iommu_type1_info_dma_avail._pack_ = 1 # source:False -struct_vfio_iommu_type1_info_dma_avail._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('avail', ctypes.c_uint32), -] - -class struct_vfio_iommu_type1_dma_map(Structure): - pass - -struct_vfio_iommu_type1_dma_map._pack_ = 1 # source:False -struct_vfio_iommu_type1_dma_map._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaddr', ctypes.c_uint64), - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -class struct_vfio_bitmap(Structure): - pass - -struct_vfio_bitmap._pack_ = 1 # source:False -struct_vfio_bitmap._fields_ = [ - ('pgsize', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('data', ctypes.POINTER(ctypes.c_uint64)), -] - -class struct_vfio_iommu_type1_dma_unmap(Structure): - pass - -struct_vfio_iommu_type1_dma_unmap._pack_ = 1 # source:False -struct_vfio_iommu_type1_dma_unmap._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('data', ctypes.c_ubyte * 0), -] - -class struct_vfio_iommu_type1_dirty_bitmap(Structure): - pass - -struct_vfio_iommu_type1_dirty_bitmap._pack_ = 1 # source:False -struct_vfio_iommu_type1_dirty_bitmap._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 0), -] - -class struct_vfio_iommu_type1_dirty_bitmap_get(Structure): - pass - -struct_vfio_iommu_type1_dirty_bitmap_get._pack_ = 1 # source:False -struct_vfio_iommu_type1_dirty_bitmap_get._fields_ = [ - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bitmap', struct_vfio_bitmap), -] - -class struct_vfio_iommu_spapr_tce_ddw_info(Structure): - pass - -struct_vfio_iommu_spapr_tce_ddw_info._pack_ = 1 # source:False -struct_vfio_iommu_spapr_tce_ddw_info._fields_ = [ - ('pgsizes', ctypes.c_uint64), - ('max_dynamic_windows_supported', ctypes.c_uint32), - ('levels', ctypes.c_uint32), -] - -class struct_vfio_iommu_spapr_tce_info(Structure): - pass - -struct_vfio_iommu_spapr_tce_info._pack_ = 1 # source:False -struct_vfio_iommu_spapr_tce_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dma32_window_start', ctypes.c_uint32), - ('dma32_window_size', ctypes.c_uint32), - ('ddw', struct_vfio_iommu_spapr_tce_ddw_info), -] - -class struct_vfio_eeh_pe_err(Structure): - pass - -struct_vfio_eeh_pe_err._pack_ = 1 # source:False -struct_vfio_eeh_pe_err._fields_ = [ - ('type', ctypes.c_uint32), - ('func', ctypes.c_uint32), - ('addr', ctypes.c_uint64), - ('mask', ctypes.c_uint64), -] - -class struct_vfio_eeh_pe_op(Structure): - pass - -class union_vfio_eeh_pe_op_0(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('err', struct_vfio_eeh_pe_err), - ] - -struct_vfio_eeh_pe_op._pack_ = 1 # source:False -struct_vfio_eeh_pe_op._anonymous_ = ('_0',) -struct_vfio_eeh_pe_op._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_vfio_eeh_pe_op_0), -] - -class struct_vfio_iommu_spapr_register_memory(Structure): - pass - -struct_vfio_iommu_spapr_register_memory._pack_ = 1 # source:False -struct_vfio_iommu_spapr_register_memory._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -class struct_vfio_iommu_spapr_tce_create(Structure): - pass - -struct_vfio_iommu_spapr_tce_create._pack_ = 1 # source:False -struct_vfio_iommu_spapr_tce_create._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('page_shift', ctypes.c_uint32), - ('__resv1', ctypes.c_uint32), - ('window_size', ctypes.c_uint64), - ('levels', ctypes.c_uint32), - ('__resv2', ctypes.c_uint32), - ('start_addr', ctypes.c_uint64), -] - -class struct_vfio_iommu_spapr_tce_remove(Structure): - pass - -struct_vfio_iommu_spapr_tce_remove._pack_ = 1 # source:False -struct_vfio_iommu_spapr_tce_remove._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('start_addr', ctypes.c_uint64), -] - -__all__ = \ - ['VFIO_API_VERSION', 'VFIO_BASE', 'VFIO_CCW_CONFIG_REGION_INDEX', - 'VFIO_CCW_CRW_IRQ_INDEX', 'VFIO_CCW_IO_IRQ_INDEX', - 'VFIO_CCW_NUM_IRQS', 'VFIO_CCW_NUM_REGIONS', - 'VFIO_CCW_REQ_IRQ_INDEX', 'VFIO_DEVICE_API_AMBA_STRING', - 'VFIO_DEVICE_API_AP_STRING', 'VFIO_DEVICE_API_CCW_STRING', - 'VFIO_DEVICE_API_PCI_STRING', 'VFIO_DEVICE_API_PLATFORM_STRING', - 'VFIO_DEVICE_FEATURE_GET', 'VFIO_DEVICE_FEATURE_MASK', - 'VFIO_DEVICE_FEATURE_PCI_VF_TOKEN', 'VFIO_DEVICE_FEATURE_PROBE', - 'VFIO_DEVICE_FEATURE_SET', 'VFIO_DEVICE_FLAGS_AMBA', - 'VFIO_DEVICE_FLAGS_AP', 'VFIO_DEVICE_FLAGS_CAPS', - 'VFIO_DEVICE_FLAGS_CCW', 'VFIO_DEVICE_FLAGS_FSL_MC', - 'VFIO_DEVICE_FLAGS_PCI', 'VFIO_DEVICE_FLAGS_PLATFORM', - 'VFIO_DEVICE_FLAGS_RESET', 'VFIO_DEVICE_GFX_LINK_STATE_DOWN', - 'VFIO_DEVICE_GFX_LINK_STATE_UP', 'VFIO_DEVICE_INFO_CAP_ZPCI_BASE', - 'VFIO_DEVICE_INFO_CAP_ZPCI_GROUP', - 'VFIO_DEVICE_INFO_CAP_ZPCI_PFIP', - 'VFIO_DEVICE_INFO_CAP_ZPCI_UTIL', 'VFIO_DEVICE_IOEVENTFD_16', - 'VFIO_DEVICE_IOEVENTFD_32', 'VFIO_DEVICE_IOEVENTFD_64', - 'VFIO_DEVICE_IOEVENTFD_8', 'VFIO_DEVICE_IOEVENTFD_SIZE_MASK', - 'VFIO_DEVICE_STATE_MASK', 'VFIO_DEVICE_STATE_RESUMING', - 'VFIO_DEVICE_STATE_RUNNING', 'VFIO_DEVICE_STATE_SAVING', - 'VFIO_DEVICE_STATE_STOP', 'VFIO_DMA_CC_IOMMU', - 'VFIO_DMA_MAP_FLAG_READ', 'VFIO_DMA_MAP_FLAG_VADDR', - 'VFIO_DMA_MAP_FLAG_WRITE', 'VFIO_DMA_UNMAP_FLAG_ALL', - 'VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP', - 'VFIO_DMA_UNMAP_FLAG_VADDR', 'VFIO_EEH', 'VFIO_EEH_PE_CONFIGURE', - 'VFIO_EEH_PE_DISABLE', 'VFIO_EEH_PE_ENABLE', - 'VFIO_EEH_PE_GET_STATE', 'VFIO_EEH_PE_INJECT_ERR', - 'VFIO_EEH_PE_RESET_DEACTIVATE', 'VFIO_EEH_PE_RESET_FUNDAMENTAL', - 'VFIO_EEH_PE_RESET_HOT', 'VFIO_EEH_PE_STATE_NORMAL', - 'VFIO_EEH_PE_STATE_RESET', 'VFIO_EEH_PE_STATE_STOPPED', - 'VFIO_EEH_PE_STATE_STOPPED_DMA', 'VFIO_EEH_PE_STATE_UNAVAIL', - 'VFIO_EEH_PE_UNFREEZE_DMA', 'VFIO_EEH_PE_UNFREEZE_IO', - 'VFIO_GFX_PLANE_TYPE_DMABUF', 'VFIO_GFX_PLANE_TYPE_PROBE', - 'VFIO_GFX_PLANE_TYPE_REGION', 'VFIO_GROUP_FLAGS_CONTAINER_SET', - 'VFIO_GROUP_FLAGS_VIABLE', 'VFIO_H', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_START', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP', 'VFIO_IOMMU_INFO_CAPS', - 'VFIO_IOMMU_INFO_PGSIZES', 'VFIO_IOMMU_SPAPR_INFO_DDW', - 'VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE', - 'VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION', - 'VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL', 'VFIO_IRQ_INFO_AUTOMASKED', - 'VFIO_IRQ_INFO_EVENTFD', 'VFIO_IRQ_INFO_MASKABLE', - 'VFIO_IRQ_INFO_NORESIZE', 'VFIO_IRQ_SET_ACTION_MASK', - 'VFIO_IRQ_SET_ACTION_TRIGGER', 'VFIO_IRQ_SET_ACTION_TYPE_MASK', - 'VFIO_IRQ_SET_ACTION_UNMASK', 'VFIO_IRQ_SET_DATA_BOOL', - 'VFIO_IRQ_SET_DATA_EVENTFD', 'VFIO_IRQ_SET_DATA_NONE', - 'VFIO_IRQ_SET_DATA_TYPE_MASK', 'VFIO_NOIOMMU_IOMMU', - 'VFIO_PCI_BAR0_REGION_INDEX', 'VFIO_PCI_BAR1_REGION_INDEX', - 'VFIO_PCI_BAR2_REGION_INDEX', 'VFIO_PCI_BAR3_REGION_INDEX', - 'VFIO_PCI_BAR4_REGION_INDEX', 'VFIO_PCI_BAR5_REGION_INDEX', - 'VFIO_PCI_CONFIG_REGION_INDEX', 'VFIO_PCI_ERR_IRQ_INDEX', - 'VFIO_PCI_INTX_IRQ_INDEX', 'VFIO_PCI_MSIX_IRQ_INDEX', - 'VFIO_PCI_MSI_IRQ_INDEX', 'VFIO_PCI_NUM_IRQS', - 'VFIO_PCI_NUM_REGIONS', 'VFIO_PCI_REQ_IRQ_INDEX', - 'VFIO_PCI_ROM_REGION_INDEX', 'VFIO_PCI_VGA_REGION_INDEX', - 'VFIO_REGION_INFO_CAP_MSIX_MAPPABLE', - 'VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD', - 'VFIO_REGION_INFO_CAP_NVLINK2_SSATGT', - 'VFIO_REGION_INFO_CAP_SPARSE_MMAP', 'VFIO_REGION_INFO_CAP_TYPE', - 'VFIO_REGION_INFO_FLAG_CAPS', 'VFIO_REGION_INFO_FLAG_MMAP', - 'VFIO_REGION_INFO_FLAG_READ', 'VFIO_REGION_INFO_FLAG_WRITE', - 'VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD', - 'VFIO_REGION_SUBTYPE_CCW_CRW', 'VFIO_REGION_SUBTYPE_CCW_SCHIB', - 'VFIO_REGION_SUBTYPE_GFX_EDID', - 'VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION', - 'VFIO_REGION_SUBTYPE_MIGRATION', - 'VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM', 'VFIO_REGION_TYPE_CCW', - 'VFIO_REGION_TYPE_GFX', 'VFIO_REGION_TYPE_MIGRATION', - 'VFIO_REGION_TYPE_PCI_VENDOR_MASK', - 'VFIO_REGION_TYPE_PCI_VENDOR_TYPE', 'VFIO_SPAPR_TCE_IOMMU', - 'VFIO_SPAPR_TCE_v2_IOMMU', 'VFIO_TYPE', 'VFIO_TYPE1_IOMMU', - 'VFIO_TYPE1_NESTING_IOMMU', 'VFIO_TYPE1v2_IOMMU', - 'VFIO_UNMAP_ALL', 'VFIO_UPDATE_VADDR', '_IO', '_IOR', '_IOW', - '_IOWR', 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX', - 'c__Ea_VFIO_CCW_IO_IRQ_INDEX', 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX', - 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX', 'struct_vfio_bitmap', - 'struct_vfio_device_feature', 'struct_vfio_device_gfx_plane_info', - 'struct_vfio_device_info', 'struct_vfio_device_ioeventfd', - 'struct_vfio_device_migration_info', 'struct_vfio_eeh_pe_err', - 'struct_vfio_eeh_pe_op', 'struct_vfio_group_status', - 'struct_vfio_info_cap_header', - 'struct_vfio_iommu_spapr_register_memory', - 'struct_vfio_iommu_spapr_tce_create', - 'struct_vfio_iommu_spapr_tce_ddw_info', - 'struct_vfio_iommu_spapr_tce_info', - 'struct_vfio_iommu_spapr_tce_remove', - 'struct_vfio_iommu_type1_dirty_bitmap', - 'struct_vfio_iommu_type1_dirty_bitmap_get', - 'struct_vfio_iommu_type1_dma_map', - 'struct_vfio_iommu_type1_dma_unmap', - 'struct_vfio_iommu_type1_info', - 'struct_vfio_iommu_type1_info_cap_iova_range', - 'struct_vfio_iommu_type1_info_cap_migration', - 'struct_vfio_iommu_type1_info_dma_avail', - 'struct_vfio_iova_range', 'struct_vfio_irq_info', - 'struct_vfio_irq_set', 'struct_vfio_pci_dependent_device', - 'struct_vfio_pci_hot_reset', 'struct_vfio_pci_hot_reset_info', - 'struct_vfio_region_gfx_edid', 'struct_vfio_region_info', - 'struct_vfio_region_info_cap_nvlink2_lnkspd', - 'struct_vfio_region_info_cap_nvlink2_ssatgt', - 'struct_vfio_region_info_cap_sparse_mmap', - 'struct_vfio_region_info_cap_type', - 'struct_vfio_region_sparse_mmap_area', - 'union_vfio_device_gfx_plane_info_0', 'union_vfio_eeh_pe_op_0'] diff --git a/tinygrad/tinygrad/runtime/autogen/webgpu.py b/tinygrad/tinygrad/runtime/autogen/webgpu.py deleted file mode 100644 index a1bd4c75..00000000 --- a/tinygrad/tinygrad/runtime/autogen/webgpu.py +++ /dev/null @@ -1,6994 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, tinygrad.runtime.support.webgpu as webgpu_support - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['webgpu'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['webgpu'] = ctypes.CDLL(webgpu_support.WEBGPU_PATH) # ctypes.CDLL('webgpu') - - -WGPUFlags = ctypes.c_uint64 -WGPUBool = ctypes.c_uint32 -class struct_WGPUAdapterImpl(Structure): - pass - -WGPUAdapter = ctypes.POINTER(struct_WGPUAdapterImpl) -class struct_WGPUBindGroupImpl(Structure): - pass - -WGPUBindGroup = ctypes.POINTER(struct_WGPUBindGroupImpl) -class struct_WGPUBindGroupLayoutImpl(Structure): - pass - -WGPUBindGroupLayout = ctypes.POINTER(struct_WGPUBindGroupLayoutImpl) -class struct_WGPUBufferImpl(Structure): - pass - -WGPUBuffer = ctypes.POINTER(struct_WGPUBufferImpl) -class struct_WGPUCommandBufferImpl(Structure): - pass - -WGPUCommandBuffer = ctypes.POINTER(struct_WGPUCommandBufferImpl) -class struct_WGPUCommandEncoderImpl(Structure): - pass - -WGPUCommandEncoder = ctypes.POINTER(struct_WGPUCommandEncoderImpl) -class struct_WGPUComputePassEncoderImpl(Structure): - pass - -WGPUComputePassEncoder = ctypes.POINTER(struct_WGPUComputePassEncoderImpl) -class struct_WGPUComputePipelineImpl(Structure): - pass - -WGPUComputePipeline = ctypes.POINTER(struct_WGPUComputePipelineImpl) -class struct_WGPUDeviceImpl(Structure): - pass - -WGPUDevice = ctypes.POINTER(struct_WGPUDeviceImpl) -class struct_WGPUExternalTextureImpl(Structure): - pass - -WGPUExternalTexture = ctypes.POINTER(struct_WGPUExternalTextureImpl) -class struct_WGPUInstanceImpl(Structure): - pass - -WGPUInstance = ctypes.POINTER(struct_WGPUInstanceImpl) -class struct_WGPUPipelineLayoutImpl(Structure): - pass - -WGPUPipelineLayout = ctypes.POINTER(struct_WGPUPipelineLayoutImpl) -class struct_WGPUQuerySetImpl(Structure): - pass - -WGPUQuerySet = ctypes.POINTER(struct_WGPUQuerySetImpl) -class struct_WGPUQueueImpl(Structure): - pass - -WGPUQueue = ctypes.POINTER(struct_WGPUQueueImpl) -class struct_WGPURenderBundleImpl(Structure): - pass - -WGPURenderBundle = ctypes.POINTER(struct_WGPURenderBundleImpl) -class struct_WGPURenderBundleEncoderImpl(Structure): - pass - -WGPURenderBundleEncoder = ctypes.POINTER(struct_WGPURenderBundleEncoderImpl) -class struct_WGPURenderPassEncoderImpl(Structure): - pass - -WGPURenderPassEncoder = ctypes.POINTER(struct_WGPURenderPassEncoderImpl) -class struct_WGPURenderPipelineImpl(Structure): - pass - -WGPURenderPipeline = ctypes.POINTER(struct_WGPURenderPipelineImpl) -class struct_WGPUSamplerImpl(Structure): - pass - -WGPUSampler = ctypes.POINTER(struct_WGPUSamplerImpl) -class struct_WGPUShaderModuleImpl(Structure): - pass - -WGPUShaderModule = ctypes.POINTER(struct_WGPUShaderModuleImpl) -class struct_WGPUSharedBufferMemoryImpl(Structure): - pass - -WGPUSharedBufferMemory = ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl) -class struct_WGPUSharedFenceImpl(Structure): - pass - -WGPUSharedFence = ctypes.POINTER(struct_WGPUSharedFenceImpl) -class struct_WGPUSharedTextureMemoryImpl(Structure): - pass - -WGPUSharedTextureMemory = ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl) -class struct_WGPUSurfaceImpl(Structure): - pass - -WGPUSurface = ctypes.POINTER(struct_WGPUSurfaceImpl) -class struct_WGPUTextureImpl(Structure): - pass - -WGPUTexture = ctypes.POINTER(struct_WGPUTextureImpl) -class struct_WGPUTextureViewImpl(Structure): - pass - -WGPUTextureView = ctypes.POINTER(struct_WGPUTextureViewImpl) - -# values for enumeration 'WGPUWGSLFeatureName' -WGPUWGSLFeatureName__enumvalues = { - 1: 'WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures', - 2: 'WGPUWGSLFeatureName_Packed4x8IntegerDotProduct', - 3: 'WGPUWGSLFeatureName_UnrestrictedPointerParameters', - 4: 'WGPUWGSLFeatureName_PointerCompositeAccess', - 327680: 'WGPUWGSLFeatureName_ChromiumTestingUnimplemented', - 327681: 'WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental', - 327682: 'WGPUWGSLFeatureName_ChromiumTestingExperimental', - 327683: 'WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch', - 327684: 'WGPUWGSLFeatureName_ChromiumTestingShipped', - 2147483647: 'WGPUWGSLFeatureName_Force32', -} -WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures = 1 -WGPUWGSLFeatureName_Packed4x8IntegerDotProduct = 2 -WGPUWGSLFeatureName_UnrestrictedPointerParameters = 3 -WGPUWGSLFeatureName_PointerCompositeAccess = 4 -WGPUWGSLFeatureName_ChromiumTestingUnimplemented = 327680 -WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental = 327681 -WGPUWGSLFeatureName_ChromiumTestingExperimental = 327682 -WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch = 327683 -WGPUWGSLFeatureName_ChromiumTestingShipped = 327684 -WGPUWGSLFeatureName_Force32 = 2147483647 -WGPUWGSLFeatureName = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAdapterType' -WGPUAdapterType__enumvalues = { - 1: 'WGPUAdapterType_DiscreteGPU', - 2: 'WGPUAdapterType_IntegratedGPU', - 3: 'WGPUAdapterType_CPU', - 4: 'WGPUAdapterType_Unknown', - 2147483647: 'WGPUAdapterType_Force32', -} -WGPUAdapterType_DiscreteGPU = 1 -WGPUAdapterType_IntegratedGPU = 2 -WGPUAdapterType_CPU = 3 -WGPUAdapterType_Unknown = 4 -WGPUAdapterType_Force32 = 2147483647 -WGPUAdapterType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAddressMode' -WGPUAddressMode__enumvalues = { - 0: 'WGPUAddressMode_Undefined', - 1: 'WGPUAddressMode_ClampToEdge', - 2: 'WGPUAddressMode_Repeat', - 3: 'WGPUAddressMode_MirrorRepeat', - 2147483647: 'WGPUAddressMode_Force32', -} -WGPUAddressMode_Undefined = 0 -WGPUAddressMode_ClampToEdge = 1 -WGPUAddressMode_Repeat = 2 -WGPUAddressMode_MirrorRepeat = 3 -WGPUAddressMode_Force32 = 2147483647 -WGPUAddressMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAlphaMode' -WGPUAlphaMode__enumvalues = { - 1: 'WGPUAlphaMode_Opaque', - 2: 'WGPUAlphaMode_Premultiplied', - 3: 'WGPUAlphaMode_Unpremultiplied', - 2147483647: 'WGPUAlphaMode_Force32', -} -WGPUAlphaMode_Opaque = 1 -WGPUAlphaMode_Premultiplied = 2 -WGPUAlphaMode_Unpremultiplied = 3 -WGPUAlphaMode_Force32 = 2147483647 -WGPUAlphaMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBackendType' -WGPUBackendType__enumvalues = { - 0: 'WGPUBackendType_Undefined', - 1: 'WGPUBackendType_Null', - 2: 'WGPUBackendType_WebGPU', - 3: 'WGPUBackendType_D3D11', - 4: 'WGPUBackendType_D3D12', - 5: 'WGPUBackendType_Metal', - 6: 'WGPUBackendType_Vulkan', - 7: 'WGPUBackendType_OpenGL', - 8: 'WGPUBackendType_OpenGLES', - 2147483647: 'WGPUBackendType_Force32', -} -WGPUBackendType_Undefined = 0 -WGPUBackendType_Null = 1 -WGPUBackendType_WebGPU = 2 -WGPUBackendType_D3D11 = 3 -WGPUBackendType_D3D12 = 4 -WGPUBackendType_Metal = 5 -WGPUBackendType_Vulkan = 6 -WGPUBackendType_OpenGL = 7 -WGPUBackendType_OpenGLES = 8 -WGPUBackendType_Force32 = 2147483647 -WGPUBackendType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBlendFactor' -WGPUBlendFactor__enumvalues = { - 0: 'WGPUBlendFactor_Undefined', - 1: 'WGPUBlendFactor_Zero', - 2: 'WGPUBlendFactor_One', - 3: 'WGPUBlendFactor_Src', - 4: 'WGPUBlendFactor_OneMinusSrc', - 5: 'WGPUBlendFactor_SrcAlpha', - 6: 'WGPUBlendFactor_OneMinusSrcAlpha', - 7: 'WGPUBlendFactor_Dst', - 8: 'WGPUBlendFactor_OneMinusDst', - 9: 'WGPUBlendFactor_DstAlpha', - 10: 'WGPUBlendFactor_OneMinusDstAlpha', - 11: 'WGPUBlendFactor_SrcAlphaSaturated', - 12: 'WGPUBlendFactor_Constant', - 13: 'WGPUBlendFactor_OneMinusConstant', - 14: 'WGPUBlendFactor_Src1', - 15: 'WGPUBlendFactor_OneMinusSrc1', - 16: 'WGPUBlendFactor_Src1Alpha', - 17: 'WGPUBlendFactor_OneMinusSrc1Alpha', - 2147483647: 'WGPUBlendFactor_Force32', -} -WGPUBlendFactor_Undefined = 0 -WGPUBlendFactor_Zero = 1 -WGPUBlendFactor_One = 2 -WGPUBlendFactor_Src = 3 -WGPUBlendFactor_OneMinusSrc = 4 -WGPUBlendFactor_SrcAlpha = 5 -WGPUBlendFactor_OneMinusSrcAlpha = 6 -WGPUBlendFactor_Dst = 7 -WGPUBlendFactor_OneMinusDst = 8 -WGPUBlendFactor_DstAlpha = 9 -WGPUBlendFactor_OneMinusDstAlpha = 10 -WGPUBlendFactor_SrcAlphaSaturated = 11 -WGPUBlendFactor_Constant = 12 -WGPUBlendFactor_OneMinusConstant = 13 -WGPUBlendFactor_Src1 = 14 -WGPUBlendFactor_OneMinusSrc1 = 15 -WGPUBlendFactor_Src1Alpha = 16 -WGPUBlendFactor_OneMinusSrc1Alpha = 17 -WGPUBlendFactor_Force32 = 2147483647 -WGPUBlendFactor = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBlendOperation' -WGPUBlendOperation__enumvalues = { - 0: 'WGPUBlendOperation_Undefined', - 1: 'WGPUBlendOperation_Add', - 2: 'WGPUBlendOperation_Subtract', - 3: 'WGPUBlendOperation_ReverseSubtract', - 4: 'WGPUBlendOperation_Min', - 5: 'WGPUBlendOperation_Max', - 2147483647: 'WGPUBlendOperation_Force32', -} -WGPUBlendOperation_Undefined = 0 -WGPUBlendOperation_Add = 1 -WGPUBlendOperation_Subtract = 2 -WGPUBlendOperation_ReverseSubtract = 3 -WGPUBlendOperation_Min = 4 -WGPUBlendOperation_Max = 5 -WGPUBlendOperation_Force32 = 2147483647 -WGPUBlendOperation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferBindingType' -WGPUBufferBindingType__enumvalues = { - 0: 'WGPUBufferBindingType_BindingNotUsed', - 1: 'WGPUBufferBindingType_Uniform', - 2: 'WGPUBufferBindingType_Storage', - 3: 'WGPUBufferBindingType_ReadOnlyStorage', - 2147483647: 'WGPUBufferBindingType_Force32', -} -WGPUBufferBindingType_BindingNotUsed = 0 -WGPUBufferBindingType_Uniform = 1 -WGPUBufferBindingType_Storage = 2 -WGPUBufferBindingType_ReadOnlyStorage = 3 -WGPUBufferBindingType_Force32 = 2147483647 -WGPUBufferBindingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferMapAsyncStatus' -WGPUBufferMapAsyncStatus__enumvalues = { - 1: 'WGPUBufferMapAsyncStatus_Success', - 2: 'WGPUBufferMapAsyncStatus_InstanceDropped', - 3: 'WGPUBufferMapAsyncStatus_ValidationError', - 4: 'WGPUBufferMapAsyncStatus_Unknown', - 5: 'WGPUBufferMapAsyncStatus_DeviceLost', - 6: 'WGPUBufferMapAsyncStatus_DestroyedBeforeCallback', - 7: 'WGPUBufferMapAsyncStatus_UnmappedBeforeCallback', - 8: 'WGPUBufferMapAsyncStatus_MappingAlreadyPending', - 9: 'WGPUBufferMapAsyncStatus_OffsetOutOfRange', - 10: 'WGPUBufferMapAsyncStatus_SizeOutOfRange', - 2147483647: 'WGPUBufferMapAsyncStatus_Force32', -} -WGPUBufferMapAsyncStatus_Success = 1 -WGPUBufferMapAsyncStatus_InstanceDropped = 2 -WGPUBufferMapAsyncStatus_ValidationError = 3 -WGPUBufferMapAsyncStatus_Unknown = 4 -WGPUBufferMapAsyncStatus_DeviceLost = 5 -WGPUBufferMapAsyncStatus_DestroyedBeforeCallback = 6 -WGPUBufferMapAsyncStatus_UnmappedBeforeCallback = 7 -WGPUBufferMapAsyncStatus_MappingAlreadyPending = 8 -WGPUBufferMapAsyncStatus_OffsetOutOfRange = 9 -WGPUBufferMapAsyncStatus_SizeOutOfRange = 10 -WGPUBufferMapAsyncStatus_Force32 = 2147483647 -WGPUBufferMapAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferMapState' -WGPUBufferMapState__enumvalues = { - 1: 'WGPUBufferMapState_Unmapped', - 2: 'WGPUBufferMapState_Pending', - 3: 'WGPUBufferMapState_Mapped', - 2147483647: 'WGPUBufferMapState_Force32', -} -WGPUBufferMapState_Unmapped = 1 -WGPUBufferMapState_Pending = 2 -WGPUBufferMapState_Mapped = 3 -WGPUBufferMapState_Force32 = 2147483647 -WGPUBufferMapState = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCallbackMode' -WGPUCallbackMode__enumvalues = { - 1: 'WGPUCallbackMode_WaitAnyOnly', - 2: 'WGPUCallbackMode_AllowProcessEvents', - 3: 'WGPUCallbackMode_AllowSpontaneous', - 2147483647: 'WGPUCallbackMode_Force32', -} -WGPUCallbackMode_WaitAnyOnly = 1 -WGPUCallbackMode_AllowProcessEvents = 2 -WGPUCallbackMode_AllowSpontaneous = 3 -WGPUCallbackMode_Force32 = 2147483647 -WGPUCallbackMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompareFunction' -WGPUCompareFunction__enumvalues = { - 0: 'WGPUCompareFunction_Undefined', - 1: 'WGPUCompareFunction_Never', - 2: 'WGPUCompareFunction_Less', - 3: 'WGPUCompareFunction_Equal', - 4: 'WGPUCompareFunction_LessEqual', - 5: 'WGPUCompareFunction_Greater', - 6: 'WGPUCompareFunction_NotEqual', - 7: 'WGPUCompareFunction_GreaterEqual', - 8: 'WGPUCompareFunction_Always', - 2147483647: 'WGPUCompareFunction_Force32', -} -WGPUCompareFunction_Undefined = 0 -WGPUCompareFunction_Never = 1 -WGPUCompareFunction_Less = 2 -WGPUCompareFunction_Equal = 3 -WGPUCompareFunction_LessEqual = 4 -WGPUCompareFunction_Greater = 5 -WGPUCompareFunction_NotEqual = 6 -WGPUCompareFunction_GreaterEqual = 7 -WGPUCompareFunction_Always = 8 -WGPUCompareFunction_Force32 = 2147483647 -WGPUCompareFunction = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompilationInfoRequestStatus' -WGPUCompilationInfoRequestStatus__enumvalues = { - 1: 'WGPUCompilationInfoRequestStatus_Success', - 2: 'WGPUCompilationInfoRequestStatus_InstanceDropped', - 3: 'WGPUCompilationInfoRequestStatus_Error', - 4: 'WGPUCompilationInfoRequestStatus_DeviceLost', - 5: 'WGPUCompilationInfoRequestStatus_Unknown', - 2147483647: 'WGPUCompilationInfoRequestStatus_Force32', -} -WGPUCompilationInfoRequestStatus_Success = 1 -WGPUCompilationInfoRequestStatus_InstanceDropped = 2 -WGPUCompilationInfoRequestStatus_Error = 3 -WGPUCompilationInfoRequestStatus_DeviceLost = 4 -WGPUCompilationInfoRequestStatus_Unknown = 5 -WGPUCompilationInfoRequestStatus_Force32 = 2147483647 -WGPUCompilationInfoRequestStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompilationMessageType' -WGPUCompilationMessageType__enumvalues = { - 1: 'WGPUCompilationMessageType_Error', - 2: 'WGPUCompilationMessageType_Warning', - 3: 'WGPUCompilationMessageType_Info', - 2147483647: 'WGPUCompilationMessageType_Force32', -} -WGPUCompilationMessageType_Error = 1 -WGPUCompilationMessageType_Warning = 2 -WGPUCompilationMessageType_Info = 3 -WGPUCompilationMessageType_Force32 = 2147483647 -WGPUCompilationMessageType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompositeAlphaMode' -WGPUCompositeAlphaMode__enumvalues = { - 0: 'WGPUCompositeAlphaMode_Auto', - 1: 'WGPUCompositeAlphaMode_Opaque', - 2: 'WGPUCompositeAlphaMode_Premultiplied', - 3: 'WGPUCompositeAlphaMode_Unpremultiplied', - 4: 'WGPUCompositeAlphaMode_Inherit', - 2147483647: 'WGPUCompositeAlphaMode_Force32', -} -WGPUCompositeAlphaMode_Auto = 0 -WGPUCompositeAlphaMode_Opaque = 1 -WGPUCompositeAlphaMode_Premultiplied = 2 -WGPUCompositeAlphaMode_Unpremultiplied = 3 -WGPUCompositeAlphaMode_Inherit = 4 -WGPUCompositeAlphaMode_Force32 = 2147483647 -WGPUCompositeAlphaMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCreatePipelineAsyncStatus' -WGPUCreatePipelineAsyncStatus__enumvalues = { - 1: 'WGPUCreatePipelineAsyncStatus_Success', - 2: 'WGPUCreatePipelineAsyncStatus_InstanceDropped', - 3: 'WGPUCreatePipelineAsyncStatus_ValidationError', - 4: 'WGPUCreatePipelineAsyncStatus_InternalError', - 5: 'WGPUCreatePipelineAsyncStatus_DeviceLost', - 6: 'WGPUCreatePipelineAsyncStatus_DeviceDestroyed', - 7: 'WGPUCreatePipelineAsyncStatus_Unknown', - 2147483647: 'WGPUCreatePipelineAsyncStatus_Force32', -} -WGPUCreatePipelineAsyncStatus_Success = 1 -WGPUCreatePipelineAsyncStatus_InstanceDropped = 2 -WGPUCreatePipelineAsyncStatus_ValidationError = 3 -WGPUCreatePipelineAsyncStatus_InternalError = 4 -WGPUCreatePipelineAsyncStatus_DeviceLost = 5 -WGPUCreatePipelineAsyncStatus_DeviceDestroyed = 6 -WGPUCreatePipelineAsyncStatus_Unknown = 7 -WGPUCreatePipelineAsyncStatus_Force32 = 2147483647 -WGPUCreatePipelineAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCullMode' -WGPUCullMode__enumvalues = { - 0: 'WGPUCullMode_Undefined', - 1: 'WGPUCullMode_None', - 2: 'WGPUCullMode_Front', - 3: 'WGPUCullMode_Back', - 2147483647: 'WGPUCullMode_Force32', -} -WGPUCullMode_Undefined = 0 -WGPUCullMode_None = 1 -WGPUCullMode_Front = 2 -WGPUCullMode_Back = 3 -WGPUCullMode_Force32 = 2147483647 -WGPUCullMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUDeviceLostReason' -WGPUDeviceLostReason__enumvalues = { - 1: 'WGPUDeviceLostReason_Unknown', - 2: 'WGPUDeviceLostReason_Destroyed', - 3: 'WGPUDeviceLostReason_InstanceDropped', - 4: 'WGPUDeviceLostReason_FailedCreation', - 2147483647: 'WGPUDeviceLostReason_Force32', -} -WGPUDeviceLostReason_Unknown = 1 -WGPUDeviceLostReason_Destroyed = 2 -WGPUDeviceLostReason_InstanceDropped = 3 -WGPUDeviceLostReason_FailedCreation = 4 -WGPUDeviceLostReason_Force32 = 2147483647 -WGPUDeviceLostReason = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUErrorFilter' -WGPUErrorFilter__enumvalues = { - 1: 'WGPUErrorFilter_Validation', - 2: 'WGPUErrorFilter_OutOfMemory', - 3: 'WGPUErrorFilter_Internal', - 2147483647: 'WGPUErrorFilter_Force32', -} -WGPUErrorFilter_Validation = 1 -WGPUErrorFilter_OutOfMemory = 2 -WGPUErrorFilter_Internal = 3 -WGPUErrorFilter_Force32 = 2147483647 -WGPUErrorFilter = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUErrorType' -WGPUErrorType__enumvalues = { - 1: 'WGPUErrorType_NoError', - 2: 'WGPUErrorType_Validation', - 3: 'WGPUErrorType_OutOfMemory', - 4: 'WGPUErrorType_Internal', - 5: 'WGPUErrorType_Unknown', - 6: 'WGPUErrorType_DeviceLost', - 2147483647: 'WGPUErrorType_Force32', -} -WGPUErrorType_NoError = 1 -WGPUErrorType_Validation = 2 -WGPUErrorType_OutOfMemory = 3 -WGPUErrorType_Internal = 4 -WGPUErrorType_Unknown = 5 -WGPUErrorType_DeviceLost = 6 -WGPUErrorType_Force32 = 2147483647 -WGPUErrorType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUExternalTextureRotation' -WGPUExternalTextureRotation__enumvalues = { - 1: 'WGPUExternalTextureRotation_Rotate0Degrees', - 2: 'WGPUExternalTextureRotation_Rotate90Degrees', - 3: 'WGPUExternalTextureRotation_Rotate180Degrees', - 4: 'WGPUExternalTextureRotation_Rotate270Degrees', - 2147483647: 'WGPUExternalTextureRotation_Force32', -} -WGPUExternalTextureRotation_Rotate0Degrees = 1 -WGPUExternalTextureRotation_Rotate90Degrees = 2 -WGPUExternalTextureRotation_Rotate180Degrees = 3 -WGPUExternalTextureRotation_Rotate270Degrees = 4 -WGPUExternalTextureRotation_Force32 = 2147483647 -WGPUExternalTextureRotation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFeatureLevel' -WGPUFeatureLevel__enumvalues = { - 0: 'WGPUFeatureLevel_Undefined', - 1: 'WGPUFeatureLevel_Compatibility', - 2: 'WGPUFeatureLevel_Core', - 2147483647: 'WGPUFeatureLevel_Force32', -} -WGPUFeatureLevel_Undefined = 0 -WGPUFeatureLevel_Compatibility = 1 -WGPUFeatureLevel_Core = 2 -WGPUFeatureLevel_Force32 = 2147483647 -WGPUFeatureLevel = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFeatureName' -WGPUFeatureName__enumvalues = { - 1: 'WGPUFeatureName_DepthClipControl', - 2: 'WGPUFeatureName_Depth32FloatStencil8', - 3: 'WGPUFeatureName_TimestampQuery', - 4: 'WGPUFeatureName_TextureCompressionBC', - 5: 'WGPUFeatureName_TextureCompressionETC2', - 6: 'WGPUFeatureName_TextureCompressionASTC', - 7: 'WGPUFeatureName_IndirectFirstInstance', - 8: 'WGPUFeatureName_ShaderF16', - 9: 'WGPUFeatureName_RG11B10UfloatRenderable', - 10: 'WGPUFeatureName_BGRA8UnormStorage', - 11: 'WGPUFeatureName_Float32Filterable', - 12: 'WGPUFeatureName_Float32Blendable', - 13: 'WGPUFeatureName_Subgroups', - 14: 'WGPUFeatureName_SubgroupsF16', - 327680: 'WGPUFeatureName_DawnInternalUsages', - 327681: 'WGPUFeatureName_DawnMultiPlanarFormats', - 327682: 'WGPUFeatureName_DawnNative', - 327683: 'WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses', - 327684: 'WGPUFeatureName_ImplicitDeviceSynchronization', - 327685: 'WGPUFeatureName_ChromiumExperimentalImmediateData', - 327686: 'WGPUFeatureName_TransientAttachments', - 327687: 'WGPUFeatureName_MSAARenderToSingleSampled', - 327688: 'WGPUFeatureName_DualSourceBlending', - 327689: 'WGPUFeatureName_D3D11MultithreadProtected', - 327690: 'WGPUFeatureName_ANGLETextureSharing', - 327691: 'WGPUFeatureName_PixelLocalStorageCoherent', - 327692: 'WGPUFeatureName_PixelLocalStorageNonCoherent', - 327693: 'WGPUFeatureName_Unorm16TextureFormats', - 327694: 'WGPUFeatureName_Snorm16TextureFormats', - 327695: 'WGPUFeatureName_MultiPlanarFormatExtendedUsages', - 327696: 'WGPUFeatureName_MultiPlanarFormatP010', - 327697: 'WGPUFeatureName_HostMappedPointer', - 327698: 'WGPUFeatureName_MultiPlanarRenderTargets', - 327699: 'WGPUFeatureName_MultiPlanarFormatNv12a', - 327700: 'WGPUFeatureName_FramebufferFetch', - 327701: 'WGPUFeatureName_BufferMapExtendedUsages', - 327702: 'WGPUFeatureName_AdapterPropertiesMemoryHeaps', - 327703: 'WGPUFeatureName_AdapterPropertiesD3D', - 327704: 'WGPUFeatureName_AdapterPropertiesVk', - 327705: 'WGPUFeatureName_R8UnormStorage', - 327706: 'WGPUFeatureName_FormatCapabilities', - 327707: 'WGPUFeatureName_DrmFormatCapabilities', - 327708: 'WGPUFeatureName_Norm16TextureFormats', - 327709: 'WGPUFeatureName_MultiPlanarFormatNv16', - 327710: 'WGPUFeatureName_MultiPlanarFormatNv24', - 327711: 'WGPUFeatureName_MultiPlanarFormatP210', - 327712: 'WGPUFeatureName_MultiPlanarFormatP410', - 327713: 'WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation', - 327714: 'WGPUFeatureName_SharedTextureMemoryAHardwareBuffer', - 327715: 'WGPUFeatureName_SharedTextureMemoryDmaBuf', - 327716: 'WGPUFeatureName_SharedTextureMemoryOpaqueFD', - 327717: 'WGPUFeatureName_SharedTextureMemoryZirconHandle', - 327718: 'WGPUFeatureName_SharedTextureMemoryDXGISharedHandle', - 327719: 'WGPUFeatureName_SharedTextureMemoryD3D11Texture2D', - 327720: 'WGPUFeatureName_SharedTextureMemoryIOSurface', - 327721: 'WGPUFeatureName_SharedTextureMemoryEGLImage', - 327722: 'WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD', - 327723: 'WGPUFeatureName_SharedFenceSyncFD', - 327724: 'WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle', - 327725: 'WGPUFeatureName_SharedFenceDXGISharedHandle', - 327726: 'WGPUFeatureName_SharedFenceMTLSharedEvent', - 327727: 'WGPUFeatureName_SharedBufferMemoryD3D12Resource', - 327728: 'WGPUFeatureName_StaticSamplers', - 327729: 'WGPUFeatureName_YCbCrVulkanSamplers', - 327730: 'WGPUFeatureName_ShaderModuleCompilationOptions', - 327731: 'WGPUFeatureName_DawnLoadResolveTexture', - 327732: 'WGPUFeatureName_DawnPartialLoadResolveTexture', - 327733: 'WGPUFeatureName_MultiDrawIndirect', - 327734: 'WGPUFeatureName_ClipDistances', - 327735: 'WGPUFeatureName_DawnTexelCopyBufferRowAlignment', - 327736: 'WGPUFeatureName_FlexibleTextureViews', - 2147483647: 'WGPUFeatureName_Force32', -} -WGPUFeatureName_DepthClipControl = 1 -WGPUFeatureName_Depth32FloatStencil8 = 2 -WGPUFeatureName_TimestampQuery = 3 -WGPUFeatureName_TextureCompressionBC = 4 -WGPUFeatureName_TextureCompressionETC2 = 5 -WGPUFeatureName_TextureCompressionASTC = 6 -WGPUFeatureName_IndirectFirstInstance = 7 -WGPUFeatureName_ShaderF16 = 8 -WGPUFeatureName_RG11B10UfloatRenderable = 9 -WGPUFeatureName_BGRA8UnormStorage = 10 -WGPUFeatureName_Float32Filterable = 11 -WGPUFeatureName_Float32Blendable = 12 -WGPUFeatureName_Subgroups = 13 -WGPUFeatureName_SubgroupsF16 = 14 -WGPUFeatureName_DawnInternalUsages = 327680 -WGPUFeatureName_DawnMultiPlanarFormats = 327681 -WGPUFeatureName_DawnNative = 327682 -WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses = 327683 -WGPUFeatureName_ImplicitDeviceSynchronization = 327684 -WGPUFeatureName_ChromiumExperimentalImmediateData = 327685 -WGPUFeatureName_TransientAttachments = 327686 -WGPUFeatureName_MSAARenderToSingleSampled = 327687 -WGPUFeatureName_DualSourceBlending = 327688 -WGPUFeatureName_D3D11MultithreadProtected = 327689 -WGPUFeatureName_ANGLETextureSharing = 327690 -WGPUFeatureName_PixelLocalStorageCoherent = 327691 -WGPUFeatureName_PixelLocalStorageNonCoherent = 327692 -WGPUFeatureName_Unorm16TextureFormats = 327693 -WGPUFeatureName_Snorm16TextureFormats = 327694 -WGPUFeatureName_MultiPlanarFormatExtendedUsages = 327695 -WGPUFeatureName_MultiPlanarFormatP010 = 327696 -WGPUFeatureName_HostMappedPointer = 327697 -WGPUFeatureName_MultiPlanarRenderTargets = 327698 -WGPUFeatureName_MultiPlanarFormatNv12a = 327699 -WGPUFeatureName_FramebufferFetch = 327700 -WGPUFeatureName_BufferMapExtendedUsages = 327701 -WGPUFeatureName_AdapterPropertiesMemoryHeaps = 327702 -WGPUFeatureName_AdapterPropertiesD3D = 327703 -WGPUFeatureName_AdapterPropertiesVk = 327704 -WGPUFeatureName_R8UnormStorage = 327705 -WGPUFeatureName_FormatCapabilities = 327706 -WGPUFeatureName_DrmFormatCapabilities = 327707 -WGPUFeatureName_Norm16TextureFormats = 327708 -WGPUFeatureName_MultiPlanarFormatNv16 = 327709 -WGPUFeatureName_MultiPlanarFormatNv24 = 327710 -WGPUFeatureName_MultiPlanarFormatP210 = 327711 -WGPUFeatureName_MultiPlanarFormatP410 = 327712 -WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation = 327713 -WGPUFeatureName_SharedTextureMemoryAHardwareBuffer = 327714 -WGPUFeatureName_SharedTextureMemoryDmaBuf = 327715 -WGPUFeatureName_SharedTextureMemoryOpaqueFD = 327716 -WGPUFeatureName_SharedTextureMemoryZirconHandle = 327717 -WGPUFeatureName_SharedTextureMemoryDXGISharedHandle = 327718 -WGPUFeatureName_SharedTextureMemoryD3D11Texture2D = 327719 -WGPUFeatureName_SharedTextureMemoryIOSurface = 327720 -WGPUFeatureName_SharedTextureMemoryEGLImage = 327721 -WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD = 327722 -WGPUFeatureName_SharedFenceSyncFD = 327723 -WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle = 327724 -WGPUFeatureName_SharedFenceDXGISharedHandle = 327725 -WGPUFeatureName_SharedFenceMTLSharedEvent = 327726 -WGPUFeatureName_SharedBufferMemoryD3D12Resource = 327727 -WGPUFeatureName_StaticSamplers = 327728 -WGPUFeatureName_YCbCrVulkanSamplers = 327729 -WGPUFeatureName_ShaderModuleCompilationOptions = 327730 -WGPUFeatureName_DawnLoadResolveTexture = 327731 -WGPUFeatureName_DawnPartialLoadResolveTexture = 327732 -WGPUFeatureName_MultiDrawIndirect = 327733 -WGPUFeatureName_ClipDistances = 327734 -WGPUFeatureName_DawnTexelCopyBufferRowAlignment = 327735 -WGPUFeatureName_FlexibleTextureViews = 327736 -WGPUFeatureName_Force32 = 2147483647 -WGPUFeatureName = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFilterMode' -WGPUFilterMode__enumvalues = { - 0: 'WGPUFilterMode_Undefined', - 1: 'WGPUFilterMode_Nearest', - 2: 'WGPUFilterMode_Linear', - 2147483647: 'WGPUFilterMode_Force32', -} -WGPUFilterMode_Undefined = 0 -WGPUFilterMode_Nearest = 1 -WGPUFilterMode_Linear = 2 -WGPUFilterMode_Force32 = 2147483647 -WGPUFilterMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFrontFace' -WGPUFrontFace__enumvalues = { - 0: 'WGPUFrontFace_Undefined', - 1: 'WGPUFrontFace_CCW', - 2: 'WGPUFrontFace_CW', - 2147483647: 'WGPUFrontFace_Force32', -} -WGPUFrontFace_Undefined = 0 -WGPUFrontFace_CCW = 1 -WGPUFrontFace_CW = 2 -WGPUFrontFace_Force32 = 2147483647 -WGPUFrontFace = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUIndexFormat' -WGPUIndexFormat__enumvalues = { - 0: 'WGPUIndexFormat_Undefined', - 1: 'WGPUIndexFormat_Uint16', - 2: 'WGPUIndexFormat_Uint32', - 2147483647: 'WGPUIndexFormat_Force32', -} -WGPUIndexFormat_Undefined = 0 -WGPUIndexFormat_Uint16 = 1 -WGPUIndexFormat_Uint32 = 2 -WGPUIndexFormat_Force32 = 2147483647 -WGPUIndexFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPULoadOp' -WGPULoadOp__enumvalues = { - 0: 'WGPULoadOp_Undefined', - 1: 'WGPULoadOp_Load', - 2: 'WGPULoadOp_Clear', - 327683: 'WGPULoadOp_ExpandResolveTexture', - 2147483647: 'WGPULoadOp_Force32', -} -WGPULoadOp_Undefined = 0 -WGPULoadOp_Load = 1 -WGPULoadOp_Clear = 2 -WGPULoadOp_ExpandResolveTexture = 327683 -WGPULoadOp_Force32 = 2147483647 -WGPULoadOp = ctypes.c_uint32 # enum - -# values for enumeration 'WGPULoggingType' -WGPULoggingType__enumvalues = { - 1: 'WGPULoggingType_Verbose', - 2: 'WGPULoggingType_Info', - 3: 'WGPULoggingType_Warning', - 4: 'WGPULoggingType_Error', - 2147483647: 'WGPULoggingType_Force32', -} -WGPULoggingType_Verbose = 1 -WGPULoggingType_Info = 2 -WGPULoggingType_Warning = 3 -WGPULoggingType_Error = 4 -WGPULoggingType_Force32 = 2147483647 -WGPULoggingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUMapAsyncStatus' -WGPUMapAsyncStatus__enumvalues = { - 1: 'WGPUMapAsyncStatus_Success', - 2: 'WGPUMapAsyncStatus_InstanceDropped', - 3: 'WGPUMapAsyncStatus_Error', - 4: 'WGPUMapAsyncStatus_Aborted', - 5: 'WGPUMapAsyncStatus_Unknown', - 2147483647: 'WGPUMapAsyncStatus_Force32', -} -WGPUMapAsyncStatus_Success = 1 -WGPUMapAsyncStatus_InstanceDropped = 2 -WGPUMapAsyncStatus_Error = 3 -WGPUMapAsyncStatus_Aborted = 4 -WGPUMapAsyncStatus_Unknown = 5 -WGPUMapAsyncStatus_Force32 = 2147483647 -WGPUMapAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUMipmapFilterMode' -WGPUMipmapFilterMode__enumvalues = { - 0: 'WGPUMipmapFilterMode_Undefined', - 1: 'WGPUMipmapFilterMode_Nearest', - 2: 'WGPUMipmapFilterMode_Linear', - 2147483647: 'WGPUMipmapFilterMode_Force32', -} -WGPUMipmapFilterMode_Undefined = 0 -WGPUMipmapFilterMode_Nearest = 1 -WGPUMipmapFilterMode_Linear = 2 -WGPUMipmapFilterMode_Force32 = 2147483647 -WGPUMipmapFilterMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUOptionalBool' -WGPUOptionalBool__enumvalues = { - 0: 'WGPUOptionalBool_False', - 1: 'WGPUOptionalBool_True', - 2: 'WGPUOptionalBool_Undefined', - 2147483647: 'WGPUOptionalBool_Force32', -} -WGPUOptionalBool_False = 0 -WGPUOptionalBool_True = 1 -WGPUOptionalBool_Undefined = 2 -WGPUOptionalBool_Force32 = 2147483647 -WGPUOptionalBool = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPopErrorScopeStatus' -WGPUPopErrorScopeStatus__enumvalues = { - 1: 'WGPUPopErrorScopeStatus_Success', - 2: 'WGPUPopErrorScopeStatus_InstanceDropped', - 2147483647: 'WGPUPopErrorScopeStatus_Force32', -} -WGPUPopErrorScopeStatus_Success = 1 -WGPUPopErrorScopeStatus_InstanceDropped = 2 -WGPUPopErrorScopeStatus_Force32 = 2147483647 -WGPUPopErrorScopeStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPowerPreference' -WGPUPowerPreference__enumvalues = { - 0: 'WGPUPowerPreference_Undefined', - 1: 'WGPUPowerPreference_LowPower', - 2: 'WGPUPowerPreference_HighPerformance', - 2147483647: 'WGPUPowerPreference_Force32', -} -WGPUPowerPreference_Undefined = 0 -WGPUPowerPreference_LowPower = 1 -WGPUPowerPreference_HighPerformance = 2 -WGPUPowerPreference_Force32 = 2147483647 -WGPUPowerPreference = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPresentMode' -WGPUPresentMode__enumvalues = { - 1: 'WGPUPresentMode_Fifo', - 2: 'WGPUPresentMode_FifoRelaxed', - 3: 'WGPUPresentMode_Immediate', - 4: 'WGPUPresentMode_Mailbox', - 2147483647: 'WGPUPresentMode_Force32', -} -WGPUPresentMode_Fifo = 1 -WGPUPresentMode_FifoRelaxed = 2 -WGPUPresentMode_Immediate = 3 -WGPUPresentMode_Mailbox = 4 -WGPUPresentMode_Force32 = 2147483647 -WGPUPresentMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPrimitiveTopology' -WGPUPrimitiveTopology__enumvalues = { - 0: 'WGPUPrimitiveTopology_Undefined', - 1: 'WGPUPrimitiveTopology_PointList', - 2: 'WGPUPrimitiveTopology_LineList', - 3: 'WGPUPrimitiveTopology_LineStrip', - 4: 'WGPUPrimitiveTopology_TriangleList', - 5: 'WGPUPrimitiveTopology_TriangleStrip', - 2147483647: 'WGPUPrimitiveTopology_Force32', -} -WGPUPrimitiveTopology_Undefined = 0 -WGPUPrimitiveTopology_PointList = 1 -WGPUPrimitiveTopology_LineList = 2 -WGPUPrimitiveTopology_LineStrip = 3 -WGPUPrimitiveTopology_TriangleList = 4 -WGPUPrimitiveTopology_TriangleStrip = 5 -WGPUPrimitiveTopology_Force32 = 2147483647 -WGPUPrimitiveTopology = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUQueryType' -WGPUQueryType__enumvalues = { - 1: 'WGPUQueryType_Occlusion', - 2: 'WGPUQueryType_Timestamp', - 2147483647: 'WGPUQueryType_Force32', -} -WGPUQueryType_Occlusion = 1 -WGPUQueryType_Timestamp = 2 -WGPUQueryType_Force32 = 2147483647 -WGPUQueryType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUQueueWorkDoneStatus' -WGPUQueueWorkDoneStatus__enumvalues = { - 1: 'WGPUQueueWorkDoneStatus_Success', - 2: 'WGPUQueueWorkDoneStatus_InstanceDropped', - 3: 'WGPUQueueWorkDoneStatus_Error', - 4: 'WGPUQueueWorkDoneStatus_Unknown', - 5: 'WGPUQueueWorkDoneStatus_DeviceLost', - 2147483647: 'WGPUQueueWorkDoneStatus_Force32', -} -WGPUQueueWorkDoneStatus_Success = 1 -WGPUQueueWorkDoneStatus_InstanceDropped = 2 -WGPUQueueWorkDoneStatus_Error = 3 -WGPUQueueWorkDoneStatus_Unknown = 4 -WGPUQueueWorkDoneStatus_DeviceLost = 5 -WGPUQueueWorkDoneStatus_Force32 = 2147483647 -WGPUQueueWorkDoneStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPURequestAdapterStatus' -WGPURequestAdapterStatus__enumvalues = { - 1: 'WGPURequestAdapterStatus_Success', - 2: 'WGPURequestAdapterStatus_InstanceDropped', - 3: 'WGPURequestAdapterStatus_Unavailable', - 4: 'WGPURequestAdapterStatus_Error', - 5: 'WGPURequestAdapterStatus_Unknown', - 2147483647: 'WGPURequestAdapterStatus_Force32', -} -WGPURequestAdapterStatus_Success = 1 -WGPURequestAdapterStatus_InstanceDropped = 2 -WGPURequestAdapterStatus_Unavailable = 3 -WGPURequestAdapterStatus_Error = 4 -WGPURequestAdapterStatus_Unknown = 5 -WGPURequestAdapterStatus_Force32 = 2147483647 -WGPURequestAdapterStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPURequestDeviceStatus' -WGPURequestDeviceStatus__enumvalues = { - 1: 'WGPURequestDeviceStatus_Success', - 2: 'WGPURequestDeviceStatus_InstanceDropped', - 3: 'WGPURequestDeviceStatus_Error', - 4: 'WGPURequestDeviceStatus_Unknown', - 2147483647: 'WGPURequestDeviceStatus_Force32', -} -WGPURequestDeviceStatus_Success = 1 -WGPURequestDeviceStatus_InstanceDropped = 2 -WGPURequestDeviceStatus_Error = 3 -WGPURequestDeviceStatus_Unknown = 4 -WGPURequestDeviceStatus_Force32 = 2147483647 -WGPURequestDeviceStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSType' -WGPUSType__enumvalues = { - 1: 'WGPUSType_ShaderSourceSPIRV', - 2: 'WGPUSType_ShaderSourceWGSL', - 3: 'WGPUSType_RenderPassMaxDrawCount', - 4: 'WGPUSType_SurfaceSourceMetalLayer', - 5: 'WGPUSType_SurfaceSourceWindowsHWND', - 6: 'WGPUSType_SurfaceSourceXlibWindow', - 7: 'WGPUSType_SurfaceSourceWaylandSurface', - 8: 'WGPUSType_SurfaceSourceAndroidNativeWindow', - 9: 'WGPUSType_SurfaceSourceXCBWindow', - 10: 'WGPUSType_AdapterPropertiesSubgroups', - 131072: 'WGPUSType_TextureBindingViewDimensionDescriptor', - 262144: 'WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten', - 327680: 'WGPUSType_SurfaceDescriptorFromWindowsCoreWindow', - 327681: 'WGPUSType_ExternalTextureBindingEntry', - 327682: 'WGPUSType_ExternalTextureBindingLayout', - 327683: 'WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel', - 327684: 'WGPUSType_DawnTextureInternalUsageDescriptor', - 327685: 'WGPUSType_DawnEncoderInternalUsageDescriptor', - 327686: 'WGPUSType_DawnInstanceDescriptor', - 327687: 'WGPUSType_DawnCacheDeviceDescriptor', - 327688: 'WGPUSType_DawnAdapterPropertiesPowerPreference', - 327689: 'WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient', - 327690: 'WGPUSType_DawnTogglesDescriptor', - 327691: 'WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor', - 327692: 'WGPUSType_RequestAdapterOptionsLUID', - 327693: 'WGPUSType_RequestAdapterOptionsGetGLProc', - 327694: 'WGPUSType_RequestAdapterOptionsD3D11Device', - 327695: 'WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled', - 327696: 'WGPUSType_RenderPassPixelLocalStorage', - 327697: 'WGPUSType_PipelineLayoutPixelLocalStorage', - 327698: 'WGPUSType_BufferHostMappedPointer', - 327699: 'WGPUSType_DawnExperimentalSubgroupLimits', - 327700: 'WGPUSType_AdapterPropertiesMemoryHeaps', - 327701: 'WGPUSType_AdapterPropertiesD3D', - 327702: 'WGPUSType_AdapterPropertiesVk', - 327703: 'WGPUSType_DawnWireWGSLControl', - 327704: 'WGPUSType_DawnWGSLBlocklist', - 327705: 'WGPUSType_DrmFormatCapabilities', - 327706: 'WGPUSType_ShaderModuleCompilationOptions', - 327707: 'WGPUSType_ColorTargetStateExpandResolveTextureDawn', - 327708: 'WGPUSType_RenderPassDescriptorExpandResolveRect', - 327709: 'WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor', - 327710: 'WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor', - 327711: 'WGPUSType_SharedTextureMemoryDmaBufDescriptor', - 327712: 'WGPUSType_SharedTextureMemoryOpaqueFDDescriptor', - 327713: 'WGPUSType_SharedTextureMemoryZirconHandleDescriptor', - 327714: 'WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor', - 327715: 'WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor', - 327716: 'WGPUSType_SharedTextureMemoryIOSurfaceDescriptor', - 327717: 'WGPUSType_SharedTextureMemoryEGLImageDescriptor', - 327718: 'WGPUSType_SharedTextureMemoryInitializedBeginState', - 327719: 'WGPUSType_SharedTextureMemoryInitializedEndState', - 327720: 'WGPUSType_SharedTextureMemoryVkImageLayoutBeginState', - 327721: 'WGPUSType_SharedTextureMemoryVkImageLayoutEndState', - 327722: 'WGPUSType_SharedTextureMemoryD3DSwapchainBeginState', - 327723: 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor', - 327724: 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo', - 327725: 'WGPUSType_SharedFenceSyncFDDescriptor', - 327726: 'WGPUSType_SharedFenceSyncFDExportInfo', - 327727: 'WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor', - 327728: 'WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo', - 327729: 'WGPUSType_SharedFenceDXGISharedHandleDescriptor', - 327730: 'WGPUSType_SharedFenceDXGISharedHandleExportInfo', - 327731: 'WGPUSType_SharedFenceMTLSharedEventDescriptor', - 327732: 'WGPUSType_SharedFenceMTLSharedEventExportInfo', - 327733: 'WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor', - 327734: 'WGPUSType_StaticSamplerBindingLayout', - 327735: 'WGPUSType_YCbCrVkDescriptor', - 327736: 'WGPUSType_SharedTextureMemoryAHardwareBufferProperties', - 327737: 'WGPUSType_AHardwareBufferProperties', - 327738: 'WGPUSType_DawnExperimentalImmediateDataLimits', - 327739: 'WGPUSType_DawnTexelCopyBufferRowAlignmentLimits', - 2147483647: 'WGPUSType_Force32', -} -WGPUSType_ShaderSourceSPIRV = 1 -WGPUSType_ShaderSourceWGSL = 2 -WGPUSType_RenderPassMaxDrawCount = 3 -WGPUSType_SurfaceSourceMetalLayer = 4 -WGPUSType_SurfaceSourceWindowsHWND = 5 -WGPUSType_SurfaceSourceXlibWindow = 6 -WGPUSType_SurfaceSourceWaylandSurface = 7 -WGPUSType_SurfaceSourceAndroidNativeWindow = 8 -WGPUSType_SurfaceSourceXCBWindow = 9 -WGPUSType_AdapterPropertiesSubgroups = 10 -WGPUSType_TextureBindingViewDimensionDescriptor = 131072 -WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten = 262144 -WGPUSType_SurfaceDescriptorFromWindowsCoreWindow = 327680 -WGPUSType_ExternalTextureBindingEntry = 327681 -WGPUSType_ExternalTextureBindingLayout = 327682 -WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel = 327683 -WGPUSType_DawnTextureInternalUsageDescriptor = 327684 -WGPUSType_DawnEncoderInternalUsageDescriptor = 327685 -WGPUSType_DawnInstanceDescriptor = 327686 -WGPUSType_DawnCacheDeviceDescriptor = 327687 -WGPUSType_DawnAdapterPropertiesPowerPreference = 327688 -WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient = 327689 -WGPUSType_DawnTogglesDescriptor = 327690 -WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor = 327691 -WGPUSType_RequestAdapterOptionsLUID = 327692 -WGPUSType_RequestAdapterOptionsGetGLProc = 327693 -WGPUSType_RequestAdapterOptionsD3D11Device = 327694 -WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled = 327695 -WGPUSType_RenderPassPixelLocalStorage = 327696 -WGPUSType_PipelineLayoutPixelLocalStorage = 327697 -WGPUSType_BufferHostMappedPointer = 327698 -WGPUSType_DawnExperimentalSubgroupLimits = 327699 -WGPUSType_AdapterPropertiesMemoryHeaps = 327700 -WGPUSType_AdapterPropertiesD3D = 327701 -WGPUSType_AdapterPropertiesVk = 327702 -WGPUSType_DawnWireWGSLControl = 327703 -WGPUSType_DawnWGSLBlocklist = 327704 -WGPUSType_DrmFormatCapabilities = 327705 -WGPUSType_ShaderModuleCompilationOptions = 327706 -WGPUSType_ColorTargetStateExpandResolveTextureDawn = 327707 -WGPUSType_RenderPassDescriptorExpandResolveRect = 327708 -WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor = 327709 -WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor = 327710 -WGPUSType_SharedTextureMemoryDmaBufDescriptor = 327711 -WGPUSType_SharedTextureMemoryOpaqueFDDescriptor = 327712 -WGPUSType_SharedTextureMemoryZirconHandleDescriptor = 327713 -WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor = 327714 -WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor = 327715 -WGPUSType_SharedTextureMemoryIOSurfaceDescriptor = 327716 -WGPUSType_SharedTextureMemoryEGLImageDescriptor = 327717 -WGPUSType_SharedTextureMemoryInitializedBeginState = 327718 -WGPUSType_SharedTextureMemoryInitializedEndState = 327719 -WGPUSType_SharedTextureMemoryVkImageLayoutBeginState = 327720 -WGPUSType_SharedTextureMemoryVkImageLayoutEndState = 327721 -WGPUSType_SharedTextureMemoryD3DSwapchainBeginState = 327722 -WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor = 327723 -WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo = 327724 -WGPUSType_SharedFenceSyncFDDescriptor = 327725 -WGPUSType_SharedFenceSyncFDExportInfo = 327726 -WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor = 327727 -WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo = 327728 -WGPUSType_SharedFenceDXGISharedHandleDescriptor = 327729 -WGPUSType_SharedFenceDXGISharedHandleExportInfo = 327730 -WGPUSType_SharedFenceMTLSharedEventDescriptor = 327731 -WGPUSType_SharedFenceMTLSharedEventExportInfo = 327732 -WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor = 327733 -WGPUSType_StaticSamplerBindingLayout = 327734 -WGPUSType_YCbCrVkDescriptor = 327735 -WGPUSType_SharedTextureMemoryAHardwareBufferProperties = 327736 -WGPUSType_AHardwareBufferProperties = 327737 -WGPUSType_DawnExperimentalImmediateDataLimits = 327738 -WGPUSType_DawnTexelCopyBufferRowAlignmentLimits = 327739 -WGPUSType_Force32 = 2147483647 -WGPUSType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSamplerBindingType' -WGPUSamplerBindingType__enumvalues = { - 0: 'WGPUSamplerBindingType_BindingNotUsed', - 1: 'WGPUSamplerBindingType_Filtering', - 2: 'WGPUSamplerBindingType_NonFiltering', - 3: 'WGPUSamplerBindingType_Comparison', - 2147483647: 'WGPUSamplerBindingType_Force32', -} -WGPUSamplerBindingType_BindingNotUsed = 0 -WGPUSamplerBindingType_Filtering = 1 -WGPUSamplerBindingType_NonFiltering = 2 -WGPUSamplerBindingType_Comparison = 3 -WGPUSamplerBindingType_Force32 = 2147483647 -WGPUSamplerBindingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSharedFenceType' -WGPUSharedFenceType__enumvalues = { - 1: 'WGPUSharedFenceType_VkSemaphoreOpaqueFD', - 2: 'WGPUSharedFenceType_SyncFD', - 3: 'WGPUSharedFenceType_VkSemaphoreZirconHandle', - 4: 'WGPUSharedFenceType_DXGISharedHandle', - 5: 'WGPUSharedFenceType_MTLSharedEvent', - 2147483647: 'WGPUSharedFenceType_Force32', -} -WGPUSharedFenceType_VkSemaphoreOpaqueFD = 1 -WGPUSharedFenceType_SyncFD = 2 -WGPUSharedFenceType_VkSemaphoreZirconHandle = 3 -WGPUSharedFenceType_DXGISharedHandle = 4 -WGPUSharedFenceType_MTLSharedEvent = 5 -WGPUSharedFenceType_Force32 = 2147483647 -WGPUSharedFenceType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStatus' -WGPUStatus__enumvalues = { - 1: 'WGPUStatus_Success', - 2: 'WGPUStatus_Error', - 2147483647: 'WGPUStatus_Force32', -} -WGPUStatus_Success = 1 -WGPUStatus_Error = 2 -WGPUStatus_Force32 = 2147483647 -WGPUStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStencilOperation' -WGPUStencilOperation__enumvalues = { - 0: 'WGPUStencilOperation_Undefined', - 1: 'WGPUStencilOperation_Keep', - 2: 'WGPUStencilOperation_Zero', - 3: 'WGPUStencilOperation_Replace', - 4: 'WGPUStencilOperation_Invert', - 5: 'WGPUStencilOperation_IncrementClamp', - 6: 'WGPUStencilOperation_DecrementClamp', - 7: 'WGPUStencilOperation_IncrementWrap', - 8: 'WGPUStencilOperation_DecrementWrap', - 2147483647: 'WGPUStencilOperation_Force32', -} -WGPUStencilOperation_Undefined = 0 -WGPUStencilOperation_Keep = 1 -WGPUStencilOperation_Zero = 2 -WGPUStencilOperation_Replace = 3 -WGPUStencilOperation_Invert = 4 -WGPUStencilOperation_IncrementClamp = 5 -WGPUStencilOperation_DecrementClamp = 6 -WGPUStencilOperation_IncrementWrap = 7 -WGPUStencilOperation_DecrementWrap = 8 -WGPUStencilOperation_Force32 = 2147483647 -WGPUStencilOperation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStorageTextureAccess' -WGPUStorageTextureAccess__enumvalues = { - 0: 'WGPUStorageTextureAccess_BindingNotUsed', - 1: 'WGPUStorageTextureAccess_WriteOnly', - 2: 'WGPUStorageTextureAccess_ReadOnly', - 3: 'WGPUStorageTextureAccess_ReadWrite', - 2147483647: 'WGPUStorageTextureAccess_Force32', -} -WGPUStorageTextureAccess_BindingNotUsed = 0 -WGPUStorageTextureAccess_WriteOnly = 1 -WGPUStorageTextureAccess_ReadOnly = 2 -WGPUStorageTextureAccess_ReadWrite = 3 -WGPUStorageTextureAccess_Force32 = 2147483647 -WGPUStorageTextureAccess = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStoreOp' -WGPUStoreOp__enumvalues = { - 0: 'WGPUStoreOp_Undefined', - 1: 'WGPUStoreOp_Store', - 2: 'WGPUStoreOp_Discard', - 2147483647: 'WGPUStoreOp_Force32', -} -WGPUStoreOp_Undefined = 0 -WGPUStoreOp_Store = 1 -WGPUStoreOp_Discard = 2 -WGPUStoreOp_Force32 = 2147483647 -WGPUStoreOp = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSurfaceGetCurrentTextureStatus' -WGPUSurfaceGetCurrentTextureStatus__enumvalues = { - 1: 'WGPUSurfaceGetCurrentTextureStatus_Success', - 2: 'WGPUSurfaceGetCurrentTextureStatus_Timeout', - 3: 'WGPUSurfaceGetCurrentTextureStatus_Outdated', - 4: 'WGPUSurfaceGetCurrentTextureStatus_Lost', - 5: 'WGPUSurfaceGetCurrentTextureStatus_OutOfMemory', - 6: 'WGPUSurfaceGetCurrentTextureStatus_DeviceLost', - 7: 'WGPUSurfaceGetCurrentTextureStatus_Error', - 2147483647: 'WGPUSurfaceGetCurrentTextureStatus_Force32', -} -WGPUSurfaceGetCurrentTextureStatus_Success = 1 -WGPUSurfaceGetCurrentTextureStatus_Timeout = 2 -WGPUSurfaceGetCurrentTextureStatus_Outdated = 3 -WGPUSurfaceGetCurrentTextureStatus_Lost = 4 -WGPUSurfaceGetCurrentTextureStatus_OutOfMemory = 5 -WGPUSurfaceGetCurrentTextureStatus_DeviceLost = 6 -WGPUSurfaceGetCurrentTextureStatus_Error = 7 -WGPUSurfaceGetCurrentTextureStatus_Force32 = 2147483647 -WGPUSurfaceGetCurrentTextureStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureAspect' -WGPUTextureAspect__enumvalues = { - 0: 'WGPUTextureAspect_Undefined', - 1: 'WGPUTextureAspect_All', - 2: 'WGPUTextureAspect_StencilOnly', - 3: 'WGPUTextureAspect_DepthOnly', - 327680: 'WGPUTextureAspect_Plane0Only', - 327681: 'WGPUTextureAspect_Plane1Only', - 327682: 'WGPUTextureAspect_Plane2Only', - 2147483647: 'WGPUTextureAspect_Force32', -} -WGPUTextureAspect_Undefined = 0 -WGPUTextureAspect_All = 1 -WGPUTextureAspect_StencilOnly = 2 -WGPUTextureAspect_DepthOnly = 3 -WGPUTextureAspect_Plane0Only = 327680 -WGPUTextureAspect_Plane1Only = 327681 -WGPUTextureAspect_Plane2Only = 327682 -WGPUTextureAspect_Force32 = 2147483647 -WGPUTextureAspect = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureDimension' -WGPUTextureDimension__enumvalues = { - 0: 'WGPUTextureDimension_Undefined', - 1: 'WGPUTextureDimension_1D', - 2: 'WGPUTextureDimension_2D', - 3: 'WGPUTextureDimension_3D', - 2147483647: 'WGPUTextureDimension_Force32', -} -WGPUTextureDimension_Undefined = 0 -WGPUTextureDimension_1D = 1 -WGPUTextureDimension_2D = 2 -WGPUTextureDimension_3D = 3 -WGPUTextureDimension_Force32 = 2147483647 -WGPUTextureDimension = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureFormat' -WGPUTextureFormat__enumvalues = { - 0: 'WGPUTextureFormat_Undefined', - 1: 'WGPUTextureFormat_R8Unorm', - 2: 'WGPUTextureFormat_R8Snorm', - 3: 'WGPUTextureFormat_R8Uint', - 4: 'WGPUTextureFormat_R8Sint', - 5: 'WGPUTextureFormat_R16Uint', - 6: 'WGPUTextureFormat_R16Sint', - 7: 'WGPUTextureFormat_R16Float', - 8: 'WGPUTextureFormat_RG8Unorm', - 9: 'WGPUTextureFormat_RG8Snorm', - 10: 'WGPUTextureFormat_RG8Uint', - 11: 'WGPUTextureFormat_RG8Sint', - 12: 'WGPUTextureFormat_R32Float', - 13: 'WGPUTextureFormat_R32Uint', - 14: 'WGPUTextureFormat_R32Sint', - 15: 'WGPUTextureFormat_RG16Uint', - 16: 'WGPUTextureFormat_RG16Sint', - 17: 'WGPUTextureFormat_RG16Float', - 18: 'WGPUTextureFormat_RGBA8Unorm', - 19: 'WGPUTextureFormat_RGBA8UnormSrgb', - 20: 'WGPUTextureFormat_RGBA8Snorm', - 21: 'WGPUTextureFormat_RGBA8Uint', - 22: 'WGPUTextureFormat_RGBA8Sint', - 23: 'WGPUTextureFormat_BGRA8Unorm', - 24: 'WGPUTextureFormat_BGRA8UnormSrgb', - 25: 'WGPUTextureFormat_RGB10A2Uint', - 26: 'WGPUTextureFormat_RGB10A2Unorm', - 27: 'WGPUTextureFormat_RG11B10Ufloat', - 28: 'WGPUTextureFormat_RGB9E5Ufloat', - 29: 'WGPUTextureFormat_RG32Float', - 30: 'WGPUTextureFormat_RG32Uint', - 31: 'WGPUTextureFormat_RG32Sint', - 32: 'WGPUTextureFormat_RGBA16Uint', - 33: 'WGPUTextureFormat_RGBA16Sint', - 34: 'WGPUTextureFormat_RGBA16Float', - 35: 'WGPUTextureFormat_RGBA32Float', - 36: 'WGPUTextureFormat_RGBA32Uint', - 37: 'WGPUTextureFormat_RGBA32Sint', - 38: 'WGPUTextureFormat_Stencil8', - 39: 'WGPUTextureFormat_Depth16Unorm', - 40: 'WGPUTextureFormat_Depth24Plus', - 41: 'WGPUTextureFormat_Depth24PlusStencil8', - 42: 'WGPUTextureFormat_Depth32Float', - 43: 'WGPUTextureFormat_Depth32FloatStencil8', - 44: 'WGPUTextureFormat_BC1RGBAUnorm', - 45: 'WGPUTextureFormat_BC1RGBAUnormSrgb', - 46: 'WGPUTextureFormat_BC2RGBAUnorm', - 47: 'WGPUTextureFormat_BC2RGBAUnormSrgb', - 48: 'WGPUTextureFormat_BC3RGBAUnorm', - 49: 'WGPUTextureFormat_BC3RGBAUnormSrgb', - 50: 'WGPUTextureFormat_BC4RUnorm', - 51: 'WGPUTextureFormat_BC4RSnorm', - 52: 'WGPUTextureFormat_BC5RGUnorm', - 53: 'WGPUTextureFormat_BC5RGSnorm', - 54: 'WGPUTextureFormat_BC6HRGBUfloat', - 55: 'WGPUTextureFormat_BC6HRGBFloat', - 56: 'WGPUTextureFormat_BC7RGBAUnorm', - 57: 'WGPUTextureFormat_BC7RGBAUnormSrgb', - 58: 'WGPUTextureFormat_ETC2RGB8Unorm', - 59: 'WGPUTextureFormat_ETC2RGB8UnormSrgb', - 60: 'WGPUTextureFormat_ETC2RGB8A1Unorm', - 61: 'WGPUTextureFormat_ETC2RGB8A1UnormSrgb', - 62: 'WGPUTextureFormat_ETC2RGBA8Unorm', - 63: 'WGPUTextureFormat_ETC2RGBA8UnormSrgb', - 64: 'WGPUTextureFormat_EACR11Unorm', - 65: 'WGPUTextureFormat_EACR11Snorm', - 66: 'WGPUTextureFormat_EACRG11Unorm', - 67: 'WGPUTextureFormat_EACRG11Snorm', - 68: 'WGPUTextureFormat_ASTC4x4Unorm', - 69: 'WGPUTextureFormat_ASTC4x4UnormSrgb', - 70: 'WGPUTextureFormat_ASTC5x4Unorm', - 71: 'WGPUTextureFormat_ASTC5x4UnormSrgb', - 72: 'WGPUTextureFormat_ASTC5x5Unorm', - 73: 'WGPUTextureFormat_ASTC5x5UnormSrgb', - 74: 'WGPUTextureFormat_ASTC6x5Unorm', - 75: 'WGPUTextureFormat_ASTC6x5UnormSrgb', - 76: 'WGPUTextureFormat_ASTC6x6Unorm', - 77: 'WGPUTextureFormat_ASTC6x6UnormSrgb', - 78: 'WGPUTextureFormat_ASTC8x5Unorm', - 79: 'WGPUTextureFormat_ASTC8x5UnormSrgb', - 80: 'WGPUTextureFormat_ASTC8x6Unorm', - 81: 'WGPUTextureFormat_ASTC8x6UnormSrgb', - 82: 'WGPUTextureFormat_ASTC8x8Unorm', - 83: 'WGPUTextureFormat_ASTC8x8UnormSrgb', - 84: 'WGPUTextureFormat_ASTC10x5Unorm', - 85: 'WGPUTextureFormat_ASTC10x5UnormSrgb', - 86: 'WGPUTextureFormat_ASTC10x6Unorm', - 87: 'WGPUTextureFormat_ASTC10x6UnormSrgb', - 88: 'WGPUTextureFormat_ASTC10x8Unorm', - 89: 'WGPUTextureFormat_ASTC10x8UnormSrgb', - 90: 'WGPUTextureFormat_ASTC10x10Unorm', - 91: 'WGPUTextureFormat_ASTC10x10UnormSrgb', - 92: 'WGPUTextureFormat_ASTC12x10Unorm', - 93: 'WGPUTextureFormat_ASTC12x10UnormSrgb', - 94: 'WGPUTextureFormat_ASTC12x12Unorm', - 95: 'WGPUTextureFormat_ASTC12x12UnormSrgb', - 327680: 'WGPUTextureFormat_R16Unorm', - 327681: 'WGPUTextureFormat_RG16Unorm', - 327682: 'WGPUTextureFormat_RGBA16Unorm', - 327683: 'WGPUTextureFormat_R16Snorm', - 327684: 'WGPUTextureFormat_RG16Snorm', - 327685: 'WGPUTextureFormat_RGBA16Snorm', - 327686: 'WGPUTextureFormat_R8BG8Biplanar420Unorm', - 327687: 'WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm', - 327688: 'WGPUTextureFormat_R8BG8A8Triplanar420Unorm', - 327689: 'WGPUTextureFormat_R8BG8Biplanar422Unorm', - 327690: 'WGPUTextureFormat_R8BG8Biplanar444Unorm', - 327691: 'WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm', - 327692: 'WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm', - 327693: 'WGPUTextureFormat_External', - 2147483647: 'WGPUTextureFormat_Force32', -} -WGPUTextureFormat_Undefined = 0 -WGPUTextureFormat_R8Unorm = 1 -WGPUTextureFormat_R8Snorm = 2 -WGPUTextureFormat_R8Uint = 3 -WGPUTextureFormat_R8Sint = 4 -WGPUTextureFormat_R16Uint = 5 -WGPUTextureFormat_R16Sint = 6 -WGPUTextureFormat_R16Float = 7 -WGPUTextureFormat_RG8Unorm = 8 -WGPUTextureFormat_RG8Snorm = 9 -WGPUTextureFormat_RG8Uint = 10 -WGPUTextureFormat_RG8Sint = 11 -WGPUTextureFormat_R32Float = 12 -WGPUTextureFormat_R32Uint = 13 -WGPUTextureFormat_R32Sint = 14 -WGPUTextureFormat_RG16Uint = 15 -WGPUTextureFormat_RG16Sint = 16 -WGPUTextureFormat_RG16Float = 17 -WGPUTextureFormat_RGBA8Unorm = 18 -WGPUTextureFormat_RGBA8UnormSrgb = 19 -WGPUTextureFormat_RGBA8Snorm = 20 -WGPUTextureFormat_RGBA8Uint = 21 -WGPUTextureFormat_RGBA8Sint = 22 -WGPUTextureFormat_BGRA8Unorm = 23 -WGPUTextureFormat_BGRA8UnormSrgb = 24 -WGPUTextureFormat_RGB10A2Uint = 25 -WGPUTextureFormat_RGB10A2Unorm = 26 -WGPUTextureFormat_RG11B10Ufloat = 27 -WGPUTextureFormat_RGB9E5Ufloat = 28 -WGPUTextureFormat_RG32Float = 29 -WGPUTextureFormat_RG32Uint = 30 -WGPUTextureFormat_RG32Sint = 31 -WGPUTextureFormat_RGBA16Uint = 32 -WGPUTextureFormat_RGBA16Sint = 33 -WGPUTextureFormat_RGBA16Float = 34 -WGPUTextureFormat_RGBA32Float = 35 -WGPUTextureFormat_RGBA32Uint = 36 -WGPUTextureFormat_RGBA32Sint = 37 -WGPUTextureFormat_Stencil8 = 38 -WGPUTextureFormat_Depth16Unorm = 39 -WGPUTextureFormat_Depth24Plus = 40 -WGPUTextureFormat_Depth24PlusStencil8 = 41 -WGPUTextureFormat_Depth32Float = 42 -WGPUTextureFormat_Depth32FloatStencil8 = 43 -WGPUTextureFormat_BC1RGBAUnorm = 44 -WGPUTextureFormat_BC1RGBAUnormSrgb = 45 -WGPUTextureFormat_BC2RGBAUnorm = 46 -WGPUTextureFormat_BC2RGBAUnormSrgb = 47 -WGPUTextureFormat_BC3RGBAUnorm = 48 -WGPUTextureFormat_BC3RGBAUnormSrgb = 49 -WGPUTextureFormat_BC4RUnorm = 50 -WGPUTextureFormat_BC4RSnorm = 51 -WGPUTextureFormat_BC5RGUnorm = 52 -WGPUTextureFormat_BC5RGSnorm = 53 -WGPUTextureFormat_BC6HRGBUfloat = 54 -WGPUTextureFormat_BC6HRGBFloat = 55 -WGPUTextureFormat_BC7RGBAUnorm = 56 -WGPUTextureFormat_BC7RGBAUnormSrgb = 57 -WGPUTextureFormat_ETC2RGB8Unorm = 58 -WGPUTextureFormat_ETC2RGB8UnormSrgb = 59 -WGPUTextureFormat_ETC2RGB8A1Unorm = 60 -WGPUTextureFormat_ETC2RGB8A1UnormSrgb = 61 -WGPUTextureFormat_ETC2RGBA8Unorm = 62 -WGPUTextureFormat_ETC2RGBA8UnormSrgb = 63 -WGPUTextureFormat_EACR11Unorm = 64 -WGPUTextureFormat_EACR11Snorm = 65 -WGPUTextureFormat_EACRG11Unorm = 66 -WGPUTextureFormat_EACRG11Snorm = 67 -WGPUTextureFormat_ASTC4x4Unorm = 68 -WGPUTextureFormat_ASTC4x4UnormSrgb = 69 -WGPUTextureFormat_ASTC5x4Unorm = 70 -WGPUTextureFormat_ASTC5x4UnormSrgb = 71 -WGPUTextureFormat_ASTC5x5Unorm = 72 -WGPUTextureFormat_ASTC5x5UnormSrgb = 73 -WGPUTextureFormat_ASTC6x5Unorm = 74 -WGPUTextureFormat_ASTC6x5UnormSrgb = 75 -WGPUTextureFormat_ASTC6x6Unorm = 76 -WGPUTextureFormat_ASTC6x6UnormSrgb = 77 -WGPUTextureFormat_ASTC8x5Unorm = 78 -WGPUTextureFormat_ASTC8x5UnormSrgb = 79 -WGPUTextureFormat_ASTC8x6Unorm = 80 -WGPUTextureFormat_ASTC8x6UnormSrgb = 81 -WGPUTextureFormat_ASTC8x8Unorm = 82 -WGPUTextureFormat_ASTC8x8UnormSrgb = 83 -WGPUTextureFormat_ASTC10x5Unorm = 84 -WGPUTextureFormat_ASTC10x5UnormSrgb = 85 -WGPUTextureFormat_ASTC10x6Unorm = 86 -WGPUTextureFormat_ASTC10x6UnormSrgb = 87 -WGPUTextureFormat_ASTC10x8Unorm = 88 -WGPUTextureFormat_ASTC10x8UnormSrgb = 89 -WGPUTextureFormat_ASTC10x10Unorm = 90 -WGPUTextureFormat_ASTC10x10UnormSrgb = 91 -WGPUTextureFormat_ASTC12x10Unorm = 92 -WGPUTextureFormat_ASTC12x10UnormSrgb = 93 -WGPUTextureFormat_ASTC12x12Unorm = 94 -WGPUTextureFormat_ASTC12x12UnormSrgb = 95 -WGPUTextureFormat_R16Unorm = 327680 -WGPUTextureFormat_RG16Unorm = 327681 -WGPUTextureFormat_RGBA16Unorm = 327682 -WGPUTextureFormat_R16Snorm = 327683 -WGPUTextureFormat_RG16Snorm = 327684 -WGPUTextureFormat_RGBA16Snorm = 327685 -WGPUTextureFormat_R8BG8Biplanar420Unorm = 327686 -WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm = 327687 -WGPUTextureFormat_R8BG8A8Triplanar420Unorm = 327688 -WGPUTextureFormat_R8BG8Biplanar422Unorm = 327689 -WGPUTextureFormat_R8BG8Biplanar444Unorm = 327690 -WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm = 327691 -WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm = 327692 -WGPUTextureFormat_External = 327693 -WGPUTextureFormat_Force32 = 2147483647 -WGPUTextureFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureSampleType' -WGPUTextureSampleType__enumvalues = { - 0: 'WGPUTextureSampleType_BindingNotUsed', - 1: 'WGPUTextureSampleType_Float', - 2: 'WGPUTextureSampleType_UnfilterableFloat', - 3: 'WGPUTextureSampleType_Depth', - 4: 'WGPUTextureSampleType_Sint', - 5: 'WGPUTextureSampleType_Uint', - 2147483647: 'WGPUTextureSampleType_Force32', -} -WGPUTextureSampleType_BindingNotUsed = 0 -WGPUTextureSampleType_Float = 1 -WGPUTextureSampleType_UnfilterableFloat = 2 -WGPUTextureSampleType_Depth = 3 -WGPUTextureSampleType_Sint = 4 -WGPUTextureSampleType_Uint = 5 -WGPUTextureSampleType_Force32 = 2147483647 -WGPUTextureSampleType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureViewDimension' -WGPUTextureViewDimension__enumvalues = { - 0: 'WGPUTextureViewDimension_Undefined', - 1: 'WGPUTextureViewDimension_1D', - 2: 'WGPUTextureViewDimension_2D', - 3: 'WGPUTextureViewDimension_2DArray', - 4: 'WGPUTextureViewDimension_Cube', - 5: 'WGPUTextureViewDimension_CubeArray', - 6: 'WGPUTextureViewDimension_3D', - 2147483647: 'WGPUTextureViewDimension_Force32', -} -WGPUTextureViewDimension_Undefined = 0 -WGPUTextureViewDimension_1D = 1 -WGPUTextureViewDimension_2D = 2 -WGPUTextureViewDimension_2DArray = 3 -WGPUTextureViewDimension_Cube = 4 -WGPUTextureViewDimension_CubeArray = 5 -WGPUTextureViewDimension_3D = 6 -WGPUTextureViewDimension_Force32 = 2147483647 -WGPUTextureViewDimension = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUVertexFormat' -WGPUVertexFormat__enumvalues = { - 1: 'WGPUVertexFormat_Uint8', - 2: 'WGPUVertexFormat_Uint8x2', - 3: 'WGPUVertexFormat_Uint8x4', - 4: 'WGPUVertexFormat_Sint8', - 5: 'WGPUVertexFormat_Sint8x2', - 6: 'WGPUVertexFormat_Sint8x4', - 7: 'WGPUVertexFormat_Unorm8', - 8: 'WGPUVertexFormat_Unorm8x2', - 9: 'WGPUVertexFormat_Unorm8x4', - 10: 'WGPUVertexFormat_Snorm8', - 11: 'WGPUVertexFormat_Snorm8x2', - 12: 'WGPUVertexFormat_Snorm8x4', - 13: 'WGPUVertexFormat_Uint16', - 14: 'WGPUVertexFormat_Uint16x2', - 15: 'WGPUVertexFormat_Uint16x4', - 16: 'WGPUVertexFormat_Sint16', - 17: 'WGPUVertexFormat_Sint16x2', - 18: 'WGPUVertexFormat_Sint16x4', - 19: 'WGPUVertexFormat_Unorm16', - 20: 'WGPUVertexFormat_Unorm16x2', - 21: 'WGPUVertexFormat_Unorm16x4', - 22: 'WGPUVertexFormat_Snorm16', - 23: 'WGPUVertexFormat_Snorm16x2', - 24: 'WGPUVertexFormat_Snorm16x4', - 25: 'WGPUVertexFormat_Float16', - 26: 'WGPUVertexFormat_Float16x2', - 27: 'WGPUVertexFormat_Float16x4', - 28: 'WGPUVertexFormat_Float32', - 29: 'WGPUVertexFormat_Float32x2', - 30: 'WGPUVertexFormat_Float32x3', - 31: 'WGPUVertexFormat_Float32x4', - 32: 'WGPUVertexFormat_Uint32', - 33: 'WGPUVertexFormat_Uint32x2', - 34: 'WGPUVertexFormat_Uint32x3', - 35: 'WGPUVertexFormat_Uint32x4', - 36: 'WGPUVertexFormat_Sint32', - 37: 'WGPUVertexFormat_Sint32x2', - 38: 'WGPUVertexFormat_Sint32x3', - 39: 'WGPUVertexFormat_Sint32x4', - 40: 'WGPUVertexFormat_Unorm10_10_10_2', - 41: 'WGPUVertexFormat_Unorm8x4BGRA', - 2147483647: 'WGPUVertexFormat_Force32', -} -WGPUVertexFormat_Uint8 = 1 -WGPUVertexFormat_Uint8x2 = 2 -WGPUVertexFormat_Uint8x4 = 3 -WGPUVertexFormat_Sint8 = 4 -WGPUVertexFormat_Sint8x2 = 5 -WGPUVertexFormat_Sint8x4 = 6 -WGPUVertexFormat_Unorm8 = 7 -WGPUVertexFormat_Unorm8x2 = 8 -WGPUVertexFormat_Unorm8x4 = 9 -WGPUVertexFormat_Snorm8 = 10 -WGPUVertexFormat_Snorm8x2 = 11 -WGPUVertexFormat_Snorm8x4 = 12 -WGPUVertexFormat_Uint16 = 13 -WGPUVertexFormat_Uint16x2 = 14 -WGPUVertexFormat_Uint16x4 = 15 -WGPUVertexFormat_Sint16 = 16 -WGPUVertexFormat_Sint16x2 = 17 -WGPUVertexFormat_Sint16x4 = 18 -WGPUVertexFormat_Unorm16 = 19 -WGPUVertexFormat_Unorm16x2 = 20 -WGPUVertexFormat_Unorm16x4 = 21 -WGPUVertexFormat_Snorm16 = 22 -WGPUVertexFormat_Snorm16x2 = 23 -WGPUVertexFormat_Snorm16x4 = 24 -WGPUVertexFormat_Float16 = 25 -WGPUVertexFormat_Float16x2 = 26 -WGPUVertexFormat_Float16x4 = 27 -WGPUVertexFormat_Float32 = 28 -WGPUVertexFormat_Float32x2 = 29 -WGPUVertexFormat_Float32x3 = 30 -WGPUVertexFormat_Float32x4 = 31 -WGPUVertexFormat_Uint32 = 32 -WGPUVertexFormat_Uint32x2 = 33 -WGPUVertexFormat_Uint32x3 = 34 -WGPUVertexFormat_Uint32x4 = 35 -WGPUVertexFormat_Sint32 = 36 -WGPUVertexFormat_Sint32x2 = 37 -WGPUVertexFormat_Sint32x3 = 38 -WGPUVertexFormat_Sint32x4 = 39 -WGPUVertexFormat_Unorm10_10_10_2 = 40 -WGPUVertexFormat_Unorm8x4BGRA = 41 -WGPUVertexFormat_Force32 = 2147483647 -WGPUVertexFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUVertexStepMode' -WGPUVertexStepMode__enumvalues = { - 0: 'WGPUVertexStepMode_Undefined', - 1: 'WGPUVertexStepMode_Vertex', - 2: 'WGPUVertexStepMode_Instance', - 2147483647: 'WGPUVertexStepMode_Force32', -} -WGPUVertexStepMode_Undefined = 0 -WGPUVertexStepMode_Vertex = 1 -WGPUVertexStepMode_Instance = 2 -WGPUVertexStepMode_Force32 = 2147483647 -WGPUVertexStepMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUWaitStatus' -WGPUWaitStatus__enumvalues = { - 1: 'WGPUWaitStatus_Success', - 2: 'WGPUWaitStatus_TimedOut', - 3: 'WGPUWaitStatus_UnsupportedTimeout', - 4: 'WGPUWaitStatus_UnsupportedCount', - 5: 'WGPUWaitStatus_UnsupportedMixedSources', - 6: 'WGPUWaitStatus_Unknown', - 2147483647: 'WGPUWaitStatus_Force32', -} -WGPUWaitStatus_Success = 1 -WGPUWaitStatus_TimedOut = 2 -WGPUWaitStatus_UnsupportedTimeout = 3 -WGPUWaitStatus_UnsupportedCount = 4 -WGPUWaitStatus_UnsupportedMixedSources = 5 -WGPUWaitStatus_Unknown = 6 -WGPUWaitStatus_Force32 = 2147483647 -WGPUWaitStatus = ctypes.c_uint32 # enum -WGPUBufferUsage = ctypes.c_uint64 -WGPUBufferUsage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUBufferUsage_MapRead = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUBufferUsage_MapWrite = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUBufferUsage_CopySrc = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUBufferUsage_CopyDst = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUBufferUsage_Index = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUBufferUsage_Vertex = 0x0000000000000020 # Variable ctypes.c_uint64 -WGPUBufferUsage_Uniform = 0x0000000000000040 # Variable ctypes.c_uint64 -WGPUBufferUsage_Storage = 0x0000000000000080 # Variable ctypes.c_uint64 -WGPUBufferUsage_Indirect = 0x0000000000000100 # Variable ctypes.c_uint64 -WGPUBufferUsage_QueryResolve = 0x0000000000000200 # Variable ctypes.c_uint64 -WGPUColorWriteMask = ctypes.c_uint64 -WGPUColorWriteMask_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Red = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Green = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Blue = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Alpha = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUColorWriteMask_All = 0x000000000000000F # Variable ctypes.c_uint64 -WGPUHeapProperty = ctypes.c_uint64 -WGPUHeapProperty_DeviceLocal = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostVisible = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostCoherent = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostUncached = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostCached = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUMapMode = ctypes.c_uint64 -WGPUMapMode_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUMapMode_Read = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUMapMode_Write = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUShaderStage = ctypes.c_uint64 -WGPUShaderStage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUShaderStage_Vertex = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUShaderStage_Fragment = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUShaderStage_Compute = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUTextureUsage = ctypes.c_uint64 -WGPUTextureUsage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUTextureUsage_CopySrc = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUTextureUsage_CopyDst = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUTextureUsage_TextureBinding = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUTextureUsage_StorageBinding = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUTextureUsage_RenderAttachment = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUTextureUsage_TransientAttachment = 0x0000000000000020 # Variable ctypes.c_uint64 -WGPUTextureUsage_StorageAttachment = 0x0000000000000040 # Variable ctypes.c_uint64 -WGPUBufferMapCallback = ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None)) -WGPUCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_WGPUCompilationInfo(Structure): - pass - -WGPUCompilationInfoCallback = ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None)) -class struct_WGPUStringView(Structure): - pass - -struct_WGPUStringView._pack_ = 1 # source:False -struct_WGPUStringView._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_char)), - ('length', ctypes.c_uint64), -] - -WGPUCreateComputePipelineAsyncCallback = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUCreateRenderPipelineAsyncCallback = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUDawnLoadCacheDataFunction = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)) -WGPUDawnStoreCacheDataFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)) -WGPUDeviceLostCallback = ctypes.CFUNCTYPE(None, WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUDeviceLostCallbackNew = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUErrorCallback = ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPULoggingCallback = ctypes.CFUNCTYPE(None, WGPULoggingType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUPopErrorScopeCallback = ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUProc = ctypes.CFUNCTYPE(None) -WGPUQueueWorkDoneCallback = ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None)) -WGPURequestAdapterCallback = ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPURequestDeviceCallback = ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUBufferMapCallback2 = ctypes.CFUNCTYPE(None, WGPUMapAsyncStatus, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCompilationInfoCallback2 = ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCreateComputePipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCreateRenderPipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUDeviceLostCallback2 = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUPopErrorScopeCallback2 = ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUQueueWorkDoneCallback2 = ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPURequestAdapterCallback2 = ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPURequestDeviceCallback2 = ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUUncapturedErrorCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -class struct_WGPUChainedStruct(Structure): - pass - -struct_WGPUChainedStruct._pack_ = 1 # source:False -struct_WGPUChainedStruct._fields_ = [ - ('next', ctypes.POINTER(struct_WGPUChainedStruct)), - ('sType', WGPUSType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUChainedStruct = struct_WGPUChainedStruct -class struct_WGPUChainedStructOut(Structure): - pass - -struct_WGPUChainedStructOut._pack_ = 1 # source:False -struct_WGPUChainedStructOut._fields_ = [ - ('next', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('sType', WGPUSType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUChainedStructOut = struct_WGPUChainedStructOut -class struct_WGPUBufferMapCallbackInfo2(Structure): - pass - -struct_WGPUBufferMapCallbackInfo2._pack_ = 1 # source:False -struct_WGPUBufferMapCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUMapAsyncStatus, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUBufferMapCallbackInfo2 = struct_WGPUBufferMapCallbackInfo2 -class struct_WGPUCompilationInfoCallbackInfo2(Structure): - pass - -struct_WGPUCompilationInfoCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCompilationInfoCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCompilationInfoCallbackInfo2 = struct_WGPUCompilationInfoCallbackInfo2 -class struct_WGPUCreateComputePipelineAsyncCallbackInfo2(Structure): - pass - -struct_WGPUCreateComputePipelineAsyncCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCreateComputePipelineAsyncCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCreateComputePipelineAsyncCallbackInfo2 = struct_WGPUCreateComputePipelineAsyncCallbackInfo2 -class struct_WGPUCreateRenderPipelineAsyncCallbackInfo2(Structure): - pass - -struct_WGPUCreateRenderPipelineAsyncCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCreateRenderPipelineAsyncCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCreateRenderPipelineAsyncCallbackInfo2 = struct_WGPUCreateRenderPipelineAsyncCallbackInfo2 -class struct_WGPUDeviceLostCallbackInfo2(Structure): - pass - -struct_WGPUDeviceLostCallbackInfo2._pack_ = 1 # source:False -struct_WGPUDeviceLostCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUDeviceLostCallbackInfo2 = struct_WGPUDeviceLostCallbackInfo2 -class struct_WGPUPopErrorScopeCallbackInfo2(Structure): - pass - -struct_WGPUPopErrorScopeCallbackInfo2._pack_ = 1 # source:False -struct_WGPUPopErrorScopeCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUPopErrorScopeCallbackInfo2 = struct_WGPUPopErrorScopeCallbackInfo2 -class struct_WGPUQueueWorkDoneCallbackInfo2(Structure): - pass - -struct_WGPUQueueWorkDoneCallbackInfo2._pack_ = 1 # source:False -struct_WGPUQueueWorkDoneCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUQueueWorkDoneCallbackInfo2 = struct_WGPUQueueWorkDoneCallbackInfo2 -class struct_WGPURequestAdapterCallbackInfo2(Structure): - pass - -struct_WGPURequestAdapterCallbackInfo2._pack_ = 1 # source:False -struct_WGPURequestAdapterCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPURequestAdapterCallbackInfo2 = struct_WGPURequestAdapterCallbackInfo2 -class struct_WGPURequestDeviceCallbackInfo2(Structure): - pass - -struct_WGPURequestDeviceCallbackInfo2._pack_ = 1 # source:False -struct_WGPURequestDeviceCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPURequestDeviceCallbackInfo2 = struct_WGPURequestDeviceCallbackInfo2 -class struct_WGPUUncapturedErrorCallbackInfo2(Structure): - pass - -struct_WGPUUncapturedErrorCallbackInfo2._pack_ = 1 # source:False -struct_WGPUUncapturedErrorCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUUncapturedErrorCallbackInfo2 = struct_WGPUUncapturedErrorCallbackInfo2 -class struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER(Structure): - pass - -struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER._pack_ = 1 # source:False -struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER._fields_ = [ - ('unused', ctypes.c_uint32), -] - -WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER = struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER -class struct_WGPUAdapterPropertiesD3D(Structure): - pass - -struct_WGPUAdapterPropertiesD3D._pack_ = 1 # source:False -struct_WGPUAdapterPropertiesD3D._fields_ = [ - ('chain', WGPUChainedStructOut), - ('shaderModel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUAdapterPropertiesD3D = struct_WGPUAdapterPropertiesD3D -class struct_WGPUAdapterPropertiesSubgroups(Structure): - pass - -struct_WGPUAdapterPropertiesSubgroups._pack_ = 1 # source:False -struct_WGPUAdapterPropertiesSubgroups._fields_ = [ - ('chain', WGPUChainedStructOut), - ('subgroupMinSize', ctypes.c_uint32), - ('subgroupMaxSize', ctypes.c_uint32), -] - -WGPUAdapterPropertiesSubgroups = struct_WGPUAdapterPropertiesSubgroups -class struct_WGPUAdapterPropertiesVk(Structure): - pass - -struct_WGPUAdapterPropertiesVk._pack_ = 1 # source:False -struct_WGPUAdapterPropertiesVk._fields_ = [ - ('chain', WGPUChainedStructOut), - ('driverVersion', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUAdapterPropertiesVk = struct_WGPUAdapterPropertiesVk -class struct_WGPUBindGroupEntry(Structure): - pass - -struct_WGPUBindGroupEntry._pack_ = 1 # source:False -struct_WGPUBindGroupEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('binding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('buffer', ctypes.POINTER(struct_WGPUBufferImpl)), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('sampler', ctypes.POINTER(struct_WGPUSamplerImpl)), - ('textureView', ctypes.POINTER(struct_WGPUTextureViewImpl)), -] - -WGPUBindGroupEntry = struct_WGPUBindGroupEntry -class struct_WGPUBlendComponent(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('operation', WGPUBlendOperation), - ('srcFactor', WGPUBlendFactor), - ('dstFactor', WGPUBlendFactor), - ] - -WGPUBlendComponent = struct_WGPUBlendComponent -class struct_WGPUBufferBindingLayout(Structure): - pass - -struct_WGPUBufferBindingLayout._pack_ = 1 # source:False -struct_WGPUBufferBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('type', WGPUBufferBindingType), - ('hasDynamicOffset', ctypes.c_uint32), - ('minBindingSize', ctypes.c_uint64), -] - -WGPUBufferBindingLayout = struct_WGPUBufferBindingLayout -class struct_WGPUBufferHostMappedPointer(Structure): - pass - -struct_WGPUBufferHostMappedPointer._pack_ = 1 # source:False -struct_WGPUBufferHostMappedPointer._fields_ = [ - ('chain', WGPUChainedStruct), - ('pointer', ctypes.POINTER(None)), - ('disposeCallback', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUBufferHostMappedPointer = struct_WGPUBufferHostMappedPointer -class struct_WGPUBufferMapCallbackInfo(Structure): - pass - -struct_WGPUBufferMapCallbackInfo._pack_ = 1 # source:False -struct_WGPUBufferMapCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUBufferMapCallbackInfo = struct_WGPUBufferMapCallbackInfo -class struct_WGPUColor(Structure): - pass - -struct_WGPUColor._pack_ = 1 # source:False -struct_WGPUColor._fields_ = [ - ('r', ctypes.c_double), - ('g', ctypes.c_double), - ('b', ctypes.c_double), - ('a', ctypes.c_double), -] - -WGPUColor = struct_WGPUColor -class struct_WGPUColorTargetStateExpandResolveTextureDawn(Structure): - pass - -struct_WGPUColorTargetStateExpandResolveTextureDawn._pack_ = 1 # source:False -struct_WGPUColorTargetStateExpandResolveTextureDawn._fields_ = [ - ('chain', WGPUChainedStruct), - ('enabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUColorTargetStateExpandResolveTextureDawn = struct_WGPUColorTargetStateExpandResolveTextureDawn -class struct_WGPUCompilationInfoCallbackInfo(Structure): - pass - -struct_WGPUCompilationInfoCallbackInfo._pack_ = 1 # source:False -struct_WGPUCompilationInfoCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCompilationInfoCallbackInfo = struct_WGPUCompilationInfoCallbackInfo -class struct_WGPUComputePassTimestampWrites(Structure): - pass - -struct_WGPUComputePassTimestampWrites._pack_ = 1 # source:False -struct_WGPUComputePassTimestampWrites._fields_ = [ - ('querySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('beginningOfPassWriteIndex', ctypes.c_uint32), - ('endOfPassWriteIndex', ctypes.c_uint32), -] - -WGPUComputePassTimestampWrites = struct_WGPUComputePassTimestampWrites -class struct_WGPUCopyTextureForBrowserOptions(Structure): - pass - -struct_WGPUCopyTextureForBrowserOptions._pack_ = 1 # source:False -struct_WGPUCopyTextureForBrowserOptions._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('flipY', ctypes.c_uint32), - ('needsColorSpaceConversion', ctypes.c_uint32), - ('srcAlphaMode', WGPUAlphaMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('conversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('dstAlphaMode', WGPUAlphaMode), - ('internalUsage', ctypes.c_uint32), -] - -WGPUCopyTextureForBrowserOptions = struct_WGPUCopyTextureForBrowserOptions -class struct_WGPUCreateComputePipelineAsyncCallbackInfo(Structure): - pass - -struct_WGPUCreateComputePipelineAsyncCallbackInfo._pack_ = 1 # source:False -struct_WGPUCreateComputePipelineAsyncCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCreateComputePipelineAsyncCallbackInfo = struct_WGPUCreateComputePipelineAsyncCallbackInfo -class struct_WGPUCreateRenderPipelineAsyncCallbackInfo(Structure): - pass - -struct_WGPUCreateRenderPipelineAsyncCallbackInfo._pack_ = 1 # source:False -struct_WGPUCreateRenderPipelineAsyncCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCreateRenderPipelineAsyncCallbackInfo = struct_WGPUCreateRenderPipelineAsyncCallbackInfo -class struct_WGPUDawnWGSLBlocklist(Structure): - pass - -struct_WGPUDawnWGSLBlocklist._pack_ = 1 # source:False -struct_WGPUDawnWGSLBlocklist._fields_ = [ - ('chain', WGPUChainedStruct), - ('blocklistedFeatureCount', ctypes.c_uint64), - ('blocklistedFeatures', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), -] - -WGPUDawnWGSLBlocklist = struct_WGPUDawnWGSLBlocklist -class struct_WGPUDawnAdapterPropertiesPowerPreference(Structure): - pass - -struct_WGPUDawnAdapterPropertiesPowerPreference._pack_ = 1 # source:False -struct_WGPUDawnAdapterPropertiesPowerPreference._fields_ = [ - ('chain', WGPUChainedStructOut), - ('powerPreference', WGPUPowerPreference), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnAdapterPropertiesPowerPreference = struct_WGPUDawnAdapterPropertiesPowerPreference -class struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient(Structure): - pass - -struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient._pack_ = 1 # source:False -struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient._fields_ = [ - ('chain', WGPUChainedStruct), - ('outOfMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnBufferDescriptorErrorInfoFromWireClient = struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient -class struct_WGPUDawnEncoderInternalUsageDescriptor(Structure): - pass - -struct_WGPUDawnEncoderInternalUsageDescriptor._pack_ = 1 # source:False -struct_WGPUDawnEncoderInternalUsageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('useInternalUsages', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnEncoderInternalUsageDescriptor = struct_WGPUDawnEncoderInternalUsageDescriptor -class struct_WGPUDawnExperimentalImmediateDataLimits(Structure): - pass - -struct_WGPUDawnExperimentalImmediateDataLimits._pack_ = 1 # source:False -struct_WGPUDawnExperimentalImmediateDataLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('maxImmediateDataRangeByteSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnExperimentalImmediateDataLimits = struct_WGPUDawnExperimentalImmediateDataLimits -class struct_WGPUDawnExperimentalSubgroupLimits(Structure): - pass - -struct_WGPUDawnExperimentalSubgroupLimits._pack_ = 1 # source:False -struct_WGPUDawnExperimentalSubgroupLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('minSubgroupSize', ctypes.c_uint32), - ('maxSubgroupSize', ctypes.c_uint32), -] - -WGPUDawnExperimentalSubgroupLimits = struct_WGPUDawnExperimentalSubgroupLimits -class struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled(Structure): - pass - -struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled._pack_ = 1 # source:False -struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled._fields_ = [ - ('chain', WGPUChainedStruct), - ('implicitSampleCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnRenderPassColorAttachmentRenderToSingleSampled = struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled -class struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor(Structure): - pass - -struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor._pack_ = 1 # source:False -struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('allowNonUniformDerivatives', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnShaderModuleSPIRVOptionsDescriptor = struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor -class struct_WGPUDawnTexelCopyBufferRowAlignmentLimits(Structure): - pass - -struct_WGPUDawnTexelCopyBufferRowAlignmentLimits._pack_ = 1 # source:False -struct_WGPUDawnTexelCopyBufferRowAlignmentLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('minTexelCopyBufferRowAlignment', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnTexelCopyBufferRowAlignmentLimits = struct_WGPUDawnTexelCopyBufferRowAlignmentLimits -class struct_WGPUDawnTextureInternalUsageDescriptor(Structure): - pass - -struct_WGPUDawnTextureInternalUsageDescriptor._pack_ = 1 # source:False -struct_WGPUDawnTextureInternalUsageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('internalUsage', ctypes.c_uint64), -] - -WGPUDawnTextureInternalUsageDescriptor = struct_WGPUDawnTextureInternalUsageDescriptor -class struct_WGPUDawnTogglesDescriptor(Structure): - pass - -struct_WGPUDawnTogglesDescriptor._pack_ = 1 # source:False -struct_WGPUDawnTogglesDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('enabledToggleCount', ctypes.c_uint64), - ('enabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), - ('disabledToggleCount', ctypes.c_uint64), - ('disabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), -] - -WGPUDawnTogglesDescriptor = struct_WGPUDawnTogglesDescriptor -class struct_WGPUDawnWireWGSLControl(Structure): - pass - -struct_WGPUDawnWireWGSLControl._pack_ = 1 # source:False -struct_WGPUDawnWireWGSLControl._fields_ = [ - ('chain', WGPUChainedStruct), - ('enableExperimental', ctypes.c_uint32), - ('enableUnsafe', ctypes.c_uint32), - ('enableTesting', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnWireWGSLControl = struct_WGPUDawnWireWGSLControl -class struct_WGPUDeviceLostCallbackInfo(Structure): - pass - -struct_WGPUDeviceLostCallbackInfo._pack_ = 1 # source:False -struct_WGPUDeviceLostCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUDeviceLostCallbackInfo = struct_WGPUDeviceLostCallbackInfo -class struct_WGPUDrmFormatProperties(Structure): - pass - -struct_WGPUDrmFormatProperties._pack_ = 1 # source:False -struct_WGPUDrmFormatProperties._fields_ = [ - ('modifier', ctypes.c_uint64), - ('modifierPlaneCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDrmFormatProperties = struct_WGPUDrmFormatProperties -class struct_WGPUExtent2D(Structure): - pass - -struct_WGPUExtent2D._pack_ = 1 # source:False -struct_WGPUExtent2D._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), -] - -WGPUExtent2D = struct_WGPUExtent2D -class struct_WGPUExtent3D(Structure): - pass - -struct_WGPUExtent3D._pack_ = 1 # source:False -struct_WGPUExtent3D._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depthOrArrayLayers', ctypes.c_uint32), -] - -WGPUExtent3D = struct_WGPUExtent3D -class struct_WGPUExternalTextureBindingEntry(Structure): - pass - -struct_WGPUExternalTextureBindingEntry._pack_ = 1 # source:False -struct_WGPUExternalTextureBindingEntry._fields_ = [ - ('chain', WGPUChainedStruct), - ('externalTexture', ctypes.POINTER(struct_WGPUExternalTextureImpl)), -] - -WGPUExternalTextureBindingEntry = struct_WGPUExternalTextureBindingEntry -class struct_WGPUExternalTextureBindingLayout(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ] - -WGPUExternalTextureBindingLayout = struct_WGPUExternalTextureBindingLayout -class struct_WGPUFormatCapabilities(Structure): - pass - -struct_WGPUFormatCapabilities._pack_ = 1 # source:False -struct_WGPUFormatCapabilities._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), -] - -WGPUFormatCapabilities = struct_WGPUFormatCapabilities -class struct_WGPUFuture(Structure): - pass - -struct_WGPUFuture._pack_ = 1 # source:False -struct_WGPUFuture._fields_ = [ - ('id', ctypes.c_uint64), -] - -WGPUFuture = struct_WGPUFuture -class struct_WGPUInstanceFeatures(Structure): - pass - -struct_WGPUInstanceFeatures._pack_ = 1 # source:False -struct_WGPUInstanceFeatures._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('timedWaitAnyEnable', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timedWaitAnyMaxCount', ctypes.c_uint64), -] - -WGPUInstanceFeatures = struct_WGPUInstanceFeatures -class struct_WGPULimits(Structure): - pass - -struct_WGPULimits._pack_ = 1 # source:False -struct_WGPULimits._fields_ = [ - ('maxTextureDimension1D', ctypes.c_uint32), - ('maxTextureDimension2D', ctypes.c_uint32), - ('maxTextureDimension3D', ctypes.c_uint32), - ('maxTextureArrayLayers', ctypes.c_uint32), - ('maxBindGroups', ctypes.c_uint32), - ('maxBindGroupsPlusVertexBuffers', ctypes.c_uint32), - ('maxBindingsPerBindGroup', ctypes.c_uint32), - ('maxDynamicUniformBuffersPerPipelineLayout', ctypes.c_uint32), - ('maxDynamicStorageBuffersPerPipelineLayout', ctypes.c_uint32), - ('maxSampledTexturesPerShaderStage', ctypes.c_uint32), - ('maxSamplersPerShaderStage', ctypes.c_uint32), - ('maxStorageBuffersPerShaderStage', ctypes.c_uint32), - ('maxStorageTexturesPerShaderStage', ctypes.c_uint32), - ('maxUniformBuffersPerShaderStage', ctypes.c_uint32), - ('maxUniformBufferBindingSize', ctypes.c_uint64), - ('maxStorageBufferBindingSize', ctypes.c_uint64), - ('minUniformBufferOffsetAlignment', ctypes.c_uint32), - ('minStorageBufferOffsetAlignment', ctypes.c_uint32), - ('maxVertexBuffers', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('maxBufferSize', ctypes.c_uint64), - ('maxVertexAttributes', ctypes.c_uint32), - ('maxVertexBufferArrayStride', ctypes.c_uint32), - ('maxInterStageShaderComponents', ctypes.c_uint32), - ('maxInterStageShaderVariables', ctypes.c_uint32), - ('maxColorAttachments', ctypes.c_uint32), - ('maxColorAttachmentBytesPerSample', ctypes.c_uint32), - ('maxComputeWorkgroupStorageSize', ctypes.c_uint32), - ('maxComputeInvocationsPerWorkgroup', ctypes.c_uint32), - ('maxComputeWorkgroupSizeX', ctypes.c_uint32), - ('maxComputeWorkgroupSizeY', ctypes.c_uint32), - ('maxComputeWorkgroupSizeZ', ctypes.c_uint32), - ('maxComputeWorkgroupsPerDimension', ctypes.c_uint32), - ('maxStorageBuffersInVertexStage', ctypes.c_uint32), - ('maxStorageTexturesInVertexStage', ctypes.c_uint32), - ('maxStorageBuffersInFragmentStage', ctypes.c_uint32), - ('maxStorageTexturesInFragmentStage', ctypes.c_uint32), -] - -WGPULimits = struct_WGPULimits -class struct_WGPUMemoryHeapInfo(Structure): - pass - -struct_WGPUMemoryHeapInfo._pack_ = 1 # source:False -struct_WGPUMemoryHeapInfo._fields_ = [ - ('properties', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -WGPUMemoryHeapInfo = struct_WGPUMemoryHeapInfo -class struct_WGPUMultisampleState(Structure): - pass - -struct_WGPUMultisampleState._pack_ = 1 # source:False -struct_WGPUMultisampleState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('count', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('alphaToCoverageEnabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUMultisampleState = struct_WGPUMultisampleState -class struct_WGPUOrigin2D(Structure): - pass - -struct_WGPUOrigin2D._pack_ = 1 # source:False -struct_WGPUOrigin2D._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), -] - -WGPUOrigin2D = struct_WGPUOrigin2D -class struct_WGPUOrigin3D(Structure): - pass - -struct_WGPUOrigin3D._pack_ = 1 # source:False -struct_WGPUOrigin3D._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -WGPUOrigin3D = struct_WGPUOrigin3D -class struct_WGPUPipelineLayoutStorageAttachment(Structure): - pass - -struct_WGPUPipelineLayoutStorageAttachment._pack_ = 1 # source:False -struct_WGPUPipelineLayoutStorageAttachment._fields_ = [ - ('offset', ctypes.c_uint64), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUPipelineLayoutStorageAttachment = struct_WGPUPipelineLayoutStorageAttachment -class struct_WGPUPopErrorScopeCallbackInfo(Structure): - pass - -struct_WGPUPopErrorScopeCallbackInfo._pack_ = 1 # source:False -struct_WGPUPopErrorScopeCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('oldCallback', ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUPopErrorScopeCallbackInfo = struct_WGPUPopErrorScopeCallbackInfo -class struct_WGPUPrimitiveState(Structure): - pass - -struct_WGPUPrimitiveState._pack_ = 1 # source:False -struct_WGPUPrimitiveState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('topology', WGPUPrimitiveTopology), - ('stripIndexFormat', WGPUIndexFormat), - ('frontFace', WGPUFrontFace), - ('cullMode', WGPUCullMode), - ('unclippedDepth', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUPrimitiveState = struct_WGPUPrimitiveState -class struct_WGPUQueueWorkDoneCallbackInfo(Structure): - pass - -struct_WGPUQueueWorkDoneCallbackInfo._pack_ = 1 # source:False -struct_WGPUQueueWorkDoneCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUQueueWorkDoneCallbackInfo = struct_WGPUQueueWorkDoneCallbackInfo -class struct_WGPURenderPassDepthStencilAttachment(Structure): - pass - -struct_WGPURenderPassDepthStencilAttachment._pack_ = 1 # source:False -struct_WGPURenderPassDepthStencilAttachment._fields_ = [ - ('view', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('depthLoadOp', WGPULoadOp), - ('depthStoreOp', WGPUStoreOp), - ('depthClearValue', ctypes.c_float), - ('depthReadOnly', ctypes.c_uint32), - ('stencilLoadOp', WGPULoadOp), - ('stencilStoreOp', WGPUStoreOp), - ('stencilClearValue', ctypes.c_uint32), - ('stencilReadOnly', ctypes.c_uint32), -] - -WGPURenderPassDepthStencilAttachment = struct_WGPURenderPassDepthStencilAttachment -class struct_WGPURenderPassDescriptorExpandResolveRect(Structure): - pass - -struct_WGPURenderPassDescriptorExpandResolveRect._pack_ = 1 # source:False -struct_WGPURenderPassDescriptorExpandResolveRect._fields_ = [ - ('chain', WGPUChainedStruct), - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), -] - -WGPURenderPassDescriptorExpandResolveRect = struct_WGPURenderPassDescriptorExpandResolveRect -class struct_WGPURenderPassMaxDrawCount(Structure): - pass - -struct_WGPURenderPassMaxDrawCount._pack_ = 1 # source:False -struct_WGPURenderPassMaxDrawCount._fields_ = [ - ('chain', WGPUChainedStruct), - ('maxDrawCount', ctypes.c_uint64), -] - -WGPURenderPassMaxDrawCount = struct_WGPURenderPassMaxDrawCount -class struct_WGPURenderPassTimestampWrites(Structure): - pass - -struct_WGPURenderPassTimestampWrites._pack_ = 1 # source:False -struct_WGPURenderPassTimestampWrites._fields_ = [ - ('querySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('beginningOfPassWriteIndex', ctypes.c_uint32), - ('endOfPassWriteIndex', ctypes.c_uint32), -] - -WGPURenderPassTimestampWrites = struct_WGPURenderPassTimestampWrites -class struct_WGPURequestAdapterCallbackInfo(Structure): - pass - -struct_WGPURequestAdapterCallbackInfo._pack_ = 1 # source:False -struct_WGPURequestAdapterCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPURequestAdapterCallbackInfo = struct_WGPURequestAdapterCallbackInfo -class struct_WGPURequestAdapterOptions(Structure): - pass - -struct_WGPURequestAdapterOptions._pack_ = 1 # source:False -struct_WGPURequestAdapterOptions._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('compatibleSurface', ctypes.POINTER(struct_WGPUSurfaceImpl)), - ('featureLevel', WGPUFeatureLevel), - ('powerPreference', WGPUPowerPreference), - ('backendType', WGPUBackendType), - ('forceFallbackAdapter', ctypes.c_uint32), - ('compatibilityMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPURequestAdapterOptions = struct_WGPURequestAdapterOptions -class struct_WGPURequestDeviceCallbackInfo(Structure): - pass - -struct_WGPURequestDeviceCallbackInfo._pack_ = 1 # source:False -struct_WGPURequestDeviceCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPURequestDeviceCallbackInfo = struct_WGPURequestDeviceCallbackInfo -class struct_WGPUSamplerBindingLayout(Structure): - pass - -struct_WGPUSamplerBindingLayout._pack_ = 1 # source:False -struct_WGPUSamplerBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('type', WGPUSamplerBindingType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSamplerBindingLayout = struct_WGPUSamplerBindingLayout -class struct_WGPUShaderModuleCompilationOptions(Structure): - pass - -struct_WGPUShaderModuleCompilationOptions._pack_ = 1 # source:False -struct_WGPUShaderModuleCompilationOptions._fields_ = [ - ('chain', WGPUChainedStruct), - ('strictMath', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUShaderModuleCompilationOptions = struct_WGPUShaderModuleCompilationOptions -class struct_WGPUShaderSourceSPIRV(Structure): - pass - -struct_WGPUShaderSourceSPIRV._pack_ = 1 # source:False -struct_WGPUShaderSourceSPIRV._fields_ = [ - ('chain', WGPUChainedStruct), - ('codeSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('code', ctypes.POINTER(ctypes.c_uint32)), -] - -WGPUShaderSourceSPIRV = struct_WGPUShaderSourceSPIRV -class struct_WGPUSharedBufferMemoryBeginAccessDescriptor(Structure): - pass - -struct_WGPUSharedBufferMemoryBeginAccessDescriptor._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryBeginAccessDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedBufferMemoryBeginAccessDescriptor = struct_WGPUSharedBufferMemoryBeginAccessDescriptor -class struct_WGPUSharedBufferMemoryEndAccessState(Structure): - pass - -struct_WGPUSharedBufferMemoryEndAccessState._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryEndAccessState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedBufferMemoryEndAccessState = struct_WGPUSharedBufferMemoryEndAccessState -class struct_WGPUSharedBufferMemoryProperties(Structure): - pass - -struct_WGPUSharedBufferMemoryProperties._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryProperties._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usage', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -WGPUSharedBufferMemoryProperties = struct_WGPUSharedBufferMemoryProperties -class struct_WGPUSharedFenceDXGISharedHandleDescriptor(Structure): - pass - -struct_WGPUSharedFenceDXGISharedHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceDXGISharedHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), -] - -WGPUSharedFenceDXGISharedHandleDescriptor = struct_WGPUSharedFenceDXGISharedHandleDescriptor -class struct_WGPUSharedFenceDXGISharedHandleExportInfo(Structure): - pass - -struct_WGPUSharedFenceDXGISharedHandleExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceDXGISharedHandleExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.POINTER(None)), -] - -WGPUSharedFenceDXGISharedHandleExportInfo = struct_WGPUSharedFenceDXGISharedHandleExportInfo -class struct_WGPUSharedFenceMTLSharedEventDescriptor(Structure): - pass - -struct_WGPUSharedFenceMTLSharedEventDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceMTLSharedEventDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('sharedEvent', ctypes.POINTER(None)), -] - -WGPUSharedFenceMTLSharedEventDescriptor = struct_WGPUSharedFenceMTLSharedEventDescriptor -class struct_WGPUSharedFenceMTLSharedEventExportInfo(Structure): - pass - -struct_WGPUSharedFenceMTLSharedEventExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceMTLSharedEventExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('sharedEvent', ctypes.POINTER(None)), -] - -WGPUSharedFenceMTLSharedEventExportInfo = struct_WGPUSharedFenceMTLSharedEventExportInfo -class struct_WGPUSharedFenceExportInfo(Structure): - pass - -struct_WGPUSharedFenceExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceExportInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('type', WGPUSharedFenceType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceExportInfo = struct_WGPUSharedFenceExportInfo -class struct_WGPUSharedFenceSyncFDDescriptor(Structure): - pass - -struct_WGPUSharedFenceSyncFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceSyncFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceSyncFDDescriptor = struct_WGPUSharedFenceSyncFDDescriptor -class struct_WGPUSharedFenceSyncFDExportInfo(Structure): - pass - -struct_WGPUSharedFenceSyncFDExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceSyncFDExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceSyncFDExportInfo = struct_WGPUSharedFenceSyncFDExportInfo -class struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor = struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor -class struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo = struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo -class struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreZirconHandleDescriptor = struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor -class struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreZirconHandleExportInfo = struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo -class struct_WGPUSharedTextureMemoryD3DSwapchainBeginState(Structure): - pass - -struct_WGPUSharedTextureMemoryD3DSwapchainBeginState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryD3DSwapchainBeginState._fields_ = [ - ('chain', WGPUChainedStruct), - ('isSwapchain', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryD3DSwapchainBeginState = struct_WGPUSharedTextureMemoryD3DSwapchainBeginState -class struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), - ('useKeyedMutex', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryDXGISharedHandleDescriptor = struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor -class struct_WGPUSharedTextureMemoryEGLImageDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryEGLImageDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryEGLImageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('image', ctypes.POINTER(None)), -] - -WGPUSharedTextureMemoryEGLImageDescriptor = struct_WGPUSharedTextureMemoryEGLImageDescriptor -class struct_WGPUSharedTextureMemoryIOSurfaceDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryIOSurfaceDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryIOSurfaceDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('ioSurface', ctypes.POINTER(None)), -] - -WGPUSharedTextureMemoryIOSurfaceDescriptor = struct_WGPUSharedTextureMemoryIOSurfaceDescriptor -class struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), - ('useExternalFormat', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryAHardwareBufferDescriptor = struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor -class struct_WGPUSharedTextureMemoryBeginAccessDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryBeginAccessDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryBeginAccessDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('concurrentRead', ctypes.c_uint32), - ('initialized', ctypes.c_uint32), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedTextureMemoryBeginAccessDescriptor = struct_WGPUSharedTextureMemoryBeginAccessDescriptor -class struct_WGPUSharedTextureMemoryDmaBufPlane(Structure): - pass - -struct_WGPUSharedTextureMemoryDmaBufPlane._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDmaBufPlane._fields_ = [ - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('stride', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryDmaBufPlane = struct_WGPUSharedTextureMemoryDmaBufPlane -class struct_WGPUSharedTextureMemoryEndAccessState(Structure): - pass - -struct_WGPUSharedTextureMemoryEndAccessState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryEndAccessState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedTextureMemoryEndAccessState = struct_WGPUSharedTextureMemoryEndAccessState -class struct_WGPUSharedTextureMemoryOpaqueFDDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryOpaqueFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryOpaqueFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('vkImageCreateInfo', ctypes.POINTER(None)), - ('memoryFD', ctypes.c_int32), - ('memoryTypeIndex', ctypes.c_uint32), - ('allocationSize', ctypes.c_uint64), - ('dedicatedAllocation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryOpaqueFDDescriptor = struct_WGPUSharedTextureMemoryOpaqueFDDescriptor -class struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('dedicatedAllocation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor = struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor -class struct_WGPUSharedTextureMemoryVkImageLayoutBeginState(Structure): - pass - -struct_WGPUSharedTextureMemoryVkImageLayoutBeginState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkImageLayoutBeginState._fields_ = [ - ('chain', WGPUChainedStruct), - ('oldLayout', ctypes.c_int32), - ('newLayout', ctypes.c_int32), -] - -WGPUSharedTextureMemoryVkImageLayoutBeginState = struct_WGPUSharedTextureMemoryVkImageLayoutBeginState -class struct_WGPUSharedTextureMemoryVkImageLayoutEndState(Structure): - pass - -struct_WGPUSharedTextureMemoryVkImageLayoutEndState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkImageLayoutEndState._fields_ = [ - ('chain', WGPUChainedStructOut), - ('oldLayout', ctypes.c_int32), - ('newLayout', ctypes.c_int32), -] - -WGPUSharedTextureMemoryVkImageLayoutEndState = struct_WGPUSharedTextureMemoryVkImageLayoutEndState -class struct_WGPUSharedTextureMemoryZirconHandleDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryZirconHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryZirconHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('memoryFD', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('allocationSize', ctypes.c_uint64), -] - -WGPUSharedTextureMemoryZirconHandleDescriptor = struct_WGPUSharedTextureMemoryZirconHandleDescriptor -class struct_WGPUStaticSamplerBindingLayout(Structure): - pass - -struct_WGPUStaticSamplerBindingLayout._pack_ = 1 # source:False -struct_WGPUStaticSamplerBindingLayout._fields_ = [ - ('chain', WGPUChainedStruct), - ('sampler', ctypes.POINTER(struct_WGPUSamplerImpl)), - ('sampledTextureBinding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUStaticSamplerBindingLayout = struct_WGPUStaticSamplerBindingLayout -class struct_WGPUStencilFaceState(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('compare', WGPUCompareFunction), - ('failOp', WGPUStencilOperation), - ('depthFailOp', WGPUStencilOperation), - ('passOp', WGPUStencilOperation), - ] - -WGPUStencilFaceState = struct_WGPUStencilFaceState -class struct_WGPUStorageTextureBindingLayout(Structure): - pass - -struct_WGPUStorageTextureBindingLayout._pack_ = 1 # source:False -struct_WGPUStorageTextureBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('access', WGPUStorageTextureAccess), - ('format', WGPUTextureFormat), - ('viewDimension', WGPUTextureViewDimension), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUStorageTextureBindingLayout = struct_WGPUStorageTextureBindingLayout -WGPUStringView = struct_WGPUStringView -class struct_WGPUSupportedFeatures(Structure): - pass - -struct_WGPUSupportedFeatures._pack_ = 1 # source:False -struct_WGPUSupportedFeatures._fields_ = [ - ('featureCount', ctypes.c_uint64), - ('features', ctypes.POINTER(WGPUFeatureName)), -] - -WGPUSupportedFeatures = struct_WGPUSupportedFeatures -class struct_WGPUSurfaceCapabilities(Structure): - pass - -struct_WGPUSurfaceCapabilities._pack_ = 1 # source:False -struct_WGPUSurfaceCapabilities._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usages', ctypes.c_uint64), - ('formatCount', ctypes.c_uint64), - ('formats', ctypes.POINTER(WGPUTextureFormat)), - ('presentModeCount', ctypes.c_uint64), - ('presentModes', ctypes.POINTER(WGPUPresentMode)), - ('alphaModeCount', ctypes.c_uint64), - ('alphaModes', ctypes.POINTER(WGPUCompositeAlphaMode)), -] - -WGPUSurfaceCapabilities = struct_WGPUSurfaceCapabilities -class struct_WGPUSurfaceConfiguration(Structure): - pass - -struct_WGPUSurfaceConfiguration._pack_ = 1 # source:False -struct_WGPUSurfaceConfiguration._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('device', ctypes.POINTER(struct_WGPUDeviceImpl)), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('usage', ctypes.c_uint64), - ('viewFormatCount', ctypes.c_uint64), - ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), - ('alphaMode', WGPUCompositeAlphaMode), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('presentMode', WGPUPresentMode), -] - -WGPUSurfaceConfiguration = struct_WGPUSurfaceConfiguration -class struct_WGPUSurfaceDescriptorFromWindowsCoreWindow(Structure): - pass - -struct_WGPUSurfaceDescriptorFromWindowsCoreWindow._pack_ = 1 # source:False -struct_WGPUSurfaceDescriptorFromWindowsCoreWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('coreWindow', ctypes.POINTER(None)), -] - -WGPUSurfaceDescriptorFromWindowsCoreWindow = struct_WGPUSurfaceDescriptorFromWindowsCoreWindow -class struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel(Structure): - pass - -struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel._pack_ = 1 # source:False -struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel._fields_ = [ - ('chain', WGPUChainedStruct), - ('swapChainPanel', ctypes.POINTER(None)), -] - -WGPUSurfaceDescriptorFromWindowsSwapChainPanel = struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel -class struct_WGPUSurfaceSourceXCBWindow(Structure): - pass - -struct_WGPUSurfaceSourceXCBWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceXCBWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('connection', ctypes.POINTER(None)), - ('window', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSurfaceSourceXCBWindow = struct_WGPUSurfaceSourceXCBWindow -class struct_WGPUSurfaceSourceAndroidNativeWindow(Structure): - pass - -struct_WGPUSurfaceSourceAndroidNativeWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceAndroidNativeWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('window', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceAndroidNativeWindow = struct_WGPUSurfaceSourceAndroidNativeWindow -class struct_WGPUSurfaceSourceMetalLayer(Structure): - pass - -struct_WGPUSurfaceSourceMetalLayer._pack_ = 1 # source:False -struct_WGPUSurfaceSourceMetalLayer._fields_ = [ - ('chain', WGPUChainedStruct), - ('layer', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceMetalLayer = struct_WGPUSurfaceSourceMetalLayer -class struct_WGPUSurfaceSourceWaylandSurface(Structure): - pass - -struct_WGPUSurfaceSourceWaylandSurface._pack_ = 1 # source:False -struct_WGPUSurfaceSourceWaylandSurface._fields_ = [ - ('chain', WGPUChainedStruct), - ('display', ctypes.POINTER(None)), - ('surface', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceWaylandSurface = struct_WGPUSurfaceSourceWaylandSurface -class struct_WGPUSurfaceSourceWindowsHWND(Structure): - pass - -struct_WGPUSurfaceSourceWindowsHWND._pack_ = 1 # source:False -struct_WGPUSurfaceSourceWindowsHWND._fields_ = [ - ('chain', WGPUChainedStruct), - ('hinstance', ctypes.POINTER(None)), - ('hwnd', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceWindowsHWND = struct_WGPUSurfaceSourceWindowsHWND -class struct_WGPUSurfaceSourceXlibWindow(Structure): - pass - -struct_WGPUSurfaceSourceXlibWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceXlibWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('display', ctypes.POINTER(None)), - ('window', ctypes.c_uint64), -] - -WGPUSurfaceSourceXlibWindow = struct_WGPUSurfaceSourceXlibWindow -class struct_WGPUSurfaceTexture(Structure): - pass - -struct_WGPUSurfaceTexture._pack_ = 1 # source:False -struct_WGPUSurfaceTexture._fields_ = [ - ('texture', ctypes.POINTER(struct_WGPUTextureImpl)), - ('suboptimal', ctypes.c_uint32), - ('status', WGPUSurfaceGetCurrentTextureStatus), -] - -WGPUSurfaceTexture = struct_WGPUSurfaceTexture -class struct_WGPUTextureBindingLayout(Structure): - pass - -struct_WGPUTextureBindingLayout._pack_ = 1 # source:False -struct_WGPUTextureBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('sampleType', WGPUTextureSampleType), - ('viewDimension', WGPUTextureViewDimension), - ('multisampled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUTextureBindingLayout = struct_WGPUTextureBindingLayout -class struct_WGPUTextureBindingViewDimensionDescriptor(Structure): - pass - -struct_WGPUTextureBindingViewDimensionDescriptor._pack_ = 1 # source:False -struct_WGPUTextureBindingViewDimensionDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('textureBindingViewDimension', WGPUTextureViewDimension), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUTextureBindingViewDimensionDescriptor = struct_WGPUTextureBindingViewDimensionDescriptor -class struct_WGPUTextureDataLayout(Structure): - pass - -struct_WGPUTextureDataLayout._pack_ = 1 # source:False -struct_WGPUTextureDataLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('offset', ctypes.c_uint64), - ('bytesPerRow', ctypes.c_uint32), - ('rowsPerImage', ctypes.c_uint32), -] - -WGPUTextureDataLayout = struct_WGPUTextureDataLayout -class struct_WGPUUncapturedErrorCallbackInfo(Structure): - pass - -struct_WGPUUncapturedErrorCallbackInfo._pack_ = 1 # source:False -struct_WGPUUncapturedErrorCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('callback', ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUUncapturedErrorCallbackInfo = struct_WGPUUncapturedErrorCallbackInfo -class struct_WGPUVertexAttribute(Structure): - pass - -struct_WGPUVertexAttribute._pack_ = 1 # source:False -struct_WGPUVertexAttribute._fields_ = [ - ('format', WGPUVertexFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('shaderLocation', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -WGPUVertexAttribute = struct_WGPUVertexAttribute -class struct_WGPUYCbCrVkDescriptor(Structure): - pass - -struct_WGPUYCbCrVkDescriptor._pack_ = 1 # source:False -struct_WGPUYCbCrVkDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('vkFormat', ctypes.c_uint32), - ('vkYCbCrModel', ctypes.c_uint32), - ('vkYCbCrRange', ctypes.c_uint32), - ('vkComponentSwizzleRed', ctypes.c_uint32), - ('vkComponentSwizzleGreen', ctypes.c_uint32), - ('vkComponentSwizzleBlue', ctypes.c_uint32), - ('vkComponentSwizzleAlpha', ctypes.c_uint32), - ('vkXChromaOffset', ctypes.c_uint32), - ('vkYChromaOffset', ctypes.c_uint32), - ('vkChromaFilter', WGPUFilterMode), - ('forceExplicitReconstruction', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('externalFormat', ctypes.c_uint64), -] - -WGPUYCbCrVkDescriptor = struct_WGPUYCbCrVkDescriptor -class struct_WGPUAHardwareBufferProperties(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('yCbCrInfo', WGPUYCbCrVkDescriptor), - ] - -WGPUAHardwareBufferProperties = struct_WGPUAHardwareBufferProperties -class struct_WGPUAdapterInfo(Structure): - pass - -struct_WGPUAdapterInfo._pack_ = 1 # source:False -struct_WGPUAdapterInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('vendor', WGPUStringView), - ('architecture', WGPUStringView), - ('device', WGPUStringView), - ('description', WGPUStringView), - ('backendType', WGPUBackendType), - ('adapterType', WGPUAdapterType), - ('vendorID', ctypes.c_uint32), - ('deviceID', ctypes.c_uint32), - ('compatibilityMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUAdapterInfo = struct_WGPUAdapterInfo -class struct_WGPUAdapterPropertiesMemoryHeaps(Structure): - pass - -struct_WGPUAdapterPropertiesMemoryHeaps._pack_ = 1 # source:False -struct_WGPUAdapterPropertiesMemoryHeaps._fields_ = [ - ('chain', WGPUChainedStructOut), - ('heapCount', ctypes.c_uint64), - ('heapInfo', ctypes.POINTER(struct_WGPUMemoryHeapInfo)), -] - -WGPUAdapterPropertiesMemoryHeaps = struct_WGPUAdapterPropertiesMemoryHeaps -class struct_WGPUBindGroupDescriptor(Structure): - pass - -struct_WGPUBindGroupDescriptor._pack_ = 1 # source:False -struct_WGPUBindGroupDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)), - ('entryCount', ctypes.c_uint64), - ('entries', ctypes.POINTER(struct_WGPUBindGroupEntry)), -] - -WGPUBindGroupDescriptor = struct_WGPUBindGroupDescriptor -class struct_WGPUBindGroupLayoutEntry(Structure): - pass - -struct_WGPUBindGroupLayoutEntry._pack_ = 1 # source:False -struct_WGPUBindGroupLayoutEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('binding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('visibility', ctypes.c_uint64), - ('buffer', WGPUBufferBindingLayout), - ('sampler', WGPUSamplerBindingLayout), - ('texture', WGPUTextureBindingLayout), - ('storageTexture', WGPUStorageTextureBindingLayout), -] - -WGPUBindGroupLayoutEntry = struct_WGPUBindGroupLayoutEntry -class struct_WGPUBlendState(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('color', WGPUBlendComponent), - ('alpha', WGPUBlendComponent), - ] - -WGPUBlendState = struct_WGPUBlendState -class struct_WGPUBufferDescriptor(Structure): - pass - -struct_WGPUBufferDescriptor._pack_ = 1 # source:False -struct_WGPUBufferDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('usage', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('mappedAtCreation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUBufferDescriptor = struct_WGPUBufferDescriptor -class struct_WGPUCommandBufferDescriptor(Structure): - pass - -struct_WGPUCommandBufferDescriptor._pack_ = 1 # source:False -struct_WGPUCommandBufferDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUCommandBufferDescriptor = struct_WGPUCommandBufferDescriptor -class struct_WGPUCommandEncoderDescriptor(Structure): - pass - -struct_WGPUCommandEncoderDescriptor._pack_ = 1 # source:False -struct_WGPUCommandEncoderDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUCommandEncoderDescriptor = struct_WGPUCommandEncoderDescriptor -class struct_WGPUCompilationMessage(Structure): - pass - -struct_WGPUCompilationMessage._pack_ = 1 # source:False -struct_WGPUCompilationMessage._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('message', WGPUStringView), - ('type', WGPUCompilationMessageType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('lineNum', ctypes.c_uint64), - ('linePos', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('utf16LinePos', ctypes.c_uint64), - ('utf16Offset', ctypes.c_uint64), - ('utf16Length', ctypes.c_uint64), -] - -WGPUCompilationMessage = struct_WGPUCompilationMessage -class struct_WGPUComputePassDescriptor(Structure): - pass - -struct_WGPUComputePassDescriptor._pack_ = 1 # source:False -struct_WGPUComputePassDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('timestampWrites', ctypes.POINTER(struct_WGPUComputePassTimestampWrites)), -] - -WGPUComputePassDescriptor = struct_WGPUComputePassDescriptor -class struct_WGPUConstantEntry(Structure): - pass - -struct_WGPUConstantEntry._pack_ = 1 # source:False -struct_WGPUConstantEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('key', WGPUStringView), - ('value', ctypes.c_double), -] - -WGPUConstantEntry = struct_WGPUConstantEntry -class struct_WGPUDawnCacheDeviceDescriptor(Structure): - pass - -struct_WGPUDawnCacheDeviceDescriptor._pack_ = 1 # source:False -struct_WGPUDawnCacheDeviceDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('isolationKey', WGPUStringView), - ('loadDataFunction', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None))), - ('storeDataFunction', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None))), - ('functionUserdata', ctypes.POINTER(None)), -] - -WGPUDawnCacheDeviceDescriptor = struct_WGPUDawnCacheDeviceDescriptor -class struct_WGPUDepthStencilState(Structure): - pass - -struct_WGPUDepthStencilState._pack_ = 1 # source:False -struct_WGPUDepthStencilState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('format', WGPUTextureFormat), - ('depthWriteEnabled', WGPUOptionalBool), - ('depthCompare', WGPUCompareFunction), - ('stencilFront', WGPUStencilFaceState), - ('stencilBack', WGPUStencilFaceState), - ('stencilReadMask', ctypes.c_uint32), - ('stencilWriteMask', ctypes.c_uint32), - ('depthBias', ctypes.c_int32), - ('depthBiasSlopeScale', ctypes.c_float), - ('depthBiasClamp', ctypes.c_float), -] - -WGPUDepthStencilState = struct_WGPUDepthStencilState -class struct_WGPUDrmFormatCapabilities(Structure): - pass - -struct_WGPUDrmFormatCapabilities._pack_ = 1 # source:False -struct_WGPUDrmFormatCapabilities._fields_ = [ - ('chain', WGPUChainedStructOut), - ('propertiesCount', ctypes.c_uint64), - ('properties', ctypes.POINTER(struct_WGPUDrmFormatProperties)), -] - -WGPUDrmFormatCapabilities = struct_WGPUDrmFormatCapabilities -class struct_WGPUExternalTextureDescriptor(Structure): - pass - -struct_WGPUExternalTextureDescriptor._pack_ = 1 # source:False -struct_WGPUExternalTextureDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('plane0', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('plane1', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('cropOrigin', WGPUOrigin2D), - ('cropSize', WGPUExtent2D), - ('apparentSize', WGPUExtent2D), - ('doYuvToRgbConversionOnly', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('yuvToRgbConversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('gamutConversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('mirrored', ctypes.c_uint32), - ('rotation', WGPUExternalTextureRotation), -] - -WGPUExternalTextureDescriptor = struct_WGPUExternalTextureDescriptor -class struct_WGPUFutureWaitInfo(Structure): - pass - -struct_WGPUFutureWaitInfo._pack_ = 1 # source:False -struct_WGPUFutureWaitInfo._fields_ = [ - ('future', WGPUFuture), - ('completed', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUFutureWaitInfo = struct_WGPUFutureWaitInfo -class struct_WGPUImageCopyBuffer(Structure): - pass - -struct_WGPUImageCopyBuffer._pack_ = 1 # source:False -struct_WGPUImageCopyBuffer._fields_ = [ - ('layout', WGPUTextureDataLayout), - ('buffer', ctypes.POINTER(struct_WGPUBufferImpl)), -] - -WGPUImageCopyBuffer = struct_WGPUImageCopyBuffer -class struct_WGPUImageCopyExternalTexture(Structure): - pass - -struct_WGPUImageCopyExternalTexture._pack_ = 1 # source:False -struct_WGPUImageCopyExternalTexture._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('externalTexture', ctypes.POINTER(struct_WGPUExternalTextureImpl)), - ('origin', WGPUOrigin3D), - ('naturalSize', WGPUExtent2D), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUImageCopyExternalTexture = struct_WGPUImageCopyExternalTexture -class struct_WGPUImageCopyTexture(Structure): - pass - -struct_WGPUImageCopyTexture._pack_ = 1 # source:False -struct_WGPUImageCopyTexture._fields_ = [ - ('texture', ctypes.POINTER(struct_WGPUTextureImpl)), - ('mipLevel', ctypes.c_uint32), - ('origin', WGPUOrigin3D), - ('aspect', WGPUTextureAspect), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUImageCopyTexture = struct_WGPUImageCopyTexture -class struct_WGPUInstanceDescriptor(Structure): - pass - -struct_WGPUInstanceDescriptor._pack_ = 1 # source:False -struct_WGPUInstanceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('features', WGPUInstanceFeatures), -] - -WGPUInstanceDescriptor = struct_WGPUInstanceDescriptor -class struct_WGPUPipelineLayoutDescriptor(Structure): - pass - -struct_WGPUPipelineLayoutDescriptor._pack_ = 1 # source:False -struct_WGPUPipelineLayoutDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('bindGroupLayoutCount', ctypes.c_uint64), - ('bindGroupLayouts', ctypes.POINTER(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl))), - ('immediateDataRangeByteSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUPipelineLayoutDescriptor = struct_WGPUPipelineLayoutDescriptor -class struct_WGPUPipelineLayoutPixelLocalStorage(Structure): - pass - -struct_WGPUPipelineLayoutPixelLocalStorage._pack_ = 1 # source:False -struct_WGPUPipelineLayoutPixelLocalStorage._fields_ = [ - ('chain', WGPUChainedStruct), - ('totalPixelLocalStorageSize', ctypes.c_uint64), - ('storageAttachmentCount', ctypes.c_uint64), - ('storageAttachments', ctypes.POINTER(struct_WGPUPipelineLayoutStorageAttachment)), -] - -WGPUPipelineLayoutPixelLocalStorage = struct_WGPUPipelineLayoutPixelLocalStorage -class struct_WGPUQuerySetDescriptor(Structure): - pass - -struct_WGPUQuerySetDescriptor._pack_ = 1 # source:False -struct_WGPUQuerySetDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('type', WGPUQueryType), - ('count', ctypes.c_uint32), -] - -WGPUQuerySetDescriptor = struct_WGPUQuerySetDescriptor -class struct_WGPUQueueDescriptor(Structure): - pass - -struct_WGPUQueueDescriptor._pack_ = 1 # source:False -struct_WGPUQueueDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUQueueDescriptor = struct_WGPUQueueDescriptor -class struct_WGPURenderBundleDescriptor(Structure): - pass - -struct_WGPURenderBundleDescriptor._pack_ = 1 # source:False -struct_WGPURenderBundleDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPURenderBundleDescriptor = struct_WGPURenderBundleDescriptor -class struct_WGPURenderBundleEncoderDescriptor(Structure): - pass - -struct_WGPURenderBundleEncoderDescriptor._pack_ = 1 # source:False -struct_WGPURenderBundleEncoderDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('colorFormatCount', ctypes.c_uint64), - ('colorFormats', ctypes.POINTER(WGPUTextureFormat)), - ('depthStencilFormat', WGPUTextureFormat), - ('sampleCount', ctypes.c_uint32), - ('depthReadOnly', ctypes.c_uint32), - ('stencilReadOnly', ctypes.c_uint32), -] - -WGPURenderBundleEncoderDescriptor = struct_WGPURenderBundleEncoderDescriptor -class struct_WGPURenderPassColorAttachment(Structure): - pass - -struct_WGPURenderPassColorAttachment._pack_ = 1 # source:False -struct_WGPURenderPassColorAttachment._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('view', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('depthSlice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resolveTarget', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('loadOp', WGPULoadOp), - ('storeOp', WGPUStoreOp), - ('clearValue', WGPUColor), -] - -WGPURenderPassColorAttachment = struct_WGPURenderPassColorAttachment -class struct_WGPURenderPassStorageAttachment(Structure): - pass - -struct_WGPURenderPassStorageAttachment._pack_ = 1 # source:False -struct_WGPURenderPassStorageAttachment._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('offset', ctypes.c_uint64), - ('storage', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('loadOp', WGPULoadOp), - ('storeOp', WGPUStoreOp), - ('clearValue', WGPUColor), -] - -WGPURenderPassStorageAttachment = struct_WGPURenderPassStorageAttachment -class struct_WGPURequiredLimits(Structure): - pass - -struct_WGPURequiredLimits._pack_ = 1 # source:False -struct_WGPURequiredLimits._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('limits', WGPULimits), -] - -WGPURequiredLimits = struct_WGPURequiredLimits -class struct_WGPUSamplerDescriptor(Structure): - pass - -struct_WGPUSamplerDescriptor._pack_ = 1 # source:False -struct_WGPUSamplerDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('addressModeU', WGPUAddressMode), - ('addressModeV', WGPUAddressMode), - ('addressModeW', WGPUAddressMode), - ('magFilter', WGPUFilterMode), - ('minFilter', WGPUFilterMode), - ('mipmapFilter', WGPUMipmapFilterMode), - ('lodMinClamp', ctypes.c_float), - ('lodMaxClamp', ctypes.c_float), - ('compare', WGPUCompareFunction), - ('maxAnisotropy', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -WGPUSamplerDescriptor = struct_WGPUSamplerDescriptor -class struct_WGPUShaderModuleDescriptor(Structure): - pass - -struct_WGPUShaderModuleDescriptor._pack_ = 1 # source:False -struct_WGPUShaderModuleDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUShaderModuleDescriptor = struct_WGPUShaderModuleDescriptor -class struct_WGPUShaderSourceWGSL(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ('code', WGPUStringView), - ] - -WGPUShaderSourceWGSL = struct_WGPUShaderSourceWGSL -class struct_WGPUSharedBufferMemoryDescriptor(Structure): - pass - -struct_WGPUSharedBufferMemoryDescriptor._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUSharedBufferMemoryDescriptor = struct_WGPUSharedBufferMemoryDescriptor -class struct_WGPUSharedFenceDescriptor(Structure): - pass - -struct_WGPUSharedFenceDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUSharedFenceDescriptor = struct_WGPUSharedFenceDescriptor -class struct_WGPUSharedTextureMemoryAHardwareBufferProperties(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStructOut), - ('yCbCrInfo', WGPUYCbCrVkDescriptor), - ] - -WGPUSharedTextureMemoryAHardwareBufferProperties = struct_WGPUSharedTextureMemoryAHardwareBufferProperties -class struct_WGPUSharedTextureMemoryDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUSharedTextureMemoryDescriptor = struct_WGPUSharedTextureMemoryDescriptor -class struct_WGPUSharedTextureMemoryDmaBufDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDmaBufDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDmaBufDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('size', WGPUExtent3D), - ('drmFormat', ctypes.c_uint32), - ('drmModifier', ctypes.c_uint64), - ('planeCount', ctypes.c_uint64), - ('planes', ctypes.POINTER(struct_WGPUSharedTextureMemoryDmaBufPlane)), -] - -WGPUSharedTextureMemoryDmaBufDescriptor = struct_WGPUSharedTextureMemoryDmaBufDescriptor -class struct_WGPUSharedTextureMemoryProperties(Structure): - pass - -struct_WGPUSharedTextureMemoryProperties._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryProperties._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usage', ctypes.c_uint64), - ('size', WGPUExtent3D), - ('format', WGPUTextureFormat), -] - -WGPUSharedTextureMemoryProperties = struct_WGPUSharedTextureMemoryProperties -class struct_WGPUSupportedLimits(Structure): - pass - -struct_WGPUSupportedLimits._pack_ = 1 # source:False -struct_WGPUSupportedLimits._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('limits', WGPULimits), -] - -WGPUSupportedLimits = struct_WGPUSupportedLimits -class struct_WGPUSurfaceDescriptor(Structure): - pass - -struct_WGPUSurfaceDescriptor._pack_ = 1 # source:False -struct_WGPUSurfaceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUSurfaceDescriptor = struct_WGPUSurfaceDescriptor -class struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ('selector', WGPUStringView), - ] - -WGPUSurfaceSourceCanvasHTMLSelector_Emscripten = struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten -class struct_WGPUTextureDescriptor(Structure): - pass - -struct_WGPUTextureDescriptor._pack_ = 1 # source:False -struct_WGPUTextureDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('usage', ctypes.c_uint64), - ('dimension', WGPUTextureDimension), - ('size', WGPUExtent3D), - ('format', WGPUTextureFormat), - ('mipLevelCount', ctypes.c_uint32), - ('sampleCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('viewFormatCount', ctypes.c_uint64), - ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), -] - -WGPUTextureDescriptor = struct_WGPUTextureDescriptor -class struct_WGPUTextureViewDescriptor(Structure): - pass - -struct_WGPUTextureViewDescriptor._pack_ = 1 # source:False -struct_WGPUTextureViewDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('format', WGPUTextureFormat), - ('dimension', WGPUTextureViewDimension), - ('baseMipLevel', ctypes.c_uint32), - ('mipLevelCount', ctypes.c_uint32), - ('baseArrayLayer', ctypes.c_uint32), - ('arrayLayerCount', ctypes.c_uint32), - ('aspect', WGPUTextureAspect), - ('PADDING_0', ctypes.c_ubyte * 4), - ('usage', ctypes.c_uint64), -] - -WGPUTextureViewDescriptor = struct_WGPUTextureViewDescriptor -class struct_WGPUVertexBufferLayout(Structure): - pass - -struct_WGPUVertexBufferLayout._pack_ = 1 # source:False -struct_WGPUVertexBufferLayout._fields_ = [ - ('arrayStride', ctypes.c_uint64), - ('stepMode', WGPUVertexStepMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('attributeCount', ctypes.c_uint64), - ('attributes', ctypes.POINTER(struct_WGPUVertexAttribute)), -] - -WGPUVertexBufferLayout = struct_WGPUVertexBufferLayout -class struct_WGPUBindGroupLayoutDescriptor(Structure): - pass - -struct_WGPUBindGroupLayoutDescriptor._pack_ = 1 # source:False -struct_WGPUBindGroupLayoutDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('entryCount', ctypes.c_uint64), - ('entries', ctypes.POINTER(struct_WGPUBindGroupLayoutEntry)), -] - -WGPUBindGroupLayoutDescriptor = struct_WGPUBindGroupLayoutDescriptor -class struct_WGPUColorTargetState(Structure): - pass - -struct_WGPUColorTargetState._pack_ = 1 # source:False -struct_WGPUColorTargetState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('blend', ctypes.POINTER(struct_WGPUBlendState)), - ('writeMask', ctypes.c_uint64), -] - -WGPUColorTargetState = struct_WGPUColorTargetState -struct_WGPUCompilationInfo._pack_ = 1 # source:False -struct_WGPUCompilationInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('messageCount', ctypes.c_uint64), - ('messages', ctypes.POINTER(struct_WGPUCompilationMessage)), -] - -WGPUCompilationInfo = struct_WGPUCompilationInfo -class struct_WGPUComputeState(Structure): - pass - -struct_WGPUComputeState._pack_ = 1 # source:False -struct_WGPUComputeState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), -] - -WGPUComputeState = struct_WGPUComputeState -class struct_WGPUDeviceDescriptor(Structure): - pass - -struct_WGPUDeviceDescriptor._pack_ = 1 # source:False -struct_WGPUDeviceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('requiredFeatureCount', ctypes.c_uint64), - ('requiredFeatures', ctypes.POINTER(WGPUFeatureName)), - ('requiredLimits', ctypes.POINTER(struct_WGPURequiredLimits)), - ('defaultQueue', WGPUQueueDescriptor), - ('deviceLostCallbackInfo2', WGPUDeviceLostCallbackInfo2), - ('uncapturedErrorCallbackInfo2', WGPUUncapturedErrorCallbackInfo2), -] - -WGPUDeviceDescriptor = struct_WGPUDeviceDescriptor -class struct_WGPURenderPassDescriptor(Structure): - pass - -struct_WGPURenderPassDescriptor._pack_ = 1 # source:False -struct_WGPURenderPassDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('colorAttachmentCount', ctypes.c_uint64), - ('colorAttachments', ctypes.POINTER(struct_WGPURenderPassColorAttachment)), - ('depthStencilAttachment', ctypes.POINTER(struct_WGPURenderPassDepthStencilAttachment)), - ('occlusionQuerySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('timestampWrites', ctypes.POINTER(struct_WGPURenderPassTimestampWrites)), -] - -WGPURenderPassDescriptor = struct_WGPURenderPassDescriptor -class struct_WGPURenderPassPixelLocalStorage(Structure): - pass - -struct_WGPURenderPassPixelLocalStorage._pack_ = 1 # source:False -struct_WGPURenderPassPixelLocalStorage._fields_ = [ - ('chain', WGPUChainedStruct), - ('totalPixelLocalStorageSize', ctypes.c_uint64), - ('storageAttachmentCount', ctypes.c_uint64), - ('storageAttachments', ctypes.POINTER(struct_WGPURenderPassStorageAttachment)), -] - -WGPURenderPassPixelLocalStorage = struct_WGPURenderPassPixelLocalStorage -class struct_WGPUVertexState(Structure): - pass - -struct_WGPUVertexState._pack_ = 1 # source:False -struct_WGPUVertexState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), - ('bufferCount', ctypes.c_uint64), - ('buffers', ctypes.POINTER(struct_WGPUVertexBufferLayout)), -] - -WGPUVertexState = struct_WGPUVertexState -class struct_WGPUComputePipelineDescriptor(Structure): - pass - -struct_WGPUComputePipelineDescriptor._pack_ = 1 # source:False -struct_WGPUComputePipelineDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUPipelineLayoutImpl)), - ('compute', WGPUComputeState), -] - -WGPUComputePipelineDescriptor = struct_WGPUComputePipelineDescriptor -class struct_WGPUFragmentState(Structure): - pass - -struct_WGPUFragmentState._pack_ = 1 # source:False -struct_WGPUFragmentState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), - ('targetCount', ctypes.c_uint64), - ('targets', ctypes.POINTER(struct_WGPUColorTargetState)), -] - -WGPUFragmentState = struct_WGPUFragmentState -class struct_WGPURenderPipelineDescriptor(Structure): - pass - -struct_WGPURenderPipelineDescriptor._pack_ = 1 # source:False -struct_WGPURenderPipelineDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUPipelineLayoutImpl)), - ('vertex', WGPUVertexState), - ('primitive', WGPUPrimitiveState), - ('depthStencil', ctypes.POINTER(struct_WGPUDepthStencilState)), - ('multisample', WGPUMultisampleState), - ('fragment', ctypes.POINTER(struct_WGPUFragmentState)), -] - -WGPURenderPipelineDescriptor = struct_WGPURenderPipelineDescriptor -WGPURenderPassDescriptorMaxDrawCount = struct_WGPURenderPassMaxDrawCount -WGPUShaderModuleSPIRVDescriptor = struct_WGPUShaderSourceSPIRV -WGPUShaderModuleWGSLDescriptor = struct_WGPUShaderSourceWGSL -WGPUSurfaceDescriptorFromAndroidNativeWindow = struct_WGPUSurfaceSourceAndroidNativeWindow -WGPUSurfaceDescriptorFromCanvasHTMLSelector = struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten -WGPUSurfaceDescriptorFromMetalLayer = struct_WGPUSurfaceSourceMetalLayer -WGPUSurfaceDescriptorFromWaylandSurface = struct_WGPUSurfaceSourceWaylandSurface -WGPUSurfaceDescriptorFromWindowsHWND = struct_WGPUSurfaceSourceWindowsHWND -WGPUSurfaceDescriptorFromXcbWindow = struct_WGPUSurfaceSourceXCBWindow -WGPUSurfaceDescriptorFromXlibWindow = struct_WGPUSurfaceSourceXlibWindow -WGPUProcAdapterInfoFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUAdapterInfo) -WGPUProcAdapterPropertiesMemoryHeapsFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUAdapterPropertiesMemoryHeaps) -WGPUProcCreateInstance = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUInstanceDescriptor)) -WGPUProcDrmFormatCapabilitiesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUDrmFormatCapabilities) -WGPUProcGetInstanceFeatures = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUInstanceFeatures)) -WGPUProcGetProcAddress = ctypes.CFUNCTYPE(ctypes.CFUNCTYPE(None), struct_WGPUStringView) -WGPUProcSharedBufferMemoryEndAccessStateFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSharedBufferMemoryEndAccessState) -WGPUProcSharedTextureMemoryEndAccessStateFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSharedTextureMemoryEndAccessState) -WGPUProcSupportedFeaturesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSupportedFeatures) -WGPUProcSurfaceCapabilitiesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSurfaceCapabilities) -WGPUProcAdapterCreateDevice = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor)) -WGPUProcAdapterGetFeatures = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSupportedFeatures)) -WGPUProcAdapterGetFormatCapabilities = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), WGPUTextureFormat, ctypes.POINTER(struct_WGPUFormatCapabilities)) -WGPUProcAdapterGetInfo = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) -WGPUProcAdapterGetInstance = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUAdapterImpl)) -WGPUProcAdapterGetLimits = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) -WGPUProcAdapterHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUAdapterImpl), WGPUFeatureName) -WGPUProcAdapterRequestDevice = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcAdapterRequestDevice2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo2) -WGPUProcAdapterRequestDeviceF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo) -WGPUProcAdapterAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl)) -WGPUProcAdapterRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl)) -WGPUProcBindGroupSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupImpl), struct_WGPUStringView) -WGPUProcBindGroupAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupImpl)) -WGPUProcBindGroupRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupImpl)) -WGPUProcBindGroupLayoutSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), struct_WGPUStringView) -WGPUProcBindGroupLayoutAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)) -WGPUProcBindGroupLayoutRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)) -WGPUProcBufferDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferGetConstMappedRange = ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcBufferGetMapState = ctypes.CFUNCTYPE(WGPUBufferMapState, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferGetMappedRange = ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcBufferGetSize = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferGetUsage = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferMapAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcBufferMapAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, struct_WGPUBufferMapCallbackInfo2) -WGPUProcBufferMapAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, struct_WGPUBufferMapCallbackInfo) -WGPUProcBufferSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl), struct_WGPUStringView) -WGPUProcBufferUnmap = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcCommandBufferSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl), struct_WGPUStringView) -WGPUProcCommandBufferAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl)) -WGPUProcCommandBufferRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl)) -WGPUProcCommandEncoderBeginComputePass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUComputePassDescriptor)) -WGPUProcCommandEncoderBeginRenderPass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPURenderPassDescriptor)) -WGPUProcCommandEncoderClearBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcCommandEncoderCopyBufferToBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcCommandEncoderCopyBufferToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderCopyTextureToBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderCopyTextureToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandBufferImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUCommandBufferDescriptor)) -WGPUProcCommandEncoderInjectValidationError = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) -WGPUProcCommandEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) -WGPUProcCommandEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl)) -WGPUProcCommandEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) -WGPUProcCommandEncoderResolveQuerySet = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcCommandEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) -WGPUProcCommandEncoderWriteBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_uint64) -WGPUProcCommandEncoderWriteTimestamp = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.c_uint32) -WGPUProcCommandEncoderAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl)) -WGPUProcCommandEncoderRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl)) -WGPUProcComputePassEncoderDispatchWorkgroups = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -WGPUProcComputePassEncoderDispatchWorkgroupsIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcComputePassEncoderEnd = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl)) -WGPUProcComputePassEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), struct_WGPUStringView) -WGPUProcComputePassEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl)) -WGPUProcComputePassEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), struct_WGPUStringView) -WGPUProcComputePassEncoderSetBindGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint32)) -WGPUProcComputePassEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), struct_WGPUStringView) -WGPUProcComputePassEncoderSetPipeline = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUComputePipelineImpl)) -WGPUProcComputePassEncoderWriteTimestamp = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.c_uint32) -WGPUProcComputePassEncoderAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl)) -WGPUProcComputePassEncoderRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePassEncoderImpl)) -WGPUProcComputePipelineGetBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), ctypes.POINTER(struct_WGPUComputePipelineImpl), ctypes.c_uint32) -WGPUProcComputePipelineSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView) -WGPUProcComputePipelineAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl)) -WGPUProcComputePipelineRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl)) -WGPUProcDeviceCreateBindGroup = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBindGroupDescriptor)) -WGPUProcDeviceCreateBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBindGroupLayoutDescriptor)) -WGPUProcDeviceCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) -WGPUProcDeviceCreateCommandEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUCommandEncoderDescriptor)) -WGPUProcDeviceCreateComputePipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor)) -WGPUProcDeviceCreateComputePipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDeviceCreateComputePipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo2) -WGPUProcDeviceCreateComputePipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo) -WGPUProcDeviceCreateErrorBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) -WGPUProcDeviceCreateErrorExternalTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUExternalTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceCreateErrorShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUShaderModuleDescriptor), struct_WGPUStringView) -WGPUProcDeviceCreateErrorTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcDeviceCreateExternalTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUExternalTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUExternalTextureDescriptor)) -WGPUProcDeviceCreatePipelineLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUPipelineLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUPipelineLayoutDescriptor)) -WGPUProcDeviceCreateQuerySet = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUQuerySetDescriptor)) -WGPUProcDeviceCreateRenderBundleEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderBundleEncoderDescriptor)) -WGPUProcDeviceCreateRenderPipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor)) -WGPUProcDeviceCreateRenderPipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDeviceCreateRenderPipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo2) -WGPUProcDeviceCreateRenderPipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo) -WGPUProcDeviceCreateSampler = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSamplerImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSamplerDescriptor)) -WGPUProcDeviceCreateShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUShaderModuleDescriptor)) -WGPUProcDeviceCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcDeviceDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceForceLoss = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUDeviceLostReason, struct_WGPUStringView) -WGPUProcDeviceGetAHardwareBufferProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(None), ctypes.POINTER(struct_WGPUAHardwareBufferProperties)) -WGPUProcDeviceGetAdapter = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceGetAdapterInfo = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) -WGPUProcDeviceGetFeatures = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSupportedFeatures)) -WGPUProcDeviceGetLimits = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) -WGPUProcDeviceGetLostFuture = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceGetQueue = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUFeatureName) -WGPUProcDeviceImportSharedBufferMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryDescriptor)) -WGPUProcDeviceImportSharedFence = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedFenceImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedFenceDescriptor)) -WGPUProcDeviceImportSharedTextureMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryDescriptor)) -WGPUProcDeviceInjectError = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUErrorType, struct_WGPUStringView) -WGPUProcDevicePopErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDevicePopErrorScope2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUPopErrorScopeCallbackInfo2) -WGPUProcDevicePopErrorScopeF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUPopErrorScopeCallbackInfo) -WGPUProcDevicePushErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUErrorFilter) -WGPUProcDeviceSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView) -WGPUProcDeviceSetLoggingCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, WGPULoggingType, struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDeviceTick = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceValidateTextureDescriptor = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcDeviceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcExternalTextureDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcExternalTextureExpire = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcExternalTextureRefresh = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcExternalTextureSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl), struct_WGPUStringView) -WGPUProcExternalTextureAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcExternalTextureRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcInstanceCreateSurface = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUSurfaceDescriptor)) -WGPUProcInstanceEnumerateWGSLLanguageFeatures = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(WGPUWGSLFeatureName)) -WGPUProcInstanceHasWGSLLanguageFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUInstanceImpl), WGPUWGSLFeatureName) -WGPUProcInstanceProcessEvents = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) -WGPUProcInstanceRequestAdapter = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcInstanceRequestAdapter2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo2) -WGPUProcInstanceRequestAdapterF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo) -WGPUProcInstanceWaitAny = ctypes.CFUNCTYPE(WGPUWaitStatus, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.c_uint64, ctypes.POINTER(struct_WGPUFutureWaitInfo), ctypes.c_uint64) -WGPUProcInstanceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) -WGPUProcInstanceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) -WGPUProcPipelineLayoutSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUPipelineLayoutImpl), struct_WGPUStringView) -WGPUProcPipelineLayoutAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUPipelineLayoutImpl)) -WGPUProcPipelineLayoutRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUPipelineLayoutImpl)) -WGPUProcQuerySetDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQuerySetGetCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQuerySetGetType = ctypes.CFUNCTYPE(WGPUQueryType, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQuerySetSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl), struct_WGPUStringView) -WGPUProcQuerySetAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQuerySetRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQueueCopyExternalTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyExternalTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)) -WGPUProcQueueCopyTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)) -WGPUProcQueueOnSubmittedWorkDone = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcQueueOnSubmittedWorkDone2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUQueueWorkDoneCallbackInfo2) -WGPUProcQueueOnSubmittedWorkDoneF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUQueueWorkDoneCallbackInfo) -WGPUProcQueueSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUStringView) -WGPUProcQueueSubmit = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(struct_WGPUCommandBufferImpl))) -WGPUProcQueueWriteBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64) -WGPUProcQueueWriteTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(struct_WGPUTextureDataLayout), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcQueueAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl)) -WGPUProcQueueRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl)) -WGPUProcRenderBundleSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleImpl), struct_WGPUStringView) -WGPUProcRenderBundleAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleImpl)) -WGPUProcRenderBundleRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleImpl)) -WGPUProcRenderBundleEncoderDraw = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -WGPUProcRenderBundleEncoderDrawIndexed = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int32, ctypes.c_uint32) -WGPUProcRenderBundleEncoderDrawIndexedIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderBundleEncoderDrawIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderBundleEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleImpl), ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPURenderBundleDescriptor)) -WGPUProcRenderBundleEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) -WGPUProcRenderBundleEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl)) -WGPUProcRenderBundleEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) -WGPUProcRenderBundleEncoderSetBindGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint32)) -WGPUProcRenderBundleEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) -WGPUProcRenderBundleEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) -WGPUProcRenderBundleEncoderSetPipeline = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPURenderPipelineImpl)) -WGPUProcRenderBundleEncoderSetVertexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcRenderBundleEncoderAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl)) -WGPUProcRenderBundleEncoderRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl)) -WGPUProcRenderPassEncoderBeginOcclusionQuery = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32) -WGPUProcRenderPassEncoderDraw = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -WGPUProcRenderPassEncoderDrawIndexed = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int32, ctypes.c_uint32) -WGPUProcRenderPassEncoderDrawIndexedIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderPassEncoderDrawIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderPassEncoderEnd = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPassEncoderEndOcclusionQuery = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPassEncoderExecuteBundles = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(struct_WGPURenderBundleImpl))) -WGPUProcRenderPassEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), struct_WGPUStringView) -WGPUProcRenderPassEncoderMultiDrawIndexedIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderPassEncoderMultiDrawIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderPassEncoderPixelLocalStorageBarrier = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPassEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPassEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), struct_WGPUStringView) -WGPUProcRenderPassEncoderSetBindGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint32)) -WGPUProcRenderPassEncoderSetBlendConstant = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUColor)) -WGPUProcRenderPassEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) -WGPUProcRenderPassEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), struct_WGPUStringView) -WGPUProcRenderPassEncoderSetPipeline = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPURenderPipelineImpl)) -WGPUProcRenderPassEncoderSetScissorRect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -WGPUProcRenderPassEncoderSetStencilReference = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32) -WGPUProcRenderPassEncoderSetVertexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcRenderPassEncoderSetViewport = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float) -WGPUProcRenderPassEncoderWriteTimestamp = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.c_uint32) -WGPUProcRenderPassEncoderAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPassEncoderRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) -WGPUProcRenderPipelineGetBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), ctypes.POINTER(struct_WGPURenderPipelineImpl), ctypes.c_uint32) -WGPUProcRenderPipelineSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView) -WGPUProcRenderPipelineAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPipelineImpl)) -WGPUProcRenderPipelineRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPipelineImpl)) -WGPUProcSamplerSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl), struct_WGPUStringView) -WGPUProcSamplerAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl)) -WGPUProcSamplerRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl)) -WGPUProcShaderModuleGetCompilationInfo = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcShaderModuleGetCompilationInfo2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUCompilationInfoCallbackInfo2) -WGPUProcShaderModuleGetCompilationInfoF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUCompilationInfoCallbackInfo) -WGPUProcShaderModuleSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUStringView) -WGPUProcShaderModuleAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl)) -WGPUProcShaderModuleRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl)) -WGPUProcSharedBufferMemoryBeginAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryBeginAccessDescriptor)) -WGPUProcSharedBufferMemoryCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) -WGPUProcSharedBufferMemoryEndAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryEndAccessState)) -WGPUProcSharedBufferMemoryGetProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryProperties)) -WGPUProcSharedBufferMemoryIsDeviceLost = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl)) -WGPUProcSharedBufferMemorySetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), struct_WGPUStringView) -WGPUProcSharedBufferMemoryAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl)) -WGPUProcSharedBufferMemoryRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl)) -WGPUProcSharedFenceExportInfo = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl), ctypes.POINTER(struct_WGPUSharedFenceExportInfo)) -WGPUProcSharedFenceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl)) -WGPUProcSharedFenceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl)) -WGPUProcSharedTextureMemoryBeginAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryBeginAccessDescriptor)) -WGPUProcSharedTextureMemoryCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcSharedTextureMemoryEndAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryEndAccessState)) -WGPUProcSharedTextureMemoryGetProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryProperties)) -WGPUProcSharedTextureMemoryIsDeviceLost = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) -WGPUProcSharedTextureMemorySetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), struct_WGPUStringView) -WGPUProcSharedTextureMemoryAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) -WGPUProcSharedTextureMemoryRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) -WGPUProcSurfaceConfigure = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUSurfaceConfiguration)) -WGPUProcSurfaceGetCapabilities = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSurfaceCapabilities)) -WGPUProcSurfaceGetCurrentTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUSurfaceTexture)) -WGPUProcSurfacePresent = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) -WGPUProcSurfaceSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), struct_WGPUStringView) -WGPUProcSurfaceUnconfigure = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) -WGPUProcSurfaceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) -WGPUProcSurfaceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) -WGPUProcTextureCreateErrorView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUTextureViewDescriptor)) -WGPUProcTextureCreateView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUTextureViewDescriptor)) -WGPUProcTextureDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetDepthOrArrayLayers = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetDimension = ctypes.CFUNCTYPE(WGPUTextureDimension, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetFormat = ctypes.CFUNCTYPE(WGPUTextureFormat, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetHeight = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetMipLevelCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetSampleCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetUsage = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetWidth = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureImpl), struct_WGPUStringView) -WGPUProcTextureAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureViewSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl), struct_WGPUStringView) -WGPUProcTextureViewAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl)) -WGPUProcTextureViewRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl)) -try: - wgpuAdapterInfoFreeMembers = _libraries['webgpu'].wgpuAdapterInfoFreeMembers - wgpuAdapterInfoFreeMembers.restype = None - wgpuAdapterInfoFreeMembers.argtypes = [WGPUAdapterInfo] -except AttributeError: - pass -try: - wgpuAdapterPropertiesMemoryHeapsFreeMembers = _libraries['webgpu'].wgpuAdapterPropertiesMemoryHeapsFreeMembers - wgpuAdapterPropertiesMemoryHeapsFreeMembers.restype = None - wgpuAdapterPropertiesMemoryHeapsFreeMembers.argtypes = [WGPUAdapterPropertiesMemoryHeaps] -except AttributeError: - pass -try: - wgpuCreateInstance = _libraries['webgpu'].wgpuCreateInstance - wgpuCreateInstance.restype = WGPUInstance - wgpuCreateInstance.argtypes = [ctypes.POINTER(struct_WGPUInstanceDescriptor)] -except AttributeError: - pass -try: - wgpuDrmFormatCapabilitiesFreeMembers = _libraries['webgpu'].wgpuDrmFormatCapabilitiesFreeMembers - wgpuDrmFormatCapabilitiesFreeMembers.restype = None - wgpuDrmFormatCapabilitiesFreeMembers.argtypes = [WGPUDrmFormatCapabilities] -except AttributeError: - pass -try: - wgpuGetInstanceFeatures = _libraries['webgpu'].wgpuGetInstanceFeatures - wgpuGetInstanceFeatures.restype = WGPUStatus - wgpuGetInstanceFeatures.argtypes = [ctypes.POINTER(struct_WGPUInstanceFeatures)] -except AttributeError: - pass -try: - wgpuGetProcAddress = _libraries['webgpu'].wgpuGetProcAddress - wgpuGetProcAddress.restype = WGPUProc - wgpuGetProcAddress.argtypes = [WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryEndAccessStateFreeMembers = _libraries['webgpu'].wgpuSharedBufferMemoryEndAccessStateFreeMembers - wgpuSharedBufferMemoryEndAccessStateFreeMembers.restype = None - wgpuSharedBufferMemoryEndAccessStateFreeMembers.argtypes = [WGPUSharedBufferMemoryEndAccessState] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryEndAccessStateFreeMembers = _libraries['webgpu'].wgpuSharedTextureMemoryEndAccessStateFreeMembers - wgpuSharedTextureMemoryEndAccessStateFreeMembers.restype = None - wgpuSharedTextureMemoryEndAccessStateFreeMembers.argtypes = [WGPUSharedTextureMemoryEndAccessState] -except AttributeError: - pass -try: - wgpuSupportedFeaturesFreeMembers = _libraries['webgpu'].wgpuSupportedFeaturesFreeMembers - wgpuSupportedFeaturesFreeMembers.restype = None - wgpuSupportedFeaturesFreeMembers.argtypes = [WGPUSupportedFeatures] -except AttributeError: - pass -try: - wgpuSurfaceCapabilitiesFreeMembers = _libraries['webgpu'].wgpuSurfaceCapabilitiesFreeMembers - wgpuSurfaceCapabilitiesFreeMembers.restype = None - wgpuSurfaceCapabilitiesFreeMembers.argtypes = [WGPUSurfaceCapabilities] -except AttributeError: - pass -try: - wgpuAdapterCreateDevice = _libraries['webgpu'].wgpuAdapterCreateDevice - wgpuAdapterCreateDevice.restype = WGPUDevice - wgpuAdapterCreateDevice.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor)] -except AttributeError: - pass -try: - wgpuAdapterGetFeatures = _libraries['webgpu'].wgpuAdapterGetFeatures - wgpuAdapterGetFeatures.restype = None - wgpuAdapterGetFeatures.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUSupportedFeatures)] -except AttributeError: - pass -try: - wgpuAdapterGetFormatCapabilities = _libraries['webgpu'].wgpuAdapterGetFormatCapabilities - wgpuAdapterGetFormatCapabilities.restype = WGPUStatus - wgpuAdapterGetFormatCapabilities.argtypes = [WGPUAdapter, WGPUTextureFormat, ctypes.POINTER(struct_WGPUFormatCapabilities)] -except AttributeError: - pass -try: - wgpuAdapterGetInfo = _libraries['webgpu'].wgpuAdapterGetInfo - wgpuAdapterGetInfo.restype = WGPUStatus - wgpuAdapterGetInfo.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUAdapterInfo)] -except AttributeError: - pass -try: - wgpuAdapterGetInstance = _libraries['webgpu'].wgpuAdapterGetInstance - wgpuAdapterGetInstance.restype = WGPUInstance - wgpuAdapterGetInstance.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuAdapterGetLimits = _libraries['webgpu'].wgpuAdapterGetLimits - wgpuAdapterGetLimits.restype = WGPUStatus - wgpuAdapterGetLimits.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUSupportedLimits)] -except AttributeError: - pass -try: - wgpuAdapterHasFeature = _libraries['webgpu'].wgpuAdapterHasFeature - wgpuAdapterHasFeature.restype = WGPUBool - wgpuAdapterHasFeature.argtypes = [WGPUAdapter, WGPUFeatureName] -except AttributeError: - pass -try: - wgpuAdapterRequestDevice = _libraries['webgpu'].wgpuAdapterRequestDevice - wgpuAdapterRequestDevice.restype = None - wgpuAdapterRequestDevice.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuAdapterRequestDevice2 = _libraries['webgpu'].wgpuAdapterRequestDevice2 - wgpuAdapterRequestDevice2.restype = WGPUFuture - wgpuAdapterRequestDevice2.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo2] -except AttributeError: - pass -try: - wgpuAdapterRequestDeviceF = _libraries['webgpu'].wgpuAdapterRequestDeviceF - wgpuAdapterRequestDeviceF.restype = WGPUFuture - wgpuAdapterRequestDeviceF.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo] -except AttributeError: - pass -try: - wgpuAdapterAddRef = _libraries['webgpu'].wgpuAdapterAddRef - wgpuAdapterAddRef.restype = None - wgpuAdapterAddRef.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuAdapterRelease = _libraries['webgpu'].wgpuAdapterRelease - wgpuAdapterRelease.restype = None - wgpuAdapterRelease.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuBindGroupSetLabel = _libraries['webgpu'].wgpuBindGroupSetLabel - wgpuBindGroupSetLabel.restype = None - wgpuBindGroupSetLabel.argtypes = [WGPUBindGroup, WGPUStringView] -except AttributeError: - pass -try: - wgpuBindGroupAddRef = _libraries['webgpu'].wgpuBindGroupAddRef - wgpuBindGroupAddRef.restype = None - wgpuBindGroupAddRef.argtypes = [WGPUBindGroup] -except AttributeError: - pass -try: - wgpuBindGroupRelease = _libraries['webgpu'].wgpuBindGroupRelease - wgpuBindGroupRelease.restype = None - wgpuBindGroupRelease.argtypes = [WGPUBindGroup] -except AttributeError: - pass -try: - wgpuBindGroupLayoutSetLabel = _libraries['webgpu'].wgpuBindGroupLayoutSetLabel - wgpuBindGroupLayoutSetLabel.restype = None - wgpuBindGroupLayoutSetLabel.argtypes = [WGPUBindGroupLayout, WGPUStringView] -except AttributeError: - pass -try: - wgpuBindGroupLayoutAddRef = _libraries['webgpu'].wgpuBindGroupLayoutAddRef - wgpuBindGroupLayoutAddRef.restype = None - wgpuBindGroupLayoutAddRef.argtypes = [WGPUBindGroupLayout] -except AttributeError: - pass -try: - wgpuBindGroupLayoutRelease = _libraries['webgpu'].wgpuBindGroupLayoutRelease - wgpuBindGroupLayoutRelease.restype = None - wgpuBindGroupLayoutRelease.argtypes = [WGPUBindGroupLayout] -except AttributeError: - pass -try: - wgpuBufferDestroy = _libraries['webgpu'].wgpuBufferDestroy - wgpuBufferDestroy.restype = None - wgpuBufferDestroy.argtypes = [WGPUBuffer] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - wgpuBufferGetConstMappedRange = _libraries['webgpu'].wgpuBufferGetConstMappedRange - wgpuBufferGetConstMappedRange.restype = ctypes.POINTER(None) - wgpuBufferGetConstMappedRange.argtypes = [WGPUBuffer, size_t, size_t] -except AttributeError: - pass -try: - wgpuBufferGetMapState = _libraries['webgpu'].wgpuBufferGetMapState - wgpuBufferGetMapState.restype = WGPUBufferMapState - wgpuBufferGetMapState.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferGetMappedRange = _libraries['webgpu'].wgpuBufferGetMappedRange - wgpuBufferGetMappedRange.restype = ctypes.POINTER(None) - wgpuBufferGetMappedRange.argtypes = [WGPUBuffer, size_t, size_t] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - wgpuBufferGetSize = _libraries['webgpu'].wgpuBufferGetSize - wgpuBufferGetSize.restype = uint64_t - wgpuBufferGetSize.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferGetUsage = _libraries['webgpu'].wgpuBufferGetUsage - wgpuBufferGetUsage.restype = WGPUBufferUsage - wgpuBufferGetUsage.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferMapAsync = _libraries['webgpu'].wgpuBufferMapAsync - wgpuBufferMapAsync.restype = None - wgpuBufferMapAsync.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuBufferMapAsync2 = _libraries['webgpu'].wgpuBufferMapAsync2 - wgpuBufferMapAsync2.restype = WGPUFuture - wgpuBufferMapAsync2.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo2] -except AttributeError: - pass -try: - wgpuBufferMapAsyncF = _libraries['webgpu'].wgpuBufferMapAsyncF - wgpuBufferMapAsyncF.restype = WGPUFuture - wgpuBufferMapAsyncF.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo] -except AttributeError: - pass -try: - wgpuBufferSetLabel = _libraries['webgpu'].wgpuBufferSetLabel - wgpuBufferSetLabel.restype = None - wgpuBufferSetLabel.argtypes = [WGPUBuffer, WGPUStringView] -except AttributeError: - pass -try: - wgpuBufferUnmap = _libraries['webgpu'].wgpuBufferUnmap - wgpuBufferUnmap.restype = None - wgpuBufferUnmap.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferAddRef = _libraries['webgpu'].wgpuBufferAddRef - wgpuBufferAddRef.restype = None - wgpuBufferAddRef.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferRelease = _libraries['webgpu'].wgpuBufferRelease - wgpuBufferRelease.restype = None - wgpuBufferRelease.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuCommandBufferSetLabel = _libraries['webgpu'].wgpuCommandBufferSetLabel - wgpuCommandBufferSetLabel.restype = None - wgpuCommandBufferSetLabel.argtypes = [WGPUCommandBuffer, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandBufferAddRef = _libraries['webgpu'].wgpuCommandBufferAddRef - wgpuCommandBufferAddRef.restype = None - wgpuCommandBufferAddRef.argtypes = [WGPUCommandBuffer] -except AttributeError: - pass -try: - wgpuCommandBufferRelease = _libraries['webgpu'].wgpuCommandBufferRelease - wgpuCommandBufferRelease.restype = None - wgpuCommandBufferRelease.argtypes = [WGPUCommandBuffer] -except AttributeError: - pass -try: - wgpuCommandEncoderBeginComputePass = _libraries['webgpu'].wgpuCommandEncoderBeginComputePass - wgpuCommandEncoderBeginComputePass.restype = WGPUComputePassEncoder - wgpuCommandEncoderBeginComputePass.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUComputePassDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderBeginRenderPass = _libraries['webgpu'].wgpuCommandEncoderBeginRenderPass - wgpuCommandEncoderBeginRenderPass.restype = WGPURenderPassEncoder - wgpuCommandEncoderBeginRenderPass.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPURenderPassDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderClearBuffer = _libraries['webgpu'].wgpuCommandEncoderClearBuffer - wgpuCommandEncoderClearBuffer.restype = None - wgpuCommandEncoderClearBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyBufferToBuffer = _libraries['webgpu'].wgpuCommandEncoderCopyBufferToBuffer - wgpuCommandEncoderCopyBufferToBuffer.restype = None - wgpuCommandEncoderCopyBufferToBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyBufferToTexture = _libraries['webgpu'].wgpuCommandEncoderCopyBufferToTexture - wgpuCommandEncoderCopyBufferToTexture.restype = None - wgpuCommandEncoderCopyBufferToTexture.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyTextureToBuffer = _libraries['webgpu'].wgpuCommandEncoderCopyTextureToBuffer - wgpuCommandEncoderCopyTextureToBuffer.restype = None - wgpuCommandEncoderCopyTextureToBuffer.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyTextureToTexture = _libraries['webgpu'].wgpuCommandEncoderCopyTextureToTexture - wgpuCommandEncoderCopyTextureToTexture.restype = None - wgpuCommandEncoderCopyTextureToTexture.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderFinish = _libraries['webgpu'].wgpuCommandEncoderFinish - wgpuCommandEncoderFinish.restype = WGPUCommandBuffer - wgpuCommandEncoderFinish.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUCommandBufferDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderInjectValidationError = _libraries['webgpu'].wgpuCommandEncoderInjectValidationError - wgpuCommandEncoderInjectValidationError.restype = None - wgpuCommandEncoderInjectValidationError.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderInsertDebugMarker = _libraries['webgpu'].wgpuCommandEncoderInsertDebugMarker - wgpuCommandEncoderInsertDebugMarker.restype = None - wgpuCommandEncoderInsertDebugMarker.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderPopDebugGroup = _libraries['webgpu'].wgpuCommandEncoderPopDebugGroup - wgpuCommandEncoderPopDebugGroup.restype = None - wgpuCommandEncoderPopDebugGroup.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuCommandEncoderPushDebugGroup = _libraries['webgpu'].wgpuCommandEncoderPushDebugGroup - wgpuCommandEncoderPushDebugGroup.restype = None - wgpuCommandEncoderPushDebugGroup.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - wgpuCommandEncoderResolveQuerySet = _libraries['webgpu'].wgpuCommandEncoderResolveQuerySet - wgpuCommandEncoderResolveQuerySet.restype = None - wgpuCommandEncoderResolveQuerySet.argtypes = [WGPUCommandEncoder, WGPUQuerySet, uint32_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderSetLabel = _libraries['webgpu'].wgpuCommandEncoderSetLabel - wgpuCommandEncoderSetLabel.restype = None - wgpuCommandEncoderSetLabel.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderWriteBuffer = _libraries['webgpu'].wgpuCommandEncoderWriteBuffer - wgpuCommandEncoderWriteBuffer.restype = None - wgpuCommandEncoderWriteBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, ctypes.POINTER(ctypes.c_ubyte), uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderWriteTimestamp = _libraries['webgpu'].wgpuCommandEncoderWriteTimestamp - wgpuCommandEncoderWriteTimestamp.restype = None - wgpuCommandEncoderWriteTimestamp.argtypes = [WGPUCommandEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuCommandEncoderAddRef = _libraries['webgpu'].wgpuCommandEncoderAddRef - wgpuCommandEncoderAddRef.restype = None - wgpuCommandEncoderAddRef.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuCommandEncoderRelease = _libraries['webgpu'].wgpuCommandEncoderRelease - wgpuCommandEncoderRelease.restype = None - wgpuCommandEncoderRelease.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderDispatchWorkgroups = _libraries['webgpu'].wgpuComputePassEncoderDispatchWorkgroups - wgpuComputePassEncoderDispatchWorkgroups.restype = None - wgpuComputePassEncoderDispatchWorkgroups.argtypes = [WGPUComputePassEncoder, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderDispatchWorkgroupsIndirect = _libraries['webgpu'].wgpuComputePassEncoderDispatchWorkgroupsIndirect - wgpuComputePassEncoderDispatchWorkgroupsIndirect.restype = None - wgpuComputePassEncoderDispatchWorkgroupsIndirect.argtypes = [WGPUComputePassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderEnd = _libraries['webgpu'].wgpuComputePassEncoderEnd - wgpuComputePassEncoderEnd.restype = None - wgpuComputePassEncoderEnd.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderInsertDebugMarker = _libraries['webgpu'].wgpuComputePassEncoderInsertDebugMarker - wgpuComputePassEncoderInsertDebugMarker.restype = None - wgpuComputePassEncoderInsertDebugMarker.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderPopDebugGroup = _libraries['webgpu'].wgpuComputePassEncoderPopDebugGroup - wgpuComputePassEncoderPopDebugGroup.restype = None - wgpuComputePassEncoderPopDebugGroup.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderPushDebugGroup = _libraries['webgpu'].wgpuComputePassEncoderPushDebugGroup - wgpuComputePassEncoderPushDebugGroup.restype = None - wgpuComputePassEncoderPushDebugGroup.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetBindGroup = _libraries['webgpu'].wgpuComputePassEncoderSetBindGroup - wgpuComputePassEncoderSetBindGroup.restype = None - wgpuComputePassEncoderSetBindGroup.argtypes = [WGPUComputePassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetLabel = _libraries['webgpu'].wgpuComputePassEncoderSetLabel - wgpuComputePassEncoderSetLabel.restype = None - wgpuComputePassEncoderSetLabel.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetPipeline = _libraries['webgpu'].wgpuComputePassEncoderSetPipeline - wgpuComputePassEncoderSetPipeline.restype = None - wgpuComputePassEncoderSetPipeline.argtypes = [WGPUComputePassEncoder, WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuComputePassEncoderWriteTimestamp = _libraries['webgpu'].wgpuComputePassEncoderWriteTimestamp - wgpuComputePassEncoderWriteTimestamp.restype = None - wgpuComputePassEncoderWriteTimestamp.argtypes = [WGPUComputePassEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderAddRef = _libraries['webgpu'].wgpuComputePassEncoderAddRef - wgpuComputePassEncoderAddRef.restype = None - wgpuComputePassEncoderAddRef.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderRelease = _libraries['webgpu'].wgpuComputePassEncoderRelease - wgpuComputePassEncoderRelease.restype = None - wgpuComputePassEncoderRelease.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePipelineGetBindGroupLayout = _libraries['webgpu'].wgpuComputePipelineGetBindGroupLayout - wgpuComputePipelineGetBindGroupLayout.restype = WGPUBindGroupLayout - wgpuComputePipelineGetBindGroupLayout.argtypes = [WGPUComputePipeline, uint32_t] -except AttributeError: - pass -try: - wgpuComputePipelineSetLabel = _libraries['webgpu'].wgpuComputePipelineSetLabel - wgpuComputePipelineSetLabel.restype = None - wgpuComputePipelineSetLabel.argtypes = [WGPUComputePipeline, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePipelineAddRef = _libraries['webgpu'].wgpuComputePipelineAddRef - wgpuComputePipelineAddRef.restype = None - wgpuComputePipelineAddRef.argtypes = [WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuComputePipelineRelease = _libraries['webgpu'].wgpuComputePipelineRelease - wgpuComputePipelineRelease.restype = None - wgpuComputePipelineRelease.argtypes = [WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuDeviceCreateBindGroup = _libraries['webgpu'].wgpuDeviceCreateBindGroup - wgpuDeviceCreateBindGroup.restype = WGPUBindGroup - wgpuDeviceCreateBindGroup.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBindGroupDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateBindGroupLayout = _libraries['webgpu'].wgpuDeviceCreateBindGroupLayout - wgpuDeviceCreateBindGroupLayout.restype = WGPUBindGroupLayout - wgpuDeviceCreateBindGroupLayout.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBindGroupLayoutDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateBuffer = _libraries['webgpu'].wgpuDeviceCreateBuffer - wgpuDeviceCreateBuffer.restype = WGPUBuffer - wgpuDeviceCreateBuffer.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateCommandEncoder = _libraries['webgpu'].wgpuDeviceCreateCommandEncoder - wgpuDeviceCreateCommandEncoder.restype = WGPUCommandEncoder - wgpuDeviceCreateCommandEncoder.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUCommandEncoderDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipeline = _libraries['webgpu'].wgpuDeviceCreateComputePipeline - wgpuDeviceCreateComputePipeline.restype = WGPUComputePipeline - wgpuDeviceCreateComputePipeline.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsync = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsync - wgpuDeviceCreateComputePipelineAsync.restype = None - wgpuDeviceCreateComputePipelineAsync.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsync2 = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsync2 - wgpuDeviceCreateComputePipelineAsync2.restype = WGPUFuture - wgpuDeviceCreateComputePipelineAsync2.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo2] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsyncF = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsyncF - wgpuDeviceCreateComputePipelineAsyncF.restype = WGPUFuture - wgpuDeviceCreateComputePipelineAsyncF.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorBuffer = _libraries['webgpu'].wgpuDeviceCreateErrorBuffer - wgpuDeviceCreateErrorBuffer.restype = WGPUBuffer - wgpuDeviceCreateErrorBuffer.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorExternalTexture = _libraries['webgpu'].wgpuDeviceCreateErrorExternalTexture - wgpuDeviceCreateErrorExternalTexture.restype = WGPUExternalTexture - wgpuDeviceCreateErrorExternalTexture.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorShaderModule = _libraries['webgpu'].wgpuDeviceCreateErrorShaderModule - wgpuDeviceCreateErrorShaderModule.restype = WGPUShaderModule - wgpuDeviceCreateErrorShaderModule.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUShaderModuleDescriptor), WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorTexture = _libraries['webgpu'].wgpuDeviceCreateErrorTexture - wgpuDeviceCreateErrorTexture.restype = WGPUTexture - wgpuDeviceCreateErrorTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateExternalTexture = _libraries['webgpu'].wgpuDeviceCreateExternalTexture - wgpuDeviceCreateExternalTexture.restype = WGPUExternalTexture - wgpuDeviceCreateExternalTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUExternalTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreatePipelineLayout = _libraries['webgpu'].wgpuDeviceCreatePipelineLayout - wgpuDeviceCreatePipelineLayout.restype = WGPUPipelineLayout - wgpuDeviceCreatePipelineLayout.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUPipelineLayoutDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateQuerySet = _libraries['webgpu'].wgpuDeviceCreateQuerySet - wgpuDeviceCreateQuerySet.restype = WGPUQuerySet - wgpuDeviceCreateQuerySet.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUQuerySetDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderBundleEncoder = _libraries['webgpu'].wgpuDeviceCreateRenderBundleEncoder - wgpuDeviceCreateRenderBundleEncoder.restype = WGPURenderBundleEncoder - wgpuDeviceCreateRenderBundleEncoder.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderBundleEncoderDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipeline = _libraries['webgpu'].wgpuDeviceCreateRenderPipeline - wgpuDeviceCreateRenderPipeline.restype = WGPURenderPipeline - wgpuDeviceCreateRenderPipeline.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsync = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsync - wgpuDeviceCreateRenderPipelineAsync.restype = None - wgpuDeviceCreateRenderPipelineAsync.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsync2 = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsync2 - wgpuDeviceCreateRenderPipelineAsync2.restype = WGPUFuture - wgpuDeviceCreateRenderPipelineAsync2.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo2] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsyncF = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsyncF - wgpuDeviceCreateRenderPipelineAsyncF.restype = WGPUFuture - wgpuDeviceCreateRenderPipelineAsyncF.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo] -except AttributeError: - pass -try: - wgpuDeviceCreateSampler = _libraries['webgpu'].wgpuDeviceCreateSampler - wgpuDeviceCreateSampler.restype = WGPUSampler - wgpuDeviceCreateSampler.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSamplerDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateShaderModule = _libraries['webgpu'].wgpuDeviceCreateShaderModule - wgpuDeviceCreateShaderModule.restype = WGPUShaderModule - wgpuDeviceCreateShaderModule.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUShaderModuleDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateTexture = _libraries['webgpu'].wgpuDeviceCreateTexture - wgpuDeviceCreateTexture.restype = WGPUTexture - wgpuDeviceCreateTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceDestroy = _libraries['webgpu'].wgpuDeviceDestroy - wgpuDeviceDestroy.restype = None - wgpuDeviceDestroy.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceForceLoss = _libraries['webgpu'].wgpuDeviceForceLoss - wgpuDeviceForceLoss.restype = None - wgpuDeviceForceLoss.argtypes = [WGPUDevice, WGPUDeviceLostReason, WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceGetAHardwareBufferProperties = _libraries['webgpu'].wgpuDeviceGetAHardwareBufferProperties - wgpuDeviceGetAHardwareBufferProperties.restype = WGPUStatus - wgpuDeviceGetAHardwareBufferProperties.argtypes = [WGPUDevice, ctypes.POINTER(None), ctypes.POINTER(struct_WGPUAHardwareBufferProperties)] -except AttributeError: - pass -try: - wgpuDeviceGetAdapter = _libraries['webgpu'].wgpuDeviceGetAdapter - wgpuDeviceGetAdapter.restype = WGPUAdapter - wgpuDeviceGetAdapter.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceGetAdapterInfo = _libraries['webgpu'].wgpuDeviceGetAdapterInfo - wgpuDeviceGetAdapterInfo.restype = WGPUStatus - wgpuDeviceGetAdapterInfo.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUAdapterInfo)] -except AttributeError: - pass -try: - wgpuDeviceGetFeatures = _libraries['webgpu'].wgpuDeviceGetFeatures - wgpuDeviceGetFeatures.restype = None - wgpuDeviceGetFeatures.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSupportedFeatures)] -except AttributeError: - pass -try: - wgpuDeviceGetLimits = _libraries['webgpu'].wgpuDeviceGetLimits - wgpuDeviceGetLimits.restype = WGPUStatus - wgpuDeviceGetLimits.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSupportedLimits)] -except AttributeError: - pass -try: - wgpuDeviceGetLostFuture = _libraries['webgpu'].wgpuDeviceGetLostFuture - wgpuDeviceGetLostFuture.restype = WGPUFuture - wgpuDeviceGetLostFuture.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceGetQueue = _libraries['webgpu'].wgpuDeviceGetQueue - wgpuDeviceGetQueue.restype = WGPUQueue - wgpuDeviceGetQueue.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceHasFeature = _libraries['webgpu'].wgpuDeviceHasFeature - wgpuDeviceHasFeature.restype = WGPUBool - wgpuDeviceHasFeature.argtypes = [WGPUDevice, WGPUFeatureName] -except AttributeError: - pass -try: - wgpuDeviceImportSharedBufferMemory = _libraries['webgpu'].wgpuDeviceImportSharedBufferMemory - wgpuDeviceImportSharedBufferMemory.restype = WGPUSharedBufferMemory - wgpuDeviceImportSharedBufferMemory.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedBufferMemoryDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceImportSharedFence = _libraries['webgpu'].wgpuDeviceImportSharedFence - wgpuDeviceImportSharedFence.restype = WGPUSharedFence - wgpuDeviceImportSharedFence.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedFenceDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceImportSharedTextureMemory = _libraries['webgpu'].wgpuDeviceImportSharedTextureMemory - wgpuDeviceImportSharedTextureMemory.restype = WGPUSharedTextureMemory - wgpuDeviceImportSharedTextureMemory.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedTextureMemoryDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceInjectError = _libraries['webgpu'].wgpuDeviceInjectError - wgpuDeviceInjectError.restype = None - wgpuDeviceInjectError.argtypes = [WGPUDevice, WGPUErrorType, WGPUStringView] -except AttributeError: - pass -try: - wgpuDevicePopErrorScope = _libraries['webgpu'].wgpuDevicePopErrorScope - wgpuDevicePopErrorScope.restype = None - wgpuDevicePopErrorScope.argtypes = [WGPUDevice, WGPUErrorCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDevicePopErrorScope2 = _libraries['webgpu'].wgpuDevicePopErrorScope2 - wgpuDevicePopErrorScope2.restype = WGPUFuture - wgpuDevicePopErrorScope2.argtypes = [WGPUDevice, WGPUPopErrorScopeCallbackInfo2] -except AttributeError: - pass -try: - wgpuDevicePopErrorScopeF = _libraries['webgpu'].wgpuDevicePopErrorScopeF - wgpuDevicePopErrorScopeF.restype = WGPUFuture - wgpuDevicePopErrorScopeF.argtypes = [WGPUDevice, WGPUPopErrorScopeCallbackInfo] -except AttributeError: - pass -try: - wgpuDevicePushErrorScope = _libraries['webgpu'].wgpuDevicePushErrorScope - wgpuDevicePushErrorScope.restype = None - wgpuDevicePushErrorScope.argtypes = [WGPUDevice, WGPUErrorFilter] -except AttributeError: - pass -try: - wgpuDeviceSetLabel = _libraries['webgpu'].wgpuDeviceSetLabel - wgpuDeviceSetLabel.restype = None - wgpuDeviceSetLabel.argtypes = [WGPUDevice, WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceSetLoggingCallback = _libraries['webgpu'].wgpuDeviceSetLoggingCallback - wgpuDeviceSetLoggingCallback.restype = None - wgpuDeviceSetLoggingCallback.argtypes = [WGPUDevice, WGPULoggingCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceTick = _libraries['webgpu'].wgpuDeviceTick - wgpuDeviceTick.restype = None - wgpuDeviceTick.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceValidateTextureDescriptor = _libraries['webgpu'].wgpuDeviceValidateTextureDescriptor - wgpuDeviceValidateTextureDescriptor.restype = None - wgpuDeviceValidateTextureDescriptor.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceAddRef = _libraries['webgpu'].wgpuDeviceAddRef - wgpuDeviceAddRef.restype = None - wgpuDeviceAddRef.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceRelease = _libraries['webgpu'].wgpuDeviceRelease - wgpuDeviceRelease.restype = None - wgpuDeviceRelease.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuExternalTextureDestroy = _libraries['webgpu'].wgpuExternalTextureDestroy - wgpuExternalTextureDestroy.restype = None - wgpuExternalTextureDestroy.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureExpire = _libraries['webgpu'].wgpuExternalTextureExpire - wgpuExternalTextureExpire.restype = None - wgpuExternalTextureExpire.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureRefresh = _libraries['webgpu'].wgpuExternalTextureRefresh - wgpuExternalTextureRefresh.restype = None - wgpuExternalTextureRefresh.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureSetLabel = _libraries['webgpu'].wgpuExternalTextureSetLabel - wgpuExternalTextureSetLabel.restype = None - wgpuExternalTextureSetLabel.argtypes = [WGPUExternalTexture, WGPUStringView] -except AttributeError: - pass -try: - wgpuExternalTextureAddRef = _libraries['webgpu'].wgpuExternalTextureAddRef - wgpuExternalTextureAddRef.restype = None - wgpuExternalTextureAddRef.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureRelease = _libraries['webgpu'].wgpuExternalTextureRelease - wgpuExternalTextureRelease.restype = None - wgpuExternalTextureRelease.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuInstanceCreateSurface = _libraries['webgpu'].wgpuInstanceCreateSurface - wgpuInstanceCreateSurface.restype = WGPUSurface - wgpuInstanceCreateSurface.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPUSurfaceDescriptor)] -except AttributeError: - pass -try: - wgpuInstanceEnumerateWGSLLanguageFeatures = _libraries['webgpu'].wgpuInstanceEnumerateWGSLLanguageFeatures - wgpuInstanceEnumerateWGSLLanguageFeatures.restype = size_t - wgpuInstanceEnumerateWGSLLanguageFeatures.argtypes = [WGPUInstance, ctypes.POINTER(WGPUWGSLFeatureName)] -except AttributeError: - pass -try: - wgpuInstanceHasWGSLLanguageFeature = _libraries['webgpu'].wgpuInstanceHasWGSLLanguageFeature - wgpuInstanceHasWGSLLanguageFeature.restype = WGPUBool - wgpuInstanceHasWGSLLanguageFeature.argtypes = [WGPUInstance, WGPUWGSLFeatureName] -except AttributeError: - pass -try: - wgpuInstanceProcessEvents = _libraries['webgpu'].wgpuInstanceProcessEvents - wgpuInstanceProcessEvents.restype = None - wgpuInstanceProcessEvents.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapter = _libraries['webgpu'].wgpuInstanceRequestAdapter - wgpuInstanceRequestAdapter.restype = None - wgpuInstanceRequestAdapter.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapter2 = _libraries['webgpu'].wgpuInstanceRequestAdapter2 - wgpuInstanceRequestAdapter2.restype = WGPUFuture - wgpuInstanceRequestAdapter2.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo2] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapterF = _libraries['webgpu'].wgpuInstanceRequestAdapterF - wgpuInstanceRequestAdapterF.restype = WGPUFuture - wgpuInstanceRequestAdapterF.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo] -except AttributeError: - pass -try: - wgpuInstanceWaitAny = _libraries['webgpu'].wgpuInstanceWaitAny - wgpuInstanceWaitAny.restype = WGPUWaitStatus - wgpuInstanceWaitAny.argtypes = [WGPUInstance, size_t, ctypes.POINTER(struct_WGPUFutureWaitInfo), uint64_t] -except AttributeError: - pass -try: - wgpuInstanceAddRef = _libraries['webgpu'].wgpuInstanceAddRef - wgpuInstanceAddRef.restype = None - wgpuInstanceAddRef.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuInstanceRelease = _libraries['webgpu'].wgpuInstanceRelease - wgpuInstanceRelease.restype = None - wgpuInstanceRelease.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuPipelineLayoutSetLabel = _libraries['webgpu'].wgpuPipelineLayoutSetLabel - wgpuPipelineLayoutSetLabel.restype = None - wgpuPipelineLayoutSetLabel.argtypes = [WGPUPipelineLayout, WGPUStringView] -except AttributeError: - pass -try: - wgpuPipelineLayoutAddRef = _libraries['webgpu'].wgpuPipelineLayoutAddRef - wgpuPipelineLayoutAddRef.restype = None - wgpuPipelineLayoutAddRef.argtypes = [WGPUPipelineLayout] -except AttributeError: - pass -try: - wgpuPipelineLayoutRelease = _libraries['webgpu'].wgpuPipelineLayoutRelease - wgpuPipelineLayoutRelease.restype = None - wgpuPipelineLayoutRelease.argtypes = [WGPUPipelineLayout] -except AttributeError: - pass -try: - wgpuQuerySetDestroy = _libraries['webgpu'].wgpuQuerySetDestroy - wgpuQuerySetDestroy.restype = None - wgpuQuerySetDestroy.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetGetCount = _libraries['webgpu'].wgpuQuerySetGetCount - wgpuQuerySetGetCount.restype = uint32_t - wgpuQuerySetGetCount.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetGetType = _libraries['webgpu'].wgpuQuerySetGetType - wgpuQuerySetGetType.restype = WGPUQueryType - wgpuQuerySetGetType.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetSetLabel = _libraries['webgpu'].wgpuQuerySetSetLabel - wgpuQuerySetSetLabel.restype = None - wgpuQuerySetSetLabel.argtypes = [WGPUQuerySet, WGPUStringView] -except AttributeError: - pass -try: - wgpuQuerySetAddRef = _libraries['webgpu'].wgpuQuerySetAddRef - wgpuQuerySetAddRef.restype = None - wgpuQuerySetAddRef.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetRelease = _libraries['webgpu'].wgpuQuerySetRelease - wgpuQuerySetRelease.restype = None - wgpuQuerySetRelease.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQueueCopyExternalTextureForBrowser = _libraries['webgpu'].wgpuQueueCopyExternalTextureForBrowser - wgpuQueueCopyExternalTextureForBrowser.restype = None - wgpuQueueCopyExternalTextureForBrowser.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyExternalTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)] -except AttributeError: - pass -try: - wgpuQueueCopyTextureForBrowser = _libraries['webgpu'].wgpuQueueCopyTextureForBrowser - wgpuQueueCopyTextureForBrowser.restype = None - wgpuQueueCopyTextureForBrowser.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDone = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDone - wgpuQueueOnSubmittedWorkDone.restype = None - wgpuQueueOnSubmittedWorkDone.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDone2 = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDone2 - wgpuQueueOnSubmittedWorkDone2.restype = WGPUFuture - wgpuQueueOnSubmittedWorkDone2.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallbackInfo2] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDoneF = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDoneF - wgpuQueueOnSubmittedWorkDoneF.restype = WGPUFuture - wgpuQueueOnSubmittedWorkDoneF.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallbackInfo] -except AttributeError: - pass -try: - wgpuQueueSetLabel = _libraries['webgpu'].wgpuQueueSetLabel - wgpuQueueSetLabel.restype = None - wgpuQueueSetLabel.argtypes = [WGPUQueue, WGPUStringView] -except AttributeError: - pass -try: - wgpuQueueSubmit = _libraries['webgpu'].wgpuQueueSubmit - wgpuQueueSubmit.restype = None - wgpuQueueSubmit.argtypes = [WGPUQueue, size_t, ctypes.POINTER(ctypes.POINTER(struct_WGPUCommandBufferImpl))] -except AttributeError: - pass -try: - wgpuQueueWriteBuffer = _libraries['webgpu'].wgpuQueueWriteBuffer - wgpuQueueWriteBuffer.restype = None - wgpuQueueWriteBuffer.argtypes = [WGPUQueue, WGPUBuffer, uint64_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - wgpuQueueWriteTexture = _libraries['webgpu'].wgpuQueueWriteTexture - wgpuQueueWriteTexture.restype = None - wgpuQueueWriteTexture.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(None), size_t, ctypes.POINTER(struct_WGPUTextureDataLayout), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuQueueAddRef = _libraries['webgpu'].wgpuQueueAddRef - wgpuQueueAddRef.restype = None - wgpuQueueAddRef.argtypes = [WGPUQueue] -except AttributeError: - pass -try: - wgpuQueueRelease = _libraries['webgpu'].wgpuQueueRelease - wgpuQueueRelease.restype = None - wgpuQueueRelease.argtypes = [WGPUQueue] -except AttributeError: - pass -try: - wgpuRenderBundleSetLabel = _libraries['webgpu'].wgpuRenderBundleSetLabel - wgpuRenderBundleSetLabel.restype = None - wgpuRenderBundleSetLabel.argtypes = [WGPURenderBundle, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleAddRef = _libraries['webgpu'].wgpuRenderBundleAddRef - wgpuRenderBundleAddRef.restype = None - wgpuRenderBundleAddRef.argtypes = [WGPURenderBundle] -except AttributeError: - pass -try: - wgpuRenderBundleRelease = _libraries['webgpu'].wgpuRenderBundleRelease - wgpuRenderBundleRelease.restype = None - wgpuRenderBundleRelease.argtypes = [WGPURenderBundle] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDraw = _libraries['webgpu'].wgpuRenderBundleEncoderDraw - wgpuRenderBundleEncoderDraw.restype = None - wgpuRenderBundleEncoderDraw.argtypes = [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -int32_t = ctypes.c_int32 -try: - wgpuRenderBundleEncoderDrawIndexed = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndexed - wgpuRenderBundleEncoderDrawIndexed.restype = None - wgpuRenderBundleEncoderDrawIndexed.argtypes = [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndexedIndirect - wgpuRenderBundleEncoderDrawIndexedIndirect.restype = None - wgpuRenderBundleEncoderDrawIndexedIndirect.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDrawIndirect = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndirect - wgpuRenderBundleEncoderDrawIndirect.restype = None - wgpuRenderBundleEncoderDrawIndirect.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderFinish = _libraries['webgpu'].wgpuRenderBundleEncoderFinish - wgpuRenderBundleEncoderFinish.restype = WGPURenderBundle - wgpuRenderBundleEncoderFinish.argtypes = [WGPURenderBundleEncoder, ctypes.POINTER(struct_WGPURenderBundleDescriptor)] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderInsertDebugMarker = _libraries['webgpu'].wgpuRenderBundleEncoderInsertDebugMarker - wgpuRenderBundleEncoderInsertDebugMarker.restype = None - wgpuRenderBundleEncoderInsertDebugMarker.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderPopDebugGroup = _libraries['webgpu'].wgpuRenderBundleEncoderPopDebugGroup - wgpuRenderBundleEncoderPopDebugGroup.restype = None - wgpuRenderBundleEncoderPopDebugGroup.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderPushDebugGroup = _libraries['webgpu'].wgpuRenderBundleEncoderPushDebugGroup - wgpuRenderBundleEncoderPushDebugGroup.restype = None - wgpuRenderBundleEncoderPushDebugGroup.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetBindGroup = _libraries['webgpu'].wgpuRenderBundleEncoderSetBindGroup - wgpuRenderBundleEncoderSetBindGroup.restype = None - wgpuRenderBundleEncoderSetBindGroup.argtypes = [WGPURenderBundleEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetIndexBuffer = _libraries['webgpu'].wgpuRenderBundleEncoderSetIndexBuffer - wgpuRenderBundleEncoderSetIndexBuffer.restype = None - wgpuRenderBundleEncoderSetIndexBuffer.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetLabel = _libraries['webgpu'].wgpuRenderBundleEncoderSetLabel - wgpuRenderBundleEncoderSetLabel.restype = None - wgpuRenderBundleEncoderSetLabel.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetPipeline = _libraries['webgpu'].wgpuRenderBundleEncoderSetPipeline - wgpuRenderBundleEncoderSetPipeline.restype = None - wgpuRenderBundleEncoderSetPipeline.argtypes = [WGPURenderBundleEncoder, WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetVertexBuffer = _libraries['webgpu'].wgpuRenderBundleEncoderSetVertexBuffer - wgpuRenderBundleEncoderSetVertexBuffer.restype = None - wgpuRenderBundleEncoderSetVertexBuffer.argtypes = [WGPURenderBundleEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderAddRef = _libraries['webgpu'].wgpuRenderBundleEncoderAddRef - wgpuRenderBundleEncoderAddRef.restype = None - wgpuRenderBundleEncoderAddRef.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderRelease = _libraries['webgpu'].wgpuRenderBundleEncoderRelease - wgpuRenderBundleEncoderRelease.restype = None - wgpuRenderBundleEncoderRelease.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderBeginOcclusionQuery = _libraries['webgpu'].wgpuRenderPassEncoderBeginOcclusionQuery - wgpuRenderPassEncoderBeginOcclusionQuery.restype = None - wgpuRenderPassEncoderBeginOcclusionQuery.argtypes = [WGPURenderPassEncoder, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDraw = _libraries['webgpu'].wgpuRenderPassEncoderDraw - wgpuRenderPassEncoderDraw.restype = None - wgpuRenderPassEncoderDraw.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndexed = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndexed - wgpuRenderPassEncoderDrawIndexed.restype = None - wgpuRenderPassEncoderDrawIndexed.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndexedIndirect - wgpuRenderPassEncoderDrawIndexedIndirect.restype = None - wgpuRenderPassEncoderDrawIndexedIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndirect = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndirect - wgpuRenderPassEncoderDrawIndirect.restype = None - wgpuRenderPassEncoderDrawIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderEnd = _libraries['webgpu'].wgpuRenderPassEncoderEnd - wgpuRenderPassEncoderEnd.restype = None - wgpuRenderPassEncoderEnd.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderEndOcclusionQuery = _libraries['webgpu'].wgpuRenderPassEncoderEndOcclusionQuery - wgpuRenderPassEncoderEndOcclusionQuery.restype = None - wgpuRenderPassEncoderEndOcclusionQuery.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderExecuteBundles = _libraries['webgpu'].wgpuRenderPassEncoderExecuteBundles - wgpuRenderPassEncoderExecuteBundles.restype = None - wgpuRenderPassEncoderExecuteBundles.argtypes = [WGPURenderPassEncoder, size_t, ctypes.POINTER(ctypes.POINTER(struct_WGPURenderBundleImpl))] -except AttributeError: - pass -try: - wgpuRenderPassEncoderInsertDebugMarker = _libraries['webgpu'].wgpuRenderPassEncoderInsertDebugMarker - wgpuRenderPassEncoderInsertDebugMarker.restype = None - wgpuRenderPassEncoderInsertDebugMarker.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderMultiDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderPassEncoderMultiDrawIndexedIndirect - wgpuRenderPassEncoderMultiDrawIndexedIndirect.restype = None - wgpuRenderPassEncoderMultiDrawIndexedIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderMultiDrawIndirect = _libraries['webgpu'].wgpuRenderPassEncoderMultiDrawIndirect - wgpuRenderPassEncoderMultiDrawIndirect.restype = None - wgpuRenderPassEncoderMultiDrawIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPixelLocalStorageBarrier = _libraries['webgpu'].wgpuRenderPassEncoderPixelLocalStorageBarrier - wgpuRenderPassEncoderPixelLocalStorageBarrier.restype = None - wgpuRenderPassEncoderPixelLocalStorageBarrier.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPopDebugGroup = _libraries['webgpu'].wgpuRenderPassEncoderPopDebugGroup - wgpuRenderPassEncoderPopDebugGroup.restype = None - wgpuRenderPassEncoderPopDebugGroup.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPushDebugGroup = _libraries['webgpu'].wgpuRenderPassEncoderPushDebugGroup - wgpuRenderPassEncoderPushDebugGroup.restype = None - wgpuRenderPassEncoderPushDebugGroup.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetBindGroup = _libraries['webgpu'].wgpuRenderPassEncoderSetBindGroup - wgpuRenderPassEncoderSetBindGroup.restype = None - wgpuRenderPassEncoderSetBindGroup.argtypes = [WGPURenderPassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetBlendConstant = _libraries['webgpu'].wgpuRenderPassEncoderSetBlendConstant - wgpuRenderPassEncoderSetBlendConstant.restype = None - wgpuRenderPassEncoderSetBlendConstant.argtypes = [WGPURenderPassEncoder, ctypes.POINTER(struct_WGPUColor)] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetIndexBuffer = _libraries['webgpu'].wgpuRenderPassEncoderSetIndexBuffer - wgpuRenderPassEncoderSetIndexBuffer.restype = None - wgpuRenderPassEncoderSetIndexBuffer.argtypes = [WGPURenderPassEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetLabel = _libraries['webgpu'].wgpuRenderPassEncoderSetLabel - wgpuRenderPassEncoderSetLabel.restype = None - wgpuRenderPassEncoderSetLabel.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetPipeline = _libraries['webgpu'].wgpuRenderPassEncoderSetPipeline - wgpuRenderPassEncoderSetPipeline.restype = None - wgpuRenderPassEncoderSetPipeline.argtypes = [WGPURenderPassEncoder, WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetScissorRect = _libraries['webgpu'].wgpuRenderPassEncoderSetScissorRect - wgpuRenderPassEncoderSetScissorRect.restype = None - wgpuRenderPassEncoderSetScissorRect.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetStencilReference = _libraries['webgpu'].wgpuRenderPassEncoderSetStencilReference - wgpuRenderPassEncoderSetStencilReference.restype = None - wgpuRenderPassEncoderSetStencilReference.argtypes = [WGPURenderPassEncoder, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetVertexBuffer = _libraries['webgpu'].wgpuRenderPassEncoderSetVertexBuffer - wgpuRenderPassEncoderSetVertexBuffer.restype = None - wgpuRenderPassEncoderSetVertexBuffer.argtypes = [WGPURenderPassEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetViewport = _libraries['webgpu'].wgpuRenderPassEncoderSetViewport - wgpuRenderPassEncoderSetViewport.restype = None - wgpuRenderPassEncoderSetViewport.argtypes = [WGPURenderPassEncoder, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - wgpuRenderPassEncoderWriteTimestamp = _libraries['webgpu'].wgpuRenderPassEncoderWriteTimestamp - wgpuRenderPassEncoderWriteTimestamp.restype = None - wgpuRenderPassEncoderWriteTimestamp.argtypes = [WGPURenderPassEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderAddRef = _libraries['webgpu'].wgpuRenderPassEncoderAddRef - wgpuRenderPassEncoderAddRef.restype = None - wgpuRenderPassEncoderAddRef.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderRelease = _libraries['webgpu'].wgpuRenderPassEncoderRelease - wgpuRenderPassEncoderRelease.restype = None - wgpuRenderPassEncoderRelease.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPipelineGetBindGroupLayout = _libraries['webgpu'].wgpuRenderPipelineGetBindGroupLayout - wgpuRenderPipelineGetBindGroupLayout.restype = WGPUBindGroupLayout - wgpuRenderPipelineGetBindGroupLayout.argtypes = [WGPURenderPipeline, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPipelineSetLabel = _libraries['webgpu'].wgpuRenderPipelineSetLabel - wgpuRenderPipelineSetLabel.restype = None - wgpuRenderPipelineSetLabel.argtypes = [WGPURenderPipeline, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPipelineAddRef = _libraries['webgpu'].wgpuRenderPipelineAddRef - wgpuRenderPipelineAddRef.restype = None - wgpuRenderPipelineAddRef.argtypes = [WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderPipelineRelease = _libraries['webgpu'].wgpuRenderPipelineRelease - wgpuRenderPipelineRelease.restype = None - wgpuRenderPipelineRelease.argtypes = [WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuSamplerSetLabel = _libraries['webgpu'].wgpuSamplerSetLabel - wgpuSamplerSetLabel.restype = None - wgpuSamplerSetLabel.argtypes = [WGPUSampler, WGPUStringView] -except AttributeError: - pass -try: - wgpuSamplerAddRef = _libraries['webgpu'].wgpuSamplerAddRef - wgpuSamplerAddRef.restype = None - wgpuSamplerAddRef.argtypes = [WGPUSampler] -except AttributeError: - pass -try: - wgpuSamplerRelease = _libraries['webgpu'].wgpuSamplerRelease - wgpuSamplerRelease.restype = None - wgpuSamplerRelease.argtypes = [WGPUSampler] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfo = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfo - wgpuShaderModuleGetCompilationInfo.restype = None - wgpuShaderModuleGetCompilationInfo.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfo2 = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfo2 - wgpuShaderModuleGetCompilationInfo2.restype = WGPUFuture - wgpuShaderModuleGetCompilationInfo2.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallbackInfo2] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfoF = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfoF - wgpuShaderModuleGetCompilationInfoF.restype = WGPUFuture - wgpuShaderModuleGetCompilationInfoF.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallbackInfo] -except AttributeError: - pass -try: - wgpuShaderModuleSetLabel = _libraries['webgpu'].wgpuShaderModuleSetLabel - wgpuShaderModuleSetLabel.restype = None - wgpuShaderModuleSetLabel.argtypes = [WGPUShaderModule, WGPUStringView] -except AttributeError: - pass -try: - wgpuShaderModuleAddRef = _libraries['webgpu'].wgpuShaderModuleAddRef - wgpuShaderModuleAddRef.restype = None - wgpuShaderModuleAddRef.argtypes = [WGPUShaderModule] -except AttributeError: - pass -try: - wgpuShaderModuleRelease = _libraries['webgpu'].wgpuShaderModuleRelease - wgpuShaderModuleRelease.restype = None - wgpuShaderModuleRelease.argtypes = [WGPUShaderModule] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryBeginAccess = _libraries['webgpu'].wgpuSharedBufferMemoryBeginAccess - wgpuSharedBufferMemoryBeginAccess.restype = WGPUStatus - wgpuSharedBufferMemoryBeginAccess.argtypes = [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(struct_WGPUSharedBufferMemoryBeginAccessDescriptor)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryCreateBuffer = _libraries['webgpu'].wgpuSharedBufferMemoryCreateBuffer - wgpuSharedBufferMemoryCreateBuffer.restype = WGPUBuffer - wgpuSharedBufferMemoryCreateBuffer.argtypes = [WGPUSharedBufferMemory, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryEndAccess = _libraries['webgpu'].wgpuSharedBufferMemoryEndAccess - wgpuSharedBufferMemoryEndAccess.restype = WGPUStatus - wgpuSharedBufferMemoryEndAccess.argtypes = [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(struct_WGPUSharedBufferMemoryEndAccessState)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryGetProperties = _libraries['webgpu'].wgpuSharedBufferMemoryGetProperties - wgpuSharedBufferMemoryGetProperties.restype = WGPUStatus - wgpuSharedBufferMemoryGetProperties.argtypes = [WGPUSharedBufferMemory, ctypes.POINTER(struct_WGPUSharedBufferMemoryProperties)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryIsDeviceLost = _libraries['webgpu'].wgpuSharedBufferMemoryIsDeviceLost - wgpuSharedBufferMemoryIsDeviceLost.restype = WGPUBool - wgpuSharedBufferMemoryIsDeviceLost.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedBufferMemorySetLabel = _libraries['webgpu'].wgpuSharedBufferMemorySetLabel - wgpuSharedBufferMemorySetLabel.restype = None - wgpuSharedBufferMemorySetLabel.argtypes = [WGPUSharedBufferMemory, WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryAddRef = _libraries['webgpu'].wgpuSharedBufferMemoryAddRef - wgpuSharedBufferMemoryAddRef.restype = None - wgpuSharedBufferMemoryAddRef.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryRelease = _libraries['webgpu'].wgpuSharedBufferMemoryRelease - wgpuSharedBufferMemoryRelease.restype = None - wgpuSharedBufferMemoryRelease.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedFenceExportInfo = _libraries['webgpu'].wgpuSharedFenceExportInfo - wgpuSharedFenceExportInfo.restype = None - wgpuSharedFenceExportInfo.argtypes = [WGPUSharedFence, ctypes.POINTER(struct_WGPUSharedFenceExportInfo)] -except AttributeError: - pass -try: - wgpuSharedFenceAddRef = _libraries['webgpu'].wgpuSharedFenceAddRef - wgpuSharedFenceAddRef.restype = None - wgpuSharedFenceAddRef.argtypes = [WGPUSharedFence] -except AttributeError: - pass -try: - wgpuSharedFenceRelease = _libraries['webgpu'].wgpuSharedFenceRelease - wgpuSharedFenceRelease.restype = None - wgpuSharedFenceRelease.argtypes = [WGPUSharedFence] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryBeginAccess = _libraries['webgpu'].wgpuSharedTextureMemoryBeginAccess - wgpuSharedTextureMemoryBeginAccess.restype = WGPUStatus - wgpuSharedTextureMemoryBeginAccess.argtypes = [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(struct_WGPUSharedTextureMemoryBeginAccessDescriptor)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryCreateTexture = _libraries['webgpu'].wgpuSharedTextureMemoryCreateTexture - wgpuSharedTextureMemoryCreateTexture.restype = WGPUTexture - wgpuSharedTextureMemoryCreateTexture.argtypes = [WGPUSharedTextureMemory, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryEndAccess = _libraries['webgpu'].wgpuSharedTextureMemoryEndAccess - wgpuSharedTextureMemoryEndAccess.restype = WGPUStatus - wgpuSharedTextureMemoryEndAccess.argtypes = [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(struct_WGPUSharedTextureMemoryEndAccessState)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryGetProperties = _libraries['webgpu'].wgpuSharedTextureMemoryGetProperties - wgpuSharedTextureMemoryGetProperties.restype = WGPUStatus - wgpuSharedTextureMemoryGetProperties.argtypes = [WGPUSharedTextureMemory, ctypes.POINTER(struct_WGPUSharedTextureMemoryProperties)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryIsDeviceLost = _libraries['webgpu'].wgpuSharedTextureMemoryIsDeviceLost - wgpuSharedTextureMemoryIsDeviceLost.restype = WGPUBool - wgpuSharedTextureMemoryIsDeviceLost.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSharedTextureMemorySetLabel = _libraries['webgpu'].wgpuSharedTextureMemorySetLabel - wgpuSharedTextureMemorySetLabel.restype = None - wgpuSharedTextureMemorySetLabel.argtypes = [WGPUSharedTextureMemory, WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryAddRef = _libraries['webgpu'].wgpuSharedTextureMemoryAddRef - wgpuSharedTextureMemoryAddRef.restype = None - wgpuSharedTextureMemoryAddRef.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryRelease = _libraries['webgpu'].wgpuSharedTextureMemoryRelease - wgpuSharedTextureMemoryRelease.restype = None - wgpuSharedTextureMemoryRelease.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSurfaceConfigure = _libraries['webgpu'].wgpuSurfaceConfigure - wgpuSurfaceConfigure.restype = None - wgpuSurfaceConfigure.argtypes = [WGPUSurface, ctypes.POINTER(struct_WGPUSurfaceConfiguration)] -except AttributeError: - pass -try: - wgpuSurfaceGetCapabilities = _libraries['webgpu'].wgpuSurfaceGetCapabilities - wgpuSurfaceGetCapabilities.restype = WGPUStatus - wgpuSurfaceGetCapabilities.argtypes = [WGPUSurface, WGPUAdapter, ctypes.POINTER(struct_WGPUSurfaceCapabilities)] -except AttributeError: - pass -try: - wgpuSurfaceGetCurrentTexture = _libraries['webgpu'].wgpuSurfaceGetCurrentTexture - wgpuSurfaceGetCurrentTexture.restype = None - wgpuSurfaceGetCurrentTexture.argtypes = [WGPUSurface, ctypes.POINTER(struct_WGPUSurfaceTexture)] -except AttributeError: - pass -try: - wgpuSurfacePresent = _libraries['webgpu'].wgpuSurfacePresent - wgpuSurfacePresent.restype = None - wgpuSurfacePresent.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceSetLabel = _libraries['webgpu'].wgpuSurfaceSetLabel - wgpuSurfaceSetLabel.restype = None - wgpuSurfaceSetLabel.argtypes = [WGPUSurface, WGPUStringView] -except AttributeError: - pass -try: - wgpuSurfaceUnconfigure = _libraries['webgpu'].wgpuSurfaceUnconfigure - wgpuSurfaceUnconfigure.restype = None - wgpuSurfaceUnconfigure.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceAddRef = _libraries['webgpu'].wgpuSurfaceAddRef - wgpuSurfaceAddRef.restype = None - wgpuSurfaceAddRef.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceRelease = _libraries['webgpu'].wgpuSurfaceRelease - wgpuSurfaceRelease.restype = None - wgpuSurfaceRelease.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuTextureCreateErrorView = _libraries['webgpu'].wgpuTextureCreateErrorView - wgpuTextureCreateErrorView.restype = WGPUTextureView - wgpuTextureCreateErrorView.argtypes = [WGPUTexture, ctypes.POINTER(struct_WGPUTextureViewDescriptor)] -except AttributeError: - pass -try: - wgpuTextureCreateView = _libraries['webgpu'].wgpuTextureCreateView - wgpuTextureCreateView.restype = WGPUTextureView - wgpuTextureCreateView.argtypes = [WGPUTexture, ctypes.POINTER(struct_WGPUTextureViewDescriptor)] -except AttributeError: - pass -try: - wgpuTextureDestroy = _libraries['webgpu'].wgpuTextureDestroy - wgpuTextureDestroy.restype = None - wgpuTextureDestroy.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetDepthOrArrayLayers = _libraries['webgpu'].wgpuTextureGetDepthOrArrayLayers - wgpuTextureGetDepthOrArrayLayers.restype = uint32_t - wgpuTextureGetDepthOrArrayLayers.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetDimension = _libraries['webgpu'].wgpuTextureGetDimension - wgpuTextureGetDimension.restype = WGPUTextureDimension - wgpuTextureGetDimension.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetFormat = _libraries['webgpu'].wgpuTextureGetFormat - wgpuTextureGetFormat.restype = WGPUTextureFormat - wgpuTextureGetFormat.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetHeight = _libraries['webgpu'].wgpuTextureGetHeight - wgpuTextureGetHeight.restype = uint32_t - wgpuTextureGetHeight.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetMipLevelCount = _libraries['webgpu'].wgpuTextureGetMipLevelCount - wgpuTextureGetMipLevelCount.restype = uint32_t - wgpuTextureGetMipLevelCount.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetSampleCount = _libraries['webgpu'].wgpuTextureGetSampleCount - wgpuTextureGetSampleCount.restype = uint32_t - wgpuTextureGetSampleCount.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetUsage = _libraries['webgpu'].wgpuTextureGetUsage - wgpuTextureGetUsage.restype = WGPUTextureUsage - wgpuTextureGetUsage.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetWidth = _libraries['webgpu'].wgpuTextureGetWidth - wgpuTextureGetWidth.restype = uint32_t - wgpuTextureGetWidth.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureSetLabel = _libraries['webgpu'].wgpuTextureSetLabel - wgpuTextureSetLabel.restype = None - wgpuTextureSetLabel.argtypes = [WGPUTexture, WGPUStringView] -except AttributeError: - pass -try: - wgpuTextureAddRef = _libraries['webgpu'].wgpuTextureAddRef - wgpuTextureAddRef.restype = None - wgpuTextureAddRef.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureRelease = _libraries['webgpu'].wgpuTextureRelease - wgpuTextureRelease.restype = None - wgpuTextureRelease.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureViewSetLabel = _libraries['webgpu'].wgpuTextureViewSetLabel - wgpuTextureViewSetLabel.restype = None - wgpuTextureViewSetLabel.argtypes = [WGPUTextureView, WGPUStringView] -except AttributeError: - pass -try: - wgpuTextureViewAddRef = _libraries['webgpu'].wgpuTextureViewAddRef - wgpuTextureViewAddRef.restype = None - wgpuTextureViewAddRef.argtypes = [WGPUTextureView] -except AttributeError: - pass -try: - wgpuTextureViewRelease = _libraries['webgpu'].wgpuTextureViewRelease - wgpuTextureViewRelease.restype = None - wgpuTextureViewRelease.argtypes = [WGPUTextureView] -except AttributeError: - pass -__all__ = \ - ['WGPUAHardwareBufferProperties', 'WGPUAdapter', - 'WGPUAdapterInfo', 'WGPUAdapterPropertiesD3D', - 'WGPUAdapterPropertiesMemoryHeaps', - 'WGPUAdapterPropertiesSubgroups', 'WGPUAdapterPropertiesVk', - 'WGPUAdapterType', 'WGPUAdapterType_CPU', - 'WGPUAdapterType_DiscreteGPU', 'WGPUAdapterType_Force32', - 'WGPUAdapterType_IntegratedGPU', 'WGPUAdapterType_Unknown', - 'WGPUAddressMode', 'WGPUAddressMode_ClampToEdge', - 'WGPUAddressMode_Force32', 'WGPUAddressMode_MirrorRepeat', - 'WGPUAddressMode_Repeat', 'WGPUAddressMode_Undefined', - 'WGPUAlphaMode', 'WGPUAlphaMode_Force32', 'WGPUAlphaMode_Opaque', - 'WGPUAlphaMode_Premultiplied', 'WGPUAlphaMode_Unpremultiplied', - 'WGPUBackendType', 'WGPUBackendType_D3D11', - 'WGPUBackendType_D3D12', 'WGPUBackendType_Force32', - 'WGPUBackendType_Metal', 'WGPUBackendType_Null', - 'WGPUBackendType_OpenGL', 'WGPUBackendType_OpenGLES', - 'WGPUBackendType_Undefined', 'WGPUBackendType_Vulkan', - 'WGPUBackendType_WebGPU', 'WGPUBindGroup', - 'WGPUBindGroupDescriptor', 'WGPUBindGroupEntry', - 'WGPUBindGroupLayout', 'WGPUBindGroupLayoutDescriptor', - 'WGPUBindGroupLayoutEntry', 'WGPUBlendComponent', - 'WGPUBlendFactor', 'WGPUBlendFactor_Constant', - 'WGPUBlendFactor_Dst', 'WGPUBlendFactor_DstAlpha', - 'WGPUBlendFactor_Force32', 'WGPUBlendFactor_One', - 'WGPUBlendFactor_OneMinusConstant', 'WGPUBlendFactor_OneMinusDst', - 'WGPUBlendFactor_OneMinusDstAlpha', 'WGPUBlendFactor_OneMinusSrc', - 'WGPUBlendFactor_OneMinusSrc1', - 'WGPUBlendFactor_OneMinusSrc1Alpha', - 'WGPUBlendFactor_OneMinusSrcAlpha', 'WGPUBlendFactor_Src', - 'WGPUBlendFactor_Src1', 'WGPUBlendFactor_Src1Alpha', - 'WGPUBlendFactor_SrcAlpha', 'WGPUBlendFactor_SrcAlphaSaturated', - 'WGPUBlendFactor_Undefined', 'WGPUBlendFactor_Zero', - 'WGPUBlendOperation', 'WGPUBlendOperation_Add', - 'WGPUBlendOperation_Force32', 'WGPUBlendOperation_Max', - 'WGPUBlendOperation_Min', 'WGPUBlendOperation_ReverseSubtract', - 'WGPUBlendOperation_Subtract', 'WGPUBlendOperation_Undefined', - 'WGPUBlendState', 'WGPUBool', 'WGPUBuffer', - 'WGPUBufferBindingLayout', 'WGPUBufferBindingType', - 'WGPUBufferBindingType_BindingNotUsed', - 'WGPUBufferBindingType_Force32', - 'WGPUBufferBindingType_ReadOnlyStorage', - 'WGPUBufferBindingType_Storage', 'WGPUBufferBindingType_Uniform', - 'WGPUBufferDescriptor', 'WGPUBufferHostMappedPointer', - 'WGPUBufferMapAsyncStatus', - 'WGPUBufferMapAsyncStatus_DestroyedBeforeCallback', - 'WGPUBufferMapAsyncStatus_DeviceLost', - 'WGPUBufferMapAsyncStatus_Force32', - 'WGPUBufferMapAsyncStatus_InstanceDropped', - 'WGPUBufferMapAsyncStatus_MappingAlreadyPending', - 'WGPUBufferMapAsyncStatus_OffsetOutOfRange', - 'WGPUBufferMapAsyncStatus_SizeOutOfRange', - 'WGPUBufferMapAsyncStatus_Success', - 'WGPUBufferMapAsyncStatus_Unknown', - 'WGPUBufferMapAsyncStatus_UnmappedBeforeCallback', - 'WGPUBufferMapAsyncStatus_ValidationError', - 'WGPUBufferMapCallback', 'WGPUBufferMapCallback2', - 'WGPUBufferMapCallbackInfo', 'WGPUBufferMapCallbackInfo2', - 'WGPUBufferMapState', 'WGPUBufferMapState_Force32', - 'WGPUBufferMapState_Mapped', 'WGPUBufferMapState_Pending', - 'WGPUBufferMapState_Unmapped', 'WGPUBufferUsage', - 'WGPUBufferUsage_CopyDst', 'WGPUBufferUsage_CopySrc', - 'WGPUBufferUsage_Index', 'WGPUBufferUsage_Indirect', - 'WGPUBufferUsage_MapRead', 'WGPUBufferUsage_MapWrite', - 'WGPUBufferUsage_None', 'WGPUBufferUsage_QueryResolve', - 'WGPUBufferUsage_Storage', 'WGPUBufferUsage_Uniform', - 'WGPUBufferUsage_Vertex', 'WGPUCallback', 'WGPUCallbackMode', - 'WGPUCallbackMode_AllowProcessEvents', - 'WGPUCallbackMode_AllowSpontaneous', 'WGPUCallbackMode_Force32', - 'WGPUCallbackMode_WaitAnyOnly', 'WGPUChainedStruct', - 'WGPUChainedStructOut', 'WGPUColor', 'WGPUColorTargetState', - 'WGPUColorTargetStateExpandResolveTextureDawn', - 'WGPUColorWriteMask', 'WGPUColorWriteMask_All', - 'WGPUColorWriteMask_Alpha', 'WGPUColorWriteMask_Blue', - 'WGPUColorWriteMask_Green', 'WGPUColorWriteMask_None', - 'WGPUColorWriteMask_Red', 'WGPUCommandBuffer', - 'WGPUCommandBufferDescriptor', 'WGPUCommandEncoder', - 'WGPUCommandEncoderDescriptor', 'WGPUCompareFunction', - 'WGPUCompareFunction_Always', 'WGPUCompareFunction_Equal', - 'WGPUCompareFunction_Force32', 'WGPUCompareFunction_Greater', - 'WGPUCompareFunction_GreaterEqual', 'WGPUCompareFunction_Less', - 'WGPUCompareFunction_LessEqual', 'WGPUCompareFunction_Never', - 'WGPUCompareFunction_NotEqual', 'WGPUCompareFunction_Undefined', - 'WGPUCompilationInfo', 'WGPUCompilationInfoCallback', - 'WGPUCompilationInfoCallback2', 'WGPUCompilationInfoCallbackInfo', - 'WGPUCompilationInfoCallbackInfo2', - 'WGPUCompilationInfoRequestStatus', - 'WGPUCompilationInfoRequestStatus_DeviceLost', - 'WGPUCompilationInfoRequestStatus_Error', - 'WGPUCompilationInfoRequestStatus_Force32', - 'WGPUCompilationInfoRequestStatus_InstanceDropped', - 'WGPUCompilationInfoRequestStatus_Success', - 'WGPUCompilationInfoRequestStatus_Unknown', - 'WGPUCompilationMessage', 'WGPUCompilationMessageType', - 'WGPUCompilationMessageType_Error', - 'WGPUCompilationMessageType_Force32', - 'WGPUCompilationMessageType_Info', - 'WGPUCompilationMessageType_Warning', 'WGPUCompositeAlphaMode', - 'WGPUCompositeAlphaMode_Auto', 'WGPUCompositeAlphaMode_Force32', - 'WGPUCompositeAlphaMode_Inherit', 'WGPUCompositeAlphaMode_Opaque', - 'WGPUCompositeAlphaMode_Premultiplied', - 'WGPUCompositeAlphaMode_Unpremultiplied', - 'WGPUComputePassDescriptor', 'WGPUComputePassEncoder', - 'WGPUComputePassTimestampWrites', 'WGPUComputePipeline', - 'WGPUComputePipelineDescriptor', 'WGPUComputeState', - 'WGPUConstantEntry', 'WGPUCopyTextureForBrowserOptions', - 'WGPUCreateComputePipelineAsyncCallback', - 'WGPUCreateComputePipelineAsyncCallback2', - 'WGPUCreateComputePipelineAsyncCallbackInfo', - 'WGPUCreateComputePipelineAsyncCallbackInfo2', - 'WGPUCreatePipelineAsyncStatus', - 'WGPUCreatePipelineAsyncStatus_DeviceDestroyed', - 'WGPUCreatePipelineAsyncStatus_DeviceLost', - 'WGPUCreatePipelineAsyncStatus_Force32', - 'WGPUCreatePipelineAsyncStatus_InstanceDropped', - 'WGPUCreatePipelineAsyncStatus_InternalError', - 'WGPUCreatePipelineAsyncStatus_Success', - 'WGPUCreatePipelineAsyncStatus_Unknown', - 'WGPUCreatePipelineAsyncStatus_ValidationError', - 'WGPUCreateRenderPipelineAsyncCallback', - 'WGPUCreateRenderPipelineAsyncCallback2', - 'WGPUCreateRenderPipelineAsyncCallbackInfo', - 'WGPUCreateRenderPipelineAsyncCallbackInfo2', 'WGPUCullMode', - 'WGPUCullMode_Back', 'WGPUCullMode_Force32', 'WGPUCullMode_Front', - 'WGPUCullMode_None', 'WGPUCullMode_Undefined', - 'WGPUDawnAdapterPropertiesPowerPreference', - 'WGPUDawnBufferDescriptorErrorInfoFromWireClient', - 'WGPUDawnCacheDeviceDescriptor', - 'WGPUDawnEncoderInternalUsageDescriptor', - 'WGPUDawnExperimentalImmediateDataLimits', - 'WGPUDawnExperimentalSubgroupLimits', - 'WGPUDawnLoadCacheDataFunction', - 'WGPUDawnRenderPassColorAttachmentRenderToSingleSampled', - 'WGPUDawnShaderModuleSPIRVOptionsDescriptor', - 'WGPUDawnStoreCacheDataFunction', - 'WGPUDawnTexelCopyBufferRowAlignmentLimits', - 'WGPUDawnTextureInternalUsageDescriptor', - 'WGPUDawnTogglesDescriptor', 'WGPUDawnWGSLBlocklist', - 'WGPUDawnWireWGSLControl', 'WGPUDepthStencilState', 'WGPUDevice', - 'WGPUDeviceDescriptor', 'WGPUDeviceLostCallback', - 'WGPUDeviceLostCallback2', 'WGPUDeviceLostCallbackInfo', - 'WGPUDeviceLostCallbackInfo2', 'WGPUDeviceLostCallbackNew', - 'WGPUDeviceLostReason', 'WGPUDeviceLostReason_Destroyed', - 'WGPUDeviceLostReason_FailedCreation', - 'WGPUDeviceLostReason_Force32', - 'WGPUDeviceLostReason_InstanceDropped', - 'WGPUDeviceLostReason_Unknown', 'WGPUDrmFormatCapabilities', - 'WGPUDrmFormatProperties', 'WGPUErrorCallback', 'WGPUErrorFilter', - 'WGPUErrorFilter_Force32', 'WGPUErrorFilter_Internal', - 'WGPUErrorFilter_OutOfMemory', 'WGPUErrorFilter_Validation', - 'WGPUErrorType', 'WGPUErrorType_DeviceLost', - 'WGPUErrorType_Force32', 'WGPUErrorType_Internal', - 'WGPUErrorType_NoError', 'WGPUErrorType_OutOfMemory', - 'WGPUErrorType_Unknown', 'WGPUErrorType_Validation', - 'WGPUExtent2D', 'WGPUExtent3D', 'WGPUExternalTexture', - 'WGPUExternalTextureBindingEntry', - 'WGPUExternalTextureBindingLayout', - 'WGPUExternalTextureDescriptor', 'WGPUExternalTextureRotation', - 'WGPUExternalTextureRotation_Force32', - 'WGPUExternalTextureRotation_Rotate0Degrees', - 'WGPUExternalTextureRotation_Rotate180Degrees', - 'WGPUExternalTextureRotation_Rotate270Degrees', - 'WGPUExternalTextureRotation_Rotate90Degrees', 'WGPUFeatureLevel', - 'WGPUFeatureLevel_Compatibility', 'WGPUFeatureLevel_Core', - 'WGPUFeatureLevel_Force32', 'WGPUFeatureLevel_Undefined', - 'WGPUFeatureName', 'WGPUFeatureName_ANGLETextureSharing', - 'WGPUFeatureName_AdapterPropertiesD3D', - 'WGPUFeatureName_AdapterPropertiesMemoryHeaps', - 'WGPUFeatureName_AdapterPropertiesVk', - 'WGPUFeatureName_BGRA8UnormStorage', - 'WGPUFeatureName_BufferMapExtendedUsages', - 'WGPUFeatureName_ChromiumExperimentalImmediateData', - 'WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses', - 'WGPUFeatureName_ClipDistances', - 'WGPUFeatureName_D3D11MultithreadProtected', - 'WGPUFeatureName_DawnInternalUsages', - 'WGPUFeatureName_DawnLoadResolveTexture', - 'WGPUFeatureName_DawnMultiPlanarFormats', - 'WGPUFeatureName_DawnNative', - 'WGPUFeatureName_DawnPartialLoadResolveTexture', - 'WGPUFeatureName_DawnTexelCopyBufferRowAlignment', - 'WGPUFeatureName_Depth32FloatStencil8', - 'WGPUFeatureName_DepthClipControl', - 'WGPUFeatureName_DrmFormatCapabilities', - 'WGPUFeatureName_DualSourceBlending', - 'WGPUFeatureName_FlexibleTextureViews', - 'WGPUFeatureName_Float32Blendable', - 'WGPUFeatureName_Float32Filterable', 'WGPUFeatureName_Force32', - 'WGPUFeatureName_FormatCapabilities', - 'WGPUFeatureName_FramebufferFetch', - 'WGPUFeatureName_HostMappedPointer', - 'WGPUFeatureName_ImplicitDeviceSynchronization', - 'WGPUFeatureName_IndirectFirstInstance', - 'WGPUFeatureName_MSAARenderToSingleSampled', - 'WGPUFeatureName_MultiDrawIndirect', - 'WGPUFeatureName_MultiPlanarFormatExtendedUsages', - 'WGPUFeatureName_MultiPlanarFormatNv12a', - 'WGPUFeatureName_MultiPlanarFormatNv16', - 'WGPUFeatureName_MultiPlanarFormatNv24', - 'WGPUFeatureName_MultiPlanarFormatP010', - 'WGPUFeatureName_MultiPlanarFormatP210', - 'WGPUFeatureName_MultiPlanarFormatP410', - 'WGPUFeatureName_MultiPlanarRenderTargets', - 'WGPUFeatureName_Norm16TextureFormats', - 'WGPUFeatureName_PixelLocalStorageCoherent', - 'WGPUFeatureName_PixelLocalStorageNonCoherent', - 'WGPUFeatureName_R8UnormStorage', - 'WGPUFeatureName_RG11B10UfloatRenderable', - 'WGPUFeatureName_ShaderF16', - 'WGPUFeatureName_ShaderModuleCompilationOptions', - 'WGPUFeatureName_SharedBufferMemoryD3D12Resource', - 'WGPUFeatureName_SharedFenceDXGISharedHandle', - 'WGPUFeatureName_SharedFenceMTLSharedEvent', - 'WGPUFeatureName_SharedFenceSyncFD', - 'WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD', - 'WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle', - 'WGPUFeatureName_SharedTextureMemoryAHardwareBuffer', - 'WGPUFeatureName_SharedTextureMemoryD3D11Texture2D', - 'WGPUFeatureName_SharedTextureMemoryDXGISharedHandle', - 'WGPUFeatureName_SharedTextureMemoryDmaBuf', - 'WGPUFeatureName_SharedTextureMemoryEGLImage', - 'WGPUFeatureName_SharedTextureMemoryIOSurface', - 'WGPUFeatureName_SharedTextureMemoryOpaqueFD', - 'WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation', - 'WGPUFeatureName_SharedTextureMemoryZirconHandle', - 'WGPUFeatureName_Snorm16TextureFormats', - 'WGPUFeatureName_StaticSamplers', 'WGPUFeatureName_Subgroups', - 'WGPUFeatureName_SubgroupsF16', - 'WGPUFeatureName_TextureCompressionASTC', - 'WGPUFeatureName_TextureCompressionBC', - 'WGPUFeatureName_TextureCompressionETC2', - 'WGPUFeatureName_TimestampQuery', - 'WGPUFeatureName_TransientAttachments', - 'WGPUFeatureName_Unorm16TextureFormats', - 'WGPUFeatureName_YCbCrVulkanSamplers', 'WGPUFilterMode', - 'WGPUFilterMode_Force32', 'WGPUFilterMode_Linear', - 'WGPUFilterMode_Nearest', 'WGPUFilterMode_Undefined', 'WGPUFlags', - 'WGPUFormatCapabilities', 'WGPUFragmentState', 'WGPUFrontFace', - 'WGPUFrontFace_CCW', 'WGPUFrontFace_CW', 'WGPUFrontFace_Force32', - 'WGPUFrontFace_Undefined', 'WGPUFuture', 'WGPUFutureWaitInfo', - 'WGPUHeapProperty', 'WGPUHeapProperty_DeviceLocal', - 'WGPUHeapProperty_HostCached', 'WGPUHeapProperty_HostCoherent', - 'WGPUHeapProperty_HostUncached', 'WGPUHeapProperty_HostVisible', - 'WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER', 'WGPUImageCopyBuffer', - 'WGPUImageCopyExternalTexture', 'WGPUImageCopyTexture', - 'WGPUIndexFormat', 'WGPUIndexFormat_Force32', - 'WGPUIndexFormat_Uint16', 'WGPUIndexFormat_Uint32', - 'WGPUIndexFormat_Undefined', 'WGPUInstance', - 'WGPUInstanceDescriptor', 'WGPUInstanceFeatures', 'WGPULimits', - 'WGPULoadOp', 'WGPULoadOp_Clear', - 'WGPULoadOp_ExpandResolveTexture', 'WGPULoadOp_Force32', - 'WGPULoadOp_Load', 'WGPULoadOp_Undefined', 'WGPULoggingCallback', - 'WGPULoggingType', 'WGPULoggingType_Error', - 'WGPULoggingType_Force32', 'WGPULoggingType_Info', - 'WGPULoggingType_Verbose', 'WGPULoggingType_Warning', - 'WGPUMapAsyncStatus', 'WGPUMapAsyncStatus_Aborted', - 'WGPUMapAsyncStatus_Error', 'WGPUMapAsyncStatus_Force32', - 'WGPUMapAsyncStatus_InstanceDropped', - 'WGPUMapAsyncStatus_Success', 'WGPUMapAsyncStatus_Unknown', - 'WGPUMapMode', 'WGPUMapMode_None', 'WGPUMapMode_Read', - 'WGPUMapMode_Write', 'WGPUMemoryHeapInfo', 'WGPUMipmapFilterMode', - 'WGPUMipmapFilterMode_Force32', 'WGPUMipmapFilterMode_Linear', - 'WGPUMipmapFilterMode_Nearest', 'WGPUMipmapFilterMode_Undefined', - 'WGPUMultisampleState', 'WGPUOptionalBool', - 'WGPUOptionalBool_False', 'WGPUOptionalBool_Force32', - 'WGPUOptionalBool_True', 'WGPUOptionalBool_Undefined', - 'WGPUOrigin2D', 'WGPUOrigin3D', 'WGPUPipelineLayout', - 'WGPUPipelineLayoutDescriptor', - 'WGPUPipelineLayoutPixelLocalStorage', - 'WGPUPipelineLayoutStorageAttachment', - 'WGPUPopErrorScopeCallback', 'WGPUPopErrorScopeCallback2', - 'WGPUPopErrorScopeCallbackInfo', 'WGPUPopErrorScopeCallbackInfo2', - 'WGPUPopErrorScopeStatus', 'WGPUPopErrorScopeStatus_Force32', - 'WGPUPopErrorScopeStatus_InstanceDropped', - 'WGPUPopErrorScopeStatus_Success', 'WGPUPowerPreference', - 'WGPUPowerPreference_Force32', - 'WGPUPowerPreference_HighPerformance', - 'WGPUPowerPreference_LowPower', 'WGPUPowerPreference_Undefined', - 'WGPUPresentMode', 'WGPUPresentMode_Fifo', - 'WGPUPresentMode_FifoRelaxed', 'WGPUPresentMode_Force32', - 'WGPUPresentMode_Immediate', 'WGPUPresentMode_Mailbox', - 'WGPUPrimitiveState', 'WGPUPrimitiveTopology', - 'WGPUPrimitiveTopology_Force32', 'WGPUPrimitiveTopology_LineList', - 'WGPUPrimitiveTopology_LineStrip', - 'WGPUPrimitiveTopology_PointList', - 'WGPUPrimitiveTopology_TriangleList', - 'WGPUPrimitiveTopology_TriangleStrip', - 'WGPUPrimitiveTopology_Undefined', 'WGPUProc', - 'WGPUProcAdapterAddRef', 'WGPUProcAdapterCreateDevice', - 'WGPUProcAdapterGetFeatures', - 'WGPUProcAdapterGetFormatCapabilities', 'WGPUProcAdapterGetInfo', - 'WGPUProcAdapterGetInstance', 'WGPUProcAdapterGetLimits', - 'WGPUProcAdapterHasFeature', 'WGPUProcAdapterInfoFreeMembers', - 'WGPUProcAdapterPropertiesMemoryHeapsFreeMembers', - 'WGPUProcAdapterRelease', 'WGPUProcAdapterRequestDevice', - 'WGPUProcAdapterRequestDevice2', 'WGPUProcAdapterRequestDeviceF', - 'WGPUProcBindGroupAddRef', 'WGPUProcBindGroupLayoutAddRef', - 'WGPUProcBindGroupLayoutRelease', - 'WGPUProcBindGroupLayoutSetLabel', 'WGPUProcBindGroupRelease', - 'WGPUProcBindGroupSetLabel', 'WGPUProcBufferAddRef', - 'WGPUProcBufferDestroy', 'WGPUProcBufferGetConstMappedRange', - 'WGPUProcBufferGetMapState', 'WGPUProcBufferGetMappedRange', - 'WGPUProcBufferGetSize', 'WGPUProcBufferGetUsage', - 'WGPUProcBufferMapAsync', 'WGPUProcBufferMapAsync2', - 'WGPUProcBufferMapAsyncF', 'WGPUProcBufferRelease', - 'WGPUProcBufferSetLabel', 'WGPUProcBufferUnmap', - 'WGPUProcCommandBufferAddRef', 'WGPUProcCommandBufferRelease', - 'WGPUProcCommandBufferSetLabel', 'WGPUProcCommandEncoderAddRef', - 'WGPUProcCommandEncoderBeginComputePass', - 'WGPUProcCommandEncoderBeginRenderPass', - 'WGPUProcCommandEncoderClearBuffer', - 'WGPUProcCommandEncoderCopyBufferToBuffer', - 'WGPUProcCommandEncoderCopyBufferToTexture', - 'WGPUProcCommandEncoderCopyTextureToBuffer', - 'WGPUProcCommandEncoderCopyTextureToTexture', - 'WGPUProcCommandEncoderFinish', - 'WGPUProcCommandEncoderInjectValidationError', - 'WGPUProcCommandEncoderInsertDebugMarker', - 'WGPUProcCommandEncoderPopDebugGroup', - 'WGPUProcCommandEncoderPushDebugGroup', - 'WGPUProcCommandEncoderRelease', - 'WGPUProcCommandEncoderResolveQuerySet', - 'WGPUProcCommandEncoderSetLabel', - 'WGPUProcCommandEncoderWriteBuffer', - 'WGPUProcCommandEncoderWriteTimestamp', - 'WGPUProcComputePassEncoderAddRef', - 'WGPUProcComputePassEncoderDispatchWorkgroups', - 'WGPUProcComputePassEncoderDispatchWorkgroupsIndirect', - 'WGPUProcComputePassEncoderEnd', - 'WGPUProcComputePassEncoderInsertDebugMarker', - 'WGPUProcComputePassEncoderPopDebugGroup', - 'WGPUProcComputePassEncoderPushDebugGroup', - 'WGPUProcComputePassEncoderRelease', - 'WGPUProcComputePassEncoderSetBindGroup', - 'WGPUProcComputePassEncoderSetLabel', - 'WGPUProcComputePassEncoderSetPipeline', - 'WGPUProcComputePassEncoderWriteTimestamp', - 'WGPUProcComputePipelineAddRef', - 'WGPUProcComputePipelineGetBindGroupLayout', - 'WGPUProcComputePipelineRelease', - 'WGPUProcComputePipelineSetLabel', 'WGPUProcCreateInstance', - 'WGPUProcDeviceAddRef', 'WGPUProcDeviceCreateBindGroup', - 'WGPUProcDeviceCreateBindGroupLayout', - 'WGPUProcDeviceCreateBuffer', - 'WGPUProcDeviceCreateCommandEncoder', - 'WGPUProcDeviceCreateComputePipeline', - 'WGPUProcDeviceCreateComputePipelineAsync', - 'WGPUProcDeviceCreateComputePipelineAsync2', - 'WGPUProcDeviceCreateComputePipelineAsyncF', - 'WGPUProcDeviceCreateErrorBuffer', - 'WGPUProcDeviceCreateErrorExternalTexture', - 'WGPUProcDeviceCreateErrorShaderModule', - 'WGPUProcDeviceCreateErrorTexture', - 'WGPUProcDeviceCreateExternalTexture', - 'WGPUProcDeviceCreatePipelineLayout', - 'WGPUProcDeviceCreateQuerySet', - 'WGPUProcDeviceCreateRenderBundleEncoder', - 'WGPUProcDeviceCreateRenderPipeline', - 'WGPUProcDeviceCreateRenderPipelineAsync', - 'WGPUProcDeviceCreateRenderPipelineAsync2', - 'WGPUProcDeviceCreateRenderPipelineAsyncF', - 'WGPUProcDeviceCreateSampler', 'WGPUProcDeviceCreateShaderModule', - 'WGPUProcDeviceCreateTexture', 'WGPUProcDeviceDestroy', - 'WGPUProcDeviceForceLoss', - 'WGPUProcDeviceGetAHardwareBufferProperties', - 'WGPUProcDeviceGetAdapter', 'WGPUProcDeviceGetAdapterInfo', - 'WGPUProcDeviceGetFeatures', 'WGPUProcDeviceGetLimits', - 'WGPUProcDeviceGetLostFuture', 'WGPUProcDeviceGetQueue', - 'WGPUProcDeviceHasFeature', - 'WGPUProcDeviceImportSharedBufferMemory', - 'WGPUProcDeviceImportSharedFence', - 'WGPUProcDeviceImportSharedTextureMemory', - 'WGPUProcDeviceInjectError', 'WGPUProcDevicePopErrorScope', - 'WGPUProcDevicePopErrorScope2', 'WGPUProcDevicePopErrorScopeF', - 'WGPUProcDevicePushErrorScope', 'WGPUProcDeviceRelease', - 'WGPUProcDeviceSetLabel', 'WGPUProcDeviceSetLoggingCallback', - 'WGPUProcDeviceTick', 'WGPUProcDeviceValidateTextureDescriptor', - 'WGPUProcDrmFormatCapabilitiesFreeMembers', - 'WGPUProcExternalTextureAddRef', 'WGPUProcExternalTextureDestroy', - 'WGPUProcExternalTextureExpire', 'WGPUProcExternalTextureRefresh', - 'WGPUProcExternalTextureRelease', - 'WGPUProcExternalTextureSetLabel', 'WGPUProcGetInstanceFeatures', - 'WGPUProcGetProcAddress', 'WGPUProcInstanceAddRef', - 'WGPUProcInstanceCreateSurface', - 'WGPUProcInstanceEnumerateWGSLLanguageFeatures', - 'WGPUProcInstanceHasWGSLLanguageFeature', - 'WGPUProcInstanceProcessEvents', 'WGPUProcInstanceRelease', - 'WGPUProcInstanceRequestAdapter', - 'WGPUProcInstanceRequestAdapter2', - 'WGPUProcInstanceRequestAdapterF', 'WGPUProcInstanceWaitAny', - 'WGPUProcPipelineLayoutAddRef', 'WGPUProcPipelineLayoutRelease', - 'WGPUProcPipelineLayoutSetLabel', 'WGPUProcQuerySetAddRef', - 'WGPUProcQuerySetDestroy', 'WGPUProcQuerySetGetCount', - 'WGPUProcQuerySetGetType', 'WGPUProcQuerySetRelease', - 'WGPUProcQuerySetSetLabel', 'WGPUProcQueueAddRef', - 'WGPUProcQueueCopyExternalTextureForBrowser', - 'WGPUProcQueueCopyTextureForBrowser', - 'WGPUProcQueueOnSubmittedWorkDone', - 'WGPUProcQueueOnSubmittedWorkDone2', - 'WGPUProcQueueOnSubmittedWorkDoneF', 'WGPUProcQueueRelease', - 'WGPUProcQueueSetLabel', 'WGPUProcQueueSubmit', - 'WGPUProcQueueWriteBuffer', 'WGPUProcQueueWriteTexture', - 'WGPUProcRenderBundleAddRef', 'WGPUProcRenderBundleEncoderAddRef', - 'WGPUProcRenderBundleEncoderDraw', - 'WGPUProcRenderBundleEncoderDrawIndexed', - 'WGPUProcRenderBundleEncoderDrawIndexedIndirect', - 'WGPUProcRenderBundleEncoderDrawIndirect', - 'WGPUProcRenderBundleEncoderFinish', - 'WGPUProcRenderBundleEncoderInsertDebugMarker', - 'WGPUProcRenderBundleEncoderPopDebugGroup', - 'WGPUProcRenderBundleEncoderPushDebugGroup', - 'WGPUProcRenderBundleEncoderRelease', - 'WGPUProcRenderBundleEncoderSetBindGroup', - 'WGPUProcRenderBundleEncoderSetIndexBuffer', - 'WGPUProcRenderBundleEncoderSetLabel', - 'WGPUProcRenderBundleEncoderSetPipeline', - 'WGPUProcRenderBundleEncoderSetVertexBuffer', - 'WGPUProcRenderBundleRelease', 'WGPUProcRenderBundleSetLabel', - 'WGPUProcRenderPassEncoderAddRef', - 'WGPUProcRenderPassEncoderBeginOcclusionQuery', - 'WGPUProcRenderPassEncoderDraw', - 'WGPUProcRenderPassEncoderDrawIndexed', - 'WGPUProcRenderPassEncoderDrawIndexedIndirect', - 'WGPUProcRenderPassEncoderDrawIndirect', - 'WGPUProcRenderPassEncoderEnd', - 'WGPUProcRenderPassEncoderEndOcclusionQuery', - 'WGPUProcRenderPassEncoderExecuteBundles', - 'WGPUProcRenderPassEncoderInsertDebugMarker', - 'WGPUProcRenderPassEncoderMultiDrawIndexedIndirect', - 'WGPUProcRenderPassEncoderMultiDrawIndirect', - 'WGPUProcRenderPassEncoderPixelLocalStorageBarrier', - 'WGPUProcRenderPassEncoderPopDebugGroup', - 'WGPUProcRenderPassEncoderPushDebugGroup', - 'WGPUProcRenderPassEncoderRelease', - 'WGPUProcRenderPassEncoderSetBindGroup', - 'WGPUProcRenderPassEncoderSetBlendConstant', - 'WGPUProcRenderPassEncoderSetIndexBuffer', - 'WGPUProcRenderPassEncoderSetLabel', - 'WGPUProcRenderPassEncoderSetPipeline', - 'WGPUProcRenderPassEncoderSetScissorRect', - 'WGPUProcRenderPassEncoderSetStencilReference', - 'WGPUProcRenderPassEncoderSetVertexBuffer', - 'WGPUProcRenderPassEncoderSetViewport', - 'WGPUProcRenderPassEncoderWriteTimestamp', - 'WGPUProcRenderPipelineAddRef', - 'WGPUProcRenderPipelineGetBindGroupLayout', - 'WGPUProcRenderPipelineRelease', 'WGPUProcRenderPipelineSetLabel', - 'WGPUProcSamplerAddRef', 'WGPUProcSamplerRelease', - 'WGPUProcSamplerSetLabel', 'WGPUProcShaderModuleAddRef', - 'WGPUProcShaderModuleGetCompilationInfo', - 'WGPUProcShaderModuleGetCompilationInfo2', - 'WGPUProcShaderModuleGetCompilationInfoF', - 'WGPUProcShaderModuleRelease', 'WGPUProcShaderModuleSetLabel', - 'WGPUProcSharedBufferMemoryAddRef', - 'WGPUProcSharedBufferMemoryBeginAccess', - 'WGPUProcSharedBufferMemoryCreateBuffer', - 'WGPUProcSharedBufferMemoryEndAccess', - 'WGPUProcSharedBufferMemoryEndAccessStateFreeMembers', - 'WGPUProcSharedBufferMemoryGetProperties', - 'WGPUProcSharedBufferMemoryIsDeviceLost', - 'WGPUProcSharedBufferMemoryRelease', - 'WGPUProcSharedBufferMemorySetLabel', 'WGPUProcSharedFenceAddRef', - 'WGPUProcSharedFenceExportInfo', 'WGPUProcSharedFenceRelease', - 'WGPUProcSharedTextureMemoryAddRef', - 'WGPUProcSharedTextureMemoryBeginAccess', - 'WGPUProcSharedTextureMemoryCreateTexture', - 'WGPUProcSharedTextureMemoryEndAccess', - 'WGPUProcSharedTextureMemoryEndAccessStateFreeMembers', - 'WGPUProcSharedTextureMemoryGetProperties', - 'WGPUProcSharedTextureMemoryIsDeviceLost', - 'WGPUProcSharedTextureMemoryRelease', - 'WGPUProcSharedTextureMemorySetLabel', - 'WGPUProcSupportedFeaturesFreeMembers', 'WGPUProcSurfaceAddRef', - 'WGPUProcSurfaceCapabilitiesFreeMembers', - 'WGPUProcSurfaceConfigure', 'WGPUProcSurfaceGetCapabilities', - 'WGPUProcSurfaceGetCurrentTexture', 'WGPUProcSurfacePresent', - 'WGPUProcSurfaceRelease', 'WGPUProcSurfaceSetLabel', - 'WGPUProcSurfaceUnconfigure', 'WGPUProcTextureAddRef', - 'WGPUProcTextureCreateErrorView', 'WGPUProcTextureCreateView', - 'WGPUProcTextureDestroy', 'WGPUProcTextureGetDepthOrArrayLayers', - 'WGPUProcTextureGetDimension', 'WGPUProcTextureGetFormat', - 'WGPUProcTextureGetHeight', 'WGPUProcTextureGetMipLevelCount', - 'WGPUProcTextureGetSampleCount', 'WGPUProcTextureGetUsage', - 'WGPUProcTextureGetWidth', 'WGPUProcTextureRelease', - 'WGPUProcTextureSetLabel', 'WGPUProcTextureViewAddRef', - 'WGPUProcTextureViewRelease', 'WGPUProcTextureViewSetLabel', - 'WGPUQuerySet', 'WGPUQuerySetDescriptor', 'WGPUQueryType', - 'WGPUQueryType_Force32', 'WGPUQueryType_Occlusion', - 'WGPUQueryType_Timestamp', 'WGPUQueue', 'WGPUQueueDescriptor', - 'WGPUQueueWorkDoneCallback', 'WGPUQueueWorkDoneCallback2', - 'WGPUQueueWorkDoneCallbackInfo', 'WGPUQueueWorkDoneCallbackInfo2', - 'WGPUQueueWorkDoneStatus', 'WGPUQueueWorkDoneStatus_DeviceLost', - 'WGPUQueueWorkDoneStatus_Error', - 'WGPUQueueWorkDoneStatus_Force32', - 'WGPUQueueWorkDoneStatus_InstanceDropped', - 'WGPUQueueWorkDoneStatus_Success', - 'WGPUQueueWorkDoneStatus_Unknown', 'WGPURenderBundle', - 'WGPURenderBundleDescriptor', 'WGPURenderBundleEncoder', - 'WGPURenderBundleEncoderDescriptor', - 'WGPURenderPassColorAttachment', - 'WGPURenderPassDepthStencilAttachment', - 'WGPURenderPassDescriptor', - 'WGPURenderPassDescriptorExpandResolveRect', - 'WGPURenderPassDescriptorMaxDrawCount', 'WGPURenderPassEncoder', - 'WGPURenderPassMaxDrawCount', 'WGPURenderPassPixelLocalStorage', - 'WGPURenderPassStorageAttachment', - 'WGPURenderPassTimestampWrites', 'WGPURenderPipeline', - 'WGPURenderPipelineDescriptor', 'WGPURequestAdapterCallback', - 'WGPURequestAdapterCallback2', 'WGPURequestAdapterCallbackInfo', - 'WGPURequestAdapterCallbackInfo2', 'WGPURequestAdapterOptions', - 'WGPURequestAdapterStatus', 'WGPURequestAdapterStatus_Error', - 'WGPURequestAdapterStatus_Force32', - 'WGPURequestAdapterStatus_InstanceDropped', - 'WGPURequestAdapterStatus_Success', - 'WGPURequestAdapterStatus_Unavailable', - 'WGPURequestAdapterStatus_Unknown', 'WGPURequestDeviceCallback', - 'WGPURequestDeviceCallback2', 'WGPURequestDeviceCallbackInfo', - 'WGPURequestDeviceCallbackInfo2', 'WGPURequestDeviceStatus', - 'WGPURequestDeviceStatus_Error', - 'WGPURequestDeviceStatus_Force32', - 'WGPURequestDeviceStatus_InstanceDropped', - 'WGPURequestDeviceStatus_Success', - 'WGPURequestDeviceStatus_Unknown', 'WGPURequiredLimits', - 'WGPUSType', 'WGPUSType_AHardwareBufferProperties', - 'WGPUSType_AdapterPropertiesD3D', - 'WGPUSType_AdapterPropertiesMemoryHeaps', - 'WGPUSType_AdapterPropertiesSubgroups', - 'WGPUSType_AdapterPropertiesVk', - 'WGPUSType_BufferHostMappedPointer', - 'WGPUSType_ColorTargetStateExpandResolveTextureDawn', - 'WGPUSType_DawnAdapterPropertiesPowerPreference', - 'WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient', - 'WGPUSType_DawnCacheDeviceDescriptor', - 'WGPUSType_DawnEncoderInternalUsageDescriptor', - 'WGPUSType_DawnExperimentalImmediateDataLimits', - 'WGPUSType_DawnExperimentalSubgroupLimits', - 'WGPUSType_DawnInstanceDescriptor', - 'WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled', - 'WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor', - 'WGPUSType_DawnTexelCopyBufferRowAlignmentLimits', - 'WGPUSType_DawnTextureInternalUsageDescriptor', - 'WGPUSType_DawnTogglesDescriptor', 'WGPUSType_DawnWGSLBlocklist', - 'WGPUSType_DawnWireWGSLControl', - 'WGPUSType_DrmFormatCapabilities', - 'WGPUSType_ExternalTextureBindingEntry', - 'WGPUSType_ExternalTextureBindingLayout', 'WGPUSType_Force32', - 'WGPUSType_PipelineLayoutPixelLocalStorage', - 'WGPUSType_RenderPassDescriptorExpandResolveRect', - 'WGPUSType_RenderPassMaxDrawCount', - 'WGPUSType_RenderPassPixelLocalStorage', - 'WGPUSType_RequestAdapterOptionsD3D11Device', - 'WGPUSType_RequestAdapterOptionsGetGLProc', - 'WGPUSType_RequestAdapterOptionsLUID', - 'WGPUSType_ShaderModuleCompilationOptions', - 'WGPUSType_ShaderSourceSPIRV', 'WGPUSType_ShaderSourceWGSL', - 'WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor', - 'WGPUSType_SharedFenceDXGISharedHandleDescriptor', - 'WGPUSType_SharedFenceDXGISharedHandleExportInfo', - 'WGPUSType_SharedFenceMTLSharedEventDescriptor', - 'WGPUSType_SharedFenceMTLSharedEventExportInfo', - 'WGPUSType_SharedFenceSyncFDDescriptor', - 'WGPUSType_SharedFenceSyncFDExportInfo', - 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor', - 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo', - 'WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor', - 'WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo', - 'WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor', - 'WGPUSType_SharedTextureMemoryAHardwareBufferProperties', - 'WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor', - 'WGPUSType_SharedTextureMemoryD3DSwapchainBeginState', - 'WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor', - 'WGPUSType_SharedTextureMemoryDmaBufDescriptor', - 'WGPUSType_SharedTextureMemoryEGLImageDescriptor', - 'WGPUSType_SharedTextureMemoryIOSurfaceDescriptor', - 'WGPUSType_SharedTextureMemoryInitializedBeginState', - 'WGPUSType_SharedTextureMemoryInitializedEndState', - 'WGPUSType_SharedTextureMemoryOpaqueFDDescriptor', - 'WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor', - 'WGPUSType_SharedTextureMemoryVkImageLayoutBeginState', - 'WGPUSType_SharedTextureMemoryVkImageLayoutEndState', - 'WGPUSType_SharedTextureMemoryZirconHandleDescriptor', - 'WGPUSType_StaticSamplerBindingLayout', - 'WGPUSType_SurfaceDescriptorFromWindowsCoreWindow', - 'WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel', - 'WGPUSType_SurfaceSourceAndroidNativeWindow', - 'WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten', - 'WGPUSType_SurfaceSourceMetalLayer', - 'WGPUSType_SurfaceSourceWaylandSurface', - 'WGPUSType_SurfaceSourceWindowsHWND', - 'WGPUSType_SurfaceSourceXCBWindow', - 'WGPUSType_SurfaceSourceXlibWindow', - 'WGPUSType_TextureBindingViewDimensionDescriptor', - 'WGPUSType_YCbCrVkDescriptor', 'WGPUSampler', - 'WGPUSamplerBindingLayout', 'WGPUSamplerBindingType', - 'WGPUSamplerBindingType_BindingNotUsed', - 'WGPUSamplerBindingType_Comparison', - 'WGPUSamplerBindingType_Filtering', - 'WGPUSamplerBindingType_Force32', - 'WGPUSamplerBindingType_NonFiltering', 'WGPUSamplerDescriptor', - 'WGPUShaderModule', 'WGPUShaderModuleCompilationOptions', - 'WGPUShaderModuleDescriptor', 'WGPUShaderModuleSPIRVDescriptor', - 'WGPUShaderModuleWGSLDescriptor', 'WGPUShaderSourceSPIRV', - 'WGPUShaderSourceWGSL', 'WGPUShaderStage', - 'WGPUShaderStage_Compute', 'WGPUShaderStage_Fragment', - 'WGPUShaderStage_None', 'WGPUShaderStage_Vertex', - 'WGPUSharedBufferMemory', - 'WGPUSharedBufferMemoryBeginAccessDescriptor', - 'WGPUSharedBufferMemoryDescriptor', - 'WGPUSharedBufferMemoryEndAccessState', - 'WGPUSharedBufferMemoryProperties', 'WGPUSharedFence', - 'WGPUSharedFenceDXGISharedHandleDescriptor', - 'WGPUSharedFenceDXGISharedHandleExportInfo', - 'WGPUSharedFenceDescriptor', 'WGPUSharedFenceExportInfo', - 'WGPUSharedFenceMTLSharedEventDescriptor', - 'WGPUSharedFenceMTLSharedEventExportInfo', - 'WGPUSharedFenceSyncFDDescriptor', - 'WGPUSharedFenceSyncFDExportInfo', 'WGPUSharedFenceType', - 'WGPUSharedFenceType_DXGISharedHandle', - 'WGPUSharedFenceType_Force32', - 'WGPUSharedFenceType_MTLSharedEvent', - 'WGPUSharedFenceType_SyncFD', - 'WGPUSharedFenceType_VkSemaphoreOpaqueFD', - 'WGPUSharedFenceType_VkSemaphoreZirconHandle', - 'WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor', - 'WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo', - 'WGPUSharedFenceVkSemaphoreZirconHandleDescriptor', - 'WGPUSharedFenceVkSemaphoreZirconHandleExportInfo', - 'WGPUSharedTextureMemory', - 'WGPUSharedTextureMemoryAHardwareBufferDescriptor', - 'WGPUSharedTextureMemoryAHardwareBufferProperties', - 'WGPUSharedTextureMemoryBeginAccessDescriptor', - 'WGPUSharedTextureMemoryD3DSwapchainBeginState', - 'WGPUSharedTextureMemoryDXGISharedHandleDescriptor', - 'WGPUSharedTextureMemoryDescriptor', - 'WGPUSharedTextureMemoryDmaBufDescriptor', - 'WGPUSharedTextureMemoryDmaBufPlane', - 'WGPUSharedTextureMemoryEGLImageDescriptor', - 'WGPUSharedTextureMemoryEndAccessState', - 'WGPUSharedTextureMemoryIOSurfaceDescriptor', - 'WGPUSharedTextureMemoryOpaqueFDDescriptor', - 'WGPUSharedTextureMemoryProperties', - 'WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor', - 'WGPUSharedTextureMemoryVkImageLayoutBeginState', - 'WGPUSharedTextureMemoryVkImageLayoutEndState', - 'WGPUSharedTextureMemoryZirconHandleDescriptor', - 'WGPUStaticSamplerBindingLayout', 'WGPUStatus', - 'WGPUStatus_Error', 'WGPUStatus_Force32', 'WGPUStatus_Success', - 'WGPUStencilFaceState', 'WGPUStencilOperation', - 'WGPUStencilOperation_DecrementClamp', - 'WGPUStencilOperation_DecrementWrap', - 'WGPUStencilOperation_Force32', - 'WGPUStencilOperation_IncrementClamp', - 'WGPUStencilOperation_IncrementWrap', - 'WGPUStencilOperation_Invert', 'WGPUStencilOperation_Keep', - 'WGPUStencilOperation_Replace', 'WGPUStencilOperation_Undefined', - 'WGPUStencilOperation_Zero', 'WGPUStorageTextureAccess', - 'WGPUStorageTextureAccess_BindingNotUsed', - 'WGPUStorageTextureAccess_Force32', - 'WGPUStorageTextureAccess_ReadOnly', - 'WGPUStorageTextureAccess_ReadWrite', - 'WGPUStorageTextureAccess_WriteOnly', - 'WGPUStorageTextureBindingLayout', 'WGPUStoreOp', - 'WGPUStoreOp_Discard', 'WGPUStoreOp_Force32', 'WGPUStoreOp_Store', - 'WGPUStoreOp_Undefined', 'WGPUStringView', - 'WGPUSupportedFeatures', 'WGPUSupportedLimits', 'WGPUSurface', - 'WGPUSurfaceCapabilities', 'WGPUSurfaceConfiguration', - 'WGPUSurfaceDescriptor', - 'WGPUSurfaceDescriptorFromAndroidNativeWindow', - 'WGPUSurfaceDescriptorFromCanvasHTMLSelector', - 'WGPUSurfaceDescriptorFromMetalLayer', - 'WGPUSurfaceDescriptorFromWaylandSurface', - 'WGPUSurfaceDescriptorFromWindowsCoreWindow', - 'WGPUSurfaceDescriptorFromWindowsHWND', - 'WGPUSurfaceDescriptorFromWindowsSwapChainPanel', - 'WGPUSurfaceDescriptorFromXcbWindow', - 'WGPUSurfaceDescriptorFromXlibWindow', - 'WGPUSurfaceGetCurrentTextureStatus', - 'WGPUSurfaceGetCurrentTextureStatus_DeviceLost', - 'WGPUSurfaceGetCurrentTextureStatus_Error', - 'WGPUSurfaceGetCurrentTextureStatus_Force32', - 'WGPUSurfaceGetCurrentTextureStatus_Lost', - 'WGPUSurfaceGetCurrentTextureStatus_OutOfMemory', - 'WGPUSurfaceGetCurrentTextureStatus_Outdated', - 'WGPUSurfaceGetCurrentTextureStatus_Success', - 'WGPUSurfaceGetCurrentTextureStatus_Timeout', - 'WGPUSurfaceSourceAndroidNativeWindow', - 'WGPUSurfaceSourceCanvasHTMLSelector_Emscripten', - 'WGPUSurfaceSourceMetalLayer', 'WGPUSurfaceSourceWaylandSurface', - 'WGPUSurfaceSourceWindowsHWND', 'WGPUSurfaceSourceXCBWindow', - 'WGPUSurfaceSourceXlibWindow', 'WGPUSurfaceTexture', - 'WGPUTexture', 'WGPUTextureAspect', 'WGPUTextureAspect_All', - 'WGPUTextureAspect_DepthOnly', 'WGPUTextureAspect_Force32', - 'WGPUTextureAspect_Plane0Only', 'WGPUTextureAspect_Plane1Only', - 'WGPUTextureAspect_Plane2Only', 'WGPUTextureAspect_StencilOnly', - 'WGPUTextureAspect_Undefined', 'WGPUTextureBindingLayout', - 'WGPUTextureBindingViewDimensionDescriptor', - 'WGPUTextureDataLayout', 'WGPUTextureDescriptor', - 'WGPUTextureDimension', 'WGPUTextureDimension_1D', - 'WGPUTextureDimension_2D', 'WGPUTextureDimension_3D', - 'WGPUTextureDimension_Force32', 'WGPUTextureDimension_Undefined', - 'WGPUTextureFormat', 'WGPUTextureFormat_ASTC10x10Unorm', - 'WGPUTextureFormat_ASTC10x10UnormSrgb', - 'WGPUTextureFormat_ASTC10x5Unorm', - 'WGPUTextureFormat_ASTC10x5UnormSrgb', - 'WGPUTextureFormat_ASTC10x6Unorm', - 'WGPUTextureFormat_ASTC10x6UnormSrgb', - 'WGPUTextureFormat_ASTC10x8Unorm', - 'WGPUTextureFormat_ASTC10x8UnormSrgb', - 'WGPUTextureFormat_ASTC12x10Unorm', - 'WGPUTextureFormat_ASTC12x10UnormSrgb', - 'WGPUTextureFormat_ASTC12x12Unorm', - 'WGPUTextureFormat_ASTC12x12UnormSrgb', - 'WGPUTextureFormat_ASTC4x4Unorm', - 'WGPUTextureFormat_ASTC4x4UnormSrgb', - 'WGPUTextureFormat_ASTC5x4Unorm', - 'WGPUTextureFormat_ASTC5x4UnormSrgb', - 'WGPUTextureFormat_ASTC5x5Unorm', - 'WGPUTextureFormat_ASTC5x5UnormSrgb', - 'WGPUTextureFormat_ASTC6x5Unorm', - 'WGPUTextureFormat_ASTC6x5UnormSrgb', - 'WGPUTextureFormat_ASTC6x6Unorm', - 'WGPUTextureFormat_ASTC6x6UnormSrgb', - 'WGPUTextureFormat_ASTC8x5Unorm', - 'WGPUTextureFormat_ASTC8x5UnormSrgb', - 'WGPUTextureFormat_ASTC8x6Unorm', - 'WGPUTextureFormat_ASTC8x6UnormSrgb', - 'WGPUTextureFormat_ASTC8x8Unorm', - 'WGPUTextureFormat_ASTC8x8UnormSrgb', - 'WGPUTextureFormat_BC1RGBAUnorm', - 'WGPUTextureFormat_BC1RGBAUnormSrgb', - 'WGPUTextureFormat_BC2RGBAUnorm', - 'WGPUTextureFormat_BC2RGBAUnormSrgb', - 'WGPUTextureFormat_BC3RGBAUnorm', - 'WGPUTextureFormat_BC3RGBAUnormSrgb', - 'WGPUTextureFormat_BC4RSnorm', 'WGPUTextureFormat_BC4RUnorm', - 'WGPUTextureFormat_BC5RGSnorm', 'WGPUTextureFormat_BC5RGUnorm', - 'WGPUTextureFormat_BC6HRGBFloat', - 'WGPUTextureFormat_BC6HRGBUfloat', - 'WGPUTextureFormat_BC7RGBAUnorm', - 'WGPUTextureFormat_BC7RGBAUnormSrgb', - 'WGPUTextureFormat_BGRA8Unorm', - 'WGPUTextureFormat_BGRA8UnormSrgb', - 'WGPUTextureFormat_Depth16Unorm', 'WGPUTextureFormat_Depth24Plus', - 'WGPUTextureFormat_Depth24PlusStencil8', - 'WGPUTextureFormat_Depth32Float', - 'WGPUTextureFormat_Depth32FloatStencil8', - 'WGPUTextureFormat_EACR11Snorm', 'WGPUTextureFormat_EACR11Unorm', - 'WGPUTextureFormat_EACRG11Snorm', - 'WGPUTextureFormat_EACRG11Unorm', - 'WGPUTextureFormat_ETC2RGB8A1Unorm', - 'WGPUTextureFormat_ETC2RGB8A1UnormSrgb', - 'WGPUTextureFormat_ETC2RGB8Unorm', - 'WGPUTextureFormat_ETC2RGB8UnormSrgb', - 'WGPUTextureFormat_ETC2RGBA8Unorm', - 'WGPUTextureFormat_ETC2RGBA8UnormSrgb', - 'WGPUTextureFormat_External', 'WGPUTextureFormat_Force32', - 'WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm', - 'WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm', - 'WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm', - 'WGPUTextureFormat_R16Float', 'WGPUTextureFormat_R16Sint', - 'WGPUTextureFormat_R16Snorm', 'WGPUTextureFormat_R16Uint', - 'WGPUTextureFormat_R16Unorm', 'WGPUTextureFormat_R32Float', - 'WGPUTextureFormat_R32Sint', 'WGPUTextureFormat_R32Uint', - 'WGPUTextureFormat_R8BG8A8Triplanar420Unorm', - 'WGPUTextureFormat_R8BG8Biplanar420Unorm', - 'WGPUTextureFormat_R8BG8Biplanar422Unorm', - 'WGPUTextureFormat_R8BG8Biplanar444Unorm', - 'WGPUTextureFormat_R8Sint', 'WGPUTextureFormat_R8Snorm', - 'WGPUTextureFormat_R8Uint', 'WGPUTextureFormat_R8Unorm', - 'WGPUTextureFormat_RG11B10Ufloat', 'WGPUTextureFormat_RG16Float', - 'WGPUTextureFormat_RG16Sint', 'WGPUTextureFormat_RG16Snorm', - 'WGPUTextureFormat_RG16Uint', 'WGPUTextureFormat_RG16Unorm', - 'WGPUTextureFormat_RG32Float', 'WGPUTextureFormat_RG32Sint', - 'WGPUTextureFormat_RG32Uint', 'WGPUTextureFormat_RG8Sint', - 'WGPUTextureFormat_RG8Snorm', 'WGPUTextureFormat_RG8Uint', - 'WGPUTextureFormat_RG8Unorm', 'WGPUTextureFormat_RGB10A2Uint', - 'WGPUTextureFormat_RGB10A2Unorm', - 'WGPUTextureFormat_RGB9E5Ufloat', 'WGPUTextureFormat_RGBA16Float', - 'WGPUTextureFormat_RGBA16Sint', 'WGPUTextureFormat_RGBA16Snorm', - 'WGPUTextureFormat_RGBA16Uint', 'WGPUTextureFormat_RGBA16Unorm', - 'WGPUTextureFormat_RGBA32Float', 'WGPUTextureFormat_RGBA32Sint', - 'WGPUTextureFormat_RGBA32Uint', 'WGPUTextureFormat_RGBA8Sint', - 'WGPUTextureFormat_RGBA8Snorm', 'WGPUTextureFormat_RGBA8Uint', - 'WGPUTextureFormat_RGBA8Unorm', - 'WGPUTextureFormat_RGBA8UnormSrgb', 'WGPUTextureFormat_Stencil8', - 'WGPUTextureFormat_Undefined', 'WGPUTextureSampleType', - 'WGPUTextureSampleType_BindingNotUsed', - 'WGPUTextureSampleType_Depth', 'WGPUTextureSampleType_Float', - 'WGPUTextureSampleType_Force32', 'WGPUTextureSampleType_Sint', - 'WGPUTextureSampleType_Uint', - 'WGPUTextureSampleType_UnfilterableFloat', 'WGPUTextureUsage', - 'WGPUTextureUsage_CopyDst', 'WGPUTextureUsage_CopySrc', - 'WGPUTextureUsage_None', 'WGPUTextureUsage_RenderAttachment', - 'WGPUTextureUsage_StorageAttachment', - 'WGPUTextureUsage_StorageBinding', - 'WGPUTextureUsage_TextureBinding', - 'WGPUTextureUsage_TransientAttachment', 'WGPUTextureView', - 'WGPUTextureViewDescriptor', 'WGPUTextureViewDimension', - 'WGPUTextureViewDimension_1D', 'WGPUTextureViewDimension_2D', - 'WGPUTextureViewDimension_2DArray', 'WGPUTextureViewDimension_3D', - 'WGPUTextureViewDimension_Cube', - 'WGPUTextureViewDimension_CubeArray', - 'WGPUTextureViewDimension_Force32', - 'WGPUTextureViewDimension_Undefined', - 'WGPUUncapturedErrorCallback', 'WGPUUncapturedErrorCallbackInfo', - 'WGPUUncapturedErrorCallbackInfo2', 'WGPUVertexAttribute', - 'WGPUVertexBufferLayout', 'WGPUVertexFormat', - 'WGPUVertexFormat_Float16', 'WGPUVertexFormat_Float16x2', - 'WGPUVertexFormat_Float16x4', 'WGPUVertexFormat_Float32', - 'WGPUVertexFormat_Float32x2', 'WGPUVertexFormat_Float32x3', - 'WGPUVertexFormat_Float32x4', 'WGPUVertexFormat_Force32', - 'WGPUVertexFormat_Sint16', 'WGPUVertexFormat_Sint16x2', - 'WGPUVertexFormat_Sint16x4', 'WGPUVertexFormat_Sint32', - 'WGPUVertexFormat_Sint32x2', 'WGPUVertexFormat_Sint32x3', - 'WGPUVertexFormat_Sint32x4', 'WGPUVertexFormat_Sint8', - 'WGPUVertexFormat_Sint8x2', 'WGPUVertexFormat_Sint8x4', - 'WGPUVertexFormat_Snorm16', 'WGPUVertexFormat_Snorm16x2', - 'WGPUVertexFormat_Snorm16x4', 'WGPUVertexFormat_Snorm8', - 'WGPUVertexFormat_Snorm8x2', 'WGPUVertexFormat_Snorm8x4', - 'WGPUVertexFormat_Uint16', 'WGPUVertexFormat_Uint16x2', - 'WGPUVertexFormat_Uint16x4', 'WGPUVertexFormat_Uint32', - 'WGPUVertexFormat_Uint32x2', 'WGPUVertexFormat_Uint32x3', - 'WGPUVertexFormat_Uint32x4', 'WGPUVertexFormat_Uint8', - 'WGPUVertexFormat_Uint8x2', 'WGPUVertexFormat_Uint8x4', - 'WGPUVertexFormat_Unorm10_10_10_2', 'WGPUVertexFormat_Unorm16', - 'WGPUVertexFormat_Unorm16x2', 'WGPUVertexFormat_Unorm16x4', - 'WGPUVertexFormat_Unorm8', 'WGPUVertexFormat_Unorm8x2', - 'WGPUVertexFormat_Unorm8x4', 'WGPUVertexFormat_Unorm8x4BGRA', - 'WGPUVertexState', 'WGPUVertexStepMode', - 'WGPUVertexStepMode_Force32', 'WGPUVertexStepMode_Instance', - 'WGPUVertexStepMode_Undefined', 'WGPUVertexStepMode_Vertex', - 'WGPUWGSLFeatureName', - 'WGPUWGSLFeatureName_ChromiumTestingExperimental', - 'WGPUWGSLFeatureName_ChromiumTestingShipped', - 'WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch', - 'WGPUWGSLFeatureName_ChromiumTestingUnimplemented', - 'WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental', - 'WGPUWGSLFeatureName_Force32', - 'WGPUWGSLFeatureName_Packed4x8IntegerDotProduct', - 'WGPUWGSLFeatureName_PointerCompositeAccess', - 'WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures', - 'WGPUWGSLFeatureName_UnrestrictedPointerParameters', - 'WGPUWaitStatus', 'WGPUWaitStatus_Force32', - 'WGPUWaitStatus_Success', 'WGPUWaitStatus_TimedOut', - 'WGPUWaitStatus_Unknown', 'WGPUWaitStatus_UnsupportedCount', - 'WGPUWaitStatus_UnsupportedMixedSources', - 'WGPUWaitStatus_UnsupportedTimeout', 'WGPUYCbCrVkDescriptor', - 'int32_t', 'size_t', 'struct_WGPUAHardwareBufferProperties', - 'struct_WGPUAdapterImpl', 'struct_WGPUAdapterInfo', - 'struct_WGPUAdapterPropertiesD3D', - 'struct_WGPUAdapterPropertiesMemoryHeaps', - 'struct_WGPUAdapterPropertiesSubgroups', - 'struct_WGPUAdapterPropertiesVk', - 'struct_WGPUBindGroupDescriptor', 'struct_WGPUBindGroupEntry', - 'struct_WGPUBindGroupImpl', - 'struct_WGPUBindGroupLayoutDescriptor', - 'struct_WGPUBindGroupLayoutEntry', - 'struct_WGPUBindGroupLayoutImpl', 'struct_WGPUBlendComponent', - 'struct_WGPUBlendState', 'struct_WGPUBufferBindingLayout', - 'struct_WGPUBufferDescriptor', - 'struct_WGPUBufferHostMappedPointer', 'struct_WGPUBufferImpl', - 'struct_WGPUBufferMapCallbackInfo', - 'struct_WGPUBufferMapCallbackInfo2', 'struct_WGPUChainedStruct', - 'struct_WGPUChainedStructOut', 'struct_WGPUColor', - 'struct_WGPUColorTargetState', - 'struct_WGPUColorTargetStateExpandResolveTextureDawn', - 'struct_WGPUCommandBufferDescriptor', - 'struct_WGPUCommandBufferImpl', - 'struct_WGPUCommandEncoderDescriptor', - 'struct_WGPUCommandEncoderImpl', 'struct_WGPUCompilationInfo', - 'struct_WGPUCompilationInfoCallbackInfo', - 'struct_WGPUCompilationInfoCallbackInfo2', - 'struct_WGPUCompilationMessage', - 'struct_WGPUComputePassDescriptor', - 'struct_WGPUComputePassEncoderImpl', - 'struct_WGPUComputePassTimestampWrites', - 'struct_WGPUComputePipelineDescriptor', - 'struct_WGPUComputePipelineImpl', 'struct_WGPUComputeState', - 'struct_WGPUConstantEntry', - 'struct_WGPUCopyTextureForBrowserOptions', - 'struct_WGPUCreateComputePipelineAsyncCallbackInfo', - 'struct_WGPUCreateComputePipelineAsyncCallbackInfo2', - 'struct_WGPUCreateRenderPipelineAsyncCallbackInfo', - 'struct_WGPUCreateRenderPipelineAsyncCallbackInfo2', - 'struct_WGPUDawnAdapterPropertiesPowerPreference', - 'struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient', - 'struct_WGPUDawnCacheDeviceDescriptor', - 'struct_WGPUDawnEncoderInternalUsageDescriptor', - 'struct_WGPUDawnExperimentalImmediateDataLimits', - 'struct_WGPUDawnExperimentalSubgroupLimits', - 'struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled', - 'struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor', - 'struct_WGPUDawnTexelCopyBufferRowAlignmentLimits', - 'struct_WGPUDawnTextureInternalUsageDescriptor', - 'struct_WGPUDawnTogglesDescriptor', - 'struct_WGPUDawnWGSLBlocklist', 'struct_WGPUDawnWireWGSLControl', - 'struct_WGPUDepthStencilState', 'struct_WGPUDeviceDescriptor', - 'struct_WGPUDeviceImpl', 'struct_WGPUDeviceLostCallbackInfo', - 'struct_WGPUDeviceLostCallbackInfo2', - 'struct_WGPUDrmFormatCapabilities', - 'struct_WGPUDrmFormatProperties', 'struct_WGPUExtent2D', - 'struct_WGPUExtent3D', 'struct_WGPUExternalTextureBindingEntry', - 'struct_WGPUExternalTextureBindingLayout', - 'struct_WGPUExternalTextureDescriptor', - 'struct_WGPUExternalTextureImpl', 'struct_WGPUFormatCapabilities', - 'struct_WGPUFragmentState', 'struct_WGPUFuture', - 'struct_WGPUFutureWaitInfo', - 'struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER', - 'struct_WGPUImageCopyBuffer', - 'struct_WGPUImageCopyExternalTexture', - 'struct_WGPUImageCopyTexture', 'struct_WGPUInstanceDescriptor', - 'struct_WGPUInstanceFeatures', 'struct_WGPUInstanceImpl', - 'struct_WGPULimits', 'struct_WGPUMemoryHeapInfo', - 'struct_WGPUMultisampleState', 'struct_WGPUOrigin2D', - 'struct_WGPUOrigin3D', 'struct_WGPUPipelineLayoutDescriptor', - 'struct_WGPUPipelineLayoutImpl', - 'struct_WGPUPipelineLayoutPixelLocalStorage', - 'struct_WGPUPipelineLayoutStorageAttachment', - 'struct_WGPUPopErrorScopeCallbackInfo', - 'struct_WGPUPopErrorScopeCallbackInfo2', - 'struct_WGPUPrimitiveState', 'struct_WGPUQuerySetDescriptor', - 'struct_WGPUQuerySetImpl', 'struct_WGPUQueueDescriptor', - 'struct_WGPUQueueImpl', 'struct_WGPUQueueWorkDoneCallbackInfo', - 'struct_WGPUQueueWorkDoneCallbackInfo2', - 'struct_WGPURenderBundleDescriptor', - 'struct_WGPURenderBundleEncoderDescriptor', - 'struct_WGPURenderBundleEncoderImpl', - 'struct_WGPURenderBundleImpl', - 'struct_WGPURenderPassColorAttachment', - 'struct_WGPURenderPassDepthStencilAttachment', - 'struct_WGPURenderPassDescriptor', - 'struct_WGPURenderPassDescriptorExpandResolveRect', - 'struct_WGPURenderPassEncoderImpl', - 'struct_WGPURenderPassMaxDrawCount', - 'struct_WGPURenderPassPixelLocalStorage', - 'struct_WGPURenderPassStorageAttachment', - 'struct_WGPURenderPassTimestampWrites', - 'struct_WGPURenderPipelineDescriptor', - 'struct_WGPURenderPipelineImpl', - 'struct_WGPURequestAdapterCallbackInfo', - 'struct_WGPURequestAdapterCallbackInfo2', - 'struct_WGPURequestAdapterOptions', - 'struct_WGPURequestDeviceCallbackInfo', - 'struct_WGPURequestDeviceCallbackInfo2', - 'struct_WGPURequiredLimits', 'struct_WGPUSamplerBindingLayout', - 'struct_WGPUSamplerDescriptor', 'struct_WGPUSamplerImpl', - 'struct_WGPUShaderModuleCompilationOptions', - 'struct_WGPUShaderModuleDescriptor', - 'struct_WGPUShaderModuleImpl', 'struct_WGPUShaderSourceSPIRV', - 'struct_WGPUShaderSourceWGSL', - 'struct_WGPUSharedBufferMemoryBeginAccessDescriptor', - 'struct_WGPUSharedBufferMemoryDescriptor', - 'struct_WGPUSharedBufferMemoryEndAccessState', - 'struct_WGPUSharedBufferMemoryImpl', - 'struct_WGPUSharedBufferMemoryProperties', - 'struct_WGPUSharedFenceDXGISharedHandleDescriptor', - 'struct_WGPUSharedFenceDXGISharedHandleExportInfo', - 'struct_WGPUSharedFenceDescriptor', - 'struct_WGPUSharedFenceExportInfo', 'struct_WGPUSharedFenceImpl', - 'struct_WGPUSharedFenceMTLSharedEventDescriptor', - 'struct_WGPUSharedFenceMTLSharedEventExportInfo', - 'struct_WGPUSharedFenceSyncFDDescriptor', - 'struct_WGPUSharedFenceSyncFDExportInfo', - 'struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor', - 'struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo', - 'struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor', - 'struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo', - 'struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor', - 'struct_WGPUSharedTextureMemoryAHardwareBufferProperties', - 'struct_WGPUSharedTextureMemoryBeginAccessDescriptor', - 'struct_WGPUSharedTextureMemoryD3DSwapchainBeginState', - 'struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor', - 'struct_WGPUSharedTextureMemoryDescriptor', - 'struct_WGPUSharedTextureMemoryDmaBufDescriptor', - 'struct_WGPUSharedTextureMemoryDmaBufPlane', - 'struct_WGPUSharedTextureMemoryEGLImageDescriptor', - 'struct_WGPUSharedTextureMemoryEndAccessState', - 'struct_WGPUSharedTextureMemoryIOSurfaceDescriptor', - 'struct_WGPUSharedTextureMemoryImpl', - 'struct_WGPUSharedTextureMemoryOpaqueFDDescriptor', - 'struct_WGPUSharedTextureMemoryProperties', - 'struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor', - 'struct_WGPUSharedTextureMemoryVkImageLayoutBeginState', - 'struct_WGPUSharedTextureMemoryVkImageLayoutEndState', - 'struct_WGPUSharedTextureMemoryZirconHandleDescriptor', - 'struct_WGPUStaticSamplerBindingLayout', - 'struct_WGPUStencilFaceState', - 'struct_WGPUStorageTextureBindingLayout', 'struct_WGPUStringView', - 'struct_WGPUSupportedFeatures', 'struct_WGPUSupportedLimits', - 'struct_WGPUSurfaceCapabilities', - 'struct_WGPUSurfaceConfiguration', 'struct_WGPUSurfaceDescriptor', - 'struct_WGPUSurfaceDescriptorFromWindowsCoreWindow', - 'struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel', - 'struct_WGPUSurfaceImpl', - 'struct_WGPUSurfaceSourceAndroidNativeWindow', - 'struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten', - 'struct_WGPUSurfaceSourceMetalLayer', - 'struct_WGPUSurfaceSourceWaylandSurface', - 'struct_WGPUSurfaceSourceWindowsHWND', - 'struct_WGPUSurfaceSourceXCBWindow', - 'struct_WGPUSurfaceSourceXlibWindow', 'struct_WGPUSurfaceTexture', - 'struct_WGPUTextureBindingLayout', - 'struct_WGPUTextureBindingViewDimensionDescriptor', - 'struct_WGPUTextureDataLayout', 'struct_WGPUTextureDescriptor', - 'struct_WGPUTextureImpl', 'struct_WGPUTextureViewDescriptor', - 'struct_WGPUTextureViewImpl', - 'struct_WGPUUncapturedErrorCallbackInfo', - 'struct_WGPUUncapturedErrorCallbackInfo2', - 'struct_WGPUVertexAttribute', 'struct_WGPUVertexBufferLayout', - 'struct_WGPUVertexState', 'struct_WGPUYCbCrVkDescriptor', - 'uint32_t', 'uint64_t', 'wgpuAdapterAddRef', - 'wgpuAdapterCreateDevice', 'wgpuAdapterGetFeatures', - 'wgpuAdapterGetFormatCapabilities', 'wgpuAdapterGetInfo', - 'wgpuAdapterGetInstance', 'wgpuAdapterGetLimits', - 'wgpuAdapterHasFeature', 'wgpuAdapterInfoFreeMembers', - 'wgpuAdapterPropertiesMemoryHeapsFreeMembers', - 'wgpuAdapterRelease', 'wgpuAdapterRequestDevice', - 'wgpuAdapterRequestDevice2', 'wgpuAdapterRequestDeviceF', - 'wgpuBindGroupAddRef', 'wgpuBindGroupLayoutAddRef', - 'wgpuBindGroupLayoutRelease', 'wgpuBindGroupLayoutSetLabel', - 'wgpuBindGroupRelease', 'wgpuBindGroupSetLabel', - 'wgpuBufferAddRef', 'wgpuBufferDestroy', - 'wgpuBufferGetConstMappedRange', 'wgpuBufferGetMapState', - 'wgpuBufferGetMappedRange', 'wgpuBufferGetSize', - 'wgpuBufferGetUsage', 'wgpuBufferMapAsync', 'wgpuBufferMapAsync2', - 'wgpuBufferMapAsyncF', 'wgpuBufferRelease', 'wgpuBufferSetLabel', - 'wgpuBufferUnmap', 'wgpuCommandBufferAddRef', - 'wgpuCommandBufferRelease', 'wgpuCommandBufferSetLabel', - 'wgpuCommandEncoderAddRef', 'wgpuCommandEncoderBeginComputePass', - 'wgpuCommandEncoderBeginRenderPass', - 'wgpuCommandEncoderClearBuffer', - 'wgpuCommandEncoderCopyBufferToBuffer', - 'wgpuCommandEncoderCopyBufferToTexture', - 'wgpuCommandEncoderCopyTextureToBuffer', - 'wgpuCommandEncoderCopyTextureToTexture', - 'wgpuCommandEncoderFinish', - 'wgpuCommandEncoderInjectValidationError', - 'wgpuCommandEncoderInsertDebugMarker', - 'wgpuCommandEncoderPopDebugGroup', - 'wgpuCommandEncoderPushDebugGroup', 'wgpuCommandEncoderRelease', - 'wgpuCommandEncoderResolveQuerySet', 'wgpuCommandEncoderSetLabel', - 'wgpuCommandEncoderWriteBuffer', - 'wgpuCommandEncoderWriteTimestamp', - 'wgpuComputePassEncoderAddRef', - 'wgpuComputePassEncoderDispatchWorkgroups', - 'wgpuComputePassEncoderDispatchWorkgroupsIndirect', - 'wgpuComputePassEncoderEnd', - 'wgpuComputePassEncoderInsertDebugMarker', - 'wgpuComputePassEncoderPopDebugGroup', - 'wgpuComputePassEncoderPushDebugGroup', - 'wgpuComputePassEncoderRelease', - 'wgpuComputePassEncoderSetBindGroup', - 'wgpuComputePassEncoderSetLabel', - 'wgpuComputePassEncoderSetPipeline', - 'wgpuComputePassEncoderWriteTimestamp', - 'wgpuComputePipelineAddRef', - 'wgpuComputePipelineGetBindGroupLayout', - 'wgpuComputePipelineRelease', 'wgpuComputePipelineSetLabel', - 'wgpuCreateInstance', 'wgpuDeviceAddRef', - 'wgpuDeviceCreateBindGroup', 'wgpuDeviceCreateBindGroupLayout', - 'wgpuDeviceCreateBuffer', 'wgpuDeviceCreateCommandEncoder', - 'wgpuDeviceCreateComputePipeline', - 'wgpuDeviceCreateComputePipelineAsync', - 'wgpuDeviceCreateComputePipelineAsync2', - 'wgpuDeviceCreateComputePipelineAsyncF', - 'wgpuDeviceCreateErrorBuffer', - 'wgpuDeviceCreateErrorExternalTexture', - 'wgpuDeviceCreateErrorShaderModule', - 'wgpuDeviceCreateErrorTexture', 'wgpuDeviceCreateExternalTexture', - 'wgpuDeviceCreatePipelineLayout', 'wgpuDeviceCreateQuerySet', - 'wgpuDeviceCreateRenderBundleEncoder', - 'wgpuDeviceCreateRenderPipeline', - 'wgpuDeviceCreateRenderPipelineAsync', - 'wgpuDeviceCreateRenderPipelineAsync2', - 'wgpuDeviceCreateRenderPipelineAsyncF', 'wgpuDeviceCreateSampler', - 'wgpuDeviceCreateShaderModule', 'wgpuDeviceCreateTexture', - 'wgpuDeviceDestroy', 'wgpuDeviceForceLoss', - 'wgpuDeviceGetAHardwareBufferProperties', 'wgpuDeviceGetAdapter', - 'wgpuDeviceGetAdapterInfo', 'wgpuDeviceGetFeatures', - 'wgpuDeviceGetLimits', 'wgpuDeviceGetLostFuture', - 'wgpuDeviceGetQueue', 'wgpuDeviceHasFeature', - 'wgpuDeviceImportSharedBufferMemory', - 'wgpuDeviceImportSharedFence', - 'wgpuDeviceImportSharedTextureMemory', 'wgpuDeviceInjectError', - 'wgpuDevicePopErrorScope', 'wgpuDevicePopErrorScope2', - 'wgpuDevicePopErrorScopeF', 'wgpuDevicePushErrorScope', - 'wgpuDeviceRelease', 'wgpuDeviceSetLabel', - 'wgpuDeviceSetLoggingCallback', 'wgpuDeviceTick', - 'wgpuDeviceValidateTextureDescriptor', - 'wgpuDrmFormatCapabilitiesFreeMembers', - 'wgpuExternalTextureAddRef', 'wgpuExternalTextureDestroy', - 'wgpuExternalTextureExpire', 'wgpuExternalTextureRefresh', - 'wgpuExternalTextureRelease', 'wgpuExternalTextureSetLabel', - 'wgpuGetInstanceFeatures', 'wgpuGetProcAddress', - 'wgpuInstanceAddRef', 'wgpuInstanceCreateSurface', - 'wgpuInstanceEnumerateWGSLLanguageFeatures', - 'wgpuInstanceHasWGSLLanguageFeature', 'wgpuInstanceProcessEvents', - 'wgpuInstanceRelease', 'wgpuInstanceRequestAdapter', - 'wgpuInstanceRequestAdapter2', 'wgpuInstanceRequestAdapterF', - 'wgpuInstanceWaitAny', 'wgpuPipelineLayoutAddRef', - 'wgpuPipelineLayoutRelease', 'wgpuPipelineLayoutSetLabel', - 'wgpuQuerySetAddRef', 'wgpuQuerySetDestroy', - 'wgpuQuerySetGetCount', 'wgpuQuerySetGetType', - 'wgpuQuerySetRelease', 'wgpuQuerySetSetLabel', 'wgpuQueueAddRef', - 'wgpuQueueCopyExternalTextureForBrowser', - 'wgpuQueueCopyTextureForBrowser', 'wgpuQueueOnSubmittedWorkDone', - 'wgpuQueueOnSubmittedWorkDone2', 'wgpuQueueOnSubmittedWorkDoneF', - 'wgpuQueueRelease', 'wgpuQueueSetLabel', 'wgpuQueueSubmit', - 'wgpuQueueWriteBuffer', 'wgpuQueueWriteTexture', - 'wgpuRenderBundleAddRef', 'wgpuRenderBundleEncoderAddRef', - 'wgpuRenderBundleEncoderDraw', - 'wgpuRenderBundleEncoderDrawIndexed', - 'wgpuRenderBundleEncoderDrawIndexedIndirect', - 'wgpuRenderBundleEncoderDrawIndirect', - 'wgpuRenderBundleEncoderFinish', - 'wgpuRenderBundleEncoderInsertDebugMarker', - 'wgpuRenderBundleEncoderPopDebugGroup', - 'wgpuRenderBundleEncoderPushDebugGroup', - 'wgpuRenderBundleEncoderRelease', - 'wgpuRenderBundleEncoderSetBindGroup', - 'wgpuRenderBundleEncoderSetIndexBuffer', - 'wgpuRenderBundleEncoderSetLabel', - 'wgpuRenderBundleEncoderSetPipeline', - 'wgpuRenderBundleEncoderSetVertexBuffer', - 'wgpuRenderBundleRelease', 'wgpuRenderBundleSetLabel', - 'wgpuRenderPassEncoderAddRef', - 'wgpuRenderPassEncoderBeginOcclusionQuery', - 'wgpuRenderPassEncoderDraw', 'wgpuRenderPassEncoderDrawIndexed', - 'wgpuRenderPassEncoderDrawIndexedIndirect', - 'wgpuRenderPassEncoderDrawIndirect', 'wgpuRenderPassEncoderEnd', - 'wgpuRenderPassEncoderEndOcclusionQuery', - 'wgpuRenderPassEncoderExecuteBundles', - 'wgpuRenderPassEncoderInsertDebugMarker', - 'wgpuRenderPassEncoderMultiDrawIndexedIndirect', - 'wgpuRenderPassEncoderMultiDrawIndirect', - 'wgpuRenderPassEncoderPixelLocalStorageBarrier', - 'wgpuRenderPassEncoderPopDebugGroup', - 'wgpuRenderPassEncoderPushDebugGroup', - 'wgpuRenderPassEncoderRelease', - 'wgpuRenderPassEncoderSetBindGroup', - 'wgpuRenderPassEncoderSetBlendConstant', - 'wgpuRenderPassEncoderSetIndexBuffer', - 'wgpuRenderPassEncoderSetLabel', - 'wgpuRenderPassEncoderSetPipeline', - 'wgpuRenderPassEncoderSetScissorRect', - 'wgpuRenderPassEncoderSetStencilReference', - 'wgpuRenderPassEncoderSetVertexBuffer', - 'wgpuRenderPassEncoderSetViewport', - 'wgpuRenderPassEncoderWriteTimestamp', 'wgpuRenderPipelineAddRef', - 'wgpuRenderPipelineGetBindGroupLayout', - 'wgpuRenderPipelineRelease', 'wgpuRenderPipelineSetLabel', - 'wgpuSamplerAddRef', 'wgpuSamplerRelease', 'wgpuSamplerSetLabel', - 'wgpuShaderModuleAddRef', 'wgpuShaderModuleGetCompilationInfo', - 'wgpuShaderModuleGetCompilationInfo2', - 'wgpuShaderModuleGetCompilationInfoF', 'wgpuShaderModuleRelease', - 'wgpuShaderModuleSetLabel', 'wgpuSharedBufferMemoryAddRef', - 'wgpuSharedBufferMemoryBeginAccess', - 'wgpuSharedBufferMemoryCreateBuffer', - 'wgpuSharedBufferMemoryEndAccess', - 'wgpuSharedBufferMemoryEndAccessStateFreeMembers', - 'wgpuSharedBufferMemoryGetProperties', - 'wgpuSharedBufferMemoryIsDeviceLost', - 'wgpuSharedBufferMemoryRelease', 'wgpuSharedBufferMemorySetLabel', - 'wgpuSharedFenceAddRef', 'wgpuSharedFenceExportInfo', - 'wgpuSharedFenceRelease', 'wgpuSharedTextureMemoryAddRef', - 'wgpuSharedTextureMemoryBeginAccess', - 'wgpuSharedTextureMemoryCreateTexture', - 'wgpuSharedTextureMemoryEndAccess', - 'wgpuSharedTextureMemoryEndAccessStateFreeMembers', - 'wgpuSharedTextureMemoryGetProperties', - 'wgpuSharedTextureMemoryIsDeviceLost', - 'wgpuSharedTextureMemoryRelease', - 'wgpuSharedTextureMemorySetLabel', - 'wgpuSupportedFeaturesFreeMembers', 'wgpuSurfaceAddRef', - 'wgpuSurfaceCapabilitiesFreeMembers', 'wgpuSurfaceConfigure', - 'wgpuSurfaceGetCapabilities', 'wgpuSurfaceGetCurrentTexture', - 'wgpuSurfacePresent', 'wgpuSurfaceRelease', 'wgpuSurfaceSetLabel', - 'wgpuSurfaceUnconfigure', 'wgpuTextureAddRef', - 'wgpuTextureCreateErrorView', 'wgpuTextureCreateView', - 'wgpuTextureDestroy', 'wgpuTextureGetDepthOrArrayLayers', - 'wgpuTextureGetDimension', 'wgpuTextureGetFormat', - 'wgpuTextureGetHeight', 'wgpuTextureGetMipLevelCount', - 'wgpuTextureGetSampleCount', 'wgpuTextureGetUsage', - 'wgpuTextureGetWidth', 'wgpuTextureRelease', - 'wgpuTextureSetLabel', 'wgpuTextureViewAddRef', - 'wgpuTextureViewRelease', 'wgpuTextureViewSetLabel'] diff --git a/tinygrad/tinygrad/runtime/graph/__init__.py b/tinygrad/tinygrad/runtime/graph/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/runtime/graph/cpu.py b/tinygrad/tinygrad/runtime/graph/cpu.py deleted file mode 100644 index 390c35a2..00000000 --- a/tinygrad/tinygrad/runtime/graph/cpu.py +++ /dev/null @@ -1,67 +0,0 @@ -from typing import cast, TypeVar, Generic, get_args as get_typing_args -import itertools -from tinygrad.helpers import dedup, flatten, DEBUG, to_function_name -from tinygrad.engine.jit import GraphRunner, GraphException -from tinygrad.device import Buffer -from tinygrad.engine.realize import ExecItem, CompiledRunner -from tinygrad.uop.ops import Variable -from tinygrad.dtype import DType, dtypes -from tinygrad.renderer.cstyle import ClangRenderer -from tinygrad.renderer.llvmir import LLVMRenderer, ldt - -T = TypeVar('T') -class BatchedGraph(Generic[T], GraphRunner): - def __init__(self, device, jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int]): - renderer_class = get_typing_args(getattr(self, "__orig_bases__")[0])[0] - if not issubclass(type(device.renderer), renderer_class) and not isinstance(device.renderer, renderer_class): raise GraphException - - super().__init__(jit_cache, input_rawbuffers, var_vals) - self.base_bufs = dedup(b.base for ji in jit_cache for b in ji.bufs if b is not None and b not in input_rawbuffers) - self.base_rawbufs = [b._buf for b in self.base_bufs] - - targs = [(f"arg{i}", x.dtype.ptr()) for i,x in enumerate(input_rawbuffers)] + \ - [(f"cbuf{i}", dtypes.char.ptr()) for i in range(len(self.base_bufs))] + \ - sorted([(f"{v.expr}", dtypes.int) for v in var_vals]) - code = self._prepare_code(device.renderer, jit_cache, input_rawbuffers, targs) - if DEBUG >= 4: print(code) - self.clprg = device.runtime("batched", device.compiler.compile_cached(code)) - - def _prepare_code(self, renderer:T, jit_cache:list[ExecItem], input_rawbuffers:list[Buffer], targs:list[tuple[str, DType]]) -> str: return "" - def __call__(self, rawbufs: list[Buffer], var_vals: dict[Variable, int], wait=False): - return self.clprg(*[x._buf for x in rawbufs], *self.base_rawbufs, *[x[1] for x in sorted(var_vals.items(), key=lambda x: x[0].expr)], wait=wait) - -class CPUGraph(BatchedGraph[ClangRenderer]): - def _prepare_code(self, renderer:ClangRenderer, jit_cache:list[ExecItem], input_rawbuffers:list[Buffer], targs:list[tuple[str, DType]]) -> str: - def render_arg(buf): - if buf in input_rawbuffers: return f"arg{input_rawbuffers.index(buf)}" - return f"({renderer.render_dtype(buf.dtype)}*)(cbuf{self.base_bufs.index(buf.base)} + {buf.offset})" - - batched = ["void batched("+','.join([f"{renderer.render_dtype(x[1])} {x[0]}" for x in targs])+") {"] - for i, ji in enumerate(jit_cache): - args = [render_arg(buf) for buf in ji.bufs] + [x.expr for x in cast(CompiledRunner, ji.prg).p.vars] - batched.append(f" {to_function_name(cast(CompiledRunner, ji.prg).p.name)}({','.join(args)});") - batched.append("}") - - prep = [renderer._render(cast(CompiledRunner, ji.prg).p.uops or []) for i,ji in enumerate(jit_cache)] - funcs = dedup(renderer._render_body(prep[i][0], *prep[i][1:], cast(CompiledRunner, ji.prg).p.uops, - ["static", "__attribute__((always_inline))"]) for i,ji in enumerate(jit_cache)) - defines = dedup(itertools.chain.from_iterable(renderer._render_defines(cast(CompiledRunner, ji.prg).p.uops) for ji in jit_cache)) - entry = renderer._render_entry("batched", [(t[0], (t[1], False)) for t in targs]) - return '\n'.join(defines) + '\n' + '\n'.join([''.join(f) for f in funcs]) + '\n'.join(batched) + '\n' + entry - -class LLVMGraph(BatchedGraph[LLVMRenderer]): - def _prepare_code(self, renderer, jit_cache:list[ExecItem], input_rawbuffers:list[Buffer], targs:list[tuple[str, DType]]) -> str: - out = [] - for i,ji in enumerate(jit_cache): - args = [] - for j,buf in enumerate(cast(list[Buffer], ji.bufs)): - arg = f"%arg{input_rawbuffers.index(buf)}" if buf in input_rawbuffers else f"%b{i}_{j}" - if buf not in input_rawbuffers: out.append(f" {arg} = getelementptr inbounds i8,ptr %cbuf{self.base_bufs.index(buf.base)},i64 {buf.offset}") - args.append(f"{ldt(buf.dtype.ptr())} {arg}") - args += [f"{ldt(x.dtype)} %{x.expr}" for x in cast(CompiledRunner, ji.prg).p.vars] - out.append(f" call void @{to_function_name(cast(CompiledRunner, ji.prg).p.name)}({','.join(args)})") - - kernels = dedup(tuple(renderer._render_kernel(cast(CompiledRunner, ji.prg).p.uops, ["internal"]) for i,ji in enumerate(jit_cache))) - kernels += [((), renderer._render_fn("batched", [(f"%{x[0]}", x[1]) for x in targs], out))] - assert flatten(x[0] for x in kernels) == [] # global definitions are not used in CPU mode right now - return "\n".join([x[1] for x in kernels] + [renderer._render_footer(cast(CompiledRunner, ji.prg).p.uops)]) diff --git a/tinygrad/tinygrad/runtime/graph/cuda.py b/tinygrad/tinygrad/runtime/graph/cuda.py deleted file mode 100644 index 7ab99ad0..00000000 --- a/tinygrad/tinygrad/runtime/graph/cuda.py +++ /dev/null @@ -1,76 +0,0 @@ -import ctypes -from typing import Any, cast -import tinygrad.runtime.autogen.cuda as cuda -from tinygrad.helpers import init_c_var, dedup -from tinygrad.device import Buffer, Device -from tinygrad.runtime.ops_cuda import CUDADevice, check, encode_args, cu_time_execution -from tinygrad.uop.ops import Variable -from tinygrad.engine.realize import ExecItem, BufferXfer, CompiledRunner -from tinygrad.engine.jit import MultiGraphRunner, GraphException - -class CUDAGraph(MultiGraphRunner): - def __init__(self, jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int]): - super().__init__(jit_cache, input_rawbuffers, var_vals) - - # Check all jit items are compatible. - if not all(isinstance(ji.prg, (CompiledRunner, BufferXfer)) for ji in jit_cache): raise GraphException - - self.jc_idx_with_updatable_rawbufs = dedup([x[0] for x in self.input_replace.keys()]) - self.updatable_nodes: dict[int, tuple[Any, Any, Any, bool]] = {} # dict[jc index] = tuple(graph node, node params, input kernel params, is memcpy) - - self.graph = init_c_var(cuda.CUgraph(), lambda x: check(cuda.cuGraphCreate(ctypes.byref(x), 0))) - - for j,ji in enumerate(jit_cache): - if isinstance(ji.prg, CompiledRunner): - global_size, local_size = ji.prg.p.launch_dims(var_vals) - - new_node = cuda.CUgraphNode() - deps = self._access_resources([x.base for x in ji.bufs if x is not None], ji.prg.p.outs, new_dependency=new_node) - c_deps = (cuda.CUgraphNode*len(deps))(*deps) if deps else None - - c_args, vargs = encode_args([cast(Buffer, x)._buf for x in ji.bufs], [var_vals.get(x, ji.fixedvars.get(x)) for x in ji.prg.p.vars]) - kern_params = cuda.CUDA_KERNEL_NODE_PARAMS(ji.prg._prg.prg, *global_size, *local_size, 0, None, vargs) - check(cuda.cuGraphAddKernelNode(ctypes.byref(new_node), self.graph, c_deps, len(deps), ctypes.byref(kern_params))) - - if j in self.launch_dims_replace or j in self.var_vals_replace or j in self.jc_idx_with_updatable_rawbufs: - self.updatable_nodes[j] = (new_node, kern_params, c_args, False) - elif isinstance(ji.prg, BufferXfer): - dest, src = [cast(Buffer, x) for x in ji.bufs[0:2]] - src_dev = cast(CUDADevice, Device[src.device]) - node_from = cuda.CUgraphNode() - deps = self._access_resources(rawbufs=[dest.base, src.base], write=[0], new_dependency=node_from) - c_deps = (cuda.CUgraphNode*len(deps))(*deps) if deps else None - cp_params = cuda.CUDA_MEMCPY3D_v2(srcMemoryType=cuda.CU_MEMORYTYPE_DEVICE, srcDevice=src._buf, srcPitch=src.nbytes, srcHeight=1, - dstMemoryType=cuda.CU_MEMORYTYPE_DEVICE, dstDevice=dest._buf, dstPitch=dest.nbytes, dstHeight=1, - WidthInBytes=dest.nbytes, Height=1, Depth=1) - check(cuda.cuGraphAddMemcpyNode(ctypes.byref(node_from), self.graph, c_deps, len(deps), ctypes.byref(cp_params), src_dev.context)) - if j in self.jc_idx_with_updatable_rawbufs: self.updatable_nodes[j] = (node_from, cp_params, src_dev.context, True) - - self.instance = init_c_var(cuda.CUgraphExec(), lambda x: check(cuda.cuGraphInstantiate_v2(ctypes.byref(x), self.graph, None, None, 0))) - - def __call__(self, input_rawbuffers: list[Buffer], var_vals: dict[Variable, int], wait=False) -> float|None: - # Update rawbuffers in the c_args struct. - for (j,i),input_idx in self.input_replace.items(): - if not self.updatable_nodes[j][3]: setattr(self.updatable_nodes[j][2], f'f{i}', input_rawbuffers[input_idx]._buf) - else: - if i == 0: self.updatable_nodes[j][1].destDevice = input_rawbuffers[input_idx]._buf - elif i == 1: self.updatable_nodes[j][1].srcDevice = input_rawbuffers[input_idx]._buf - - # Update var_vals in the c_args struct. - for j, i, v in self.updated_vars(var_vals): setattr(self.updatable_nodes[j][2], f'v{i}', v) - - # Update launch dims in the kern_params struct. - for j, global_dims, local_dims in self.updated_launch_dims(var_vals): - node = self.updatable_nodes[j][1] - node.blockDimX, node.blockDimY, node.blockDimZ, node.gridDimX, node.gridDimY, node.gridDimZ = *local_dims, *global_dims # type: ignore[misc] - - # Update graph nodes with the updated structs. - for node, c_node_params, c_args, is_copy in self.updatable_nodes.values(): - if not is_copy: check(cuda.cuGraphExecKernelNodeSetParams(self.instance, node, ctypes.byref(c_node_params))) - else: check(cuda.cuGraphExecMemcpyNodeSetParams(self.instance, node, ctypes.byref(c_node_params), c_args)) - - return cu_time_execution(lambda: check(cuda.cuGraphLaunch(self.instance, None)), enable=wait) - - def __del__(self): - if hasattr(self, 'graph'): check(cuda.cuGraphDestroy(self.graph)) - if hasattr(self, 'instance'): check(cuda.cuGraphExecDestroy(self.instance)) diff --git a/tinygrad/tinygrad/runtime/graph/hcq.py b/tinygrad/tinygrad/runtime/graph/hcq.py deleted file mode 100644 index 4bcf17db..00000000 --- a/tinygrad/tinygrad/runtime/graph/hcq.py +++ /dev/null @@ -1,210 +0,0 @@ -import collections, time -from typing import Any, cast -from tinygrad.helpers import round_up, PROFILE, merge_dicts -from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQSignal, HCQBuffer, HWQueue, HCQArgsState, BumpAllocator -from tinygrad.device import Buffer, BufferSpec, Compiled, Device, ProfileGraphEntry, ProfileGraphEvent -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UOp, Variable -from tinygrad.engine.realize import ExecItem, BufferXfer, CompiledRunner -from tinygrad.engine.jit import MultiGraphRunner - -class HCQGraph(MultiGraphRunner): - def __init__(self, jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int]): - super().__init__(jit_cache, input_rawbuffers, var_vals) - self.devices = list(set(cast(HCQCompiled, d) for ji in jit_cache for d in [Device[cast(Buffer, x).device] for x in ji.bufs])) - - # Replace input buffers with variables. - self.hcq_bufs = [[cast(Buffer, x)._buf for x in ji.bufs] for ji in jit_cache] - self.input_replace_to_var: dict[tuple[int, int], Variable] = {} - - for (j,i), input_idx in self.input_replace.items(): - x = self.input_replace_to_var.setdefault((j,i), UOp.variable(f"input_{input_idx}", 0, 0xffffffffffffffff, dtype=dtypes.uint64)) - self.hcq_bufs[j][i] = HCQBuffer(x, self.hcq_bufs[j][i].size, texture_info=self.hcq_bufs[j][i].texture_info) # Create fake buffer with variable - - # Allocate kernel args. - kernargs_size: dict[Compiled, int] = collections.defaultdict(int) - for ji in jit_cache: - if not isinstance(ji.prg, CompiledRunner): continue - kernargs_size[ji.prg.dev] += round_up(ji.prg._prg.kernargs_alloc_size, 16) - self.kernargs_bufs: dict[Compiled, HCQBuffer] = {dev:dev.allocator._alloc(sz, BufferSpec(cpu_access=True)) for dev,sz in kernargs_size.items()} - - # Fill initial arguments. - self.ji_args: dict[int, HCQArgsState] = {} - - kargs_alloc: dict[Compiled, BumpAllocator] = {dev:BumpAllocator(buf.size) for dev,buf in self.kernargs_bufs.items()} - for j,ji in enumerate(jit_cache): - if not isinstance(ji.prg, CompiledRunner): continue - - argsbuf = self.kernargs_bufs[ji.prg.dev].offset(kargs_alloc[ji.prg.dev].alloc(ji.prg._prg.kernargs_alloc_size, 16)) - self.ji_args[j] = ji.prg._prg.fill_kernargs(self.hcq_bufs[j], ji.prg.p.vars, argsbuf) - - # Schedule Dependencies. - # There are two types of queues on each device: copy and compute. Both must synchronize with all external operations before launching any - # graph-related tasks. This synchronization uses a global timeline signal per device. Within the graph, the compute queue coordinates with - # global operations and sets a kickoff signal. Any queue accessing a buffer from another device waits for this signal from the device’s - # compute queue to ensure exclusive access. The compute queue signals the completion of the graph, synchronizing with the device's copy queue. - self.ji_schedule: dict[int, tuple[HCQCompiled, HWQueue, list, list, HCQSignal, int|None]] = {} - - self.comp_queues: dict[HCQCompiled, HWQueue] = {dev: dev.hw_compute_queue_t() for dev in self.devices} - self.copy_queues: dict[HCQCompiled, HWQueue] = {} # lazy allocation - - self.signals: dict[Any, HCQSignal] = {**{dev: dev.signal_t(value=0) for dev in self.devices}, **{"CPU": self.devices[0].signal_t(value=0)}} - self.kickoff_value: int = 0 - self.kickoff_var = UOp.variable("kickoff_var", 0, 0xffffffff, dtype=dtypes.uint32) - - # When profiling allocate 2 signals for each jit item to measure speed. The jth jit item have signals at 2*j and 2*j+1. - # TODO: This logic might allocate a few extra signals... - self.prof_signals: list[HCQSignal] = [self.devices[0].signal_t() for i in range(len(jit_cache) * 2)] if PROFILE else [] - self.prog_graph_deps: list[list[int]] = [] - self.prof_graph_entries: list[ProfileGraphEntry] = [] - - last_j: dict[HWQueue, int|None] = collections.defaultdict(lambda: None) - queue_access: dict[HWQueue, dict[HWQueue, int|None]] = collections.defaultdict(lambda: collections.defaultdict(lambda: None)) - dev_access: dict[HWQueue, set[HCQCompiled]] = collections.defaultdict(set) - - for dev, queue in self.comp_queues.items(): dev_access[queue].add(dev) - - self.fixedvars: dict[HCQCompiled, dict[Variable, int]] = {} - - for j,ji in enumerate(jit_cache): - enqueue_dev: HCQCompiled = ji.prg.dev if (is_exec_prg:=isinstance(ji.prg, CompiledRunner)) else Device[ji.bufs[1].device] #type:ignore - - # set any fixedvars on the device - self.fixedvars[enqueue_dev] = merge_dicts([self.fixedvars.get(enqueue_dev, {}), ji.fixedvars]) - - if is_exec_prg: - enqueue_queue = self.comp_queues[enqueue_dev] - else: - assert (enqueue_dev.hw_copy_queue_t is not None), "device must implement a copy queue" - enqueue_queue = self.copy_queues.setdefault(enqueue_dev, enqueue_dev.hw_copy_queue_t()) - - out_signal = self.signals.setdefault(enqueue_queue, enqueue_dev.signal_t(value=0)) - - # Get dependencies based on input and output buffers. - rdeps = self._access_resources(ji.bufs, ji.prg.p.outs if is_exec_prg else [0], (enqueue_queue, j + 1)) #type:ignore - - # Update dependencies to include previous kernel in queue. This is required for timeline signals. - opt_deps, deps = [], rdeps + ([(enqueue_queue, prev_ji + 1)] if (prev_ji:=last_j[enqueue_queue]) is not None else []) - - # Optimize dependencies by removing redundant ones. Remove waiting for the value of the queue which is known to be already - # synced with the current queue. - for dep_queue, dep_val in sorted(deps, key=lambda x: x[1], reverse=True): - if (qa:=queue_access[enqueue_queue][dep_queue]) is None or qa < dep_val: - opt_deps.append((self.signals[dep_queue], dep_val)) - queue_access[enqueue_queue][dep_queue] = dep_val - - # Ensure device is ready for use in current context: the graph has initialized the device and it's safe to operate on it within this graph. - for dep_queue, _ in opt_deps: dev_access[enqueue_queue].update(dev_access[dep_queue]) - sync_signals = [(self.signals[d], self.kickoff_var) for b in ji.bufs if (d:=Device[cast(Buffer, b).device]) not in dev_access[enqueue_queue]] - dev_access[enqueue_queue].update(cast(HCQCompiled, Device[cast(Buffer, b).device]) for b in ji.bufs) - - # Remove self-dependency for compute and copy queues. - # For compute, in case of NV, optimize when only 1 same-queue dependency exists, since NV chains 2+ executions in this case, - # eliminating dependency need. - dname = enqueue_dev.device.split(":", 1)[0] - can_opt = dname in {"AMD", "QCOM"} or (dname == "NV" and len(sync_signals) == 0 and len(opt_deps) == 1 and id(opt_deps[0][0]) == id(out_signal)) - if can_opt or isinstance(ji.prg, BufferXfer): opt_deps = [x for x in opt_deps if id(x[0]) != id(out_signal)] - - # Enable necessary signals in the schedule by setting the signal value. - for sig, val in opt_deps: self.ji_schedule[val - 1] = self.ji_schedule[val - 1][:5] + (val,) - self.ji_schedule[j] = (enqueue_dev, enqueue_queue, sync_signals, opt_deps[::-1], out_signal, None if is_exec_prg else (j + 1)) - - # Collect profile information if profiling is enabled. - if PROFILE: - # When execution are chained, we can reuse the end timestamp from the previous command as the start timestamp for the current command. - sig_st = prev_ji * 2 + 1 if len(opt_deps) == 0 and (prev_ji:=last_j[enqueue_queue]) is not None else j * 2 - - # Description based on the command. - prof_ji_desc = ji.prg._prg.name if is_exec_prg else f"{ji.bufs[1].device} -> {ji.bufs[0].device}" # type: ignore - - self.prof_graph_entries.append(ProfileGraphEntry(enqueue_dev.device, prof_ji_desc, sig_st, j * 2 + 1, is_copy=not is_exec_prg)) - self.prog_graph_deps.append([d - 1 for _, d in rdeps]) - - last_j[enqueue_queue] = j - - # Check which signals are used in the profile graph. - self.prof_signal_is_used = [any(ent.st_id == j or ent.en_id == j for ent in self.prof_graph_entries) for j in range(len(self.prof_signals))] - - # Build hardware queues. - self.copy_to_devs: dict[HCQCompiled, set[HCQCompiled]] = {dev: set() for dev in self.devices} - - # Create variable timeline signals for each device. - timeline_sigaddrs = {dev: UOp.variable(f"timeline_sig_{dev.device_id}", 0, 0xffffffffffffffff, dtype=dtypes.uint64) for dev in self.devices} - self.virt_timeline_vals = {dev: UOp.variable(f"timeline_var_{dev.device_id}", 0, 0xffffffff, dtype=dtypes.uint32) for dev in self.devices} - self.virt_timeline_signals = {dev: dev.signal_t(base_buf=HCQBuffer(timeline_sigaddrs[dev], 16), timeline_for_device=dev) for dev in self.devices} - - for dev in self.devices: - self.comp_queues[dev].memory_barrier().wait(self.virt_timeline_signals[dev], self.virt_timeline_vals[dev]) \ - .wait(self.signals['CPU'], self.kickoff_var).signal(self.signals[dev], self.kickoff_var) - - for j,ji in enumerate(jit_cache): - enqueue_dev, enqueue_queue, sync_signals, deps, signal, signal_val = self.ji_schedule[j] - - for sig, val in sync_signals + deps: enqueue_queue.wait(sig, val) - - # Encode waits and start profile timestamp (if needed). - if PROFILE and self.prof_signal_is_used[j * 2]: enqueue_queue.timestamp(self.prof_signals[j * 2]) - - # Encode main commands based on ji type. - if isinstance(ji.prg, CompiledRunner): - enqueue_queue.exec(ji.prg._prg, self.ji_args[j], tuple(ji.prg.p.global_size or (1,1,1)), tuple(ji.prg.p.local_size or (1,1,1))) - elif isinstance(ji.prg, BufferXfer): - dest, src = [cast(Buffer, x) for x in ji.bufs[0:2]] - cast(HCQAllocator, Device[src.device].allocator).map(dest._buf) - - enqueue_queue.copy(self.hcq_bufs[j][0].va_addr, self.hcq_bufs[j][1].va_addr, dest.nbytes) - self.copy_to_devs[cast(HCQCompiled, Device[dest.device])].add(cast(HCQCompiled, Device[src.device])) - - # Encode finish profile timestamp (if needed). - if PROFILE and self.prof_signal_is_used[j * 2 + 1]: enqueue_queue.timestamp(self.prof_signals[j * 2 + 1]) - - if signal_val is not None: enqueue_queue.signal(signal, signal_val) - - for dev in self.devices: - for dep_dev in list(self.copy_to_devs[dev]) + [dev]: - if dep_dev in self.copy_queues: self.comp_queues[dev].wait(self.signals[(copy_q:=self.copy_queues[dep_dev])], cast(int, last_j[copy_q]) + 1) - - self.comp_queues[dev].signal(self.virt_timeline_signals[dev], self.virt_timeline_vals[dev] + 1).bind(dev) - if dev in self.copy_queues: self.copy_queues[dev].bind(dev) - - self.last_timeline: dict[HCQCompiled, tuple[HCQSignal, int]] = {dev: (dev.timeline_signal, 0) for dev in self.devices} - self.queue_signals_to_reset = [self.signals[q] for q in list(self.comp_queues.values()) + list(self.copy_queues.values()) if q in self.signals] - - def __call__(self, input_rawbuffers: list[Buffer], var_vals: dict[Variable, int], wait=False) -> float|None: - # Wait and restore signals - self.kickoff_value += 1 - for dev in self.devices: self.last_timeline[dev][0].wait(self.last_timeline[dev][1]) - for sig in self.queue_signals_to_reset: sig.value = 0 - self.signals['CPU'].value = self.kickoff_value - - if PROFILE and self.kickoff_value > 1: self.collect_timestamps() - - hcq_var_vals = {self.kickoff_var: self.kickoff_value, **var_vals, - **{var: dev.timeline_value - 1 for dev, var in self.virt_timeline_vals.items()}, - **{sig.base_buf.va_addr: dev.timeline_signal.base_buf.va_addr for dev, sig in self.virt_timeline_signals.items()}} - - # Update rawbuffers - for (j,i),input_idx in self.input_replace.items(): hcq_var_vals[self.input_replace_to_var.get((j,i))] = input_rawbuffers[input_idx]._buf.va_addr - - for dev in self.devices: - self.comp_queues[dev].submit(dev, hcq_var_vals_local:=hcq_var_vals|self.fixedvars.get(dev, {})) - if (copy_queue:=self.copy_queues.get(dev, None)) is not None: copy_queue.submit(dev, hcq_var_vals_local) - - self.last_timeline[dev] = (dev.timeline_signal, dev.next_timeline()) - - if wait: - st = time.perf_counter() - for dev in self.devices: self.last_timeline[dev][0].wait(self.last_timeline[dev][1]) - return time.perf_counter() - st - return None - - def collect_timestamps(self): - # NOTE: Append to any device is fine... - self.devices[0].profile_events += [ProfileGraphEvent(self.prof_graph_entries, self.prog_graph_deps, [s.timestamp for s in self.prof_signals])] - - def __del__(self): - for dev in self.devices: self.last_timeline[dev][0].wait(self.last_timeline[dev][1]) - - if PROFILE and self.kickoff_value >= 1: self.collect_timestamps() - - for fdev, buf in self.kernargs_bufs.items(): fdev.allocator._free(buf, BufferSpec(cpu_access=True)) diff --git a/tinygrad/tinygrad/runtime/graph/metal.py b/tinygrad/tinygrad/runtime/graph/metal.py deleted file mode 100644 index d8fd14ab..00000000 --- a/tinygrad/tinygrad/runtime/graph/metal.py +++ /dev/null @@ -1,102 +0,0 @@ -from typing import Any, cast -import ctypes, re -from tinygrad.dtype import dtypes -from tinygrad.helpers import dedup, getenv, merge_dicts -from tinygrad.device import Buffer -from tinygrad.engine.realize import ExecItem, CompiledRunner -from tinygrad.engine.jit import GraphRunner, GraphException -from tinygrad.uop.ops import Variable -from tinygrad.runtime.ops_metal import wait_check, msg, libobjc, to_struct, objc_instance,\ - MTLResourceOptions, cmdbuf_st_time, cmdbuf_en_time, objc_id, to_ns_str - -class MTLIndirectCommandType: - MTLIndirectCommandTypeConcurrentDispatch = (1 << 5) - -class MTLResourceUsage: - MTLResourceUsageRead = 0b01 - MTLResourceUsageWrite = 0b10 - -class MetalGraph(GraphRunner): - def __init__(self, jit_cache: list[ExecItem], input_rawbuffers: list[Buffer], var_vals: dict[Variable, int]): - super().__init__(jit_cache, input_rawbuffers, var_vals) - if not all(isinstance(ji.prg, CompiledRunner) for ji in jit_cache): raise GraphException - - # create metal batch exec - icb_descriptor = msg("new", objc_instance)(libobjc.objc_getClass(b"MTLIndirectCommandBufferDescriptor")) - msg("setCommandTypes:")(icb_descriptor, MTLIndirectCommandType.MTLIndirectCommandTypeConcurrentDispatch) - msg("setInheritBuffers:")(icb_descriptor, False) - msg("setInheritPipelineState:")(icb_descriptor, False) - msg("setMaxKernelBufferBindCount:")(icb_descriptor, 31) - - self.icb = msg("newIndirectCommandBufferWithDescriptor:maxCommandCount:options:", objc_instance)(self.dev.sysdevice, - icb_descriptor, len(jit_cache), MTLResourceOptions.MTLResourceCPUCacheModeDefaultCache) - if self.icb.value is None: raise GraphException("create indirect command buffer failed, does your system support this?") - icb_label = bytes(msg("UTF8String", ctypes.c_char_p)(msg("description", objc_instance)(self.icb))).decode() - self.needs_icb_fix = int((m := re.search(r'AGXG(\d+)XFamily', icb_label)) is None or int(m.group(1)) < 15) # not required on M3+ - - self.fixedvars = merge_dicts([ji.fixedvars for ji in jit_cache]) - self.varlist = self.vars + list(self.fixedvars.keys()) - if len(self.varlist): self.int_buf = self.dev.allocator.alloc(len(self.varlist)*dtypes.int32.itemsize) - - all_pipelines, all_resources = [], [self.int_buf.buf] if len(self.varlist) else [] - for j,ji in enumerate(jit_cache): - prg: CompiledRunner = cast(CompiledRunner, ji.prg) - icb_command = msg("indirectComputeCommandAtIndex:", objc_instance)(self.icb, j) - all_pipelines.append(prg._prg.pipeline_state) - msg("setComputePipelineState:")(icb_command, prg._prg.pipeline_state) - for i,b in enumerate(ji.bufs): - if b is not None and b not in input_rawbuffers: - msg("setKernelBuffer:offset:atIndex:")(icb_command, b._buf.buf, b._buf.offset, i) - all_resources.append(b._buf.buf) - for i,v in enumerate(prg.p.vars): msg("setKernelBuffer:offset:atIndex:")(icb_command, self.int_buf.buf, self.varlist.index(v)*4, len(ji.bufs)+i) - - global_size, local_size = prg.p.launch_dims(var_vals) - msg("concurrentDispatchThreadgroups:threadsPerThreadgroup:")(icb_command, to_struct(*global_size), to_struct(*local_size)) - msg("setBarrier")(icb_command) - - self.all_resources = dedup(all_resources) - self.all_pipelines = dedup(all_pipelines) - self.command_buffer: Any = None - if len(self.varlist): self.int_buf_view = self.dev.allocator._as_buffer(self.int_buf).cast('i') - for var in self.fixedvars: self.int_buf_view[self.varlist.index(var)] = self.fixedvars[var] - self.range = to_struct(0, len(jit_cache)) - - def __call__(self, input_rawbuffers: list[Buffer], var_vals: dict[Variable, int], wait=False) -> float|None: - if self.command_buffer is not None and self.command_buffer in self.dev.mtl_buffers_in_flight: wait_check(self.command_buffer) - - all_resources = dedup(self.all_resources + [input_rawbuffers[input_idx]._buf.buf for input_idx in self.input_replace.values()]) - for (j,i),input_idx in self.input_replace.items(): - computeCommand = msg("indirectComputeCommandAtIndex:", objc_id)(self.icb, j) - msg("setKernelBuffer:offset:atIndex:")(computeCommand, input_rawbuffers[input_idx]._buf.buf, input_rawbuffers[input_idx]._buf.offset, i) - - for j, global_dims, local_dims in self.updated_launch_dims(var_vals): - computeCommand = msg("indirectComputeCommandAtIndex:", objc_id)(self.icb, j) - msg("concurrentDispatchThreadgroups:threadsPerThreadgroup:")(computeCommand, to_struct(*global_dims), to_struct(*local_dims)) - for var in self.vars: self.int_buf_view[self.varlist.index(var)] = var_vals[var] - - command_buffer = msg("commandBuffer", objc_instance)(self.dev.mtl_queue) - encoder = msg("computeCommandEncoder", objc_instance)(command_buffer) - msg("useResources:count:usage:")(encoder, (objc_id * len(all_resources))(*all_resources), len(all_resources), - MTLResourceUsage.MTLResourceUsageRead | MTLResourceUsage.MTLResourceUsageWrite) - - # NOTE: the pipelines likely need to be added to the used resources to fix the crash on M1/M2, but I haven't figured out how - # this is a O(n) hack to get them used. what should work is: - #encoder.useResources_count_usage_(self.all_pipelines, len(self.all_pipelines), Metal.MTLResourceUsageRead) - # but it fails with "Invalid Resource (00000009:kIOGPUCommandBufferCallbackErrorInvalidResource)" - # to repro the crash (which can also crash other running GPU apps), run with FIX_METAL_ICB=0 - if getenv("FIX_METAL_ICB", self.needs_icb_fix): - for ps in self.all_pipelines: - msg("setComputePipelineState:")(encoder, ps) - msg("dispatchThreadgroups:threadsPerThreadgroup:")(encoder, to_struct(0,0,0), to_struct(0,0,0)) - - msg("executeCommandsInBuffer:withRange:")(encoder, self.icb, self.range) - msg("endEncoding")(encoder) - msg("setLabel:")(command_buffer, to_ns_str(f"batched {len(self.jit_cache)}")) - msg("commit")(command_buffer) - self.command_buffer = command_buffer - - self.dev.mtl_buffers_in_flight.append(command_buffer) - if wait: - wait_check(command_buffer) - return cmdbuf_en_time(command_buffer) - cmdbuf_st_time(command_buffer) - return None diff --git a/tinygrad/tinygrad/runtime/graph/remote.py b/tinygrad/tinygrad/runtime/graph/remote.py deleted file mode 100644 index 04c6dbdb..00000000 --- a/tinygrad/tinygrad/runtime/graph/remote.py +++ /dev/null @@ -1,40 +0,0 @@ -from tinygrad.uop.ops import Variable -from tinygrad.engine.jit import GraphRunner, MultiGraphRunner, GraphException -from tinygrad.engine.realize import CompiledRunner, BufferXfer, ExecItem -from tinygrad.device import Device, Buffer -from tinygrad.runtime.ops_remote import RemoteDevice, GraphComputeItem, Transfer, GraphAlloc, GraphFree, GraphExec -from tinygrad.helpers import unwrap, flatten, dedup, all_same -from typing import cast - -class RemoteGraph(GraphRunner): - def __init__(self, jit_cache: list[ExecItem], rawbufs: list[Buffer], var_vals: dict[Variable, int]): - super().__init__(jit_cache, rawbufs, var_vals) - self.devices = dedup(flatten([[Device[unwrap(buf).device] for buf in ji.bufs] for ji in jit_cache])) - if not all_same([d.conn for d in self.devices]): raise GraphException(f"Cross-host remote graph is not supported ({self.devices})") - self.iids = sorted(self.input_replace.values()) - def _process_ji(ji: ExecItem): - match ji.prg: - case CompiledRunner(): - return GraphComputeItem(ji.prg.dev.session, ji.prg._prg.name, ji.prg._prg.datahash, tuple(unwrap(buf)._buf for buf in ji.bufs), - tuple(ji.prg.p.vars), ji.fixedvars, tuple(ji.prg.p.ins), tuple(ji.prg.p.outs), - tuple(ji.prg.p.global_size) if ji.prg.p.global_size is not None else None, - tuple(ji.prg.p.local_size) if ji.prg.p.local_size is not None else None) - case BufferXfer(): - dest, src = ji.bufs[0:2] - assert dest is not None and src is not None, ji - return Transfer(session=cast(RemoteDevice, Device[dest.device]).session, buffer_num=dest._buf, - ssession=cast(RemoteDevice, Device[src.device]).session, sbuffer_num=src._buf) - self.graph_num = next(self.devices[0].graph_num) - self.devices[0].q(GraphAlloc(self.graph_num, tuple(_process_ji(ji) for ji in jit_cache), self.map_rawbufs(rawbufs), var_vals)) - - def __del__(self): - self.devices[0].q(GraphFree(self.graph_num)) - - def map_rawbufs(self, rawbufs:list[Buffer]): - return tuple((cast(RemoteDevice, Device[rawbufs[i].device]).session, rawbufs[i]._buf) for i in self.iids) - - def __call__(self, rawbufs: list[Buffer], var_vals: dict[Variable, int], wait=False): - self.devices[0].q(GraphExec(self.graph_num, self.map_rawbufs(rawbufs), var_vals, wait)) - if wait: return float(self.devices[0].conn.batch_submit()) - -class RemoteMultiGraph(RemoteGraph, MultiGraphRunner): pass diff --git a/tinygrad/tinygrad/runtime/ops_amd.py b/tinygrad/tinygrad/runtime/ops_amd.py deleted file mode 100644 index 513dbf8e..00000000 --- a/tinygrad/tinygrad/runtime/ops_amd.py +++ /dev/null @@ -1,981 +0,0 @@ -from __future__ import annotations -from typing import Any, cast, ClassVar -import os, ctypes, ctypes.util, struct, hashlib, functools, importlib, mmap, errno, array, contextlib, sys, select, weakref, traceback -assert sys.platform != 'win32' -from dataclasses import dataclass -from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQSignal, HCQProgram, FileIOInterface -from tinygrad.runtime.support.hcq import MMIOInterface -from tinygrad.uop.ops import sint -from tinygrad.device import Compiled, ProfileEvent, BufferSpec, CPUProgram, PROFILE -from tinygrad.helpers import getenv, to_mv, round_up, data64_le, all_same, flatten, DEBUG, OSX -from tinygrad.renderer.cstyle import AMDRenderer -from tinygrad.renderer.llvmir import AMDLLVMRenderer -from tinygrad.runtime.autogen import kfd, hsa, libc, pci, vfio, sqtt -from tinygrad.runtime.autogen.am import am -from tinygrad.runtime.support.compiler_amd import HIPCompiler, AMDLLVMCompiler -from tinygrad.runtime.support.elf import elf_loader -from tinygrad.runtime.support.am.amdev import AMDev, AMMapping -from tinygrad.runtime.support.amd import AMDReg, AMDIP, import_module, setup_pci_bars -from tinygrad.runtime.support.usb import ASM24Controller, USBMMIOInterface -if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 # pylint: disable=unused-import - -EVENT_INDEX_PARTIAL_FLUSH = 4 # based on a comment in nvd.h -WAIT_REG_MEM_FUNCTION_EQ = 3 # == -WAIT_REG_MEM_FUNCTION_NEQ = 4 # != -WAIT_REG_MEM_FUNCTION_GEQ = 5 # >= - -class AMDSignal(HCQSignal): - def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): - super().__init__(base_buf, **kwargs, timestamp_divider=100, dev_t=AMDDevice) - - def _sleep(self, time_spent_waiting_ms:int): - # Resonable to sleep for long workloads (which take more than 2s) and only timeline signals. - if time_spent_waiting_ms > 2000 and self.timeline_for_device is not None: self.timeline_for_device.dev_iface.sleep(200) - -class AMDComputeQueue(HWQueue): - def __init__(self, dev:AMDDevice): - self.dev, self.soc, self.pm4, self.gc, self.nbio = dev, dev.soc, dev.pm4, dev.gc, dev.nbio - super().__init__() - - def __del__(self): - if self.binded_device is not None: - self.binded_device.allocator.free(self.hw_page, self.hw_page.size, BufferSpec(cpu_access=True, nolru=True, uncached=True)) - - def pkt3(self, cmd, *vals): self.q(self.pm4.PACKET3(cmd, len(vals) - 1), *vals) - - def wreg(self, reg:AMDReg, *args:sint, **kwargs:int): - if bool(args) == bool(kwargs): raise RuntimeError('One (and only one) of *args or **kwargs must be specified') - if self.pm4.PACKET3_SET_SH_REG_START <= reg.addr < self.pm4.PACKET3_SET_SH_REG_END: - set_packet, set_packet_start = self.pm4.PACKET3_SET_SH_REG, self.pm4.PACKET3_SET_SH_REG_START - elif self.pm4.PACKET3_SET_UCONFIG_REG_START <= reg.addr < self.pm4.PACKET3_SET_UCONFIG_REG_START + 2**16-1: - set_packet, set_packet_start = self.pm4.PACKET3_SET_UCONFIG_REG, self.pm4.PACKET3_SET_UCONFIG_REG_START - else: raise RuntimeError(f'Cannot set {reg.name} ({reg.addr}) via pm4 packet') - self.pkt3(set_packet, reg.addr - set_packet_start, *(args or (reg.encode(**kwargs),))) - - @contextlib.contextmanager - def pred_exec(self, xcc_mask:int): - if self.dev.xccs > 1: - self.pkt3(self.pm4.PACKET3_PRED_EXEC, xcc_mask << 24) - prev_len = len(self._q) - yield - if self.dev.xccs > 1: - self._q[prev_len-1] |= (len(self._q) - prev_len) - - def wait_reg_mem(self, value, mask=0xffffffff, mem=None, reg_req=None, reg_done=None): - wrm_info_dw = self.pm4.WAIT_REG_MEM_MEM_SPACE(int(mem is not None)) | self.pm4.WAIT_REG_MEM_OPERATION(int(mem is None)) \ - | self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_GEQ) | self.pm4.WAIT_REG_MEM_ENGINE(0) - - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, wrm_info_dw, *(data64_le(mem) if mem is not None else (reg_req, reg_done)), value, mask, 4) - - def acquire_mem(self, addr=0x0, sz=(1 << 64)-1, gli=1, glm=1, glk=1, glv=1, gl1=1, gl2=1): - if self.dev.target >= (10,0,0): - cache_flags_dw = self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(gli) \ - | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(glm) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(glm) \ - | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(glk) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(glk) \ - | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(glv) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(gl1) \ - | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(gl2) | self.pm4.PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(gl2) - - self.pkt3(self.pm4.PACKET3_ACQUIRE_MEM, 0, *data64_le(sz), *data64_le(addr), 0, cache_flags_dw) - else: - cp_coher_cntl = self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(gli) | \ - self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(glk) | \ - self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(gl2) | \ - self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(gl1) | \ - self.pm4.PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(gl2) - self.pkt3(self.pm4.PACKET3_ACQUIRE_MEM, cp_coher_cntl, *data64_le(sz), *data64_le(addr), 0x0000000A) - - def release_mem(self, address=0x0, value=0, data_sel=0, int_sel=2, ctxid=0, cache_flush=False): - if self.dev.target >= (10,0,0): - cache_flags_dw = 0 if not cache_flush else (self.pm4.PACKET3_RELEASE_MEM_GCR_GLV_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL1_INV \ - | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_WB \ - | self.pm4.PACKET3_RELEASE_MEM_GCR_GLM_INV | self.pm4.PACKET3_RELEASE_MEM_GCR_GL2_WB | self.pm4.PACKET3_RELEASE_MEM_GCR_SEQ) - - event_dw = self.pm4.PACKET3_RELEASE_MEM_EVENT_TYPE(self.pm4.CACHE_FLUSH_AND_INV_TS_EVENT) \ - | self.pm4.PACKET3_RELEASE_MEM_EVENT_INDEX(self.pm4.event_index__mec_release_mem__end_of_pipe) - - memsel_dw = self.pm4.PACKET3_RELEASE_MEM_DATA_SEL(data_sel) | self.pm4.PACKET3_RELEASE_MEM_INT_SEL(int_sel) \ - | self.pm4.PACKET3_RELEASE_MEM_DST_SEL(0) - else: - cache_flags_dw = 0 if not cache_flush else (self.pm4.EOP_TC_WB_ACTION_EN | self.pm4.EOP_TC_NC_ACTION_EN) - - event_dw = self.pm4.EVENT_TYPE(self.pm4.CACHE_FLUSH_AND_INV_TS_EVENT) | self.pm4.EVENT_INDEX(self.pm4.event_index__mec_release_mem__end_of_pipe) - - memsel_dw = self.pm4.DATA_SEL(data_sel) | self.pm4.INT_SEL(int_sel) - - ctxid = 0 - - self.pkt3(self.pm4.PACKET3_RELEASE_MEM, event_dw | cache_flags_dw, memsel_dw, *data64_le(address), *data64_le(value), ctxid) - - def xcc_barrier(self): - if self.dev.xcc_sync is None: return self - assert self.dev.xccs == 8, 'only 8 XCCs supported' - a, b = self.dev.xcc_sync - mem_eq = self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ) | self.pm4.WAIT_REG_MEM_MEM_SPACE(1) - self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(a.value_addr), *data64_le(1), *data64_le(0), 0x10) # a += 1 - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(a.value_addr), 0, 0b111, 0x80) # a == 0 (mod 8) via bitmask - self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(b.value_addr), *data64_le(1), *data64_le(0), 0x10) # b += 1 - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(b.value_addr), 0, 0b111, 0x80) # b == 0 (mod 8) via bitmask - return self - - def memory_barrier(self): - pf = '' if self.nbio.version[0] == 2 else '0' if self.nbio.version[:2] != (7, 11) else '1' - self.wait_reg_mem(reg_req=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_REQ').addr, - reg_done=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_DONE').addr, value=0xffffffff) - self.acquire_mem() - return self - - def xcc_config(self): - self.wreg(self.gc.regCOMPUTE_TG_CHUNK_SIZE, 1) - for xcc_id in range(self.dev.xccs): - with self.pred_exec(xcc_mask=1 << xcc_id): - self.wreg(self.dev.regCOMPUTE_CURRENT_LOGIC_XCC_ID, xcc_id) - return self - - def spi_config(self, tracing:bool): - self.wreg(self.gc.regSPI_CONFIG_CNTL, ps_pkr_priority_cntl=3, exp_priority_order=3, gpr_write_priority=0x2c688, - enable_sqg_bop_events=int(tracing), enable_sqg_top_events=int(tracing)) - - ### SQTT ### - - def sqtt_userdata(self, data, *extra_dwords): - data_ints = [x[0] for x in struct.iter_unpack('>12) - self.wreg(self.gc.regSQ_THREAD_TRACE_BUF0_SIZE, base_hi=buf0_hi, size=buf0s[se].size>>12) - self.wreg(self.gc.regSQ_THREAD_TRACE_BUF0_BASE, base_lo=buf0_lo) - # NOTE: SQTT can only trace instructions on one simd per se, this selects first simd in first wgp in first sa. - # For RGP to display instruction trace it has to see it on first SE. Howerver ACE/MEC/whatever does the dispatching starting with second se, - # and on amdgpu/non-AM it also does weird things with dispatch order inside se: around 7 times out of 10 it starts from the last cu, but - # sometimes not, especially if the kernel has more than one wavefront which means that kernels with small global size might get unlucky and - # be dispatched on something else and not be seen in instruction tracing tab. You can force the wavefronts of a kernel to be dispatched on the - # CUs you want to by disabling other CUs via bits in regCOMPUTE_STATIC_THREAD_MGMT_SE and trace even kernels that only have one wavefront. - self.wreg(self.gc.regSQ_THREAD_TRACE_MASK, wtype_include=self.soc.SQ_TT_WTYPE_INCLUDE_CS_BIT, simd_sel=0, wgp_sel=0, sa_sel=0) - REG_INCLUDE = self.soc.SQ_TT_TOKEN_MASK_SQDEC_BIT | self.soc.SQ_TT_TOKEN_MASK_SHDEC_BIT | self.soc.SQ_TT_TOKEN_MASK_GFXUDEC_BIT | \ - self.soc.SQ_TT_TOKEN_MASK_COMP_BIT | self.soc.SQ_TT_TOKEN_MASK_CONTEXT_BIT | self.soc.SQ_TT_TOKEN_MASK_CONTEXT_BIT - TOKEN_EXCLUDE = 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT - if not (se_mask >> se) & 0b1: - TOKEN_EXCLUDE |= 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT | 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT | \ - 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT | 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT | \ - 1 << self.soc.SQ_TT_TOKEN_EXCLUDE_INST_SHIFT - self.wreg(self.gc.regSQ_THREAD_TRACE_TOKEN_MASK, reg_include=REG_INCLUDE, token_exclude=TOKEN_EXCLUDE, bop_events_token_include=1) - # Enable SQTT - self.sqtt_config(tracing=True) - # Restore global broadcasting - self.wreg(self.gc.regGRBM_GFX_INDEX, se_broadcast_writes=1, sa_broadcast_writes=1, instance_broadcast_writes=1) - self.wreg(self.gc.regCOMPUTE_THREAD_TRACE_ENABLE, 1) - self.memory_barrier() - return self - - # Magic values from src/amd/common/ac_sqtt.c:ac_sqtt_emit_stop and src/amd/common/ac_sqtt.c:ac_sqtt_emit_wait - def sqtt_stop(self, ses: int, wptrs: HCQBuffer): - self.memory_barrier() - # Start shutting everything down - self.wreg(self.gc.regCOMPUTE_THREAD_TRACE_ENABLE, 0) - self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.THREAD_TRACE_FINISH) | self.pm4.EVENT_INDEX(0)) - # For each SE wait for finish to complete and copy regSQ_THREAD_TRACE_WPTR to know where in the buffer trace data ends - for se in range(ses): - self.wreg(self.gc.regGRBM_GFX_INDEX, se_index=se, instance_broadcast_writes=1) - # Wait for FINISH_PENDING==0 - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_pending'), 4) - # Wait for FINISH_DONE!=0 - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_NEQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_done'), 4) - # Disable SQTT - self.sqtt_config(tracing=False) - # Wait for BUSY==0 - self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('busy'), 4) - # Copy WPTR to memory (src_sel = perf, dst_sel = tc_l2, wr_confirm = True) - self.pkt3(self.pm4.PACKET3_COPY_DATA, 1 << 20 | 2 << 8 | 4, self.gc.regSQ_THREAD_TRACE_WPTR.addr, 0, *data64_le(wptrs.va_addr+(se*4))) - # Restore global broadcasting - self.wreg(self.gc.regGRBM_GFX_INDEX, se_broadcast_writes=1, sa_broadcast_writes=1, instance_broadcast_writes=1) - self.spi_config(tracing=False) - self.memory_barrier() - return self - - def sqtt_prg_marker(self, prg:AMDProgram, global_size:tuple[sint, ...]): - BIND_POINT_COMPUTE = 1 - - self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_pipeline_bind( - _0=sqtt.union_rgp_sqtt_marker_pipeline_bind_0(_0=sqtt.struct_rgp_sqtt_marker_pipeline_bind_0_0( - identifier=sqtt.RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE, bind_point=BIND_POINT_COMPUTE)), - _1=sqtt.union_rgp_sqtt_marker_pipeline_bind_1(api_pso_hash=data64_le(prg.libhash[0])))) - - self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_event( - _0=sqtt.union_rgp_sqtt_marker_event_0(_0=sqtt.struct_rgp_sqtt_marker_event_0_0(has_thread_dims=1)), - _2=sqtt.union_rgp_sqtt_marker_event_2(cmd_id=prg.dev.cmd_id)), *global_size) - - prg.dev.cmd_id += 1 - - def exec(self, prg:AMDProgram, args_state:CLikeArgsState, global_size:tuple[sint, ...], local_size:tuple[sint, ...]): - self.bind_args_state(args_state) - - self.acquire_mem(gli=0, gl2=0) - - user_regs = [] - if prg.enable_private_segment_sgpr: - assert self.dev.xccs == 1, "Only architected flat scratch is suppored on multi-xcc" - scratch_hilo = data64_le(prg.dev.scratch.va_addr) - # sgpr word1 bit31 enables swizzle - # sgpr word3 = 0x14 << 12 | 2 << 28 | 2 << 21 | 1 << 23 - user_regs = [scratch_hilo[0], scratch_hilo[1] | 1 << 31, 0xffffffff, 0x20c14000] - - if prg.enable_dispatch_ptr: - dp = (dp_t:=hsa.hsa_kernel_dispatch_packet_t).from_address(cast(int, (disp_buf:=args_state.buf.offset(prg.kernargs_segment_size)).va_addr)) - - self.bind_sints(*local_size, mem=disp_buf.cpu_view(), struct_t=dp_t, start_field='workgroup_size_x', fmt='H') - self.bind_sints(*[g*l for g,l in zip(global_size, local_size)], mem=disp_buf.cpu_view(), struct_t=dp_t, start_field='grid_size_x', fmt='I') - dp.group_segment_size, dp.private_segment_size, dp.kernarg_address = prg.group_segment_size, prg.private_segment_size, args_state.buf.va_addr - user_regs += [*data64_le(disp_buf.va_addr)] - - user_regs += [*data64_le(args_state.buf.va_addr)] - - if prg.dev.sqtt_enabled: self.sqtt_prg_marker(prg, global_size) - - self.wreg(self.gc.regCOMPUTE_PGM_LO, *data64_le(prg.prog_addr >> 8)) - self.wreg(self.gc.regCOMPUTE_PGM_RSRC1, prg.rsrc1, prg.rsrc2) - self.wreg(self.gc.regCOMPUTE_PGM_RSRC3, prg.rsrc3) - self.wreg(self.gc.regCOMPUTE_TMPRING_SIZE, prg.dev.tmpring_size) - - if prg.dev.has_scratch_base_registers: - for xcc_id in range(self.dev.xccs): - with self.pred_exec(xcc_mask=1<> 8)) - - if (10,0,0) <= prg.dev.target < (11,0,0): self.wreg(self.gc.mmCP_COHER_START_DELAY, 0x20) - - self.wreg(self.gc.regCOMPUTE_RESTART_X, 0, 0, 0) - self.wreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xFFFFFFFF, 0xFFFFFFFF) - self.wreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE2, 0xFFFFFFFF, 0xFFFFFFFF) - if prg.dev.target >= (11,0,0): self.wreg(self.gc.regCOMPUTE_STATIC_THREAD_MGMT_SE4, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) - - self.wreg(self.gc.regCOMPUTE_USER_DATA_0, *user_regs) - self.wreg(self.gc.regCOMPUTE_RESOURCE_LIMITS, 0) - - self.wreg(self.gc.regCOMPUTE_START_X, 0, 0, 0, *local_size, 0, 0) - - gfx10p = {'cs_w32_en': int(prg.wave32)} if prg.dev.target >= (10,0,0) else {} - DISPATCH_INITIATOR = self.gc.regCOMPUTE_DISPATCH_INITIATOR.encode(**gfx10p, force_start_at_000=1, compute_shader_en=1) - self.pkt3(self.pm4.PACKET3_DISPATCH_DIRECT, *global_size, DISPATCH_INITIATOR) - - if prg.dev.sqtt_enabled: self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.THREAD_TRACE_MARKER) | self.pm4.EVENT_INDEX(0)) - self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.CS_PARTIAL_FLUSH) | self.pm4.EVENT_INDEX(EVENT_INDEX_PARTIAL_FLUSH)) - - if self.dev.xccs > 1: - self.release_mem(cache_flush=True) - self.acquire_mem(gli=0) - self.xcc_barrier() - return self - - def wait(self, signal:AMDSignal, value:sint=0): - self.wait_reg_mem(mem=signal.value_addr, value=value, mask=0xffffffff) - if self.dev.xccs > 1: self.xcc_barrier() - return self - - def timestamp(self, signal:AMDSignal): - with self.pred_exec(xcc_mask=0b1): - self.release_mem(signal.timestamp_addr, 0, self.pm4.data_sel__mec_release_mem__send_gpu_clock_counter, self.pm4.int_sel__mec_release_mem__none) - return self - - def signal(self, signal:AMDSignal, value:sint=0): - with self.pred_exec(xcc_mask=0b1): - # NOTE: this needs an EOP buffer on the queue or it will NULL pointer - self.release_mem(signal.value_addr, value, self.pm4.data_sel__mec_release_mem__send_32_bit_low, - self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) - - if (dev:=signal.timeline_for_device) is not None and not dev.is_am(): - self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, self.pm4.data_sel__mec_release_mem__send_32_bit_low, - self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) - return self - - def bind(self, dev:AMDDevice): - self.binded_device = dev - self.hw_page = dev.allocator.alloc(len(self._q) * 4, BufferSpec(cpu_access=True, nolru=True, uncached=True)) - hw_view = self.hw_page.cpu_view().view(fmt='I') - for i, value in enumerate(self._q): hw_view[i] = value - - self.indirect_cmd = [self.pm4.PACKET3(self.pm4.PACKET3_INDIRECT_BUFFER, 2), *data64_le(self.hw_page.va_addr), - len(self._q) | self.pm4.INDIRECT_BUFFER_VALID] - self._q = hw_view - return self - - def _submit(self, dev:AMDDevice): - cmds = self.indirect_cmd if dev == self.binded_device else self._q - # WORKAROUND: PACKET3_PRED_EXEC doesn't work in rings, only in IBs, create a fake IB inside a ring to work around that - if self.dev.xccs > 1 and dev != self.binded_device: - ib_end = ((dev.compute_queue.put_value + 5) % len(dev.compute_queue.ring)) + len(cmds) - ib_pad = len(dev.compute_queue.ring) - (ib_end - len(cmds)) if ib_end > len(dev.compute_queue.ring) else 0 - ib_ptr = dev.compute_queue.ring.addr + ((dev.compute_queue.put_value + 5 + ib_pad) % len(dev.compute_queue.ring)) * 4 - cmds = [self.pm4.PACKET3(self.pm4.PACKET3_INDIRECT_BUFFER, 2), *data64_le(ib_ptr), len(cmds) | self.pm4.INDIRECT_BUFFER_VALID, - self.pm4.PACKET3(self.pm4.PACKET3_NOP, ib_pad + len(cmds) - 1), *((0,) * ib_pad), *cmds] - - for i, value in enumerate(cmds): dev.compute_queue.ring[(dev.compute_queue.put_value + i) % len(dev.compute_queue.ring)] = value - - dev.compute_queue.put_value += len(cmds) - dev.compute_queue.signal_doorbell(dev) - -class AMDCopyQueue(HWQueue): - def __init__(self, dev, max_copy_size=0x40000000): - self.dev, self.sdma, self.internal_cmd_sizes, self.max_copy_size = dev, dev.sdma, [], max_copy_size - super().__init__() - - def q(self, *arr): - super().q(*arr) - self.internal_cmd_sizes.append(len(arr)) - - def copy(self, dest:sint, src:sint, copy_size:int): - copied, copy_commands = 0, (copy_size + self.max_copy_size - 1) // self.max_copy_size - - for _ in range(copy_commands): - step_copy_size = min(copy_size - copied, self.max_copy_size) - - self.q(self.sdma.SDMA_OP_COPY | self.sdma.SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(self.sdma.SDMA_SUBOP_COPY_LINEAR), - self.sdma.SDMA_PKT_COPY_LINEAR_COUNT_COUNT(step_copy_size - 1), 0, *data64_le(src + copied), *data64_le(dest + copied)) - - copied += step_copy_size - return self - - def signal(self, signal:AMDSignal, value:sint=0): - fence_flags = self.sdma.SDMA_PKT_FENCE_HEADER_MTYPE(3) if self.dev.target >= (10,0,0) else 0 - self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(signal.value_addr), value) - - if (dev:=signal.timeline_for_device) is not None and not dev.is_am(): - self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id) - self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(dev.queue_event.event_id)) - elif dev is not None and dev.is_am(): self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)) - - return self - - def wait(self, signal:AMDSignal, value:sint=0): - self.q(self.sdma.SDMA_OP_POLL_REGMEM | self.sdma.SDMA_PKT_POLL_REGMEM_HEADER_FUNC(WAIT_REG_MEM_FUNCTION_GEQ) | \ - self.sdma.SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1), *data64_le(signal.value_addr), value, 0xffffffff, - self.sdma.SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(0x04) | self.sdma.SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)) - return self - - def timestamp(self, signal:AMDSignal): - self.q(self.sdma.SDMA_OP_TIMESTAMP | self.sdma.SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(self.sdma.SDMA_SUBOP_TIMESTAMP_GET_GLOBAL), - *data64_le(signal.timestamp_addr)) - return self - - def bind(self, dev:AMDDevice): - if not getenv("AMD_SDMA_BIND", 0) or not dev.is_am(): return - - self.binded_device = dev - self.hw_page = dev.allocator.alloc((qsz:=round_up(len(self._q), 8)) * 4, BufferSpec(cpu_access=True, nolru=True, uncached=True)) - hw_view = self.hw_page.cpu_view().view(fmt='I') - for i in range(qsz): hw_view[i] = self._q[i] if i < len(self._q) else 0 - - self.indirect_cmd = [self.sdma.SDMA_OP_INDIRECT | self.sdma.SDMA_PKT_INDIRECT_HEADER_VMID(0), *data64_le(self.hw_page.va_addr), qsz, - *data64_le(0)] - self._q, self.cmd_sizes = hw_view, [len(self.indirect_cmd)] - - def _submit(self, dev:AMDDevice): - # usb devices run in single-step mode, so they can't overrun the queue. - if not dev.is_usb() and dev.sdma_queue.put_value - dev.sdma_queue.read_ptr > dev.sdma_queue.ring.nbytes: raise RuntimeError("SDMA queue overrun") - - if self.binded_device == dev: - # An IB packet must end on a 8 DW boundary. - add = (8 - (((dev.sdma_queue.put_value % 32) // 4) + len(self.indirect_cmd) % 8)) % 8 - cmds, cmd_sizes = ([0] * add) + self.indirect_cmd, [len(self.indirect_cmd) + add] - - if len(cmds) * 4 >= (dev.sdma_queue.ring.nbytes - dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes): - cmds, cmd_sizes = [0, 0] + self.indirect_cmd, [8] - else: cmds, cmd_sizes = self._q, self.internal_cmd_sizes - - tail_blit_dword = 0 - for cmdsz in cmd_sizes: - if (tail_blit_dword + cmdsz) * 4 >= dev.sdma_queue.ring.nbytes - dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes: break - tail_blit_dword += cmdsz - - # Force align of submits to hit our usb layer write cache. - if dev.is_usb() and (rem_packet_cnt := len(cmds) - tail_blit_dword) > 0: tail_blit_dword = 0 - - start_idx = (dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes) // 4 - dev.sdma_queue.ring[start_idx : start_idx + tail_blit_dword] = array.array('I', cmds[:tail_blit_dword]) - dev.sdma_queue.put_value += tail_blit_dword * 4 - - if (rem_packet_cnt := len(cmds) - tail_blit_dword) > 0: - zero_fill = dev.sdma_queue.ring.nbytes - dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes - dev.sdma_queue.ring.view(dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes, zero_fill, fmt='B')[:] = bytes(zero_fill) - dev.sdma_queue.put_value += zero_fill - - dev.sdma_queue.ring[0:rem_packet_cnt] = array.array('I', cmds[tail_blit_dword:]) - dev.sdma_queue.put_value += rem_packet_cnt * 4 - - dev.sdma_queue.signal_doorbell(dev) - -class AMDProgram(HCQProgram): - def __init__(self, dev:AMDDevice, name:str, lib:bytes): - # TODO; this API needs the type signature of the function and global_size/local_size - self.dev, self.name, self.lib = dev, name, lib - - image, sections, _ = elf_loader(self.lib) - self.lib_gpu = self.dev.allocator.alloc(round_up(image.nbytes, 0x1000), buf_spec:=BufferSpec(cpu_access=True, nolru=True)) - self.dev.allocator._copyin(self.lib_gpu, image) - self.dev.synchronize() - - rodata_entry = next((sh.header.sh_addr for sh in sections if sh.name == ".rodata"), -1) - text_entry = next((sh.header.sh_addr for sh in sections if sh.name == ".text"), -1) - assert rodata_entry >= 0 and text_entry >= 0, ".text or .rodata section not found" - self.group_segment_size = image[rodata_entry:rodata_entry+4].cast("I")[0] - self.private_segment_size = image[rodata_entry+4:rodata_entry+8].cast("I")[0] - self.kernargs_segment_size = image[rodata_entry+8:rodata_entry+12].cast("I")[0] - lds_size = ((self.group_segment_size + 511) // 512) & 0x1FF - if lds_size > (self.dev.dev_iface.props['lds_size_in_kb'] * 1024) // 512: raise RuntimeError("Too many resources requested: group_segment_size") - - # Ensure scratch size - self.dev._ensure_has_local_memory(self.private_segment_size) - - # NOTE: this is wrong, it's not this object. pad it, since it might be smaller than the struct - code = hsa.amd_kernel_code_t.from_buffer_copy(bytes(image[rodata_entry:rodata_entry+256]) + b'\x00'*256) - self.wave32: bool = code.kernel_code_properties & 0x400 == 0x400 - - # Set rsrc1.priv=1 on gfx11 to workaround cwsr. - self.rsrc1: int = code.compute_pgm_rsrc1 | ((1 << 20) if (11,0,0) <= self.dev.target < (12,0,0) else 0) - self.rsrc2: int = code.compute_pgm_rsrc2 | (lds_size << 15) - self.rsrc3: int = image[rodata_entry+44:rodata_entry+48].cast("I")[0] # NOTE: kernel descriptor, not in amd_kernel_code_t struct - self.prog_addr: int = self.lib_gpu.va_addr + rodata_entry + code.kernel_code_entry_byte_offset - if code.kernel_code_entry_byte_offset == 0: self.prog_addr = self.lib_gpu.va_addr + text_entry - # Some programs use hsa_kernel_dispatch_packet_t to read workgroup sizes during execution. - # The packet is represented as a pointer and set up in SGPRs. Space for the packet is allocated as part of the kernel arguments. - self.enable_dispatch_ptr: int = code.kernel_code_properties & hsa.AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR - self.enable_private_segment_sgpr: int = code.kernel_code_properties & hsa.AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER - additional_alloc_sz = ctypes.sizeof(hsa.hsa_kernel_dispatch_packet_t) if self.enable_dispatch_ptr else 0 - - if dev.sqtt_enabled: self.libhash: tuple[int, int] = struct.unpack(' HCQBuffer: - return self.dev.dev_iface.alloc(size, host=options.host, uncached=options.uncached, cpu_access=options.cpu_access) - - def _free(self, opaque, options:BufferSpec): - try: - self.dev.synchronize() - self.dev.dev_iface.free(opaque) - except AttributeError: pass - - def map(self, buf:HCQBuffer): self.dev.dev_iface.map(buf._base if buf._base is not None else buf) - -MAP_FIXED, MAP_NORESERVE, MAP_LOCKED, MAP_POPULATE = 0x10, 0x400, 0 if OSX else 0x2000, getattr(mmap, "MAP_POPULATE", 0 if OSX else 0x008000) - -@dataclass(frozen=True) -class ProfileSQTTEvent(ProfileEvent): device:str; se:int; blob:bytes; itrace:bool # noqa: E702 - -@dataclass -class AMDQueueDesc: - ring: MMIOInterface - read_ptrs: list[MMIOInterface] - write_ptrs: list[MMIOInterface] - doorbells: list[MMIOInterface] - put_value: int = 0 - - @property - def read_ptr(self): return min(p[0] for p in self.read_ptrs) - - @classmethod - def multi(cls, *queues: AMDQueueDesc): - assert all_same([(q.ring.addr, q.put_value) for q in queues]), f"All queues must have the same ring and put_value: {queues}" - return cls(ring=queues[0].ring, put_value=queues[0].put_value, doorbells=flatten(q.doorbells for q in queues), - read_ptrs=flatten(q.read_ptrs for q in queues), write_ptrs=flatten(q.write_ptrs for q in queues)) - - def signal_doorbell(self, dev): - for write_ptr in self.write_ptrs: write_ptr[0] = self.put_value - - # Ensure all prior writes are visible to the GPU. - if CPUProgram.atomic_lib is not None: CPUProgram.atomic_lib.atomic_thread_fence(__ATOMIC_SEQ_CST:=5) - - # Flush hdp if queue is in dev mem. - if dev.is_am() and not dev.is_usb(): dev.dev_iface.adev.gmc.flush_hdp() - for doorbell in self.doorbells: doorbell[0] = self.put_value - -class KFDIface: - kfd:FileIOInterface|None = None - event_page:HCQBuffer|None = None - gpus:list[FileIOInterface] = [] - - def _is_usable_gpu(self, gpu_id): - with contextlib.suppress(OSError): return int(gpu_id.read()) != 0 - return False - - def __init__(self, dev, device_id): - self.dev = dev - - kfd_topo_path = "/sys/devices/virtual/kfd/kfd/topology/nodes" - - # Initialize KFD interface during first run - if KFDIface.kfd is None: - KFDIface.kfd = FileIOInterface("/dev/kfd", os.O_RDWR) - gpus = [g for g in FileIOInterface(kfd_topo_path).listdir() if self._is_usable_gpu(FileIOInterface(f"{kfd_topo_path}/{g}/gpu_id"))] - gpus = sorted(gpus, key=lambda x: int(x.split('/')[-1])) - visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('HIP_VISIBLE_DEVICES', ''))).split(',') if x.strip()] - KFDIface.gpus = [gpus[x] for x in visible_devices] if visible_devices else gpus - - if device_id >= len(KFDIface.gpus): raise RuntimeError(f"No device found for {device_id}. Requesting more devices than the system has?") - - self.gpu_id = int(FileIOInterface(f"{kfd_topo_path}/{KFDIface.gpus[device_id]}/gpu_id").read()) - self.props = {(p:=l.split())[0]: int(p[1]) for l in FileIOInterface(f"{kfd_topo_path}/{KFDIface.gpus[device_id]}/properties").read().splitlines()} - ip_base = f"/sys/class/drm/renderD{self.props['drm_render_minor']}/device/ip_discovery/die/0" - id2ip = {am.GC_HWID: am.GC_HWIP, am.SDMA0_HWID: am.SDMA0_HWIP, am.NBIF_HWID: am.NBIF_HWIP} - self.ip_versions = {id2ip[int(hwid)]:tuple(int(FileIOInterface(f'{ip_base}/{hwid}/0/{part}').read()) for part in ['major', 'minor', 'revision']) - for hwid in FileIOInterface(ip_base).listdir() if hwid.isnumeric() and int(hwid) in id2ip} - self.ip_offsets = {id2ip[int(hwid)]:tuple(int(x, 16) for x in FileIOInterface(f'{ip_base}/{hwid}/0/base_addr').read().splitlines()) - for hwid in FileIOInterface(ip_base).listdir() if hwid.isnumeric() and int(hwid) in id2ip} - self.drm_fd = FileIOInterface(f"/dev/dri/renderD{self.props['drm_render_minor']}", os.O_RDWR) - - kfd.AMDKFD_IOC_ACQUIRE_VM(KFDIface.kfd, drm_fd=self.drm_fd.fd, gpu_id=self.gpu_id) - - # Set these for our device. - if KFDIface.event_page is None: - KFDIface.event_page = self.alloc(0x8000, uncached=True) - kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_page_offset=KFDIface.event_page.meta.handle) - else: self.map(KFDIface.event_page) - - # Event to wait for queues completion - self.dev.queue_event = kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_type=kfd.KFD_IOC_EVENT_SIGNAL, auto_reset=1) - self.dev.queue_event_mailbox_ptr = KFDIface.event_page.va_addr + self.dev.queue_event.event_slot_index * 8 - self.queue_event_arr = (kfd.struct_kfd_event_data)(event_id=self.dev.queue_event.event_id) - self.queue_event_arr_ptr = ctypes.addressof(self.queue_event_arr) - - # OS events to collect memory and hardware faults - self.mem_fault_event = kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_type=kfd.KFD_IOC_EVENT_MEMORY) - self.hw_fault_event = kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_type=kfd.KFD_IOC_EVENT_HW_EXCEPTION) - - def alloc(self, size:int, host=False, uncached=False, cpu_access=False) -> HCQBuffer: - flags = kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE - - if uncached: flags |= kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT - else: flags |= (kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR if host else kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - - if cpu_access or host: flags |= kfd.KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC - - if flags & kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR: - buf = addr = FileIOInterface.anon_mmap(0, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, 0) - else: buf, addr = 0, FileIOInterface.anon_mmap(0, size, 0, mmap.MAP_PRIVATE | mmap.MAP_ANONYMOUS | MAP_NORESERVE, 0) - - try: mem = kfd.AMDKFD_IOC_ALLOC_MEMORY_OF_GPU(self.kfd, va_addr=addr, size=size, base=addr, length=size, gpu_id=self.gpu_id, - flags=flags, mmap_offset=buf) - except OSError as e: - if e.errno == errno.EINVAL and (flags & kfd.KFD_IOC_ALLOC_MEM_FLAGS_VRAM) and cpu_access: - raise MemoryError("Cannot allocate host-visible VRAM. Ensure the resizable BAR option is enabled on your system.") from e - if e.errno == errno.ENOMEM: raise MemoryError("Cannot allocate memory: no memory is available.") from e - raise - - if not (flags & kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR): - buf = self.drm_fd.mmap(mem.va_addr, mem.size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | MAP_FIXED, mem.mmap_offset) - assert addr == buf == mem.va_addr - - self.map(hcqbuf:=HCQBuffer(mem.va_addr, mem.size, meta=mem, view=MMIOInterface(mem.va_addr, mem.size, fmt='B') if cpu_access or host else None)) - return hcqbuf - - def free(self, mem): - if len(gpus:=getattr(mem.meta, "mapped_gpu_ids", [])): - c_gpus = (ctypes.c_int32 * len(gpus))(*gpus) - stm = kfd.AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(c_gpus), n_devices=len(gpus)) - assert stm.n_success == len(gpus) - if mem.va_addr: FileIOInterface.munmap(mem.va_addr, mem.size) - kfd.AMDKFD_IOC_FREE_MEMORY_OF_GPU(self.kfd, handle=mem.meta.handle) - - def map(self, mem): - if self.gpu_id in getattr(mem.meta, "mapped_gpu_ids", []): return - mem.meta.__setattr__("mapped_gpu_ids", getattr(mem.meta, "mapped_gpu_ids", []) + [self.gpu_id]) - c_gpus = (ctypes.c_int32 * len(mem.meta.mapped_gpu_ids))(*mem.meta.mapped_gpu_ids) - stm = kfd.AMDKFD_IOC_MAP_MEMORY_TO_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(c_gpus), - n_devices=len(mem.meta.mapped_gpu_ids)) - assert stm.n_success == len(mem.meta.mapped_gpu_ids) - - def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): - queue = kfd.AMDKFD_IOC_CREATE_QUEUE(KFDIface.kfd, ring_base_address=ring.va_addr, ring_size=ring.size, gpu_id=self.gpu_id, - queue_type=queue_type, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE|(xcc_id<<8), queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, - eop_buffer_address=eop_buffer.va_addr if eop_buffer else 0, eop_buffer_size=eop_buffer.size if eop_buffer else 0, ctl_stack_size=ctl_stack_size, - ctx_save_restore_address=cwsr_buffer.va_addr if cwsr_buffer else 0, ctx_save_restore_size=ctx_save_restore_size, - write_pointer_address=gart.va_addr, read_pointer_address=gart.va_addr + 8 * (xcc_id + 1)) - - if not hasattr(self, 'doorbells'): - self.doorbells_base = queue.doorbell_offset & (~0x1fff) # doorbell is two pages - self.doorbells = cast(FileIOInterface, KFDIface.kfd).mmap(0, 0x2000, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED, self.doorbells_base) - - return AMDQueueDesc(ring=MMIOInterface(ring.va_addr, ring.size, fmt='I'), read_ptrs=[MMIOInterface(queue.read_pointer_address, 8, fmt='Q')], - write_ptrs=[MMIOInterface(queue.write_pointer_address, 8, fmt='Q')], - doorbells=[MMIOInterface(self.doorbells + queue.doorbell_offset - self.doorbells_base, 8, fmt='Q')]) - - def sleep(self, tm:int): kfd.AMDKFD_IOC_WAIT_EVENTS(KFDIface.kfd, events_ptr=self.queue_event_arr_ptr, num_events=1, wait_for_all=1, timeout=tm) - - def on_device_hang(self): - def _collect_str(st): return ' '.join(f'{k[0]}={getattr(st, k[0])}' for k in st._fields_) - - report = [] - for evnt in [self.mem_fault_event, self.hw_fault_event]: - ev = (kfd.struct_kfd_event_data)(event_id=evnt.event_id) - kfd.AMDKFD_IOC_WAIT_EVENTS(KFDIface.kfd, events_ptr=ctypes.addressof(ev), num_events=1, wait_for_all=1) - if evnt == self.mem_fault_event and ev.memory_exception_data.gpu_id: - report += [f"MMU fault: 0x{ev.memory_exception_data.va:X} | {_collect_str(ev.memory_exception_data.failure)}"] - if evnt == self.hw_fault_event and ev.hw_exception_data.gpu_id: report += [f"HW fault: {_collect_str(ev.hw_exception_data)}"] - - raise RuntimeError("\n".join(report)) - -@dataclass -class AMAllocationMeta: owner:AMDDevice; mapped_devs:list[AMDDevice]; mapping:AMMapping; has_cpu_mapping:bool # noqa: E702 - -class PCIIface: - supported_devs:list[int] = [0x744c, 0x7480, 0x7550] - vfio_fd:FileIOInterface|None = None - gpus:list[Any] = [] - - def __init__(self, dev, dev_id): - self.dev = dev - - if first_dev:=len(PCIIface.gpus) == 0: - for pcibus in FileIOInterface("/sys/bus/pci/devices").listdir(): - vendor = int(FileIOInterface(f"/sys/bus/pci/devices/{pcibus}/vendor").read(), 16) - device = int(FileIOInterface(f"/sys/bus/pci/devices/{pcibus}/device").read(), 16) - if vendor == 0x1002 and device in PCIIface.supported_devs: PCIIface.gpus.append(pcibus) - PCIIface.gpus = sorted(PCIIface.gpus) - - # TODO: visible_devices should be handled layer above this? - visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('HIP_VISIBLE_DEVICES', ''))).split(',') if x.strip()] - PCIIface.gpus = [PCIIface.gpus[x] for x in visible_devices] if visible_devices else PCIIface.gpus - - self.pcibus = PCIIface.gpus[dev_id] - - # Unbind the device from the kernel driver - if FileIOInterface.exists(f"/sys/bus/pci/devices/{self.pcibus}/driver"): - FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/driver/unbind", os.O_WRONLY).write(self.pcibus) - - supported_sizes = int(FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource0_resize", os.O_RDONLY).read(), 16) - try: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource0_resize", os.O_RDWR).write(str(supported_sizes.bit_length() - 1)) - except OSError as e: raise RuntimeError(f"Cannot resize BAR: {e}. Ensure the resizable BAR option is enabled on your system.") from e - - # Disable migartion of locked pages. - if first_dev and FileIOInterface(reloc_sysfs:="/proc/sys/vm/compact_unevictable_allowed", os.O_RDONLY).read()[0] != "0": - os.system(cmd:=f"sudo sh -c 'echo 0 > {reloc_sysfs}'") - assert FileIOInterface(reloc_sysfs, os.O_RDONLY).read()[0] == "0", f"Failed to disable migration of locked pages. Please run {cmd} manually." - - # Try to init vfio. Use it if success. - if getenv("VFIO", 0): - try: - if first_dev: - if not FileIOInterface.exists("/sys/module/vfio"): os.system("sudo modprobe vfio-pci disable_idle_d3=1") - - FileIOInterface("/sys/module/vfio/parameters/enable_unsafe_noiommu_mode", os.O_RDWR).write("1") - PCIIface.vfio_fd = FileIOInterface("/dev/vfio/vfio", os.O_RDWR) - vfio.VFIO_CHECK_EXTENSION(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU) - - FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/driver_override", os.O_WRONLY).write("vfio-pci") - FileIOInterface("/sys/bus/pci/drivers_probe", os.O_WRONLY).write(self.pcibus) - - iommu_group = FileIOInterface.readlink(f"/sys/bus/pci/devices/{self.pcibus}/iommu_group").split('/')[-1] - except OSError as e: - if DEBUG >= 1: print(f"am {self.pcibus}: failed to init vfio-pci module (run `sudo modprobe vfio-pci`): {e}.") - PCIIface.vfio_fd = None - - # Init vfio for the device - if PCIIface.vfio_fd is not None: - self.vfio_group = FileIOInterface(f"/dev/vfio/noiommu-{iommu_group}", os.O_RDWR) - vfio.VFIO_GROUP_SET_CONTAINER(self.vfio_group, ctypes.c_int(PCIIface.vfio_fd.fd)) - - if first_dev: vfio.VFIO_SET_IOMMU(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU) - self.vfio_dev = FileIOInterface(fd=vfio.VFIO_GROUP_GET_DEVICE_FD(self.vfio_group, ctypes.create_string_buffer(self.pcibus.encode()))) - - self.irq_fd = FileIOInterface.eventfd(0, 0) - self.irq_poller = select.poll() - self.irq_poller.register(self.irq_fd.fd, select.POLLIN) - - irqs = vfio.struct_vfio_irq_set(index=vfio.VFIO_PCI_MSI_IRQ_INDEX, flags=vfio.VFIO_IRQ_SET_DATA_EVENTFD|vfio.VFIO_IRQ_SET_ACTION_TRIGGER, - argsz=ctypes.sizeof(vfio.struct_vfio_irq_set), count=1, data=(ctypes.c_int * 1)(self.irq_fd.fd)) - vfio.VFIO_DEVICE_SET_IRQS(self.vfio_dev, irqs) - else: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/enable", os.O_RDWR).write("1") - - self.pagemap = FileIOInterface("/proc/self/pagemap", os.O_RDONLY) - self.cfg_fd = FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/config", os.O_RDWR | os.O_SYNC | os.O_CLOEXEC) - self.bar_fds = {b: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource{b}", os.O_RDWR | os.O_SYNC | os.O_CLOEXEC) for b in [0, 2, 5]} - - bar_info = FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource", os.O_RDONLY).read().splitlines() - self.bar_info = {j:(int(start,16), int(end,16), int(flgs,16)) for j,(start,end,flgs) in enumerate(l.split() for l in bar_info)} - - self._setup_adev(self.pcibus, self._map_pci_range(0), dbell:=self._map_pci_range(2, fmt='Q'), self._map_pci_range(5, fmt='I')) - self.doorbell_cpu_addr = dbell.addr - - if first_dev: - FileIOInterface.anon_mmap((alloc:=self.adev.mm.va_allocator).base, alloc.size, 0, mmap.MAP_PRIVATE|mmap.MAP_ANONYMOUS|MAP_NORESERVE, 0) - - pci_cmd = int.from_bytes(self.cfg_fd.read(2, binary=True, offset=pci.PCI_COMMAND), byteorder='little') | pci.PCI_COMMAND_MASTER - self.cfg_fd.write(pci_cmd.to_bytes(2, byteorder='little'), binary=True, offset=pci.PCI_COMMAND) - - def _setup_adev(self, name, vram:MMIOInterface, doorbell:MMIOInterface, mmio:MMIOInterface, dma_regions:list[tuple[int, MMIOInterface]]|None=None): - self.adev = AMDev(name, vram, doorbell, mmio, dma_regions) - self.ip_versions = self.adev.ip_ver - self.ip_offsets = {hwip: tuple(instances[0]) for hwip,instances in self.adev.regs_offset.items()} - - gfxver = int(f"{self.adev.ip_ver[am.GC_HWIP][0]:02d}{self.adev.ip_ver[am.GC_HWIP][1]:02d}{self.adev.ip_ver[am.GC_HWIP][2]:02d}") - array_count = self.adev.gc_info.gc_num_sa_per_se * self.adev.gc_info.gc_num_se - simd_count = 2 * array_count * (self.adev.gc_info.gc_num_wgp0_per_sa + self.adev.gc_info.gc_num_wgp1_per_sa) - self.props = {'simd_count': 2 * simd_count, 'simd_per_cu': 2, 'array_count': array_count, 'gfx_target_version': gfxver, - 'max_slots_scratch_cu': self.adev.gc_info.gc_max_scratch_slots_per_cu, 'max_waves_per_simd': self.adev.gc_info.gc_max_waves_per_simd, - 'simd_arrays_per_engine': self.adev.gc_info.gc_num_sa_per_se, 'lds_size_in_kb': self.adev.gc_info.gc_lds_size} - - def _map_pci_range(self, bar, off=0, addr=0, size=None, fmt='B'): - fd, sz = self.bar_fds[bar], size or (self.bar_info[bar][1] - self.bar_info[bar][0] + 1) - libc.madvise(loc:=fd.mmap(addr, sz, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | (MAP_FIXED if addr else 0), off), sz, libc.MADV_DONTFORK) - return MMIOInterface(loc, sz, fmt=fmt) - - def alloc(self, size:int, host=False, uncached=False, cpu_access=False): - if host or (not getenv("AMD_ALLOC_QUEUE_DEV_MEM", 1) and uncached and cpu_access): # host or gtt-like memory. - vaddr = self.adev.mm.alloc_vaddr(size:=round_up(size, mmap.PAGESIZE), align=mmap.PAGESIZE) - FileIOInterface.anon_mmap(vaddr, size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED|mmap.MAP_ANONYMOUS|MAP_POPULATE|MAP_LOCKED|MAP_FIXED, 0) - - # Read pagemap to get the physical address of each page. The pages are locked. - self.pagemap.seek(vaddr // mmap.PAGESIZE * 8) - paddrs = [((x & ((1<<55) - 1)) * mmap.PAGESIZE, mmap.PAGESIZE) for x in array.array('Q', self.pagemap.read(size//mmap.PAGESIZE*8, binary=True))] - am_mapping = self.adev.mm.map_range(vaddr, size, paddrs, system=True, snooped=True, uncached=True) - return HCQBuffer(vaddr, size, meta=AMAllocationMeta(self.dev, [self.dev], am_mapping, has_cpu_mapping=True), - view=MMIOInterface(am_mapping.va_addr, size, fmt='B')) - - am_mapping = self.adev.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contigous=cpu_access) - if cpu_access: self._map_pci_range(bar=0, off=am_mapping.paddrs[0][0], addr=am_mapping.va_addr, size=am_mapping.size) - return HCQBuffer(am_mapping.va_addr, size, meta=AMAllocationMeta(self.dev, [self.dev], am_mapping, has_cpu_mapping=cpu_access), - view=MMIOInterface(am_mapping.va_addr, size, fmt='B') if cpu_access else None) - - def free(self, mem): - for dev in mem.meta.mapped_devs[1:]: dev.dev_iface.adev.mm.unmap_range(mem.va_addr, mem.size) - if not mem.meta.mapping.system: self.adev.mm.vfree(mem.meta.mapping) - if mem.meta.owner == self.dev and mem.meta.has_cpu_mapping: FileIOInterface.munmap(mem.va_addr, mem.size) - - def map(self, mem): - # Check if the memory is already mapped on this device - if self.dev in mem.meta.mapped_devs: return - mem.meta.mapped_devs.append(self.dev) - - paddrs = [(paddr if mem.meta.mapping.system else (paddr+mem.meta.owner.dev_iface.bar_info[0][0]), size) for paddr,size in mem.meta.mapping.paddrs] - self.adev.mm.map_range(mem.va_addr, mem.size, paddrs, system=True, snooped=mem.meta.mapping.snooped, uncached=mem.meta.mapping.uncached) - - def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): - assert cwsr_buffer is None, "no cwsr buffer for am" - - if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: - self.adev.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, - doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) - else: - self.adev.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, - eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) - - return AMDQueueDesc(ring=MMIOInterface(ring.va_addr, ring.size, fmt='I'), read_ptrs=[MMIOInterface(gart.va_addr, 8, fmt='Q')], - write_ptrs=[MMIOInterface(gart.va_addr+0x10, 8, fmt='Q')], doorbells=[MMIOInterface(self.doorbell_cpu_addr + doorbell_index * 8, 8, fmt='Q')]) - - def sleep(self, timeout): - if PCIIface.vfio_fd is not None and (events_cnt:=len(self.irq_poller.poll(timeout))): - self.irq_fd.read(8 * events_cnt) - self.adev.ih.interrupt_handler() - - def on_device_hang(self): - for d in self.dev.devices: d.dev_iface.adev.gmc.on_interrupt() - raise RuntimeError("Device hang detected") - - def device_fini(self): self.adev.fini() - -class USBIface(PCIIface): - def __init__(self, dev, dev_id): - self.dev = dev - self.usb = ASM24Controller() - self.bars = setup_pci_bars(self.usb, gpu_bus=4, mem_base=0x10000000, pref_mem_base=(32 << 30)) - - self._setup_adev(f"usb:{dev_id}", USBMMIOInterface(self.usb, *self.bars[0], fmt='B'), USBMMIOInterface(self.usb, *self.bars[2], fmt='Q'), - USBMMIOInterface(self.usb, *self.bars[5], fmt='I'), dma_regions=[(0x200000, self._dma_view(0xf000, 0x80000))]) - self.usb._pci_cacheable += [self.bars[2]] # doorbell region is cacheable - - # special regions - self.copy_bufs = [self._dma_region(ctrl_addr=0xf000, sys_addr=0x200000, size=0x80000)] - self.sys_buf, self.sys_next_off = self._dma_region(ctrl_addr=0xa000, sys_addr=0x820000, size=0x1000), 0x800 - - def _dma_view(self, ctrl_addr, size): return USBMMIOInterface(self.usb, ctrl_addr, size, fmt='B', pcimem=False) - def _dma_region(self, ctrl_addr, sys_addr, size): - region = self.adev.mm.map_range(vaddr:=self.adev.mm.alloc_vaddr(size=size), size, [(sys_addr, size)], system=True, snooped=False, uncached=True) - return HCQBuffer(vaddr, size, meta=AMAllocationMeta(self.dev, [self.dev], region, has_cpu_mapping=False), view=self._dma_view(ctrl_addr, size)) - - def alloc(self, size:int, host=False, uncached=False, cpu_access=False): - if (host or (uncached and cpu_access)) and self.sys_next_off + size < self.sys_buf.size: - self.sys_next_off += size - return self.sys_buf.offset(self.sys_next_off - size, size) - - am_mapping = self.adev.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contigous=cpu_access) - return HCQBuffer(am_mapping.va_addr, size, meta=AMAllocationMeta(self.dev, [self.dev], am_mapping, has_cpu_mapping=False), - view=USBMMIOInterface(self.usb, self.bars[0][0] + am_mapping.paddrs[0][0], size, fmt='B') if cpu_access else None) - - def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): - if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: - self.adev.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, - doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) - else: - self.adev.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, - eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) - self.usb._pci_cacheable += [(ring.cpu_view().addr, ring.size)] - - return AMDQueueDesc(ring=ring.cpu_view().view(fmt='I'), doorbells=[self.adev.doorbell64.view(doorbell_index * 8, 8, fmt='Q')], - read_ptrs=[gart.cpu_view().view(size=8, fmt='Q')], write_ptrs=[gart.cpu_view().view(offset=0x10, size=8, fmt='Q')]) - -class AMDDevice(HCQCompiled): - devices: ClassVar[list[HCQCompiled]] = [] - signal_pages: ClassVar[list[HCQBuffer]] = [] - signal_pool: ClassVar[list[HCQBuffer]] = [] - - def is_am(self) -> bool: return isinstance(self.dev_iface, (PCIIface, USBIface)) - def is_usb(self) -> bool: return isinstance(self.dev_iface, USBIface) - - def _select_iface(self): - if len(nm:=getenv("AMD_IFACE", "")) > 0: return getattr(sys.modules[__name__], f"{nm.upper()}Iface")(self, self.device_id) - - errs:str = "" - for iface_t in (KFDIface, PCIIface, USBIface): - try: return iface_t(self, self.device_id) - except Exception: errs += f"\n{iface_t.__name__}: {traceback.format_exc()}" - raise RuntimeError(f"Cannot find a usable interface for AMD:{self.device_id}:\n{errs}") - - def __init__(self, device:str=""): - self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.dev_iface = self._select_iface() - self.target:tuple[int, ...] = ((trgt:=self.dev_iface.props['gfx_target_version']) // 10000, (trgt // 100) % 100, trgt % 100) - self.arch = "gfx%d%x%x" % self.target - if self.target < (9,4,2) or self.target >= (13,0,0): raise RuntimeError(f"Unsupported arch: {self.arch}") - if DEBUG >= 1: print(f"AMDDevice: opening {self.device_id} with target {self.target} arch {self.arch}") - - self.max_cu_id = self.dev_iface.props['simd_count'] // self.dev_iface.props['simd_per_cu'] // self.dev_iface.props.get('num_xcc', 1) - 1 - self.max_wave_id = (self.dev_iface.props['max_waves_per_simd'] * self.dev_iface.props['simd_per_cu'] - 1) if self.target >= (10,1,0) else \ - (min((self.max_cu_id+1)*40, self.dev_iface.props['array_count'] // self.dev_iface.props['simd_arrays_per_engine'] * 512) - 1) - self.xccs = self.dev_iface.props.get('num_xcc', 1) if getenv("XCCS", 1) else 1 - self.has_scratch_base_registers = self.target >= (11,0,0) or self.target == (9,4,2) # this is what llvm refers to as "architected flat scratch" - - # https://gitlab.freedesktop.org/agd5f/linux/-/blob/a1fc9f584c4aaf8bc1ebfa459fc57a3f26a290d8/drivers/gpu/drm/amd/amdkfd/kfd_queue.c#L391 - sgrp_size_per_cu, lds_size_per_cu, hwreg_size_per_cu = 0x4000, 0x10000, 0x1000 - vgpr_size_per_cu = 0x60000 if self.target in {(11,0,0), (11,0,1), (12,0,0), (12,0,1)} else \ - 0x80000 if (self.target[:2]) == (9,4) or self.target in {(9,0,8), (9,0,10)} else 0x40000 - wg_data_size = round_up((vgpr_size_per_cu + sgrp_size_per_cu + lds_size_per_cu + hwreg_size_per_cu) * (self.max_cu_id + 1), mmap.PAGESIZE) - ctl_stack_size = round_up(12 * (self.max_cu_id + 1) * (self.max_wave_id + 1) + 8 + 40, mmap.PAGESIZE) if self.target >= (10,1,0) else \ - round_up((self.max_wave_id + 1) * 8 + 8 + 40, mmap.PAGESIZE) - debug_memory_size = round_up((self.max_cu_id + 1 if self.target >= (10,1,0) else 1) * (self.max_wave_id + 1) * 32, 64) - if self.target[0] == 10: ctl_stack_size = min(ctl_stack_size, 0x7000) - - self.soc = importlib.import_module(f"tinygrad.runtime.autogen.am.{({9: 'vega10', 10: 'navi10', 11: 'soc21', 12: 'soc24'}[self.target[0]])}") - self.pm4 = importlib.import_module(f"tinygrad.runtime.autogen.am.pm4_{'nv' if self.target[0] >= 10 else 'soc15'}") - self.sdma = import_module('sdma', min(self.dev_iface.ip_versions[am.SDMA0_HWIP], (6, 0, 0))) - self.gc = AMDIP('gc', self.dev_iface.ip_versions[am.GC_HWIP], self.dev_iface.ip_offsets[am.GC_HWIP]) - - # Define the regCOMPUTE_CURRENT_LOGIC_XCC_ID register, which is missing from the asic_regs files. - if self.target[:2] == (9,4): self.regCOMPUTE_CURRENT_LOGIC_XCC_ID = AMDReg("regCOMPUTE_CURRENT_LOGIC_XCC_ID", 0xe25, 0, {}, self.gc.bases) - - nbio_name = 'nbio' if self.target[0] < 12 else 'nbif' - nbio_pad = (0,) if self.target[0] == 9 else () - self.nbio = AMDIP(nbio_name, self.dev_iface.ip_versions[am.NBIF_HWIP], nbio_pad+self.dev_iface.ip_offsets[am.NBIF_HWIP]) - - self.compute_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_COMPUTE, 0x2000 if self.is_usb() else 0x800000, eop_buffer_size=0x1000, - ctx_save_restore_size=0 if self.is_am() else wg_data_size + ctl_stack_size, ctl_stack_size=ctl_stack_size, debug_memory_size=debug_memory_size) - - max_copy_size = 0x40000000 if self.dev_iface.ip_versions[am.SDMA0_HWIP][0] >= 5 else 0x400000 - self.sdma_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_SDMA, 0x200 if self.is_usb() else 0x800000) - - super().__init__(device, AMDAllocator(self), AMDLLVMRenderer(self.arch) if getenv("AMD_LLVM", 1) else AMDRenderer(self.arch), - AMDLLVMCompiler(self.arch) if getenv("AMD_LLVM", 1) else HIPCompiler(self.arch), functools.partial(AMDProgram, self), - AMDSignal, functools.partial(AMDComputeQueue, self), functools.partial(AMDCopyQueue, self, max_copy_size=max_copy_size), - kernargs_size=(8 << 10) if self.is_usb() else (16 << 20), sigalloc_size=0x100 if self.is_usb() else 0x1000) - - # Scratch setup - self.max_private_segment_size = 0 - self._ensure_has_local_memory(128) # set default scratch size to 128 bytes per thread - - # XCC setup - self.xcc_sync: tuple[AMDSignal, AMDSignal]|None = None - if self.xccs > 1: - self.xcc_sync_area = self.allocator.alloc(0x1000, BufferSpec(nolru=True, cpu_access=True)) - self.xcc_sync = (AMDSignal(base_buf=self.xcc_sync_area), AMDSignal(base_buf=self.xcc_sync_area.offset(256))) - AMDComputeQueue(self).xcc_config().submit(self) - - # SQTT is disabled by default because of runtime overhead and big file sizes (~200mb to Tensor.full() two 4096x4096 tensors and matmul them) - self.sqtt_enabled = PROFILE and bool(getenv("SQTT", 0)) - if self.sqtt_enabled: - if self.arch != 'gfx1100': raise RuntimeError('SQ Thread Tracing is only supported on 7900XTX') - if not self.is_am() and (ppfeaturemask:=int(FileIOInterface('/sys/module/amdgpu/parameters/ppfeaturemask', os.O_RDONLY).read(), 16))&0x8000: - raise RuntimeError("SQTT can't be enabled because of hardware bug, to workaround either use AMD_IFACE=PCI or add " - f"ppfeaturemask={(ppfeaturemask&~0x8000):#x} (current {ppfeaturemask=:#x} & ~PP_GFXOFF_MASK) to amdgpu module parameters\n" - "For more information read https://github.com/tinygrad/tinygrad/blob/master/extra/sqtt/README.md") - SQTT_BUFFER_SIZE = getenv("SQTT_BUFFER_SIZE", 256) # in mb, per shader engine - SQTT_NUM = self.dev_iface.props['array_count'] // self.dev_iface.props['simd_arrays_per_engine'] - self.sqtt_buffers = [self.allocator.alloc(SQTT_BUFFER_SIZE*1024*1024, BufferSpec(cpu_access=True, nolru=True)) for _ in range(SQTT_NUM)] - self.sqtt_itrace_se_mask = getenv("SQTT_ITRACE_SE_MASK", 2) # -1 enable all, 0 disable all, >0 bitmask for where to enable instruction tracing - self.cmd_id = 0 - AMDComputeQueue(self).sqtt_start(self.sqtt_buffers, self.sqtt_itrace_se_mask).submit(self) - - def create_queue(self, queue_type, ring_size, ctx_save_restore_size=0, eop_buffer_size=0, ctl_stack_size=0, debug_memory_size=0): - ring = self.dev_iface.alloc(ring_size, uncached=True, cpu_access=True) - gart = self.dev_iface.alloc(0x100, uncached=True, cpu_access=True) - - cwsr_buffer_size = round_up((ctx_save_restore_size + debug_memory_size) * self.dev_iface.props.get('num_xcc', 1), mmap.PAGESIZE) - cwsr_buffer = self.dev_iface.alloc(cwsr_buffer_size) if ctx_save_restore_size else None - eop_buffer = self.dev_iface.alloc(eop_buffer_size) if eop_buffer_size else None - - return AMDQueueDesc.multi(*(self.dev_iface.create_queue(queue_type, ring, gart, eop_buffer=eop_buffer, cwsr_buffer=cwsr_buffer, xcc_id=xcc_id, - ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size) - for xcc_id in range(self.xccs if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE else 1))) - - def _ensure_has_local_memory(self, required): - if self.max_private_segment_size >= required: return - - # =gfx11 requires 256 - wave_scratch_len = round_up(((self.max_wave_id + 1) * required), 256 if self.target >= (11,0,0) else 1024) - - scratch_size = (self.max_cu_id+1)*self.dev_iface.props['max_slots_scratch_cu']*wave_scratch_len # per xcc - self.scratch, ok = self._realloc(getattr(self, 'scratch', None), scratch_size*self.xccs) - if ok: - engines = self.dev_iface.props['array_count'] // self.dev_iface.props['simd_arrays_per_engine'] - waves = wave_scratch_len // (256 if self.target >= (11,0,0) else 1024) - # >=gfx11 wavesize is per SE - wavesize = scratch_size // ((wave_scratch_len * engines) if self.target >= (11,0,0) else wave_scratch_len) - self.tmpring_size = waves << 12 | wavesize - self.max_private_segment_size = required - - def invalidate_caches(self): - AMDComputeQueue(self).memory_barrier().signal(self.timeline_signal, self.next_timeline()).submit(self) - self.synchronize() - - def on_device_hang(self): self.dev_iface.on_device_hang() - - def _at_profile_finalize(self): - if self.sqtt_enabled: - wptrs_buf = self.allocator.alloc(round_up(len(self.sqtt_buffers), 0x1000), BufferSpec(cpu_access=True, nolru=True)) - wptrs = to_mv(wptrs_buf.va_addr, wptrs_buf.size) - AMDComputeQueue(self).sqtt_stop(len(self.sqtt_buffers), wptrs_buf).signal(self.timeline_signal, self.next_timeline()).submit(self) - self.synchronize() - if DEBUG>=2: print('Saving SQTT in profile...') - for i,buf0 in enumerate(self.sqtt_buffers): - wptr = ((struct.unpack('=2: print(f'Se {i} blob size {wptr:#x}') - assert wptr >= 0 and wptr <= buf0.size, f"{wptr} > {buf0.size}, should never happen" - # When sqtt buffer overflows, wptr stops at the last dword - if wptr >= buf0.size-32: print(f"WARNING: SQTT BUFFER IS FULL (SE {i})! INCREASE SQTT BUFFER SIZE WITH SQTT_BUFFER_SIZE=X (in MB)") - self.allocator._copyout(sqtt_buf:=memoryview(bytearray(wptr)), buf0) - Compiled.profile_events += [ProfileSQTTEvent(self.device, i, bytes(sqtt_buf), bool((self.sqtt_itrace_se_mask >> i) & 0b1))] - super()._at_profile_finalize() - - def finalize(self): - try: self.synchronize() # Try to finalize device in any case. - except RuntimeError as e: print(f"{self.device} synchronization failed before finalizing: {e}") - if hasattr(self.dev_iface, 'device_fini'): self.dev_iface.device_fini() diff --git a/tinygrad/tinygrad/runtime/ops_cpu.py b/tinygrad/tinygrad/runtime/ops_cpu.py deleted file mode 100644 index e180a0a6..00000000 --- a/tinygrad/tinygrad/runtime/ops_cpu.py +++ /dev/null @@ -1,26 +0,0 @@ -import functools, platform, subprocess, sys -from tinygrad.helpers import capstone_flatdump, getenv -from tinygrad.device import Compiled, Compiler, MallocAllocator, CPUProgram -from tinygrad.runtime.support.elf import jit_loader -from tinygrad.renderer.cstyle import ClangRenderer - -class ClangJITCompiler(Compiler): - def __init__(self, cachekey="compile_clang_jit"): super().__init__(cachekey) - - def compile(self, src:str) -> bytes: - # -fno-math-errno is required for __builtin_sqrt to become an instruction instead of a function call - # x18 is a reserved platform register. It is clobbered on context switch in macos and is used to store TEB pointer in windows on arm, don't use it - target = 'x86_64' if sys.platform == 'win32' else platform.machine() - args = ['-march=native', f'--target={target}-none-unknown-elf', '-O2', '-fPIC', '-ffreestanding', '-fno-math-errno', '-nostdlib', '-fno-ident'] - arch_args = ['-ffixed-x18'] if target == 'arm64' else [] - obj = subprocess.check_output([getenv("CC", 'clang'), '-c', '-x', 'c', *args, *arch_args, '-', '-o', '-'], input=src.encode('utf-8')) - return jit_loader(obj) - - def disassemble(self, lib:bytes): return capstone_flatdump(lib) - -class ClangDevice(Compiled): - def __init__(self, device:str): - from tinygrad.runtime.graph.cpu import CPUGraph - super().__init__(device, MallocAllocator, ClangRenderer(), ClangJITCompiler(), CPUProgram, functools.partial(CPUGraph, self)) - -CPUDevice = ClangDevice \ No newline at end of file diff --git a/tinygrad/tinygrad/runtime/ops_cuda.py b/tinygrad/tinygrad/runtime/ops_cuda.py deleted file mode 100644 index f62577b2..00000000 --- a/tinygrad/tinygrad/runtime/ops_cuda.py +++ /dev/null @@ -1,130 +0,0 @@ -from __future__ import annotations -import ctypes, ctypes.util, functools -from tinygrad.helpers import DEBUG, getenv, from_mv, init_c_var, init_c_struct_t -from tinygrad.device import Compiled, BufferSpec, LRUAllocator -from tinygrad.renderer.cstyle import CUDARenderer -from tinygrad.renderer.ptx import PTXRenderer -from tinygrad.runtime.autogen import cuda -from tinygrad.runtime.support.compiler_cuda import pretty_ptx, CUDACompiler, PTXCompiler, PTX -if getenv("IOCTL"): import extra.nv_gpu_driver.nv_ioctl # noqa: F401 # pylint: disable=unused-import -if MOCKGPU:=getenv("MOCKGPU"): from test.mockgpu.cuda import cuda # type: ignore # pylint: disable=reimported - -def check(status): - if status != 0: raise RuntimeError(f"CUDA Error {status}, {ctypes.string_at(init_c_var(ctypes.POINTER(ctypes.c_char)(), lambda x: cuda.cuGetErrorString(status, ctypes.byref(x)))).decode()}") # noqa: E501 - -def encode_args(args, vals) -> tuple[ctypes.Structure, ctypes.Array]: - c_args = init_c_struct_t(tuple([(f'f{i}', cuda.CUdeviceptr_v2) for i in range(len(args))] + - [(f'v{i}', ctypes.c_int) for i in range(len(vals))]))(*args, *vals) - vargs = (ctypes.c_void_p * 5)(ctypes.c_void_p(1), ctypes.cast(ctypes.byref(c_args), ctypes.c_void_p), ctypes.c_void_p(2), - ctypes.cast(ctypes.pointer(ctypes.c_size_t(ctypes.sizeof(c_args))), ctypes.c_void_p), ctypes.c_void_p(0)) - return c_args, vargs - -def cu_time_execution(cb, enable=False) -> float|None: - if not enable: return cb() - evs = [init_c_var(cuda.CUevent(), lambda x: cuda.cuEventCreate(ctypes.byref(x), 0)) for _ in range(2)] - cuda.cuEventRecord(evs[0], None) - cb() - cuda.cuEventRecord(evs[1], None) - check(cuda.cuEventSynchronize(evs[1])) - cuda.cuEventElapsedTime(ctypes.byref(ret := ctypes.c_float()), evs[0], evs[1]) - for ev in evs: cuda.cuEventDestroy_v2(ev) - return ret.value * 1e-3 - -class CUDAProgram: - def __init__(self, dev:CUDADevice, name:str, lib:bytes, smem:int=0): - self.dev, self.name, self.lib, self.smem = dev, name, lib, smem - if DEBUG >= 5: print("\n".join([f"{i+1:>3} {line}" for i, line in enumerate(pretty_ptx(lib.decode('utf-8')).split("\n"))])) - - check(cuda.cuCtxSetCurrent(self.dev.context)) - self.module = cuda.CUmodule() - status = cuda.cuModuleLoadData(ctypes.byref(self.module), lib) - if status != 0: - del self.module - raise RuntimeError(f"module load failed with status code {status}: {cuda.cudaError_enum__enumvalues[status]}") - check(cuda.cuModuleGetFunction(ctypes.byref(prg := cuda.CUfunction()), self.module, name.encode("utf-8"))) - self.prg = prg - if self.smem > 0: check(cuda.cuFuncSetAttribute(self.prg, cuda.CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES, self.smem)) - - def __del__(self): - try: check(cuda.cuModuleUnload(self.module)) - except AttributeError: pass - - def __call__(self, *args, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - check(cuda.cuCtxSetCurrent(self.dev.context)) - if not hasattr(self, "vargs"): - self.c_args, self.vargs = encode_args(args, vals) - - # HACK: For MOCKGPU send the args struct itself. - if MOCKGPU: self.vargs = self.c_args # type: ignore[assignment] - else: - for i in range(len(args)): self.c_args.__setattr__(f'f{i}', args[i]) - for i in range(len(vals)): self.c_args.__setattr__(f'v{i}', vals[i]) - return cu_time_execution(lambda: check(cuda.cuLaunchKernel(self.prg, *global_size, *local_size, self.smem, None, None, self.vargs)), enable=wait) - -class CUDAAllocator(LRUAllocator['CUDADevice']): - def _alloc(self, size, options:BufferSpec): - check(cuda.cuCtxSetCurrent(self.dev.context)) - if options.external_ptr: return cuda.CUdeviceptr_v2(options.external_ptr) - if options.host: return init_c_var(ctypes.c_void_p(), lambda x: check(cuda.cuMemHostAlloc(ctypes.byref(x), size, 0x01))) - return init_c_var(cuda.CUdeviceptr(), lambda x: check(cuda.cuMemAlloc_v2(ctypes.byref(x), size))) - def _free(self, opaque, options:BufferSpec): - try: - if options.host: check(cuda.cuMemFreeHost(opaque)) - else: check(cuda.cuMemFree_v2(opaque)) - except (TypeError, AttributeError): pass - def _copyin(self, dest, src:memoryview): - check(cuda.cuCtxSetCurrent(self.dev.context)) - host_mem = self.alloc(len(src), BufferSpec(host=True)) - self.dev.pending_copyin.append((host_mem, len(src), BufferSpec(host=True))) - ctypes.memmove(host_mem, from_mv(src), len(src)) - check(cuda.cuMemcpyHtoDAsync_v2(dest, host_mem, len(src), None)) - def _copyout(self, dest:memoryview, src): - CUDADevice.synchronize_system() - check(cuda.cuCtxSetCurrent(self.dev.context)) - check(cuda.cuMemcpyDtoH_v2(from_mv(dest), src, len(dest))) - def _transfer(self, dest, src, sz:int, src_dev, dest_dev): - check(cuda.cuCtxSetCurrent(src_dev.context)) - check(cuda.cuEventCreate(ctypes.byref(sync_event := cuda.CUevent()), 0)) - check(cuda.cuMemcpyDtoDAsync_v2(dest, src, sz, None)) - check(cuda.cuEventRecord(sync_event, None)) - check(cuda.cuCtxSetCurrent(dest_dev.context)) - check(cuda.cuStreamWaitEvent(None, sync_event, 0)) # sync the default stream on the dest dev - def _offset(self, buf, size:int, offset:int): return cuda.CUdeviceptr_v2(buf.value + offset) - -class CUDADevice(Compiled): - devices: list[CUDADevice] = [] - peer_access = False - - def __init__(self, device:str): - device_id = int(device.split(":")[1]) if ":" in device else 0 - check(cuda.cuInit(0)) - self.cu_device = init_c_var(cuda.CUdevice(), lambda x: check(cuda.cuDeviceGet(ctypes.byref(x), device_id))) - self.context = init_c_var(cuda.CUcontext(), lambda x: check(cuda.cuCtxCreate_v2(ctypes.byref(x), 0, self.cu_device))) - check(cuda.cuDeviceComputeCapability(ctypes.byref(major := ctypes.c_int()), ctypes.byref(minor := ctypes.c_int()), device_id)) - - for dev in CUDADevice.devices: - check(cuda.cuDeviceCanAccessPeer(ctypes.byref(val := ctypes.c_int()), self.cu_device, dev.cu_device)) - if val.value != 1: continue - check(cuda.cuCtxSetCurrent(dev.context)) - check(cuda.cuCtxEnablePeerAccess(self.context, 0)) - check(cuda.cuCtxSetCurrent(self.context)) - check(cuda.cuCtxEnablePeerAccess(dev.context, 0)) - CUDADevice.peer_access = True - - self.arch = f"sm_{major.value}{minor.value}" - self.pending_copyin: list[tuple[int, int, BufferSpec|None]] = [] - CUDADevice.devices.append(self) - - from tinygrad.runtime.graph.cuda import CUDAGraph - super().__init__(device, CUDAAllocator(self), PTXRenderer(self.arch) if PTX else CUDARenderer(self.arch), - PTXCompiler(self.arch) if PTX else CUDACompiler(self.arch), functools.partial(CUDAProgram, self), None if MOCKGPU else CUDAGraph) - - def synchronize(self): - check(cuda.cuCtxSetCurrent(self.context)) - check(cuda.cuCtxSynchronize()) - for opaque,sz,options in self.pending_copyin: self.allocator.free(opaque, sz, options) - self.pending_copyin.clear() - - @staticmethod - def synchronize_system(): - for d in CUDADevice.devices: d.synchronize() diff --git a/tinygrad/tinygrad/runtime/ops_disk.py b/tinygrad/tinygrad/runtime/ops_disk.py deleted file mode 100644 index 34d49996..00000000 --- a/tinygrad/tinygrad/runtime/ops_disk.py +++ /dev/null @@ -1,124 +0,0 @@ -import os, sys, mmap, io, ctypes, ctypes.util, contextlib -from typing import Optional, Generator, Callable -from tinygrad.helpers import OSX, round_up -from tinygrad.device import Compiled, Allocator -with contextlib.suppress(ImportError): - import _posixshmem - from tinygrad.runtime.autogen import io_uring, libc - -class DiskDevice(Compiled): - _tried_io_uring_init = False - - def __init__(self, device:str): - if not DiskDevice._tried_io_uring_init: self._iouring_setup() - - self.size: Optional[int] = None - self.fd: Optional[int] = None - self.count = 0 - super().__init__(device, DiskAllocator(self), None, None, None) - def _might_open(self, size): - self.count += 1 - assert self.size is None or size <= self.size, f"can't reopen Disk tensor with larger size, opened with {self.size}, tried to open with {size}" - if self.size is not None: return - filename = self.device[len("disk:"):] - self.size = size - - if sys.platform != "win32" and filename.startswith("shm:"): - fd = _posixshmem.shm_open("/"+filename[4:].lstrip("/"), os.O_RDWR, 0o600) - self.mem = mmap.mmap(fd, self.size, mmap.MAP_SHARED | MAP_POPULATE | MAP_LOCKED) - os.close(fd) - else: - try: self.fd = os.open(filename, os.O_RDWR|os.O_CREAT|getattr(os, "O_DIRECT", 0)) - except OSError: self.fd = os.open(filename, os.O_RDWR|os.O_CREAT) - if os.fstat(self.fd).st_size < self.size: os.ftruncate(self.fd, self.size) - self.mem = mmap.mmap(self.fd, self.size) - if hasattr(self.mem, 'madvise') and (hp := getattr(mmap, "MADV_HUGEPAGE", None)) is not None: - with contextlib.suppress(OSError): self.mem.madvise(hp) # some systems have transparent_hugepage disabled - def _might_close(self): - self.count -= 1 - if self.count == 0: - if self.fd is not None: os.close(self.fd) - self.size = None - def _iouring_setup(self): - DiskDevice._tried_io_uring_init = True - - if sys.platform == 'linux' and not hasattr(sys, "getandroidapilevel"): - fd = libc.syscall(io_uring.NR_io_uring_setup, 4096, ctypes.byref(p:=io_uring.struct_io_uring_params())) - if fd < 0: return - - sq_ptr = libc.mmap(0, p.sq_off.array + p.sq_entries * 4, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | MAP_POPULATE, fd, 0) - cq_ptr = libc.mmap(0, p.cq_off.cqes + p.cq_entries * ctypes.sizeof(io_uring.struct_io_uring_cqe), - mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | MAP_POPULATE, fd, io_uring.IORING_OFF_CQ_RING) - sqes = libc.mmap(0, p.sq_entries * ctypes.sizeof(io_uring.struct_io_uring_sqe), - mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | MAP_POPULATE, fd, io_uring.IORING_OFF_SQES) - - def u32ptr(val): return ctypes.cast(val, ctypes.POINTER(ctypes.c_uint32)) - sqdesc = io_uring.struct_io_uring_sq(khead=u32ptr(sq_ptr+p.sq_off.head), ktail=u32ptr(sq_ptr+p.sq_off.tail), - array=u32ptr(sq_ptr+p.sq_off.array), - kring_mask=u32ptr(sq_ptr+p.sq_off.ring_mask), sqes=ctypes.cast(sqes, ctypes.POINTER(io_uring.struct_io_uring_sqe))) - - cqdesc = io_uring.struct_io_uring_cq(khead=u32ptr(cq_ptr+p.cq_off.head), ktail=u32ptr(cq_ptr+p.cq_off.tail), - kring_mask=u32ptr(sq_ptr+p.cq_off.ring_mask), cqes=ctypes.cast(cq_ptr+p.cq_off.cqes, ctypes.POINTER(io_uring.struct_io_uring_cqe))) - - DiskDevice.io_uring = io_uring.struct_io_uring(ring_fd=fd, sq=sqdesc, cq=cqdesc) # type: ignore - -class DiskBuffer: - def __init__(self, device:DiskDevice, size:int, offset=0): - self.device, self.size, self.offset = device, size, offset - def __repr__(self): return f"" - def _buf(self) -> memoryview: - assert hasattr(self.device, "mem"), f"DiskBuffer wasn't opened: {self.device.device}" - return memoryview(self.device.mem)[self.offset:self.offset+self.size] - -MAP_LOCKED, MAP_POPULATE = 0 if OSX else 0x2000, getattr(mmap, "MAP_POPULATE", 0 if OSX else 0x008000) -class DiskAllocator(Allocator): - def __init__(self, dev:DiskDevice): super().__init__(dev) - def _alloc(self, size:int, options): - self.dev._might_open(size) - return DiskBuffer(self.dev, size) - def _free(self, opaque, options): self.dev._might_close() - def _as_buffer(self, src:DiskBuffer): return src._buf() - def _copyin(self, dest:DiskBuffer, src:memoryview): dest._buf()[:] = src - def _copyout(self, dest:memoryview, src:DiskBuffer): - if OSX and self.dev.fd is not None: - # OSX doesn't seem great at mmap, this is faster - with io.FileIO(self.dev.fd, "a+b", closefd=False) as fo: - fo.seek(src.offset) - bytes_read = 0 - while (n := fo.readinto(dest[bytes_read:])) is not None and n > 0: bytes_read += n - else: - dest[:] = src._buf() - - def _copyout_sharded(self, src:DiskBuffer, size:int, _get_free_buf:Callable, seg_len:int) -> Generator[tuple[int, int, int, int], None, None]: - assert hasattr(DiskDevice, 'io_uring'), "function requires io uring support" - - fd_offset = src.offset - (minor_offset := src.offset % mmap.PAGESIZE) - processed_reqs_cnt, copied_in, next_read_offset, total_copy_size = 0, 0, 0, round_up(size + minor_offset, mmap.PAGESIZE) - reqs: list[tuple[int, int, int, int]] = [] - - while next_read_offset < total_copy_size or len(reqs) != processed_reqs_cnt: - if next_read_offset < total_copy_size and (copy_batch := _get_free_buf()) is not None: - # Prepare sqe - sqe_index = (tail:=DiskDevice.io_uring.sq.ktail[0]) & DiskDevice.io_uring.sq.kring_mask[0] - sqe = DiskDevice.io_uring.sq.sqes[sqe_index] - sqe.opcode, sqe.fd, sqe.off = io_uring.IORING_OP_READ, self.dev.fd, fd_offset + next_read_offset - sqe.addr, sqe.len, sqe.user_data = copy_batch[0], min(seg_len, total_copy_size - next_read_offset), len(reqs) - - # Send sqe - DiskDevice.io_uring.sq.array[sqe_index] = sqe_index - DiskDevice.io_uring.sq.ktail[0] = tail + 1 - libc.syscall(io_uring.NR_io_uring_enter, DiskDevice.io_uring.ring_fd, 1, 1, io_uring.IORING_ENTER_GETEVENTS) - - reqs.append((copy_batch, copied_in, minor_offset, real_copy_size:=min(sqe.len - minor_offset, size - copied_in))) - next_read_offset += sqe.len - copied_in += real_copy_size - minor_offset = 0 - - if (head:=DiskDevice.io_uring.cq.khead[0]) != DiskDevice.io_uring.cq.ktail[0]: - cqe = DiskDevice.io_uring.cq.cqes[head & DiskDevice.io_uring.cq.kring_mask[0]] - assert cqe.res >= 0, f"read from disk failed, err: {cqe.res}" - yield reqs[cqe.user_data] - DiskDevice.io_uring.cq.khead[0] = head + 1 # advance - processed_reqs_cnt += 1 - - def _offset(self, buf:DiskBuffer, size:int, offset:int): return DiskBuffer(buf.device, size, offset) diff --git a/tinygrad/tinygrad/runtime/ops_dsp.py b/tinygrad/tinygrad/runtime/ops_dsp.py deleted file mode 100644 index ccbdda24..00000000 --- a/tinygrad/tinygrad/runtime/ops_dsp.py +++ /dev/null @@ -1,305 +0,0 @@ -from __future__ import annotations -import ctypes, os, mmap, tempfile, pathlib, array, functools, threading, contextlib, sys, subprocess, struct -assert sys.platform != 'win32' -from tinygrad.device import BufferSpec, Compiled, Allocator, Compiler, MallocAllocator -from tinygrad.dtype import dtypes, DType, PtrDType -from tinygrad.uop.ops import Ops, UOp -from tinygrad.helpers import from_mv, getenv, round_up, mv_address, to_mv, cpu_objdump, DEBUG -from tinygrad.renderer.cstyle import ClangRenderer -from tinygrad.runtime.autogen import libc, qcom_dsp -if getenv("IOCTL"): import extra.dsp.run # noqa: F401 # pylint: disable=unused-import - -from tinygrad.uop.ops import PatternMatcher, UPat - -dsp_pm = PatternMatcher([ - (((UPat.var('x').maximum(0) ^ -1).maximum(-256) ^ -1).cast(dtypes.uchar.vec(128)), - lambda x: UOp(Ops.CUSTOM, dtypes.uchar.vec(128), src=tuple(x.gep(tuple(range(i, i+32))) for i in range(0, 128, 32)), - arg="__builtin_HEXAGON_V6_vpackhub_sat_128B(__builtin_HEXAGON_V6_vpackwh_sat_128B({3}, {2}), __builtin_HEXAGON_V6_vpackwh_sat_128B({1}, {0}))")), - (UPat(Ops.GEP, name="x"), lambda x: UOp(Ops.CUSTOM, x.dtype, x.src+x.src, - "__builtin_shufflevector({0}, {1}, "+','.join([str(y) for y in x.arg])+")") if len(x.arg) > 1 and x.src[0].dtype.count > 1 else None), -]) - -dsp_pm_late = PatternMatcher([ - (UPat.var("x")+UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x+UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), - (UPat.var("x")*UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x*UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), - (UPat.var("x")//UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x//UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), - (UPat(Ops.DEFINE_ACC, src=(UPat(Ops.VECTORIZE, src=UPat(Ops.CONST, arg=0)),), dtype=dtypes.uchar.vec(128), name="d", allow_any_len=True), - lambda d: d.replace(src=(UOp(Ops.CUSTOMI, d.dtype, arg="__builtin_HEXAGON_V6_vd0_128B()"),)+d.src[1:])), -]) - -# NOTE: this just increases readability of the generated code -dsp_string = PatternMatcher([ - (UPat(Ops.CONST, (dtypes.int8, dtypes.uint8), name="x"), lambda ctx,x: str(x.arg)), -]) - -class DSPRenderer(ClangRenderer): - device = "DSP" - supports_float4 = True - buffer_suffix = " restrict __attribute__((align_value(128)))" - kernel_typedef = "__attribute__((noinline)) void" - pre_matcher = dsp_pm - extra_matcher = dsp_pm_late+ClangRenderer.extra_matcher - string_rewrite = dsp_string+ClangRenderer.string_rewrite - type_map = { **ClangRenderer.type_map, dtypes.uint64: "unsigned long long", dtypes.int64: "long long" } - code_for_op = {k:v for k,v in ClangRenderer.code_for_op.items() if k != Ops.SQRT} - - def _render_defines(self, uops) -> list[str]: - return ['''/* DSP boilerplate */ struct dcvs_v2_req { int type; int _pad; _Bool dcvs_enable; char dcvs_option; _Bool set_latency; int latency; - _Bool set_dcvs_params; short _pad2; char target_corner; char min_corner; char max_corner; int _pad3[3];};''','int HAP_power_set(void*, void*);', - 'typedef union { struct { void *pv; unsigned int len; } buf; struct { int fd; unsigned int offset; } dma; } remote_arg;', - 'void* HAP_mmap(void *addr, int len, int prot, int flags, int fd, long offset);', 'int HAP_munmap(void *addr, int len);', - 'unsigned long long HAP_perf_get_time_us(void);'] + super()._render_defines(uops) - - def _render_entry(self, function_name:str, bufs:list[tuple[str,tuple[DType,bool]]]) -> str: - msrc = ['int entry(unsigned long long handle, unsigned int sc, remote_arg* pra) {', - 'struct dcvs_v2_req req = {.type=7, .dcvs_enable=0, .set_latency=1, .latency=100, .set_dcvs_params=1, .target_corner = 6 /* TURBO */};', - 'HAP_power_set((void*)handle, (void*)&req);'] - msrc += ['if ((sc>>24) != 2) return 0;'] - msrc += [f'int sz_or_val_{i} = ((int*)pra[0].buf.pv)[{i}];' for i,b in enumerate(bufs)] - msrc += [f'int off{i} = ((int*)pra[1].buf.pv)[{i}];' for i,b in enumerate(bufs) if isinstance(b[1][0], PtrDType)] - msrc += [f'void *buf_{i} = HAP_mmap(0,sz_or_val_{i},3,0,pra[{i+3}].dma.fd,0)+off{i};' for i,b in enumerate(bufs) if isinstance(b[1][0], PtrDType)] - msrc += ["unsigned long long start = HAP_perf_get_time_us();"] - msrc += [f"{function_name}({', '.join([(f'buf_{i}' if isinstance(b[1][0], PtrDType) else f'sz_or_val_{i}') for i,b in enumerate(bufs)])});"] - msrc += ["*(unsigned long long *)(pra[2].buf.pv) = HAP_perf_get_time_us() - start;"] - msrc += [f'HAP_munmap(buf_{i}, sz_or_val_{i});' for i,b in enumerate(bufs) if isinstance(b[1][0], PtrDType)] - msrc += ["return 0; }"] - return '\n'.join(msrc) - -def rpc_sc(method=0, ins=0, outs=0, fds=0): return (method << 24) | (ins << 16) | (outs << 8) | fds -def rpc_prep_args(ins=None, outs=None, in_fds=None): - ins, outs, in_fds = ins or list(), outs or list(), in_fds or list() - - pra = (qcom_dsp.union_remote_arg * (len(ins) + len(outs) + len(in_fds)))() - fds = (ctypes.c_int32 * (len(ins) + len(outs) + len(in_fds)))(*([-1] * (len(ins) + len(outs))), *in_fds) - attrs = (ctypes.c_uint32 * (len(ins) + len(outs) + len(in_fds)))(*([0] * (len(ins) + len(outs))), *([1] * (len(in_fds)))) - - for i, mv in enumerate(ins + outs): pra[i].buf.pv, pra[i].buf.len = mv_address(mv) if mv.nbytes > 0 else 0, mv.nbytes - return pra, fds, attrs, (ins, outs) - -class DSPProgram: - def __init__(self, dev:DSPDevice, name:str, lib:bytes): - self.dev, self.lib = dev, lib - - def __call__(self, *bufs, vals:tuple[int, ...]=(), wait=False): - if len(bufs) >= 16: raise RuntimeError(f"Too many buffers to execute: {len(bufs)}") - - pra, fds, attrs, _ = rpc_prep_args(ins=[var_vals_mv:=memoryview(bytearray((len(bufs)+len(vals))*4)), off_mv:=memoryview(bytearray(len(bufs)*4))], - outs=[timer:=memoryview(bytearray(8)).cast('Q')], in_fds=[b.share_info.fd for b in bufs]) - var_vals_mv.cast('i')[:] = array.array('i', tuple(b.size for b in bufs) + vals) - off_mv.cast('I')[:] = array.array('I', tuple(b.offset for b in bufs)) - self.dev.exec_lib(self.lib, rpc_sc(method=2, ins=2, outs=1, fds=len(bufs)), pra, fds, attrs) - return timer[0] / 1e6 - -class DSPBuffer: - def __init__(self, va_addr:int, size:int, share_info, offset:int=0): - self.va_addr, self.size, self.share_info, self.offset = va_addr, size, share_info, offset - -class DSPAllocator(Allocator['DSPDevice']): - def _alloc(self, size:int, options:BufferSpec): - b = qcom_dsp.ION_IOC_ALLOC(self.dev.ion_fd, len=size, align=0x200, heap_id_mask=1< memoryview: return to_mv(src.va_addr, src.size) - def _copyin(self, dest:DSPBuffer, src:memoryview): ctypes.memmove(dest.va_addr, from_mv(src), src.nbytes) - def _copyout(self, dest:memoryview, src:DSPBuffer): ctypes.memmove(from_mv(dest), src.va_addr, dest.nbytes) - def _offset(self, buf, size:int, offset:int): return DSPBuffer(buf.va_addr+offset, size, buf.share_info, buf.offset+offset) - -class ClangCompiler(Compiler): - def __init__(self, cachekey="compile_clang", args:list[str]|None=None, objdump_tool='objdump'): - self.args = ['-shared', '-march=native'] if args is None else args - self.objdump_tool = objdump_tool - super().__init__(cachekey) - - def compile(self, src:str) -> bytes: - # TODO: remove file write. sadly clang doesn't like the use of /dev/stdout here - with tempfile.NamedTemporaryFile(delete=True) as output_file: - subprocess.check_output([getenv("CC", 'clang'), *self.args, '-O2', '-Wall', '-Werror', '-x', 'c', '-fPIC', '-ffreestanding', '-nostdlib', - '-', '-o', str(output_file.name)], input=src.encode('utf-8')) - return pathlib.Path(output_file.name).read_bytes() - - def disassemble(self, lib:bytes): return cpu_objdump(lib, self.objdump_tool) - -class DSPDevice(Compiled): - def __init__(self, device:str=""): - compiler_args = ["--target=hexagon", "-mcpu=hexagonv65", "-fuse-ld=lld", "-nostdlib", "-mhvx=v65", "-mhvx-length=128b"] - if getenv("MOCKDSP"): - super().__init__(device, MallocAllocator, MockDSPRenderer(), ClangCompiler(None, ["-static"] + compiler_args, 'llvm-objdump'), MockDSPProgram) - else: - self.ion_fd = os.open('/dev/ion', os.O_RDONLY) - # Generate link script to pass into clang. Aligning all used sections to 4k fixes invoke problem. - sections = ['text', 'rela.plt', 'rela.dyn', 'plt', 'data', 'bss', 'hash', 'dynamic', - 'got', 'got.plt', 'dynsym', 'dynstr', 'symtab', 'shstrtab', 'strtab'] - sections_link = '\n'.join([f'.{n} : ALIGN(4096) {{ *(.{n}) }}' for n in sections]) - with tempfile.NamedTemporaryFile(delete=False) as self.link_ld: - self.link_ld.write(f"SECTIONS {{ . = 0x0; {sections_link}\n /DISCARD/ : {{ *(.note .note.* .gnu.hash .comment) }} }}".encode()) - self.link_ld.flush() - - from tinygrad.runtime.graph.cpu import CPUGraph - super().__init__(device, DSPAllocator(self), DSPRenderer(), - ClangCompiler("compile_dsp", ["-shared"] + compiler_args + [f"-T{self.link_ld.name}"], 'llvm-objdump'), functools.partial(DSPProgram, self), - functools.partial(CPUGraph, self)) - fastrpc_shell = memoryview(bytearray(pathlib.Path('/dsp/cdsp/fastrpc_shell_3').read_bytes())) - self.shell_buf = self.allocator.alloc(round_up(fastrpc_shell.nbytes, 0x1000), BufferSpec(nolru=True)) - ctypes.memmove(self.shell_buf.va_addr, mv_address(fastrpc_shell), fastrpc_shell.nbytes) - - self.init_dsp() - RPCListener(self).start() - - def open_lib(self, lib): - self.binded_lib, self.binded_lib_off = lib, 0 - fp = "file:///tinylib?entry&_modver=1.0&_dom=cdsp\0" - pra, _, _, _ = rpc_prep_args(ins=[memoryview(array.array('I', [len(fp), 0xff])), memoryview(bytearray(fp.encode()))], - outs=[o1:=memoryview(bytearray(0x8)), o2:=memoryview(bytearray(0xff))]) - qcom_dsp.FASTRPC_IOCTL_INVOKE(self.rpc_fd, handle=0, sc=rpc_sc(method=0, ins=2, outs=2), pra=pra) - if o1.cast('i')[1] < 0: raise RuntimeError(f"Cannot open lib: {o2.tobytes().decode()}") - return o1.cast('I')[0] - - def close_lib(self, handle): - pra, _, _, _ = rpc_prep_args(ins=[memoryview(array.array('I', [handle, 0xff]))], outs=[memoryview(bytearray(0x8)), memoryview(bytearray(0xff))]) - qcom_dsp.FASTRPC_IOCTL_INVOKE(self.rpc_fd, handle=0, sc=rpc_sc(method=1, ins=1, outs=2), pra=pra) - - def exec_lib(self, lib, sc, args, fds, attrs): - def _exec_lib(): - handle = self.open_lib(lib) - qcom_dsp.FASTRPC_IOCTL_INVOKE_ATTRS(self.rpc_fd, fds=fds, attrs=attrs, inv=qcom_dsp.struct_fastrpc_ioctl_invoke(handle=handle, sc=sc, pra=args)) - self.close_lib(handle) - try: _exec_lib() - except (OSError, PermissionError): - # DSP might ask for a connection reset or just fail with operation not permitted, try to reset connection. - self.init_dsp() - try: _exec_lib() - except (OSError, PermissionError) as e: raise RuntimeError(e) - - def init_dsp(self): - if hasattr(self, 'rpc_fd'): - with contextlib.suppress(OSError): - qcom_dsp.FASTRPC_IOCTL_INVOKE(self.rpc_fd, handle=4, sc=rpc_sc(method=2, ins=0, outs=0)) # pylint: disable=access-member-before-definition - os.close(self.rpc_fd) # pylint: disable=access-member-before-definition - - self.rpc_fd: int = os.open('/dev/adsprpc-smd', os.O_RDONLY | os.O_NONBLOCK) - qcom_dsp.FASTRPC_IOCTL_GETINFO(self.rpc_fd, 3) - qcom_dsp.FASTRPC_IOCTL_CONTROL(self.rpc_fd, req=0x3) - qcom_dsp.FASTRPC_IOCTL_INIT(self.rpc_fd, flags=0x1, file=self.shell_buf.va_addr, filelen=self.shell_buf.size, filefd=self.shell_buf.share_info.fd) - qcom_dsp.FASTRPC_IOCTL_INVOKE(self.rpc_fd, handle=3, sc=rpc_sc(method=3, ins=0, outs=0)) - -class RPCListener(threading.Thread): - def __init__(self, device:DSPDevice): - super().__init__() - self.device, self.daemon = device, True - - def run(self): - # Setup initial request arguments. - context, status, TINYFD = 0, 0xffffffff, 0xffff - req_args, _, _, _ = rpc_prep_args(ins=[msg_send:=memoryview(bytearray(0x10)).cast('I'), out_buf:=memoryview(bytearray(0x10000)).cast('I')], - outs=[msg_recv:=memoryview(bytearray(0x10)).cast('I'), in_buf:=memoryview(bytearray(0x10000)).cast('I')]) - req_args[1].buf.len = 0 - - while True: - # Update message request and send it. - msg_send[:] = array.array('I', [context, status, req_args[1].buf.len, in_buf.nbytes]) - - try: qcom_dsp.FASTRPC_IOCTL_INVOKE(self.device.rpc_fd, handle=0x3, sc=0x04020200, pra=req_args) - except OSError: continue # retry - - context, inbufs, outbufs = msg_recv[0], ((sc:=msg_recv[2]) >> 16) & 0xff, (msg_recv[2] >> 8) & 0xff - - in_ptr, out_ptr, objs = mv_address(in_buf), mv_address(out_buf), [] - for i in range(inbufs + outbufs): - obj_ptr = round_up(in_ptr + 4, 8) if i < inbufs else round_up(out_ptr + 4, 8) - objs.append(to_mv(obj_ptr, obj_size:=to_mv(in_ptr, 4).cast('I')[0])) - if i < inbufs: in_ptr = obj_ptr + obj_size - else: - to_mv(out_ptr, 4).cast('I')[0] = obj_size - out_ptr = obj_ptr + obj_size - in_ptr += 4 - - in_args, out_args = objs[:inbufs], objs[inbufs:] - req_args[1].buf.len = out_ptr - mv_address(out_buf) - - status = 0 # reset status, will set if error - if sc == 0x20200: pass # greating - elif sc == 0x13050100: # open - try: out_args[0].cast('I')[0] = TINYFD if (name:=in_args[3].tobytes()[:-1].decode()) == "tinylib" else os.open(name, os.O_RDONLY) - except OSError: status = 1 - elif sc == 0x3010000: - if (fd:=in_args[0].cast('I')[0]) != TINYFD: os.close(fd) - elif sc == 0x9010000: # seek - if (fd:=in_args[0].cast('I')[0]) == TINYFD: - assert in_args[0].cast('I')[2] == qcom_dsp.APPS_STD_SEEK_SET, "Supported only SEEK_SET" - res, self.device.binded_lib_off = 0, in_args[0].cast('I')[1] - else: res = os.lseek(fd, in_args[0].cast('I')[1], in_args[0].cast('I')[2]) - status = 0 if res >= 0 else res - elif sc == 0x4010200: # read - if (fd:=in_args[0].cast('I')[0]) == TINYFD: - buf = self.device.binded_lib[self.device.binded_lib_off:self.device.binded_lib_off+in_args[0].cast('I')[1]] - self.device.binded_lib_off += len(buf) - else: buf = os.read(fd, in_args[0].cast('I')[1]) - out_args[1][:len(buf)] = buf - out_args[0].cast('I')[0:2] = array.array('I', [len(buf), int(len(buf) == 0)]) - elif sc == 0x1f020100: # stat - stat = os.stat(in_args[1].tobytes()[:-1].decode()) - out_stat = qcom_dsp.struct_apps_std_STAT.from_address(mv_address(out_args[0])) - for f in out_stat._fields_: out_stat.__setattr__(f[0], int(getattr(stat, f"st_{f[0]}", 0))) - elif sc == 0x2010100: # mmap - st = qcom_dsp.FASTRPC_IOCTL_MMAP(self.device.rpc_fd, fd=-1, flags=in_args[0].cast('I')[2], vaddrin=0, size=in_args[0].cast('Q')[3]) - out_args[0].cast('Q')[0:2] = array.array('Q', [0, st.vaddrout]) - else: raise RuntimeError(f"Unknown op: {sc=:X}") - -# ***** mock DSP ***** - -mockdsp_boilerplate = '''/* DSP boilerplate */ static long syscall(long r0, long r1, long r2, long r3, long r4, long r5, long r6) { -long retval; __asm__ volatile("r0 = %1; r1 = %2; r2 = %3; r3 = %4; r4 = %5; r5 = %6; r6 = %7; trap0(#1); %0 = r0" : "=r" (retval) - : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5), "r" (r6) : "r0", "r1", "r2", "r3", "r4", "r5", "r6"); return retval; } -static int read(int fd, void* buf, int len) {{ return syscall(fd, (long)buf, len, 0, 0, 0, 63); }} -static int write(int fd, void* buf, int len) {{ return syscall(fd, (long)buf, len, 0, 0, 0, 64); }} -static int exit(int ret) {{ return syscall(ret, 0, 0, 0, 0, 0, 93); }} -static unsigned int inscount(void) {{ unsigned int ret; __asm__ volatile(".word 0x6a15c000; %0 = R0" : "=r" (ret) : : "r0"); return ret; }} -static void *mmap2(void *addr, unsigned int length, int prot, int flags, int fd, unsigned long offset) {{ -return (void*)syscall((long)addr, length, prot, flags, fd, offset, 222); }}''' - -class MockDSPRenderer(DSPRenderer): - def _render_defines(self, uops) -> list[str]: return ClangRenderer._render_defines(self, uops) - def _render_entry(self, function_name:str, bufs:list[tuple[str,tuple[DType,bool]]]) -> str: - # https://gpages.juszkiewicz.com.pl/syscalls-table/syscalls.html - # control register 21 is HEX_REG_QEMU_INSN_CNT, 0x6a15c000 loads it - msrc = [mockdsp_boilerplate, 'void _start(void) {'] - for i,b in enumerate(bufs): - if isinstance(b[1][0], PtrDType): - sz = b[1][0].size*b[1][0].itemsize - # for loop for big reads - msrc.append(f"void *buf{i} = mmap2(0, {sz}, 3, 0x21, -1, 0); for(int rd = 0; rd < {sz}; rd += read(0, buf{i}+rd, {sz}-rd));") - else: - msrc.append(f"unsigned int val{i}; read(0, &val{i}, 4);") - msrc.append("unsigned int st = inscount();") - msrc.append(f"{function_name}({', '.join([(f'(void*)buf{i}' if isinstance(b[1][0], PtrDType) else f'val{i}') for i,b in enumerate(bufs)])});") - msrc.append("unsigned int et = inscount() - st; write(1, &et, sizeof(et));") - for i,b in enumerate(bufs): - if isinstance(b[1][0], PtrDType): msrc.append(f"write(1, buf{i}, {b[1][0].size*b[1][0].itemsize});") - msrc.append('exit(0); }') - return '\n'.join(msrc) - -class MockDSPProgram: - def __init__(self, name:str, lib:bytes): self.lib = lib - def __call__(self, *bufs, vals:tuple[int, ...]=(), wait=False): - with tempfile.NamedTemporaryFile(suffix=".out") as dsp_lib: - dsp_lib.write(self.lib) - dsp_lib.flush() - os.chmod(dsp_lib.name, 0o0777) - # NOTE: this timing includes a docker launch - proc = subprocess.run(["docker", "run", "--rm", "-i", "-v", f"{os.path.abspath(os.path.dirname(dsp_lib.name))}:/work", "-w", "/work", - "qemu-hexagon", "-c", f"qemu-hexagon {'-strace' if DEBUG >= 5 else ''} /work/"+os.path.basename(dsp_lib.name)], - input=b''.join([bytes(x) for x in bufs] + [struct.pack("I", x) for x in vals]), stdout=subprocess.PIPE, check=True) - offset = 4 - for x in bufs: - x[:] = proc.stdout[offset:offset+len(x)] - offset += len(x) - assert offset == len(proc.stdout) - return struct.unpack("I", proc.stdout[0:4])[0] / 1e9 # pretend it's 1 Ghz, but this is an inscount, not a time diff --git a/tinygrad/tinygrad/runtime/ops_gpu.py b/tinygrad/tinygrad/runtime/ops_gpu.py deleted file mode 100644 index 0a8304d8..00000000 --- a/tinygrad/tinygrad/runtime/ops_gpu.py +++ /dev/null @@ -1,117 +0,0 @@ -from __future__ import annotations -from typing import Optional, cast -import ctypes, functools, hashlib -from tinygrad.runtime.autogen import opencl as cl -from tinygrad.helpers import init_c_var, to_char_p_p, from_mv, OSX, DEBUG, getenv, mv_address -from tinygrad.renderer.cstyle import OpenCLRenderer, IntelRenderer -from tinygrad.device import BufferSpec, LRUAllocator, Compiled, Compiler, CompileError - -# see test/external/external_osx_profiling.py to determine this ratio. it's in like GPU clocks or something -OSX_TIMING_RATIO = (125/3) if OSX else 1.0 - -cl_errors = {attr: k for k in dir(cl) if k.startswith("CL_") and isinstance(attr:=getattr(cl, k), int) and attr <= 0} -def check(status): - if status != 0: raise RuntimeError(f"OpenCL Error {status}: {cl_errors.get(status, 'Unknown error')}") -def checked(ret, status): return (check(status.value), ret)[1] - -class CLCompiler(Compiler): - def __init__(self, dev:CLDevice, compile_key:str): - self.dev = dev - super().__init__(f"compile_cl_{compile_key}") - def compile(self, src:str) -> bytes: - program = checked(cl.clCreateProgramWithSource(self.dev.context, 1, to_char_p_p([src.encode()]), None, status := ctypes.c_int32()), status) - build_status: int = cl.clBuildProgram(program, 1, self.dev.device_id, None, cl.clBuildProgram.argtypes[4](), None) - if build_status != 0: - cl.clGetProgramBuildInfo(program, self.dev.device_id, cl.CL_PROGRAM_BUILD_LOG, 0, None, log_size := ctypes.c_size_t()) - cl.clGetProgramBuildInfo(program, self.dev.device_id, cl.CL_PROGRAM_BUILD_LOG, log_size.value, mstr := ctypes.create_string_buffer(log_size.value), None) # noqa: E501 - raise CompileError(f"OpenCL Compile Error\n\n{mstr.value.decode()}") - check(cl.clGetProgramInfo(program, cl.CL_PROGRAM_BINARY_SIZES, ctypes.sizeof(ctypes.c_size_t), binary_sizes := (ctypes.c_size_t * 1)(), None)) - check(cl.clGetProgramInfo(program, cl.CL_PROGRAM_BINARIES, ctypes.sizeof(ctypes.c_void_p), (ctypes.c_void_p * 1)(ctypes.addressof(binary := ctypes.create_string_buffer(binary_sizes[0]))), None)) # noqa: E501 - check(cl.clReleaseProgram(program)) - return bytes(binary) - -class CLProgram: - def __init__(self, device:CLDevice, name:str, lib:bytes): - self.dev, self.name, self.lib = device, name, lib - self.program = checked(cl.clCreateProgramWithBinary(device.context, 1, device.device_id, (ctypes.c_size_t * 1)(len(lib)), - to_char_p_p([lib], ctypes.c_ubyte), binary_status := ctypes.c_int32(), - errcode_ret := ctypes.c_int32()), errcode_ret) - check(binary_status.value) - check(cl.clBuildProgram(self.program, 1, device.device_id, None, cl.clBuildProgram.argtypes[4](), None)) # NOTE: OSX requires this - self.kernel = checked(cl.clCreateKernel(self.program, name.encode(), status := ctypes.c_int32()), status) - - def __del__(self): - try: check(cl.clReleaseKernel(self.kernel)) - except (TypeError, AttributeError): pass - try: check(cl.clReleaseProgram(self.program)) - except (TypeError, AttributeError): pass - - def __call__(self, *bufs:tuple[ctypes._CData, BufferSpec], global_size:tuple[int,int,int]=(1,1,1), local_size:Optional[tuple[int,int,int]]=None, vals:tuple[int, ...]=(), wait=False) -> Optional[float]: # noqa: E501 - for i,(b,_) in enumerate(bufs): cl.clSetKernelArg(self.kernel, i, ctypes.sizeof(b), ctypes.byref(b)) - for i,v in enumerate(vals,start=len(bufs)): cl.clSetKernelArg(self.kernel, i, 4, ctypes.byref(ctypes.c_int32(v))) - if local_size is not None: global_size = cast(tuple[int,int,int], tuple(int(g*l) for g,l in zip(global_size, local_size))) - event = cl.cl_event() if wait else None - check(cl.clEnqueueNDRangeKernel(self.dev.queue, self.kernel, len(global_size), None, (ctypes.c_size_t * len(global_size))(*global_size), (ctypes.c_size_t * len(local_size))(*local_size) if local_size else None, 0, None, event)) # noqa: E501 - if wait: - assert event is not None - check(cl.clWaitForEvents(1, event)) - check(cl.clGetEventProfilingInfo(event, cl.CL_PROFILING_COMMAND_START, 8, ctypes.byref(start := ctypes.c_uint64()), None)) - check(cl.clGetEventProfilingInfo(event, cl.CL_PROFILING_COMMAND_END, 8, ctypes.byref(end := ctypes.c_uint64()), None)) - return float(end.value-start.value) * OSX_TIMING_RATIO * 1e-9 - return None - -class CLAllocator(LRUAllocator['CLDevice']): - def _alloc(self, size:int, options:BufferSpec) -> tuple[ctypes._CData, BufferSpec]: - if options.image is not None: - return (checked(cl.clCreateImage2D(self.dev.context, cl.CL_MEM_READ_WRITE, - cl.cl_image_format(cl.CL_RGBA, {2: cl.CL_HALF_FLOAT, 4: cl.CL_FLOAT}[options.image.itemsize]), - options.image.shape[1], options.image.shape[0], 0, None, status := ctypes.c_int32()), status), options) - return (checked(cl.clCreateBuffer(self.dev.context, cl.CL_MEM_READ_WRITE, size, None, status := ctypes.c_int32()), status), options) - def _free(self, opaque:tuple[ctypes._CData, BufferSpec], options:BufferSpec): - try: check(cl.clReleaseMemObject(opaque[0])) - except AttributeError: pass - def _copyin(self, dest:tuple[ctypes._CData, BufferSpec], src:memoryview): - if dest[1].image is not None: - check(cl.clEnqueueWriteImage(self.dev.queue, dest[0], False, (ctypes.c_size_t * 3)(0,0,0), - (ctypes.c_size_t * 3)(dest[1].image.shape[1],dest[1].image.shape[0],1), 0, 0, from_mv(src), 0, None, None)) - else: - if mv_address(src) % 16: src = memoryview(bytearray(src)) - check(cl.clEnqueueWriteBuffer(self.dev.queue, dest[0], False, 0, len(src)*src.itemsize, from_mv(src), 0, None, None)) - self.dev.pending_copyin.append(src) # NOTE: these can't be freed until the GPU actually executes this command - def _copyout(self, dest:memoryview, src:tuple[ctypes._CData, BufferSpec]): - if src[1].image is not None: - check(cl.clEnqueueReadImage(self.dev.queue, src[0], False, (ctypes.c_size_t * 3)(0,0,0), - (ctypes.c_size_t * 3)(src[1].image.shape[1],src[1].image.shape[0],1), 0, 0, from_mv(dest), 0, None, None)) - else: - check(cl.clEnqueueReadBuffer(self.dev.queue, src[0], False, 0, len(dest)*dest.itemsize, from_mv(dest), 0, None, None)) - self.dev.synchronize() - -class CLDevice(Compiled): - device_ids = None # this is global and only initted once - def __init__(self, device:str=""): - if CLDevice.device_ids is None: - check(cl.clGetPlatformIDs(0, None, num_platforms := ctypes.c_uint32())) - check(cl.clGetPlatformIDs(num_platforms.value, platform_ids := (cl.cl_platform_id * num_platforms.value)(), None)) - for device_type in [cl.CL_DEVICE_TYPE_GPU, cl.CL_DEVICE_TYPE_DEFAULT]: - err = cl.clGetDeviceIDs(platform_ids[0], device_type, 0, None, num_devices := ctypes.c_uint32()) - if err == 0 and num_devices.value != 0: break - if DEBUG >= 1: print(f"CLDevice: got {num_platforms.value} platforms and {num_devices.value} devices") - CLDevice.device_ids = init_c_var((cl.cl_device_id * num_devices.value)(), lambda x: check(cl.clGetDeviceIDs(platform_ids[0], device_type, num_devices, x, None))) # noqa: E501 - - self.device_id = CLDevice.device_ids[0 if ":" not in device else int(device.split(":")[1])] - self.device_name = (cl.clGetDeviceInfo(self.device_id, cl.CL_DEVICE_NAME, 256, buf := ctypes.create_string_buffer(256), None), buf.value.decode())[1] # noqa: E501 - self.driver_version = (cl.clGetDeviceInfo(self.device_id, cl.CL_DRIVER_VERSION, 256, buf := ctypes.create_string_buffer(256), None), buf.value.decode())[1] # noqa: E501 - if DEBUG >= 1: print(f"CLDevice: opening {self.device_name} with version {self.driver_version}") - self.context = checked(cl.clCreateContext(None, 1, self.device_id, cl.clCreateContext.argtypes[3](), None, status := ctypes.c_int32()), status) - self.queue = checked(cl.clCreateCommandQueue(self.context, self.device_id, cl.CL_QUEUE_PROFILING_ENABLE, status), status) - self.pending_copyin: list[memoryview] = [] - self.device_exts = (cl.clGetDeviceInfo(self.device_id, cl.CL_DEVICE_EXTENSIONS, 4096, ctypes.byref(buf := ctypes.create_string_buffer(4096)), ctypes.byref(total := ctypes.c_size_t())), ctypes.string_at(buf, size=total.value).decode())[1] # noqa: E501 - - compile_key = hashlib.md5(self.device_name.encode() + self.driver_version.encode()).hexdigest() - renderer = IntelRenderer() if "cl_intel_subgroup_matrix_multiply_accumulate" in self.device_exts and getenv("INTEL") else OpenCLRenderer() - super().__init__(device, CLAllocator(self), renderer, CLCompiler(self, f"compile_cl_{compile_key}"), functools.partial(CLProgram, self)) - def synchronize(self): - check(cl.clFinish(self.queue)) - self.pending_copyin.clear() - -GPUDevice = CLDevice # for legacy reasons diff --git a/tinygrad/tinygrad/runtime/ops_hip.py b/tinygrad/tinygrad/runtime/ops_hip.py deleted file mode 100644 index d26a91d2..00000000 --- a/tinygrad/tinygrad/runtime/ops_hip.py +++ /dev/null @@ -1,63 +0,0 @@ -import ctypes, functools -from tinygrad.helpers import init_c_var, from_mv, init_c_struct_t, getenv -from tinygrad.device import Compiled, LRUAllocator, BufferSpec -from tinygrad.runtime.autogen import hip -from tinygrad.runtime.support.compiler_amd import HIPCompiler -from tinygrad.renderer.cstyle import HIPRenderer -if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 # pylint: disable=unused-import - -def check(status): - if status != 0: raise RuntimeError(f"HIP Error {status}, {ctypes.string_at(hip.hipGetErrorString(status)).decode()}") - -class HIPDevice(Compiled): - def __init__(self, device:str=""): - self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.arch = init_c_var(hip.hipDeviceProp_t(), lambda x: check(hip.hipGetDeviceProperties(x, self.device_id))).gcnArchName.decode() - self.time_event_st, self.time_event_en = [init_c_var(hip.hipEvent_t(), lambda x: hip.hipEventCreate(ctypes.byref(x), 0)) for _ in range(2)] - super().__init__(device, HIPAllocator(self), HIPRenderer(self.arch), HIPCompiler(self.arch), functools.partial(HIPProgram, self)) - def synchronize(self): - check(hip.hipSetDevice(self.device_id)) - check(hip.hipDeviceSynchronize()) - -class HIPProgram: - def __init__(self, dev:HIPDevice, name:str, lib:bytes): - self.dev, self.name, self.lib = dev, name, lib - check(hip.hipSetDevice(self.dev.device_id)) - self.module = init_c_var(hip.hipModule_t(), lambda x: check(hip.hipModuleLoadData(ctypes.byref(x), lib))) - self.prg = init_c_var(hip.hipFunction_t(), lambda x: check(hip.hipModuleGetFunction(ctypes.byref(x), self.module, name.encode("utf-8")))) - - def __del__(self): - if hasattr(self, 'module'): check(hip.hipModuleUnload(self.module)) - - def __call__(self, *args, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - check(hip.hipSetDevice(self.dev.device_id)) - if not hasattr(self, "vargs"): - self.c_args = init_c_struct_t(tuple([(f'f{i}', hip.hipDeviceptr_t) for i in range(len(args))] + - [(f'v{i}', ctypes.c_int) for i in range(len(vals))]))(*args, *vals) - self.vargs = (ctypes.c_void_p * 5)(1, ctypes.cast(ctypes.byref(self.c_args), ctypes.c_void_p), 2, - ctypes.cast(ctypes.pointer(ctypes.c_size_t(ctypes.sizeof(self.c_args))), ctypes.c_void_p), 3) - - for i in range(len(args)): self.c_args.__setattr__(f'f{i}', args[i]) - for i in range(len(vals)): self.c_args.__setattr__(f'v{i}', vals[i]) - - if wait: check(hip.hipEventRecord(self.dev.time_event_st, None)) - - check(hip.hipModuleLaunchKernel(self.prg, *global_size, *local_size, 0, None, None, self.vargs)) - - if wait: - check(hip.hipEventRecord(self.dev.time_event_en, None)) - check(hip.hipEventSynchronize(self.dev.time_event_en)) - check(hip.hipEventElapsedTime(ctypes.byref(ret := ctypes.c_float()), self.dev.time_event_st, self.dev.time_event_en)) - return ret.value * 1e-3 - -class HIPAllocator(LRUAllocator[HIPDevice]): - def _alloc(self, size:int, options:BufferSpec): - check(hip.hipSetDevice(self.dev.device_id)) - return init_c_var(hip.hipDeviceptr_t(), lambda x: check(hip.hipMalloc(ctypes.byref(x), size))) - def _free(self, opaque, options:BufferSpec): check(hip.hipFree(opaque)) - def _copyin(self, dest, src: memoryview): - check(hip.hipSetDevice(self.dev.device_id)) - check(hip.hipMemcpy(dest, from_mv(src), len(src), hip.hipMemcpyHostToDevice)) - def _copyout(self, dest:memoryview, src): - self.dev.synchronize() - check(hip.hipMemcpy(from_mv(dest), src, len(dest), hip.hipMemcpyDeviceToHost)) diff --git a/tinygrad/tinygrad/runtime/ops_llvm.py b/tinygrad/tinygrad/runtime/ops_llvm.py deleted file mode 100644 index 1c1cb6ba..00000000 --- a/tinygrad/tinygrad/runtime/ops_llvm.py +++ /dev/null @@ -1,75 +0,0 @@ -import functools, ctypes, platform -from tinygrad.device import Compiled, Compiler, MallocAllocator, CPUProgram -from tinygrad.helpers import OSX, getenv, capstone_flatdump, DEBUG -from tinygrad.renderer.llvmir import LLVMRenderer -import tinygrad.runtime.autogen.llvm as llvm -from tinygrad.runtime.support.elf import jit_loader - -def cerr(): return ctypes.pointer(ctypes.pointer(ctypes.c_char())) - -def expect(x, err, ret=None): - if x: raise RuntimeError(llvm.string_cast(err.contents) if not isinstance(err, str) else err) - return ret - -class LLVMCompiler(Compiler): - jit = True - target_arch = {'arm64': 'AArch64', 'aarch64': 'AArch64', 'x86_64': 'X86', 'AMD64': 'X86'}[platform.machine()] - def __init__(self, processor:str, feats:str): - for component in ['Target', 'TargetInfo', 'TargetMC', 'AsmParser', 'AsmPrinter']: getattr(llvm, f'LLVMInitialize{self.target_arch}{component}')() - - triple = {'AArch64': b'aarch64-none-unknown-elf', 'X86': b'x86_64-none-unknown-elf', 'AMDGPU': b'amdgcn-amd-amdhsa'}[self.target_arch] - target = expect(llvm.LLVMGetTargetFromTriple(triple, ctypes.pointer(tgt:=llvm.LLVMTargetRef()), err:=cerr()), err, tgt) - if DEBUG >= 3: print(f"LLVM init for {processor!r} with {feats!r}") - self.target_machine = llvm.LLVMCreateTargetMachine(target, triple, processor.encode(), feats.encode(), - llvm.LLVMCodeGenLevelDefault, llvm.LLVMRelocPIC, llvm.LLVMCodeModelDefault) - - self.pbo = llvm.LLVMCreatePassBuilderOptions() - if (opt:=bool(getenv("LLVMOPT", "1"))): - self.passes = b'default' - llvm.LLVMPassBuilderOptionsSetLoopUnrolling(self.pbo, True) - llvm.LLVMPassBuilderOptionsSetLoopVectorization(self.pbo, True) - llvm.LLVMPassBuilderOptionsSetSLPVectorization(self.pbo, True) - llvm.LLVMPassBuilderOptionsSetVerifyEach(self.pbo, True) - else: - self.passes = b'default' - - self.diag_msgs: list[str] = [] - @ctypes.CFUNCTYPE(None, llvm.LLVMDiagnosticInfoRef, ctypes.c_void_p) - def handle_diag(diag_ref, _arg): - severity = llvm.LLVMGetDiagInfoSeverity(diag_ref) - msg = ctypes.string_at(llvm.LLVMGetDiagInfoDescription(diag_ref)).decode() - if severity == llvm.LLVMDSError: - self.diag_msgs.append(msg) - self.handle_diag = handle_diag - llvm.LLVMContextSetDiagnosticHandler(llvm.LLVMGetGlobalContext(), handle_diag, None) - super().__init__(f"compile_llvm_{self.target_arch}{'_jit' if self.jit else ''}{'_opt' if opt else ''}") - - def __del__(self): llvm.LLVMDisposePassBuilderOptions(self.pbo) - - def compile(self, src:str) -> bytes: - self.diag_msgs.clear() - src_buf = llvm.LLVMCreateMemoryBufferWithMemoryRangeCopy(ctypes.create_string_buffer(src_bytes:=src.encode()), len(src_bytes), b'src') - mod = expect(llvm.LLVMParseIRInContext(llvm.LLVMGetGlobalContext(), src_buf, ctypes.pointer(m:=llvm.LLVMModuleRef()), err:=cerr()), err, m) - expect(llvm.LLVMVerifyModule(mod, llvm.LLVMReturnStatusAction, err:=cerr()), err) - expect(llvm.LLVMRunPasses(mod, self.passes, self.target_machine, self.pbo), 'failed to run passes') - if DEBUG >= 7: print(ctypes.string_at(llvm.LLVMPrintModuleToString(mod)).decode()) - obj_buf = expect(llvm.LLVMTargetMachineEmitToMemoryBuffer(self.target_machine, mod, llvm.LLVMObjectFile, err:=cerr(), - ctypes.pointer(buf:=llvm.LLVMMemoryBufferRef())), err, buf) - llvm.LLVMDisposeModule(mod) - obj = ctypes.string_at(llvm.LLVMGetBufferStart(obj_buf), llvm.LLVMGetBufferSize(obj_buf)) - llvm.LLVMDisposeMemoryBuffer(obj_buf) - if self.diag_msgs: raise RuntimeError("llvm diagnostic: " + "\n".join(self.diag_msgs)) - return jit_loader(obj) if self.jit else obj - - def disassemble(self, lib:bytes): capstone_flatdump(lib) - -class HostLLVMCompiler(LLVMCompiler): - def __init__(self): - # +reserve-x18 here does the same thing as -ffixed-x18 in ops_cpu.py, see comments there for why it's needed on arm osx - cpu, feats = ctypes.string_at(llvm.LLVMGetHostCPUName()), (b'+reserve-x18,' if OSX else b'') + ctypes.string_at(llvm.LLVMGetHostCPUFeatures()) - super().__init__(cpu.decode(), feats.decode()) - -class LLVMDevice(Compiled): - def __init__(self, device:str): - from tinygrad.runtime.graph.cpu import LLVMGraph - super().__init__(device, MallocAllocator, LLVMRenderer(), HostLLVMCompiler(), CPUProgram, functools.partial(LLVMGraph, self)) diff --git a/tinygrad/tinygrad/runtime/ops_metal.py b/tinygrad/tinygrad/runtime/ops_metal.py deleted file mode 100644 index 8a41570f..00000000 --- a/tinygrad/tinygrad/runtime/ops_metal.py +++ /dev/null @@ -1,225 +0,0 @@ -import os, pathlib, struct, ctypes, tempfile, functools, contextlib, decimal, platform -from typing import Any, Union, cast -from tinygrad.helpers import prod, to_mv, getenv, round_up, cache_dir, T, init_c_struct_t, PROFILE -from tinygrad.device import Compiled, Compiler, CompileError, LRUAllocator, cpu_profile, ProfileDeviceEvent, ProfileRangeEvent -from tinygrad.renderer.cstyle import MetalRenderer - -class objc_id(ctypes.c_void_p): # This prevents ctypes from converting response to plain int, and dict.fromkeys() can use it to dedup - def __hash__(self): return hash(self.value) - def __eq__(self, other): return self.value == other.value - -class objc_instance(objc_id): # method with name "new", "alloc" should be freed after use - def __del__(self): - # CPython doesn't make any guarantees about order in which globals (like `msg` or `libobjc`) are destroyed when the interpreter shuts down - # https://github.com/tinygrad/tinygrad/pull/8949 triggered the unlucky ordering which lead to a bunch of errors at exit - # TODO: Why isn't `sys.is_finalizing` working? - if msg is not None and libobjc is not None: msg("release")(self) - -class MTLResourceOptions: - MTLResourceCPUCacheModeDefaultCache = 0 - MTLResourceStorageModeShared = 0 << 4 - -class MTLPipelineOption: - MTLPipelineOptionNone = 0 - -# 13 is requestType that metal uses to compile source code into MTLB, there aren't any docs or symbols. -REQUEST_TYPE_COMPILE = 13 - -libobjc = ctypes.CDLL("/usr/lib/libobjc.dylib") -libmetal = ctypes.CDLL("/System/Library/Frameworks/Metal.framework/Metal") -# Must be loaded for default Metal Device: https://developer.apple.com/documentation/metal/1433401-mtlcreatesystemdefaultdevice?language=objc -ctypes.CDLL("/System/Library/Frameworks/CoreGraphics.framework/CoreGraphics") -libdispatch = ctypes.CDLL("/usr/lib/libSystem.dylib") # libdispatch is part of libSystem on mac -libobjc.objc_getClass.restype = objc_id -libobjc.sel_registerName.restype = objc_id -libmetal.MTLCreateSystemDefaultDevice.restype = objc_instance -libdispatch.dispatch_data_create.restype = objc_instance - -@functools.cache -def msg(selector: str, restype: type[T] = objc_id): # type: ignore [assignment] - resname = libobjc.sel_registerName(selector.encode()) - sender = libobjc["objc_msgSend"] # Using attribute access returns a new reference so setting restype is safe - sender.restype = restype - def _msg(ptr: objc_id, *args: Any) -> T: return sender(ptr, resname, *args) - return _msg - -@functools.cache -def to_ns_str(s: str): return msg("stringWithUTF8String:", objc_instance)(libobjc.objc_getClass(b"NSString"), s.encode()) -def from_ns_str(s): return bytes(msg("UTF8String", ctypes.c_char_p)(s)).decode() - -def to_struct(*t: int, _type: type = ctypes.c_ulong): return init_c_struct_t(tuple([(f"field{i}", _type) for i in range(len(t))]))(*t) - -def wait_check(cbuf: Any): - msg("waitUntilCompleted")(cbuf) - error_check(msg("error", objc_instance)(cbuf)) - -def cmdbuf_label(cbuf: objc_id) -> str|None: return from_ns_str(label) if (label:=msg("label", objc_id)(cbuf)).value is not None else None -def cmdbuf_st_time(cbuf: objc_id) -> float: return cast(float, msg("GPUStartTime", ctypes.c_double)(cbuf)) -def cmdbuf_en_time(cbuf: objc_id) -> float: return cast(float, msg("GPUEndTime", ctypes.c_double)(cbuf)) - -def error_check(error: objc_instance, error_constructor: type[Exception] = RuntimeError): - if error.value is None: return None - raise error_constructor(from_ns_str(msg("localizedDescription", objc_instance)(error))) - -class MetalDevice(Compiled): - def __init__(self, device:str): - self.sysdevice = libmetal.MTLCreateSystemDefaultDevice() - self.mtl_queue = msg("newCommandQueueWithMaxCommandBufferCount:", objc_instance)(self.sysdevice, 1024) - if self.mtl_queue is None: raise RuntimeError("Cannot allocate a new command queue") - self.mtl_buffers_in_flight: list[Any] = [] - self.timeline_signal = msg("newSharedEvent", objc_instance)(self.sysdevice) - self.timeline_value = 0 - - Compiled.profile_events += [ProfileDeviceEvent(device)] - - from tinygrad.runtime.graph.metal import MetalGraph - # NOTE: GitHub CI macOS runners use paravirtualized metal which is broken with graph. - # This can be reproduced locally with any virtualization software (like utm) that can create macOS VMs with apple's own virtualization framework. - super().__init__(device, MetalAllocator(self), MetalRenderer(), MetalCompiler() if getenv("METAL_DIRECT", 1) else Compiler(), - functools.partial(MetalProgram, self), MetalGraph if 'virtual' not in from_ns_str(msg('name')(self.sysdevice)).lower() else None) - - def synchronize(self): - for cbuf in self.mtl_buffers_in_flight: - wait_check(cbuf) - st, en = decimal.Decimal(cmdbuf_st_time(cbuf)) * 1000000, decimal.Decimal(cmdbuf_en_time(cbuf)) * 1000000 - if PROFILE and (lb:=cmdbuf_label(cbuf)) is not None: - Compiled.profile_events += [ProfileRangeEvent(self.device, lb, st, en, is_copy=lb.startswith("COPY"))] - self.mtl_buffers_in_flight.clear() - -def metal_src_to_library(device:MetalDevice, src:str) -> objc_instance: - options = msg("new", objc_instance)(libobjc.objc_getClass(b"MTLCompileOptions")) - msg("setFastMathEnabled:")(options, getenv("METAL_FAST_MATH")) - library = msg("newLibraryWithSource:options:error:", objc_instance)(device.sysdevice, to_ns_str(src), - options, ctypes.byref(compileError:=objc_instance())) - error_check(compileError, CompileError) - return library - -class MetalCompiler(Compiler): - # Opening METAL after LLVM doesn't fail because ctypes.CDLL opens with RTLD_LOCAL but MTLCompiler opens it's own llvm with RTLD_GLOBAL - # This means that MTLCompiler's llvm will create it's own instances of global state because RTLD_LOCAL doesn't export symbols, but if RTLD_GLOBAL - # library is loaded first then RTLD_LOCAL library will just use it's symbols. On linux there is RTLD_DEEPBIND to prevent that, but on macos there - # doesn't seem to be anything we can do. - with contextlib.suppress(FileNotFoundError, ModuleNotFoundError): - import tinygrad.runtime.autogen.llvm # noqa: F401 - support = ctypes.CDLL("/System/Library/PrivateFrameworks/MTLCompiler.framework/MTLCompiler") - support.MTLCodeGenServiceCreate.restype = ctypes.c_void_p - - def __init__(self): - self.cgs = ctypes.c_void_p(MetalCompiler.support.MTLCodeGenServiceCreate(b"tinygrad")) - super().__init__("compile_metal_direct") - def __reduce__(self): return (MetalCompiler,()) # force pickle to create new instance for each multiprocessing fork - def compile(self, src:str) -> bytes: - ret: Union[Exception, bytes] = CompileError("MTLCodeGenServiceBuildRequest returned without calling the callback") - @ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_int32, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_char_p) - def callback(blockptr, error, dataPtr, dataLen, errorMessage): - nonlocal ret - if error == 0: - reply = bytes(to_mv(dataPtr, dataLen)) - # offset from beginning to data = header size + warning size - ret = reply[sum(struct.unpack('= 14 else "metal3.0" if macos_major >= 13 else "macos-metal2.0" - - # llvm will create modules.timestamp in cache path and cache compilation of metal stdlib (250ms => 8ms compilation time) - # note that llvm won't necessarily create anything else here as apple has prebuilt versions of many standard libraries - params = f'-fno-fast-math -std={metal_version} --driver-mode=metal -x metal -fmodules-cache-path="{cache_dir}" -fno-caret-diagnostics' - # source blob has to be padded to multiple of 4 but at least one 'b\x00' should be added, params blob just has to be null terminated - src_padded, params_padded = src.encode() + b'\x00'*(round_up(len(src) + 1, 4) - len(src)), params.encode() + b'\x00' - request = struct.pack(' self.max_total_threads: - exec_width = msg("threadExecutionWidth", ctypes.c_ulong)(self.pipeline_state) - memory_length = msg("staticThreadgroupMemoryLength", ctypes.c_ulong)(self.pipeline_state) - raise RuntimeError(f"local size {local_size} bigger than {self.max_total_threads} with exec width {exec_width} memory length {memory_length}") - command_buffer = msg("commandBuffer", objc_instance)(self.dev.mtl_queue) - encoder = msg("computeCommandEncoder", objc_instance)(command_buffer) - msg("setComputePipelineState:")(encoder, self.pipeline_state) - for i,a in enumerate(bufs): msg("setBuffer:offset:atIndex:")(encoder, a.buf, a.offset, i) - for i,a in enumerate(vals, start=len(bufs)): msg("setBytes:length:atIndex:")(encoder, bytes(ctypes.c_int(a)), 4, i) - msg("dispatchThreadgroups:threadsPerThreadgroup:")(encoder, to_struct(*global_size), to_struct(*local_size)) - msg("endEncoding")(encoder) - msg("setLabel:")(command_buffer, to_ns_str(self.name)) # TODO: is this always needed? - msg("commit")(command_buffer) - self.dev.mtl_buffers_in_flight.append(command_buffer) - if wait: - wait_check(command_buffer) - return cmdbuf_en_time(command_buffer) - cmdbuf_st_time(command_buffer) - -class MetalBuffer: - def __init__(self, buf:Any, size:int, offset=0): self.buf, self.size, self.offset = buf, size, offset - -class MetalAllocator(LRUAllocator[MetalDevice]): - def _alloc(self, size:int, options) -> MetalBuffer: - if options.external_ptr: return MetalBuffer(objc_id(options.external_ptr), size) - - # Buffer is explicitly released in _free() rather than garbage collected via reference count - ret = msg("newBufferWithLength:options:", objc_id)(self.dev.sysdevice, ctypes.c_ulong(size), MTLResourceOptions.MTLResourceStorageModeShared) - if ret.value is None: raise MemoryError(f"Metal OOM while allocating {size=}") - return MetalBuffer(ret, size) - def _free(self, opaque:MetalBuffer, options): msg("release")(opaque.buf) - def _transfer(self, dest:MetalBuffer, src:MetalBuffer, sz:int, src_dev:MetalDevice, dest_dev:MetalDevice): - dest_dev.synchronize() - src_command_buffer = msg("commandBuffer", objc_instance)(src_dev.mtl_queue) - encoder = msg("blitCommandEncoder", objc_instance)(src_command_buffer) - msg("copyFromBuffer:sourceOffset:toBuffer:destinationOffset:size:")(encoder, src.buf, ctypes.c_ulong(src.offset), - dest.buf, ctypes.c_ulong(dest.offset), ctypes.c_ulong(sz)) - msg("endEncoding")(encoder) - if src_dev != dest_dev: - msg("encodeSignalEvent:value:")(src_command_buffer, src_dev.timeline_signal, src_dev.timeline_value) - dest_command_buffer = msg("commandBuffer", objc_instance)(dest_dev.mtl_queue) - msg("encodeWaitForEvent:value:")(dest_command_buffer, src_dev.timeline_signal, src_dev.timeline_value) - msg("commit")(dest_command_buffer) - dest_dev.mtl_buffers_in_flight.append(dest_command_buffer) - src_dev.timeline_value += 1 - msg("setLabel:")(src_command_buffer, to_ns_str(f"COPY {src_dev.device} -> {dest_dev.device}")) - msg("commit")(src_command_buffer) - src_dev.mtl_buffers_in_flight.append(src_command_buffer) - def _cp_mv(self, dst, src, prof_desc): - with cpu_profile(prof_desc, self.dev.device, is_copy=True): dst[:] = src - def _as_buffer(self, src:MetalBuffer) -> memoryview: - self.dev.synchronize() - return to_mv(cast(int, msg("contents", objc_id)(src.buf).value), src.size + src.offset)[src.offset:] - def _copyin(self, dest:MetalBuffer, src:memoryview): self._cp_mv(self._as_buffer(dest), src, "CPU -> METAL") - def _copyout(self, dest:memoryview, src:MetalBuffer): self._cp_mv(dest, self._as_buffer(src), "METAL -> CPU") - def _offset(self, buf:MetalBuffer, size:int, offset:int): return MetalBuffer(buf.buf, size, offset) diff --git a/tinygrad/tinygrad/runtime/ops_npy.py b/tinygrad/tinygrad/runtime/ops_npy.py deleted file mode 100644 index f40bfcde..00000000 --- a/tinygrad/tinygrad/runtime/ops_npy.py +++ /dev/null @@ -1,11 +0,0 @@ -import numpy as np -from tinygrad.helpers import flat_mv -from tinygrad.device import Compiled, Allocator - -class NpyAllocator(Allocator['NpyDevice']): - def _alloc(self, size:int, options=None) -> np.ndarray: return np.empty(size, dtype=np.uint8) - def _as_buffer(self, src:np.ndarray) -> memoryview: return flat_mv(np.require(src, requirements='C').data) - def _copyout(self, dest:memoryview, src:np.ndarray): dest[:] = self._as_buffer(src) - -class NpyDevice(Compiled): - def __init__(self, device:str): super().__init__(device, NpyAllocator(self), None, None, None) diff --git a/tinygrad/tinygrad/runtime/ops_null.py b/tinygrad/tinygrad/runtime/ops_null.py deleted file mode 100644 index 569888d8..00000000 --- a/tinygrad/tinygrad/runtime/ops_null.py +++ /dev/null @@ -1,26 +0,0 @@ -from tinygrad.device import Compiled, Compiler, Renderer, Allocator -from tinygrad.uop.ops import Ops -from tinygrad.engine.jit import MultiGraphRunner - -class NullRenderer(Renderer): - device = "NULL" - code_for_op = {k:lambda:None for k in [Ops.EXP2, Ops.LOG2, Ops.SIN, Ops.SQRT]} - has_local = False - def render(self, uops:list) -> str: return "" - -class NullProgram: - def __init__(self, name:str, lib:bytes): pass - def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - return 1e-4 - -class NullAllocator(Allocator['NullDevice']): - def _alloc(self, size, options): pass - def _copyin(self, dest, src:memoryview): pass - def _copyout(self, dest:memoryview, src): pass - def _transfer(self, dest, src, sz:int, src_dev, dest_dev): pass - -class NullGraph(MultiGraphRunner): - def __call__(self, input_rawbuffers, var_vals, wait=False) -> float|None: return 1e-3 - -class NullDevice(Compiled): - def __init__(self, device:str): super().__init__(device, NullAllocator(self), NullRenderer(), Compiler(), NullProgram, NullGraph) diff --git a/tinygrad/tinygrad/runtime/ops_nv.py b/tinygrad/tinygrad/runtime/ops_nv.py deleted file mode 100644 index f9decbda..00000000 --- a/tinygrad/tinygrad/runtime/ops_nv.py +++ /dev/null @@ -1,590 +0,0 @@ -from __future__ import annotations -import os, ctypes, contextlib, re, functools, mmap, struct, array, sys, weakref -assert sys.platform != 'win32' -from typing import cast, Union, ClassVar -from dataclasses import dataclass -from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQProgram, HCQSignal, BumpAllocator -from tinygrad.runtime.support.hcq import MMIOInterface, FileIOInterface, MOCKGPU -from tinygrad.uop.ops import sint -from tinygrad.device import BufferSpec, CPUProgram -from tinygrad.helpers import getenv, mv_address, round_up, data64, data64_le, DEBUG, prod, OSX, to_mv, hi32, lo32 -from tinygrad.renderer.ptx import PTXRenderer -from tinygrad.renderer.cstyle import NVRenderer -from tinygrad.runtime.support.compiler_cuda import CUDACompiler, PTXCompiler, PTX, NVPTXCompiler, NVCompiler -from tinygrad.runtime.autogen import nv_gpu -from tinygrad.runtime.support.elf import elf_loader -if getenv("IOCTL"): import extra.nv_gpu_driver.nv_ioctl # noqa: F401 # pylint: disable=unused-import - -def get_error_str(status): return f"{status}: {nv_gpu.nv_status_codes.get(status, 'Unknown error')}" - -NV_PFAULT_FAULT_TYPE = {dt:name for name,dt in nv_gpu.__dict__.items() if name.startswith("NV_PFAULT_FAULT_TYPE_")} -NV_PFAULT_ACCESS_TYPE = {dt:name.split("_")[-1] for name,dt in nv_gpu.__dict__.items() if name.startswith("NV_PFAULT_ACCESS_TYPE_")} - -def nv_iowr(fd:FileIOInterface, nr, args): - ret = fd.ioctl((3 << 30) | (ctypes.sizeof(args) & 0x1FFF) << 16 | (ord('F') & 0xFF) << 8 | (nr & 0xFF), args) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - -def rm_alloc(fd, clss, root, parant, params): - made = nv_gpu.NVOS21_PARAMETERS(hRoot=root, hObjectParent=parant, hClass=clss, - pAllocParms=ctypes.cast(ctypes.byref(params), ctypes.c_void_p) if params is not None else None) - nv_iowr(fd, nv_gpu.NV_ESC_RM_ALLOC, made) - if made.status != 0: - if made.status == nv_gpu.NV_ERR_NO_MEMORY: raise MemoryError(f"rm_alloc returned {get_error_str(made.status)}") - raise RuntimeError(f"rm_alloc returned {get_error_str(made.status)}") - return made - -def rm_control(cmd, sttyp, fd, client, obj, **kwargs): - made = nv_gpu.NVOS54_PARAMETERS(hClient=client, hObject=obj, cmd=cmd, paramsSize=ctypes.sizeof(params:=sttyp(**kwargs)), - params=ctypes.cast(ctypes.byref(params), ctypes.c_void_p) if params is not None else None) - nv_iowr(fd, nv_gpu.NV_ESC_RM_CONTROL, made) - if made.status != 0: raise RuntimeError(f"rm_control returned {get_error_str(made.status)}") - return params - -def make_rmctrl_type(): - return type("NVRMCTRL", (object,), {name[name.find("_CTRL_CMD_")+10:].lower(): functools.partial(rm_control, dt, sttyp) - for name,dt in nv_gpu.__dict__.items() if name.find("_CTRL_CMD_")>=0 and (sttyp:=getattr(nv_gpu, name.replace("_CTRL_CMD_", "_CTRL_")+"_PARAMS", \ - getattr(nv_gpu, name+"_PARAMS", getattr(nv_gpu, name.replace("_CTRL_CMD_", "_CTRL_DEBUG_")+"_PARAMETERS", None))))}) -rmctrl = make_rmctrl_type() - -def uvm_ioctl(cmd, sttyp, fd:FileIOInterface, **kwargs): - ret = fd.ioctl(cmd, made:=sttyp(**kwargs)) - if ret != 0: raise RuntimeError(f"ioctl(uvm) returned {ret}") - if made.rmStatus != 0: raise RuntimeError(f"uvm_ioctl returned {get_error_str(made.rmStatus)}") - return made - -def make_uvm_type(): - return type("NVUVM", (object,), {name.replace("UVM_", "").lower(): functools.partial(uvm_ioctl, dt, getattr(nv_gpu, name+"_PARAMS")) - for name,dt in nv_gpu.__dict__.items() if name.startswith("UVM_") and nv_gpu.__dict__.get(name+"_PARAMS")}) -uvm = make_uvm_type() - -class QMD: - fields: dict[str, dict[str, tuple[int, int]]] = {} - - def __init__(self, dev:NVDevice, addr:int|None=None, **kwargs): - self.ver, self.sz = (5, 0x60) if dev.compute_class >= nv_gpu.BLACKWELL_COMPUTE_A else (3, 0x40) - - # Init fields from module - if (pref:="NVCEC0_QMDV05_00" if self.ver == 5 else "NVC6C0_QMDV03_00") not in QMD.fields: - QMD.fields[pref] = {**{name[len(pref)+1:]: dt for name,dt in nv_gpu.__dict__.items() if name.startswith(pref) and isinstance(dt, tuple)}, - **{name[len(pref)+1:]+f"_{i}": dt(i) for name,dt in nv_gpu.__dict__.items() for i in range(8) if name.startswith(pref) and callable(dt)}} - - self.mv, self.pref = (memoryview(bytearray(self.sz * 4)) if addr is None else to_mv(addr, self.sz * 4)), pref - if kwargs: self.write(**kwargs) - - def _rw_bits(self, hi:int, lo:int, value:int|None=None): - mask = ((1 << (width:=hi - lo + 1)) - 1) << (lo % 8) - num = int.from_bytes(self.mv[lo//8:hi//8+1], "little") - - if value is None: return (num & mask) >> (lo % 8) - - if value >= (1 << width): raise ValueError(f"{value:#x} does not fit.") - self.mv[lo//8:hi//8+1] = int((num & ~mask) | ((value << (lo % 8)) & mask)).to_bytes((hi//8 - lo//8 + 1), "little") - - def write(self, **kwargs): - for k,val in kwargs.items(): self._rw_bits(*QMD.fields[self.pref][k.upper()], value=val) - - def read(self, k, val=0): return self._rw_bits(*QMD.fields[self.pref][k.upper()]) - - def field_offset(self, k): return QMD.fields[self.pref][k.upper()][1] // 8 - - def set_constant_buf_addr(self, i, addr): - if self.ver < 4: self.write(**{f'constant_buffer_addr_upper_{i}':hi32(addr), f'constant_buffer_addr_lower_{i}':lo32(addr)}) - else: self.write(**{f'constant_buffer_addr_upper_shifted6_{i}':hi32(addr >> 6), f'constant_buffer_addr_lower_shifted6_{i}':lo32(addr >> 6)}) - -class NVSignal(HCQSignal): - def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): - super().__init__(base_buf, **kwargs, timestamp_divider=1000, dev_t=NVDevice) - -class NVCommandQueue(HWQueue[NVSignal, 'NVDevice', 'NVProgram', 'NVArgsState']): - def __init__(self): - self.active_qmd = None - super().__init__() - - def __del__(self): - if self.binded_device is not None: self.binded_device.allocator.free(self.hw_page, self.hw_page.size, BufferSpec(cpu_access=True, nolru=True)) - - def nvm(self, subchannel, mthd, *args, typ=2): self.q((typ << 28) | (len(args) << 16) | (subchannel << 13) | (mthd >> 2), *args) - - def setup(self, compute_class=None, copy_class=None, local_mem_window=None, shared_mem_window=None, local_mem=None, local_mem_tpc_bytes=None): - if compute_class: self.nvm(1, nv_gpu.NVC6C0_SET_OBJECT, compute_class) - if copy_class: self.nvm(4, nv_gpu.NVC6C0_SET_OBJECT, copy_class) - if local_mem_window: self.nvm(1, nv_gpu.NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A, *data64(local_mem_window)) - if shared_mem_window: self.nvm(1, nv_gpu.NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A, *data64(shared_mem_window)) - if local_mem: self.nvm(1, nv_gpu.NVC6C0_SET_SHADER_LOCAL_MEMORY_A, *data64(local_mem)) - if local_mem_tpc_bytes: self.nvm(1, nv_gpu.NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A, *data64(local_mem_tpc_bytes), 0xff) - return self - - def wait(self, signal:NVSignal, value:sint=0): - self.nvm(0, nv_gpu.NVC56F_SEM_ADDR_LO, *data64_le(signal.value_addr), *data64_le(value), (3 << 0) | (1 << 24)) # ACQUIRE | PAYLOAD_SIZE_64BIT - self.active_qmd = None - return self - - def timestamp(self, signal:NVSignal): return self.signal(signal, 0) - - def bind(self, dev:NVDevice): - self.binded_device = dev - self.hw_page = dev.allocator.alloc(len(self._q) * 4, BufferSpec(cpu_access=True, nolru=True)) - hw_view = self.hw_page.cpu_view().view(fmt='I') - for i, value in enumerate(self._q): hw_view[i] = value - - # From now on, the queue is on the device for faster submission. - self._q = hw_view - - def _submit_to_gpfifo(self, dev:NVDevice, gpfifo:GPFifo): - if dev == self.binded_device: cmdq_addr = self.hw_page.va_addr - else: - cmdq_addr = dev.cmdq_allocator.alloc(len(self._q) * 4) - cmdq_wptr = (cmdq_addr - dev.cmdq_page.va_addr) // 4 - dev.cmdq[cmdq_wptr : cmdq_wptr + len(self._q)] = array.array('I', self._q) - - gpfifo.ring[gpfifo.put_value % gpfifo.entries_count] = (cmdq_addr//4 << 2) | (len(self._q) << 42) | (1 << 41) - gpfifo.controls.GPPut = (gpfifo.put_value + 1) % gpfifo.entries_count - - if CPUProgram.atomic_lib is not None: CPUProgram.atomic_lib.atomic_thread_fence(__ATOMIC_SEQ_CST:=5) - dev.gpu_mmio[0x90 // 4] = gpfifo.token - gpfifo.put_value += 1 - -class NVComputeQueue(NVCommandQueue): - def memory_barrier(self): - self.nvm(1, nv_gpu.NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI, (1 << 12) | (1 << 4) | (1 << 0)) - self.active_qmd:QMD|None = None - return self - - def exec(self, prg:NVProgram, args_state:NVArgsState, global_size:tuple[sint, ...], local_size:tuple[sint, ...]): - self.bind_args_state(args_state) - - qmd_buf = args_state.buf.offset(round_up(prg.constbufs[0][1], 1 << 8)) - qmd_buf.cpu_view().view(size=prg.qmd.mv.nbytes, fmt='B')[:] = prg.qmd.mv - assert qmd_buf.va_addr < (1 << 40), f"large qmd addr {qmd_buf.va_addr:x}" - - qmd = QMD(dev=prg.dev, addr=cast(int, qmd_buf.va_addr)) # Save qmd for later update - - self.bind_sints_to_mem(*global_size, mem=qmd_buf.cpu_view(), fmt='I', offset=qmd.field_offset('cta_raster_width' if qmd.ver<4 else 'grid_width')) - self.bind_sints_to_mem(*(local_size[:2]), mem=qmd_buf.cpu_view(), fmt='H', offset=qmd.field_offset('cta_thread_dimension0')) - self.bind_sints_to_mem(local_size[2], mem=qmd_buf.cpu_view(), fmt='B', offset=qmd.field_offset('cta_thread_dimension2')) - qmd.set_constant_buf_addr(0, args_state.buf.va_addr) - - if self.active_qmd is None: - self.nvm(1, nv_gpu.NVC6C0_SEND_PCAS_A, qmd_buf.va_addr >> 8) - self.nvm(1, nv_gpu.NVC6C0_SEND_SIGNALING_PCAS2_B, 9) - else: - self.active_qmd.write(dependent_qmd0_pointer=qmd_buf.va_addr >> 8, dependent_qmd0_action=1, dependent_qmd0_prefetch=1, dependent_qmd0_enable=1) - - self.active_qmd, self.active_qmd_buf = qmd, qmd_buf - return self - - def signal(self, signal:NVSignal, value:sint=0): - if self.active_qmd is not None: - for i in range(2): - if self.active_qmd.read(f'release{i}_enable') == 0: - self.active_qmd.write(**{f'release{i}_enable': 1}) - self.bind_sints_to_mem(signal.value_addr, mem=self.active_qmd_buf.cpu_view(), fmt='Q', mask=0xfffffffff, - offset=self.active_qmd.field_offset(f'release{i}_address_lower' if self.active_qmd.ver<4 else f'release_semaphore{i}_addr_lower')) - self.bind_sints_to_mem(value, mem=self.active_qmd_buf.cpu_view(), fmt='Q', - offset=self.active_qmd.field_offset(f'release{i}_payload_lower' if self.active_qmd.ver<4 else f'release_semaphore{i}_payload_lower')) - return self - - self.nvm(0, nv_gpu.NVC56F_SEM_ADDR_LO, *data64_le(signal.value_addr), *data64_le(value), - (1 << 0) | (1 << 20) | (1 << 24) | (1 << 25)) # RELEASE | RELEASE_WFI | PAYLOAD_SIZE_64BIT | RELEASE_TIMESTAMP - self.nvm(0, nv_gpu.NVC56F_NON_STALL_INTERRUPT, 0x0) - self.active_qmd = None - return self - - def _submit(self, dev:NVDevice): self._submit_to_gpfifo(dev, dev.compute_gpfifo) - -class NVCopyQueue(NVCommandQueue): - def copy(self, dest:sint, src:sint, copy_size:int): - for off in range(0, copy_size, step:=(1 << 31)): - self.nvm(4, nv_gpu.NVC6B5_OFFSET_IN_UPPER, *data64(src+off), *data64(dest+off)) - self.nvm(4, nv_gpu.NVC6B5_LINE_LENGTH_IN, min(copy_size-off, step)) - self.nvm(4, nv_gpu.NVC6B5_LAUNCH_DMA, 0x182) # TRANSFER_TYPE_NON_PIPELINED | DST_MEMORY_LAYOUT_PITCH | SRC_MEMORY_LAYOUT_PITCH - return self - - def signal(self, signal:NVSignal, value:sint=0): - self.nvm(4, nv_gpu.NVC6B5_SET_SEMAPHORE_A, *data64(signal.value_addr), value) - self.nvm(4, nv_gpu.NVC6B5_LAUNCH_DMA, 0x14) - return self - - def _submit(self, dev:NVDevice): self._submit_to_gpfifo(dev, dev.dma_gpfifo) - -class NVArgsState(CLikeArgsState): - def __init__(self, buf:HCQBuffer, prg:NVProgram, bufs:tuple[HCQBuffer, ...], vals:tuple[int, ...]=()): - if MOCKGPU: prg.constbuffer_0[80:82] = [len(bufs), len(vals)] - super().__init__(buf, prg, bufs, vals=vals, prefix=prg.constbuffer_0) - -class NVProgram(HCQProgram): - def __init__(self, dev:NVDevice, name:str, lib:bytes): - self.dev, self.name, self.lib = dev, name, lib - - # For MOCKGPU, the lib is PTX code, so some values are emulated. - cbuf0_size = 0 if not MOCKGPU else 0x160 - - if MOCKGPU: image, sections, relocs = memoryview(bytearray(lib) + b'\x00' * (4 - len(lib)%4)).cast("I"), [], [] # type: ignore - else: image, sections, relocs = elf_loader(self.lib, force_section_align=128) - - # NOTE: Ensure at least 4KB of space after the program to mitigate prefetch memory faults. - self.lib_gpu = self.dev.allocator.alloc(round_up(image.nbytes, 0x1000) + 0x1000, buf_spec:=BufferSpec(cpu_access=True)) - - self.prog_addr, self.prog_sz, self.regs_usage, self.shmem_usage, self.lcmem_usage = self.lib_gpu.va_addr, image.nbytes, 0, 0x400, 0 - self.constbufs: dict[int, tuple[int, int]] = {0: (0, 0x160)} # dict[constbuf index, tuple[va_addr, size]] - for sh in sections: - if sh.name == f".nv.shared.{self.name}": self.shmem_usage = round_up(0x400 + sh.header.sh_size, 128) - if sh.name == f".text.{self.name}": self.prog_addr, self.prog_sz = self.lib_gpu.va_addr+sh.header.sh_addr, sh.header.sh_size - elif m:=re.match(r'\.nv\.constant(\d+)', sh.name): self.constbufs[int(m.group(1))] = (self.lib_gpu.va_addr+sh.header.sh_addr, sh.header.sh_size) - elif sh.name.startswith(".nv.info"): - for typ, param, data in self._parse_elf_info(sh): - if sh.name == f".nv.info.{name}" and param == 0xa: cbuf0_size = struct.unpack_from("IH", data)[1] # EIATTR_PARAM_CBANK - elif sh.name == ".nv.info" and param == 0x12: self.lcmem_usage = struct.unpack_from("II", data)[1] + 0x240 # EIATTR_MIN_STACK_SIZE - elif sh.name == ".nv.info" and param == 0x2f: self.regs_usage = struct.unpack_from("II", data)[1] # EIATTR_REGCOUNT - - # Ensure device has enough local memory to run the program - self.dev._ensure_has_local_memory(self.lcmem_usage) - - # Apply relocs - for apply_image_offset, rel_sym_offset, typ, _ in relocs: - # These types are CUDA-specific, applying them here - if typ == 2: image[apply_image_offset:apply_image_offset+8] = struct.pack('> 32) - else: raise RuntimeError(f"unknown NV reloc {typ}") - - ctypes.memmove(self.lib_gpu.va_addr, mv_address(image), image.nbytes) - - self.constbuffer_0 = [0] * (cbuf0_size // 4) - - if dev.compute_class >= nv_gpu.BLACKWELL_COMPUTE_A: - self.constbuffer_0[188:192], self.constbuffer_0[223] = [*data64_le(self.dev.shared_mem_window), *data64_le(self.dev.local_mem_window)], 0xfffdc0 - qmd = {'qmd_major_version':5, 'qmd_type':nv_gpu.NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA, 'register_count':self.regs_usage, - 'program_address_upper_shifted4':hi32(self.prog_addr>>4), 'program_address_lower_shifted4':lo32(self.prog_addr>>4), - 'shared_memory_size_shifted7':self.shmem_usage>>7, 'shader_local_memory_high_size_shifted4':self.dev.slm_per_thread>>4} - else: - self.constbuffer_0[6:12] = [*data64_le(self.dev.shared_mem_window), *data64_le(self.dev.local_mem_window), *data64_le(0xfffdc0)] - qmd = {'qmd_major_version':3, 'sm_global_caching_enable':1, 'shader_local_memory_high_size':self.dev.slm_per_thread, - 'program_address_upper':hi32(self.prog_addr), 'program_address_lower':lo32(self.prog_addr), 'shared_memory_size':self.shmem_usage, - 'register_count_v':self.regs_usage} - - smem_cfg = min(shmem_conf * 1024 for shmem_conf in [32, 64, 100] if shmem_conf * 1024 >= self.shmem_usage) // 4096 + 1 - - self.qmd:QMD = QMD(dev, **qmd, qmd_group_id=0x3f, invalidate_texture_header_cache=1, invalidate_texture_sampler_cache=1, - invalidate_texture_data_cache=1, invalidate_shader_data_cache=1, api_visible_call_limit=1, sampler_index=1, barrier_count=1, - cwd_membar_type=nv_gpu.NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR, constant_buffer_invalidate_0=1, - min_sm_config_shared_mem_size=smem_cfg, target_sm_config_shared_mem_size=smem_cfg, max_sm_config_shared_mem_size=0x1a, - program_prefetch_size=min(self.prog_sz>>8, 0x1ff), sass_version=dev.sass_version, - program_prefetch_addr_upper_shifted=self.prog_addr>>40, program_prefetch_addr_lower_shifted=self.prog_addr>>8) - - for i,(addr,sz) in self.constbufs.items(): - self.qmd.set_constant_buf_addr(i, addr) - self.qmd.write(**{f'constant_buffer_size_shifted4_{i}': sz, f'constant_buffer_valid_{i}': 1}) - - # Registers allocation granularity per warp is 256, warp allocation granularity is 4. Register file size is 65536. - self.max_threads = ((65536 // round_up(max(1, self.regs_usage) * 32, 256)) // 4) * 4 * 32 - - # NV's kernargs is constbuffer, then arguments to the kernel follows. Kernargs also appends QMD at the end of the kernel. - super().__init__(NVArgsState, self.dev, self.name, kernargs_alloc_size=round_up(self.constbufs[0][1], 1 << 8) + (8 << 8)) - weakref.finalize(self, self._fini, self.dev, self.lib_gpu, buf_spec) - - def _parse_elf_info(self, sh, start_off=0): - while start_off < sh.header.sh_size: - typ, param, sz = struct.unpack_from("BBH", sh.content, start_off) - yield typ, param, sh.content[start_off+4:start_off+sz+4] if typ == 0x4 else sz - start_off += (sz if typ == 0x4 else 0) + 4 - - def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - if prod(local_size) > 1024 or self.max_threads < prod(local_size) or self.lcmem_usage > cast(NVDevice, self.dev).slm_per_thread: - raise RuntimeError(f"Too many resources requested for launch, {prod(local_size)=}, {self.max_threads=}") - if any(cur > mx for cur,mx in zip(global_size, [2147483647, 65535, 65535])) or any(cur > mx for cur,mx in zip(local_size, [1024, 1024, 64])): - raise RuntimeError(f"Invalid global/local dims {global_size=}, {local_size=}") - return super().__call__(*bufs, global_size=global_size, local_size=local_size, vals=vals, wait=wait) - -class NVAllocator(HCQAllocator['NVDevice']): - def _alloc(self, size:int, options:BufferSpec) -> HCQBuffer: - if options.host: return self.dev._gpu_alloc(size, host=True, tag="user host memory") - return self.dev._gpu_alloc(size, cpu_access=options.cpu_access, tag=f"user memory ({options})") - - def _free(self, opaque:HCQBuffer, options:BufferSpec): - try: - self.dev.synchronize() - self.dev._gpu_free(opaque) - except AttributeError: pass - - def map(self, buf:HCQBuffer): self.dev._gpu_map(buf._base if buf._base is not None else buf) - -@dataclass -class GPFifo: - ring: MMIOInterface - controls: nv_gpu.AmpereAControlGPFifo - entries_count: int - token: int - put_value: int = 0 - -MAP_FIXED, MAP_NORESERVE = 0x10, 0x400 -class NVDevice(HCQCompiled[NVSignal]): - devices: ClassVar[list[HCQCompiled]] = [] - signal_pages: ClassVar[list[HCQBuffer]] = [] - signal_pool: ClassVar[list[HCQBuffer]] = [] - - root = None - fd_ctl: FileIOInterface - fd_uvm: FileIOInterface - gpus_info: Union[list, ctypes.Array] = [] - - # TODO: Need a proper allocator for va addresses - # 0x1000000000 - 0x2000000000, reserved for system/cpu mappings - # VA space is 48bits. - low_uvm_vaddr_allocator: BumpAllocator = BumpAllocator(size=0x1000000000, base=0x8000000000 if OSX else 0x1000000000, wrap=False) - uvm_vaddr_allocator: BumpAllocator = BumpAllocator(size=(1 << 48) - 1, base=low_uvm_vaddr_allocator.base + low_uvm_vaddr_allocator.size, wrap=False) - host_object_enumerator: int = 0x1000 - - def _new_gpu_fd(self): - fd_dev = FileIOInterface(f"/dev/nvidia{NVDevice.gpus_info[self.device_id].minor_number}", os.O_RDWR | os.O_CLOEXEC) - nv_iowr(fd_dev, nv_gpu.NV_ESC_REGISTER_FD, nv_gpu.nv_ioctl_register_fd_t(ctl_fd=self.fd_ctl.fd)) - return fd_dev - - def _gpu_map_to_cpu(self, memory_handle, size, target=None, flags=0, system=False): - fd_dev = self._new_gpu_fd() if not system else FileIOInterface("/dev/nvidiactl", os.O_RDWR | os.O_CLOEXEC) - made = nv_gpu.nv_ioctl_nvos33_parameters_with_fd(fd=fd_dev.fd, - params=nv_gpu.NVOS33_PARAMETERS(hClient=self.root, hDevice=self.nvdevice, hMemory=memory_handle, length=size, flags=flags)) - nv_iowr(self.fd_ctl, nv_gpu.NV_ESC_RM_MAP_MEMORY, made) - if made.params.status != 0: raise RuntimeError(f"_gpu_map_to_cpu returned {get_error_str(made.params.status)}") - return fd_dev.mmap(target, size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED | (MAP_FIXED if target is not None else 0), 0) - - def _gpu_alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, map_flags=0, tag="") -> HCQBuffer: - # Uncached memory is "system". Use huge pages only for gpu memory. - page_size = (4 << (12 if OSX else 10)) if uncached or host else ((2 << 20) if size >= (8 << 20) else (4 << (12 if OSX else 10))) - size = round_up(size, page_size) - va_addr = self._alloc_gpu_vaddr(size, alignment=page_size, force_low=cpu_access) - - if host: - va_addr = FileIOInterface.anon_mmap(va_addr, size, mmap.PROT_READ | mmap.PROT_WRITE, MAP_FIXED | mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, 0) - - flags = (nv_gpu.NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS << 4) | (nv_gpu.NVOS02_FLAGS_COHERENCY_CACHED << 12) \ - | (nv_gpu.NVOS02_FLAGS_MAPPING_NO_MAP << 30) - - NVDevice.host_object_enumerator += 1 - made = nv_gpu.nv_ioctl_nvos02_parameters_with_fd(params=nv_gpu.NVOS02_PARAMETERS(hRoot=self.root, hObjectParent=self.nvdevice, flags=flags, - hObjectNew=NVDevice.host_object_enumerator, hClass=nv_gpu.NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, pMemory=va_addr, limit=size-1), fd=-1) - nv_iowr(self.fd_dev, nv_gpu.NV_ESC_RM_ALLOC_MEMORY, made) - - if made.params.status != 0: raise RuntimeError(f"host alloc returned {get_error_str(made.params.status)}") - mem_handle = made.params.hObjectNew - else: - attr = ((nv_gpu.NVOS32_ATTR_PHYSICALITY_CONTIGUOUS if contiguous else nv_gpu.NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS) << 27) \ - | (nv_gpu.NVOS32_ATTR_PAGE_SIZE_HUGE if page_size > 0x1000 else 0) << 23 | ((nv_gpu.NVOS32_ATTR_LOCATION_PCI if uncached else 0) << 25) - - attr2 = ((nv_gpu.NVOS32_ATTR2_GPU_CACHEABLE_NO if uncached else nv_gpu.NVOS32_ATTR2_GPU_CACHEABLE_YES) << 2) \ - | ((nv_gpu.NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB if page_size > 0x1000 else 0) << 20) | nv_gpu.NVOS32_ATTR2_ZBC_PREFER_NO_ZBC - - fl = nv_gpu.NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED | nv_gpu.NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED | nv_gpu.NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE \ - | nv_gpu.NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT | (nv_gpu.NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM if not uncached else 0) - - alloc_func = nv_gpu.NV1_MEMORY_SYSTEM if uncached else nv_gpu.NV1_MEMORY_USER - alloc_params = nv_gpu.NV_MEMORY_ALLOCATION_PARAMS(owner=self.root, alignment=page_size, offset=0, limit=size-1, format=6, size=size, - type=nv_gpu.NVOS32_TYPE_NOTIFIER if uncached else nv_gpu.NVOS32_TYPE_IMAGE, attr=attr, attr2=attr2, flags=fl) - mem_handle = rm_alloc(self.fd_ctl, alloc_func, self.root, self.nvdevice, alloc_params).hObjectNew - - if cpu_access: va_addr = self._gpu_map_to_cpu(mem_handle, size, target=va_addr, flags=map_flags, system=uncached) - - return self._gpu_uvm_map(va_addr, size, mem_handle, has_cpu_mapping=cpu_access or host, tag=tag) - - def _gpu_free(self, mem:HCQBuffer): - if mem.meta.hMemory > NVDevice.host_object_enumerator: # not a host object, clear phys mem. - made = nv_gpu.NVOS00_PARAMETERS(hRoot=self.root, hObjectParent=self.nvdevice, hObjectOld=mem.meta.hMemory) - nv_iowr(self.fd_ctl, nv_gpu.NV_ESC_RM_FREE, made) - if made.status != 0: raise RuntimeError(f"_gpu_free returned {get_error_str(made.status)}") - - self._debug_mappings.pop((cast(int, mem.va_addr), mem.size)) - uvm.free(self.fd_uvm, base=cast(int, mem.va_addr), length=mem.size) - if mem.meta.has_cpu_mapping: FileIOInterface.munmap(cast(int, mem.va_addr), mem.size) - - def _gpu_uvm_map(self, va_base, size, mem_handle, create_range=True, has_cpu_mapping=False, tag="") -> HCQBuffer: - if create_range: uvm.create_external_range(self.fd_uvm, base=va_base, length=size) - attrs = (nv_gpu.struct_c__SA_UvmGpuMappingAttributes*256)(nv_gpu.struct_c__SA_UvmGpuMappingAttributes(gpuUuid=self.gpu_uuid, gpuMappingType=1)) - - # NOTE: va_addr is set to make rawbufs compatible with HCQBuffer protocol. - self._debug_mappings[(va_base, size)] = tag - return HCQBuffer(va_base, size, meta=uvm.map_external_allocation(self.fd_uvm, base=va_base, length=size, rmCtrlFd=self.fd_ctl.fd, - hClient=self.root, hMemory=mem_handle, gpuAttributesCount=1, perGpuAttributes=attrs, - mapped_gpu_ids=[self.gpu_uuid], has_cpu_mapping=has_cpu_mapping), - view=MMIOInterface(va_base, size, fmt='B') if has_cpu_mapping else None) - - def _gpu_map(self, mem:HCQBuffer): - if self.gpu_uuid in mem.meta.mapped_gpu_ids: return - mem.meta.mapped_gpu_ids.append(self.gpu_uuid) - self._gpu_uvm_map(mem.va_addr, mem.size, mem.meta.hMemory, create_range=False, tag="p2p mem") - - def _alloc_gpu_vaddr(self, size, alignment=(4 << 10), force_low=False): - return NVDevice.low_uvm_vaddr_allocator.alloc(size, alignment) if force_low else NVDevice.uvm_vaddr_allocator.alloc(size, alignment) - - def _setup_nvclasses(self): - classlist = memoryview(bytearray(100 * 4)).cast('I') - clsinfo = rmctrl.gpu_get_classlist(self.fd_ctl, self.root, self.nvdevice, numClasses=100, classList=mv_address(classlist)) - self.nvclasses = {classlist[i] for i in range(clsinfo.numClasses)} - self.usermode_class:int = next(c for c in [nv_gpu.HOPPER_USERMODE_A, nv_gpu.TURING_USERMODE_A] if c in self.nvclasses) - self.gpfifo_class:int = next(c for c in [nv_gpu.BLACKWELL_CHANNEL_GPFIFO_A, nv_gpu.AMPERE_CHANNEL_GPFIFO_A] if c in self.nvclasses) - self.compute_class:int = next(c for c in [nv_gpu.BLACKWELL_COMPUTE_B, nv_gpu.ADA_COMPUTE_A, nv_gpu.AMPERE_COMPUTE_B] if c in self.nvclasses) - self.dma_class:int = next(c for c in [nv_gpu.BLACKWELL_DMA_COPY_B, nv_gpu.AMPERE_DMA_COPY_B] if c in self.nvclasses) - - def __init__(self, device:str=""): - if NVDevice.root is None: - NVDevice.fd_ctl = FileIOInterface("/dev/nvidiactl", os.O_RDWR | os.O_CLOEXEC) - NVDevice.fd_uvm = FileIOInterface("/dev/nvidia-uvm", os.O_RDWR | os.O_CLOEXEC) - self.fd_uvm_2 = FileIOInterface("/dev/nvidia-uvm", os.O_RDWR | os.O_CLOEXEC) - NVDevice.root = rm_alloc(self.fd_ctl, nv_gpu.NV01_ROOT_CLIENT, 0, 0, None).hObjectNew - uvm.initialize(self.fd_uvm) - with contextlib.suppress(RuntimeError): uvm.mm_initialize(self.fd_uvm_2, uvmFd=self.fd_uvm.fd) # this error is okay, CUDA hits it too - - nv_iowr(NVDevice.fd_ctl, nv_gpu.NV_ESC_CARD_INFO, gpus_info:=(nv_gpu.nv_ioctl_card_info_t*64)()) - visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('CUDA_VISIBLE_DEVICES', ''))).split(',') if x.strip()] - NVDevice.gpus_info = [gpus_info[x] for x in visible_devices] if visible_devices else gpus_info - - self.device_id = int(device.split(":")[1]) if ":" in device else 0 - - if self.device_id >= len(NVDevice.gpus_info) or not NVDevice.gpus_info[self.device_id].valid: - raise RuntimeError(f"No device found for {device}. Requesting more devices than the system has?") - - self.fd_dev = self._new_gpu_fd() - self.gpu_info = rmctrl.gpu_get_id_info_v2(self.fd_ctl, self.root, self.root, gpuId=NVDevice.gpus_info[self.device_id].gpu_id) - self.gpu_minor = NVDevice.gpus_info[self.device_id].minor_number - - device_params = nv_gpu.NV0080_ALLOC_PARAMETERS(deviceId=self.gpu_info.deviceInstance, hClientShare=self.root, - vaMode=nv_gpu.NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES) - self.nvdevice = rm_alloc(self.fd_ctl, nv_gpu.NV01_DEVICE_0, self.root, self.root, device_params).hObjectNew - self.subdevice = rm_alloc(self.fd_ctl, nv_gpu.NV20_SUBDEVICE_0, self.root, self.nvdevice, None).hObjectNew - - self._setup_nvclasses() - self._debug_mappings: dict[tuple[int, int], str] = dict() - - self.usermode = rm_alloc(self.fd_ctl, self.usermode_class, self.root, self.subdevice, None).hObjectNew - self.gpu_mmio = MMIOInterface(self._gpu_map_to_cpu(self.usermode, mmio_sz:=0x10000, flags=2), mmio_sz, fmt='I') - - rmctrl.perf_boost(self.fd_ctl, self.root, self.subdevice, duration=0xffffffff, flags=((nv_gpu.NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES << 4) | \ - (nv_gpu.NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH << 6) | (nv_gpu.NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX << 0))) - - vaspace_params = nv_gpu.NV_VASPACE_ALLOCATION_PARAMETERS(vaBase=0x1000, vaSize=0x1fffffb000000, - flags=nv_gpu.NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING | nv_gpu.NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED) - vaspace = rm_alloc(self.fd_ctl, nv_gpu.FERMI_VASPACE_A, self.root, self.nvdevice, vaspace_params).hObjectNew - - raw_uuid = rmctrl.gpu_get_gid_info(self.fd_ctl, self.root, self.subdevice, flags=nv_gpu.NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY, length=16) - self.gpu_uuid = nv_gpu.struct_nv_uuid(uuid=(ctypes.c_ubyte*16)(*[raw_uuid.data[i] for i in range(16)])) - - uvm.register_gpu(self.fd_uvm, rmCtrlFd=-1, gpu_uuid=self.gpu_uuid) - uvm.register_gpu_vaspace(self.fd_uvm, gpuUuid=self.gpu_uuid, rmCtrlFd=self.fd_ctl.fd, hClient=self.root, hVaSpace=vaspace) - - for dev in cast(list[NVDevice], self.devices): - try: uvm.enable_peer_access(self.fd_uvm, gpuUuidA=self.gpu_uuid, gpuUuidB=dev.gpu_uuid) - except RuntimeError as e: raise RuntimeError(str(e) + f". Make sure GPUs #{self.gpu_minor} & #{dev.gpu_minor} have P2P enabled between.") from e - - channel_params = nv_gpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(engineType=nv_gpu.NV2080_ENGINE_TYPE_GRAPHICS) - channel_group = rm_alloc(self.fd_ctl, nv_gpu.KEPLER_CHANNEL_GROUP_A, self.root, self.nvdevice, channel_params).hObjectNew - - gpfifo_area = self._gpu_alloc(0x200000, contiguous=True, cpu_access=True, map_flags=0x10d0000, tag="gpfifo") - - ctxshare_params = nv_gpu.NV_CTXSHARE_ALLOCATION_PARAMETERS(hVASpace=vaspace, flags=nv_gpu.NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC) - ctxshare = rm_alloc(self.fd_ctl, nv_gpu.FERMI_CONTEXT_SHARE_A, self.root, channel_group, ctxshare_params).hObjectNew - - self.compute_gpfifo = self._new_gpu_fifo(gpfifo_area, ctxshare, channel_group, offset=0, entries=0x10000, enable_debug=True) - self.dma_gpfifo = self._new_gpu_fifo(gpfifo_area, ctxshare, channel_group, offset=0x100000, entries=0x10000) - - rmctrl.gpfifo_schedule(self.fd_ctl, self.root, channel_group, bEnable=1) - - self.cmdq_page:HCQBuffer = self._gpu_alloc(0x200000, cpu_access=True, tag="cmdq") - self.cmdq_allocator = BumpAllocator(size=self.cmdq_page.size, base=cast(int, self.cmdq_page.va_addr), wrap=True) - self.cmdq = MMIOInterface(cast(int, self.cmdq_page.va_addr), 0x200000, fmt='I') - - self.num_gpcs, self.num_tpc_per_gpc, self.num_sm_per_tpc, self.max_warps_per_sm, self.sm_version = self._query_gpu_info('num_gpcs', - 'num_tpc_per_gpc', 'num_sm_per_tpc', 'max_warps_per_sm', 'sm_version') - - # FIXME: no idea how to convert this for blackwells - self.arch: str = "sm_120" if self.sm_version==0xa04 else f"sm_{(self.sm_version>>8)&0xff}{(val>>4) if (val:=self.sm_version&0xff) > 0xf else val}" - self.sass_version = ((self.sm_version & 0xf00) >> 4) | (self.sm_version & 0xf) - - compiler_t = (PTXCompiler if PTX else CUDACompiler) if MOCKGPU else (NVPTXCompiler if PTX else NVCompiler) - super().__init__(device, NVAllocator(self), PTXRenderer(self.arch, device="NV") if PTX else NVRenderer(self.arch), compiler_t(self.arch), - functools.partial(NVProgram, self), NVSignal, NVComputeQueue, NVCopyQueue) - - self._setup_gpfifos() - - def _new_gpu_fifo(self, gpfifo_area, ctxshare, channel_group, offset=0, entries=0x400, enable_debug=False) -> GPFifo: - notifier = self._gpu_alloc(48 << 20, uncached=True) - params = nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS(hObjectError=notifier.meta.hMemory, hObjectBuffer=gpfifo_area.meta.hMemory, - gpFifoOffset=gpfifo_area.va_addr+offset, gpFifoEntries=entries, hContextShare=ctxshare, - hUserdMemory=(ctypes.c_uint32*8)(gpfifo_area.meta.hMemory), userdOffset=(ctypes.c_uint64*8)(entries*8+offset)) - gpfifo = rm_alloc(self.fd_ctl, self.gpfifo_class, self.root, channel_group, params).hObjectNew - comp = rm_alloc(self.fd_ctl, self.compute_class, self.root, gpfifo, None).hObjectNew - rm_alloc(self.fd_ctl, self.dma_class, self.root, gpfifo, None) - - if enable_debug: - self.debug_compute_obj, self.debug_channel = comp, gpfifo - debugger_params = nv_gpu.NV83DE_ALLOC_PARAMETERS(hAppClient=self.root, hClass3dObject=self.debug_compute_obj) - self.debugger = rm_alloc(self.fd_ctl, nv_gpu.GT200_DEBUGGER, self.root, self.nvdevice, debugger_params).hObjectNew - - ws_token_params = rmctrl.gpfifo_get_work_submit_token(self.fd_ctl, self.root, gpfifo, workSubmitToken=-1) - assert ws_token_params.workSubmitToken != -1 - - channel_base = self._alloc_gpu_vaddr(0x4000000, force_low=True) - uvm.register_channel(self.fd_uvm, gpuUuid=self.gpu_uuid, rmCtrlFd=self.fd_ctl.fd, hClient=self.root, - hChannel=gpfifo, base=channel_base, length=0x4000000) - - return GPFifo(ring=MMIOInterface(gpfifo_area.va_addr + offset, entries*8, fmt='Q'), entries_count=entries, token=ws_token_params.workSubmitToken, - controls=nv_gpu.AmpereAControlGPFifo.from_address(gpfifo_area.va_addr + offset + entries * 8)) - - def _query_gpu_info(self, *reqs): - nvrs = [getattr(nv_gpu,'NV2080_CTRL_GR_INFO_INDEX_'+r.upper(), getattr(nv_gpu,'NV2080_CTRL_GR_INFO_INDEX_LITTER_'+r.upper(),None)) for r in reqs] - infos = (nv_gpu.NV2080_CTRL_GR_INFO*len(nvrs))(*[nv_gpu.NV2080_CTRL_GR_INFO(index=nvr) for nvr in nvrs]) - rmctrl.gr_get_info(self.fd_ctl, self.root, self.subdevice, grInfoListSize=len(infos), grInfoList=ctypes.addressof(infos)) - return [x.data for x in infos] - - def _setup_gpfifos(self): - self.slm_per_thread, self.shader_local_mem = 0, None - - # Set windows addresses to not collide with other allocated buffers. - self.shared_mem_window = 0x729400000000 if self.compute_class >= nv_gpu.BLACKWELL_COMPUTE_A else 0xfe000000 - self.local_mem_window = 0x729300000000 if self.compute_class >= nv_gpu.BLACKWELL_COMPUTE_A else 0xff000000 - - NVComputeQueue().setup(compute_class=self.compute_class, local_mem_window=self.local_mem_window, shared_mem_window=self.shared_mem_window) \ - .signal(self.timeline_signal, self.timeline_value).submit(self) - - cast(NVCopyQueue, NVCopyQueue().wait(self.timeline_signal, self.timeline_value)) \ - .setup(copy_class=self.dma_class) \ - .signal(self.timeline_signal, self.timeline_value + 1).submit(self) - - self.timeline_value += 2 - - def _ensure_has_local_memory(self, required): - if self.slm_per_thread >= required or ((maxlm:=getenv("NV_MAX_LOCAL_MEMORY_PER_THREAD")) > 0 and required >= maxlm): return - - self.slm_per_thread, old_slm_per_thread = round_up(required, 32), self.slm_per_thread - bytes_per_tpc = round_up(round_up(self.slm_per_thread * 32, 0x200) * self.max_warps_per_sm * self.num_sm_per_tpc, 0x8000) - self.shader_local_mem, ok = self._realloc(self.shader_local_mem, round_up(bytes_per_tpc*self.num_tpc_per_gpc*self.num_gpcs, 0x20000)) - - # Realloc failed, restore the old value. - if not ok: self.slm_per_thread = old_slm_per_thread - - cast(NVComputeQueue, NVComputeQueue().wait(self.timeline_signal, self.timeline_value - 1)) \ - .setup(local_mem=self.shader_local_mem.va_addr, local_mem_tpc_bytes=bytes_per_tpc) \ - .signal(self.timeline_signal, self.next_timeline()).submit(self) - - def invalidate_caches(self): - rmctrl.fb_flush_gpu_cache(self.fd_ctl, self.root, self.subdevice, - flags=((nv_gpu.NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES << 2) | (nv_gpu.NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES << 3) | - (nv_gpu.NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE << 4))) - - def on_device_hang(self): - # Prepare fault report. - # TODO: Restore the GPU using NV83DE_CTRL_CMD_CLEAR_ALL_SM_ERROR_STATES if needed. - - report = [] - sm_errors = rmctrl.debug_read_all_sm_error_states(self.fd_ctl, self.root, self.debugger, hTargetChannel=self.debug_channel, numSMsToRead=100) - - if sm_errors.mmuFault.valid: - mmu_info = rmctrl.debug_read_mmu_fault_info(self.fd_ctl, self.root, self.debugger) - for i in range(mmu_info.count): - pfinfo = mmu_info.mmuFaultInfoList[i] - report += [f"MMU fault: 0x{pfinfo.faultAddress:X} | {NV_PFAULT_FAULT_TYPE[pfinfo.faultType]} | {NV_PFAULT_ACCESS_TYPE[pfinfo.accessType]}"] - if DEBUG >= 5: - report += ["GPU mappings:\n"+"\n".join(f"\t0x{x:X} - 0x{x+y-1:X} | {self._debug_mappings[(x,y)]}" for x,y in sorted(self._debug_mappings))] - else: - for i, e in enumerate(sm_errors.smErrorStateArray): - if e.hwwGlobalEsr or e.hwwWarpEsr: report += [f"SM {i} fault: esr={e.hwwGlobalEsr} warp_esr={e.hwwWarpEsr} warp_pc={e.hwwWarpEsrPc64}"] - - raise RuntimeError("\n".join(report)) diff --git a/tinygrad/tinygrad/runtime/ops_python.py b/tinygrad/tinygrad/runtime/ops_python.py deleted file mode 100644 index 0cdc5985..00000000 --- a/tinygrad/tinygrad/runtime/ops_python.py +++ /dev/null @@ -1,225 +0,0 @@ -# pylint: disable=cell-var-from-loop -# a python uops emulator -# works to test the tensor cores, and all the uops in general -# this is the (living) definition of uops -from typing import Optional, Any, TYPE_CHECKING -import pickle, base64, itertools, time, struct, sys -from tinygrad.dtype import DType, dtypes, ImageDType, PtrDType, truncate -from tinygrad.helpers import all_same, getenv, flatten, get_single_element -from tinygrad.device import Compiled, Compiler, Allocator -from tinygrad.uop.ops import exec_alu, Ops, UOp, GroupOp -from tinygrad.renderer import Renderer -from tinygrad.renderer.cstyle import CUDARenderer, MetalRenderer, AMDRenderer, IntelRenderer, ClangRenderer - -def _load(m, i): - if i is None: return 0.0 - if i < 0 or i >= len(m): raise IndexError(f"load out of bounds, size is {len(m)} and access is {i}") - return m[i] - -def load(inp, j=0): - if len(inp) == 2: return [_load(m, x+j if x is not None else None) if gate else default for (m,x,gate),default in zip(*inp)] - return [_load(m, x+j if x is not None else None) for m,x,_ in inp[0]] - -def _store(m, i, v): - if i < 0 or i >= len(m): raise IndexError(f"store out of bounds, size is {len(m)}, access is {i}, value is {v}") - m[i] = v - -class PythonProgram: - def __init__(self, name:str, lib:bytes): - self.uops: list[tuple[Ops, Optional[DType], list[int], Any]] = pickle.loads(lib) - def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - st = time.perf_counter() - warp = list(itertools.product(*[range(x) for x in local_size[::-1]])) - warp_size = len(warp) - for idxs in itertools.product(*[range(x) for x in global_size[::-1]]): - ul: dict[int, Any] = {} - dl: dict[int, DType] = {} - pbufs: list[memoryview] = list(bufs) - pvals: list[int] = list(vals) - i = 0 - loop_ends: dict[int, int] = {} - while i < len(self.uops): - uop, dtype, idp, arg = self.uops[i] - void_ops = {Ops.STORE, Ops.ENDRANGE, Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK} - if uop is Ops.DEFINE_ACC: idp = [idp[0]] - inp = [ul[v] for v in idp if self.uops[v][0] not in void_ops] - dtp = [dl[v] for v in idp if self.uops[v][0] not in void_ops] - if getenv("TRACE"): print(i, uop, dtype, arg, inp, dtp) - if uop is Ops.STORE: - assert len(inp) == 2, "expected store is ([(memory, offset, gate)], [value])" - if dtp[1].count > 1: - for j,val in enumerate(inp[1]): - for (m,o,g),v in zip(inp[0], val): - if g: _store(m, o+j, v) - else: - for (m,o,g),v in zip(*inp): - if g: _store(m, o, v) - i += 1 - continue - if uop is Ops.ENDRANGE: - loop_ends[idp[0]] = i - i = idp[0] - continue - if uop in (Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK): - # in the python emulator, the warp is always in sync - i += 1 - continue - assert dtype is not None, f"{uop} is missing a dtype" - dl[i] = dtype - if uop in {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL}: - assert dtype.fmt is not None and isinstance(dtype, PtrDType) - if TYPE_CHECKING or sys.version_info < (3, 12): assert dtype.fmt != "e" - buf = memoryview(bytearray(dtype.size*dtype.itemsize)) if uop is Ops.DEFINE_LOCAL else pbufs.pop(0) - ul[i] = [buf.cast(dtype.fmt)] * warp_size - elif uop is Ops.DEFINE_VAR: - ul[i] = [pvals.pop(0)] * warp_size - elif uop is Ops.SPECIAL: - if arg[0][0] == 'g': ul[i] = [idxs[2-int(arg[0][-1])]] * warp_size - elif arg[0][0] == 'l': ul[i] = [x[2-int(arg[0][-1])] for x in warp] - elif uop is Ops.CONST: ul[i] = [arg] * warp_size - elif uop is Ops.DEFINE_ACC: - ul[i] = [[inp[0][0][0]] * warp_size for _ in range(dtype.count)] if dtype.count > 1 else [inp[0][0]] * warp_size - elif uop is Ops.INDEX: - ret:list = [] - if isinstance(dtp[0], ImageDType): - for m,ox,oy in zip(inp[0], inp[1][0], inp[1][1]): - if ox < 0 or ox >= dtp[0].shape[1] or oy < 0 or oy >= dtp[0].shape[0]: ret.append((m, None)) - else: ret.append((m, ox*4 + oy*dtp[0].shape[1]*4)) - else: - for m,o in zip(inp[0], inp[1]): ret.append((m,o)) - ul[i] = [(m,o,g) for (m,o),g in zip(ret, inp[2] if len(inp) == 3 else [True]*len(ret))] # set the gate last - elif uop is Ops.CAST and isinstance(dtype, PtrDType): - ul[i] = inp[0] - elif uop is Ops.RANGE: - if i not in ul: ul[i] = [0] * warp_size - else: - for j in range(len(ul[i])): - ul[i][j] += 1 - if ul[i][0] == inp[0][0]: - del ul[i] - i = loop_ends[i] + 1 - continue - elif uop is Ops.VECTORIZE: ul[i] = inp - elif uop is Ops.BITCAST: - assert dtp[0].fmt and dtype.fmt - pack_format, unpack_format = str(warp_size) + dtp[0].fmt, str(warp_size) + dtype.fmt - ul[i] = list(struct.unpack(unpack_format, struct.pack(pack_format, *inp[0]))) - elif uop is Ops.CAST: - ul[i] = [truncate.get(dtype, lambda dt: dt)(dtypes.as_const(x, dtype)) for x in inp[0]] - elif uop is Ops.LOAD: - if dtype.count > 1: - ul[i] = [load([inp[i][j] if i != 0 and dtp[i].count > 1 else inp[i] for i in range(len(inp))], j) for j in range(dtype.count)] - else: - ul[i] = load(inp) - elif uop is Ops.ASSIGN: - for j in range(len(inp[0])): inp[0][j] = inp[1][j] - ul[i] = inp[0] - elif uop is Ops.GEP: ul[i] = inp[0][get_single_element(arg)] - elif uop is Ops.WMMA: - # here are the models for the WMMA instruction on the different hardware - def wmma_helper(WARP_THREADS, K, NUM_A, NUM_B, NUM_C, a_elem, b_elem, c_map): - for cc, tinp, num in zip(("A", "B", "C"), inp, (NUM_A, NUM_B, NUM_C)): - assert len(tinp) == num, f"{cc} must have {num} elements per thread, it has {len(tinp)}" - assert len(flatten(tinp)) == num * warp_size, f"WMMA must have {num * warp_size} total elements for {cc} in WMMA" - assert warp_size > 0 and warp_size % WARP_THREADS == 0, f"must have multiples of {WARP_THREADS} warp threads" - out = [inp[2][elem_idx][:] for elem_idx in range(NUM_C)] - for goff in range(0, warp_size, WARP_THREADS): - for lane_id in range(WARP_THREADS): - for elem_idx in range(NUM_C): # calculate new muls and add to acc - (c_i, c_j) = c_map(lane_id, elem_idx) - out[elem_idx][goff+lane_id] += sum(a_elem(inp[0], _k, c_j, goff) * b_elem(inp[1], c_i, _k, goff) for _k in range(K)) - return out - - # TODO: refactor these to a shared TensorCoreLayout in kernel.py - if arg[4] == "METAL": - # A (2 elements on 32 threads): row major - def a_b_elem(x, i, j, goff): return x[(i%2)][goff+(i//2)%2+(j%4)*2+(i//4)*8+(j//4)*16] - # (i, j), C, D (2 elements on 32 threads): row major same as A/B - def c_map(lane, elem): return (elem + ((lane%2)*2) + ((lane//8)%2)*4, ((lane//2)%4) + (lane//16)*4) - ul[i] = wmma_helper(32, 8, 2, 2, 2, a_b_elem, a_b_elem, c_map) - elif arg[4] == "AMD" and arg[5] == 64: - def a_elem(x, k, row, goff): return x[k%4][goff + (k//4)*16 + row] - def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) # pylint: disable=arguments-out-of-order - def c_map(lane, elem): return (lane%16, (lane//16)*4 + elem) - ul[i] = wmma_helper(64, 16, 4, 4, 4, a_elem, b_elem, c_map) - elif arg[4] == "AMD" and len(inp[0]) == 8: # RDNA4 - def a_elem(x, k, row, goff): return x[k - [0, 4, 4, 8][k//4]][goff + row + [0, 16, 0, 16][k//4]] - def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) - def c_map(lane, elem): return (lane%16, (lane//16)*8 + elem) - ul[i] = wmma_helper(32, 16, 8, 8, 8, a_elem, b_elem, c_map) - elif arg[4] == "AMD": - # A (16 elements on 32 threads): col major, lane 16-32 == lane 0-15 - def a_elem(x, k, row, goff): - assert x[k][goff+row] == x[k][goff+row+16], "warp elements not duplicated properly across lanes" - return x[k][goff+row] - # B (16 elements on 32 threads): row major, lane 16-32 == lane 0-15 - def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) # pylint: disable=arguments-out-of-order - def c_map(lane, elem): return (lane%16, lane//16+elem*2) # (i, j), C, D (8 elements on 32 threads): row major - ul[i] = wmma_helper(32, 16, 16, 16, 8, a_elem, b_elem, c_map) - elif arg[4] == "CUDA": - # (col, row) given (lane, elem) for C & D (4 elements on 32 threads); shared by all tc shapes with M=16 N=8 - def c_map(lane, elem): return (elem%2 + (lane%4)*2, lane//4 + (elem//2)*8) - - if arg[1] == (8,16,16): - def a_elem(x, k, row, goff): return x[k%2 + (row//8)*2 + (k//8)*4][goff + (k//2)%4 + (row%8)*4] - def b_elem(x, col, k, goff): return x[k%2 + (k//8)*2][goff + (k//2)%4 + col*4] - ul[i] = wmma_helper(32, 16, 8, 4, 4, a_elem, b_elem, c_map) - - elif arg[1] == (8,16,8) and arg[2] == dtypes.half: - def a_elem(x, k, row, goff): return x[k%2 + (row//8)*2][goff + k//2 + (row%8)*4] - def b_elem(x, col, k, goff): return x[k%2][goff + k//2 + col*4] - ul[i] = wmma_helper(32, 8, 4, 2, 4, a_elem, b_elem, c_map) - - elif arg[1] == (8,16,8) and arg[2] == dtypes.float: - def a_elem(x, k, row, goff): return x[(k//4)*2 + row//8][goff + k%4 + (row%8)*4] - def b_elem(x, col, k, goff): return x[k//4][goff + k%4 + col*4] - ul[i] = wmma_helper(32, 8, 4, 2, 4, a_elem, b_elem, c_map) - - else: raise NotImplementedError(f"unimplemented tensor core {arg}") - elif arg[4] == "INTEL": - # A (16 elements on 8 threads) - def a_elem(x, k, row, goff): return x[k%2+row*2][goff+k//2] - # B (16 elements on 8 threads) - def b_elem(x, col, k, goff): return x[k][goff+col] - # C, D (8 elements on 8 threads) - def c_map(lane, elem): return (lane, elem) - ul[i] = wmma_helper(8, 16, 16, 16, 8, a_elem, b_elem, c_map) - elif arg[4] == "CPU": - def elem(x, col, row, _): return x[col+row][0] # k is always 0 - def c_map(_, elem): return (elem%16, elem//16) - ul[i] = wmma_helper(1, 1, 16, 16, 256, elem, elem, c_map) - else: raise NotImplementedError(f"unimplemented tensor core {arg}") - elif uop in GroupOp.ALU: - assert all_same([len(x) for x in inp]), f"{[len(x) for x in inp]} doesn't match on {uop}" - assert all_same([dtype] + dtp) or uop in {Ops.CMPNE, Ops.CMPLT, Ops.WHERE}, f"dtype mismatch on {uop}" - ul[i] = [exec_alu(uop, dtype, p) for p in zip(*inp)] - assert i in ul, (uop, dtype, idp, arg) - i += 1 - return time.perf_counter() - st - -class PythonRenderer(Renderer): - device = "PYTHON" - def __init__(self): - if getenv("EMULATE_METAL"): self.device, self.tensor_cores = "METAL", MetalRenderer.tensor_cores - if getenv("EMULATE_AMD"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores - if getenv("EMULATE_AMD_MFMA"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores_mfma - if getenv("EMULATE_AMD_RDNA4"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores_rdna4 - if getenv("EMULATE_CUDA"): self.device, self.tensor_cores = "CUDA", CUDARenderer.tc_sm80 - if getenv("EMULATE_CUDA_SM75"): self.device, self.tensor_cores = "CUDA", CUDARenderer.tc_sm75 - if getenv("EMULATE_INTEL"): self.device, self.suffix, self.tensor_cores = "INTEL", "INTEL", IntelRenderer.tensor_cores - if getenv("EMULATE_AMX"): self.device, self.tensor_cores = "CPU", ClangRenderer.tensor_cores - - def render(self, uops:list[UOp]) -> str: - lops = [(u.op, u.dtype, [uops.index(v) for v in u.src], u.arg) for u in uops] - return base64.b64encode(pickle.dumps(lops)).decode() - -class PythonCompiler(Compiler): - def compile(self, src:str) -> bytes: return base64.b64decode(src) - -class PythonAllocator(Allocator['PythonDevice']): - def _alloc(self, size, options): return memoryview(bytearray(size)) - def _copyin(self, dest, src:memoryview): dest[:] = src - def _copyout(self, dest:memoryview, src): dest[:] = src - -class PythonDevice(Compiled): - def __init__(self, device:str): super().__init__(device, PythonAllocator(self), PythonRenderer(), PythonCompiler(), PythonProgram) diff --git a/tinygrad/tinygrad/runtime/ops_qcom.py b/tinygrad/tinygrad/runtime/ops_qcom.py deleted file mode 100644 index 08501812..00000000 --- a/tinygrad/tinygrad/runtime/ops_qcom.py +++ /dev/null @@ -1,372 +0,0 @@ -from __future__ import annotations -import os, ctypes, functools, mmap, struct, array, math, sys, weakref -assert sys.platform != 'win32' -from types import SimpleNamespace -from typing import Any, cast, ClassVar -from tinygrad.device import BufferSpec -from tinygrad.runtime.support.hcq import HCQBuffer, HWQueue, HCQProgram, HCQCompiled, HCQAllocatorBase, HCQSignal, HCQArgsState, BumpAllocator -from tinygrad.runtime.support.hcq import FileIOInterface, MMIOInterface -from tinygrad.runtime.autogen import kgsl, adreno -from tinygrad.runtime.ops_gpu import CLCompiler, CLDevice -from tinygrad.renderer.cstyle import QCOMRenderer -from tinygrad.helpers import getenv, mv_address, to_mv, round_up, data64_le, prod, fromimport -if getenv("IOCTL"): import extra.qcom_gpu_driver.opencl_ioctl # noqa: F401 # pylint: disable=unused-import - -BUFTYPE_BUF, BUFTYPE_TEX, BUFTYPE_IBO = 0, 1, 2 - -#Parse C-style defines: ___SHIFT and ___MASK from the adreno module into the following format: -# qreg.(=..., =..., ..., =...) -def _qreg_exec(reg, __val=0, **kwargs): - for k, v in kwargs.items(): - __val |= (getattr(adreno, f'{reg[4:]}_{k.upper()}') if v else 0) if type(v) is bool else (v << getattr(adreno, f'{reg[4:]}_{k.upper()}__SHIFT')) - return __val -qreg: Any = type("QREG", (object,), {name[4:].lower(): functools.partial(_qreg_exec, name) for name in adreno.__dict__.keys() if name[:4] == 'REG_'}) - -def next_power2(x): return 1 if x == 0 else 1 << (x - 1).bit_length() - -def parity(val: int): - for i in range(4,1,-1): val ^= val >> (1 << i) - return (~0x6996 >> (val & 0xf)) & 1 - -def pkt7_hdr(opcode: int, cnt: int): return adreno.CP_TYPE7_PKT | cnt & 0x3FFF | parity(cnt) << 15 | (opcode & 0x7F) << 16 | parity(opcode) << 23 - -def pkt4_hdr(reg: int, cnt: int): return adreno.CP_TYPE4_PKT | cnt & 0x7F | parity(cnt) << 7 | (reg & 0x3FFFF) << 8 | parity(reg) << 27 - -class QCOMCompiler(CLCompiler): - def __init__(self, device:str=""): super().__init__(CLDevice(device), 'compile_qcom') - def disassemble(self, lib:bytes): fromimport('extra.disassemblers.adreno', 'disasm')(lib) - -class QCOMSignal(HCQSignal): - def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): - super().__init__(base_buf, **kwargs, timestamp_divider=19.2, dev_t=QCOMDevice) - - def _sleep(self, time_spent_waiting_ms:int): - # Sleep only for only timeline signals. Do it immediately to free cpu. - if self.timeline_for_device is not None: - kgsl.IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID(self.timeline_for_device.fd, context_id=self.timeline_for_device.ctx, - timestamp=self.timeline_for_device.last_cmd, timeout=0xffffffff) - -class QCOMComputeQueue(HWQueue): - def __del__(self): - if self.binded_device is not None: self.binded_device.allocator.free(self.hw_page, self.hw_page.size, BufferSpec(cpu_access=True, nolru=True)) - - def cmd(self, opcode: int, *vals: int): self.q(pkt7_hdr(opcode, len(vals)), *vals) - - def reg(self, reg: int, *vals: int): self.q(pkt4_hdr(reg, len(vals)), *vals) - - def _cache_flush(self, write_back=True, invalidate=False, sync=True, memsync=False): - # TODO: 7xx support. - if write_back: self.cmd(adreno.CP_EVENT_WRITE, adreno.CACHE_FLUSH_TS, *data64_le(QCOMDevice.dummy_addr), 0) # dirty cache write-back. - if invalidate: self.cmd(adreno.CP_EVENT_WRITE, adreno.CACHE_INVALIDATE) # invalidate cache lines (following reads from RAM). - if memsync: self.cmd(adreno.CP_WAIT_MEM_WRITES) - if sync: self.cmd(adreno.CP_WAIT_FOR_IDLE) - - def memory_barrier(self): - self._cache_flush(write_back=True, invalidate=True, sync=True, memsync=True) - return self - - def signal(self, signal:QCOMSignal, value=0, ts=False): - self.cmd(adreno.CP_WAIT_FOR_IDLE) - if QCOMDevice.gpu_id < 700: - self.cmd(adreno.CP_EVENT_WRITE, qreg.cp_event_write_0(event=adreno.CACHE_FLUSH_TS, timestamp=ts), - *data64_le(signal.timestamp_addr if ts else signal.value_addr), qreg.cp_event_write_3(value & 0xFFFFFFFF)) - self._cache_flush(write_back=True, invalidate=False, sync=False, memsync=False) - else: - # TODO: support devices starting with 8 Gen 1. Also, 700th series have convenient CP_GLOBAL_TIMESTAMP and CP_LOCAL_TIMESTAMP - raise RuntimeError('CP_EVENT_WRITE7 is not supported') - return self - - def timestamp(self, signal:QCOMSignal): return self.signal(signal, 0, ts=True) - - def wait(self, signal:QCOMSignal, value=0): - self.cmd(adreno.CP_WAIT_REG_MEM, qreg.cp_wait_reg_mem_0(function=adreno.WRITE_GE, poll=adreno.POLL_MEMORY),*data64_le(signal.value_addr), - qreg.cp_wait_reg_mem_3(ref=value&0xFFFFFFFF), qreg.cp_wait_reg_mem_4(mask=0xFFFFFFFF), qreg.cp_wait_reg_mem_5(delay_loop_cycles=32)) - return self - - def _build_gpu_command(self, dev:QCOMDevice, hw_addr=None): - to_mv((hw_page_addr:=hw_addr or dev.cmd_buf_allocator.alloc(len(self._q) * 4)), len(self._q) * 4).cast('I')[:] = array.array('I', self._q) - obj = kgsl.struct_kgsl_command_object(gpuaddr=hw_page_addr, size=len(self._q) * 4, flags=kgsl.KGSL_CMDLIST_IB) - submit_req = kgsl.struct_kgsl_gpu_command(cmdlist=ctypes.addressof(obj), numcmds=1, context_id=dev.ctx, - cmdsize=ctypes.sizeof(kgsl.struct_kgsl_command_object)) - return submit_req, obj - - def bind(self, dev:QCOMDevice): - self.binded_device = dev - self.hw_page = dev.allocator.alloc(len(self._q) * 4, BufferSpec(cpu_access=True, nolru=True)) - self.submit_req, self.obj = self._build_gpu_command(self.binded_device, self.hw_page.va_addr) - # From now on, the queue is on the device for faster submission. - self._q = to_mv(self.obj.gpuaddr, len(self._q) * 4).cast("I") - - def _submit(self, dev:QCOMDevice): - if self.binded_device == dev: submit_req = self.submit_req - else: submit_req, _ = self._build_gpu_command(dev) - dev.last_cmd = kgsl.IOCTL_KGSL_GPU_COMMAND(dev.fd, __payload=submit_req).timestamp - - def exec(self, prg:QCOMProgram, args_state:QCOMArgsState, global_size, local_size): - self.bind_args_state(args_state) - - def cast_int(x, ceil=False): return (math.ceil(x) if ceil else int(x)) if isinstance(x, float) else x - global_size_mp = [cast_int(g*l) for g,l in zip(global_size, local_size)] - - self.cmd(adreno.CP_SET_MARKER, qreg.a6xx_cp_set_marker_0(mode=adreno.RM6_COMPUTE)) - self.reg(adreno.REG_A6XX_HLSQ_INVALIDATE_CMD, qreg.a6xx_hlsq_invalidate_cmd(cs_state=True, cs_ibo=True)) - self.reg(adreno.REG_A6XX_HLSQ_INVALIDATE_CMD, 0x0) - self.reg(adreno.REG_A6XX_SP_CS_TEX_COUNT, qreg.a6xx_sp_cs_tex_count(0x80)) - self.reg(adreno.REG_A6XX_SP_CS_IBO_COUNT, qreg.a6xx_sp_cs_ibo_count(0x40)) - self.reg(adreno.REG_A6XX_SP_MODE_CONTROL, qreg.a6xx_sp_mode_control(isammode=adreno.ISAMMODE_CL)) - self.reg(adreno.REG_A6XX_SP_PERFCTR_ENABLE, qreg.a6xx_sp_perfctr_enable(cs=True)) - self.reg(adreno.REG_A6XX_SP_TP_MODE_CNTL, qreg.a6xx_sp_tp_mode_cntl(isammode=adreno.ISAMMODE_CL, unk3=2)) - self.reg(adreno.REG_A6XX_TPL1_DBG_ECO_CNTL, 0) - self.cmd(adreno.CP_WAIT_FOR_IDLE) - - self.reg(adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, - qreg.a6xx_hlsq_cs_ndrange_0(kerneldim=3, localsizex=local_size[0] - 1, localsizey=local_size[1] - 1, localsizez=local_size[2] - 1), - global_size_mp[0], 0, global_size_mp[1], 0, global_size_mp[2], 0, 0xccc0cf, 0xfc | qreg.a6xx_hlsq_cs_cntl_1(threadsize=adreno.THREAD64), - cast_int(global_size[0], ceil=True), cast_int(global_size[1], ceil=True), cast_int(global_size[2], ceil=True)) - - self.reg(adreno.REG_A6XX_SP_CS_CTRL_REG0, - qreg.a6xx_sp_cs_ctrl_reg0(threadsize=adreno.THREAD64, halfregfootprint=prg.hregs, fullregfootprint=prg.fregs, branchstack=prg.brnchstck), - qreg.a6xx_sp_cs_unknown_a9b1(unk6=True, shared_size=prg.shared_size), 0, prg.prg_offset, *data64_le(prg.lib_gpu.va_addr), - qreg.a6xx_sp_cs_pvt_mem_param(memsizeperitem=prg.pvtmem_size_per_item), *data64_le(prg.dev._stack.va_addr), - qreg.a6xx_sp_cs_pvt_mem_size(totalpvtmemsize=prg.pvtmem_size_total)) - - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_CONSTANTS, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=1024 // 4), - *data64_le(args_state.buf.va_addr)) - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_SHADER, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=round_up(prg.image_size, 128) // 128), - *data64_le(prg.lib_gpu.va_addr)) - - self.reg(adreno.REG_A6XX_HLSQ_CONTROL_2_REG, 0xfcfcfcfc, 0xfcfcfcfc, 0xfcfcfcfc, 0xfc, qreg.a6xx_hlsq_cs_cntl(constlen=1024 // 4, enabled=True)) - - self.reg(adreno.REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET, qreg.a6xx_sp_cs_pvt_mem_hw_stack_offset(prg.hw_stack_offset)) - self.reg(adreno.REG_A6XX_SP_CS_INSTRLEN, qreg.a6xx_sp_cs_instrlen(prg.image_size // 4)) - - if args_state.prg.samp_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_SHADER, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_TEX, num_unit=args_state.prg.samp_cnt), - *data64_le(args_state.buf.va_addr + args_state.prg.samp_off)) - self.reg(adreno.REG_A6XX_SP_CS_TEX_SAMP, *data64_le(args_state.buf.va_addr + args_state.prg.samp_off)) - self.reg(adreno.REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, *data64_le(prg.dev.border_color_buf.va_addr)) - - if args_state.prg.tex_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_CONSTANTS, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_TEX, num_unit=min(16, args_state.prg.tex_cnt)), - *data64_le(args_state.buf.va_addr + args_state.prg.tex_off)) - self.reg(adreno.REG_A6XX_SP_CS_TEX_CONST, *data64_le(args_state.buf.va_addr + args_state.prg.tex_off)) - - if args_state.prg.ibo_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST6_IBO, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=args_state.prg.ibo_cnt), - *data64_le(args_state.buf.va_addr + args_state.prg.ibo_off)) - self.reg(adreno.REG_A6XX_SP_CS_IBO, *data64_le(args_state.buf.va_addr + args_state.prg.ibo_off)) - - self.reg(adreno.REG_A6XX_SP_CS_CONFIG, - qreg.a6xx_sp_cs_config(enabled=True, nsamp=args_state.prg.samp_cnt, ntex=args_state.prg.tex_cnt, nibo=args_state.prg.ibo_cnt)) - self.cmd(adreno.CP_RUN_OPENCL, 0) - self._cache_flush(write_back=True, invalidate=False, sync=False, memsync=False) - return self - -class QCOMArgsState(HCQArgsState): - def __init__(self, buf:HCQBuffer, prg:QCOMProgram, bufs:tuple[HCQBuffer, ...], vals:tuple[int, ...]=()): - super().__init__(buf, prg, bufs, vals=vals) - - if len(bufs) + len(vals) != len(prg.buf_info): raise RuntimeError(f'incorrect args size given={len(bufs)+len(vals)} != want={len(prg.buf_info)}') - - self.buf_info, self.args_info = prg.buf_info[:len(bufs)], prg.buf_info[len(bufs):] - - ctypes.memset(cast(int, self.buf.va_addr), 0, prg.kernargs_alloc_size) - for cnst_val,cnst_off,cnst_sz in prg.consts_info: to_mv(self.buf.va_addr + cnst_off, cnst_sz)[:] = cnst_val.to_bytes(cnst_sz, byteorder='little') - - if prg.samp_cnt > 0: to_mv(self.buf.va_addr + prg.samp_off, len(prg.samplers) * 4).cast('I')[:] = array.array('I', prg.samplers) - for i, b in enumerate(bufs): - if prg.buf_info[i].type in {BUFTYPE_TEX, BUFTYPE_IBO}: - obj = b.texture_info.desc if prg.buf_info[i].type is BUFTYPE_TEX else b.texture_info.ibo - to_mv(self.buf.va_addr + prg.buf_info[i].offset, len(obj) * 4).cast('I')[:] = array.array('I', obj) - self.bind_sints_to_buf(b.va_addr, buf=self.buf, fmt='Q', offset=self.buf_info[i].offset+(0 if self.buf_info[i].type is BUFTYPE_BUF else 16)) - - for i, v in enumerate(vals): self.bind_sints_to_buf(v, buf=self.buf, fmt='I', offset=self.args_info[i].offset) - -class QCOMProgram(HCQProgram): - def __init__(self, dev: QCOMDevice, name: str, lib: bytes): - self.dev: QCOMDevice = dev - self.name, self.lib = name, lib - self._parse_lib() - - self.lib_gpu: HCQBuffer = self.dev.allocator.alloc(self.image_size, buf_spec:=BufferSpec(cpu_access=True, nolru=True)) - to_mv(cast(int, self.lib_gpu.va_addr), self.image_size)[:] = self.image - - self.pvtmem_size_per_item: int = round_up(self.pvtmem, 512) >> 9 - self.pvtmem_size_total: int = self.pvtmem_size_per_item * 128 * 2 - self.hw_stack_offset: int = round_up(next_power2(round_up(self.pvtmem, 512)) * 128 * 16, 0x1000) - self.shared_size: int = max(1, (self.shmem - 1) // 1024) - self.max_threads = min(1024, ((384 * 32) // (max(1, (self.fregs + round_up(self.hregs, 2) // 2)) * 128)) * 128) - dev._ensure_stack_size(self.hw_stack_offset * 4) - - kernargs_alloc_size = round_up(2048 + (self.tex_cnt + self.ibo_cnt) * 0x40 + self.samp_cnt * 0x10, 0x100) - super().__init__(QCOMArgsState, self.dev, self.name, kernargs_alloc_size=kernargs_alloc_size) - weakref.finalize(self, self._fini, self.dev, self.lib_gpu, buf_spec) - - def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - if self.max_threads < prod(local_size): raise RuntimeError("Too many resources requested for launch") - if any(g*l>mx for g,l,mx in zip(global_size, local_size, [65536, 65536, 65536])) and any(l>mx for l,mx in zip(local_size, [1024, 1024, 1024])): - raise RuntimeError(f"Invalid global/local dims {global_size=}, {local_size=}") - return super().__call__(*bufs, global_size=global_size, local_size=local_size, vals=vals, wait=wait) - - def _parse_lib(self): - def _read_lib(off) -> int: return struct.unpack("I", self.lib[off:off+4])[0] - - # Extract image binary - self.image_size = _read_lib(0x100) - self.image = bytearray(self.lib[(image_offset:=_read_lib(0xc0)):image_offset+self.image_size]) - - # Parse image descriptors - image_desc_off = _read_lib(0x110) - self.prg_offset, self.brnchstck = _read_lib(image_desc_off+0xc4), _read_lib(image_desc_off+0x108) // 2 - self.pvtmem, self.shmem = _read_lib(image_desc_off+0xc8), _read_lib(image_desc_off+0xd8) - - # Fill up constants and buffers info - self.buf_info, self.consts_info = [], [] - - # Collect sampler info. - self.samp_cnt = samp_cnt_in_file = _read_lib(image_desc_off + 0xdc) - assert self.samp_cnt <= 1, "Up to one sampler supported" - if self.samp_cnt: - self.samp_cnt += 1 - self.samplers = [qreg.a6xx_tex_samp_0(wrap_s=(clamp_mode:=adreno.A6XX_TEX_CLAMP_TO_BORDER), wrap_t=clamp_mode, wrap_r=clamp_mode), - qreg.a6xx_tex_samp_1(unnorm_coords=True, cubemapseamlessfiltoff=True), 0, 0, 0, 0, 0, 0] - - # Collect kernel arguments (buffers) info. - bdoff = round_up(image_desc_off + 0x158 + len(self.name), 4) + 8 * samp_cnt_in_file - while bdoff + 32 <= len(self.lib): - length, _, _, offset_words, _, _, _, typ = struct.unpack("IIIIIIII", self.lib[bdoff:bdoff+32]) - if length == 0: break - self.buf_info.append(SimpleNamespace(offset=offset_words * 4, type=typ)) - bdoff += length - - # Setting correct offsets to textures/ibos. - self.tex_cnt, self.ibo_cnt = sum(x.type is BUFTYPE_TEX for x in self.buf_info), sum(x.type is BUFTYPE_IBO for x in self.buf_info) - self.ibo_off, self.tex_off, self.samp_off = 2048, 2048 + 0x40 * self.ibo_cnt, 2048 + 0x40 * self.tex_cnt + 0x40 * self.ibo_cnt - cur_ibo_off, cur_tex_off = self.ibo_off, self.tex_off - for x in self.buf_info: - if x.type is BUFTYPE_IBO: x.offset, cur_ibo_off = cur_ibo_off, cur_ibo_off + 0x40 - elif x.type is BUFTYPE_TEX: x.offset, cur_tex_off = cur_tex_off, cur_tex_off + 0x40 - - if _read_lib(0xb0) != 0: # check if we have constants. - cdoff = _read_lib(0xac) - while cdoff + 40 <= image_offset: - cnst, offset_words, _, is32 = struct.unpack("I", self.lib[cdoff:cdoff+4])[0], *struct.unpack("III", self.lib[cdoff+16:cdoff+28]) - self.consts_info.append((cnst, offset_words * (sz_bytes:=(2 << is32)), sz_bytes)) - cdoff += 40 - - # Registers info - reg_desc_off = _read_lib(0x34) - self.fregs, self.hregs = _read_lib(reg_desc_off + 0x14), _read_lib(reg_desc_off + 0x18) - -class QCOMTextureInfo: - def __init__(self, pitch:int, real_stride:int, desc:list[int], ibo:list[int]): - self.pitch, self.real_stride, self.desc, self.ibo = pitch, real_stride, desc, ibo - -class QCOMAllocator(HCQAllocatorBase): - def _alloc(self, size:int, options:BufferSpec) -> HCQBuffer: - # Recalculate real size for texture - if options.image is not None: - imgw, imgh, itemsize_log = options.image.shape[1], options.image.shape[0], int(math.log2(options.image.itemsize)) - pitchalign = max(6, 11 - int(math.log2(imgh))) if imgh > 1 else 6 - align_up = max(1, (8 // itemsize_log + 1) - imgh // 32) if pitchalign == 6 else (2 ** (pitchalign - itemsize_log - 2)) - - granularity = 128 if options.image.itemsize == 4 else 256 - pitch_add = (1 << pitchalign) if min(next_power2(imgw), round_up(imgw, granularity)) - align_up + 1 <= imgw and imgw > granularity//2 else 0 - pitch = round_up((real_stride:=imgw * 4 * options.image.itemsize), 1 << pitchalign) + pitch_add - size = pitch * imgh - - buf = HCQBuffer(options.external_ptr, size) if options.external_ptr else self.dev._gpu_alloc(size) - - if options.image is not None: - tex_fmt = adreno.FMT6_32_32_32_32_FLOAT if options.image.itemsize == 4 else adreno.FMT6_16_16_16_16_FLOAT - desc = [qreg.a6xx_tex_const_0(0x8, swiz_x=0, swiz_y=1, swiz_z=2, swiz_w=3, fmt=tex_fmt), qreg.a6xx_tex_const_1(width=imgw, height=imgh), - qreg.a6xx_tex_const_2(type=adreno.A6XX_TEX_2D, pitch=pitch, pitchalign=pitchalign-6), 0, - *data64_le(buf.va_addr), qreg.a6xx_tex_const_6(plane_pitch=0x400000), qreg.a6xx_tex_const_7(13)] - - buf.texture_info = QCOMTextureInfo(pitch, real_stride, desc, [desc[0] & (~0xffff), *desc[1:len(desc)]]) - return buf - - def _do_copy(self, src_addr, dest_addr, src_size, real_size, src_stride, dest_stride, dest_off=0, src_off=0): - while src_off < src_size: - ctypes.memmove(dest_addr+dest_off, src_addr+src_off, real_size) - src_off, dest_off = src_off+src_stride, dest_off+dest_stride - - def _copyin(self, dest:HCQBuffer, src:memoryview): - stride, pitch = (src.nbytes, src.nbytes) if (ti:=cast(QCOMTextureInfo, dest.texture_info)) is None else (ti.real_stride, ti.pitch) - self._do_copy(mv_address(src), dest.va_addr, src.nbytes, stride, stride, pitch) - - def _copyout(self, dest:memoryview, src:HCQBuffer): - self.dev.synchronize() - - stride, pitch = (src.size, src.size) if (ti:=cast(QCOMTextureInfo, src.texture_info)) is None else (ti.real_stride, ti.pitch) - self._do_copy(src.va_addr, mv_address(dest), src.size, stride, pitch, stride) - - def _as_buffer(self, src:HCQBuffer) -> memoryview: - self.dev.synchronize() - return to_mv(cast(int, src.va_addr), src.size) - - def _free(self, opaque, options:BufferSpec): - self.dev.synchronize() - self.dev._gpu_free(opaque) - -class QCOMDevice(HCQCompiled): - devices: ClassVar[list[HCQCompiled]] = [] - signal_pages: ClassVar[list[HCQBuffer]] = [] - signal_pool: ClassVar[list[HCQBuffer]] = [] - - gpu_id: int = 0 - dummy_addr: int = 0 - - def __init__(self, device:str=""): - self.fd = FileIOInterface('/dev/kgsl-3d0', os.O_RDWR) - QCOMDevice.dummy_addr = cast(int, self._gpu_alloc(0x1000).va_addr) - - flags = kgsl.KGSL_CONTEXT_PREAMBLE | kgsl.KGSL_CONTEXT_PWR_CONSTRAINT | kgsl.KGSL_CONTEXT_NO_FAULT_TOLERANCE | kgsl.KGSL_CONTEXT_NO_GMEM_ALLOC \ - | kgsl.KGSL_CONTEXT_PRIORITY(8) | kgsl.KGSL_CONTEXT_PREEMPT_STYLE(kgsl.KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN) - self.ctx = kgsl.IOCTL_KGSL_DRAWCTXT_CREATE(self.fd, flags=flags).drawctxt_id - - self.cmd_buf = self._gpu_alloc(16 << 20) - self.cmd_buf_allocator = BumpAllocator(size=self.cmd_buf.size, base=cast(int, self.cmd_buf.va_addr), wrap=True) - - self.border_color_buf = self._gpu_alloc(0x1000, fill_zeroes=True) - - self.last_cmd:int = 0 - - # Set max power - struct.pack_into('IIQQ', pwr:=memoryview(bytearray(0x18)), 0, 1, self.ctx, mv_address(_:=memoryview(array.array('I', [1]))), 4) - kgsl.IOCTL_KGSL_SETPROPERTY(self.fd, type=kgsl.KGSL_PROP_PWR_CONSTRAINT, value=mv_address(pwr), sizebytes=pwr.nbytes) - - # Load info about qcom device - info = kgsl.struct_kgsl_devinfo() - kgsl.IOCTL_KGSL_DEVICE_GETPROPERTY(self.fd, type=kgsl.KGSL_PROP_DEVICE_INFO, value=ctypes.addressof(info), sizebytes=ctypes.sizeof(info)) - QCOMDevice.gpu_id = ((info.chip_id >> 24) & 0xFF) * 100 + ((info.chip_id >> 16) & 0xFF) * 10 + ((info.chip_id >> 8) & 0xFF) - if QCOMDevice.gpu_id >= 700: raise RuntimeError(f"Unsupported GPU: {QCOMDevice.gpu_id}") - - super().__init__(device, QCOMAllocator(self), QCOMRenderer(), QCOMCompiler(device), functools.partial(QCOMProgram, self), - QCOMSignal, QCOMComputeQueue, None) - - def _gpu_alloc(self, size:int, flags:int=0, uncached=False, fill_zeroes=False) -> HCQBuffer: - flags |= kgsl.KGSL_MEMALIGN(alignment_hint:=12) | kgsl.KGSL_MEMFLAGS_USE_CPU_MAP - if uncached: flags |= kgsl.KGSL_CACHEMODE(kgsl.KGSL_CACHEMODE_UNCACHED) - - alloc = kgsl.IOCTL_KGSL_GPUOBJ_ALLOC(self.fd, size=(bosz:=round_up(size, 1< middleware <-> runtime <-> hardware -# with REMOTE tinygrad is frontend <-> middleware <-> RemoteDevice ///HTTP/// remote_server <-> runtime <-> hardware -# this client and server can be on the same machine, same network, or just same internet -# it should be a secure (example: no use of pickle) boundary. HTTP is used for RPC - -from __future__ import annotations -from typing import Callable, Iterator, Optional, Any, cast -from collections import defaultdict -from dataclasses import dataclass, field, replace -import multiprocessing, functools, itertools, asyncio, http, http.client, hashlib, time, os, binascii, struct, ast, contextlib, weakref -from tinygrad.renderer import Renderer, ProgramSpec -from tinygrad.dtype import DTYPES_DICT, dtypes -from tinygrad.uop.ops import UOp, Ops, Variable, sint -from tinygrad.helpers import getenv, DEBUG, fromimport, unwrap, Timing -from tinygrad.engine.jit import GraphRunner, MultiGraphRunner, ExecItem, graph_class -from tinygrad.engine.realize import CompiledRunner, BufferXfer -from tinygrad.device import Compiled, Buffer, Allocator, Compiler, Device, BufferSpec -from tinygrad.runtime.graph.cpu import CPUGraph - -# ***** API ***** - -@dataclass(frozen=True) -class RemoteRequest: session: tuple[str, int]|None = field(default=None, kw_only=True) - -@dataclass(frozen=True) -class SessionFree(RemoteRequest): pass - -@dataclass(frozen=True) -class RemoteProperties: - real_device: str - renderer: tuple[str, str, tuple[Any, ...]] - graph_supported: bool - graph_supports_multi: bool - transfer_supported: bool - offset_supported: bool - -@dataclass(frozen=True) -class GetProperties(RemoteRequest): pass - -@dataclass(frozen=True) -class BufferAlloc(RemoteRequest): buffer_num: int; size: int; options: BufferSpec # noqa: E702 - -@dataclass(frozen=True) -class BufferOffset(RemoteRequest): buffer_num: int; size: int; offset: int; sbuffer_num: int # noqa: E702 - -@dataclass(frozen=True) -class BufferFree(RemoteRequest): buffer_num: int # noqa: E702 - -@dataclass(frozen=True) -class CopyIn(RemoteRequest): buffer_num: int; datahash: str # noqa: E702 - -@dataclass(frozen=True) -class CopyOut(RemoteRequest): buffer_num: int - -@dataclass(frozen=True) -class Transfer(RemoteRequest): buffer_num: int; ssession: tuple[str, int]; sbuffer_num: int # noqa: E702 - -@dataclass(frozen=True) -class ProgramAlloc(RemoteRequest): name: str; datahash: str # noqa: E702 - -@dataclass(frozen=True) -class ProgramFree(RemoteRequest): name: str; datahash: str # noqa: E702 - -@dataclass(frozen=True) -class ProgramExec(RemoteRequest): - name: str; datahash: str; bufs: tuple[int, ...]; vals: tuple[int, ...] # noqa: E702 - global_size: Optional[tuple[int, ...]]; local_size: Optional[tuple[int, ...]]; wait: bool # noqa: E702 - -@dataclass(frozen=True) -class GraphComputeItem: - session: tuple[str, int] - name: str - datahash: str - bufs: tuple[int, ...] - vars: tuple[Variable, ...] - fixedvars: dict[Variable, int] - ins: tuple[int, ...] - outs: tuple[int, ...] - global_size: tuple[sint, ...]|None - local_size: tuple[sint, ...]|None - -@dataclass(frozen=True) -class GraphAlloc(RemoteRequest): - graph_num: int - jit_cache: tuple[GraphComputeItem|Transfer, ...] - bufs: tuple[tuple[tuple[str, int], int], ...] - var_vals: dict[Variable, int] - -@dataclass(frozen=True) -class GraphFree(RemoteRequest): - graph_num: int - -@dataclass(frozen=True) -class GraphExec(RemoteRequest): - graph_num: int - bufs: tuple[tuple[tuple[str, int], int], ...] - var_vals: dict[Variable, int] - wait: bool - -# for safe deserialization -eval_globals = {x.__name__:x for x in [SessionFree, RemoteProperties, GetProperties, BufferAlloc, BufferOffset, BufferFree, CopyIn, CopyOut, Transfer, - ProgramAlloc, ProgramFree, ProgramExec, GraphComputeItem, GraphAlloc, GraphFree, GraphExec, BufferSpec, UOp, - Ops, dtypes]} -attribute_whitelist: dict[Any, set[str]] = {dtypes: {*DTYPES_DICT.keys(), 'imagef', 'imageh'}, Ops: {x.name for x in Ops}} -eval_fxns = {ast.Constant: lambda x: x.value, ast.Tuple: lambda x: tuple(map(safe_eval, x.elts)), ast.List: lambda x: list(map(safe_eval, x.elts)), - ast.Dict: lambda x: {safe_eval(k):safe_eval(v) for k,v in zip(x.keys, x.values)}, - ast.Call: lambda x: safe_eval(x.func)(*[safe_eval(arg) for arg in x.args], **{kwarg.arg: safe_eval(kwarg.value) for kwarg in x.keywords}), - ast.Name: lambda x: eval_globals[x.id], ast.Attribute: lambda x: safe_getattr(safe_eval(x.value), x.attr)} -def safe_getattr(value, attr): - assert attr in attribute_whitelist.get(value, set()), f'getattr({value}, {repr(attr)}) is not whitelisted' - return getattr(value, attr) -def safe_eval(node): return eval_fxns[node.__class__](node) - -class BatchRequest: - def __init__(self): - self._q: list[RemoteRequest] = [] - self._h: dict[str, bytes] = {} - def h(self, d:bytes|memoryview) -> str: - datahash = hashlib.sha256(d).hexdigest() # NOTE: this is very slow, should use blake3 on gpu instead - if datahash not in self._h: - self._h[datahash] = bytes.fromhex(datahash)+struct.pack(" bytes: - self.h(repr(self._q).encode()) - return b''.join(self._h.values()) - def deserialize(self, dat:bytes) -> BatchRequest: - ptr = 0 - while ptr < len(dat): - datahash, datalen = binascii.hexlify(dat[ptr:ptr+0x20]).decode(), struct.unpack(" tuple[http.HTTPStatus, bytes]: - status, ret = http.HTTPStatus.OK, b"" - if path == "/batch" and method == "POST": - # TODO: streaming deserialize? - req = BatchRequest().deserialize(body) - # the cmds are always last (currently in datahash) - for c in req._q: - if DEBUG >= 1: print(c) - session, dev = self.sessions[unwrap(c.session)], Device[f"{self.base_device}:{unwrap(c.session)[1]}"] - match c: - case SessionFree(): del self.sessions[unwrap(c.session)] - case GetProperties(): - cls, args = dev.renderer.__reduce__() - # CPUGraph re-renders kernel from uops specified in CompiledRunner, this is not supported - graph_cls = gt if (gt:=graph_class(Device[self.base_device])) is not CPUGraph else None - rp = RemoteProperties( - real_device=dev.device, renderer=(cls.__module__, cls.__name__, args), - graph_supported=graph_cls is not None, graph_supports_multi=graph_cls is not None and issubclass(graph_cls, MultiGraphRunner), - transfer_supported=hasattr(dev.allocator, '_transfer'), offset_supported=hasattr(dev.allocator, '_offset'), - ) - ret = repr(rp).encode() - case BufferAlloc(): - assert c.buffer_num not in session.buffers, f"buffer {c.buffer_num} already allocated" - session.buffers[c.buffer_num] = Buffer(dev.device, c.size, dtypes.uint8, options=c.options, preallocate=True) - case BufferOffset(): - assert c.buffer_num not in session.buffers, f"buffer {c.buffer_num} already exists" - session.buffers[c.buffer_num] = session.buffers[c.sbuffer_num].view(c.size, dtypes.uint8, c.offset).allocate() - case BufferFree(): del session.buffers[c.buffer_num] - case CopyIn(): session.buffers[c.buffer_num].copyin(memoryview(bytearray(req._h[c.datahash]))) - case CopyOut(): session.buffers[c.buffer_num].copyout(memoryview(ret:=bytearray(session.buffers[c.buffer_num].nbytes))) - case Transfer(): - ssession, sdev = self.sessions[c.ssession], Device[f"{self.base_device}:{unwrap(c.ssession)[1]}"] - dbuf, sbuf = session.buffers[c.buffer_num], ssession.buffers[c.sbuffer_num] - assert dbuf.nbytes == sbuf.nbytes, f"{dbuf.nbytes} != {sbuf.nbytes}" - assert hasattr(dev.allocator, '_transfer'), f"Device {dev.device} doesn't support transfers" - dev.allocator._transfer(dbuf._buf, sbuf._buf, dbuf.nbytes, dest_dev=dev, src_dev=sdev) - case ProgramAlloc(): - lib = dev.compiler.compile_cached(req._h[c.datahash].decode()) - session.programs[(c.name, c.datahash)] = dev.runtime(c.name, lib) - case ProgramFree(): del session.programs[(c.name, c.datahash)] - case ProgramExec(): - bufs = [session.buffers[x]._buf for x in c.bufs] - extra_args = {k:v for k,v in [("global_size", c.global_size), ("local_size", c.local_size)] if v is not None} - r = session.programs[(c.name, c.datahash)](*bufs, vals=c.vals, wait=c.wait, **extra_args) - if r is not None: ret = str(r).encode() - case GraphAlloc(): - graph_fn: Callable = unwrap(dev.graph) - def _parse_ji(gi: GraphComputeItem|Transfer): - match gi: - case GraphComputeItem(): - prg = self.sessions[gi.session].programs[(gi.name, gi.datahash)] - ps = ProgramSpec(gi.name, '', f"{self.base_device}:{gi.session[1]}", UOp(Ops.NOOP), - vars=list(gi.vars), ins=list(gi.ins), outs=list(gi.outs), - global_size=list(cast(tuple[int], gi.global_size)) if gi.global_size is not None else None, - local_size=list(cast(tuple[int], gi.local_size)) if gi.local_size is not None else None) - return ExecItem(CompiledRunner(ps, precompiled=b'', prg=prg), [self.sessions[gi.session].buffers[buf] for buf in gi.bufs], - fixedvars=gi.fixedvars) - case Transfer(): - dbuf, sbuf = self.sessions[unwrap(gi.session)].buffers[gi.buffer_num], self.sessions[gi.ssession].buffers[gi.sbuffer_num] - assert dbuf.nbytes == sbuf.nbytes, f"{dbuf.nbytes} != {sbuf.nbytes}" - return ExecItem(BufferXfer(dbuf.nbytes, dbuf.device, sbuf.device), [dbuf, sbuf]) - assert c.graph_num not in session.graphs, f"graph {c.graph_num} already allocated" - session.graphs[c.graph_num] = graph_fn(list(map(_parse_ji, c.jit_cache)), [self.sessions[s].buffers[i] for s,i in c.bufs], c.var_vals) - case GraphFree(): del session.graphs[c.graph_num] - case GraphExec(): - r = session.graphs[c.graph_num]([self.sessions[s].buffers[i] for s,i in c.bufs], c.var_vals, wait=c.wait) - if r is not None: ret = str(r).encode() - else: status, ret = http.HTTPStatus.NOT_FOUND, b"Not Found" - return status, ret - -def remote_server(port:int): - device = getenv("REMOTEDEV", next(Device.get_available_devices()) if Device.DEFAULT == "REMOTE" else Device.DEFAULT) - async def _inner_async(port:int, device:str): - print(f"start remote server on {port} with device {device}") - await (await asyncio.start_server(RemoteHandler(device), host='', port=port)).serve_forever() - asyncio.run(_inner_async(port, device)) - -# ***** frontend ***** - -class RemoteAllocator(Allocator['RemoteDevice']): - def __init__(self, dev:RemoteDevice): - if dev.properties.offset_supported: self._offset = self._dyn_offset - super().__init__(dev) - # TODO: ideally we shouldn't have to deal with images here - def _alloc(self, size:int, options:BufferSpec) -> int: - self.dev.q(BufferAlloc(buffer_num:=next(self.dev.buffer_num), size, options)) - return buffer_num - # TODO: options should not be here in any Allocator - def _free(self, opaque:int, options): - try: self.dev.q(BufferFree(opaque)) - except (TypeError, AttributeError): pass - def _copyin(self, dest:int, src:memoryview): self.dev.q(CopyIn(dest, self.dev.conn.req.h(src))) - def _copyout(self, dest:memoryview, src:int): - resp = self.dev.q(CopyOut(src), wait=True) - assert len(resp) == len(dest), f"buffer length mismatch {len(resp)} != {len(dest)}" - dest[:] = resp - def _transfer(self, dest, src, sz, src_dev, dest_dev): - if dest_dev.properties.transfer_supported and src_dev.conn == dest_dev.conn: - dest_dev.q(Transfer(dest, src_dev.session, src)) - else: - src_dev.allocator._copyout(tmp:=memoryview(bytearray(sz)), src) - dest_dev.allocator._copyin(dest, tmp) - def _dyn_offset(self, opaque:int, size:int, offset:int) -> int: - self.dev.q(BufferOffset(buffer_num:=next(self.dev.buffer_num), size, offset, opaque)) - return buffer_num - -class RemoteProgram: - def __init__(self, dev:RemoteDevice, name:str, lib:bytes): - self.dev, self.name = dev, name - self.datahash = self.dev.conn.req.h(lib) - self.dev.q(ProgramAlloc(self.name, self.datahash)) - super().__init__() - weakref.finalize(self, self._fini, self.dev, self.name, self.datahash) - - @staticmethod - def _fini(dev:RemoteDevice, name:str, datahash:str): dev.q(ProgramFree(name, datahash)) - - def __call__(self, *bufs, global_size=None, local_size=None, vals:tuple[int, ...]=(), wait=False): - ret = self.dev.q(ProgramExec(self.name, self.datahash, bufs, vals, global_size, local_size, wait), wait=wait) - if wait: return float(ret) - -@functools.cache -class RemoteConnection: - def __init__(self, host:str): - if DEBUG >= 1: print(f"remote with host {host}") - while 1: - try: - self.conn = http.client.HTTPConnection(host, timeout=getenv("REMOTE_TIMEOUT", 300.0)) - self.conn.connect() - break - except Exception as e: - print(e) - time.sleep(0.1) - self.req: BatchRequest = BatchRequest() - - def batch_submit(self): - data = self.req.serialize() - with Timing(f"*** send {len(self.req._q):-3d} requests {len(self.req._h):-3d} hashes with len {len(data)/1024:.2f} kB in ", enabled=DEBUG>=3): - self.conn.request("POST", "/batch", data) - response = self.conn.getresponse() - assert response.status == 200, f"POST /batch failed: {response}" - ret = response.read() - self.req = BatchRequest() - return ret - -class RemoteDevice(Compiled): - def __init__(self, device:str): - self.conn: RemoteConnection = RemoteConnection(getenv("HOST", "") or RemoteDevice.local_server()) - - # state for the connection - self.session = (binascii.hexlify(os.urandom(0x10)).decode(), int(device.split(":")[1]) if ":" in device else 0) - self.buffer_num: Iterator[int] = itertools.count(0) - self.graph_num: Iterator[int] = itertools.count(0) - - self.properties: RemoteProperties = safe_eval(ast.parse(self.q(GetProperties(), wait=True), mode="eval").body) - if DEBUG >= 1: print(f"remote has device {self.properties.real_device}") - # TODO: how to we have BEAM be cached on the backend? this should just send a specification of the compute. rethink what goes in Renderer - renderer = self.properties.renderer - if not renderer[0].startswith("tinygrad.renderer.") or not renderer[1].endswith("Renderer"): raise RuntimeError(f"bad renderer {renderer}") - renderer_class = fromimport(renderer[0], renderer[1]) # TODO: is this secure? - if not issubclass(renderer_class, Renderer): raise RuntimeError(f"renderer isn't a Renderer {renderer}") - renderer_instance = renderer_class(*renderer[2]) - renderer_instance.device = device - graph_supported, graph_multi = self.properties.graph_supported, self.properties.graph_supports_multi - graph = fromimport('tinygrad.runtime.graph.remote', f"Remote{'Multi' if graph_multi else ''}Graph") if graph_supported else None - super().__init__(device, RemoteAllocator(self), renderer_instance, Compiler(), functools.partial(RemoteProgram, self), graph) - - def finalize(self): - with contextlib.suppress(ConnectionError, http.client.HTTPException): self.q(SessionFree(), wait=True) - - def q(self, x:RemoteRequest, wait:bool=False): - self.conn.req.q(replace(x, session=self.session)) - if wait: return self.conn.batch_submit() - - @functools.cache - @staticmethod - def local_server(): - multiprocessing.Process(target=remote_server, args=(6667,), name="MainProcess", daemon=True).start() - return "127.0.0.1:6667" - -if __name__ == "__main__": remote_server(getenv("PORT", 6667)) diff --git a/tinygrad/tinygrad/runtime/ops_webgpu.py b/tinygrad/tinygrad/runtime/ops_webgpu.py deleted file mode 100644 index 1386c963..00000000 --- a/tinygrad/tinygrad/runtime/ops_webgpu.py +++ /dev/null @@ -1,226 +0,0 @@ -import functools, struct -from tinygrad.device import Compiled, Allocator, Compiler, BufferSpec -from tinygrad.renderer.wgsl import WGSLRenderer -from tinygrad.helpers import round_up -from tinygrad.runtime.autogen import webgpu -from typing import List, Any, TypeAlias -import ctypes -import os - -WGPUDevPtr: TypeAlias = webgpu.WGPUDevice # type: ignore -WGPUBufPtr: TypeAlias = webgpu.WGPUBuffer # type: ignore - -backend_types = {v: k for k, v in webgpu.WGPUBackendType__enumvalues.items() } - -instance = webgpu.wgpuCreateInstance(webgpu.WGPUInstanceDescriptor(features = webgpu.WGPUInstanceFeatures(timedWaitAnyEnable = True))) - -def to_c_string(_str:str) -> ctypes.Array: return ctypes.create_string_buffer(_str.encode('utf-8')) - -def from_wgpu_str(string_view:webgpu.struct_WGPUStringView) -> str: return ctypes.string_at(string_view.data, string_view.length).decode("utf-8") - -def to_wgpu_str(_str:str) -> webgpu.struct_WGPUStringView: - return webgpu.WGPUStringView(data=ctypes.cast(ctypes.pointer(to_c_string(_str)), ctypes.POINTER(ctypes.c_char)), length=len(_str)) - -def _wait(future:webgpu.struct_WGPUFuture): - assert webgpu.wgpuInstanceWaitAny(instance, 1, webgpu.WGPUFutureWaitInfo(future=future), 2**64-1) == webgpu.WGPUWaitStatus_Success, "Future failed" - -def write_buffer(device:WGPUDevPtr, buf:WGPUBufPtr, offset:int, src:memoryview|bytearray|bytes): - src = bytearray(src) - webgpu.wgpuQueueWriteBuffer(webgpu.wgpuDeviceGetQueue(device), buf, offset, (ctypes.c_uint8 * len(src)).from_buffer(src), len(src)) - -def _run(async_fun, cb_info_type, cb_type, status_enum, res_idx:int|None, msg_idx:int|None, *params): - result: List[Any] = [] - - def cb(*params): - result[:] = params - if msg_idx: result[msg_idx] = from_wgpu_str(result[msg_idx]) - - cb_info = cb_info_type(nextInChain=None, mode=webgpu.WGPUCallbackMode_WaitAnyOnly, callback=cb_type(cb)) - _wait(async_fun(*params, cb_info)) - - if result[0] != 1: raise RuntimeError(f"[{status_enum[result[0]] if status_enum else 'ERROR'}]{result[msg_idx] if msg_idx else ''}") - return result[res_idx] if res_idx else None - -def copy_buffer_to_buffer(dev:WGPUDevPtr, src:WGPUBufPtr, src_offset:int, dst:WGPUBufPtr, dst_offset:int, size:int): - encoder = webgpu.wgpuDeviceCreateCommandEncoder(dev, webgpu.WGPUCommandEncoderDescriptor()) - webgpu.wgpuCommandEncoderCopyBufferToBuffer(encoder, src, src_offset, dst, dst_offset, size) - cb = webgpu.wgpuCommandEncoderFinish(encoder, webgpu.WGPUCommandBufferDescriptor()) - webgpu.wgpuQueueSubmit(webgpu.wgpuDeviceGetQueue(dev), 1, (webgpu.WGPUCommandBuffer*1)(cb)) - webgpu.wgpuCommandBufferRelease(cb) - webgpu.wgpuCommandEncoderRelease(encoder) - -def read_buffer(dev:WGPUDevPtr, buf:WGPUBufPtr) -> memoryview: - size = webgpu.wgpuBufferGetSize(buf) - tmp_buffer = webgpu.wgpuDeviceCreateBuffer(dev, webgpu.WGPUBufferDescriptor(size=size, - usage=webgpu.WGPUBufferUsage_CopyDst | webgpu.WGPUBufferUsage_MapRead, mappedAtCreation=False)) - copy_buffer_to_buffer(dev, buf, 0, tmp_buffer, 0, size) - _run(webgpu.wgpuBufferMapAsync2, webgpu.WGPUBufferMapCallbackInfo2, webgpu.WGPUBufferMapCallback2, webgpu.WGPUBufferMapAsyncStatus__enumvalues, - None, 0, tmp_buffer, webgpu.WGPUMapMode_Read, 0, size) - void_ptr = ctypes.cast(webgpu.wgpuBufferGetConstMappedRange(tmp_buffer, 0, size), ctypes.c_void_p) - buf_copy = bytearray((ctypes.c_uint8 * size).from_address(void_ptr.value)) - webgpu.wgpuBufferUnmap(tmp_buffer) - webgpu.wgpuBufferDestroy(tmp_buffer) - return memoryview(buf_copy).cast("B") - -def pop_error(device:WGPUDevPtr) -> str: - return _run(webgpu.wgpuDevicePopErrorScopeF, webgpu.WGPUPopErrorScopeCallbackInfo, webgpu.WGPUPopErrorScopeCallback, None, 2, 2, device) - -def create_uniform(wgpu_device:WGPUDevPtr, val:int|float) -> WGPUBufPtr: - buf = webgpu.wgpuDeviceCreateBuffer(wgpu_device, - webgpu.WGPUBufferDescriptor(size=4, usage=webgpu.WGPUBufferUsage_Uniform | webgpu.WGPUBufferUsage_CopyDst)) - write_buffer(wgpu_device, buf, 0, val.to_bytes(4, "little") if isinstance(val, int) else struct.pack(' float|None: - wait = wait and self.timestamp_supported - tmp_bufs = [*bufs] - buf_patch = False - - # WebGPU does not allow using the same buffer for input and output - for i in range(1, len(bufs)): - if ctypes.addressof(bufs[i]) == ctypes.addressof(bufs[0]): - tmp_bufs[0] = webgpu.wgpuDeviceCreateBuffer(self.dev, - webgpu.WGPUBufferDescriptor(size=webgpu.wgpuBufferGetSize(bufs[0]), usage=webgpu.wgpuBufferGetUsage(bufs[0]))) - buf_patch = True - - # Creating bind group layout - binding_layouts = [webgpu.WGPUBindGroupLayoutEntry(binding=0, visibility= webgpu.WGPUShaderStage_Compute, - buffer=webgpu.WGPUBufferBindingLayout(type=webgpu.WGPUBufferBindingType_Uniform))] - binding_layouts += [webgpu.WGPUBindGroupLayoutEntry(binding=i+1, visibility=webgpu.WGPUShaderStage_Compute, - buffer=webgpu.WGPUBufferBindingLayout(type=webgpu.WGPUBufferBindingType_Uniform if i >= len(tmp_bufs) - else webgpu.WGPUBufferBindingType_Storage)) for i in range(len(tmp_bufs)+len(vals))] - - bl_arr_type = webgpu.WGPUBindGroupLayoutEntry * len(binding_layouts) - webgpu.wgpuDevicePushErrorScope(self.dev, webgpu.WGPUErrorFilter_Validation) - bind_group_layouts = [webgpu.wgpuDeviceCreateBindGroupLayout(self.dev, webgpu.WGPUBindGroupLayoutDescriptor( - entryCount=len(binding_layouts), entries=ctypes.cast(bl_arr_type(*binding_layouts), ctypes.POINTER(webgpu.WGPUBindGroupLayoutEntry))))] - - if bg_layout_err := pop_error(self.dev): raise RuntimeError(f"Error creating bind group layout: {bg_layout_err}") - - # Creating pipeline layout - pipeline_layout_desc = webgpu.WGPUPipelineLayoutDescriptor(bindGroupLayoutCount=len(bind_group_layouts), - bindGroupLayouts = (webgpu.WGPUBindGroupLayout * len(bind_group_layouts))(*bind_group_layouts)) - - webgpu.wgpuDevicePushErrorScope(self.dev, webgpu.WGPUErrorFilter_Validation) - pipeline_layout = webgpu.wgpuDeviceCreatePipelineLayout(self.dev, pipeline_layout_desc) - - if pipe_err := pop_error(self.dev): raise RuntimeError(f"Error creating pipeline layout: {pipe_err}") - - # Creating bind group - bindings = [webgpu.WGPUBindGroupEntry(binding=0, buffer=create_uniform(self.dev, float('inf')), offset=0, size=4)] - bindings += [webgpu.WGPUBindGroupEntry(binding=i+1, buffer=create_uniform(self.dev, x) if i >= len(tmp_bufs) else x, offset=0, - size=4 if i >= len(tmp_bufs) else webgpu.wgpuBufferGetSize(x)) for i,x in enumerate(tuple(tmp_bufs)+vals)] - - bg_arr_type = webgpu.WGPUBindGroupEntry * len(bindings) - bind_group_desc = webgpu.WGPUBindGroupDescriptor(layout=bind_group_layouts[0], entryCount=len(bindings), entries=bg_arr_type(*bindings)) - webgpu.wgpuDevicePushErrorScope(self.dev, webgpu.WGPUErrorFilter_Validation) - bind_group = webgpu.wgpuDeviceCreateBindGroup(self.dev, bind_group_desc) - - if bind_err := pop_error(self.dev): raise RuntimeError(f"Error creating bind group: {bind_err}") - - # Creating compute pipeline - compute_desc = webgpu.WGPUComputePipelineDescriptor(layout=pipeline_layout, - compute=webgpu.WGPUComputeState(module=self.prg, entryPoint=to_wgpu_str(self.name))) - pipeline_result = _run(webgpu.wgpuDeviceCreateComputePipelineAsync2, webgpu.WGPUCreateComputePipelineAsyncCallbackInfo2, - webgpu.WGPUCreateComputePipelineAsyncCallback2, webgpu.WGPUCreatePipelineAsyncStatus__enumvalues, 1, None, self.dev, compute_desc) - - command_encoder = webgpu.wgpuDeviceCreateCommandEncoder(self.dev, webgpu.WGPUCommandEncoderDescriptor()) - comp_pass_desc = webgpu.WGPUComputePassDescriptor(nextInChain=None) - - if wait: - query_set = webgpu.wgpuDeviceCreateQuerySet(self.dev, webgpu.WGPUQuerySetDescriptor(type=webgpu.WGPUQueryType_Timestamp, count=2)) - query_buf = webgpu.wgpuDeviceCreateBuffer(self.dev, - webgpu.WGPUBufferDescriptor(size=16, usage=webgpu.WGPUBufferUsage_QueryResolve | webgpu.WGPUBufferUsage_CopySrc)) - comp_pass_desc.timestampWrites = ctypes.pointer(webgpu.WGPUComputePassTimestampWrites( - querySet=query_set, beginningOfPassWriteIndex=0, endOfPassWriteIndex=1)) - - # Begin compute pass - compute_pass = webgpu.wgpuCommandEncoderBeginComputePass(command_encoder, comp_pass_desc) - webgpu.wgpuComputePassEncoderSetPipeline(compute_pass, pipeline_result) - webgpu.wgpuComputePassEncoderSetBindGroup(compute_pass, 0, bind_group, 0, None) - webgpu.wgpuComputePassEncoderDispatchWorkgroups(compute_pass, *global_size) - webgpu.wgpuComputePassEncoderEnd(compute_pass) - - if wait: webgpu.wgpuCommandEncoderResolveQuerySet(command_encoder, query_set, 0, 2, query_buf, 0) - - cmd_buf = webgpu.wgpuCommandEncoderFinish(command_encoder, webgpu.WGPUCommandBufferDescriptor()) - webgpu.wgpuQueueSubmit(webgpu.wgpuDeviceGetQueue(self.dev), 1, (webgpu.WGPUCommandBuffer*1)(cmd_buf)) - - if buf_patch: - copy_buffer_to_buffer(self.dev, tmp_bufs[0], 0, bufs[0], 0, webgpu.wgpuBufferGetSize(bufs[0])) - webgpu.wgpuBufferDestroy(tmp_bufs[0]) - - if wait: - time = ((timestamps:=read_buffer(self.dev, query_buf).cast("Q").tolist())[1] - timestamps[0]) / 1e9 - webgpu.wgpuBufferDestroy(query_buf) - webgpu.wgpuQuerySetDestroy(query_set) - return time - return None - -class WebGpuAllocator(Allocator['WGPUDevPtr']): - def _alloc(self, size:int, options:BufferSpec) -> WGPUBufPtr: - # WebGPU buffers have to be 4-byte aligned - return webgpu.wgpuDeviceCreateBuffer(self.dev, webgpu.WGPUBufferDescriptor(size=round_up(size, 4), - usage=webgpu.WGPUBufferUsage_Storage | webgpu.WGPUBufferUsage_CopyDst | webgpu.WGPUBufferUsage_CopySrc)) - def _copyin(self, dest:WGPUBufPtr, src:memoryview): - if src.nbytes % 4: - padded_src = bytearray(round_up(src.nbytes, 4)) - padded_src[:src.nbytes] = src - write_buffer(self.dev, dest, 0, padded_src if src.nbytes % 4 else src) - def _copyout(self, dest:memoryview, src:WGPUBufPtr): - buffer_data = read_buffer(self.dev, src) - dest[:] = buffer_data[:dest.nbytes] if webgpu.wgpuBufferGetSize(src) > dest.nbytes else buffer_data - def _free(self, opaque:WGPUBufPtr, options:BufferSpec): - try: webgpu.wgpuBufferDestroy(opaque) - except AttributeError: pass - -class WebGpuDevice(Compiled): - def __init__(self, device:str): - # Requesting an adapter - adapter_res = _run(webgpu.wgpuInstanceRequestAdapterF, webgpu.WGPURequestAdapterCallbackInfo, webgpu.WGPURequestAdapterCallback, - webgpu.WGPURequestAdapterStatus__enumvalues, 1, 2, instance, - - webgpu.WGPURequestAdapterOptions(powerPreference=webgpu.WGPUPowerPreference_HighPerformance, - backendType=backend_types.get(os.getenv("WEBGPU_BACKEND", ""), 0))) - - # Get supported features - supported_features = webgpu.WGPUSupportedFeatures() - webgpu.wgpuAdapterGetFeatures(adapter_res, supported_features) - supported = [supported_features.features[i] for i in range(supported_features.featureCount)] - features = [feat for feat in [webgpu.WGPUFeatureName_TimestampQuery, webgpu.WGPUFeatureName_ShaderF16] if feat in supported] - dev_desc = webgpu.WGPUDeviceDescriptor(requiredFeatureCount=len(features),requiredFeatures=(webgpu.WGPUFeatureName * len(features))(*features)) - - # Limits - supported_limits = webgpu.WGPUSupportedLimits() - webgpu.wgpuAdapterGetLimits(adapter_res, ctypes.cast(ctypes.pointer(supported_limits),ctypes.POINTER(webgpu.struct_WGPUSupportedLimits))) - limits = webgpu.WGPURequiredLimits(limits=supported_limits.limits) - dev_desc.requiredLimits = ctypes.cast(ctypes.pointer(limits),ctypes.POINTER(webgpu.struct_WGPURequiredLimits)) - - # Requesting a device - device_res = _run(webgpu.wgpuAdapterRequestDeviceF, webgpu.WGPURequestDeviceCallbackInfo, webgpu.WGPURequestDeviceCallback, - webgpu.WGPURequestDeviceStatus__enumvalues, 1, 2, adapter_res, dev_desc) - - super().__init__(device, WebGpuAllocator(device_res), WGSLRenderer(), Compiler(), - functools.partial(WebGPUProgram, (device_res, webgpu.WGPUFeatureName_TimestampQuery in supported))) - - def synchronize(self): - _run(webgpu.wgpuQueueOnSubmittedWorkDone2, webgpu.WGPUQueueWorkDoneCallbackInfo2, webgpu.WGPUQueueWorkDoneCallback2, - webgpu.WGPUQueueWorkDoneStatus__enumvalues, None, None, webgpu.wgpuDeviceGetQueue(self.runtime.args[0][0])) diff --git a/tinygrad/tinygrad/runtime/support/__init__.py b/tinygrad/tinygrad/runtime/support/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/runtime/support/allocator.py b/tinygrad/tinygrad/runtime/support/allocator.py deleted file mode 100644 index 12c97572..00000000 --- a/tinygrad/tinygrad/runtime/support/allocator.py +++ /dev/null @@ -1,97 +0,0 @@ -import collections, functools -from tinygrad.helpers import round_up - -class TLSFAllocator: - """ - The allocator is based on the Two-Level Segregated Fit (TLSF) algorithm. The allocator maintains 2 level of buckets: - * 1st level is determined by the most significant bit of the size. - * 2nd level splits the covered memory of 1st level into @lv2_cnt entries. - - For each allocation request, the allocator searches for the smallest block that can fit the requested size. - For each deallocation request, the allocator merges the block with its neighbors if they are free. - """ - - def __init__(self, size:int, base:int=0, block_size:int=16, lv2_cnt:int=16): - self.size, self.base, self.block_size, self.l2_cnt = size, base, block_size, lv2_cnt.bit_length() - self.storage:list = [collections.defaultdict(list) for _ in range(size.bit_length() + 1)] - self.lv1_entries:list[int] = [0] * len(self.storage) - - # self.blocks is more like a linked list, where each entry is a contigous block. - self.blocks:dict[int, tuple[int, int|None, int|None, bool]] = {0: (size, None, None, True)} # size, next, prev, is_free - self._insert_block(0, size) - - @functools.cache - def lv1(self, size): return size.bit_length() - - @functools.cache - def lv2(self, size): return (size - (1 << (size.bit_length() - 1))) // (1 << max(0, size.bit_length() - self.l2_cnt)) - - def _insert_block(self, start:int, size:int, prev:int|None=None): - if prev is None: prev = self.blocks[start][2] - self.storage[self.lv1(size)][self.lv2(size)].append(start) - self.lv1_entries[self.lv1(size)] += 1 - self.blocks[start] = (size, start + size, prev, True) - return self - - def _remove_block(self, start:int, size:int, prev:int|None=None): - if prev is None: prev = self.blocks[start][2] - self.storage[self.lv1(size)][self.lv2(size)].remove(start) - self.lv1_entries[self.lv1(size)] -= 1 - self.blocks[start] = (size, start + size, prev, False) - return self - - def _split_block(self, start:int, size:int, new_size:int): - nxt = self.blocks[start][1] - assert self.blocks[start][3], "block must be free" - self._remove_block(start, size)._insert_block(start, new_size)._insert_block(start + new_size, size - new_size, prev=start) - if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start + new_size, self.blocks[nxt][3]) - return self - - def _merge_right(self, start:int): - size, nxt, _, is_free = self.blocks[start] - assert is_free, "block must be free" - - while is_free and nxt in self.blocks: - if (blk:=self.blocks[nxt])[3] is False: break - self._remove_block(start, size)._remove_block(nxt, blk[0])._insert_block(start, size:=size + blk[0]) - assert self.blocks[start][1] == blk[1] - _, nxt, _, _ = self.blocks.pop(nxt) - - if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start, self.blocks[nxt][3]) - - def _merge_block(self, start:int): - # Go left while blocks are free. Then merge all them right. - while (x:=self.blocks[start][2]) is not None and self.blocks[x][3] is True: start = x - self._merge_right(start) - - def alloc(self, req_size:int, align:int=1) -> int: - req_size = max(self.block_size, req_size) # at least block size. - size = max(self.block_size, req_size + align - 1) - - # Round up the allocation size to the next bucket, so any entry there can fit the requested size. - size = round_up(size, (1 << size.bit_length() - self.l2_cnt)) - - # Search for the smallest block that can fit the requested size. Start with the it's bucket and go up until any block is found. - for l1 in range(self.lv1(size), len(self.storage)): - if self.lv1_entries[l1] == 0: continue - for l2 in range(self.lv2(size) if l1 == size.bit_length() else 0, (1 << self.l2_cnt)): - if len(self.storage[l1][l2]) > 0: - nsize = self.blocks[self.storage[l1][l2][0]][0] - assert nsize >= size, "block must be larger" - - # Block start address. - start = self.storage[l1][l2][0] - - # If request contains alignment, split the block into two parts. - if (new_start:=round_up(start, align)) != start: - self._split_block(start, nsize, new_start - start) - start, nsize = new_start, self.blocks[new_start][0] - - # If the block is larger than the requested size, split it into two parts. - if nsize > req_size: self._split_block(start, nsize, req_size) - self._remove_block(start, req_size) # Mark the block as allocated. - return start + self.base - raise MemoryError(f"Can't allocate {req_size} bytes") - - def free(self, start:int): - self._insert_block(start - self.base, self.blocks[start - self.base][0])._merge_block(start - self.base) diff --git a/tinygrad/tinygrad/runtime/support/am/__init__.py b/tinygrad/tinygrad/runtime/support/am/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/runtime/support/am/amdev.py b/tinygrad/tinygrad/runtime/support/am/amdev.py deleted file mode 100644 index 22e88c0b..00000000 --- a/tinygrad/tinygrad/runtime/support/am/amdev.py +++ /dev/null @@ -1,392 +0,0 @@ -from __future__ import annotations -import ctypes, collections, time, dataclasses, functools, fcntl, os, hashlib -from tinygrad.helpers import mv_address, getenv, round_up, DEBUG, temp, fetch -from tinygrad.runtime.autogen.am import am -from tinygrad.runtime.support.hcq import MMIOInterface -from tinygrad.runtime.support.amd import AMDReg, import_module, import_asic_regs -from tinygrad.runtime.support.allocator import TLSFAllocator -from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA - -AM_DEBUG = getenv("AM_DEBUG", 0) - -@dataclasses.dataclass(frozen=True) -class AMRegister(AMDReg): - adev:AMDev - - def read(self): return self.adev.rreg(self.addr) - def read_bitfields(self) -> dict[str, int]: return self.decode(self.read()) - - def write(self, _am_val:int=0, **kwargs): self.adev.wreg(self.addr, _am_val | self.encode(**kwargs)) - - def update(self, **kwargs): self.write(self.read() & ~self.fields_mask(*kwargs.keys()), **kwargs) - -class AMFirmware: - def __init__(self, adev): - self.adev = adev - def fmt_ver(hwip): return '_'.join(map(str, adev.ip_ver[hwip])) - - # Load SOS firmware - self.sos_fw = {} - - blob, sos_hdr = self.load_fw(f"psp_{fmt_ver(am.MP0_HWIP)}_sos.bin", am.struct_psp_firmware_header_v2_0) - fw_bin = sos_hdr.psp_fw_bin - - for fw_i in range(sos_hdr.psp_fw_bin_count): - fw_bin_desc = am.struct_psp_fw_bin_desc.from_address(ctypes.addressof(fw_bin) + fw_i * ctypes.sizeof(am.struct_psp_fw_bin_desc)) - ucode_start_offset = fw_bin_desc.offset_bytes + sos_hdr.header.ucode_array_offset_bytes - self.sos_fw[fw_bin_desc.fw_type] = blob[ucode_start_offset:ucode_start_offset+fw_bin_desc.size_bytes] - - # Load other fw - self.ucode_start: dict[str, int] = {} - self.descs: list[tuple[list[int], memoryview]] = [] - - blob, hdr = self.load_fw(f"smu_{fmt_ver(am.MP1_HWIP)}.bin", am.struct_smc_firmware_header_v1_0) - self.smu_psp_desc = self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes, am.GFX_FW_TYPE_SMU) - - # SDMA firmware - blob, hdr, hdr_v3 = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", am.struct_sdma_firmware_header_v2_0, am.struct_sdma_firmware_header_v3_0) - if hdr.header.header_version_major < 3: - self.descs += [self.desc(blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH1)] - self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)] - else: self.descs += [self.desc(blob, hdr_v3.header.ucode_array_offset_bytes, hdr_v3.ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)] - - # PFP, ME, MEC firmware - for (fw_name, fw_cnt) in ([('PFP', 1), ('ME', 1)] if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else []) + [('MEC', 1)]: - blob, hdr = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_{fw_name.lower()}.bin", am.struct_gfx_firmware_header_v2_0) - - # Code part - self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes, getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}'))] - - # Stack - stack_fws = [getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}_P{fwnum}_STACK') for fwnum in range(fw_cnt)] - self.descs += [self.desc(blob, hdr.data_offset_bytes, hdr.data_size_bytes, *stack_fws)] - self.ucode_start[fw_name] = hdr.ucode_start_addr_lo | (hdr.ucode_start_addr_hi << 32) - - # IMU firmware - blob, hdr = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_imu.bin", am.struct_imu_firmware_header_v1_0) - imu_i_off, imu_i_sz, imu_d_sz = hdr.header.ucode_array_offset_bytes, hdr.imu_iram_ucode_size_bytes, hdr.imu_dram_ucode_size_bytes - self.descs += [self.desc(blob, imu_i_off, imu_i_sz, am.GFX_FW_TYPE_IMU_I), self.desc(blob, imu_i_off + imu_i_sz, imu_d_sz, am.GFX_FW_TYPE_IMU_D)] - - # RLC firmware - blob, hdr0, _hdr1, hdr2, hdr3 = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_rlc.bin", am.struct_rlc_firmware_header_v2_0, - am.struct_rlc_firmware_header_v2_1, am.struct_rlc_firmware_header_v2_2, am.struct_rlc_firmware_header_v2_3) - - for mem,fmem in [('IRAM', 'iram'), ('DRAM_BOOT', 'dram')]: - off, sz = getattr(hdr2, f'rlc_{fmem}_ucode_offset_bytes'), getattr(hdr2, f'rlc_{fmem}_ucode_size_bytes') - self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))] - - if hdr0.header.header_version_minor == 3: - for mem in ['P', 'V']: - off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes') - self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))] - - self.descs += [self.desc(blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes, am.GFX_FW_TYPE_RLC_G)] - - def load_fw(self, fname:str, *headers): - fpath = fetch(f"https://gitlab.com/kernel-firmware/linux-firmware/-/raw/45f59212aebd226c7630aff4b58598967c0c8c91/amdgpu/{fname}", subdir="fw") - blob = memoryview(bytearray(fpath.read_bytes())) - if AM_DEBUG >= 1: print(f"am {self.adev.devfmt}: loading firmware {fname}: {hashlib.sha256(blob).hexdigest()}") - return tuple([blob] + [hdr.from_address(mv_address(blob)) for hdr in headers]) - - def desc(self, blob:memoryview, offset:int, size:int, *types:int) -> tuple[list[int], memoryview]: return (list(types), blob[offset:offset+size]) - -@dataclasses.dataclass(frozen=True) -class AMMapping: va_addr:int; size:int; paddrs:list[tuple[int, int]]; uncached:bool=False; system:bool=False; snooped:bool=False # noqa: E702 - -class AMPageTableEntry: - def __init__(self, adev, paddr, lv): self.adev, self.paddr, self.lv, self.entries = adev, paddr, lv, adev.vram.view(paddr, 0x1000, fmt='Q') - - def set_entry(self, entry_id:int, paddr:int, table=False, uncached=False, system=False, snooped=False, frag=0, valid=True): - assert paddr & self.adev.gmc.address_space_mask == paddr, f"Invalid physical address {paddr:#x}" - self.entries[entry_id] = self.adev.gmc.get_pte_flags(self.lv, table, frag, uncached, system, snooped, valid) | (paddr & 0x0000FFFFFFFFF000) - -class AMPageTableTraverseContext: - def __init__(self, adev, pt, vaddr, create_pts=False, free_pts=False, boot=False): - self.adev, self.vaddr, self.create_pts, self.free_pts, self.boot = adev, vaddr - adev.gmc.vm_base, create_pts, free_pts, boot - self.pt_stack:list[tuple[AMPageTableEntry, int, int]] = [(pt, self._pt_pte_idx(pt, vaddr), self._pt_pte_size(pt))] - - def _pt_pte_size(self, pt): return (1 << ((9 * (3-pt.lv)) + 12)) - def _pt_pte_idx(self, pt, va): return (va // self._pt_pte_size(pt)) % 512 - - def level_down(self): - pt, pte_idx, _ = self.pt_stack[-1] - if (entry:=pt.entries[pte_idx]) & am.AMDGPU_PTE_VALID == 0: - assert self.create_pts, "Not allowed to create new page table" - pt.set_entry(pte_idx, self.adev.mm.palloc(0x1000, zero=True, boot=self.boot), table=True, valid=True) - entry = pt.entries[pte_idx] - - assert not self.adev.gmc.is_pte_huge_page(entry), f"Must be table pt={pt.paddr:#x}, {pte_idx=} {entry=:#x}" - child_page_table = AMPageTableEntry(self.adev, entry & 0x0000FFFFFFFFF000, lv=pt.lv+1) - - self.pt_stack.append((child_page_table, self._pt_pte_idx(child_page_table, self.vaddr), self._pt_pte_size(child_page_table))) - return self.pt_stack[-1] - - def _try_free_pt(self) -> bool: - pt, _, _ = self.pt_stack[-1] - if self.free_pts and pt != self.adev.mm.root_page_table and all(pt.entries[i] & am.AMDGPU_PTE_VALID == 0 for i in range(512)): - self.adev.mm.pfree(pt.paddr) - parent_pt, parent_pte_idx, _ = self.pt_stack[-2] - parent_pt.set_entry(parent_pte_idx, 0x0, valid=False) - return True - return False - - def level_up(self): - while self._try_free_pt() or self.pt_stack[-1][1] == 512: - _, pt_cnt, _ = self.pt_stack.pop() - if pt_cnt == 512: self.pt_stack[-1] = (self.pt_stack[-1][0], self.pt_stack[-1][1] + 1, self.pt_stack[-1][2]) - - def next(self, size:int, off=0): - while size > 0: - pt, pte_idx, pte_covers = self.pt_stack[-1] - if self.create_pts: - while pte_covers > size: pt, pte_idx, pte_covers = self.level_down() - else: - while pt.lv!=am.AMDGPU_VM_PTB and not self.adev.gmc.is_pte_huge_page(pt.entries[pte_idx]): pt, pte_idx, pte_covers = self.level_down() - - entries = min(size // pte_covers, 512 - pte_idx) - assert entries > 0, "Invalid entries" - yield off, pt, pte_idx, entries, pte_covers - - size, off, self.vaddr = size - entries * pte_covers, off + entries * pte_covers, self.vaddr + entries * pte_covers - self.pt_stack[-1] = (pt, pte_idx + entries, pte_covers) - self.level_up() - -class AMMemoryManager: - va_allocator = TLSFAllocator(512 * (1 << 30), base=0x200000000000) # global for all devices. - - def __init__(self, adev:AMDev, vram_size:int): - self.adev, self.vram_size = adev, vram_size - self.boot_allocator = TLSFAllocator(32 << 20, base=0) # per device - self.pa_allocator = TLSFAllocator(vram_size - (64 << 20), base=self.boot_allocator.size) # per device - self.root_page_table = AMPageTableEntry(self.adev, self.palloc(0x1000, zero=not self.adev.smi_dev, boot=True), lv=am.AMDGPU_VM_PDB1) - - def _frag_size(self, va, sz, must_cover=True): - """ - Calculate the tlb fragment size for a given virtual address and size. - If must_cover is True, the fragment size must cover the size, otherwise the biggest fragment size that fits the size is returned. - Fragment 0 is 4KB, 1 is 8KB and so on. - """ - va_pwr2_div, sz_pwr2_div, sz_pwr2_max = va & -(va) if va > 0 else (1 << 63), sz & -(sz), (1 << (sz.bit_length() - 1)) - return (min(va_pwr2_div, sz_pwr2_div) if must_cover else min(va_pwr2_div, sz_pwr2_max)).bit_length() - 1 - 12 - - def map_range(self, vaddr:int, size:int, paddrs:list[tuple[int, int]], uncached=False, system=False, snooped=False, boot=False) -> AMMapping: - if AM_DEBUG >= 2: print(f"am {self.adev.devfmt}: mapping {vaddr=:#x} ({size=:#x})") - - assert size == sum(p[1] for p in paddrs), f"Size mismatch {size=} {sum(p[1] for p in paddrs)=}" - - ctx = AMPageTableTraverseContext(self.adev, self.root_page_table, vaddr, create_pts=True, boot=boot) - for paddr, psize in paddrs: - for off, pt, pte_idx, pte_cnt, pte_covers in ctx.next(psize): - for pte_off in range(pte_cnt): - assert pt.entries[pte_idx + pte_off] & am.AMDGPU_PTE_VALID == 0, f"PTE already mapped: {pt.entries[pte_idx + pte_off]:#x}" - pt.set_entry(pte_idx + pte_off, paddr + off + pte_off * pte_covers, uncached=uncached, system=system, snooped=snooped, - frag=self._frag_size(ctx.vaddr+off, pte_cnt * pte_covers), valid=True) - - # Invalidate TLB after mappings. - self.adev.gmc.flush_tlb(ip='GC', vmid=0) - self.adev.gmc.flush_tlb(ip='MM', vmid=0) - return AMMapping(vaddr, size, paddrs, uncached=uncached, system=system, snooped=snooped) - - def unmap_range(self, vaddr:int, size:int): - if AM_DEBUG >= 2: print(f"am {self.adev.devfmt}: unmapping {vaddr=:#x} ({size=:#x})") - - ctx = AMPageTableTraverseContext(self.adev, self.root_page_table, vaddr, free_pts=True) - for off, pt, pte_idx, pte_cnt, pte_covers in ctx.next(size): - for pte_id in range(pte_idx, pte_idx + pte_cnt): - assert pt.entries[pte_id] & am.AMDGPU_PTE_VALID == am.AMDGPU_PTE_VALID, f"PTE not mapped: {pt.entries[pte_id]:#x}" - pt.set_entry(pte_id, paddr=0x0, valid=False) - - @staticmethod - def alloc_vaddr(size:int, align=0x1000) -> int: return AMMemoryManager.va_allocator.alloc(size, max((1 << (size.bit_length() - 1)), align)) - - def valloc(self, size:int, align=0x1000, uncached=False, contigous=False) -> AMMapping: - # Alloc physical memory and map it to the virtual address - va = self.alloc_vaddr(size:=round_up(size, 0x1000), align) - - if contigous: paddrs = [(self.palloc(size, zero=True), size)] - else: - # Traverse the PT to find the largest contiguous sizes we need to allocate. Try to allocate the longest segment to reduce TLB pressure. - paddrs = [] - ctx = AMPageTableTraverseContext(self.adev, self.root_page_table, va, create_pts=True) - for off, _, _, seg_cnt, seg_size in ctx.next(size): - rem_len = seg_cnt * seg_size - while rem_len > 0: - # Try to allocate as long segment (power of 2) as possible - cont_seg_sz, paddr = 1 << (self._frag_size(ctx.vaddr+off, rem_len) + 12), None - while cont_seg_sz >= 0x1000: - try: paddr = self.palloc(cont_seg_sz, zero=False) - except MemoryError: cont_seg_sz //= 2 - else: break - - if paddr is not None: paddrs += [(paddr, cont_seg_sz)] - else: - for paddr, _ in paddrs: self.pa_allocator.free(paddr) - raise MemoryError(f"Failed to allocate a contiguous page. (allocation size={size:#x})") - rem_len, off = rem_len - cont_seg_sz, off + cont_seg_sz - - return self.map_range(va, size, paddrs, uncached=uncached) - - def vfree(self, vm:AMMapping): - self.unmap_range(vm.va_addr, vm.size) - self.va_allocator.free(vm.va_addr) - for paddr, _ in vm.paddrs: self.pa_allocator.free(paddr) - - def palloc(self, size:int, align:int=0x1000, zero=True, boot=False) -> int: - assert self.adev.is_booting == boot, "During booting, only boot memory can be allocated" - paddr = (self.boot_allocator if boot else self.pa_allocator).alloc(round_up(size, 0x1000), align) - if zero: self.adev.vram[paddr:paddr+size] = bytes(size) - return paddr - - def pfree(self, paddr:int): self.pa_allocator.free(paddr) - -class AMDev: - def __init__(self, devfmt, vram:MMIOInterface, doorbell:MMIOInterface, mmio:MMIOInterface, dma_regions:list[tuple[int, MMIOInterface]]|None=None): - self.devfmt, self.vram, self.doorbell64, self.mmio, self.dma_regions = devfmt, vram, doorbell, mmio, dma_regions - - os.umask(0) # Set umask to 0 to allow creating files with 0666 permissions - - # Avoid O_CREAT because we don’t want to re-create/replace an existing file (triggers extra perms checks) when opening as non-owner. - if os.path.exists(lock_name:=temp(f"am_{self.devfmt}.lock")): self.lock_fd = os.open(lock_name, os.O_RDWR) - else: self.lock_fd = os.open(lock_name, os.O_RDWR | os.O_CREAT | os.O_CLOEXEC, 0o666) - - try: fcntl.flock(self.lock_fd, fcntl.LOCK_EX | fcntl.LOCK_NB) - except OSError: raise RuntimeError(f"Failed to open AM device {self.devfmt}. It's already in use.") - - self._run_discovery() - self._build_regs() - - # AM boot Process: - # The GPU being passed can be in one of several states: 1. Not initialized. 2. Initialized by amdgpu. 3. Initialized by AM. - # The 1st and 2nd states require a full GPU setup since their states are unknown. The 2nd state also requires a mode1 reset to - # reinitialize all components. - # - # The 3rd state can be set up partially to optimize boot time. In this case, only the GFX and SDMA IPs need to be initialized. - # To enable this, AM uses a separate boot memory that is guaranteed not to be overwritten. This physical memory is utilized for - # all blocks that are initialized only during the initial AM boot. - # To determine if the GPU is in the third state, AM uses regSCRATCH_REG7 as a flag. - self.is_booting, self.smi_dev = True, False # During boot only boot memory can be allocated. This flag is to validate this. - self.partial_boot = (self.reg("regSCRATCH_REG7").read() == (am_version:=0xA0000005)) and (getenv("AM_RESET", 0) != 1) - - # Memory manager & firmware - self.mm = AMMemoryManager(self, self.vram_size) - self.fw = AMFirmware(self) - - # Initialize IP blocks - self.soc:AM_SOC = AM_SOC(self) - self.gmc:AM_GMC = AM_GMC(self) - self.ih:AM_IH = AM_IH(self) - self.psp:AM_PSP = AM_PSP(self) - self.smu:AM_SMU = AM_SMU(self) - self.gfx:AM_GFX = AM_GFX(self) - self.sdma:AM_SDMA = AM_SDMA(self) - - # Init sw for all IP blocks - for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init_sw() - - if self.partial_boot and (self.reg("regGCVM_CONTEXT0_CNTL").read() != 0 or self.reg(self.gmc.pf_status_reg("GC")).read() != 0): - if DEBUG >= 2: print(f"am {self.devfmt}: Malformed state. Issuing a full reset.") - self.partial_boot = False - - # Init hw for IP blocks where it is needed - if not self.partial_boot: - if self.psp.is_sos_alive() and self.smu.is_smu_alive(): self.smu.mode1_reset() - for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu]: - ip.init_hw() - if DEBUG >= 2: print(f"am {self.devfmt}: {ip.__class__.__name__} initialized") - - # Booting done - self.is_booting = False - - # Re-initialize main blocks - for ip in [self.gfx, self.sdma]: - ip.init_hw() - if DEBUG >= 2: print(f"am {self.devfmt}: {ip.__class__.__name__} initialized") - - self.smu.set_clocks(level=-1) # last level, max perf. - for ip in [self.soc, self.gfx]: ip.set_clockgating_state() - self.reg("regSCRATCH_REG7").write(am_version) - if DEBUG >= 2: print(f"am {self.devfmt}: boot done") - - def fini(self): - if DEBUG >= 2: print(f"am {self.devfmt}: Finalizing") - for ip in [self.sdma, self.gfx]: ip.fini_hw() - self.smu.set_clocks(level=0) - self.ih.interrupt_handler() - os.close(self.lock_fd) - - def paddr2mc(self, paddr:int) -> int: return self.gmc.mc_base + paddr - - def reg(self, reg:str) -> AMRegister: return self.__dict__[reg] - - def rreg(self, reg:int) -> int: - val = self.indirect_rreg(reg * 4) if reg > len(self.mmio) else self.mmio[reg] - if AM_DEBUG >= 4 and getattr(self, '_prev_rreg', None) != (reg, val): print(f"am {self.devfmt}: Reading register {reg:#x} with value {val:#x}") - self._prev_rreg = (reg, val) - return val - - def wreg(self, reg:int, val:int): - if AM_DEBUG >= 4: print(f"am {self.devfmt}: Writing register {reg:#x} with value {val:#x}") - if reg > len(self.mmio): self.indirect_wreg(reg * 4, val) - else: self.mmio[reg] = val - - def wreg_pair(self, reg_base:str, lo_suffix:str, hi_suffix:str, val:int): - self.reg(f"{reg_base}{lo_suffix}").write(val & 0xffffffff) - self.reg(f"{reg_base}{hi_suffix}").write(val >> 32) - - def indirect_rreg(self, reg:int) -> int: - self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg) - return self.reg("regBIF_BX_PF0_RSMU_DATA").read() - - def indirect_wreg(self, reg:int, val:int): - self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg) - self.reg("regBIF_BX_PF0_RSMU_DATA").write(val) - - def wait_reg(self, reg:AMRegister, value:int, mask=0xffffffff, timeout=10000) -> int: - start_time = int(time.perf_counter() * 1000) - while int(time.perf_counter() * 1000) - start_time < timeout: - if ((rval:=reg.read()) & mask) == value: return rval - raise RuntimeError(f'wait_reg timeout reg=0x{reg.addr:X} mask=0x{mask:X} value=0x{value:X} last_val=0x{rval}') - - def _run_discovery(self): - # NOTE: Fixed register to query memory size without known ip bases to find the discovery table. - # The table is located at the end of VRAM - 64KB and is 10KB in size. - mmRCC_CONFIG_MEMSIZE = 0xde3 - self.vram_size = self.rreg(mmRCC_CONFIG_MEMSIZE) << 20 - tmr_offset, tmr_size = self.vram_size - (64 << 10), (10 << 10) - - self.bhdr = am.struct_binary_header.from_buffer(bytearray(self.vram.view(tmr_offset, tmr_size)[:])) - ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.IP_DISCOVERY].offset) - assert ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE and not ihdr.base_addr_64_bit, f"0x{ihdr.signature:X} != 0x{am.DISCOVERY_TABLE_SIGNATURE:X}" - - # Mapping of HW IP to Discovery HW IP - hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map} - self.regs_offset:dict[int, dict[int, tuple]] = collections.defaultdict(dict) - self.ip_ver:dict[int, tuple[int, int, int]] = {} - - for num_die in range(ihdr.num_dies): - dhdr = am.struct_die_header.from_address(ctypes.addressof(self.bhdr) + ihdr.die_info[num_die].die_offset) - - ip_offset = ctypes.addressof(self.bhdr) + ctypes.sizeof(dhdr) + ihdr.die_info[num_die].die_offset - for _ in range(dhdr.num_ips): - ip = am.struct_ip_v4.from_address(ip_offset) - ba = (ctypes.c_uint32 * ip.num_base_address).from_address(ip_offset + 8) - for hw_ip in range(1, am.MAX_HWIP): - if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id: - self.regs_offset[hw_ip][ip.instance_number] = tuple(list(ba)) - self.ip_ver[hw_ip] = (ip.major, ip.minor, ip.revision) - - ip_offset += 8 + (8 if ihdr.base_addr_64_bit else 4) * ip.num_base_address - - gc_info = am.struct_gc_info_v1_0.from_address(gc_addr:=ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.GC].offset) - self.gc_info = getattr(am, f"struct_gc_info_v{gc_info.header.version_major}_{gc_info.header.version_minor}").from_address(gc_addr) - - def _ip_module(self, prefix:str, hwip, prever_prefix:str=""): return import_module(prefix, self.ip_ver[hwip], prever_prefix) - - def _build_regs(self): - mods = [("mp", am.MP0_HWIP), ("hdp", am.HDP_HWIP), ("gc", am.GC_HWIP), ("mmhub", am.MMHUB_HWIP), ("osssys", am.OSSSYS_HWIP), - ("nbio" if self.ip_ver[am.GC_HWIP] < (12,0,0) else "nbif", am.NBIO_HWIP)] - - for prefix, hwip in mods: - self.__dict__.update(import_asic_regs(prefix, self.ip_ver[hwip], cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[hwip][0]))) - self.__dict__.update(import_asic_regs('mp', (11, 0), cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[am.MP1_HWIP][0]))) - diff --git a/tinygrad/tinygrad/runtime/support/am/ip.py b/tinygrad/tinygrad/runtime/support/am/ip.py deleted file mode 100644 index 59cc734c..00000000 --- a/tinygrad/tinygrad/runtime/support/am/ip.py +++ /dev/null @@ -1,503 +0,0 @@ -import ctypes, time, contextlib, importlib, functools -from typing import Literal -from tinygrad.runtime.autogen.am import am -from tinygrad.helpers import to_mv, data64, lo32, hi32, DEBUG - -class AM_IP: - def __init__(self, adev): self.adev = adev - def init_sw(self): pass # Prepare sw/allocations for this IP - def init_hw(self): pass # Initialize hw for this IP - def fini_hw(self): pass # Finalize hw for this IP - def set_clockgating_state(self): pass # Set clockgating state for this IP - -class AM_SOC(AM_IP): - def init_sw(self): - self.soc_ver = 24 if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else 21 - self.module = importlib.import_module(f"tinygrad.runtime.autogen.am.soc{self.soc_ver}") - - def init_hw(self): - self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0) - self.adev.regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN.write(0x1) - def set_clockgating_state(self): self.adev.regHDP_MEM_POWER_CTRL.update(atomic_mem_power_ctrl_en=1, atomic_mem_power_ds_en=1) - - def doorbell_enable(self, port, awid=0, awaddr_31_28_value=0, offset=0, size=0): - self.adev.reg(f"{'regGDC_S2A0_S2A' if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else 'regS2A'}_DOORBELL_ENTRY_{port}_CTRL").update( - **{f"s2a_doorbell_port{port}_enable":1, f"s2a_doorbell_port{port}_awid":awid, f"s2a_doorbell_port{port}_awaddr_31_28_value":awaddr_31_28_value, - f"s2a_doorbell_port{port}_range_offset":offset, f"s2a_doorbell_port{port}_range_size":size}) - -class AM_GMC(AM_IP): - def init_sw(self): - # Memory controller aperture - self.mc_base = (self.adev.regMMMC_VM_FB_LOCATION_BASE.read() & 0xFFFFFF) << 24 - self.mc_end = self.mc_base + self.adev.mm.vram_size - 1 - - # VM aperture - self.vm_base = self.adev.mm.va_allocator.base - self.vm_end = self.vm_base + self.adev.mm.va_allocator.size - 1 - - # GFX11/GFX12 has 44-bit address space - self.address_space_mask = (1 << 44) - 1 - - self.memscratch_paddr = self.adev.mm.palloc(0x1000, zero=False, boot=True) - self.dummy_page_paddr = self.adev.mm.palloc(0x1000, zero=False, boot=True) - self.hub_initted = {"MM": False, "GC": False} - - self.pf_status_reg = lambda ip: f"reg{ip}VM_L2_PROTECTION_FAULT_STATUS{'_LO32' if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else ''}" - - def init_hw(self): self.init_hub("MM") - - def flush_hdp(self): self.adev.wreg(self.adev.reg("regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL").read() // 4, 0x0) - def flush_tlb(self, ip:Literal["MM", "GC"], vmid, flush_type=0): - self.flush_hdp() - - # Can't issue TLB invalidation if the hub isn't initialized. - if not self.hub_initted[ip]: return - - if ip == "MM": self.adev.wait_reg(self.adev.regMMVM_INVALIDATE_ENG17_SEM, mask=0x1, value=0x1) - - self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_REQ").write(flush_type=flush_type, per_vmid_invalidate_req=(1 << vmid), invalidate_l2_ptes=1, - invalidate_l2_pde0=1, invalidate_l2_pde1=1, invalidate_l2_pde2=1, invalidate_l1_ptes=1, clear_protection_fault_status_addr=0) - - self.adev.wait_reg(self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_ACK"), mask=(1 << vmid), value=(1 << vmid)) - - if ip == "MM": - self.adev.regMMVM_INVALIDATE_ENG17_SEM.write(0x0) - self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.update(reserved_cache_private_invalidation=1) - - # Read back the register to ensure the invalidation is complete - self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.read() - - def enable_vm_addressing(self, page_table, ip:Literal["MM", "GC"], vmid): - self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_START_ADDR", "_LO32", "_HI32", self.vm_base >> 12) - self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_END_ADDR", "_LO32", "_HI32", self.vm_end >> 12) - self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_BASE_ADDR", "_LO32", "_HI32", page_table.paddr | 1) - self.adev.reg(f"reg{ip}VM_CONTEXT{vmid}_CNTL").write(0x1800000, pde0_protection_fault_enable_interrupt=1, pde0_protection_fault_enable_default=1, - dummy_page_protection_fault_enable_interrupt=1, dummy_page_protection_fault_enable_default=1, - range_protection_fault_enable_interrupt=1, range_protection_fault_enable_default=1, - valid_protection_fault_enable_interrupt=1, valid_protection_fault_enable_default=1, - read_protection_fault_enable_interrupt=1, read_protection_fault_enable_default=1, - write_protection_fault_enable_interrupt=1, write_protection_fault_enable_default=1, - execute_protection_fault_enable_interrupt=1, execute_protection_fault_enable_default=1, - enable_context=1, page_table_depth=(3 - page_table.lv)) - - def init_hub(self, ip:Literal["MM", "GC"]): - # Init system apertures - self.adev.reg(f"reg{ip}MC_VM_AGP_BASE").write(0) - self.adev.reg(f"reg{ip}MC_VM_AGP_BOT").write(0xffffffffffff >> 24) # disable AGP - self.adev.reg(f"reg{ip}MC_VM_AGP_TOP").write(0) - - self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_LOW_ADDR").write(self.mc_base >> 18) - self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_HIGH_ADDR").write(self.mc_end >> 18) - self.adev.wreg_pair(f"reg{ip}MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", "_LSB", "_MSB", self.memscratch_paddr >> 12) - self.adev.wreg_pair(f"reg{ip}VM_L2_PROTECTION_FAULT_DEFAULT_ADDR", "_LO32", "_HI32", self.dummy_page_paddr >> 12) - - self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_CNTL2").update(active_page_migration_pte_read_retry=1) - - # Init TLB and cache - self.adev.reg(f"reg{ip}MC_VM_MX_L1_TLB_CNTL").update(enable_l1_tlb=1, system_access_mode=3, enable_advanced_driver_model=1, - system_aperture_unmapped_access=0, eco_bits=0, mtype=self.adev.soc.module.MTYPE_UC) - - self.adev.reg(f"reg{ip}VM_L2_CNTL").update(enable_l2_cache=1, enable_l2_fragment_processing=0, enable_default_page_out_to_system_memory=1, - l2_pde0_cache_tag_generation_mode=0, pde_fault_classification=0, context1_identity_access_mode=1, identity_mode_fragment_size=0) - self.adev.reg(f"reg{ip}VM_L2_CNTL2").update(invalidate_all_l1_tlbs=1, invalidate_l2_cache=1) - self.adev.reg(f"reg{ip}VM_L2_CNTL3").write(bank_select=9, l2_cache_bigk_fragment_size=6,l2_cache_4k_associativity=1,l2_cache_bigk_associativity=1) - self.adev.reg(f"reg{ip}VM_L2_CNTL4").write(l2_cache_4k_partition_count=1) - self.adev.reg(f"reg{ip}VM_L2_CNTL5").write(walker_priority_client_id=0x1ff) - - self.enable_vm_addressing(self.adev.mm.root_page_table, ip, vmid=0) - - # Disable identity aperture - self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", "_LO32", "_HI32", 0xfffffffff) - self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", "_LO32", "_HI32", 0x0) - self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", "_LO32", "_HI32", 0x0) - - for eng_i in range(18): self.adev.wreg_pair(f"reg{ip}VM_INVALIDATE_ENG{eng_i}_ADDR_RANGE", "_LO32", "_HI32", 0x1fffffffff) - self.hub_initted[ip] = True - - @functools.cache - def get_pte_flags(self, pte_lv, is_table, frag, uncached, system, snooped, valid, extra=0): - extra |= (am.AMDGPU_PTE_SYSTEM * system) | (am.AMDGPU_PTE_SNOOPED * snooped) | (am.AMDGPU_PTE_VALID * valid) | am.AMDGPU_PTE_FRAG(frag) - if not is_table: extra |= (am.AMDGPU_PTE_WRITEABLE | am.AMDGPU_PTE_READABLE | am.AMDGPU_PTE_EXECUTABLE) - if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0): - extra |= am.AMDGPU_PTE_MTYPE_GFX12(0, self.adev.soc.module.MTYPE_UC if uncached else 0) - extra |= (am.AMDGPU_PDE_PTE_GFX12 if not is_table and pte_lv != am.AMDGPU_VM_PTB else (am.AMDGPU_PTE_IS_PTE if not is_table else 0)) - else: - extra |= am.AMDGPU_PTE_MTYPE_NV10(0, self.adev.soc.module.MTYPE_UC if uncached else 0) - extra |= (am.AMDGPU_PDE_PTE if not is_table and pte_lv != am.AMDGPU_VM_PTB else 0) - return extra - def is_pte_huge_page(self, pte): return pte & (am.AMDGPU_PDE_PTE_GFX12 if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else am.AMDGPU_PDE_PTE) - - def on_interrupt(self): - for ip in ["MM", "GC"]: - va = (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_HI32').read()<<32) | self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_LO32').read() - if self.adev.reg(self.pf_status_reg(ip)).read(): - raise RuntimeError(f"{ip}VM_L2_PROTECTION_FAULT_STATUS: {self.adev.reg(self.pf_status_reg(ip)).read_bitfields()} {va<<12:#x}") - -class AM_SMU(AM_IP): - def init_sw(self): - self.smu_mod = self.adev._ip_module("smu", am.MP1_HWIP, prever_prefix='v') - self.driver_table_paddr = self.adev.mm.palloc(0x4000, zero=False, boot=True) - - def init_hw(self): - self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrHigh, hi32(self.adev.paddr2mc(self.driver_table_paddr))) - self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrLow, lo32(self.adev.paddr2mc(self.driver_table_paddr))) - self._send_msg(self.smu_mod.PPSMC_MSG_EnableAllSmuFeatures, 0) - - def is_smu_alive(self): - with contextlib.suppress(RuntimeError): self._send_msg(self.smu_mod.PPSMC_MSG_GetSmuVersion, 0, timeout=100) - return self.adev.mmMP1_SMN_C2PMSG_90.read() != 0 - - def mode1_reset(self): - if DEBUG >= 2: print(f"am {self.adev.devfmt}: mode1 reset") - if self.adev.ip_ver[am.MP0_HWIP] >= (14,0,0): self._send_msg(__DEBUGSMC_MSG_Mode1Reset:=2, 0, debug=True) - else: self._send_msg(self.smu_mod.PPSMC_MSG_Mode1Reset, 0) - time.sleep(0.5) # 500ms - - def read_table(self, table_t, cmd): - self._send_msg(self.smu_mod.PPSMC_MSG_TransferTableSmu2Dram, cmd) - return table_t.from_buffer(bytearray(self.adev.vram.view(self.driver_table_paddr, ctypes.sizeof(table_t))[:])) - def read_metrics(self): return self.read_table(self.smu_mod.SmuMetricsExternal_t, self.smu_mod.TABLE_SMU_METRICS) - - def set_clocks(self, level): - if not hasattr(self, 'clcks'): - self.clcks = {} - for clck in [self.smu_mod.PPCLK_GFXCLK, self.smu_mod.PPCLK_UCLK, self.smu_mod.PPCLK_FCLK, self.smu_mod.PPCLK_SOCCLK]: - cnt = self._send_msg(self.smu_mod.PPSMC_MSG_GetDpmFreqByIndex, (clck<<16)|0xff, read_back_arg=True)&0x7fffffff - self.clcks[clck] = [self._send_msg(self.smu_mod.PPSMC_MSG_GetDpmFreqByIndex, (clck<<16)|i, read_back_arg=True)&0x7fffffff for i in range(cnt)] - - for clck, vals in self.clcks.items(): - self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMinByFreq, clck << 16 | (vals[level])) - self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMaxByFreq, clck << 16 | (vals[level])) - - def _smu_cmn_send_msg(self, msg, param=0, debug=False): - (self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54).write(0) # resp reg - (self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).write(param) - (self.adev.mmMP1_SMN_C2PMSG_66 if not debug else self.adev.mmMP1_SMN_C2PMSG_75).write(msg) - - def _send_msg(self, msg, param, read_back_arg=False, timeout=10000, debug=False): # 10s - self._smu_cmn_send_msg(msg, param, debug=debug) - self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54, mask=0xFFFFFFFF, value=1, timeout=timeout) - return (self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).read() if read_back_arg else None - -class AM_GFX(AM_IP): - def init_hw(self): - # Wait for RLC autoload to complete - while self.adev.regCP_STAT.read() != 0 and self.adev.regRLC_RLCS_BOOTLOAD_STATUS.read_bitfields()['bootload_complete'] != 0: pass - - self._config_gfx_rs64() - self.adev.gmc.init_hub("GC") - - # NOTE: Golden reg for gfx11. No values for this reg provided. The kernel just ors 0x20000000 to this reg. - self.adev.regTCP_CNTL.write(self.adev.regTCP_CNTL.read() | 0x20000000) - - self.adev.regRLC_SRM_CNTL.update(srm_enable=1, auto_incr_addr=1) - - self.adev.soc.doorbell_enable(port=0, awid=0x3, awaddr_31_28_value=0x3) - self.adev.soc.doorbell_enable(port=3, awid=0x6, awaddr_31_28_value=0x3) - - self.adev.regGRBM_CNTL.update(read_timeout=0xff) - for i in range(0, 16): - self._grbm_select(vmid=i) - self.adev.regSH_MEM_CONFIG.write(address_mode=self.adev.soc.module.SH_MEM_ADDRESS_MODE_64, - alignment_mode=self.adev.soc.module.SH_MEM_ALIGNMENT_MODE_UNALIGNED, initial_inst_prefetch=3) - - # Configure apertures: - # LDS: 0x10000000'00000000 - 0x10000001'00000000 (4GB) - # Scratch: 0x20000000'00000000 - 0x20000001'00000000 (4GB) - self.adev.regSH_MEM_BASES.write(shared_base=0x1, private_base=0x2) - self._grbm_select() - - # Configure MEC doorbell range - self.adev.regCP_MEC_DOORBELL_RANGE_LOWER.write(0x0) - self.adev.regCP_MEC_DOORBELL_RANGE_UPPER.write(0x450) - - # Enable MEC - self.adev.regCP_MEC_RS64_CNTL.update(mec_invalidate_icache=0, mec_pipe0_reset=0, mec_pipe0_active=1, mec_halt=0) - - # NOTE: Wait for MEC to be ready. The kernel does udelay here as well. - time.sleep(0.05) - - def fini_hw(self): - self._grbm_select(me=1, pipe=0, queue=0) - self.adev.regCP_HQD_DEQUEUE_REQUEST.write(0x2) # 1 - DRAIN_PIPE; 2 - RESET_WAVES - self.adev.regSPI_COMPUTE_QUEUE_RESET.write(1) - self._grbm_select() - self.adev.regGCVM_CONTEXT0_CNTL.write(0) - - def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int): - mqd = self.adev.mm.valloc(0x1000, uncached=True, contigous=True) - - struct_t = getattr(am, f"struct_v{self.adev.ip_ver[am.GC_HWIP][0]}_compute_mqd") - mqd_struct = struct_t(header=0xC0310800, cp_mqd_base_addr_lo=lo32(mqd.va_addr), cp_mqd_base_addr_hi=hi32(mqd.va_addr), - cp_hqd_persistent_state=self.adev.regCP_HQD_PERSISTENT_STATE.encode(preload_size=0x55, preload_req=1), - cp_hqd_pipe_priority=0x2, cp_hqd_queue_priority=0xf, cp_hqd_quantum=0x111, - cp_hqd_pq_base_lo=lo32(ring_addr>>8), cp_hqd_pq_base_hi=hi32(ring_addr>>8), - cp_hqd_pq_rptr_report_addr_lo=lo32(rptr_addr), cp_hqd_pq_rptr_report_addr_hi=hi32(rptr_addr), - cp_hqd_pq_wptr_poll_addr_lo=lo32(wptr_addr), cp_hqd_pq_wptr_poll_addr_hi=hi32(wptr_addr), - cp_hqd_pq_doorbell_control=self.adev.regCP_HQD_PQ_DOORBELL_CONTROL.encode(doorbell_offset=doorbell*2, doorbell_en=1), - cp_hqd_pq_control=self.adev.regCP_HQD_PQ_CONTROL.encode(rptr_block_size=5, unord_dispatch=0, queue_size=(ring_size//4).bit_length()-2), - cp_hqd_ib_control=self.adev.regCP_HQD_IB_CONTROL.encode(min_ib_avail_size=0x3), cp_hqd_hq_status0=0x20004000, - cp_mqd_control=self.adev.regCP_MQD_CONTROL.encode(priv_state=1), cp_hqd_vmid=0, - cp_hqd_eop_base_addr_lo=lo32(eop_addr>>8), cp_hqd_eop_base_addr_hi=hi32(eop_addr>>8), - cp_hqd_eop_control=self.adev.regCP_HQD_EOP_CONTROL.encode(eop_size=(eop_size//4).bit_length()-2)) - - # Copy mqd into memory - self.adev.vram.view(mqd.paddrs[0][0], ctypes.sizeof(mqd_struct))[:] = memoryview(mqd_struct).cast('B') - self.adev.gmc.flush_hdp() - - self._grbm_select(me=1, pipe=pipe, queue=queue) - - mqd_st_mv = to_mv(ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct)).cast('I') - for i, reg in enumerate(range(self.adev.regCP_MQD_BASE_ADDR.addr, self.adev.regCP_HQD_PQ_WPTR_HI.addr + 1)): - self.adev.wreg(reg, mqd_st_mv[0x80 + i]) - self.adev.regCP_HQD_ACTIVE.write(0x1) - - self._grbm_select() - - self.adev.reg(f"regCP_ME1_PIPE{pipe}_INT_CNTL").update(time_stamp_int_enable=1, generic0_int_enable=1) - - def set_clockgating_state(self): - if hasattr(self.adev, 'regMM_ATC_L2_MISC_CG'): self.adev.regMM_ATC_L2_MISC_CG.write(enable=1, mem_ls_enable=1) - - self.adev.regRLC_SAFE_MODE.write(message=1, cmd=1) - self.adev.wait_reg(self.adev.regRLC_SAFE_MODE, mask=0x1, value=0x0) - - self.adev.regRLC_CGCG_CGLS_CTRL.update(cgcg_gfx_idle_threshold=0x36, cgcg_en=1, cgls_rep_compansat_delay=0xf, cgls_en=1) - - self.adev.regCP_RB_WPTR_POLL_CNTL.update(poll_frequency=0x100, idle_poll_count=0x90) - self.adev.regCP_INT_CNTL.update(cntx_busy_int_enable=1, cntx_empty_int_enable=1, cmp_busy_int_enable=1, gfx_idle_int_enable=1) - self.adev.regSDMA0_RLC_CGCG_CTRL.update(cgcg_int_enable=1) - self.adev.regSDMA1_RLC_CGCG_CTRL.update(cgcg_int_enable=1) - - self.adev.regRLC_CGTT_MGCG_OVERRIDE.update(perfmon_clock_state=0, gfxip_fgcg_override=0, gfxip_repeater_fgcg_override=0, - grbm_cgtt_sclk_override=0, rlc_cgtt_sclk_override=0, gfxip_mgcg_override=0, gfxip_cgls_override=0, gfxip_cgcg_override=0) - - self.adev.regRLC_SAFE_MODE.write(message=0, cmd=1) - - def _grbm_select(self, me=0, pipe=0, queue=0, vmid=0): self.adev.regGRBM_GFX_CNTL.write(meid=me, pipeid=pipe, vmid=vmid, queueid=queue) - - def _config_gfx_rs64(self): - def _config_helper(eng_name, cntl_reg, eng_reg, pipe_cnt, me=0): - for pipe in range(pipe_cnt): - self._grbm_select(me=me, pipe=pipe) - self.adev.wreg_pair(f"regCP_{eng_reg}_PRGRM_CNTR_START", "", "_HI", self.adev.fw.ucode_start[eng_name] >> 2) - self._grbm_select() - self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 1 for pipe in range(pipe_cnt)}) - self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 0 for pipe in range(pipe_cnt)}) - - if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0): - _config_helper(eng_name="PFP", cntl_reg="ME", eng_reg="PFP", pipe_cnt=1) - _config_helper(eng_name="ME", cntl_reg="ME", eng_reg="ME", pipe_cnt=1) - _config_helper(eng_name="MEC", cntl_reg="MEC_RS64", eng_reg="MEC_RS64", pipe_cnt=1, me=1) - -class AM_IH(AM_IP): - def init_sw(self): - self.ring_size = 512 << 10 - def _alloc_ring(size): return (self.adev.mm.palloc(size, zero=False, boot=True), self.adev.mm.palloc(0x1000, zero=False, boot=True)) - self.rings = [(*_alloc_ring(self.ring_size), "", 0), (*_alloc_ring(self.ring_size), "_RING1", 1)] - - def init_hw(self): - for ring_vm, rwptr_vm, suf, ring_id in self.rings: - self.adev.wreg_pair("regIH_RB_BASE", suf, f"_HI{suf}", self.adev.paddr2mc(ring_vm) >> 8) - - self.adev.reg(f"regIH_RB_CNTL{suf}").write(mc_space=4, wptr_overflow_clear=1, rb_size=(self.ring_size//4).bit_length(), - mc_snoop=1, mc_ro=0, mc_vmid=0, **({'wptr_overflow_enable': 1, 'rptr_rearm': 1} if ring_id == 0 else {'rb_full_drain_enable': 1})) - - if ring_id == 0: self.adev.wreg_pair("regIH_RB_WPTR_ADDR", "_LO", "_HI", self.adev.paddr2mc(rwptr_vm)) - - self.adev.reg(f"regIH_RB_WPTR{suf}").write(0) - self.adev.reg(f"regIH_RB_RPTR{suf}").write(0) - - self.adev.reg(f"regIH_DOORBELL_RPTR{suf}").write(offset=(am.AMDGPU_NAVI10_DOORBELL_IH + ring_id) * 2, enable=1) - - self.adev.regIH_STORM_CLIENT_LIST_CNTL.update(client18_is_storm_client=1) - self.adev.regIH_INT_FLOOD_CNTL.update(flood_cntl_enable=1) - self.adev.regIH_MSI_STORM_CTRL.update(delay=3) - - # toggle interrupts - for _, rwptr_vm, suf, ring_id in self.rings: - self.adev.reg(f"regIH_RB_CNTL{suf}").update(rb_enable=1, **({'enable_intr': 1} if ring_id == 0 else {})) - - self.adev.soc.doorbell_enable(port=1, awid=0x0, awaddr_31_28_value=0x0, offset=am.AMDGPU_NAVI10_DOORBELL_IH*2, size=2) - - def interrupt_handler(self): - _, rwptr_vm, suf, _ = self.rings[0] - wptr = self.adev.vram.view(offset=rwptr_vm, size=8, fmt='Q')[0] - - if self.adev.reg(f"regIH_RB_WPTR{suf}").read_bitfields()['rb_overflow']: - self.adev.reg(f"regIH_RB_WPTR{suf}").update(rb_overflow=0) - self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=1) - self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=0) - self.adev.regIH_RB_RPTR.write(wptr % self.ring_size) - -class AM_SDMA(AM_IP): - def init_sw(self): self.sdma_name = "F32" if self.adev.ip_ver[am.SDMA0_HWIP] < (7,0,0) else "MCU" - def init_hw(self): - for pipe in range(2): - self.adev.reg(f"regSDMA{pipe}_WATCHDOG_CNTL").update(queue_hang_count=100) # 10s, 100ms per unit - self.adev.reg(f"regSDMA{pipe}_UTCL1_CNTL").update(resp_mode=3, redo_delay=9) - - # rd=noa, wr=bypass - self.adev.reg(f"regSDMA{pipe}_UTCL1_PAGE").update(rd_l2_policy=0x2, wr_l2_policy=0x3, **({'llc_noalloc':1} if self.sdma_name == "F32" else {})) - self.adev.reg(f"regSDMA{pipe}_{self.sdma_name}_CNTL").update(halt=0, **{f"{'th1_' if self.sdma_name == 'F32' else ''}reset":0}) - self.adev.reg(f"regSDMA{pipe}_CNTL").update(ctxempty_int_enable=1, trap_enable=1) - self.adev.soc.doorbell_enable(port=2, awid=0xe, awaddr_31_28_value=0x3, offset=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0*2, size=4) - - def fini_hw(self): - self.adev.regSDMA0_QUEUE0_RB_CNTL.update(rb_enable=0) - self.adev.regSDMA0_QUEUE0_IB_CNTL.update(ib_enable=0) - self.adev.regGRBM_SOFT_RESET.write(soft_reset_sdma0=1) - time.sleep(0.01) - self.adev.regGRBM_SOFT_RESET.write(0x0) - - def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, doorbell:int, pipe:int, queue:int): - # Setup the ring - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_MINOR_PTR_UPDATE").write(0x1) - self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR", "", "_HI", 0) - self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR", "", "_HI", 0) - self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_BASE", "", "_HI", ring_addr >> 8) - self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR_ADDR", "_LO", "_HI", rptr_addr) - self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR_POLL_ADDR", "_LO", "_HI", wptr_addr) - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL_OFFSET").update(offset=doorbell * 2) - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL").update(enable=1) - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_MINOR_PTR_UPDATE").write(0x0) - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").write(rb_vmid=0, rptr_writeback_enable=1, rptr_writeback_timer=4, - **{f'{self.sdma_name.lower()}_wptr_poll_enable':1}, rb_size=(ring_size//4).bit_length()-1, rb_enable=1, rb_priv=1) - self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_IB_CNTL").update(ib_enable=1) - -class AM_PSP(AM_IP): - def init_sw(self): - self.reg_pref = "regMP0_SMN_C2PMSG" if self.adev.ip_ver[am.MP0_HWIP] < (14,0,0) else "regMPASP_SMN_C2PMSG" - - msg1_region = next((reg for reg in self.adev.dma_regions or [] if reg[1].nbytes >= (512 << 10)), None) - if msg1_region is not None: - self.msg1_addr, self.msg1_view = self.adev.mm.alloc_vaddr(size=msg1_region[1].nbytes, align=am.PSP_1_MEG), msg1_region[1] - self.adev.mm.map_range(self.msg1_addr, msg1_region[1].nbytes, [(msg1_region[0], msg1_region[1].nbytes)], system=True, uncached=True, boot=True) - else: - self.msg1_paddr = self.adev.mm.palloc(am.PSP_1_MEG, align=am.PSP_1_MEG, zero=False, boot=True) - self.msg1_addr, self.msg1_view = self.adev.paddr2mc(self.msg1_paddr), self.adev.vram.view(self.msg1_paddr, am.PSP_1_MEG, 'B') - - self.cmd_paddr = self.adev.mm.palloc(am.PSP_CMD_BUFFER_SIZE, zero=False, boot=True) - self.fence_paddr = self.adev.mm.palloc(am.PSP_FENCE_BUFFER_SIZE, zero=True, boot=True) - - self.ring_size = 0x10000 - self.ring_paddr = self.adev.mm.palloc(self.ring_size, zero=False, boot=True) - - self.max_tmr_size = 0x1300000 - self.boot_time_tmr = self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) - if not self.boot_time_tmr: - self.tmr_paddr = self.adev.mm.palloc(self.max_tmr_size, align=am.PSP_TMR_ALIGNMENT, zero=False, boot=True) - - def init_hw(self): - spl_key = am.PSP_FW_TYPE_PSP_SPL if self.adev.ip_ver[am.MP0_HWIP] >= (14,0,0) else am.PSP_FW_TYPE_PSP_KDB - sos_components = [(am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_KEY_DATABASE), (spl_key, am.PSP_BL__LOAD_TOS_SPL_TABLE), - (am.PSP_FW_TYPE_PSP_SYS_DRV, am.PSP_BL__LOAD_SYSDRV), (am.PSP_FW_TYPE_PSP_SOC_DRV, am.PSP_BL__LOAD_SOCDRV), - (am.PSP_FW_TYPE_PSP_INTF_DRV, am.PSP_BL__LOAD_INTFDRV), (am.PSP_FW_TYPE_PSP_DBG_DRV, am.PSP_BL__LOAD_DBGDRV), - (am.PSP_FW_TYPE_PSP_RAS_DRV, am.PSP_BL__LOAD_RASDRV), (am.PSP_FW_TYPE_PSP_SOS, am.PSP_BL__LOAD_SOSDRV)] - - if not self.is_sos_alive(): - for fw, compid in sos_components: self._bootloader_load_component(fw, compid) - while not self.is_sos_alive(): time.sleep(0.01) - - self._ring_create() - self._tmr_init() - - # SMU fw should be loaded before TMR. - self._load_ip_fw_cmd(*self.adev.fw.smu_psp_desc) - if not self.boot_time_tmr: self._tmr_load_cmd() - - for psp_desc in self.adev.fw.descs: self._load_ip_fw_cmd(*psp_desc) - self._rlc_autoload_cmd() - - def is_sos_alive(self): return self.adev.reg(f"{self.reg_pref}_81").read() != 0x0 - - def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_35"), mask=0x80000000, value=0x80000000) - - def _prep_msg1(self, data): - assert len(data) <= self.msg1_view.nbytes, f"msg1 buffer is too small {len(data):#x} > {self.msg1_view.nbytes:#x}" - self.msg1_view[:len(data)+4] = bytes(data) + b'\x00' * 4 - self.adev.gmc.flush_hdp() - - def _bootloader_load_component(self, fw, compid): - if fw not in self.adev.fw.sos_fw: return 0 - - self._wait_for_bootloader() - - if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading sos component: {am.psp_fw_type__enumvalues[fw]}") - - self._prep_msg1(self.adev.fw.sos_fw[fw]) - self.adev.reg(f"{self.reg_pref}_36").write(self.msg1_addr >> 20) - self.adev.reg(f"{self.reg_pref}_35").write(compid) - - return self._wait_for_bootloader() if compid != am.PSP_BL__LOAD_SOSDRV else 0 - - def _tmr_init(self): - # Load TOC and calculate TMR size - self._prep_msg1(fwm:=self.adev.fw.sos_fw[am.PSP_FW_TYPE_PSP_TOC]) - self.tmr_size = self._load_toc_cmd(len(fwm)).resp.tmr_size - assert self.tmr_size <= self.max_tmr_size - - def _ring_create(self): - # If the ring is already created, destroy it - if self.adev.reg(f"{self.reg_pref}_71").read() != 0: - self.adev.reg(f"{self.reg_pref}_64").write(am.GFX_CTRL_CMD_ID_DESTROY_RINGS) - - # There might be handshake issue with hardware which needs delay - time.sleep(0.02) - - # Wait until the sOS is ready - self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x80000000, value=0x80000000) - - self.adev.wreg_pair(self.reg_pref, "_69", "_70", self.adev.paddr2mc(self.ring_paddr)) - self.adev.reg(f"{self.reg_pref}_71").write(self.ring_size) - self.adev.reg(f"{self.reg_pref}_64").write(am.PSP_RING_TYPE__KM << 16) - - # There might be handshake issue with hardware which needs delay - time.sleep(0.02) - - self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x8000FFFF, value=0x80000000) - - def _ring_submit(self, cmd): - msg = am.struct_psp_gfx_rb_frame(fence_value=(prev_wptr:=self.adev.reg(f"{self.reg_pref}_67").read()), - cmd_buf_addr_lo=lo32(self.adev.paddr2mc(self.cmd_paddr)), cmd_buf_addr_hi=hi32(self.adev.paddr2mc(self.cmd_paddr)), - fence_addr_lo=lo32(self.adev.paddr2mc(self.fence_paddr)), fence_addr_hi=hi32(self.adev.paddr2mc(self.fence_paddr))) - - self.adev.vram.view(self.cmd_paddr, ctypes.sizeof(cmd))[:] = memoryview(cmd).cast('B') - self.adev.vram.view(self.ring_paddr + prev_wptr * 4, ctypes.sizeof(msg))[:] = memoryview(msg).cast('B') - - # Move the wptr - self.adev.reg(f"{self.reg_pref}_67").write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4) - - while self.adev.vram.view(self.fence_paddr, 4, 'I')[0] != prev_wptr: pass - time.sleep(0.005) - - resp = type(cmd).from_buffer(bytearray(self.adev.vram.view(self.cmd_paddr, ctypes.sizeof(cmd))[:])) - if resp.resp.status != 0: raise RuntimeError(f"PSP command failed {resp.cmd_id} {resp.resp.status}") - - return resp - - def _load_ip_fw_cmd(self, fw_types, fw_bytes): - self._prep_msg1(fw_bytes) - for fw_type in fw_types: - if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading fw: {am.psp_gfx_fw_type__enumvalues[fw_type]}") - cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_LOAD_IP_FW) - cmd.cmd.cmd_load_ip_fw.fw_phy_addr_hi, cmd.cmd.cmd_load_ip_fw.fw_phy_addr_lo = data64(self.msg1_addr) - cmd.cmd.cmd_load_ip_fw.fw_size = len(fw_bytes) - cmd.cmd.cmd_load_ip_fw.fw_type = fw_type - self._ring_submit(cmd) - - def _tmr_load_cmd(self): - cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_SETUP_TMR) - cmd.cmd.cmd_setup_tmr.buf_phy_addr_hi, cmd.cmd.cmd_setup_tmr.buf_phy_addr_lo = data64(self.adev.paddr2mc(self.tmr_paddr)) - cmd.cmd.cmd_setup_tmr.system_phy_addr_hi, cmd.cmd.cmd_setup_tmr.system_phy_addr_lo = data64(self.tmr_paddr) - cmd.cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1 - cmd.cmd.cmd_setup_tmr.buf_size = self.tmr_size - return self._ring_submit(cmd) - - def _load_toc_cmd(self, toc_size): - cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_LOAD_TOC) - cmd.cmd.cmd_load_toc.toc_phy_addr_hi, cmd.cmd.cmd_load_toc.toc_phy_addr_lo = data64(self.msg1_addr) - cmd.cmd.cmd_load_toc.toc_size = toc_size - return self._ring_submit(cmd) - - def _rlc_autoload_cmd(self): return self._ring_submit(am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_AUTOLOAD_RLC)) diff --git a/tinygrad/tinygrad/runtime/support/amd.py b/tinygrad/tinygrad/runtime/support/amd.py deleted file mode 100644 index 8177418e..00000000 --- a/tinygrad/tinygrad/runtime/support/amd.py +++ /dev/null @@ -1,130 +0,0 @@ -import functools, importlib, re, urllib -from collections import defaultdict -from dataclasses import dataclass -from tinygrad.helpers import getbits, round_up, fetch -from tinygrad.runtime.autogen import pci -from tinygrad.runtime.support.usb import ASM24Controller - -@dataclass(frozen=True) -class AMDReg: - name:str; offset:int; segment:int; fields:dict[str, tuple[int, int]]; bases:tuple[int, ...] # noqa: E702 - - def encode(self, **kwargs) -> int: return functools.reduce(int.__or__, (value << self.fields[name][0] for name,value in kwargs.items()), 0) - def decode(self, val: int) -> dict: return {name:getbits(val, start, end) for name,(start,end) in self.fields.items()} - - def fields_mask(self, *names) -> int: - return functools.reduce(int.__or__, ((((1 << (self.fields[nm][1]-self.fields[nm][0]+1)) - 1) << self.fields[nm][0]) for nm in names), 0) - - @property - def addr(self): return self.bases[self.segment] + self.offset - -@dataclass -class AMDIP: - name:str; version:tuple[int, ...]; bases:tuple[int, ...] # noqa: E702 - def __post_init__(self): self.version = fixup_ip_version(self.name, self.version)[0] - - @functools.cached_property - def regs(self): return import_asic_regs(self.name, self.version, cls=functools.partial(AMDReg, bases=self.bases)) - - def __getattr__(self, name:str): - if name in self.regs: return self.regs[name] - - # NOTE: gfx10 gc registers always start with mm, no reg prefix - return self.regs[name.replace('reg', 'mm')] - -def fixup_ip_version(ip:str, version:tuple[int, ...]) -> list[tuple[int, ...]]: - # override versions - def _apply_ovrd(ovrd:dict[tuple[int, ...], tuple[int, ...]]) -> tuple[int, ...]: - for ver, ovrd_ver in ovrd.items(): - if version[:len(ver)] == ver: return ovrd_ver - return version - - if ip in ['nbio', 'nbif']: version = _apply_ovrd({(3,3): (2,3,0)}) - elif ip == 'mp': version = _apply_ovrd({(14,0,3): (14,0,2)}) - - return [version, version[:2], version[:2]+(0,), version[:1]+(0, 0)] - -def import_module(name:str, version:tuple[int, ...], version_prefix:str=""): - for ver in fixup_ip_version(name, version): - try: return importlib.import_module(f"tinygrad.runtime.autogen.am.{name}_{version_prefix}{'_'.join(map(str, ver))}") - except ImportError: pass - raise ImportError(f"Failed to load autogen module for {name.upper()} {'.'.join(map(str, version))}") - -def import_asic_regs(prefix:str, version:tuple[int, ...], cls=AMDReg) -> dict[str, AMDReg]: - def _split_name(name): return name[:(pos:=next((i for i,c in enumerate(name) if c.isupper()), len(name)))], name[pos:] - def _extract_regs(txt): - return {m.group(1): int(m.group(2), 0) for line in txt.splitlines() if (m:=re.match(r'#define\s+(\S+)\s+(0x[\da-fA-F]+|\d+)', line))} - def _download_file(ver, suff) -> str: - dir_prefix = {"osssys": "oss"}.get(prefix, prefix) - fetch_name, file_name = f"{prefix}_{'_'.join(map(str, ver))}_{suff}.h", f"{prefix}_{'_'.join(map(str, version))}_{suff}.h" - url = "https://gitlab.com/linux-kernel/linux-next/-/raw/cf6d949a409e09539477d32dbe7c954e4852e744/drivers/gpu/drm/amd/include/asic_reg" - return fetch(f"{url}/{dir_prefix}/{fetch_name}", name=file_name, subdir="asic_regs").read_text() - - for ver in fixup_ip_version(prefix, version): - try: offs, sh_masks = _extract_regs(_download_file(ver, "offset")), _extract_regs(_download_file(ver, "sh_mask")) - except urllib.error.HTTPError as e: - if e.code == 404: continue - raise - - offsets = {k:v for k,v in offs.items() if _split_name(k)[0] in {'reg', 'mm'} and not k.endswith('_BASE_IDX')} - bases = {k[:-len('_BASE_IDX')]:v for k,v in offs.items() if _split_name(k)[0] in {'reg', 'mm'} and k.endswith('_BASE_IDX')} - - fields: defaultdict[str, dict[str, tuple[int, int]]] = defaultdict(dict) - for field_name, field_mask in sh_masks.items(): - if not ('__' in field_name and field_name.endswith('_MASK')): continue - reg_name, reg_field_name = field_name[:-len('_MASK')].split('__') - fields[reg_name][reg_field_name.lower()] = ((field_mask & -field_mask).bit_length()-1, field_mask.bit_length()-1) - - # NOTE: Some registers like regGFX_IMU_FUSESTRAP in gc_11_0_0 are missing base idx, just skip them - return {reg:cls(name=reg, offset=off, segment=bases[reg], fields=fields[_split_name(reg)[1]]) for reg,off in offsets.items() if reg in bases} - raise ImportError(f"Failed to load ASIC registers for {prefix.upper()} {'.'.join(map(str, version))}") - -def setup_pci_bars(usb:ASM24Controller, gpu_bus:int, mem_base:int, pref_mem_base:int) -> dict[int, tuple[int, int]]: - for bus in range(gpu_bus): - # All 3 values must be written at the same time. - buses = (0 << 0) | ((bus+1) << 8) | ((gpu_bus) << 16) - usb.pcie_cfg_req(pci.PCI_PRIMARY_BUS, bus=bus, dev=0, fn=0, value=buses, size=4) - - usb.pcie_cfg_req(pci.PCI_MEMORY_BASE, bus=bus, dev=0, fn=0, value=(mem_base>>16) & 0xffff, size=2) - usb.pcie_cfg_req(pci.PCI_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0xffff, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_BASE, bus=bus, dev=0, fn=0, value=(pref_mem_base>>16) & 0xffff, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_MEMORY_LIMIT, bus=bus, dev=0, fn=0, value=0xffff, size=2) - usb.pcie_cfg_req(pci.PCI_PREF_BASE_UPPER32, bus=bus, dev=0, fn=0, value=pref_mem_base >> 32, size=4) - usb.pcie_cfg_req(pci.PCI_PREF_LIMIT_UPPER32, bus=bus, dev=0, fn=0, value=0xffffffff, size=4) - - usb.pcie_cfg_req(pci.PCI_COMMAND, bus=bus, dev=0, fn=0, value=pci.PCI_COMMAND_IO | pci.PCI_COMMAND_MEMORY | pci.PCI_COMMAND_MASTER, size=1) - - # resize bar 0 - cap_ptr = 0x100 - while cap_ptr: - if pci.PCI_EXT_CAP_ID(hdr:=usb.pcie_cfg_req(cap_ptr, bus=gpu_bus, dev=0, fn=0, size=4)) == pci.PCI_EXT_CAP_ID_REBAR: - cap = usb.pcie_cfg_req(cap_ptr + 0x04, bus=gpu_bus, dev=0, fn=0, size=4) - new_ctrl = (usb.pcie_cfg_req(cap_ptr + 0x08, bus=gpu_bus, dev=0, fn=0, size=4) & ~0x1F00) | ((int(cap >> 4).bit_length() - 1) << 8) - usb.pcie_cfg_req(cap_ptr + 0x08, bus=gpu_bus, dev=0, fn=0, value=new_ctrl, size=4) - - cap_ptr = pci.PCI_EXT_CAP_NEXT(hdr) - - mem_space_addr, bar_off, bars = [mem_base, pref_mem_base], 0, {} - while bar_off < 24: - cfg = usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off, bus=gpu_bus, dev=0, fn=0, size=4) - bar_mem, bar_64 = bool(cfg & pci.PCI_BASE_ADDRESS_MEM_PREFETCH), cfg & pci.PCI_BASE_ADDRESS_MEM_TYPE_64 - - if (cfg & pci.PCI_BASE_ADDRESS_SPACE) == pci.PCI_BASE_ADDRESS_SPACE_MEMORY: - usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off, bus=gpu_bus, dev=0, fn=0, value=0xffffffff, size=4) - lo = (usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off, bus=gpu_bus, dev=0, fn=0, size=4) & 0xfffffff0) - - if bar_64: usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off + 4, bus=gpu_bus, dev=0, fn=0, value=0xffffffff, size=4) - hi = (usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off + 4, bus=gpu_bus, dev=0, fn=0, size=4) if bar_64 else 0) - - bar_size = ((~(((hi << 32) | lo) & ~0xf)) + 1) & (0xffffffffffffffff if bar_64 else 0xffffffff) - - usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off, bus=gpu_bus, dev=0, fn=0, value=mem_space_addr[bar_mem] & 0xffffffff, size=4) - if bar_64: usb.pcie_cfg_req(pci.PCI_BASE_ADDRESS_0 + bar_off + 4, bus=gpu_bus, dev=0, fn=0, value=mem_space_addr[bar_mem] >> 32, size=4) - - bars[bar_off // 4] = (mem_space_addr[bar_mem], bar_size) - mem_space_addr[bar_mem] += round_up(bar_size, 2 << 20) - - bar_off += 8 if bar_64 else 4 - - usb.pcie_cfg_req(pci.PCI_COMMAND, bus=gpu_bus, dev=0, fn=0, value=pci.PCI_COMMAND_IO | pci.PCI_COMMAND_MEMORY | pci.PCI_COMMAND_MASTER, size=1) - return bars diff --git a/tinygrad/tinygrad/runtime/support/compiler_amd.py b/tinygrad/tinygrad/runtime/support/compiler_amd.py deleted file mode 100644 index fd00ea03..00000000 --- a/tinygrad/tinygrad/runtime/support/compiler_amd.py +++ /dev/null @@ -1,100 +0,0 @@ -import ctypes, subprocess -import tinygrad.runtime.autogen.comgr as comgr -assert comgr.AMD_COMGR_LANGUAGE_HIP == 4 -try: - comgr.amd_comgr_get_version(ctypes.byref(major:=ctypes.c_uint64()), ctypes.byref(minor:=ctypes.c_uint64())) - if major.value >= 3: - # in comgr 3 the values of enums in headers were changed: https://github.com/ROCm/llvm-project/issues/272 - import tinygrad.runtime.autogen.comgr_3 as comgr # type: ignore[no-redef] - assert comgr.AMD_COMGR_LANGUAGE_HIP == 3 -except AttributeError: pass # ignore if ROCm isn't installed -from tinygrad.device import Compiler, CompileError -from tinygrad.runtime.ops_llvm import LLVMCompiler -from tinygrad.helpers import OSX, to_char_p_p - -def amdgpu_disassemble(lib:bytes): - asm = subprocess.check_output(["llvm-objdump" if OSX else "/opt/rocm/llvm/bin/llvm-objdump", '-d', '-'], input=lib) - print('\n'.join([x for x in asm.decode('utf-8').split("\n") if 's_code_end' not in x])) - -def check(status): - if status != 0: - comgr.amd_comgr_status_string(status, ctypes.byref(status_str := ctypes.POINTER(ctypes.c_char)())) - raise RuntimeError(f"comgr fail {status}, {ctypes.string_at(status_str).decode()}") - -def _get_comgr_data(data_set, data_type): - check(comgr.amd_comgr_action_data_get_data(data_set, data_type, 0, ctypes.byref(data_exec := comgr.amd_comgr_data_t()))) - check(comgr.amd_comgr_get_data(data_exec, ctypes.byref(sz := ctypes.c_uint64()), None)) - check(comgr.amd_comgr_get_data(data_exec, ctypes.byref(sz), (dat := ctypes.create_string_buffer(sz.value)))) - check(comgr.amd_comgr_release_data(data_exec)) - return bytes(dat) - -# amd_comgr_action_info_set_options was deprecated -def set_options(action_info, options:bytes): - # TODO: this type should be correct in the autogen stub - comgr.amd_comgr_action_info_set_option_list.argtypes = [comgr.amd_comgr_action_info_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), comgr.size_t] - return comgr.amd_comgr_action_info_set_option_list(action_info, to_char_p_p(options_list:=options.split(b' ')), len(options_list)) - -# AMD_COMGR_SAVE_TEMPS=1 AMD_COMGR_REDIRECT_LOGS=stdout AMD_COMGR_EMIT_VERBOSE_LOGS=1 -def compile_hip(prg:str, arch="gfx1100", asm=False) -> bytes: - check(comgr.amd_comgr_create_action_info(ctypes.byref(action_info := comgr.amd_comgr_action_info_t()))) - check(comgr.amd_comgr_action_info_set_language(action_info, comgr.AMD_COMGR_LANGUAGE_HIP)) - check(comgr.amd_comgr_action_info_set_isa_name(action_info, b"amdgcn-amd-amdhsa--" + arch.encode())) - check(comgr.amd_comgr_action_info_set_logging(action_info, True)) - - check(comgr.amd_comgr_create_data_set(ctypes.byref(data_set_src := comgr.amd_comgr_data_set_t()))) - check(comgr.amd_comgr_create_data_set(ctypes.byref(data_set_bc := comgr.amd_comgr_data_set_t()))) - check(comgr.amd_comgr_create_data_set(ctypes.byref(data_set_reloc := comgr.amd_comgr_data_set_t()))) - check(comgr.amd_comgr_create_data_set(ctypes.byref(data_set_exec := comgr.amd_comgr_data_set_t()))) - - check(comgr.amd_comgr_create_data(comgr.AMD_COMGR_DATA_KIND_SOURCE, ctypes.byref(data_src := comgr.amd_comgr_data_t()))) - check(comgr.amd_comgr_set_data(data_src, len(rprg := prg.encode()), rprg)) - - if asm: - check(comgr.amd_comgr_set_data_name(data_src, b".s")) - check(comgr.amd_comgr_data_set_add(data_set_src, data_src)) - status = comgr.amd_comgr_do_action(comgr.AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE, action_info, data_set_src, data_set_reloc) - if status != 0: - print(_get_comgr_data(data_set_reloc, comgr.AMD_COMGR_DATA_KIND_LOG).decode()) - raise RuntimeError("assemble failed") - else: - check(comgr.amd_comgr_set_data_name(data_src, b"")) - check(comgr.amd_comgr_data_set_add(data_set_src, data_src)) - # -include hiprtc_runtime.h was removed - check(set_options(action_info, f"-O3 -mcumode --hip-version=6.0.32830 -DHIP_VERSION_MAJOR=6 -DHIP_VERSION_MINOR=0 -DHIP_VERSION_PATCH=32830 -D__HIPCC_RTC__ -std=c++14 -nogpuinc -Wno-gnu-line-marker -Wno-missing-prototypes --offload-arch={arch} -I/opt/rocm/include -Xclang -disable-llvm-passes -Xclang -aux-triple -Xclang x86_64-unknown-linux-gnu".encode())) # noqa: E501 - status = comgr.amd_comgr_do_action(comgr.AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, action_info, data_set_src, data_set_bc) - if status != 0: - print(_get_comgr_data(data_set_bc, comgr.AMD_COMGR_DATA_KIND_LOG).decode()) - raise RuntimeError("compile failed") - check(set_options(action_info, b"-O3 -mllvm -amdgpu-internalize-symbols")) - check(comgr.amd_comgr_do_action(comgr.AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE, action_info, data_set_bc, data_set_reloc)) - - check(set_options(action_info, b"")) - check(comgr.amd_comgr_do_action(comgr.AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE, action_info, data_set_reloc, data_set_exec)) - ret = _get_comgr_data(data_set_exec, comgr.AMD_COMGR_DATA_KIND_EXECUTABLE) - check(comgr.amd_comgr_release_data(data_src)) - for x in [data_set_src, data_set_bc, data_set_reloc, data_set_exec]: check(comgr.amd_comgr_destroy_data_set(x)) - check(comgr.amd_comgr_destroy_action_info(action_info)) - return ret - -class HIPCompiler(Compiler): - def __init__(self, arch:str): - self.arch = arch - super().__init__(f"compile_hip_{self.arch}") - def compile(self, src:str) -> bytes: - try: return compile_hip(src, self.arch, src.split('\n', 1)[0].strip() == '.text') - except RuntimeError as e: raise CompileError(e) from e - def disassemble(self, lib:bytes): amdgpu_disassemble(lib) - -class AMDLLVMCompiler(LLVMCompiler): - jit = False - target_arch = "AMDGPU" - def __init__(self, arch: str): - self.arch = arch - super().__init__(self.arch, "+cumode") - def __reduce__(self): return (AMDLLVMCompiler, (self.arch,)) - def compile(self, src:str) -> bytes: - try: return super().compile(src) - except RuntimeError as e: - if "undefined value '@llvm.amdgcn." in str(e): raise CompileError(str(e) + "AMD with LLVM backend requires LLVM >= 18") from e - raise CompileError(e) from e - def disassemble(self, lib:bytes): amdgpu_disassemble(lib) diff --git a/tinygrad/tinygrad/runtime/support/compiler_cuda.py b/tinygrad/tinygrad/runtime/support/compiler_cuda.py deleted file mode 100644 index 1b27d026..00000000 --- a/tinygrad/tinygrad/runtime/support/compiler_cuda.py +++ /dev/null @@ -1,76 +0,0 @@ -import subprocess, hashlib, tempfile, ctypes, ctypes.util, re, pathlib -from typing import Callable -from tinygrad.helpers import to_char_p_p, colored, init_c_var, getenv -import tinygrad.runtime.autogen.nvrtc as nvrtc -from tinygrad.device import Compiler, CompileError - -PTX, CUDA_PATH = getenv("PTX"), getenv("CUDA_PATH", "") # PTX shouldn't be here, in fact, it shouldn't exist - -def _get_bytes(arg, get_str, get_sz, check) -> bytes: - sz = init_c_var(ctypes.c_size_t(), lambda x: check(get_sz(arg, ctypes.byref(x)))) - return ctypes.string_at(init_c_var(ctypes.create_string_buffer(sz.value), lambda x: check(get_str(arg, x))), size=sz.value) - -def nvrtc_check(status, ctx=None): - if status != 0: - err_log = _get_bytes(ctx, nvrtc.nvrtcGetProgramLog, nvrtc.nvrtcGetProgramLogSize, lambda _: None).decode() if ctx else "" - raise CompileError(f"Nvrtc Error {status}, {ctypes.string_at(nvrtc.nvrtcGetErrorString(status)).decode()}\n{err_log}") - -def jitlink_check(status, ctx=None): - if status != 0: - err_log = _get_bytes(ctx, nvrtc.nvJitLinkGetErrorLog, nvrtc.nvJitLinkGetErrorLogSize, lambda _: None).decode() if ctx else "" - raise CompileError(f"NvJitLink Error {status}, {nvrtc.nvJitLinkResult__enumvalues.get(status, 'Unknown')}\n{err_log}") - -def pretty_ptx(s): - # all expressions match `` and replace it with `color()` - s = re.sub(r'([!@<\[\s,\+\-;\n])((?:[_%$][\w%\$_]+(?:\.[xyz])?\:?)|(?:buf\d+))([<>\]\s,\+\-;\n\)])', lambda m:m[1]+colored(m[2], "blue")+m[3], s, flags=re.M) # identifiers # noqa: E501 - s = re.sub(r'(.)((?:b|s|u|f)(?:8|16|32|64)|pred)([\.\s])', lambda m:m[1]+colored(m[2], "green")+m[3], s, flags=re.M) # types - s = re.sub(r'^(\s*)([\w]+)(.*?;$)', lambda m:m[1]+colored(m[2], "yellow")+m[3], s, flags=re.M) # instructions - s = re.sub(r'([<>\[\]\s,\+\-;])((?:0[fF][0-9a-fA-F]{8})|(?:[0-9]+)|(?:0[xX][0-9a-fA-F]+))([<>\[\]\s,\+\-;])', lambda m:m[1]+colored(m[2], "yellow")+m[3], s, flags=re.M) # numbers # noqa: E501 - s = re.sub(r'(\.)(param|reg|global)', lambda m:m[1]+colored(m[2], "magenta"), s, flags=re.M) # space - s = re.sub(r'(\.)(version|target|address_size|visible|entry)', lambda m:m[1]+colored(m[2], "magenta"), s, flags=re.M) # derivatives - return s - -def cuda_disassemble(lib:bytes, arch:str): - try: - fn = (pathlib.Path(tempfile.gettempdir()) / f"tinycuda_{hashlib.md5(lib).hexdigest()}").as_posix() - with open(fn, "wb") as f: f.write(lib) - subprocess.run(["ptxas", f"-arch={arch}", "-o", fn, fn], check=False, stderr=subprocess.DEVNULL) # optional ptx -> sass step for CUDA=1 - print(subprocess.check_output(['nvdisasm', fn]).decode('utf-8')) - except Exception as e: print("Failed to generate SASS", str(e), "Make sure your PATH contains ptxas/nvdisasm binary of compatible version.") - -class CUDACompiler(Compiler): - def __init__(self, arch:str, cache_key:str="cuda"): - self.arch, self.compile_options = arch, [f'--gpu-architecture={arch}'] - self.compile_options += [f"-I{CUDA_PATH}/include"] if CUDA_PATH else ["-I/usr/local/cuda/include", "-I/usr/include", "-I/opt/cuda/include"] - nvrtc_check(nvrtc.nvrtcVersion((nvrtcMajor := ctypes.c_int()), (nvrtcMinor := ctypes.c_int()))) - if (nvrtcMajor.value, nvrtcMinor.value) >= (12, 4): self.compile_options.append("--minimal") - super().__init__(f"compile_{cache_key}_{self.arch}") - def _compile_program(self, src:str, nvrtc_get_content:Callable, nvrtc_get_size:Callable) -> bytes: - nvrtc_check(nvrtc.nvrtcCreateProgram(ctypes.byref(prog := nvrtc.nvrtcProgram()), src.encode(), "".encode(), 0, None, None)) - nvrtc_check(nvrtc.nvrtcCompileProgram(prog, len(self.compile_options), to_char_p_p([o.encode() for o in self.compile_options])), prog) - data = _get_bytes(prog, nvrtc_get_content, nvrtc_get_size, nvrtc_check) - nvrtc_check(nvrtc.nvrtcDestroyProgram(ctypes.byref(prog))) - return data - def compile(self, src:str) -> bytes: return self._compile_program(src, nvrtc.nvrtcGetPTX, nvrtc.nvrtcGetPTXSize) - def disassemble(self, lib:bytes): cuda_disassemble(lib, self.arch) - -class NVCompiler(CUDACompiler): - def __init__(self, arch:str): super().__init__(arch, cache_key="nv") - def compile(self, src:str) -> bytes: return self._compile_program(src, nvrtc.nvrtcGetCUBIN, nvrtc.nvrtcGetCUBINSize) - -class PTXCompiler(Compiler): - def __init__(self, arch:str, cache_key="ptx"): - self.arch = arch - super().__init__(f"compile_{cache_key}_{self.arch}") - def compile(self, src:str) -> bytes: return src.replace("TARGET", self.arch).replace("VERSION", "7.8" if self.arch >= "sm_89" else "7.5").encode() - def disassemble(self, lib:bytes): cuda_disassemble(lib, self.arch) - -class NVPTXCompiler(PTXCompiler): - def __init__(self, arch:str): super().__init__(arch, cache_key="nv_ptx") - def compile(self, src:str) -> bytes: - jitlink_check(nvrtc.nvJitLinkCreate(handle := nvrtc.nvJitLinkHandle(), 1, to_char_p_p([f'-arch={self.arch}'.encode()])), handle) - jitlink_check(nvrtc.nvJitLinkAddData(handle, nvrtc.NVJITLINK_INPUT_PTX, ptxsrc:=super().compile(src), len(ptxsrc), "".encode()), handle) - jitlink_check(nvrtc.nvJitLinkComplete(handle), handle) - data = _get_bytes(handle, nvrtc.nvJitLinkGetLinkedCubin, nvrtc.nvJitLinkGetLinkedCubinSize, jitlink_check) - jitlink_check(nvrtc.nvJitLinkDestroy(handle)) - return data diff --git a/tinygrad/tinygrad/runtime/support/elf.py b/tinygrad/tinygrad/runtime/support/elf.py deleted file mode 100644 index 26495ca3..00000000 --- a/tinygrad/tinygrad/runtime/support/elf.py +++ /dev/null @@ -1,62 +0,0 @@ -import struct, tinygrad.runtime.autogen.libc as libc -from dataclasses import dataclass -from tinygrad.helpers import getbits, i2u - -@dataclass(frozen=True) -class ElfSection: name:str; header:libc.Elf64_Shdr; content:bytes # noqa: E702 - -def elf_loader(blob:bytes, force_section_align:int=1) -> tuple[memoryview, list[ElfSection], list[tuple]]: - def _strtab(blob: bytes, idx: int) -> str: return blob[idx:blob.find(b'\x00', idx)].decode('utf-8') - - header = libc.Elf64_Ehdr.from_buffer_copy(blob) - section_headers = (libc.Elf64_Shdr * header.e_shnum).from_buffer_copy(blob[header.e_shoff:]) - sh_strtab = blob[(shstrst:=section_headers[header.e_shstrndx].sh_offset):shstrst+section_headers[header.e_shstrndx].sh_size] - sections = [ElfSection(_strtab(sh_strtab, sh.sh_name), sh, blob[sh.sh_offset:sh.sh_offset+sh.sh_size]) for sh in section_headers] - - def _to_carray(sh, ctype): return (ctype * (sh.header.sh_size // sh.header.sh_entsize)).from_buffer_copy(sh.content) - rel = [(sh, sh.name[4:], _to_carray(sh, libc.Elf64_Rel)) for sh in sections if sh.header.sh_type == libc.SHT_REL] - rela = [(sh, sh.name[5:], _to_carray(sh, libc.Elf64_Rela)) for sh in sections if sh.header.sh_type == libc.SHT_RELA] - symtab = [_to_carray(sh, libc.Elf64_Sym) for sh in sections if sh.header.sh_type == libc.SHT_SYMTAB][0] - progbits = [sh for sh in sections if sh.header.sh_type == libc.SHT_PROGBITS] - - # Prealloc image for all fixed addresses. - image = bytearray(max([sh.header.sh_addr + sh.header.sh_size for sh in progbits if sh.header.sh_addr != 0] + [0])) - for sh in progbits: - if sh.header.sh_addr != 0: image[sh.header.sh_addr:sh.header.sh_addr+sh.header.sh_size] = sh.content - else: - image += b'\0' * (((align:=max(sh.header.sh_addralign, force_section_align)) - len(image) % align) % align) + sh.content - sh.header.sh_addr = len(image) - len(sh.content) - - # Relocations - relocs = [] - for sh, trgt_sh_name, c_rels in rel + rela: - target_image_off = next(tsh for tsh in sections if tsh.name == trgt_sh_name).header.sh_addr - rels = [(r.r_offset, symtab[libc.ELF64_R_SYM(r.r_info)], libc.ELF64_R_TYPE(r.r_info), getattr(r, "r_addend", 0)) for r in c_rels] - for roff, sym, r_type_, r_addend in rels: - if sym.st_shndx == 0: raise RuntimeError(f'Attempting to relocate against an undefined symbol {repr(_strtab(sh_strtab, sym.st_name))}') - relocs += [(target_image_off + roff, sections[sym.st_shndx].header.sh_addr + sym.st_value, rtype, raddend) for roff, sym, rtype, raddend in rels] - - return memoryview(image), sections, relocs - -def relocate(instr: int, ploc: int, tgt: int, r_type: int): - match r_type: - # https://refspecs.linuxfoundation.org/elf/x86_64-abi-0.95.pdf - case libc.R_X86_64_PC32: return i2u(32, tgt-ploc) - # https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst for definitions of relocations - # https://www.scs.stanford.edu/~zyedidia/arm64/index.html for instruction encodings - case libc.R_AARCH64_ADR_PREL_PG_HI21: - rel_pg = (tgt & ~0xFFF) - (ploc & ~0xFFF) - return instr | (getbits(rel_pg, 12, 13) << 29) | (getbits(rel_pg, 14, 32) << 5) - case libc.R_AARCH64_ADD_ABS_LO12_NC: return instr | (getbits(tgt, 0, 11) << 10) - case libc.R_AARCH64_LDST16_ABS_LO12_NC: return instr | (getbits(tgt, 1, 11) << 10) - case libc.R_AARCH64_LDST32_ABS_LO12_NC: return instr | (getbits(tgt, 2, 11) << 10) - case libc.R_AARCH64_LDST64_ABS_LO12_NC: return instr | (getbits(tgt, 3, 11) << 10) - case libc.R_AARCH64_LDST128_ABS_LO12_NC: return instr | (getbits(tgt, 4, 11) << 10) - raise NotImplementedError(f"Encountered unknown relocation type {r_type}") - -def jit_loader(obj: bytes) -> bytes: - image, _, relocs = elf_loader(obj) - # This is needed because we have an object file, not a .so that has all internal references (like loads of constants from .rodata) resolved. - for ploc,tgt,r_type,r_addend in relocs: - image[ploc:ploc+4] = struct.pack(" MMIOInterface: - return MMIOInterface(self.addr+offset, size or (self.nbytes - offset), fmt=fmt or self.fmt) - -class FileIOInterface: - """ - Hardware Abstraction Layer for HCQ devices. The class provides a unified interface for interacting with hardware devices. - """ - - def __init__(self, path:str="", flags:int=os.O_RDONLY, fd:int|None=None): - self.path:str = path - self.fd:int = fd or os.open(path, flags) - def __del__(self): - if hasattr(self, 'fd'): os.close(self.fd) - def ioctl(self, request, arg): return fcntl.ioctl(self.fd, request, arg) - def mmap(self, start, sz, prot, flags, offset): - x = libc.mmap(start, sz, prot, flags, self.fd, offset) - if x == 0xffffffffffffffff: raise OSError(f"Failed to mmap {sz} bytes at {hex(start)}: {os.strerror(ctypes.get_errno())}") - return x - def read(self, size=None, binary=False, offset=None): - if offset is not None: self.seek(offset) - with open(self.fd, "rb" if binary else "r", closefd=False) as file: return file.read(size) - def write(self, content, binary=False, offset=None): - if offset is not None: self.seek(offset) - with open(self.fd, "wb" if binary else "w", closefd=False) as file: file.write(content) - def listdir(self): return os.listdir(self.path) - def seek(self, offset): os.lseek(self.fd, offset, os.SEEK_SET) - @staticmethod - def anon_mmap(start, sz, prot, flags, offset): - x = libc.mmap(start, sz, prot, flags, -1, offset) - if x == 0xffffffffffffffff: raise OSError(f"Failed to mmap {sz} bytes at {hex(start)}: {os.strerror(ctypes.get_errno())}") - return x - @staticmethod - def munmap(buf, sz): return libc.munmap(buf, sz) - @staticmethod - def exists(path): return os.path.exists(path) - @staticmethod - def readlink(path): return os.readlink(path) - @staticmethod - def eventfd(initval, flags=None): return FileIOInterface(fd=os.eventfd(initval, flags)) # type: ignore[attr-defined] - -if MOCKGPU:=getenv("MOCKGPU"): from test.mockgpu.mockgpu import MockFileIOInterface as FileIOInterface # noqa: F401 # pylint: disable=unused-import - -# **************** for HCQ Compatible Devices **************** - -SignalType = TypeVar('SignalType', bound='HCQSignal') -HCQDeviceType = TypeVar('HCQDeviceType', bound='HCQCompiled') -ProgramType = TypeVar('ProgramType', bound='HCQProgram') -ArgsStateType = TypeVar('ArgsStateType', bound='HCQArgsState') -QueueType = TypeVar('QueueType', bound='HWQueue') - -class BumpAllocator: - def __init__(self, size:int, base:int=0, wrap:bool=True): self.size, self.ptr, self.base, self.wrap = size, 0, base, wrap - def alloc(self, size:int, alignment:int=1) -> int: - if round_up(self.ptr, alignment) + size > self.size: - if not self.wrap: raise RuntimeError("Out of memory") - self.ptr = 0 - self.ptr = (res:=round_up(self.ptr, alignment)) + size - return res + self.base - -class HWQueue(Generic[SignalType, HCQDeviceType, ProgramType, ArgsStateType]): - """ - A base class for hardware command queues in the HCQ (Hardware Command Queue) API. - """ - - def __init__(self): - self._q:Any = [] - self.binded_device:HCQDeviceType|None = None - self.q_sints:list[tuple[int, int]] = [] - self.mv_sints:list[tuple[MMIOInterface, int, int, int|None]] = [] - self.syms:list[sint] = [] - self._prev_resolved_syms:list[int|None] = [] - - def _new_sym(self, sym:sint) -> int: - if sym not in self.syms: - self.syms.append(sym) - self._prev_resolved_syms.append(None) - return self.syms.index(sym) - - def q(self, *values): - """ - Enqueues values in the queue. - - Args: - values: The values to enqueue in the queue. - """ - - for v in values: - if isinstance(v, UOp): - self.q_sints.append((len(self._q), self._new_sym(v))) - self._q.append(0xbadc0ded) - else: self._q.append(v) - - # *** common commands *** - - def timestamp(self, signal:SignalType): - """ - Enqueues a timestamp command which records the current time in a signal after all previously enqueued commands are completed. - - Args: - signal: The signal to store the timestamp - """ - - def signal(self, signal:SignalType, value:sint): - """ - Enqueues a signal command which sets the signal to the given value, ensuring all previous operations are completed. - - Args: - signal: The signal to set - value: The value to set the signal to - """ - - def wait(self, signal:SignalType, value:sint): - """ - Enqueues a wait command which halts execution until the signal is greater than or equal to a specific value. - - Args: - signal: The signal to wait on - value: The value to wait for - """ - - # *** commands for compute queues *** - - def memory_barrier(self): - """ - Enqueues a memory barrier command to ensure memory coherence between agents. Only on compute queues. - """ - - def exec(self, prg:ProgramType, args_state:ArgsStateType, global_size:tuple[sint, ...], local_size:tuple[sint, ...]): - """ - Enqueues an execution command for a kernel program. Only on compute queues. - - Args: - prg: The program to execute - args_state: The args state to execute program with - global_size: The global work size - local_size: The local work size - """ - - # *** commands for copy queues *** - - def copy(self, dest:sint, src:sint, copy_size:int): - """ - Enqueues a copy command to transfer data. Only on copy queues. - - Args: - dest: The destination of the copy - src: The source of the copy - copy_size: The size of data to copy - """ - - # *** submit and bind commands *** - - def bind(self, dev:HCQDeviceType): - """ - Associates the queue with a specific device for optimized execution. - - This optional method allows backend implementations to tailor the queue for efficient use on the given device. When implemented, it can eliminate - the need to copy queues into the device, thereby enhancing performance. - - Args: - dev: The target device for queue optimization. - - Note: - Implementing this method is optional but recommended for performance gains. - """ - - def bind_args_state(self, args_state:ArgsStateType): - for vals, mem, fmt in args_state.bind_data: self.bind_sints_to_mem(*vals, mem=mem, fmt=fmt) - - def bind_sints(self, *vals:sint, mem:MMIOInterface, struct_t:Type[ctypes.Structure], start_field:str, fmt, mask:int|None=None): - self.bind_sints_to_mem(*vals, mem=mem, fmt=fmt, mask=mask, offset=getattr(struct_t, start_field).offset) - - def bind_sints_to_mem(self, *vals:sint, mem:MMIOInterface, fmt, mask:int|None=None, offset:int=0): - mv = mem.view(offset=offset, size=len(vals)*8, fmt=fmt) - for i, val in enumerate(vals): - if isinstance(val, int): mv[i] = val if mask is None else ((mv[i] & ~mask) | val) - else: self.mv_sints.append((mv, i, self._new_sym(val), mask)) - - def _apply_var_vals(self, var_vals:dict[Variable, int]): - resolved_syms = [sym_infer(sym, var_vals) for sym in self.syms] - - for off, sym_idx in self.q_sints: - if self._prev_resolved_syms[sym_idx] == resolved_syms[sym_idx]: continue - self._q[off] = resolved_syms[sym_idx] - - for mv, off, sym_idx, mask in self.mv_sints: - if self._prev_resolved_syms[sym_idx] == resolved_syms[sym_idx]: continue - mv[off] = resolved_syms[sym_idx] if mask is None else ((mv[off] & ~mask) | resolved_syms[sym_idx]) - - self._prev_resolved_syms = cast(list[int|None], resolved_syms) - - def submit(self, dev:HCQDeviceType, var_vals:dict[Variable, int]|None=None): - """ - Submits the command queue to a specific device for execution. - - Args: - dev: The device to submit the queue to - """ - - if var_vals is not None: self._apply_var_vals(var_vals) - self._submit(dev) - return self - def _submit(self, dev:HCQDeviceType): raise NotImplementedError("need _submit") - -class HCQSignal(Generic[HCQDeviceType]): - def __init__(self, base_buf:HCQBuffer|None=None, value:int=0, dev_t:Type[HCQDeviceType]|None=None, timeline_for_device:HCQDeviceType|None=None, - timestamp_divider=1, value_off=0, timestamp_off=8): - self.base_buf = cast(HCQBuffer, dev_t._alloc_signal() if dev_t is not None and base_buf is None else base_buf) - self.value_addr, self.timestamp_addr, self.dev_t = self.base_buf.va_addr+value_off, self.base_buf.va_addr+timestamp_off, dev_t - self.timestamp_divider:decimal.Decimal = decimal.Decimal(timestamp_divider) - self.timeline_for_device:HCQDeviceType|None = timeline_for_device - - if isinstance(self.base_buf.va_addr, int): - self.value_mv, self.timestamp_mv = self.base_buf.cpu_view().view(value_off, 8, 'Q'), self.base_buf.cpu_view().view(timestamp_off, 8, 'Q') - self.value_mv[0] = value - - def __del__(self): - if isinstance(self.base_buf.va_addr, int) and self.dev_t is not None: self.dev_t.signal_pool.append(self.base_buf) - - @property - def value(self) -> int: return self.value_mv[0] - - @value.setter - def value(self, new_value:int): self.value_mv[0] = new_value - - @property - def timestamp(self) -> decimal.Decimal: - """ - Get the timestamp field of the signal. - - This property provides read-only access to the signal's timestamp. - - Returns: - The timestamp in microseconds. - """ - return self.timestamp_mv[0] / self.timestamp_divider - - def _sleep(self, time_spent_waiting_ms:int): - """ - Optional function which can implement sleep functionality for the signal. - """ - - def wait(self, value:int, timeout:int=getenv("HCQDEV_WAIT_TIMEOUT_MS", 30000)): - """ - Waits the signal is greater than or equal to a specific value. - - Args: - value: The value to wait for. - timeout: Maximum time to wait in milliseconds. Defaults to 30s. - """ - start_time = int(time.perf_counter() * 1000) - while (not_passed:=(prev_value:=self.value) < value) and (time_spent:=int(time.perf_counter() * 1000) - start_time) < timeout: - self._sleep(time_spent) - if self.value != prev_value: start_time = int(time.perf_counter() * 1000) # progress was made, reset timer - if not_passed and self.value < value: raise RuntimeError(f"Wait timeout: {timeout} ms! (the signal is not set to {value}, but {self.value})") - -@contextlib.contextmanager -def hcq_profile(dev:HCQCompiled, enabled, desc, queue_type:Callable[[], HWQueue]|None=None, queue:HWQueue|None=None): - st, en = (dev.signal_t(), dev.signal_t()) if enabled else (None, None) - - if enabled and queue is not None: queue.timestamp(st) - elif enabled: - assert queue_type is not None - queue_type().wait(dev.timeline_signal, dev.timeline_value - 1).timestamp(st).signal(dev.timeline_signal, dev.next_timeline()).submit(dev) - - try: yield (st, en) - finally: - if enabled and queue is not None: queue.timestamp(en) - elif enabled: - assert queue_type is not None - queue_type().wait(dev.timeline_signal, dev.timeline_value - 1).timestamp(en).signal(dev.timeline_signal, dev.next_timeline()).submit(dev) - - if enabled and PROFILE: dev.sig_prof_records.append((cast(HCQSignal, st), cast(HCQSignal, en), desc, queue_type is dev.hw_copy_queue_t)) - -class HCQArgsState(Generic[ProgramType]): - def __init__(self, buf:HCQBuffer, prg:ProgramType, bufs:tuple[HCQBuffer, ...], vals:tuple[sint, ...]=()): - self.buf, self.prg = buf, prg - self.bind_data:list[tuple[tuple[sint, ...], MMIOInterface, str]] = [] - - def bind_sints_to_buf(self, *vals:sint, buf:HCQBuffer, fmt, offset=0): self.bind_data.append((vals, buf.cpu_view().view(offset=offset), fmt)) - -class CLikeArgsState(HCQArgsState[ProgramType]): - def __init__(self, buf:HCQBuffer, prg:ProgramType, bufs:tuple[HCQBuffer, ...], vals:tuple[sint, ...]=(), prefix:list[int]|None=None): - super().__init__(buf, prg, bufs, vals=vals) - - if prefix is not None: self.buf.cpu_view().view(size=len(prefix) * 4, fmt='I')[:] = array.array('I', prefix) - - self.bind_sints_to_buf(*[b.va_addr for b in bufs], buf=self.buf, fmt='Q', offset=len(prefix or []) * 4) - self.bind_sints_to_buf(*vals, buf=self.buf, fmt='I', offset=len(prefix or []) * 4 + len(bufs) * 8) - -class HCQProgram(Generic[HCQDeviceType]): - def __init__(self, args_state_t:Type[HCQArgsState], dev:HCQDeviceType, name:str, kernargs_alloc_size:int, lib:bytes|None=None, base:int|None=None): - self.args_state_t, self.dev, self.name, self.kernargs_alloc_size = args_state_t, dev, name, kernargs_alloc_size - if PROFILE: Compiled.profile_events += [ProfileProgramEvent(dev.device, name, lib, base)] - - @staticmethod - def _fini(dev, buf, spec): dev.allocator.free(buf, buf.size, spec) - - def fill_kernargs(self, bufs:tuple[HCQBuffer, ...], vals:tuple[int, ...]=(), kernargs:HCQBuffer|None=None) -> HCQArgsState: - """ - Fills arguments for the kernel, optionally allocating space from the device if `kernargs_ptr` is not provided. - Args: - bufs: Buffers to be written to kernel arguments. - vals: Values to be written to kernel arguments. - kernargs_ptr: Optional pointer to pre-allocated kernel arguments memory. - Returns: - Arguments state with the given buffers and values set for the program. - """ - argsbuf = kernargs or self.dev.kernargs_buf.offset(offset=self.dev.kernargs_offset_allocator.alloc(self.kernargs_alloc_size)) - return self.args_state_t(argsbuf, self, bufs, vals=vals) - - def __call__(self, *bufs:HCQBuffer, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), - vals:tuple[int, ...]=(), wait:bool=False) -> float|None: - """ - Enqueues the program for execution with the given arguments and dimensions. - - Args: - bufs: Buffer arguments to execute the kernel with. - global_size: Specifies the global work size for kernel execution (equivalent to CUDA's grid size). - local_size: Specifies the local work size for kernel execution (equivalent to CUDA's block size). - vals: Value arguments to execute the kernel with. - wait: If True, waits for the kernel to complete execution. - - Returns: - Execution time of the kernel if 'wait' is True, otherwise None. - """ - - kernargs = self.fill_kernargs(bufs, vals) - q = self.dev.hw_compute_queue_t().wait(self.dev.timeline_signal, self.dev.timeline_value - 1).memory_barrier() - - with hcq_profile(self.dev, queue=q, desc=self.name, enabled=wait or PROFILE) as (sig_st, sig_en): - q.exec(self, kernargs, global_size, local_size) - - q.signal(self.dev.timeline_signal, self.dev.next_timeline()).submit(self.dev) - - if wait: self.dev.synchronize() - return (float(sig_en.timestamp - sig_st.timestamp) / 1e6) if wait else None - -class HCQCompiled(Compiled, Generic[SignalType]): - """ - A base class for devices compatible with the HCQ (Hardware Command Queue) API. - """ - devices: ClassVar[list[HCQCompiled]] = [] - signal_pages: ClassVar[list[HCQBuffer]] = [] - signal_pool: ClassVar[list[HCQBuffer]] = [] - - def __init__(self, device:str, allocator:HCQAllocatorBase, renderer:Renderer, compiler:Compiler, runtime, signal_t:Type[SignalType], - comp_queue_t:Callable[[], HWQueue], copy_queue_t:Callable[[], HWQueue]|None, kernargs_size=(16 << 20), sigalloc_size=0x1000): - self.device_id:int = int(device.split(":")[1]) if ":" in device else 0 - - from tinygrad.runtime.graph.hcq import HCQGraph - super().__init__(device, allocator, renderer, compiler, runtime, HCQGraph) - - # Map signals if any - for sig_page in self.signal_pages: cast(HCQAllocator, self.allocator).map(sig_page) - self.devices.append(self) - - self.sigalloc_size = sigalloc_size - self.signal_t, self.hw_compute_queue_t, self.hw_copy_queue_t = signal_t, comp_queue_t, copy_queue_t - self.timeline_value:int = 1 - self.timeline_signal:SignalType = self.signal_t(value=0, timeline_for_device=self) - self._shadow_timeline_signal:SignalType = self.signal_t(value=0, timeline_for_device=self) - self.sig_prof_records:list[tuple[HCQSignal, HCQSignal, str, bool]] = [] - - self.kernargs_buf:HCQBuffer = self.allocator.alloc(kernargs_size, BufferSpec(cpu_access=True)) - self.kernargs_offset_allocator:BumpAllocator = BumpAllocator(self.kernargs_buf.size, wrap=True) - - def synchronize(self): - try: self.timeline_signal.wait(self.timeline_value - 1) - except RuntimeError as e: - if hasattr(self, 'on_device_hang'): self.on_device_hang() - else: raise e - - if self.timeline_value > (1 << 31): self._wrap_timeline_signal() - if PROFILE: - Compiled.profile_events += [ProfileRangeEvent(self.device, name, st.timestamp, en.timestamp, cp) for st,en,name,cp in self.sig_prof_records] - self.sig_prof_records = [] - - def next_timeline(self): - self.timeline_value += 1 - return self.timeline_value - 1 - - @classmethod - def _alloc_signal(cls) -> HCQBuffer: - if not cls.signal_pool: - cls.signal_pages.append(alc:=cls.devices[0].allocator.alloc(cls.devices[0].sigalloc_size, BufferSpec(host=True,uncached=True,cpu_access=True))) - cls.signal_pool += [alc.offset(offset=off, size=16) for off in range(0, alc.size, 16)] - for dev in cls.devices: cast(HCQAllocator, dev.allocator).map(alc) - return cls.signal_pool.pop() - - def _at_profile_finalize(self): - def _sync(d:HCQCompiled, q_t:Callable[[], HWQueue]): - q_t().timestamp(d.timeline_signal).signal(d.timeline_signal, d.next_timeline()).submit(d) - st = time.perf_counter_ns() - d.timeline_signal.wait(d.timeline_value - 1) # average of the two - et = time.perf_counter_ns() - return (decimal.Decimal(et+st) / 2000) - d.timeline_signal.timestamp - - gpu2cpu_compute_time_diff = statistics.median([_sync(self, self.hw_compute_queue_t) for _ in range(40)]) - if self.hw_copy_queue_t is None: gpu2cpu_copy_time_diff = decimal.Decimal(0) - else: gpu2cpu_copy_time_diff = statistics.median([_sync(self, self.hw_copy_queue_t) for _ in range(40)]) - Compiled.profile_events += [ProfileDeviceEvent(self.device, gpu2cpu_compute_time_diff, gpu2cpu_copy_time_diff)] - - def _wrap_timeline_signal(self): - self.timeline_signal, self._shadow_timeline_signal, self.timeline_value = self._shadow_timeline_signal, self.timeline_signal, 1 - self.timeline_signal.value = 0 - cast(HCQAllocatorBase, self.allocator).b_timeline = [0] * len(cast(HCQAllocatorBase, self.allocator).b) - - def _realloc(self, oldbuf:HCQBuffer|None, new_size:int, options:BufferSpec|None=None) -> tuple[HCQBuffer, bool]: - if oldbuf is not None: self.allocator.free(oldbuf, oldbuf.size, options=options) - try: buf, realloced = self.allocator.alloc(new_size, options=options), True - except MemoryError: buf, realloced = self.allocator.alloc(oldbuf.size if oldbuf is not None else new_size, options=options), False - return buf, realloced - -class HCQBuffer: - def __init__(self, va_addr:sint, size:int, texture_info:Any=None, meta:Any=None, _base:HCQBuffer|None=None, view:MMIOInterface|None=None): - self.va_addr, self.size, self.texture_info, self.meta, self._base, self.view = va_addr, size, texture_info, meta, _base, view - - def offset(self, offset:int=0, size:int|None=None) -> HCQBuffer: - return HCQBuffer(self.va_addr+offset, size or (self.size - offset), texture_info=self.texture_info, meta=self.meta, _base=self._base or self, - view=(self.view.view(offset=offset, size=size) if self.view is not None else None)) - - def cpu_view(self) -> MMIOInterface: - assert self.view is not None, "buffer has no cpu_view" - return self.view - -class HCQAllocatorBase(LRUAllocator[HCQDeviceType], Generic[HCQDeviceType]): - """ - A base allocator class compatible with the HCQ (Hardware Command Queue) API. - - This class implements basic copy operations following the HCQ API, utilizing both types of `HWQueue`. - """ - - def __init__(self, dev:HCQDeviceType, batch_size:int=(2 << 20), batch_cnt:int=32, copy_bufs=None, max_copyout_size:int|None=None): - super().__init__(dev) - self.b = copy_bufs or [self._alloc(batch_size, BufferSpec(host=True)) for _ in range(batch_cnt)] - self.b_timeline, self.b_next, self.max_copyout_size = [0] * len(self.b), 0, max_copyout_size - - def map(self, buf:HCQBuffer): pass - def _offset(self, buf, size:int, offset:int) -> HCQBuffer: return buf.offset(offset=offset, size=size) - -class HCQAllocator(HCQAllocatorBase, Generic[HCQDeviceType]): - def _copyin(self, dest:HCQBuffer, src:memoryview): - assert self.dev.hw_copy_queue_t is not None - with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"CPU -> {self.dev.device}", enabled=PROFILE): - for i in range(0, src.nbytes, self.b[0].size): - self.b_next = (self.b_next + 1) % len(self.b) - self.dev.timeline_signal.wait(self.b_timeline[self.b_next]) - - lsize = min(self.b[self.b_next].size, src.nbytes - i) - self.b[self.b_next].cpu_view().view(size=lsize, fmt='B')[:] = src[i:i+lsize] - self.dev.hw_copy_queue_t().wait(self.dev.timeline_signal, self.dev.timeline_value - 1) \ - .copy(dest.va_addr+i, self.b[self.b_next].va_addr, lsize) \ - .signal(self.dev.timeline_signal, self.dev.next_timeline()).submit(self.dev) - self.b_timeline[self.b_next] = self.dev.timeline_value - 1 - - def copy_from_disk(self, dest:HCQBuffer, src, size): - def _get_temp_buf(): - # Check if the next buffer is safe to be used (its signal has passed) and reserve it. - if self.b_timeline[(self.b_next + 1) % len(self.b)] <= self.dev.timeline_signal.value: - self.b_timeline[(self.b_next + 1) % len(self.b)], self.b_next = (1 << 64), (self.b_next + 1) % len(self.b) - return (self.b[self.b_next].va_addr, self.b_next) - return None - - assert self.dev.hw_copy_queue_t is not None - with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"DISK -> {self.dev.device}", enabled=PROFILE): - for (batch_info, dst_off, src_off, copy_size) in src.device.allocator._copyout_sharded(src, size, _get_temp_buf, seg_len=self.b[0].size): - self.dev.hw_copy_queue_t().wait(self.dev.timeline_signal, self.dev.timeline_value - 1) \ - .copy(dest.va_addr + dst_off, batch_info[0] + src_off, copy_size) \ - .signal(self.dev.timeline_signal, self.dev.next_timeline()).submit(self.dev) - self.b_timeline[batch_info[1]] = self.dev.timeline_value - 1 - - def _copyout(self, dest:memoryview, src:HCQBuffer): - self.dev.synchronize() - - assert self.dev.hw_copy_queue_t is not None - with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"{self.dev.device} -> CPU", enabled=PROFILE): - for i in range(0, dest.nbytes, cp_size:=(self.max_copyout_size or self.b[0].size)): - self.dev.hw_copy_queue_t().wait(self.dev.timeline_signal, self.dev.timeline_value - 1) \ - .copy(self.b[0].va_addr, src.va_addr+i, lsize:=min(cp_size, dest.nbytes-i)) \ - .signal(self.dev.timeline_signal, self.dev.next_timeline()).submit(self.dev) - self.dev.timeline_signal.wait(self.dev.timeline_value - 1) - dest[i:i+lsize] = self.b[0].cpu_view().view(size=lsize, fmt='B')[:] - - def _transfer(self, dest:HCQBuffer, src:HCQBuffer, sz:int, src_dev:HCQDeviceType, dest_dev:HCQDeviceType): - cast(HCQAllocator, src_dev.allocator).map(dest) - - assert src_dev.hw_copy_queue_t is not None - with hcq_profile(src_dev, queue_type=src_dev.hw_copy_queue_t, desc=f"{src_dev.device} -> {dest_dev.device}", enabled=PROFILE): - src_dev.hw_copy_queue_t().wait(src_dev.timeline_signal, src_dev.timeline_value - 1) \ - .wait(dest_dev.timeline_signal, dest_dev.timeline_value - 1) \ - .copy(dest.va_addr, src.va_addr, sz) \ - .signal(src_dev.timeline_signal, src_dev.next_timeline()).submit(src_dev) - - if src_dev != dest_dev: - dest_dev.hw_compute_queue_t().wait(src_dev.timeline_signal, src_dev.timeline_value - 1) \ - .wait(dest_dev.timeline_signal, dest_dev.timeline_value - 1) \ - .signal(dest_dev.timeline_signal, dest_dev.next_timeline()).submit(dest_dev) diff --git a/tinygrad/tinygrad/runtime/support/llvm.py b/tinygrad/tinygrad/runtime/support/llvm.py deleted file mode 100644 index bb1490e5..00000000 --- a/tinygrad/tinygrad/runtime/support/llvm.py +++ /dev/null @@ -1,25 +0,0 @@ -import ctypes, ctypes.util, os, sys, subprocess -from tinygrad.helpers import DEBUG, OSX, getenv - -if sys.platform == 'win32': - # Windows llvm distribution doesn't seem to add itself to PATH or anywhere else where it can be easily retrieved from. - # winget also doesn't have something like `brew --prefix llvm` so just hardcode default installation path with an option to override - LLVM_PATH = getenv('LLVM_PATH', 'C:\\Program Files\\LLVM\\bin\\LLVM-C.dll') - if not os.path.exists(LLVM_PATH): - raise FileNotFoundError('LLVM not found, you can install it with `winget install LLVM.LLVM` or point at a custom dll with LLVM_PATH') -elif OSX: - # Will raise FileNotFoundError if brew is not installed - # `brew --prefix` will return even if formula is not installed - if not os.path.exists(brew_prefix:=subprocess.check_output(['brew', '--prefix', 'llvm@19']).decode().strip()): - raise FileNotFoundError('LLVM not found, you can install it with `brew install llvm@19`') - LLVM_PATH: str|None = os.path.join(brew_prefix, 'lib', 'libLLVM.dylib') -else: - LLVM_PATH = ctypes.util.find_library('LLVM') - # use newer LLVM if possible - for ver in reversed(range(14, 19+1)): - if LLVM_PATH is not None: break - LLVM_PATH = ctypes.util.find_library(f'LLVM-{ver}') - if LLVM_PATH is None: - raise FileNotFoundError("No LLVM library found on the system. Install it via your distro's package manager and ensure it's findable as 'LLVM'") - -if DEBUG>=3: print(f'Using LLVM at {repr(LLVM_PATH)}') diff --git a/tinygrad/tinygrad/runtime/support/usb.py b/tinygrad/tinygrad/runtime/support/usb.py deleted file mode 100644 index 09b49204..00000000 --- a/tinygrad/tinygrad/runtime/support/usb.py +++ /dev/null @@ -1,268 +0,0 @@ -import ctypes, struct, dataclasses, array, itertools -from typing import Sequence -from tinygrad.runtime.autogen import libusb -from tinygrad.helpers import DEBUG, to_mv, round_up, OSX -from tinygrad.runtime.support.hcq import MMIOInterface - -class USB3: - def __init__(self, vendor:int, dev:int, ep_data_in:int, ep_stat_in:int, ep_data_out:int, ep_cmd_out:int, max_streams:int=31): - self.vendor, self.dev = vendor, dev - self.ep_data_in, self.ep_stat_in, self.ep_data_out, self.ep_cmd_out = ep_data_in, ep_stat_in, ep_data_out, ep_cmd_out - self.max_streams = max_streams - self.ctx = ctypes.POINTER(libusb.struct_libusb_context)() - - if libusb.libusb_init(ctypes.byref(self.ctx)): raise RuntimeError("libusb_init failed") - if DEBUG >= 6: libusb.libusb_set_option(self.ctx, libusb.LIBUSB_OPTION_LOG_LEVEL, 4) - - self.handle = libusb.libusb_open_device_with_vid_pid(self.ctx, self.vendor, self.dev) - if not self.handle: raise RuntimeError(f"device {self.vendor:04x}:{self.dev:04x} not found. sudo required?") - - # Detach kernel driver if needed - if libusb.libusb_kernel_driver_active(self.handle, 0): - libusb.libusb_detach_kernel_driver(self.handle, 0) - libusb.libusb_reset_device(self.handle) - - # Set configuration and claim interface - if libusb.libusb_set_configuration(self.handle, 1): raise RuntimeError("set_configuration failed") - if libusb.libusb_claim_interface(self.handle, 0): raise RuntimeError("claim_interface failed. sudo required?") - if libusb.libusb_set_interface_alt_setting(self.handle, 0, 1): raise RuntimeError("alt_setting failed") - - # Clear any stalled endpoints - all_eps = (self.ep_data_out, self.ep_data_in, self.ep_stat_in, self.ep_cmd_out) - for ep in all_eps: libusb.libusb_clear_halt(self.handle, ep) - - # Allocate streams - stream_eps = (ctypes.c_uint8 * 3)(self.ep_data_out, self.ep_data_in, self.ep_stat_in) - if (rc:=libusb.libusb_alloc_streams(self.handle, self.max_streams * len(stream_eps), stream_eps, len(stream_eps))) < 0: - raise RuntimeError(f"alloc_streams failed: {rc}") - - # Base cmd - cmd_template = bytes([0x01, 0x00, 0x00, 0x01, *([0] * 12), 0xE4, 0x24, 0x00, 0xB2, 0x1A, 0x00, 0x00, 0x00, *([0] * 8)]) - - # Init pools - self.tr = {ep: [libusb.libusb_alloc_transfer(0) for _ in range(self.max_streams)] for ep in all_eps} - - self.buf_cmd = [(ctypes.c_uint8 * len(cmd_template))(*cmd_template) for _ in range(self.max_streams)] - self.buf_stat = [(ctypes.c_uint8 * 64)() for _ in range(self.max_streams)] - self.buf_data_in = [(ctypes.c_uint8 * 0x1000)() for _ in range(self.max_streams)] - self.buf_data_out = [(ctypes.c_uint8 * 0x80000)() for _ in range(self.max_streams)] - self.buf_data_out_mvs = [to_mv(ctypes.addressof(self.buf_data_out[i]), 0x80000) for i in range(self.max_streams)] - - for slot in range(self.max_streams): struct.pack_into(">B", self.buf_cmd[slot], 3, slot + 1) - - def _prep_transfer(self, tr, ep, stream_id, buf, length): - tr.contents.dev_handle, tr.contents.endpoint, tr.contents.length, tr.contents.buffer = self.handle, ep, length, buf - tr.contents.status, tr.contents.flags, tr.contents.timeout, tr.contents.num_iso_packets = 0xff, 0, 1000, 0 - tr.contents.type = (libusb.LIBUSB_TRANSFER_TYPE_BULK_STREAM if stream_id is not None else libusb.LIBUSB_TRANSFER_TYPE_BULK) - if stream_id is not None: libusb.libusb_transfer_set_stream_id(tr, stream_id) - return tr - - def _submit_and_wait(self, cmds): - for tr in cmds: libusb.libusb_submit_transfer(tr) - - running = len(cmds) - while running: - libusb.libusb_handle_events(self.ctx) - running = len(cmds) - for tr in cmds: - if tr.contents.status == libusb.LIBUSB_TRANSFER_COMPLETED: running -= 1 - elif tr.contents.status != 0xFF: raise RuntimeError(f"EP 0x{tr.contents.endpoint:02X} error: {tr.contents.status}") - - def send_batch(self, cdbs:list[bytes], idata:list[int]|None=None, odata:list[bytes|None]|None=None) -> list[bytes|None]: - idata, odata = idata or [0] * len(cdbs), odata or [None] * len(cdbs) - results, tr_window, op_window = [], [], [] - - for idx, (cdb, rlen, send_data) in enumerate(zip(cdbs, idata, odata)): - # allocate slot and stream. stream is 1-based - slot, stream = idx % self.max_streams, (idx % self.max_streams) + 1 - - # build cmd packet - self.buf_cmd[slot][16:16+len(cdb)] = list(cdb) - - # cmd + stat transfers - tr_window.append(self._prep_transfer(self.tr[self.ep_cmd_out][slot], self.ep_cmd_out, None, self.buf_cmd[slot], len(self.buf_cmd[slot]))) - tr_window.append(self._prep_transfer(self.tr[self.ep_stat_in][slot], self.ep_stat_in, stream, self.buf_stat[slot], 64)) - - if rlen: - if rlen > len(self.buf_data_in[slot]): self.buf_data_in[slot] = (ctypes.c_uint8 * round_up(rlen, 0x1000))() - tr_window.append(self._prep_transfer(self.tr[self.ep_data_in][slot], self.ep_data_in, stream, self.buf_data_in[slot], rlen)) - - if send_data is not None: - if len(send_data) > len(self.buf_data_out[slot]): - self.buf_data_out[slot] = (ctypes.c_uint8 * len(send_data))() - self.buf_data_out_mvs[slot] = to_mv(ctypes.addressof(self.buf_data_out[slot]), len(send_data)) - - self.buf_data_out_mvs[slot][:len(send_data)] = bytes(send_data) - tr_window.append(self._prep_transfer(self.tr[self.ep_data_out][slot], self.ep_data_out, stream, self.buf_data_out[slot], len(send_data))) - - op_window.append((idx, slot, rlen)) - if (idx + 1 == len(cdbs)) or len(op_window) >= self.max_streams: - self._submit_and_wait(tr_window) - for idx, slot, rlen in op_window: results.append(bytes(self.buf_data_in[slot][:rlen]) if rlen else None) - tr_window = [] - - return results - -@dataclasses.dataclass(frozen=True) -class WriteOp: addr:int; data:bytes; ignore_cache:bool=True # noqa: E702 - -@dataclasses.dataclass(frozen=True) -class ReadOp: addr:int; size:int # noqa: E702 - -@dataclasses.dataclass(frozen=True) -class ScsiWriteOp: data:bytes; lba:int=0 # noqa: E702 - -class ASM24Controller: - def __init__(self): - self.usb = USB3(0xADD1, 0x0001, 0x81, 0x83, 0x02, 0x04) - self._cache: dict[int, int|None] = {} - self._pci_cacheable: list[tuple[int, int]] = [] - self._pci_cache: dict[int, int|None] = {} - - # Init controller. - self.exec_ops([WriteOp(0x54b, b' '), WriteOp(0x54e, b'\x04'), WriteOp(0x5a8, b'\x02'), WriteOp(0x5f8, b'\x04'), - WriteOp(0x7ec, b'\x01\x00\x00\x00'), WriteOp(0xc422, b'\x02'), WriteOp(0x0, b'\x33')]) - - def exec_ops(self, ops:Sequence[WriteOp|ReadOp|ScsiWriteOp]): - cdbs:list[bytes] = [] - idata:list[int] = [] - odata:list[bytes|None] = [] - - def _add_req(cdb:bytes, i:int, o:bytes|None): - nonlocal cdbs, idata, odata - cdbs, idata, odata = cdbs + [cdb], idata + [i], odata + [o] - - for op in ops: - if isinstance(op, WriteOp): - for off, value in enumerate(op.data): - addr = ((op.addr + off) & 0x1FFFF) | 0x500000 - if not op.ignore_cache and self._cache.get(addr) == value: continue - _add_req(struct.pack('>BBBHB', 0xE5, value, addr >> 16, addr & 0xFFFF, 0), 0, None) - self._cache[addr] = value - elif isinstance(op, ReadOp): - assert op.size <= 0xff - addr = (op.addr & 0x1FFFF) | 0x500000 - _add_req(struct.pack('>BBBHB', 0xE4, op.size, addr >> 16, addr & 0xFFFF, 0), op.size, None) - for i in range(op.size): self._cache[addr + i] = None - elif isinstance(op, ScsiWriteOp): - sectors = round_up(len(op.data), 512) // 512 - _add_req(struct.pack('>BBQIBB', 0x8A, 0, op.lba, sectors, 0, 0), 0, op.data+b'\x00'*((sectors*512)-len(op.data))) - - return self.usb.send_batch(cdbs, idata, odata) - - def write(self, base_addr:int, data:bytes, ignore_cache:bool=True): return self.exec_ops([WriteOp(base_addr, data, ignore_cache)]) - - def scsi_write(self, buf:bytes, lba:int=0): - if len(buf) > 0x4000: buf += b'\x00' * (round_up(len(buf), 0x10000) - len(buf)) - - for i in range(0, len(buf), 0x10000): - self.exec_ops([ScsiWriteOp(buf[i:i+0x10000], lba), WriteOp(0x171, b'\xff\xff\xff', ignore_cache=True)]) - self.exec_ops([WriteOp(0xce6e, b'\x00\x00', ignore_cache=True)]) - - if len(buf) > 0x4000: - for i in range(4): self.exec_ops([WriteOp(0xce40 + i, b'\x00', ignore_cache=True)]) - - def read(self, base_addr:int, length:int, stride:int=0xff) -> bytes: - parts = self.exec_ops([ReadOp(base_addr + off, min(stride, length - off)) for off in range(0, length, stride)]) - return b''.join(p or b'' for p in parts)[:length] - - def _is_pci_cacheable(self, addr:int) -> bool: return any(x <= addr <= x + sz for x, sz in self._pci_cacheable) - def pcie_prep_request(self, fmt_type:int, address:int, value:int|None=None, size:int=4) -> list[WriteOp]: - if fmt_type == 0x60 and size == 4 and self._is_pci_cacheable(address) and self._pci_cache.get(address) == value: return [] - - assert fmt_type >> 8 == 0 and size > 0 and size <= 4, f"Invalid fmt_type {fmt_type} or size {size}" - if DEBUG >= 3: print("pcie_request", hex(fmt_type), hex(address), value, size) - - masked_address, offset = address & 0xFFFFFFFC, address & 0x3 - assert size + offset <= 4 and (value is None or value >> (8 * size) == 0) - self._pci_cache[address] = value if size == 4 and fmt_type == 0x60 else None - - return ([WriteOp(0xB220, struct.pack('>I', value << (8 * offset)), ignore_cache=False)] if value is not None else []) + \ - [WriteOp(0xB218, struct.pack('>I', masked_address), ignore_cache=False), WriteOp(0xB21c, struct.pack('>I', address>>32), ignore_cache=False), - WriteOp(0xB217, bytes([((1 << size) - 1) << offset]), ignore_cache=False), WriteOp(0xB210, bytes([fmt_type]), ignore_cache=False), - WriteOp(0xB254, b"\x0f", ignore_cache=True), WriteOp(0xB296, b"\x04", ignore_cache=True)] - - def pcie_request(self, fmt_type, address, value=None, size=4, cnt=10): - self.exec_ops(self.pcie_prep_request(fmt_type, address, value, size)) - - # Fast path for write requests - if ((fmt_type & 0b11011111) == 0b01000000) or ((fmt_type & 0b10111000) == 0b00110000): return - - while (stat:=self.read(0xB296, 1)[0]) & 2 == 0: - if stat & 1: - self.write(0xB296, bytes([0x01])) - if cnt > 0: return self.pcie_request(fmt_type, address, value, size, cnt=cnt-1) - assert stat == 2, f"stat read 2 was {stat}" - - # Retrieve completion data from Link Status (0xB22A, 0xB22B) - b284 = self.read(0xB284, 1)[0] - completion = struct.unpack('>H', self.read(0xB22A, 2)) - - # Validate completion status based on PCIe request typ - # Completion TLPs for configuration requests always have a byte count of 4. - assert completion[0] & 0xfff == (4 if (fmt_type & 0xbe == 0x04) else size) - - # Extract completion status field - status = (completion[0] >> 13) & 0x7 - - # Handle completion errors or inconsistencies - if status or ((fmt_type & 0xbe == 0x04) and (((value is None) and (not (b284 & 0x01))) or ((value is not None) and (b284 & 0x01)))): - status_map = {0b001: f"Unsupported Request: invalid address/function (target might not be reachable): {address:#x}", - 0b100: "Completer Abort: abort due to internal error", 0b010: "Configuration Request Retry Status: configuration space busy"} - raise RuntimeError(f"TLP status: {status_map.get(status, 'Reserved (0b{:03b})'.format(status))}") - - if value is None: return (struct.unpack('>I', self.read(0xB220, 4))[0] >> (8 * (address & 0x3))) & ((1 << (8 * size)) - 1) - - def pcie_cfg_req(self, byte_addr, bus=1, dev=0, fn=0, value=None, size=4): - assert byte_addr >> 12 == 0 and bus >> 8 == 0 and dev >> 5 == 0 and fn >> 3 == 0, f"Invalid byte_addr {byte_addr}, bus {bus}, dev {dev}, fn {fn}" - - fmt_type = (0x44 if value is not None else 0x4) | int(bus > 0) - address = (bus << 24) | (dev << 19) | (fn << 16) | (byte_addr & 0xfff) - return self.pcie_request(fmt_type, address, value, size) - - def pcie_mem_req(self, address, value=None, size=4): return self.pcie_request(0x60 if value is not None else 0x20, address, value, size) - - def pcie_mem_write(self, address, values, size): - ops = [self.pcie_prep_request(0x60, address + i * size, value, size) for i, value in enumerate(values)] - - # Send in batches of 4 for OSX and 16 for Linux (benchmarked values) - for i in range(0, len(ops), bs:=(4 if OSX else 16)): self.exec_ops(list(itertools.chain.from_iterable(ops[i:i+bs]))) - -class USBMMIOInterface(MMIOInterface): - def __init__(self, usb, addr, size, fmt, pcimem=True): - self.usb, self.addr, self.nbytes, self.fmt, self.pcimem, self.el_sz = usb, addr, size, fmt, pcimem, struct.calcsize(fmt) - - def __getitem__(self, index): return self._access_items(index) - def __setitem__(self, index, val): self._access_items(index, val) - - def _access_items(self, index, val=None): - if isinstance(index, slice): return self._acc((index.start or 0) * self.el_sz, ((index.stop or len(self))-(index.start or 0)) * self.el_sz, val) - return self._acc_one(index * self.el_sz, self.el_sz, val) if self.pcimem else self._acc(index * self.el_sz, self.el_sz, val) - - def view(self, offset:int=0, size:int|None=None, fmt=None): - return USBMMIOInterface(self.usb, self.addr+offset, size or (self.nbytes - offset), fmt=fmt or self.fmt, pcimem=self.pcimem) - - def _acc_size(self, sz): return next(x for x in [('I', 4), ('H', 2), ('B', 1)] if sz % x[1] == 0) - - def _acc_one(self, off, sz, val=None): - upper = 0 if sz < 8 else self.usb.pcie_mem_req(self.addr + off + 4, val if val is None else (val >> 32), 4) - lower = self.usb.pcie_mem_req(self.addr + off, val if val is None else val & 0xffffffff, min(sz, 4)) - if val is None: return lower | (upper << 32) - - def _acc(self, off, sz, data=None): - if data is None: # read op - if not self.pcimem: - return int.from_bytes(self.usb.read(self.addr + off, sz), "little") if sz == self.el_sz else self.usb.read(self.addr + off, sz) - - acc, acc_size = self._acc_size(sz) - return bytes(array.array(acc, [self._acc_one(off + i * acc_size, acc_size) for i in range(sz // acc_size)])) - else: # write op - data = struct.pack(self.fmt, data) if isinstance(data, int) else bytes(data) - - if not self.pcimem: - # Fast path for writing into buffer 0xf000 - use_cache = 0xa800 <= self.addr <= 0xb000 - return self.usb.scsi_write(bytes(data)) if self.addr == 0xf000 else self.usb.write(self.addr + off, bytes(data), ignore_cache=not use_cache) - - _, acc_sz = self._acc_size(len(data) * struct.calcsize(self.fmt)) - self.usb.pcie_mem_write(self.addr+off, [int.from_bytes(data[i:i+acc_sz], "little") for i in range(0, len(data), acc_sz)], acc_sz) diff --git a/tinygrad/tinygrad/runtime/support/webgpu.py b/tinygrad/tinygrad/runtime/support/webgpu.py deleted file mode 100644 index 24fb75c7..00000000 --- a/tinygrad/tinygrad/runtime/support/webgpu.py +++ /dev/null @@ -1,11 +0,0 @@ -import ctypes, ctypes.util, os, subprocess -from tinygrad.helpers import OSX - -if OSX: - if not os.path.exists(brew_prefix:=subprocess.check_output(['brew', '--prefix', 'dawn']).decode().strip()): - raise FileNotFoundError('dawn library not found. Install it with `brew tap wpmed92/dawn && brew install dawn`') - WEBGPU_PATH: str|None = os.path.join(brew_prefix, 'lib', 'libwebgpu_dawn.dylib') -else: - if (WEBGPU_PATH:=ctypes.util.find_library('webgpu_dawn')) is None: - raise FileNotFoundError("dawn library not found. " + - "Install it with `sudo curl -L https://github.com/wpmed92/pydawn/releases/download/v0.1.6/libwebgpu_dawn.so -o /usr/lib/libwebgpu_dawn.so`") diff --git a/tinygrad/tinygrad/shape/__init__.py b/tinygrad/tinygrad/shape/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/tinygrad/tinygrad/shape/shapetracker.py b/tinygrad/tinygrad/shape/shapetracker.py deleted file mode 100644 index 031fb64e..00000000 --- a/tinygrad/tinygrad/shape/shapetracker.py +++ /dev/null @@ -1,140 +0,0 @@ -# ShapeTracker allows movement operations to a buffer that don't require a copy to be made. -from __future__ import annotations -from dataclasses import dataclass -import functools -from typing import Optional, Callable -from tinygrad.helpers import merge_dicts, getenv -from tinygrad.shape.view import View, strides_for_shape, unravel -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import UOp, Ops, graph_rewrite, Variable, sint, sint_to_uop, Context, PatternMatcher, UPat, GroupOp -from tinygrad.codegen.symbolic import split_uop, symbolic_flat, uop_given_valid, simplify_valid - -# If a node overflow, its srcs need to be checked to see if this overflow is the result of an ALU operation, -# or that the node simply inherits the dtype from srcs. Upcast is either `Ops.CAST`+`replace` or just `replace`. -def handle_upcast(u: UOp) -> UOp|None: - dtype = dtypes.int64.vec(u.dtype.count) if u.dtype.count > 1 else dtypes.int64 - # check for overflow, upcast this to int64 - if u.vmax > dtypes.max(dtypes.int) or u.vmin < dtypes.min(dtypes.int): - return u.replace(dtype=dtype, src=tuple([x.cast(dtype) for x in u.src])) - # if any inputs are int64 and this *doesn't* overflow, cast back to int - if any(x.dtype == dtypes.int64 for x in u.src): - return u.replace(dtype=dtype, src=tuple([x.cast(dtype) for x in u.src])).cast(u.dtype) - return None -pm_upcast = PatternMatcher([(UPat(GroupOp.ALU, dtype=dtypes.int, name="u"), handle_upcast),]) - -@functools.cache -def views_to_indexed_uops(views: tuple[View, ...], _idxs:Optional[tuple[UOp, ...]]=None) -> tuple[UOp, UOp]: - idx, valid = views[-1].to_indexed_uops(_idxs) - for view in reversed(views[0:-1]): - view = view.minify() - idx, valid = view.to_indexed_uops([sint_to_uop(i) for i in unravel(view.shape, idx)], valid) - # symbolic - idx, valid = graph_rewrite(UOp.sink(idx, valid), symbolic_flat, name="indexing sym @ 1").src - # simplify - if (newvalid:=simplify_valid(valid)) is not None: valid = newvalid - if (newidx:=uop_given_valid(valid, idx)) is not None: idx = newidx - # symbolic again, upcast if needed - return graph_rewrite(UOp.sink(idx, valid), symbolic_flat+pm_upcast, name="indexing sym @ 2").src - -@functools.cache -def views_to_real_strides(views: tuple[View, ...], ignore_valid=False) -> tuple[Optional[sint], ...]: - # NOTE: if a stride is not always valid, it will be None - if len(views) == 1 and views[-1].mask is None: return views[-1].strides - ret: list[Optional[sint]] = [None] * len(views[-1].shape) - idx, valid = views_to_indexed_uops(views) - for c in split_uop(idx, Ops.ADD): - if c.op is Ops.RANGE: ret[c.arg] = 1 - if c.op is Ops.MUL and c.src[0].op is Ops.RANGE and c.src[1].op is Ops.CONST: ret[c.src[0].arg] = c.src[1].arg - if c.op is Ops.MUL and c.src[1].op is Ops.RANGE and c.src[0].op is Ops.CONST: ret[c.src[1].arg] = c.src[0].arg - used_ranges = [x.arg for x in idx.toposort() if x.op is Ops.RANGE] - ret = [x if i in used_ranges else 0 for i,x in enumerate(ret)] - if not ignore_valid: - for masked_axis in [x.arg for x in valid.toposort() if x.op is Ops.RANGE]: ret[masked_axis] = None - return tuple(ret) - -@dataclass(frozen=True, order=True) -class ShapeTracker: - views: tuple[View, ...] - - def __add__(self, st:ShapeTracker) -> ShapeTracker: - ret = self - for v in st.views: ret = ShapeTracker(ret.views + (v,)).simplify() # one view at a time = better simplification - return ret - - def invert(self, out_shape:tuple[sint, ...]) -> Optional[ShapeTracker]: - inverted_views:list[View] = [] - for v,s in zip(self.views[::-1], [x.shape for x in self.views[::-1][1:]]+[out_shape]): - if (inverted:= v.invert(s)) is None: return None - inverted_views.append(inverted) - return ShapeTracker(tuple(inverted_views)).reshape(out_shape) - - @staticmethod - def from_shape(shape:tuple[sint, ...], strides:tuple[sint, ...]|None=None) -> ShapeTracker: return ShapeTracker((View.create(shape, strides),)) - - @property - def contiguous(self) -> bool: return len(self.views) == 1 and self.views[0].contiguous - - @property - def consecutive(self) -> bool: return len(self.views) == 1 and (v:=self.views[0]).mask is None and v.strides == strides_for_shape(v.shape) - - @property - def shape(self) -> tuple[sint, ...]: return self.views[-1].shape - - @property - def size(self) -> int: return self.views[-1].size() - - def reduce(self, axis:tuple[int, ...]) -> tuple[sint, ...]: return tuple(1 if i in axis else s for i,s in enumerate(self.shape)) - - def to_uop(self) -> UOp: return UOp(Ops.VIEW, dtypes.void, (), self) - def to_indexed_uops(self, _idxs:Optional[list[UOp]|tuple[UOp, ...]]=None) -> tuple[UOp, UOp]: - return views_to_indexed_uops(self.views, tuple(_idxs) if _idxs is not None else None) - - # upper bound on buffer size required to fit this shapetracker - def real_size(self) -> int: - if 0 in self.shape: return 0 - view = (v.shrink(v.mask) if (v:=self.views[0]).mask else v) - idx, _ = views_to_indexed_uops((view,)) - assert idx.vmax < 1e12, f"real_size broken for {self}" - return int(idx.vmax + 1) - - def vars(self) -> set[Variable]: return set().union(*[v.vars() for v in self.views]) - - @property - def var_vals(self) -> dict[Variable, int]: return merge_dicts([dict([v.unbind()]) for v in self.vars()]) - - def unbind(self) -> tuple[ShapeTracker, dict[Variable, int]]: - unbound_views, var_vals = zip(*[v.unbind() for v in self.views]) - if all(len(x) == 0 for x in var_vals): return self, {} - return ShapeTracker(tuple(unbound_views)), merge_dicts(var_vals) - def substitute(self, dvars:dict[UOp, UOp]): return ShapeTracker(tuple(x.substitute(dvars) for x in self.views)) - - def real_strides(self, ignore_valid=False) -> tuple[Optional[sint], ...]: - with Context(TRACK_MATCH_STATS=0): return views_to_real_strides(self.views, ignore_valid) - def unit_stride_axes(self, ignore_valid=False) -> list[int]: return [i for i,st in enumerate(self.real_strides(ignore_valid)) if st == 1] - - def axis_is_masked(self, axis:int) -> bool: - with Context(TRACK_MATCH_STATS=0): - _, valid = self.to_indexed_uops() - return axis in [x.arg for x in graph_rewrite(valid, symbolic_flat).toposort() if x.op is Ops.RANGE] - - def simplify(self) -> ShapeTracker: - if len(self.views) >= 2 and (new_view := self.views[-2] + self.views[-1]) is not None: - return ShapeTracker(self.views[:-2] + (new_view,)).simplify() - return self - - # *** under this line are the movement ops *** - - def pad(self, arg: tuple[tuple[sint, sint], ...]) -> ShapeTracker: return ShapeTracker(self.views[0:-1] + (self.views[-1].pad(arg), )) - def shrink(self, arg: tuple[tuple[sint, sint], ...]) -> ShapeTracker: return ShapeTracker(self.views[0:-1] + (self.views[-1].shrink(arg), )) - def expand(self, new_shape: tuple[sint, ...]) -> ShapeTracker: return ShapeTracker(self.views[0:-1] + (self.views[-1].expand(new_shape), )) - def permute(self, axis: tuple[int, ...]) -> ShapeTracker: return ShapeTracker(self.views[0:-1] + (self.views[-1].permute(axis), )) - def flip(self, mul: tuple[int, ...]) -> ShapeTracker: return ShapeTracker(self.views[0:-1] + (self.views[-1].flip(mul), )) - - def reshape(self, new_shape: tuple[sint, ...]) -> ShapeTracker: - if getenv("MERGE_VIEW", 1) and (new_view := self.views[-1].reshape(new_shape)) is not None: return ShapeTracker(self.views[0:-1] + (new_view,)) - return ShapeTracker(self.views + (View.create(new_shape), )) - - def mop(self, op, arg): return mops[op](self, arg) - -mops: dict[Ops, Callable] = {Ops.RESHAPE: ShapeTracker.reshape, Ops.PERMUTE: ShapeTracker.permute, Ops.EXPAND: ShapeTracker.expand, - Ops.SHRINK: ShapeTracker.shrink, Ops.FLIP: ShapeTracker.flip, Ops.PAD: ShapeTracker.pad} diff --git a/tinygrad/tinygrad/shape/view.py b/tinygrad/tinygrad/shape/view.py deleted file mode 100644 index 5351ce47..00000000 --- a/tinygrad/tinygrad/shape/view.py +++ /dev/null @@ -1,322 +0,0 @@ -from __future__ import annotations -import functools, operator, itertools -from dataclasses import dataclass -from typing import Optional, cast, Sequence -from tinygrad.dtype import dtypes -from tinygrad.uop.ops import resolve, UOp, Variable, sint, sym_infer, smax, smin, sint_to_uop, Ops, ssimplify -from tinygrad.helpers import prod, all_int, argsort, flatten, ceildiv - -@functools.cache -def canonicalize_strides(shape:tuple[sint, ...], strides:tuple[sint, ...]) -> tuple[sint, ...]: - return tuple(0 if s == 1 else st for s, st in zip(shape, strides)) - -@functools.cache -def strides_for_shape(shape:tuple[sint, ...]) -> tuple[sint, ...]: - if not shape: return () - strides = tuple(itertools.accumulate(reversed(shape[1:]), operator.mul, initial=1))[::-1] - return canonicalize_strides(shape, strides) - -@functools.cache -def merge_dims(shape:tuple[int, ...], strides:tuple[int, ...], mask:Optional[tuple[tuple[int, int], ...]]=None) -> tuple[tuple[int, int, int], ...]: - # merge contiguous sub-parts or zero strided dims - # any stride 0, masked from dim=1, or contiguous part is merged into next dim. - # stride != 0 to stride == 0 starts a new merging block - # ret = tuple[(merged_size, stride, merged size w/o zero stride), ...] - if not shape: return () - assert len(shape) == len(strides) and (mask is None or len(shape) == len(mask)) - ret = [(shape[0], strides[0], shape[0] if strides[0] != 0 else 0)] - # merge this dim to next dim if size is 1 - merging = (mask[0][1] - mask[0][0] == 1) if mask is not None else shape[0] == 1 - for i, (s, st) in enumerate(zip(shape[1:], strides[1:]), start=1): - # always merge 1 - if s == 1: continue - last_s, last_st, last_pre_expand_s = ret[-1] - # merge last dim with this dim if merging or strides matched - if merging or last_st == s * st: ret[-1] = (last_s * s, st, (s if merging else last_pre_expand_s * s)) - else: ret.append((s, st, s)) - # merge this dim to next dim if size is 1 - merging = (mask[i][1] - mask[i][0] == 1) if mask is not None else s == 1 - return tuple(ret) - -@functools.cache -def _reshape_mask(_mask:Optional[tuple[tuple[sint, sint], ...]], old_shape:tuple[sint, ...], new_shape:tuple[sint, ...]) \ - -> Optional[tuple[tuple[sint, sint], ...]]: - """Returns the new mask if reshape is possible, and None if not possible.""" - if _mask is None: return tuple((0, s) for s in new_shape) - if not all_int(flatten(_mask)): return None - - new_mask: list[tuple[int, int]] = [] - # _mask is all int here - r_masks, r_shape, r_new_shape = reversed(cast(tuple[tuple[int, int], ...], _mask)), reversed(old_shape), reversed(new_shape) - curr_stride, old_dim, new_dim, mask = 1, next(r_shape, 1), next(r_new_shape, 1), next(r_masks, (0,1)) - - while len(new_mask) < len(new_shape): - (l, r), next_stride = mask, ssimplify(new_dim * curr_stride) - - # need to split mask - if old_dim == next_stride: # simply copy the mask and get next batch for merging - new_mask.append((l // curr_stride, (r - 1) // curr_stride + 1)) - curr_stride, old_dim, new_dim, mask = 1, next(r_shape, 1), next(r_new_shape, 1), next(r_masks, (0,1)) - elif old_dim > next_stride: # mask can only be splitted if reshape doesn't cut across the mask. - if old_dim % next_stride != 0: return None - if (l % next_stride != 0 or r % next_stride != 0) and l // next_stride != (r - 1) // next_stride: return None - new_mask.append((l % next_stride // curr_stride, (r - 1) % next_stride // curr_stride + 1)) - curr_stride, new_dim = next_stride, next(r_new_shape, 1) # need to get mask for next dimension - else: - next_mask = next(r_masks, (0, 1)) - # combine if the mask can unfold continuously - if mask != (0, old_dim) and l != r and next_mask[1] - next_mask[0] != 1: return None - mask, old_dim = (next_mask[0] * old_dim + l, (next_mask[1] - 1) * old_dim + r), ssimplify(old_dim * next(r_shape, 1)) - - return tuple(reversed(new_mask)) - -def unravel(shape:tuple[sint, ...], offset:sint) -> list[sint]: - # find the position of offset on each dimension based on shape - # similar to unravel_index in numpy/torch - acc, idxs = 1, [] - for d in reversed(shape): - idxs.append((offset//acc)%d) - acc *= d - return idxs[::-1] - -@dataclass(frozen=True) -class View: - shape:tuple[sint, ...] - strides:tuple[sint, ...] - offset:sint - mask:Optional[tuple[tuple[sint, sint], ...]] - contiguous:bool - - def to_indexed_uops(self:View, idxs:Optional[Sequence[UOp]]=None, vexpr:UOp=UOp.const(dtypes.bool, True)) -> tuple[UOp, UOp]: - """(idx, valid)""" - if idxs is None: idxs = [UOp.range(dtypes.int, s, i) for i,s in enumerate(self.shape)] - iexpr = sint_to_uop(self.offset) - for idx,sh,st,m in zip(idxs, self.shape, self.strides, self.mask if self.mask is not None else itertools.repeat(None)): - if resolve(sh != 1) and resolve(st != 0): iexpr = iexpr + idx*st - if m is not None: - if resolve(m[0] != 0): vexpr = vexpr * (idx >= m[0]) - if resolve(m[1] != sh): vexpr = vexpr * (idx < m[1]) - return iexpr, vexpr - - @functools.cache # pylint: disable=method-cache-max-size-none - def size(self) -> int: - ret = prod([x.vmax if isinstance(x, UOp) else x for x in self.shape]) - assert isinstance(ret, int), f"{ret=} is not int" - return ret - - @staticmethod - @functools.cache - def create(shape:tuple[sint, ...], strides:Optional[tuple[sint, ...]]=None, offset:sint=0, mask:Optional[tuple[tuple[sint, sint], ...]]=None): - # TODO: resolve shouldn't be needed here - if not all(resolve(s >= 0) for s in shape): raise ValueError(f"Trying to create View with negative dimension: {shape=}") - strides = canonicalize_strides(shape, strides) if strides else strides_for_shape(shape) - # canonicalize 0 in shape - if 0 in shape: return View(shape, (0,) * len(shape), offset=0, mask=None, contiguous=True) - # canonicalize no-op mask - if mask is not None and all(m == (0,s) for m,s in zip(mask, shape)): mask = None - # if any dimension has size >1, but is masked such that only one index in the dimension is unmasked - # then its stride can also be set to 0, albeit with a corresponding adjustment required to the offset - if mask and any(elim := [not resolve(b+1 < e) for b,e in mask]): - if any(not resolve(b < e) for b,e in mask): - strides, offset, mask = (0,) * len(shape), 0, ((0,0),) * len(shape) - offset += sum((strides[i] * mask[i][0]) if e else 0 for i, e in enumerate(elim)) - strides = tuple(0 if e else st for st,e in zip(strides, elim)) - # simplify as we go - if isinstance(offset, UOp): offset = cast(sint, offset.ssimplify()) - shape = tuple(cast(sint, x.ssimplify()) if isinstance(x, UOp) else x for x in shape) - # TODO: enabling stride simplification breaks symbolic jit - """ - strides = tuple(x.ssimplify() if isinstance(x, UOp) else x for x in strides) - if mask: mask = tuple((s.ssimplify() if isinstance(s, UOp) else s, e.ssimplify() if isinstance(e, UOp) else e) for s,e in mask) - """ - contiguous = offset == 0 and mask is None and strides == strides_for_shape(shape) - return View(shape, strides, offset, mask, contiguous) - - @functools.cache # pylint: disable=method-cache-max-size-none - def vars(self) -> set[Variable]: - flatten_mask = tuple(x for m in self.mask for x in m) if self.mask is not None else tuple() - return functools.reduce(operator.or_, [x.vars() for x in self.shape+self.strides+(self.offset,)+flatten_mask if isinstance(x, UOp)], set()) - - @functools.cache # pylint: disable=method-cache-max-size-none - def unbind(self) -> tuple[View, dict[Variable, int]]: - var_unboundvar_val = [(v, v.unbind()) for v in self.vars() if v.op is Ops.BIND] - unbound_vars = {v:uv for v,(uv,_) in var_unboundvar_val} - return self.substitute(unbound_vars), dict(x[1] for x in var_unboundvar_val) - - def substitute(self, dvars:dict[UOp, UOp]): - def _substitute(x:sint): return x if isinstance(x, int) else x.substitute(dvars) - new_shape = tuple(map(_substitute, self.shape)) - new_strides = tuple(map(_substitute, self.strides)) - new_offset = _substitute(self.offset) - new_mask = tuple((_substitute(x[0]), _substitute(x[1])) for x in self.mask) if self.mask is not None else None - return View.create(new_shape, new_strides, new_offset, new_mask) - - @functools.cache # pylint: disable=method-cache-max-size-none - def __add__(self, vm1:View) -> Optional[View]: - vm2 = self - if vm2.contiguous: return vm1 - if vm1.contiguous and vm1.shape == vm2.shape: return vm2 - if vm1.contiguous and vm1.size() == vm2.size() and (ret := vm2.reshape(vm1.shape)) is not None: return ret - if vm1.mask: - if (new_vm1 := vm1.shrink(vm1.mask)) == vm1 or (merged := vm2 + new_vm1) is None: return None - return merged.pad(tuple((b,s-e) for (b,e),s in zip(vm1.mask, vm1.shape))) - if not all_int(vm1.shape): - # if all strides are 0 and vm2 is unmasked, return vm1 - if all(x == 0 for x in vm2.strides+vm1.strides) and vm2.mask is None: return vm1 - # TODO: handle more cases - return None - - # Project vm1's offset and strides on to vm2. - origin = unravel(vm2.shape, vm1.offset) - terms: list[list[tuple[int, sint]]] = [[] for _ in vm2.shape] - strides: list[sint] = [0] * len(vm1.shape) - for d1, st in enumerate(vm1.strides): - if st == 0: continue - for d2, (o, s1) in enumerate(zip(origin, unravel(vm2.shape, vm1.offset + st))): - if (s1 := s1 - o) == 0: continue - terms[d2].append((d1, s1)) - strides[d1] += s1 * vm2.strides[d2] - - # Merge dimensions in vm2 if required. - # NB: Merging too many dimensions can make it difficult to project vm2's mask, hence only combining when required. - idxs: list[UOp] = [UOp.variable(f"idx{i}", 0, s-1) for i,s in enumerate(vm1.shape)] - merged_size, merged_term = 1, UOp.const(dtypes.int, 0) - extents: list[tuple[sint, UOp]] = [] - for term, s, o in zip(reversed(terms), reversed(vm2.shape), reversed(origin)): - merged_term += (sum([idxs[d1] * s1 for d1, s1 in term]) + o) * merged_size - merged_size *= s - if resolve(merged_term < merged_size, False) and resolve(0 <= merged_term, False): - extents.append((merged_size, merged_term)) - merged_size, merged_term = 1, UOp.const(dtypes.int, 0) - if resolve(merged_term != 0): return None - if (vm2_shape := tuple(s for s,_ in reversed(extents))) != vm2.shape: - if (reshaped_vm2 := vm2.reshape(vm2_shape)) is None: return None - # NOTE: this != to prevent infinite loop - if reshaped_vm2.shape != vm2.shape: return reshaped_vm2 + vm1 - - if vm2.mask: - # Try to project vm2's mask on to vm1. - newb, newe, bad = [0] * len(vm1.shape), list(vm1.shape), False - for (b, e), o, term, (_, t) in zip(vm2.mask, origin, terms, reversed(extents)): - if resolve(b <= t.vmin and t.vmax < e, False): continue - if len(term) != 1: - if not term and newe: newe[0] = 0 - else: bad = True - continue - d1, s1 = term[0] - newb[d1] = smax(newb[d1], ceildiv(b - o if s1 > 0 else e - o - 1, s1)) - newe[d1] = smin(newe[d1], (b - o if s1 < 0 else e - o - 1) // s1 + 1) - - # If any of vm1 was masked off, try again with that mask in place. - if any((b, e) != (0, s) for b, e, s in zip(newb, newe, vm1.shape)): - return vm2 + View.create(vm1.shape, vm1.strides, vm1.offset, tuple(zip(newb, newe))) - # Otherwise if vm2's mask was violated, then cannot merge. - if bad: return None - - return View.create(vm1.shape, tuple(strides), sum(o * s for o, s in zip(origin, vm2.strides)) + vm2.offset) - - @functools.cache # pylint: disable=method-cache-max-size-none - def invert(self, out_shape:tuple[sint, ...]) -> Optional[View]: - ret = View.create(self.shape) - if self.mask: ret = ret.shrink(self.mask) - ret = ret.flip(tuple(x < 0 for x in self.strides)).permute(argsort(tuple(-x if x > 0 else x for x in self.strides))) - return ret if prod(ret.shape) == prod(out_shape) else None # don't support shrink, expand, or stride != (-1, 1) - - @functools.cache # pylint: disable=method-cache-max-size-none - def minify(self): - min_shape = tuple(x[0] for x in merge_dims(self.shape, self.strides, self.mask)) - return nv if (nv := self.reshape(min_shape)) else self - - def __unsafe_resize(self, arg: tuple[tuple[sint, sint], ...], mask=None) -> View: - offset = sum([s * x[0] for s, x in zip(self.strides,arg)]) - if self.mask: - # move the old mask - nmask = tuple([(smax(0, smin(mx-ax,ay-ax)), smax(0, smin(my-ax,ay-ax))) for (mx,my),(ax,ay) in zip(self.mask, arg)]) - # merge the masks if we have two - mask = tuple([(smax(mx1, mx2), smin(my1, my2)) for (mx1, my1), (mx2, my2) in zip(nmask, mask)]) if mask is not None else nmask - return View.create(tuple([y-x for x,y in arg]), self.strides, self.offset+offset, mask) - - @functools.cache # pylint: disable=method-cache-max-size-none - def pad(self, arg: tuple[tuple[sint, sint], ...]) -> View: - assert len(arg) == len(self.shape), f"invalid pad {arg} for {self.shape}" - # NOTE: not checking for symbolic arg - for b,e in arg: assert not all_int([b,e]) or b>=0 and e>=0, f"invalid pad {arg} for {self.shape}" - if any(resolve(b!=0) or resolve(e!=0) for b, e in arg): - zvarg = tuple([(-b,s+e) for s,(b,e) in zip(self.shape, arg)]) - mask = tuple([(b,s+b) for s,(b,_) in zip(self.shape, arg)]) - return self.__unsafe_resize(zvarg, mask=mask) - return self - - @functools.cache # pylint: disable=method-cache-max-size-none - def shrink(self, arg: tuple[tuple[sint, sint], ...]) -> View: - assert len(arg) == len(self.shape), f"invalid shrink {arg} for {self.shape}" - # NOTE: not checking for symbolic arg - for s,(b,e) in zip(self.shape,arg): assert not all_int([s,b,e]) or (0<=b<=e<=s), f"invalid shrink {arg} for {self.shape}" - return self.__unsafe_resize(arg) - - @functools.cache # pylint: disable=method-cache-max-size-none - def expand(self, new_shape: tuple[sint, ...]) -> View: - if len(new_shape) != len(self.shape): raise ValueError(f"expand arg {new_shape=} must have same number of dimensions as shape {self.shape=}") - # NOTE: does not check multiple of symbolic shape - assert all(resolve(s == ns) or s == 1 for s,ns in zip(self.shape, new_shape)), f"can't expand {self.shape} into {new_shape}" - if 0 in self.shape: return View.create(new_shape) - # TODO: resolve may not be needed, but it's hard because vars need to be canonicalized - mask = tuple([(((0,0) if m != (0,1) else (0,ns)) if resolve(s != ns) and resolve(s == 1, False) else m) \ - for m,s,ns in zip(self.mask, self.shape, new_shape)]) if self.mask else None - return View.create(new_shape, self.strides, self.offset, mask) - - @functools.cache # pylint: disable=method-cache-max-size-none - def permute(self, axis: tuple[int, ...]) -> View: - assert sorted(axis) == list(range(len(self.shape))), f"invalid permutation {axis} of len {len(self.shape)}" - return View.create(tuple(self.shape[a] for a in axis), tuple(self.strides[a] for a in axis), self.offset, - tuple(self.mask[a] for a in axis) if self.mask is not None else None) - - @functools.cache # pylint: disable=method-cache-max-size-none - def flip(self, arg: tuple[bool, ...]) -> View: - offset = sum((s-1)*z for s,z,f in zip(self.shape, self.strides, arg) if f) - mask = tuple((s-my,s-mx) if f else (mx,my) for (mx,my),s,f in zip(self.mask, self.shape, arg)) if self.mask is not None else None - return View.create(self.shape, tuple(-z if f else z for z,f in zip(self.strides, arg)), self.offset+offset, mask) - - @functools.cache # pylint: disable=method-cache-max-size-none - def reshape(self, new_shape: tuple[sint, ...]) -> Optional[View]: - if self.shape == new_shape: return self - - if not all(x >= 0 for x in new_shape): raise ValueError(f"shape can't contain negative numbers {new_shape}") - # check for the same size - if (self_all_int := all_int(self.shape)): - assert all(isinstance(s, (int, UOp)) for s in new_shape), f"{self.shape=} -> {new_shape=} contains non (int, Variable) dim" - if resolve(prod(self.shape) != prod(new_shape), False): raise ValueError(f"size mismatched, can't reshape {self.shape=} -> {new_shape=}") - - if 0 in self.shape: return View.create(new_shape) - if new_shape == () and self.mask and any(mx==my for (mx,my) in self.mask): return None - - # after the asserts, it's okay to check contiguous - if self.contiguous: return View.create(new_shape) - - # if it's not contiguous and new shape is symbolic, check if it's directly replaceable - if self_all_int and not all_int(new_shape): - if len(self.shape) != len(new_shape): raise ValueError(f"cannot symbolic reshape non-contiguous {self} -> {new_shape}") - for si, so in zip(self.shape, new_shape): - if not isinstance(so, int): so = sym_infer(so, dict([v.unbind() for v in so.vars()])) - if si != so: raise ValueError(f"cannot symbolic reshape non-contiguous {self} -> {new_shape}") - # all dimensions matched, return the new view directly - return View(new_shape, self.strides, self.offset, self.mask, self.contiguous) - - r_strides, r_new_shape = [], reversed(new_shape) - for merged_size, new_stride, real_size in reversed(merge_dims(self.shape, self.strides, self.mask)): - # TODO: write with get_contraction - acc = 1 - # TODO: third resolve shouldn't be needed - while resolve(acc <= merged_size) and resolve(acc != merged_size) and resolve((new_dim := next(r_new_shape, 0)) > 0): - r_strides.append(new_stride * acc) - acc = acc * new_dim - if not resolve(acc < real_size): new_stride = 0 - if resolve(acc != merged_size): return None - new_strides = (0,) * (len(new_shape) - len(r_strides)) + tuple(r_strides[::-1]) - - if (new_mask:=_reshape_mask(self.mask, self.shape, new_shape)) is not None: - extra_offset = (sum(m[0] * s for m,s in zip(self.mask, self.strides)) if self.mask else 0) - \ - (sum(m[0] * s for m,s in zip(new_mask, new_strides))) - return View.create(new_shape, new_strides, self.offset + extra_offset, new_mask) - - return None diff --git a/tinygrad/tinygrad/tensor.py b/tinygrad/tinygrad/tensor.py deleted file mode 100644 index 8d046b1a..00000000 --- a/tinygrad/tinygrad/tensor.py +++ /dev/null @@ -1,4315 +0,0 @@ -# inspired by https://github.com/karpathy/micrograd/blob/master/micrograd/engine.py -from __future__ import annotations -import time, math, itertools, functools, struct, sys, inspect, pathlib, string, hashlib, weakref, contextvars -from contextlib import ContextDecorator -from typing import Callable, ClassVar, Sequence, cast, get_args, Literal, SupportsIndex, ParamSpec, TypeVar, Optional -from tinygrad.dtype import DType, DTypeLike, dtypes, ImageDType, ConstType, least_upper_float, least_upper_dtype, sum_acc_dtype, to_dtype, truncate -from tinygrad.dtype import _from_np_dtype, _to_np_dtype -from tinygrad.helpers import argfix, make_tuple, flatten, prod, all_int, round_up, merge_dicts, argsort, getenv, all_same, fully_flatten, dedup -from tinygrad.helpers import IMAGE, WINO, Metadata, TRACEMETA, ceildiv, fetch, polyN, unwrap, DEBUG -from tinygrad.gradient import compute_gradient -from tinygrad.uop.ops import smax, smin, resolve, UOp, Ops, sint, Variable, MathTrait, identity_element, all_metadata -from tinygrad.uop.spec import tensor_uop_spec, type_verify -from tinygrad.device import Device, Buffer -from tinygrad.engine.realize import run_schedule -from tinygrad.engine.memory import memory_planner -from tinygrad.engine.schedule import ScheduleItem, create_schedule_with_vars -from tinygrad.engine.grouper import get_kernelize_map - -# *** all in scope Tensors are here. this gets relevant UOps *** - -all_tensors: set[weakref.ref[Tensor]] = set() -def _find_all_tensors_for_uops(all_uops: set[UOp]) -> list[Tensor]: - return [t for tref in all_tensors if (t:=tref()) is not None and t.uop in all_uops] - -def _apply_map_to_tensors(applied_map:dict[UOp, UOp], name:str|None=None) -> None: - # get all children of keys in applied_map - all_uops: set[UOp] = set() - search_uops = list(applied_map) - while len(search_uops): - x = search_uops.pop() - if x in all_uops: continue - all_uops.add(x) - search_uops.extend([u for c in x.children if (u:=c()) is not None]) - - # link the found UOps back to Tensors. exit early if there's no Tensors to realize - # NOTE: this uses all_tensors, but it's fast - if len(fixed_tensors := _find_all_tensors_for_uops(all_uops)): - # potentially rewrite all the discovered Tensors - sink = UOp.sink(*[t.uop for t in fixed_tensors]) - new_sink = sink.substitute(applied_map, name=name) - - # set the relevant uop to the realized UOps - for t,s,ns in zip(fixed_tensors, sink.src, new_sink.src): - if s is ns: continue - t.uop = ns - -# **** Tensor helper functions **** - -# this tracks the tensor.py METADATA -_METADATA: contextvars.ContextVar[Optional[Metadata]] = contextvars.ContextVar("_METADATA", default=None) - -def _fromnp(x: 'np.ndarray') -> UOp: # type: ignore [name-defined] # noqa: F821 - ret = UOp.new_buffer("NPY", x.size, _from_np_dtype(x.dtype)) - # fake realize - ret.buffer.allocate(x) - return ret.reshape(x.shape) - -def get_shape(x) -> tuple[int, ...]: - # NOTE: str is special because __getitem__ on a str is still a str - if not hasattr(x, "__len__") or not hasattr(x, "__getitem__") or isinstance(x, str) or (hasattr(x, "shape") and x.shape == ()): return () - if not all_same(subs:=[get_shape(xi) for xi in x]): raise ValueError(f"inhomogeneous shape from {x}") - return (len(subs),) + (subs[0] if subs else ()) - -def _frompy(x:list|tuple|bytes, dtype:DType) -> UOp: - if isinstance(x, bytes): ret, data = UOp.new_buffer("PYTHON", len(x)//dtype.itemsize, dtype), x - else: - ret = UOp.new_buffer("PYTHON", prod(shape:=get_shape(x)), dtype).reshape(shape) - assert dtype.fmt is not None, f"{dtype=} has None fmt" - truncate_function = truncate[dtype] - data = struct.pack(f"@{ret.size}{dtype.fmt}", *[truncate_function(xi) for xi in fully_flatten(x)]) - # fake realize - ret.buffer.allocate(memoryview(data if Device.DEFAULT != "PYTHON" else bytearray(data))) - return ret - -def _get_winograd_matcols(mat, dims:int, shp:tuple[sint, ...], device:str|tuple[str, ...], dtype:DType) -> list[list[Tensor]]: - return [[Tensor.cat(*[Tensor.full(shp[:dim] + (1,) + shp[dim+1:], float(m[k]), device=device, dtype=dtype) for m in mat], dim=dim) - for k in range(len(mat[0]))] for dim in range(dims)] - -# winograd conv 3 kernel f(4x4,3x3) see: http://arxiv.org/abs/1509.09308 -def _apply_winograd_matrix(mat, t:Tensor, dims:int) -> Tensor: - # multiply mat_1 @ mat_2 @ t with foldable constants, where mat_i acts on vector t along dimension i; roughly kron(mat, mat) @ t - # due to realize-before-expand rule in lazy.py, we must operate in this order: reshape -> expand -> arithmetic - t_ = t.reshape(t.shape[:dims] + (1,) * dims + t.shape[dims:]).expand(t.shape[:dims] + (len(mat),) * dims + t.shape[dims:]) # add output dims - # precalculate mat columns for each dim; prod(itertools.product(matcols)) gives the columns of kron(mat, mat, ...) - matcols = _get_winograd_matcols(mat, dims, t_.shape[dims:], t_.device, t_.dtype) - # multiply each element of t_ by the corresponding stacked column of kron(mat, mat), producing only one view for each element of t - ret = sum(prod(col[idx] for col, idx in zip(matcols, mat_is)) * t_[mat_is] for mat_is in itertools.product(range(len(mat[0])), repeat=dims)) - assert isinstance(ret, Tensor), "sum didn't return a Tensor" - return ret - -def _align_left(*shapes:tuple[sint, ...]) -> tuple[tuple[sint, ...], ...]: - # unsqueeze left to make every shape same length - max_dim = max(len(shape) for shape in shapes) - return tuple((1,) * (max_dim - len(shape)) + shape for shape in shapes) -def _broadcast_shape(*shapes:tuple[sint, ...]) -> tuple[sint, ...]: - return tuple(0 if 0 in nth_dim_sizes else smax(nth_dim_sizes) for nth_dim_sizes in zip(*_align_left(*shapes))) - -def _masked_setitem(target:Tensor, values:Tensor, mask:Tensor, axes:tuple[int, ...]) -> Tensor: - # reduce such that if mask contains repeated indices the last one remains - for dim in axes: mask, values = functools.reduce(lambda x,y: (x[0]|y[0], y[0].where(y[1], x[1])), zip(mask.split(1, dim), values.split(1, dim))) - # remove extra dims from reduce - for dim in reversed(axes): mask, values = mask.squeeze(dim), values.squeeze(dim) - # select from values for each True element in mask else select from target - return mask.where(values, target) - -# `(padding_left, padding_right, padding_top, padding_bottom, ...)` -> `(..., (padding_top, padding_bottom), (padding_left, padding_right))` -def _flat_to_grouped(padding:Sequence[sint]) -> tuple[tuple[sint, sint], ...]: return tuple(zip(padding[-2::-2], padding[::-2])) - -ReductionStr = Literal["mean", "sum", "none"] - -class Tensor(MathTrait): - """ - A `Tensor` is a multi-dimensional matrix containing elements of a single data type. - - ```python exec="true" session="tensor" - from tinygrad import Tensor, dtypes, nn - import numpy as np - import math - np.set_printoptions(precision=4) - ``` - """ - __slots__ = "uop", "requires_grad", "grad" - training: ClassVar[bool] = False - - def __init__(self, data:ConstType|bytes|list|tuple|UOp|'np.ndarray'|pathlib.Path|None, # type: ignore [name-defined] # noqa: F821 - device:str|tuple|list|None=None, dtype:DTypeLike|None=None, requires_grad:bool|None=None): - if dtype is not None: dtype = to_dtype(dtype) - if device is None and isinstance(data, pathlib.Path): device = f"DISK:{data.resolve()}" # keep it on the disk if device is None - device = tuple(Device.canonicalize(x) for x in device) if isinstance(device, (tuple, list)) else Device.canonicalize(device) - - # tensors can have gradients if you have called .backward - self.grad:Tensor|None = None - - # NOTE: this can be in three states. False and None: no gradient, True: gradient - # None (the default) will be updated to True if it's put in an optimizer - self.requires_grad:bool|None = requires_grad - - # create a UOp from the different types of inputs - if isinstance(data, UOp): - assert dtype is None or dtype==data.dtype, "dtype doesn't match, and casting isn't supported" - if data.op is Ops.BIND: - var, val = data.unbind() - # give the bound constant a device - const = UOp.const(var.dtype, val, device, ()) - data = data.replace(src=(var.replace(src=const.src), const)) - elif data is None: data = UOp.const(dtype or dtypes.default_float, 0, device, ()) - elif isinstance(data, get_args(ConstType)): data = UOp.const(dtype or dtypes.from_py(data), data, device, ()) - elif isinstance(data, bytes): data = _frompy(data, dtypes.uint8 if dtype is None else dtype) - elif isinstance(data, (list, tuple)): - if dtype is None: - if (d := fully_flatten(data)) and all(isinstance(s, bool) for s in d): dtype = dtypes.bool - else: dtype = dtypes.default_int if d and all_int(d) else dtypes.default_float # NOTE: this works because all_int([True, False]) is True - if dtype in [dtypes.bfloat16, *dtypes.fp8s]: data = Tensor(_frompy(data, dtypes.float32), device=device).cast(dtype).uop - else: data = _frompy(data, dtype) - elif str(type(data)) == "": - import numpy as np - assert isinstance(data, np.ndarray), f"expected np.ndarray, got {data}" - if data.shape == (): data = UOp.const(dtype or _from_np_dtype(data.dtype), data.item(), device, ()) - else: data = _fromnp(data.astype(npdtype) if dtype is not None and (npdtype:=_to_np_dtype(dtype)) is not None else data) # type: ignore [name-defined] - elif isinstance(data, pathlib.Path): - dtype = dtype or dtypes.uint8 - data = UOp.new_buffer(f"DISK:{data.resolve()}", data.stat().st_size // dtype.itemsize, dtype) - - # by this point, it has to be a UOp - if not isinstance(data, UOp): raise RuntimeError(f"can't create Tensor from {data!r} with type {type(data)}") - - # data might be on a different device - if isinstance(device, str): self.uop:UOp = data if data.device == device else data.copy_to_device(device) - # if device is a tuple, we should have/construct a MultiLazyBuffer - elif isinstance(data.device, str): self.uop = Tensor(data).shard(device).uop - else: - assert data.device == device, f"MultiLazyBuffer device mismatch, {data.device} != {device}" - self.uop = data - - # add to all_tensors after construction succeeds - all_tensors.add(weakref.ref(self)) - def __del__(self): all_tensors.discard(weakref.ref(self)) - - def _apply_uop(self, fxn:Callable, *x:Tensor, **kwargs) -> Tensor: - new_uop: UOp = fxn(*[t.uop for t in (self,)+x], **kwargs) - if (metadata:=_METADATA.get()) is not None: all_metadata[new_uop] = (metadata,) - needs_input_grad = [t.requires_grad for t in (self,)+x] - return Tensor(new_uop, device=new_uop.device, requires_grad=True if any(needs_input_grad) else None if None in needs_input_grad else False) - - def _apply_broadcasted_uop(self, fxn:Callable, x:Tensor|ConstType, reverse=False) -> Tensor: - lhs,rhs = self._broadcasted(x, reverse) - return lhs._apply_uop(fxn, rhs) - - # _binop is used by MathTrait - def _binop(self, op, x, reverse): return self._apply_broadcasted_uop(lambda *u: UOp.alu(u[0], op, *u[1:]), x, reverse) - - def requires_grad_(self, requires_grad=True) -> Tensor: - self.requires_grad = requires_grad - return self - - class train(ContextDecorator): - def __init__(self, mode:bool = True): self.mode = mode - def __enter__(self): self.prev, Tensor.training = Tensor.training, self.mode - def __exit__(self, exc_type, exc_value, traceback): Tensor.training = self.prev - - def __repr__(self): - ld = self.uop - ld_repr = f"" - return f"" - - # Python has a non moving GC, so this should be okay - def __hash__(self): return id(self) - - def __bool__(self): raise TypeError("__bool__ on Tensor is not defined") - - def __len__(self): - if not self.shape: raise TypeError("len() of a 0-d tensor") - return self.shape[0] - - @property - def device(self) -> str|tuple[str, ...]: return self.uop.device - - @property - def shape(self) -> tuple[sint, ...]: return self.uop.shape - - @property - def dtype(self) -> DType: return self.uop.dtype - - # ***** data handlers **** - - def kernelize(self, *lst:Tensor) -> Tensor: - """ - Creates the kernels and buffers needed to realize these Tensor(s). - - NOTE: Kernelize can be called multiple times on a Tensor - """ - big_sink = UOp.sink(*[x.uop for x in (self,)+lst]) - - # verify Tensors match the spec - if __debug__: type_verify(list(big_sink.toposort()), tensor_uop_spec) - - becomes_map = get_kernelize_map(big_sink) - _apply_map_to_tensors(becomes_map, name="Apply Kernelize Map") - return self - - def schedule_with_vars(self, *lst:Tensor) -> tuple[list[ScheduleItem], dict[Variable, int]]: - """ - Creates the schedule needed to realize these Tensor(s), with Variables. - - NOTE: A Tensor can only be scheduled once. - """ - st = time.perf_counter() - self.kernelize(*lst) - sink = UOp.sink(*[x.uop for x in (self,)+lst]) - - # remove all ASSIGNs, after scheduling, the tensors are just buffers - remove_assign_map = {u:u.buf_uop for u in sink.toposort() if u.op is Ops.ASSIGN} - _apply_map_to_tensors(remove_assign_map, name="Remove Assigns") - - # create the schedule - schedule, var_vals = create_schedule_with_vars(sink) - schedule = memory_planner(schedule) - if DEBUG >= 1 and len(schedule) >= 10: print(f"scheduled {len(schedule)} kernels in {(time.perf_counter()-st)*1000:.2f} ms") - return schedule, var_vals - - def schedule(self, *lst:Tensor) -> list[ScheduleItem]: - """Creates the schedule needed to realize these Tensor(s).""" - schedule, var_vals = self.schedule_with_vars(*lst) - assert len(var_vals) == 0 - return schedule - - def realize(self, *lst:Tensor, do_update_stats=True) -> Tensor: - """Triggers the computation needed to create these Tensor(s).""" - run_schedule(*self.schedule_with_vars(*lst), do_update_stats=do_update_stats) - return self - - def replace(self, x:Tensor, allow_shape_mismatch=False) -> Tensor: - """ - Replaces the data of this tensor with the data of another tensor. Only the shape of the tensors must match. - """ - # used for replacing a Tensor with a new version of it (potentially with a different device and dtype) - assert self.shape == x.shape or allow_shape_mismatch, f"replace shape mismatch {self.shape} != {x.shape}" - self.uop = x.uop - return self - - def assign(self, x) -> Tensor: - # TODO: this is a hack for writing to DISK. remove with working assign - if isinstance(self.device, str) and self.device.startswith("DISK"): - if x.__class__ is not Tensor: x = Tensor(x, device="CPU", dtype=self.dtype) - cast(Buffer, self.contiguous().realize().uop.base.buffer).ensure_allocated().copyin(x._data()) - return self - if x.__class__ is not Tensor: x = Tensor(x, device=self.device, dtype=self.dtype) - if self.uop is x.uop: return self # a self assign is a NOOP - # NOTE: we allow cross device assign - assert self.shape == x.shape, f"assign shape mismatch {self.shape} != {x.shape}" - assert self.device == x.device, f"assign device mismatch {self.device} != {x.device}" - assert self.dtype == x.dtype, f"assign dtype mismatch {self.dtype} != {x.dtype}" - self.uop = self.uop.assign(x.uop) - return self - - def detach(self) -> Tensor: - """ - Returns a new tensor with the same data as this tensor, but detached from the autograd graph. - """ - return Tensor(self.uop.detach(), device=self.device, requires_grad=False) - - def _buffer(self) -> Buffer: return cast(Buffer, self.cast(self.dtype.base).contiguous().to("CPU").realize().uop.base.buffer) - def _data(self) -> memoryview: return self._buffer().as_buffer() - - def data(self) -> memoryview: - """ - Returns the data of this tensor as a memoryview. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4]) - print(np.frombuffer(t.data(), dtype=np.int32)) - ``` - """ - if 0 in self.shape: return memoryview(bytearray(0)).cast(self.dtype.base.fmt) - assert all_int(self.shape), f"no data if shape is symbolic, {self.shape=}" - return self._buffer().as_typed_buffer(self.shape) - - def item(self) -> ConstType: - """ - Returns the value of this tensor as a standard Python number. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor(42) - print(t.item()) - ``` - """ - assert self.numel() == 1, "must have one element for item" - return self.data()[(0,) * len(self.shape)] - - # TODO: should be Tensor.tolist() -> Union[list[ConstType], ConstType]. The list is Sequence because mypy expects memoryview.tolist() -> list[int] - # src: https://github.com/python/mypy/blob/release-1.6/mypy/typeshed/stdlib/builtins.pyi#L803 - def tolist(self) -> Sequence[ConstType]|ConstType: - """ - Returns the value of this tensor as a nested list. - Returns single value for const tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4]) - print(t.tolist()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor(5) - print(t.tolist()) - ``` - """ - return self.data().tolist() - - def numpy(self) -> 'np.ndarray': # type: ignore [name-defined] # noqa: F821 - """ - Returns the value of this tensor as a `numpy.ndarray`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4]) - print(repr(t.numpy())) - ``` - """ - assert all_int(self.shape), f"no data if shape is symbolic, {self.shape=}" - import numpy as np - if self.dtype.base == dtypes.bfloat16: return self.float().numpy() - if 0 in self.shape: return np.empty(self.shape, dtype=_to_np_dtype(self.dtype.base)) - return self._buffer().numpy().reshape(self.shape) - - def clone(self) -> Tensor: - """ - Creates a clone of this tensor allocating a separate buffer for the data. - """ - ret = Tensor.empty(self.shape, device=self.device, dtype=self.dtype) - if self.grad is not None: ret.grad = self.grad.clone() - return ret.assign(self) - - def to(self, device:str|tuple[str, ...]|None) -> Tensor: - """ - Moves the tensor to the given device. - """ - device = tuple(Device.canonicalize(x) for x in device) if isinstance(device, (tuple, list)) else Device.canonicalize(device) - if device == self.device: return self - if not isinstance(device, str): return self.shard(device) - ret = Tensor(self.uop, device, requires_grad=self.requires_grad) - if self.grad is not None: ret.grad = self.grad.to(device) - return ret - - def to_(self, device:str|tuple[str, ...]|None) -> Tensor: - """ - Moves the tensor to the given device in place. - """ - real = self.to(device) - if self.grad is not None and real.grad is not None: self.grad.replace(real.grad) - return self.replace(real) - - def shard(self, devices:tuple[str, ...], axis:int|None=None) -> Tensor: - """ - Shards the tensor across the given devices. Optionally specify which axis to shard on. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.empty(2, 4) - print(t.shard((t.device, t.device), axis=1).uop) - ``` - """ - assert isinstance(self.device, str), "can't shard a MultiLazyBuffer" - devices = tuple(Device.canonicalize(x) for x in devices) - mlb = self.uop.shard(devices, self._resolve_dim(axis)) if axis is not None else self.uop.copy_to_device(devices) - return Tensor(mlb, device=devices, requires_grad=self.requires_grad) - - def shard_(self, devices:tuple[str, ...], axis:int|None=None) -> Tensor: - """ - Shards the tensor across the given devices in place. - """ - return self.replace(self.shard(devices, axis)) - - @staticmethod - def from_uop(y:UOp, **kwargs) -> Tensor: - if y.op is Ops.BIND: return Tensor(y, **kwargs, requires_grad=False) - if y.op is Ops.CONST: return Tensor(y.arg, **kwargs, requires_grad=False) - if y.op is Ops.MUL: return Tensor.from_uop(y.src[0]) * Tensor.from_uop(y.src[1]) - if y.op is Ops.ADD: return Tensor.from_uop(y.src[0]) + Tensor.from_uop(y.src[1]) - raise RuntimeError(f"unhandled UOp {y}") - - # ***** creation entrypoint ***** - - @staticmethod - def empty(*shape, device:str|tuple[str, ...]|None=None, dtype:DTypeLike|None=None, **kwargs) -> Tensor: - """ - Creates an empty tensor with the given shape. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.empty(2, 3) - print(t.shape) - ``` - """ - dtype, shape = to_dtype(dtype) if dtype is not None else dtypes.default_float, argfix(*shape) - if not isinstance(size:=prod([x.vmax if isinstance(x, UOp) else x for x in shape]), int): raise ValueError(f"size must be int {size}") - # TODO: add test for multidevice tensor - device = tuple(Device.canonicalize(d) for d in device) if isinstance(device, tuple) else Device.canonicalize(device) - return Tensor(UOp.new_buffer(device, size, dtype), device, dtype, **kwargs).reshape(shape) - - @staticmethod - def from_blob(ptr:int, shape:tuple[int, ...], **kwargs) -> Tensor: - """ - Exposes the pointer as a Tensor without taking ownership of the original data. - The pointer must remain valid for the entire lifetime of the created Tensor. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - """ - r = Tensor.empty(*shape, **kwargs) - assert isinstance(r.device, str) - cast(Buffer, r.uop.buffer).allocate(external_ptr=ptr) - return r - - @staticmethod - def from_url(url:str, gunzip:bool=False, **kwargs) -> Tensor: - """ - Creates a Tensor from a URL. - - This is the preferred way to access Internet resources. - It currently returns a DISK Tensor, but in the future it may return an HTTP Tensor. - This also will soon become lazy (when possible) and not print progress without DEBUG. - - The `gunzip` flag will gzip extract the resource and return an extracted Tensor. - """ - return Tensor(fetch(url, gunzip=gunzip), **kwargs) - - _seed: int = int(time.time()) - _device_seeds: dict[str, Tensor] = {} - _device_rng_counters: dict[str, Tensor] = {} - @staticmethod - def manual_seed(seed=0) -> None: - """ - Sets the seed for random operations. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.rand(5).numpy()) - print(Tensor.rand(5).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) # reset to the same seed - print(Tensor.rand(5).numpy()) - print(Tensor.rand(5).numpy()) - ``` - """ - Tensor._seed, Tensor._device_seeds, Tensor._device_rng_counters = seed, {}, {} - - @staticmethod - def _threefry_random_bits(key:Tensor, counts0:Tensor, counts1:Tensor) -> Tensor: - x = (counts1.cast(dtypes.uint64) << 32) | counts0.cast(dtypes.uint64) - x = x._apply_uop(UOp.threefry, (key[1]._broadcast_to(x.shape).cast(dtypes.uint64) << 32) | key[0]._broadcast_to(x.shape).cast(dtypes.uint64)) - counts0, counts1 = (x & 0xffffffff).cast(dtypes.uint32), ((x >> 32) & 0xffffffff).cast(dtypes.uint32) - return counts0.cat(counts1) - - @staticmethod - def rand(*shape, device:str|None=None, dtype:DTypeLike|None=None, contiguous:bool=True, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random values from a uniform distribution over the interval `[0, 1)`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.rand(2, 3) - print(t.numpy()) - ``` - """ - if not dtypes.is_float(dtype := to_dtype(dtype or dtypes.default_float)): raise ValueError(f"rand only supports float dtypes, got {dtype}") - if not all_int(shape:=argfix(*shape)) or not all(s >= 0 for s in shape): raise ValueError(f"invalid input {shape=}") - if device is not None and not isinstance(device, str): raise ValueError(f"rand only supports single device, got {device=}") - device = Device.canonicalize(device) - - # if shape has 0, return zero tensor - if (numel := prod(shape)) == 0: return Tensor.zeros(shape, device=device, dtype=dtype, **kwargs) - num = ceildiv(numel * dtype.itemsize, 4) - - # generate per device seeds and rng counter if we haven't seen this device yet - if device not in Tensor._device_seeds: - Tensor._device_seeds[device] = Tensor( - [int.from_bytes(hashlib.sha256(len(Tensor._device_seeds).to_bytes(4, "big")).digest(), "big"), Tensor._seed], - device=device, dtype=dtypes.uint32, requires_grad=False) - Tensor._device_rng_counters[device] = Tensor([num], device=device, dtype=dtypes.uint32, requires_grad=False) - # increment rng counter for devices - else: Tensor._device_rng_counters[device].assign(Tensor._device_rng_counters[device] + num).contiguous() - - # threefry random bits - bits_count = Tensor._device_rng_counters[device] - num - counts0 = (Tensor.arange(ceildiv(num, 2), device=device, dtype=dtypes.uint32, requires_grad=False)+bits_count) - counts1 = counts0 + ceildiv(num, 2) - bits = Tensor._threefry_random_bits(Tensor._device_seeds[device], counts0, counts1)[:num] - - # bitcast to uint with same number of bits - _, nmant = dtypes.finfo(dtype) - uint_dtype = {1: dtypes.uint8, 2: dtypes.uint16, 4: dtypes.uint32, 8: dtypes.uint64}[dtype.itemsize] - bits = bits.bitcast(uint_dtype) - # only randomize the mantissa bits and set the exponent to 1 - one = Tensor.ones_like(bits, device=bits.device, dtype=dtype).bitcast(uint_dtype) - bits = bits.rshift((dtype.itemsize * 8) - nmant).bitwise_or(one) - # bitcast back to the original dtype and reshape - out = bits.bitcast(dtype)[:numel].sub(1).reshape(shape).requires_grad_(kwargs.get("requires_grad")) - return out.contiguous() if contiguous else out - - # ***** creation helper functions ***** - - @staticmethod - def full(shape:tuple[sint, ...], fill_value:ConstType, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with the given value. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.full((2, 3), 42).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.full((2, 3), False).numpy()) - ``` - """ - return Tensor(fill_value, **kwargs).reshape((1, )*len(new_shape := argfix(shape))).expand(new_shape) - - @staticmethod - def zeros(*shape, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with zeros. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.zeros(2, 3).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.zeros(2, 3, dtype=dtypes.int32).numpy()) - ``` - """ - return Tensor.full(argfix(*shape), 0.0, **kwargs) - - @staticmethod - def ones(*shape, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with ones. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(2, 3).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(2, 3, dtype=dtypes.int32).numpy()) - ``` - """ - return Tensor.full(argfix(*shape), 1.0, **kwargs) - - @staticmethod - def arange(start, stop=None, step=1, **kwargs) -> Tensor: - """ - Returns a 1-D tensor of size `ceil((stop - start) / step)` with values from `[start, stop)`, with spacing between values given by `step`. - - If `stop` is not specified, values are generated from `[0, start)` with the given `step`. - - If `stop` is specified, values are generated from `[start, stop)` with the given `step`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.arange(5).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.arange(5, 10).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.arange(5, 10, 2).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.arange(5.5, 10, 2).numpy()) - ``` - """ - if stop is None: stop, start = start, 0 - dtype = kwargs.pop("dtype", dtypes.default_float if any(isinstance(x, float) for x in (start, stop, step)) else dtypes.default_int) - # NOTE: this matches numpy, torch raises RuntimeError if stop-start and step have different signs - if (output_len:=ceildiv(stop-start, step)) <= 0: return Tensor([], dtype=dtype, **kwargs) - return (Tensor.full((output_len,), step, dtype=dtype, **kwargs)._cumalu(0, Ops.ADD) + (start - step)).cast(dtype) - - @staticmethod - def linspace(start:int|float, stop:int|float, steps:int, **kwargs) -> Tensor: - """ - Returns a 1-D tensor of `steps` evenly spaced values from `start` to `stop`, inclusive. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.linspace(0, 10, 5).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.linspace(-1, 1, 5).numpy()) - ``` - """ - if steps < 0: raise ValueError("number of steps must be non-negative") - if (dtype := to_dtype(kwargs.pop("dtype", dtypes.default_float))) == dtypes.bool: raise ValueError("linspace with bool dtype is not supported") - if steps == 1: return Tensor([start], dtype=dtype, **kwargs) - return (start + Tensor.arange(steps, **kwargs) * ((stop - start) / (steps - 1))).cast(dtype) - - @staticmethod - def eye(n:int, m:int|None=None, **kwargs) -> Tensor: - """ - Returns a 2-D tensor with `n` rows and `m` columns, with ones on the diagonal and zeros elsewhere. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.eye(3).numpy()) - ``` - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.eye(2, 4).numpy()) - ``` - """ - if n < 0 or (m is not None and m < 0): raise ValueError(f"cannot have negative {n=}, {m=}") - x = Tensor.ones((n,1),**kwargs).pad((None,(0,n))).flatten().shrink(((0,n*n),)).reshape(n,n) - return x if m is None else x.pad((None, (0, m-n))) if m > n else x.shrink((None, (0, m))) - - def full_like(self, fill_value:ConstType, **kwargs) -> Tensor: - """ - Creates a tensor with the same shape as `self`, filled with the given value. - If `dtype` is not specified, the dtype of `self` is used. - - You can pass in the `device` keyword argument to control device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.ones(2, 3) - print(Tensor.full_like(t, 42).numpy()) - ``` - """ - return Tensor.full(self.shape, fill_value, dtype=kwargs.pop("dtype", self.dtype), device=kwargs.pop("device", self.device), **kwargs) - - def zeros_like(self, **kwargs) -> Tensor: - """ - Creates a tensor with the same shape as `self`, filled with zeros. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.ones(2, 3) - print(Tensor.zeros_like(t).numpy()) - ``` - """ - return self.full_like(0, **kwargs) - - def ones_like(self, **kwargs) -> Tensor: - """ - Creates a tensor with the same shape as `self`, filled with ones. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.zeros(2, 3) - print(Tensor.ones_like(t).numpy()) - ``` - """ - return self.full_like(1, **kwargs) - - def rand_like(self, **kwargs) -> Tensor: - """ - Creates a tensor with the same shape and sharding as `self`, filled with random values from a uniform distribution over the interval `[0, 1)`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.ones(2, 3) - print(Tensor.rand_like(t).numpy()) - ``` - """ - dtype = kwargs.pop("dtype", self.dtype) - if isinstance(self.device, tuple): - if kwargs.get("device") is not None: raise RuntimeError("cannot specify `device` on `rand_like` of a multi device tensor") - return Tensor.rand(*self.shape, dtype=dtype, **kwargs).shard(self.device, self.uop.axis) - return Tensor.rand(*self.shape, device=kwargs.pop("device", self.device), dtype=dtype, **kwargs) - - # ***** rng hlops ***** - - def randn_like(self, dtype:DTypeLike|None=None, requires_grad:bool|None=None, **kwargs) -> Tensor: - """ - Creates a tensor with the same shape and sharding as `self`, filled with random values from a normal distribution with mean 0 and variance 1. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.ones(2, 3) - print(Tensor.randn_like(t).numpy()) - ``` - """ - src = self.stack(self).rand_like(**{**kwargs, "dtype": dtypes.float32}) - # https://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform - return (src[0].mul(2*math.pi).cos().mul((1 - src[1]).log().mul(-2).sqrt()).cast(dtype or self.dtype)).requires_grad_(requires_grad) - - @staticmethod - def randn(*shape, dtype:DTypeLike|None=None, requires_grad:bool|None=None, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random values from a normal distribution with mean `0` and standard deviation `1`. - If `dtype` is not specified, the default type is used. - - You can pass in the `device` keyword argument to control device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.randn(2, 3).numpy()) - ``` - """ - return Tensor.empty(*shape).randn_like(dtype=dtype, requires_grad=requires_grad) - - @staticmethod - def randint(*shape, low=0, high=10, dtype=dtypes.int32, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random integer values generated uniformly from the interval `[low, high)`. - If `dtype` is not specified, the default type is used. - - You can pass in the `device` keyword argument to control device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.randint(2, 3, low=5, high=10).numpy()) - ``` - """ - if not isinstance(low, int) or not isinstance(high, int): raise TypeError(f"{low=} and {high=} must be integers") - dtype = to_dtype(dtype) - if not dtypes.is_int(dtype): raise TypeError(f"{dtype=} must be int") - return Tensor.uniform(*shape, low=low, high=high, dtype=dtype, **kwargs) - - @staticmethod - def normal(*shape, mean=0.0, std=1.0, requires_grad:bool|None=None, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random values from a normal distribution with the given `mean` and standard deviation `std`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.normal(2, 3, mean=10, std=2).numpy()) - ``` - """ - return ((std * Tensor.randn(*shape, **kwargs)) + mean).requires_grad_(requires_grad) - - @staticmethod - def uniform(*shape, low=0.0, high=1.0, dtype:DTypeLike|None=None, requires_grad:bool|None=None, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random values from a uniform distribution over the interval `[low, high)`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.uniform(2, 3, low=2, high=10).numpy()) - ``` - """ - return (((high-low) * Tensor.rand(*shape, **kwargs)).cast(dtype or dtypes.default_float) + low).requires_grad_(requires_grad) - - @staticmethod - def scaled_uniform(*shape, **kwargs) -> Tensor: - """ - Creates a tensor with the given shape, filled with random values from a uniform distribution - over the interval `[-prod(shape)**-0.5, prod(shape)**-0.5)`. - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.scaled_uniform(2, 3).numpy()) - ``` - """ - return Tensor.uniform(*shape, low=-1.0, high=1.0, **kwargs).mul(prod(argfix(*shape))**-0.5) - - # https://www.tensorflow.org/api_docs/python/tf/keras/initializers/GlorotUniform - @staticmethod - def glorot_uniform(*shape, **kwargs) -> Tensor: - """ - - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.glorot_uniform(2, 3).numpy()) - ``` - """ - return Tensor.uniform(*shape, low=-1.0, high=1.0, **kwargs).mul((6/(argfix(*shape)[0]+prod(argfix(*shape)[1:])))**0.5) - - # https://pytorch.org/docs/stable/_modules/torch/nn/init.html#kaiming_uniform_ - @staticmethod - def kaiming_uniform(*shape, a:float = 0.01, **kwargs) -> Tensor: - """ - - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.kaiming_uniform(2, 3).numpy()) - ``` - """ - bound = math.sqrt(3.0) * math.sqrt(2.0 / (1 + a ** 2)) / math.sqrt(prod(argfix(*shape)[1:])) - return Tensor.uniform(*shape, low=-bound, high=bound, **kwargs) - - # https://pytorch.org/docs/stable/_modules/torch/nn/init.html#kaiming_normal_ - @staticmethod - def kaiming_normal(*shape, a:float = 0.01, **kwargs) -> Tensor: - """ - - - You can pass in `dtype` and `device` keyword arguments to control the data type and device of the tensor. - Additionally, all other keyword arguments are passed to the constructor of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.kaiming_normal(2, 3).numpy()) - ``` - """ - std = math.sqrt(2.0 / (1 + a ** 2)) / math.sqrt(prod(argfix(*shape)[1:])) - return Tensor.normal(*shape, mean=0.0, std=std, **kwargs) - - @staticmethod - def randperm(n:int, device=None, dtype=dtypes.int32, **kwargs) -> Tensor: - """ - Returns a tensor with a random permutation of integers from `0` to `n-1`. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - print(Tensor.randperm(6).numpy()) - ``` - """ - r = Tensor.rand(n, device=device, **kwargs) - _, indices = r.sort() - return indices.cast(dtype) - - def multinomial(self:Tensor, num_samples:int = 1, replacement:bool = False) -> Tensor: - """ - Returns a tensor with `num_samples` indices sampled from a multinomial distribution weighted by `self`. - - NOTE: `replacement=False` for `num_samples > 1` is not supported yet. - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor([1, 2, 3, 4]) - print(t.multinomial(20, replacement=True).numpy()) - ``` - """ - assert 1 <= self.ndim <= 2 and num_samples > 0, f"{self.ndim=} must be 1 or 2 dim, {num_samples=} must be positive" - assert replacement or num_samples == 1, "no replacement only supports num_samples = 1" - weight = self.unsqueeze(0) if self.ndim == 1 else self - cdf = (cw := weight.cumsum(1).float()) / cw[:, -1].unsqueeze(1) - unif_samples = Tensor.rand(num_samples, cdf.shape[0], 1).to(self.device) - indices = (unif_samples.expand((-1, -1, cdf.shape[1])) >= cdf).sum(2).permute((1, 0)) - return (indices.squeeze(0) if self.ndim == 1 else indices).cast(dtypes.int32) - - # ***** toposort and backward pass ***** - - def gradient(self, *targets:Tensor, gradient:Tensor|None=None, materialize_grads=False) -> list[Tensor]: - """ - Computes the gradient of the targets with respect to self. - - ```python exec="true" source="above" session="tensor" result="python" - x = Tensor.eye(3) - y = Tensor([[2.0,0,-2.0]]) - z = y.matmul(x).sum() - dx, dy = z.gradient(x, y) - - print(dx.tolist()) # dz/dx - print(dy.tolist()) # dz/dy - ``` - """ - assert gradient is not None or self.shape == tuple(), "when no gradient is provided, backward must be called on a scalar tensor" - if not (self.is_floating_point() and all(t.is_floating_point() for t in targets)): raise RuntimeError("only float Tensors have gradient") - if gradient is None: gradient = Tensor(1.0, dtype=self.dtype, device=self.device, requires_grad=False) - target_uops = [x.uop for x in targets] - grads = compute_gradient(self.uop, gradient.uop, set(target_uops)) - ret = [] - for x in target_uops: - if (y:=grads.get(x)) is None: - if materialize_grads: y = x.const_like(0) - else: raise RuntimeError(f"{x}\n\nnot found in\n\n{self.uop}") - ret.append(y) - # create returned Tensors - return [Tensor(u, device=t.device) for t,u in zip(targets, ret)] - - def backward(self, gradient:Tensor|None=None) -> Tensor: - """ - Propagates the gradient of a tensor backwards through the computation graph. - If the 'gradient' argument is not provided, the tensor must be a scalar, and the gradient is implicitly set to 1.0. - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1.0, 2.0, 3.0, 4.0], requires_grad=True) - t.sum().backward() - print(t.grad.numpy()) - ``` - """ - all_uops = self.uop.toposort() - tensors_need_grad: list[Tensor] = [t for tref in all_tensors if (t:=tref()) is not None and \ - t.uop in all_uops and t.requires_grad] - # clear contexts - for t,g in zip(tensors_need_grad, self.gradient(*tensors_need_grad, gradient=gradient, materialize_grads=True)): - assert g.shape == t.shape, f"grad shape must match tensor shape, {g.shape!r} != {t.shape!r}" - t.grad = g if t.grad is None else (t.grad + g) - return self - - # ***** movement low level ops ***** - - def view(self, shape:tuple[sint, ...], *args) -> Tensor: - """`.view` is an alias for `.reshape`.""" - return self.reshape(shape, *args) - - def reshape(self, shape, *args) -> Tensor: - """ - Returns a tensor with the same data as the original tensor but with a different shape. - `shape` can be passed as a tuple or as separate arguments. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(6) - print(t.reshape(2, 3).numpy()) - ``` - """ - # resolve None and args - new_shape = tuple([s if s is not None else self.shape[i] for i,s in enumerate(argfix(shape, *args))]) - # resolve -1 - if (c := new_shape.count(-1)) > 1: raise RuntimeError(f"only one dimension can be inferred using -1, getting {new_shape}") - if c: new_shape = tuple([-prod(self.shape) // prod(new_shape) if s == -1 else s for s in new_shape]) - return self._apply_uop(UOp.reshape, arg=new_shape) if new_shape != self.shape else self - - def expand(self, shape, *args) -> Tensor: - """ - Returns a tensor that is expanded to the shape that is specified. - Expand can also increase the number of dimensions that a tensor has. - - Passing a `-1` or `None` to a dimension means that its size will not be changed. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3]) - print(t.expand(4, -1).numpy()) - ``` - """ - new_shape = tuple(from_ if to == -1 or to is None else to for from_, to in zip(*(_align_left(self.shape, argfix(shape, *args))))) - return self._broadcast_to(new_shape) - - def permute(self, order, *args) -> Tensor: - """ - Returns a tensor that is a permutation of the original tensor. - The new tensor has the same data as the original tensor but with the dimensions permuted according to the order specified. - `order` can be passed as a tuple or as separate arguments. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.empty(2, 3, 5) - print(t.shape) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.permute(2, 0, 1).shape) - ``` - """ - order_arg = tuple(self._resolve_dim(x) for x in argfix(order, *args)) - if sorted(order_arg) != list(range(self.ndim)): raise RuntimeError(f"order is not a valid permutation, getting {order_arg}") - return self._apply_uop(UOp.permute, arg=order_arg) - - def flip(self, axis, *args) -> Tensor: - """ - Returns a tensor that reverses the order of the original tensor along given `axis`. - `axis` can be passed as a tuple or as separate arguments. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(6).reshape(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.flip(0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.flip((0, 1)).numpy()) - ``` - """ - axis_arg = tuple(self._resolve_dim(x) for x in argfix(axis, *args)) - if len(axis_arg) != len(dedup(axis_arg)): raise RuntimeError(f"dim can appear at most once, getting {axis_arg}") - return self._apply_uop(UOp.flip, arg=tuple([i in axis_arg for i in range(len(self.shape))])) - - def shrink(self, arg:tuple[tuple[sint, sint]|None, ...]) -> Tensor: - """ - Returns a tensor that shrinks the each axis based on input arg. - `arg` must have the same length as `self.ndim`. - For each axis, it can be `None`, which means no shrink, or a tuple `(start, end)` that works the same as Python slice. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(9).reshape(3, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.shrink(((None, (1, 3)))).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.shrink((((0, 2), (0, 2)))).numpy()) - ``` - """ - if (shrink_arg:=[x if x is not None else (0,s) for x,s in zip(arg, self.shape)]) == [(0,s) for s in self.shape]: return self - return self._apply_uop(UOp.shrink, arg=tuple(shrink_arg)) - - def pad(self, padding:Sequence[sint]|Sequence[tuple[sint, sint]|None], mode:str="constant", value:float=0.0) -> Tensor: - """ - Returns a tensor with padding applied based on the input `padding`. - - `padding` supports two padding structures: - - 1. Flat padding: `(padding_left, padding_right, padding_top, padding_bottom, ...)` - - This structure matches PyTorch's pad. - - `padding` length must be even. - - 2. Group padding: `(..., (padding_top, padding_bottom), (padding_left, padding_right))` - - This structure matches pad for JAX, NumPy, TensorFlow, and others. - - For each axis, padding can be `None`, meaning no padding, or a tuple `(start, end)`. - - `padding` must have the same length as `self.ndim`. - - Padding values can be negative, resulting in dimension shrinks that work similarly to Python negative slices. - Padding modes is selected with `mode` which supports `constant`, `reflect` and `replicate`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(9).reshape(1, 1, 3, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.pad((1, 2, 0, -1)).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.pad(((None, None, (0, -1), (1, 2)))).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.pad((1, 2, 0, -1), value=-float('inf')).numpy()) - ``` - """ - if mode not in {"constant", "reflect", "replicate", "circular"}: raise NotImplementedError(f"{mode=} is not supported") - # flat padding - if all(isinstance(p, (int,UOp)) for p in padding): - if len(padding)%2 != 0: raise ValueError("Flat padding must have even number of pads") - pX = _flat_to_grouped(tuple(cast(Sequence[sint], padding)) + (0,0)*(self.ndim - len(padding)//2)) - # group padding - else: pX = tuple((0,0) if p is None else p for p in cast(Sequence[tuple[sint, sint]|None], padding)) - if len(pX) != self.ndim: raise ValueError(f"padding length is improper, {padding=} {self.ndim=}") - X, pads = self, tuple((smax(pB,0), smax(pA,0)) for pB,pA in pX) - if mode == "constant": - def _constant(x:Tensor,px,v) -> Tensor: - return x._apply_uop(UOp.pad, arg=px) if v == 0 else (x._apply_uop(UOp.pad, arg=px)+Tensor.ones_like(x)._apply_uop(UOp.pad, arg=px).where(0,v)) - return _constant(X, pX, value) if all(resolve(p >= 0) for p in flatten(pX)) else \ - _constant(X.shrink(tuple((-smin(pB,0),smin(pA+s,s)) for (pB,pA),s in zip(pX, X.shape))), pads, value) - assert all_int(self.shape), f"does not support symbolic shape {self.shape}" - if mode == "circular": - if any(pB>sh or pA>sh for (pB,pA),sh in zip(pX, X.shape)): raise ValueError('Padding value causes wrapping around more than once.') - if any(pB<0 or pA<0 for pB,pA in pX): raise NotImplementedError("Negative pads with circular pads is not supported") - orig_shape, X = X.shape, X.repeat(tuple(1 + bool(pB) + bool(pA) for pB,pA in pads)) - return X.shrink(tuple((0 if pB == 0 else osh-pB, xsh if pA == 0 else xsh-osh+pA) for (pB,pA),osh,xsh in zip(pads, orig_shape, X.shape))) - for d,(pB,pA) in enumerate(pads): - if mode == "reflect": - if pB >= (s:=X.shape[d]) or pA>=s: raise ValueError(f"Padding ({pB}, {pA}) should be less than the input size={s} for dim={d}.") - slcB, slcA, = slice(pB,0,-1), slice(s-2 if s-2>=0 else None, s-2-pA if s-2-pA>=0 else None, -1) - xB, xA = (X[[slc if i == d else slice(None) for i in range(X.ndim)]] if p > 0 else None for slc, p in ((slcB, pB), (slcA, pA))) - if mode == "replicate": - shrB, shrA, = tuple((0,1) if i==d else None for i in range(X.ndim)), tuple((X.shape[i]-1,X.shape[i]) if i==d else None for i in range(X.ndim)) - xB, xA = (X.shrink(shr).expand(tuple(p if i==d else None for i in range(X.ndim))) if p > 0 else None for shr, p in ((shrB, pB), (shrA, pA))) - X = Tensor.cat(*(X_ for X_ in (xB, X, xA) if X_ is not None), dim=d) - return X.shrink(tuple((-min(pB,0), min(pA+s,s)) for (pB,pA),s in zip(pX, X.shape))) - - # ***** movement high level ops ***** - - def _getitem(self, indices, v: Tensor|None = None) -> Tensor: - # wrap single index into a list - if (isinstance(indices, list) and all_int(indices)) or not isinstance(indices, (tuple, list)): indices = [indices] - x, indices = self, list(indices) - - # filter ellipsis and fill with slice(None) or fill rest of indices with slice(None) - if len(ellipsis_idx := [dim for dim, i in enumerate(indices) if i is Ellipsis]) > 1: raise IndexError("indices can only have a single ellipsis") - fill_idx = ellipsis_idx[0] if ellipsis_idx else len(indices) - num_indices = len(indices) - len(ellipsis_idx) - sum(1 for i in indices if i is None) - if num_indices > self.ndim: raise IndexError(f"too many {num_indices=} for {self.ndim=}") - indices[fill_idx:fill_idx+1] = [slice(None)] * (self.ndim - num_indices) - - indices_parsed, dim = [], 0 - for index in indices: - size = 1 if index is None else self.shape[dim] - boundary, stride = [0, size], 1 # defaults - match index: - case list() | tuple() | Tensor(): - if not isinstance(index, Tensor): index = Tensor(index, self.device, requires_grad=False) - if not dtypes.is_int(index.dtype): raise IndexError(f"index dtype {index.dtype} is not supported") - index = (index.to(self.device) < 0).where(index+size, index) # treat negative index values - case int() | UOp(): # sint - if index >= size or index < -size: raise IndexError(f"{index=} is out of bounds with {size=}") - boundary = [index, index+1] if index >= 0 else [index+size, index+size+1] - case slice(): - if index.step == 0: raise ValueError(f"{index=} cannot have 0 as step") - if all(s is None for s in (index.start,index.stop,index.step)): - boundary, stride = [0, size], 1 - elif all(isinstance(s, int) or s is None for s in (index.start,index.stop,index.step)): - # handle int slicing - *boundary, stride = index.indices(cast(SupportsIndex, size)) - if stride * (boundary[1] - boundary[0]) < 0: boundary = [0, 0] - elif stride < 0: boundary = [boundary[1] + 1, boundary[0] + 1] - # update size for slice - size = ceildiv((boundary[1] - boundary[0]), abs(stride)) - elif index.step is None and all(isinstance(s,(int,UOp))for s in (index.start,index.stop)) and resolve((index.stop-index.start) > 0, False): - # simple symbolic slice - boundary = [index.start, index.stop] - size = (index.stop - index.start).ssimplify() - else: raise TypeError(f"slice {index=} is not supported") - case None: pass # do nothing - case _: raise IndexError(f"{type(index).__name__} indexing is not supported") - indices_parsed.append({"index":index, "size":size, "boundary":tuple(boundary), "stride":stride}) - if index is not None: dim += 1 - - # movement op indexing - if mops := [i for i in indices_parsed if i['index'] is not None]: - # flip negative strides - shrinks, strides = zip(*((i['boundary'], i['stride']) for i in mops)) - x = x.shrink(shrinks).flip(tuple(i for i,st in enumerate(strides) if st < 0)) - # handle stride != 1 or -1 - if any(abs(st) != 1 for st in strides): - strides = tuple(abs(s) for s in strides) - # pad shape to multiple of stride - if not all_int(x.shape): raise RuntimeError("symbolic shape not supported") - x = x.pad(tuple((0, round_up(s, st) - s) for s, st in zip(x.shape, strides))) - x = x.reshape(tuple(flatten((s // st, st) for s, st in zip(x.shape, strides)))) - x = x.shrink(tuple(flatten(((0, s), (0, 1)) for s in x.shape[::2]))).reshape(x.shape[::2]) - - # dim injection from None by including None dim size (which is 1) and dim collapse by skipping int dim size - x = x.reshape(tuple(index['size'] for index in indices_parsed if not isinstance(index['index'], (int, UOp)))) - - # tensor indexing - if tops := [(d,i) for d,i in enumerate(i_ for i_ in indices_parsed if not isinstance(i_['index'], int)) if isinstance(i['index'], Tensor)]: - # unload the tensor object into actual tensors - dims, tensors, masks = [d for d,_ in tops], cast(list[Tensor], [i['index'] for _,i in tops]), [] - pre_reduce_shape = x.shape[:dims[0]] + (big_shape := _broadcast_shape(*(t.shape for t in tensors))) + x.shape[dims[0]:] - - # create index masks - for dim, tensor in zip(dims, tensors): - try: i = tensor.reshape(tensor.shape + (1,)*(x.ndim - dims[0])).expand(pre_reduce_shape) - except ValueError as e: raise IndexError(f"cannot broadcast indices: {e}") from e - masks.append(i._one_hot_along_dim(num_classes=x.shape[dim], dim=(dim - x.ndim))) - - # reduce masks to 1 mask - mask: Tensor = functools.reduce(lambda x,y: x.mul(y), masks) - - # inject 1's for the extra dims added in create masks - reshape_arg = x.shape[:dims[0]] + (1,) * len(big_shape) + x.shape[dims[0]:] - # sum reduce the extra dims introduced in create masks - x = (x.reshape(reshape_arg) * mask).sum(sum_axis:=tuple(d + len(big_shape) for d in dims), dtype=x.dtype) - - # special permute case - if dims[0] != 0 and len(dims) != 1 and tuple(dims) != tuple(range(dims[0], dims[-1]+1)): - x = x.permute(*range(dims[0], dims[0]+len(big_shape)), *range(0, dims[0]), *range(dims[0]+len(big_shape), x.ndim)) - - # for advanced setitem, returns whole tensor with indices replaced - if v is not None: - vb = v.cast(self.dtype)._broadcast_to(_broadcast_shape(x.shape, v.shape)) - # add back reduced dims from sum - for dim in sum_axis: vb = vb.unsqueeze(dim) - # run _masked_setitem on tuple of axis that is to be reduced to match self.shape - x = _masked_setitem(self, vb, mask, tuple(range(dims[0], dims[0] + len(big_shape)))) - - return x - - def __getitem__(self, indices) -> Tensor: - """ - Retrieves a sub-tensor using indexing. - - Supported Index Types: `int | slice | Tensor | None | list | tuple | Ellipsis` - - Examples: - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(12).reshape(3, 4) - print(t.numpy()) - ``` - - - Int Indexing: Select an element or sub-tensor using integers for each dimension. - ```python exec="true" source="above" session="tensor" result="python" - print(t[1, 2].numpy()) - ``` - - - Slice Indexing: Select a range of elements using slice notation (`start:end:stride`). - ```python exec="true" source="above" session="tensor" result="python" - print(t[0:2, ::2].numpy()) - ``` - - - Tensor Indexing: Use another tensor as indices for advanced indexing. Using `tuple` or `list` here also works. - ```python exec="true" source="above" session="tensor" result="python" - print(t[Tensor([2, 0, 1]), Tensor([1, 2, 3])].numpy()) - ``` - - - `None` Indexing: Add a new dimension to the tensor. - ```python exec="true" source="above" session="tensor" result="python" - print(t[:, None].shape) - ``` - - NOTE: Out-of-bounds indexing results in a value of `0`. - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3]) - print(t[Tensor([4, 3, 2])].numpy()) - ``` - """ - return self._getitem(indices) - - def __setitem__(self, indices, v:Tensor|ConstType) -> None: - if isinstance(self.device, str) and self.device.startswith("DISK"): - self.realize()._getitem(indices).assign(v) - return - # NOTE: check that setitem target is valid first - if not unwrap(self.uop.st).contiguous: raise RuntimeError("setitem target needs to be contiguous") - if isinstance(v, get_args(ConstType)): v = Tensor(v, device=self.device, dtype=self.dtype) - if not isinstance(v, Tensor): raise TypeError(f"can't set a {type(v).__name__} to a Tensor") - if self.requires_grad or v.requires_grad: raise NotImplementedError("setitem with requires_grad is not supported") - - res = self.realize()._getitem(indices, v) - # if shapes match and data is not shared it's a copy and we assign to self - if res.shape == self.shape and res.uop is not self.uop: - self.assign(res).realize() - else: # no copy, basic setitem - v = v.cast(res.dtype)._broadcast_to(_broadcast_shape(res.shape, v.shape)).contiguous() - res.assign(v).realize() - - def gather(self:Tensor, dim:int, index:Tensor) -> Tensor: - """ - Gathers values along an axis specified by `dim`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2], [3, 4]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.gather(1, Tensor([[0, 0], [1, 0]])).numpy()) - ``` - """ - assert index.ndim == self.ndim, f"self.ndim must equal index.ndim, {self.ndim=}, {index.ndim=}" - dim = self._resolve_dim(dim) - assert all(s >= i for d,(s,i) in enumerate(zip(self.shape, index.shape)) if d != dim), "requires self.shape[d] >= index.shape[d] for all d != dim" - index = index.to(self.device) - x = self.shrink(tuple((0, i) if d != dim else None for d,i in enumerate(index.shape))).unsqueeze(-1).transpose(-1, dim) - return (x * index.unsqueeze(-1)._one_hot_along_dim(self.shape[dim])).sum(-1, dtype=self.dtype) - - def cat(self:Tensor, *args:Tensor, dim:int=0) -> Tensor: - """ - Concatenates self with other `Tensor` in `args` along an axis specified by `dim`. - All tensors must have the same shape except in the concatenating dimension. - - ```python exec="true" source="above" session="tensor" result="python" - t0, t1, t2 = Tensor([[1, 2]]), Tensor([[3, 4]]), Tensor([[5, 6]]) - print(t0.cat(t1, t2, dim=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t0.cat(t1, t2, dim=1).numpy()) - ``` - """ - dim = self._resolve_dim(dim) - for arg in args: assert arg.ndim==self.ndim and all(ti==ai for i,(ti,ai) in enumerate(zip(self.shape, arg.shape)) if i!=dim) - tensors = [self, *args] - dim_cumsum = list(itertools.accumulate([t.shape[dim] for t in tensors], initial=0)) - for i,t in enumerate(tensors): tensors[i] = t.pad([(dim_cumsum[i], dim_cumsum[-1]-dim_cumsum[i+1]) if j==dim else None for j in range(t.ndim)]) - return functools.reduce(Tensor.add, tensors) - - def stack(self:Tensor, *args:Tensor, dim:int=0) -> Tensor: - """ - Concatenates self with other `Tensor` in `args` along a new dimension specified by `dim`. - - ```python exec="true" source="above" session="tensor" result="python" - t0, t1, t2 = Tensor([1, 2]), Tensor([3, 4]), Tensor([5, 6]) - print(t0.stack(t1, t2, dim=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t0.stack(t1, t2, dim=1).numpy()) - ``` - """ - # checks for shapes and number of dimensions delegated to cat - return Tensor.cat(*[t.unsqueeze(dim) for t in [self, *args]], dim=dim) - - def repeat_interleave(self, repeats:int, dim:int|None=None) -> Tensor: - """ - Repeats elements of a tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3]) - print(t.repeat_interleave(2).numpy()) - ``` - """ - x, dim = (self.flatten(), 0) if dim is None else (self, self._resolve_dim(dim)) - shp = x.shape - return x.reshape(*shp[:dim+1], 1, *shp[dim+1:]).expand(*shp[:dim+1], repeats, *shp[dim+1:]).reshape(*shp[:dim], shp[dim]*repeats, *shp[dim+1:]) - - def repeat(self, repeats, *args) -> Tensor: - """ - Repeats tensor number of times along each dimension specified by `repeats`. - `repeats` can be passed as a tuple or as separate arguments. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3]) - print(t.repeat(4, 2).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.repeat(4, 2, 1).shape) - ``` - """ - repeats = argfix(repeats, *args) - base_shape = _align_left(self.shape, repeats)[0] - unsqueezed_shape = flatten([[1, s] for s in base_shape]) - expanded_shape = flatten([[r, s] for r,s in zip(repeats, base_shape)]) - final_shape = [r*s for r,s in zip(repeats, base_shape)] - return self.reshape(unsqueezed_shape).expand(expanded_shape).reshape(final_shape) - - def _resolve_dim(self, dim:int, *, extra:bool=False) -> int: - total = self.ndim + int(extra) - if not -max(1, total) <= dim <= max(1, total)-1: raise IndexError(f"{dim=} out of range {[-max(1, total), max(1, total)-1]}") - return dim + total if dim < 0 else dim - - def split(self, sizes:int|Sequence[int], dim:int=0) -> tuple[Tensor, ...]: - """ - Splits the tensor into chunks along the dimension specified by `dim`. - If `sizes` is an integer, it splits into equally sized chunks if possible, otherwise the last chunk will be smaller. - If `sizes` is a list, it splits into `len(sizes)` chunks with size in `dim` according to `size`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(10).reshape(5, 2) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - split = t.split(2) - print("\\n".join([repr(x.numpy()) for x in split])) - ``` - ```python exec="true" source="above" session="tensor" result="python" - split = t.split([1, 4]) - print("\\n".join([repr(x.numpy()) for x in split])) - ``` - """ - assert all_int(self.shape), f"does not support symbolic shape {self.shape}" - dim = self._resolve_dim(dim) - if isinstance(sizes, int): sizes = [min(sizes, self.shape[dim]-i) for i in range(0, max(1, self.shape[dim]), max(1, sizes))] - assert sum(sizes) == self.shape[dim], f"expect sizes to sum exactly to {self.shape[dim]}, but got {sum(sizes)}" - return tuple(self[sl] for sl in [tuple([slice(None)]*dim + [slice(sum(sizes[:i]), sum(sizes[:i + 1]))]) for i in range(len(sizes))]) - - def chunk(self, chunks:int, dim:int=0) -> list[Tensor]: - """ - Splits the tensor into `chunks` number of chunks along the dimension `dim`. - If the tensor size along `dim` is not divisible by `chunks`, all returned chunks will be the same size except the last one. - The function may return fewer than the specified number of chunks. - - ```python exec="true" source="above" session="tensor" result="python" - chunked = Tensor.arange(11).chunk(6) - print("\\n".join([repr(x.numpy()) for x in chunked])) - ``` - ```python exec="true" source="above" session="tensor" result="python" - chunked = Tensor.arange(12).chunk(6) - print("\\n".join([repr(x.numpy()) for x in chunked])) - ``` - ```python exec="true" source="above" session="tensor" result="python" - chunked = Tensor.arange(13).chunk(6) - print("\\n".join([repr(x.numpy()) for x in chunked])) - ``` - """ - assert all_int(self.shape), f"does not support symbolic shape {self.shape}" - assert chunks > 0, f"expect chunks to be greater than 0, got: {chunks}" - dim = self._resolve_dim(dim) - return list(self.split(ceildiv(self.shape[dim], chunks) if self.shape[dim] else [0]*chunks, dim=dim)) - - def unfold(self, dim:int, size:sint, step:int) -> Tensor: - """ - Unfolds the tensor along dimension `dim` into overlapping windows. - - Each window has length `size` and begins every `step` elements of `self`. - Returns the input tensor with dimension `dim` replaced by dims `(n_windows, size)` - where `n_windows = (self.shape[dim] - size) // step + 1`. - - ```python exec="true" source="above" session="tensor" result="python" - unfolded = Tensor.arange(8).unfold(0,2,2) - print("\\n".join([repr(x.numpy()) for x in unfolded])) - ``` - ```python exec="true" source="above" session="tensor" result="python" - unfolded = Tensor.arange(27).reshape(3,3,3).unfold(-1,2,3) - print("\\n".join([repr(x.numpy()) for x in unfolded])) - ``` - """ - if size < 0: raise RuntimeError(f'size must be >= 0 but got {size=}') - if step <= 0: raise RuntimeError(f'step must be > 0 but got {step=}') - if size > self.shape[dim]: raise RuntimeError(f'maximum size for tensor at dimension {dim} is {self.shape[dim]} but size is {size}') - dim = self._resolve_dim(dim) - perm_to_last = tuple(i for i in range(self.ndim) if i != dim) + (dim,) - return self.permute(perm_to_last)._pool((size,), step).permute(argsort(perm_to_last) + (self.ndim,)) - - def meshgrid(self:Tensor, *args:Tensor, indexing:Literal["ij", "xy"]="ij") -> tuple[Tensor, ...]: - """ - Generates coordinate matrices from coordinate vectors. - Input tensors can be scalars or 1D tensors. - - `indexing` determines how the output grids are aligned. - `ij` indexing follows matrix-style indexing and `xy` indexing follows Cartesian-style indexing. - - ```python exec="true" source="above" session="tensor" result="python" - x, y = Tensor([1, 2, 3]), Tensor([4, 5, 6]) - grid_x, grid_y = x.meshgrid(y) - print(grid_x.numpy()) - print(grid_y.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - grid_x, grid_y = x.meshgrid(y, indexing="xy") - print(grid_x.numpy()) - print(grid_y.numpy()) - ``` - """ - if indexing not in ("ij", "xy"): raise RuntimeError(f'indexing must be in ("ij", "xy"), got {indexing}') - if len(tensors:=(self, *args)) == 1: return tensors - basis = tuple(range(len(tensors))) if indexing == "ij" else (1, 0) + tuple(range(2, len(tensors))) - tensors = tuple(t.reshape((-1,) + (1,)*(len(args) - i)) for i,t in zip(basis, tensors)) - output_shape = _broadcast_shape(*(t.shape for t in tensors)) - return tuple(t._broadcast_to(output_shape) for t in tensors) - - def squeeze(self, dim:int|None=None) -> Tensor: - """ - Returns a tensor with specified dimensions of input of size 1 removed. - If `dim` is not specified, all dimensions with size 1 are removed. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.zeros(2, 1, 2, 1, 2) - print(t.squeeze().shape) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.squeeze(0).shape) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.squeeze(1).shape) - ``` - """ - if dim is None: return self.reshape(tuple(dim for dim in self.shape if dim != 1)) - dim = self._resolve_dim(dim) - return self if not self.ndim or self.shape[dim] != 1 else self.reshape(self.shape[:dim] + self.shape[dim+1:]) - - def unsqueeze(self, dim:int) -> Tensor: - """ - Returns a tensor with a new dimension of size 1 inserted at the specified `dim`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4]) - print(t.unsqueeze(0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.unsqueeze(1).numpy()) - ``` - """ - dim = self._resolve_dim(dim, extra=True) - return self.reshape(self.shape[:dim] + (1,) + self.shape[dim:]) - - @property - def T(self) -> Tensor: - """`.T` is an alias for `.transpose()`.""" - return self.transpose() - - def transpose(self, dim0=1, dim1=0) -> Tensor: - """ - Returns a tensor that is a transposed version of the original tensor. - The given dimensions `dim0` and `dim1` are swapped. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(6).reshape(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.transpose(0, 1).numpy()) - ``` - """ - order = list(range(self.ndim)) - order[dim0], order[dim1] = order[dim1], order[dim0] - return self.permute(order) - - def flatten(self, start_dim=0, end_dim=-1) -> Tensor: - """ - Flattens the tensor by reshaping it into a one-dimensional tensor. - If `start_dim` or `end_dim` are passed, only dimensions starting with `start_dim` and ending with `end_dim` are flattened. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(8).reshape(2, 2, 2) - print(t.flatten().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.flatten(start_dim=1).numpy()) - ``` - """ - start_dim, end_dim = self._resolve_dim(start_dim), self._resolve_dim(end_dim) - return self.reshape(self.shape[:start_dim] + (prod(self.shape[start_dim:end_dim+1]), ) + self.shape[end_dim+1:]) - - def unflatten(self, dim:int, sizes:tuple[int,...]) -> Tensor: - """ - Unflattens dimension `dim` of the tensor into multiple dimensions specified by `sizes`. `Tensor.flatten()` is the inverse of this function. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(3, 4, 1).unflatten(1, (2, 2)).shape) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(3, 4, 1).unflatten(1, (-1, 2)).shape) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(5, 12, 3).unflatten(-2, (2, 2, 3, 1, 1)).shape) - ``` - """ - dim = self._resolve_dim(dim) - return self.reshape(self.shape[:dim] + sizes + self.shape[dim+1:]) - - def roll(self, shifts:int|tuple[int, ...], dims:int|tuple[int, ...]) -> Tensor: - """ - Rolls the tensor along specified dimension(s). - The rolling operation is circular, meaning that elements that go beyond the edge are wrapped around to the beginning of the dimension. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(4) - print(t.roll(shifts=1, dims=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.roll(shifts=-1, dims=0).numpy()) - ``` - """ - dims, rolled = tuple(self._resolve_dim(d) for d in make_tuple(dims, 1)), self - for dim, shift in zip(dims, make_tuple(shifts, 1)): - shift = shift % self.shape[dim] - rolled = Tensor.cat(rolled[tuple(slice(None) if i != dim else slice(-shift, None) for i in range(rolled.ndim))], - rolled[tuple(slice(None) if i != dim else slice(None, -shift) for i in range(rolled.ndim))], dim=dim) - return rolled - - def rearrange(self, formula:str, **sizes) -> Tensor: - """ - Rearranges input according to formula - - See: https://einops.rocks/api/rearrange/ - - ```python exec="true" source="above" session="tensor" result="python" - x = Tensor([[1, 2], [3, 4]]) - print(Tensor.rearrange(x, "batch channel -> (batch channel)").numpy()) - ``` - """ - def parse_formula(formula: str): - tokens = f" {formula} ".replace("…", "...").replace("(", " ( ").replace(")", " ) ").replace(" ", " ").replace(" 1 ", " ( ) ").split() - lparens, rparens = map(lambda x: [i for i, ch in enumerate(tokens) if ch == x], ("(", ")")) - pairs = list(zip(lparens, rparens)) - assert len(lparens) == len(rparens) and sorted(flatten(pairs)) == flatten(pairs), "bracket mismatch" - return [name for name in tokens if name not in ("(", ")")], [(s - 2*i, e - 1 - 2*i) for i, (s, e) in enumerate(pairs)] - - assert formula.count("->") == 1, 'need exactly one "->" in formula' - - (lhs, unflatten_dims), (rhs, flatten_dims) = map(parse_formula, formula.split("->")) - - for name in sizes: assert name in lhs, f"axis {name} is not used in transform" - assert sorted(lhs) == sorted(rhs) and len(lhs) == len(set(lhs)), f"name mismatch in {formula}" - for name in flatten((lhs, rhs)): assert name == "..." or (name.isidentifier() and "_" not in (name[0], name[-1])), f"invalid axis name {name}" - assert "..." not in flatten([lhs[s:e] for s, e in unflatten_dims]), f"cannot have collapsed ellipsis (...) in lhs of {formula}" - assert lhs.count("...") <= 1, f"too many ellipses in {formula}" - - # resolve ellipsis - if "..." in lhs: ell_len = len(self.shape) - len(lhs) + 1 + sum(e - s - 1 for s, e in unflatten_dims) - lhs, rhs = map(lambda l: l[:(i:=l.index("..."))] + [f"...{j}" for j in range(ell_len)] + l[i + 1:] if "..." in l else l, (lhs, rhs)) - unflatten_dims = [(s + (ell_len - 1 if "...0" in lhs[:s] else 0), e + (ell_len - 1 if "...0" in lhs[:e] else 0)) for s, e in unflatten_dims] - flatten_dims = [(s + (ell_len - 1 if "...0" in rhs[:s] else 0), e + (ell_len - 1 if "...0" in rhs[:e] else 0)) for s, e in flatten_dims] - - # apply movement ops in order unflatten -> permute -> flatten/unsqueeze - t = functools.reduce(lambda x, dims: x.unflatten(dims[0], tuple(sizes.get(lhs[d], -1) for d in range(*dims))), unflatten_dims, self) - for i, name in enumerate(lhs): assert (name not in sizes) or sizes[name] == t.shape[i], f"size provided for dimension {name} incorrect" - t = t.permute([lhs.index(name) for name in rhs]) - return functools.reduce(lambda x, dims: x.flatten(dims[0], dims[1] - 1) if dims[0] Tensor: - """ - Replaces `self` with `value` wherever the elements of `mask` are True. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4, 5]) - mask = Tensor([True, False, True, False, False]) - print(t.masked_fill(mask, -12).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3, 4, 5]) - mask = Tensor([True, False, True, False, False]) - value = Tensor([-1, -2, -3, -4, -5]) - print(t.masked_fill(mask, value).numpy()) - ``` - """ - return mask.where(value, self) - - # ***** reduce ops ***** - - def _reduce(self, op:Ops, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - axis = tuple(self._resolve_dim(x) for x in (range(self.ndim) if axis is None else make_tuple(axis, 1))) - if self.ndim == 0: axis = () - ret = self._apply_uop(UOp.r, op=op, axis=axis) - return ret if keepdim else ret.reshape(tuple(s for i,s in enumerate(self.shape) if i not in axis)) - - def sum(self, axis:int|Sequence[int]|None=None, keepdim=False, dtype:DTypeLike|None=None) -> Tensor: - """ - Returns the sum of the elements of the tensor along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the maximum is computed and whether the reduced dimensions are retained. - - You can pass in `dtype` keyword argument to control the data type of the accumulation. - If not specified, the accumulation data type is chosen based on the input tensor's data type. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(6).reshape(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.sum().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.sum(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.sum(axis=1).numpy()) - ``` - """ - ret = self.cast(sum_acc_dtype(self.dtype) if dtype is None else dtype)._reduce(Ops.ADD, axis, keepdim) - return ret.cast(self.dtype) if dtype is None and self.dtype in (dtypes.float16, dtypes.bfloat16) else ret - - def prod(self, axis:int|Sequence[int]|None=None, keepdim=False, dtype:DTypeLike|None=None) -> Tensor: - """ - Returns the product of the elements of the tensor along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the maximum is computed and whether the reduced dimensions are retained. - - You can pass in `dtype` keyword argument to control the data type of the accumulation. - If not specified, the accumulation data type is chosen based on the input tensor's data type. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, -2, -3, 1, 2, 3]).reshape(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.prod().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.prod(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.prod(axis=1).numpy()) - ``` - """ - return self.cast(dtype if dtype is not None else self.dtype)._reduce(Ops.MUL, axis, keepdim) - - def max(self, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - """ - Returns the maximum value of the tensor along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the maximum is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 0, 2], [5, 4, 3]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.max().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.max(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.max(axis=1, keepdim=True).numpy()) - ``` - """ - return self._reduce(Ops.MAX, axis, keepdim) - - def _inverse(self) -> Tensor: return -self if self.is_floating_point() else ~self if dtypes.is_int(self.dtype) else self.logical_not() - - def min(self, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - """ - Returns the minimum value of the tensor along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the minimum is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 0, 2], [5, 4, 3]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.min().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.min(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.min(axis=1, keepdim=True).numpy()) - ``` - """ - return self._inverse().max(axis=axis, keepdim=keepdim)._inverse() - - def any(self, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - """ - Tests if any element evaluates to `True` along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the reduce axis and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[True, True], [True, False], [False, False]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.any().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.any(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.any(axis=1, keepdim=True).numpy()) - ``` - """ - return self.bool().max(axis, keepdim) - - def all(self, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - """ - Tests if all element evaluates to `True` along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the reduce axis and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[True, True], [True, False], [False, False]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.all().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.all(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.all(axis=1, keepdim=True).numpy()) - ``` - """ - return self.logical_not().any(axis, keepdim).logical_not() - - def isclose(self, other:Tensor, rtol:float=1e-05, atol:float=1e-08, equal_nan=False) -> Tensor: - """ - Returns a new tensor with element-wise comparison of closeness to `other` within a tolerance. - - The `rtol` and `atol` keyword arguments control the relative and absolute tolerance of the comparison. - - By default, two `NaN` values are not close to each other. If `equal_nan` is `True`, two `NaN` values are considered close. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1e-7, 1e-8, 1e-9, float('nan')]).isclose(Tensor([0.0, 0.0, 0.0, float('nan')])).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([float('nan')]).isclose(Tensor([float('nan')]), equal_nan=True).numpy()) - ``` - """ - is_finite_close = self.isfinite() & other.isfinite() & ((self - other).abs() <= atol + rtol * other.abs()) - is_infinite_close = (self.isinf() | other.isinf()) & (self == other) - is_nan_close = (self.isnan() & other.isnan()) & equal_nan - return is_finite_close | is_infinite_close | is_nan_close - - def mean(self, axis:int|Sequence[int]|None=None, keepdim=False) -> Tensor: - """ - Returns the mean value of the tensor along the specified axis or axes. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the mean is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.normal(2, 3, mean=2.5, std=0.5) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.mean().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.mean(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.mean(axis=1).numpy()) - ``` - """ - output_dtype = self.dtype if dtypes.is_float(self.dtype) else dtypes.float32 - numerator = self.cast(sum_acc_dtype(self.dtype)).sum(axis=axis, keepdim=keepdim) - return numerator.div(prod([cast(int, si) for si, so in zip(self.shape, self.sum(axis=axis, keepdim=True).shape) if resolve(si != so)])) \ - .cast(output_dtype) - - def var(self, axis:int|Sequence[int]|None=None, keepdim=False, correction=1) -> Tensor: - """ - Returns the variance of the tensor along the specified axis or axes. - - You can pass in `axis`, `keepdim`, and `correction` keyword arguments to control the axis along - which the variance is computed, whether the reduced dimensions are retained, and the Bessel's correction applied. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.normal(2, 3, mean=2.5, std=0.5) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.var().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.var(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.var(axis=1).numpy()) - ``` - """ - squares = (self - self.mean(axis=axis, keepdim=True)).square() - n = prod([si for si, so in zip(self.shape, squares.sum(axis=axis, keepdim=True).shape) if resolve(si != so)]) - return squares.sum(axis=axis, keepdim=keepdim).div(smax([0, n-correction])) - - def var_mean(self, axis:int|Sequence[int]|None=None, keepdim=False, correction=1) -> tuple[Tensor, Tensor]: - """ - Calculates the variance and mean over the dimensions specified by dim. - Syntactic sugar around `Tensor.var` and `Tensor.mean` to match `torch.var_mean`. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.normal(2, 3, mean=2.5, std=0.5) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - var, mean = t.var_mean() - print(var.numpy(), mean.numpy()) - ``` - """ - return self.var(axis, keepdim, correction), self.mean(axis, keepdim) - - def std(self, axis:int|Sequence[int]|None=None, keepdim=False, correction=1) -> Tensor: - """ - Returns the standard deviation of the tensor along the specified axis or axes. - - You can pass in `axis`, `keepdim`, and `correction` keyword arguments to control the axis along - which the standard deviation is computed, whether the reduced dimensions are retained, and the Bessel's correction applied. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.normal(2, 3, mean=2.5, std=0.5) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.std().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.std(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.std(axis=1).numpy()) - ``` - """ - return self.var(axis, keepdim, correction).sqrt() - - def std_mean(self, axis:int|Sequence[int]|None=None, keepdim=False, correction=1) -> tuple[Tensor, Tensor]: - """ - Calculates the standard deviation and mean over the dimensions specified by dim. - Syntactic sugar around `Tensor.std` and `Tensor.mean` to match `torch.std_mean`. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.normal(2, 3, mean=2.5, std=0.5) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - std, mean = t.std_mean() - print(std.numpy(), mean.numpy()) - ``` - """ - return self.std(axis, keepdim, correction), self.mean(axis, keepdim) - - def keccak(self, cfg:str|tuple[int, int] = "sha3_256"): - """ - Calculates a Keccak hash over the last dimension. Uses "sha3_256" by default. - - ```python exec="false" source="above" session="tensor" result="python" - t = Tensor(b"Hello World!").keccak() - print(t.data().hex()) - ``` - """ - - # https://keccak.team/keccak_specs_summary.html - - def ctensor(l: Sequence[ConstType], dtype: DType = dtypes.uint64): return Tensor.stack(*(Tensor(v, dtype=dtype, device=self.device) for v in l)) - rot_offsets = [44, 43, 21, 14, 28, 20, 3, 45, 61, 1, 6, 25, 8, 18, 27, 36, 10, 15, 56, 62, 55, 39, 41, 2] - rot_offsets_v0, rot_offsets_v1 = ctensor([0] + [1 << v for v in rot_offsets]), ctensor([1] + [1 << (64 - v) for v in rot_offsets]) - - # calculated from π step - reorder_indexes = [0,6,12,18,24,3,9,10,16,22,1,7,13,19,20,4,5,11,17,23,2,8,14,15,21] - rnd_const_masks = [ctensor([v]).pad((0, 24)) for v in (1, 0x8082, 0x800000000000808a, 0x8000000080008000, 0x808b, 0x80000001, 0x8000000080008081, - 0x8000000000008009, 0x8a, 0x88, 0x80008009, 0x8000000a, 0x8000808b, 0x800000000000008b, 0x8000000000008089, 0x8000000000008003, - 0x8000000000008002, 0x8000000000000080, 0x800a, 0x800000008000000a, 0x8000000080008081, 0x8000000000008080, 0x80000001, 0x8000000080008008)] - - rate, dsbyte = { "sha3_224": (144, 6), "sha3_256": (136, 6), "shake_128": (168, 31) }[cfg] if isinstance(cfg, str) else cfg - data, data_pad = self.bitcast(dtypes.uint8).reshape(prod(self.shape[:-1]), -1), rate - (self.shape[-1] * self.dtype.itemsize % rate) - # pad batches then pad blocks - data = data.pad((None, (0, data_pad))).reshape(data.shape[0], -1, rate).pad((None, None, (0, 200 - rate))).flatten(1) - - # create pad mask - lbe = data.shape[1] + rate - data_pad - 200 - if data_pad == 1: mb = [(lbe, 0), (1, dsbyte ^ 0x80), (data.shape[-1] - lbe - 1, 0)] - else: mb = [(lbe, 0), (1, dsbyte), (data.shape[-1] + rate - lbe - 202, 0), (1, 0x80), (200 - rate, 0)] - pad_mask = Tensor.cat(*(Tensor(v, dtype=dtypes.uint8, device=data.device).expand(l) for l, v in mb if l > 0)) - - data = (data ^ pad_mask).reshape(data.shape[0], -1, 200).bitcast(dtypes.uint64) - - state = Tensor.zeros((data.shape[0], 25), device=self.device, dtype=dtypes.uint64) - for k in range(int(data.shape[1])): - state = state.bitwise_xor(data[:,k].reshape(-1, 25)) - for i in range(24): # f1600 - # θ step - p = state.reshape((-1, 5, 5)).transpose(2, 1) - t1 = (p[:,:,0] ^ p[:,:,1] ^ p[:,:,2] ^ p[:,:,3] ^ p[:,:,4]).roll(-1, 1) # xor reduce - state = state ^ (t1.roll(2, 1).bitwise_xor((t1 << 1) ^ (t1 >> 63)).unsqueeze(2).expand((-1, -1, 5)).transpose(2, 1).flatten(1)) - # ρ and π steps - state = state[:,reorder_indexes] - state = (state * rot_offsets_v0).bitwise_or(state // rot_offsets_v1).reshape((-1, 5, 5)) - # χ and ι step - state = state.bitwise_xor((state.roll(shifts=-1, dims=2) ^ -1) & state.roll(shifts=-2, dims=2)).flatten(1) ^ rnd_const_masks[i] - return state.bitcast(dtypes.uint8)[:,:(200 - rate) // 2].reshape(*self.shape[:-1], -1) - - def _softmax(self, axis, dtype:DTypeLike|None=None) -> tuple[Tensor, Tensor, Tensor]: - m = self - self.max(axis=axis, keepdim=True).detach() - if dtype is not None: m = m.cast(dtype) - e = m.exp() - return m, e, e.sum(axis=axis, keepdim=True) - - def softmax(self, axis=-1, dtype:DTypeLike|None=None, _single_kernel=getenv("SINGLE_KERNEL_SOFTMAX")) -> Tensor: - """ - Applies the softmax function to the tensor along the specified axis. - - Rescales the elements of the tensor such that they lie in the range [0, 1] and sum to 1. - - You can pass in the `axis` keyword argument to control the axis along which the softmax is computed. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.softmax().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.softmax(axis=0).numpy()) - ``` - """ - if _single_kernel: - _, e, ss = self.contiguous()._softmax(axis, dtype) - return e.div(ss).fuse() - _, e, ss = self._softmax(axis, dtype) - return e.div(ss) - - def log_softmax(self, axis=-1, dtype:DTypeLike|None=None) -> Tensor: - """ - Applies the log-softmax function to the tensor along the specified axis. - - The log-softmax function is a numerically stable alternative to the softmax function in log space. - - You can pass in the `axis` keyword argument to control the axis along which the log-softmax is computed. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.log_softmax().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.log_softmax(axis=0).numpy()) - ``` - """ - m, _, ss = self._softmax(axis, dtype) - return m - ss.log() - - def logsumexp(self, axis=None, keepdim=False) -> Tensor: - """ - Computes the log-sum-exp of the tensor along the specified axis or axes. - - The log-sum-exp function is a numerically stable way to compute the logarithm of the sum of exponentials. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the log-sum-exp is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logsumexp().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logsumexp(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logsumexp(axis=1).numpy()) - ``` - """ - m = self.max(axis=axis, keepdim=True) - return (self - m).exp().sum(axis=axis, keepdim=keepdim).log() + m.squeeze(axis) - - def logcumsumexp(self, axis=0) -> Tensor: - """ - Computes the log-cumsum-exp of the tensor along the specified axis or axes. - - The log-cumsum-exp function is a numerically stable way to compute the logarithm of the cumulative sum of exponentials. - - You can pass in the `axis` keyword argument to control the axis along which - the log-cum-sum-exp is computed. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logcumsumexp().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logcumsumexp(axis=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.logcumsumexp(axis=1).numpy()) - ``` - """ - if self.ndim == 0: return self - axis = self._resolve_dim(axis) - x = self.transpose(axis, -1) - last_dim_size = x.shape[-1] - x_reshaped = x.reshape(-1, last_dim_size) - x_cummax = x_reshaped.cummax(-1).unsqueeze(-1) - x_expand = x_reshaped.unsqueeze(1).expand(*x_reshaped.shape, last_dim_size) - mask = Tensor.ones(last_dim_size, last_dim_size, requires_grad=False, device=self.device).tril().unsqueeze(0) - ret = ((x_expand - x_cummax).exp() * mask).sum(-1).log() + x_cummax.squeeze(-1) - return ret.reshape(*x.shape).transpose(-1, axis) - - def argmax(self, axis=None, keepdim=False) -> Tensor: - """ - Returns the indices of the maximum value of the tensor along the specified axis. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the maximum is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 0, 2], [5, 4, 3]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmax().numpy()) # Returns the index of the maximum value in the flattened tensor. - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmax(axis=0).numpy()) # Returns the indices of the maximum values along axis 0. - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmax(axis=1).numpy()) # Returns the indices of the maximum values along axis 1. - ``` - """ - if axis is None: return self.flatten().argmax(0) - axis = self._resolve_dim(axis) - m = self == self.max(axis=axis, keepdim=True) - idx = m * Tensor.arange(self.shape[axis],0,-1, requires_grad=False, device=self.device).reshape(self.shape[axis], *[1]*(self.ndim-axis-1)) - return (self.shape[axis]-idx.max(axis=axis, keepdim=keepdim)).cast(dtypes.int32) - - def argmin(self, axis=None, keepdim=False) -> Tensor: - """ - Returns the indices of the minimum value of the tensor along the specified axis. - - You can pass in `axis` and `keepdim` keyword arguments to control the axis along - which the minimum is computed and whether the reduced dimensions are retained. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 0, 2], [5, 4, 3]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmin().numpy()) # Returns the index of the minimum value in the flattened tensor. - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmin(axis=0).numpy()) # Returns the indices of the minimum values along axis 0. - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.argmin(axis=1).numpy()) # Returns the indices of the minimum values along axis 1. - ``` - """ - return self._inverse().argmax(axis=axis, keepdim=keepdim) - - @staticmethod - def einsum(formula:str, *operands:Tensor|Sequence[Tensor], dtype:DTypeLike|None=None) -> Tensor: - """ - Sums the product of the elements of the input tensors according to a formula based on the Einstein summation convention. - - See: https://pytorch.org/docs/stable/generated/torch.einsum.html - - ```python exec="true" source="above" session="tensor" result="python" - x = Tensor([[1, 2], [3, 4]]) - y = Tensor([[5, 6], [7, 8]]) - print(Tensor.einsum("ij,ij->", x, y).numpy()) - ``` - """ - def parse_formula(formula:str, *operands:Tensor): - if "..." in (formula := formula.replace(" ", "")): - ell_chars, ell_longest = "".join(set(string.ascii_letters) - set(formula)), 0 - for i, inp in enumerate(filter(lambda x: "..." in x, inputs := formula.split("->")[0].split(","))): - if (ell_count := max(operands[i].ndim, 1) - (len(inp) - len("..."))) > ell_longest: ell_longest = ell_count - inputs[i] = inp.replace("...", ell_chars[-ell_count:]) - inputs_str, out_ellipse = ",".join(inputs), ell_chars[-ell_longest:] - return (inputs_str, formula.split("->")[1].replace("...", out_ellipse)) if "->" in formula else \ - (inputs_str, out_ellipse + ''.join(sorted(c for c in inputs_str if inputs_str.count(c) == 1 and c.isalpha() and c not in out_ellipse))) - return formula.split("->") if "->" in formula else (formula, ''.join(c for c in sorted(formula) if formula.count(c) == 1 and c.isalpha())) - - xs:tuple[Tensor, ...] = argfix(*operands) - inputs_str, output = parse_formula(formula, *xs) - inputs = inputs_str.split(",") - assert len(xs) == len(inputs), f"number of inputs doesn't match number of operands in formula, expected {len(inputs)}, got {len(xs)}" - - # map the value of each letter in the formula - letter_val = sorted(merge_dicts([dict(zip(letters, tensor.shape)) for letters, tensor in zip(inputs, xs)]).items()) - - xs_:list[Tensor] = [] - lhs = [sorted(enumerate(s), key=lambda e:e[1]) for s in inputs] - for x,(order,letters) in zip(xs, [list(zip(*l)) for l in lhs]): - # permute to the sorted letter order, then reshape/expand to create dimensions for the missing letters - xs_.append(x.permute(order).reshape([val if letter in letters else 1 for letter,val in letter_val]).expand([val for _,val in letter_val])) - - # ordinal encode the output alphabet - rhs_order = argsort(argsort(list(output))) - - # sum over all axes that's not in the output, then permute to the output order - return functools.reduce(lambda a,b:a*b, xs_) \ - .sum(axis=[axis for axis,(letter,_) in enumerate(letter_val) if letter not in output], dtype=dtype).permute(rhs_order) - - # ***** processing ops ***** - - def _pool(self, k_:tuple[sint, ...], stride:int|tuple[int, ...]=1, dilation:int|tuple[int, ...]=1) -> Tensor: - assert len(self.shape) >= len(k_), f"can't pool {self.shape} with {k_}" - s_, d_ = make_tuple(stride, len(k_)), make_tuple(dilation, len(k_)) - assert len(k_) == len(s_) == len(d_), f"stride/dilation mismatch kernel:{k_} stride:{s_} dilation:{d_}" - noop, i_ = [None] * (self.ndim-len(k_)), self.shape[-len(k_):] - assert all(resolve(d*(k-1)+1 <= i) for k,d,i in zip(k_,d_,i_)), "kernel size cannot be greater than actual input size" - o_ = [ceildiv(i-d*(k-1), s) for i,d,k,s in zip(i_,d_,k_,s_)] - if any(resolve(k > s) for k,s in zip(k_,s_)) or any(d != 1 for d in d_): - # input size scaling factor to make sure shrink for stride is possible - f_ = [1 + int(resolve(o*s > (i - d*(k-1)))) for o,s,i,d,k in zip(o_,s_,i_,d_,k_)] - # # repeats such that we don't need padding - x = self.repeat([1]*len(noop) + [ceildiv(k*(i*f+d),i) for k,i,d,f in zip(k_,i_,d_,f_)]) - # handle dilation - x = x.shrink(tuple(noop + [(0,k*(i*f+d)) for k,i,d,f in zip(k_,i_,d_,f_)])).reshape(noop + flatten((k,(i*f+d)) for k,i,d,f in zip(k_,i_,d_,f_))) - # handle stride - x = x.shrink(tuple(noop + flatten(((0,k), (0,o*s)) for k,o,s in zip(k_,o_,s_)))).reshape(noop + flatten((k,o,s) for k,o,s in zip(k_,o_,s_))) - x = x.shrink(tuple(noop + flatten(((0,k), (0,o), (0,1)) for k,o in zip(k_,o_)))).reshape(noop + flatten((k,o) for k,o in zip(k_,o_))) - # permute to move reduce to the end - return x.permute(*range(len(noop)), *[len(noop)+i*2+1 for i in range(len(i_))], *[len(noop)+i*2 for i in range(len(i_))]) - # TODO: once the shapetracker can optimize well, remove this alternative implementation - x = self.pad(tuple(noop + [(0, max(0,o*s-i)) for i,o,s in zip(i_,o_,s_)])).shrink(tuple(noop + [(0,o*s) for o,s in zip(o_,s_)])) - x = x.reshape(noop + flatten(((o,s) for o,s in zip(o_,s_)))) - x = x.shrink(tuple(noop + flatten(((0,o), (0,k)) for o,k in zip(o_,k_)))) - return x.permute(*range(len(noop)), *[len(noop)+i*2 for i in range(len(i_))], *[len(noop)+i*2+1 for i in range(len(i_))]) - - def _resolve_pool_pads(self, padding:int|Sequence[int], dims:int) -> Sequence[int]: - if not isinstance(padding, int) and not (len(padding) == 2*dims or len(padding) == dims): - raise ValueError(f"Padding must be an int or a sequence of length {dims} or {2*dims}, but got {padding=} for {self.shape=} with {dims=}.") - return [padding]*2*dims if isinstance(padding, int) else (padding if len(padding) == 2*dims else [p for p in padding for _ in range(2)][::-1]) - - def _apply_ceil_mode(self, pads:Sequence[int], k_:tuple[sint, ...], s_:int|tuple[int, ...], d_:int|tuple[int, ...]) -> list[int]: - (d_,s_), i_ = (make_tuple(x, len(k_)) for x in (d_,s_)), self.shape[-len(k_):] - pads, grouped_pads = list(pads), _flat_to_grouped(pads) - # https://arxiv.org/pdf/1603.07285 section 5.1, relationship 15. - o_ = [ceildiv(i+pB+pA - (d*(k-1)+1), s) + 1 for i,d,k,s,(pB,pA) in zip(i_,d_,k_,s_,grouped_pads)] - for dim,(o,i,s,k,d,(pB,pA)) in enumerate(zip(o_,i_,s_,k_,d_,grouped_pads)): - # we have to do additional padding before `_pool` so that `o_` in `_pool` is calculated correctly - # `s*(o-1) + (d*(k-1)+1) - (i+pB+pA)` -> last_sliding_window_start + full_kernel_size - padded_input_shape - # we decrease padding in the case that a sliding window starts in the end padded region, thereby decreasing `o_` in `_pool` - # `smax(s*(o-1) - (pB+i-1), 0)` -> last_sliding_window_start - (pad_before + input_size - zero_offset) - pads[-1-dim*2] += s*(o-1) + (d*(k-1)+1) - (i+pB+pA) - smax(s*(o-1) - (pB+i-1), 0) - return pads - - # NOTE: these work for more than 2D - def avg_pool2d(self, kernel_size:tuple[int, ...]=(2,2), stride=None, dilation=1, padding:int|tuple[int, ...]=0, - ceil_mode=False, count_include_pad=True) -> Tensor: - """ - Applies average pooling over a tensor. - - This function supports three different types of `padding` - - 1. `int` (single value): - Applies the same padding value uniformly to all spatial dimensions. - - 2. `tuple[int, ...]` (length = number of spatial dimensions): - Specifies a distinct padding value for each spatial dimension in the form `(padding_height, padding_width, ...)`. - - 3. `tuple[int, ...]` (length = 2 * number of spatial dimensions): - Specifies explicit padding for each side of each spatial dimension in the form - `(padding_left, padding_right, padding_top, padding_bottom, ...)`. - - When `ceil_mode` is set to `True`, output shape will be determined using ceil division. - When `count_include_pad` is set to `False`, zero padding will not be included in the averaging calculation. - - NOTE: unlike PyTorch, this implementation is not limited to only 2d pooling and instead works for any number of dimensions. - - See: https://paperswithcode.com/method/average-pooling - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(25).reshape(1, 1, 5, 5) - print(t.avg_pool2d().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.avg_pool2d(ceil_mode=True).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.avg_pool2d(padding=1).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.avg_pool2d(padding=1, count_include_pad=False).numpy()) - ``` - """ - axis = tuple(range(-len(k_ := make_tuple(kernel_size, 2)), 0)) - def pool(x:Tensor, padding_:Sequence[int]) -> Tensor: return x.pad(padding_)._pool(k_, stride if stride is not None else k_, dilation) - reg_pads = self._resolve_pool_pads(padding, len(k_)) - ceil_pads = self._apply_ceil_mode(reg_pads, k_, stride if stride is not None else k_, dilation) - if not count_include_pad: - pads = ceil_pads if ceil_mode else reg_pads - return pool(self, pads).sum(axis) / pool(self.ones_like(), pads).sum(axis) - if not ceil_mode: return pool(self, reg_pads).mean(axis) - return pool(self, ceil_pads).sum(axis) / pool(self.pad(reg_pads).ones_like(), tuple(cp-rp for cp,rp in zip(ceil_pads, reg_pads))).sum(axis) - - def max_pool2d(self, kernel_size:tuple[int, ...]=(2,2), stride=None, dilation=1, padding:int|tuple[int, ...]=0, - ceil_mode=False, return_indices=False) -> Tensor | tuple[Tensor, Tensor]: - """ - Applies max pooling over a tensor. - - This function supports three different types of `padding` - - 1. `int` (single value): - Applies the same padding value uniformly to all spatial dimensions. - - 2. `tuple[int, ...]` (length = number of spatial dimensions): - Specifies a distinct padding value for each spatial dimension in the form `(padding_height, padding_width, ...)`. - - 3. `tuple[int, ...]` (length = 2 * number of spatial dimensions): - Specifies explicit padding for each side of each spatial dimension in the form - `(padding_left, padding_right, padding_top, padding_bottom, ...)`. - - When `ceil_mode` is set to `True`, output shape will be determined using ceil division. - When `return_indices` is set to `True`, the argmax will be returned along with the max values. - - NOTE: unlike PyTorch, this implementation is not limited to only 2d pooling and instead works for any number of dimensions. - - See: https://paperswithcode.com/method/max-pooling - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(25).reshape(1, 1, 5, 5) - print(t.max_pool2d().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.max_pool2d(ceil_mode=True).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.max_pool2d(padding=1).numpy()) - ``` - """ - axis = tuple(range(-len(k_ := make_tuple(kernel_size, 2)), 0)) - pads = self._resolve_pool_pads(padding, len(k_)) - if ceil_mode: pads = self._apply_ceil_mode(pads, k_, stride if stride is not None else k_, dilation) - pooled = self.pad(pads, value=dtypes.min(self.dtype))._pool(k_, stride if stride is not None else k_, dilation) - if not return_indices: return pooled.max(axis) - spatial_sz = math.prod(spatial_shape := self.shape[-len(k_):]) - idx = Tensor.arange(spatial_sz,0,-1, requires_grad=False, device=self.device).reshape(spatial_shape) - m = pooled == pooled.max(axis, keepdim=True) - idx = m * idx.pad(pads, value=dtypes.min(idx.dtype))._pool(k_, stride if stride is not None else k_, dilation) - return pooled.max(axis), spatial_sz - idx.max(axis) - - def max_unpool2d(self, indices:Tensor, kernel_size:tuple[int, ...]=(2,2), stride=None, dilation=1, padding:int|tuple[int, ...]=0, output_size=None): - """ - Performs a partial inverse of `max_pool2d` using the indices from the argmax. - - When `output_size` is provided, the output shape disambiguates to the provided shape. - - NOTE: unlike PyTorch, this implementation is not limited to only 2d pooling and instead works for any number of dimensions. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(1, 17).reshape(1, 1, 4, 4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - output, indices = Tensor.max_pool2d(t, return_indices=True) - print(output.numpy()) - print(indices.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.max_unpool2d(output, indices).numpy()) - ``` - """ - bs,c,*spatial_shape = self.shape - if output_size is None: - k_,d_,s_ = (make_tuple(x, len(spatial_shape)) for x in (kernel_size, dilation, stride if stride is not None else kernel_size)) - p_ = _flat_to_grouped(self._resolve_pool_pads(padding, len(spatial_shape))) - # https://arxiv.org/pdf/1603.07285 inverse of relationship 15 in section 5.1. - output_size = tuple((i-1)*s - (pB+pA) + (d*(k-1)+1) for i,k,d,s,(pA,pB) in zip(spatial_shape,k_,d_,s_,p_)) - else: output_size = output_size[-len(spatial_shape):] - ret = (indices.reshape(bs,c,1,-1)._one_hot_along_dim(prod(output_size), 2) * self.reshape(bs,c,1,-1)).sum(3) - return ret.reshape(bs,c,*output_size) - - def conv2d(self, weight:Tensor, bias:Tensor|None=None, groups=1, stride=1, dilation=1, padding:int|tuple[int, ...]=0, - dtype:DTypeLike|None=None) -> Tensor: - """ - Applies a convolution over a tensor with a given `weight` and optional `bias`. - - This function supports three different types of `padding` - - 1. `int` (single value): - Applies the same padding value uniformly to all spatial dimensions. - - 2. `tuple[int, ...]` (length = number of spatial dimensions): - Specifies a distinct padding value for each spatial dimension in the form `(padding_height, padding_width, ...)`. - - 3. `tuple[int, ...]` (length = 2 * number of spatial dimensions): - Specifies explicit padding for each side of each spatial dimension in the form - `(padding_left, padding_right, padding_top, padding_bottom, ...)`. - - NOTE: unlike PyTorch, this implementation is not limited to only 2d convolutions and instead works for any number of dimensions. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Conv2d.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(9).reshape(1, 1, 3, 3) - w = Tensor.ones(1, 1, 2, 2) - print(t.conv2d(w).numpy()) - ``` - """ - if IMAGE: return self.image_conv2d(weight, bias, groups, stride, dilation, padding, dtype) - (bs,cin_), (cout,cin), HW = self.shape[:2], weight.shape[:2], weight.shape[2:] - padding_ = self._resolve_pool_pads(padding, len(HW)) - assert groups*cin == cin_ and len(self.shape) == len(weight.shape), f"Input Tensor shape {self.shape} does not match the shape of the weights {weight.shape}. ({groups*cin} vs. {cin_})" # noqa: E501 - - # conv2d is a pooling op (with padding) - x = self.pad(padding_)._pool(HW, stride, dilation) # (bs, groups*cin, oy, ox, H, W) - rcout, oyx = cout//groups, x.shape[2:-len(HW)] - if not all(x == 3 for x in HW) or stride != 1 or dilation != 1 or not WINO: - # normal conv - x = x.reshape(bs, groups, cin, 1, *oyx, *HW).expand(bs, groups, cin, rcout, *oyx, *HW).permute(0,1,3,*[4+i for i in range(len(oyx))],2,*[4+len(oyx)+i for i in range(len(HW))]) # noqa: E501 - - # conv! broadcasted to (bs, groups, rcout, *oyx, cin, *HW) - ret = (x * weight.reshape(1, groups, rcout, *[1] * len(oyx), cin, *HW)).sum([-1-i for i in range(1+len(oyx))], keepdim=True, dtype=dtype).reshape(bs, cout, *oyx) # noqa: E501 - return ret if bias is None else ret.add(bias.reshape(1, -1, *[1] * len(HW))) - - HWI, HWO = (6,) * len(HW), (4,) * len(HW) # F(4x4,3x3) winograd tiles - winograd_G = [[1/4, 0, 0], [-1/6, -1/6, -1/6], [-1/6, 1/6, -1/6], [1/24, 1/12, 1/6], [1/24, -1/12, 1/6], [0, 0, 1]] - winograd_Bt = [[4, 0, -5, 0, 1, 0], [0, -4, -4, 1, 1, 0], [0, 4, -4, -1, 1, 0], [0, -2, -1, 2, 1, 0], [0, 2, -1, -2, 1, 0], [0, 4, 0, -5, 0, 1]] - winograd_At = [[1, 1, 1, 1, 1, 0], [0, 1, -1, 2, -2, 0], [0, 1, 1, 4, 4, 0], [0, 1, -1, 8, -8, 1]] # applying At in pre-order doubles compile time - - # TODO: stride == dilation - # use padding to round up to 4x4 output tiles - # (bs, cin_, tyx, HWI) - d = self.pad(sum([[padding_[i*2], padding_[i*2+1] + (-(dim + sum(padding_[i * 2:(i + 1) * 2]) - 2) % 4)] for i, dim in enumerate(self.shape[-len(HW):])], []))._pool(HWI, HWO) # noqa: E501 - # move HW to the front: # (HWI, bs, cin_, tyx) - d = d.permute(*range(len(d.shape)-len(HW),len(d.shape)), *range(len(d.shape)-len(HW))) - tyx = d.shape[-len(HWI):] # dim of tiling - - g = weight.permute(*range(len(weight.shape)-len(HW),len(weight.shape)), *range(len(weight.shape)-len(HW))) # move HW to the front - - # compute 6x6 winograd tiles: GgGt, BtdB - # (HWI, groups * rcout, cin) -> (HWI, bs=1, groups, rcout, cin, tyx=(1,1)) - gfactors = _apply_winograd_matrix(winograd_G, g, len(HW)).reshape(*HWI, 1, groups, rcout, cin, *([1]*len(tyx))) - # (HWI, bs, cin_, tyx) -> (HWI, bs, groups, 1 ,cin, *tyx) - dfactors = _apply_winograd_matrix(winograd_Bt, d, len(HW)).reshape(*HWI, bs, groups, 1, cin, *tyx) - - # matmul; sum across cin: (HWI, bs, groups, rcout, *tyx); then HWI -> HWO: (HWO, bs, groups, rcout, *tyx) - ret = _apply_winograd_matrix(winograd_At, (gfactors * dfactors).sum(axis=-1-len(HW), dtype=dtype), len(HW)) - - # interleave tyx and HWO: (bs, groups, rcout, oy, HO, ox, WO) - ret = ret.permute([*range(len(HW), len(ret.shape)-len(HW)), *[i+o for i in range(len(HW)) for o in [len(ret.shape)-len(HW),0]]]) - # merge groups and rcout, tyx and HWO: (bs, groups, cout, *yx), shrink to final - ret = ret.reshape(bs, cout, *[c * HWO[i] for i, c in enumerate(tyx)]).shrink(tuple((0, s) for s in [bs, cout, *oyx])) - - return (ret if bias is None else ret.add(bias.reshape(1, -1, *[1 for _ in range(len(HW))]))).contiguous().contiguous_backward() - - def conv_transpose2d(self, weight:Tensor, bias:Tensor|None=None, groups=1, stride=1, dilation=1, padding=0, output_padding=0) -> Tensor: - """ - Applies a transposed convolution over a tensor with a given `weight` and optional `bias`. - - This function supports three different types of `padding` - - 1. `int` (single value): - Applies the same padding value uniformly to all spatial dimensions. - - 2. `tuple[int, ...]` (length = number of spatial dimensions): - Specifies a distinct padding value for each spatial dimension in the form `(padding_height, padding_width, ...)`. - - 3. `tuple[int, ...]` (length = 2 * number of spatial dimensions): - Specifies explicit padding for each side of each spatial dimension in the form - `(padding_left, padding_right, padding_top, padding_bottom, ...)`. - - NOTE: unlike PyTorch, this implementation is not limited to only 2d transposed convolutions and instead works for any number of dimensions. - - See: https://pytorch.org/docs/stable/generated/torch.nn.ConvTranspose2d.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(9).reshape(1, 1, 3, 3) - w = Tensor.ones(1, 1, 2, 2) - print(t.conv_transpose2d(w).numpy()) - ``` - """ - x, w = self, weight.unflatten(0, (groups, -1)).transpose(1, 2).flip(*range(3, len(weight.shape)+1)) - HW = weight.shape[2:] - padding = _flat_to_grouped(self._resolve_pool_pads(padding, len(HW))) - stride, dilation, output_padding = [make_tuple(x, len(HW)) for x in (stride, dilation, output_padding)] - if any(s>1 for s in stride): - # handle strides: (k) -> reshape -> (k,1) -> pad -> (k,s) -> reshape -> (k*s) -> shrink (k-(s-1)) - x = x.reshape(None, None, *flatten((k,1) for k in x.shape[2:])) - x = x.pad((None, None, *flatten((None,(0,s-1)) for s in stride))) - x = x.reshape(None, None, *[k*s for k,s in zip(x.shape[2::2], stride)]) - x = x.shrink((None, None, *[(0,k-(s-1)) for k,s in zip(x.shape[2:], stride)])) - padding = flatten((((k-1)*d-pB,(k-1)*d-pA+op) for k,d,(pB,pA),op in reversed(list(zip(HW, dilation, padding, output_padding))))) - return x.conv2d(w.flatten(end_dim=1), groups=groups, bias=bias, dilation=dilation, padding=padding) - - def dot(self, w:Tensor, dtype:DTypeLike|None=None) -> Tensor: - - """ - Performs dot product between two tensors. - If `w` is 1-D, it's a sum product over the last axis of `self` and `w`. - If `w` is N-D with N>=2, it's a sum product over the last axis of `self` and the second-to-last axis of `w`. - - You can pass in the optional `dtype` keyword argument to control the data type of the accumulation. - - ```python exec="true" source="above" session="tensor" result="python" - a = Tensor([1, 2, 3]) - b = Tensor([1, 1, 0]) - print(a.dot(b).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - a = Tensor([[1, 2], [3, 4]]) - b = Tensor([[5, 6], [7, 8]]) - print(a.dot(b).numpy()) - ``` - """ - if IMAGE: return self.image_dot(w, dtype) - x, dx, dw = self, self.ndim, w.ndim - if not (dx > 0 and dw > 0): raise RuntimeError(f"both tensors need to be at least 1D, got {dx}D and {dw}D") - if x.shape[-1] != w.shape[axis_w:=-min(w.ndim,2)]: raise RuntimeError(f"cannot dot {x.shape} and {w.shape}") - x = x.reshape(*x.shape[0:-1], *[1]*min(dx-1, dw-1, 1), x.shape[-1]) - w = w.reshape(*w.shape[0:-2], *[1]*min(dx-1, dw-1, 1), *w.shape[axis_w:]).transpose(-1, axis_w) - return (x*w).sum(-1, dtype=dtype).cast(least_upper_dtype(x.dtype, w.dtype) if dtype is None else dtype) - - def matmul(self, x:Tensor, reverse=False, dtype:DTypeLike|None=None) -> Tensor: - """ - Performs matrix multiplication between two tensors. - - You can pass in the `reverse` keyword argument to control the order of the matrix multiplication. - You can pass in the optional `dtype` keyword argument to control the data type of the accumulation. - - ```python exec="true" source="above" session="tensor" result="python" - a = Tensor([[1, 2], [3, 4]]) - b = Tensor([[5, 6], [7, 8]]) - print(a.matmul(b).numpy()) - ``` - """ - return x.dot(self, dtype=dtype) if reverse else self.dot(x, dtype=dtype) - - def _cumalu(self, axis:int, op:Ops, _include_initial=False) -> Tensor: - assert self.shape[axis] != 0 and op in (Ops.ADD, Ops.MAX, Ops.MUL) - pl_sz = self.shape[axis] - int(not _include_initial) - pooled = self.transpose(axis,-1).pad((pl_sz, -int(_include_initial)), value=identity_element(op, self.dtype))._pool((self.shape[axis],)) - return {Ops.ADD: pooled.sum(-1), Ops.MAX: pooled.max(-1), Ops.MUL: pooled.prod(-1)}[op].transpose(axis, -1) - - def _split_cumalu(self, axis:int, op:Ops) -> Tensor: - axis = self._resolve_dim(axis) - if self.ndim == 0 or 0 in self.shape: return self - # TODO: someday the optimizer will find this on its own - # for now this is a two stage cumsum - SPLIT = 256 - if not isinstance(s:=self.shape[axis], int) or s <= SPLIT*2: return self._cumalu(axis, op) - ret = self.transpose(axis,-1).pad((round_up(s, SPLIT)-s, 0), value=identity_element(op, self.dtype)).unflatten(-1, (-1, SPLIT))._cumalu(-1, op) - base = ret[..., -1]._cumalu(-1, op, _include_initial=True) - base = base.unsqueeze(-1).expand(*base.shape, ret.shape[-1]) - def fix(x: Tensor) -> Tensor: return x.flatten(start_dim=-2)[..., -s:].transpose(axis,-1) - return {Ops.ADD: Tensor.__add__, Ops.MAX: Tensor.maximum, Ops.MUL: Tensor.__mul__}[op](fix(ret), fix(base)) - - def cumsum(self, axis:int=0) -> Tensor: - """ - Computes the cumulative sum of the tensor along the specified `axis`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.ones(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.cumsum(1).numpy()) - ``` - """ - return self._split_cumalu(axis, Ops.ADD) - - def cumprod(self, axis:int) -> Tensor: - """ - Computes the cumulative product of the elements of the tensor along the specified `axis`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(1, 7).reshape(2, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.cumprod(axis=0).numpy()) - ``` - """ - return self._split_cumalu(axis, Ops.MUL) - - def cummax(self, axis:int=0) -> Tensor: - """ - Computes the cumulative max of the tensor along the specified `axis`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([0, 1, -1, 2, -2, 3, -3]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.cummax(0).numpy()) - ``` - """ - return self._split_cumalu(axis, Ops.MAX) - - @staticmethod - def _tri(r:sint, c:sint, diagonal:int=0, **kwargs) -> Tensor: - assert isinstance(r, int) and isinstance(c, int), f"does not support symbolic, getting {r=}, {c=}" - if r == 0 or c == 0 or diagonal >= c: return Tensor.zeros(r,c,**kwargs) - if r+diagonal <= 0: return Tensor.ones(r,c,**kwargs) - s = r+c-1 - # build a (s, s) upper triangle - t = Tensor.ones(s,s,**kwargs).pad((None,(0,s))).flatten().shrink(((0,s*(2*s-1)),)).reshape(s,-1).shrink((None,(0,s))) - return t[:r,-diagonal:c-diagonal] if diagonal <= 0 else t[diagonal:r+diagonal,:c] - - def triu(self, diagonal:int=0) -> Tensor: - """ - Returns the upper triangular part of the tensor, the other elements are set to 0. - - The argument `diagonal` determines which diagonal is on the boundary. `diagonal = 0` means the main diagonal. - Positive `diagonal` means above the main diagonal, and negative `diagonal` means below the main diagonal. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2, 3, 4], [5, 6, 7, 8], [9, 10, 11, 12]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.triu(diagonal=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.triu(diagonal=1).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.triu(diagonal=-1).numpy()) - ``` - """ - return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal, device=self.device, dtype=dtypes.bool).where(self, 0).cast(self.dtype) - - def tril(self, diagonal:int=0) -> Tensor: - """ - Returns the lower triangular part of the tensor, the other elements are set to 0. - - The argument `diagonal` determines which diagonal is on the boundary. `diagonal = 0` means the main diagonal. - Positive `diagonal` means above the main diagonal, and negative `diagonal` means below the main diagonal. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2, 3, 4], [5, 6, 7, 8], [9, 10, 11, 12]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.tril(diagonal=0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.tril(diagonal=1).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.tril(diagonal=-1).numpy()) - ``` - """ - return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal+1, device=self.device, dtype=dtypes.bool).where(0, self).cast(self.dtype) - - def interpolate(self, size:tuple[int, ...], mode:str="linear", align_corners:bool=False) -> Tensor: - """ - Downsamples or Upsamples to the input `size`, accepts 0 to N batch dimensions. - - The interpolation algorithm is selected with `mode` which currently only supports `linear`, `nearest` and `nearest-exact`. - To run `bilinear` or `trilinear`, pass in a 2D or 3D size. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2, 3, 4], [21, 22, 23, 24], [41, 42, 43, 44]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.interpolate(size=(2,3), mode="linear").numpy()) - ``` - """ - assert isinstance(size, (tuple,list)) and all_int(size) and 0 < len(size) <= self.ndim, f"invalid {size=}" - assert mode in ("linear", "nearest", "nearest-exact"), "only supports linear, nearest or nearest-exact interpolate" - assert not (align_corners and mode != "linear"), "align_corners option can only be set with the interpolating mode linear" - x, expand = self, list(self.shape) - for i in range(-1,-len(size)-1,-1): - scale = (self.shape[i] - int(align_corners)) / (size[i] - int(align_corners)) - arr, reshape = Tensor.arange(size[i], dtype=dtypes.float32, device=self.device), [1] * self.ndim - reshape[i] = expand[i] = size[i] - if mode == "linear": - index = (scale*arr if align_corners else (scale*(arr+0.5))-0.5).clip(0, self.shape[i]-1) - low, high, perc = [y.reshape(reshape).expand(expand) for y in (index.floor().int(), index.ceil().int(), index - index.floor())] - x = x.gather(i, low).lerp(x.gather(i, high), perc) - else: - index = (scale*(arr+0.5) if mode=="nearest-exact" else scale*arr).cast(dtypes.int32).reshape(reshape).expand(expand) - x = x.gather(i, index) - return x.cast(self.dtype) - - def _pre_scatter(self, dim:int, index:Tensor, src:Tensor) -> tuple[Tensor, Tensor]: - index, dim = index.to(self.device), self._resolve_dim(dim) - assert index.ndim == self.ndim == src.ndim, f"self.ndim, index.ndim and src.ndim must all equal, {self.ndim=} {index.ndim=} {src.ndim=}" - assert all((d == dim or self_ >= index_) and src_ >= index_ for d,(self_,index_,src_) in enumerate(zip(self.shape, index.shape, src.shape))), \ - f"All dimensions of {index.shape=} should be <= to all dimensions of {src.shape=} and all dimensions except dimension {dim} of {self.shape=}" - if self.dtype != src.dtype: raise RuntimeError(f"expect {self.dtype=} to be equal to {src.dtype=}") - # shrink src to index shape to shrink away the unused values - src = src.shrink(tuple((0,s) for s in index.shape)) - # prepare src and mask for reduce with respect to dim - src = src.unsqueeze(-1).expand(*src.shape, self.shape[dim]).transpose(-1, dim) - mask = index.unsqueeze(-1)._one_hot_along_dim(self.shape[dim]).transpose(-1, dim) - # pad src and mask to self.shape so that reduce can be done with padded values as no-ops - src, mask = (x.pad(tuple((0, self.shape[i] - x.shape[i]) if i != dim else None for i in range(self.ndim)) + (None,)) for x in (src, mask)) - return src, mask - - def scatter(self, dim:int, index:Tensor, src:Tensor|ConstType, reduce:Literal['multiply', 'add']|None=None) -> Tensor: - """ - Scatters `src` values along an axis specified by `dim`. - Apply `add` or `multiply` reduction operation with `reduce`. - - NOTE: To use the `reduce` argument with a Tensor `src`, see `Tensor.scatter_reduce`. - - ```python exec="true" source="above" session="tensor" result="python" - src = Tensor.arange(1, 11).reshape(2, 5) - print(src.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - index = Tensor([[0, 1, 2, 0]]) - print(Tensor.zeros(3, 5, dtype=src.dtype).scatter(0, index, src).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - index = Tensor([[0, 1, 2], [0, 1, 4]]) - print(Tensor.zeros(3, 5, dtype=src.dtype).scatter(1, index, src).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.full((2, 4), 2.0).scatter(1, Tensor([[2], [3]]), 1.23, reduce='multiply').numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.full((2, 4), 2.0).scatter(1, Tensor([[2], [3]]), 1.23, reduce='add').numpy()) - ``` - """ - if reduce not in {None, "add", "multiply"}: raise TypeError(f"{reduce=} must be one of None, 'multiply', or 'add'") - if reduce and isinstance(src, Tensor): raise TypeError("Tensor src is not supported with reduce arg. see scatter_reduce") - if not isinstance(src, Tensor): src = index.full_like(src, device=self.device, dtype=self.dtype) - if reduce == "add": return self.scatter_reduce(dim, index, src, "sum", include_self=True) - if reduce == "multiply": return self.scatter_reduce(dim, index, src, "prod", include_self=True) - src, mask = self._pre_scatter(dim, index, src) - return _masked_setitem(self, src, mask, (-1,)) - - def scatter_reduce(self, dim:int, index:Tensor, src:Tensor, reduce:Literal["sum", "prod", "mean", "amax", "amin"], - include_self:bool=True) -> Tensor: - """ - Scatters `src` values along an axis specified by `dim`. - Apply `"sum"`, `"prod"`, `"mean"`, `"amax"`, or `"amin"` reduction operations with `reduce`. - - Set `include_self=False` to exclude values in the `self` Tensor from the reduction. - - ```python exec="true" source="above" session="tensor" result="python" - src = Tensor.arange(1, 11).cast(dtypes.float).reshape(2, 5) - print(src.numpy()) - index = Tensor([[0, 0, 0, 0, 0], [0, 0, 0, 0, 0]]) - print(index.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(1, 5, dtype=src.dtype).scatter_reduce(0, index, src, reduce='sum').numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(1, 5, dtype=src.dtype).scatter_reduce(0, index, src, reduce='prod').numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor.ones(1, 5, dtype=src.dtype).scatter_reduce(0, index, src, reduce='mean', include_self=False).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([[-10, 20, 0, 5, 10]], dtype=src.dtype).scatter_reduce(0, index, src, reduce='amax').numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([[-10, 20, 0, 5, 10]], dtype=src.dtype).scatter_reduce(0, index, src, reduce='amin').numpy()) - ``` - """ - src, mask = self._pre_scatter(dim, index, src) - def _inv_mask(a:Tensor|ConstType, b:Tensor|ConstType) -> Tensor: return mask.any(-1).logical_not().where(a, b) - if reduce == "sum": return mask.where(src, 0).sum(-1).add(self if include_self else _inv_mask(self, 0)) - if reduce == "prod": return mask.where(src, 1).prod(-1).mul(self if include_self else _inv_mask(self, 1)) - if reduce == "amax": return mask.where(src, m := dtypes.min(src.dtype)).max(-1).maximum(self if include_self else _inv_mask(self, m)) - if reduce == "amin": return mask.where(src, m := dtypes.max(src.dtype)).min(-1).minimum(self if include_self else _inv_mask(self, m)) - if reduce == "mean": - count = mask.where(1, 0).sum(-1).add(1 if include_self else _inv_mask(1, 0)) - return mask.where(src, 0).sum(-1).add(self if include_self else _inv_mask(self, 0)).div(count) - raise RuntimeError(f"{reduce=} must be one of 'sum', 'prod', 'mean', 'amax', 'amin'") - - def sort(self, dim:int=-1, descending:bool=False) -> tuple[Tensor, Tensor]: - """ - Performs a bitonic sort on the tensor along the specified dimension. - - Order of indices for equivalent elements is always preserved. - - See: https://en.wikipedia.org/wiki/Bitonic_sorter - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[0.1, 0.5, 1.2, 3.4, 2.1], [2.2, 1.9, 0.3, 4.5, 0.8]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - sorted_values, indices = t.sort(dim=1, descending=True) - print(sorted_values.numpy()) - print(indices.numpy()) - ``` - """ - x, dim = self, self._resolve_dim(dim) - # pad to power of 2 - orig_len = x.shape[dim] - n_stages = math.ceil(math.log2(orig_len)) - fill_value = dtypes.min(x.dtype) if descending else dtypes.max(x.dtype) - pads = tuple((0, 2**n_stages - orig_len) if i == dim else None for i in range(x.ndim)) - x = x.pad(pads, value=fill_value).unflatten(dim, (2,)*n_stages) - # https://en.wikipedia.org/wiki/Bitonic_sorter#/media/File:BitonicSort1.svg - for stage in range(1, n_stages+1): - if stage != n_stages: - # flip so arrows of green boxes point the same way as blue boxes - crossover_dim = dim + n_stages - stage - 1 - blue_box, green_box = x.split(1, crossover_dim) - flip_dims = tuple(-i for i in range(1, stage+1+(self.ndim-dim))) - x = (blue_box.cat(green_box.flip(flip_dims), dim=crossover_dim)).contiguous() - for substage in range(stage-1, -1, -1): - partner_dim = dim + n_stages - substage - 1 - x_top, x_bottom = x.split(1, partner_dim) - x_larger, x_smaller = x_top.maximum(x_bottom), x_top.minimum(x_bottom) - x = (x_larger.cat(x_smaller, dim=partner_dim) if descending else x_smaller.cat(x_larger, dim=partner_dim)).contiguous() - if stage != n_stages: - # flip wires back to undo the crossover - blue_box, flipped_green_box = x.split(1, crossover_dim) - x = blue_box.cat(flipped_green_box.flip(flip_dims), dim=crossover_dim) - x = x.flatten(dim, dim+n_stages-1).shrink(tuple((0, orig_len) if i == dim else None for i in range(x.ndim))) - # compute indices for sorted values - idx = Tensor.arange(orig_len, requires_grad=False, device=self.device).reshape(tuple(orig_len if i == dim else 1 for i in range(x.ndim))) - idx = idx.expand(x.shape) - def compute_counts(t:Tensor): return ((idx.unsqueeze(dim) <= idx.unsqueeze(dim+1)) & (t.unsqueeze(dim) == t.unsqueeze(dim+1))).sum(dim+1) - count_orig, count_sorted = compute_counts(self), compute_counts(x) - cond = (self.unsqueeze(dim+1) == x.unsqueeze(dim)) & (count_orig.unsqueeze(dim+1) == count_sorted.unsqueeze(dim)) - idx = (cond * idx.unsqueeze(dim+1)).sum(dim) - return x, idx - - def topk(self, k:int, dim:int=-1, largest:bool=True, sorted_:bool=True) -> tuple[Tensor, Tensor]: - """ - Computes the top-k elements of the tensor along the specified `dim`. - - Order of indices for equivalent elements is always preserved. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[0.1, 0.5, 1.2, 3.4, 2.1], [2.2, 1.9, 0.3, 4.5, 0.8]]) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - topk_values, topk_indices = t.topk(2, dim=1) - print(topk_values.numpy()) - print(topk_indices.numpy()) - ``` - """ - if not sorted_: raise NotImplementedError("topk with sorted_=False is not supported") - if k > self.shape[dim:=self._resolve_dim(dim)]: raise ValueError(f"selected index {k=} is out of range") - x, idx = self.sort(dim, descending=largest) - shrink_to_k = tuple((0, k) if i == dim else None for i in range(self.ndim)) - return x.shrink(shrink_to_k), idx.shrink(shrink_to_k) - - # ***** unary ops ***** - - def logical_not(self) -> Tensor: - """ - Computes the logical NOT of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([False, True]).logical_not().numpy()) - ``` - """ - return self.cast(dtypes.bool)._apply_broadcasted_uop(UOp.ne, True) - - def neg(self) -> Tensor: - """ - Negates the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).neg().numpy()) - ``` - """ - return self*-1 if self.dtype != dtypes.bool else self.logical_not() - - def contiguous(self) -> Tensor: - """ - Returns a contiguous tensor. - """ - return self._apply_uop(UOp.contiguous) - - def fuse(self) -> Tensor: - """ - Makes this a single kernel back to Ops.CONTIGUOUS on the inputs. - - Useful for single kernel softmax and flash attention. - Careful, this can break codegen or make kernels really slow. - """ - return self._apply_uop(UOp.fuse) - - def contiguous_backward(self) -> Tensor: - """ - Inserts a contiguous operation in the backward pass. - """ - return self._apply_uop(UOp.contiguous_backward) - - def log(self) -> Tensor: - """ - Computes the natural logarithm element-wise. - - See: https://en.wikipedia.org/wiki/Logarithm - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 4., 8.]).log().numpy()) - ``` - """ - return self.log2()*math.log(2) - - def log2(self) -> Tensor: - """ - Computes the base-2 logarithm element-wise. - - See: https://en.wikipedia.org/wiki/Logarithm - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 4., 8.]).log2().numpy()) - ``` - """ - return self.cast(least_upper_float(self.dtype))._apply_uop(UOp.log2) - - def exp(self) -> Tensor: - """ - Computes the exponential function element-wise. - - See: https://en.wikipedia.org/wiki/Exponential_function - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0., 1., 2., 3.]).exp().numpy()) - ``` - """ - return self.mul(1/math.log(2)).exp2() - - def exp2(self) -> Tensor: - """ - Computes the base-2 exponential function element-wise. - - See: https://en.wikipedia.org/wiki/Exponential_function - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0., 1., 2., 3.]).exp2().numpy()) - ``` - """ - return self.cast(least_upper_float(self.dtype))._apply_uop(UOp.exp2) - - def relu(self) -> Tensor: - """ - Applies the Rectified Linear Unit (ReLU) function element-wise. - - - Described: https://paperswithcode.com/method/relu - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).relu().numpy()) - ``` - """ - # NOTE: if you write this as self.maximum(0) the gradient is wrong, passing through half when self is 0 - return (self>0).where(self, 0) - - def sigmoid(self) -> Tensor: - """ - Applies the Sigmoid function element-wise. - - - Described: https://en.wikipedia.org/wiki/Sigmoid_function - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).sigmoid().numpy()) - ``` - """ - return (1 + (self * (-1/math.log(2))).exp2()).reciprocal() - - def hardsigmoid(self, alpha:float=1/6, beta:float=0.5) -> Tensor: - """ - Applies the Hardsigmoid function element-wise. - NOTE: default `alpha` and `beta` values are taken from torch - - - Described: https://paperswithcode.com/method/hard-sigmoid - - See: https://pytorch.org/docs/stable/generated/torch.nn.functional.hardsigmoid.html - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).hardsigmoid().numpy()) - ``` - """ - return (alpha * self + beta).relu() - (alpha * self + beta - 1).relu() - - def sqrt(self) -> Tensor: - """ - Computes the square root of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 3., 4.]).sqrt().numpy()) - ``` - """ - return self.cast(least_upper_float(self.dtype))._apply_uop(UOp.sqrt) - - def rsqrt(self) -> Tensor: - """ - Computes the reciprocal of the square root of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 3., 4.]).rsqrt().numpy()) - ``` - """ - return self.sqrt().reciprocal() - - def sin(self) -> Tensor: - """ - Computes the sine of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0., math.pi/2, math.pi, 3*math.pi/2, 2*math.pi]).sin().numpy()) - ``` - """ - return self.cast(least_upper_float(self.dtype))._apply_uop(UOp.sin) - - def cos(self) -> Tensor: - """ - Computes the cosine of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0., math.pi/2, math.pi, 3*math.pi/2, 2*math.pi]).cos().numpy()) - ``` - """ - return ((math.pi/2)-self).sin() - - def tan(self) -> Tensor: - """ - Computes the tangent of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0., math.pi/4, math.pi/2, 3*math.pi/4, math.pi]).tan().numpy()) - ``` - """ - return self.sin() / self.cos() - - def asin(self) -> Tensor: - """ - Computes the inverse sine (arcsine) of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-0.9, -0.6, -0.3, 0., 0.3, 0.6, 0.9]).asin().numpy()) - ``` - """ - # https://personal.math.ubc.ca/~cbm/aands/page_81.htm 4.4.46 - coefficients = [-0.0012624911, 0.0066700901, -0.0170881256, 0.0308918810, -0.0501743046, 0.0889789874, -0.2145988016, 1.5707963050] - x = math.pi / 2 - (1.0 - self.abs()).sqrt() * polyN(self.abs(), coefficients) - return self.sign() * x - - def acos(self) -> Tensor: - """ - Computes the inverse cosine (arccosine) of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-0.9, -0.6, -0.3, 0., 0.3, 0.6, 0.9]).acos().numpy()) - ``` - """ - return math.pi / 2 - self.asin() - - def atan(self) -> Tensor: - """ - Computes the inverse tangent (arctan) of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).atan().numpy()) - ``` - """ - return (self / (1 + self * self).sqrt()).asin() - - # ***** math functions ***** - - def trunc(self: Tensor) -> Tensor: - """ - Truncates the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).trunc().numpy()) - ``` - """ - return self.cast(dtypes.int32).cast(self.dtype) - - def ceil(self: Tensor) -> Tensor: - """ - Rounds the tensor element-wise towards positive infinity. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).ceil().numpy()) - ``` - """ - return (self > (b := self.trunc())).where(b+1, b) - - def floor(self: Tensor) -> Tensor: - """ - Rounds the tensor element-wise towards negative infinity. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).floor().numpy()) - ``` - """ - return (self < (b := self.trunc())).where(b-1, b) - - def round(self: Tensor) -> Tensor: - """ - Rounds the tensor element-wise with rounding half to even. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).round().numpy()) - ``` - """ - return ((self > 0) == ((b := self.cast(dtypes.int32) / 2.0).cast(dtypes.int32) == b)).where((self - 0.5).ceil(), (self + 0.5).floor()) - - def isinf(self:Tensor, detect_positive:bool=True, detect_negative:bool=True) -> Tensor: - """ - Checks the tensor element-wise to return True where the element is infinity, otherwise returns False - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, float('inf'), 2, float('-inf'), float('nan')]).isinf().numpy()) - ``` - """ - return (self == float("inf")) * detect_positive + (self == float("-inf")) * detect_negative - - def isnan(self:Tensor) -> Tensor: - """ - Checks the tensor element-wise to return True where the element is NaN, otherwise returns False - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, float('inf'), 2, float('-inf'), float('nan')]).isnan().numpy()) - ``` - """ - return self != self - - def isfinite(self:Tensor) -> Tensor: - """ - Checks the tensor element-wise to return True where the element is finite, otherwise returns False - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, float('inf'), 2, float('-inf'), float('nan')]).isfinite().numpy()) - ``` - """ - return (self.isinf()|self.isnan()).logical_not() - - def lerp(self, end:Tensor, weight:Tensor|float) -> Tensor: - """ - Linearly interpolates between `self` and `end` by `weight`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 3.]).lerp(Tensor([4., 5., 6.]), 0.5).numpy()) - ``` - """ - if self.dtype == dtypes.uint8 and isinstance(weight, Tensor): - w_i = (weight * (1<<(W_PREC:=7)) + 0.5).cast(dtypes.int16) - return (self+(((end - self).cast(dtypes.int8) * w_i + (1<> W_PREC)).cast(dtypes.uint8) - return self + (end - self) * weight - - def square(self) -> Tensor: - """ - Squares the tensor element-wise. - Equivalent to `self*self`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).square().numpy()) - ``` - """ - return self*self - - def clamp(self, min_=None, max_=None) -> Tensor: - """ - Clips (clamps) the values in the tensor between `min_` and `max_` element-wise. - If `min_` is `None`, there is no lower bound. If `max_` is None, there is no upper bound. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).clip(-1, 1).numpy()) - ``` - """ - if min_ is None and max_ is None: raise RuntimeError("at least one of 'min_' or 'max_' must not be None") - ret = self.maximum(min_) if min_ is not None else self - return ret.minimum(max_) if max_ is not None else ret - - def clip(self, min_=None, max_=None) -> Tensor: - """ - Alias for `Tensor.clamp`. - """ - return self.clamp(min_, max_) - - def sign(self) -> Tensor: - """ - Returns the sign of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).sign().numpy()) - ``` - """ - return self.ne(0).where((self<0).where(self.full_like(-1), self.full_like(1)), self.full_like(0)) + self*0 - - def abs(self) -> Tensor: - """ - Computes the absolute value of the tensor element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).abs().numpy()) - ``` - """ - return self * self.sign() - - def reciprocal(self) -> Tensor: - """ - Computes `1/x` element-wise. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1., 2., 3., 4.]).reciprocal().numpy()) - ``` - """ - return self.cast(least_upper_float(self.dtype))._apply_uop(UOp.reciprocal) - - # ***** activation functions ***** - - def elu(self, alpha=1.0) -> Tensor: - """ - Applies the Exponential Linear Unit (ELU) function element-wise. - - - Described: https://paperswithcode.com/method/elu - - Paper: https://arxiv.org/abs/1511.07289v5 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).elu().numpy()) - ``` - """ - return self.relu() - alpha*(1-self.exp()).relu() - - def celu(self, alpha=1.0) -> Tensor: - """ - Applies the Continuously differentiable Exponential Linear Unit (CELU) function element-wise. - - - Described: https://paperswithcode.com/method/celu - - Paper: https://arxiv.org/abs/1704.07483 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).celu().numpy()) - ``` - """ - return self.maximum(0) + (alpha * ((self / alpha).exp() - 1)).minimum(0) - - def selu(self, alpha=1.67326, gamma=1.0507) -> Tensor: - """ - Applies the Scaled Exponential Linear Unit (SELU) function element-wise. - - - Described: https://paperswithcode.com/method/selu - - Paper: https://arxiv.org/abs/1706.02515v5 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).selu().numpy()) - ``` - """ - return gamma * (self >= 0).detach().where(self, alpha * (self.exp() - 1)) - - def swish(self) -> Tensor: - """ - See `.silu()` - - - Paper: https://arxiv.org/abs/1710.05941v1 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).swish().numpy()) - ``` - """ - return self * self.sigmoid() - - def silu(self) -> Tensor: - """ - Applies the Sigmoid Linear Unit (SiLU) function element-wise. - - - Described: https://paperswithcode.com/method/silu - - Paper: https://arxiv.org/abs/1606.08415 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).silu().numpy()) - ``` - """ - return self.swish() # The SiLU function is also known as the swish function. - - def relu6(self) -> Tensor: - """ - Applies the ReLU6 function element-wise. - - - Described: https://paperswithcode.com/method/relu6 - - Paper: https://arxiv.org/abs/1704.04861v1 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-9., -6., -3., 0., 3., 6., 9.]).relu6().numpy()) - ``` - """ - return self.relu() - (self-6).relu() - - def hardswish(self) -> Tensor: - """ - Applies the Hardswish function element-wise. - - - Described: https://paperswithcode.com/method/hard-swish - - Paper: https://arxiv.org/abs/1905.02244v5 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).hardswish().numpy()) - ``` - """ - return self * (self+3).relu6() * (1/6) - - def tanh(self) -> Tensor: - """ - Applies the Hyperbolic Tangent (tanh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Hyperbolic_functions#Tanh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).tanh().numpy()) - ``` - """ - return 2.0 * ((2.0 * self).sigmoid()) - 1.0 - - def sinh(self) -> Tensor: - """ - Applies the Hyperbolic Sine (sinh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Hyperbolic_functions#Sinh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).sinh().numpy()) - ``` - """ - return (self.exp() - self.neg().exp()) / 2 - - def cosh(self) -> Tensor: - """ - Applies the Hyperbolic Cosine (cosh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Hyperbolic_functions#Cosh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).cosh().numpy()) - ``` - """ - return (self.exp() + self.neg().exp()) / 2 - - def atanh(self) -> Tensor: - """ - Applies the Inverse Hyperbolic Tangent (atanh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Inverse_hyperbolic_functions#atanh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-0.9, -0.6, -0.3, 0., 0.3, 0.6, 0.9]).atanh().numpy()) - ``` - """ - return ((1 + self)/(1 - self)).log() / 2 - - def asinh(self) -> Tensor: - """ - Applies the Inverse Hyperbolic Sine (asinh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Inverse_hyperbolic_functions#asinh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).asinh().numpy()) - ``` - """ - return (self + (self.square() + 1).sqrt()).log() - - def acosh(self) -> Tensor: - """ - Applies the Inverse Hyperbolic Cosine (acosh) function element-wise. - - - Described: https://en.wikipedia.org/wiki/Inverse_hyperbolic_functions#acosh - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).acosh().numpy()) - ``` - """ - return (self + (self.square() - 1).sqrt()).log() - - def hardtanh(self, min_val=-1, max_val=1) -> Tensor: - """ - Applies the Hardtanh function element-wise. - - - Described: https://paperswithcode.com/method/hardtanh-activation - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1.5, -1.0, -0.5, 0., 0.5, 1.0, 1.5]).hardtanh().numpy()) - ``` - """ - return self.clip(min_val, max_val) - - def erf(self) -> Tensor: - """ - Applies error function element-wise. - - - Described: https://en.wikipedia.org/wiki/Error_function - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1.5, -1.0, -0.5, 0., 0.5, 1.0, 1.5]).erf().numpy()) - ``` - """ - # https://personal.math.ubc.ca/~cbm/aands/page_299.htm 7.1.26 - t = 1.0 / (1.0 + 0.3275911 * self.abs()) - return self.sign() * (1.0 - t * polyN(t, [1.061405429, -1.453152027, 1.421413741, -0.284496736, 0.254829592]) * (-self.square()).exp()) - - def gelu(self) -> Tensor: - """ - Applies the Gaussian Error Linear Unit (GELU) function element-wise. - - - Described: https://paperswithcode.com/method/gelu - - Paper: https://arxiv.org/abs/1606.08415v5 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).gelu().numpy()) - ``` - """ - return 0.5 * self * (1 + (math.sqrt(2 / math.pi) * (self + 0.044715 * self ** 3)).tanh()) - - def quick_gelu(self) -> Tensor: - """ - Applies the Sigmoid GELU approximation element-wise. - - - Described: https://paperswithcode.com/method/gelu - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).quick_gelu().numpy()) - ``` - """ - return self * (self * 1.702).sigmoid() - - def leaky_relu(self, neg_slope=0.01) -> Tensor: - """ - Applies the Leaky ReLU function element-wise. - - - Described: https://paperswithcode.com/method/leaky-relu - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).leaky_relu().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).leaky_relu(neg_slope=0.42).numpy()) - ``` - """ - return (self<0).where(neg_slope*self, self) - - def mish(self) -> Tensor: - """ - Applies the Mish function element-wise. - - - Described: https://paperswithcode.com/method/mish - - Paper: https://arxiv.org/abs/1908.08681v3 - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).mish().numpy()) - ``` - """ - return self * self.softplus().tanh() - - def softplus(self, beta=1) -> Tensor: - """ - Applies the Softplus function element-wise. - - - Described: https://paperswithcode.com/method/softplus - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).softplus().numpy()) - ``` - """ - return (1/beta) * (1 + (self*beta).exp()).log() - - def softsign(self) -> Tensor: - """ - Applies the Softsign function element-wise. - - - Described: https://paperswithcode.com/method/softsign - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).softsign().numpy()) - ``` - """ - return self / (1 + self.abs()) - - # ***** broadcasted elementwise ops ***** - def _broadcast_to(self, new_shape:tuple[sint, ...]) -> Tensor: - if self.shape == new_shape: return self - if self.ndim > len(new_shape): raise ValueError(f"cannot broadcast tensor to fewer dimensions. shape={self.shape} to {new_shape=}") - # first unsqueeze left with 1s https://data-apis.org/array-api/latest/API_specification/broadcasting.html - shape, _ = _align_left(self.shape, new_shape) - # for each dimension, check either dim is 1, or it does not change - if not all(resolve(s == ns) or resolve(s == 1) for s,ns in zip(shape, new_shape)): - raise ValueError(f"cannot broadcast {self.shape} to {new_shape=}") - return self.reshape(shape)._apply_uop(UOp.expand, arg=new_shape) - - def _broadcasted(self, y:Tensor|ConstType|UOp, reverse:bool=False, match_dtype:bool=True) -> tuple[Tensor, Tensor]: - x: Tensor = self - if not isinstance(y, Tensor): - # make y a Tensor - assert isinstance(y, (*get_args(ConstType), UOp)), f"{type(y)=}, {y=}" - if isinstance(x.dtype, ImageDType) or dtypes.is_float(x.dtype) or (dtypes.is_int(x.dtype) and isinstance(y, int)): y_dtype = x.dtype - elif not isinstance(y, UOp): y_dtype = dtypes.from_py(y) - if isinstance(y, UOp): y = Tensor.from_uop(y, device=x.device) - else: y = Tensor(dtypes.as_const(y, y_dtype), x.device, y_dtype, requires_grad=False) - - if match_dtype and x.dtype != y.dtype: - output_dtype = least_upper_dtype(x.dtype, y.dtype) - x, y = x.cast(output_dtype), y.cast(output_dtype) - - if reverse: x, y = y, x - - # broadcast - return x._broadcast_to(out_shape:=_broadcast_shape(x.shape, y.shape)), y._broadcast_to(out_shape) - - def sub(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Subtracts `x` from `self`. - Equivalent to `self - x`. - Supports broadcasting to a common shape, type promotion, and integer, float, boolean inputs. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.sub(20).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.sub(Tensor([[2.0], [3.5]])).numpy()) - ``` - """ - a, b = self._broadcasted(x, reverse) - return a + (-b) - - def div(self, x:Tensor|ConstType, reverse=False, rounding_mode:Literal["trunc", "floor"]|None=None) -> Tensor: - """ - Divides `self` by `x`. - Equivalent to `self / x`. - Supports broadcasting to a common shape, type promotion, and integer, float, boolean inputs. - `div` performs true division. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.div(3).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, 4, 10]).div(Tensor([2, 3, 4])).numpy()) - ``` - """ - numerator, denominator = self._broadcasted(x, reverse) - d = numerator.cast(least_upper_float(numerator.dtype)) * denominator.cast(least_upper_float(denominator.dtype)).reciprocal() - output_dtype = numerator.dtype if dtypes.is_int(numerator.dtype) else d.dtype - if dtypes.is_int(dt:=least_upper_dtype(numerator.dtype, denominator.dtype)) and rounding_mode is not None: - numerator, denominator = numerator.cast(dt), denominator.cast(dt) - if rounding_mode == "trunc": return numerator.idiv(denominator) - if rounding_mode == "floor": - truncate_div, truncate_mod = numerator.idiv(denominator), numerator._apply_broadcasted_uop(UOp.mod, denominator) - opposite_sign = ((numerator>0)&(denominator<0)) | ((numerator<0)&(denominator>0)) - return (opposite_sign&(truncate_mod!=0)).where(truncate_div-1, truncate_div) - if rounding_mode == "trunc": return d.trunc().cast(output_dtype) - if rounding_mode == "floor": return d.floor().cast(output_dtype) - if rounding_mode is not None: raise RuntimeError(f"{rounding_mode=} is not supported") - return d - - def mod(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Mod `self` by `x`. - Equivalent to `self % x`. - Supports broadcasting to a common shape, type promotion, and integer inputs. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-4, 7, 5, 4, -7, 8]).mod(Tensor([2, -3, 8, -2, 3, 5])).numpy()) - ``` - """ - a, b = self._broadcasted(x, reverse) - return a - a.div(b, rounding_mode="floor") * b - - def bitwise_xor(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Computes bitwise xor of `self` and `x`. - Equivalent to `self ^ x`. - Supports broadcasting to a common shape, type promotion, and integer, boolean inputs. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, -2, 3]).bitwise_xor(Tensor([1, 0, 3])).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([True, True, False, False]).bitwise_xor(Tensor([True, False, True, False])).numpy()) - ``` - """ - if self.dtype != dtypes.bool and not dtypes.is_int(self.dtype): raise RuntimeError(f"{self.dtype} is not supported") - return self._apply_broadcasted_uop(UOp.bitwise_xor, x, reverse) - - def bitwise_and(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Computes the bitwise AND of `self` and `x`. - Equivalent to `self & x`. - Supports broadcasting to a common shape, type promotion, and integer, boolean inputs. - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([2, 5, 255]).bitwise_and(Tensor([3, 14, 16])).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([True, True, False, False]).bitwise_and(Tensor([True, False, True, False])).numpy()) - ``` - """ - if self.dtype != dtypes.bool and not dtypes.is_int(self.dtype): raise RuntimeError(f"{self.dtype} is not supported") - return self._apply_broadcasted_uop(UOp.bitwise_and, x, reverse) - - def bitwise_or(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Computes the bitwise OR of `self` and `x`. - Equivalent to `self | x`. - Supports broadcasting to a common shape, type promotion, and integer, boolean inputs. - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([2, 5, 255]).bitwise_or(Tensor([4, 4, 4])).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([True, True, False, False]).bitwise_or(Tensor([True, False, True, False])).numpy()) - ``` - """ - if self.dtype != dtypes.bool and not dtypes.is_int(self.dtype): raise RuntimeError(f"{self.dtype} is not supported") - return self._apply_broadcasted_uop(UOp.bitwise_or, x, reverse) - - def bitwise_not(self) -> Tensor: - """ - Computes the bitwise NOT of `self`. - Equivalent to `~self`. - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([0, 2, 5, 255], dtype="int8").bitwise_not().numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([True, False]).bitwise_not().numpy()) - ``` - """ - if self.dtype != dtypes.bool and not dtypes.is_int(self.dtype): raise RuntimeError(f"{self.dtype} is not supported") - return self.logical_not() if self.dtype == dtypes.bool else self ^ -1 - - def lshift(self, x:int, reverse=False) -> Tensor: - """ - Computes left arithmetic shift of `self` by `x` bits. `self` must have unsigned dtype. - Equivalent to `self << x`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, 3, 31], dtype=dtypes.uint8).lshift(2).numpy()) - ``` - """ - assert dtypes.is_unsigned(self.dtype) and isinstance(x, int) and x >= 0 and not reverse, f"not supported {self.dtype=} {x=}" - return self.mul(2 ** x, reverse) - - def rshift(self, x:int, reverse=False) -> Tensor: - """ - Computes right arithmetic shift of `self` by `x` bits. `self` must have unsigned dtype. - Equivalent to `self >> x`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([4, 13, 125], dtype=dtypes.uint8).rshift(2).numpy()) - ``` - """ - assert dtypes.is_unsigned(self.dtype) and isinstance(x, int) and x >= 0 and not reverse, f"not supported {self.dtype=} {x=}" - return self.idiv(2 ** x, reverse) - - def pow(self, x:Tensor|ConstType, reverse=False) -> Tensor: - """ - Computes power of `self` with `x`. - Equivalent to `self ** x`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).pow(2.0).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).pow(Tensor([-1.5, 0.5, 1.5])).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print((2.0 ** Tensor([-1, 2, 3])).numpy()) - ``` - """ - base, exponent = self._broadcasted(x, reverse=reverse) - # TODO: int pow - if not base.is_floating_point(): raise RuntimeError("base needs to be float") - - ret = base._apply_uop(UOp.pow, exponent) - # NOTE: pow(int, float) -> int - return ret.round().cast(self.dtype) if not reverse and not dtypes.is_float(self.dtype) else ret - - def maximum(self, x:Tensor|ConstType) -> Tensor: - """ - Computes element-wise maximum of `self` and `x`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).maximum(1).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).maximum(Tensor([-4, -2, 9])).numpy()) - ``` - """ - return self._apply_broadcasted_uop(UOp.maximum, x) - - def minimum(self, x:Tensor|ConstType) -> Tensor: - """ - Computes element-wise minimum of `self` and `x`. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).minimum(1).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-1, 2, 3]).minimum(Tensor([-4, -2, 9])).numpy()) - ``` - """ - t, x = self._broadcasted(x) - return t._inverse().maximum(x._inverse())._inverse() - - def where(self:Tensor, x:Tensor|ConstType|sint, y:Tensor|ConstType|sint) -> Tensor: - """ - Returns a tensor of elements selected from either `x` or `y`, depending on `self`. - `output_i = x_i if self_i else y_i`. - - ```python exec="true" source="above" session="tensor" result="python" - cond = Tensor([[True, True, False], [True, False, False]]) - print(cond.where(1, 3).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - cond = Tensor.randn(2, 3) - print(cond.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print((cond > 0).where(cond, -float("inf")).numpy()) - ``` - """ - if isinstance(x, Tensor): x, y = x._broadcasted(y) - elif isinstance(y, Tensor): y, x = y._broadcasted(x) - cond, x = self._broadcasted(x, match_dtype=False) - cond, y = cond._broadcasted(y, match_dtype=False) - return cond.cast(dtypes.bool)._apply_uop(UOp.where, *x._broadcasted(y)) - - def copysign(self, other) -> Tensor: - """ - Returns a tensor of with the magnitude of `self` and the sign of `other`, elementwise. - """ - # NOTE: torch always return in float, we return based on the broadcasting rule. - other = self._broadcasted(other)[1] - # TODO: remove other*0? - return (other < 0).where(-self.abs(), self.abs()) + other*0 - - # ***** op wrappers ***** - - def __invert__(self) -> Tensor: return self.bitwise_not() - - # TODO: combine with UOps __floordiv__ - def __floordiv__(self, x): return self.div(x, rounding_mode="floor") - def __rfloordiv__(self, x): return self.div(x, rounding_mode="floor", reverse=True) - - def __pow__(self, x) -> Tensor: return self.pow(x) - def __matmul__(self, x) -> Tensor: return self.matmul(x) - - def __rpow__(self, x) -> Tensor: return self.pow(x, True) - def __rmatmul__(self, x) -> Tensor: return self.matmul(x, True) - - def __iadd__(self, x) -> Tensor: return self.assign(self.add(x)) - def __isub__(self, x) -> Tensor: return self.assign(self.sub(x)) - def __imul__(self, x) -> Tensor: return self.assign(self.mul(x)) - def __ipow__(self, x) -> Tensor: return self.assign(self.pow(x)) - def __itruediv__(self, x) -> Tensor: return self.assign(self.div(x)) - def __ifloordiv__(self, x) -> Tensor: return self.assign(self.__floordiv__(x)) - def __imatmul__(self, x) -> Tensor: return self.assign(self.matmul(x)) - def __iand__(self, x) -> Tensor: return self.assign(self.bitwise_and(x)) - def __ior__(self, x) -> Tensor: return self.assign(self.bitwise_or(x)) - def __ixor__(self, x) -> Tensor: return self.assign(self.bitwise_xor(x)) - def __ilshift__(self, x) -> Tensor: return self.assign(self.lshift(x)) - def __irshift__(self, x) -> Tensor: return self.assign(self.rshift(x)) - - def __lt__(self, x) -> Tensor: return self._apply_broadcasted_uop(UOp.__lt__, x, False) - def __gt__(self, x) -> Tensor: return self._apply_broadcasted_uop(UOp.__lt__, x, True) - def ne(self, x) -> Tensor: return self._apply_broadcasted_uop(UOp.ne, x, False) - - def __eq__(self, x) -> Tensor: return self.eq(x) # type: ignore[override] - - # ***** functional nn ops ***** - - def linear(self, weight:Tensor, bias:Tensor|None=None, dtype:DTypeLike|None=None) -> Tensor: - """ - Applies a linear transformation to `self` using `weight` and `bias`. - - See: https://pytorch.org/docs/stable/generated/torch.nn.Linear.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2], [3, 4]]) - weight = Tensor([[1, 2], [3, 4]]) - bias = Tensor([1, 2]) - print(t.linear(weight, bias).numpy()) - ``` - """ - if dtype is not None: return self.cast(dtype).linear(weight.cast(dtype), bias.cast(dtype) if bias is not None else bias) - x = self.mul(weight) if len(weight.shape) == 1 else self.dot(weight) - return x.add(bias) if bias is not None else x - - def sequential(self, ll:list[Callable[[Tensor], Tensor]]) -> Tensor: - """ - Applies a sequence of functions to `self` chaining the output of each function to the input of the next. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([1, 2, 3]) - print(t.sequential([lambda x: x * 2, lambda x: x + 1]).numpy()) - ``` - """ - return functools.reduce(lambda x,f: f(x), ll, self) - - def layernorm(self, axis:int|tuple[int,...]=-1, eps:float=1e-5) -> Tensor: - """ - Applies Layer Normalization over a mini-batch of inputs. - - - Described: https://paperswithcode.com/method/layer-normalization - - Paper: https://arxiv.org/abs/1607.06450v1 - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.randn(8, 10, 16) * 2 + 8 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.layernorm() - print(t.mean().item(), t.std().item()) - ``` - """ - y = (self - self.mean(axis, keepdim=True)) - return y.mul((y*y).mean(axis, keepdim=True).add(eps).rsqrt()) - - def batchnorm(self, weight:Tensor|None, bias:Tensor|None, mean:Tensor, invstd:Tensor, axis:int|tuple[int, ...]=1) -> Tensor: - """ - Applies Batch Normalization over a mini-batch of inputs. - - - Described: https://paperswithcode.com/method/batch-normalization - - Paper: https://arxiv.org/abs/1502.03167 - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.randn(8, 4, 16, 16) * 2 + 8 - print(t.mean().item(), t.std().item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.batchnorm(None, None, t.mean(axis=(0,2,3)), t.var(axis=(0,2,3)).add(1e-5).rsqrt()) - print(t.mean().item(), t.std().item()) - ``` - """ - axis_ = argfix(axis) - shape = tuple(s if ax in axis_ else 1 for ax, s in enumerate(self.shape)) - x = self - mean.reshape(shape) - if weight is not None: x = x * weight.reshape(shape) - ret = x.mul(invstd.reshape(shape) if len(invstd.shape) == len(axis_) else invstd) - return (ret + bias.reshape(shape)) if bias is not None else ret - - def dropout(self, p=0.5) -> Tensor: - """ - Applies dropout to `self`. - - NOTE: dropout is only applied when `Tensor.training` is `True`. - - - Described: https://paperswithcode.com/method/dropout - - Paper: https://jmlr.org/papers/v15/srivastava14a.html - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(2, 2) - with Tensor.train(): - print(t.dropout().numpy()) - ``` - """ - if not Tensor.training or p == 0: return self - return (Tensor.rand_like(self, requires_grad=False, dtype=dtypes.default_float, contiguous=False) >= p).contiguous().where(self, 0) / (1.0 - p) - - # helper function commonly used for indexing - def _one_hot_along_dim(self:Tensor, num_classes:sint, dim:int=-1) -> Tensor: - if not dtypes.is_int(self.dtype): raise RuntimeError(f"_one_hot_along_dim expects int index tensor, getting {self.dtype}") - offset = self.ndim - self._resolve_dim(dim) - 1 - return self == Tensor.arange(num_classes, device=self.device, requires_grad=False).reshape((num_classes,) + (1,) * offset) - - def one_hot(self, num_classes:int=-1) -> Tensor: - """ - Converts `self` to a one-hot tensor. - - `num_classes` defaults to -1, which means num_classes will be inferred as max(self) + 1. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([0, 1, 3, 3, 4]) - print(t.one_hot(5).numpy()) - ``` - """ - if not dtypes.is_int(self.dtype): raise RuntimeError(f"expect integer dtype, getting {self.dtype=}") - if num_classes == -1: num_classes = (self.max()+1).item() - return self[..., None]._one_hot_along_dim(num_classes).where(1, 0) - - def scaled_dot_product_attention(self, key:Tensor, value:Tensor, attn_mask:Tensor|None=None, dropout_p:float=0.0, is_causal:bool=False) -> Tensor: - """ - Computes scaled dot-product attention. - `self` is the query tensor, `key` is the key tensor, and `value` is the value tensor. - - - Described: https://paperswithcode.com/method/scaled - - Paper: https://arxiv.org/abs/1706.03762v7 - - ```python exec="true" source="above" session="tensor" result="python" - q = Tensor.randn(2, 4, 8) - k = Tensor.randn(2, 4, 8) - v = Tensor.randn(2, 4, 8) - print(q.scaled_dot_product_attention(k, v).numpy()) - ``` - """ - # NOTE: it also works when `key` and `value` have symbolic shape. - assert all_int(self.shape), f"does not support symbolic shape {self.shape}" - qk = self.matmul(key.transpose(-2,-1), dtype=least_upper_dtype(self.dtype, key.dtype, dtypes.float32)) / math.sqrt(self.shape[-1]) - # handle attention mask - if is_causal: - if attn_mask is not None: raise RuntimeError("cannot set attn_mask when is_causal=True") - attn_mask = qk.ones_like(requires_grad=False, device=self.device, dtype=dtypes.bool).tril() - if attn_mask is not None: - if attn_mask.dtype == dtypes.bool: attn_mask = attn_mask.where(0, -float("inf")) - qk = qk + attn_mask - return qk.cast(self.dtype).softmax(-1).dropout(dropout_p) @ value - - def _do_reduction(self, reduction:ReductionStr="mean") -> Tensor: - if reduction not in get_args(ReductionStr): raise ValueError(f"{reduction=} must be one of {get_args(ReductionStr)}") - reductions: dict[str, Callable[[Tensor], Tensor]] = {"mean": Tensor.mean, "sum": Tensor.sum, "none": lambda x: x} - return reductions[reduction](self) - - def binary_crossentropy(self, Y:Tensor, reduction:ReductionStr="mean") -> Tensor: - """ - Computes the binary cross-entropy loss between `self` and `Y`. - - See: https://pytorch.org/docs/stable/generated/torch.nn.BCELoss.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([0.1, 0.9, 0.2]) - Y = Tensor([0, 1, 0]) - print(t.binary_crossentropy(Y).item()) - ``` - """ - return (-Y*self.log() - (1-Y)*(1-self).log())._do_reduction(reduction) - - def binary_crossentropy_logits(self, Y:Tensor, reduction:ReductionStr="mean") -> Tensor: - """ - Computes the binary cross-entropy loss between `self` and `Y` where `self` is logits. - - See: https://pytorch.org/docs/stable/generated/torch.nn.BCEWithLogitsLoss.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 2, -3]) - Y = Tensor([0, 1, 0]) - print(t.binary_crossentropy_logits(Y).item()) - ``` - """ - return (self.maximum(0) - Y * self + (1 + self.abs().neg().exp()).log())._do_reduction(reduction) - - def sparse_categorical_crossentropy(self, Y:Tensor, ignore_index:int=-1, label_smoothing=0.0, reduction:ReductionStr="mean") -> Tensor: - """ - Computes the sparse categorical cross-entropy loss between `self` and `Y`. - - NOTE: `self` is logits and `Y` is the target labels. - NOTE: unlike PyTorch, this function expects the class axis to be -1 - - See: https://pytorch.org/docs/stable/generated/torch.nn.CrossEntropyLoss.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[-1, 2, -3], [1, -2, 3]]) - Y = Tensor([1, 2]) - print(t.sparse_categorical_crossentropy(Y).item()) - ``` - """ - assert 0.0 <= label_smoothing <= 1.0, "label_smoothing must be in [0.0, 1.0]" - assert reduction in ("mean", "sum", "none"), "reduction must be one of ['mean', 'sum', 'none']" - log_probs, loss_mask = self.log_softmax(), (Y != ignore_index) if ignore_index != -1 else Y.ones_like(dtype=dtypes.bool) - y_counted = Y.to(self.device).flatten().reshape(-1, 1)._one_hot_along_dim(self.shape[-1]) - y = (y_counted * loss_mask.reshape(-1, 1)).reshape(*Y.shape, self.shape[-1]) - smoothing = label_smoothing * (log_probs.mean(-1) * loss_mask) - unreduced = ((1 - label_smoothing) * (log_probs * y).sum(-1) + smoothing) - # NOTE: because of ignore_index, we can't use Tensor.mean (so can't use `_do_reduction` here) - return -(unreduced.sum() / loss_mask.sum() if reduction == "mean" else (unreduced.sum() if reduction == "sum" else unreduced)) - - def cross_entropy(self, Y:Tensor, reduction:ReductionStr="mean", label_smoothing:float=0.0) -> Tensor: - """ - Computes the cross entropy loss between input logits and target. - - NOTE: `self` are logits and `Y` are the target labels or class probabilities. - - See: https://pytorch.org/docs/stable/generated/torch.nn.functional.cross_entropy.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[-1, 2, -3], [1, -2, 3]]) - Y = Tensor([1, 2]) - print(t.cross_entropy(Y).item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[-1, 2, -3], [1, -2, 3]]) - Y = Tensor([1, 2]) - print(t.cross_entropy(Y, reduction='none').numpy()) - ``` - """ - assert 0.0 <= label_smoothing <= 1.0, "label_smoothing must be in [0.0, 1.0]" - Y = Y.one_hot(num_classes=cast(int, self.shape[1])) if Y.ndim < 2 else Y - Y = (1 - label_smoothing)*Y + label_smoothing / cast(int, Y.shape[1]) - ret = -self.log_softmax(axis=1).mul(Y).sum(axis=1) - return ret._do_reduction(reduction) - - def nll_loss(self, Y:Tensor, weight:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean") -> Tensor: - """ - Computes the negative log likelihood loss between log-probabilities and target labels. - - NOTE: `self` is log-probabilities and `Y` is the Y labels or class probabilities. - - See: https://pytorch.org/docs/stable/generated/torch.nn.functional.nll_loss.html - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[-1, 2, -3], [1, -2, 3]]) - Y = Tensor([1, 2]) - print(t.log_softmax().nll_loss(Y).item()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[-1, 2, -3], [1, -2, 3]]) - Y = Tensor([1, 2]) - print(t.log_softmax().nll_loss(Y, reduction='none').numpy()) - ``` - """ - weight = Tensor.ones_like(Y, requires_grad=False) if weight is None else weight[Y] - masked_weight = weight if ignore_index is None else weight * (Y != ignore_index) - nll = -self.gather(1, Y.unsqueeze(1)).squeeze(1) * masked_weight - return nll.sum() / masked_weight.sum() if reduction == "mean" else nll._do_reduction(reduction) - - # ***** Tensor Properties ***** - - @property - def ndim(self) -> int: - """ - Returns the number of dimensions in the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[1, 2], [3, 4]]) - print(t.ndim) - ``` - """ - return len(self.shape) - - def numel(self) -> sint: - """ - Returns the total number of elements in the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[[1, 2], [3, 4]], [[5, 6], [7, 8]]]) - print(t.numel()) - ``` - """ - return prod(self.shape) - - def element_size(self) -> int: - """ - Returns the size in bytes of an individual element in the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([5], dtype=dtypes.int16) - print(t.element_size()) - ``` - """ - return self.dtype.itemsize - - def nbytes(self) -> int: - """ - Returns the total number of bytes of all elements in the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([8, 9], dtype=dtypes.float) - print(t.nbytes()) - ``` - """ - return self.numel() * self.element_size() - - def is_floating_point(self) -> bool: - """ - Returns `True` if the tensor contains floating point types, i.e. is one of `dtypes.float64`, `dtypes.float32`, - `dtypes.float16`, `dtypes.bfloat16`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([8, 9], dtype=dtypes.float32) - print(t.is_floating_point()) - ``` - """ - return dtypes.is_float(self.dtype) - - def size(self, dim:int|None=None) -> sint|tuple[sint, ...]: - """ - Returns the size of the tensor. If `dim` is specified, return the length along dimension `dim`. Otherwise return the shape of the tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[4, 5, 6], [7, 8, 9]]) - print(t.size()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.size(dim=1)) - ``` - """ - return self.shape if dim is None else self.shape[dim] - - # ***** cast ops ***** - - def llvm_bf16_cast(self, dtype:DTypeLike) -> Tensor: - # hack for devices that don't support bfloat16 - assert self.dtype == dtypes.bfloat16 - return self.to("LLVM").cast(dtype) - - def cast(self, dtype:DTypeLike) -> Tensor: - """ - Casts `self` to the given `dtype`. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 2.5, 3], dtype=dtypes.float) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.cast(dtypes.int32) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.cast(dtypes.uint8) - print(t.dtype, t.numpy()) - ``` - """ - if (dt:=to_dtype(dtype)) in {dtypes.uint8, dtypes.uint16} and dtypes.is_float(self.dtype): - # NOTE: values within the int32 range and outside the unsigned dtype range will cause values to wrap around - return self._apply_uop(UOp.cast, dtype=dtypes.int32)._apply_uop(UOp.cast, dtype=dt) - return self if self.dtype == dt else self._apply_uop(UOp.cast, dtype=dt) - - def bitcast(self, dtype:DTypeLike) -> Tensor: - """ - Bitcasts `self` to the given `dtype` of the same itemsize. - - `self` must not require a gradient. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 2, 3], dtype=dtypes.int32) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.bitcast(dtypes.uint32) - print(t.dtype, t.numpy()) - ``` - """ - if self.requires_grad: raise RuntimeError("can't backprop through bitcast") - dt = to_dtype(dtype) - if (ns:=dt.itemsize) != (os:=self.dtype.itemsize) and (self.shape[-1]*os) % ns != 0: raise RuntimeError("unsupported size in bitcast") - if (not isinstance(self.device, str) or not self.device.startswith("DISK")) and ns != os: - new_uint, old_uint = to_dtype(f"uint{8*ns}"), to_dtype(f"uint{8*os}") - tmp = self.bitcast(old_uint) - if ns > os: - tmp = tmp.reshape(self.shape[:-1] + (self.shape[-1]//(rate := ns//os), rate)) - nones = (None,) * (tmp.ndim - 1) - return functools.reduce(Tensor.add, (tmp.shrink(nones + ((i, i+1),)).cast(new_uint)<<8*i*os for i in range(rate))).squeeze(-1).bitcast(dtype) - return Tensor.stack(*(tmp>>8*i*ns for i in range(os//ns)), dim=-1).flatten(-2).cast(new_uint).bitcast(dtype) - return self._apply_uop(UOp.bitcast, dtype=dt) if self.dtype != dt else self - - def float(self) -> Tensor: - """ - Convenience method to cast `self` to a `float32` Tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 2, 3], dtype=dtypes.int32) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.float() - print(t.dtype, t.numpy()) - ``` - """ - return self.cast(dtypes.float32) - - def half(self) -> Tensor: - """ - Convenience method to cast `self` to a `float16` Tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 2, 3], dtype=dtypes.int32) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.half() - print(t.dtype, t.numpy()) - ``` - """ - return self.cast(dtypes.float16) - - def int(self) -> Tensor: - """ - Convenience method to cast `self` to a `int32` Tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1.5, -0.5, 0.0, 0.5, 1.5]) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.int() - print(t.dtype, t.numpy()) - ``` - """ - return self.cast(dtypes.int32) - - def bool(self) -> Tensor: - """ - Convenience method to cast `self` to a `bool` Tensor. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([-1, 0, 1]) - print(t.dtype, t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - t = t.bool() - print(t.dtype, t.numpy()) - ``` - """ - return self.cast(dtypes.bool) - - # *** image Tensor function replacements *** - - def image_dot(self, w:Tensor, dtype:DTypeLike|None=None) -> Tensor: - # NOTE: we use a 1x1 conv2d to do the matmul. mxk @ kxn = (1,k,m,1).conv2d(n,k,1,1) - x, dx, dw = self, self.ndim, w.ndim - if not (dx > 0 and dw > 0): raise RuntimeError(f"both tensors need to be at least 1D, got {dx}D and {dw}D") - if x.shape[-1] != w.shape[-min(w.ndim, 2)]: raise RuntimeError(f"cannot image_dot {x.shape} and {w.shape}") - - bs, groups, cin, cout = prod(self.shape[0:-2]), prod(w.shape[0:-2]), w.shape[-2], w.shape[-1] - out_shape_t = self.shape[0:-2] + (cout,-1) if len(self.shape) > 1 else (cout, ) - - # NOTE: with NHWC we can remove the transposes - # bs x groups*cin x H x W - cx = self.transpose(self.ndim-1, self.ndim-2).reshape((bs//groups, groups*cin, -1, 1)) - # groups*cout x cin x H, W - cw = w.transpose(w.ndim-1, w.ndim-2).reshape((groups*cout, cin, 1, 1)) - return cx.image_conv2d(cw, groups=groups, dtype=dtype).reshape(out_shape_t).transpose(self.ndim-1, self.ndim-2) - - def image_conv2d(self, weight:Tensor, bias:Tensor|None=None, groups=1, stride=1, dilation=1, padding=0, dtype=None) -> Tensor: - base_image_type = dtypes.imageh if getenv("FLOAT16", 0) else dtypes.imagef - - (bs,_,iy,ix), (cout,cin,H,W) = self.shape, weight.shape - x, w = self, weight.reshape(groups, (rcout := cout//groups), cin, H, W) - - # hack for non multiples of 4 on cin - if cin % 4 != 0 and not (cin == 1 and groups%4 == 0): - x = x.reshape(bs, groups, cin, iy, ix) # do this always? - added_input_channels = 4 - (cin % 4) - w = w.pad(tuple((0, added_input_channels) if i == 2 else None for i in range(w.ndim))) - x = x.pad(tuple((0, added_input_channels) if i == 2 else None for i in range(x.ndim))) - cin = cin + added_input_channels - x = x.reshape(bs, groups*cin, iy, ix) - - # hack for non multiples of 4 on rcout - added_output_channels = 0 - if rcout % 4 != 0 and not (rcout == 1 and groups%4 == 0): - added_output_channels = 4 - (rcout % 4) - rcout += added_output_channels - cout = groups * rcout - w = w.pad(tuple((0, added_output_channels) if i == 1 else None for i in range(w.ndim))) - - # packed (note: flipping bs and iy would make the auto-padding work) - x = x.permute(0,2,3,1) - cin_last = iy == 1 and ix == 1 - if cin == 1: w = w.reshape(cout//4,4,H,W).permute(0,2,3,1) - elif cin_last: w = w.reshape(cout//4,4,cin//4,4,H,W).permute(0,4,2,5,1,3) - else: w = w.reshape(cout//4,4,cin//4,4,H,W).permute(0,4,2,5,3,1) - - # contiguous creates the image, and early realize static weights (TODO: test for the static weight) - if IMAGE >= 2: x,w = x.cast(base_image_type((bs*iy, ix*groups*cin//4, 4))), w.cast(base_image_type((cout//4, H*W*cin, 4))) - x, w = x.contiguous(), w.contiguous() - - # expand out - rcin_hi, rcin_lo = cin//4 if cin >= 4 else 1, 4 if cin >= 4 else 1 - cout_expand = [groups//4 if cin == 1 else groups, 4 if cin == 1 else 1, rcout//4 if rcout >= 4 else 1, 4 if rcout >= 4 else 1] - x = x.reshape(bs, iy, ix, groups, rcin_hi, rcin_lo) - if cin_last: w = w.reshape(cout//4, H, rcin_hi, W, 4, rcin_lo) - else: w = w.reshape(cout//4, H, rcin_hi, W, rcin_lo, 4).permute(0,1,2,3,5,4) - - # prepare input - x = x.permute(0,3,4,5,1,2).pad(self._resolve_pool_pads(padding,2))._pool((H,W), stride, dilation)# -> (bs, groups, rcin_hi, rcin_lo, oy, ox, H, W) - x = x.permute(0,4,5,1,2,3,6,7).reshape(bs, (oy := x.shape[4]), (ox := x.shape[5]), *cout_expand[0:2], 1, 1, rcin_hi, rcin_lo, H, W) - - # prepare weights - w = w.permute(0,4,2,5,1,3).reshape((1, 1, 1, *cout_expand, rcin_hi, rcin_lo, H, W)) - - # the conv! - ret = (x*w).cast(base_image_type((bs*oy, ox*cout//4, 4)) if IMAGE >= 2 else dtypes.float32).sum((-4, -3, -2, -1), dtype=dtype) - - # undo hack for non multiples of 4 on C.rcout - if added_output_channels != 0: - ret = ret.reshape(bs, oy, ox, groups, rcout)[:, :, :, :, :-added_output_channels] - cout = groups * (rcout - added_output_channels) - - # NCHW output - ret = ret.reshape(bs, oy, ox, cout).permute(0,3,1,2) - return ret if bias is None else ret.add(bias.reshape(1, -1, 1, 1)) - -P = ParamSpec("P") -T = TypeVar("T") -def _metadata_wrapper(fn: Callable[P, T]) -> Callable[P, T]: - def _wrapper(*args: P.args, **kwargs: P.kwargs) -> T: - if _METADATA.get() is not None: return fn(*args, **kwargs) - - if TRACEMETA >= 2: - caller_frame = sys._getframe(frame := 1) - caller_module = caller_frame.f_globals.get("__name__", None) - caller_func = caller_frame.f_code.co_name - if caller_module is None: return fn(*args, **kwargs) - - # if its called from nn we want to step up frames until we are out of nn - while caller_module.startswith("tinygrad.nn") and "optim" not in caller_module: - caller_frame = sys._getframe(frame := frame + 1) - caller_module = caller_frame.f_globals.get("__name__", None) - if caller_module is None: return fn(*args, **kwargs) - - # if its called from a lambda in tinygrad we want to look two more frames up - if caller_module.startswith("tinygrad") and caller_func == "": caller_frame = sys._getframe(frame := frame + 2) - caller_module = caller_frame.f_globals.get("__name__", None) - if caller_module is None: return fn(*args, **kwargs) - caller_func = caller_frame.f_code.co_name - caller_lineno = caller_frame.f_lineno - - caller = f"{caller_module}:{caller_lineno}::{caller_func}" - else: caller = "" - - token = _METADATA.set(Metadata(name=fn.__name__, caller=caller)) - ret = fn(*args, **kwargs) - _METADATA.reset(token) - return ret - return _wrapper - -if TRACEMETA >= 1: - for name, fn in inspect.getmembers(Tensor, inspect.isfunction): - if name in ["__class__", "__init__", "__new__", "__repr__", "backward", "sequential", "gradient"]: continue - setattr(Tensor, name, functools.wraps(fn)(_metadata_wrapper(fn))) diff --git a/tinygrad/tinygrad/uop/__init__.py b/tinygrad/tinygrad/uop/__init__.py deleted file mode 100644 index 225d0c01..00000000 --- a/tinygrad/tinygrad/uop/__init__.py +++ /dev/null @@ -1,99 +0,0 @@ -from enum import auto, IntEnum, Enum - -# wrapper around IntEnum that preserves Enum.__str__ and makes auto() unique across all FastEnum subclasses -class FastEnum(IntEnum): - def __str__(self): return Enum.__str__(self) - @staticmethod - def _generate_next_value_(_, __, ___, last_values): return 1 + max([0, *last_values, *[max(c) for c in FastEnum.__subclasses__()]]) - -# the order of these Ops controls the order of the toposort -class Ops(FastEnum): - # uops that aren't rendered - SINK = auto(); CONTIGUOUS = auto(); CONTIGUOUS_BACKWARD = auto(); DETACH = auto(); KERNEL = auto(); UNIQUE = auto() # noqa: E702 - - # MetaOps - COPY = auto(); BUFFER_VIEW = auto(); MSELECT = auto(); MSTACK = auto() # noqa: E702 - - # blocks in linearizer - BLOCK = auto(); BLOCKSTART = auto(); BLOCKEND = auto(); BLOCKFINAL = auto() # noqa: E702 - - # movement ops! - RESHAPE = auto(); PERMUTE = auto(); EXPAND = auto(); PAD = auto(); SHRINK = auto(); FLIP = auto() # noqa: E702 - - # misc ops - UNROLL = auto(); CONTRACT = auto() # noqa: E702 - VIEW = auto(); DEFINE_GLOBAL = auto(); BUFFER = auto() # noqa: E702 - DEFINE_VAR = auto(); DEFINE_LOCAL = auto(); DEFINE_ACC = auto() # noqa: E702 - VALID = auto(); SPECIAL = auto(); NOOP = auto() # noqa: E702 - - # reduce - REDUCE_AXIS = auto(); REDUCE = auto(); ALLREDUCE = auto() # noqa: E702 - - # helper ops - GEP = auto(); VECTORIZE = auto(); CAT = auto(); PTRCAT = auto() # noqa: E702 - - # UnaryOps - CAST = auto(); BITCAST = auto(); EXP2 = auto(); LOG2 = auto(); SIN = auto(); SQRT = auto(); RECIP = auto(); NEG = auto() # noqa: E702 - - # load/store before math - LOAD = auto(); STORE = auto() # noqa: E702 - - # early INDEX - INDEX = auto() - - # math ops - WMMA = auto() - - # BinaryOps - ADD = auto(); MUL = auto(); SHL = auto(); SHR = auto(); IDIV = auto(); MAX = auto(); MOD = auto(); CMPLT = auto(); CMPNE = auto() # noqa: E702 - XOR = auto(); OR = auto(); AND = auto(); THREEFRY = auto(); SUB = auto(); FDIV = auto(); POW = auto() # noqa: E702 - - # TernaryOps - WHERE = auto(); MULACC = auto() # noqa: E702 - - # assignment ops - ASSIGN = auto() - BIND = auto() - - # control flow ops - BARRIER = auto(); RANGE = auto(); IF = auto(); ENDRANGE = auto(); ENDIF = auto(); GBARRIER = auto() # noqa: E702 - - # consts last! - VCONST = auto(); CONST = auto() # noqa: E702 - - # device - DEVICE = auto() - MULTI = auto() - - # CUSTOMI is inline - CUSTOM = auto(); CUSTOMI = auto() # noqa: E702 - IGNORE = auto(); FUSE = auto() # noqa: E702 - -class GroupOp: - Unary = {Ops.EXP2, Ops.LOG2, Ops.SIN, Ops.SQRT, Ops.RECIP, Ops.NEG} - Binary = {Ops.ADD, Ops.MUL, Ops.IDIV, Ops.MAX, Ops.MOD, Ops.CMPLT, Ops.CMPNE, Ops.XOR, Ops.SHL, Ops.SHR, Ops.OR, Ops.AND, Ops.THREEFRY, - Ops.SUB, Ops.FDIV, Ops.POW} - Ternary = {Ops.WHERE, Ops.MULACC} - ALU = set.union(Unary, Binary, Ternary) - - Irreducible = {Ops.CONST, Ops.DEFINE_VAR, Ops.SPECIAL, Ops.RANGE} - Movement = {Ops.RESHAPE, Ops.EXPAND, Ops.PERMUTE, Ops.PAD, Ops.SHRINK, Ops.FLIP} - - Buffer = {Ops.LOAD, Ops.STORE, Ops.VALID, Ops.CONST, Ops.DEFINE_VAR} - Block = {Ops.BLOCK, Ops.BLOCKEND, Ops.BLOCKSTART} - - # BinaryOps that can be flipped - Commutative = {Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPNE, Ops.XOR, Ops.AND, Ops.OR} - - # BinaryOps where f(f(a,b),c) = f(a,f(b,c)) - Associative = {Ops.ADD, Ops.MUL, Ops.AND, Ops.OR, Ops.MAX} - - # BinaryOps that satisfy f(x,x)=x see https://en.wikipedia.org/wiki/Idempotence - Idempotent = {Ops.OR, Ops.AND, Ops.MAX} - - # do not preserve f(0) = 0 - UnsafePad = {Ops.RECIP, Ops.LOG2, Ops.EXP2, Ops.IDIV, Ops.POW} - - Meta = {Ops.COPY, Ops.BUFFER_VIEW} - - All = set(Ops) diff --git a/tinygrad/tinygrad/uop/mathtraits.py b/tinygrad/tinygrad/uop/mathtraits.py deleted file mode 100644 index 1433dde0..00000000 --- a/tinygrad/tinygrad/uop/mathtraits.py +++ /dev/null @@ -1,124 +0,0 @@ -from tinygrad.uop import Ops -from tinygrad.helpers import T -from tinygrad.dtype import dtypes - -class MathTrait: - # required to implement - def alu(self:T, arg:Ops, *src) -> T: raise NotImplementedError - def const_like(self:T, b) -> T: raise NotImplementedError - - # great functions you get! - def ufix(self, x): return self.const_like(x) if not isinstance(x, MathTrait) else x - def _binop(self, op, x, reverse): return self.ufix(x).alu(op, self) if reverse else self.alu(op, self.ufix(x)) - def logical_not(self): return self.ne(True) - def neg(self): - if (dtype:=getattr(self, 'dtype')) is None: raise TypeError(f"MathTraits __neg__ requires a dtype, {self=}") - return self.logical_not() if dtype.scalar() == dtypes.bool else self*(-1) - def add(self, x, reverse=False): - """ - Adds `self` and `x`. - Equivalent to `self + x`. - Supports broadcasting to a common shape, type promotion, and integer, float, boolean inputs. - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.add(20).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.add(Tensor([[2.0], [3.5]])).numpy()) - ``` - """ - return self._binop(Ops.ADD, x, reverse) - def mul(self, x, reverse=False): - """ - Multiplies `self` and `x`. - Equivalent to `self * x`. - Supports broadcasting to a common shape, type promotion, and integer, float, boolean inputs. - - ```python exec="true" source="above" session="tensor" result="python" - Tensor.manual_seed(42) - t = Tensor.randn(4) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.mul(3).numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.mul(Tensor([[-1.0], [2.0]])).numpy()) - ``` - """ - return self._binop(Ops.MUL, x, reverse) - def bitwise_and(self, x, reverse=False): return self._binop(Ops.AND, x, reverse) - def bitwise_or(self, x, reverse=False): return self._binop(Ops.OR, x, reverse) - def bitwise_xor(self, x, reverse=False): return self._binop(Ops.XOR, x, reverse) - def idiv(self, x, reverse=False): - """ - Divides `self` by `x`. - Equivalent to `self // x`. - Supports broadcasting to a common shape, type promotion, and integer inputs. - `idiv` performs integer division (truncate towards zero). - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([-4, 7, 5, 4, -7, 8]).idiv(Tensor([2, -3, 8, -2, 3, 5])).numpy()) - ``` - """ - return self._binop(Ops.IDIV, x, reverse) - def mod(self, x, reverse=False): return self._binop(Ops.MOD, x, reverse) - def sub(self, x, reverse=False): return self.ufix(x).alu(Ops.ADD, -self) if reverse else self.alu(Ops.ADD, self.ufix(-x)) - def div(self, x, reverse=False): return (self.ufix(x)*self.alu(Ops.RECIP)) if reverse else (self*self.ufix(x).alu(Ops.RECIP)) - - def __neg__(self): return self.neg() - - def __add__(self, x): return self.add(x) - def __sub__(self, x): return self.sub(x) - def __mul__(self, x): return self.mul(x) - def __truediv__(self, x): return self.div(x) - def __floordiv__(self, x): return self.idiv(x) # TODO: idiv is trunc div, not floordiv - def __mod__(self, x): return self.mod(x) - def __and__(self, x): return self.bitwise_and(x) - def __or__(self, x): return self.bitwise_or(x) - def __xor__(self, x): return self.bitwise_xor(x) - - def __radd__(self, x): return self.add(x, True) - def __rsub__(self, x): return self.sub(x, True) - def __rmul__(self, x): return self.mul(x, True) - def __rtruediv__(self, x): return self.div(x, True) - def __rfloordiv__(self, x): return self.idiv(x, True) - def __rand__(self, x): return self.bitwise_and(x, True) - def __ror__(self, x): return self.bitwise_or(x, True) - def __rxor__(self, x): return self.bitwise_xor(x, True) - def __rmod__(self, x): return self.mod(x, True) - - def __lt__(self, x): return self.alu(Ops.CMPLT, self.ufix(x)) - def __gt__(self, x): return self.ufix(x).alu(Ops.CMPLT, self) - def __ge__(self, x): return (self < x).logical_not() - def __le__(self, x): return (self > x).logical_not() - - def ne(self, x): return self.alu(Ops.CMPNE, self.ufix(x)) - def eq(self, x): return self.ne(x).logical_not() - def __ne__(self, x): return self.ne(x) - # NOTE: __eq__ isn't overridden, and means the same thing as is by default - - def lshift(self, x, reverse=False): return self._binop(Ops.SHL, x, reverse) - def rshift(self, x, reverse=False): return self._binop(Ops.SHR, x, reverse) - def __lshift__(self, x): return self.lshift(x) - def __rshift__(self, x): return self.rshift(x) - def __rlshift__(self, x): return self.lshift(x, True) - def __rrshift__(self, x): return self.rshift(x, True) - - def maximum(self, x): return self.alu(Ops.MAX, self.ufix(x)) - def minimum(self, x): return -(-self).maximum(-x) - def where(self, x, y): - if type(self) is type(x): return self.alu(Ops.WHERE, x, x.ufix(y)) - if type(self) is type(y): return self.alu(Ops.WHERE, y.ufix(x), y) - raise RuntimeError("where needs at least one UOp arg") - def threefry(self, seed): return self.alu(Ops.THREEFRY, seed) - def reciprocal(self): return self.alu(Ops.RECIP) - def sqrt(self): return self.alu(Ops.SQRT) - def sin(self): return self.alu(Ops.SIN) - def log2(self): return self.alu(Ops.LOG2) - def exp2(self): return self.alu(Ops.EXP2) - def pow(self, x): return self.alu(Ops.POW, self.ufix(x)) diff --git a/tinygrad/tinygrad/uop/ops.py b/tinygrad/tinygrad/uop/ops.py deleted file mode 100644 index 40122499..00000000 --- a/tinygrad/tinygrad/uop/ops.py +++ /dev/null @@ -1,905 +0,0 @@ -from __future__ import annotations -from typing import Any, Optional, Union, Callable, cast, TYPE_CHECKING, Type, Sequence -import sys, time, functools, itertools, math, operator, hashlib, os, types, pickle, pathlib, inspect, weakref -from dataclasses import dataclass, field -from tinygrad.uop import Ops, GroupOp -from tinygrad.uop.mathtraits import MathTrait -from tinygrad.dtype import ConstType, ImageDType, dtypes, DType, truncate -from tinygrad.helpers import ContextVar, all_int, prod, getenv, all_same, Context, partition, temp, unwrap, T, argfix, Metadata, flatten -from tinygrad.helpers import PICKLE_BUFFERS, dedup, cdiv, cmod, diskcache_put -if TYPE_CHECKING: - from tinygrad.shape.shapetracker import ShapeTracker - from tinygrad.device import Buffer, MultiBuffer - -# https://en.wikipedia.org/wiki/Identity_element -def identity_element(op:Ops, dt:DType) -> ConstType: return dtypes.as_const({Ops.ADD:0, Ops.MUL:1, Ops.MAX:dtypes.min(dt)}[op], dt) - -def can_pad(root:UOp, edges:dict[UOp, None]) -> bool: - return all(u.op not in GroupOp.UnsafePad for u in root.toposort(gate=lambda x:x not in edges)) - -# With True as the default, this matches the old symbolic behavior -def resolve(x:UOp|bool, default:bool=True): - if isinstance(x, bool): return x - assert x.dtype == dtypes.bool, "UOp in resolve must be bool" - # NOTE: generating the text for the exception is expensive, so we do this - return bool(sx.vmin) if (sx:=x.simplify()).vmin == sx.vmax else default - -# smax/smin are replacements for max/min that preserve symbolic -def _suop(lst, uop_fxn, python_fxn): - uops, nums = partition(lst, lambda x: isinstance(x, UOp)) - return ssimplify(functools.reduce(uop_fxn, uops + ([python_fxn(nums)] if nums else []))) -def smax(*lst): return _suop(argfix(*lst), UOp.maximum, max) -def smin(*lst): return _suop(argfix(*lst), UOp.minimum, min) -def srender(x) -> str: return x.render() if isinstance(x, UOp) else str(x) - -def ssimplify(uop): return uop.ssimplify() if isinstance(uop, UOp) else uop -def sym_infer(uop: Union[UOp, int], var_vals: dict[UOp, int]) -> int: return uop.sym_infer(var_vals) if isinstance(uop, UOp) else uop - -# used for UOp and UPat -def pretty_print(x:Any, rep:Callable, srcfn=lambda x: x.src, cache=None, d=0)->str: - def dfs(x:Any, cache:dict): - for s in srcfn(x) or []: - cache.setdefault(s, [len(cache), 0, False])[1] += 1 - if cache[s][1] == 1: dfs(s, cache) - if cache is None: dfs(x, cache:={}) - if (cx:=cache.setdefault(x, [0,0,False]))[2]: return f"{' '*d} x{cx[0]}" - cx[2], srcs = True, ('None' if srcfn(x) is None else ''.join(f'\n{pretty_print(s, rep, srcfn, cache, d+2)},' for s in srcfn(x))) - return f"{' '*d}{f'x{cx[0]}:=' * (cx[1]>1)}{rep(x)}" % srcs - -class UOpMetaClass(type): - ucache:dict[tuple, weakref.ReferenceType[UOp]] = {} - def __call__(cls, op:Ops, dtype:DType=dtypes.void, src:tuple[UOp,...]=tuple(), arg:Any=None, tag:Any=None, - metadata:tuple[Metadata,...]|None=None, _buffer:Buffer|None=None): - if (wret:=UOpMetaClass.ucache.get(key:=(op, dtype, src, arg, tag), None)) is not None and (ret:=wret()) is not None: return ret - UOpMetaClass.ucache[key] = ref = weakref.ref(created:=super().__call__(*key)) - for s in src: s.children.add(ref) - if metadata is not None: all_metadata[created] = metadata - # NOTE: this value is set by pickle when pickling a realized tensor - if _buffer is not None: - assert op is Ops.BUFFER, f"trying to set Buffer {_buffer} for {op}" - buffers[created] = _buffer - return created - -# some uops map to other stuff -buffers:weakref.WeakKeyDictionary[UOp, Buffer|MultiBuffer] = weakref.WeakKeyDictionary() # this maps BUFFER uops to their device Buffers -all_metadata:weakref.WeakKeyDictionary[UOp, tuple[Metadata, ...]] = weakref.WeakKeyDictionary() # TODO: should this be here? - -# NOTE: this should be frozen, but frozen is slower -@dataclass(eq=False, slots=True) -class UOp(MathTrait, metaclass=UOpMetaClass): - op:Ops - dtype:DType = dtypes.void - src:tuple[UOp, ...] = tuple() - arg:Any = None - tag:Any = None - children:set[weakref.ref[UOp]] = field(default_factory=set) - def __del__(self): - if self.op is Ops.BUFFER and (buffer:=buffers.get(self)) is not None: buffer.ref(-1) - if (ref:=UOpMetaClass.ucache.get(k:=(self.op, self.dtype, self.src, self.arg, self.tag))) is not None: - for s in self.src: s.children.discard(ref) - del UOpMetaClass.ucache[k] - def __reduce__(self): - args = [self.op, self.dtype, self.src, self.arg, self.tag, self.metadata] - if self.op is Ops.BUFFER and self.realized is not None and PICKLE_BUFFERS: args.append(self.realized) - return UOp, tuple(args) - def replace(self, **kwargs) -> UOp: - new_args = (kwargs.pop("op", self.op), kwargs.pop("dtype", self.dtype), kwargs.pop("src", self.src), - kwargs.pop("arg", self.arg), kwargs.pop("tag", self.tag)) - assert len(kwargs) == 0, f"unused kwargs in replace {list(kwargs)}" - if (self.op, self.dtype, self.src, self.arg, self.tag) == new_args: return self - return UOp(*new_args) - @functools.cached_property - def key(self) -> bytes: - return hashlib.sha256(str((self.op, self.dtype, self.arg)).encode() + b"".join([s.key for s in self.src])).digest() - def __repr__(self): return pretty_print(self, lambda x: f"{type(self).__name__}({x.op}, {x.dtype}, arg={x.argstr()}{x.tagstr()}, src=(%s))") - def argstr(self): return f'({", ".join(map(str, self.arg))})' if self.op is Ops.REDUCE_AXIS else repr(self.arg) - def tagstr(self): return f", tag={self.tag}" if self.tag is not None else "" - - @functools.cached_property - def parents(self:UOp) -> dict[UOp, None]: - ret = {s:None for s in self.src} - for s in self.src: ret.update(s.parents) - return ret - @property - def sparents(self:UOp) -> dict[UOp, None]: return {self:None, **self.parents} - - def toposort(self, gate:Callable|None=None) -> dict[UOp, None]: - ret: dict[UOp, None] = {} - stack: list[tuple[UOp, bool]] = [(self, False)] # each stack entry is (node, visited_flag) - while stack: - node, visited = stack.pop() - if node in ret: continue - if not visited: - if gate is None or gate(node): - stack.append((node, True)) # push node back on stack to process after its parents - for parent in reversed(node.src): stack.append((parent, False)) # push parents on the stack - else: ret[node] = None # second time i'm seeing this node, add it to returned toposort - return ret - - # returns map of UOps to their children in the graph rooted by self - def get_children_map(self) -> dict[UOp, dict[UOp, None]]: - ret: dict[UOp, dict[UOp, None]] = {} - for u in self.toposort(): - ret[u] = {} - for s in u.src: ret[s][u] = None - return ret - - @functools.cached_property - def tuplize(self:UOp) -> tuple: - return (self.op.value, self.arg, self.dtype,)+tuple([x.tuplize for x in self.src]) - - # *** uop shape stuff *** - - @functools.cached_property - def st(self) -> ShapeTracker|None: - # VIEW and MovementOps define a new ShapeTracker from the arg - if self.op is Ops.VIEW: return self.arg - if self.op in GroupOp.Movement: return unwrap(self.src[0].st).mop(self.op, self.arg) - # BufferOps and ASSIGN flow ShapeTracker from a direct edge - if self.op in GroupOp.Buffer: return views[0] if (views:=[x.st for x in self.src if x.op is Ops.VIEW]) else None - if self.op is Ops.ASSIGN: return self.src[0].st - - from tinygrad.shape.shapetracker import ShapeTracker - # BUFFER/BUFFER_VIEW and KERNEL only have a size - if self.op in {Ops.BUFFER, Ops.BUFFER_VIEW}: return ShapeTracker.from_shape((self.size,)) - if self.op is Ops.KERNEL: return ShapeTracker.from_shape((self.arg.ast.size,)) - - # otherwise we get the shape from sources - if not (src_sts := [x.st for x in self.src if x.st is not None]): return None - assert all_same([x.shape for x in src_sts]), f"UOp sources must have the same shape {self} {[x.shape for x in src_sts]}" - match self.op: - case Ops.MULTI: shape = tuple(self.src[0].shape[a]*len(self.device) if a == self.axis else s for a,s in enumerate(self.src[0].shape)) - case Ops.BITCAST: - shape = src_sts[0].shape - if self.dtype.itemsize != (input_sz:=self.src[0].dtype.itemsize): shape = shape[:-1]+((shape[-1]*input_sz) // self.dtype.itemsize,) - case Ops.REDUCE_AXIS | Ops.WMMA: shape = src_sts[0].reduce(self.axis_arg) - case _: shape = src_sts[0].shape - return ShapeTracker.from_shape(shape) - - @functools.cached_property - def full_shape(self) -> tuple[sint, ...]: - if self.op is Ops.VIEW: return self.shape - # NOTE: if a parent doesn't have st its full_shape is empty - parent_shapes = [x.full_shape for x in self.src] - return tuple(smax(x) for x in zip(*[x for x in parent_shapes if x != ()])) - @property - def shape(self) -> tuple[sint, ...]: return unwrap(self.st).shape - @property - def size(self) -> int: return self.arg[0] if self.op is Ops.BUFFER_VIEW else self.arg if self.op is Ops.BUFFER else unwrap(self.st).size - - # *** uop evaluation *** - - def simplify(self): - # late import! - from tinygrad.codegen.symbolic import symbolic - with Context(TRACK_MATCH_STATS=0): - return graph_rewrite(self, symbolic) - def ssimplify(self) -> Union[UOp, ConstType]: return ret.arg if (ret:=self.simplify()).op is Ops.CONST else ret - def _eval(self, dtype, expected_type:Type[T]) -> T: - assert self.dtype in dtype, f"eval with wrong dtype {self}" - vmin, vmax = (simple_self:=self.simplify())._min_max - if vmin != vmax: raise ValueError(f"eval failed to be a single number, range is {vmin} to {vmax} in {simple_self.render()}") - assert isinstance(vmin, expected_type), f"vmin is wrong dtype {type(vmin)} != {expected_type}" - return vmin - def __bool__(self): return self._eval((dtypes.bool,), bool) - def __int__(self): return self._eval(dtypes.ints, int) - def __float__(self): return self._eval(dtypes.floats, float) - def substitute(self, dvars:dict[UOp, UOp], name:str|None=None): - dvars = {k:v for k,v in dvars.items() if k is not v} - if len(dvars) == 0: return self - with Context(TRACK_MATCH_STATS=(0 if name is None else TRACK_MATCH_STATS.value)): - return graph_rewrite(self, _substitute, dvars, bottom_up=True, name=name) - - # *** uop syntactic sugar *** - - @property - def st_arg(self) -> ShapeTracker: - assert self.op in GroupOp.Buffer, f"st_arg called on {self.op}" - return unwrap(self.st) - @property - def axis_arg(self) -> tuple[int, ...]: - assert self.op in {Ops.REDUCE_AXIS, Ops.WMMA}, f"axis_arg called on {self.op}" - ret = self.arg[1] if self.op is Ops.REDUCE_AXIS else self.arg[7] - assert isinstance(ret, tuple) and all(isinstance(x, int) for x in ret), f"axis_arg trying to return {ret}" - return ret - def sink(self, *srcs:UOp|None, **kwargs): return UOp(Ops.SINK, dtypes.void, (self,)+tuple([x for x in srcs if x is not None]), **kwargs) - def detach(self): return UOp(Ops.DETACH, self.dtype, (self,)) - def index(self, idx:UOp, valid:UOp|None=None): return UOp(Ops.INDEX, self.dtype, (self,idx,valid) if valid is not None else (self,idx)) - def const_like(self, b:ConstLike): - # constants can optionally have a DEVICE source - return UOp.const(self.dtype, b, device=self._device, shape=self.shape if self.st is not None else None) - def broadcast(self, count:int): - assert self.dtype.count == 1 - if count == 1: return self - return UOp(Ops.VECTORIZE, self.dtype.vec(count), (self,)*count) - def cast(self, dtype:DType): - if self.dtype == dtype: return self - return UOp(Ops.CAST, dtype, (self,)) - def cast_vec(self, dtype:DType): return UOp(Ops.CAST, dtype.vec(self.dtype.count), (self,)) - def bitcast(self, dtype:DType): return UOp(Ops.BITCAST, dtype, (self,)) - def gep(self, i:Union[tuple[int, ...], int]): - if isinstance(i, tuple) and len(i) == 1: return self.gep(i[0]) - if isinstance(i, int): - # NOTE: these are just shortcuts to not have to create and fold later - if self.op is Ops.VECTORIZE: return self.src[i] - if self.op is Ops.VCONST: return UOp.const(self.dtype.scalar(), self.arg[i]) - if self.op is Ops.CONST: return UOp.const(self.dtype.scalar(), self.arg) - i = (i,) - return UOp(Ops.GEP, self.dtype.scalar().vec(len(i)) if len(i) > 1 else self.dtype.scalar(), (self,), i) - def load(self, *src:UOp, **kwargs): - if 'dtype' not in kwargs: kwargs['dtype'] = self.dtype.base - return UOp(Ops.LOAD, src=(self,)+src, **kwargs) - def store(self, *src:UOp, **kwargs): return UOp(Ops.STORE, dtypes.void, (self,)+src, **kwargs) - def alu(self, arg, *src:UOp): - out_dtype = (self, *src)[-1].dtype - if arg in {Ops.CMPLT, Ops.CMPNE}: out_dtype = dtypes.bool.vec(out_dtype.count) if out_dtype.count > 1 else dtypes.bool - return UOp(arg, out_dtype, (self,)+src) - @staticmethod - def const(dtype:DType, b:ConstLike, device:str|tuple[str, ...]|None=None, shape:tuple[sint, ...]|None=None): - if isinstance(b, UOp): return b.unbind()[0] if b.op is Ops.BIND else b - if isinstance(b, tuple) and all_same(b): b = b[0] # doesn't have to be a VCONST if they are all the same - ret = UOp(Ops.VCONST if isinstance(b, tuple) else Ops.CONST, dtype, arg=dtypes.as_const(b, dtype)) - if shape is not None: - from tinygrad.shape.shapetracker import ShapeTracker - ret = ret.replace(src=(ShapeTracker.from_shape(()).reshape((1,)*len(shape)).expand(shape).to_uop(),)) - if device is not None: - ret = ret.replace(src=(UOp(Ops.DEVICE, arg=device).view(unwrap(ret.st)),)) - return ret - def valid(self): return UOp.where(UOp(Ops.VALID, dtypes.bool, (UOp(Ops.VIEW, arg=self.st),)), self.const_like(self.base.arg), 0) - @staticmethod - def range(dtype:DType, end:sint, idx:int): return UOp(Ops.RANGE, dtype=dtype, src=(sint_to_uop(end),), arg=idx) - def r(self, op:Ops, axis:tuple[int, ...]): - axis = tuple(sorted([x for x in axis if resolve(self.shape[x] != 1)])) - return self if len(axis) == 0 else UOp(Ops.REDUCE_AXIS, self.dtype, (self,), (op, axis)) - def assign(self, x:UOp): return UOp(Ops.ASSIGN, self.dtype, (self,x)) - def reduce(self, *src:UOp, **kwargs): return UOp(Ops.REDUCE, kwargs.pop('dtype', self.dtype), src=(self,)+src, **kwargs) - def contiguous(self): return self.alu(Ops.CONTIGUOUS) - def contiguous_backward(self): return self.alu(Ops.CONTIGUOUS_BACKWARD) - def fuse(self): return self.alu(Ops.FUSE) - def gbarrier(self): return self.alu(Ops.GBARRIER) - def allreduce(self, op, device:str|tuple[str, ...]|UOp): - assert isinstance(self.device, tuple), f"allreduce must be on tuple {self.device} isn't" - return UOp(Ops.ALLREDUCE, self.dtype, (self, UOp(Ops.DEVICE, arg=device) if not isinstance(device, UOp) else device), op) - - # *** from MultiLazyBuffer *** - - def multi(self, axis:int|None): - assert isinstance(self.device, tuple), f"multi device must be tuple, {self.device} isn't" - assert axis is not None, "multi None is no longer supported" - return UOp(Ops.MULTI, self.dtype, (self,), axis) - - @property - def bounds(self): - if self.axis is None: raise RuntimeError("bounds is not defined when axis is None") - return tuple(itertools.pairwise(itertools.accumulate([self.src[0].shape[self.axis] for _ in self.device], initial=0))) - - @functools.cached_property - def axis(self) -> Optional[int]: - if self.op is Ops.MULTI: return self.arg - # NOTE: they all have to share an axis, we always choose [-1] - if self.op in GroupOp.ALU: return axes[-1] if (axes := dedup([x.axis for x in self.src if x.axis is not None])) else None - if len(self.src) == 0: return None - src_axis = self.src[0].axis - if self.op is Ops.REDUCE_AXIS: return None if src_axis is not None and src_axis in self.arg[1] else src_axis - if self.op is Ops.RESHAPE: - if src_axis is None: return None - arg_acc:list[sint] = list(itertools.accumulate(self.arg, operator.mul, initial=1)) - # new_axis is the last one that preserves prod(prior to new_axis) and must not move items between shards - # TODO: what to do about shrinking to self.shape[self.axis]==1 len(self.real_lbs)==1? - return len(arg_acc) - arg_acc[::-1].index(prod(self.src[0].shape[:src_axis])) - 1 - if self.op is Ops.PERMUTE: return self.arg.index(src_axis) if src_axis is not None else None - return src_axis - - def _unshard(self, axis:int) -> UOp: - bsz, dcount = self.shape[axis], len(self.device) - dnum = UOp.variable("_device_num", 0, dcount-1) - return self.pad(tuple((0,0) if a != axis else (bsz*dnum, bsz*(dcount-1) - bsz*dnum) for a in range(len(self.shape)))) - - def _shard(self, axis:int) -> UOp: - dcount = len(self.device) - dnum = UOp.variable("_device_num", 0, dcount-1) - if self.shape[axis] % dcount != 0: raise RuntimeError(f"multi axis uneven: {self.shape[axis]=} {axis=} {dcount=}") - sz = self.shape[axis] // dcount - return self.shrink(tuple((0,s) if i != axis else (dnum*sz,dnum*sz+sz) for i,s in enumerate(self.shape))) - def shard(self, devices:tuple[str, ...], axis:int) -> UOp: return self.copy_to_device(devices)._shard(axis).multi(axis) - - # *** from LazyBuffer *** - - def copy_to_device(self, device:str|tuple[str, ...]|UOp, arg=None): - assert arg is None or isinstance(self.device, tuple) - inp = self if arg is None else UOp(Ops.MSELECT, self.dtype, src=(self,), arg=arg) - return UOp(Ops.COPY, self.dtype, (inp, UOp(Ops.DEVICE, arg=device) if not isinstance(device, UOp) else device)) - def mselect(self, arg:int) -> UOp: return UOp(Ops.MSELECT, self.dtype, (self,), arg) - @property - def metadata(self) -> tuple[Metadata, ...]|None: return all_metadata.get(self, None) - - # *** uop movement ops *** - - @property - def base(self) -> UOp: - if (self.op is Ops.VIEW and len(self.src) != 0) or self.op in GroupOp.Movement: return self.src[0].base - if self.op is Ops.MULTI: return self.src[0].base # MULTI is really a VIEW - return self - def view(self, new_st:ShapeTracker) -> UOp: return UOp(Ops.VIEW, self.dtype, (self,), new_st) - - def _mop(self, op:Ops, arg): - ret = UOp(op, self.dtype, (self,), arg) - if self.st == ret.st: return self # ignore NOOPs, also check ret.st - return ret - - def reshape(self, arg:tuple[sint, ...]): return self._mop(Ops.RESHAPE, arg) - def pad(self, arg:tuple[tuple[sint, sint], ...]): return self._mop(Ops.PAD, arg) - def expand(self, arg:tuple[sint, ...]): return self._mop(Ops.EXPAND, arg) - def permute(self, arg:tuple[sint, ...]): return self._mop(Ops.PERMUTE, arg) - def shrink(self, arg:tuple[tuple[sint, sint], ...]): return self._mop(Ops.SHRINK, arg) - def flip(self, arg:tuple[bool, ...]): return self._mop(Ops.FLIP, arg) - - # *** uop UNIQUE *** - - # TODO: use this in Buffer - unique_num = itertools.count(0) - @staticmethod - def unique(): return UOp(Ops.UNIQUE, arg=next(UOp.unique_num)) - - # *** uop Buffer stuff *** - - @staticmethod - def new_buffer(device:str|tuple[str, ...], size:int, dtype:DType): return UOp(Ops.BUFFER, dtype, (UOp.unique(), UOp(Ops.DEVICE, arg=device)), size) - @property - def device(self) -> str|tuple[str, ...]: return cast(str|tuple[str, ...], unwrap(self._device)) - @functools.cached_property - def _device(self) -> Optional[str|tuple[str, ...]]: - if self.op is Ops.DEVICE: return self.arg - if self.op is Ops.MSELECT: - assert isinstance(self.src[0].device, tuple), "mselect must be on tuple device" - return self.src[0].device[self.arg] - if self.op is Ops.MSTACK: return tuple(cast(str, x.device) for x in self.src) - if self.op in {Ops.COPY, Ops.BUFFER, Ops.ALLREDUCE}: return self.src[1].device - return dsrcs[0]._device if len(dsrcs:=[x for x in self.src if x._device is not None]) != 0 else None - @property - def buf_uop(self) -> UOp: - if self.op is Ops.BUFFER: return self - if self.op is Ops.MSELECT: return self.src[0].buf_uop.mselect(self.arg) - if self.op is Ops.MSTACK: return UOp(Ops.MSTACK, self.dtype, src=tuple(x.buf_uop for x in self.src)) - assert self.op is Ops.ASSIGN, f"must be ASSIGN {self.op}" - return self.src[0].base - @property - def buffer(self) -> Buffer|MultiBuffer: - from tinygrad.device import Buffer, MultiBuffer - if self is not self.base: - assert unwrap(self.st).contiguous, "VIEW only works here if it's contiguous" - return self.src[0].buffer - if self.op is Ops.MSELECT: - ret = self.src[0].buffer - assert isinstance(ret, MultiBuffer) - return ret.bufs[self.arg] - if self.op is Ops.MSTACK: - ret = MultiBuffer.__new__(MultiBuffer) - ret.bufs = [cast(Buffer, x.buffer) for x in self.src] - assert all_same([x.size for x in ret.bufs]) and all_same([x.dtype for x in ret.bufs]), "multibuffers mismatch buffers" - return ret - assert self.op is Ops.BUFFER, f"must be BUFFER {self.op}" - if (cret:=buffers.get(self)) is not None: return cret - rdtype = self.dtype if isinstance(self.dtype, ImageDType) else self.dtype.base - if isinstance(self.device, tuple): ret = MultiBuffer(self.device, self.size, rdtype).ref(1) - else: ret = Buffer(self.device, self.size, rdtype).ref(1) - buffers[self] = ret - return ret - @property - def realized(self) -> Optional[Buffer|MultiBuffer]: - # NOTE: this is used by the JIT to determine which inputs we capture - return self.buffer if self.op in {Ops.BUFFER, Ops.MSTACK} and self.buffer.is_allocated() else None - @property - def is_realized(self) -> bool: - return all(x.base.realized is not None for x in self.base.src) if self.base.op is Ops.MULTI else self.base.realized is not None - - # *** uop Variable stuff *** - - @staticmethod - def variable(name:str, min_val:ConstType, max_val:ConstType, dtype:DType=dtypes.int): - assert not isinstance(min_val, UOp) and not isinstance(max_val, UOp), f"can't create Variable {name} with {min_val}/{max_val}" - return UOp(Ops.DEFINE_VAR, dtype, arg=(name, min_val, max_val)) - @property - def expr(self): - assert self.op is Ops.DEFINE_VAR, f"op is {self.op}, need DEFINE_VAR" - return self.arg[0] - def bind(self, val:int): - assert self.op is Ops.DEFINE_VAR, f"op is {self.op}, need DEFINE_VAR" - assert self.arg[1] <= val and val <= self.arg[2], f"bind {val} not in range [{self.arg[1]}, {self.arg[2]}]" - return UOp(Ops.BIND, self.dtype, (self, self.const_like(val))) - def unbind(self) -> tuple[Variable, int]: - assert self.op is Ops.BIND and self.src[0].op is Ops.DEFINE_VAR and self.src[1].op is Ops.CONST, f"can't unbind {self}" - return self.src[0], self.src[1].arg - @property - def val(self) -> int: return self.unbind()[1] - def vars(self) -> set[UOp]: - bound_vars = set([x for x in self.toposort() if x.op is Ops.BIND and x.src[0].op is Ops.DEFINE_VAR]) - bound_var_base = set(x.src[0] for x in bound_vars) - all_vars = set([x for x in self.toposort() if x.op is Ops.DEFINE_VAR]) - return bound_vars.union(set([x for x in all_vars if x not in bound_var_base])) - def variables(self) -> list[Variable]: - st_vars: list[set[Variable]] = [x.st_arg.vars() for x in self.toposort() if x.op in GroupOp.Buffer] - return sorted(set.union(*st_vars, set([x.unbind()[0] if x.op is not Ops.DEFINE_VAR else x for x in self.vars()])), key=lambda v: v.arg) - - # *** uop symbolic stuff *** - - def is_increasing(self:UOp) -> bool: - # is f a monotonically increasing function regards its input - if self.op in GroupOp.Irreducible: return True - if self.op is Ops.ADD: return self.src[0].is_increasing() and self.src[1].is_increasing() - if self.op in (Ops.MUL, Ops.IDIV) and self.src[1].op is Ops.CONST and self.src[1].arg >= 0: return self.src[0].is_increasing() - return False # False if not sure - def const_factor(self) -> int: - """largest known int that divides self""" - # TODO: for negatives it's not the largest - if self.op is Ops.CONST: return self.arg - if self.op is Ops.VCONST: return math.gcd(*self.arg) - if self.op is Ops.ADD: return math.gcd(self.src[0].const_factor(), self.src[1].const_factor()) - if self.op is Ops.MUL: return self.src[0].arg if self.src[0].op is Ops.CONST else self.src[1].arg if self.src[1].op is Ops.CONST else 1 - return 1 - def divides(self, v:int) -> UOp|None: - if v==1: return self - if self.op is Ops.CONST: return self.const_like(self.arg//v) if self.arg%v == 0 else None - if self.op is Ops.VCONST: return self.const_like(tuple(x//v for x in self.arg)) if all(x%v == 0 for x in self.arg) else None - if self.op is Ops.ADD: return d0+d1 if (d0:=self.src[0].divides(v)) is not None and (d1:=self.src[1].divides(v)) is not None else None - if self.op is Ops.MUL: - if (d0:=self.src[0].divides(v)) is not None: return d0 * self.src[1] - if (d1:=self.src[1].divides(v)) is not None: return self.src[0] * d1 - return None # generic None if we aren't sure - @property - def vmin(self) -> ConstType: return self._min_max[0] - @property - def vmax(self) -> ConstType: return self._min_max[1] - @functools.cached_property - def _min_max(self) -> tuple[ConstType, ConstType]: - if self.op in GroupOp.Binary and not dtypes.is_float(self.dtype): - (s0_vmin, s0_vmax), (s1_vmin, s1_vmax) = self.src[0]._min_max, self.src[1]._min_max - if self.op is Ops.ADD: return s0_vmin+s1_vmin, s0_vmax+s1_vmax - if self.op is Ops.SUB: return s0_vmin-s1_vmax, s0_vmax-s1_vmin - if self.op is Ops.AND and s1_vmin == s1_vmax and s0_vmin >= 0 and s1_vmin >= 0: return min(0, s0_vmin), min(s0_vmax, s1_vmax) - if self.op is Ops.MUL: return min(vals:=(s0_vmin*s1_vmin, s0_vmin*s1_vmax, s0_vmax*s1_vmin, s0_vmax*s1_vmax)), max(vals) - # SHL/SHR on consts only - if self.op is Ops.SHL and s1_vmin == s1_vmax and all_int(t:=(s0_vmin, s0_vmax, s1_vmin)): return t[0] << t[2], t[1] << t[2] - if self.op is Ops.SHR and s1_vmin == s1_vmax and all_int(t:=(s0_vmin, s0_vmax, s1_vmin)): return t[0] >> t[2], t[1] >> t[2] - if self.op is Ops.MOD: - if s1_vmin > 0: return (0, s1_vmax-1) if s0_vmin >= 0 else (-(s1_vmax-1), 0) if s0_vmax <= 0 else (-(s1_vmax-1), s1_vmax-1) - if s1_vmax < 0: return (0, -s1_vmax-1) if s0_vmin >= 0 else (-(-s1_vmax-1), 0) if s0_vmax <= 0 else (-(-s1_vmax-1), -s1_vmax-1) - if self.op is Ops.IDIV: - assert isinstance(s0_vmin, int) and isinstance(s0_vmax, int) and isinstance(s1_vmin, int) and isinstance(s1_vmax, int) - if (c:=s1_vmin) == s1_vmax: # s1 is a const - if c > 0: return cdiv(s0_vmin, c), cdiv(s0_vmax, c) - if c < 0: return cdiv(s0_vmax, c), cdiv(s0_vmin, c) - if (s0_vmax <= 0 and s1_vmax < 0): return cdiv(s0_vmax, s1_vmin), cdiv(s0_vmin, s1_vmax) - if (s0_vmin >= 0 and s1_vmin > 0): return cdiv(s0_vmin, s1_vmax), cdiv(s0_vmax, s1_vmin) - if (s0_vmax <= 0 and s1_vmin > 0): return cdiv(s0_vmin, s1_vmin), cdiv(s0_vmax, s1_vmax) - if (s0_vmin >= 0 and s1_vmax < 0): return cdiv(s0_vmax, s1_vmax), cdiv(s0_vmin, s1_vmin) - if self.op is Ops.MAX: return max(s0_vmin, s1_vmin), max(s0_vmax, s1_vmax) - if self.op is Ops.CMPLT: return (s0_vmax str: - ret = graph_rewrite(self.simplify() if simplify else self, renderer if pm is None else pm) - return ret.arg if ret.op is Ops.NOOP else str(ret) - -@dataclass(frozen=True) -class KernelInfo: - name: str = "test" # name of the kernel - local_dims: int = 0 # number of local dimensions (this is remapping RANGE to SPECIAL) - upcasted: int = 0 # count that are upcasted (this is remapping RANGE to UNROLL) - dont_use_locals: bool = False # don't use local indexing - -# ******** ops in python ******** - -def safe_exp2(x): - try: return 2 ** x - except OverflowError: return math.inf - -def safe_pow(x, y): - try: return math.nan if isinstance(p:=pow(x, y), complex) else p - except ZeroDivisionError: return math.inf - except ValueError: return math.inf if x > 0 else -math.inf - -python_alu: dict[Ops, Callable] = { - Ops.LOG2: lambda x: math.log2(x) if x > 0 else -math.inf if x == 0 else math.nan, Ops.EXP2: safe_exp2, - Ops.SQRT: lambda x: math.sqrt(x) if x >= 0 else math.nan, Ops.RECIP: lambda x: 1/x if x != 0 else math.copysign(math.inf, x), - Ops.SIN: lambda x: math.sin(x) if not math.isinf(x) else math.nan, Ops.POW: safe_pow, - Ops.NEG: operator.neg, Ops.ADD: operator.add, Ops.SUB: operator.sub, Ops.MUL: operator.mul, Ops.CMPNE: operator.ne, Ops.CMPLT: operator.lt, - Ops.XOR: operator.xor, Ops.OR: operator.or_, Ops.AND: operator.and_, Ops.SHR: operator.rshift, Ops.SHL: operator.lshift, Ops.MAX: max, - Ops.MOD: cmod, Ops.IDIV: cdiv, Ops.MULACC: lambda x,y,z: (x*y)+z, Ops.WHERE: lambda x,y,z: y if x else z} - -def exec_alu(op:Ops, dtype:DType, operands, truncate_output=True): - if dtype.count > 1: - return tuple([exec_alu(op, dtype.scalar(), [x[i] if isinstance(x, tuple) else x for x in operands]) for i in range(dtype.count)]) - alu = python_alu[op](*operands) - return truncate.get(dtype, lambda x: x)(alu) if truncate_output else alu - -# ***** uop helpers ***** - -def print_uops(uops:list[UOp]): - for i,u in enumerate(uops): - formatted_parents = [(uops.index(x) if x.op is not Ops.CONST else f"{x.arg}") if x in uops else "--" for x in u.src] - print(f"{i:4d} {str(u.op):20s}: {str(u.dtype):30s} " f"{str(formatted_parents):32s} {u.arg}") - -# ***** pattern matcher ***** - -def get_location() -> tuple[str, int]: - frm = sys._getframe(1) - # skip over ops.py (unless there's nothing but ops.py) - while pathlib.Path(frm.f_code.co_filename).name == "ops.py" and frm.f_back is not None and not frm.f_back.f_code.co_filename.startswith(" list[str]: - with open(fn) as f: return f.readlines() - -class UPat(MathTrait): - __slots__ = ("op", "dtype", "arg", "name", "src") - def __init__(self, op:Optional[Union[Ops, tuple[Ops, ...], set[Ops]]]=None, dtype:Optional[Union[DType, tuple[DType, ...]]]=None, - src:Optional[Union[tuple[UPat, ...], list[UPat], UPat]]=None, arg:Any=None, - name:Optional[str]=None, allow_any_len:bool=False, custom_early_reject:Optional[set[Ops]]=None, location=None): - assert op is None or isinstance(op, (Ops, tuple, set)), "op must be Ops or tuple of Ops" - self.op: Optional[tuple[Ops, ...]] = (op,) if isinstance(op, Ops) else (tuple(op) if isinstance(op, set) else op) - self.dtype: Optional[tuple[DType, ...]] = (dtype,) if isinstance(dtype, DType) else dtype - self.arg, self.name, self._in_src, self.custom_early_reject = arg, name, src, custom_early_reject - self.src: Any = None - assert self.name != "ctx", "UPat can't be named ctx" - assert dtype is None or isinstance(dtype, DType) or all(isinstance(x, DType) for x in dtype), f"invalid dtype {dtype}" - - # try all permutations if it's a list - if isinstance(src, list): self.src = list(itertools.permutations(src)) if not all_same(src) else [tuple(src)] - # only one if it's a tuple - elif isinstance(src, tuple): self.src = [src] - # repeat if it's a UPat - elif isinstance(src, UPat): self.src = [itertools.repeat(src)] - - self.strict_length = not (allow_any_len or isinstance(src, UPat) or src is None) - self.required_len: int = 0 if isinstance(src, UPat) or src is None else len(src) - self.location = location or get_location() - - if custom_early_reject is not None: self.early_reject = custom_early_reject - else: - upat_match = [src] if isinstance(src, UPat) else ([] if src is None else self.src[0]) - self.early_reject = {pp.op[0] for pp in upat_match if pp.op is not None and len(pp.op) == 1} - - def __reduce__(self): - return UPat, (self.op, self.dtype, self._in_src, self.arg, self.name, not self.strict_length, self.custom_early_reject, self.location) - def named(self, name:str): return UPat(self.op, self.dtype, self._in_src, self.arg, name, not self.strict_length, self.custom_early_reject) - - @staticmethod - def any(*src): return UPatAny(src=src) - def or_casted(self, name:str|None=None): return UPat.any(self if name is None else self.named(name), UPat(Ops.CAST, name=name, src=(self,))) - - @staticmethod - @functools.cache - def var(name:Optional[str]=None, dtype:Optional[Union[DType, tuple[DType, ...]]]=None): return UPat(dtype=dtype, name=name) - @staticmethod - @functools.cache - def cvar(name:Optional[str]=None, dtype:Optional[DType]=None, vec=True): return UPat((Ops.CONST,Ops.VCONST) if vec else Ops.CONST, dtype, name=name) - @staticmethod - def const(dtype:Optional[Union[DType, tuple[DType, ...]]], b:ConstType): return UPat(Ops.CONST, dtype=dtype, arg=b) - - # copied from UOp - def index(self, idx:UPat, valid:Optional[UPat]=None): return UPat(Ops.INDEX, self.dtype, (self,idx,valid) if valid is not None else (self,idx)) - def view(self, st=None, **kwargs): return UPat(Ops.VIEW, self.dtype, (self,), st, **kwargs) - def cast(self, dtype=None, **kwargs): return UPat(Ops.CAST, dtype, (self,), **kwargs) - def bitcast(self, dtype=None): return UPat(Ops.BITCAST, dtype, (self,)) - def gep(self, i:int|None=None, **kwargs): return UPat(Ops.GEP, None, (self,), (i,) if i is not None else None, **kwargs) - def load(self, *src:UPat, **kwargs): return UPat(Ops.LOAD, src=(self,)+src, **kwargs) - def store(self, *src:UPat, **kwargs): return UPat(Ops.STORE, dtypes.void, (self,)+src, **kwargs) - def assign(self, x:UPat, **kwargs): return UPat(Ops.ASSIGN, self.dtype, (self,x), **kwargs) - def reduce(self, *src:UPat, **kwargs): return UPat(Ops.REDUCE, self.dtype, src=(self,)+src, **kwargs) - def fuse(self): return self.alu(Ops.FUSE) - def or_broadcasted(self, **kwargs): return UPat.any(self, UPat(Ops.VECTORIZE, self.dtype, src=self, **kwargs)) - - def const_like(self, b:ConstLike): return UPat.const(self.dtype, cast(ConstType, b)) - def alu(self, op:Ops, *src:UPat): - asrc = (self,)+src - return UPat(op, dtypes.bool if op in {Ops.CMPLT, Ops.CMPNE} else asrc[-1].dtype, list(asrc) if op in GroupOp.Commutative else asrc) - - def printable(self:UPat) -> str: - try: return lines(self.location[0])[self.location[1]-1].strip() - except FileNotFoundError: return "" - - def __repr__(self): - def rep(x): - form = "UPat(%s, %s, name=%s, dtype=%s, allow_any_len=%s, src=%s)" - return form % (None if x.op is None else ('(%s)'%', '.join(map(str, x.op))), x.arg, repr(x.name), - set(x.dtype) if x.dtype else None, not x.strict_length, "[%s]" if x.src and len(x.src)>1 else ("(%s)" if x.src else "%s")) - return pretty_print(self, rep, srcfn=lambda x:None if x.src is None else [next(x.src[0])] if isinstance(x.src[0], itertools.repeat) else x.src[0]) - - def match(self:UPat, uop:UOp, store:dict[str, UOp]) -> list[dict[str, UOp]]: - if (self.op is not None and uop.op not in self.op) or \ - (self.name is not None and store.setdefault(self.name, uop) is not uop) or \ - (self.dtype is not None and uop.dtype not in self.dtype and uop.dtype.scalar() not in self.dtype) or \ - (self.arg is not None and self.arg != uop.arg) or \ - (len(uop.src) < self.required_len) or \ - (self.strict_length and len(uop.src) != self.required_len): return [] - if self.src is None: return [store] - res: list[dict[str, UOp]] = [] - for vp in self.src: - stores, new_stores = [store.copy()], [] - for uu, vv in zip(uop.src, vp): - for s in stores: new_stores.extend(vv.match(uu, s)) - stores, new_stores = new_stores, [] - res.extend(stores) - return res - -class UPatAny(UPat): - def match(self:UPat, uop:UOp, store:dict[str, UOp]) -> list[dict[str, UOp]]: - matches = [x.match(uop, store.copy()) for x in self.src[0]] - return flatten([x for x in matches if x is not None]) - -def deconstruct_function(fxn:Callable) -> tuple: - new_globals = {k:v for k,v in fxn.__globals__.items() if k in fxn.__code__.co_names} - for co in fxn.__code__.co_consts: - if isinstance(co, types.CodeType): new_globals.update({k:v for k,v in fxn.__globals__.items() if k in co.co_names}) - # NOTE: optional round trip through pickle! - assert fxn.__closure__ is None, "closures are not supported in pattern matchers" - ret = fxn.__code__, new_globals, fxn.__name__, fxn.__defaults__ - return pickle.loads(pickle.dumps(ret)) if getenv("TEST_PICKLE") else ret - -@functools.cache -def upat_interpret(p:UPat, fxn:Callable) -> Callable: - real_fxn = types.FunctionType(*deconstruct_function(fxn)) - if 'ctx' in inspect.signature(real_fxn).parameters: - def universal_match(uop, ctx): - for match in p.match(uop, {}): - if (ret:=real_fxn(ctx=ctx, **match)) is not None: return ret # pylint: disable=not-callable - return None - else: - def universal_match(uop, _): - for match in p.match(uop, {}): - if (ret:=real_fxn(**match)) is not None: return ret # pylint: disable=not-callable - return None - return universal_match - -class PatternMatcher: - def __init__(self, patterns:Sequence[tuple[UPat, Callable|tuple]], compiled=bool(getenv("UPAT_COMPILE", 1))): - if compiled: from tinygrad.uop.upat import upat_compile - # if this comes from a pickle, we reconstruct the lambda functions here - self.patterns:list[tuple[UPat, Callable]] = [(p,types.FunctionType(*fxn) if isinstance(fxn, tuple) else fxn) for p,fxn in patterns] - # NOTE: use of DefaultDict here is very dangerous! all keys will live for the lifetime of the PatternMatcher! - self.pdict: dict[Ops, list[tuple[UPat, Callable, set]]] = {} - # uop is required, arg is optional - for p,fxn in self.patterns: - assert p.op is not None - if compiled and (match:=upat_compile(p, fxn)) is not None: pass # pylint: disable=E0606 - else: match = upat_interpret(p, fxn) - for uop in p.op: self.pdict.setdefault(uop, []).append((p, match, p.early_reject)) - - def __reduce__(self): return PatternMatcher, ([(x,deconstruct_function(fxn) if fxn.__name__ == "" else fxn) for x,fxn in self.patterns],) - - @functools.cache # pylint: disable=method-cache-max-size-none - def __add__(self, more:PatternMatcher): return PatternMatcher(self.patterns+more.patterns) - - def rewrite(self, uop:UOp, ctx=None) -> UOp|None: - ler = {u.op for u in uop.src} - for _,match,early_reject in self.pdict.get(uop.op, []): - if not early_reject.issubset(ler): continue - if (ret:=match(uop, ctx)) is not None: return ret - return None - - def fixed_point_rewrite(self, uop:UOp, ctx=None) -> UOp: - # apply rewrite rules until a fixed point is reached. may return `uop` itself if PatternMatcher doesn't match - new_n: UOp|None = uop - while new_n is not None: last_n, new_n = new_n, self.rewrite(new_n, ctx) - return last_n - -# *** tracking pattern matcher *** - -TRACK_MATCH_STATS = ContextVar("TRACK_MATCH_STATS", 2 if getenv("VIZ") else 0) -match_stats:dict[UPat, list[Union[int, float]]] = dict() -@dataclass(frozen=True) -class TrackedGraphRewrite: - loc: tuple[str, int] # location that called graph_rewrite - sink: UOp # the sink input to graph_rewrite - matches: list[tuple[UOp, UOp, UPat]] # before+after of all the matches - name: str|None # optional name of the rewrite - depth: int # depth if it's a subrewrite - bottom_up: bool -tracked_keys:list[Any] = [] -tracked_ctxs:list[list[TrackedGraphRewrite]] = [] -_name_cnt:dict[str, int] = {} - -if getenv("CAPTURE_PROCESS_REPLAY"): - replay_capture: dict[str, bytes] = {} - import atexit - @atexit.register - def save_to_diskcache(): - for k,v in replay_capture.items(): diskcache_put("process_replay", k, v, prepickled=True) - -def track_rewrites(named=False, name_fxn:Callable|None=None): - def _decorator(func): - def __wrapper(*args, **kwargs): - if TRACK_MATCH_STATS >= 2: - if (count_names:=(named or name_fxn or not args)): _name_cnt[func.__name__] = _name_cnt.get(func.__name__, 0)+1 - tracked_keys.append(f"{func.__name__}_{_name_cnt[func.__name__]}" if count_names else args[0]) - tracked_ctxs.append([]) - ret = func(*args, **kwargs) - if TRACK_MATCH_STATS >= 2 and name_fxn is not None: tracked_keys[-1] = f"{name_fxn(*args, **kwargs, ret=ret)} n{_name_cnt[func.__name__]}" - if getenv("CAPTURE_PROCESS_REPLAY"): - # find the unittest frame we're capturing in - frm = sys._getframe(1) - while (f_back:=frm.f_back) is not None and "unittest" not in f_back.f_code.co_filename: frm = f_back - loc = f"{frm.f_code.co_filename.split('/')[-1]}:{frm.f_lineno} {frm.f_code.co_name}" - # capture global context vars and all the args passed in - with Context(PICKLE_BUFFERS=0): - inputs = (func.__name__, args, kwargs, ContextVar._cache) - replay_capture[hashlib.sha256(pickle.dumps(inputs)).hexdigest()] = pickle.dumps(inputs+(loc, ret)) - return ret - return __wrapper - return _decorator - -active_rewrites:list[TrackedGraphRewrite] = [] -def track_matches(func): - def _track_func(*args, **kwargs): - if tracking:=(TRACK_MATCH_STATS >= 2 and tracked_ctxs): - loc = ((frm:=sys._getframe(1)).f_code.co_filename, frm.f_lineno) - depth = len(active_rewrites) - tracked_ctxs[-1].append(ctx:=TrackedGraphRewrite(loc, args[0], [], kwargs.get("name", None), depth, kwargs.get("bottom_up", False))) - active_rewrites.append(ctx) - ret = func(*args, **kwargs) - if tracking: active_rewrites.pop() - return ret - return _track_func - -class TrackedPatternMatcher(PatternMatcher): - def rewrite(self, uop:UOp, ctx=None) -> UOp|None: - ret = None - ler = {u.op for u in uop.src} - for p,match,early_reject in self.pdict.get(uop.op, []): - if p not in match_stats: match_stats[p] = [0,0,0.0,0.0] - st = time.perf_counter() - if not early_reject.issubset(ler): - match_stats[p][2] += time.perf_counter()-st - continue - match_stats[p][1] += 1 - if (ret:=match(uop, ctx)) is not None: - match_stats[p][0] += 1 - match_stats[p][3] += (et:=time.perf_counter()-st) - if TRACK_MATCH_STATS >= 3: print(f"{et*1e6:7.2f} us -- ", p.printable()) - if TRACK_MATCH_STATS >= 2 and isinstance(ret, UOp) and active_rewrites: active_rewrites[-1].matches.append((uop, ret, p)) - return ret - match_stats[p][2] += time.perf_counter()-st - return None - -if TRACK_MATCH_STATS: - PatternMatcher = TrackedPatternMatcher # type: ignore - import atexit - @atexit.register - def print_match_stats(): - if TRACK_MATCH_STATS >= 2: - with open(fn:=temp("rewrites.pkl", append_user=True), "wb") as f: - print(f"rewrote {len(tracked_ctxs)} graphs and matched {sum(len(r.matches) for x in tracked_ctxs for r in x)} times, saved to {fn}") - with Context(PICKLE_BUFFERS=0): pickle.dump((tracked_keys, tracked_ctxs), f) - if getenv("VIZ"): launch_viz("VIZ", temp("rewrites.pkl", append_user=True)) - if getenv("PRINT_MATCH_STATS", 1): - ret = [0,0,0.0,0.0] - for k,v in sorted(list(match_stats.items()), key=lambda x: x[1][2]+x[1][3]): - loc_str = f"{k.location[0].split('/')[-1]}:{k.location[1]}" - if v[1] != 0: print(f"{v[0]:6d} / {v[1]:7d} -- {v[3]*1000.:9.2f} / {(v[2]+v[3])*1000.:9.2f} ms -- {loc_str:20s}", k.printable()) - ret = [x+y for x,y in zip(ret, v)] - print(f"{ret[0]:6d} / {ret[1]:7d} -- {ret[3]*1000.:9.2f} / {(ret[2]+ret[3])*1000.:9.2f} ms -- TOTAL") - -def launch_viz(env_str:str, data:str): - os.environ[env_str] = "0" - os.environ[f"{env_str}_DATA"] = data - if not int(os.getenv("VIZ", "0")) and not int(os.getenv("PROFILE", "0")): - args = ['--kernels', getenv("VIZ_DATA", "")] if getenv("VIZ_DATA", "") else [] - args += ['--profile', getenv("PROFILE_DATA", "")] if getenv("PROFILE_DATA", "") else [] - os.execv(sys.executable, [sys.executable] + [os.path.join(os.path.dirname(__file__), "../", "viz", "serve.py")] + args) - -# *** simple graph rewrite engine *** - -class RewriteContext: - def __init__(self, pm, ctx=None): - self.pm: PatternMatcher = pm - self.ctx = ctx - self.replace: dict[UOp, UOp] = {} - - def unified_rewrite(self, root:UOp, bottom_up=False) -> UOp: - stack: list[tuple[UOp, int, UOp]] = [(root, 0, root)] - while stack: - n, stage, new_n = stack.pop() - if n in self.replace: continue # skip any nodes we have seen - if stage == 0: - # if bottom up, we rewrite this node early. in both cases, we add its parents to the stack - if bottom_up: new_n = self.pm.fixed_point_rewrite(new_n, self.ctx) - stack.append((n, 1, new_n)) - for x in reversed(new_n.src): stack.append((x, 0, x)) - elif stage == 1: - if (new_src:=tuple([self.replace[x] for x in new_n.src])) == new_n.src: - # if top down, do the rewrite. if no rewrite or bottom up, we are done rewriting this node so we add it to the dict - if bottom_up or (new_src_n:=self.pm.rewrite(new_n, self.ctx)) is None: - self.replace[n] = new_n - continue - else: - # if srcs changed from rewrites, construct a new UOp with the new srcs - new_src_n = UOp(new_n.op, new_n.dtype, new_src, new_n.arg, new_n.tag) - # trigger a rewrite of new_src_n, then after that rewrite is done, link it back to n - stack.append((n, 2, new_src_n)) - stack.append((new_src_n, 0, new_src_n)) - else: - # in stage 2, we link the result of new_n to the result of n - self.replace[n] = self.replace[new_n] - return self.replace[root] - -@track_matches -def graph_rewrite(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None) -> UOp: - rewrite_ctx = RewriteContext(pm, ctx) - return rewrite_ctx.unified_rewrite(sink, bottom_up) - -@track_matches -def graph_rewrite_map(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None, input_map:dict[UOp, UOp]|None=None) -> dict[UOp, UOp]: - rewrite_ctx = RewriteContext(pm, ctx) - new_map: dict[UOp, UOp] = {} - for k in sink.toposort(): - new_map[k] = v = rewrite_ctx.unified_rewrite(k, bottom_up) - if k is not v and k.metadata is not None: all_metadata[v] = tuple(dedup(all_metadata.get(v, ())))+k.metadata - if input_map is not None: - for k,v in input_map.items(): new_map[k] = new_map.get(v,v) - return new_map - -def sint_to_uop(x:sint, dtype:DType=dtypes.int) -> UOp: return UOp.const(dtype, x) if isinstance(x, int) else x - -_substitute = PatternMatcher([(UPat(tuple(Ops), name="x"), lambda ctx,x: ctx.get(x,None))]) - -# for debug -syms = { Ops.ADD: "+", Ops.SUB: "-", Ops.IDIV: "//", Ops.MOD: "%", Ops.SHL: "<<", Ops.SHR: ">>", - Ops.MUL: "*", Ops.CMPLT: "<", Ops.CMPNE: "!=", Ops.AND: "&", Ops.OR: "|", Ops.XOR: "^"} -renderer = PatternMatcher([ - (UPat((Ops.DEFINE_VAR, Ops.SPECIAL), name="x"), lambda x: UOp(Ops.NOOP, arg=x.arg[0])), - (UPat(Ops.RANGE, name="x"), lambda x: UOp(Ops.NOOP, arg=f"ridx{x.arg}")), - (UPat((Ops.CONST, Ops.VCONST), name="x"), lambda x: UOp(Ops.NOOP, arg=str(x.arg))), - (UPat(Ops.UNROLL, name="x"), lambda x: UOp(Ops.NOOP, arg=f"UNROLL({x.src[0].arg}, {x.arg})")), - (UPat(Ops.CAST, name="x"), lambda x: UOp(Ops.NOOP, arg=f"({str(x.dtype)[7:]})({x.src[0].arg})")), - (UPat(Ops.LOAD), lambda: UOp(Ops.NOOP, arg="load")), - (UPat(Ops.BIND, src=UPat(Ops.NOOP), name="x"), lambda x: x.src[0]), - #(UPat(Ops.BIND, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"{x.src[0].arg}[={x.src[1].arg}]")), - (UPat(Ops.NEG, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(-{x.src[0].arg})")), - (UPat(Ops.MAX, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"max({x.src[0].arg}, {x.src[1].arg})")), - (UPat(Ops.MULACC, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"({x.src[0].arg}*{x.src[1].arg}+{x.src[2].arg})")), - (UPat(Ops.WHERE, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"({x.src[1].arg} if {x.src[0].arg} else {x.src[2].arg})")), - (UPat(GroupOp.ALU, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"({x.src[0].arg}{syms[x.op]}{x.src[1].arg})")), -]) -renderer_infer = PatternMatcher([ - (UPat(Ops.MOD, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"cmod({x.src[0].arg}, {x.src[1].arg})")), - (UPat(Ops.IDIV, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"cdiv({x.src[0].arg}, {x.src[1].arg})")), - *renderer.patterns -]) - -# *** what was symbolic.py *** - -sint = Union[int, UOp] -Variable = UOp - -ConstLike = Union[ConstType, Variable, tuple[ConstType, ...]] diff --git a/tinygrad/tinygrad/uop/spec.py b/tinygrad/tinygrad/uop/spec.py deleted file mode 100644 index dca56dc9..00000000 --- a/tinygrad/tinygrad/uop/spec.py +++ /dev/null @@ -1,228 +0,0 @@ -from typing import cast, Callable -from tinygrad.uop.ops import PatternMatcher, UPat, GroupOp, Ops, UOp, print_uops, python_alu, graph_rewrite, resolve -from tinygrad.dtype import DType, ImageDType, dtypes, PtrDType -from tinygrad.helpers import all_same, prod, DEBUG, ContextVar, Context -try: - import z3 - - # IDIV is truncated division but z3 does floored division; mod by power of two sometimes uses Ops.AND - def z3_cdiv(a,b): return z3.If(a<0, (a+(b-1))/b, a/b) - z3_alu: dict[Ops, Callable] = python_alu | {Ops.MOD: lambda a,b: a-z3_cdiv(a,b)*b, Ops.IDIV: z3_cdiv, Ops.SHR: lambda a,b: a/(2**b.as_long()), - Ops.SHL: lambda a,b: a*(2**b.as_long()), Ops.AND: lambda a,b: a%(b+1) if isinstance(b, z3.ArithRef) else a&b, Ops.WHERE: z3.If, - Ops.MAX: lambda a,b: z3.If(a z3.ArithRef: - s = z3.Int(name, ctx=solver.ctx) - solver.add(vmin <= s, s <= vmax) - return s - - # ctx is (solver, load_number_dict) - z3_renderer = PatternMatcher([ - # Ops.SPECIAL can have symbolic arg but it wont be in the toposort beacuse its not a src, we need to add it manually - (UPat(Ops.SPECIAL, src=(), name="x"), lambda x: UOp(Ops.SPECIAL, arg=x.arg[0], src=(x.ufix(x.arg[1]),))), - (UPat(Ops.SPECIAL, src=UPat(Ops.NOOP), name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(x.arg, 0, x.src[0].arg-1, ctx[0]))), - (UPat(Ops.DEFINE_VAR, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(x.arg[0], x.arg[1], x.arg[2], ctx[0]))), - (UPat(Ops.RANGE, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(f"ridx{x.arg}", 0, x.src[0].arg-1, ctx[0]))), - (UPat(Ops.LOAD, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(f"load{ctx[1].setdefault(x, len(ctx[1]))}", x.vmin, x.vmax, ctx[0]))), - (UPat(Ops.CONST, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(z3.BoolVal if dtypes.is_bool(x.dtype) else z3.IntVal)(x.arg, ctx=ctx[0].ctx))), - (UPat(Ops.CAST, name="x"), lambda x: x.src[0]), - (UPat(GroupOp.ALU, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=z3_alu[x.op](*(s.arg for s in x.src)))), - ]) - - z3_imported = True -except (ImportError, AttributeError): z3_imported = False - -# if you have z3 installed, by default we check the bounds -IGNORE_OOB = ContextVar("IGNORE_OOB", int(not z3_imported)) - -buffer_spec = PatternMatcher([ - (UPat(Ops.UNIQUE, dtypes.void, ()), lambda: True), - (UPat(Ops.DEVICE, dtypes.void, (), name="d"), lambda d: - isinstance(d.arg, str) or (isinstance(d.arg, tuple) and all(isinstance(s, str) for s in d.arg))), - (UPat(Ops.BUFFER, src=(UPat(Ops.UNIQUE), UPat(Ops.DEVICE)), allow_any_len=True, name="buf"), - lambda buf: isinstance(buf.arg, int) and isinstance(buf.dtype, (DType, ImageDType))), - (UPat(Ops.BUFFER_VIEW, src=(UPat(Ops.BUFFER),), name="buf_view"), - lambda buf_view: isinstance(buf_view.arg, tuple) and len(buf_view.arg) == 2 and all(isinstance(arg, (int, UOp)) for arg in buf_view.arg)), - (UPat(Ops.BUFFER_VIEW, src=(UPat(Ops.MSTACK, src=UPat(Ops.BUFFER)),)), lambda: True), - # allow VIEW here. TODO: what views specifically are allowed? does this mess with gradient? - (UPat(Ops.VIEW), lambda: True), -]) - -def validate_kernel(k:UOp): - assert k.arg.ast.op in {Ops.COPY, Ops.BUFFER_VIEW, Ops.SINK}, f"must end with SINK/COPY/BUFFER_VIEW {k.arg}" - if k.arg.ast.op is Ops.SINK: assert all(s.op is Ops.STORE for s in k.arg.ast.src), f"SINK must end with STORE {k.arg.ast}" - return True - -assign_spec = PatternMatcher([ - # KERNEL can attach to an ASSIGN to describe the compute required to realize a BUFFER - (UPat(Ops.KERNEL, src=UPat((Ops.BUFFER, Ops.BUFFER_VIEW, Ops.ASSIGN, Ops.MSELECT, Ops.MSTACK)), name="k"), validate_kernel), - - # ASSIGN has a target and a value. It can also optionally depend on other assigns - (UPat(Ops.ASSIGN, name="x"), lambda x: len(x.src) >= 2 and all(s.op is Ops.ASSIGN for s in x.src[2:])), - - # MSELECT chooses one of the multi buffers - (UPat(Ops.MSELECT, name="x"), lambda x: isinstance(x.src[0].device, tuple) and x.arg < len(x.src[0].device)), - - # MSTACK combines buffers into multi - (UPat(Ops.MSTACK, name="x"), lambda x: all(isinstance(x.device, str) for x in x.src)), -]) - -# *** this is the spec of a Tensor in UOp *** - -tensor_uop_spec = buffer_spec+assign_spec+PatternMatcher([ - (UPat(GroupOp.Movement, name="mv", src=(UPat.var("x"),)), - # naturally correct - lambda mv,x: (isinstance(mv.arg, tuple) and mv.dtype == x.dtype) or - # "make things that can't be images not images" can change the buffer dtype - # this is fine as long as it's a realized buffer and base dtypes match. - ((isinstance(mv.dtype, ImageDType) or isinstance(x.dtype, ImageDType)) and x.dtype.base == mv.dtype.base and x.base.op is Ops.BUFFER)), - (UPat(Ops.VIEW, src=(UPat.var("x"),)), lambda x: x.base.op in {Ops.BUFFER, Ops.BUFFER_VIEW, Ops.ASSIGN, Ops.CONST, Ops.DEVICE}), - - # Tensor variable bindings - (UPat(Ops.BIND, dtypes.int, (UPat(Ops.DEFINE_VAR), UPat.cvar(dtype=dtypes.int)), arg=None), lambda: True), - - # Tensor const has a device and an unmasked ShapeTracker of stride 0 - # NOTE: variables in shape can cause multiple views in this ShapeTracker and other issues, see TestSymbolicJit.test_ones_sum - (UPat(Ops.CONST, src=(UPat(Ops.VIEW, name="st", src=(UPat(Ops.DEVICE),)),)), - lambda st: len(st.st.views) == 1 and all(v.mask is None for v in st.st.views)), - - # DETACH and CONTIGUOUS change how we interpret the source UOp - # CONTIGUOUS ensures the source UOp realizes - (UPat((Ops.DETACH, Ops.CONTIGUOUS, Ops.CONTIGUOUS_BACKWARD, Ops.FUSE), name="root", src=(UPat.var("x"),), arg=None), - lambda root,x: root.dtype == x.dtype), - - # COPY/ALLREDUCE/MULTI - (UPat(Ops.COPY, name="copy", src=(UPat.var("x"), UPat(Ops.DEVICE)), arg=None), lambda copy,x: copy.dtype == x.dtype), - (UPat(Ops.ALLREDUCE, name="red", src=(UPat.var("x"), UPat(Ops.DEVICE))), lambda red,x: red.dtype == x.dtype and isinstance(red.arg, Ops)), - (UPat(Ops.MULTI, name="multi"), lambda multi: all(x.dtype == multi.dtype for x in multi.src) and isinstance(multi.arg, int)), -]) - -# ***** uop type spec ***** - -def validate_index(idx:UOp, mask:UOp|None=None): - if IGNORE_OOB or isinstance(idx.dtype, ImageDType) or (sz := cast(PtrDType, idx.src[0].dtype).size) == -1: return True - # We can use UOp min/max to do a faster check, but it can give false positive since its not an exact bound and doesn't consider the mask - if 0<=idx.src[1].vmin and idx.src[1].vmax - (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)),)), lambda: True), - (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)), UPat(Ops.STORE))), lambda: True), - - # early STORE has a - (UPat(Ops.STORE, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)), UPat())), lambda: True), - - # **** new style load/store **** - - # INDEX is used in new style load/store - # INDEX takes a - (UPat(Ops.INDEX, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)), UPat()), name="idx"), validate_index), - (UPat(Ops.INDEX, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)), UPat(), UPat(dtype=dtypes.bool, name="mask")), name="idx"), validate_index), - - # LOAD takes a - (UPat(Ops.LOAD, src=(UPat((Ops.INDEX, Ops.CAST)),)), lambda: True), - (UPat(Ops.LOAD, src=(UPat((Ops.INDEX, Ops.CAST)), UPat((Ops.IF, Ops.BARRIER)))), lambda: True), - (UPat(Ops.LOAD, src=(UPat((Ops.INDEX, Ops.CAST)), UPat.var("alt")), name="ld"), lambda ld,alt: ld.dtype == alt.dtype), - - # STORE takes a - (UPat(Ops.STORE, dtype=dtypes.void, src=(UPat((Ops.INDEX, Ops.CAST)), UPat())), lambda: True), - (UPat(Ops.STORE, dtype=dtypes.void, src=(UPat((Ops.INDEX, Ops.CAST)), UPat(), UPat(dtype=dtypes.bool))), lambda: True), - (UPat(Ops.STORE, dtype=dtypes.void, src=(UPat((Ops.INDEX, Ops.CAST)), UPat(), UPat(Ops.IF))), lambda: True), - - # most ALUs have all matching dtypes, except CMPLT, CMPNE, and WHERE - (UPat(Ops.WHERE, name="w", src=(UPat(dtype=dtypes.bool), UPat.var("x"), UPat.var("y"))), lambda w,x,y: w.dtype == x.dtype == y.dtype), - (UPat((Ops.CMPLT, Ops.CMPNE), dtype=dtypes.bool, src=(UPat.var("x"), UPat.var("y"))), lambda x,y: x.dtype.base == y.dtype.base), - # and SHL/SHR, the shift distance can be an int - (UPat((Ops.SHL, Ops.SHR), src=(UPat.var("x"), UPat.var("y")), name="a"), lambda a,x,y: a.dtype == x.dtype and y.dtype in (x.dtype, dtypes.uint)), - (UPat((Ops.IDIV, Ops.MOD), name="x"), lambda x: None if dtypes.is_int(x.dtype) else False), - (UPat(GroupOp.ALU, name="x"), lambda x: all(x.dtype.base == y.dtype.base for y in x.src)), - - (UPat(Ops.ASSIGN, src=(UPat((Ops.DEFINE_ACC, Ops.DEFINE_GLOBAL)), UPat())), lambda: True), - (UPat(Ops.ENDRANGE, dtype=dtypes.void, src=(UPat(Ops.RANGE),)), lambda: True), - - # WMMA has a - (UPat(Ops.WMMA, src=(UPat(), UPat(), UPat()), name="x"), lambda x: isinstance(x.arg, tuple) and len(x.arg) == 8), - (UPat(Ops.CONTRACT, name="x"), lambda x: x.dtype.count == prod(y[1] for y in x.arg)), - (UPat(Ops.UNROLL, name="x"), lambda x: x.src[0].dtype.count == prod(y[1] for y in x.arg)), - - # if has a - (UPat(Ops.IF, dtype=dtypes.void, src=(UPat(),)), lambda: True), - (UPat(Ops.IF, dtype=dtypes.void, src=(UPat(), UPat(Ops.BARRIER))), lambda: True), - (UPat(Ops.ENDIF, dtype=dtypes.void, src=(UPat(Ops.IF),)), lambda: True), - - (UPat(Ops.REDUCE_AXIS, name="x"), lambda x: isinstance(x.arg, tuple) and len(x.arg) >= 2 and x.arg[0] in {Ops.ADD, Ops.MUL, Ops.MAX}), - (UPat(Ops.GEP, src=(UPat.var("src"),), name="gep"), lambda gep,src: gep.dtype == src.dtype.scalar()), - (UPat(Ops.VECTORIZE, name="x"), lambda x: len(x.src)>1 and len(x.src) == x.dtype.count and all(x.dtype == y.dtype.vec(len(x.src)) for y in x.src)), - (UPat((Ops.BITCAST, Ops.CAST), src=(UPat(),), name="x"), lambda x: x.arg is None), - (UPat(Ops.BARRIER, dtypes.void, src=UPat(Ops.STORE, allow_any_len=True)), lambda: True), # NOTE: all pointers must be local - (UPat(Ops.BARRIER, dtypes.void), lambda: True), # BARRIERs can also happen at the end of loops - - # NOTE: for testing, we let sinks be anything - #(UPat(Ops.SINK, src=UPat(Ops.STORE)), lambda: True), - (UPat(Ops.SINK, dtypes.void), lambda: True), - (UPat((Ops.NOOP, Ops.CUSTOMI, Ops.CUSTOM)), lambda: True), - - # PTX LOAD/STORE - (UPat((Ops.LOAD, Ops.STORE), src=(UPat(dtype=dtypes.int64),), allow_any_len=True), lambda: True), -]) - -# *** this is the UOp AST spec *** - -def verify_sink_dims(sink:UOp): - if not all_same([s.shape for s in sink.src]): return False - for dims in zip(*[x.shape for x in sink.toposort() if x.st is not None]): - if len(n_dims:={s for s in dims if resolve(s!=1)}) > 1: - print(f"# INVALID KERNEL DIMS: can only have 1 or n in each dimension: {n_dims}") - return False - -ast_spec = PatternMatcher([ - # shapes must have either 1 or n in each dimension - (UPat(Ops.SINK, src=UPat(Ops.STORE), name="sink"), verify_sink_dims), - # VIEW can only exist in the edges - (UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL),))), lambda: True), - (UPat(Ops.VIEW, name="view"), lambda view: len(view.src) == 0), - # all parent UOps must have the same shape - (UPat(GroupOp.All-{Ops.SINK}, name="root"), lambda root: all_same([x.shape for x in root.src if x.st is not None])), -]) - -# ***** uop helpers ***** - -def type_verify(uops:list[UOp], extra_spec:PatternMatcher|None=None): - check_spec = (extra_spec+spec) if extra_spec is not None else spec - for i,u in enumerate(uops): - with Context(TRACK_MATCH_STATS=0): ret = check_spec.rewrite(u) - if cast(bool|None, ret) is not True: - if DEBUG >= 3: print_uops(uops) - raise RuntimeError(f"UOp verification failed at {i} on {u.op} {u.dtype} {len(u.src)} {[x.op for x in u.src]} {u.arg}") diff --git a/tinygrad/tinygrad/uop/upat.py b/tinygrad/tinygrad/uop/upat.py deleted file mode 100644 index 090de213..00000000 --- a/tinygrad/tinygrad/uop/upat.py +++ /dev/null @@ -1,163 +0,0 @@ -from typing import Any, Callable -import itertools, inspect, functools, types -from tinygrad.helpers import partition, dedup, Context -from tinygrad.uop.ops import UPat, UPatAny, UOp, Ops, PatternMatcher, graph_rewrite, deconstruct_function - -class UPatCompileError(Exception): pass - -# **** UPat compiled **** - -def _get_clause(self:UPat, base:UOp, depth=0) -> UOp: - if isinstance(self, UPatAny): - assert len(self.src) == 1 - return UOp(Ops.AND, src=(UOp(Ops.OR, src=tuple(_get_clause(s, base, depth) for s in self.src[0])),)) - # build the and_clause for acceptance - and_clause:list[UOp] = [] - if self.op is not None: - if len(self.op) > 1: and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=tuple(int(x) for x in self.op))), arg="{0}.op in {1}")) - else: and_clause.append(UOp(Ops.CUSTOM, src=(base,), arg="{0}.op == "+str(self.op[0].value))) - if self.arg is not None: - if isinstance(self.arg, int): and_clause.append(UOp(Ops.CUSTOM, src=(base,), arg="{0}.arg == "+str(int(self.arg)))) - else: and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=self.arg)), arg="{0}.arg == {1}")) - if self.strict_length or self.required_len > 0: - and_clause.append(UOp(Ops.CUSTOM, src=(base,), arg=("len({0}.src)"+(" == " if self.strict_length else " >= ")+str(self.required_len)))) - if self.name is not None: and_clause.append(UOp(Ops.ASSIGN, src=(UOp(Ops.DEFINE_VAR, arg=self.name), base))) - if self.dtype is not None: - if len(self.dtype) > 1: - and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=tuple(self.dtype))), arg="({0}.dtype in {1} or {0}.dtype._scalar in {1})")) - else: and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=self.dtype[0])), arg="({0}.dtype == {1} or {0}.dtype._scalar == {1})")) - if self.src is not None: - # single match - if len(self.src) == 1 and isinstance(self.src[0], tuple): - and_clause += [_get_clause(s, base.gep(i), depth) for i,s in enumerate(self.src[0])] - # repeat match - elif len(self.src) == 1 and isinstance(self.src[0], itertools.repeat): - it = UOp(Ops.NOOP, arg=f"ituop{depth}") - match = _get_clause(next(self.src[0]), it, depth+1) - and_clause.append(UOp(Ops.RANGE, src=(match, it, base), arg="all([{0} for {1} in {2}.src])")) - # multi match (fork) - elif len(self.src) > 1 and all(isinstance(x, tuple) for x in self.src): - fork_cond = [UOp(Ops.AND, src=tuple([_get_clause(s, base.gep(i), depth) for i,s in enumerate(ss)])) for ss in self.src] - and_clause.append(UOp(Ops.OR, src=tuple(fork_cond))) - else: raise RuntimeError("broken") - return UOp(Ops.AND, src=tuple(and_clause)) - -# *** pattern matcher *** - -def do_process_and(a:UOp) -> UOp|None: - found = False - new_src:list[UOp] = [] - or_clause:list[UOp] = [] - - # remove any nested ANDs, extract or clauses - for x in a.src: - if x.op is Ops.AND: - new_src.extend(x.src) - found = True - elif x.op is Ops.OR: or_clause.append(x) - else: new_src.append(x) - - # too big to compile - if len(or_clause) >= 4: raise UPatCompileError("too big to compile") - - # one or clause max - if len(or_clause) > 1: - # need the product of the or clauses - or_clause = [UOp(Ops.OR, src=tuple([UOp(Ops.AND, src=x) for x in itertools.product(*[x.src for x in or_clause])]))] - found = True - - # handle assigns - assigns, new_src = partition(new_src, lambda x: x.op is Ops.ASSIGN) - if len(assigns): - if len(or_clause): - # push assigns to the top if we have an or_clause - assert len(or_clause) == 1 and all(x.op is Ops.AND for x in or_clause[0].src) - or_clause = [UOp(Ops.OR, src=tuple([x.replace(src=x.src+tuple(assigns)) for x in or_clause[0].src]))] - found = True - else: - # check for duplicate assigns - dict_assigns: dict[UOp, UOp] = {} - for a in assigns: - if a.src[0] in dict_assigns: - # duplicate assign is a compare - new_src.append(UOp(Ops.CMPNE, src=(dict_assigns[a.src[0]], a.src[1]))) - found = True - else: - dict_assigns[a.src[0]] = a.src[1] - # put the assigns back - for k,v in dict_assigns.items(): new_src.append(UOp(Ops.ASSIGN, src=(k,v))) - - # reassemble, if there's any deduping to do, do it - if len(dretand:=dedup(new_src+or_clause)) != len(new_src)+len(or_clause): found = True - return UOp(Ops.AND, src=tuple(dretand)) if found else None - -# processor -pm_proc = PatternMatcher([(UPat(Ops.AND, name="a"), do_process_and)], compiled=False) - -# renderer -def wrap(ctx, x) -> UOp: - ctx[ret:=f"a{len(ctx)}"] = x.arg - return UOp(Ops.NOOP, arg=ret) - -pm_renderer = PatternMatcher([ - (UPat(Ops.BIND, name="x"), wrap), - - # CMPNE is actually equal - (UPat(Ops.CMPNE, name="x"), lambda x: UOp(Ops.CUSTOM, src=x.src, arg="{0} is {1}")), - - # RANGE can't have OR inside it - (UPat(Ops.RANGE, src=(UPat(Ops.AND, src=UPat(Ops.NOOP), name="x"), UPat(), UPat()), name="r"), - lambda r,x: r.replace(op=Ops.CUSTOM, src=(UOp(Ops.NOOP, arg="(" + ' and '.join(y.arg for y in x.src) + ")"),)+r.src[1:])), - - (UPat(Ops.CUSTOM, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=x.arg.format(*[y.arg for y in x.src]))), - (UPat(Ops.GEP, src=UPat(Ops.NOOP, name="x"), name="g"), lambda x,g: x.replace(arg=x.arg+f".src[{g.arg[0]}]")) -], compiled=False) - -def _final_render(x:UOp, has_ctx:bool, depth=1) -> list[str]: - assert x.op is Ops.AND - and_pieces, assign_pieces = [], [] - or_pieces: list[str] = [] - for s in x.src: - if s.op is Ops.OR: - assert len(or_pieces) == 0 and len(s.src) >= 1 - for ss in s.src: or_pieces.extend(_final_render(ss, has_ctx, depth+1)) - elif s.op is Ops.ASSIGN: - assert s.src[0].op is Ops.DEFINE_VAR and s.src[1].op is Ops.NOOP - assign_pieces.append(f"{s.src[0].arg}={s.src[1].arg}") - elif s.op is Ops.NOOP: and_pieces.append(s.arg) - else: raise UPatCompileError(f"can't compile this {s}") - # if we have an or, render it - if len(or_pieces): - assert len(assign_pieces) == 0 - and_clause = ' and '.join(and_pieces) - return [f"{' '*depth}if {and_clause if len(and_clause) else 'True'}:"] + or_pieces - # if we don't, this is a final return - assign_clause = ', '.join((["ctx=ctx"] if has_ctx else [])+assign_pieces) - and_clause = ' and '.join(and_pieces + [f"(_ret:=_fxn({assign_clause})) is not None"]) - return [f"{' '*depth}if {and_clause}: return _ret"] - -def _get_code(self:UPat, has_ctx:bool): - ret = _get_clause(self, UOp(Ops.NOOP, arg="uop")) - try: - # TODO: this should be tracked in a "system" rewrite, not untracked or tracked with kernel - with Context(TRACK_MATCH_STATS=0): - ret = graph_rewrite(ret, pm_proc, name="process UPat") - dyn_lookup: dict[str, Any] = {} - out = graph_rewrite(ret, pm_renderer, ctx=dyn_lookup, name="compile UPat") - rendered = _final_render(out, has_ctx) - except UPatCompileError: - #print("FAILED", self, self.location) - return None - return '\n'.join([f"# match for {self.location}", "def compiled_match(uop, ctx):"] + rendered + [" return None"]), dyn_lookup - -@functools.cache -def upat_compile(self:UPat, fxn) -> Callable|None: - real_fxn = types.FunctionType(*deconstruct_function(fxn)) - code = _get_code(self, 'ctx' in inspect.signature(real_fxn).parameters) - if code is None: return None - code_str, dyn_lookup = code - globs = dyn_lookup.copy() - globs["_fxn"] = real_fxn - namespace: dict = {} - exec(code_str, globs, namespace) # pylint: disable=W0122 - return namespace["compiled_match"] diff --git a/tinygrad/tinygrad/viz/README b/tinygrad/tinygrad/viz/README deleted file mode 100644 index ce46d461..00000000 --- a/tinygrad/tinygrad/viz/README +++ /dev/null @@ -1,53 +0,0 @@ -viz is a replacement for: -GRAPH=1 -JITGRAPH=1 (this restricts the graph...no need if we can select the schedules) -GRAPHUOPS=1 -most uses of DEBUG >= 3 -tiny-tools - -and a viewer for: -SAVE_SCHEDULE=1 -TRACK_MATCH_STATS=2 -PROFILE=1 - -to use: -1. Run tinygrad with VIZ=1 and/or PROFILE=1 (this saves the pkls and launches the server (new process please!)) -2. That's it! - -This should be able to: -1. See all schedules (VIZ=1) -2. See all graphs and how they were rewritten (VIZ=1) -3. See generated code (VIZ=1) -4. See profile (PROFILE=1) - -bunch of dev rules: -* everything must be responsive to keyboard smashing! lag should never happen -* no requirement to use any of these libraries, but in general libraries are bad -* pure python server + browser ready JS -* serialization is very annoying! UOps are fine...others think carefully -* NOTE: we don't have to save very much - * anything pure functional can be regen by the server (stable tinygrad APIs only!) - -user story: viewing code -* tinygrad ran 3 schedules: init the model + first train step, train step, test step - * schedule 1 (123) = main.py:97 - * schedule 2 (97) = main.py:97 - * schedule 3 (10) = main.py:145 -* click "schedule 1", get list of kernels (like DEBUG=2) - * kernel 1 "E_34_34" -- 'sin' - * kernel 2 "R_4545" -* click "E_34_34" - * pre-rewritten UOp graph (step through rewrite here) - * post-rewritten UOp graph - * UOp list - * generated code - -user story: debugging scheduler -* tinygrad ran 3 schedules: init the model + first train step, train step, test step - * ... -* click "schedule 1 graph", get a graph of the schedule in UOps - * step through rewrite rules - * see how things are broken into kernels - * see why two kernels didn't fuse - -this needs to be tested, both as the server and as the frontend diff --git a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/highlight.min.js b/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/highlight.min.js deleted file mode 100644 index 5442f21b..00000000 --- a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/highlight.min.js +++ /dev/null @@ -1,1232 +0,0 @@ -/*! - Highlight.js v11.10.0 (git: 366a8bd012) - (c) 2006-2024 Josh Goebel and other contributors - License: BSD-3-Clause - */ -var hljs=function(){"use strict";function e(n){ -return n instanceof Map?n.clear=n.delete=n.set=()=>{ -throw Error("map is read-only")}:n instanceof Set&&(n.add=n.clear=n.delete=()=>{ -throw Error("set is read-only") -}),Object.freeze(n),Object.getOwnPropertyNames(n).forEach((t=>{ -const a=n[t],i=typeof a;"object"!==i&&"function"!==i||Object.isFrozen(a)||e(a) -})),n}class n{constructor(e){ -void 0===e.data&&(e.data={}),this.data=e.data,this.isMatchIgnored=!1} -ignoreMatch(){this.isMatchIgnored=!0}}function t(e){ -return e.replace(/&/g,"&").replace(//g,">").replace(/"/g,""").replace(/'/g,"'") -}function a(e,...n){const t=Object.create(null);for(const n in e)t[n]=e[n] -;return n.forEach((e=>{for(const n in e)t[n]=e[n]})),t}const i=e=>!!e.scope -;class r{constructor(e,n){ -this.buffer="",this.classPrefix=n.classPrefix,e.walk(this)}addText(e){ -this.buffer+=t(e)}openNode(e){if(!i(e))return;const n=((e,{prefix:n})=>{ -if(e.startsWith("language:"))return e.replace("language:","language-") -;if(e.includes(".")){const t=e.split(".") -;return[`${n}${t.shift()}`,...t.map(((e,n)=>`${e}${"_".repeat(n+1)}`))].join(" ") -}return`${n}${e}`})(e.scope,{prefix:this.classPrefix});this.span(n)} -closeNode(e){i(e)&&(this.buffer+="")}value(){return this.buffer}span(e){ -this.buffer+=``}}const s=(e={})=>{const n={children:[]} -;return Object.assign(n,e),n};class o{constructor(){ -this.rootNode=s(),this.stack=[this.rootNode]}get top(){ -return this.stack[this.stack.length-1]}get root(){return this.rootNode}add(e){ -this.top.children.push(e)}openNode(e){const n=s({scope:e}) -;this.add(n),this.stack.push(n)}closeNode(){ -if(this.stack.length>1)return this.stack.pop()}closeAllNodes(){ -for(;this.closeNode(););}toJSON(){return JSON.stringify(this.rootNode,null,4)} -walk(e){return this.constructor._walk(e,this.rootNode)}static _walk(e,n){ -return"string"==typeof n?e.addText(n):n.children&&(e.openNode(n), -n.children.forEach((n=>this._walk(e,n))),e.closeNode(n)),e}static _collapse(e){ -"string"!=typeof e&&e.children&&(e.children.every((e=>"string"==typeof e))?e.children=[e.children.join("")]:e.children.forEach((e=>{ -o._collapse(e)})))}}class l extends o{constructor(e){super(),this.options=e} -addText(e){""!==e&&this.add(e)}startScope(e){this.openNode(e)}endScope(){ -this.closeNode()}__addSublanguage(e,n){const t=e.root -;n&&(t.scope="language:"+n),this.add(t)}toHTML(){ -return new r(this,this.options).value()}finalize(){ -return this.closeAllNodes(),!0}}function c(e){ -return e?"string"==typeof e?e:e.source:null}function d(e){return b("(?=",e,")")} -function g(e){return b("(?:",e,")*")}function u(e){return b("(?:",e,")?")} -function b(...e){return e.map((e=>c(e))).join("")}function m(...e){const n=(e=>{ -const n=e[e.length-1] -;return"object"==typeof n&&n.constructor===Object?(e.splice(e.length-1,1),n):{} -})(e);return"("+(n.capture?"":"?:")+e.map((e=>c(e))).join("|")+")"} -function p(e){return RegExp(e.toString()+"|").exec("").length-1} -const _=/\[(?:[^\\\]]|\\.)*\]|\(\??|\\([1-9][0-9]*)|\\./ -;function h(e,{joinWith:n}){let t=0;return e.map((e=>{t+=1;const n=t -;let a=c(e),i="";for(;a.length>0;){const e=_.exec(a);if(!e){i+=a;break} -i+=a.substring(0,e.index), -a=a.substring(e.index+e[0].length),"\\"===e[0][0]&&e[1]?i+="\\"+(Number(e[1])+n):(i+=e[0], -"("===e[0]&&t++)}return i})).map((e=>`(${e})`)).join(n)} -const f="[a-zA-Z]\\w*",E="[a-zA-Z_]\\w*",y="\\b\\d+(\\.\\d+)?",w="(-?)(\\b0[xX][a-fA-F0-9]+|(\\b\\d+(\\.\\d*)?|\\.\\d+)([eE][-+]?\\d+)?)",N="\\b(0b[01]+)",v={ -begin:"\\\\[\\s\\S]",relevance:0},k={scope:"string",begin:"'",end:"'", -illegal:"\\n",contains:[v]},x={scope:"string",begin:'"',end:'"',illegal:"\\n", -contains:[v]},O=(e,n,t={})=>{const i=a({scope:"comment",begin:e,end:n, -contains:[]},t);i.contains.push({scope:"doctag", -begin:"[ ]*(?=(TODO|FIXME|NOTE|BUG|OPTIMIZE|HACK|XXX):)", -end:/(TODO|FIXME|NOTE|BUG|OPTIMIZE|HACK|XXX):/,excludeBegin:!0,relevance:0}) -;const r=m("I","a","is","so","us","to","at","if","in","it","on",/[A-Za-z]+['](d|ve|re|ll|t|s|n)/,/[A-Za-z]+[-][a-z]+/,/[A-Za-z][a-z]{2,}/) -;return i.contains.push({begin:b(/[ ]+/,"(",r,/[.]?[:]?([.][ ]|[ ])/,"){3}")}),i -},M=O("//","$"),A=O("/\\*","\\*/"),S=O("#","$");var C=Object.freeze({ -__proto__:null,APOS_STRING_MODE:k,BACKSLASH_ESCAPE:v,BINARY_NUMBER_MODE:{ -scope:"number",begin:N,relevance:0},BINARY_NUMBER_RE:N,COMMENT:O, -C_BLOCK_COMMENT_MODE:A,C_LINE_COMMENT_MODE:M,C_NUMBER_MODE:{scope:"number", -begin:w,relevance:0},C_NUMBER_RE:w,END_SAME_AS_BEGIN:e=>Object.assign(e,{ -"on:begin":(e,n)=>{n.data._beginMatch=e[1]},"on:end":(e,n)=>{ -n.data._beginMatch!==e[1]&&n.ignoreMatch()}}),HASH_COMMENT_MODE:S,IDENT_RE:f, -MATCH_NOTHING_RE:/\b\B/,METHOD_GUARD:{begin:"\\.\\s*"+E,relevance:0}, -NUMBER_MODE:{scope:"number",begin:y,relevance:0},NUMBER_RE:y, -PHRASAL_WORDS_MODE:{ -begin:/\b(a|an|the|are|I'm|isn't|don't|doesn't|won't|but|just|should|pretty|simply|enough|gonna|going|wtf|so|such|will|you|your|they|like|more)\b/ -},QUOTE_STRING_MODE:x,REGEXP_MODE:{scope:"regexp",begin:/\/(?=[^/\n]*\/)/, -end:/\/[gimuy]*/,contains:[v,{begin:/\[/,end:/\]/,relevance:0,contains:[v]}]}, -RE_STARTERS_RE:"!|!=|!==|%|%=|&|&&|&=|\\*|\\*=|\\+|\\+=|,|-|-=|/=|/|:|;|<<|<<=|<=|<|===|==|=|>>>=|>>=|>=|>>>|>>|>|\\?|\\[|\\{|\\(|\\^|\\^=|\\||\\|=|\\|\\||~", -SHEBANG:(e={})=>{const n=/^#![ ]*\// -;return e.binary&&(e.begin=b(n,/.*\b/,e.binary,/\b.*/)),a({scope:"meta",begin:n, -end:/$/,relevance:0,"on:begin":(e,n)=>{0!==e.index&&n.ignoreMatch()}},e)}, -TITLE_MODE:{scope:"title",begin:f,relevance:0},UNDERSCORE_IDENT_RE:E, -UNDERSCORE_TITLE_MODE:{scope:"title",begin:E,relevance:0}});function T(e,n){ -"."===e.input[e.index-1]&&n.ignoreMatch()}function R(e,n){ -void 0!==e.className&&(e.scope=e.className,delete e.className)}function D(e,n){ -n&&e.beginKeywords&&(e.begin="\\b("+e.beginKeywords.split(" ").join("|")+")(?!\\.)(?=\\b|\\s)", -e.__beforeBegin=T,e.keywords=e.keywords||e.beginKeywords,delete e.beginKeywords, -void 0===e.relevance&&(e.relevance=0))}function I(e,n){ -Array.isArray(e.illegal)&&(e.illegal=m(...e.illegal))}function L(e,n){ -if(e.match){ -if(e.begin||e.end)throw Error("begin & end are not supported with match") -;e.begin=e.match,delete e.match}}function B(e,n){ -void 0===e.relevance&&(e.relevance=1)}const $=(e,n)=>{if(!e.beforeMatch)return -;if(e.starts)throw Error("beforeMatch cannot be used with starts") -;const t=Object.assign({},e);Object.keys(e).forEach((n=>{delete e[n] -})),e.keywords=t.keywords,e.begin=b(t.beforeMatch,d(t.begin)),e.starts={ -relevance:0,contains:[Object.assign(t,{endsParent:!0})] -},e.relevance=0,delete t.beforeMatch -},F=["of","and","for","in","not","or","if","then","parent","list","value"],z="keyword" -;function j(e,n,t=z){const a=Object.create(null) -;return"string"==typeof e?i(t,e.split(" ")):Array.isArray(e)?i(t,e):Object.keys(e).forEach((t=>{ -Object.assign(a,j(e[t],n,t))})),a;function i(e,t){ -n&&(t=t.map((e=>e.toLowerCase()))),t.forEach((n=>{const t=n.split("|") -;a[t[0]]=[e,U(t[0],t[1])]}))}}function U(e,n){ -return n?Number(n):(e=>F.includes(e.toLowerCase()))(e)?0:1}const P={},K=e=>{ -console.error(e)},q=(e,...n)=>{console.log("WARN: "+e,...n)},H=(e,n)=>{ -P[`${e}/${n}`]||(console.log(`Deprecated as of ${e}. ${n}`),P[`${e}/${n}`]=!0) -},G=Error();function Z(e,n,{key:t}){let a=0;const i=e[t],r={},s={} -;for(let e=1;e<=n.length;e++)s[e+a]=i[e],r[e+a]=!0,a+=p(n[e-1]) -;e[t]=s,e[t]._emit=r,e[t]._multi=!0}function W(e){(e=>{ -e.scope&&"object"==typeof e.scope&&null!==e.scope&&(e.beginScope=e.scope, -delete e.scope)})(e),"string"==typeof e.beginScope&&(e.beginScope={ -_wrap:e.beginScope}),"string"==typeof e.endScope&&(e.endScope={_wrap:e.endScope -}),(e=>{if(Array.isArray(e.begin)){ -if(e.skip||e.excludeBegin||e.returnBegin)throw K("skip, excludeBegin, returnBegin not compatible with beginScope: {}"), -G -;if("object"!=typeof e.beginScope||null===e.beginScope)throw K("beginScope must be object"), -G;Z(e,e.begin,{key:"beginScope"}),e.begin=h(e.begin,{joinWith:""})}})(e),(e=>{ -if(Array.isArray(e.end)){ -if(e.skip||e.excludeEnd||e.returnEnd)throw K("skip, excludeEnd, returnEnd not compatible with endScope: {}"), -G -;if("object"!=typeof e.endScope||null===e.endScope)throw K("endScope must be object"), -G;Z(e,e.end,{key:"endScope"}),e.end=h(e.end,{joinWith:""})}})(e)}function Q(e){ -function n(n,t){ -return RegExp(c(n),"m"+(e.case_insensitive?"i":"")+(e.unicodeRegex?"u":"")+(t?"g":"")) -}class t{constructor(){ -this.matchIndexes={},this.regexes=[],this.matchAt=1,this.position=0} -addRule(e,n){ -n.position=this.position++,this.matchIndexes[this.matchAt]=n,this.regexes.push([n,e]), -this.matchAt+=p(e)+1}compile(){0===this.regexes.length&&(this.exec=()=>null) -;const e=this.regexes.map((e=>e[1]));this.matcherRe=n(h(e,{joinWith:"|" -}),!0),this.lastIndex=0}exec(e){this.matcherRe.lastIndex=this.lastIndex -;const n=this.matcherRe.exec(e);if(!n)return null -;const t=n.findIndex(((e,n)=>n>0&&void 0!==e)),a=this.matchIndexes[t] -;return n.splice(0,t),Object.assign(n,a)}}class i{constructor(){ -this.rules=[],this.multiRegexes=[], -this.count=0,this.lastIndex=0,this.regexIndex=0}getMatcher(e){ -if(this.multiRegexes[e])return this.multiRegexes[e];const n=new t -;return this.rules.slice(e).forEach((([e,t])=>n.addRule(e,t))), -n.compile(),this.multiRegexes[e]=n,n}resumingScanAtSamePosition(){ -return 0!==this.regexIndex}considerAll(){this.regexIndex=0}addRule(e,n){ -this.rules.push([e,n]),"begin"===n.type&&this.count++}exec(e){ -const n=this.getMatcher(this.regexIndex);n.lastIndex=this.lastIndex -;let t=n.exec(e) -;if(this.resumingScanAtSamePosition())if(t&&t.index===this.lastIndex);else{ -const n=this.getMatcher(0);n.lastIndex=this.lastIndex+1,t=n.exec(e)} -return t&&(this.regexIndex+=t.position+1, -this.regexIndex===this.count&&this.considerAll()),t}} -if(e.compilerExtensions||(e.compilerExtensions=[]), -e.contains&&e.contains.includes("self"))throw Error("ERR: contains `self` is not supported at the top-level of a language. See documentation.") -;return e.classNameAliases=a(e.classNameAliases||{}),function t(r,s){const o=r -;if(r.isCompiled)return o -;[R,L,W,$].forEach((e=>e(r,s))),e.compilerExtensions.forEach((e=>e(r,s))), -r.__beforeBegin=null,[D,I,B].forEach((e=>e(r,s))),r.isCompiled=!0;let l=null -;return"object"==typeof r.keywords&&r.keywords.$pattern&&(r.keywords=Object.assign({},r.keywords), -l=r.keywords.$pattern, -delete r.keywords.$pattern),l=l||/\w+/,r.keywords&&(r.keywords=j(r.keywords,e.case_insensitive)), -o.keywordPatternRe=n(l,!0), -s&&(r.begin||(r.begin=/\B|\b/),o.beginRe=n(o.begin),r.end||r.endsWithParent||(r.end=/\B|\b/), -r.end&&(o.endRe=n(o.end)), -o.terminatorEnd=c(o.end)||"",r.endsWithParent&&s.terminatorEnd&&(o.terminatorEnd+=(r.end?"|":"")+s.terminatorEnd)), -r.illegal&&(o.illegalRe=n(r.illegal)), -r.contains||(r.contains=[]),r.contains=[].concat(...r.contains.map((e=>(e=>(e.variants&&!e.cachedVariants&&(e.cachedVariants=e.variants.map((n=>a(e,{ -variants:null},n)))),e.cachedVariants?e.cachedVariants:X(e)?a(e,{ -starts:e.starts?a(e.starts):null -}):Object.isFrozen(e)?a(e):e))("self"===e?r:e)))),r.contains.forEach((e=>{t(e,o) -})),r.starts&&t(r.starts,s),o.matcher=(e=>{const n=new i -;return e.contains.forEach((e=>n.addRule(e.begin,{rule:e,type:"begin" -}))),e.terminatorEnd&&n.addRule(e.terminatorEnd,{type:"end" -}),e.illegal&&n.addRule(e.illegal,{type:"illegal"}),n})(o),o}(e)}function X(e){ -return!!e&&(e.endsWithParent||X(e.starts))}class V extends Error{ -constructor(e,n){super(e),this.name="HTMLInjectionError",this.html=n}} -const J=t,Y=a,ee=Symbol("nomatch"),ne=t=>{ -const a=Object.create(null),i=Object.create(null),r=[];let s=!0 -;const o="Could not find the language '{}', did you forget to load/include a language module?",c={ -disableAutodetect:!0,name:"Plain text",contains:[]};let p={ -ignoreUnescapedHTML:!1,throwUnescapedHTML:!1,noHighlightRe:/^(no-?highlight)$/i, -languageDetectRe:/\blang(?:uage)?-([\w-]+)\b/i,classPrefix:"hljs-", -cssSelector:"pre code",languages:null,__emitter:l};function _(e){ -return p.noHighlightRe.test(e)}function h(e,n,t){let a="",i="" -;"object"==typeof n?(a=e, -t=n.ignoreIllegals,i=n.language):(H("10.7.0","highlight(lang, code, ...args) has been deprecated."), -H("10.7.0","Please use highlight(code, options) instead.\nhttps://github.com/highlightjs/highlight.js/issues/2277"), -i=e,a=n),void 0===t&&(t=!0);const r={code:a,language:i};O("before:highlight",r) -;const s=r.result?r.result:f(r.language,r.code,t) -;return s.code=r.code,O("after:highlight",s),s}function f(e,t,i,r){ -const l=Object.create(null);function c(){if(!O.keywords)return void A.addText(S) -;let e=0;O.keywordPatternRe.lastIndex=0;let n=O.keywordPatternRe.exec(S),t="" -;for(;n;){t+=S.substring(e,n.index) -;const i=N.case_insensitive?n[0].toLowerCase():n[0],r=(a=i,O.keywords[a]);if(r){ -const[e,a]=r -;if(A.addText(t),t="",l[i]=(l[i]||0)+1,l[i]<=7&&(C+=a),e.startsWith("_"))t+=n[0];else{ -const t=N.classNameAliases[e]||e;g(n[0],t)}}else t+=n[0] -;e=O.keywordPatternRe.lastIndex,n=O.keywordPatternRe.exec(S)}var a -;t+=S.substring(e),A.addText(t)}function d(){null!=O.subLanguage?(()=>{ -if(""===S)return;let e=null;if("string"==typeof O.subLanguage){ -if(!a[O.subLanguage])return void A.addText(S) -;e=f(O.subLanguage,S,!0,M[O.subLanguage]),M[O.subLanguage]=e._top -}else e=E(S,O.subLanguage.length?O.subLanguage:null) -;O.relevance>0&&(C+=e.relevance),A.__addSublanguage(e._emitter,e.language) -})():c(),S=""}function g(e,n){ -""!==e&&(A.startScope(n),A.addText(e),A.endScope())}function u(e,n){let t=1 -;const a=n.length-1;for(;t<=a;){if(!e._emit[t]){t++;continue} -const a=N.classNameAliases[e[t]]||e[t],i=n[t];a?g(i,a):(S=i,c(),S=""),t++}} -function b(e,n){ -return e.scope&&"string"==typeof e.scope&&A.openNode(N.classNameAliases[e.scope]||e.scope), -e.beginScope&&(e.beginScope._wrap?(g(S,N.classNameAliases[e.beginScope._wrap]||e.beginScope._wrap), -S=""):e.beginScope._multi&&(u(e.beginScope,n),S="")),O=Object.create(e,{parent:{ -value:O}}),O}function m(e,t,a){let i=((e,n)=>{const t=e&&e.exec(n) -;return t&&0===t.index})(e.endRe,a);if(i){if(e["on:end"]){const a=new n(e) -;e["on:end"](t,a),a.isMatchIgnored&&(i=!1)}if(i){ -for(;e.endsParent&&e.parent;)e=e.parent;return e}} -if(e.endsWithParent)return m(e.parent,t,a)}function _(e){ -return 0===O.matcher.regexIndex?(S+=e[0],1):(D=!0,0)}function h(e){ -const n=e[0],a=t.substring(e.index),i=m(O,e,a);if(!i)return ee;const r=O -;O.endScope&&O.endScope._wrap?(d(), -g(n,O.endScope._wrap)):O.endScope&&O.endScope._multi?(d(), -u(O.endScope,e)):r.skip?S+=n:(r.returnEnd||r.excludeEnd||(S+=n), -d(),r.excludeEnd&&(S=n));do{ -O.scope&&A.closeNode(),O.skip||O.subLanguage||(C+=O.relevance),O=O.parent -}while(O!==i.parent);return i.starts&&b(i.starts,e),r.returnEnd?0:n.length} -let y={};function w(a,r){const o=r&&r[0];if(S+=a,null==o)return d(),0 -;if("begin"===y.type&&"end"===r.type&&y.index===r.index&&""===o){ -if(S+=t.slice(r.index,r.index+1),!s){const n=Error(`0 width match regex (${e})`) -;throw n.languageName=e,n.badRule=y.rule,n}return 1} -if(y=r,"begin"===r.type)return(e=>{ -const t=e[0],a=e.rule,i=new n(a),r=[a.__beforeBegin,a["on:begin"]] -;for(const n of r)if(n&&(n(e,i),i.isMatchIgnored))return _(t) -;return a.skip?S+=t:(a.excludeBegin&&(S+=t), -d(),a.returnBegin||a.excludeBegin||(S=t)),b(a,e),a.returnBegin?0:t.length})(r) -;if("illegal"===r.type&&!i){ -const e=Error('Illegal lexeme "'+o+'" for mode "'+(O.scope||"")+'"') -;throw e.mode=O,e}if("end"===r.type){const e=h(r);if(e!==ee)return e} -if("illegal"===r.type&&""===o)return 1 -;if(R>1e5&&R>3*r.index)throw Error("potential infinite loop, way more iterations than matches") -;return S+=o,o.length}const N=v(e) -;if(!N)throw K(o.replace("{}",e)),Error('Unknown language: "'+e+'"') -;const k=Q(N);let x="",O=r||k;const M={},A=new p.__emitter(p);(()=>{const e=[] -;for(let n=O;n!==N;n=n.parent)n.scope&&e.unshift(n.scope) -;e.forEach((e=>A.openNode(e)))})();let S="",C=0,T=0,R=0,D=!1;try{ -if(N.__emitTokens)N.__emitTokens(t,A);else{for(O.matcher.considerAll();;){ -R++,D?D=!1:O.matcher.considerAll(),O.matcher.lastIndex=T -;const e=O.matcher.exec(t);if(!e)break;const n=w(t.substring(T,e.index),e) -;T=e.index+n}w(t.substring(T))}return A.finalize(),x=A.toHTML(),{language:e, -value:x,relevance:C,illegal:!1,_emitter:A,_top:O}}catch(n){ -if(n.message&&n.message.includes("Illegal"))return{language:e,value:J(t), -illegal:!0,relevance:0,_illegalBy:{message:n.message,index:T, -context:t.slice(T-100,T+100),mode:n.mode,resultSoFar:x},_emitter:A};if(s)return{ -language:e,value:J(t),illegal:!1,relevance:0,errorRaised:n,_emitter:A,_top:O} -;throw n}}function E(e,n){n=n||p.languages||Object.keys(a);const t=(e=>{ -const n={value:J(e),illegal:!1,relevance:0,_top:c,_emitter:new p.__emitter(p)} -;return n._emitter.addText(e),n})(e),i=n.filter(v).filter(x).map((n=>f(n,e,!1))) -;i.unshift(t);const r=i.sort(((e,n)=>{ -if(e.relevance!==n.relevance)return n.relevance-e.relevance -;if(e.language&&n.language){if(v(e.language).supersetOf===n.language)return 1 -;if(v(n.language).supersetOf===e.language)return-1}return 0})),[s,o]=r,l=s -;return l.secondBest=o,l}function y(e){let n=null;const t=(e=>{ -let n=e.className+" ";n+=e.parentNode?e.parentNode.className:"" -;const t=p.languageDetectRe.exec(n);if(t){const n=v(t[1]) -;return n||(q(o.replace("{}",t[1])), -q("Falling back to no-highlight mode for this block.",e)),n?t[1]:"no-highlight"} -return n.split(/\s+/).find((e=>_(e)||v(e)))})(e);if(_(t))return -;if(O("before:highlightElement",{el:e,language:t -}),e.dataset.highlighted)return void console.log("Element previously highlighted. To highlight again, first unset `dataset.highlighted`.",e) -;if(e.children.length>0&&(p.ignoreUnescapedHTML||(console.warn("One of your code blocks includes unescaped HTML. This is a potentially serious security risk."), -console.warn("https://github.com/highlightjs/highlight.js/wiki/security"), -console.warn("The element with unescaped HTML:"), -console.warn(e)),p.throwUnescapedHTML))throw new V("One of your code blocks includes unescaped HTML.",e.innerHTML) -;n=e;const a=n.textContent,r=t?h(a,{language:t,ignoreIllegals:!0}):E(a) -;e.innerHTML=r.value,e.dataset.highlighted="yes",((e,n,t)=>{const a=n&&i[n]||t -;e.classList.add("hljs"),e.classList.add("language-"+a) -})(e,t,r.language),e.result={language:r.language,re:r.relevance, -relevance:r.relevance},r.secondBest&&(e.secondBest={ -language:r.secondBest.language,relevance:r.secondBest.relevance -}),O("after:highlightElement",{el:e,result:r,text:a})}let w=!1;function N(){ -"loading"!==document.readyState?document.querySelectorAll(p.cssSelector).forEach(y):w=!0 -}function v(e){return e=(e||"").toLowerCase(),a[e]||a[i[e]]} -function k(e,{languageName:n}){"string"==typeof e&&(e=[e]),e.forEach((e=>{ -i[e.toLowerCase()]=n}))}function x(e){const n=v(e) -;return n&&!n.disableAutodetect}function O(e,n){const t=e;r.forEach((e=>{ -e[t]&&e[t](n)}))} -"undefined"!=typeof window&&window.addEventListener&&window.addEventListener("DOMContentLoaded",(()=>{ -w&&N()}),!1),Object.assign(t,{highlight:h,highlightAuto:E,highlightAll:N, -highlightElement:y, -highlightBlock:e=>(H("10.7.0","highlightBlock will be removed entirely in v12.0"), -H("10.7.0","Please use highlightElement now."),y(e)),configure:e=>{p=Y(p,e)}, -initHighlighting:()=>{ -N(),H("10.6.0","initHighlighting() deprecated. Use highlightAll() now.")}, -initHighlightingOnLoad:()=>{ -N(),H("10.6.0","initHighlightingOnLoad() deprecated. Use highlightAll() now.") -},registerLanguage:(e,n)=>{let i=null;try{i=n(t)}catch(n){ -if(K("Language definition for '{}' could not be registered.".replace("{}",e)), -!s)throw n;K(n),i=c} -i.name||(i.name=e),a[e]=i,i.rawDefinition=n.bind(null,t),i.aliases&&k(i.aliases,{ -languageName:e})},unregisterLanguage:e=>{delete a[e] -;for(const n of Object.keys(i))i[n]===e&&delete i[n]}, -listLanguages:()=>Object.keys(a),getLanguage:v,registerAliases:k, -autoDetection:x,inherit:Y,addPlugin:e=>{(e=>{ -e["before:highlightBlock"]&&!e["before:highlightElement"]&&(e["before:highlightElement"]=n=>{ -e["before:highlightBlock"](Object.assign({block:n.el},n)) -}),e["after:highlightBlock"]&&!e["after:highlightElement"]&&(e["after:highlightElement"]=n=>{ -e["after:highlightBlock"](Object.assign({block:n.el},n))})})(e),r.push(e)}, -removePlugin:e=>{const n=r.indexOf(e);-1!==n&&r.splice(n,1)}}),t.debugMode=()=>{ -s=!1},t.safeMode=()=>{s=!0},t.versionString="11.10.0",t.regex={concat:b, -lookahead:d,either:m,optional:u,anyNumberOfTimes:g} -;for(const n in C)"object"==typeof C[n]&&e(C[n]);return Object.assign(t,C),t -},te=ne({});te.newInstance=()=>ne({});const ae=e=>({IMPORTANT:{scope:"meta", -begin:"!important"},BLOCK_COMMENT:e.C_BLOCK_COMMENT_MODE,HEXCOLOR:{ -scope:"number",begin:/#(([0-9a-fA-F]{3,4})|(([0-9a-fA-F]{2}){3,4}))\b/}, -FUNCTION_DISPATCH:{className:"built_in",begin:/[\w-]+(?=\()/}, -ATTRIBUTE_SELECTOR_MODE:{scope:"selector-attr",begin:/\[/,end:/\]/,illegal:"$", -contains:[e.APOS_STRING_MODE,e.QUOTE_STRING_MODE]},CSS_NUMBER_MODE:{ -scope:"number", -begin:e.NUMBER_RE+"(%|em|ex|ch|rem|vw|vh|vmin|vmax|cm|mm|in|pt|pc|px|deg|grad|rad|turn|s|ms|Hz|kHz|dpi|dpcm|dppx)?", -relevance:0},CSS_VARIABLE:{className:"attr",begin:/--[A-Za-z_][A-Za-z0-9_-]*/} -}),ie=["a","abbr","address","article","aside","audio","b","blockquote","body","button","canvas","caption","cite","code","dd","del","details","dfn","div","dl","dt","em","fieldset","figcaption","figure","footer","form","h1","h2","h3","h4","h5","h6","header","hgroup","html","i","iframe","img","input","ins","kbd","label","legend","li","main","mark","menu","nav","object","ol","optgroup","option","p","picture","q","quote","samp","section","select","source","span","strong","summary","sup","table","tbody","td","textarea","tfoot","th","thead","time","tr","ul","var","video","defs","g","marker","mask","pattern","svg","switch","symbol","feBlend","feColorMatrix","feComponentTransfer","feComposite","feConvolveMatrix","feDiffuseLighting","feDisplacementMap","feFlood","feGaussianBlur","feImage","feMerge","feMorphology","feOffset","feSpecularLighting","feTile","feTurbulence","linearGradient","radialGradient","stop","circle","ellipse","image","line","path","polygon","polyline","rect","text","use","textPath","tspan","foreignObject","clipPath"],re=["any-hover","any-pointer","aspect-ratio","color","color-gamut","color-index","device-aspect-ratio","device-height","device-width","display-mode","forced-colors","grid","height","hover","inverted-colors","monochrome","orientation","overflow-block","overflow-inline","pointer","prefers-color-scheme","prefers-contrast","prefers-reduced-motion","prefers-reduced-transparency","resolution","scan","scripting","update","width","min-width","max-width","min-height","max-height"].sort().reverse(),se=["active","any-link","blank","checked","current","default","defined","dir","disabled","drop","empty","enabled","first","first-child","first-of-type","fullscreen","future","focus","focus-visible","focus-within","has","host","host-context","hover","indeterminate","in-range","invalid","is","lang","last-child","last-of-type","left","link","local-link","not","nth-child","nth-col","nth-last-child","nth-last-col","nth-last-of-type","nth-of-type","only-child","only-of-type","optional","out-of-range","past","placeholder-shown","read-only","read-write","required","right","root","scope","target","target-within","user-invalid","valid","visited","where"].sort().reverse(),oe=["after","backdrop","before","cue","cue-region","first-letter","first-line","grammar-error","marker","part","placeholder","selection","slotted","spelling-error"].sort().reverse(),le=["accent-color","align-content","align-items","align-self","alignment-baseline","all","animation","animation-delay","animation-direction","animation-duration","animation-fill-mode","animation-iteration-count","animation-name","animation-play-state","animation-timing-function","appearance","backface-visibility","background","background-attachment","background-blend-mode","background-clip","background-color","background-image","background-origin","background-position","background-repeat","background-size","baseline-shift","block-size","border","border-block","border-block-color","border-block-end","border-block-end-color","border-block-end-style","border-block-end-width","border-block-start","border-block-start-color","border-block-start-style","border-block-start-width","border-block-style","border-block-width","border-bottom","border-bottom-color","border-bottom-left-radius","border-bottom-right-radius","border-bottom-style","border-bottom-width","border-collapse","border-color","border-image","border-image-outset","border-image-repeat","border-image-slice","border-image-source","border-image-width","border-inline","border-inline-color","border-inline-end","border-inline-end-color","border-inline-end-style","border-inline-end-width","border-inline-start","border-inline-start-color","border-inline-start-style","border-inline-start-width","border-inline-style","border-inline-width","border-left","border-left-color","border-left-style","border-left-width","border-radius","border-right","border-end-end-radius","border-end-start-radius","border-right-color","border-right-style","border-right-width","border-spacing","border-start-end-radius","border-start-start-radius","border-style","border-top","border-top-color","border-top-left-radius","border-top-right-radius","border-top-style","border-top-width","border-width","bottom","box-decoration-break","box-shadow","box-sizing","break-after","break-before","break-inside","cx","cy","caption-side","caret-color","clear","clip","clip-path","clip-rule","color","color-interpolation","color-interpolation-filters","color-profile","color-rendering","color-scheme","column-count","column-fill","column-gap","column-rule","column-rule-color","column-rule-style","column-rule-width","column-span","column-width","columns","contain","content","content-visibility","counter-increment","counter-reset","cue","cue-after","cue-before","cursor","direction","display","dominant-baseline","empty-cells","enable-background","fill","fill-opacity","fill-rule","filter","flex","flex-basis","flex-direction","flex-flow","flex-grow","flex-shrink","flex-wrap","float","flow","flood-color","flood-opacity","font","font-display","font-family","font-feature-settings","font-kerning","font-language-override","font-size","font-size-adjust","font-smoothing","font-stretch","font-style","font-synthesis","font-variant","font-variant-caps","font-variant-east-asian","font-variant-ligatures","font-variant-numeric","font-variant-position","font-variation-settings","font-weight","gap","glyph-orientation-horizontal","glyph-orientation-vertical","grid","grid-area","grid-auto-columns","grid-auto-flow","grid-auto-rows","grid-column","grid-column-end","grid-column-start","grid-gap","grid-row","grid-row-end","grid-row-start","grid-template","grid-template-areas","grid-template-columns","grid-template-rows","hanging-punctuation","height","hyphens","icon","image-orientation","image-rendering","image-resolution","ime-mode","inline-size","inset","inset-block","inset-block-end","inset-block-start","inset-inline","inset-inline-end","inset-inline-start","isolation","kerning","justify-content","justify-items","justify-self","left","letter-spacing","lighting-color","line-break","line-height","list-style","list-style-image","list-style-position","list-style-type","marker","marker-end","marker-mid","marker-start","mask","margin","margin-block","margin-block-end","margin-block-start","margin-bottom","margin-inline","margin-inline-end","margin-inline-start","margin-left","margin-right","margin-top","marks","mask","mask-border","mask-border-mode","mask-border-outset","mask-border-repeat","mask-border-slice","mask-border-source","mask-border-width","mask-clip","mask-composite","mask-image","mask-mode","mask-origin","mask-position","mask-repeat","mask-size","mask-type","max-block-size","max-height","max-inline-size","max-width","min-block-size","min-height","min-inline-size","min-width","mix-blend-mode","nav-down","nav-index","nav-left","nav-right","nav-up","none","normal","object-fit","object-position","opacity","order","orphans","outline","outline-color","outline-offset","outline-style","outline-width","overflow","overflow-wrap","overflow-x","overflow-y","padding","padding-block","padding-block-end","padding-block-start","padding-bottom","padding-inline","padding-inline-end","padding-inline-start","padding-left","padding-right","padding-top","page-break-after","page-break-before","page-break-inside","pause","pause-after","pause-before","perspective","perspective-origin","pointer-events","position","quotes","r","resize","rest","rest-after","rest-before","right","rotate","row-gap","scale","scroll-margin","scroll-margin-block","scroll-margin-block-end","scroll-margin-block-start","scroll-margin-bottom","scroll-margin-inline","scroll-margin-inline-end","scroll-margin-inline-start","scroll-margin-left","scroll-margin-right","scroll-margin-top","scroll-padding","scroll-padding-block","scroll-padding-block-end","scroll-padding-block-start","scroll-padding-bottom","scroll-padding-inline","scroll-padding-inline-end","scroll-padding-inline-start","scroll-padding-left","scroll-padding-right","scroll-padding-top","scroll-snap-align","scroll-snap-stop","scroll-snap-type","scrollbar-color","scrollbar-gutter","scrollbar-width","shape-image-threshold","shape-margin","shape-outside","shape-rendering","stop-color","stop-opacity","stroke","stroke-dasharray","stroke-dashoffset","stroke-linecap","stroke-linejoin","stroke-miterlimit","stroke-opacity","stroke-width","speak","speak-as","src","tab-size","table-layout","text-anchor","text-align","text-align-all","text-align-last","text-combine-upright","text-decoration","text-decoration-color","text-decoration-line","text-decoration-skip-ink","text-decoration-style","text-decoration-thickness","text-emphasis","text-emphasis-color","text-emphasis-position","text-emphasis-style","text-indent","text-justify","text-orientation","text-overflow","text-rendering","text-shadow","text-transform","text-underline-offset","text-underline-position","top","transform","transform-box","transform-origin","transform-style","transition","transition-delay","transition-duration","transition-property","transition-timing-function","translate","unicode-bidi","vector-effect","vertical-align","visibility","voice-balance","voice-duration","voice-family","voice-pitch","voice-range","voice-rate","voice-stress","voice-volume","white-space","widows","width","will-change","word-break","word-spacing","word-wrap","writing-mode","x","y","z-index"].sort().reverse(),ce=se.concat(oe).sort().reverse() -;var de="[0-9](_*[0-9])*",ge=`\\.(${de})`,ue="[0-9a-fA-F](_*[0-9a-fA-F])*",be={ -className:"number",variants:[{ -begin:`(\\b(${de})((${ge})|\\.)?|(${ge}))[eE][+-]?(${de})[fFdD]?\\b`},{ -begin:`\\b(${de})((${ge})[fFdD]?\\b|\\.([fFdD]\\b)?)`},{ -begin:`(${ge})[fFdD]?\\b`},{begin:`\\b(${de})[fFdD]\\b`},{ -begin:`\\b0[xX]((${ue})\\.?|(${ue})?\\.(${ue}))[pP][+-]?(${de})[fFdD]?\\b`},{ -begin:"\\b(0|[1-9](_*[0-9])*)[lL]?\\b"},{begin:`\\b0[xX](${ue})[lL]?\\b`},{ -begin:"\\b0(_*[0-7])*[lL]?\\b"},{begin:"\\b0[bB][01](_*[01])*[lL]?\\b"}], -relevance:0};function me(e,n,t){return-1===t?"":e.replace(n,(a=>me(e,n,t-1)))} -const pe="[A-Za-z$_][0-9A-Za-z$_]*",_e=["as","in","of","if","for","while","finally","var","new","function","do","return","void","else","break","catch","instanceof","with","throw","case","default","try","switch","continue","typeof","delete","let","yield","const","class","debugger","async","await","static","import","from","export","extends"],he=["true","false","null","undefined","NaN","Infinity"],fe=["Object","Function","Boolean","Symbol","Math","Date","Number","BigInt","String","RegExp","Array","Float32Array","Float64Array","Int8Array","Uint8Array","Uint8ClampedArray","Int16Array","Int32Array","Uint16Array","Uint32Array","BigInt64Array","BigUint64Array","Set","Map","WeakSet","WeakMap","ArrayBuffer","SharedArrayBuffer","Atomics","DataView","JSON","Promise","Generator","GeneratorFunction","AsyncFunction","Reflect","Proxy","Intl","WebAssembly"],Ee=["Error","EvalError","InternalError","RangeError","ReferenceError","SyntaxError","TypeError","URIError"],ye=["setInterval","setTimeout","clearInterval","clearTimeout","require","exports","eval","isFinite","isNaN","parseFloat","parseInt","decodeURI","decodeURIComponent","encodeURI","encodeURIComponent","escape","unescape"],we=["arguments","this","super","console","window","document","localStorage","sessionStorage","module","global"],Ne=[].concat(ye,fe,Ee) -;function ve(e){const n=e.regex,t=pe,a={begin:/<[A-Za-z0-9\\._:-]+/, -end:/\/[A-Za-z0-9\\._:-]+>|\/>/,isTrulyOpeningTag:(e,n)=>{ -const t=e[0].length+e.index,a=e.input[t] -;if("<"===a||","===a)return void n.ignoreMatch();let i -;">"===a&&(((e,{after:n})=>{const t="e+"\\s*\\(")), -n.concat("(?!",v.join("|"),")")),t,n.lookahead(/\s*\(/)), -className:"title.function",relevance:0};var v;const k={ -begin:n.concat(/\./,n.lookahead(n.concat(t,/(?![0-9A-Za-z$_(])/))),end:t, -excludeBegin:!0,keywords:"prototype",className:"property",relevance:0},x={ -match:[/get|set/,/\s+/,t,/(?=\()/],className:{1:"keyword",3:"title.function"}, -contains:[{begin:/\(\)/},f] -},O="(\\([^()]*(\\([^()]*(\\([^()]*\\)[^()]*)*\\)[^()]*)*\\)|"+e.UNDERSCORE_IDENT_RE+")\\s*=>",M={ -match:[/const|var|let/,/\s+/,t,/\s*/,/=\s*/,/(async\s*)?/,n.lookahead(O)], -keywords:"async",className:{1:"keyword",3:"title.function"},contains:[f]} -;return{name:"JavaScript",aliases:["js","jsx","mjs","cjs"],keywords:i,exports:{ -PARAMS_CONTAINS:h,CLASS_REFERENCE:y},illegal:/#(?![$_A-z])/, -contains:[e.SHEBANG({label:"shebang",binary:"node",relevance:5}),{ -label:"use_strict",className:"meta",relevance:10, -begin:/^\s*['"]use (strict|asm)['"]/ -},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,d,g,u,b,m,{match:/\$\d+/},l,y,{ -className:"attr",begin:t+n.lookahead(":"),relevance:0},M,{ -begin:"("+e.RE_STARTERS_RE+"|\\b(case|return|throw)\\b)\\s*", -keywords:"return throw case",relevance:0,contains:[m,e.REGEXP_MODE,{ -className:"function",begin:O,returnBegin:!0,end:"\\s*=>",contains:[{ -className:"params",variants:[{begin:e.UNDERSCORE_IDENT_RE,relevance:0},{ -className:null,begin:/\(\s*\)/,skip:!0},{begin:/(\s*)\(/,end:/\)/, -excludeBegin:!0,excludeEnd:!0,keywords:i,contains:h}]}]},{begin:/,/,relevance:0 -},{match:/\s+/,relevance:0},{variants:[{begin:"<>",end:""},{ -match:/<[A-Za-z0-9\\._:-]+\s*\/>/},{begin:a.begin, -"on:begin":a.isTrulyOpeningTag,end:a.end}],subLanguage:"xml",contains:[{ -begin:a.begin,end:a.end,skip:!0,contains:["self"]}]}]},w,{ -beginKeywords:"while if switch catch for"},{ -begin:"\\b(?!function)"+e.UNDERSCORE_IDENT_RE+"\\([^()]*(\\([^()]*(\\([^()]*\\)[^()]*)*\\)[^()]*)*\\)\\s*\\{", -returnBegin:!0,label:"func.def",contains:[f,e.inherit(e.TITLE_MODE,{begin:t, -className:"title.function"})]},{match:/\.\.\./,relevance:0},k,{match:"\\$"+t, -relevance:0},{match:[/\bconstructor(?=\s*\()/],className:{1:"title.function"}, -contains:[f]},N,{relevance:0,match:/\b[A-Z][A-Z_0-9]+\b/, -className:"variable.constant"},E,x,{match:/\$[(.]/}]}} -const ke=e=>b(/\b/,e,/\w$/.test(e)?/\b/:/\B/),xe=["Protocol","Type"].map(ke),Oe=["init","self"].map(ke),Me=["Any","Self"],Ae=["actor","any","associatedtype","async","await",/as\?/,/as!/,"as","borrowing","break","case","catch","class","consume","consuming","continue","convenience","copy","default","defer","deinit","didSet","distributed","do","dynamic","each","else","enum","extension","fallthrough",/fileprivate\(set\)/,"fileprivate","final","for","func","get","guard","if","import","indirect","infix",/init\?/,/init!/,"inout",/internal\(set\)/,"internal","in","is","isolated","nonisolated","lazy","let","macro","mutating","nonmutating",/open\(set\)/,"open","operator","optional","override","package","postfix","precedencegroup","prefix",/private\(set\)/,"private","protocol",/public\(set\)/,"public","repeat","required","rethrows","return","set","some","static","struct","subscript","super","switch","throws","throw",/try\?/,/try!/,"try","typealias",/unowned\(safe\)/,/unowned\(unsafe\)/,"unowned","var","weak","where","while","willSet"],Se=["false","nil","true"],Ce=["assignment","associativity","higherThan","left","lowerThan","none","right"],Te=["#colorLiteral","#column","#dsohandle","#else","#elseif","#endif","#error","#file","#fileID","#fileLiteral","#filePath","#function","#if","#imageLiteral","#keyPath","#line","#selector","#sourceLocation","#warning"],Re=["abs","all","any","assert","assertionFailure","debugPrint","dump","fatalError","getVaList","isKnownUniquelyReferenced","max","min","numericCast","pointwiseMax","pointwiseMin","precondition","preconditionFailure","print","readLine","repeatElement","sequence","stride","swap","swift_unboxFromSwiftValueWithType","transcode","type","unsafeBitCast","unsafeDowncast","withExtendedLifetime","withUnsafeMutablePointer","withUnsafePointer","withVaList","withoutActuallyEscaping","zip"],De=m(/[/=\-+!*%<>&|^~?]/,/[\u00A1-\u00A7]/,/[\u00A9\u00AB]/,/[\u00AC\u00AE]/,/[\u00B0\u00B1]/,/[\u00B6\u00BB\u00BF\u00D7\u00F7]/,/[\u2016-\u2017]/,/[\u2020-\u2027]/,/[\u2030-\u203E]/,/[\u2041-\u2053]/,/[\u2055-\u205E]/,/[\u2190-\u23FF]/,/[\u2500-\u2775]/,/[\u2794-\u2BFF]/,/[\u2E00-\u2E7F]/,/[\u3001-\u3003]/,/[\u3008-\u3020]/,/[\u3030]/),Ie=m(De,/[\u0300-\u036F]/,/[\u1DC0-\u1DFF]/,/[\u20D0-\u20FF]/,/[\uFE00-\uFE0F]/,/[\uFE20-\uFE2F]/),Le=b(De,Ie,"*"),Be=m(/[a-zA-Z_]/,/[\u00A8\u00AA\u00AD\u00AF\u00B2-\u00B5\u00B7-\u00BA]/,/[\u00BC-\u00BE\u00C0-\u00D6\u00D8-\u00F6\u00F8-\u00FF]/,/[\u0100-\u02FF\u0370-\u167F\u1681-\u180D\u180F-\u1DBF]/,/[\u1E00-\u1FFF]/,/[\u200B-\u200D\u202A-\u202E\u203F-\u2040\u2054\u2060-\u206F]/,/[\u2070-\u20CF\u2100-\u218F\u2460-\u24FF\u2776-\u2793]/,/[\u2C00-\u2DFF\u2E80-\u2FFF]/,/[\u3004-\u3007\u3021-\u302F\u3031-\u303F\u3040-\uD7FF]/,/[\uF900-\uFD3D\uFD40-\uFDCF\uFDF0-\uFE1F\uFE30-\uFE44]/,/[\uFE47-\uFEFE\uFF00-\uFFFD]/),$e=m(Be,/\d/,/[\u0300-\u036F\u1DC0-\u1DFF\u20D0-\u20FF\uFE20-\uFE2F]/),Fe=b(Be,$e,"*"),ze=b(/[A-Z]/,$e,"*"),je=["attached","autoclosure",b(/convention\(/,m("swift","block","c"),/\)/),"discardableResult","dynamicCallable","dynamicMemberLookup","escaping","freestanding","frozen","GKInspectable","IBAction","IBDesignable","IBInspectable","IBOutlet","IBSegueAction","inlinable","main","nonobjc","NSApplicationMain","NSCopying","NSManaged",b(/objc\(/,Fe,/\)/),"objc","objcMembers","propertyWrapper","requires_stored_property_inits","resultBuilder","Sendable","testable","UIApplicationMain","unchecked","unknown","usableFromInline","warn_unqualified_access"],Ue=["iOS","iOSApplicationExtension","macOS","macOSApplicationExtension","macCatalyst","macCatalystApplicationExtension","watchOS","watchOSApplicationExtension","tvOS","tvOSApplicationExtension","swift"] -;var Pe=Object.freeze({__proto__:null,grmr_bash:e=>{const n=e.regex,t={},a={ -begin:/\$\{/,end:/\}/,contains:["self",{begin:/:-/,contains:[t]}]} -;Object.assign(t,{className:"variable",variants:[{ -begin:n.concat(/\$[\w\d#@][\w\d_]*/,"(?![\\w\\d])(?![$])")},a]});const i={ -className:"subst",begin:/\$\(/,end:/\)/,contains:[e.BACKSLASH_ESCAPE] -},r=e.inherit(e.COMMENT(),{match:[/(^|\s)/,/#.*$/],scope:{2:"comment"}}),s={ -begin:/<<-?\s*(?=\w+)/,starts:{contains:[e.END_SAME_AS_BEGIN({begin:/(\w+)/, -end:/(\w+)/,className:"string"})]}},o={className:"string",begin:/"/,end:/"/, -contains:[e.BACKSLASH_ESCAPE,t,i]};i.contains.push(o);const l={begin:/\$?\(\(/, -end:/\)\)/,contains:[{begin:/\d+#[0-9a-f]+/,className:"number"},e.NUMBER_MODE,t] -},c=e.SHEBANG({binary:"(fish|bash|zsh|sh|csh|ksh|tcsh|dash|scsh)",relevance:10 -}),d={className:"function",begin:/\w[\w\d_]*\s*\(\s*\)\s*\{/,returnBegin:!0, -contains:[e.inherit(e.TITLE_MODE,{begin:/\w[\w\d_]*/})],relevance:0};return{ -name:"Bash",aliases:["sh","zsh"],keywords:{$pattern:/\b[a-z][a-z0-9._-]+\b/, -keyword:["if","then","else","elif","fi","for","while","until","in","do","done","case","esac","function","select"], -literal:["true","false"], -built_in:["break","cd","continue","eval","exec","exit","export","getopts","hash","pwd","readonly","return","shift","test","times","trap","umask","unset","alias","bind","builtin","caller","command","declare","echo","enable","help","let","local","logout","mapfile","printf","read","readarray","source","sudo","type","typeset","ulimit","unalias","set","shopt","autoload","bg","bindkey","bye","cap","chdir","clone","comparguments","compcall","compctl","compdescribe","compfiles","compgroups","compquote","comptags","comptry","compvalues","dirs","disable","disown","echotc","echoti","emulate","fc","fg","float","functions","getcap","getln","history","integer","jobs","kill","limit","log","noglob","popd","print","pushd","pushln","rehash","sched","setcap","setopt","stat","suspend","ttyctl","unfunction","unhash","unlimit","unsetopt","vared","wait","whence","where","which","zcompile","zformat","zftp","zle","zmodload","zparseopts","zprof","zpty","zregexparse","zsocket","zstyle","ztcp","chcon","chgrp","chown","chmod","cp","dd","df","dir","dircolors","ln","ls","mkdir","mkfifo","mknod","mktemp","mv","realpath","rm","rmdir","shred","sync","touch","truncate","vdir","b2sum","base32","base64","cat","cksum","comm","csplit","cut","expand","fmt","fold","head","join","md5sum","nl","numfmt","od","paste","ptx","pr","sha1sum","sha224sum","sha256sum","sha384sum","sha512sum","shuf","sort","split","sum","tac","tail","tr","tsort","unexpand","uniq","wc","arch","basename","chroot","date","dirname","du","echo","env","expr","factor","groups","hostid","id","link","logname","nice","nohup","nproc","pathchk","pinky","printenv","printf","pwd","readlink","runcon","seq","sleep","stat","stdbuf","stty","tee","test","timeout","tty","uname","unlink","uptime","users","who","whoami","yes"] -},contains:[c,e.SHEBANG(),d,l,r,s,{match:/(\/[a-z._-]+)+/},o,{match:/\\"/},{ -className:"string",begin:/'/,end:/'/},{match:/\\'/},t]}},grmr_c:e=>{ -const n=e.regex,t=e.COMMENT("//","$",{contains:[{begin:/\\\n/}] -}),a="decltype\\(auto\\)",i="[a-zA-Z_]\\w*::",r="("+a+"|"+n.optional(i)+"[a-zA-Z_]\\w*"+n.optional("<[^<>]+>")+")",s={ -className:"type",variants:[{begin:"\\b[a-z\\d_]*_t\\b"},{ -match:/\batomic_[a-z]{3,6}\b/}]},o={className:"string",variants:[{ -begin:'(u8?|U|L)?"',end:'"',illegal:"\\n",contains:[e.BACKSLASH_ESCAPE]},{ -begin:"(u8?|U|L)?'(\\\\(x[0-9A-Fa-f]{2}|u[0-9A-Fa-f]{4,8}|[0-7]{3}|\\S)|.)", -end:"'",illegal:"."},e.END_SAME_AS_BEGIN({ -begin:/(?:u8?|U|L)?R"([^()\\ ]{0,16})\(/,end:/\)([^()\\ ]{0,16})"/})]},l={ -className:"number",variants:[{begin:"\\b(0b[01']+)"},{ -begin:"(-?)\\b([\\d']+(\\.[\\d']*)?|\\.[\\d']+)((ll|LL|l|L)(u|U)?|(u|U)(ll|LL|l|L)?|f|F|b|B)" -},{ -begin:"(-?)(\\b0[xX][a-fA-F0-9']+|(\\b[\\d']+(\\.[\\d']*)?|\\.[\\d']+)([eE][-+]?[\\d']+)?)" -}],relevance:0},c={className:"meta",begin:/#\s*[a-z]+\b/,end:/$/,keywords:{ -keyword:"if else elif endif define undef warning error line pragma _Pragma ifdef ifndef elifdef elifndef include" -},contains:[{begin:/\\\n/,relevance:0},e.inherit(o,{className:"string"}),{ -className:"string",begin:/<.*?>/},t,e.C_BLOCK_COMMENT_MODE]},d={ -className:"title",begin:n.optional(i)+e.IDENT_RE,relevance:0 -},g=n.optional(i)+e.IDENT_RE+"\\s*\\(",u={ -keyword:["asm","auto","break","case","continue","default","do","else","enum","extern","for","fortran","goto","if","inline","register","restrict","return","sizeof","typeof","typeof_unqual","struct","switch","typedef","union","volatile","while","_Alignas","_Alignof","_Atomic","_Generic","_Noreturn","_Static_assert","_Thread_local","alignas","alignof","noreturn","static_assert","thread_local","_Pragma"], -type:["float","double","signed","unsigned","int","short","long","char","void","_Bool","_BitInt","_Complex","_Imaginary","_Decimal32","_Decimal64","_Decimal96","_Decimal128","_Decimal64x","_Decimal128x","_Float16","_Float32","_Float64","_Float128","_Float32x","_Float64x","_Float128x","const","static","constexpr","complex","bool","imaginary"], -literal:"true false NULL", -built_in:"std string wstring cin cout cerr clog stdin stdout stderr stringstream istringstream ostringstream auto_ptr deque list queue stack vector map set pair bitset multiset multimap unordered_set unordered_map unordered_multiset unordered_multimap priority_queue make_pair array shared_ptr abort terminate abs acos asin atan2 atan calloc ceil cosh cos exit exp fabs floor fmod fprintf fputs free frexp fscanf future isalnum isalpha iscntrl isdigit isgraph islower isprint ispunct isspace isupper isxdigit tolower toupper labs ldexp log10 log malloc realloc memchr memcmp memcpy memset modf pow printf putchar puts scanf sinh sin snprintf sprintf sqrt sscanf strcat strchr strcmp strcpy strcspn strlen strncat strncmp strncpy strpbrk strrchr strspn strstr tanh tan vfprintf vprintf vsprintf endl initializer_list unique_ptr" -},b=[c,s,t,e.C_BLOCK_COMMENT_MODE,l,o],m={variants:[{begin:/=/,end:/;/},{ -begin:/\(/,end:/\)/},{beginKeywords:"new throw return else",end:/;/}], -keywords:u,contains:b.concat([{begin:/\(/,end:/\)/,keywords:u, -contains:b.concat(["self"]),relevance:0}]),relevance:0},p={ -begin:"("+r+"[\\*&\\s]+)+"+g,returnBegin:!0,end:/[{;=]/,excludeEnd:!0, -keywords:u,illegal:/[^\w\s\*&:<>.]/,contains:[{begin:a,keywords:u,relevance:0},{ -begin:g,returnBegin:!0,contains:[e.inherit(d,{className:"title.function"})], -relevance:0},{relevance:0,match:/,/},{className:"params",begin:/\(/,end:/\)/, -keywords:u,relevance:0,contains:[t,e.C_BLOCK_COMMENT_MODE,o,l,s,{begin:/\(/, -end:/\)/,keywords:u,relevance:0,contains:["self",t,e.C_BLOCK_COMMENT_MODE,o,l,s] -}]},s,t,e.C_BLOCK_COMMENT_MODE,c]};return{name:"C",aliases:["h"],keywords:u, -disableAutodetect:!0,illegal:"=]/,contains:[{ -beginKeywords:"final class struct"},e.TITLE_MODE]}]),exports:{preprocessor:c, -strings:o,keywords:u}}},grmr_cpp:e=>{const n=e.regex,t=e.COMMENT("//","$",{ -contains:[{begin:/\\\n/}] -}),a="decltype\\(auto\\)",i="[a-zA-Z_]\\w*::",r="(?!struct)("+a+"|"+n.optional(i)+"[a-zA-Z_]\\w*"+n.optional("<[^<>]+>")+")",s={ -className:"type",begin:"\\b[a-z\\d_]*_t\\b"},o={className:"string",variants:[{ -begin:'(u8?|U|L)?"',end:'"',illegal:"\\n",contains:[e.BACKSLASH_ESCAPE]},{ -begin:"(u8?|U|L)?'(\\\\(x[0-9A-Fa-f]{2}|u[0-9A-Fa-f]{4,8}|[0-7]{3}|\\S)|.)", -end:"'",illegal:"."},e.END_SAME_AS_BEGIN({ -begin:/(?:u8?|U|L)?R"([^()\\ ]{0,16})\(/,end:/\)([^()\\ ]{0,16})"/})]},l={ -className:"number",variants:[{ -begin:"[+-]?(?:(?:[0-9](?:'?[0-9])*\\.(?:[0-9](?:'?[0-9])*)?|\\.[0-9](?:'?[0-9])*)(?:[Ee][+-]?[0-9](?:'?[0-9])*)?|[0-9](?:'?[0-9])*[Ee][+-]?[0-9](?:'?[0-9])*|0[Xx](?:[0-9A-Fa-f](?:'?[0-9A-Fa-f])*(?:\\.(?:[0-9A-Fa-f](?:'?[0-9A-Fa-f])*)?)?|\\.[0-9A-Fa-f](?:'?[0-9A-Fa-f])*)[Pp][+-]?[0-9](?:'?[0-9])*)(?:[Ff](?:16|32|64|128)?|(BF|bf)16|[Ll]|)" -},{ -begin:"[+-]?\\b(?:0[Bb][01](?:'?[01])*|0[Xx][0-9A-Fa-f](?:'?[0-9A-Fa-f])*|0(?:'?[0-7])*|[1-9](?:'?[0-9])*)(?:[Uu](?:LL?|ll?)|[Uu][Zz]?|(?:LL?|ll?)[Uu]?|[Zz][Uu]|)" -}],relevance:0},c={className:"meta",begin:/#\s*[a-z]+\b/,end:/$/,keywords:{ -keyword:"if else elif endif define undef warning error line pragma _Pragma ifdef ifndef include" -},contains:[{begin:/\\\n/,relevance:0},e.inherit(o,{className:"string"}),{ -className:"string",begin:/<.*?>/},t,e.C_BLOCK_COMMENT_MODE]},d={ -className:"title",begin:n.optional(i)+e.IDENT_RE,relevance:0 -},g=n.optional(i)+e.IDENT_RE+"\\s*\\(",u={ -type:["bool","char","char16_t","char32_t","char8_t","double","float","int","long","short","void","wchar_t","unsigned","signed","const","static"], -keyword:["alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit","atomic_noexcept","auto","bitand","bitor","break","case","catch","class","co_await","co_return","co_yield","compl","concept","const_cast|10","consteval","constexpr","constinit","continue","decltype","default","delete","do","dynamic_cast|10","else","enum","explicit","export","extern","false","final","for","friend","goto","if","import","inline","module","mutable","namespace","new","noexcept","not","not_eq","nullptr","operator","or","or_eq","override","private","protected","public","reflexpr","register","reinterpret_cast|10","requires","return","sizeof","static_assert","static_cast|10","struct","switch","synchronized","template","this","thread_local","throw","transaction_safe","transaction_safe_dynamic","true","try","typedef","typeid","typename","union","using","virtual","volatile","while","xor","xor_eq"], -literal:["NULL","false","nullopt","nullptr","true"],built_in:["_Pragma"], -_type_hints:["any","auto_ptr","barrier","binary_semaphore","bitset","complex","condition_variable","condition_variable_any","counting_semaphore","deque","false_type","future","imaginary","initializer_list","istringstream","jthread","latch","lock_guard","multimap","multiset","mutex","optional","ostringstream","packaged_task","pair","promise","priority_queue","queue","recursive_mutex","recursive_timed_mutex","scoped_lock","set","shared_future","shared_lock","shared_mutex","shared_timed_mutex","shared_ptr","stack","string_view","stringstream","timed_mutex","thread","true_type","tuple","unique_lock","unique_ptr","unordered_map","unordered_multimap","unordered_multiset","unordered_set","variant","vector","weak_ptr","wstring","wstring_view"] -},b={className:"function.dispatch",relevance:0,keywords:{ -_hint:["abort","abs","acos","apply","as_const","asin","atan","atan2","calloc","ceil","cerr","cin","clog","cos","cosh","cout","declval","endl","exchange","exit","exp","fabs","floor","fmod","forward","fprintf","fputs","free","frexp","fscanf","future","invoke","isalnum","isalpha","iscntrl","isdigit","isgraph","islower","isprint","ispunct","isspace","isupper","isxdigit","labs","launder","ldexp","log","log10","make_pair","make_shared","make_shared_for_overwrite","make_tuple","make_unique","malloc","memchr","memcmp","memcpy","memset","modf","move","pow","printf","putchar","puts","realloc","scanf","sin","sinh","snprintf","sprintf","sqrt","sscanf","std","stderr","stdin","stdout","strcat","strchr","strcmp","strcpy","strcspn","strlen","strncat","strncmp","strncpy","strpbrk","strrchr","strspn","strstr","swap","tan","tanh","terminate","to_underlying","tolower","toupper","vfprintf","visit","vprintf","vsprintf"] -}, -begin:n.concat(/\b/,/(?!decltype)/,/(?!if)/,/(?!for)/,/(?!switch)/,/(?!while)/,e.IDENT_RE,n.lookahead(/(<[^<>]+>|)\s*\(/)) -},m=[b,c,s,t,e.C_BLOCK_COMMENT_MODE,l,o],p={variants:[{begin:/=/,end:/;/},{ -begin:/\(/,end:/\)/},{beginKeywords:"new throw return else",end:/;/}], -keywords:u,contains:m.concat([{begin:/\(/,end:/\)/,keywords:u, -contains:m.concat(["self"]),relevance:0}]),relevance:0},_={className:"function", -begin:"("+r+"[\\*&\\s]+)+"+g,returnBegin:!0,end:/[{;=]/,excludeEnd:!0, -keywords:u,illegal:/[^\w\s\*&:<>.]/,contains:[{begin:a,keywords:u,relevance:0},{ -begin:g,returnBegin:!0,contains:[d],relevance:0},{begin:/::/,relevance:0},{ -begin:/:/,endsWithParent:!0,contains:[o,l]},{relevance:0,match:/,/},{ -className:"params",begin:/\(/,end:/\)/,keywords:u,relevance:0, -contains:[t,e.C_BLOCK_COMMENT_MODE,o,l,s,{begin:/\(/,end:/\)/,keywords:u, -relevance:0,contains:["self",t,e.C_BLOCK_COMMENT_MODE,o,l,s]}] -},s,t,e.C_BLOCK_COMMENT_MODE,c]};return{name:"C++", -aliases:["cc","c++","h++","hpp","hh","hxx","cxx"],keywords:u,illegal:"",keywords:u,contains:["self",s]},{begin:e.IDENT_RE+"::",keywords:u},{ -match:[/\b(?:enum(?:\s+(?:class|struct))?|class|struct|union)/,/\s+/,/\w+/], -className:{1:"keyword",3:"title.class"}}])}},grmr_csharp:e=>{const n={ -keyword:["abstract","as","base","break","case","catch","class","const","continue","do","else","event","explicit","extern","finally","fixed","for","foreach","goto","if","implicit","in","interface","internal","is","lock","namespace","new","operator","out","override","params","private","protected","public","readonly","record","ref","return","scoped","sealed","sizeof","stackalloc","static","struct","switch","this","throw","try","typeof","unchecked","unsafe","using","virtual","void","volatile","while"].concat(["add","alias","and","ascending","async","await","by","descending","equals","from","get","global","group","init","into","join","let","nameof","not","notnull","on","or","orderby","partial","remove","select","set","unmanaged","value|0","var","when","where","with","yield"]), -built_in:["bool","byte","char","decimal","delegate","double","dynamic","enum","float","int","long","nint","nuint","object","sbyte","short","string","ulong","uint","ushort"], -literal:["default","false","null","true"]},t=e.inherit(e.TITLE_MODE,{ -begin:"[a-zA-Z](\\.?\\w)*"}),a={className:"number",variants:[{ -begin:"\\b(0b[01']+)"},{ -begin:"(-?)\\b([\\d']+(\\.[\\d']*)?|\\.[\\d']+)(u|U|l|L|ul|UL|f|F|b|B)"},{ -begin:"(-?)(\\b0[xX][a-fA-F0-9']+|(\\b[\\d']+(\\.[\\d']*)?|\\.[\\d']+)([eE][-+]?[\\d']+)?)" -}],relevance:0},i={className:"string",begin:'@"',end:'"',contains:[{begin:'""'}] -},r=e.inherit(i,{illegal:/\n/}),s={className:"subst",begin:/\{/,end:/\}/, -keywords:n},o=e.inherit(s,{illegal:/\n/}),l={className:"string",begin:/\$"/, -end:'"',illegal:/\n/,contains:[{begin:/\{\{/},{begin:/\}\}/ -},e.BACKSLASH_ESCAPE,o]},c={className:"string",begin:/\$@"/,end:'"',contains:[{ -begin:/\{\{/},{begin:/\}\}/},{begin:'""'},s]},d=e.inherit(c,{illegal:/\n/, -contains:[{begin:/\{\{/},{begin:/\}\}/},{begin:'""'},o]}) -;s.contains=[c,l,i,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,a,e.C_BLOCK_COMMENT_MODE], -o.contains=[d,l,r,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,a,e.inherit(e.C_BLOCK_COMMENT_MODE,{ -illegal:/\n/})];const g={variants:[{className:"string", -begin:/"""("*)(?!")(.|\n)*?"""\1/,relevance:1 -},c,l,i,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE]},u={begin:"<",end:">", -contains:[{beginKeywords:"in out"},t] -},b=e.IDENT_RE+"(<"+e.IDENT_RE+"(\\s*,\\s*"+e.IDENT_RE+")*>)?(\\[\\])?",m={ -begin:"@"+e.IDENT_RE,relevance:0};return{name:"C#",aliases:["cs","c#"], -keywords:n,illegal:/::/,contains:[e.COMMENT("///","$",{returnBegin:!0, -contains:[{className:"doctag",variants:[{begin:"///",relevance:0},{ -begin:"\x3c!--|--\x3e"},{begin:""}]}] -}),e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,{className:"meta",begin:"#", -end:"$",keywords:{ -keyword:"if else elif endif define undef warning error line region endregion pragma checksum" -}},g,a,{beginKeywords:"class interface",relevance:0,end:/[{;=]/, -illegal:/[^\s:,]/,contains:[{beginKeywords:"where class" -},t,u,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{beginKeywords:"namespace", -relevance:0,end:/[{;=]/,illegal:/[^\s:]/, -contains:[t,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{ -beginKeywords:"record",relevance:0,end:/[{;=]/,illegal:/[^\s:]/, -contains:[t,u,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{className:"meta", -begin:"^\\s*\\[(?=[\\w])",excludeBegin:!0,end:"\\]",excludeEnd:!0,contains:[{ -className:"string",begin:/"/,end:/"/}]},{ -beginKeywords:"new return throw await else",relevance:0},{className:"function", -begin:"("+b+"\\s+)+"+e.IDENT_RE+"\\s*(<[^=]+>\\s*)?\\(",returnBegin:!0, -end:/\s*[{;=]/,excludeEnd:!0,keywords:n,contains:[{ -beginKeywords:"public private protected static internal protected abstract async extern override unsafe virtual new sealed partial", -relevance:0},{begin:e.IDENT_RE+"\\s*(<[^=]+>\\s*)?\\(",returnBegin:!0, -contains:[e.TITLE_MODE,u],relevance:0},{match:/\(\)/},{className:"params", -begin:/\(/,end:/\)/,excludeBegin:!0,excludeEnd:!0,keywords:n,relevance:0, -contains:[g,a,e.C_BLOCK_COMMENT_MODE] -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},m]}},grmr_css:e=>{ -const n=e.regex,t=ae(e),a=[e.APOS_STRING_MODE,e.QUOTE_STRING_MODE];return{ -name:"CSS",case_insensitive:!0,illegal:/[=|'\$]/,keywords:{ -keyframePosition:"from to"},classNameAliases:{keyframePosition:"selector-tag"}, -contains:[t.BLOCK_COMMENT,{begin:/-(webkit|moz|ms|o)-(?=[a-z])/ -},t.CSS_NUMBER_MODE,{className:"selector-id",begin:/#[A-Za-z0-9_-]+/,relevance:0 -},{className:"selector-class",begin:"\\.[a-zA-Z-][a-zA-Z0-9_-]*",relevance:0 -},t.ATTRIBUTE_SELECTOR_MODE,{className:"selector-pseudo",variants:[{ -begin:":("+se.join("|")+")"},{begin:":(:)?("+oe.join("|")+")"}] -},t.CSS_VARIABLE,{className:"attribute",begin:"\\b("+le.join("|")+")\\b"},{ -begin:/:/,end:/[;}{]/, -contains:[t.BLOCK_COMMENT,t.HEXCOLOR,t.IMPORTANT,t.CSS_NUMBER_MODE,...a,{ -begin:/(url|data-uri)\(/,end:/\)/,relevance:0,keywords:{built_in:"url data-uri" -},contains:[...a,{className:"string",begin:/[^)]/,endsWithParent:!0, -excludeEnd:!0}]},t.FUNCTION_DISPATCH]},{begin:n.lookahead(/@/),end:"[{;]", -relevance:0,illegal:/:/,contains:[{className:"keyword",begin:/@-?\w[\w]*(-\w+)*/ -},{begin:/\s/,endsWithParent:!0,excludeEnd:!0,relevance:0,keywords:{ -$pattern:/[a-z-]+/,keyword:"and or not only",attribute:re.join(" ")},contains:[{ -begin:/[a-z-]+(?=:)/,className:"attribute"},...a,t.CSS_NUMBER_MODE]}]},{ -className:"selector-tag",begin:"\\b("+ie.join("|")+")\\b"}]}},grmr_diff:e=>{ -const n=e.regex;return{name:"Diff",aliases:["patch"],contains:[{ -className:"meta",relevance:10, -match:n.either(/^@@ +-\d+,\d+ +\+\d+,\d+ +@@/,/^\*\*\* +\d+,\d+ +\*\*\*\*$/,/^--- +\d+,\d+ +----$/) -},{className:"comment",variants:[{ -begin:n.either(/Index: /,/^index/,/={3,}/,/^-{3}/,/^\*{3} /,/^\+{3}/,/^diff --git/), -end:/$/},{match:/^\*{15}$/}]},{className:"addition",begin:/^\+/,end:/$/},{ -className:"deletion",begin:/^-/,end:/$/},{className:"addition",begin:/^!/, -end:/$/}]}},grmr_go:e=>{const n={ -keyword:["break","case","chan","const","continue","default","defer","else","fallthrough","for","func","go","goto","if","import","interface","map","package","range","return","select","struct","switch","type","var"], -type:["bool","byte","complex64","complex128","error","float32","float64","int8","int16","int32","int64","string","uint8","uint16","uint32","uint64","int","uint","uintptr","rune"], -literal:["true","false","iota","nil"], -built_in:["append","cap","close","complex","copy","imag","len","make","new","panic","print","println","real","recover","delete"] -};return{name:"Go",aliases:["golang"],keywords:n,illegal:"{const n=e.regex -;return{name:"GraphQL",aliases:["gql"],case_insensitive:!0,disableAutodetect:!1, -keywords:{ -keyword:["query","mutation","subscription","type","input","schema","directive","interface","union","scalar","fragment","enum","on"], -literal:["true","false","null"]}, -contains:[e.HASH_COMMENT_MODE,e.QUOTE_STRING_MODE,e.NUMBER_MODE,{ -scope:"punctuation",match:/[.]{3}/,relevance:0},{scope:"punctuation", -begin:/[\!\(\)\:\=\[\]\{\|\}]{1}/,relevance:0},{scope:"variable",begin:/\$/, -end:/\W/,excludeEnd:!0,relevance:0},{scope:"meta",match:/@\w+/,excludeEnd:!0},{ -scope:"symbol",begin:n.concat(/[_A-Za-z][_0-9A-Za-z]*/,n.lookahead(/\s*:/)), -relevance:0}],illegal:[/[;<']/,/BEGIN/]}},grmr_ini:e=>{const n=e.regex,t={ -className:"number",relevance:0,variants:[{begin:/([+-]+)?[\d]+_[\d_]+/},{ -begin:e.NUMBER_RE}]},a=e.COMMENT();a.variants=[{begin:/;/,end:/$/},{begin:/#/, -end:/$/}];const i={className:"variable",variants:[{begin:/\$[\w\d"][\w\d_]*/},{ -begin:/\$\{(.*?)\}/}]},r={className:"literal", -begin:/\bon|off|true|false|yes|no\b/},s={className:"string", -contains:[e.BACKSLASH_ESCAPE],variants:[{begin:"'''",end:"'''",relevance:10},{ -begin:'"""',end:'"""',relevance:10},{begin:'"',end:'"'},{begin:"'",end:"'"}] -},o={begin:/\[/,end:/\]/,contains:[a,r,i,s,t,"self"],relevance:0 -},l=n.either(/[A-Za-z0-9_-]+/,/"(\\"|[^"])*"/,/'[^']*'/);return{ -name:"TOML, also INI",aliases:["toml"],case_insensitive:!0,illegal:/\S/, -contains:[a,{className:"section",begin:/\[+/,end:/\]+/},{ -begin:n.concat(l,"(\\s*\\.\\s*",l,")*",n.lookahead(/\s*=\s*[^#\s]/)), -className:"attr",starts:{end:/$/,contains:[a,o,r,i,s,t]}}]}},grmr_java:e=>{ -const n=e.regex,t="[\xc0-\u02b8a-zA-Z_$][\xc0-\u02b8a-zA-Z_$0-9]*",a=t+me("(?:<"+t+"~~~(?:\\s*,\\s*"+t+"~~~)*>)?",/~~~/g,2),i={ -keyword:["synchronized","abstract","private","var","static","if","const ","for","while","strictfp","finally","protected","import","native","final","void","enum","else","break","transient","catch","instanceof","volatile","case","assert","package","default","public","try","switch","continue","throws","protected","public","private","module","requires","exports","do","sealed","yield","permits","goto"], -literal:["false","true","null"], -type:["char","boolean","long","float","int","byte","short","double"], -built_in:["super","this"]},r={className:"meta",begin:"@"+t,contains:[{ -begin:/\(/,end:/\)/,contains:["self"]}]},s={className:"params",begin:/\(/, -end:/\)/,keywords:i,relevance:0,contains:[e.C_BLOCK_COMMENT_MODE],endsParent:!0} -;return{name:"Java",aliases:["jsp"],keywords:i,illegal:/<\/|#/, -contains:[e.COMMENT("/\\*\\*","\\*/",{relevance:0,contains:[{begin:/\w+@/, -relevance:0},{className:"doctag",begin:"@[A-Za-z]+"}]}),{ -begin:/import java\.[a-z]+\./,keywords:"import",relevance:2 -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,{begin:/"""/,end:/"""/, -className:"string",contains:[e.BACKSLASH_ESCAPE] -},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,{ -match:[/\b(?:class|interface|enum|extends|implements|new)/,/\s+/,t],className:{ -1:"keyword",3:"title.class"}},{match:/non-sealed/,scope:"keyword"},{ -begin:[n.concat(/(?!else)/,t),/\s+/,t,/\s+/,/=(?!=)/],className:{1:"type", -3:"variable",5:"operator"}},{begin:[/record/,/\s+/,t],className:{1:"keyword", -3:"title.class"},contains:[s,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{ -beginKeywords:"new throw return else",relevance:0},{ -begin:["(?:"+a+"\\s+)",e.UNDERSCORE_IDENT_RE,/\s*(?=\()/],className:{ -2:"title.function"},keywords:i,contains:[{className:"params",begin:/\(/, -end:/\)/,keywords:i,relevance:0, -contains:[r,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,be,e.C_BLOCK_COMMENT_MODE] -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},be,r]}},grmr_javascript:ve, -grmr_json:e=>{const n=["true","false","null"],t={scope:"literal", -beginKeywords:n.join(" ")};return{name:"JSON",aliases:["jsonc"],keywords:{ -literal:n},contains:[{className:"attr",begin:/"(\\.|[^\\"\r\n])*"(?=\s*:)/, -relevance:1.01},{match:/[{}[\],:]/,className:"punctuation",relevance:0 -},e.QUOTE_STRING_MODE,t,e.C_NUMBER_MODE,e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE], -illegal:"\\S"}},grmr_kotlin:e=>{const n={ -keyword:"abstract as val var vararg get set class object open private protected public noinline crossinline dynamic final enum if else do while for when throw try catch finally import package is in fun override companion reified inline lateinit init interface annotation data sealed internal infix operator out by constructor super tailrec where const inner suspend typealias external expect actual", -built_in:"Byte Short Char Int Long Boolean Float Double Void Unit Nothing", -literal:"true false null"},t={className:"symbol",begin:e.UNDERSCORE_IDENT_RE+"@" -},a={className:"subst",begin:/\$\{/,end:/\}/,contains:[e.C_NUMBER_MODE]},i={ -className:"variable",begin:"\\$"+e.UNDERSCORE_IDENT_RE},r={className:"string", -variants:[{begin:'"""',end:'"""(?=[^"])',contains:[i,a]},{begin:"'",end:"'", -illegal:/\n/,contains:[e.BACKSLASH_ESCAPE]},{begin:'"',end:'"',illegal:/\n/, -contains:[e.BACKSLASH_ESCAPE,i,a]}]};a.contains.push(r);const s={ -className:"meta", -begin:"@(?:file|property|field|get|set|receiver|param|setparam|delegate)\\s*:(?:\\s*"+e.UNDERSCORE_IDENT_RE+")?" -},o={className:"meta",begin:"@"+e.UNDERSCORE_IDENT_RE,contains:[{begin:/\(/, -end:/\)/,contains:[e.inherit(r,{className:"string"}),"self"]}] -},l=be,c=e.COMMENT("/\\*","\\*/",{contains:[e.C_BLOCK_COMMENT_MODE]}),d={ -variants:[{className:"type",begin:e.UNDERSCORE_IDENT_RE},{begin:/\(/,end:/\)/, -contains:[]}]},g=d;return g.variants[1].contains=[d],d.variants[1].contains=[g], -{name:"Kotlin",aliases:["kt","kts"],keywords:n, -contains:[e.COMMENT("/\\*\\*","\\*/",{relevance:0,contains:[{className:"doctag", -begin:"@[A-Za-z]+"}]}),e.C_LINE_COMMENT_MODE,c,{className:"keyword", -begin:/\b(break|continue|return|this)\b/,starts:{contains:[{className:"symbol", -begin:/@\w+/}]}},t,s,o,{className:"function",beginKeywords:"fun",end:"[(]|$", -returnBegin:!0,excludeEnd:!0,keywords:n,relevance:5,contains:[{ -begin:e.UNDERSCORE_IDENT_RE+"\\s*\\(",returnBegin:!0,relevance:0, -contains:[e.UNDERSCORE_TITLE_MODE]},{className:"type",begin://, -keywords:"reified",relevance:0},{className:"params",begin:/\(/,end:/\)/, -endsParent:!0,keywords:n,relevance:0,contains:[{begin:/:/,end:/[=,\/]/, -endsWithParent:!0,contains:[d,e.C_LINE_COMMENT_MODE,c],relevance:0 -},e.C_LINE_COMMENT_MODE,c,s,o,r,e.C_NUMBER_MODE]},c]},{ -begin:[/class|interface|trait/,/\s+/,e.UNDERSCORE_IDENT_RE],beginScope:{ -3:"title.class"},keywords:"class interface trait",end:/[:\{(]|$/,excludeEnd:!0, -illegal:"extends implements",contains:[{ -beginKeywords:"public protected internal private constructor" -},e.UNDERSCORE_TITLE_MODE,{className:"type",begin://,excludeBegin:!0, -excludeEnd:!0,relevance:0},{className:"type",begin:/[,:]\s*/,end:/[<\(,){\s]|$/, -excludeBegin:!0,returnEnd:!0},s,o]},r,{className:"meta",begin:"^#!/usr/bin/env", -end:"$",illegal:"\n"},l]}},grmr_less:e=>{ -const n=ae(e),t=ce,a="[\\w-]+",i="("+a+"|@\\{"+a+"\\})",r=[],s=[],o=e=>({ -className:"string",begin:"~?"+e+".*?"+e}),l=(e,n,t)=>({className:e,begin:n, -relevance:t}),c={$pattern:/[a-z-]+/,keyword:"and or not only", -attribute:re.join(" ")},d={begin:"\\(",end:"\\)",contains:s,keywords:c, -relevance:0} -;s.push(e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,o("'"),o('"'),n.CSS_NUMBER_MODE,{ -begin:"(url|data-uri)\\(",starts:{className:"string",end:"[\\)\\n]", -excludeEnd:!0} -},n.HEXCOLOR,d,l("variable","@@?"+a,10),l("variable","@\\{"+a+"\\}"),l("built_in","~?`[^`]*?`"),{ -className:"attribute",begin:a+"\\s*:",end:":",returnBegin:!0,excludeEnd:!0 -},n.IMPORTANT,{beginKeywords:"and not"},n.FUNCTION_DISPATCH);const g=s.concat({ -begin:/\{/,end:/\}/,contains:r}),u={beginKeywords:"when",endsWithParent:!0, -contains:[{beginKeywords:"and not"}].concat(s)},b={begin:i+"\\s*:", -returnBegin:!0,end:/[;}]/,relevance:0,contains:[{begin:/-(webkit|moz|ms|o)-/ -},n.CSS_VARIABLE,{className:"attribute",begin:"\\b("+le.join("|")+")\\b", -end:/(?=:)/,starts:{endsWithParent:!0,illegal:"[<=$]",relevance:0,contains:s}}] -},m={className:"keyword", -begin:"@(import|media|charset|font-face|(-[a-z]+-)?keyframes|supports|document|namespace|page|viewport|host)\\b", -starts:{end:"[;{}]",keywords:c,returnEnd:!0,contains:s,relevance:0}},p={ -className:"variable",variants:[{begin:"@"+a+"\\s*:",relevance:15},{begin:"@"+a -}],starts:{end:"[;}]",returnEnd:!0,contains:g}},_={variants:[{ -begin:"[\\.#:&\\[>]",end:"[;{}]"},{begin:i,end:/\{/}],returnBegin:!0, -returnEnd:!0,illegal:"[<='$\"]",relevance:0, -contains:[e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,u,l("keyword","all\\b"),l("variable","@\\{"+a+"\\}"),{ -begin:"\\b("+ie.join("|")+")\\b",className:"selector-tag" -},n.CSS_NUMBER_MODE,l("selector-tag",i,0),l("selector-id","#"+i),l("selector-class","\\."+i,0),l("selector-tag","&",0),n.ATTRIBUTE_SELECTOR_MODE,{ -className:"selector-pseudo",begin:":("+se.join("|")+")"},{ -className:"selector-pseudo",begin:":(:)?("+oe.join("|")+")"},{begin:/\(/, -end:/\)/,relevance:0,contains:g},{begin:"!important"},n.FUNCTION_DISPATCH]},h={ -begin:a+":(:)?"+`(${t.join("|")})`,returnBegin:!0,contains:[_]} -;return r.push(e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,m,p,h,b,_,u,n.FUNCTION_DISPATCH), -{name:"Less",case_insensitive:!0,illegal:"[=>'/<($\"]",contains:r}}, -grmr_lua:e=>{const n="\\[=*\\[",t="\\]=*\\]",a={begin:n,end:t,contains:["self"] -},i=[e.COMMENT("--(?!"+n+")","$"),e.COMMENT("--"+n,t,{contains:[a],relevance:10 -})];return{name:"Lua",keywords:{$pattern:e.UNDERSCORE_IDENT_RE, -literal:"true false nil", -keyword:"and break do else elseif end for goto if in local not or repeat return then until while", -built_in:"_G _ENV _VERSION __index __newindex __mode __call __metatable __tostring __len __gc __add __sub __mul __div __mod __pow __concat __unm __eq __lt __le assert collectgarbage dofile error getfenv getmetatable ipairs load loadfile loadstring module next pairs pcall print rawequal rawget rawset require select setfenv setmetatable tonumber tostring type unpack xpcall arg self coroutine resume yield status wrap create running debug getupvalue debug sethook getmetatable gethook setmetatable setlocal traceback setfenv getinfo setupvalue getlocal getregistry getfenv io lines write close flush open output type read stderr stdin input stdout popen tmpfile math log max acos huge ldexp pi cos tanh pow deg tan cosh sinh random randomseed frexp ceil floor rad abs sqrt modf asin min mod fmod log10 atan2 exp sin atan os exit setlocale date getenv difftime remove time clock tmpname rename execute package preload loadlib loaded loaders cpath config path seeall string sub upper len gfind rep find match char dump gmatch reverse byte format gsub lower table setn insert getn foreachi maxn foreach concat sort remove" -},contains:i.concat([{className:"function",beginKeywords:"function",end:"\\)", -contains:[e.inherit(e.TITLE_MODE,{ -begin:"([_a-zA-Z]\\w*\\.)*([_a-zA-Z]\\w*:)?[_a-zA-Z]\\w*"}),{className:"params", -begin:"\\(",endsWithParent:!0,contains:i}].concat(i) -},e.C_NUMBER_MODE,e.APOS_STRING_MODE,e.QUOTE_STRING_MODE,{className:"string", -begin:n,end:t,contains:[a],relevance:5}])}},grmr_makefile:e=>{const n={ -className:"variable",variants:[{begin:"\\$\\("+e.UNDERSCORE_IDENT_RE+"\\)", -contains:[e.BACKSLASH_ESCAPE]},{begin:/\$[@%{ -const n={begin:/<\/?[A-Za-z_]/,end:">",subLanguage:"xml",relevance:0},t={ -variants:[{begin:/\[.+?\]\[.*?\]/,relevance:0},{ -begin:/\[.+?\]\(((data|javascript|mailto):|(?:http|ftp)s?:\/\/).*?\)/, -relevance:2},{ -begin:e.regex.concat(/\[.+?\]\(/,/[A-Za-z][A-Za-z0-9+.-]*/,/:\/\/.*?\)/), -relevance:2},{begin:/\[.+?\]\([./?&#].*?\)/,relevance:1},{ -begin:/\[.*?\]\(.*?\)/,relevance:0}],returnBegin:!0,contains:[{match:/\[(?=\])/ -},{className:"string",relevance:0,begin:"\\[",end:"\\]",excludeBegin:!0, -returnEnd:!0},{className:"link",relevance:0,begin:"\\]\\(",end:"\\)", -excludeBegin:!0,excludeEnd:!0},{className:"symbol",relevance:0,begin:"\\]\\[", -end:"\\]",excludeBegin:!0,excludeEnd:!0}]},a={className:"strong",contains:[], -variants:[{begin:/_{2}(?!\s)/,end:/_{2}/},{begin:/\*{2}(?!\s)/,end:/\*{2}/}] -},i={className:"emphasis",contains:[],variants:[{begin:/\*(?![*\s])/,end:/\*/},{ -begin:/_(?![_\s])/,end:/_/,relevance:0}]},r=e.inherit(a,{contains:[] -}),s=e.inherit(i,{contains:[]});a.contains.push(s),i.contains.push(r) -;let o=[n,t];return[a,i,r,s].forEach((e=>{e.contains=e.contains.concat(o) -})),o=o.concat(a,i),{name:"Markdown",aliases:["md","mkdown","mkd"],contains:[{ -className:"section",variants:[{begin:"^#{1,6}",end:"$",contains:o},{ -begin:"(?=^.+?\\n[=-]{2,}$)",contains:[{begin:"^[=-]*$"},{begin:"^",end:"\\n", -contains:o}]}]},n,{className:"bullet",begin:"^[ \t]*([*+-]|(\\d+\\.))(?=\\s+)", -end:"\\s+",excludeEnd:!0},a,i,{className:"quote",begin:"^>\\s+",contains:o, -end:"$"},{className:"code",variants:[{begin:"(`{3,})[^`](.|\\n)*?\\1`*[ ]*"},{ -begin:"(~{3,})[^~](.|\\n)*?\\1~*[ ]*"},{begin:"```",end:"```+[ ]*$"},{ -begin:"~~~",end:"~~~+[ ]*$"},{begin:"`.+?`"},{begin:"(?=^( {4}|\\t))", -contains:[{begin:"^( {4}|\\t)",end:"(\\n)$"}],relevance:0}]},{ -begin:"^[-\\*]{3,}",end:"$"},t,{begin:/^\[[^\n]+\]:/,returnBegin:!0,contains:[{ -className:"symbol",begin:/\[/,end:/\]/,excludeBegin:!0,excludeEnd:!0},{ -className:"link",begin:/:\s*/,end:/$/,excludeBegin:!0}]},{scope:"literal", -match:/&([a-zA-Z0-9]+|#[0-9]{1,7}|#[Xx][0-9a-fA-F]{1,6});/}]}}, -grmr_objectivec:e=>{const n=/[a-zA-Z@][a-zA-Z0-9_]*/,t={$pattern:n, -keyword:["@interface","@class","@protocol","@implementation"]};return{ -name:"Objective-C",aliases:["mm","objc","obj-c","obj-c++","objective-c++"], -keywords:{"variable.language":["this","super"],$pattern:n, -keyword:["while","export","sizeof","typedef","const","struct","for","union","volatile","static","mutable","if","do","return","goto","enum","else","break","extern","asm","case","default","register","explicit","typename","switch","continue","inline","readonly","assign","readwrite","self","@synchronized","id","typeof","nonatomic","IBOutlet","IBAction","strong","weak","copy","in","out","inout","bycopy","byref","oneway","__strong","__weak","__block","__autoreleasing","@private","@protected","@public","@try","@property","@end","@throw","@catch","@finally","@autoreleasepool","@synthesize","@dynamic","@selector","@optional","@required","@encode","@package","@import","@defs","@compatibility_alias","__bridge","__bridge_transfer","__bridge_retained","__bridge_retain","__covariant","__contravariant","__kindof","_Nonnull","_Nullable","_Null_unspecified","__FUNCTION__","__PRETTY_FUNCTION__","__attribute__","getter","setter","retain","unsafe_unretained","nonnull","nullable","null_unspecified","null_resettable","class","instancetype","NS_DESIGNATED_INITIALIZER","NS_UNAVAILABLE","NS_REQUIRES_SUPER","NS_RETURNS_INNER_POINTER","NS_INLINE","NS_AVAILABLE","NS_DEPRECATED","NS_ENUM","NS_OPTIONS","NS_SWIFT_UNAVAILABLE","NS_ASSUME_NONNULL_BEGIN","NS_ASSUME_NONNULL_END","NS_REFINED_FOR_SWIFT","NS_SWIFT_NAME","NS_SWIFT_NOTHROW","NS_DURING","NS_HANDLER","NS_ENDHANDLER","NS_VALUERETURN","NS_VOIDRETURN"], -literal:["false","true","FALSE","TRUE","nil","YES","NO","NULL"], -built_in:["dispatch_once_t","dispatch_queue_t","dispatch_sync","dispatch_async","dispatch_once"], -type:["int","float","char","unsigned","signed","short","long","double","wchar_t","unichar","void","bool","BOOL","id|0","_Bool"] -},illegal:"/,end:/$/,illegal:"\\n" -},e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE]},{className:"class", -begin:"("+t.keyword.join("|")+")\\b",end:/(\{|$)/,excludeEnd:!0,keywords:t, -contains:[e.UNDERSCORE_TITLE_MODE]},{begin:"\\."+e.UNDERSCORE_IDENT_RE, -relevance:0}]}},grmr_perl:e=>{const n=e.regex,t=/[dualxmsipngr]{0,12}/,a={ -$pattern:/[\w.]+/, -keyword:"abs accept alarm and atan2 bind binmode bless break caller chdir chmod chomp chop chown chr chroot class close closedir connect continue cos crypt dbmclose dbmopen defined delete die do dump each else elsif endgrent endhostent endnetent endprotoent endpwent endservent eof eval exec exists exit exp fcntl field fileno flock for foreach fork format formline getc getgrent getgrgid getgrnam gethostbyaddr gethostbyname gethostent getlogin getnetbyaddr getnetbyname getnetent getpeername getpgrp getpriority getprotobyname getprotobynumber getprotoent getpwent getpwnam getpwuid getservbyname getservbyport getservent getsockname getsockopt given glob gmtime goto grep gt hex if index int ioctl join keys kill last lc lcfirst length link listen local localtime log lstat lt ma map method mkdir msgctl msgget msgrcv msgsnd my ne next no not oct open opendir or ord our pack package pipe pop pos print printf prototype push q|0 qq quotemeta qw qx rand read readdir readline readlink readpipe recv redo ref rename require reset return reverse rewinddir rindex rmdir say scalar seek seekdir select semctl semget semop send setgrent sethostent setnetent setpgrp setpriority setprotoent setpwent setservent setsockopt shift shmctl shmget shmread shmwrite shutdown sin sleep socket socketpair sort splice split sprintf sqrt srand stat state study sub substr symlink syscall sysopen sysread sysseek system syswrite tell telldir tie tied time times tr truncate uc ucfirst umask undef unless unlink unpack unshift untie until use utime values vec wait waitpid wantarray warn when while write x|0 xor y|0" -},i={className:"subst",begin:"[$@]\\{",end:"\\}",keywords:a},r={begin:/->\{/, -end:/\}/},s={scope:"attr",match:/\s+:\s*\w+(\s*\(.*?\))?/},o={scope:"variable", -variants:[{begin:/\$\d/},{ -begin:n.concat(/[$%@](?!")(\^\w\b|#\w+(::\w+)*|\{\w+\}|\w+(::\w*)*)/,"(?![A-Za-z])(?![@$%])") -},{begin:/[$%@](?!")[^\s\w{=]|\$=/,relevance:0}],contains:[s]},l={ -className:"number",variants:[{match:/0?\.[0-9][0-9_]+\b/},{ -match:/\bv?(0|[1-9][0-9_]*(\.[0-9_]+)?|[1-9][0-9_]*)\b/},{ -match:/\b0[0-7][0-7_]*\b/},{match:/\b0x[0-9a-fA-F][0-9a-fA-F_]*\b/},{ -match:/\b0b[0-1][0-1_]*\b/}],relevance:0 -},c=[e.BACKSLASH_ESCAPE,i,o],d=[/!/,/\//,/\|/,/\?/,/'/,/"/,/#/],g=(e,a,i="\\1")=>{ -const r="\\1"===i?i:n.concat(i,a) -;return n.concat(n.concat("(?:",e,")"),a,/(?:\\.|[^\\\/])*?/,r,/(?:\\.|[^\\\/])*?/,i,t) -},u=(e,a,i)=>n.concat(n.concat("(?:",e,")"),a,/(?:\\.|[^\\\/])*?/,i,t),b=[o,e.HASH_COMMENT_MODE,e.COMMENT(/^=\w/,/=cut/,{ -endsWithParent:!0}),r,{className:"string",contains:c,variants:[{ -begin:"q[qwxr]?\\s*\\(",end:"\\)",relevance:5},{begin:"q[qwxr]?\\s*\\[", -end:"\\]",relevance:5},{begin:"q[qwxr]?\\s*\\{",end:"\\}",relevance:5},{ -begin:"q[qwxr]?\\s*\\|",end:"\\|",relevance:5},{begin:"q[qwxr]?\\s*<",end:">", -relevance:5},{begin:"qw\\s+q",end:"q",relevance:5},{begin:"'",end:"'", -contains:[e.BACKSLASH_ESCAPE]},{begin:'"',end:'"'},{begin:"`",end:"`", -contains:[e.BACKSLASH_ESCAPE]},{begin:/\{\w+\}/,relevance:0},{ -begin:"-?\\w+\\s*=>",relevance:0}]},l,{ -begin:"(\\/\\/|"+e.RE_STARTERS_RE+"|\\b(split|return|print|reverse|grep)\\b)\\s*", -keywords:"split return print reverse grep",relevance:0, -contains:[e.HASH_COMMENT_MODE,{className:"regexp",variants:[{ -begin:g("s|tr|y",n.either(...d,{capture:!0}))},{begin:g("s|tr|y","\\(","\\)")},{ -begin:g("s|tr|y","\\[","\\]")},{begin:g("s|tr|y","\\{","\\}")}],relevance:2},{ -className:"regexp",variants:[{begin:/(m|qr)\/\//,relevance:0},{ -begin:u("(?:m|qr)?",/\//,/\//)},{begin:u("m|qr",n.either(...d,{capture:!0 -}),/\1/)},{begin:u("m|qr",/\(/,/\)/)},{begin:u("m|qr",/\[/,/\]/)},{ -begin:u("m|qr",/\{/,/\}/)}]}]},{className:"function",beginKeywords:"sub method", -end:"(\\s*\\(.*?\\))?[;{]",excludeEnd:!0,relevance:5,contains:[e.TITLE_MODE,s] -},{className:"class",beginKeywords:"class",end:"[;{]",excludeEnd:!0,relevance:5, -contains:[e.TITLE_MODE,s,l]},{begin:"-\\w\\b",relevance:0},{begin:"^__DATA__$", -end:"^__END__$",subLanguage:"mojolicious",contains:[{begin:"^@@.*",end:"$", -className:"comment"}]}];return i.contains=b,r.contains=b,{name:"Perl", -aliases:["pl","pm"],keywords:a,contains:b}},grmr_php:e=>{ -const n=e.regex,t=/(?![A-Za-z0-9])(?![$])/,a=n.concat(/[a-zA-Z_\x7f-\xff][a-zA-Z0-9_\x7f-\xff]*/,t),i=n.concat(/(\\?[A-Z][a-z0-9_\x7f-\xff]+|\\?[A-Z]+(?=[A-Z][a-z0-9_\x7f-\xff])){1,}/,t),r={ -scope:"variable",match:"\\$+"+a},s={scope:"subst",variants:[{begin:/\$\w+/},{ -begin:/\{\$/,end:/\}/}]},o=e.inherit(e.APOS_STRING_MODE,{illegal:null -}),l="[ \t\n]",c={scope:"string",variants:[e.inherit(e.QUOTE_STRING_MODE,{ -illegal:null,contains:e.QUOTE_STRING_MODE.contains.concat(s)}),o,{ -begin:/<<<[ \t]*(?:(\w+)|"(\w+)")\n/,end:/[ \t]*(\w+)\b/, -contains:e.QUOTE_STRING_MODE.contains.concat(s),"on:begin":(e,n)=>{ -n.data._beginMatch=e[1]||e[2]},"on:end":(e,n)=>{ -n.data._beginMatch!==e[1]&&n.ignoreMatch()}},e.END_SAME_AS_BEGIN({ -begin:/<<<[ \t]*'(\w+)'\n/,end:/[ \t]*(\w+)\b/})]},d={scope:"number",variants:[{ -begin:"\\b0[bB][01]+(?:_[01]+)*\\b"},{begin:"\\b0[oO][0-7]+(?:_[0-7]+)*\\b"},{ -begin:"\\b0[xX][\\da-fA-F]+(?:_[\\da-fA-F]+)*\\b"},{ -begin:"(?:\\b\\d+(?:_\\d+)*(\\.(?:\\d+(?:_\\d+)*))?|\\B\\.\\d+)(?:[eE][+-]?\\d+)?" -}],relevance:0 -},g=["false","null","true"],u=["__CLASS__","__DIR__","__FILE__","__FUNCTION__","__COMPILER_HALT_OFFSET__","__LINE__","__METHOD__","__NAMESPACE__","__TRAIT__","die","echo","exit","include","include_once","print","require","require_once","array","abstract","and","as","binary","bool","boolean","break","callable","case","catch","class","clone","const","continue","declare","default","do","double","else","elseif","empty","enddeclare","endfor","endforeach","endif","endswitch","endwhile","enum","eval","extends","final","finally","float","for","foreach","from","global","goto","if","implements","instanceof","insteadof","int","integer","interface","isset","iterable","list","match|0","mixed","new","never","object","or","private","protected","public","readonly","real","return","string","switch","throw","trait","try","unset","use","var","void","while","xor","yield"],b=["Error|0","AppendIterator","ArgumentCountError","ArithmeticError","ArrayIterator","ArrayObject","AssertionError","BadFunctionCallException","BadMethodCallException","CachingIterator","CallbackFilterIterator","CompileError","Countable","DirectoryIterator","DivisionByZeroError","DomainException","EmptyIterator","ErrorException","Exception","FilesystemIterator","FilterIterator","GlobIterator","InfiniteIterator","InvalidArgumentException","IteratorIterator","LengthException","LimitIterator","LogicException","MultipleIterator","NoRewindIterator","OutOfBoundsException","OutOfRangeException","OuterIterator","OverflowException","ParentIterator","ParseError","RangeException","RecursiveArrayIterator","RecursiveCachingIterator","RecursiveCallbackFilterIterator","RecursiveDirectoryIterator","RecursiveFilterIterator","RecursiveIterator","RecursiveIteratorIterator","RecursiveRegexIterator","RecursiveTreeIterator","RegexIterator","RuntimeException","SeekableIterator","SplDoublyLinkedList","SplFileInfo","SplFileObject","SplFixedArray","SplHeap","SplMaxHeap","SplMinHeap","SplObjectStorage","SplObserver","SplPriorityQueue","SplQueue","SplStack","SplSubject","SplTempFileObject","TypeError","UnderflowException","UnexpectedValueException","UnhandledMatchError","ArrayAccess","BackedEnum","Closure","Fiber","Generator","Iterator","IteratorAggregate","Serializable","Stringable","Throwable","Traversable","UnitEnum","WeakReference","WeakMap","Directory","__PHP_Incomplete_Class","parent","php_user_filter","self","static","stdClass"],m={ -keyword:u,literal:(e=>{const n=[];return e.forEach((e=>{ -n.push(e),e.toLowerCase()===e?n.push(e.toUpperCase()):n.push(e.toLowerCase()) -})),n})(g),built_in:b},p=e=>e.map((e=>e.replace(/\|\d+$/,""))),_={variants:[{ -match:[/new/,n.concat(l,"+"),n.concat("(?!",p(b).join("\\b|"),"\\b)"),i],scope:{ -1:"keyword",4:"title.class"}}]},h=n.concat(a,"\\b(?!\\()"),f={variants:[{ -match:[n.concat(/::/,n.lookahead(/(?!class\b)/)),h],scope:{2:"variable.constant" -}},{match:[/::/,/class/],scope:{2:"variable.language"}},{ -match:[i,n.concat(/::/,n.lookahead(/(?!class\b)/)),h],scope:{1:"title.class", -3:"variable.constant"}},{match:[i,n.concat("::",n.lookahead(/(?!class\b)/))], -scope:{1:"title.class"}},{match:[i,/::/,/class/],scope:{1:"title.class", -3:"variable.language"}}]},E={scope:"attr", -match:n.concat(a,n.lookahead(":"),n.lookahead(/(?!::)/))},y={relevance:0, -begin:/\(/,end:/\)/,keywords:m,contains:[E,r,f,e.C_BLOCK_COMMENT_MODE,c,d,_] -},w={relevance:0, -match:[/\b/,n.concat("(?!fn\\b|function\\b|",p(u).join("\\b|"),"|",p(b).join("\\b|"),"\\b)"),a,n.concat(l,"*"),n.lookahead(/(?=\()/)], -scope:{3:"title.function.invoke"},contains:[y]};y.contains.push(w) -;const N=[E,f,e.C_BLOCK_COMMENT_MODE,c,d,_];return{case_insensitive:!1, -keywords:m,contains:[{begin:n.concat(/#\[\s*/,i),beginScope:"meta",end:/]/, -endScope:"meta",keywords:{literal:g,keyword:["new","array"]},contains:[{ -begin:/\[/,end:/]/,keywords:{literal:g,keyword:["new","array"]}, -contains:["self",...N]},...N,{scope:"meta",match:i}] -},e.HASH_COMMENT_MODE,e.COMMENT("//","$"),e.COMMENT("/\\*","\\*/",{contains:[{ -scope:"doctag",match:"@[A-Za-z]+"}]}),{match:/__halt_compiler\(\);/, -keywords:"__halt_compiler",starts:{scope:"comment",end:e.MATCH_NOTHING_RE, -contains:[{match:/\?>/,scope:"meta",endsParent:!0}]}},{scope:"meta",variants:[{ -begin:/<\?php/,relevance:10},{begin:/<\?=/},{begin:/<\?/,relevance:.1},{ -begin:/\?>/}]},{scope:"variable.language",match:/\$this\b/},r,w,f,{ -match:[/const/,/\s/,a],scope:{1:"keyword",3:"variable.constant"}},_,{ -scope:"function",relevance:0,beginKeywords:"fn function",end:/[;{]/, -excludeEnd:!0,illegal:"[$%\\[]",contains:[{beginKeywords:"use" -},e.UNDERSCORE_TITLE_MODE,{begin:"=>",endsParent:!0},{scope:"params", -begin:"\\(",end:"\\)",excludeBegin:!0,excludeEnd:!0,keywords:m, -contains:["self",r,f,e.C_BLOCK_COMMENT_MODE,c,d]}]},{scope:"class",variants:[{ -beginKeywords:"enum",illegal:/[($"]/},{beginKeywords:"class interface trait", -illegal:/[:($"]/}],relevance:0,end:/\{/,excludeEnd:!0,contains:[{ -beginKeywords:"extends implements"},e.UNDERSCORE_TITLE_MODE]},{ -beginKeywords:"namespace",relevance:0,end:";",illegal:/[.']/, -contains:[e.inherit(e.UNDERSCORE_TITLE_MODE,{scope:"title.class"})]},{ -beginKeywords:"use",relevance:0,end:";",contains:[{ -match:/\b(as|const|function)\b/,scope:"keyword"},e.UNDERSCORE_TITLE_MODE]},c,d]} -},grmr_php_template:e=>({name:"PHP template",subLanguage:"xml",contains:[{ -begin:/<\?(php|=)?/,end:/\?>/,subLanguage:"php",contains:[{begin:"/\\*", -end:"\\*/",skip:!0},{begin:'b"',end:'"',skip:!0},{begin:"b'",end:"'",skip:!0 -},e.inherit(e.APOS_STRING_MODE,{illegal:null,className:null,contains:null, -skip:!0}),e.inherit(e.QUOTE_STRING_MODE,{illegal:null,className:null, -contains:null,skip:!0})]}]}),grmr_plaintext:e=>({name:"Plain text", -aliases:["text","txt"],disableAutodetect:!0}),grmr_python:e=>{ -const n=e.regex,t=/[\p{XID_Start}_]\p{XID_Continue}*/u,a=["and","as","assert","async","await","break","case","class","continue","def","del","elif","else","except","finally","for","from","global","if","import","in","is","lambda","match","nonlocal|10","not","or","pass","raise","return","try","while","with","yield"],i={ -$pattern:/[A-Za-z]\w+|__\w+__/,keyword:a, -built_in:["__import__","abs","all","any","ascii","bin","bool","breakpoint","bytearray","bytes","callable","chr","classmethod","compile","complex","delattr","dict","dir","divmod","enumerate","eval","exec","filter","float","format","frozenset","getattr","globals","hasattr","hash","help","hex","id","input","int","isinstance","issubclass","iter","len","list","locals","map","max","memoryview","min","next","object","oct","open","ord","pow","print","property","range","repr","reversed","round","set","setattr","slice","sorted","staticmethod","str","sum","super","tuple","type","vars","zip"], -literal:["__debug__","Ellipsis","False","None","NotImplemented","True"], -type:["Any","Callable","Coroutine","Dict","List","Literal","Generic","Optional","Sequence","Set","Tuple","Type","Union"] -},r={className:"meta",begin:/^(>>>|\.\.\.) /},s={className:"subst",begin:/\{/, -end:/\}/,keywords:i,illegal:/#/},o={begin:/\{\{/,relevance:0},l={ -className:"string",contains:[e.BACKSLASH_ESCAPE],variants:[{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,r],relevance:10},{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?"""/,end:/"""/, -contains:[e.BACKSLASH_ESCAPE,r],relevance:10},{ -begin:/([fF][rR]|[rR][fF]|[fF])'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,r,o,s]},{begin:/([fF][rR]|[rR][fF]|[fF])"""/, -end:/"""/,contains:[e.BACKSLASH_ESCAPE,r,o,s]},{begin:/([uU]|[rR])'/,end:/'/, -relevance:10},{begin:/([uU]|[rR])"/,end:/"/,relevance:10},{ -begin:/([bB]|[bB][rR]|[rR][bB])'/,end:/'/},{begin:/([bB]|[bB][rR]|[rR][bB])"/, -end:/"/},{begin:/([fF][rR]|[rR][fF]|[fF])'/,end:/'/, -contains:[e.BACKSLASH_ESCAPE,o,s]},{begin:/([fF][rR]|[rR][fF]|[fF])"/,end:/"/, -contains:[e.BACKSLASH_ESCAPE,o,s]},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE] -},c="[0-9](_?[0-9])*",d=`(\\b(${c}))?\\.(${c})|\\b(${c})\\.`,g="\\b|"+a.join("|"),u={ -className:"number",relevance:0,variants:[{ -begin:`(\\b(${c})|(${d}))[eE][+-]?(${c})[jJ]?(?=${g})`},{begin:`(${d})[jJ]?`},{ -begin:`\\b([1-9](_?[0-9])*|0+(_?0)*)[lLjJ]?(?=${g})`},{ -begin:`\\b0[bB](_?[01])+[lL]?(?=${g})`},{begin:`\\b0[oO](_?[0-7])+[lL]?(?=${g})` -},{begin:`\\b0[xX](_?[0-9a-fA-F])+[lL]?(?=${g})`},{begin:`\\b(${c})[jJ](?=${g})` -}]},b={className:"comment",begin:n.lookahead(/# type:/),end:/$/,keywords:i, -contains:[{begin:/# type:/},{begin:/#/,end:/\b\B/,endsWithParent:!0}]},m={ -className:"params",variants:[{className:"",begin:/\(\s*\)/,skip:!0},{begin:/\(/, -end:/\)/,excludeBegin:!0,excludeEnd:!0,keywords:i, -contains:["self",r,u,l,e.HASH_COMMENT_MODE]}]};return s.contains=[l,u,r],{ -name:"Python",aliases:["py","gyp","ipython"],unicodeRegex:!0,keywords:i, -illegal:/(<\/|\?)|=>/,contains:[r,u,{scope:"variable.language",match:/\bself\b/ -},{beginKeywords:"if",relevance:0},{match:/\bor\b/,scope:"keyword" -},l,b,e.HASH_COMMENT_MODE,{match:[/\bdef/,/\s+/,t],scope:{1:"keyword", -3:"title.function"},contains:[m]},{variants:[{ -match:[/\bclass/,/\s+/,t,/\s*/,/\(\s*/,t,/\s*\)/]},{match:[/\bclass/,/\s+/,t]}], -scope:{1:"keyword",3:"title.class",6:"title.class.inherited"}},{ -className:"meta",begin:/^[\t ]*@/,end:/(?=#)|$/,contains:[u,m,l]}]}}, -grmr_python_repl:e=>({aliases:["pycon"],contains:[{className:"meta.prompt", -starts:{end:/ |$/,starts:{end:"$",subLanguage:"python"}},variants:[{ -begin:/^>>>(?=[ ]|$)/},{begin:/^\.\.\.(?=[ ]|$)/}]}]}),grmr_r:e=>{ -const n=e.regex,t=/(?:(?:[a-zA-Z]|\.[._a-zA-Z])[._a-zA-Z0-9]*)|\.(?!\d)/,a=n.either(/0[xX][0-9a-fA-F]+\.[0-9a-fA-F]*[pP][+-]?\d+i?/,/0[xX][0-9a-fA-F]+(?:[pP][+-]?\d+)?[Li]?/,/(?:\d+(?:\.\d*)?|\.\d+)(?:[eE][+-]?\d+)?[Li]?/),i=/[=!<>:]=|\|\||&&|:::?|<-|<<-|->>|->|\|>|[-+*\/?!$&|:<=>@^~]|\*\*/,r=n.either(/[()]/,/[{}]/,/\[\[/,/[[\]]/,/\\/,/,/) -;return{name:"R",keywords:{$pattern:t, -keyword:"function if in break next repeat else for while", -literal:"NULL NA TRUE FALSE Inf NaN NA_integer_|10 NA_real_|10 NA_character_|10 NA_complex_|10", -built_in:"LETTERS letters month.abb month.name pi T F abs acos acosh all any anyNA Arg as.call as.character as.complex as.double as.environment as.integer as.logical as.null.default as.numeric as.raw asin asinh atan atanh attr attributes baseenv browser c call ceiling class Conj cos cosh cospi cummax cummin cumprod cumsum digamma dim dimnames emptyenv exp expression floor forceAndCall gamma gc.time globalenv Im interactive invisible is.array is.atomic is.call is.character is.complex is.double is.environment is.expression is.finite is.function is.infinite is.integer is.language is.list is.logical is.matrix is.na is.name is.nan is.null is.numeric is.object is.pairlist is.raw is.recursive is.single is.symbol lazyLoadDBfetch length lgamma list log max min missing Mod names nargs nzchar oldClass on.exit pos.to.env proc.time prod quote range Re rep retracemem return round seq_along seq_len seq.int sign signif sin sinh sinpi sqrt standardGeneric substitute sum switch tan tanh tanpi tracemem trigamma trunc unclass untracemem UseMethod xtfrm" -},contains:[e.COMMENT(/#'/,/$/,{contains:[{scope:"doctag",match:/@examples/, -starts:{end:n.lookahead(n.either(/\n^#'\s*(?=@[a-zA-Z]+)/,/\n^(?!#')/)), -endsParent:!0}},{scope:"doctag",begin:"@param",end:/$/,contains:[{ -scope:"variable",variants:[{match:t},{match:/`(?:\\.|[^`\\])+`/}],endsParent:!0 -}]},{scope:"doctag",match:/@[a-zA-Z]+/},{scope:"keyword",match:/\\[a-zA-Z]+/}] -}),e.HASH_COMMENT_MODE,{scope:"string",contains:[e.BACKSLASH_ESCAPE], -variants:[e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\(/,end:/\)(-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\{/,end:/\}(-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]"(-*)\[/,end:/\](-*)"/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\(/,end:/\)(-*)'/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\{/,end:/\}(-*)'/ -}),e.END_SAME_AS_BEGIN({begin:/[rR]'(-*)\[/,end:/\](-*)'/}),{begin:'"',end:'"', -relevance:0},{begin:"'",end:"'",relevance:0}]},{relevance:0,variants:[{scope:{ -1:"operator",2:"number"},match:[i,a]},{scope:{1:"operator",2:"number"}, -match:[/%[^%]*%/,a]},{scope:{1:"punctuation",2:"number"},match:[r,a]},{scope:{ -2:"number"},match:[/[^a-zA-Z0-9._]|^/,a]}]},{scope:{3:"operator"}, -match:[t,/\s+/,/<-/,/\s+/]},{scope:"operator",relevance:0,variants:[{match:i},{ -match:/%[^%]*%/}]},{scope:"punctuation",relevance:0,match:r},{begin:"`",end:"`", -contains:[{begin:/\\./}]}]}},grmr_ruby:e=>{ -const n=e.regex,t="([a-zA-Z_]\\w*[!?=]?|[-+~]@|<<|>>|=~|===?|<=>|[<>]=?|\\*\\*|[-/+%^&*~`|]|\\[\\]=?)",a=n.either(/\b([A-Z]+[a-z0-9]+)+/,/\b([A-Z]+[a-z0-9]+)+[A-Z]+/),i=n.concat(a,/(::\w+)*/),r={ -"variable.constant":["__FILE__","__LINE__","__ENCODING__"], -"variable.language":["self","super"], -keyword:["alias","and","begin","BEGIN","break","case","class","defined","do","else","elsif","end","END","ensure","for","if","in","module","next","not","or","redo","require","rescue","retry","return","then","undef","unless","until","when","while","yield","include","extend","prepend","public","private","protected","raise","throw"], -built_in:["proc","lambda","attr_accessor","attr_reader","attr_writer","define_method","private_constant","module_function"], -literal:["true","false","nil"]},s={className:"doctag",begin:"@[A-Za-z]+"},o={ -begin:"#<",end:">"},l=[e.COMMENT("#","$",{contains:[s] -}),e.COMMENT("^=begin","^=end",{contains:[s],relevance:10 -}),e.COMMENT("^__END__",e.MATCH_NOTHING_RE)],c={className:"subst",begin:/#\{/, -end:/\}/,keywords:r},d={className:"string",contains:[e.BACKSLASH_ESCAPE,c], -variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/},{begin:/`/,end:/`/},{ -begin:/%[qQwWx]?\(/,end:/\)/},{begin:/%[qQwWx]?\[/,end:/\]/},{ -begin:/%[qQwWx]?\{/,end:/\}/},{begin:/%[qQwWx]?/},{begin:/%[qQwWx]?\//, -end:/\//},{begin:/%[qQwWx]?%/,end:/%/},{begin:/%[qQwWx]?-/,end:/-/},{ -begin:/%[qQwWx]?\|/,end:/\|/},{begin:/\B\?(\\\d{1,3})/},{ -begin:/\B\?(\\x[A-Fa-f0-9]{1,2})/},{begin:/\B\?(\\u\{?[A-Fa-f0-9]{1,6}\}?)/},{ -begin:/\B\?(\\M-\\C-|\\M-\\c|\\c\\M-|\\M-|\\C-\\M-)[\x20-\x7e]/},{ -begin:/\B\?\\(c|C-)[\x20-\x7e]/},{begin:/\B\?\\?\S/},{ -begin:n.concat(/<<[-~]?'?/,n.lookahead(/(\w+)(?=\W)[^\n]*\n(?:[^\n]*\n)*?\s*\1\b/)), -contains:[e.END_SAME_AS_BEGIN({begin:/(\w+)/,end:/(\w+)/, -contains:[e.BACKSLASH_ESCAPE,c]})]}]},g="[0-9](_?[0-9])*",u={className:"number", -relevance:0,variants:[{ -begin:`\\b([1-9](_?[0-9])*|0)(\\.(${g}))?([eE][+-]?(${g})|r)?i?\\b`},{ -begin:"\\b0[dD][0-9](_?[0-9])*r?i?\\b"},{begin:"\\b0[bB][0-1](_?[0-1])*r?i?\\b" -},{begin:"\\b0[oO][0-7](_?[0-7])*r?i?\\b"},{ -begin:"\\b0[xX][0-9a-fA-F](_?[0-9a-fA-F])*r?i?\\b"},{ -begin:"\\b0(_?[0-7])+r?i?\\b"}]},b={variants:[{match:/\(\)/},{ -className:"params",begin:/\(/,end:/(?=\))/,excludeBegin:!0,endsParent:!0, -keywords:r}]},m=[d,{variants:[{match:[/class\s+/,i,/\s+<\s+/,i]},{ -match:[/\b(class|module)\s+/,i]}],scope:{2:"title.class", -4:"title.class.inherited"},keywords:r},{match:[/(include|extend)\s+/,i],scope:{ -2:"title.class"},keywords:r},{relevance:0,match:[i,/\.new[. (]/],scope:{ -1:"title.class"}},{relevance:0,match:/\b[A-Z][A-Z_0-9]+\b/, -className:"variable.constant"},{relevance:0,match:a,scope:"title.class"},{ -match:[/def/,/\s+/,t],scope:{1:"keyword",3:"title.function"},contains:[b]},{ -begin:e.IDENT_RE+"::"},{className:"symbol", -begin:e.UNDERSCORE_IDENT_RE+"(!|\\?)?:",relevance:0},{className:"symbol", -begin:":(?!\\s)",contains:[d,{begin:t}],relevance:0},u,{className:"variable", -begin:"(\\$\\W)|((\\$|@@?)(\\w+))(?=[^@$?])(?![A-Za-z])(?![@$?'])"},{ -className:"params",begin:/\|/,end:/\|/,excludeBegin:!0,excludeEnd:!0, -relevance:0,keywords:r},{begin:"("+e.RE_STARTERS_RE+"|unless)\\s*", -keywords:"unless",contains:[{className:"regexp",contains:[e.BACKSLASH_ESCAPE,c], -illegal:/\n/,variants:[{begin:"/",end:"/[a-z]*"},{begin:/%r\{/,end:/\}[a-z]*/},{ -begin:"%r\\(",end:"\\)[a-z]*"},{begin:"%r!",end:"![a-z]*"},{begin:"%r\\[", -end:"\\][a-z]*"}]}].concat(o,l),relevance:0}].concat(o,l) -;c.contains=m,b.contains=m;const p=[{begin:/^\s*=>/,starts:{end:"$",contains:m} -},{className:"meta.prompt", -begin:"^([>?]>|[\\w#]+\\(\\w+\\):\\d+:\\d+[>*]|(\\w+-)?\\d+\\.\\d+\\.\\d+(p\\d+)?[^\\d][^>]+>)(?=[ ])", -starts:{end:"$",keywords:r,contains:m}}];return l.unshift(o),{name:"Ruby", -aliases:["rb","gemspec","podspec","thor","irb"],keywords:r,illegal:/\/\*/, -contains:[e.SHEBANG({binary:"ruby"})].concat(p).concat(l).concat(m)}}, -grmr_rust:e=>{ -const n=e.regex,t=/(r#)?/,a=n.concat(t,e.UNDERSCORE_IDENT_RE),i=n.concat(t,e.IDENT_RE),r={ -className:"title.function.invoke",relevance:0, -begin:n.concat(/\b/,/(?!let|for|while|if|else|match\b)/,i,n.lookahead(/\s*\(/)) -},s="([ui](8|16|32|64|128|size)|f(32|64))?",o=["drop ","Copy","Send","Sized","Sync","Drop","Fn","FnMut","FnOnce","ToOwned","Clone","Debug","PartialEq","PartialOrd","Eq","Ord","AsRef","AsMut","Into","From","Default","Iterator","Extend","IntoIterator","DoubleEndedIterator","ExactSizeIterator","SliceConcatExt","ToString","assert!","assert_eq!","bitflags!","bytes!","cfg!","col!","concat!","concat_idents!","debug_assert!","debug_assert_eq!","env!","eprintln!","panic!","file!","format!","format_args!","include_bytes!","include_str!","line!","local_data_key!","module_path!","option_env!","print!","println!","select!","stringify!","try!","unimplemented!","unreachable!","vec!","write!","writeln!","macro_rules!","assert_ne!","debug_assert_ne!"],l=["i8","i16","i32","i64","i128","isize","u8","u16","u32","u64","u128","usize","f32","f64","str","char","bool","Box","Option","Result","String","Vec"] -;return{name:"Rust",aliases:["rs"],keywords:{$pattern:e.IDENT_RE+"!?",type:l, -keyword:["abstract","as","async","await","become","box","break","const","continue","crate","do","dyn","else","enum","extern","false","final","fn","for","if","impl","in","let","loop","macro","match","mod","move","mut","override","priv","pub","ref","return","self","Self","static","struct","super","trait","true","try","type","typeof","union","unsafe","unsized","use","virtual","where","while","yield"], -literal:["true","false","Some","None","Ok","Err"],built_in:o},illegal:""},r]}}, -grmr_scss:e=>{const n=ae(e),t=oe,a=se,i="@[a-z-]+",r={className:"variable", -begin:"(\\$[a-zA-Z-][a-zA-Z0-9_-]*)\\b",relevance:0};return{name:"SCSS", -case_insensitive:!0,illegal:"[=/|']", -contains:[e.C_LINE_COMMENT_MODE,e.C_BLOCK_COMMENT_MODE,n.CSS_NUMBER_MODE,{ -className:"selector-id",begin:"#[A-Za-z0-9_-]+",relevance:0},{ -className:"selector-class",begin:"\\.[A-Za-z0-9_-]+",relevance:0 -},n.ATTRIBUTE_SELECTOR_MODE,{className:"selector-tag", -begin:"\\b("+ie.join("|")+")\\b",relevance:0},{className:"selector-pseudo", -begin:":("+a.join("|")+")"},{className:"selector-pseudo", -begin:":(:)?("+t.join("|")+")"},r,{begin:/\(/,end:/\)/, -contains:[n.CSS_NUMBER_MODE]},n.CSS_VARIABLE,{className:"attribute", -begin:"\\b("+le.join("|")+")\\b"},{ -begin:"\\b(whitespace|wait|w-resize|visible|vertical-text|vertical-ideographic|uppercase|upper-roman|upper-alpha|underline|transparent|top|thin|thick|text|text-top|text-bottom|tb-rl|table-header-group|table-footer-group|sw-resize|super|strict|static|square|solid|small-caps|separate|se-resize|scroll|s-resize|rtl|row-resize|ridge|right|repeat|repeat-y|repeat-x|relative|progress|pointer|overline|outside|outset|oblique|nowrap|not-allowed|normal|none|nw-resize|no-repeat|no-drop|newspaper|ne-resize|n-resize|move|middle|medium|ltr|lr-tb|lowercase|lower-roman|lower-alpha|loose|list-item|line|line-through|line-edge|lighter|left|keep-all|justify|italic|inter-word|inter-ideograph|inside|inset|inline|inline-block|inherit|inactive|ideograph-space|ideograph-parenthesis|ideograph-numeric|ideograph-alpha|horizontal|hidden|help|hand|groove|fixed|ellipsis|e-resize|double|dotted|distribute|distribute-space|distribute-letter|distribute-all-lines|disc|disabled|default|decimal|dashed|crosshair|collapse|col-resize|circle|char|center|capitalize|break-word|break-all|bottom|both|bolder|bold|block|bidi-override|below|baseline|auto|always|all-scroll|absolute|table|table-cell)\\b" -},{begin:/:/,end:/[;}{]/,relevance:0, -contains:[n.BLOCK_COMMENT,r,n.HEXCOLOR,n.CSS_NUMBER_MODE,e.QUOTE_STRING_MODE,e.APOS_STRING_MODE,n.IMPORTANT,n.FUNCTION_DISPATCH] -},{begin:"@(page|font-face)",keywords:{$pattern:i,keyword:"@page @font-face"}},{ -begin:"@",end:"[{;]",returnBegin:!0,keywords:{$pattern:/[a-z-]+/, -keyword:"and or not only",attribute:re.join(" ")},contains:[{begin:i, -className:"keyword"},{begin:/[a-z-]+(?=:)/,className:"attribute" -},r,e.QUOTE_STRING_MODE,e.APOS_STRING_MODE,n.HEXCOLOR,n.CSS_NUMBER_MODE] -},n.FUNCTION_DISPATCH]}},grmr_shell:e=>({name:"Shell Session", -aliases:["console","shellsession"],contains:[{className:"meta.prompt", -begin:/^\s{0,3}[/~\w\d[\]()@-]*[>%$#][ ]?/,starts:{end:/[^\\](?=\s*$)/, -subLanguage:"bash"}}]}),grmr_sql:e=>{ -const n=e.regex,t=e.COMMENT("--","$"),a=["true","false","unknown"],i=["bigint","binary","blob","boolean","char","character","clob","date","dec","decfloat","decimal","float","int","integer","interval","nchar","nclob","national","numeric","real","row","smallint","time","timestamp","varchar","varying","varbinary"],r=["abs","acos","array_agg","asin","atan","avg","cast","ceil","ceiling","coalesce","corr","cos","cosh","count","covar_pop","covar_samp","cume_dist","dense_rank","deref","element","exp","extract","first_value","floor","json_array","json_arrayagg","json_exists","json_object","json_objectagg","json_query","json_table","json_table_primitive","json_value","lag","last_value","lead","listagg","ln","log","log10","lower","max","min","mod","nth_value","ntile","nullif","percent_rank","percentile_cont","percentile_disc","position","position_regex","power","rank","regr_avgx","regr_avgy","regr_count","regr_intercept","regr_r2","regr_slope","regr_sxx","regr_sxy","regr_syy","row_number","sin","sinh","sqrt","stddev_pop","stddev_samp","substring","substring_regex","sum","tan","tanh","translate","translate_regex","treat","trim","trim_array","unnest","upper","value_of","var_pop","var_samp","width_bucket"],s=["create table","insert into","primary key","foreign key","not null","alter table","add constraint","grouping sets","on overflow","character set","respect nulls","ignore nulls","nulls first","nulls last","depth first","breadth first"],o=r,l=["abs","acos","all","allocate","alter","and","any","are","array","array_agg","array_max_cardinality","as","asensitive","asin","asymmetric","at","atan","atomic","authorization","avg","begin","begin_frame","begin_partition","between","bigint","binary","blob","boolean","both","by","call","called","cardinality","cascaded","case","cast","ceil","ceiling","char","char_length","character","character_length","check","classifier","clob","close","coalesce","collate","collect","column","commit","condition","connect","constraint","contains","convert","copy","corr","corresponding","cos","cosh","count","covar_pop","covar_samp","create","cross","cube","cume_dist","current","current_catalog","current_date","current_default_transform_group","current_path","current_role","current_row","current_schema","current_time","current_timestamp","current_path","current_role","current_transform_group_for_type","current_user","cursor","cycle","date","day","deallocate","dec","decimal","decfloat","declare","default","define","delete","dense_rank","deref","describe","deterministic","disconnect","distinct","double","drop","dynamic","each","element","else","empty","end","end_frame","end_partition","end-exec","equals","escape","every","except","exec","execute","exists","exp","external","extract","false","fetch","filter","first_value","float","floor","for","foreign","frame_row","free","from","full","function","fusion","get","global","grant","group","grouping","groups","having","hold","hour","identity","in","indicator","initial","inner","inout","insensitive","insert","int","integer","intersect","intersection","interval","into","is","join","json_array","json_arrayagg","json_exists","json_object","json_objectagg","json_query","json_table","json_table_primitive","json_value","lag","language","large","last_value","lateral","lead","leading","left","like","like_regex","listagg","ln","local","localtime","localtimestamp","log","log10","lower","match","match_number","match_recognize","matches","max","member","merge","method","min","minute","mod","modifies","module","month","multiset","national","natural","nchar","nclob","new","no","none","normalize","not","nth_value","ntile","null","nullif","numeric","octet_length","occurrences_regex","of","offset","old","omit","on","one","only","open","or","order","out","outer","over","overlaps","overlay","parameter","partition","pattern","per","percent","percent_rank","percentile_cont","percentile_disc","period","portion","position","position_regex","power","precedes","precision","prepare","primary","procedure","ptf","range","rank","reads","real","recursive","ref","references","referencing","regr_avgx","regr_avgy","regr_count","regr_intercept","regr_r2","regr_slope","regr_sxx","regr_sxy","regr_syy","release","result","return","returns","revoke","right","rollback","rollup","row","row_number","rows","running","savepoint","scope","scroll","search","second","seek","select","sensitive","session_user","set","show","similar","sin","sinh","skip","smallint","some","specific","specifictype","sql","sqlexception","sqlstate","sqlwarning","sqrt","start","static","stddev_pop","stddev_samp","submultiset","subset","substring","substring_regex","succeeds","sum","symmetric","system","system_time","system_user","table","tablesample","tan","tanh","then","time","timestamp","timezone_hour","timezone_minute","to","trailing","translate","translate_regex","translation","treat","trigger","trim","trim_array","true","truncate","uescape","union","unique","unknown","unnest","update","upper","user","using","value","values","value_of","var_pop","var_samp","varbinary","varchar","varying","versioning","when","whenever","where","width_bucket","window","with","within","without","year","add","asc","collation","desc","final","first","last","view"].filter((e=>!r.includes(e))),c={ -begin:n.concat(/\b/,n.either(...o),/\s*\(/),relevance:0,keywords:{built_in:o}} -;return{name:"SQL",case_insensitive:!0,illegal:/[{}]|<\//,keywords:{ -$pattern:/\b[\w\.]+/,keyword:((e,{exceptions:n,when:t}={})=>{const a=t -;return n=n||[],e.map((e=>e.match(/\|\d+$/)||n.includes(e)?e:a(e)?e+"|0":e)) -})(l,{when:e=>e.length<3}),literal:a,type:i, -built_in:["current_catalog","current_date","current_default_transform_group","current_path","current_role","current_schema","current_transform_group_for_type","current_user","session_user","system_time","system_user","current_time","localtime","current_timestamp","localtimestamp"] -},contains:[{begin:n.either(...s),relevance:0,keywords:{$pattern:/[\w\.]+/, -keyword:l.concat(s),literal:a,type:i}},{className:"type", -begin:n.either("double precision","large object","with timezone","without timezone") -},c,{className:"variable",begin:/@[a-z0-9][a-z0-9_]*/},{className:"string", -variants:[{begin:/'/,end:/'/,contains:[{begin:/''/}]}]},{begin:/"/,end:/"/, -contains:[{begin:/""/}]},e.C_NUMBER_MODE,e.C_BLOCK_COMMENT_MODE,t,{ -className:"operator",begin:/[-+*/=%^~]|&&?|\|\|?|!=?|<(?:=>?|<|>)?|>[>=]?/, -relevance:0}]}},grmr_swift:e=>{const n={match:/\s+/,relevance:0 -},t=e.COMMENT("/\\*","\\*/",{contains:["self"]}),a=[e.C_LINE_COMMENT_MODE,t],i={ -match:[/\./,m(...xe,...Oe)],className:{2:"keyword"}},r={match:b(/\./,m(...Ae)), -relevance:0},s=Ae.filter((e=>"string"==typeof e)).concat(["_|0"]),o={variants:[{ -className:"keyword", -match:m(...Ae.filter((e=>"string"!=typeof e)).concat(Me).map(ke),...Oe)}]},l={ -$pattern:m(/\b\w+/,/#\w+/),keyword:s.concat(Te),literal:Se},c=[i,r,o],g=[{ -match:b(/\./,m(...Re)),relevance:0},{className:"built_in", -match:b(/\b/,m(...Re),/(?=\()/)}],u={match:/->/,relevance:0},p=[u,{ -className:"operator",relevance:0,variants:[{match:Le},{match:`\\.(\\.|${Ie})+`}] -}],_="([0-9]_*)+",h="([0-9a-fA-F]_*)+",f={className:"number",relevance:0, -variants:[{match:`\\b(${_})(\\.(${_}))?([eE][+-]?(${_}))?\\b`},{ -match:`\\b0x(${h})(\\.(${h}))?([pP][+-]?(${_}))?\\b`},{match:/\b0o([0-7]_*)+\b/ -},{match:/\b0b([01]_*)+\b/}]},E=(e="")=>({className:"subst",variants:[{ -match:b(/\\/,e,/[0\\tnr"']/)},{match:b(/\\/,e,/u\{[0-9a-fA-F]{1,8}\}/)}] -}),y=(e="")=>({className:"subst",match:b(/\\/,e,/[\t ]*(?:[\r\n]|\r\n)/) -}),w=(e="")=>({className:"subst",label:"interpol",begin:b(/\\/,e,/\(/),end:/\)/ -}),N=(e="")=>({begin:b(e,/"""/),end:b(/"""/,e),contains:[E(e),y(e),w(e)] -}),v=(e="")=>({begin:b(e,/"/),end:b(/"/,e),contains:[E(e),w(e)]}),k={ -className:"string", -variants:[N(),N("#"),N("##"),N("###"),v(),v("#"),v("##"),v("###")] -},x=[e.BACKSLASH_ESCAPE,{begin:/\[/,end:/\]/,relevance:0, -contains:[e.BACKSLASH_ESCAPE]}],O={begin:/\/[^\s](?=[^/\n]*\/)/,end:/\//, -contains:x},M=e=>{const n=b(e,/\//),t=b(/\//,e);return{begin:n,end:t, -contains:[...x,{scope:"comment",begin:`#(?!.*${t})`,end:/$/}]}},A={ -scope:"regexp",variants:[M("###"),M("##"),M("#"),O]},S={match:b(/`/,Fe,/`/) -},C=[S,{className:"variable",match:/\$\d+/},{className:"variable", -match:`\\$${$e}+`}],T=[{match:/(@|#(un)?)available/,scope:"keyword",starts:{ -contains:[{begin:/\(/,end:/\)/,keywords:Ue,contains:[...p,f,k]}]}},{ -scope:"keyword",match:b(/@/,m(...je),d(m(/\(/,/\s+/)))},{scope:"meta", -match:b(/@/,Fe)}],R={match:d(/\b[A-Z]/),relevance:0,contains:[{className:"type", -match:b(/(AV|CA|CF|CG|CI|CL|CM|CN|CT|MK|MP|MTK|MTL|NS|SCN|SK|UI|WK|XC)/,$e,"+") -},{className:"type",match:ze,relevance:0},{match:/[?!]+/,relevance:0},{ -match:/\.\.\./,relevance:0},{match:b(/\s+&\s+/,d(ze)),relevance:0}]},D={ -begin://,keywords:l,contains:[...a,...c,...T,u,R]};R.contains.push(D) -;const I={begin:/\(/,end:/\)/,relevance:0,keywords:l,contains:["self",{ -match:b(Fe,/\s*:/),keywords:"_|0",relevance:0 -},...a,A,...c,...g,...p,f,k,...C,...T,R]},L={begin://, -keywords:"repeat each",contains:[...a,R]},B={begin:/\(/,end:/\)/,keywords:l, -contains:[{begin:m(d(b(Fe,/\s*:/)),d(b(Fe,/\s+/,Fe,/\s*:/))),end:/:/, -relevance:0,contains:[{className:"keyword",match:/\b_\b/},{className:"params", -match:Fe}]},...a,...c,...p,f,k,...T,R,I],endsParent:!0,illegal:/["']/},$={ -match:[/(func|macro)/,/\s+/,m(S.match,Fe,Le)],className:{1:"keyword", -3:"title.function"},contains:[L,B,n],illegal:[/\[/,/%/]},F={ -match:[/\b(?:subscript|init[?!]?)/,/\s*(?=[<(])/],className:{1:"keyword"}, -contains:[L,B,n],illegal:/\[|%/},z={match:[/operator/,/\s+/,Le],className:{ -1:"keyword",3:"title"}},j={begin:[/precedencegroup/,/\s+/,ze],className:{ -1:"keyword",3:"title"},contains:[R],keywords:[...Ce,...Se],end:/}/},U={ -begin:[/(struct|protocol|class|extension|enum|actor)/,/\s+/,Fe,/\s*/], -beginScope:{1:"keyword",3:"title.class"},keywords:l,contains:[L,...c,{begin:/:/, -end:/\{/,keywords:l,contains:[{scope:"title.class.inherited",match:ze},...c], -relevance:0}]};for(const e of k.variants){ -const n=e.contains.find((e=>"interpol"===e.label));n.keywords=l -;const t=[...c,...g,...p,f,k,...C];n.contains=[...t,{begin:/\(/,end:/\)/, -contains:["self",...t]}]}return{name:"Swift",keywords:l, -contains:[...a,$,F,U,z,j,{beginKeywords:"import",end:/$/,contains:[...a], -relevance:0},A,...c,...g,...p,f,k,...C,...T,R,I]}},grmr_typescript:e=>{ -const n=ve(e),t=pe,a=["any","void","number","boolean","string","object","never","symbol","bigint","unknown"],i={ -begin:[/namespace/,/\s+/,e.IDENT_RE],beginScope:{1:"keyword",3:"title.class"} -},r={beginKeywords:"interface",end:/\{/,excludeEnd:!0,keywords:{ -keyword:"interface extends",built_in:a},contains:[n.exports.CLASS_REFERENCE] -},s={$pattern:pe, -keyword:_e.concat(["type","interface","public","private","protected","implements","declare","abstract","readonly","enum","override","satisfies"]), -literal:he,built_in:Ne.concat(a),"variable.language":we},o={className:"meta", -begin:"@"+t},l=(e,n,t)=>{const a=e.contains.findIndex((e=>e.label===n)) -;if(-1===a)throw Error("can not find mode to replace");e.contains.splice(a,1,t)} -;Object.assign(n.keywords,s),n.exports.PARAMS_CONTAINS.push(o) -;const c=n.contains.find((e=>"attr"===e.className)) -;return n.exports.PARAMS_CONTAINS.push([n.exports.CLASS_REFERENCE,c]), -n.contains=n.contains.concat([o,i,r]), -l(n,"shebang",e.SHEBANG()),l(n,"use_strict",{className:"meta",relevance:10, -begin:/^\s*['"]use strict['"]/ -}),n.contains.find((e=>"func.def"===e.label)).relevance=0,Object.assign(n,{ -name:"TypeScript",aliases:["ts","tsx","mts","cts"]}),n},grmr_vbnet:e=>{ -const n=e.regex,t=/\d{1,2}\/\d{1,2}\/\d{4}/,a=/\d{4}-\d{1,2}-\d{1,2}/,i=/(\d|1[012])(:\d+){0,2} *(AM|PM)/,r=/\d{1,2}(:\d{1,2}){1,2}/,s={ -className:"literal",variants:[{begin:n.concat(/# */,n.either(a,t),/ *#/)},{ -begin:n.concat(/# */,r,/ *#/)},{begin:n.concat(/# */,i,/ *#/)},{ -begin:n.concat(/# */,n.either(a,t),/ +/,n.either(i,r),/ *#/)}] -},o=e.COMMENT(/'''/,/$/,{contains:[{className:"doctag",begin:/<\/?/,end:/>/}] -}),l=e.COMMENT(null,/$/,{variants:[{begin:/'/},{begin:/([\t ]|^)REM(?=\s)/}]}) -;return{name:"Visual Basic .NET",aliases:["vb"],case_insensitive:!0, -classNameAliases:{label:"symbol"},keywords:{ -keyword:"addhandler alias aggregate ansi as async assembly auto binary by byref byval call case catch class compare const continue custom declare default delegate dim distinct do each equals else elseif end enum erase error event exit explicit finally for friend from function get global goto group handles if implements imports in inherits interface into iterator join key let lib loop me mid module mustinherit mustoverride mybase myclass namespace narrowing new next notinheritable notoverridable of off on operator option optional order overloads overridable overrides paramarray partial preserve private property protected public raiseevent readonly redim removehandler resume return select set shadows shared skip static step stop structure strict sub synclock take text then throw to try unicode until using when where while widening with withevents writeonly yield", -built_in:"addressof and andalso await directcast gettype getxmlnamespace is isfalse isnot istrue like mod nameof new not or orelse trycast typeof xor cbool cbyte cchar cdate cdbl cdec cint clng cobj csbyte cshort csng cstr cuint culng cushort", -type:"boolean byte char date decimal double integer long object sbyte short single string uinteger ulong ushort", -literal:"true false nothing"}, -illegal:"//|\\{|\\}|endif|gosub|variant|wend|^\\$ ",contains:[{ -className:"string",begin:/"(""|[^/n])"C\b/},{className:"string",begin:/"/, -end:/"/,illegal:/\n/,contains:[{begin:/""/}]},s,{className:"number",relevance:0, -variants:[{begin:/\b\d[\d_]*((\.[\d_]+(E[+-]?[\d_]+)?)|(E[+-]?[\d_]+))[RFD@!#]?/ -},{begin:/\b\d[\d_]*((U?[SIL])|[%&])?/},{begin:/&H[\dA-F_]+((U?[SIL])|[%&])?/},{ -begin:/&O[0-7_]+((U?[SIL])|[%&])?/},{begin:/&B[01_]+((U?[SIL])|[%&])?/}]},{ -className:"label",begin:/^\w+:/},o,l,{className:"meta", -begin:/[\t ]*#(const|disable|else|elseif|enable|end|externalsource|if|region)\b/, -end:/$/,keywords:{ -keyword:"const disable else elseif enable end externalsource if region then"}, -contains:[l]}]}},grmr_wasm:e=>{e.regex;const n=e.COMMENT(/\(;/,/;\)/) -;return n.contains.push("self"),{name:"WebAssembly",keywords:{$pattern:/[\w.]+/, -keyword:["anyfunc","block","br","br_if","br_table","call","call_indirect","data","drop","elem","else","end","export","func","global.get","global.set","local.get","local.set","local.tee","get_global","get_local","global","if","import","local","loop","memory","memory.grow","memory.size","module","mut","nop","offset","param","result","return","select","set_global","set_local","start","table","tee_local","then","type","unreachable"] -},contains:[e.COMMENT(/;;/,/$/),n,{match:[/(?:offset|align)/,/\s*/,/=/], -className:{1:"keyword",3:"operator"}},{className:"variable",begin:/\$[\w_]+/},{ -match:/(\((?!;)|\))+/,className:"punctuation",relevance:0},{ -begin:[/(?:func|call|call_indirect)/,/\s+/,/\$[^\s)]+/],className:{1:"keyword", -3:"title.function"}},e.QUOTE_STRING_MODE,{match:/(i32|i64|f32|f64)(?!\.)/, -className:"type"},{className:"keyword", -match:/\b(f32|f64|i32|i64)(?:\.(?:abs|add|and|ceil|clz|const|convert_[su]\/i(?:32|64)|copysign|ctz|demote\/f64|div(?:_[su])?|eqz?|extend_[su]\/i32|floor|ge(?:_[su])?|gt(?:_[su])?|le(?:_[su])?|load(?:(?:8|16|32)_[su])?|lt(?:_[su])?|max|min|mul|nearest|neg?|or|popcnt|promote\/f32|reinterpret\/[fi](?:32|64)|rem_[su]|rot[lr]|shl|shr_[su]|store(?:8|16|32)?|sqrt|sub|trunc(?:_[su]\/f(?:32|64))?|wrap\/i64|xor))\b/ -},{className:"number",relevance:0, -match:/[+-]?\b(?:\d(?:_?\d)*(?:\.\d(?:_?\d)*)?(?:[eE][+-]?\d(?:_?\d)*)?|0x[\da-fA-F](?:_?[\da-fA-F])*(?:\.[\da-fA-F](?:_?[\da-fA-D])*)?(?:[pP][+-]?\d(?:_?\d)*)?)\b|\binf\b|\bnan(?::0x[\da-fA-F](?:_?[\da-fA-D])*)?\b/ -}]}},grmr_xml:e=>{ -const n=e.regex,t=n.concat(/[\p{L}_]/u,n.optional(/[\p{L}0-9_.-]*:/u),/[\p{L}0-9_.-]*/u),a={ -className:"symbol",begin:/&[a-z]+;|&#[0-9]+;|&#x[a-f0-9]+;/},i={begin:/\s/, -contains:[{className:"keyword",begin:/#?[a-z_][a-z1-9_-]+/,illegal:/\n/}] -},r=e.inherit(i,{begin:/\(/,end:/\)/}),s=e.inherit(e.APOS_STRING_MODE,{ -className:"string"}),o=e.inherit(e.QUOTE_STRING_MODE,{className:"string"}),l={ -endsWithParent:!0,illegal:/`]+/}]}]}]};return{ -name:"HTML, XML", -aliases:["html","xhtml","rss","atom","xjb","xsd","xsl","plist","wsf","svg"], -case_insensitive:!0,unicodeRegex:!0,contains:[{className:"meta",begin://,relevance:10,contains:[i,o,s,r,{begin:/\[/,end:/\]/,contains:[{ -className:"meta",begin://,contains:[i,r,o,s]}]}] -},e.COMMENT(//,{relevance:10}),{begin://, -relevance:10},a,{className:"meta",end:/\?>/,variants:[{begin:/<\?xml/, -relevance:10,contains:[o]},{begin:/<\?[a-z][a-z0-9]+/}]},{className:"tag", -begin:/)/,end:/>/,keywords:{name:"style"},contains:[l],starts:{ -end:/<\/style>/,returnEnd:!0,subLanguage:["css","xml"]}},{className:"tag", -begin:/)/,end:/>/,keywords:{name:"script"},contains:[l],starts:{ -end:/<\/script>/,returnEnd:!0,subLanguage:["javascript","handlebars","xml"]}},{ -className:"tag",begin:/<>|<\/>/},{className:"tag", -begin:n.concat(//,/>/,/\s/)))), -end:/\/?>/,contains:[{className:"name",begin:t,relevance:0,starts:l}]},{ -className:"tag",begin:n.concat(/<\//,n.lookahead(n.concat(t,/>/))),contains:[{ -className:"name",begin:t,relevance:0},{begin:/>/,relevance:0,endsParent:!0}]}]} -},grmr_yaml:e=>{ -const n="true false yes no null",t="[\\w#;/?:@&=+$,.~*'()[\\]]+",a={ -className:"string",relevance:0,variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/ -},{begin:/\S+/}],contains:[e.BACKSLASH_ESCAPE,{className:"template-variable", -variants:[{begin:/\{\{/,end:/\}\}/},{begin:/%\{/,end:/\}/}]}]},i=e.inherit(a,{ -variants:[{begin:/'/,end:/'/},{begin:/"/,end:/"/},{begin:/[^\s,{}[\]]+/}]}),r={ -end:",",endsWithParent:!0,excludeEnd:!0,keywords:n,relevance:0},s={begin:/\{/, -end:/\}/,contains:[r],illegal:"\\n",relevance:0},o={begin:"\\[",end:"\\]", -contains:[r],illegal:"\\n",relevance:0},l=[{className:"attr",variants:[{ -begin:/\w[\w :()\./-]*:(?=[ \t]|$)/},{begin:/"\w[\w :()\./-]*":(?=[ \t]|$)/},{ -begin:/'\w[\w :()\./-]*':(?=[ \t]|$)/}]},{className:"meta",begin:"^---\\s*$", -relevance:10},{className:"string", -begin:"[\\|>]([1-9]?[+-])?[ ]*\\n( +)[^ ][^\\n]*\\n(\\2[^\\n]+\\n?)*"},{ -begin:"<%[%=-]?",end:"[%-]?%>",subLanguage:"ruby",excludeBegin:!0,excludeEnd:!0, -relevance:0},{className:"type",begin:"!\\w+!"+t},{className:"type", -begin:"!<"+t+">"},{className:"type",begin:"!"+t},{className:"type",begin:"!!"+t -},{className:"meta",begin:"&"+e.UNDERSCORE_IDENT_RE+"$"},{className:"meta", -begin:"\\*"+e.UNDERSCORE_IDENT_RE+"$"},{className:"bullet",begin:"-(?=[ ]|$)", -relevance:0},e.HASH_COMMENT_MODE,{beginKeywords:n,keywords:{literal:n}},{ -className:"number", -begin:"\\b[0-9]{4}(-[0-9][0-9]){0,2}([Tt \\t][0-9][0-9]?(:[0-9][0-9]){2})?(\\.[0-9]*)?([ \\t])*(Z|[-+][0-9][0-9]?(:[0-9][0-9])?)?\\b" -},{className:"number",begin:e.C_NUMBER_RE+"\\b",relevance:0},s,o,a],c=[...l] -;return c.pop(),c.push(i),r.contains=c,{name:"YAML",case_insensitive:!0, -aliases:["yml"],contains:l}}});const Ke=te;for(const e of Object.keys(Pe)){ -const n=e.replace("grmr_","").replace("_","-");Ke.registerLanguage(n,Pe[e])} -return Ke}() -;"object"==typeof exports&&"undefined"!=typeof module&&(module.exports=hljs); \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/cpp.min.js b/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/cpp.min.js deleted file mode 100644 index 9f0411f0..00000000 --- a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/cpp.min.js +++ /dev/null @@ -1,47 +0,0 @@ -/*! `cpp` grammar compiled for Highlight.js 11.10.0 */ -(()=>{var e=(()=>{"use strict";return e=>{const t=e.regex,a=e.COMMENT("//","$",{ -contains:[{begin:/\\\n/}] -}),n="decltype\\(auto\\)",r="[a-zA-Z_]\\w*::",i="(?!struct)("+n+"|"+t.optional(r)+"[a-zA-Z_]\\w*"+t.optional("<[^<>]+>")+")",s={ -className:"type",begin:"\\b[a-z\\d_]*_t\\b"},c={className:"string",variants:[{ -begin:'(u8?|U|L)?"',end:'"',illegal:"\\n",contains:[e.BACKSLASH_ESCAPE]},{ -begin:"(u8?|U|L)?'(\\\\(x[0-9A-Fa-f]{2}|u[0-9A-Fa-f]{4,8}|[0-7]{3}|\\S)|.)", -end:"'",illegal:"."},e.END_SAME_AS_BEGIN({ -begin:/(?:u8?|U|L)?R"([^()\\ ]{0,16})\(/,end:/\)([^()\\ ]{0,16})"/})]},o={ -className:"number",variants:[{ -begin:"[+-]?(?:(?:[0-9](?:'?[0-9])*\\.(?:[0-9](?:'?[0-9])*)?|\\.[0-9](?:'?[0-9])*)(?:[Ee][+-]?[0-9](?:'?[0-9])*)?|[0-9](?:'?[0-9])*[Ee][+-]?[0-9](?:'?[0-9])*|0[Xx](?:[0-9A-Fa-f](?:'?[0-9A-Fa-f])*(?:\\.(?:[0-9A-Fa-f](?:'?[0-9A-Fa-f])*)?)?|\\.[0-9A-Fa-f](?:'?[0-9A-Fa-f])*)[Pp][+-]?[0-9](?:'?[0-9])*)(?:[Ff](?:16|32|64|128)?|(BF|bf)16|[Ll]|)" -},{ -begin:"[+-]?\\b(?:0[Bb][01](?:'?[01])*|0[Xx][0-9A-Fa-f](?:'?[0-9A-Fa-f])*|0(?:'?[0-7])*|[1-9](?:'?[0-9])*)(?:[Uu](?:LL?|ll?)|[Uu][Zz]?|(?:LL?|ll?)[Uu]?|[Zz][Uu]|)" -}],relevance:0},l={className:"meta",begin:/#\s*[a-z]+\b/,end:/$/,keywords:{ -keyword:"if else elif endif define undef warning error line pragma _Pragma ifdef ifndef include" -},contains:[{begin:/\\\n/,relevance:0},e.inherit(c,{className:"string"}),{ -className:"string",begin:/<.*?>/},a,e.C_BLOCK_COMMENT_MODE]},u={ -className:"title",begin:t.optional(r)+e.IDENT_RE,relevance:0 -},d=t.optional(r)+e.IDENT_RE+"\\s*\\(",p={ -type:["bool","char","char16_t","char32_t","char8_t","double","float","int","long","short","void","wchar_t","unsigned","signed","const","static"], -keyword:["alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit","atomic_noexcept","auto","bitand","bitor","break","case","catch","class","co_await","co_return","co_yield","compl","concept","const_cast|10","consteval","constexpr","constinit","continue","decltype","default","delete","do","dynamic_cast|10","else","enum","explicit","export","extern","false","final","for","friend","goto","if","import","inline","module","mutable","namespace","new","noexcept","not","not_eq","nullptr","operator","or","or_eq","override","private","protected","public","reflexpr","register","reinterpret_cast|10","requires","return","sizeof","static_assert","static_cast|10","struct","switch","synchronized","template","this","thread_local","throw","transaction_safe","transaction_safe_dynamic","true","try","typedef","typeid","typename","union","using","virtual","volatile","while","xor","xor_eq"], -literal:["NULL","false","nullopt","nullptr","true"],built_in:["_Pragma"], -_type_hints:["any","auto_ptr","barrier","binary_semaphore","bitset","complex","condition_variable","condition_variable_any","counting_semaphore","deque","false_type","future","imaginary","initializer_list","istringstream","jthread","latch","lock_guard","multimap","multiset","mutex","optional","ostringstream","packaged_task","pair","promise","priority_queue","queue","recursive_mutex","recursive_timed_mutex","scoped_lock","set","shared_future","shared_lock","shared_mutex","shared_timed_mutex","shared_ptr","stack","string_view","stringstream","timed_mutex","thread","true_type","tuple","unique_lock","unique_ptr","unordered_map","unordered_multimap","unordered_multiset","unordered_set","variant","vector","weak_ptr","wstring","wstring_view"] -},_={className:"function.dispatch",relevance:0,keywords:{ -_hint:["abort","abs","acos","apply","as_const","asin","atan","atan2","calloc","ceil","cerr","cin","clog","cos","cosh","cout","declval","endl","exchange","exit","exp","fabs","floor","fmod","forward","fprintf","fputs","free","frexp","fscanf","future","invoke","isalnum","isalpha","iscntrl","isdigit","isgraph","islower","isprint","ispunct","isspace","isupper","isxdigit","labs","launder","ldexp","log","log10","make_pair","make_shared","make_shared_for_overwrite","make_tuple","make_unique","malloc","memchr","memcmp","memcpy","memset","modf","move","pow","printf","putchar","puts","realloc","scanf","sin","sinh","snprintf","sprintf","sqrt","sscanf","std","stderr","stdin","stdout","strcat","strchr","strcmp","strcpy","strcspn","strlen","strncat","strncmp","strncpy","strpbrk","strrchr","strspn","strstr","swap","tan","tanh","terminate","to_underlying","tolower","toupper","vfprintf","visit","vprintf","vsprintf"] -}, -begin:t.concat(/\b/,/(?!decltype)/,/(?!if)/,/(?!for)/,/(?!switch)/,/(?!while)/,e.IDENT_RE,t.lookahead(/(<[^<>]+>|)\s*\(/)) -},m=[_,l,s,a,e.C_BLOCK_COMMENT_MODE,o,c],f={variants:[{begin:/=/,end:/;/},{ -begin:/\(/,end:/\)/},{beginKeywords:"new throw return else",end:/;/}], -keywords:p,contains:m.concat([{begin:/\(/,end:/\)/,keywords:p, -contains:m.concat(["self"]),relevance:0}]),relevance:0},g={className:"function", -begin:"("+i+"[\\*&\\s]+)+"+d,returnBegin:!0,end:/[{;=]/,excludeEnd:!0, -keywords:p,illegal:/[^\w\s\*&:<>.]/,contains:[{begin:n,keywords:p,relevance:0},{ -begin:d,returnBegin:!0,contains:[u],relevance:0},{begin:/::/,relevance:0},{ -begin:/:/,endsWithParent:!0,contains:[c,o]},{relevance:0,match:/,/},{ -className:"params",begin:/\(/,end:/\)/,keywords:p,relevance:0, -contains:[a,e.C_BLOCK_COMMENT_MODE,c,o,s,{begin:/\(/,end:/\)/,keywords:p, -relevance:0,contains:["self",a,e.C_BLOCK_COMMENT_MODE,c,o,s]}] -},s,a,e.C_BLOCK_COMMENT_MODE,l]};return{name:"C++", -aliases:["cc","c++","h++","hpp","hh","hxx","cxx"],keywords:p,illegal:"",keywords:p,contains:["self",s]},{begin:e.IDENT_RE+"::",keywords:p},{ -match:[/\b(?:enum(?:\s+(?:class|struct))?|class|struct|union)/,/\s+/,/\w+/], -className:{1:"keyword",3:"title.class"}}])}}})();hljs.registerLanguage("cpp",e) -})(); \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/python.min.js b/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/python.min.js deleted file mode 100644 index 2f53bd30..00000000 --- a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/python.min.js +++ /dev/null @@ -1,42 +0,0 @@ -/*! `python` grammar compiled for Highlight.js 11.10.0 */ -(()=>{var e=(()=>{"use strict";return e=>{ -const n=e.regex,a=/[\p{XID_Start}_]\p{XID_Continue}*/u,s=["and","as","assert","async","await","break","case","class","continue","def","del","elif","else","except","finally","for","from","global","if","import","in","is","lambda","match","nonlocal|10","not","or","pass","raise","return","try","while","with","yield"],t={ -$pattern:/[A-Za-z]\w+|__\w+__/,keyword:s, -built_in:["__import__","abs","all","any","ascii","bin","bool","breakpoint","bytearray","bytes","callable","chr","classmethod","compile","complex","delattr","dict","dir","divmod","enumerate","eval","exec","filter","float","format","frozenset","getattr","globals","hasattr","hash","help","hex","id","input","int","isinstance","issubclass","iter","len","list","locals","map","max","memoryview","min","next","object","oct","open","ord","pow","print","property","range","repr","reversed","round","set","setattr","slice","sorted","staticmethod","str","sum","super","tuple","type","vars","zip"], -literal:["__debug__","Ellipsis","False","None","NotImplemented","True"], -type:["Any","Callable","Coroutine","Dict","List","Literal","Generic","Optional","Sequence","Set","Tuple","Type","Union"] -},i={className:"meta",begin:/^(>>>|\.\.\.) /},r={className:"subst",begin:/\{/, -end:/\}/,keywords:t,illegal:/#/},l={begin:/\{\{/,relevance:0},o={ -className:"string",contains:[e.BACKSLASH_ESCAPE],variants:[{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,i],relevance:10},{ -begin:/([uU]|[bB]|[rR]|[bB][rR]|[rR][bB])?"""/,end:/"""/, -contains:[e.BACKSLASH_ESCAPE,i],relevance:10},{ -begin:/([fF][rR]|[rR][fF]|[fF])'''/,end:/'''/, -contains:[e.BACKSLASH_ESCAPE,i,l,r]},{begin:/([fF][rR]|[rR][fF]|[fF])"""/, -end:/"""/,contains:[e.BACKSLASH_ESCAPE,i,l,r]},{begin:/([uU]|[rR])'/,end:/'/, -relevance:10},{begin:/([uU]|[rR])"/,end:/"/,relevance:10},{ -begin:/([bB]|[bB][rR]|[rR][bB])'/,end:/'/},{begin:/([bB]|[bB][rR]|[rR][bB])"/, -end:/"/},{begin:/([fF][rR]|[rR][fF]|[fF])'/,end:/'/, -contains:[e.BACKSLASH_ESCAPE,l,r]},{begin:/([fF][rR]|[rR][fF]|[fF])"/,end:/"/, -contains:[e.BACKSLASH_ESCAPE,l,r]},e.APOS_STRING_MODE,e.QUOTE_STRING_MODE] -},b="[0-9](_?[0-9])*",c=`(\\b(${b}))?\\.(${b})|\\b(${b})\\.`,d="\\b|"+s.join("|"),g={ -className:"number",relevance:0,variants:[{ -begin:`(\\b(${b})|(${c}))[eE][+-]?(${b})[jJ]?(?=${d})`},{begin:`(${c})[jJ]?`},{ -begin:`\\b([1-9](_?[0-9])*|0+(_?0)*)[lLjJ]?(?=${d})`},{ -begin:`\\b0[bB](_?[01])+[lL]?(?=${d})`},{begin:`\\b0[oO](_?[0-7])+[lL]?(?=${d})` -},{begin:`\\b0[xX](_?[0-9a-fA-F])+[lL]?(?=${d})`},{begin:`\\b(${b})[jJ](?=${d})` -}]},p={className:"comment",begin:n.lookahead(/# type:/),end:/$/,keywords:t, -contains:[{begin:/# type:/},{begin:/#/,end:/\b\B/,endsWithParent:!0}]},m={ -className:"params",variants:[{className:"",begin:/\(\s*\)/,skip:!0},{begin:/\(/, -end:/\)/,excludeBegin:!0,excludeEnd:!0,keywords:t, -contains:["self",i,g,o,e.HASH_COMMENT_MODE]}]};return r.contains=[o,g,i],{ -name:"Python",aliases:["py","gyp","ipython"],unicodeRegex:!0,keywords:t, -illegal:/(<\/|\?)|=>/,contains:[i,g,{scope:"variable.language",match:/\bself\b/ -},{beginKeywords:"if",relevance:0},{match:/\bor\b/,scope:"keyword" -},o,p,e.HASH_COMMENT_MODE,{match:[/\bdef/,/\s+/,a],scope:{1:"keyword", -3:"title.function"},contains:[m]},{variants:[{ -match:[/\bclass/,/\s+/,a,/\s*/,/\(\s*/,a,/\s*\)/]},{match:[/\bclass/,/\s+/,a]}], -scope:{1:"keyword",3:"title.class",6:"title.class.inherited"}},{ -className:"meta",begin:/^[\t ]*@/,end:/(?=#)|$/,contains:[g,m,o]}]}}})() -;hljs.registerLanguage("python",e)})(); \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/styles/default.min.css b/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/styles/default.min.css deleted file mode 100644 index a75ea911..00000000 --- a/tinygrad/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/styles/default.min.css +++ /dev/null @@ -1,9 +0,0 @@ -/*! - Theme: Default - Description: Original highlight.js style - Author: (c) Ivan Sagalaev - Maintainer: @highlightjs/core-team - Website: https://highlightjs.org/ - License: see project LICENSE - Touched: 2021 -*/pre code.hljs{display:block;overflow-x:auto;padding:1em}code.hljs{padding:3px 5px}.hljs{background:#f3f3f3;color:#444}.hljs-comment{color:#697070}.hljs-punctuation,.hljs-tag{color:#444a}.hljs-tag .hljs-attr,.hljs-tag .hljs-name{color:#444}.hljs-attribute,.hljs-doctag,.hljs-keyword,.hljs-meta .hljs-keyword,.hljs-name,.hljs-selector-tag{font-weight:700}.hljs-deletion,.hljs-number,.hljs-quote,.hljs-selector-class,.hljs-selector-id,.hljs-string,.hljs-template-tag,.hljs-type{color:#800}.hljs-section,.hljs-title{color:#800;font-weight:700}.hljs-link,.hljs-operator,.hljs-regexp,.hljs-selector-attr,.hljs-selector-pseudo,.hljs-symbol,.hljs-template-variable,.hljs-variable{color:#ab5656}.hljs-literal{color:#695}.hljs-addition,.hljs-built_in,.hljs-bullet,.hljs-code{color:#397300}.hljs-meta{color:#1f7199}.hljs-meta .hljs-string{color:#38a}.hljs-emphasis{font-style:italic}.hljs-strong{font-weight:700} \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/assets/d3js.org/d3.v7.min.js b/tinygrad/tinygrad/viz/assets/d3js.org/d3.v7.min.js deleted file mode 100644 index 33bb8802..00000000 --- a/tinygrad/tinygrad/viz/assets/d3js.org/d3.v7.min.js +++ /dev/null @@ -1,2 +0,0 @@ -// https://d3js.org v7.9.0 Copyright 2010-2023 Mike Bostock -!function(t,n){"object"==typeof exports&&"undefined"!=typeof module?n(exports):"function"==typeof define&&define.amd?define(["exports"],n):n((t="undefined"!=typeof globalThis?globalThis:t||self).d3=t.d3||{})}(this,(function(t){"use strict";function n(t,n){return null==t||null==n?NaN:tn?1:t>=n?0:NaN}function e(t,n){return null==t||null==n?NaN:nt?1:n>=t?0:NaN}function r(t){let r,o,a;function u(t,n,e=0,i=t.length){if(e>>1;o(t[r],n)<0?e=r+1:i=r}while(en(t(e),r),a=(n,e)=>t(n)-e):(r=t===n||t===e?t:i,o=t,a=t),{left:u,center:function(t,n,e=0,r=t.length){const i=u(t,n,e,r-1);return i>e&&a(t[i-1],n)>-a(t[i],n)?i-1:i},right:function(t,n,e=0,i=t.length){if(e>>1;o(t[r],n)<=0?e=r+1:i=r}while(e{n(t,e,(r<<=2)+0,(i<<=2)+0,o<<=2),n(t,e,r+1,i+1,o),n(t,e,r+2,i+2,o),n(t,e,r+3,i+3,o)}}));function d(t){return function(n,e,r=e){if(!((e=+e)>=0))throw new RangeError("invalid rx");if(!((r=+r)>=0))throw new RangeError("invalid ry");let{data:i,width:o,height:a}=n;if(!((o=Math.floor(o))>=0))throw new RangeError("invalid width");if(!((a=Math.floor(void 0!==a?a:i.length/o))>=0))throw new RangeError("invalid height");if(!o||!a||!e&&!r)return n;const u=e&&t(e),c=r&&t(r),f=i.slice();return u&&c?(p(u,f,i,o,a),p(u,i,f,o,a),p(u,f,i,o,a),g(c,i,f,o,a),g(c,f,i,o,a),g(c,i,f,o,a)):u?(p(u,i,f,o,a),p(u,f,i,o,a),p(u,i,f,o,a)):c&&(g(c,i,f,o,a),g(c,f,i,o,a),g(c,i,f,o,a)),n}}function p(t,n,e,r,i){for(let o=0,a=r*i;o{if(!((o-=a)>=i))return;let u=t*r[i];const c=a*t;for(let t=i,n=i+c;t{if(!((a-=u)>=o))return;let c=n*i[o];const f=u*n,s=f+u;for(let t=o,n=o+f;t=n&&++e;else{let r=-1;for(let i of t)null!=(i=n(i,++r,t))&&(i=+i)>=i&&++e}return e}function _(t){return 0|t.length}function b(t){return!(t>0)}function m(t){return"object"!=typeof t||"length"in t?t:Array.from(t)}function x(t,n){let e,r=0,i=0,o=0;if(void 0===n)for(let n of t)null!=n&&(n=+n)>=n&&(e=n-i,i+=e/++r,o+=e*(n-i));else{let a=-1;for(let u of t)null!=(u=n(u,++a,t))&&(u=+u)>=u&&(e=u-i,i+=e/++r,o+=e*(u-i))}if(r>1)return o/(r-1)}function w(t,n){const e=x(t,n);return e?Math.sqrt(e):e}function M(t,n){let e,r;if(void 0===n)for(const n of t)null!=n&&(void 0===e?n>=n&&(e=r=n):(e>n&&(e=n),r=o&&(e=r=o):(e>o&&(e=o),r0){for(o=t[--i];i>0&&(n=o,e=t[--i],o=n+e,r=e-(o-n),!r););i>0&&(r<0&&t[i-1]<0||r>0&&t[i-1]>0)&&(e=2*r,n=o+e,e==n-o&&(o=n))}return o}}class InternMap extends Map{constructor(t,n=N){if(super(),Object.defineProperties(this,{_intern:{value:new Map},_key:{value:n}}),null!=t)for(const[n,e]of t)this.set(n,e)}get(t){return super.get(A(this,t))}has(t){return super.has(A(this,t))}set(t,n){return super.set(S(this,t),n)}delete(t){return super.delete(E(this,t))}}class InternSet extends Set{constructor(t,n=N){if(super(),Object.defineProperties(this,{_intern:{value:new Map},_key:{value:n}}),null!=t)for(const n of t)this.add(n)}has(t){return super.has(A(this,t))}add(t){return super.add(S(this,t))}delete(t){return super.delete(E(this,t))}}function A({_intern:t,_key:n},e){const r=n(e);return t.has(r)?t.get(r):e}function S({_intern:t,_key:n},e){const r=n(e);return t.has(r)?t.get(r):(t.set(r,e),e)}function E({_intern:t,_key:n},e){const r=n(e);return t.has(r)&&(e=t.get(r),t.delete(r)),e}function N(t){return null!==t&&"object"==typeof t?t.valueOf():t}function k(t){return t}function C(t,...n){return F(t,k,k,n)}function P(t,...n){return F(t,Array.from,k,n)}function z(t,n){for(let e=1,r=n.length;et.pop().map((([n,e])=>[...t,n,e]))));return t}function $(t,n,...e){return F(t,k,n,e)}function D(t,n,...e){return F(t,Array.from,n,e)}function R(t){if(1!==t.length)throw new Error("duplicate key");return t[0]}function F(t,n,e,r){return function t(i,o){if(o>=r.length)return e(i);const a=new InternMap,u=r[o++];let c=-1;for(const t of i){const n=u(t,++c,i),e=a.get(n);e?e.push(t):a.set(n,[t])}for(const[n,e]of a)a.set(n,t(e,o));return n(a)}(t,0)}function q(t,n){return Array.from(n,(n=>t[n]))}function U(t,...n){if("function"!=typeof t[Symbol.iterator])throw new TypeError("values is not iterable");t=Array.from(t);let[e]=n;if(e&&2!==e.length||n.length>1){const r=Uint32Array.from(t,((t,n)=>n));return n.length>1?(n=n.map((n=>t.map(n))),r.sort(((t,e)=>{for(const r of n){const n=O(r[t],r[e]);if(n)return n}}))):(e=t.map(e),r.sort(((t,n)=>O(e[t],e[n])))),q(t,r)}return t.sort(I(e))}function I(t=n){if(t===n)return O;if("function"!=typeof t)throw new TypeError("compare is not a function");return(n,e)=>{const r=t(n,e);return r||0===r?r:(0===t(e,e))-(0===t(n,n))}}function O(t,n){return(null==t||!(t>=t))-(null==n||!(n>=n))||(tn?1:0)}var B=Array.prototype.slice;function Y(t){return()=>t}const L=Math.sqrt(50),j=Math.sqrt(10),H=Math.sqrt(2);function X(t,n,e){const r=(n-t)/Math.max(0,e),i=Math.floor(Math.log10(r)),o=r/Math.pow(10,i),a=o>=L?10:o>=j?5:o>=H?2:1;let u,c,f;return i<0?(f=Math.pow(10,-i)/a,u=Math.round(t*f),c=Math.round(n*f),u/fn&&--c,f=-f):(f=Math.pow(10,i)*a,u=Math.round(t/f),c=Math.round(n/f),u*fn&&--c),c0))return[];if((t=+t)===(n=+n))return[t];const r=n=i))return[];const u=o-i+1,c=new Array(u);if(r)if(a<0)for(let t=0;t0?(t=Math.floor(t/i)*i,n=Math.ceil(n/i)*i):i<0&&(t=Math.ceil(t*i)/i,n=Math.floor(n*i)/i),r=i}}function K(t){return Math.max(1,Math.ceil(Math.log(v(t))/Math.LN2)+1)}function Q(){var t=k,n=M,e=K;function r(r){Array.isArray(r)||(r=Array.from(r));var i,o,a,u=r.length,c=new Array(u);for(i=0;i=h)if(t>=h&&n===M){const t=V(l,h,e);isFinite(t)&&(t>0?h=(Math.floor(h/t)+1)*t:t<0&&(h=(Math.ceil(h*-t)+1)/-t))}else d.pop()}for(var p=d.length,g=0,y=p;d[g]<=l;)++g;for(;d[y-1]>h;)--y;(g||y0?d[i-1]:l,v.x1=i0)for(i=0;i=n)&&(e=n);else{let r=-1;for(let i of t)null!=(i=n(i,++r,t))&&(e=i)&&(e=i)}return e}function tt(t,n){let e,r=-1,i=-1;if(void 0===n)for(const n of t)++i,null!=n&&(e=n)&&(e=n,r=i);else for(let o of t)null!=(o=n(o,++i,t))&&(e=o)&&(e=o,r=i);return r}function nt(t,n){let e;if(void 0===n)for(const n of t)null!=n&&(e>n||void 0===e&&n>=n)&&(e=n);else{let r=-1;for(let i of t)null!=(i=n(i,++r,t))&&(e>i||void 0===e&&i>=i)&&(e=i)}return e}function et(t,n){let e,r=-1,i=-1;if(void 0===n)for(const n of t)++i,null!=n&&(e>n||void 0===e&&n>=n)&&(e=n,r=i);else for(let o of t)null!=(o=n(o,++i,t))&&(e>o||void 0===e&&o>=o)&&(e=o,r=i);return r}function rt(t,n,e=0,r=1/0,i){if(n=Math.floor(n),e=Math.floor(Math.max(0,e)),r=Math.floor(Math.min(t.length-1,r)),!(e<=n&&n<=r))return t;for(i=void 0===i?O:I(i);r>e;){if(r-e>600){const o=r-e+1,a=n-e+1,u=Math.log(o),c=.5*Math.exp(2*u/3),f=.5*Math.sqrt(u*c*(o-c)/o)*(a-o/2<0?-1:1);rt(t,n,Math.max(e,Math.floor(n-a*c/o+f)),Math.min(r,Math.floor(n+(o-a)*c/o+f)),i)}const o=t[n];let a=e,u=r;for(it(t,e,n),i(t[r],o)>0&&it(t,e,r);a0;)--u}0===i(t[e],o)?it(t,e,u):(++u,it(t,u,r)),u<=n&&(e=u+1),n<=u&&(r=u-1)}return t}function it(t,n,e){const r=t[n];t[n]=t[e],t[e]=r}function ot(t,e=n){let r,i=!1;if(1===e.length){let o;for(const a of t){const t=e(a);(i?n(t,o)>0:0===n(t,t))&&(r=a,o=t,i=!0)}}else for(const n of t)(i?e(n,r)>0:0===e(n,n))&&(r=n,i=!0);return r}function at(t,n,e){if(t=Float64Array.from(function*(t,n){if(void 0===n)for(let n of t)null!=n&&(n=+n)>=n&&(yield n);else{let e=-1;for(let r of t)null!=(r=n(r,++e,t))&&(r=+r)>=r&&(yield r)}}(t,e)),(r=t.length)&&!isNaN(n=+n)){if(n<=0||r<2)return nt(t);if(n>=1)return J(t);var r,i=(r-1)*n,o=Math.floor(i),a=J(rt(t,o).subarray(0,o+1));return a+(nt(t.subarray(o+1))-a)*(i-o)}}function ut(t,n,e=o){if((r=t.length)&&!isNaN(n=+n)){if(n<=0||r<2)return+e(t[0],0,t);if(n>=1)return+e(t[r-1],r-1,t);var r,i=(r-1)*n,a=Math.floor(i),u=+e(t[a],a,t);return u+(+e(t[a+1],a+1,t)-u)*(i-a)}}function ct(t,n,e=o){if(!isNaN(n=+n)){if(r=Float64Array.from(t,((n,r)=>o(e(t[r],r,t)))),n<=0)return et(r);if(n>=1)return tt(r);var r,i=Uint32Array.from(t,((t,n)=>n)),a=r.length-1,u=Math.floor(a*n);return rt(i,u,0,a,((t,n)=>O(r[t],r[n]))),(u=ot(i.subarray(0,u+1),(t=>r[t])))>=0?u:-1}}function ft(t){return Array.from(function*(t){for(const n of t)yield*n}(t))}function st(t,n){return[t,n]}function lt(t,n,e){t=+t,n=+n,e=(i=arguments.length)<2?(n=t,t=0,1):i<3?1:+e;for(var r=-1,i=0|Math.max(0,Math.ceil((n-t)/e)),o=new Array(i);++r+t(n)}function kt(t,n){return n=Math.max(0,t.bandwidth()-2*n)/2,t.round()&&(n=Math.round(n)),e=>+t(e)+n}function Ct(){return!this.__axis}function Pt(t,n){var e=[],r=null,i=null,o=6,a=6,u=3,c="undefined"!=typeof window&&window.devicePixelRatio>1?0:.5,f=t===xt||t===Tt?-1:1,s=t===Tt||t===wt?"x":"y",l=t===xt||t===Mt?St:Et;function h(h){var d=null==r?n.ticks?n.ticks.apply(n,e):n.domain():r,p=null==i?n.tickFormat?n.tickFormat.apply(n,e):mt:i,g=Math.max(o,0)+u,y=n.range(),v=+y[0]+c,_=+y[y.length-1]+c,b=(n.bandwidth?kt:Nt)(n.copy(),c),m=h.selection?h.selection():h,x=m.selectAll(".domain").data([null]),w=m.selectAll(".tick").data(d,n).order(),M=w.exit(),T=w.enter().append("g").attr("class","tick"),A=w.select("line"),S=w.select("text");x=x.merge(x.enter().insert("path",".tick").attr("class","domain").attr("stroke","currentColor")),w=w.merge(T),A=A.merge(T.append("line").attr("stroke","currentColor").attr(s+"2",f*o)),S=S.merge(T.append("text").attr("fill","currentColor").attr(s,f*g).attr("dy",t===xt?"0em":t===Mt?"0.71em":"0.32em")),h!==m&&(x=x.transition(h),w=w.transition(h),A=A.transition(h),S=S.transition(h),M=M.transition(h).attr("opacity",At).attr("transform",(function(t){return isFinite(t=b(t))?l(t+c):this.getAttribute("transform")})),T.attr("opacity",At).attr("transform",(function(t){var n=this.parentNode.__axis;return l((n&&isFinite(n=n(t))?n:b(t))+c)}))),M.remove(),x.attr("d",t===Tt||t===wt?a?"M"+f*a+","+v+"H"+c+"V"+_+"H"+f*a:"M"+c+","+v+"V"+_:a?"M"+v+","+f*a+"V"+c+"H"+_+"V"+f*a:"M"+v+","+c+"H"+_),w.attr("opacity",1).attr("transform",(function(t){return l(b(t)+c)})),A.attr(s+"2",f*o),S.attr(s,f*g).text(p),m.filter(Ct).attr("fill","none").attr("font-size",10).attr("font-family","sans-serif").attr("text-anchor",t===wt?"start":t===Tt?"end":"middle"),m.each((function(){this.__axis=b}))}return h.scale=function(t){return arguments.length?(n=t,h):n},h.ticks=function(){return e=Array.from(arguments),h},h.tickArguments=function(t){return arguments.length?(e=null==t?[]:Array.from(t),h):e.slice()},h.tickValues=function(t){return arguments.length?(r=null==t?null:Array.from(t),h):r&&r.slice()},h.tickFormat=function(t){return arguments.length?(i=t,h):i},h.tickSize=function(t){return arguments.length?(o=a=+t,h):o},h.tickSizeInner=function(t){return arguments.length?(o=+t,h):o},h.tickSizeOuter=function(t){return arguments.length?(a=+t,h):a},h.tickPadding=function(t){return arguments.length?(u=+t,h):u},h.offset=function(t){return arguments.length?(c=+t,h):c},h}var zt={value:()=>{}};function $t(){for(var t,n=0,e=arguments.length,r={};n=0&&(n=t.slice(e+1),t=t.slice(0,e)),t&&!r.hasOwnProperty(t))throw new Error("unknown type: "+t);return{type:t,name:n}}))),a=-1,u=o.length;if(!(arguments.length<2)){if(null!=n&&"function"!=typeof n)throw new Error("invalid callback: "+n);for(;++a0)for(var e,r,i=new Array(e),o=0;o=0&&"xmlns"!==(n=t.slice(0,e))&&(t=t.slice(e+1)),Ut.hasOwnProperty(n)?{space:Ut[n],local:t}:t}function Ot(t){return function(){var n=this.ownerDocument,e=this.namespaceURI;return e===qt&&n.documentElement.namespaceURI===qt?n.createElement(t):n.createElementNS(e,t)}}function Bt(t){return function(){return this.ownerDocument.createElementNS(t.space,t.local)}}function Yt(t){var n=It(t);return(n.local?Bt:Ot)(n)}function Lt(){}function jt(t){return null==t?Lt:function(){return this.querySelector(t)}}function Ht(t){return null==t?[]:Array.isArray(t)?t:Array.from(t)}function Xt(){return[]}function Gt(t){return null==t?Xt:function(){return this.querySelectorAll(t)}}function Vt(t){return function(){return this.matches(t)}}function Wt(t){return function(n){return n.matches(t)}}var Zt=Array.prototype.find;function Kt(){return this.firstElementChild}var Qt=Array.prototype.filter;function Jt(){return Array.from(this.children)}function tn(t){return new Array(t.length)}function nn(t,n){this.ownerDocument=t.ownerDocument,this.namespaceURI=t.namespaceURI,this._next=null,this._parent=t,this.__data__=n}function en(t,n,e,r,i,o){for(var a,u=0,c=n.length,f=o.length;un?1:t>=n?0:NaN}function cn(t){return function(){this.removeAttribute(t)}}function fn(t){return function(){this.removeAttributeNS(t.space,t.local)}}function sn(t,n){return function(){this.setAttribute(t,n)}}function ln(t,n){return function(){this.setAttributeNS(t.space,t.local,n)}}function hn(t,n){return function(){var e=n.apply(this,arguments);null==e?this.removeAttribute(t):this.setAttribute(t,e)}}function dn(t,n){return function(){var e=n.apply(this,arguments);null==e?this.removeAttributeNS(t.space,t.local):this.setAttributeNS(t.space,t.local,e)}}function pn(t){return t.ownerDocument&&t.ownerDocument.defaultView||t.document&&t||t.defaultView}function gn(t){return function(){this.style.removeProperty(t)}}function yn(t,n,e){return function(){this.style.setProperty(t,n,e)}}function vn(t,n,e){return function(){var r=n.apply(this,arguments);null==r?this.style.removeProperty(t):this.style.setProperty(t,r,e)}}function _n(t,n){return t.style.getPropertyValue(n)||pn(t).getComputedStyle(t,null).getPropertyValue(n)}function bn(t){return function(){delete this[t]}}function mn(t,n){return function(){this[t]=n}}function xn(t,n){return function(){var e=n.apply(this,arguments);null==e?delete this[t]:this[t]=e}}function wn(t){return t.trim().split(/^|\s+/)}function Mn(t){return t.classList||new Tn(t)}function Tn(t){this._node=t,this._names=wn(t.getAttribute("class")||"")}function An(t,n){for(var e=Mn(t),r=-1,i=n.length;++r=0&&(this._names.splice(n,1),this._node.setAttribute("class",this._names.join(" ")))},contains:function(t){return this._names.indexOf(t)>=0}};var Gn=[null];function Vn(t,n){this._groups=t,this._parents=n}function Wn(){return new Vn([[document.documentElement]],Gn)}function Zn(t){return"string"==typeof t?new Vn([[document.querySelector(t)]],[document.documentElement]):new Vn([[t]],Gn)}Vn.prototype=Wn.prototype={constructor:Vn,select:function(t){"function"!=typeof t&&(t=jt(t));for(var n=this._groups,e=n.length,r=new Array(e),i=0;i=m&&(m=b+1);!(_=y[m])&&++m=0;)(r=i[o])&&(a&&4^r.compareDocumentPosition(a)&&a.parentNode.insertBefore(r,a),a=r);return this},sort:function(t){function n(n,e){return n&&e?t(n.__data__,e.__data__):!n-!e}t||(t=un);for(var e=this._groups,r=e.length,i=new Array(r),o=0;o1?this.each((null==n?gn:"function"==typeof n?vn:yn)(t,n,null==e?"":e)):_n(this.node(),t)},property:function(t,n){return arguments.length>1?this.each((null==n?bn:"function"==typeof n?xn:mn)(t,n)):this.node()[t]},classed:function(t,n){var e=wn(t+"");if(arguments.length<2){for(var r=Mn(this.node()),i=-1,o=e.length;++i=0&&(n=t.slice(e+1),t=t.slice(0,e)),{type:t,name:n}}))}(t+""),a=o.length;if(!(arguments.length<2)){for(u=n?Ln:Yn,r=0;r()=>t;function fe(t,{sourceEvent:n,subject:e,target:r,identifier:i,active:o,x:a,y:u,dx:c,dy:f,dispatch:s}){Object.defineProperties(this,{type:{value:t,enumerable:!0,configurable:!0},sourceEvent:{value:n,enumerable:!0,configurable:!0},subject:{value:e,enumerable:!0,configurable:!0},target:{value:r,enumerable:!0,configurable:!0},identifier:{value:i,enumerable:!0,configurable:!0},active:{value:o,enumerable:!0,configurable:!0},x:{value:a,enumerable:!0,configurable:!0},y:{value:u,enumerable:!0,configurable:!0},dx:{value:c,enumerable:!0,configurable:!0},dy:{value:f,enumerable:!0,configurable:!0},_:{value:s}})}function se(t){return!t.ctrlKey&&!t.button}function le(){return this.parentNode}function he(t,n){return null==n?{x:t.x,y:t.y}:n}function de(){return navigator.maxTouchPoints||"ontouchstart"in this}function pe(t,n,e){t.prototype=n.prototype=e,e.constructor=t}function ge(t,n){var e=Object.create(t.prototype);for(var r in n)e[r]=n[r];return e}function ye(){}fe.prototype.on=function(){var t=this._.on.apply(this._,arguments);return t===this._?this:t};var ve=.7,_e=1/ve,be="\\s*([+-]?\\d+)\\s*",me="\\s*([+-]?(?:\\d*\\.)?\\d+(?:[eE][+-]?\\d+)?)\\s*",xe="\\s*([+-]?(?:\\d*\\.)?\\d+(?:[eE][+-]?\\d+)?)%\\s*",we=/^#([0-9a-f]{3,8})$/,Me=new RegExp(`^rgb\\(${be},${be},${be}\\)$`),Te=new RegExp(`^rgb\\(${xe},${xe},${xe}\\)$`),Ae=new RegExp(`^rgba\\(${be},${be},${be},${me}\\)$`),Se=new RegExp(`^rgba\\(${xe},${xe},${xe},${me}\\)$`),Ee=new RegExp(`^hsl\\(${me},${xe},${xe}\\)$`),Ne=new RegExp(`^hsla\\(${me},${xe},${xe},${me}\\)$`),ke={aliceblue:15792383,antiquewhite:16444375,aqua:65535,aquamarine:8388564,azure:15794175,beige:16119260,bisque:16770244,black:0,blanchedalmond:16772045,blue:255,blueviolet:9055202,brown:10824234,burlywood:14596231,cadetblue:6266528,chartreuse:8388352,chocolate:13789470,coral:16744272,cornflowerblue:6591981,cornsilk:16775388,crimson:14423100,cyan:65535,darkblue:139,darkcyan:35723,darkgoldenrod:12092939,darkgray:11119017,darkgreen:25600,darkgrey:11119017,darkkhaki:12433259,darkmagenta:9109643,darkolivegreen:5597999,darkorange:16747520,darkorchid:10040012,darkred:9109504,darksalmon:15308410,darkseagreen:9419919,darkslateblue:4734347,darkslategray:3100495,darkslategrey:3100495,darkturquoise:52945,darkviolet:9699539,deeppink:16716947,deepskyblue:49151,dimgray:6908265,dimgrey:6908265,dodgerblue:2003199,firebrick:11674146,floralwhite:16775920,forestgreen:2263842,fuchsia:16711935,gainsboro:14474460,ghostwhite:16316671,gold:16766720,goldenrod:14329120,gray:8421504,green:32768,greenyellow:11403055,grey:8421504,honeydew:15794160,hotpink:16738740,indianred:13458524,indigo:4915330,ivory:16777200,khaki:15787660,lavender:15132410,lavenderblush:16773365,lawngreen:8190976,lemonchiffon:16775885,lightblue:11393254,lightcoral:15761536,lightcyan:14745599,lightgoldenrodyellow:16448210,lightgray:13882323,lightgreen:9498256,lightgrey:13882323,lightpink:16758465,lightsalmon:16752762,lightseagreen:2142890,lightskyblue:8900346,lightslategray:7833753,lightslategrey:7833753,lightsteelblue:11584734,lightyellow:16777184,lime:65280,limegreen:3329330,linen:16445670,magenta:16711935,maroon:8388608,mediumaquamarine:6737322,mediumblue:205,mediumorchid:12211667,mediumpurple:9662683,mediumseagreen:3978097,mediumslateblue:8087790,mediumspringgreen:64154,mediumturquoise:4772300,mediumvioletred:13047173,midnightblue:1644912,mintcream:16121850,mistyrose:16770273,moccasin:16770229,navajowhite:16768685,navy:128,oldlace:16643558,olive:8421376,olivedrab:7048739,orange:16753920,orangered:16729344,orchid:14315734,palegoldenrod:15657130,palegreen:10025880,paleturquoise:11529966,palevioletred:14381203,papayawhip:16773077,peachpuff:16767673,peru:13468991,pink:16761035,plum:14524637,powderblue:11591910,purple:8388736,rebeccapurple:6697881,red:16711680,rosybrown:12357519,royalblue:4286945,saddlebrown:9127187,salmon:16416882,sandybrown:16032864,seagreen:3050327,seashell:16774638,sienna:10506797,silver:12632256,skyblue:8900331,slateblue:6970061,slategray:7372944,slategrey:7372944,snow:16775930,springgreen:65407,steelblue:4620980,tan:13808780,teal:32896,thistle:14204888,tomato:16737095,turquoise:4251856,violet:15631086,wheat:16113331,white:16777215,whitesmoke:16119285,yellow:16776960,yellowgreen:10145074};function Ce(){return this.rgb().formatHex()}function Pe(){return this.rgb().formatRgb()}function ze(t){var n,e;return t=(t+"").trim().toLowerCase(),(n=we.exec(t))?(e=n[1].length,n=parseInt(n[1],16),6===e?$e(n):3===e?new qe(n>>8&15|n>>4&240,n>>4&15|240&n,(15&n)<<4|15&n,1):8===e?De(n>>24&255,n>>16&255,n>>8&255,(255&n)/255):4===e?De(n>>12&15|n>>8&240,n>>8&15|n>>4&240,n>>4&15|240&n,((15&n)<<4|15&n)/255):null):(n=Me.exec(t))?new qe(n[1],n[2],n[3],1):(n=Te.exec(t))?new qe(255*n[1]/100,255*n[2]/100,255*n[3]/100,1):(n=Ae.exec(t))?De(n[1],n[2],n[3],n[4]):(n=Se.exec(t))?De(255*n[1]/100,255*n[2]/100,255*n[3]/100,n[4]):(n=Ee.exec(t))?Le(n[1],n[2]/100,n[3]/100,1):(n=Ne.exec(t))?Le(n[1],n[2]/100,n[3]/100,n[4]):ke.hasOwnProperty(t)?$e(ke[t]):"transparent"===t?new qe(NaN,NaN,NaN,0):null}function $e(t){return new qe(t>>16&255,t>>8&255,255&t,1)}function De(t,n,e,r){return r<=0&&(t=n=e=NaN),new qe(t,n,e,r)}function Re(t){return t instanceof ye||(t=ze(t)),t?new qe((t=t.rgb()).r,t.g,t.b,t.opacity):new qe}function Fe(t,n,e,r){return 1===arguments.length?Re(t):new qe(t,n,e,null==r?1:r)}function qe(t,n,e,r){this.r=+t,this.g=+n,this.b=+e,this.opacity=+r}function Ue(){return`#${Ye(this.r)}${Ye(this.g)}${Ye(this.b)}`}function Ie(){const t=Oe(this.opacity);return`${1===t?"rgb(":"rgba("}${Be(this.r)}, ${Be(this.g)}, ${Be(this.b)}${1===t?")":`, ${t})`}`}function Oe(t){return isNaN(t)?1:Math.max(0,Math.min(1,t))}function Be(t){return Math.max(0,Math.min(255,Math.round(t)||0))}function Ye(t){return((t=Be(t))<16?"0":"")+t.toString(16)}function Le(t,n,e,r){return r<=0?t=n=e=NaN:e<=0||e>=1?t=n=NaN:n<=0&&(t=NaN),new Xe(t,n,e,r)}function je(t){if(t instanceof Xe)return new Xe(t.h,t.s,t.l,t.opacity);if(t instanceof ye||(t=ze(t)),!t)return new Xe;if(t instanceof Xe)return t;var n=(t=t.rgb()).r/255,e=t.g/255,r=t.b/255,i=Math.min(n,e,r),o=Math.max(n,e,r),a=NaN,u=o-i,c=(o+i)/2;return u?(a=n===o?(e-r)/u+6*(e0&&c<1?0:a,new Xe(a,u,c,t.opacity)}function He(t,n,e,r){return 1===arguments.length?je(t):new Xe(t,n,e,null==r?1:r)}function Xe(t,n,e,r){this.h=+t,this.s=+n,this.l=+e,this.opacity=+r}function Ge(t){return(t=(t||0)%360)<0?t+360:t}function Ve(t){return Math.max(0,Math.min(1,t||0))}function We(t,n,e){return 255*(t<60?n+(e-n)*t/60:t<180?e:t<240?n+(e-n)*(240-t)/60:n)}pe(ye,ze,{copy(t){return Object.assign(new this.constructor,this,t)},displayable(){return this.rgb().displayable()},hex:Ce,formatHex:Ce,formatHex8:function(){return this.rgb().formatHex8()},formatHsl:function(){return je(this).formatHsl()},formatRgb:Pe,toString:Pe}),pe(qe,Fe,ge(ye,{brighter(t){return t=null==t?_e:Math.pow(_e,t),new qe(this.r*t,this.g*t,this.b*t,this.opacity)},darker(t){return t=null==t?ve:Math.pow(ve,t),new qe(this.r*t,this.g*t,this.b*t,this.opacity)},rgb(){return this},clamp(){return new qe(Be(this.r),Be(this.g),Be(this.b),Oe(this.opacity))},displayable(){return-.5<=this.r&&this.r<255.5&&-.5<=this.g&&this.g<255.5&&-.5<=this.b&&this.b<255.5&&0<=this.opacity&&this.opacity<=1},hex:Ue,formatHex:Ue,formatHex8:function(){return`#${Ye(this.r)}${Ye(this.g)}${Ye(this.b)}${Ye(255*(isNaN(this.opacity)?1:this.opacity))}`},formatRgb:Ie,toString:Ie})),pe(Xe,He,ge(ye,{brighter(t){return t=null==t?_e:Math.pow(_e,t),new Xe(this.h,this.s,this.l*t,this.opacity)},darker(t){return t=null==t?ve:Math.pow(ve,t),new Xe(this.h,this.s,this.l*t,this.opacity)},rgb(){var t=this.h%360+360*(this.h<0),n=isNaN(t)||isNaN(this.s)?0:this.s,e=this.l,r=e+(e<.5?e:1-e)*n,i=2*e-r;return new qe(We(t>=240?t-240:t+120,i,r),We(t,i,r),We(t<120?t+240:t-120,i,r),this.opacity)},clamp(){return new Xe(Ge(this.h),Ve(this.s),Ve(this.l),Oe(this.opacity))},displayable(){return(0<=this.s&&this.s<=1||isNaN(this.s))&&0<=this.l&&this.l<=1&&0<=this.opacity&&this.opacity<=1},formatHsl(){const t=Oe(this.opacity);return`${1===t?"hsl(":"hsla("}${Ge(this.h)}, ${100*Ve(this.s)}%, ${100*Ve(this.l)}%${1===t?")":`, ${t})`}`}}));const Ze=Math.PI/180,Ke=180/Math.PI,Qe=.96422,Je=1,tr=.82521,nr=4/29,er=6/29,rr=3*er*er,ir=er*er*er;function or(t){if(t instanceof ur)return new ur(t.l,t.a,t.b,t.opacity);if(t instanceof pr)return gr(t);t instanceof qe||(t=Re(t));var n,e,r=lr(t.r),i=lr(t.g),o=lr(t.b),a=cr((.2225045*r+.7168786*i+.0606169*o)/Je);return r===i&&i===o?n=e=a:(n=cr((.4360747*r+.3850649*i+.1430804*o)/Qe),e=cr((.0139322*r+.0971045*i+.7141733*o)/tr)),new ur(116*a-16,500*(n-a),200*(a-e),t.opacity)}function ar(t,n,e,r){return 1===arguments.length?or(t):new ur(t,n,e,null==r?1:r)}function ur(t,n,e,r){this.l=+t,this.a=+n,this.b=+e,this.opacity=+r}function cr(t){return t>ir?Math.pow(t,1/3):t/rr+nr}function fr(t){return t>er?t*t*t:rr*(t-nr)}function sr(t){return 255*(t<=.0031308?12.92*t:1.055*Math.pow(t,1/2.4)-.055)}function lr(t){return(t/=255)<=.04045?t/12.92:Math.pow((t+.055)/1.055,2.4)}function hr(t){if(t instanceof pr)return new pr(t.h,t.c,t.l,t.opacity);if(t instanceof ur||(t=or(t)),0===t.a&&0===t.b)return new pr(NaN,0=1?(e=1,n-1):Math.floor(e*n),i=t[r],o=t[r+1],a=r>0?t[r-1]:2*i-o,u=r()=>t;function Cr(t,n){return function(e){return t+e*n}}function Pr(t,n){var e=n-t;return e?Cr(t,e>180||e<-180?e-360*Math.round(e/360):e):kr(isNaN(t)?n:t)}function zr(t){return 1==(t=+t)?$r:function(n,e){return e-n?function(t,n,e){return t=Math.pow(t,e),n=Math.pow(n,e)-t,e=1/e,function(r){return Math.pow(t+r*n,e)}}(n,e,t):kr(isNaN(n)?e:n)}}function $r(t,n){var e=n-t;return e?Cr(t,e):kr(isNaN(t)?n:t)}var Dr=function t(n){var e=zr(n);function r(t,n){var r=e((t=Fe(t)).r,(n=Fe(n)).r),i=e(t.g,n.g),o=e(t.b,n.b),a=$r(t.opacity,n.opacity);return function(n){return t.r=r(n),t.g=i(n),t.b=o(n),t.opacity=a(n),t+""}}return r.gamma=t,r}(1);function Rr(t){return function(n){var e,r,i=n.length,o=new Array(i),a=new Array(i),u=new Array(i);for(e=0;eo&&(i=n.slice(o,i),u[a]?u[a]+=i:u[++a]=i),(e=e[0])===(r=r[0])?u[a]?u[a]+=r:u[++a]=r:(u[++a]=null,c.push({i:a,x:Yr(e,r)})),o=Hr.lastIndex;return o180?n+=360:n-t>180&&(t+=360),o.push({i:e.push(i(e)+"rotate(",null,r)-2,x:Yr(t,n)})):n&&e.push(i(e)+"rotate("+n+r)}(o.rotate,a.rotate,u,c),function(t,n,e,o){t!==n?o.push({i:e.push(i(e)+"skewX(",null,r)-2,x:Yr(t,n)}):n&&e.push(i(e)+"skewX("+n+r)}(o.skewX,a.skewX,u,c),function(t,n,e,r,o,a){if(t!==e||n!==r){var u=o.push(i(o)+"scale(",null,",",null,")");a.push({i:u-4,x:Yr(t,e)},{i:u-2,x:Yr(n,r)})}else 1===e&&1===r||o.push(i(o)+"scale("+e+","+r+")")}(o.scaleX,o.scaleY,a.scaleX,a.scaleY,u,c),o=a=null,function(t){for(var n,e=-1,r=c.length;++e=0&&n._call.call(void 0,t),n=n._next;--yi}function Ci(){xi=(mi=Mi.now())+wi,yi=vi=0;try{ki()}finally{yi=0,function(){var t,n,e=pi,r=1/0;for(;e;)e._call?(r>e._time&&(r=e._time),t=e,e=e._next):(n=e._next,e._next=null,e=t?t._next=n:pi=n);gi=t,zi(r)}(),xi=0}}function Pi(){var t=Mi.now(),n=t-mi;n>bi&&(wi-=n,mi=t)}function zi(t){yi||(vi&&(vi=clearTimeout(vi)),t-xi>24?(t<1/0&&(vi=setTimeout(Ci,t-Mi.now()-wi)),_i&&(_i=clearInterval(_i))):(_i||(mi=Mi.now(),_i=setInterval(Pi,bi)),yi=1,Ti(Ci)))}function $i(t,n,e){var r=new Ei;return n=null==n?0:+n,r.restart((e=>{r.stop(),t(e+n)}),n,e),r}Ei.prototype=Ni.prototype={constructor:Ei,restart:function(t,n,e){if("function"!=typeof t)throw new TypeError("callback is not a function");e=(null==e?Ai():+e)+(null==n?0:+n),this._next||gi===this||(gi?gi._next=this:pi=this,gi=this),this._call=t,this._time=e,zi()},stop:function(){this._call&&(this._call=null,this._time=1/0,zi())}};var Di=$t("start","end","cancel","interrupt"),Ri=[],Fi=0,qi=1,Ui=2,Ii=3,Oi=4,Bi=5,Yi=6;function Li(t,n,e,r,i,o){var a=t.__transition;if(a){if(e in a)return}else t.__transition={};!function(t,n,e){var r,i=t.__transition;function o(t){e.state=qi,e.timer.restart(a,e.delay,e.time),e.delay<=t&&a(t-e.delay)}function a(o){var f,s,l,h;if(e.state!==qi)return c();for(f in i)if((h=i[f]).name===e.name){if(h.state===Ii)return $i(a);h.state===Oi?(h.state=Yi,h.timer.stop(),h.on.call("interrupt",t,t.__data__,h.index,h.group),delete i[f]):+fFi)throw new Error("too late; already scheduled");return e}function Hi(t,n){var e=Xi(t,n);if(e.state>Ii)throw new Error("too late; already running");return e}function Xi(t,n){var e=t.__transition;if(!e||!(e=e[n]))throw new Error("transition not found");return e}function Gi(t,n){var e,r,i,o=t.__transition,a=!0;if(o){for(i in n=null==n?null:n+"",o)(e=o[i]).name===n?(r=e.state>Ui&&e.state=0&&(t=t.slice(0,n)),!t||"start"===t}))}(n)?ji:Hi;return function(){var a=o(this,t),u=a.on;u!==r&&(i=(r=u).copy()).on(n,e),a.on=i}}(e,t,n))},attr:function(t,n){var e=It(t),r="transform"===e?ni:Ki;return this.attrTween(t,"function"==typeof n?(e.local?ro:eo)(e,r,Zi(this,"attr."+t,n)):null==n?(e.local?Ji:Qi)(e):(e.local?no:to)(e,r,n))},attrTween:function(t,n){var e="attr."+t;if(arguments.length<2)return(e=this.tween(e))&&e._value;if(null==n)return this.tween(e,null);if("function"!=typeof n)throw new Error;var r=It(t);return this.tween(e,(r.local?io:oo)(r,n))},style:function(t,n,e){var r="transform"==(t+="")?ti:Ki;return null==n?this.styleTween(t,function(t,n){var e,r,i;return function(){var o=_n(this,t),a=(this.style.removeProperty(t),_n(this,t));return o===a?null:o===e&&a===r?i:i=n(e=o,r=a)}}(t,r)).on("end.style."+t,lo(t)):"function"==typeof n?this.styleTween(t,function(t,n,e){var r,i,o;return function(){var a=_n(this,t),u=e(this),c=u+"";return null==u&&(this.style.removeProperty(t),c=u=_n(this,t)),a===c?null:a===r&&c===i?o:(i=c,o=n(r=a,u))}}(t,r,Zi(this,"style."+t,n))).each(function(t,n){var e,r,i,o,a="style."+n,u="end."+a;return function(){var c=Hi(this,t),f=c.on,s=null==c.value[a]?o||(o=lo(n)):void 0;f===e&&i===s||(r=(e=f).copy()).on(u,i=s),c.on=r}}(this._id,t)):this.styleTween(t,function(t,n,e){var r,i,o=e+"";return function(){var a=_n(this,t);return a===o?null:a===r?i:i=n(r=a,e)}}(t,r,n),e).on("end.style."+t,null)},styleTween:function(t,n,e){var r="style."+(t+="");if(arguments.length<2)return(r=this.tween(r))&&r._value;if(null==n)return this.tween(r,null);if("function"!=typeof n)throw new Error;return this.tween(r,function(t,n,e){var r,i;function o(){var o=n.apply(this,arguments);return o!==i&&(r=(i=o)&&function(t,n,e){return function(r){this.style.setProperty(t,n.call(this,r),e)}}(t,o,e)),r}return o._value=n,o}(t,n,null==e?"":e))},text:function(t){return this.tween("text","function"==typeof t?function(t){return function(){var n=t(this);this.textContent=null==n?"":n}}(Zi(this,"text",t)):function(t){return function(){this.textContent=t}}(null==t?"":t+""))},textTween:function(t){var n="text";if(arguments.length<1)return(n=this.tween(n))&&n._value;if(null==t)return this.tween(n,null);if("function"!=typeof t)throw new Error;return this.tween(n,function(t){var n,e;function r(){var r=t.apply(this,arguments);return r!==e&&(n=(e=r)&&function(t){return function(n){this.textContent=t.call(this,n)}}(r)),n}return r._value=t,r}(t))},remove:function(){return this.on("end.remove",function(t){return function(){var n=this.parentNode;for(var e in this.__transition)if(+e!==t)return;n&&n.removeChild(this)}}(this._id))},tween:function(t,n){var e=this._id;if(t+="",arguments.length<2){for(var r,i=Xi(this.node(),e).tween,o=0,a=i.length;o()=>t;function Qo(t,{sourceEvent:n,target:e,selection:r,mode:i,dispatch:o}){Object.defineProperties(this,{type:{value:t,enumerable:!0,configurable:!0},sourceEvent:{value:n,enumerable:!0,configurable:!0},target:{value:e,enumerable:!0,configurable:!0},selection:{value:r,enumerable:!0,configurable:!0},mode:{value:i,enumerable:!0,configurable:!0},_:{value:o}})}function Jo(t){t.preventDefault(),t.stopImmediatePropagation()}var ta={name:"drag"},na={name:"space"},ea={name:"handle"},ra={name:"center"};const{abs:ia,max:oa,min:aa}=Math;function ua(t){return[+t[0],+t[1]]}function ca(t){return[ua(t[0]),ua(t[1])]}var fa={name:"x",handles:["w","e"].map(va),input:function(t,n){return null==t?null:[[+t[0],n[0][1]],[+t[1],n[1][1]]]},output:function(t){return t&&[t[0][0],t[1][0]]}},sa={name:"y",handles:["n","s"].map(va),input:function(t,n){return null==t?null:[[n[0][0],+t[0]],[n[1][0],+t[1]]]},output:function(t){return t&&[t[0][1],t[1][1]]}},la={name:"xy",handles:["n","w","e","s","nw","ne","sw","se"].map(va),input:function(t){return null==t?null:ca(t)},output:function(t){return t}},ha={overlay:"crosshair",selection:"move",n:"ns-resize",e:"ew-resize",s:"ns-resize",w:"ew-resize",nw:"nwse-resize",ne:"nesw-resize",se:"nwse-resize",sw:"nesw-resize"},da={e:"w",w:"e",nw:"ne",ne:"nw",se:"sw",sw:"se"},pa={n:"s",s:"n",nw:"sw",ne:"se",se:"ne",sw:"nw"},ga={overlay:1,selection:1,n:null,e:1,s:null,w:-1,nw:-1,ne:1,se:1,sw:-1},ya={overlay:1,selection:1,n:-1,e:null,s:1,w:null,nw:-1,ne:-1,se:1,sw:1};function va(t){return{type:t}}function _a(t){return!t.ctrlKey&&!t.button}function ba(){var t=this.ownerSVGElement||this;return t.hasAttribute("viewBox")?[[(t=t.viewBox.baseVal).x,t.y],[t.x+t.width,t.y+t.height]]:[[0,0],[t.width.baseVal.value,t.height.baseVal.value]]}function ma(){return navigator.maxTouchPoints||"ontouchstart"in this}function xa(t){for(;!t.__brush;)if(!(t=t.parentNode))return;return t.__brush}function wa(t){var n,e=ba,r=_a,i=ma,o=!0,a=$t("start","brush","end"),u=6;function c(n){var e=n.property("__brush",g).selectAll(".overlay").data([va("overlay")]);e.enter().append("rect").attr("class","overlay").attr("pointer-events","all").attr("cursor",ha.overlay).merge(e).each((function(){var t=xa(this).extent;Zn(this).attr("x",t[0][0]).attr("y",t[0][1]).attr("width",t[1][0]-t[0][0]).attr("height",t[1][1]-t[0][1])})),n.selectAll(".selection").data([va("selection")]).enter().append("rect").attr("class","selection").attr("cursor",ha.selection).attr("fill","#777").attr("fill-opacity",.3).attr("stroke","#fff").attr("shape-rendering","crispEdges");var r=n.selectAll(".handle").data(t.handles,(function(t){return t.type}));r.exit().remove(),r.enter().append("rect").attr("class",(function(t){return"handle handle--"+t.type})).attr("cursor",(function(t){return ha[t.type]})),n.each(f).attr("fill","none").attr("pointer-events","all").on("mousedown.brush",h).filter(i).on("touchstart.brush",h).on("touchmove.brush",d).on("touchend.brush touchcancel.brush",p).style("touch-action","none").style("-webkit-tap-highlight-color","rgba(0,0,0,0)")}function f(){var t=Zn(this),n=xa(this).selection;n?(t.selectAll(".selection").style("display",null).attr("x",n[0][0]).attr("y",n[0][1]).attr("width",n[1][0]-n[0][0]).attr("height",n[1][1]-n[0][1]),t.selectAll(".handle").style("display",null).attr("x",(function(t){return"e"===t.type[t.type.length-1]?n[1][0]-u/2:n[0][0]-u/2})).attr("y",(function(t){return"s"===t.type[0]?n[1][1]-u/2:n[0][1]-u/2})).attr("width",(function(t){return"n"===t.type||"s"===t.type?n[1][0]-n[0][0]+u:u})).attr("height",(function(t){return"e"===t.type||"w"===t.type?n[1][1]-n[0][1]+u:u}))):t.selectAll(".selection,.handle").style("display","none").attr("x",null).attr("y",null).attr("width",null).attr("height",null)}function s(t,n,e){var r=t.__brush.emitter;return!r||e&&r.clean?new l(t,n,e):r}function l(t,n,e){this.that=t,this.args=n,this.state=t.__brush,this.active=0,this.clean=e}function h(e){if((!n||e.touches)&&r.apply(this,arguments)){var i,a,u,c,l,h,d,p,g,y,v,_=this,b=e.target.__data__.type,m="selection"===(o&&e.metaKey?b="overlay":b)?ta:o&&e.altKey?ra:ea,x=t===sa?null:ga[b],w=t===fa?null:ya[b],M=xa(_),T=M.extent,A=M.selection,S=T[0][0],E=T[0][1],N=T[1][0],k=T[1][1],C=0,P=0,z=x&&w&&o&&e.shiftKey,$=Array.from(e.touches||[e],(t=>{const n=t.identifier;return(t=ne(t,_)).point0=t.slice(),t.identifier=n,t}));Gi(_);var D=s(_,arguments,!0).beforestart();if("overlay"===b){A&&(g=!0);const n=[$[0],$[1]||$[0]];M.selection=A=[[i=t===sa?S:aa(n[0][0],n[1][0]),u=t===fa?E:aa(n[0][1],n[1][1])],[l=t===sa?N:oa(n[0][0],n[1][0]),d=t===fa?k:oa(n[0][1],n[1][1])]],$.length>1&&I(e)}else i=A[0][0],u=A[0][1],l=A[1][0],d=A[1][1];a=i,c=u,h=l,p=d;var R=Zn(_).attr("pointer-events","none"),F=R.selectAll(".overlay").attr("cursor",ha[b]);if(e.touches)D.moved=U,D.ended=O;else{var q=Zn(e.view).on("mousemove.brush",U,!0).on("mouseup.brush",O,!0);o&&q.on("keydown.brush",(function(t){switch(t.keyCode){case 16:z=x&&w;break;case 18:m===ea&&(x&&(l=h-C*x,i=a+C*x),w&&(d=p-P*w,u=c+P*w),m=ra,I(t));break;case 32:m!==ea&&m!==ra||(x<0?l=h-C:x>0&&(i=a-C),w<0?d=p-P:w>0&&(u=c-P),m=na,F.attr("cursor",ha.selection),I(t));break;default:return}Jo(t)}),!0).on("keyup.brush",(function(t){switch(t.keyCode){case 16:z&&(y=v=z=!1,I(t));break;case 18:m===ra&&(x<0?l=h:x>0&&(i=a),w<0?d=p:w>0&&(u=c),m=ea,I(t));break;case 32:m===na&&(t.altKey?(x&&(l=h-C*x,i=a+C*x),w&&(d=p-P*w,u=c+P*w),m=ra):(x<0?l=h:x>0&&(i=a),w<0?d=p:w>0&&(u=c),m=ea),F.attr("cursor",ha[b]),I(t));break;default:return}Jo(t)}),!0),ae(e.view)}f.call(_),D.start(e,m.name)}function U(t){for(const n of t.changedTouches||[t])for(const t of $)t.identifier===n.identifier&&(t.cur=ne(n,_));if(z&&!y&&!v&&1===$.length){const t=$[0];ia(t.cur[0]-t[0])>ia(t.cur[1]-t[1])?v=!0:y=!0}for(const t of $)t.cur&&(t[0]=t.cur[0],t[1]=t.cur[1]);g=!0,Jo(t),I(t)}function I(t){const n=$[0],e=n.point0;var r;switch(C=n[0]-e[0],P=n[1]-e[1],m){case na:case ta:x&&(C=oa(S-i,aa(N-l,C)),a=i+C,h=l+C),w&&(P=oa(E-u,aa(k-d,P)),c=u+P,p=d+P);break;case ea:$[1]?(x&&(a=oa(S,aa(N,$[0][0])),h=oa(S,aa(N,$[1][0])),x=1),w&&(c=oa(E,aa(k,$[0][1])),p=oa(E,aa(k,$[1][1])),w=1)):(x<0?(C=oa(S-i,aa(N-i,C)),a=i+C,h=l):x>0&&(C=oa(S-l,aa(N-l,C)),a=i,h=l+C),w<0?(P=oa(E-u,aa(k-u,P)),c=u+P,p=d):w>0&&(P=oa(E-d,aa(k-d,P)),c=u,p=d+P));break;case ra:x&&(a=oa(S,aa(N,i-C*x)),h=oa(S,aa(N,l+C*x))),w&&(c=oa(E,aa(k,u-P*w)),p=oa(E,aa(k,d+P*w)))}ht+e))}function za(t,n){var e=0,r=null,i=null,o=null;function a(a){var u,c=a.length,f=new Array(c),s=Pa(0,c),l=new Array(c*c),h=new Array(c),d=0;a=Float64Array.from({length:c*c},n?(t,n)=>a[n%c][n/c|0]:(t,n)=>a[n/c|0][n%c]);for(let n=0;nr(f[t],f[n])));for(const e of s){const r=n;if(t){const t=Pa(1+~c,c).filter((t=>t<0?a[~t*c+e]:a[e*c+t]));i&&t.sort(((t,n)=>i(t<0?-a[~t*c+e]:a[e*c+t],n<0?-a[~n*c+e]:a[e*c+n])));for(const r of t)if(r<0){(l[~r*c+e]||(l[~r*c+e]={source:null,target:null})).target={index:e,startAngle:n,endAngle:n+=a[~r*c+e]*d,value:a[~r*c+e]}}else{(l[e*c+r]||(l[e*c+r]={source:null,target:null})).source={index:e,startAngle:n,endAngle:n+=a[e*c+r]*d,value:a[e*c+r]}}h[e]={index:e,startAngle:r,endAngle:n,value:f[e]}}else{const t=Pa(0,c).filter((t=>a[e*c+t]||a[t*c+e]));i&&t.sort(((t,n)=>i(a[e*c+t],a[e*c+n])));for(const r of t){let t;if(e=0))throw new Error(`invalid digits: ${t}`);if(n>15)return qa;const e=10**n;return function(t){this._+=t[0];for(let n=1,r=t.length;nRa)if(Math.abs(s*u-c*f)>Ra&&i){let h=e-o,d=r-a,p=u*u+c*c,g=h*h+d*d,y=Math.sqrt(p),v=Math.sqrt(l),_=i*Math.tan(($a-Math.acos((p+l-g)/(2*y*v)))/2),b=_/v,m=_/y;Math.abs(b-1)>Ra&&this._append`L${t+b*f},${n+b*s}`,this._append`A${i},${i},0,0,${+(s*h>f*d)},${this._x1=t+m*u},${this._y1=n+m*c}`}else this._append`L${this._x1=t},${this._y1=n}`;else;}arc(t,n,e,r,i,o){if(t=+t,n=+n,o=!!o,(e=+e)<0)throw new Error(`negative radius: ${e}`);let a=e*Math.cos(r),u=e*Math.sin(r),c=t+a,f=n+u,s=1^o,l=o?r-i:i-r;null===this._x1?this._append`M${c},${f}`:(Math.abs(this._x1-c)>Ra||Math.abs(this._y1-f)>Ra)&&this._append`L${c},${f}`,e&&(l<0&&(l=l%Da+Da),l>Fa?this._append`A${e},${e},0,1,${s},${t-a},${n-u}A${e},${e},0,1,${s},${this._x1=c},${this._y1=f}`:l>Ra&&this._append`A${e},${e},0,${+(l>=$a)},${s},${this._x1=t+e*Math.cos(i)},${this._y1=n+e*Math.sin(i)}`)}rect(t,n,e,r){this._append`M${this._x0=this._x1=+t},${this._y0=this._y1=+n}h${e=+e}v${+r}h${-e}Z`}toString(){return this._}};function Ia(){return new Ua}Ia.prototype=Ua.prototype;var Oa=Array.prototype.slice;function Ba(t){return function(){return t}}function Ya(t){return t.source}function La(t){return t.target}function ja(t){return t.radius}function Ha(t){return t.startAngle}function Xa(t){return t.endAngle}function Ga(){return 0}function Va(){return 10}function Wa(t){var n=Ya,e=La,r=ja,i=ja,o=Ha,a=Xa,u=Ga,c=null;function f(){var f,s=n.apply(this,arguments),l=e.apply(this,arguments),h=u.apply(this,arguments)/2,d=Oa.call(arguments),p=+r.apply(this,(d[0]=s,d)),g=o.apply(this,d)-Ea,y=a.apply(this,d)-Ea,v=+i.apply(this,(d[0]=l,d)),_=o.apply(this,d)-Ea,b=a.apply(this,d)-Ea;if(c||(c=f=Ia()),h>Ca&&(Ma(y-g)>2*h+Ca?y>g?(g+=h,y-=h):(g-=h,y+=h):g=y=(g+y)/2,Ma(b-_)>2*h+Ca?b>_?(_+=h,b-=h):(_-=h,b+=h):_=b=(_+b)/2),c.moveTo(p*Ta(g),p*Aa(g)),c.arc(0,0,p,g,y),g!==_||y!==b)if(t){var m=v-+t.apply(this,arguments),x=(_+b)/2;c.quadraticCurveTo(0,0,m*Ta(_),m*Aa(_)),c.lineTo(v*Ta(x),v*Aa(x)),c.lineTo(m*Ta(b),m*Aa(b))}else c.quadraticCurveTo(0,0,v*Ta(_),v*Aa(_)),c.arc(0,0,v,_,b);if(c.quadraticCurveTo(0,0,p*Ta(g),p*Aa(g)),c.closePath(),f)return c=null,f+""||null}return t&&(f.headRadius=function(n){return arguments.length?(t="function"==typeof n?n:Ba(+n),f):t}),f.radius=function(t){return arguments.length?(r=i="function"==typeof t?t:Ba(+t),f):r},f.sourceRadius=function(t){return arguments.length?(r="function"==typeof t?t:Ba(+t),f):r},f.targetRadius=function(t){return arguments.length?(i="function"==typeof t?t:Ba(+t),f):i},f.startAngle=function(t){return arguments.length?(o="function"==typeof t?t:Ba(+t),f):o},f.endAngle=function(t){return arguments.length?(a="function"==typeof t?t:Ba(+t),f):a},f.padAngle=function(t){return arguments.length?(u="function"==typeof t?t:Ba(+t),f):u},f.source=function(t){return arguments.length?(n=t,f):n},f.target=function(t){return arguments.length?(e=t,f):e},f.context=function(t){return arguments.length?(c=null==t?null:t,f):c},f}var Za=Array.prototype.slice;function Ka(t,n){return t-n}var Qa=t=>()=>t;function Ja(t,n){for(var e,r=-1,i=n.length;++rr!=d>r&&e<(h-f)*(r-s)/(d-s)+f&&(i=-i)}return i}function nu(t,n,e){var r,i,o,a;return function(t,n,e){return(n[0]-t[0])*(e[1]-t[1])==(e[0]-t[0])*(n[1]-t[1])}(t,n,e)&&(i=t[r=+(t[0]===n[0])],o=e[r],a=n[r],i<=o&&o<=a||a<=o&&o<=i)}function eu(){}var ru=[[],[[[1,1.5],[.5,1]]],[[[1.5,1],[1,1.5]]],[[[1.5,1],[.5,1]]],[[[1,.5],[1.5,1]]],[[[1,1.5],[.5,1]],[[1,.5],[1.5,1]]],[[[1,.5],[1,1.5]]],[[[1,.5],[.5,1]]],[[[.5,1],[1,.5]]],[[[1,1.5],[1,.5]]],[[[.5,1],[1,.5]],[[1.5,1],[1,1.5]]],[[[1.5,1],[1,.5]]],[[[.5,1],[1.5,1]]],[[[1,1.5],[1.5,1]]],[[[.5,1],[1,1.5]]],[]];function iu(){var t=1,n=1,e=K,r=u;function i(t){var n=e(t);if(Array.isArray(n))n=n.slice().sort(Ka);else{const e=M(t,ou);for(n=G(...Z(e[0],e[1],n),n);n[n.length-1]>=e[1];)n.pop();for(;n[1]o(t,n)))}function o(e,i){const o=null==i?NaN:+i;if(isNaN(o))throw new Error(`invalid value: ${i}`);var u=[],c=[];return function(e,r,i){var o,u,c,f,s,l,h=new Array,d=new Array;o=u=-1,f=au(e[0],r),ru[f<<1].forEach(p);for(;++o=r,ru[s<<2].forEach(p);for(;++o0?u.push([t]):c.push(t)})),c.forEach((function(t){for(var n,e=0,r=u.length;e0&&o0&&a=0&&o>=0))throw new Error("invalid size");return t=r,n=o,i},i.thresholds=function(t){return arguments.length?(e="function"==typeof t?t:Array.isArray(t)?Qa(Za.call(t)):Qa(t),i):e},i.smooth=function(t){return arguments.length?(r=t?u:eu,i):r===u},i}function ou(t){return isFinite(t)?t:NaN}function au(t,n){return null!=t&&+t>=n}function uu(t){return null==t||isNaN(t=+t)?-1/0:t}function cu(t,n,e,r){const i=r-n,o=e-n,a=isFinite(i)||isFinite(o)?i/o:Math.sign(i)/Math.sign(o);return isNaN(a)?t:t+a-.5}function fu(t){return t[0]}function su(t){return t[1]}function lu(){return 1}const hu=134217729,du=33306690738754706e-32;function pu(t,n,e,r,i){let o,a,u,c,f=n[0],s=r[0],l=0,h=0;s>f==s>-f?(o=f,f=n[++l]):(o=s,s=r[++h]);let d=0;if(lf==s>-f?(a=f+o,u=o-(a-f),f=n[++l]):(a=s+o,u=o-(a-s),s=r[++h]),o=a,0!==u&&(i[d++]=u);lf==s>-f?(a=o+f,c=a-o,u=o-(a-c)+(f-c),f=n[++l]):(a=o+s,c=a-o,u=o-(a-c)+(s-c),s=r[++h]),o=a,0!==u&&(i[d++]=u);for(;l=33306690738754716e-32*f?c:-function(t,n,e,r,i,o,a){let u,c,f,s,l,h,d,p,g,y,v,_,b,m,x,w,M,T;const A=t-i,S=e-i,E=n-o,N=r-o;m=A*N,h=hu*A,d=h-(h-A),p=A-d,h=hu*N,g=h-(h-N),y=N-g,x=p*y-(m-d*g-p*g-d*y),w=E*S,h=hu*E,d=h-(h-E),p=E-d,h=hu*S,g=h-(h-S),y=S-g,M=p*y-(w-d*g-p*g-d*y),v=x-M,l=x-v,_u[0]=x-(v+l)+(l-M),_=m+v,l=_-m,b=m-(_-l)+(v-l),v=b-w,l=b-v,_u[1]=b-(v+l)+(l-w),T=_+v,l=T-_,_u[2]=_-(T-l)+(v-l),_u[3]=T;let k=function(t,n){let e=n[0];for(let r=1;r=C||-k>=C)return k;if(l=t-A,u=t-(A+l)+(l-i),l=e-S,f=e-(S+l)+(l-i),l=n-E,c=n-(E+l)+(l-o),l=r-N,s=r-(N+l)+(l-o),0===u&&0===c&&0===f&&0===s)return k;if(C=vu*a+du*Math.abs(k),k+=A*s+N*u-(E*f+S*c),k>=C||-k>=C)return k;m=u*N,h=hu*u,d=h-(h-u),p=u-d,h=hu*N,g=h-(h-N),y=N-g,x=p*y-(m-d*g-p*g-d*y),w=c*S,h=hu*c,d=h-(h-c),p=c-d,h=hu*S,g=h-(h-S),y=S-g,M=p*y-(w-d*g-p*g-d*y),v=x-M,l=x-v,wu[0]=x-(v+l)+(l-M),_=m+v,l=_-m,b=m-(_-l)+(v-l),v=b-w,l=b-v,wu[1]=b-(v+l)+(l-w),T=_+v,l=T-_,wu[2]=_-(T-l)+(v-l),wu[3]=T;const P=pu(4,_u,4,wu,bu);m=A*s,h=hu*A,d=h-(h-A),p=A-d,h=hu*s,g=h-(h-s),y=s-g,x=p*y-(m-d*g-p*g-d*y),w=E*f,h=hu*E,d=h-(h-E),p=E-d,h=hu*f,g=h-(h-f),y=f-g,M=p*y-(w-d*g-p*g-d*y),v=x-M,l=x-v,wu[0]=x-(v+l)+(l-M),_=m+v,l=_-m,b=m-(_-l)+(v-l),v=b-w,l=b-v,wu[1]=b-(v+l)+(l-w),T=_+v,l=T-_,wu[2]=_-(T-l)+(v-l),wu[3]=T;const z=pu(P,bu,4,wu,mu);m=u*s,h=hu*u,d=h-(h-u),p=u-d,h=hu*s,g=h-(h-s),y=s-g,x=p*y-(m-d*g-p*g-d*y),w=c*f,h=hu*c,d=h-(h-c),p=c-d,h=hu*f,g=h-(h-f),y=f-g,M=p*y-(w-d*g-p*g-d*y),v=x-M,l=x-v,wu[0]=x-(v+l)+(l-M),_=m+v,l=_-m,b=m-(_-l)+(v-l),v=b-w,l=b-v,wu[1]=b-(v+l)+(l-w),T=_+v,l=T-_,wu[2]=_-(T-l)+(v-l),wu[3]=T;const $=pu(z,mu,4,wu,xu);return xu[$-1]}(t,n,e,r,i,o,f)}const Tu=Math.pow(2,-52),Au=new Uint32Array(512);class Su{static from(t,n=zu,e=$u){const r=t.length,i=new Float64Array(2*r);for(let o=0;o>1;if(n>0&&"number"!=typeof t[0])throw new Error("Expected coords to contain numbers.");this.coords=t;const e=Math.max(2*n-5,0);this._triangles=new Uint32Array(3*e),this._halfedges=new Int32Array(3*e),this._hashSize=Math.ceil(Math.sqrt(n)),this._hullPrev=new Uint32Array(n),this._hullNext=new Uint32Array(n),this._hullTri=new Uint32Array(n),this._hullHash=new Int32Array(this._hashSize),this._ids=new Uint32Array(n),this._dists=new Float64Array(n),this.update()}update(){const{coords:t,_hullPrev:n,_hullNext:e,_hullTri:r,_hullHash:i}=this,o=t.length>>1;let a=1/0,u=1/0,c=-1/0,f=-1/0;for(let n=0;nc&&(c=e),r>f&&(f=r),this._ids[n]=n}const s=(a+c)/2,l=(u+f)/2;let h,d,p;for(let n=0,e=1/0;n0&&(d=n,e=r)}let v=t[2*d],_=t[2*d+1],b=1/0;for(let n=0;nr&&(n[e++]=i,r=o)}return this.hull=n.subarray(0,e),this.triangles=new Uint32Array(0),void(this.halfedges=new Uint32Array(0))}if(Mu(g,y,v,_,m,x)<0){const t=d,n=v,e=_;d=p,v=m,_=x,p=t,m=n,x=e}const w=function(t,n,e,r,i,o){const a=e-t,u=r-n,c=i-t,f=o-n,s=a*a+u*u,l=c*c+f*f,h=.5/(a*f-u*c),d=t+(f*s-u*l)*h,p=n+(a*l-c*s)*h;return{x:d,y:p}}(g,y,v,_,m,x);this._cx=w.x,this._cy=w.y;for(let n=0;n0&&Math.abs(f-o)<=Tu&&Math.abs(s-a)<=Tu)continue;if(o=f,a=s,c===h||c===d||c===p)continue;let l=0;for(let t=0,n=this._hashKey(f,s);t=0;)if(y=g,y===l){y=-1;break}if(-1===y)continue;let v=this._addTriangle(y,c,e[y],-1,-1,r[y]);r[c]=this._legalize(v+2),r[y]=v,M++;let _=e[y];for(;g=e[_],Mu(f,s,t[2*_],t[2*_+1],t[2*g],t[2*g+1])<0;)v=this._addTriangle(_,c,g,r[c],-1,r[_]),r[c]=this._legalize(v+2),e[_]=_,M--,_=g;if(y===l)for(;g=n[y],Mu(f,s,t[2*g],t[2*g+1],t[2*y],t[2*y+1])<0;)v=this._addTriangle(g,c,y,-1,r[y],r[g]),this._legalize(v+2),r[g]=v,e[y]=y,M--,y=g;this._hullStart=n[c]=y,e[y]=n[_]=c,e[c]=_,i[this._hashKey(f,s)]=c,i[this._hashKey(t[2*y],t[2*y+1])]=y}this.hull=new Uint32Array(M);for(let t=0,n=this._hullStart;t0?3-e:1+e)/4}(t-this._cx,n-this._cy)*this._hashSize)%this._hashSize}_legalize(t){const{_triangles:n,_halfedges:e,coords:r}=this;let i=0,o=0;for(;;){const a=e[t],u=t-t%3;if(o=u+(t+2)%3,-1===a){if(0===i)break;t=Au[--i];continue}const c=a-a%3,f=u+(t+1)%3,s=c+(a+2)%3,l=n[o],h=n[t],d=n[f],p=n[s];if(Nu(r[2*l],r[2*l+1],r[2*h],r[2*h+1],r[2*d],r[2*d+1],r[2*p],r[2*p+1])){n[t]=p,n[a]=l;const r=e[s];if(-1===r){let n=this._hullStart;do{if(this._hullTri[n]===s){this._hullTri[n]=t;break}n=this._hullPrev[n]}while(n!==this._hullStart)}this._link(t,r),this._link(a,e[o]),this._link(o,s);const u=c+(a+1)%3;i=e&&n[t[a]]>o;)t[a+1]=t[a--];t[a+1]=r}else{let i=e+1,o=r;Pu(t,e+r>>1,i),n[t[e]]>n[t[r]]&&Pu(t,e,r),n[t[i]]>n[t[r]]&&Pu(t,i,r),n[t[e]]>n[t[i]]&&Pu(t,e,i);const a=t[i],u=n[a];for(;;){do{i++}while(n[t[i]]u);if(o=o-e?(Cu(t,n,i,r),Cu(t,n,e,o-1)):(Cu(t,n,e,o-1),Cu(t,n,i,r))}}function Pu(t,n,e){const r=t[n];t[n]=t[e],t[e]=r}function zu(t){return t[0]}function $u(t){return t[1]}const Du=1e-6;class Ru{constructor(){this._x0=this._y0=this._x1=this._y1=null,this._=""}moveTo(t,n){this._+=`M${this._x0=this._x1=+t},${this._y0=this._y1=+n}`}closePath(){null!==this._x1&&(this._x1=this._x0,this._y1=this._y0,this._+="Z")}lineTo(t,n){this._+=`L${this._x1=+t},${this._y1=+n}`}arc(t,n,e){const r=(t=+t)+(e=+e),i=n=+n;if(e<0)throw new Error("negative radius");null===this._x1?this._+=`M${r},${i}`:(Math.abs(this._x1-r)>Du||Math.abs(this._y1-i)>Du)&&(this._+="L"+r+","+i),e&&(this._+=`A${e},${e},0,1,1,${t-e},${n}A${e},${e},0,1,1,${this._x1=r},${this._y1=i}`)}rect(t,n,e,r){this._+=`M${this._x0=this._x1=+t},${this._y0=this._y1=+n}h${+e}v${+r}h${-e}Z`}value(){return this._||null}}class Fu{constructor(){this._=[]}moveTo(t,n){this._.push([t,n])}closePath(){this._.push(this._[0].slice())}lineTo(t,n){this._.push([t,n])}value(){return this._.length?this._:null}}class qu{constructor(t,[n,e,r,i]=[0,0,960,500]){if(!((r=+r)>=(n=+n)&&(i=+i)>=(e=+e)))throw new Error("invalid bounds");this.delaunay=t,this._circumcenters=new Float64Array(2*t.points.length),this.vectors=new Float64Array(2*t.points.length),this.xmax=r,this.xmin=n,this.ymax=i,this.ymin=e,this._init()}update(){return this.delaunay.update(),this._init(),this}_init(){const{delaunay:{points:t,hull:n,triangles:e},vectors:r}=this;let i,o;const a=this.circumcenters=this._circumcenters.subarray(0,e.length/3*2);for(let r,u,c=0,f=0,s=e.length;c1;)i-=2;for(let t=2;t0){if(n>=this.ymax)return null;(i=(this.ymax-n)/r)0){if(t>=this.xmax)return null;(i=(this.xmax-t)/e)this.xmax?2:0)|(nthis.ymax?8:0)}_simplify(t){if(t&&t.length>4){for(let n=0;n2&&function(t){const{triangles:n,coords:e}=t;for(let t=0;t1e-10)return!1}return!0}(t)){this.collinear=Int32Array.from({length:n.length/2},((t,n)=>n)).sort(((t,e)=>n[2*t]-n[2*e]||n[2*t+1]-n[2*e+1]));const t=this.collinear[0],e=this.collinear[this.collinear.length-1],r=[n[2*t],n[2*t+1],n[2*e],n[2*e+1]],i=1e-8*Math.hypot(r[3]-r[1],r[2]-r[0]);for(let t=0,e=n.length/2;t0&&(this.triangles=new Int32Array(3).fill(-1),this.halfedges=new Int32Array(3).fill(-1),this.triangles[0]=r[0],o[r[0]]=1,2===r.length&&(o[r[1]]=0,this.triangles[1]=r[1],this.triangles[2]=r[1]))}voronoi(t){return new qu(this,t)}*neighbors(t){const{inedges:n,hull:e,_hullIndex:r,halfedges:i,triangles:o,collinear:a}=this;if(a){const n=a.indexOf(t);return n>0&&(yield a[n-1]),void(n=0&&i!==e&&i!==r;)e=i;return i}_step(t,n,e){const{inedges:r,hull:i,_hullIndex:o,halfedges:a,triangles:u,points:c}=this;if(-1===r[t]||!c.length)return(t+1)%(c.length>>1);let f=t,s=Iu(n-c[2*t],2)+Iu(e-c[2*t+1],2);const l=r[t];let h=l;do{let r=u[h];const l=Iu(n-c[2*r],2)+Iu(e-c[2*r+1],2);if(l9999?"+"+Ku(n,6):Ku(n,4))+"-"+Ku(t.getUTCMonth()+1,2)+"-"+Ku(t.getUTCDate(),2)+(o?"T"+Ku(e,2)+":"+Ku(r,2)+":"+Ku(i,2)+"."+Ku(o,3)+"Z":i?"T"+Ku(e,2)+":"+Ku(r,2)+":"+Ku(i,2)+"Z":r||e?"T"+Ku(e,2)+":"+Ku(r,2)+"Z":"")}function Ju(t){var n=new RegExp('["'+t+"\n\r]"),e=t.charCodeAt(0);function r(t,n){var r,i=[],o=t.length,a=0,u=0,c=o<=0,f=!1;function s(){if(c)return Hu;if(f)return f=!1,ju;var n,r,i=a;if(t.charCodeAt(i)===Xu){for(;a++=o?c=!0:(r=t.charCodeAt(a++))===Gu?f=!0:r===Vu&&(f=!0,t.charCodeAt(a)===Gu&&++a),t.slice(i+1,n-1).replace(/""/g,'"')}for(;amc(n,e).then((n=>(new DOMParser).parseFromString(n,t)))}var Sc=Ac("application/xml"),Ec=Ac("text/html"),Nc=Ac("image/svg+xml");function kc(t,n,e,r){if(isNaN(n)||isNaN(e))return t;var i,o,a,u,c,f,s,l,h,d=t._root,p={data:r},g=t._x0,y=t._y0,v=t._x1,_=t._y1;if(!d)return t._root=p,t;for(;d.length;)if((f=n>=(o=(g+v)/2))?g=o:v=o,(s=e>=(a=(y+_)/2))?y=a:_=a,i=d,!(d=d[l=s<<1|f]))return i[l]=p,t;if(u=+t._x.call(null,d.data),c=+t._y.call(null,d.data),n===u&&e===c)return p.next=d,i?i[l]=p:t._root=p,t;do{i=i?i[l]=new Array(4):t._root=new Array(4),(f=n>=(o=(g+v)/2))?g=o:v=o,(s=e>=(a=(y+_)/2))?y=a:_=a}while((l=s<<1|f)==(h=(c>=a)<<1|u>=o));return i[h]=d,i[l]=p,t}function Cc(t,n,e,r,i){this.node=t,this.x0=n,this.y0=e,this.x1=r,this.y1=i}function Pc(t){return t[0]}function zc(t){return t[1]}function $c(t,n,e){var r=new Dc(null==n?Pc:n,null==e?zc:e,NaN,NaN,NaN,NaN);return null==t?r:r.addAll(t)}function Dc(t,n,e,r,i,o){this._x=t,this._y=n,this._x0=e,this._y0=r,this._x1=i,this._y1=o,this._root=void 0}function Rc(t){for(var n={data:t.data},e=n;t=t.next;)e=e.next={data:t.data};return n}var Fc=$c.prototype=Dc.prototype;function qc(t){return function(){return t}}function Uc(t){return 1e-6*(t()-.5)}function Ic(t){return t.x+t.vx}function Oc(t){return t.y+t.vy}function Bc(t){return t.index}function Yc(t,n){var e=t.get(n);if(!e)throw new Error("node not found: "+n);return e}Fc.copy=function(){var t,n,e=new Dc(this._x,this._y,this._x0,this._y0,this._x1,this._y1),r=this._root;if(!r)return e;if(!r.length)return e._root=Rc(r),e;for(t=[{source:r,target:e._root=new Array(4)}];r=t.pop();)for(var i=0;i<4;++i)(n=r.source[i])&&(n.length?t.push({source:n,target:r.target[i]=new Array(4)}):r.target[i]=Rc(n));return e},Fc.add=function(t){const n=+this._x.call(null,t),e=+this._y.call(null,t);return kc(this.cover(n,e),n,e,t)},Fc.addAll=function(t){var n,e,r,i,o=t.length,a=new Array(o),u=new Array(o),c=1/0,f=1/0,s=-1/0,l=-1/0;for(e=0;es&&(s=r),il&&(l=i));if(c>s||f>l)return this;for(this.cover(c,f).cover(s,l),e=0;et||t>=i||r>n||n>=o;)switch(u=(nh||(o=c.y0)>d||(a=c.x1)=v)<<1|t>=y)&&(c=p[p.length-1],p[p.length-1]=p[p.length-1-f],p[p.length-1-f]=c)}else{var _=t-+this._x.call(null,g.data),b=n-+this._y.call(null,g.data),m=_*_+b*b;if(m=(u=(p+y)/2))?p=u:y=u,(s=a>=(c=(g+v)/2))?g=c:v=c,n=d,!(d=d[l=s<<1|f]))return this;if(!d.length)break;(n[l+1&3]||n[l+2&3]||n[l+3&3])&&(e=n,h=l)}for(;d.data!==t;)if(r=d,!(d=d.next))return this;return(i=d.next)&&delete d.next,r?(i?r.next=i:delete r.next,this):n?(i?n[l]=i:delete n[l],(d=n[0]||n[1]||n[2]||n[3])&&d===(n[3]||n[2]||n[1]||n[0])&&!d.length&&(e?e[h]=d:this._root=d),this):(this._root=i,this)},Fc.removeAll=function(t){for(var n=0,e=t.length;n1?r[0]+r.slice(2):r,+t.slice(e+1)]}function Zc(t){return(t=Wc(Math.abs(t)))?t[1]:NaN}var Kc,Qc=/^(?:(.)?([<>=^]))?([+\-( ])?([$#])?(0)?(\d+)?(,)?(\.\d+)?(~)?([a-z%])?$/i;function Jc(t){if(!(n=Qc.exec(t)))throw new Error("invalid format: "+t);var n;return new tf({fill:n[1],align:n[2],sign:n[3],symbol:n[4],zero:n[5],width:n[6],comma:n[7],precision:n[8]&&n[8].slice(1),trim:n[9],type:n[10]})}function tf(t){this.fill=void 0===t.fill?" ":t.fill+"",this.align=void 0===t.align?">":t.align+"",this.sign=void 0===t.sign?"-":t.sign+"",this.symbol=void 0===t.symbol?"":t.symbol+"",this.zero=!!t.zero,this.width=void 0===t.width?void 0:+t.width,this.comma=!!t.comma,this.precision=void 0===t.precision?void 0:+t.precision,this.trim=!!t.trim,this.type=void 0===t.type?"":t.type+""}function nf(t,n){var e=Wc(t,n);if(!e)return t+"";var r=e[0],i=e[1];return i<0?"0."+new Array(-i).join("0")+r:r.length>i+1?r.slice(0,i+1)+"."+r.slice(i+1):r+new Array(i-r.length+2).join("0")}Jc.prototype=tf.prototype,tf.prototype.toString=function(){return this.fill+this.align+this.sign+this.symbol+(this.zero?"0":"")+(void 0===this.width?"":Math.max(1,0|this.width))+(this.comma?",":"")+(void 0===this.precision?"":"."+Math.max(0,0|this.precision))+(this.trim?"~":"")+this.type};var ef={"%":(t,n)=>(100*t).toFixed(n),b:t=>Math.round(t).toString(2),c:t=>t+"",d:function(t){return Math.abs(t=Math.round(t))>=1e21?t.toLocaleString("en").replace(/,/g,""):t.toString(10)},e:(t,n)=>t.toExponential(n),f:(t,n)=>t.toFixed(n),g:(t,n)=>t.toPrecision(n),o:t=>Math.round(t).toString(8),p:(t,n)=>nf(100*t,n),r:nf,s:function(t,n){var e=Wc(t,n);if(!e)return t+"";var r=e[0],i=e[1],o=i-(Kc=3*Math.max(-8,Math.min(8,Math.floor(i/3))))+1,a=r.length;return o===a?r:o>a?r+new Array(o-a+1).join("0"):o>0?r.slice(0,o)+"."+r.slice(o):"0."+new Array(1-o).join("0")+Wc(t,Math.max(0,n+o-1))[0]},X:t=>Math.round(t).toString(16).toUpperCase(),x:t=>Math.round(t).toString(16)};function rf(t){return t}var of,af=Array.prototype.map,uf=["y","z","a","f","p","n","µ","m","","k","M","G","T","P","E","Z","Y"];function cf(t){var n,e,r=void 0===t.grouping||void 0===t.thousands?rf:(n=af.call(t.grouping,Number),e=t.thousands+"",function(t,r){for(var i=t.length,o=[],a=0,u=n[0],c=0;i>0&&u>0&&(c+u+1>r&&(u=Math.max(1,r-c)),o.push(t.substring(i-=u,i+u)),!((c+=u+1)>r));)u=n[a=(a+1)%n.length];return o.reverse().join(e)}),i=void 0===t.currency?"":t.currency[0]+"",o=void 0===t.currency?"":t.currency[1]+"",a=void 0===t.decimal?".":t.decimal+"",u=void 0===t.numerals?rf:function(t){return function(n){return n.replace(/[0-9]/g,(function(n){return t[+n]}))}}(af.call(t.numerals,String)),c=void 0===t.percent?"%":t.percent+"",f=void 0===t.minus?"−":t.minus+"",s=void 0===t.nan?"NaN":t.nan+"";function l(t){var n=(t=Jc(t)).fill,e=t.align,l=t.sign,h=t.symbol,d=t.zero,p=t.width,g=t.comma,y=t.precision,v=t.trim,_=t.type;"n"===_?(g=!0,_="g"):ef[_]||(void 0===y&&(y=12),v=!0,_="g"),(d||"0"===n&&"="===e)&&(d=!0,n="0",e="=");var b="$"===h?i:"#"===h&&/[boxX]/.test(_)?"0"+_.toLowerCase():"",m="$"===h?o:/[%p]/.test(_)?c:"",x=ef[_],w=/[defgprs%]/.test(_);function M(t){var i,o,c,h=b,M=m;if("c"===_)M=x(t)+M,t="";else{var T=(t=+t)<0||1/t<0;if(t=isNaN(t)?s:x(Math.abs(t),y),v&&(t=function(t){t:for(var n,e=t.length,r=1,i=-1;r0&&(i=0)}return i>0?t.slice(0,i)+t.slice(n+1):t}(t)),T&&0==+t&&"+"!==l&&(T=!1),h=(T?"("===l?l:f:"-"===l||"("===l?"":l)+h,M=("s"===_?uf[8+Kc/3]:"")+M+(T&&"("===l?")":""),w)for(i=-1,o=t.length;++i(c=t.charCodeAt(i))||c>57){M=(46===c?a+t.slice(i+1):t.slice(i))+M,t=t.slice(0,i);break}}g&&!d&&(t=r(t,1/0));var A=h.length+t.length+M.length,S=A>1)+h+t+M+S.slice(A);break;default:t=S+h+t+M}return u(t)}return y=void 0===y?6:/[gprs]/.test(_)?Math.max(1,Math.min(21,y)):Math.max(0,Math.min(20,y)),M.toString=function(){return t+""},M}return{format:l,formatPrefix:function(t,n){var e=l(((t=Jc(t)).type="f",t)),r=3*Math.max(-8,Math.min(8,Math.floor(Zc(n)/3))),i=Math.pow(10,-r),o=uf[8+r/3];return function(t){return e(i*t)+o}}}}function ff(n){return of=cf(n),t.format=of.format,t.formatPrefix=of.formatPrefix,of}function sf(t){return Math.max(0,-Zc(Math.abs(t)))}function lf(t,n){return Math.max(0,3*Math.max(-8,Math.min(8,Math.floor(Zc(n)/3)))-Zc(Math.abs(t)))}function hf(t,n){return t=Math.abs(t),n=Math.abs(n)-t,Math.max(0,Zc(n)-Zc(t))+1}t.format=void 0,t.formatPrefix=void 0,ff({thousands:",",grouping:[3],currency:["$",""]});var df=1e-6,pf=1e-12,gf=Math.PI,yf=gf/2,vf=gf/4,_f=2*gf,bf=180/gf,mf=gf/180,xf=Math.abs,wf=Math.atan,Mf=Math.atan2,Tf=Math.cos,Af=Math.ceil,Sf=Math.exp,Ef=Math.hypot,Nf=Math.log,kf=Math.pow,Cf=Math.sin,Pf=Math.sign||function(t){return t>0?1:t<0?-1:0},zf=Math.sqrt,$f=Math.tan;function Df(t){return t>1?0:t<-1?gf:Math.acos(t)}function Rf(t){return t>1?yf:t<-1?-yf:Math.asin(t)}function Ff(t){return(t=Cf(t/2))*t}function qf(){}function Uf(t,n){t&&Of.hasOwnProperty(t.type)&&Of[t.type](t,n)}var If={Feature:function(t,n){Uf(t.geometry,n)},FeatureCollection:function(t,n){for(var e=t.features,r=-1,i=e.length;++r=0?1:-1,i=r*e,o=Tf(n=(n*=mf)/2+vf),a=Cf(n),u=Vf*a,c=Gf*o+u*Tf(i),f=u*r*Cf(i);as.add(Mf(f,c)),Xf=t,Gf=o,Vf=a}function ds(t){return[Mf(t[1],t[0]),Rf(t[2])]}function ps(t){var n=t[0],e=t[1],r=Tf(e);return[r*Tf(n),r*Cf(n),Cf(e)]}function gs(t,n){return t[0]*n[0]+t[1]*n[1]+t[2]*n[2]}function ys(t,n){return[t[1]*n[2]-t[2]*n[1],t[2]*n[0]-t[0]*n[2],t[0]*n[1]-t[1]*n[0]]}function vs(t,n){t[0]+=n[0],t[1]+=n[1],t[2]+=n[2]}function _s(t,n){return[t[0]*n,t[1]*n,t[2]*n]}function bs(t){var n=zf(t[0]*t[0]+t[1]*t[1]+t[2]*t[2]);t[0]/=n,t[1]/=n,t[2]/=n}var ms,xs,ws,Ms,Ts,As,Ss,Es,Ns,ks,Cs,Ps,zs,$s,Ds,Rs,Fs={point:qs,lineStart:Is,lineEnd:Os,polygonStart:function(){Fs.point=Bs,Fs.lineStart=Ys,Fs.lineEnd=Ls,rs=new T,cs.polygonStart()},polygonEnd:function(){cs.polygonEnd(),Fs.point=qs,Fs.lineStart=Is,Fs.lineEnd=Os,as<0?(Wf=-(Kf=180),Zf=-(Qf=90)):rs>df?Qf=90:rs<-df&&(Zf=-90),os[0]=Wf,os[1]=Kf},sphere:function(){Wf=-(Kf=180),Zf=-(Qf=90)}};function qs(t,n){is.push(os=[Wf=t,Kf=t]),nQf&&(Qf=n)}function Us(t,n){var e=ps([t*mf,n*mf]);if(es){var r=ys(es,e),i=ys([r[1],-r[0],0],r);bs(i),i=ds(i);var o,a=t-Jf,u=a>0?1:-1,c=i[0]*bf*u,f=xf(a)>180;f^(u*JfQf&&(Qf=o):f^(u*Jf<(c=(c+360)%360-180)&&cQf&&(Qf=n)),f?tjs(Wf,Kf)&&(Kf=t):js(t,Kf)>js(Wf,Kf)&&(Wf=t):Kf>=Wf?(tKf&&(Kf=t)):t>Jf?js(Wf,t)>js(Wf,Kf)&&(Kf=t):js(t,Kf)>js(Wf,Kf)&&(Wf=t)}else is.push(os=[Wf=t,Kf=t]);nQf&&(Qf=n),es=e,Jf=t}function Is(){Fs.point=Us}function Os(){os[0]=Wf,os[1]=Kf,Fs.point=qs,es=null}function Bs(t,n){if(es){var e=t-Jf;rs.add(xf(e)>180?e+(e>0?360:-360):e)}else ts=t,ns=n;cs.point(t,n),Us(t,n)}function Ys(){cs.lineStart()}function Ls(){Bs(ts,ns),cs.lineEnd(),xf(rs)>df&&(Wf=-(Kf=180)),os[0]=Wf,os[1]=Kf,es=null}function js(t,n){return(n-=t)<0?n+360:n}function Hs(t,n){return t[0]-n[0]}function Xs(t,n){return t[0]<=t[1]?t[0]<=n&&n<=t[1]:ngf&&(t-=Math.round(t/_f)*_f),[t,n]}function ul(t,n,e){return(t%=_f)?n||e?ol(fl(t),sl(n,e)):fl(t):n||e?sl(n,e):al}function cl(t){return function(n,e){return xf(n+=t)>gf&&(n-=Math.round(n/_f)*_f),[n,e]}}function fl(t){var n=cl(t);return n.invert=cl(-t),n}function sl(t,n){var e=Tf(t),r=Cf(t),i=Tf(n),o=Cf(n);function a(t,n){var a=Tf(n),u=Tf(t)*a,c=Cf(t)*a,f=Cf(n),s=f*e+u*r;return[Mf(c*i-s*o,u*e-f*r),Rf(s*i+c*o)]}return a.invert=function(t,n){var a=Tf(n),u=Tf(t)*a,c=Cf(t)*a,f=Cf(n),s=f*i-c*o;return[Mf(c*i+f*o,u*e+s*r),Rf(s*e-u*r)]},a}function ll(t){function n(n){return(n=t(n[0]*mf,n[1]*mf))[0]*=bf,n[1]*=bf,n}return t=ul(t[0]*mf,t[1]*mf,t.length>2?t[2]*mf:0),n.invert=function(n){return(n=t.invert(n[0]*mf,n[1]*mf))[0]*=bf,n[1]*=bf,n},n}function hl(t,n,e,r,i,o){if(e){var a=Tf(n),u=Cf(n),c=r*e;null==i?(i=n+r*_f,o=n-c/2):(i=dl(a,i),o=dl(a,o),(r>0?io)&&(i+=r*_f));for(var f,s=i;r>0?s>o:s1&&n.push(n.pop().concat(n.shift()))},result:function(){var e=n;return n=[],t=null,e}}}function gl(t,n){return xf(t[0]-n[0])=0;--o)i.point((s=f[o])[0],s[1]);else r(h.x,h.p.x,-1,i);h=h.p}f=(h=h.o).z,d=!d}while(!h.v);i.lineEnd()}}}function _l(t){if(n=t.length){for(var n,e,r=0,i=t[0];++r=0?1:-1,E=S*A,N=E>gf,k=y*w;if(c.add(Mf(k*S*Cf(E),v*M+k*Tf(E))),a+=N?A+S*_f:A,N^p>=e^m>=e){var C=ys(ps(d),ps(b));bs(C);var P=ys(o,C);bs(P);var z=(N^A>=0?-1:1)*Rf(P[2]);(r>z||r===z&&(C[0]||C[1]))&&(u+=N^A>=0?1:-1)}}return(a<-df||a0){for(l||(i.polygonStart(),l=!0),i.lineStart(),t=0;t1&&2&c&&h.push(h.pop().concat(h.shift())),a.push(h.filter(wl))}return h}}function wl(t){return t.length>1}function Ml(t,n){return((t=t.x)[0]<0?t[1]-yf-df:yf-t[1])-((n=n.x)[0]<0?n[1]-yf-df:yf-n[1])}al.invert=al;var Tl=xl((function(){return!0}),(function(t){var n,e=NaN,r=NaN,i=NaN;return{lineStart:function(){t.lineStart(),n=1},point:function(o,a){var u=o>0?gf:-gf,c=xf(o-e);xf(c-gf)0?yf:-yf),t.point(i,r),t.lineEnd(),t.lineStart(),t.point(u,r),t.point(o,r),n=0):i!==u&&c>=gf&&(xf(e-i)df?wf((Cf(n)*(o=Tf(r))*Cf(e)-Cf(r)*(i=Tf(n))*Cf(t))/(i*o*a)):(n+r)/2}(e,r,o,a),t.point(i,r),t.lineEnd(),t.lineStart(),t.point(u,r),n=0),t.point(e=o,r=a),i=u},lineEnd:function(){t.lineEnd(),e=r=NaN},clean:function(){return 2-n}}}),(function(t,n,e,r){var i;if(null==t)i=e*yf,r.point(-gf,i),r.point(0,i),r.point(gf,i),r.point(gf,0),r.point(gf,-i),r.point(0,-i),r.point(-gf,-i),r.point(-gf,0),r.point(-gf,i);else if(xf(t[0]-n[0])>df){var o=t[0]0,i=xf(n)>df;function o(t,e){return Tf(t)*Tf(e)>n}function a(t,e,r){var i=[1,0,0],o=ys(ps(t),ps(e)),a=gs(o,o),u=o[0],c=a-u*u;if(!c)return!r&&t;var f=n*a/c,s=-n*u/c,l=ys(i,o),h=_s(i,f);vs(h,_s(o,s));var d=l,p=gs(h,d),g=gs(d,d),y=p*p-g*(gs(h,h)-1);if(!(y<0)){var v=zf(y),_=_s(d,(-p-v)/g);if(vs(_,h),_=ds(_),!r)return _;var b,m=t[0],x=e[0],w=t[1],M=e[1];x0^_[1]<(xf(_[0]-m)gf^(m<=_[0]&&_[0]<=x)){var S=_s(d,(-p+v)/g);return vs(S,h),[_,ds(S)]}}}function u(n,e){var i=r?t:gf-t,o=0;return n<-i?o|=1:n>i&&(o|=2),e<-i?o|=4:e>i&&(o|=8),o}return xl(o,(function(t){var n,e,c,f,s;return{lineStart:function(){f=c=!1,s=1},point:function(l,h){var d,p=[l,h],g=o(l,h),y=r?g?0:u(l,h):g?u(l+(l<0?gf:-gf),h):0;if(!n&&(f=c=g)&&t.lineStart(),g!==c&&(!(d=a(n,p))||gl(n,d)||gl(p,d))&&(p[2]=1),g!==c)s=0,g?(t.lineStart(),d=a(p,n),t.point(d[0],d[1])):(d=a(n,p),t.point(d[0],d[1],2),t.lineEnd()),n=d;else if(i&&n&&r^g){var v;y&e||!(v=a(p,n,!0))||(s=0,r?(t.lineStart(),t.point(v[0][0],v[0][1]),t.point(v[1][0],v[1][1]),t.lineEnd()):(t.point(v[1][0],v[1][1]),t.lineEnd(),t.lineStart(),t.point(v[0][0],v[0][1],3)))}!g||n&&gl(n,p)||t.point(p[0],p[1]),n=p,c=g,e=y},lineEnd:function(){c&&t.lineEnd(),n=null},clean:function(){return s|(f&&c)<<1}}}),(function(n,r,i,o){hl(o,t,e,i,n,r)}),r?[0,-t]:[-gf,t-gf])}var Sl,El,Nl,kl,Cl=1e9,Pl=-Cl;function zl(t,n,e,r){function i(i,o){return t<=i&&i<=e&&n<=o&&o<=r}function o(i,o,u,f){var s=0,l=0;if(null==i||(s=a(i,u))!==(l=a(o,u))||c(i,o)<0^u>0)do{f.point(0===s||3===s?t:e,s>1?r:n)}while((s=(s+u+4)%4)!==l);else f.point(o[0],o[1])}function a(r,i){return xf(r[0]-t)0?0:3:xf(r[0]-e)0?2:1:xf(r[1]-n)0?1:0:i>0?3:2}function u(t,n){return c(t.x,n.x)}function c(t,n){var e=a(t,1),r=a(n,1);return e!==r?e-r:0===e?n[1]-t[1]:1===e?t[0]-n[0]:2===e?t[1]-n[1]:n[0]-t[0]}return function(a){var c,f,s,l,h,d,p,g,y,v,_,b=a,m=pl(),x={point:w,lineStart:function(){x.point=M,f&&f.push(s=[]);v=!0,y=!1,p=g=NaN},lineEnd:function(){c&&(M(l,h),d&&y&&m.rejoin(),c.push(m.result()));x.point=w,y&&b.lineEnd()},polygonStart:function(){b=m,c=[],f=[],_=!0},polygonEnd:function(){var n=function(){for(var n=0,e=0,i=f.length;er&&(h-o)*(r-a)>(d-a)*(t-o)&&++n:d<=r&&(h-o)*(r-a)<(d-a)*(t-o)&&--n;return n}(),e=_&&n,i=(c=ft(c)).length;(e||i)&&(a.polygonStart(),e&&(a.lineStart(),o(null,null,1,a),a.lineEnd()),i&&vl(c,u,n,o,a),a.polygonEnd());b=a,c=f=s=null}};function w(t,n){i(t,n)&&b.point(t,n)}function M(o,a){var u=i(o,a);if(f&&s.push([o,a]),v)l=o,h=a,d=u,v=!1,u&&(b.lineStart(),b.point(o,a));else if(u&&y)b.point(o,a);else{var c=[p=Math.max(Pl,Math.min(Cl,p)),g=Math.max(Pl,Math.min(Cl,g))],m=[o=Math.max(Pl,Math.min(Cl,o)),a=Math.max(Pl,Math.min(Cl,a))];!function(t,n,e,r,i,o){var a,u=t[0],c=t[1],f=0,s=1,l=n[0]-u,h=n[1]-c;if(a=e-u,l||!(a>0)){if(a/=l,l<0){if(a0){if(a>s)return;a>f&&(f=a)}if(a=i-u,l||!(a<0)){if(a/=l,l<0){if(a>s)return;a>f&&(f=a)}else if(l>0){if(a0)){if(a/=h,h<0){if(a0){if(a>s)return;a>f&&(f=a)}if(a=o-c,h||!(a<0)){if(a/=h,h<0){if(a>s)return;a>f&&(f=a)}else if(h>0){if(a0&&(t[0]=u+f*l,t[1]=c+f*h),s<1&&(n[0]=u+s*l,n[1]=c+s*h),!0}}}}}(c,m,t,n,e,r)?u&&(b.lineStart(),b.point(o,a),_=!1):(y||(b.lineStart(),b.point(c[0],c[1])),b.point(m[0],m[1]),u||b.lineEnd(),_=!1)}p=o,g=a,y=u}return x}}var $l={sphere:qf,point:qf,lineStart:function(){$l.point=Rl,$l.lineEnd=Dl},lineEnd:qf,polygonStart:qf,polygonEnd:qf};function Dl(){$l.point=$l.lineEnd=qf}function Rl(t,n){El=t*=mf,Nl=Cf(n*=mf),kl=Tf(n),$l.point=Fl}function Fl(t,n){t*=mf;var e=Cf(n*=mf),r=Tf(n),i=xf(t-El),o=Tf(i),a=r*Cf(i),u=kl*e-Nl*r*o,c=Nl*e+kl*r*o;Sl.add(Mf(zf(a*a+u*u),c)),El=t,Nl=e,kl=r}function ql(t){return Sl=new T,Lf(t,$l),+Sl}var Ul=[null,null],Il={type:"LineString",coordinates:Ul};function Ol(t,n){return Ul[0]=t,Ul[1]=n,ql(Il)}var Bl={Feature:function(t,n){return Ll(t.geometry,n)},FeatureCollection:function(t,n){for(var e=t.features,r=-1,i=e.length;++r0&&(i=Ol(t[o],t[o-1]))>0&&e<=i&&r<=i&&(e+r-i)*(1-Math.pow((e-r)/i,2))df})).map(c)).concat(lt(Af(o/d)*d,i,d).filter((function(t){return xf(t%g)>df})).map(f))}return v.lines=function(){return _().map((function(t){return{type:"LineString",coordinates:t}}))},v.outline=function(){return{type:"Polygon",coordinates:[s(r).concat(l(a).slice(1),s(e).reverse().slice(1),l(u).reverse().slice(1))]}},v.extent=function(t){return arguments.length?v.extentMajor(t).extentMinor(t):v.extentMinor()},v.extentMajor=function(t){return arguments.length?(r=+t[0][0],e=+t[1][0],u=+t[0][1],a=+t[1][1],r>e&&(t=r,r=e,e=t),u>a&&(t=u,u=a,a=t),v.precision(y)):[[r,u],[e,a]]},v.extentMinor=function(e){return arguments.length?(n=+e[0][0],t=+e[1][0],o=+e[0][1],i=+e[1][1],n>t&&(e=n,n=t,t=e),o>i&&(e=o,o=i,i=e),v.precision(y)):[[n,o],[t,i]]},v.step=function(t){return arguments.length?v.stepMajor(t).stepMinor(t):v.stepMinor()},v.stepMajor=function(t){return arguments.length?(p=+t[0],g=+t[1],v):[p,g]},v.stepMinor=function(t){return arguments.length?(h=+t[0],d=+t[1],v):[h,d]},v.precision=function(h){return arguments.length?(y=+h,c=Wl(o,i,90),f=Zl(n,t,y),s=Wl(u,a,90),l=Zl(r,e,y),v):y},v.extentMajor([[-180,-90+df],[180,90-df]]).extentMinor([[-180,-80-df],[180,80+df]])}var Ql,Jl,th,nh,eh=t=>t,rh=new T,ih=new T,oh={point:qf,lineStart:qf,lineEnd:qf,polygonStart:function(){oh.lineStart=ah,oh.lineEnd=fh},polygonEnd:function(){oh.lineStart=oh.lineEnd=oh.point=qf,rh.add(xf(ih)),ih=new T},result:function(){var t=rh/2;return rh=new T,t}};function ah(){oh.point=uh}function uh(t,n){oh.point=ch,Ql=th=t,Jl=nh=n}function ch(t,n){ih.add(nh*t-th*n),th=t,nh=n}function fh(){ch(Ql,Jl)}var sh=oh,lh=1/0,hh=lh,dh=-lh,ph=dh,gh={point:function(t,n){tdh&&(dh=t);nph&&(ph=n)},lineStart:qf,lineEnd:qf,polygonStart:qf,polygonEnd:qf,result:function(){var t=[[lh,hh],[dh,ph]];return dh=ph=-(hh=lh=1/0),t}};var yh,vh,_h,bh,mh=gh,xh=0,wh=0,Mh=0,Th=0,Ah=0,Sh=0,Eh=0,Nh=0,kh=0,Ch={point:Ph,lineStart:zh,lineEnd:Rh,polygonStart:function(){Ch.lineStart=Fh,Ch.lineEnd=qh},polygonEnd:function(){Ch.point=Ph,Ch.lineStart=zh,Ch.lineEnd=Rh},result:function(){var t=kh?[Eh/kh,Nh/kh]:Sh?[Th/Sh,Ah/Sh]:Mh?[xh/Mh,wh/Mh]:[NaN,NaN];return xh=wh=Mh=Th=Ah=Sh=Eh=Nh=kh=0,t}};function Ph(t,n){xh+=t,wh+=n,++Mh}function zh(){Ch.point=$h}function $h(t,n){Ch.point=Dh,Ph(_h=t,bh=n)}function Dh(t,n){var e=t-_h,r=n-bh,i=zf(e*e+r*r);Th+=i*(_h+t)/2,Ah+=i*(bh+n)/2,Sh+=i,Ph(_h=t,bh=n)}function Rh(){Ch.point=Ph}function Fh(){Ch.point=Uh}function qh(){Ih(yh,vh)}function Uh(t,n){Ch.point=Ih,Ph(yh=_h=t,vh=bh=n)}function Ih(t,n){var e=t-_h,r=n-bh,i=zf(e*e+r*r);Th+=i*(_h+t)/2,Ah+=i*(bh+n)/2,Sh+=i,Eh+=(i=bh*t-_h*n)*(_h+t),Nh+=i*(bh+n),kh+=3*i,Ph(_h=t,bh=n)}var Oh=Ch;function Bh(t){this._context=t}Bh.prototype={_radius:4.5,pointRadius:function(t){return this._radius=t,this},polygonStart:function(){this._line=0},polygonEnd:function(){this._line=NaN},lineStart:function(){this._point=0},lineEnd:function(){0===this._line&&this._context.closePath(),this._point=NaN},point:function(t,n){switch(this._point){case 0:this._context.moveTo(t,n),this._point=1;break;case 1:this._context.lineTo(t,n);break;default:this._context.moveTo(t+this._radius,n),this._context.arc(t,n,this._radius,0,_f)}},result:qf};var Yh,Lh,jh,Hh,Xh,Gh=new T,Vh={point:qf,lineStart:function(){Vh.point=Wh},lineEnd:function(){Yh&&Zh(Lh,jh),Vh.point=qf},polygonStart:function(){Yh=!0},polygonEnd:function(){Yh=null},result:function(){var t=+Gh;return Gh=new T,t}};function Wh(t,n){Vh.point=Zh,Lh=Hh=t,jh=Xh=n}function Zh(t,n){Hh-=t,Xh-=n,Gh.add(zf(Hh*Hh+Xh*Xh)),Hh=t,Xh=n}var Kh=Vh;let Qh,Jh,td,nd;class ed{constructor(t){this._append=null==t?rd:function(t){const n=Math.floor(t);if(!(n>=0))throw new RangeError(`invalid digits: ${t}`);if(n>15)return rd;if(n!==Qh){const t=10**n;Qh=n,Jh=function(n){let e=1;this._+=n[0];for(const r=n.length;e4*n&&g--){var m=a+h,x=u+d,w=c+p,M=zf(m*m+x*x+w*w),T=Rf(w/=M),A=xf(xf(w)-1)n||xf((v*k+_*C)/b-.5)>.3||a*h+u*d+c*p2?t[2]%360*mf:0,k()):[y*bf,v*bf,_*bf]},E.angle=function(t){return arguments.length?(b=t%360*mf,k()):b*bf},E.reflectX=function(t){return arguments.length?(m=t?-1:1,k()):m<0},E.reflectY=function(t){return arguments.length?(x=t?-1:1,k()):x<0},E.precision=function(t){return arguments.length?(a=dd(u,S=t*t),C()):zf(S)},E.fitExtent=function(t,n){return ud(E,t,n)},E.fitSize=function(t,n){return cd(E,t,n)},E.fitWidth=function(t,n){return fd(E,t,n)},E.fitHeight=function(t,n){return sd(E,t,n)},function(){return n=t.apply(this,arguments),E.invert=n.invert&&N,k()}}function _d(t){var n=0,e=gf/3,r=vd(t),i=r(n,e);return i.parallels=function(t){return arguments.length?r(n=t[0]*mf,e=t[1]*mf):[n*bf,e*bf]},i}function bd(t,n){var e=Cf(t),r=(e+Cf(n))/2;if(xf(r)0?n<-yf+df&&(n=-yf+df):n>yf-df&&(n=yf-df);var e=i/kf(Nd(n),r);return[e*Cf(r*t),i-e*Tf(r*t)]}return o.invert=function(t,n){var e=i-n,o=Pf(r)*zf(t*t+e*e),a=Mf(t,xf(e))*Pf(e);return e*r<0&&(a-=gf*Pf(t)*Pf(e)),[a/r,2*wf(kf(i/o,1/r))-yf]},o}function Cd(t,n){return[t,n]}function Pd(t,n){var e=Tf(t),r=t===n?Cf(t):(e-Tf(n))/(n-t),i=e/r+t;if(xf(r)=0;)n+=e[r].value;else n=1;t.value=n}function Gd(t,n){t instanceof Map?(t=[void 0,t],void 0===n&&(n=Wd)):void 0===n&&(n=Vd);for(var e,r,i,o,a,u=new Qd(t),c=[u];e=c.pop();)if((i=n(e.data))&&(a=(i=Array.from(i)).length))for(e.children=i,o=a-1;o>=0;--o)c.push(r=i[o]=new Qd(i[o])),r.parent=e,r.depth=e.depth+1;return u.eachBefore(Kd)}function Vd(t){return t.children}function Wd(t){return Array.isArray(t)?t[1]:null}function Zd(t){void 0!==t.data.value&&(t.value=t.data.value),t.data=t.data.data}function Kd(t){var n=0;do{t.height=n}while((t=t.parent)&&t.height<++n)}function Qd(t){this.data=t,this.depth=this.height=0,this.parent=null}function Jd(t){return null==t?null:tp(t)}function tp(t){if("function"!=typeof t)throw new Error;return t}function np(){return 0}function ep(t){return function(){return t}}qd.invert=function(t,n){for(var e,r=n,i=r*r,o=i*i*i,a=0;a<12&&(o=(i=(r-=e=(r*(zd+$d*i+o*(Dd+Rd*i))-n)/(zd+3*$d*i+o*(7*Dd+9*Rd*i)))*r)*i*i,!(xf(e)df&&--i>0);return[t/(.8707+(o=r*r)*(o*(o*o*o*(.003971-.001529*o)-.013791)-.131979)),r]},Od.invert=Md(Rf),Bd.invert=Md((function(t){return 2*wf(t)})),Yd.invert=function(t,n){return[-n,2*wf(Sf(t))-yf]},Qd.prototype=Gd.prototype={constructor:Qd,count:function(){return this.eachAfter(Xd)},each:function(t,n){let e=-1;for(const r of this)t.call(n,r,++e,this);return this},eachAfter:function(t,n){for(var e,r,i,o=this,a=[o],u=[],c=-1;o=a.pop();)if(u.push(o),e=o.children)for(r=0,i=e.length;r=0;--r)o.push(e[r]);return this},find:function(t,n){let e=-1;for(const r of this)if(t.call(n,r,++e,this))return r},sum:function(t){return this.eachAfter((function(n){for(var e=+t(n.data)||0,r=n.children,i=r&&r.length;--i>=0;)e+=r[i].value;n.value=e}))},sort:function(t){return this.eachBefore((function(n){n.children&&n.children.sort(t)}))},path:function(t){for(var n=this,e=function(t,n){if(t===n)return t;var e=t.ancestors(),r=n.ancestors(),i=null;t=e.pop(),n=r.pop();for(;t===n;)i=t,t=e.pop(),n=r.pop();return i}(n,t),r=[n];n!==e;)n=n.parent,r.push(n);for(var i=r.length;t!==e;)r.splice(i,0,t),t=t.parent;return r},ancestors:function(){for(var t=this,n=[t];t=t.parent;)n.push(t);return n},descendants:function(){return Array.from(this)},leaves:function(){var t=[];return this.eachBefore((function(n){n.children||t.push(n)})),t},links:function(){var t=this,n=[];return t.each((function(e){e!==t&&n.push({source:e.parent,target:e})})),n},copy:function(){return Gd(this).eachBefore(Zd)},[Symbol.iterator]:function*(){var t,n,e,r,i=this,o=[i];do{for(t=o.reverse(),o=[];i=t.pop();)if(yield i,n=i.children)for(e=0,r=n.length;e(t=(rp*t+ip)%op)/op}function up(t,n){for(var e,r,i=0,o=(t=function(t,n){let e,r,i=t.length;for(;i;)r=n()*i--|0,e=t[i],t[i]=t[r],t[r]=e;return t}(Array.from(t),n)).length,a=[];i0&&e*e>r*r+i*i}function lp(t,n){for(var e=0;e1e-6?(E+Math.sqrt(E*E-4*S*N))/(2*S):N/E);return{x:r+w+M*k,y:i+T+A*k,r:k}}function gp(t,n,e){var r,i,o,a,u=t.x-n.x,c=t.y-n.y,f=u*u+c*c;f?(i=n.r+e.r,i*=i,a=t.r+e.r,i>(a*=a)?(r=(f+a-i)/(2*f),o=Math.sqrt(Math.max(0,a/f-r*r)),e.x=t.x-r*u-o*c,e.y=t.y-r*c+o*u):(r=(f+i-a)/(2*f),o=Math.sqrt(Math.max(0,i/f-r*r)),e.x=n.x+r*u-o*c,e.y=n.y+r*c+o*u)):(e.x=n.x+e.r,e.y=n.y)}function yp(t,n){var e=t.r+n.r-1e-6,r=n.x-t.x,i=n.y-t.y;return e>0&&e*e>r*r+i*i}function vp(t){var n=t._,e=t.next._,r=n.r+e.r,i=(n.x*e.r+e.x*n.r)/r,o=(n.y*e.r+e.y*n.r)/r;return i*i+o*o}function _p(t){this._=t,this.next=null,this.previous=null}function bp(t,n){if(!(o=(t=function(t){return"object"==typeof t&&"length"in t?t:Array.from(t)}(t)).length))return 0;var e,r,i,o,a,u,c,f,s,l,h;if((e=t[0]).x=0,e.y=0,!(o>1))return e.r;if(r=t[1],e.x=-r.r,r.x=e.r,r.y=0,!(o>2))return e.r+r.r;gp(r,e,i=t[2]),e=new _p(e),r=new _p(r),i=new _p(i),e.next=i.previous=r,r.next=e.previous=i,i.next=r.previous=e;t:for(c=3;c1&&!zp(t,n););return t.slice(0,n)}function zp(t,n){if("/"===t[n]){let e=0;for(;n>0&&"\\"===t[--n];)++e;if(!(1&e))return!0}return!1}function $p(t,n){return t.parent===n.parent?1:2}function Dp(t){var n=t.children;return n?n[0]:t.t}function Rp(t){var n=t.children;return n?n[n.length-1]:t.t}function Fp(t,n,e){var r=e/(n.i-t.i);n.c-=r,n.s+=e,t.c+=r,n.z+=e,n.m+=e}function qp(t,n,e){return t.a.parent===n.parent?t.a:e}function Up(t,n){this._=t,this.parent=null,this.children=null,this.A=null,this.a=this,this.z=0,this.m=0,this.c=0,this.s=0,this.t=null,this.i=n}function Ip(t,n,e,r,i){for(var o,a=t.children,u=-1,c=a.length,f=t.value&&(i-e)/t.value;++uh&&(h=u),y=s*s*g,(d=Math.max(h/y,y/l))>p){s-=u;break}p=d}v.push(a={value:s,dice:c1?n:1)},e}(Op);var Lp=function t(n){function e(t,e,r,i,o){if((a=t._squarify)&&a.ratio===n)for(var a,u,c,f,s,l=-1,h=a.length,d=t.value;++l1?n:1)},e}(Op);function jp(t,n,e){return(n[0]-t[0])*(e[1]-t[1])-(n[1]-t[1])*(e[0]-t[0])}function Hp(t,n){return t[0]-n[0]||t[1]-n[1]}function Xp(t){const n=t.length,e=[0,1];let r,i=2;for(r=2;r1&&jp(t[e[i-2]],t[e[i-1]],t[r])<=0;)--i;e[i++]=r}return e.slice(0,i)}var Gp=Math.random,Vp=function t(n){function e(t,e){return t=null==t?0:+t,e=null==e?1:+e,1===arguments.length?(e=t,t=0):e-=t,function(){return n()*e+t}}return e.source=t,e}(Gp),Wp=function t(n){function e(t,e){return arguments.length<2&&(e=t,t=0),t=Math.floor(t),e=Math.floor(e)-t,function(){return Math.floor(n()*e+t)}}return e.source=t,e}(Gp),Zp=function t(n){function e(t,e){var r,i;return t=null==t?0:+t,e=null==e?1:+e,function(){var o;if(null!=r)o=r,r=null;else do{r=2*n()-1,o=2*n()-1,i=r*r+o*o}while(!i||i>1);return t+e*o*Math.sqrt(-2*Math.log(i)/i)}}return e.source=t,e}(Gp),Kp=function t(n){var e=Zp.source(n);function r(){var t=e.apply(this,arguments);return function(){return Math.exp(t())}}return r.source=t,r}(Gp),Qp=function t(n){function e(t){return(t=+t)<=0?()=>0:function(){for(var e=0,r=t;r>1;--r)e+=n();return e+r*n()}}return e.source=t,e}(Gp),Jp=function t(n){var e=Qp.source(n);function r(t){if(0==(t=+t))return n;var r=e(t);return function(){return r()/t}}return r.source=t,r}(Gp),tg=function t(n){function e(t){return function(){return-Math.log1p(-n())/t}}return e.source=t,e}(Gp),ng=function t(n){function e(t){if((t=+t)<0)throw new RangeError("invalid alpha");return t=1/-t,function(){return Math.pow(1-n(),t)}}return e.source=t,e}(Gp),eg=function t(n){function e(t){if((t=+t)<0||t>1)throw new RangeError("invalid p");return function(){return Math.floor(n()+t)}}return e.source=t,e}(Gp),rg=function t(n){function e(t){if((t=+t)<0||t>1)throw new RangeError("invalid p");return 0===t?()=>1/0:1===t?()=>1:(t=Math.log1p(-t),function(){return 1+Math.floor(Math.log1p(-n())/t)})}return e.source=t,e}(Gp),ig=function t(n){var e=Zp.source(n)();function r(t,r){if((t=+t)<0)throw new RangeError("invalid k");if(0===t)return()=>0;if(r=null==r?1:+r,1===t)return()=>-Math.log1p(-n())*r;var i=(t<1?t+1:t)-1/3,o=1/(3*Math.sqrt(i)),a=t<1?()=>Math.pow(n(),1/t):()=>1;return function(){do{do{var t=e(),u=1+o*t}while(u<=0);u*=u*u;var c=1-n()}while(c>=1-.0331*t*t*t*t&&Math.log(c)>=.5*t*t+i*(1-u+Math.log(u)));return i*u*a()*r}}return r.source=t,r}(Gp),og=function t(n){var e=ig.source(n);function r(t,n){var r=e(t),i=e(n);return function(){var t=r();return 0===t?0:t/(t+i())}}return r.source=t,r}(Gp),ag=function t(n){var e=rg.source(n),r=og.source(n);function i(t,n){return t=+t,(n=+n)>=1?()=>t:n<=0?()=>0:function(){for(var i=0,o=t,a=n;o*a>16&&o*(1-a)>16;){var u=Math.floor((o+1)*a),c=r(u,o-u+1)();c<=a?(i+=u,o-=u,a=(a-c)/(1-c)):(o=u-1,a/=c)}for(var f=a<.5,s=e(f?a:1-a),l=s(),h=0;l<=o;++h)l+=s();return i+(f?h:o-h)}}return i.source=t,i}(Gp),ug=function t(n){function e(t,e,r){var i;return 0==(t=+t)?i=t=>-Math.log(t):(t=1/t,i=n=>Math.pow(n,t)),e=null==e?0:+e,r=null==r?1:+r,function(){return e+r*i(-Math.log1p(-n()))}}return e.source=t,e}(Gp),cg=function t(n){function e(t,e){return t=null==t?0:+t,e=null==e?1:+e,function(){return t+e*Math.tan(Math.PI*n())}}return e.source=t,e}(Gp),fg=function t(n){function e(t,e){return t=null==t?0:+t,e=null==e?1:+e,function(){var r=n();return t+e*Math.log(r/(1-r))}}return e.source=t,e}(Gp),sg=function t(n){var e=ig.source(n),r=ag.source(n);function i(t){return function(){for(var i=0,o=t;o>16;){var a=Math.floor(.875*o),u=e(a)();if(u>o)return i+r(a-1,o/u)();i+=a,o-=u}for(var c=-Math.log1p(-n()),f=0;c<=o;++f)c-=Math.log1p(-n());return i+f}}return i.source=t,i}(Gp);const lg=1/4294967296;function hg(t,n){switch(arguments.length){case 0:break;case 1:this.range(t);break;default:this.range(n).domain(t)}return this}function dg(t,n){switch(arguments.length){case 0:break;case 1:"function"==typeof t?this.interpolator(t):this.range(t);break;default:this.domain(t),"function"==typeof n?this.interpolator(n):this.range(n)}return this}const pg=Symbol("implicit");function gg(){var t=new InternMap,n=[],e=[],r=pg;function i(i){let o=t.get(i);if(void 0===o){if(r!==pg)return r;t.set(i,o=n.push(i)-1)}return e[o%e.length]}return i.domain=function(e){if(!arguments.length)return n.slice();n=[],t=new InternMap;for(const r of e)t.has(r)||t.set(r,n.push(r)-1);return i},i.range=function(t){return arguments.length?(e=Array.from(t),i):e.slice()},i.unknown=function(t){return arguments.length?(r=t,i):r},i.copy=function(){return gg(n,e).unknown(r)},hg.apply(i,arguments),i}function yg(){var t,n,e=gg().unknown(void 0),r=e.domain,i=e.range,o=0,a=1,u=!1,c=0,f=0,s=.5;function l(){var e=r().length,l=an&&(e=t,t=n,n=e),function(e){return Math.max(t,Math.min(n,e))}}(a[0],a[t-1])),r=t>2?Mg:wg,i=o=null,l}function l(n){return null==n||isNaN(n=+n)?e:(i||(i=r(a.map(t),u,c)))(t(f(n)))}return l.invert=function(e){return f(n((o||(o=r(u,a.map(t),Yr)))(e)))},l.domain=function(t){return arguments.length?(a=Array.from(t,_g),s()):a.slice()},l.range=function(t){return arguments.length?(u=Array.from(t),s()):u.slice()},l.rangeRound=function(t){return u=Array.from(t),c=Vr,s()},l.clamp=function(t){return arguments.length?(f=!!t||mg,s()):f!==mg},l.interpolate=function(t){return arguments.length?(c=t,s()):c},l.unknown=function(t){return arguments.length?(e=t,l):e},function(e,r){return t=e,n=r,s()}}function Sg(){return Ag()(mg,mg)}function Eg(n,e,r,i){var o,a=W(n,e,r);switch((i=Jc(null==i?",f":i)).type){case"s":var u=Math.max(Math.abs(n),Math.abs(e));return null!=i.precision||isNaN(o=lf(a,u))||(i.precision=o),t.formatPrefix(i,u);case"":case"e":case"g":case"p":case"r":null!=i.precision||isNaN(o=hf(a,Math.max(Math.abs(n),Math.abs(e))))||(i.precision=o-("e"===i.type));break;case"f":case"%":null!=i.precision||isNaN(o=sf(a))||(i.precision=o-2*("%"===i.type))}return t.format(i)}function Ng(t){var n=t.domain;return t.ticks=function(t){var e=n();return G(e[0],e[e.length-1],null==t?10:t)},t.tickFormat=function(t,e){var r=n();return Eg(r[0],r[r.length-1],null==t?10:t,e)},t.nice=function(e){null==e&&(e=10);var r,i,o=n(),a=0,u=o.length-1,c=o[a],f=o[u],s=10;for(f0;){if((i=V(c,f,e))===r)return o[a]=c,o[u]=f,n(o);if(i>0)c=Math.floor(c/i)*i,f=Math.ceil(f/i)*i;else{if(!(i<0))break;c=Math.ceil(c*i)/i,f=Math.floor(f*i)/i}r=i}return t},t}function kg(t,n){var e,r=0,i=(t=t.slice()).length-1,o=t[r],a=t[i];return a-t(-n,e)}function Fg(n){const e=n(Cg,Pg),r=e.domain;let i,o,a=10;function u(){return i=function(t){return t===Math.E?Math.log:10===t&&Math.log10||2===t&&Math.log2||(t=Math.log(t),n=>Math.log(n)/t)}(a),o=function(t){return 10===t?Dg:t===Math.E?Math.exp:n=>Math.pow(t,n)}(a),r()[0]<0?(i=Rg(i),o=Rg(o),n(zg,$g)):n(Cg,Pg),e}return e.base=function(t){return arguments.length?(a=+t,u()):a},e.domain=function(t){return arguments.length?(r(t),u()):r()},e.ticks=t=>{const n=r();let e=n[0],u=n[n.length-1];const c=u0){for(;l<=h;++l)for(f=1;fu)break;p.push(s)}}else for(;l<=h;++l)for(f=a-1;f>=1;--f)if(s=l>0?f/o(-l):f*o(l),!(su)break;p.push(s)}2*p.length{if(null==n&&(n=10),null==r&&(r=10===a?"s":","),"function"!=typeof r&&(a%1||null!=(r=Jc(r)).precision||(r.trim=!0),r=t.format(r)),n===1/0)return r;const u=Math.max(1,a*n/e.ticks().length);return t=>{let n=t/o(Math.round(i(t)));return n*ar(kg(r(),{floor:t=>o(Math.floor(i(t))),ceil:t=>o(Math.ceil(i(t)))})),e}function qg(t){return function(n){return Math.sign(n)*Math.log1p(Math.abs(n/t))}}function Ug(t){return function(n){return Math.sign(n)*Math.expm1(Math.abs(n))*t}}function Ig(t){var n=1,e=t(qg(n),Ug(n));return e.constant=function(e){return arguments.length?t(qg(n=+e),Ug(n)):n},Ng(e)}function Og(t){return function(n){return n<0?-Math.pow(-n,t):Math.pow(n,t)}}function Bg(t){return t<0?-Math.sqrt(-t):Math.sqrt(t)}function Yg(t){return t<0?-t*t:t*t}function Lg(t){var n=t(mg,mg),e=1;return n.exponent=function(n){return arguments.length?1===(e=+n)?t(mg,mg):.5===e?t(Bg,Yg):t(Og(e),Og(1/e)):e},Ng(n)}function jg(){var t=Lg(Ag());return t.copy=function(){return Tg(t,jg()).exponent(t.exponent())},hg.apply(t,arguments),t}function Hg(t){return Math.sign(t)*t*t}const Xg=new Date,Gg=new Date;function Vg(t,n,e,r){function i(n){return t(n=0===arguments.length?new Date:new Date(+n)),n}return i.floor=n=>(t(n=new Date(+n)),n),i.ceil=e=>(t(e=new Date(e-1)),n(e,1),t(e),e),i.round=t=>{const n=i(t),e=i.ceil(t);return t-n(n(t=new Date(+t),null==e?1:Math.floor(e)),t),i.range=(e,r,o)=>{const a=[];if(e=i.ceil(e),o=null==o?1:Math.floor(o),!(e0))return a;let u;do{a.push(u=new Date(+e)),n(e,o),t(e)}while(uVg((n=>{if(n>=n)for(;t(n),!e(n);)n.setTime(n-1)}),((t,r)=>{if(t>=t)if(r<0)for(;++r<=0;)for(;n(t,-1),!e(t););else for(;--r>=0;)for(;n(t,1),!e(t););})),e&&(i.count=(n,r)=>(Xg.setTime(+n),Gg.setTime(+r),t(Xg),t(Gg),Math.floor(e(Xg,Gg))),i.every=t=>(t=Math.floor(t),isFinite(t)&&t>0?t>1?i.filter(r?n=>r(n)%t==0:n=>i.count(0,n)%t==0):i:null)),i}const Wg=Vg((()=>{}),((t,n)=>{t.setTime(+t+n)}),((t,n)=>n-t));Wg.every=t=>(t=Math.floor(t),isFinite(t)&&t>0?t>1?Vg((n=>{n.setTime(Math.floor(n/t)*t)}),((n,e)=>{n.setTime(+n+e*t)}),((n,e)=>(e-n)/t)):Wg:null);const Zg=Wg.range,Kg=1e3,Qg=6e4,Jg=36e5,ty=864e5,ny=6048e5,ey=2592e6,ry=31536e6,iy=Vg((t=>{t.setTime(t-t.getMilliseconds())}),((t,n)=>{t.setTime(+t+n*Kg)}),((t,n)=>(n-t)/Kg),(t=>t.getUTCSeconds())),oy=iy.range,ay=Vg((t=>{t.setTime(t-t.getMilliseconds()-t.getSeconds()*Kg)}),((t,n)=>{t.setTime(+t+n*Qg)}),((t,n)=>(n-t)/Qg),(t=>t.getMinutes())),uy=ay.range,cy=Vg((t=>{t.setUTCSeconds(0,0)}),((t,n)=>{t.setTime(+t+n*Qg)}),((t,n)=>(n-t)/Qg),(t=>t.getUTCMinutes())),fy=cy.range,sy=Vg((t=>{t.setTime(t-t.getMilliseconds()-t.getSeconds()*Kg-t.getMinutes()*Qg)}),((t,n)=>{t.setTime(+t+n*Jg)}),((t,n)=>(n-t)/Jg),(t=>t.getHours())),ly=sy.range,hy=Vg((t=>{t.setUTCMinutes(0,0,0)}),((t,n)=>{t.setTime(+t+n*Jg)}),((t,n)=>(n-t)/Jg),(t=>t.getUTCHours())),dy=hy.range,py=Vg((t=>t.setHours(0,0,0,0)),((t,n)=>t.setDate(t.getDate()+n)),((t,n)=>(n-t-(n.getTimezoneOffset()-t.getTimezoneOffset())*Qg)/ty),(t=>t.getDate()-1)),gy=py.range,yy=Vg((t=>{t.setUTCHours(0,0,0,0)}),((t,n)=>{t.setUTCDate(t.getUTCDate()+n)}),((t,n)=>(n-t)/ty),(t=>t.getUTCDate()-1)),vy=yy.range,_y=Vg((t=>{t.setUTCHours(0,0,0,0)}),((t,n)=>{t.setUTCDate(t.getUTCDate()+n)}),((t,n)=>(n-t)/ty),(t=>Math.floor(t/ty))),by=_y.range;function my(t){return Vg((n=>{n.setDate(n.getDate()-(n.getDay()+7-t)%7),n.setHours(0,0,0,0)}),((t,n)=>{t.setDate(t.getDate()+7*n)}),((t,n)=>(n-t-(n.getTimezoneOffset()-t.getTimezoneOffset())*Qg)/ny))}const xy=my(0),wy=my(1),My=my(2),Ty=my(3),Ay=my(4),Sy=my(5),Ey=my(6),Ny=xy.range,ky=wy.range,Cy=My.range,Py=Ty.range,zy=Ay.range,$y=Sy.range,Dy=Ey.range;function Ry(t){return Vg((n=>{n.setUTCDate(n.getUTCDate()-(n.getUTCDay()+7-t)%7),n.setUTCHours(0,0,0,0)}),((t,n)=>{t.setUTCDate(t.getUTCDate()+7*n)}),((t,n)=>(n-t)/ny))}const Fy=Ry(0),qy=Ry(1),Uy=Ry(2),Iy=Ry(3),Oy=Ry(4),By=Ry(5),Yy=Ry(6),Ly=Fy.range,jy=qy.range,Hy=Uy.range,Xy=Iy.range,Gy=Oy.range,Vy=By.range,Wy=Yy.range,Zy=Vg((t=>{t.setDate(1),t.setHours(0,0,0,0)}),((t,n)=>{t.setMonth(t.getMonth()+n)}),((t,n)=>n.getMonth()-t.getMonth()+12*(n.getFullYear()-t.getFullYear())),(t=>t.getMonth())),Ky=Zy.range,Qy=Vg((t=>{t.setUTCDate(1),t.setUTCHours(0,0,0,0)}),((t,n)=>{t.setUTCMonth(t.getUTCMonth()+n)}),((t,n)=>n.getUTCMonth()-t.getUTCMonth()+12*(n.getUTCFullYear()-t.getUTCFullYear())),(t=>t.getUTCMonth())),Jy=Qy.range,tv=Vg((t=>{t.setMonth(0,1),t.setHours(0,0,0,0)}),((t,n)=>{t.setFullYear(t.getFullYear()+n)}),((t,n)=>n.getFullYear()-t.getFullYear()),(t=>t.getFullYear()));tv.every=t=>isFinite(t=Math.floor(t))&&t>0?Vg((n=>{n.setFullYear(Math.floor(n.getFullYear()/t)*t),n.setMonth(0,1),n.setHours(0,0,0,0)}),((n,e)=>{n.setFullYear(n.getFullYear()+e*t)})):null;const nv=tv.range,ev=Vg((t=>{t.setUTCMonth(0,1),t.setUTCHours(0,0,0,0)}),((t,n)=>{t.setUTCFullYear(t.getUTCFullYear()+n)}),((t,n)=>n.getUTCFullYear()-t.getUTCFullYear()),(t=>t.getUTCFullYear()));ev.every=t=>isFinite(t=Math.floor(t))&&t>0?Vg((n=>{n.setUTCFullYear(Math.floor(n.getUTCFullYear()/t)*t),n.setUTCMonth(0,1),n.setUTCHours(0,0,0,0)}),((n,e)=>{n.setUTCFullYear(n.getUTCFullYear()+e*t)})):null;const rv=ev.range;function iv(t,n,e,i,o,a){const u=[[iy,1,Kg],[iy,5,5e3],[iy,15,15e3],[iy,30,3e4],[a,1,Qg],[a,5,3e5],[a,15,9e5],[a,30,18e5],[o,1,Jg],[o,3,108e5],[o,6,216e5],[o,12,432e5],[i,1,ty],[i,2,1728e5],[e,1,ny],[n,1,ey],[n,3,7776e6],[t,1,ry]];function c(n,e,i){const o=Math.abs(e-n)/i,a=r((([,,t])=>t)).right(u,o);if(a===u.length)return t.every(W(n/ry,e/ry,i));if(0===a)return Wg.every(Math.max(W(n,e,i),1));const[c,f]=u[o/u[a-1][2]=12)]},q:function(t){return 1+~~(t.getMonth()/3)},Q:k_,s:C_,S:Zv,u:Kv,U:Qv,V:t_,w:n_,W:e_,x:null,X:null,y:r_,Y:o_,Z:u_,"%":N_},m={a:function(t){return a[t.getUTCDay()]},A:function(t){return o[t.getUTCDay()]},b:function(t){return c[t.getUTCMonth()]},B:function(t){return u[t.getUTCMonth()]},c:null,d:c_,e:c_,f:d_,g:T_,G:S_,H:f_,I:s_,j:l_,L:h_,m:p_,M:g_,p:function(t){return i[+(t.getUTCHours()>=12)]},q:function(t){return 1+~~(t.getUTCMonth()/3)},Q:k_,s:C_,S:y_,u:v_,U:__,V:m_,w:x_,W:w_,x:null,X:null,y:M_,Y:A_,Z:E_,"%":N_},x={a:function(t,n,e){var r=d.exec(n.slice(e));return r?(t.w=p.get(r[0].toLowerCase()),e+r[0].length):-1},A:function(t,n,e){var r=l.exec(n.slice(e));return r?(t.w=h.get(r[0].toLowerCase()),e+r[0].length):-1},b:function(t,n,e){var r=v.exec(n.slice(e));return r?(t.m=_.get(r[0].toLowerCase()),e+r[0].length):-1},B:function(t,n,e){var r=g.exec(n.slice(e));return r?(t.m=y.get(r[0].toLowerCase()),e+r[0].length):-1},c:function(t,e,r){return T(t,n,e,r)},d:zv,e:zv,f:Uv,g:Nv,G:Ev,H:Dv,I:Dv,j:$v,L:qv,m:Pv,M:Rv,p:function(t,n,e){var r=f.exec(n.slice(e));return r?(t.p=s.get(r[0].toLowerCase()),e+r[0].length):-1},q:Cv,Q:Ov,s:Bv,S:Fv,u:Mv,U:Tv,V:Av,w:wv,W:Sv,x:function(t,n,r){return T(t,e,n,r)},X:function(t,n,e){return T(t,r,n,e)},y:Nv,Y:Ev,Z:kv,"%":Iv};function w(t,n){return function(e){var r,i,o,a=[],u=-1,c=0,f=t.length;for(e instanceof Date||(e=new Date(+e));++u53)return null;"w"in o||(o.w=1),"Z"in o?(i=(r=sv(lv(o.y,0,1))).getUTCDay(),r=i>4||0===i?qy.ceil(r):qy(r),r=yy.offset(r,7*(o.V-1)),o.y=r.getUTCFullYear(),o.m=r.getUTCMonth(),o.d=r.getUTCDate()+(o.w+6)%7):(i=(r=fv(lv(o.y,0,1))).getDay(),r=i>4||0===i?wy.ceil(r):wy(r),r=py.offset(r,7*(o.V-1)),o.y=r.getFullYear(),o.m=r.getMonth(),o.d=r.getDate()+(o.w+6)%7)}else("W"in o||"U"in o)&&("w"in o||(o.w="u"in o?o.u%7:"W"in o?1:0),i="Z"in o?sv(lv(o.y,0,1)).getUTCDay():fv(lv(o.y,0,1)).getDay(),o.m=0,o.d="W"in o?(o.w+6)%7+7*o.W-(i+5)%7:o.w+7*o.U-(i+6)%7);return"Z"in o?(o.H+=o.Z/100|0,o.M+=o.Z%100,sv(o)):fv(o)}}function T(t,n,e,r){for(var i,o,a=0,u=n.length,c=e.length;a=c)return-1;if(37===(i=n.charCodeAt(a++))){if(i=n.charAt(a++),!(o=x[i in pv?n.charAt(a++):i])||(r=o(t,e,r))<0)return-1}else if(i!=e.charCodeAt(r++))return-1}return r}return b.x=w(e,b),b.X=w(r,b),b.c=w(n,b),m.x=w(e,m),m.X=w(r,m),m.c=w(n,m),{format:function(t){var n=w(t+="",b);return n.toString=function(){return t},n},parse:function(t){var n=M(t+="",!1);return n.toString=function(){return t},n},utcFormat:function(t){var n=w(t+="",m);return n.toString=function(){return t},n},utcParse:function(t){var n=M(t+="",!0);return n.toString=function(){return t},n}}}var dv,pv={"-":"",_:" ",0:"0"},gv=/^\s*\d+/,yv=/^%/,vv=/[\\^$*+?|[\]().{}]/g;function _v(t,n,e){var r=t<0?"-":"",i=(r?-t:t)+"",o=i.length;return r+(o[t.toLowerCase(),n])))}function wv(t,n,e){var r=gv.exec(n.slice(e,e+1));return r?(t.w=+r[0],e+r[0].length):-1}function Mv(t,n,e){var r=gv.exec(n.slice(e,e+1));return r?(t.u=+r[0],e+r[0].length):-1}function Tv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.U=+r[0],e+r[0].length):-1}function Av(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.V=+r[0],e+r[0].length):-1}function Sv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.W=+r[0],e+r[0].length):-1}function Ev(t,n,e){var r=gv.exec(n.slice(e,e+4));return r?(t.y=+r[0],e+r[0].length):-1}function Nv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.y=+r[0]+(+r[0]>68?1900:2e3),e+r[0].length):-1}function kv(t,n,e){var r=/^(Z)|([+-]\d\d)(?::?(\d\d))?/.exec(n.slice(e,e+6));return r?(t.Z=r[1]?0:-(r[2]+(r[3]||"00")),e+r[0].length):-1}function Cv(t,n,e){var r=gv.exec(n.slice(e,e+1));return r?(t.q=3*r[0]-3,e+r[0].length):-1}function Pv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.m=r[0]-1,e+r[0].length):-1}function zv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.d=+r[0],e+r[0].length):-1}function $v(t,n,e){var r=gv.exec(n.slice(e,e+3));return r?(t.m=0,t.d=+r[0],e+r[0].length):-1}function Dv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.H=+r[0],e+r[0].length):-1}function Rv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.M=+r[0],e+r[0].length):-1}function Fv(t,n,e){var r=gv.exec(n.slice(e,e+2));return r?(t.S=+r[0],e+r[0].length):-1}function qv(t,n,e){var r=gv.exec(n.slice(e,e+3));return r?(t.L=+r[0],e+r[0].length):-1}function Uv(t,n,e){var r=gv.exec(n.slice(e,e+6));return r?(t.L=Math.floor(r[0]/1e3),e+r[0].length):-1}function Iv(t,n,e){var r=yv.exec(n.slice(e,e+1));return r?e+r[0].length:-1}function Ov(t,n,e){var r=gv.exec(n.slice(e));return r?(t.Q=+r[0],e+r[0].length):-1}function Bv(t,n,e){var r=gv.exec(n.slice(e));return r?(t.s=+r[0],e+r[0].length):-1}function Yv(t,n){return _v(t.getDate(),n,2)}function Lv(t,n){return _v(t.getHours(),n,2)}function jv(t,n){return _v(t.getHours()%12||12,n,2)}function Hv(t,n){return _v(1+py.count(tv(t),t),n,3)}function Xv(t,n){return _v(t.getMilliseconds(),n,3)}function Gv(t,n){return Xv(t,n)+"000"}function Vv(t,n){return _v(t.getMonth()+1,n,2)}function Wv(t,n){return _v(t.getMinutes(),n,2)}function Zv(t,n){return _v(t.getSeconds(),n,2)}function Kv(t){var n=t.getDay();return 0===n?7:n}function Qv(t,n){return _v(xy.count(tv(t)-1,t),n,2)}function Jv(t){var n=t.getDay();return n>=4||0===n?Ay(t):Ay.ceil(t)}function t_(t,n){return t=Jv(t),_v(Ay.count(tv(t),t)+(4===tv(t).getDay()),n,2)}function n_(t){return t.getDay()}function e_(t,n){return _v(wy.count(tv(t)-1,t),n,2)}function r_(t,n){return _v(t.getFullYear()%100,n,2)}function i_(t,n){return _v((t=Jv(t)).getFullYear()%100,n,2)}function o_(t,n){return _v(t.getFullYear()%1e4,n,4)}function a_(t,n){var e=t.getDay();return _v((t=e>=4||0===e?Ay(t):Ay.ceil(t)).getFullYear()%1e4,n,4)}function u_(t){var n=t.getTimezoneOffset();return(n>0?"-":(n*=-1,"+"))+_v(n/60|0,"0",2)+_v(n%60,"0",2)}function c_(t,n){return _v(t.getUTCDate(),n,2)}function f_(t,n){return _v(t.getUTCHours(),n,2)}function s_(t,n){return _v(t.getUTCHours()%12||12,n,2)}function l_(t,n){return _v(1+yy.count(ev(t),t),n,3)}function h_(t,n){return _v(t.getUTCMilliseconds(),n,3)}function d_(t,n){return h_(t,n)+"000"}function p_(t,n){return _v(t.getUTCMonth()+1,n,2)}function g_(t,n){return _v(t.getUTCMinutes(),n,2)}function y_(t,n){return _v(t.getUTCSeconds(),n,2)}function v_(t){var n=t.getUTCDay();return 0===n?7:n}function __(t,n){return _v(Fy.count(ev(t)-1,t),n,2)}function b_(t){var n=t.getUTCDay();return n>=4||0===n?Oy(t):Oy.ceil(t)}function m_(t,n){return t=b_(t),_v(Oy.count(ev(t),t)+(4===ev(t).getUTCDay()),n,2)}function x_(t){return t.getUTCDay()}function w_(t,n){return _v(qy.count(ev(t)-1,t),n,2)}function M_(t,n){return _v(t.getUTCFullYear()%100,n,2)}function T_(t,n){return _v((t=b_(t)).getUTCFullYear()%100,n,2)}function A_(t,n){return _v(t.getUTCFullYear()%1e4,n,4)}function S_(t,n){var e=t.getUTCDay();return _v((t=e>=4||0===e?Oy(t):Oy.ceil(t)).getUTCFullYear()%1e4,n,4)}function E_(){return"+0000"}function N_(){return"%"}function k_(t){return+t}function C_(t){return Math.floor(+t/1e3)}function P_(n){return dv=hv(n),t.timeFormat=dv.format,t.timeParse=dv.parse,t.utcFormat=dv.utcFormat,t.utcParse=dv.utcParse,dv}t.timeFormat=void 0,t.timeParse=void 0,t.utcFormat=void 0,t.utcParse=void 0,P_({dateTime:"%x, %X",date:"%-m/%-d/%Y",time:"%-I:%M:%S %p",periods:["AM","PM"],days:["Sunday","Monday","Tuesday","Wednesday","Thursday","Friday","Saturday"],shortDays:["Sun","Mon","Tue","Wed","Thu","Fri","Sat"],months:["January","February","March","April","May","June","July","August","September","October","November","December"],shortMonths:["Jan","Feb","Mar","Apr","May","Jun","Jul","Aug","Sep","Oct","Nov","Dec"]});var z_="%Y-%m-%dT%H:%M:%S.%LZ";var $_=Date.prototype.toISOString?function(t){return t.toISOString()}:t.utcFormat(z_),D_=$_;var R_=+new Date("2000-01-01T00:00:00.000Z")?function(t){var n=new Date(t);return isNaN(n)?null:n}:t.utcParse(z_),F_=R_;function q_(t){return new Date(t)}function U_(t){return t instanceof Date?+t:+new Date(+t)}function I_(t,n,e,r,i,o,a,u,c,f){var s=Sg(),l=s.invert,h=s.domain,d=f(".%L"),p=f(":%S"),g=f("%I:%M"),y=f("%I %p"),v=f("%a %d"),_=f("%b %d"),b=f("%B"),m=f("%Y");function x(t){return(c(t)Fr(t[t.length-1]),ib=new Array(3).concat("d8b365f5f5f55ab4ac","a6611adfc27d80cdc1018571","a6611adfc27df5f5f580cdc1018571","8c510ad8b365f6e8c3c7eae55ab4ac01665e","8c510ad8b365f6e8c3f5f5f5c7eae55ab4ac01665e","8c510abf812ddfc27df6e8c3c7eae580cdc135978f01665e","8c510abf812ddfc27df6e8c3f5f5f5c7eae580cdc135978f01665e","5430058c510abf812ddfc27df6e8c3c7eae580cdc135978f01665e003c30","5430058c510abf812ddfc27df6e8c3f5f5f5c7eae580cdc135978f01665e003c30").map(H_),ob=rb(ib),ab=new Array(3).concat("af8dc3f7f7f77fbf7b","7b3294c2a5cfa6dba0008837","7b3294c2a5cff7f7f7a6dba0008837","762a83af8dc3e7d4e8d9f0d37fbf7b1b7837","762a83af8dc3e7d4e8f7f7f7d9f0d37fbf7b1b7837","762a839970abc2a5cfe7d4e8d9f0d3a6dba05aae611b7837","762a839970abc2a5cfe7d4e8f7f7f7d9f0d3a6dba05aae611b7837","40004b762a839970abc2a5cfe7d4e8d9f0d3a6dba05aae611b783700441b","40004b762a839970abc2a5cfe7d4e8f7f7f7d9f0d3a6dba05aae611b783700441b").map(H_),ub=rb(ab),cb=new Array(3).concat("e9a3c9f7f7f7a1d76a","d01c8bf1b6dab8e1864dac26","d01c8bf1b6daf7f7f7b8e1864dac26","c51b7de9a3c9fde0efe6f5d0a1d76a4d9221","c51b7de9a3c9fde0eff7f7f7e6f5d0a1d76a4d9221","c51b7dde77aef1b6dafde0efe6f5d0b8e1867fbc414d9221","c51b7dde77aef1b6dafde0eff7f7f7e6f5d0b8e1867fbc414d9221","8e0152c51b7dde77aef1b6dafde0efe6f5d0b8e1867fbc414d9221276419","8e0152c51b7dde77aef1b6dafde0eff7f7f7e6f5d0b8e1867fbc414d9221276419").map(H_),fb=rb(cb),sb=new Array(3).concat("998ec3f7f7f7f1a340","5e3c99b2abd2fdb863e66101","5e3c99b2abd2f7f7f7fdb863e66101","542788998ec3d8daebfee0b6f1a340b35806","542788998ec3d8daebf7f7f7fee0b6f1a340b35806","5427888073acb2abd2d8daebfee0b6fdb863e08214b35806","5427888073acb2abd2d8daebf7f7f7fee0b6fdb863e08214b35806","2d004b5427888073acb2abd2d8daebfee0b6fdb863e08214b358067f3b08","2d004b5427888073acb2abd2d8daebf7f7f7fee0b6fdb863e08214b358067f3b08").map(H_),lb=rb(sb),hb=new Array(3).concat("ef8a62f7f7f767a9cf","ca0020f4a58292c5de0571b0","ca0020f4a582f7f7f792c5de0571b0","b2182bef8a62fddbc7d1e5f067a9cf2166ac","b2182bef8a62fddbc7f7f7f7d1e5f067a9cf2166ac","b2182bd6604df4a582fddbc7d1e5f092c5de4393c32166ac","b2182bd6604df4a582fddbc7f7f7f7d1e5f092c5de4393c32166ac","67001fb2182bd6604df4a582fddbc7d1e5f092c5de4393c32166ac053061","67001fb2182bd6604df4a582fddbc7f7f7f7d1e5f092c5de4393c32166ac053061").map(H_),db=rb(hb),pb=new Array(3).concat("ef8a62ffffff999999","ca0020f4a582bababa404040","ca0020f4a582ffffffbababa404040","b2182bef8a62fddbc7e0e0e09999994d4d4d","b2182bef8a62fddbc7ffffffe0e0e09999994d4d4d","b2182bd6604df4a582fddbc7e0e0e0bababa8787874d4d4d","b2182bd6604df4a582fddbc7ffffffe0e0e0bababa8787874d4d4d","67001fb2182bd6604df4a582fddbc7e0e0e0bababa8787874d4d4d1a1a1a","67001fb2182bd6604df4a582fddbc7ffffffe0e0e0bababa8787874d4d4d1a1a1a").map(H_),gb=rb(pb),yb=new Array(3).concat("fc8d59ffffbf91bfdb","d7191cfdae61abd9e92c7bb6","d7191cfdae61ffffbfabd9e92c7bb6","d73027fc8d59fee090e0f3f891bfdb4575b4","d73027fc8d59fee090ffffbfe0f3f891bfdb4575b4","d73027f46d43fdae61fee090e0f3f8abd9e974add14575b4","d73027f46d43fdae61fee090ffffbfe0f3f8abd9e974add14575b4","a50026d73027f46d43fdae61fee090e0f3f8abd9e974add14575b4313695","a50026d73027f46d43fdae61fee090ffffbfe0f3f8abd9e974add14575b4313695").map(H_),vb=rb(yb),_b=new Array(3).concat("fc8d59ffffbf91cf60","d7191cfdae61a6d96a1a9641","d7191cfdae61ffffbfa6d96a1a9641","d73027fc8d59fee08bd9ef8b91cf601a9850","d73027fc8d59fee08bffffbfd9ef8b91cf601a9850","d73027f46d43fdae61fee08bd9ef8ba6d96a66bd631a9850","d73027f46d43fdae61fee08bffffbfd9ef8ba6d96a66bd631a9850","a50026d73027f46d43fdae61fee08bd9ef8ba6d96a66bd631a9850006837","a50026d73027f46d43fdae61fee08bffffbfd9ef8ba6d96a66bd631a9850006837").map(H_),bb=rb(_b),mb=new Array(3).concat("fc8d59ffffbf99d594","d7191cfdae61abdda42b83ba","d7191cfdae61ffffbfabdda42b83ba","d53e4ffc8d59fee08be6f59899d5943288bd","d53e4ffc8d59fee08bffffbfe6f59899d5943288bd","d53e4ff46d43fdae61fee08be6f598abdda466c2a53288bd","d53e4ff46d43fdae61fee08bffffbfe6f598abdda466c2a53288bd","9e0142d53e4ff46d43fdae61fee08be6f598abdda466c2a53288bd5e4fa2","9e0142d53e4ff46d43fdae61fee08bffffbfe6f598abdda466c2a53288bd5e4fa2").map(H_),xb=rb(mb),wb=new Array(3).concat("e5f5f999d8c92ca25f","edf8fbb2e2e266c2a4238b45","edf8fbb2e2e266c2a42ca25f006d2c","edf8fbccece699d8c966c2a42ca25f006d2c","edf8fbccece699d8c966c2a441ae76238b45005824","f7fcfde5f5f9ccece699d8c966c2a441ae76238b45005824","f7fcfde5f5f9ccece699d8c966c2a441ae76238b45006d2c00441b").map(H_),Mb=rb(wb),Tb=new Array(3).concat("e0ecf49ebcda8856a7","edf8fbb3cde38c96c688419d","edf8fbb3cde38c96c68856a7810f7c","edf8fbbfd3e69ebcda8c96c68856a7810f7c","edf8fbbfd3e69ebcda8c96c68c6bb188419d6e016b","f7fcfde0ecf4bfd3e69ebcda8c96c68c6bb188419d6e016b","f7fcfde0ecf4bfd3e69ebcda8c96c68c6bb188419d810f7c4d004b").map(H_),Ab=rb(Tb),Sb=new Array(3).concat("e0f3dba8ddb543a2ca","f0f9e8bae4bc7bccc42b8cbe","f0f9e8bae4bc7bccc443a2ca0868ac","f0f9e8ccebc5a8ddb57bccc443a2ca0868ac","f0f9e8ccebc5a8ddb57bccc44eb3d32b8cbe08589e","f7fcf0e0f3dbccebc5a8ddb57bccc44eb3d32b8cbe08589e","f7fcf0e0f3dbccebc5a8ddb57bccc44eb3d32b8cbe0868ac084081").map(H_),Eb=rb(Sb),Nb=new Array(3).concat("fee8c8fdbb84e34a33","fef0d9fdcc8afc8d59d7301f","fef0d9fdcc8afc8d59e34a33b30000","fef0d9fdd49efdbb84fc8d59e34a33b30000","fef0d9fdd49efdbb84fc8d59ef6548d7301f990000","fff7ecfee8c8fdd49efdbb84fc8d59ef6548d7301f990000","fff7ecfee8c8fdd49efdbb84fc8d59ef6548d7301fb300007f0000").map(H_),kb=rb(Nb),Cb=new Array(3).concat("ece2f0a6bddb1c9099","f6eff7bdc9e167a9cf02818a","f6eff7bdc9e167a9cf1c9099016c59","f6eff7d0d1e6a6bddb67a9cf1c9099016c59","f6eff7d0d1e6a6bddb67a9cf3690c002818a016450","fff7fbece2f0d0d1e6a6bddb67a9cf3690c002818a016450","fff7fbece2f0d0d1e6a6bddb67a9cf3690c002818a016c59014636").map(H_),Pb=rb(Cb),zb=new Array(3).concat("ece7f2a6bddb2b8cbe","f1eef6bdc9e174a9cf0570b0","f1eef6bdc9e174a9cf2b8cbe045a8d","f1eef6d0d1e6a6bddb74a9cf2b8cbe045a8d","f1eef6d0d1e6a6bddb74a9cf3690c00570b0034e7b","fff7fbece7f2d0d1e6a6bddb74a9cf3690c00570b0034e7b","fff7fbece7f2d0d1e6a6bddb74a9cf3690c00570b0045a8d023858").map(H_),$b=rb(zb),Db=new Array(3).concat("e7e1efc994c7dd1c77","f1eef6d7b5d8df65b0ce1256","f1eef6d7b5d8df65b0dd1c77980043","f1eef6d4b9dac994c7df65b0dd1c77980043","f1eef6d4b9dac994c7df65b0e7298ace125691003f","f7f4f9e7e1efd4b9dac994c7df65b0e7298ace125691003f","f7f4f9e7e1efd4b9dac994c7df65b0e7298ace125698004367001f").map(H_),Rb=rb(Db),Fb=new Array(3).concat("fde0ddfa9fb5c51b8a","feebe2fbb4b9f768a1ae017e","feebe2fbb4b9f768a1c51b8a7a0177","feebe2fcc5c0fa9fb5f768a1c51b8a7a0177","feebe2fcc5c0fa9fb5f768a1dd3497ae017e7a0177","fff7f3fde0ddfcc5c0fa9fb5f768a1dd3497ae017e7a0177","fff7f3fde0ddfcc5c0fa9fb5f768a1dd3497ae017e7a017749006a").map(H_),qb=rb(Fb),Ub=new Array(3).concat("edf8b17fcdbb2c7fb8","ffffcca1dab441b6c4225ea8","ffffcca1dab441b6c42c7fb8253494","ffffccc7e9b47fcdbb41b6c42c7fb8253494","ffffccc7e9b47fcdbb41b6c41d91c0225ea80c2c84","ffffd9edf8b1c7e9b47fcdbb41b6c41d91c0225ea80c2c84","ffffd9edf8b1c7e9b47fcdbb41b6c41d91c0225ea8253494081d58").map(H_),Ib=rb(Ub),Ob=new Array(3).concat("f7fcb9addd8e31a354","ffffccc2e69978c679238443","ffffccc2e69978c67931a354006837","ffffccd9f0a3addd8e78c67931a354006837","ffffccd9f0a3addd8e78c67941ab5d238443005a32","ffffe5f7fcb9d9f0a3addd8e78c67941ab5d238443005a32","ffffe5f7fcb9d9f0a3addd8e78c67941ab5d238443006837004529").map(H_),Bb=rb(Ob),Yb=new Array(3).concat("fff7bcfec44fd95f0e","ffffd4fed98efe9929cc4c02","ffffd4fed98efe9929d95f0e993404","ffffd4fee391fec44ffe9929d95f0e993404","ffffd4fee391fec44ffe9929ec7014cc4c028c2d04","ffffe5fff7bcfee391fec44ffe9929ec7014cc4c028c2d04","ffffe5fff7bcfee391fec44ffe9929ec7014cc4c02993404662506").map(H_),Lb=rb(Yb),jb=new Array(3).concat("ffeda0feb24cf03b20","ffffb2fecc5cfd8d3ce31a1c","ffffb2fecc5cfd8d3cf03b20bd0026","ffffb2fed976feb24cfd8d3cf03b20bd0026","ffffb2fed976feb24cfd8d3cfc4e2ae31a1cb10026","ffffccffeda0fed976feb24cfd8d3cfc4e2ae31a1cb10026","ffffccffeda0fed976feb24cfd8d3cfc4e2ae31a1cbd0026800026").map(H_),Hb=rb(jb),Xb=new Array(3).concat("deebf79ecae13182bd","eff3ffbdd7e76baed62171b5","eff3ffbdd7e76baed63182bd08519c","eff3ffc6dbef9ecae16baed63182bd08519c","eff3ffc6dbef9ecae16baed64292c62171b5084594","f7fbffdeebf7c6dbef9ecae16baed64292c62171b5084594","f7fbffdeebf7c6dbef9ecae16baed64292c62171b508519c08306b").map(H_),Gb=rb(Xb),Vb=new Array(3).concat("e5f5e0a1d99b31a354","edf8e9bae4b374c476238b45","edf8e9bae4b374c47631a354006d2c","edf8e9c7e9c0a1d99b74c47631a354006d2c","edf8e9c7e9c0a1d99b74c47641ab5d238b45005a32","f7fcf5e5f5e0c7e9c0a1d99b74c47641ab5d238b45005a32","f7fcf5e5f5e0c7e9c0a1d99b74c47641ab5d238b45006d2c00441b").map(H_),Wb=rb(Vb),Zb=new Array(3).concat("f0f0f0bdbdbd636363","f7f7f7cccccc969696525252","f7f7f7cccccc969696636363252525","f7f7f7d9d9d9bdbdbd969696636363252525","f7f7f7d9d9d9bdbdbd969696737373525252252525","fffffff0f0f0d9d9d9bdbdbd969696737373525252252525","fffffff0f0f0d9d9d9bdbdbd969696737373525252252525000000").map(H_),Kb=rb(Zb),Qb=new Array(3).concat("efedf5bcbddc756bb1","f2f0f7cbc9e29e9ac86a51a3","f2f0f7cbc9e29e9ac8756bb154278f","f2f0f7dadaebbcbddc9e9ac8756bb154278f","f2f0f7dadaebbcbddc9e9ac8807dba6a51a34a1486","fcfbfdefedf5dadaebbcbddc9e9ac8807dba6a51a34a1486","fcfbfdefedf5dadaebbcbddc9e9ac8807dba6a51a354278f3f007d").map(H_),Jb=rb(Qb),tm=new Array(3).concat("fee0d2fc9272de2d26","fee5d9fcae91fb6a4acb181d","fee5d9fcae91fb6a4ade2d26a50f15","fee5d9fcbba1fc9272fb6a4ade2d26a50f15","fee5d9fcbba1fc9272fb6a4aef3b2ccb181d99000d","fff5f0fee0d2fcbba1fc9272fb6a4aef3b2ccb181d99000d","fff5f0fee0d2fcbba1fc9272fb6a4aef3b2ccb181da50f1567000d").map(H_),nm=rb(tm),em=new Array(3).concat("fee6cefdae6be6550d","feeddefdbe85fd8d3cd94701","feeddefdbe85fd8d3ce6550da63603","feeddefdd0a2fdae6bfd8d3ce6550da63603","feeddefdd0a2fdae6bfd8d3cf16913d948018c2d04","fff5ebfee6cefdd0a2fdae6bfd8d3cf16913d948018c2d04","fff5ebfee6cefdd0a2fdae6bfd8d3cf16913d94801a636037f2704").map(H_),rm=rb(em);var im=hi(Tr(300,.5,0),Tr(-240,.5,1)),om=hi(Tr(-100,.75,.35),Tr(80,1.5,.8)),am=hi(Tr(260,.75,.35),Tr(80,1.5,.8)),um=Tr();var cm=Fe(),fm=Math.PI/3,sm=2*Math.PI/3;function lm(t){var n=t.length;return function(e){return t[Math.max(0,Math.min(n-1,Math.floor(e*n)))]}}var hm=lm(H_("44015444025645045745055946075a46085c460a5d460b5e470d60470e6147106347116447136548146748166848176948186a481a6c481b6d481c6e481d6f481f70482071482173482374482475482576482677482878482979472a7a472c7a472d7b472e7c472f7d46307e46327e46337f463480453581453781453882443983443a83443b84433d84433e85423f854240864241864142874144874045884046883f47883f48893e49893e4a893e4c8a3d4d8a3d4e8a3c4f8a3c508b3b518b3b528b3a538b3a548c39558c39568c38588c38598c375a8c375b8d365c8d365d8d355e8d355f8d34608d34618d33628d33638d32648e32658e31668e31678e31688e30698e306a8e2f6b8e2f6c8e2e6d8e2e6e8e2e6f8e2d708e2d718e2c718e2c728e2c738e2b748e2b758e2a768e2a778e2a788e29798e297a8e297b8e287c8e287d8e277e8e277f8e27808e26818e26828e26828e25838e25848e25858e24868e24878e23888e23898e238a8d228b8d228c8d228d8d218e8d218f8d21908d21918c20928c20928c20938c1f948c1f958b1f968b1f978b1f988b1f998a1f9a8a1e9b8a1e9c891e9d891f9e891f9f881fa0881fa1881fa1871fa28720a38620a48621a58521a68522a78522a88423a98324aa8325ab8225ac8226ad8127ad8128ae8029af7f2ab07f2cb17e2db27d2eb37c2fb47c31b57b32b67a34b67935b77937b87838b9773aba763bbb753dbc743fbc7340bd7242be7144bf7046c06f48c16e4ac16d4cc26c4ec36b50c46a52c56954c56856c66758c7655ac8645cc8635ec96260ca6063cb5f65cb5e67cc5c69cd5b6ccd5a6ece5870cf5773d05675d05477d1537ad1517cd2507fd34e81d34d84d44b86d54989d5488bd6468ed64590d74393d74195d84098d83e9bd93c9dd93ba0da39a2da37a5db36a8db34aadc32addc30b0dd2fb2dd2db5de2bb8de29bade28bddf26c0df25c2df23c5e021c8e020cae11fcde11dd0e11cd2e21bd5e21ad8e219dae319dde318dfe318e2e418e5e419e7e419eae51aece51befe51cf1e51df4e61ef6e620f8e621fbe723fde725")),dm=lm(H_("00000401000501010601010802010902020b02020d03030f03031204041405041606051806051a07061c08071e0907200a08220b09240c09260d0a290e0b2b100b2d110c2f120d31130d34140e36150e38160f3b180f3d19103f1a10421c10441d11471e114920114b21114e22115024125325125527125829115a2a115c2c115f2d11612f116331116533106734106936106b38106c390f6e3b0f703d0f713f0f72400f74420f75440f764510774710784910784a10794c117a4e117b4f127b51127c52137c54137d56147d57157e59157e5a167e5c167f5d177f5f187f601880621980641a80651a80671b80681c816a1c816b1d816d1d816e1e81701f81721f817320817521817621817822817922827b23827c23827e24828025828125818326818426818627818827818928818b29818c29818e2a81902a81912b81932b80942c80962c80982d80992d809b2e7f9c2e7f9e2f7fa02f7fa1307ea3307ea5317ea6317da8327daa337dab337cad347cae347bb0357bb2357bb3367ab5367ab73779b83779ba3878bc3978bd3977bf3a77c03a76c23b75c43c75c53c74c73d73c83e73ca3e72cc3f71cd4071cf4070d0416fd2426fd3436ed5446dd6456cd8456cd9466bdb476adc4869de4968df4a68e04c67e24d66e34e65e44f64e55064e75263e85362e95462ea5661eb5760ec5860ed5a5fee5b5eef5d5ef05f5ef1605df2625df2645cf3655cf4675cf4695cf56b5cf66c5cf66e5cf7705cf7725cf8745cf8765cf9785df9795df97b5dfa7d5efa7f5efa815ffb835ffb8560fb8761fc8961fc8a62fc8c63fc8e64fc9065fd9266fd9467fd9668fd9869fd9a6afd9b6bfe9d6cfe9f6dfea16efea36ffea571fea772fea973feaa74feac76feae77feb078feb27afeb47bfeb67cfeb77efeb97ffebb81febd82febf84fec185fec287fec488fec68afec88cfeca8dfecc8ffecd90fecf92fed194fed395fed597fed799fed89afdda9cfddc9efddea0fde0a1fde2a3fde3a5fde5a7fde7a9fde9aafdebacfcecaefceeb0fcf0b2fcf2b4fcf4b6fcf6b8fcf7b9fcf9bbfcfbbdfcfdbf")),pm=lm(H_("00000401000501010601010802010a02020c02020e03021004031204031405041706041907051b08051d09061f0a07220b07240c08260d08290e092b10092d110a30120a32140b34150b37160b39180c3c190c3e1b0c411c0c431e0c451f0c48210c4a230c4c240c4f260c51280b53290b552b0b572d0b592f0a5b310a5c320a5e340a5f3609613809623909633b09643d09653e0966400a67420a68440a68450a69470b6a490b6a4a0c6b4c0c6b4d0d6c4f0d6c510e6c520e6d540f6d550f6d57106e59106e5a116e5c126e5d126e5f136e61136e62146e64156e65156e67166e69166e6a176e6c186e6d186e6f196e71196e721a6e741a6e751b6e771c6d781c6d7a1d6d7c1d6d7d1e6d7f1e6c801f6c82206c84206b85216b87216b88226a8a226a8c23698d23698f24699025689225689326679526679727669827669a28659b29649d29649f2a63a02a63a22b62a32c61a52c60a62d60a82e5fa92e5eab2f5ead305dae305cb0315bb1325ab3325ab43359b63458b73557b93556ba3655bc3754bd3853bf3952c03a51c13a50c33b4fc43c4ec63d4dc73e4cc83f4bca404acb4149cc4248ce4347cf4446d04545d24644d34743d44842d54a41d74b3fd84c3ed94d3dda4e3cdb503bdd513ade5238df5337e05536e15635e25734e35933e45a31e55c30e65d2fe75e2ee8602de9612bea632aeb6429eb6628ec6726ed6925ee6a24ef6c23ef6e21f06f20f1711ff1731df2741cf3761bf37819f47918f57b17f57d15f67e14f68013f78212f78410f8850ff8870ef8890cf98b0bf98c0af98e09fa9008fa9207fa9407fb9606fb9706fb9906fb9b06fb9d07fc9f07fca108fca309fca50afca60cfca80dfcaa0ffcac11fcae12fcb014fcb216fcb418fbb61afbb81dfbba1ffbbc21fbbe23fac026fac228fac42afac62df9c72ff9c932f9cb35f8cd37f8cf3af7d13df7d340f6d543f6d746f5d949f5db4cf4dd4ff4df53f4e156f3e35af3e55df2e661f2e865f2ea69f1ec6df1ed71f1ef75f1f179f2f27df2f482f3f586f3f68af4f88ef5f992f6fa96f8fb9af9fc9dfafda1fcffa4")),gm=lm(H_("0d088710078813078916078a19068c1b068d1d068e20068f2206902406912605912805922a05932c05942e05952f059631059733059735049837049938049a3a049a3c049b3e049c3f049c41049d43039e44039e46039f48039f4903a04b03a14c02a14e02a25002a25102a35302a35502a45601a45801a45901a55b01a55c01a65e01a66001a66100a76300a76400a76600a76700a86900a86a00a86c00a86e00a86f00a87100a87201a87401a87501a87701a87801a87a02a87b02a87d03a87e03a88004a88104a78305a78405a78606a68707a68808a68a09a58b0aa58d0ba58e0ca48f0da4910ea3920fa39410a29511a19613a19814a099159f9a169f9c179e9d189d9e199da01a9ca11b9ba21d9aa31e9aa51f99a62098a72197a82296aa2395ab2494ac2694ad2793ae2892b02991b12a90b22b8fb32c8eb42e8db52f8cb6308bb7318ab83289ba3388bb3488bc3587bd3786be3885bf3984c03a83c13b82c23c81c33d80c43e7fc5407ec6417dc7427cc8437bc9447aca457acb4679cc4778cc4977cd4a76ce4b75cf4c74d04d73d14e72d24f71d35171d45270d5536fd5546ed6556dd7566cd8576bd9586ada5a6ada5b69db5c68dc5d67dd5e66de5f65de6164df6263e06363e16462e26561e26660e3685fe4695ee56a5de56b5de66c5ce76e5be76f5ae87059e97158e97257ea7457eb7556eb7655ec7754ed7953ed7a52ee7b51ef7c51ef7e50f07f4ff0804ef1814df1834cf2844bf3854bf3874af48849f48948f58b47f58c46f68d45f68f44f79044f79143f79342f89441f89540f9973ff9983ef99a3efa9b3dfa9c3cfa9e3bfb9f3afba139fba238fca338fca537fca636fca835fca934fdab33fdac33fdae32fdaf31fdb130fdb22ffdb42ffdb52efeb72dfeb82cfeba2cfebb2bfebd2afebe2afec029fdc229fdc328fdc527fdc627fdc827fdca26fdcb26fccd25fcce25fcd025fcd225fbd324fbd524fbd724fad824fada24f9dc24f9dd25f8df25f8e125f7e225f7e425f6e626f6e826f5e926f5eb27f4ed27f3ee27f3f027f2f227f1f426f1f525f0f724f0f921"));function ym(t){return function(){return t}}const vm=Math.abs,_m=Math.atan2,bm=Math.cos,mm=Math.max,xm=Math.min,wm=Math.sin,Mm=Math.sqrt,Tm=1e-12,Am=Math.PI,Sm=Am/2,Em=2*Am;function Nm(t){return t>=1?Sm:t<=-1?-Sm:Math.asin(t)}function km(t){let n=3;return t.digits=function(e){if(!arguments.length)return n;if(null==e)n=null;else{const t=Math.floor(e);if(!(t>=0))throw new RangeError(`invalid digits: ${e}`);n=t}return t},()=>new Ua(n)}function Cm(t){return t.innerRadius}function Pm(t){return t.outerRadius}function zm(t){return t.startAngle}function $m(t){return t.endAngle}function Dm(t){return t&&t.padAngle}function Rm(t,n,e,r,i,o,a){var u=t-e,c=n-r,f=(a?o:-o)/Mm(u*u+c*c),s=f*c,l=-f*u,h=t+s,d=n+l,p=e+s,g=r+l,y=(h+p)/2,v=(d+g)/2,_=p-h,b=g-d,m=_*_+b*b,x=i-o,w=h*g-p*d,M=(b<0?-1:1)*Mm(mm(0,x*x*m-w*w)),T=(w*b-_*M)/m,A=(-w*_-b*M)/m,S=(w*b+_*M)/m,E=(-w*_+b*M)/m,N=T-y,k=A-v,C=S-y,P=E-v;return N*N+k*k>C*C+P*P&&(T=S,A=E),{cx:T,cy:A,x01:-s,y01:-l,x11:T*(i/x-1),y11:A*(i/x-1)}}var Fm=Array.prototype.slice;function qm(t){return"object"==typeof t&&"length"in t?t:Array.from(t)}function Um(t){this._context=t}function Im(t){return new Um(t)}function Om(t){return t[0]}function Bm(t){return t[1]}function Ym(t,n){var e=ym(!0),r=null,i=Im,o=null,a=km(u);function u(u){var c,f,s,l=(u=qm(u)).length,h=!1;for(null==r&&(o=i(s=a())),c=0;c<=l;++c)!(c=l;--h)u.point(v[h],_[h]);u.lineEnd(),u.areaEnd()}y&&(v[s]=+t(d,s,f),_[s]=+n(d,s,f),u.point(r?+r(d,s,f):v[s],e?+e(d,s,f):_[s]))}if(p)return u=null,p+""||null}function s(){return Ym().defined(i).curve(a).context(o)}return t="function"==typeof t?t:void 0===t?Om:ym(+t),n="function"==typeof n?n:ym(void 0===n?0:+n),e="function"==typeof e?e:void 0===e?Bm:ym(+e),f.x=function(n){return arguments.length?(t="function"==typeof n?n:ym(+n),r=null,f):t},f.x0=function(n){return arguments.length?(t="function"==typeof n?n:ym(+n),f):t},f.x1=function(t){return arguments.length?(r=null==t?null:"function"==typeof t?t:ym(+t),f):r},f.y=function(t){return arguments.length?(n="function"==typeof t?t:ym(+t),e=null,f):n},f.y0=function(t){return arguments.length?(n="function"==typeof t?t:ym(+t),f):n},f.y1=function(t){return arguments.length?(e=null==t?null:"function"==typeof t?t:ym(+t),f):e},f.lineX0=f.lineY0=function(){return s().x(t).y(n)},f.lineY1=function(){return s().x(t).y(e)},f.lineX1=function(){return s().x(r).y(n)},f.defined=function(t){return arguments.length?(i="function"==typeof t?t:ym(!!t),f):i},f.curve=function(t){return arguments.length?(a=t,null!=o&&(u=a(o)),f):a},f.context=function(t){return arguments.length?(null==t?o=u=null:u=a(o=t),f):o},f}function jm(t,n){return nt?1:n>=t?0:NaN}function Hm(t){return t}Um.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._point=0},lineEnd:function(){(this._line||0!==this._line&&1===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2;default:this._context.lineTo(t,n)}}};var Xm=Vm(Im);function Gm(t){this._curve=t}function Vm(t){function n(n){return new Gm(t(n))}return n._curve=t,n}function Wm(t){var n=t.curve;return t.angle=t.x,delete t.x,t.radius=t.y,delete t.y,t.curve=function(t){return arguments.length?n(Vm(t)):n()._curve},t}function Zm(){return Wm(Ym().curve(Xm))}function Km(){var t=Lm().curve(Xm),n=t.curve,e=t.lineX0,r=t.lineX1,i=t.lineY0,o=t.lineY1;return t.angle=t.x,delete t.x,t.startAngle=t.x0,delete t.x0,t.endAngle=t.x1,delete t.x1,t.radius=t.y,delete t.y,t.innerRadius=t.y0,delete t.y0,t.outerRadius=t.y1,delete t.y1,t.lineStartAngle=function(){return Wm(e())},delete t.lineX0,t.lineEndAngle=function(){return Wm(r())},delete t.lineX1,t.lineInnerRadius=function(){return Wm(i())},delete t.lineY0,t.lineOuterRadius=function(){return Wm(o())},delete t.lineY1,t.curve=function(t){return arguments.length?n(Vm(t)):n()._curve},t}function Qm(t,n){return[(n=+n)*Math.cos(t-=Math.PI/2),n*Math.sin(t)]}Gm.prototype={areaStart:function(){this._curve.areaStart()},areaEnd:function(){this._curve.areaEnd()},lineStart:function(){this._curve.lineStart()},lineEnd:function(){this._curve.lineEnd()},point:function(t,n){this._curve.point(n*Math.sin(t),n*-Math.cos(t))}};class Jm{constructor(t,n){this._context=t,this._x=n}areaStart(){this._line=0}areaEnd(){this._line=NaN}lineStart(){this._point=0}lineEnd(){(this._line||0!==this._line&&1===this._point)&&this._context.closePath(),this._line=1-this._line}point(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2;default:this._x?this._context.bezierCurveTo(this._x0=(this._x0+t)/2,this._y0,this._x0,n,t,n):this._context.bezierCurveTo(this._x0,this._y0=(this._y0+n)/2,t,this._y0,t,n)}this._x0=t,this._y0=n}}class tx{constructor(t){this._context=t}lineStart(){this._point=0}lineEnd(){}point(t,n){if(t=+t,n=+n,0===this._point)this._point=1;else{const e=Qm(this._x0,this._y0),r=Qm(this._x0,this._y0=(this._y0+n)/2),i=Qm(t,this._y0),o=Qm(t,n);this._context.moveTo(...e),this._context.bezierCurveTo(...r,...i,...o)}this._x0=t,this._y0=n}}function nx(t){return new Jm(t,!0)}function ex(t){return new Jm(t,!1)}function rx(t){return new tx(t)}function ix(t){return t.source}function ox(t){return t.target}function ax(t){let n=ix,e=ox,r=Om,i=Bm,o=null,a=null,u=km(c);function c(){let c;const f=Fm.call(arguments),s=n.apply(this,f),l=e.apply(this,f);if(null==o&&(a=t(c=u())),a.lineStart(),f[0]=s,a.point(+r.apply(this,f),+i.apply(this,f)),f[0]=l,a.point(+r.apply(this,f),+i.apply(this,f)),a.lineEnd(),c)return a=null,c+""||null}return c.source=function(t){return arguments.length?(n=t,c):n},c.target=function(t){return arguments.length?(e=t,c):e},c.x=function(t){return arguments.length?(r="function"==typeof t?t:ym(+t),c):r},c.y=function(t){return arguments.length?(i="function"==typeof t?t:ym(+t),c):i},c.context=function(n){return arguments.length?(null==n?o=a=null:a=t(o=n),c):o},c}const ux=Mm(3);var cx={draw(t,n){const e=.59436*Mm(n+xm(n/28,.75)),r=e/2,i=r*ux;t.moveTo(0,e),t.lineTo(0,-e),t.moveTo(-i,-r),t.lineTo(i,r),t.moveTo(-i,r),t.lineTo(i,-r)}},fx={draw(t,n){const e=Mm(n/Am);t.moveTo(e,0),t.arc(0,0,e,0,Em)}},sx={draw(t,n){const e=Mm(n/5)/2;t.moveTo(-3*e,-e),t.lineTo(-e,-e),t.lineTo(-e,-3*e),t.lineTo(e,-3*e),t.lineTo(e,-e),t.lineTo(3*e,-e),t.lineTo(3*e,e),t.lineTo(e,e),t.lineTo(e,3*e),t.lineTo(-e,3*e),t.lineTo(-e,e),t.lineTo(-3*e,e),t.closePath()}};const lx=Mm(1/3),hx=2*lx;var dx={draw(t,n){const e=Mm(n/hx),r=e*lx;t.moveTo(0,-e),t.lineTo(r,0),t.lineTo(0,e),t.lineTo(-r,0),t.closePath()}},px={draw(t,n){const e=.62625*Mm(n);t.moveTo(0,-e),t.lineTo(e,0),t.lineTo(0,e),t.lineTo(-e,0),t.closePath()}},gx={draw(t,n){const e=.87559*Mm(n-xm(n/7,2));t.moveTo(-e,0),t.lineTo(e,0),t.moveTo(0,e),t.lineTo(0,-e)}},yx={draw(t,n){const e=Mm(n),r=-e/2;t.rect(r,r,e,e)}},vx={draw(t,n){const e=.4431*Mm(n);t.moveTo(e,e),t.lineTo(e,-e),t.lineTo(-e,-e),t.lineTo(-e,e),t.closePath()}};const _x=wm(Am/10)/wm(7*Am/10),bx=wm(Em/10)*_x,mx=-bm(Em/10)*_x;var xx={draw(t,n){const e=Mm(.8908130915292852*n),r=bx*e,i=mx*e;t.moveTo(0,-e),t.lineTo(r,i);for(let n=1;n<5;++n){const o=Em*n/5,a=bm(o),u=wm(o);t.lineTo(u*e,-a*e),t.lineTo(a*r-u*i,u*r+a*i)}t.closePath()}};const wx=Mm(3);var Mx={draw(t,n){const e=-Mm(n/(3*wx));t.moveTo(0,2*e),t.lineTo(-wx*e,-e),t.lineTo(wx*e,-e),t.closePath()}};const Tx=Mm(3);var Ax={draw(t,n){const e=.6824*Mm(n),r=e/2,i=e*Tx/2;t.moveTo(0,-e),t.lineTo(i,r),t.lineTo(-i,r),t.closePath()}};const Sx=-.5,Ex=Mm(3)/2,Nx=1/Mm(12),kx=3*(Nx/2+1);var Cx={draw(t,n){const e=Mm(n/kx),r=e/2,i=e*Nx,o=r,a=e*Nx+e,u=-o,c=a;t.moveTo(r,i),t.lineTo(o,a),t.lineTo(u,c),t.lineTo(Sx*r-Ex*i,Ex*r+Sx*i),t.lineTo(Sx*o-Ex*a,Ex*o+Sx*a),t.lineTo(Sx*u-Ex*c,Ex*u+Sx*c),t.lineTo(Sx*r+Ex*i,Sx*i-Ex*r),t.lineTo(Sx*o+Ex*a,Sx*a-Ex*o),t.lineTo(Sx*u+Ex*c,Sx*c-Ex*u),t.closePath()}},Px={draw(t,n){const e=.6189*Mm(n-xm(n/6,1.7));t.moveTo(-e,-e),t.lineTo(e,e),t.moveTo(-e,e),t.lineTo(e,-e)}};const zx=[fx,sx,dx,yx,xx,Mx,Cx],$x=[fx,gx,Px,Ax,cx,vx,px];function Dx(){}function Rx(t,n,e){t._context.bezierCurveTo((2*t._x0+t._x1)/3,(2*t._y0+t._y1)/3,(t._x0+2*t._x1)/3,(t._y0+2*t._y1)/3,(t._x0+4*t._x1+n)/6,(t._y0+4*t._y1+e)/6)}function Fx(t){this._context=t}function qx(t){this._context=t}function Ux(t){this._context=t}function Ix(t,n){this._basis=new Fx(t),this._beta=n}Fx.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._y0=this._y1=NaN,this._point=0},lineEnd:function(){switch(this._point){case 3:Rx(this,this._x1,this._y1);case 2:this._context.lineTo(this._x1,this._y1)}(this._line||0!==this._line&&1===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2;break;case 2:this._point=3,this._context.lineTo((5*this._x0+this._x1)/6,(5*this._y0+this._y1)/6);default:Rx(this,t,n)}this._x0=this._x1,this._x1=t,this._y0=this._y1,this._y1=n}},qx.prototype={areaStart:Dx,areaEnd:Dx,lineStart:function(){this._x0=this._x1=this._x2=this._x3=this._x4=this._y0=this._y1=this._y2=this._y3=this._y4=NaN,this._point=0},lineEnd:function(){switch(this._point){case 1:this._context.moveTo(this._x2,this._y2),this._context.closePath();break;case 2:this._context.moveTo((this._x2+2*this._x3)/3,(this._y2+2*this._y3)/3),this._context.lineTo((this._x3+2*this._x2)/3,(this._y3+2*this._y2)/3),this._context.closePath();break;case 3:this.point(this._x2,this._y2),this.point(this._x3,this._y3),this.point(this._x4,this._y4)}},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._x2=t,this._y2=n;break;case 1:this._point=2,this._x3=t,this._y3=n;break;case 2:this._point=3,this._x4=t,this._y4=n,this._context.moveTo((this._x0+4*this._x1+t)/6,(this._y0+4*this._y1+n)/6);break;default:Rx(this,t,n)}this._x0=this._x1,this._x1=t,this._y0=this._y1,this._y1=n}},Ux.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._y0=this._y1=NaN,this._point=0},lineEnd:function(){(this._line||0!==this._line&&3===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1;break;case 1:this._point=2;break;case 2:this._point=3;var e=(this._x0+4*this._x1+t)/6,r=(this._y0+4*this._y1+n)/6;this._line?this._context.lineTo(e,r):this._context.moveTo(e,r);break;case 3:this._point=4;default:Rx(this,t,n)}this._x0=this._x1,this._x1=t,this._y0=this._y1,this._y1=n}},Ix.prototype={lineStart:function(){this._x=[],this._y=[],this._basis.lineStart()},lineEnd:function(){var t=this._x,n=this._y,e=t.length-1;if(e>0)for(var r,i=t[0],o=n[0],a=t[e]-i,u=n[e]-o,c=-1;++c<=e;)r=c/e,this._basis.point(this._beta*t[c]+(1-this._beta)*(i+r*a),this._beta*n[c]+(1-this._beta)*(o+r*u));this._x=this._y=null,this._basis.lineEnd()},point:function(t,n){this._x.push(+t),this._y.push(+n)}};var Ox=function t(n){function e(t){return 1===n?new Fx(t):new Ix(t,n)}return e.beta=function(n){return t(+n)},e}(.85);function Bx(t,n,e){t._context.bezierCurveTo(t._x1+t._k*(t._x2-t._x0),t._y1+t._k*(t._y2-t._y0),t._x2+t._k*(t._x1-n),t._y2+t._k*(t._y1-e),t._x2,t._y2)}function Yx(t,n){this._context=t,this._k=(1-n)/6}Yx.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._x2=this._y0=this._y1=this._y2=NaN,this._point=0},lineEnd:function(){switch(this._point){case 2:this._context.lineTo(this._x2,this._y2);break;case 3:Bx(this,this._x1,this._y1)}(this._line||0!==this._line&&1===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2,this._x1=t,this._y1=n;break;case 2:this._point=3;default:Bx(this,t,n)}this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var Lx=function t(n){function e(t){return new Yx(t,n)}return e.tension=function(n){return t(+n)},e}(0);function jx(t,n){this._context=t,this._k=(1-n)/6}jx.prototype={areaStart:Dx,areaEnd:Dx,lineStart:function(){this._x0=this._x1=this._x2=this._x3=this._x4=this._x5=this._y0=this._y1=this._y2=this._y3=this._y4=this._y5=NaN,this._point=0},lineEnd:function(){switch(this._point){case 1:this._context.moveTo(this._x3,this._y3),this._context.closePath();break;case 2:this._context.lineTo(this._x3,this._y3),this._context.closePath();break;case 3:this.point(this._x3,this._y3),this.point(this._x4,this._y4),this.point(this._x5,this._y5)}},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._x3=t,this._y3=n;break;case 1:this._point=2,this._context.moveTo(this._x4=t,this._y4=n);break;case 2:this._point=3,this._x5=t,this._y5=n;break;default:Bx(this,t,n)}this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var Hx=function t(n){function e(t){return new jx(t,n)}return e.tension=function(n){return t(+n)},e}(0);function Xx(t,n){this._context=t,this._k=(1-n)/6}Xx.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._x2=this._y0=this._y1=this._y2=NaN,this._point=0},lineEnd:function(){(this._line||0!==this._line&&3===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1;break;case 1:this._point=2;break;case 2:this._point=3,this._line?this._context.lineTo(this._x2,this._y2):this._context.moveTo(this._x2,this._y2);break;case 3:this._point=4;default:Bx(this,t,n)}this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var Gx=function t(n){function e(t){return new Xx(t,n)}return e.tension=function(n){return t(+n)},e}(0);function Vx(t,n,e){var r=t._x1,i=t._y1,o=t._x2,a=t._y2;if(t._l01_a>Tm){var u=2*t._l01_2a+3*t._l01_a*t._l12_a+t._l12_2a,c=3*t._l01_a*(t._l01_a+t._l12_a);r=(r*u-t._x0*t._l12_2a+t._x2*t._l01_2a)/c,i=(i*u-t._y0*t._l12_2a+t._y2*t._l01_2a)/c}if(t._l23_a>Tm){var f=2*t._l23_2a+3*t._l23_a*t._l12_a+t._l12_2a,s=3*t._l23_a*(t._l23_a+t._l12_a);o=(o*f+t._x1*t._l23_2a-n*t._l12_2a)/s,a=(a*f+t._y1*t._l23_2a-e*t._l12_2a)/s}t._context.bezierCurveTo(r,i,o,a,t._x2,t._y2)}function Wx(t,n){this._context=t,this._alpha=n}Wx.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._x2=this._y0=this._y1=this._y2=NaN,this._l01_a=this._l12_a=this._l23_a=this._l01_2a=this._l12_2a=this._l23_2a=this._point=0},lineEnd:function(){switch(this._point){case 2:this._context.lineTo(this._x2,this._y2);break;case 3:this.point(this._x2,this._y2)}(this._line||0!==this._line&&1===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){if(t=+t,n=+n,this._point){var e=this._x2-t,r=this._y2-n;this._l23_a=Math.sqrt(this._l23_2a=Math.pow(e*e+r*r,this._alpha))}switch(this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2;break;case 2:this._point=3;default:Vx(this,t,n)}this._l01_a=this._l12_a,this._l12_a=this._l23_a,this._l01_2a=this._l12_2a,this._l12_2a=this._l23_2a,this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var Zx=function t(n){function e(t){return n?new Wx(t,n):new Yx(t,0)}return e.alpha=function(n){return t(+n)},e}(.5);function Kx(t,n){this._context=t,this._alpha=n}Kx.prototype={areaStart:Dx,areaEnd:Dx,lineStart:function(){this._x0=this._x1=this._x2=this._x3=this._x4=this._x5=this._y0=this._y1=this._y2=this._y3=this._y4=this._y5=NaN,this._l01_a=this._l12_a=this._l23_a=this._l01_2a=this._l12_2a=this._l23_2a=this._point=0},lineEnd:function(){switch(this._point){case 1:this._context.moveTo(this._x3,this._y3),this._context.closePath();break;case 2:this._context.lineTo(this._x3,this._y3),this._context.closePath();break;case 3:this.point(this._x3,this._y3),this.point(this._x4,this._y4),this.point(this._x5,this._y5)}},point:function(t,n){if(t=+t,n=+n,this._point){var e=this._x2-t,r=this._y2-n;this._l23_a=Math.sqrt(this._l23_2a=Math.pow(e*e+r*r,this._alpha))}switch(this._point){case 0:this._point=1,this._x3=t,this._y3=n;break;case 1:this._point=2,this._context.moveTo(this._x4=t,this._y4=n);break;case 2:this._point=3,this._x5=t,this._y5=n;break;default:Vx(this,t,n)}this._l01_a=this._l12_a,this._l12_a=this._l23_a,this._l01_2a=this._l12_2a,this._l12_2a=this._l23_2a,this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var Qx=function t(n){function e(t){return n?new Kx(t,n):new jx(t,0)}return e.alpha=function(n){return t(+n)},e}(.5);function Jx(t,n){this._context=t,this._alpha=n}Jx.prototype={areaStart:function(){this._line=0},areaEnd:function(){this._line=NaN},lineStart:function(){this._x0=this._x1=this._x2=this._y0=this._y1=this._y2=NaN,this._l01_a=this._l12_a=this._l23_a=this._l01_2a=this._l12_2a=this._l23_2a=this._point=0},lineEnd:function(){(this._line||0!==this._line&&3===this._point)&&this._context.closePath(),this._line=1-this._line},point:function(t,n){if(t=+t,n=+n,this._point){var e=this._x2-t,r=this._y2-n;this._l23_a=Math.sqrt(this._l23_2a=Math.pow(e*e+r*r,this._alpha))}switch(this._point){case 0:this._point=1;break;case 1:this._point=2;break;case 2:this._point=3,this._line?this._context.lineTo(this._x2,this._y2):this._context.moveTo(this._x2,this._y2);break;case 3:this._point=4;default:Vx(this,t,n)}this._l01_a=this._l12_a,this._l12_a=this._l23_a,this._l01_2a=this._l12_2a,this._l12_2a=this._l23_2a,this._x0=this._x1,this._x1=this._x2,this._x2=t,this._y0=this._y1,this._y1=this._y2,this._y2=n}};var tw=function t(n){function e(t){return n?new Jx(t,n):new Xx(t,0)}return e.alpha=function(n){return t(+n)},e}(.5);function nw(t){this._context=t}function ew(t){return t<0?-1:1}function rw(t,n,e){var r=t._x1-t._x0,i=n-t._x1,o=(t._y1-t._y0)/(r||i<0&&-0),a=(e-t._y1)/(i||r<0&&-0),u=(o*i+a*r)/(r+i);return(ew(o)+ew(a))*Math.min(Math.abs(o),Math.abs(a),.5*Math.abs(u))||0}function iw(t,n){var e=t._x1-t._x0;return e?(3*(t._y1-t._y0)/e-n)/2:n}function ow(t,n,e){var r=t._x0,i=t._y0,o=t._x1,a=t._y1,u=(o-r)/3;t._context.bezierCurveTo(r+u,i+u*n,o-u,a-u*e,o,a)}function aw(t){this._context=t}function uw(t){this._context=new cw(t)}function cw(t){this._context=t}function fw(t){this._context=t}function sw(t){var n,e,r=t.length-1,i=new Array(r),o=new Array(r),a=new Array(r);for(i[0]=0,o[0]=2,a[0]=t[0]+2*t[1],n=1;n=0;--n)i[n]=(a[n]-i[n+1])/o[n];for(o[r-1]=(t[r]+i[r-1])/2,n=0;n1)for(var e,r,i,o=1,a=t[n[0]],u=a.length;o=0;)e[n]=n;return e}function pw(t,n){return t[n]}function gw(t){const n=[];return n.key=t,n}function yw(t){var n=t.map(vw);return dw(t).sort((function(t,e){return n[t]-n[e]}))}function vw(t){for(var n,e=-1,r=0,i=t.length,o=-1/0;++eo&&(o=n,r=e);return r}function _w(t){var n=t.map(bw);return dw(t).sort((function(t,e){return n[t]-n[e]}))}function bw(t){for(var n,e=0,r=-1,i=t.length;++r=0&&(this._t=1-this._t,this._line=1-this._line)},point:function(t,n){switch(t=+t,n=+n,this._point){case 0:this._point=1,this._line?this._context.lineTo(t,n):this._context.moveTo(t,n);break;case 1:this._point=2;default:if(this._t<=0)this._context.lineTo(this._x,n),this._context.lineTo(t,n);else{var e=this._x*(1-this._t)+t*this._t;this._context.lineTo(e,this._y),this._context.lineTo(e,n)}}this._x=t,this._y=n}};var mw=t=>()=>t;function xw(t,{sourceEvent:n,target:e,transform:r,dispatch:i}){Object.defineProperties(this,{type:{value:t,enumerable:!0,configurable:!0},sourceEvent:{value:n,enumerable:!0,configurable:!0},target:{value:e,enumerable:!0,configurable:!0},transform:{value:r,enumerable:!0,configurable:!0},_:{value:i}})}function ww(t,n,e){this.k=t,this.x=n,this.y=e}ww.prototype={constructor:ww,scale:function(t){return 1===t?this:new ww(this.k*t,this.x,this.y)},translate:function(t,n){return 0===t&0===n?this:new ww(this.k,this.x+this.k*t,this.y+this.k*n)},apply:function(t){return[t[0]*this.k+this.x,t[1]*this.k+this.y]},applyX:function(t){return t*this.k+this.x},applyY:function(t){return t*this.k+this.y},invert:function(t){return[(t[0]-this.x)/this.k,(t[1]-this.y)/this.k]},invertX:function(t){return(t-this.x)/this.k},invertY:function(t){return(t-this.y)/this.k},rescaleX:function(t){return t.copy().domain(t.range().map(this.invertX,this).map(t.invert,t))},rescaleY:function(t){return t.copy().domain(t.range().map(this.invertY,this).map(t.invert,t))},toString:function(){return"translate("+this.x+","+this.y+") scale("+this.k+")"}};var Mw=new ww(1,0,0);function Tw(t){for(;!t.__zoom;)if(!(t=t.parentNode))return Mw;return t.__zoom}function Aw(t){t.stopImmediatePropagation()}function Sw(t){t.preventDefault(),t.stopImmediatePropagation()}function Ew(t){return!(t.ctrlKey&&"wheel"!==t.type||t.button)}function Nw(){var t=this;return t instanceof SVGElement?(t=t.ownerSVGElement||t).hasAttribute("viewBox")?[[(t=t.viewBox.baseVal).x,t.y],[t.x+t.width,t.y+t.height]]:[[0,0],[t.width.baseVal.value,t.height.baseVal.value]]:[[0,0],[t.clientWidth,t.clientHeight]]}function kw(){return this.__zoom||Mw}function Cw(t){return-t.deltaY*(1===t.deltaMode?.05:t.deltaMode?1:.002)*(t.ctrlKey?10:1)}function Pw(){return navigator.maxTouchPoints||"ontouchstart"in this}function zw(t,n,e){var r=t.invertX(n[0][0])-e[0][0],i=t.invertX(n[1][0])-e[1][0],o=t.invertY(n[0][1])-e[0][1],a=t.invertY(n[1][1])-e[1][1];return t.translate(i>r?(r+i)/2:Math.min(0,r)||Math.max(0,i),a>o?(o+a)/2:Math.min(0,o)||Math.max(0,a))}Tw.prototype=ww.prototype,t.Adder=T,t.Delaunay=Lu,t.FormatSpecifier=tf,t.InternMap=InternMap,t.InternSet=InternSet,t.Node=Qd,t.Path=Ua,t.Voronoi=qu,t.ZoomTransform=ww,t.active=function(t,n){var e,r,i=t.__transition;if(i)for(r in n=null==n?null:n+"",i)if((e=i[r]).state>qi&&e.name===n)return new po([[t]],Zo,n,+r);return null},t.arc=function(){var t=Cm,n=Pm,e=ym(0),r=null,i=zm,o=$m,a=Dm,u=null,c=km(f);function f(){var f,s,l=+t.apply(this,arguments),h=+n.apply(this,arguments),d=i.apply(this,arguments)-Sm,p=o.apply(this,arguments)-Sm,g=vm(p-d),y=p>d;if(u||(u=f=c()),hTm)if(g>Em-Tm)u.moveTo(h*bm(d),h*wm(d)),u.arc(0,0,h,d,p,!y),l>Tm&&(u.moveTo(l*bm(p),l*wm(p)),u.arc(0,0,l,p,d,y));else{var v,_,b=d,m=p,x=d,w=p,M=g,T=g,A=a.apply(this,arguments)/2,S=A>Tm&&(r?+r.apply(this,arguments):Mm(l*l+h*h)),E=xm(vm(h-l)/2,+e.apply(this,arguments)),N=E,k=E;if(S>Tm){var C=Nm(S/l*wm(A)),P=Nm(S/h*wm(A));(M-=2*C)>Tm?(x+=C*=y?1:-1,w-=C):(M=0,x=w=(d+p)/2),(T-=2*P)>Tm?(b+=P*=y?1:-1,m-=P):(T=0,b=m=(d+p)/2)}var z=h*bm(b),$=h*wm(b),D=l*bm(w),R=l*wm(w);if(E>Tm){var F,q=h*bm(m),U=h*wm(m),I=l*bm(x),O=l*wm(x);if(g1?0:t<-1?Am:Math.acos(t)}((B*L+Y*j)/(Mm(B*B+Y*Y)*Mm(L*L+j*j)))/2),X=Mm(F[0]*F[0]+F[1]*F[1]);N=xm(E,(l-X)/(H-1)),k=xm(E,(h-X)/(H+1))}else N=k=0}T>Tm?k>Tm?(v=Rm(I,O,z,$,h,k,y),_=Rm(q,U,D,R,h,k,y),u.moveTo(v.cx+v.x01,v.cy+v.y01),kTm&&M>Tm?N>Tm?(v=Rm(D,R,q,U,l,-N,y),_=Rm(z,$,I,O,l,-N,y),u.lineTo(v.cx+v.x01,v.cy+v.y01),N=0))throw new RangeError("invalid r");let e=t.length;if(!((e=Math.floor(e))>=0))throw new RangeError("invalid length");if(!e||!n)return t;const r=y(n),i=t.slice();return r(t,i,0,e,1),r(i,t,0,e,1),r(t,i,0,e,1),t},t.blur2=l,t.blurImage=h,t.brush=function(){return wa(la)},t.brushSelection=function(t){var n=t.__brush;return n?n.dim.output(n.selection):null},t.brushX=function(){return wa(fa)},t.brushY=function(){return wa(sa)},t.buffer=function(t,n){return fetch(t,n).then(_c)},t.chord=function(){return za(!1,!1)},t.chordDirected=function(){return za(!0,!1)},t.chordTranspose=function(){return za(!1,!0)},t.cluster=function(){var t=Ld,n=1,e=1,r=!1;function i(i){var o,a=0;i.eachAfter((function(n){var e=n.children;e?(n.x=function(t){return t.reduce(jd,0)/t.length}(e),n.y=function(t){return 1+t.reduce(Hd,0)}(e)):(n.x=o?a+=t(n,o):0,n.y=0,o=n)}));var u=function(t){for(var n;n=t.children;)t=n[0];return t}(i),c=function(t){for(var n;n=t.children;)t=n[n.length-1];return t}(i),f=u.x-t(u,c)/2,s=c.x+t(c,u)/2;return i.eachAfter(r?function(t){t.x=(t.x-i.x)*n,t.y=(i.y-t.y)*e}:function(t){t.x=(t.x-f)/(s-f)*n,t.y=(1-(i.y?t.y/i.y:1))*e})}return i.separation=function(n){return arguments.length?(t=n,i):t},i.size=function(t){return arguments.length?(r=!1,n=+t[0],e=+t[1],i):r?null:[n,e]},i.nodeSize=function(t){return arguments.length?(r=!0,n=+t[0],e=+t[1],i):r?[n,e]:null},i},t.color=ze,t.contourDensity=function(){var t=fu,n=su,e=lu,r=960,i=500,o=20,a=2,u=3*o,c=r+2*u>>a,f=i+2*u>>a,s=Qa(20);function h(r){var i=new Float32Array(c*f),s=Math.pow(2,-a),h=-1;for(const o of r){var d=(t(o,++h,r)+u)*s,p=(n(o,h,r)+u)*s,g=+e(o,h,r);if(g&&d>=0&&d=0&&pt*r)))(n).map(((t,n)=>(t.value=+e[n],p(t))))}function p(t){return t.coordinates.forEach(g),t}function g(t){t.forEach(y)}function y(t){t.forEach(v)}function v(t){t[0]=t[0]*Math.pow(2,a)-u,t[1]=t[1]*Math.pow(2,a)-u}function _(){return c=r+2*(u=3*o)>>a,f=i+2*u>>a,d}return d.contours=function(t){var n=h(t),e=iu().size([c,f]),r=Math.pow(2,2*a),i=t=>{t=+t;var i=p(e.contour(n,t*r));return i.value=t,i};return Object.defineProperty(i,"max",{get:()=>J(n)/r}),i},d.x=function(n){return arguments.length?(t="function"==typeof n?n:Qa(+n),d):t},d.y=function(t){return arguments.length?(n="function"==typeof t?t:Qa(+t),d):n},d.weight=function(t){return arguments.length?(e="function"==typeof t?t:Qa(+t),d):e},d.size=function(t){if(!arguments.length)return[r,i];var n=+t[0],e=+t[1];if(!(n>=0&&e>=0))throw new Error("invalid size");return r=n,i=e,_()},d.cellSize=function(t){if(!arguments.length)return 1<=1))throw new Error("invalid cell size");return a=Math.floor(Math.log(t)/Math.LN2),_()},d.thresholds=function(t){return arguments.length?(s="function"==typeof t?t:Array.isArray(t)?Qa(Za.call(t)):Qa(t),d):s},d.bandwidth=function(t){if(!arguments.length)return Math.sqrt(o*(o+1));if(!((t=+t)>=0))throw new Error("invalid bandwidth");return o=(Math.sqrt(4*t*t+1)-1)/2,_()},d},t.contours=iu,t.count=v,t.create=function(t){return Zn(Yt(t).call(document.documentElement))},t.creator=Yt,t.cross=function(...t){const n="function"==typeof t[t.length-1]&&function(t){return n=>t(...n)}(t.pop()),e=(t=t.map(m)).map(_),r=t.length-1,i=new Array(r+1).fill(0),o=[];if(r<0||e.some(b))return o;for(;;){o.push(i.map(((n,e)=>t[e][n])));let a=r;for(;++i[a]===e[a];){if(0===a)return n?o.map(n):o;i[a--]=0}}},t.csv=wc,t.csvFormat=rc,t.csvFormatBody=ic,t.csvFormatRow=ac,t.csvFormatRows=oc,t.csvFormatValue=uc,t.csvParse=nc,t.csvParseRows=ec,t.cubehelix=Tr,t.cumsum=function(t,n){var e=0,r=0;return Float64Array.from(t,void 0===n?t=>e+=+t||0:i=>e+=+n(i,r++,t)||0)},t.curveBasis=function(t){return new Fx(t)},t.curveBasisClosed=function(t){return new qx(t)},t.curveBasisOpen=function(t){return new Ux(t)},t.curveBumpX=nx,t.curveBumpY=ex,t.curveBundle=Ox,t.curveCardinal=Lx,t.curveCardinalClosed=Hx,t.curveCardinalOpen=Gx,t.curveCatmullRom=Zx,t.curveCatmullRomClosed=Qx,t.curveCatmullRomOpen=tw,t.curveLinear=Im,t.curveLinearClosed=function(t){return new nw(t)},t.curveMonotoneX=function(t){return new aw(t)},t.curveMonotoneY=function(t){return new uw(t)},t.curveNatural=function(t){return new fw(t)},t.curveStep=function(t){return new lw(t,.5)},t.curveStepAfter=function(t){return new lw(t,1)},t.curveStepBefore=function(t){return new lw(t,0)},t.descending=e,t.deviation=w,t.difference=function(t,...n){t=new InternSet(t);for(const e of n)for(const n of e)t.delete(n);return t},t.disjoint=function(t,n){const e=n[Symbol.iterator](),r=new InternSet;for(const n of t){if(r.has(n))return!1;let t,i;for(;({value:t,done:i}=e.next())&&!i;){if(Object.is(n,t))return!1;r.add(t)}}return!0},t.dispatch=$t,t.drag=function(){var t,n,e,r,i=se,o=le,a=he,u=de,c={},f=$t("start","drag","end"),s=0,l=0;function h(t){t.on("mousedown.drag",d).filter(u).on("touchstart.drag",y).on("touchmove.drag",v,ee).on("touchend.drag touchcancel.drag",_).style("touch-action","none").style("-webkit-tap-highlight-color","rgba(0,0,0,0)")}function d(a,u){if(!r&&i.call(this,a,u)){var c=b(this,o.call(this,a,u),a,u,"mouse");c&&(Zn(a.view).on("mousemove.drag",p,re).on("mouseup.drag",g,re),ae(a.view),ie(a),e=!1,t=a.clientX,n=a.clientY,c("start",a))}}function p(r){if(oe(r),!e){var i=r.clientX-t,o=r.clientY-n;e=i*i+o*o>l}c.mouse("drag",r)}function g(t){Zn(t.view).on("mousemove.drag mouseup.drag",null),ue(t.view,e),oe(t),c.mouse("end",t)}function y(t,n){if(i.call(this,t,n)){var e,r,a=t.changedTouches,u=o.call(this,t,n),c=a.length;for(e=0;e+t,t.easePoly=wo,t.easePolyIn=mo,t.easePolyInOut=wo,t.easePolyOut=xo,t.easeQuad=_o,t.easeQuadIn=function(t){return t*t},t.easeQuadInOut=_o,t.easeQuadOut=function(t){return t*(2-t)},t.easeSin=Ao,t.easeSinIn=function(t){return 1==+t?1:1-Math.cos(t*To)},t.easeSinInOut=Ao,t.easeSinOut=function(t){return Math.sin(t*To)},t.every=function(t,n){if("function"!=typeof n)throw new TypeError("test is not a function");let e=-1;for(const r of t)if(!n(r,++e,t))return!1;return!0},t.extent=M,t.fcumsum=function(t,n){const e=new T;let r=-1;return Float64Array.from(t,void 0===n?t=>e.add(+t||0):i=>e.add(+n(i,++r,t)||0))},t.filter=function(t,n){if("function"!=typeof n)throw new TypeError("test is not a function");const e=[];let r=-1;for(const i of t)n(i,++r,t)&&e.push(i);return e},t.flatGroup=function(t,...n){return z(P(t,...n),n)},t.flatRollup=function(t,n,...e){return z(D(t,n,...e),e)},t.forceCenter=function(t,n){var e,r=1;function i(){var i,o,a=e.length,u=0,c=0;for(i=0;if+p||os+p||ac.index){var g=f-u.x-u.vx,y=s-u.y-u.vy,v=g*g+y*y;vt.r&&(t.r=t[n].r)}function c(){if(n){var r,i,o=n.length;for(e=new Array(o),r=0;r[u(t,n,r),t])));for(a=0,i=new Array(f);a=u)){(t.data!==n||t.next)&&(0===l&&(p+=(l=Uc(e))*l),0===h&&(p+=(h=Uc(e))*h),p(t=(Lc*t+jc)%Hc)/Hc}();function l(){h(),f.call("tick",n),e1?(null==e?u.delete(t):u.set(t,p(e)),n):u.get(t)},find:function(n,e,r){var i,o,a,u,c,f=0,s=t.length;for(null==r?r=1/0:r*=r,f=0;f1?(f.on(t,e),n):f.on(t)}}},t.forceX=function(t){var n,e,r,i=qc(.1);function o(t){for(var i,o=0,a=n.length;o=.12&&i<.234&&r>=-.425&&r<-.214?u:i>=.166&&i<.234&&r>=-.214&&r<-.115?c:a).invert(t)},s.stream=function(e){return t&&n===e?t:(r=[a.stream(n=e),u.stream(e),c.stream(e)],i=r.length,t={point:function(t,n){for(var e=-1;++ejs(r[0],r[1])&&(r[1]=i[1]),js(i[0],r[1])>js(r[0],r[1])&&(r[0]=i[0])):o.push(r=i);for(a=-1/0,n=0,r=o[e=o.length-1];n<=e;r=i,++n)i=o[n],(u=js(r[1],i[0]))>a&&(a=u,Wf=i[0],Kf=r[1])}return is=os=null,Wf===1/0||Zf===1/0?[[NaN,NaN],[NaN,NaN]]:[[Wf,Zf],[Kf,Qf]]},t.geoCentroid=function(t){ms=xs=ws=Ms=Ts=As=Ss=Es=0,Ns=new T,ks=new T,Cs=new T,Lf(t,Gs);var n=+Ns,e=+ks,r=+Cs,i=Ef(n,e,r);return i=0))throw new RangeError(`invalid digits: ${t}`);i=n}return null===n&&(r=new ed(i)),a},a.projection(t).digits(i).context(n)},t.geoProjection=yd,t.geoProjectionMutator=vd,t.geoRotation=ll,t.geoStereographic=function(){return yd(Bd).scale(250).clipAngle(142)},t.geoStereographicRaw=Bd,t.geoStream=Lf,t.geoTransform=function(t){return{stream:id(t)}},t.geoTransverseMercator=function(){var t=Ed(Yd),n=t.center,e=t.rotate;return t.center=function(t){return arguments.length?n([-t[1],t[0]]):[(t=n())[1],-t[0]]},t.rotate=function(t){return arguments.length?e([t[0],t[1],t.length>2?t[2]+90:90]):[(t=e())[0],t[1],t[2]-90]},e([0,0,90]).scale(159.155)},t.geoTransverseMercatorRaw=Yd,t.gray=function(t,n){return new ur(t,0,0,null==n?1:n)},t.greatest=ot,t.greatestIndex=function(t,e=n){if(1===e.length)return tt(t,e);let r,i=-1,o=-1;for(const n of t)++o,(i<0?0===e(n,n):e(n,r)>0)&&(r=n,i=o);return i},t.group=C,t.groupSort=function(t,e,r){return(2!==e.length?U($(t,e,r),(([t,e],[r,i])=>n(e,i)||n(t,r))):U(C(t,r),(([t,r],[i,o])=>e(r,o)||n(t,i)))).map((([t])=>t))},t.groups=P,t.hcl=dr,t.hierarchy=Gd,t.histogram=Q,t.hsl=He,t.html=Ec,t.image=function(t,n){return new Promise((function(e,r){var i=new Image;for(var o in n)i[o]=n[o];i.onerror=r,i.onload=function(){e(i)},i.src=t}))},t.index=function(t,...n){return F(t,k,R,n)},t.indexes=function(t,...n){return F(t,Array.from,R,n)},t.interpolate=Gr,t.interpolateArray=function(t,n){return(Ir(n)?Ur:Or)(t,n)},t.interpolateBasis=Er,t.interpolateBasisClosed=Nr,t.interpolateBlues=Gb,t.interpolateBrBG=ob,t.interpolateBuGn=Mb,t.interpolateBuPu=Ab,t.interpolateCividis=function(t){return t=Math.max(0,Math.min(1,t)),"rgb("+Math.max(0,Math.min(255,Math.round(-4.54-t*(35.34-t*(2381.73-t*(6402.7-t*(7024.72-2710.57*t)))))))+", "+Math.max(0,Math.min(255,Math.round(32.49+t*(170.73+t*(52.82-t*(131.46-t*(176.58-67.37*t)))))))+", "+Math.max(0,Math.min(255,Math.round(81.24+t*(442.36-t*(2482.43-t*(6167.24-t*(6614.94-2475.67*t)))))))+")"},t.interpolateCool=am,t.interpolateCubehelix=li,t.interpolateCubehelixDefault=im,t.interpolateCubehelixLong=hi,t.interpolateDate=Br,t.interpolateDiscrete=function(t){var n=t.length;return function(e){return t[Math.max(0,Math.min(n-1,Math.floor(e*n)))]}},t.interpolateGnBu=Eb,t.interpolateGreens=Wb,t.interpolateGreys=Kb,t.interpolateHcl=ci,t.interpolateHclLong=fi,t.interpolateHsl=oi,t.interpolateHslLong=ai,t.interpolateHue=function(t,n){var e=Pr(+t,+n);return function(t){var n=e(t);return n-360*Math.floor(n/360)}},t.interpolateInferno=pm,t.interpolateLab=function(t,n){var e=$r((t=ar(t)).l,(n=ar(n)).l),r=$r(t.a,n.a),i=$r(t.b,n.b),o=$r(t.opacity,n.opacity);return function(n){return t.l=e(n),t.a=r(n),t.b=i(n),t.opacity=o(n),t+""}},t.interpolateMagma=dm,t.interpolateNumber=Yr,t.interpolateNumberArray=Ur,t.interpolateObject=Lr,t.interpolateOrRd=kb,t.interpolateOranges=rm,t.interpolatePRGn=ub,t.interpolatePiYG=fb,t.interpolatePlasma=gm,t.interpolatePuBu=$b,t.interpolatePuBuGn=Pb,t.interpolatePuOr=lb,t.interpolatePuRd=Rb,t.interpolatePurples=Jb,t.interpolateRainbow=function(t){(t<0||t>1)&&(t-=Math.floor(t));var n=Math.abs(t-.5);return um.h=360*t-100,um.s=1.5-1.5*n,um.l=.8-.9*n,um+""},t.interpolateRdBu=db,t.interpolateRdGy=gb,t.interpolateRdPu=qb,t.interpolateRdYlBu=vb,t.interpolateRdYlGn=bb,t.interpolateReds=nm,t.interpolateRgb=Dr,t.interpolateRgbBasis=Fr,t.interpolateRgbBasisClosed=qr,t.interpolateRound=Vr,t.interpolateSinebow=function(t){var n;return t=(.5-t)*Math.PI,cm.r=255*(n=Math.sin(t))*n,cm.g=255*(n=Math.sin(t+fm))*n,cm.b=255*(n=Math.sin(t+sm))*n,cm+""},t.interpolateSpectral=xb,t.interpolateString=Xr,t.interpolateTransformCss=ti,t.interpolateTransformSvg=ni,t.interpolateTurbo=function(t){return t=Math.max(0,Math.min(1,t)),"rgb("+Math.max(0,Math.min(255,Math.round(34.61+t*(1172.33-t*(10793.56-t*(33300.12-t*(38394.49-14825.05*t)))))))+", "+Math.max(0,Math.min(255,Math.round(23.31+t*(557.33+t*(1225.33-t*(3574.96-t*(1073.77+707.56*t)))))))+", "+Math.max(0,Math.min(255,Math.round(27.2+t*(3211.1-t*(15327.97-t*(27814-t*(22569.18-6838.66*t)))))))+")"},t.interpolateViridis=hm,t.interpolateWarm=om,t.interpolateYlGn=Bb,t.interpolateYlGnBu=Ib,t.interpolateYlOrBr=Lb,t.interpolateYlOrRd=Hb,t.interpolateZoom=ri,t.interrupt=Gi,t.intersection=function(t,...n){t=new InternSet(t),n=n.map(vt);t:for(const e of t)for(const r of n)if(!r.has(e)){t.delete(e);continue t}return t},t.interval=function(t,n,e){var r=new Ei,i=n;return null==n?(r.restart(t,n,e),r):(r._restart=r.restart,r.restart=function(t,n,e){n=+n,e=null==e?Ai():+e,r._restart((function o(a){a+=i,r._restart(o,i+=n,e),t(a)}),n,e)},r.restart(t,n,e),r)},t.isoFormat=D_,t.isoParse=F_,t.json=function(t,n){return fetch(t,n).then(Tc)},t.lab=ar,t.lch=function(t,n,e,r){return 1===arguments.length?hr(t):new pr(e,n,t,null==r?1:r)},t.least=function(t,e=n){let r,i=!1;if(1===e.length){let o;for(const a of t){const t=e(a);(i?n(t,o)<0:0===n(t,t))&&(r=a,o=t,i=!0)}}else for(const n of t)(i?e(n,r)<0:0===e(n,n))&&(r=n,i=!0);return r},t.leastIndex=ht,t.line=Ym,t.lineRadial=Zm,t.link=ax,t.linkHorizontal=function(){return ax(nx)},t.linkRadial=function(){const t=ax(rx);return t.angle=t.x,delete t.x,t.radius=t.y,delete t.y,t},t.linkVertical=function(){return ax(ex)},t.local=Qn,t.map=function(t,n){if("function"!=typeof t[Symbol.iterator])throw new TypeError("values is not iterable");if("function"!=typeof n)throw new TypeError("mapper is not a function");return Array.from(t,((e,r)=>n(e,r,t)))},t.matcher=Vt,t.max=J,t.maxIndex=tt,t.mean=function(t,n){let e=0,r=0;if(void 0===n)for(let n of t)null!=n&&(n=+n)>=n&&(++e,r+=n);else{let i=-1;for(let o of t)null!=(o=n(o,++i,t))&&(o=+o)>=o&&(++e,r+=o)}if(e)return r/e},t.median=function(t,n){return at(t,.5,n)},t.medianIndex=function(t,n){return ct(t,.5,n)},t.merge=ft,t.min=nt,t.minIndex=et,t.mode=function(t,n){const e=new InternMap;if(void 0===n)for(let n of t)null!=n&&n>=n&&e.set(n,(e.get(n)||0)+1);else{let r=-1;for(let i of t)null!=(i=n(i,++r,t))&&i>=i&&e.set(i,(e.get(i)||0)+1)}let r,i=0;for(const[t,n]of e)n>i&&(i=n,r=t);return r},t.namespace=It,t.namespaces=Ut,t.nice=Z,t.now=Ai,t.pack=function(){var t=null,n=1,e=1,r=np;function i(i){const o=ap();return i.x=n/2,i.y=e/2,t?i.eachBefore(xp(t)).eachAfter(wp(r,.5,o)).eachBefore(Mp(1)):i.eachBefore(xp(mp)).eachAfter(wp(np,1,o)).eachAfter(wp(r,i.r/Math.min(n,e),o)).eachBefore(Mp(Math.min(n,e)/(2*i.r))),i}return i.radius=function(n){return arguments.length?(t=Jd(n),i):t},i.size=function(t){return arguments.length?(n=+t[0],e=+t[1],i):[n,e]},i.padding=function(t){return arguments.length?(r="function"==typeof t?t:ep(+t),i):r},i},t.packEnclose=function(t){return up(t,ap())},t.packSiblings=function(t){return bp(t,ap()),t},t.pairs=function(t,n=st){const e=[];let r,i=!1;for(const o of t)i&&e.push(n(r,o)),r=o,i=!0;return e},t.partition=function(){var t=1,n=1,e=0,r=!1;function i(i){var o=i.height+1;return i.x0=i.y0=e,i.x1=t,i.y1=n/o,i.eachBefore(function(t,n){return function(r){r.children&&Ap(r,r.x0,t*(r.depth+1)/n,r.x1,t*(r.depth+2)/n);var i=r.x0,o=r.y0,a=r.x1-e,u=r.y1-e;a0&&(d+=l);for(null!=n?p.sort((function(t,e){return n(g[t],g[e])})):null!=e&&p.sort((function(t,n){return e(a[t],a[n])})),u=0,f=d?(v-h*b)/d:0;u0?l*f:0)+b,g[c]={data:a[c],index:u,value:l,startAngle:y,endAngle:s,padAngle:_};return g}return a.value=function(n){return arguments.length?(t="function"==typeof n?n:ym(+n),a):t},a.sortValues=function(t){return arguments.length?(n=t,e=null,a):n},a.sort=function(t){return arguments.length?(e=t,n=null,a):e},a.startAngle=function(t){return arguments.length?(r="function"==typeof t?t:ym(+t),a):r},a.endAngle=function(t){return arguments.length?(i="function"==typeof t?t:ym(+t),a):i},a.padAngle=function(t){return arguments.length?(o="function"==typeof t?t:ym(+t),a):o},a},t.piecewise=di,t.pointRadial=Qm,t.pointer=ne,t.pointers=function(t,n){return t.target&&(t=te(t),void 0===n&&(n=t.currentTarget),t=t.touches||[t]),Array.from(t,(t=>ne(t,n)))},t.polygonArea=function(t){for(var n,e=-1,r=t.length,i=t[r-1],o=0;++eu!=f>u&&a<(c-e)*(u-r)/(f-r)+e&&(s=!s),c=e,f=r;return s},t.polygonHull=function(t){if((e=t.length)<3)return null;var n,e,r=new Array(e),i=new Array(e);for(n=0;n=0;--n)f.push(t[r[o[n]][2]]);for(n=+u;n(n=1664525*n+1013904223|0,lg*(n>>>0))},t.randomLogNormal=Kp,t.randomLogistic=fg,t.randomNormal=Zp,t.randomPareto=ng,t.randomPoisson=sg,t.randomUniform=Vp,t.randomWeibull=ug,t.range=lt,t.rank=function(t,e=n){if("function"!=typeof t[Symbol.iterator])throw new TypeError("values is not iterable");let r=Array.from(t);const i=new Float64Array(r.length);2!==e.length&&(r=r.map(e),e=n);const o=(t,n)=>e(r[t],r[n]);let a,u;return(t=Uint32Array.from(r,((t,n)=>n))).sort(e===n?(t,n)=>O(r[t],r[n]):I(o)),t.forEach(((t,n)=>{const e=o(t,void 0===a?t:a);e>=0?((void 0===a||e>0)&&(a=t,u=n),i[t]=u):i[t]=NaN})),i},t.reduce=function(t,n,e){if("function"!=typeof n)throw new TypeError("reducer is not a function");const r=t[Symbol.iterator]();let i,o,a=-1;if(arguments.length<3){if(({done:i,value:e}=r.next()),i)return;++a}for(;({done:i,value:o}=r.next()),!i;)e=n(e,o,++a,t);return e},t.reverse=function(t){if("function"!=typeof t[Symbol.iterator])throw new TypeError("values is not iterable");return Array.from(t).reverse()},t.rgb=Fe,t.ribbon=function(){return Wa()},t.ribbonArrow=function(){return Wa(Va)},t.rollup=$,t.rollups=D,t.scaleBand=yg,t.scaleDiverging=function t(){var n=Ng(L_()(mg));return n.copy=function(){return B_(n,t())},dg.apply(n,arguments)},t.scaleDivergingLog=function t(){var n=Fg(L_()).domain([.1,1,10]);return n.copy=function(){return B_(n,t()).base(n.base())},dg.apply(n,arguments)},t.scaleDivergingPow=j_,t.scaleDivergingSqrt=function(){return j_.apply(null,arguments).exponent(.5)},t.scaleDivergingSymlog=function t(){var n=Ig(L_());return n.copy=function(){return B_(n,t()).constant(n.constant())},dg.apply(n,arguments)},t.scaleIdentity=function t(n){var e;function r(t){return null==t||isNaN(t=+t)?e:t}return r.invert=r,r.domain=r.range=function(t){return arguments.length?(n=Array.from(t,_g),r):n.slice()},r.unknown=function(t){return arguments.length?(e=t,r):e},r.copy=function(){return t(n).unknown(e)},n=arguments.length?Array.from(n,_g):[0,1],Ng(r)},t.scaleImplicit=pg,t.scaleLinear=function t(){var n=Sg();return n.copy=function(){return Tg(n,t())},hg.apply(n,arguments),Ng(n)},t.scaleLog=function t(){const n=Fg(Ag()).domain([1,10]);return n.copy=()=>Tg(n,t()).base(n.base()),hg.apply(n,arguments),n},t.scaleOrdinal=gg,t.scalePoint=function(){return vg(yg.apply(null,arguments).paddingInner(1))},t.scalePow=jg,t.scaleQuantile=function t(){var e,r=[],i=[],o=[];function a(){var t=0,n=Math.max(1,i.length);for(o=new Array(n-1);++t0?o[n-1]:r[0],n=i?[o[i-1],r]:[o[n-1],o[n]]},u.unknown=function(t){return arguments.length?(n=t,u):u},u.thresholds=function(){return o.slice()},u.copy=function(){return t().domain([e,r]).range(a).unknown(n)},hg.apply(Ng(u),arguments)},t.scaleRadial=function t(){var n,e=Sg(),r=[0,1],i=!1;function o(t){var r=function(t){return Math.sign(t)*Math.sqrt(Math.abs(t))}(e(t));return isNaN(r)?n:i?Math.round(r):r}return o.invert=function(t){return e.invert(Hg(t))},o.domain=function(t){return arguments.length?(e.domain(t),o):e.domain()},o.range=function(t){return arguments.length?(e.range((r=Array.from(t,_g)).map(Hg)),o):r.slice()},o.rangeRound=function(t){return o.range(t).round(!0)},o.round=function(t){return arguments.length?(i=!!t,o):i},o.clamp=function(t){return arguments.length?(e.clamp(t),o):e.clamp()},o.unknown=function(t){return arguments.length?(n=t,o):n},o.copy=function(){return t(e.domain(),r).round(i).clamp(e.clamp()).unknown(n)},hg.apply(o,arguments),Ng(o)},t.scaleSequential=function t(){var n=Ng(O_()(mg));return n.copy=function(){return B_(n,t())},dg.apply(n,arguments)},t.scaleSequentialLog=function t(){var n=Fg(O_()).domain([1,10]);return n.copy=function(){return B_(n,t()).base(n.base())},dg.apply(n,arguments)},t.scaleSequentialPow=Y_,t.scaleSequentialQuantile=function t(){var e=[],r=mg;function i(t){if(null!=t&&!isNaN(t=+t))return r((s(e,t,1)-1)/(e.length-1))}return i.domain=function(t){if(!arguments.length)return e.slice();e=[];for(let n of t)null==n||isNaN(n=+n)||e.push(n);return e.sort(n),i},i.interpolator=function(t){return arguments.length?(r=t,i):r},i.range=function(){return e.map(((t,n)=>r(n/(e.length-1))))},i.quantiles=function(t){return Array.from({length:t+1},((n,r)=>at(e,r/t)))},i.copy=function(){return t(r).domain(e)},dg.apply(i,arguments)},t.scaleSequentialSqrt=function(){return Y_.apply(null,arguments).exponent(.5)},t.scaleSequentialSymlog=function t(){var n=Ig(O_());return n.copy=function(){return B_(n,t()).constant(n.constant())},dg.apply(n,arguments)},t.scaleSqrt=function(){return jg.apply(null,arguments).exponent(.5)},t.scaleSymlog=function t(){var n=Ig(Ag());return n.copy=function(){return Tg(n,t()).constant(n.constant())},hg.apply(n,arguments)},t.scaleThreshold=function t(){var n,e=[.5],r=[0,1],i=1;function o(t){return null!=t&&t<=t?r[s(e,t,0,i)]:n}return o.domain=function(t){return arguments.length?(e=Array.from(t),i=Math.min(e.length,r.length-1),o):e.slice()},o.range=function(t){return arguments.length?(r=Array.from(t),i=Math.min(e.length,r.length-1),o):r.slice()},o.invertExtent=function(t){var n=r.indexOf(t);return[e[n-1],e[n]]},o.unknown=function(t){return arguments.length?(n=t,o):n},o.copy=function(){return t().domain(e).range(r).unknown(n)},hg.apply(o,arguments)},t.scaleTime=function(){return hg.apply(I_(uv,cv,tv,Zy,xy,py,sy,ay,iy,t.timeFormat).domain([new Date(2e3,0,1),new Date(2e3,0,2)]),arguments)},t.scaleUtc=function(){return hg.apply(I_(ov,av,ev,Qy,Fy,yy,hy,cy,iy,t.utcFormat).domain([Date.UTC(2e3,0,1),Date.UTC(2e3,0,2)]),arguments)},t.scan=function(t,n){const e=ht(t,n);return e<0?void 0:e},t.schemeAccent=G_,t.schemeBlues=Xb,t.schemeBrBG=ib,t.schemeBuGn=wb,t.schemeBuPu=Tb,t.schemeCategory10=X_,t.schemeDark2=V_,t.schemeGnBu=Sb,t.schemeGreens=Vb,t.schemeGreys=Zb,t.schemeObservable10=W_,t.schemeOrRd=Nb,t.schemeOranges=em,t.schemePRGn=ab,t.schemePaired=Z_,t.schemePastel1=K_,t.schemePastel2=Q_,t.schemePiYG=cb,t.schemePuBu=zb,t.schemePuBuGn=Cb,t.schemePuOr=sb,t.schemePuRd=Db,t.schemePurples=Qb,t.schemeRdBu=hb,t.schemeRdGy=pb,t.schemeRdPu=Fb,t.schemeRdYlBu=yb,t.schemeRdYlGn=_b,t.schemeReds=tm,t.schemeSet1=J_,t.schemeSet2=tb,t.schemeSet3=nb,t.schemeSpectral=mb,t.schemeTableau10=eb,t.schemeYlGn=Ob,t.schemeYlGnBu=Ub,t.schemeYlOrBr=Yb,t.schemeYlOrRd=jb,t.select=Zn,t.selectAll=function(t){return"string"==typeof t?new Vn([document.querySelectorAll(t)],[document.documentElement]):new Vn([Ht(t)],Gn)},t.selection=Wn,t.selector=jt,t.selectorAll=Gt,t.shuffle=dt,t.shuffler=pt,t.some=function(t,n){if("function"!=typeof n)throw new TypeError("test is not a function");let e=-1;for(const r of t)if(n(r,++e,t))return!0;return!1},t.sort=U,t.stack=function(){var t=ym([]),n=dw,e=hw,r=pw;function i(i){var o,a,u=Array.from(t.apply(this,arguments),gw),c=u.length,f=-1;for(const t of i)for(o=0,++f;o0)for(var e,r,i,o,a,u,c=0,f=t[n[0]].length;c0?(r[0]=o,r[1]=o+=i):i<0?(r[1]=a,r[0]=a+=i):(r[0]=0,r[1]=i)},t.stackOffsetExpand=function(t,n){if((r=t.length)>0){for(var e,r,i,o=0,a=t[0].length;o0){for(var e,r=0,i=t[n[0]],o=i.length;r0&&(r=(e=t[n[0]]).length)>0){for(var e,r,i,o=0,a=1;afunction(t){t=`${t}`;let n=t.length;zp(t,n-1)&&!zp(t,n-2)&&(t=t.slice(0,-1));return"/"===t[0]?t:`/${t}`}(t(n,e,r)))),e=n.map(Pp),i=new Set(n).add("");for(const t of e)i.has(t)||(i.add(t),n.push(t),e.push(Pp(t)),h.push(Np));d=(t,e)=>n[e],p=(t,n)=>e[n]}for(a=0,i=h.length;a=0&&(f=h[t]).data===Np;--t)f.data=null}if(u.parent=Sp,u.eachBefore((function(t){t.depth=t.parent.depth+1,--i})).eachBefore(Kd),u.parent=null,i>0)throw new Error("cycle");return u}return r.id=function(t){return arguments.length?(n=Jd(t),r):n},r.parentId=function(t){return arguments.length?(e=Jd(t),r):e},r.path=function(n){return arguments.length?(t=Jd(n),r):t},r},t.style=_n,t.subset=function(t,n){return _t(n,t)},t.sum=function(t,n){let e=0;if(void 0===n)for(let n of t)(n=+n)&&(e+=n);else{let r=-1;for(let i of t)(i=+n(i,++r,t))&&(e+=i)}return e},t.superset=_t,t.svg=Nc,t.symbol=function(t,n){let e=null,r=km(i);function i(){let i;if(e||(e=i=r()),t.apply(this,arguments).draw(e,+n.apply(this,arguments)),i)return e=null,i+""||null}return t="function"==typeof t?t:ym(t||fx),n="function"==typeof n?n:ym(void 0===n?64:+n),i.type=function(n){return arguments.length?(t="function"==typeof n?n:ym(n),i):t},i.size=function(t){return arguments.length?(n="function"==typeof t?t:ym(+t),i):n},i.context=function(t){return arguments.length?(e=null==t?null:t,i):e},i},t.symbolAsterisk=cx,t.symbolCircle=fx,t.symbolCross=sx,t.symbolDiamond=dx,t.symbolDiamond2=px,t.symbolPlus=gx,t.symbolSquare=yx,t.symbolSquare2=vx,t.symbolStar=xx,t.symbolTimes=Px,t.symbolTriangle=Mx,t.symbolTriangle2=Ax,t.symbolWye=Cx,t.symbolX=Px,t.symbols=zx,t.symbolsFill=zx,t.symbolsStroke=$x,t.text=mc,t.thresholdFreedmanDiaconis=function(t,n,e){const r=v(t),i=at(t,.75)-at(t,.25);return r&&i?Math.ceil((e-n)/(2*i*Math.pow(r,-1/3))):1},t.thresholdScott=function(t,n,e){const r=v(t),i=w(t);return r&&i?Math.ceil((e-n)*Math.cbrt(r)/(3.49*i)):1},t.thresholdSturges=K,t.tickFormat=Eg,t.tickIncrement=V,t.tickStep=W,t.ticks=G,t.timeDay=py,t.timeDays=gy,t.timeFormatDefaultLocale=P_,t.timeFormatLocale=hv,t.timeFriday=Sy,t.timeFridays=$y,t.timeHour=sy,t.timeHours=ly,t.timeInterval=Vg,t.timeMillisecond=Wg,t.timeMilliseconds=Zg,t.timeMinute=ay,t.timeMinutes=uy,t.timeMonday=wy,t.timeMondays=ky,t.timeMonth=Zy,t.timeMonths=Ky,t.timeSaturday=Ey,t.timeSaturdays=Dy,t.timeSecond=iy,t.timeSeconds=oy,t.timeSunday=xy,t.timeSundays=Ny,t.timeThursday=Ay,t.timeThursdays=zy,t.timeTickInterval=cv,t.timeTicks=uv,t.timeTuesday=My,t.timeTuesdays=Cy,t.timeWednesday=Ty,t.timeWednesdays=Py,t.timeWeek=xy,t.timeWeeks=Ny,t.timeYear=tv,t.timeYears=nv,t.timeout=$i,t.timer=Ni,t.timerFlush=ki,t.transition=go,t.transpose=gt,t.tree=function(){var t=$p,n=1,e=1,r=null;function i(i){var c=function(t){for(var n,e,r,i,o,a=new Up(t,0),u=[a];n=u.pop();)if(r=n._.children)for(n.children=new Array(o=r.length),i=o-1;i>=0;--i)u.push(e=n.children[i]=new Up(r[i],i)),e.parent=n;return(a.parent=new Up(null,0)).children=[a],a}(i);if(c.eachAfter(o),c.parent.m=-c.z,c.eachBefore(a),r)i.eachBefore(u);else{var f=i,s=i,l=i;i.eachBefore((function(t){t.xs.x&&(s=t),t.depth>l.depth&&(l=t)}));var h=f===s?1:t(f,s)/2,d=h-f.x,p=n/(s.x+h+d),g=e/(l.depth||1);i.eachBefore((function(t){t.x=(t.x+d)*p,t.y=t.depth*g}))}return i}function o(n){var e=n.children,r=n.parent.children,i=n.i?r[n.i-1]:null;if(e){!function(t){for(var n,e=0,r=0,i=t.children,o=i.length;--o>=0;)(n=i[o]).z+=e,n.m+=e,e+=n.s+(r+=n.c)}(n);var o=(e[0].z+e[e.length-1].z)/2;i?(n.z=i.z+t(n._,i._),n.m=n.z-o):n.z=o}else i&&(n.z=i.z+t(n._,i._));n.parent.A=function(n,e,r){if(e){for(var i,o=n,a=n,u=e,c=o.parent.children[0],f=o.m,s=a.m,l=u.m,h=c.m;u=Rp(u),o=Dp(o),u&&o;)c=Dp(c),(a=Rp(a)).a=n,(i=u.z+l-o.z-f+t(u._,o._))>0&&(Fp(qp(u,n,r),n,i),f+=i,s+=i),l+=u.m,f+=o.m,h+=c.m,s+=a.m;u&&!Rp(a)&&(a.t=u,a.m+=l-s),o&&!Dp(c)&&(c.t=o,c.m+=f-h,r=n)}return r}(n,i,n.parent.A||r[0])}function a(t){t._.x=t.z+t.parent.m,t.m+=t.parent.m}function u(t){t.x*=n,t.y=t.depth*e}return i.separation=function(n){return arguments.length?(t=n,i):t},i.size=function(t){return arguments.length?(r=!1,n=+t[0],e=+t[1],i):r?null:[n,e]},i.nodeSize=function(t){return arguments.length?(r=!0,n=+t[0],e=+t[1],i):r?[n,e]:null},i},t.treemap=function(){var t=Yp,n=!1,e=1,r=1,i=[0],o=np,a=np,u=np,c=np,f=np;function s(t){return t.x0=t.y0=0,t.x1=e,t.y1=r,t.eachBefore(l),i=[0],n&&t.eachBefore(Tp),t}function l(n){var e=i[n.depth],r=n.x0+e,s=n.y0+e,l=n.x1-e,h=n.y1-e;l=e-1){var s=u[n];return s.x0=i,s.y0=o,s.x1=a,void(s.y1=c)}var l=f[n],h=r/2+l,d=n+1,p=e-1;for(;d>>1;f[g]c-o){var _=r?(i*v+a*y)/r:a;t(n,d,y,i,o,_,c),t(d,e,v,_,o,a,c)}else{var b=r?(o*v+c*y)/r:c;t(n,d,y,i,o,a,b),t(d,e,v,i,b,a,c)}}(0,c,t.value,n,e,r,i)},t.treemapDice=Ap,t.treemapResquarify=Lp,t.treemapSlice=Ip,t.treemapSliceDice=function(t,n,e,r,i){(1&t.depth?Ip:Ap)(t,n,e,r,i)},t.treemapSquarify=Yp,t.tsv=Mc,t.tsvFormat=lc,t.tsvFormatBody=hc,t.tsvFormatRow=pc,t.tsvFormatRows=dc,t.tsvFormatValue=gc,t.tsvParse=fc,t.tsvParseRows=sc,t.union=function(...t){const n=new InternSet;for(const e of t)for(const t of e)n.add(t);return n},t.unixDay=_y,t.unixDays=by,t.utcDay=yy,t.utcDays=vy,t.utcFriday=By,t.utcFridays=Vy,t.utcHour=hy,t.utcHours=dy,t.utcMillisecond=Wg,t.utcMilliseconds=Zg,t.utcMinute=cy,t.utcMinutes=fy,t.utcMonday=qy,t.utcMondays=jy,t.utcMonth=Qy,t.utcMonths=Jy,t.utcSaturday=Yy,t.utcSaturdays=Wy,t.utcSecond=iy,t.utcSeconds=oy,t.utcSunday=Fy,t.utcSundays=Ly,t.utcThursday=Oy,t.utcThursdays=Gy,t.utcTickInterval=av,t.utcTicks=ov,t.utcTuesday=Uy,t.utcTuesdays=Hy,t.utcWednesday=Iy,t.utcWednesdays=Xy,t.utcWeek=Fy,t.utcWeeks=Ly,t.utcYear=ev,t.utcYears=rv,t.variance=x,t.version="7.9.0",t.window=pn,t.xml=Sc,t.zip=function(){return gt(arguments)},t.zoom=function(){var t,n,e,r=Ew,i=Nw,o=zw,a=Cw,u=Pw,c=[0,1/0],f=[[-1/0,-1/0],[1/0,1/0]],s=250,l=ri,h=$t("start","zoom","end"),d=500,p=150,g=0,y=10;function v(t){t.property("__zoom",kw).on("wheel.zoom",T,{passive:!1}).on("mousedown.zoom",A).on("dblclick.zoom",S).filter(u).on("touchstart.zoom",E).on("touchmove.zoom",N).on("touchend.zoom touchcancel.zoom",k).style("-webkit-tap-highlight-color","rgba(0,0,0,0)")}function _(t,n){return(n=Math.max(c[0],Math.min(c[1],n)))===t.k?t:new ww(n,t.x,t.y)}function b(t,n,e){var r=n[0]-e[0]*t.k,i=n[1]-e[1]*t.k;return r===t.x&&i===t.y?t:new ww(t.k,r,i)}function m(t){return[(+t[0][0]+ +t[1][0])/2,(+t[0][1]+ +t[1][1])/2]}function x(t,n,e,r){t.on("start.zoom",(function(){w(this,arguments).event(r).start()})).on("interrupt.zoom end.zoom",(function(){w(this,arguments).event(r).end()})).tween("zoom",(function(){var t=this,o=arguments,a=w(t,o).event(r),u=i.apply(t,o),c=null==e?m(u):"function"==typeof e?e.apply(t,o):e,f=Math.max(u[1][0]-u[0][0],u[1][1]-u[0][1]),s=t.__zoom,h="function"==typeof n?n.apply(t,o):n,d=l(s.invert(c).concat(f/s.k),h.invert(c).concat(f/h.k));return function(t){if(1===t)t=h;else{var n=d(t),e=f/n[2];t=new ww(e,c[0]-n[0]*e,c[1]-n[1]*e)}a.zoom(null,t)}}))}function w(t,n,e){return!e&&t.__zooming||new M(t,n)}function M(t,n){this.that=t,this.args=n,this.active=0,this.sourceEvent=null,this.extent=i.apply(t,n),this.taps=0}function T(t,...n){if(r.apply(this,arguments)){var e=w(this,n).event(t),i=this.__zoom,u=Math.max(c[0],Math.min(c[1],i.k*Math.pow(2,a.apply(this,arguments)))),s=ne(t);if(e.wheel)e.mouse[0][0]===s[0]&&e.mouse[0][1]===s[1]||(e.mouse[1]=i.invert(e.mouse[0]=s)),clearTimeout(e.wheel);else{if(i.k===u)return;e.mouse=[s,i.invert(s)],Gi(this),e.start()}Sw(t),e.wheel=setTimeout((function(){e.wheel=null,e.end()}),p),e.zoom("mouse",o(b(_(i,u),e.mouse[0],e.mouse[1]),e.extent,f))}}function A(t,...n){if(!e&&r.apply(this,arguments)){var i=t.currentTarget,a=w(this,n,!0).event(t),u=Zn(t.view).on("mousemove.zoom",(function(t){if(Sw(t),!a.moved){var n=t.clientX-s,e=t.clientY-l;a.moved=n*n+e*e>g}a.event(t).zoom("mouse",o(b(a.that.__zoom,a.mouse[0]=ne(t,i),a.mouse[1]),a.extent,f))}),!0).on("mouseup.zoom",(function(t){u.on("mousemove.zoom mouseup.zoom",null),ue(t.view,a.moved),Sw(t),a.event(t).end()}),!0),c=ne(t,i),s=t.clientX,l=t.clientY;ae(t.view),Aw(t),a.mouse=[c,this.__zoom.invert(c)],Gi(this),a.start()}}function S(t,...n){if(r.apply(this,arguments)){var e=this.__zoom,a=ne(t.changedTouches?t.changedTouches[0]:t,this),u=e.invert(a),c=e.k*(t.shiftKey?.5:2),l=o(b(_(e,c),a,u),i.apply(this,n),f);Sw(t),s>0?Zn(this).transition().duration(s).call(x,l,a,t):Zn(this).call(v.transform,l,a,t)}}function E(e,...i){if(r.apply(this,arguments)){var o,a,u,c,f=e.touches,s=f.length,l=w(this,i,e.changedTouches.length===s).event(e);for(Aw(e),a=0;a{let label=g.edge(e);g.removeEdge(e);label.forwardName=e.name;label.reversed=true;g.setEdge(e.w,e.v,label,uniqueId("rev"))});function weightFn(g){return e=>{return g.edge(e).weight}}}function dfsFAS(g){let fas=[];let stack={};let visited={};function dfs(v){if(Object.hasOwn(visited,v)){return}visited[v]=true;stack[v]=true;g.outEdges(v).forEach(e=>{if(Object.hasOwn(stack,e.w)){fas.push(e)}else{dfs(e.w)}});delete stack[v]}g.nodes().forEach(dfs);return fas}function undo(g){g.edges().forEach(e=>{let label=g.edge(e);if(label.reversed){g.removeEdge(e);let forwardName=label.forwardName;delete label.reversed;delete label.forwardName;g.setEdge(e.w,e.v,label,forwardName)}})}},{"./greedy-fas":7,"./util":27}],3:[function(require,module,exports){let util=require("./util");module.exports=addBorderSegments;function addBorderSegments(g){function dfs(v){let children=g.children(v);let node=g.node(v);if(children.length){children.forEach(dfs)}if(Object.hasOwn(node,"minRank")){node.borderLeft=[];node.borderRight=[];for(let rank=node.minRank,maxRank=node.maxRank+1;rankswapWidthHeightOne(g.node(v)));g.edges().forEach(e=>swapWidthHeightOne(g.edge(e)))}function swapWidthHeightOne(attrs){let w=attrs.width;attrs.width=attrs.height;attrs.height=w}function reverseY(g){g.nodes().forEach(v=>reverseYOne(g.node(v)));g.edges().forEach(e=>{let edge=g.edge(e);edge.points.forEach(reverseYOne);if(Object.hasOwn(edge,"y")){reverseYOne(edge)}})}function reverseYOne(attrs){attrs.y=-attrs.y}function swapXY(g){g.nodes().forEach(v=>swapXYOne(g.node(v)));g.edges().forEach(e=>{let edge=g.edge(e);edge.points.forEach(swapXYOne);if(Object.hasOwn(edge,"x")){swapXYOne(edge)}})}function swapXYOne(attrs){let x=attrs.x;attrs.x=attrs.y;attrs.y=x}},{}],5:[function(require,module,exports){ -/* - * Simple doubly linked list implementation derived from Cormen, et al., - * "Introduction to Algorithms". - */ -class List{constructor(){let sentinel={};sentinel._next=sentinel._prev=sentinel;this._sentinel=sentinel}dequeue(){let sentinel=this._sentinel;let entry=sentinel._prev;if(entry!==sentinel){unlink(entry);return entry}}enqueue(entry){let sentinel=this._sentinel;if(entry._prev&&entry._next){unlink(entry)}entry._next=sentinel._next;sentinel._next._prev=entry;sentinel._next=entry;entry._prev=sentinel}toString(){let strs=[];let sentinel=this._sentinel;let curr=sentinel._prev;while(curr!==sentinel){strs.push(JSON.stringify(curr,filterOutLinks));curr=curr._prev}return"["+strs.join(", ")+"]"}}function unlink(entry){entry._prev._next=entry._next;entry._next._prev=entry._prev;delete entry._next;delete entry._prev}function filterOutLinks(k,v){if(k!=="_next"&&k!=="_prev"){return v}}module.exports=List},{}],6:[function(require,module,exports){let util=require("./util");let Graph=require("@dagrejs/graphlib").Graph;module.exports={debugOrdering:debugOrdering}; -/* istanbul ignore next */function debugOrdering(g){let layerMatrix=util.buildLayerMatrix(g);let h=new Graph({compound:true,multigraph:true}).setGraph({});g.nodes().forEach(v=>{h.setNode(v,{label:v});h.setParent(v,"layer"+g.node(v).rank)});g.edges().forEach(e=>h.setEdge(e.v,e.w,{},e.name));layerMatrix.forEach((layer,i)=>{let layerV="layer"+i;h.setNode(layerV,{rank:"same"});layer.reduce((u,v)=>{h.setEdge(u,v,{style:"invis"});return v})});return h}},{"./util":27,"@dagrejs/graphlib":29}],7:[function(require,module,exports){let Graph=require("@dagrejs/graphlib").Graph;let List=require("./data/list"); -/* - * A greedy heuristic for finding a feedback arc set for a graph. A feedback - * arc set is a set of edges that can be removed to make a graph acyclic. - * The algorithm comes from: P. Eades, X. Lin, and W. F. Smyth, "A fast and - * effective heuristic for the feedback arc set problem." This implementation - * adjusts that from the paper to allow for weighted edges. - */module.exports=greedyFAS;let DEFAULT_WEIGHT_FN=()=>1;function greedyFAS(g,weightFn){if(g.nodeCount()<=1){return[]}let state=buildState(g,weightFn||DEFAULT_WEIGHT_FN);let results=doGreedyFAS(state.graph,state.buckets,state.zeroIdx); -// Expand multi-edges -return results.flatMap(e=>g.outEdges(e.v,e.w))}function doGreedyFAS(g,buckets,zeroIdx){let results=[];let sources=buckets[buckets.length-1];let sinks=buckets[0];let entry;while(g.nodeCount()){while(entry=sinks.dequeue()){removeNode(g,buckets,zeroIdx,entry)}while(entry=sources.dequeue()){removeNode(g,buckets,zeroIdx,entry)}if(g.nodeCount()){for(let i=buckets.length-2;i>0;--i){entry=buckets[i].dequeue();if(entry){results=results.concat(removeNode(g,buckets,zeroIdx,entry,true));break}}}}return results}function removeNode(g,buckets,zeroIdx,entry,collectPredecessors){let results=collectPredecessors?[]:undefined;g.inEdges(entry.v).forEach(edge=>{let weight=g.edge(edge);let uEntry=g.node(edge.v);if(collectPredecessors){results.push({v:edge.v,w:edge.w})}uEntry.out-=weight;assignBucket(buckets,zeroIdx,uEntry)});g.outEdges(entry.v).forEach(edge=>{let weight=g.edge(edge);let w=edge.w;let wEntry=g.node(w);wEntry["in"]-=weight;assignBucket(buckets,zeroIdx,wEntry)});g.removeNode(entry.v);return results}function buildState(g,weightFn){let fasGraph=new Graph;let maxIn=0;let maxOut=0;g.nodes().forEach(v=>{fasGraph.setNode(v,{v:v,in:0,out:0})}); -// Aggregate weights on nodes, but also sum the weights across multi-edges -// into a single edge for the fasGraph. -g.edges().forEach(e=>{let prevWeight=fasGraph.edge(e.v,e.w)||0;let weight=weightFn(e);let edgeWeight=prevWeight+weight;fasGraph.setEdge(e.v,e.w,edgeWeight);maxOut=Math.max(maxOut,fasGraph.node(e.v).out+=weight);maxIn=Math.max(maxIn,fasGraph.node(e.w)["in"]+=weight)});let buckets=range(maxOut+maxIn+3).map(()=>new List);let zeroIdx=maxIn+1;fasGraph.nodes().forEach(v=>{assignBucket(buckets,zeroIdx,fasGraph.node(v))});return{graph:fasGraph,buckets:buckets,zeroIdx:zeroIdx}}function assignBucket(buckets,zeroIdx,entry){if(!entry.out){buckets[0].enqueue(entry)}else if(!entry["in"]){buckets[buckets.length-1].enqueue(entry)}else{buckets[entry.out-entry["in"]+zeroIdx].enqueue(entry)}}function range(limit){const range=[];for(let i=0;i{let layoutGraph=time(" buildLayoutGraph",()=>buildLayoutGraph(g));time(" runLayout",()=>runLayout(layoutGraph,time,opts));time(" updateInputGraph",()=>updateInputGraph(g,layoutGraph))})}function runLayout(g,time,opts){time(" makeSpaceForEdgeLabels",()=>makeSpaceForEdgeLabels(g));time(" removeSelfEdges",()=>removeSelfEdges(g));time(" acyclic",()=>acyclic.run(g));time(" nestingGraph.run",()=>nestingGraph.run(g));time(" rank",()=>rank(util.asNonCompoundGraph(g)));time(" injectEdgeLabelProxies",()=>injectEdgeLabelProxies(g));time(" removeEmptyRanks",()=>removeEmptyRanks(g));time(" nestingGraph.cleanup",()=>nestingGraph.cleanup(g));time(" normalizeRanks",()=>normalizeRanks(g));time(" assignRankMinMax",()=>assignRankMinMax(g));time(" removeEdgeLabelProxies",()=>removeEdgeLabelProxies(g));time(" normalize.run",()=>normalize.run(g));time(" parentDummyChains",()=>parentDummyChains(g));time(" addBorderSegments",()=>addBorderSegments(g));time(" order",()=>order(g,opts));time(" insertSelfEdges",()=>insertSelfEdges(g));time(" adjustCoordinateSystem",()=>coordinateSystem.adjust(g));time(" position",()=>position(g));time(" positionSelfEdges",()=>positionSelfEdges(g));time(" removeBorderNodes",()=>removeBorderNodes(g));time(" normalize.undo",()=>normalize.undo(g));time(" fixupEdgeLabelCoords",()=>fixupEdgeLabelCoords(g));time(" undoCoordinateSystem",()=>coordinateSystem.undo(g));time(" translateGraph",()=>translateGraph(g));time(" assignNodeIntersects",()=>assignNodeIntersects(g));time(" reversePoints",()=>reversePointsForReversedEdges(g));time(" acyclic.undo",()=>acyclic.undo(g))} -/* - * Copies final layout information from the layout graph back to the input - * graph. This process only copies whitelisted attributes from the layout graph - * to the input graph, so it serves as a good place to determine what - * attributes can influence layout. - */function updateInputGraph(inputGraph,layoutGraph){inputGraph.nodes().forEach(v=>{let inputLabel=inputGraph.node(v);let layoutLabel=layoutGraph.node(v);if(inputLabel){inputLabel.x=layoutLabel.x;inputLabel.y=layoutLabel.y;inputLabel.rank=layoutLabel.rank;if(layoutGraph.children(v).length){inputLabel.width=layoutLabel.width;inputLabel.height=layoutLabel.height}}});inputGraph.edges().forEach(e=>{let inputLabel=inputGraph.edge(e);let layoutLabel=layoutGraph.edge(e);inputLabel.points=layoutLabel.points;if(Object.hasOwn(layoutLabel,"x")){inputLabel.x=layoutLabel.x;inputLabel.y=layoutLabel.y}});inputGraph.graph().width=layoutGraph.graph().width;inputGraph.graph().height=layoutGraph.graph().height}let graphNumAttrs=["nodesep","edgesep","ranksep","marginx","marginy"];let graphDefaults={ranksep:50,edgesep:20,nodesep:50,rankdir:"tb"};let graphAttrs=["acyclicer","ranker","rankdir","align"];let nodeNumAttrs=["width","height"];let nodeDefaults={width:0,height:0};let edgeNumAttrs=["minlen","weight","width","height","labeloffset"];let edgeDefaults={minlen:1,weight:1,width:0,height:0,labeloffset:10,labelpos:"r"};let edgeAttrs=["labelpos"]; -/* - * Constructs a new graph from the input graph, which can be used for layout. - * This process copies only whitelisted attributes from the input graph to the - * layout graph. Thus this function serves as a good place to determine what - * attributes can influence layout. - */function buildLayoutGraph(inputGraph){let g=new Graph({multigraph:true,compound:true});let graph=canonicalize(inputGraph.graph());g.setGraph(Object.assign({},graphDefaults,selectNumberAttrs(graph,graphNumAttrs),util.pick(graph,graphAttrs)));inputGraph.nodes().forEach(v=>{let node=canonicalize(inputGraph.node(v));const newNode=selectNumberAttrs(node,nodeNumAttrs);Object.keys(nodeDefaults).forEach(k=>{if(newNode[k]===undefined){newNode[k]=nodeDefaults[k]}});g.setNode(v,newNode);g.setParent(v,inputGraph.parent(v))});inputGraph.edges().forEach(e=>{let edge=canonicalize(inputGraph.edge(e));g.setEdge(e,Object.assign({},edgeDefaults,selectNumberAttrs(edge,edgeNumAttrs),util.pick(edge,edgeAttrs)))});return g} -/* - * This idea comes from the Gansner paper: to account for edge labels in our - * layout we split each rank in half by doubling minlen and halving ranksep. - * Then we can place labels at these mid-points between nodes. - * - * We also add some minimal padding to the width to push the label for the edge - * away from the edge itself a bit. - */function makeSpaceForEdgeLabels(g){let graph=g.graph();graph.ranksep/=2;g.edges().forEach(e=>{let edge=g.edge(e);edge.minlen*=2;if(edge.labelpos.toLowerCase()!=="c"){if(graph.rankdir==="TB"||graph.rankdir==="BT"){edge.width+=edge.labeloffset}else{edge.height+=edge.labeloffset}}})} -/* - * Creates temporary dummy nodes that capture the rank in which each edge's - * label is going to, if it has one of non-zero width and height. We do this - * so that we can safely remove empty ranks while preserving balance for the - * label's position. - */function injectEdgeLabelProxies(g){g.edges().forEach(e=>{let edge=g.edge(e);if(edge.width&&edge.height){let v=g.node(e.v);let w=g.node(e.w);let label={rank:(w.rank-v.rank)/2+v.rank,e:e};util.addDummyNode(g,"edge-proxy",label,"_ep")}})}function assignRankMinMax(g){let maxRank=0;g.nodes().forEach(v=>{let node=g.node(v);if(node.borderTop){node.minRank=g.node(node.borderTop).rank;node.maxRank=g.node(node.borderBottom).rank;maxRank=Math.max(maxRank,node.maxRank)}});g.graph().maxRank=maxRank}function removeEdgeLabelProxies(g){g.nodes().forEach(v=>{let node=g.node(v);if(node.dummy==="edge-proxy"){g.edge(node.e).labelRank=node.rank;g.removeNode(v)}})}function translateGraph(g){let minX=Number.POSITIVE_INFINITY;let maxX=0;let minY=Number.POSITIVE_INFINITY;let maxY=0;let graphLabel=g.graph();let marginX=graphLabel.marginx||0;let marginY=graphLabel.marginy||0;function getExtremes(attrs){let x=attrs.x;let y=attrs.y;let w=attrs.width;let h=attrs.height;minX=Math.min(minX,x-w/2);maxX=Math.max(maxX,x+w/2);minY=Math.min(minY,y-h/2);maxY=Math.max(maxY,y+h/2)}g.nodes().forEach(v=>getExtremes(g.node(v)));g.edges().forEach(e=>{let edge=g.edge(e);if(Object.hasOwn(edge,"x")){getExtremes(edge)}});minX-=marginX;minY-=marginY;g.nodes().forEach(v=>{let node=g.node(v);node.x-=minX;node.y-=minY});g.edges().forEach(e=>{let edge=g.edge(e);edge.points.forEach(p=>{p.x-=minX;p.y-=minY});if(Object.hasOwn(edge,"x")){edge.x-=minX}if(Object.hasOwn(edge,"y")){edge.y-=minY}});graphLabel.width=maxX-minX+marginX;graphLabel.height=maxY-minY+marginY}function assignNodeIntersects(g){g.edges().forEach(e=>{let edge=g.edge(e);let nodeV=g.node(e.v);let nodeW=g.node(e.w);let p1,p2;if(!edge.points){edge.points=[];p1=nodeW;p2=nodeV}else{p1=edge.points[0];p2=edge.points[edge.points.length-1]}edge.points.unshift(util.intersectRect(nodeV,p1));edge.points.push(util.intersectRect(nodeW,p2))})}function fixupEdgeLabelCoords(g){g.edges().forEach(e=>{let edge=g.edge(e);if(Object.hasOwn(edge,"x")){if(edge.labelpos==="l"||edge.labelpos==="r"){edge.width-=edge.labeloffset}switch(edge.labelpos){case"l":edge.x-=edge.width/2+edge.labeloffset;break;case"r":edge.x+=edge.width/2+edge.labeloffset;break}}})}function reversePointsForReversedEdges(g){g.edges().forEach(e=>{let edge=g.edge(e);if(edge.reversed){edge.points.reverse()}})}function removeBorderNodes(g){g.nodes().forEach(v=>{if(g.children(v).length){let node=g.node(v);let t=g.node(node.borderTop);let b=g.node(node.borderBottom);let l=g.node(node.borderLeft[node.borderLeft.length-1]);let r=g.node(node.borderRight[node.borderRight.length-1]);node.width=Math.abs(r.x-l.x);node.height=Math.abs(b.y-t.y);node.x=l.x+node.width/2;node.y=t.y+node.height/2}});g.nodes().forEach(v=>{if(g.node(v).dummy==="border"){g.removeNode(v)}})}function removeSelfEdges(g){g.edges().forEach(e=>{if(e.v===e.w){var node=g.node(e.v);if(!node.selfEdges){node.selfEdges=[]}node.selfEdges.push({e:e,label:g.edge(e)});g.removeEdge(e)}})}function insertSelfEdges(g){var layers=util.buildLayerMatrix(g);layers.forEach(layer=>{var orderShift=0;layer.forEach((v,i)=>{var node=g.node(v);node.order=i+orderShift;(node.selfEdges||[]).forEach(selfEdge=>{util.addDummyNode(g,"selfedge",{width:selfEdge.label.width,height:selfEdge.label.height,rank:node.rank,order:i+ ++orderShift,e:selfEdge.e,label:selfEdge.label},"_se")});delete node.selfEdges})})}function positionSelfEdges(g){g.nodes().forEach(v=>{var node=g.node(v);if(node.dummy==="selfedge"){var selfNode=g.node(node.e.v);var x=selfNode.x+selfNode.width/2;var y=selfNode.y;var dx=node.x-x;var dy=selfNode.height/2;g.setEdge(node.e,node.label);g.removeNode(v);node.label.points=[{x:x+2*dx/3,y:y-dy},{x:x+5*dx/6,y:y-dy},{x:x+dx,y:y},{x:x+5*dx/6,y:y+dy},{x:x+2*dx/3,y:y+dy}];node.label.x=node.x;node.label.y=node.y}})}function selectNumberAttrs(obj,attrs){return util.mapValues(util.pick(obj,attrs),Number)}function canonicalize(attrs){var newAttrs={};if(attrs){Object.entries(attrs).forEach(([k,v])=>{if(typeof k==="string"){k=k.toLowerCase()}newAttrs[k]=v})}return newAttrs}},{"./acyclic":2,"./add-border-segments":3,"./coordinate-system":4,"./nesting-graph":9,"./normalize":10,"./order":15,"./parent-dummy-chains":20,"./position":22,"./rank":24,"./util":27,"@dagrejs/graphlib":29}],9:[function(require,module,exports){let util=require("./util");module.exports={run:run,cleanup:cleanup}; -/* - * A nesting graph creates dummy nodes for the tops and bottoms of subgraphs, - * adds appropriate edges to ensure that all cluster nodes are placed between - * these boundaries, and ensures that the graph is connected. - * - * In addition we ensure, through the use of the minlen property, that nodes - * and subgraph border nodes to not end up on the same rank. - * - * Preconditions: - * - * 1. Input graph is a DAG - * 2. Nodes in the input graph has a minlen attribute - * - * Postconditions: - * - * 1. Input graph is connected. - * 2. Dummy nodes are added for the tops and bottoms of subgraphs. - * 3. The minlen attribute for nodes is adjusted to ensure nodes do not - * get placed on the same rank as subgraph border nodes. - * - * The nesting graph idea comes from Sander, "Layout of Compound Directed - * Graphs." - */function run(g){let root=util.addDummyNode(g,"root",{},"_root");let depths=treeDepths(g);let depthsArr=Object.values(depths);let height=util.applyWithChunking(Math.max,depthsArr)-1;// Note: depths is an Object not an array -let nodeSep=2*height+1;g.graph().nestingRoot=root; -// Multiply minlen by nodeSep to align nodes on non-border ranks. -g.edges().forEach(e=>g.edge(e).minlen*=nodeSep); -// Calculate a weight that is sufficient to keep subgraphs vertically compact -let weight=sumWeights(g)+1; -// Create border nodes and link them up -g.children().forEach(child=>dfs(g,root,nodeSep,weight,height,depths,child)); -// Save the multiplier for node layers for later removal of empty border -// layers. -g.graph().nodeRankFactor=nodeSep}function dfs(g,root,nodeSep,weight,height,depths,v){let children=g.children(v);if(!children.length){if(v!==root){g.setEdge(root,v,{weight:0,minlen:nodeSep})}return}let top=util.addBorderNode(g,"_bt");let bottom=util.addBorderNode(g,"_bb");let label=g.node(v);g.setParent(top,v);label.borderTop=top;g.setParent(bottom,v);label.borderBottom=bottom;children.forEach(child=>{dfs(g,root,nodeSep,weight,height,depths,child);let childNode=g.node(child);let childTop=childNode.borderTop?childNode.borderTop:child;let childBottom=childNode.borderBottom?childNode.borderBottom:child;let thisWeight=childNode.borderTop?weight:2*weight;let minlen=childTop!==childBottom?1:height-depths[v]+1;g.setEdge(top,childTop,{weight:thisWeight,minlen:minlen,nestingEdge:true});g.setEdge(childBottom,bottom,{weight:thisWeight,minlen:minlen,nestingEdge:true})});if(!g.parent(v)){g.setEdge(root,top,{weight:0,minlen:height+depths[v]})}}function treeDepths(g){var depths={};function dfs(v,depth){var children=g.children(v);if(children&&children.length){children.forEach(child=>dfs(child,depth+1))}depths[v]=depth}g.children().forEach(v=>dfs(v,1));return depths}function sumWeights(g){return g.edges().reduce((acc,e)=>acc+g.edge(e).weight,0)}function cleanup(g){var graphLabel=g.graph();g.removeNode(graphLabel.nestingRoot);delete graphLabel.nestingRoot;g.edges().forEach(e=>{var edge=g.edge(e);if(edge.nestingEdge){g.removeEdge(e)}})}},{"./util":27}],10:[function(require,module,exports){"use strict";let util=require("./util");module.exports={run:run,undo:undo}; -/* - * Breaks any long edges in the graph into short segments that span 1 layer - * each. This operation is undoable with the denormalize function. - * - * Pre-conditions: - * - * 1. The input graph is a DAG. - * 2. Each node in the graph has a "rank" property. - * - * Post-condition: - * - * 1. All edges in the graph have a length of 1. - * 2. Dummy nodes are added where edges have been split into segments. - * 3. The graph is augmented with a "dummyChains" attribute which contains - * the first dummy in each chain of dummy nodes produced. - */function run(g){g.graph().dummyChains=[];g.edges().forEach(edge=>normalizeEdge(g,edge))}function normalizeEdge(g,e){let v=e.v;let vRank=g.node(v).rank;let w=e.w;let wRank=g.node(w).rank;let name=e.name;let edgeLabel=g.edge(e);let labelRank=edgeLabel.labelRank;if(wRank===vRank+1)return;g.removeEdge(e);let dummy,attrs,i;for(i=0,++vRank;vRank{let node=g.node(v);let origLabel=node.edgeLabel;let w;g.setEdge(node.edgeObj,origLabel);while(node.dummy){w=g.successors(v)[0];g.removeNode(v);origLabel.points.push({x:node.x,y:node.y});if(node.dummy==="edge-label"){origLabel.x=node.x;origLabel.y=node.y;origLabel.width=node.width;origLabel.height=node.height}v=w;node=g.node(v)}})}},{"./util":27}],11:[function(require,module,exports){module.exports=addSubgraphConstraints;function addSubgraphConstraints(g,cg,vs){let prev={},rootPrev;vs.forEach(v=>{let child=g.parent(v),parent,prevChild;while(child){parent=g.parent(child);if(parent){prevChild=prev[parent];prev[parent]=child}else{prevChild=rootPrev;rootPrev=child}if(prevChild&&prevChild!==child){cg.setEdge(prevChild,child);return}child=parent}}); -/* - function dfs(v) { - var children = v ? g.children(v) : g.children(); - if (children.length) { - var min = Number.POSITIVE_INFINITY, - subgraphs = []; - children.forEach(function(child) { - var childMin = dfs(child); - if (g.children(child).length) { - subgraphs.push({ v: child, order: childMin }); - } - min = Math.min(min, childMin); - }); - _.sortBy(subgraphs, "order").reduce(function(prev, curr) { - cg.setEdge(prev.v, curr.v); - return curr; - }); - return min; - } - return g.node(v).order; - } - dfs(undefined); - */}},{}],12:[function(require,module,exports){module.exports=barycenter;function barycenter(g,movable=[]){return movable.map(v=>{let inV=g.inEdges(v);if(!inV.length){return{v:v}}else{let result=inV.reduce((acc,e)=>{let edge=g.edge(e),nodeU=g.node(e.v);return{sum:acc.sum+edge.weight*nodeU.order,weight:acc.weight+edge.weight}},{sum:0,weight:0});return{v:v,barycenter:result.sum/result.weight,weight:result.weight}}})}},{}],13:[function(require,module,exports){let Graph=require("@dagrejs/graphlib").Graph;let util=require("../util");module.exports=buildLayerGraph; -/* - * Constructs a graph that can be used to sort a layer of nodes. The graph will - * contain all base and subgraph nodes from the request layer in their original - * hierarchy and any edges that are incident on these nodes and are of the type - * requested by the "relationship" parameter. - * - * Nodes from the requested rank that do not have parents are assigned a root - * node in the output graph, which is set in the root graph attribute. This - * makes it easy to walk the hierarchy of movable nodes during ordering. - * - * Pre-conditions: - * - * 1. Input graph is a DAG - * 2. Base nodes in the input graph have a rank attribute - * 3. Subgraph nodes in the input graph has minRank and maxRank attributes - * 4. Edges have an assigned weight - * - * Post-conditions: - * - * 1. Output graph has all nodes in the movable rank with preserved - * hierarchy. - * 2. Root nodes in the movable layer are made children of the node - * indicated by the root attribute of the graph. - * 3. Non-movable nodes incident on movable nodes, selected by the - * relationship parameter, are included in the graph (without hierarchy). - * 4. Edges incident on movable nodes, selected by the relationship - * parameter, are added to the output graph. - * 5. The weights for copied edges are aggregated as need, since the output - * graph is not a multi-graph. - */function buildLayerGraph(g,rank,relationship){let root=createRootNode(g),result=new Graph({compound:true}).setGraph({root:root}).setDefaultNodeLabel(v=>g.node(v));g.nodes().forEach(v=>{let node=g.node(v),parent=g.parent(v);if(node.rank===rank||node.minRank<=rank&&rank<=node.maxRank){result.setNode(v);result.setParent(v,parent||root); -// This assumes we have only short edges! -g[relationship](v).forEach(e=>{let u=e.v===v?e.w:e.v,edge=result.edge(u,v),weight=edge!==undefined?edge.weight:0;result.setEdge(u,v,{weight:g.edge(e).weight+weight})});if(Object.hasOwn(node,"minRank")){result.setNode(v,{borderLeft:node.borderLeft[rank],borderRight:node.borderRight[rank]})}}});return result}function createRootNode(g){var v;while(g.hasNode(v=util.uniqueId("_root")));return v}},{"../util":27,"@dagrejs/graphlib":29}],14:[function(require,module,exports){"use strict";let zipObject=require("../util").zipObject;module.exports=crossCount; -/* - * A function that takes a layering (an array of layers, each with an array of - * ordererd nodes) and a graph and returns a weighted crossing count. - * - * Pre-conditions: - * - * 1. Input graph must be simple (not a multigraph), directed, and include - * only simple edges. - * 2. Edges in the input graph must have assigned weights. - * - * Post-conditions: - * - * 1. The graph and layering matrix are left unchanged. - * - * This algorithm is derived from Barth, et al., "Bilayer Cross Counting." - */function crossCount(g,layering){let cc=0;for(let i=1;ii));let southEntries=northLayer.flatMap(v=>{return g.outEdges(v).map(e=>{return{pos:southPos[e.w],weight:g.edge(e).weight}}).sort((a,b)=>a.pos-b.pos)}); -// Build the accumulator tree -let firstIndex=1;while(firstIndex{let index=entry.pos+firstIndex;tree[index]+=entry.weight;let weightSum=0;while(index>0){if(index%2){weightSum+=tree[index+1]}index=index-1>>1;tree[index]+=entry.weight}cc+=entry.weight*weightSum});return cc}},{"../util":27}],15:[function(require,module,exports){"use strict";let initOrder=require("./init-order");let crossCount=require("./cross-count");let sortSubgraph=require("./sort-subgraph");let buildLayerGraph=require("./build-layer-graph");let addSubgraphConstraints=require("./add-subgraph-constraints");let Graph=require("@dagrejs/graphlib").Graph;let util=require("../util");module.exports=order; -/* - * Applies heuristics to minimize edge crossings in the graph and sets the best - * order solution as an order attribute on each node. - * - * Pre-conditions: - * - * 1. Graph must be DAG - * 2. Graph nodes must be objects with a "rank" attribute - * 3. Graph edges must have the "weight" attribute - * - * Post-conditions: - * - * 1. Graph nodes will have an "order" attribute based on the results of the - * algorithm. - */function order(g,opts){if(opts&&typeof opts.customOrder==="function"){opts.customOrder(g,order);return}let maxRank=util.maxRank(g),downLayerGraphs=buildLayerGraphs(g,util.range(1,maxRank+1),"inEdges"),upLayerGraphs=buildLayerGraphs(g,util.range(maxRank-1,-1,-1),"outEdges");let layering=initOrder(g);assignOrder(g,layering);if(opts&&opts.disableOptimalOrderHeuristic){return}let bestCC=Number.POSITIVE_INFINITY,best;for(let i=0,lastBest=0;lastBest<4;++i,++lastBest){sweepLayerGraphs(i%2?downLayerGraphs:upLayerGraphs,i%4>=2);layering=util.buildLayerMatrix(g);let cc=crossCount(g,layering);if(cclg.node(v).order=i);addSubgraphConstraints(lg,cg,sorted.vs)})}function assignOrder(g,layering){Object.values(layering).forEach(layer=>layer.forEach((v,i)=>g.node(v).order=i))}},{"../util":27,"./add-subgraph-constraints":11,"./build-layer-graph":13,"./cross-count":14,"./init-order":16,"./sort-subgraph":18,"@dagrejs/graphlib":29}],16:[function(require,module,exports){"use strict";let util=require("../util");module.exports=initOrder; -/* - * Assigns an initial order value for each node by performing a DFS search - * starting from nodes in the first rank. Nodes are assigned an order in their - * rank as they are first visited. - * - * This approach comes from Gansner, et al., "A Technique for Drawing Directed - * Graphs." - * - * Returns a layering matrix with an array per layer and each layer sorted by - * the order of its nodes. - */function initOrder(g){let visited={};let simpleNodes=g.nodes().filter(v=>!g.children(v).length);let simpleNodesRanks=simpleNodes.map(v=>g.node(v).rank);let maxRank=util.applyWithChunking(Math.max,simpleNodesRanks);let layers=util.range(maxRank+1).map(()=>[]);function dfs(v){if(visited[v])return;visited[v]=true;let node=g.node(v);layers[node.rank].push(v);g.successors(v).forEach(dfs)}let orderedVs=simpleNodes.sort((a,b)=>g.node(a).rank-g.node(b).rank);orderedVs.forEach(dfs);return layers}},{"../util":27}],17:[function(require,module,exports){"use strict";let util=require("../util");module.exports=resolveConflicts; -/* - * Given a list of entries of the form {v, barycenter, weight} and a - * constraint graph this function will resolve any conflicts between the - * constraint graph and the barycenters for the entries. If the barycenters for - * an entry would violate a constraint in the constraint graph then we coalesce - * the nodes in the conflict into a new node that respects the contraint and - * aggregates barycenter and weight information. - * - * This implementation is based on the description in Forster, "A Fast and - * Simple Hueristic for Constrained Two-Level Crossing Reduction," thought it - * differs in some specific details. - * - * Pre-conditions: - * - * 1. Each entry has the form {v, barycenter, weight}, or if the node has - * no barycenter, then {v}. - * - * Returns: - * - * A new list of entries of the form {vs, i, barycenter, weight}. The list - * `vs` may either be a singleton or it may be an aggregation of nodes - * ordered such that they do not violate constraints from the constraint - * graph. The property `i` is the lowest original index of any of the - * elements in `vs`. - */function resolveConflicts(entries,cg){let mappedEntries={};entries.forEach((entry,i)=>{let tmp=mappedEntries[entry.v]={indegree:0,in:[],out:[],vs:[entry.v],i:i};if(entry.barycenter!==undefined){tmp.barycenter=entry.barycenter;tmp.weight=entry.weight}});cg.edges().forEach(e=>{let entryV=mappedEntries[e.v];let entryW=mappedEntries[e.w];if(entryV!==undefined&&entryW!==undefined){entryW.indegree++;entryV.out.push(mappedEntries[e.w])}});let sourceSet=Object.values(mappedEntries).filter(entry=>!entry.indegree);return doResolveConflicts(sourceSet)}function doResolveConflicts(sourceSet){let entries=[];function handleIn(vEntry){return uEntry=>{if(uEntry.merged){return}if(uEntry.barycenter===undefined||vEntry.barycenter===undefined||uEntry.barycenter>=vEntry.barycenter){mergeEntries(vEntry,uEntry)}}}function handleOut(vEntry){return wEntry=>{wEntry["in"].push(vEntry);if(--wEntry.indegree===0){sourceSet.push(wEntry)}}}while(sourceSet.length){let entry=sourceSet.pop();entries.push(entry);entry["in"].reverse().forEach(handleIn(entry));entry.out.forEach(handleOut(entry))}return entries.filter(entry=>!entry.merged).map(entry=>{return util.pick(entry,["vs","i","barycenter","weight"])})}function mergeEntries(target,source){let sum=0;let weight=0;if(target.weight){sum+=target.barycenter*target.weight;weight+=target.weight}if(source.weight){sum+=source.barycenter*source.weight;weight+=source.weight}target.vs=source.vs.concat(target.vs);target.barycenter=sum/weight;target.weight=weight;target.i=Math.min(source.i,target.i);source.merged=true}},{"../util":27}],18:[function(require,module,exports){let barycenter=require("./barycenter");let resolveConflicts=require("./resolve-conflicts");let sort=require("./sort");module.exports=sortSubgraph;function sortSubgraph(g,v,cg,biasRight){let movable=g.children(v);let node=g.node(v);let bl=node?node.borderLeft:undefined;let br=node?node.borderRight:undefined;let subgraphs={};if(bl){movable=movable.filter(w=>w!==bl&&w!==br)}let barycenters=barycenter(g,movable);barycenters.forEach(entry=>{if(g.children(entry.v).length){let subgraphResult=sortSubgraph(g,entry.v,cg,biasRight);subgraphs[entry.v]=subgraphResult;if(Object.hasOwn(subgraphResult,"barycenter")){mergeBarycenters(entry,subgraphResult)}}});let entries=resolveConflicts(barycenters,cg);expandSubgraphs(entries,subgraphs);let result=sort(entries,biasRight);if(bl){result.vs=[bl,result.vs,br].flat(true);if(g.predecessors(bl).length){let blPred=g.node(g.predecessors(bl)[0]),brPred=g.node(g.predecessors(br)[0]);if(!Object.hasOwn(result,"barycenter")){result.barycenter=0;result.weight=0}result.barycenter=(result.barycenter*result.weight+blPred.order+brPred.order)/(result.weight+2);result.weight+=2}}return result}function expandSubgraphs(entries,subgraphs){entries.forEach(entry=>{entry.vs=entry.vs.flatMap(v=>{if(subgraphs[v]){return subgraphs[v].vs}return v})})}function mergeBarycenters(target,other){if(target.barycenter!==undefined){target.barycenter=(target.barycenter*target.weight+other.barycenter*other.weight)/(target.weight+other.weight);target.weight+=other.weight}else{target.barycenter=other.barycenter;target.weight=other.weight}}},{"./barycenter":12,"./resolve-conflicts":17,"./sort":19}],19:[function(require,module,exports){let util=require("../util");module.exports=sort;function sort(entries,biasRight){let parts=util.partition(entries,entry=>{return Object.hasOwn(entry,"barycenter")});let sortable=parts.lhs,unsortable=parts.rhs.sort((a,b)=>b.i-a.i),vs=[],sum=0,weight=0,vsIndex=0;sortable.sort(compareWithBias(!!biasRight));vsIndex=consumeUnsortable(vs,unsortable,vsIndex);sortable.forEach(entry=>{vsIndex+=entry.vs.length;vs.push(entry.vs);sum+=entry.barycenter*entry.weight;weight+=entry.weight;vsIndex=consumeUnsortable(vs,unsortable,vsIndex)});let result={vs:vs.flat(true)};if(weight){result.barycenter=sum/weight;result.weight=weight}return result}function consumeUnsortable(vs,unsortable,index){let last;while(unsortable.length&&(last=unsortable[unsortable.length-1]).i<=index){unsortable.pop();vs.push(last.vs);index++}return index}function compareWithBias(bias){return(entryV,entryW)=>{if(entryV.barycenterentryW.barycenter){return 1}return!bias?entryV.i-entryW.i:entryW.i-entryV.i}}},{"../util":27}],20:[function(require,module,exports){module.exports=parentDummyChains;function parentDummyChains(g){let postorderNums=postorder(g);g.graph().dummyChains.forEach(v=>{let node=g.node(v);let edgeObj=node.edgeObj;let pathData=findPath(g,postorderNums,edgeObj.v,edgeObj.w);let path=pathData.path;let lca=pathData.lca;let pathIdx=0;let pathV=path[pathIdx];let ascending=true;while(v!==edgeObj.w){node=g.node(v);if(ascending){while((pathV=path[pathIdx])!==lca&&g.node(pathV).maxRanklow||lim>postorderNums[parent].lim));lca=parent; -// Traverse from w to LCA -parent=w;while((parent=g.parent(parent))!==lca){wPath.push(parent)}return{path:vPath.concat(wPath.reverse()),lca:lca}}function postorder(g){let result={};let lim=0;function dfs(v){let low=lim;g.children(v).forEach(dfs);result[v]={low:low,lim:lim++}}g.children().forEach(dfs);return result}},{}],21:[function(require,module,exports){"use strict";let Graph=require("@dagrejs/graphlib").Graph;let util=require("../util"); -/* - * This module provides coordinate assignment based on Brandes and Köpf, "Fast - * and Simple Horizontal Coordinate Assignment." - */module.exports={positionX:positionX,findType1Conflicts:findType1Conflicts,findType2Conflicts:findType2Conflicts,addConflict:addConflict,hasConflict:hasConflict,verticalAlignment:verticalAlignment,horizontalCompaction:horizontalCompaction,alignCoordinates:alignCoordinates,findSmallestWidthAlignment:findSmallestWidthAlignment,balance:balance}; -/* - * Marks all edges in the graph with a type-1 conflict with the "type1Conflict" - * property. A type-1 conflict is one where a non-inner segment crosses an - * inner segment. An inner segment is an edge with both incident nodes marked - * with the "dummy" property. - * - * This algorithm scans layer by layer, starting with the second, for type-1 - * conflicts between the current layer and the previous layer. For each layer - * it scans the nodes from left to right until it reaches one that is incident - * on an inner segment. It then scans predecessors to determine if they have - * edges that cross that inner segment. At the end a final scan is done for all - * nodes on the current rank to see if they cross the last visited inner - * segment. - * - * This algorithm (safely) assumes that a dummy node will only be incident on a - * single node in the layers being scanned. - */function findType1Conflicts(g,layering){let conflicts={};function visitLayer(prevLayer,layer){let -// last visited node in the previous layer that is incident on an inner -// segment. -k0=0, -// Tracks the last node in this layer scanned for crossings with a type-1 -// segment. -scanPos=0,prevLayerLength=prevLayer.length,lastNode=layer[layer.length-1];layer.forEach((v,i)=>{let w=findOtherInnerSegmentNode(g,v),k1=w?g.node(w).order:prevLayerLength;if(w||v===lastNode){layer.slice(scanPos,i+1).forEach(scanNode=>{g.predecessors(scanNode).forEach(u=>{let uLabel=g.node(u),uPos=uLabel.order;if((uPos{v=south[i];if(g.node(v).dummy){g.predecessors(v).forEach(u=>{let uNode=g.node(u);if(uNode.dummy&&(uNode.ordernextNorthBorder)){addConflict(conflicts,u,v)}})}})}function visitLayer(north,south){let prevNorthPos=-1,nextNorthPos,southPos=0;south.forEach((v,southLookahead)=>{if(g.node(v).dummy==="border"){let predecessors=g.predecessors(v);if(predecessors.length){nextNorthPos=g.node(predecessors[0]).order;scan(south,southPos,southLookahead,prevNorthPos,nextNorthPos);southPos=southLookahead;prevNorthPos=nextNorthPos}}scan(south,southPos,south.length,nextNorthPos,north.length)});return south}layering.length&&layering.reduce(visitLayer);return conflicts}function findOtherInnerSegmentNode(g,v){if(g.node(v).dummy){return g.predecessors(v).find(u=>g.node(u).dummy)}}function addConflict(conflicts,v,w){if(v>w){let tmp=v;v=w;w=tmp}let conflictsV=conflicts[v];if(!conflictsV){conflicts[v]=conflictsV={}}conflictsV[w]=true}function hasConflict(conflicts,v,w){if(v>w){let tmp=v;v=w;w=tmp}return!!conflicts[v]&&Object.hasOwn(conflicts[v],w)} -/* - * Try to align nodes into vertical "blocks" where possible. This algorithm - * attempts to align a node with one of its median neighbors. If the edge - * connecting a neighbor is a type-1 conflict then we ignore that possibility. - * If a previous node has already formed a block with a node after the node - * we're trying to form a block with, we also ignore that possibility - our - * blocks would be split in that scenario. - */function verticalAlignment(g,layering,conflicts,neighborFn){let root={},align={},pos={}; -// We cache the position here based on the layering because the graph and -// layering may be out of sync. The layering matrix is manipulated to -// generate different extreme alignments. -layering.forEach(layer=>{layer.forEach((v,order)=>{root[v]=v;align[v]=v;pos[v]=order})});layering.forEach(layer=>{let prevIdx=-1;layer.forEach(v=>{let ws=neighborFn(v);if(ws.length){ws=ws.sort((a,b)=>pos[a]-pos[b]);let mp=(ws.length-1)/2;for(let i=Math.floor(mp),il=Math.ceil(mp);i<=il;++i){let w=ws[i];if(align[v]===v&&prevIdx{return Math.max(acc,xs[e.v]+blockG.edge(e))},0)} -// Second pass, assign greatest coordinates -function pass2(elem){let min=blockG.outEdges(elem).reduce((acc,e)=>{return Math.min(acc,xs[e.w]-blockG.edge(e))},Number.POSITIVE_INFINITY);let node=g.node(elem);if(min!==Number.POSITIVE_INFINITY&&node.borderType!==borderType){xs[elem]=Math.max(xs[elem],min)}}iterate(pass1,blockG.predecessors.bind(blockG));iterate(pass2,blockG.successors.bind(blockG)); -// Assign x coordinates to all nodes -Object.keys(align).forEach(v=>xs[v]=xs[root[v]]);return xs}function buildBlockGraph(g,layering,root,reverseSep){let blockGraph=new Graph,graphLabel=g.graph(),sepFn=sep(graphLabel.nodesep,graphLabel.edgesep,reverseSep);layering.forEach(layer=>{let u;layer.forEach(v=>{let vRoot=root[v];blockGraph.setNode(vRoot);if(u){var uRoot=root[u],prevMax=blockGraph.edge(uRoot,vRoot);blockGraph.setEdge(uRoot,vRoot,Math.max(sepFn(g,v,u),prevMax||0))}u=v})});return blockGraph} -/* - * Returns the alignment that has the smallest width of the given alignments. - */function findSmallestWidthAlignment(g,xss){return Object.values(xss).reduce((currentMinAndXs,xs)=>{let max=Number.NEGATIVE_INFINITY;let min=Number.POSITIVE_INFINITY;Object.entries(xs).forEach(([v,x])=>{let halfWidth=width(g,v)/2;max=Math.max(x+halfWidth,max);min=Math.min(x-halfWidth,min)});const newMin=max-min;if(newMin{["l","r"].forEach(horiz=>{let alignment=vert+horiz,xs=xss[alignment];if(xs===alignTo)return;let xsVals=Object.values(xs);let delta=alignToMin-util.applyWithChunking(Math.min,xsVals);if(horiz!=="l"){delta=alignToMax-util.applyWithChunking(Math.max,xsVals)}if(delta){xss[alignment]=util.mapValues(xs,x=>x+delta)}})})}function balance(xss,align){return util.mapValues(xss.ul,(num,v)=>{if(align){return xss[align.toLowerCase()][v]}else{let xs=Object.values(xss).map(xs=>xs[v]).sort((a,b)=>a-b);return(xs[1]+xs[2])/2}})}function positionX(g){let layering=util.buildLayerMatrix(g);let conflicts=Object.assign(findType1Conflicts(g,layering),findType2Conflicts(g,layering));let xss={};let adjustedLayering;["u","d"].forEach(vert=>{adjustedLayering=vert==="u"?layering:Object.values(layering).reverse();["l","r"].forEach(horiz=>{if(horiz==="r"){adjustedLayering=adjustedLayering.map(inner=>{return Object.values(inner).reverse()})}let neighborFn=(vert==="u"?g.predecessors:g.successors).bind(g);let align=verticalAlignment(g,adjustedLayering,conflicts,neighborFn);let xs=horizontalCompaction(g,adjustedLayering,align.root,align.align,horiz==="r");if(horiz==="r"){xs=util.mapValues(xs,x=>-x)}xss[vert+horiz]=xs})});let smallestWidth=findSmallestWidthAlignment(g,xss);alignCoordinates(xss,smallestWidth);return balance(xss,g.graph().align)}function sep(nodeSep,edgeSep,reverseSep){return(g,v,w)=>{let vLabel=g.node(v);let wLabel=g.node(w);let sum=0;let delta;sum+=vLabel.width/2;if(Object.hasOwn(vLabel,"labelpos")){switch(vLabel.labelpos.toLowerCase()){case"l":delta=-vLabel.width/2;break;case"r":delta=vLabel.width/2;break}}if(delta){sum+=reverseSep?delta:-delta}delta=0;sum+=(vLabel.dummy?edgeSep:nodeSep)/2;sum+=(wLabel.dummy?edgeSep:nodeSep)/2;sum+=wLabel.width/2;if(Object.hasOwn(wLabel,"labelpos")){switch(wLabel.labelpos.toLowerCase()){case"l":delta=wLabel.width/2;break;case"r":delta=-wLabel.width/2;break}}if(delta){sum+=reverseSep?delta:-delta}delta=0;return sum}}function width(g,v){return g.node(v).width}},{"../util":27,"@dagrejs/graphlib":29}],22:[function(require,module,exports){"use strict";let util=require("../util");let positionX=require("./bk").positionX;module.exports=position;function position(g){g=util.asNonCompoundGraph(g);positionY(g);Object.entries(positionX(g)).forEach(([v,x])=>g.node(v).x=x)}function positionY(g){let layering=util.buildLayerMatrix(g);let rankSep=g.graph().ranksep;let prevY=0;layering.forEach(layer=>{const maxHeight=layer.reduce((acc,v)=>{const height=g.node(v).height;if(acc>height){return acc}else{return height}},0);layer.forEach(v=>g.node(v).y=prevY+maxHeight/2);prevY+=maxHeight+rankSep})}},{"../util":27,"./bk":21}],23:[function(require,module,exports){"use strict";var Graph=require("@dagrejs/graphlib").Graph;var slack=require("./util").slack;module.exports=feasibleTree; -/* - * Constructs a spanning tree with tight edges and adjusted the input node's - * ranks to achieve this. A tight edge is one that is has a length that matches - * its "minlen" attribute. - * - * The basic structure for this function is derived from Gansner, et al., "A - * Technique for Drawing Directed Graphs." - * - * Pre-conditions: - * - * 1. Graph must be a DAG. - * 2. Graph must be connected. - * 3. Graph must have at least one node. - * 5. Graph nodes must have been previously assigned a "rank" property that - * respects the "minlen" property of incident edges. - * 6. Graph edges must have a "minlen" property. - * - * Post-conditions: - * - * - Graph nodes will have their rank adjusted to ensure that all edges are - * tight. - * - * Returns a tree (undirected graph) that is constructed using only "tight" - * edges. - */function feasibleTree(g){var t=new Graph({directed:false}); -// Choose arbitrary node from which to start our tree -var start=g.nodes()[0];var size=g.nodeCount();t.setNode(start,{});var edge,delta;while(tightTree(t,g){var edgeV=e.v,w=v===edgeV?e.w:edgeV;if(!t.hasNode(w)&&!slack(g,e)){t.setNode(w,{});t.setEdge(v,w,{});dfs(w)}})}t.nodes().forEach(dfs);return t.nodeCount()} -/* - * Finds the edge with the smallest slack that is incident on tree and returns - * it. - */function findMinSlackEdge(t,g){const edges=g.edges();return edges.reduce((acc,edge)=>{let edgeSlack=Number.POSITIVE_INFINITY;if(t.hasNode(edge.v)!==t.hasNode(edge.w)){edgeSlack=slack(g,edge)}if(edgeSlackg.node(v).rank+=delta)}},{"./util":26,"@dagrejs/graphlib":29}],24:[function(require,module,exports){"use strict";var rankUtil=require("./util");var longestPath=rankUtil.longestPath;var feasibleTree=require("./feasible-tree");var networkSimplex=require("./network-simplex");module.exports=rank; -/* - * Assigns a rank to each node in the input graph that respects the "minlen" - * constraint specified on edges between nodes. - * - * This basic structure is derived from Gansner, et al., "A Technique for - * Drawing Directed Graphs." - * - * Pre-conditions: - * - * 1. Graph must be a connected DAG - * 2. Graph nodes must be objects - * 3. Graph edges must have "weight" and "minlen" attributes - * - * Post-conditions: - * - * 1. Graph nodes will have a "rank" attribute based on the results of the - * algorithm. Ranks can start at any index (including negative), we'll - * fix them up later. - */function rank(g){switch(g.graph().ranker){case"network-simplex":networkSimplexRanker(g);break;case"tight-tree":tightTreeRanker(g);break;case"longest-path":longestPathRanker(g);break;default:networkSimplexRanker(g)}} -// A fast and simple ranker, but results are far from optimal. -var longestPathRanker=longestPath;function tightTreeRanker(g){longestPath(g);feasibleTree(g)}function networkSimplexRanker(g){networkSimplex(g)}},{"./feasible-tree":23,"./network-simplex":25,"./util":26}],25:[function(require,module,exports){"use strict";var feasibleTree=require("./feasible-tree");var slack=require("./util").slack;var initRank=require("./util").longestPath;var preorder=require("@dagrejs/graphlib").alg.preorder;var postorder=require("@dagrejs/graphlib").alg.postorder;var simplify=require("../util").simplify;module.exports=networkSimplex; -// Expose some internals for testing purposes -networkSimplex.initLowLimValues=initLowLimValues;networkSimplex.initCutValues=initCutValues;networkSimplex.calcCutValue=calcCutValue;networkSimplex.leaveEdge=leaveEdge;networkSimplex.enterEdge=enterEdge;networkSimplex.exchangeEdges=exchangeEdges; -/* - * The network simplex algorithm assigns ranks to each node in the input graph - * and iteratively improves the ranking to reduce the length of edges. - * - * Preconditions: - * - * 1. The input graph must be a DAG. - * 2. All nodes in the graph must have an object value. - * 3. All edges in the graph must have "minlen" and "weight" attributes. - * - * Postconditions: - * - * 1. All nodes in the graph will have an assigned "rank" attribute that has - * been optimized by the network simplex algorithm. Ranks start at 0. - * - * - * A rough sketch of the algorithm is as follows: - * - * 1. Assign initial ranks to each node. We use the longest path algorithm, - * which assigns ranks to the lowest position possible. In general this - * leads to very wide bottom ranks and unnecessarily long edges. - * 2. Construct a feasible tight tree. A tight tree is one such that all - * edges in the tree have no slack (difference between length of edge - * and minlen for the edge). This by itself greatly improves the assigned - * rankings by shorting edges. - * 3. Iteratively find edges that have negative cut values. Generally a - * negative cut value indicates that the edge could be removed and a new - * tree edge could be added to produce a more compact graph. - * - * Much of the algorithms here are derived from Gansner, et al., "A Technique - * for Drawing Directed Graphs." The structure of the file roughly follows the - * structure of the overall algorithm. - */function networkSimplex(g){g=simplify(g);initRank(g);var t=feasibleTree(g);initLowLimValues(t);initCutValues(t,g);var e,f;while(e=leaveEdge(t)){f=enterEdge(t,g,e);exchangeEdges(t,g,e,f)}} -/* - * Initializes cut values for all edges in the tree. - */function initCutValues(t,g){var vs=postorder(t,t.nodes());vs=vs.slice(0,vs.length-1);vs.forEach(v=>assignCutValue(t,g,v))}function assignCutValue(t,g,child){var childLab=t.node(child);var parent=childLab.parent;t.edge(child,parent).cutvalue=calcCutValue(t,g,child)} -/* - * Given the tight tree, its graph, and a child in the graph calculate and - * return the cut value for the edge between the child and its parent. - */function calcCutValue(t,g,child){var childLab=t.node(child);var parent=childLab.parent; -// True if the child is on the tail end of the edge in the directed graph -var childIsTail=true; -// The graph's view of the tree edge we're inspecting -var graphEdge=g.edge(child,parent); -// The accumulated cut value for the edge between this node and its parent -var cutValue=0;if(!graphEdge){childIsTail=false;graphEdge=g.edge(parent,child)}cutValue=graphEdge.weight;g.nodeEdges(child).forEach(e=>{var isOutEdge=e.v===child,other=isOutEdge?e.w:e.v;if(other!==parent){var pointsToHead=isOutEdge===childIsTail,otherWeight=g.edge(e).weight;cutValue+=pointsToHead?otherWeight:-otherWeight;if(isTreeEdge(t,child,other)){var otherCutValue=t.edge(child,other).cutvalue;cutValue+=pointsToHead?-otherCutValue:otherCutValue}}});return cutValue}function initLowLimValues(tree,root){if(arguments.length<2){root=tree.nodes()[0]}dfsAssignLowLim(tree,{},1,root)}function dfsAssignLowLim(tree,visited,nextLim,v,parent){var low=nextLim;var label=tree.node(v);visited[v]=true;tree.neighbors(v).forEach(w=>{if(!Object.hasOwn(visited,w)){nextLim=dfsAssignLowLim(tree,visited,nextLim,w,v)}});label.low=low;label.lim=nextLim++;if(parent){label.parent=parent}else{ -// TODO should be able to remove this when we incrementally update low lim -delete label.parent}return nextLim}function leaveEdge(tree){return tree.edges().find(e=>tree.edge(e).cutvalue<0)}function enterEdge(t,g,edge){var v=edge.v;var w=edge.w; -// For the rest of this function we assume that v is the tail and w is the -// head, so if we don't have this edge in the graph we should flip it to -// match the correct orientation. -if(!g.hasEdge(v,w)){v=edge.w;w=edge.v}var vLabel=t.node(v);var wLabel=t.node(w);var tailLabel=vLabel;var flip=false; -// If the root is in the tail of the edge then we need to flip the logic that -// checks for the head and tail nodes in the candidates function below. -if(vLabel.lim>wLabel.lim){tailLabel=wLabel;flip=true}var candidates=g.edges().filter(edge=>{return flip===isDescendant(t,t.node(edge.v),tailLabel)&&flip!==isDescendant(t,t.node(edge.w),tailLabel)});return candidates.reduce((acc,edge)=>{if(slack(g,edge)!g.node(v).parent);var vs=preorder(t,root);vs=vs.slice(1);vs.forEach(v=>{var parent=t.node(v).parent,edge=g.edge(v,parent),flipped=false;if(!edge){edge=g.edge(parent,v);flipped=true}g.node(v).rank=g.node(parent).rank+(flipped?edge.minlen:-edge.minlen)})} -/* - * Returns true if the edge is in the tree. - */function isTreeEdge(tree,u,v){return tree.hasEdge(u,v)} -/* - * Returns true if the specified node is descendant of the root node per the - * assigned low and lim attributes in the tree. - */function isDescendant(tree,vLabel,rootLabel){return rootLabel.low<=vLabel.lim&&vLabel.lim<=rootLabel.lim}},{"../util":27,"./feasible-tree":23,"./util":26,"@dagrejs/graphlib":29}],26:[function(require,module,exports){"use strict";const{applyWithChunking}=require("../util");module.exports={longestPath:longestPath,slack:slack}; -/* - * Initializes ranks for the input graph using the longest path algorithm. This - * algorithm scales well and is fast in practice, it yields rather poor - * solutions. Nodes are pushed to the lowest layer possible, leaving the bottom - * ranks wide and leaving edges longer than necessary. However, due to its - * speed, this algorithm is good for getting an initial ranking that can be fed - * into other algorithms. - * - * This algorithm does not normalize layers because it will be used by other - * algorithms in most cases. If using this algorithm directly, be sure to - * run normalize at the end. - * - * Pre-conditions: - * - * 1. Input graph is a DAG. - * 2. Input graph node labels can be assigned properties. - * - * Post-conditions: - * - * 1. Each node will be assign an (unnormalized) "rank" property. - */function longestPath(g){var visited={};function dfs(v){var label=g.node(v);if(Object.hasOwn(visited,v)){return label.rank}visited[v]=true;let outEdgesMinLens=g.outEdges(v).map(e=>{if(e==null){return Number.POSITIVE_INFINITY}return dfs(e.w)-g.edge(e).minlen});var rank=applyWithChunking(Math.min,outEdgesMinLens);if(rank===Number.POSITIVE_INFINITY){rank=0}return label.rank=rank}g.sources().forEach(dfs)} -/* - * Returns the amount of slack for the given edge. The slack is defined as the - * difference between the length of the edge and its minimum length. - */function slack(g,e){return g.node(e.w).rank-g.node(e.v).rank-g.edge(e).minlen}},{"../util":27}],27:[function(require,module,exports){ -/* eslint "no-console": off */ -"use strict";let Graph=require("@dagrejs/graphlib").Graph;module.exports={addBorderNode:addBorderNode,addDummyNode:addDummyNode,applyWithChunking:applyWithChunking,asNonCompoundGraph:asNonCompoundGraph,buildLayerMatrix:buildLayerMatrix,intersectRect:intersectRect,mapValues:mapValues,maxRank:maxRank,normalizeRanks:normalizeRanks,notime:notime,partition:partition,pick:pick,predecessorWeights:predecessorWeights,range:range,removeEmptyRanks:removeEmptyRanks,simplify:simplify,successorWeights:successorWeights,time:time,uniqueId:uniqueId,zipObject:zipObject}; -/* - * Adds a dummy node to the graph and return v. - */function addDummyNode(g,type,attrs,name){let v;do{v=uniqueId(name)}while(g.hasNode(v));attrs.dummy=type;g.setNode(v,attrs);return v} -/* - * Returns a new graph with only simple edges. Handles aggregation of data - * associated with multi-edges. - */function simplify(g){let simplified=(new Graph).setGraph(g.graph());g.nodes().forEach(v=>simplified.setNode(v,g.node(v)));g.edges().forEach(e=>{let simpleLabel=simplified.edge(e.v,e.w)||{weight:0,minlen:1};let label=g.edge(e);simplified.setEdge(e.v,e.w,{weight:simpleLabel.weight+label.weight,minlen:Math.max(simpleLabel.minlen,label.minlen)})});return simplified}function asNonCompoundGraph(g){let simplified=new Graph({multigraph:g.isMultigraph()}).setGraph(g.graph());g.nodes().forEach(v=>{if(!g.children(v).length){simplified.setNode(v,g.node(v))}});g.edges().forEach(e=>{simplified.setEdge(e,g.edge(e))});return simplified}function successorWeights(g){let weightMap=g.nodes().map(v=>{let sucs={};g.outEdges(v).forEach(e=>{sucs[e.w]=(sucs[e.w]||0)+g.edge(e).weight});return sucs});return zipObject(g.nodes(),weightMap)}function predecessorWeights(g){let weightMap=g.nodes().map(v=>{let preds={};g.inEdges(v).forEach(e=>{preds[e.v]=(preds[e.v]||0)+g.edge(e).weight});return preds});return zipObject(g.nodes(),weightMap)} -/* - * Finds where a line starting at point ({x, y}) would intersect a rectangle - * ({x, y, width, height}) if it were pointing at the rectangle's center. - */function intersectRect(rect,point){let x=rect.x;let y=rect.y; -// Rectangle intersection algorithm from: -// http://math.stackexchange.com/questions/108113/find-edge-between-two-boxes -let dx=point.x-x;let dy=point.y-y;let w=rect.width/2;let h=rect.height/2;if(!dx&&!dy){throw new Error("Not possible to find intersection inside of the rectangle")}let sx,sy;if(Math.abs(dy)*w>Math.abs(dx)*h){ -// Intersection is top or bottom of rect. -if(dy<0){h=-h}sx=h*dx/dy;sy=h}else{ -// Intersection is left or right of rect. -if(dx<0){w=-w}sx=w;sy=w*dy/dx}return{x:x+sx,y:y+sy}} -/* - * Given a DAG with each node assigned "rank" and "order" properties, this - * function will produce a matrix with the ids of each node. - */function buildLayerMatrix(g){let layering=range(maxRank(g)+1).map(()=>[]);g.nodes().forEach(v=>{let node=g.node(v);let rank=node.rank;if(rank!==undefined){layering[rank][node.order]=v}});return layering} -/* - * Adjusts the ranks for all nodes in the graph such that all nodes v have - * rank(v) >= 0 and at least one node w has rank(w) = 0. - */function normalizeRanks(g){let nodeRanks=g.nodes().map(v=>{let rank=g.node(v).rank;if(rank===undefined){return Number.MAX_VALUE}return rank});let min=applyWithChunking(Math.min,nodeRanks);g.nodes().forEach(v=>{let node=g.node(v);if(Object.hasOwn(node,"rank")){node.rank-=min}})}function removeEmptyRanks(g){ -// Ranks may not start at 0, so we need to offset them -let nodeRanks=g.nodes().map(v=>g.node(v).rank);let offset=applyWithChunking(Math.min,nodeRanks);let layers=[];g.nodes().forEach(v=>{let rank=g.node(v).rank-offset;if(!layers[rank]){layers[rank]=[]}layers[rank].push(v)});let delta=0;let nodeRankFactor=g.graph().nodeRankFactor;Array.from(layers).forEach((vs,i)=>{if(vs===undefined&&i%nodeRankFactor!==0){--delta}else if(vs!==undefined&&delta){vs.forEach(v=>g.node(v).rank+=delta)}})}function addBorderNode(g,prefix,rank,order){let node={width:0,height:0};if(arguments.length>=4){node.rank=rank;node.order=order}return addDummyNode(g,"border",node,prefix)}function splitToChunks(array,chunkSize=CHUNKING_THRESHOLD){const chunks=[];for(let i=0;iCHUNKING_THRESHOLD){const chunks=splitToChunks(argsArray);return fn.apply(null,chunks.map(chunk=>fn.apply(null,chunk)))}else{return fn.apply(null,argsArray)}}function maxRank(g){const nodes=g.nodes();const nodeRanks=nodes.map(v=>{let rank=g.node(v).rank;if(rank===undefined){return Number.MIN_VALUE}return rank});return applyWithChunking(Math.max,nodeRanks)} -/* - * Partition a collection into two groups: `lhs` and `rhs`. If the supplied - * function returns true for an entry it goes into `lhs`. Otherwise it goes - * into `rhs. - */function partition(collection,fn){let result={lhs:[],rhs:[]};collection.forEach(value=>{if(fn(value)){result.lhs.push(value)}else{result.rhs.push(value)}});return result} -/* - * Returns a new function that wraps `fn` with a timer. The wrapper logs the - * time it takes to execute the function. - */function time(name,fn){let start=Date.now();try{return fn()}finally{console.log(name+" time: "+(Date.now()-start)+"ms")}}function notime(name,fn){return fn()}let idCounter=0;function uniqueId(prefix){var id=++idCounter;return toString(prefix)+id}function range(start,limit,step=1){if(limit==null){limit=start;start=0}let endCon=i=>ilimitval[funcOrProp]}return Object.entries(obj).reduce((acc,[k,v])=>{acc[k]=func(v,k);return acc},{})}function zipObject(props,values){return props.reduce((acc,key,i)=>{acc[key]=values[i];return acc},{})}},{"@dagrejs/graphlib":29}],28:[function(require,module,exports){module.exports="1.1.4"},{}],29:[function(require,module,exports){ -/** - * Copyright (c) 2014, Chris Pettitt - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -var lib=require("./lib");module.exports={Graph:lib.Graph,json:require("./lib/json"),alg:require("./lib/alg"),version:lib.version}},{"./lib":45,"./lib/alg":36,"./lib/json":46}],30:[function(require,module,exports){module.exports=components;function components(g){var visited={};var cmpts=[];var cmpt;function dfs(v){if(Object.hasOwn(visited,v))return;visited[v]=true;cmpt.push(v);g.successors(v).forEach(dfs);g.predecessors(v).forEach(dfs)}g.nodes().forEach(function(v){cmpt=[];dfs(v);if(cmpt.length){cmpts.push(cmpt)}});return cmpts}},{}],31:[function(require,module,exports){module.exports=dfs; -/* - * A helper that preforms a pre- or post-order traversal on the input graph - * and returns the nodes in the order they were visited. If the graph is - * undirected then this algorithm will navigate using neighbors. If the graph - * is directed then this algorithm will navigate using successors. - * - * If the order is not "post", it will be treated as "pre". - */function dfs(g,vs,order){if(!Array.isArray(vs)){vs=[vs]}var navigation=g.isDirected()?v=>g.successors(v):v=>g.neighbors(v);var orderFunc=order==="post"?postOrderDfs:preOrderDfs;var acc=[];var visited={};vs.forEach(v=>{if(!g.hasNode(v)){throw new Error("Graph does not have node: "+v)}orderFunc(v,navigation,visited,acc)});return acc}function postOrderDfs(v,navigation,visited,acc){var stack=[[v,false]];while(stack.length>0){var curr=stack.pop();if(curr[1]){acc.push(curr[0])}else{if(!Object.hasOwn(visited,curr[0])){visited[curr[0]]=true;stack.push([curr[0],true]);forEachRight(navigation(curr[0]),w=>stack.push([w,false]))}}}}function preOrderDfs(v,navigation,visited,acc){var stack=[v];while(stack.length>0){var curr=stack.pop();if(!Object.hasOwn(visited,curr)){visited[curr]=true;acc.push(curr);forEachRight(navigation(curr),w=>stack.push(w))}}}function forEachRight(array,iteratee){var length=array.length;while(length--){iteratee(array[length],length,array)}return array}},{}],32:[function(require,module,exports){var dijkstra=require("./dijkstra");module.exports=dijkstraAll;function dijkstraAll(g,weightFunc,edgeFunc){return g.nodes().reduce(function(acc,v){acc[v]=dijkstra(g,v,weightFunc,edgeFunc);return acc},{})}},{"./dijkstra":33}],33:[function(require,module,exports){var PriorityQueue=require("../data/priority-queue");module.exports=dijkstra;var DEFAULT_WEIGHT_FUNC=()=>1;function dijkstra(g,source,weightFn,edgeFn){return runDijkstra(g,String(source),weightFn||DEFAULT_WEIGHT_FUNC,edgeFn||function(v){return g.outEdges(v)})}function runDijkstra(g,source,weightFn,edgeFn){var results={};var pq=new PriorityQueue;var v,vEntry;var updateNeighbors=function(edge){var w=edge.v!==v?edge.v:edge.w;var wEntry=results[w];var weight=weightFn(edge);var distance=vEntry.distance+weight;if(weight<0){throw new Error("dijkstra does not allow negative edge weights. "+"Bad edge: "+edge+" Weight: "+weight)}if(distance0){v=pq.removeMin();vEntry=results[v];if(vEntry.distance===Number.POSITIVE_INFINITY){break}edgeFn(v).forEach(updateNeighbors)}return results}},{"../data/priority-queue":43}],34:[function(require,module,exports){var tarjan=require("./tarjan");module.exports=findCycles;function findCycles(g){return tarjan(g).filter(function(cmpt){return cmpt.length>1||cmpt.length===1&&g.hasEdge(cmpt[0],cmpt[0])})}},{"./tarjan":41}],35:[function(require,module,exports){module.exports=floydWarshall;var DEFAULT_WEIGHT_FUNC=()=>1;function floydWarshall(g,weightFn,edgeFn){return runFloydWarshall(g,weightFn||DEFAULT_WEIGHT_FUNC,edgeFn||function(v){return g.outEdges(v)})}function runFloydWarshall(g,weightFn,edgeFn){var results={};var nodes=g.nodes();nodes.forEach(function(v){results[v]={};results[v][v]={distance:0};nodes.forEach(function(w){if(v!==w){results[v][w]={distance:Number.POSITIVE_INFINITY}}});edgeFn(v).forEach(function(edge){var w=edge.v===v?edge.w:edge.v;var d=weightFn(edge);results[v][w]={distance:d,predecessor:v}})});nodes.forEach(function(k){var rowK=results[k];nodes.forEach(function(i){var rowI=results[i];nodes.forEach(function(j){var ik=rowI[k];var kj=rowK[j];var ij=rowI[j];var altDistance=ik.distance+kj.distance;if(altDistance0){v=pq.removeMin();if(Object.hasOwn(parents,v)){result.setEdge(v,parents[v])}else if(init){throw new Error("Input graph is not connected: "+g)}else{init=true}g.nodeEdges(v).forEach(updateNeighbors)}return result}},{"../data/priority-queue":43,"../graph":44}],41:[function(require,module,exports){module.exports=tarjan;function tarjan(g){var index=0;var stack=[];var visited={};// node id -> { onStack, lowlink, index } -var results=[];function dfs(v){var entry=visited[v]={onStack:true,lowlink:index,index:index++};stack.push(v);g.successors(v).forEach(function(w){if(!Object.hasOwn(visited,w)){dfs(w);entry.lowlink=Math.min(entry.lowlink,visited[w].lowlink)}else if(visited[w].onStack){entry.lowlink=Math.min(entry.lowlink,visited[w].index)}});if(entry.lowlink===entry.index){var cmpt=[];var w;do{w=stack.pop();visited[w].onStack=false;cmpt.push(w)}while(v!==w);results.push(cmpt)}}g.nodes().forEach(function(v){if(!Object.hasOwn(visited,v)){dfs(v)}});return results}},{}],42:[function(require,module,exports){function topsort(g){var visited={};var stack={};var results=[];function visit(node){if(Object.hasOwn(stack,node)){throw new CycleException}if(!Object.hasOwn(visited,node)){stack[node]=true;visited[node]=true;g.predecessors(node).forEach(visit);delete stack[node];results.push(node)}}g.sinks().forEach(visit);if(Object.keys(visited).length!==g.nodeCount()){throw new CycleException}return results}class CycleException extends Error{constructor(){super(...arguments)}}module.exports=topsort;topsort.CycleException=CycleException},{}],43:[function(require,module,exports){ -/** - * A min-priority queue data structure. This algorithm is derived from Cormen, - * et al., "Introduction to Algorithms". The basic idea of a min-priority - * queue is that you can efficiently (in O(1) time) get the smallest key in - * the queue. Adding and removing elements takes O(log n) time. A key can - * have its priority decreased in O(log n) time. - */ -class PriorityQueue{_arr=[];_keyIndices={}; -/** - * Returns the number of elements in the queue. Takes `O(1)` time. - */size(){return this._arr.length} -/** - * Returns the keys that are in the queue. Takes `O(n)` time. - */keys(){return this._arr.map(function(x){return x.key})} -/** - * Returns `true` if **key** is in the queue and `false` if not. - */has(key){return Object.hasOwn(this._keyIndices,key)} -/** - * Returns the priority for **key**. If **key** is not present in the queue - * then this function returns `undefined`. Takes `O(1)` time. - * - * @param {Object} key - */priority(key){var index=this._keyIndices[key];if(index!==undefined){return this._arr[index].priority}} -/** - * Returns the key for the minimum element in this queue. If the queue is - * empty this function throws an Error. Takes `O(1)` time. - */min(){if(this.size()===0){throw new Error("Queue underflow")}return this._arr[0].key} -/** - * Inserts a new key into the priority queue. If the key already exists in - * the queue this function returns `false`; otherwise it will return `true`. - * Takes `O(n)` time. - * - * @param {Object} key the key to add - * @param {Number} priority the initial priority for the key - */add(key,priority){var keyIndices=this._keyIndices;key=String(key);if(!Object.hasOwn(keyIndices,key)){var arr=this._arr;var index=arr.length;keyIndices[key]=index;arr.push({key:key,priority:priority});this._decrease(index);return true}return false} -/** - * Removes and returns the smallest key in the queue. Takes `O(log n)` time. - */removeMin(){this._swap(0,this._arr.length-1);var min=this._arr.pop();delete this._keyIndices[min.key];this._heapify(0);return min.key} -/** - * Decreases the priority for **key** to **priority**. If the new priority is - * greater than the previous priority, this function will throw an Error. - * - * @param {Object} key the key for which to raise priority - * @param {Number} priority the new priority for the key - */decrease(key,priority){var index=this._keyIndices[key];if(priority>this._arr[index].priority){throw new Error("New priority is greater than current priority. "+"Key: "+key+" Old: "+this._arr[index].priority+" New: "+priority)}this._arr[index].priority=priority;this._decrease(index)}_heapify(i){var arr=this._arr;var l=2*i;var r=l+1;var largest=i;if(l>1;if(arr[parent].priorityundefined; -// Defaults to be set when creating a new edge -_defaultEdgeLabelFn=()=>undefined; -// v -> label -_nodes={}; -// v -> edgeObj -_in={}; -// u -> v -> Number -_preds={}; -// v -> edgeObj -_out={}; -// v -> w -> Number -_sucs={}; -// e -> edgeObj -_edgeObjs={}; -// e -> label -_edgeLabels={}; -/* Number of nodes in the graph. Should only be changed by the implementation. */_nodeCount=0; -/* Number of edges in the graph. Should only be changed by the implementation. */_edgeCount=0;_parent;_children;constructor(opts){if(opts){this._isDirected=Object.hasOwn(opts,"directed")?opts.directed:true;this._isMultigraph=Object.hasOwn(opts,"multigraph")?opts.multigraph:false;this._isCompound=Object.hasOwn(opts,"compound")?opts.compound:false}if(this._isCompound){ -// v -> parent -this._parent={}; -// v -> children -this._children={};this._children[GRAPH_NODE]={}}} -/* === Graph functions ========= */ -/** - * Whether graph was created with 'directed' flag set to true or not. - */isDirected(){return this._isDirected} -/** - * Whether graph was created with 'multigraph' flag set to true or not. - */isMultigraph(){return this._isMultigraph} -/** - * Whether graph was created with 'compound' flag set to true or not. - */isCompound(){return this._isCompound} -/** - * Sets the label of the graph. - */setGraph(label){this._label=label;return this} -/** - * Gets the graph label. - */graph(){return this._label} -/* === Node functions ========== */ -/** - * Sets the default node label. If newDefault is a function, it will be - * invoked ach time when setting a label for a node. Otherwise, this label - * will be assigned as default label in case if no label was specified while - * setting a node. - * Complexity: O(1). - */setDefaultNodeLabel(newDefault){this._defaultNodeLabelFn=newDefault;if(typeof newDefault!=="function"){this._defaultNodeLabelFn=()=>newDefault}return this} -/** - * Gets the number of nodes in the graph. - * Complexity: O(1). - */nodeCount(){return this._nodeCount} -/** - * Gets all nodes of the graph. Note, the in case of compound graph subnodes are - * not included in list. - * Complexity: O(1). - */nodes(){return Object.keys(this._nodes)} -/** - * Gets list of nodes without in-edges. - * Complexity: O(|V|). - */sources(){var self=this;return this.nodes().filter(v=>Object.keys(self._in[v]).length===0)} -/** - * Gets list of nodes without out-edges. - * Complexity: O(|V|). - */sinks(){var self=this;return this.nodes().filter(v=>Object.keys(self._out[v]).length===0)} -/** - * Invokes setNode method for each node in names list. - * Complexity: O(|names|). - */setNodes(vs,value){var args=arguments;var self=this;vs.forEach(function(v){if(args.length>1){self.setNode(v,value)}else{self.setNode(v)}});return this} -/** - * Creates or updates the value for the node v in the graph. If label is supplied - * it is set as the value for the node. If label is not supplied and the node was - * created by this call then the default node label will be assigned. - * Complexity: O(1). - */setNode(v,value){if(Object.hasOwn(this._nodes,v)){if(arguments.length>1){this._nodes[v]=value}return this}this._nodes[v]=arguments.length>1?value:this._defaultNodeLabelFn(v);if(this._isCompound){this._parent[v]=GRAPH_NODE;this._children[v]={};this._children[GRAPH_NODE][v]=true}this._in[v]={};this._preds[v]={};this._out[v]={};this._sucs[v]={};++this._nodeCount;return this} -/** - * Gets the label of node with specified name. - * Complexity: O(|V|). - */node(v){return this._nodes[v]} -/** - * Detects whether graph has a node with specified name or not. - */hasNode(v){return Object.hasOwn(this._nodes,v)} -/** - * Remove the node with the name from the graph or do nothing if the node is not in - * the graph. If the node was removed this function also removes any incident - * edges. - * Complexity: O(1). - */removeNode(v){var self=this;if(Object.hasOwn(this._nodes,v)){var removeEdge=e=>self.removeEdge(self._edgeObjs[e]);delete this._nodes[v];if(this._isCompound){this._removeFromParentsChildList(v);delete this._parent[v];this.children(v).forEach(function(child){self.setParent(child)});delete this._children[v]}Object.keys(this._in[v]).forEach(removeEdge);delete this._in[v];delete this._preds[v];Object.keys(this._out[v]).forEach(removeEdge);delete this._out[v];delete this._sucs[v];--this._nodeCount}return this} -/** - * Sets node p as a parent for node v if it is defined, or removes the - * parent for v if p is undefined. Method throws an exception in case of - * invoking it in context of noncompound graph. - * Average-case complexity: O(1). - */setParent(v,parent){if(!this._isCompound){throw new Error("Cannot set parent in a non-compound graph")}if(parent===undefined){parent=GRAPH_NODE}else{ -// Coerce parent to string -parent+="";for(var ancestor=parent;ancestor!==undefined;ancestor=this.parent(ancestor)){if(ancestor===v){throw new Error("Setting "+parent+" as parent of "+v+" would create a cycle")}}this.setNode(parent)}this.setNode(v);this._removeFromParentsChildList(v);this._parent[v]=parent;this._children[parent][v]=true;return this}_removeFromParentsChildList(v){delete this._children[this._parent[v]][v]} -/** - * Gets parent node for node v. - * Complexity: O(1). - */parent(v){if(this._isCompound){var parent=this._parent[v];if(parent!==GRAPH_NODE){return parent}}} -/** - * Gets list of direct children of node v. - * Complexity: O(1). - */children(v=GRAPH_NODE){if(this._isCompound){var children=this._children[v];if(children){return Object.keys(children)}}else if(v===GRAPH_NODE){return this.nodes()}else if(this.hasNode(v)){return[]}} -/** - * Return all nodes that are predecessors of the specified node or undefined if node v is not in - * the graph. Behavior is undefined for undirected graphs - use neighbors instead. - * Complexity: O(|V|). - */predecessors(v){var predsV=this._preds[v];if(predsV){return Object.keys(predsV)}} -/** - * Return all nodes that are successors of the specified node or undefined if node v is not in - * the graph. Behavior is undefined for undirected graphs - use neighbors instead. - * Complexity: O(|V|). - */successors(v){var sucsV=this._sucs[v];if(sucsV){return Object.keys(sucsV)}} -/** - * Return all nodes that are predecessors or successors of the specified node or undefined if - * node v is not in the graph. - * Complexity: O(|V|). - */neighbors(v){var preds=this.predecessors(v);if(preds){const union=new Set(preds);for(var succ of this.successors(v)){union.add(succ)}return Array.from(union.values())}}isLeaf(v){var neighbors;if(this.isDirected()){neighbors=this.successors(v)}else{neighbors=this.neighbors(v)}return neighbors.length===0} -/** - * Creates new graph with nodes filtered via filter. Edges incident to rejected node - * are also removed. In case of compound graph, if parent is rejected by filter, - * than all its children are rejected too. - * Average-case complexity: O(|E|+|V|). - */filterNodes(filter){var copy=new this.constructor({directed:this._isDirected,multigraph:this._isMultigraph,compound:this._isCompound});copy.setGraph(this.graph());var self=this;Object.entries(this._nodes).forEach(function([v,value]){if(filter(v)){copy.setNode(v,value)}});Object.values(this._edgeObjs).forEach(function(e){if(copy.hasNode(e.v)&©.hasNode(e.w)){copy.setEdge(e,self.edge(e))}});var parents={};function findParent(v){var parent=self.parent(v);if(parent===undefined||copy.hasNode(parent)){parents[v]=parent;return parent}else if(parent in parents){return parents[parent]}else{return findParent(parent)}}if(this._isCompound){copy.nodes().forEach(v=>copy.setParent(v,findParent(v)))}return copy} -/* === Edge functions ========== */ -/** - * Sets the default edge label or factory function. This label will be - * assigned as default label in case if no label was specified while setting - * an edge or this function will be invoked each time when setting an edge - * with no label specified and returned value * will be used as a label for edge. - * Complexity: O(1). - */setDefaultEdgeLabel(newDefault){this._defaultEdgeLabelFn=newDefault;if(typeof newDefault!=="function"){this._defaultEdgeLabelFn=()=>newDefault}return this} -/** - * Gets the number of edges in the graph. - * Complexity: O(1). - */edgeCount(){return this._edgeCount} -/** - * Gets edges of the graph. In case of compound graph subgraphs are not considered. - * Complexity: O(|E|). - */edges(){return Object.values(this._edgeObjs)} -/** - * Establish an edges path over the nodes in nodes list. If some edge is already - * exists, it will update its label, otherwise it will create an edge between pair - * of nodes with label provided or default label if no label provided. - * Complexity: O(|nodes|). - */setPath(vs,value){var self=this;var args=arguments;vs.reduce(function(v,w){if(args.length>1){self.setEdge(v,w,value)}else{self.setEdge(v,w)}return w});return this} -/** - * Creates or updates the label for the edge (v, w) with the optionally supplied - * name. If label is supplied it is set as the value for the edge. If label is not - * supplied and the edge was created by this call then the default edge label will - * be assigned. The name parameter is only useful with multigraphs. - */setEdge(){var v,w,name,value;var valueSpecified=false;var arg0=arguments[0];if(typeof arg0==="object"&&arg0!==null&&"v"in arg0){v=arg0.v;w=arg0.w;name=arg0.name;if(arguments.length===2){value=arguments[1];valueSpecified=true}}else{v=arg0;w=arguments[1];name=arguments[3];if(arguments.length>2){value=arguments[2];valueSpecified=true}}v=""+v;w=""+w;if(name!==undefined){name=""+name}var e=edgeArgsToId(this._isDirected,v,w,name);if(Object.hasOwn(this._edgeLabels,e)){if(valueSpecified){this._edgeLabels[e]=value}return this}if(name!==undefined&&!this._isMultigraph){throw new Error("Cannot set a named edge when isMultigraph = false")} -// It didn't exist, so we need to create it. -// First ensure the nodes exist. -this.setNode(v);this.setNode(w);this._edgeLabels[e]=valueSpecified?value:this._defaultEdgeLabelFn(v,w,name);var edgeObj=edgeArgsToObj(this._isDirected,v,w,name); -// Ensure we add undirected edges in a consistent way. -v=edgeObj.v;w=edgeObj.w;Object.freeze(edgeObj);this._edgeObjs[e]=edgeObj;incrementOrInitEntry(this._preds[w],v);incrementOrInitEntry(this._sucs[v],w);this._in[w][e]=edgeObj;this._out[v][e]=edgeObj;this._edgeCount++;return this} -/** - * Gets the label for the specified edge. - * Complexity: O(1). - */edge(v,w,name){var e=arguments.length===1?edgeObjToId(this._isDirected,arguments[0]):edgeArgsToId(this._isDirected,v,w,name);return this._edgeLabels[e]} -/** - * Gets the label for the specified edge and converts it to an object. - * Complexity: O(1) - */edgeAsObj(){const edge=this.edge(...arguments);if(typeof edge!=="object"){return{label:edge}}return edge} -/** - * Detects whether the graph contains specified edge or not. No subgraphs are considered. - * Complexity: O(1). - */hasEdge(v,w,name){var e=arguments.length===1?edgeObjToId(this._isDirected,arguments[0]):edgeArgsToId(this._isDirected,v,w,name);return Object.hasOwn(this._edgeLabels,e)} -/** - * Removes the specified edge from the graph. No subgraphs are considered. - * Complexity: O(1). - */removeEdge(v,w,name){var e=arguments.length===1?edgeObjToId(this._isDirected,arguments[0]):edgeArgsToId(this._isDirected,v,w,name);var edge=this._edgeObjs[e];if(edge){v=edge.v;w=edge.w;delete this._edgeLabels[e];delete this._edgeObjs[e];decrementOrRemoveEntry(this._preds[w],v);decrementOrRemoveEntry(this._sucs[v],w);delete this._in[w][e];delete this._out[v][e];this._edgeCount--}return this} -/** - * Return all edges that point to the node v. Optionally filters those edges down to just those - * coming from node u. Behavior is undefined for undirected graphs - use nodeEdges instead. - * Complexity: O(|E|). - */inEdges(v,u){var inV=this._in[v];if(inV){var edges=Object.values(inV);if(!u){return edges}return edges.filter(edge=>edge.v===u)}} -/** - * Return all edges that are pointed at by node v. Optionally filters those edges down to just - * those point to w. Behavior is undefined for undirected graphs - use nodeEdges instead. - * Complexity: O(|E|). - */outEdges(v,w){var outV=this._out[v];if(outV){var edges=Object.values(outV);if(!w){return edges}return edges.filter(edge=>edge.w===w)}} -/** - * Returns all edges to or from node v regardless of direction. Optionally filters those edges - * down to just those between nodes v and w regardless of direction. - * Complexity: O(|E|). - */nodeEdges(v,w){var inEdges=this.inEdges(v,w);if(inEdges){return inEdges.concat(this.outEdges(v,w))}}}function incrementOrInitEntry(map,k){if(map[k]){map[k]++}else{map[k]=1}}function decrementOrRemoveEntry(map,k){if(!--map[k]){delete map[k]}}function edgeArgsToId(isDirected,v_,w_,name){var v=""+v_;var w=""+w_;if(!isDirected&&v>w){var tmp=v;v=w;w=tmp}return v+EDGE_KEY_DELIM+w+EDGE_KEY_DELIM+(name===undefined?DEFAULT_EDGE_NAME:name)}function edgeArgsToObj(isDirected,v_,w_,name){var v=""+v_;var w=""+w_;if(!isDirected&&v>w){var tmp=v;v=w;w=tmp}var edgeObj={v:v,w:w};if(name){edgeObj.name=name}return edgeObj}function edgeObjToId(isDirected,edgeObj){return edgeArgsToId(isDirected,edgeObj.v,edgeObj.w,edgeObj.name)}module.exports=Graph},{}],45:[function(require,module,exports){ -// Includes only the "core" of graphlib -module.exports={Graph:require("./graph"),version:require("./version")}},{"./graph":44,"./version":47}],46:[function(require,module,exports){var Graph=require("./graph");module.exports={write:write,read:read}; -/** - * Creates a JSON representation of the graph that can be serialized to a string with - * JSON.stringify. The graph can later be restored using json.read. - */function write(g){var json={options:{directed:g.isDirected(),multigraph:g.isMultigraph(),compound:g.isCompound()},nodes:writeNodes(g),edges:writeEdges(g)};if(g.graph()!==undefined){json.value=structuredClone(g.graph())}return json}function writeNodes(g){return g.nodes().map(function(v){var nodeValue=g.node(v);var parent=g.parent(v);var node={v:v};if(nodeValue!==undefined){node.value=nodeValue}if(parent!==undefined){node.parent=parent}return node})}function writeEdges(g){return g.edges().map(function(e){var edgeValue=g.edge(e);var edge={v:e.v,w:e.w};if(e.name!==undefined){edge.name=e.name}if(edgeValue!==undefined){edge.value=edgeValue}return edge})} -/** - * Takes JSON as input and returns the graph representation. - * - * @example - * var g2 = graphlib.json.read(JSON.parse(str)); - * g2.nodes(); - * // ['a', 'b'] - * g2.edges() - * // [ { v: 'a', w: 'b' } ] - */function read(json){var g=new Graph(json.options).setGraph(json.value);json.nodes.forEach(function(entry){g.setNode(entry.v,entry.value);if(entry.parent){g.setParent(entry.v,entry.parent)}});json.edges.forEach(function(entry){g.setEdge({v:entry.v,w:entry.w,name:entry.name},entry.value)});return g}},{"./graph":44}],47:[function(require,module,exports){module.exports="2.2.4"},{}]},{},[1])(1)}); diff --git a/tinygrad/tinygrad/viz/assets/unpkg.com/@highlightjs/cdn-assets@11.10.0/styles/tokyo-night-dark.min.css b/tinygrad/tinygrad/viz/assets/unpkg.com/@highlightjs/cdn-assets@11.10.0/styles/tokyo-night-dark.min.css deleted file mode 100644 index dc63ad9e..00000000 --- a/tinygrad/tinygrad/viz/assets/unpkg.com/@highlightjs/cdn-assets@11.10.0/styles/tokyo-night-dark.min.css +++ /dev/null @@ -1,8 +0,0 @@ -pre code.hljs{display:block;overflow-x:auto;padding:1em}code.hljs{padding:3px 5px}/*! - Theme: Tokyo-night-Dark - origin: https://github.com/enkia/tokyo-night-vscode-theme - Description: Original highlight.js style - Author: (c) Henri Vandersleyen - License: see project LICENSE - Touched: 2022 -*/.hljs-comment,.hljs-meta{color:#565f89}.hljs-deletion,.hljs-doctag,.hljs-regexp,.hljs-selector-attr,.hljs-selector-class,.hljs-selector-id,.hljs-selector-pseudo,.hljs-tag,.hljs-template-tag,.hljs-variable.language_{color:#f7768e}.hljs-link,.hljs-literal,.hljs-number,.hljs-params,.hljs-template-variable,.hljs-type,.hljs-variable{color:#ff9e64}.hljs-attribute,.hljs-built_in{color:#e0af68}.hljs-keyword,.hljs-property,.hljs-subst,.hljs-title,.hljs-title.class_,.hljs-title.class_.inherited__,.hljs-title.function_{color:#7dcfff}.hljs-selector-tag{color:#73daca}.hljs-addition,.hljs-bullet,.hljs-quote,.hljs-string,.hljs-symbol{color:#9ece6a}.hljs-code,.hljs-formula,.hljs-section{color:#7aa2f7}.hljs-attr,.hljs-char.escape_,.hljs-keyword,.hljs-name,.hljs-operator{color:#bb9af7}.hljs-punctuation{color:#c0caf5}.hljs{background:#1a1b26;color:#9aa5ce}.hljs-emphasis{font-style:italic}.hljs-strong{font-weight:700} \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/fetch_assets.sh b/tinygrad/tinygrad/viz/fetch_assets.sh deleted file mode 100755 index ae4720ce..00000000 --- a/tinygrad/tinygrad/viz/fetch_assets.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -fetch() { - echo "fetch $1" - mkdir -p assets/$1 - rmdir assets/$1 - curl -o assets/$1 https://$1 -} -fetch "d3js.org/d3.v7.min.js" -fetch "dagrejs.github.io/project/dagre/latest/dagre.min.js" -fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/styles/default.min.css" -fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/highlight.min.js" -fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/python.min.js" -fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/cpp.min.js" -fetch "unpkg.com/@highlightjs/cdn-assets@11.10.0/styles/tokyo-night-dark.min.css" diff --git a/tinygrad/tinygrad/viz/index.html b/tinygrad/tinygrad/viz/index.html deleted file mode 100644 index 8006dce7..00000000 --- a/tinygrad/tinygrad/viz/index.html +++ /dev/null @@ -1,228 +0,0 @@ - - - - tinygrad viz - - - - - - - - - - - - -
-
- - Profiler - -
-
-
-
Rendering new layout...
- - - - - - - - - - - - - -
-
-
- - - diff --git a/tinygrad/tinygrad/viz/js/index.js b/tinygrad/tinygrad/viz/js/index.js deleted file mode 100644 index 2db0ff3d..00000000 --- a/tinygrad/tinygrad/viz/js/index.js +++ /dev/null @@ -1,466 +0,0 @@ -// **** graph renderers - -// ** UOp graph - -function intersectRect(r1, r2) { - const dx = r2.x-r1.x; - const dy = r2.y-r1.y; - if (dx === 0 && dy === 0) throw new Error("Invalid node coordinates, rects must not overlap"); - const scaleX = dx !== 0 ? (r1.width/2)/Math.abs(dx) : Infinity; - const scaleY = dy !== 0 ? (r1.height/2)/Math.abs(dy) : Infinity; - const scale = Math.min(scaleX, scaleY); - return {x:r1.x+dx*scale, y:r1.y+dy*scale}; -} - -const rect = (s) => document.querySelector(s).getBoundingClientRect(); - -let [workerUrl, worker, timeout] = [null, null, null]; -async function renderDag(graph, additions, recenter=false) { - // start calculating the new layout (non-blocking) - if (worker == null) { - const resp = await Promise.all(["/assets/dagrejs.github.io/project/dagre/latest/dagre.min.js","/js/worker.js"].map(u => fetch(u))); - workerUrl = URL.createObjectURL(new Blob([(await Promise.all(resp.map((r) => r.text()))).join("\n")], { type: "application/javascript" })); - worker = new Worker(workerUrl); - } else { - worker.terminate(); - worker = new Worker(workerUrl); - } - if (timeout != null) clearTimeout(timeout); - const progressMessage = document.querySelector(".progress-message"); - timeout = setTimeout(() => {progressMessage.style.display = "block"}, 2000); - worker.postMessage({graph, additions, ctxs}); - worker.onmessage = (e) => { - progressMessage.style.display = "none"; - clearTimeout(timeout); - d3.select("#bars").html(""); - const g = dagre.graphlib.json.read(e.data); - // draw nodes - const STROKE_WIDTH = 1.4; - const nodes = d3.select("#nodes").selectAll("g").data(g.nodes().map(id => g.node(id)), d => d).join("g") - .attr("transform", d => `translate(${d.x},${d.y})`).classed("clickable", d => d.ref != null) - .on("click", (_,d) => d.ref != null && setState({ expandSteps: true, currentCtx:d.ref, currentStep:0, currentRewrite:0 })); - nodes.selectAll("rect").data(d => [d]).join("rect").attr("width", d => d.width).attr("height", d => d.height).attr("fill", d => d.color) - .attr("x", d => -d.width/2).attr("y", d => -d.height/2).attr("style", d => d.style ?? `stroke:#4a4b57; stroke-width:${STROKE_WIDTH}px;`); - nodes.selectAll("g.label").data(d => [d]).join("g").attr("class", "label").attr("transform", d => { - const x = (d.width-d.padding*2)/2; - const y = (d.height-d.padding*2)/2+STROKE_WIDTH; - return `translate(-${x}, -${y})`; - }).selectAll("text").data(d => [d.label.split("\n")]).join("text").selectAll("tspan").data(d => d).join("tspan").text(d => d).attr("x", "0") - .attr("dy", 14).attr("xml:space", "preserve"); - const tags = nodes.selectAll("g.tag").data(d => d.tag != null ? [d] : []).join("g").attr("class", "tag") - .attr("transform", d => `translate(${-d.width/2+8}, ${-d.height/2+8})`); - tags.selectAll("circle").data(d => [d]).join("circle"); - tags.selectAll("text").data(d => [d.tag]).join("text").text(d => d).attr("dy", "0.35em"); - // draw edges - const line = d3.line().x(d => d.x).y(d => d.y).curve(d3.curveBasis); - d3.select("#edges").selectAll("path.edgePath").data(g.edges()).join("path").attr("class", "edgePath").attr("d", (e) => { - const edge = g.edge(e); - const points = edge.points.slice(1, edge.points.length-1); - points.unshift(intersectRect(g.node(e.v), points[0])); - points.push(intersectRect(g.node(e.w), points[points.length-1])); - return line(points); - }).attr("marker-end", "url(#arrowhead)"); - const edgeLabels = d3.select("#edge-labels").selectAll("g").data(g.edges().filter(e => g.edge(e).label != null)).join("g").attr("transform", (e) => { - // get a point near the end - const [p1, p2] = g.edge(e).points.slice(-2); - const dx = p2.x-p1.x; - const dy = p2.y-p1.y; - // normalize to the unit vector - const len = Math.sqrt(dx*dx + dy*dy); - const ux = dx / len; - const uy = dy / len; - // avoid overlap with the arrowhead - const offset = 17; - const x = p2.x - ux * offset; - const y = p2.y - uy * offset; - return `translate(${x}, ${y})` - }).attr("class", "tag"); - edgeLabels.selectAll("circle").data(e => [g.edge(e).label]).join("circle"); - edgeLabels.selectAll("text").data(e => [g.edge(e).label]).join("text").text(d => d).attr("dy", "0.35em"); - if (recenter) document.getElementById("zoom-to-fit-btn").click(); - }; - -} - -// ** Memory graph (WIP) - -DTYPE_SIZE = {"bool": 1, "char": 1, "uchar": 1, "short": 2, "ushort": 2, "int": 4, "uint": 4, - "long": 8, "ulong": 8, "half": 2, "bfloat": 2, "float": 4, "double": 8} -function getBuffer(e) { - const [_, size, dtype, num, device] = e.label.split("\n"); - return {nbytes:size*DTYPE_SIZE[dtype.split("dtypes.")[1]], dtype, device:device.split(" ")[1], num:parseInt(num.split(" ")[1])}; -} - -function pluralize(num, name, alt=null) { - return num === 1 ? `${num} ${name}` : `${num} ${alt ?? name+'s'}` -} - -function renderMemoryGraph(graph) { - // ** construct alloc/free traces - // we can map reads/writes from the kernel graph - const actions = []; - const children = new Map(); // {buffer: [...assign]} - for (const [k,v] of Object.entries(graph)) { - if (!v.label.startsWith("ASSIGN")) continue; - actions.push({ op: "write", buffer: v.src[0] }); - for (const ks of graph[v.src[1]].src) { - const node = graph[ks]; - const s = node.label.startsWith("ASSIGN") ? node.src[0] : ks; - if (!children.has(s)) children.set(s, []); - children.get(s).push(v); - if (s !== v.src[0]) actions.push({ op: "read", buffer: s }); - } - } - const prealloc = new Set(); - const traces = []; - for (const a of actions) { - // a buffer is allocated immediately before the first write - // TODO: we don't know the buffer is preallocated if there's only an assign in the graph - if (a.op === "write") { - traces.push({ type: "alloc", buffer: a.buffer }); - } - else { - if (traces.find(t => t.buffer === a.buffer && t.type === "alloc") == null) { - prealloc.add(a.buffer); - } - else if (a === actions.findLast(({ buffer }) => buffer === a.buffer)) { - traces.push({type: "free", buffer: a.buffer }); - } - } - } - // ** get coordinates and layout for each buffer - const ret = {}; - let timestep = 0; // x - let memUsed = 0; // y - for (const id of prealloc) { - const buf = getBuffer(graph[id]); - ret[id] = { x: [timestep], y: [memUsed], buf, id }; - memUsed += buf.nbytes; - } - let peak = memUsed; - const liveBufs = [...prealloc]; - for (const t of traces) { - const buf = getBuffer(graph[t.buffer]); - const idx = liveBufs.findLastIndex(b => t.buffer === b); - // alloc - if (idx === -1) { - liveBufs.push(t.buffer); - ret[t.buffer] = { x: [timestep], y: [memUsed], buf, id: t.buffer }; - memUsed += buf.nbytes; - peak = Math.max(memUsed, peak); - timestep += 1; - } // free - else { - memUsed -= buf.nbytes; - timestep += 1; - const removed = ret[liveBufs.splice(idx, 1)[0]]; - removed.x.push(timestep); - removed.y.push(removed.y.at(-1)); - if (idx < liveBufs.length) { - for (let j=idx; j d3.format(".3~s")(d)+"B"; - axesGroup.append("g").call(d3.axisLeft(yscale).tickFormat(nbytes_format)); - axesGroup.append("g").attr("transform", `translate(0, ${yscale.range()[0]})`).call(d3.axisBottom(xscale).tickFormat(() => "")); - const polygonGroup = render.append("g").attr("id", "polygons"); - const colors = ["7aa2f7", "ff9e64", "f7768e", "2ac3de", "7dcfff", "1abc9c", "9ece6a", "e0af68", "bb9af7", "9d7cd8", "ff007c"]; - const polygons = polygonGroup.selectAll("polygon").data(Object.values(ret)).join("polygon").attr("points", (d) => { - const xs = d.x.map(t => xscale(t)); - const y1 = d.y.map(t => yscale(t)); - const y2 = d.y.map(t => yscale(t+d.buf.nbytes)); - const p0 = xs.map((x, i) => `${x},${y1[i]}`); - const p1 = xs.map((x, i) => `${x},${y2[i]}`).reverse(); - return `${p0.join(' ')} ${p1.join(' ')}`; - }).attr("fill", d => `#${colors[d.buf.num % colors.length]}`).on("mouseover", (e, { id, buf, x }) => { - d3.select(e.currentTarget).attr("stroke", "rgba(26, 27, 38, 0.8)").attr("stroke-width", 0.8); - const metadata = document.querySelector(".metadata"); - document.getElementById("current-buf")?.remove(); - const { num, dtype, nbytes, ...rest } = buf; - let label = `\nalive for ${pluralize(x[x.length-1]-x[0], 'timestep')}`; - label += '\n'+Object.entries(rest).map(([k, v]) => `${k}=${v}`).join('\n'); - const buf_children = children.get(id); - if (buf_children) { - label += `\n${pluralize(buf_children.length, 'child', 'children')}\n`; - label += buf_children.map((c,i) => `[${i+1}] `+graph[c.src[1]].label.split("\n")[1]).join("\n"); - } - metadata.appendChild(Object.assign(document.createElement("pre"), { innerText: label, id: "current-buf", className: "wrap" })); - }).on("mouseout", (e, _) => { - d3.select(e.currentTarget).attr("stroke", null).attr("stroke-width", null); - document.getElementById("current-buf")?.remove() - }); - // TODO: add the kernel line here - document.getElementById("zoom-to-fit-btn").click(); -} - -// ** zoom and recentering - -const zoom = d3.zoom().on("zoom", (e) => d3.select("#render").attr("transform", e.transform)); -d3.select("#graph-svg").call(zoom); -// zoom to fit into view -document.getElementById("zoom-to-fit-btn").addEventListener("click", () => { - const svg = d3.select("#graph-svg"); - svg.call(zoom.transform, d3.zoomIdentity); - const mainRect = rect(".main-container"); - const x0 = rect(".ctx-list-parent").right; - const x1 = rect(".metadata-parent").left; - const pad = 16; - const R = { x: x0+pad, y: mainRect.top+pad, width: (x1>0 ? x1-x0 : mainRect.width)-2*pad, height: mainRect.height-2*pad }; - const r = rect("#render"); - if (r.width === 0) return; - const scale = Math.min(R.width/r.width, R.height/r.height); - const [tx, ty] = [R.x+(R.width-r.width*scale)/2-r.left*scale, R.y+(R.height-r.height*scale)/2]; - svg.call(zoom.transform, d3.zoomIdentity.translate(tx, ty).scale(scale)); -}); - -// **** main VIZ interfacae - -function codeBlock(st, language, { loc, wrap }) { - const code = document.createElement("code"); - code.innerHTML = hljs.highlight(st, { language }).value; - code.className = "hljs"; - const ret = document.createElement("pre"); - if (wrap) ret.className = "wrap"; - if (loc != null) { - const link = ret.appendChild(document.createElement("a")); - link.href = "vscode://file"+loc.join(":"); - link.textContent = `${loc[0].split("/").at(-1)}:${loc[1]}`+"\n\n"; - } - ret.appendChild(code); - return ret; -} - -// ** hljs extra definitions for UOps and float4 -hljs.registerLanguage("python", (hljs) => ({ - ...hljs.getLanguage("python"), - case_insensitive: false, - contains: [ - { begin: 'dtypes\\.[a-zA-Z_][a-zA-Z0-9_-]*(\\.[a-zA-Z_][a-zA-Z0-9_-]*)*' + '(?=[.\\s\\n[:,(])', className: "type" }, - { begin: 'dtypes\\.[a-zA-Z_][a-zA-Z0-9_-].vec*' + '(?=[.\\s\\n[:,(])', className: "type" }, - { begin: '[a-zA-Z_][a-zA-Z0-9_-]*\\.[a-zA-Z_][a-zA-Z0-9_-]*' + '(?=[.\\s\\n[:,()])', className: "operator" }, - { begin: '[A-Z][a-zA-Z0-9_]*(?=\\()', className: "section", ignoreEnd: true }, - ...hljs.getLanguage("python").contains, - ] -})); -hljs.registerLanguage("cpp", (hljs) => ({ - ...hljs.getLanguage('cpp'), - contains: [{ begin: '\\b(?:float|half)[0-9]+\\b', className: 'type' }, ...hljs.getLanguage('cpp').contains] -})); - -var ret = []; -var cache = {}; -var ctxs = null; -const evtSources = []; -// VIZ displays graph rewrites in 3 levels, from bottom-up: -// rewrite: a single UOp transformation -// step: collection of rewrites -// context: collection of steps -const state = {currentCtx:-1, currentStep:0, currentRewrite:0, expandSteps:false}; -function setState(ns) { - Object.assign(state, ns); - main(); -} -async function main() { - const { currentCtx, currentStep, currentRewrite, expandSteps } = state; - // ** left sidebar context list - if (ctxs == null) { - ctxs = await (await fetch("/ctxs")).json(); - setState({ currentCtx:-1 }); - } - const ctxList = document.querySelector(".ctx-list"); - ctxList.innerHTML = ""; - for (const [i,{name, steps}] of ctxs.entries()) { - const ul = ctxList.appendChild(document.createElement("ul")); - if (i === currentCtx) { - ul.className = "active"; - requestAnimationFrame(() => ul.scrollIntoView({ behavior: "auto", block: "nearest" })); - } - const p = ul.appendChild(document.createElement("p")); - p.innerHTML = name.replace(/\u001b\[(\d+)m(.*?)\u001b\[0m/g, (_, code, st) => { - const colors = ['gray','red','green','yellow','blue','magenta','cyan','white']; - return `${st}`; - }); - p.onclick = () => { - setState(i === currentCtx ? { expandSteps:!expandSteps } : { expandSteps:true, currentCtx:i, currentStep:0, currentRewrite:0 }); - } - for (const [j,u] of steps.entries()) { - const inner = ul.appendChild(document.createElement("ul")); - if (i === currentCtx && j === currentStep) { - inner.className = "active"; - requestAnimationFrame(() => inner.scrollIntoView({ behavior: "auto", block: "nearest" })); - } - inner.innerText = `${u.name ?? u.loc[0].replaceAll("\\", "/").split("/").pop()+':'+u.loc[1]} - ${u.match_count}`; - inner.style.marginLeft = `${8*u.depth}px`; - inner.style.display = i === currentCtx && expandSteps ? "block" : "none"; - inner.onclick = (e) => { - e.stopPropagation(); - setState({ currentStep:j, currentCtx:i, currentRewrite:0 }); - } - } - } - // ** center graph - if (currentCtx == -1) return; - const ctx = ctxs[currentCtx]; - const step = ctx.steps[currentStep]; - const ckey = `ctx=${currentCtx}&idx=${currentStep}`; - // close any pending event sources - let activeSrc = null; - for (const e of evtSources) { - if (e.url.split("?")[1] !== ckey) e.close(); - else if (e.readyState === EventSource.OPEN) activeSrc = e; - } - if (ckey in cache) { - ret = cache[ckey]; - } - // if we don't have a complete cache yet we start streaming rewrites in this step - if (!(ckey in cache) || (cache[ckey].length !== step.match_count+1 && activeSrc == null)) { - ret = []; - cache[ckey] = ret; - const eventSource = new EventSource(`/ctxs?${ckey}`); - evtSources.push(eventSource); - eventSource.onmessage = (e) => { - if (e.data === "END") return eventSource.close(); - const chunk = JSON.parse(e.data); - ret.push(chunk); - // if it's the first one render this new rgaph - if (ret.length === 1) return main(); - // otherwise just enable the graph selector - const ul = document.getElementById(`rewrite-${ret.length-1}`); - if (ul != null) ul.classList.remove("disabled"); - }; - } - if (ret.length === 0) return; - if (step.name == "View Memory Graph") { - renderMemoryGraph(ret[currentRewrite].graph); - } else { - renderDag(ret[currentRewrite].graph, ret[currentRewrite].changed_nodes || [], recenter=currentRewrite === 0); - } - // ** right sidebar code blocks - const metadata = document.querySelector(".metadata"); - const [code, lang] = ctx.kernel_code != null ? [ctx.kernel_code, "cpp"] : [ret[currentRewrite].uop, "python"]; - metadata.replaceChildren(codeBlock(step.code_line, "python", { loc:step.loc, wrap:true }), codeBlock(code, lang, { wrap:false })); - // ** rewrite steps - if (step.match_count >= 1) { - const rewriteList = metadata.appendChild(document.createElement("div")); - rewriteList.className = "rewrite-list"; - for (let s=0; s<=step.match_count; s++) { - const ul = rewriteList.appendChild(document.createElement("ul")); - ul.innerText = s; - ul.id = `rewrite-${s}`; - ul.onclick = () => setState({ currentRewrite:s }); - ul.className = s > ret.length-1 ? "disabled" : s === currentRewrite ? "active" : ""; - if (s > 0 && s === currentRewrite) { - const { upat, diff } = ret[s]; - metadata.appendChild(codeBlock(upat[1], "python", { loc:upat[0], wrap:true })); - const diffCode = metadata.appendChild(document.createElement("pre")).appendChild(document.createElement("code")); - for (const line of diff) { - const span = diffCode.appendChild(document.createElement("span")); - span.style.color = line.startsWith("+") ? "#3aa56d" : line.startsWith("-") ? "#d14b4b" : "#f0f0f5"; - span.innerText = line; - diffCode.appendChild(document.createElement("br")); - } - diffCode.className = "wrap"; - } - } - } -} - -// **** collapse/expand - -let isCollapsed = false; -document.querySelector(".collapse-btn").addEventListener("click", (e) => { - isCollapsed = !isCollapsed; - document.querySelector(".main-container").classList.toggle("collapsed", isCollapsed); - e.currentTarget.blur(); - e.currentTarget.style.transform = isCollapsed ? "rotate(180deg)" : "rotate(0deg)"; -}); - -// **** resizer - -function appendResizer(element, { minWidth, maxWidth }, left=false) { - const handle = Object.assign(document.createElement("div"), { className: "resize-handle", style: left ? "right: 0" : "left: 0; margin-top: 0" }); - element.appendChild(handle); - const resize = (e) => { - const change = e.clientX - element.dataset.startX; - let newWidth = ((Number(element.dataset.startWidth)+(left ? change : -change))/Number(element.dataset.containerWidth))*100; - element.style.width = `${Math.max(minWidth, Math.min(maxWidth, newWidth))}%`; - }; - handle.addEventListener("mousedown", (e) => { - e.preventDefault(); - element.dataset.startX = e.clientX; - element.dataset.containerWidth = rect(".main-container").width; - element.dataset.startWidth = element.getBoundingClientRect().width; - document.documentElement.addEventListener("mousemove", resize, false); - document.documentElement.addEventListener("mouseup", () => { - document.documentElement.removeEventListener("mousemove", resize, false); - element.style.userSelect = "initial"; - }, { once: true }); - }); -} -appendResizer(document.querySelector(".ctx-list-parent"), { minWidth: 15, maxWidth: 50 }, left=true); -appendResizer(document.querySelector(".metadata-parent"), { minWidth: 20, maxWidth: 50 }); - -// **** keyboard shortcuts - -document.addEventListener("keydown", async function(event) { - const { currentCtx, currentStep, currentRewrite, expandSteps } = state; - // up and down change the step or context from the list - if (event.key == "ArrowUp") { - event.preventDefault(); - if (expandSteps) { - return setState({ currentRewrite:0, currentStep:Math.max(0, currentStep-1) }); - } - return setState({ currentStep:0, currentRewrite:0, currentCtx:Math.max(0, currentCtx-1) }); - } - if (event.key == "ArrowDown") { - event.preventDefault(); - if (expandSteps) { - const totalUOps = ctxs[currentCtx].steps.length-1; - return setState({ currentRewrite:0, currentStep:Math.min(totalUOps, currentStep+1) }); - } - return setState({ currentStep:0, currentRewrite:0, currentCtx:Math.min(ctxs.length-1, currentCtx+1) }); - } - // enter toggles focus on a single rewrite stage - if (event.key == "Enter") { - event.preventDefault() - if (currentCtx === -1) { - return setState({ currentCtx:0, expandSteps:true }); - } - return setState({ currentStep:0, currentRewrite:0, expandSteps:!expandSteps }); - } - // left and right go through rewrites in a single UOp - if (event.key == "ArrowLeft") { - event.preventDefault() - return setState({ currentRewrite:Math.max(0, currentRewrite-1) }); - } - if (event.key == "ArrowRight") { - event.preventDefault() - const totalRewrites = ret.length-1; - return setState({ currentRewrite:Math.min(totalRewrites, currentRewrite+1) }); - } - // space recenters the graph - if (event.key == " ") { - event.preventDefault() - document.getElementById("zoom-to-fit-btn").click(); - } -}); - -main() diff --git a/tinygrad/tinygrad/viz/js/worker.js b/tinygrad/tinygrad/viz/js/worker.js deleted file mode 100644 index 31b7ba10..00000000 --- a/tinygrad/tinygrad/viz/js/worker.js +++ /dev/null @@ -1,33 +0,0 @@ -const NODE_PADDING = 10; -const LINE_HEIGHT = 14; -const canvas = new OffscreenCanvas(0, 0); -const ctx = canvas.getContext("2d"); -ctx.font = `${LINE_HEIGHT}px sans-serif`; - -const ansiStrip = (st, tag) => st.replace(/\u001b\[(\d+)m(.*?)\u001b\[0m/g, (_,__,st) => st); - -onmessage = (e) => { - const { graph, additions, ctxs } = e.data; - const g = new dagre.graphlib.Graph({ compound: true }); - g.setGraph({ rankdir: "LR" }).setDefaultEdgeLabel(function() { return {}; }); - if (additions.length !== 0) g.setNode("addition", {label:"", style:"fill: rgba(26, 27, 38, 0.5);", padding:0}); - for (let [k, {label, src, ref, ...rest }] of Object.entries(graph)) { - const idx = ref ? ctxs.findIndex(k => k.ref === ref) : -1; - if (idx != -1) label += `\ncodegen@${ansiStrip(ctxs[idx].name)}`; - // adjust node dims by label size + add padding - let [width, height] = [0, 0]; - for (line of label.split("\n")) { - width = Math.max(width, ctx.measureText(line).width); - height += LINE_HEIGHT; - } - g.setNode(k, {width:width+NODE_PADDING*2, height:height+NODE_PADDING*2, padding:NODE_PADDING, label, ref:idx==-1 ? null : idx, ...rest}); - // add edges - const edgeCounts = {} - for (const s of src) edgeCounts[s] = (edgeCounts[s] || 0)+1; - for (const s of src) g.setEdge(s, k, { label: edgeCounts[s] > 1 ? edgeCounts[s] : null }); - if (additions.includes(parseInt(k))) g.setParent(k, "addition"); - } - dagre.layout(g); - postMessage(dagre.graphlib.json.write(g)); - self.close(); -} diff --git a/tinygrad/tinygrad/viz/perfetto.html b/tinygrad/tinygrad/viz/perfetto.html deleted file mode 100644 index a2d55c29..00000000 --- a/tinygrad/tinygrad/viz/perfetto.html +++ /dev/null @@ -1,178 +0,0 @@ - - - - - - -
-
- UOps -
- -
-
-
Loading trace data...
-
- - - - - - \ No newline at end of file diff --git a/tinygrad/tinygrad/viz/serve.py b/tinygrad/tinygrad/viz/serve.py deleted file mode 100755 index 5aabce46..00000000 --- a/tinygrad/tinygrad/viz/serve.py +++ /dev/null @@ -1,210 +0,0 @@ -#!/usr/bin/env python3 -import multiprocessing, pickle, functools, difflib, os, threading, json, time, sys, webbrowser, socket, argparse, decimal, socketserver -from http.server import BaseHTTPRequestHandler -from urllib.parse import parse_qs, urlparse -from typing import Any, TypedDict, Generator -from tinygrad.helpers import colored, getenv, tqdm, unwrap, word_wrap, TRACEMETA -from tinygrad.uop.ops import TrackedGraphRewrite, UOp, Ops, lines, GroupOp, srender, sint -from tinygrad.codegen.kernel import Kernel -from tinygrad.device import ProfileEvent, ProfileDeviceEvent, ProfileRangeEvent, ProfileGraphEvent -from tinygrad.dtype import dtypes - -uops_colors = {Ops.LOAD: "#ffc0c0", Ops.STORE: "#87CEEB", Ops.CONST: "#e0e0e0", Ops.VCONST: "#e0e0e0", Ops.REDUCE: "#FF5B5B", - Ops.DEFINE_GLOBAL: "#ffe0b0", Ops.DEFINE_LOCAL: "#ffe0d0", Ops.DEFINE_ACC: "#f0ffe0", Ops.REDUCE_AXIS: "#FF6B6B", - Ops.RANGE: "#c8a0e0", Ops.ASSIGN: "#909090", Ops.BARRIER: "#ff8080", Ops.IF: "#c8b0c0", Ops.SPECIAL: "#c0c0ff", - Ops.INDEX: "#e8ffa0", Ops.WMMA: "#efefc0", Ops.VIEW: "#C8F9D4", Ops.MULTI: "#f6ccff", Ops.KERNEL: "#3e7f55", Ops.IGNORE: "#00C000", - **{x:"#D8F9E4" for x in GroupOp.Movement}, **{x:"#ffffc0" for x in GroupOp.ALU}, Ops.THREEFRY:"#ffff80", Ops.BUFFER_VIEW: "#E5EAFF", - Ops.BLOCK: "#C4A484", Ops.BLOCKEND: "#C4A4A4", Ops.BUFFER: "#B0BDFF", Ops.COPY: "#a040a0", Ops.FUSE: "#FFa500", - Ops.ALLREDUCE: "#ff40a0", Ops.GBARRIER: "#FFC14D", Ops.MSELECT: "#d040a0", Ops.MSTACK: "#d040a0"} - -# VIZ API - -# ** Metadata for a track_rewrites scope - -@functools.cache -def render_program(k:Kernel): - try: return k.opts.render(k.uops) - except Exception as e: return f"ISSUE RENDERING KERNEL: {e}\nast = {k.ast}\nopts = {k.applied_opts}" - -def get_metadata(keys:list[Any], contexts:list[list[TrackedGraphRewrite]]) -> list[dict]: - ret = [] - for k,v in zip(keys, contexts): - steps = [{"name":s.name, "loc":s.loc, "depth":s.depth, "match_count":len(s.matches), "code_line":lines(s.loc[0])[s.loc[1]-1].strip()} for s in v] - if isinstance(k, Kernel): ret.append({"name":k.name, "kernel_code":render_program(k), "ref":id(k.ast), "steps":steps}) - else: ret.append({"name":str(k), "steps":steps}) - return ret - -# ** Complete rewrite details for a graph_rewrite call - -class GraphRewriteDetails(TypedDict): - graph: dict # JSON serialized UOp for this rewrite step - uop: str # strigified UOp for this rewrite step - diff: list[str]|None # diff of the single UOp that changed - changed_nodes: list[int]|None # the changed UOp id + all its parents ids - upat: tuple[tuple[str, int], str]|None # [loc, source_code] of the matched UPat - -def shape_to_str(s:tuple[sint, ...]): return "(" + ','.join(srender(x) for x in s) + ")" -def mask_to_str(s:tuple[tuple[sint, sint], ...]): return "(" + ','.join(shape_to_str(x) for x in s) + ")" - -def uop_to_json(x:UOp) -> dict[int, dict]: - assert isinstance(x, UOp) - graph: dict[int, dict] = {} - excluded: set[UOp] = set() - for u in (toposort:=x.toposort()): - # always exclude DEVICE/CONST/UNIQUE - if u.op in {Ops.DEVICE, Ops.CONST, Ops.UNIQUE}: excluded.add(u) - # only exclude CONST VIEW source if it has no other children in the graph - if u.op is Ops.CONST and len(u.src) != 0 and all(cr.op is Ops.CONST for c in u.src[0].children if (cr:=c()) is not None and cr in toposort): - excluded.update(u.src) - for u in toposort: - if u in excluded: continue - argst = str(u.arg) - if u.op is Ops.VIEW: - argst = ("\n".join([f"{shape_to_str(v.shape)} / {shape_to_str(v.strides)}"+("" if v.offset == 0 else f" / {srender(v.offset)}")+ - (f"\nMASK {mask_to_str(v.mask)}" if v.mask is not None else "") for v in unwrap(u.st).views])) - label = f"{str(u.op).split('.')[1]}{(chr(10)+word_wrap(argst.replace(':', ''))) if u.arg is not None else ''}" - if u.dtype != dtypes.void: label += f"\n{u.dtype}" - for idx,x in enumerate(u.src): - if x in excluded: - if x.op is Ops.CONST and dtypes.is_float(u.dtype): label += f"\nCONST{idx} {x.arg:g}" - else: label += f"\n{x.op.name}{idx} {x.arg}" - try: - if u.op not in {Ops.VIEW, Ops.BUFFER, Ops.KERNEL, Ops.ASSIGN, Ops.COPY, Ops.SINK, *GroupOp.Buffer} and u.st is not None: - label += f"\n{shape_to_str(u.shape)}" - except Exception: - label += "\n" - # NOTE: kernel already has metadata in arg - if TRACEMETA >= 2 and u.metadata is not None and u.op is not Ops.KERNEL: label += "\n"+repr(u.metadata) - graph[id(u)] = {"label":label, "src":[id(x) for x in u.src if x not in excluded], "color":uops_colors.get(u.op, "#ffffff"), - "ref":id(u.arg.ast) if u.op is Ops.KERNEL else None, "tag":u.tag} - return graph - -def get_details(ctx:TrackedGraphRewrite) -> Generator[GraphRewriteDetails, None, None]: - yield {"graph":uop_to_json(next_sink:=ctx.sink), "uop":str(ctx.sink), "changed_nodes":None, "diff":None, "upat":None} - replaces: dict[UOp, UOp] = {} - for u0,u1,upat in tqdm(ctx.matches): - replaces[u0] = u1 - try: new_sink = next_sink.substitute(replaces) - except RecursionError as e: new_sink = UOp(Ops.NOOP, arg=str(e)) - yield {"graph":(sink_json:=uop_to_json(new_sink)), "uop":str(new_sink), "changed_nodes":[id(x) for x in u1.toposort() if id(x) in sink_json], - "diff":list(difflib.unified_diff(str(u0).splitlines(), str(u1).splitlines())), "upat":(upat.location, upat.printable())} - if not ctx.bottom_up: next_sink = new_sink - -# Profiler API -devices:dict[str, tuple[decimal.Decimal, decimal.Decimal, int]] = {} -def prep_ts(device:str, ts:decimal.Decimal, is_copy): return int(decimal.Decimal(ts) + devices[device][is_copy]) -def dev_to_pid(device:str, is_copy=False): return {"pid": devices[device][2], "tid": int(is_copy)} -def dev_ev_to_perfetto_json(ev:ProfileDeviceEvent): - devices[ev.device] = (ev.comp_tdiff, ev.copy_tdiff if ev.copy_tdiff is not None else ev.comp_tdiff, len(devices)) - return [{"name": "process_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "args": {"name": ev.device}}, - {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 0, "args": {"name": "COMPUTE"}}, - {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 1, "args": {"name": "COPY"}}] -def range_ev_to_perfetto_json(ev:ProfileRangeEvent): - return [{"name": ev.name, "ph": "X", "ts": prep_ts(ev.device, ev.st, ev.is_copy), "dur": float(ev.en-ev.st), **dev_to_pid(ev.device, ev.is_copy)}] -def graph_ev_to_perfetto_json(ev:ProfileGraphEvent, reccnt): - ret = [] - for i,e in enumerate(ev.ents): - st, en = ev.sigs[e.st_id], ev.sigs[e.en_id] - ret += [{"name": e.name, "ph": "X", "ts": prep_ts(e.device, st, e.is_copy), "dur": float(en-st), **dev_to_pid(e.device, e.is_copy)}] - for dep in ev.deps[i]: - d = ev.ents[dep] - ret += [{"ph": "s", **dev_to_pid(d.device, d.is_copy), "id": reccnt+len(ret), "ts": prep_ts(d.device, ev.sigs[d.en_id], d.is_copy), "bp": "e"}] - ret += [{"ph": "f", **dev_to_pid(e.device, e.is_copy), "id": reccnt+len(ret)-1, "ts": prep_ts(e.device, st, e.is_copy), "bp": "e"}] - return ret -def to_perfetto(profile:list[ProfileEvent]): - # Start json with devices. - prof_json = [x for ev in profile if isinstance(ev, ProfileDeviceEvent) for x in dev_ev_to_perfetto_json(ev)] - for ev in tqdm(profile, desc="preparing profile"): - if isinstance(ev, ProfileRangeEvent): prof_json += range_ev_to_perfetto_json(ev) - elif isinstance(ev, ProfileGraphEvent): prof_json += graph_ev_to_perfetto_json(ev, reccnt=len(prof_json)) - return json.dumps({"traceEvents": prof_json}).encode() if len(prof_json) > 0 else None - -# ** HTTP server - -class Handler(BaseHTTPRequestHandler): - def do_GET(self): - ret, status_code, content_type = b"", 200, "text/html" - - if (fn:={"/":"index", "/profiler":"perfetto"}.get((url:=urlparse(self.path)).path)): - with open(os.path.join(os.path.dirname(__file__), f"{fn}.html"), "rb") as f: ret = f.read() - elif self.path.startswith(("/assets/", "/js/")) and '/..' not in self.path: - try: - with open(os.path.join(os.path.dirname(__file__), self.path.strip('/')), "rb") as f: ret = f.read() - if url.path.endswith(".js"): content_type = "application/javascript" - if url.path.endswith(".css"): content_type = "text/css" - except FileNotFoundError: status_code = 404 - elif url.path == "/ctxs": - if "ctx" in (query:=parse_qs(url.query)): - kidx, ridx = int(query["ctx"][0]), int(query["idx"][0]) - try: - # stream details - self.send_response(200) - self.send_header("Content-Type", "text/event-stream") - self.send_header("Cache-Control", "no-cache") - self.end_headers() - for r in get_details(contexts[1][kidx][ridx]): - self.wfile.write(f"data: {json.dumps(r)}\n\n".encode("utf-8")) - self.wfile.flush() - self.wfile.write("data: END\n\n".encode("utf-8")) - return self.wfile.flush() - # pass if client closed connection - except (BrokenPipeError, ConnectionResetError): return - ret, content_type = json.dumps(ctxs).encode(), "application/json" - elif url.path == "/get_profile" and perfetto_profile is not None: ret, content_type = perfetto_profile, "application/json" - else: status_code = 404 - - # send response - self.send_response(status_code) - self.send_header('Content-Type', content_type) - self.send_header('Content-Length', str(len(ret))) - self.end_headers() - return self.wfile.write(ret) - -# ** main loop - -def reloader(): - mtime = os.stat(__file__).st_mtime - while not stop_reloader.is_set(): - if mtime != os.stat(__file__).st_mtime: - print("reloading server...") - os.execv(sys.executable, [sys.executable] + sys.argv) - time.sleep(0.1) - -def load_pickle(path:str): - if path is None or not os.path.exists(path): return None - with open(path, "rb") as f: return pickle.load(f) - -# NOTE: using HTTPServer forces a potentially slow socket.getfqdn -class TCPServerWithReuse(socketserver.TCPServer): allow_reuse_address = True - -if __name__ == "__main__": - parser = argparse.ArgumentParser() - parser.add_argument('--kernels', type=str, help='Path to kernels', default=None) - parser.add_argument('--profile', type=str, help='Path profile', default=None) - args = parser.parse_args() - - with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: - if s.connect_ex(((HOST:="http://127.0.0.1").replace("http://", ""), PORT:=getenv("PORT", 8000))) == 0: - raise RuntimeError(f"{HOST}:{PORT} is occupied! use PORT= to change.") - stop_reloader = threading.Event() - multiprocessing.current_process().name = "VizProcess" # disallow opening of devices - st = time.perf_counter() - print("*** viz is starting") - - contexts, profile = load_pickle(args.kernels), load_pickle(args.profile) - - # NOTE: this context is a tuple of list[keys] and list[values] - ctxs = get_metadata(*contexts) if contexts is not None else [] - - perfetto_profile = to_perfetto(profile) if profile is not None else None - - server = TCPServerWithReuse(('', PORT), Handler) - reloader_thread = threading.Thread(target=reloader) - reloader_thread.start() - print(f"*** started viz on {HOST}:{PORT}") - print(colored(f"*** ready in {(time.perf_counter()-st)*1e3:4.2f}ms", "green"), flush=True) - if len(getenv("BROWSER", "")) > 0: webbrowser.open(f"{HOST}:{PORT}{'/profiler' if contexts is None else ''}") - try: server.serve_forever() - except KeyboardInterrupt: - print("*** viz is shutting down...") - stop_reloader.set() diff --git a/tinyturing/.envrc b/tinyturing/.envrc deleted file mode 100644 index 3550a30f..00000000 --- a/tinyturing/.envrc +++ /dev/null @@ -1 +0,0 @@ -use flake diff --git a/tinyturing/.gitignore b/tinyturing/.gitignore deleted file mode 100644 index a6ed128e..00000000 --- a/tinyturing/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -.direnv/ -__pycache__/ -result diff --git a/tinyturing/README.md b/tinyturing/README.md deleted file mode 100644 index 5f7542f9..00000000 --- a/tinyturing/README.md +++ /dev/null @@ -1 +0,0 @@ -A high performance driver for the 5" Turing Smart Screen diff --git a/tinyturing/default.nix b/tinyturing/default.nix deleted file mode 100644 index 0576cd6c..00000000 --- a/tinyturing/default.nix +++ /dev/null @@ -1,29 +0,0 @@ -{ - buildPythonPackage, - numba, - numpy, - pyserial, - pillow, - setuptools, - wheel, -}: -buildPythonPackage { - pname = "tinyturing"; - version = "0.1.0"; - pyproject = true; - src = ./.; - - nativeBuildInputs = [ - setuptools - wheel - ]; - - propagatedBuildInputs = [ - numba - numpy - pyserial - pillow - ]; - - pythonImportsCheck = [ "tinyturing" ]; -} diff --git a/tinyturing/examples/camera.py b/tinyturing/examples/camera.py deleted file mode 100644 index 01d4cc79..00000000 --- a/tinyturing/examples/camera.py +++ /dev/null @@ -1,28 +0,0 @@ -import logging, time -logging.basicConfig(level=logging.INFO) - -from tinyturing.display import Display, WIDTH, HEIGHT -import cv2 - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -video = cv2.VideoCapture(1) - -while True: - st = time.perf_counter() - display.clear() - - ret, frame = video.read() - frame = cv2.resize(frame, (160, 90)) - frame = cv2.cvtColor(frame, cv2.COLOR_BGR2RGB) - - np_frame = frame.transpose(1, 0, 2) - display.blit(np_frame, ((WIDTH - frame.shape[1]) // 2, (HEIGHT - frame.shape[0]) // 2)) - - display.flip() - flip_time = time.perf_counter() - st - - if (sleep_time := 0.03 - flip_time) > 0: time.sleep(sleep_time) diff --git a/tinyturing/examples/docs_qr.png b/tinyturing/examples/docs_qr.png deleted file mode 100644 index 847cfc46..00000000 Binary files a/tinyturing/examples/docs_qr.png and /dev/null differ diff --git a/tinyturing/examples/font.py b/tinyturing/examples/font.py deleted file mode 100644 index 6b9c0366..00000000 --- a/tinyturing/examples/font.py +++ /dev/null @@ -1,28 +0,0 @@ -import logging, time -logging.basicConfig(level=logging.INFO) - -from tinyturing.display import Display, WIDTH - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -style = "sans" -while True: - display.clear() - text = display.text(" !\"#$%&'()*+,-./012", style=style) - display.blit(text, ((WIDTH - text.shape[0]) // 2, (text.shape[1] // 2) - 72 * 0)) - text = display.text("3456789:;<=>?@ABCDE", style=style) - display.blit(text, ((WIDTH - text.shape[0]) // 2, (text.shape[1] // 2) + 72 * 1)) - text = display.text("FGHIJKLMNOPQRSTUVWX", style=style) - display.blit(text, ((WIDTH - text.shape[0]) // 2, (text.shape[1] // 2) + 72 * 2)) - text = display.text("YZ[\\]^_`abcdefghijk", style=style) - display.blit(text, ((WIDTH - text.shape[0]) // 2, (text.shape[1] // 2) + 72 * 3)) - text = display.text("lmnopqrstuvwxyz{|}~", style=style) - display.blit(text, ((WIDTH - text.shape[0]) // 2, (text.shape[1] // 2) + 72 * 4)) - display.flip() - - if input() == "q": break - if style == "sans": style = "mono" - else: style = "sans" diff --git a/tinyturing/examples/logo.png b/tinyturing/examples/logo.png deleted file mode 100644 index 47ab6641..00000000 Binary files a/tinyturing/examples/logo.png and /dev/null differ diff --git a/tinyturing/examples/physics.py b/tinyturing/examples/physics.py deleted file mode 100644 index da7be4bb..00000000 --- a/tinyturing/examples/physics.py +++ /dev/null @@ -1,59 +0,0 @@ -from tinyturing.display import Display, WIDTH, HEIGHT -from PIL import Image -import numpy as np -import logging, time, math, random -from pathlib import Path -import pymunk -logging.basicConfig(level=logging.INFO) - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -space = pymunk.Space() -space.gravity = 0, 981 - -tracked_logos = [] -def spawn_logo(): - logo = Image.open(Path(__file__).parent / "logo.png").convert("RGBA") - logo = logo.resize((50, 19)) - logo_body = pymunk.Body(1, pymunk.moment_for_box(1, logo.size)) - logo_shape = pymunk.Poly.create_box(logo_body, logo.size) - logo_shape.friction = 0.5 - logo_body.position = WIDTH // 4, random.randint(-HEIGHT, 0) - space.add(logo_body, logo_shape) - tracked_logos.append((logo, logo_body)) - -floor = Image.new("RGBA", (WIDTH, 10), (255, 255, 255, 255)) -floor_body = pymunk.Body(body_type=pymunk.Body.STATIC) -floor_shape = pymunk.Poly.create_box(floor_body, (WIDTH, 10)) -floor_shape.friction = 0.5 -floor_body.position = 0, HEIGHT - 5 -space.add(floor_body, floor_shape) - -for i in range(150): - spawn_logo() - -while True: - st = time.perf_counter() - display.clear() - - space.step(0.01) - - for logo, logo_body in tracked_logos: - if logo_body.position.y > HEIGHT + 200: - logo_body.position = WIDTH // 4, 0 - logo_body.velocity = 0, 0 - - logo_rotated = logo.rotate(-math.degrees(logo_body.angle), resample=Image.BICUBIC, expand=True) - np_logo = np.array(logo_rotated).transpose(1, 0, 2) - display.blit(np_logo, (int(logo_body.position.x) - logo_rotated.size[0] // 2, int(logo_body.position.y) - logo_rotated.size[1] // 2)) - - np_floor = np.array(floor).transpose(1, 0, 2) - display.blit(np_floor, (int(floor_body.position.x) - WIDTH // 2, int(floor_body.position.y) - 5)) - - display.flip() - flip_time = time.perf_counter() - st - - if (sleep_time := 0.05 - flip_time) > 0: time.sleep(sleep_time) diff --git a/tinyturing/examples/scrolling_text.py b/tinyturing/examples/scrolling_text.py deleted file mode 100644 index 20178730..00000000 --- a/tinyturing/examples/scrolling_text.py +++ /dev/null @@ -1,24 +0,0 @@ -import logging, time -logging.basicConfig(level=logging.INFO) - -from pathlib import Path - -from tinyturing.display import Display, WIDTH, HEIGHT -from tinyturing.components import Anchor, ComponentParent -from tinyturing.components import AnimatedText - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -display.clear() - -text = AnimatedText(["aaa\nbbb\nccc", "bbb\nccc\naaa", "ccc\naaa\nbbb"], "sans", x=WIDTH // 2, y=HEIGHT // 2, anchor=Anchor.MIDDLE_CENTER) - -while True: - display.clear() - text.blit(display) - display.flip() - - time.sleep(0.1) diff --git a/tinyturing/examples/sleep.py b/tinyturing/examples/sleep.py deleted file mode 100644 index 9b3e05ba..00000000 --- a/tinyturing/examples/sleep.py +++ /dev/null @@ -1,72 +0,0 @@ -import logging, time, random, math, subprocess -logging.basicConfig(level=logging.INFO) - -from pathlib import Path - -from tinyturing.display import Display, WIDTH, HEIGHT -from tinyturing.components import Anchor, ComponentParent, Component -from tinyturing.components import Text, MultiCollidingDVDImage, HorizontalProgressBar, VerticalProgressBar, Rectangle, LineGraph - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -display.clear() - -class SleepScreen(Component): - def __init__(self): - # read bmc password from /root/.bmc_password - # if os.path.exists("/root/.bmc_password"): - # try: - # with open("/root/.bmc_password", "r") as f: - # bmc_password = f.read().strip().split("=")[1].strip() - # self.bmc_password = Text(bmc_password, "mono", y=HEIGHT, anchor=Anchor.BOTTOM_CENTER) - # try: subprocess.run(["ipmitool", "user", "set", "password", "2", bmc_password]) - # except: logging.warning("Failed to set BMC password") - # except: logging.warning("Failed to read BMC password") - # else: logging.warning("BMC password file not found") - self.bmc_password = Text("BMC PW: Tq3j11enlGpm", "mono", x=WIDTH//2, y=HEIGHT, anchor=Anchor.BOTTOM_CENTER) - - # bmc ip - # bmc_lan_info = subprocess.run(["ipmitool", "lan", "print"], capture_output=True).stdout.decode().split("\n") - # bmc_ip = next((line.split()[3] for line in bmc_lan_info if "IP Address " in line), "N/A") - bmc_ip = "192.168.52.220" - - if hasattr(self, "bmc_password"): self.bmc_ip = Text(f"BMC: {bmc_ip}", "mono", anchor=Anchor.BOTTOM_CENTER, parent=ComponentParent(self.bmc_password, Anchor.TOP_CENTER)) - else: self.bmc_ip = Text(f"BMC: {bmc_ip}", "mono", x=WIDTH//2, y=HEIGHT, anchor=Anchor.BOTTOM_CENTER) - - # ip - # ip = subprocess.run(["hostname", "-I"], capture_output=True).stdout.decode().strip() - # ip = ip.split(" ")[0] if ip else "N/A" - ip = "192.168.52.22" - - self.ip = Text(f"IP: {ip}", "mono", anchor=Anchor.BOTTOM_CENTER, parent=ComponentParent(self.bmc_ip, Anchor.TOP_CENTER)) - - # seperator line - self.line = Rectangle(WIDTH - WIDTH // 5, 1, y=-8, anchor=Anchor.BOTTOM_CENTER, parent=ComponentParent(self.ip, Anchor.TOP_CENTER)) - - # bouncing logo - offset = -2 if hasattr(self, "bmc_password") else 62 - self.logo = MultiCollidingDVDImage([ - Path(__file__).parent / "logo.png", - ], [ - (400, 154), - ], width=WIDTH, height=HEIGHT - (196 - offset), y=offset) - - def blit(self, display:Display): - self.logo.blit(display) - if hasattr(self, "bmc_password"): - self.bmc_password.blit(display) - self.bmc_ip.blit(display) - self.ip.blit(display) - self.line.blit(display) - -screen = SleepScreen() - -while True: - display.clear() - screen.blit(display) - display.flip() - - time.sleep(0.01) diff --git a/tinyturing/examples/status.py b/tinyturing/examples/status.py deleted file mode 100644 index c582c6ae..00000000 --- a/tinyturing/examples/status.py +++ /dev/null @@ -1,76 +0,0 @@ -import logging, time, random, math -logging.basicConfig(level=logging.INFO) - -from pathlib import Path - -from tinyturing.display import Display, WIDTH, HEIGHT -from tinyturing.components import Anchor, ComponentParent, Component -from tinyturing.components import Text, HorizontalProgressBar, VerticalProgressBar, Rectangle, LineGraph - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -display.clear() - -class StatusScreen(Component): - def __init__(self, gpu_count:int): - gpu_bars_space = (6 - gpu_count) * 64 - self.gpu_bars = [VerticalProgressBar(50, 430, x=30 + 64 * i, y=HEIGHT // 2) for i in range(gpu_count)] - self.gpu_mem_bars = [HorizontalProgressBar(160, 5, x=425 - gpu_bars_space, y=100 + 7 * i, anchor=Anchor.MIDDLE_LEFT) for i in range(gpu_count)] - self.gpu_mem_bar_backgrounds = [Rectangle(160, 5, color=0x323232ff, x=425 - gpu_bars_space, y=100 + 7 * i, anchor=Anchor.MIDDLE_LEFT) for i in range(gpu_count)] - - self.vertical_separator = Rectangle(1, 280, x=WIDTH // 2 - gpu_bars_space, y=HEIGHT // 2) - self.horizontal_separator = Rectangle(280 + gpu_bars_space, 1, x=WIDTH // 2 + WIDTH // 4 - gpu_bars_space // 2, y=HEIGHT // 2) - - bar_width = (6 - gpu_count) + 2 - self.cpu_bars = [VerticalProgressBar(bar_width, 117, x=604 + (bar_width + 1) * i - gpu_bars_space, y=84) for i in range(64)] - - self.rolling_power_draw = 0 - self.power_draw_text = Text("0W", style="mono", x=425 - gpu_bars_space, y=57, anchor=Anchor.MIDDLE_LEFT) - self.rolling_disk_io = 0 - self.disk_io_text = Text("0MB/s", style="mono", x=WIDTH - 5, y=190, anchor=Anchor.MIDDLE_RIGHT) - - self.line_graph = LineGraph(370 + gpu_bars_space, 190, x=610 - gpu_bars_space // 2, y=360) - - def update(self, gpu_utilizations: list[float], gpu_memory_utilizations: list[float], cpu_utilizations: list[float], gpu_power_draws: list[float], cpu_power_draw: float, disk_io: tuple[int, int]): - for i, bar in enumerate(self.gpu_bars): bar.value = gpu_utilizations[i] - for i, bar in enumerate(self.gpu_mem_bars): bar.value = gpu_memory_utilizations[i] - for i, bar in enumerate(self.cpu_bars): bar.value = cpu_utilizations[i] - - self.rolling_power_draw = math.floor(0.8 * self.rolling_power_draw + 0.2 * sum(gpu_power_draws, cpu_power_draw)) - self.power_draw_text.text = f"{self.rolling_power_draw}W" - - self.rolling_disk_io = math.floor(0.8 * self.rolling_disk_io + 0.2 * sum(disk_io)) - self.disk_io_text.text = f"{self.rolling_disk_io}MB/s" - - self.line_graph.add_data(self.rolling_power_draw) - - def blit(self, display:Display): - for bar in self.gpu_bars: bar.blit(display) - for bar in self.gpu_mem_bar_backgrounds: bar.blit(display) - for bar in self.gpu_mem_bars: bar.blit(display) - self.vertical_separator.blit(display) - self.horizontal_separator.blit(display) - for bar in self.cpu_bars: bar.blit(display) - self.power_draw_text.blit(display) - self.disk_io_text.blit(display) - self.line_graph.blit(display) - -status_screen = StatusScreen(4) - -while True: - display.clear() - status_screen.update( - [random.uniform(50, 100) for _ in range(6)], - [random.uniform(50, 100) for _ in range(6)], - [random.uniform(90, 100) for _ in range(64)], - [random.uniform(50, 450) for _ in range(6)], - random.uniform(50, 300), - (random.randint(0, 10000), random.randint(0, 10000)) - ) - status_screen.blit(display) - display.flip() - - time.sleep(0.01) diff --git a/tinyturing/examples/welcome.py b/tinyturing/examples/welcome.py deleted file mode 100644 index 5d4a7b7c..00000000 --- a/tinyturing/examples/welcome.py +++ /dev/null @@ -1,34 +0,0 @@ -import logging -logging.basicConfig(level=logging.INFO) - -from pathlib import Path - -from tinyturing.display import Display, HEIGHT -from tinyturing.components import Anchor, Component, ComponentParent -from tinyturing.components import Image, Text - -# initialize -display = Display() -display.clear() -display.flip(force=True) - -display.clear() - -class WelcomeScreen(Component): - def __init__(self): - self.qr = Image(Path(__file__).parent / "docs_qr.png", (300, 300), y=HEIGHT // 2, anchor=Anchor.MIDDLE_LEFT) - self.desc1 = Text("Scan for Docs", "sans", anchor=Anchor.TOP_LEFT, parent=ComponentParent(self.qr, Anchor.TOP_RIGHT)) - self.bmc_password = Text("", "mono", anchor=Anchor.BOTTOM_LEFT, parent=ComponentParent(self.qr, Anchor.BOTTOM_RIGHT)) - self.bmc_ip = Text("", "mono", anchor=Anchor.BOTTOM_LEFT, parent=ComponentParent(self.bmc_password, Anchor.TOP_LEFT)) - self.desc2 = Text("BMC IP & Passwd", "sans", anchor=Anchor.BOTTOM_LEFT, parent=ComponentParent(self.bmc_ip, Anchor.TOP_LEFT)) - - def blit(self, display:Display): - self.qr.blit(display) - self.desc1.blit(display) - self.bmc_password.blit(display) - self.bmc_ip.blit(display) - self.desc2.blit(display) - -screen = WelcomeScreen() -screen.blit(display) -display.flip() diff --git a/tinyturing/extra/convert_font.py b/tinyturing/extra/convert_font.py deleted file mode 100644 index e2e4276f..00000000 --- a/tinyturing/extra/convert_font.py +++ /dev/null @@ -1,43 +0,0 @@ -# Use https://stmn.github.io/font2bitmap/ to convert a font to a bitmap then feed it to this script to convert it into the format that the display driver is expecting. - -import sys - -from PIL import Image -import numpy as np - -# font is 32x64 -# grid is 19x5 -font_grid = Image.open(sys.argv[1]) -# convert to 8bpp grayscale -font_grid = font_grid.convert("LA") - -font_grid_order = " !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~" -# sort by ascii -corrected_font_grid_order = sorted(font_grid_order, key=lambda x: ord(x)) -# get the index of each char in corrected_font_grid_order -corrected_index = [font_grid_order.index(char) for char in corrected_font_grid_order] - -# we want to convert it to a binary array of 95x32x64 -chars = [] -for y in range(5): - for x in range(19): - char = font_grid.crop((x * 32, y * 64, (x + 1) * 32, (y + 1) * 64)) - # numpy array - char = np.array(char)[:, :, 1] - chars.append(char) - - # print - for i in range(64): - for j in range(32): - if not char[i, j]: print(" ", end="") - else: - print("#", end="") - print() - -# reorder chars to match corrected_font_grid_order -chars = [chars[i] for i in corrected_index] - -# save -chars = np.array(chars) -print(chars.shape) -np.save(sys.argv[2], chars) diff --git a/tinyturing/flake.lock b/tinyturing/flake.lock deleted file mode 100644 index 6ab0e3cc..00000000 --- a/tinyturing/flake.lock +++ /dev/null @@ -1,61 +0,0 @@ -{ - "nodes": { - "flake-utils": { - "inputs": { - "systems": "systems" - }, - "locked": { - "lastModified": 1710146030, - "narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=", - "owner": "numtide", - "repo": "flake-utils", - "rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a", - "type": "github" - }, - "original": { - "owner": "numtide", - "repo": "flake-utils", - "type": "github" - } - }, - "nixpkgs": { - "locked": { - "lastModified": 1714562304, - "narHash": "sha256-Mr3U37Rh6tH0FbaDFu0aZDwk9mPAe7ASaqDOGgLqqLU=", - "owner": "nixos", - "repo": "nixpkgs", - "rev": "bcd44e224fd68ce7d269b4f44d24c2220fd821e7", - "type": "github" - }, - "original": { - "owner": "nixos", - "ref": "nixpkgs-unstable", - "repo": "nixpkgs", - "type": "github" - } - }, - "root": { - "inputs": { - "flake-utils": "flake-utils", - "nixpkgs": "nixpkgs" - } - }, - "systems": { - "locked": { - "lastModified": 1681028828, - "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", - "owner": "nix-systems", - "repo": "default", - "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", - "type": "github" - }, - "original": { - "owner": "nix-systems", - "repo": "default", - "type": "github" - } - } - }, - "root": "root", - "version": 7 -} diff --git a/tinyturing/flake.nix b/tinyturing/flake.nix deleted file mode 100644 index 6676e5e4..00000000 --- a/tinyturing/flake.nix +++ /dev/null @@ -1,60 +0,0 @@ -{ - description = "python turing usb display driver"; - - inputs.nixpkgs.url = "github:nixos/nixpkgs/nixpkgs-unstable"; - inputs.flake-utils.url = "github:numtide/flake-utils"; - - outputs = - { - nixpkgs, - flake-utils, - ... - }: - let - overlay = final: prev: { - pythonPackagesExtensions = prev.pythonPackagesExtensions ++ [ - (python-final: python-prev: { - tinyturing = python-final.callPackage ./default.nix { }; - }) - ]; - }; - in - flake-utils.lib.eachDefaultSystem ( - system: - let - pkgs = import nixpkgs { - inherit system; - overlays = [ overlay ]; - }; - in - { - devShells.default = pkgs.mkShell { - nativeBuildInputs = - with pkgs; - let - pythonWithPackages = python3.withPackages ( - p: with p; [ - pyserial - pillow - numpy - numba - opencv4 - pymunk - bdffont - pillow - ] - ); - in - [ - pythonWithPackages - usb-reset - ]; - }; - - packages.default = pkgs.python3Packages.tinyturing; - } - ) - // { - overlays.default = overlay; - }; -} diff --git a/tinyturing/pyproject.toml b/tinyturing/pyproject.toml deleted file mode 100644 index 6e929a0d..00000000 --- a/tinyturing/pyproject.toml +++ /dev/null @@ -1,12 +0,0 @@ -[build-system] -requires = ["setuptools", "wheel"] - -[project] -name = "tinyturing" -version = "0.1.0" - -[tool.setuptools] -packages = ["tinyturing"] - -[tool.setuptools.package-data] -tinyturing = ["*.npy"] diff --git a/tinyturing/tinyturing/components.py b/tinyturing/tinyturing/components.py deleted file mode 100644 index ee8243c6..00000000 --- a/tinyturing/tinyturing/components.py +++ /dev/null @@ -1,290 +0,0 @@ -from enum import Enum -from dataclasses import dataclass -from pathlib import Path -import random, logging - -import numpy as np -import PIL.Image -from numba import njit - -from tinyturing.display import Display - -class Anchor(Enum): - """An enum to represent the anchor points of a component.""" - TOP_LEFT = 0 - TOP_CENTER = 1 - TOP_RIGHT = 2 - MIDDLE_LEFT = 3 - MIDDLE_CENTER = 4 - MIDDLE_RIGHT = 5 - BOTTOM_LEFT = 6 - BOTTOM_CENTER = 7 - BOTTOM_RIGHT = 8 - - def offset(self, component): - """ - Return the offset of the anchor point for the given component. - """ - if self == Anchor.TOP_LEFT: return 0, 0 - elif self == Anchor.TOP_CENTER: return -component.width // 2, 0 - elif self == Anchor.TOP_RIGHT: return -component.width, 0 - elif self == Anchor.MIDDLE_LEFT: return 0, -component.height // 2 - elif self == Anchor.MIDDLE_CENTER: return -component.width // 2, -component.height // 2 - elif self == Anchor.MIDDLE_RIGHT: return -component.width, -component.height // 2 - elif self == Anchor.BOTTOM_LEFT: return 0, -component.height - elif self == Anchor.BOTTOM_CENTER: return -component.width // 2, -component.height - elif self == Anchor.BOTTOM_RIGHT: return -component.width, -component.height - else: raise ValueError(f"Unknown anchor: {self}") - -class Component: - """ - A base class for all components. - """ - def __init__(self, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - self.anchor: Anchor = anchor - self.parent: ComponentParent | None = parent - - self.x, self.y = x, y - self.width: int = 0 - self.height: int = 0 - - def _pre_blit(self, display:Display): pass - def blit(self, display:Display): - """ - Draw the component to the display. - """ - self._pre_blit(display) - x, y = self.x, self.y - - # first calculate x and y - # if we have a parent we draw relative to it - if self.parent is not None: - parent = self.parent - while parent is not None: - x += parent.component.x - y += parent.component.y - offset = parent.component.anchor.offset(parent.component) - x += offset[0] - y += offset[1] - offset = parent.anchor.offset(parent.component) - x -= offset[0] - y -= offset[1] - parent = parent.component.parent - - # add anchor offset - offset = self.anchor.offset(self) - x += offset[0] - y += offset[1] - - # finally draw - self._blit(display, x, y) - def _blit(self, display:Display, x:int, y:int): raise NotImplementedError() - -@dataclass(frozen=True) -class ComponentParent: - """ - A dataclass to represent a parent pointer along with where it's child anchor point should be. - """ - component: Component - anchor: Anchor - -class SimpleComponent(Component): - """ - A simple component with a single blittable surface. - """ - def __init__(self, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self.surface = None - - def _draw(self, display:Display): raise NotImplementedError() - def _pre_blit(self, display:Display): - self.surface = self._draw(display) - self.width, self.height = self.surface.shape[0], self.surface.shape[1] - def _blit(self, display: Display, x:int, y:int): - display.blit(self.surface, (x, y)) - -class Text(SimpleComponent): - """ - A component that represents text. - """ - def __init__(self, text:str, style:str, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self.text: str = text - self.style: str = style - - def _draw(self, display:Display): - return display.text(self.text, style=self.style) - -class AnimatedText(SimpleComponent): - """ - A component that cycles through a list of texts. - """ - def __init__(self, texts:list[str], style:str, bounce=False, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self.texts: list[str] = texts - self.style: str = style - self.bounce, self.dir = bounce, -1 - self.index = -1 # this gets incremented on the first draw - - def _draw(self, display:Display): - self.index = (self.index + self.dir) % len(self.texts) - if self.bounce and (self.index == 0 or self.index == len(self.texts) - 1): self.dir *= -1 - return display.text(self.texts[self.index], style=self.style) - -class Image(SimpleComponent): - """ - A component that represents an image. - """ - def __init__(self, path:str|Path, size:tuple[int, int], rotation:float=0, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self.image = PIL.Image.open(path).convert("RGBA").resize(size) - self.rotation = rotation - - def _draw(self, display:Display): - image = self.image - if self.rotation != 0: image = image.rotate(self.rotation, resample=PIL.Image.BICUBIC, expand=True) - return np.array(image).transpose(1, 0, 2) - -class DVDImage(SimpleComponent): - """ - A component that represents a bouncing DVD logo. - """ - def __init__(self, path:str|Path, size:tuple[int, int], x:int=0, y:int=0): - super().__init__(x, y, Anchor.TOP_LEFT, None) - self.image = np.array(PIL.Image.open(path).convert("RGBA").resize(size)).transpose(1, 0, 2) - self.dx, self.dy = 1, 1 - - def _draw(self, display:Display): - self.x += self.dx - self.y += self.dy - if self.x < 0 or self.x + self.image.shape[0] >= display.width: self.dx *= -1 - if self.y < 0 or self.y + self.image.shape[1] >= display.height: self.dy *= -1 - return self.image - -class MultiCollidingDVDImage(Component): - """ - A component that represents multiple bouncing DVD logos that can collide with each other. - """ - def __init__(self, paths:list[str|Path], sizes:list[tuple[int, int]], width:int, height:int, x:int=0, y:int=0): - super().__init__(0, 0, Anchor.TOP_LEFT, None) - self.width, self.height, self.x, self.y = width, height, x, y - self.images = [np.array(PIL.Image.open(path).convert("RGBA").resize(size)).transpose(1, 0, 2) for path, size in zip(paths, sizes)] - # cache unique pairs that we need to check for collision - self.pairs = [(i, j) for i in range(len(self.images)) for j in range(i + 1, len(self.images))] - self.dx, self.dy = [random.choice([-1, 1]) for _ in self.images], [random.choice([-1, 1]) for _ in self.images] - # start at random positions that don't overlap - self.xs, self.ys = [], [] - random_calls = 0 - for image in self.images: - x, y = random.randint(0, width - image.shape[0]), random.randint(0, height - image.shape[1]) - random_calls += 1 - while any(x < xs + image.shape[0] and x + image.shape[0] > xs and y < ys + image.shape[1] and y + image.shape[1] > ys for xs, ys in zip(self.xs, self.ys)): - x, y = random.randint(0, width - image.shape[0]), random.randint(0, height - image.shape[1]) - random_calls += 1 - self.xs.append(x) - self.ys.append(y) - logging.info(f"needed {random_calls} random calls to find non-overlapping positions") - - def blit(self, display:Display): - # calculate new position and edge bounce - for i, image in enumerate(self.images): - self.xs[i] += self.dx[i] - self.ys[i] += self.dy[i] - if self.xs[i] < 0 or self.xs[i] + image.shape[0] >= self.width: self.dx[i] *= -1 - if self.ys[i] < 0 or self.ys[i] + image.shape[1] >= self.height: self.dy[i] *= -1 - - # calculate collision - for i, j in self.pairs: - if self.xs[i] < self.xs[j] + self.images[j].shape[0] and self.xs[i] + self.images[i].shape[0] > self.xs[j] and self.ys[i] < self.ys[j] + self.images[j].shape[1] and self.ys[i] + self.images[i].shape[1] > self.ys[j]: - self.dx[i], self.dx[j] = self.dx[j], self.dx[i] - self.dy[i], self.dy[j] = self.dy[j], self.dy[i] - - # blit - for i, image in enumerate(self.images): - display.blit(image, (self.xs[i] + self.x, self.ys[i] + self.y)) - -class Rectangle(SimpleComponent): - """ - A component that represents a rectangle. - """ - def __init__(self, width:int, height:int, color:int=0xffffffff, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self._width, self._height = width, height - self.color = color - - def _draw(self, display:Display): - return np.full((self._width, self._height), self.color, dtype=np.uint32) - -class VerticalProgressBar(SimpleComponent): - """ - A component that represents a vertical progress bar. - """ - def __init__(self, width:int, height:int, value:float=0, max_value:float=100, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self._width, self._height = width, height - self.value, self.max_value = value, max_value - - def _draw(self, display:Display): - filled = int(self._height * self.value // self.max_value) - return np.full((self._width, filled), 0xffffffff, dtype=np.uint32) - -class HorizontalProgressBar(SimpleComponent): - """ - A component that represents a horizontal progress bar. - """ - def __init__(self, width:int, height:int, value:float=0, max_value:float=100, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self._width, self._height = width, height - self.value, self.max_value = value, max_value - - def _draw(self, display:Display): - filled = int(self._width * self.value // self.max_value) - return np.full((filled, self._height), 0xffffffff, dtype=np.uint32) - -@njit -def _line(x1: int, y1: int, x2: int, y2: int) -> list[tuple[int, int]]: - points = [] - dx, dy = abs(x2 - x1), abs(y2 - y1) - sx, sy = 1 if x1 < x2 else -1, 1 if y1 < y2 else -1 - err = dx - dy - while True: - points.append((x1, y1)) - if x1 == x2 and y1 == y2: break - e2 = 2 * err - if e2 > -dy: - err -= dy - x1 += sx - if e2 < dx: - err += dx - y1 += sy - return points - -class LineGraph(SimpleComponent): - """ - A component that represents a scrolling line graph. - """ - def __init__(self, width:int, height:int, max_points:int=20, x:int=0, y:int=0, anchor=Anchor.MIDDLE_CENTER, parent=None): - super().__init__(x, y, anchor, parent) - self._width, self._height = width, height - self.max_points, self.data = max_points, [] - - def add_data(self, point: float): - self.data.append(point) - if len(self.data) > self.max_points: self.data.pop(0) - - def _draw(self, display:Display): - min_data, max_data = min(self.data), max(self.data) - data_range = max_data - min_data - if data_range == 0: data_range = 1 - surface = np.zeros((self._width, self._height), dtype=np.uint32) - if len(self.data) < 2: return surface - for i in range(len(self.data) - 1): - x1, y1 = int(self._width * i / (self.max_points - 1)), self._height - int(self._height * (self.data[i] - min_data) / data_range) - x2, y2 = int(self._width * (i + 1) / (self.max_points - 1)), self._height - int(self._height * (self.data[i + 1] - min_data) / data_range) - # draw line - for point in _line(x1, y1, x2, y2): - # clamp point to graph bounds - point = (max(0, min(self._width - 1, point[0])), max(0, min(self.height - 1, point[1]))) - surface[point[0], point[1]] = 0xffffffff - return surface - diff --git a/tinyturing/tinyturing/display.py b/tinyturing/tinyturing/display.py deleted file mode 100644 index b58155af..00000000 --- a/tinyturing/tinyturing/display.py +++ /dev/null @@ -1,231 +0,0 @@ -import math, subprocess, time, logging -from pathlib import Path -import serial -from serial.tools.list_ports import comports -import numpy as np -from numba import njit - -# commands -HELLO = bytearray([0x01, 0xef, 0x69, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc5, 0xd3]) -OPTIONS = bytearray([0x7d, 0xef, 0x69, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2d]) -SET_BRIGHTNESS = bytearray([0x7b, 0xef, 0x69, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00]) -PRE_UPDATE_BITMAP = bytearray([0x86, 0xef, 0x69, 0x00, 0x00, 0x00, 0x01]) -START_DISPLAY_BITMAP = bytearray([0x2c]) -DISPLAY_BITMAP = bytearray([0xc8, 0xef, 0x69, 0x00, 0x17, 0x70]) -UPDATE_BITMAP = bytes([0xcc, 0xef, 0x69]) -QUERY_STATUS = bytearray([0xcf, 0xef, 0x69, 0x00, 0x00, 0x00, 0x01]) - -WIDTH, HEIGHT = 800, 480 -class Display: - def __init__(self, brightness:int=0xff): - self._connect() - - # initialize display - self.send_command(HELLO) - logging.debug(self.lcd.read(22)) - self.send_command(OPTIONS, bytearray([0x00, 0x00, 0x00, 0x00])) - self.send_command(SET_BRIGHTNESS, bytearray([brightness])) - - self.width, self.height = WIDTH, HEIGHT - - self.font = np.load(Path(__file__).parent / "font.npy") - self.font_mono = np.load(Path(__file__).parent / "font_mono.npy") - self.framebuffer = np.full((WIDTH, HEIGHT), 0xff, dtype=np.uint32) - self.old_framebuffer = self.framebuffer.copy() - self.update_buffer = np.zeros(self.framebuffer.size * self.framebuffer.itemsize * 2, dtype=np.uint8) - self.partial_update_count = 0 - - def __del__(self): - if hasattr(self, "lcd"): - self.lcd.close() - - def _connect(self): - # auto detect com port - for port in comports(): - if port.serial_number == "20080411": - logging.info(f"Found display at {port.device}") - break - else: - logging.error("Display not found") - raise RuntimeError("Display not found") - self.lcd = serial.Serial(port.device, 1825200 * 2, timeout=1, write_timeout=1) - - def send_command(self, command, payload=None): - logging.debug(f"Sending command {command}") - command = command.copy() if command != bytearray([0xff]) else bytearray() - if payload is not None: command += payload - padding = 0 if command[0] != 0x2c else 0x2c - if not ((cmd_len:=len(command)) / 250).is_integer(): command += bytearray([padding] * (250 * math.ceil(cmd_len / 250) - cmd_len)) - try: self.lcd.write(command) - except serial.SerialTimeoutException: - logging.warning("Serial write timeout, resetting usb device and retrying") - self.lcd.close() - subprocess.run(["usbreset", "1d6b:0106"]) - logging.warning("Waiting 2 seconds for usb device to reset") - time.sleep(2) - self._connect() - self.lcd.write(command) - - def text(self, text, style="sans"): - if style == "sans": return _blit_text(text, self.font) - elif style == "mono": return _blit_text(text, self.font_mono) - else: raise ValueError("Invalid style") - def clear(self): - self.old_framebuffer = self.framebuffer.copy() - self.framebuffer.fill(0xff) - def blit(self, source, dest=(0, 0)): - if source.ndim == 3: - # check if alpha channel is present - if source.shape[2] == 4: - source = (source[:, :, 0].astype(np.uint32) << 24) | (source[:, :, 1].astype(np.uint32) << 16) | (source[:, :, 2].astype(np.uint32) << 8) | (source[:, :, 3].astype(np.uint32) & 0xff) - else: - source = (source[:, :, 0].astype(np.uint32) << 24) | (source[:, :, 1].astype(np.uint32) << 16) | (source[:, :, 2].astype(np.uint32) << 8) | 0xff - # clip source to framebuffer - if dest[0] >= self.framebuffer.shape[0] or dest[1] >= self.framebuffer.shape[1]: return - if dest[0] + source.shape[0] > self.framebuffer.shape[0]: source = source[:self.framebuffer.shape[0] - dest[0]] - if dest[1] + source.shape[1] > self.framebuffer.shape[1]: source = source[:, :self.framebuffer.shape[1] - dest[1]] - if dest[0] < 0: - source = source[-dest[0]:] - dest = (0, dest[1]) - if dest[1] < 0: - source = source[:, -dest[1]:] - dest = (dest[0], 0) - # blit with alpha mixing - _blit_alpha(source, dest, self.framebuffer) - - def flip(self, force=False): - dirty = _track_damage(self.old_framebuffer, self.framebuffer) - - if not np.any(dirty) and not force: - logging.debug("Skipping flip because framebuffer is clean") - return - - # check if the whole framebuffer is dirty - if np.all(dirty) or force: - logging.debug("Flipping full framebuffer") - self.send_command(PRE_UPDATE_BITMAP) - self.send_command(START_DISPLAY_BITMAP) - self.send_command(DISPLAY_BITMAP) - framebuffer = self.framebuffer.transpose().tobytes() - self.send_command(bytearray([0xff]), b"\x00".join([framebuffer[i:i+249] for i in range(0, len(framebuffer), 249)])) - logging.debug(f"{self.lcd.read(1024)[:0x20]}") - self.send_command(QUERY_STATUS) - logging.debug(f"{self.lcd.read(1024)[:0x20]}") - else: - logging.debug("Flipping partial framebuffer") - update, payload = _update_payload(dirty, self.framebuffer, self.update_buffer, self.partial_update_count) - self.send_command(bytearray([0xff]), payload) - self.send_command(bytearray([0xff]), update) - self.send_command(QUERY_STATUS) - try: res = self.lcd.read(1024)[:0x20] - except serial.SerialTimeoutException: res = b"" - logging.debug(f"{res}") - if res == b"\x00" or res == b"" or b"Send:1" in res: - logging.warning("Partial update failed, full update required") - self.send_command(PRE_UPDATE_BITMAP) - self.send_command(START_DISPLAY_BITMAP) - self.send_command(DISPLAY_BITMAP) - framebuffer = self.framebuffer.transpose().tobytes() - self.send_command(bytearray([0xff]), b"\x00".join([framebuffer[i:i+249] for i in range(0, len(framebuffer), 249)])) - logging.debug(f"{self.lcd.read(1024)[:0x20]}") - self.send_command(QUERY_STATUS) - logging.debug(f"{self.lcd.read(1024)[:0x20]}") - self.partial_update_count = 0 - else: - self.partial_update_count += 1 - -@njit(cache=True) -def _blit_text(text, font): - # split on newlines - text_chunks = text.split("\n") - # the width is the max width - text_width = max([len(chunk) for chunk in text_chunks]) * 32 - # the height is the number of chunks - text_height = len(text_chunks) * 64 - # create a surface to blit to - text_surface = np.zeros((text_width, text_height), dtype=np.uint32) - # blit each character from the bitmap font - for y, chunk in enumerate(text_chunks): - for i, char in enumerate(chunk): - char_bitmap = font[ord(char) - 32] - text_surface[i*32:(i+1)*32, y*64:(y+1)*64] = 0xffffff00 | char_bitmap.T - return text_surface - -@njit(cache=True) -def _blit_alpha(source, dest, framebuffer): - # extract alpha channel - alpha = source & 0xff - # blend source with framebuffer using alpha channel - source = source & 0xffffff00 - fbuf = framebuffer[dest[0]:dest[0]+source.shape[0], dest[1]:dest[1]+source.shape[1]] & 0xffffff00 - # separate color channels - fbuf_red = (fbuf >> 24) & 0xff - fbuf_green = (fbuf >> 16) & 0xff - fbuf_blue = (fbuf >> 8) & 0xff - source_red = (source >> 24) & 0xff - source_green = (source >> 16) & 0xff - source_blue = (source >> 8) & 0xff - # blend each color channel - fbuf_blend_amount = (0xff - alpha) / 0xff - source_blend_amount = alpha / 0xff - red = (fbuf_red * fbuf_blend_amount + source_red * source_blend_amount).astype(np.uint8) - green = (fbuf_green * fbuf_blend_amount + source_green * source_blend_amount).astype(np.uint8) - blue = (fbuf_blue * fbuf_blend_amount + source_blue * source_blend_amount).astype(np.uint8) - # combine color channels - framebuffer[dest[0]:dest[0]+source.shape[0], dest[1]:dest[1]+source.shape[1]] = (red << 24) | (green << 16) | (blue << 8) - -@njit(cache=True) -def _track_damage(old:np.ndarray, new:np.ndarray): return np.where(old != new, 1, 0).T - -@njit(cache=True) -def _build_update(dirty:np.ndarray, fb, update): - write = 0 - for y in range(HEIGHT): - if not np.any(dirty[y]): continue - - # find all dirty segments - i = 0 - while i < WIDTH: - if dirty[y][i]: - segment_start, segment_length = i, 1 - j = i + 1 - while j < WIDTH and dirty[y][j]: - segment_length += 1 - j += 1 - i = j - - if segment_length > 1: - pos = y * WIDTH + segment_start - update[write] = (pos >> 16) & 0xff - update[write + 1] = (pos >> 8) & 0xff - update[write + 2] = pos & 0xff - update[write + 3] = (segment_length >> 8) & 0xff - update[write + 4] = segment_length & 0xff - write += 5 - for x in range(segment_length): - px = fb[segment_start + x, y] - update[write] = (px >> 8) & 0xff - update[write + 1] = (px >> 16) & 0xff - update[write + 2] = (px >> 24) & 0xff - write += 3 - else: - pos = y * WIDTH + segment_start + 0x800000 - update[write] = (pos >> 16) & 0xff - update[write + 1] = (pos >> 8) & 0xff - update[write + 2] = pos & 0xff - px = fb[segment_start, y] - update[write + 3] = (px >> 8) & 0xff - update[write + 4] = (px >> 16) & 0xff - update[write + 5] = (px >> 24) & 0xff - write += 6 - i += 1 - return update[:write] - -def _update_payload(dirty:np.ndarray, fb, update_buffer, partial_update_count): - update = _build_update(dirty, fb, update_buffer).tobytes() - if len(update) % 249 == 0 or len(update) % 249 == 248 or len(update) % 249 == 247: update = update + b"\x80\x00\x00\x00\x00\x00" - update_size = (len(update) + 2).to_bytes(4, "big") - payload = UPDATE_BITMAP + update_size + b"\x00\x00\x00" + partial_update_count.to_bytes(4, "big") - update_chunks = [] - for i in range(0, len(update), 249): update_chunks.append(update[i:i+249]) - return b"\x00".join(update_chunks) + b"\xef\x69", payload diff --git a/tinyturing/tinyturing/font.npy b/tinyturing/tinyturing/font.npy deleted file mode 100644 index 9cbb3eef..00000000 Binary files a/tinyturing/tinyturing/font.npy and /dev/null differ diff --git a/tinyturing/tinyturing/font_mono.npy b/tinyturing/tinyturing/font_mono.npy deleted file mode 100644 index 65e515a4..00000000 Binary files a/tinyturing/tinyturing/font_mono.npy and /dev/null differ